From b7cba400c43153ac9640fc9da0304952d276c018 Mon Sep 17 00:00:00 2001 From: taoli4rs Date: Thu, 16 Jun 2022 19:12:16 -0700 Subject: [PATCH 001/453] WIP: Allow source node query in rr graph view. --- libs/librrgraph/src/base/rr_graph_storage.h | 19 ++++-- libs/librrgraph/src/base/rr_graph_view.h | 67 ++++++++++++--------- 2 files changed, 52 insertions(+), 34 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 63dc4c9b38d..d67f0d3ce32 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -63,13 +63,13 @@ struct alignas(16) t_rr_node_data { t_rr_type type_ = NUM_RR_TYPES; /* The character is a hex number which is a 4-bit truth table for node sides - * The 4-bits in serial represent 4 sides on which a node could appear - * It follows a fixed sequence, which is (LEFT, BOTTOM, RIGHT, TOP) whose indices are (3, 2, 1, 0) + * The 4-bits in serial represent 4 sides on which a node could appear + * It follows a fixed sequence, which is (LEFT, BOTTOM, RIGHT, TOP) whose indices are (3, 2, 1, 0) * - When a node appears on a given side, it is set to "1" * - When a node does not appear on a given side, it is set to "0" * For example, - * - '1' means '0001' in hex number, which means the node appears on TOP - * - 'A' means '1100' in hex number, which means the node appears on LEFT and BOTTOM sides, + * - '1' means '0001' in hex number, which means the node appears on TOP + * - 'A' means '1100' in hex number, which means the node appears on LEFT and BOTTOM sides, */ union { Direction direction; //Valid only for CHANX/CHANY @@ -252,6 +252,7 @@ class t_rr_graph_storage { * - num_non_configurable_edges(RRNodeId) * - edge_id(RRNodeId, t_edge_size) * - edge_sink_node(RRNodeId, t_edge_size) + * - edge_source_node(RRNodeId, t_edge_size) * - edge_switch(RRNodeId, t_edge_size) * * Only call these methods after partition_edges has been invoked. */ @@ -316,6 +317,11 @@ class t_rr_graph_storage { return edge_dest_node_[edge]; } + // Get the source node for the specified edge. + RRNodeId edge_source_node(const RREdgeId& edge) const { + return edge_src_node_[edge]; + } + // Call the `apply` function with the edge id, source, and sink nodes of every edge. void for_each_edge(std::function apply) const { for (size_t i = 0; i < edge_dest_node_.size(); i++) { @@ -332,6 +338,11 @@ class t_rr_graph_storage { return edge_sink_node(edge_id(id, iedge)); } + // Get the source node for the iedge'th edge from specified RRNodeId. + RRNodeId edge_source_node(const RRNodeId& id, t_edge_size iedge) const { + return edge_source_node(edge_id(id, iedge)); + } + // Get the switch used for the specified edge. short edge_switch(const RREdgeId& edge) const { return edge_switch_[edge]; diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 1c7e88260db..6d0c995864b 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -25,9 +25,9 @@ * - This avoids massive changes for each client on using the APIs * as each frame view provides adhoc APIs for each client * - * TODO: more compact frame views will be created, e.g., + * TODO: more compact frame views will be created, e.g., * - a mini frame view: contains only node and edges, representing the connectivity of the graph - * - a geometry frame view: an extended mini frame view with node-level attributes, + * - a geometry frame view: an extended mini frame view with node-level attributes, * in particular geometry information (type, x, y etc). * */ @@ -45,29 +45,29 @@ class RRGraphView { const vtr::vector& rr_switch_inf); /* Disable copy constructors and copy assignment operator - * This is to avoid accidental copy because it could be an expensive operation considering that the + * This is to avoid accidental copy because it could be an expensive operation considering that the * memory footprint of the data structure could ~ Gb - * Using the following syntax, we prohibit accidental 'pass-by-value' which can be immediately caught + * Using the following syntax, we prohibit accidental 'pass-by-value' which can be immediately caught * by compiler */ RRGraphView(const RRGraphView&) = delete; void operator=(const RRGraphView&) = delete; /* -- Accessors -- */ - /* TODO: The accessors may be turned into private later if they are replacable by 'questionin' + /* TODO: The accessors may be turned into private later if they are replacable by 'questionin' * kind of accessors */ public: /* Aggregates: create range-based loops for nodes - * To iterate over the nodes in a RRGraph, - * using a range-based loop is suggested. - * ----------------------------------------------------------------- - * Example: iterate over all the nodes - * // Strongly suggest to use a read-only rr_graph object - * const RRGraph& rr_graph; - * for (const RRNodeId& node : rr_graph.nodes()) { - * // Do something with each node - * } + * To iterate over the nodes in a RRGraph, + * using a range-based loop is suggested. + * ----------------------------------------------------------------- + * Example: iterate over all the nodes + * // Strongly suggest to use a read-only rr_graph object + * const RRGraph& rr_graph; + * for (const RRNodeId& node : rr_graph.nodes()) { + * // Do something with each node + * } */ inline vtr::StrongIdRange nodes() const { return vtr::StrongIdRange(RRNodeId(0), RRNodeId(num_nodes())); @@ -188,7 +188,7 @@ class RRGraphView { && (node_xhigh(node) == -1) && (node_yhigh(node) == -1)); } - /** @brief Check if two routing resource nodes are adjacent (must be a CHANX and a CHANY). + /** @brief Check if two routing resource nodes are adjacent (must be a CHANX and a CHANY). * This function is used for error checking; it checks if two nodes are physically adjacent (could be connected) based on their geometry. * It does not check the routing edges to see if they are, in fact, possible to connect in the current routing graph. * This function is inlined for runtime optimization. */ @@ -203,7 +203,7 @@ class RRGraphView { return true; } - /** @brief Check if node is within bounding box. + /** @brief Check if node is within bounding box. * To return true, the RRNode must be completely contained within the specified bounding box, with the edges of the bounding box being inclusive. *This function is inlined for runtime optimization. */ inline bool node_is_inside_bounding_box(RRNodeId node, vtr::Rect bounding_box) const { @@ -307,6 +307,13 @@ class RRGraphView { return node_storage_.edge_sink_node(id, iedge); } + /** @brief Get the source node for the iedge'th edge from specified RRNodeId. + * This method should generally not be used, and instead first_edge and + * last_edge should be used.*/ + inline RRNodeId edge_source_node(RRNodeId id, t_edge_size iedge) const { + return node_storage_.edge_source_node(id, iedge); + } + /** @brief Detect if the edge is a configurable edge (controlled by a programmable routing multipler or a tri-state switch). */ inline bool edge_is_configurable(RRNodeId id, t_edge_size iedge) const { return node_storage_.edge_is_configurable(id, iedge, rr_switch_inf_); @@ -322,16 +329,16 @@ class RRGraphView { return node_storage_.num_non_configurable_edges(node, rr_switch_inf_); } - /** @brief A configurable edge represents a programmable switch between routing resources, which could be + /** @brief A configurable edge represents a programmable switch between routing resources, which could be * a multiplexer * a tri-state buffer - * a pass gate + * a pass gate * This API gets ID range for configurable edges. This function is inlined for runtime optimization. */ inline edge_idx_range configurable_edges(RRNodeId node) const { return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(node_storage_.num_edges(node) - num_non_configurable_edges(node))); } - /** @brief A non-configurable edge represents a hard-wired connection between routing resources, which could be + /** @brief A non-configurable edge represents a hard-wired connection between routing resources, which could be * a non-configurable buffer that can not be turned off * a short metal connection that can not be turned off * This API gets ID range for non-configurable edges. This function is inlined for runtime optimization. */ @@ -357,26 +364,26 @@ class RRGraphView { return node_storage_.num_edges(node); } - /** @brief The ptc_num carries different meanings for different node types - * (true in VPR RRG that is currently supported, may not be true in customized RRG) - * CHANX or CHANY: the track id in routing channels - * OPIN or IPIN: the index of pins in the logic block data structure - * SOURCE and SINK: the class id of a pin (indicating logic equivalence of pins) in the logic block data structure - * @note - * This API is very powerful and developers should not use it unless it is necessary, - * e.g the node type is unknown. If the node type is known, the more specific routines, `node_pin_num()`, + /** @brief The ptc_num carries different meanings for different node types + * (true in VPR RRG that is currently supported, may not be true in customized RRG) + * CHANX or CHANY: the track id in routing channels + * OPIN or IPIN: the index of pins in the logic block data structure + * SOURCE and SINK: the class id of a pin (indicating logic equivalence of pins) in the logic block data structure + * @note + * This API is very powerful and developers should not use it unless it is necessary, + * e.g the node type is unknown. If the node type is known, the more specific routines, `node_pin_num()`, * `node_track_num()`and `node_class_num()`, for different types of nodes should be used.*/ inline short node_ptc_num(RRNodeId node) const { return node_storage_.node_ptc_num(node); } - /** @brief Get the pin num of a routing resource node. This is designed for logic blocks, + /** @brief Get the pin num of a routing resource node. This is designed for logic blocks, * which are IPIN and OPIN nodes. This function is inlined for runtime optimization. */ inline short node_pin_num(RRNodeId node) const { return node_storage_.node_pin_num(node); } - /** @brief Get the track num of a routing resource node. This is designed for routing tracks, + /** @brief Get the track num of a routing resource node. This is designed for routing tracks, * which are CHANX and CHANY nodes. This function is inlined for runtime optimization. */ inline short node_track_num(RRNodeId node) const { return node_storage_.node_track_num(node); @@ -498,7 +505,7 @@ class RRGraphView { /* rr_indexed_data_ and rr_segments_ are needed to lookup the segment information in node_coordinate_to_string() */ const vtr::vector& rr_indexed_data_; - /* RC data for nodes. This is a flyweight data */ + /* RC data for nodes. This is a flyweight data */ const std::vector& rr_rc_data_; /* Segment info for rr nodes */ From 4a05cade293995865aaf9a52dac061c76966538c Mon Sep 17 00:00:00 2001 From: taoli4rs Date: Mon, 25 Jul 2022 23:24:40 -0700 Subject: [PATCH 002/453] Add tileable rr graph support. --- libs/libarchfpga/src/physical_types.h | 18 +- libs/libvtrutil/src/vtr_geometry.h | 3 + .../tileable_rr_graph/chan_node_details.cpp | 299 ++++ vpr/src/tileable_rr_graph/chan_node_details.h | 77 + vpr/src/tileable_rr_graph/clb2clb_directs.h | 16 + vpr/src/tileable_rr_graph/openfpga_port.h | 96 ++ .../openfpga_rr_graph_utils.cpp | 184 +++ .../openfpga_rr_graph_utils.h | 46 + .../tileable_rr_graph/openfpga_side_manager.h | 49 + vpr/src/tileable_rr_graph/rr_chan.cpp | 225 +++ vpr/src/tileable_rr_graph/rr_chan.h | 94 ++ .../rr_graph_builder_utils.cpp | 556 +++++++ .../rr_graph_builder_utils.h | 98 ++ vpr/src/tileable_rr_graph/rr_graph_obj_util.h | 35 + vpr/src/tileable_rr_graph/rr_graph_types.h | 46 + vpr/src/tileable_rr_graph/rr_gsb.cpp | 1149 +++++++++++++ vpr/src/tileable_rr_graph/rr_gsb.h | 289 ++++ .../tileable_chan_details_builder.cpp | 234 +++ .../tileable_chan_details_builder.h | 32 + .../tileable_rr_graph_builder.cpp | 370 +++++ .../tileable_rr_graph_builder.h | 39 + .../tileable_rr_graph_edge_builder.cpp | 170 ++ .../tileable_rr_graph_edge_builder.h | 45 + .../tileable_rr_graph_gsb.cpp | 1447 +++++++++++++++++ .../tileable_rr_graph/tileable_rr_graph_gsb.h | 80 + .../tileable_rr_graph_node_builder.cpp | 1061 ++++++++++++ .../tileable_rr_graph_node_builder.h | 47 + 27 files changed, 6800 insertions(+), 5 deletions(-) create mode 100644 vpr/src/tileable_rr_graph/chan_node_details.cpp create mode 100644 vpr/src/tileable_rr_graph/chan_node_details.h create mode 100644 vpr/src/tileable_rr_graph/clb2clb_directs.h create mode 100644 vpr/src/tileable_rr_graph/openfpga_port.h create mode 100644 vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp create mode 100644 vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h create mode 100644 vpr/src/tileable_rr_graph/openfpga_side_manager.h create mode 100644 vpr/src/tileable_rr_graph/rr_chan.cpp create mode 100644 vpr/src/tileable_rr_graph/rr_chan.h create mode 100644 vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp create mode 100644 vpr/src/tileable_rr_graph/rr_graph_builder_utils.h create mode 100644 vpr/src/tileable_rr_graph/rr_graph_obj_util.h create mode 100644 vpr/src/tileable_rr_graph/rr_graph_types.h create mode 100644 vpr/src/tileable_rr_graph/rr_gsb.cpp create mode 100644 vpr/src/tileable_rr_graph/rr_gsb.h create mode 100644 vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp create mode 100644 vpr/src/tileable_rr_graph/tileable_chan_details_builder.h create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h create mode 100755 vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp create mode 100755 vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 3c0b1c760ac..b8cbd664f34 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -613,6 +613,8 @@ struct t_physical_tile_type { std::vector class_inf; /* [0..num_class-1] */ + int num_class = 0; + std::vector pin_width_offset; // [0..num_pins-1] std::vector pin_height_offset; // [0..num_pins-1] std::vector pin_class; // [0..num_pins-1] @@ -1397,7 +1399,7 @@ enum e_directionality { BI_DIRECTIONAL }; /* X_AXIS: Data that describes an x-directed wire segment (CHANX) * - * Y_AXIS: Data that describes an y-directed wire segment (CHANY) * + * Y_AXIS: Data that describes an y-directed wire segment (CHANY) * * BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */ enum e_parallel_axis { X_AXIS, @@ -1442,7 +1444,7 @@ enum e_Fc_type { * Cmetal: Capacitance of a routing track, per unit logic block length. * * Rmetal: Resistance of a routing track, per unit logic block length. * * (UDSD by AY) drivers: How do signals driving a routing track connect to * - * the track? + * the track? * seg_index: The index of the segment as stored in the appropriate Segs list* * Upon loading the architecture, we use this field to keep track * * the segment's index in the unified segment_inf vector. This is * @@ -1498,12 +1500,12 @@ constexpr std::array SWITCH_T /* Constant/Reserved names for switches in architecture XML * Delayless switch: - * The zero-delay switch created by VPR internally + * The zero-delay switch created by VPR internally * This is a special switch just to ease CAD algorithms * It is mainly used in - * - the edges between SOURCE and SINK nodes in routing resource graphs + * - the edges between SOURCE and SINK nodes in routing resource graphs * - the edges in CLB-to-CLB connections (defined by in arch XML) - * + * */ constexpr const char* VPR_DELAYLESS_SWITCH_NAME = "__vpr_delayless_switch__"; @@ -1798,12 +1800,18 @@ struct t_arch { char* architecture_id; //Secure hash digest of the architecture file to uniquely identify this architecture + /* Xifan Tang: options for tileable routing architectures */ + bool tileable; + bool through_channel; + t_chan_width_dist Chans; enum e_switch_block_type SBType; + enum e_switch_block_type SBSubType; std::vector switchblocks; float R_minW_nmos; float R_minW_pmos; int Fs; + int subFs; float grid_logic_tile_area; std::vector Segments; t_arch_switch_inf* Switches = nullptr; diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 3685c308653..1e11f87e1d7 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -61,6 +61,9 @@ bool operator!=(const RectUnion& lhs, const RectUnion& rhs); template class Point { public: //Constructors + // below is to create a no argument constructor for libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp + // need to figure out a better solution to avoid change this in libs from vtr + Point(); Point(T x_val, T y_val) noexcept; public: //Accessors diff --git a/vpr/src/tileable_rr_graph/chan_node_details.cpp b/vpr/src/tileable_rr_graph/chan_node_details.cpp new file mode 100644 index 00000000000..6f0f38e820c --- /dev/null +++ b/vpr/src/tileable_rr_graph/chan_node_details.cpp @@ -0,0 +1,299 @@ +/************************************************************************ + * This file contains member functions for class ChanNodeDetails + ***********************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" + +#include "chan_node_details.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Constructors + ***********************************************************************/ +ChanNodeDetails::ChanNodeDetails(const ChanNodeDetails& src) { + /* duplicate */ + size_t chan_width = src.get_chan_width(); + this->reserve(chan_width); + for (size_t itrack = 0; itrack < chan_width; ++itrack) { + track_node_ids_.push_back(src.get_track_node_id(itrack)); + track_direction_.push_back(src.get_track_direction(itrack)); + seg_ids_.push_back(src.get_track_segment_id(itrack)); + seg_length_.push_back(src.get_track_segment_length(itrack)); + track_start_.push_back(src.is_track_start(itrack)); + track_end_.push_back(src.is_track_end(itrack)); + } +} + +ChanNodeDetails::ChanNodeDetails() { + this->clear(); +} + +/************************************************************************ + * Accessors + ***********************************************************************/ +size_t ChanNodeDetails::get_chan_width() const { + VTR_ASSERT(validate_chan_width()); + return track_node_ids_.size(); +} + +size_t ChanNodeDetails::get_track_node_id(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_node_ids_[track_id]; +} + +/* Return a copy of vector */ +std::vector ChanNodeDetails::get_track_node_ids() const { + std::vector copy; + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + copy.push_back(track_node_ids_[inode]); + } + return copy; +} + +Direction ChanNodeDetails::get_track_direction(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_direction_[track_id]; +} + +size_t ChanNodeDetails::get_track_segment_length(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return seg_length_[track_id]; +} + +size_t ChanNodeDetails::get_track_segment_id(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return seg_ids_[track_id]; +} + +bool ChanNodeDetails::is_track_start(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_start_[track_id]; +} + +bool ChanNodeDetails::is_track_end(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_end_[track_id]; +} + +/* Track_id is the starting point of group (whose is_start should be true) + * This function will try to find the track_ids with the same directionality as track_id and seg_length + * A group size is the number of such nodes between the starting points (include the 1st starting point) + */ +std::vector ChanNodeDetails::get_seg_group(const size_t& track_id) const { + VTR_ASSERT(validate_chan_width()); + VTR_ASSERT(validate_track_id(track_id)); + VTR_ASSERT(is_track_start(track_id)); + + std::vector group; + /* Make sure a clean start */ + group.clear(); + + for (size_t itrack = track_id; itrack < get_chan_width(); ++itrack) { + if ( (get_track_direction(itrack) != get_track_direction(track_id) ) + || (get_track_segment_id(itrack) != get_track_segment_id(track_id)) ) { + /* Bypass any nodes in different direction and segment information*/ + continue; + } + if ( (false == is_track_start(itrack)) + || ( (true == is_track_start(itrack)) && (itrack == track_id)) ) { + group.push_back(itrack); + continue; + } + /* Stop if this another starting point */ + if (true == is_track_start(itrack)) { + break; + } + } + return group; +} + +/* Get a list of track_ids with the given list of track indices */ +std::vector ChanNodeDetails::get_seg_group_node_id(const std::vector& seg_group) const { + std::vector group; + /* Make sure a clean start */ + group.clear(); + + for (size_t id = 0; id < seg_group.size(); ++id) { + VTR_ASSERT(validate_track_id(seg_group[id])); + group.push_back(get_track_node_id(seg_group[id])); + } + + return group; +} + +/* Get the number of tracks that starts in this routing channel */ +size_t ChanNodeDetails::get_num_starting_tracks(const Direction& track_direction) const { + size_t counter = 0; + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass unmatched track_direction */ + if (track_direction != get_track_direction(itrack)) { + continue; + } + if (false == is_track_start(itrack)) { + continue; + } + counter++; + } + return counter; +} + +/* Get the number of tracks that ends in this routing channel */ +size_t ChanNodeDetails::get_num_ending_tracks(const Direction& track_direction) const { + size_t counter = 0; + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass unmatched track_direction */ + if (track_direction != get_track_direction(itrack)) { + continue; + } + if (false == is_track_end(itrack)) { + continue; + } + counter++; + } + return counter; +} + + +/************************************************************************ + * Mutators + ***********************************************************************/ +/* Reserve the capacitcy of vectors */ +void ChanNodeDetails::reserve(const size_t& chan_width) { + track_node_ids_.reserve(chan_width); + track_direction_.reserve(chan_width); + seg_length_.reserve(chan_width); + seg_ids_.reserve(chan_width); + track_start_.reserve(chan_width); + track_end_.reserve(chan_width); +} + +/* Add a track to the channel */ +void ChanNodeDetails::add_track(const size_t& track_node_id, const Direction& track_direction, + const size_t& seg_id, const size_t& seg_length, + const size_t& is_start, const size_t& is_end) { + track_node_ids_.push_back(track_node_id); + track_direction_.push_back(track_direction); + seg_ids_.push_back(seg_id); + seg_length_.push_back(seg_length); + track_start_.push_back(is_start); + track_end_.push_back(is_end); +} + +/* Update the node_id of a given track */ +void ChanNodeDetails::set_track_node_id(const size_t& track_index, const size_t& track_node_id) { + VTR_ASSERT(validate_track_id(track_index)); + track_node_ids_[track_index] = track_node_id; +} + +/* Update the node_ids from a vector */ +void ChanNodeDetails::set_track_node_ids(const std::vector& track_node_ids) { + /* the size of vector should match chan_width */ + VTR_ASSERT ( get_chan_width() == track_node_ids.size() ); + for (size_t inode = 0; inode < track_node_ids.size(); ++inode) { + track_node_ids_[inode] = track_node_ids[inode]; + } +} + +/* Set tracks with a given direction to start */ +void ChanNodeDetails::set_tracks_start(const Direction& track_direction) { + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Bypass non-match tracks */ + if (track_direction != get_track_direction(inode)) { + continue; /* Pass condition*/ + } + track_start_[inode] = true; + } +} + +/* Set tracks with a given direction to end */ +void ChanNodeDetails::set_tracks_end(const Direction& track_direction) { + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Bypass non-match tracks */ + if (track_direction != get_track_direction(inode)) { + continue; /* Pass condition*/ + } + track_end_[inode] = true; + } +} + +/* rotate the track_node_id by an offset */ +void ChanNodeDetails::rotate_track_node_id(const size_t& offset, const Direction& track_direction, const bool& counter_rotate) { + /* Direct return if offset = 0*/ + if (0 == offset) { + return; + } + + /* Rotate the node_ids by groups + * A group begins from a track_start and ends before another track_start + */ + VTR_ASSERT(validate_chan_width()); + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass non-start segment */ + if (false == is_track_start(itrack) ) { + continue; + } + /* Bypass segments do not match track_direction */ + if (track_direction != get_track_direction(itrack) ) { + continue; + } + /* Find the group nodes */ + std::vector track_group = get_seg_group(itrack); + /* Build a vector of the node ids of the tracks */ + std::vector track_group_node_id = get_seg_group_node_id(track_group); + /* adapt offset to the range of track_group_node_id */ + size_t actual_offset = offset % track_group_node_id.size(); + /* Rotate or Counter rotate */ + if (true == counter_rotate) { + std::rotate(track_group_node_id.rbegin(), track_group_node_id.rbegin() + actual_offset, track_group_node_id.rend()); + } else { + std::rotate(track_group_node_id.begin(), track_group_node_id.begin() + actual_offset, track_group_node_id.end()); + } + /* Update the node_ids */ + for (size_t inode = 0; inode < track_group.size(); ++inode) { + track_node_ids_[track_group[inode]] = track_group_node_id[inode]; + } + } + return; +} + +void ChanNodeDetails::clear() { + track_node_ids_.clear(); + track_direction_.clear(); + seg_ids_.clear(); + seg_length_.clear(); + track_start_.clear(); + track_end_.clear(); +} + +/************************************************************************ + * Validators + ***********************************************************************/ +bool ChanNodeDetails::validate_chan_width() const { + size_t chan_width = track_node_ids_.size(); + if ( (chan_width == track_direction_.size()) + &&(chan_width == seg_ids_.size()) + &&(chan_width == seg_length_.size()) + &&(chan_width == track_start_.size()) + &&(chan_width == track_end_.size()) ) { + return true; + } + return false; +} + +bool ChanNodeDetails::validate_track_id(const size_t& track_id) const { + if ( (track_id < track_node_ids_.size()) + && (track_id < track_direction_.size()) + && (track_id < seg_ids_.size()) + && (track_id < seg_length_.size()) + && (track_id < track_start_.size()) + && (track_id < track_end_.size()) ) { + return true; + } + return false; +} + +} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h new file mode 100644 index 00000000000..b2426ae56a1 --- /dev/null +++ b/vpr/src/tileable_rr_graph/chan_node_details.h @@ -0,0 +1,77 @@ +#ifndef CHAN_NODE_DETAILS_H +#define CHAN_NODE_DETAILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "vpr_types.h" +#include "rr_node_types.h" +#include "rr_graph_types.h" + +/************************************************************************ + * This file contains a class to model the details of routing node + * in a channel: + * 1. segment information: length, frequency etc. + * 2. starting point of segment + * 3. ending point of segment + * 4. potentail track_id(ptc_num) of each segment + ***********************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * ChanNodeDetails records segment length, directionality and starting of routing tracks + * +---------------------------------+ + * | Index | Direction | Start Point | + * +---------------------------------+ + * | 0 | --------> | Yes | + * +---------------------------------+ + ***********************************************************************/ + +class ChanNodeDetails { + public : /* Constructor */ + ChanNodeDetails(const ChanNodeDetails&); /* Duplication */ + ChanNodeDetails(); /* Initilization */ + public: /* Accessors */ + size_t get_chan_width() const; + size_t get_track_node_id(const size_t& track_id) const; + std::vector get_track_node_ids() const; + Direction get_track_direction(const size_t& track_id) const; + size_t get_track_segment_length(const size_t& track_id) const; + size_t get_track_segment_id(const size_t& track_id) const; + bool is_track_start(const size_t& track_id) const; + bool is_track_end(const size_t& track_id) const; + std::vector get_seg_group(const size_t& track_id) const; + std::vector get_seg_group_node_id(const std::vector& seg_group) const; + size_t get_num_starting_tracks(const Direction& track_direction) const; + size_t get_num_ending_tracks(const Direction& track_direction) const; + public: /* Mutators */ + void reserve(const size_t& chan_width); /* Reserve the capacitcy of vectors */ + void add_track(const size_t& track_node_id, const Direction& track_direction, + const size_t& seg_id, const size_t& seg_length, + const size_t& is_start, const size_t& is_end); + void set_track_node_id(const size_t& track_index, const size_t& track_node_id); + void set_track_node_ids(const std::vector& track_node_ids); + void set_tracks_start(const Direction& track_direction); + void set_tracks_end(const Direction& track_direction); + void rotate_track_node_id(const size_t& offset, + const Direction& track_direction, + const bool& counter_rotate); /* rotate the track_node_id by an offset */ + void clear(); + private: /* validators */ + bool validate_chan_width() const; + bool validate_track_id(const size_t& track_id) const; + private: /* Internal data */ + std::vector track_node_ids_; /* indices of each track */ + std::vector track_direction_; /* direction of each track */ + std::vector seg_ids_; /* id of segment of each track */ + std::vector seg_length_; /* Length of each segment */ + std::vector track_start_; /* flag to identify if this is the starting point of the track */ + std::vector track_end_; /* flag to identify if this is the ending point of the track */ +}; + +} /* end namespace openfpga */ + +#endif diff --git a/vpr/src/tileable_rr_graph/clb2clb_directs.h b/vpr/src/tileable_rr_graph/clb2clb_directs.h new file mode 100644 index 00000000000..7cc54bb8813 --- /dev/null +++ b/vpr/src/tileable_rr_graph/clb2clb_directs.h @@ -0,0 +1,16 @@ +#ifndef CLB2CLB_DIRECTS_H +#define CLB2CLB_DIRECTS_H + +#include "physical_types.h" + +struct t_clb_to_clb_directs { + t_physical_tile_type_ptr from_clb_type; + int from_clb_pin_start_index; + int from_clb_pin_end_index; + t_physical_tile_type_ptr to_clb_type; + int to_clb_pin_start_index; + int to_clb_pin_end_index; + int switch_index; //The switch type used by this direct connection +}; + +#endif diff --git a/vpr/src/tileable_rr_graph/openfpga_port.h b/vpr/src/tileable_rr_graph/openfpga_port.h new file mode 100644 index 00000000000..3df6d0efa40 --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_port.h @@ -0,0 +1,96 @@ +#ifndef OPENFPGA_PORT_H +#define OPENFPGA_PORT_H + +/******************************************************************** + * Include header files that are required by data structure declaration + *******************************************************************/ +#include +#include + +/* namespace openfpga begins */ +namespace openfpga { + +/* A basic port */ +class BasicPort { + public: /* Constructors */ + BasicPort(); + BasicPort(const char* name, const size_t& lsb, const size_t& msb); + BasicPort(const char* name, const size_t& width); + BasicPort(const std::string& name, const size_t& lsb, const size_t& msb); + BasicPort(const std::string& name, const size_t& width); + public: /* Overloaded operators */ + bool operator== (const BasicPort& portA) const; + bool operator< (const BasicPort& portA) const; + public: /* Accessors */ + size_t get_width() const; /* get the port width */ + size_t get_msb() const; /* get the LSB */ + size_t get_lsb() const; /* get the LSB */ + std::string get_name() const; /* get the name */ + bool is_valid() const; /* check if port size is valid > 0 */ + std::vector pins() const; /* Make a range of the pin indices */ + bool mergeable(const BasicPort& portA) const; /* Check if a port can be merged with this port */ + bool contained(const BasicPort& portA) const; /* Check if a port is contained by this port */ + size_t get_origin_port_width() const; + public: /* Mutators */ + void set(const BasicPort& basic_port); /* copy */ + void set_name(const std::string& name); /* set the port LSB and MSB */ + void set_width(const size_t& width); /* set the port LSB and MSB */ + void set_width(const size_t& lsb, const size_t& msb); /* set the port LSB and MSB */ + void set_lsb(const size_t& lsb); + void set_msb(const size_t& msb); + void expand(const size_t& width); /* Increase the port width */ + void revert(); /* Swap lsb and msb */ + bool rotate(const size_t& offset); /* rotate */ + bool counter_rotate(const size_t& offset); /* counter rotate */ + void reset(); /* Reset to initial port */ + void combine(const BasicPort& port); /* Combine two ports */ + void merge(const BasicPort& portA); + void set_origin_port_width(const size_t& origin_port_width); + private: /* internal functions */ + void make_invalid(); /* Make a port invalid */ + private: /* Internal Data */ + std::string name_; /* Name of this port */ + size_t msb_; /* Most Significant Bit of this port */ + size_t lsb_; /* Least Significant Bit of this port */ + size_t origin_port_width_; /* Original port width of a port, used by traceback port conversion history */ +}; + +/* Configuration ports: + * 1. reserved configuration port, which is used by RRAM FPGA architecture + * 2. regular configuration port, which is used by any FPGA architecture + */ +class ConfPorts { + public: /* Constructors */ + ConfPorts(); /* default port */ + ConfPorts(const ConfPorts& conf_ports); /* copy */ + public: /* Accessors */ + size_t get_reserved_port_width() const; + size_t get_reserved_port_lsb() const; + size_t get_reserved_port_msb() const; + size_t get_regular_port_width() const; + size_t get_regular_port_lsb() const; + size_t get_regular_port_msb() const; + public: /* Mutators */ + void set(const ConfPorts& conf_ports); + void set_reserved_port(size_t width); + void set_regular_port(size_t width); + void set_regular_port(size_t lsb, size_t msb); + void set_regular_port_lsb(size_t lsb); + void set_regular_port_msb(size_t msb); + void expand_reserved_port(size_t width); /* Increase the port width of reserved port */ + void expand_regular_port(size_t width); /* Increase the port width of regular port */ + void expand(size_t width); /* Increase the port width of both ports */ + bool rotate_regular_port(size_t offset); /* rotate */ + bool counter_rotate_regular_port(size_t offset); /* counter rotate */ + void reset(); /* Reset to initial port */ + private: /* Internal Data */ + BasicPort reserved_; + BasicPort regular_; +}; + +/* TODO: create a class for BL and WL ports */ + +} /* namespace openfpga ends */ + +#endif + diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp new file mode 100644 index 00000000000..60a8698f8e7 --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -0,0 +1,184 @@ +/******************************************************************** + * This file includes most utilized functions for the rr_graph + * data structure in the OpenFPGA context + *******************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "openfpga_rr_graph_utils.h" +#include "rr_graph_types.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Get the coordinator of a starting point of a routing track + * For routing tracks in INC_DIRECTION + * (xlow, ylow) should be the starting point + * + * For routing tracks in DEC_DIRECTION + * (xhigh, yhigh) should be the starting point + ***********************************************************************/ +vtr::Point get_track_rr_node_start_coordinate(const RRGraph& rr_graph, + const RRNodeId& track_rr_node) { + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node)) ); + + vtr::Point start_coordinator; + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + start_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + start_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node)); + } + + return start_coordinator; +} + +/************************************************************************ + * Get the coordinator of a end point of a routing track + * For routing tracks in INC_DIRECTION + * (xhigh, yhigh) should be the starting point + * + * For routing tracks in DEC_DIRECTION + * (xlow, ylow) should be the starting point + ***********************************************************************/ +vtr::Point get_track_rr_node_end_coordinate(const RRGraph& rr_graph, + const RRNodeId& track_rr_node) { + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node)) ); + + vtr::Point end_coordinator; + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + end_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node)); + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + end_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + } + + return end_coordinator; +} + +/************************************************************************ + * Find the driver switches for a node in the rr_graph + * This function only return unique driver switches + ***********************************************************************/ +std::vector get_rr_graph_driver_switches(const RRGraph& rr_graph, + const RRNodeId& node) { + std::vector driver_switches; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) { + driver_switches.push_back(rr_graph.edge_switch(edge)); + } + } + + return driver_switches; +} + +/************************************************************************ + * Find the driver nodes for a node in the rr_graph + ***********************************************************************/ +std::vector get_rr_graph_driver_nodes(const RRGraph& rr_graph, + const RRNodeId& node) { + std::vector driver_nodes; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } + + return driver_nodes; +} + +/************************************************************************ + * Find the configurable driver nodes for a node in the rr_graph + ***********************************************************************/ +std::vector get_rr_graph_configurable_driver_nodes(const RRGraph& rr_graph, + const RRNodeId& node) { + std::vector driver_nodes; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + /* Bypass non-configurable edges */ + if (false == rr_graph.edge_is_configurable(edge)) { + continue; + } + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } + + return driver_nodes; +} + +/************************************************************************ + * Find the configurable driver nodes for a node in the rr_graph + ***********************************************************************/ +std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraph& rr_graph, + const RRNodeId& node) { + std::vector driver_nodes; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + /* Bypass configurable edges */ + if (true == rr_graph.edge_is_configurable(edge)) { + continue; + } + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } + + return driver_nodes; +} + +/************************************************************************ + * Check if an OPIN of a rr_graph is directly driving an IPIN + * To meet this requirement, the OPIN must: + * - Have only 1 fan-out + * - The only fan-out is an IPIN + ***********************************************************************/ +bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, + const RRNodeId& node) { + /* We only accept OPIN */ + VTR_ASSERT(OPIN == rr_graph.node_type(node)); + + if (1 != rr_graph.node_out_edges(node).size()) { + return false; + } + + VTR_ASSERT(1 == rr_graph.node_out_edges(node).size()); + for (const RREdgeId& edge: rr_graph.node_out_edges(node)) { + const RRNodeId& sink_node = rr_graph.edge_sink_node(edge); + if (IPIN != rr_graph.node_type(sink_node)) { + return false; + } + } + + return true; +} + +/************************************************************************ + * Check if an IPIN of a rr_graph is directly connected to an OPIN + * To meet this requirement, the IPIN must: + * - Have only 1 fan-in + * - The only fan-in is an OPIN + ***********************************************************************/ +bool is_ipin_direct_connected_opin(const RRGraph& rr_graph, + const RRNodeId& node) { + /* We only accept IPIN */ + VTR_ASSERT(IPIN == rr_graph.node_type(node)); + + if (1 != rr_graph.node_in_edges(node).size()) { + return false; + } + + VTR_ASSERT(1 == rr_graph.node_in_edges(node).size()); + for (const RREdgeId& edge: rr_graph.node_in_edges(node)) { + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + if (OPIN != rr_graph.node_type(src_node)) { + return false; + } + } + + return true; +} + +} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h new file mode 100644 index 00000000000..ebf741f8d97 --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h @@ -0,0 +1,46 @@ +#ifndef OPENFPGA_RR_GRAPH_UTILS_H +#define OPENFPGA_RR_GRAPH_UTILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_geometry.h" + +/* Headers from vpr library */ +#include "rr_graph_obj.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +vtr::Point get_track_rr_node_start_coordinate(const RRGraph& rr_graph, + const RRNodeId& track_rr_node); + +vtr::Point get_track_rr_node_end_coordinate(const RRGraph& rr_graph, + const RRNodeId& track_rr_node); + +std::vector get_rr_graph_driver_switches(const RRGraph& rr_graph, + const RRNodeId& node); + +std::vector get_rr_graph_driver_nodes(const RRGraph& rr_graph, + const RRNodeId& node); + +std::vector get_rr_graph_configurable_driver_nodes(const RRGraph& rr_graph, + const RRNodeId& node); + +std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraph& rr_graph, + const RRNodeId& node); + +bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, + const RRNodeId& node); + +bool is_ipin_direct_connected_opin(const RRGraph& rr_graph, + const RRNodeId& node); + +} /* end namespace openfpga */ + +#endif diff --git a/vpr/src/tileable_rr_graph/openfpga_side_manager.h b/vpr/src/tileable_rr_graph/openfpga_side_manager.h new file mode 100644 index 00000000000..4903f7b4bba --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_side_manager.h @@ -0,0 +1,49 @@ +#ifndef OPENFPGA_SIDE_MANAGER_H +#define OPENFPGA_SIDE_MANAGER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include + +/* Header files form archfpga library */ +#include "physical_types.h" + +/* namespace openfpga begins */ +namespace openfpga { + +/******************************************************************** + * Define a class for the sides of a physical block in FPGA architecture + * Basically, each block has four sides : + * TOP, RIGHT, BOTTOM, LEFT + * This class aims to provide a easy proctol for manipulating a side + ********************************************************************/ + +class SideManager { + public: /* Constructor */ + SideManager(enum e_side side); + SideManager(); + SideManager(size_t side); + public: /* Accessors */ + enum e_side get_side() const; + enum e_side get_opposite() const; + enum e_side get_rotate_clockwise() const; + enum e_side get_rotate_counterclockwise() const; + bool validate() const; + size_t to_size_t() const; + const char* c_str() const; + std::string to_string() const; + public: /* Mutators */ + void set_side(size_t side); + void set_side(enum e_side side); + void set_opposite(); + void rotate_clockwise(); + void rotate_counterclockwise(); + private: /* internal data */ + enum e_side side_; +}; + +} /* namespace openfpga ends */ + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp new file mode 100644 index 00000000000..0aea3cee48a --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_chan.cpp @@ -0,0 +1,225 @@ +/************************************************************************ + * Member functions for class RRChan + ***********************************************************************/ +#include "vtr_log.h" +#include "vtr_assert.h" +#include "rr_chan.h" + +/* namespace openfpga begins */ +namespace openfpga { + +/************************************************************************ + * Constructors + ***********************************************************************/ +/* default constructor */ +RRChan::RRChan() { + type_ = NUM_RR_TYPES; + nodes_.resize(0); + node_segments_.resize(0); +} + +/************************************************************************ + * Accessors + ***********************************************************************/ +t_rr_type RRChan::get_type() const { + return type_; +} + +/* get the number of tracks in this channel */ +size_t RRChan::get_chan_width() const { + return nodes_.size(); +} + +/* get the track_id of a node */ +int RRChan::get_node_track_id(const RRNodeId& node) const { + /* if the given node is NULL, we return an invalid id */ + if (RRNodeId::INVALID() == node) { + return -1; + } + /* check each member and return if we find a match in content */ + std::vector::const_iterator it = std::find(nodes_.begin(), nodes_.end(), node); + if (nodes_.end() == it) { + return -1; + } + return it - nodes_.begin(); +} + +/* get the rr_node with the track_id */ +RRNodeId RRChan::get_node(const size_t& track_num) const { + if ( false == valid_node_id(track_num) ) { + return RRNodeId::INVALID(); + } + return nodes_[track_num]; +} + +/* get the segment id of a node */ +RRSegmentId RRChan::get_node_segment(const RRNodeId& node) const { + int node_id = get_node_track_id(node); + if ( false == valid_node_id(node_id)) { + return RRSegmentId::INVALID(); + } + return get_node_segment(node_id); +} + +/* get the segment id of a node */ +RRSegmentId RRChan::get_node_segment(const size_t& track_num) const { + if ( false == valid_node_id(track_num)) { + return RRSegmentId::INVALID(); + } + return node_segments_[track_num]; +} + +/* evaluate if two RRChan is mirror to each other */ +bool RRChan::is_mirror(const RRGraph& rr_graph, const RRChan& cand) const { + /* If any following element does not match, it is not mirror */ + /* 1. type */ + if (this->get_type() != cand.get_type()) { + return false; + } + /* 2. track_width */ + if (this->get_chan_width() != cand.get_chan_width()) { + return false; + } + /* 3. for each node */ + for (size_t inode = 0; inode < this->get_chan_width(); ++inode) { + /* 3.1 check node type */ + if (rr_graph.node_type(this->get_node(inode)) != rr_graph.node_type(cand.get_node(inode))) { + return false; + } + /* 3.2 check node directionality */ + if (rr_graph.node_direction(this->get_node(inode)) != rr_graph.node_direction(cand.get_node(inode))) { + return false; + } + /* 3.3 check node segment */ + if (this->get_node_segment(inode) != cand.get_node_segment(inode)) { + return false; + } + } + + return true; +} + +/* Get a list of segments used in this routing channel */ +std::vector RRChan::get_segment_ids() const { + std::vector seg_list; + + /* make sure a clean start */ + seg_list.clear(); + + /* Traverse node_segments */ + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + std::vector::iterator it; + /* Try to find the node_segment id in the list */ + it = find(seg_list.begin(), seg_list.end(), node_segments_[inode]); + if ( it == seg_list.end() ) { + /* Not found, add it to the list */ + seg_list.push_back(node_segments_[inode]); + } + } + + return seg_list; +} + +/* Get a list of nodes whose segment_id is specified */ +std::vector RRChan::get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const { + std::vector node_list; + + /* make sure a clean start */ + node_list.clear(); + + /* Traverse node_segments */ + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Try to find the node_segment id in the list */ + if ( seg_id == node_segments_[inode] ) { + node_list.push_back(inode); + } + } + + return node_list; +} + +/************************************************************************ + * Mutators + ***********************************************************************/ +void RRChan::set(const RRChan& rr_chan) { + /* Ensure a clean start */ + this->clear(); + /* Assign type of this routing channel */ + this->type_ = rr_chan.get_type(); + /* Copy node and node_segments */ + this->nodes_.resize(rr_chan.get_chan_width()); + this->node_segments_.resize(rr_chan.get_chan_width()); + for (size_t inode = 0; inode < rr_chan.get_chan_width(); ++inode) { + this->nodes_[inode] = rr_chan.get_node(inode); + this->node_segments_[inode] = rr_chan.get_node_segment(inode); + } + return; +} + +/* modify type */ +void RRChan::set_type(const t_rr_type& type) { + VTR_ASSERT(valid_type(type)); + type_ = type; +} + +/* Reserve node list */ +void RRChan::reserve_node(const size_t& node_size) { + nodes_.reserve(node_size); /* reserve to the maximum */ + node_segments_.reserve(node_size); /* reserve to the maximum */ +} + +/* add a node to the array */ +void RRChan::add_node(const RRGraph& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment) { + /* fill the dedicated element in the vector */ + nodes_.push_back(node); + node_segments_.push_back(node_segment); + + if (NUM_RR_TYPES == type_) { + type_ = rr_graph.node_type(node); + } else { + VTR_ASSERT(type_ == rr_graph.node_type(node)); + } + + VTR_ASSERT(valid_node_type(rr_graph, node)); +} + +/* Clear content */ +void RRChan::clear() { + nodes_.clear(); + node_segments_.clear(); +} + +/************************************************************************ + * Internal validators + ***********************************************************************/ +/* for type, only valid type is CHANX and CHANY */ +bool RRChan::valid_type(const t_rr_type& type) const { + if ((CHANX == type) || (CHANY == type)) { + return true; + } + return false; +} + +/* Check each node, see if the node type is consistent with the type */ +bool RRChan::valid_node_type(const RRGraph& rr_graph, const RRNodeId& node) const { + valid_type(rr_graph.node_type(node)); + if (NUM_RR_TYPES == type_) { + return true; + } + valid_type(type_); + if (type_ != rr_graph.node_type(node)) { + return false; + } + return true; +} + +/* check if the node id is valid */ +bool RRChan::valid_node_id(const size_t& node_id) const { + if (node_id < nodes_.size()) { + return true; + } + + return false; +} + +} /* End namespace openfpga*/ diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h new file mode 100644 index 00000000000..d06d894caa8 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -0,0 +1,94 @@ +#ifndef RR_CHAN_H +#define RR_CHAN_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_geometry.h" + +/* Headers from openfpgautil library */ +#include "openfpga_port.h" + +/* Headers from vpr library */ +#include "rr_graph_obj.h" + +/* Begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * RRChan object aim to describe a routing channel in a routing resource graph + * - What are the nodes in the RRGraph object, for each routing track + * - What are routing segments used by each node in the channel + * - What are the directions of each routing channel + * being either X-direction or Y-direction + * + * Note : + * - This is a collection of rr_nodes from the RRGraph Object + * It does not rebuild or contruct any connects between rr_nodes + * It is just an annotation on an existing RRGraph + * ------------- ------ + * | | | | + * | | | Y | + * | CLB | | Chan | + * | | | | + * | | | | + * ------------- ------ + * ------------- + * | X | + * | Channel | + * ------------- + *******************************************************************/ +class RRChan { + public: /* Constructors */ + RRChan(); + public: /* Accessors */ + t_rr_type get_type() const; + size_t get_chan_width() const; /* get the number of tracks in this channel */ + int get_node_track_id(const RRNodeId& node) const; /* get the track_id of a node */ + RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */ + RRSegmentId get_node_segment(const RRNodeId& node) const; + RRSegmentId get_node_segment(const size_t& track_num) const; + bool is_mirror(const RRGraph& rr_graph, const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */ + std::vector get_segment_ids() const; /* Get a list of segments used in this routing channel */ + std::vector get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const; /* Get a list of segments used in this routing channel */ + public: /* Mutators */ + /* copy */ + void set(const RRChan&); + + /* modify the type of routing channel */ + void set_type(const t_rr_type& type); + + /* reseve a number of nodes to the array */ + void reserve_node(const size_t& node_size); + + /* add a node to the routing channel */ + void add_node(const RRGraph& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment); + + /* clear the content */ + void clear(); + + private: /* internal functions */ + + /* For the type of a routing channel, only valid type is CHANX and CHANY */ + bool valid_type(const t_rr_type& type) const; + + /* Check each node, see if the node type is consistent with the type of routing channel */ + bool valid_node_type(const RRGraph& rr_graph, const RRNodeId& node) const; + + /* Validate if the track number in the range */ + bool valid_node_id(const size_t& node_id) const; + + private: /* Internal Data */ + t_rr_type type_; /* channel type: CHANX or CHANY */ + std::vector nodes_; /* rr nodes of each track in the channel */ + std::vector node_segments_; /* segment of each track */ +}; + + + +} /* End namespace openfpga*/ + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp new file mode 100644 index 00000000000..3aaba3e1ac2 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -0,0 +1,556 @@ +/************************************************************************ + * This file contains most utilized functions for rr_graph builders + ***********************************************************************/ +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "vpr_utils.h" + +#include "rr_graph_builder_utils.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Correct number of routing channel width to be compatible to + * uni-directional routing architecture + ***********************************************************************/ +size_t find_unidir_routing_channel_width(const size_t& chan_width) { + size_t actual_chan_width = chan_width; + /* Correct the chan_width: it should be an even number */ + if (0 != actual_chan_width % 2) { + actual_chan_width++; /* increment it to be even */ + } + VTR_ASSERT(0 == actual_chan_width % 2); + + return actual_chan_width; +} + +/************************************************************************ + * Get the class index of a grid pin + ***********************************************************************/ +int get_grid_pin_class_index(const t_grid_tile& cur_grid, + const int pin_index) { + /* check */ + VTR_ASSERT(pin_index < cur_grid.type->num_pins); + return cur_grid.type->pin_class[pin_index]; +} + +/* Deteremine the side of a io grid */ +e_side determine_io_grid_pin_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate) { + /* TOP side IO of FPGA */ + if (device_size.y() == grid_coordinate.y()) { + return BOTTOM; /* Such I/O has only Bottom side pins */ + } else if (device_size.x() == grid_coordinate.x()) { /* RIGHT side IO of FPGA */ + return LEFT; /* Such I/O has only Left side pins */ + } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ + return TOP; /* Such I/O has only Top side pins */ + } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ + return RIGHT; /* Such I/O has only Right side pins */ + } else if ((grid_coordinate.x() < device_size.x()) && (grid_coordinate.y() < device_size.y())) { + /* I/O grid in the center grid */ + return NUM_SIDES; + } + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n", + grid_coordinate.x(), grid_coordinate.y(), + device_size.x(), device_size.y()); + exit(1); +} + +/* Deteremine the side of a pin of a grid */ +std::vector find_grid_pin_sides(const t_grid_tile& grid, + const size_t& pin_id) { + std::vector pin_sides; + + for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT} ) { + if (true == grid.type->pinloc[grid.width_offset][grid.height_offset][size_t(side)][pin_id]) { + pin_sides.push_back(side); + } + } + + return pin_sides; +} + +/************************************************************************ + * Get a list of pin_index for a grid (either OPIN or IPIN) + * For IO_TYPE, only one side will be used, we consider one side of pins + * For others, we consider all the sides + ***********************************************************************/ +std::vector get_grid_side_pins(const t_grid_tile& cur_grid, + const e_pin_type& pin_type, + const e_side& pin_side, + const int& pin_width, + const int& pin_height) { + std::vector pin_list; + /* Make sure a clear start */ + pin_list.clear(); + + for (int ipin = 0; ipin < cur_grid.type->num_pins; ++ipin) { + int class_id = cur_grid.type->pin_class[ipin]; + if ( (1 == cur_grid.type->pinloc[pin_width][pin_height][pin_side][ipin]) + && (pin_type == cur_grid.type->class_inf[class_id].type) ) { + pin_list.push_back(ipin); + } + } + return pin_list; +} + +/************************************************************************ + * Get the number of pins for a grid (either OPIN or IPIN) + * For IO_TYPE, only one side will be used, we consider one side of pins + * For others, we consider all the sides + ***********************************************************************/ +size_t get_grid_num_pins(const t_grid_tile& cur_grid, + const e_pin_type& pin_type, + const e_side& io_side) { + size_t num_pins = 0; + + /* For IO_TYPE sides */ + for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { + /* skip unwanted sides */ + if ( (true == is_io_type(cur_grid.type)) + && (side != io_side) && (NUM_SIDES != io_side)) { + continue; + } + /* Get pin list */ + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + std::vector pin_list = get_grid_side_pins(cur_grid, pin_type, side, width, height); + num_pins += pin_list.size(); + } + } + } + + return num_pins; +} + +/************************************************************************ + * Get the number of pins for a grid (either OPIN or IPIN) + * For IO_TYPE, only one side will be used, we consider one side of pins + * For others, we consider all the sides + ***********************************************************************/ +size_t get_grid_num_classes(const t_grid_tile& cur_grid, + const e_pin_type& pin_type) { + size_t num_classes = 0; + + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Bypass unmatched pin_type */ + if (pin_type != cur_grid.type->class_inf[iclass].type) { + continue; + } + num_classes++; + } + + return num_classes; +} + +/************************************************************************ + * Idenfity if a X-direction routing channel exist in the fabric + * This could be entirely possible that a routig channel + * is in the middle of a multi-width and multi-height grid + * + * As the chanx always locates on top of a grid with the same coord + * + * +----------+ + * | CHANX | + * | [x][y] | + * +----------+ + * + * +----------+ + * | Grid | height_offset = height - 1 + * | [x][y] | + * +----------+ + * + * +----------+ + * | Grid | height_offset = height - 2 + * | [x][y-1] | + * +----------+ + * If the CHANX is in the middle of a multi-width and multi-height grid + * it should locate at a grid whose height_offset is lower than the its height defined in physical_tile + * When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block + ***********************************************************************/ +bool is_chanx_exist(const DeviceGrid& grids, + const vtr::Point& chanx_coord, + const bool& through_channel) { + + if ((1 > chanx_coord.x()) || (chanx_coord.x() > grids.width() - 2)) { + return false; + } + + if (chanx_coord.y() > grids.height() - 2) { + return false; + } + + if (true == through_channel) { + return true; + } + + return (grids[chanx_coord.x()][chanx_coord.y()].height_offset == grids[chanx_coord.x()][chanx_coord.y()].type->height - 1); +} + +/************************************************************************ + * Idenfity if a Y-direction routing channel exist in the fabric + * This could be entirely possible that a routig channel + * is in the middle of a multi-width and multi-height grid + * + * As the chany always locates on right of a grid with the same coord + * + * +-----------+ +---------+ +--------+ + * | Grid | | Grid | | CHANY | + * | [x-1][y] | | [x][y] | | [x][y] | + * +-----------+ +---------+ +--------+ + * width_offset width_offset + * = width - 2 = width -1 + * If the CHANY is in the middle of a multi-width and multi-height grid + * it should locate at a grid whose width_offset is lower than the its width defined in physical_tile + * When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block + * + * If through channel is allowed, the chany will always exists + * unless it falls out of the grid array + ***********************************************************************/ +bool is_chany_exist(const DeviceGrid& grids, + const vtr::Point& chany_coord, + const bool& through_channel) { + + if (chany_coord.x() > grids.width() - 2) { + return false; + } + + if ((1 > chany_coord.y()) || (chany_coord.y() > grids.height() - 2)) { + return false; + } + + if (true == through_channel) { + return true; + } + + return (grids[chany_coord.x()][chany_coord.y()].width_offset == grids[chany_coord.x()][chany_coord.y()].type->width - 1); +} + +/************************************************************************ + * Identify if a X-direction routing channel is at the right side of a + * multi-height grid + * + * +-----------------+ + * | | + * | | +-------------+ + * | Grid | | CHANX | + * | [x-1][y] | | [x][y] | + * | | +-------------+ + * | | + * +-----------------+ + ***********************************************************************/ +bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, + const vtr::Point& chanx_coord, + const bool& through_channel) { + VTR_ASSERT(0 < chanx_coord.x()); + if (1 == chanx_coord.x()) { + /* This is already the LEFT side of FPGA fabric, + * it is the same results as chanx is right to a multi-height grid + */ + return true; + } + + if (false == through_channel) { + /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ + vtr::Point left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y()); + if (false == is_chanx_exist(grids, left_chanx_coord)) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Identify if a X-direction routing channel is at the left side of a + * multi-height grid + * + * +-----------------+ + * | | + * +---------------+ | | + * | CHANX | | Grid | + * | [x][y] | | [x+1][y] | + * +---------------+ | | + * | | + * +-----------------+ + ***********************************************************************/ +bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, + const vtr::Point& chanx_coord, + const bool& through_channel) { + VTR_ASSERT(chanx_coord.x() < grids.width() - 1); + if (grids.width() - 2 == chanx_coord.x()) { + /* This is already the RIGHT side of FPGA fabric, + * it is the same results as chanx is right to a multi-height grid + */ + return true; + } + + + if (false == through_channel) { + /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ + vtr::Point right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y()); + if (false == is_chanx_exist(grids, right_chanx_coord)) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Identify if a Y-direction routing channel is at the top side of a + * multi-width grid + * + * +--------+ + * | CHANY | + * | [x][y] | + * +--------+ + * + * +-----------------+ + * | | + * | | + * | Grid | + * | [x-1][y] | + * | | + * | | + * +-----------------+ + ***********************************************************************/ +bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, + const vtr::Point& chany_coord, + const bool& through_channel) { + VTR_ASSERT(0 < chany_coord.y()); + if (1 == chany_coord.y()) { + /* This is already the BOTTOM side of FPGA fabric, + * it is the same results as chany is at the top of a multi-width grid + */ + return true; + } + + if (false == through_channel) { + /* We check the bottom neighbor of chany, if it does not exist, the chany is top to a multi-height grid */ + vtr::Point bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1); + if (false == is_chany_exist(grids, bottom_chany_coord)) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Identify if a Y-direction routing channel is at the bottom side of a + * multi-width grid + * + * +-----------------+ + * | | + * | | + * | Grid | + * | [x][y+1] | + * | | + * | | + * +-----------------+ + * +--------+ + * | CHANY | + * | [x][y] | + * +--------+ + * + ***********************************************************************/ +bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, + const vtr::Point& chany_coord, + const bool& through_channel) { + VTR_ASSERT(chany_coord.y() < grids.height() - 1); + if (grids.height() - 2 == chany_coord.y()) { + /* This is already the TOP side of FPGA fabric, + * it is the same results as chany is at the bottom of a multi-width grid + */ + return true; + } + + if (false == through_channel) { + /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */ + vtr::Point top_chany_coord(chany_coord.x(), chany_coord.y() + 1); + if (false == is_chany_exist(grids, top_chany_coord)) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Get the track_id of a routing track w.r.t its coordinator + * In tileable routing architecture, the track_id changes SB by SB. + * Therefore the track_ids are stored in a vector, indexed by the relative coordinator + * based on the starting point of the track + * For routing tracks in INC_DIRECTION + * (xlow, ylow) should be the starting point + * + * (xlow, ylow) (xhigh, yhigh) + * track_id[0] -------------------------------> track_id[xhigh - xlow + yhigh - ylow] + * + * For routing tracks in DEC_DIRECTION + * (xhigh, yhigh) should be the starting point + * + * (xlow, ylow) (xhigh, yhigh) + * track_id[0] <------------------------------- track_id[xhigh - xlow + yhigh - ylow] + * + * + ***********************************************************************/ +short get_rr_node_actual_track_id(const RRGraph& rr_graph, + const RRNodeId& track_rr_node, + const vtr::Point& coord, + const vtr::vector>& tileable_rr_graph_node_track_ids) { + vtr::Point low_coord(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + size_t offset = (int)abs((int)coord.x() - (int)low_coord.x() + (int)coord.y() - (int)low_coord.y()); + return tileable_rr_graph_node_track_ids[track_rr_node][offset]; +} + +/************************************************************************ + * Get the ptc of a routing track in the channel where it ends + * For routing tracks in INC_DIRECTION + * the ptc is the last of track_ids + * + * For routing tracks in DEC_DIRECTION + * the ptc is the first of track_ids + ***********************************************************************/ +short get_track_rr_node_end_track_id(const RRGraph& rr_graph, + const RRNodeId& track_rr_node, + const vtr::vector>& tileable_rr_graph_node_track_ids) { + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node)) ); + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + return tileable_rr_graph_node_track_ids[track_rr_node].back(); + } + + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + return tileable_rr_graph_node_track_ids[track_rr_node].front(); +} + +/************************************************************************ + * Find the number of nodes in the same class + * in a routing resource graph + ************************************************************************/ +short find_rr_graph_num_nodes(const RRGraph& rr_graph, + const std::vector& node_types) { + short counter = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + counter++; + } + + return counter; +} + +/************************************************************************ + * Find the maximum fan-in for a given class of nodes + * in a routing resource graph + ************************************************************************/ +short find_rr_graph_max_fan_in(const RRGraph& rr_graph, + const std::vector& node_types) { + short max_fan_in = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + max_fan_in = std::max(rr_graph.node_fan_in(node), max_fan_in); + } + + return max_fan_in; +} + +/************************************************************************ + * Find the minimum fan-in for a given class of nodes + * in a routing resource graph + ************************************************************************/ +short find_rr_graph_min_fan_in(const RRGraph& rr_graph, + const std::vector& node_types) { + short min_fan_in = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + min_fan_in = std::min(rr_graph.node_fan_in(node), min_fan_in); + } + + + return min_fan_in; +} + +/************************************************************************ + * Find the average fan-in for a given class of nodes + * in a routing resource graph + ************************************************************************/ +short find_rr_graph_average_fan_in(const RRGraph& rr_graph, + const std::vector& node_types) { + /* Get the maximum SB mux size */ + size_t sum = 0; + size_t counter = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + + sum += rr_graph.node_fan_in(node); + counter++; + } + + return sum / counter; +} + +/************************************************************************ + * Print statistics of multiplexers in a routing resource graph + ************************************************************************/ +void print_rr_graph_mux_stats(const RRGraph& rr_graph) { + + /* Print MUX size distribution */ + std::vector sb_node_types; + sb_node_types.push_back(CHANX); + sb_node_types.push_back(CHANY); + + /* Print statistics */ + VTR_LOG("------------------------------------------------\n"); + VTR_LOG("Total No. of Switch Block multiplexer size: %d\n", + find_rr_graph_num_nodes(rr_graph, sb_node_types)); + VTR_LOG("Maximum Switch Block multiplexer size: %d\n", + find_rr_graph_max_fan_in(rr_graph, sb_node_types)); + VTR_LOG("Minimum Switch Block multiplexer size: %d\n", + find_rr_graph_min_fan_in(rr_graph, sb_node_types)); + VTR_LOG("Average Switch Block multiplexer size: %lu\n", + find_rr_graph_average_fan_in(rr_graph, sb_node_types)); + VTR_LOG("------------------------------------------------\n"); + + /* Get the maximum CB mux size */ + std::vector cb_node_types(1, IPIN); + + VTR_LOG("------------------------------------------------\n"); + VTR_LOG("Total No. of Connection Block Multiplexer size: %d\n", + find_rr_graph_num_nodes(rr_graph, cb_node_types)); + VTR_LOG("Maximum Connection Block Multiplexer size: %d\n", + find_rr_graph_max_fan_in(rr_graph, cb_node_types)); + VTR_LOG("Minimum Connection Block Multiplexer size: %d\n", + find_rr_graph_min_fan_in(rr_graph, cb_node_types)); + VTR_LOG("Average Connection Block Multiplexer size: %lu\n", + find_rr_graph_average_fan_in(rr_graph, cb_node_types)); + VTR_LOG("------------------------------------------------\n"); +} + +} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h new file mode 100644 index 00000000000..6ff78412f06 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -0,0 +1,98 @@ +#ifndef RR_GRAPH_BUILDER_UTILS_H +#define RR_GRAPH_BUILDER_UTILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "device_grid.h" +#include "rr_graph_obj.h" +#include "vtr_geometry.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +size_t find_unidir_routing_channel_width(const size_t& chan_width); + +int get_grid_pin_class_index(const t_grid_tile& cur_grid, + const int pin_index); + +std::vector find_grid_pin_sides(const t_grid_tile& grid, + const size_t& pin_id); + +e_side determine_io_grid_pin_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate); + +std::vector get_grid_side_pins(const t_grid_tile& cur_grid, + const e_pin_type& pin_type, + const e_side& pin_side, + const int& pin_width, + const int& pin_height); + +size_t get_grid_num_pins(const t_grid_tile& cur_grid, + const e_pin_type& pin_type, + const e_side& io_side); + +size_t get_grid_num_classes(const t_grid_tile& cur_grid, + const e_pin_type& pin_type); + +bool is_chanx_exist(const DeviceGrid& grids, + const vtr::Point& chanx_coord, + const bool& through_channel=false); + +bool is_chany_exist(const DeviceGrid& grids, + const vtr::Point& chany_coord, + const bool& through_channel=false); + +bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, + const vtr::Point& chanx_coord, + const bool& through_channel); + +bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, + const vtr::Point& chanx_coord, + const bool& through_channel); + +bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, + const vtr::Point& chany_coord, + const bool& through_channel); + +bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, + const vtr::Point& chany_coord, + const bool& through_channel); + +short get_rr_node_actual_track_id(const RRGraph& rr_graph, + const RRNodeId& track_rr_node, + const vtr::Point& coord, + const vtr::vector>& tileable_rr_graph_node_track_ids); + +vtr::Point get_track_rr_node_start_coordinator(const RRGraph& rr_graph, + const RRNodeId& track_rr_node); + +vtr::Point get_track_rr_node_end_coordinator(const RRGraph& rr_graph, + const RRNodeId& track_rr_node); + +short get_track_rr_node_end_track_id(const RRGraph& rr_graph, + const RRNodeId& track_rr_node, + const vtr::vector>& tileable_rr_graph_node_track_ids); + +short find_rr_graph_num_nodes(const RRGraph& rr_graph, + const std::vector& node_types); + +short find_rr_graph_max_fan_in(const RRGraph& rr_graph, + const std::vector& node_types); + +short find_rr_graph_min_fan_in(const RRGraph& rr_graph, + const std::vector& node_types); + +short find_rr_graph_average_fan_in(const RRGraph& rr_graph, + const std::vector& node_types); + +void print_rr_graph_mux_stats(const RRGraph& rr_graph); + +} /* end namespace openfpga */ + +#endif + diff --git a/vpr/src/tileable_rr_graph/rr_graph_obj_util.h b/vpr/src/tileable_rr_graph/rr_graph_obj_util.h new file mode 100644 index 00000000000..01f753ddcf6 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_obj_util.h @@ -0,0 +1,35 @@ +#ifndef RR_GRAPH_OBJ_UTIL_H +#define RR_GRAPH_OBJ_UTIL_H + +/* Include header files which include data structures used by + * the function declaration + */ +#include +#include "rr_graph_obj.h" +#include "device_grid.h" + +/* Get node-to-node switches in a RRGraph */ +std::vector find_rr_graph_switches(const RRGraph& rr_graph, + const RRNodeId& from_node, + const RRNodeId& to_node); + +std::vector find_rr_graph_nodes(const RRGraph& rr_graph, + const int& x, + const int& y, + const t_rr_type& rr_type, + const int& ptc); + +std::vector find_rr_graph_chan_nodes(const RRGraph& rr_graph, + const int& x, + const int& y, + const t_rr_type& rr_type); + +std::vector find_rr_graph_grid_nodes(const RRGraph& rr_graph, + const DeviceGrid& device_grid, + const int& x, + const int& y, + const t_rr_type& rr_type, + const e_side& side); + + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_types.h b/vpr/src/tileable_rr_graph/rr_graph_types.h new file mode 100644 index 00000000000..6cf7e1b56eb --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_types.h @@ -0,0 +1,46 @@ +#ifndef RR_GRAPH_TYPES +#define RR_GRAPH_TYPES + +/******************************************************************** + * Data types required by routing resource graph (RRGraph) definition + *******************************************************************/ + +/******************************************************************** + * Directionality of a routing track (node type CHANX and CHANY) in + * a routing resource graph + *******************************************************************/ +enum e_direction : unsigned char { + INC_DIRECTION = 0, + DEC_DIRECTION = 1, + BI_DIRECTION = 2, + NO_DIRECTION = 3, + NUM_DIRECTIONS +}; + +/* Xifan Tang - string used in describe_rr_node() and write_xml_rr_graph_obj() */ +constexpr std::array DIRECTION_STRING_WRITE_XML = {{"INC_DIR", "DEC_DIR", "BI_DIR", "NO_DIR"}}; + +#if 0 +/* Type of a routing resource node. x-directed channel segment, * + * y-directed channel segment, input pin to a clb to pad, output * + * from a clb or pad (i.e. output pin of a net) and: * + * SOURCE: A dummy node that is a logical output within a block * + * -- i.e., the gate that generates a signal. * + * SINK: A dummy node that is a logical input within a block * + * -- i.e. the gate that needs a signal. */ +typedef enum e_rr_type : unsigned char { + SOURCE = 0, + SINK, + IPIN, + OPIN, + CHANX, + CHANY, + NUM_RR_TYPES +} t_rr_type; +#endif + +// constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; +// constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; + + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp new file mode 100644 index 00000000000..badaa663bac --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -0,0 +1,1149 @@ +/************************************************************************ + * Member functions for class RRGSB + ***********************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_log.h" +#include "vtr_assert.h" + +#include "openfpga_rr_graph_utils.h" +#include "openfpga_side_manager.h" + +#include "rr_gsb.h" + +/* namespace openfpga begins */ +namespace openfpga { + +/************************************************************************ + * Constructors + ***********************************************************************/ +/* Constructor for an empty object */ +RRGSB::RRGSB() { + /* Set a clean start! */ + coordinate_.set(0, 0); + + chan_node_.clear(); + chan_node_direction_.clear(); + chan_node_in_edges_.clear(); + + ipin_node_.clear(); + + opin_node_.clear(); +} + +/************************************************************************ + * Accessors + ***********************************************************************/ +/* Get the number of sides of this SB */ +size_t RRGSB::get_num_sides() const { + VTR_ASSERT (validate_num_sides()); + return chan_node_direction_.size(); +} + +/* Get the number of routing tracks on a side */ +size_t RRGSB::get_chan_width(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return chan_node_[side_manager.to_size_t()].get_chan_width(); +} + +/* Get the number of routing tracks on a side */ +t_rr_type RRGSB::get_chan_type(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return chan_node_[side_manager.to_size_t()].get_type(); +} + +/* Get the maximum number of routing tracks on all sides */ +size_t RRGSB::get_max_chan_width() const { + size_t max_chan_width = 0; + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + max_chan_width = std::max(max_chan_width, get_chan_width(side_manager.get_side())); + } + return max_chan_width; +} + +/* Get the number of routing tracks of a X/Y-direction CB */ +size_t RRGSB::get_cb_chan_width(const t_rr_type& cb_type) const { + return get_chan_width(get_cb_chan_side(cb_type)); +} + +/* Get the sides of ipin_nodes belong to the cb */ +std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) const { + VTR_ASSERT (validate_cb_type(cb_type)); + + std::vector ipin_sides; + + /* Make sure a clean start */ + ipin_sides.clear(); + + switch(cb_type) { + case CHANX: + ipin_sides.push_back(TOP); + ipin_sides.push_back(BOTTOM); + break; + case CHANY: + ipin_sides.push_back(RIGHT); + ipin_sides.push_back(LEFT); + break; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } + + return ipin_sides; +} + +/* Get the direction of a rr_node at a given side and track_id */ +enum PORTS RRGSB::get_chan_node_direction(const e_side& side, const size_t& track_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT( validate_side(side) ); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT( validate_track_id(side, track_id) ); + + return chan_node_direction_[side_manager.to_size_t()][track_id]; +} + +/* Get a list of segments used in this routing channel */ +std::vector RRGSB::get_chan_segment_ids(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT( validate_side(side) ); + + return chan_node_[side_manager.to_size_t()].get_segment_ids(); +} + +/* Get a list of rr_nodes whose sed_id is specified */ +std::vector RRGSB::get_chan_node_ids_by_segment_ids(const e_side& side, + const RRSegmentId& seg_id) const { + return chan_node_[size_t(side)].get_node_ids_by_segment_ids(seg_id); +} + +/* get a rr_node at a given side and track_id */ +RRNodeId RRGSB::get_chan_node(const e_side& side, const size_t& track_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT( validate_side(side) ); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT( validate_track_id(side, track_id) ); + + return chan_node_[side_manager.to_size_t()].get_node(track_id); +} + +std::vector RRGSB::get_chan_node_in_edges(const RRGraph& rr_graph, + const e_side& side, + const size_t& track_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT( validate_side(side) ); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT( validate_track_id(side, track_id) ); + + /* The chan node must be an output port for the GSB, we allow users to access input edges*/ + VTR_ASSERT(OUT_PORT == get_chan_node_direction(side, track_id)); + + /* if sorted, we give sorted edges + * if not sorted, we give the empty vector + */ + if (0 == chan_node_in_edges_.size()) { + std::vector unsorted_edges; + for (const RREdgeId& edge : rr_graph.node_in_edges(get_chan_node(side, track_id))) { + unsorted_edges.push_back(edge); + } + + return unsorted_edges; + } + + return chan_node_in_edges_[side_manager.to_size_t()][track_id]; +} + +/* get the segment id of a channel rr_node */ +RRSegmentId RRGSB::get_chan_node_segment(const e_side& side, const size_t& track_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT( validate_side(side) ); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT( validate_track_id(side, track_id) ); + + return chan_node_[side_manager.to_size_t()].get_node_segment(track_id); +} + +/* Get the number of IPIN rr_nodes on a side */ +size_t RRGSB::get_num_ipin_nodes(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return ipin_node_[side_manager.to_size_t()].size(); +} + +/* get a opin_node at a given side and track_id */ +RRNodeId RRGSB::get_ipin_node(const e_side& side, const size_t& node_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT( validate_side(side) ); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT( validate_ipin_node_id(side, node_id) ); + + return ipin_node_[side_manager.to_size_t()][node_id]; +} + +/* Get the number of OPIN rr_nodes on a side */ +size_t RRGSB::get_num_opin_nodes(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return opin_node_[side_manager.to_size_t()].size(); +} + +/* get a opin_node at a given side and track_id */ +RRNodeId RRGSB::get_opin_node(const e_side& side, const size_t& node_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side) ); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_opin_node_id(side, node_id) ); + + return opin_node_[side_manager.to_size_t()][node_id]; +} + +/* Get the node index of a routing track of a connection block, return -1 if not found */ +int RRGSB::get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const { + enum e_side chan_side = get_cb_chan_side(cb_type); + return get_chan_node_index(chan_side, node); +} + +/* Get the node index in the array, return -1 if not found */ +int RRGSB::get_chan_node_index(const e_side& node_side, const RRNodeId& node) const { + VTR_ASSERT (validate_side(node_side)); + return chan_node_[size_t(node_side)].get_node_track_id(node); +} + +/* Get the node index in the array, return -1 if not found */ +int RRGSB::get_node_index(const RRGraph& rr_graph, + const RRNodeId& node, + const e_side& node_side, + const PORTS& node_direction) const { + size_t cnt; + int ret; + + cnt = 0; + ret = -1; + + /* Depending on the type of rr_node, we search different arrays */ + switch (rr_graph.node_type(node)) { + case CHANX: + case CHANY: + for (size_t inode = 0; inode < get_chan_width(node_side); ++inode){ + if ((node == chan_node_[size_t(node_side)].get_node(inode)) + /* Check if direction meets specification */ + &&(node_direction == chan_node_direction_[size_t(node_side)][inode])) { + cnt++; + ret = inode; + break; + } + } + break; + case IPIN: + for (size_t inode = 0; inode < get_num_ipin_nodes(node_side); ++inode) { + if (node == ipin_node_[size_t(node_side)][inode]) { + cnt++; + ret = inode; + break; + } + } + break; + case OPIN: + for (size_t inode = 0; inode < get_num_opin_nodes(node_side); ++inode) { + if (node == opin_node_[size_t(node_side)][inode]) { + cnt++; + ret = inode; + break; + } + } + break; + default: + VTR_LOG("Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n"); + exit(1); + } + + VTR_ASSERT((0 == cnt)||(1 == cnt)); + + return ret; /* Return an invalid value: nonthing is found*/ +} + +/* Get the side of a node in this SB */ +void RRGSB::get_node_side_and_index(const RRGraph& rr_graph, + const RRNodeId& node, + const PORTS& node_direction, + e_side& node_side, + int& node_index) const { + size_t side; + SideManager side_manager; + + /* Count the number of existence of cur_rr_node in cur_sb_info + * It could happen that same cur_rr_node appears on different sides of a SB + * For example, a routing track go vertically across the SB. + * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. + * We need to ensure that the found rr_node has the same direction as user want. + * By specifying the direction of rr_node, There should be only one rr_node can satisfy! + */ + for (side = 0; side < get_num_sides(); ++side) { + side_manager.set_side(side); + node_index = get_node_index(rr_graph, node, side_manager.get_side(), node_direction); + if (-1 != node_index) { + break; + } + } + + if (side == get_num_sides()) { + /* we find nothing, return NUM_SIDES, and a OPEN node (-1) */ + node_side = NUM_SIDES; + VTR_ASSERT(-1 == node_index); + return; + } + + node_side = side_manager.get_side(); + VTR_ASSERT(-1 != node_index); + + return; +} + +/* Check if the node exist in the opposite side of this Switch Block */ +bool RRGSB::is_sb_node_exist_opposite_side(const RRGraph& rr_graph, + const RRNodeId& node, + const e_side& node_side) const { + SideManager side_manager(node_side); + int index; + + VTR_ASSERT((CHANX == rr_graph.node_type(node)) || (CHANY == rr_graph.node_type(node))); + + /* See if we can find the same src_rr_node in the opposite chan_side + * if there is one, it means a shorted wire across the SB + */ + index = get_node_index(rr_graph, node, side_manager.get_opposite(), IN_PORT); + + return (-1 != index); +} + +/* check if the candidate CB is a mirror of the current one */ +bool RRGSB::is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const { + /* Check if channel width is the same */ + if ( get_cb_chan_width(cb_type) != cand.get_cb_chan_width(cb_type) ) { + return false; + } + + enum e_side chan_side = get_cb_chan_side(cb_type); + + /* check the numbers/directionality of channel rr_nodes */ + if ( false == chan_node_[size_t(chan_side)].is_mirror(rr_graph, cand.chan_node_[size_t(chan_side)]) ) { + return false; + } + + /* check the equivalence of ipins */ + std::vector ipin_side = get_cb_ipin_sides(cb_type); + for (size_t side = 0; side < ipin_side.size(); ++side) { + /* Ensure we have the same number of IPINs on this side */ + if ( get_num_ipin_nodes(ipin_side[side]) != cand.get_num_ipin_nodes(ipin_side[side]) ) { + return false; + } + for (size_t inode = 0; inode < get_num_ipin_nodes(ipin_side[side]); ++inode) { + if (false == is_cb_node_mirror(rr_graph, cand, cb_type, ipin_side[side], inode)) { + return false; + } + } + } + + return true; +} + +/* check if the CB exist in this GSB */ +bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const { + /* if channel width is zero, there is no CB */ + return (0 != get_cb_chan_width(cb_type)); +} + +/* check if the SB exist in this GSB */ +bool RRGSB::is_sb_exist() const { + /* if all the channel width is zero and number of OPINs are zero, there is no SB */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + if (0 != get_chan_width(side_manager.get_side())) { + return true; + } + if (0 != get_num_opin_nodes(side_manager.get_side())) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Check if the node indicates a passing wire across the Switch Block part of the GSB + * Therefore, we actually do the following check + * Check if a track starts from this GSB or not + * For INC_DIRECTION + * (xlow, ylow) should be same as the GSB side coordinate + * For DEC_DIRECTION + * (xhigh, yhigh) should be same as the GSB side coordinate + ***********************************************************************/ +bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph, + const e_side& node_side, + const size_t& track_id) const { + + /* Get the rr_node */ + RRNodeId track_node = get_chan_node(node_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = get_side_block_coordinate(node_side); + + /* Get the coordinate of where the track starts */ + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */ + /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + if ( (track_start.x() == side_coordinate.x()) + && (track_start.y() == side_coordinate.y()) + && (OUT_PORT == get_chan_node_direction(node_side, track_id)) ) { + /* Double check: start track should be an OUTPUT PORT of the GSB */ + return false; /* This is a starting point */ + } + + /* Get the coordinate of where the track ends */ + vtr::Point track_end = get_track_rr_node_end_coordinate(rr_graph, track_node); + + /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ + if ( (track_end.x() == side_coordinate.x()) + && (track_end.y() == side_coordinate.y()) + && (IN_PORT == get_chan_node_direction(node_side, track_id)) ) { + /* Double check: end track should be an INPUT PORT of the GSB */ + return false; /* This is an ending point */ + } + + /* Reach here it means that this will be a passing wire, + * we should be able to find the node on the opposite side of the GSB! + */ + if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) { + VTR_LOG("GSB[%lu][%lu] track node[%lu] at %s:\n", + get_x(), get_y(), track_id, SIDE_STRING[node_side]); + rr_graph.print_node(track_node); + } + VTR_ASSERT (true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)); + + return true; +} + +/* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ +/* Idenify mirror Switch blocks + * Check each two switch blocks: + * Number of channel/opin/ipin rr_nodes are same + * If all above are satisfied, the two switch blocks may be mirrors ! + */ +bool RRGSB::is_sb_mirrorable(const RRGraph& rr_graph, const RRGSB& cand) const { + /* check the numbers of sides */ + if (get_num_sides() != cand.get_num_sides()) { + return false; + } + + /* check the numbers/directionality of channel rr_nodes */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + + /* Ensure we have the same channel width on this side */ + if (get_chan_width(side_manager.get_side()) != cand.get_chan_width(side_manager.get_side())) { + return false; + } + + if ( ((size_t(-1) == get_track_id_first_short_connection(rr_graph, side_manager.get_side())) + && (size_t(-1) != cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side()))) + || ((size_t(-1) != get_track_id_first_short_connection(rr_graph, side_manager.get_side()) ) + && ( size_t(-1) == cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side()))) ) { + return false; + } + } + + /* check the numbers of opin_rr_nodes */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + + if (get_num_opin_nodes(side_manager.get_side()) != cand.get_num_opin_nodes(side_manager.get_side())) { + return false; + } + } + + return true; +} + +/* check if all the routing segments of a side of candidate SB is a mirror of the current one */ +bool RRGSB::is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand, + const e_side& side, const RRSegmentId& seg_id) const { + /* Create a side manager */ + SideManager side_manager(side); + + /* Make sure both Switch blocks has this side!!! */ + VTR_ASSERT ( side_manager.to_size_t() < get_num_sides() ); + VTR_ASSERT ( side_manager.to_size_t() < cand.get_num_sides() ); + + /* check the numbers/directionality of channel rr_nodes */ + /* Ensure we have the same channel width on this side */ + if (get_chan_width(side) != cand.get_chan_width(side)) { + return false; + } + for (size_t itrack = 0; itrack < get_chan_width(side); ++itrack) { + /* Bypass unrelated segments */ + if (seg_id != get_chan_node_segment(side, itrack)) { + continue; + } + /* Check the directionality of each node */ + if (get_chan_node_direction(side, itrack) != cand.get_chan_node_direction(side, itrack)) { + return false; + } + /* Check the track_id of each node + * ptc is not necessary, we care the connectivity! + */ + /* For OUT_PORT rr_node, we need to check fan-in */ + if (OUT_PORT != get_chan_node_direction(side, itrack)) { + continue; /* skip IN_PORT */ + } + + if (false == is_sb_node_mirror(rr_graph, cand, side, itrack)) { + return false; + } + } + + /* check the numbers of opin_rr_nodes */ + if (get_num_opin_nodes(side) != cand.get_num_opin_nodes(side)) { + return false; + } + + /* check the numbers of ipin_rr_nodes */ + if (get_num_ipin_nodes(side) != cand.get_num_ipin_nodes(side)) { + return false; + } + + return true; +} + +/* check if a side of candidate SB is a mirror of the current one */ +bool RRGSB::is_sb_side_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side) const { + + /* get a list of segments */ + std::vector seg_ids = chan_node_[size_t(side)].get_segment_ids(); + + for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { + if (false == is_sb_side_segment_mirror(rr_graph, cand, side, seg_ids[iseg])) { + return false; + } + } + + return true; +} + +/* check if the candidate SB is a mirror of the current one */ +bool RRGSB::is_sb_mirror(const RRGraph& rr_graph, const RRGSB& cand) const { + /* check the numbers of sides */ + if (get_num_sides() != cand.get_num_sides()) { + return false; + } + + /* check the numbers/directionality of channel rr_nodes */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + if (false == is_sb_side_mirror(rr_graph, cand, side_manager.get_side())) { + return false; + } + } + + return true; +} + +/* Public Accessors: Cooridinator conversion */ + +/* get the x coordinate of this GSB */ +size_t RRGSB::get_x() const { + return coordinate_.x(); +} + +/* get the y coordinate of this GSB */ +size_t RRGSB::get_y() const { + return coordinate_.y(); +} + + +/* get the x coordinate of this switch block */ +size_t RRGSB::get_sb_x() const { + return coordinate_.x(); +} + +/* get the y coordinate of this switch block */ +size_t RRGSB::get_sb_y() const { + return coordinate_.y(); +} + +/* Get the number of sides of this SB */ +vtr::Point RRGSB::get_sb_coordinate() const { + return coordinate_; +} + +/* get the x coordinate of this X/Y-direction block */ +size_t RRGSB::get_cb_x(const t_rr_type& cb_type) const { + VTR_ASSERT (validate_cb_type(cb_type)); + switch(cb_type) { + case CHANX: + return get_side_block_coordinate(LEFT).x(); + case CHANY: + return get_side_block_coordinate(TOP).x(); + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } +} + +/* get the y coordinate of this X/Y-direction block */ +size_t RRGSB::get_cb_y(const t_rr_type& cb_type) const { + VTR_ASSERT (validate_cb_type(cb_type)); + switch(cb_type) { + case CHANX: + return get_side_block_coordinate(LEFT).y(); + case CHANY: + return get_side_block_coordinate(TOP).y(); + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } +} + +/* Get the coordinate of the X/Y-direction CB */ +vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { + VTR_ASSERT (validate_cb_type(cb_type)); + switch(cb_type) { + case CHANX: + return get_side_block_coordinate(LEFT); + case CHANY: + return get_side_block_coordinate(TOP); + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } +} + +e_side RRGSB::get_cb_chan_side(const t_rr_type& cb_type) const { + VTR_ASSERT (validate_cb_type(cb_type)); + switch(cb_type) { + case CHANX: + return LEFT; + case CHANY: + return TOP; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } +} + +/* Get the side of routing channel in the GSB according to the side of IPIN */ +e_side RRGSB::get_cb_chan_side(const e_side& ipin_side) const { + switch(ipin_side) { + case TOP: + return LEFT; + case RIGHT: + return TOP; + case BOTTOM: + return LEFT; + case LEFT: + return TOP; + default: + VTR_LOG("Invalid type of ipin_side!\n"); + exit(1); + } +} + +vtr::Point RRGSB::get_side_block_coordinate(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + vtr::Point ret(get_sb_x(), get_sb_y()); + + switch (side_manager.get_side()) { + case TOP: + /* (0 == side) */ + /* 1. Channel Y [x][y+1] inputs */ + ret.set_y(ret.y() + 1); + break; + case RIGHT: + /* 1 == side */ + /* 2. Channel X [x+1][y] inputs */ + ret.set_x(ret.x() + 1); + break; + case BOTTOM: + /* 2 == side */ + /* 3. Channel Y [x][y] inputs */ + break; + case LEFT: + /* 3 == side */ + /* 4. Channel X [x][y] inputs */ + break; + default: + VTR_LOG(" Invalid side!\n"); + exit(1); + } + + return ret; +} + +vtr::Point RRGSB::get_grid_coordinate() const { + vtr::Point ret(get_sb_x(), get_sb_y()); + ret.set_y(ret.y() + 1); + + return ret; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +/* get a copy from a source */ +void RRGSB::set(const RRGSB& src) { + /* Copy coordinate */ + this->set_coordinate(src.get_sb_coordinate().x(), src.get_sb_coordinate().y()); + + /* Initialize sides */ + this->init_num_sides(src.get_num_sides()); + + /* Copy vectors */ + for (size_t side = 0; side < src.get_num_sides(); ++side) { + SideManager side_manager(side); + /* Copy chan_nodes */ + /* skip if there is no channel width */ + if ( 0 < src.get_chan_width(side_manager.get_side()) ) { + this->chan_node_[side_manager.get_side()].set(src.chan_node_[side_manager.get_side()]); + /* Copy chan_node_direction_*/ + this->chan_node_direction_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_chan_width(side_manager.get_side()); ++inode) { + this->chan_node_direction_[side_manager.get_side()].push_back(src.get_chan_node_direction(side_manager.get_side(), inode)); + } + } + + /* Copy opin_node and opin_node_grid_side_ */ + this->opin_node_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_num_opin_nodes(side_manager.get_side()); ++inode) { + this->opin_node_[side_manager.get_side()].push_back(src.get_opin_node(side_manager.get_side(), inode)); + } + + /* Copy ipin_node and ipin_node_grid_side_ */ + this->ipin_node_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_num_ipin_nodes(side_manager.get_side()); ++inode) { + this->ipin_node_[side_manager.get_side()].push_back(src.get_ipin_node(side_manager.get_side(), inode)); + } + } +} + +/* Set the coordinate (x,y) for the switch block */ +void RRGSB::set_coordinate(const size_t& x, const size_t& y) { + coordinate_.set(x, y); +} + +/* Allocate the vectors with the given number of sides */ +void RRGSB::init_num_sides(const size_t& num_sides) { + /* Initialize the vectors */ + chan_node_.resize(num_sides); + chan_node_direction_.resize(num_sides); + ipin_node_.resize(num_sides); + opin_node_.resize(num_sides); +} + +/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ +void RRGSB::add_chan_node(const e_side& node_side, + const RRChan& rr_chan, + const std::vector& rr_chan_dir) { + /* Validate: 1. side is valid, the type of node is valid */ + VTR_ASSERT(validate_side(node_side)); + + /* fill the dedicated element in the vector */ + chan_node_[size_t(node_side)].set(rr_chan); + chan_node_direction_[size_t(node_side)].resize(rr_chan_dir.size()); + for (size_t inode = 0; inode < rr_chan_dir.size(); ++inode) { + chan_node_direction_[size_t(node_side)][inode] = rr_chan_dir[inode]; + } +} + +/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ +void RRGSB::add_ipin_node(const RRNodeId& node, const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + /* push pack the dedicated element in the vector */ + ipin_node_[size_t(node_side)].push_back(node); +} + +/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ +void RRGSB::add_opin_node(const RRNodeId& node, const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + /* push pack the dedicated element in the vector */ + opin_node_[size_t(node_side)].push_back(node); +} + +void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph, + const e_side& chan_side, + const size_t& track_id) { + std::map> from_grid_edge_map; + std::map> from_track_edge_map; + + const RRNodeId& chan_node = chan_node_[size_t(chan_side)].get_node(track_id); + + /* Count the edges and ensure every of them has been sorted */ + size_t edge_counter = 0; + + /* For each incoming edge, find the node side and index in this GSB. + * and cache these. Then we will use the data to sort the edge in the + * following sequence: + * 0----------------------------------------------------------------> num_in_edges() + * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| + * For each side, the edge will be sorted by the node index starting from 0 + * For each side, the edge from grid pins will be the 1st part + * while the edge from routing tracks will be the 2nd part + */ + for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) { + /* We care the source node of this edge, and it should be an input of the GSB!!! */ + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + e_side side = NUM_SIDES; + int index = 0; + get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index); + + /* Must have valid side and index */ + if (NUM_SIDES == side) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("SRC node:\n"); + rr_graph.print_node(src_node); + VTR_LOG("Channel node:\n"); + rr_graph.print_node(chan_node); + } + + VTR_ASSERT(NUM_SIDES != side); + VTR_ASSERT(OPEN != index); + + if (OPIN == rr_graph.node_type(src_node)) { + from_grid_edge_map[side][index] = edge; + } else { + VTR_ASSERT( (CHANX == rr_graph.node_type(src_node)) + || (CHANY == rr_graph.node_type(src_node)) ); + from_track_edge_map[side][index] = edge; + } + + edge_counter++; + } + + /* Store the sorted edge */ + for (size_t side = 0; side < get_num_sides(); ++side) { + /* Edges from grid outputs are the 1st part */ + for (size_t opin_id = 0; opin_id < opin_node_[side].size(); ++opin_id) { + if ( (0 < from_grid_edge_map.count(side)) + && (0 < from_grid_edge_map.at(side).count(opin_id)) ) { + chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_grid_edge_map[side][opin_id]); + } + } + + /* Edges from routing tracks are the 2nd part */ + for (size_t itrack = 0; itrack < chan_node_[side].get_chan_width(); ++itrack) { + if ( (0 < from_track_edge_map.count(side)) + && (0 < from_track_edge_map.at(side).count(itrack)) ) { + chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_track_edge_map[side][itrack]); + } + } + } + + VTR_ASSERT(edge_counter == chan_node_in_edges_[size_t(chan_side)][track_id].size()); +} + +void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph) { + /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ + chan_node_in_edges_.resize(get_num_sides()); + + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width()); + for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) { + /* Only sort the output nodes and bypass passing wires */ + if ( (OUT_PORT == chan_node_direction_[side][track_id]) + && (false == is_sb_node_passing_wire(rr_graph, side_manager.get_side(), track_id)) ) { + sort_chan_node_in_edges(rr_graph, side_manager.get_side(), track_id); + } + } + } +} + +/************************************************************************ + * Public Mutators: clean-up functions + ***********************************************************************/ +/* Reset the RRGSB to pristine state */ +void RRGSB::clear() { + /* Clean all the vectors */ + VTR_ASSERT(validate_num_sides()); + /* Clear the inner vector of each matrix */ + for (size_t side = 0; side < get_num_sides(); ++side) { + chan_node_direction_[side].clear(); + chan_node_[side].clear(); + ipin_node_[side].clear(); + opin_node_[side].clear(); + } + chan_node_direction_.clear(); + chan_node_.clear(); + ipin_node_.clear(); + opin_node_.clear(); +} + +/* Clean the chan_width of a side */ +void RRGSB::clear_chan_nodes(const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + + chan_node_[size_t(node_side)].clear(); + chan_node_direction_[size_t(node_side)].clear(); +} + +/* Clean the number of IPINs of a side */ +void RRGSB::clear_ipin_nodes(const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + + ipin_node_[size_t(node_side)].clear(); +} + +/* Clean the number of OPINs of a side */ +void RRGSB::clear_opin_nodes(const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + + opin_node_[size_t(node_side)].clear(); +} + +/* Clean chan/opin/ipin nodes at one side */ +void RRGSB::clear_one_side(const e_side& node_side) { + clear_chan_nodes(node_side); + clear_ipin_nodes(node_side); + clear_opin_nodes(node_side); +} + +/************************************************************************ + * Internal Accessors: identify mirrors + ***********************************************************************/ + +/* check if two rr_nodes have a similar set of drive_rr_nodes + * for each drive_rr_node: + * 1. CHANX or CHANY: should have the same side and index + * 2. OPIN or IPIN: should have the same side and index + * 3. each drive_rr_switch should be the same + */ +bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph, + const RRGSB& cand, + const e_side& node_side, + const size_t& track_id) const { + /* Ensure rr_nodes are either the output of short-connection or multiplexer */ + bool is_short_conkt = this->is_sb_node_passing_wire(rr_graph, node_side, track_id); + + if (is_short_conkt != cand.is_sb_node_passing_wire(rr_graph, node_side, track_id)) { + return false; + } + + if (true == is_short_conkt) { + /* Since, both are pass wires, + * The two node should be equivalent + * we can return here + */ + return true; + } + + /* Use unsorted/sorted edges */ + std::vector node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id); + std::vector cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id); + + /* For non-passing wires, check driving rr_nodes */ + if (node_in_edges.size() != cand_node_in_edges.size()) { + return false; + } + + VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); + + for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { + RREdgeId src_edge = node_in_edges[iedge]; + RREdgeId src_cand_edge = cand_node_in_edges[iedge]; + RRNodeId src_node = rr_graph.edge_src_node(src_edge); + RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge); + /* node type should be the same */ + if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) { + return false; + } + /* switch type should be the same */ + if (rr_graph.edge_switch(src_edge) != rr_graph.edge_switch(src_cand_edge)) { + return false; + } + int src_node_id, des_node_id; + enum e_side src_node_side, des_node_side; + this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id); + cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id); + if (src_node_id != des_node_id) { + return false; + } + if (src_node_side != des_node_side) { + return false; + } + } + + return true; +} + +/* check if two ipin_nodes have a similar set of drive_rr_nodes + * for each drive_rr_node: + * 1. CHANX or CHANY: should have the same side and index + * 2. each drive_rr_switch should be the same + */ +bool RRGSB::is_cb_node_mirror(const RRGraph& rr_graph, + const RRGSB& cand, + const t_rr_type& cb_type, + const e_side& node_side, + const size_t& node_id) const { + /* Ensure rr_nodes are either the output of short-connection or multiplexer */ + RRNodeId node = this->get_ipin_node(node_side, node_id); + RRNodeId cand_node = cand.get_ipin_node(node_side, node_id); + + if ( rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size() ) { + return false; + } + + std::vector node_in_edges; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + node_in_edges.push_back(edge); + } + + std::vector cand_node_in_edges; + for (const RREdgeId& edge : rr_graph.node_in_edges(cand_node)) { + cand_node_in_edges.push_back(edge); + } + VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); + + for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { + RREdgeId src_edge = node_in_edges[iedge]; + RREdgeId src_cand_edge = cand_node_in_edges[iedge]; + RRNodeId src_node = rr_graph.edge_src_node(src_edge); + RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge); + /* node type should be the same */ + if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) { + return false; + } + /* switch type should be the same */ + if (rr_graph.edge_switch(src_edge)!= rr_graph.edge_switch(src_cand_edge)) { + return false; + } + + int src_node_id, des_node_id; + enum e_side src_node_side, des_node_side; + enum e_side chan_side = get_cb_chan_side(cb_type); + switch (rr_graph.node_type(src_node)) { + case CHANX: + case CHANY: + /* if the drive rr_nodes are routing tracks, find index */ + src_node_id = this->get_chan_node_index(chan_side, src_node); + des_node_id = cand.get_chan_node_index(chan_side, src_cand_node); + break; + case OPIN: + this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id); + cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id); + if (src_node_side != des_node_side) { + return false; + } + break; + default: + VTR_LOG("Invalid type of drive_rr_nodes for ipin_node!\n"); + exit(1); + } + if (src_node_id != des_node_id) { + return false; + } + } + + return true; +} + +size_t RRGSB::get_track_id_first_short_connection(const RRGraph& rr_graph, const e_side& node_side) const { + VTR_ASSERT(validate_side(node_side)); + + /* Walk through chan_nodes and find the first short connection */ + for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { + if (true == is_sb_node_passing_wire(rr_graph, node_side, inode)) { + return inode; + } + } + + return size_t(-1); +} + + +/************************************************************************ + * Internal validators + ***********************************************************************/ +/* Validate if the number of sides are consistent among internal data arrays ! */ +bool RRGSB::validate_num_sides() const { + size_t num_sides = chan_node_direction_.size(); + + if ( num_sides != chan_node_.size() ) { + return false; + } + + if ( num_sides != ipin_node_.size() ) { + return false; + } + + if ( num_sides != opin_node_.size() ) { + return false; + } + + return true; +} + +/* Check if the side valid in the context: does the switch block have the side? */ +bool RRGSB::validate_side(const e_side& side) const { + return (size_t(side) < get_num_sides()); +} + +/* Check the track_id is valid for chan_node_ and chan_node_direction_ */ +bool RRGSB::validate_track_id(const e_side& side, const size_t& track_id) const { + if (false == validate_side(side)) { + return false; + } + + return ( ( track_id < chan_node_[size_t(side)].get_chan_width()) + && ( track_id < chan_node_direction_[size_t(side)].size()) ); +} + +/* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ +bool RRGSB::validate_opin_node_id(const e_side& side, const size_t& node_id) const { + if (false == validate_side(side)) { + return false; + } + return (node_id < opin_node_[size_t(side)].size()); +} + +/* Check the ipin_node_id is valid for opin_node_ and opin_node_grid_side_ */ +bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) const { + if (false == validate_side(side)) { + return false; + } + return (node_id < ipin_node_[size_t(side)].size()); +} + +bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { + return ( (CHANX == cb_type) || (CHANY == cb_type) ); +} + +} /* End namespace openfpga*/ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h new file mode 100644 index 00000000000..279f206f9da --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -0,0 +1,289 @@ +#ifndef RR_GSB_H +#define RR_GSB_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_geometry.h" + +#include "rr_chan.h" + +/* Begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Object Generic Switch Block + * This block contains + * 1. A switch block + * 2. A X-direction Connection block locates at the left side of the switch block + * 2. A Y-direction Connection block locates at the top side of the switch block + * + * +-------------+ +---------------------------------+ + * | | | Y-direction CB | + * | Grid | | [x][y + 1] | + * | [x][y+1] | +---------------------------------+ + * +-------------+ + * TOP SIDE + * +-------------+ +---------------------------------+ + * | | | OPIN_NODE CHAN_NODES OPIN_NODES | + * | | | | + * | | | OPIN_NODES OPIN_NODES | + * | X-direction | | | + * | CB | LEFT SIDE | Switch Block | RIGHT SIDE + * | [x][y] | | [x][y] | + * | | | | + * | | | CHAN_NODES CHAN_NODES | + * | | | | + * | | | OPIN_NODES OPIN_NODES | + * | | | | + * | | | OPIN_NODE CHAN_NODES OPIN_NODES | + * +-------------+ +---------------------------------+ + * BOTTOM SIDE + * num_sides: number of sides of this switch block + * chan_rr_node: a collection of rr_nodes as routing tracks locating at each side of the Switch block <0..num_sides-1><0..chan_width-1> + * chan_rr_node_direction: Indicate if this rr_node is an input or an output of the Switch block <0..num_sides-1><0..chan_width-1> + * ipin_rr_node: a collection of rr_nodes as IPIN of a GRID locating at each side of the Switch block <0..num_sides-1><0..num_ipin_rr_nodes-1> + * ipin_rr_node_grid_side: specify the side of the input pins on which side of a GRID <0..num_sides-1><0..num_ipin_rr_nodes-1> + * opin_rr_node: a collection of rr_nodes as OPIN of a GRID locating at each side of the Switch block <0..num_sides-1><0..num_opin_rr_nodes-1> + * opin_rr_node_grid_side: specify the side of the output pins on which side of a GRID <0..num_sides-1><0..num_opin_rr_nodes-1> + * num_reserved_conf_bits: number of reserved configuration bits this switch block requires (mainly due to RRAM-based multiplexers) + * num_conf_bits: number of configuration bits this switch block requires + *******************************************************************/ +class RRGSB { + public: /* Contructors */ + RRGSB();/* Default constructor */ + public: /* Accessors */ + /* Get the number of sides of this SB */ + size_t get_num_sides() const; + + /* Get the number of routing tracks on a side */ + size_t get_chan_width(const e_side& side) const; + + /* Get the type of routing tracks on a side */ + t_rr_type get_chan_type(const e_side& side) const; + + /* Get the maximum number of routing tracks on all sides */ + size_t get_max_chan_width() const; + + /* Get the number of routing tracks of a X/Y-direction CB */ + size_t get_cb_chan_width(const t_rr_type& cb_type) const; + + /* Get the sides of CB ipins in the array */ + std::vector get_cb_ipin_sides(const t_rr_type& cb_type) const; + + /* Get the direction of a rr_node at a given side and track_id */ + enum PORTS get_chan_node_direction(const e_side& side, const size_t& track_id) const; + + /* Get a list of segments used in this routing channel */ + std::vector get_chan_segment_ids(const e_side& side) const; + + /* Get a list of segments used in this routing channel */ + std::vector get_chan_node_ids_by_segment_ids(const e_side& side, + const RRSegmentId& seg_id) const; + + /* get a rr_node at a given side and track_id */ + RRNodeId get_chan_node(const e_side& side, const size_t& track_id) const; + + /* get all the sorted incoming edges for a rr_node at a given side and track_id */ + std::vector get_chan_node_in_edges(const RRGraph& rr_graph, + const e_side& side, + const size_t& track_id) const; + + /* get the segment id of a channel rr_node */ + RRSegmentId get_chan_node_segment(const e_side& side, const size_t& track_id) const; + + /* Get the number of IPIN rr_nodes on a side */ + size_t get_num_ipin_nodes(const e_side& side) const; + + /* get a rr_node at a given side and track_id */ + RRNodeId get_ipin_node(const e_side& side, const size_t& node_id) const; + + /* Get the number of OPIN rr_nodes on a side */ + size_t get_num_opin_nodes(const e_side& side) const; + + /* get a rr_node at a given side and track_id */ + RRNodeId get_opin_node(const e_side& side, const size_t& node_id) const; + + int get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const; + + int get_chan_node_index(const e_side& node_side, const RRNodeId& node) const; + + /* Get the node index in the array, return -1 if not found */ + int get_node_index(const RRGraph& rr_graph, const RRNodeId& node, const e_side& node_side, const PORTS& node_direction) const; + + /* Given a rr_node, try to find its side and index in the Switch block */ + void get_node_side_and_index(const RRGraph& rr_graph, const RRNodeId& node, const PORTS& node_direction, e_side& node_side, int& node_index) const; + + /* Check if the node exist in the opposite side of this Switch Block */ + bool is_sb_node_exist_opposite_side(const RRGraph& rr_graph, const RRNodeId& node, const e_side& node_side) const; + public: /* Accessors: to identify mirrors */ + /* check if the candidate SB is a mirror of the current one */ + bool is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const; + + /* check if the connect block exists in the GSB */ + bool is_cb_exist(const t_rr_type& cb_type) const; + + /* check if the switch block exists in the GSB */ + bool is_sb_exist() const; + + /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */ + bool is_sb_node_passing_wire(const RRGraph& rr_graph, const e_side& node_side, const size_t& track_id) const; + + /* check if the candidate SB satisfy the basic requirements + * on being a mirror of the current one + */ + bool is_sb_mirrorable(const RRGraph& rr_graph, const RRGSB& cand) const; + + /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ + bool is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand, + const e_side& side, const RRSegmentId& seg_id) const; + + /* check if a side of candidate SB is a mirror of the current one + * Check the specified side of two switch blocks: + * 1. Number of channel/opin/ipin rr_nodes are same + * For channel rr_nodes + * 2. check if their track_ids (ptc_num) are same + * 3. Check if the switches (ids) are same + * For opin/ipin rr_nodes, + * 4. check if their parent type_descriptors same, + * 5. check if pin class id and pin id are same + * If all above are satisfied, the side of the two switch blocks are mirrors! + */ + bool is_sb_side_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side) const; + + /* check if the candidate SB is a mirror of the current one + * Idenify mirror Switch blocks + * Check each two switch blocks: + * 1. Number of channel/opin/ipin rr_nodes are same + * For channel rr_nodes + * 2. check if their track_ids (ptc_num) are same + * 3. Check if the switches (ids) are same + * For opin/ipin rr_nodes, + * 4. check if their parent type_descriptors same, + * 5. check if pin class id and pin id are same + * If all above are satisfied, the two switch blocks are mirrors! + */ + bool is_sb_mirror(const RRGraph& rr_graph, const RRGSB& cand) const; + + public: /* Cooridinator conversion and output */ + size_t get_x() const; /* get the x coordinate of this switch block */ + size_t get_y() const; /* get the y coordinate of this switch block */ + size_t get_sb_x() const; /* get the x coordinate of this switch block */ + size_t get_sb_y() const; /* get the y coordinate of this switch block */ + vtr::Point get_sb_coordinate() const; /* Get the coordinate of the SB */ + size_t get_cb_x(const t_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */ + size_t get_cb_y(const t_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */ + vtr::Point get_cb_coordinate(const t_rr_type& cb_type) const; /* Get the coordinate of the X/Y-direction CB */ + e_side get_cb_chan_side(const t_rr_type& cb_type) const; /* get the side of a Connection block */ + e_side get_cb_chan_side(const e_side& ipin_side) const; /* get the side of a Connection block */ + vtr::Point get_side_block_coordinate(const e_side& side) const; + vtr::Point get_grid_coordinate() const; + public: /* Mutators */ + /* get a copy from a source */ + void set(const RRGSB& src); + void set_coordinate(const size_t& x, const size_t& y); + + /* Allocate the vectors with the given number of sides */ + void init_num_sides(const size_t& num_sides); + + /* Add a node to the chan_rr_node_ list and also + * assign its direction in chan_rr_node_direction_ + */ + void add_chan_node(const e_side& node_side, + const RRChan& rr_chan, + const std::vector& rr_chan_dir); + + /* Add a node to the chan_rr_node_ list and also + * assign its direction in chan_rr_node_direction_ + */ + void add_ipin_node(const RRNodeId& node, + const e_side& node_side); + + /* Add a node to the chan_rr_node_ list and also + * assign its direction in chan_rr_node_direction_ + */ + void add_opin_node(const RRNodeId& node, + const e_side& node_side); + + /* Sort all the incoming edges for routing channel rr_node */ + void sort_chan_node_in_edges(const RRGraph& rr_graph); + + public: /* Mutators: cleaners */ + void clear(); + + /* Clean the chan_width of a side */ + void clear_chan_nodes(const e_side& node_side); + + /* Clean the number of IPINs of a side */ + void clear_ipin_nodes(const e_side& node_side); + + /* Clean the number of OPINs of a side */ + void clear_opin_nodes(const e_side& node_side); + + /* Clean chan/opin/ipin nodes at one side */ + void clear_one_side(const e_side& node_side); + + private: /* Private Mutators: edge sorting */ + /* Sort all the incoming edges for one channel rr_node */ + void sort_chan_node_in_edges(const RRGraph& rr_graph, + const e_side& chan_side, + const size_t& track_id); + + private: /* internal functions */ + bool is_sb_node_mirror(const RRGraph& rr_graph, + const RRGSB& cand, + const e_side& node_side, + const size_t& track_id) const; + + bool is_cb_node_mirror(const RRGraph& rr_graph, + const RRGSB& cand, + const t_rr_type& cb_type, + const e_side& node_side, + const size_t& node_id) const; + + size_t get_track_id_first_short_connection(const RRGraph& rr_graph, const e_side& node_side) const; + + private: /* internal validators */ + bool validate_num_sides() const; + bool validate_side(const e_side& side) const; + bool validate_track_id(const e_side& side, const size_t& track_id) const; + bool validate_opin_node_id(const e_side& side, const size_t& node_id) const; + bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const; + bool validate_cb_type(const t_rr_type& cb_type) const; + private: /* Internal Data */ + /* Coordinator */ + vtr::Point coordinate_; + + /* Routing channel data + * Each GSB may have four sides of routing track nodes + */ + /* Node id in rr_graph denoting each routing track */ + std::vector chan_node_; + + /* Direction of a port when the channel node appear in the GSB module */ + std::vector> chan_node_direction_; + + /* Sequence of edge ids for each routing channel node, + * this is sorted by the location of edge source nodes in the context of GSB + * The edge sorting is critical to uniquify the routing modules in OpenFPGA + * This is due to that VPR allocate and sort edges randomly when building the rr_graph + * As a result, previous nodes of a chan node may be the same in different GSBs + * but their sequence is not. This will cause graph comparison to fail when uniquifying + * the routing modules. Therefore, edge sorting can be done inside the GSB + * + * Storage organization: + * [chan_side][chan_node][edge_id_in_gsb_context] + */ + std::vector>> chan_node_in_edges_; + + /* Logic Block Inputs data */ + std::vector> ipin_node_; + + /* Logic Block Outputs data */ + std::vector> opin_node_; +}; + +} /* End namespace openfpga*/ + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp new file mode 100644 index 00000000000..2436d170c6d --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -0,0 +1,234 @@ +/************************************************************************ + * This file contains a builder for the ChanNodeDetails data structure + * Different from VPR rr_graph builders, this builder aims to create a + * highly regular routing channel. Thus, it is called tileable, + * which brings significant advantage in producing large FPGA fabrics. + ***********************************************************************/ +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "rr_graph_builder_utils.h" +#include "tileable_chan_details_builder.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Generate the number of tracks for each types of routing segments + * w.r.t. the frequency of each of segments and channel width + * Note that if we dertermine the number of tracks per type using + * chan_width * segment_frequency / total_freq may cause + * The total track num may not match the chan_width, + * therefore, we assign tracks one by one until we meet the frequency requirement + * In this way, we can assign the number of tracks with repect to frequency + ***********************************************************************/ +std::vector get_num_tracks_per_seg_type(const size_t& chan_width, + const std::vector& segment_inf, + const bool& use_full_seg_groups) { + std::vector result; + std::vector demand; + /* Make sure a clean start */ + result.resize(segment_inf.size()); + demand.resize(segment_inf.size()); + + /* Scale factor so we can divide by any length + * and still use integers */ + /* Get the sum of frequency */ + size_t scale = 1; + size_t freq_sum = 0; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + scale *= segment_inf[iseg].length; + freq_sum += segment_inf[iseg].frequency; + } + size_t reduce = scale * freq_sum; + + /* Init assignments to 0 and set the demand values */ + /* Get the fraction of each segment type considering the frequency: + * num_track_per_seg = chan_width * (freq_of_seg / sum_freq) + */ + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + result[iseg] = 0; + demand[iseg] = scale * chan_width * segment_inf[iseg].frequency; + if (true == use_full_seg_groups) { + demand[iseg] /= segment_inf[iseg].length; + } + } + + /* check if the sum of num_tracks, matches the chan_width */ + /* Keep assigning tracks until we use them up */ + size_t assigned = 0; + size_t size = 0; + size_t imax = 0; + while (assigned < chan_width) { + /* Find current maximum demand */ + double max = 0; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + if (demand[iseg] > max) { + imax = iseg; + } + max = std::max(demand[iseg], max); + } + + /* Assign tracks to the type and reduce the types demand */ + size = (use_full_seg_groups ? segment_inf[imax].length : 1); + demand[imax] -= reduce; + result[imax] += size; + assigned += size; + } + + /* Undo last assignment if we were closer to goal without it */ + if ((assigned - chan_width) > (size / 2)) { + result[imax] -= size; + } + + return result; +} + +/************************************************************************ + * Adapt the number of channel width to a tileable routing architecture + ***********************************************************************/ +int adapt_to_tileable_route_chan_width(const int& chan_width, + const std::vector& segment_infs) { + int tileable_chan_width = 0; + + /* Estimate the number of segments per type by the given ChanW*/ + std::vector num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width, + segment_infs, + true); /* Force to use the full segment group */ + /* Sum-up the number of tracks */ + for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) { + tileable_chan_width += num_tracks_per_seg_type[iseg]; + } + + return tileable_chan_width; +} + +/************************************************************************ + * Build details of routing tracks in a channel + * The function will + * 1. Assign the segments for each routing channel, + * To be specific, for each routing track, we assign a routing segment. + * The assignment is subject to users' specifications, such as + * a. length of each type of segment + * b. frequency of each type of segment. + * c. routing channel width + * + * 2. The starting point of each segment in the channel will be assigned + * For each segment group with same directionality (tracks have the same length), + * every L track will be a starting point (where L denotes the length of segments) + * In this case, if the number of tracks is not a multiple of L, + * indeed we may have some | Yes | No | + * +---------------------------------------+--------------+ + * | 1 | <--------MUX | Yes | No | + * +---------------------------------------+--------------+ + * | 2 | --------> | No | No | + * +---------------------------------------+--------------+ + * | 3 | <-------- | No | No | + * +---------------------------------------+--------------+ + * | 4 | --------> | No | No | + * +---------------------------------------+--------------+ + * | 5 | <-------- | No | No | + * +---------------------------------------+--------------+ + * | 7 | -------->MUX | No | Yes | + * +---------------------------------------+--------------+ + * | 8 | MUX<-------- | No | Yes | + * +---------------------------------------+--------------+ + * | 9 | MUX--------> | Yes | No | + * +---------------------------------------+--------------+ + * | 10 | <--------MUX | Yes | No | + * +---------------------------------------+--------------+ + * | 11 | -------->MUX | No | Yes | + * +------------------------------------------------------+ + * | 12 | <-------- | No | No | + * +------------------------------------------------------+ + * + * 3. SPECIAL for fringes: TOP|RIGHT|BOTTOM|RIGHT + * if device_side is NUM_SIDES, we assume this channel does not locate on borders + * All segments will start and ends with no exception + * + * 4. IMPORTANT: we should be aware that channel width maybe different + * in X-direction and Y-direction channels!!! + * So we will load segment details for different channels + ***********************************************************************/ +ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, + const size_t& max_seg_length, + const bool& force_start, + const bool& force_end, + const std::vector& segment_inf) { + ChanNodeDetails chan_node_details; + size_t actual_chan_width = find_unidir_routing_channel_width(chan_width); + VTR_ASSERT(0 == actual_chan_width % 2); + + /* Reserve channel width */ + chan_node_details.reserve(chan_width); + /* Return if zero width is forced */ + if (0 == actual_chan_width) { + return chan_node_details; + } + + /* Find the number of segments required by each group */ + std::vector num_tracks = get_num_tracks_per_seg_type(actual_chan_width / 2, segment_inf, false); + + /* Add node to ChanNodeDetails */ + size_t cur_track = 0; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + /* segment length will be set to maxium segment length if this is a longwire */ + size_t seg_len = segment_inf[iseg].length; + if (true == segment_inf[iseg].longline) { + seg_len = max_seg_length; + } + for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { + bool seg_start = false; + bool seg_end = false; + /* Every first track of a group of Length-N wires, we set a starting point */ + if (0 == itrack % seg_len) { + seg_start = true; + } + /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ + if ( (seg_len - 1 == itrack % seg_len) + || (itrack == num_tracks[iseg] - 1) ) { + seg_end = true; + } + /* Since this is a unidirectional routing architecture, + * Add a pair of tracks, 1 INC track and 1 DEC track + */ + chan_node_details.add_track(cur_track, Direction::INC, iseg, seg_len, seg_start, seg_end); + cur_track++; + chan_node_details.add_track(cur_track, Direction::DEC, iseg, seg_len, seg_start, seg_end); + cur_track++; + } + } + /* Check if all the tracks have been satisified */ + VTR_ASSERT(cur_track == actual_chan_width); + + /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ + if (true == force_start) { + /* INC should all start */ + chan_node_details.set_tracks_start(Direction::INC); + /* DEC should all end */ + chan_node_details.set_tracks_end(Direction::DEC); + } + + /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ + if (true == force_end) { + /* INC should all end */ + chan_node_details.set_tracks_end(Direction::INC); + /* DEC should all start */ + chan_node_details.set_tracks_start(Direction::DEC); + } + + return chan_node_details; +} + +} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h new file mode 100644 index 00000000000..e6adb71621b --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h @@ -0,0 +1,32 @@ +#ifndef TILEABLE_CHAN_DETAILS_BUILDER_H +#define TILEABLE_CHAN_DETAILS_BUILDER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "physical_types.h" +#include "chan_node_details.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +std::vector get_num_tracks_per_seg_type(const size_t& chan_width, + const std::vector& segment_inf, + const bool& use_full_seg_groups); + +int adapt_to_tileable_route_chan_width(const int& chan_width, const std::vector& segment_inf); + +ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, + const size_t& max_seg_length, + const bool& force_start, + const bool& force_end, + const std::vector& segment_inf); + +} /* end namespace openfpga */ + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp new file mode 100644 index 00000000000..43c41de5416 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -0,0 +1,370 @@ +/************************************************************************ + * This file contains a builder for the complex rr_graph data structure + * Different from VPR rr_graph builders, this builder aims to create a + * highly regular rr_graph, where each Connection Block (CB), Switch + * Block (SB) is the same (except for those on the borders). Thus, the + * rr_graph is called tileable, which brings significant advantage in + * producing large FPGA fabrics. + ***********************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_time.h" +#include "vtr_log.h" +#include "vtr_memory.h" + +#include "vpr_error.h" +#include "vpr_utils.h" + +#include "rr_graph.h" +#include "check_rr_graph.h" +#include "check_rr_graph_obj.h" + +#include "rr_graph_builder_utils.h" +#include "tileable_chan_details_builder.h" +#include "tileable_rr_graph_node_builder.h" +#include "tileable_rr_graph_edge_builder.h" +#include "tileable_rr_graph_builder.h" + +#include "globals.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Main function of this file + * Builder for a detailed uni-directional tileable rr_graph + * Global graph is not supported here, the VPR rr_graph generator can be used + * It follows the procedures to complete the rr_graph generation + * 1. Assign the segments for each routing channel, + * To be specific, for each routing track, we assign a routing segment. + * The assignment is subject to users' specifications, such as + * a. length of each type of segment + * b. frequency of each type of segment. + * c. routing channel width + * 2. Estimate the number of nodes in the rr_graph + * This will estimate the number of + * a. IPINs, input pins of each grid + * b. OPINs, output pins of each grid + * c. SOURCE, virtual node which drives OPINs + * d. SINK, virtual node which is connected to IPINs + * e. CHANX and CHANY, routing segments of each channel + * 3. Create the connectivity of OPINs + * a. Evenly assign connections to OPINs to routing tracks + * b. the connection pattern should be same across the fabric + * 4. Create the connectivity of IPINs + * a. Evenly assign connections from routing tracks to IPINs + * b. the connection pattern should be same across the fabric + * 5. Create the switch block patterns, + * It is based on the type of switch block, the supported patterns are + * a. Disjoint, which connects routing track (i)th from (i)th and (i)th routing segments + * b. Universal, which connects routing track (i)th from (i)th and (M-i)th routing segments + * c. Wilton, which rotates the connection of Disjoint by 1 track + * 6. Allocate rr_graph, fill the node information + * For each node, fill + * a. basic information: coordinate(xlow, xhigh, ylow, yhigh), ptc_num + * b. edges (both incoming and outcoming) + * c. handle direct-connections + * 7. Build fast look-up for the rr_graph + * 8. Allocate external data structures + * a. cost_index + * b. RC tree + ***********************************************************************/ + +// external functions: in vpr/src/route/rr_graph.cpp +extern std::vector> alloc_and_load_actual_fc(const std::vector& types, + const int max_pins, + const std::vector& segment_inf, + + const int* sets_per_seg_type, + const int max_chan_width, + const e_fc_type fc_type, + const enum e_directionality directionality, + bool* Fc_clipped); +extern t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch); +extern void alloc_and_load_rr_switch_inf(const int num_arch_switches, + const float R_minW_nmos, + const float R_minW_pmos, + const int wire_to_arch_ipin_switch, + int* wire_to_rr_ipin_switch); +extern void rr_graph_externals(const std::vector& segment_inf, + int wire_to_rr_ipin_switch, + enum e_base_cost_type base_cost_type); + +void build_tileable_unidir_rr_graph(const std::vector& types, + const DeviceGrid& grids, + const t_chan_width& chan_width, + const e_switch_block_type& sb_type, const int& Fs, + const e_switch_block_type& sb_subtype, const int& subFs, + const std::vector& segment_inf, + const int& delayless_switch, + const int& wire_to_arch_ipin_switch, + const float R_minW_nmos, + const float R_minW_pmos, + const enum e_base_cost_type& base_cost_type, + const t_direct_inf *directs, + const int& num_directs, + int* wire_to_rr_ipin_switch, + const bool& through_channel, + const bool& wire_opposite_side, + int *Warnings) { + + vtr::ScopedStartFinishTimer timer("Build tileable routing resource graph"); + + /* Reset warning flag */ + *Warnings = RR_GRAPH_NO_WARN; + + /* Create a matrix of grid */ + /* Create a vector of channel width, we support X-direction and Y-direction has different W */ + vtr::Point device_chan_width(chan_width.x_max, chan_width.y_max); + + VTR_LOG("X-direction routing channel width is %lu\n", device_chan_width.x()); + VTR_LOG("Y-direction routing channel width is %lu\n", device_chan_width.y()); + + /* Get a mutable device ctx so that we have a mutable rr_graph */ + DeviceContext& device_ctx = g_vpr_ctx.mutable_device(); + + /* The number of segments are in general small, reserve segments may not bring + * significant memory efficiency */ + device_ctx.rr_graph_builder.reserve_segments(segment_inf.size()); + /* Create the segments */ + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + device_ctx.rr_graph_builder.add_rr_segment(segment_inf[iseg]); + } + + /* TODO: Load architecture switch to rr_graph switches + * Draft the switches as internal data of RRGraph object + * These are temporary switches copied from arch switches + * We use them to build the edges + * We will reset all the switches in the function + * alloc_and_load_rr_switch_inf() + */ + /* TODO: Spot the switch id in the architecture switch list */ + RRSwitchId wire_to_ipin_rr_switch = RRSwitchId::INVALID(); + RRSwitchId delayless_rr_switch = RRSwitchId::INVALID(); + + device_ctx.rr_graph_builder.reserve_switches(device_ctx.num_arch_switches); + /* Create the switches */ + for (int iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) { + const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(iswitch, R_minW_nmos, R_minW_pmos); + RRSwitchId rr_switch = device_ctx.rr_graph_builder.add_rr_switch(temp_rr_switch); + if (iswitch == wire_to_arch_ipin_switch) { + wire_to_ipin_rr_switch = rr_switch; + } + if (iswitch == delayless_switch) { + delayless_rr_switch = rr_switch; + } + } + // NYI + #if 0 + /* Validate the special switches */ + VTR_ASSERT(true == device_ctx.rr_graph_builder.valid_switch_id(wire_to_ipin_rr_switch)); + VTR_ASSERT(true == device_ctx.rr_graph_builder.valid_switch_id(delayless_rr_switch)); + #endif + + /* A temp data about the driver switch ids for each rr_node */ + vtr::vector rr_node_driver_switches; + + /* A temp data about the track ids for each CHANX and CHANY rr_node */ + std::map> rr_node_track_ids; + + /************************ + * Allocate the rr_nodes + ************************/ + alloc_tileable_rr_graph_nodes(device_ctx.rr_graph_builder, + rr_node_driver_switches, + grids, + device_chan_width, + segment_inf, + through_channel); + + /************************ + * Create all the rr_nodes + ************************/ + create_tileable_rr_graph_nodes(device_ctx.rr_graph, + device_ctx.rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + device_chan_width, + segment_inf, + wire_to_ipin_rr_switch, + delayless_rr_switch, + through_channel); + + /************************************************************************ + * Create the connectivity of OPINs + * a. Evenly assign connections to OPINs to routing tracks + * b. the connection pattern should be same across the fabric + * + * Create the connectivity of IPINs + * a. Evenly assign connections from routing tracks to IPINs + * b. the connection pattern should be same across the fabric + ***********************************************************************/ + /* Global routing uses a single longwire track */ + int max_chan_width = find_unidir_routing_channel_width(chan_width.max); + VTR_ASSERT(max_chan_width > 0); + + /* get maximum number of pins across all blocks */ + int max_pins = types[0].num_pins; + for (const auto& type : types) { + if (is_empty_type(&type)) { + continue; + } + + if (type.num_pins > max_pins) { + max_pins = type.num_pins; + } + } + + /* Fc assignment still uses the old function from VPR. + * Should use tileable version so that we have can have full control + */ + std::vector num_tracks = get_num_tracks_per_seg_type(max_chan_width / 2, segment_inf, false); + int* sets_per_seg_type = (int*)vtr::malloc(sizeof(int) * segment_inf.size()); + VTR_ASSERT(num_tracks.size() == segment_inf.size()); + for (size_t iseg = 0; iseg < num_tracks.size(); ++iseg) { + sets_per_seg_type[iseg] = num_tracks[iseg]; + } + + bool Fc_clipped = false; + /* [0..num_types-1][0..num_pins-1] */ + std::vector> Fc_in; + Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width, + e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped); + if (Fc_clipped) { + *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; + } + + Fc_clipped = false; + /* [0..num_types-1][0..num_pins-1] */ + std::vector> Fc_out; + Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width, + e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped); + + if (Fc_clipped) { + *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; + } + + /************************************************************************ + * Build the connections tile by tile: + * We classify rr_nodes into a general switch block (GSB) data structure + * where we create edges to each rr_nodes in the GSB with respect to + * Fc_in and Fc_out, switch block patterns + * In addition, we will also handle direct-connections: + * Add edges that bridge OPINs and IPINs to the rr_graph + ***********************************************************************/ + /* Create edges for a tileable rr_graph */ + build_rr_graph_edges(device_ctx.rr_graph, + rr_node_driver_switches, + grids, + device_chan_width, + segment_inf, + Fc_in, Fc_out, + sb_type, Fs, sb_subtype, subFs, + wire_opposite_side); + + /************************************************************************ + * Build direction connection lists + * TODO: use tile direct builder + ***********************************************************************/ + /* Create data structure of direct-connections */ + t_clb_to_clb_directs* clb_to_clb_directs = NULL; + if (num_directs > 0) { + clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs, delayless_switch); + } + std::vector arch_directs; + std::vector clb2clb_directs; + for (int idirect = 0; idirect < num_directs; ++idirect) { + arch_directs.push_back(directs[idirect]); + clb2clb_directs.push_back(clb_to_clb_directs[idirect]); + } + + build_rr_graph_direct_connections(device_ctx.rr_graph, grids, delayless_rr_switch, + arch_directs, clb2clb_directs); + +//NYI +#if 0 + /* First time to build edges so that we can remap the architecture switch to rr_switch + * This is a must-do before function alloc_and_load_rr_switch_inf() + */ + device_ctx.rr_graph.rebuild_node_edges(); +#endif + + /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, + * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ + alloc_and_load_rr_switch_inf(device_ctx.num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); + + /* Save the channel widths for the newly constructed graph */ + device_ctx.chan_width = chan_width; + +//NYI +#if 0 + /* Save the track ids for tileable routing resource graph */ + device_ctx.rr_node_track_ids = rr_node_track_ids; +#endif + + /************************************************************************ + * Allocate external data structures + * a. cost_index + * b. RC tree + ***********************************************************************/ + rr_graph_externals(segment_inf, + *wire_to_rr_ipin_switch, base_cost_type); + + /* Rebuild the link between RRGraph node and segments + * Should be called only AFTER the function + * rr_graph_externals() + */ + for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { + if ( (CHANX != device_ctx.rr_graph.node_type(inode)) + && (CHANY != device_ctx.rr_graph.node_type(inode)) ) { + continue; + } +//NYI +#if 0 + RRIndexedDataId irc_data = device_ctx.rr_graph.node_cost_index(inode); + short iseg = device_ctx.rr_indexed_data[irc_data].seg_index; + device_ctx.rr_graph_builder.set_node_segment(inode, RRSegmentId(iseg)); // NYI +#endif + + } + + /************************************************************************ + * Sanitizer for the rr_graph, check connectivities of rr_nodes + ***********************************************************************/ + /* Essential check for rr_graph, build look-up and */ + if (false == device_ctx.rr_graph_builder.validate()) { + /* Error out if built-in validator of rr_graph fails */ + vpr_throw(VPR_ERROR_ROUTE, + __FILE__, + __LINE__, + "Fundamental errors occurred when validating rr_graph object!\n"); + } + + check_rr_graph(GRAPH_UNIDIR, grids, types); + + // NYI + // vpr integration: DeviceContext does not provide direct RRGraph access + // we can skip it since check_rr_graph(GRAPH_UNDIR, GRIDS, TYPES) has been called above +#if 0 + /* Error out if advanced checker of rr_graph fails */ + if (false == check_rr_graph(device_ctx.rr_graph)) { + vpr_throw(VPR_ERROR_ROUTE, + __FILE__, + __LINE__, + "Advanced checking rr_graph object fails! Routing may still work " + "but not smooth\n"); + } +#endif + + /************************************************************************ + * Free all temp stucts + ***********************************************************************/ + free(sets_per_seg_type); + + if (nullptr != clb_to_clb_directs) { + free(clb_to_clb_directs); + } +} + +} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h new file mode 100644 index 00000000000..46be3817d76 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -0,0 +1,39 @@ +#ifndef TILEABLE_RR_GRAPH_BUILDER_H +#define TILEABLE_RR_GRAPH_BUILDER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "physical_types.h" +#include "device_grid.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void build_tileable_unidir_rr_graph(const std::vector& types, + const DeviceGrid& grids, + const t_chan_width& chan_width, + const e_switch_block_type& sb_type, const int& Fs, + const e_switch_block_type& sb_subtype, const int& subFs, + const std::vector& segment_inf, + const int& delayless_switch, + const int& wire_to_arch_ipin_switch, + const float R_minW_nmos, + const float R_minW_pmos, + const enum e_base_cost_type& base_cost_type, + const t_direct_inf *directs, + const int& num_directs, + int* wire_to_rr_ipin_switch, + const bool& through_channel, + const bool& wire_opposite_side, + int *Warnings); + +} /* end namespace openfpga */ + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp new file mode 100644 index 00000000000..fd2d4db62d8 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -0,0 +1,170 @@ +/************************************************************************ + * This file contains functions that are used to build edges + * between nodes of a tileable routing resource graph + ***********************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +#include "vpr_utils.h" + +#include "rr_graph_builder_utils.h" +#include "tileable_rr_graph_gsb.h" +#include "tileable_rr_graph_edge_builder.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Build the edges for all the SOURCE and SINKs nodes: + * 1. create edges between SOURCE and OPINs + ***********************************************************************/ +static +void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids) { + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass all the non OPIN nodes */ + if (OPIN != rr_graph.node_type(node)) { + continue; + } + /* Now, we have an OPIN node, we get the source node index */ + short xlow = rr_graph.node_xlow(node); + short ylow = rr_graph.node_ylow(node); + short src_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], + rr_graph.node_pin_num(node)); + + /* Create edges between SOURCE and OPINs */ + const RRNodeId& src_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, + ylow - grids[xlow][ylow].height_offset, + SOURCE, src_node_class_num); + VTR_ASSERT(true == rr_graph.valid_node_id(src_node)); + + /* add edges to the src_node */ + rr_graph.create_edge(src_node, node, rr_node_driver_switches[node]); + } +} + +/************************************************************************ + * Build the edges for all the SINKs nodes: + * 1. create edges between IPINs and SINKs + ***********************************************************************/ +static +void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids) { + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass all the non IPIN nodes */ + if (IPIN != rr_graph.node_type(node)) { + continue; + } + /* Now, we have an OPIN node, we get the source node index */ + short xlow = rr_graph.node_xlow(node); + short ylow = rr_graph.node_ylow(node); + short sink_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], + rr_graph.node_pin_num(node)); + /* 1. create edges between IPINs and SINKs */ + const RRNodeId& sink_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, + ylow - grids[xlow][ylow].height_offset, + SINK, sink_node_class_num); + VTR_ASSERT(true == rr_graph.valid_node_id(sink_node)); + + /* add edges to connect the IPIN node to SINK nodes */ + rr_graph.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); + } +} + +/************************************************************************ + * Build the edges of each rr_node tile by tile: + * We classify rr_nodes into a general switch block (GSB) data structure + * where we create edges to each rr_nodes in the GSB with respect to + * Fc_in and Fc_out, switch block patterns + * For each GSB: + * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) + * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) + * 3. create edges between OPINs and IPINs (direct-connections) + ***********************************************************************/ +void build_rr_graph_edges(RRGraph& rr_graph, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, const int& Fs, + const e_switch_block_type& sb_subtype, const int& subFs, + const bool& wire_opposite_side) { + + /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ + build_rr_graph_edges_for_source_nodes(rr_graph, rr_node_driver_switches, grids); + build_rr_graph_edges_for_sink_nodes(rr_graph, rr_node_driver_switches, grids); + + vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); + + /* Go Switch Block by Switch Block */ + for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { + for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { + //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); + + vtr::Point gsb_coord(ix, iy); + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf, + gsb_coord); + + /* adapt the track_to_ipin_lookup for the GSB nodes */ + t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); + + /* adapt the opin_to_track_map for the GSB nodes */ + t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out); + + /* adapt the switch_block_conn for the GSB nodes */ + t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, sb_subtype, subFs, wire_opposite_side, + segment_inf); + + /* Build edges for a GSB */ + build_edges_for_one_tileable_rr_gsb(rr_graph, rr_gsb, + track2ipin_map, opin2track_map, + sb_conn, rr_node_driver_switches); + /* Finish this GSB, go to the next*/ + } + } +} + +/************************************************************************ + * Build direct edges for Grids * + ***********************************************************************/ +void build_rr_graph_direct_connections(RRGraph& rr_graph, + const DeviceGrid& grids, + const RRSwitchId& delayless_switch, + const std::vector& directs, + const std::vector& clb_to_clb_directs) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ( (0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset) ) { + continue; + } + vtr::Point from_grid_coordinate(ix, iy); + build_direct_connections_for_one_gsb(rr_graph, + grids, + from_grid_coordinate, + delayless_switch, + directs, clb_to_clb_directs); + } + } +} + +} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h new file mode 100644 index 00000000000..a20cef71712 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -0,0 +1,45 @@ +#ifndef TILEABLE_RR_GRAPH_EDGE_BUILDER_H +#define TILEABLE_RR_GRAPH_EDGE_BUILDER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_ndmatrix.h" +#include "vtr_geometry.h" + +#include "physical_types.h" +#include "device_grid.h" +#include "rr_graph_obj.h" +#include "clb2clb_directs.h" +#include "rr_graph_view.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void build_rr_graph_edges(RRGraphView& rr_graph, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, const int& Fs, + const e_switch_block_type& sb_subtype, const int& subFs, + const bool& wire_opposite_side); + +void build_rr_graph_direct_connections(RRGraphView& rr_graph, + const DeviceGrid& grids, + const RRSwitchId& delayless_switch, + const std::vector& directs, + const std::vector& clb_to_clb_directs); + +} /* end namespace openfpga */ + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp new file mode 100755 index 00000000000..0fc75853dfb --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -0,0 +1,1447 @@ +/************************************************************************ + * This file contains a builder for track-to-track connections inside a + * tileable General Switch Block (GSB). + ***********************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +/* Headers from openfpgautil library */ +#include "openfpga_side_manager.h" + +#include "vpr_utils.h" +#include "rr_graph_obj_util.h" +#include "openfpga_rr_graph_utils.h" +#include "rr_graph_builder_utils.h" +#include "tileable_chan_details_builder.h" +#include "tileable_rr_graph_gsb.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Internal data structures + ***********************************************************************/ +typedef std::vector> t_track_group; + +/************************************************************************ + * A enumeration to list the status of a track inside a GSB + * 1. start; 2. end; 3. passing + * This is used to group tracks which ease the building of + * track-to-track mapping matrix + ***********************************************************************/ +enum e_track_status { + TRACK_START, + TRACK_END, + TRACK_PASS, + NUM_TRACK_STATUS /* just a place holder to get the number of status */ +}; + +/************************************************************************ + * Check if a track starts from this GSB or not + * (xlow, ylow) should be same as the GSB side coordinate + * + * Check if a track ends at this GSB or not + * (xhigh, yhigh) should be same as the GSB side coordinate + ***********************************************************************/ +static +enum e_track_status determine_track_status_of_gsb(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& gsb_side, + const size_t& track_id) { + enum e_track_status track_status = TRACK_PASS; + /* Get the rr_node */ + RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + /* Get the coordinate of where the track starts */ + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */ + /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + if ( (track_start.x() == side_coordinate.x()) + && (track_start.y() == side_coordinate.y()) + && (OUT_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id)) ) { + /* Double check: start track should be an OUTPUT PORT of the GSB */ + track_status = TRACK_START; + } + + /* Get the coordinate of where the track ends */ + vtr::Point track_end = get_track_rr_node_end_coordinate(rr_graph, track_node); + + /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ + if ( (track_end.x() == side_coordinate.x()) + && (track_end.y() == side_coordinate.y()) + && (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id)) ) { + /* Double check: end track should be an INPUT PORT of the GSB */ + track_status = TRACK_END; + } + + return track_status; +} + +/************************************************************************ + * Check if the GSB is in the Connection Block (CB) population list of the segment + * SB population of a L4 wire: 1 0 0 1 + * + * +----+ +----+ +----+ +----+ + * | CB |--->| CB |--->| CB |--->| CB | + * +----+ +----+ +----+ +----+ + * Engage CB connection Yes No No Yes + * + * We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track + * Use the offset to check if the tracks should engage in this GSB connection + ***********************************************************************/ +static +bool is_gsb_in_track_cb_population(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const e_side& gsb_side, + const int& track_id, + const std::vector& segment_inf) { + /* Get the rr_node */ + RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* Get the offset */ + size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) + + std::abs((int)side_coordinate.y() - (int)track_start.y()); + + /* Get segment id */ + RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); + /* validate offset */ + VTR_ASSERT(offset < segment_inf[size_t(seg_id)].cb.size()); + + /* Get the SB population */ + bool in_cb_population = false; + if (true == segment_inf[size_t(seg_id)].cb[offset]) { + in_cb_population = true; + } + + return in_cb_population; +} + +/************************************************************************ + * Check if the GSB is in the Switch Block (SB) population list of the segment + * SB population of a L3 wire: 1 0 0 1 + * + * +----+ +----+ +----+ +----+ + * | SB |--->| SB |--->| SB |--->| SB | + * +----+ +----+ +----+ +----+ + * Engage SB connection Yes No No Yes + * + * We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track + * Use the offset to check if the tracks should engage in this GSB connection + ***********************************************************************/ +static +bool is_gsb_in_track_sb_population(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const e_side& gsb_side, + const int& track_id, + const std::vector& segment_inf) { + /* Get the rr_node */ + const RRNodeId& track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* Get the offset */ + size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) + + std::abs((int)side_coordinate.y() - (int)track_start.y()); + + /* Get segment id */ + RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); + /* validate offset */ + VTR_ASSERT(offset < segment_inf[size_t(seg_id)].sb.size()); + + /* Get the SB population */ + bool in_sb_population = false; + if (true == segment_inf[size_t(seg_id)].sb[offset]) { + in_sb_population = true; + } + + return in_sb_population; +} + +/************************************************************************ + * Create a list of track_id based on the to_track and num_to_tracks + * We consider the following list [to_track, to_track + Fs/3 - 1] + * if the [to_track + Fs/3 - 1] exceeds the num_to_tracks, we start over from 0! +***********************************************************************/ +static +std::vector get_to_track_list(const int& Fs, const int& to_track, const int& num_to_tracks) { + std::vector to_tracks; + + for (int i = 0; i < Fs; i = i + 3) { + /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied + * The optimal track selection should be done in a more scientific way!!! + */ + int to_track_i = to_track + i; + /* make sure the track id is still in range */ + if ( to_track_i > num_to_tracks - 1) { + to_track_i = to_track_i % num_to_tracks; + } + /* Ensure we are in the range */ + VTR_ASSERT(to_track_i < num_to_tracks); + /* from track must be connected */ + to_tracks.push_back(to_track_i); + } + return to_tracks; +} + +/************************************************************************ + * This function aims to return the track indices that drive the from_track + * in a Switch Block + * The track_ids to return will depend on different topologies of SB + * SUBSET, UNIVERSAL, and WILTON. + ***********************************************************************/ +static +std::vector get_switch_block_to_track_id(const e_switch_block_type& switch_block_type, + const int& Fs, + const e_side& from_side, + const int& from_track, + const e_side& to_side, + const int& num_to_tracks) { + + /* This routine returns the track number to which the from_track should + * connect. It supports any Fs % 3 == 0, switch blocks. + */ + std::vector to_tracks; + + /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied + * The optimal track selection should be done in a more scientific way!!! + */ + VTR_ASSERT(0 == Fs % 3); + + /* Adapt from_track to fit in the range of num_to_tracks */ + size_t actual_from_track = from_track % num_to_tracks; + + switch (switch_block_type) { + case SUBSET: /* NB: Global routing uses SUBSET too */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + /* Finish, we return */ + return to_tracks; + case UNIVERSAL: + if ( (from_side == LEFT) + || (from_side == RIGHT) ) { + /* For the prev_side, to_track is from_track + * For the next_side, to_track is num_to_tracks - 1 - from_track + * For the opposite_side, to_track is always from_track + */ + SideManager side_manager(from_side); + if ( (to_side == side_manager.get_opposite()) + || (to_side == side_manager.get_rotate_counterclockwise()) ) { + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == side_manager.get_rotate_clockwise()) { + to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); + } + } + + if ( (from_side == TOP) + || (from_side == BOTTOM) ) { + /* For the next_side, to_track is from_track + * For the prev_side, to_track is num_to_tracks - 1 - from_track + * For the opposite_side, to_track is always from_track + */ + SideManager side_manager(from_side); + if ( (to_side == side_manager.get_opposite()) + || (to_side == side_manager.get_rotate_clockwise()) ) { + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == side_manager.get_rotate_counterclockwise()) { + to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); + } + } + /* Finish, we return */ + return to_tracks; + /* End switch_block_type == UNIVERSAL case. */ + case WILTON: + /* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */ + if (from_side == LEFT) { + if (to_side == RIGHT) { /* CHANX to CHANX */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track ) % num_to_tracks, num_to_tracks); + } else if (to_side == BOTTOM) { + to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); + } + } else if (from_side == RIGHT) { + if (to_side == LEFT) { /* CHANX to CHANX */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); + } else if (to_side == BOTTOM) { + to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); + } + } else if (from_side == BOTTOM) { + if (to_side == TOP) { /* CHANY to CHANY */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); + } else if (to_side == RIGHT) { + to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); + } + } else if (from_side == TOP) { + if (to_side == BOTTOM) { /* CHANY to CHANY */ + to_tracks = get_to_track_list(Fs, from_track, num_to_tracks); + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track) % num_to_tracks, num_to_tracks); + } else if (to_side == RIGHT) { + to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); + } + } + /* Finish, we return */ + return to_tracks; + /* End switch_block_type == WILTON case. */ + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid switch block pattern !\n"); + exit(1); + } + + return to_tracks; +} + + +/************************************************************************ + * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] + * For a group of from_track nodes and to_track nodes + * For each side of from_tracks, we call a routine to get the list of to_tracks + * Then, we fill the track2track_map + ***********************************************************************/ +static +void build_gsb_one_group_track_to_track_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const e_switch_block_type& sb_type, + const int& Fs, + const bool& wire_opposite_side, + const t_track_group& from_tracks, /* [0..gsb_side][track_indices] */ + const t_track_group& to_tracks, /* [0..gsb_side][track_indices] */ + t_track2track_map& track2track_map) { + for (size_t side = 0; side < from_tracks.size(); ++side) { + SideManager side_manager(side); + e_side from_side = side_manager.get_side(); + /* Find the other sides where the start tracks will locate */ + std::vector to_track_sides; + /* 0. opposite side */ + to_track_sides.push_back(side_manager.get_opposite()); + /* 1. prev side */ + /* Previous side definition: TOP => LEFT; RIGHT=>TOP; BOTTOM=>RIGHT; LEFT=>BOTTOM */ + to_track_sides.push_back(side_manager.get_rotate_counterclockwise()); + /* 2. next side */ + /* Next side definition: TOP => RIGHT; RIGHT=>BOTTOM; BOTTOM=>LEFT; LEFT=>TOP */ + to_track_sides.push_back(side_manager.get_rotate_clockwise()); + + for (size_t inode = 0; inode < from_tracks[side].size(); ++inode) { + for (size_t to_side_id = 0; to_side_id < to_track_sides.size(); ++to_side_id) { + enum e_side to_side = to_track_sides[to_side_id]; + SideManager to_side_manager(to_side); + size_t to_side_index = to_side_manager.to_size_t(); + /* Bypass those to_sides have no nodes */ + if (0 == to_tracks[to_side_index].size()) { + continue; + } + /* Bypass those from_side is same as to_side */ + if (from_side == to_side) { + continue; + } + /* Bypass those from_side is opposite to to_side if required */ + if ( (true == wire_opposite_side) + && (to_side_manager.get_opposite() == from_side) ) { + continue; + } + /* Get other track_ids depending on the switch block pattern */ + /* Find the track ids that will start at the other sides */ + std::vector to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode, + to_side, + to_tracks[to_side_index].size()); + /* Update the track2track_map: */ + for (size_t to_track_id = 0; to_track_id < to_track_ids.size(); ++to_track_id) { + size_t from_side_index = side_manager.to_size_t(); + size_t from_track_index = from_tracks[side][inode]; + /* Check the id is still in the range !*/ + VTR_ASSERT( to_track_ids[to_track_id] < to_tracks[to_side_index].size() ); + size_t to_track_index = to_tracks[to_side_index][to_track_ids[to_track_id]]; + //printf("from_track(size=%lu): %lu , to_track_ids[%lu]:%lu, to_track_index: %lu in a group of %lu tracks\n", + // from_tracks[side].size(), inode, to_track_id, to_track_ids[to_track_id], + // to_track_index, to_tracks[to_side_index].size()); + const RRNodeId& to_track_node = rr_gsb.get_chan_node(to_side, to_track_index); + VTR_ASSERT(true == rr_graph.valid_node_id(to_track_node)); + + /* from_track should be IN_PORT */ + VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index)); + /* to_track should be OUT_PORT */ + VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index)); + + /* Check if the to_track_node is already in the list ! */ + std::vector::iterator it = std::find(track2track_map[from_side_index][from_track_index].begin(), + track2track_map[from_side_index][from_track_index].end(), + to_track_node); + if (it != track2track_map[from_side_index][from_track_index].end()) { + continue; /* the node_id is already in the list, go for the next */ + } + /* Clear, we should add to the list */ + track2track_map[from_side_index][from_track_index].push_back(to_track_node); + } + } + } + } +} + +/************************************************************************ + * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] + * based on the existing routing resources in the General Switch Block (GSB) + * The track_indices is the indices of tracks that the node at from_side and [0..chan_width-1] will drive + * IMPORTANT: the track_indices are the indicies in the GSB context, but not the rr_graph!!! + * We separate the connections into two groups: + * Group 1: the routing tracks start from this GSB + * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) + * Group 2: the routing tracks do not start from this GSB (bypassing wires) + * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) + * but we will check the Switch Block (SB) population of these + * routing segments, and determine which requires connections + * + * CHANY CHANY CHANY CHANY + * [0] [1] [2] [3] + * start yes no yes no + * end +-------------------------+ start Group 1 Group 2 + * no CHANX[0] | TOP | CHANX[0] yes TOP/BOTTOM TOP/BOTTOM + * | | CHANY[0,2] CHANY[1,3] + * yes CHANX[1] | | CHANX[1] no + * | LEFT RIGHT | + * no CHANX[2] | | CHANX[2] yes + * | | + * yes CHANX[3] | BOTTOM | CHANX[3] no + * +-------------------------+ + * CHANY CHANY CHANY CHANY + * [0] [1] [2] [3] + * start yes no yes no + * + * The mapping is done in the following steps: (For each side of the GSB) + * 1. Build a list of tracks that will start from this side + * if a track starts, its xlow/ylow is the same as the x,y of this gsb + * 2. Build a list of tracks on the other sides belonging to Group 1. + * Take the example of RIGHT side, we will collect + * a. tracks that will end at the LEFT side + * b. tracks that will start at the TOP side + * c. tracks that will start at the BOTTOM side + * 3. Apply switch block patterns to Group 1 (SUBSET, UNIVERSAL, WILTON) + * 4. Build a list of tracks on the other sides belonging to Group 1. + * Take the example of RIGHT side, we will collect + * a. tracks that will bypass at the TOP side + * b. tracks that will bypass at the BOTTOM side + * 5. Apply switch block patterns to Group 2 (SUBSET, UNIVERSAL, WILTON) + ***********************************************************************/ +t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& wire_opposite_side, + const std::vector& segment_inf) { + t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ + + /* Categorize tracks into 3 groups: + * (1) tracks will start here + * (2) tracks will end here + * (2) tracks will just pass through the SB */ + t_track_group start_tracks; /* [0..gsb_side][track_indices] */ + t_track_group end_tracks; /* [0..gsb_side][track_indices] */ + t_track_group pass_tracks; /* [0..gsb_side][track_indices] */ + + /* resize to the number of sides */ + start_tracks.resize(rr_gsb.get_num_sides()); + end_tracks.resize(rr_gsb.get_num_sides()); + pass_tracks.resize(rr_gsb.get_num_sides()); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + e_side gsb_side = side_manager.get_side(); + /* Build a list of tracks that will start from this side */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + /* We need to check Switch block population of this track + * The track node will not be considered if there supposed to be no SB at this position + */ + if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, gsb_side, inode, segment_inf)) { + continue; /* skip this node and go to the next */ + } + /* check if this track will start from here */ + enum e_track_status track_status = determine_track_status_of_gsb(rr_graph, rr_gsb, gsb_side, inode); + + switch (track_status) { + case TRACK_START: + /* update starting track list */ + start_tracks[side].push_back(inode); + break; + case TRACK_END: + /* Update end track list */ + end_tracks[side].push_back(inode); + break; + case TRACK_PASS: + /* Update passing track list */ + /* Note that the pass_track should be IN_PORT only !!! */ + if (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, inode)) { + pass_tracks[side].push_back(inode); + } + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid track status!\n"); + exit(1); + } + } + } + + /* Allocate track2track map */ + track2track_map.resize(rr_gsb.get_num_sides()); + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side gsb_side = side_manager.get_side(); + /* allocate track2track_map[gsb_side] */ + track2track_map[side].resize(rr_gsb.get_chan_width(gsb_side)); + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + /* allocate track2track_map[gsb_side][inode] */ + track2track_map[side][inode].clear(); + } + } + + /* For Group 1: we build connections between end_tracks and start_tracks*/ + build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, + true, /* End tracks should always to wired to start tracks */ + end_tracks, start_tracks, + track2track_map); + + /* For Group 2: we build connections between end_tracks and start_tracks*/ + /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks, + * TODO: This can be improved with different patterns! + */ + build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, + sb_subtype, subFs, + wire_opposite_side, /* Pass tracks may not be wired to start tracks */ + pass_tracks, start_tracks, + track2track_map); + + return track2track_map; +} + +/* Build a RRChan Object with the given channel type and coorindators */ +static +RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + const RRGraph& rr_graph, + const ChanNodeDetails& chan_details) { + std::vector chan_rr_nodes; + + /* Create a rr_chan object and check if it is unique in the graph */ + RRChan rr_chan; + + /* Fill the information */ + rr_chan.set_type(chan_type); + + /* Collect rr_nodes for this channel */ + chan_rr_nodes = find_rr_graph_chan_nodes(rr_graph, + chan_coordinate.x(), chan_coordinate.y(), + chan_type); + + /* Reserve */ + /* rr_chan.reserve_node(size_t(chan_width)); */ + + /* Fill the rr_chan */ + for (size_t itrack = 0; itrack < chan_rr_nodes.size(); ++itrack) { + size_t iseg = chan_details.get_track_segment_id(itrack); + rr_chan.add_node(rr_graph, chan_rr_nodes[itrack], RRSegmentId(iseg)); + } + + return rr_chan; +} + +/*********************************************************************** + * Build a General Switch Block (GSB) + * which includes: + * [I] A Switch Box subckt consists of following ports: + * 1. Channel Y [x][y] inputs + * 2. Channel X [x+1][y] inputs + * 3. Channel Y [x][y-1] outputs + * 4. Channel X [x][y] outputs + * 5. Grid[x][y+1] Right side outputs pins + * 6. Grid[x+1][y+1] Left side output pins + * 7. Grid[x+1][y+1] Bottom side output pins + * 8. Grid[x+1][y] Top side output pins + * 9. Grid[x+1][y] Left side output pins + * 10. Grid[x][y] Right side output pins + * 11. Grid[x][y] Top side output pins + * 12. Grid[x][y+1] Bottom side output pins + * + * -------------- -------------- + * | | CBY | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * | | | | + * -------------- -------------- + * ---------- + * ChanX & CBX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * | [x][y] | + * ---------- + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * | | | | + * -------------- -------------- + * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs + * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs + * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs + * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs + * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs + * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs + * + * [II] A X-direction Connection Block [x][y] + * The connection block shares the same routing channel[x][y] with the Switch Block + * We just need to fill the ipin nodes at TOP and BOTTOM sides + * as well as properly fill the ipin_grid_side information + * [III] A Y-direction Connection Block [x][y+1] + * The connection block shares the same routing channel[x][y+1] with the Switch Block + * We just need to fill the ipin nodes at LEFT and RIGHT sides + * as well as properly fill the ipin_grid_side information + ***********************************************************************/ +RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, + const RRGraph& rr_graph, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const vtr::Point& gsb_coordinate) { + /* Create an object to return */ + RRGSB rr_gsb; + + /* Check */ + VTR_ASSERT(gsb_coordinate.x() <= grids.width()); + VTR_ASSERT(gsb_coordinate.y() <= grids.height()); + + /* Coordinator initialization */ + rr_gsb.set_coordinate(gsb_coordinate.x(), gsb_coordinate.y()); + + /* Basic information*/ + rr_gsb.init_num_sides(4); /* Fixed number of sides */ + + /* Find all rr_nodes of channels */ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + /* Local variables inside this for loop */ + SideManager side_manager(side); + vtr::Point coordinate = rr_gsb.get_side_block_coordinate(side_manager.get_side()); + RRChan rr_chan; + std::vector> temp_opin_rr_nodes(2); + enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; + enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ + + /* Build a segment details, where we need the segment ids for building rr_chan + * We do not care starting and ending points here, so set chan_side as NUM_SIDES + */ + ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width.x(), grids.width() - 1, + false, false, segment_inf); + ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width.y(), grids.height() - 1, + false, false, segment_inf); + + switch (side) { + case TOP: /* TOP = 0 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.y() == grids.height() - 1) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details); + chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ + chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x][y+1] RIGHT side outputs pins */ + opin_grid_side[0] = RIGHT; + /* Grid[x+1][y+1] left side outputs pins */ + opin_grid_side[1] = LEFT; + + /* Build the Switch block: opin and opin_grid_side */ + /* Include Grid[x][y+1] RIGHT side outputs pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x(), gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* Include Grid[x+1][y+1] Left side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, + OPIN, opin_grid_side[1]); + + break; + case RIGHT: /* RIGHT = 1 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.x() == grids.width() - 1) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details); + chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ + chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x+1][y+1] BOTTOM side outputs pins */ + opin_grid_side[0] = BOTTOM; + /* Grid[x+1][y] TOP side outputs pins */ + opin_grid_side[1] = TOP; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x+1][y+1] Bottom side output pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* include Grid[x+1][y] Top side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x() + 1, gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + break; + case BOTTOM: /* BOTTOM = 2*/ + /* For the bording, we should take special care */ + if (gsb_coordinate.y() == 0) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details); + chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ + chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x+1][y] LEFT side outputs pins */ + opin_grid_side[0] = LEFT; + /* Grid[x][y] RIGHT side outputs pins */ + opin_grid_side[1] = RIGHT; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x+1][y] Left side output pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x() + 1, gsb_coordinate.y(), + OPIN, opin_grid_side[0]); + /* include Grid[x][y] Right side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x(), gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + break; + case LEFT: /* LEFT = 3 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.x() == 0) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for left: chanx[x][y] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details); + chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ + chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ + + /* Grid[x][y+1] BOTTOM side outputs pins */ + opin_grid_side[0] = BOTTOM; + /* Grid[x][y] TOP side outputs pins */ + opin_grid_side[1] = TOP; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x][y+1] Bottom side outputs pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x(), gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* include Grid[x][y] Top side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x(), gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid side index!\n"); + exit(1); + } + + /* Organize a vector of port direction */ + if (0 < rr_chan.get_chan_width()) { + std::vector rr_chan_dir; + rr_chan_dir.resize(rr_chan.get_chan_width()); + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + /* Identify the directionality, record it in rr_node_direction */ + if (Direction::INC == rr_graph.node_direction(rr_chan.get_node(itrack))) { + rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0]; + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(rr_chan.get_node(itrack))); + rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1]; + } + } + /* Fill chan_rr_nodes */ + rr_gsb.add_chan_node(side_manager.get_side(), rr_chan, rr_chan_dir); + } + + /* Fill opin_rr_nodes */ + /* Copy from temp_opin_rr_node to opin_rr_node */ + for (const RRNodeId& inode : temp_opin_rr_nodes[0]) { + /* Grid[x+1][y+1] Bottom side outputs pins */ + rr_gsb.add_opin_node(inode, side_manager.get_side()); + } + for (const RRNodeId& inode : temp_opin_rr_nodes[1]) { + /* Grid[x+1][y] TOP side outputs pins */ + rr_gsb.add_opin_node(inode, side_manager.get_side()); + } + + /* Clean ipin_rr_nodes */ + /* We do not have any IPIN for a Switch Block */ + rr_gsb.clear_ipin_nodes(side_manager.get_side()); + + /* Clear the temp data */ + temp_opin_rr_nodes[0].clear(); + temp_opin_rr_nodes[1].clear(); + opin_grid_side[0] = NUM_SIDES; + opin_grid_side[1] = NUM_SIDES; + } + + /* Add IPIN nodes from adjacent grids: the 4 grids sitting on the 4 corners of the Switch Block + * + * - The concept of top/bottom side of connection block in GSB domain: + * + * | Grid[x][y+1] | + * | BOTTOM side | + * +-----------------------+ + * | + * v + * +-----------------------+ + * | TOP side | + * | X- Connection Block | + * | BOTTOM side | + * +-----------------------+ + * ^ + * | + * +-----------------------+ + * | TOP side | + * | Grid[x][y] | + * + * - The concept of top/bottom side of connection block in GSB domain: + * + * ---------------+ +---------------------- ... ---------------------+ +---------------- + * Grid[x][y+1] |->| Y- Connection Block Y- Connection Block |<-| Grid[x+1][y+1] + * RIGHT side | | LEFT side ... RIGHT side | | LEFT side + * --------------+ +---------------------- ... ---------------------+ +---------------- + * + */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + size_t ix; + size_t iy; + enum e_side chan_side; + std::vector temp_ipin_rr_nodes; + enum e_side ipin_rr_node_grid_side; + + switch (side) { + case TOP: + /* Consider the routing channel that is connected to the left side of the switch block */ + chan_side = LEFT; + /* The input pins of the routing channel come from the bottom side of Grid[x][y+1] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y() + 1; + ipin_rr_node_grid_side = BOTTOM; + break; + case RIGHT: + /* Consider the routing channel that is connected to the top side of the switch block */ + chan_side = TOP; + /* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */ + ix = rr_gsb.get_sb_x() + 1; + iy = rr_gsb.get_sb_y() + 1; + ipin_rr_node_grid_side = LEFT; + break; + case BOTTOM: + /* Consider the routing channel that is connected to the left side of the switch block */ + chan_side = LEFT; + /* The input pins of the routing channel come from the top side of Grid[x][y] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y(); + ipin_rr_node_grid_side = TOP; + break; + case LEFT: + /* Consider the routing channel that is connected to the top side of the switch block */ + chan_side = TOP; + /* The input pins of the routing channel come from the right side of Grid[x][y+1] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y() + 1; + ipin_rr_node_grid_side = RIGHT; + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid side index!\n"); + exit(1); + } + + /* If there is no channel at this side, we skip ipin_node annotation */ + if (0 == rr_gsb.get_chan_width(chan_side)) { + continue; + } + /* Collect IPIN rr_nodes*/ + temp_ipin_rr_nodes = find_rr_graph_grid_nodes(rr_graph, grids, + ix, iy, IPIN, ipin_rr_node_grid_side); + /* Fill the ipin nodes of RRGSB */ + for (const RRNodeId& inode : temp_ipin_rr_nodes) { + rr_gsb.add_ipin_node(inode, side_manager.get_side()); + } + /* Clear the temp data */ + temp_ipin_rr_nodes.clear(); + } + + return rr_gsb; +} + +/************************************************************************ + * Create edges for each rr_node of a General Switch Blocks (GSB): + * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) + * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) + * 3. create edges between OPINs and IPINs (direct-connections) + ***********************************************************************/ +void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, + const RRGSB& rr_gsb, + const t_track2pin_map& track2ipin_map, + const t_pin2track_map& opin2track_map, + const t_track2track_map& track2track_map, + const vtr::vector& rr_node_driver_switches) { + + /* Walk through each sides */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side gsb_side = side_manager.get_side(); + + /* Find OPINs */ + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); + + /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ + /* add edges to the opin_node */ + for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) { + rr_graph.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]); + } + } + + /* Find CHANX or CHANY */ + /* For TRACKs to IPINs, we only care LEFT and TOP sides + * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs + */ + if ( (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY)) ) { + /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { + rr_graph.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]); + } + } + } + + /* 3. create edges between CHANX|CHANY and CHANX|CHANY, using track2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { + rr_graph.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]); + } + } + } +} + +/************************************************************************ + * Build track2ipin_map for an IPIN + * 1. build a list of routing tracks which are allowed for connections + * We will check the Connection Block (CB) population of each routing track. + * By comparing current chan_y - ylow, we can determine if a CB connection + * is required for each routing track + * 2. Divide the routing tracks by segment types, so that we can balance + * the connections between IPINs and different types of routing tracks. + * 3. Scale the Fc of each pin to the actual number of routing tracks + * actual_Fc = (int) Fc * num_tracks / chan_width + ***********************************************************************/ +static +void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& ipin_side, + const size_t& ipin_node_id, + const std::vector& Fc, + const size_t& offset, + const std::vector& segment_inf, + t_track2pin_map& track2ipin_map) { + /* Get a list of segment_ids*/ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + std::vector seg_list = rr_gsb.get_chan_segment_ids(chan_side); + size_t chan_width = rr_gsb.get_chan_width(chan_side); + SideManager ipin_side_manager(ipin_side); + const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, ipin_node_id); + + for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { + /* Get a list of node that have the segment id */ + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); + /* Refine the track_list: keep those will have connection blocks in the GSB */ + std::vector actual_track_list; + for (size_t inode = 0; inode < track_list.size(); ++inode) { + /* Check if tracks allow connection blocks in the GSB*/ + if (false == is_gsb_in_track_cb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) { + continue; /* Bypass condition */ + } + /* Push the node to actual_track_list */ + actual_track_list.push_back(track_list[inode]); + } + /* Check the actual track list */ + VTR_ASSERT(0 == actual_track_list.size() % 2); + + /* Scale Fc */ + int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); + /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ + actual_Fc = std::max(1, actual_Fc); + /* Compute the step between two connection from this IPIN to tracks: + * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + */ + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); + /* Make sure step should be at least 2 */ + track_step = std::max(1, (int)track_step); + /* Adapt offset to the range of actual_track_list */ + size_t actual_offset = offset % actual_track_list.size(); + /* rotate the track list by an offset */ + if (0 < actual_offset) { + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } + + /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ + int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ + for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) { + /* Update pin2track map */ + size_t chan_side_index = chan_side_manager.to_size_t(); + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + /* track_index may exceed the chan_width(), adapt it */ + size_t track_index = actual_track_list[actual_itrack] % chan_width; + + track2ipin_map[chan_side_index][track_index].push_back(ipin_node); + + /* track_index may exceed the chan_width(), adapt it */ + track_index = (actual_track_list[actual_itrack] + 1) % chan_width; + + track2ipin_map[chan_side_index][track_index].push_back(ipin_node); + + track_cnt += 2; + } + + /* Ensure the number of tracks is similar to Fc */ + /* Give a warning if Fc is < track_cnt */ + /* + if (actual_Fc != track_cnt) { + vpr_printf(TIO_MESSAGE_INFO, + "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); + } + */ + } +} + +/************************************************************************ + * Build opin2track_map for an OPIN + * 1. build a list of routing tracks which are allowed for connections + * We will check the Switch Block (SB) population of each routing track. + * By comparing current chan_y - ylow, we can determine if a SB connection + * is required for each routing track + * 2. Divide the routing tracks by segment types, so that we can balance + * the connections between OPINs and different types of routing tracks. + * 3. Scale the Fc of each pin to the actual number of routing tracks + * actual_Fc = (int) Fc * num_tracks / chan_width + ***********************************************************************/ +static +void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& opin_side, + const size_t& opin_node_id, + const std::vector& Fc, + const size_t& offset, + const std::vector& segment_inf, + t_pin2track_map& opin2track_map) { + /* Get a list of segment_ids*/ + std::vector seg_list = rr_gsb.get_chan_segment_ids(opin_side); + enum e_side chan_side = opin_side; + size_t chan_width = rr_gsb.get_chan_width(chan_side); + SideManager opin_side_manager(opin_side); + + for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { + /* Get a list of node that have the segment id */ + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); + /* Refine the track_list: keep those will have connection blocks in the GSB */ + std::vector actual_track_list; + for (size_t inode = 0; inode < track_list.size(); ++inode) { + /* Check if tracks allow connection blocks in the GSB*/ + if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, chan_side, + track_list[inode], segment_inf)) { + continue; /* Bypass condition */ + } + if (TRACK_START != determine_track_status_of_gsb(rr_graph, rr_gsb, chan_side, track_list[inode])) { + continue; /* Bypass condition */ + } + /* Push the node to actual_track_list */ + actual_track_list.push_back(track_list[inode]); + } + + /* Go the next segment if offset is zero or actual_track_list is empty */ + if (0 == actual_track_list.size()) { + continue; + } + + /* Scale Fc */ + int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); + /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ + actual_Fc = std::max(1, actual_Fc); + /* Compute the step between two connection from this IPIN to tracks: + * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + */ + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); + /* Track step mush be a multiple of 2!!!*/ + /* Make sure step should be at least 1 */ + track_step = std::max(1, (int)track_step); + /* Adapt offset to the range of actual_track_list */ + size_t actual_offset = offset % actual_track_list.size(); + + /* No need to rotate if offset is zero */ + if (0 < actual_offset) { + /* rotate the track list by an offset */ + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } + + /* Assign tracks */ + int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ + for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { + /* Update pin2track map */ + size_t opin_side_index = opin_side_manager.to_size_t(); + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + size_t track_index = actual_track_list[actual_itrack]; + const RRNodeId& track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index); + opin2track_map[opin_side_index][opin_node_id].push_back(track_rr_node_index); + /* update track counter */ + track_cnt++; + /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. + * So I comment it. And we just make sure its track_cnt >= actual_Fc + if (actual_Fc == track_cnt) { + break; + } + */ + } + + /* Ensure the number of tracks is similar to Fc */ + /* Give a warning if Fc is < track_cnt */ + /* + if (actual_Fc != track_cnt) { + vpr_printf(TIO_MESSAGE_INFO, + "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + opin_node_id, track_cnt, actual_Fc); + } + */ + } +} + + +/************************************************************************ + * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] + * based on the existing routing resources in the General Switch Block (GSB) + * This function supports both X-directional and Y-directional tracks + * The mapping is done in the following steps: + * 1. Build ipin_to_track_map[gsb_side][0..num_ipin_nodes-1][track_indices] + * For each IPIN, we ensure at least one connection to the tracks. + * Then, we assign IPINs to tracks evenly while satisfying the actual_Fc + * 2. Convert the ipin_to_track_map to track_to_ipin_map + ***********************************************************************/ +t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_in) { + t_track2pin_map track2ipin_map; + /* Resize the matrix */ + track2ipin_map.resize(rr_gsb.get_num_sides()); + + /* offset counter: it aims to balance the track-to-IPIN for each connection block */ + size_t offset_size = 0; + std::vector offset; + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side ipin_side = side_manager.get_side(); + /* Get the chan_side */ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + /* resize offset to the maximum chan_side*/ + offset_size = std::max(offset_size, chan_side_manager.to_size_t() + 1); + } + /* Initial offset */ + offset.resize(offset_size); + offset.assign(offset.size(), 0); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side ipin_side = side_manager.get_side(); + /* Get the chan_side */ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ + /* Get channel width and resize the matrix */ + size_t chan_width = rr_gsb.get_chan_width(chan_side); + track2ipin_map[chan_side_manager.to_size_t()].resize(chan_width); + /* Find the ipin/opin nodes */ + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { + const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); + /* Skip EMPTY type */ + if (true == is_empty_type(grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type)) { + continue; + } + + int grid_type_index = grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type->index; + /* Get Fc of the ipin */ + /* skip Fc = 0 or unintialized, those pins are in the */ + bool skip_conn2track = true; + std::vector ipin_Fc_out; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)][iseg]; + ipin_Fc_out.push_back(ipin_Fc); + if (0 != ipin_Fc) { + skip_conn2track = false; + continue; + } + } + + if (true == skip_conn2track) { + continue; + } + + VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size()); + + /* Build track2ipin_map for this IPIN */ + build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[chan_side_manager.to_size_t()], + segment_inf, track2ipin_map); + /* update offset */ + offset[chan_side_manager.to_size_t()] += 2; + //printf("offset[%lu]=%lu\n", chan_side_manager.to_size_t(), offset[chan_side_manager.to_size_t()]); + } + } + + return track2ipin_map; +} + +/************************************************************************ + * Build the opin_to_track_map[gsb_side][0..num_opin_nodes-1][track_indices] + * based on the existing routing resources in the General Switch Block (GSB) + * This function supports both X-directional and Y-directional tracks + * The mapping is done in the following steps: + * 1. Build a list of routing tracks whose starting points locate at this GSB + * (xlow - gsb_x == 0) + * 2. Divide the routing tracks by segment types, so that we can balance + * the connections between OPINs and different types of routing tracks. + * 3. Scale the Fc of each pin to the actual number of routing tracks + * actual_Fc = (int) Fc * num_tracks / chan_width + ***********************************************************************/ +t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_out) { + t_pin2track_map opin2track_map; + /* Resize the matrix */ + opin2track_map.resize(rr_gsb.get_num_sides()); + + /* offset counter: it aims to balance the OPIN-to-track for each switch block */ + std::vector offset; + /* Get the chan_side: which is the same as the opin side */ + offset.resize(rr_gsb.get_num_sides()); + /* Initial offset */ + offset.assign(offset.size(), 0); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side opin_side = side_manager.get_side(); + /* Get the chan_side */ + /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ + /* Get channel width and resize the matrix */ + size_t num_opin_nodes = rr_gsb.get_num_opin_nodes(opin_side); + opin2track_map[side].resize(num_opin_nodes); + /* Find the ipin/opin nodes */ + for (size_t inode = 0; inode < num_opin_nodes; ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode); + /* Skip EMPTY type */ + if (true == is_empty_type(grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type)) { + continue; + } + int grid_type_index = grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type->index; + + /* Get Fc of the ipin */ + /* skip Fc = 0 or unintialized, those pins are in the */ + bool skip_conn2track = true; + std::vector opin_Fc_out; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)][iseg]; + opin_Fc_out.push_back(opin_Fc); + if (0 != opin_Fc) { + skip_conn2track = false; + continue; + } + } + + if (true == skip_conn2track) { + continue; + } + VTR_ASSERT(opin_Fc_out.size() == segment_inf.size()); + + /* Build track2ipin_map for this IPIN */ + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); + /* update offset: aim to rotate starting tracks by 1*/ + offset[side_manager.to_size_t()] += 1; + } + + /* Check: + * 1. We want to ensure that each OPIN will drive at least one track + * 2. We want to ensure that each track will be driven by at least 1 OPIN */ + } + + return opin2track_map; +} + +/************************************************************************ + * Add all direct clb-pin-to-clb-pin edges to given opin + ***********************************************************************/ +void build_direct_connections_for_one_gsb(RRGraph& rr_graph, + const DeviceGrid& grids, + const vtr::Point& from_grid_coordinate, + const RRSwitchId& delayless_switch, + const std::vector& directs, + const std::vector& clb_to_clb_directs) { + VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); + + const t_grid_tile& from_grid = grids[from_grid_coordinate.x()][from_grid_coordinate.y()]; + t_physical_tile_type_ptr grid_type = from_grid.type; + + /* Iterate through all direct connections */ + for (size_t i = 0; i < directs.size(); ++i) { + /* Bypass unmatched direct clb-to-clb connections */ + if (grid_type != clb_to_clb_directs[i].from_clb_type) { + continue; + } + + /* This opin is specified to connect directly to an ipin, + * now compute which ipin to connect to + */ + vtr::Point to_grid_coordinate(from_grid_coordinate.x() + directs[i].x_offset, + from_grid_coordinate.y() + directs[i].y_offset); + + /* Bypass unmatched direct clb-to-clb connections */ + t_physical_tile_type_ptr to_grid_type = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].type; + /* Check if to_grid if the same grid */ + if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { + continue; + } + + bool swap; + int max_index, min_index; + /* Compute index of opin with regards to given pins */ + if ( clb_to_clb_directs[i].from_clb_pin_start_index + > clb_to_clb_directs[i].from_clb_pin_end_index) { + swap = true; + max_index = clb_to_clb_directs[i].from_clb_pin_start_index; + min_index = clb_to_clb_directs[i].from_clb_pin_end_index; + } else { + swap = false; + min_index = clb_to_clb_directs[i].from_clb_pin_start_index; + max_index = clb_to_clb_directs[i].from_clb_pin_end_index; + } + + /* get every opin in the range */ + for (int opin = min_index; opin <= max_index; ++opin) { + int offset = opin - min_index; + + if ( (to_grid_coordinate.x() < grids.width() - 1) + && (to_grid_coordinate.y() < grids.height() - 1) ) { + int ipin = OPEN; + if ( clb_to_clb_directs[i].to_clb_pin_start_index + > clb_to_clb_directs[i].to_clb_pin_end_index) { + if (true == swap) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; + } + } else { + if(true == swap) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; + } + } + + /* Get the pin index in the rr_graph */ + int from_grid_width_ofs = from_grid.width_offset; + int from_grid_height_ofs = from_grid.height_offset; + int to_grid_width_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].width_offset; + int to_grid_height_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].height_offset; + + /* Find the side of grid pins, the pin location should be unique! + * Pin location is required by searching a node in rr_graph + */ + std::vector opin_grid_side = find_grid_pin_sides(from_grid, opin); + VTR_ASSERT(1 == opin_grid_side.size()); + + std::vector ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin); + VTR_ASSERT(1 == ipin_grid_side.size()); + + const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs, + from_grid_coordinate.y() - from_grid_height_ofs, + OPIN, opin, opin_grid_side[0]); + const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs, + to_grid_coordinate.y() - to_grid_height_ofs, + IPIN, ipin, ipin_grid_side[0]); + /* + VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", + from_grid_coordinate.x() - from_grid_width_ofs, + from_grid_coordinate.y() - from_grid_height_ofs, + opin, SIDE_STRING[opin_grid_side[0]], + to_grid_coordinate.x() - to_grid_width_ofs, + to_grid_coordinate.y() - to_grid_height_ofs, + ipin, SIDE_STRING[ipin_grid_side[0]]); + */ + + /* add edges to the opin_node */ + rr_graph.create_edge(opin_node_id, ipin_node_id, + delayless_switch); + } + } + } +} + + +} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h new file mode 100755 index 00000000000..adf6118fbbe --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -0,0 +1,80 @@ +#ifndef TILEABLE_RR_GRAPH_GSB_H +#define TILEABLE_RR_GRAPH_GSB_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "vtr_vector.h" +#include "vtr_geometry.h" + +#include "physical_types.h" +#include "device_grid.h" + +#include "rr_gsb.h" +#include "rr_graph_obj.h" +#include "clb2clb_directs.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Data stuctures related to the functions + ***********************************************************************/ +typedef std::vector>> t_track2track_map; +typedef std::vector>> t_track2pin_map; +typedef std::vector>> t_pin2track_map; + +/************************************************************************ + * Functions + ***********************************************************************/ +t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& wire_opposite_side, + const std::vector& segment_inf); + +RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, + const RRGraph& rr_graph, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const vtr::Point& gsb_coordinate); + +void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, + const RRGSB& rr_gsb, + const t_track2pin_map& track2ipin_map, + const t_pin2track_map& opin2track_map, + const t_track2track_map& track2track_map, + const vtr::vector& rr_node_driver_switches); + +t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_in); + +t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_out); + +void build_direct_connections_for_one_gsb(RRGraph& rr_graph, + const DeviceGrid& grids, + const vtr::Point& from_grid_coordinate, + const RRSwitchId& delayless_switch, + const std::vector& directs, + const std::vector& clb_to_clb_directs); + +} /* end namespace openfpga */ + +#endif + diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp new file mode 100644 index 00000000000..89a0e264904 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -0,0 +1,1061 @@ +/************************************************************************ + * This file contains functions that are used to allocate nodes + * for the tileable routing resource graph builder + ***********************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_geometry.h" + +/* Headers from openfpgautil library */ +#include "openfpga_side_manager.h" + +#include "vpr_types.h" +#include "vpr_utils.h" + +#include "rr_node.h" + +#include "rr_graph_builder_utils.h" +#include "rr_graph_builder.h" +#include "tileable_chan_details_builder.h" +#include "tileable_rr_graph_node_builder.h" +#include "rr_rc_data.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/************************************************************************ + * Find the number output pins by considering all the grid + ***********************************************************************/ +static +size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, + const t_rr_type& node_type) { + size_t num_grid_rr_nodes = 0; + + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ( (0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset) ) { + continue; + } + + enum e_side io_side = NUM_SIDES; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids[ix][iy].type)) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + vtr::Point grid_coordinate(ix, iy); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + } + + switch (node_type) { + case OPIN: + /* get the number of OPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); + break; + case IPIN: + /* get the number of IPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); + break; + case SOURCE: + /* SOURCE: number of classes whose type is DRIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER); + break; + case SINK: + /* SINK: number of classes whose type is RECEIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER); + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid routing resource node!\n"); + exit(1); + } + } + } + + return num_grid_rr_nodes; +} + +/************************************************************************ + * For X-direction Channel: CHANX + * We pair each x-direction routing channel to the grid below it + * as they share the same coordinate + * + * As such, the range of CHANX coordinate starts from x = 1, y = 0 + * which is the grid (I/O) at the left bottom of the fabric + * + * As such, the range of CHANX coordinate ends to x = width - 2, y = height - 2 + * which is the grid at the top right of the core fabric + * Note that the I/O ring is + * + * TOP SIDE OF FPGA + * + * +-------------+ +-------------+ +---------------------+ + * | Grid | | Grid | ... | Grid | + * | [1][0] | | [2][0] | | [width-2][height-1] | + * +-------------+ +-------------+ +---------------------+ + * + * +-------------+ +-------------+ +---------------------+ + * | X-Channel | | X-Channel | ... | X-Channel | + * | [1][0] | | [2][0] | | [width-2][height-2] | + * +-------------+ +-------------+ +---------------------+ + * + * +-------------+ +-------------+ +---------------------+ + * | Grid | | Grid | ... | Grid | + * | [1][0] | | [2][0] | | [width-2][height-2] | + * +-------------+ +-------------+ +---------------------+ + * + * ... ... ... + * + * +-------------+ +-------------+ +--------------+ + * | X-Channel | | X-Channel | ... | X-Channel | + * | [1][1] | | [2][1] | | [width-2][1] | + * +-------------+ +-------------+ +--------------+ + * + * LEFT +-------------+ +-------------+ +--------------+ RIGHT + * SIDE | Grid | | Grid | ... | Grid | SIDE + * GRID | [1][1] | | [2][1] | | [width-2][1] | GRID + * +-------------+ +-------------+ +--------------+ + * + * +-------------+ +-------------+ +--------------+ + * | X-Channel | | X-Channel | ... | X-Channel | + * | [1][0] | | [2][0] | | [width-2][0] | + * +-------------+ +-------------+ +--------------+ + * + * +-------------+ +-------------+ +--------------+ + * | Grid | | Grid | ... | Grid | + * | [1][0] | | [2][0] | | [width-2][0] | + * +-------------+ +-------------+ +--------------+ + * + * BOTTOM SIDE OF FPGA + * + * The figure above describe how the X-direction routing channels are + * organized in a homogeneous FPGA fabric + * Note that we talk about general-purpose uni-directional routing architecture here + * It means that a routing track may span across multiple grids + * However, the hard limits are as follows + * All the routing tracks will start at the most LEFT routing channel + * All the routing tracks will end at the most RIGHT routing channel + * + * Things will become more complicated in terms of track starting and end + * in the context of heterogeneous FPGAs + * We may have a grid which span multiple column and rows, as exemplified in the figure below + * In such case, + * all the routing tracks [x-1][y] at the left side of the grid [x][y] are forced to end + * all the routing tracks [x+2][y] at the right side of the grid [x][y] are forced to start + * And there are no routing tracks inside the grid[x][y] + * It means that X-channel [x][y] & [x+1][y] will no exist + * + * +------------+ +-------------+ +-------------+ +--------------+ + * | X-Channel | | X-Channel | | X-Channel | | X-Channel | + * | [x-1][y+2] | | [x][y+2] | | [x+1][y+2] | | [x+2][y+2] | + * +------------+ +-------------+ +-------------+ +--------------+ + * + * +------------+ +-----------------------------------+ +--------------+ + * | Grid | | | | Grid | + * | [x-1][y+1] | | | | [x+2][y+1] | + * +------------+ | | +--------------+ + * | | + * +------------+ | | +--------------+ + * | X-channel | | Grid | | X-Channel | + * | [x-1][y] | | [x][y] - [x+1][y+1] | | [x+2][y] | + * +------------+ | | +--------------+ + * | | + * +------------+ | | +--------------+ + * | Grid | | | | Grid | + * | [x-1][y] | | | | [x+2][y] | + * +------------+ +-----------------------------------+ +--------------+ + * + * + * + ***********************************************************************/ +static +size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + size_t num_chanx_rr_nodes = 0; + + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ( (false == through_channel) + && (false == is_chanx_exist(grids, chanx_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when + * - the routing channel touch the RIGHT side a heterogeneous block + * - the routing channel touch the LEFT side of FPGA + */ + if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_start = true; + } + + /* All the tracks have to end when + * - the routing channel touch the LEFT side a heterogeneous block + * - the routing channel touch the RIGHT side of FPGA + */ + if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_end = true; + } + + /* Evaluate if the routing channel locates in the middle of a grid */ + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(Direction::DEC); + } + } + + return num_chanx_rr_nodes; +} + +/************************************************************************ + * Estimate the number of CHANY rr_nodes for Y-direction routing channels + * The technical rationale is very similar to the X-direction routing channel + * Refer to the detailed explanation there + ***********************************************************************/ +static +size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + size_t num_chany_rr_nodes = 0; + + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Point chany_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ( (false == through_channel) + && (false == is_chany_exist(grids, chany_coord))) { + continue; + } + + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when + * - the routing channel touch the TOP side a heterogeneous block + * - the routing channel touch the BOTTOM side of FPGA + */ + if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_start = true; + } + + /* All the tracks have to end when + * - the routing channel touch the BOTTOM side a heterogeneous block + * - the routing channel touch the TOP side of FPGA + */ + if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_ending_tracks(Direction::DEC); + } + } + + return num_chany_rr_nodes; +} + +/************************************************************************ + * Estimate the number of nodes by each type in a routing resource graph + ***********************************************************************/ +static +std::vector estimate_num_rr_nodes(const DeviceGrid& grids, + const vtr::Point& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + + /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ + std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); + + /** + * 1 Find number of rr nodes related to grids + */ + num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); + num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); + num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); + num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); + + /** + * 2. Assign the segments for each routing channel, + * To be specific, for each routing track, we assign a routing segment. + * The assignment is subject to users' specifications, such as + * a. length of each type of segment + * b. frequency of each type of segment. + * c. routing channel width + * + * SPECIAL for fringes: + * All segments will start and ends with no exception + * + * IMPORTANT: we should be aware that channel width maybe different + * in X-direction and Y-direction channels!!! + * So we will load segment details for different channels + */ + num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, + chan_width.x(), + segment_infs, + through_channel); + num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, + chan_width.y(), + segment_infs, + through_channel); + + return num_rr_nodes_per_type; +} + +/************************************************************************ + * Allocate rr_nodes to a rr_graph object + * This function just allocate the memory and ensure its efficiency + * It will NOT fill detailed information for each node!!! + * + * Note: ensure that there are NO nodes in the rr_graph + ***********************************************************************/ +void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const vtr::Point& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); + + std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + chan_width, + segment_infs, + through_channel); + + /* Reserve the number of node to be memory efficient */ + size_t num_nodes = 0; + for (const size_t& num_node_per_type : num_rr_nodes_per_type) { + num_nodes += num_node_per_type; + } + + rr_graph_builder.reserve_nodes(num_nodes); + + rr_node_driver_switches.reserve(num_nodes); +} + +/************************************************************************ + * Configure OPIN rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, ptc_num (pin_num), + * + * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! + ***********************************************************************/ +static +void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Walk through the width height of each grid, + * get pins and configure the rr_nodes + */ + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + /* Walk through sides */ + for (e_side side : SIDES) { + SideManager side_manager(side); + /* skip unwanted sides */ + if ( (true == is_io_type(cur_grid.type)) + && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side) ) { + continue; + } + /* Find OPINs */ + /* Configure pins by pins */ + std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), + width, height); + for (const int& pin_num : opin_list) { + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, OPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of loading OPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ + +} + +/************************************************************************ + * Configure IPIN rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, ptc_num (pin_num), + * + * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! + ***********************************************************************/ +static +void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& wire_to_ipin_switch) { + SideManager io_side_manager(io_side); + + /* Walk through the width and height of each grid, + * get pins and configure the rr_nodes + */ + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + /* Walk through sides */ + for (e_side side : SIDES) { + SideManager side_manager(side); + /* skip unwanted sides */ + if ( (true == is_io_type(cur_grid.type)) + && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side) ) { + continue; + } + + /* Find IPINs */ + /* Configure pins by pins */ + std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); + for (const int& pin_num : ipin_list) { + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, IPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(wire_to_ipin_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of loading IPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ +} + +/************************************************************************ + * Configure SOURCE rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, ptc_num (pin_num), + * + * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! + ***********************************************************************/ +static +void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Set a SOURCE rr_node for each DRIVER class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (DRIVER != cur_grid.type->class_inf[iclass].type) { + continue; + } + + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); + + rr_graph_builder.set_node_capacity(node, 1); + + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + + /* cost index is a FIXED value for SOURCE */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of class enumeration */ +} + +/************************************************************************ + * Configure SINK rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, ptc_num (pin_num), + * + * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! + ***********************************************************************/ +static +void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Set a SINK rr_node for each RECEIVER class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (RECEIVER != cur_grid.type->class_inf[iclass].type) { + continue; + } + + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); + + rr_graph_builder.set_node_capacity(node, 1); + + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + + /* cost index is a FIXED value for SINK */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of class enumeration */ +} + +/************************************************************************ + * Create all the rr_nodes for grids + ***********************************************************************/ +static +void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch) { + + for (size_t iy = 0; iy < grids.height(); ++iy) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + + /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ + if ( (0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset) ) { + continue; + } + + vtr::Point grid_coordinate(ix, iy); + enum e_side io_side = NUM_SIDES; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids[ix][iy].type)) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + } + + /* Configure source rr_nodes for this grid */ + load_one_grid_source_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure sink rr_nodes for this grid */ + load_one_grid_sink_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure opin rr_nodes for this grid */ + load_one_grid_opin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure ipin rr_nodes for this grid */ + load_one_grid_ipin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + wire_to_ipin_switch); + + } + } +} + +/************************************************************************ + * Initialize the basic information of routing track rr_nodes + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction + ***********************************************************************/ +static +void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + ChanNodeDetails& chan_details, + const std::vector& segment_infs, + const int& cost_index_offset) { + /* Check each node_id(potential ptc_num) in the channel : + * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num + * If this is a ending point, we set xhigh/yhigh and track_ids + * For other nodes, we set changes in track_ids + */ + for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { + /* For INC direction, a starting point requires a new chan rr_node */ + if ( ( (true == chan_details.is_track_start(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack)) ) + /* For DEC direction, an ending point requires a new chan rr_node */ + || + ( (true == chan_details.is_track_end(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)) ) ) { + + /* Create a new chan rr_node */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); + + rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); + rr_graph_builder.set_node_track_num(node, itrack); + rr_node_track_ids[node].push_back(itrack); + + rr_graph_builder.set_node_capacity(node, 1); + + /* assign switch id */ + size_t seg_id = chan_details.get_track_segment_id(itrack); + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); + + /* Update chan_details with node_id */ + chan_details.set_track_node_id(itrack, size_t(node)); + + /* cost index depends on the segment index */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_id)); + /* Finish here, go to next */ + } + + /* For INC direction, an ending point requires an update on xhigh and yhigh */ + if ( ( (true == chan_details.is_track_end(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack)) ) + || + /* For DEC direction, an starting point requires an update on xlow and ylow */ + ( (true == chan_details.is_track_start(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)) ) ) { + + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + + /* set xhigh/yhigh and push changes to track_ids */ + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ + if ( (rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) + || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id)) ) { + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.set_node_track_num(rr_node_id, itrack); + } + /* Finish here, go to next */ + } + + /* Finish processing starting and ending tracks */ + if ( (true == chan_details.is_track_start(itrack)) + || (true == chan_details.is_track_end(itrack)) ) { + /* Finish here, go to next */ + continue; + } + + /* For other nodes, we get the node_id and just update track_ids */ + /* Ensure those nodes are neither starting nor ending points */ + VTR_ASSERT( (false == chan_details.is_track_start(itrack)) + && (false == chan_details.is_track_end(itrack)) ); + + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + + /* Deposit xhigh and yhigh using the current chan_coordinate + * We will update when this track ends + */ + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Update track_ids */ + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.set_node_track_num(rr_node_id, itrack); + /* Finish here, go to next */ + } +} + +/************************************************************************ + * Initialize the basic information of X-channel rr_nodes: + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction + * grid_info : pb_graph_pin + ***********************************************************************/ +static +void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + + /* For X-direction Channel: CHANX */ + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ( (false == through_channel) + && (false == is_chanx_exist(grids, chanx_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when + * - the routing channel touch the RIGHT side a heterogeneous block + * - the routing channel touch the LEFT side of FPGA + */ + if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_start = true; + } + + /* All the tracks have to end when + * - the routing channel touch the LEFT side a heterogeneous block + * - the routing channel touch the RIGHT side of FPGA + */ + if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chanx */ + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction + */ + ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, + false, false, segment_infs); + chanx_details_tt.set_track_node_ids(track_node_ids); + + /* TODO: + * Do NOT rotate the tracks when the routing channel + * locates inside a multi-height and multi-width grid + * Let the routing channel passing through the grid (if through channel is allowed!) + * An example: + * + * +------------------------------ + * | | + * | Grid | + * track0 ----->+-----------------------------+----> track0 + * | | + */ + if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { + /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ + /* For INC_DIRECTION, we use clockwise rotation + * node_id A ----> -----> node_id D + * node_id B ----> / ----> node_id A + * node_id C ----> / ----> node_id B + * node_id D ----> ----> node_id C + */ + chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation + * node_id A <----- <----- node_id B + * node_id B <----- \ <----- node_id C + * node_id C <----- \ <----- node_id D + * node_id D <----- <----- node_id A + */ + chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chanx_details_tt.get_track_node_ids(); + chanx_details.set_track_node_ids(track_node_ids); + } + + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + chanx_coord, CHANX, + chanx_details, + segment_infs, + CHANX_COST_INDEX_START); + /* Get a copy of node_ids */ + track_node_ids = chanx_details.get_track_node_ids(); + } + } +} + +/************************************************************************ + * Initialize the basic information of Y-channel rr_nodes: + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction + ***********************************************************************/ +static +void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + + /* For Y-direction Channel: CHANY */ + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Point chany_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ( (false == through_channel) + && (false == is_chany_exist(grids, chany_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when + * - the routing channel touch the TOP side a heterogeneous block + * - the routing channel touch the BOTTOM side of FPGA + */ + if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_start = true; + } + + /* All the tracks have to end when + * - the routing channel touch the BOTTOM side a heterogeneous block + * - the routing channel touch the TOP side of FPGA + */ + if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chany + * This will not be applied when the routing channel is cut off (force to start) + */ + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction + */ + ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, + false, false, segment_infs); + + chany_details_tt.set_track_node_ids(track_node_ids); + + /* TODO: + * Do NOT rotate the tracks when the routing channel + * locates inside a multi-height and multi-width grid + * Let the routing channel passing through the grid (if through channel is allowed!) + * An example: + * + * +------------------------------ + * | | + * | Grid | + * track0 ----->+-----------------------------+----> track0 + * | | + * we should rotate only once at the bottom side of a grid + */ + if (true == is_chany_exist(grids, chany_coord, through_channel)) { + /* Rotate the chany_details by an offset of 1*/ + /* For INC_DIRECTION, we use clockwise rotation + * node_id A ----> -----> node_id D + * node_id B ----> / ----> node_id A + * node_id C ----> / ----> node_id B + * node_id D ----> ----> node_id C + */ + chany_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation + * node_id A <----- <----- node_id B + * node_id B <----- \ <----- node_id C + * node_id C <----- \ <----- node_id D + * node_id D <----- <----- node_id A + */ + chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chany_details_tt.get_track_node_ids(); + chany_details.set_track_node_ids(track_node_ids); + } + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + chany_coord, CHANY, + chany_details, + segment_infs, + CHANX_COST_INDEX_START + segment_infs.size()); + /* Get a copy of node_ids */ + track_node_ids = chany_details.get_track_node_ids(); + } + } +} + +/************************************************************************ + * Reverse the track_ids of CHANX and CHANY nodes in DEC_DIRECTION + * This is required as the track ids are allocated in the sequence + * of incrementing x and y + * However, DEC direction routing tracks should have a reversed sequence in + * track ids + ***********************************************************************/ +static +void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, + std::map>& rr_node_track_ids) { + // this should call rr_graph_view to do the job + +for (auto& node : rr_graph.nodes()) { + /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ + if ( (CHANX != rr_graph.node_type(node)) + && (CHANY != rr_graph.node_type(node)) ) { + continue; + } + /* Reach here, we must have a node of CHANX or CHANY */ + if (Direction::DEC != rr_graph.node_direction(node)) { + continue; + } + std::reverse(rr_node_track_ids[node].begin(), + rr_node_track_ids[node].end() ); + } +} + +/************************************************************************ + * Create all the rr_nodes covering both grids and routing channels + ***********************************************************************/ +void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const vtr::Point& chan_width, + const std::vector& segment_infs, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch, + const bool& through_channel) { + load_grid_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grids, + wire_to_ipin_switch, + delayless_switch); + + load_chanx_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + chan_width.x(), + segment_infs, + through_channel); + + load_chany_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + chan_width.y(), + segment_infs, + through_channel); + + reverse_dec_chan_rr_node_track_ids(rr_graph, + rr_node_track_ids); + +} + +} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h new file mode 100644 index 00000000000..1e90fc2feda --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -0,0 +1,47 @@ +#ifndef TILEABLE_RR_GRAPH_NODE_BUILDER_H +#define TILEABLE_RR_GRAPH_NODE_BUILDER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_geometry.h" + +/* Headers from readarch library */ +#include "physical_types.h" + +/* Headers from vpr library */ +#include "rr_graph_obj.h" +#include "device_grid.h" +#include "rr_graph_view.h" +#include "rr_graph_builder.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, + vtr::vector& driver_switches, + const DeviceGrid& grids, + const vtr::Point& chan_width, + const std::vector& segment_infs, + const bool& through_channel); + +void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const vtr::Point& chan_width, + const std::vector& segment_infs, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch, + const bool& through_channel); + + +} /* end namespace openfpga */ + +#endif From 619caea32c36e087d620c0b6aba64455369edc70 Mon Sep 17 00:00:00 2001 From: taoli4rs Date: Tue, 26 Jul 2022 12:54:51 -0700 Subject: [PATCH 003/453] Fix format issue. --- .../tileable_rr_graph/chan_node_details.cpp | 355 ++- .../openfpga_rr_graph_utils.cpp | 178 +- vpr/src/tileable_rr_graph/rr_chan.cpp | 252 +- .../rr_graph_builder_utils.cpp | 477 ++-- vpr/src/tileable_rr_graph/rr_gsb.cpp | 1523 ++++++------ .../tileable_chan_details_builder.cpp | 254 +-- .../tileable_rr_graph_builder.cpp | 350 +-- .../tileable_rr_graph_edge_builder.cpp | 219 +- .../tileable_rr_graph_edge_builder.h | 5 - .../tileable_rr_graph_gsb.cpp | 2031 ++++++++--------- .../tileable_rr_graph_node_builder.cpp | 1297 ++++++----- .../tileable_rr_graph_node_builder.h | 13 +- 12 files changed, 3445 insertions(+), 3509 deletions(-) diff --git a/vpr/src/tileable_rr_graph/chan_node_details.cpp b/vpr/src/tileable_rr_graph/chan_node_details.cpp index 6f0f38e820c..3da5f2f29de 100644 --- a/vpr/src/tileable_rr_graph/chan_node_details.cpp +++ b/vpr/src/tileable_rr_graph/chan_node_details.cpp @@ -15,68 +15,68 @@ namespace openfpga { * Constructors ***********************************************************************/ ChanNodeDetails::ChanNodeDetails(const ChanNodeDetails& src) { - /* duplicate */ - size_t chan_width = src.get_chan_width(); - this->reserve(chan_width); - for (size_t itrack = 0; itrack < chan_width; ++itrack) { - track_node_ids_.push_back(src.get_track_node_id(itrack)); - track_direction_.push_back(src.get_track_direction(itrack)); - seg_ids_.push_back(src.get_track_segment_id(itrack)); - seg_length_.push_back(src.get_track_segment_length(itrack)); - track_start_.push_back(src.is_track_start(itrack)); - track_end_.push_back(src.is_track_end(itrack)); - } + /* duplicate */ + size_t chan_width = src.get_chan_width(); + this->reserve(chan_width); + for (size_t itrack = 0; itrack < chan_width; ++itrack) { + track_node_ids_.push_back(src.get_track_node_id(itrack)); + track_direction_.push_back(src.get_track_direction(itrack)); + seg_ids_.push_back(src.get_track_segment_id(itrack)); + seg_length_.push_back(src.get_track_segment_length(itrack)); + track_start_.push_back(src.is_track_start(itrack)); + track_end_.push_back(src.is_track_end(itrack)); + } } ChanNodeDetails::ChanNodeDetails() { - this->clear(); + this->clear(); } /************************************************************************ * Accessors ***********************************************************************/ size_t ChanNodeDetails::get_chan_width() const { - VTR_ASSERT(validate_chan_width()); - return track_node_ids_.size(); + VTR_ASSERT(validate_chan_width()); + return track_node_ids_.size(); } size_t ChanNodeDetails::get_track_node_id(const size_t& track_id) const { - VTR_ASSERT(validate_track_id(track_id)); - return track_node_ids_[track_id]; + VTR_ASSERT(validate_track_id(track_id)); + return track_node_ids_[track_id]; } /* Return a copy of vector */ std::vector ChanNodeDetails::get_track_node_ids() const { - std::vector copy; - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - copy.push_back(track_node_ids_[inode]); - } - return copy; + std::vector copy; + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + copy.push_back(track_node_ids_[inode]); + } + return copy; } Direction ChanNodeDetails::get_track_direction(const size_t& track_id) const { - VTR_ASSERT(validate_track_id(track_id)); - return track_direction_[track_id]; + VTR_ASSERT(validate_track_id(track_id)); + return track_direction_[track_id]; } size_t ChanNodeDetails::get_track_segment_length(const size_t& track_id) const { - VTR_ASSERT(validate_track_id(track_id)); - return seg_length_[track_id]; + VTR_ASSERT(validate_track_id(track_id)); + return seg_length_[track_id]; } size_t ChanNodeDetails::get_track_segment_id(const size_t& track_id) const { - VTR_ASSERT(validate_track_id(track_id)); - return seg_ids_[track_id]; + VTR_ASSERT(validate_track_id(track_id)); + return seg_ids_[track_id]; } -bool ChanNodeDetails::is_track_start(const size_t& track_id) const { - VTR_ASSERT(validate_track_id(track_id)); - return track_start_[track_id]; +bool ChanNodeDetails::is_track_start(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_start_[track_id]; } -bool ChanNodeDetails::is_track_end(const size_t& track_id) const { - VTR_ASSERT(validate_track_id(track_id)); - return track_end_[track_id]; +bool ChanNodeDetails::is_track_end(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_end_[track_id]; } /* Track_id is the starting point of group (whose is_start should be true) @@ -84,216 +84,213 @@ bool ChanNodeDetails::is_track_end(const size_t& track_id) const { * A group size is the number of such nodes between the starting points (include the 1st starting point) */ std::vector ChanNodeDetails::get_seg_group(const size_t& track_id) const { - VTR_ASSERT(validate_chan_width()); - VTR_ASSERT(validate_track_id(track_id)); - VTR_ASSERT(is_track_start(track_id)); - - std::vector group; - /* Make sure a clean start */ - group.clear(); - - for (size_t itrack = track_id; itrack < get_chan_width(); ++itrack) { - if ( (get_track_direction(itrack) != get_track_direction(track_id) ) - || (get_track_segment_id(itrack) != get_track_segment_id(track_id)) ) { - /* Bypass any nodes in different direction and segment information*/ - continue; - } - if ( (false == is_track_start(itrack)) - || ( (true == is_track_start(itrack)) && (itrack == track_id)) ) { - group.push_back(itrack); - continue; - } - /* Stop if this another starting point */ - if (true == is_track_start(itrack)) { - break; + VTR_ASSERT(validate_chan_width()); + VTR_ASSERT(validate_track_id(track_id)); + VTR_ASSERT(is_track_start(track_id)); + + std::vector group; + /* Make sure a clean start */ + group.clear(); + + for (size_t itrack = track_id; itrack < get_chan_width(); ++itrack) { + if ((get_track_direction(itrack) != get_track_direction(track_id)) + || (get_track_segment_id(itrack) != get_track_segment_id(track_id))) { + /* Bypass any nodes in different direction and segment information*/ + continue; + } + if ((false == is_track_start(itrack)) + || ((true == is_track_start(itrack)) && (itrack == track_id))) { + group.push_back(itrack); + continue; + } + /* Stop if this another starting point */ + if (true == is_track_start(itrack)) { + break; + } } - } - return group; + return group; } /* Get a list of track_ids with the given list of track indices */ std::vector ChanNodeDetails::get_seg_group_node_id(const std::vector& seg_group) const { - std::vector group; - /* Make sure a clean start */ - group.clear(); + std::vector group; + /* Make sure a clean start */ + group.clear(); - for (size_t id = 0; id < seg_group.size(); ++id) { - VTR_ASSERT(validate_track_id(seg_group[id])); - group.push_back(get_track_node_id(seg_group[id])); - } + for (size_t id = 0; id < seg_group.size(); ++id) { + VTR_ASSERT(validate_track_id(seg_group[id])); + group.push_back(get_track_node_id(seg_group[id])); + } - return group; + return group; } /* Get the number of tracks that starts in this routing channel */ size_t ChanNodeDetails::get_num_starting_tracks(const Direction& track_direction) const { - size_t counter = 0; - for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { - /* Bypass unmatched track_direction */ - if (track_direction != get_track_direction(itrack)) { - continue; + size_t counter = 0; + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass unmatched track_direction */ + if (track_direction != get_track_direction(itrack)) { + continue; + } + if (false == is_track_start(itrack)) { + continue; + } + counter++; } - if (false == is_track_start(itrack)) { - continue; - } - counter++; - } - return counter; + return counter; } /* Get the number of tracks that ends in this routing channel */ size_t ChanNodeDetails::get_num_ending_tracks(const Direction& track_direction) const { - size_t counter = 0; - for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { - /* Bypass unmatched track_direction */ - if (track_direction != get_track_direction(itrack)) { - continue; + size_t counter = 0; + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass unmatched track_direction */ + if (track_direction != get_track_direction(itrack)) { + continue; + } + if (false == is_track_end(itrack)) { + continue; + } + counter++; } - if (false == is_track_end(itrack)) { - continue; - } - counter++; - } - return counter; + return counter; } - /************************************************************************ * Mutators ***********************************************************************/ /* Reserve the capacitcy of vectors */ void ChanNodeDetails::reserve(const size_t& chan_width) { - track_node_ids_.reserve(chan_width); - track_direction_.reserve(chan_width); - seg_length_.reserve(chan_width); - seg_ids_.reserve(chan_width); - track_start_.reserve(chan_width); - track_end_.reserve(chan_width); + track_node_ids_.reserve(chan_width); + track_direction_.reserve(chan_width); + seg_length_.reserve(chan_width); + seg_ids_.reserve(chan_width); + track_start_.reserve(chan_width); + track_end_.reserve(chan_width); } /* Add a track to the channel */ -void ChanNodeDetails::add_track(const size_t& track_node_id, const Direction& track_direction, - const size_t& seg_id, const size_t& seg_length, - const size_t& is_start, const size_t& is_end) { - track_node_ids_.push_back(track_node_id); - track_direction_.push_back(track_direction); - seg_ids_.push_back(seg_id); - seg_length_.push_back(seg_length); - track_start_.push_back(is_start); - track_end_.push_back(is_end); +void ChanNodeDetails::add_track(const size_t& track_node_id, const Direction& track_direction, const size_t& seg_id, const size_t& seg_length, const size_t& is_start, const size_t& is_end) { + track_node_ids_.push_back(track_node_id); + track_direction_.push_back(track_direction); + seg_ids_.push_back(seg_id); + seg_length_.push_back(seg_length); + track_start_.push_back(is_start); + track_end_.push_back(is_end); } /* Update the node_id of a given track */ void ChanNodeDetails::set_track_node_id(const size_t& track_index, const size_t& track_node_id) { - VTR_ASSERT(validate_track_id(track_index)); - track_node_ids_[track_index] = track_node_id; + VTR_ASSERT(validate_track_id(track_index)); + track_node_ids_[track_index] = track_node_id; } /* Update the node_ids from a vector */ void ChanNodeDetails::set_track_node_ids(const std::vector& track_node_ids) { - /* the size of vector should match chan_width */ - VTR_ASSERT ( get_chan_width() == track_node_ids.size() ); - for (size_t inode = 0; inode < track_node_ids.size(); ++inode) { - track_node_ids_[inode] = track_node_ids[inode]; - } + /* the size of vector should match chan_width */ + VTR_ASSERT(get_chan_width() == track_node_ids.size()); + for (size_t inode = 0; inode < track_node_ids.size(); ++inode) { + track_node_ids_[inode] = track_node_ids[inode]; + } } /* Set tracks with a given direction to start */ void ChanNodeDetails::set_tracks_start(const Direction& track_direction) { - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - /* Bypass non-match tracks */ - if (track_direction != get_track_direction(inode)) { - continue; /* Pass condition*/ + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Bypass non-match tracks */ + if (track_direction != get_track_direction(inode)) { + continue; /* Pass condition*/ + } + track_start_[inode] = true; } - track_start_[inode] = true; - } } /* Set tracks with a given direction to end */ void ChanNodeDetails::set_tracks_end(const Direction& track_direction) { - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - /* Bypass non-match tracks */ - if (track_direction != get_track_direction(inode)) { - continue; /* Pass condition*/ + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Bypass non-match tracks */ + if (track_direction != get_track_direction(inode)) { + continue; /* Pass condition*/ + } + track_end_[inode] = true; } - track_end_[inode] = true; - } } /* rotate the track_node_id by an offset */ void ChanNodeDetails::rotate_track_node_id(const size_t& offset, const Direction& track_direction, const bool& counter_rotate) { - /* Direct return if offset = 0*/ - if (0 == offset) { - return; - } - - /* Rotate the node_ids by groups + /* Direct return if offset = 0*/ + if (0 == offset) { + return; + } + + /* Rotate the node_ids by groups * A group begins from a track_start and ends before another track_start */ - VTR_ASSERT(validate_chan_width()); - for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { - /* Bypass non-start segment */ - if (false == is_track_start(itrack) ) { - continue; - } - /* Bypass segments do not match track_direction */ - if (track_direction != get_track_direction(itrack) ) { - continue; - } - /* Find the group nodes */ - std::vector track_group = get_seg_group(itrack); - /* Build a vector of the node ids of the tracks */ - std::vector track_group_node_id = get_seg_group_node_id(track_group); - /* adapt offset to the range of track_group_node_id */ - size_t actual_offset = offset % track_group_node_id.size(); - /* Rotate or Counter rotate */ - if (true == counter_rotate) { - std::rotate(track_group_node_id.rbegin(), track_group_node_id.rbegin() + actual_offset, track_group_node_id.rend()); - } else { - std::rotate(track_group_node_id.begin(), track_group_node_id.begin() + actual_offset, track_group_node_id.end()); + VTR_ASSERT(validate_chan_width()); + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass non-start segment */ + if (false == is_track_start(itrack)) { + continue; + } + /* Bypass segments do not match track_direction */ + if (track_direction != get_track_direction(itrack)) { + continue; + } + /* Find the group nodes */ + std::vector track_group = get_seg_group(itrack); + /* Build a vector of the node ids of the tracks */ + std::vector track_group_node_id = get_seg_group_node_id(track_group); + /* adapt offset to the range of track_group_node_id */ + size_t actual_offset = offset % track_group_node_id.size(); + /* Rotate or Counter rotate */ + if (true == counter_rotate) { + std::rotate(track_group_node_id.rbegin(), track_group_node_id.rbegin() + actual_offset, track_group_node_id.rend()); + } else { + std::rotate(track_group_node_id.begin(), track_group_node_id.begin() + actual_offset, track_group_node_id.end()); + } + /* Update the node_ids */ + for (size_t inode = 0; inode < track_group.size(); ++inode) { + track_node_ids_[track_group[inode]] = track_group_node_id[inode]; + } } - /* Update the node_ids */ - for (size_t inode = 0; inode < track_group.size(); ++inode) { - track_node_ids_[track_group[inode]] = track_group_node_id[inode]; - } - } - return; + return; } void ChanNodeDetails::clear() { - track_node_ids_.clear(); - track_direction_.clear(); - seg_ids_.clear(); - seg_length_.clear(); - track_start_.clear(); - track_end_.clear(); + track_node_ids_.clear(); + track_direction_.clear(); + seg_ids_.clear(); + seg_length_.clear(); + track_start_.clear(); + track_end_.clear(); } /************************************************************************ * Validators ***********************************************************************/ bool ChanNodeDetails::validate_chan_width() const { - size_t chan_width = track_node_ids_.size(); - if ( (chan_width == track_direction_.size()) - &&(chan_width == seg_ids_.size()) - &&(chan_width == seg_length_.size()) - &&(chan_width == track_start_.size()) - &&(chan_width == track_end_.size()) ) { - return true; - } - return false; + size_t chan_width = track_node_ids_.size(); + if ((chan_width == track_direction_.size()) + && (chan_width == seg_ids_.size()) + && (chan_width == seg_length_.size()) + && (chan_width == track_start_.size()) + && (chan_width == track_end_.size())) { + return true; + } + return false; } bool ChanNodeDetails::validate_track_id(const size_t& track_id) const { - if ( (track_id < track_node_ids_.size()) - && (track_id < track_direction_.size()) - && (track_id < seg_ids_.size()) - && (track_id < seg_length_.size()) - && (track_id < track_start_.size()) - && (track_id < track_end_.size()) ) { - return true; - } - return false; + if ((track_id < track_node_ids_.size()) + && (track_id < track_direction_.size()) + && (track_id < seg_ids_.size()) + && (track_id < seg_length_.size()) + && (track_id < track_start_.size()) + && (track_id < track_end_.size())) { + return true; + } + return false; } } /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index 60a8698f8e7..231781a69b2 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -24,20 +24,20 @@ namespace openfpga { ***********************************************************************/ vtr::Point get_track_rr_node_start_coordinate(const RRGraph& rr_graph, const RRNodeId& track_rr_node) { - /* Make sure we have CHANX or CHANY */ - VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node)) ); - - vtr::Point start_coordinator; - - if (Direction::INC == rr_graph.node_direction(track_rr_node)) { - start_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); - } else { - VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); - start_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node)); - } - - return start_coordinator; + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node))); + + vtr::Point start_coordinator; + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + start_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + start_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node)); + } + + return start_coordinator; } /************************************************************************ @@ -50,20 +50,20 @@ vtr::Point get_track_rr_node_start_coordinate(const RRGraph& rr_graph, ***********************************************************************/ vtr::Point get_track_rr_node_end_coordinate(const RRGraph& rr_graph, const RRNodeId& track_rr_node) { - /* Make sure we have CHANX or CHANY */ - VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node)) ); - - vtr::Point end_coordinator; - - if (Direction::INC == rr_graph.node_direction(track_rr_node)) { - end_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node)); - } else { - VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); - end_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); - } - - return end_coordinator; + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node))); + + vtr::Point end_coordinator; + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + end_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node)); + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + end_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + } + + return end_coordinator; } /************************************************************************ @@ -72,14 +72,14 @@ vtr::Point get_track_rr_node_end_coordinate(const RRGraph& rr_graph, ***********************************************************************/ std::vector get_rr_graph_driver_switches(const RRGraph& rr_graph, const RRNodeId& node) { - std::vector driver_switches; - for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { - if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) { - driver_switches.push_back(rr_graph.edge_switch(edge)); + std::vector driver_switches; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) { + driver_switches.push_back(rr_graph.edge_switch(edge)); + } } - } - return driver_switches; + return driver_switches; } /************************************************************************ @@ -87,12 +87,12 @@ std::vector get_rr_graph_driver_switches(const RRGraph& rr_graph, ***********************************************************************/ std::vector get_rr_graph_driver_nodes(const RRGraph& rr_graph, const RRNodeId& node) { - std::vector driver_nodes; - for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { - driver_nodes.push_back(rr_graph.edge_src_node(edge)); - } + std::vector driver_nodes; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } - return driver_nodes; + return driver_nodes; } /************************************************************************ @@ -100,16 +100,16 @@ std::vector get_rr_graph_driver_nodes(const RRGraph& rr_graph, ***********************************************************************/ std::vector get_rr_graph_configurable_driver_nodes(const RRGraph& rr_graph, const RRNodeId& node) { - std::vector driver_nodes; - for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { - /* Bypass non-configurable edges */ - if (false == rr_graph.edge_is_configurable(edge)) { - continue; - } - driver_nodes.push_back(rr_graph.edge_src_node(edge)); - } - - return driver_nodes; + std::vector driver_nodes; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + /* Bypass non-configurable edges */ + if (false == rr_graph.edge_is_configurable(edge)) { + continue; + } + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } + + return driver_nodes; } /************************************************************************ @@ -117,16 +117,16 @@ std::vector get_rr_graph_configurable_driver_nodes(const RRGraph& rr_g ***********************************************************************/ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraph& rr_graph, const RRNodeId& node) { - std::vector driver_nodes; - for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { - /* Bypass configurable edges */ - if (true == rr_graph.edge_is_configurable(edge)) { - continue; - } - driver_nodes.push_back(rr_graph.edge_src_node(edge)); - } - - return driver_nodes; + std::vector driver_nodes; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + /* Bypass configurable edges */ + if (true == rr_graph.edge_is_configurable(edge)) { + continue; + } + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } + + return driver_nodes; } /************************************************************************ @@ -137,22 +137,22 @@ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraph& ***********************************************************************/ bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, const RRNodeId& node) { - /* We only accept OPIN */ - VTR_ASSERT(OPIN == rr_graph.node_type(node)); - - if (1 != rr_graph.node_out_edges(node).size()) { - return false; - } - - VTR_ASSERT(1 == rr_graph.node_out_edges(node).size()); - for (const RREdgeId& edge: rr_graph.node_out_edges(node)) { - const RRNodeId& sink_node = rr_graph.edge_sink_node(edge); - if (IPIN != rr_graph.node_type(sink_node)) { - return false; + /* We only accept OPIN */ + VTR_ASSERT(OPIN == rr_graph.node_type(node)); + + if (1 != rr_graph.node_out_edges(node).size()) { + return false; + } + + VTR_ASSERT(1 == rr_graph.node_out_edges(node).size()); + for (const RREdgeId& edge : rr_graph.node_out_edges(node)) { + const RRNodeId& sink_node = rr_graph.edge_sink_node(edge); + if (IPIN != rr_graph.node_type(sink_node)) { + return false; + } } - } - - return true; + + return true; } /************************************************************************ @@ -163,22 +163,22 @@ bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, ***********************************************************************/ bool is_ipin_direct_connected_opin(const RRGraph& rr_graph, const RRNodeId& node) { - /* We only accept IPIN */ - VTR_ASSERT(IPIN == rr_graph.node_type(node)); - - if (1 != rr_graph.node_in_edges(node).size()) { - return false; - } - - VTR_ASSERT(1 == rr_graph.node_in_edges(node).size()); - for (const RREdgeId& edge: rr_graph.node_in_edges(node)) { - const RRNodeId& src_node = rr_graph.edge_src_node(edge); - if (OPIN != rr_graph.node_type(src_node)) { - return false; + /* We only accept IPIN */ + VTR_ASSERT(IPIN == rr_graph.node_type(node)); + + if (1 != rr_graph.node_in_edges(node).size()) { + return false; } - } - - return true; + + VTR_ASSERT(1 == rr_graph.node_in_edges(node).size()); + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + if (OPIN != rr_graph.node_type(src_node)) { + return false; + } + } + + return true; } } /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp index 0aea3cee48a..556f1893a74 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.cpp +++ b/vpr/src/tileable_rr_graph/rr_chan.cpp @@ -13,180 +13,180 @@ namespace openfpga { ***********************************************************************/ /* default constructor */ RRChan::RRChan() { - type_ = NUM_RR_TYPES; - nodes_.resize(0); - node_segments_.resize(0); + type_ = NUM_RR_TYPES; + nodes_.resize(0); + node_segments_.resize(0); } /************************************************************************ * Accessors ***********************************************************************/ t_rr_type RRChan::get_type() const { - return type_; + return type_; } /* get the number of tracks in this channel */ -size_t RRChan::get_chan_width() const { - return nodes_.size(); +size_t RRChan::get_chan_width() const { + return nodes_.size(); } /* get the track_id of a node */ int RRChan::get_node_track_id(const RRNodeId& node) const { - /* if the given node is NULL, we return an invalid id */ - if (RRNodeId::INVALID() == node) { - return -1; - } - /* check each member and return if we find a match in content */ - std::vector::const_iterator it = std::find(nodes_.begin(), nodes_.end(), node); - if (nodes_.end() == it) { - return -1; - } - return it - nodes_.begin(); + /* if the given node is NULL, we return an invalid id */ + if (RRNodeId::INVALID() == node) { + return -1; + } + /* check each member and return if we find a match in content */ + std::vector::const_iterator it = std::find(nodes_.begin(), nodes_.end(), node); + if (nodes_.end() == it) { + return -1; + } + return it - nodes_.begin(); } /* get the rr_node with the track_id */ RRNodeId RRChan::get_node(const size_t& track_num) const { - if ( false == valid_node_id(track_num) ) { - return RRNodeId::INVALID(); - } - return nodes_[track_num]; -} + if (false == valid_node_id(track_num)) { + return RRNodeId::INVALID(); + } + return nodes_[track_num]; +} /* get the segment id of a node */ RRSegmentId RRChan::get_node_segment(const RRNodeId& node) const { - int node_id = get_node_track_id(node); - if ( false == valid_node_id(node_id)) { - return RRSegmentId::INVALID(); - } - return get_node_segment(node_id); + int node_id = get_node_track_id(node); + if (false == valid_node_id(node_id)) { + return RRSegmentId::INVALID(); + } + return get_node_segment(node_id); } /* get the segment id of a node */ RRSegmentId RRChan::get_node_segment(const size_t& track_num) const { - if ( false == valid_node_id(track_num)) { - return RRSegmentId::INVALID(); - } - return node_segments_[track_num]; + if (false == valid_node_id(track_num)) { + return RRSegmentId::INVALID(); + } + return node_segments_[track_num]; } /* evaluate if two RRChan is mirror to each other */ bool RRChan::is_mirror(const RRGraph& rr_graph, const RRChan& cand) const { - /* If any following element does not match, it is not mirror */ - /* 1. type */ - if (this->get_type() != cand.get_type()) { - return false; - } - /* 2. track_width */ - if (this->get_chan_width() != cand.get_chan_width()) { - return false; - } - /* 3. for each node */ - for (size_t inode = 0; inode < this->get_chan_width(); ++inode) { - /* 3.1 check node type */ - if (rr_graph.node_type(this->get_node(inode)) != rr_graph.node_type(cand.get_node(inode))) { - return false; + /* If any following element does not match, it is not mirror */ + /* 1. type */ + if (this->get_type() != cand.get_type()) { + return false; } - /* 3.2 check node directionality */ - if (rr_graph.node_direction(this->get_node(inode)) != rr_graph.node_direction(cand.get_node(inode))) { - return false; + /* 2. track_width */ + if (this->get_chan_width() != cand.get_chan_width()) { + return false; } - /* 3.3 check node segment */ - if (this->get_node_segment(inode) != cand.get_node_segment(inode)) { - return false; + /* 3. for each node */ + for (size_t inode = 0; inode < this->get_chan_width(); ++inode) { + /* 3.1 check node type */ + if (rr_graph.node_type(this->get_node(inode)) != rr_graph.node_type(cand.get_node(inode))) { + return false; + } + /* 3.2 check node directionality */ + if (rr_graph.node_direction(this->get_node(inode)) != rr_graph.node_direction(cand.get_node(inode))) { + return false; + } + /* 3.3 check node segment */ + if (this->get_node_segment(inode) != cand.get_node_segment(inode)) { + return false; + } } - } - - return true; + + return true; } /* Get a list of segments used in this routing channel */ -std::vector RRChan::get_segment_ids() const { - std::vector seg_list; - - /* make sure a clean start */ - seg_list.clear(); - - /* Traverse node_segments */ - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - std::vector::iterator it; - /* Try to find the node_segment id in the list */ - it = find(seg_list.begin(), seg_list.end(), node_segments_[inode]); - if ( it == seg_list.end() ) { - /* Not found, add it to the list */ - seg_list.push_back(node_segments_[inode]); +std::vector RRChan::get_segment_ids() const { + std::vector seg_list; + + /* make sure a clean start */ + seg_list.clear(); + + /* Traverse node_segments */ + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + std::vector::iterator it; + /* Try to find the node_segment id in the list */ + it = find(seg_list.begin(), seg_list.end(), node_segments_[inode]); + if (it == seg_list.end()) { + /* Not found, add it to the list */ + seg_list.push_back(node_segments_[inode]); + } } - } - return seg_list; + return seg_list; } /* Get a list of nodes whose segment_id is specified */ std::vector RRChan::get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const { - std::vector node_list; + std::vector node_list; - /* make sure a clean start */ - node_list.clear(); + /* make sure a clean start */ + node_list.clear(); - /* Traverse node_segments */ - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - /* Try to find the node_segment id in the list */ - if ( seg_id == node_segments_[inode] ) { - node_list.push_back(inode); + /* Traverse node_segments */ + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Try to find the node_segment id in the list */ + if (seg_id == node_segments_[inode]) { + node_list.push_back(inode); + } } - } - return node_list; -} + return node_list; +} /************************************************************************ * Mutators ***********************************************************************/ void RRChan::set(const RRChan& rr_chan) { - /* Ensure a clean start */ - this->clear(); - /* Assign type of this routing channel */ - this->type_ = rr_chan.get_type(); - /* Copy node and node_segments */ - this->nodes_.resize(rr_chan.get_chan_width()); - this->node_segments_.resize(rr_chan.get_chan_width()); - for (size_t inode = 0; inode < rr_chan.get_chan_width(); ++inode) { - this->nodes_[inode] = rr_chan.get_node(inode); - this->node_segments_[inode] = rr_chan.get_node_segment(inode); - } - return; + /* Ensure a clean start */ + this->clear(); + /* Assign type of this routing channel */ + this->type_ = rr_chan.get_type(); + /* Copy node and node_segments */ + this->nodes_.resize(rr_chan.get_chan_width()); + this->node_segments_.resize(rr_chan.get_chan_width()); + for (size_t inode = 0; inode < rr_chan.get_chan_width(); ++inode) { + this->nodes_[inode] = rr_chan.get_node(inode); + this->node_segments_[inode] = rr_chan.get_node_segment(inode); + } + return; } /* modify type */ void RRChan::set_type(const t_rr_type& type) { - VTR_ASSERT(valid_type(type)); - type_ = type; -} + VTR_ASSERT(valid_type(type)); + type_ = type; +} /* Reserve node list */ void RRChan::reserve_node(const size_t& node_size) { - nodes_.reserve(node_size); /* reserve to the maximum */ - node_segments_.reserve(node_size); /* reserve to the maximum */ + nodes_.reserve(node_size); /* reserve to the maximum */ + node_segments_.reserve(node_size); /* reserve to the maximum */ } /* add a node to the array */ void RRChan::add_node(const RRGraph& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment) { - /* fill the dedicated element in the vector */ - nodes_.push_back(node); - node_segments_.push_back(node_segment); - - if (NUM_RR_TYPES == type_) { - type_ = rr_graph.node_type(node); - } else { - VTR_ASSERT(type_ == rr_graph.node_type(node)); - } + /* fill the dedicated element in the vector */ + nodes_.push_back(node); + node_segments_.push_back(node_segment); + + if (NUM_RR_TYPES == type_) { + type_ = rr_graph.node_type(node); + } else { + VTR_ASSERT(type_ == rr_graph.node_type(node)); + } - VTR_ASSERT(valid_node_type(rr_graph, node)); + VTR_ASSERT(valid_node_type(rr_graph, node)); } /* Clear content */ void RRChan::clear() { - nodes_.clear(); - node_segments_.clear(); + nodes_.clear(); + node_segments_.clear(); } /************************************************************************ @@ -194,32 +194,32 @@ void RRChan::clear() { ***********************************************************************/ /* for type, only valid type is CHANX and CHANY */ bool RRChan::valid_type(const t_rr_type& type) const { - if ((CHANX == type) || (CHANY == type)) { - return true; - } - return false; -} + if ((CHANX == type) || (CHANY == type)) { + return true; + } + return false; +} /* Check each node, see if the node type is consistent with the type */ bool RRChan::valid_node_type(const RRGraph& rr_graph, const RRNodeId& node) const { - valid_type(rr_graph.node_type(node)); - if (NUM_RR_TYPES == type_) { + valid_type(rr_graph.node_type(node)); + if (NUM_RR_TYPES == type_) { + return true; + } + valid_type(type_); + if (type_ != rr_graph.node_type(node)) { + return false; + } return true; - } - valid_type(type_); - if (type_ != rr_graph.node_type(node)) { - return false; - } - return true; } /* check if the node id is valid */ bool RRChan::valid_node_id(const size_t& node_id) const { - if (node_id < nodes_.size()) { - return true; - } + if (node_id < nodes_.size()) { + return true; + } - return false; + return false; } } /* End namespace openfpga*/ diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 3aaba3e1ac2..c3653ac3b73 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -20,14 +20,14 @@ namespace openfpga { * uni-directional routing architecture ***********************************************************************/ size_t find_unidir_routing_channel_width(const size_t& chan_width) { - size_t actual_chan_width = chan_width; - /* Correct the chan_width: it should be an even number */ - if (0 != actual_chan_width % 2) { - actual_chan_width++; /* increment it to be even */ - } - VTR_ASSERT(0 == actual_chan_width % 2); - - return actual_chan_width; + size_t actual_chan_width = chan_width; + /* Correct the chan_width: it should be an even number */ + if (0 != actual_chan_width % 2) { + actual_chan_width++; /* increment it to be even */ + } + VTR_ASSERT(0 == actual_chan_width % 2); + + return actual_chan_width; } /************************************************************************ @@ -35,46 +35,46 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width) { ***********************************************************************/ int get_grid_pin_class_index(const t_grid_tile& cur_grid, const int pin_index) { - /* check */ - VTR_ASSERT(pin_index < cur_grid.type->num_pins); - return cur_grid.type->pin_class[pin_index]; + /* check */ + VTR_ASSERT(pin_index < cur_grid.type->num_pins); + return cur_grid.type->pin_class[pin_index]; } /* Deteremine the side of a io grid */ -e_side determine_io_grid_pin_side(const vtr::Point& device_size, +e_side determine_io_grid_pin_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate) { - /* TOP side IO of FPGA */ - if (device_size.y() == grid_coordinate.y()) { - return BOTTOM; /* Such I/O has only Bottom side pins */ - } else if (device_size.x() == grid_coordinate.x()) { /* RIGHT side IO of FPGA */ - return LEFT; /* Such I/O has only Left side pins */ - } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ - return TOP; /* Such I/O has only Top side pins */ - } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ - return RIGHT; /* Such I/O has only Right side pins */ - } else if ((grid_coordinate.x() < device_size.x()) && (grid_coordinate.y() < device_size.y())) { - /* I/O grid in the center grid */ - return NUM_SIDES; - } - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n", - grid_coordinate.x(), grid_coordinate.y(), - device_size.x(), device_size.y()); - exit(1); + /* TOP side IO of FPGA */ + if (device_size.y() == grid_coordinate.y()) { + return BOTTOM; /* Such I/O has only Bottom side pins */ + } else if (device_size.x() == grid_coordinate.x()) { /* RIGHT side IO of FPGA */ + return LEFT; /* Such I/O has only Left side pins */ + } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ + return TOP; /* Such I/O has only Top side pins */ + } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ + return RIGHT; /* Such I/O has only Right side pins */ + } else if ((grid_coordinate.x() < device_size.x()) && (grid_coordinate.y() < device_size.y())) { + /* I/O grid in the center grid */ + return NUM_SIDES; + } + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n", + grid_coordinate.x(), grid_coordinate.y(), + device_size.x(), device_size.y()); + exit(1); } /* Deteremine the side of a pin of a grid */ -std::vector find_grid_pin_sides(const t_grid_tile& grid, +std::vector find_grid_pin_sides(const t_grid_tile& grid, const size_t& pin_id) { - std::vector pin_sides; + std::vector pin_sides; - for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT} ) { - if (true == grid.type->pinloc[grid.width_offset][grid.height_offset][size_t(side)][pin_id]) { - pin_sides.push_back(side); + for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { + if (true == grid.type->pinloc[grid.width_offset][grid.height_offset][size_t(side)][pin_id]) { + pin_sides.push_back(side); + } } - } - return pin_sides; + return pin_sides; } /************************************************************************ @@ -82,23 +82,23 @@ std::vector find_grid_pin_sides(const t_grid_tile& grid, * For IO_TYPE, only one side will be used, we consider one side of pins * For others, we consider all the sides ***********************************************************************/ -std::vector get_grid_side_pins(const t_grid_tile& cur_grid, - const e_pin_type& pin_type, - const e_side& pin_side, +std::vector get_grid_side_pins(const t_grid_tile& cur_grid, + const e_pin_type& pin_type, + const e_side& pin_side, const int& pin_width, const int& pin_height) { - std::vector pin_list; - /* Make sure a clear start */ - pin_list.clear(); - - for (int ipin = 0; ipin < cur_grid.type->num_pins; ++ipin) { - int class_id = cur_grid.type->pin_class[ipin]; - if ( (1 == cur_grid.type->pinloc[pin_width][pin_height][pin_side][ipin]) - && (pin_type == cur_grid.type->class_inf[class_id].type) ) { - pin_list.push_back(ipin); + std::vector pin_list; + /* Make sure a clear start */ + pin_list.clear(); + + for (int ipin = 0; ipin < cur_grid.type->num_pins; ++ipin) { + int class_id = cur_grid.type->pin_class[ipin]; + if ((1 == cur_grid.type->pinloc[pin_width][pin_height][pin_side][ipin]) + && (pin_type == cur_grid.type->class_inf[class_id].type)) { + pin_list.push_back(ipin); + } } - } - return pin_list; + return pin_list; } /************************************************************************ @@ -106,28 +106,28 @@ std::vector get_grid_side_pins(const t_grid_tile& cur_grid, * For IO_TYPE, only one side will be used, we consider one side of pins * For others, we consider all the sides ***********************************************************************/ -size_t get_grid_num_pins(const t_grid_tile& cur_grid, - const e_pin_type& pin_type, +size_t get_grid_num_pins(const t_grid_tile& cur_grid, + const e_pin_type& pin_type, const e_side& io_side) { - size_t num_pins = 0; - - /* For IO_TYPE sides */ - for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { - /* skip unwanted sides */ - if ( (true == is_io_type(cur_grid.type)) - && (side != io_side) && (NUM_SIDES != io_side)) { - continue; + size_t num_pins = 0; + + /* For IO_TYPE sides */ + for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { + /* skip unwanted sides */ + if ((true == is_io_type(cur_grid.type)) + && (side != io_side) && (NUM_SIDES != io_side)) { + continue; + } + /* Get pin list */ + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + std::vector pin_list = get_grid_side_pins(cur_grid, pin_type, side, width, height); + num_pins += pin_list.size(); + } + } } - /* Get pin list */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { - std::vector pin_list = get_grid_side_pins(cur_grid, pin_type, side, width, height); - num_pins += pin_list.size(); - } - } - } - - return num_pins; + + return num_pins; } /************************************************************************ @@ -135,19 +135,19 @@ size_t get_grid_num_pins(const t_grid_tile& cur_grid, * For IO_TYPE, only one side will be used, we consider one side of pins * For others, we consider all the sides ***********************************************************************/ -size_t get_grid_num_classes(const t_grid_tile& cur_grid, +size_t get_grid_num_classes(const t_grid_tile& cur_grid, const e_pin_type& pin_type) { - size_t num_classes = 0; - - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Bypass unmatched pin_type */ - if (pin_type != cur_grid.type->class_inf[iclass].type) { - continue; + size_t num_classes = 0; + + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Bypass unmatched pin_type */ + if (pin_type != cur_grid.type->class_inf[iclass].type) { + continue; + } + num_classes++; } - num_classes++; - } - return num_classes; + return num_classes; } /************************************************************************ @@ -178,20 +178,19 @@ size_t get_grid_num_classes(const t_grid_tile& cur_grid, bool is_chanx_exist(const DeviceGrid& grids, const vtr::Point& chanx_coord, const bool& through_channel) { + if ((1 > chanx_coord.x()) || (chanx_coord.x() > grids.width() - 2)) { + return false; + } - if ((1 > chanx_coord.x()) || (chanx_coord.x() > grids.width() - 2)) { - return false; - } - - if (chanx_coord.y() > grids.height() - 2) { - return false; - } + if (chanx_coord.y() > grids.height() - 2) { + return false; + } - if (true == through_channel) { - return true; - } + if (true == through_channel) { + return true; + } - return (grids[chanx_coord.x()][chanx_coord.y()].height_offset == grids[chanx_coord.x()][chanx_coord.y()].type->height - 1); + return (grids[chanx_coord.x()][chanx_coord.y()].height_offset == grids[chanx_coord.x()][chanx_coord.y()].type->height - 1); } /************************************************************************ @@ -217,20 +216,19 @@ bool is_chanx_exist(const DeviceGrid& grids, bool is_chany_exist(const DeviceGrid& grids, const vtr::Point& chany_coord, const bool& through_channel) { + if (chany_coord.x() > grids.width() - 2) { + return false; + } - if (chany_coord.x() > grids.width() - 2) { - return false; - } - - if ((1 > chany_coord.y()) || (chany_coord.y() > grids.height() - 2)) { - return false; - } + if ((1 > chany_coord.y()) || (chany_coord.y() > grids.height() - 2)) { + return false; + } - if (true == through_channel) { - return true; - } + if (true == through_channel) { + return true; + } - return (grids[chany_coord.x()][chany_coord.y()].width_offset == grids[chany_coord.x()][chany_coord.y()].type->width - 1); + return (grids[chany_coord.x()][chany_coord.y()].width_offset == grids[chany_coord.x()][chany_coord.y()].type->width - 1); } /************************************************************************ @@ -249,23 +247,23 @@ bool is_chany_exist(const DeviceGrid& grids, bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, const vtr::Point& chanx_coord, const bool& through_channel) { - VTR_ASSERT(0 < chanx_coord.x()); - if (1 == chanx_coord.x()) { - /* This is already the LEFT side of FPGA fabric, + VTR_ASSERT(0 < chanx_coord.x()); + if (1 == chanx_coord.x()) { + /* This is already the LEFT side of FPGA fabric, * it is the same results as chanx is right to a multi-height grid */ - return true; - } - - if (false == through_channel) { - /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ - vtr::Point left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y()); - if (false == is_chanx_exist(grids, left_chanx_coord)) { - return true; + return true; + } + + if (false == through_channel) { + /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ + vtr::Point left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y()); + if (false == is_chanx_exist(grids, left_chanx_coord)) { + return true; + } } - } - return false; + return false; } /************************************************************************ @@ -284,24 +282,23 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, const vtr::Point& chanx_coord, const bool& through_channel) { - VTR_ASSERT(chanx_coord.x() < grids.width() - 1); - if (grids.width() - 2 == chanx_coord.x()) { - /* This is already the RIGHT side of FPGA fabric, + VTR_ASSERT(chanx_coord.x() < grids.width() - 1); + if (grids.width() - 2 == chanx_coord.x()) { + /* This is already the RIGHT side of FPGA fabric, * it is the same results as chanx is right to a multi-height grid */ - return true; - } - - - if (false == through_channel) { - /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ - vtr::Point right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y()); - if (false == is_chanx_exist(grids, right_chanx_coord)) { - return true; + return true; + } + + if (false == through_channel) { + /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ + vtr::Point right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y()); + if (false == is_chanx_exist(grids, right_chanx_coord)) { + return true; + } } - } - return false; + return false; } /************************************************************************ @@ -325,23 +322,23 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, const vtr::Point& chany_coord, const bool& through_channel) { - VTR_ASSERT(0 < chany_coord.y()); - if (1 == chany_coord.y()) { - /* This is already the BOTTOM side of FPGA fabric, + VTR_ASSERT(0 < chany_coord.y()); + if (1 == chany_coord.y()) { + /* This is already the BOTTOM side of FPGA fabric, * it is the same results as chany is at the top of a multi-width grid */ - return true; - } - - if (false == through_channel) { - /* We check the bottom neighbor of chany, if it does not exist, the chany is top to a multi-height grid */ - vtr::Point bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1); - if (false == is_chany_exist(grids, bottom_chany_coord)) { - return true; + return true; + } + + if (false == through_channel) { + /* We check the bottom neighbor of chany, if it does not exist, the chany is top to a multi-height grid */ + vtr::Point bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1); + if (false == is_chany_exist(grids, bottom_chany_coord)) { + return true; + } } - } - return false; + return false; } /************************************************************************ @@ -365,23 +362,23 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, const vtr::Point& chany_coord, const bool& through_channel) { - VTR_ASSERT(chany_coord.y() < grids.height() - 1); - if (grids.height() - 2 == chany_coord.y()) { - /* This is already the TOP side of FPGA fabric, + VTR_ASSERT(chany_coord.y() < grids.height() - 1); + if (grids.height() - 2 == chany_coord.y()) { + /* This is already the TOP side of FPGA fabric, * it is the same results as chany is at the bottom of a multi-width grid */ - return true; - } - - if (false == through_channel) { - /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */ - vtr::Point top_chany_coord(chany_coord.x(), chany_coord.y() + 1); - if (false == is_chany_exist(grids, top_chany_coord)) { - return true; + return true; } - } - return false; + if (false == through_channel) { + /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */ + vtr::Point top_chany_coord(chany_coord.x(), chany_coord.y() + 1); + if (false == is_chany_exist(grids, top_chany_coord)) { + return true; + } + } + + return false; } /************************************************************************ @@ -407,9 +404,9 @@ short get_rr_node_actual_track_id(const RRGraph& rr_graph, const RRNodeId& track_rr_node, const vtr::Point& coord, const vtr::vector>& tileable_rr_graph_node_track_ids) { - vtr::Point low_coord(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); - size_t offset = (int)abs((int)coord.x() - (int)low_coord.x() + (int)coord.y() - (int)low_coord.y()); - return tileable_rr_graph_node_track_ids[track_rr_node][offset]; + vtr::Point low_coord(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + size_t offset = (int)abs((int)coord.x() - (int)low_coord.x() + (int)coord.y() - (int)low_coord.y()); + return tileable_rr_graph_node_track_ids[track_rr_node][offset]; } /************************************************************************ @@ -423,16 +420,16 @@ short get_rr_node_actual_track_id(const RRGraph& rr_graph, short get_track_rr_node_end_track_id(const RRGraph& rr_graph, const RRNodeId& track_rr_node, const vtr::vector>& tileable_rr_graph_node_track_ids) { - /* Make sure we have CHANX or CHANY */ - VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node)) ); - - if (Direction::INC == rr_graph.node_direction(track_rr_node)) { - return tileable_rr_graph_node_track_ids[track_rr_node].back(); - } - - VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); - return tileable_rr_graph_node_track_ids[track_rr_node].front(); + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node))); + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + return tileable_rr_graph_node_track_ids[track_rr_node].back(); + } + + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + return tileable_rr_graph_node_track_ids[track_rr_node].front(); } /************************************************************************ @@ -441,17 +438,17 @@ short get_track_rr_node_end_track_id(const RRGraph& rr_graph, ************************************************************************/ short find_rr_graph_num_nodes(const RRGraph& rr_graph, const std::vector& node_types) { - short counter = 0; - - for (const RRNodeId& node : rr_graph.nodes()) { - /* Bypass the nodes not in the class */ - if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { - continue; + short counter = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + counter++; } - counter++; - } - return counter; + return counter; } /************************************************************************ @@ -460,17 +457,17 @@ short find_rr_graph_num_nodes(const RRGraph& rr_graph, ************************************************************************/ short find_rr_graph_max_fan_in(const RRGraph& rr_graph, const std::vector& node_types) { - short max_fan_in = 0; - - for (const RRNodeId& node : rr_graph.nodes()) { - /* Bypass the nodes not in the class */ - if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { - continue; + short max_fan_in = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + max_fan_in = std::max(rr_graph.node_fan_in(node), max_fan_in); } - max_fan_in = std::max(rr_graph.node_fan_in(node), max_fan_in); - } - return max_fan_in; + return max_fan_in; } /************************************************************************ @@ -479,18 +476,17 @@ short find_rr_graph_max_fan_in(const RRGraph& rr_graph, ************************************************************************/ short find_rr_graph_min_fan_in(const RRGraph& rr_graph, const std::vector& node_types) { - short min_fan_in = 0; - - for (const RRNodeId& node : rr_graph.nodes()) { - /* Bypass the nodes not in the class */ - if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { - continue; + short min_fan_in = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + min_fan_in = std::min(rr_graph.node_fan_in(node), min_fan_in); } - min_fan_in = std::min(rr_graph.node_fan_in(node), min_fan_in); - } - - return min_fan_in; + return min_fan_in; } /************************************************************************ @@ -499,58 +495,57 @@ short find_rr_graph_min_fan_in(const RRGraph& rr_graph, ************************************************************************/ short find_rr_graph_average_fan_in(const RRGraph& rr_graph, const std::vector& node_types) { - /* Get the maximum SB mux size */ - size_t sum = 0; - size_t counter = 0; - - for (const RRNodeId& node : rr_graph.nodes()) { - /* Bypass the nodes not in the class */ - if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { - continue; + /* Get the maximum SB mux size */ + size_t sum = 0; + size_t counter = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + + sum += rr_graph.node_fan_in(node); + counter++; } - sum += rr_graph.node_fan_in(node); - counter++; - } - - return sum / counter; + return sum / counter; } /************************************************************************ * Print statistics of multiplexers in a routing resource graph ************************************************************************/ void print_rr_graph_mux_stats(const RRGraph& rr_graph) { - - /* Print MUX size distribution */ - std::vector sb_node_types; - sb_node_types.push_back(CHANX); - sb_node_types.push_back(CHANY); - - /* Print statistics */ - VTR_LOG("------------------------------------------------\n"); - VTR_LOG("Total No. of Switch Block multiplexer size: %d\n", - find_rr_graph_num_nodes(rr_graph, sb_node_types)); - VTR_LOG("Maximum Switch Block multiplexer size: %d\n", - find_rr_graph_max_fan_in(rr_graph, sb_node_types)); - VTR_LOG("Minimum Switch Block multiplexer size: %d\n", - find_rr_graph_min_fan_in(rr_graph, sb_node_types)); - VTR_LOG("Average Switch Block multiplexer size: %lu\n", - find_rr_graph_average_fan_in(rr_graph, sb_node_types)); - VTR_LOG("------------------------------------------------\n"); - - /* Get the maximum CB mux size */ - std::vector cb_node_types(1, IPIN); - - VTR_LOG("------------------------------------------------\n"); - VTR_LOG("Total No. of Connection Block Multiplexer size: %d\n", - find_rr_graph_num_nodes(rr_graph, cb_node_types)); - VTR_LOG("Maximum Connection Block Multiplexer size: %d\n", - find_rr_graph_max_fan_in(rr_graph, cb_node_types)); - VTR_LOG("Minimum Connection Block Multiplexer size: %d\n", - find_rr_graph_min_fan_in(rr_graph, cb_node_types)); - VTR_LOG("Average Connection Block Multiplexer size: %lu\n", - find_rr_graph_average_fan_in(rr_graph, cb_node_types)); - VTR_LOG("------------------------------------------------\n"); + /* Print MUX size distribution */ + std::vector sb_node_types; + sb_node_types.push_back(CHANX); + sb_node_types.push_back(CHANY); + + /* Print statistics */ + VTR_LOG("------------------------------------------------\n"); + VTR_LOG("Total No. of Switch Block multiplexer size: %d\n", + find_rr_graph_num_nodes(rr_graph, sb_node_types)); + VTR_LOG("Maximum Switch Block multiplexer size: %d\n", + find_rr_graph_max_fan_in(rr_graph, sb_node_types)); + VTR_LOG("Minimum Switch Block multiplexer size: %d\n", + find_rr_graph_min_fan_in(rr_graph, sb_node_types)); + VTR_LOG("Average Switch Block multiplexer size: %lu\n", + find_rr_graph_average_fan_in(rr_graph, sb_node_types)); + VTR_LOG("------------------------------------------------\n"); + + /* Get the maximum CB mux size */ + std::vector cb_node_types(1, IPIN); + + VTR_LOG("------------------------------------------------\n"); + VTR_LOG("Total No. of Connection Block Multiplexer size: %d\n", + find_rr_graph_num_nodes(rr_graph, cb_node_types)); + VTR_LOG("Maximum Connection Block Multiplexer size: %d\n", + find_rr_graph_max_fan_in(rr_graph, cb_node_types)); + VTR_LOG("Minimum Connection Block Multiplexer size: %d\n", + find_rr_graph_min_fan_in(rr_graph, cb_node_types)); + VTR_LOG("Average Connection Block Multiplexer size: %lu\n", + find_rr_graph_average_fan_in(rr_graph, cb_node_types)); + VTR_LOG("------------------------------------------------\n"); } } /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index badaa663bac..68f287e291c 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -18,16 +18,16 @@ namespace openfpga { ***********************************************************************/ /* Constructor for an empty object */ RRGSB::RRGSB() { - /* Set a clean start! */ - coordinate_.set(0, 0); + /* Set a clean start! */ + coordinate_.set(0, 0); - chan_node_.clear(); - chan_node_direction_.clear(); - chan_node_in_edges_.clear(); + chan_node_.clear(); + chan_node_direction_.clear(); + chan_node_in_edges_.clear(); - ipin_node_.clear(); + ipin_node_.clear(); - opin_node_.clear(); + opin_node_.clear(); } /************************************************************************ @@ -35,367 +35,367 @@ RRGSB::RRGSB() { ***********************************************************************/ /* Get the number of sides of this SB */ size_t RRGSB::get_num_sides() const { - VTR_ASSERT (validate_num_sides()); - return chan_node_direction_.size(); + VTR_ASSERT(validate_num_sides()); + return chan_node_direction_.size(); } /* Get the number of routing tracks on a side */ size_t RRGSB::get_chan_width(const e_side& side) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - return chan_node_[side_manager.to_size_t()].get_chan_width(); + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return chan_node_[side_manager.to_size_t()].get_chan_width(); } /* Get the number of routing tracks on a side */ t_rr_type RRGSB::get_chan_type(const e_side& side) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - return chan_node_[side_manager.to_size_t()].get_type(); + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return chan_node_[side_manager.to_size_t()].get_type(); } /* Get the maximum number of routing tracks on all sides */ size_t RRGSB::get_max_chan_width() const { - size_t max_chan_width = 0; - for (size_t side = 0; side < get_num_sides(); ++side) { - SideManager side_manager(side); - max_chan_width = std::max(max_chan_width, get_chan_width(side_manager.get_side())); - } - return max_chan_width; -} + size_t max_chan_width = 0; + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + max_chan_width = std::max(max_chan_width, get_chan_width(side_manager.get_side())); + } + return max_chan_width; +} /* Get the number of routing tracks of a X/Y-direction CB */ size_t RRGSB::get_cb_chan_width(const t_rr_type& cb_type) const { - return get_chan_width(get_cb_chan_side(cb_type)); + return get_chan_width(get_cb_chan_side(cb_type)); } /* Get the sides of ipin_nodes belong to the cb */ std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) const { - VTR_ASSERT (validate_cb_type(cb_type)); - - std::vector ipin_sides; - - /* Make sure a clean start */ - ipin_sides.clear(); - - switch(cb_type) { - case CHANX: - ipin_sides.push_back(TOP); - ipin_sides.push_back(BOTTOM); - break; - case CHANY: - ipin_sides.push_back(RIGHT); - ipin_sides.push_back(LEFT); - break; - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } - - return ipin_sides; + VTR_ASSERT(validate_cb_type(cb_type)); + + std::vector ipin_sides; + + /* Make sure a clean start */ + ipin_sides.clear(); + + switch (cb_type) { + case CHANX: + ipin_sides.push_back(TOP); + ipin_sides.push_back(BOTTOM); + break; + case CHANY: + ipin_sides.push_back(RIGHT); + ipin_sides.push_back(LEFT); + break; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } + + return ipin_sides; } /* Get the direction of a rr_node at a given side and track_id */ enum PORTS RRGSB::get_chan_node_direction(const e_side& side, const size_t& track_id) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - VTR_ASSERT( validate_side(side) ); + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); - /* Ensure the track is valid in the context of this switch block at a specific side */ - VTR_ASSERT( validate_track_id(side, track_id) ); - - return chan_node_direction_[side_manager.to_size_t()][track_id]; + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_track_id(side, track_id)); + + return chan_node_direction_[side_manager.to_size_t()][track_id]; } /* Get a list of segments used in this routing channel */ std::vector RRGSB::get_chan_segment_ids(const e_side& side) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - VTR_ASSERT( validate_side(side) ); + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); - return chan_node_[side_manager.to_size_t()].get_segment_ids(); + return chan_node_[side_manager.to_size_t()].get_segment_ids(); } /* Get a list of rr_nodes whose sed_id is specified */ std::vector RRGSB::get_chan_node_ids_by_segment_ids(const e_side& side, - const RRSegmentId& seg_id) const { - return chan_node_[size_t(side)].get_node_ids_by_segment_ids(seg_id); -} + const RRSegmentId& seg_id) const { + return chan_node_[size_t(side)].get_node_ids_by_segment_ids(seg_id); +} /* get a rr_node at a given side and track_id */ RRNodeId RRGSB::get_chan_node(const e_side& side, const size_t& track_id) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - VTR_ASSERT( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - VTR_ASSERT( validate_track_id(side, track_id) ); - - return chan_node_[side_manager.to_size_t()].get_node(track_id); -} - -std::vector RRGSB::get_chan_node_in_edges(const RRGraph& rr_graph, + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_track_id(side, track_id)); + + return chan_node_[side_manager.to_size_t()].get_node(track_id); +} + +std::vector RRGSB::get_chan_node_in_edges(const RRGraph& rr_graph, const e_side& side, const size_t& track_id) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - VTR_ASSERT( validate_side(side) ); + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); - /* Ensure the track is valid in the context of this switch block at a specific side */ - VTR_ASSERT( validate_track_id(side, track_id) ); + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_track_id(side, track_id)); - /* The chan node must be an output port for the GSB, we allow users to access input edges*/ - VTR_ASSERT(OUT_PORT == get_chan_node_direction(side, track_id)); + /* The chan node must be an output port for the GSB, we allow users to access input edges*/ + VTR_ASSERT(OUT_PORT == get_chan_node_direction(side, track_id)); - /* if sorted, we give sorted edges + /* if sorted, we give sorted edges * if not sorted, we give the empty vector */ - if (0 == chan_node_in_edges_.size()) { - std::vector unsorted_edges; - for (const RREdgeId& edge : rr_graph.node_in_edges(get_chan_node(side, track_id))) { - unsorted_edges.push_back(edge); - } + if (0 == chan_node_in_edges_.size()) { + std::vector unsorted_edges; + for (const RREdgeId& edge : rr_graph.node_in_edges(get_chan_node(side, track_id))) { + unsorted_edges.push_back(edge); + } - return unsorted_edges; - } + return unsorted_edges; + } - return chan_node_in_edges_[side_manager.to_size_t()][track_id]; + return chan_node_in_edges_[side_manager.to_size_t()][track_id]; } /* get the segment id of a channel rr_node */ RRSegmentId RRGSB::get_chan_node_segment(const e_side& side, const size_t& track_id) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - VTR_ASSERT( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - VTR_ASSERT( validate_track_id(side, track_id) ); - - return chan_node_[side_manager.to_size_t()].get_node_segment(track_id); -} + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_track_id(side, track_id)); + + return chan_node_[side_manager.to_size_t()].get_node_segment(track_id); +} /* Get the number of IPIN rr_nodes on a side */ size_t RRGSB::get_num_ipin_nodes(const e_side& side) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - return ipin_node_[side_manager.to_size_t()].size(); -} + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return ipin_node_[side_manager.to_size_t()].size(); +} /* get a opin_node at a given side and track_id */ RRNodeId RRGSB::get_ipin_node(const e_side& side, const size_t& node_id) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - VTR_ASSERT( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - VTR_ASSERT( validate_ipin_node_id(side, node_id) ); - - return ipin_node_[side_manager.to_size_t()][node_id]; -} + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_ipin_node_id(side, node_id)); + + return ipin_node_[side_manager.to_size_t()][node_id]; +} /* Get the number of OPIN rr_nodes on a side */ size_t RRGSB::get_num_opin_nodes(const e_side& side) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - return opin_node_[side_manager.to_size_t()].size(); -} + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return opin_node_[side_manager.to_size_t()].size(); +} /* get a opin_node at a given side and track_id */ RRNodeId RRGSB::get_opin_node(const e_side& side, const size_t& node_id) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - VTR_ASSERT(validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - VTR_ASSERT(validate_opin_node_id(side, node_id) ); - - return opin_node_[side_manager.to_size_t()][node_id]; -} + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_opin_node_id(side, node_id)); + + return opin_node_[side_manager.to_size_t()][node_id]; +} /* Get the node index of a routing track of a connection block, return -1 if not found */ int RRGSB::get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const { - enum e_side chan_side = get_cb_chan_side(cb_type); - return get_chan_node_index(chan_side, node); + enum e_side chan_side = get_cb_chan_side(cb_type); + return get_chan_node_index(chan_side, node); } /* Get the node index in the array, return -1 if not found */ int RRGSB::get_chan_node_index(const e_side& node_side, const RRNodeId& node) const { - VTR_ASSERT (validate_side(node_side)); - return chan_node_[size_t(node_side)].get_node_track_id(node); + VTR_ASSERT(validate_side(node_side)); + return chan_node_[size_t(node_side)].get_node_track_id(node); } /* Get the node index in the array, return -1 if not found */ int RRGSB::get_node_index(const RRGraph& rr_graph, - const RRNodeId& node, - const e_side& node_side, + const RRNodeId& node, + const e_side& node_side, const PORTS& node_direction) const { - size_t cnt; - int ret; - - cnt = 0; - ret = -1; - - /* Depending on the type of rr_node, we search different arrays */ - switch (rr_graph.node_type(node)) { - case CHANX: - case CHANY: - for (size_t inode = 0; inode < get_chan_width(node_side); ++inode){ - if ((node == chan_node_[size_t(node_side)].get_node(inode)) - /* Check if direction meets specification */ - &&(node_direction == chan_node_direction_[size_t(node_side)][inode])) { - cnt++; - ret = inode; - break; - } - } - break; - case IPIN: - for (size_t inode = 0; inode < get_num_ipin_nodes(node_side); ++inode) { - if (node == ipin_node_[size_t(node_side)][inode]) { - cnt++; - ret = inode; - break; - } + size_t cnt; + int ret; + + cnt = 0; + ret = -1; + + /* Depending on the type of rr_node, we search different arrays */ + switch (rr_graph.node_type(node)) { + case CHANX: + case CHANY: + for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { + if ((node == chan_node_[size_t(node_side)].get_node(inode)) + /* Check if direction meets specification */ + && (node_direction == chan_node_direction_[size_t(node_side)][inode])) { + cnt++; + ret = inode; + break; + } + } + break; + case IPIN: + for (size_t inode = 0; inode < get_num_ipin_nodes(node_side); ++inode) { + if (node == ipin_node_[size_t(node_side)][inode]) { + cnt++; + ret = inode; + break; + } + } + break; + case OPIN: + for (size_t inode = 0; inode < get_num_opin_nodes(node_side); ++inode) { + if (node == opin_node_[size_t(node_side)][inode]) { + cnt++; + ret = inode; + break; + } + } + break; + default: + VTR_LOG("Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n"); + exit(1); } - break; - case OPIN: - for (size_t inode = 0; inode < get_num_opin_nodes(node_side); ++inode) { - if (node == opin_node_[size_t(node_side)][inode]) { - cnt++; - ret = inode; - break; - } - } - break; - default: - VTR_LOG("Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n"); - exit(1); - } - VTR_ASSERT((0 == cnt)||(1 == cnt)); + VTR_ASSERT((0 == cnt) || (1 == cnt)); - return ret; /* Return an invalid value: nonthing is found*/ + return ret; /* Return an invalid value: nonthing is found*/ } /* Get the side of a node in this SB */ void RRGSB::get_node_side_and_index(const RRGraph& rr_graph, - const RRNodeId& node, + const RRNodeId& node, const PORTS& node_direction, - e_side& node_side, + e_side& node_side, int& node_index) const { - size_t side; - SideManager side_manager; - - /* Count the number of existence of cur_rr_node in cur_sb_info + size_t side; + SideManager side_manager; + + /* Count the number of existence of cur_rr_node in cur_sb_info * It could happen that same cur_rr_node appears on different sides of a SB * For example, a routing track go vertically across the SB. * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. * We need to ensure that the found rr_node has the same direction as user want. * By specifying the direction of rr_node, There should be only one rr_node can satisfy! */ - for (side = 0; side < get_num_sides(); ++side) { - side_manager.set_side(side); - node_index = get_node_index(rr_graph, node, side_manager.get_side(), node_direction); - if (-1 != node_index) { - break; + for (side = 0; side < get_num_sides(); ++side) { + side_manager.set_side(side); + node_index = get_node_index(rr_graph, node, side_manager.get_side(), node_direction); + if (-1 != node_index) { + break; + } } - } - if (side == get_num_sides()) { - /* we find nothing, return NUM_SIDES, and a OPEN node (-1) */ - node_side = NUM_SIDES; - VTR_ASSERT(-1 == node_index); - return; - } + if (side == get_num_sides()) { + /* we find nothing, return NUM_SIDES, and a OPEN node (-1) */ + node_side = NUM_SIDES; + VTR_ASSERT(-1 == node_index); + return; + } - node_side = side_manager.get_side(); - VTR_ASSERT(-1 != node_index); + node_side = side_manager.get_side(); + VTR_ASSERT(-1 != node_index); - return; -} + return; +} /* Check if the node exist in the opposite side of this Switch Block */ bool RRGSB::is_sb_node_exist_opposite_side(const RRGraph& rr_graph, - const RRNodeId& node, + const RRNodeId& node, const e_side& node_side) const { - SideManager side_manager(node_side); - int index; + SideManager side_manager(node_side); + int index; - VTR_ASSERT((CHANX == rr_graph.node_type(node)) || (CHANY == rr_graph.node_type(node))); + VTR_ASSERT((CHANX == rr_graph.node_type(node)) || (CHANY == rr_graph.node_type(node))); - /* See if we can find the same src_rr_node in the opposite chan_side + /* See if we can find the same src_rr_node in the opposite chan_side * if there is one, it means a shorted wire across the SB */ - index = get_node_index(rr_graph, node, side_manager.get_opposite(), IN_PORT); + index = get_node_index(rr_graph, node, side_manager.get_opposite(), IN_PORT); - return (-1 != index); + return (-1 != index); } /* check if the candidate CB is a mirror of the current one */ -bool RRGSB::is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const { - /* Check if channel width is the same */ - if ( get_cb_chan_width(cb_type) != cand.get_cb_chan_width(cb_type) ) { - return false; - } - - enum e_side chan_side = get_cb_chan_side(cb_type); +bool RRGSB::is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const { + /* Check if channel width is the same */ + if (get_cb_chan_width(cb_type) != cand.get_cb_chan_width(cb_type)) { + return false; + } - /* check the numbers/directionality of channel rr_nodes */ - if ( false == chan_node_[size_t(chan_side)].is_mirror(rr_graph, cand.chan_node_[size_t(chan_side)]) ) { - return false; - } + enum e_side chan_side = get_cb_chan_side(cb_type); - /* check the equivalence of ipins */ - std::vector ipin_side = get_cb_ipin_sides(cb_type); - for (size_t side = 0; side < ipin_side.size(); ++side) { - /* Ensure we have the same number of IPINs on this side */ - if ( get_num_ipin_nodes(ipin_side[side]) != cand.get_num_ipin_nodes(ipin_side[side]) ) { - return false; - } - for (size_t inode = 0; inode < get_num_ipin_nodes(ipin_side[side]); ++inode) { - if (false == is_cb_node_mirror(rr_graph, cand, cb_type, ipin_side[side], inode)) { + /* check the numbers/directionality of channel rr_nodes */ + if (false == chan_node_[size_t(chan_side)].is_mirror(rr_graph, cand.chan_node_[size_t(chan_side)])) { return false; - } } - } - return true; + /* check the equivalence of ipins */ + std::vector ipin_side = get_cb_ipin_sides(cb_type); + for (size_t side = 0; side < ipin_side.size(); ++side) { + /* Ensure we have the same number of IPINs on this side */ + if (get_num_ipin_nodes(ipin_side[side]) != cand.get_num_ipin_nodes(ipin_side[side])) { + return false; + } + for (size_t inode = 0; inode < get_num_ipin_nodes(ipin_side[side]); ++inode) { + if (false == is_cb_node_mirror(rr_graph, cand, cb_type, ipin_side[side], inode)) { + return false; + } + } + } + + return true; } /* check if the CB exist in this GSB */ bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const { - /* if channel width is zero, there is no CB */ - return (0 != get_cb_chan_width(cb_type)); -} + /* if channel width is zero, there is no CB */ + return (0 != get_cb_chan_width(cb_type)); +} /* check if the SB exist in this GSB */ bool RRGSB::is_sb_exist() const { - /* if all the channel width is zero and number of OPINs are zero, there is no SB */ - for (size_t side = 0; side < get_num_sides(); ++side) { - SideManager side_manager(side); - if (0 != get_chan_width(side_manager.get_side())) { - return true; + /* if all the channel width is zero and number of OPINs are zero, there is no SB */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + if (0 != get_chan_width(side_manager.get_side())) { + return true; + } + if (0 != get_num_opin_nodes(side_manager.get_side())) { + return true; + } } - if (0 != get_num_opin_nodes(side_manager.get_side())) { - return true; - } - } - return false; -} + return false; +} /************************************************************************ * Check if the node indicates a passing wire across the Switch Block part of the GSB @@ -407,49 +407,48 @@ bool RRGSB::is_sb_exist() const { * (xhigh, yhigh) should be same as the GSB side coordinate ***********************************************************************/ bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph, - const e_side& node_side, - const size_t& track_id) const { - - /* Get the rr_node */ - RRNodeId track_node = get_chan_node(node_side, track_id); - /* Get the coordinates */ - vtr::Point side_coordinate = get_side_block_coordinate(node_side); - - /* Get the coordinate of where the track starts */ - vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); - - /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */ - /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */ - if ( (track_start.x() == side_coordinate.x()) - && (track_start.y() == side_coordinate.y()) - && (OUT_PORT == get_chan_node_direction(node_side, track_id)) ) { - /* Double check: start track should be an OUTPUT PORT of the GSB */ - return false; /* This is a starting point */ - } - - /* Get the coordinate of where the track ends */ - vtr::Point track_end = get_track_rr_node_end_coordinate(rr_graph, track_node); - - /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ - /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ - if ( (track_end.x() == side_coordinate.x()) - && (track_end.y() == side_coordinate.y()) - && (IN_PORT == get_chan_node_direction(node_side, track_id)) ) { - /* Double check: end track should be an INPUT PORT of the GSB */ - return false; /* This is an ending point */ - } - - /* Reach here it means that this will be a passing wire, + const e_side& node_side, + const size_t& track_id) const { + /* Get the rr_node */ + RRNodeId track_node = get_chan_node(node_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = get_side_block_coordinate(node_side); + + /* Get the coordinate of where the track starts */ + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */ + /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + if ((track_start.x() == side_coordinate.x()) + && (track_start.y() == side_coordinate.y()) + && (OUT_PORT == get_chan_node_direction(node_side, track_id))) { + /* Double check: start track should be an OUTPUT PORT of the GSB */ + return false; /* This is a starting point */ + } + + /* Get the coordinate of where the track ends */ + vtr::Point track_end = get_track_rr_node_end_coordinate(rr_graph, track_node); + + /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ + if ((track_end.x() == side_coordinate.x()) + && (track_end.y() == side_coordinate.y()) + && (IN_PORT == get_chan_node_direction(node_side, track_id))) { + /* Double check: end track should be an INPUT PORT of the GSB */ + return false; /* This is an ending point */ + } + + /* Reach here it means that this will be a passing wire, * we should be able to find the node on the opposite side of the GSB! */ - if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) { - VTR_LOG("GSB[%lu][%lu] track node[%lu] at %s:\n", - get_x(), get_y(), track_id, SIDE_STRING[node_side]); - rr_graph.print_node(track_node); - } - VTR_ASSERT (true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)); + if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) { + VTR_LOG("GSB[%lu][%lu] track node[%lu] at %s:\n", + get_x(), get_y(), track_id, SIDE_STRING[node_side]); + rr_graph.print_node(track_node); + } + VTR_ASSERT(true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)); - return true; + return true; } /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ @@ -459,356 +458,353 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph, * If all above are satisfied, the two switch blocks may be mirrors ! */ bool RRGSB::is_sb_mirrorable(const RRGraph& rr_graph, const RRGSB& cand) const { - /* check the numbers of sides */ - if (get_num_sides() != cand.get_num_sides()) { - return false; - } - - /* check the numbers/directionality of channel rr_nodes */ - for (size_t side = 0; side < get_num_sides(); ++side) { - SideManager side_manager(side); - - /* Ensure we have the same channel width on this side */ - if (get_chan_width(side_manager.get_side()) != cand.get_chan_width(side_manager.get_side())) { - return false; + /* check the numbers of sides */ + if (get_num_sides() != cand.get_num_sides()) { + return false; } - if ( ((size_t(-1) == get_track_id_first_short_connection(rr_graph, side_manager.get_side())) - && (size_t(-1) != cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side()))) - || ((size_t(-1) != get_track_id_first_short_connection(rr_graph, side_manager.get_side()) ) - && ( size_t(-1) == cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side()))) ) { - return false; + /* check the numbers/directionality of channel rr_nodes */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + + /* Ensure we have the same channel width on this side */ + if (get_chan_width(side_manager.get_side()) != cand.get_chan_width(side_manager.get_side())) { + return false; + } + + if (((size_t(-1) == get_track_id_first_short_connection(rr_graph, side_manager.get_side())) + && (size_t(-1) != cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side()))) + || ((size_t(-1) != get_track_id_first_short_connection(rr_graph, side_manager.get_side())) + && (size_t(-1) == cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side())))) { + return false; + } } - } - /* check the numbers of opin_rr_nodes */ - for (size_t side = 0; side < get_num_sides(); ++side) { - SideManager side_manager(side); + /* check the numbers of opin_rr_nodes */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); - if (get_num_opin_nodes(side_manager.get_side()) != cand.get_num_opin_nodes(side_manager.get_side())) { - return false; + if (get_num_opin_nodes(side_manager.get_side()) != cand.get_num_opin_nodes(side_manager.get_side())) { + return false; + } } - } - return true; + return true; } /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ -bool RRGSB::is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand, - const e_side& side, const RRSegmentId& seg_id) const { - /* Create a side manager */ - SideManager side_manager(side); - - /* Make sure both Switch blocks has this side!!! */ - VTR_ASSERT ( side_manager.to_size_t() < get_num_sides() ); - VTR_ASSERT ( side_manager.to_size_t() < cand.get_num_sides() ); - - /* check the numbers/directionality of channel rr_nodes */ - /* Ensure we have the same channel width on this side */ - if (get_chan_width(side) != cand.get_chan_width(side)) { - return false; - } - for (size_t itrack = 0; itrack < get_chan_width(side); ++itrack) { - /* Bypass unrelated segments */ - if (seg_id != get_chan_node_segment(side, itrack)) { - continue; - } - /* Check the directionality of each node */ - if (get_chan_node_direction(side, itrack) != cand.get_chan_node_direction(side, itrack)) { - return false; +bool RRGSB::is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side, const RRSegmentId& seg_id) const { + /* Create a side manager */ + SideManager side_manager(side); + + /* Make sure both Switch blocks has this side!!! */ + VTR_ASSERT(side_manager.to_size_t() < get_num_sides()); + VTR_ASSERT(side_manager.to_size_t() < cand.get_num_sides()); + + /* check the numbers/directionality of channel rr_nodes */ + /* Ensure we have the same channel width on this side */ + if (get_chan_width(side) != cand.get_chan_width(side)) { + return false; } - /* Check the track_id of each node + for (size_t itrack = 0; itrack < get_chan_width(side); ++itrack) { + /* Bypass unrelated segments */ + if (seg_id != get_chan_node_segment(side, itrack)) { + continue; + } + /* Check the directionality of each node */ + if (get_chan_node_direction(side, itrack) != cand.get_chan_node_direction(side, itrack)) { + return false; + } + /* Check the track_id of each node * ptc is not necessary, we care the connectivity! */ - /* For OUT_PORT rr_node, we need to check fan-in */ - if (OUT_PORT != get_chan_node_direction(side, itrack)) { - continue; /* skip IN_PORT */ + /* For OUT_PORT rr_node, we need to check fan-in */ + if (OUT_PORT != get_chan_node_direction(side, itrack)) { + continue; /* skip IN_PORT */ + } + + if (false == is_sb_node_mirror(rr_graph, cand, side, itrack)) { + return false; + } } - if (false == is_sb_node_mirror(rr_graph, cand, side, itrack)) { - return false; - } - } - - /* check the numbers of opin_rr_nodes */ - if (get_num_opin_nodes(side) != cand.get_num_opin_nodes(side)) { - return false; - } + /* check the numbers of opin_rr_nodes */ + if (get_num_opin_nodes(side) != cand.get_num_opin_nodes(side)) { + return false; + } - /* check the numbers of ipin_rr_nodes */ - if (get_num_ipin_nodes(side) != cand.get_num_ipin_nodes(side)) { - return false; - } + /* check the numbers of ipin_rr_nodes */ + if (get_num_ipin_nodes(side) != cand.get_num_ipin_nodes(side)) { + return false; + } - return true; -} + return true; +} /* check if a side of candidate SB is a mirror of the current one */ bool RRGSB::is_sb_side_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side) const { + /* get a list of segments */ + std::vector seg_ids = chan_node_[size_t(side)].get_segment_ids(); - /* get a list of segments */ - std::vector seg_ids = chan_node_[size_t(side)].get_segment_ids(); - - for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { - if (false == is_sb_side_segment_mirror(rr_graph, cand, side, seg_ids[iseg])) { - return false; + for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { + if (false == is_sb_side_segment_mirror(rr_graph, cand, side, seg_ids[iseg])) { + return false; + } } - } - return true; + return true; } /* check if the candidate SB is a mirror of the current one */ bool RRGSB::is_sb_mirror(const RRGraph& rr_graph, const RRGSB& cand) const { - /* check the numbers of sides */ - if (get_num_sides() != cand.get_num_sides()) { - return false; - } + /* check the numbers of sides */ + if (get_num_sides() != cand.get_num_sides()) { + return false; + } - /* check the numbers/directionality of channel rr_nodes */ - for (size_t side = 0; side < get_num_sides(); ++side) { - SideManager side_manager(side); - if (false == is_sb_side_mirror(rr_graph, cand, side_manager.get_side())) { - return false; - } - } + /* check the numbers/directionality of channel rr_nodes */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + if (false == is_sb_side_mirror(rr_graph, cand, side_manager.get_side())) { + return false; + } + } - return true; + return true; } /* Public Accessors: Cooridinator conversion */ /* get the x coordinate of this GSB */ size_t RRGSB::get_x() const { - return coordinate_.x(); -} + return coordinate_.x(); +} /* get the y coordinate of this GSB */ -size_t RRGSB::get_y() const { - return coordinate_.y(); +size_t RRGSB::get_y() const { + return coordinate_.y(); } - /* get the x coordinate of this switch block */ size_t RRGSB::get_sb_x() const { - return coordinate_.x(); -} + return coordinate_.x(); +} /* get the y coordinate of this switch block */ -size_t RRGSB::get_sb_y() const { - return coordinate_.y(); +size_t RRGSB::get_sb_y() const { + return coordinate_.y(); } /* Get the number of sides of this SB */ vtr::Point RRGSB::get_sb_coordinate() const { - return coordinate_; -} + return coordinate_; +} /* get the x coordinate of this X/Y-direction block */ size_t RRGSB::get_cb_x(const t_rr_type& cb_type) const { - VTR_ASSERT (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return get_side_block_coordinate(LEFT).x(); - case CHANY: - return get_side_block_coordinate(TOP).x(); - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } -} + VTR_ASSERT(validate_cb_type(cb_type)); + switch (cb_type) { + case CHANX: + return get_side_block_coordinate(LEFT).x(); + case CHANY: + return get_side_block_coordinate(TOP).x(); + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } +} /* get the y coordinate of this X/Y-direction block */ -size_t RRGSB::get_cb_y(const t_rr_type& cb_type) const { - VTR_ASSERT (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return get_side_block_coordinate(LEFT).y(); - case CHANY: - return get_side_block_coordinate(TOP).y(); - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } +size_t RRGSB::get_cb_y(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + switch (cb_type) { + case CHANX: + return get_side_block_coordinate(LEFT).y(); + case CHANY: + return get_side_block_coordinate(TOP).y(); + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } } /* Get the coordinate of the X/Y-direction CB */ vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { - VTR_ASSERT (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return get_side_block_coordinate(LEFT); - case CHANY: - return get_side_block_coordinate(TOP); - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } -} + VTR_ASSERT(validate_cb_type(cb_type)); + switch (cb_type) { + case CHANX: + return get_side_block_coordinate(LEFT); + case CHANY: + return get_side_block_coordinate(TOP); + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } +} e_side RRGSB::get_cb_chan_side(const t_rr_type& cb_type) const { - VTR_ASSERT (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return LEFT; - case CHANY: - return TOP; - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } + VTR_ASSERT(validate_cb_type(cb_type)); + switch (cb_type) { + case CHANX: + return LEFT; + case CHANY: + return TOP; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } } /* Get the side of routing channel in the GSB according to the side of IPIN */ e_side RRGSB::get_cb_chan_side(const e_side& ipin_side) const { - switch(ipin_side) { - case TOP: - return LEFT; - case RIGHT: - return TOP; - case BOTTOM: - return LEFT; - case LEFT: - return TOP; - default: - VTR_LOG("Invalid type of ipin_side!\n"); - exit(1); - } + switch (ipin_side) { + case TOP: + return LEFT; + case RIGHT: + return TOP; + case BOTTOM: + return LEFT; + case LEFT: + return TOP; + default: + VTR_LOG("Invalid type of ipin_side!\n"); + exit(1); + } } vtr::Point RRGSB::get_side_block_coordinate(const e_side& side) const { - SideManager side_manager(side); - VTR_ASSERT(side_manager.validate()); - vtr::Point ret(get_sb_x(), get_sb_y()); - - switch (side_manager.get_side()) { - case TOP: - /* (0 == side) */ - /* 1. Channel Y [x][y+1] inputs */ - ret.set_y(ret.y() + 1); - break; - case RIGHT: - /* 1 == side */ - /* 2. Channel X [x+1][y] inputs */ - ret.set_x(ret.x() + 1); - break; - case BOTTOM: - /* 2 == side */ - /* 3. Channel Y [x][y] inputs */ - break; - case LEFT: - /* 3 == side */ - /* 4. Channel X [x][y] inputs */ - break; - default: - VTR_LOG(" Invalid side!\n"); - exit(1); - } - - return ret; + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + vtr::Point ret(get_sb_x(), get_sb_y()); + + switch (side_manager.get_side()) { + case TOP: + /* (0 == side) */ + /* 1. Channel Y [x][y+1] inputs */ + ret.set_y(ret.y() + 1); + break; + case RIGHT: + /* 1 == side */ + /* 2. Channel X [x+1][y] inputs */ + ret.set_x(ret.x() + 1); + break; + case BOTTOM: + /* 2 == side */ + /* 3. Channel Y [x][y] inputs */ + break; + case LEFT: + /* 3 == side */ + /* 4. Channel X [x][y] inputs */ + break; + default: + VTR_LOG(" Invalid side!\n"); + exit(1); + } + + return ret; } vtr::Point RRGSB::get_grid_coordinate() const { - vtr::Point ret(get_sb_x(), get_sb_y()); - ret.set_y(ret.y() + 1); + vtr::Point ret(get_sb_x(), get_sb_y()); + ret.set_y(ret.y() + 1); - return ret; + return ret; } /************************************************************************ * Public Mutators ***********************************************************************/ /* get a copy from a source */ -void RRGSB::set(const RRGSB& src) { - /* Copy coordinate */ - this->set_coordinate(src.get_sb_coordinate().x(), src.get_sb_coordinate().y()); - - /* Initialize sides */ - this->init_num_sides(src.get_num_sides()); - - /* Copy vectors */ - for (size_t side = 0; side < src.get_num_sides(); ++side) { - SideManager side_manager(side); - /* Copy chan_nodes */ - /* skip if there is no channel width */ - if ( 0 < src.get_chan_width(side_manager.get_side()) ) { - this->chan_node_[side_manager.get_side()].set(src.chan_node_[side_manager.get_side()]); - /* Copy chan_node_direction_*/ - this->chan_node_direction_[side_manager.get_side()].clear(); - for (size_t inode = 0; inode < src.get_chan_width(side_manager.get_side()); ++inode) { - this->chan_node_direction_[side_manager.get_side()].push_back(src.get_chan_node_direction(side_manager.get_side(), inode)); - } - } - - /* Copy opin_node and opin_node_grid_side_ */ - this->opin_node_[side_manager.get_side()].clear(); - for (size_t inode = 0; inode < src.get_num_opin_nodes(side_manager.get_side()); ++inode) { - this->opin_node_[side_manager.get_side()].push_back(src.get_opin_node(side_manager.get_side(), inode)); +void RRGSB::set(const RRGSB& src) { + /* Copy coordinate */ + this->set_coordinate(src.get_sb_coordinate().x(), src.get_sb_coordinate().y()); + + /* Initialize sides */ + this->init_num_sides(src.get_num_sides()); + + /* Copy vectors */ + for (size_t side = 0; side < src.get_num_sides(); ++side) { + SideManager side_manager(side); + /* Copy chan_nodes */ + /* skip if there is no channel width */ + if (0 < src.get_chan_width(side_manager.get_side())) { + this->chan_node_[side_manager.get_side()].set(src.chan_node_[side_manager.get_side()]); + /* Copy chan_node_direction_*/ + this->chan_node_direction_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_chan_width(side_manager.get_side()); ++inode) { + this->chan_node_direction_[side_manager.get_side()].push_back(src.get_chan_node_direction(side_manager.get_side(), inode)); + } + } + + /* Copy opin_node and opin_node_grid_side_ */ + this->opin_node_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_num_opin_nodes(side_manager.get_side()); ++inode) { + this->opin_node_[side_manager.get_side()].push_back(src.get_opin_node(side_manager.get_side(), inode)); + } + + /* Copy ipin_node and ipin_node_grid_side_ */ + this->ipin_node_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_num_ipin_nodes(side_manager.get_side()); ++inode) { + this->ipin_node_[side_manager.get_side()].push_back(src.get_ipin_node(side_manager.get_side(), inode)); + } } - - /* Copy ipin_node and ipin_node_grid_side_ */ - this->ipin_node_[side_manager.get_side()].clear(); - for (size_t inode = 0; inode < src.get_num_ipin_nodes(side_manager.get_side()); ++inode) { - this->ipin_node_[side_manager.get_side()].push_back(src.get_ipin_node(side_manager.get_side(), inode)); - } - } } /* Set the coordinate (x,y) for the switch block */ void RRGSB::set_coordinate(const size_t& x, const size_t& y) { - coordinate_.set(x, y); + coordinate_.set(x, y); } /* Allocate the vectors with the given number of sides */ void RRGSB::init_num_sides(const size_t& num_sides) { - /* Initialize the vectors */ - chan_node_.resize(num_sides); - chan_node_direction_.resize(num_sides); - ipin_node_.resize(num_sides); - opin_node_.resize(num_sides); + /* Initialize the vectors */ + chan_node_.resize(num_sides); + chan_node_direction_.resize(num_sides); + ipin_node_.resize(num_sides); + opin_node_.resize(num_sides); } /* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ void RRGSB::add_chan_node(const e_side& node_side, const RRChan& rr_chan, const std::vector& rr_chan_dir) { - /* Validate: 1. side is valid, the type of node is valid */ - VTR_ASSERT(validate_side(node_side)); - - /* fill the dedicated element in the vector */ - chan_node_[size_t(node_side)].set(rr_chan); - chan_node_direction_[size_t(node_side)].resize(rr_chan_dir.size()); - for (size_t inode = 0; inode < rr_chan_dir.size(); ++inode) { - chan_node_direction_[size_t(node_side)][inode] = rr_chan_dir[inode]; - } -} + /* Validate: 1. side is valid, the type of node is valid */ + VTR_ASSERT(validate_side(node_side)); + + /* fill the dedicated element in the vector */ + chan_node_[size_t(node_side)].set(rr_chan); + chan_node_direction_[size_t(node_side)].resize(rr_chan_dir.size()); + for (size_t inode = 0; inode < rr_chan_dir.size(); ++inode) { + chan_node_direction_[size_t(node_side)][inode] = rr_chan_dir[inode]; + } +} /* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ void RRGSB::add_ipin_node(const RRNodeId& node, const e_side& node_side) { - VTR_ASSERT(validate_side(node_side)); - /* push pack the dedicated element in the vector */ - ipin_node_[size_t(node_side)].push_back(node); + VTR_ASSERT(validate_side(node_side)); + /* push pack the dedicated element in the vector */ + ipin_node_[size_t(node_side)].push_back(node); } /* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ void RRGSB::add_opin_node(const RRNodeId& node, const e_side& node_side) { - VTR_ASSERT(validate_side(node_side)); - /* push pack the dedicated element in the vector */ - opin_node_[size_t(node_side)].push_back(node); -} + VTR_ASSERT(validate_side(node_side)); + /* push pack the dedicated element in the vector */ + opin_node_[size_t(node_side)].push_back(node); +} void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph, const e_side& chan_side, const size_t& track_id) { - std::map> from_grid_edge_map; - std::map> from_track_edge_map; + std::map> from_grid_edge_map; + std::map> from_track_edge_map; - const RRNodeId& chan_node = chan_node_[size_t(chan_side)].get_node(track_id); - - /* Count the edges and ensure every of them has been sorted */ - size_t edge_counter = 0; + const RRNodeId& chan_node = chan_node_[size_t(chan_side)].get_node(track_id); - /* For each incoming edge, find the node side and index in this GSB. + /* Count the edges and ensure every of them has been sorted */ + size_t edge_counter = 0; + + /* For each incoming edge, find the node side and index in this GSB. * and cache these. Then we will use the data to sort the edge in the * following sequence: * 0----------------------------------------------------------------> num_in_edges() @@ -817,73 +813,73 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph, * For each side, the edge from grid pins will be the 1st part * while the edge from routing tracks will be the 2nd part */ - for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) { - /* We care the source node of this edge, and it should be an input of the GSB!!! */ - const RRNodeId& src_node = rr_graph.edge_src_node(edge); - e_side side = NUM_SIDES; - int index = 0; - get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index); - - /* Must have valid side and index */ - if (NUM_SIDES == side) { - VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); - VTR_LOG("SRC node:\n"); - rr_graph.print_node(src_node); - VTR_LOG("Channel node:\n"); - rr_graph.print_node(chan_node); + for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) { + /* We care the source node of this edge, and it should be an input of the GSB!!! */ + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + e_side side = NUM_SIDES; + int index = 0; + get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index); + + /* Must have valid side and index */ + if (NUM_SIDES == side) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("SRC node:\n"); + rr_graph.print_node(src_node); + VTR_LOG("Channel node:\n"); + rr_graph.print_node(chan_node); + } + + VTR_ASSERT(NUM_SIDES != side); + VTR_ASSERT(OPEN != index); + + if (OPIN == rr_graph.node_type(src_node)) { + from_grid_edge_map[side][index] = edge; + } else { + VTR_ASSERT((CHANX == rr_graph.node_type(src_node)) + || (CHANY == rr_graph.node_type(src_node))); + from_track_edge_map[side][index] = edge; + } + + edge_counter++; } - VTR_ASSERT(NUM_SIDES != side); - VTR_ASSERT(OPEN != index); - - if (OPIN == rr_graph.node_type(src_node)) { - from_grid_edge_map[side][index] = edge; - } else { - VTR_ASSERT( (CHANX == rr_graph.node_type(src_node)) - || (CHANY == rr_graph.node_type(src_node)) ); - from_track_edge_map[side][index] = edge; - } - - edge_counter++; - } - - /* Store the sorted edge */ - for (size_t side = 0; side < get_num_sides(); ++side) { - /* Edges from grid outputs are the 1st part */ - for (size_t opin_id = 0; opin_id < opin_node_[side].size(); ++opin_id) { - if ( (0 < from_grid_edge_map.count(side)) - && (0 < from_grid_edge_map.at(side).count(opin_id)) ) { - chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_grid_edge_map[side][opin_id]); - } + /* Store the sorted edge */ + for (size_t side = 0; side < get_num_sides(); ++side) { + /* Edges from grid outputs are the 1st part */ + for (size_t opin_id = 0; opin_id < opin_node_[side].size(); ++opin_id) { + if ((0 < from_grid_edge_map.count(side)) + && (0 < from_grid_edge_map.at(side).count(opin_id))) { + chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_grid_edge_map[side][opin_id]); + } + } + + /* Edges from routing tracks are the 2nd part */ + for (size_t itrack = 0; itrack < chan_node_[side].get_chan_width(); ++itrack) { + if ((0 < from_track_edge_map.count(side)) + && (0 < from_track_edge_map.at(side).count(itrack))) { + chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_track_edge_map[side][itrack]); + } + } } - - /* Edges from routing tracks are the 2nd part */ - for (size_t itrack = 0; itrack < chan_node_[side].get_chan_width(); ++itrack) { - if ( (0 < from_track_edge_map.count(side)) - && (0 < from_track_edge_map.at(side).count(itrack)) ) { - chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_track_edge_map[side][itrack]); - } - } - } - VTR_ASSERT(edge_counter == chan_node_in_edges_[size_t(chan_side)][track_id].size()); -} + VTR_ASSERT(edge_counter == chan_node_in_edges_[size_t(chan_side)][track_id].size()); +} void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph) { - /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ - chan_node_in_edges_.resize(get_num_sides()); - - for (size_t side = 0; side < get_num_sides(); ++side) { - SideManager side_manager(side); - chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width()); - for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) { - /* Only sort the output nodes and bypass passing wires */ - if ( (OUT_PORT == chan_node_direction_[side][track_id]) - && (false == is_sb_node_passing_wire(rr_graph, side_manager.get_side(), track_id)) ) { - sort_chan_node_in_edges(rr_graph, side_manager.get_side(), track_id); - } + /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ + chan_node_in_edges_.resize(get_num_sides()); + + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width()); + for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) { + /* Only sort the output nodes and bypass passing wires */ + if ((OUT_PORT == chan_node_direction_[side][track_id]) + && (false == is_sb_node_passing_wire(rr_graph, side_manager.get_side(), track_id))) { + sort_chan_node_in_edges(rr_graph, side_manager.get_side(), track_id); + } + } } - } } /************************************************************************ @@ -891,49 +887,49 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph) { ***********************************************************************/ /* Reset the RRGSB to pristine state */ void RRGSB::clear() { - /* Clean all the vectors */ - VTR_ASSERT(validate_num_sides()); - /* Clear the inner vector of each matrix */ - for (size_t side = 0; side < get_num_sides(); ++side) { - chan_node_direction_[side].clear(); - chan_node_[side].clear(); - ipin_node_[side].clear(); - opin_node_[side].clear(); - } - chan_node_direction_.clear(); - chan_node_.clear(); - ipin_node_.clear(); - opin_node_.clear(); + /* Clean all the vectors */ + VTR_ASSERT(validate_num_sides()); + /* Clear the inner vector of each matrix */ + for (size_t side = 0; side < get_num_sides(); ++side) { + chan_node_direction_[side].clear(); + chan_node_[side].clear(); + ipin_node_[side].clear(); + opin_node_[side].clear(); + } + chan_node_direction_.clear(); + chan_node_.clear(); + ipin_node_.clear(); + opin_node_.clear(); } /* Clean the chan_width of a side */ void RRGSB::clear_chan_nodes(const e_side& node_side) { - VTR_ASSERT(validate_side(node_side)); - - chan_node_[size_t(node_side)].clear(); - chan_node_direction_[size_t(node_side)].clear(); -} + VTR_ASSERT(validate_side(node_side)); + + chan_node_[size_t(node_side)].clear(); + chan_node_direction_[size_t(node_side)].clear(); +} /* Clean the number of IPINs of a side */ void RRGSB::clear_ipin_nodes(const e_side& node_side) { - VTR_ASSERT(validate_side(node_side)); - - ipin_node_[size_t(node_side)].clear(); -} + VTR_ASSERT(validate_side(node_side)); + + ipin_node_[size_t(node_side)].clear(); +} /* Clean the number of OPINs of a side */ void RRGSB::clear_opin_nodes(const e_side& node_side) { - VTR_ASSERT(validate_side(node_side)); - - opin_node_[size_t(node_side)].clear(); + VTR_ASSERT(validate_side(node_side)); + + opin_node_[size_t(node_side)].clear(); } /* Clean chan/opin/ipin nodes at one side */ void RRGSB::clear_one_side(const e_side& node_side) { - clear_chan_nodes(node_side); - clear_ipin_nodes(node_side); - clear_opin_nodes(node_side); -} + clear_chan_nodes(node_side); + clear_ipin_nodes(node_side); + clear_opin_nodes(node_side); +} /************************************************************************ * Internal Accessors: identify mirrors @@ -946,62 +942,62 @@ void RRGSB::clear_one_side(const e_side& node_side) { * 3. each drive_rr_switch should be the same */ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph, - const RRGSB& cand, - const e_side& node_side, + const RRGSB& cand, + const e_side& node_side, const size_t& track_id) const { - /* Ensure rr_nodes are either the output of short-connection or multiplexer */ - bool is_short_conkt = this->is_sb_node_passing_wire(rr_graph, node_side, track_id); + /* Ensure rr_nodes are either the output of short-connection or multiplexer */ + bool is_short_conkt = this->is_sb_node_passing_wire(rr_graph, node_side, track_id); - if (is_short_conkt != cand.is_sb_node_passing_wire(rr_graph, node_side, track_id)) { - return false; - } + if (is_short_conkt != cand.is_sb_node_passing_wire(rr_graph, node_side, track_id)) { + return false; + } - if (true == is_short_conkt) { - /* Since, both are pass wires, + if (true == is_short_conkt) { + /* Since, both are pass wires, * The two node should be equivalent * we can return here */ - return true; - } + return true; + } - /* Use unsorted/sorted edges */ - std::vector node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id); - std::vector cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id); + /* Use unsorted/sorted edges */ + std::vector node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id); + std::vector cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id); - /* For non-passing wires, check driving rr_nodes */ - if (node_in_edges.size() != cand_node_in_edges.size()) { - return false; - } - - VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); - - for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { - RREdgeId src_edge = node_in_edges[iedge]; - RREdgeId src_cand_edge = cand_node_in_edges[iedge]; - RRNodeId src_node = rr_graph.edge_src_node(src_edge); - RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge); - /* node type should be the same */ - if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) { - return false; + /* For non-passing wires, check driving rr_nodes */ + if (node_in_edges.size() != cand_node_in_edges.size()) { + return false; } - /* switch type should be the same */ - if (rr_graph.edge_switch(src_edge) != rr_graph.edge_switch(src_cand_edge)) { - return false; + + VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); + + for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { + RREdgeId src_edge = node_in_edges[iedge]; + RREdgeId src_cand_edge = cand_node_in_edges[iedge]; + RRNodeId src_node = rr_graph.edge_src_node(src_edge); + RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge); + /* node type should be the same */ + if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) { + return false; + } + /* switch type should be the same */ + if (rr_graph.edge_switch(src_edge) != rr_graph.edge_switch(src_cand_edge)) { + return false; + } + int src_node_id, des_node_id; + enum e_side src_node_side, des_node_side; + this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id); + cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id); + if (src_node_id != des_node_id) { + return false; + } + if (src_node_side != des_node_side) { + return false; + } } - int src_node_id, des_node_id; - enum e_side src_node_side, des_node_side; - this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id); - cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id); - if (src_node_id != des_node_id) { - return false; - } - if (src_node_side != des_node_side) { - return false; - } - } - - return true; -} + + return true; +} /* check if two ipin_nodes have a similar set of drive_rr_nodes * for each drive_rr_node: @@ -1009,141 +1005,140 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph, * 2. each drive_rr_switch should be the same */ bool RRGSB::is_cb_node_mirror(const RRGraph& rr_graph, - const RRGSB& cand, + const RRGSB& cand, const t_rr_type& cb_type, - const e_side& node_side, + const e_side& node_side, const size_t& node_id) const { - /* Ensure rr_nodes are either the output of short-connection or multiplexer */ - RRNodeId node = this->get_ipin_node(node_side, node_id); - RRNodeId cand_node = cand.get_ipin_node(node_side, node_id); + /* Ensure rr_nodes are either the output of short-connection or multiplexer */ + RRNodeId node = this->get_ipin_node(node_side, node_id); + RRNodeId cand_node = cand.get_ipin_node(node_side, node_id); - if ( rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size() ) { - return false; - } - - std::vector node_in_edges; - for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { - node_in_edges.push_back(edge); - } - - std::vector cand_node_in_edges; - for (const RREdgeId& edge : rr_graph.node_in_edges(cand_node)) { - cand_node_in_edges.push_back(edge); - } - VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); - - for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { - RREdgeId src_edge = node_in_edges[iedge]; - RREdgeId src_cand_edge = cand_node_in_edges[iedge]; - RRNodeId src_node = rr_graph.edge_src_node(src_edge); - RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge); - /* node type should be the same */ - if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) { - return false; + if (rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size()) { + return false; } - /* switch type should be the same */ - if (rr_graph.edge_switch(src_edge)!= rr_graph.edge_switch(src_cand_edge)) { - return false; + + std::vector node_in_edges; + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + node_in_edges.push_back(edge); } - int src_node_id, des_node_id; - enum e_side src_node_side, des_node_side; - enum e_side chan_side = get_cb_chan_side(cb_type); - switch (rr_graph.node_type(src_node)) { - case CHANX: - case CHANY: - /* if the drive rr_nodes are routing tracks, find index */ - src_node_id = this->get_chan_node_index(chan_side, src_node); - des_node_id = cand.get_chan_node_index(chan_side, src_cand_node); - break; - case OPIN: - this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id); - cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id); - if (src_node_side != des_node_side) { - return false; - } - break; - default: - VTR_LOG("Invalid type of drive_rr_nodes for ipin_node!\n"); - exit(1); + std::vector cand_node_in_edges; + for (const RREdgeId& edge : rr_graph.node_in_edges(cand_node)) { + cand_node_in_edges.push_back(edge); + } + VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); + + for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { + RREdgeId src_edge = node_in_edges[iedge]; + RREdgeId src_cand_edge = cand_node_in_edges[iedge]; + RRNodeId src_node = rr_graph.edge_src_node(src_edge); + RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge); + /* node type should be the same */ + if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) { + return false; + } + /* switch type should be the same */ + if (rr_graph.edge_switch(src_edge) != rr_graph.edge_switch(src_cand_edge)) { + return false; + } + + int src_node_id, des_node_id; + enum e_side src_node_side, des_node_side; + enum e_side chan_side = get_cb_chan_side(cb_type); + switch (rr_graph.node_type(src_node)) { + case CHANX: + case CHANY: + /* if the drive rr_nodes are routing tracks, find index */ + src_node_id = this->get_chan_node_index(chan_side, src_node); + des_node_id = cand.get_chan_node_index(chan_side, src_cand_node); + break; + case OPIN: + this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id); + cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id); + if (src_node_side != des_node_side) { + return false; + } + break; + default: + VTR_LOG("Invalid type of drive_rr_nodes for ipin_node!\n"); + exit(1); + } + if (src_node_id != des_node_id) { + return false; + } } - if (src_node_id != des_node_id) { - return false; - } - } - return true; -} + return true; +} size_t RRGSB::get_track_id_first_short_connection(const RRGraph& rr_graph, const e_side& node_side) const { - VTR_ASSERT(validate_side(node_side)); + VTR_ASSERT(validate_side(node_side)); - /* Walk through chan_nodes and find the first short connection */ - for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { - if (true == is_sb_node_passing_wire(rr_graph, node_side, inode)) { - return inode; + /* Walk through chan_nodes and find the first short connection */ + for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { + if (true == is_sb_node_passing_wire(rr_graph, node_side, inode)) { + return inode; + } } - } - return size_t(-1); + return size_t(-1); } - /************************************************************************ * Internal validators ***********************************************************************/ /* Validate if the number of sides are consistent among internal data arrays ! */ bool RRGSB::validate_num_sides() const { - size_t num_sides = chan_node_direction_.size(); + size_t num_sides = chan_node_direction_.size(); - if ( num_sides != chan_node_.size() ) { - return false; - } + if (num_sides != chan_node_.size()) { + return false; + } - if ( num_sides != ipin_node_.size() ) { - return false; - } + if (num_sides != ipin_node_.size()) { + return false; + } - if ( num_sides != opin_node_.size() ) { - return false; - } + if (num_sides != opin_node_.size()) { + return false; + } - return true; + return true; } /* Check if the side valid in the context: does the switch block have the side? */ bool RRGSB::validate_side(const e_side& side) const { - return (size_t(side) < get_num_sides()); + return (size_t(side) < get_num_sides()); } /* Check the track_id is valid for chan_node_ and chan_node_direction_ */ bool RRGSB::validate_track_id(const e_side& side, const size_t& track_id) const { - if (false == validate_side(side)) { - return false; - } - - return ( ( track_id < chan_node_[size_t(side)].get_chan_width()) - && ( track_id < chan_node_direction_[size_t(side)].size()) ); + if (false == validate_side(side)) { + return false; + } + + return ((track_id < chan_node_[size_t(side)].get_chan_width()) + && (track_id < chan_node_direction_[size_t(side)].size())); } /* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ bool RRGSB::validate_opin_node_id(const e_side& side, const size_t& node_id) const { - if (false == validate_side(side)) { - return false; - } - return (node_id < opin_node_[size_t(side)].size()); + if (false == validate_side(side)) { + return false; + } + return (node_id < opin_node_[size_t(side)].size()); } /* Check the ipin_node_id is valid for opin_node_ and opin_node_grid_side_ */ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) const { - if (false == validate_side(side)) { - return false; - } - return (node_id < ipin_node_[size_t(side)].size()); + if (false == validate_side(side)) { + return false; + } + return (node_id < ipin_node_[size_t(side)].size()); } bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { - return ( (CHANX == cb_type) || (CHANY == cb_type) ); + return ((CHANX == cb_type) || (CHANY == cb_type)); } } /* End namespace openfpga*/ diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index 2436d170c6d..d2afce3edd7 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -26,85 +26,85 @@ namespace openfpga { * therefore, we assign tracks one by one until we meet the frequency requirement * In this way, we can assign the number of tracks with repect to frequency ***********************************************************************/ -std::vector get_num_tracks_per_seg_type(const size_t& chan_width, - const std::vector& segment_inf, +std::vector get_num_tracks_per_seg_type(const size_t& chan_width, + const std::vector& segment_inf, const bool& use_full_seg_groups) { - std::vector result; - std::vector demand; - /* Make sure a clean start */ - result.resize(segment_inf.size()); - demand.resize(segment_inf.size()); + std::vector result; + std::vector demand; + /* Make sure a clean start */ + result.resize(segment_inf.size()); + demand.resize(segment_inf.size()); - /* Scale factor so we can divide by any length + /* Scale factor so we can divide by any length * and still use integers */ - /* Get the sum of frequency */ - size_t scale = 1; - size_t freq_sum = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - scale *= segment_inf[iseg].length; - freq_sum += segment_inf[iseg].frequency; - } - size_t reduce = scale * freq_sum; - - /* Init assignments to 0 and set the demand values */ - /* Get the fraction of each segment type considering the frequency: + /* Get the sum of frequency */ + size_t scale = 1; + size_t freq_sum = 0; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + scale *= segment_inf[iseg].length; + freq_sum += segment_inf[iseg].frequency; + } + size_t reduce = scale * freq_sum; + + /* Init assignments to 0 and set the demand values */ + /* Get the fraction of each segment type considering the frequency: * num_track_per_seg = chan_width * (freq_of_seg / sum_freq) */ - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - result[iseg] = 0; - demand[iseg] = scale * chan_width * segment_inf[iseg].frequency; - if (true == use_full_seg_groups) { - demand[iseg] /= segment_inf[iseg].length; - } - } - - /* check if the sum of num_tracks, matches the chan_width */ - /* Keep assigning tracks until we use them up */ - size_t assigned = 0; - size_t size = 0; - size_t imax = 0; - while (assigned < chan_width) { - /* Find current maximum demand */ - double max = 0; for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - if (demand[iseg] > max) { - imax = iseg; - } - max = std::max(demand[iseg], max); + result[iseg] = 0; + demand[iseg] = scale * chan_width * segment_inf[iseg].frequency; + if (true == use_full_seg_groups) { + demand[iseg] /= segment_inf[iseg].length; + } } - /* Assign tracks to the type and reduce the types demand */ - size = (use_full_seg_groups ? segment_inf[imax].length : 1); - demand[imax] -= reduce; - result[imax] += size; - assigned += size; - } + /* check if the sum of num_tracks, matches the chan_width */ + /* Keep assigning tracks until we use them up */ + size_t assigned = 0; + size_t size = 0; + size_t imax = 0; + while (assigned < chan_width) { + /* Find current maximum demand */ + double max = 0; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + if (demand[iseg] > max) { + imax = iseg; + } + max = std::max(demand[iseg], max); + } + + /* Assign tracks to the type and reduce the types demand */ + size = (use_full_seg_groups ? segment_inf[imax].length : 1); + demand[imax] -= reduce; + result[imax] += size; + assigned += size; + } - /* Undo last assignment if we were closer to goal without it */ - if ((assigned - chan_width) > (size / 2)) { - result[imax] -= size; - } + /* Undo last assignment if we were closer to goal without it */ + if ((assigned - chan_width) > (size / 2)) { + result[imax] -= size; + } - return result; -} + return result; +} /************************************************************************ * Adapt the number of channel width to a tileable routing architecture ***********************************************************************/ -int adapt_to_tileable_route_chan_width(const int& chan_width, +int adapt_to_tileable_route_chan_width(const int& chan_width, const std::vector& segment_infs) { - int tileable_chan_width = 0; - - /* Estimate the number of segments per type by the given ChanW*/ - std::vector num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width, - segment_infs, - true); /* Force to use the full segment group */ - /* Sum-up the number of tracks */ - for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) { - tileable_chan_width += num_tracks_per_seg_type[iseg]; - } - - return tileable_chan_width; + int tileable_chan_width = 0; + + /* Estimate the number of segments per type by the given ChanW*/ + std::vector num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width, + segment_infs, + true); /* Force to use the full segment group */ + /* Sum-up the number of tracks */ + for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) { + tileable_chan_width += num_tracks_per_seg_type[iseg]; + } + + return tileable_chan_width; } /************************************************************************ @@ -163,72 +163,72 @@ int adapt_to_tileable_route_chan_width(const int& chan_width, ***********************************************************************/ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length, - const bool& force_start, - const bool& force_end, + const bool& force_start, + const bool& force_end, const std::vector& segment_inf) { - ChanNodeDetails chan_node_details; - size_t actual_chan_width = find_unidir_routing_channel_width(chan_width); - VTR_ASSERT(0 == actual_chan_width % 2); - - /* Reserve channel width */ - chan_node_details.reserve(chan_width); - /* Return if zero width is forced */ - if (0 == actual_chan_width) { - return chan_node_details; - } - - /* Find the number of segments required by each group */ - std::vector num_tracks = get_num_tracks_per_seg_type(actual_chan_width / 2, segment_inf, false); - - /* Add node to ChanNodeDetails */ - size_t cur_track = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - /* segment length will be set to maxium segment length if this is a longwire */ - size_t seg_len = segment_inf[iseg].length; - if (true == segment_inf[iseg].longline) { - seg_len = max_seg_length; - } - for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { - bool seg_start = false; - bool seg_end = false; - /* Every first track of a group of Length-N wires, we set a starting point */ - if (0 == itrack % seg_len) { - seg_start = true; - } - /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ - if ( (seg_len - 1 == itrack % seg_len) - || (itrack == num_tracks[iseg] - 1) ) { - seg_end = true; - } - /* Since this is a unidirectional routing architecture, + ChanNodeDetails chan_node_details; + size_t actual_chan_width = find_unidir_routing_channel_width(chan_width); + VTR_ASSERT(0 == actual_chan_width % 2); + + /* Reserve channel width */ + chan_node_details.reserve(chan_width); + /* Return if zero width is forced */ + if (0 == actual_chan_width) { + return chan_node_details; + } + + /* Find the number of segments required by each group */ + std::vector num_tracks = get_num_tracks_per_seg_type(actual_chan_width / 2, segment_inf, false); + + /* Add node to ChanNodeDetails */ + size_t cur_track = 0; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + /* segment length will be set to maxium segment length if this is a longwire */ + size_t seg_len = segment_inf[iseg].length; + if (true == segment_inf[iseg].longline) { + seg_len = max_seg_length; + } + for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { + bool seg_start = false; + bool seg_end = false; + /* Every first track of a group of Length-N wires, we set a starting point */ + if (0 == itrack % seg_len) { + seg_start = true; + } + /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ + if ((seg_len - 1 == itrack % seg_len) + || (itrack == num_tracks[iseg] - 1)) { + seg_end = true; + } + /* Since this is a unidirectional routing architecture, * Add a pair of tracks, 1 INC track and 1 DEC track */ - chan_node_details.add_track(cur_track, Direction::INC, iseg, seg_len, seg_start, seg_end); - cur_track++; - chan_node_details.add_track(cur_track, Direction::DEC, iseg, seg_len, seg_start, seg_end); - cur_track++; - } - } - /* Check if all the tracks have been satisified */ - VTR_ASSERT(cur_track == actual_chan_width); - - /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ - if (true == force_start) { - /* INC should all start */ - chan_node_details.set_tracks_start(Direction::INC); - /* DEC should all end */ - chan_node_details.set_tracks_end(Direction::DEC); - } - - /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ - if (true == force_end) { - /* INC should all end */ - chan_node_details.set_tracks_end(Direction::INC); - /* DEC should all start */ - chan_node_details.set_tracks_start(Direction::DEC); - } - - return chan_node_details; + chan_node_details.add_track(cur_track, Direction::INC, iseg, seg_len, seg_start, seg_end); + cur_track++; + chan_node_details.add_track(cur_track, Direction::DEC, iseg, seg_len, seg_start, seg_end); + cur_track++; + } + } + /* Check if all the tracks have been satisified */ + VTR_ASSERT(cur_track == actual_chan_width); + + /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ + if (true == force_start) { + /* INC should all start */ + chan_node_details.set_tracks_start(Direction::INC); + /* DEC should all end */ + chan_node_details.set_tracks_end(Direction::DEC); + } + + /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ + if (true == force_end) { + /* INC should all end */ + chan_node_details.set_tracks_end(Direction::INC); + /* DEC should all start */ + chan_node_details.set_tracks_start(Direction::DEC); + } + + return chan_node_details; } } /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 43c41de5416..198c2fc5e1c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -72,126 +72,127 @@ namespace openfpga { // external functions: in vpr/src/route/rr_graph.cpp extern std::vector> alloc_and_load_actual_fc(const std::vector& types, - const int max_pins, - const std::vector& segment_inf, - - const int* sets_per_seg_type, - const int max_chan_width, - const e_fc_type fc_type, - const enum e_directionality directionality, - bool* Fc_clipped); -extern t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch); + const int max_pins, + const std::vector& segment_inf, + + const int* sets_per_seg_type, + const int max_chan_width, + const e_fc_type fc_type, + const enum e_directionality directionality, + bool* Fc_clipped); +extern t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch); extern void alloc_and_load_rr_switch_inf(const int num_arch_switches, - const float R_minW_nmos, - const float R_minW_pmos, - const int wire_to_arch_ipin_switch, - int* wire_to_rr_ipin_switch); + const float R_minW_nmos, + const float R_minW_pmos, + const int wire_to_arch_ipin_switch, + int* wire_to_rr_ipin_switch); extern void rr_graph_externals(const std::vector& segment_inf, - int wire_to_rr_ipin_switch, - enum e_base_cost_type base_cost_type); + int wire_to_rr_ipin_switch, + enum e_base_cost_type base_cost_type); void build_tileable_unidir_rr_graph(const std::vector& types, const DeviceGrid& grids, const t_chan_width& chan_width, - const e_switch_block_type& sb_type, const int& Fs, - const e_switch_block_type& sb_subtype, const int& subFs, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, const std::vector& segment_inf, const int& delayless_switch, const int& wire_to_arch_ipin_switch, const float R_minW_nmos, const float R_minW_pmos, const enum e_base_cost_type& base_cost_type, - const t_direct_inf *directs, + const t_direct_inf* directs, const int& num_directs, int* wire_to_rr_ipin_switch, const bool& through_channel, const bool& wire_opposite_side, - int *Warnings) { + int* Warnings) { + vtr::ScopedStartFinishTimer timer("Build tileable routing resource graph"); - vtr::ScopedStartFinishTimer timer("Build tileable routing resource graph"); + /* Reset warning flag */ + *Warnings = RR_GRAPH_NO_WARN; - /* Reset warning flag */ - *Warnings = RR_GRAPH_NO_WARN; + /* Create a matrix of grid */ + /* Create a vector of channel width, we support X-direction and Y-direction has different W */ + vtr::Point device_chan_width(chan_width.x_max, chan_width.y_max); - /* Create a matrix of grid */ - /* Create a vector of channel width, we support X-direction and Y-direction has different W */ - vtr::Point device_chan_width(chan_width.x_max, chan_width.y_max); + VTR_LOG("X-direction routing channel width is %lu\n", device_chan_width.x()); + VTR_LOG("Y-direction routing channel width is %lu\n", device_chan_width.y()); - VTR_LOG("X-direction routing channel width is %lu\n", device_chan_width.x()); - VTR_LOG("Y-direction routing channel width is %lu\n", device_chan_width.y()); + /* Get a mutable device ctx so that we have a mutable rr_graph */ + DeviceContext& device_ctx = g_vpr_ctx.mutable_device(); - /* Get a mutable device ctx so that we have a mutable rr_graph */ - DeviceContext& device_ctx = g_vpr_ctx.mutable_device(); - - /* The number of segments are in general small, reserve segments may not bring + /* The number of segments are in general small, reserve segments may not bring * significant memory efficiency */ - device_ctx.rr_graph_builder.reserve_segments(segment_inf.size()); - /* Create the segments */ - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - device_ctx.rr_graph_builder.add_rr_segment(segment_inf[iseg]); - } + device_ctx.rr_graph_builder.reserve_segments(segment_inf.size()); + /* Create the segments */ + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + device_ctx.rr_graph_builder.add_rr_segment(segment_inf[iseg]); + } - /* TODO: Load architecture switch to rr_graph switches + /* TODO: Load architecture switch to rr_graph switches * Draft the switches as internal data of RRGraph object * These are temporary switches copied from arch switches * We use them to build the edges * We will reset all the switches in the function * alloc_and_load_rr_switch_inf() */ - /* TODO: Spot the switch id in the architecture switch list */ - RRSwitchId wire_to_ipin_rr_switch = RRSwitchId::INVALID(); - RRSwitchId delayless_rr_switch = RRSwitchId::INVALID(); - - device_ctx.rr_graph_builder.reserve_switches(device_ctx.num_arch_switches); - /* Create the switches */ - for (int iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) { - const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(iswitch, R_minW_nmos, R_minW_pmos); - RRSwitchId rr_switch = device_ctx.rr_graph_builder.add_rr_switch(temp_rr_switch); - if (iswitch == wire_to_arch_ipin_switch) { - wire_to_ipin_rr_switch = rr_switch; - } - if (iswitch == delayless_switch) { - delayless_rr_switch = rr_switch; + /* TODO: Spot the switch id in the architecture switch list */ + RRSwitchId wire_to_ipin_rr_switch = RRSwitchId::INVALID(); + RRSwitchId delayless_rr_switch = RRSwitchId::INVALID(); + + device_ctx.rr_graph_builder.reserve_switches(device_ctx.num_arch_switches); + /* Create the switches */ + for (int iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) { + const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(iswitch, R_minW_nmos, R_minW_pmos); + RRSwitchId rr_switch = device_ctx.rr_graph_builder.add_rr_switch(temp_rr_switch); + if (iswitch == wire_to_arch_ipin_switch) { + wire_to_ipin_rr_switch = rr_switch; + } + if (iswitch == delayless_switch) { + delayless_rr_switch = rr_switch; + } } - } - // NYI - #if 0 +// NYI +#if 0 /* Validate the special switches */ VTR_ASSERT(true == device_ctx.rr_graph_builder.valid_switch_id(wire_to_ipin_rr_switch)); VTR_ASSERT(true == device_ctx.rr_graph_builder.valid_switch_id(delayless_rr_switch)); - #endif +#endif - /* A temp data about the driver switch ids for each rr_node */ - vtr::vector rr_node_driver_switches; + /* A temp data about the driver switch ids for each rr_node */ + vtr::vector rr_node_driver_switches; - /* A temp data about the track ids for each CHANX and CHANY rr_node */ - std::map> rr_node_track_ids; + /* A temp data about the track ids for each CHANX and CHANY rr_node */ + std::map> rr_node_track_ids; - /************************ + /************************ * Allocate the rr_nodes ************************/ - alloc_tileable_rr_graph_nodes(device_ctx.rr_graph_builder, - rr_node_driver_switches, - grids, - device_chan_width, - segment_inf, - through_channel); - - /************************ + alloc_tileable_rr_graph_nodes(device_ctx.rr_graph_builder, + rr_node_driver_switches, + grids, + device_chan_width, + segment_inf, + through_channel); + + /************************ * Create all the rr_nodes ************************/ - create_tileable_rr_graph_nodes(device_ctx.rr_graph, - device_ctx.rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - grids, - device_chan_width, - segment_inf, - wire_to_ipin_rr_switch, - delayless_rr_switch, - through_channel); - - /************************************************************************ + create_tileable_rr_graph_nodes(device_ctx.rr_graph, + device_ctx.rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + device_chan_width, + segment_inf, + wire_to_ipin_rr_switch, + delayless_rr_switch, + through_channel); + + /************************************************************************ * Create the connectivity of OPINs * a. Evenly assign connections to OPINs to routing tracks * b. the connection pattern should be same across the fabric @@ -200,52 +201,52 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * a. Evenly assign connections from routing tracks to IPINs * b. the connection pattern should be same across the fabric ***********************************************************************/ - /* Global routing uses a single longwire track */ - int max_chan_width = find_unidir_routing_channel_width(chan_width.max); - VTR_ASSERT(max_chan_width > 0); - - /* get maximum number of pins across all blocks */ - int max_pins = types[0].num_pins; - for (const auto& type : types) { - if (is_empty_type(&type)) { - continue; - } - - if (type.num_pins > max_pins) { - max_pins = type.num_pins; + /* Global routing uses a single longwire track */ + int max_chan_width = find_unidir_routing_channel_width(chan_width.max); + VTR_ASSERT(max_chan_width > 0); + + /* get maximum number of pins across all blocks */ + int max_pins = types[0].num_pins; + for (const auto& type : types) { + if (is_empty_type(&type)) { + continue; + } + + if (type.num_pins > max_pins) { + max_pins = type.num_pins; + } } - } - /* Fc assignment still uses the old function from VPR. + /* Fc assignment still uses the old function from VPR. * Should use tileable version so that we have can have full control */ - std::vector num_tracks = get_num_tracks_per_seg_type(max_chan_width / 2, segment_inf, false); - int* sets_per_seg_type = (int*)vtr::malloc(sizeof(int) * segment_inf.size()); - VTR_ASSERT(num_tracks.size() == segment_inf.size()); - for (size_t iseg = 0; iseg < num_tracks.size(); ++iseg) { - sets_per_seg_type[iseg] = num_tracks[iseg]; - } + std::vector num_tracks = get_num_tracks_per_seg_type(max_chan_width / 2, segment_inf, false); + int* sets_per_seg_type = (int*)vtr::malloc(sizeof(int) * segment_inf.size()); + VTR_ASSERT(num_tracks.size() == segment_inf.size()); + for (size_t iseg = 0; iseg < num_tracks.size(); ++iseg) { + sets_per_seg_type[iseg] = num_tracks[iseg]; + } - bool Fc_clipped = false; - /* [0..num_types-1][0..num_pins-1] */ - std::vector> Fc_in; - Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width, - e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped); - if (Fc_clipped) { - *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; - } + bool Fc_clipped = false; + /* [0..num_types-1][0..num_pins-1] */ + std::vector> Fc_in; + Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width, + e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped); + if (Fc_clipped) { + *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; + } - Fc_clipped = false; - /* [0..num_types-1][0..num_pins-1] */ - std::vector> Fc_out; - Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width, - e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped); + Fc_clipped = false; + /* [0..num_types-1][0..num_pins-1] */ + std::vector> Fc_out; + Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width, + e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped); - if (Fc_clipped) { - *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; - } + if (Fc_clipped) { + *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; + } - /************************************************************************ + /************************************************************************ * Build the connections tile by tile: * We classify rr_nodes into a general switch block (GSB) data structure * where we create edges to each rr_nodes in the GSB with respect to @@ -253,34 +254,34 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * In addition, we will also handle direct-connections: * Add edges that bridge OPINs and IPINs to the rr_graph ***********************************************************************/ - /* Create edges for a tileable rr_graph */ - build_rr_graph_edges(device_ctx.rr_graph, - rr_node_driver_switches, - grids, - device_chan_width, - segment_inf, - Fc_in, Fc_out, - sb_type, Fs, sb_subtype, subFs, - wire_opposite_side); - - /************************************************************************ + /* Create edges for a tileable rr_graph */ + build_rr_graph_edges(device_ctx.rr_graph, + rr_node_driver_switches, + grids, + device_chan_width, + segment_inf, + Fc_in, Fc_out, + sb_type, Fs, sb_subtype, subFs, + wire_opposite_side); + + /************************************************************************ * Build direction connection lists * TODO: use tile direct builder ***********************************************************************/ - /* Create data structure of direct-connections */ - t_clb_to_clb_directs* clb_to_clb_directs = NULL; - if (num_directs > 0) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs, delayless_switch); - } - std::vector arch_directs; - std::vector clb2clb_directs; - for (int idirect = 0; idirect < num_directs; ++idirect) { - arch_directs.push_back(directs[idirect]); - clb2clb_directs.push_back(clb_to_clb_directs[idirect]); - } + /* Create data structure of direct-connections */ + t_clb_to_clb_directs* clb_to_clb_directs = NULL; + if (num_directs > 0) { + clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs, delayless_switch); + } + std::vector arch_directs; + std::vector clb2clb_directs; + for (int idirect = 0; idirect < num_directs; ++idirect) { + arch_directs.push_back(directs[idirect]); + clb2clb_directs.push_back(clb_to_clb_directs[idirect]); + } - build_rr_graph_direct_connections(device_ctx.rr_graph, grids, delayless_rr_switch, - arch_directs, clb2clb_directs); + build_rr_graph_direct_connections(device_ctx.rr_graph, grids, delayless_rr_switch, + arch_directs, clb2clb_directs); //NYI #if 0 @@ -290,12 +291,12 @@ void build_tileable_unidir_rr_graph(const std::vector& typ device_ctx.rr_graph.rebuild_node_edges(); #endif - /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, + /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ - alloc_and_load_rr_switch_inf(device_ctx.num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); + alloc_and_load_rr_switch_inf(device_ctx.num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); - /* Save the channel widths for the newly constructed graph */ - device_ctx.chan_width = chan_width; + /* Save the channel widths for the newly constructed graph */ + device_ctx.chan_width = chan_width; //NYI #if 0 @@ -303,49 +304,48 @@ void build_tileable_unidir_rr_graph(const std::vector& typ device_ctx.rr_node_track_ids = rr_node_track_ids; #endif - /************************************************************************ + /************************************************************************ * Allocate external data structures * a. cost_index * b. RC tree ***********************************************************************/ - rr_graph_externals(segment_inf, - *wire_to_rr_ipin_switch, base_cost_type); + rr_graph_externals(segment_inf, + *wire_to_rr_ipin_switch, base_cost_type); - /* Rebuild the link between RRGraph node and segments + /* Rebuild the link between RRGraph node and segments * Should be called only AFTER the function * rr_graph_externals() */ - for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { - if ( (CHANX != device_ctx.rr_graph.node_type(inode)) - && (CHANY != device_ctx.rr_graph.node_type(inode)) ) { - continue; - } + for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { + if ((CHANX != device_ctx.rr_graph.node_type(inode)) + && (CHANY != device_ctx.rr_graph.node_type(inode))) { + continue; + } //NYI #if 0 RRIndexedDataId irc_data = device_ctx.rr_graph.node_cost_index(inode); short iseg = device_ctx.rr_indexed_data[irc_data].seg_index; device_ctx.rr_graph_builder.set_node_segment(inode, RRSegmentId(iseg)); // NYI #endif + } - } - - /************************************************************************ + /************************************************************************ * Sanitizer for the rr_graph, check connectivities of rr_nodes ***********************************************************************/ - /* Essential check for rr_graph, build look-up and */ - if (false == device_ctx.rr_graph_builder.validate()) { - /* Error out if built-in validator of rr_graph fails */ - vpr_throw(VPR_ERROR_ROUTE, - __FILE__, - __LINE__, - "Fundamental errors occurred when validating rr_graph object!\n"); - } + /* Essential check for rr_graph, build look-up and */ + if (false == device_ctx.rr_graph_builder.validate()) { + /* Error out if built-in validator of rr_graph fails */ + vpr_throw(VPR_ERROR_ROUTE, + __FILE__, + __LINE__, + "Fundamental errors occurred when validating rr_graph object!\n"); + } - check_rr_graph(GRAPH_UNIDIR, grids, types); + check_rr_graph(GRAPH_UNIDIR, grids, types); - // NYI - // vpr integration: DeviceContext does not provide direct RRGraph access - // we can skip it since check_rr_graph(GRAPH_UNDIR, GRIDS, TYPES) has been called above + // NYI + // vpr integration: DeviceContext does not provide direct RRGraph access + // we can skip it since check_rr_graph(GRAPH_UNDIR, GRIDS, TYPES) has been called above #if 0 /* Error out if advanced checker of rr_graph fails */ if (false == check_rr_graph(device_ctx.rr_graph)) { @@ -357,14 +357,14 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } #endif - /************************************************************************ + /************************************************************************ * Free all temp stucts ***********************************************************************/ - free(sets_per_seg_type); + free(sets_per_seg_type); - if (nullptr != clb_to_clb_directs) { - free(clb_to_clb_directs); - } + if (nullptr != clb_to_clb_directs) { + free(clb_to_clb_directs); + } } } /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index fd2d4db62d8..3252bd412c9 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -22,59 +22,57 @@ namespace openfpga { * Build the edges for all the SOURCE and SINKs nodes: * 1. create edges between SOURCE and OPINs ***********************************************************************/ -static -void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, - const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids) { - for (const RRNodeId& node : rr_graph.nodes()) { - /* Bypass all the non OPIN nodes */ - if (OPIN != rr_graph.node_type(node)) { - continue; +static void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids) { + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass all the non OPIN nodes */ + if (OPIN != rr_graph.node_type(node)) { + continue; + } + /* Now, we have an OPIN node, we get the source node index */ + short xlow = rr_graph.node_xlow(node); + short ylow = rr_graph.node_ylow(node); + short src_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], + rr_graph.node_pin_num(node)); + + /* Create edges between SOURCE and OPINs */ + const RRNodeId& src_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, + ylow - grids[xlow][ylow].height_offset, + SOURCE, src_node_class_num); + VTR_ASSERT(true == rr_graph.valid_node_id(src_node)); + + /* add edges to the src_node */ + rr_graph.create_edge(src_node, node, rr_node_driver_switches[node]); } - /* Now, we have an OPIN node, we get the source node index */ - short xlow = rr_graph.node_xlow(node); - short ylow = rr_graph.node_ylow(node); - short src_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], - rr_graph.node_pin_num(node)); - - /* Create edges between SOURCE and OPINs */ - const RRNodeId& src_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, - ylow - grids[xlow][ylow].height_offset, - SOURCE, src_node_class_num); - VTR_ASSERT(true == rr_graph.valid_node_id(src_node)); - - /* add edges to the src_node */ - rr_graph.create_edge(src_node, node, rr_node_driver_switches[node]); - } } /************************************************************************ * Build the edges for all the SINKs nodes: * 1. create edges between IPINs and SINKs ***********************************************************************/ -static -void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, - const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids) { - for (const RRNodeId& node : rr_graph.nodes()) { - /* Bypass all the non IPIN nodes */ - if (IPIN != rr_graph.node_type(node)) { - continue; +static void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids) { + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass all the non IPIN nodes */ + if (IPIN != rr_graph.node_type(node)) { + continue; + } + /* Now, we have an OPIN node, we get the source node index */ + short xlow = rr_graph.node_xlow(node); + short ylow = rr_graph.node_ylow(node); + short sink_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], + rr_graph.node_pin_num(node)); + /* 1. create edges between IPINs and SINKs */ + const RRNodeId& sink_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, + ylow - grids[xlow][ylow].height_offset, + SINK, sink_node_class_num); + VTR_ASSERT(true == rr_graph.valid_node_id(sink_node)); + + /* add edges to connect the IPIN node to SINK nodes */ + rr_graph.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); } - /* Now, we have an OPIN node, we get the source node index */ - short xlow = rr_graph.node_xlow(node); - short ylow = rr_graph.node_ylow(node); - short sink_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], - rr_graph.node_pin_num(node)); - /* 1. create edges between IPINs and SINKs */ - const RRNodeId& sink_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, - ylow - grids[xlow][ylow].height_offset, - SINK, sink_node_class_num); - VTR_ASSERT(true == rr_graph.valid_node_id(sink_node)); - - /* add edges to connect the IPIN node to SINK nodes */ - rr_graph.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); - } } /************************************************************************ @@ -87,84 +85,85 @@ void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) * 3. create edges between OPINs and IPINs (direct-connections) ***********************************************************************/ -void build_rr_graph_edges(RRGraph& rr_graph, +void build_rr_graph_edges(RRGraph& rr_graph, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, - const vtr::Point& device_chan_width, + const vtr::Point& device_chan_width, const std::vector& segment_inf, const std::vector>& Fc_in, const std::vector>& Fc_out, - const e_switch_block_type& sb_type, const int& Fs, - const e_switch_block_type& sb_subtype, const int& subFs, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, const bool& wire_opposite_side) { - - /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ - build_rr_graph_edges_for_source_nodes(rr_graph, rr_node_driver_switches, grids); - build_rr_graph_edges_for_sink_nodes(rr_graph, rr_node_driver_switches, grids); - - vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); - - /* Go Switch Block by Switch Block */ - for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { - for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { - //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); - - vtr::Point gsb_coord(ix, iy); - /* Create a GSB object */ - const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, - device_chan_width, segment_inf, - gsb_coord); - - /* adapt the track_to_ipin_lookup for the GSB nodes */ - t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ - track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); - - /* adapt the opin_to_track_map for the GSB nodes */ - t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ - opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out); - - /* adapt the switch_block_conn for the GSB nodes */ - t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ - sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, sb_subtype, subFs, wire_opposite_side, - segment_inf); - - /* Build edges for a GSB */ - build_edges_for_one_tileable_rr_gsb(rr_graph, rr_gsb, - track2ipin_map, opin2track_map, - sb_conn, rr_node_driver_switches); - /* Finish this GSB, go to the next*/ + /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ + build_rr_graph_edges_for_source_nodes(rr_graph, rr_node_driver_switches, grids); + build_rr_graph_edges_for_sink_nodes(rr_graph, rr_node_driver_switches, grids); + + vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); + + /* Go Switch Block by Switch Block */ + for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { + for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { + //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); + + vtr::Point gsb_coord(ix, iy); + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf, + gsb_coord); + + /* adapt the track_to_ipin_lookup for the GSB nodes */ + t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); + + /* adapt the opin_to_track_map for the GSB nodes */ + t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out); + + /* adapt the switch_block_conn for the GSB nodes */ + t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, sb_subtype, subFs, wire_opposite_side, + segment_inf); + + /* Build edges for a GSB */ + build_edges_for_one_tileable_rr_gsb(rr_graph, rr_gsb, + track2ipin_map, opin2track_map, + sb_conn, rr_node_driver_switches); + /* Finish this GSB, go to the next*/ + } } - } } /************************************************************************ * Build direct edges for Grids * ***********************************************************************/ -void build_rr_graph_direct_connections(RRGraph& rr_graph, - const DeviceGrid& grids, - const RRSwitchId& delayless_switch, - const std::vector& directs, +void build_rr_graph_direct_connections(RRGraph& rr_graph, + const DeviceGrid& grids, + const RRSwitchId& delayless_switch, + const std::vector& directs, const std::vector& clb_to_clb_directs) { - for (size_t ix = 0; ix < grids.width(); ++ix) { - for (size_t iy = 0; iy < grids.height(); ++iy) { - /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { - continue; - } - /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ( (0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset) ) { - continue; - } - vtr::Point from_grid_coordinate(ix, iy); - build_direct_connections_for_one_gsb(rr_graph, - grids, - from_grid_coordinate, - delayless_switch, - directs, clb_to_clb_directs); + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ((0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset)) { + continue; + } + vtr::Point from_grid_coordinate(ix, iy); + build_direct_connections_for_one_gsb(rr_graph, + grids, + from_grid_coordinate, + delayless_switch, + directs, clb_to_clb_directs); + } } - } } - + } /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index a20cef71712..936b9944f50 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -1,6 +1,3 @@ -#ifndef TILEABLE_RR_GRAPH_EDGE_BUILDER_H -#define TILEABLE_RR_GRAPH_EDGE_BUILDER_H - /******************************************************************** * Include header files that are required by function declaration *******************************************************************/ @@ -41,5 +38,3 @@ void build_rr_graph_direct_connections(RRGraphView& rr_graph, const std::vector& clb_to_clb_directs); } /* end namespace openfpga */ - -#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 0fc75853dfb..6aab10566ea 100755 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -35,10 +35,10 @@ typedef std::vector> t_track_group; * track-to-track mapping matrix ***********************************************************************/ enum e_track_status { - TRACK_START, - TRACK_END, - TRACK_PASS, - NUM_TRACK_STATUS /* just a place holder to get the number of status */ + TRACK_START, + TRACK_END, + TRACK_PASS, + NUM_TRACK_STATUS /* just a place holder to get the number of status */ }; /************************************************************************ @@ -48,42 +48,41 @@ enum e_track_status { * Check if a track ends at this GSB or not * (xhigh, yhigh) should be same as the GSB side coordinate ***********************************************************************/ -static -enum e_track_status determine_track_status_of_gsb(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const enum e_side& gsb_side, - const size_t& track_id) { - enum e_track_status track_status = TRACK_PASS; - /* Get the rr_node */ - RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id); - /* Get the coordinates */ - vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); - - /* Get the coordinate of where the track starts */ - vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); - - /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */ - /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */ - if ( (track_start.x() == side_coordinate.x()) - && (track_start.y() == side_coordinate.y()) - && (OUT_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id)) ) { - /* Double check: start track should be an OUTPUT PORT of the GSB */ - track_status = TRACK_START; - } - - /* Get the coordinate of where the track ends */ - vtr::Point track_end = get_track_rr_node_end_coordinate(rr_graph, track_node); - - /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ - /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ - if ( (track_end.x() == side_coordinate.x()) - && (track_end.y() == side_coordinate.y()) - && (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id)) ) { - /* Double check: end track should be an INPUT PORT of the GSB */ - track_status = TRACK_END; - } - - return track_status; +static enum e_track_status determine_track_status_of_gsb(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& gsb_side, + const size_t& track_id) { + enum e_track_status track_status = TRACK_PASS; + /* Get the rr_node */ + RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + /* Get the coordinate of where the track starts */ + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */ + /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + if ((track_start.x() == side_coordinate.x()) + && (track_start.y() == side_coordinate.y()) + && (OUT_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id))) { + /* Double check: start track should be an OUTPUT PORT of the GSB */ + track_status = TRACK_START; + } + + /* Get the coordinate of where the track ends */ + vtr::Point track_end = get_track_rr_node_end_coordinate(rr_graph, track_node); + + /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ + if ((track_end.x() == side_coordinate.x()) + && (track_end.y() == side_coordinate.y()) + && (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id))) { + /* Double check: end track should be an INPUT PORT of the GSB */ + track_status = TRACK_END; + } + + return track_status; } /************************************************************************ @@ -98,35 +97,34 @@ enum e_track_status determine_track_status_of_gsb(const RRGraph& rr_graph, * We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track * Use the offset to check if the tracks should engage in this GSB connection ***********************************************************************/ -static -bool is_gsb_in_track_cb_population(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const e_side& gsb_side, - const int& track_id, - const std::vector& segment_inf) { - /* Get the rr_node */ - RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id); - /* Get the coordinates */ - vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); - - vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); - - /* Get the offset */ - size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) - + std::abs((int)side_coordinate.y() - (int)track_start.y()); - - /* Get segment id */ - RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); - /* validate offset */ - VTR_ASSERT(offset < segment_inf[size_t(seg_id)].cb.size()); - - /* Get the SB population */ - bool in_cb_population = false; - if (true == segment_inf[size_t(seg_id)].cb[offset]) { - in_cb_population = true; - } - - return in_cb_population; +static bool is_gsb_in_track_cb_population(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const e_side& gsb_side, + const int& track_id, + const std::vector& segment_inf) { + /* Get the rr_node */ + RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* Get the offset */ + size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) + + std::abs((int)side_coordinate.y() - (int)track_start.y()); + + /* Get segment id */ + RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); + /* validate offset */ + VTR_ASSERT(offset < segment_inf[size_t(seg_id)].cb.size()); + + /* Get the SB population */ + bool in_cb_population = false; + if (true == segment_inf[size_t(seg_id)].cb[offset]) { + in_cb_population = true; + } + + return in_cb_population; } /************************************************************************ @@ -141,35 +139,34 @@ bool is_gsb_in_track_cb_population(const RRGraph& rr_graph, * We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track * Use the offset to check if the tracks should engage in this GSB connection ***********************************************************************/ -static -bool is_gsb_in_track_sb_population(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const e_side& gsb_side, - const int& track_id, - const std::vector& segment_inf) { - /* Get the rr_node */ - const RRNodeId& track_node = rr_gsb.get_chan_node(gsb_side, track_id); - /* Get the coordinates */ - vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); - - vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); - - /* Get the offset */ - size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) - + std::abs((int)side_coordinate.y() - (int)track_start.y()); - - /* Get segment id */ - RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); - /* validate offset */ - VTR_ASSERT(offset < segment_inf[size_t(seg_id)].sb.size()); - - /* Get the SB population */ - bool in_sb_population = false; - if (true == segment_inf[size_t(seg_id)].sb[offset]) { - in_sb_population = true; - } - - return in_sb_population; +static bool is_gsb_in_track_sb_population(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const e_side& gsb_side, + const int& track_id, + const std::vector& segment_inf) { + /* Get the rr_node */ + const RRNodeId& track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* Get the offset */ + size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) + + std::abs((int)side_coordinate.y() - (int)track_start.y()); + + /* Get segment id */ + RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); + /* validate offset */ + VTR_ASSERT(offset < segment_inf[size_t(seg_id)].sb.size()); + + /* Get the SB population */ + bool in_sb_population = false; + if (true == segment_inf[size_t(seg_id)].sb[offset]) { + in_sb_population = true; + } + + return in_sb_population; } /************************************************************************ @@ -177,25 +174,24 @@ bool is_gsb_in_track_sb_population(const RRGraph& rr_graph, * We consider the following list [to_track, to_track + Fs/3 - 1] * if the [to_track + Fs/3 - 1] exceeds the num_to_tracks, we start over from 0! ***********************************************************************/ -static -std::vector get_to_track_list(const int& Fs, const int& to_track, const int& num_to_tracks) { - std::vector to_tracks; +static std::vector get_to_track_list(const int& Fs, const int& to_track, const int& num_to_tracks) { + std::vector to_tracks; - for (int i = 0; i < Fs; i = i + 3) { - /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied + for (int i = 0; i < Fs; i = i + 3) { + /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied * The optimal track selection should be done in a more scientific way!!! */ - int to_track_i = to_track + i; - /* make sure the track id is still in range */ - if ( to_track_i > num_to_tracks - 1) { - to_track_i = to_track_i % num_to_tracks; + int to_track_i = to_track + i; + /* make sure the track id is still in range */ + if (to_track_i > num_to_tracks - 1) { + to_track_i = to_track_i % num_to_tracks; + } + /* Ensure we are in the range */ + VTR_ASSERT(to_track_i < num_to_tracks); + /* from track must be connected */ + to_tracks.push_back(to_track_i); } - /* Ensure we are in the range */ - VTR_ASSERT(to_track_i < num_to_tracks); - /* from track must be connected */ - to_tracks.push_back(to_track_i); - } - return to_tracks; + return to_tracks; } /************************************************************************ @@ -204,196 +200,192 @@ std::vector get_to_track_list(const int& Fs, const int& to_track, const * The track_ids to return will depend on different topologies of SB * SUBSET, UNIVERSAL, and WILTON. ***********************************************************************/ -static -std::vector get_switch_block_to_track_id(const e_switch_block_type& switch_block_type, - const int& Fs, - const e_side& from_side, - const int& from_track, - const e_side& to_side, - const int& num_to_tracks) { - - /* This routine returns the track number to which the from_track should +static std::vector get_switch_block_to_track_id(const e_switch_block_type& switch_block_type, + const int& Fs, + const e_side& from_side, + const int& from_track, + const e_side& to_side, + const int& num_to_tracks) { + /* This routine returns the track number to which the from_track should * connect. It supports any Fs % 3 == 0, switch blocks. */ - std::vector to_tracks; + std::vector to_tracks; - /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied + /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied * The optimal track selection should be done in a more scientific way!!! */ - VTR_ASSERT(0 == Fs % 3); - - /* Adapt from_track to fit in the range of num_to_tracks */ - size_t actual_from_track = from_track % num_to_tracks; - - switch (switch_block_type) { - case SUBSET: /* NB: Global routing uses SUBSET too */ - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - /* Finish, we return */ - return to_tracks; - case UNIVERSAL: - if ( (from_side == LEFT) - || (from_side == RIGHT) ) { - /* For the prev_side, to_track is from_track + VTR_ASSERT(0 == Fs % 3); + + /* Adapt from_track to fit in the range of num_to_tracks */ + size_t actual_from_track = from_track % num_to_tracks; + + switch (switch_block_type) { + case SUBSET: /* NB: Global routing uses SUBSET too */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + /* Finish, we return */ + return to_tracks; + case UNIVERSAL: + if ((from_side == LEFT) + || (from_side == RIGHT)) { + /* For the prev_side, to_track is from_track * For the next_side, to_track is num_to_tracks - 1 - from_track * For the opposite_side, to_track is always from_track */ - SideManager side_manager(from_side); - if ( (to_side == side_manager.get_opposite()) - || (to_side == side_manager.get_rotate_counterclockwise()) ) { - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == side_manager.get_rotate_clockwise()) { - to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); - } - } - - if ( (from_side == TOP) - || (from_side == BOTTOM) ) { - /* For the next_side, to_track is from_track + SideManager side_manager(from_side); + if ((to_side == side_manager.get_opposite()) + || (to_side == side_manager.get_rotate_counterclockwise())) { + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == side_manager.get_rotate_clockwise()) { + to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); + } + } + + if ((from_side == TOP) + || (from_side == BOTTOM)) { + /* For the next_side, to_track is from_track * For the prev_side, to_track is num_to_tracks - 1 - from_track * For the opposite_side, to_track is always from_track */ - SideManager side_manager(from_side); - if ( (to_side == side_manager.get_opposite()) - || (to_side == side_manager.get_rotate_clockwise()) ) { - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == side_manager.get_rotate_counterclockwise()) { - to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); - } + SideManager side_manager(from_side); + if ((to_side == side_manager.get_opposite()) + || (to_side == side_manager.get_rotate_clockwise())) { + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == side_manager.get_rotate_counterclockwise()) { + to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); + } + } + /* Finish, we return */ + return to_tracks; + /* End switch_block_type == UNIVERSAL case. */ + case WILTON: + /* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */ + if (from_side == LEFT) { + if (to_side == RIGHT) { /* CHANX to CHANX */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track) % num_to_tracks, num_to_tracks); + } else if (to_side == BOTTOM) { + to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); + } + } else if (from_side == RIGHT) { + if (to_side == LEFT) { /* CHANX to CHANX */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); + } else if (to_side == BOTTOM) { + to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); + } + } else if (from_side == BOTTOM) { + if (to_side == TOP) { /* CHANY to CHANY */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); + } else if (to_side == RIGHT) { + to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); + } + } else if (from_side == TOP) { + if (to_side == BOTTOM) { /* CHANY to CHANY */ + to_tracks = get_to_track_list(Fs, from_track, num_to_tracks); + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track) % num_to_tracks, num_to_tracks); + } else if (to_side == RIGHT) { + to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); + } + } + /* Finish, we return */ + return to_tracks; + /* End switch_block_type == WILTON case. */ + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid switch block pattern !\n"); + exit(1); } - /* Finish, we return */ - return to_tracks; - /* End switch_block_type == UNIVERSAL case. */ - case WILTON: - /* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */ - if (from_side == LEFT) { - if (to_side == RIGHT) { /* CHANX to CHANX */ - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == TOP) { /* from CHANX to CHANY */ - to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track ) % num_to_tracks, num_to_tracks); - } else if (to_side == BOTTOM) { - to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); - } - } else if (from_side == RIGHT) { - if (to_side == LEFT) { /* CHANX to CHANX */ - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == TOP) { /* from CHANX to CHANY */ - to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); - } else if (to_side == BOTTOM) { - to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); - } - } else if (from_side == BOTTOM) { - if (to_side == TOP) { /* CHANY to CHANY */ - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == LEFT) { /* from CHANY to CHANX */ - to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); - } else if (to_side == RIGHT) { - to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); - } - } else if (from_side == TOP) { - if (to_side == BOTTOM) { /* CHANY to CHANY */ - to_tracks = get_to_track_list(Fs, from_track, num_to_tracks); - } else if (to_side == LEFT) { /* from CHANY to CHANX */ - to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track) % num_to_tracks, num_to_tracks); - } else if (to_side == RIGHT) { - to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); - } - } - /* Finish, we return */ + return to_tracks; - /* End switch_block_type == WILTON case. */ - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid switch block pattern !\n"); - exit(1); - } - - return to_tracks; } - /************************************************************************ * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] * For a group of from_track nodes and to_track nodes * For each side of from_tracks, we call a routine to get the list of to_tracks * Then, we fill the track2track_map ***********************************************************************/ -static -void build_gsb_one_group_track_to_track_map(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const e_switch_block_type& sb_type, - const int& Fs, - const bool& wire_opposite_side, - const t_track_group& from_tracks, /* [0..gsb_side][track_indices] */ - const t_track_group& to_tracks, /* [0..gsb_side][track_indices] */ - t_track2track_map& track2track_map) { - for (size_t side = 0; side < from_tracks.size(); ++side) { - SideManager side_manager(side); - e_side from_side = side_manager.get_side(); - /* Find the other sides where the start tracks will locate */ - std::vector to_track_sides; - /* 0. opposite side */ - to_track_sides.push_back(side_manager.get_opposite()); - /* 1. prev side */ - /* Previous side definition: TOP => LEFT; RIGHT=>TOP; BOTTOM=>RIGHT; LEFT=>BOTTOM */ - to_track_sides.push_back(side_manager.get_rotate_counterclockwise()); - /* 2. next side */ - /* Next side definition: TOP => RIGHT; RIGHT=>BOTTOM; BOTTOM=>LEFT; LEFT=>TOP */ - to_track_sides.push_back(side_manager.get_rotate_clockwise()); - - for (size_t inode = 0; inode < from_tracks[side].size(); ++inode) { - for (size_t to_side_id = 0; to_side_id < to_track_sides.size(); ++to_side_id) { - enum e_side to_side = to_track_sides[to_side_id]; - SideManager to_side_manager(to_side); - size_t to_side_index = to_side_manager.to_size_t(); - /* Bypass those to_sides have no nodes */ - if (0 == to_tracks[to_side_index].size()) { - continue; - } - /* Bypass those from_side is same as to_side */ - if (from_side == to_side) { - continue; - } - /* Bypass those from_side is opposite to to_side if required */ - if ( (true == wire_opposite_side) - && (to_side_manager.get_opposite() == from_side) ) { - continue; +static void build_gsb_one_group_track_to_track_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const e_switch_block_type& sb_type, + const int& Fs, + const bool& wire_opposite_side, + const t_track_group& from_tracks, /* [0..gsb_side][track_indices] */ + const t_track_group& to_tracks, /* [0..gsb_side][track_indices] */ + t_track2track_map& track2track_map) { + for (size_t side = 0; side < from_tracks.size(); ++side) { + SideManager side_manager(side); + e_side from_side = side_manager.get_side(); + /* Find the other sides where the start tracks will locate */ + std::vector to_track_sides; + /* 0. opposite side */ + to_track_sides.push_back(side_manager.get_opposite()); + /* 1. prev side */ + /* Previous side definition: TOP => LEFT; RIGHT=>TOP; BOTTOM=>RIGHT; LEFT=>BOTTOM */ + to_track_sides.push_back(side_manager.get_rotate_counterclockwise()); + /* 2. next side */ + /* Next side definition: TOP => RIGHT; RIGHT=>BOTTOM; BOTTOM=>LEFT; LEFT=>TOP */ + to_track_sides.push_back(side_manager.get_rotate_clockwise()); + + for (size_t inode = 0; inode < from_tracks[side].size(); ++inode) { + for (size_t to_side_id = 0; to_side_id < to_track_sides.size(); ++to_side_id) { + enum e_side to_side = to_track_sides[to_side_id]; + SideManager to_side_manager(to_side); + size_t to_side_index = to_side_manager.to_size_t(); + /* Bypass those to_sides have no nodes */ + if (0 == to_tracks[to_side_index].size()) { + continue; + } + /* Bypass those from_side is same as to_side */ + if (from_side == to_side) { + continue; + } + /* Bypass those from_side is opposite to to_side if required */ + if ((true == wire_opposite_side) + && (to_side_manager.get_opposite() == from_side)) { + continue; + } + /* Get other track_ids depending on the switch block pattern */ + /* Find the track ids that will start at the other sides */ + std::vector to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode, + to_side, + to_tracks[to_side_index].size()); + /* Update the track2track_map: */ + for (size_t to_track_id = 0; to_track_id < to_track_ids.size(); ++to_track_id) { + size_t from_side_index = side_manager.to_size_t(); + size_t from_track_index = from_tracks[side][inode]; + /* Check the id is still in the range !*/ + VTR_ASSERT(to_track_ids[to_track_id] < to_tracks[to_side_index].size()); + size_t to_track_index = to_tracks[to_side_index][to_track_ids[to_track_id]]; + //printf("from_track(size=%lu): %lu , to_track_ids[%lu]:%lu, to_track_index: %lu in a group of %lu tracks\n", + // from_tracks[side].size(), inode, to_track_id, to_track_ids[to_track_id], + // to_track_index, to_tracks[to_side_index].size()); + const RRNodeId& to_track_node = rr_gsb.get_chan_node(to_side, to_track_index); + VTR_ASSERT(true == rr_graph.valid_node_id(to_track_node)); + + /* from_track should be IN_PORT */ + VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index)); + /* to_track should be OUT_PORT */ + VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index)); + + /* Check if the to_track_node is already in the list ! */ + std::vector::iterator it = std::find(track2track_map[from_side_index][from_track_index].begin(), + track2track_map[from_side_index][from_track_index].end(), + to_track_node); + if (it != track2track_map[from_side_index][from_track_index].end()) { + continue; /* the node_id is already in the list, go for the next */ + } + /* Clear, we should add to the list */ + track2track_map[from_side_index][from_track_index].push_back(to_track_node); + } + } } - /* Get other track_ids depending on the switch block pattern */ - /* Find the track ids that will start at the other sides */ - std::vector to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode, - to_side, - to_tracks[to_side_index].size()); - /* Update the track2track_map: */ - for (size_t to_track_id = 0; to_track_id < to_track_ids.size(); ++to_track_id) { - size_t from_side_index = side_manager.to_size_t(); - size_t from_track_index = from_tracks[side][inode]; - /* Check the id is still in the range !*/ - VTR_ASSERT( to_track_ids[to_track_id] < to_tracks[to_side_index].size() ); - size_t to_track_index = to_tracks[to_side_index][to_track_ids[to_track_id]]; - //printf("from_track(size=%lu): %lu , to_track_ids[%lu]:%lu, to_track_index: %lu in a group of %lu tracks\n", - // from_tracks[side].size(), inode, to_track_id, to_track_ids[to_track_id], - // to_track_index, to_tracks[to_side_index].size()); - const RRNodeId& to_track_node = rr_gsb.get_chan_node(to_side, to_track_index); - VTR_ASSERT(true == rr_graph.valid_node_id(to_track_node)); - - /* from_track should be IN_PORT */ - VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index)); - /* to_track should be OUT_PORT */ - VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index)); - - /* Check if the to_track_node is already in the list ! */ - std::vector::iterator it = std::find(track2track_map[from_side_index][from_track_index].begin(), - track2track_map[from_side_index][from_track_index].end(), - to_track_node); - if (it != track2track_map[from_side_index][from_track_index].end()) { - continue; /* the node_id is already in the list, go for the next */ - } - /* Clear, we should add to the list */ - track2track_map[from_side_index][from_track_index].push_back(to_track_node); - } - } } - } } /************************************************************************ @@ -442,128 +434,127 @@ void build_gsb_one_group_track_to_track_map(const RRGraph& rr_graph, ***********************************************************************/ t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph, const RRGSB& rr_gsb, - const e_switch_block_type& sb_type, + const e_switch_block_type& sb_type, const int& Fs, - const e_switch_block_type& sb_subtype, + const e_switch_block_type& sb_subtype, const int& subFs, const bool& wire_opposite_side, const std::vector& segment_inf) { - t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ + t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ - /* Categorize tracks into 3 groups: + /* Categorize tracks into 3 groups: * (1) tracks will start here * (2) tracks will end here * (2) tracks will just pass through the SB */ - t_track_group start_tracks; /* [0..gsb_side][track_indices] */ - t_track_group end_tracks; /* [0..gsb_side][track_indices] */ - t_track_group pass_tracks; /* [0..gsb_side][track_indices] */ - - /* resize to the number of sides */ - start_tracks.resize(rr_gsb.get_num_sides()); - end_tracks.resize(rr_gsb.get_num_sides()); - pass_tracks.resize(rr_gsb.get_num_sides()); - - /* Walk through each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - e_side gsb_side = side_manager.get_side(); - /* Build a list of tracks that will start from this side */ - for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - /* We need to check Switch block population of this track + t_track_group start_tracks; /* [0..gsb_side][track_indices] */ + t_track_group end_tracks; /* [0..gsb_side][track_indices] */ + t_track_group pass_tracks; /* [0..gsb_side][track_indices] */ + + /* resize to the number of sides */ + start_tracks.resize(rr_gsb.get_num_sides()); + end_tracks.resize(rr_gsb.get_num_sides()); + pass_tracks.resize(rr_gsb.get_num_sides()); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + e_side gsb_side = side_manager.get_side(); + /* Build a list of tracks that will start from this side */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + /* We need to check Switch block population of this track * The track node will not be considered if there supposed to be no SB at this position */ - if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, gsb_side, inode, segment_inf)) { - continue; /* skip this node and go to the next */ - } - /* check if this track will start from here */ - enum e_track_status track_status = determine_track_status_of_gsb(rr_graph, rr_gsb, gsb_side, inode); - - switch (track_status) { - case TRACK_START: - /* update starting track list */ - start_tracks[side].push_back(inode); - break; - case TRACK_END: - /* Update end track list */ - end_tracks[side].push_back(inode); - break; - case TRACK_PASS: - /* Update passing track list */ - /* Note that the pass_track should be IN_PORT only !!! */ - if (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, inode)) { - pass_tracks[side].push_back(inode); + if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, gsb_side, inode, segment_inf)) { + continue; /* skip this node and go to the next */ + } + /* check if this track will start from here */ + enum e_track_status track_status = determine_track_status_of_gsb(rr_graph, rr_gsb, gsb_side, inode); + + switch (track_status) { + case TRACK_START: + /* update starting track list */ + start_tracks[side].push_back(inode); + break; + case TRACK_END: + /* Update end track list */ + end_tracks[side].push_back(inode); + break; + case TRACK_PASS: + /* Update passing track list */ + /* Note that the pass_track should be IN_PORT only !!! */ + if (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, inode)) { + pass_tracks[side].push_back(inode); + } + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid track status!\n"); + exit(1); + } } - break; - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid track status!\n"); - exit(1); - } } - } - - /* Allocate track2track map */ - track2track_map.resize(rr_gsb.get_num_sides()); - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - enum e_side gsb_side = side_manager.get_side(); - /* allocate track2track_map[gsb_side] */ - track2track_map[side].resize(rr_gsb.get_chan_width(gsb_side)); - for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - /* allocate track2track_map[gsb_side][inode] */ - track2track_map[side][inode].clear(); + + /* Allocate track2track map */ + track2track_map.resize(rr_gsb.get_num_sides()); + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side gsb_side = side_manager.get_side(); + /* allocate track2track_map[gsb_side] */ + track2track_map[side].resize(rr_gsb.get_chan_width(gsb_side)); + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + /* allocate track2track_map[gsb_side][inode] */ + track2track_map[side][inode].clear(); + } } - } - /* For Group 1: we build connections between end_tracks and start_tracks*/ - build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, - true, /* End tracks should always to wired to start tracks */ - end_tracks, start_tracks, - track2track_map); + /* For Group 1: we build connections between end_tracks and start_tracks*/ + build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, + true, /* End tracks should always to wired to start tracks */ + end_tracks, start_tracks, + track2track_map); - /* For Group 2: we build connections between end_tracks and start_tracks*/ - /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks, + /* For Group 2: we build connections between end_tracks and start_tracks*/ + /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks, * TODO: This can be improved with different patterns! */ - build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, - sb_subtype, subFs, - wire_opposite_side, /* Pass tracks may not be wired to start tracks */ - pass_tracks, start_tracks, - track2track_map); + build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, + sb_subtype, subFs, + wire_opposite_side, /* Pass tracks may not be wired to start tracks */ + pass_tracks, start_tracks, + track2track_map); - return track2track_map; + return track2track_map; } /* Build a RRChan Object with the given channel type and coorindators */ -static -RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, - const RRGraph& rr_graph, - const ChanNodeDetails& chan_details) { - std::vector chan_rr_nodes; - - /* Create a rr_chan object and check if it is unique in the graph */ - RRChan rr_chan; - - /* Fill the information */ - rr_chan.set_type(chan_type); - - /* Collect rr_nodes for this channel */ - chan_rr_nodes = find_rr_graph_chan_nodes(rr_graph, - chan_coordinate.x(), chan_coordinate.y(), - chan_type); - - /* Reserve */ - /* rr_chan.reserve_node(size_t(chan_width)); */ - - /* Fill the rr_chan */ - for (size_t itrack = 0; itrack < chan_rr_nodes.size(); ++itrack) { - size_t iseg = chan_details.get_track_segment_id(itrack); - rr_chan.add_node(rr_graph, chan_rr_nodes[itrack], RRSegmentId(iseg)); - } - - return rr_chan; +static RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + const RRGraph& rr_graph, + const ChanNodeDetails& chan_details) { + std::vector chan_rr_nodes; + + /* Create a rr_chan object and check if it is unique in the graph */ + RRChan rr_chan; + + /* Fill the information */ + rr_chan.set_type(chan_type); + + /* Collect rr_nodes for this channel */ + chan_rr_nodes = find_rr_graph_chan_nodes(rr_graph, + chan_coordinate.x(), chan_coordinate.y(), + chan_type); + + /* Reserve */ + /* rr_chan.reserve_node(size_t(chan_width)); */ + + /* Fill the rr_chan */ + for (size_t itrack = 0; itrack < chan_rr_nodes.size(); ++itrack) { + size_t iseg = chan_details.get_track_segment_id(itrack); + rr_chan.add_node(rr_graph, chan_rr_nodes[itrack], RRSegmentId(iseg)); + } + + return rr_chan; } /*********************************************************************** @@ -618,210 +609,210 @@ RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordinate, * We just need to fill the ipin nodes at LEFT and RIGHT sides * as well as properly fill the ipin_grid_side information ***********************************************************************/ -RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, +RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const RRGraph& rr_graph, - const vtr::Point& device_chan_width, + const vtr::Point& device_chan_width, const std::vector& segment_inf, const vtr::Point& gsb_coordinate) { - /* Create an object to return */ - RRGSB rr_gsb; - - /* Check */ - VTR_ASSERT(gsb_coordinate.x() <= grids.width()); - VTR_ASSERT(gsb_coordinate.y() <= grids.height()); - - /* Coordinator initialization */ - rr_gsb.set_coordinate(gsb_coordinate.x(), gsb_coordinate.y()); - - /* Basic information*/ - rr_gsb.init_num_sides(4); /* Fixed number of sides */ - - /* Find all rr_nodes of channels */ - /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - /* Local variables inside this for loop */ - SideManager side_manager(side); - vtr::Point coordinate = rr_gsb.get_side_block_coordinate(side_manager.get_side()); - RRChan rr_chan; - std::vector> temp_opin_rr_nodes(2); - enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; - enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ - - /* Build a segment details, where we need the segment ids for building rr_chan + /* Create an object to return */ + RRGSB rr_gsb; + + /* Check */ + VTR_ASSERT(gsb_coordinate.x() <= grids.width()); + VTR_ASSERT(gsb_coordinate.y() <= grids.height()); + + /* Coordinator initialization */ + rr_gsb.set_coordinate(gsb_coordinate.x(), gsb_coordinate.y()); + + /* Basic information*/ + rr_gsb.init_num_sides(4); /* Fixed number of sides */ + + /* Find all rr_nodes of channels */ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + /* Local variables inside this for loop */ + SideManager side_manager(side); + vtr::Point coordinate = rr_gsb.get_side_block_coordinate(side_manager.get_side()); + RRChan rr_chan; + std::vector> temp_opin_rr_nodes(2); + enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; + enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ + + /* Build a segment details, where we need the segment ids for building rr_chan * We do not care starting and ending points here, so set chan_side as NUM_SIDES */ - ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width.x(), grids.width() - 1, - false, false, segment_inf); - ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width.y(), grids.height() - 1, - false, false, segment_inf); - - switch (side) { - case TOP: /* TOP = 0 */ - /* For the bording, we should take special care */ - if (gsb_coordinate.y() == grids.height() - 1) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details); - chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ - chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ - - /* Assign grid side of OPIN */ - /* Grid[x][y+1] RIGHT side outputs pins */ - opin_grid_side[0] = RIGHT; - /* Grid[x+1][y+1] left side outputs pins */ - opin_grid_side[1] = LEFT; - - /* Build the Switch block: opin and opin_grid_side */ - /* Include Grid[x][y+1] RIGHT side outputs pins */ - temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x(), gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); - /* Include Grid[x+1][y+1] Left side output pins */ - temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, - OPIN, opin_grid_side[1]); - - break; - case RIGHT: /* RIGHT = 1 */ - /* For the bording, we should take special care */ - if (gsb_coordinate.x() == grids.width() - 1) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details); - chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ - chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ - - /* Assign grid side of OPIN */ - /* Grid[x+1][y+1] BOTTOM side outputs pins */ - opin_grid_side[0] = BOTTOM; - /* Grid[x+1][y] TOP side outputs pins */ - opin_grid_side[1] = TOP; - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x+1][y+1] Bottom side output pins */ - temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); - /* include Grid[x+1][y] Top side output pins */ - temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x() + 1, gsb_coordinate.y(), - OPIN, opin_grid_side[1]); - break; - case BOTTOM: /* BOTTOM = 2*/ - /* For the bording, we should take special care */ - if (gsb_coordinate.y() == 0) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details); - chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ - chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ - - /* Assign grid side of OPIN */ - /* Grid[x+1][y] LEFT side outputs pins */ - opin_grid_side[0] = LEFT; - /* Grid[x][y] RIGHT side outputs pins */ - opin_grid_side[1] = RIGHT; - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x+1][y] Left side output pins */ - temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x() + 1, gsb_coordinate.y(), - OPIN, opin_grid_side[0]); - /* include Grid[x][y] Right side output pins */ - temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x(), gsb_coordinate.y(), - OPIN, opin_grid_side[1]); - break; - case LEFT: /* LEFT = 3 */ - /* For the bording, we should take special care */ - if (gsb_coordinate.x() == 0) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for left: chanx[x][y] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details); - chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ - chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ - - /* Grid[x][y+1] BOTTOM side outputs pins */ - opin_grid_side[0] = BOTTOM; - /* Grid[x][y] TOP side outputs pins */ - opin_grid_side[1] = TOP; - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x][y+1] Bottom side outputs pins */ - temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x(), gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); - /* include Grid[x][y] Top side output pins */ - temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x(), gsb_coordinate.y(), - OPIN, opin_grid_side[1]); - - break; - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid side index!\n"); - exit(1); - } + ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width.x(), grids.width() - 1, + false, false, segment_inf); + ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width.y(), grids.height() - 1, + false, false, segment_inf); + + switch (side) { + case TOP: /* TOP = 0 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.y() == grids.height() - 1) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details); + chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ + chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x][y+1] RIGHT side outputs pins */ + opin_grid_side[0] = RIGHT; + /* Grid[x+1][y+1] left side outputs pins */ + opin_grid_side[1] = LEFT; + + /* Build the Switch block: opin and opin_grid_side */ + /* Include Grid[x][y+1] RIGHT side outputs pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x(), gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* Include Grid[x+1][y+1] Left side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, + OPIN, opin_grid_side[1]); + + break; + case RIGHT: /* RIGHT = 1 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.x() == grids.width() - 1) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details); + chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ + chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x+1][y+1] BOTTOM side outputs pins */ + opin_grid_side[0] = BOTTOM; + /* Grid[x+1][y] TOP side outputs pins */ + opin_grid_side[1] = TOP; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x+1][y+1] Bottom side output pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* include Grid[x+1][y] Top side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x() + 1, gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + break; + case BOTTOM: /* BOTTOM = 2*/ + /* For the bording, we should take special care */ + if (gsb_coordinate.y() == 0) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details); + chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ + chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x+1][y] LEFT side outputs pins */ + opin_grid_side[0] = LEFT; + /* Grid[x][y] RIGHT side outputs pins */ + opin_grid_side[1] = RIGHT; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x+1][y] Left side output pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x() + 1, gsb_coordinate.y(), + OPIN, opin_grid_side[0]); + /* include Grid[x][y] Right side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x(), gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + break; + case LEFT: /* LEFT = 3 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.x() == 0) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for left: chanx[x][y] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details); + chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ + chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ + + /* Grid[x][y+1] BOTTOM side outputs pins */ + opin_grid_side[0] = BOTTOM; + /* Grid[x][y] TOP side outputs pins */ + opin_grid_side[1] = TOP; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x][y+1] Bottom side outputs pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x(), gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* include Grid[x][y] Top side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + gsb_coordinate.x(), gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid side index!\n"); + exit(1); + } - /* Organize a vector of port direction */ - if (0 < rr_chan.get_chan_width()) { - std::vector rr_chan_dir; - rr_chan_dir.resize(rr_chan.get_chan_width()); - for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { - /* Identify the directionality, record it in rr_node_direction */ - if (Direction::INC == rr_graph.node_direction(rr_chan.get_node(itrack))) { - rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0]; - } else { - VTR_ASSERT(Direction::DEC == rr_graph.node_direction(rr_chan.get_node(itrack))); - rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1]; + /* Organize a vector of port direction */ + if (0 < rr_chan.get_chan_width()) { + std::vector rr_chan_dir; + rr_chan_dir.resize(rr_chan.get_chan_width()); + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + /* Identify the directionality, record it in rr_node_direction */ + if (Direction::INC == rr_graph.node_direction(rr_chan.get_node(itrack))) { + rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0]; + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(rr_chan.get_node(itrack))); + rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1]; + } + } + /* Fill chan_rr_nodes */ + rr_gsb.add_chan_node(side_manager.get_side(), rr_chan, rr_chan_dir); } - } - /* Fill chan_rr_nodes */ - rr_gsb.add_chan_node(side_manager.get_side(), rr_chan, rr_chan_dir); - } - /* Fill opin_rr_nodes */ - /* Copy from temp_opin_rr_node to opin_rr_node */ - for (const RRNodeId& inode : temp_opin_rr_nodes[0]) { - /* Grid[x+1][y+1] Bottom side outputs pins */ - rr_gsb.add_opin_node(inode, side_manager.get_side()); - } - for (const RRNodeId& inode : temp_opin_rr_nodes[1]) { - /* Grid[x+1][y] TOP side outputs pins */ - rr_gsb.add_opin_node(inode, side_manager.get_side()); - } + /* Fill opin_rr_nodes */ + /* Copy from temp_opin_rr_node to opin_rr_node */ + for (const RRNodeId& inode : temp_opin_rr_nodes[0]) { + /* Grid[x+1][y+1] Bottom side outputs pins */ + rr_gsb.add_opin_node(inode, side_manager.get_side()); + } + for (const RRNodeId& inode : temp_opin_rr_nodes[1]) { + /* Grid[x+1][y] TOP side outputs pins */ + rr_gsb.add_opin_node(inode, side_manager.get_side()); + } - /* Clean ipin_rr_nodes */ - /* We do not have any IPIN for a Switch Block */ - rr_gsb.clear_ipin_nodes(side_manager.get_side()); + /* Clean ipin_rr_nodes */ + /* We do not have any IPIN for a Switch Block */ + rr_gsb.clear_ipin_nodes(side_manager.get_side()); - /* Clear the temp data */ - temp_opin_rr_nodes[0].clear(); - temp_opin_rr_nodes[1].clear(); - opin_grid_side[0] = NUM_SIDES; - opin_grid_side[1] = NUM_SIDES; - } + /* Clear the temp data */ + temp_opin_rr_nodes[0].clear(); + temp_opin_rr_nodes[1].clear(); + opin_grid_side[0] = NUM_SIDES; + opin_grid_side[1] = NUM_SIDES; + } - /* Add IPIN nodes from adjacent grids: the 4 grids sitting on the 4 corners of the Switch Block + /* Add IPIN nodes from adjacent grids: the 4 grids sitting on the 4 corners of the Switch Block * * - The concept of top/bottom side of connection block in GSB domain: * @@ -849,69 +840,69 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, * --------------+ +---------------------- ... ---------------------+ +---------------- * */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - size_t ix; - size_t iy; - enum e_side chan_side; - std::vector temp_ipin_rr_nodes; - enum e_side ipin_rr_node_grid_side; - - switch (side) { - case TOP: - /* Consider the routing channel that is connected to the left side of the switch block */ - chan_side = LEFT; - /* The input pins of the routing channel come from the bottom side of Grid[x][y+1] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = BOTTOM; - break; - case RIGHT: - /* Consider the routing channel that is connected to the top side of the switch block */ - chan_side = TOP; - /* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */ - ix = rr_gsb.get_sb_x() + 1; - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = LEFT; - break; - case BOTTOM: - /* Consider the routing channel that is connected to the left side of the switch block */ - chan_side = LEFT; - /* The input pins of the routing channel come from the top side of Grid[x][y] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y(); - ipin_rr_node_grid_side = TOP; - break; - case LEFT: - /* Consider the routing channel that is connected to the top side of the switch block */ - chan_side = TOP; - /* The input pins of the routing channel come from the right side of Grid[x][y+1] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = RIGHT; - break; - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid side index!\n"); - exit(1); - } - - /* If there is no channel at this side, we skip ipin_node annotation */ - if (0 == rr_gsb.get_chan_width(chan_side)) { - continue; - } - /* Collect IPIN rr_nodes*/ - temp_ipin_rr_nodes = find_rr_graph_grid_nodes(rr_graph, grids, - ix, iy, IPIN, ipin_rr_node_grid_side); - /* Fill the ipin nodes of RRGSB */ - for (const RRNodeId& inode : temp_ipin_rr_nodes) { - rr_gsb.add_ipin_node(inode, side_manager.get_side()); + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + size_t ix; + size_t iy; + enum e_side chan_side; + std::vector temp_ipin_rr_nodes; + enum e_side ipin_rr_node_grid_side; + + switch (side) { + case TOP: + /* Consider the routing channel that is connected to the left side of the switch block */ + chan_side = LEFT; + /* The input pins of the routing channel come from the bottom side of Grid[x][y+1] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y() + 1; + ipin_rr_node_grid_side = BOTTOM; + break; + case RIGHT: + /* Consider the routing channel that is connected to the top side of the switch block */ + chan_side = TOP; + /* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */ + ix = rr_gsb.get_sb_x() + 1; + iy = rr_gsb.get_sb_y() + 1; + ipin_rr_node_grid_side = LEFT; + break; + case BOTTOM: + /* Consider the routing channel that is connected to the left side of the switch block */ + chan_side = LEFT; + /* The input pins of the routing channel come from the top side of Grid[x][y] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y(); + ipin_rr_node_grid_side = TOP; + break; + case LEFT: + /* Consider the routing channel that is connected to the top side of the switch block */ + chan_side = TOP; + /* The input pins of the routing channel come from the right side of Grid[x][y+1] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y() + 1; + ipin_rr_node_grid_side = RIGHT; + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid side index!\n"); + exit(1); + } + + /* If there is no channel at this side, we skip ipin_node annotation */ + if (0 == rr_gsb.get_chan_width(chan_side)) { + continue; + } + /* Collect IPIN rr_nodes*/ + temp_ipin_rr_nodes = find_rr_graph_grid_nodes(rr_graph, grids, + ix, iy, IPIN, ipin_rr_node_grid_side); + /* Fill the ipin nodes of RRGSB */ + for (const RRNodeId& inode : temp_ipin_rr_nodes) { + rr_gsb.add_ipin_node(inode, side_manager.get_side()); + } + /* Clear the temp data */ + temp_ipin_rr_nodes.clear(); } - /* Clear the temp data */ - temp_ipin_rr_nodes.clear(); - } - return rr_gsb; + return rr_gsb; } /************************************************************************ @@ -920,52 +911,51 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) * 3. create edges between OPINs and IPINs (direct-connections) ***********************************************************************/ -void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, +void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, const RRGSB& rr_gsb, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, const vtr::vector& rr_node_driver_switches) { - - /* Walk through each sides */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - enum e_side gsb_side = side_manager.get_side(); - - /* Find OPINs */ - for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { - const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); - - /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ - /* add edges to the opin_node */ - for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) { - rr_graph.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]); - } - } + /* Walk through each sides */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side gsb_side = side_manager.get_side(); + + /* Find OPINs */ + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); + + /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ + /* add edges to the opin_node */ + for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) { + rr_graph.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]); + } + } - /* Find CHANX or CHANY */ - /* For TRACKs to IPINs, we only care LEFT and TOP sides + /* Find CHANX or CHANY */ + /* For TRACKs to IPINs, we only care LEFT and TOP sides * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs */ - if ( (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) - || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY)) ) { - /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ - for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); - for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { - rr_graph.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]); + if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { + /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { + rr_graph.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]); + } + } } - } - } - /* 3. create edges between CHANX|CHANY and CHANX|CHANY, using track2track_map */ - for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); - for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { - rr_graph.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]); - } + /* 3. create edges between CHANX|CHANY and CHANX|CHANY, using track2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { + rr_graph.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]); + } + } } - } } /************************************************************************ @@ -979,87 +969,86 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, * 3. Scale the Fc of each pin to the actual number of routing tracks * actual_Fc = (int) Fc * num_tracks / chan_width ***********************************************************************/ -static -void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const enum e_side& ipin_side, - const size_t& ipin_node_id, - const std::vector& Fc, - const size_t& offset, - const std::vector& segment_inf, - t_track2pin_map& track2ipin_map) { - /* Get a list of segment_ids*/ - enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); - SideManager chan_side_manager(chan_side); - std::vector seg_list = rr_gsb.get_chan_segment_ids(chan_side); - size_t chan_width = rr_gsb.get_chan_width(chan_side); - SideManager ipin_side_manager(ipin_side); - const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, ipin_node_id); - - for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { - /* Get a list of node that have the segment id */ - std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); - /* Refine the track_list: keep those will have connection blocks in the GSB */ - std::vector actual_track_list; - for (size_t inode = 0; inode < track_list.size(); ++inode) { - /* Check if tracks allow connection blocks in the GSB*/ - if (false == is_gsb_in_track_cb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) { - continue; /* Bypass condition */ - } - /* Push the node to actual_track_list */ - actual_track_list.push_back(track_list[inode]); - } - /* Check the actual track list */ - VTR_ASSERT(0 == actual_track_list.size() % 2); - - /* Scale Fc */ - int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); - /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ - actual_Fc = std::max(1, actual_Fc); - /* Compute the step between two connection from this IPIN to tracks: +static void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& ipin_side, + const size_t& ipin_node_id, + const std::vector& Fc, + const size_t& offset, + const std::vector& segment_inf, + t_track2pin_map& track2ipin_map) { + /* Get a list of segment_ids*/ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + std::vector seg_list = rr_gsb.get_chan_segment_ids(chan_side); + size_t chan_width = rr_gsb.get_chan_width(chan_side); + SideManager ipin_side_manager(ipin_side); + const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, ipin_node_id); + + for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { + /* Get a list of node that have the segment id */ + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); + /* Refine the track_list: keep those will have connection blocks in the GSB */ + std::vector actual_track_list; + for (size_t inode = 0; inode < track_list.size(); ++inode) { + /* Check if tracks allow connection blocks in the GSB*/ + if (false == is_gsb_in_track_cb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) { + continue; /* Bypass condition */ + } + /* Push the node to actual_track_list */ + actual_track_list.push_back(track_list[inode]); + } + /* Check the actual track list */ + VTR_ASSERT(0 == actual_track_list.size() % 2); + + /* Scale Fc */ + int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); + /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ + actual_Fc = std::max(1, actual_Fc); + /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in */ - size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); - /* Make sure step should be at least 2 */ - track_step = std::max(1, (int)track_step); - /* Adapt offset to the range of actual_track_list */ - size_t actual_offset = offset % actual_track_list.size(); - /* rotate the track list by an offset */ - if (0 < actual_offset) { - std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); - } + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); + /* Make sure step should be at least 2 */ + track_step = std::max(1, (int)track_step); + /* Adapt offset to the range of actual_track_list */ + size_t actual_offset = offset % actual_track_list.size(); + /* rotate the track list by an offset */ + if (0 < actual_offset) { + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } - /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ - int track_cnt = 0; - /* Keep assigning until we meet the Fc requirement */ - for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) { - /* Update pin2track map */ - size_t chan_side_index = chan_side_manager.to_size_t(); - /* itrack may exceed the size of actual_track_list, adapt it */ - size_t actual_itrack = itrack % actual_track_list.size(); - /* track_index may exceed the chan_width(), adapt it */ - size_t track_index = actual_track_list[actual_itrack] % chan_width; + /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ + int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ + for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) { + /* Update pin2track map */ + size_t chan_side_index = chan_side_manager.to_size_t(); + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + /* track_index may exceed the chan_width(), adapt it */ + size_t track_index = actual_track_list[actual_itrack] % chan_width; - track2ipin_map[chan_side_index][track_index].push_back(ipin_node); + track2ipin_map[chan_side_index][track_index].push_back(ipin_node); - /* track_index may exceed the chan_width(), adapt it */ - track_index = (actual_track_list[actual_itrack] + 1) % chan_width; + /* track_index may exceed the chan_width(), adapt it */ + track_index = (actual_track_list[actual_itrack] + 1) % chan_width; - track2ipin_map[chan_side_index][track_index].push_back(ipin_node); + track2ipin_map[chan_side_index][track_index].push_back(ipin_node); - track_cnt += 2; - } + track_cnt += 2; + } - /* Ensure the number of tracks is similar to Fc */ - /* Give a warning if Fc is < track_cnt */ - /* + /* Ensure the number of tracks is similar to Fc */ + /* Give a warning if Fc is < track_cnt */ + /* if (actual_Fc != track_cnt) { vpr_printf(TIO_MESSAGE_INFO, "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); } */ - } + } } /************************************************************************ @@ -1073,98 +1062,95 @@ void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph, * 3. Scale the Fc of each pin to the actual number of routing tracks * actual_Fc = (int) Fc * num_tracks / chan_width ***********************************************************************/ -static -void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const enum e_side& opin_side, - const size_t& opin_node_id, - const std::vector& Fc, - const size_t& offset, - const std::vector& segment_inf, - t_pin2track_map& opin2track_map) { - /* Get a list of segment_ids*/ - std::vector seg_list = rr_gsb.get_chan_segment_ids(opin_side); - enum e_side chan_side = opin_side; - size_t chan_width = rr_gsb.get_chan_width(chan_side); - SideManager opin_side_manager(opin_side); - - for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { - /* Get a list of node that have the segment id */ - std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); - /* Refine the track_list: keep those will have connection blocks in the GSB */ - std::vector actual_track_list; - for (size_t inode = 0; inode < track_list.size(); ++inode) { - /* Check if tracks allow connection blocks in the GSB*/ - if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, chan_side, - track_list[inode], segment_inf)) { - continue; /* Bypass condition */ - } - if (TRACK_START != determine_track_status_of_gsb(rr_graph, rr_gsb, chan_side, track_list[inode])) { - continue; /* Bypass condition */ - } - /* Push the node to actual_track_list */ - actual_track_list.push_back(track_list[inode]); - } +static void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& opin_side, + const size_t& opin_node_id, + const std::vector& Fc, + const size_t& offset, + const std::vector& segment_inf, + t_pin2track_map& opin2track_map) { + /* Get a list of segment_ids*/ + std::vector seg_list = rr_gsb.get_chan_segment_ids(opin_side); + enum e_side chan_side = opin_side; + size_t chan_width = rr_gsb.get_chan_width(chan_side); + SideManager opin_side_manager(opin_side); + + for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { + /* Get a list of node that have the segment id */ + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); + /* Refine the track_list: keep those will have connection blocks in the GSB */ + std::vector actual_track_list; + for (size_t inode = 0; inode < track_list.size(); ++inode) { + /* Check if tracks allow connection blocks in the GSB*/ + if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) { + continue; /* Bypass condition */ + } + if (TRACK_START != determine_track_status_of_gsb(rr_graph, rr_gsb, chan_side, track_list[inode])) { + continue; /* Bypass condition */ + } + /* Push the node to actual_track_list */ + actual_track_list.push_back(track_list[inode]); + } - /* Go the next segment if offset is zero or actual_track_list is empty */ - if (0 == actual_track_list.size()) { - continue; - } - - /* Scale Fc */ - int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); - /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ - actual_Fc = std::max(1, actual_Fc); - /* Compute the step between two connection from this IPIN to tracks: + /* Go the next segment if offset is zero or actual_track_list is empty */ + if (0 == actual_track_list.size()) { + continue; + } + + /* Scale Fc */ + int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); + /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ + actual_Fc = std::max(1, actual_Fc); + /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in */ - size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); - /* Track step mush be a multiple of 2!!!*/ - /* Make sure step should be at least 1 */ - track_step = std::max(1, (int)track_step); - /* Adapt offset to the range of actual_track_list */ - size_t actual_offset = offset % actual_track_list.size(); - - /* No need to rotate if offset is zero */ - if (0 < actual_offset) { - /* rotate the track list by an offset */ - std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); - } + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); + /* Track step mush be a multiple of 2!!!*/ + /* Make sure step should be at least 1 */ + track_step = std::max(1, (int)track_step); + /* Adapt offset to the range of actual_track_list */ + size_t actual_offset = offset % actual_track_list.size(); + + /* No need to rotate if offset is zero */ + if (0 < actual_offset) { + /* rotate the track list by an offset */ + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } - /* Assign tracks */ - int track_cnt = 0; - /* Keep assigning until we meet the Fc requirement */ - for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { - /* Update pin2track map */ - size_t opin_side_index = opin_side_manager.to_size_t(); - /* itrack may exceed the size of actual_track_list, adapt it */ - size_t actual_itrack = itrack % actual_track_list.size(); - size_t track_index = actual_track_list[actual_itrack]; - const RRNodeId& track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index); - opin2track_map[opin_side_index][opin_node_id].push_back(track_rr_node_index); - /* update track counter */ - track_cnt++; - /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. + /* Assign tracks */ + int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ + for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { + /* Update pin2track map */ + size_t opin_side_index = opin_side_manager.to_size_t(); + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + size_t track_index = actual_track_list[actual_itrack]; + const RRNodeId& track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index); + opin2track_map[opin_side_index][opin_node_id].push_back(track_rr_node_index); + /* update track counter */ + track_cnt++; + /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. * So I comment it. And we just make sure its track_cnt >= actual_Fc if (actual_Fc == track_cnt) { break; } */ - } + } - /* Ensure the number of tracks is similar to Fc */ - /* Give a warning if Fc is < track_cnt */ - /* + /* Ensure the number of tracks is similar to Fc */ + /* Give a warning if Fc is < track_cnt */ + /* if (actual_Fc != track_cnt) { vpr_printf(TIO_MESSAGE_INFO, "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", opin_node_id, track_cnt, actual_Fc); } */ - } + } } - /************************************************************************ * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] * based on the existing routing resources in the General Switch Block (GSB) @@ -1176,81 +1162,81 @@ void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph, * 2. Convert the ipin_to_track_map to track_to_ipin_map ***********************************************************************/ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const DeviceGrid& grids, - const std::vector& segment_inf, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, const std::vector>& Fc_in) { - t_track2pin_map track2ipin_map; - /* Resize the matrix */ - track2ipin_map.resize(rr_gsb.get_num_sides()); - - /* offset counter: it aims to balance the track-to-IPIN for each connection block */ - size_t offset_size = 0; - std::vector offset; - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - enum e_side ipin_side = side_manager.get_side(); - /* Get the chan_side */ - enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); - SideManager chan_side_manager(chan_side); - /* resize offset to the maximum chan_side*/ - offset_size = std::max(offset_size, chan_side_manager.to_size_t() + 1); - } - /* Initial offset */ - offset.resize(offset_size); - offset.assign(offset.size(), 0); - - /* Walk through each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - enum e_side ipin_side = side_manager.get_side(); - /* Get the chan_side */ - enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); - SideManager chan_side_manager(chan_side); - /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ - /* Get channel width and resize the matrix */ - size_t chan_width = rr_gsb.get_chan_width(chan_side); - track2ipin_map[chan_side_manager.to_size_t()].resize(chan_width); - /* Find the ipin/opin nodes */ - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { - const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); - /* Skip EMPTY type */ - if (true == is_empty_type(grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type)) { - continue; - } - - int grid_type_index = grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type->index; - /* Get Fc of the ipin */ - /* skip Fc = 0 or unintialized, those pins are in the */ - bool skip_conn2track = true; - std::vector ipin_Fc_out; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)][iseg]; - ipin_Fc_out.push_back(ipin_Fc); - if (0 != ipin_Fc) { - skip_conn2track = false; - continue; + t_track2pin_map track2ipin_map; + /* Resize the matrix */ + track2ipin_map.resize(rr_gsb.get_num_sides()); + + /* offset counter: it aims to balance the track-to-IPIN for each connection block */ + size_t offset_size = 0; + std::vector offset; + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side ipin_side = side_manager.get_side(); + /* Get the chan_side */ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + /* resize offset to the maximum chan_side*/ + offset_size = std::max(offset_size, chan_side_manager.to_size_t() + 1); + } + /* Initial offset */ + offset.resize(offset_size); + offset.assign(offset.size(), 0); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side ipin_side = side_manager.get_side(); + /* Get the chan_side */ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ + /* Get channel width and resize the matrix */ + size_t chan_width = rr_gsb.get_chan_width(chan_side); + track2ipin_map[chan_side_manager.to_size_t()].resize(chan_width); + /* Find the ipin/opin nodes */ + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { + const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); + /* Skip EMPTY type */ + if (true == is_empty_type(grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type)) { + continue; + } + + int grid_type_index = grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type->index; + /* Get Fc of the ipin */ + /* skip Fc = 0 or unintialized, those pins are in the */ + bool skip_conn2track = true; + std::vector ipin_Fc_out; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)][iseg]; + ipin_Fc_out.push_back(ipin_Fc); + if (0 != ipin_Fc) { + skip_conn2track = false; + continue; + } + } + + if (true == skip_conn2track) { + continue; + } + + VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size()); + + /* Build track2ipin_map for this IPIN */ + build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[chan_side_manager.to_size_t()], + segment_inf, track2ipin_map); + /* update offset */ + offset[chan_side_manager.to_size_t()] += 2; + //printf("offset[%lu]=%lu\n", chan_side_manager.to_size_t(), offset[chan_side_manager.to_size_t()]); } - } - - if (true == skip_conn2track) { - continue; - } - - VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size()); - - /* Build track2ipin_map for this IPIN */ - build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc_out, - /* Give an offset for the first track that this ipin will connect to */ - offset[chan_side_manager.to_size_t()], - segment_inf, track2ipin_map); - /* update offset */ - offset[chan_side_manager.to_size_t()] += 2; - //printf("offset[%lu]=%lu\n", chan_side_manager.to_size_t(), offset[chan_side_manager.to_size_t()]); } - } - return track2ipin_map; + return track2ipin_map; } /************************************************************************ @@ -1266,72 +1252,72 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph, * actual_Fc = (int) Fc * num_tracks / chan_width ***********************************************************************/ t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const DeviceGrid& grids, - const std::vector& segment_inf, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, const std::vector>& Fc_out) { - t_pin2track_map opin2track_map; - /* Resize the matrix */ - opin2track_map.resize(rr_gsb.get_num_sides()); - - /* offset counter: it aims to balance the OPIN-to-track for each switch block */ - std::vector offset; - /* Get the chan_side: which is the same as the opin side */ - offset.resize(rr_gsb.get_num_sides()); - /* Initial offset */ - offset.assign(offset.size(), 0); - - /* Walk through each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - enum e_side opin_side = side_manager.get_side(); - /* Get the chan_side */ - /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ - /* Get channel width and resize the matrix */ - size_t num_opin_nodes = rr_gsb.get_num_opin_nodes(opin_side); - opin2track_map[side].resize(num_opin_nodes); - /* Find the ipin/opin nodes */ - for (size_t inode = 0; inode < num_opin_nodes; ++inode) { - const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode); - /* Skip EMPTY type */ - if (true == is_empty_type(grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type)) { - continue; - } - int grid_type_index = grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type->index; - - /* Get Fc of the ipin */ - /* skip Fc = 0 or unintialized, those pins are in the */ - bool skip_conn2track = true; - std::vector opin_Fc_out; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)][iseg]; - opin_Fc_out.push_back(opin_Fc); - if (0 != opin_Fc) { - skip_conn2track = false; - continue; + t_pin2track_map opin2track_map; + /* Resize the matrix */ + opin2track_map.resize(rr_gsb.get_num_sides()); + + /* offset counter: it aims to balance the OPIN-to-track for each switch block */ + std::vector offset; + /* Get the chan_side: which is the same as the opin side */ + offset.resize(rr_gsb.get_num_sides()); + /* Initial offset */ + offset.assign(offset.size(), 0); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side opin_side = side_manager.get_side(); + /* Get the chan_side */ + /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ + /* Get channel width and resize the matrix */ + size_t num_opin_nodes = rr_gsb.get_num_opin_nodes(opin_side); + opin2track_map[side].resize(num_opin_nodes); + /* Find the ipin/opin nodes */ + for (size_t inode = 0; inode < num_opin_nodes; ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode); + /* Skip EMPTY type */ + if (true == is_empty_type(grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type)) { + continue; + } + int grid_type_index = grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type->index; + + /* Get Fc of the ipin */ + /* skip Fc = 0 or unintialized, those pins are in the */ + bool skip_conn2track = true; + std::vector opin_Fc_out; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)][iseg]; + opin_Fc_out.push_back(opin_Fc); + if (0 != opin_Fc) { + skip_conn2track = false; + continue; + } + } + + if (true == skip_conn2track) { + continue; + } + VTR_ASSERT(opin_Fc_out.size() == segment_inf.size()); + + /* Build track2ipin_map for this IPIN */ + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); + /* update offset: aim to rotate starting tracks by 1*/ + offset[side_manager.to_size_t()] += 1; } - } - - if (true == skip_conn2track) { - continue; - } - VTR_ASSERT(opin_Fc_out.size() == segment_inf.size()); - - /* Build track2ipin_map for this IPIN */ - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, - /* Give an offset for the first track that this ipin will connect to */ - offset[side_manager.to_size_t()], - segment_inf, opin2track_map); - /* update offset: aim to rotate starting tracks by 1*/ - offset[side_manager.to_size_t()] += 1; - } - /* Check: + /* Check: * 1. We want to ensure that each OPIN will drive at least one track * 2. We want to ensure that each track will be driven by at least 1 OPIN */ - } + } - return opin2track_map; + return opin2track_map; } /************************************************************************ @@ -1340,92 +1326,92 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph, void build_direct_connections_for_one_gsb(RRGraph& rr_graph, const DeviceGrid& grids, const vtr::Point& from_grid_coordinate, - const RRSwitchId& delayless_switch, - const std::vector& directs, + const RRSwitchId& delayless_switch, + const std::vector& directs, const std::vector& clb_to_clb_directs) { - VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); + VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); - const t_grid_tile& from_grid = grids[from_grid_coordinate.x()][from_grid_coordinate.y()]; - t_physical_tile_type_ptr grid_type = from_grid.type; + const t_grid_tile& from_grid = grids[from_grid_coordinate.x()][from_grid_coordinate.y()]; + t_physical_tile_type_ptr grid_type = from_grid.type; - /* Iterate through all direct connections */ - for (size_t i = 0; i < directs.size(); ++i) { - /* Bypass unmatched direct clb-to-clb connections */ - if (grid_type != clb_to_clb_directs[i].from_clb_type) { - continue; - } + /* Iterate through all direct connections */ + for (size_t i = 0; i < directs.size(); ++i) { + /* Bypass unmatched direct clb-to-clb connections */ + if (grid_type != clb_to_clb_directs[i].from_clb_type) { + continue; + } - /* This opin is specified to connect directly to an ipin, + /* This opin is specified to connect directly to an ipin, * now compute which ipin to connect to */ - vtr::Point to_grid_coordinate(from_grid_coordinate.x() + directs[i].x_offset, - from_grid_coordinate.y() + directs[i].y_offset); - - /* Bypass unmatched direct clb-to-clb connections */ - t_physical_tile_type_ptr to_grid_type = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].type; - /* Check if to_grid if the same grid */ - if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { - continue; - } - - bool swap; - int max_index, min_index; - /* Compute index of opin with regards to given pins */ - if ( clb_to_clb_directs[i].from_clb_pin_start_index - > clb_to_clb_directs[i].from_clb_pin_end_index) { - swap = true; - max_index = clb_to_clb_directs[i].from_clb_pin_start_index; - min_index = clb_to_clb_directs[i].from_clb_pin_end_index; - } else { - swap = false; - min_index = clb_to_clb_directs[i].from_clb_pin_start_index; - max_index = clb_to_clb_directs[i].from_clb_pin_end_index; - } + vtr::Point to_grid_coordinate(from_grid_coordinate.x() + directs[i].x_offset, + from_grid_coordinate.y() + directs[i].y_offset); + + /* Bypass unmatched direct clb-to-clb connections */ + t_physical_tile_type_ptr to_grid_type = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].type; + /* Check if to_grid if the same grid */ + if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { + continue; + } - /* get every opin in the range */ - for (int opin = min_index; opin <= max_index; ++opin) { - int offset = opin - min_index; - - if ( (to_grid_coordinate.x() < grids.width() - 1) - && (to_grid_coordinate.y() < grids.height() - 1) ) { - int ipin = OPEN; - if ( clb_to_clb_directs[i].to_clb_pin_start_index - > clb_to_clb_directs[i].to_clb_pin_end_index) { - if (true == swap) { - ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; - } else { - ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; - } + bool swap; + int max_index, min_index; + /* Compute index of opin with regards to given pins */ + if (clb_to_clb_directs[i].from_clb_pin_start_index + > clb_to_clb_directs[i].from_clb_pin_end_index) { + swap = true; + max_index = clb_to_clb_directs[i].from_clb_pin_start_index; + min_index = clb_to_clb_directs[i].from_clb_pin_end_index; } else { - if(true == swap) { - ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; - } else { - ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; - } + swap = false; + min_index = clb_to_clb_directs[i].from_clb_pin_start_index; + max_index = clb_to_clb_directs[i].from_clb_pin_end_index; } - /* Get the pin index in the rr_graph */ - int from_grid_width_ofs = from_grid.width_offset; - int from_grid_height_ofs = from_grid.height_offset; - int to_grid_width_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].width_offset; - int to_grid_height_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].height_offset; - - /* Find the side of grid pins, the pin location should be unique! + /* get every opin in the range */ + for (int opin = min_index; opin <= max_index; ++opin) { + int offset = opin - min_index; + + if ((to_grid_coordinate.x() < grids.width() - 1) + && (to_grid_coordinate.y() < grids.height() - 1)) { + int ipin = OPEN; + if (clb_to_clb_directs[i].to_clb_pin_start_index + > clb_to_clb_directs[i].to_clb_pin_end_index) { + if (true == swap) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; + } + } else { + if (true == swap) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; + } + } + + /* Get the pin index in the rr_graph */ + int from_grid_width_ofs = from_grid.width_offset; + int from_grid_height_ofs = from_grid.height_offset; + int to_grid_width_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].width_offset; + int to_grid_height_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].height_offset; + + /* Find the side of grid pins, the pin location should be unique! * Pin location is required by searching a node in rr_graph */ - std::vector opin_grid_side = find_grid_pin_sides(from_grid, opin); - VTR_ASSERT(1 == opin_grid_side.size()); - - std::vector ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin); - VTR_ASSERT(1 == ipin_grid_side.size()); - - const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs, - from_grid_coordinate.y() - from_grid_height_ofs, - OPIN, opin, opin_grid_side[0]); - const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs, - to_grid_coordinate.y() - to_grid_height_ofs, - IPIN, ipin, ipin_grid_side[0]); - /* + std::vector opin_grid_side = find_grid_pin_sides(from_grid, opin); + VTR_ASSERT(1 == opin_grid_side.size()); + + std::vector ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin); + VTR_ASSERT(1 == ipin_grid_side.size()); + + const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs, + from_grid_coordinate.y() - from_grid_height_ofs, + OPIN, opin, opin_grid_side[0]); + const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs, + to_grid_coordinate.y() - to_grid_height_ofs, + IPIN, ipin, ipin_grid_side[0]); + /* VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", from_grid_coordinate.x() - from_grid_width_ofs, from_grid_coordinate.y() - from_grid_height_ofs, @@ -1434,14 +1420,13 @@ void build_direct_connections_for_one_gsb(RRGraph& rr_graph, to_grid_coordinate.y() - to_grid_height_ofs, ipin, SIDE_STRING[ipin_grid_side[0]]); */ - - /* add edges to the opin_node */ - rr_graph.create_edge(opin_node_id, ipin_node_id, - delayless_switch); - } + + /* add edges to the opin_node */ + rr_graph.create_edge(opin_node_id, ipin_node_id, + delayless_switch); + } + } } - } } - } /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 89a0e264904..3d4627576bd 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -27,60 +27,58 @@ namespace openfpga { /************************************************************************ * Find the number output pins by considering all the grid ***********************************************************************/ -static -size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, - const t_rr_type& node_type) { - size_t num_grid_rr_nodes = 0; +static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, + const t_rr_type& node_type) { + size_t num_grid_rr_nodes = 0; - for (size_t ix = 0; ix < grids.width(); ++ix) { - for (size_t iy = 0; iy < grids.height(); ++iy) { - - /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { - continue; - } - - /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ( (0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset) ) { - continue; - } - - enum e_side io_side = NUM_SIDES; - - /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids[ix][iy].type)) { - vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); - vtr::Point grid_coordinate(ix, iy); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); - } - - switch (node_type) { - case OPIN: - /* get the number of OPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); - break; - case IPIN: - /* get the number of IPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); - break; - case SOURCE: - /* SOURCE: number of classes whose type is DRIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER); - break; - case SINK: - /* SINK: number of classes whose type is RECEIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER); - break; - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid routing resource node!\n"); - exit(1); - } + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ((0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset)) { + continue; + } + + enum e_side io_side = NUM_SIDES; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids[ix][iy].type)) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + vtr::Point grid_coordinate(ix, iy); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + } + + switch (node_type) { + case OPIN: + /* get the number of OPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); + break; + case IPIN: + /* get the number of IPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); + break; + case SOURCE: + /* SOURCE: number of classes whose type is DRIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER); + break; + case SINK: + /* SINK: number of classes whose type is RECEIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER); + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid routing resource node!\n"); + exit(1); + } + } } - } - return num_grid_rr_nodes; + return num_grid_rr_nodes; } /************************************************************************ @@ -176,52 +174,51 @@ size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * * ***********************************************************************/ -static -size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - size_t num_chanx_rr_nodes = 0; +static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + size_t num_chanx_rr_nodes = 0; - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { - vtr::Point chanx_coord(ix, iy); + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + vtr::Point chanx_coord(ix, iy); - /* Bypass if the routing channel does not exist when through channels are not allowed */ - if ( (false == through_channel) - && (false == is_chanx_exist(grids, chanx_coord))) { - continue; - } + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ((false == through_channel) + && (false == is_chanx_exist(grids, chanx_coord))) { + continue; + } - bool force_start = false; - bool force_end = false; + bool force_start = false; + bool force_end = false; - /* All the tracks have to start when + /* All the tracks have to start when * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_start = true; - } + if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_end = true; - } - - /* Evaluate if the routing channel locates in the middle of a grid */ - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); - /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ - num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); - /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ - num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(Direction::DEC); + if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_end = true; + } + + /* Evaluate if the routing channel locates in the middle of a grid */ + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(Direction::DEC); + } } - } - return num_chanx_rr_nodes; + return num_chanx_rr_nodes; } /************************************************************************ @@ -229,75 +226,71 @@ size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, * The technical rationale is very similar to the X-direction routing channel * Refer to the detailed explanation there ***********************************************************************/ -static -size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - size_t num_chany_rr_nodes = 0; - - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - vtr::Point chany_coord(ix, iy); +static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + size_t num_chany_rr_nodes = 0; - /* Bypass if the routing channel does not exist when through channel are not allowed */ - if ( (false == through_channel) - && (false == is_chany_exist(grids, chany_coord))) { - continue; - } + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Point chany_coord(ix, iy); + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ((false == through_channel) + && (false == is_chany_exist(grids, chany_coord))) { + continue; + } - bool force_start = false; - bool force_end = false; + bool force_start = false; + bool force_end = false; - /* All the tracks have to start when + /* All the tracks have to start when * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_start = true; - } + if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_end = true; - } - - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); - /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ - num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); - /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ - num_chany_rr_nodes += chany_details.get_num_ending_tracks(Direction::DEC); + if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_ending_tracks(Direction::DEC); + } } - } - return num_chany_rr_nodes; + return num_chany_rr_nodes; } /************************************************************************ * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ -static -std::vector estimate_num_rr_nodes(const DeviceGrid& grids, - const vtr::Point& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - - /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ - std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); - - /** +static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, + const vtr::Point& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ + std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); + + /** * 1 Find number of rr nodes related to grids */ - num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); - num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); - num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); - num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); + num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); + num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); + num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); + num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); - /** + /** * 2. Assign the segments for each routing channel, * To be specific, for each routing track, we assign a routing segment. * The assignment is subject to users' specifications, such as @@ -312,16 +305,16 @@ std::vector estimate_num_rr_nodes(const DeviceGrid& grids, * in X-direction and Y-direction channels!!! * So we will load segment details for different channels */ - num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, - chan_width.x(), - segment_infs, - through_channel); - num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, - chan_width.y(), - segment_infs, - through_channel); - - return num_rr_nodes_per_type; + num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, + chan_width.x(), + segment_infs, + through_channel); + num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, + chan_width.y(), + segment_infs, + through_channel); + + return num_rr_nodes_per_type; } /************************************************************************ @@ -337,22 +330,22 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const vtr::Point& chan_width, const std::vector& segment_infs, const bool& through_channel) { - VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); + VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); - std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, - chan_width, - segment_infs, - through_channel); + std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + chan_width, + segment_infs, + through_channel); - /* Reserve the number of node to be memory efficient */ - size_t num_nodes = 0; - for (const size_t& num_node_per_type : num_rr_nodes_per_type) { - num_nodes += num_node_per_type; - } + /* Reserve the number of node to be memory efficient */ + size_t num_nodes = 0; + for (const size_t& num_node_per_type : num_rr_nodes_per_type) { + num_nodes += num_node_per_type; + } - rr_graph_builder.reserve_nodes(num_nodes); + rr_graph_builder.reserve_nodes(num_nodes); - rr_node_driver_switches.reserve(num_nodes); + rr_node_driver_switches.reserve(num_nodes); } /************************************************************************ @@ -362,61 +355,59 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static -void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Walk through the width height of each grid, +static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Walk through the width height of each grid, * get pins and configure the rr_nodes */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { - /* Walk through sides */ - for (e_side side : SIDES) { - SideManager side_manager(side); - /* skip unwanted sides */ - if ( (true == is_io_type(cur_grid.type)) - && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side) ) { - continue; - } - /* Find OPINs */ - /* Configure pins by pins */ - std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), - width, height); - for (const int& pin_num : opin_list) { - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, OPIN, pin_num, side); - - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, - grid_coordinate.y() + height, - grid_coordinate.x() + width, - grid_coordinate.y() + height); - rr_graph_builder.add_node_side(node, side_manager.get_side()); - rr_graph_builder.set_node_pin_num(node, pin_num); - - rr_graph_builder.set_node_capacity(node, 1); - - /* cost index is a FIXED value for OPIN */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); - - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); - - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - - } /* End of loading OPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ - + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + /* Walk through sides */ + for (e_side side : SIDES) { + SideManager side_manager(side); + /* skip unwanted sides */ + if ((true == is_io_type(cur_grid.type)) + && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { + continue; + } + /* Find OPINs */ + /* Configure pins by pins */ + std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), + width, height); + for (const int& pin_num : opin_list) { + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, OPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of loading OPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ @@ -426,60 +417,59 @@ void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static -void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& wire_to_ipin_switch) { - SideManager io_side_manager(io_side); - - /* Walk through the width and height of each grid, +static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& wire_to_ipin_switch) { + SideManager io_side_manager(io_side); + + /* Walk through the width and height of each grid, * get pins and configure the rr_nodes */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { - /* Walk through sides */ - for (e_side side : SIDES) { - SideManager side_manager(side); - /* skip unwanted sides */ - if ( (true == is_io_type(cur_grid.type)) - && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side) ) { - continue; - } - - /* Find IPINs */ - /* Configure pins by pins */ - std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); - for (const int& pin_num : ipin_list) { - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, IPIN, pin_num, side); - - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, - grid_coordinate.y() + height, - grid_coordinate.x() + width, - grid_coordinate.y() + height); - rr_graph_builder.add_node_side(node, side_manager.get_side()); - rr_graph_builder.set_node_pin_num(node, pin_num); - - rr_graph_builder.set_node_capacity(node, 1); - - /* cost index is a FIXED value for OPIN */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); - - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(wire_to_ipin_switch); - - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - - } /* End of loading IPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + /* Walk through sides */ + for (e_side side : SIDES) { + SideManager side_manager(side); + /* skip unwanted sides */ + if ((true == is_io_type(cur_grid.type)) + && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { + continue; + } + + /* Find IPINs */ + /* Configure pins by pins */ + std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); + for (const int& pin_num : ipin_list) { + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, IPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(wire_to_ipin_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of loading IPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ @@ -489,48 +479,47 @@ void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static -void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Set a SOURCE rr_node for each DRIVER class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Set a SINK rr_node for the OPIN */ - if (DRIVER != cur_grid.type->class_inf[iclass].type) { - continue; - } +static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Set a SOURCE rr_node for each DRIVER class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (DRIVER != cur_grid.type->class_inf[iclass].type) { + continue; + } - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), - grid_coordinate.y(), - grid_coordinate.x() + cur_grid.type->width - 1, - grid_coordinate.y() + cur_grid.type->height - 1); - rr_graph_builder.set_node_class_num(node, iclass); + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); - rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_capacity(node, 1); - /* The capacity should be the number of pins in this class*/ - rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); - /* cost index is a FIXED value for SOURCE */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); + /* cost index is a FIXED value for SOURCE */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - } /* End of class enumeration */ + } /* End of class enumeration */ } /************************************************************************ @@ -540,116 +529,112 @@ void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static -void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Set a SINK rr_node for each RECEIVER class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Set a SINK rr_node for the OPIN */ - if (RECEIVER != cur_grid.type->class_inf[iclass].type) { - continue; - } +static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Set a SINK rr_node for each RECEIVER class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (RECEIVER != cur_grid.type->class_inf[iclass].type) { + continue; + } - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), - grid_coordinate.y(), - grid_coordinate.x() + cur_grid.type->width - 1, - grid_coordinate.y() + cur_grid.type->height - 1); - rr_graph_builder.set_node_class_num(node, iclass); + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); - rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_capacity(node, 1); - /* The capacity should be the number of pins in this class*/ - rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); - /* cost index is a FIXED value for SINK */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); + /* cost index is a FIXED value for SINK */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - } /* End of class enumeration */ + } /* End of class enumeration */ } /************************************************************************ * Create all the rr_nodes for grids ***********************************************************************/ -static -void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids, - const RRSwitchId& wire_to_ipin_switch, - const RRSwitchId& delayless_switch) { - - for (size_t iy = 0; iy < grids.height(); ++iy) { - for (size_t ix = 0; ix < grids.width(); ++ix) { - /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { - continue; - } - - /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ - if ( (0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset) ) { - continue; - } - - vtr::Point grid_coordinate(ix, iy); - enum e_side io_side = NUM_SIDES; - - /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids[ix][iy].type)) { - vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); - } - - /* Configure source rr_nodes for this grid */ - load_one_grid_source_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure sink rr_nodes for this grid */ - load_one_grid_sink_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure opin rr_nodes for this grid */ - load_one_grid_opin_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure ipin rr_nodes for this grid */ - load_one_grid_ipin_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - wire_to_ipin_switch); - +static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + + /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ + if ((0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset)) { + continue; + } + + vtr::Point grid_coordinate(ix, iy); + enum e_side io_side = NUM_SIDES; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids[ix][iy].type)) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + } + + /* Configure source rr_nodes for this grid */ + load_one_grid_source_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure sink rr_nodes for this grid */ + load_one_grid_sink_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure opin rr_nodes for this grid */ + load_one_grid_opin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure ipin rr_nodes for this grid */ + load_one_grid_ipin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + wire_to_ipin_switch); + } } - } } /************************************************************************ @@ -657,114 +642,110 @@ void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, track_ids, ptc_num, direction ***********************************************************************/ -static -void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, - ChanNodeDetails& chan_details, - const std::vector& segment_infs, - const int& cost_index_offset) { - /* Check each node_id(potential ptc_num) in the channel : +static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + ChanNodeDetails& chan_details, + const std::vector& segment_infs, + const int& cost_index_offset) { + /* Check each node_id(potential ptc_num) in the channel : * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num * If this is a ending point, we set xhigh/yhigh and track_ids * For other nodes, we set changes in track_ids */ - for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { - /* For INC direction, a starting point requires a new chan rr_node */ - if ( ( (true == chan_details.is_track_start(itrack)) - && (Direction::INC == chan_details.get_track_direction(itrack)) ) - /* For DEC direction, an ending point requires a new chan rr_node */ - || - ( (true == chan_details.is_track_end(itrack)) - && (Direction::DEC == chan_details.get_track_direction(itrack)) ) ) { - - /* Create a new chan rr_node */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); - - rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); - rr_graph_builder.set_node_track_num(node, itrack); - rr_node_track_ids[node].push_back(itrack); - - rr_graph_builder.set_node_capacity(node, 1); - - /* assign switch id */ - size_t seg_id = chan_details.get_track_segment_id(itrack); - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); - - /* Update chan_details with node_id */ - chan_details.set_track_node_id(itrack, size_t(node)); - - /* cost index depends on the segment index */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_id)); - /* Finish here, go to next */ - } + for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { + /* For INC direction, a starting point requires a new chan rr_node */ + if (((true == chan_details.is_track_start(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack))) + /* For DEC direction, an ending point requires a new chan rr_node */ + || ((true == chan_details.is_track_end(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)))) { + /* Create a new chan rr_node */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); + + rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); + rr_graph_builder.set_node_track_num(node, itrack); + rr_node_track_ids[node].push_back(itrack); + + rr_graph_builder.set_node_capacity(node, 1); + + /* assign switch id */ + size_t seg_id = chan_details.get_track_segment_id(itrack); + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); + + /* Update chan_details with node_id */ + chan_details.set_track_node_id(itrack, size_t(node)); + + /* cost index depends on the segment index */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_id)); + /* Finish here, go to next */ + } - /* For INC direction, an ending point requires an update on xhigh and yhigh */ - if ( ( (true == chan_details.is_track_end(itrack)) - && (Direction::INC == chan_details.get_track_direction(itrack)) ) - || - /* For DEC direction, an starting point requires an update on xlow and ylow */ - ( (true == chan_details.is_track_start(itrack)) - && (Direction::DEC == chan_details.get_track_direction(itrack)) ) ) { - - /* Get the node_id */ - const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); - - /* Do a quick check, make sure we do not mistakenly modify other nodes */ - VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); - VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); - - /* set xhigh/yhigh and push changes to track_ids */ - rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), - rr_graph.node_ylow(rr_node_id), - chan_coordinate.x(), - chan_coordinate.y()); - - /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ - if ( (rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) - || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id)) ) { - rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.set_node_track_num(rr_node_id, itrack); - } - /* Finish here, go to next */ - } + /* For INC direction, an ending point requires an update on xhigh and yhigh */ + if (((true == chan_details.is_track_end(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack))) + || + /* For DEC direction, an starting point requires an update on xlow and ylow */ + ((true == chan_details.is_track_start(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)))) { + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + + /* set xhigh/yhigh and push changes to track_ids */ + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ + if ((rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) + || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id))) { + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.set_node_track_num(rr_node_id, itrack); + } + /* Finish here, go to next */ + } - /* Finish processing starting and ending tracks */ - if ( (true == chan_details.is_track_start(itrack)) - || (true == chan_details.is_track_end(itrack)) ) { - /* Finish here, go to next */ - continue; - } + /* Finish processing starting and ending tracks */ + if ((true == chan_details.is_track_start(itrack)) + || (true == chan_details.is_track_end(itrack))) { + /* Finish here, go to next */ + continue; + } - /* For other nodes, we get the node_id and just update track_ids */ - /* Ensure those nodes are neither starting nor ending points */ - VTR_ASSERT( (false == chan_details.is_track_start(itrack)) - && (false == chan_details.is_track_end(itrack)) ); + /* For other nodes, we get the node_id and just update track_ids */ + /* Ensure those nodes are neither starting nor ending points */ + VTR_ASSERT((false == chan_details.is_track_start(itrack)) + && (false == chan_details.is_track_end(itrack))); - /* Get the node_id */ - const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); - /* Do a quick check, make sure we do not mistakenly modify other nodes */ - VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); - VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); - /* Deposit xhigh and yhigh using the current chan_coordinate + /* Deposit xhigh and yhigh using the current chan_coordinate * We will update when this track ends */ - rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), - rr_graph.node_ylow(rr_node_id), - chan_coordinate.x(), - chan_coordinate.y()); - - /* Update track_ids */ - rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.set_node_track_num(rr_node_id, itrack); - /* Finish here, go to next */ - } + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Update track_ids */ + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.set_node_track_num(rr_node_id, itrack); + /* Finish here, go to next */ + } } /************************************************************************ @@ -773,62 +754,60 @@ void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, * features: capacity, track_ids, ptc_num, direction * grid_info : pb_graph_pin ***********************************************************************/ -static -void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - - /* For X-direction Channel: CHANX */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ - std::vector track_node_ids; - - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { - vtr::Point chanx_coord(ix, iy); - - /* Bypass if the routing channel does not exist when through channels are not allowed */ - if ( (false == through_channel) - && (false == is_chanx_exist(grids, chanx_coord))) { - continue; - } - - bool force_start = false; - bool force_end = false; - - /* All the tracks have to start when +static void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + /* For X-direction Channel: CHANX */ + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ((false == through_channel) + && (false == is_chanx_exist(grids, chanx_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_start = true; - } + if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_end = true; - } - - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, - force_start, force_end, segment_infs); - /* Force node_ids from the previous chanx */ - if (0 < track_node_ids.size()) { - /* Rotate should be done based on a typical case of routing tracks. + if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chanx */ + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. * Tracks on the borders are not regularly started and ended, * which causes the node_rotation malfunction */ - ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, - false, false, segment_infs); - chanx_details_tt.set_track_node_ids(track_node_ids); + ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, + false, false, segment_infs); + chanx_details_tt.set_track_node_ids(track_node_ids); - /* TODO: + /* TODO: * Do NOT rotate the tracks when the routing channel * locates inside a multi-height and multi-width grid * Let the routing channel passing through the grid (if through channel is allowed!) @@ -840,41 +819,41 @@ void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, * track0 ----->+-----------------------------+----> track0 * | | */ - if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { - /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ - /* For INC_DIRECTION, we use clockwise rotation + if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { + /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ + /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D * node_id B ----> / ----> node_id A * node_id C ----> / ----> node_id B * node_id D ----> ----> node_id C */ - chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); - /* For DEC_DIRECTION, we use clockwise rotation + chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation * node_id A <----- <----- node_id B * node_id B <----- \ <----- node_id C * node_id C <----- \ <----- node_id D * node_id D <----- <----- node_id A */ - chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); + chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chanx_details_tt.get_track_node_ids(); + chanx_details.set_track_node_ids(track_node_ids); + } + + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + chanx_coord, CHANX, + chanx_details, + segment_infs, + CHANX_COST_INDEX_START); + /* Get a copy of node_ids */ + track_node_ids = chanx_details.get_track_node_ids(); } - - track_node_ids = chanx_details_tt.get_track_node_ids(); - chanx_details.set_track_node_ids(track_node_ids); - } - - /* Configure CHANX in this channel */ - load_one_chan_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - chanx_coord, CHANX, - chanx_details, - segment_infs, - CHANX_COST_INDEX_START); - /* Get a copy of node_ids */ - track_node_ids = chanx_details.get_track_node_ids(); } - } } /************************************************************************ @@ -882,65 +861,63 @@ void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, track_ids, ptc_num, direction ***********************************************************************/ -static -void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - - /* For Y-direction Channel: CHANY */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ - std::vector track_node_ids; - - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - vtr::Point chany_coord(ix, iy); - - /* Bypass if the routing channel does not exist when through channel are not allowed */ - if ( (false == through_channel) - && (false == is_chany_exist(grids, chany_coord))) { - continue; - } - - bool force_start = false; - bool force_end = false; - - /* All the tracks have to start when +static void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + /* For Y-direction Channel: CHANY */ + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Point chany_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ((false == through_channel) + && (false == is_chany_exist(grids, chany_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_start = true; - } + if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_end = true; - } + if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_end = true; + } - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, - force_start, force_end, segment_infs); - /* Force node_ids from the previous chany + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chany * This will not be applied when the routing channel is cut off (force to start) */ - if (0 < track_node_ids.size()) { - /* Rotate should be done based on a typical case of routing tracks. + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. * Tracks on the borders are not regularly started and ended, * which causes the node_rotation malfunction */ - ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, - false, false, segment_infs); + ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, + false, false, segment_infs); - chany_details_tt.set_track_node_ids(track_node_ids); + chany_details_tt.set_track_node_ids(track_node_ids); - /* TODO: + /* TODO: * Do NOT rotate the tracks when the routing channel * locates inside a multi-height and multi-width grid * Let the routing channel passing through the grid (if through channel is allowed!) @@ -953,40 +930,40 @@ void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, * | | * we should rotate only once at the bottom side of a grid */ - if (true == is_chany_exist(grids, chany_coord, through_channel)) { - /* Rotate the chany_details by an offset of 1*/ - /* For INC_DIRECTION, we use clockwise rotation + if (true == is_chany_exist(grids, chany_coord, through_channel)) { + /* Rotate the chany_details by an offset of 1*/ + /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D * node_id B ----> / ----> node_id A * node_id C ----> / ----> node_id B * node_id D ----> ----> node_id C */ - chany_details_tt.rotate_track_node_id(1, Direction::INC, true); - /* For DEC_DIRECTION, we use clockwise rotation + chany_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation * node_id A <----- <----- node_id B * node_id B <----- \ <----- node_id C * node_id C <----- \ <----- node_id D * node_id D <----- <----- node_id A */ - chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); + chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chany_details_tt.get_track_node_ids(); + chany_details.set_track_node_ids(track_node_ids); + } + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + chany_coord, CHANY, + chany_details, + segment_infs, + CHANX_COST_INDEX_START + segment_infs.size()); + /* Get a copy of node_ids */ + track_node_ids = chany_details.get_track_node_ids(); } - - track_node_ids = chany_details_tt.get_track_node_ids(); - chany_details.set_track_node_ids(track_node_ids); - } - /* Configure CHANX in this channel */ - load_one_chan_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - chany_coord, CHANY, - chany_details, - segment_infs, - CHANX_COST_INDEX_START + segment_infs.size()); - /* Get a copy of node_ids */ - track_node_ids = chany_details.get_track_node_ids(); } - } } /************************************************************************ @@ -996,24 +973,23 @@ void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, * However, DEC direction routing tracks should have a reversed sequence in * track ids ***********************************************************************/ -static -void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, - std::map>& rr_node_track_ids) { +static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, + std::map>& rr_node_track_ids) { // this should call rr_graph_view to do the job -for (auto& node : rr_graph.nodes()) { - /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ - if ( (CHANX != rr_graph.node_type(node)) - && (CHANY != rr_graph.node_type(node)) ) { - continue; - } - /* Reach here, we must have a node of CHANX or CHANY */ - if (Direction::DEC != rr_graph.node_direction(node)) { - continue; + for (auto& node : rr_graph.nodes()) { + /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ + if ((CHANX != rr_graph.node_type(node)) + && (CHANY != rr_graph.node_type(node))) { + continue; + } + /* Reach here, we must have a node of CHANX or CHANY */ + if (Direction::DEC != rr_graph.node_direction(node)) { + continue; + } + std::reverse(rr_node_track_ids[node].begin(), + rr_node_track_ids[node].end()); } - std::reverse(rr_node_track_ids[node].begin(), - rr_node_track_ids[node].end() ); - } } /************************************************************************ @@ -1029,33 +1005,32 @@ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, const bool& through_channel) { - load_grid_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grids, - wire_to_ipin_switch, - delayless_switch); - - load_chanx_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - grids, - chan_width.x(), - segment_infs, - through_channel); - - load_chany_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - grids, - chan_width.y(), - segment_infs, - through_channel); - - reverse_dec_chan_rr_node_track_ids(rr_graph, - rr_node_track_ids); - + load_grid_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grids, + wire_to_ipin_switch, + delayless_switch); + + load_chanx_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + chan_width.x(), + segment_infs, + through_channel); + + load_chany_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + chan_width.y(), + segment_infs, + through_channel); + + reverse_dec_chan_rr_node_track_ids(rr_graph, + rr_node_track_ids); } } /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 1e90fc2feda..48bfe54bd46 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -1,6 +1,3 @@ -#ifndef TILEABLE_RR_GRAPH_NODE_BUILDER_H -#define TILEABLE_RR_GRAPH_NODE_BUILDER_H - /******************************************************************** * Include header files that are required by function declaration *******************************************************************/ @@ -24,7 +21,7 @@ namespace openfpga { void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, - vtr::vector& driver_switches, + vtr::vector& driver_switches, const DeviceGrid& grids, const vtr::Point& chan_width, const std::vector& segment_infs, @@ -32,10 +29,10 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const vtr::Point& chan_width, + const DeviceGrid& grids, + const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, @@ -43,5 +40,3 @@ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, } /* end namespace openfpga */ - -#endif From b749ce139e9d65d62f38dd3bc6fe671b50c88b02 Mon Sep 17 00:00:00 2001 From: taoli4rs Date: Wed, 27 Jul 2022 23:36:42 -0700 Subject: [PATCH 004/453] Enable tileable rr graph builder for unidir graph arch; code cleanup. --- vpr/src/base/SetupVPR.cpp | 9 ++ vpr/src/base/ShowSetup.cpp | 2 + vpr/src/base/vpr_api.cpp | 3 + vpr/src/base/vpr_types.h | 60 ++++++---- vpr/src/route/rr_graph.cpp | 110 ++++++++---------- vpr/src/route/rr_graph.h | 30 +++++ .../tileable_rr_graph/chan_node_details.cpp | 5 - vpr/src/tileable_rr_graph/chan_node_details.h | 5 - vpr/src/tileable_rr_graph/clb2clb_directs.h | 16 --- vpr/src/tileable_rr_graph/openfpga_port.h | 5 - .../openfpga_rr_graph_utils.cpp | 5 - .../openfpga_rr_graph_utils.h | 5 - .../tileable_rr_graph/openfpga_side_manager.h | 5 - vpr/src/tileable_rr_graph/rr_chan.cpp | 5 - vpr/src/tileable_rr_graph/rr_chan.h | 7 -- .../rr_graph_builder_utils.cpp | 5 - .../rr_graph_builder_utils.h | 5 - vpr/src/tileable_rr_graph/rr_graph_types.h | 4 +- vpr/src/tileable_rr_graph/rr_gsb.cpp | 5 - vpr/src/tileable_rr_graph/rr_gsb.h | 5 - .../tileable_chan_details_builder.cpp | 5 - .../tileable_chan_details_builder.h | 5 - .../tileable_rr_graph_builder.cpp | 64 +++++----- .../tileable_rr_graph_builder.h | 5 - .../tileable_rr_graph_edge_builder.cpp | 12 +- .../tileable_rr_graph_edge_builder.h | 25 ++-- .../tileable_rr_graph_gsb.cpp | 5 - .../tileable_rr_graph/tileable_rr_graph_gsb.h | 38 +++--- .../tileable_rr_graph_node_builder.cpp | 5 - .../tileable_rr_graph_node_builder.h | 7 +- 30 files changed, 200 insertions(+), 267 deletions(-) delete mode 100644 vpr/src/tileable_rr_graph/clb2clb_directs.h mode change 100755 => 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp mode change 100755 => 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index f75745facae..123bbb2d423 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -351,6 +351,10 @@ static void SetupRoutingArch(const t_arch& Arch, /* copy over the switch block information */ RoutingArch->switchblocks = Arch.switchblocks; + + /* Copy the tileable routing setting */ + RoutingArch->tileable = Arch.tileable; + RoutingArch->through_channel = Arch.through_channel; } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { @@ -378,6 +382,11 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->router_algorithm = Options.RouterAlgorithm; RouterOpts->fixed_channel_width = Options.RouteChanWidth; RouterOpts->min_channel_width_hint = Options.min_route_chan_width_hint; + + //TODO document these? + RouterOpts->trim_empty_channels = false; /* DEFAULT */ + RouterOpts->trim_obs_channels = false; /* DEFAULT */ + RouterOpts->read_rr_edge_metadata = Options.read_rr_edge_metadata; RouterOpts->reorder_rr_graph_nodes_algorithm = Options.reorder_rr_graph_nodes_algorithm; RouterOpts->reorder_rr_graph_nodes_threshold = Options.reorder_rr_graph_nodes_threshold; diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index 782038c4a31..a3188fe5eb1 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -302,6 +302,8 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) { VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown check_route value\n"); } + VTR_LOG("RouterOpts.trim_empty_chan: %s\n", (RouterOpts.trim_empty_channels ? "true" : "false")); + VTR_LOG("RouterOpts.trim_obs_chan: %s\n", (RouterOpts.trim_obs_channels ? "true" : "false")); VTR_LOG("RouterOpts.acc_fac: %f\n", RouterOpts.acc_fac); VTR_LOG("RouterOpts.bb_factor: %d\n", RouterOpts.bb_factor); VTR_LOG("RouterOpts.bend_cost: %f\n", RouterOpts.bend_cost); diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index d2b55121543..2f6fc3017f9 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -901,6 +901,9 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + if ((UNI_DIRECTIONAL == det_routing_arch->directionality) && (true == det_routing_arch->tileable)) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } } t_chan_width chan_width = init_chan(chan_width_fac, arch.Chans, graph_directionality); diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 584762da50c..0075939d570 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1200,6 +1200,8 @@ struct t_router_opts { enum e_route_type route_type; int fixed_channel_width; int min_channel_width_hint; /// switchblocks; + /* Xifan Tang: subtype of switch blocks. + * Sub type and Fs are applied to pass tracks + */ + int subFs; + enum e_switch_block_type switch_block_subtype; + + /* Xifan Tang: tileable routing */ + bool tileable; + bool through_channel; + short global_route_switch; short delayless_switch; int wire_to_arch_ipin_switch; @@ -1347,17 +1359,17 @@ struct t_det_routing_arch { * Note that this index will store the index of the segment * relative to its **parallel** segment types, not all segments * as stored in device_ctx. Look in rr_graph.cpp: build_rr_graph - * for details but here is an example: say our segment_inf_vec in + * for details but here is an example: say our segment_inf_vec in * device_ctx is as follows: [seg_a_x, seg_b_x, seg_a_y, seg_b_y] - * when building the rr_graph, static segment_inf_vectors will be - * created for each direction, thus you will have the following - * 2 vectors: X_vec =[seg_a_x,seg_b_x] and Y_vec = [seg_a_y,seg_b_y]. - * As a result, e.g. seg_b_y::index == 1 (index in Y_vec) + * when building the rr_graph, static segment_inf_vectors will be + * created for each direction, thus you will have the following + * 2 vectors: X_vec =[seg_a_x,seg_b_x] and Y_vec = [seg_a_y,seg_b_y]. + * As a result, e.g. seg_b_y::index == 1 (index in Y_vec) * and != 3 (index in device_ctx segment_inf_vec). - * @param abs_index index is relative to the segment_inf vec as stored in device_ctx. - * Note that the above vector is **unifies** both x-parallel and - * y-parallel segments and is loaded up originally in read_xml_arch_file.cpp - * + * @param abs_index index is relative to the segment_inf vec as stored in device_ctx. + * Note that the above vector is **unifies** both x-parallel and + * y-parallel segments and is loaded up originally in read_xml_arch_file.cpp + * * @param type_name_ptr pointer to name of the segment type this track belongs * to. points to the appropriate name in s_segment_inf */ @@ -1441,7 +1453,7 @@ class t_chan_seg_details { const t_seg_details* seg_detail_ = nullptr; }; -/* Defines a 3-D array of t_chan_seg_details data structures (one per-each horizontal and vertical channel) +/* Defines a 3-D array of t_chan_seg_details data structures (one per-each horizontal and vertical channel) * once allocated in rr_graph2.cpp, is can be accessed like: [0..grid.width()][0..grid.height()][0..num_tracks-1] */ typedef vtr::NdMatrix t_chan_details; @@ -1464,14 +1476,14 @@ constexpr bool is_src_sink(e_rr_type type) { return (type == SOURCE || type == S * @brief Basic element used to store the traceback (routing) of each net. * * @param index Array index (ID) of this routing resource node. - * @param net_pin_index: Net pin index associated with the node. This value - * ranges from 1 to fanout [1..num_pins-1]. For cases when - * different speed paths are taken to the same SINK for - * different pins, node index cannot uniquely identify - * each SINK, so the net pin index guarantees an unique - * identification for each SINK node. For non-SINK nodes - * and for SINK nodes with no associated net pin index - * (i.e. special SINKs like the source of a clock tree + * @param net_pin_index: Net pin index associated with the node. This value + * ranges from 1 to fanout [1..num_pins-1]. For cases when + * different speed paths are taken to the same SINK for + * different pins, node index cannot uniquely identify + * each SINK, so the net pin index guarantees an unique + * identification for each SINK node. For non-SINK nodes + * and for SINK nodes with no associated net pin index + * (i.e. special SINKs like the source of a clock tree * which do not correspond to an actual netlist connection), * the value for this member should be set to OPEN (-1). * @param iswitch Index of the switch type used to go from this rr_node to @@ -1604,12 +1616,12 @@ struct t_power_opts { }; /** @brief Channel width data - * @param max= Maximum channel width between x_max and y_max. - * @param x_min= Minimum channel width of horizontal channels. Initialized when init_chan() is invoked in rr_graph2.cpp - * @param y_min= Same as above but for vertical channels. - * @param x_max= Maximum channel width of horiozntal channels. Initialized when init_chan() is invoked in rr_graph2.cpp - * @param y_max= Same as above but for vertical channels. - * @param x_list= Stores the channel width of all horizontal channels and thus goes from [0..grid.height()] + * @param max= Maximum channel width between x_max and y_max. + * @param x_min= Minimum channel width of horizontal channels. Initialized when init_chan() is invoked in rr_graph2.cpp + * @param y_min= Same as above but for vertical channels. + * @param x_max= Maximum channel width of horiozntal channels. Initialized when init_chan() is invoked in rr_graph2.cpp + * @param y_max= Same as above but for vertical channels. + * @param x_list= Stores the channel width of all horizontal channels and thus goes from [0..grid.height()] * (imagine a 2D Cartesian grid with horizontal lines starting at every grid point on a line parallel to the y-axis) * @param y_list= Stores the channel width of all verical channels and thus goes from [0..grid.width()] * (imagine a 2D Cartesian grid with vertical lines starting at every grid point on a line parallel to the x-axis) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 711187fbce8..23ed4a8ce40 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -35,6 +35,7 @@ #include "rr_graph_clock.h" #include "edge_groups.h" #include "rr_graph_builder.h" +#include "tileable_rr_graph_builder.h" #include "rr_types.h" @@ -53,16 +54,6 @@ struct t_mux_size_distribution { t_mux_size_distribution* next; }; -struct t_clb_to_clb_directs { - t_physical_tile_type_ptr from_clb_type; - int from_clb_pin_start_index; - int from_clb_pin_end_index; - t_physical_tile_type_ptr to_clb_type; - int to_clb_pin_start_index; - int to_clb_pin_end_index; - int switch_index; //The switch type used by this direct connection -}; - struct t_pin_loc { int pin_index; int width_offset; @@ -244,11 +235,7 @@ void uniquify_edges(t_rr_edge_info_set& rr_edges_to_create); void alloc_and_load_edges(RRGraphBuilder& rr_graph_builder, const t_rr_edge_info_set& rr_edges_to_create); -static void alloc_and_load_rr_switch_inf(const int num_arch_switches, - const float R_minW_nmos, - const float R_minW_pmos, - const int wire_to_arch_ipin_switch, - int* wire_to_rr_ipin_switch); + static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin); @@ -256,26 +243,9 @@ static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_n static void alloc_rr_switch_inf(t_arch_switch_fanin& switch_fanin); -static void rr_graph_externals(const std::vector& segment_inf, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - int wire_to_rr_ipin_switch, - enum e_base_cost_type base_cost_type); - -static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, const int delayless_switch); - static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, int* num_seg_details = nullptr); -static std::vector> alloc_and_load_actual_fc(const std::vector& types, - const int max_pins, - const std::vector& segment_inf, - const int* sets_per_seg_type, - const t_chan_width* nodes_per_chan, - const e_fc_type fc_type, - const enum e_directionality directionality, - bool* Fc_clipped); - static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_graph, RRNodeId from_rr, const std::vector& candidate_rr_nodes); @@ -344,29 +314,51 @@ void create_rr_graph(const t_graph_type graph_type, } free_rr_graph(); - build_rr_graph(graph_type, - block_types, - grid, - nodes_per_chan, - det_routing_arch->switch_block_type, - det_routing_arch->Fs, - det_routing_arch->switchblocks, - num_arch_switches, - segment_inf, - det_routing_arch->global_route_switch, - det_routing_arch->wire_to_arch_ipin_switch, - det_routing_arch->delayless_switch, - det_routing_arch->R_minW_nmos, - det_routing_arch->R_minW_pmos, - router_opts.base_cost_type, - router_opts.clock_modeling, - directs, num_directs, - &det_routing_arch->wire_to_rr_ipin_switch, - Warnings); - if (router_opts.reorder_rr_graph_nodes_algorithm != DONT_REORDER) { - mutable_device_ctx.rr_graph_builder.reorder_nodes(router_opts.reorder_rr_graph_nodes_algorithm, - router_opts.reorder_rr_graph_nodes_threshold, - router_opts.reorder_rr_graph_nodes_seed); + if (GRAPH_UNIDIR_TILEABLE != graph_type) { + build_rr_graph(graph_type, + block_types, + grid, + nodes_per_chan, + det_routing_arch->switch_block_type, + det_routing_arch->Fs, + det_routing_arch->switchblocks, + num_arch_switches, + segment_inf, + det_routing_arch->global_route_switch, + det_routing_arch->wire_to_arch_ipin_switch, + det_routing_arch->delayless_switch, + det_routing_arch->R_minW_nmos, + det_routing_arch->R_minW_pmos, + router_opts.base_cost_type, + router_opts.clock_modeling, + directs, num_directs, + &det_routing_arch->wire_to_rr_ipin_switch, + Warnings); + if (router_opts.reorder_rr_graph_nodes_algorithm != DONT_REORDER) { + mutable_device_ctx.rr_graph_builder.reorder_nodes(router_opts.reorder_rr_graph_nodes_algorithm, + router_opts.reorder_rr_graph_nodes_threshold, + router_opts.reorder_rr_graph_nodes_seed); + } + } else { + /* We do not support dedicated network for clocks in tileable rr_graph generation */ + build_tileable_unidir_rr_graph(block_types, + grid, + nodes_per_chan, + det_routing_arch->switch_block_type, + det_routing_arch->Fs, + det_routing_arch->switch_block_subtype, + det_routing_arch->subFs, + segment_inf, + det_routing_arch->delayless_switch, + det_routing_arch->wire_to_arch_ipin_switch, + det_routing_arch->R_minW_nmos, + det_routing_arch->R_minW_pmos, + router_opts.base_cost_type, + directs, num_directs, + &det_routing_arch->wire_to_rr_ipin_switch, + router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ + false, /* Do not allow passing tracks to be wired to the same routing channels */ + Warnings); } } @@ -872,7 +864,7 @@ static void build_rr_graph(const t_graph_type graph_type, * and count how many different fan-ins exist for each arch switch. * Then we create these rr switches and update the switch indices * of rr_nodes to index into the rr_switch_inf array. */ -static void alloc_and_load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const int wire_to_arch_ipin_switch, int* wire_to_rr_ipin_switch) { +void alloc_and_load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const int wire_to_arch_ipin_switch, int* wire_to_rr_ipin_switch) { /* we will potentially be creating a couple of versions of each arch switch where * each version corresponds to a different fan-in. We will need to fill device_ctx.rr_switch_inf * with this expanded list of switches. @@ -1033,7 +1025,7 @@ static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin device_ctx.rr_graph_builder.remap_rr_node_switch_indices(switch_fanin); } -static void rr_graph_externals(const std::vector& segment_inf, +void rr_graph_externals(const std::vector& segment_inf, const std::vector& segment_inf_x, const std::vector& segment_inf_y, int wire_to_rr_ipin_switch, @@ -1130,7 +1122,7 @@ static t_seg_details* alloc_and_load_global_route_seg_details(const int global_r } /* Calculates the number of track connections from each block pin to each segment type */ -static std::vector> alloc_and_load_actual_fc(const std::vector& types, +std::vector> alloc_and_load_actual_fc(const std::vector& types, const int max_pins, const std::vector& segment_inf, const int* sets_per_seg_type, @@ -2774,7 +2766,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * This data structure supplements the the info in the "directs" data structure * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one */ -static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch) { +t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch) { int i; t_clb_to_clb_directs* clb_to_clb_directs; char *tile_name, *port_name; diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index e4f29959207..2d230f92fb8 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -9,6 +9,16 @@ #include "device_grid.h" #include "vpr_types.h" +struct t_clb_to_clb_directs { + t_physical_tile_type_ptr from_clb_type; + int from_clb_pin_start_index; + int from_clb_pin_end_index; + t_physical_tile_type_ptr to_clb_type; + int to_clb_pin_start_index; + int to_clb_pin_end_index; + int switch_index; //The switch type used by this direct connection +}; + enum e_graph_type { GRAPH_GLOBAL, /* One node per channel with wire capacity > 1 and full connectivity */ GRAPH_BIDIR, /* Detailed bidirectional graph */ @@ -56,4 +66,24 @@ void load_rr_switch_from_arch_switch(int arch_switch_idx, t_non_configurable_rr_sets identify_non_configurable_rr_sets(); +void rr_graph_externals(const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + int wire_to_rr_ipin_switch, + enum e_base_cost_type base_cost_type); + +std::vector> alloc_and_load_actual_fc(const std::vector& types, + const int max_pins, + const std::vector& segment_inf, + const int* sets_per_seg_type, + const t_chan_width* nodes_per_chan, + const e_fc_type fc_type, + const enum e_directionality directionality, + bool* Fc_clipped); +t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, const int delayless_switch); +void alloc_and_load_rr_switch_inf(const int num_arch_switches, + const float R_minW_nmos, + const float R_minW_pmos, + const int wire_to_arch_ipin_switch, + int* wire_to_rr_ipin_switch); #endif diff --git a/vpr/src/tileable_rr_graph/chan_node_details.cpp b/vpr/src/tileable_rr_graph/chan_node_details.cpp index 3da5f2f29de..3109039b1a7 100644 --- a/vpr/src/tileable_rr_graph/chan_node_details.cpp +++ b/vpr/src/tileable_rr_graph/chan_node_details.cpp @@ -8,9 +8,6 @@ #include "chan_node_details.h" -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * Constructors ***********************************************************************/ @@ -292,5 +289,3 @@ bool ChanNodeDetails::validate_track_id(const size_t& track_id) const { } return false; } - -} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h index b2426ae56a1..4b50d7b2405 100644 --- a/vpr/src/tileable_rr_graph/chan_node_details.h +++ b/vpr/src/tileable_rr_graph/chan_node_details.h @@ -18,9 +18,6 @@ * 4. potentail track_id(ptc_num) of each segment ***********************************************************************/ -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * ChanNodeDetails records segment length, directionality and starting of routing tracks * +---------------------------------+ @@ -72,6 +69,4 @@ class ChanNodeDetails { std::vector track_end_; /* flag to identify if this is the ending point of the track */ }; -} /* end namespace openfpga */ - #endif diff --git a/vpr/src/tileable_rr_graph/clb2clb_directs.h b/vpr/src/tileable_rr_graph/clb2clb_directs.h deleted file mode 100644 index 7cc54bb8813..00000000000 --- a/vpr/src/tileable_rr_graph/clb2clb_directs.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef CLB2CLB_DIRECTS_H -#define CLB2CLB_DIRECTS_H - -#include "physical_types.h" - -struct t_clb_to_clb_directs { - t_physical_tile_type_ptr from_clb_type; - int from_clb_pin_start_index; - int from_clb_pin_end_index; - t_physical_tile_type_ptr to_clb_type; - int to_clb_pin_start_index; - int to_clb_pin_end_index; - int switch_index; //The switch type used by this direct connection -}; - -#endif diff --git a/vpr/src/tileable_rr_graph/openfpga_port.h b/vpr/src/tileable_rr_graph/openfpga_port.h index 3df6d0efa40..2975405ebe5 100644 --- a/vpr/src/tileable_rr_graph/openfpga_port.h +++ b/vpr/src/tileable_rr_graph/openfpga_port.h @@ -7,9 +7,6 @@ #include #include -/* namespace openfpga begins */ -namespace openfpga { - /* A basic port */ class BasicPort { public: /* Constructors */ @@ -90,7 +87,5 @@ class ConfPorts { /* TODO: create a class for BL and WL ports */ -} /* namespace openfpga ends */ - #endif diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index 231781a69b2..c532b888b9b 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -11,9 +11,6 @@ #include "openfpga_rr_graph_utils.h" #include "rr_graph_types.h" -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * Get the coordinator of a starting point of a routing track * For routing tracks in INC_DIRECTION @@ -180,5 +177,3 @@ bool is_ipin_direct_connected_opin(const RRGraph& rr_graph, return true; } - -} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h index ebf741f8d97..1a1801379ec 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h @@ -14,9 +14,6 @@ * Function declaration *******************************************************************/ -/* begin namespace openfpga */ -namespace openfpga { - vtr::Point get_track_rr_node_start_coordinate(const RRGraph& rr_graph, const RRNodeId& track_rr_node); @@ -41,6 +38,4 @@ bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, bool is_ipin_direct_connected_opin(const RRGraph& rr_graph, const RRNodeId& node); -} /* end namespace openfpga */ - #endif diff --git a/vpr/src/tileable_rr_graph/openfpga_side_manager.h b/vpr/src/tileable_rr_graph/openfpga_side_manager.h index 4903f7b4bba..a6eb01d9197 100644 --- a/vpr/src/tileable_rr_graph/openfpga_side_manager.h +++ b/vpr/src/tileable_rr_graph/openfpga_side_manager.h @@ -10,9 +10,6 @@ /* Header files form archfpga library */ #include "physical_types.h" -/* namespace openfpga begins */ -namespace openfpga { - /******************************************************************** * Define a class for the sides of a physical block in FPGA architecture * Basically, each block has four sides : @@ -44,6 +41,4 @@ class SideManager { enum e_side side_; }; -} /* namespace openfpga ends */ - #endif diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp index 556f1893a74..13ba606cefd 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.cpp +++ b/vpr/src/tileable_rr_graph/rr_chan.cpp @@ -5,9 +5,6 @@ #include "vtr_assert.h" #include "rr_chan.h" -/* namespace openfpga begins */ -namespace openfpga { - /************************************************************************ * Constructors ***********************************************************************/ @@ -221,5 +218,3 @@ bool RRChan::valid_node_id(const size_t& node_id) const { return false; } - -} /* End namespace openfpga*/ diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h index d06d894caa8..e6dacde42f8 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.h +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -15,9 +15,6 @@ /* Headers from vpr library */ #include "rr_graph_obj.h" -/* Begin namespace openfpga */ -namespace openfpga { - /******************************************************************** * RRChan object aim to describe a routing channel in a routing resource graph * - What are the nodes in the RRGraph object, for each routing track @@ -87,8 +84,4 @@ class RRChan { std::vector node_segments_; /* segment of each track */ }; - - -} /* End namespace openfpga*/ - #endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index c3653ac3b73..47660c0bd26 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -12,9 +12,6 @@ #include "rr_graph_builder_utils.h" -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * Correct number of routing channel width to be compatible to * uni-directional routing architecture @@ -547,5 +544,3 @@ void print_rr_graph_mux_stats(const RRGraph& rr_graph) { find_rr_graph_average_fan_in(rr_graph, cb_node_types)); VTR_LOG("------------------------------------------------\n"); } - -} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index 6ff78412f06..05628fac18e 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -12,9 +12,6 @@ * Function declaration *******************************************************************/ -/* begin namespace openfpga */ -namespace openfpga { - size_t find_unidir_routing_channel_width(const size_t& chan_width); int get_grid_pin_class_index(const t_grid_tile& cur_grid, @@ -92,7 +89,5 @@ short find_rr_graph_average_fan_in(const RRGraph& rr_graph, void print_rr_graph_mux_stats(const RRGraph& rr_graph); -} /* end namespace openfpga */ - #endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_types.h b/vpr/src/tileable_rr_graph/rr_graph_types.h index 6cf7e1b56eb..5f7297a49c4 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_types.h +++ b/vpr/src/tileable_rr_graph/rr_graph_types.h @@ -1,5 +1,5 @@ -#ifndef RR_GRAPH_TYPES -#define RR_GRAPH_TYPES +#ifndef RR_GRAPH_TYPES_H +#define RR_GRAPH_TYPES_H /******************************************************************** * Data types required by routing resource graph (RRGraph) definition diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 68f287e291c..2a467d61ff5 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -10,9 +10,6 @@ #include "rr_gsb.h" -/* namespace openfpga begins */ -namespace openfpga { - /************************************************************************ * Constructors ***********************************************************************/ @@ -1140,5 +1137,3 @@ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) con bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { return ((CHANX == cb_type) || (CHANY == cb_type)); } - -} /* End namespace openfpga*/ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 279f206f9da..e533007d57a 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -9,9 +9,6 @@ #include "rr_chan.h" -/* Begin namespace openfpga */ -namespace openfpga { - /******************************************************************** * Object Generic Switch Block * This block contains @@ -284,6 +281,4 @@ class RRGSB { std::vector> opin_node_; }; -} /* End namespace openfpga*/ - #endif diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index d2afce3edd7..4c185ecd347 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -14,9 +14,6 @@ #include "rr_graph_builder_utils.h" #include "tileable_chan_details_builder.h" -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * Generate the number of tracks for each types of routing segments * w.r.t. the frequency of each of segments and channel width @@ -230,5 +227,3 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, return chan_node_details; } - -} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h index e6adb71621b..34a476d80e4 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h @@ -12,9 +12,6 @@ * Function declaration *******************************************************************/ -/* begin namespace openfpga */ -namespace openfpga { - std::vector get_num_tracks_per_seg_type(const size_t& chan_width, const std::vector& segment_inf, const bool& use_full_seg_groups); @@ -27,6 +24,4 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const bool& force_end, const std::vector& segment_inf); -} /* end namespace openfpga */ - #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 198c2fc5e1c..1aa8766a73c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -27,9 +27,6 @@ #include "globals.h" -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * Main function of this file * Builder for a detailed uni-directional tileable rr_graph @@ -70,26 +67,6 @@ namespace openfpga { * b. RC tree ***********************************************************************/ -// external functions: in vpr/src/route/rr_graph.cpp -extern std::vector> alloc_and_load_actual_fc(const std::vector& types, - const int max_pins, - const std::vector& segment_inf, - - const int* sets_per_seg_type, - const int max_chan_width, - const e_fc_type fc_type, - const enum e_directionality directionality, - bool* Fc_clipped); -extern t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch); -extern void alloc_and_load_rr_switch_inf(const int num_arch_switches, - const float R_minW_nmos, - const float R_minW_pmos, - const int wire_to_arch_ipin_switch, - int* wire_to_rr_ipin_switch); -extern void rr_graph_externals(const std::vector& segment_inf, - int wire_to_rr_ipin_switch, - enum e_base_cost_type base_cost_type); - void build_tileable_unidir_rr_graph(const std::vector& types, const DeviceGrid& grids, const t_chan_width& chan_width, @@ -157,9 +134,9 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } // NYI #if 0 - /* Validate the special switches */ - VTR_ASSERT(true == device_ctx.rr_graph_builder.valid_switch_id(wire_to_ipin_rr_switch)); - VTR_ASSERT(true == device_ctx.rr_graph_builder.valid_switch_id(delayless_rr_switch)); + /* Validate the special switches */ + VTR_ASSERT(true == device_ctx.rr_graph.validate_node(wire_to_ipin_rr_switch)); + VTR_ASSERT(true == device_ctx.rr_graph.validate_node(delayless_rr_switch)); #endif /* A temp data about the driver switch ids for each rr_node */ @@ -230,7 +207,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ bool Fc_clipped = false; /* [0..num_types-1][0..num_pins-1] */ std::vector> Fc_in; - Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width, + Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*) &chan_width, e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped); if (Fc_clipped) { *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; @@ -239,7 +216,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ Fc_clipped = false; /* [0..num_types-1][0..num_pins-1] */ std::vector> Fc_out; - Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width, + Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*) &chan_width, e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped); if (Fc_clipped) { @@ -255,6 +232,9 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * Add edges that bridge OPINs and IPINs to the rr_graph ***********************************************************************/ /* Create edges for a tileable rr_graph */ + +// Link error: undefined reference to `build_rr_graph_edges` +#if 0 build_rr_graph_edges(device_ctx.rr_graph, rr_node_driver_switches, grids, @@ -263,6 +243,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ Fc_in, Fc_out, sb_type, Fs, sb_subtype, subFs, wire_opposite_side); +#endif /************************************************************************ * Build direction connection lists @@ -280,8 +261,11 @@ void build_tileable_unidir_rr_graph(const std::vector& typ clb2clb_directs.push_back(clb_to_clb_directs[idirect]); } +// Link error: undefined reference to `build_rr_graph_direct_connections` +#if 0 build_rr_graph_direct_connections(device_ctx.rr_graph, grids, delayless_rr_switch, arch_directs, clb2clb_directs); +#endif //NYI #if 0 @@ -309,7 +293,10 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * a. cost_index * b. RC tree ***********************************************************************/ - rr_graph_externals(segment_inf, + t_unified_to_parallel_seg_index segment_index_map; + std::vector segment_inf_x = get_parallel_segs(segment_inf, segment_index_map, X_AXIS); + std::vector segment_inf_y = get_parallel_segs(segment_inf, segment_index_map, Y_AXIS); + rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); /* Rebuild the link between RRGraph node and segments @@ -321,12 +308,14 @@ void build_tileable_unidir_rr_graph(const std::vector& typ && (CHANY != device_ctx.rr_graph.node_type(inode))) { continue; } -//NYI -#if 0 - RRIndexedDataId irc_data = device_ctx.rr_graph.node_cost_index(inode); - short iseg = device_ctx.rr_indexed_data[irc_data].seg_index; - device_ctx.rr_graph_builder.set_node_segment(inode, RRSegmentId(iseg)); // NYI -#endif + // NYI + #if 0 + RRIndexedDataId irc_data = device_ctx.rr_graph.node_cost_index(inode); + short iseg = device_ctx.rr_indexed_data[irc_data].seg_index; + // device_ctx.rr_graph_builder.set_node_segment(inode, RRSegmentId(iseg)); // NYI + vtr::vector rr_segments = device_ctx.rr_graph_builder.rr_segments(); + rr_segments[(RRSegmentId)iseg] = segment_inf; + #endif } /************************************************************************ @@ -345,7 +334,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ // NYI // vpr integration: DeviceContext does not provide direct RRGraph access - // we can skip it since check_rr_graph(GRAPH_UNDIR, GRIDS, TYPES) has been called above + // for advanced rr graph checker in check_rr_graph_obj.h, needs rr graph object + // rr graph view won't work here #if 0 /* Error out if advanced checker of rr_graph fails */ if (false == check_rr_graph(device_ctx.rr_graph)) { @@ -366,5 +356,3 @@ void build_tileable_unidir_rr_graph(const std::vector& typ free(clb_to_clb_directs); } } - -} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h index 46be3817d76..e2372d4d196 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -13,9 +13,6 @@ * Function declaration *******************************************************************/ -/* begin namespace openfpga */ -namespace openfpga { - void build_tileable_unidir_rr_graph(const std::vector& types, const DeviceGrid& grids, const t_chan_width& chan_width, @@ -34,6 +31,4 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const bool& wire_opposite_side, int *Warnings); -} /* end namespace openfpga */ - #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 3252bd412c9..3a2ea544605 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -15,14 +15,11 @@ #include "tileable_rr_graph_gsb.h" #include "tileable_rr_graph_edge_builder.h" -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * Build the edges for all the SOURCE and SINKs nodes: * 1. create edges between SOURCE and OPINs ***********************************************************************/ -static void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, +void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids) { for (const RRNodeId& node : rr_graph.nodes()) { @@ -51,7 +48,7 @@ static void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, * Build the edges for all the SINKs nodes: * 1. create edges between IPINs and SINKs ***********************************************************************/ -static void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, +void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids) { for (const RRNodeId& node : rr_graph.nodes()) { @@ -79,8 +76,8 @@ static void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, * Build the edges of each rr_node tile by tile: * We classify rr_nodes into a general switch block (GSB) data structure * where we create edges to each rr_nodes in the GSB with respect to - * Fc_in and Fc_out, switch block patterns - * For each GSB: + * Fc_in and Fc_out, switch block patterns + * For each GSB: * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) * 3. create edges between OPINs and IPINs (direct-connections) @@ -166,4 +163,3 @@ void build_rr_graph_direct_connections(RRGraph& rr_graph, } } -} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 936b9944f50..1d92f4fc7c0 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -1,3 +1,6 @@ +#ifndef BILEABLE_RR_GRAPH_EDGE_BUILDER_H +#define BILEABLE_RR_GRAPH_EDGE_BUILDER_H + /******************************************************************** * Include header files that are required by function declaration *******************************************************************/ @@ -10,16 +13,13 @@ #include "physical_types.h" #include "device_grid.h" #include "rr_graph_obj.h" -#include "clb2clb_directs.h" #include "rr_graph_view.h" +#include "rr_graph.h" /******************************************************************** * Function declaration *******************************************************************/ -/* begin namespace openfpga */ -namespace openfpga { - void build_rr_graph_edges(RRGraphView& rr_graph, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, @@ -27,8 +27,10 @@ void build_rr_graph_edges(RRGraphView& rr_graph, const std::vector& segment_inf, const std::vector>& Fc_in, const std::vector>& Fc_out, - const e_switch_block_type& sb_type, const int& Fs, - const e_switch_block_type& sb_subtype, const int& subFs, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, const bool& wire_opposite_side); void build_rr_graph_direct_connections(RRGraphView& rr_graph, @@ -37,4 +39,13 @@ void build_rr_graph_direct_connections(RRGraphView& rr_graph, const std::vector& directs, const std::vector& clb_to_clb_directs); -} /* end namespace openfpga */ +void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids); + +void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids); + +#endif + diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp old mode 100755 new mode 100644 index 6aab10566ea..4d23c3b723c --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -20,9 +20,6 @@ #include "tileable_chan_details_builder.h" #include "tileable_rr_graph_gsb.h" -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * Internal data structures ***********************************************************************/ @@ -1428,5 +1425,3 @@ void build_direct_connections_for_one_gsb(RRGraph& rr_graph, } } } - -} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h old mode 100755 new mode 100644 index adf6118fbbe..fbe3a90f89a --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -1,6 +1,5 @@ #ifndef TILEABLE_RR_GRAPH_GSB_H #define TILEABLE_RR_GRAPH_GSB_H - /******************************************************************** * Include header files that are required by function declaration *******************************************************************/ @@ -14,41 +13,38 @@ #include "rr_gsb.h" #include "rr_graph_obj.h" -#include "clb2clb_directs.h" +#include "rr_graph.h" /******************************************************************** * Function declaration *******************************************************************/ -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ - * Data stuctures related to the functions + * Data stuctures related to the functions ***********************************************************************/ typedef std::vector>> t_track2track_map; typedef std::vector>> t_track2pin_map; typedef std::vector>> t_pin2track_map; /************************************************************************ - * Functions + * Functions ***********************************************************************/ t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph, const RRGSB& rr_gsb, - const e_switch_block_type& sb_type, + const e_switch_block_type& sb_type, const int& Fs, - const e_switch_block_type& sb_subtype, + const e_switch_block_type& sb_subtype, const int& subFs, const bool& wire_opposite_side, const std::vector& segment_inf); -RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, +RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const RRGraph& rr_graph, - const vtr::Point& device_chan_width, + const vtr::Point& device_chan_width, const std::vector& segment_inf, const vtr::Point& gsb_coordinate); -void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, +void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, const RRGSB& rr_gsb, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, @@ -56,25 +52,23 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, const vtr::vector& rr_node_driver_switches); t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const DeviceGrid& grids, - const std::vector& segment_inf, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, const std::vector>& Fc_in); t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph, - const RRGSB& rr_gsb, - const DeviceGrid& grids, - const std::vector& segment_inf, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, const std::vector>& Fc_out); void build_direct_connections_for_one_gsb(RRGraph& rr_graph, const DeviceGrid& grids, const vtr::Point& from_grid_coordinate, - const RRSwitchId& delayless_switch, - const std::vector& directs, + const RRSwitchId& delayless_switch, + const std::vector& directs, const std::vector& clb_to_clb_directs); -} /* end namespace openfpga */ - #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 3d4627576bd..20727607473 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -21,9 +21,6 @@ #include "tileable_rr_graph_node_builder.h" #include "rr_rc_data.h" -/* begin namespace openfpga */ -namespace openfpga { - /************************************************************************ * Find the number output pins by considering all the grid ***********************************************************************/ @@ -1032,5 +1029,3 @@ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, reverse_dec_chan_rr_node_track_ids(rr_graph, rr_node_track_ids); } - -} /* end namespace openfpga */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 48bfe54bd46..c555c19a178 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -1,3 +1,5 @@ +#ifndef TILEABLE_RR_GRAPH_NODE_BUILDER_H +#define TILEABLE_RR_GRAPH_NODE_BUILDER_H /******************************************************************** * Include header files that are required by function declaration *******************************************************************/ @@ -17,9 +19,6 @@ * Function declaration *******************************************************************/ -/* begin namespace openfpga */ -namespace openfpga { - void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& driver_switches, const DeviceGrid& grids, @@ -38,5 +37,5 @@ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, const RRSwitchId& delayless_switch, const bool& through_channel); +#endif -} /* end namespace openfpga */ From 3932e1d1192bc219261e098655fafafe8c40e231 Mon Sep 17 00:00:00 2001 From: taoli4rs Date: Thu, 28 Jul 2022 16:24:07 -0700 Subject: [PATCH 005/453] Fix typo. --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 1d92f4fc7c0..0d5c31af691 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -1,5 +1,5 @@ -#ifndef BILEABLE_RR_GRAPH_EDGE_BUILDER_H -#define BILEABLE_RR_GRAPH_EDGE_BUILDER_H +#ifndef TILEABLE_RR_GRAPH_EDGE_BUILDER_H +#define TILEABLE_RR_GRAPH_EDGE_BUILDER_H /******************************************************************** * Include header files that are required by function declaration From aecd504a283a1e04112e34f386b9ce3afa049f70 Mon Sep 17 00:00:00 2001 From: taoli4rs Date: Fri, 29 Jul 2022 22:58:08 -0700 Subject: [PATCH 006/453] Add missing tileable rr graph functions and support class to make it compileable. --- libs/libvtrutil/src/vtr_geometry.tpp | 5 + vpr/src/tileable_rr_graph/openfpga_port.cpp | 439 +++++ .../openfpga_rr_graph_utils.cpp | 61 +- .../openfpga_rr_graph_utils.h | 17 +- .../openfpga_side_manager.cpp | 171 ++ vpr/src/tileable_rr_graph/rr_chan.cpp | 6 +- vpr/src/tileable_rr_graph/rr_chan.h | 8 +- .../tileable_rr_graph/rr_graph_obj_util.cpp | 161 ++ vpr/src/tileable_rr_graph/rr_graph_obj_util.h | 9 +- vpr/src/tileable_rr_graph/rr_gsb.cpp | 61 +- vpr/src/tileable_rr_graph/rr_gsb.h | 31 +- .../tileable_rr_graph_builder.cpp | 10 +- .../tileable_rr_graph_edge_builder.cpp | 41 +- .../tileable_rr_graph_edge_builder.h | 12 +- .../tileable_rr_graph_gsb.cpp | 67 +- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 15 +- .../tileable_rr_graph_node_builder.cpp | 1430 +++++++++-------- .../tileable_rr_graph_node_builder.h | 12 +- 18 files changed, 1748 insertions(+), 808 deletions(-) create mode 100644 vpr/src/tileable_rr_graph/openfpga_port.cpp create mode 100644 vpr/src/tileable_rr_graph/openfpga_side_manager.cpp create mode 100644 vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 2010700fc50..c3e25dcf8a9 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -3,6 +3,11 @@ namespace vtr { * Point */ +template +Point::Point() { + //pass +} + template Point::Point(T x_val, T y_val) noexcept : x_(x_val) diff --git a/vpr/src/tileable_rr_graph/openfpga_port.cpp b/vpr/src/tileable_rr_graph/openfpga_port.cpp new file mode 100644 index 00000000000..7cfd03b20f5 --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_port.cpp @@ -0,0 +1,439 @@ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" + +#include "openfpga_port.h" + +/************************************************************************ + * Member functions for BasicPort class + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ +/* Default constructor */ +BasicPort::BasicPort() { + /* By default we set an invalid port, which size is 0 */ + lsb_ = 1; + msb_ = 0; + + origin_port_width_ = -1; +} + +/* Quick constructor */ +BasicPort::BasicPort(const char* name, const size_t& lsb, const size_t& msb) { + set_name(std::string(name)); + set_width(lsb, msb); + set_origin_port_width(-1); +} + +BasicPort::BasicPort(const std::string& name, const size_t& lsb, const size_t& msb) { + set_name(name); + set_width(lsb, msb); + set_origin_port_width(-1); +} + +BasicPort::BasicPort(const char* name, const size_t& width) { + set_name(std::string(name)); + set_width(width); + set_origin_port_width(-1); +} + +BasicPort::BasicPort(const std::string& name, const size_t& width) { + set_name(name); + set_width(width); + set_origin_port_width(-1); +} + +/************************************************************************ + * Accessors + ***********************************************************************/ +/* get the port width */ +size_t BasicPort::get_width() const { + if (true == is_valid()) { + return msb_ - lsb_ + 1; + } + return 0; /* invalid port has a zero width */ +} + +/* get the LSB */ +size_t BasicPort::get_msb() const { + return msb_; +} + +/* get the LSB */ +size_t BasicPort::get_lsb() const { + return lsb_; +} + +/* get the name */ +std::string BasicPort::get_name() const { + return name_; +} + +/* Make a range of the pin indices */ +std::vector BasicPort::pins() const { + std::vector pin_indices; + + /* Return if the port is invalid */ + if (false == is_valid()) { + return pin_indices; /* Return an empty vector */ + } + /* For valid ports, create a vector whose length is the port width */ + pin_indices.resize(get_width()); + /* Fill in an incremental sequence */ + std::iota(pin_indices.begin(), pin_indices.end(), get_lsb()); + /* Ensure the last one is MSB */ + VTR_ASSERT(get_msb() == pin_indices.back()); + + return pin_indices; +} + +/* Check if a port can be merged with this port: their name should be the same */ +bool BasicPort::mergeable(const BasicPort& portA) const { + return (0 == this->get_name().compare(portA.get_name())); +} + +/* Check if a port is contained by this port: + * this function will check if the (LSB, MSB) of portA + * is contained by the (LSB, MSB) of this port + */ +bool BasicPort::contained(const BasicPort& portA) const { + return ( lsb_ <= portA.get_lsb() && portA.get_msb() <= msb_ ); +} + +/* Set original port width */ +size_t BasicPort::get_origin_port_width() const { + return origin_port_width_; +} + +/************************************************************************ + * Overloaded operators + ***********************************************************************/ +/* Two ports are the same only when: + * 1. port names are the same + * 2. LSBs are the same + * 3. MSBs are the same + */ +bool BasicPort::operator== (const BasicPort& portA) const { + if ( (0 == this->get_name().compare(portA.get_name())) + && (this->get_lsb() == portA.get_lsb()) + && (this->get_msb() == portA.get_msb()) ) { + return true; + } + return false; +} + +bool BasicPort::operator< (const BasicPort& portA) const { + if ( (0 == this->get_name().compare(portA.get_name())) + && (this->get_lsb() < portA.get_lsb()) + && (this->get_msb() < portA.get_msb()) ) { + return true; + } + return false; +} + + +/************************************************************************ + * Mutators + ***********************************************************************/ +/* copy */ +void BasicPort::set(const BasicPort& basic_port) { + name_ = basic_port.get_name(); + lsb_ = basic_port.get_lsb(); + msb_ = basic_port.get_msb(); + origin_port_width_ = basic_port.get_origin_port_width(); + + return; +} + +/* set the port LSB and MSB */ +void BasicPort::set_name(const std::string& name) { + name_ = name; + return; +} + +/* set the port LSB and MSB */ +void BasicPort::set_width(const size_t& width) { + if (0 == width) { + make_invalid(); + return; + } + lsb_ = 0; + msb_ = width - 1; + return; +} + +/* set the port LSB and MSB */ +void BasicPort::set_width(const size_t& lsb, const size_t& msb) { + /* If lsb and msb is invalid, we make a default port */ + if (lsb > msb) { + make_invalid(); + return; + } + set_lsb(lsb); + set_msb(msb); + return; +} + +void BasicPort::set_lsb(const size_t& lsb) { + lsb_ = lsb; + return; +} + +void BasicPort::set_msb(const size_t& msb) { + msb_ = msb; + return; +} + +void BasicPort::set_origin_port_width(const size_t& origin_port_width) { + origin_port_width_ = origin_port_width; + return; +} + +/* Increase the port width */ +void BasicPort::expand(const size_t& width) { + if (0 == width) { + return; /* ignore zero-width port */ + } + /* If current port is invalid, we do not combine */ + if (0 == get_width()) { + lsb_ = 0; + msb_ = width; + return; + } + /* Increase MSB */ + msb_ += width; + return; +} + +/* Swap lsb and msb */ +void BasicPort::revert() { + std::swap(lsb_, msb_); + return; +} + +/* rotate: increase both lsb and msb by an offset */ +bool BasicPort::rotate(const size_t& offset) { + /* If offset is 0, we do nothing */ + if (0 == offset) { + return true; + } + + /* If current width is 0, we set a width using the offset! */ + if (0 == get_width()) { + set_width(offset); + return true; + } + /* check if leads to overflow: + * if limits - msb is larger than offset + */ + if ( (std::numeric_limits::max() - msb_ < offset) ) { + return false; + } + /* Increase LSB and MSB */ + lsb_ += offset; + msb_ += offset; + return true; +} + +/* rotate: decrease both lsb and msb by an offset */ +bool BasicPort::counter_rotate(const size_t& offset) { + /* If current port is invalid or offset is 0, + * we do nothing + */ + if ((0 == offset) || (0 == get_width())) { + return true; + } + /* check if leads to overflow: + * if limits is larger than offset + */ + if ( (std::numeric_limits::min() + lsb_ < offset) ) { + return false; + } + /* decrease LSB and MSB */ + lsb_ -= offset; + msb_ -= offset; + return true; +} + +/* Reset to initial port */ +void BasicPort::reset() { + make_invalid(); + return; +} + +/* Combine two ports */ +void BasicPort::combine(const BasicPort& port) { + /* LSB follows the current LSB */ + /* MSB increases */ + VTR_ASSERT(0 < port.get_width() ); /* Make sure port is valid */ + /* If current port is invalid, we do not combine */ + if (0 == get_width()) { + return; + } + /* Increase MSB */ + msb_ += port.get_width(); + return; +} + +/* A restricted combine function for two ports, + * Following conditions will be applied: + * 1. the two ports have the same name + * Note: you must run mergable() function first + * to make sure this assumption is valid + * 2. the new MSB will be the maximum MSB of the two ports + * 3. the new LSB will be the minimum LSB of the two ports + * 4. both ports should be valid!!! + */ +void BasicPort::merge(const BasicPort& portA) { + VTR_ASSERT(true == this->mergeable(portA)); + VTR_ASSERT(true == this->is_valid() && true == portA.is_valid()); + /* We skip merging if the portA is already contained by this port */ + if (true == this->contained(portA)) { + return; + } + /* LSB follows the minium LSB of the two ports */ + lsb_ = std::min((int)lsb_, (int)portA.get_lsb()); + /* MSB follows the minium MSB of the two ports */ + msb_ = std::max((int)msb_, (int)portA.get_msb()); + /* Origin port width follows the maximum of the two ports */ + msb_ = std::max((int)origin_port_width_, (int)portA.get_origin_port_width()); + return; +} + +/* Internal functions */ +/* Make a port to be invalid: msb < lsb */ +void BasicPort::make_invalid() { + /* set a default invalid port */ + lsb_ = 1; + msb_ = 0; + return; +} + +/* check if port size is valid > 0 */ +bool BasicPort::is_valid() const { + /* msb should be equal or greater than lsb, if this is a valid port */ + if ( msb_ < lsb_ ) { + return false; + } + return true; +} + +/************************************************************************ + * ConfPorts member functions + ***********************************************************************/ + +/************************************************************************ + * Constructor + ***********************************************************************/ +/* Default constructor */ +ConfPorts::ConfPorts() { + /* default port */ + reserved_.reset(); + regular_.reset(); +} + +/* copy */ +ConfPorts::ConfPorts(const ConfPorts& conf_ports) { + set(conf_ports); +} + +/************************************************************************ + * Accessors + ***********************************************************************/ +size_t ConfPorts::get_reserved_port_width() const { + return reserved_.get_width(); +} + +size_t ConfPorts::get_reserved_port_lsb() const { + return reserved_.get_lsb(); +} + +size_t ConfPorts::get_reserved_port_msb() const { + return reserved_.get_msb(); +} + +size_t ConfPorts::get_regular_port_width() const { + return regular_.get_width(); +} + +size_t ConfPorts::get_regular_port_lsb() const { + return regular_.get_lsb(); +} + +size_t ConfPorts::get_regular_port_msb() const { + return regular_.get_msb(); +} + +/************************************************************************ + * Mutators + ***********************************************************************/ +void ConfPorts::set(const ConfPorts& conf_ports) { + set_reserved_port(conf_ports.get_reserved_port_width()); + set_regular_port(conf_ports.get_regular_port_lsb(), conf_ports.get_regular_port_msb()); + return; +} + +void ConfPorts::set_reserved_port(size_t width) { + reserved_.set_width(width); + return; +} + +void ConfPorts::set_regular_port(size_t width) { + regular_.set_width(width); + return; +} + +void ConfPorts::set_regular_port(size_t lsb, size_t msb) { + regular_.set_width(lsb, msb); + return; +} + +void ConfPorts::set_regular_port_lsb(size_t lsb) { + regular_.set_lsb(lsb); + return; +} + +void ConfPorts::set_regular_port_msb(size_t msb) { + regular_.set_msb(msb); + return; +} + +/* Increase the port width of reserved port */ +void ConfPorts::expand_reserved_port(size_t width) { + reserved_.expand(width); + return; +} + +/* Increase the port width of regular port */ +void ConfPorts::expand_regular_port(size_t width) { + regular_.expand(width); + return; +} + +/* Increase the port width of both ports */ +void ConfPorts::expand(size_t width) { + expand_reserved_port(width); + expand_regular_port(width); +} + +/* rotate */ +bool ConfPorts::rotate_regular_port(size_t offset) { + return regular_.rotate(offset); +} + +/* counter rotate */ +bool ConfPorts::counter_rotate_regular_port(size_t offset) { + return regular_.counter_rotate(offset); +} + +/* Reset to initial port */ +void ConfPorts::reset() { + reserved_.reset(); + regular_.reset(); + return; +} diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index c532b888b9b..b237e104443 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -10,6 +10,8 @@ #include "openfpga_rr_graph_utils.h" #include "rr_graph_types.h" +#include "rr_graph_view.h" +#include "vtr_geometry.h" /************************************************************************ * Get the coordinator of a starting point of a routing track @@ -19,7 +21,7 @@ * For routing tracks in DEC_DIRECTION * (xhigh, yhigh) should be the starting point ***********************************************************************/ -vtr::Point get_track_rr_node_start_coordinate(const RRGraph& rr_graph, +vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node) { /* Make sure we have CHANX or CHANY */ VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) @@ -45,7 +47,7 @@ vtr::Point get_track_rr_node_start_coordinate(const RRGraph& rr_graph, * For routing tracks in DEC_DIRECTION * (xlow, ylow) should be the starting point ***********************************************************************/ -vtr::Point get_track_rr_node_end_coordinate(const RRGraph& rr_graph, +vtr::Point get_track_rr_node_end_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node) { /* Make sure we have CHANX or CHANY */ VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) @@ -67,14 +69,22 @@ vtr::Point get_track_rr_node_end_coordinate(const RRGraph& rr_graph, * Find the driver switches for a node in the rr_graph * This function only return unique driver switches ***********************************************************************/ -std::vector get_rr_graph_driver_switches(const RRGraph& rr_graph, +std::vector get_rr_graph_driver_switches(const RRGraphView& rr_graph, const RRNodeId& node) { + std::vector driver_switches; + +// NYI +// unused argements + (void)(rr_graph); + (void)(node); +#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) { driver_switches.push_back(rr_graph.edge_switch(edge)); } } +#endif return driver_switches; } @@ -82,12 +92,19 @@ std::vector get_rr_graph_driver_switches(const RRGraph& rr_graph, /************************************************************************ * Find the driver nodes for a node in the rr_graph ***********************************************************************/ -std::vector get_rr_graph_driver_nodes(const RRGraph& rr_graph, +std::vector get_rr_graph_driver_nodes(const RRGraphView& rr_graph, const RRNodeId& node) { std::vector driver_nodes; + +// NYI +// unused argements + (void)(rr_graph); + (void)(node); +#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { driver_nodes.push_back(rr_graph.edge_src_node(edge)); } +#endif return driver_nodes; } @@ -95,9 +112,17 @@ std::vector get_rr_graph_driver_nodes(const RRGraph& rr_graph, /************************************************************************ * Find the configurable driver nodes for a node in the rr_graph ***********************************************************************/ -std::vector get_rr_graph_configurable_driver_nodes(const RRGraph& rr_graph, +std::vector get_rr_graph_configurable_driver_nodes(const RRGraphView& rr_graph, const RRNodeId& node) { std::vector driver_nodes; + +// NYI +// unused argements + (void)(rr_graph); + (void)(node); +#if 0 + (void)(rr_graph); + (void)(node); for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { /* Bypass non-configurable edges */ if (false == rr_graph.edge_is_configurable(edge)) { @@ -105,6 +130,7 @@ std::vector get_rr_graph_configurable_driver_nodes(const RRGraph& rr_g } driver_nodes.push_back(rr_graph.edge_src_node(edge)); } +#endif return driver_nodes; } @@ -112,9 +138,15 @@ std::vector get_rr_graph_configurable_driver_nodes(const RRGraph& rr_g /************************************************************************ * Find the configurable driver nodes for a node in the rr_graph ***********************************************************************/ -std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraph& rr_graph, +std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphView& rr_graph, const RRNodeId& node) { std::vector driver_nodes; + +// NYI +// unused argements + (void)(rr_graph); + (void)(node); +#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { /* Bypass configurable edges */ if (true == rr_graph.edge_is_configurable(edge)) { @@ -122,6 +154,7 @@ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraph& } driver_nodes.push_back(rr_graph.edge_src_node(edge)); } +#endif return driver_nodes; } @@ -132,11 +165,16 @@ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraph& * - Have only 1 fan-out * - The only fan-out is an IPIN ***********************************************************************/ -bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, +bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, const RRNodeId& node) { /* We only accept OPIN */ VTR_ASSERT(OPIN == rr_graph.node_type(node)); +// NYI +// unused argements + (void)(rr_graph); + (void)(node); +#if 0 if (1 != rr_graph.node_out_edges(node).size()) { return false; } @@ -148,6 +186,7 @@ bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, return false; } } +#endif return true; } @@ -158,11 +197,16 @@ bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, * - Have only 1 fan-in * - The only fan-in is an OPIN ***********************************************************************/ -bool is_ipin_direct_connected_opin(const RRGraph& rr_graph, +bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, const RRNodeId& node) { /* We only accept IPIN */ VTR_ASSERT(IPIN == rr_graph.node_type(node)); +// NYI +// unused argements + (void)(rr_graph); + (void)(node); +#if 0 if (1 != rr_graph.node_in_edges(node).size()) { return false; } @@ -174,6 +218,7 @@ bool is_ipin_direct_connected_opin(const RRGraph& rr_graph, return false; } } +#endif return true; } diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h index 1a1801379ec..69668d762c7 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h @@ -9,33 +9,34 @@ /* Headers from vpr library */ #include "rr_graph_obj.h" +#include "rr_graph_view.h" /******************************************************************** * Function declaration *******************************************************************/ -vtr::Point get_track_rr_node_start_coordinate(const RRGraph& rr_graph, +vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node); -vtr::Point get_track_rr_node_end_coordinate(const RRGraph& rr_graph, +vtr::Point get_track_rr_node_end_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node); -std::vector get_rr_graph_driver_switches(const RRGraph& rr_graph, +std::vector get_rr_graph_driver_switches(const RRGraphView& rr_graph, const RRNodeId& node); -std::vector get_rr_graph_driver_nodes(const RRGraph& rr_graph, +std::vector get_rr_graph_driver_nodes(const RRGraphView& rr_graph, const RRNodeId& node); -std::vector get_rr_graph_configurable_driver_nodes(const RRGraph& rr_graph, +std::vector get_rr_graph_configurable_driver_nodes(const RRGraphView& rr_graph, const RRNodeId& node); -std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraph& rr_graph, +std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphView& rr_graph, const RRNodeId& node); -bool is_opin_direct_connected_ipin(const RRGraph& rr_graph, +bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, const RRNodeId& node); -bool is_ipin_direct_connected_opin(const RRGraph& rr_graph, +bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, const RRNodeId& node); #endif diff --git a/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp b/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp new file mode 100644 index 00000000000..ceb93882d23 --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp @@ -0,0 +1,171 @@ +/******************************************************************** + * Memeber function for class SideManagerManager + *******************************************************************/ +#include "openfpga_side_manager.h" + +/* Constructors */ +SideManager::SideManager(enum e_side side) { + side_ = side; +} + +SideManager::SideManager() { + side_ = NUM_SIDES; +} + +SideManager::SideManager(size_t side) { + set_side(side); +} + +/* Public Accessors */ +enum e_side SideManager::get_side() const { + return side_; +} + +enum e_side SideManager::get_opposite() const { + switch (side_) { + case TOP: + return BOTTOM; + case RIGHT: + return LEFT; + case BOTTOM: + return TOP; + case LEFT: + return RIGHT; + default: + return NUM_SIDES; + } +} + +enum e_side SideManager::get_rotate_clockwise() const { + switch (side_) { + case TOP: + return RIGHT; + case RIGHT: + return BOTTOM; + case BOTTOM: + return LEFT; + case LEFT: + return TOP; + default: + return NUM_SIDES; + } +} + +enum e_side SideManager::get_rotate_counterclockwise() const { + switch (side_) { + case TOP: + return LEFT; + case RIGHT: + return TOP; + case BOTTOM: + return RIGHT; + case LEFT: + return BOTTOM; + default: + return NUM_SIDES; + } +} + +bool SideManager::validate() const { + if (NUM_SIDES == side_) { + return false; + } + return true; +} + +size_t SideManager::to_size_t() const { + switch (side_) { + case TOP: + return 0; + case RIGHT: + return 1; + case BOTTOM: + return 2; + case LEFT: + return 3; + default: + return 4; + } +} + +/* Convert to char* */ +const char* SideManager::c_str() const { + switch (side_) { + case TOP: + return "top"; + case RIGHT: + return "right"; + case BOTTOM: + return "bottom"; + case LEFT: + return "left"; + default: + return "invalid_side"; + } +} + +/* Convert to char* */ +std::string SideManager::to_string() const { + std::string ret; + switch (side_) { + case TOP: + ret.assign("top"); + break; + case RIGHT: + ret.assign("right"); + break; + case BOTTOM: + ret.assign("bottom"); + break; + case LEFT: + ret.assign("left"); + break; + default: + ret.assign("invalid_side"); + break; + } + + return ret; +} + +/* Public Mutators */ +void SideManager::set_side(size_t side) { + switch (side) { + case 0: + side_ = TOP; + return; + case 1: + side_ = RIGHT; + return; + case 2: + side_ = BOTTOM; + return; + case 3: + side_ = LEFT; + return; + default: + side_ = NUM_SIDES; + return; + } +} + +void SideManager::set_side(enum e_side side) { + side_ = side; + return; +} + +void SideManager::set_opposite() { + side_ = get_opposite(); + return; +} + +void SideManager::rotate_clockwise() { + side_ = get_rotate_clockwise(); + return; +} + +void SideManager::rotate_counterclockwise() { + side_ = get_rotate_counterclockwise(); + return; +} + diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp index 13ba606cefd..2f69bd659b1 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.cpp +++ b/vpr/src/tileable_rr_graph/rr_chan.cpp @@ -67,7 +67,7 @@ RRSegmentId RRChan::get_node_segment(const size_t& track_num) const { } /* evaluate if two RRChan is mirror to each other */ -bool RRChan::is_mirror(const RRGraph& rr_graph, const RRChan& cand) const { +bool RRChan::is_mirror(const RRGraphView& rr_graph, const RRChan& cand) const { /* If any following element does not match, it is not mirror */ /* 1. type */ if (this->get_type() != cand.get_type()) { @@ -166,7 +166,7 @@ void RRChan::reserve_node(const size_t& node_size) { } /* add a node to the array */ -void RRChan::add_node(const RRGraph& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment) { +void RRChan::add_node(const RRGraphView& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment) { /* fill the dedicated element in the vector */ nodes_.push_back(node); node_segments_.push_back(node_segment); @@ -198,7 +198,7 @@ bool RRChan::valid_type(const t_rr_type& type) const { } /* Check each node, see if the node type is consistent with the type */ -bool RRChan::valid_node_type(const RRGraph& rr_graph, const RRNodeId& node) const { +bool RRChan::valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const { valid_type(rr_graph.node_type(node)); if (NUM_RR_TYPES == type_) { return true; diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h index e6dacde42f8..effa69273f7 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.h +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -15,6 +15,8 @@ /* Headers from vpr library */ #include "rr_graph_obj.h" +#include "rr_graph_view.h" + /******************************************************************** * RRChan object aim to describe a routing channel in a routing resource graph * - What are the nodes in the RRGraph object, for each routing track @@ -48,7 +50,7 @@ class RRChan { RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */ RRSegmentId get_node_segment(const RRNodeId& node) const; RRSegmentId get_node_segment(const size_t& track_num) const; - bool is_mirror(const RRGraph& rr_graph, const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */ + bool is_mirror(const RRGraphView& rr_graph, const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */ std::vector get_segment_ids() const; /* Get a list of segments used in this routing channel */ std::vector get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const; /* Get a list of segments used in this routing channel */ public: /* Mutators */ @@ -62,7 +64,7 @@ class RRChan { void reserve_node(const size_t& node_size); /* add a node to the routing channel */ - void add_node(const RRGraph& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment); + void add_node(const RRGraphView& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment); /* clear the content */ void clear(); @@ -73,7 +75,7 @@ class RRChan { bool valid_type(const t_rr_type& type) const; /* Check each node, see if the node type is consistent with the type of routing channel */ - bool valid_node_type(const RRGraph& rr_graph, const RRNodeId& node) const; + bool valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const; /* Validate if the track number in the range */ bool valid_node_id(const size_t& node_id) const; diff --git a/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp new file mode 100644 index 00000000000..bef1c745557 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp @@ -0,0 +1,161 @@ +/**************************************************************************** + * This file include most-utilized functions that manipulate on the + * RRGraph object + ***************************************************************************/ +#include "rr_graph_obj.h" +#include "rr_graph_obj_util.h" + +/**************************************************************************** + * Find the switches interconnecting two nodes + * Return a vector of switch ids + ***************************************************************************/ +std::vector find_rr_graph_switches(const RRGraphView& rr_graph, + const RRNodeId& from_node, + const RRNodeId& to_node) { + + std::vector switches; + + // NYI + // unused parameters + (void)(rr_graph); + (void)(from_node); + (void)(to_node); + #if 0 + std::vector edges = rr_graph.find_edges(from_node, to_node); + if (true == edges.empty()) { + /* edge is open, we return an empty vector of switches */ + return switches; + } + + /* Reach here, edge list is not empty, find switch id one by one + * and update the switch list + */ + for (auto edge : edges) { + switches.push_back(rr_graph.edge_switch(edge)); + } + #endif + + return switches; +} + +/********************************************************************* + * Like the RRGraph.find_node() but returns all matching nodes, + * rather than just the first. This is particularly useful for getting all instances + * of a specific IPIN/OPIN at a specific grid tile (x,y) location. + **********************************************************************/ +std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, + const int& x, + const int& y, + const t_rr_type& rr_type, + const int& ptc) { + std::vector indices; + + // NYI + // unused parameters + (void)(rr_graph); + (void)(x); + (void)(y); + (void)(rr_type); + (void)(ptc); + #if 0 + if (rr_type == IPIN || rr_type == OPIN) { + //For pins we need to look at all the sides of the current grid tile + + for (e_side side : SIDES) { + RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, ptc, side); + + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + } else { + //Sides do not effect non-pins so there should only be one per ptc + RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, ptc); + + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + #endif + + return indices; +} + +/********************************************************************* + * Find a list of rr nodes in a routing channel at (x,y) + **********************************************************************/ +std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, + const int& x, + const int& y, + const t_rr_type& rr_type) { + std::vector indices; + + VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); + + // NYI + // unused parameters + (void)(rr_graph); + (void)(x); + (void)(y); + #if 0 + for (short track = 0; track < rr_graph.chan_num_tracks(x, y, rr_type); ++track) { + RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, track); + + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + #endif + + return indices; +} + +/********************************************************************* + * Find a list of rr_nodes that locate at a side of a grid + **********************************************************************/ +std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, + const DeviceGrid& device_grid, + const int& x, + const int& y, + const t_rr_type& rr_type, + const e_side& side) { + std::vector indices; + + VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); + + /* Ensure that (x, y) is a valid location in grids */ + VTR_ASSERT(size_t(x) <= device_grid.width() && size_t(y) <= device_grid.height()); + + /* Ensure we have a valid side */ + VTR_ASSERT(side != NUM_SIDES); + + /* Find all the pins on the side of the grid */ + int width_offset = device_grid[x][y].width_offset; + int height_offset = device_grid[x][y].height_offset; + for (int pin = 0; pin < device_grid[x][y].type->num_pins; ++pin) { + /* Skip those pins have been ignored during rr_graph build-up */ + if (true == device_grid[x][y].type->is_ignored_pin[pin]) { + continue; + } + if (false == device_grid[x][y].type->pinloc[width_offset][height_offset][side][pin]) { + /* Not the pin on this side, we skip */ + continue; + } + + // NYI + // unused parameter + (void)(rr_graph); + #if 0 + /* Try to find the rr node */ + RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, pin, side); + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + #endif + + } + + + return indices; +} + diff --git a/vpr/src/tileable_rr_graph/rr_graph_obj_util.h b/vpr/src/tileable_rr_graph/rr_graph_obj_util.h index 01f753ddcf6..c413386c5dc 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_obj_util.h +++ b/vpr/src/tileable_rr_graph/rr_graph_obj_util.h @@ -7,24 +7,25 @@ #include #include "rr_graph_obj.h" #include "device_grid.h" +#include "rr_graph_view.h" /* Get node-to-node switches in a RRGraph */ -std::vector find_rr_graph_switches(const RRGraph& rr_graph, +std::vector find_rr_graph_switches(const RRGraphView& rr_graph, const RRNodeId& from_node, const RRNodeId& to_node); -std::vector find_rr_graph_nodes(const RRGraph& rr_graph, +std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, const int& x, const int& y, const t_rr_type& rr_type, const int& ptc); -std::vector find_rr_graph_chan_nodes(const RRGraph& rr_graph, +std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, const int& x, const int& y, const t_rr_type& rr_type); -std::vector find_rr_graph_grid_nodes(const RRGraph& rr_graph, +std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const DeviceGrid& device_grid, const int& x, const int& y, diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 2a467d61ff5..59436c84c1d 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -9,6 +9,7 @@ #include "openfpga_side_manager.h" #include "rr_gsb.h" +#include "vtr_geometry.h" /************************************************************************ * Constructors @@ -136,7 +137,7 @@ RRNodeId RRGSB::get_chan_node(const e_side& side, const size_t& track_id) const return chan_node_[side_manager.to_size_t()].get_node(track_id); } -std::vector RRGSB::get_chan_node_in_edges(const RRGraph& rr_graph, +std::vector RRGSB::get_chan_node_in_edges(const RRGraphView& rr_graph, const e_side& side, const size_t& track_id) const { SideManager side_manager(side); @@ -156,9 +157,15 @@ std::vector RRGSB::get_chan_node_in_edges(const RRGraph& rr_graph, */ if (0 == chan_node_in_edges_.size()) { std::vector unsorted_edges; + + // NYI + // unused parameter + (void)(rr_graph); + #if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(get_chan_node(side, track_id))) { unsorted_edges.push_back(edge); } + #endif return unsorted_edges; } @@ -235,7 +242,7 @@ int RRGSB::get_chan_node_index(const e_side& node_side, const RRNodeId& node) co } /* Get the node index in the array, return -1 if not found */ -int RRGSB::get_node_index(const RRGraph& rr_graph, +int RRGSB::get_node_index(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side, const PORTS& node_direction) const { @@ -288,7 +295,7 @@ int RRGSB::get_node_index(const RRGraph& rr_graph, } /* Get the side of a node in this SB */ -void RRGSB::get_node_side_and_index(const RRGraph& rr_graph, +void RRGSB::get_node_side_and_index(const RRGraphView& rr_graph, const RRNodeId& node, const PORTS& node_direction, e_side& node_side, @@ -325,7 +332,7 @@ void RRGSB::get_node_side_and_index(const RRGraph& rr_graph, } /* Check if the node exist in the opposite side of this Switch Block */ -bool RRGSB::is_sb_node_exist_opposite_side(const RRGraph& rr_graph, +bool RRGSB::is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side) const { SideManager side_manager(node_side); @@ -342,7 +349,7 @@ bool RRGSB::is_sb_node_exist_opposite_side(const RRGraph& rr_graph, } /* check if the candidate CB is a mirror of the current one */ -bool RRGSB::is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const { +bool RRGSB::is_cb_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const { /* Check if channel width is the same */ if (get_cb_chan_width(cb_type) != cand.get_cb_chan_width(cb_type)) { return false; @@ -403,7 +410,7 @@ bool RRGSB::is_sb_exist() const { * For DEC_DIRECTION * (xhigh, yhigh) should be same as the GSB side coordinate ***********************************************************************/ -bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph, +bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, const e_side& node_side, const size_t& track_id) const { /* Get the rr_node */ @@ -441,7 +448,11 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph, if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) { VTR_LOG("GSB[%lu][%lu] track node[%lu] at %s:\n", get_x(), get_y(), track_id, SIDE_STRING[node_side]); + + // NYI + #if 0 rr_graph.print_node(track_node); + #endif } VTR_ASSERT(true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)); @@ -454,7 +465,7 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph, * Number of channel/opin/ipin rr_nodes are same * If all above are satisfied, the two switch blocks may be mirrors ! */ -bool RRGSB::is_sb_mirrorable(const RRGraph& rr_graph, const RRGSB& cand) const { +bool RRGSB::is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) const { /* check the numbers of sides */ if (get_num_sides() != cand.get_num_sides()) { return false; @@ -490,7 +501,7 @@ bool RRGSB::is_sb_mirrorable(const RRGraph& rr_graph, const RRGSB& cand) const { } /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ -bool RRGSB::is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side, const RRSegmentId& seg_id) const { +bool RRGSB::is_sb_side_segment_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side, const RRSegmentId& seg_id) const { /* Create a side manager */ SideManager side_manager(side); @@ -539,7 +550,7 @@ bool RRGSB::is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand } /* check if a side of candidate SB is a mirror of the current one */ -bool RRGSB::is_sb_side_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side) const { +bool RRGSB::is_sb_side_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side) const { /* get a list of segments */ std::vector seg_ids = chan_node_[size_t(side)].get_segment_ids(); @@ -553,7 +564,7 @@ bool RRGSB::is_sb_side_mirror(const RRGraph& rr_graph, const RRGSB& cand, const } /* check if the candidate SB is a mirror of the current one */ -bool RRGSB::is_sb_mirror(const RRGraph& rr_graph, const RRGSB& cand) const { +bool RRGSB::is_sb_mirror(const RRGraphView& rr_graph, const RRGSB& cand) const { /* check the numbers of sides */ if (get_num_sides() != cand.get_num_sides()) { return false; @@ -790,7 +801,7 @@ void RRGSB::add_opin_node(const RRNodeId& node, const e_side& node_side) { opin_node_[size_t(node_side)].push_back(node); } -void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph, +void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, const e_side& chan_side, const size_t& track_id) { std::map> from_grid_edge_map; @@ -810,6 +821,13 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph, * For each side, the edge from grid pins will be the 1st part * while the edge from routing tracks will be the 2nd part */ + + // NYI + // unused parameter + (void)(rr_graph); + // unused variable + (void)(chan_node); + #if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) { /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); @@ -839,6 +857,7 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph, edge_counter++; } + #endif /* Store the sorted edge */ for (size_t side = 0; side < get_num_sides(); ++side) { @@ -862,7 +881,7 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph, VTR_ASSERT(edge_counter == chan_node_in_edges_[size_t(chan_side)][track_id].size()); } -void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph) { +void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph) { /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ chan_node_in_edges_.resize(get_num_sides()); @@ -938,7 +957,7 @@ void RRGSB::clear_one_side(const e_side& node_side) { * 2. OPIN or IPIN: should have the same side and index * 3. each drive_rr_switch should be the same */ -bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph, +bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& node_side, const size_t& track_id) const { @@ -968,6 +987,8 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph, VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); + // NYI + #if 0 for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { RREdgeId src_edge = node_in_edges[iedge]; RREdgeId src_cand_edge = cand_node_in_edges[iedge]; @@ -992,6 +1013,7 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph, return false; } } + #endif return true; } @@ -1001,7 +1023,7 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph, * 1. CHANX or CHANY: should have the same side and index * 2. each drive_rr_switch should be the same */ -bool RRGSB::is_cb_node_mirror(const RRGraph& rr_graph, +bool RRGSB::is_cb_node_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const t_rr_type& cb_type, const e_side& node_side, @@ -1010,6 +1032,14 @@ bool RRGSB::is_cb_node_mirror(const RRGraph& rr_graph, RRNodeId node = this->get_ipin_node(node_side, node_id); RRNodeId cand_node = cand.get_ipin_node(node_side, node_id); + // NYI + // unused parameter + (void)(rr_graph); + (void)(cb_type); + // unused variables + (void)(node); + (void)(cand_node); + #if 0 if (rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size()) { return false; } @@ -1064,11 +1094,12 @@ bool RRGSB::is_cb_node_mirror(const RRGraph& rr_graph, return false; } } + #endif return true; } -size_t RRGSB::get_track_id_first_short_connection(const RRGraph& rr_graph, const e_side& node_side) const { +size_t RRGSB::get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const { VTR_ASSERT(validate_side(node_side)); /* Walk through chan_nodes and find the first short connection */ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index e533007d57a..a2106325c62 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -8,6 +8,7 @@ #include "vtr_geometry.h" #include "rr_chan.h" +#include "rr_graph_view.h" /******************************************************************** * Object Generic Switch Block @@ -83,7 +84,7 @@ class RRGSB { RRNodeId get_chan_node(const e_side& side, const size_t& track_id) const; /* get all the sorted incoming edges for a rr_node at a given side and track_id */ - std::vector get_chan_node_in_edges(const RRGraph& rr_graph, + std::vector get_chan_node_in_edges(const RRGraphView& rr_graph, const e_side& side, const size_t& track_id) const; @@ -107,16 +108,16 @@ class RRGSB { int get_chan_node_index(const e_side& node_side, const RRNodeId& node) const; /* Get the node index in the array, return -1 if not found */ - int get_node_index(const RRGraph& rr_graph, const RRNodeId& node, const e_side& node_side, const PORTS& node_direction) const; + int get_node_index(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side, const PORTS& node_direction) const; /* Given a rr_node, try to find its side and index in the Switch block */ - void get_node_side_and_index(const RRGraph& rr_graph, const RRNodeId& node, const PORTS& node_direction, e_side& node_side, int& node_index) const; + void get_node_side_and_index(const RRGraphView& rr_graph, const RRNodeId& node, const PORTS& node_direction, e_side& node_side, int& node_index) const; /* Check if the node exist in the opposite side of this Switch Block */ - bool is_sb_node_exist_opposite_side(const RRGraph& rr_graph, const RRNodeId& node, const e_side& node_side) const; + bool is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side) const; public: /* Accessors: to identify mirrors */ /* check if the candidate SB is a mirror of the current one */ - bool is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const; + bool is_cb_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const; /* check if the connect block exists in the GSB */ bool is_cb_exist(const t_rr_type& cb_type) const; @@ -125,15 +126,15 @@ class RRGSB { bool is_sb_exist() const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */ - bool is_sb_node_passing_wire(const RRGraph& rr_graph, const e_side& node_side, const size_t& track_id) const; + bool is_sb_node_passing_wire(const RRGraphView& rr_graph, const e_side& node_side, const size_t& track_id) const; /* check if the candidate SB satisfy the basic requirements * on being a mirror of the current one */ - bool is_sb_mirrorable(const RRGraph& rr_graph, const RRGSB& cand) const; + bool is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ - bool is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand, + bool is_sb_side_segment_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side, const RRSegmentId& seg_id) const; /* check if a side of candidate SB is a mirror of the current one @@ -147,7 +148,7 @@ class RRGSB { * 5. check if pin class id and pin id are same * If all above are satisfied, the side of the two switch blocks are mirrors! */ - bool is_sb_side_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side) const; + bool is_sb_side_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side) const; /* check if the candidate SB is a mirror of the current one * Idenify mirror Switch blocks @@ -161,7 +162,7 @@ class RRGSB { * 5. check if pin class id and pin id are same * If all above are satisfied, the two switch blocks are mirrors! */ - bool is_sb_mirror(const RRGraph& rr_graph, const RRGSB& cand) const; + bool is_sb_mirror(const RRGraphView& rr_graph, const RRGSB& cand) const; public: /* Cooridinator conversion and output */ size_t get_x() const; /* get the x coordinate of this switch block */ @@ -204,7 +205,7 @@ class RRGSB { const e_side& node_side); /* Sort all the incoming edges for routing channel rr_node */ - void sort_chan_node_in_edges(const RRGraph& rr_graph); + void sort_chan_node_in_edges(const RRGraphView& rr_graph); public: /* Mutators: cleaners */ void clear(); @@ -223,23 +224,23 @@ class RRGSB { private: /* Private Mutators: edge sorting */ /* Sort all the incoming edges for one channel rr_node */ - void sort_chan_node_in_edges(const RRGraph& rr_graph, + void sort_chan_node_in_edges(const RRGraphView& rr_graph, const e_side& chan_side, const size_t& track_id); private: /* internal functions */ - bool is_sb_node_mirror(const RRGraph& rr_graph, + bool is_sb_node_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& node_side, const size_t& track_id) const; - bool is_cb_node_mirror(const RRGraph& rr_graph, + bool is_cb_node_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const t_rr_type& cb_type, const e_side& node_side, const size_t& node_id) const; - size_t get_track_id_first_short_connection(const RRGraph& rr_graph, const e_side& node_side) const; + size_t get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const; private: /* internal validators */ bool validate_num_sides() const; diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 1aa8766a73c..c4814f5b78e 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -233,9 +233,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ ***********************************************************************/ /* Create edges for a tileable rr_graph */ -// Link error: undefined reference to `build_rr_graph_edges` -#if 0 build_rr_graph_edges(device_ctx.rr_graph, + device_ctx.rr_graph_builder, rr_node_driver_switches, grids, device_chan_width, @@ -243,7 +242,6 @@ void build_tileable_unidir_rr_graph(const std::vector& typ Fc_in, Fc_out, sb_type, Fs, sb_subtype, subFs, wire_opposite_side); -#endif /************************************************************************ * Build direction connection lists @@ -261,13 +259,11 @@ void build_tileable_unidir_rr_graph(const std::vector& typ clb2clb_directs.push_back(clb_to_clb_directs[idirect]); } -// Link error: undefined reference to `build_rr_graph_direct_connections` -#if 0 - build_rr_graph_direct_connections(device_ctx.rr_graph, grids, delayless_rr_switch, + build_rr_graph_direct_connections(device_ctx.rr_graph, device_ctx.rr_graph_builder, device_ctx.grid, delayless_rr_switch, arch_directs, clb2clb_directs); -#endif //NYI +// We may not need to rebuild it again #if 0 /* First time to build edges so that we can remap the architecture switch to rr_switch * This is a must-do before function alloc_and_load_rr_switch_inf() diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 3a2ea544605..f46e1fc48da 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -19,7 +19,8 @@ * Build the edges for all the SOURCE and SINKs nodes: * 1. create edges between SOURCE and OPINs ***********************************************************************/ -void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, +void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids) { for (const RRNodeId& node : rr_graph.nodes()) { @@ -34,13 +35,17 @@ void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, rr_graph.node_pin_num(node)); /* Create edges between SOURCE and OPINs */ - const RRNodeId& src_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, + const RRNodeId& src_node = rr_graph_builder.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, ylow - grids[xlow][ylow].height_offset, SOURCE, src_node_class_num); - VTR_ASSERT(true == rr_graph.valid_node_id(src_node)); + VTR_ASSERT(true == rr_graph.validate_node(src_node)); + // NYI + (void)(rr_node_driver_switches); + #if 0 /* add edges to the src_node */ - rr_graph.create_edge(src_node, node, rr_node_driver_switches[node]); + rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node]); + #endif } } @@ -48,7 +53,8 @@ void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, * Build the edges for all the SINKs nodes: * 1. create edges between IPINs and SINKs ***********************************************************************/ -void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, +void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids) { for (const RRNodeId& node : rr_graph.nodes()) { @@ -62,13 +68,23 @@ void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, short sink_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], rr_graph.node_pin_num(node)); /* 1. create edges between IPINs and SINKs */ + // NYI + (void)(sink_node_class_num); + #if 0 const RRNodeId& sink_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, ylow - grids[xlow][ylow].height_offset, SINK, sink_node_class_num); VTR_ASSERT(true == rr_graph.valid_node_id(sink_node)); + #endif + // NYI + (void)(rr_node_driver_switches); + (void)(rr_graph_builder); + #if 0 /* add edges to connect the IPIN node to SINK nodes */ - rr_graph.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); + rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); + #endif + } } @@ -82,7 +98,8 @@ void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) * 3. create edges between OPINs and IPINs (direct-connections) ***********************************************************************/ -void build_rr_graph_edges(RRGraph& rr_graph, +void build_rr_graph_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, const vtr::Point& device_chan_width, @@ -95,8 +112,8 @@ void build_rr_graph_edges(RRGraph& rr_graph, const int& subFs, const bool& wire_opposite_side) { /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ - build_rr_graph_edges_for_source_nodes(rr_graph, rr_node_driver_switches, grids); - build_rr_graph_edges_for_sink_nodes(rr_graph, rr_node_driver_switches, grids); + build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids); + build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids); vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); @@ -126,7 +143,7 @@ void build_rr_graph_edges(RRGraph& rr_graph, segment_inf); /* Build edges for a GSB */ - build_edges_for_one_tileable_rr_gsb(rr_graph, rr_gsb, + build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, track2ipin_map, opin2track_map, sb_conn, rr_node_driver_switches); /* Finish this GSB, go to the next*/ @@ -137,7 +154,8 @@ void build_rr_graph_edges(RRGraph& rr_graph, /************************************************************************ * Build direct edges for Grids * ***********************************************************************/ -void build_rr_graph_direct_connections(RRGraph& rr_graph, +void build_rr_graph_direct_connections(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const RRSwitchId& delayless_switch, const std::vector& directs, @@ -155,6 +173,7 @@ void build_rr_graph_direct_connections(RRGraph& rr_graph, } vtr::Point from_grid_coordinate(ix, iy); build_direct_connections_for_one_gsb(rr_graph, + rr_graph_builder, grids, from_grid_coordinate, delayless_switch, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 0d5c31af691..cb43d80f8fb 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -20,7 +20,8 @@ * Function declaration *******************************************************************/ -void build_rr_graph_edges(RRGraphView& rr_graph, +void build_rr_graph_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, const vtr::Point& device_chan_width, @@ -33,17 +34,20 @@ void build_rr_graph_edges(RRGraphView& rr_graph, const int& subFs, const bool& wire_opposite_side); -void build_rr_graph_direct_connections(RRGraphView& rr_graph, +void build_rr_graph_direct_connections(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const RRSwitchId& delayless_switch, const std::vector& directs, const std::vector& clb_to_clb_directs); -void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph, +void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids); -void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph, +void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 4d23c3b723c..e8c019724da 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -19,6 +19,9 @@ #include "rr_graph_builder_utils.h" #include "tileable_chan_details_builder.h" #include "tileable_rr_graph_gsb.h" +#include "rr_graph_view.h" +#include "rr_graph_builder.h" +#include "vtr_geometry.h" /************************************************************************ * Internal data structures @@ -45,7 +48,7 @@ enum e_track_status { * Check if a track ends at this GSB or not * (xhigh, yhigh) should be same as the GSB side coordinate ***********************************************************************/ -static enum e_track_status determine_track_status_of_gsb(const RRGraph& rr_graph, +static enum e_track_status determine_track_status_of_gsb(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const enum e_side& gsb_side, const size_t& track_id) { @@ -94,7 +97,7 @@ static enum e_track_status determine_track_status_of_gsb(const RRGraph& rr_graph * We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track * Use the offset to check if the tracks should engage in this GSB connection ***********************************************************************/ -static bool is_gsb_in_track_cb_population(const RRGraph& rr_graph, +static bool is_gsb_in_track_cb_population(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const e_side& gsb_side, const int& track_id, @@ -136,7 +139,7 @@ static bool is_gsb_in_track_cb_population(const RRGraph& rr_graph, * We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track * Use the offset to check if the tracks should engage in this GSB connection ***********************************************************************/ -static bool is_gsb_in_track_sb_population(const RRGraph& rr_graph, +static bool is_gsb_in_track_sb_population(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const e_side& gsb_side, const int& track_id, @@ -307,7 +310,7 @@ static std::vector get_switch_block_to_track_id(const e_switch_block_typ * For each side of from_tracks, we call a routine to get the list of to_tracks * Then, we fill the track2track_map ***********************************************************************/ -static void build_gsb_one_group_track_to_track_map(const RRGraph& rr_graph, +static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const e_switch_block_type& sb_type, const int& Fs, @@ -363,7 +366,7 @@ static void build_gsb_one_group_track_to_track_map(const RRGraph& rr_graph, // from_tracks[side].size(), inode, to_track_id, to_track_ids[to_track_id], // to_track_index, to_tracks[to_side_index].size()); const RRNodeId& to_track_node = rr_gsb.get_chan_node(to_side, to_track_index); - VTR_ASSERT(true == rr_graph.valid_node_id(to_track_node)); + VTR_ASSERT(true == rr_graph.validate_node(to_track_node)); /* from_track should be IN_PORT */ VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index)); @@ -429,7 +432,7 @@ static void build_gsb_one_group_track_to_track_map(const RRGraph& rr_graph, * b. tracks that will bypass at the BOTTOM side * 5. Apply switch block patterns to Group 2 (SUBSET, UNIVERSAL, WILTON) ***********************************************************************/ -t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph, +t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const e_switch_block_type& sb_type, const int& Fs, @@ -527,7 +530,7 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph, /* Build a RRChan Object with the given channel type and coorindators */ static RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordinate, const t_rr_type& chan_type, - const RRGraph& rr_graph, + const RRGraphView& rr_graph, const ChanNodeDetails& chan_details) { std::vector chan_rr_nodes; @@ -607,7 +610,7 @@ static RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordina * as well as properly fill the ipin_grid_side information ***********************************************************************/ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, - const RRGraph& rr_graph, + const RRGraphView& rr_graph, const vtr::Point& device_chan_width, const std::vector& segment_inf, const vtr::Point& gsb_coordinate) { @@ -908,12 +911,22 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) * 3. create edges between OPINs and IPINs (direct-connections) ***********************************************************************/ -void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, +void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRGSB& rr_gsb, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, const vtr::vector& rr_node_driver_switches) { + + // NYI + // unused parameters + (void) (rr_graph_builder); + (void) (rr_gsb); + (void) (track2ipin_map); + (void) (opin2track_map); + (void) (track2track_map); + (void) (rr_node_driver_switches); + #if 0 /* Walk through each sides */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager side_manager(side); @@ -926,7 +939,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ /* add edges to the opin_node */ for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) { - rr_graph.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]); + rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]); } } @@ -940,7 +953,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { - rr_graph.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]); + rr_graph_builder.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]); } } } @@ -953,6 +966,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, } } } + #endif } /************************************************************************ @@ -966,7 +980,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, * 3. Scale the Fc of each pin to the actual number of routing tracks * actual_Fc = (int) Fc * num_tracks / chan_width ***********************************************************************/ -static void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph, +static void build_gsb_one_ipin_track2pin_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const enum e_side& ipin_side, const size_t& ipin_node_id, @@ -1059,7 +1073,7 @@ static void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph, * 3. Scale the Fc of each pin to the actual number of routing tracks * actual_Fc = (int) Fc * num_tracks / chan_width ***********************************************************************/ -static void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph, +static void build_gsb_one_opin_pin2track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const enum e_side& opin_side, const size_t& opin_node_id, @@ -1158,7 +1172,7 @@ static void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph, * Then, we assign IPINs to tracks evenly while satisfying the actual_Fc * 2. Convert the ipin_to_track_map to track_to_ipin_map ***********************************************************************/ -t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph, +t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, const std::vector& segment_inf, @@ -1248,7 +1262,7 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph, * 3. Scale the Fc of each pin to the actual number of routing tracks * actual_Fc = (int) Fc * num_tracks / chan_width ***********************************************************************/ -t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph, +t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, const std::vector& segment_inf, @@ -1320,7 +1334,8 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph, /************************************************************************ * Add all direct clb-pin-to-clb-pin edges to given opin ***********************************************************************/ -void build_direct_connections_for_one_gsb(RRGraph& rr_graph, +void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const vtr::Point& from_grid_coordinate, const RRSwitchId& delayless_switch, @@ -1402,12 +1417,23 @@ void build_direct_connections_for_one_gsb(RRGraph& rr_graph, std::vector ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin); VTR_ASSERT(1 == ipin_grid_side.size()); + // NYI + // unused parameters + (void)(rr_graph); + (void)(rr_graph_builder); + // unused variables + (void)(from_grid_width_ofs); + (void)(from_grid_height_ofs); + (void)(to_grid_width_ofs); + (void)(to_grid_height_ofs); + #if 0 const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs, from_grid_coordinate.y() - from_grid_height_ofs, OPIN, opin, opin_grid_side[0]); const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs, to_grid_coordinate.y() - to_grid_height_ofs, IPIN, ipin, ipin_grid_side[0]); + #endif /* VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", from_grid_coordinate.x() - from_grid_width_ofs, @@ -1419,8 +1445,15 @@ void build_direct_connections_for_one_gsb(RRGraph& rr_graph, */ /* add edges to the opin_node */ - rr_graph.create_edge(opin_node_id, ipin_node_id, + + // NYI + // unused parameters + (void)(delayless_switch); + #if 0 + rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch); + #endif + } } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index fbe3a90f89a..992a446706a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -14,6 +14,8 @@ #include "rr_gsb.h" #include "rr_graph_obj.h" #include "rr_graph.h" +#include "rr_graph_view.h" +#include "rr_graph_builder.h" /******************************************************************** * Function declaration @@ -29,7 +31,7 @@ typedef std::vector>> t_pin2track_map; /************************************************************************ * Functions ***********************************************************************/ -t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph, +t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const e_switch_block_type& sb_type, const int& Fs, @@ -39,31 +41,32 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph, const std::vector& segment_inf); RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, - const RRGraph& rr_graph, + const RRGraphView& rr_graph, const vtr::Point& device_chan_width, const std::vector& segment_inf, const vtr::Point& gsb_coordinate); -void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, +void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRGSB& rr_gsb, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, const vtr::vector& rr_node_driver_switches); -t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph, +t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, const std::vector& segment_inf, const std::vector>& Fc_in); -t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph, +t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, const std::vector& segment_inf, const std::vector>& Fc_out); -void build_direct_connections_for_one_gsb(RRGraph& rr_graph, +void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const vtr::Point& from_grid_coordinate, const RRSwitchId& delayless_switch, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 20727607473..a1a6fc1ffd5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -1,5 +1,5 @@ /************************************************************************ - * This file contains functions that are used to allocate nodes + * This file contains functions that are used to allocate nodes * for the tileable routing resource graph builder ***********************************************************************/ /* Headers from vtrutil library */ @@ -24,58 +24,60 @@ /************************************************************************ * Find the number output pins by considering all the grid ***********************************************************************/ -static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, - const t_rr_type& node_type) { - size_t num_grid_rr_nodes = 0; - - for (size_t ix = 0; ix < grids.width(); ++ix) { - for (size_t iy = 0; iy < grids.height(); ++iy) { - /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { - continue; - } - - /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset)) { - continue; - } - - enum e_side io_side = NUM_SIDES; - - /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids[ix][iy].type)) { - vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); - vtr::Point grid_coordinate(ix, iy); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); - } - - switch (node_type) { - case OPIN: - /* get the number of OPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); - break; - case IPIN: - /* get the number of IPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); - break; - case SOURCE: - /* SOURCE: number of classes whose type is DRIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER); - break; - case SINK: - /* SINK: number of classes whose type is RECEIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER); - break; - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid routing resource node!\n"); - exit(1); - } - } +static +size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, + const t_rr_type& node_type) { + size_t num_grid_rr_nodes = 0; + + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ( (0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset) ) { + continue; + } + + enum e_side io_side = NUM_SIDES; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids[ix][iy].type)) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + vtr::Point grid_coordinate(ix, iy); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + } + + switch (node_type) { + case OPIN: + /* get the number of OPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); + break; + case IPIN: + /* get the number of IPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); + break; + case SOURCE: + /* SOURCE: number of classes whose type is DRIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER); + break; + case SINK: + /* SINK: number of classes whose type is RECEIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER); + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid routing resource node!\n"); + exit(1); + } } + } - return num_grid_rr_nodes; + return num_grid_rr_nodes; } /************************************************************************ @@ -85,10 +87,10 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * * As such, the range of CHANX coordinate starts from x = 1, y = 0 * which is the grid (I/O) at the left bottom of the fabric - * + * * As such, the range of CHANX coordinate ends to x = width - 2, y = height - 2 * which is the grid at the top right of the core fabric - * Note that the I/O ring is + * Note that the I/O ring is * * TOP SIDE OF FPGA * @@ -106,16 +108,16 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * | Grid | | Grid | ... | Grid | * | [1][0] | | [2][0] | | [width-2][height-2] | * +-------------+ +-------------+ +---------------------+ - * + * * ... ... ... - * + * * +-------------+ +-------------+ +--------------+ * | X-Channel | | X-Channel | ... | X-Channel | * | [1][1] | | [2][1] | | [width-2][1] | * +-------------+ +-------------+ +--------------+ * * LEFT +-------------+ +-------------+ +--------------+ RIGHT - * SIDE | Grid | | Grid | ... | Grid | SIDE + * SIDE | Grid | | Grid | ... | Grid | SIDE * GRID | [1][1] | | [2][1] | | [width-2][1] | GRID * +-------------+ +-------------+ +--------------+ * @@ -131,9 +133,9 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * * BOTTOM SIDE OF FPGA * - * The figure above describe how the X-direction routing channels are - * organized in a homogeneous FPGA fabric - * Note that we talk about general-purpose uni-directional routing architecture here + * The figure above describe how the X-direction routing channels are + * organized in a homogeneous FPGA fabric + * Note that we talk about general-purpose uni-directional routing architecture here * It means that a routing track may span across multiple grids * However, the hard limits are as follows * All the routing tracks will start at the most LEFT routing channel @@ -143,7 +145,7 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * in the context of heterogeneous FPGAs * We may have a grid which span multiple column and rows, as exemplified in the figure below * In such case, - * all the routing tracks [x-1][y] at the left side of the grid [x][y] are forced to end + * all the routing tracks [x-1][y] at the left side of the grid [x][y] are forced to end * all the routing tracks [x+2][y] at the right side of the grid [x][y] are forced to start * And there are no routing tracks inside the grid[x][y] * It means that X-channel [x][y] & [x+1][y] will no exist @@ -171,51 +173,52 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * * ***********************************************************************/ -static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - size_t num_chanx_rr_nodes = 0; - - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { - vtr::Point chanx_coord(ix, iy); - - /* Bypass if the routing channel does not exist when through channels are not allowed */ - if ((false == through_channel) - && (false == is_chanx_exist(grids, chanx_coord))) { - continue; - } - - bool force_start = false; - bool force_end = false; - - /* All the tracks have to start when +static +size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + size_t num_chanx_rr_nodes = 0; + + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ( (false == through_channel) + && (false == is_chanx_exist(grids, chanx_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_start = true; - } + if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_end = true; - } - - /* Evaluate if the routing channel locates in the middle of a grid */ - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); - /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ - num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); - /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ - num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(Direction::DEC); - } + if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_end = true; + } + + /* Evaluate if the routing channel locates in the middle of a grid */ + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(Direction::DEC); } + } - return num_chanx_rr_nodes; + return num_chanx_rr_nodes; } /************************************************************************ @@ -223,74 +226,78 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, * The technical rationale is very similar to the X-direction routing channel * Refer to the detailed explanation there ***********************************************************************/ -static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - size_t num_chany_rr_nodes = 0; +static +size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + size_t num_chany_rr_nodes = 0; - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - vtr::Point chany_coord(ix, iy); + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Point chany_coord(ix, iy); - /* Bypass if the routing channel does not exist when through channel are not allowed */ - if ((false == through_channel) - && (false == is_chany_exist(grids, chany_coord))) { - continue; - } + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ( (false == through_channel) + && (false == is_chany_exist(grids, chany_coord))) { + continue; + } - bool force_start = false; - bool force_end = false; - /* All the tracks have to start when + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_start = true; - } + if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_end = true; - } - - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); - /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ - num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); - /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ - num_chany_rr_nodes += chany_details.get_num_ending_tracks(Direction::DEC); - } + if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_ending_tracks(Direction::DEC); } + } - return num_chany_rr_nodes; + return num_chany_rr_nodes; } /************************************************************************ * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ -static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, - const vtr::Point& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ - std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); - - /** +static +std::vector estimate_num_rr_nodes(const DeviceGrid& grids, + const vtr::Point& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + + /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ + std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); + + /** * 1 Find number of rr nodes related to grids */ - num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); - num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); - num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); - num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); + num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); + num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); + num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); + num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); - /** + /** * 2. Assign the segments for each routing channel, * To be specific, for each routing track, we assign a routing segment. - * The assignment is subject to users' specifications, such as + * The assignment is subject to users' specifications, such as * a. length of each type of segment * b. frequency of each type of segment. * c. routing channel width @@ -298,695 +305,713 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, * SPECIAL for fringes: * All segments will start and ends with no exception * - * IMPORTANT: we should be aware that channel width maybe different + * IMPORTANT: we should be aware that channel width maybe different * in X-direction and Y-direction channels!!! - * So we will load segment details for different channels + * So we will load segment details for different channels */ - num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, - chan_width.x(), - segment_infs, - through_channel); - num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, - chan_width.y(), - segment_infs, - through_channel); - - return num_rr_nodes_per_type; + num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, + chan_width.x(), + segment_infs, + through_channel); + num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, + chan_width.y(), + segment_infs, + through_channel); + + return num_rr_nodes_per_type; } /************************************************************************ - * Allocate rr_nodes to a rr_graph object + * Allocate rr_nodes to a rr_graph object * This function just allocate the memory and ensure its efficiency * It will NOT fill detailed information for each node!!! * * Note: ensure that there are NO nodes in the rr_graph ***********************************************************************/ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, const vtr::Point& chan_width, const std::vector& segment_infs, const bool& through_channel) { - VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); + VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); - std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, - chan_width, - segment_infs, - through_channel); + std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + chan_width, + segment_infs, + through_channel); - /* Reserve the number of node to be memory efficient */ - size_t num_nodes = 0; - for (const size_t& num_node_per_type : num_rr_nodes_per_type) { - num_nodes += num_node_per_type; - } + /* Reserve the number of node to be memory efficient */ + size_t num_nodes = 0; + for (const size_t& num_node_per_type : num_rr_nodes_per_type) { + num_nodes += num_node_per_type; + } - rr_graph_builder.reserve_nodes(num_nodes); + rr_graph_builder.reserve_nodes(num_nodes); - rr_node_driver_switches.reserve(num_nodes); + rr_node_driver_switches.reserve(num_nodes); } /************************************************************************ - * Configure OPIN rr_nodes for this grid - * coordinates: xlow, ylow, xhigh, yhigh, + * Configure OPIN rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, ptc_num (pin_num), * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Walk through the width height of each grid, +static +void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Walk through the width height of each grid, * get pins and configure the rr_nodes */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { - /* Walk through sides */ - for (e_side side : SIDES) { - SideManager side_manager(side); - /* skip unwanted sides */ - if ((true == is_io_type(cur_grid.type)) - && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { - continue; - } - /* Find OPINs */ - /* Configure pins by pins */ - std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), - width, height); - for (const int& pin_num : opin_list) { - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, OPIN, pin_num, side); - - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, - grid_coordinate.y() + height, - grid_coordinate.x() + width, - grid_coordinate.y() + height); - rr_graph_builder.add_node_side(node, side_manager.get_side()); - rr_graph_builder.set_node_pin_num(node, pin_num); - - rr_graph_builder.set_node_capacity(node, 1); - - /* cost index is a FIXED value for OPIN */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); - - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); - - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - - } /* End of loading OPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + /* Walk through sides */ + for (e_side side : SIDES) { + SideManager side_manager(side); + /* skip unwanted sides */ + if ( (true == is_io_type(cur_grid.type)) + && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side) ) { + continue; + } + /* Find OPINs */ + /* Configure pins by pins */ + std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), + width, height); + for (const int& pin_num : opin_list) { + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, OPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of loading OPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ + } /************************************************************************ - * Configure IPIN rr_nodes for this grid - * coordinates: xlow, ylow, xhigh, yhigh, + * Configure IPIN rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, ptc_num (pin_num), * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& wire_to_ipin_switch) { - SideManager io_side_manager(io_side); - - /* Walk through the width and height of each grid, +static +void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& wire_to_ipin_switch) { + SideManager io_side_manager(io_side); + + /* Walk through the width and height of each grid, * get pins and configure the rr_nodes */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { - /* Walk through sides */ - for (e_side side : SIDES) { - SideManager side_manager(side); - /* skip unwanted sides */ - if ((true == is_io_type(cur_grid.type)) - && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { - continue; - } - - /* Find IPINs */ - /* Configure pins by pins */ - std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); - for (const int& pin_num : ipin_list) { - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, IPIN, pin_num, side); - - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, - grid_coordinate.y() + height, - grid_coordinate.x() + width, - grid_coordinate.y() + height); - rr_graph_builder.add_node_side(node, side_manager.get_side()); - rr_graph_builder.set_node_pin_num(node, pin_num); - - rr_graph_builder.set_node_capacity(node, 1); - - /* cost index is a FIXED value for OPIN */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); - - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(wire_to_ipin_switch); - - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - - } /* End of loading IPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + /* Walk through sides */ + for (e_side side : SIDES) { + SideManager side_manager(side); + /* skip unwanted sides */ + if ( (true == is_io_type(cur_grid.type)) + && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side) ) { + continue; + } + + /* Find IPINs */ + /* Configure pins by pins */ + std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); + for (const int& pin_num : ipin_list) { + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, IPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(wire_to_ipin_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of loading IPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ - * Configure SOURCE rr_nodes for this grid - * coordinates: xlow, ylow, xhigh, yhigh, + * Configure SOURCE rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, ptc_num (pin_num), * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Set a SOURCE rr_node for each DRIVER class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Set a SINK rr_node for the OPIN */ - if (DRIVER != cur_grid.type->class_inf[iclass].type) { - continue; - } - - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); - - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), - grid_coordinate.y(), - grid_coordinate.x() + cur_grid.type->width - 1, - grid_coordinate.y() + cur_grid.type->height - 1); - rr_graph_builder.set_node_class_num(node, iclass); - - rr_graph_builder.set_node_capacity(node, 1); - - /* The capacity should be the number of pins in this class*/ - rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); - - /* cost index is a FIXED value for SOURCE */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); - - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); - - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - - } /* End of class enumeration */ +static +void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Set a SOURCE rr_node for each DRIVER class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (DRIVER != cur_grid.type->class_inf[iclass].type) { + continue; + } + + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); + + rr_graph_builder.set_node_capacity(node, 1); + + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + + /* cost index is a FIXED value for SOURCE */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of class enumeration */ } /************************************************************************ - * Configure SINK rr_nodes for this grid - * coordinates: xlow, ylow, xhigh, yhigh, + * Configure SINK rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, ptc_num (pin_num), * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Set a SINK rr_node for each RECEIVER class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Set a SINK rr_node for the OPIN */ - if (RECEIVER != cur_grid.type->class_inf[iclass].type) { - continue; - } +static +void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Set a SINK rr_node for each RECEIVER class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (RECEIVER != cur_grid.type->class_inf[iclass].type) { + continue; + } - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), - grid_coordinate.y(), - grid_coordinate.x() + cur_grid.type->width - 1, - grid_coordinate.y() + cur_grid.type->height - 1); - rr_graph_builder.set_node_class_num(node, iclass); + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); - rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_capacity(node, 1); - /* The capacity should be the number of pins in this class*/ - rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); - /* cost index is a FIXED value for SINK */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); + /* cost index is a FIXED value for SINK */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - } /* End of class enumeration */ + } /* End of class enumeration */ } /************************************************************************ * Create all the rr_nodes for grids ***********************************************************************/ -static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids, - const RRSwitchId& wire_to_ipin_switch, - const RRSwitchId& delayless_switch) { - for (size_t iy = 0; iy < grids.height(); ++iy) { - for (size_t ix = 0; ix < grids.width(); ++ix) { - /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { - continue; - } - - /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ - if ((0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset)) { - continue; - } - - vtr::Point grid_coordinate(ix, iy); - enum e_side io_side = NUM_SIDES; - - /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids[ix][iy].type)) { - vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); - } - - /* Configure source rr_nodes for this grid */ - load_one_grid_source_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure sink rr_nodes for this grid */ - load_one_grid_sink_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure opin rr_nodes for this grid */ - load_one_grid_opin_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure ipin rr_nodes for this grid */ - load_one_grid_ipin_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - wire_to_ipin_switch); - } +static +void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch) { + + for (size_t iy = 0; iy < grids.height(); ++iy) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + + /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ + if ( (0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset) ) { + continue; + } + + vtr::Point grid_coordinate(ix, iy); + enum e_side io_side = NUM_SIDES; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids[ix][iy].type)) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + } + + /* Configure source rr_nodes for this grid */ + load_one_grid_source_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure sink rr_nodes for this grid */ + load_one_grid_sink_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure opin rr_nodes for this grid */ + load_one_grid_opin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure ipin rr_nodes for this grid */ + load_one_grid_ipin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + wire_to_ipin_switch); + } + } } /************************************************************************ * Initialize the basic information of routing track rr_nodes - * coordinates: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction ***********************************************************************/ -static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, - ChanNodeDetails& chan_details, - const std::vector& segment_infs, - const int& cost_index_offset) { - /* Check each node_id(potential ptc_num) in the channel : +static +void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + ChanNodeDetails& chan_details, + const std::vector& segment_infs, + const int& cost_index_offset) { + /* Check each node_id(potential ptc_num) in the channel : * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num * If this is a ending point, we set xhigh/yhigh and track_ids * For other nodes, we set changes in track_ids */ - for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { - /* For INC direction, a starting point requires a new chan rr_node */ - if (((true == chan_details.is_track_start(itrack)) - && (Direction::INC == chan_details.get_track_direction(itrack))) - /* For DEC direction, an ending point requires a new chan rr_node */ - || ((true == chan_details.is_track_end(itrack)) - && (Direction::DEC == chan_details.get_track_direction(itrack)))) { - /* Create a new chan rr_node */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); - - rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); - rr_graph_builder.set_node_track_num(node, itrack); - rr_node_track_ids[node].push_back(itrack); - - rr_graph_builder.set_node_capacity(node, 1); - - /* assign switch id */ - size_t seg_id = chan_details.get_track_segment_id(itrack); - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); - - /* Update chan_details with node_id */ - chan_details.set_track_node_id(itrack, size_t(node)); - - /* cost index depends on the segment index */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_id)); - /* Finish here, go to next */ - } + for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { + /* For INC direction, a starting point requires a new chan rr_node */ + if ( ( (true == chan_details.is_track_start(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack)) ) + /* For DEC direction, an ending point requires a new chan rr_node */ + || + ( (true == chan_details.is_track_end(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)) ) ) { + + /* Create a new chan rr_node */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); + + rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); + rr_graph_builder.set_node_track_num(node, itrack); + rr_node_track_ids[node].push_back(itrack); + + rr_graph_builder.set_node_capacity(node, 1); + + /* assign switch id */ + size_t seg_id = chan_details.get_track_segment_id(itrack); + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); + + /* Update chan_details with node_id */ + chan_details.set_track_node_id(itrack, size_t(node)); + + /* cost index depends on the segment index */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_id)); + /* Finish here, go to next */ + } - /* For INC direction, an ending point requires an update on xhigh and yhigh */ - if (((true == chan_details.is_track_end(itrack)) - && (Direction::INC == chan_details.get_track_direction(itrack))) - || - /* For DEC direction, an starting point requires an update on xlow and ylow */ - ((true == chan_details.is_track_start(itrack)) - && (Direction::DEC == chan_details.get_track_direction(itrack)))) { - /* Get the node_id */ - const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); - - /* Do a quick check, make sure we do not mistakenly modify other nodes */ - VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); - VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); - - /* set xhigh/yhigh and push changes to track_ids */ - rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), - rr_graph.node_ylow(rr_node_id), - chan_coordinate.x(), - chan_coordinate.y()); - - /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ - if ((rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) - || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id))) { - rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.set_node_track_num(rr_node_id, itrack); - } - /* Finish here, go to next */ - } + /* For INC direction, an ending point requires an update on xhigh and yhigh */ + if ( ( (true == chan_details.is_track_end(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack)) ) + || + /* For DEC direction, an starting point requires an update on xlow and ylow */ + ( (true == chan_details.is_track_start(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)) ) ) { + + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + + /* set xhigh/yhigh and push changes to track_ids */ + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ + if ( (rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) + || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id)) ) { + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.set_node_track_num(rr_node_id, itrack); + } + /* Finish here, go to next */ + } - /* Finish processing starting and ending tracks */ - if ((true == chan_details.is_track_start(itrack)) - || (true == chan_details.is_track_end(itrack))) { - /* Finish here, go to next */ - continue; - } + /* Finish processing starting and ending tracks */ + if ( (true == chan_details.is_track_start(itrack)) + || (true == chan_details.is_track_end(itrack)) ) { + /* Finish here, go to next */ + continue; + } - /* For other nodes, we get the node_id and just update track_ids */ - /* Ensure those nodes are neither starting nor ending points */ - VTR_ASSERT((false == chan_details.is_track_start(itrack)) - && (false == chan_details.is_track_end(itrack))); + /* For other nodes, we get the node_id and just update track_ids */ + /* Ensure those nodes are neither starting nor ending points */ + VTR_ASSERT( (false == chan_details.is_track_start(itrack)) + && (false == chan_details.is_track_end(itrack)) ); - /* Get the node_id */ - const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); - /* Do a quick check, make sure we do not mistakenly modify other nodes */ - VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); - VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); - /* Deposit xhigh and yhigh using the current chan_coordinate + /* Deposit xhigh and yhigh using the current chan_coordinate * We will update when this track ends */ - rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), - rr_graph.node_ylow(rr_node_id), - chan_coordinate.x(), - chan_coordinate.y()); - - /* Update track_ids */ - rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.set_node_track_num(rr_node_id, itrack); - /* Finish here, go to next */ - } -} + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Update track_ids */ + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.set_node_track_num(rr_node_id, itrack); + /* Finish here, go to next */ + } +} /************************************************************************ * Initialize the basic information of X-channel rr_nodes: - * coordinates: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction * grid_info : pb_graph_pin ***********************************************************************/ -static void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - /* For X-direction Channel: CHANX */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ - std::vector track_node_ids; - - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { - vtr::Point chanx_coord(ix, iy); - - /* Bypass if the routing channel does not exist when through channels are not allowed */ - if ((false == through_channel) - && (false == is_chanx_exist(grids, chanx_coord))) { - continue; - } - - bool force_start = false; - bool force_end = false; - - /* All the tracks have to start when +static +void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + + /* For X-direction Channel: CHANX */ + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ( (false == through_channel) + && (false == is_chanx_exist(grids, chanx_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_start = true; - } + if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_end = true; - } - - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, - force_start, force_end, segment_infs); - /* Force node_ids from the previous chanx */ - if (0 < track_node_ids.size()) { - /* Rotate should be done based on a typical case of routing tracks. - * Tracks on the borders are not regularly started and ended, - * which causes the node_rotation malfunction + if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chanx */ + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction */ - ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, - false, false, segment_infs); - chanx_details_tt.set_track_node_ids(track_node_ids); + ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, + false, false, segment_infs); + chanx_details_tt.set_track_node_ids(track_node_ids); - /* TODO: - * Do NOT rotate the tracks when the routing channel + /* TODO: + * Do NOT rotate the tracks when the routing channel * locates inside a multi-height and multi-width grid - * Let the routing channel passing through the grid (if through channel is allowed!) + * Let the routing channel passing through the grid (if through channel is allowed!) * An example: - * + * * +------------------------------ * | | * | Grid | * track0 ----->+-----------------------------+----> track0 * | | */ - if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { - /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ - /* For INC_DIRECTION, we use clockwise rotation + if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { + /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ + /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D * node_id B ----> / ----> node_id A * node_id C ----> / ----> node_id B - * node_id D ----> ----> node_id C + * node_id D ----> ----> node_id C */ - chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); - /* For DEC_DIRECTION, we use clockwise rotation + chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation * node_id A <----- <----- node_id B * node_id B <----- \ <----- node_id C * node_id C <----- \ <----- node_id D - * node_id D <----- <----- node_id A + * node_id D <----- <----- node_id A */ - chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); - } - - track_node_ids = chanx_details_tt.get_track_node_ids(); - chanx_details.set_track_node_ids(track_node_ids); - } - - /* Configure CHANX in this channel */ - load_one_chan_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - chanx_coord, CHANX, - chanx_details, - segment_infs, - CHANX_COST_INDEX_START); - /* Get a copy of node_ids */ - track_node_ids = chanx_details.get_track_node_ids(); - } + chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chanx_details_tt.get_track_node_ids(); + chanx_details.set_track_node_ids(track_node_ids); + } + + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + chanx_coord, CHANX, + chanx_details, + segment_infs, + CHANX_COST_INDEX_START); + /* Get a copy of node_ids */ + track_node_ids = chanx_details.get_track_node_ids(); } + } } /************************************************************************ * Initialize the basic information of Y-channel rr_nodes: - * coordinates: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction ***********************************************************************/ -static void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - /* For Y-direction Channel: CHANY */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ - std::vector track_node_ids; - - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - vtr::Point chany_coord(ix, iy); - - /* Bypass if the routing channel does not exist when through channel are not allowed */ - if ((false == through_channel) - && (false == is_chany_exist(grids, chany_coord))) { - continue; - } - - bool force_start = false; - bool force_end = false; - - /* All the tracks have to start when +static +void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + + /* For Y-direction Channel: CHANY */ + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Point chany_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ( (false == through_channel) + && (false == is_chany_exist(grids, chany_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_start = true; - } + if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_end = true; - } + if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_end = true; + } - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, - force_start, force_end, segment_infs); - /* Force node_ids from the previous chany + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chany * This will not be applied when the routing channel is cut off (force to start) */ - if (0 < track_node_ids.size()) { - /* Rotate should be done based on a typical case of routing tracks. - * Tracks on the borders are not regularly started and ended, - * which causes the node_rotation malfunction + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction */ - ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, - false, false, segment_infs); + ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, + false, false, segment_infs); - chany_details_tt.set_track_node_ids(track_node_ids); + chany_details_tt.set_track_node_ids(track_node_ids); - /* TODO: - * Do NOT rotate the tracks when the routing channel + /* TODO: + * Do NOT rotate the tracks when the routing channel * locates inside a multi-height and multi-width grid - * Let the routing channel passing through the grid (if through channel is allowed!) + * Let the routing channel passing through the grid (if through channel is allowed!) * An example: - * + * * +------------------------------ * | | * | Grid | * track0 ----->+-----------------------------+----> track0 * | | - * we should rotate only once at the bottom side of a grid + * we should rotate only once at the bottom side of a grid */ - if (true == is_chany_exist(grids, chany_coord, through_channel)) { - /* Rotate the chany_details by an offset of 1*/ - /* For INC_DIRECTION, we use clockwise rotation + if (true == is_chany_exist(grids, chany_coord, through_channel)) { + /* Rotate the chany_details by an offset of 1*/ + /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D * node_id B ----> / ----> node_id A * node_id C ----> / ----> node_id B - * node_id D ----> ----> node_id C + * node_id D ----> ----> node_id C */ - chany_details_tt.rotate_track_node_id(1, Direction::INC, true); - /* For DEC_DIRECTION, we use clockwise rotation + chany_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation * node_id A <----- <----- node_id B * node_id B <----- \ <----- node_id C * node_id C <----- \ <----- node_id D - * node_id D <----- <----- node_id A + * node_id D <----- <----- node_id A */ - chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); - } - - track_node_ids = chany_details_tt.get_track_node_ids(); - chany_details.set_track_node_ids(track_node_ids); - } - /* Configure CHANX in this channel */ - load_one_chan_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - chany_coord, CHANY, - chany_details, - segment_infs, - CHANX_COST_INDEX_START + segment_infs.size()); - /* Get a copy of node_ids */ - track_node_ids = chany_details.get_track_node_ids(); + chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); } + + track_node_ids = chany_details_tt.get_track_node_ids(); + chany_details.set_track_node_ids(track_node_ids); + } + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + chany_coord, CHANY, + chany_details, + segment_infs, + CHANX_COST_INDEX_START + segment_infs.size()); + /* Get a copy of node_ids */ + track_node_ids = chany_details.get_track_node_ids(); } + } } /************************************************************************ * Reverse the track_ids of CHANX and CHANY nodes in DEC_DIRECTION * This is required as the track ids are allocated in the sequence * of incrementing x and y - * However, DEC direction routing tracks should have a reversed sequence in - * track ids + * However, DEC direction routing tracks should have a reversed sequence in + * track ids ***********************************************************************/ -static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, - std::map>& rr_node_track_ids) { - // this should call rr_graph_view to do the job - - for (auto& node : rr_graph.nodes()) { - /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ - if ((CHANX != rr_graph.node_type(node)) - && (CHANY != rr_graph.node_type(node))) { - continue; - } - /* Reach here, we must have a node of CHANX or CHANY */ - if (Direction::DEC != rr_graph.node_direction(node)) { - continue; - } - std::reverse(rr_node_track_ids[node].begin(), - rr_node_track_ids[node].end()); +static +void reverse_dec_chan_rr_node_track_ids(const RRGraphBuilder& rr_graph_builder, + std::map>& rr_node_track_ids) { +#if 0 + // this should call rr_graph_builder to do the job + for (const RRNodeId& node : rr_graph_builder.nodes()) { + /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ + if ( (CHANX != rr_graph_builder.node_type(node)) + && (CHANY != rr_graph_builder.node_type(node)) ) { + continue; + } + /* Reach here, we must have a node of CHANX or CHANY */ + if (Direction::DEC != rr_graph_builder.node_direction(node)) { + continue; } + std::reverse(rr_node_track_ids[node].begin(), + rr_node_track_ids[node].end() ); + } +#endif } /************************************************************************ @@ -994,38 +1019,39 @@ static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, ***********************************************************************/ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const vtr::Point& chan_width, + const DeviceGrid& grids, + const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, const bool& through_channel) { - load_grid_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grids, - wire_to_ipin_switch, - delayless_switch); - - load_chanx_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - grids, - chan_width.x(), - segment_infs, - through_channel); - - load_chany_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - grids, - chan_width.y(), - segment_infs, - through_channel); - - reverse_dec_chan_rr_node_track_ids(rr_graph, - rr_node_track_ids); + load_grid_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grids, + wire_to_ipin_switch, + delayless_switch); + + load_chanx_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + chan_width.x(), + segment_infs, + through_channel); + + load_chany_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + chan_width.y(), + segment_infs, + through_channel); + + reverse_dec_chan_rr_node_track_ids(rr_graph_builder, + rr_node_track_ids); + } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index c555c19a178..8317c10169b 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -1,5 +1,6 @@ #ifndef TILEABLE_RR_GRAPH_NODE_BUILDER_H #define TILEABLE_RR_GRAPH_NODE_BUILDER_H + /******************************************************************** * Include header files that are required by function declaration *******************************************************************/ @@ -20,7 +21,7 @@ *******************************************************************/ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, - vtr::vector& driver_switches, + vtr::vector& driver_switches, const DeviceGrid& grids, const vtr::Point& chan_width, const std::vector& segment_infs, @@ -28,14 +29,15 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const vtr::Point& chan_width, + const DeviceGrid& grids, + const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, const bool& through_channel); -#endif + +#endif From 17626dd80e3cea905766b00a7c50ddf7509439ba Mon Sep 17 00:00:00 2001 From: taoli4rs Date: Tue, 2 Aug 2022 18:05:38 -0700 Subject: [PATCH 007/453] Code cleanup: fix warnings and format code by complying to vtr format. --- vpr/src/tileable_rr_graph/chan_node_details.h | 29 +- vpr/src/tileable_rr_graph/openfpga_port.cpp | 417 +++-- vpr/src/tileable_rr_graph/openfpga_port.h | 72 +- .../openfpga_rr_graph_utils.cpp | 25 +- .../openfpga_rr_graph_utils.h | 2 +- .../openfpga_side_manager.cpp | 227 ++- .../tileable_rr_graph/openfpga_side_manager.h | 5 +- vpr/src/tileable_rr_graph/rr_chan.h | 34 +- .../rr_graph_builder_utils.h | 21 +- .../tileable_rr_graph/rr_graph_obj_util.cpp | 30 +- vpr/src/tileable_rr_graph/rr_graph_obj_util.h | 1 - vpr/src/tileable_rr_graph/rr_graph_types.h | 1 - vpr/src/tileable_rr_graph/rr_gsb.cpp | 24 +- vpr/src/tileable_rr_graph/rr_gsb.h | 40 +- .../tileable_chan_details_builder.h | 12 +- .../tileable_rr_graph_builder.cpp | 12 +- .../tileable_rr_graph_builder.h | 14 +- .../tileable_rr_graph_edge_builder.cpp | 30 +- .../tileable_rr_graph_edge_builder.h | 13 +- .../tileable_rr_graph_gsb.cpp | 26 +- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 1 - .../tileable_rr_graph_node_builder.cpp | 1405 ++++++++--------- .../tileable_rr_graph_node_builder.h | 10 +- 23 files changed, 1212 insertions(+), 1239 deletions(-) diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h index 4b50d7b2405..e322b5c6d73 100644 --- a/vpr/src/tileable_rr_graph/chan_node_details.h +++ b/vpr/src/tileable_rr_graph/chan_node_details.h @@ -28,10 +28,10 @@ ***********************************************************************/ class ChanNodeDetails { - public : /* Constructor */ + public: /* Constructor */ ChanNodeDetails(const ChanNodeDetails&); /* Duplication */ - ChanNodeDetails(); /* Initilization */ - public: /* Accessors */ + ChanNodeDetails(); /* Initilization */ + public: /* Accessors */ size_t get_chan_width() const; size_t get_track_node_id(const size_t& track_id) const; std::vector get_track_node_ids() const; @@ -44,11 +44,10 @@ class ChanNodeDetails { std::vector get_seg_group_node_id(const std::vector& seg_group) const; size_t get_num_starting_tracks(const Direction& track_direction) const; size_t get_num_ending_tracks(const Direction& track_direction) const; - public: /* Mutators */ + + public: /* Mutators */ void reserve(const size_t& chan_width); /* Reserve the capacitcy of vectors */ - void add_track(const size_t& track_node_id, const Direction& track_direction, - const size_t& seg_id, const size_t& seg_length, - const size_t& is_start, const size_t& is_end); + void add_track(const size_t& track_node_id, const Direction& track_direction, const size_t& seg_id, const size_t& seg_length, const size_t& is_start, const size_t& is_end); void set_track_node_id(const size_t& track_index, const size_t& track_node_id); void set_track_node_ids(const std::vector& track_node_ids); void set_tracks_start(const Direction& track_direction); @@ -57,16 +56,18 @@ class ChanNodeDetails { const Direction& track_direction, const bool& counter_rotate); /* rotate the track_node_id by an offset */ void clear(); + private: /* validators */ bool validate_chan_width() const; bool validate_track_id(const size_t& track_id) const; - private: /* Internal data */ - std::vector track_node_ids_; /* indices of each track */ + + private: /* Internal data */ + std::vector track_node_ids_; /* indices of each track */ std::vector track_direction_; /* direction of each track */ - std::vector seg_ids_; /* id of segment of each track */ - std::vector seg_length_; /* Length of each segment */ - std::vector track_start_; /* flag to identify if this is the starting point of the track */ - std::vector track_end_; /* flag to identify if this is the ending point of the track */ + std::vector seg_ids_; /* id of segment of each track */ + std::vector seg_length_; /* Length of each segment */ + std::vector track_start_; /* flag to identify if this is the starting point of the track */ + std::vector track_end_; /* flag to identify if this is the ending point of the track */ }; -#endif +#endif diff --git a/vpr/src/tileable_rr_graph/openfpga_port.cpp b/vpr/src/tileable_rr_graph/openfpga_port.cpp index 7cfd03b20f5..3d4d59348f6 100644 --- a/vpr/src/tileable_rr_graph/openfpga_port.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_port.cpp @@ -16,36 +16,36 @@ ***********************************************************************/ /* Default constructor */ BasicPort::BasicPort() { - /* By default we set an invalid port, which size is 0 */ - lsb_ = 1; - msb_ = 0; + /* By default we set an invalid port, which size is 0 */ + lsb_ = 1; + msb_ = 0; - origin_port_width_ = -1; + origin_port_width_ = -1; } /* Quick constructor */ BasicPort::BasicPort(const char* name, const size_t& lsb, const size_t& msb) { - set_name(std::string(name)); - set_width(lsb, msb); - set_origin_port_width(-1); + set_name(std::string(name)); + set_width(lsb, msb); + set_origin_port_width(-1); } BasicPort::BasicPort(const std::string& name, const size_t& lsb, const size_t& msb) { - set_name(name); - set_width(lsb, msb); - set_origin_port_width(-1); + set_name(name); + set_width(lsb, msb); + set_origin_port_width(-1); } BasicPort::BasicPort(const char* name, const size_t& width) { - set_name(std::string(name)); - set_width(width); - set_origin_port_width(-1); + set_name(std::string(name)); + set_width(width); + set_origin_port_width(-1); } BasicPort::BasicPort(const std::string& name, const size_t& width) { - set_name(name); - set_width(width); - set_origin_port_width(-1); + set_name(name); + set_width(width); + set_origin_port_width(-1); } /************************************************************************ @@ -53,62 +53,62 @@ BasicPort::BasicPort(const std::string& name, const size_t& width) { ***********************************************************************/ /* get the port width */ size_t BasicPort::get_width() const { - if (true == is_valid()) { - return msb_ - lsb_ + 1; - } - return 0; /* invalid port has a zero width */ + if (true == is_valid()) { + return msb_ - lsb_ + 1; + } + return 0; /* invalid port has a zero width */ } - + /* get the LSB */ size_t BasicPort::get_msb() const { - return msb_; + return msb_; } /* get the LSB */ size_t BasicPort::get_lsb() const { - return lsb_; + return lsb_; } /* get the name */ std::string BasicPort::get_name() const { - return name_; -} + return name_; +} /* Make a range of the pin indices */ std::vector BasicPort::pins() const { - std::vector pin_indices; + std::vector pin_indices; - /* Return if the port is invalid */ - if (false == is_valid()) { - return pin_indices; /* Return an empty vector */ - } - /* For valid ports, create a vector whose length is the port width */ - pin_indices.resize(get_width()); - /* Fill in an incremental sequence */ - std::iota(pin_indices.begin(), pin_indices.end(), get_lsb()); - /* Ensure the last one is MSB */ - VTR_ASSERT(get_msb() == pin_indices.back()); + /* Return if the port is invalid */ + if (false == is_valid()) { + return pin_indices; /* Return an empty vector */ + } + /* For valid ports, create a vector whose length is the port width */ + pin_indices.resize(get_width()); + /* Fill in an incremental sequence */ + std::iota(pin_indices.begin(), pin_indices.end(), get_lsb()); + /* Ensure the last one is MSB */ + VTR_ASSERT(get_msb() == pin_indices.back()); - return pin_indices; + return pin_indices; } /* Check if a port can be merged with this port: their name should be the same */ bool BasicPort::mergeable(const BasicPort& portA) const { - return (0 == this->get_name().compare(portA.get_name())); -} + return (0 == this->get_name().compare(portA.get_name())); +} /* Check if a port is contained by this port: * this function will check if the (LSB, MSB) of portA * is contained by the (LSB, MSB) of this port */ bool BasicPort::contained(const BasicPort& portA) const { - return ( lsb_ <= portA.get_lsb() && portA.get_msb() <= msb_ ); + return (lsb_ <= portA.get_lsb() && portA.get_msb() <= msb_); } /* Set original port width */ size_t BasicPort::get_origin_port_width() const { - return origin_port_width_; -} + return origin_port_width_; +} /************************************************************************ * Overloaded operators @@ -118,167 +118,166 @@ size_t BasicPort::get_origin_port_width() const { * 2. LSBs are the same * 3. MSBs are the same */ -bool BasicPort::operator== (const BasicPort& portA) const { - if ( (0 == this->get_name().compare(portA.get_name())) - && (this->get_lsb() == portA.get_lsb()) - && (this->get_msb() == portA.get_msb()) ) { - return true; - } - return false; +bool BasicPort::operator==(const BasicPort& portA) const { + if ((0 == this->get_name().compare(portA.get_name())) + && (this->get_lsb() == portA.get_lsb()) + && (this->get_msb() == portA.get_msb())) { + return true; + } + return false; } -bool BasicPort::operator< (const BasicPort& portA) const { - if ( (0 == this->get_name().compare(portA.get_name())) - && (this->get_lsb() < portA.get_lsb()) - && (this->get_msb() < portA.get_msb()) ) { - return true; - } - return false; +bool BasicPort::operator<(const BasicPort& portA) const { + if ((0 == this->get_name().compare(portA.get_name())) + && (this->get_lsb() < portA.get_lsb()) + && (this->get_msb() < portA.get_msb())) { + return true; + } + return false; } - /************************************************************************ * Mutators ***********************************************************************/ /* copy */ void BasicPort::set(const BasicPort& basic_port) { - name_ = basic_port.get_name(); - lsb_ = basic_port.get_lsb(); - msb_ = basic_port.get_msb(); - origin_port_width_ = basic_port.get_origin_port_width(); + name_ = basic_port.get_name(); + lsb_ = basic_port.get_lsb(); + msb_ = basic_port.get_msb(); + origin_port_width_ = basic_port.get_origin_port_width(); - return; + return; } /* set the port LSB and MSB */ -void BasicPort::set_name(const std::string& name) { - name_ = name; - return; +void BasicPort::set_name(const std::string& name) { + name_ = name; + return; } - + /* set the port LSB and MSB */ void BasicPort::set_width(const size_t& width) { - if (0 == width) { - make_invalid(); + if (0 == width) { + make_invalid(); + return; + } + lsb_ = 0; + msb_ = width - 1; return; - } - lsb_ = 0; - msb_ = width - 1; - return; } - + /* set the port LSB and MSB */ void BasicPort::set_width(const size_t& lsb, const size_t& msb) { - /* If lsb and msb is invalid, we make a default port */ - if (lsb > msb) { - make_invalid(); + /* If lsb and msb is invalid, we make a default port */ + if (lsb > msb) { + make_invalid(); + return; + } + set_lsb(lsb); + set_msb(msb); return; - } - set_lsb(lsb); - set_msb(msb); - return; } - + void BasicPort::set_lsb(const size_t& lsb) { - lsb_ = lsb; - return; + lsb_ = lsb; + return; } void BasicPort::set_msb(const size_t& msb) { - msb_ = msb; - return; + msb_ = msb; + return; } void BasicPort::set_origin_port_width(const size_t& origin_port_width) { - origin_port_width_ = origin_port_width; - return; + origin_port_width_ = origin_port_width; + return; } /* Increase the port width */ -void BasicPort::expand(const size_t& width) { - if (0 == width) { - return; /* ignore zero-width port */ - } - /* If current port is invalid, we do not combine */ - if (0 == get_width()) { - lsb_ = 0; - msb_ = width; +void BasicPort::expand(const size_t& width) { + if (0 == width) { + return; /* ignore zero-width port */ + } + /* If current port is invalid, we do not combine */ + if (0 == get_width()) { + lsb_ = 0; + msb_ = width; + return; + } + /* Increase MSB */ + msb_ += width; return; - } - /* Increase MSB */ - msb_ += width; - return; } /* Swap lsb and msb */ void BasicPort::revert() { - std::swap(lsb_, msb_); - return; + std::swap(lsb_, msb_); + return; } - + /* rotate: increase both lsb and msb by an offset */ bool BasicPort::rotate(const size_t& offset) { - /* If offset is 0, we do nothing */ - if (0 == offset) { - return true; - } - - /* If current width is 0, we set a width using the offset! */ - if (0 == get_width()) { - set_width(offset); - return true; - } - /* check if leads to overflow: + /* If offset is 0, we do nothing */ + if (0 == offset) { + return true; + } + + /* If current width is 0, we set a width using the offset! */ + if (0 == get_width()) { + set_width(offset); + return true; + } + /* check if leads to overflow: * if limits - msb is larger than offset */ - if ( (std::numeric_limits::max() - msb_ < offset) ) { - return false; - } - /* Increase LSB and MSB */ - lsb_ += offset; - msb_ += offset; - return true; + if ((std::numeric_limits::max() - msb_ < offset)) { + return false; + } + /* Increase LSB and MSB */ + lsb_ += offset; + msb_ += offset; + return true; } /* rotate: decrease both lsb and msb by an offset */ bool BasicPort::counter_rotate(const size_t& offset) { - /* If current port is invalid or offset is 0, + /* If current port is invalid or offset is 0, * we do nothing */ - if ((0 == offset) || (0 == get_width())) { - return true; - } - /* check if leads to overflow: + if ((0 == offset) || (0 == get_width())) { + return true; + } + /* check if leads to overflow: * if limits is larger than offset */ - if ( (std::numeric_limits::min() + lsb_ < offset) ) { - return false; - } - /* decrease LSB and MSB */ - lsb_ -= offset; - msb_ -= offset; - return true; + if ((std::numeric_limits::min() + lsb_ < offset)) { + return false; + } + /* decrease LSB and MSB */ + lsb_ -= offset; + msb_ -= offset; + return true; } - + /* Reset to initial port */ void BasicPort::reset() { - make_invalid(); - return; -} + make_invalid(); + return; +} /* Combine two ports */ void BasicPort::combine(const BasicPort& port) { - /* LSB follows the current LSB */ - /* MSB increases */ - VTR_ASSERT(0 < port.get_width() ); /* Make sure port is valid */ - /* If current port is invalid, we do not combine */ - if (0 == get_width()) { + /* LSB follows the current LSB */ + /* MSB increases */ + VTR_ASSERT(0 < port.get_width()); /* Make sure port is valid */ + /* If current port is invalid, we do not combine */ + if (0 == get_width()) { + return; + } + /* Increase MSB */ + msb_ += port.get_width(); return; - } - /* Increase MSB */ - msb_ += port.get_width(); - return; -} +} /* A restricted combine function for two ports, * Following conditions will be applied: @@ -290,38 +289,38 @@ void BasicPort::combine(const BasicPort& port) { * 4. both ports should be valid!!! */ void BasicPort::merge(const BasicPort& portA) { - VTR_ASSERT(true == this->mergeable(portA)); - VTR_ASSERT(true == this->is_valid() && true == portA.is_valid()); - /* We skip merging if the portA is already contained by this port */ - if (true == this->contained(portA)) { + VTR_ASSERT(true == this->mergeable(portA)); + VTR_ASSERT(true == this->is_valid() && true == portA.is_valid()); + /* We skip merging if the portA is already contained by this port */ + if (true == this->contained(portA)) { + return; + } + /* LSB follows the minium LSB of the two ports */ + lsb_ = std::min((int)lsb_, (int)portA.get_lsb()); + /* MSB follows the minium MSB of the two ports */ + msb_ = std::max((int)msb_, (int)portA.get_msb()); + /* Origin port width follows the maximum of the two ports */ + msb_ = std::max((int)origin_port_width_, (int)portA.get_origin_port_width()); return; - } - /* LSB follows the minium LSB of the two ports */ - lsb_ = std::min((int)lsb_, (int)portA.get_lsb()); - /* MSB follows the minium MSB of the two ports */ - msb_ = std::max((int)msb_, (int)portA.get_msb()); - /* Origin port width follows the maximum of the two ports */ - msb_ = std::max((int)origin_port_width_, (int)portA.get_origin_port_width()); - return; } /* Internal functions */ /* Make a port to be invalid: msb < lsb */ void BasicPort::make_invalid() { - /* set a default invalid port */ - lsb_ = 1; - msb_ = 0; - return; + /* set a default invalid port */ + lsb_ = 1; + msb_ = 0; + return; } /* check if port size is valid > 0 */ bool BasicPort::is_valid() const { - /* msb should be equal or greater than lsb, if this is a valid port */ - if ( msb_ < lsb_ ) { - return false; - } - return true; -} + /* msb should be equal or greater than lsb, if this is a valid port */ + if (msb_ < lsb_) { + return false; + } + return true; +} /************************************************************************ * ConfPorts member functions @@ -331,109 +330,109 @@ bool BasicPort::is_valid() const { * Constructor ***********************************************************************/ /* Default constructor */ -ConfPorts::ConfPorts() { - /* default port */ - reserved_.reset(); - regular_.reset(); +ConfPorts::ConfPorts() { + /* default port */ + reserved_.reset(); + regular_.reset(); } /* copy */ -ConfPorts::ConfPorts(const ConfPorts& conf_ports) { - set(conf_ports); +ConfPorts::ConfPorts(const ConfPorts& conf_ports) { + set(conf_ports); } /************************************************************************ * Accessors ***********************************************************************/ size_t ConfPorts::get_reserved_port_width() const { - return reserved_.get_width(); + return reserved_.get_width(); } size_t ConfPorts::get_reserved_port_lsb() const { - return reserved_.get_lsb(); + return reserved_.get_lsb(); } size_t ConfPorts::get_reserved_port_msb() const { - return reserved_.get_msb(); + return reserved_.get_msb(); } size_t ConfPorts::get_regular_port_width() const { - return regular_.get_width(); + return regular_.get_width(); } size_t ConfPorts::get_regular_port_lsb() const { - return regular_.get_lsb(); + return regular_.get_lsb(); } size_t ConfPorts::get_regular_port_msb() const { - return regular_.get_msb(); + return regular_.get_msb(); } /************************************************************************ * Mutators ***********************************************************************/ void ConfPorts::set(const ConfPorts& conf_ports) { - set_reserved_port(conf_ports.get_reserved_port_width()); - set_regular_port(conf_ports.get_regular_port_lsb(), conf_ports.get_regular_port_msb()); - return; + set_reserved_port(conf_ports.get_reserved_port_width()); + set_regular_port(conf_ports.get_regular_port_lsb(), conf_ports.get_regular_port_msb()); + return; } void ConfPorts::set_reserved_port(size_t width) { - reserved_.set_width(width); - return; + reserved_.set_width(width); + return; } void ConfPorts::set_regular_port(size_t width) { - regular_.set_width(width); - return; + regular_.set_width(width); + return; } void ConfPorts::set_regular_port(size_t lsb, size_t msb) { - regular_.set_width(lsb, msb); - return; + regular_.set_width(lsb, msb); + return; } void ConfPorts::set_regular_port_lsb(size_t lsb) { - regular_.set_lsb(lsb); - return; + regular_.set_lsb(lsb); + return; } void ConfPorts::set_regular_port_msb(size_t msb) { - regular_.set_msb(msb); - return; + regular_.set_msb(msb); + return; } /* Increase the port width of reserved port */ void ConfPorts::expand_reserved_port(size_t width) { - reserved_.expand(width); - return; + reserved_.expand(width); + return; } - + /* Increase the port width of regular port */ -void ConfPorts::expand_regular_port(size_t width) { - regular_.expand(width); - return; +void ConfPorts::expand_regular_port(size_t width) { + regular_.expand(width); + return; } /* Increase the port width of both ports */ -void ConfPorts::expand(size_t width) { - expand_reserved_port(width); - expand_regular_port(width); +void ConfPorts::expand(size_t width) { + expand_reserved_port(width); + expand_regular_port(width); } /* rotate */ bool ConfPorts::rotate_regular_port(size_t offset) { - return regular_.rotate(offset); -} + return regular_.rotate(offset); +} /* counter rotate */ bool ConfPorts::counter_rotate_regular_port(size_t offset) { - return regular_.counter_rotate(offset); + return regular_.counter_rotate(offset); } /* Reset to initial port */ void ConfPorts::reset() { - reserved_.reset(); - regular_.reset(); - return; -} + reserved_.reset(); + regular_.reset(); + return; +} diff --git a/vpr/src/tileable_rr_graph/openfpga_port.h b/vpr/src/tileable_rr_graph/openfpga_port.h index 2975405ebe5..5d9a8ef910c 100644 --- a/vpr/src/tileable_rr_graph/openfpga_port.h +++ b/vpr/src/tileable_rr_graph/openfpga_port.h @@ -15,40 +15,44 @@ class BasicPort { BasicPort(const char* name, const size_t& width); BasicPort(const std::string& name, const size_t& lsb, const size_t& msb); BasicPort(const std::string& name, const size_t& width); + public: /* Overloaded operators */ - bool operator== (const BasicPort& portA) const; - bool operator< (const BasicPort& portA) const; - public: /* Accessors */ - size_t get_width() const; /* get the port width */ - size_t get_msb() const; /* get the LSB */ - size_t get_lsb() const; /* get the LSB */ - std::string get_name() const; /* get the name */ - bool is_valid() const; /* check if port size is valid > 0 */ - std::vector pins() const; /* Make a range of the pin indices */ + bool operator==(const BasicPort& portA) const; + bool operator<(const BasicPort& portA) const; + + public: /* Accessors */ + size_t get_width() const; /* get the port width */ + size_t get_msb() const; /* get the LSB */ + size_t get_lsb() const; /* get the LSB */ + std::string get_name() const; /* get the name */ + bool is_valid() const; /* check if port size is valid > 0 */ + std::vector pins() const; /* Make a range of the pin indices */ bool mergeable(const BasicPort& portA) const; /* Check if a port can be merged with this port */ bool contained(const BasicPort& portA) const; /* Check if a port is contained by this port */ size_t get_origin_port_width() const; - public: /* Mutators */ - void set(const BasicPort& basic_port); /* copy */ - void set_name(const std::string& name); /* set the port LSB and MSB */ - void set_width(const size_t& width); /* set the port LSB and MSB */ + + public: /* Mutators */ + void set(const BasicPort& basic_port); /* copy */ + void set_name(const std::string& name); /* set the port LSB and MSB */ + void set_width(const size_t& width); /* set the port LSB and MSB */ void set_width(const size_t& lsb, const size_t& msb); /* set the port LSB and MSB */ void set_lsb(const size_t& lsb); void set_msb(const size_t& msb); - void expand(const size_t& width); /* Increase the port width */ - void revert(); /* Swap lsb and msb */ - bool rotate(const size_t& offset); /* rotate */ + void expand(const size_t& width); /* Increase the port width */ + void revert(); /* Swap lsb and msb */ + bool rotate(const size_t& offset); /* rotate */ bool counter_rotate(const size_t& offset); /* counter rotate */ - void reset(); /* Reset to initial port */ - void combine(const BasicPort& port); /* Combine two ports */ + void reset(); /* Reset to initial port */ + void combine(const BasicPort& port); /* Combine two ports */ void merge(const BasicPort& portA); void set_origin_port_width(const size_t& origin_port_width); - private: /* internal functions */ - void make_invalid(); /* Make a port invalid */ - private: /* Internal Data */ - std::string name_; /* Name of this port */ - size_t msb_; /* Most Significant Bit of this port */ - size_t lsb_; /* Least Significant Bit of this port */ + + private: /* internal functions */ + void make_invalid(); /* Make a port invalid */ + private: /* Internal Data */ + std::string name_; /* Name of this port */ + size_t msb_; /* Most Significant Bit of this port */ + size_t lsb_; /* Least Significant Bit of this port */ size_t origin_port_width_; /* Original port width of a port, used by traceback port conversion history */ }; @@ -57,16 +61,17 @@ class BasicPort { * 2. regular configuration port, which is used by any FPGA architecture */ class ConfPorts { - public: /* Constructors */ - ConfPorts(); /* default port */ + public: /* Constructors */ + ConfPorts(); /* default port */ ConfPorts(const ConfPorts& conf_ports); /* copy */ - public: /* Accessors */ + public: /* Accessors */ size_t get_reserved_port_width() const; size_t get_reserved_port_lsb() const; size_t get_reserved_port_msb() const; size_t get_regular_port_width() const; size_t get_regular_port_lsb() const; size_t get_regular_port_msb() const; + public: /* Mutators */ void set(const ConfPorts& conf_ports); void set_reserved_port(size_t width); @@ -74,13 +79,13 @@ class ConfPorts { void set_regular_port(size_t lsb, size_t msb); void set_regular_port_lsb(size_t lsb); void set_regular_port_msb(size_t msb); - void expand_reserved_port(size_t width); /* Increase the port width of reserved port */ - void expand_regular_port(size_t width); /* Increase the port width of regular port */ - void expand(size_t width); /* Increase the port width of both ports */ - bool rotate_regular_port(size_t offset); /* rotate */ + void expand_reserved_port(size_t width); /* Increase the port width of reserved port */ + void expand_regular_port(size_t width); /* Increase the port width of regular port */ + void expand(size_t width); /* Increase the port width of both ports */ + bool rotate_regular_port(size_t offset); /* rotate */ bool counter_rotate_regular_port(size_t offset); /* counter rotate */ - void reset(); /* Reset to initial port */ - private: /* Internal Data */ + void reset(); /* Reset to initial port */ + private: /* Internal Data */ BasicPort reserved_; BasicPort regular_; }; @@ -88,4 +93,3 @@ class ConfPorts { /* TODO: create a class for BL and WL ports */ #endif - diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index b237e104443..47809f9da8f 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -71,11 +71,10 @@ vtr::Point get_track_rr_node_end_coordinate(const RRGraphView& rr_graph, ***********************************************************************/ std::vector get_rr_graph_driver_switches(const RRGraphView& rr_graph, const RRNodeId& node) { - std::vector driver_switches; -// NYI -// unused argements + // NYI + // unused argements (void)(rr_graph); (void)(node); #if 0 @@ -96,8 +95,8 @@ std::vector get_rr_graph_driver_nodes(const RRGraphView& rr_graph, const RRNodeId& node) { std::vector driver_nodes; -// NYI -// unused argements + // NYI + // unused argements (void)(rr_graph); (void)(node); #if 0 @@ -116,8 +115,8 @@ std::vector get_rr_graph_configurable_driver_nodes(const RRGraphView& const RRNodeId& node) { std::vector driver_nodes; -// NYI -// unused argements + // NYI + // unused argements (void)(rr_graph); (void)(node); #if 0 @@ -142,8 +141,8 @@ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphVi const RRNodeId& node) { std::vector driver_nodes; -// NYI -// unused argements + // NYI + // unused argements (void)(rr_graph); (void)(node); #if 0 @@ -170,8 +169,8 @@ bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, /* We only accept OPIN */ VTR_ASSERT(OPIN == rr_graph.node_type(node)); -// NYI -// unused argements + // NYI + // unused argements (void)(rr_graph); (void)(node); #if 0 @@ -202,8 +201,8 @@ bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, /* We only accept IPIN */ VTR_ASSERT(IPIN == rr_graph.node_type(node)); -// NYI -// unused argements + // NYI + // unused argements (void)(rr_graph); (void)(node); #if 0 diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h index 69668d762c7..f3d3f65abe8 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h @@ -15,7 +15,7 @@ * Function declaration *******************************************************************/ -vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_graph, +vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node); vtr::Point get_track_rr_node_end_coordinate(const RRGraphView& rr_graph, diff --git a/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp b/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp index ceb93882d23..3b1ee1ec404 100644 --- a/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp @@ -5,167 +5,166 @@ /* Constructors */ SideManager::SideManager(enum e_side side) { - side_ = side; + side_ = side; } SideManager::SideManager() { - side_ = NUM_SIDES; + side_ = NUM_SIDES; } SideManager::SideManager(size_t side) { - set_side(side); + set_side(side); } /* Public Accessors */ enum e_side SideManager::get_side() const { - return side_; + return side_; } enum e_side SideManager::get_opposite() const { - switch (side_) { - case TOP: - return BOTTOM; - case RIGHT: - return LEFT; - case BOTTOM: - return TOP; - case LEFT: - return RIGHT; - default: - return NUM_SIDES; - } + switch (side_) { + case TOP: + return BOTTOM; + case RIGHT: + return LEFT; + case BOTTOM: + return TOP; + case LEFT: + return RIGHT; + default: + return NUM_SIDES; + } } enum e_side SideManager::get_rotate_clockwise() const { - switch (side_) { - case TOP: - return RIGHT; - case RIGHT: - return BOTTOM; - case BOTTOM: - return LEFT; - case LEFT: - return TOP; - default: - return NUM_SIDES; - } + switch (side_) { + case TOP: + return RIGHT; + case RIGHT: + return BOTTOM; + case BOTTOM: + return LEFT; + case LEFT: + return TOP; + default: + return NUM_SIDES; + } } enum e_side SideManager::get_rotate_counterclockwise() const { - switch (side_) { - case TOP: - return LEFT; - case RIGHT: - return TOP; - case BOTTOM: - return RIGHT; - case LEFT: - return BOTTOM; - default: - return NUM_SIDES; - } + switch (side_) { + case TOP: + return LEFT; + case RIGHT: + return TOP; + case BOTTOM: + return RIGHT; + case LEFT: + return BOTTOM; + default: + return NUM_SIDES; + } } bool SideManager::validate() const { - if (NUM_SIDES == side_) { - return false; - } - return true; + if (NUM_SIDES == side_) { + return false; + } + return true; } size_t SideManager::to_size_t() const { - switch (side_) { - case TOP: - return 0; - case RIGHT: - return 1; - case BOTTOM: - return 2; - case LEFT: - return 3; - default: - return 4; - } + switch (side_) { + case TOP: + return 0; + case RIGHT: + return 1; + case BOTTOM: + return 2; + case LEFT: + return 3; + default: + return 4; + } } /* Convert to char* */ const char* SideManager::c_str() const { - switch (side_) { - case TOP: - return "top"; - case RIGHT: - return "right"; - case BOTTOM: - return "bottom"; - case LEFT: - return "left"; - default: - return "invalid_side"; - } + switch (side_) { + case TOP: + return "top"; + case RIGHT: + return "right"; + case BOTTOM: + return "bottom"; + case LEFT: + return "left"; + default: + return "invalid_side"; + } } /* Convert to char* */ std::string SideManager::to_string() const { - std::string ret; - switch (side_) { - case TOP: - ret.assign("top"); - break; - case RIGHT: - ret.assign("right"); - break; - case BOTTOM: - ret.assign("bottom"); - break; - case LEFT: - ret.assign("left"); - break; - default: - ret.assign("invalid_side"); - break; - } - - return ret; + std::string ret; + switch (side_) { + case TOP: + ret.assign("top"); + break; + case RIGHT: + ret.assign("right"); + break; + case BOTTOM: + ret.assign("bottom"); + break; + case LEFT: + ret.assign("left"); + break; + default: + ret.assign("invalid_side"); + break; + } + + return ret; } /* Public Mutators */ void SideManager::set_side(size_t side) { - switch (side) { - case 0: - side_ = TOP; - return; - case 1: - side_ = RIGHT; - return; - case 2: - side_ = BOTTOM; - return; - case 3: - side_ = LEFT; - return; - default: - side_ = NUM_SIDES; - return; - } + switch (side) { + case 0: + side_ = TOP; + return; + case 1: + side_ = RIGHT; + return; + case 2: + side_ = BOTTOM; + return; + case 3: + side_ = LEFT; + return; + default: + side_ = NUM_SIDES; + return; + } } void SideManager::set_side(enum e_side side) { - side_ = side; - return; + side_ = side; + return; } void SideManager::set_opposite() { - side_ = get_opposite(); - return; + side_ = get_opposite(); + return; } void SideManager::rotate_clockwise() { - side_ = get_rotate_clockwise(); - return; + side_ = get_rotate_clockwise(); + return; } void SideManager::rotate_counterclockwise() { - side_ = get_rotate_counterclockwise(); - return; + side_ = get_rotate_counterclockwise(); + return; } - diff --git a/vpr/src/tileable_rr_graph/openfpga_side_manager.h b/vpr/src/tileable_rr_graph/openfpga_side_manager.h index a6eb01d9197..a6eb265cd64 100644 --- a/vpr/src/tileable_rr_graph/openfpga_side_manager.h +++ b/vpr/src/tileable_rr_graph/openfpga_side_manager.h @@ -22,6 +22,7 @@ class SideManager { SideManager(enum e_side side); SideManager(); SideManager(size_t side); + public: /* Accessors */ enum e_side get_side() const; enum e_side get_opposite() const; @@ -31,14 +32,16 @@ class SideManager { size_t to_size_t() const; const char* c_str() const; std::string to_string() const; + public: /* Mutators */ void set_side(size_t side); void set_side(enum e_side side); void set_opposite(); void rotate_clockwise(); void rotate_counterclockwise(); + private: /* internal data */ - enum e_side side_; + enum e_side side_; }; #endif diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h index effa69273f7..11c40595bd3 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.h +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -43,46 +43,46 @@ class RRChan { public: /* Constructors */ RRChan(); + public: /* Accessors */ t_rr_type get_type() const; - size_t get_chan_width() const; /* get the number of tracks in this channel */ + size_t get_chan_width() const; /* get the number of tracks in this channel */ int get_node_track_id(const RRNodeId& node) const; /* get the track_id of a node */ - RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */ + RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */ RRSegmentId get_node_segment(const RRNodeId& node) const; RRSegmentId get_node_segment(const size_t& track_num) const; - bool is_mirror(const RRGraphView& rr_graph, const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */ - std::vector get_segment_ids() const; /* Get a list of segments used in this routing channel */ + bool is_mirror(const RRGraphView& rr_graph, const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */ + std::vector get_segment_ids() const; /* Get a list of segments used in this routing channel */ std::vector get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const; /* Get a list of segments used in this routing channel */ - public: /* Mutators */ + public: /* Mutators */ /* copy */ - void set(const RRChan&); + void set(const RRChan&); /* modify the type of routing channel */ - void set_type(const t_rr_type& type); + void set_type(const t_rr_type& type); /* reseve a number of nodes to the array */ - void reserve_node(const size_t& node_size); + void reserve_node(const size_t& node_size); /* add a node to the routing channel */ - void add_node(const RRGraphView& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment); + void add_node(const RRGraphView& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment); /* clear the content */ - void clear(); + void clear(); private: /* internal functions */ - /* For the type of a routing channel, only valid type is CHANX and CHANY */ - bool valid_type(const t_rr_type& type) const; + bool valid_type(const t_rr_type& type) const; /* Check each node, see if the node type is consistent with the type of routing channel */ - bool valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const; + bool valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const; /* Validate if the track number in the range */ - bool valid_node_id(const size_t& node_id) const; + bool valid_node_id(const size_t& node_id) const; - private: /* Internal Data */ - t_rr_type type_; /* channel type: CHANX or CHANY */ - std::vector nodes_; /* rr nodes of each track in the channel */ + private: /* Internal Data */ + t_rr_type type_; /* channel type: CHANX or CHANY */ + std::vector nodes_; /* rr nodes of each track in the channel */ std::vector node_segments_; /* segment of each track */ }; diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index 05628fac18e..ff0cc9ab782 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -17,32 +17,32 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width); int get_grid_pin_class_index(const t_grid_tile& cur_grid, const int pin_index); -std::vector find_grid_pin_sides(const t_grid_tile& grid, +std::vector find_grid_pin_sides(const t_grid_tile& grid, const size_t& pin_id); -e_side determine_io_grid_pin_side(const vtr::Point& device_size, +e_side determine_io_grid_pin_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate); -std::vector get_grid_side_pins(const t_grid_tile& cur_grid, - const e_pin_type& pin_type, - const e_side& pin_side, +std::vector get_grid_side_pins(const t_grid_tile& cur_grid, + const e_pin_type& pin_type, + const e_side& pin_side, const int& pin_width, const int& pin_height); -size_t get_grid_num_pins(const t_grid_tile& cur_grid, - const e_pin_type& pin_type, +size_t get_grid_num_pins(const t_grid_tile& cur_grid, + const e_pin_type& pin_type, const e_side& io_side); -size_t get_grid_num_classes(const t_grid_tile& cur_grid, +size_t get_grid_num_classes(const t_grid_tile& cur_grid, const e_pin_type& pin_type); bool is_chanx_exist(const DeviceGrid& grids, const vtr::Point& chanx_coord, - const bool& through_channel=false); + const bool& through_channel = false); bool is_chany_exist(const DeviceGrid& grids, const vtr::Point& chany_coord, - const bool& through_channel=false); + const bool& through_channel = false); bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, const vtr::Point& chanx_coord, @@ -90,4 +90,3 @@ short find_rr_graph_average_fan_in(const RRGraph& rr_graph, void print_rr_graph_mux_stats(const RRGraph& rr_graph); #endif - diff --git a/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp index bef1c745557..d389ab757e4 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp @@ -12,15 +12,14 @@ std::vector find_rr_graph_switches(const RRGraphView& rr_graph, const RRNodeId& from_node, const RRNodeId& to_node) { - std::vector switches; - + // NYI // unused parameters (void)(rr_graph); (void)(from_node); (void)(to_node); - #if 0 +#if 0 std::vector edges = rr_graph.find_edges(from_node, to_node); if (true == edges.empty()) { /* edge is open, we return an empty vector of switches */ @@ -33,7 +32,7 @@ std::vector find_rr_graph_switches(const RRGraphView& rr_graph, for (auto edge : edges) { switches.push_back(rr_graph.edge_switch(edge)); } - #endif +#endif return switches; } @@ -57,7 +56,7 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, (void)(y); (void)(rr_type); (void)(ptc); - #if 0 +#if 0 if (rr_type == IPIN || rr_type == OPIN) { //For pins we need to look at all the sides of the current grid tile @@ -76,7 +75,7 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, indices.push_back(rr_node_index); } } - #endif +#endif return indices; } @@ -97,7 +96,7 @@ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, (void)(rr_graph); (void)(x); (void)(y); - #if 0 +#if 0 for (short track = 0; track < rr_graph.chan_num_tracks(x, y, rr_type); ++track) { RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, track); @@ -105,7 +104,7 @@ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, indices.push_back(rr_node_index); } } - #endif +#endif return indices; } @@ -122,14 +121,14 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, std::vector indices; VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); - - /* Ensure that (x, y) is a valid location in grids */ + + /* Ensure that (x, y) is a valid location in grids */ VTR_ASSERT(size_t(x) <= device_grid.width() && size_t(y) <= device_grid.height()); /* Ensure we have a valid side */ VTR_ASSERT(side != NUM_SIDES); - - /* Find all the pins on the side of the grid */ + + /* Find all the pins on the side of the grid */ int width_offset = device_grid[x][y].width_offset; int height_offset = device_grid[x][y].height_offset; for (int pin = 0; pin < device_grid[x][y].type->num_pins; ++pin) { @@ -145,17 +144,14 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, // NYI // unused parameter (void)(rr_graph); - #if 0 +#if 0 /* Try to find the rr node */ RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, pin, side); if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); } - #endif - +#endif } - return indices; } - diff --git a/vpr/src/tileable_rr_graph/rr_graph_obj_util.h b/vpr/src/tileable_rr_graph/rr_graph_obj_util.h index c413386c5dc..f32957e43c2 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_obj_util.h +++ b/vpr/src/tileable_rr_graph/rr_graph_obj_util.h @@ -32,5 +32,4 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const t_rr_type& rr_type, const e_side& side); - #endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_types.h b/vpr/src/tileable_rr_graph/rr_graph_types.h index 5f7297a49c4..ca97d7d38a9 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_types.h +++ b/vpr/src/tileable_rr_graph/rr_graph_types.h @@ -42,5 +42,4 @@ typedef enum e_rr_type : unsigned char { // constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; // constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; - #endif diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 59436c84c1d..d1b6e2b4e1e 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -161,11 +161,11 @@ std::vector RRGSB::get_chan_node_in_edges(const RRGraphView& rr_graph, // NYI // unused parameter (void)(rr_graph); - #if 0 +#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(get_chan_node(side, track_id))) { unsorted_edges.push_back(edge); } - #endif +#endif return unsorted_edges; } @@ -449,10 +449,10 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, VTR_LOG("GSB[%lu][%lu] track node[%lu] at %s:\n", get_x(), get_y(), track_id, SIDE_STRING[node_side]); - // NYI - #if 0 +// NYI +#if 0 rr_graph.print_node(track_node); - #endif +#endif } VTR_ASSERT(true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)); @@ -827,7 +827,7 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, (void)(rr_graph); // unused variable (void)(chan_node); - #if 0 +#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) { /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); @@ -857,7 +857,7 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, edge_counter++; } - #endif +#endif /* Store the sorted edge */ for (size_t side = 0; side < get_num_sides(); ++side) { @@ -987,8 +987,8 @@ bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); - // NYI - #if 0 +// NYI +#if 0 for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { RREdgeId src_edge = node_in_edges[iedge]; RREdgeId src_cand_edge = cand_node_in_edges[iedge]; @@ -1013,7 +1013,7 @@ bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, return false; } } - #endif +#endif return true; } @@ -1039,7 +1039,7 @@ bool RRGSB::is_cb_node_mirror(const RRGraphView& rr_graph, // unused variables (void)(node); (void)(cand_node); - #if 0 +#if 0 if (rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size()) { return false; } @@ -1094,7 +1094,7 @@ bool RRGSB::is_cb_node_mirror(const RRGraphView& rr_graph, return false; } } - #endif +#endif return true; } diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index a2106325c62..00caa876d29 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -49,9 +49,9 @@ * num_conf_bits: number of configuration bits this switch block requires *******************************************************************/ class RRGSB { - public: /* Contructors */ - RRGSB();/* Default constructor */ - public: /* Accessors */ + public: /* Contructors */ + RRGSB(); /* Default constructor */ + public: /* Accessors */ /* Get the number of sides of this SB */ size_t get_num_sides() const; @@ -115,6 +115,7 @@ class RRGSB { /* Check if the node exist in the opposite side of this Switch Block */ bool is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side) const; + public: /* Accessors: to identify mirrors */ /* check if the candidate SB is a mirror of the current one */ bool is_cb_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const; @@ -134,8 +135,7 @@ class RRGSB { bool is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ - bool is_sb_side_segment_mirror(const RRGraphView& rr_graph, const RRGSB& cand, - const e_side& side, const RRSegmentId& seg_id) const; + bool is_sb_side_segment_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side, const RRSegmentId& seg_id) const; /* check if a side of candidate SB is a mirror of the current one * Check the specified side of two switch blocks: @@ -164,19 +164,20 @@ class RRGSB { */ bool is_sb_mirror(const RRGraphView& rr_graph, const RRGSB& cand) const; - public: /* Cooridinator conversion and output */ - size_t get_x() const; /* get the x coordinate of this switch block */ - size_t get_y() const; /* get the y coordinate of this switch block */ - size_t get_sb_x() const; /* get the x coordinate of this switch block */ - size_t get_sb_y() const; /* get the y coordinate of this switch block */ - vtr::Point get_sb_coordinate() const; /* Get the coordinate of the SB */ - size_t get_cb_x(const t_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */ - size_t get_cb_y(const t_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */ + public: /* Cooridinator conversion and output */ + size_t get_x() const; /* get the x coordinate of this switch block */ + size_t get_y() const; /* get the y coordinate of this switch block */ + size_t get_sb_x() const; /* get the x coordinate of this switch block */ + size_t get_sb_y() const; /* get the y coordinate of this switch block */ + vtr::Point get_sb_coordinate() const; /* Get the coordinate of the SB */ + size_t get_cb_x(const t_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */ + size_t get_cb_y(const t_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */ vtr::Point get_cb_coordinate(const t_rr_type& cb_type) const; /* Get the coordinate of the X/Y-direction CB */ - e_side get_cb_chan_side(const t_rr_type& cb_type) const; /* get the side of a Connection block */ - e_side get_cb_chan_side(const e_side& ipin_side) const; /* get the side of a Connection block */ + e_side get_cb_chan_side(const t_rr_type& cb_type) const; /* get the side of a Connection block */ + e_side get_cb_chan_side(const e_side& ipin_side) const; /* get the side of a Connection block */ vtr::Point get_side_block_coordinate(const e_side& side) const; vtr::Point get_grid_coordinate() const; + public: /* Mutators */ /* get a copy from a source */ void set(const RRGSB& src); @@ -249,6 +250,7 @@ class RRGSB { bool validate_opin_node_id(const e_side& side, const size_t& node_id) const; bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const; bool validate_cb_type(const t_rr_type& cb_type) const; + private: /* Internal Data */ /* Coordinator */ vtr::Point coordinate_; @@ -257,10 +259,10 @@ class RRGSB { * Each GSB may have four sides of routing track nodes */ /* Node id in rr_graph denoting each routing track */ - std::vector chan_node_; + std::vector chan_node_; /* Direction of a port when the channel node appear in the GSB module */ - std::vector> chan_node_direction_; + std::vector> chan_node_direction_; /* Sequence of edge ids for each routing channel node, * this is sorted by the location of edge source nodes in the context of GSB @@ -276,10 +278,10 @@ class RRGSB { std::vector>> chan_node_in_edges_; /* Logic Block Inputs data */ - std::vector> ipin_node_; + std::vector> ipin_node_; /* Logic Block Outputs data */ - std::vector> opin_node_; + std::vector> opin_node_; }; #endif diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h index 34a476d80e4..5ce79b61221 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h @@ -1,5 +1,5 @@ -#ifndef TILEABLE_CHAN_DETAILS_BUILDER_H -#define TILEABLE_CHAN_DETAILS_BUILDER_H +#ifndef TILEABLE_CHAN_DETAILS_BUILDER_H +#define TILEABLE_CHAN_DETAILS_BUILDER_H /******************************************************************** * Include header files that are required by function declaration @@ -12,16 +12,16 @@ * Function declaration *******************************************************************/ -std::vector get_num_tracks_per_seg_type(const size_t& chan_width, - const std::vector& segment_inf, +std::vector get_num_tracks_per_seg_type(const size_t& chan_width, + const std::vector& segment_inf, const bool& use_full_seg_groups); int adapt_to_tileable_route_chan_width(const int& chan_width, const std::vector& segment_inf); ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length, - const bool& force_start, - const bool& force_end, + const bool& force_start, + const bool& force_end, const std::vector& segment_inf); #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index c4814f5b78e..8aa3b8485ef 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -207,7 +207,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ bool Fc_clipped = false; /* [0..num_types-1][0..num_pins-1] */ std::vector> Fc_in; - Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*) &chan_width, + Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*)&chan_width, e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped); if (Fc_clipped) { *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; @@ -216,7 +216,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ Fc_clipped = false; /* [0..num_types-1][0..num_pins-1] */ std::vector> Fc_out; - Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*) &chan_width, + Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*)&chan_width, e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped); if (Fc_clipped) { @@ -263,7 +263,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ arch_directs, clb2clb_directs); //NYI -// We may not need to rebuild it again +// We may not need to rebuild it again #if 0 /* First time to build edges so that we can remap the architecture switch to rr_switch * This is a must-do before function alloc_and_load_rr_switch_inf() @@ -304,14 +304,14 @@ void build_tileable_unidir_rr_graph(const std::vector& typ && (CHANY != device_ctx.rr_graph.node_type(inode))) { continue; } - // NYI - #if 0 +// NYI +#if 0 RRIndexedDataId irc_data = device_ctx.rr_graph.node_cost_index(inode); short iseg = device_ctx.rr_indexed_data[irc_data].seg_index; // device_ctx.rr_graph_builder.set_node_segment(inode, RRSegmentId(iseg)); // NYI vtr::vector rr_segments = device_ctx.rr_graph_builder.rr_segments(); rr_segments[(RRSegmentId)iseg] = segment_inf; - #endif +#endif } /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h index e2372d4d196..c5275e1d0a7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -16,19 +16,21 @@ void build_tileable_unidir_rr_graph(const std::vector& types, const DeviceGrid& grids, const t_chan_width& chan_width, - const e_switch_block_type& sb_type, const int& Fs, - const e_switch_block_type& sb_subtype, const int& subFs, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, const std::vector& segment_inf, - const int& delayless_switch, + const int& delayless_switch, const int& wire_to_arch_ipin_switch, const float R_minW_nmos, const float R_minW_pmos, - const enum e_base_cost_type& base_cost_type, - const t_direct_inf *directs, + const enum e_base_cost_type& base_cost_type, + const t_direct_inf* directs, const int& num_directs, int* wire_to_rr_ipin_switch, const bool& through_channel, const bool& wire_opposite_side, - int *Warnings); + int* Warnings); #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index f46e1fc48da..c261af8f655 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -20,9 +20,9 @@ * 1. create edges between SOURCE and OPINs ***********************************************************************/ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids) { + RRGraphBuilder& rr_graph_builder, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids) { for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non OPIN nodes */ if (OPIN != rr_graph.node_type(node)) { @@ -36,16 +36,16 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, /* Create edges between SOURCE and OPINs */ const RRNodeId& src_node = rr_graph_builder.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, - ylow - grids[xlow][ylow].height_offset, - SOURCE, src_node_class_num); + ylow - grids[xlow][ylow].height_offset, + SOURCE, src_node_class_num); VTR_ASSERT(true == rr_graph.validate_node(src_node)); // NYI (void)(rr_node_driver_switches); - #if 0 +#if 0 /* add edges to the src_node */ rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node]); - #endif +#endif } } @@ -54,9 +54,9 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, * 1. create edges between IPINs and SINKs ***********************************************************************/ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids) { + RRGraphBuilder& rr_graph_builder, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids) { for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non IPIN nodes */ if (IPIN != rr_graph.node_type(node)) { @@ -70,21 +70,20 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, /* 1. create edges between IPINs and SINKs */ // NYI (void)(sink_node_class_num); - #if 0 +#if 0 const RRNodeId& sink_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, ylow - grids[xlow][ylow].height_offset, SINK, sink_node_class_num); VTR_ASSERT(true == rr_graph.valid_node_id(sink_node)); - #endif +#endif // NYI (void)(rr_node_driver_switches); (void)(rr_graph_builder); - #if 0 +#if 0 /* add edges to connect the IPIN node to SINK nodes */ rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); - #endif - +#endif } } @@ -181,4 +180,3 @@ void build_rr_graph_direct_connections(const RRGraphView& rr_graph, } } } - diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index cb43d80f8fb..8e780521da3 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -42,14 +42,13 @@ void build_rr_graph_direct_connections(const RRGraphView& rr_graph, const std::vector& clb_to_clb_directs); void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids); + RRGraphBuilder& rr_graph_builder, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids); void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids); + RRGraphBuilder& rr_graph_builder, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids); #endif - diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index e8c019724da..549a50c4d98 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -917,16 +917,15 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, const vtr::vector& rr_node_driver_switches) { - // NYI // unused parameters - (void) (rr_graph_builder); - (void) (rr_gsb); - (void) (track2ipin_map); - (void) (opin2track_map); - (void) (track2track_map); - (void) (rr_node_driver_switches); - #if 0 + (void)(rr_graph_builder); + (void)(rr_gsb); + (void)(track2ipin_map); + (void)(opin2track_map); + (void)(track2track_map); + (void)(rr_node_driver_switches); +#if 0 /* Walk through each sides */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager side_manager(side); @@ -966,7 +965,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, } } } - #endif +#endif } /************************************************************************ @@ -1426,14 +1425,14 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, (void)(from_grid_height_ofs); (void)(to_grid_width_ofs); (void)(to_grid_height_ofs); - #if 0 +#if 0 const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs, from_grid_coordinate.y() - from_grid_height_ofs, OPIN, opin, opin_grid_side[0]); const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs, to_grid_coordinate.y() - to_grid_height_ofs, IPIN, ipin, ipin_grid_side[0]); - #endif +#endif /* VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", from_grid_coordinate.x() - from_grid_width_ofs, @@ -1449,11 +1448,10 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, // NYI // unused parameters (void)(delayless_switch); - #if 0 +#if 0 rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch); - #endif - +#endif } } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 992a446706a..43224fbdbc7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -74,4 +74,3 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, const std::vector& clb_to_clb_directs); #endif - diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index a1a6fc1ffd5..5c9f583658b 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -1,5 +1,5 @@ /************************************************************************ - * This file contains functions that are used to allocate nodes + * This file contains functions that are used to allocate nodes * for the tileable routing resource graph builder ***********************************************************************/ /* Headers from vtrutil library */ @@ -24,60 +24,58 @@ /************************************************************************ * Find the number output pins by considering all the grid ***********************************************************************/ -static -size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, - const t_rr_type& node_type) { - size_t num_grid_rr_nodes = 0; - - for (size_t ix = 0; ix < grids.width(); ++ix) { - for (size_t iy = 0; iy < grids.height(); ++iy) { - - /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { - continue; - } - - /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ( (0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset) ) { - continue; - } - - enum e_side io_side = NUM_SIDES; - - /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids[ix][iy].type)) { - vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); - vtr::Point grid_coordinate(ix, iy); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); - } - - switch (node_type) { - case OPIN: - /* get the number of OPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); - break; - case IPIN: - /* get the number of IPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); - break; - case SOURCE: - /* SOURCE: number of classes whose type is DRIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER); - break; - case SINK: - /* SINK: number of classes whose type is RECEIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER); - break; - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid routing resource node!\n"); - exit(1); - } +static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, + const t_rr_type& node_type) { + size_t num_grid_rr_nodes = 0; + + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ((0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset)) { + continue; + } + + enum e_side io_side = NUM_SIDES; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids[ix][iy].type)) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + vtr::Point grid_coordinate(ix, iy); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + } + + switch (node_type) { + case OPIN: + /* get the number of OPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); + break; + case IPIN: + /* get the number of IPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); + break; + case SOURCE: + /* SOURCE: number of classes whose type is DRIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER); + break; + case SINK: + /* SINK: number of classes whose type is RECEIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER); + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid routing resource node!\n"); + exit(1); + } + } } - } - return num_grid_rr_nodes; + return num_grid_rr_nodes; } /************************************************************************ @@ -87,10 +85,10 @@ size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * * As such, the range of CHANX coordinate starts from x = 1, y = 0 * which is the grid (I/O) at the left bottom of the fabric - * + * * As such, the range of CHANX coordinate ends to x = width - 2, y = height - 2 * which is the grid at the top right of the core fabric - * Note that the I/O ring is + * Note that the I/O ring is * * TOP SIDE OF FPGA * @@ -108,16 +106,16 @@ size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * | Grid | | Grid | ... | Grid | * | [1][0] | | [2][0] | | [width-2][height-2] | * +-------------+ +-------------+ +---------------------+ - * + * * ... ... ... - * + * * +-------------+ +-------------+ +--------------+ * | X-Channel | | X-Channel | ... | X-Channel | * | [1][1] | | [2][1] | | [width-2][1] | * +-------------+ +-------------+ +--------------+ * * LEFT +-------------+ +-------------+ +--------------+ RIGHT - * SIDE | Grid | | Grid | ... | Grid | SIDE + * SIDE | Grid | | Grid | ... | Grid | SIDE * GRID | [1][1] | | [2][1] | | [width-2][1] | GRID * +-------------+ +-------------+ +--------------+ * @@ -133,9 +131,9 @@ size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * * BOTTOM SIDE OF FPGA * - * The figure above describe how the X-direction routing channels are - * organized in a homogeneous FPGA fabric - * Note that we talk about general-purpose uni-directional routing architecture here + * The figure above describe how the X-direction routing channels are + * organized in a homogeneous FPGA fabric + * Note that we talk about general-purpose uni-directional routing architecture here * It means that a routing track may span across multiple grids * However, the hard limits are as follows * All the routing tracks will start at the most LEFT routing channel @@ -145,7 +143,7 @@ size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * in the context of heterogeneous FPGAs * We may have a grid which span multiple column and rows, as exemplified in the figure below * In such case, - * all the routing tracks [x-1][y] at the left side of the grid [x][y] are forced to end + * all the routing tracks [x-1][y] at the left side of the grid [x][y] are forced to end * all the routing tracks [x+2][y] at the right side of the grid [x][y] are forced to start * And there are no routing tracks inside the grid[x][y] * It means that X-channel [x][y] & [x+1][y] will no exist @@ -173,52 +171,51 @@ size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * * ***********************************************************************/ -static -size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - size_t num_chanx_rr_nodes = 0; - - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { - vtr::Point chanx_coord(ix, iy); - - /* Bypass if the routing channel does not exist when through channels are not allowed */ - if ( (false == through_channel) - && (false == is_chanx_exist(grids, chanx_coord))) { - continue; - } - - bool force_start = false; - bool force_end = false; - - /* All the tracks have to start when +static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + size_t num_chanx_rr_nodes = 0; + + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ((false == through_channel) + && (false == is_chanx_exist(grids, chanx_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_start = true; - } + if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_end = true; - } - - /* Evaluate if the routing channel locates in the middle of a grid */ - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); - /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ - num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); - /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ - num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(Direction::DEC); + if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_end = true; + } + + /* Evaluate if the routing channel locates in the middle of a grid */ + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(Direction::DEC); + } } - } - return num_chanx_rr_nodes; + return num_chanx_rr_nodes; } /************************************************************************ @@ -226,78 +223,74 @@ size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, * The technical rationale is very similar to the X-direction routing channel * Refer to the detailed explanation there ***********************************************************************/ -static -size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - size_t num_chany_rr_nodes = 0; - - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - vtr::Point chany_coord(ix, iy); +static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + size_t num_chany_rr_nodes = 0; - /* Bypass if the routing channel does not exist when through channel are not allowed */ - if ( (false == through_channel) - && (false == is_chany_exist(grids, chany_coord))) { - continue; - } + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Point chany_coord(ix, iy); + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ((false == through_channel) + && (false == is_chany_exist(grids, chany_coord))) { + continue; + } - bool force_start = false; - bool force_end = false; + bool force_start = false; + bool force_end = false; - /* All the tracks have to start when + /* All the tracks have to start when * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_start = true; - } + if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_end = true; - } - - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); - /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ - num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); - /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ - num_chany_rr_nodes += chany_details.get_num_ending_tracks(Direction::DEC); + if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_ending_tracks(Direction::DEC); + } } - } - return num_chany_rr_nodes; + return num_chany_rr_nodes; } /************************************************************************ * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ -static -std::vector estimate_num_rr_nodes(const DeviceGrid& grids, - const vtr::Point& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - - /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ - std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); - - /** +static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, + const vtr::Point& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ + std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); + + /** * 1 Find number of rr nodes related to grids */ - num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); - num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); - num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); - num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); + num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); + num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); + num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); + num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); - /** + /** * 2. Assign the segments for each routing channel, * To be specific, for each routing track, we assign a routing segment. - * The assignment is subject to users' specifications, such as + * The assignment is subject to users' specifications, such as * a. length of each type of segment * b. frequency of each type of segment. * c. routing channel width @@ -305,697 +298,684 @@ std::vector estimate_num_rr_nodes(const DeviceGrid& grids, * SPECIAL for fringes: * All segments will start and ends with no exception * - * IMPORTANT: we should be aware that channel width maybe different + * IMPORTANT: we should be aware that channel width maybe different * in X-direction and Y-direction channels!!! - * So we will load segment details for different channels + * So we will load segment details for different channels */ - num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, - chan_width.x(), - segment_infs, - through_channel); - num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, - chan_width.y(), - segment_infs, - through_channel); - - return num_rr_nodes_per_type; + num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, + chan_width.x(), + segment_infs, + through_channel); + num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, + chan_width.y(), + segment_infs, + through_channel); + + return num_rr_nodes_per_type; } /************************************************************************ - * Allocate rr_nodes to a rr_graph object + * Allocate rr_nodes to a rr_graph object * This function just allocate the memory and ensure its efficiency * It will NOT fill detailed information for each node!!! * * Note: ensure that there are NO nodes in the rr_graph ***********************************************************************/ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, const vtr::Point& chan_width, const std::vector& segment_infs, const bool& through_channel) { - VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); + VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); - std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, - chan_width, - segment_infs, - through_channel); + std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + chan_width, + segment_infs, + through_channel); - /* Reserve the number of node to be memory efficient */ - size_t num_nodes = 0; - for (const size_t& num_node_per_type : num_rr_nodes_per_type) { - num_nodes += num_node_per_type; - } + /* Reserve the number of node to be memory efficient */ + size_t num_nodes = 0; + for (const size_t& num_node_per_type : num_rr_nodes_per_type) { + num_nodes += num_node_per_type; + } - rr_graph_builder.reserve_nodes(num_nodes); + rr_graph_builder.reserve_nodes(num_nodes); - rr_node_driver_switches.reserve(num_nodes); + rr_node_driver_switches.reserve(num_nodes); } /************************************************************************ - * Configure OPIN rr_nodes for this grid - * coordinates: xlow, ylow, xhigh, yhigh, + * Configure OPIN rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, ptc_num (pin_num), * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static -void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Walk through the width height of each grid, +static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Walk through the width height of each grid, * get pins and configure the rr_nodes */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { - /* Walk through sides */ - for (e_side side : SIDES) { - SideManager side_manager(side); - /* skip unwanted sides */ - if ( (true == is_io_type(cur_grid.type)) - && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side) ) { - continue; - } - /* Find OPINs */ - /* Configure pins by pins */ - std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), - width, height); - for (const int& pin_num : opin_list) { - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, OPIN, pin_num, side); - - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, - grid_coordinate.y() + height, - grid_coordinate.x() + width, - grid_coordinate.y() + height); - rr_graph_builder.add_node_side(node, side_manager.get_side()); - rr_graph_builder.set_node_pin_num(node, pin_num); - - rr_graph_builder.set_node_capacity(node, 1); - - /* cost index is a FIXED value for OPIN */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); - - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); - - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - - } /* End of loading OPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ - + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + /* Walk through sides */ + for (e_side side : SIDES) { + SideManager side_manager(side); + /* skip unwanted sides */ + if ((true == is_io_type(cur_grid.type)) + && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { + continue; + } + /* Find OPINs */ + /* Configure pins by pins */ + std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), + width, height); + for (const int& pin_num : opin_list) { + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, OPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of loading OPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ - * Configure IPIN rr_nodes for this grid - * coordinates: xlow, ylow, xhigh, yhigh, + * Configure IPIN rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, ptc_num (pin_num), * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static -void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& wire_to_ipin_switch) { - SideManager io_side_manager(io_side); - - /* Walk through the width and height of each grid, +static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& wire_to_ipin_switch) { + SideManager io_side_manager(io_side); + + /* Walk through the width and height of each grid, * get pins and configure the rr_nodes */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { - /* Walk through sides */ - for (e_side side : SIDES) { - SideManager side_manager(side); - /* skip unwanted sides */ - if ( (true == is_io_type(cur_grid.type)) - && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side) ) { - continue; - } - - /* Find IPINs */ - /* Configure pins by pins */ - std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); - for (const int& pin_num : ipin_list) { - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, IPIN, pin_num, side); - - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, - grid_coordinate.y() + height, - grid_coordinate.x() + width, - grid_coordinate.y() + height); - rr_graph_builder.add_node_side(node, side_manager.get_side()); - rr_graph_builder.set_node_pin_num(node, pin_num); - - rr_graph_builder.set_node_capacity(node, 1); - - /* cost index is a FIXED value for OPIN */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); - - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(wire_to_ipin_switch); - - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - - } /* End of loading IPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ + for (int width = 0; width < cur_grid.type->width; ++width) { + for (int height = 0; height < cur_grid.type->height; ++height) { + /* Walk through sides */ + for (e_side side : SIDES) { + SideManager side_manager(side); + /* skip unwanted sides */ + if ((true == is_io_type(cur_grid.type)) + && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { + continue; + } + + /* Find IPINs */ + /* Configure pins by pins */ + std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); + for (const int& pin_num : ipin_list) { + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, IPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(wire_to_ipin_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of loading IPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ - * Configure SOURCE rr_nodes for this grid - * coordinates: xlow, ylow, xhigh, yhigh, + * Configure SOURCE rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, ptc_num (pin_num), * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static -void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Set a SOURCE rr_node for each DRIVER class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Set a SINK rr_node for the OPIN */ - if (DRIVER != cur_grid.type->class_inf[iclass].type) { - continue; - } - - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); - - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), - grid_coordinate.y(), - grid_coordinate.x() + cur_grid.type->width - 1, - grid_coordinate.y() + cur_grid.type->height - 1); - rr_graph_builder.set_node_class_num(node, iclass); - - rr_graph_builder.set_node_capacity(node, 1); - - /* The capacity should be the number of pins in this class*/ - rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); - - /* cost index is a FIXED value for SOURCE */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); - - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); - - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - - } /* End of class enumeration */ +static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Set a SOURCE rr_node for each DRIVER class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (DRIVER != cur_grid.type->class_inf[iclass].type) { + continue; + } + + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); + + rr_graph_builder.set_node_capacity(node, 1); + + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + + /* cost index is a FIXED value for SOURCE */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); + + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + + } /* End of class enumeration */ } /************************************************************************ - * Configure SINK rr_nodes for this grid - * coordinates: xlow, ylow, xhigh, yhigh, + * Configure SINK rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, ptc_num (pin_num), * * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! ***********************************************************************/ -static -void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, - const e_side& io_side, - const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - - /* Set a SINK rr_node for each RECEIVER class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Set a SINK rr_node for the OPIN */ - if (RECEIVER != cur_grid.type->class_inf[iclass].type) { - continue; - } +static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const vtr::Point& grid_coordinate, + const t_grid_tile& cur_grid, + const e_side& io_side, + const RRSwitchId& delayless_switch) { + SideManager io_side_manager(io_side); + + /* Set a SINK rr_node for each RECEIVER class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (RECEIVER != cur_grid.type->class_inf[iclass].type) { + continue; + } - /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + /* Create a new node and fill information */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); - /* node bounding box */ - rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), - grid_coordinate.y(), - grid_coordinate.x() + cur_grid.type->width - 1, - grid_coordinate.y() + cur_grid.type->height - 1); - rr_graph_builder.set_node_class_num(node, iclass); + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + cur_grid.type->width - 1, + grid_coordinate.y() + cur_grid.type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); - rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_capacity(node, 1); - /* The capacity should be the number of pins in this class*/ - rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); - /* cost index is a FIXED value for SINK */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); + /* cost index is a FIXED value for SINK */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); - /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); + /* Switch info */ + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(delayless_switch); - /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); - } /* End of class enumeration */ + } /* End of class enumeration */ } /************************************************************************ * Create all the rr_nodes for grids ***********************************************************************/ -static -void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids, - const RRSwitchId& wire_to_ipin_switch, - const RRSwitchId& delayless_switch) { - - for (size_t iy = 0; iy < grids.height(); ++iy) { - for (size_t ix = 0; ix < grids.width(); ++ix) { - /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { - continue; - } - - /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ - if ( (0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset) ) { - continue; - } - - vtr::Point grid_coordinate(ix, iy); - enum e_side io_side = NUM_SIDES; - - /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids[ix][iy].type)) { - vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); - } - - /* Configure source rr_nodes for this grid */ - load_one_grid_source_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure sink rr_nodes for this grid */ - load_one_grid_sink_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure opin rr_nodes for this grid */ - load_one_grid_opin_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - delayless_switch); - - /* Configure ipin rr_nodes for this grid */ - load_one_grid_ipin_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grid_coordinate, - grids[ix][iy], - io_side, - wire_to_ipin_switch); - +static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids[ix][iy].type)) { + continue; + } + + /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ + if ((0 < grids[ix][iy].width_offset) + || (0 < grids[ix][iy].height_offset)) { + continue; + } + + vtr::Point grid_coordinate(ix, iy); + enum e_side io_side = NUM_SIDES; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids[ix][iy].type)) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + } + + /* Configure source rr_nodes for this grid */ + load_one_grid_source_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure sink rr_nodes for this grid */ + load_one_grid_sink_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure opin rr_nodes for this grid */ + load_one_grid_opin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + delayless_switch); + + /* Configure ipin rr_nodes for this grid */ + load_one_grid_ipin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grid_coordinate, + grids[ix][iy], + io_side, + wire_to_ipin_switch); + } } - } } /************************************************************************ * Initialize the basic information of routing track rr_nodes - * coordinates: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction ***********************************************************************/ -static -void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, - ChanNodeDetails& chan_details, - const std::vector& segment_infs, - const int& cost_index_offset) { - /* Check each node_id(potential ptc_num) in the channel : +static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + ChanNodeDetails& chan_details, + const std::vector& segment_infs, + const int& cost_index_offset) { + /* Check each node_id(potential ptc_num) in the channel : * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num * If this is a ending point, we set xhigh/yhigh and track_ids * For other nodes, we set changes in track_ids */ - for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { - /* For INC direction, a starting point requires a new chan rr_node */ - if ( ( (true == chan_details.is_track_start(itrack)) - && (Direction::INC == chan_details.get_track_direction(itrack)) ) - /* For DEC direction, an ending point requires a new chan rr_node */ - || - ( (true == chan_details.is_track_end(itrack)) - && (Direction::DEC == chan_details.get_track_direction(itrack)) ) ) { - - /* Create a new chan rr_node */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); - - rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); - rr_graph_builder.set_node_track_num(node, itrack); - rr_node_track_ids[node].push_back(itrack); - - rr_graph_builder.set_node_capacity(node, 1); - - /* assign switch id */ - size_t seg_id = chan_details.get_track_segment_id(itrack); - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); - - /* Update chan_details with node_id */ - chan_details.set_track_node_id(itrack, size_t(node)); - - /* cost index depends on the segment index */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_id)); - /* Finish here, go to next */ - } + for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { + /* For INC direction, a starting point requires a new chan rr_node */ + if (((true == chan_details.is_track_start(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack))) + /* For DEC direction, an ending point requires a new chan rr_node */ + || ((true == chan_details.is_track_end(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)))) { + /* Create a new chan rr_node */ + const RRNodeId& node = rr_graph_builder.node_lookup().find_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); + + rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); + rr_graph_builder.set_node_track_num(node, itrack); + rr_node_track_ids[node].push_back(itrack); + + rr_graph_builder.set_node_capacity(node, 1); + + /* assign switch id */ + size_t seg_id = chan_details.get_track_segment_id(itrack); + VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); + rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); + + /* Update chan_details with node_id */ + chan_details.set_track_node_id(itrack, size_t(node)); + + /* cost index depends on the segment index */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_id)); + /* Finish here, go to next */ + } - /* For INC direction, an ending point requires an update on xhigh and yhigh */ - if ( ( (true == chan_details.is_track_end(itrack)) - && (Direction::INC == chan_details.get_track_direction(itrack)) ) - || - /* For DEC direction, an starting point requires an update on xlow and ylow */ - ( (true == chan_details.is_track_start(itrack)) - && (Direction::DEC == chan_details.get_track_direction(itrack)) ) ) { - - /* Get the node_id */ - const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); - - /* Do a quick check, make sure we do not mistakenly modify other nodes */ - VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); - VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); - - /* set xhigh/yhigh and push changes to track_ids */ - rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), - rr_graph.node_ylow(rr_node_id), - chan_coordinate.x(), - chan_coordinate.y()); - - /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ - if ( (rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) - || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id)) ) { - rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.set_node_track_num(rr_node_id, itrack); - } - /* Finish here, go to next */ - } + /* For INC direction, an ending point requires an update on xhigh and yhigh */ + if (((true == chan_details.is_track_end(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack))) + || + /* For DEC direction, an starting point requires an update on xlow and ylow */ + ((true == chan_details.is_track_start(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)))) { + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + + /* set xhigh/yhigh and push changes to track_ids */ + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ + if ((rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) + || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id))) { + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.set_node_track_num(rr_node_id, itrack); + } + /* Finish here, go to next */ + } - /* Finish processing starting and ending tracks */ - if ( (true == chan_details.is_track_start(itrack)) - || (true == chan_details.is_track_end(itrack)) ) { - /* Finish here, go to next */ - continue; - } + /* Finish processing starting and ending tracks */ + if ((true == chan_details.is_track_start(itrack)) + || (true == chan_details.is_track_end(itrack))) { + /* Finish here, go to next */ + continue; + } - /* For other nodes, we get the node_id and just update track_ids */ - /* Ensure those nodes are neither starting nor ending points */ - VTR_ASSERT( (false == chan_details.is_track_start(itrack)) - && (false == chan_details.is_track_end(itrack)) ); + /* For other nodes, we get the node_id and just update track_ids */ + /* Ensure those nodes are neither starting nor ending points */ + VTR_ASSERT((false == chan_details.is_track_start(itrack)) + && (false == chan_details.is_track_end(itrack))); - /* Get the node_id */ - const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); - /* Do a quick check, make sure we do not mistakenly modify other nodes */ - VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); - VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); - /* Deposit xhigh and yhigh using the current chan_coordinate + /* Deposit xhigh and yhigh using the current chan_coordinate * We will update when this track ends */ - rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), - rr_graph.node_ylow(rr_node_id), - chan_coordinate.x(), - chan_coordinate.y()); - - /* Update track_ids */ - rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.set_node_track_num(rr_node_id, itrack); - /* Finish here, go to next */ - } -} + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Update track_ids */ + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.set_node_track_num(rr_node_id, itrack); + /* Finish here, go to next */ + } +} /************************************************************************ * Initialize the basic information of X-channel rr_nodes: - * coordinates: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction * grid_info : pb_graph_pin ***********************************************************************/ -static -void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - - /* For X-direction Channel: CHANX */ - for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ - std::vector track_node_ids; - - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { - vtr::Point chanx_coord(ix, iy); - - /* Bypass if the routing channel does not exist when through channels are not allowed */ - if ( (false == through_channel) - && (false == is_chanx_exist(grids, chanx_coord))) { - continue; - } - - bool force_start = false; - bool force_end = false; - - /* All the tracks have to start when +static void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + /* For X-direction Channel: CHANX */ + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ((false == through_channel) + && (false == is_chanx_exist(grids, chanx_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_start = true; - } + if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { - force_end = true; - } - - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, - force_start, force_end, segment_infs); - /* Force node_ids from the previous chanx */ - if (0 < track_node_ids.size()) { - /* Rotate should be done based on a typical case of routing tracks. - * Tracks on the borders are not regularly started and ended, - * which causes the node_rotation malfunction + if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + force_end = true; + } + + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chanx */ + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction */ - ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, - false, false, segment_infs); - chanx_details_tt.set_track_node_ids(track_node_ids); + ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, + false, false, segment_infs); + chanx_details_tt.set_track_node_ids(track_node_ids); - /* TODO: - * Do NOT rotate the tracks when the routing channel + /* TODO: + * Do NOT rotate the tracks when the routing channel * locates inside a multi-height and multi-width grid - * Let the routing channel passing through the grid (if through channel is allowed!) + * Let the routing channel passing through the grid (if through channel is allowed!) * An example: - * + * * +------------------------------ * | | * | Grid | * track0 ----->+-----------------------------+----> track0 * | | */ - if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { - /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ - /* For INC_DIRECTION, we use clockwise rotation + if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { + /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ + /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D * node_id B ----> / ----> node_id A * node_id C ----> / ----> node_id B - * node_id D ----> ----> node_id C + * node_id D ----> ----> node_id C */ - chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); - /* For DEC_DIRECTION, we use clockwise rotation + chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation * node_id A <----- <----- node_id B * node_id B <----- \ <----- node_id C * node_id C <----- \ <----- node_id D - * node_id D <----- <----- node_id A + * node_id D <----- <----- node_id A */ - chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); - } - - track_node_ids = chanx_details_tt.get_track_node_ids(); - chanx_details.set_track_node_ids(track_node_ids); - } - - /* Configure CHANX in this channel */ - load_one_chan_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - chanx_coord, CHANX, - chanx_details, - segment_infs, - CHANX_COST_INDEX_START); - /* Get a copy of node_ids */ - track_node_ids = chanx_details.get_track_node_ids(); + chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chanx_details_tt.get_track_node_ids(); + chanx_details.set_track_node_ids(track_node_ids); + } + + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + chanx_coord, CHANX, + chanx_details, + segment_infs, + CHANX_COST_INDEX_START); + /* Get a copy of node_ids */ + track_node_ids = chanx_details.get_track_node_ids(); + } } - } } /************************************************************************ * Initialize the basic information of Y-channel rr_nodes: - * coordinates: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction ***********************************************************************/ -static -void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, - std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const size_t& chan_width, - const std::vector& segment_infs, - const bool& through_channel) { - - /* For Y-direction Channel: CHANY */ - for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ - std::vector track_node_ids; - - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - vtr::Point chany_coord(ix, iy); - - /* Bypass if the routing channel does not exist when through channel are not allowed */ - if ( (false == through_channel) - && (false == is_chany_exist(grids, chany_coord))) { - continue; - } - - bool force_start = false; - bool force_end = false; - - /* All the tracks have to start when +static void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + const DeviceGrid& grids, + const size_t& chan_width, + const std::vector& segment_infs, + const bool& through_channel) { + /* For Y-direction Channel: CHANY */ + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + vtr::Point chany_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ((false == through_channel) + && (false == is_chany_exist(grids, chany_coord))) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_start = true; - } + if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_start = true; + } - /* All the tracks have to end when + /* All the tracks have to end when * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { - force_end = true; - } + if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + force_end = true; + } - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, - force_start, force_end, segment_infs); - /* Force node_ids from the previous chany + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chany * This will not be applied when the routing channel is cut off (force to start) */ - if (0 < track_node_ids.size()) { - /* Rotate should be done based on a typical case of routing tracks. - * Tracks on the borders are not regularly started and ended, - * which causes the node_rotation malfunction + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction */ - ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, - false, false, segment_infs); + ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, + false, false, segment_infs); - chany_details_tt.set_track_node_ids(track_node_ids); + chany_details_tt.set_track_node_ids(track_node_ids); - /* TODO: - * Do NOT rotate the tracks when the routing channel + /* TODO: + * Do NOT rotate the tracks when the routing channel * locates inside a multi-height and multi-width grid - * Let the routing channel passing through the grid (if through channel is allowed!) + * Let the routing channel passing through the grid (if through channel is allowed!) * An example: - * + * * +------------------------------ * | | * | Grid | * track0 ----->+-----------------------------+----> track0 * | | - * we should rotate only once at the bottom side of a grid + * we should rotate only once at the bottom side of a grid */ - if (true == is_chany_exist(grids, chany_coord, through_channel)) { - /* Rotate the chany_details by an offset of 1*/ - /* For INC_DIRECTION, we use clockwise rotation + if (true == is_chany_exist(grids, chany_coord, through_channel)) { + /* Rotate the chany_details by an offset of 1*/ + /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D * node_id B ----> / ----> node_id A * node_id C ----> / ----> node_id B - * node_id D ----> ----> node_id C + * node_id D ----> ----> node_id C */ - chany_details_tt.rotate_track_node_id(1, Direction::INC, true); - /* For DEC_DIRECTION, we use clockwise rotation + chany_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation * node_id A <----- <----- node_id B * node_id B <----- \ <----- node_id C * node_id C <----- \ <----- node_id D - * node_id D <----- <----- node_id A + * node_id D <----- <----- node_id A */ - chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); + chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chany_details_tt.get_track_node_ids(); + chany_details.set_track_node_ids(track_node_ids); + } + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + chany_coord, CHANY, + chany_details, + segment_infs, + CHANX_COST_INDEX_START + segment_infs.size()); + /* Get a copy of node_ids */ + track_node_ids = chany_details.get_track_node_ids(); } - - track_node_ids = chany_details_tt.get_track_node_ids(); - chany_details.set_track_node_ids(track_node_ids); - } - /* Configure CHANX in this channel */ - load_one_chan_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - chany_coord, CHANY, - chany_details, - segment_infs, - CHANX_COST_INDEX_START + segment_infs.size()); - /* Get a copy of node_ids */ - track_node_ids = chany_details.get_track_node_ids(); } - } } /************************************************************************ * Reverse the track_ids of CHANX and CHANY nodes in DEC_DIRECTION * This is required as the track ids are allocated in the sequence * of incrementing x and y - * However, DEC direction routing tracks should have a reversed sequence in - * track ids + * However, DEC direction routing tracks should have a reversed sequence in + * track ids ***********************************************************************/ -static -void reverse_dec_chan_rr_node_track_ids(const RRGraphBuilder& rr_graph_builder, - std::map>& rr_node_track_ids) { +static void reverse_dec_chan_rr_node_track_ids(const RRGraphBuilder& rr_graph_builder, + std::map>& rr_node_track_ids) { + // NYI + // unused parameters + (void)(rr_graph_builder); + (void)(rr_node_track_ids); #if 0 // this should call rr_graph_builder to do the job for (const RRNodeId& node : rr_graph_builder.nodes()) { @@ -1019,39 +999,38 @@ void reverse_dec_chan_rr_node_track_ids(const RRGraphBuilder& rr_graph_builder, ***********************************************************************/ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const vtr::Point& chan_width, + const DeviceGrid& grids, + const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, const bool& through_channel) { - load_grid_nodes_basic_info(rr_graph_builder, - rr_node_driver_switches, - grids, - wire_to_ipin_switch, - delayless_switch); - - load_chanx_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - grids, - chan_width.x(), - segment_infs, - through_channel); - - load_chany_rr_nodes_basic_info(rr_graph, - rr_graph_builder, - rr_node_driver_switches, - rr_node_track_ids, - grids, - chan_width.y(), - segment_infs, - through_channel); - - reverse_dec_chan_rr_node_track_ids(rr_graph_builder, - rr_node_track_ids); - + load_grid_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + grids, + wire_to_ipin_switch, + delayless_switch); + + load_chanx_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + chan_width.x(), + segment_infs, + through_channel); + + load_chany_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + grids, + chan_width.y(), + segment_infs, + through_channel); + + reverse_dec_chan_rr_node_track_ids(rr_graph_builder, + rr_node_track_ids); } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 8317c10169b..cb8839018a7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -21,7 +21,7 @@ *******************************************************************/ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, - vtr::vector& driver_switches, + vtr::vector& driver_switches, const DeviceGrid& grids, const vtr::Point& chan_width, const std::vector& segment_infs, @@ -29,15 +29,13 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, - vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, - const vtr::Point& chan_width, + const DeviceGrid& grids, + const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, const bool& through_channel); - - #endif From f3a6875e19b5a4785964638ef6bde8c3342b7147 Mon Sep 17 00:00:00 2001 From: taoli4rs Date: Wed, 3 Aug 2022 10:42:15 -0700 Subject: [PATCH 008/453] Code cleanup: change comments format by complying to vtr clang format. --- vpr/src/base/SetupVPR.cpp | 2 +- vpr/src/route/rr_graph.cpp | 24 +- vpr/src/route/rr_graph.h | 10 +- .../tileable_rr_graph/chan_node_details.cpp | 12 +- vpr/src/tileable_rr_graph/openfpga_port.cpp | 42 +-- .../rr_graph_builder_utils.cpp | 12 +- vpr/src/tileable_rr_graph/rr_gsb.cpp | 80 ++--- .../tileable_chan_details_builder.cpp | 32 +- .../tileable_rr_graph_builder.cpp | 86 +++--- .../tileable_rr_graph_gsb.cpp | 284 +++++++++--------- .../tileable_rr_graph_node_builder.cpp | 202 ++++++------- 11 files changed, 393 insertions(+), 393 deletions(-) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 123bbb2d423..14bb78b40be 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -351,7 +351,7 @@ static void SetupRoutingArch(const t_arch& Arch, /* copy over the switch block information */ RoutingArch->switchblocks = Arch.switchblocks; - + /* Copy the tileable routing setting */ RoutingArch->tileable = Arch.tileable; RoutingArch->through_channel = Arch.through_channel; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 23ed4a8ce40..8c1b44dffad 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -235,8 +235,6 @@ void uniquify_edges(t_rr_edge_info_set& rr_edges_to_create); void alloc_and_load_edges(RRGraphBuilder& rr_graph_builder, const t_rr_edge_info_set& rr_edges_to_create); - - static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin); static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const t_arch_switch_fanin& switch_fanin); @@ -1026,10 +1024,10 @@ static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin } void rr_graph_externals(const std::vector& segment_inf, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - int wire_to_rr_ipin_switch, - enum e_base_cost_type base_cost_type) { + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + int wire_to_rr_ipin_switch, + enum e_base_cost_type base_cost_type) { auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; add_rr_graph_C_from_switches(rr_graph.rr_switch_inf(RRSwitchId(wire_to_rr_ipin_switch)).Cin); @@ -1123,13 +1121,13 @@ static t_seg_details* alloc_and_load_global_route_seg_details(const int global_r /* Calculates the number of track connections from each block pin to each segment type */ std::vector> alloc_and_load_actual_fc(const std::vector& types, - const int max_pins, - const std::vector& segment_inf, - const int* sets_per_seg_type, - const t_chan_width* nodes_per_chan, - const e_fc_type fc_type, - const enum e_directionality directionality, - bool* Fc_clipped) { + const int max_pins, + const std::vector& segment_inf, + const int* sets_per_seg_type, + const t_chan_width* nodes_per_chan, + const e_fc_type fc_type, + const enum e_directionality directionality, + bool* Fc_clipped) { //Initialize Fc of all blocks to zero auto zeros = vtr::Matrix({size_t(max_pins), segment_inf.size()}, 0); std::vector> Fc(types.size(), zeros); diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index 2d230f92fb8..2a6bcd8a367 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -80,10 +80,12 @@ std::vector> alloc_and_load_actual_fc(const std::vector ChanNodeDetails::get_seg_group(const size_t& track_id) const { VTR_ASSERT(validate_chan_width()); @@ -222,8 +222,8 @@ void ChanNodeDetails::rotate_track_node_id(const size_t& offset, const Direction } /* Rotate the node_ids by groups - * A group begins from a track_start and ends before another track_start - */ + * A group begins from a track_start and ends before another track_start + */ VTR_ASSERT(validate_chan_width()); for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { /* Bypass non-start segment */ @@ -264,7 +264,7 @@ void ChanNodeDetails::clear() { } /************************************************************************ - * Validators + * Validators ***********************************************************************/ bool ChanNodeDetails::validate_chan_width() const { size_t chan_width = track_node_ids_.size(); diff --git a/vpr/src/tileable_rr_graph/openfpga_port.cpp b/vpr/src/tileable_rr_graph/openfpga_port.cpp index 3d4d59348f6..63542cd7d5a 100644 --- a/vpr/src/tileable_rr_graph/openfpga_port.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_port.cpp @@ -8,7 +8,7 @@ #include "openfpga_port.h" /************************************************************************ - * Member functions for BasicPort class + * Member functions for BasicPort class ***********************************************************************/ /************************************************************************ @@ -49,7 +49,7 @@ BasicPort::BasicPort(const std::string& name, const size_t& width) { } /************************************************************************ - * Accessors + * Accessors ***********************************************************************/ /* get the port width */ size_t BasicPort::get_width() const { @@ -98,8 +98,8 @@ bool BasicPort::mergeable(const BasicPort& portA) const { } /* Check if a port is contained by this port: - * this function will check if the (LSB, MSB) of portA - * is contained by the (LSB, MSB) of this port + * this function will check if the (LSB, MSB) of portA + * is contained by the (LSB, MSB) of this port */ bool BasicPort::contained(const BasicPort& portA) const { return (lsb_ <= portA.get_lsb() && portA.get_msb() <= msb_); @@ -111,12 +111,12 @@ size_t BasicPort::get_origin_port_width() const { } /************************************************************************ - * Overloaded operators + * Overloaded operators ***********************************************************************/ -/* Two ports are the same only when: +/* Two ports are the same only when: * 1. port names are the same * 2. LSBs are the same - * 3. MSBs are the same + * 3. MSBs are the same */ bool BasicPort::operator==(const BasicPort& portA) const { if ((0 == this->get_name().compare(portA.get_name())) @@ -137,7 +137,7 @@ bool BasicPort::operator<(const BasicPort& portA) const { } /************************************************************************ - * Mutators + * Mutators ***********************************************************************/ /* copy */ void BasicPort::set(const BasicPort& basic_port) { @@ -227,9 +227,9 @@ bool BasicPort::rotate(const size_t& offset) { set_width(offset); return true; } - /* check if leads to overflow: - * if limits - msb is larger than offset - */ + /* check if leads to overflow: + * if limits - msb is larger than offset + */ if ((std::numeric_limits::max() - msb_ < offset)) { return false; } @@ -241,15 +241,15 @@ bool BasicPort::rotate(const size_t& offset) { /* rotate: decrease both lsb and msb by an offset */ bool BasicPort::counter_rotate(const size_t& offset) { - /* If current port is invalid or offset is 0, - * we do nothing - */ + /* If current port is invalid or offset is 0, + * we do nothing + */ if ((0 == offset) || (0 == get_width())) { return true; } - /* check if leads to overflow: - * if limits is larger than offset - */ + /* check if leads to overflow: + * if limits is larger than offset + */ if ((std::numeric_limits::min() + lsb_ < offset)) { return false; } @@ -282,7 +282,7 @@ void BasicPort::combine(const BasicPort& port) { /* A restricted combine function for two ports, * Following conditions will be applied: * 1. the two ports have the same name - * Note: you must run mergable() function first + * Note: you must run mergable() function first * to make sure this assumption is valid * 2. the new MSB will be the maximum MSB of the two ports * 3. the new LSB will be the minimum LSB of the two ports @@ -323,11 +323,11 @@ bool BasicPort::is_valid() const { } /************************************************************************ - * ConfPorts member functions + * ConfPorts member functions ***********************************************************************/ /************************************************************************ - * Constructor + * Constructor ***********************************************************************/ /* Default constructor */ ConfPorts::ConfPorts() { @@ -369,7 +369,7 @@ size_t ConfPorts::get_regular_port_msb() const { } /************************************************************************ - * Mutators + * Mutators ***********************************************************************/ void ConfPorts::set(const ConfPorts& conf_ports) { set_reserved_port(conf_ports.get_reserved_port_width()); diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 47660c0bd26..cb8afb1db9a 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -247,8 +247,8 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, VTR_ASSERT(0 < chanx_coord.x()); if (1 == chanx_coord.x()) { /* This is already the LEFT side of FPGA fabric, - * it is the same results as chanx is right to a multi-height grid - */ + * it is the same results as chanx is right to a multi-height grid + */ return true; } @@ -322,8 +322,8 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, VTR_ASSERT(0 < chany_coord.y()); if (1 == chany_coord.y()) { /* This is already the BOTTOM side of FPGA fabric, - * it is the same results as chany is at the top of a multi-width grid - */ + * it is the same results as chany is at the top of a multi-width grid + */ return true; } @@ -362,8 +362,8 @@ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, VTR_ASSERT(chany_coord.y() < grids.height() - 1); if (grids.height() - 2 == chany_coord.y()) { /* This is already the TOP side of FPGA fabric, - * it is the same results as chany is at the bottom of a multi-width grid - */ + * it is the same results as chany is at the bottom of a multi-width grid + */ return true; } diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index d1b6e2b4e1e..d1b6f7e4a18 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -153,8 +153,8 @@ std::vector RRGSB::get_chan_node_in_edges(const RRGraphView& rr_graph, VTR_ASSERT(OUT_PORT == get_chan_node_direction(side, track_id)); /* if sorted, we give sorted edges - * if not sorted, we give the empty vector - */ + * if not sorted, we give the empty vector + */ if (0 == chan_node_in_edges_.size()) { std::vector unsorted_edges; @@ -304,12 +304,12 @@ void RRGSB::get_node_side_and_index(const RRGraphView& rr_graph, SideManager side_manager; /* Count the number of existence of cur_rr_node in cur_sb_info - * It could happen that same cur_rr_node appears on different sides of a SB - * For example, a routing track go vertically across the SB. - * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. - * We need to ensure that the found rr_node has the same direction as user want. - * By specifying the direction of rr_node, There should be only one rr_node can satisfy! - */ + * It could happen that same cur_rr_node appears on different sides of a SB + * For example, a routing track go vertically across the SB. + * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. + * We need to ensure that the found rr_node has the same direction as user want. + * By specifying the direction of rr_node, There should be only one rr_node can satisfy! + */ for (side = 0; side < get_num_sides(); ++side) { side_manager.set_side(side); node_index = get_node_index(rr_graph, node, side_manager.get_side(), node_direction); @@ -340,9 +340,9 @@ bool RRGSB::is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, VTR_ASSERT((CHANX == rr_graph.node_type(node)) || (CHANY == rr_graph.node_type(node))); - /* See if we can find the same src_rr_node in the opposite chan_side - * if there is one, it means a shorted wire across the SB - */ + /* See if we can find the same src_rr_node in the opposite chan_side + * if there is one, it means a shorted wire across the SB + */ index = get_node_index(rr_graph, node, side_manager.get_opposite(), IN_PORT); return (-1 != index); @@ -402,13 +402,13 @@ bool RRGSB::is_sb_exist() const { } /************************************************************************ - * Check if the node indicates a passing wire across the Switch Block part of the GSB - * Therefore, we actually do the following check - * Check if a track starts from this GSB or not + * Check if the node indicates a passing wire across the Switch Block part of the GSB + * Therefore, we actually do the following check + * Check if a track starts from this GSB or not * For INC_DIRECTION - * (xlow, ylow) should be same as the GSB side coordinate + * (xlow, ylow) should be same as the GSB side coordinate * For DEC_DIRECTION - * (xhigh, yhigh) should be same as the GSB side coordinate + * (xhigh, yhigh) should be same as the GSB side coordinate ***********************************************************************/ bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, const e_side& node_side, @@ -442,9 +442,9 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, return false; /* This is an ending point */ } - /* Reach here it means that this will be a passing wire, - * we should be able to find the node on the opposite side of the GSB! - */ + /* Reach here it means that this will be a passing wire, + * we should be able to find the node on the opposite side of the GSB! + */ if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) { VTR_LOG("GSB[%lu][%lu] track node[%lu] at %s:\n", get_x(), get_y(), track_id, SIDE_STRING[node_side]); @@ -460,9 +460,9 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, } /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ -/* Idenify mirror Switch blocks - * Check each two switch blocks: - * Number of channel/opin/ipin rr_nodes are same +/* Idenify mirror Switch blocks + * Check each two switch blocks: + * Number of channel/opin/ipin rr_nodes are same * If all above are satisfied, the two switch blocks may be mirrors ! */ bool RRGSB::is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) const { @@ -524,8 +524,8 @@ bool RRGSB::is_sb_side_segment_mirror(const RRGraphView& rr_graph, const RRGSB& return false; } /* Check the track_id of each node - * ptc is not necessary, we care the connectivity! - */ + * ptc is not necessary, we care the connectivity! + */ /* For OUT_PORT rr_node, we need to check fan-in */ if (OUT_PORT != get_chan_node_direction(side, itrack)) { continue; /* skip IN_PORT */ @@ -813,14 +813,14 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, size_t edge_counter = 0; /* For each incoming edge, find the node side and index in this GSB. - * and cache these. Then we will use the data to sort the edge in the - * following sequence: - * 0----------------------------------------------------------------> num_in_edges() - * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| - * For each side, the edge will be sorted by the node index starting from 0 - * For each side, the edge from grid pins will be the 1st part - * while the edge from routing tracks will be the 2nd part - */ + * and cache these. Then we will use the data to sort the edge in the + * following sequence: + * 0----------------------------------------------------------------> num_in_edges() + * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| + * For each side, the edge will be sorted by the node index starting from 0 + * For each side, the edge from grid pins will be the 1st part + * while the edge from routing tracks will be the 2nd part + */ // NYI // unused parameter @@ -951,11 +951,11 @@ void RRGSB::clear_one_side(const e_side& node_side) { * Internal Accessors: identify mirrors ***********************************************************************/ -/* check if two rr_nodes have a similar set of drive_rr_nodes +/* check if two rr_nodes have a similar set of drive_rr_nodes * for each drive_rr_node: * 1. CHANX or CHANY: should have the same side and index * 2. OPIN or IPIN: should have the same side and index - * 3. each drive_rr_switch should be the same + * 3. each drive_rr_switch should be the same */ bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, const RRGSB& cand, @@ -969,10 +969,10 @@ bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, } if (true == is_short_conkt) { - /* Since, both are pass wires, - * The two node should be equivalent - * we can return here - */ + /* Since, both are pass wires, + * The two node should be equivalent + * we can return here + */ return true; } @@ -1018,10 +1018,10 @@ bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, return true; } -/* check if two ipin_nodes have a similar set of drive_rr_nodes +/* check if two ipin_nodes have a similar set of drive_rr_nodes * for each drive_rr_node: * 1. CHANX or CHANY: should have the same side and index - * 2. each drive_rr_switch should be the same + * 2. each drive_rr_switch should be the same */ bool RRGSB::is_cb_node_mirror(const RRGraphView& rr_graph, const RRGSB& cand, diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index 4c185ecd347..1dbdb7a3917 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -1,7 +1,7 @@ /************************************************************************ - * This file contains a builder for the ChanNodeDetails data structure - * Different from VPR rr_graph builders, this builder aims to create a - * highly regular routing channel. Thus, it is called tileable, + * This file contains a builder for the ChanNodeDetails data structure + * Different from VPR rr_graph builders, this builder aims to create a + * highly regular routing channel. Thus, it is called tileable, * which brings significant advantage in producing large FPGA fabrics. ***********************************************************************/ #include @@ -18,10 +18,10 @@ * Generate the number of tracks for each types of routing segments * w.r.t. the frequency of each of segments and channel width * Note that if we dertermine the number of tracks per type using - * chan_width * segment_frequency / total_freq may cause - * The total track num may not match the chan_width, + * chan_width * segment_frequency / total_freq may cause + * The total track num may not match the chan_width, * therefore, we assign tracks one by one until we meet the frequency requirement - * In this way, we can assign the number of tracks with repect to frequency + * In this way, we can assign the number of tracks with repect to frequency ***********************************************************************/ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, const std::vector& segment_inf, @@ -33,7 +33,7 @@ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, demand.resize(segment_inf.size()); /* Scale factor so we can divide by any length - * and still use integers */ + * and still use integers */ /* Get the sum of frequency */ size_t scale = 1; size_t freq_sum = 0; @@ -45,8 +45,8 @@ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, /* Init assignments to 0 and set the demand values */ /* Get the fraction of each segment type considering the frequency: - * num_track_per_seg = chan_width * (freq_of_seg / sum_freq) - */ + * num_track_per_seg = chan_width * (freq_of_seg / sum_freq) + */ for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { result[iseg] = 0; demand[iseg] = scale * chan_width * segment_inf[iseg].frequency; @@ -105,11 +105,11 @@ int adapt_to_tileable_route_chan_width(const int& chan_width, } /************************************************************************ - * Build details of routing tracks in a channel - * The function will + * Build details of routing tracks in a channel + * The function will * 1. Assign the segments for each routing channel, * To be specific, for each routing track, we assign a routing segment. - * The assignment is subject to users' specifications, such as + * The assignment is subject to users' specifications, such as * a. length of each type of segment * b. frequency of each type of segment. * c. routing channel width @@ -154,9 +154,9 @@ int adapt_to_tileable_route_chan_width(const int& chan_width, * if device_side is NUM_SIDES, we assume this channel does not locate on borders * All segments will start and ends with no exception * - * 4. IMPORTANT: we should be aware that channel width maybe different + * 4. IMPORTANT: we should be aware that channel width maybe different * in X-direction and Y-direction channels!!! - * So we will load segment details for different channels + * So we will load segment details for different channels ***********************************************************************/ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length, @@ -198,8 +198,8 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, seg_end = true; } /* Since this is a unidirectional routing architecture, - * Add a pair of tracks, 1 INC track and 1 DEC track - */ + * Add a pair of tracks, 1 INC track and 1 DEC track + */ chan_node_details.add_track(cur_track, Direction::INC, iseg, seg_len, seg_start, seg_end); cur_track++; chan_node_details.add_track(cur_track, Direction::DEC, iseg, seg_len, seg_start, seg_end); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 8aa3b8485ef..ab759e8a219 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -102,7 +102,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ DeviceContext& device_ctx = g_vpr_ctx.mutable_device(); /* The number of segments are in general small, reserve segments may not bring - * significant memory efficiency */ + * significant memory efficiency */ device_ctx.rr_graph_builder.reserve_segments(segment_inf.size()); /* Create the segments */ for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { @@ -110,12 +110,12 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } /* TODO: Load architecture switch to rr_graph switches - * Draft the switches as internal data of RRGraph object - * These are temporary switches copied from arch switches - * We use them to build the edges - * We will reset all the switches in the function - * alloc_and_load_rr_switch_inf() - */ + * Draft the switches as internal data of RRGraph object + * These are temporary switches copied from arch switches + * We use them to build the edges + * We will reset all the switches in the function + * alloc_and_load_rr_switch_inf() + */ /* TODO: Spot the switch id in the architecture switch list */ RRSwitchId wire_to_ipin_rr_switch = RRSwitchId::INVALID(); RRSwitchId delayless_rr_switch = RRSwitchId::INVALID(); @@ -146,8 +146,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ std::map> rr_node_track_ids; /************************ - * Allocate the rr_nodes - ************************/ + * Allocate the rr_nodes + ************************/ alloc_tileable_rr_graph_nodes(device_ctx.rr_graph_builder, rr_node_driver_switches, grids, @@ -156,8 +156,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ through_channel); /************************ - * Create all the rr_nodes - ************************/ + * Create all the rr_nodes + ************************/ create_tileable_rr_graph_nodes(device_ctx.rr_graph, device_ctx.rr_graph_builder, rr_node_driver_switches, @@ -170,14 +170,14 @@ void build_tileable_unidir_rr_graph(const std::vector& typ through_channel); /************************************************************************ - * Create the connectivity of OPINs - * a. Evenly assign connections to OPINs to routing tracks - * b. the connection pattern should be same across the fabric - * - * Create the connectivity of IPINs - * a. Evenly assign connections from routing tracks to IPINs - * b. the connection pattern should be same across the fabric - ***********************************************************************/ + * Create the connectivity of OPINs + * a. Evenly assign connections to OPINs to routing tracks + * b. the connection pattern should be same across the fabric + * + * Create the connectivity of IPINs + * a. Evenly assign connections from routing tracks to IPINs + * b. the connection pattern should be same across the fabric + ***********************************************************************/ /* Global routing uses a single longwire track */ int max_chan_width = find_unidir_routing_channel_width(chan_width.max); VTR_ASSERT(max_chan_width > 0); @@ -195,8 +195,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } /* Fc assignment still uses the old function from VPR. - * Should use tileable version so that we have can have full control - */ + * Should use tileable version so that we have can have full control + */ std::vector num_tracks = get_num_tracks_per_seg_type(max_chan_width / 2, segment_inf, false); int* sets_per_seg_type = (int*)vtr::malloc(sizeof(int) * segment_inf.size()); VTR_ASSERT(num_tracks.size() == segment_inf.size()); @@ -224,13 +224,13 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } /************************************************************************ - * Build the connections tile by tile: - * We classify rr_nodes into a general switch block (GSB) data structure - * where we create edges to each rr_nodes in the GSB with respect to - * Fc_in and Fc_out, switch block patterns - * In addition, we will also handle direct-connections: - * Add edges that bridge OPINs and IPINs to the rr_graph - ***********************************************************************/ + * Build the connections tile by tile: + * We classify rr_nodes into a general switch block (GSB) data structure + * where we create edges to each rr_nodes in the GSB with respect to + * Fc_in and Fc_out, switch block patterns + * In addition, we will also handle direct-connections: + * Add edges that bridge OPINs and IPINs to the rr_graph + ***********************************************************************/ /* Create edges for a tileable rr_graph */ build_rr_graph_edges(device_ctx.rr_graph, @@ -244,9 +244,9 @@ void build_tileable_unidir_rr_graph(const std::vector& typ wire_opposite_side); /************************************************************************ - * Build direction connection lists - * TODO: use tile direct builder - ***********************************************************************/ + * Build direction connection lists + * TODO: use tile direct builder + ***********************************************************************/ /* Create data structure of direct-connections */ t_clb_to_clb_directs* clb_to_clb_directs = NULL; if (num_directs > 0) { @@ -272,7 +272,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ #endif /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, - * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ + * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ alloc_and_load_rr_switch_inf(device_ctx.num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); /* Save the channel widths for the newly constructed graph */ @@ -285,10 +285,10 @@ void build_tileable_unidir_rr_graph(const std::vector& typ #endif /************************************************************************ - * Allocate external data structures - * a. cost_index - * b. RC tree - ***********************************************************************/ + * Allocate external data structures + * a. cost_index + * b. RC tree + ***********************************************************************/ t_unified_to_parallel_seg_index segment_index_map; std::vector segment_inf_x = get_parallel_segs(segment_inf, segment_index_map, X_AXIS); std::vector segment_inf_y = get_parallel_segs(segment_inf, segment_index_map, Y_AXIS); @@ -296,9 +296,9 @@ void build_tileable_unidir_rr_graph(const std::vector& typ *wire_to_rr_ipin_switch, base_cost_type); /* Rebuild the link between RRGraph node and segments - * Should be called only AFTER the function - * rr_graph_externals() - */ + * Should be called only AFTER the function + * rr_graph_externals() + */ for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { if ((CHANX != device_ctx.rr_graph.node_type(inode)) && (CHANY != device_ctx.rr_graph.node_type(inode))) { @@ -315,8 +315,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } /************************************************************************ - * Sanitizer for the rr_graph, check connectivities of rr_nodes - ***********************************************************************/ + * Sanitizer for the rr_graph, check connectivities of rr_nodes + ***********************************************************************/ /* Essential check for rr_graph, build look-up and */ if (false == device_ctx.rr_graph_builder.validate()) { /* Error out if built-in validator of rr_graph fails */ @@ -344,8 +344,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ #endif /************************************************************************ - * Free all temp stucts - ***********************************************************************/ + * Free all temp stucts + ***********************************************************************/ free(sets_per_seg_type); if (nullptr != clb_to_clb_directs) { diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 549a50c4d98..978341a7399 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1,5 +1,5 @@ /************************************************************************ - * This file contains a builder for track-to-track connections inside a + * This file contains a builder for track-to-track connections inside a * tileable General Switch Block (GSB). ***********************************************************************/ #include @@ -42,11 +42,11 @@ enum e_track_status { }; /************************************************************************ - * Check if a track starts from this GSB or not - * (xlow, ylow) should be same as the GSB side coordinate + * Check if a track starts from this GSB or not + * (xlow, ylow) should be same as the GSB side coordinate * - * Check if a track ends at this GSB or not - * (xhigh, yhigh) should be same as the GSB side coordinate + * Check if a track ends at this GSB or not + * (xhigh, yhigh) should be same as the GSB side coordinate ***********************************************************************/ static enum e_track_status determine_track_status_of_gsb(const RRGraphView& rr_graph, const RRGSB& rr_gsb, @@ -173,14 +173,14 @@ static bool is_gsb_in_track_sb_population(const RRGraphView& rr_graph, * Create a list of track_id based on the to_track and num_to_tracks * We consider the following list [to_track, to_track + Fs/3 - 1] * if the [to_track + Fs/3 - 1] exceeds the num_to_tracks, we start over from 0! -***********************************************************************/ + ***********************************************************************/ static std::vector get_to_track_list(const int& Fs, const int& to_track, const int& num_to_tracks) { std::vector to_tracks; for (int i = 0; i < Fs; i = i + 3) { - /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied - * The optimal track selection should be done in a more scientific way!!! - */ + /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied + * The optimal track selection should be done in a more scientific way!!! + */ int to_track_i = to_track + i; /* make sure the track id is still in range */ if (to_track_i > num_to_tracks - 1) { @@ -196,9 +196,9 @@ static std::vector get_to_track_list(const int& Fs, const int& to_track, /************************************************************************ * This function aims to return the track indices that drive the from_track - * in a Switch Block + * in a Switch Block * The track_ids to return will depend on different topologies of SB - * SUBSET, UNIVERSAL, and WILTON. + * SUBSET, UNIVERSAL, and WILTON. ***********************************************************************/ static std::vector get_switch_block_to_track_id(const e_switch_block_type& switch_block_type, const int& Fs, @@ -206,14 +206,14 @@ static std::vector get_switch_block_to_track_id(const e_switch_block_typ const int& from_track, const e_side& to_side, const int& num_to_tracks) { - /* This routine returns the track number to which the from_track should - * connect. It supports any Fs % 3 == 0, switch blocks. - */ + /* This routine returns the track number to which the from_track should + * connect. It supports any Fs % 3 == 0, switch blocks. + */ std::vector to_tracks; - /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied - * The optimal track selection should be done in a more scientific way!!! - */ + /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied + * The optimal track selection should be done in a more scientific way!!! + */ VTR_ASSERT(0 == Fs % 3); /* Adapt from_track to fit in the range of num_to_tracks */ @@ -227,10 +227,10 @@ static std::vector get_switch_block_to_track_id(const e_switch_block_typ case UNIVERSAL: if ((from_side == LEFT) || (from_side == RIGHT)) { - /* For the prev_side, to_track is from_track - * For the next_side, to_track is num_to_tracks - 1 - from_track - * For the opposite_side, to_track is always from_track - */ + /* For the prev_side, to_track is from_track + * For the next_side, to_track is num_to_tracks - 1 - from_track + * For the opposite_side, to_track is always from_track + */ SideManager side_manager(from_side); if ((to_side == side_manager.get_opposite()) || (to_side == side_manager.get_rotate_counterclockwise())) { @@ -242,10 +242,10 @@ static std::vector get_switch_block_to_track_id(const e_switch_block_typ if ((from_side == TOP) || (from_side == BOTTOM)) { - /* For the next_side, to_track is from_track - * For the prev_side, to_track is num_to_tracks - 1 - from_track - * For the opposite_side, to_track is always from_track - */ + /* For the next_side, to_track is from_track + * For the prev_side, to_track is num_to_tracks - 1 - from_track + * For the opposite_side, to_track is always from_track + */ SideManager side_manager(from_side); if ((to_side == side_manager.get_opposite()) || (to_side == side_manager.get_rotate_clockwise())) { @@ -305,7 +305,7 @@ static std::vector get_switch_block_to_track_id(const e_switch_block_typ } /************************************************************************ - * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] + * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] * For a group of from_track nodes and to_track nodes * For each side of from_tracks, we call a routine to get the list of to_tracks * Then, we fill the track2track_map @@ -389,21 +389,21 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, } /************************************************************************ - * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] + * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] * based on the existing routing resources in the General Switch Block (GSB) - * The track_indices is the indices of tracks that the node at from_side and [0..chan_width-1] will drive + * The track_indices is the indices of tracks that the node at from_side and [0..chan_width-1] will drive * IMPORTANT: the track_indices are the indicies in the GSB context, but not the rr_graph!!! * We separate the connections into two groups: - * Group 1: the routing tracks start from this GSB - * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) + * Group 1: the routing tracks start from this GSB + * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) * Group 2: the routing tracks do not start from this GSB (bypassing wires) - * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) - * but we will check the Switch Block (SB) population of these + * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) + * but we will check the Switch Block (SB) population of these * routing segments, and determine which requires connections - * + * * CHANY CHANY CHANY CHANY * [0] [1] [2] [3] - * start yes no yes no + * start yes no yes no * end +-------------------------+ start Group 1 Group 2 * no CHANX[0] | TOP | CHANX[0] yes TOP/BOTTOM TOP/BOTTOM * | | CHANY[0,2] CHANY[1,3] @@ -412,25 +412,25 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, * no CHANX[2] | | CHANX[2] yes * | | * yes CHANX[3] | BOTTOM | CHANX[3] no - * +-------------------------+ + * +-------------------------+ * CHANY CHANY CHANY CHANY * [0] [1] [2] [3] - * start yes no yes no - * + * start yes no yes no + * * The mapping is done in the following steps: (For each side of the GSB) * 1. Build a list of tracks that will start from this side * if a track starts, its xlow/ylow is the same as the x,y of this gsb * 2. Build a list of tracks on the other sides belonging to Group 1. - * Take the example of RIGHT side, we will collect - * a. tracks that will end at the LEFT side + * Take the example of RIGHT side, we will collect + * a. tracks that will end at the LEFT side * b. tracks that will start at the TOP side * c. tracks that will start at the BOTTOM side - * 3. Apply switch block patterns to Group 1 (SUBSET, UNIVERSAL, WILTON) + * 3. Apply switch block patterns to Group 1 (SUBSET, UNIVERSAL, WILTON) * 4. Build a list of tracks on the other sides belonging to Group 1. - * Take the example of RIGHT side, we will collect + * Take the example of RIGHT side, we will collect * a. tracks that will bypass at the TOP side * b. tracks that will bypass at the BOTTOM side - * 5. Apply switch block patterns to Group 2 (SUBSET, UNIVERSAL, WILTON) + * 5. Apply switch block patterns to Group 2 (SUBSET, UNIVERSAL, WILTON) ***********************************************************************/ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, @@ -442,10 +442,10 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const std::vector& segment_inf) { t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ - /* Categorize tracks into 3 groups: - * (1) tracks will start here - * (2) tracks will end here - * (2) tracks will just pass through the SB */ + /* Categorize tracks into 3 groups: + * (1) tracks will start here + * (2) tracks will end here + * (2) tracks will just pass through the SB */ t_track_group start_tracks; /* [0..gsb_side][track_indices] */ t_track_group end_tracks; /* [0..gsb_side][track_indices] */ t_track_group pass_tracks; /* [0..gsb_side][track_indices] */ @@ -461,9 +461,9 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, e_side gsb_side = side_manager.get_side(); /* Build a list of tracks that will start from this side */ for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - /* We need to check Switch block population of this track - * The track node will not be considered if there supposed to be no SB at this position - */ + /* We need to check Switch block population of this track + * The track node will not be considered if there supposed to be no SB at this position + */ if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, gsb_side, inode, segment_inf)) { continue; /* skip this node and go to the next */ } @@ -516,8 +516,8 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, /* For Group 2: we build connections between end_tracks and start_tracks*/ /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks, - * TODO: This can be improved with different patterns! - */ + * TODO: This can be improved with different patterns! + */ build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, sb_subtype, subFs, wire_opposite_side, /* Pass tracks may not be wired to start tracks */ @@ -558,10 +558,10 @@ static RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordina } /*********************************************************************** - * Build a General Switch Block (GSB) + * Build a General Switch Block (GSB) * which includes: * [I] A Switch Box subckt consists of following ports: - * 1. Channel Y [x][y] inputs + * 1. Channel Y [x][y] inputs * 2. Channel X [x+1][y] inputs * 3. Channel Y [x][y-1] outputs * 4. Channel X [x][y] outputs @@ -581,7 +581,7 @@ static RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordina * | | | | * -------------- -------------- * ---------- - * ChanX & CBX | Switch | ChanX + * ChanX & CBX | Switch | ChanX * [x][y] | Box | [x+1][y] * | [x][y] | * ---------- @@ -602,11 +602,11 @@ static RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordina * * [II] A X-direction Connection Block [x][y] * The connection block shares the same routing channel[x][y] with the Switch Block - * We just need to fill the ipin nodes at TOP and BOTTOM sides + * We just need to fill the ipin nodes at TOP and BOTTOM sides * as well as properly fill the ipin_grid_side information * [III] A Y-direction Connection Block [x][y+1] * The connection block shares the same routing channel[x][y+1] with the Switch Block - * We just need to fill the ipin nodes at LEFT and RIGHT sides + * We just need to fill the ipin nodes at LEFT and RIGHT sides * as well as properly fill the ipin_grid_side information ***********************************************************************/ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, @@ -638,9 +638,9 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ - /* Build a segment details, where we need the segment ids for building rr_chan - * We do not care starting and ending points here, so set chan_side as NUM_SIDES - */ + /* Build a segment details, where we need the segment ids for building rr_chan + * We do not care starting and ending points here, so set chan_side as NUM_SIDES + */ ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width.x(), grids.width() - 1, false, false, segment_inf); ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width.y(), grids.height() - 1, @@ -812,34 +812,34 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, opin_grid_side[1] = NUM_SIDES; } - /* Add IPIN nodes from adjacent grids: the 4 grids sitting on the 4 corners of the Switch Block - * - * - The concept of top/bottom side of connection block in GSB domain: - * - * | Grid[x][y+1] | - * | BOTTOM side | - * +-----------------------+ - * | - * v - * +-----------------------+ - * | TOP side | - * | X- Connection Block | - * | BOTTOM side | - * +-----------------------+ - * ^ - * | - * +-----------------------+ - * | TOP side | - * | Grid[x][y] | - * - * - The concept of top/bottom side of connection block in GSB domain: - * - * ---------------+ +---------------------- ... ---------------------+ +---------------- - * Grid[x][y+1] |->| Y- Connection Block Y- Connection Block |<-| Grid[x+1][y+1] - * RIGHT side | | LEFT side ... RIGHT side | | LEFT side - * --------------+ +---------------------- ... ---------------------+ +---------------- - * - */ + /* Add IPIN nodes from adjacent grids: the 4 grids sitting on the 4 corners of the Switch Block + * + * - The concept of top/bottom side of connection block in GSB domain: + * + * | Grid[x][y+1] | + * | BOTTOM side | + * +-----------------------+ + * | + * v + * +-----------------------+ + * | TOP side | + * | X- Connection Block | + * | BOTTOM side | + * +-----------------------+ + * ^ + * | + * +-----------------------+ + * | TOP side | + * | Grid[x][y] | + * + * - The concept of top/bottom side of connection block in GSB domain: + * + * ---------------+ +---------------------- ... ---------------------+ +---------------- + * Grid[x][y+1] |->| Y- Connection Block Y- Connection Block |<-| Grid[x+1][y+1] + * RIGHT side | | LEFT side ... RIGHT side | | LEFT side + * --------------+ +---------------------- ... ---------------------+ +---------------- + * + */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager side_manager(side); size_t ix; @@ -907,9 +907,9 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /************************************************************************ * Create edges for each rr_node of a General Switch Blocks (GSB): - * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) - * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) - * 3. create edges between OPINs and IPINs (direct-connections) + * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) + * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) + * 3. create edges between OPINs and IPINs (direct-connections) ***********************************************************************/ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRGSB& rr_gsb, @@ -943,9 +943,9 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, } /* Find CHANX or CHANY */ - /* For TRACKs to IPINs, we only care LEFT and TOP sides - * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs - */ + /* For TRACKs to IPINs, we only care LEFT and TOP sides + * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs + */ if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ @@ -969,9 +969,9 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, } /************************************************************************ - * Build track2ipin_map for an IPIN + * Build track2ipin_map for an IPIN * 1. build a list of routing tracks which are allowed for connections - * We will check the Connection Block (CB) population of each routing track. + * We will check the Connection Block (CB) population of each routing track. * By comparing current chan_y - ylow, we can determine if a CB connection * is required for each routing track * 2. Divide the routing tracks by segment types, so that we can balance @@ -1015,9 +1015,9 @@ static void build_gsb_one_ipin_track2pin_map(const RRGraphView& rr_graph, int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ actual_Fc = std::max(1, actual_Fc); - /* Compute the step between two connection from this IPIN to tracks: - * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in - */ + /* Compute the step between two connection from this IPIN to tracks: + * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + */ size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); /* Make sure step should be at least 2 */ track_step = std::max(1, (int)track_step); @@ -1052,19 +1052,19 @@ static void build_gsb_one_ipin_track2pin_map(const RRGraphView& rr_graph, /* Ensure the number of tracks is similar to Fc */ /* Give a warning if Fc is < track_cnt */ /* - if (actual_Fc != track_cnt) { - vpr_printf(TIO_MESSAGE_INFO, - "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", - ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); - } - */ + * if (actual_Fc != track_cnt) { + * vpr_printf(TIO_MESSAGE_INFO, + * "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + * ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); + * } + */ } } /************************************************************************ - * Build opin2track_map for an OPIN + * Build opin2track_map for an OPIN * 1. build a list of routing tracks which are allowed for connections - * We will check the Switch Block (SB) population of each routing track. + * We will check the Switch Block (SB) population of each routing track. * By comparing current chan_y - ylow, we can determine if a SB connection * is required for each routing track * 2. Divide the routing tracks by segment types, so that we can balance @@ -1112,9 +1112,9 @@ static void build_gsb_one_opin_pin2track_map(const RRGraphView& rr_graph, int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ actual_Fc = std::max(1, actual_Fc); - /* Compute the step between two connection from this IPIN to tracks: - * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in - */ + /* Compute the step between two connection from this IPIN to tracks: + * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + */ size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); /* Track step mush be a multiple of 2!!!*/ /* Make sure step should be at least 1 */ @@ -1141,34 +1141,34 @@ static void build_gsb_one_opin_pin2track_map(const RRGraphView& rr_graph, opin2track_map[opin_side_index][opin_node_id].push_back(track_rr_node_index); /* update track counter */ track_cnt++; - /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. - * So I comment it. And we just make sure its track_cnt >= actual_Fc - if (actual_Fc == track_cnt) { - break; - } - */ + /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. + * So I comment it. And we just make sure its track_cnt >= actual_Fc + * if (actual_Fc == track_cnt) { + * break; + * } + */ } /* Ensure the number of tracks is similar to Fc */ /* Give a warning if Fc is < track_cnt */ /* - if (actual_Fc != track_cnt) { - vpr_printf(TIO_MESSAGE_INFO, - "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", - opin_node_id, track_cnt, actual_Fc); - } - */ + * if (actual_Fc != track_cnt) { + * vpr_printf(TIO_MESSAGE_INFO, + * "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + * opin_node_id, track_cnt, actual_Fc); + * } + */ } } /************************************************************************ - * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] + * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] * based on the existing routing resources in the General Switch Block (GSB) - * This function supports both X-directional and Y-directional tracks + * This function supports both X-directional and Y-directional tracks * The mapping is done in the following steps: * 1. Build ipin_to_track_map[gsb_side][0..num_ipin_nodes-1][track_indices] * For each IPIN, we ensure at least one connection to the tracks. - * Then, we assign IPINs to tracks evenly while satisfying the actual_Fc + * Then, we assign IPINs to tracks evenly while satisfying the actual_Fc * 2. Convert the ipin_to_track_map to track_to_ipin_map ***********************************************************************/ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, @@ -1250,9 +1250,9 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, } /************************************************************************ - * Build the opin_to_track_map[gsb_side][0..num_opin_nodes-1][track_indices] + * Build the opin_to_track_map[gsb_side][0..num_opin_nodes-1][track_indices] * based on the existing routing resources in the General Switch Block (GSB) - * This function supports both X-directional and Y-directional tracks + * This function supports both X-directional and Y-directional tracks * The mapping is done in the following steps: * 1. Build a list of routing tracks whose starting points locate at this GSB * (xlow - gsb_x == 0) @@ -1323,15 +1323,15 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, } /* Check: - * 1. We want to ensure that each OPIN will drive at least one track - * 2. We want to ensure that each track will be driven by at least 1 OPIN */ + * 1. We want to ensure that each OPIN will drive at least one track + * 2. We want to ensure that each track will be driven by at least 1 OPIN */ } return opin2track_map; } /************************************************************************ - * Add all direct clb-pin-to-clb-pin edges to given opin + * Add all direct clb-pin-to-clb-pin edges to given opin ***********************************************************************/ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, @@ -1352,9 +1352,9 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, continue; } - /* This opin is specified to connect directly to an ipin, - * now compute which ipin to connect to - */ + /* This opin is specified to connect directly to an ipin, + * now compute which ipin to connect to + */ vtr::Point to_grid_coordinate(from_grid_coordinate.x() + directs[i].x_offset, from_grid_coordinate.y() + directs[i].y_offset); @@ -1408,8 +1408,8 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, int to_grid_height_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].height_offset; /* Find the side of grid pins, the pin location should be unique! - * Pin location is required by searching a node in rr_graph - */ + * Pin location is required by searching a node in rr_graph + */ std::vector opin_grid_side = find_grid_pin_sides(from_grid, opin); VTR_ASSERT(1 == opin_grid_side.size()); @@ -1434,14 +1434,14 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, IPIN, ipin, ipin_grid_side[0]); #endif /* - VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", - from_grid_coordinate.x() - from_grid_width_ofs, - from_grid_coordinate.y() - from_grid_height_ofs, - opin, SIDE_STRING[opin_grid_side[0]], - to_grid_coordinate.x() - to_grid_width_ofs, - to_grid_coordinate.y() - to_grid_height_ofs, - ipin, SIDE_STRING[ipin_grid_side[0]]); - */ + * VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", + * from_grid_coordinate.x() - from_grid_width_ofs, + * from_grid_coordinate.y() - from_grid_height_ofs, + * opin, SIDE_STRING[opin_grid_side[0]], + * to_grid_coordinate.x() - to_grid_width_ofs, + * to_grid_coordinate.y() - to_grid_height_ofs, + * ipin, SIDE_STRING[ipin_grid_side[0]]); + */ /* add edges to the opin_node */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 5c9f583658b..f64bde1340a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -191,17 +191,17 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, bool force_end = false; /* All the tracks have to start when - * - the routing channel touch the RIGHT side a heterogeneous block - * - the routing channel touch the LEFT side of FPGA - */ + * - the routing channel touch the RIGHT side a heterogeneous block + * - the routing channel touch the LEFT side of FPGA + */ if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { force_start = true; } /* All the tracks have to end when - * - the routing channel touch the LEFT side a heterogeneous block - * - the routing channel touch the RIGHT side of FPGA - */ + * - the routing channel touch the LEFT side a heterogeneous block + * - the routing channel touch the RIGHT side of FPGA + */ if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { force_end = true; } @@ -243,17 +243,17 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, bool force_end = false; /* All the tracks have to start when - * - the routing channel touch the TOP side a heterogeneous block - * - the routing channel touch the BOTTOM side of FPGA - */ + * - the routing channel touch the TOP side a heterogeneous block + * - the routing channel touch the BOTTOM side of FPGA + */ if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { force_start = true; } /* All the tracks have to end when - * - the routing channel touch the BOTTOM side a heterogeneous block - * - the routing channel touch the TOP side of FPGA - */ + * - the routing channel touch the BOTTOM side a heterogeneous block + * - the routing channel touch the TOP side of FPGA + */ if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { force_end = true; } @@ -280,28 +280,28 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); /** - * 1 Find number of rr nodes related to grids - */ + * 1 Find number of rr nodes related to grids + */ num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); /** - * 2. Assign the segments for each routing channel, - * To be specific, for each routing track, we assign a routing segment. - * The assignment is subject to users' specifications, such as - * a. length of each type of segment - * b. frequency of each type of segment. - * c. routing channel width - * - * SPECIAL for fringes: - * All segments will start and ends with no exception - * - * IMPORTANT: we should be aware that channel width maybe different - * in X-direction and Y-direction channels!!! - * So we will load segment details for different channels - */ + * 2. Assign the segments for each routing channel, + * To be specific, for each routing track, we assign a routing segment. + * The assignment is subject to users' specifications, such as + * a. length of each type of segment + * b. frequency of each type of segment. + * c. routing channel width + * + * SPECIAL for fringes: + * All segments will start and ends with no exception + * + * IMPORTANT: we should be aware that channel width maybe different + * in X-direction and Y-direction channels!!! + * So we will load segment details for different channels + */ num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, chan_width.x(), segment_infs, @@ -361,8 +361,8 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder SideManager io_side_manager(io_side); /* Walk through the width height of each grid, - * get pins and configure the rr_nodes - */ + * get pins and configure the rr_nodes + */ for (int width = 0; width < cur_grid.type->width; ++width) { for (int height = 0; height < cur_grid.type->height; ++height) { /* Walk through sides */ @@ -423,8 +423,8 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder SideManager io_side_manager(io_side); /* Walk through the width and height of each grid, - * get pins and configure the rr_nodes - */ + * get pins and configure the rr_nodes + */ for (int width = 0; width < cur_grid.type->width; ++width) { for (int height = 0; height < cur_grid.type->height; ++height) { /* Walk through sides */ @@ -649,10 +649,10 @@ static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, const std::vector& segment_infs, const int& cost_index_offset) { /* Check each node_id(potential ptc_num) in the channel : - * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num - * If this is a ending point, we set xhigh/yhigh and track_ids - * For other nodes, we set changes in track_ids - */ + * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num + * If this is a ending point, we set xhigh/yhigh and track_ids + * For other nodes, we set changes in track_ids + */ for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { /* For INC direction, a starting point requires a new chan rr_node */ if (((true == chan_details.is_track_start(itrack)) @@ -731,8 +731,8 @@ static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); /* Deposit xhigh and yhigh using the current chan_coordinate - * We will update when this track ends - */ + * We will update when this track ends + */ rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), rr_graph.node_ylow(rr_node_id), chan_coordinate.x(), @@ -777,17 +777,17 @@ static void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, bool force_end = false; /* All the tracks have to start when - * - the routing channel touch the RIGHT side a heterogeneous block - * - the routing channel touch the LEFT side of FPGA - */ + * - the routing channel touch the RIGHT side a heterogeneous block + * - the routing channel touch the LEFT side of FPGA + */ if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { force_start = true; } /* All the tracks have to end when - * - the routing channel touch the LEFT side a heterogeneous block - * - the routing channel touch the RIGHT side of FPGA - */ + * - the routing channel touch the LEFT side a heterogeneous block + * - the routing channel touch the RIGHT side of FPGA + */ if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { force_end = true; } @@ -797,40 +797,40 @@ static void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, /* Force node_ids from the previous chanx */ if (0 < track_node_ids.size()) { /* Rotate should be done based on a typical case of routing tracks. - * Tracks on the borders are not regularly started and ended, - * which causes the node_rotation malfunction - */ + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction + */ ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, false, false, segment_infs); chanx_details_tt.set_track_node_ids(track_node_ids); /* TODO: - * Do NOT rotate the tracks when the routing channel - * locates inside a multi-height and multi-width grid - * Let the routing channel passing through the grid (if through channel is allowed!) - * An example: - * - * +------------------------------ - * | | - * | Grid | - * track0 ----->+-----------------------------+----> track0 - * | | - */ + * Do NOT rotate the tracks when the routing channel + * locates inside a multi-height and multi-width grid + * Let the routing channel passing through the grid (if through channel is allowed!) + * An example: + * + * +------------------------------ + * | | + * | Grid | + * track0 ----->+-----------------------------+----> track0 + * | | + */ if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ /* For INC_DIRECTION, we use clockwise rotation - * node_id A ----> -----> node_id D - * node_id B ----> / ----> node_id A - * node_id C ----> / ----> node_id B - * node_id D ----> ----> node_id C - */ + * node_id A ----> -----> node_id D + * node_id B ----> / ----> node_id A + * node_id C ----> / ----> node_id B + * node_id D ----> ----> node_id C + */ chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); /* For DEC_DIRECTION, we use clockwise rotation - * node_id A <----- <----- node_id B - * node_id B <----- \ <----- node_id C - * node_id C <----- \ <----- node_id D - * node_id D <----- <----- node_id A - */ + * node_id A <----- <----- node_id B + * node_id B <----- \ <----- node_id C + * node_id C <----- \ <----- node_id D + * node_id D <----- <----- node_id A + */ chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); } @@ -884,17 +884,17 @@ static void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, bool force_end = false; /* All the tracks have to start when - * - the routing channel touch the TOP side a heterogeneous block - * - the routing channel touch the BOTTOM side of FPGA - */ + * - the routing channel touch the TOP side a heterogeneous block + * - the routing channel touch the BOTTOM side of FPGA + */ if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { force_start = true; } /* All the tracks have to end when - * - the routing channel touch the BOTTOM side a heterogeneous block - * - the routing channel touch the TOP side of FPGA - */ + * - the routing channel touch the BOTTOM side a heterogeneous block + * - the routing channel touch the TOP side of FPGA + */ if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { force_end = true; } @@ -902,46 +902,46 @@ static void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); /* Force node_ids from the previous chany - * This will not be applied when the routing channel is cut off (force to start) - */ + * This will not be applied when the routing channel is cut off (force to start) + */ if (0 < track_node_ids.size()) { /* Rotate should be done based on a typical case of routing tracks. - * Tracks on the borders are not regularly started and ended, - * which causes the node_rotation malfunction - */ + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction + */ ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, false, false, segment_infs); chany_details_tt.set_track_node_ids(track_node_ids); /* TODO: - * Do NOT rotate the tracks when the routing channel - * locates inside a multi-height and multi-width grid - * Let the routing channel passing through the grid (if through channel is allowed!) - * An example: - * - * +------------------------------ - * | | - * | Grid | - * track0 ----->+-----------------------------+----> track0 - * | | - * we should rotate only once at the bottom side of a grid - */ + * Do NOT rotate the tracks when the routing channel + * locates inside a multi-height and multi-width grid + * Let the routing channel passing through the grid (if through channel is allowed!) + * An example: + * + * +------------------------------ + * | | + * | Grid | + * track0 ----->+-----------------------------+----> track0 + * | | + * we should rotate only once at the bottom side of a grid + */ if (true == is_chany_exist(grids, chany_coord, through_channel)) { /* Rotate the chany_details by an offset of 1*/ /* For INC_DIRECTION, we use clockwise rotation - * node_id A ----> -----> node_id D - * node_id B ----> / ----> node_id A - * node_id C ----> / ----> node_id B - * node_id D ----> ----> node_id C - */ + * node_id A ----> -----> node_id D + * node_id B ----> / ----> node_id A + * node_id C ----> / ----> node_id B + * node_id D ----> ----> node_id C + */ chany_details_tt.rotate_track_node_id(1, Direction::INC, true); /* For DEC_DIRECTION, we use clockwise rotation - * node_id A <----- <----- node_id B - * node_id B <----- \ <----- node_id C - * node_id C <----- \ <----- node_id D - * node_id D <----- <----- node_id A - */ + * node_id A <----- <----- node_id B + * node_id B <----- \ <----- node_id C + * node_id C <----- \ <----- node_id D + * node_id D <----- <----- node_id A + */ chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); } From 3f4a404fe4ee3eebb830aacad2ad417b91f82ca9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 13 Aug 2022 14:11:53 -0700 Subject: [PATCH 009/453] [vpr] add missing files --- vpr/src/tileable_rr_graph/clb2clb_directs.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 vpr/src/tileable_rr_graph/clb2clb_directs.h diff --git a/vpr/src/tileable_rr_graph/clb2clb_directs.h b/vpr/src/tileable_rr_graph/clb2clb_directs.h new file mode 100644 index 00000000000..7cc54bb8813 --- /dev/null +++ b/vpr/src/tileable_rr_graph/clb2clb_directs.h @@ -0,0 +1,16 @@ +#ifndef CLB2CLB_DIRECTS_H +#define CLB2CLB_DIRECTS_H + +#include "physical_types.h" + +struct t_clb_to_clb_directs { + t_physical_tile_type_ptr from_clb_type; + int from_clb_pin_start_index; + int from_clb_pin_end_index; + t_physical_tile_type_ptr to_clb_type; + int to_clb_pin_start_index; + int to_clb_pin_end_index; + int switch_index; //The switch type used by this direct connection +}; + +#endif From 6e2166330b70dc1edca9193b009f807326c905ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 13 Aug 2022 14:20:33 -0700 Subject: [PATCH 010/453] [vpr] add the declaration of common rr_graph building function to header file --- vpr/src/route/rr_graph.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index c1a7a20f25b..0373c3efbd8 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -10,6 +10,7 @@ #include "vpr_types.h" #include "rr_graph_type.h" #include "describe_rr_node.h" +#include "clb2clb_directs.h" /* Warnings about the routing graph that can be returned. * This is to avoid output messages during a value sweep */ @@ -37,6 +38,26 @@ void free_rr_graph(); t_rr_switch_inf create_rr_switch_from_arch_switch(int arch_switch_idx, const float R_minW_nmos, const float R_minW_pmos); + +void alloc_and_load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const int wire_to_arch_ipin_switch, int* wire_to_rr_ipin_switch); + +void rr_graph_externals(const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + int wire_to_rr_ipin_switch, + enum e_base_cost_type base_cost_type); + +t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch); + +std::vector> alloc_and_load_actual_fc(const std::vector& types, + const int max_pins, + const std::vector& segment_inf, + const int* sets_per_seg_type, + const t_chan_width* nodes_per_chan, + const e_fc_type fc_type, + const enum e_directionality directionality, + bool* Fc_clipped); + // Sets the spec for the rr_switch based on the arch switch void load_rr_switch_from_arch_switch(int arch_switch_idx, int rr_switch_idx, From ac554b1ed9d6dbd2afc1310de5e9a4cb471905e1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 13 Aug 2022 16:13:22 -0700 Subject: [PATCH 011/453] [vpr] cleaning up compilation errors --- vpr/src/base/vpr_context.h | 6 ++ .../tileable_rr_graph_builder.cpp | 62 +++---------------- .../tileable_rr_graph_node_builder.cpp | 19 ++++-- .../tileable_rr_graph_node_builder.h | 3 +- 4 files changed, 31 insertions(+), 59 deletions(-) diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 17d0f55a3d5..8e3cb7effc0 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -192,6 +192,12 @@ struct DeviceContext : public Context { * for client functions: GUI, placer, router, timing analyzer etc. */ RRGraphView rr_graph{rr_graph_builder.rr_nodes(), rr_graph_builder.node_lookup(), rr_graph_builder.rr_node_metadata(), rr_graph_builder.rr_edge_metadata(), rr_indexed_data, rr_rc_data, rr_graph_builder.rr_segments(), rr_graph_builder.rr_switch()}; + + /* Track ids for each rr_node in the rr_graph. + * This is used by drawer for tileable routing resource graph + */ + std::map> rr_node_track_ids; + int num_arch_switches; t_arch_switch_inf* arch_switch_inf; // [0..(num_arch_switches-1)] diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index ab759e8a219..2d34082c464 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -132,12 +132,10 @@ void build_tileable_unidir_rr_graph(const std::vector& typ delayless_rr_switch = rr_switch; } } -// NYI -#if 0 + /* Validate the special switches */ - VTR_ASSERT(true == device_ctx.rr_graph.validate_node(wire_to_ipin_rr_switch)); - VTR_ASSERT(true == device_ctx.rr_graph.validate_node(delayless_rr_switch)); -#endif + VTR_ASSERT(true == device_ctx.rr_graph.rr_nodes().validate_node(wire_to_ipin_rr_switch)); + VTR_ASSERT(true == device_ctx.rr_graph.rr_nodes().validate_node(delayless_rr_switch)); /* A temp data about the driver switch ids for each rr_node */ vtr::vector rr_node_driver_switches; @@ -162,6 +160,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ device_ctx.rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, + device_ctx.rr_rc_data, grids, device_chan_width, segment_inf, @@ -262,15 +261,6 @@ void build_tileable_unidir_rr_graph(const std::vector& typ build_rr_graph_direct_connections(device_ctx.rr_graph, device_ctx.rr_graph_builder, device_ctx.grid, delayless_rr_switch, arch_directs, clb2clb_directs); -//NYI -// We may not need to rebuild it again -#if 0 - /* First time to build edges so that we can remap the architecture switch to rr_switch - * This is a must-do before function alloc_and_load_rr_switch_inf() - */ - device_ctx.rr_graph.rebuild_node_edges(); -#endif - /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ alloc_and_load_rr_switch_inf(device_ctx.num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); @@ -278,11 +268,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* Save the channel widths for the newly constructed graph */ device_ctx.chan_width = chan_width; -//NYI -#if 0 - /* Save the track ids for tileable routing resource graph */ - device_ctx.rr_node_track_ids = rr_node_track_ids; -#endif + /* Save the track ids for tileable routing resource graph */ + device_ctx.rr_node_track_ids = rr_node_track_ids; /************************************************************************ * Allocate external data structures @@ -295,25 +282,6 @@ void build_tileable_unidir_rr_graph(const std::vector& typ rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); - /* Rebuild the link between RRGraph node and segments - * Should be called only AFTER the function - * rr_graph_externals() - */ - for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { - if ((CHANX != device_ctx.rr_graph.node_type(inode)) - && (CHANY != device_ctx.rr_graph.node_type(inode))) { - continue; - } -// NYI -#if 0 - RRIndexedDataId irc_data = device_ctx.rr_graph.node_cost_index(inode); - short iseg = device_ctx.rr_indexed_data[irc_data].seg_index; - // device_ctx.rr_graph_builder.set_node_segment(inode, RRSegmentId(iseg)); // NYI - vtr::vector rr_segments = device_ctx.rr_graph_builder.rr_segments(); - rr_segments[(RRSegmentId)iseg] = segment_inf; -#endif - } - /************************************************************************ * Sanitizer for the rr_graph, check connectivities of rr_nodes ***********************************************************************/ @@ -326,22 +294,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ "Fundamental errors occurred when validating rr_graph object!\n"); } - check_rr_graph(GRAPH_UNIDIR, grids, types); - - // NYI - // vpr integration: DeviceContext does not provide direct RRGraph access - // for advanced rr graph checker in check_rr_graph_obj.h, needs rr graph object - // rr graph view won't work here -#if 0 - /* Error out if advanced checker of rr_graph fails */ - if (false == check_rr_graph(device_ctx.rr_graph)) { - vpr_throw(VPR_ERROR_ROUTE, - __FILE__, - __LINE__, - "Advanced checking rr_graph object fails! Routing may still work " - "but not smooth\n"); - } -#endif + /* No clock network support yet */ + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, device_ctx.chan_width, GRAPH_UNIDIR, OPEN); /************************************************************************ * Free all temp stucts diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index f64bde1340a..17054fc5d28 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -354,6 +354,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, ***********************************************************************/ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, const vtr::Point& grid_coordinate, const t_grid_tile& cur_grid, const e_side& io_side, @@ -399,7 +400,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_node_driver_switches.push_back(delayless_switch); /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } /* End of loading OPIN rr_nodes */ } /* End of side enumeration */ @@ -416,6 +417,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder ***********************************************************************/ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, const vtr::Point& grid_coordinate, const t_grid_tile& cur_grid, const e_side& io_side, @@ -461,7 +463,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_node_driver_switches.push_back(wire_to_ipin_switch); /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } /* End of loading IPIN rr_nodes */ } /* End of side enumeration */ @@ -478,6 +480,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder ***********************************************************************/ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, const vtr::Point& grid_coordinate, const t_grid_tile& cur_grid, const e_side& io_side, @@ -514,7 +517,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build rr_node_driver_switches.push_back(delayless_switch); /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } /* End of class enumeration */ } @@ -528,6 +531,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build ***********************************************************************/ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, const vtr::Point& grid_coordinate, const t_grid_tile& cur_grid, const e_side& io_side, @@ -564,7 +568,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_node_driver_switches.push_back(delayless_switch); /* RC data */ - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0.))); + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } /* End of class enumeration */ } @@ -574,6 +578,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder ***********************************************************************/ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, const DeviceGrid& grids, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch) { @@ -602,6 +607,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, /* Configure source rr_nodes for this grid */ load_one_grid_source_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, + rr_rc_data, grid_coordinate, grids[ix][iy], io_side, @@ -610,6 +616,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, /* Configure sink rr_nodes for this grid */ load_one_grid_sink_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, + rr_rc_data, grid_coordinate, grids[ix][iy], io_side, @@ -618,6 +625,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, /* Configure opin rr_nodes for this grid */ load_one_grid_opin_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, + rr_rc_data, grid_coordinate, grids[ix][iy], io_side, @@ -626,6 +634,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, /* Configure ipin rr_nodes for this grid */ load_one_grid_ipin_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, + rr_rc_data, grid_coordinate, grids[ix][iy], io_side, @@ -1001,6 +1010,7 @@ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, + std::vector& rr_rc_data, const DeviceGrid& grids, const vtr::Point& chan_width, const std::vector& segment_infs, @@ -1009,6 +1019,7 @@ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, const bool& through_channel) { load_grid_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, + rr_rc_data, grids, wire_to_ipin_switch, delayless_switch); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index cb8839018a7..116f51e3a89 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -11,8 +11,8 @@ #include "physical_types.h" /* Headers from vpr library */ -#include "rr_graph_obj.h" #include "device_grid.h" +#include "rr_node_types.h" #include "rr_graph_view.h" #include "rr_graph_builder.h" @@ -31,6 +31,7 @@ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, + std::vector& rr_rc_data, const DeviceGrid& grids, const vtr::Point& chan_width, const std::vector& segment_infs, From 7490a21bc70ae43d826cc66f19468415a51b451b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 13 Aug 2022 17:24:02 -0700 Subject: [PATCH 012/453] [vpr] adapting API in tileable rr_graph builder --- libs/librrgraph/src/base/rr_graph_view.h | 7 +++- .../tileable_rr_graph_builder.cpp | 4 +-- .../tileable_rr_graph_node_builder.cpp | 34 ++++++++----------- 3 files changed, 22 insertions(+), 23 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 6d0c995864b..ffea6084e18 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -462,7 +462,7 @@ class RRGraphView { } public: /* Validators */ - /** brief Validate that edge data is partitioned correctly + /** @brief Validate that edge data is partitioned correctly * @note This function is used to validate the correctness of the routing resource graph in terms * of graph attributes. Strongly recommend to call it when you finish the building a routing resource * graph. If you need more advance checks, which are related to architecture features, you should @@ -471,6 +471,11 @@ class RRGraphView { return node_storage_.validate_node(node_id, rr_switch_inf_); } + /** @brief Check if the switch is a valid one in storage */ + inline bool valid_switch(RRSwitchId switch_id) const { + return (size_t(switch_id) < rr_switch_inf_.size()); + } + /* -- Internal data storage -- */ /* Note: only read-only object or data structures are allowed!!! */ private: diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 2d34082c464..cd8c5aa2f83 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -134,8 +134,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } /* Validate the special switches */ - VTR_ASSERT(true == device_ctx.rr_graph.rr_nodes().validate_node(wire_to_ipin_rr_switch)); - VTR_ASSERT(true == device_ctx.rr_graph.rr_nodes().validate_node(delayless_rr_switch)); + VTR_ASSERT(true == device_ctx.rr_graph.valid_switch(wire_to_ipin_rr_switch)); + VTR_ASSERT(true == device_ctx.rr_graph.valid_switch(delayless_rr_switch)); /* A temp data about the driver switch ids for each rr_node */ vtr::vector rr_node_driver_switches; diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 17054fc5d28..9662cb52bcd 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -979,28 +979,22 @@ static void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, * However, DEC direction routing tracks should have a reversed sequence in * track ids ***********************************************************************/ -static void reverse_dec_chan_rr_node_track_ids(const RRGraphBuilder& rr_graph_builder, +static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, std::map>& rr_node_track_ids) { - // NYI - // unused parameters - (void)(rr_graph_builder); - (void)(rr_node_track_ids); -#if 0 // this should call rr_graph_builder to do the job - for (const RRNodeId& node : rr_graph_builder.nodes()) { - /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ - if ( (CHANX != rr_graph_builder.node_type(node)) - && (CHANY != rr_graph_builder.node_type(node)) ) { - continue; - } - /* Reach here, we must have a node of CHANX or CHANY */ - if (Direction::DEC != rr_graph_builder.node_direction(node)) { - continue; + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ + if ( (CHANX != rr_graph.node_type(node)) + && (CHANY != rr_graph.node_type(node)) ) { + continue; + } + /* Reach here, we must have a node of CHANX or CHANY */ + if (Direction::DEC != rr_graph.node_direction(node)) { + continue; + } + std::reverse(rr_node_track_ids[node].begin(), + rr_node_track_ids[node].end() ); } - std::reverse(rr_node_track_ids[node].begin(), - rr_node_track_ids[node].end() ); - } -#endif } /************************************************************************ @@ -1042,6 +1036,6 @@ void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, segment_infs, through_channel); - reverse_dec_chan_rr_node_track_ids(rr_graph_builder, + reverse_dec_chan_rr_node_track_ids(rr_graph, rr_node_track_ids); } From e4fa74700ff37747ff27eaec7b4812a30d3cd950 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 13 Aug 2022 17:53:18 -0700 Subject: [PATCH 013/453] [vpr] adapting apis in tileable rr_graph builder --- .../tileable_rr_graph_edge_builder.cpp | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index c261af8f655..ea031c0467e 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -68,14 +68,10 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, short sink_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], rr_graph.node_pin_num(node)); /* 1. create edges between IPINs and SINKs */ - // NYI - (void)(sink_node_class_num); -#if 0 - const RRNodeId& sink_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset, - ylow - grids[xlow][ylow].height_offset, - SINK, sink_node_class_num); - VTR_ASSERT(true == rr_graph.valid_node_id(sink_node)); -#endif + const RRNodeId& sink_node = rr_graph.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, + ylow - grids[xlow][ylow].height_offset, + SINK, sink_node_class_num); + VTR_ASSERT(true == rr_graph.validate_node(sink_node)); // NYI (void)(rr_node_driver_switches); From 11015885c2060dcd02cc2b22f07fedf5e6fbee75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 13 Aug 2022 20:02:47 -0700 Subject: [PATCH 014/453] [vpr] enrich error message in rr_gsb --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index d1b6f7e4a18..f02d2ef4be5 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -446,13 +446,11 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, * we should be able to find the node on the opposite side of the GSB! */ if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) { - VTR_LOG("GSB[%lu][%lu] track node[%lu] at %s:\n", + VTR_LOG("Cannot find a node on the opposite side to GSB[%lu][%lu] track node[%lu] at %s!\nDetailed node information:\n", get_x(), get_y(), track_id, SIDE_STRING[node_side]); - -// NYI -#if 0 - rr_graph.print_node(track_node); -#endif + VTR_LOG("Node type: %s\n", rr_graph.node_type_string(track_node)); + VTR_LOG("Node coordinate: %d\n", rr_graph.node_coordinate_to_string(track_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(track_node)); } VTR_ASSERT(true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)); From 2bbb7f2417ba22780aaa781fa7b0086e8e125b96 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 14 Aug 2022 10:49:06 -0700 Subject: [PATCH 015/453] [vpr] integrating edge builder to rrgraph builder --- libs/librrgraph/src/base/rr_graph_builder.cpp | 12 ++++++ libs/librrgraph/src/base/rr_graph_builder.h | 22 +++++++++- .../tileable_rr_graph_edge_builder.cpp | 14 +++---- .../tileable_rr_graph_gsb.cpp | 41 ++++--------------- 4 files changed, 44 insertions(+), 45 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 535e027ca9f..88ed3e042e4 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -66,6 +66,7 @@ void RRGraphBuilder::clear() { rr_edge_metadata_.clear(); rr_segments_.clear(); rr_switch_inf_.clear(); + edges_to_build_.clear(); } void RRGraphBuilder::reorder_nodes(e_rr_node_reorder_algorithm reorder_rr_graph_nodes_algorithm, @@ -137,3 +138,14 @@ void RRGraphBuilder::reorder_nodes(e_rr_node_reorder_algorithm reorder_rr_graph_ std::get<2>(edge)); }); } + +void RRGraphBuilder::create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch) { + edges_to_build_.emplace_back(src, dest, size_t(edge_switch)); +} + +void RRGraphBuilder::build_edges() { + std::sort(edges_to_build_.begin(), edges_to_build_.end()); + edges_to_build_.erase(std::unique(edges_to_build_.begin(), edges_to_build_.end()), edges_to_build_.end()); + alloc_and_load_edges(&edges_to_build_); + edges_to_build_.clear(); +} diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index df3018e928a..000ee750fbd 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -16,6 +16,7 @@ #include "rr_graph_storage.h" #include "rr_spatial_lookup.h" #include "metadata_storage.h" +#include "rr_edge.h" class RRGraphBuilder { /* -- Constructors -- */ @@ -200,6 +201,15 @@ class RRGraphBuilder { node_storage_.set_node_direction(id, new_direction); } + /** @brief Add a new edge to the cache of edges to be built + * .. note:: This will not add an edge to storage! You need to call build_edges() after all the edges are cached! */ + void create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch); + + /** @brief Allocate and build actual edges in storage. + * Once called, the cached edges will be uniquified and added to routing resource nodes, + * while the cache will be empty once build-up is accomplished */ + void build_edges(); + /** @brief Reserve the lists of edges to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, * when adding a large number of edges in order to avoid memory fragements */ @@ -285,13 +295,13 @@ class RRGraphBuilder { rr_switch_inf_.resize(size); } - /** @brief Validate that edge data is partitioned correctly + /** @brief Validate that edge data is partitioned correctly. Also there are no edges left to be built! * @note This function is used to validate the correctness of the routing resource graph in terms * of graph attributes. Strongly recommend to call it when you finish the building a routing resource * graph. If you need more advance checks, which are related to architecture features, you should * consider to use the check_rr_graph() function or build your own check_rr_graph() function. */ inline bool validate() const { - return node_storage_.validate(rr_switch_inf_); + return node_storage_.validate(rr_switch_inf_) && edges_to_build_.empty(); } /** @brief Sorts edge data such that configurable edges appears before @@ -325,6 +335,14 @@ class RRGraphBuilder { /* Fast look-up for rr nodes */ RRSpatialLookup node_lookup_; + /* A cache for edge-related information, required to build edges for routing resource nodes. + * It is used when building a routing resource graph by considering memory efficiency. + * It will be clear up after calling build_edges(). + * + * .. warning:: This is a temporary data which is used to collect edges to be built for nodes + */ + t_rr_edge_info_set edges_to_build_; + /** Wire segment types in RR graph * - Each rr_segment contains the detailed information of a routing track, which is denoted by a node in CHANX or CHANY type. * - We use a fly-weight data structure here, in the same philosophy as the rr_indexed_data. See detailed explanation in the t_segment_inf data structure diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index ea031c0467e..317cafca793 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -40,13 +40,11 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, SOURCE, src_node_class_num); VTR_ASSERT(true == rr_graph.validate_node(src_node)); - // NYI - (void)(rr_node_driver_switches); -#if 0 /* add edges to the src_node */ rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node]); -#endif } + /* Allocate edges for all the source nodes */ + rr_graph_builder.build_edges(); } /************************************************************************ @@ -73,14 +71,11 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, SINK, sink_node_class_num); VTR_ASSERT(true == rr_graph.validate_node(sink_node)); - // NYI - (void)(rr_node_driver_switches); - (void)(rr_graph_builder); -#if 0 /* add edges to connect the IPIN node to SINK nodes */ rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); -#endif } + /* Allocate edges for all the source nodes */ + rr_graph_builder.build_edges(); } /************************************************************************ @@ -142,6 +137,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, track2ipin_map, opin2track_map, sb_conn, rr_node_driver_switches); /* Finish this GSB, go to the next*/ + rr_graph_builder.build_edges(); } } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 978341a7399..cad2574d51a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -917,15 +917,6 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, const vtr::vector& rr_node_driver_switches) { - // NYI - // unused parameters - (void)(rr_graph_builder); - (void)(rr_gsb); - (void)(track2ipin_map); - (void)(opin2track_map); - (void)(track2track_map); - (void)(rr_node_driver_switches); -#if 0 /* Walk through each sides */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager side_manager(side); @@ -965,7 +956,6 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, } } } -#endif } /************************************************************************ @@ -1416,23 +1406,12 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, std::vector ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin); VTR_ASSERT(1 == ipin_grid_side.size()); - // NYI - // unused parameters - (void)(rr_graph); - (void)(rr_graph_builder); - // unused variables - (void)(from_grid_width_ofs); - (void)(from_grid_height_ofs); - (void)(to_grid_width_ofs); - (void)(to_grid_height_ofs); -#if 0 - const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs, - from_grid_coordinate.y() - from_grid_height_ofs, - OPIN, opin, opin_grid_side[0]); - const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs, - to_grid_coordinate.y() - to_grid_height_ofs, - IPIN, ipin, ipin_grid_side[0]); -#endif + const RRNodeId& opin_node_id = rr_graph.node_lookup().find_node(from_grid_coordinate.x() - from_grid_width_ofs, + from_grid_coordinate.y() - from_grid_height_ofs, + OPIN, opin, opin_grid_side[0]); + const RRNodeId& ipin_node_id = rr_graph.node_lookup().find_node(to_grid_coordinate.x() - to_grid_width_ofs, + to_grid_coordinate.y() - to_grid_height_ofs, + IPIN, ipin, ipin_grid_side[0]); /* * VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", * from_grid_coordinate.x() - from_grid_width_ofs, @@ -1445,13 +1424,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, /* add edges to the opin_node */ - // NYI - // unused parameters - (void)(delayless_switch); -#if 0 - rr_graph_builder.create_edge(opin_node_id, ipin_node_id, - delayless_switch); -#endif + rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch); } } } From 4d46b4761ee727d43ff3805cdf47b1b134f5cd85 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 14 Aug 2022 12:34:28 -0700 Subject: [PATCH 016/453] [vpr] syntax error --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index cad2574d51a..52c9ab56d2c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -952,7 +952,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { - rr_graph.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]); + rr_graph_builder.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]); } } } From 3ecee3e522d21b97f713c9a97ef15d00271ebe05 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 14 Aug 2022 13:08:14 -0700 Subject: [PATCH 017/453] [vpr] rename header file --- .../{rr_graph_obj_util.cpp => rr_graph_view_util.cpp} | 3 +-- .../{rr_graph_obj_util.h => rr_graph_view_util.h} | 5 ++--- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) rename vpr/src/tileable_rr_graph/{rr_graph_obj_util.cpp => rr_graph_view_util.cpp} (98%) rename vpr/src/tileable_rr_graph/{rr_graph_obj_util.h => rr_graph_view_util.h} (94%) diff --git a/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp similarity index 98% rename from vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp rename to vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index d389ab757e4..637c926872e 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_obj_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -2,8 +2,7 @@ * This file include most-utilized functions that manipulate on the * RRGraph object ***************************************************************************/ -#include "rr_graph_obj.h" -#include "rr_graph_obj_util.h" +#include "rr_graph_view_util.h" /**************************************************************************** * Find the switches interconnecting two nodes diff --git a/vpr/src/tileable_rr_graph/rr_graph_obj_util.h b/vpr/src/tileable_rr_graph/rr_graph_view_util.h similarity index 94% rename from vpr/src/tileable_rr_graph/rr_graph_obj_util.h rename to vpr/src/tileable_rr_graph/rr_graph_view_util.h index f32957e43c2..0834f34ef22 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_obj_util.h +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.h @@ -1,11 +1,10 @@ -#ifndef RR_GRAPH_OBJ_UTIL_H -#define RR_GRAPH_OBJ_UTIL_H +#ifndef RR_GRAPH_VIEW_UTIL_H +#define RR_GRAPH_VIEW_UTIL_H /* Include header files which include data structures used by * the function declaration */ #include -#include "rr_graph_obj.h" #include "device_grid.h" #include "rr_graph_view.h" diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 52c9ab56d2c..2df3a759286 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -14,7 +14,7 @@ #include "openfpga_side_manager.h" #include "vpr_utils.h" -#include "rr_graph_obj_util.h" +#include "rr_graph_view_util.h" #include "openfpga_rr_graph_utils.h" #include "rr_graph_builder_utils.h" #include "tileable_chan_details_builder.h" From 2b71a2cb1cd5d423ed5ed227e836c90079e4257c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 14 Aug 2022 14:33:16 -0700 Subject: [PATCH 018/453] [vpr] add api for node_in_edges --- libs/librrgraph/src/base/rr_graph_builder.cpp | 36 ++++++++++++++++++- libs/librrgraph/src/base/rr_graph_builder.h | 18 ++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 88ed3e042e4..baf353322bf 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -7,7 +7,10 @@ //#include "globals.h" -RRGraphBuilder::RRGraphBuilder() {} +RRGraphBuilder::RRGraphBuilder() { + is_edge_dirty_ = true; + is_incoming_edge_dirty_ = true; +} t_rr_graph_storage& RRGraphBuilder::rr_nodes() { return node_storage_; @@ -67,6 +70,8 @@ void RRGraphBuilder::clear() { rr_segments_.clear(); rr_switch_inf_.clear(); edges_to_build_.clear(); + is_edge_dirty_ = true; + is_incoming_edge_dirty_ = true; } void RRGraphBuilder::reorder_nodes(e_rr_node_reorder_algorithm reorder_rr_graph_nodes_algorithm, @@ -141,6 +146,8 @@ void RRGraphBuilder::reorder_nodes(e_rr_node_reorder_algorithm reorder_rr_graph_ void RRGraphBuilder::create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch) { edges_to_build_.emplace_back(src, dest, size_t(edge_switch)); + is_edge_dirty_ = true; /* Adding a new edge revokes the flag */ + is_incoming_edge_dirty_ = true; } void RRGraphBuilder::build_edges() { @@ -148,4 +155,31 @@ void RRGraphBuilder::build_edges() { edges_to_build_.erase(std::unique(edges_to_build_.begin(), edges_to_build_.end()), edges_to_build_.end()); alloc_and_load_edges(&edges_to_build_); edges_to_build_.clear(); + is_edge_dirty_ = false; +} + +void RRGraphBuilder::build_in_edges() { + VTR_ASSERT(validate()); + node_in_edges_.clear(); + node_in_edges_.resize(node_storage_.size()); + + for (const RRNodeId& src_node: vtr::StrongIdRange(RRNodeId(0), RRNodeId(node_storage_.size()))) { + for (size_t iedge = size_t(node_storage_.first_edge(src_node)); iedge < size_t(node_storage_.last_edge(src_node)); iedge++) { + RRNodeId des_node = node_storage_.edge_sink_node(RREdgeId(iedge)); + node_in_edges_[des_node].push_back(RREdgeId(iedge)); + } + } + is_incoming_edge_dirty_ = false; +} + +std::vector RRGraphBuilder::node_in_edges(RRNodeId node) { + VTR_ASSERT(size_t(node) < node_storage_.size()); + if (is_incoming_edge_dirty_) { + VTR_LOG_ERROR("Incoming edges are built yet in routing resource graph. Please call build_in_edges()."); + return std::vector(); + } + if (node_in_edges_.empty()) { + return std::vector(); + } + return node_in_edges_[node]; } diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 000ee750fbd..3c3b845cabb 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -210,6 +210,15 @@ class RRGraphBuilder { * while the cache will be empty once build-up is accomplished */ void build_edges(); + /** @brief Allocate and build incoming edges for each node. + * By default, no incoming edges are kept in storage, to be memory efficient */ + void build_in_edges(); + + /** @brief Return incoming edges for a given routing resource node + * Require build_in_edges() to be called first + */ + std::vector node_in_edges(RRNodeId node); + /** @brief Reserve the lists of edges to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, * when adding a large number of edges in order to avoid memory fragements */ @@ -357,6 +366,10 @@ class RRGraphBuilder { /* Detailed information about the switches, which are used in the RRGraph */ vtr::vector rr_switch_inf_; + /** A list of incoming edges for each routing resource node. This can be built optionally, as required by applications. + * By default, it is empty! Call build_in_edges() to construct it!!! */ + vtr::vector> node_in_edges_; + /** .. warning:: The Metadata should stay as an independent data structure than rest of the internal data, * e.g., node_lookup! */ /* Metadata is an extra data on rr-nodes and edges, respectively, that is not used by vpr @@ -381,6 +394,11 @@ class RRGraphBuilder { * value: map of */ MetadataStorage> rr_edge_metadata_; + + /** @brief a flag to mark the status of edge storage + * dirty means that the edge storage is not complete, should call related APIs to build */ + bool is_edge_dirty_; + bool is_incoming_edge_dirty_; }; #endif From bef7983cd3f9047f0075053c61fa520d9f658c7f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 14 Aug 2022 15:30:06 -0700 Subject: [PATCH 019/453] [vpr] added APIs for node_in_edges and adapt tileable rr graph generator --- libs/librrgraph/src/base/rr_graph_builder.cpp | 6 ++- libs/librrgraph/src/base/rr_graph_builder.h | 4 +- libs/librrgraph/src/base/rr_graph_storage.cpp | 5 +++ libs/librrgraph/src/base/rr_graph_storage.h | 1 + libs/librrgraph/src/base/rr_graph_view.cpp | 14 ++++++- libs/librrgraph/src/base/rr_graph_view.h | 31 +++++++++++++- vpr/src/base/vpr_context.h | 2 +- .../openfpga_rr_graph_utils.cpp | 42 +------------------ .../tileable_rr_graph/rr_graph_view_util.cpp | 20 ++------- vpr/src/tileable_rr_graph/rr_gsb.cpp | 33 +++------------ 10 files changed, 68 insertions(+), 90 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index baf353322bf..9523000dc83 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -28,6 +28,10 @@ MetadataStorage>& RRGraphBuilder::rr_edge_metadata() return rr_edge_metadata_; } +vtr::vector> RRGraphBuilder::node_in_edge_storage() { + return node_in_edges_; +} + void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { t_rr_type node_type = node_storage_.node_type(node); short node_ptc_num = node_storage_.node_ptc_num(node); @@ -172,7 +176,7 @@ void RRGraphBuilder::build_in_edges() { is_incoming_edge_dirty_ = false; } -std::vector RRGraphBuilder::node_in_edges(RRNodeId node) { +std::vector RRGraphBuilder::node_in_edges(RRNodeId node) const { VTR_ASSERT(size_t(node) < node_storage_.size()); if (is_incoming_edge_dirty_) { VTR_LOG_ERROR("Incoming edges are built yet in routing resource graph. Please call build_in_edges()."); diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 3c3b845cabb..a036fea7866 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -45,6 +45,8 @@ class RRGraphBuilder { MetadataStorage& rr_node_metadata(); /** @brief Return a writable object for the meta data on the edge */ MetadataStorage>& rr_edge_metadata(); + /** @brief Return a writable object fo the incoming edge storage */ + vtr::vector> node_in_edge_storage(); /** @brief Return the size for rr_node_metadata */ inline size_t rr_node_metadata_size() const { @@ -217,7 +219,7 @@ class RRGraphBuilder { /** @brief Return incoming edges for a given routing resource node * Require build_in_edges() to be called first */ - std::vector node_in_edges(RRNodeId node); + std::vector node_in_edges(RRNodeId node) const; /** @brief Reserve the lists of edges to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index dbf6fdb2e2a..5e85557499d 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -531,6 +531,11 @@ t_edge_size t_rr_graph_storage::num_non_configurable_edges(RRNodeId node, const return num_edges(node) - num_configurable_edges(node, rr_switches); } +bool t_rr_graph_storage::edge_is_configurable(RREdgeId edge, const vtr::vector& rr_switches) const { + auto iswitch = edge_switch(edge); + return rr_switches[RRSwitchId(iswitch)].configurable(); +} + bool t_rr_graph_storage::edge_is_configurable(RRNodeId id, t_edge_size iedge, const vtr::vector& rr_switches) const { auto iswitch = edge_switch(id, iedge); return rr_switches[RRSwitchId(iswitch)].configurable(); diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index a23ce92c67d..20d791c9596 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -270,6 +270,7 @@ class t_rr_graph_storage { t_edge_size num_edges(const RRNodeId& id) const { return size_t(last_edge(id)) - size_t(first_edge(id)); } + bool edge_is_configurable(RREdgeId edge, const vtr::vector& rr_switches) const; bool edge_is_configurable(RRNodeId id, t_edge_size iedge, const vtr::vector& rr_switches) const; t_edge_size num_configurable_edges(RRNodeId node, const vtr::vector& rr_switches) const; t_edge_size num_non_configurable_edges(RRNodeId node, const vtr::vector& rr_switches) const; diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index 0ddc5445d42..eccac8b7f05 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -9,7 +9,8 @@ RRGraphView::RRGraphView(const t_rr_graph_storage& node_storage, const vtr::vector& rr_indexed_data, const std::vector& rr_rc_data, const vtr::vector& rr_segments, - const vtr::vector& rr_switch_inf) + const vtr::vector& rr_switch_inf, + const vtr::vector>& node_in_edges) : node_storage_(node_storage) , node_lookup_(node_lookup) , rr_node_metadata_(rr_node_metadata) @@ -17,5 +18,14 @@ RRGraphView::RRGraphView(const t_rr_graph_storage& node_storage, , rr_indexed_data_(rr_indexed_data) , rr_rc_data_(rr_rc_data) , rr_segments_(rr_segments) - , rr_switch_inf_(rr_switch_inf) { + , rr_switch_inf_(rr_switch_inf) + , node_in_edges_(node_in_edges) { +} + +std::vector RRGraphView::node_in_edges(RRNodeId node) const { + VTR_ASSERT(size_t(node) < node_storage_.size()); + if (node_in_edges_.empty()) { + return std::vector(); + } + return node_in_edges_[node]; } diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index ffea6084e18..1719751da08 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -42,7 +42,8 @@ class RRGraphView { const vtr::vector& rr_indexed_data, const std::vector& rr_rc_data, const vtr::vector& rr_segments, - const vtr::vector& rr_switch_inf); + const vtr::vector& rr_switch_inf, + const vtr::vector>& node_in_edges); /* Disable copy constructors and copy assignment operator * This is to avoid accidental copy because it could be an expensive operation considering that the @@ -300,12 +301,24 @@ class RRGraphView { inline short edge_switch(RRNodeId id, t_edge_size iedge) const { return node_storage_.edge_switch(id, iedge); } + inline RRSwitchId edge_switch(RREdgeId edge) const { + return RRSwitchId(node_storage_.edge_switch(edge)); + } + /** @brief Get the source node for the iedge'th edge from specified RRNodeId. + * This method should generally not be used, and instead first_edge and + * last_edge should be used.*/ + inline RRNodeId edge_src_node(RREdgeId edge) const { + return node_storage_.edge_source_node(edge); + } /** @brief Get the destination node for the iedge'th edge from specified RRNodeId. * This method should generally not be used, and instead first_edge and * last_edge should be used.*/ inline RRNodeId edge_sink_node(RRNodeId id, t_edge_size iedge) const { return node_storage_.edge_sink_node(id, iedge); } + inline RRNodeId edge_sink_node(RREdgeId edge) const { + return node_storage_.edge_sink_node(edge); + } /** @brief Get the source node for the iedge'th edge from specified RRNodeId. * This method should generally not be used, and instead first_edge and @@ -318,6 +331,9 @@ class RRGraphView { inline bool edge_is_configurable(RRNodeId id, t_edge_size iedge) const { return node_storage_.edge_is_configurable(id, iedge, rr_switch_inf_); } + inline bool edge_is_configurable(RREdgeId edge) const { + return node_storage_.edge_is_configurable(edge, rr_switch_inf_); + } /** @brief Get the number of configurable edges. This function is inlined for runtime optimization. */ inline t_edge_size num_configurable_edges(RRNodeId node) const { @@ -358,6 +374,9 @@ class RRGraphView { inline edge_idx_range edges(const RRNodeId& id) const { return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(num_edges(id))); } + inline edge_idx_range node_out_edges(const RRNodeId& id) const { + return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(num_edges(id))); + } /** @brief Get the number of edges. This function is inlined for runtime optimization. */ inline t_edge_size num_edges(RRNodeId node) const { @@ -399,6 +418,12 @@ class RRGraphView { RRIndexedDataId node_cost_index(RRNodeId node) const { return node_storage_.node_cost_index(node); } + + /** @brief Return incoming edges for a given routing resource node + * Require build_in_edges() to be called first + */ + std::vector node_in_edges(RRNodeId node) const; + /** @brief Return detailed routing segment information with a given id* @note The routing segments here may not be exactly same as those defined in architecture file. They have been * adapted to fit the context of routing resource graphs. */ @@ -517,6 +542,10 @@ class RRGraphView { const vtr::vector& rr_segments_; /* switch info for rr nodes */ const vtr::vector& rr_switch_inf_; + + /** A list of incoming edges for each routing resource node. This can be built optionally, as required by applications. + * By default, it is empty! Call build_in_edges() to construct it!!! */ + const vtr::vector>& node_in_edges_; }; #endif diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 8e3cb7effc0..25dc0687fcb 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -191,7 +191,7 @@ struct DeviceContext : public Context { /* A read-only view of routing resource graph to be the ONLY database * for client functions: GUI, placer, router, timing analyzer etc. */ - RRGraphView rr_graph{rr_graph_builder.rr_nodes(), rr_graph_builder.node_lookup(), rr_graph_builder.rr_node_metadata(), rr_graph_builder.rr_edge_metadata(), rr_indexed_data, rr_rc_data, rr_graph_builder.rr_segments(), rr_graph_builder.rr_switch()}; + RRGraphView rr_graph{rr_graph_builder.rr_nodes(), rr_graph_builder.node_lookup(), rr_graph_builder.rr_node_metadata(), rr_graph_builder.rr_edge_metadata(), rr_indexed_data, rr_rc_data, rr_graph_builder.rr_segments(), rr_graph_builder.rr_switch(), rr_graph_builder.node_in_edge_storage()}; /* Track ids for each rr_node in the rr_graph. * This is used by drawer for tileable routing resource graph diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index 47809f9da8f..0855c082691 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -73,17 +73,11 @@ std::vector get_rr_graph_driver_switches(const RRGraphView& rr_graph const RRNodeId& node) { std::vector driver_switches; - // NYI - // unused argements - (void)(rr_graph); - (void)(node); -#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) { driver_switches.push_back(rr_graph.edge_switch(edge)); } } -#endif return driver_switches; } @@ -95,15 +89,9 @@ std::vector get_rr_graph_driver_nodes(const RRGraphView& rr_graph, const RRNodeId& node) { std::vector driver_nodes; - // NYI - // unused argements - (void)(rr_graph); - (void)(node); -#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { driver_nodes.push_back(rr_graph.edge_src_node(edge)); } -#endif return driver_nodes; } @@ -115,13 +103,6 @@ std::vector get_rr_graph_configurable_driver_nodes(const RRGraphView& const RRNodeId& node) { std::vector driver_nodes; - // NYI - // unused argements - (void)(rr_graph); - (void)(node); -#if 0 - (void)(rr_graph); - (void)(node); for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { /* Bypass non-configurable edges */ if (false == rr_graph.edge_is_configurable(edge)) { @@ -129,7 +110,6 @@ std::vector get_rr_graph_configurable_driver_nodes(const RRGraphView& } driver_nodes.push_back(rr_graph.edge_src_node(edge)); } -#endif return driver_nodes; } @@ -141,11 +121,6 @@ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphVi const RRNodeId& node) { std::vector driver_nodes; - // NYI - // unused argements - (void)(rr_graph); - (void)(node); -#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { /* Bypass configurable edges */ if (true == rr_graph.edge_is_configurable(edge)) { @@ -153,7 +128,6 @@ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphVi } driver_nodes.push_back(rr_graph.edge_src_node(edge)); } -#endif return driver_nodes; } @@ -169,23 +143,17 @@ bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, /* We only accept OPIN */ VTR_ASSERT(OPIN == rr_graph.node_type(node)); - // NYI - // unused argements - (void)(rr_graph); - (void)(node); -#if 0 if (1 != rr_graph.node_out_edges(node).size()) { return false; } VTR_ASSERT(1 == rr_graph.node_out_edges(node).size()); - for (const RREdgeId& edge : rr_graph.node_out_edges(node)) { - const RRNodeId& sink_node = rr_graph.edge_sink_node(edge); + for (auto edge : rr_graph.node_out_edges(node)) { + const RRNodeId& sink_node = rr_graph.edge_sink_node(RREdgeId(edge)); if (IPIN != rr_graph.node_type(sink_node)) { return false; } } -#endif return true; } @@ -201,11 +169,6 @@ bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, /* We only accept IPIN */ VTR_ASSERT(IPIN == rr_graph.node_type(node)); - // NYI - // unused argements - (void)(rr_graph); - (void)(node); -#if 0 if (1 != rr_graph.node_in_edges(node).size()) { return false; } @@ -217,7 +180,6 @@ bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, return false; } } -#endif return true; } diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 637c926872e..4c3a55144ef 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -48,19 +48,11 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, const int& ptc) { std::vector indices; - // NYI - // unused parameters - (void)(rr_graph); - (void)(x); - (void)(y); - (void)(rr_type); - (void)(ptc); -#if 0 if (rr_type == IPIN || rr_type == OPIN) { //For pins we need to look at all the sides of the current grid tile for (e_side side : SIDES) { - RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, ptc, side); + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(x, y, rr_type, ptc, side); if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); @@ -68,13 +60,12 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, } } else { //Sides do not effect non-pins so there should only be one per ptc - RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, ptc); + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(x, y, rr_type, ptc); if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); } } -#endif return indices; } @@ -140,16 +131,11 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, continue; } - // NYI - // unused parameter - (void)(rr_graph); -#if 0 /* Try to find the rr node */ - RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, pin, side); + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(x, y, rr_type, pin, side); if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); } -#endif } return indices; diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index f02d2ef4be5..4aa7b8e4352 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -158,14 +158,9 @@ std::vector RRGSB::get_chan_node_in_edges(const RRGraphView& rr_graph, if (0 == chan_node_in_edges_.size()) { std::vector unsorted_edges; - // NYI - // unused parameter - (void)(rr_graph); -#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(get_chan_node(side, track_id))) { unsorted_edges.push_back(edge); } -#endif return unsorted_edges; } @@ -819,13 +814,6 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, * For each side, the edge from grid pins will be the 1st part * while the edge from routing tracks will be the 2nd part */ - - // NYI - // unused parameter - (void)(rr_graph); - // unused variable - (void)(chan_node); -#if 0 for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) { /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); @@ -837,9 +825,13 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, if (NUM_SIDES == side) { VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG("SRC node:\n"); - rr_graph.print_node(src_node); + VTR_LOG("Node type: %s\n", rr_graph.node_type_string(src_node)); + VTR_LOG("Node coordinate: %d\n", rr_graph.node_coordinate_to_string(src_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); VTR_LOG("Channel node:\n"); - rr_graph.print_node(chan_node); + VTR_LOG("Node type: %s\n", rr_graph.node_type_string(chan_node)); + VTR_LOG("Node coordinate: %d\n", rr_graph.node_coordinate_to_string(chan_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(chan_node)); } VTR_ASSERT(NUM_SIDES != side); @@ -855,7 +847,6 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, edge_counter++; } -#endif /* Store the sorted edge */ for (size_t side = 0; side < get_num_sides(); ++side) { @@ -985,8 +976,6 @@ bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); -// NYI -#if 0 for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { RREdgeId src_edge = node_in_edges[iedge]; RREdgeId src_cand_edge = cand_node_in_edges[iedge]; @@ -1011,7 +1000,6 @@ bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, return false; } } -#endif return true; } @@ -1030,14 +1018,6 @@ bool RRGSB::is_cb_node_mirror(const RRGraphView& rr_graph, RRNodeId node = this->get_ipin_node(node_side, node_id); RRNodeId cand_node = cand.get_ipin_node(node_side, node_id); - // NYI - // unused parameter - (void)(rr_graph); - (void)(cb_type); - // unused variables - (void)(node); - (void)(cand_node); -#if 0 if (rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size()) { return false; } @@ -1092,7 +1072,6 @@ bool RRGSB::is_cb_node_mirror(const RRGraphView& rr_graph, return false; } } -#endif return true; } From 38a8569de47d644c1f0ac5bdb6166cb627a945f4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 14 Aug 2022 15:45:14 -0700 Subject: [PATCH 020/453] [vpr] add missing API find_edges() for tileable rr_graph builder --- libs/librrgraph/src/base/rr_graph_view.cpp | 20 ++++++++++++++----- libs/librrgraph/src/base/rr_graph_view.h | 3 +++ .../tileable_rr_graph/rr_graph_view_util.cpp | 7 ------- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index eccac8b7f05..5ae0d7a430e 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -23,9 +23,19 @@ RRGraphView::RRGraphView(const t_rr_graph_storage& node_storage, } std::vector RRGraphView::node_in_edges(RRNodeId node) const { - VTR_ASSERT(size_t(node) < node_storage_.size()); - if (node_in_edges_.empty()) { - return std::vector(); - } - return node_in_edges_[node]; + VTR_ASSERT(size_t(node) < node_storage_.size()); + if (node_in_edges_.empty()) { + return std::vector(); + } + return node_in_edges_[node]; +} + +std::vector RRGraphView::find_edges(const RRNodeId& src_node, const RRNodeId& des_node) const { + std::vector edge_list; + for (auto iedge : node_out_edges(src_node)) { + if (edge_sink_node(RREdgeId(iedge)) == des_node) { + edge_list.push_back(RREdgeId(iedge)); + } + } + return edge_list; } diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 1719751da08..b2695e67e62 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -378,6 +378,9 @@ class RRGraphView { return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(num_edges(id))); } + /** @brief find the edges between two nodes */ + std::vector find_edges(const RRNodeId& src_node, const RRNodeId& des_node) const; + /** @brief Get the number of edges. This function is inlined for runtime optimization. */ inline t_edge_size num_edges(RRNodeId node) const { return node_storage_.num_edges(node); diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 4c3a55144ef..292cade3111 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -13,12 +13,6 @@ std::vector find_rr_graph_switches(const RRGraphView& rr_graph, const RRNodeId& to_node) { std::vector switches; - // NYI - // unused parameters - (void)(rr_graph); - (void)(from_node); - (void)(to_node); -#if 0 std::vector edges = rr_graph.find_edges(from_node, to_node); if (true == edges.empty()) { /* edge is open, we return an empty vector of switches */ @@ -31,7 +25,6 @@ std::vector find_rr_graph_switches(const RRGraphView& rr_graph, for (auto edge : edges) { switches.push_back(rr_graph.edge_switch(edge)); } -#endif return switches; } From 0af16341a4e5c0266be2f7fe0872e708bfacde40 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 14 Aug 2022 15:52:22 -0700 Subject: [PATCH 021/453] [vpr] using updated api in tileable rrgraph builder when finding channel nodes --- vpr/src/tileable_rr_graph/rr_graph_view_util.cpp | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 292cade3111..90dadea3964 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -74,20 +74,11 @@ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); - // NYI - // unused parameters - (void)(rr_graph); - (void)(x); - (void)(y); -#if 0 - for (short track = 0; track < rr_graph.chan_num_tracks(x, y, rr_type); ++track) { - RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, track); - + for (const RRNodeId& rr_node_index : rr_graph.node_lookup().find_channel_nodes(x, y, rr_type)) { if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); } } -#endif return indices; } From aba2572f053eb7712a9ffedc000e7c79470a0c82 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 09:07:08 -0700 Subject: [PATCH 022/453] [vpr] now enable build edges and incoming edges --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 3 +++ vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index cd8c5aa2f83..b2bc9135c39 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -271,6 +271,9 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* Save the track ids for tileable routing resource graph */ device_ctx.rr_node_track_ids = rr_node_track_ids; + /* Build incoming edges */ + device_ctx.rr_graph_builder.build_incoming_edges(); + /************************************************************************ * Allocate external data structures * a. cost_index diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 2df3a759286..1f0c886ae9d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1423,9 +1423,10 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, */ /* add edges to the opin_node */ - rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch); } } } + /* Build actual edges */ + rr_graph_builder.build_edges(); } From b06c5bad536ef0063f4b2070f8e13dce0fc43084 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 09:10:17 -0700 Subject: [PATCH 023/453] [vpr] syntax --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index b2bc9135c39..031deebd58a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -272,7 +272,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ device_ctx.rr_node_track_ids = rr_node_track_ids; /* Build incoming edges */ - device_ctx.rr_graph_builder.build_incoming_edges(); + device_ctx.rr_graph_builder.build_in_edges(); /************************************************************************ * Allocate external data structures From 314d22a0900cf5a17e6360e1868f48c673c0bec2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 09:28:48 -0700 Subject: [PATCH 024/453] [vpr] enable tileable rr_graph in create_rr_graph() --- vpr/src/route/rr_graph.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 3cb077b2d48..f992602a6ca 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -348,13 +348,9 @@ void create_rr_graph(const t_graph_type graph_type, directs, num_directs, &det_routing_arch->wire_to_rr_ipin_switch, Warnings); - if (router_opts.reorder_rr_graph_nodes_algorithm != DONT_REORDER) { - mutable_device_ctx.rr_graph_builder.reorder_nodes(router_opts.reorder_rr_graph_nodes_algorithm, - router_opts.reorder_rr_graph_nodes_threshold, - router_opts.reorder_rr_graph_nodes_seed); - } } else { /* We do not support dedicated network for clocks in tileable rr_graph generation */ + VTR_LOG_WARN("Tileable routing resource graph does not support clock modeling yet! Related options are ignored..."); build_tileable_unidir_rr_graph(block_types, grid, nodes_per_chan, @@ -374,6 +370,12 @@ void create_rr_graph(const t_graph_type graph_type, false, /* Do not allow passing tracks to be wired to the same routing channels */ Warnings); } + /* Reorder nodes upon needs in algorithms and router options */ + if (router_opts.reorder_rr_graph_nodes_algorithm != DONT_REORDER) { + mutable_device_ctx.rr_graph_builder.reorder_nodes(router_opts.reorder_rr_graph_nodes_algorithm, + router_opts.reorder_rr_graph_nodes_threshold, + router_opts.reorder_rr_graph_nodes_seed); + } } process_non_config_sets(); From 4f19f8e0573a4844fe66a334bfaa20abe48913df Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 09:32:21 -0700 Subject: [PATCH 025/453] [test] add a quick test for tileable rr_graph --- vtr_flow/arch/timing/k4_N4_tileable_90nm.xml | 194 ++++++++++++++++++ .../config/config.txt | 29 +++ .../config/golden_results.txt | 4 + 3 files changed, 227 insertions(+) create mode 100644 vtr_flow/arch/timing/k4_N4_tileable_90nm.xml create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt diff --git a/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml b/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml new file mode 100644 index 00000000000..5193264205e --- /dev/null +++ b/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml @@ -0,0 +1,194 @@ + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2.253000e-10 + 2.253000e-10 + 2.253000e-10 + 2.253000e-10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt new file mode 100755 index 00000000000..fbf3358dd11 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt @@ -0,0 +1,29 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/4 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=diffeq.blif +circuit_list_add=ex5p.blif +circuit_list_add=s298.blif + +# Add architectures to list to sweep +arch_list_add=k4_N4_tileable_90nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +script_params=-starting_stage vpr -track_memory_usage + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt new file mode 100644 index 00000000000..7abe3a1a1c3 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time placement_technique reward uniform_percentage median_percentage wmedian_percentage wcent_percentage fr_percentage critUni_percentage centroid_percentage + k4_N4_90nm.xml diffeq.blif common 6.72 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-3198-gd038c933b release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-01-02T13:20:16 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 87228 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.40 10030 0.93 0.01 6.59694 -1414.7 -6.59694 6.59694 0.45 0.00189405 0.00143772 0.221979 0.167805 24 12059 26 983127 929624 797780. 1508.09 2.59 0.588243 0.472549 11020 20 7062 23191 1573824 393127 6.8984 6.8984 -1529.52 -6.8984 0 0 1.04508e+06 1975.57 0.13 0.43 0.131471 0.112481 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 + k4_N4_90nm.xml ex5p.blif common 16.92 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-3198-gd038c933b release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-01-02T13:20:16 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 68688 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.17 11681 0.71 0.01 6.75152 -301.537 -6.75152 nan 0.34 0.00117768 0.000911645 0.136814 0.106107 34 15896 33 804782 771343 910617. 2064.89 13.76 0.477973 0.383445 13620 21 8417 29539 3341244 830781 6.81396 nan -313.113 -6.81396 0 0 1.15594e+06 2621.17 0.13 0.55 0.0731153 0.0639044 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 + k4_N4_90nm.xml s298.blif common 11.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-3198-gd038c933b release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-01-02T13:20:16 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 78820 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.31 14228 1.11 0.01 11.6554 -90.3611 -11.6554 11.6554 0.56 0.00215172 0.00157042 0.245315 0.182305 26 18055 30 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 6.01 0.62371 0.489649 16623 19 8342 42276 3817766 734253 11.5305 11.5305 -91.3072 -11.5305 0 0 1.43821e+06 2127.53 0.31 0.73 0.120758 0.1047 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 From 0b778565370406691184c204323044735ad90947 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 09:33:03 -0700 Subject: [PATCH 026/453] [test] enable new test in strong regression test --- vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 058abb05c9c..35e0d783fbe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -80,3 +80,4 @@ regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan regression_tests/vtr_reg_strong/koios regression_tests/vtr_reg_strong/koios_no_complex_dsp +regression_tests/vtr_reg_strong/strong_tileable_rr_graph From 8c2bc64d97307f433dcafe802c2d8827860dfca1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 09:38:08 -0700 Subject: [PATCH 027/453] [lib] enable tileable options in read fpga arch library --- libs/libarchfpga/src/read_xml_arch_file.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 95481f264e4..ba85a5a2804 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2367,7 +2367,10 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti VTR_ASSERT(layout_tag.name() == std::string("layout")); //Expect no attributes on - expect_only_attributes(layout_tag, {}, loc_data); + //expect_only_attributes(layout_tag, {}, loc_data); + + arch->tileable = get_attribute(layout_tag, "tileable", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false); //Count the number of or tags size_t auto_layout_cnt = 0; From 2a846e4cb096c6f74266302cabd50405186de852 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 10:54:52 -0700 Subject: [PATCH 028/453] [vpr] allocate nodes --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 9662cb52bcd..721a48f43c5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -340,7 +340,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, num_nodes += num_node_per_type; } - rr_graph_builder.reserve_nodes(num_nodes); + rr_graph_builder.resize_nodes(num_nodes); rr_node_driver_switches.reserve(num_nodes); } From 54efbc26332cd1bc5945eda007a58b70d94ed889 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 14:43:33 -0700 Subject: [PATCH 029/453] [vpr] debugging tileable rr_graph builder --- libs/librrgraph/src/base/rr_graph_builder.cpp | 14 +++++++++ libs/librrgraph/src/base/rr_graph_builder.h | 4 +++ libs/librrgraph/src/base/rr_graph_storage.cpp | 20 ++++++------- .../tileable_rr_graph_node_builder.cpp | 29 ++++++++----------- 4 files changed, 40 insertions(+), 27 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 9523000dc83..d7cbea13ff6 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -66,6 +66,20 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { } } +RRNodeId RRGraphBuilder::create_node(int x, int y, t_rr_type type, int ptc, e_side side) { + node_storage_.emplace_back(); + RRNodeId new_node = RRNodeId(node_storage_.size() - 1); + node_storage_.set_node_type(new_node, type); + node_storage_.set_node_coordinates(new_node, x, y, x, y); + node_storage_.set_node_ptc_num(new_node, ptc); + if (CHANX != type && CHANY != type) { + node_storage_.add_node_side(new_node, side); + } + node_lookup_.add_node(new_node, x, y, type, ptc, side); + + return new_node; +} + void RRGraphBuilder::clear() { node_lookup_.clear(); node_storage_.clear(); diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index a036fea7866..1a539d4fb30 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -118,6 +118,10 @@ class RRGraphBuilder { inline void set_node_type(RRNodeId id, t_rr_type type) { node_storage_.set_node_type(id, type); } + /** @brief Create a new rr_node in the node storage and register it to the node look-up. + * Return a valid node id if succeed. Otherwise, return an invalid id. + */ + RRNodeId create_node(int x, int y, t_rr_type type, int ptc, e_side side = SIDES[0]); /** * @brief Add an existing rr_node in the node storage to the node look-up * diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 5e85557499d..179b159083c 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -601,21 +601,21 @@ void t_rr_graph_storage::set_node_ptc_num(RRNodeId id, short new_ptc_num) { } void t_rr_graph_storage::set_node_pin_num(RRNodeId id, short new_pin_num) { if (node_type(id) != IPIN && node_type(id) != OPIN) { - VTR_LOG_ERROR("Attempted to set RR node 'pin_num' for non-IPIN/OPIN type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'pin_num' for non-IPIN/OPIN type '%s'\n", node_type_string(id)); } node_ptc_[id].ptc_.pin_num = new_pin_num; } void t_rr_graph_storage::set_node_track_num(RRNodeId id, short new_track_num) { if (node_type(id) != CHANX && node_type(id) != CHANY) { - VTR_LOG_ERROR("Attempted to set RR node 'track_num' for non-CHANX/CHANY type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'track_num' for non-CHANX/CHANY type '%s'\n", node_type_string(id)); } node_ptc_[id].ptc_.track_num = new_track_num; } void t_rr_graph_storage::set_node_class_num(RRNodeId id, short new_class_num) { if (node_type(id) != SOURCE && node_type(id) != SINK) { - VTR_LOG_ERROR("Attempted to set RR node 'class_num' for non-SOURCE/SINK type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'class_num' for non-SOURCE/SINK type '%s'\n", node_type_string(id)); } node_ptc_[id].ptc_.class_num = new_class_num; } @@ -630,7 +630,7 @@ static short get_node_pin_num( RRNodeId id) { auto node_type = node_storage[id].type_; if (node_type != IPIN && node_type != OPIN) { - VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'", rr_node_typename[node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'\n", rr_node_typename[node_type]); } return node_ptc[id].ptc_.pin_num; } @@ -641,7 +641,7 @@ static short get_node_track_num( RRNodeId id) { auto node_type = node_storage[id].type_; if (node_type != CHANX && node_type != CHANY) { - VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'", rr_node_typename[node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'\n", rr_node_typename[node_type]); } return node_ptc[id].ptc_.track_num; } @@ -652,7 +652,7 @@ static short get_node_class_num( RRNodeId id) { auto node_type = node_storage[id].type_; if (node_type != SOURCE && node_type != SINK) { - VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'", rr_node_typename[node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'\n", rr_node_typename[node_type]); } return node_ptc[id].ptc_.class_num; } @@ -702,7 +702,7 @@ void t_rr_graph_storage::set_node_coordinates(RRNodeId id, short x1, short y1, s void t_rr_graph_storage::set_node_cost_index(RRNodeId id, RRIndexedDataId new_cost_index) { auto& node = node_storage_[id]; if ((size_t)new_cost_index >= std::numeric_limits::max()) { - VTR_LOG_ERROR("Attempted to set cost_index_ %zu above cost_index storage max value.", + VTR_LOG_ERROR("Attempted to set cost_index_ %zu above cost_index storage max value.\n", new_cost_index); } node.cost_index_ = (size_t)new_cost_index; @@ -719,19 +719,19 @@ void t_rr_graph_storage::set_node_capacity(RRNodeId id, short new_capacity) { void t_rr_graph_storage::set_node_direction(RRNodeId id, Direction new_direction) { if (node_type(id) != CHANX && node_type(id) != CHANY) { - VTR_LOG_ERROR("Attempted to set RR node 'direction' for non-channel type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'direction' for non-channel type '%s'\n", node_type_string(id)); } node_storage_[id].dir_side_.direction = new_direction; } void t_rr_graph_storage::add_node_side(RRNodeId id, e_side new_side) { if (node_type(id) != IPIN && node_type(id) != OPIN) { - VTR_LOG_ERROR("Attempted to set RR node 'side' for non-channel type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'side' for non-channel type '%s'\n", node_type_string(id)); } std::bitset side_bits = node_storage_[id].dir_side_.sides; side_bits[size_t(new_side)] = true; if (side_bits.to_ulong() > CHAR_MAX) { - VTR_LOG_ERROR("Invalid side '%s' to be added to rr node %u", SIDE_STRING[new_side], size_t(id)); + VTR_LOG_ERROR("Invalid side '%s' to be added to rr node %u\n", SIDE_STRING[new_side], size_t(id)); } node_storage_[id].dir_side_.sides = static_cast(side_bits.to_ulong()); } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 721a48f43c5..3c845839b01 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -340,9 +340,9 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, num_nodes += num_node_per_type; } - rr_graph_builder.resize_nodes(num_nodes); + rr_graph_builder.reserve_nodes(num_nodes); - rr_node_driver_switches.reserve(num_nodes); + rr_node_driver_switches.resize(num_nodes); } /************************************************************************ @@ -380,7 +380,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder width, height); for (const int& pin_num : opin_list) { /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, OPIN, pin_num, side); + const RRNodeId& node = rr_graph_builder.create_node(width, height, OPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -396,8 +396,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); + rr_node_driver_switches[node] = delayless_switch; /* RC data */ rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); @@ -443,7 +442,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); for (const int& pin_num : ipin_list) { /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(width, height, IPIN, pin_num, side); + const RRNodeId& node = rr_graph_builder.create_node(width, height, IPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -459,8 +458,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(wire_to_ipin_switch); + rr_node_driver_switches[node] = wire_to_ipin_switch; /* RC data */ rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); @@ -495,7 +493,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build } /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + const RRNodeId& node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -513,8 +511,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); + rr_node_driver_switches[node] = delayless_switch; /* RC data */ rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); @@ -546,7 +543,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder } /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + const RRNodeId& node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -564,8 +561,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); /* Switch info */ - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(delayless_switch); + rr_node_driver_switches[node] = delayless_switch; /* RC data */ rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); @@ -670,7 +666,7 @@ static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, || ((true == chan_details.is_track_end(itrack)) && (Direction::DEC == chan_details.get_track_direction(itrack)))) { /* Create a new chan rr_node */ - const RRNodeId& node = rr_graph_builder.node_lookup().find_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); + const RRNodeId& node = rr_graph_builder.create_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); rr_graph_builder.set_node_track_num(node, itrack); @@ -680,8 +676,7 @@ static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, /* assign switch id */ size_t seg_id = chan_details.get_track_segment_id(itrack); - VTR_ASSERT(size_t(node) == rr_node_driver_switches.size()); - rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); + rr_node_driver_switches[node] = RRSwitchId(segment_infs[seg_id].arch_opin_switch); /* Update chan_details with node_id */ chan_details.set_track_node_id(itrack, size_t(node)); From a46461bd56bae466425431da3d4cbd725943086b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 17:07:35 -0700 Subject: [PATCH 030/453] [vpr] debugging tileable rr_graph generator --- libs/librrgraph/src/base/rr_graph_builder.cpp | 11 +++-- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- libs/librrgraph/src/base/rr_graph_view.h | 5 +++ vpr/src/route/rr_graph.cpp | 2 +- .../tileable_rr_graph_builder.cpp | 2 + .../tileable_rr_graph_edge_builder.cpp | 16 +++++--- .../tileable_rr_graph_gsb.cpp | 2 +- .../tileable_rr_graph_node_builder.cpp | 41 +++++++++++++++---- 8 files changed, 61 insertions(+), 20 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index d7cbea13ff6..a55e7ee2882 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -67,15 +67,20 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { } RRNodeId RRGraphBuilder::create_node(int x, int y, t_rr_type type, int ptc, e_side side) { + e_side node_side = SIDES[0]; + /* Only OPIN and IPIN nodes have sides, otherwise force to use a default side */ + if (OPIN == type || IPIN == type) { + node_side = side; + } node_storage_.emplace_back(); RRNodeId new_node = RRNodeId(node_storage_.size() - 1); node_storage_.set_node_type(new_node, type); node_storage_.set_node_coordinates(new_node, x, y, x, y); node_storage_.set_node_ptc_num(new_node, ptc); - if (CHANX != type && CHANY != type) { - node_storage_.add_node_side(new_node, side); + if (OPIN == type || IPIN == type) { + node_storage_.add_node_side(new_node, node_side); } - node_lookup_.add_node(new_node, x, y, type, ptc, side); + node_lookup_.add_node(new_node, x, y, type, ptc, node_side); return new_node; } diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 1a539d4fb30..bba33b21cf4 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -121,7 +121,7 @@ class RRGraphBuilder { /** @brief Create a new rr_node in the node storage and register it to the node look-up. * Return a valid node id if succeed. Otherwise, return an invalid id. */ - RRNodeId create_node(int x, int y, t_rr_type type, int ptc, e_side side = SIDES[0]); + RRNodeId create_node(int x, int y, t_rr_type type, int ptc, e_side side = NUM_SIDES); /** * @brief Add an existing rr_node in the node storage to the node look-up * diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index b2695e67e62..f5a4312ad07 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -499,6 +499,11 @@ class RRGraphView { return node_storage_.validate_node(node_id, rr_switch_inf_); } + /** @brief Check if the node id is a valid one in storage */ + inline bool valid_node(RRNodeId node_id) const { + return size_t(node_id) < node_storage_.size(); + } + /** @brief Check if the switch is a valid one in storage */ inline bool valid_switch(RRSwitchId switch_id) const { return (size_t(switch_id) < rr_switch_inf_.size()); diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index f992602a6ca..0bc7faf11df 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -350,7 +350,7 @@ void create_rr_graph(const t_graph_type graph_type, Warnings); } else { /* We do not support dedicated network for clocks in tileable rr_graph generation */ - VTR_LOG_WARN("Tileable routing resource graph does not support clock modeling yet! Related options are ignored..."); + VTR_LOG_WARN("Tileable routing resource graph does not support clock modeling yet! Related options are ignored...\n"); build_tileable_unidir_rr_graph(block_types, grid, nodes_per_chan, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 031deebd58a..ed43eb14657 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -168,6 +168,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ delayless_rr_switch, through_channel); + VTR_LOG("Built %d nodes\n", device_ctx.rr_graph.num_nodes()); + /************************************************************************ * Create the connectivity of OPINs * a. Evenly assign connections to OPINs to routing tracks diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 317cafca793..ae24c263708 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -35,10 +35,14 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, rr_graph.node_pin_num(node)); /* Create edges between SOURCE and OPINs */ - const RRNodeId& src_node = rr_graph_builder.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, - ylow - grids[xlow][ylow].height_offset, - SOURCE, src_node_class_num); - VTR_ASSERT(true == rr_graph.validate_node(src_node)); + const RRNodeId& src_node = rr_graph.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, + ylow - grids[xlow][ylow].height_offset, + SOURCE, src_node_class_num, SIDES[0]); + VTR_LOG("Des Node: %ld, %s\n", + size_t(node), rr_graph.node_coordinate_to_string(node).c_str()); + VTR_LOG("Src Node: %ld, xlow: %d, ylow:%d, grid.width_offset:%d, grid.height_offset:%d, class_id:%d\n", + size_t(src_node), xlow, ylow, grids[xlow][ylow].width_offset, grids[xlow][ylow].height_offset, src_node_class_num); + VTR_ASSERT(true == rr_graph.valid_node(src_node)); /* add edges to the src_node */ rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node]); @@ -68,8 +72,8 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, /* 1. create edges between IPINs and SINKs */ const RRNodeId& sink_node = rr_graph.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, ylow - grids[xlow][ylow].height_offset, - SINK, sink_node_class_num); - VTR_ASSERT(true == rr_graph.validate_node(sink_node)); + SINK, sink_node_class_num, SIDES[0]); + VTR_ASSERT(true == rr_graph.valid_node(sink_node)); /* add edges to connect the IPIN node to SINK nodes */ rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 1f0c886ae9d..d5f103737bd 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -366,7 +366,7 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, // from_tracks[side].size(), inode, to_track_id, to_track_ids[to_track_id], // to_track_index, to_tracks[to_side_index].size()); const RRNodeId& to_track_node = rr_gsb.get_chan_node(to_side, to_track_index); - VTR_ASSERT(true == rr_graph.validate_node(to_track_node)); + VTR_ASSERT(true == rr_graph.valid_node(to_track_node)); /* from_track should be IN_PORT */ VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index)); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 3c845839b01..bec760f5735 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -343,6 +343,8 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, rr_graph_builder.reserve_nodes(num_nodes); rr_node_driver_switches.resize(num_nodes); + + VTR_LOG("Allocated %d nodes\n", num_nodes); } /************************************************************************ @@ -380,7 +382,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder width, height); for (const int& pin_num : opin_list) { /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.create_node(width, height, OPIN, pin_num, side); + RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x() + width, grid_coordinate.y() + height, OPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -442,7 +444,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); for (const int& pin_num : ipin_list) { /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.create_node(width, height, IPIN, pin_num, side); + RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x() + width, grid_coordinate.y() + height, IPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -486,14 +488,18 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build SideManager io_side_manager(io_side); /* Set a SOURCE rr_node for each DRIVER class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + VTR_LOG("Grid type=%s, x=%d, y=%d, num_class=%d\n", + cur_grid.type->name, grid_coordinate.x(), grid_coordinate.y(), cur_grid.type->class_inf.size()); + for (int iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { /* Set a SINK rr_node for the OPIN */ if (DRIVER != cur_grid.type->class_inf[iclass].type) { continue; } /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + VTR_LOG("Node: %d, x=%d, y=%d, type=SOURCE, class=%d\n", + size_t(node), grid_coordinate.x(), grid_coordinate.y(), iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -502,8 +508,6 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build grid_coordinate.y() + cur_grid.type->height - 1); rr_graph_builder.set_node_class_num(node, iclass); - rr_graph_builder.set_node_capacity(node, 1); - /* The capacity should be the number of pins in this class*/ rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); @@ -536,14 +540,14 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder SideManager io_side_manager(io_side); /* Set a SINK rr_node for each RECEIVER class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + for (int iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { /* Set a SINK rr_node for the OPIN */ if (RECEIVER != cur_grid.type->class_inf[iclass].type) { continue; } /* Create a new node and fill information */ - const RRNodeId& node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -637,6 +641,27 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, wire_to_ipin_switch); } } + //Copy the SOURCE/SINK nodes to all offset positions for blocks with width > 1 and/or height > 1 + // This ensures that look-ups on non-root locations will still find the correct SOURCE/SINK + for (size_t x = 0; x < grids.width(); x++) { + for (size_t y = 0; y < grids.height(); y++) { + int width_offset = grids[x][y].width_offset; + int height_offset = grids[x][y].height_offset; + if (width_offset != 0 || height_offset != 0) { + int root_x = x - width_offset; + int root_y = y - height_offset; + + rr_graph_builder.node_lookup().mirror_nodes(vtr::Point(root_x, root_y), + vtr::Point(x, y), + SOURCE, + SIDES[0]); + rr_graph_builder.node_lookup().mirror_nodes(vtr::Point(root_x, root_y), + vtr::Point(x, y), + SINK, + SIDES[0]); + } + } + } } /************************************************************************ From a96afb91dd51eef4ab04a5715ce2714049092821 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 18:43:10 -0700 Subject: [PATCH 031/453] [vpr] fixed a bug --- vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index cb8afb1db9a..4fc935fae4b 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -136,7 +136,7 @@ size_t get_grid_num_classes(const t_grid_tile& cur_grid, const e_pin_type& pin_type) { size_t num_classes = 0; - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + for (int iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { /* Bypass unmatched pin_type */ if (pin_type != cur_grid.type->class_inf[iclass].type) { continue; From 00d118d101e3453c4ba247c67219730b31ebff65 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 15 Aug 2022 22:37:41 -0700 Subject: [PATCH 032/453] [vpr] keep debugging the errors in find_node() --- .../tileable_rr_graph_builder.cpp | 1 - .../tileable_rr_graph_edge_builder.cpp | 7 ++++--- .../tileable_rr_graph_node_builder.cpp | 18 ++++++++---------- .../tileable_rr_graph_node_builder.h | 2 +- 4 files changed, 13 insertions(+), 15 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index ed43eb14657..ddc8e4399ab 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -233,7 +233,6 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * Add edges that bridge OPINs and IPINs to the rr_graph ***********************************************************************/ /* Create edges for a tileable rr_graph */ - build_rr_graph_edges(device_ctx.rr_graph, device_ctx.rr_graph_builder, rr_node_driver_switches, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index ae24c263708..5b89fca945c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -33,11 +33,12 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, short ylow = rr_graph.node_ylow(node); short src_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], rr_graph.node_pin_num(node)); + VTR_ASSERT(node == rr_graph.node_lookup().find_node(xlow, ylow, OPIN, rr_graph.node_pin_num(node), TOP)); /* Create edges between SOURCE and OPINs */ - const RRNodeId& src_node = rr_graph.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, - ylow - grids[xlow][ylow].height_offset, - SOURCE, src_node_class_num, SIDES[0]); + RRNodeId src_node = rr_graph.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, + ylow - grids[xlow][ylow].height_offset, + SOURCE, src_node_class_num); VTR_LOG("Des Node: %ld, %s\n", size_t(node), rr_graph.node_coordinate_to_string(node).c_str()); VTR_LOG("Src Node: %ld, xlow: %d, ylow:%d, grid.width_offset:%d, grid.height_offset:%d, class_id:%d\n", diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index bec760f5735..c897fa0f306 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -488,9 +488,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build SideManager io_side_manager(io_side); /* Set a SOURCE rr_node for each DRIVER class */ - VTR_LOG("Grid type=%s, x=%d, y=%d, num_class=%d\n", - cur_grid.type->name, grid_coordinate.x(), grid_coordinate.y(), cur_grid.type->class_inf.size()); - for (int iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { + for (size_t iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { /* Set a SINK rr_node for the OPIN */ if (DRIVER != cur_grid.type->class_inf[iclass].type) { continue; @@ -498,8 +496,8 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build /* Create a new node and fill information */ RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); - VTR_LOG("Node: %d, x=%d, y=%d, type=SOURCE, class=%d\n", - size_t(node), grid_coordinate.x(), grid_coordinate.y(), iclass); + VTR_LOG("Node id=%d, x=%d, y=%d, class=%d\n", size_t(node), grid_coordinate.x(), grid_coordinate.y(), iclass); + VTR_ASSERT(RRNodeId(0) == rr_graph_builder.node_lookup().find_node(1, 0, SOURCE, 1)); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -540,7 +538,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder SideManager io_side_manager(io_side); /* Set a SINK rr_node for each RECEIVER class */ - for (int iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { + for (size_t iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { /* Set a SINK rr_node for the OPIN */ if (RECEIVER != cur_grid.type->class_inf[iclass].type) { continue; @@ -669,7 +667,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, track_ids, ptc_num, direction ***********************************************************************/ -static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, +static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, @@ -780,7 +778,7 @@ static void load_one_chan_rr_nodes_basic_info(RRGraphView& rr_graph, * features: capacity, track_ids, ptc_num, direction * grid_info : pb_graph_pin ***********************************************************************/ -static void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, +static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, @@ -887,7 +885,7 @@ static void load_chanx_rr_nodes_basic_info(RRGraphView& rr_graph, * coordinates: xlow, ylow, xhigh, yhigh, * features: capacity, track_ids, ptc_num, direction ***********************************************************************/ -static void load_chany_rr_nodes_basic_info(RRGraphView& rr_graph, +static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, @@ -1020,7 +1018,7 @@ static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, /************************************************************************ * Create all the rr_nodes covering both grids and routing channels ***********************************************************************/ -void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, +void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 116f51e3a89..1372513200a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -27,7 +27,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const std::vector& segment_infs, const bool& through_channel); -void create_tileable_rr_graph_nodes(RRGraphView& rr_graph, +void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, From c460ad1ce6077a4491f45358c49eff4c17a4fcea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Aug 2022 11:14:30 -0700 Subject: [PATCH 033/453] [vpr] identify bugs in resize() in RRSpatial, Use reserve() to bypass it --- .../librrgraph/src/base/rr_spatial_lookup.cpp | 1 + .../tileable_rr_graph_edge_builder.cpp | 6 ---- .../tileable_rr_graph_node_builder.cpp | 32 +++++++++++++++++-- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 6f6bae475d3..7818a5254e8 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -1,4 +1,5 @@ #include "vtr_assert.h" +#include "vtr_log.h" #include "rr_spatial_lookup.h" RRSpatialLookup::RRSpatialLookup() { diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 5b89fca945c..195c5eabe9f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -33,16 +33,10 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, short ylow = rr_graph.node_ylow(node); short src_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], rr_graph.node_pin_num(node)); - VTR_ASSERT(node == rr_graph.node_lookup().find_node(xlow, ylow, OPIN, rr_graph.node_pin_num(node), TOP)); - /* Create edges between SOURCE and OPINs */ RRNodeId src_node = rr_graph.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, ylow - grids[xlow][ylow].height_offset, SOURCE, src_node_class_num); - VTR_LOG("Des Node: %ld, %s\n", - size_t(node), rr_graph.node_coordinate_to_string(node).c_str()); - VTR_LOG("Src Node: %ld, xlow: %d, ylow:%d, grid.width_offset:%d, grid.height_offset:%d, class_id:%d\n", - size_t(src_node), xlow, ylow, grids[xlow][ylow].width_offset, grids[xlow][ylow].height_offset, src_node_class_num); VTR_ASSERT(true == rr_graph.valid_node(src_node)); /* add edges to the src_node */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index c897fa0f306..f6bf54b917f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -496,8 +496,6 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build /* Create a new node and fill information */ RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); - VTR_LOG("Node id=%d, x=%d, y=%d, class=%d\n", size_t(node), grid_coordinate.x(), grid_coordinate.y(), iclass); - VTR_ASSERT(RRNodeId(0) == rr_graph_builder.node_lookup().find_node(1, 0, SOURCE, 1)); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -596,12 +594,27 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::Point grid_coordinate(ix, iy); enum e_side io_side = NUM_SIDES; + std::vector wanted_sides{TOP, RIGHT, BOTTOM, LEFT}; + /* If this is the block on borders, we consider IO side */ if (true == is_io_type(grids[ix][iy].type)) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + wanted_sides.clear(); + wanted_sides.push_back(io_side); } + for (e_side side : wanted_sides) { + for (int width_offset = 0; width_offset < grids[ix][iy].type->width; ++width_offset) { + int x_tile = ix + width_offset; + for (int height_offset = 0; height_offset < grids[ix][iy].type->height; ++height_offset) { + int y_tile = iy + height_offset; + rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, OPIN, grids[ix][iy].type->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, IPIN, grids[ix][iy].type->num_pins, side); + } + } + } + /* Configure source rr_nodes for this grid */ load_one_grid_source_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, @@ -1029,6 +1042,21 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, const bool& through_channel) { + /* Allocates and loads all the structures needed for fast lookups of the * + * index of an rr_node. rr_node_indices is a matrix containing the index * + * of the *first* rr_node at a given (i,j) location. */ + + /* Alloc the lookup table + * .. warning: It is mandatory. There are bugs in resize() when called incrementally in RRSpatialLookup. + * When comment the following block out, you will see errors */ + for (t_rr_type rr_type : RR_TYPES) { + if (rr_type == CHANX) { + rr_graph_builder.node_lookup().resize_nodes(grids.height(), grids.width(), rr_type, NUM_SIDES); + } else { + rr_graph_builder.node_lookup().resize_nodes(grids.width(), grids.height(), rr_type, NUM_SIDES); + } + } + load_grid_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, rr_rc_data, From dcb50bc99ae6e98547bcbe755531fd659aab3303 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Aug 2022 11:27:30 -0700 Subject: [PATCH 034/453] [vpr] consider special case for CHANX when creating a new node --- libs/librrgraph/src/base/rr_graph_builder.cpp | 7 ++++++- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 1 + .../tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index a55e7ee2882..caff0554418 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -80,7 +80,12 @@ RRNodeId RRGraphBuilder::create_node(int x, int y, t_rr_type type, int ptc, e_si if (OPIN == type || IPIN == type) { node_storage_.add_node_side(new_node, node_side); } - node_lookup_.add_node(new_node, x, y, type, ptc, node_side); + /* Special for CHANX, being consistent with the rule in find_node() */ + if (CHANX == type) { + node_lookup_.add_node(new_node, y, x, type, ptc, node_side); + } else { + node_lookup_.add_node(new_node, x, y, type, ptc, node_side); + } return new_node; } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index d5f103737bd..a33eda105d4 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -158,6 +158,7 @@ static bool is_gsb_in_track_sb_population(const RRGraphView& rr_graph, /* Get segment id */ RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); /* validate offset */ + if (!(offset < segment_inf[size_t(seg_id)].sb.size())) VTR_ASSERT(offset < segment_inf[size_t(seg_id)].sb.size()); /* Get the SB population */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index f6bf54b917f..992874c0c25 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -702,7 +702,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, || ((true == chan_details.is_track_end(itrack)) && (Direction::DEC == chan_details.get_track_direction(itrack)))) { /* Create a new chan rr_node */ - const RRNodeId& node = rr_graph_builder.create_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); + RRNodeId node = rr_graph_builder.create_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); rr_graph_builder.set_node_track_num(node, itrack); From fa22d5b7a82d3a08462e51b17a16e5e5e010101e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Aug 2022 11:43:37 -0700 Subject: [PATCH 035/453] [vpr] now tileable rr_graph builder is working. Correctness not checked. Still need to check backward compatibility --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 4 ++-- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index ddc8e4399ab..3df202df572 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -168,8 +168,6 @@ void build_tileable_unidir_rr_graph(const std::vector& typ delayless_rr_switch, through_channel); - VTR_LOG("Built %d nodes\n", device_ctx.rr_graph.num_nodes()); - /************************************************************************ * Create the connectivity of OPINs * a. Evenly assign connections to OPINs to routing tracks @@ -264,6 +262,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ + device_ctx.rr_graph_builder.init_fan_in(); alloc_and_load_rr_switch_inf(device_ctx.num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); /* Save the channel widths for the newly constructed graph */ @@ -273,6 +272,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ device_ctx.rr_node_track_ids = rr_node_track_ids; /* Build incoming edges */ + device_ctx.rr_graph_builder.partition_edges(); device_ctx.rr_graph_builder.build_in_edges(); /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 992874c0c25..6dd205d0f18 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -343,8 +343,6 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, rr_graph_builder.reserve_nodes(num_nodes); rr_node_driver_switches.resize(num_nodes); - - VTR_LOG("Allocated %d nodes\n", num_nodes); } /************************************************************************ From 2ee2bae4b4bd7222fa7272d38acf3ef098652be7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Aug 2022 15:12:36 -0700 Subject: [PATCH 036/453] [script] use relative path in lib capn'proto, to solve compilation errors when using VTR as a submodule --- libs/libvtrcapnproto/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libvtrcapnproto/CMakeLists.txt b/libs/libvtrcapnproto/CMakeLists.txt index cd97b0ec4f1..0f66a10856a 100644 --- a/libs/libvtrcapnproto/CMakeLists.txt +++ b/libs/libvtrcapnproto/CMakeLists.txt @@ -32,7 +32,7 @@ capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS ) if (VPR_ENABLE_INTERCHANGE) - set(IC_DIR ${CMAKE_SOURCE_DIR}/libs/EXTERNAL/libinterchange/interchange) + set(IC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../EXTERNAL/libinterchange/interchange) set(CAPNPC_SRC_PREFIX ${IC_DIR}) find_program(WGET wget REQUIRED) From d43e6672066a029edf5de19d31218cb719ee0601 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Aug 2022 16:34:13 -0700 Subject: [PATCH 037/453] [lib] add interconnect string version and add invalid type --- libs/libarchfpga/src/physical_types.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index bd265299bf8..44aa09d543f 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -164,8 +164,11 @@ enum e_pin_type { enum e_interconnect { COMPLETE_INTERC = 1, DIRECT_INTERC = 2, - MUX_INTERC = 3 + MUX_INTERC = 3, + NUM_INTERC_TYPES /* Invalid type */ }; +/* String version of interconnect types. Use for debugging messages */ +constexpr std::array INTERCONNECT_TYPE_STRING = {{"unknown", "complete", "direct", "mux"}}; /* Orientations. */ enum e_side : unsigned char { From f6844ecb7a70197553f33b5e3ad38a2ca79f9a98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Aug 2022 16:37:05 -0700 Subject: [PATCH 038/453] [lib] typo --- libs/libarchfpga/src/physical_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 44aa09d543f..a652d684dac 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -168,7 +168,7 @@ enum e_interconnect { NUM_INTERC_TYPES /* Invalid type */ }; /* String version of interconnect types. Use for debugging messages */ -constexpr std::array INTERCONNECT_TYPE_STRING = {{"unknown", "complete", "direct", "mux"}}; +constexpr std::array INTERCONNECT_TYPE_STRING = {{"unknown", "complete", "direct", "mux"}}; /* Orientations. */ enum e_side : unsigned char { From 3653c773711ca7893e98372792b1b3e560bcf95e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 09:53:51 -0700 Subject: [PATCH 039/453] [lib] add APIs required by OpenFPGA for rr_graph --- libs/librrgraph/src/base/rr_graph_view.cpp | 5 +++++ libs/librrgraph/src/base/rr_graph_view.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index 5ae0d7a430e..da435033980 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -39,3 +39,8 @@ std::vector RRGraphView::find_edges(const RRNodeId& src_node, const RR } return edge_list; } + +RRSegmentId node_segment(RRNodeId node) const { + RRIndexedDataId cost_index = node_cost_index(node); + return RRSegmentId(rr_indexed_data_[cost_index].seg_index); +} diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index f5a4312ad07..7ca760b8d6a 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -422,6 +422,9 @@ class RRGraphView { return node_storage_.node_cost_index(node); } + /** @brief Get the segment id which a routing resource node represents. Only applicable to nodes whose type is CHANX or CHANY */ + RRSegmentId node_segment(RRNodeId node) const; + /** @brief Return incoming edges for a given routing resource node * Require build_in_edges() to be called first */ From bcc0fd9dbefc8649647b99525421274a538d07f4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 09:55:54 -0700 Subject: [PATCH 040/453] [lib] syntax --- libs/librrgraph/src/base/rr_graph_view.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index da435033980..f20ba626bea 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -40,7 +40,7 @@ std::vector RRGraphView::find_edges(const RRNodeId& src_node, const RR return edge_list; } -RRSegmentId node_segment(RRNodeId node) const { +RRSegmentId RRGraphView::node_segment(RRNodeId node) const { RRIndexedDataId cost_index = node_cost_index(node); return RRSegmentId(rr_indexed_data_[cost_index].seg_index); } From b54d4ad4f3e6bbd0e54a567be3921fdd30efed4d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 10:16:35 -0700 Subject: [PATCH 041/453] [lib] add missing APIs required by OpenFPGA to RRGraphView --- libs/librrgraph/src/base/rr_graph_view.cpp | 30 +++++++++++++++++++ libs/librrgraph/src/base/rr_graph_view.h | 8 +++++ .../rr_graph_builder_utils.cpp | 2 +- 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index f20ba626bea..968ca940f47 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -30,6 +30,36 @@ std::vector RRGraphView::node_in_edges(RRNodeId node) const { return node_in_edges_[node]; } +std::vector RRGraphView::node_configurable_in_edges(RRNodeId node) const { + /* Note: This is not efficient in runtime, should sort edges by configurability when allocating the array! */ + VTR_ASSERT(size_t(node) < node_storage_.size()); + std::vector ret_edges; + if (node_in_edges_.empty()) { + return ret_edges; + } + for (const RREdgeId& edge : node_in_edges_[node]) { + if (rr_switch_inf_[edge_switch(edge)].configurable()) { + ret_edges.push_back(edge); + } + } + return ret_edges; +} + +std::vector RRGraphView::node_non_configurable_in_edges(RRNodeId node) const { + /* Note: This is not efficient in runtime, should sort edges by configurability when allocating the array! */ + VTR_ASSERT(size_t(node) < node_storage_.size()); + std::vector ret_edges; + if (node_in_edges_.empty()) { + return ret_edges; + } + for (const RREdgeId& edge : node_in_edges_[node]) { + if (!rr_switch_inf_[edge_switch(edge)].configurable()) { + ret_edges.push_back(edge); + } + } + return ret_edges; +} + std::vector RRGraphView::find_edges(const RRNodeId& src_node, const RRNodeId& des_node) const { std::vector edge_list; for (auto iedge : node_out_edges(src_node)) { diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 7ca760b8d6a..162161569a6 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -353,6 +353,9 @@ class RRGraphView { inline edge_idx_range configurable_edges(RRNodeId node) const { return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(node_storage_.num_edges(node) - num_non_configurable_edges(node))); } + inline edge_idx_range node_configurable_out_edges(RRNodeId node) const { + return configurable_edges(node); + } /** @brief A non-configurable edge represents a hard-wired connection between routing resources, which could be * a non-configurable buffer that can not be turned off @@ -361,6 +364,9 @@ class RRGraphView { inline edge_idx_range non_configurable_edges(RRNodeId node) const { return vtr::make_range(edge_idx_iterator(node_storage_.num_edges(node) - num_non_configurable_edges(node)), edge_idx_iterator(num_edges(node))); } + inline edge_idx_range node_non_configurable_out_edges(RRNodeId node) const { + return non_configurable_edges(node); + } /** @brief Get outgoing edges for a node. * This API is designed to enable range-based loop to walk through the outgoing edges of a node @@ -429,6 +435,8 @@ class RRGraphView { * Require build_in_edges() to be called first */ std::vector node_in_edges(RRNodeId node) const; + std::vector node_configurable_in_edges(RRNodeId node) const; + std::vector node_non_configurable_in_edges(RRNodeId node) const; /** @brief Return detailed routing segment information with a given id* @note The routing segments here may not be exactly same as those defined in architecture file. They have been * adapted to fit the context of routing resource graphs. diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 4fc935fae4b..c2fb1a580d4 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -136,7 +136,7 @@ size_t get_grid_num_classes(const t_grid_tile& cur_grid, const e_pin_type& pin_type) { size_t num_classes = 0; - for (int iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { + for (size_t iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { /* Bypass unmatched pin_type */ if (pin_type != cur_grid.type->class_inf[iclass].type) { continue; From 4e8ad95dcd623b7c9f362b419511fb9638c92f1e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 14:05:00 -0700 Subject: [PATCH 042/453] [vpr] remove unused headers --- vpr/src/tileable_rr_graph/openfpga_port.cpp | 438 -------------------- vpr/src/tileable_rr_graph/openfpga_port.h | 95 ----- vpr/src/tileable_rr_graph/rr_chan.h | 5 - 3 files changed, 538 deletions(-) delete mode 100644 vpr/src/tileable_rr_graph/openfpga_port.cpp delete mode 100644 vpr/src/tileable_rr_graph/openfpga_port.h diff --git a/vpr/src/tileable_rr_graph/openfpga_port.cpp b/vpr/src/tileable_rr_graph/openfpga_port.cpp deleted file mode 100644 index 63542cd7d5a..00000000000 --- a/vpr/src/tileable_rr_graph/openfpga_port.cpp +++ /dev/null @@ -1,438 +0,0 @@ -#include -#include -#include - -/* Headers from vtrutil library */ -#include "vtr_assert.h" - -#include "openfpga_port.h" - -/************************************************************************ - * Member functions for BasicPort class - ***********************************************************************/ - -/************************************************************************ - * Constructors - ***********************************************************************/ -/* Default constructor */ -BasicPort::BasicPort() { - /* By default we set an invalid port, which size is 0 */ - lsb_ = 1; - msb_ = 0; - - origin_port_width_ = -1; -} - -/* Quick constructor */ -BasicPort::BasicPort(const char* name, const size_t& lsb, const size_t& msb) { - set_name(std::string(name)); - set_width(lsb, msb); - set_origin_port_width(-1); -} - -BasicPort::BasicPort(const std::string& name, const size_t& lsb, const size_t& msb) { - set_name(name); - set_width(lsb, msb); - set_origin_port_width(-1); -} - -BasicPort::BasicPort(const char* name, const size_t& width) { - set_name(std::string(name)); - set_width(width); - set_origin_port_width(-1); -} - -BasicPort::BasicPort(const std::string& name, const size_t& width) { - set_name(name); - set_width(width); - set_origin_port_width(-1); -} - -/************************************************************************ - * Accessors - ***********************************************************************/ -/* get the port width */ -size_t BasicPort::get_width() const { - if (true == is_valid()) { - return msb_ - lsb_ + 1; - } - return 0; /* invalid port has a zero width */ -} - -/* get the LSB */ -size_t BasicPort::get_msb() const { - return msb_; -} - -/* get the LSB */ -size_t BasicPort::get_lsb() const { - return lsb_; -} - -/* get the name */ -std::string BasicPort::get_name() const { - return name_; -} - -/* Make a range of the pin indices */ -std::vector BasicPort::pins() const { - std::vector pin_indices; - - /* Return if the port is invalid */ - if (false == is_valid()) { - return pin_indices; /* Return an empty vector */ - } - /* For valid ports, create a vector whose length is the port width */ - pin_indices.resize(get_width()); - /* Fill in an incremental sequence */ - std::iota(pin_indices.begin(), pin_indices.end(), get_lsb()); - /* Ensure the last one is MSB */ - VTR_ASSERT(get_msb() == pin_indices.back()); - - return pin_indices; -} - -/* Check if a port can be merged with this port: their name should be the same */ -bool BasicPort::mergeable(const BasicPort& portA) const { - return (0 == this->get_name().compare(portA.get_name())); -} - -/* Check if a port is contained by this port: - * this function will check if the (LSB, MSB) of portA - * is contained by the (LSB, MSB) of this port - */ -bool BasicPort::contained(const BasicPort& portA) const { - return (lsb_ <= portA.get_lsb() && portA.get_msb() <= msb_); -} - -/* Set original port width */ -size_t BasicPort::get_origin_port_width() const { - return origin_port_width_; -} - -/************************************************************************ - * Overloaded operators - ***********************************************************************/ -/* Two ports are the same only when: - * 1. port names are the same - * 2. LSBs are the same - * 3. MSBs are the same - */ -bool BasicPort::operator==(const BasicPort& portA) const { - if ((0 == this->get_name().compare(portA.get_name())) - && (this->get_lsb() == portA.get_lsb()) - && (this->get_msb() == portA.get_msb())) { - return true; - } - return false; -} - -bool BasicPort::operator<(const BasicPort& portA) const { - if ((0 == this->get_name().compare(portA.get_name())) - && (this->get_lsb() < portA.get_lsb()) - && (this->get_msb() < portA.get_msb())) { - return true; - } - return false; -} - -/************************************************************************ - * Mutators - ***********************************************************************/ -/* copy */ -void BasicPort::set(const BasicPort& basic_port) { - name_ = basic_port.get_name(); - lsb_ = basic_port.get_lsb(); - msb_ = basic_port.get_msb(); - origin_port_width_ = basic_port.get_origin_port_width(); - - return; -} - -/* set the port LSB and MSB */ -void BasicPort::set_name(const std::string& name) { - name_ = name; - return; -} - -/* set the port LSB and MSB */ -void BasicPort::set_width(const size_t& width) { - if (0 == width) { - make_invalid(); - return; - } - lsb_ = 0; - msb_ = width - 1; - return; -} - -/* set the port LSB and MSB */ -void BasicPort::set_width(const size_t& lsb, const size_t& msb) { - /* If lsb and msb is invalid, we make a default port */ - if (lsb > msb) { - make_invalid(); - return; - } - set_lsb(lsb); - set_msb(msb); - return; -} - -void BasicPort::set_lsb(const size_t& lsb) { - lsb_ = lsb; - return; -} - -void BasicPort::set_msb(const size_t& msb) { - msb_ = msb; - return; -} - -void BasicPort::set_origin_port_width(const size_t& origin_port_width) { - origin_port_width_ = origin_port_width; - return; -} - -/* Increase the port width */ -void BasicPort::expand(const size_t& width) { - if (0 == width) { - return; /* ignore zero-width port */ - } - /* If current port is invalid, we do not combine */ - if (0 == get_width()) { - lsb_ = 0; - msb_ = width; - return; - } - /* Increase MSB */ - msb_ += width; - return; -} - -/* Swap lsb and msb */ -void BasicPort::revert() { - std::swap(lsb_, msb_); - return; -} - -/* rotate: increase both lsb and msb by an offset */ -bool BasicPort::rotate(const size_t& offset) { - /* If offset is 0, we do nothing */ - if (0 == offset) { - return true; - } - - /* If current width is 0, we set a width using the offset! */ - if (0 == get_width()) { - set_width(offset); - return true; - } - /* check if leads to overflow: - * if limits - msb is larger than offset - */ - if ((std::numeric_limits::max() - msb_ < offset)) { - return false; - } - /* Increase LSB and MSB */ - lsb_ += offset; - msb_ += offset; - return true; -} - -/* rotate: decrease both lsb and msb by an offset */ -bool BasicPort::counter_rotate(const size_t& offset) { - /* If current port is invalid or offset is 0, - * we do nothing - */ - if ((0 == offset) || (0 == get_width())) { - return true; - } - /* check if leads to overflow: - * if limits is larger than offset - */ - if ((std::numeric_limits::min() + lsb_ < offset)) { - return false; - } - /* decrease LSB and MSB */ - lsb_ -= offset; - msb_ -= offset; - return true; -} - -/* Reset to initial port */ -void BasicPort::reset() { - make_invalid(); - return; -} - -/* Combine two ports */ -void BasicPort::combine(const BasicPort& port) { - /* LSB follows the current LSB */ - /* MSB increases */ - VTR_ASSERT(0 < port.get_width()); /* Make sure port is valid */ - /* If current port is invalid, we do not combine */ - if (0 == get_width()) { - return; - } - /* Increase MSB */ - msb_ += port.get_width(); - return; -} - -/* A restricted combine function for two ports, - * Following conditions will be applied: - * 1. the two ports have the same name - * Note: you must run mergable() function first - * to make sure this assumption is valid - * 2. the new MSB will be the maximum MSB of the two ports - * 3. the new LSB will be the minimum LSB of the two ports - * 4. both ports should be valid!!! - */ -void BasicPort::merge(const BasicPort& portA) { - VTR_ASSERT(true == this->mergeable(portA)); - VTR_ASSERT(true == this->is_valid() && true == portA.is_valid()); - /* We skip merging if the portA is already contained by this port */ - if (true == this->contained(portA)) { - return; - } - /* LSB follows the minium LSB of the two ports */ - lsb_ = std::min((int)lsb_, (int)portA.get_lsb()); - /* MSB follows the minium MSB of the two ports */ - msb_ = std::max((int)msb_, (int)portA.get_msb()); - /* Origin port width follows the maximum of the two ports */ - msb_ = std::max((int)origin_port_width_, (int)portA.get_origin_port_width()); - return; -} - -/* Internal functions */ -/* Make a port to be invalid: msb < lsb */ -void BasicPort::make_invalid() { - /* set a default invalid port */ - lsb_ = 1; - msb_ = 0; - return; -} - -/* check if port size is valid > 0 */ -bool BasicPort::is_valid() const { - /* msb should be equal or greater than lsb, if this is a valid port */ - if (msb_ < lsb_) { - return false; - } - return true; -} - -/************************************************************************ - * ConfPorts member functions - ***********************************************************************/ - -/************************************************************************ - * Constructor - ***********************************************************************/ -/* Default constructor */ -ConfPorts::ConfPorts() { - /* default port */ - reserved_.reset(); - regular_.reset(); -} - -/* copy */ -ConfPorts::ConfPorts(const ConfPorts& conf_ports) { - set(conf_ports); -} - -/************************************************************************ - * Accessors - ***********************************************************************/ -size_t ConfPorts::get_reserved_port_width() const { - return reserved_.get_width(); -} - -size_t ConfPorts::get_reserved_port_lsb() const { - return reserved_.get_lsb(); -} - -size_t ConfPorts::get_reserved_port_msb() const { - return reserved_.get_msb(); -} - -size_t ConfPorts::get_regular_port_width() const { - return regular_.get_width(); -} - -size_t ConfPorts::get_regular_port_lsb() const { - return regular_.get_lsb(); -} - -size_t ConfPorts::get_regular_port_msb() const { - return regular_.get_msb(); -} - -/************************************************************************ - * Mutators - ***********************************************************************/ -void ConfPorts::set(const ConfPorts& conf_ports) { - set_reserved_port(conf_ports.get_reserved_port_width()); - set_regular_port(conf_ports.get_regular_port_lsb(), conf_ports.get_regular_port_msb()); - return; -} - -void ConfPorts::set_reserved_port(size_t width) { - reserved_.set_width(width); - return; -} - -void ConfPorts::set_regular_port(size_t width) { - regular_.set_width(width); - return; -} - -void ConfPorts::set_regular_port(size_t lsb, size_t msb) { - regular_.set_width(lsb, msb); - return; -} - -void ConfPorts::set_regular_port_lsb(size_t lsb) { - regular_.set_lsb(lsb); - return; -} - -void ConfPorts::set_regular_port_msb(size_t msb) { - regular_.set_msb(msb); - return; -} - -/* Increase the port width of reserved port */ -void ConfPorts::expand_reserved_port(size_t width) { - reserved_.expand(width); - return; -} - -/* Increase the port width of regular port */ -void ConfPorts::expand_regular_port(size_t width) { - regular_.expand(width); - return; -} - -/* Increase the port width of both ports */ -void ConfPorts::expand(size_t width) { - expand_reserved_port(width); - expand_regular_port(width); -} - -/* rotate */ -bool ConfPorts::rotate_regular_port(size_t offset) { - return regular_.rotate(offset); -} - -/* counter rotate */ -bool ConfPorts::counter_rotate_regular_port(size_t offset) { - return regular_.counter_rotate(offset); -} - -/* Reset to initial port */ -void ConfPorts::reset() { - reserved_.reset(); - regular_.reset(); - return; -} diff --git a/vpr/src/tileable_rr_graph/openfpga_port.h b/vpr/src/tileable_rr_graph/openfpga_port.h deleted file mode 100644 index 5d9a8ef910c..00000000000 --- a/vpr/src/tileable_rr_graph/openfpga_port.h +++ /dev/null @@ -1,95 +0,0 @@ -#ifndef OPENFPGA_PORT_H -#define OPENFPGA_PORT_H - -/******************************************************************** - * Include header files that are required by data structure declaration - *******************************************************************/ -#include -#include - -/* A basic port */ -class BasicPort { - public: /* Constructors */ - BasicPort(); - BasicPort(const char* name, const size_t& lsb, const size_t& msb); - BasicPort(const char* name, const size_t& width); - BasicPort(const std::string& name, const size_t& lsb, const size_t& msb); - BasicPort(const std::string& name, const size_t& width); - - public: /* Overloaded operators */ - bool operator==(const BasicPort& portA) const; - bool operator<(const BasicPort& portA) const; - - public: /* Accessors */ - size_t get_width() const; /* get the port width */ - size_t get_msb() const; /* get the LSB */ - size_t get_lsb() const; /* get the LSB */ - std::string get_name() const; /* get the name */ - bool is_valid() const; /* check if port size is valid > 0 */ - std::vector pins() const; /* Make a range of the pin indices */ - bool mergeable(const BasicPort& portA) const; /* Check if a port can be merged with this port */ - bool contained(const BasicPort& portA) const; /* Check if a port is contained by this port */ - size_t get_origin_port_width() const; - - public: /* Mutators */ - void set(const BasicPort& basic_port); /* copy */ - void set_name(const std::string& name); /* set the port LSB and MSB */ - void set_width(const size_t& width); /* set the port LSB and MSB */ - void set_width(const size_t& lsb, const size_t& msb); /* set the port LSB and MSB */ - void set_lsb(const size_t& lsb); - void set_msb(const size_t& msb); - void expand(const size_t& width); /* Increase the port width */ - void revert(); /* Swap lsb and msb */ - bool rotate(const size_t& offset); /* rotate */ - bool counter_rotate(const size_t& offset); /* counter rotate */ - void reset(); /* Reset to initial port */ - void combine(const BasicPort& port); /* Combine two ports */ - void merge(const BasicPort& portA); - void set_origin_port_width(const size_t& origin_port_width); - - private: /* internal functions */ - void make_invalid(); /* Make a port invalid */ - private: /* Internal Data */ - std::string name_; /* Name of this port */ - size_t msb_; /* Most Significant Bit of this port */ - size_t lsb_; /* Least Significant Bit of this port */ - size_t origin_port_width_; /* Original port width of a port, used by traceback port conversion history */ -}; - -/* Configuration ports: - * 1. reserved configuration port, which is used by RRAM FPGA architecture - * 2. regular configuration port, which is used by any FPGA architecture - */ -class ConfPorts { - public: /* Constructors */ - ConfPorts(); /* default port */ - ConfPorts(const ConfPorts& conf_ports); /* copy */ - public: /* Accessors */ - size_t get_reserved_port_width() const; - size_t get_reserved_port_lsb() const; - size_t get_reserved_port_msb() const; - size_t get_regular_port_width() const; - size_t get_regular_port_lsb() const; - size_t get_regular_port_msb() const; - - public: /* Mutators */ - void set(const ConfPorts& conf_ports); - void set_reserved_port(size_t width); - void set_regular_port(size_t width); - void set_regular_port(size_t lsb, size_t msb); - void set_regular_port_lsb(size_t lsb); - void set_regular_port_msb(size_t msb); - void expand_reserved_port(size_t width); /* Increase the port width of reserved port */ - void expand_regular_port(size_t width); /* Increase the port width of regular port */ - void expand(size_t width); /* Increase the port width of both ports */ - bool rotate_regular_port(size_t offset); /* rotate */ - bool counter_rotate_regular_port(size_t offset); /* counter rotate */ - void reset(); /* Reset to initial port */ - private: /* Internal Data */ - BasicPort reserved_; - BasicPort regular_; -}; - -/* TODO: create a class for BL and WL ports */ - -#endif diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h index 11c40595bd3..2e40e06c3d2 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.h +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -9,12 +9,7 @@ /* Headers from vtrutil library */ #include "vtr_geometry.h" -/* Headers from openfpgautil library */ -#include "openfpga_port.h" - /* Headers from vpr library */ -#include "rr_graph_obj.h" - #include "rr_graph_view.h" /******************************************************************** From 885eb58feef2d0fb6789cff017803e032bc3ee82 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 14:36:36 -0700 Subject: [PATCH 043/453] [vpr] add a useful API to get node side --- .../openfpga_rr_graph_utils.cpp | 16 ++++++++++++++++ .../tileable_rr_graph/openfpga_rr_graph_utils.h | 3 +++ 2 files changed, 19 insertions(+) diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index 0855c082691..da17b51b2fc 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -183,3 +183,19 @@ bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, return true; } + +/** @brief Get a side of a given node in a routing resource graph. + * Note that this function expect one valid side to be got. Otherwise, it will fail! */ +e_side get_rr_graph_single_node_side(const RRGraphView& rr_graph, + const RRNodeId& node) { + e_side node_side = NUM_SIDES; + int num_sides = 0; + for (e_side candidate_side : SIDES) { + if (rr_graph.is_node_on_specific_side(node, candidate_side)) { + node_side = candidate_side; + num_sides++; + } + } + VTR_ASSERT(1 == num_sides && node_side != NUM_SIDES); + return node_side; +} diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h index f3d3f65abe8..cba64125615 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h @@ -39,4 +39,7 @@ bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, const RRNodeId& node); +e_side get_rr_graph_single_node_side(const RRGraphView& rr_graph, + const RRNodeId& node); + #endif From e1d6d03cf5954e31f34049ddace7689630993a36 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 16:20:31 -0700 Subject: [PATCH 044/453] [vpr] give access to utility function due to requirement from OpenFPGA --- vpr/src/util/vpr_utils.cpp | 2 +- vpr/src/util/vpr_utils.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 0a62faa03b0..cddd622237f 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -1143,7 +1143,7 @@ static void load_pb_graph_pin_lookup_from_index_rec(t_pb_graph_pin** pb_graph_pi } /* Create a lookup that returns a pb_graph_pin pointer given the pb_graph_pin index */ -static t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type) { +t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type) { t_pb_graph_pin** pb_graph_pin_lookup_from_type = nullptr; t_pb_graph_node* pb_graph_head = type->pb_graph_head; diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 60921ac3645..1599d4f86eb 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -112,6 +112,7 @@ bool primitive_type_feasible(AtomBlockId blk_id, const t_pb_type* cur_pb_type); t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* model_port, const int model_pin, const t_pb_graph_node* pb_graph_node); const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, const AtomPinId pin_id); t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(ClusterBlockId iblock, int ipin); +t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type); vtr::vector alloc_and_load_pin_id_to_pb_mapping(); void free_pin_id_to_pb_mapping(vtr::vector& pin_id_to_pb_mapping); From 674a569688455eccbd620e0612afaf50763c7652 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 16:28:36 -0700 Subject: [PATCH 045/453] [vpr] syntax --- vpr/src/util/vpr_utils.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index cddd622237f..3365cacaa61 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -73,7 +73,6 @@ static AtomPinId find_atom_pin_for_pb_route_id(ClusterBlockId clb, int pb_route_ static bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::regex& blif_model_regex); static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::regex& blif_model_regex); -static t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type); static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type); /******************** Subroutine definitions *********************************/ From 090322cd55f02e6f2d359e58afd91c3e486bfba9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 16:32:02 -0700 Subject: [PATCH 046/453] [vpr] release more API from vpr_utils --- vpr/src/util/vpr_utils.cpp | 3 +-- vpr/src/util/vpr_utils.h | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 3365cacaa61..104fa703c3f 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -73,7 +73,6 @@ static AtomPinId find_atom_pin_for_pb_route_id(ClusterBlockId clb, int pb_route_ static bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::regex& blif_model_regex); static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::regex& blif_model_regex); -static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type); /******************** Subroutine definitions *********************************/ @@ -1170,7 +1169,7 @@ t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_t } /* Free pb_graph_pin lookup array */ -static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type) { +void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type) { if (pb_graph_pin_lookup_from_type == nullptr) { return; } diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 1599d4f86eb..a5fe377cadb 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -114,6 +114,7 @@ const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomLo t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(ClusterBlockId iblock, int ipin); t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type); vtr::vector alloc_and_load_pin_id_to_pb_mapping(); +void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type); void free_pin_id_to_pb_mapping(vtr::vector& pin_id_to_pb_mapping); float compute_primitive_base_cost(const t_pb_graph_node* primitive); From a18c4199afb5a4350c171d3e8be7116330d2a67b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 16:35:38 -0700 Subject: [PATCH 047/453] [lib] add constant string for logic value, useful for debugging messages --- libs/libvtrutil/src/vtr_logic.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/libs/libvtrutil/src/vtr_logic.h b/libs/libvtrutil/src/vtr_logic.h index 30d44c4a6b9..e1ae4ce463d 100644 --- a/libs/libvtrutil/src/vtr_logic.h +++ b/libs/libvtrutil/src/vtr_logic.h @@ -25,9 +25,12 @@ enum class LogicValue { FALSE = 0, TRUE = 1, DONT_CARE = 2, - UNKOWN = 3 + UNKOWN = 3, + NUM_LOGIC_VALUE_TYPES }; +constexpr std::array LOGIC_VALUE_STRING = {{"false", "true", "don't care", "unknown"}}; + } // namespace vtr #endif From 6c781e84795ca263d4660401f5fc125add359ef9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 18:04:51 -0700 Subject: [PATCH 048/453] [vpr] add missing include --- libs/libvtrutil/src/vtr_logic.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libs/libvtrutil/src/vtr_logic.h b/libs/libvtrutil/src/vtr_logic.h index e1ae4ce463d..b43ee49291e 100644 --- a/libs/libvtrutil/src/vtr_logic.h +++ b/libs/libvtrutil/src/vtr_logic.h @@ -16,6 +16,8 @@ constexpr int FALSE = 0; constexpr int TRUE = 1; +#include + namespace vtr { /** From d0a65ad6b86ae312d8a34fa3954656de3a4f1252 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 14:12:32 -0700 Subject: [PATCH 049/453] [vpr] correct the use of header files --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 3df202df572..b1bef8021d3 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -17,7 +17,7 @@ #include "rr_graph.h" #include "check_rr_graph.h" -#include "check_rr_graph_obj.h" +#include "get_parallel_segs.h" #include "rr_graph_builder_utils.h" #include "tileable_chan_details_builder.h" From c854a5eaedcba45c0e778325d583855c29e63a2b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 15:27:48 -0700 Subject: [PATCH 050/453] [lib] fixed a bug on sharing the storage for incoming edges --- libs/librrgraph/src/base/rr_graph_builder.cpp | 2 +- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index caff0554418..63939f5fc16 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -28,7 +28,7 @@ MetadataStorage>& RRGraphBuilder::rr_edge_metadata() return rr_edge_metadata_; } -vtr::vector> RRGraphBuilder::node_in_edge_storage() { +vtr::vector>& RRGraphBuilder::node_in_edge_storage() { return node_in_edges_; } diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index bba33b21cf4..9f015f9c91b 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -46,7 +46,7 @@ class RRGraphBuilder { /** @brief Return a writable object for the meta data on the edge */ MetadataStorage>& rr_edge_metadata(); /** @brief Return a writable object fo the incoming edge storage */ - vtr::vector> node_in_edge_storage(); + vtr::vector>& node_in_edge_storage(); /** @brief Return the size for rr_node_metadata */ inline size_t rr_node_metadata_size() const { From e78f446095456ddad4f70a0b67a912f98931e5ba Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 16:06:33 -0700 Subject: [PATCH 051/453] [vpr] fixed a bug in showing debugging messages --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 4aa7b8e4352..803958db2c1 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -825,12 +825,10 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, if (NUM_SIDES == side) { VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG("SRC node:\n"); - VTR_LOG("Node type: %s\n", rr_graph.node_type_string(src_node)); - VTR_LOG("Node coordinate: %d\n", rr_graph.node_coordinate_to_string(src_node).c_str()); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(src_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); VTR_LOG("Channel node:\n"); - VTR_LOG("Node type: %s\n", rr_graph.node_type_string(chan_node)); - VTR_LOG("Node coordinate: %d\n", rr_graph.node_coordinate_to_string(chan_node).c_str()); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(chan_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(chan_node)); } From 43a80a46bd3c9dc2702c0e225e30663d2fad3401 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 16:15:34 -0700 Subject: [PATCH 052/453] [vpr] fixed a bug on range --- libs/librrgraph/src/base/rr_graph_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 63939f5fc16..f09b54baff0 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -192,7 +192,7 @@ void RRGraphBuilder::build_in_edges() { node_in_edges_.resize(node_storage_.size()); for (const RRNodeId& src_node: vtr::StrongIdRange(RRNodeId(0), RRNodeId(node_storage_.size()))) { - for (size_t iedge = size_t(node_storage_.first_edge(src_node)); iedge < size_t(node_storage_.last_edge(src_node)); iedge++) { + for (size_t iedge = size_t(node_storage_.first_edge(src_node)); iedge <= size_t(node_storage_.last_edge(src_node)); iedge++) { RRNodeId des_node = node_storage_.edge_sink_node(RREdgeId(iedge)); node_in_edges_[des_node].push_back(RREdgeId(iedge)); } From 4c2b47e484110f6b4f5cc6f602e0d6f9c220fb2d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 18:37:49 -0700 Subject: [PATCH 053/453] [lib] clean up header files --- libs/librrgraph/src/base/rr_graph_fwd.h | 6 ++---- libs/librrgraph/src/base/rr_graph_utils.h | 4 ++-- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_fwd.h b/libs/librrgraph/src/base/rr_graph_fwd.h index fee69b34cd2..15199830642 100644 --- a/libs/librrgraph/src/base/rr_graph_fwd.h +++ b/libs/librrgraph/src/base/rr_graph_fwd.h @@ -1,5 +1,5 @@ -#ifndef RR_GRAPH_OBJ_FWD_H -#define RR_GRAPH_OBJ_FWD_H +#ifndef RR_GRAPH_FWD_H +#define RR_GRAPH_FWD_H #include "vtr_strong_id.h" /*************************************************************** @@ -11,8 +11,6 @@ //Forward declaration class t_rr_graph_storage; -class RRGraph; - struct rr_node_id_tag; struct rr_edge_id_tag; struct rr_indexed_data_id_tag; diff --git a/libs/librrgraph/src/base/rr_graph_utils.h b/libs/librrgraph/src/base/rr_graph_utils.h index d3ef4440daa..cf773fb3e3f 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.h +++ b/libs/librrgraph/src/base/rr_graph_utils.h @@ -5,8 +5,8 @@ * the function declaration */ #include -#include "rr_graph_fwd.h" #include "rr_node_types.h" +#include "rr_graph_obj.h" #include "rr_graph_view.h" /* Get node-to-node switches in a RRGraph */ @@ -21,4 +21,4 @@ vtr::vector> get_fan_in_list(const RRGraphView& int seg_index_of_cblock(const RRGraphView& rr_graph, t_rr_type from_rr_type, int to_node); int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node); -#endif \ No newline at end of file +#endif From a88ac6e01bc2ef2793c56f10e5fcd5f340277a78 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 22:10:00 -0700 Subject: [PATCH 054/453] [vpr] print more debugging info when rr_gsb encounts fatal errors --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 803958db2c1..22df200ff4c 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -827,9 +827,17 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, VTR_LOG("SRC node:\n"); VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(src_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& edge : rr_graph.edge_range(src_node)) { + VTR_LOG("%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(edge))); + } VTR_LOG("Channel node:\n"); VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(chan_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(chan_node)); + VTR_LOG("Fan-in nodes:\n"); + for (const auto& edge : rr_graph.node_in_edges(chan_node)) { + VTR_LOG("%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(edge))); + } } VTR_ASSERT(NUM_SIDES != side); From 0d1339e3cb3ddeb45d17a900add7f388382a3753 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 22:24:46 -0700 Subject: [PATCH 055/453] [vpr] format debugging messages --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 22df200ff4c..525b3ca5576 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -824,19 +824,21 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, /* Must have valid side and index */ if (NUM_SIDES == side) { VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); VTR_LOG("SRC node:\n"); VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(src_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); VTR_LOG("Fan-out nodes:\n"); - for (const auto& edge : rr_graph.edge_range(src_node)) { - VTR_LOG("%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(edge))); + for (const auto& temp_edge : rr_graph.edge_range(src_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); } + VTR_LOG("\n----------------------------------\n"); VTR_LOG("Channel node:\n"); VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(chan_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(chan_node)); VTR_LOG("Fan-in nodes:\n"); - for (const auto& edge : rr_graph.node_in_edges(chan_node)) { - VTR_LOG("%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(edge))); + for (const auto& temp_edge : rr_graph.node_in_edges(chan_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(temp_edge)).c_str()); } } From c16fcb8fba16b45484e5c41db506533ee706e986 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 23 Aug 2022 23:12:45 -0700 Subject: [PATCH 056/453] [lib] fixed a bug on clear() for rrgraph builder --- libs/librrgraph/src/base/rr_graph_builder.cpp | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index f09b54baff0..3da9c11c931 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -1,3 +1,4 @@ +#include "vtr_assert.h" #include "vtr_log.h" #include "rr_graph_builder.h" #include "vtr_time.h" @@ -93,6 +94,7 @@ RRNodeId RRGraphBuilder::create_node(int x, int y, t_rr_type type, int ptc, e_si void RRGraphBuilder::clear() { node_lookup_.clear(); node_storage_.clear(); + node_in_edges_.clear(); rr_node_metadata_.clear(); rr_edge_metadata_.clear(); rr_segments_.clear(); @@ -191,10 +193,11 @@ void RRGraphBuilder::build_in_edges() { node_in_edges_.clear(); node_in_edges_.resize(node_storage_.size()); - for (const RRNodeId& src_node: vtr::StrongIdRange(RRNodeId(0), RRNodeId(node_storage_.size()))) { - for (size_t iedge = size_t(node_storage_.first_edge(src_node)); iedge <= size_t(node_storage_.last_edge(src_node)); iedge++) { - RRNodeId des_node = node_storage_.edge_sink_node(RREdgeId(iedge)); - node_in_edges_[des_node].push_back(RREdgeId(iedge)); + for (RRNodeId src_node : vtr::StrongIdRange(RRNodeId(0), RRNodeId(node_storage_.size()))) { + for (auto iedge : node_storage_.edges(src_node)) { + VTR_ASSERT(src_node == node_storage_.edge_source_node(node_storage_.edge_id(src_node, iedge))); + RRNodeId des_node = node_storage_.edge_sink_node(node_storage_.edge_id(src_node, iedge)); + node_in_edges_[des_node].push_back(node_storage_.edge_id(src_node, iedge)); } } is_incoming_edge_dirty_ = false; @@ -203,7 +206,7 @@ void RRGraphBuilder::build_in_edges() { std::vector RRGraphBuilder::node_in_edges(RRNodeId node) const { VTR_ASSERT(size_t(node) < node_storage_.size()); if (is_incoming_edge_dirty_) { - VTR_LOG_ERROR("Incoming edges are built yet in routing resource graph. Please call build_in_edges()."); + VTR_LOG_ERROR("Incoming edges are not built yet in routing resource graph. Please call build_in_edges()."); return std::vector(); } if (node_in_edges_.empty()) { From 3ca5e2f221c78742d0893209e07c6d084c0ef730 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Aug 2022 12:20:45 -0700 Subject: [PATCH 057/453] [lib] add validate APIs for checking incoming edges --- libs/librrgraph/src/base/rr_graph_view.cpp | 52 ++++++++++++++++++++++ libs/librrgraph/src/base/rr_graph_view.h | 5 +++ 2 files changed, 57 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index 968ca940f47..22b1a1e1ba1 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -1,3 +1,4 @@ +#include #include "rr_graph_view.h" #include "rr_node.h" #include "physical_types.h" @@ -74,3 +75,54 @@ RRSegmentId RRGraphView::node_segment(RRNodeId node) const { RRIndexedDataId cost_index = node_cost_index(node); return RRSegmentId(rr_indexed_data_[cost_index].seg_index); } + +size_t RRGraphView::in_edges_count() const { + size_t edge_count = 0; + for (auto edge_list : node_in_edges_) { + edge_count += edge_list.size(); + } + return edge_count; +} + +bool RRGraphView::validate_in_edges() const { + size_t num_err = 0; + /* For each edge, validate that + * - The source node is in the fan-in edge list of the destination node + * - The sink node is in the fan-out edge list of the source node + */ + for (RRNodeId curr_node : vtr::StrongIdRange(RRNodeId(0), RRNodeId(node_storage_.size()))) { + for (auto iedge : node_storage_.edges(curr_node)) { + RRNodeId des_node = node_storage_.edge_sink_node(node_storage_.edge_id(curr_node, iedge)); + std::vector des_fanin_nodes; + for (auto next_edge : node_in_edges(des_node)) { + RRNodeId prev_edge_des_node = node_storage_.edge_source_node(next_edge); + des_fanin_nodes.push_back(prev_edge_des_node); + } + if (des_fanin_nodes.end() == std::find(des_fanin_nodes.begin(), des_fanin_nodes.end(), des_node)) { + VTR_LOG_ERROR("Node '%s' does not appear in the fannout edges of Node '%s'\n", + node_coordinate_to_string(des_node).c_str(), node_coordinate_to_string(curr_node).c_str()); + num_err++; + } + } + for (auto iedge : node_in_edges(curr_node)) { + RRNodeId src_node = node_storage_.edge_source_node(iedge); + std::vector src_fanout_nodes; + for (auto prev_edge : node_storage_.edges(src_node)) { + RRNodeId prev_edge_des_node = node_storage_.edge_sink_node(node_storage_.edge_id(src_node, prev_edge)); + src_fanout_nodes.push_back(prev_edge_des_node); + } + if (src_fanout_nodes.end() == std::find(src_fanout_nodes.begin(), src_fanout_nodes.end(), curr_node)) { + VTR_LOG_ERROR("Node '%s' does not appear in the fan-in edges of Node '%s'\n", + node_coordinate_to_string(src_node).c_str(), node_coordinate_to_string(curr_node).c_str()); + num_err++; + } + } + } + if (num_err) { + VTR_LOG_ERROR("Found %ld errors when validating incoming edges for routing resource graph\n", num_err); + return false; + } + return true; +} + + diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 162161569a6..e52654c03e6 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -520,6 +520,11 @@ class RRGraphView { return (size_t(switch_id) < rr_switch_inf_.size()); } + /** @brief Validate if all the fan-in edge lists are valid */ + bool validate_in_edges() const; + /** @brief Count the number of incoming edges for all the nodes */ + size_t in_edges_count() const; + /* -- Internal data storage -- */ /* Note: only read-only object or data structures are allowed!!! */ private: From ad0d96c8b558de9578a190235ce6e07d064de057 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Aug 2022 12:28:15 -0700 Subject: [PATCH 058/453] [lib] add code comments --- libs/librrgraph/src/base/rr_graph_view.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index 22b1a1e1ba1..02e03c42c57 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -91,6 +91,9 @@ bool RRGraphView::validate_in_edges() const { * - The sink node is in the fan-out edge list of the source node */ for (RRNodeId curr_node : vtr::StrongIdRange(RRNodeId(0), RRNodeId(node_storage_.size()))) { + /* curr_node ---> des_node + * <-?- check if the incoming edge is correct or not + */ for (auto iedge : node_storage_.edges(curr_node)) { RRNodeId des_node = node_storage_.edge_sink_node(node_storage_.edge_id(curr_node, iedge)); std::vector des_fanin_nodes; @@ -104,6 +107,9 @@ bool RRGraphView::validate_in_edges() const { num_err++; } } + /* src_node -?-> curr_node + * <--- check if the fan-out edge is correct or not + */ for (auto iedge : node_in_edges(curr_node)) { RRNodeId src_node = node_storage_.edge_source_node(iedge); std::vector src_fanout_nodes; From f3b5a30913668447922f07f6b13924ff9b54947f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Aug 2022 13:33:39 -0700 Subject: [PATCH 059/453] [lib] fixed a bug in validating incoming edges --- libs/librrgraph/src/base/rr_graph_view.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index 02e03c42c57..edddaed097d 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -101,9 +101,9 @@ bool RRGraphView::validate_in_edges() const { RRNodeId prev_edge_des_node = node_storage_.edge_source_node(next_edge); des_fanin_nodes.push_back(prev_edge_des_node); } - if (des_fanin_nodes.end() == std::find(des_fanin_nodes.begin(), des_fanin_nodes.end(), des_node)) { - VTR_LOG_ERROR("Node '%s' does not appear in the fannout edges of Node '%s'\n", - node_coordinate_to_string(des_node).c_str(), node_coordinate_to_string(curr_node).c_str()); + if (des_fanin_nodes.end() == std::find(des_fanin_nodes.begin(), des_fanin_nodes.end(), curr_node)) { + VTR_LOG_ERROR("Node '%s' does not appear in the fan-in edges of Node '%s', while does drive it in its fan-out list\n", + node_coordinate_to_string(curr_node).c_str(), node_coordinate_to_string(des_node).c_str()); num_err++; } } @@ -118,8 +118,8 @@ bool RRGraphView::validate_in_edges() const { src_fanout_nodes.push_back(prev_edge_des_node); } if (src_fanout_nodes.end() == std::find(src_fanout_nodes.begin(), src_fanout_nodes.end(), curr_node)) { - VTR_LOG_ERROR("Node '%s' does not appear in the fan-in edges of Node '%s'\n", - node_coordinate_to_string(src_node).c_str(), node_coordinate_to_string(curr_node).c_str()); + VTR_LOG_ERROR("Node '%s' does not appear in the fan-out edges of Node '%s', while does exist in its fan-in list\n", + node_coordinate_to_string(curr_node).c_str(), node_coordinate_to_string(src_node).c_str()); num_err++; } } From f77645a5164f405807a130116c743a65ac30260a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Aug 2022 10:30:24 -0700 Subject: [PATCH 060/453] [vpr] now update node-lookup for CHANX and CHANY nodes --- .../tileable_rr_graph_node_builder.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 6dd205d0f18..1d12d4c7705 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -739,6 +739,16 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_graph.node_ylow(rr_node_id), chan_coordinate.x(), chan_coordinate.y()); + /* Update node look-up */ + size_t xlow = std::min(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); + size_t xhigh = std::max(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); + size_t ylow = std::min(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); + size_t yhigh = std::max(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); + for (int ix = xlow; ix <= xhigh; ix++) { + for (int iy = ylow; iy <= yhigh; iy++) { + rr_graph_builder.node_lookup().add_node(rr_node_id, ix, iy, rr_graph.node_type(rr_node_id), itrack); + } + } /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ if ((rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) From bd49f85218718c9ee87c95bd015df8c6d7a9e9a2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Aug 2022 10:43:25 -0700 Subject: [PATCH 061/453] [vpr] debugging CHANX and CHANY coord --- .../tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 1d12d4c7705..5b44a91919d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -744,9 +744,9 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, size_t xhigh = std::max(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); size_t ylow = std::min(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); size_t yhigh = std::max(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); - for (int ix = xlow; ix <= xhigh; ix++) { - for (int iy = ylow; iy <= yhigh; iy++) { - rr_graph_builder.node_lookup().add_node(rr_node_id, ix, iy, rr_graph.node_type(rr_node_id), itrack); + for (size_t ix = xlow; ix <= xhigh; ix++) { + for (size_t iy = ylow; iy <= yhigh; iy++) { + rr_graph_builder.node_lookup().add_node(rr_node_id, ix, iy, rr_graph.node_type(rr_node_id), rr_graph.node_track_num(rr_node_id)); } } From 4155c0b178f6aa73d9aa1e5c14fd7a1dd1fde324 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Aug 2022 10:56:18 -0700 Subject: [PATCH 062/453] [vpr] remove existing node in look-up when updating coordinates --- .../tileable_rr_graph_node_builder.cpp | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 5b44a91919d..db69cd9f9eb 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -734,19 +734,33 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + /* Unset existing node coordinate in the lookup */ + { + size_t xlow = std::min(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); + size_t xhigh = std::max(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); + size_t ylow = std::min(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); + size_t yhigh = std::max(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); + for (size_t ix = xlow; ix <= xhigh; ix++) { + for (size_t iy = ylow; iy <= yhigh; iy++) { + rr_graph_builder.node_lookup().add_node(RRNodeId::INVALID(), ix, iy, rr_graph.node_type(rr_node_id), rr_graph.node_track_num(rr_node_id)); + } + } + } /* set xhigh/yhigh and push changes to track_ids */ rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), rr_graph.node_ylow(rr_node_id), chan_coordinate.x(), chan_coordinate.y()); /* Update node look-up */ - size_t xlow = std::min(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); - size_t xhigh = std::max(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); - size_t ylow = std::min(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); - size_t yhigh = std::max(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); - for (size_t ix = xlow; ix <= xhigh; ix++) { - for (size_t iy = ylow; iy <= yhigh; iy++) { - rr_graph_builder.node_lookup().add_node(rr_node_id, ix, iy, rr_graph.node_type(rr_node_id), rr_graph.node_track_num(rr_node_id)); + { + size_t xlow = std::min(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); + size_t xhigh = std::max(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); + size_t ylow = std::min(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); + size_t yhigh = std::max(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); + for (size_t ix = xlow; ix <= xhigh; ix++) { + for (size_t iy = ylow; iy <= yhigh; iy++) { + rr_graph_builder.node_lookup().add_node(rr_node_id, ix, iy, rr_graph.node_type(rr_node_id), rr_graph.node_track_num(rr_node_id)); + } } } From edd61a38d082895473196afd121dd5326c41aa81 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Aug 2022 13:31:43 -0700 Subject: [PATCH 063/453] [vpr] debugging --- .../tileable_rr_graph_node_builder.cpp | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index db69cd9f9eb..a7c3109b9d4 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -734,18 +734,6 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); - /* Unset existing node coordinate in the lookup */ - { - size_t xlow = std::min(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); - size_t xhigh = std::max(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); - size_t ylow = std::min(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); - size_t yhigh = std::max(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); - for (size_t ix = xlow; ix <= xhigh; ix++) { - for (size_t iy = ylow; iy <= yhigh; iy++) { - rr_graph_builder.node_lookup().add_node(RRNodeId::INVALID(), ix, iy, rr_graph.node_type(rr_node_id), rr_graph.node_track_num(rr_node_id)); - } - } - } /* set xhigh/yhigh and push changes to track_ids */ rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), rr_graph.node_ylow(rr_node_id), @@ -759,7 +747,12 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, size_t yhigh = std::max(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); for (size_t ix = xlow; ix <= xhigh; ix++) { for (size_t iy = ylow; iy <= yhigh; iy++) { - rr_graph_builder.node_lookup().add_node(rr_node_id, ix, iy, rr_graph.node_type(rr_node_id), rr_graph.node_track_num(rr_node_id)); + if (CHANX == rr_graph.node_type(rr_node_id)) { + rr_graph_builder.node_lookup().add_node(rr_node_id, iy, ix, rr_graph.node_type(rr_node_id), rr_graph.node_track_num(rr_node_id)); + } else { + VTR_ASSERT_SAFE(CHANY == rr_graph.node_type(rr_node_id)); + rr_graph_builder.node_lookup().add_node(rr_node_id, ix, iy, rr_graph.node_type(rr_node_id), rr_graph.node_track_num(rr_node_id)); + } } } } From 53e6b0091812ab97786b00bc173988aeedf84d75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Aug 2022 15:05:00 -0700 Subject: [PATCH 064/453] [vpr] now supports multiple ptc number of a routing track in tileable routing resource graph --- libs/librrgraph/src/base/rr_graph_builder.cpp | 73 ++++++++++++++++--- libs/librrgraph/src/base/rr_graph_builder.h | 32 +++++++- libs/librrgraph/src/base/rr_graph_view.cpp | 6 +- libs/librrgraph/src/base/rr_graph_view.h | 6 +- vpr/src/base/vpr_context.h | 2 +- .../tileable_rr_graph_node_builder.cpp | 21 +++--- 6 files changed, 114 insertions(+), 26 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 3da9c11c931..edefb3c8445 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -33,6 +33,10 @@ vtr::vector>& RRGraphBuilder::node_in_edge_stora return node_in_edges_; } +vtr::vector>& RRGraphBuilder::node_ptc_storage() { + return node_ptc_nums_; +} + void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { t_rr_type node_type = node_storage_.node_type(node); short node_ptc_num = node_storage_.node_ptc_num(node); @@ -74,6 +78,7 @@ RRNodeId RRGraphBuilder::create_node(int x, int y, t_rr_type type, int ptc, e_si node_side = side; } node_storage_.emplace_back(); + node_ptc_nums_.emplace_back(); RRNodeId new_node = RRNodeId(node_storage_.size() - 1); node_storage_.set_node_type(new_node, type); node_storage_.set_node_coordinates(new_node, x, y, x, y); @@ -95,6 +100,7 @@ void RRGraphBuilder::clear() { node_lookup_.clear(); node_storage_.clear(); node_in_edges_.clear(); + node_ptc_nums_.clear(); rr_node_metadata_.clear(); rr_edge_metadata_.clear(); rr_segments_.clear(); @@ -204,13 +210,62 @@ void RRGraphBuilder::build_in_edges() { } std::vector RRGraphBuilder::node_in_edges(RRNodeId node) const { - VTR_ASSERT(size_t(node) < node_storage_.size()); - if (is_incoming_edge_dirty_) { - VTR_LOG_ERROR("Incoming edges are not built yet in routing resource graph. Please call build_in_edges()."); - return std::vector(); - } - if (node_in_edges_.empty()) { - return std::vector(); - } - return node_in_edges_[node]; + VTR_ASSERT(size_t(node) < node_storage_.size()); + if (is_incoming_edge_dirty_) { + VTR_LOG_ERROR("Incoming edges are not built yet in routing resource graph. Please call build_in_edges()."); + return std::vector(); + } + if (node_in_edges_.empty()) { + return std::vector(); + } + return node_in_edges_[node]; +} + +void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id) { + VTR_ASSERT(size_t(node) < node_storage_.size()); + VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes"); + + size_t node_length = std::abs(node_storage_.node_xhigh(node) - node_storage_.node_xlow(node)) + + std::abs(node_storage_.node_yhigh(node) - node_storage_.node_ylow(node)); + if (node_length + 1 != node_ptc_nums_[node].size()) { + node_ptc_nums_[node].resize(node_length + 1); + } + + size_t offset = node_offset.x() - node_storage_.node_xlow(node) + node_offset.y() - node_storage_.node_ylow(node); + VTR_ASSERT(offset < node_ptc_nums_[node].size()); + + node_ptc_nums_[node][offset] = track_id; +} + +void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { + /* Compute the track id based on the (x, y) coordinate */ + size_t x_start = std::min(node_storage_.node_xlow(node), node_storage_.node_xhigh(node)); + size_t y_start = std::min(node_storage_.node_ylow(node), node_storage_.node_yhigh(node)); + std::vector node_x(std::abs(node_storage_.node_xlow(node) - node_storage_.node_xhigh(node)) + 1); + std::vector node_y(std::abs(node_storage_.node_ylow(node) - node_storage_.node_yhigh(node)) + 1); + + std::iota(node_x.begin(), node_x.end(), x_start); + std::iota(node_y.begin(), node_y.end(), y_start); + + VTR_ASSERT(size_t(std::max(node_storage_.node_xlow(node), node_storage_.node_xhigh(node))) == node_x.back()); + VTR_ASSERT(size_t(std::max(node_storage_.node_ylow(node), node_storage_.node_yhigh(node))) == node_y.back()); + + size_t itype = node_storage_.node_type(node); + + for (const size_t& x : node_x) { + for (const size_t& y : node_y) { + size_t ptc = node_storage_.node_ptc_num(node); + /* Routing channel nodes may have different ptc num + * Find the track ids using the x/y offset + * FIXME: Special case on assigning CHANX (x,y) should be changed to a natural way! + */ + if (CHANX == node_storage_.node_type(node)) { + ptc = node_ptc_nums_[node][x - node_storage_.node_xlow(node)]; + node_lookup_.add_node(node, y, x, CHANX, ptc); + } else if (CHANY == node_storage_.node_type(node)) { + ptc = node_ptc_nums_[node][y - node_storage_.node_ylow(node)]; + node_lookup_.add_node(node, x, y, CHANY, ptc); + } + } + } } diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 9f015f9c91b..d557e43ea01 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -47,6 +47,8 @@ class RRGraphBuilder { MetadataStorage>& rr_edge_metadata(); /** @brief Return a writable object fo the incoming edge storage */ vtr::vector>& node_in_edge_storage(); + /** @brief Return a writable object of the node ptc storage (for tileable routing resource graph) */ + vtr::vector>& node_ptc_storage(); /** @brief Return the size for rr_node_metadata */ inline size_t rr_node_metadata_size() const { @@ -197,7 +199,16 @@ class RRGraphBuilder { node_storage_.set_node_track_num(id, new_track_num); } - /** @brief set_ node_class_num() is designed for routing source and sinks, which are SOURCE and SINK nodes */ + /** @brief Add a track id for a given node base on the offset in coordinate, applicable only to CHANX and CHANY nodes. + * This API is used by tileable routing resource graph generator, which requires each routing track has a different + * track id depending their location in FPGA fabric. + */ + void add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id); + + /** @brief Update the node_lookup for a track node. This is applicable to tileable routing graph */ + void add_track_node_to_lookup(RRNodeId node); + + /** @brief set_node_class_num() is designed for routing source and sinks, which are SOURCE and SINK nodes */ inline void set_node_class_num(RRNodeId id, short new_class_num) { node_storage_.set_node_class_num(id, new_class_num); } @@ -376,6 +387,25 @@ class RRGraphBuilder { * By default, it is empty! Call build_in_edges() to construct it!!! */ vtr::vector> node_in_edges_; + /* Extra ptc number for each routing resource node. This is required by tileable routing resource graph. + * In a tileable routing architecture, routing tracks, e.g., CHANX and CHANY, follows a staggered organization. + * Hence, a routing track may appear in different routing channels, representing different ptc/track id. + * Here is an illustrative example of a X-direction routing track (CHANX) in INC direction, which is organized in staggered way. + * + * Coord(x,y) (1,0) (2,0) (3,0) (4,0) Another track (node) + * ptc=0 ------> ------> + * \ / + * ptc=1 ------> / + * \ / + * ptc=2 ------> / + * \ / + * ptc=3 -------> + * ^ ^ + * | | + * starting point ending point + */ + vtr::vector> node_ptc_nums_; + /** .. warning:: The Metadata should stay as an independent data structure than rest of the internal data, * e.g., node_lookup! */ /* Metadata is an extra data on rr-nodes and edges, respectively, that is not used by vpr diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index edddaed097d..225af722e5b 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -11,7 +11,8 @@ RRGraphView::RRGraphView(const t_rr_graph_storage& node_storage, const std::vector& rr_rc_data, const vtr::vector& rr_segments, const vtr::vector& rr_switch_inf, - const vtr::vector>& node_in_edges) + const vtr::vector>& node_in_edges, + const vtr::vector>& node_ptc_nums) : node_storage_(node_storage) , node_lookup_(node_lookup) , rr_node_metadata_(rr_node_metadata) @@ -20,7 +21,8 @@ RRGraphView::RRGraphView(const t_rr_graph_storage& node_storage, , rr_rc_data_(rr_rc_data) , rr_segments_(rr_segments) , rr_switch_inf_(rr_switch_inf) - , node_in_edges_(node_in_edges) { + , node_in_edges_(node_in_edges) + , node_ptc_nums_(node_ptc_nums) { } std::vector RRGraphView::node_in_edges(RRNodeId node) const { diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index e52654c03e6..e3c9959e91c 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -43,7 +43,8 @@ class RRGraphView { const std::vector& rr_rc_data, const vtr::vector& rr_segments, const vtr::vector& rr_switch_inf, - const vtr::vector>& node_in_edges); + const vtr::vector>& node_in_edges, + const vtr::vector>& node_ptc_nums); /* Disable copy constructors and copy assignment operator * This is to avoid accidental copy because it could be an expensive operation considering that the @@ -570,6 +571,9 @@ class RRGraphView { /** A list of incoming edges for each routing resource node. This can be built optionally, as required by applications. * By default, it is empty! Call build_in_edges() to construct it!!! */ const vtr::vector>& node_in_edges_; + + /** A list of extra ptc numbers for each routing resource node. See details in RRGraphBuilder class */ + const vtr::vector>& node_ptc_nums_; }; #endif diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 09d802e381a..7c5d0ce285f 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -194,7 +194,7 @@ struct DeviceContext : public Context { /* A read-only view of routing resource graph to be the ONLY database * for client functions: GUI, placer, router, timing analyzer etc. */ - RRGraphView rr_graph{rr_graph_builder.rr_nodes(), rr_graph_builder.node_lookup(), rr_graph_builder.rr_node_metadata(), rr_graph_builder.rr_edge_metadata(), rr_indexed_data, rr_rc_data, rr_graph_builder.rr_segments(), rr_graph_builder.rr_switch(), rr_graph_builder.node_in_edge_storage()}; + RRGraphView rr_graph{rr_graph_builder.rr_nodes(), rr_graph_builder.node_lookup(), rr_graph_builder.rr_node_metadata(), rr_graph_builder.rr_edge_metadata(), rr_indexed_data, rr_rc_data, rr_graph_builder.rr_segments(), rr_graph_builder.rr_switch(), rr_graph_builder.node_in_edge_storage(), rr_graph_builder.node_ptc_storage()}; /* Track ids for each rr_node in the rr_graph. * This is used by drawer for tileable routing resource graph diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 1d12d4c7705..be77036163b 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -739,22 +739,12 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_graph.node_ylow(rr_node_id), chan_coordinate.x(), chan_coordinate.y()); - /* Update node look-up */ - size_t xlow = std::min(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); - size_t xhigh = std::max(rr_graph.node_xlow(rr_node_id), rr_graph.node_xhigh(rr_node_id)); - size_t ylow = std::min(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); - size_t yhigh = std::max(rr_graph.node_ylow(rr_node_id), rr_graph.node_yhigh(rr_node_id)); - for (int ix = xlow; ix <= xhigh; ix++) { - for (int iy = ylow; iy <= yhigh; iy++) { - rr_graph_builder.node_lookup().add_node(rr_node_id, ix, iy, rr_graph.node_type(rr_node_id), itrack); - } - } /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ if ((rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id))) { rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.set_node_track_num(rr_node_id, itrack); + rr_graph_builder.add_node_track_num(rr_node_id, chan_coordinate, itrack); } /* Finish here, go to next */ } @@ -788,7 +778,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, /* Update track_ids */ rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.set_node_track_num(rr_node_id, itrack); + rr_graph_builder.add_node_track_num(rr_node_id, chan_coordindate, itrack); /* Finish here, go to next */ } } @@ -1092,4 +1082,11 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, reverse_dec_chan_rr_node_track_ids(rr_graph, rr_node_track_ids); + + /* Update node look-up for CHANX and CHANY nodes */ + for (const RRNodeId& rr_node_id : rr_graph.nodes()) { + if (CHANX == rr_graph.node_type(rr_node_id) || CHANY == rr_graph.node_type(rr_node_id)) { + rr_graph_builder.add_track_node_to_lookup(rr_node_id); + } + } } From 087cf293c01c59e0efe71194d25c4dccff184cac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Aug 2022 15:12:50 -0700 Subject: [PATCH 065/453] [vpr] typo --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index be77036163b..f5ffc6bfea7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -778,7 +778,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, /* Update track_ids */ rr_node_track_ids[rr_node_id].push_back(itrack); - rr_graph_builder.add_node_track_num(rr_node_id, chan_coordindate, itrack); + rr_graph_builder.add_node_track_num(rr_node_id, chan_coordinate, itrack); /* Finish here, go to next */ } } From 2a1b88c430a278db03a87e89fa8edbc4530fac0f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Aug 2022 16:49:11 -0700 Subject: [PATCH 066/453] [vpr] force more assertion --- libs/librrgraph/src/base/rr_graph_builder.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index edefb3c8445..3af5004396f 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -223,6 +223,7 @@ std::vector RRGraphBuilder::node_in_edges(RRNodeId node) const { void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id) { VTR_ASSERT(size_t(node) < node_storage_.size()); + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes"); size_t node_length = std::abs(node_storage_.node_xhigh(node) - node_storage_.node_xlow(node)) @@ -238,6 +239,8 @@ void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_o } void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { + VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Update track node look-up is only valid to CHANX/CHANY nodes"); + /* Compute the track id based on the (x, y) coordinate */ size_t x_start = std::min(node_storage_.node_xlow(node), node_storage_.node_xhigh(node)); size_t y_start = std::min(node_storage_.node_ylow(node), node_storage_.node_yhigh(node)); @@ -250,8 +253,6 @@ void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { VTR_ASSERT(size_t(std::max(node_storage_.node_xlow(node), node_storage_.node_xhigh(node))) == node_x.back()); VTR_ASSERT(size_t(std::max(node_storage_.node_ylow(node), node_storage_.node_yhigh(node))) == node_y.back()); - size_t itype = node_storage_.node_type(node); - for (const size_t& x : node_x) { for (const size_t& y : node_y) { size_t ptc = node_storage_.node_ptc_num(node); From b080eda506b08df62ef808adbab1b9770d1311f6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 26 Aug 2022 17:02:56 -0700 Subject: [PATCH 067/453] [vpr] fixed a bug which causes memory issues --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index f5ffc6bfea7..7421574705b 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -703,7 +703,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, RRNodeId node = rr_graph_builder.create_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); - rr_graph_builder.set_node_track_num(node, itrack); + rr_graph_builder.add_node_track_num(node, chan_coordinate, itrack); rr_node_track_ids[node].push_back(itrack); rr_graph_builder.set_node_capacity(node, 1); From ef79f28f18578f61b63783cd9116fc721da8d9f2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 27 Aug 2022 11:34:08 -0700 Subject: [PATCH 068/453] [lib] add sub_type and subFs support to arch parser --- libs/libarchfpga/src/read_xml_arch_file.cpp | 25 ++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index ba85a5a2804..5673b4531c9 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2718,8 +2718,9 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& // tag Cur = get_single_child(Node, "switch_block", loc_data); - expect_only_attributes(Cur, {"type", "fs"}, loc_data); + expect_only_attributes(Cur, {"type", "fs", "sub_type", "sub_fs"}, loc_data); Prop = get_attribute(Cur, "type", loc_data).value(); + /* Parse attribute 'type', representing the major connectivity pattern for switch blocks */ if (strcmp(Prop, "wilton") == 0) { arch->SBType = WILTON; } else if (strcmp(Prop, "universal") == 0) { @@ -2733,9 +2734,31 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), "Unknown property %s for switch block type x\n", Prop); } + /* Parse attribute 'sub_type', representing the minor connectivity pattern for switch blocks + * If not specified, the 'sub_type' is the same as major type + * This option is only valid for tileable routing resource graph builder + * Note that sub_type does not support custom switch block pattern!!! + * If 'sub_type' is specified, the custom switch block for 'type' is not allowed! + */ + std::string sub_type_str = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).as_string(""); + if (!sub_type_str.empty()) { + if (sub_type_str == std::string("wilton")) { + arch->SBSubType = WILTON; + } else if (sub_type_str == std::string("universal")) { + arch->SBSubType = UNIVERSAL; + } else if (sub_type_str == std::string("subset")) { + arch->SBSubType = SUBSET; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "Unknown property %s for switch block subtype x\n", sub_type_str.c_str()); + } + } else { + arch->SBSubType = arch->SBType; + } ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block); arch->Fs = get_attribute(Cur, "fs", loc_data, CUSTOM_SWITCHBLOCK_REQD).as_int(3); + arch->subFs = get_attribute(Cur, "sub_fs", loc_data, BoolToReqOpt(false)).as_int(arch->Fs); Cur = get_single_child(Node, "default_fc", loc_data, ReqOpt::OPTIONAL); if (Cur) { From 750091edc8ac117cc30b5da0b19a379f31ec8dc2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 27 Aug 2022 18:44:53 -0700 Subject: [PATCH 069/453] [vpr] added a new option to skip the synchornization between clustering and routing results --- vpr/src/base/read_options.cpp | 7 +++++++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_api.cpp | 29 +++++++++++++++++------------ 3 files changed, 25 insertions(+), 12 deletions(-) diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index d6e39e7b17d..e03993c842d 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2602,6 +2602,13 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.skip_sync_clustering_and_routing_results, "--skip_sync_clustering_and_routing_results") + .help( + "Select to skip the synchronization on clustering results based on routing optimization results." + "Note that when this sync-up is disabled, clustering results may be wrong (leading to incorrect bitstreams)!") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + auto& power_grp = parser.add_argument_group("power analysis options"); power_grp.add_argument(args.do_power, "--power") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 687f435f7e1..2be9ec3b22e 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -221,6 +221,7 @@ struct t_options { argparse::ArgValue post_synth_netlist_unconn_input_handling; argparse::ArgValue post_synth_netlist_unconn_output_handling; argparse::ArgValue write_timing_summary; + argparse::ArgValue skip_sync_clustering_and_routing_results; }; argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& args); diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index f161f0e65b6..078b8815310 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1260,7 +1260,8 @@ bool vpr_analysis_flow(t_vpr_setup& vpr_setup, const t_arch& Arch, const RouteSt VTR_LOG("*****************************************************************************************\n"); } - /* If routing is successful, apply post-routing annotations + /* If routing is successful and users do not force to skip the sync-up, + * - apply post-routing annotations * - apply logic block pin fix-up * * Note: @@ -1268,17 +1269,21 @@ bool vpr_analysis_flow(t_vpr_setup& vpr_setup, const t_arch& Arch, const RouteSt * for packer (default verbosity is set to 2 for compact logs) */ if (route_status.success()) { - sync_netlists_to_routing(g_vpr_ctx.device(), - g_vpr_ctx.mutable_atom(), - g_vpr_ctx.mutable_clustering(), - g_vpr_ctx.placement(), - g_vpr_ctx.routing(), - vpr_setup.PackerOpts.pack_verbosity > 2); - - std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing"; - write_packing_results_to_xml(vpr_setup.PackerOpts.global_clocks, - Arch.architecture_id, - post_routing_packing_output_file_name.c_str()); + if (analysis.opts.skip_sync_clustering_and_routing_results) { + sync_netlists_to_routing(g_vpr_ctx.device(), + g_vpr_ctx.mutable_atom(), + g_vpr_ctx.mutable_clustering(), + g_vpr_ctx.placement(), + g_vpr_ctx.routing(), + vpr_setup.PackerOpts.pack_verbosity > 2); + + std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing"; + write_packing_results_to_xml(vpr_setup.PackerOpts.global_clocks, + Arch.architecture_id, + post_routing_packing_output_file_name.c_str()); + } else { + VTR_LOG_WARN("Sychronization between packing and routing results is not applied due to users select to skip it\n"); + } } else { VTR_LOG_WARN("Sychronization between packing and routing results is not applied due to illegal circuit implementation\n"); } From f0cf714da1048671841b4bbfa0c457e2cd36ea9e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 27 Aug 2022 18:47:17 -0700 Subject: [PATCH 070/453] [vpr] syntax --- vpr/src/base/vpr_api.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 078b8815310..32933566c4c 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1269,7 +1269,7 @@ bool vpr_analysis_flow(t_vpr_setup& vpr_setup, const t_arch& Arch, const RouteSt * for packer (default verbosity is set to 2 for compact logs) */ if (route_status.success()) { - if (analysis.opts.skip_sync_clustering_and_routing_results) { + if (analysis_opts.skip_sync_clustering_and_routing_results) { sync_netlists_to_routing(g_vpr_ctx.device(), g_vpr_ctx.mutable_atom(), g_vpr_ctx.mutable_clustering(), From e36edc3a9aa3dea8b0c57c8eb2f4d688866c1704 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 27 Aug 2022 18:52:58 -0700 Subject: [PATCH 071/453] [vpr] add options --- vpr/src/base/SetupVPR.cpp | 2 ++ vpr/src/base/vpr_types.h | 1 + 2 files changed, 3 insertions(+) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index f850a31840f..08d9f1e17b7 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -648,6 +648,8 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.timing_update_type = Options.timing_update_type; analysis_opts.write_timing_summary = Options.write_timing_summary; + + analysis_opts.skip_sync_clustering_and_routing_results = Options.skip_sync_clustering_and_routing_results; } static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch) { diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 1a537e61ba0..6f505418cd5 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1258,6 +1258,7 @@ struct t_analysis_opts { std::string write_timing_summary; e_timing_update_type timing_update_type; + bool skip_sync_clustering_and_routing_results = false; }; // used to store NoC specific options, when supplied as an input by the user From b5d4f8ca41bc65ce35eae6ef3ec8ce1bf7f6a5a3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 27 Aug 2022 19:07:07 -0700 Subject: [PATCH 072/453] [vpr] typo --- vpr/src/base/vpr_api.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 32933566c4c..224a59500c9 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1269,7 +1269,7 @@ bool vpr_analysis_flow(t_vpr_setup& vpr_setup, const t_arch& Arch, const RouteSt * for packer (default verbosity is set to 2 for compact logs) */ if (route_status.success()) { - if (analysis_opts.skip_sync_clustering_and_routing_results) { + if (!analysis_opts.skip_sync_clustering_and_routing_results) { sync_netlists_to_routing(g_vpr_ctx.device(), g_vpr_ctx.mutable_atom(), g_vpr_ctx.mutable_clustering(), From 78f8c821131c52d424597c391a3bf308fe63452b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Sep 2022 14:07:36 -0700 Subject: [PATCH 073/453] [vpr] adapt to the API change on check_rr_graph() --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index b1bef8021d3..de96104dd1b 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -298,8 +298,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ "Fundamental errors occurred when validating rr_graph object!\n"); } - /* No clock network support yet */ - check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, device_ctx.chan_width, GRAPH_UNIDIR, OPEN); + /* No clock network support yet; Does not support flatten rr_graph yet */ + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, device_ctx.chan_width, GRAPH_UNIDIR, OPEN, false); /************************************************************************ * Free all temp stucts From ce3173cef27b8dc16576709da7894fde66e1e2ce Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Sep 2022 15:09:09 -0700 Subject: [PATCH 074/453] [vpr] remove GSB graph matching APIs --- vpr/src/tileable_rr_graph/rr_chan.cpp | 30 ---- vpr/src/tileable_rr_graph/rr_chan.h | 1 - vpr/src/tileable_rr_graph/rr_gsb.cpp | 249 -------------------------- vpr/src/tileable_rr_graph/rr_gsb.h | 46 +---- 4 files changed, 1 insertion(+), 325 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp index 2f69bd659b1..c6a991ea524 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.cpp +++ b/vpr/src/tileable_rr_graph/rr_chan.cpp @@ -66,36 +66,6 @@ RRSegmentId RRChan::get_node_segment(const size_t& track_num) const { return node_segments_[track_num]; } -/* evaluate if two RRChan is mirror to each other */ -bool RRChan::is_mirror(const RRGraphView& rr_graph, const RRChan& cand) const { - /* If any following element does not match, it is not mirror */ - /* 1. type */ - if (this->get_type() != cand.get_type()) { - return false; - } - /* 2. track_width */ - if (this->get_chan_width() != cand.get_chan_width()) { - return false; - } - /* 3. for each node */ - for (size_t inode = 0; inode < this->get_chan_width(); ++inode) { - /* 3.1 check node type */ - if (rr_graph.node_type(this->get_node(inode)) != rr_graph.node_type(cand.get_node(inode))) { - return false; - } - /* 3.2 check node directionality */ - if (rr_graph.node_direction(this->get_node(inode)) != rr_graph.node_direction(cand.get_node(inode))) { - return false; - } - /* 3.3 check node segment */ - if (this->get_node_segment(inode) != cand.get_node_segment(inode)) { - return false; - } - } - - return true; -} - /* Get a list of segments used in this routing channel */ std::vector RRChan::get_segment_ids() const { std::vector seg_list; diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h index 2e40e06c3d2..5ba9bc09af5 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.h +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -46,7 +46,6 @@ class RRChan { RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */ RRSegmentId get_node_segment(const RRNodeId& node) const; RRSegmentId get_node_segment(const size_t& track_num) const; - bool is_mirror(const RRGraphView& rr_graph, const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */ std::vector get_segment_ids() const; /* Get a list of segments used in this routing channel */ std::vector get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const; /* Get a list of segments used in this routing channel */ public: /* Mutators */ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 525b3ca5576..cad8fdb32d4 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -343,37 +343,6 @@ bool RRGSB::is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, return (-1 != index); } -/* check if the candidate CB is a mirror of the current one */ -bool RRGSB::is_cb_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const { - /* Check if channel width is the same */ - if (get_cb_chan_width(cb_type) != cand.get_cb_chan_width(cb_type)) { - return false; - } - - enum e_side chan_side = get_cb_chan_side(cb_type); - - /* check the numbers/directionality of channel rr_nodes */ - if (false == chan_node_[size_t(chan_side)].is_mirror(rr_graph, cand.chan_node_[size_t(chan_side)])) { - return false; - } - - /* check the equivalence of ipins */ - std::vector ipin_side = get_cb_ipin_sides(cb_type); - for (size_t side = 0; side < ipin_side.size(); ++side) { - /* Ensure we have the same number of IPINs on this side */ - if (get_num_ipin_nodes(ipin_side[side]) != cand.get_num_ipin_nodes(ipin_side[side])) { - return false; - } - for (size_t inode = 0; inode < get_num_ipin_nodes(ipin_side[side]); ++inode) { - if (false == is_cb_node_mirror(rr_graph, cand, cb_type, ipin_side[side], inode)) { - return false; - } - } - } - - return true; -} - /* check if the CB exist in this GSB */ bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const { /* if channel width is zero, there is no CB */ @@ -493,87 +462,6 @@ bool RRGSB::is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) con return true; } -/* check if all the routing segments of a side of candidate SB is a mirror of the current one */ -bool RRGSB::is_sb_side_segment_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side, const RRSegmentId& seg_id) const { - /* Create a side manager */ - SideManager side_manager(side); - - /* Make sure both Switch blocks has this side!!! */ - VTR_ASSERT(side_manager.to_size_t() < get_num_sides()); - VTR_ASSERT(side_manager.to_size_t() < cand.get_num_sides()); - - /* check the numbers/directionality of channel rr_nodes */ - /* Ensure we have the same channel width on this side */ - if (get_chan_width(side) != cand.get_chan_width(side)) { - return false; - } - for (size_t itrack = 0; itrack < get_chan_width(side); ++itrack) { - /* Bypass unrelated segments */ - if (seg_id != get_chan_node_segment(side, itrack)) { - continue; - } - /* Check the directionality of each node */ - if (get_chan_node_direction(side, itrack) != cand.get_chan_node_direction(side, itrack)) { - return false; - } - /* Check the track_id of each node - * ptc is not necessary, we care the connectivity! - */ - /* For OUT_PORT rr_node, we need to check fan-in */ - if (OUT_PORT != get_chan_node_direction(side, itrack)) { - continue; /* skip IN_PORT */ - } - - if (false == is_sb_node_mirror(rr_graph, cand, side, itrack)) { - return false; - } - } - - /* check the numbers of opin_rr_nodes */ - if (get_num_opin_nodes(side) != cand.get_num_opin_nodes(side)) { - return false; - } - - /* check the numbers of ipin_rr_nodes */ - if (get_num_ipin_nodes(side) != cand.get_num_ipin_nodes(side)) { - return false; - } - - return true; -} - -/* check if a side of candidate SB is a mirror of the current one */ -bool RRGSB::is_sb_side_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side) const { - /* get a list of segments */ - std::vector seg_ids = chan_node_[size_t(side)].get_segment_ids(); - - for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { - if (false == is_sb_side_segment_mirror(rr_graph, cand, side, seg_ids[iseg])) { - return false; - } - } - - return true; -} - -/* check if the candidate SB is a mirror of the current one */ -bool RRGSB::is_sb_mirror(const RRGraphView& rr_graph, const RRGSB& cand) const { - /* check the numbers of sides */ - if (get_num_sides() != cand.get_num_sides()) { - return false; - } - - /* check the numbers/directionality of channel rr_nodes */ - for (size_t side = 0; side < get_num_sides(); ++side) { - SideManager side_manager(side); - if (false == is_sb_side_mirror(rr_graph, cand, side_manager.get_side())) { - return false; - } - } - - return true; -} - /* Public Accessors: Cooridinator conversion */ /* get the x coordinate of this GSB */ @@ -947,143 +835,6 @@ void RRGSB::clear_one_side(const e_side& node_side) { /************************************************************************ * Internal Accessors: identify mirrors ***********************************************************************/ - -/* check if two rr_nodes have a similar set of drive_rr_nodes - * for each drive_rr_node: - * 1. CHANX or CHANY: should have the same side and index - * 2. OPIN or IPIN: should have the same side and index - * 3. each drive_rr_switch should be the same - */ -bool RRGSB::is_sb_node_mirror(const RRGraphView& rr_graph, - const RRGSB& cand, - const e_side& node_side, - const size_t& track_id) const { - /* Ensure rr_nodes are either the output of short-connection or multiplexer */ - bool is_short_conkt = this->is_sb_node_passing_wire(rr_graph, node_side, track_id); - - if (is_short_conkt != cand.is_sb_node_passing_wire(rr_graph, node_side, track_id)) { - return false; - } - - if (true == is_short_conkt) { - /* Since, both are pass wires, - * The two node should be equivalent - * we can return here - */ - return true; - } - - /* Use unsorted/sorted edges */ - std::vector node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id); - std::vector cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id); - - /* For non-passing wires, check driving rr_nodes */ - if (node_in_edges.size() != cand_node_in_edges.size()) { - return false; - } - - VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); - - for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { - RREdgeId src_edge = node_in_edges[iedge]; - RREdgeId src_cand_edge = cand_node_in_edges[iedge]; - RRNodeId src_node = rr_graph.edge_src_node(src_edge); - RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge); - /* node type should be the same */ - if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) { - return false; - } - /* switch type should be the same */ - if (rr_graph.edge_switch(src_edge) != rr_graph.edge_switch(src_cand_edge)) { - return false; - } - int src_node_id, des_node_id; - enum e_side src_node_side, des_node_side; - this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id); - cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id); - if (src_node_id != des_node_id) { - return false; - } - if (src_node_side != des_node_side) { - return false; - } - } - - return true; -} - -/* check if two ipin_nodes have a similar set of drive_rr_nodes - * for each drive_rr_node: - * 1. CHANX or CHANY: should have the same side and index - * 2. each drive_rr_switch should be the same - */ -bool RRGSB::is_cb_node_mirror(const RRGraphView& rr_graph, - const RRGSB& cand, - const t_rr_type& cb_type, - const e_side& node_side, - const size_t& node_id) const { - /* Ensure rr_nodes are either the output of short-connection or multiplexer */ - RRNodeId node = this->get_ipin_node(node_side, node_id); - RRNodeId cand_node = cand.get_ipin_node(node_side, node_id); - - if (rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size()) { - return false; - } - - std::vector node_in_edges; - for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { - node_in_edges.push_back(edge); - } - - std::vector cand_node_in_edges; - for (const RREdgeId& edge : rr_graph.node_in_edges(cand_node)) { - cand_node_in_edges.push_back(edge); - } - VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size()); - - for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) { - RREdgeId src_edge = node_in_edges[iedge]; - RREdgeId src_cand_edge = cand_node_in_edges[iedge]; - RRNodeId src_node = rr_graph.edge_src_node(src_edge); - RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge); - /* node type should be the same */ - if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) { - return false; - } - /* switch type should be the same */ - if (rr_graph.edge_switch(src_edge) != rr_graph.edge_switch(src_cand_edge)) { - return false; - } - - int src_node_id, des_node_id; - enum e_side src_node_side, des_node_side; - enum e_side chan_side = get_cb_chan_side(cb_type); - switch (rr_graph.node_type(src_node)) { - case CHANX: - case CHANY: - /* if the drive rr_nodes are routing tracks, find index */ - src_node_id = this->get_chan_node_index(chan_side, src_node); - des_node_id = cand.get_chan_node_index(chan_side, src_cand_node); - break; - case OPIN: - this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id); - cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id); - if (src_node_side != des_node_side) { - return false; - } - break; - default: - VTR_LOG("Invalid type of drive_rr_nodes for ipin_node!\n"); - exit(1); - } - if (src_node_id != des_node_id) { - return false; - } - } - - return true; -} - size_t RRGSB::get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const { VTR_ASSERT(validate_side(node_side)); diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 00caa876d29..241007c8490 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -117,9 +117,6 @@ class RRGSB { bool is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side) const; public: /* Accessors: to identify mirrors */ - /* check if the candidate SB is a mirror of the current one */ - bool is_cb_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const; - /* check if the connect block exists in the GSB */ bool is_cb_exist(const t_rr_type& cb_type) const; @@ -133,37 +130,7 @@ class RRGSB { * on being a mirror of the current one */ bool is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) const; - - /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ - bool is_sb_side_segment_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side, const RRSegmentId& seg_id) const; - - /* check if a side of candidate SB is a mirror of the current one - * Check the specified side of two switch blocks: - * 1. Number of channel/opin/ipin rr_nodes are same - * For channel rr_nodes - * 2. check if their track_ids (ptc_num) are same - * 3. Check if the switches (ids) are same - * For opin/ipin rr_nodes, - * 4. check if their parent type_descriptors same, - * 5. check if pin class id and pin id are same - * If all above are satisfied, the side of the two switch blocks are mirrors! - */ - bool is_sb_side_mirror(const RRGraphView& rr_graph, const RRGSB& cand, const e_side& side) const; - - /* check if the candidate SB is a mirror of the current one - * Idenify mirror Switch blocks - * Check each two switch blocks: - * 1. Number of channel/opin/ipin rr_nodes are same - * For channel rr_nodes - * 2. check if their track_ids (ptc_num) are same - * 3. Check if the switches (ids) are same - * For opin/ipin rr_nodes, - * 4. check if their parent type_descriptors same, - * 5. check if pin class id and pin id are same - * If all above are satisfied, the two switch blocks are mirrors! - */ - bool is_sb_mirror(const RRGraphView& rr_graph, const RRGSB& cand) const; - + public: /* Cooridinator conversion and output */ size_t get_x() const; /* get the x coordinate of this switch block */ size_t get_y() const; /* get the y coordinate of this switch block */ @@ -230,17 +197,6 @@ class RRGSB { const size_t& track_id); private: /* internal functions */ - bool is_sb_node_mirror(const RRGraphView& rr_graph, - const RRGSB& cand, - const e_side& node_side, - const size_t& track_id) const; - - bool is_cb_node_mirror(const RRGraphView& rr_graph, - const RRGSB& cand, - const t_rr_type& cb_type, - const e_side& node_side, - const size_t& node_id) const; - size_t get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const; private: /* internal validators */ From 6a515ff79beecc3b4ce1830f072b0e441420e19c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Sep 2022 16:19:34 -0700 Subject: [PATCH 075/453] [vpr] add missing APi required by latest openfpga --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 4 ++++ vpr/src/tileable_rr_graph/rr_gsb.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index cad8fdb32d4..9c811a13de1 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -61,6 +61,10 @@ size_t RRGSB::get_max_chan_width() const { return max_chan_width; } +const RRGSB::RRChan& chan(const e_side& chan_side) const { + return chan_node_[size_t(chan_side)]; +} + /* Get the number of routing tracks of a X/Y-direction CB */ size_t RRGSB::get_cb_chan_width(const t_rr_type& cb_type) const { return get_chan_width(get_cb_chan_side(cb_type)); diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 241007c8490..854bc37eae1 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -67,6 +67,9 @@ class RRGSB { /* Get the number of routing tracks of a X/Y-direction CB */ size_t get_cb_chan_width(const t_rr_type& cb_type) const; + /* Return read-only object of the routing channels with a given side */ + const RRChan& chan(const e_side& chan_side) const; + /* Get the sides of CB ipins in the array */ std::vector get_cb_ipin_sides(const t_rr_type& cb_type) const; From abc6555a0b096ec7237094471d3f4cfaa679ffa0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Sep 2022 16:23:43 -0700 Subject: [PATCH 076/453] [vpr] syntax --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 9c811a13de1..c21f093983f 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -61,7 +61,7 @@ size_t RRGSB::get_max_chan_width() const { return max_chan_width; } -const RRGSB::RRChan& chan(const e_side& chan_side) const { +const RRChan& RRGSB::chan(const e_side& chan_side) const { return chan_node_[size_t(chan_side)]; } From 3b758f01bb615ffaaccb99df8737219d4cd7494a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Sep 2022 14:59:04 -0700 Subject: [PATCH 077/453] [lib] now arch parser supports subtile index when parsing pin location assignments --- libs/libarchfpga/src/read_xml_arch_file.cpp | 168 +++++++++++++++++--- 1 file changed, 150 insertions(+), 18 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 20aececca82..9af15bd42b7 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -119,6 +119,11 @@ static std::pair ProcessPinString(pugi::xml_node Locations, T type, const char* pin_loc_string, const pugiutil::loc_data& loc_data); +template +static std::pair ProcessInstanceString(pugi::xml_node Locations, + T type, + const char* pin_loc_string, + const pugiutil::loc_data& loc_data); /* Process XML hierarchy */ static void ProcessTiles(pugi::xml_node Node, @@ -609,10 +614,15 @@ static void LoadPinLoc(pugi::xml_node Locations, &sub_tile, token.c_str(), loc_data); - + /* Get the offset in the capacity range */ + auto capacity_range = ProcessInstanceString(Locations, + &sub_tile, + token.c_str(), + loc_data); + VTR_ASSERT(0 <= capacity_range.first && capacity_range.second < sub_tile_capacity); for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) { VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); - for (int capacity = 0; capacity < sub_tile_capacity; ++capacity) { + for (int capacity = capacity_range.first; capacity <= capacity_range.second; ++capacity) { int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; type->pinloc[width][height][side][physical_pin_index] = true; @@ -639,6 +649,99 @@ static void LoadPinLoc(pugi::xml_node Locations, } } +/* Parse the string to extract instance range, e.g., io[4:7] -> (4, 7) + * If no instance range is explicitly defined, we assume the range of type capacity, i.e., (0, capacity - 1) */ +template +static std::pair ProcessInstanceString(pugi::xml_node Locations, + T type, + const char* pin_loc_string, + const pugiutil::loc_data& loc_data) { + int num_tokens; + auto tokens = GetTokensFromString(pin_loc_string, &num_tokens); + + int token_index = 0; + auto token = tokens[token_index]; + + if (token.type != TOKEN_STRING || 0 != strcmp(token.data, type->name)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Wrong physical type name of the port: %s\n", pin_loc_string); + } + + token_index++; + token = tokens[token_index]; + + int first_inst = 0; + int last_inst = type->capacity - 1; + + /* If there is a dot, such as io.input[0:3], it indicates the full range of the capacity, the default value should be returned */ + if (token.type == TOKEN_DOT) { + freeTokens(tokens, num_tokens); + return std::make_pair(first_inst, last_inst); + } + + /* If the string contains index for capacity range, e.g., io[3:3].in[0:5], we skip the capacity range here. */ + if (token.type != TOKEN_OPEN_SQUARE_BRACKET) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No open square bracket present: %s\n", pin_loc_string); + } + + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_INT) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No integer to indicate least significant instance index: %s\n", pin_loc_string); + } + + first_inst = vtr::atoi(token.data); + + token_index++; + token = tokens[token_index]; + + // Single pin is specified + if (token.type != TOKEN_COLON) { + if (token.type != TOKEN_CLOSE_SQUARE_BRACKET) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No closing bracket: %s\n", pin_loc_string); + } + + token_index++; + + if (token_index != num_tokens) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "instance of pin location should be completed, but more tokens are present: %s\n", pin_loc_string); + } + + freeTokens(tokens, num_tokens); + return std::make_pair(first_inst, first_inst); + } + + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_INT) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No integer to indicate most significant instance index: %s\n", pin_loc_string); + } + + last_inst = vtr::atoi(token.data); + + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_CLOSE_SQUARE_BRACKET) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No closed square bracket: %s\n", pin_loc_string); + } + + if (first_inst > last_inst) { + std::swap(first_inst, last_inst); + } + + freeTokens(tokens, num_tokens); + return std::make_pair(first_inst, last_inst); +} + template static std::pair ProcessPinString(pugi::xml_node Locations, T type, @@ -658,6 +761,20 @@ static std::pair ProcessPinString(pugi::xml_node Locations, token_index++; token = tokens[token_index]; + /* If the string contains index for capacity range, e.g., io[3:3].in[0:5], we skip the capacity range here. */ + if (token.type == TOKEN_OPEN_SQUARE_BRACKET) { + while (token.type != TOKEN_CLOSE_SQUARE_BRACKET) { + token_index++; + token = tokens[token_index]; + if (token_index == num_tokens) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Found an open '[' but miss close ']' of the port: %s\n", pin_loc_string); + } + } + token_index++; + token = tokens[token_index]; + } + if (token.type != TOKEN_DOT) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "No dot is present to separate type name and port name: %s\n", pin_loc_string); @@ -3314,19 +3431,30 @@ static void ProcessPinLocations(pugi::xml_node Locations, //Verify that all top-level pins have had their locations specified - //Record all the specified pins - std::map> port_pins_with_specified_locations; + //Record all the specified pins, (capacity, port_name, index) + std::map>> port_pins_with_specified_locations; for (int w = 0; w < PhysicalTileType->width; ++w) { for (int h = 0; h < PhysicalTileType->height; ++h) { for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) { for (auto token : pin_locs->assignments[sub_tile_index][w][h][side]) { InstPort inst_port(token.c_str()); - //A pin specification should contain only the block name, and not any instace count information + //A pin specification may contain instance count, but should be in the range of capacity + int inst_lsb = 0; + int inst_msb = PhysicalTileType->capacity - 1; if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "Pin location specification '%s' should not contain an instance range (should only be the block name)", - token.c_str()); + /* Extract range numbers */ + inst_lsb = inst_port.instance_low_index(); + inst_msb = inst_port.instance_high_index(); + if (inst_lsb > inst_msb) { + std::swap(inst_lsb, inst_msb); + } + /* Check if we have a valid range */ + if (inst_lsb < 0 || inst_msb > PhysicalTileType->capacity - 1) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Pin location specification '%s' contain an out-of-range instance. Expect [%d:%d]", + token.c_str(), 0 , PhysicalTileType->capacity - 1); + } } //Check that the block name matches @@ -3363,9 +3491,11 @@ static void ProcessPinLocations(pugi::xml_node Locations, VTR_ASSERT(pin_low_idx >= 0); VTR_ASSERT(pin_high_idx >= 0); - for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) { - //Record that the pin has it's location specified - port_pins_with_specified_locations[inst_port.port_name()].insert(ipin); + for (int iinst = inst_lsb; iinst <= inst_msb; ++iinst) { + for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) { + //Record that the pin has it's location specified + port_pins_with_specified_locations[iinst][inst_port.port_name()].insert(ipin); + } } } } @@ -3373,13 +3503,15 @@ static void ProcessPinLocations(pugi::xml_node Locations, } //Check for any pins missing location specs - for (const auto& port : SubTile->ports) { - for (int ipin = 0; ipin < port.num_pins; ++ipin) { - if (!port_pins_with_specified_locations[port.name].count(ipin)) { - //Missing - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "Pin '%s.%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", - SubTile->name, port.name, ipin); + for (int iinst = 0; iinst < PhysicalTileType->capacity; ++iinst) { + for (const auto& port : SubTile->ports) { + for (int ipin = 0; ipin < port.num_pins; ++ipin) { + if (!port_pins_with_specified_locations[port.name].count(ipin)) { + //Missing + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", + SubTile->name, iinst, port.name, ipin); + } } } } From f97b7e2e03c3434bad65ca3a15d8a41ccf225fcc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Sep 2022 15:02:21 -0700 Subject: [PATCH 078/453] [lib] syntax --- libs/libarchfpga/src/read_xml_arch_file.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 9af15bd42b7..75557afd6e1 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -615,10 +615,10 @@ static void LoadPinLoc(pugi::xml_node Locations, token.c_str(), loc_data); /* Get the offset in the capacity range */ - auto capacity_range = ProcessInstanceString(Locations, - &sub_tile, - token.c_str(), - loc_data); + auto capacity_range = ProcessInstanceString(Locations, + &sub_tile, + token.c_str(), + loc_data); VTR_ASSERT(0 <= capacity_range.first && capacity_range.second < sub_tile_capacity); for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) { VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); @@ -3506,7 +3506,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, for (int iinst = 0; iinst < PhysicalTileType->capacity; ++iinst) { for (const auto& port : SubTile->ports) { for (int ipin = 0; ipin < port.num_pins; ++ipin) { - if (!port_pins_with_specified_locations[port.name].count(ipin)) { + if (!port_pins_with_specified_locations[iinst][port.name].count(ipin)) { //Missing archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", From 7994e804e9ea2be7d65b806699ed2c7692e878b3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Sep 2022 15:09:41 -0700 Subject: [PATCH 079/453] [lib] syntax --- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 75557afd6e1..edf257f0e3d 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -671,7 +671,7 @@ static std::pair ProcessInstanceString(pugi::xml_node Locations, token = tokens[token_index]; int first_inst = 0; - int last_inst = type->capacity - 1; + int last_inst = type->capacity.total() - 1; /* If there is a dot, such as io.input[0:3], it indicates the full range of the capacity, the default value should be returned */ if (token.type == TOKEN_DOT) { From 7482107eb3bc39a25eac2be2c49e8ae331675ee9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 16 Sep 2022 21:41:12 -0700 Subject: [PATCH 080/453] [lib] add an option to avoid sorting edges when creating them. This is to check whether this is the reason causing back-compatibility issues --- libs/librrgraph/src/base/rr_graph_builder.cpp | 6 ++++-- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- .../tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 3af5004396f..7ddf6f96e67 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -186,9 +186,11 @@ void RRGraphBuilder::create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_sw is_incoming_edge_dirty_ = true; } -void RRGraphBuilder::build_edges() { +void RRGraphBuilder::build_edges(const bool& uniquify) { std::sort(edges_to_build_.begin(), edges_to_build_.end()); - edges_to_build_.erase(std::unique(edges_to_build_.begin(), edges_to_build_.end()), edges_to_build_.end()); + if (uniquify) { + edges_to_build_.erase(std::unique(edges_to_build_.begin(), edges_to_build_.end()), edges_to_build_.end()); + } alloc_and_load_edges(&edges_to_build_); edges_to_build_.clear(); is_edge_dirty_ = false; diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index fb26f5e88de..228a7e94b5c 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -225,7 +225,7 @@ class RRGraphBuilder { /** @brief Allocate and build actual edges in storage. * Once called, the cached edges will be uniquified and added to routing resource nodes, * while the cache will be empty once build-up is accomplished */ - void build_edges(); + void build_edges(const bool& uniquify = true); /** @brief Allocate and build incoming edges for each node. * By default, no incoming edges are kept in storage, to be memory efficient */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 195c5eabe9f..61b52b72190 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -136,7 +136,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, track2ipin_map, opin2track_map, sb_conn, rr_node_driver_switches); /* Finish this GSB, go to the next*/ - rr_graph_builder.build_edges(); + rr_graph_builder.build_edges(false); } } } From eb75a5a3a1c26f98261d6625aeb7df8b656548b5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 17 Sep 2022 09:51:25 -0700 Subject: [PATCH 081/453] [vtr] count number of edges before creating them; Found some mismatches in edge count by comparing the current branch to the OpenFPGA's version. --- .../tileable_rr_graph_edge_builder.cpp | 16 +++++++++++----- .../tileable_rr_graph/tileable_rr_graph_gsb.cpp | 6 +++++- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 61b52b72190..fc43b4bb955 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -22,7 +22,8 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids) { + const DeviceGrid& grids, + size_t& num_edges_to_create) { for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non OPIN nodes */ if (OPIN != rr_graph.node_type(node)) { @@ -41,6 +42,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, /* add edges to the src_node */ rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node]); + num_edges_to_create++; } /* Allocate edges for all the source nodes */ rr_graph_builder.build_edges(); @@ -53,7 +55,8 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids) { + const DeviceGrid& grids, + size_t& num_edges_to_create) { for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non IPIN nodes */ if (IPIN != rr_graph.node_type(node)) { @@ -72,6 +75,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, /* add edges to connect the IPIN node to SINK nodes */ rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); + num_edges_to_create++; } /* Allocate edges for all the source nodes */ rr_graph_builder.build_edges(); @@ -100,9 +104,10 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const e_switch_block_type& sb_subtype, const int& subFs, const bool& wire_opposite_side) { + size_t num_edges_to_create = 0; /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ - build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids); - build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids); + build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, num_edges_to_create); + build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, num_edges_to_create); vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); @@ -134,11 +139,12 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* Build edges for a GSB */ build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, track2ipin_map, opin2track_map, - sb_conn, rr_node_driver_switches); + sb_conn, rr_node_driver_switches, num_edges_to_create); /* Finish this GSB, go to the next*/ rr_graph_builder.build_edges(false); } } + VTR_LOG("Number of edges to create: %ld\n", num_edges_to_create); } /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index a33eda105d4..c89f6b51bd8 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -917,7 +917,8 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, - const vtr::vector& rr_node_driver_switches) { + const vtr::vector& rr_node_driver_switches, + size_t& num_edges_to_create) { /* Walk through each sides */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager side_manager(side); @@ -931,6 +932,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, /* add edges to the opin_node */ for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) { rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]); + num_edges_to_create++; } } @@ -945,6 +947,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { rr_graph_builder.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]); + num_edges_to_create++; } } } @@ -954,6 +957,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { rr_graph_builder.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]); + num_edges_to_create++; } } } From 5d409cba6becd237e0ddb11c4b9fead25ba9993d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 17 Sep 2022 09:56:57 -0700 Subject: [PATCH 082/453] [vpr] syntax --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 6 ++++-- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 8e780521da3..9e56e33ca19 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -44,11 +44,13 @@ void build_rr_graph_direct_connections(const RRGraphView& rr_graph, void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids); + const DeviceGrid& grids, + size_t& num_edges_to_create); void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, - const DeviceGrid& grids); + const DeviceGrid& grids, + size_t& num_edges_to_create); #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 43224fbdbc7..9e1d63963ed 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -51,7 +51,8 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, - const vtr::vector& rr_node_driver_switches); + const vtr::vector& rr_node_driver_switches, + size_t& num_edges); t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, From 6dff2000ab567207926eb0123efadb3ae1e3b5a1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 17 Sep 2022 10:21:58 -0700 Subject: [PATCH 083/453] [vpr] add more debugging info about edge count for tileable routing resource graph builder --- .../tileable_rr_graph_edge_builder.cpp | 10 ++++++++-- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 9 ++++++--- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index fc43b4bb955..f9de406966b 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -24,6 +24,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, size_t& num_edges_to_create) { + size_t& edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non OPIN nodes */ if (OPIN != rr_graph.node_type(node)) { @@ -42,10 +43,12 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, /* add edges to the src_node */ rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node]); - num_edges_to_create++; + edge_count++; } /* Allocate edges for all the source nodes */ rr_graph_builder.build_edges(); + VTR_LOG("Number of edges to create for source nodes: %ld\n", edge_count); + num_edges_to_create += edge_count; } /************************************************************************ @@ -57,6 +60,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, size_t& num_edges_to_create) { + size_t& edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non IPIN nodes */ if (IPIN != rr_graph.node_type(node)) { @@ -75,10 +79,12 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, /* add edges to connect the IPIN node to SINK nodes */ rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); - num_edges_to_create++; + edge_count++; } /* Allocate edges for all the source nodes */ rr_graph_builder.build_edges(); + VTR_LOG("Number of edges to create for sink nodes: %ld\n", edge_count); + num_edges_to_create += edge_count; } /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index c89f6b51bd8..4e174348808 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -919,6 +919,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const t_track2track_map& track2track_map, const vtr::vector& rr_node_driver_switches, size_t& num_edges_to_create) { + size_t edge_count = 0; /* Walk through each sides */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager side_manager(side); @@ -932,7 +933,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, /* add edges to the opin_node */ for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) { rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]); - num_edges_to_create++; + edge_count++; } } @@ -947,7 +948,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { rr_graph_builder.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]); - num_edges_to_create++; + edge_count++; } } } @@ -957,10 +958,12 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { rr_graph_builder.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]); - num_edges_to_create++; + edge_count++; } } } + VTR_LOG("Number of edges to create for gsb[%ld][%ld]: %ld\n", rr_gsb.get_x(), rr_gsb.get_y(), edge_count); + num_edges_to_create += edge_count; } /************************************************************************ From 1ba0c0ed5aaba67ec56c08aae7d4e72acd0f1cb3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 17 Sep 2022 10:25:17 -0700 Subject: [PATCH 084/453] [vpr] syntax --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index f9de406966b..f12fbcc59a1 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -24,7 +24,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, size_t& num_edges_to_create) { - size_t& edge_count = 0; + size_t edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non OPIN nodes */ if (OPIN != rr_graph.node_type(node)) { @@ -60,7 +60,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, size_t& num_edges_to_create) { - size_t& edge_count = 0; + size_t edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non IPIN nodes */ if (IPIN != rr_graph.node_type(node)) { From 4966634f606d0df1f4eb94442aef3d2242dc7d13 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 17 Sep 2022 22:23:10 -0700 Subject: [PATCH 085/453] [lib] Fixed a bug where subFs was not copied to det_routing arch parameters --- vpr/src/base/SetupVPR.cpp | 2 ++ vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 8f88140f136..7f6bd0c7dfc 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -350,9 +350,11 @@ static void SetupSwitches(const t_arch& Arch, static void SetupRoutingArch(const t_arch& Arch, t_det_routing_arch* RoutingArch) { RoutingArch->switch_block_type = Arch.SBType; + RoutingArch->switch_block_type = Arch.SBSubType; RoutingArch->R_minW_nmos = Arch.R_minW_nmos; RoutingArch->R_minW_pmos = Arch.R_minW_pmos; RoutingArch->Fs = Arch.Fs; + RoutingArch->subFs = Arch.subFs; RoutingArch->directionality = BI_DIRECTIONAL; if (Arch.Segments.size()) { RoutingArch->directionality = Arch.Segments[0].directionality; diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 4e174348808..6e5d9407411 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -374,6 +374,8 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, /* to_track should be OUT_PORT */ VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index)); + VTR_LOG("Consider a connection from pass tracks %d on side %s to track node %ld on side %s\n", from_track_index, SIDE_STRING[from_side], size_t(to_track_node), SIDE_STRING[to_side]); + /* Check if the to_track_node is already in the list ! */ std::vector::iterator it = std::find(track2track_map[from_side_index][from_track_index].begin(), track2track_map[from_side_index][from_track_index].end(), @@ -383,6 +385,7 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, } /* Clear, we should add to the list */ track2track_map[from_side_index][from_track_index].push_back(to_track_node); + VTR_LOG("Built a connection from pass tracks %d on side %s to track node %ld on side %s\n", from_track_index, SIDE_STRING[from_side], size_t(to_track_node), SIDE_STRING[to_side]); } } } @@ -519,6 +522,9 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks, * TODO: This can be improved with different patterns! */ + for (e_side curr_side : SIDES) { + VTR_LOG("Number of pass tracks %d on side %s\n", pass_tracks[size_t(curr_side)].size(), SIDE_STRING[curr_side]); + } build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, sb_subtype, subFs, wire_opposite_side, /* Pass tracks may not be wired to start tracks */ From 40d40506e451becf6c7af5b8f0a75c39990ccc08 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 18 Sep 2022 10:04:44 -0700 Subject: [PATCH 086/453] [vpr] comment out debug logging --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 6e5d9407411..d990f201c2c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -374,7 +374,7 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, /* to_track should be OUT_PORT */ VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index)); - VTR_LOG("Consider a connection from pass tracks %d on side %s to track node %ld on side %s\n", from_track_index, SIDE_STRING[from_side], size_t(to_track_node), SIDE_STRING[to_side]); + //VTR_LOG("Consider a connection from pass tracks %d on side %s to track node %ld on side %s\n", from_track_index, SIDE_STRING[from_side], size_t(to_track_node), SIDE_STRING[to_side]); /* Check if the to_track_node is already in the list ! */ std::vector::iterator it = std::find(track2track_map[from_side_index][from_track_index].begin(), @@ -385,7 +385,7 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, } /* Clear, we should add to the list */ track2track_map[from_side_index][from_track_index].push_back(to_track_node); - VTR_LOG("Built a connection from pass tracks %d on side %s to track node %ld on side %s\n", from_track_index, SIDE_STRING[from_side], size_t(to_track_node), SIDE_STRING[to_side]); + //VTR_LOG("Built a connection from pass tracks %d on side %s to track node %ld on side %s\n", from_track_index, SIDE_STRING[from_side], size_t(to_track_node), SIDE_STRING[to_side]); } } } @@ -522,9 +522,9 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks, * TODO: This can be improved with different patterns! */ - for (e_side curr_side : SIDES) { - VTR_LOG("Number of pass tracks %d on side %s\n", pass_tracks[size_t(curr_side)].size(), SIDE_STRING[curr_side]); - } + //for (e_side curr_side : SIDES) { + // VTR_LOG("Number of pass tracks %d on side %s\n", pass_tracks[size_t(curr_side)].size(), SIDE_STRING[curr_side]); + //} build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, sb_subtype, subFs, wire_opposite_side, /* Pass tracks may not be wired to start tracks */ From 2c3197ece7cdc95c74ceb02637f02aab66faa015 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 18 Sep 2022 10:58:08 -0700 Subject: [PATCH 087/453] [vpr] fixed a bug where subtype is not passed correctly --- vpr/src/base/SetupVPR.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 7f6bd0c7dfc..2a2ac25779d 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -350,7 +350,7 @@ static void SetupSwitches(const t_arch& Arch, static void SetupRoutingArch(const t_arch& Arch, t_det_routing_arch* RoutingArch) { RoutingArch->switch_block_type = Arch.SBType; - RoutingArch->switch_block_type = Arch.SBSubType; + RoutingArch->switch_block_subtype = Arch.SBSubType; RoutingArch->R_minW_nmos = Arch.R_minW_nmos; RoutingArch->R_minW_pmos = Arch.R_minW_pmos; RoutingArch->Fs = Arch.Fs; From 1374493be37a907cc5040c179b1c77f98330bd08 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 18 Sep 2022 21:45:15 -0700 Subject: [PATCH 088/453] [lib] fixed a bug where free_rr_graph is not thorough --- libs/librrgraph/src/base/rr_graph_builder.cpp | 2 ++ vpr/src/route/rr_graph.cpp | 2 ++ 2 files changed, 4 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 7ddf6f96e67..ebfc6e4341c 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -103,7 +103,9 @@ void RRGraphBuilder::clear() { node_ptc_nums_.clear(); rr_node_metadata_.clear(); rr_edge_metadata_.clear(); + segment_ids_.clear(); rr_segments_.clear(); + switch_ids_.clear(); rr_switch_inf_.clear(); edges_to_build_.clear(); is_edge_dirty_ = true; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 9a3538f135a..a043e2ab77d 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1674,6 +1674,8 @@ void free_rr_graph() { device_ctx.rr_graph_builder.clear(); + device_ctx.rr_node_track_ids.clear(); + device_ctx.rr_indexed_data.clear(); device_ctx.switch_fanin_remap.clear(); From 907ff5851676d42c464d128de48056be9f1df06e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 18 Sep 2022 21:56:39 -0700 Subject: [PATCH 089/453] [vpr] fixed a bug where tileable rr_graph is not considered during binary search and place --- vpr/src/base/place_and_route.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index c0956ba822a..8a3c1c13059 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -93,6 +93,10 @@ int binary_search_place_and_route(const t_placer_opts& placer_opts_ref, graph_directionality = GRAPH_BIDIR; } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); } From 5ea56610fe823a8e7e72c70371f3ce2ceb825a6a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 18 Sep 2022 22:13:39 -0700 Subject: [PATCH 090/453] [vpr] fixed a bug on using tileable rr_graph for binary place and route --- vpr/src/route/route_common.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 03d92e17cde..e8e4f05c1c7 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -266,6 +266,10 @@ bool try_route(int width_fac, graph_directionality = GRAPH_BIDIR; } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); } From bd63ae21528a9d92cce74c2d5c5cd15a0544663b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 09:54:17 -0700 Subject: [PATCH 091/453] [vpr] now skip sorting edges for tileable rr_graph builder --- libs/librrgraph/src/base/rr_graph_builder.cpp | 2 +- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 4 ++-- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index ebfc6e4341c..a5b0c3cd13b 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -189,8 +189,8 @@ void RRGraphBuilder::create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_sw } void RRGraphBuilder::build_edges(const bool& uniquify) { - std::sort(edges_to_build_.begin(), edges_to_build_.end()); if (uniquify) { + std::sort(edges_to_build_.begin(), edges_to_build_.end()); edges_to_build_.erase(std::unique(edges_to_build_.begin(), edges_to_build_.end()), edges_to_build_.end()); } alloc_and_load_edges(&edges_to_build_); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index f12fbcc59a1..cc4d5c6185d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -46,7 +46,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, edge_count++; } /* Allocate edges for all the source nodes */ - rr_graph_builder.build_edges(); + rr_graph_builder.build_edges(false); VTR_LOG("Number of edges to create for source nodes: %ld\n", edge_count); num_edges_to_create += edge_count; } @@ -82,7 +82,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, edge_count++; } /* Allocate edges for all the source nodes */ - rr_graph_builder.build_edges(); + rr_graph_builder.build_edges(false); VTR_LOG("Number of edges to create for sink nodes: %ld\n", edge_count); num_edges_to_create += edge_count; } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index d990f201c2c..ae6b8e0892e 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1442,5 +1442,5 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, } } /* Build actual edges */ - rr_graph_builder.build_edges(); + rr_graph_builder.build_edges(false); } From 69476ee33fdb19b52f9f5b8d3837fe7a3a6b5471 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 10:19:43 -0700 Subject: [PATCH 092/453] [vpr] now sort all the edges when building a tileable rr_graph --- .../tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 6 +++--- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index cc4d5c6185d..a30fc51fe35 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -46,7 +46,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, edge_count++; } /* Allocate edges for all the source nodes */ - rr_graph_builder.build_edges(false); + rr_graph_builder.build_edges(true); VTR_LOG("Number of edges to create for source nodes: %ld\n", edge_count); num_edges_to_create += edge_count; } @@ -82,7 +82,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, edge_count++; } /* Allocate edges for all the source nodes */ - rr_graph_builder.build_edges(false); + rr_graph_builder.build_edges(true); VTR_LOG("Number of edges to create for sink nodes: %ld\n", edge_count); num_edges_to_create += edge_count; } @@ -147,7 +147,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, track2ipin_map, opin2track_map, sb_conn, rr_node_driver_switches, num_edges_to_create); /* Finish this GSB, go to the next*/ - rr_graph_builder.build_edges(false); + rr_graph_builder.build_edges(true); } } VTR_LOG("Number of edges to create: %ld\n", num_edges_to_create); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index ae6b8e0892e..d33e1a0f84d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1442,5 +1442,5 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, } } /* Build actual edges */ - rr_graph_builder.build_edges(false); + rr_graph_builder.build_edges(true); } From b2df63231b62e41710e0b7846db26a8687270066 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 10:58:48 -0700 Subject: [PATCH 093/453] [vpr] sort gsb ipin edges as well --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 114 +++++++++++++++++++++++++++ vpr/src/tileable_rr_graph/rr_gsb.h | 7 ++ 2 files changed, 121 insertions(+) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index c21f093983f..ceb92c9fc70 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -22,6 +22,7 @@ RRGSB::RRGSB() { chan_node_.clear(); chan_node_direction_.clear(); chan_node_in_edges_.clear(); + ipin_node_in_edges_.clear(); ipin_node_.clear(); @@ -172,6 +173,34 @@ std::vector RRGSB::get_chan_node_in_edges(const RRGraphView& rr_graph, return chan_node_in_edges_[side_manager.to_size_t()][track_id]; } +std::vector RRGSB::get_ipin_node_in_edges(const RRGraphView& rr_graph, + const e_side& side, + const size_t& ipin_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_ipin_node_id(side, ipin_id)); + + /* if sorted, we give sorted edges + * if not sorted, we give the empty vector + */ + if (0 == ipin_node_in_edges_.size()) { + std::vector unsorted_edges; + + for (const RREdgeId& edge : rr_graph.node_in_edges(get_ipin_node(side, ipin_id))) { + unsorted_edges.push_back(edge); + } + + return unsorted_edges; + } + + return ipin_node_in_edges_[side_manager.to_size_t()][ipin_id]; +} + /* get the segment id of a channel rr_node */ RRSegmentId RRGSB::get_chan_node_segment(const e_side& side, const size_t& track_id) const { SideManager side_manager(side); @@ -787,6 +816,91 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph) { } } +void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, + const e_side& ipin_side, + const size_t& ipin_id) { + std::map> from_track_edge_map; + + const RRNodeId& ipin_node = ipin_node_[size_t(ipin_side)][ipin_id]; + + /* Count the edges and ensure every of them has been sorted */ + size_t edge_counter = 0; + + /* For each incoming edge, find the node side and index in this GSB. + * and cache these. Then we will use the data to sort the edge in the + * following sequence: + * 0----------------------------------------------------------------> num_in_edges() + * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| + * For each side, the edge will be sorted by the node index starting from 0 + * For each side, the edge from grid pins will be the 1st part + * while the edge from routing tracks will be the 2nd part + */ + for (const RREdgeId& edge : rr_graph.node_in_edges(ipin_node)) { + /* We care the source node of this edge, and it should be an input of the GSB!!! */ + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + e_side side = NUM_SIDES; + int index = 0; + get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index); + + /* Must have valid side and index */ + if (NUM_SIDES == side) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(src_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(src_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + VTR_LOG("\n----------------------------------\n"); + VTR_LOG("Channel node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(chan_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(chan_node)); + VTR_LOG("Fan-in nodes:\n"); + for (const auto& temp_edge : rr_graph.node_in_edges(ipin_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(temp_edge)).c_str()); + } + } + + VTR_ASSERT(NUM_SIDES != side); + VTR_ASSERT(OPEN != index); + + VTR_ASSERT((CHANX == rr_graph.node_type(src_node)) + || (CHANY == rr_graph.node_type(src_node))); + from_track_edge_map[side][index] = edge; + edge_counter++; + } + + /* Store the sorted edge */ + for (size_t side = 0; side < get_num_sides(); ++side) { + for (size_t iipin = 0; iipin < ipin_node_[side].size(); ++iipin) { + if ((0 < from_track_edge_map.count(side)) + && (0 < from_track_edge_map.at(side).count(ipin_id))) { + ipin_node_in_edges_[size_t(ipin_side)][ipin_id].push_back(from_track_edge_map[side][iipin]); + } + } + } + + VTR_ASSERT(edge_counter == ipin_node_in_edges_[size_t(ipin_side)][ipin_id].size()); +} + + + +void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { + /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ + ipin_node_in_edges_.resize(get_num_sides()); + + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + ipin_node_in_edges_[side].resize(ipin_node_[side].get_chan_width()); + for (size_t ipin_id = 0; ipin_id < ipin_node_[side].size(); ++ipin_id) { + sort_ipin_node_in_edges(rr_graph, side_manager.get_side(), ipin_id); + } + } +} + + /************************************************************************ * Public Mutators: clean-up functions ***********************************************************************/ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 854bc37eae1..9c455301763 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -91,6 +91,11 @@ class RRGSB { const e_side& side, const size_t& track_id) const; + /* get all the sorted incoming edges for a IPIN rr_node at a given side and ipin_id */ + std::vector get_ipin_node_in_edges(const RRGraphView& rr_graph, + const e_side& side, + const size_t& ipin_id) const; + /* get the segment id of a channel rr_node */ RRSegmentId get_chan_node_segment(const e_side& side, const size_t& track_id) const; @@ -235,6 +240,8 @@ class RRGSB { * [chan_side][chan_node][edge_id_in_gsb_context] */ std::vector>> chan_node_in_edges_; + /* Sequence of edge ids for each input pin node. Same rules applied as the channel nodes */ + std::vector>> ipin_node_in_edges_; /* Logic Block Inputs data */ std::vector> ipin_node_; From 825d44437e94f49e34d0f1cecd5c124b4c504259 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 12:14:04 -0700 Subject: [PATCH 094/453] [vpr] syntax --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 6 +++--- vpr/src/tileable_rr_graph/rr_gsb.h | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index ceb92c9fc70..a0d35329b53 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -855,8 +855,8 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, } VTR_LOG("\n----------------------------------\n"); VTR_LOG("Channel node:\n"); - VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(chan_node).c_str()); - VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(chan_node)); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(ipin_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(ipin_node)); VTR_LOG("Fan-in nodes:\n"); for (const auto& temp_edge : rr_graph.node_in_edges(ipin_node)) { VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(temp_edge)).c_str()); @@ -893,7 +893,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { for (size_t side = 0; side < get_num_sides(); ++side) { SideManager side_manager(side); - ipin_node_in_edges_[side].resize(ipin_node_[side].get_chan_width()); + ipin_node_in_edges_[side].resize(ipin_node_[side].size()); for (size_t ipin_id = 0; ipin_id < ipin_node_[side].size(); ++ipin_id) { sort_ipin_node_in_edges(rr_graph, side_manager.get_side(), ipin_id); } diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 9c455301763..6d2c718b8cb 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -182,6 +182,8 @@ class RRGSB { /* Sort all the incoming edges for routing channel rr_node */ void sort_chan_node_in_edges(const RRGraphView& rr_graph); + /* Sort all the incoming edges for input pin rr_node */ + void sort_ipin_node_in_edges(const RRGraphView& rr_graph); public: /* Mutators: cleaners */ void clear(); @@ -204,6 +206,11 @@ class RRGSB { const e_side& chan_side, const size_t& track_id); + /* Sort all the incoming edges for one input pin rr_node */ + void sort_ipin_node_in_edges(const RRGraphView& rr_graph, + const e_side& chan_side, + const size_t& ipin_id); + private: /* internal functions */ size_t get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const; From a8349b6f8086021c327a00d5c31cc06444eac2c7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 13:21:22 -0700 Subject: [PATCH 095/453] [vtr] fixed a bug when sorting in_edges for IPINs. --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index a0d35329b53..267282060b3 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -838,9 +838,14 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, for (const RREdgeId& edge : rr_graph.node_in_edges(ipin_node)) { /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); + /* The driver routing channel node can be either an input or an output to the GSB. + * Just try to find a qualified one. */ e_side side = NUM_SIDES; int index = 0; get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index); + if (NUM_SIDES == side || OPEN == index) { + get_node_side_and_index(rr_graph, src_node, OUT_PORT, side, index); + } /* Must have valid side and index */ if (NUM_SIDES == side) { @@ -854,7 +859,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); } VTR_LOG("\n----------------------------------\n"); - VTR_LOG("Channel node:\n"); + VTR_LOG("IPIN node:\n"); VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(ipin_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(ipin_node)); VTR_LOG("Fan-in nodes:\n"); From bb895cb73226336caff2eb49017ead3a3dc27f99 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 13:30:54 -0700 Subject: [PATCH 096/453] [vpr] debugging --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 267282060b3..e0d900f3dd8 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -879,10 +879,10 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, /* Store the sorted edge */ for (size_t side = 0; side < get_num_sides(); ++side) { - for (size_t iipin = 0; iipin < ipin_node_[side].size(); ++iipin) { + for (size_t itrack = 0; itrack < chan_node_[side].get_chan_width(); ++itrack) { if ((0 < from_track_edge_map.count(side)) - && (0 < from_track_edge_map.at(side).count(ipin_id))) { - ipin_node_in_edges_[size_t(ipin_side)][ipin_id].push_back(from_track_edge_map[side][iipin]); + && (0 < from_track_edge_map.at(side).count(itrack))) { + ipin_node_in_edges_[size_t(ipin_side)][ipin_id].push_back(from_track_edge_map[side][itrack]); } } } From 657624796fbdab8c69d14f788bd501a31ef35784 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 14:51:55 -0700 Subject: [PATCH 097/453] [vtr] fixed a bug on sorting incoming edges for IPIN nodes: Only consider a limited sides because channel nodes could be duplicated on multiple sides --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 33 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index e0d900f3dd8..5fae25de8ad 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -819,7 +819,9 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph) { void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const e_side& ipin_side, const size_t& ipin_id) { - std::map> from_track_edge_map; + std::map from_track_edge_map; + + e_side chan_side = get_cb_chan_side(ipin_side); const RRNodeId& ipin_node = ipin_node_[size_t(ipin_side)][ipin_id]; @@ -848,7 +850,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, } /* Must have valid side and index */ - if (NUM_SIDES == side) { + if (NUM_SIDES == side || side != chan_side) { VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG("----------------------------------\n"); VTR_LOG("SRC node:\n"); @@ -868,39 +870,36 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, } } - VTR_ASSERT(NUM_SIDES != side); + VTR_ASSERT(NUM_SIDES != side && side == chan_side); VTR_ASSERT(OPEN != index); VTR_ASSERT((CHANX == rr_graph.node_type(src_node)) || (CHANY == rr_graph.node_type(src_node))); - from_track_edge_map[side][index] = edge; + from_track_edge_map[index] = edge; edge_counter++; } /* Store the sorted edge */ - for (size_t side = 0; side < get_num_sides(); ++side) { - for (size_t itrack = 0; itrack < chan_node_[side].get_chan_width(); ++itrack) { - if ((0 < from_track_edge_map.count(side)) - && (0 < from_track_edge_map.at(side).count(itrack))) { - ipin_node_in_edges_[size_t(ipin_side)][ipin_id].push_back(from_track_edge_map[side][itrack]); - } + for (size_t itrack = 0; itrack < chan_node_[size_t(chan_side)].get_chan_width(); ++itrack) { + if (0 < from_track_edge_map.count(itrack)) { + ipin_node_in_edges_[size_t(ipin_side)][ipin_id].push_back(from_track_edge_map[itrack]); } } VTR_ASSERT(edge_counter == ipin_node_in_edges_[size_t(ipin_side)][ipin_id].size()); } - - void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ ipin_node_in_edges_.resize(get_num_sides()); - for (size_t side = 0; side < get_num_sides(); ++side) { - SideManager side_manager(side); - ipin_node_in_edges_[side].resize(ipin_node_[side].size()); - for (size_t ipin_id = 0; ipin_id < ipin_node_[side].size(); ++ipin_id) { - sort_ipin_node_in_edges(rr_graph, side_manager.get_side(), ipin_id); + for (t_rr_type cb_type : {CHANX, CHANY}) { + for (e_side ipin_side : get_cb_ipin_sides(cb_type)) { + SideManager side_manager(ipin_side); + ipin_node_in_edges_[size_t(ipin_side)].resize(ipin_node_[size_t(ipin_side)].size()); + for (size_t ipin_id = 0; ipin_id < ipin_node_[size_t(ipin_side)].size(); ++ipin_id) { + sort_ipin_node_in_edges(rr_graph, side_manager.get_side(), ipin_id); + } } } } From 332bc9085753b387773cfc37c31689705fa554f4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 15:05:28 -0700 Subject: [PATCH 098/453] [vpr] fixed a bug --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 5fae25de8ad..78de9164771 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -842,15 +842,14 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* The driver routing channel node can be either an input or an output to the GSB. * Just try to find a qualified one. */ - e_side side = NUM_SIDES; int index = 0; - get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index); - if (NUM_SIDES == side || OPEN == index) { - get_node_side_and_index(rr_graph, src_node, OUT_PORT, side, index); + get_node_index(rr_graph, src_node, chan_side, IN_PORT); + if (OPEN == index) { + get_node_index(rr_graph, src_node, chan_side, OUT_PORT); } /* Must have valid side and index */ - if (NUM_SIDES == side || side != chan_side) { + if (OPEN == index) { VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG("----------------------------------\n"); VTR_LOG("SRC node:\n"); @@ -870,7 +869,6 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, } } - VTR_ASSERT(NUM_SIDES != side && side == chan_side); VTR_ASSERT(OPEN != index); VTR_ASSERT((CHANX == rr_graph.node_type(src_node)) From 2f1bfd32080e81c63b0ea3116fbafff2f085202e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Sep 2022 15:35:06 -0700 Subject: [PATCH 099/453] [vtr] fixed a bug --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 78de9164771..78b1e51c60e 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -842,10 +842,10 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* The driver routing channel node can be either an input or an output to the GSB. * Just try to find a qualified one. */ - int index = 0; - get_node_index(rr_graph, src_node, chan_side, IN_PORT); + int index = OPEN; + index = get_node_index(rr_graph, src_node, chan_side, IN_PORT); if (OPEN == index) { - get_node_index(rr_graph, src_node, chan_side, OUT_PORT); + index = get_node_index(rr_graph, src_node, chan_side, OUT_PORT); } /* Must have valid side and index */ From d3a80393684234a4b53279cf383bace369cc854f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 26 Sep 2022 14:01:44 -0700 Subject: [PATCH 100/453] [lib] replace the use of SIGSTKSZ which is not supported in Ubuntu 21.04+ --- .../src/catch2/internal/catch_fatal_condition_handler.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/EXTERNAL/libcatch2/src/catch2/internal/catch_fatal_condition_handler.cpp b/libs/EXTERNAL/libcatch2/src/catch2/internal/catch_fatal_condition_handler.cpp index 9383257cecb..4f35b27b7a5 100644 --- a/libs/EXTERNAL/libcatch2/src/catch2/internal/catch_fatal_condition_handler.cpp +++ b/libs/EXTERNAL/libcatch2/src/catch2/internal/catch_fatal_condition_handler.cpp @@ -202,7 +202,7 @@ namespace Catch { FatalConditionHandler::FatalConditionHandler() { assert(!altStackMem && "Cannot initialize POSIX signal handler when one already exists"); if (altStackSize == 0) { - altStackSize = std::max(static_cast(SIGSTKSZ), minStackSizeForErrors); + altStackSize = std::max(static_cast(/*SIGSTKSZ*/32768), minStackSizeForErrors); } altStackMem = new char[altStackSize](); } From 1a8c8757c32bc2cac93609a6bb9d8bc0cb3248b7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 30 Sep 2022 15:21:38 -0700 Subject: [PATCH 101/453] [vpr] fixed a bug in finding direct connection in tileable rr_graph; Remove verbose outputs --- .../openfpga_rr_graph_utils.cpp | 2 +- .../tileable_rr_graph_edge_builder.cpp | 1 - .../tileable_rr_graph_gsb.cpp | 23 +++++++++---------- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index da17b51b2fc..ea3b52a5440 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -149,7 +149,7 @@ bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, VTR_ASSERT(1 == rr_graph.node_out_edges(node).size()); for (auto edge : rr_graph.node_out_edges(node)) { - const RRNodeId& sink_node = rr_graph.edge_sink_node(RREdgeId(edge)); + const RRNodeId& sink_node = rr_graph.edge_sink_node(node, edge); if (IPIN != rr_graph.node_type(sink_node)) { return false; } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index a30fc51fe35..5d6345ba8ab 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -150,7 +150,6 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, rr_graph_builder.build_edges(true); } } - VTR_LOG("Number of edges to create: %ld\n", num_edges_to_create); } /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index d33e1a0f84d..8a17720dd7b 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -968,7 +968,6 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, } } } - VTR_LOG("Number of edges to create for gsb[%ld][%ld]: %ld\n", rr_gsb.get_x(), rr_gsb.get_y(), edge_count); num_edges_to_create += edge_count; } @@ -1420,23 +1419,23 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, std::vector ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin); VTR_ASSERT(1 == ipin_grid_side.size()); - const RRNodeId& opin_node_id = rr_graph.node_lookup().find_node(from_grid_coordinate.x() - from_grid_width_ofs, + RRNodeId opin_node_id = rr_graph.node_lookup().find_node(from_grid_coordinate.x() - from_grid_width_ofs, from_grid_coordinate.y() - from_grid_height_ofs, OPIN, opin, opin_grid_side[0]); - const RRNodeId& ipin_node_id = rr_graph.node_lookup().find_node(to_grid_coordinate.x() - to_grid_width_ofs, + RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(to_grid_coordinate.x() - to_grid_width_ofs, to_grid_coordinate.y() - to_grid_height_ofs, IPIN, ipin, ipin_grid_side[0]); - /* - * VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", - * from_grid_coordinate.x() - from_grid_width_ofs, - * from_grid_coordinate.y() - from_grid_height_ofs, - * opin, SIDE_STRING[opin_grid_side[0]], - * to_grid_coordinate.x() - to_grid_width_ofs, - * to_grid_coordinate.y() - to_grid_height_ofs, - * ipin, SIDE_STRING[ipin_grid_side[0]]); - */ + + VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", + from_grid_coordinate.x() - from_grid_width_ofs, + from_grid_coordinate.y() - from_grid_height_ofs, + opin, SIDE_STRING[opin_grid_side[0]], + to_grid_coordinate.x() - to_grid_width_ofs, + to_grid_coordinate.y() - to_grid_height_ofs, + ipin, SIDE_STRING[ipin_grid_side[0]]); /* add edges to the opin_node */ + VTR_ASSERT(opin_node_id && ipin_node_id); rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch); } } From 970afa5b96231272b305bbc3112ee9af662477ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 30 Sep 2022 15:26:37 -0700 Subject: [PATCH 102/453] [vpr] remove verbose outputs --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 2 -- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 3 ++- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 5d6345ba8ab..b009874badf 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -47,7 +47,6 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, } /* Allocate edges for all the source nodes */ rr_graph_builder.build_edges(true); - VTR_LOG("Number of edges to create for source nodes: %ld\n", edge_count); num_edges_to_create += edge_count; } @@ -83,7 +82,6 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, } /* Allocate edges for all the source nodes */ rr_graph_builder.build_edges(true); - VTR_LOG("Number of edges to create for sink nodes: %ld\n", edge_count); num_edges_to_create += edge_count; } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 8a17720dd7b..b91d6426e2c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1425,7 +1425,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(to_grid_coordinate.x() - to_grid_width_ofs, to_grid_coordinate.y() - to_grid_height_ofs, IPIN, ipin, ipin_grid_side[0]); - + /* VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", from_grid_coordinate.x() - from_grid_width_ofs, from_grid_coordinate.y() - from_grid_height_ofs, @@ -1433,6 +1433,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, to_grid_coordinate.x() - to_grid_width_ofs, to_grid_coordinate.y() - to_grid_height_ofs, ipin, SIDE_STRING[ipin_grid_side[0]]); + */ /* add edges to the opin_node */ VTR_ASSERT(opin_node_id && ipin_node_id); From c33574d8db85efbc664798034992d43a7e49de77 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 3 Oct 2022 11:08:31 -0700 Subject: [PATCH 103/453] [CMake] Added an option 'VTR_ENABLE_VERSION_UP_TO_DATE' which allows users to skip version build (by default is always on). This can reduce build time when use VTR as a submodule --- CMakeLists.txt | 1 + libs/libvtrutil/CMakeLists.txt | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6dc4c952d47..7fb08dac96e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -31,6 +31,7 @@ option(VTR_ENABLE_SANITIZE "Enable address/leak/undefined-behaviour sanitizers ( option(VTR_ENABLE_PROFILING "Enable performance profiler (gprof)" OFF) option(VTR_ENABLE_COVERAGE "Enable code coverage tracking (gcov)" OFF) option(VTR_ENABLE_DEBUG_LOGGING "Enable debug logging" OFF) +option(VTR_ENABLE_VERSION_UP_TO_DATE "Enable version number up-to-date during compilation" ON) #Allow the user to decide whether to compile the graphics library set(VPR_USE_EZGL "auto" CACHE STRING "Specify whether vpr uses the graphics library") diff --git a/libs/libvtrutil/CMakeLists.txt b/libs/libvtrutil/CMakeLists.txt index 6e69ae53085..08bac8b8d64 100644 --- a/libs/libvtrutil/CMakeLists.txt +++ b/libs/libvtrutil/CMakeLists.txt @@ -98,7 +98,9 @@ target_include_directories(libvtrutil PUBLIC ${LIB_INCLUDE_DIRS}) set_target_properties(libvtrutil PROPERTIES PREFIX "") #Avoid extra 'lib' prefix #Ensure version is always up to date by requiring version to be run first -add_dependencies(libvtrutil version) +if (VTR_ENABLE_VERSION_UP_TO_DATE) + add_dependencies(libvtrutil version) +endif() #Specify link-time dependancies target_link_libraries(libvtrutil From 147200b1edce48a22705f470c9fa937cb56e1b10 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 3 Oct 2022 11:18:06 -0700 Subject: [PATCH 104/453] [cmake] bypass custom build on version number with an option --- libs/libvtrutil/CMakeLists.txt | 37 +++++++++++++++++----------------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/libs/libvtrutil/CMakeLists.txt b/libs/libvtrutil/CMakeLists.txt index 08bac8b8d64..ba4df59e77d 100644 --- a/libs/libvtrutil/CMakeLists.txt +++ b/libs/libvtrutil/CMakeLists.txt @@ -61,24 +61,25 @@ endif() # 2) The custom command depends on the touched version input file and generates the processed # version file, with updated values. The custom command uses the configure_version.cmake # script to generate the up-to-date vtr_version.cpp -add_custom_target(version ALL - COMMAND ${CMAKE_COMMAND} -E touch ${VTR_VERSION_FILE_IN}) - -add_custom_command(OUTPUT ${VTR_VERSION_FILE_OUT} - COMMAND ${CMAKE_COMMAND} - -D IN_FILE=${VTR_VERSION_FILE_IN} - -D OUT_FILE=${VTR_VERSION_FILE_OUT} - -D VTR_VERSION_MAJOR=${VTR_VERSION_MAJOR} - -D VTR_VERSION_MINOR=${VTR_VERSION_MINOR} - -D VTR_VERSION_PATCH=${VTR_VERSION_PATCH} - -D VTR_VERSION_PRERELEASE=${VTR_VERSION_PRERELEASE} - -D VTR_COMPILER_INFO=${VTR_COMPILER_INFO} - -D VTR_BUILD_INFO=${VTR_BUILD_INFO} - -P ${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules/configure_version.cmake - MAIN_DEPENDENCY ${VTR_VERSION_FILE_IN} - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - VERBATIM) - +if (VTR_ENABLE_VERSION_UP_TO_DATE) + add_custom_target(version ALL + COMMAND ${CMAKE_COMMAND} -E touch ${VTR_VERSION_FILE_IN}) + + add_custom_command(OUTPUT ${VTR_VERSION_FILE_OUT} + COMMAND ${CMAKE_COMMAND} + -D IN_FILE=${VTR_VERSION_FILE_IN} + -D OUT_FILE=${VTR_VERSION_FILE_OUT} + -D VTR_VERSION_MAJOR=${VTR_VERSION_MAJOR} + -D VTR_VERSION_MINOR=${VTR_VERSION_MINOR} + -D VTR_VERSION_PATCH=${VTR_VERSION_PATCH} + -D VTR_VERSION_PRERELEASE=${VTR_VERSION_PRERELEASE} + -D VTR_COMPILER_INFO=${VTR_COMPILER_INFO} + -D VTR_BUILD_INFO=${VTR_BUILD_INFO} + -P ${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules/configure_version.cmake + MAIN_DEPENDENCY ${VTR_VERSION_FILE_IN} + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + VERBATIM) +endif() # # Source files and library From 942d1bbfff837d9c5409f6f0932dec574fb7e7c2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 3 Oct 2022 11:36:29 -0700 Subject: [PATCH 105/453] [cmake] rename option to be short 'VTR_ENABLE_VERSION' --- CMakeLists.txt | 2 +- libs/libvtrutil/CMakeLists.txt | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7fb08dac96e..c050a83931a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -31,7 +31,7 @@ option(VTR_ENABLE_SANITIZE "Enable address/leak/undefined-behaviour sanitizers ( option(VTR_ENABLE_PROFILING "Enable performance profiler (gprof)" OFF) option(VTR_ENABLE_COVERAGE "Enable code coverage tracking (gcov)" OFF) option(VTR_ENABLE_DEBUG_LOGGING "Enable debug logging" OFF) -option(VTR_ENABLE_VERSION_UP_TO_DATE "Enable version number up-to-date during compilation" ON) +option(VTR_ENABLE_VERSION "Enable version number up-to-date during compilation" ON) #Allow the user to decide whether to compile the graphics library set(VPR_USE_EZGL "auto" CACHE STRING "Specify whether vpr uses the graphics library") diff --git a/libs/libvtrutil/CMakeLists.txt b/libs/libvtrutil/CMakeLists.txt index ba4df59e77d..a624c1b1a8c 100644 --- a/libs/libvtrutil/CMakeLists.txt +++ b/libs/libvtrutil/CMakeLists.txt @@ -61,7 +61,7 @@ endif() # 2) The custom command depends on the touched version input file and generates the processed # version file, with updated values. The custom command uses the configure_version.cmake # script to generate the up-to-date vtr_version.cpp -if (VTR_ENABLE_VERSION_UP_TO_DATE) +if (VTR_ENABLE_VERSION) add_custom_target(version ALL COMMAND ${CMAKE_COMMAND} -E touch ${VTR_VERSION_FILE_IN}) @@ -79,6 +79,9 @@ if (VTR_ENABLE_VERSION_UP_TO_DATE) MAIN_DEPENDENCY ${VTR_VERSION_FILE_IN} WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} VERBATIM) +else() +# Just copy the input file to output file with version number + configure_file(${VTR_VERSION_FILE_IN} ${VTR_VERSION_FILE_OUT}) endif() # @@ -99,7 +102,7 @@ target_include_directories(libvtrutil PUBLIC ${LIB_INCLUDE_DIRS}) set_target_properties(libvtrutil PROPERTIES PREFIX "") #Avoid extra 'lib' prefix #Ensure version is always up to date by requiring version to be run first -if (VTR_ENABLE_VERSION_UP_TO_DATE) +if (VTR_ENABLE_VERSION) add_dependencies(libvtrutil version) endif() From 69773dbfbbcf682084be44cca2251d0f3e2e41ff Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 3 Oct 2022 21:01:49 -0700 Subject: [PATCH 106/453] [vpr] enable tileable rr_graph when building routing structs --- vpr/src/route/route_common.cpp | 4 ++++ vpr/src/route/router_delay_profiling.cpp | 3 +++ 2 files changed, 7 insertions(+) diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index e8e4f05c1c7..ee94f96d681 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -213,6 +213,10 @@ void try_graph(int width_fac, const t_router_opts& router_opts, t_det_routing_ar graph_directionality = GRAPH_BIDIR; } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); } diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index 50578ff1f9a..2e990a96455 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -221,6 +221,9 @@ void alloc_routing_structs(t_chan_width chan_width, graph_type = GRAPH_GLOBAL; } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + if ((UNI_DIRECTIONAL == det_routing_arch->directionality) && (true == det_routing_arch->tileable)) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } } create_rr_graph(graph_type, From c70f97b7db73563fe881ab35713cf933c155fcfc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 3 Oct 2022 21:15:50 -0700 Subject: [PATCH 107/453] [vpr] code format --- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- .../rr_graph_builder_utils.cpp | 4 ++-- vpr/src/tileable_rr_graph/rr_gsb.cpp | 6 ++--- vpr/src/tileable_rr_graph/rr_gsb.h | 2 +- .../tileable_rr_graph_gsb.cpp | 18 ++++----------- .../tileable_rr_graph_node_builder.cpp | 23 +++++++++---------- 6 files changed, 21 insertions(+), 34 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index edf257f0e3d..541cf23a121 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -3453,7 +3453,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, if (inst_lsb < 0 || inst_msb > PhysicalTileType->capacity - 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Pin location specification '%s' contain an out-of-range instance. Expect [%d:%d]", - token.c_str(), 0 , PhysicalTileType->capacity - 1); + token.c_str(), 0, PhysicalTileType->capacity - 1); } } diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index c2fb1a580d4..a97b37e2d88 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -282,8 +282,8 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, VTR_ASSERT(chanx_coord.x() < grids.width() - 1); if (grids.width() - 2 == chanx_coord.x()) { /* This is already the RIGHT side of FPGA fabric, - * it is the same results as chanx is right to a multi-height grid - */ + * it is the same results as chanx is right to a multi-height grid + */ return true; } diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 78b1e51c60e..901a9c0bef7 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -844,7 +844,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, * Just try to find a qualified one. */ int index = OPEN; index = get_node_index(rr_graph, src_node, chan_side, IN_PORT); - if (OPEN == index) { + if (OPEN == index) { index = get_node_index(rr_graph, src_node, chan_side, OUT_PORT); } @@ -871,8 +871,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, VTR_ASSERT(OPEN != index); - VTR_ASSERT((CHANX == rr_graph.node_type(src_node)) - || (CHANY == rr_graph.node_type(src_node))); + VTR_ASSERT(CHANX == rr_graph.node_type(src_node) || CHANY == rr_graph.node_type(src_node)); from_track_edge_map[index] = edge; edge_counter++; } @@ -902,7 +901,6 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { } } - /************************************************************************ * Public Mutators: clean-up functions ***********************************************************************/ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 6d2c718b8cb..77f7b192cd0 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -138,7 +138,7 @@ class RRGSB { * on being a mirror of the current one */ bool is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) const; - + public: /* Cooridinator conversion and output */ size_t get_x() const; /* get the x coordinate of this switch block */ size_t get_y() const; /* get the y coordinate of this switch block */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index b91d6426e2c..e039fbf7418 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -158,7 +158,6 @@ static bool is_gsb_in_track_sb_population(const RRGraphView& rr_graph, /* Get segment id */ RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); /* validate offset */ - if (!(offset < segment_inf[size_t(seg_id)].sb.size())) VTR_ASSERT(offset < segment_inf[size_t(seg_id)].sb.size()); /* Get the SB population */ @@ -1420,20 +1419,11 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, VTR_ASSERT(1 == ipin_grid_side.size()); RRNodeId opin_node_id = rr_graph.node_lookup().find_node(from_grid_coordinate.x() - from_grid_width_ofs, - from_grid_coordinate.y() - from_grid_height_ofs, - OPIN, opin, opin_grid_side[0]); + from_grid_coordinate.y() - from_grid_height_ofs, + OPIN, opin, opin_grid_side[0]); RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(to_grid_coordinate.x() - to_grid_width_ofs, - to_grid_coordinate.y() - to_grid_height_ofs, - IPIN, ipin, ipin_grid_side[0]); - /* - VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n", - from_grid_coordinate.x() - from_grid_width_ofs, - from_grid_coordinate.y() - from_grid_height_ofs, - opin, SIDE_STRING[opin_grid_side[0]], - to_grid_coordinate.x() - to_grid_width_ofs, - to_grid_coordinate.y() - to_grid_height_ofs, - ipin, SIDE_STRING[ipin_grid_side[0]]); - */ + to_grid_coordinate.y() - to_grid_height_ofs, + IPIN, ipin, ipin_grid_side[0]); /* add edges to the opin_node */ VTR_ASSERT(opin_node_id && ipin_node_id); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 7421574705b..e3b063a33ff 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -603,15 +603,15 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, } for (e_side side : wanted_sides) { - for (int width_offset = 0; width_offset < grids[ix][iy].type->width; ++width_offset) { - int x_tile = ix + width_offset; - for (int height_offset = 0; height_offset < grids[ix][iy].type->height; ++height_offset) { - int y_tile = iy + height_offset; - rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, OPIN, grids[ix][iy].type->num_pins, side); - rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, IPIN, grids[ix][iy].type->num_pins, side); - } - } - } + for (int width_offset = 0; width_offset < grids[ix][iy].type->width; ++width_offset) { + int x_tile = ix + width_offset; + for (int height_offset = 0; height_offset < grids[ix][iy].type->height; ++height_offset) { + int y_tile = iy + height_offset; + rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, OPIN, grids[ix][iy].type->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, IPIN, grids[ix][iy].type->num_pins, side); + } + } + } /* Configure source rr_nodes for this grid */ load_one_grid_source_nodes_basic_info(rr_graph_builder, @@ -1013,8 +1013,7 @@ static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, // this should call rr_graph_builder to do the job for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ - if ( (CHANX != rr_graph.node_type(node)) - && (CHANY != rr_graph.node_type(node)) ) { + if (CHANX != rr_graph.node_type(node) && CHANY != rr_graph.node_type(node)) { continue; } /* Reach here, we must have a node of CHANX or CHANY */ @@ -1022,7 +1021,7 @@ static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, continue; } std::reverse(rr_node_track_ids[node].begin(), - rr_node_track_ids[node].end() ); + rr_node_track_ids[node].end()); } } From 3264072d5d4b646efaef911095767d58b5647461 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 1 Nov 2022 15:44:44 -0700 Subject: [PATCH 108/453] [vpr] a more sophiscated version of read blif api --- vpr/src/base/read_blif.cpp | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/vpr/src/base/read_blif.cpp b/vpr/src/base/read_blif.cpp index 2425a18d239..33d953cf111 100644 --- a/vpr/src/base/read_blif.cpp +++ b/vpr/src/base/read_blif.cpp @@ -718,19 +718,16 @@ bool is_binary_param(const std::string& param) { return true; } -bool is_real_param(const std::string& param) { - const std::string chars = "012345678."; - +bool is_real_param(const std::string ¶m) { /* Must be non-empty */ if (param.empty()) { return false; } - /* The string mustn't contain any other chars that the expected ones */ - for (size_t i = 0; i < param.length(); ++i) { - if (chars.find(param[i]) == std::string::npos) { - return false; - } + /* The string must match the regular expression */ + static const std::regex real_number_expr("[+-]?([0-9]*\\.[0-9]+)|([0-9]+\\.[0-9]*)"); + if (!std::regex_match(param, real_number_expr)) { + return false; } /* This is a real number param */ From c1622751a7d24ef60ca3bf2b03d511682d669325 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 1 Nov 2022 15:58:24 -0700 Subject: [PATCH 109/453] [test] update golden for new test --- .../strong_tileable_rr_graph/config/golden_results.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt index 7abe3a1a1c3..8576e7f7dc7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time placement_technique reward uniform_percentage median_percentage wmedian_percentage wcent_percentage fr_percentage critUni_percentage centroid_percentage - k4_N4_90nm.xml diffeq.blif common 6.72 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-3198-gd038c933b release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-01-02T13:20:16 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 87228 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.40 10030 0.93 0.01 6.59694 -1414.7 -6.59694 6.59694 0.45 0.00189405 0.00143772 0.221979 0.167805 24 12059 26 983127 929624 797780. 1508.09 2.59 0.588243 0.472549 11020 20 7062 23191 1573824 393127 6.8984 6.8984 -1529.52 -6.8984 0 0 1.04508e+06 1975.57 0.13 0.43 0.131471 0.112481 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k4_N4_90nm.xml ex5p.blif common 16.92 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-3198-gd038c933b release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-01-02T13:20:16 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 68688 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.17 11681 0.71 0.01 6.75152 -301.537 -6.75152 nan 0.34 0.00117768 0.000911645 0.136814 0.106107 34 15896 33 804782 771343 910617. 2064.89 13.76 0.477973 0.383445 13620 21 8417 29539 3341244 830781 6.81396 nan -313.113 -6.81396 0 0 1.15594e+06 2621.17 0.13 0.55 0.0731153 0.0639044 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k4_N4_90nm.xml s298.blif common 11.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-3198-gd038c933b release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-01-02T13:20:16 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 78820 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.31 14228 1.11 0.01 11.6554 -90.3611 -11.6554 11.6554 0.56 0.00215172 0.00157042 0.245315 0.182305 26 18055 30 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 6.01 0.62371 0.489649 16623 19 8342 42276 3817766 734253 11.5305 11.5305 -91.3072 -11.5305 0 0 1.43821e+06 2127.53 0.31 0.73 0.120758 0.1047 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 +k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 +k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 From 921e1ba453919f8f1987625fe53c61e79973e646 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 1 Nov 2022 16:21:21 -0700 Subject: [PATCH 110/453] [vpr] code format --- vpr/src/base/read_blif.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/read_blif.cpp b/vpr/src/base/read_blif.cpp index 33d953cf111..326216896f4 100644 --- a/vpr/src/base/read_blif.cpp +++ b/vpr/src/base/read_blif.cpp @@ -718,7 +718,7 @@ bool is_binary_param(const std::string& param) { return true; } -bool is_real_param(const std::string ¶m) { +bool is_real_param(const std::string& param) { /* Must be non-empty */ if (param.empty()) { return false; From 96ea971d7c92445f2b2f51c35ac2a5cdb7f3d374 Mon Sep 17 00:00:00 2001 From: Tao Li Date: Thu, 26 Jan 2023 14:29:59 -0800 Subject: [PATCH 111/453] Support route constraint. --- vpr/src/base/route_constraint.cpp | 43 ++++++++++++++++++++ vpr/src/base/route_constraint.h | 65 +++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) create mode 100644 vpr/src/base/route_constraint.cpp create mode 100644 vpr/src/base/route_constraint.h diff --git a/vpr/src/base/route_constraint.cpp b/vpr/src/base/route_constraint.cpp new file mode 100644 index 00000000000..2e2d9d524b2 --- /dev/null +++ b/vpr/src/base/route_constraint.cpp @@ -0,0 +1,43 @@ +#include "route_constraint.h" + +RouteConstraint::RouteConstraint() { + net_name_ = std::string(""); + net_type_ = std::string(""); + route_method_ = std::string(""); + is_valid_ = false; +} + +void RouteConstraint::set_net_name(std::string name) { + net_name_ = name; + return; +} + +std::string RouteConstraint::get_net_name() const { + return net_name_; +} + +void RouteConstraint::set_net_type(std::string type) { + net_type_ = type; + return; +} + +std::string RouteConstraint::get_net_type() const { + return net_type_; +} + +void RouteConstraint::set_route_model(std::string route_method) { + route_method_ = route_method; + return; +} + +std::string RouteConstraint::get_route_model() const { + return route_method_; +} + +void RouteConstraint::set_is_valid(bool value) { + is_valid_ = value;; +} + +bool RouteConstraint::get_is_valid() const { + return is_valid_; +} diff --git a/vpr/src/base/route_constraint.h b/vpr/src/base/route_constraint.h new file mode 100644 index 00000000000..50b967e3f31 --- /dev/null +++ b/vpr/src/base/route_constraint.h @@ -0,0 +1,65 @@ +#ifndef ROUTE_CONSTRAINT_H +#define ROUTE_CONSTRAINT_H + +#include "vpr_types.h" + +/** + * @file + * @brief This file defines the RouteConstraint class. + */ + +class RouteConstraint { + public: + /** + * @brief Constructor for the RouteConstraint class, sets member variables to invalid values + */ + RouteConstraint(); + + /** + * @brief get net name + */ + std::string get_net_name() const; + + /** + * @brief set net name + */ + void set_net_name(std::string); + + /** + * @brief get net type + */ + std::string get_net_type() const; + + /** + * @brief set net type + */ + void set_net_type(std::string); + + /** + * @brief get route model + */ + std::string get_route_model() const; + + /** + * @brief set route model + */ + void set_route_model(std::string); + + /** + * @brief set is valid + */ + void set_is_valid(bool); + + /** + * @brief get is valid + */ + bool get_is_valid() const; + + private: + std::string net_name_; + std::string net_type_; + std::string route_method_; + bool is_valid_; +}; + +#endif /* ROUTE_CONSTRAINT_H */ From 671c9d292605d8a87a1575044ca4c512a5bb96ab Mon Sep 17 00:00:00 2001 From: Tao Li Date: Thu, 26 Jan 2023 19:22:22 -0800 Subject: [PATCH 112/453] Support route constraints. --- vpr/src/base/gen/vpr_constraints_uxsdcxx.h | 253 +++++++++++++++++- .../gen/vpr_constraints_uxsdcxx_interface.h | 111 +++++--- vpr/src/base/vpr_api.cpp | 11 +- vpr/src/base/vpr_constraints.cpp | 42 +++ vpr/src/base/vpr_constraints.h | 34 +++ vpr/src/base/vpr_constraints.xsd | 21 ++ vpr/src/base/vpr_constraints_reader.cpp | 4 + vpr/src/base/vpr_constraints_serializer.h | 68 +++++ vpr/src/base/vpr_context.h | 5 + vpr/src/util/vpr_utils.cpp | 29 +- vpr/src/util/vpr_utils.h | 6 + 11 files changed, 526 insertions(+), 58 deletions(-) diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h index 3248c338281..836f6b95b49 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx.py vpr_constraints.xsd - * Input file: /home/khalid88/Documents/uxsdcxx/vpr_constraints.xsd - * md5sum of input file: 6b6011a6e6446347b234da82e517422e + * Cmdline: uxsdcxx.py /home/tao/works/dev/clock/test/xml_gen/vpr_constraints.xsd + * Input file: /home/tao/works/dev/clock/test/xml_gen/vpr_constraints.xsd + * md5sum of input file: 1ab0562dd315daffe9ac257ab683233e */ #include @@ -25,8 +25,6 @@ #include "pugixml.hpp" #include "vpr_constraints_uxsdcxx_interface.h" -#include "region.h" - /* All uxsdcxx functions and structs live in this namespace. */ namespace uxsd { @@ -52,6 +50,10 @@ inline void load_partition(const pugi::xml_node& root, T& out, Context& context, template inline void load_partition_list(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); template +inline void load_set_global_signal(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template +inline void load_global_route_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); /* Declarations for internal write functions for the complex types. */ @@ -60,6 +62,8 @@ inline void write_partition(T& in, std::ostream& os, const void* data, void* ite template inline void write_partition_list(T& in, std::ostream& os, const void* data, void* iter); template +inline void write_global_route_constraints(T& in, std::ostream& os, const void* data, void* iter); +template inline void write_vpr_constraints(T& in, std::ostream& os, const void* data, void* iter); /* Load function for the root element. */ @@ -142,8 +146,17 @@ constexpr const char* atok_lookup_t_partition[] = {"name"}; enum class gtok_t_partition_list { PARTITION }; constexpr const char* gtok_lookup_t_partition_list[] = {"partition"}; -enum class gtok_t_vpr_constraints { PARTITION_LIST }; -constexpr const char* gtok_lookup_t_vpr_constraints[] = {"partition_list"}; + +enum class atok_t_set_global_signal { NAME, + ROUTE_MODEL, + TYPE }; +constexpr const char* atok_lookup_t_set_global_signal[] = {"name", "route_model", "type"}; + +enum class gtok_t_global_route_constraints { SET_GLOBAL_SIGNAL }; +constexpr const char* gtok_lookup_t_global_route_constraints[] = {"set_global_signal"}; +enum class gtok_t_vpr_constraints { PARTITION_LIST, + GLOBAL_ROUTE_CONSTRAINTS }; +constexpr const char* gtok_lookup_t_vpr_constraints[] = {"partition_list", "global_route_constraints"}; enum class atok_t_vpr_constraints { TOOL_NAME }; constexpr const char* atok_lookup_t_vpr_constraints[] = {"tool_name"}; @@ -348,6 +361,84 @@ inline gtok_t_partition_list lex_node_t_partition_list(const char* in, const std noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); } +inline atok_t_set_global_signal lex_attr_t_set_global_signal(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 4: + switch (*((triehash_uu32*)&in[0])) { + case onechar('n', 0, 32) | onechar('a', 8, 32) | onechar('m', 16, 32) | onechar('e', 24, 32): + return atok_t_set_global_signal::NAME; + break; + case onechar('t', 0, 32) | onechar('y', 8, 32) | onechar('p', 16, 32) | onechar('e', 24, 32): + return atok_t_set_global_signal::TYPE; + break; + default: + break; + } + break; + case 11: + switch (*((triehash_uu64*)&in[0])) { + case onechar('r', 0, 64) | onechar('o', 8, 64) | onechar('u', 16, 64) | onechar('t', 24, 64) | onechar('e', 32, 64) | onechar('_', 40, 64) | onechar('m', 48, 64) | onechar('o', 56, 64): + switch (in[8]) { + case onechar('d', 0, 8): + switch (in[9]) { + case onechar('e', 0, 8): + switch (in[10]) { + case onechar('l', 0, 8): + return atok_t_set_global_signal::ROUTE_MODEL; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); +} + +inline gtok_t_global_route_constraints lex_node_t_global_route_constraints(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 17: + switch (*((triehash_uu64*)&in[0])) { + case onechar('s', 0, 64) | onechar('e', 8, 64) | onechar('t', 16, 64) | onechar('_', 24, 64) | onechar('g', 32, 64) | onechar('l', 40, 64) | onechar('o', 48, 64) | onechar('b', 56, 64): + switch (*((triehash_uu64*)&in[8])) { + case onechar('a', 0, 64) | onechar('l', 8, 64) | onechar('_', 16, 64) | onechar('s', 24, 64) | onechar('i', 32, 64) | onechar('g', 40, 64) | onechar('n', 48, 64) | onechar('a', 56, 64): + switch (in[16]) { + case onechar('l', 0, 8): + return gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); +} + inline gtok_t_vpr_constraints lex_node_t_vpr_constraints(const char* in, const std::function* report_error) { unsigned int len = strlen(in); switch (len) { @@ -378,6 +469,27 @@ inline gtok_t_vpr_constraints lex_node_t_vpr_constraints(const char* in, const s break; } break; + case 24: + switch (*((triehash_uu64*)&in[0])) { + case onechar('g', 0, 64) | onechar('l', 8, 64) | onechar('o', 16, 64) | onechar('b', 24, 64) | onechar('a', 32, 64) | onechar('l', 40, 64) | onechar('_', 48, 64) | onechar('r', 56, 64): + switch (*((triehash_uu64*)&in[8])) { + case onechar('o', 0, 64) | onechar('u', 8, 64) | onechar('t', 16, 64) | onechar('e', 24, 64) | onechar('_', 32, 64) | onechar('c', 40, 64) | onechar('o', 48, 64) | onechar('n', 56, 64): + switch (*((triehash_uu64*)&in[16])) { + case onechar('s', 0, 64) | onechar('t', 8, 64) | onechar('r', 16, 64) | onechar('a', 24, 64) | onechar('i', 32, 64) | onechar('n', 40, 64) | onechar('t', 48, 64) | onechar('s', 56, 64): + return gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; default: break; } @@ -427,8 +539,6 @@ template /* Internal loading functions, which validate and load a PugiXML DOM tree into memory. */ inline int load_int(const char* in, const std::function* report_error) { int out; - // global variable, must set to 0 before using it to avoid changed by other errors - errno = 0; out = std::strtol(in, NULL, 10); if (errno != 0) noreturn_report(report_error, ("Invalid value `" + std::string(in) + "` when loading into a int.").c_str()); @@ -674,6 +784,97 @@ inline void load_partition_list(const pugi::xml_node& root, T& out, Context& con if (state != 0) dfa_error("end of input", gstate_t_partition_list[state], gtok_lookup_t_partition_list, 1, report_error); } +template +inline void load_set_global_signal(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + for (pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()) { + atok_t_set_global_signal in = lex_attr_t_set_global_signal(attr.name(), report_error); + switch (in) { + case atok_t_set_global_signal::NAME: + out.set_set_global_signal_name(attr.value(), context); + break; + case atok_t_set_global_signal::ROUTE_MODEL: + out.set_set_global_signal_route_model(attr.value(), context); + break; + case atok_t_set_global_signal::TYPE: + out.set_set_global_signal_type(attr.value(), context); + break; + default: + break; /* Not possible. */ + } + } + + if (root.first_child().type() == pugi::node_element) + noreturn_report(report_error, "Unexpected child element in ."); +} + +constexpr int NUM_T_GLOBAL_ROUTE_CONSTRAINTS_STATES = 2; +constexpr const int NUM_T_GLOBAL_ROUTE_CONSTRAINTS_INPUTS = 1; +constexpr int gstate_t_global_route_constraints[NUM_T_GLOBAL_ROUTE_CONSTRAINTS_STATES][NUM_T_GLOBAL_ROUTE_CONSTRAINTS_INPUTS] = { + {0}, + {0}, +}; +template +inline void load_global_route_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + if (root.first_attribute()) + noreturn_report(report_error, "Unexpected attribute in ."); + + // Preallocate arrays by counting child nodes (if any) + size_t set_global_signal_count = 0; + { + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_global_route_constraints in = lex_node_t_global_route_constraints(node.name(), report_error); + next = gstate_t_global_route_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_global_route_constraints[(int)in], gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); + state = next; + switch (in) { + case gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL: + set_global_signal_count += 1; + break; + default: + break; /* Not possible. */ + } + } + + out.preallocate_global_route_constraints_set_global_signal(context, set_global_signal_count); + } + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_global_route_constraints in = lex_node_t_global_route_constraints(node.name(), report_error); + next = gstate_t_global_route_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_global_route_constraints[(int)in], gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); + state = next; + switch (in) { + case gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL: { + auto child_context = out.add_global_route_constraints_set_global_signal(context); + load_set_global_signal(node, out, child_context, report_error, offset_debug); + out.finish_global_route_constraints_set_global_signal(child_context); + } break; + default: + break; /* Not possible. */ + } + } + if (state != 0) dfa_error("end of input", gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); +} + template inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { (void)root; @@ -694,7 +895,7 @@ inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& co } } - std::bitset<1> gstate = 0; + std::bitset<2> gstate = 0; for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { *offset_debug = node.offset_debug(); gtok_t_vpr_constraints in = lex_node_t_vpr_constraints(node.name(), report_error); @@ -708,11 +909,16 @@ inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& co load_partition_list(node, out, child_context, report_error, offset_debug); out.finish_vpr_constraints_partition_list(child_context); } break; + case gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS: { + auto child_context = out.init_vpr_constraints_global_route_constraints(context); + load_global_route_constraints(node, out, child_context, report_error, offset_debug); + out.finish_vpr_constraints_global_route_constraints(child_context); + } break; default: break; /* Not possible. */ } } - std::bitset<1> test_gstate = gstate | std::bitset<1>(0b0); + std::bitset<2> test_gstate = gstate | std::bitset<2>(0b00); if (!test_gstate.all()) all_error(test_gstate, gtok_lookup_t_vpr_constraints, report_error); } @@ -734,7 +940,7 @@ inline void write_partition(T& in, std::ostream& os, Context& context) { for (size_t i = 0, n = in.num_partition_add_region(context); i < n; i++) { auto child_context = in.get_partition_add_region(i, context); os << " +inline void write_global_route_constraints(T& in, std::ostream& os, Context& context) { + (void)in; + (void)os; + (void)context; + { + for (size_t i = 0, n = in.num_global_route_constraints_set_global_signal(context); i < n; i++) { + auto child_context = in.get_global_route_constraints_set_global_signal(i, context); + os << "\n"; + } + } +} + template inline void write_vpr_constraints(T& in, std::ostream& os, Context& context) { (void)in; @@ -773,6 +996,12 @@ inline void write_vpr_constraints(T& in, std::ostream& os, Context& context) { write_partition_list(in, os, child_context); os << "\n"; } + { + auto child_context = in.get_vpr_constraints_global_route_constraints(context); + os << "\n"; + write_global_route_constraints(in, os, child_context); + os << "\n"; + } } inline void dfa_error(const char* wrong, const int* states, const char* const* lookup, int len, const std::function* report_error) { diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h index 6da8558b84d..d554afa970b 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx.py vpr_constraints.xsd - * Input file: /home/khalid88/Documents/uxsdcxx/vpr_constraints.xsd - * md5sum of input file: 6b6011a6e6446347b234da82e517422e + * Cmdline: uxsdcxx.py /home/tao/works/dev/clock/test/xml_gen/vpr_constraints.xsd + * Input file: /home/tao/works/dev/clock/test/xml_gen/vpr_constraints.xsd + * md5sum of input file: 1ab0562dd315daffe9ac257ab683233e */ #include @@ -24,11 +24,15 @@ struct DefaultVprConstraintsContextTypes { using AddRegionReadContext = void*; using PartitionReadContext = void*; using PartitionListReadContext = void*; + using SetGlobalSignalReadContext = void*; + using GlobalRouteConstraintsReadContext = void*; using VprConstraintsReadContext = void*; using AddAtomWriteContext = void*; using AddRegionWriteContext = void*; using PartitionWriteContext = void*; using PartitionListWriteContext = void*; + using SetGlobalSignalWriteContext = void*; + using GlobalRouteConstraintsWriteContext = void*; using VprConstraintsWriteContext = void*; }; @@ -42,22 +46,22 @@ class VprConstraintsBase { virtual void finish_write() = 0; virtual void error_encountered(const char* file, int line, const char* message) = 0; /** Generated for complex type "add_atom": - * - * - * - */ + * + * + * + */ virtual inline const char* get_add_atom_name_pattern(typename ContextTypes::AddAtomReadContext& ctx) = 0; virtual inline void set_add_atom_name_pattern(const char* name_pattern, typename ContextTypes::AddAtomWriteContext& ctx) = 0; /** Generated for complex type "add_region": - * - * - * - * - * - * - * - */ + * + * + * + * + * + * + * + */ virtual inline int get_add_region_subtile(typename ContextTypes::AddRegionReadContext& ctx) = 0; virtual inline void set_add_region_subtile(int subtile, typename ContextTypes::AddRegionWriteContext& ctx) = 0; virtual inline int get_add_region_x_high(typename ContextTypes::AddRegionReadContext& ctx) = 0; @@ -66,16 +70,16 @@ class VprConstraintsBase { virtual inline int get_add_region_y_low(typename ContextTypes::AddRegionReadContext& ctx) = 0; /** Generated for complex type "partition": - * - * - * - * - * - * - * - * - * - */ + * + * + * + * + * + * + * + * + * + */ virtual inline const char* get_partition_name(typename ContextTypes::PartitionReadContext& ctx) = 0; virtual inline void set_partition_name(const char* name, typename ContextTypes::PartitionWriteContext& ctx) = 0; virtual inline void preallocate_partition_add_atom(typename ContextTypes::PartitionWriteContext& ctx, size_t size) = 0; @@ -90,31 +94,62 @@ class VprConstraintsBase { virtual inline typename ContextTypes::AddRegionReadContext get_partition_add_region(int n, typename ContextTypes::PartitionReadContext& ctx) = 0; /** Generated for complex type "partition_list": - * - * - * - * - * - */ + * + * + * + * + * + */ virtual inline void preallocate_partition_list_partition(typename ContextTypes::PartitionListWriteContext& ctx, size_t size) = 0; virtual inline typename ContextTypes::PartitionWriteContext add_partition_list_partition(typename ContextTypes::PartitionListWriteContext& ctx) = 0; virtual inline void finish_partition_list_partition(typename ContextTypes::PartitionWriteContext& ctx) = 0; virtual inline size_t num_partition_list_partition(typename ContextTypes::PartitionListReadContext& ctx) = 0; virtual inline typename ContextTypes::PartitionReadContext get_partition_list_partition(int n, typename ContextTypes::PartitionListReadContext& ctx) = 0; + /** Generated for complex type "set_global_signal": + * + * + * + * + * + */ + virtual inline const char* get_set_global_signal_name(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_name(const char* name, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline const char* get_set_global_signal_route_model(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_route_model(const char* route_model, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline const char* get_set_global_signal_type(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_type(const char* type, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + + /** Generated for complex type "global_route_constraints": + * + * + * + * + * + */ + virtual inline void preallocate_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::SetGlobalSignalWriteContext add_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx) = 0; + virtual inline void finish_global_route_constraints_set_global_signal(typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline size_t num_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsReadContext& ctx) = 0; + virtual inline typename ContextTypes::SetGlobalSignalReadContext get_global_route_constraints_set_global_signal(int n, typename ContextTypes::GlobalRouteConstraintsReadContext& ctx) = 0; + /** Generated for complex type "vpr_constraints": - * - * - * - * - * - * - */ + * + * + * + * + * + * + * + */ virtual inline const char* get_vpr_constraints_tool_name(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; virtual inline void set_vpr_constraints_tool_name(const char* tool_name, typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; virtual inline typename ContextTypes::PartitionListWriteContext init_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; virtual inline void finish_vpr_constraints_partition_list(typename ContextTypes::PartitionListWriteContext& ctx) = 0; virtual inline typename ContextTypes::PartitionListReadContext get_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline typename ContextTypes::GlobalRouteConstraintsWriteContext init_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; + virtual inline void finish_vpr_constraints_global_route_constraints(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx) = 0; + virtual inline typename ContextTypes::GlobalRouteConstraintsReadContext get_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; }; } /* namespace uxsd */ diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 123991d4c8e..3911ecd16fb 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -346,10 +346,15 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a } } - //Initialize vpr floorplanning constraints + //Initialize vpr floorplanning and routing constraints auto& filename_opts = vpr_setup->FileNameOpts; if (!filename_opts.read_vpr_constraints_file.empty()) { load_vpr_constraints_file(filename_opts.read_vpr_constraints_file.c_str()); + + // give a notificaiton on routing constraints overiding clock modeling + if (g_vpr_ctx.routing().constraints.get_route_constraint_num() && options->clock_modeling.provenance() == argparse::Provenance::SPECIFIED) { + VTR_LOG_WARN("Route constraint(s) detected and will override clock modeling setting.\n"); + } } fflush(stdout); @@ -766,6 +771,10 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_f //Assume successful route_status = RouteStatus(true, -1); } else { //Do or load + + // apply route constraints + apply_route_constraints(g_vpr_ctx.routing().constraints); + int chan_width = router_opts.fixed_channel_width; auto& cluster_ctx = g_vpr_ctx.clustering(); diff --git a/vpr/src/base/vpr_constraints.cpp b/vpr/src/base/vpr_constraints.cpp index 95c7e7b7358..5dec3889dfe 100644 --- a/vpr/src/base/vpr_constraints.cpp +++ b/vpr/src/base/vpr_constraints.cpp @@ -1,5 +1,6 @@ #include "vpr_constraints.h" #include "partition.h" +#include "route_constraint.h" void VprConstraints::add_constrained_atom(const AtomBlockId blk_id, const PartitionId part_id) { auto got = constrained_atoms.find(blk_id); @@ -58,6 +59,47 @@ PartitionRegion VprConstraints::get_partition_pr(PartitionId part_id) { return pr; } +void VprConstraints::add_route_constraint(RouteConstraint rc) { + route_constraints_.insert({rc.get_net_name(), rc}); + return; +} + +RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) const { + RouteConstraint rc; + auto const& rc_itr = route_constraints_.find(net_name); + if (rc_itr == route_constraints_.end()) { + rc.set_net_name("INVALID"); + rc.set_net_type("INVALID"); + rc.set_route_model("INVALID"); + rc.set_is_valid(false); + } else { + rc = rc_itr->second; + } + return rc; +} + +RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) const { + RouteConstraint rc; + if ((route_constraints_.size() == 0) || (idx > route_constraints_.size() - 1)) { + rc.set_net_name("INVALID"); + rc.set_net_type("INVALID"); + rc.set_route_model("INVALID"); + rc.set_is_valid(false); + } else { + std::size_t i = 0; + for (auto const& rc_itr : route_constraints_) { + if (i == idx) { + rc = rc_itr.second; + } + } + } + return rc; +} + +int VprConstraints::get_route_constraint_num(void) const { + return route_constraints_.size(); +} + void print_constraints(FILE* fp, VprConstraints constraints) { Partition temp_part; std::vector atoms; diff --git a/vpr/src/base/vpr_constraints.h b/vpr/src/base/vpr_constraints.h index fd3f64842a4..fbe4e314f75 100644 --- a/vpr/src/base/vpr_constraints.h +++ b/vpr/src/base/vpr_constraints.h @@ -5,6 +5,7 @@ #include "vpr_utils.h" #include "partition.h" #include "partition_region.h" +#include "route_constraint.h" /** * @file @@ -87,6 +88,34 @@ class VprConstraints { */ PartitionRegion get_partition_pr(PartitionId part_id); + /** + * @brief add route constraint + * + * @param net_name the route constraint + */ + void add_route_constraint(RouteConstraint rc); + + /** + * @brief returns route constraint by index + * + * @param index the constraint index + */ + RouteConstraint get_route_constraint_by_idx(std::size_t index) const; + + /** + * @brief returns route constraint of a specific net + * + * @param net_name the net name + */ + RouteConstraint get_route_constraint_by_net_name(std::string net_name) const; + + /** + * @brief returns number of route constraints + * + * @param void + */ + int get_route_constraint_num(void) const; + private: /** * Store all constrained atoms @@ -97,6 +126,11 @@ class VprConstraints { * Store all partitions */ vtr::vector partitions; + + /** + * store all route constraints + */ + std::unordered_map route_constraints_; }; ///@brief used to print floorplanning constraints data from a VprConstraints object diff --git a/vpr/src/base/vpr_constraints.xsd b/vpr/src/base/vpr_constraints.xsd index 406e2abcda4..9144e656081 100644 --- a/vpr/src/base/vpr_constraints.xsd +++ b/vpr/src/base/vpr_constraints.xsd @@ -59,6 +59,26 @@ + + + + + + + + + + + + + + + - + - - + diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index 4c2666d0d6d..ddfe531e587 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -356,48 +356,66 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase - * - * + * + * + * * - * - * - * - */ + * + * + * + */ virtual inline const char* get_vpr_constraints_tool_name(void*& /*ctx*/) final { return temp_.c_str(); } - virtual inline void set_vpr_constraints_tool_name(const char* /*tool_name*/, void*& /*ctx*/) final {} + virtual inline void set_vpr_constraints_tool_name(const char* /*tool_name*/, void*& /*ctx*/) final { + } virtual inline void set_vpr_constraints_constraints_comment(const char* /*constraints_comment*/, void*& /*ctx*/) final {} virtual inline const char* get_vpr_constraints_constraints_comment(void*& /*ctx*/) final { return temp_.c_str(); } - virtual inline void* init_vpr_constraints_partition_list(void*& /*ctx*/) final { + + virtual inline void preallocate_vpr_constraints_partition_list(void*& /*ctx*/, size_t) final { + } + + virtual inline void* add_vpr_constraints_partition_list(void*& /*ctx*/) final { return nullptr; } virtual inline void finish_vpr_constraints_partition_list(void*& /*ctx*/) final { + return; } - virtual inline void* get_vpr_constraints_partition_list(void*& /*ctx*/) final { + virtual inline size_t num_vpr_constraints_partition_list(void*& /*ctx*/) final { + return 0; + } + + virtual inline void* get_vpr_constraints_partition_list(int, void*& /*ctx*/) final { return nullptr; } - virtual inline void* init_vpr_constraints_global_route_constraints(void*& /*ctx*/) final { + virtual inline void preallocate_vpr_constraints_global_route_constraints(void*& /*ctx*/, size_t) final { + } + + virtual inline void* add_vpr_constraints_global_route_constraints(void*& /*ctx*/) final { return nullptr; } virtual inline void finish_vpr_constraints_global_route_constraints(void*& /*ctx*/) final { + return; + } + virtual inline size_t num_vpr_constraints_global_route_constraints(void*& /*ctx*/) final { + return 0; } - virtual inline void* get_vpr_constraints_global_route_constraints(void*& /*ctx*/) final { + virtual inline void* get_vpr_constraints_global_route_constraints(int, void*& /*cts*/) final { return nullptr; } virtual void finish_load() final { + return; } //temp data for writes From afed57f519a605842ea2b84a41d7d8ffcb70899d Mon Sep 17 00:00:00 2001 From: Tao Li Date: Thu, 2 Feb 2023 21:09:21 -0800 Subject: [PATCH 115/453] Code format clang-7. --- vpr/src/base/gen/vpr_constraints_uxsdcxx.h | 1860 +++++++++-------- .../gen/vpr_constraints_uxsdcxx_interface.h | 251 ++- vpr/src/base/vpr_api.cpp | 2 +- vpr/src/base/vpr_constraints.cpp | 8 +- vpr/src/base/vpr_constraints_serializer.h | 40 +- vpr/src/base/vpr_context.h | 2 +- vpr/src/util/vpr_utils.cpp | 6 +- 7 files changed, 1107 insertions(+), 1062 deletions(-) diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h index db6e59cc088..12feabd08ab 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h @@ -11,7 +11,6 @@ #include - #include #include #include @@ -33,1026 +32,1073 @@ namespace uxsd { * Internal function for getting line and column number from file based on * byte offset. */ -inline void get_line_number(const char *filename, std::ptrdiff_t offset, int * line, int * col); +inline void get_line_number(const char* filename, std::ptrdiff_t offset, int* line, int* col); -[[noreturn]] inline void noreturn_report(const std::function * report_error, const char *msg) { +[[noreturn]] inline void noreturn_report(const std::function* report_error, const char* msg) { (*report_error)(msg); throw std::runtime_error("Unreachable!"); } /* Declarations for internal load functions for the complex types. */ -template -inline void load_add_atom(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); -template -inline void load_add_region(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); -inline void load_add_region_required_attributes(const pugi::xml_node &root, int * x_high, int * x_low, int * y_high, int * y_low, const std::function * report_error); -template -inline void load_partition(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); -template -inline void load_partition_list(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); -template -inline void load_set_global_signal(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); -template -inline void load_global_route_constraints(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); -template -inline void load_vpr_constraints(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); +template +inline void load_add_atom(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template +inline void load_add_region(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +inline void load_add_region_required_attributes(const pugi::xml_node& root, int* x_high, int* x_low, int* y_high, int* y_low, const std::function* report_error); +template +inline void load_partition(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template +inline void load_partition_list(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template +inline void load_set_global_signal(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template +inline void load_global_route_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template +inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); /* Declarations for internal write functions for the complex types. */ -template -inline void write_partition(T &in, std::ostream &os, const void *data, void *iter); -template -inline void write_partition_list(T &in, std::ostream &os, const void *data, void *iter); -template -inline void write_global_route_constraints(T &in, std::ostream &os, const void *data, void *iter); -template -inline void write_vpr_constraints(T &in, std::ostream &os, const void *data, void *iter); +template +inline void write_partition(T& in, std::ostream& os, const void* data, void* iter); +template +inline void write_partition_list(T& in, std::ostream& os, const void* data, void* iter); +template +inline void write_global_route_constraints(T& in, std::ostream& os, const void* data, void* iter); +template +inline void write_vpr_constraints(T& in, std::ostream& os, const void* data, void* iter); /* Load function for the root element. */ -template -inline void load_vpr_constraints_xml(T &out, Context &context, const char * filename, std::istream &is){ - pugi::xml_document doc; - pugi::xml_parse_result result = doc.load(is); - if(!result) { - int line, col; - get_line_number(filename, result.offset, &line, &col); - std::stringstream msg; - msg << "Unable to load XML file '" << filename << "', "; - msg << result.description() << " (line: " << line; - msg << " col: " << col << ")"; out.error_encountered(filename, line, msg.str().c_str()); - } - ptrdiff_t offset_debug = 0; - std::function report_error = [filename, &out, &offset_debug](const char * message) { - int line, col; - get_line_number(filename, offset_debug, &line, &col); - out.error_encountered(filename, line, message); - // If error_encountered didn't throw, throw now to unwind. - throw std::runtime_error(message); - }; - out.start_load(&report_error); - - for(pugi::xml_node node= doc.first_child(); node; node = node.next_sibling()){ - if(std::strcmp(node.name(), "vpr_constraints") == 0){ - /* If errno is set up to this point, it messes with strtol errno checking. */ - errno = 0; - load_vpr_constraints(node, out, context, &report_error, &offset_debug); - } else { - offset_debug = node.offset_debug(); - report_error(("Invalid root-level element " + std::string(node.name())).c_str()); - } - } - out.finish_load(); +template +inline void load_vpr_constraints_xml(T& out, Context& context, const char* filename, std::istream& is) { + pugi::xml_document doc; + pugi::xml_parse_result result = doc.load(is); + if (!result) { + int line, col; + get_line_number(filename, result.offset, &line, &col); + std::stringstream msg; + msg << "Unable to load XML file '" << filename << "', "; + msg << result.description() << " (line: " << line; + msg << " col: " << col << ")"; + out.error_encountered(filename, line, msg.str().c_str()); + } + ptrdiff_t offset_debug = 0; + std::function report_error = [filename, &out, &offset_debug](const char* message) { + int line, col; + get_line_number(filename, offset_debug, &line, &col); + out.error_encountered(filename, line, message); + // If error_encountered didn't throw, throw now to unwind. + throw std::runtime_error(message); + }; + out.start_load(&report_error); + + for (pugi::xml_node node = doc.first_child(); node; node = node.next_sibling()) { + if (std::strcmp(node.name(), "vpr_constraints") == 0) { + /* If errno is set up to this point, it messes with strtol errno checking. */ + errno = 0; + load_vpr_constraints(node, out, context, &report_error, &offset_debug); + } else { + offset_debug = node.offset_debug(); + report_error(("Invalid root-level element " + std::string(node.name())).c_str()); + } + } + out.finish_load(); } /* Write function for the root element. */ -template -inline void write_vpr_constraints_xml(T &in, Context &context, std::ostream &os){ - in.start_write(); - os << "\n"; - write_vpr_constraints(in, os, context); - os << "\n"; - in.finish_write(); +template +inline void write_vpr_constraints_xml(T& in, Context& context, std::ostream& os) { + in.start_write(); + os << "\n"; + write_vpr_constraints(in, os, context); + os << "\n"; + in.finish_write(); } - typedef const uint32_t __attribute__((aligned(1))) triehash_uu32; typedef const uint64_t __attribute__((aligned(1))) triehash_uu64; static_assert(alignof(triehash_uu32) == 1, "Unaligned 32-bit access not found."); static_assert(alignof(triehash_uu64) == 1, "Unaligned 64-bit access not found."); #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -#define onechar(c, s, l) (((uint64_t)(c)) << (s)) +# define onechar(c, s, l) (((uint64_t)(c)) << (s)) #else -#define onechar(c, s, l) (((uint64_t)(c)) << (l-8-s)) +# define onechar(c, s, l) (((uint64_t)(c)) << (l - 8 - s)) #endif /* Tokens for attribute and node names. */ -enum class atok_t_add_atom {NAME_PATTERN}; -constexpr const char *atok_lookup_t_add_atom[] = {"name_pattern"}; - - -enum class atok_t_add_region {SUBTILE, X_HIGH, X_LOW, Y_HIGH, Y_LOW}; -constexpr const char *atok_lookup_t_add_region[] = {"subtile", "x_high", "x_low", "y_high", "y_low"}; - -enum class gtok_t_partition {ADD_ATOM, ADD_REGION}; -constexpr const char *gtok_lookup_t_partition[] = {"add_atom", "add_region"}; -enum class atok_t_partition {NAME}; -constexpr const char *atok_lookup_t_partition[] = {"name"}; - -enum class gtok_t_partition_list {PARTITION}; -constexpr const char *gtok_lookup_t_partition_list[] = {"partition"}; - -enum class atok_t_set_global_signal {NAME, ROUTE_MODEL, TYPE}; -constexpr const char *atok_lookup_t_set_global_signal[] = {"name", "route_model", "type"}; - -enum class gtok_t_global_route_constraints {SET_GLOBAL_SIGNAL}; -constexpr const char *gtok_lookup_t_global_route_constraints[] = {"set_global_signal"}; -enum class gtok_t_vpr_constraints {PARTITION_LIST, GLOBAL_ROUTE_CONSTRAINTS}; -constexpr const char *gtok_lookup_t_vpr_constraints[] = {"partition_list", "global_route_constraints"}; -enum class atok_t_vpr_constraints {TOOL_NAME}; -constexpr const char *atok_lookup_t_vpr_constraints[] = {"tool_name"}; - +enum class atok_t_add_atom { NAME_PATTERN }; +constexpr const char* atok_lookup_t_add_atom[] = {"name_pattern"}; + +enum class atok_t_add_region { SUBTILE, + X_HIGH, + X_LOW, + Y_HIGH, + Y_LOW }; +constexpr const char* atok_lookup_t_add_region[] = {"subtile", "x_high", "x_low", "y_high", "y_low"}; + +enum class gtok_t_partition { ADD_ATOM, + ADD_REGION }; +constexpr const char* gtok_lookup_t_partition[] = {"add_atom", "add_region"}; +enum class atok_t_partition { NAME }; +constexpr const char* atok_lookup_t_partition[] = {"name"}; + +enum class gtok_t_partition_list { PARTITION }; +constexpr const char* gtok_lookup_t_partition_list[] = {"partition"}; + +enum class atok_t_set_global_signal { NAME, + ROUTE_MODEL, + TYPE }; +constexpr const char* atok_lookup_t_set_global_signal[] = {"name", "route_model", "type"}; + +enum class gtok_t_global_route_constraints { SET_GLOBAL_SIGNAL }; +constexpr const char* gtok_lookup_t_global_route_constraints[] = {"set_global_signal"}; +enum class gtok_t_vpr_constraints { PARTITION_LIST, + GLOBAL_ROUTE_CONSTRAINTS }; +constexpr const char* gtok_lookup_t_vpr_constraints[] = {"partition_list", "global_route_constraints"}; +enum class atok_t_vpr_constraints { TOOL_NAME }; +constexpr const char* atok_lookup_t_vpr_constraints[] = {"tool_name"}; /* Internal lexers. These convert the PugiXML node names to input tokens. */ -inline atok_t_add_atom lex_attr_t_add_atom(const char *in, const std::function * report_error){ - unsigned int len = strlen(in); - switch(len){ - case 12: - switch(*((triehash_uu64*)&in[0])){ - case onechar('n', 0, 64) | onechar('a', 8, 64) | onechar('m', 16, 64) | onechar('e', 24, 64) | onechar('_', 32, 64) | onechar('p', 40, 64) | onechar('a', 48, 64) | onechar('t', 56, 64): - switch(*((triehash_uu32*)&in[8])){ - case onechar('t', 0, 32) | onechar('e', 8, 32) | onechar('r', 16, 32) | onechar('n', 24, 32): - return atok_t_add_atom::NAME_PATTERN; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); +inline atok_t_add_atom lex_attr_t_add_atom(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 12: + switch (*((triehash_uu64*)&in[0])) { + case onechar('n', 0, 64) | onechar('a', 8, 64) | onechar('m', 16, 64) | onechar('e', 24, 64) | onechar('_', 32, 64) | onechar('p', 40, 64) | onechar('a', 48, 64) | onechar('t', 56, 64): + switch (*((triehash_uu32*)&in[8])) { + case onechar('t', 0, 32) | onechar('e', 8, 32) | onechar('r', 16, 32) | onechar('n', 24, 32): + return atok_t_add_atom::NAME_PATTERN; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); } -inline atok_t_add_region lex_attr_t_add_region(const char *in, const std::function * report_error){ - unsigned int len = strlen(in); - switch(len){ - case 5: - switch(*((triehash_uu32*)&in[0])){ - case onechar('x', 0, 32) | onechar('_', 8, 32) | onechar('l', 16, 32) | onechar('o', 24, 32): - switch(in[4]){ - case onechar('w', 0, 8): - return atok_t_add_region::X_LOW; - break; - default: break; - } - break; - case onechar('y', 0, 32) | onechar('_', 8, 32) | onechar('l', 16, 32) | onechar('o', 24, 32): - switch(in[4]){ - case onechar('w', 0, 8): - return atok_t_add_region::Y_LOW; - break; - default: break; - } - break; - default: break; - } - break; - case 6: - switch(*((triehash_uu32*)&in[0])){ - case onechar('x', 0, 32) | onechar('_', 8, 32) | onechar('h', 16, 32) | onechar('i', 24, 32): - switch(in[4]){ - case onechar('g', 0, 8): - switch(in[5]){ - case onechar('h', 0, 8): - return atok_t_add_region::X_HIGH; - break; - default: break; - } - break; - default: break; - } - break; - case onechar('y', 0, 32) | onechar('_', 8, 32) | onechar('h', 16, 32) | onechar('i', 24, 32): - switch(in[4]){ - case onechar('g', 0, 8): - switch(in[5]){ - case onechar('h', 0, 8): - return atok_t_add_region::Y_HIGH; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - case 7: - switch(*((triehash_uu32*)&in[0])){ - case onechar('s', 0, 32) | onechar('u', 8, 32) | onechar('b', 16, 32) | onechar('t', 24, 32): - switch(in[4]){ - case onechar('i', 0, 8): - switch(in[5]){ - case onechar('l', 0, 8): - switch(in[6]){ - case onechar('e', 0, 8): - return atok_t_add_region::SUBTILE; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); +inline atok_t_add_region lex_attr_t_add_region(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 5: + switch (*((triehash_uu32*)&in[0])) { + case onechar('x', 0, 32) | onechar('_', 8, 32) | onechar('l', 16, 32) | onechar('o', 24, 32): + switch (in[4]) { + case onechar('w', 0, 8): + return atok_t_add_region::X_LOW; + break; + default: + break; + } + break; + case onechar('y', 0, 32) | onechar('_', 8, 32) | onechar('l', 16, 32) | onechar('o', 24, 32): + switch (in[4]) { + case onechar('w', 0, 8): + return atok_t_add_region::Y_LOW; + break; + default: + break; + } + break; + default: + break; + } + break; + case 6: + switch (*((triehash_uu32*)&in[0])) { + case onechar('x', 0, 32) | onechar('_', 8, 32) | onechar('h', 16, 32) | onechar('i', 24, 32): + switch (in[4]) { + case onechar('g', 0, 8): + switch (in[5]) { + case onechar('h', 0, 8): + return atok_t_add_region::X_HIGH; + break; + default: + break; + } + break; + default: + break; + } + break; + case onechar('y', 0, 32) | onechar('_', 8, 32) | onechar('h', 16, 32) | onechar('i', 24, 32): + switch (in[4]) { + case onechar('g', 0, 8): + switch (in[5]) { + case onechar('h', 0, 8): + return atok_t_add_region::Y_HIGH; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + case 7: + switch (*((triehash_uu32*)&in[0])) { + case onechar('s', 0, 32) | onechar('u', 8, 32) | onechar('b', 16, 32) | onechar('t', 24, 32): + switch (in[4]) { + case onechar('i', 0, 8): + switch (in[5]) { + case onechar('l', 0, 8): + switch (in[6]) { + case onechar('e', 0, 8): + return atok_t_add_region::SUBTILE; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); } -inline gtok_t_partition lex_node_t_partition(const char *in, const std::function *report_error){ - unsigned int len = strlen(in); - switch(len){ - case 8: - switch(*((triehash_uu64*)&in[0])){ - case onechar('a', 0, 64) | onechar('d', 8, 64) | onechar('d', 16, 64) | onechar('_', 24, 64) | onechar('a', 32, 64) | onechar('t', 40, 64) | onechar('o', 48, 64) | onechar('m', 56, 64): - return gtok_t_partition::ADD_ATOM; - break; - default: break; - } - break; - case 10: - switch(*((triehash_uu64*)&in[0])){ - case onechar('a', 0, 64) | onechar('d', 8, 64) | onechar('d', 16, 64) | onechar('_', 24, 64) | onechar('r', 32, 64) | onechar('e', 40, 64) | onechar('g', 48, 64) | onechar('i', 56, 64): - switch(in[8]){ - case onechar('o', 0, 8): - switch(in[9]){ - case onechar('n', 0, 8): - return gtok_t_partition::ADD_REGION; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); +inline gtok_t_partition lex_node_t_partition(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 8: + switch (*((triehash_uu64*)&in[0])) { + case onechar('a', 0, 64) | onechar('d', 8, 64) | onechar('d', 16, 64) | onechar('_', 24, 64) | onechar('a', 32, 64) | onechar('t', 40, 64) | onechar('o', 48, 64) | onechar('m', 56, 64): + return gtok_t_partition::ADD_ATOM; + break; + default: + break; + } + break; + case 10: + switch (*((triehash_uu64*)&in[0])) { + case onechar('a', 0, 64) | onechar('d', 8, 64) | onechar('d', 16, 64) | onechar('_', 24, 64) | onechar('r', 32, 64) | onechar('e', 40, 64) | onechar('g', 48, 64) | onechar('i', 56, 64): + switch (in[8]) { + case onechar('o', 0, 8): + switch (in[9]) { + case onechar('n', 0, 8): + return gtok_t_partition::ADD_REGION; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); } -inline atok_t_partition lex_attr_t_partition(const char *in, const std::function * report_error){ - unsigned int len = strlen(in); - switch(len){ - case 4: - switch(*((triehash_uu32*)&in[0])){ - case onechar('n', 0, 32) | onechar('a', 8, 32) | onechar('m', 16, 32) | onechar('e', 24, 32): - return atok_t_partition::NAME; - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); +inline atok_t_partition lex_attr_t_partition(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 4: + switch (*((triehash_uu32*)&in[0])) { + case onechar('n', 0, 32) | onechar('a', 8, 32) | onechar('m', 16, 32) | onechar('e', 24, 32): + return atok_t_partition::NAME; + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); } -inline gtok_t_partition_list lex_node_t_partition_list(const char *in, const std::function *report_error){ - unsigned int len = strlen(in); - switch(len){ - case 9: - switch(*((triehash_uu64*)&in[0])){ - case onechar('p', 0, 64) | onechar('a', 8, 64) | onechar('r', 16, 64) | onechar('t', 24, 64) | onechar('i', 32, 64) | onechar('t', 40, 64) | onechar('i', 48, 64) | onechar('o', 56, 64): - switch(in[8]){ - case onechar('n', 0, 8): - return gtok_t_partition_list::PARTITION; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); +inline gtok_t_partition_list lex_node_t_partition_list(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 9: + switch (*((triehash_uu64*)&in[0])) { + case onechar('p', 0, 64) | onechar('a', 8, 64) | onechar('r', 16, 64) | onechar('t', 24, 64) | onechar('i', 32, 64) | onechar('t', 40, 64) | onechar('i', 48, 64) | onechar('o', 56, 64): + switch (in[8]) { + case onechar('n', 0, 8): + return gtok_t_partition_list::PARTITION; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); } -inline atok_t_set_global_signal lex_attr_t_set_global_signal(const char *in, const std::function * report_error){ - unsigned int len = strlen(in); - switch(len){ - case 4: - switch(*((triehash_uu32*)&in[0])){ - case onechar('n', 0, 32) | onechar('a', 8, 32) | onechar('m', 16, 32) | onechar('e', 24, 32): - return atok_t_set_global_signal::NAME; - break; - case onechar('t', 0, 32) | onechar('y', 8, 32) | onechar('p', 16, 32) | onechar('e', 24, 32): - return atok_t_set_global_signal::TYPE; - break; - default: break; - } - break; - case 11: - switch(*((triehash_uu64*)&in[0])){ - case onechar('r', 0, 64) | onechar('o', 8, 64) | onechar('u', 16, 64) | onechar('t', 24, 64) | onechar('e', 32, 64) | onechar('_', 40, 64) | onechar('m', 48, 64) | onechar('o', 56, 64): - switch(in[8]){ - case onechar('d', 0, 8): - switch(in[9]){ - case onechar('e', 0, 8): - switch(in[10]){ - case onechar('l', 0, 8): - return atok_t_set_global_signal::ROUTE_MODEL; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); +inline atok_t_set_global_signal lex_attr_t_set_global_signal(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 4: + switch (*((triehash_uu32*)&in[0])) { + case onechar('n', 0, 32) | onechar('a', 8, 32) | onechar('m', 16, 32) | onechar('e', 24, 32): + return atok_t_set_global_signal::NAME; + break; + case onechar('t', 0, 32) | onechar('y', 8, 32) | onechar('p', 16, 32) | onechar('e', 24, 32): + return atok_t_set_global_signal::TYPE; + break; + default: + break; + } + break; + case 11: + switch (*((triehash_uu64*)&in[0])) { + case onechar('r', 0, 64) | onechar('o', 8, 64) | onechar('u', 16, 64) | onechar('t', 24, 64) | onechar('e', 32, 64) | onechar('_', 40, 64) | onechar('m', 48, 64) | onechar('o', 56, 64): + switch (in[8]) { + case onechar('d', 0, 8): + switch (in[9]) { + case onechar('e', 0, 8): + switch (in[10]) { + case onechar('l', 0, 8): + return atok_t_set_global_signal::ROUTE_MODEL; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); } -inline gtok_t_global_route_constraints lex_node_t_global_route_constraints(const char *in, const std::function *report_error){ - unsigned int len = strlen(in); - switch(len){ - case 17: - switch(*((triehash_uu64*)&in[0])){ - case onechar('s', 0, 64) | onechar('e', 8, 64) | onechar('t', 16, 64) | onechar('_', 24, 64) | onechar('g', 32, 64) | onechar('l', 40, 64) | onechar('o', 48, 64) | onechar('b', 56, 64): - switch(*((triehash_uu64*)&in[8])){ - case onechar('a', 0, 64) | onechar('l', 8, 64) | onechar('_', 16, 64) | onechar('s', 24, 64) | onechar('i', 32, 64) | onechar('g', 40, 64) | onechar('n', 48, 64) | onechar('a', 56, 64): - switch(in[16]){ - case onechar('l', 0, 8): - return gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); +inline gtok_t_global_route_constraints lex_node_t_global_route_constraints(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 17: + switch (*((triehash_uu64*)&in[0])) { + case onechar('s', 0, 64) | onechar('e', 8, 64) | onechar('t', 16, 64) | onechar('_', 24, 64) | onechar('g', 32, 64) | onechar('l', 40, 64) | onechar('o', 48, 64) | onechar('b', 56, 64): + switch (*((triehash_uu64*)&in[8])) { + case onechar('a', 0, 64) | onechar('l', 8, 64) | onechar('_', 16, 64) | onechar('s', 24, 64) | onechar('i', 32, 64) | onechar('g', 40, 64) | onechar('n', 48, 64) | onechar('a', 56, 64): + switch (in[16]) { + case onechar('l', 0, 8): + return gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); } -inline gtok_t_vpr_constraints lex_node_t_vpr_constraints(const char *in, const std::function *report_error){ - unsigned int len = strlen(in); - switch(len){ - case 14: - switch(*((triehash_uu64*)&in[0])){ - case onechar('p', 0, 64) | onechar('a', 8, 64) | onechar('r', 16, 64) | onechar('t', 24, 64) | onechar('i', 32, 64) | onechar('t', 40, 64) | onechar('i', 48, 64) | onechar('o', 56, 64): - switch(*((triehash_uu32*)&in[8])){ - case onechar('n', 0, 32) | onechar('_', 8, 32) | onechar('l', 16, 32) | onechar('i', 24, 32): - switch(in[12]){ - case onechar('s', 0, 8): - switch(in[13]){ - case onechar('t', 0, 8): - return gtok_t_vpr_constraints::PARTITION_LIST; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - case 24: - switch(*((triehash_uu64*)&in[0])){ - case onechar('g', 0, 64) | onechar('l', 8, 64) | onechar('o', 16, 64) | onechar('b', 24, 64) | onechar('a', 32, 64) | onechar('l', 40, 64) | onechar('_', 48, 64) | onechar('r', 56, 64): - switch(*((triehash_uu64*)&in[8])){ - case onechar('o', 0, 64) | onechar('u', 8, 64) | onechar('t', 16, 64) | onechar('e', 24, 64) | onechar('_', 32, 64) | onechar('c', 40, 64) | onechar('o', 48, 64) | onechar('n', 56, 64): - switch(*((triehash_uu64*)&in[16])){ - case onechar('s', 0, 64) | onechar('t', 8, 64) | onechar('r', 16, 64) | onechar('a', 24, 64) | onechar('i', 32, 64) | onechar('n', 40, 64) | onechar('t', 48, 64) | onechar('s', 56, 64): - return gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); +inline gtok_t_vpr_constraints lex_node_t_vpr_constraints(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 14: + switch (*((triehash_uu64*)&in[0])) { + case onechar('p', 0, 64) | onechar('a', 8, 64) | onechar('r', 16, 64) | onechar('t', 24, 64) | onechar('i', 32, 64) | onechar('t', 40, 64) | onechar('i', 48, 64) | onechar('o', 56, 64): + switch (*((triehash_uu32*)&in[8])) { + case onechar('n', 0, 32) | onechar('_', 8, 32) | onechar('l', 16, 32) | onechar('i', 24, 32): + switch (in[12]) { + case onechar('s', 0, 8): + switch (in[13]) { + case onechar('t', 0, 8): + return gtok_t_vpr_constraints::PARTITION_LIST; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + case 24: + switch (*((triehash_uu64*)&in[0])) { + case onechar('g', 0, 64) | onechar('l', 8, 64) | onechar('o', 16, 64) | onechar('b', 24, 64) | onechar('a', 32, 64) | onechar('l', 40, 64) | onechar('_', 48, 64) | onechar('r', 56, 64): + switch (*((triehash_uu64*)&in[8])) { + case onechar('o', 0, 64) | onechar('u', 8, 64) | onechar('t', 16, 64) | onechar('e', 24, 64) | onechar('_', 32, 64) | onechar('c', 40, 64) | onechar('o', 48, 64) | onechar('n', 56, 64): + switch (*((triehash_uu64*)&in[16])) { + case onechar('s', 0, 64) | onechar('t', 8, 64) | onechar('r', 16, 64) | onechar('a', 24, 64) | onechar('i', 32, 64) | onechar('n', 40, 64) | onechar('t', 48, 64) | onechar('s', 56, 64): + return gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); } -inline atok_t_vpr_constraints lex_attr_t_vpr_constraints(const char *in, const std::function * report_error){ - unsigned int len = strlen(in); - switch(len){ - case 9: - switch(*((triehash_uu64*)&in[0])){ - case onechar('t', 0, 64) | onechar('o', 8, 64) | onechar('o', 16, 64) | onechar('l', 24, 64) | onechar('_', 32, 64) | onechar('n', 40, 64) | onechar('a', 48, 64) | onechar('m', 56, 64): - switch(in[8]){ - case onechar('e', 0, 8): - return atok_t_vpr_constraints::TOOL_NAME; - break; - default: break; - } - break; - default: break; - } - break; - default: break; - } - noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); +inline atok_t_vpr_constraints lex_attr_t_vpr_constraints(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 9: + switch (*((triehash_uu64*)&in[0])) { + case onechar('t', 0, 64) | onechar('o', 8, 64) | onechar('o', 16, 64) | onechar('l', 24, 64) | onechar('_', 32, 64) | onechar('n', 40, 64) | onechar('a', 48, 64) | onechar('m', 56, 64): + switch (in[8]) { + case onechar('e', 0, 8): + return atok_t_vpr_constraints::TOOL_NAME; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); } /** * Internal error function for xs:choice and xs:sequence validators. */ -[[noreturn]] inline void dfa_error(const char *wrong, const int *states, const char * const *lookup, int len, const std::function * report_error); +[[noreturn]] inline void dfa_error(const char* wrong, const int* states, const char* const* lookup, int len, const std::function* report_error); /** * Internal error function for attribute validators. */ template -[[noreturn]] inline void attr_error(std::bitset astate, const char * const *lookup, const std::function * report_error); - +[[noreturn]] inline void attr_error(std::bitset astate, const char* const* lookup, const std::function* report_error); /* Internal loading functions, which validate and load a PugiXML DOM tree into memory. */ -inline int load_int(const char *in, const std::function * report_error){ - int out; - out = std::strtol(in, NULL, 10); - if(errno != 0) - noreturn_report(report_error, ("Invalid value `" + std::string(in) + "` when loading into a int.").c_str()); - return out; +inline int load_int(const char* in, const std::function* report_error) { + int out; + out = std::strtol(in, NULL, 10); + if (errno != 0) + noreturn_report(report_error, ("Invalid value `" + std::string(in) + "` when loading into a int.").c_str()); + return out; } -inline void load_add_region_required_attributes(const pugi::xml_node &root, int * x_high, int * x_low, int * y_high, int * y_low, const std::function * report_error){ - std::bitset<5> astate = 0; - for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ - atok_t_add_region in = lex_attr_t_add_region(attr.name(), report_error); - if(astate[(int)in] == 0) astate[(int)in] = 1; - else noreturn_report(report_error, ("Duplicate attribute " + std::string(attr.name()) + " in .").c_str()); - switch(in){ - case atok_t_add_region::SUBTILE: - /* Attribute subtile set after element init */ - break; - case atok_t_add_region::X_HIGH: - *x_high = load_int(attr.value(), report_error); - break; - case atok_t_add_region::X_LOW: - *x_low = load_int(attr.value(), report_error); - break; - case atok_t_add_region::Y_HIGH: - *y_high = load_int(attr.value(), report_error); - break; - case atok_t_add_region::Y_LOW: - *y_low = load_int(attr.value(), report_error); - break; - default: break; /* Not possible. */ - } - } - std::bitset<5> test_astate = astate | std::bitset<5>(0b00001); - if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_add_region, report_error); +inline void load_add_region_required_attributes(const pugi::xml_node& root, int* x_high, int* x_low, int* y_high, int* y_low, const std::function* report_error) { + std::bitset<5> astate = 0; + for (pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()) { + atok_t_add_region in = lex_attr_t_add_region(attr.name(), report_error); + if (astate[(int)in] == 0) + astate[(int)in] = 1; + else + noreturn_report(report_error, ("Duplicate attribute " + std::string(attr.name()) + " in .").c_str()); + switch (in) { + case atok_t_add_region::SUBTILE: + /* Attribute subtile set after element init */ + break; + case atok_t_add_region::X_HIGH: + *x_high = load_int(attr.value(), report_error); + break; + case atok_t_add_region::X_LOW: + *x_low = load_int(attr.value(), report_error); + break; + case atok_t_add_region::Y_HIGH: + *y_high = load_int(attr.value(), report_error); + break; + case atok_t_add_region::Y_LOW: + *y_low = load_int(attr.value(), report_error); + break; + default: + break; /* Not possible. */ + } + } + std::bitset<5> test_astate = astate | std::bitset<5>(0b00001); + if (!test_astate.all()) attr_error(test_astate, atok_lookup_t_add_region, report_error); } template -inline void load_add_atom(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug){ - (void)root; - (void)out; - (void)context; - (void)report_error; - // Update current file offset in case an error is encountered. - *offset_debug = root.offset_debug(); - - for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ - atok_t_add_atom in = lex_attr_t_add_atom(attr.name(), report_error); - switch(in){ - case atok_t_add_atom::NAME_PATTERN: - out.set_add_atom_name_pattern(attr.value(), context); - break; - default: break; /* Not possible. */ - } - } - - if(root.first_child().type() == pugi::node_element) - noreturn_report(report_error, "Unexpected child element in ."); - +inline void load_add_atom(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + for (pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()) { + atok_t_add_atom in = lex_attr_t_add_atom(attr.name(), report_error); + switch (in) { + case atok_t_add_atom::NAME_PATTERN: + out.set_add_atom_name_pattern(attr.value(), context); + break; + default: + break; /* Not possible. */ + } + } + + if (root.first_child().type() == pugi::node_element) + noreturn_report(report_error, "Unexpected child element in ."); } template -inline void load_add_region(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug){ - (void)root; - (void)out; - (void)context; - (void)report_error; - // Update current file offset in case an error is encountered. - *offset_debug = root.offset_debug(); - - for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ - atok_t_add_region in = lex_attr_t_add_region(attr.name(), report_error); - switch(in){ - case atok_t_add_region::SUBTILE: - out.set_add_region_subtile(load_int(attr.value(), report_error), context); - break; - case atok_t_add_region::X_HIGH: - /* Attribute x_high is already set */ - break; - case atok_t_add_region::X_LOW: - /* Attribute x_low is already set */ - break; - case atok_t_add_region::Y_HIGH: - /* Attribute y_high is already set */ - break; - case atok_t_add_region::Y_LOW: - /* Attribute y_low is already set */ - break; - default: break; /* Not possible. */ - } - } - - if(root.first_child().type() == pugi::node_element) - noreturn_report(report_error, "Unexpected child element in ."); - +inline void load_add_region(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + for (pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()) { + atok_t_add_region in = lex_attr_t_add_region(attr.name(), report_error); + switch (in) { + case atok_t_add_region::SUBTILE: + out.set_add_region_subtile(load_int(attr.value(), report_error), context); + break; + case atok_t_add_region::X_HIGH: + /* Attribute x_high is already set */ + break; + case atok_t_add_region::X_LOW: + /* Attribute x_low is already set */ + break; + case atok_t_add_region::Y_HIGH: + /* Attribute y_high is already set */ + break; + case atok_t_add_region::Y_LOW: + /* Attribute y_low is already set */ + break; + default: + break; /* Not possible. */ + } + } + + if (root.first_child().type() == pugi::node_element) + noreturn_report(report_error, "Unexpected child element in ."); } constexpr int NUM_T_PARTITION_STATES = 2; constexpr const int NUM_T_PARTITION_INPUTS = 2; constexpr int gstate_t_partition[NUM_T_PARTITION_STATES][NUM_T_PARTITION_INPUTS] = { - {0, 0}, - {0, 0}, + {0, 0}, + {0, 0}, }; template -inline void load_partition(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug){ - (void)root; - (void)out; - (void)context; - (void)report_error; - // Update current file offset in case an error is encountered. - *offset_debug = root.offset_debug(); - - for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ - atok_t_partition in = lex_attr_t_partition(attr.name(), report_error); - switch(in){ - case atok_t_partition::NAME: - out.set_partition_name(attr.value(), context); - break; - default: break; /* Not possible. */ - } - } - - // Preallocate arrays by counting child nodes (if any) - size_t add_atom_count = 0; - size_t add_region_count = 0; - { - int next, state=1; - for(pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { - *offset_debug = node.offset_debug(); - gtok_t_partition in = lex_node_t_partition(node.name(), report_error); - next = gstate_t_partition[state][(int)in]; - if(next == -1) - dfa_error(gtok_lookup_t_partition[(int)in], gstate_t_partition[state], gtok_lookup_t_partition, 2, report_error); - state = next; - switch(in) { - case gtok_t_partition::ADD_ATOM: - add_atom_count += 1; - break; - case gtok_t_partition::ADD_REGION: - add_region_count += 1; - break; - default: break; /* Not possible. */ - } - } - - out.preallocate_partition_add_atom(context, add_atom_count); - out.preallocate_partition_add_region(context, add_region_count); - } - int next, state=1; - for(pugi::xml_node node = root.first_child(); node; node = node.next_sibling()){ - *offset_debug = node.offset_debug(); - gtok_t_partition in = lex_node_t_partition(node.name(), report_error); - next = gstate_t_partition[state][(int)in]; - if(next == -1) - dfa_error(gtok_lookup_t_partition[(int)in], gstate_t_partition[state], gtok_lookup_t_partition, 2, report_error); - state = next; - switch(in){ - case gtok_t_partition::ADD_ATOM: - { - auto child_context = out.add_partition_add_atom(context); - load_add_atom(node, out, child_context, report_error, offset_debug); - out.finish_partition_add_atom(child_context); - } - break; - case gtok_t_partition::ADD_REGION: - { - int add_region_x_high; - memset(&add_region_x_high, 0, sizeof(add_region_x_high)); - int add_region_x_low; - memset(&add_region_x_low, 0, sizeof(add_region_x_low)); - int add_region_y_high; - memset(&add_region_y_high, 0, sizeof(add_region_y_high)); - int add_region_y_low; - memset(&add_region_y_low, 0, sizeof(add_region_y_low)); - load_add_region_required_attributes(node, &add_region_x_high, &add_region_x_low, &add_region_y_high, &add_region_y_low, report_error); - auto child_context = out.add_partition_add_region(context, add_region_x_high, add_region_x_low, add_region_y_high, add_region_y_low); - load_add_region(node, out, child_context, report_error, offset_debug); - out.finish_partition_add_region(child_context); - } - break; - default: break; /* Not possible. */ - } - } - if(state != 0) dfa_error("end of input", gstate_t_partition[state], gtok_lookup_t_partition, 2, report_error); - +inline void load_partition(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + for (pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()) { + atok_t_partition in = lex_attr_t_partition(attr.name(), report_error); + switch (in) { + case atok_t_partition::NAME: + out.set_partition_name(attr.value(), context); + break; + default: + break; /* Not possible. */ + } + } + + // Preallocate arrays by counting child nodes (if any) + size_t add_atom_count = 0; + size_t add_region_count = 0; + { + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_partition in = lex_node_t_partition(node.name(), report_error); + next = gstate_t_partition[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_partition[(int)in], gstate_t_partition[state], gtok_lookup_t_partition, 2, report_error); + state = next; + switch (in) { + case gtok_t_partition::ADD_ATOM: + add_atom_count += 1; + break; + case gtok_t_partition::ADD_REGION: + add_region_count += 1; + break; + default: + break; /* Not possible. */ + } + } + + out.preallocate_partition_add_atom(context, add_atom_count); + out.preallocate_partition_add_region(context, add_region_count); + } + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_partition in = lex_node_t_partition(node.name(), report_error); + next = gstate_t_partition[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_partition[(int)in], gstate_t_partition[state], gtok_lookup_t_partition, 2, report_error); + state = next; + switch (in) { + case gtok_t_partition::ADD_ATOM: { + auto child_context = out.add_partition_add_atom(context); + load_add_atom(node, out, child_context, report_error, offset_debug); + out.finish_partition_add_atom(child_context); + } break; + case gtok_t_partition::ADD_REGION: { + int add_region_x_high; + memset(&add_region_x_high, 0, sizeof(add_region_x_high)); + int add_region_x_low; + memset(&add_region_x_low, 0, sizeof(add_region_x_low)); + int add_region_y_high; + memset(&add_region_y_high, 0, sizeof(add_region_y_high)); + int add_region_y_low; + memset(&add_region_y_low, 0, sizeof(add_region_y_low)); + load_add_region_required_attributes(node, &add_region_x_high, &add_region_x_low, &add_region_y_high, &add_region_y_low, report_error); + auto child_context = out.add_partition_add_region(context, add_region_x_high, add_region_x_low, add_region_y_high, add_region_y_low); + load_add_region(node, out, child_context, report_error, offset_debug); + out.finish_partition_add_region(child_context); + } break; + default: + break; /* Not possible. */ + } + } + if (state != 0) dfa_error("end of input", gstate_t_partition[state], gtok_lookup_t_partition, 2, report_error); } constexpr int NUM_T_PARTITION_LIST_STATES = 2; constexpr const int NUM_T_PARTITION_LIST_INPUTS = 1; constexpr int gstate_t_partition_list[NUM_T_PARTITION_LIST_STATES][NUM_T_PARTITION_LIST_INPUTS] = { - {0}, - {0}, + {0}, + {0}, }; template -inline void load_partition_list(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug){ - (void)root; - (void)out; - (void)context; - (void)report_error; - // Update current file offset in case an error is encountered. - *offset_debug = root.offset_debug(); - - if(root.first_attribute()) - noreturn_report(report_error, "Unexpected attribute in ."); - - // Preallocate arrays by counting child nodes (if any) - size_t partition_count = 0; - { - int next, state=1; - for(pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { - *offset_debug = node.offset_debug(); - gtok_t_partition_list in = lex_node_t_partition_list(node.name(), report_error); - next = gstate_t_partition_list[state][(int)in]; - if(next == -1) - dfa_error(gtok_lookup_t_partition_list[(int)in], gstate_t_partition_list[state], gtok_lookup_t_partition_list, 1, report_error); - state = next; - switch(in) { - case gtok_t_partition_list::PARTITION: - partition_count += 1; - break; - default: break; /* Not possible. */ - } - } - - out.preallocate_partition_list_partition(context, partition_count); - } - int next, state=1; - for(pugi::xml_node node = root.first_child(); node; node = node.next_sibling()){ - *offset_debug = node.offset_debug(); - gtok_t_partition_list in = lex_node_t_partition_list(node.name(), report_error); - next = gstate_t_partition_list[state][(int)in]; - if(next == -1) - dfa_error(gtok_lookup_t_partition_list[(int)in], gstate_t_partition_list[state], gtok_lookup_t_partition_list, 1, report_error); - state = next; - switch(in){ - case gtok_t_partition_list::PARTITION: - { - auto child_context = out.add_partition_list_partition(context); - load_partition(node, out, child_context, report_error, offset_debug); - out.finish_partition_list_partition(child_context); - } - break; - default: break; /* Not possible. */ - } - } - if(state != 0) dfa_error("end of input", gstate_t_partition_list[state], gtok_lookup_t_partition_list, 1, report_error); - +inline void load_partition_list(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + if (root.first_attribute()) + noreturn_report(report_error, "Unexpected attribute in ."); + + // Preallocate arrays by counting child nodes (if any) + size_t partition_count = 0; + { + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_partition_list in = lex_node_t_partition_list(node.name(), report_error); + next = gstate_t_partition_list[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_partition_list[(int)in], gstate_t_partition_list[state], gtok_lookup_t_partition_list, 1, report_error); + state = next; + switch (in) { + case gtok_t_partition_list::PARTITION: + partition_count += 1; + break; + default: + break; /* Not possible. */ + } + } + + out.preallocate_partition_list_partition(context, partition_count); + } + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_partition_list in = lex_node_t_partition_list(node.name(), report_error); + next = gstate_t_partition_list[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_partition_list[(int)in], gstate_t_partition_list[state], gtok_lookup_t_partition_list, 1, report_error); + state = next; + switch (in) { + case gtok_t_partition_list::PARTITION: { + auto child_context = out.add_partition_list_partition(context); + load_partition(node, out, child_context, report_error, offset_debug); + out.finish_partition_list_partition(child_context); + } break; + default: + break; /* Not possible. */ + } + } + if (state != 0) dfa_error("end of input", gstate_t_partition_list[state], gtok_lookup_t_partition_list, 1, report_error); } template -inline void load_set_global_signal(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug){ - (void)root; - (void)out; - (void)context; - (void)report_error; - // Update current file offset in case an error is encountered. - *offset_debug = root.offset_debug(); - - for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ - atok_t_set_global_signal in = lex_attr_t_set_global_signal(attr.name(), report_error); - switch(in){ - case atok_t_set_global_signal::NAME: - out.set_set_global_signal_name(attr.value(), context); - break; - case atok_t_set_global_signal::ROUTE_MODEL: - out.set_set_global_signal_route_model(attr.value(), context); - break; - case atok_t_set_global_signal::TYPE: - out.set_set_global_signal_type(attr.value(), context); - break; - default: break; /* Not possible. */ - } - } - - if(root.first_child().type() == pugi::node_element) - noreturn_report(report_error, "Unexpected child element in ."); - +inline void load_set_global_signal(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + for (pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()) { + atok_t_set_global_signal in = lex_attr_t_set_global_signal(attr.name(), report_error); + switch (in) { + case atok_t_set_global_signal::NAME: + out.set_set_global_signal_name(attr.value(), context); + break; + case atok_t_set_global_signal::ROUTE_MODEL: + out.set_set_global_signal_route_model(attr.value(), context); + break; + case atok_t_set_global_signal::TYPE: + out.set_set_global_signal_type(attr.value(), context); + break; + default: + break; /* Not possible. */ + } + } + + if (root.first_child().type() == pugi::node_element) + noreturn_report(report_error, "Unexpected child element in ."); } constexpr int NUM_T_GLOBAL_ROUTE_CONSTRAINTS_STATES = 2; constexpr const int NUM_T_GLOBAL_ROUTE_CONSTRAINTS_INPUTS = 1; constexpr int gstate_t_global_route_constraints[NUM_T_GLOBAL_ROUTE_CONSTRAINTS_STATES][NUM_T_GLOBAL_ROUTE_CONSTRAINTS_INPUTS] = { - {0}, - {0}, + {0}, + {0}, }; template -inline void load_global_route_constraints(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug){ - (void)root; - (void)out; - (void)context; - (void)report_error; - // Update current file offset in case an error is encountered. - *offset_debug = root.offset_debug(); - - if(root.first_attribute()) - noreturn_report(report_error, "Unexpected attribute in ."); - - // Preallocate arrays by counting child nodes (if any) - size_t set_global_signal_count = 0; - { - int next, state=1; - for(pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { - *offset_debug = node.offset_debug(); - gtok_t_global_route_constraints in = lex_node_t_global_route_constraints(node.name(), report_error); - next = gstate_t_global_route_constraints[state][(int)in]; - if(next == -1) - dfa_error(gtok_lookup_t_global_route_constraints[(int)in], gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); - state = next; - switch(in) { - case gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL: - set_global_signal_count += 1; - break; - default: break; /* Not possible. */ - } - } - - out.preallocate_global_route_constraints_set_global_signal(context, set_global_signal_count); - } - int next, state=1; - for(pugi::xml_node node = root.first_child(); node; node = node.next_sibling()){ - *offset_debug = node.offset_debug(); - gtok_t_global_route_constraints in = lex_node_t_global_route_constraints(node.name(), report_error); - next = gstate_t_global_route_constraints[state][(int)in]; - if(next == -1) - dfa_error(gtok_lookup_t_global_route_constraints[(int)in], gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); - state = next; - switch(in){ - case gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL: - { - auto child_context = out.add_global_route_constraints_set_global_signal(context); - load_set_global_signal(node, out, child_context, report_error, offset_debug); - out.finish_global_route_constraints_set_global_signal(child_context); - } - break; - default: break; /* Not possible. */ - } - } - if(state != 0) dfa_error("end of input", gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); - +inline void load_global_route_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + if (root.first_attribute()) + noreturn_report(report_error, "Unexpected attribute in ."); + + // Preallocate arrays by counting child nodes (if any) + size_t set_global_signal_count = 0; + { + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_global_route_constraints in = lex_node_t_global_route_constraints(node.name(), report_error); + next = gstate_t_global_route_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_global_route_constraints[(int)in], gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); + state = next; + switch (in) { + case gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL: + set_global_signal_count += 1; + break; + default: + break; /* Not possible. */ + } + } + + out.preallocate_global_route_constraints_set_global_signal(context, set_global_signal_count); + } + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_global_route_constraints in = lex_node_t_global_route_constraints(node.name(), report_error); + next = gstate_t_global_route_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_global_route_constraints[(int)in], gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); + state = next; + switch (in) { + case gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL: { + auto child_context = out.add_global_route_constraints_set_global_signal(context); + load_set_global_signal(node, out, child_context, report_error, offset_debug); + out.finish_global_route_constraints_set_global_signal(child_context); + } break; + default: + break; /* Not possible. */ + } + } + if (state != 0) dfa_error("end of input", gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); } constexpr int NUM_T_VPR_CONSTRAINTS_STATES = 1; constexpr const int NUM_T_VPR_CONSTRAINTS_INPUTS = 2; constexpr int gstate_t_vpr_constraints[NUM_T_VPR_CONSTRAINTS_STATES][NUM_T_VPR_CONSTRAINTS_INPUTS] = { - {0, 0}, + {0, 0}, }; template -inline void load_vpr_constraints(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug){ - (void)root; - (void)out; - (void)context; - (void)report_error; - // Update current file offset in case an error is encountered. - *offset_debug = root.offset_debug(); - - for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ - atok_t_vpr_constraints in = lex_attr_t_vpr_constraints(attr.name(), report_error); - switch(in){ - case atok_t_vpr_constraints::TOOL_NAME: - out.set_vpr_constraints_tool_name(attr.value(), context); - break; - default: break; /* Not possible. */ - } - } - - // Preallocate arrays by counting child nodes (if any) - size_t partition_list_count = 0; - size_t global_route_constraints_count = 0; - { - int next, state=0; - for(pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { - *offset_debug = node.offset_debug(); - gtok_t_vpr_constraints in = lex_node_t_vpr_constraints(node.name(), report_error); - next = gstate_t_vpr_constraints[state][(int)in]; - if(next == -1) - dfa_error(gtok_lookup_t_vpr_constraints[(int)in], gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); - state = next; - switch(in) { - case gtok_t_vpr_constraints::PARTITION_LIST: - partition_list_count += 1; - break; - case gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS: - global_route_constraints_count += 1; - break; - default: break; /* Not possible. */ - } - } - - out.preallocate_vpr_constraints_partition_list(context, partition_list_count); - out.preallocate_vpr_constraints_global_route_constraints(context, global_route_constraints_count); - } - int next, state=0; - for(pugi::xml_node node = root.first_child(); node; node = node.next_sibling()){ - *offset_debug = node.offset_debug(); - gtok_t_vpr_constraints in = lex_node_t_vpr_constraints(node.name(), report_error); - next = gstate_t_vpr_constraints[state][(int)in]; - if(next == -1) - dfa_error(gtok_lookup_t_vpr_constraints[(int)in], gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); - state = next; - switch(in){ - case gtok_t_vpr_constraints::PARTITION_LIST: - { - auto child_context = out.add_vpr_constraints_partition_list(context); - load_partition_list(node, out, child_context, report_error, offset_debug); - out.finish_vpr_constraints_partition_list(child_context); - } - break; - case gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS: - { - auto child_context = out.add_vpr_constraints_global_route_constraints(context); - load_global_route_constraints(node, out, child_context, report_error, offset_debug); - out.finish_vpr_constraints_global_route_constraints(child_context); - } - break; - default: break; /* Not possible. */ - } - } - if(state != 0) dfa_error("end of input", gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); - +inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + for (pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()) { + atok_t_vpr_constraints in = lex_attr_t_vpr_constraints(attr.name(), report_error); + switch (in) { + case atok_t_vpr_constraints::TOOL_NAME: + out.set_vpr_constraints_tool_name(attr.value(), context); + break; + default: + break; /* Not possible. */ + } + } + + // Preallocate arrays by counting child nodes (if any) + size_t partition_list_count = 0; + size_t global_route_constraints_count = 0; + { + int next, state = 0; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_vpr_constraints in = lex_node_t_vpr_constraints(node.name(), report_error); + next = gstate_t_vpr_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_vpr_constraints[(int)in], gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); + state = next; + switch (in) { + case gtok_t_vpr_constraints::PARTITION_LIST: + partition_list_count += 1; + break; + case gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS: + global_route_constraints_count += 1; + break; + default: + break; /* Not possible. */ + } + } + + out.preallocate_vpr_constraints_partition_list(context, partition_list_count); + out.preallocate_vpr_constraints_global_route_constraints(context, global_route_constraints_count); + } + int next, state = 0; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_vpr_constraints in = lex_node_t_vpr_constraints(node.name(), report_error); + next = gstate_t_vpr_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_vpr_constraints[(int)in], gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); + state = next; + switch (in) { + case gtok_t_vpr_constraints::PARTITION_LIST: { + auto child_context = out.add_vpr_constraints_partition_list(context); + load_partition_list(node, out, child_context, report_error, offset_debug); + out.finish_vpr_constraints_partition_list(child_context); + } break; + case gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS: { + auto child_context = out.add_vpr_constraints_global_route_constraints(context); + load_global_route_constraints(node, out, child_context, report_error, offset_debug); + out.finish_vpr_constraints_global_route_constraints(child_context); + } break; + default: + break; /* Not possible. */ + } + } + if (state != 0) dfa_error("end of input", gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); } - /* Internal writing functions, which uxsdcxx uses to write out a class. */ template -inline void write_partition(T &in, std::ostream &os, Context &context){ - (void)in; - (void)os; - (void)context; - { - for(size_t i=0, n=in.num_partition_add_atom(context); i\n"; - } - } - { - for(size_t i=0, n=in.num_partition_add_region(context); i\n"; - } - } +inline void write_partition(T& in, std::ostream& os, Context& context) { + (void)in; + (void)os; + (void)context; + { + for (size_t i = 0, n = in.num_partition_add_atom(context); i < n; i++) { + auto child_context = in.get_partition_add_atom(i, context); + os << "\n"; + } + } + { + for (size_t i = 0, n = in.num_partition_add_region(context); i < n; i++) { + auto child_context = in.get_partition_add_region(i, context); + os << "\n"; + } + } } template -inline void write_partition_list(T &in, std::ostream &os, Context &context){ - (void)in; - (void)os; - (void)context; - { - for(size_t i=0, n=in.num_partition_list_partition(context); i"; - write_partition(in, os, child_context); - os << "\n"; - } - } +inline void write_partition_list(T& in, std::ostream& os, Context& context) { + (void)in; + (void)os; + (void)context; + { + for (size_t i = 0, n = in.num_partition_list_partition(context); i < n; i++) { + auto child_context = in.get_partition_list_partition(i, context); + os << ""; + write_partition(in, os, child_context); + os << "\n"; + } + } } template -inline void write_global_route_constraints(T &in, std::ostream &os, Context &context){ - (void)in; - (void)os; - (void)context; - { - for(size_t i=0, n=in.num_global_route_constraints_set_global_signal(context); i\n"; - } - } +inline void write_global_route_constraints(T& in, std::ostream& os, Context& context) { + (void)in; + (void)os; + (void)context; + { + for (size_t i = 0, n = in.num_global_route_constraints_set_global_signal(context); i < n; i++) { + auto child_context = in.get_global_route_constraints_set_global_signal(i, context); + os << "\n"; + } + } } template -inline void write_vpr_constraints(T &in, std::ostream &os, Context &context){ - (void)in; - (void)os; - (void)context; - { - for(size_t i=0, n=in.num_vpr_constraints_partition_list(context); i\n"; - write_partition_list(in, os, child_context); - os << "\n"; - } - } - { - for(size_t i=0, n=in.num_vpr_constraints_global_route_constraints(context); i\n"; - write_global_route_constraints(in, os, child_context); - os << "\n"; - } - } +inline void write_vpr_constraints(T& in, std::ostream& os, Context& context) { + (void)in; + (void)os; + (void)context; + { + for (size_t i = 0, n = in.num_vpr_constraints_partition_list(context); i < n; i++) { + auto child_context = in.get_vpr_constraints_partition_list(i, context); + os << "\n"; + write_partition_list(in, os, child_context); + os << "\n"; + } + } + { + for (size_t i = 0, n = in.num_vpr_constraints_global_route_constraints(context); i < n; i++) { + auto child_context = in.get_vpr_constraints_global_route_constraints(i, context); + os << "\n"; + write_global_route_constraints(in, os, child_context); + os << "\n"; + } + } } -inline void dfa_error(const char *wrong, const int *states, const char * const *lookup, int len, const std::function * report_error){ - std::vector expected; - for(int i=0; i* report_error) { + std::vector expected; + for (int i = 0; i < len; i++) { + if (states[i] != -1) expected.push_back(lookup[i]); + } - std::string expected_or = expected[0]; - for(unsigned int i=1; i -inline void attr_error(std::bitset astate, const char * const *lookup, const std::function * report_error){ - std::vector missing; - for(unsigned int i=0; i astate, const char* const* lookup, const std::function* report_error) { + std::vector missing; + for (unsigned int i = 0; i < N; i++) { + if (astate[i] == 0) missing.push_back(lookup[i]); + } - std::string missing_and = missing[0]; - for(unsigned int i=1; i f(fopen(filename, "rb"), fclose); - - if (!f) { - throw std::runtime_error(std::string("Failed to open file") + filename); - } - - int current_line = 1; - std::ptrdiff_t offset = 0; - std::ptrdiff_t last_line_offset = 0; - std::ptrdiff_t current_line_offset = 0; - - char buffer[1024]; - std::size_t size; - - while ((size = fread(buffer, 1, sizeof(buffer), f.get())) > 0) { - for (std::size_t i = 0; i < size; ++i) { - if (buffer[i] == '\n') { - current_line += 1; - last_line_offset = current_line_offset; - current_line_offset = offset + i; - - if(target_offset < current_line_offset) { - if(target_offset < last_line_offset) { - throw std::runtime_error("Assertion violation"); - } - - *line = current_line - 1; - *col = target_offset - last_line_offset; - return; - } - } - } - - offset += size; - } - - *line = current_line; - *col = target_offset - current_line_offset; +inline void get_line_number(const char* filename, std::ptrdiff_t target_offset, int* line, int* col) { + std::unique_ptr f(fopen(filename, "rb"), fclose); + + if (!f) { + throw std::runtime_error(std::string("Failed to open file") + filename); + } + + int current_line = 1; + std::ptrdiff_t offset = 0; + std::ptrdiff_t last_line_offset = 0; + std::ptrdiff_t current_line_offset = 0; + + char buffer[1024]; + std::size_t size; + + while ((size = fread(buffer, 1, sizeof(buffer), f.get())) > 0) { + for (std::size_t i = 0; i < size; ++i) { + if (buffer[i] == '\n') { + current_line += 1; + last_line_offset = current_line_offset; + current_line_offset = offset + i; + + if (target_offset < current_line_offset) { + if (target_offset < last_line_offset) { + throw std::runtime_error("Assertion violation"); + } + + *line = current_line - 1; + *col = target_offset - last_line_offset; + return; + } + } + } + + offset += size; + } + + *line = current_line; + *col = target_offset - current_line_offset; } - } /* namespace uxsd */ diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h index 39f24f91d5a..280bf58c793 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h @@ -11,7 +11,6 @@ #include - /* All uxsdcxx functions and structs live in this namespace. */ #include @@ -21,140 +20,140 @@ namespace uxsd { /* Base class for the schema. */ struct DefaultVprConstraintsContextTypes { -using AddAtomReadContext = void *; - using AddRegionReadContext = void *; - using PartitionReadContext = void *; - using PartitionListReadContext = void *; - using SetGlobalSignalReadContext = void *; - using GlobalRouteConstraintsReadContext = void *; - using VprConstraintsReadContext = void *; -using AddAtomWriteContext = void *; - using AddRegionWriteContext = void *; - using PartitionWriteContext = void *; - using PartitionListWriteContext = void *; - using SetGlobalSignalWriteContext = void *; - using GlobalRouteConstraintsWriteContext = void *; - using VprConstraintsWriteContext = void *; + using AddAtomReadContext = void*; + using AddRegionReadContext = void*; + using PartitionReadContext = void*; + using PartitionListReadContext = void*; + using SetGlobalSignalReadContext = void*; + using GlobalRouteConstraintsReadContext = void*; + using VprConstraintsReadContext = void*; + using AddAtomWriteContext = void*; + using AddRegionWriteContext = void*; + using PartitionWriteContext = void*; + using PartitionListWriteContext = void*; + using SetGlobalSignalWriteContext = void*; + using GlobalRouteConstraintsWriteContext = void*; + using VprConstraintsWriteContext = void*; }; -template +template class VprConstraintsBase { -public: - virtual ~VprConstraintsBase() {} - virtual void start_load(const std::function *report_error) = 0; - virtual void finish_load() = 0; - virtual void start_write() = 0; - virtual void finish_write() = 0; - virtual void error_encountered(const char * file, int line, const char *message) = 0; - /** Generated for complex type "add_atom": - * - * - * - */ - virtual inline const char * get_add_atom_name_pattern(typename ContextTypes::AddAtomReadContext &ctx) = 0; - virtual inline void set_add_atom_name_pattern(const char * name_pattern, typename ContextTypes::AddAtomWriteContext &ctx) = 0; + public: + virtual ~VprConstraintsBase() {} + virtual void start_load(const std::function* report_error) = 0; + virtual void finish_load() = 0; + virtual void start_write() = 0; + virtual void finish_write() = 0; + virtual void error_encountered(const char* file, int line, const char* message) = 0; + /** Generated for complex type "add_atom": + * + * + * + */ + virtual inline const char* get_add_atom_name_pattern(typename ContextTypes::AddAtomReadContext& ctx) = 0; + virtual inline void set_add_atom_name_pattern(const char* name_pattern, typename ContextTypes::AddAtomWriteContext& ctx) = 0; - /** Generated for complex type "add_region": - * - * - * - * - * - * - * - */ - virtual inline int get_add_region_subtile(typename ContextTypes::AddRegionReadContext &ctx) = 0; - virtual inline void set_add_region_subtile(int subtile, typename ContextTypes::AddRegionWriteContext &ctx) = 0; - virtual inline int get_add_region_x_high(typename ContextTypes::AddRegionReadContext &ctx) = 0; - virtual inline int get_add_region_x_low(typename ContextTypes::AddRegionReadContext &ctx) = 0; - virtual inline int get_add_region_y_high(typename ContextTypes::AddRegionReadContext &ctx) = 0; - virtual inline int get_add_region_y_low(typename ContextTypes::AddRegionReadContext &ctx) = 0; + /** Generated for complex type "add_region": + * + * + * + * + * + * + * + */ + virtual inline int get_add_region_subtile(typename ContextTypes::AddRegionReadContext& ctx) = 0; + virtual inline void set_add_region_subtile(int subtile, typename ContextTypes::AddRegionWriteContext& ctx) = 0; + virtual inline int get_add_region_x_high(typename ContextTypes::AddRegionReadContext& ctx) = 0; + virtual inline int get_add_region_x_low(typename ContextTypes::AddRegionReadContext& ctx) = 0; + virtual inline int get_add_region_y_high(typename ContextTypes::AddRegionReadContext& ctx) = 0; + virtual inline int get_add_region_y_low(typename ContextTypes::AddRegionReadContext& ctx) = 0; - /** Generated for complex type "partition": - * - * - * - * - * - * - * - * - * - */ - virtual inline const char * get_partition_name(typename ContextTypes::PartitionReadContext &ctx) = 0; - virtual inline void set_partition_name(const char * name, typename ContextTypes::PartitionWriteContext &ctx) = 0; - virtual inline void preallocate_partition_add_atom(typename ContextTypes::PartitionWriteContext &ctx, size_t size) = 0; - virtual inline typename ContextTypes::AddAtomWriteContext add_partition_add_atom(typename ContextTypes::PartitionWriteContext &ctx) = 0; - virtual inline void finish_partition_add_atom(typename ContextTypes::AddAtomWriteContext &ctx) = 0; - virtual inline size_t num_partition_add_atom(typename ContextTypes::PartitionReadContext &ctx) = 0; - virtual inline typename ContextTypes::AddAtomReadContext get_partition_add_atom(int n, typename ContextTypes::PartitionReadContext &ctx) = 0; - virtual inline void preallocate_partition_add_region(typename ContextTypes::PartitionWriteContext &ctx, size_t size) = 0; - virtual inline typename ContextTypes::AddRegionWriteContext add_partition_add_region(typename ContextTypes::PartitionWriteContext &ctx, int x_high, int x_low, int y_high, int y_low) = 0; - virtual inline void finish_partition_add_region(typename ContextTypes::AddRegionWriteContext &ctx) = 0; - virtual inline size_t num_partition_add_region(typename ContextTypes::PartitionReadContext &ctx) = 0; - virtual inline typename ContextTypes::AddRegionReadContext get_partition_add_region(int n, typename ContextTypes::PartitionReadContext &ctx) = 0; + /** Generated for complex type "partition": + * + * + * + * + * + * + * + * + * + */ + virtual inline const char* get_partition_name(typename ContextTypes::PartitionReadContext& ctx) = 0; + virtual inline void set_partition_name(const char* name, typename ContextTypes::PartitionWriteContext& ctx) = 0; + virtual inline void preallocate_partition_add_atom(typename ContextTypes::PartitionWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::AddAtomWriteContext add_partition_add_atom(typename ContextTypes::PartitionWriteContext& ctx) = 0; + virtual inline void finish_partition_add_atom(typename ContextTypes::AddAtomWriteContext& ctx) = 0; + virtual inline size_t num_partition_add_atom(typename ContextTypes::PartitionReadContext& ctx) = 0; + virtual inline typename ContextTypes::AddAtomReadContext get_partition_add_atom(int n, typename ContextTypes::PartitionReadContext& ctx) = 0; + virtual inline void preallocate_partition_add_region(typename ContextTypes::PartitionWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::AddRegionWriteContext add_partition_add_region(typename ContextTypes::PartitionWriteContext& ctx, int x_high, int x_low, int y_high, int y_low) = 0; + virtual inline void finish_partition_add_region(typename ContextTypes::AddRegionWriteContext& ctx) = 0; + virtual inline size_t num_partition_add_region(typename ContextTypes::PartitionReadContext& ctx) = 0; + virtual inline typename ContextTypes::AddRegionReadContext get_partition_add_region(int n, typename ContextTypes::PartitionReadContext& ctx) = 0; - /** Generated for complex type "partition_list": - * - * - * - * - * - */ - virtual inline void preallocate_partition_list_partition(typename ContextTypes::PartitionListWriteContext &ctx, size_t size) = 0; - virtual inline typename ContextTypes::PartitionWriteContext add_partition_list_partition(typename ContextTypes::PartitionListWriteContext &ctx) = 0; - virtual inline void finish_partition_list_partition(typename ContextTypes::PartitionWriteContext &ctx) = 0; - virtual inline size_t num_partition_list_partition(typename ContextTypes::PartitionListReadContext &ctx) = 0; - virtual inline typename ContextTypes::PartitionReadContext get_partition_list_partition(int n, typename ContextTypes::PartitionListReadContext &ctx) = 0; + /** Generated for complex type "partition_list": + * + * + * + * + * + */ + virtual inline void preallocate_partition_list_partition(typename ContextTypes::PartitionListWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::PartitionWriteContext add_partition_list_partition(typename ContextTypes::PartitionListWriteContext& ctx) = 0; + virtual inline void finish_partition_list_partition(typename ContextTypes::PartitionWriteContext& ctx) = 0; + virtual inline size_t num_partition_list_partition(typename ContextTypes::PartitionListReadContext& ctx) = 0; + virtual inline typename ContextTypes::PartitionReadContext get_partition_list_partition(int n, typename ContextTypes::PartitionListReadContext& ctx) = 0; - /** Generated for complex type "set_global_signal": - * - * - * - * - * - */ - virtual inline const char * get_set_global_signal_name(typename ContextTypes::SetGlobalSignalReadContext &ctx) = 0; - virtual inline void set_set_global_signal_name(const char * name, typename ContextTypes::SetGlobalSignalWriteContext &ctx) = 0; - virtual inline const char * get_set_global_signal_route_model(typename ContextTypes::SetGlobalSignalReadContext &ctx) = 0; - virtual inline void set_set_global_signal_route_model(const char * route_model, typename ContextTypes::SetGlobalSignalWriteContext &ctx) = 0; - virtual inline const char * get_set_global_signal_type(typename ContextTypes::SetGlobalSignalReadContext &ctx) = 0; - virtual inline void set_set_global_signal_type(const char * type, typename ContextTypes::SetGlobalSignalWriteContext &ctx) = 0; + /** Generated for complex type "set_global_signal": + * + * + * + * + * + */ + virtual inline const char* get_set_global_signal_name(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_name(const char* name, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline const char* get_set_global_signal_route_model(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_route_model(const char* route_model, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline const char* get_set_global_signal_type(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_type(const char* type, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; - /** Generated for complex type "global_route_constraints": - * - * - * - * - * - */ - virtual inline void preallocate_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsWriteContext &ctx, size_t size) = 0; - virtual inline typename ContextTypes::SetGlobalSignalWriteContext add_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsWriteContext &ctx) = 0; - virtual inline void finish_global_route_constraints_set_global_signal(typename ContextTypes::SetGlobalSignalWriteContext &ctx) = 0; - virtual inline size_t num_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsReadContext &ctx) = 0; - virtual inline typename ContextTypes::SetGlobalSignalReadContext get_global_route_constraints_set_global_signal(int n, typename ContextTypes::GlobalRouteConstraintsReadContext &ctx) = 0; + /** Generated for complex type "global_route_constraints": + * + * + * + * + * + */ + virtual inline void preallocate_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::SetGlobalSignalWriteContext add_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx) = 0; + virtual inline void finish_global_route_constraints_set_global_signal(typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline size_t num_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsReadContext& ctx) = 0; + virtual inline typename ContextTypes::SetGlobalSignalReadContext get_global_route_constraints_set_global_signal(int n, typename ContextTypes::GlobalRouteConstraintsReadContext& ctx) = 0; - /** Generated for complex type "vpr_constraints": - * - * - * - * - * - * - * - */ - virtual inline const char * get_vpr_constraints_tool_name(typename ContextTypes::VprConstraintsReadContext &ctx) = 0; - virtual inline void set_vpr_constraints_tool_name(const char * tool_name, typename ContextTypes::VprConstraintsWriteContext &ctx) = 0; - virtual inline void preallocate_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsWriteContext &ctx, size_t size) = 0; - virtual inline typename ContextTypes::PartitionListWriteContext add_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsWriteContext &ctx) = 0; - virtual inline void finish_vpr_constraints_partition_list(typename ContextTypes::PartitionListWriteContext &ctx) = 0; - virtual inline size_t num_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsReadContext &ctx) = 0; - virtual inline typename ContextTypes::PartitionListReadContext get_vpr_constraints_partition_list(int n, typename ContextTypes::VprConstraintsReadContext &ctx) = 0; - virtual inline void preallocate_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsWriteContext &ctx, size_t size) = 0; - virtual inline typename ContextTypes::GlobalRouteConstraintsWriteContext add_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsWriteContext &ctx) = 0; - virtual inline void finish_vpr_constraints_global_route_constraints(typename ContextTypes::GlobalRouteConstraintsWriteContext &ctx) = 0; - virtual inline size_t num_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsReadContext &ctx) = 0; - virtual inline typename ContextTypes::GlobalRouteConstraintsReadContext get_vpr_constraints_global_route_constraints(int n, typename ContextTypes::VprConstraintsReadContext &ctx) = 0; + /** Generated for complex type "vpr_constraints": + * + * + * + * + * + * + * + */ + virtual inline const char* get_vpr_constraints_tool_name(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline void set_vpr_constraints_tool_name(const char* tool_name, typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; + virtual inline void preallocate_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::PartitionListWriteContext add_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; + virtual inline void finish_vpr_constraints_partition_list(typename ContextTypes::PartitionListWriteContext& ctx) = 0; + virtual inline size_t num_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline typename ContextTypes::PartitionListReadContext get_vpr_constraints_partition_list(int n, typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline void preallocate_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::GlobalRouteConstraintsWriteContext add_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; + virtual inline void finish_vpr_constraints_global_route_constraints(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx) = 0; + virtual inline size_t num_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline typename ContextTypes::GlobalRouteConstraintsReadContext get_vpr_constraints_global_route_constraints(int n, typename ContextTypes::VprConstraintsReadContext& ctx) = 0; }; } /* namespace uxsd */ diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 3911ecd16fb..2d48433521b 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -351,7 +351,7 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a if (!filename_opts.read_vpr_constraints_file.empty()) { load_vpr_constraints_file(filename_opts.read_vpr_constraints_file.c_str()); - // give a notificaiton on routing constraints overiding clock modeling + // give a notificaiton on routing constraints overiding clock modeling if (g_vpr_ctx.routing().constraints.get_route_constraint_num() && options->clock_modeling.provenance() == argparse::Provenance::SPECIFIED) { VTR_LOG_WARN("Route constraint(s) detected and will override clock modeling setting.\n"); } diff --git a/vpr/src/base/vpr_constraints.cpp b/vpr/src/base/vpr_constraints.cpp index 5dec3889dfe..eae4985c4f4 100644 --- a/vpr/src/base/vpr_constraints.cpp +++ b/vpr/src/base/vpr_constraints.cpp @@ -66,7 +66,7 @@ void VprConstraints::add_route_constraint(RouteConstraint rc) { RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) const { RouteConstraint rc; - auto const& rc_itr = route_constraints_.find(net_name); + auto const& rc_itr = route_constraints_.find(net_name); if (rc_itr == route_constraints_.end()) { rc.set_net_name("INVALID"); rc.set_net_type("INVALID"); @@ -88,9 +88,9 @@ RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) con } else { std::size_t i = 0; for (auto const& rc_itr : route_constraints_) { - if (i == idx) { - rc = rc_itr.second; - } + if (i == idx) { + rc = rc_itr.second; + } } } return rc; diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index ddfe531e587..b57756f5c7a 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -306,12 +306,12 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase - * - * - * - * - */ + * + * + * + * + * + */ virtual inline const char* get_set_global_signal_name(RouteConstraint& rc) final { return rc.get_net_name().c_str(); } @@ -335,12 +335,12 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase - * - * - * - * - */ + * + * + * + * + * + */ virtual inline void preallocate_global_route_constraints_set_global_signal(void*& /*ctx*/, size_t /*size*/) final {} virtual inline void* add_global_route_constraints_set_global_signal(void*& /*ctx*/) final { return nullptr; @@ -356,14 +356,14 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase - * - * - * - * - * - * - */ + * + * + * + * + * + * + * + */ virtual inline const char* get_vpr_constraints_tool_name(void*& /*ctx*/) final { return temp_.c_str(); } diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 421f8e2958c..a05119fd06d 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -435,7 +435,7 @@ struct RoutingContext : public Context { /** * @brief Routing constraints, read only - */ + */ VprConstraints constraints; }; diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 57bc95f4b36..80a54c0c47e 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -786,7 +786,7 @@ int get_max_primitives_in_pb_type(t_pb_type* pb_type) { for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { temp_size += pb_type->modes[i].pb_type_children[j].num_pb * get_max_primitives_in_pb_type( - &pb_type->modes[i].pb_type_children[j]); + &pb_type->modes[i].pb_type_children[j]); } if (temp_size > max_size) { max_size = temp_size; @@ -809,7 +809,7 @@ int get_max_nets_in_pb_type(const t_pb_type* pb_type) { for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { temp_nets += pb_type->modes[i].pb_type_children[j].num_pb * get_max_nets_in_pb_type( - &pb_type->modes[i].pb_type_children[j]); + &pb_type->modes[i].pb_type_children[j]); } if (temp_nets > max_nets) { max_nets = temp_nets; @@ -1535,7 +1535,7 @@ void free_pb_stats(t_pb* pb) { pb->pb_stats->num_pins_of_net_in_pb.clear(); if (pb->pb_stats->feasible_blocks) { - delete[] (pb->pb_stats->feasible_blocks); + delete[](pb->pb_stats->feasible_blocks); } if (!pb->parent_pb) { pb->pb_stats->transitive_fanout_candidates.clear(); From 5462d26a0f63798536a552b40e4842a88cd35fed Mon Sep 17 00:00:00 2001 From: Tao Li Date: Wed, 15 Feb 2023 13:42:04 -0800 Subject: [PATCH 116/453] Route constraint for local clock and reset. --- vpr/src/base/gen/vpr_constraints_uxsdcxx.h | 328 +++++++++++++++--- .../gen/vpr_constraints_uxsdcxx_interface.h | 55 ++- vpr/src/base/route_constraint.cpp | 43 +++ vpr/src/base/route_constraint.h | 65 ++++ vpr/src/base/vpr_api.cpp | 21 +- vpr/src/base/vpr_constraints.cpp | 64 ++++ vpr/src/base/vpr_constraints.h | 34 ++ vpr/src/base/vpr_constraints.xsd | 26 +- vpr/src/base/vpr_constraints_reader.cpp | 56 ++- vpr/src/base/vpr_constraints_reader.h | 2 +- vpr/src/base/vpr_constraints_serializer.h | 96 ++++- vpr/src/base/vpr_constraints_writer.cpp | 26 ++ vpr/src/base/vpr_constraints_writer.h | 2 + vpr/src/base/vpr_context.h | 5 + vpr/src/util/vpr_utils.cpp | 17 + vpr/src/util/vpr_utils.h | 4 + 16 files changed, 768 insertions(+), 76 deletions(-) create mode 100644 vpr/src/base/route_constraint.cpp create mode 100644 vpr/src/base/route_constraint.h diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h index 3248c338281..12feabd08ab 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx.py vpr_constraints.xsd - * Input file: /home/khalid88/Documents/uxsdcxx/vpr_constraints.xsd - * md5sum of input file: 6b6011a6e6446347b234da82e517422e + * Cmdline: uxsdcxx.py /home/tao/works/dev/clock/vtr-verilog-to-routing/vpr/src/base/vpr_constraints.xsd + * Input file: /home/tao/works/dev/clock/vtr-verilog-to-routing/vpr/src/base/vpr_constraints.xsd + * md5sum of input file: 2d6f442d8044f76e8f1b1d276b7358da */ #include @@ -25,8 +25,6 @@ #include "pugixml.hpp" #include "vpr_constraints_uxsdcxx_interface.h" -#include "region.h" - /* All uxsdcxx functions and structs live in this namespace. */ namespace uxsd { @@ -52,6 +50,10 @@ inline void load_partition(const pugi::xml_node& root, T& out, Context& context, template inline void load_partition_list(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); template +inline void load_set_global_signal(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template +inline void load_global_route_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); +template inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug); /* Declarations for internal write functions for the complex types. */ @@ -60,6 +62,8 @@ inline void write_partition(T& in, std::ostream& os, const void* data, void* ite template inline void write_partition_list(T& in, std::ostream& os, const void* data, void* iter); template +inline void write_global_route_constraints(T& in, std::ostream& os, const void* data, void* iter); +template inline void write_vpr_constraints(T& in, std::ostream& os, const void* data, void* iter); /* Load function for the root element. */ @@ -142,8 +146,17 @@ constexpr const char* atok_lookup_t_partition[] = {"name"}; enum class gtok_t_partition_list { PARTITION }; constexpr const char* gtok_lookup_t_partition_list[] = {"partition"}; -enum class gtok_t_vpr_constraints { PARTITION_LIST }; -constexpr const char* gtok_lookup_t_vpr_constraints[] = {"partition_list"}; + +enum class atok_t_set_global_signal { NAME, + ROUTE_MODEL, + TYPE }; +constexpr const char* atok_lookup_t_set_global_signal[] = {"name", "route_model", "type"}; + +enum class gtok_t_global_route_constraints { SET_GLOBAL_SIGNAL }; +constexpr const char* gtok_lookup_t_global_route_constraints[] = {"set_global_signal"}; +enum class gtok_t_vpr_constraints { PARTITION_LIST, + GLOBAL_ROUTE_CONSTRAINTS }; +constexpr const char* gtok_lookup_t_vpr_constraints[] = {"partition_list", "global_route_constraints"}; enum class atok_t_vpr_constraints { TOOL_NAME }; constexpr const char* atok_lookup_t_vpr_constraints[] = {"tool_name"}; @@ -348,6 +361,84 @@ inline gtok_t_partition_list lex_node_t_partition_list(const char* in, const std noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); } +inline atok_t_set_global_signal lex_attr_t_set_global_signal(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 4: + switch (*((triehash_uu32*)&in[0])) { + case onechar('n', 0, 32) | onechar('a', 8, 32) | onechar('m', 16, 32) | onechar('e', 24, 32): + return atok_t_set_global_signal::NAME; + break; + case onechar('t', 0, 32) | onechar('y', 8, 32) | onechar('p', 16, 32) | onechar('e', 24, 32): + return atok_t_set_global_signal::TYPE; + break; + default: + break; + } + break; + case 11: + switch (*((triehash_uu64*)&in[0])) { + case onechar('r', 0, 64) | onechar('o', 8, 64) | onechar('u', 16, 64) | onechar('t', 24, 64) | onechar('e', 32, 64) | onechar('_', 40, 64) | onechar('m', 48, 64) | onechar('o', 56, 64): + switch (in[8]) { + case onechar('d', 0, 8): + switch (in[9]) { + case onechar('e', 0, 8): + switch (in[10]) { + case onechar('l', 0, 8): + return atok_t_set_global_signal::ROUTE_MODEL; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized attribute " + std::string(in) + " of .").c_str()); +} + +inline gtok_t_global_route_constraints lex_node_t_global_route_constraints(const char* in, const std::function* report_error) { + unsigned int len = strlen(in); + switch (len) { + case 17: + switch (*((triehash_uu64*)&in[0])) { + case onechar('s', 0, 64) | onechar('e', 8, 64) | onechar('t', 16, 64) | onechar('_', 24, 64) | onechar('g', 32, 64) | onechar('l', 40, 64) | onechar('o', 48, 64) | onechar('b', 56, 64): + switch (*((triehash_uu64*)&in[8])) { + case onechar('a', 0, 64) | onechar('l', 8, 64) | onechar('_', 16, 64) | onechar('s', 24, 64) | onechar('i', 32, 64) | onechar('g', 40, 64) | onechar('n', 48, 64) | onechar('a', 56, 64): + switch (in[16]) { + case onechar('l', 0, 8): + return gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + noreturn_report(report_error, ("Found unrecognized child " + std::string(in) + " of .").c_str()); +} + inline gtok_t_vpr_constraints lex_node_t_vpr_constraints(const char* in, const std::function* report_error) { unsigned int len = strlen(in); switch (len) { @@ -378,6 +469,27 @@ inline gtok_t_vpr_constraints lex_node_t_vpr_constraints(const char* in, const s break; } break; + case 24: + switch (*((triehash_uu64*)&in[0])) { + case onechar('g', 0, 64) | onechar('l', 8, 64) | onechar('o', 16, 64) | onechar('b', 24, 64) | onechar('a', 32, 64) | onechar('l', 40, 64) | onechar('_', 48, 64) | onechar('r', 56, 64): + switch (*((triehash_uu64*)&in[8])) { + case onechar('o', 0, 64) | onechar('u', 8, 64) | onechar('t', 16, 64) | onechar('e', 24, 64) | onechar('_', 32, 64) | onechar('c', 40, 64) | onechar('o', 48, 64) | onechar('n', 56, 64): + switch (*((triehash_uu64*)&in[16])) { + case onechar('s', 0, 64) | onechar('t', 8, 64) | onechar('r', 16, 64) | onechar('a', 24, 64) | onechar('i', 32, 64) | onechar('n', 40, 64) | onechar('t', 48, 64) | onechar('s', 56, 64): + return gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS; + break; + default: + break; + } + break; + default: + break; + } + break; + default: + break; + } + break; default: break; } @@ -412,12 +524,6 @@ inline atok_t_vpr_constraints lex_attr_t_vpr_constraints(const char* in, const s */ [[noreturn]] inline void dfa_error(const char* wrong, const int* states, const char* const* lookup, int len, const std::function* report_error); -/** - * Internal error function for xs:all validators. - */ -template -[[noreturn]] inline void all_error(std::bitset gstate, const char* const* lookup, const std::function* report_error); - /** * Internal error function for attribute validators. */ @@ -427,8 +533,6 @@ template /* Internal loading functions, which validate and load a PugiXML DOM tree into memory. */ inline int load_int(const char* in, const std::function* report_error) { int out; - // global variable, must set to 0 before using it to avoid changed by other errors - errno = 0; out = std::strtol(in, NULL, 10); if (errno != 0) noreturn_report(report_error, ("Invalid value `" + std::string(in) + "` when loading into a int.").c_str()); @@ -674,6 +778,102 @@ inline void load_partition_list(const pugi::xml_node& root, T& out, Context& con if (state != 0) dfa_error("end of input", gstate_t_partition_list[state], gtok_lookup_t_partition_list, 1, report_error); } +template +inline void load_set_global_signal(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + for (pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()) { + atok_t_set_global_signal in = lex_attr_t_set_global_signal(attr.name(), report_error); + switch (in) { + case atok_t_set_global_signal::NAME: + out.set_set_global_signal_name(attr.value(), context); + break; + case atok_t_set_global_signal::ROUTE_MODEL: + out.set_set_global_signal_route_model(attr.value(), context); + break; + case atok_t_set_global_signal::TYPE: + out.set_set_global_signal_type(attr.value(), context); + break; + default: + break; /* Not possible. */ + } + } + + if (root.first_child().type() == pugi::node_element) + noreturn_report(report_error, "Unexpected child element in ."); +} + +constexpr int NUM_T_GLOBAL_ROUTE_CONSTRAINTS_STATES = 2; +constexpr const int NUM_T_GLOBAL_ROUTE_CONSTRAINTS_INPUTS = 1; +constexpr int gstate_t_global_route_constraints[NUM_T_GLOBAL_ROUTE_CONSTRAINTS_STATES][NUM_T_GLOBAL_ROUTE_CONSTRAINTS_INPUTS] = { + {0}, + {0}, +}; +template +inline void load_global_route_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { + (void)root; + (void)out; + (void)context; + (void)report_error; + // Update current file offset in case an error is encountered. + *offset_debug = root.offset_debug(); + + if (root.first_attribute()) + noreturn_report(report_error, "Unexpected attribute in ."); + + // Preallocate arrays by counting child nodes (if any) + size_t set_global_signal_count = 0; + { + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_global_route_constraints in = lex_node_t_global_route_constraints(node.name(), report_error); + next = gstate_t_global_route_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_global_route_constraints[(int)in], gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); + state = next; + switch (in) { + case gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL: + set_global_signal_count += 1; + break; + default: + break; /* Not possible. */ + } + } + + out.preallocate_global_route_constraints_set_global_signal(context, set_global_signal_count); + } + int next, state = 1; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_global_route_constraints in = lex_node_t_global_route_constraints(node.name(), report_error); + next = gstate_t_global_route_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_global_route_constraints[(int)in], gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); + state = next; + switch (in) { + case gtok_t_global_route_constraints::SET_GLOBAL_SIGNAL: { + auto child_context = out.add_global_route_constraints_set_global_signal(context); + load_set_global_signal(node, out, child_context, report_error, offset_debug); + out.finish_global_route_constraints_set_global_signal(child_context); + } break; + default: + break; /* Not possible. */ + } + } + if (state != 0) dfa_error("end of input", gstate_t_global_route_constraints[state], gtok_lookup_t_global_route_constraints, 1, report_error); +} + +constexpr int NUM_T_VPR_CONSTRAINTS_STATES = 1; +constexpr const int NUM_T_VPR_CONSTRAINTS_INPUTS = 2; +constexpr int gstate_t_vpr_constraints[NUM_T_VPR_CONSTRAINTS_STATES][NUM_T_VPR_CONSTRAINTS_INPUTS] = { + {0, 0}, +}; template inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& context, const std::function* report_error, ptrdiff_t* offset_debug) { (void)root; @@ -694,26 +894,57 @@ inline void load_vpr_constraints(const pugi::xml_node& root, T& out, Context& co } } - std::bitset<1> gstate = 0; + // Preallocate arrays by counting child nodes (if any) + size_t partition_list_count = 0; + size_t global_route_constraints_count = 0; + { + int next, state = 0; + for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { + *offset_debug = node.offset_debug(); + gtok_t_vpr_constraints in = lex_node_t_vpr_constraints(node.name(), report_error); + next = gstate_t_vpr_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_vpr_constraints[(int)in], gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); + state = next; + switch (in) { + case gtok_t_vpr_constraints::PARTITION_LIST: + partition_list_count += 1; + break; + case gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS: + global_route_constraints_count += 1; + break; + default: + break; /* Not possible. */ + } + } + + out.preallocate_vpr_constraints_partition_list(context, partition_list_count); + out.preallocate_vpr_constraints_global_route_constraints(context, global_route_constraints_count); + } + int next, state = 0; for (pugi::xml_node node = root.first_child(); node; node = node.next_sibling()) { *offset_debug = node.offset_debug(); gtok_t_vpr_constraints in = lex_node_t_vpr_constraints(node.name(), report_error); - if (gstate[(int)in] == 0) - gstate[(int)in] = 1; - else - noreturn_report(report_error, ("Duplicate element " + std::string(node.name()) + " in .").c_str()); + next = gstate_t_vpr_constraints[state][(int)in]; + if (next == -1) + dfa_error(gtok_lookup_t_vpr_constraints[(int)in], gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); + state = next; switch (in) { case gtok_t_vpr_constraints::PARTITION_LIST: { - auto child_context = out.init_vpr_constraints_partition_list(context); + auto child_context = out.add_vpr_constraints_partition_list(context); load_partition_list(node, out, child_context, report_error, offset_debug); out.finish_vpr_constraints_partition_list(child_context); } break; + case gtok_t_vpr_constraints::GLOBAL_ROUTE_CONSTRAINTS: { + auto child_context = out.add_vpr_constraints_global_route_constraints(context); + load_global_route_constraints(node, out, child_context, report_error, offset_debug); + out.finish_vpr_constraints_global_route_constraints(child_context); + } break; default: break; /* Not possible. */ } } - std::bitset<1> test_gstate = gstate | std::bitset<1>(0b0); - if (!test_gstate.all()) all_error(test_gstate, gtok_lookup_t_vpr_constraints, report_error); + if (state != 0) dfa_error("end of input", gstate_t_vpr_constraints[state], gtok_lookup_t_vpr_constraints, 2, report_error); } /* Internal writing functions, which uxsdcxx uses to write out a class. */ @@ -734,7 +965,7 @@ inline void write_partition(T& in, std::ostream& os, Context& context) { for (size_t i = 0, n = in.num_partition_add_region(context); i < n; i++) { auto child_context = in.get_partition_add_region(i, context); os << " +inline void write_global_route_constraints(T& in, std::ostream& os, Context& context) { + (void)in; + (void)os; + (void)context; + { + for (size_t i = 0, n = in.num_global_route_constraints_set_global_signal(context); i < n; i++) { + auto child_context = in.get_global_route_constraints_set_global_signal(i, context); + os << "\n"; + } + } +} + template inline void write_vpr_constraints(T& in, std::ostream& os, Context& context) { (void)in; (void)os; (void)context; { - auto child_context = in.get_vpr_constraints_partition_list(context); - os << "\n"; - write_partition_list(in, os, child_context); - os << "\n"; + for (size_t i = 0, n = in.num_vpr_constraints_partition_list(context); i < n; i++) { + auto child_context = in.get_vpr_constraints_partition_list(i, context); + os << "\n"; + write_partition_list(in, os, child_context); + os << "\n"; + } + } + { + for (size_t i = 0, n = in.num_vpr_constraints_global_route_constraints(context); i < n; i++) { + auto child_context = in.get_vpr_constraints_global_route_constraints(i, context); + os << "\n"; + write_global_route_constraints(in, os, child_context); + os << "\n"; + } } } @@ -788,20 +1046,6 @@ inline void dfa_error(const char* wrong, const int* states, const char* const* l noreturn_report(report_error, ("Expected " + expected_or + ", found " + std::string(wrong)).c_str()); } -template -inline void all_error(std::bitset gstate, const char* const* lookup, const std::function* report_error) { - std::vector missing; - for (unsigned int i = 0; i < N; i++) { - if (gstate[i] == 0) missing.push_back(lookup[i]); - } - - std::string missing_and = missing[0]; - for (unsigned int i = 1; i < missing.size(); i++) - missing_and += std::string(", ") + missing[i]; - - noreturn_report(report_error, ("Didn't find required elements " + missing_and + ".").c_str()); -} - template inline void attr_error(std::bitset astate, const char* const* lookup, const std::function* report_error) { std::vector missing; diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h index 6da8558b84d..280bf58c793 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx.py vpr_constraints.xsd - * Input file: /home/khalid88/Documents/uxsdcxx/vpr_constraints.xsd - * md5sum of input file: 6b6011a6e6446347b234da82e517422e + * Cmdline: uxsdcxx.py /home/tao/works/dev/clock/vtr-verilog-to-routing/vpr/src/base/vpr_constraints.xsd + * Input file: /home/tao/works/dev/clock/vtr-verilog-to-routing/vpr/src/base/vpr_constraints.xsd + * md5sum of input file: 2d6f442d8044f76e8f1b1d276b7358da */ #include @@ -24,11 +24,15 @@ struct DefaultVprConstraintsContextTypes { using AddRegionReadContext = void*; using PartitionReadContext = void*; using PartitionListReadContext = void*; + using SetGlobalSignalReadContext = void*; + using GlobalRouteConstraintsReadContext = void*; using VprConstraintsReadContext = void*; using AddAtomWriteContext = void*; using AddRegionWriteContext = void*; using PartitionWriteContext = void*; using PartitionListWriteContext = void*; + using SetGlobalSignalWriteContext = void*; + using GlobalRouteConstraintsWriteContext = void*; using VprConstraintsWriteContext = void*; }; @@ -92,7 +96,7 @@ class VprConstraintsBase { /** Generated for complex type "partition_list": * * - * + * * * */ @@ -102,19 +106,54 @@ class VprConstraintsBase { virtual inline size_t num_partition_list_partition(typename ContextTypes::PartitionListReadContext& ctx) = 0; virtual inline typename ContextTypes::PartitionReadContext get_partition_list_partition(int n, typename ContextTypes::PartitionListReadContext& ctx) = 0; + /** Generated for complex type "set_global_signal": + * + * + * + * + * + */ + virtual inline const char* get_set_global_signal_name(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_name(const char* name, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline const char* get_set_global_signal_route_model(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_route_model(const char* route_model, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline const char* get_set_global_signal_type(typename ContextTypes::SetGlobalSignalReadContext& ctx) = 0; + virtual inline void set_set_global_signal_type(const char* type, typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + + /** Generated for complex type "global_route_constraints": + * + * + * + * + * + */ + virtual inline void preallocate_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::SetGlobalSignalWriteContext add_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx) = 0; + virtual inline void finish_global_route_constraints_set_global_signal(typename ContextTypes::SetGlobalSignalWriteContext& ctx) = 0; + virtual inline size_t num_global_route_constraints_set_global_signal(typename ContextTypes::GlobalRouteConstraintsReadContext& ctx) = 0; + virtual inline typename ContextTypes::SetGlobalSignalReadContext get_global_route_constraints_set_global_signal(int n, typename ContextTypes::GlobalRouteConstraintsReadContext& ctx) = 0; + /** Generated for complex type "vpr_constraints": * - * + * * - * + * + * * * */ virtual inline const char* get_vpr_constraints_tool_name(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; virtual inline void set_vpr_constraints_tool_name(const char* tool_name, typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; - virtual inline typename ContextTypes::PartitionListWriteContext init_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; + virtual inline void preallocate_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::PartitionListWriteContext add_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; virtual inline void finish_vpr_constraints_partition_list(typename ContextTypes::PartitionListWriteContext& ctx) = 0; - virtual inline typename ContextTypes::PartitionListReadContext get_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline size_t num_vpr_constraints_partition_list(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline typename ContextTypes::PartitionListReadContext get_vpr_constraints_partition_list(int n, typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline void preallocate_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsWriteContext& ctx, size_t size) = 0; + virtual inline typename ContextTypes::GlobalRouteConstraintsWriteContext add_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsWriteContext& ctx) = 0; + virtual inline void finish_vpr_constraints_global_route_constraints(typename ContextTypes::GlobalRouteConstraintsWriteContext& ctx) = 0; + virtual inline size_t num_vpr_constraints_global_route_constraints(typename ContextTypes::VprConstraintsReadContext& ctx) = 0; + virtual inline typename ContextTypes::GlobalRouteConstraintsReadContext get_vpr_constraints_global_route_constraints(int n, typename ContextTypes::VprConstraintsReadContext& ctx) = 0; }; } /* namespace uxsd */ diff --git a/vpr/src/base/route_constraint.cpp b/vpr/src/base/route_constraint.cpp new file mode 100644 index 00000000000..a7dadc3a1ec --- /dev/null +++ b/vpr/src/base/route_constraint.cpp @@ -0,0 +1,43 @@ +#include "route_constraint.h" + +RouteConstraint::RouteConstraint() { + net_name_ = std::string(""); + net_type_ = std::string(""); + route_method_ = std::string(""); + is_valid_ = false; +} + +void RouteConstraint::set_net_name(std::string name) { + net_name_ = name; + return; +} + +std::string RouteConstraint::get_net_name() const { + return net_name_; +} + +void RouteConstraint::set_net_type(std::string type) { + net_type_ = type; + return; +} + +std::string RouteConstraint::get_net_type() const { + return net_type_; +} + +void RouteConstraint::set_route_model(std::string route_method) { + route_method_ = route_method; + return; +} + +std::string RouteConstraint::get_route_model() const { + return route_method_; +} + +void RouteConstraint::set_is_valid(bool value) { + is_valid_ = value; +} + +bool RouteConstraint::get_is_valid() const { + return is_valid_; +} diff --git a/vpr/src/base/route_constraint.h b/vpr/src/base/route_constraint.h new file mode 100644 index 00000000000..50b967e3f31 --- /dev/null +++ b/vpr/src/base/route_constraint.h @@ -0,0 +1,65 @@ +#ifndef ROUTE_CONSTRAINT_H +#define ROUTE_CONSTRAINT_H + +#include "vpr_types.h" + +/** + * @file + * @brief This file defines the RouteConstraint class. + */ + +class RouteConstraint { + public: + /** + * @brief Constructor for the RouteConstraint class, sets member variables to invalid values + */ + RouteConstraint(); + + /** + * @brief get net name + */ + std::string get_net_name() const; + + /** + * @brief set net name + */ + void set_net_name(std::string); + + /** + * @brief get net type + */ + std::string get_net_type() const; + + /** + * @brief set net type + */ + void set_net_type(std::string); + + /** + * @brief get route model + */ + std::string get_route_model() const; + + /** + * @brief set route model + */ + void set_route_model(std::string); + + /** + * @brief set is valid + */ + void set_is_valid(bool); + + /** + * @brief get is valid + */ + bool get_is_valid() const; + + private: + std::string net_name_; + std::string net_type_; + std::string route_method_; + bool is_valid_; +}; + +#endif /* ROUTE_CONSTRAINT_H */ diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 6a4fafc9a10..f8e481f3a24 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -346,10 +346,15 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a } } - //Initialize vpr floorplanning constraints + //Initialize vpr floorplanning and routing constraints auto& filename_opts = vpr_setup->FileNameOpts; if (!filename_opts.read_vpr_constraints_file.empty()) { - load_vpr_constraints_file(filename_opts.read_vpr_constraints_file.c_str()); + load_vpr_constraints_files(filename_opts.read_vpr_constraints_file.c_str()); + + // give a notificaiton on routing constraints overiding clock modeling + if (g_vpr_ctx.routing().constraints.get_route_constraint_num() && options->clock_modeling.provenance() == argparse::Provenance::SPECIFIED) { + VTR_LOG_WARN("Route constraint(s) detected and will override clock modeling setting.\n"); + } } fflush(stdout); @@ -696,7 +701,7 @@ bool vpr_place_flow(t_vpr_setup& vpr_setup, const t_arch& arch) { //Write out a vpr floorplanning constraints file if the option is specified if (!filename_opts.write_vpr_constraints_file.empty()) { - write_vpr_floorplan_constraints(filename_opts.write_vpr_constraints_file.c_str(), placer_opts.place_constraint_expand, placer_opts.place_constraint_subtile, + write_vpr_floorplan_constraints("vpr_floorplan_constraints.xml" /*filename_opts.write_vpr_constraints_file.c_str()*/, placer_opts.place_constraint_expand, placer_opts.place_constraint_subtile, placer_opts.floorplan_num_horizontal_partitions, placer_opts.floorplan_num_vertical_partitions); } @@ -766,6 +771,11 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_f //Assume successful route_status = RouteStatus(true, -1); } else { //Do or load + + // apply route constraints + // use mutable routing context here to apply change on the constraints when binding the constraint to real net + apply_route_constraints(g_vpr_ctx.mutable_routing().constraints); + int chan_width = router_opts.fixed_channel_width; auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -847,6 +857,11 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_f //Update interactive graphics update_screen(ScreenUpdatePriority::MAJOR, graphics_msg.c_str(), ROUTING, timing_info); + + //Write out a vpr floorplanning constraints file if the option is specified + if (!filename_opts.write_vpr_constraints_file.empty()) { + write_vpr_route_constraints(g_vpr_ctx.routing().constraints, "vpr_route_constraints.xml" /*filename_opts.write_vpr_constraints_file.c_str()*/); + } } return route_status; diff --git a/vpr/src/base/vpr_constraints.cpp b/vpr/src/base/vpr_constraints.cpp index 95c7e7b7358..4b9850be670 100644 --- a/vpr/src/base/vpr_constraints.cpp +++ b/vpr/src/base/vpr_constraints.cpp @@ -1,5 +1,7 @@ #include "vpr_constraints.h" #include "partition.h" +#include "route_constraint.h" +#include void VprConstraints::add_constrained_atom(const AtomBlockId blk_id, const PartitionId part_id) { auto got = constrained_atoms.find(blk_id); @@ -58,6 +60,68 @@ PartitionRegion VprConstraints::get_partition_pr(PartitionId part_id) { return pr; } +void VprConstraints::add_route_constraint(RouteConstraint rc) { + route_constraints_.insert({rc.get_net_name(), rc}); + return; +} + +RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) { + RouteConstraint rc; + auto const& rc_itr = route_constraints_.find(net_name); + if (rc_itr == route_constraints_.end()) { + // try regexp + bool found_thru_regex = false; + for (auto constraint : route_constraints_) { + if (std::regex_match(net_name, std::regex(constraint.first))) { + { + rc = constraint.second; + + // mark as invalid so write constraint function will not write constraint + // of regexpr name + // instead a matched constraint is inerted in + constraint.second.set_is_valid(false); + rc.set_is_valid(true); + route_constraints_.insert({net_name, rc}); + + found_thru_regex = true; + break; + } + } + } + if (!found_thru_regex) { + rc.set_net_name("INVALID"); + rc.set_net_type("INVALID"); + rc.set_route_model("INVALID"); + rc.set_is_valid(false); + } + } else { + rc = rc_itr->second; + } + return rc; +} + +RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) const { + RouteConstraint rc; + if ((route_constraints_.size() == 0) || (idx > route_constraints_.size() - 1)) { + rc.set_net_name("INVALID"); + rc.set_net_type("INVALID"); + rc.set_route_model("INVALID"); + rc.set_is_valid(false); + } else { + std::size_t i = 0; + for (auto const& rc_itr : route_constraints_) { + if (i == idx) { + rc = rc_itr.second; + } + } + } + return rc; +} + +int VprConstraints::get_route_constraint_num(void) const { + return route_constraints_.size(); +} + void print_constraints(FILE* fp, VprConstraints constraints) { Partition temp_part; std::vector atoms; diff --git a/vpr/src/base/vpr_constraints.h b/vpr/src/base/vpr_constraints.h index fd3f64842a4..61d7ed9d6b6 100644 --- a/vpr/src/base/vpr_constraints.h +++ b/vpr/src/base/vpr_constraints.h @@ -5,6 +5,7 @@ #include "vpr_utils.h" #include "partition.h" #include "partition_region.h" +#include "route_constraint.h" /** * @file @@ -87,6 +88,34 @@ class VprConstraints { */ PartitionRegion get_partition_pr(PartitionId part_id); + /** + * @brief add route constraint + * + * @param net_name the route constraint + */ + void add_route_constraint(RouteConstraint rc); + + /** + * @brief returns route constraint by index + * + * @param index the constraint index + */ + RouteConstraint get_route_constraint_by_idx(std::size_t index) const; + + /** + * @brief returns route constraint of a specific net + * + * @param net_name the net name + */ + RouteConstraint get_route_constraint_by_net_name(std::string net_name); + + /** + * @brief returns number of route constraints + * + * @param void + */ + int get_route_constraint_num(void) const; + private: /** * Store all constrained atoms @@ -97,6 +126,11 @@ class VprConstraints { * Store all partitions */ vtr::vector partitions; + + /** + * store all route constraints + */ + std::unordered_map route_constraints_; }; ///@brief used to print floorplanning constraints data from a VprConstraints object diff --git a/vpr/src/base/vpr_constraints.xsd b/vpr/src/base/vpr_constraints.xsd index 406e2abcda4..2ed93b77347 100644 --- a/vpr/src/base/vpr_constraints.xsd +++ b/vpr/src/base/vpr_constraints.xsd @@ -59,16 +59,36 @@ + + + + + + + + + + + + + + + - + - - + + diff --git a/vpr/src/base/vpr_constraints_reader.cpp b/vpr/src/base/vpr_constraints_reader.cpp index 8e69b7b42b4..eec6d772490 100644 --- a/vpr/src/base/vpr_constraints_reader.cpp +++ b/vpr/src/base/vpr_constraints_reader.cpp @@ -10,31 +10,59 @@ #include #include "vpr_constraints_reader.h" +#include "vtr_token.h" -void load_vpr_constraints_file(const char* read_vpr_constraints_name) { - vtr::ScopedStartFinishTimer timer("Loading VPR constraints file"); +void load_vpr_constraints_files(const char* read_vpr_constraints_name) { + vtr::ScopedStartFinishTimer timer("Loading VPR constraints file(s)"); VprConstraintsSerializer reader; - if (vtr::check_file_name_extension(read_vpr_constraints_name, ".xml")) { - try { - std::ifstream file(read_vpr_constraints_name); - void* context; - uxsd::load_vpr_constraints_xml(reader, context, read_vpr_constraints_name, file); - } catch (pugiutil::XmlError& e) { - vpr_throw(VPR_ERROR_ROUTE, read_vpr_constraints_name, e.line(), "%s", e.what()); + // file name from arguments could be a serial of files, seperated by colon ":" + // at this point, caller has already checked that the required constraint file name is not emtpy + int num_tokens = 0, num_file_read = 0; + bool found_file = false; + t_token* tokens = GetTokensFromString(read_vpr_constraints_name, &num_tokens); + std::string in_tokens(""); + for (int i = 0; i < num_tokens; i++) { + if ((tokens[i].type == TOKEN_COLON)) { // end of one input file + found_file = true; + } else if (i == num_tokens - 1) { // end of inputs, append token anyway + in_tokens += std::string(tokens[i].data); + found_file = true; + } else { + in_tokens += std::string(tokens[i].data); + } + if (found_file) { + const char* file_name = in_tokens.c_str(); + if (vtr::check_file_name_extension(file_name, ".xml")) { + try { + std::ifstream file(file_name); + void* context; + uxsd::load_vpr_constraints_xml(reader, context, file_name, file); + } catch (pugiutil::XmlError& e) { + vpr_throw(VPR_ERROR_ROUTE, file_name, e.line(), "%s", e.what()); + } + } else { + VTR_LOG_WARN( + "VPR constraints file '%s' may be in incorrect format. " + "Expecting .xml format. Not reading file.\n", + file_name); + } + in_tokens.clear(); + num_file_read++; + found_file = false; } - } else { - VTR_LOG_WARN( - "VPR constraints file '%s' may be in incorrect format. " - "Expecting .xml format. Not reading file.\n", - read_vpr_constraints_name); } + VTR_LOG("Read in '%d' constraint file(s) successfully.\n", num_file_read); //Update the floorplanning constraints in the floorplanning constraints context auto& floorplanning_ctx = g_vpr_ctx.mutable_floorplanning(); floorplanning_ctx.constraints = reader.constraints_; + // update vpr constraints for routing + auto& routing_ctx = g_vpr_ctx.mutable_routing(); + routing_ctx.constraints = reader.constraints_; + VprConstraints ctx_constraints = floorplanning_ctx.constraints; if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_VPR_CONSTRAINTS)) { diff --git a/vpr/src/base/vpr_constraints_reader.h b/vpr/src/base/vpr_constraints_reader.h index 95fcc988607..60aefc25b5b 100644 --- a/vpr/src/base/vpr_constraints_reader.h +++ b/vpr/src/base/vpr_constraints_reader.h @@ -5,6 +5,6 @@ #ifndef VPR_CONSTRAINTS_READER_H_ #define VPR_CONSTRAINTS_READER_H_ -void load_vpr_constraints_file(const char* read_vpr_constraints_name); +void load_vpr_constraints_files(const char* read_vpr_constraints_name); #endif /* VPR_CONSTRAINTS_READER_H_ */ diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index 4007b7c5c3b..b57756f5c7a 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -2,6 +2,7 @@ #define VPR_CONSTRAINTS_SERIALIZER_H_ #include "region.h" +#include "route_constraint.h" #include "vpr_constraints.h" #include "partition.h" #include "partition_region.h" @@ -69,11 +70,15 @@ struct VprConstraintsContextTypes : public uxsd::DefaultVprConstraintsContextTyp using AddRegionReadContext = Region; using PartitionReadContext = partition_info; using PartitionListReadContext = void*; + using SetGlobalSignalReadContext = RouteConstraint; + using GlobalRouteConstraintsReadContext = void*; using VprConstraintsReadContext = void*; using AddAtomWriteContext = void*; using AddRegionWriteContext = void*; using PartitionWriteContext = void*; using PartitionListWriteContext = void*; + using SetGlobalSignalWriteContext = void*; + using GlobalRouteConstraintsWriteContext = void*; using VprConstraintsWriteContext = void*; }; @@ -300,11 +305,62 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase + * + * + * + * + */ + virtual inline const char* get_set_global_signal_name(RouteConstraint& rc) final { + return rc.get_net_name().c_str(); + } + virtual inline void set_set_global_signal_name(const char* name, void*& /*ctx*/) final { + std::string net_name = std::string(name); + loaded_route_constraint.set_net_name(net_name); + return; + } + virtual inline const char* get_set_global_signal_route_model(RouteConstraint& rc) final { + return rc.get_route_model().c_str(); + } + virtual inline void set_set_global_signal_route_model(const char* route_model, void*& /*ctx*/) final { + loaded_route_constraint.set_route_model(std::string(route_model)); + loaded_route_constraint.set_is_valid(true); + } + virtual inline const char* get_set_global_signal_type(RouteConstraint& rc) final { + return rc.get_net_type().c_str(); + } + virtual inline void set_set_global_signal_type(const char* type, void*& /*ctx*/) final { + loaded_route_constraint.set_net_type(std::string(type)); + } + + /** Generated for complex type "global_route_constraints": + * + * + * + * + * + */ + virtual inline void preallocate_global_route_constraints_set_global_signal(void*& /*ctx*/, size_t /*size*/) final {} + virtual inline void* add_global_route_constraints_set_global_signal(void*& /*ctx*/) final { + return nullptr; + } + virtual inline void finish_global_route_constraints_set_global_signal(void*& /*ctx*/) final { + constraints_.add_route_constraint(loaded_route_constraint); + } + virtual inline size_t num_global_route_constraints_set_global_signal(void*& /*ctx*/) final { + return constraints_.get_route_constraint_num(); + } + virtual inline RouteConstraint get_global_route_constraints_set_global_signal(int n, void*& /*ctx*/) final { + return constraints_.get_route_constraint_by_idx((std::size_t)n); + } + /** Generated for complex type "vpr_constraints": * - * + * * - * + * + * * * */ @@ -312,25 +368,54 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase::max_digits10); + void* context; + uxsd::write_vpr_constraints_xml(writer, context, fp); + } else { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, + "Unknown extension on output %s", + file_name); + } + + return; +} diff --git a/vpr/src/base/vpr_constraints_writer.h b/vpr/src/base/vpr_constraints_writer.h index 756f8c17c29..caac1abd85b 100644 --- a/vpr/src/base/vpr_constraints_writer.h +++ b/vpr/src/base/vpr_constraints_writer.h @@ -47,4 +47,6 @@ void setup_vpr_floorplan_constraints_cutpoints(VprConstraints& constraints, int void create_partition(Partition& part, std::string part_name, int xmin, int ymin, int xmax, int ymax); +void write_vpr_route_constraints(const VprConstraints& constraints, const char* file_name); + #endif /* VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ */ diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 0ed27f1a070..0b7d123d1b3 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -438,6 +438,11 @@ struct RoutingContext : public Context { vtr::Cache>, RouterLookahead> cached_router_lookahead_; + + /** + * @brief Routing constraints, read only + */ + VprConstraints constraints; }; /** diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index ec8bb686a28..1583065d0ed 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -20,6 +20,7 @@ #include "pack_types.h" #include "device_grid.h" #include "timing_fail_error.h" +#include "route_constraint.h" /* This module contains subroutines that are used in several unrelated parts * * of VPR. They are VPR-specific utility routines. */ @@ -2191,3 +2192,19 @@ bool is_node_on_tile(t_physical_tile_type_ptr physical_tile, } } } + +void apply_route_constraints(VprConstraints& vpr_constraint) { + ClusteringContext& mutable_cluster_ctx = g_vpr_ctx.mutable_clustering(); + for (auto net_id : mutable_cluster_ctx.clb_nlist.nets()) { + std::string net_name = mutable_cluster_ctx.clb_nlist.net_name(net_id); + RouteConstraint rc = vpr_constraint.get_route_constraint_by_net_name(net_name); + if (rc.get_is_valid()) { + mutable_cluster_ctx.clb_nlist.set_net_is_global(net_id, true); + if (rc.get_route_model() == "route") { + mutable_cluster_ctx.clb_nlist.set_net_is_ignored(net_id, false); + } else { + mutable_cluster_ctx.clb_nlist.set_net_is_ignored(net_id, true); + } + } + } +} diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index e13909f7a01..d2ba2eefd5c 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -191,4 +191,8 @@ bool is_node_on_tile(t_physical_tile_type_ptr physical_tile, t_rr_type node_type, int node_ptc); +// apply route constraints for route flow +class VprConstraints; +void apply_route_constraints(VprConstraints& constraint); + #endif From 99c132d176ad95dbd9f868ab2991a2b05058f643 Mon Sep 17 00:00:00 2001 From: Tao Li Date: Sat, 25 Feb 2023 23:00:27 -0800 Subject: [PATCH 117/453] Update with regexpr and multi-files readin. --- vpr/src/base/vpr_api.cpp | 5 ++- vpr/src/base/vpr_constraints.cpp | 32 ++++++++++++--- vpr/src/base/vpr_constraints.h | 2 +- vpr/src/base/vpr_constraints_reader.cpp | 52 ++++++++++++++++++------- vpr/src/base/vpr_constraints_reader.h | 2 +- vpr/src/util/vpr_utils.cpp | 2 +- vpr/src/util/vpr_utils.h | 2 +- 7 files changed, 72 insertions(+), 25 deletions(-) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 2d48433521b..e094bc25eb3 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -349,7 +349,7 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a //Initialize vpr floorplanning and routing constraints auto& filename_opts = vpr_setup->FileNameOpts; if (!filename_opts.read_vpr_constraints_file.empty()) { - load_vpr_constraints_file(filename_opts.read_vpr_constraints_file.c_str()); + load_vpr_constraints_files(filename_opts.read_vpr_constraints_file.c_str()); // give a notificaiton on routing constraints overiding clock modeling if (g_vpr_ctx.routing().constraints.get_route_constraint_num() && options->clock_modeling.provenance() == argparse::Provenance::SPECIFIED) { @@ -773,7 +773,8 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_f } else { //Do or load // apply route constraints - apply_route_constraints(g_vpr_ctx.routing().constraints); + // use mutable routing context here to apply change on the constraints when binding the constraint to real net + apply_route_constraints(g_vpr_ctx.mutable_routing().constraints); int chan_width = router_opts.fixed_channel_width; diff --git a/vpr/src/base/vpr_constraints.cpp b/vpr/src/base/vpr_constraints.cpp index eae4985c4f4..4b9850be670 100644 --- a/vpr/src/base/vpr_constraints.cpp +++ b/vpr/src/base/vpr_constraints.cpp @@ -1,6 +1,7 @@ #include "vpr_constraints.h" #include "partition.h" #include "route_constraint.h" +#include void VprConstraints::add_constrained_atom(const AtomBlockId blk_id, const PartitionId part_id) { auto got = constrained_atoms.find(blk_id); @@ -64,14 +65,35 @@ void VprConstraints::add_route_constraint(RouteConstraint rc) { return; } -RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) const { +RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) { RouteConstraint rc; auto const& rc_itr = route_constraints_.find(net_name); if (rc_itr == route_constraints_.end()) { - rc.set_net_name("INVALID"); - rc.set_net_type("INVALID"); - rc.set_route_model("INVALID"); - rc.set_is_valid(false); + // try regexp + bool found_thru_regex = false; + for (auto constraint : route_constraints_) { + if (std::regex_match(net_name, std::regex(constraint.first))) { + { + rc = constraint.second; + + // mark as invalid so write constraint function will not write constraint + // of regexpr name + // instead a matched constraint is inerted in + constraint.second.set_is_valid(false); + rc.set_is_valid(true); + route_constraints_.insert({net_name, rc}); + + found_thru_regex = true; + break; + } + } + } + if (!found_thru_regex) { + rc.set_net_name("INVALID"); + rc.set_net_type("INVALID"); + rc.set_route_model("INVALID"); + rc.set_is_valid(false); + } } else { rc = rc_itr->second; } diff --git a/vpr/src/base/vpr_constraints.h b/vpr/src/base/vpr_constraints.h index fbe4e314f75..61d7ed9d6b6 100644 --- a/vpr/src/base/vpr_constraints.h +++ b/vpr/src/base/vpr_constraints.h @@ -107,7 +107,7 @@ class VprConstraints { * * @param net_name the net name */ - RouteConstraint get_route_constraint_by_net_name(std::string net_name) const; + RouteConstraint get_route_constraint_by_net_name(std::string net_name); /** * @brief returns number of route constraints diff --git a/vpr/src/base/vpr_constraints_reader.cpp b/vpr/src/base/vpr_constraints_reader.cpp index 193ae901d57..eec6d772490 100644 --- a/vpr/src/base/vpr_constraints_reader.cpp +++ b/vpr/src/base/vpr_constraints_reader.cpp @@ -10,26 +10,50 @@ #include #include "vpr_constraints_reader.h" +#include "vtr_token.h" -void load_vpr_constraints_file(const char* read_vpr_constraints_name) { - vtr::ScopedStartFinishTimer timer("Loading VPR constraints file"); +void load_vpr_constraints_files(const char* read_vpr_constraints_name) { + vtr::ScopedStartFinishTimer timer("Loading VPR constraints file(s)"); VprConstraintsSerializer reader; - if (vtr::check_file_name_extension(read_vpr_constraints_name, ".xml")) { - try { - std::ifstream file(read_vpr_constraints_name); - void* context; - uxsd::load_vpr_constraints_xml(reader, context, read_vpr_constraints_name, file); - } catch (pugiutil::XmlError& e) { - vpr_throw(VPR_ERROR_ROUTE, read_vpr_constraints_name, e.line(), "%s", e.what()); + // file name from arguments could be a serial of files, seperated by colon ":" + // at this point, caller has already checked that the required constraint file name is not emtpy + int num_tokens = 0, num_file_read = 0; + bool found_file = false; + t_token* tokens = GetTokensFromString(read_vpr_constraints_name, &num_tokens); + std::string in_tokens(""); + for (int i = 0; i < num_tokens; i++) { + if ((tokens[i].type == TOKEN_COLON)) { // end of one input file + found_file = true; + } else if (i == num_tokens - 1) { // end of inputs, append token anyway + in_tokens += std::string(tokens[i].data); + found_file = true; + } else { + in_tokens += std::string(tokens[i].data); + } + if (found_file) { + const char* file_name = in_tokens.c_str(); + if (vtr::check_file_name_extension(file_name, ".xml")) { + try { + std::ifstream file(file_name); + void* context; + uxsd::load_vpr_constraints_xml(reader, context, file_name, file); + } catch (pugiutil::XmlError& e) { + vpr_throw(VPR_ERROR_ROUTE, file_name, e.line(), "%s", e.what()); + } + } else { + VTR_LOG_WARN( + "VPR constraints file '%s' may be in incorrect format. " + "Expecting .xml format. Not reading file.\n", + file_name); + } + in_tokens.clear(); + num_file_read++; + found_file = false; } - } else { - VTR_LOG_WARN( - "VPR constraints file '%s' may be in incorrect format. " - "Expecting .xml format. Not reading file.\n", - read_vpr_constraints_name); } + VTR_LOG("Read in '%d' constraint file(s) successfully.\n", num_file_read); //Update the floorplanning constraints in the floorplanning constraints context auto& floorplanning_ctx = g_vpr_ctx.mutable_floorplanning(); diff --git a/vpr/src/base/vpr_constraints_reader.h b/vpr/src/base/vpr_constraints_reader.h index 95fcc988607..60aefc25b5b 100644 --- a/vpr/src/base/vpr_constraints_reader.h +++ b/vpr/src/base/vpr_constraints_reader.h @@ -5,6 +5,6 @@ #ifndef VPR_CONSTRAINTS_READER_H_ #define VPR_CONSTRAINTS_READER_H_ -void load_vpr_constraints_file(const char* read_vpr_constraints_name); +void load_vpr_constraints_files(const char* read_vpr_constraints_name); #endif /* VPR_CONSTRAINTS_READER_H_ */ diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 80a54c0c47e..1583065d0ed 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2193,7 +2193,7 @@ bool is_node_on_tile(t_physical_tile_type_ptr physical_tile, } } -void apply_route_constraints(const VprConstraints& vpr_constraint) { +void apply_route_constraints(VprConstraints& vpr_constraint) { ClusteringContext& mutable_cluster_ctx = g_vpr_ctx.mutable_clustering(); for (auto net_id : mutable_cluster_ctx.clb_nlist.nets()) { std::string net_name = mutable_cluster_ctx.clb_nlist.net_name(net_id); diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 349c7cb2790..d2ba2eefd5c 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -193,6 +193,6 @@ bool is_node_on_tile(t_physical_tile_type_ptr physical_tile, // apply route constraints for route flow class VprConstraints; -void apply_route_constraints(const VprConstraints& constraint); +void apply_route_constraints(VprConstraints& constraint); #endif From 7a4150d1879388d7a59e6c565f2fd757e2d600cd Mon Sep 17 00:00:00 2001 From: Tao Li Date: Fri, 3 Mar 2023 00:09:01 -0800 Subject: [PATCH 118/453] Dev vpr constraint writer for route constrain. --- libs/libvtrutil/src/vtr_geometry.h | 14 ++++---- libs/libvtrutil/src/vtr_strong_id.h | 6 ++-- vpr/src/base/vpr_api.cpp | 3 ++ vpr/src/base/vpr_constraints.cpp | 1 + vpr/src/base/vpr_constraints_serializer.h | 16 ++++++--- vpr/src/base/vpr_constraints_writer.cpp | 44 +++++++++++++++++++++++ vpr/src/base/vpr_constraints_writer.h | 8 +++++ 7 files changed, 78 insertions(+), 14 deletions(-) diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 3685c308653..280d40dc7e8 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -71,13 +71,13 @@ class Point { T y() const; ///@brief == operator - friend bool operator== <>(Point lhs, Point rhs); + friend bool operator==<>(Point lhs, Point rhs); ///@brief != operator - friend bool operator!= <>(Point lhs, Point rhs); + friend bool operator!=<>(Point lhs, Point rhs); ///@brief < operator - friend bool operator< <>(Point lhs, Point rhs); + friend bool operator<<>(Point lhs, Point rhs); public: //Mutators ///@brief Set x and y values @@ -172,10 +172,10 @@ class Rect { bool empty() const; ///@brief == operator - friend bool operator== <>(const Rect& lhs, const Rect& rhs); + friend bool operator==<>(const Rect& lhs, const Rect& rhs); ///@brief != operator - friend bool operator!= <>(const Rect& lhs, const Rect& rhs); + friend bool operator!=<>(const Rect& lhs, const Rect& rhs); public: //Mutators ///@brief set xmin to a point @@ -296,10 +296,10 @@ class RectUnion { * * Note: does not check whether the representations they are equivalent */ - friend bool operator== <>(const RectUnion& lhs, const RectUnion& rhs); + friend bool operator==<>(const RectUnion& lhs, const RectUnion& rhs); ///@brief != operator - friend bool operator!= <>(const RectUnion& lhs, const RectUnion& rhs); + friend bool operator!=<>(const RectUnion& lhs, const RectUnion& rhs); private: // Note that a union of rectanges may have holes and may not be contiguous diff --git a/libs/libvtrutil/src/vtr_strong_id.h b/libs/libvtrutil/src/vtr_strong_id.h index 1ce922ab5da..1eb7523a6d2 100644 --- a/libs/libvtrutil/src/vtr_strong_id.h +++ b/libs/libvtrutil/src/vtr_strong_id.h @@ -202,11 +202,11 @@ class StrongId { * Note that since these are templated functions we provide an empty set of template parameters * after the function name (i.e. <>) */ - friend bool operator== <>(const StrongId& lhs, const StrongId& rhs); + friend bool operator==<>(const StrongId& lhs, const StrongId& rhs); ///@brief != operator - friend bool operator!= <>(const StrongId& lhs, const StrongId& rhs); + friend bool operator!=<>(const StrongId& lhs, const StrongId& rhs); ///@brief < operator - friend bool operator< <>(const StrongId& lhs, const StrongId& rhs); + friend bool operator<<>(const StrongId& lhs, const StrongId& rhs); private: T id_; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index e094bc25eb3..abcb68e1d8e 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -400,6 +400,9 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { vpr_analysis_flow(vpr_setup, arch, route_status, is_flat); } + // write out constratins + write_vpr_constraints(vpr_setup); + //close the graphics vpr_close_graphics(vpr_setup); diff --git a/vpr/src/base/vpr_constraints.cpp b/vpr/src/base/vpr_constraints.cpp index 4b9850be670..ae65dcf28e6 100644 --- a/vpr/src/base/vpr_constraints.cpp +++ b/vpr/src/base/vpr_constraints.cpp @@ -112,6 +112,7 @@ RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) con for (auto const& rc_itr : route_constraints_) { if (i == idx) { rc = rc_itr.second; + break; } } } diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index b57756f5c7a..bba5ee0f1d2 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -313,7 +313,8 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase */ virtual inline const char* get_set_global_signal_name(RouteConstraint& rc) final { - return rc.get_net_name().c_str(); + temp_name_string_ = rc.get_net_name(); + return temp_name_string_.c_str(); } virtual inline void set_set_global_signal_name(const char* name, void*& /*ctx*/) final { std::string net_name = std::string(name); @@ -321,14 +322,16 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase::max_digits10); + void* context; + uxsd::write_vpr_constraints_xml(writer, context, fp); + } else { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, + "Unknown extension on output %s", + file_name); + } + } + return; +} + void write_vpr_floorplan_constraints(const char* file_name, int expand, bool subtile, int horizontal_partitions, int vertical_partitions) { VprConstraints constraints; diff --git a/vpr/src/base/vpr_constraints_writer.h b/vpr/src/base/vpr_constraints_writer.h index 756f8c17c29..8ca7e9d58f8 100644 --- a/vpr/src/base/vpr_constraints_writer.h +++ b/vpr/src/base/vpr_constraints_writer.h @@ -25,6 +25,14 @@ #ifndef VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ #define VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ +/** + * @brief Write out vpr constratins to an XML file based on current placement and + * route constraint settings + * + * @param vpr_setup VPR setup information +*/ +void write_vpr_constraints(t_vpr_setup& vpr_setup); + /** * @brief Write out floorplan constraints to an XML file based on current placement * From ac6b2f4b573fcf948d5bbf9510f98794ec4a75e2 Mon Sep 17 00:00:00 2001 From: Tao Li Date: Fri, 3 Mar 2023 09:41:26 -0800 Subject: [PATCH 119/453] Revert un-wanted changes made by editor. --- libs/libvtrutil/src/vtr_geometry.h | 14 +++++++------- libs/libvtrutil/src/vtr_strong_id.h | 6 +++--- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 280d40dc7e8..3685c308653 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -71,13 +71,13 @@ class Point { T y() const; ///@brief == operator - friend bool operator==<>(Point lhs, Point rhs); + friend bool operator== <>(Point lhs, Point rhs); ///@brief != operator - friend bool operator!=<>(Point lhs, Point rhs); + friend bool operator!= <>(Point lhs, Point rhs); ///@brief < operator - friend bool operator<<>(Point lhs, Point rhs); + friend bool operator< <>(Point lhs, Point rhs); public: //Mutators ///@brief Set x and y values @@ -172,10 +172,10 @@ class Rect { bool empty() const; ///@brief == operator - friend bool operator==<>(const Rect& lhs, const Rect& rhs); + friend bool operator== <>(const Rect& lhs, const Rect& rhs); ///@brief != operator - friend bool operator!=<>(const Rect& lhs, const Rect& rhs); + friend bool operator!= <>(const Rect& lhs, const Rect& rhs); public: //Mutators ///@brief set xmin to a point @@ -296,10 +296,10 @@ class RectUnion { * * Note: does not check whether the representations they are equivalent */ - friend bool operator==<>(const RectUnion& lhs, const RectUnion& rhs); + friend bool operator== <>(const RectUnion& lhs, const RectUnion& rhs); ///@brief != operator - friend bool operator!=<>(const RectUnion& lhs, const RectUnion& rhs); + friend bool operator!= <>(const RectUnion& lhs, const RectUnion& rhs); private: // Note that a union of rectanges may have holes and may not be contiguous diff --git a/libs/libvtrutil/src/vtr_strong_id.h b/libs/libvtrutil/src/vtr_strong_id.h index 1eb7523a6d2..1ce922ab5da 100644 --- a/libs/libvtrutil/src/vtr_strong_id.h +++ b/libs/libvtrutil/src/vtr_strong_id.h @@ -202,11 +202,11 @@ class StrongId { * Note that since these are templated functions we provide an empty set of template parameters * after the function name (i.e. <>) */ - friend bool operator==<>(const StrongId& lhs, const StrongId& rhs); + friend bool operator== <>(const StrongId& lhs, const StrongId& rhs); ///@brief != operator - friend bool operator!=<>(const StrongId& lhs, const StrongId& rhs); + friend bool operator!= <>(const StrongId& lhs, const StrongId& rhs); ///@brief < operator - friend bool operator<<>(const StrongId& lhs, const StrongId& rhs); + friend bool operator< <>(const StrongId& lhs, const StrongId& rhs); private: T id_; From 60721ba4845910feb54e037206fe5566a42ddb0f Mon Sep 17 00:00:00 2001 From: Tao Li Date: Fri, 3 Mar 2023 14:37:22 -0800 Subject: [PATCH 120/453] Fix CLANG 6/7/10 compile issue. --- vpr/src/base/vpr_constraints_writer.cpp | 2 +- vpr/src/base/vpr_constraints_writer.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/base/vpr_constraints_writer.cpp b/vpr/src/base/vpr_constraints_writer.cpp index a962a2e8bce..d94cf7ffb1d 100644 --- a/vpr/src/base/vpr_constraints_writer.cpp +++ b/vpr/src/base/vpr_constraints_writer.cpp @@ -58,7 +58,7 @@ void write_vpr_constraints(t_vpr_setup& vpr_setup) { } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Unknown extension on output %s", - file_name); + file_name.c_str()); } } return; diff --git a/vpr/src/base/vpr_constraints_writer.h b/vpr/src/base/vpr_constraints_writer.h index 8ca7e9d58f8..158a87aa040 100644 --- a/vpr/src/base/vpr_constraints_writer.h +++ b/vpr/src/base/vpr_constraints_writer.h @@ -30,7 +30,7 @@ * route constraint settings * * @param vpr_setup VPR setup information -*/ + */ void write_vpr_constraints(t_vpr_setup& vpr_setup); /** From 5795b7df753903b215c1273cfe910113375f6aa8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 Mar 2023 16:49:13 -0800 Subject: [PATCH 121/453] [libs] add an invalidator to rrgraph builder so that we can modify the graph after build-up --- libs/librrgraph/src/base/rr_graph_builder.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 228a7e94b5c..eb447bdff8d 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -297,6 +297,9 @@ class RRGraphBuilder { return node_storage_.count_rr_switches(num_arch_switches, arch_switch_inf, arch_switch_fanins); } + /* Unlock storage; required to modify an routing resource graph after edge is read */ + inline void unlock_storage() { node_storage_.edges_read_ = false; } + /** @brief Reserve the lists of nodes, edges, switches etc. to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, * when adding a large number of nodes/edge/switches/segments, From 69d852d7e968e9033c9f26541fae6e96eca72e5d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 15:52:54 -0800 Subject: [PATCH 122/453] [core] debugging --- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- libs/librrgraph/src/base/rr_graph_storage.cpp | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index eb447bdff8d..02ff4409054 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -298,7 +298,7 @@ class RRGraphBuilder { } /* Unlock storage; required to modify an routing resource graph after edge is read */ - inline void unlock_storage() { node_storage_.edges_read_ = false; } + inline void unlock_storage() { node_storage_.edges_read_ = false; node_storage_.partitioned_ = false; } /** @brief Reserve the lists of nodes, edges, switches etc. to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index fdb5325489d..3cb20273e79 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -371,7 +371,10 @@ void t_rr_graph_storage::assign_first_edges() { bool t_rr_graph_storage::verify_first_edges() const { size_t num_edges = edge_src_node_.size(); - VTR_ASSERT(node_first_edge_[RRNodeId(node_storage_.size())] == RREdgeId(num_edges)); + if (node_first_edge_[RRNodeId(node_storage_.size())] != RREdgeId(num_edges)) { + VTR_LOG("node first edge is '%lu' while expected edge id is '%lu'\n", size_t(node_first_edge_[RRNodeId(node_storage_.size())]), num_edges); + VTR_ASSERT(node_first_edge_[RRNodeId(node_storage_.size())] == RREdgeId(num_edges)); + } // Each edge should belong with the edge range defined by // [node_first_edge_[src_node], node_first_edge_[src_node+1]). From 67a84e1f16296e77de9642ffa1929924acb87d6c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 16:06:34 -0800 Subject: [PATCH 123/453] [core] debugging --- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 02ff4409054..6932339dd79 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -298,7 +298,7 @@ class RRGraphBuilder { } /* Unlock storage; required to modify an routing resource graph after edge is read */ - inline void unlock_storage() { node_storage_.edges_read_ = false; node_storage_.partitioned_ = false; } + inline void unlock_storage() { node_storage_.edges_read_ = false; node_storage_.partitioned_ = false; node_storage_.node_first_edge_.clear();} /** @brief Reserve the lists of nodes, edges, switches etc. to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, From 8e623dc487f9ba671f65f5fe896daac62bda9952 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 16:35:52 -0800 Subject: [PATCH 124/453] [core] debugging --- libs/librrgraph/src/base/rr_graph_storage.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index bbd388a7779..105129b2b90 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -630,7 +630,7 @@ class t_rr_graph_storage { return side_tt[size_t(side)]; } - private: + public: friend struct edge_swapper; friend class edge_sort_iterator; friend class edge_compare_dest_node; From 1a9b9708bbbf7ddd8f4786a0b5afd5db5f1404eb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 21:43:36 -0800 Subject: [PATCH 125/453] [core] allow clock to be included optionally when building a gsb --- vpr/src/tileable_rr_graph/rr_graph_view_util.cpp | 8 ++++++-- vpr/src/tileable_rr_graph/rr_graph_view_util.h | 3 ++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 90dadea3964..f7b4c063cd6 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -91,7 +91,8 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const int& x, const int& y, const t_rr_type& rr_type, - const e_side& side) { + const e_side& side, + bool include_clock) { std::vector indices; VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); @@ -108,7 +109,10 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, for (int pin = 0; pin < device_grid[x][y].type->num_pins; ++pin) { /* Skip those pins have been ignored during rr_graph build-up */ if (true == device_grid[x][y].type->is_ignored_pin[pin]) { - continue; + /* If specified, force to include all the clock pins */ + if (!include_clock || std::find(device_grid[x][y].type->get_clock_pin_indeces().begin(), device_grid[x][y].type->get_clock_pin_indeces().end(), pin) != device_grid[x][y].type->get_clock_pin_indeces().end()) { + continue; + } } if (false == device_grid[x][y].type->pinloc[width_offset][height_offset][side][pin]) { /* Not the pin on this side, we skip */ diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.h b/vpr/src/tileable_rr_graph/rr_graph_view_util.h index 0834f34ef22..ec7d352aa49 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.h +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.h @@ -29,6 +29,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const int& x, const int& y, const t_rr_type& rr_type, - const e_side& side); + const e_side& side, + bool include_clock = false); #endif From 4199c48f319c2f68ec0703546fbc41c76cd20ace Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 21:48:49 -0800 Subject: [PATCH 126/453] [core] typo --- vpr/src/tileable_rr_graph/rr_graph_view_util.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index f7b4c063cd6..98a28e0acda 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -110,7 +110,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, /* Skip those pins have been ignored during rr_graph build-up */ if (true == device_grid[x][y].type->is_ignored_pin[pin]) { /* If specified, force to include all the clock pins */ - if (!include_clock || std::find(device_grid[x][y].type->get_clock_pin_indeces().begin(), device_grid[x][y].type->get_clock_pin_indeces().end(), pin) != device_grid[x][y].type->get_clock_pin_indeces().end()) { + if (!include_clock || std::find(device_grid[x][y].type->get_clock_pin_indices().begin(), device_grid[x][y].type->get_clock_pin_indeces().end(), pin) != device_grid[x][y].type->get_clock_pin_indeces().end()) { continue; } } From 2796b587a6a06a5dd509464081a4c278f128a297 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 21:49:28 -0800 Subject: [PATCH 127/453] [core] syntax --- vpr/src/tileable_rr_graph/rr_graph_view_util.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 98a28e0acda..d6c79685824 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -110,7 +110,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, /* Skip those pins have been ignored during rr_graph build-up */ if (true == device_grid[x][y].type->is_ignored_pin[pin]) { /* If specified, force to include all the clock pins */ - if (!include_clock || std::find(device_grid[x][y].type->get_clock_pin_indices().begin(), device_grid[x][y].type->get_clock_pin_indeces().end(), pin) != device_grid[x][y].type->get_clock_pin_indeces().end()) { + if (!include_clock || std::find(device_grid[x][y].type->get_clock_pin_indices().begin(), device_grid[x][y].type->get_clock_pin_indices().end(), pin) != device_grid[x][y].type->get_clock_pin_indices().end()) { continue; } } From ebb804ee3da336b555ecf7d95c88272bb0faa14a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 21:50:14 -0800 Subject: [PATCH 128/453] [core] debugging --- vpr/src/tileable_rr_graph/rr_graph_view_util.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index d6c79685824..fed488d5683 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -110,7 +110,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, /* Skip those pins have been ignored during rr_graph build-up */ if (true == device_grid[x][y].type->is_ignored_pin[pin]) { /* If specified, force to include all the clock pins */ - if (!include_clock || std::find(device_grid[x][y].type->get_clock_pin_indices().begin(), device_grid[x][y].type->get_clock_pin_indices().end(), pin) != device_grid[x][y].type->get_clock_pin_indices().end()) { + if (!include_clock || std::find(device_grid[x][y].type->get_clock_pins_indices().begin(), device_grid[x][y].type->get_clock_pins_indices().end(), pin) != device_grid[x][y].type->get_clock_pins_indices().end()) { continue; } } From 0f40ecba43479b0f830151adcecbf641fb2e9fe3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 21:56:15 -0800 Subject: [PATCH 129/453] [core] fixed a bug --- vpr/src/tileable_rr_graph/rr_graph_view_util.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index fed488d5683..66baf26a1f6 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -110,7 +110,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, /* Skip those pins have been ignored during rr_graph build-up */ if (true == device_grid[x][y].type->is_ignored_pin[pin]) { /* If specified, force to include all the clock pins */ - if (!include_clock || std::find(device_grid[x][y].type->get_clock_pins_indices().begin(), device_grid[x][y].type->get_clock_pins_indices().end(), pin) != device_grid[x][y].type->get_clock_pins_indices().end()) { + if (!include_clock || std::find(device_grid[x][y].type->get_clock_pins_indices().begin(), device_grid[x][y].type->get_clock_pins_indices().end(), pin) == device_grid[x][y].type->get_clock_pins_indices().end()) { continue; } } From fb90ee867de298fb7be53795d640bb4889ec7a3a Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Tue, 7 Mar 2023 18:41:51 -0800 Subject: [PATCH 130/453] Code clean up: fix memory leak issue. --- vpr/src/base/vpr_constraints_reader.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/base/vpr_constraints_reader.cpp b/vpr/src/base/vpr_constraints_reader.cpp index eec6d772490..1140e5269c6 100644 --- a/vpr/src/base/vpr_constraints_reader.cpp +++ b/vpr/src/base/vpr_constraints_reader.cpp @@ -54,6 +54,7 @@ void load_vpr_constraints_files(const char* read_vpr_constraints_name) { } } VTR_LOG("Read in '%d' constraint file(s) successfully.\n", num_file_read); + freeTokens(tokens, num_tokens); //Update the floorplanning constraints in the floorplanning constraints context auto& floorplanning_ctx = g_vpr_ctx.mutable_floorplanning(); From 89cc2e22091e99a9d4f401432e3ea6569b773c58 Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Tue, 7 Mar 2023 18:56:41 -0800 Subject: [PATCH 131/453] Fix the memory leak. --- vpr/src/base/vpr_constraints_reader.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/base/vpr_constraints_reader.cpp b/vpr/src/base/vpr_constraints_reader.cpp index eec6d772490..1140e5269c6 100644 --- a/vpr/src/base/vpr_constraints_reader.cpp +++ b/vpr/src/base/vpr_constraints_reader.cpp @@ -54,6 +54,7 @@ void load_vpr_constraints_files(const char* read_vpr_constraints_name) { } } VTR_LOG("Read in '%d' constraint file(s) successfully.\n", num_file_read); + freeTokens(tokens, num_tokens); //Update the floorplanning constraints in the floorplanning constraints context auto& floorplanning_ctx = g_vpr_ctx.mutable_floorplanning(); From 5119ac8621195ddc2288a4ca4a9e34a8743157cb Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Thu, 9 Mar 2023 16:09:17 -0800 Subject: [PATCH 132/453] add test. --- .../strong_vpr_constraint/config/config.txt | 28 +++++++++++++++++++ .../config/golden_results.txt | 2 ++ .../strong_vpr_constraint/route_constaint.xml | 6 ++++ .../route_constraint.xml | 6 ++++ .../vtr_reg_strong/task_list.txt | 1 + 5 files changed, 43 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constaint.xml create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt new file mode 100644 index 00000000000..62141e7a2ed --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt @@ -0,0 +1,28 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=bigkey.blif + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 +script_params_list_add = -read_vpr_constraints tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml:tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/route_constraint.xml --write_vpr_constraints vpr_constraints.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt new file mode 100644 index 00000000000..90f0ebd8dda --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt @@ -0,0 +1,2 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 7.06 vpr 72.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 149 229 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 74736 229 197 2152 2349 1 1011 575 16 16 256 io auto 35.6 MiB 2.58 8243 73.0 MiB 1.15 0.02 2.69979 -598.935 -2.69979 2.69979 0.04 0.00335255 0.00286435 0.318486 0.278508 -1 11385 11 1.05632e+07 8.03021e+06 4.24953e+06 16599.7 0.22 0.468953 0.419533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constaint.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constaint.xml new file mode 100644 index 00000000000..eb54291e557 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constaint.xml @@ -0,0 +1,6 @@ + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml new file mode 100644 index 00000000000..eb54291e557 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml @@ -0,0 +1,6 @@ + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 38a3f4409f9..900c1ab0c0b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -82,3 +82,4 @@ regression_tests/vtr_reg_strong/koios regression_tests/vtr_reg_strong/koios_no_complex_dsp regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail +regression_tests/vtr_reg_strong/strong_vpr_constraint From d501af232fc6fed1e7f0fcf4b61586df4fb2cf22 Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Fri, 10 Mar 2023 16:03:25 -0800 Subject: [PATCH 133/453] Update test. --- vtr_flow/benchmarks/microbenchmarks/and_clk.blif | 9 +++++++++ .../strong_vpr_constraint/config/config.txt | 11 +++++------ .../strong_vpr_constraint/floor_plan.xml | 9 +++++++++ .../strong_vpr_constraint/route_constaint.xml | 6 ------ .../strong_vpr_constraint/route_constraint.xml | 2 +- 5 files changed, 24 insertions(+), 13 deletions(-) create mode 100644 vtr_flow/benchmarks/microbenchmarks/and_clk.blif create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constaint.xml diff --git a/vtr_flow/benchmarks/microbenchmarks/and_clk.blif b/vtr_flow/benchmarks/microbenchmarks/and_clk.blif new file mode 100644 index 00000000000..a810fda32f6 --- /dev/null +++ b/vtr_flow/benchmarks/microbenchmarks/and_clk.blif @@ -0,0 +1,9 @@ +.model discrete_dffn +.inputs clk_ni d_i +.outputs d_o + +.names clk_ni int_clk_reg_exp_0 +0 1 +.subckt dffeas d=d_i q=d_o clk=int_clk_reg_exp_0 + +.end diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt index 62141e7a2ed..c714d686d4d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt @@ -3,16 +3,16 @@ ############################################## # Path to directory of circuits to use -circuits_dir=benchmarks/blif +circuits_dir=benchmarks/microbenchmarks # Path to directory of architectures to use -archs_dir=arch/timing +archs_dir=arch/titan # Add circuits to list to sweep -circuit_list_add=bigkey.blif +circuit_list_add=and_clk.blif # Add architectures to list to sweep -arch_list_add=k6_frac_N10_40nm.xml +arch_list_add=stratixiv_arch.timing.xml # Parse info and how to parse parse_file=vpr_standard.txt @@ -24,5 +24,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 -script_params_list_add = -read_vpr_constraints tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml:tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/route_constraint.xml --write_vpr_constraints vpr_constraints.xml +script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --read_vpr_constraints ../../../../floor_plan.xml:../../../../route_constraint.xml --write_vpr_constraints vpr_constraints.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml new file mode 100644 index 00000000000..507d4e14296 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constaint.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constaint.xml deleted file mode 100644 index eb54291e557..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constaint.xml +++ /dev/null @@ -1,6 +0,0 @@ - - - - - - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml index eb54291e557..53e293c579e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml @@ -1,6 +1,6 @@ - + From bcc1881a7703cb2d0220f02bfd7965a77532771e Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Fri, 10 Mar 2023 21:14:42 -0800 Subject: [PATCH 134/453] fix write constraint; update with simple test. --- vpr/src/base/vpr_constraints.cpp | 3 +- .../k4_frac_N4_fracff_localClkGen_40nm.xml | 635 ++++++++++++++++++ .../benchmarks/microbenchmarks/and_clk.blif | 5 +- .../strong_vpr_constraint/config/config.txt | 6 +- .../strong_vpr_constraint/floor_plan.xml | 2 +- .../route_constraint.xml | 9 +- 6 files changed, 650 insertions(+), 10 deletions(-) create mode 100644 vtr_flow/arch/timing/k4_frac_N4_fracff_localClkGen_40nm.xml diff --git a/vpr/src/base/vpr_constraints.cpp b/vpr/src/base/vpr_constraints.cpp index ae65dcf28e6..742cc014955 100644 --- a/vpr/src/base/vpr_constraints.cpp +++ b/vpr/src/base/vpr_constraints.cpp @@ -78,8 +78,9 @@ RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net // mark as invalid so write constraint function will not write constraint // of regexpr name - // instead a matched constraint is inerted in + // instead a matched constraint is inserted in constraint.second.set_is_valid(false); + rc.set_net_name(net_name); rc.set_is_valid(true); route_constraints_.insert({net_name, rc}); diff --git a/vtr_flow/arch/timing/k4_frac_N4_fracff_localClkGen_40nm.xml b/vtr_flow/arch/timing/k4_frac_N4_fracff_localClkGen_40nm.xml new file mode 100644 index 00000000000..6b027fe6a21 --- /dev/null +++ b/vtr_flow/arch/timing/k4_frac_N4_fracff_localClkGen_40nm.xml @@ -0,0 +1,635 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/benchmarks/microbenchmarks/and_clk.blif b/vtr_flow/benchmarks/microbenchmarks/and_clk.blif index a810fda32f6..3f31b82b8d7 100644 --- a/vtr_flow/benchmarks/microbenchmarks/and_clk.blif +++ b/vtr_flow/benchmarks/microbenchmarks/and_clk.blif @@ -1,9 +1,12 @@ + .model discrete_dffn .inputs clk_ni d_i .outputs d_o .names clk_ni int_clk_reg_exp_0 0 1 -.subckt dffeas d=d_i q=d_o clk=int_clk_reg_exp_0 + +.subckt dff D=d_i Q=d_o C=int_clk_reg_exp_0 .end + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt index c714d686d4d..a3ceed7c14d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt @@ -6,13 +6,13 @@ circuits_dir=benchmarks/microbenchmarks # Path to directory of architectures to use -archs_dir=arch/titan +archs_dir=arch/timing # Add circuits to list to sweep circuit_list_add=and_clk.blif # Add architectures to list to sweep -arch_list_add=stratixiv_arch.timing.xml +arch_list_add=k4_frac_N4_fracff_localClkGen_40nm.xml # Parse info and how to parse parse_file=vpr_standard.txt @@ -24,4 +24,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --read_vpr_constraints ../../../../floor_plan.xml:../../../../route_constraint.xml --write_vpr_constraints vpr_constraints.xml +script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --read_vpr_constraints ../../../../floor_plan.xml:../../../../route_constraint.xml --write_vpr_constraints vpr_constraints.xml --clock_modeling ideal diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml index 507d4e14296..861adf40966 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml @@ -2,7 +2,7 @@ - + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml index 53e293c579e..ca3d794706b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml @@ -1,6 +1,7 @@ - - - - + + + + + From 63b028d201507bb0dfa06350c1b0ea4b8095970b Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Sat, 11 Mar 2023 17:26:42 -0800 Subject: [PATCH 135/453] Update new test golden result. --- .../strong_vpr_constraint/config/golden_results.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt index 90f0ebd8dda..76b5c59b6fa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 7.06 vpr 72.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 149 229 -1 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 74736 229 197 2152 2349 1 1011 575 16 16 256 io auto 35.6 MiB 2.58 8243 73.0 MiB 1.15 0.02 2.69979 -598.935 -2.69979 2.69979 0.04 0.00335255 0.00286435 0.318486 0.278508 -1 11385 11 1.05632e+07 8.03021e+06 4.24953e+06 16599.7 0.22 0.468953 0.419533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 1.13 vpr 199.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success d501af232-dirty debug VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-10T20:33:07 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 204100 2 1 4 5 1 4 5 4 4 16 clb auto 59.9 MiB 0.02 11 198.0 MiB 0.01 0.00 1.13498 -1.13498 -1.13498 1.13498 0.03 0.000154368 0.000127356 0.00093834 0.000650842 -1 8 1 215576 107788 120301. 7518.81 0.01 0.00241288 0.00171572 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From f3b42d289e476d387e4f7f04bd2b20d2c9156754 Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Sat, 11 Mar 2023 20:42:42 -0800 Subject: [PATCH 136/453] update document. --- doc/src/vpr/command_line_usage.rst | 6 ++--- doc/src/vpr/route_constraints.rst | 39 ++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 3 deletions(-) create mode 100644 doc/src/vpr/route_constraints.rst diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index f589969d8ef..6ce335eb15a 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -358,13 +358,13 @@ Use the options below to override this default naming behaviour. .. seealso:: :ref:`Routing Resource XML File `. -.. option:: --read_vpr_constraints +.. option:: --read_vpr_constraints ::...: - Reads the :ref:`floorplanning constraints ` that packing and placement must respect from the specified XML file. + Reads the :ref:`floorplanning constraints ` that packing and placement must respect from the specified XML file; and/or reads the :ref:`global route constraints ` that router must respect from the specified XML file. Multiple files are allowed and should be seperated with a colomn char. .. option:: --write_vpr_constraints - Writes out new :ref:`floorplanning constraints ` based on current placement to the specified XML file. + Writes out new :ref:`floorplanning constraints ` based on current placement to the specified XML file; and/or writes out new :ref:`global route constraints ` based on current global routecounstraints to the specified XML file. Note that a single combined file is written to even there are multiple input constraint files read in. .. option:: --read_router_lookahead diff --git a/doc/src/vpr/route_constraints.rst b/doc/src/vpr/route_constraints.rst new file mode 100644 index 00000000000..484e90f2574 --- /dev/null +++ b/doc/src/vpr/route_constraints.rst @@ -0,0 +1,39 @@ + +VPR Placement Constraints +========================= +.. _vpr_constraints_file: +VPR supports running flows with route constraints. Route constraints are set on global signals to specify if they should be routed or not. For example, a user may want to route a specific internal clock even clock modeling option is set to not route it. + +The route constraints should be specified by the user using an XML constraints file format, as described in the section below. + +A Constraints File Example +-------------------------- + +.. code-block:: xml + :caption: An example of a route constraints file in XML format. + :linenos: + + + + + + + + + +.. _end: + +Constraints File Format +----------------------- + +VPR has a specific XML format which must be used when creating a route constraints file. The purpose of this constraints file is to specify + +#. The signals that should be constrained for routing +#. The route model for such signals + +The file is passed as an input to VPR when running with route constraints. When the file is read in, its information is used to guide VPR route or not route such signals. + +.. note:: Use the VPR option :vpr:option:`--read_vpr_constraints` to specify the VPR route constraints file that is to be loaded. + +.. note:: Wildcard names of signals are supported to specify a list of signals. The wildcard expression should follow the C/C++ regexpr rule. + From 0dbd6851f523c2641ca112913366ac1b19fc31aa Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Mon, 13 Mar 2023 19:53:36 -0700 Subject: [PATCH 137/453] update golden results. --- .../strong_vpr_constraint/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt index 76b5c59b6fa..9e3589ac487 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 1.13 vpr 199.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success d501af232-dirty debug VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-10T20:33:07 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 204100 2 1 4 5 1 4 5 4 4 16 clb auto 59.9 MiB 0.02 11 198.0 MiB 0.01 0.00 1.13498 -1.13498 -1.13498 1.13498 0.03 0.000154368 0.000127356 0.00093834 0.000650842 -1 8 1 215576 107788 120301. 7518.81 0.01 0.00241288 0.00171572 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 1.19 vpr 198.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success d501af232-dirty debug VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-10T20:33:07 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 203636 2 1 4 5 1 4 5 4 4 16 clb auto 59.1 MiB 0.02 11 197.6 MiB 0.01 0.00 1.13498 -1.13498 -1.13498 1.13498 0.03 0.000154861 0.00012795 0.000938791 0.000647688 -1 8 1 215576 107788 120301. 7518.81 0.01 0.00242291 0.00172363 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From 71db0a4f9e632e0e493af0b008ee8ce8b78b5529 Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Tue, 14 Mar 2023 14:18:28 -0700 Subject: [PATCH 138/453] update golden result from release build. --- .../strong_vpr_constraint/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt index 9e3589ac487..359030d6c0d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 1.19 vpr 198.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success d501af232-dirty debug VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-10T20:33:07 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 203636 2 1 4 5 1 4 5 4 4 16 clb auto 59.1 MiB 0.02 11 197.6 MiB 0.01 0.00 1.13498 -1.13498 -1.13498 1.13498 0.03 0.000154861 0.00012795 0.000938791 0.000647688 -1 8 1 215576 107788 120301. 7518.81 0.01 0.00242291 0.00172363 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 0.67 vpr 186.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 0dbd6851f release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-14T11:14:58 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 191344 2 1 4 5 1 4 5 4 4 16 clb auto 45.8 MiB 0.01 11 185.3 MiB 0.00 0.00 1.13498 -1.13498 -1.13498 1.13498 0.01 6.4456e-05 6.0907e-05 0.000407814 0.00028842 -1 8 1 215576 107788 120301. 7518.81 0.00 0.000999195 0.000686301 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From bd59994063664ed21c4816636bb0195cb2d34083 Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Thu, 16 Mar 2023 21:50:04 -0700 Subject: [PATCH 139/453] update golden. --- .../strong_vpr_constraint/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt index 359030d6c0d..243f67c8e75 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 0.67 vpr 186.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 0dbd6851f release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-14T11:14:58 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 191344 2 1 4 5 1 4 5 4 4 16 clb auto 45.8 MiB 0.01 11 185.3 MiB 0.00 0.00 1.13498 -1.13498 -1.13498 1.13498 0.01 6.4456e-05 6.0907e-05 0.000407814 0.00028842 -1 8 1 215576 107788 120301. 7518.81 0.00 0.000999195 0.000686301 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 0.67 vpr 186.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 0dbd6851f release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-14T11:14:58 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 61038 2 1 4 5 1 4 5 4 4 16 clb auto 45.8 MiB 0.01 11 185.3 MiB 0.00 0.00 1.13498 -1.13498 -1.13498 1.13498 0.01 6.4456e-05 6.0907e-05 0.000407814 0.00028842 -1 8 1 215576 107788 120301. 7518.81 0.00 0.000999195 0.000686301 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From 8593cb5cb40cc65fc36fea97f552648b05ee255b Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Fri, 17 Mar 2023 18:11:14 -0700 Subject: [PATCH 140/453] update golden result with deep-cleaned build. --- .../strong_vpr_constraint/config/golden_results.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt index 243f67c8e75..1de222ff286 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 0.67 vpr 186.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 0dbd6851f release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-14T11:14:58 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 61038 2 1 4 5 1 4 5 4 4 16 clb auto 45.8 MiB 0.01 11 185.3 MiB 0.00 0.00 1.13498 -1.13498 -1.13498 1.13498 0.01 6.4456e-05 6.0907e-05 0.000407814 0.00028842 -1 8 1 215576 107788 120301. 7518.81 0.00 0.000999195 0.000686301 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 0.07 vpr 46.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success bd5999406-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-17T17:48:18 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 48016 2 1 4 5 1 4 5 4 4 16 clb auto 7.9 MiB 0.00 11 46.9 MiB 0.00 0.00 1.13498 -1.13498 -1.13498 1.13498 0.00 3.031e-06 1.541e-06 3.5814e-05 2.5748e-05 -1 8 1 215576 107788 120301. 7518.81 0.00 0.00010342 7.9026e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From 294c49ba167ee439ada0c8efd59f466e4c977dbf Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Wed, 22 Mar 2023 15:13:25 -0700 Subject: [PATCH 141/453] clean up code based on review comments. --- doc/src/vpr/route_constraints.rst | 7 ++++- vpr/src/base/route_constraint.cpp | 8 +++--- vpr/src/base/route_constraint.h | 8 +++--- vpr/src/base/vpr_constraints.cpp | 32 +++++++++++------------ vpr/src/base/vpr_constraints.h | 4 +-- vpr/src/base/vpr_constraints_serializer.h | 6 ++--- vpr/src/base/vpr_constraints_writer.cpp | 2 +- vpr/src/util/vpr_utils.cpp | 6 ++--- 8 files changed, 38 insertions(+), 35 deletions(-) diff --git a/doc/src/vpr/route_constraints.rst b/doc/src/vpr/route_constraints.rst index 484e90f2574..fe921cd5a23 100644 --- a/doc/src/vpr/route_constraints.rst +++ b/doc/src/vpr/route_constraints.rst @@ -1,9 +1,11 @@ -VPR Placement Constraints +VPR Route Constraints ========================= .. _vpr_constraints_file: VPR supports running flows with route constraints. Route constraints are set on global signals to specify if they should be routed or not. For example, a user may want to route a specific internal clock even clock modeling option is set to not route it. +.. note:: The constraint specified in this file overrides the setting of option "--clock_modeling" if it is specified. A message will be issued in such case: "Route constraint(s) detected and will override clock modeling setting". + The route constraints should be specified by the user using an XML constraints file format, as described in the section below. A Constraints File Example @@ -18,11 +20,14 @@ A Constraints File Example + .. _end: +.. note:: The "route_model" in constraint specified in this file only support "ideal" and "route" only. + Constraints File Format ----------------------- diff --git a/vpr/src/base/route_constraint.cpp b/vpr/src/base/route_constraint.cpp index a7dadc3a1ec..4ed76deb108 100644 --- a/vpr/src/base/route_constraint.cpp +++ b/vpr/src/base/route_constraint.cpp @@ -12,7 +12,7 @@ void RouteConstraint::set_net_name(std::string name) { return; } -std::string RouteConstraint::get_net_name() const { +std::string RouteConstraint::net_name() const { return net_name_; } @@ -21,7 +21,7 @@ void RouteConstraint::set_net_type(std::string type) { return; } -std::string RouteConstraint::get_net_type() const { +std::string RouteConstraint::net_type() const { return net_type_; } @@ -30,7 +30,7 @@ void RouteConstraint::set_route_model(std::string route_method) { return; } -std::string RouteConstraint::get_route_model() const { +std::string RouteConstraint::route_model() const { return route_method_; } @@ -38,6 +38,6 @@ void RouteConstraint::set_is_valid(bool value) { is_valid_ = value; } -bool RouteConstraint::get_is_valid() const { +bool RouteConstraint::is_valid() const { return is_valid_; } diff --git a/vpr/src/base/route_constraint.h b/vpr/src/base/route_constraint.h index 50b967e3f31..58b2839d060 100644 --- a/vpr/src/base/route_constraint.h +++ b/vpr/src/base/route_constraint.h @@ -18,7 +18,7 @@ class RouteConstraint { /** * @brief get net name */ - std::string get_net_name() const; + std::string net_name() const; /** * @brief set net name @@ -28,7 +28,7 @@ class RouteConstraint { /** * @brief get net type */ - std::string get_net_type() const; + std::string net_type() const; /** * @brief set net type @@ -38,7 +38,7 @@ class RouteConstraint { /** * @brief get route model */ - std::string get_route_model() const; + std::string route_model() const; /** * @brief set route model @@ -53,7 +53,7 @@ class RouteConstraint { /** * @brief get is valid */ - bool get_is_valid() const; + bool is_valid() const; private: std::string net_name_; diff --git a/vpr/src/base/vpr_constraints.cpp b/vpr/src/base/vpr_constraints.cpp index 742cc014955..64dcfd310c8 100644 --- a/vpr/src/base/vpr_constraints.cpp +++ b/vpr/src/base/vpr_constraints.cpp @@ -61,11 +61,11 @@ PartitionRegion VprConstraints::get_partition_pr(PartitionId part_id) { } void VprConstraints::add_route_constraint(RouteConstraint rc) { - route_constraints_.insert({rc.get_net_name(), rc}); + route_constraints_.insert({rc.net_name(), rc}); return; } -RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) { +const RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) { RouteConstraint rc; auto const& rc_itr = route_constraints_.find(net_name); if (rc_itr == route_constraints_.end()) { @@ -73,20 +73,18 @@ RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net bool found_thru_regex = false; for (auto constraint : route_constraints_) { if (std::regex_match(net_name, std::regex(constraint.first))) { - { - rc = constraint.second; - - // mark as invalid so write constraint function will not write constraint - // of regexpr name - // instead a matched constraint is inserted in - constraint.second.set_is_valid(false); - rc.set_net_name(net_name); - rc.set_is_valid(true); - route_constraints_.insert({net_name, rc}); - - found_thru_regex = true; - break; - } + rc = constraint.second; + + // mark as invalid so write constraint function will not write constraint + // of regexpr name + // instead a matched constraint is inserted in + constraint.second.set_is_valid(false); + rc.set_net_name(net_name); + rc.set_is_valid(true); + route_constraints_.insert({net_name, rc}); + + found_thru_regex = true; + break; } } if (!found_thru_regex) { @@ -101,7 +99,7 @@ RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net return rc; } -RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) const { +const RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) const { RouteConstraint rc; if ((route_constraints_.size() == 0) || (idx > route_constraints_.size() - 1)) { rc.set_net_name("INVALID"); diff --git a/vpr/src/base/vpr_constraints.h b/vpr/src/base/vpr_constraints.h index 61d7ed9d6b6..f9343267a9e 100644 --- a/vpr/src/base/vpr_constraints.h +++ b/vpr/src/base/vpr_constraints.h @@ -100,14 +100,14 @@ class VprConstraints { * * @param index the constraint index */ - RouteConstraint get_route_constraint_by_idx(std::size_t index) const; + const RouteConstraint get_route_constraint_by_idx(std::size_t index) const; /** * @brief returns route constraint of a specific net * * @param net_name the net name */ - RouteConstraint get_route_constraint_by_net_name(std::string net_name); + const RouteConstraint get_route_constraint_by_net_name(std::string net_name); /** * @brief returns number of route constraints diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index bba5ee0f1d2..77f8184cbc1 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -313,7 +313,7 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase */ virtual inline const char* get_set_global_signal_name(RouteConstraint& rc) final { - temp_name_string_ = rc.get_net_name(); + temp_name_string_ = rc.net_name(); return temp_name_string_.c_str(); } virtual inline void set_set_global_signal_name(const char* name, void*& /*ctx*/) final { @@ -322,7 +322,7 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase Date: Thu, 23 Mar 2023 18:02:53 -0700 Subject: [PATCH 142/453] support route constraints. --- vpr/src/base/route_constraint.cpp | 8 +-- vpr/src/base/route_constraint.h | 8 +-- vpr/src/base/vpr_api.cpp | 7 +- vpr/src/base/vpr_constraints.cpp | 32 ++++----- vpr/src/base/vpr_constraints.h | 4 +- vpr/src/base/vpr_constraints_serializer.h | 16 +++-- vpr/src/base/vpr_constraints_writer.cpp | 70 ++++++++++++------- vpr/src/base/vpr_constraints_writer.h | 10 ++- vpr/src/util/vpr_utils.cpp | 4 +- .../vtr_reg_strong/task_list.txt | 2 + 10 files changed, 95 insertions(+), 66 deletions(-) diff --git a/vpr/src/base/route_constraint.cpp b/vpr/src/base/route_constraint.cpp index a7dadc3a1ec..4ed76deb108 100644 --- a/vpr/src/base/route_constraint.cpp +++ b/vpr/src/base/route_constraint.cpp @@ -12,7 +12,7 @@ void RouteConstraint::set_net_name(std::string name) { return; } -std::string RouteConstraint::get_net_name() const { +std::string RouteConstraint::net_name() const { return net_name_; } @@ -21,7 +21,7 @@ void RouteConstraint::set_net_type(std::string type) { return; } -std::string RouteConstraint::get_net_type() const { +std::string RouteConstraint::net_type() const { return net_type_; } @@ -30,7 +30,7 @@ void RouteConstraint::set_route_model(std::string route_method) { return; } -std::string RouteConstraint::get_route_model() const { +std::string RouteConstraint::route_model() const { return route_method_; } @@ -38,6 +38,6 @@ void RouteConstraint::set_is_valid(bool value) { is_valid_ = value; } -bool RouteConstraint::get_is_valid() const { +bool RouteConstraint::is_valid() const { return is_valid_; } diff --git a/vpr/src/base/route_constraint.h b/vpr/src/base/route_constraint.h index 50b967e3f31..58b2839d060 100644 --- a/vpr/src/base/route_constraint.h +++ b/vpr/src/base/route_constraint.h @@ -18,7 +18,7 @@ class RouteConstraint { /** * @brief get net name */ - std::string get_net_name() const; + std::string net_name() const; /** * @brief set net name @@ -28,7 +28,7 @@ class RouteConstraint { /** * @brief get net type */ - std::string get_net_type() const; + std::string net_type() const; /** * @brief set net type @@ -38,7 +38,7 @@ class RouteConstraint { /** * @brief get route model */ - std::string get_route_model() const; + std::string route_model() const; /** * @brief set route model @@ -53,7 +53,7 @@ class RouteConstraint { /** * @brief get is valid */ - bool get_is_valid() const; + bool is_valid() const; private: std::string net_name_; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index f8e481f3a24..2c79268a44a 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -701,7 +701,7 @@ bool vpr_place_flow(t_vpr_setup& vpr_setup, const t_arch& arch) { //Write out a vpr floorplanning constraints file if the option is specified if (!filename_opts.write_vpr_constraints_file.empty()) { - write_vpr_floorplan_constraints("vpr_floorplan_constraints.xml" /*filename_opts.write_vpr_constraints_file.c_str()*/, placer_opts.place_constraint_expand, placer_opts.place_constraint_subtile, + write_vpr_floorplan_constraints(filename_opts.write_vpr_constraints_file.c_str(), placer_opts.place_constraint_expand, placer_opts.place_constraint_subtile, placer_opts.floorplan_num_horizontal_partitions, placer_opts.floorplan_num_vertical_partitions); } @@ -857,11 +857,6 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_f //Update interactive graphics update_screen(ScreenUpdatePriority::MAJOR, graphics_msg.c_str(), ROUTING, timing_info); - - //Write out a vpr floorplanning constraints file if the option is specified - if (!filename_opts.write_vpr_constraints_file.empty()) { - write_vpr_route_constraints(g_vpr_ctx.routing().constraints, "vpr_route_constraints.xml" /*filename_opts.write_vpr_constraints_file.c_str()*/); - } } return route_status; diff --git a/vpr/src/base/vpr_constraints.cpp b/vpr/src/base/vpr_constraints.cpp index 4b9850be670..64dcfd310c8 100644 --- a/vpr/src/base/vpr_constraints.cpp +++ b/vpr/src/base/vpr_constraints.cpp @@ -61,11 +61,11 @@ PartitionRegion VprConstraints::get_partition_pr(PartitionId part_id) { } void VprConstraints::add_route_constraint(RouteConstraint rc) { - route_constraints_.insert({rc.get_net_name(), rc}); + route_constraints_.insert({rc.net_name(), rc}); return; } -RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) { +const RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net_name) { RouteConstraint rc; auto const& rc_itr = route_constraints_.find(net_name); if (rc_itr == route_constraints_.end()) { @@ -73,19 +73,18 @@ RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net bool found_thru_regex = false; for (auto constraint : route_constraints_) { if (std::regex_match(net_name, std::regex(constraint.first))) { - { - rc = constraint.second; - - // mark as invalid so write constraint function will not write constraint - // of regexpr name - // instead a matched constraint is inerted in - constraint.second.set_is_valid(false); - rc.set_is_valid(true); - route_constraints_.insert({net_name, rc}); - - found_thru_regex = true; - break; - } + rc = constraint.second; + + // mark as invalid so write constraint function will not write constraint + // of regexpr name + // instead a matched constraint is inserted in + constraint.second.set_is_valid(false); + rc.set_net_name(net_name); + rc.set_is_valid(true); + route_constraints_.insert({net_name, rc}); + + found_thru_regex = true; + break; } } if (!found_thru_regex) { @@ -100,7 +99,7 @@ RouteConstraint VprConstraints::get_route_constraint_by_net_name(std::string net return rc; } -RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) const { +const RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) const { RouteConstraint rc; if ((route_constraints_.size() == 0) || (idx > route_constraints_.size() - 1)) { rc.set_net_name("INVALID"); @@ -112,6 +111,7 @@ RouteConstraint VprConstraints::get_route_constraint_by_idx(std::size_t idx) con for (auto const& rc_itr : route_constraints_) { if (i == idx) { rc = rc_itr.second; + break; } } } diff --git a/vpr/src/base/vpr_constraints.h b/vpr/src/base/vpr_constraints.h index 61d7ed9d6b6..f9343267a9e 100644 --- a/vpr/src/base/vpr_constraints.h +++ b/vpr/src/base/vpr_constraints.h @@ -100,14 +100,14 @@ class VprConstraints { * * @param index the constraint index */ - RouteConstraint get_route_constraint_by_idx(std::size_t index) const; + const RouteConstraint get_route_constraint_by_idx(std::size_t index) const; /** * @brief returns route constraint of a specific net * * @param net_name the net name */ - RouteConstraint get_route_constraint_by_net_name(std::string net_name); + const RouteConstraint get_route_constraint_by_net_name(std::string net_name); /** * @brief returns number of route constraints diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index b57756f5c7a..77f8184cbc1 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -313,7 +313,8 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase */ virtual inline const char* get_set_global_signal_name(RouteConstraint& rc) final { - return rc.get_net_name().c_str(); + temp_name_string_ = rc.net_name(); + return temp_name_string_.c_str(); } virtual inline void set_set_global_signal_name(const char* name, void*& /*ctx*/) final { std::string net_name = std::string(name); @@ -321,14 +322,16 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase::max_digits10); + void* context; + uxsd::write_vpr_constraints_xml(writer, context, fp); + } else { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, + "Unknown extension on output %s", + file_name.c_str()); + } + } + return; +} + void write_vpr_floorplan_constraints(const char* file_name, int expand, bool subtile, int horizontal_partitions, int vertical_partitions) { VprConstraints constraints; @@ -214,29 +258,3 @@ void create_partition(Partition& part, std::string part_name, int xmin, int ymin part_pr.set_partition_region(part_regions); part.set_part_region(part_pr); } - -void write_vpr_route_constraints(const VprConstraints& constraints, const char* file_name) { - VprConstraints write_constraints; - for (int i = 0; i < constraints.get_route_constraint_num(); i++) { - RouteConstraint rc = constraints.get_route_constraint_by_idx(i); - if (rc.get_is_valid()) { - write_constraints.add_route_constraint(rc); - } - } - - VprConstraintsSerializer writer(write_constraints); - - if (vtr::check_file_name_extension(file_name, ".xml")) { - std::fstream fp; - fp.open(file_name, std::fstream::out | std::fstream::trunc); - fp.precision(std::numeric_limits::max_digits10); - void* context; - uxsd::write_vpr_constraints_xml(writer, context, fp); - } else { - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, - "Unknown extension on output %s", - file_name); - } - - return; -} diff --git a/vpr/src/base/vpr_constraints_writer.h b/vpr/src/base/vpr_constraints_writer.h index caac1abd85b..158a87aa040 100644 --- a/vpr/src/base/vpr_constraints_writer.h +++ b/vpr/src/base/vpr_constraints_writer.h @@ -25,6 +25,14 @@ #ifndef VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ #define VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ +/** + * @brief Write out vpr constratins to an XML file based on current placement and + * route constraint settings + * + * @param vpr_setup VPR setup information + */ +void write_vpr_constraints(t_vpr_setup& vpr_setup); + /** * @brief Write out floorplan constraints to an XML file based on current placement * @@ -47,6 +55,4 @@ void setup_vpr_floorplan_constraints_cutpoints(VprConstraints& constraints, int void create_partition(Partition& part, std::string part_name, int xmin, int ymin, int xmax, int ymax); -void write_vpr_route_constraints(const VprConstraints& constraints, const char* file_name); - #endif /* VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ */ diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 1583065d0ed..8288cb1d8c5 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2198,9 +2198,9 @@ void apply_route_constraints(VprConstraints& vpr_constraint) { for (auto net_id : mutable_cluster_ctx.clb_nlist.nets()) { std::string net_name = mutable_cluster_ctx.clb_nlist.net_name(net_id); RouteConstraint rc = vpr_constraint.get_route_constraint_by_net_name(net_name); - if (rc.get_is_valid()) { + if (rc.is_valid()) { mutable_cluster_ctx.clb_nlist.set_net_is_global(net_id, true); - if (rc.get_route_model() == "route") { + if (rc.route_model() == "route") { mutable_cluster_ctx.clb_nlist.set_net_is_ignored(net_id, false); } else { mutable_cluster_ctx.clb_nlist.set_net_is_ignored(net_id, true); diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 53c065e2338..3c16003523d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -1,3 +1,4 @@ +regression_tests/vtr_reg_strong/koios regression_tests/vtr_reg_strong/strong_absorb_buffers regression_tests/vtr_reg_strong/strong_analysis_only regression_tests/vtr_reg_strong/strong_analytic_placer @@ -83,3 +84,4 @@ regression_tests/vtr_reg_strong/koios_no_complex_dsp regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail regression_tests/vtr_reg_strong/strong_tileable_rr_graph +regression_tests/vtr_reg_strong/strong_vpr_constraint From 4c43c7486b77e30b40577465a2d611211e3ff635 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 14 Apr 2023 19:51:43 -0700 Subject: [PATCH 143/453] [core] resovle mering conflicts which causes compilation failures --- libs/librrgraph/src/base/rr_graph_builder.cpp | 2 -- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- vpr/src/route/router_lookahead_map.cpp | 4 ++- vpr/src/route/rr_graph.cpp | 32 ++++--------------- vpr/src/route/rr_graph.h | 11 +++++-- .../tileable_rr_graph_builder.cpp | 16 +++++----- 6 files changed, 28 insertions(+), 39 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index a5b0c3cd13b..e1b24083159 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -103,9 +103,7 @@ void RRGraphBuilder::clear() { node_ptc_nums_.clear(); rr_node_metadata_.clear(); rr_edge_metadata_.clear(); - segment_ids_.clear(); rr_segments_.clear(); - switch_ids_.clear(); rr_switch_inf_.clear(); edges_to_build_.clear(); is_edge_dirty_ = true; diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 7ccc04815e5..089a0c393da 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -296,7 +296,7 @@ class RRGraphBuilder { } /* Unlock storage; required to modify an routing resource graph after edge is read */ - inline void unlock_storage() { node_storage_.edges_read_ = false; node_storage_.partitioned_ = false; node_storage_.node_first_edge_.clear();} + inline void unlock_storage() { node_storage_.edges_read_ = false; node_storage_.partitioned_ = false; node_storage_.clear_node_first_edge();} /** @brief Reserve the lists of nodes, edges, switches etc. to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 9836e7cfb91..7f86e6352a0 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -1350,7 +1350,9 @@ static void compute_tile_lookahead(std::unordered_map>& switch_fanin_remap, - const std::map arch_sw_inf, - const float R_minW_nmos, - const float R_minW_pmos, - const int wire_to_arch_ipin_switch, - int* wire_to_rr_ipin_switch); - static void remap_rr_node_switch_indices(RRGraphBuilder& rr_graph_builder, const t_arch_switch_fanin& switch_fanin); @@ -451,16 +443,6 @@ static void alloc_rr_switch_inf(RRGraphBuilder& rr_graph_builder, static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, int* num_seg_details = nullptr); -static std::vector> alloc_and_load_actual_fc(const std::vector& types, - const int max_pins, - const std::vector& segment_inf, - const int* sets_per_seg_type, - const t_chan_width* nodes_per_chan, - const e_fc_type fc_type, - const enum e_directionality directionality, - bool* Fc_clipped, - bool is_flat); - static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_graph, RRNodeId from_rr, const std::vector& candidate_rr_nodes); @@ -1417,13 +1399,13 @@ void build_tile_rr_graph(RRGraphBuilder& rr_graph_builder, * and count how many different fan-ins exist for each arch switch. * Then we create these rr switches and update the switch indices * of rr_nodes to index into the rr_switch_inf array. */ -static void alloc_and_load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, - std::vector>& switch_fanin_remap, - const std::map arch_sw_inf, - const float R_minW_nmos, - const float R_minW_pmos, - const int wire_to_arch_ipin_switch, - int* wire_to_rr_ipin_switch) { +void alloc_and_load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, + std::vector>& switch_fanin_remap, + const std::map arch_sw_inf, + const float R_minW_nmos, + const float R_minW_pmos, + const int wire_to_arch_ipin_switch, + int* wire_to_rr_ipin_switch) { /* we will potentially be creating a couple of versions of each arch switch where * each version corresponds to a different fan-in. We will need to fill device_ctx.rr_switch_inf * with this expanded list of switches. diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index 72a662f324f..0b49e71b218 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -46,7 +46,13 @@ t_rr_switch_inf create_rr_switch_from_arch_switch(const t_arch_switch_inf& arch_ const float R_minW_nmos, const float R_minW_pmos); -void alloc_and_load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const int wire_to_arch_ipin_switch, int* wire_to_rr_ipin_switch); +void alloc_and_load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, + std::vector>& switch_fanin_remap, + const std::map arch_sw_inf, + const float R_minW_nmos, + const float R_minW_pmos, + const int wire_to_arch_ipin_switch, + int* wire_to_rr_ipin_switch); void rr_graph_externals(const std::vector& segment_inf, const std::vector& segment_inf_x, @@ -63,7 +69,8 @@ std::vector> alloc_and_load_actual_fc(const std::vector& typ RRSwitchId wire_to_ipin_rr_switch = RRSwitchId::INVALID(); RRSwitchId delayless_rr_switch = RRSwitchId::INVALID(); - device_ctx.rr_graph_builder.reserve_switches(device_ctx.num_arch_switches); + device_ctx.rr_graph_builder.reserve_switches(device_ctx.arch_switch_inf.size()); /* Create the switches */ - for (int iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) { - const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(iswitch, R_minW_nmos, R_minW_pmos); + for (size_t iswitch = 0; iswitch < device_ctx.arch_switch_inf.size(); ++iswitch) { + const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(device_ctx.arch_switch_inf[iswitch], R_minW_nmos, R_minW_pmos); RRSwitchId rr_switch = device_ctx.rr_graph_builder.add_rr_switch(temp_rr_switch); - if (iswitch == wire_to_arch_ipin_switch) { + if ((int)iswitch == wire_to_arch_ipin_switch) { wire_to_ipin_rr_switch = rr_switch; } - if (iswitch == delayless_switch) { + if ((int)iswitch == delayless_switch) { delayless_rr_switch = rr_switch; } } @@ -207,7 +207,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* [0..num_types-1][0..num_pins-1] */ std::vector> Fc_in; Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*)&chan_width, - e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped); + e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped, false); if (Fc_clipped) { *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; } @@ -216,7 +216,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* [0..num_types-1][0..num_pins-1] */ std::vector> Fc_out; Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*)&chan_width, - e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped); + e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped, false); if (Fc_clipped) { *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; @@ -263,7 +263,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ device_ctx.rr_graph_builder.init_fan_in(); - alloc_and_load_rr_switch_inf(device_ctx.num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); + alloc_and_load_rr_switch_inf(device_ctx.rr_graph_builder, device_ctx.switch_fanin_remap, device_ctx.all_sw_inf, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); /* Save the channel widths for the newly constructed graph */ device_ctx.chan_width = chan_width; From 6ac416c70ec00448a4e5c1b2ad560d461fbe9cef Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 14 Apr 2023 21:13:41 -0700 Subject: [PATCH 144/453] [core] code format --- vpr/src/route/rr_graph.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index cfea765b9e2..4459d5fa9c1 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1688,14 +1688,14 @@ static t_seg_details* alloc_and_load_global_route_seg_details(const int global_r /* Calculates the number of track connections from each block pin to each segment type */ std::vector> alloc_and_load_actual_fc(const std::vector& types, - const int max_pins, - const std::vector& segment_inf, - const int* sets_per_seg_type, - const t_chan_width* nodes_per_chan, - const e_fc_type fc_type, - const enum e_directionality directionality, - bool* Fc_clipped, - bool is_flat) { + const int max_pins, + const std::vector& segment_inf, + const int* sets_per_seg_type, + const t_chan_width* nodes_per_chan, + const e_fc_type fc_type, + const enum e_directionality directionality, + bool* Fc_clipped, + bool is_flat) { //Initialize Fc of all blocks to zero auto zeros = vtr::Matrix({size_t(max_pins), segment_inf.size()}, 0); std::vector> Fc(types.size(), zeros); From d70659f424425dbaa6ecdb6dea40bf1841f02dac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 14 Apr 2023 21:16:41 -0700 Subject: [PATCH 145/453] [test] comment out testcase 'strong_vpr_constraints' due to a merging conflict --- vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index cf4854f14df..7ca5174654e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -84,5 +84,4 @@ regression_tests/vtr_reg_strong/koios_no_complex_dsp regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail regression_tests/vtr_reg_strong/strong_tileable_rr_graph -regression_tests/vtr_reg_strong/strong_vpr_constraint regression_tests/vtr_reg_strong/strong_noc From 42e48e544825b502e59902ea4bc906af83684ff1 Mon Sep 17 00:00:00 2001 From: Tulong4Dev Date: Wed, 19 Apr 2023 15:55:05 -0700 Subject: [PATCH 146/453] add missing new line when writing place constraint --- vpr/src/base/gen/vpr_constraints_uxsdcxx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h index 12feabd08ab..166a5629425 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h @@ -1064,7 +1064,7 @@ inline void get_line_number(const char* filename, std::ptrdiff_t target_offset, std::unique_ptr f(fopen(filename, "rb"), fclose); if (!f) { - throw std::runtime_error(std::string("Failed to open file") + filename); + throw std::runtime_error(std::string("Failed to open file ") + filename); } int current_line = 1; From 39e60670957b6eda3d08fc52604f1bc29866b96a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Jun 2023 16:46:38 -0700 Subject: [PATCH 147/453] [core] now adapt to latest api from DeviceGrid --- .../rr_graph_builder_utils.cpp | 52 +++++++---- .../rr_graph_builder_utils.h | 15 ++- .../tileable_rr_graph/rr_graph_view_util.cpp | 12 +-- .../tileable_rr_graph_edge_builder.cpp | 18 ++-- .../tileable_rr_graph_gsb.cpp | 25 +++-- .../tileable_rr_graph_node_builder.cpp | 92 ++++++++++--------- 6 files changed, 117 insertions(+), 97 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index a97b37e2d88..556ee8c2348 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -30,11 +30,13 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width) { /************************************************************************ * Get the class index of a grid pin ***********************************************************************/ -int get_grid_pin_class_index(const t_grid_tile& cur_grid, +int get_grid_pin_class_index(const DeviceGrid& grids, + const size_t& x, const size_t& y, const int pin_index) { /* check */ - VTR_ASSERT(pin_index < cur_grid.type->num_pins); - return cur_grid.type->pin_class[pin_index]; + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + VTR_ASSERT(pin_index < phy_tile_type->num_pins); + return phy_tile_type->pin_class[pin_index]; } /* Deteremine the side of a io grid */ @@ -61,12 +63,16 @@ e_side determine_io_grid_pin_side(const vtr::Point& device_size, } /* Deteremine the side of a pin of a grid */ -std::vector find_grid_pin_sides(const t_grid_tile& grid, +std::vector find_grid_pin_sides(const DeviceGrid& grids, + const size_t& x, const size_t& y, const size_t& pin_id) { std::vector pin_sides; + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + int width_offset = grids.get_width_offset(x, y); + int height_offset = grids.get_height_offset(x, y); for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { - if (true == grid.type->pinloc[grid.width_offset][grid.height_offset][size_t(side)][pin_id]) { + if (true == phy_tile_type->pinloc[width_offset][height_offset][size_t(side)][pin_id]) { pin_sides.push_back(side); } } @@ -79,7 +85,8 @@ std::vector find_grid_pin_sides(const t_grid_tile& grid, * For IO_TYPE, only one side will be used, we consider one side of pins * For others, we consider all the sides ***********************************************************************/ -std::vector get_grid_side_pins(const t_grid_tile& cur_grid, +std::vector get_grid_side_pins(const DeviceGrid& grids, + const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, @@ -88,10 +95,11 @@ std::vector get_grid_side_pins(const t_grid_tile& cur_grid, /* Make sure a clear start */ pin_list.clear(); - for (int ipin = 0; ipin < cur_grid.type->num_pins; ++ipin) { - int class_id = cur_grid.type->pin_class[ipin]; - if ((1 == cur_grid.type->pinloc[pin_width][pin_height][pin_side][ipin]) - && (pin_type == cur_grid.type->class_inf[class_id].type)) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + for (int ipin = 0; ipin < phy_tile_type->num_pins; ++ipin) { + int class_id = phy_tile_type->pin_class[ipin]; + if ((1 == phy_tile_type->pinloc[pin_width][pin_height][pin_side][ipin]) + && (pin_type == phy_tile_type->class_inf[class_id].type)) { pin_list.push_back(ipin); } } @@ -103,22 +111,24 @@ std::vector get_grid_side_pins(const t_grid_tile& cur_grid, * For IO_TYPE, only one side will be used, we consider one side of pins * For others, we consider all the sides ***********************************************************************/ -size_t get_grid_num_pins(const t_grid_tile& cur_grid, +size_t get_grid_num_pins(const DeviceGrid& grids, + const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& io_side) { size_t num_pins = 0; /* For IO_TYPE sides */ + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { /* skip unwanted sides */ - if ((true == is_io_type(cur_grid.type)) + if ((true == is_io_type(phy_tile_type)) && (side != io_side) && (NUM_SIDES != io_side)) { continue; } /* Get pin list */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { - std::vector pin_list = get_grid_side_pins(cur_grid, pin_type, side, width, height); + for (int width = 0; width < phy_tile_type->width; ++width) { + for (int height = 0; height < phy_tile_type->height; ++height) { + std::vector pin_list = get_grid_side_pins(grids, x, y, pin_type, side, width, height); num_pins += pin_list.size(); } } @@ -132,13 +142,15 @@ size_t get_grid_num_pins(const t_grid_tile& cur_grid, * For IO_TYPE, only one side will be used, we consider one side of pins * For others, we consider all the sides ***********************************************************************/ -size_t get_grid_num_classes(const t_grid_tile& cur_grid, +size_t get_grid_num_classes(const DeviceGrid& grids, + const size_t& x, const size_t& y, const e_pin_type& pin_type) { size_t num_classes = 0; - for (size_t iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { /* Bypass unmatched pin_type */ - if (pin_type != cur_grid.type->class_inf[iclass].type) { + if (pin_type != phy_tile_type->class_inf[iclass].type) { continue; } num_classes++; @@ -187,7 +199,7 @@ bool is_chanx_exist(const DeviceGrid& grids, return true; } - return (grids[chanx_coord.x()][chanx_coord.y()].height_offset == grids[chanx_coord.x()][chanx_coord.y()].type->height - 1); + return (grids.get_height_offset(chanx_coord.x(), chanx_coord.y()) == grids.get_height_offset(chanx_coord.x(), chanx_coord.y()) - 1); } /************************************************************************ @@ -225,7 +237,7 @@ bool is_chany_exist(const DeviceGrid& grids, return true; } - return (grids[chany_coord.x()][chany_coord.y()].width_offset == grids[chany_coord.x()][chany_coord.y()].type->width - 1); + return (grids.get_width_offset(chany_coord.x(), chany_coord.y()) == grids.get_width_offset(chany_coord.x(), chany_coord.y()) - 1); } /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index ff0cc9ab782..a3e6bd71375 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -14,26 +14,31 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width); -int get_grid_pin_class_index(const t_grid_tile& cur_grid, +int get_grid_pin_class_index(const DeviceGrid& grids, + const size_t& x, const size_t& y, const int pin_index); -std::vector find_grid_pin_sides(const t_grid_tile& grid, +std::vector find_grid_pin_sides(const DeviceGrid& grids, + const size_t& x, const size_t& y, const size_t& pin_id); e_side determine_io_grid_pin_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate); -std::vector get_grid_side_pins(const t_grid_tile& cur_grid, +std::vector get_grid_side_pins(const DeviceGrid& grids, + const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, const int& pin_height); -size_t get_grid_num_pins(const t_grid_tile& cur_grid, +size_t get_grid_num_pins(const DeviceGrid& grids, + const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& io_side); -size_t get_grid_num_classes(const t_grid_tile& cur_grid, +size_t get_grid_num_classes(const DeviceGrid& grids, + const size_t& x, const size_t& y, const e_pin_type& pin_type); bool is_chanx_exist(const DeviceGrid& grids, diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 66baf26a1f6..4266420be52 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -104,17 +104,17 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, VTR_ASSERT(side != NUM_SIDES); /* Find all the pins on the side of the grid */ - int width_offset = device_grid[x][y].width_offset; - int height_offset = device_grid[x][y].height_offset; - for (int pin = 0; pin < device_grid[x][y].type->num_pins; ++pin) { + int width_offset = device_grid.get_width_offset(x, y); + int height_offset = device_grid.get_height_offset(x, y); + for (int pin = 0; pin < device_grid.get_physical_type(x, y)->num_pins; ++pin) { /* Skip those pins have been ignored during rr_graph build-up */ - if (true == device_grid[x][y].type->is_ignored_pin[pin]) { + if (true == device_grid.get_physical_type(x, y)->is_ignored_pin[pin]) { /* If specified, force to include all the clock pins */ - if (!include_clock || std::find(device_grid[x][y].type->get_clock_pins_indices().begin(), device_grid[x][y].type->get_clock_pins_indices().end(), pin) == device_grid[x][y].type->get_clock_pins_indices().end()) { + if (!include_clock || std::find(device_grid.get_physical_type(x, y)->get_clock_pins_indices().begin(), device_grid.get_physical_type(x, y)->get_clock_pins_indices().end(), pin) == device_grid.get_physical_type(x, y)->get_clock_pins_indices().end()) { continue; } } - if (false == device_grid[x][y].type->pinloc[width_offset][height_offset][side][pin]) { + if (false == device_grid.get_physical_type(x, y)->pinloc[width_offset][height_offset][side][pin]) { /* Not the pin on this side, we skip */ continue; } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index b009874badf..3c409ee01fb 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -33,11 +33,11 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, /* Now, we have an OPIN node, we get the source node index */ short xlow = rr_graph.node_xlow(node); short ylow = rr_graph.node_ylow(node); - short src_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], + short src_node_class_num = get_grid_pin_class_index(grids, xlow, ylow, rr_graph.node_pin_num(node)); /* Create edges between SOURCE and OPINs */ - RRNodeId src_node = rr_graph.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, - ylow - grids[xlow][ylow].height_offset, + RRNodeId src_node = rr_graph.node_lookup().find_node(xlow - grids.get_width_offset(xlow, ylow), + ylow - grids.get_height_offset(xlow, ylow), SOURCE, src_node_class_num); VTR_ASSERT(true == rr_graph.valid_node(src_node)); @@ -68,11 +68,11 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, /* Now, we have an OPIN node, we get the source node index */ short xlow = rr_graph.node_xlow(node); short ylow = rr_graph.node_ylow(node); - short sink_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], + short sink_node_class_num = get_grid_pin_class_index(grids, xlow, ylow, rr_graph.node_pin_num(node)); /* 1. create edges between IPINs and SINKs */ - const RRNodeId& sink_node = rr_graph.node_lookup().find_node(xlow - grids[xlow][ylow].width_offset, - ylow - grids[xlow][ylow].height_offset, + const RRNodeId& sink_node = rr_graph.node_lookup().find_node(xlow - grids.get_width_offset(xlow, ylow), + ylow - grids.get_height_offset(xlow, ylow), SINK, sink_node_class_num, SIDES[0]); VTR_ASSERT(true == rr_graph.valid_node(sink_node)); @@ -162,12 +162,12 @@ void build_rr_graph_direct_connections(const RRGraphView& rr_graph, for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { + if (true == is_empty_type(grids.get_physical_type(ix, iy))) { continue; } /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset)) { + if ((0 < grids.get_width_offset(ix, iy)) + || (0 < grids.get_height_offset(ix, iy))) { continue; } vtr::Point from_grid_coordinate(ix, iy); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index e039fbf7418..335f9e2c0d9 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1213,11 +1213,11 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); /* Skip EMPTY type */ - if (true == is_empty_type(grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type)) { + if (true == is_empty_type(grids.get_physical_type(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node)))) { continue; } - int grid_type_index = grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type->index; + int grid_type_index = grids.get_physical_type(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node))->index; /* Get Fc of the ipin */ /* skip Fc = 0 or unintialized, those pins are in the */ bool skip_conn2track = true; @@ -1292,10 +1292,10 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, for (size_t inode = 0; inode < num_opin_nodes; ++inode) { const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode); /* Skip EMPTY type */ - if (true == is_empty_type(grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type)) { + if (true == is_empty_type(grids.get_physical_type(rr_graph.node_xlow(opin_node), rr_graph.node_ylow(opin_node)))) { continue; } - int grid_type_index = grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type->index; + int grid_type_index = grids.get_physical_type(rr_graph.node_xlow(opin_node), rr_graph.node_ylow(opin_node))->index; /* Get Fc of the ipin */ /* skip Fc = 0 or unintialized, those pins are in the */ @@ -1344,8 +1344,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, const std::vector& clb_to_clb_directs) { VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); - const t_grid_tile& from_grid = grids[from_grid_coordinate.x()][from_grid_coordinate.y()]; - t_physical_tile_type_ptr grid_type = from_grid.type; + t_physical_tile_type_ptr grid_type = grids.get_physical_type(from_grid_coordinate.x(), from_grid_coordinate.y()); /* Iterate through all direct connections */ for (size_t i = 0; i < directs.size(); ++i) { @@ -1361,7 +1360,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, from_grid_coordinate.y() + directs[i].y_offset); /* Bypass unmatched direct clb-to-clb connections */ - t_physical_tile_type_ptr to_grid_type = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].type; + t_physical_tile_type_ptr to_grid_type = grids.get_physical_type(to_grid_coordinate.x(), to_grid_coordinate.y()); /* Check if to_grid if the same grid */ if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { continue; @@ -1404,18 +1403,18 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, } /* Get the pin index in the rr_graph */ - int from_grid_width_ofs = from_grid.width_offset; - int from_grid_height_ofs = from_grid.height_offset; - int to_grid_width_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].width_offset; - int to_grid_height_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].height_offset; + int from_grid_width_ofs = grids.get_width_offset(from_grid_coordinate.x(), from_grid_coordinate.y()); + int from_grid_height_ofs = grids.get_height_offset(from_grid_coordinate.x(), from_grid_coordinate.y()); + int to_grid_width_ofs = grids.get_width_offset(to_grid_coordinate.x(), to_grid_coordinate.y()); + int to_grid_height_ofs = grids.get_height_offset(to_grid_coordinate.x(), to_grid_coordinate.y()); /* Find the side of grid pins, the pin location should be unique! * Pin location is required by searching a node in rr_graph */ - std::vector opin_grid_side = find_grid_pin_sides(from_grid, opin); + std::vector opin_grid_side = find_grid_pin_sides(grids, from_grid_coordinate.x(), from_grid_coordinate.y(), opin); VTR_ASSERT(1 == opin_grid_side.size()); - std::vector ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin); + std::vector ipin_grid_side = find_grid_pin_sides(grids, to_grid_coordinate.x(), to_grid_coordinate.y(), ipin); VTR_ASSERT(1 == ipin_grid_side.size()); RRNodeId opin_node_id = rr_graph.node_lookup().find_node(from_grid_coordinate.x() - from_grid_width_ofs, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index e3b063a33ff..902c4db258d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -31,20 +31,20 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { + if (true == is_empty_type(grids.get_physical_type(ix, iy))) { continue; } /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset)) { + if ((0 < grids.get_width_offset(ix, iy)) + || (0 < grids.get_height_offset(ix, iy))) { continue; } enum e_side io_side = NUM_SIDES; /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids[ix][iy].type)) { + if (true == is_io_type(grids.get_physical_type(ix, iy))) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); vtr::Point grid_coordinate(ix, iy); io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); @@ -53,19 +53,19 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, switch (node_type) { case OPIN: /* get the number of OPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); + num_grid_rr_nodes += get_grid_num_pins(grids, ix, iy, DRIVER, io_side); break; case IPIN: /* get the number of IPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); + num_grid_rr_nodes += get_grid_num_pins(grids, ix, iy, RECEIVER, io_side); break; case SOURCE: /* SOURCE: number of classes whose type is DRIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER); + num_grid_rr_nodes += get_grid_num_classes(grids, ix, iy, DRIVER); break; case SINK: /* SINK: number of classes whose type is RECEIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER); + num_grid_rr_nodes += get_grid_num_classes(grids, ix, iy, RECEIVER); break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -356,7 +356,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, + const DeviceGrid& grids, const e_side& io_side, const RRSwitchId& delayless_switch) { SideManager io_side_manager(io_side); @@ -364,19 +364,20 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder /* Walk through the width height of each grid, * get pins and configure the rr_nodes */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + for (int width = 0; width < phy_tile_type->width; ++width) { + for (int height = 0; height < phy_tile_type->height; ++height) { /* Walk through sides */ for (e_side side : SIDES) { SideManager side_manager(side); /* skip unwanted sides */ - if ((true == is_io_type(cur_grid.type)) + if ((true == is_io_type(phy_tile_type)) && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { continue; } /* Find OPINs */ /* Configure pins by pins */ - std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), + std::vector opin_list = get_grid_side_pins(grids, grid_coordinate.x(), grid_coordinate.y(), DRIVER, side_manager.get_side(), width, height); for (const int& pin_num : opin_list) { /* Create a new node and fill information */ @@ -418,7 +419,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, + const DeviceGrid& grids, const e_side& io_side, const RRSwitchId& wire_to_ipin_switch) { SideManager io_side_manager(io_side); @@ -426,20 +427,21 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder /* Walk through the width and height of each grid, * get pins and configure the rr_nodes */ - for (int width = 0; width < cur_grid.type->width; ++width) { - for (int height = 0; height < cur_grid.type->height; ++height) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + for (int width = 0; width < phy_tile_type->width; ++width) { + for (int height = 0; height < phy_tile_type->height; ++height) { /* Walk through sides */ for (e_side side : SIDES) { SideManager side_manager(side); /* skip unwanted sides */ - if ((true == is_io_type(cur_grid.type)) + if ((true == is_io_type(phy_tile_type)) && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { continue; } /* Find IPINs */ /* Configure pins by pins */ - std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height); + std::vector ipin_list = get_grid_side_pins(grids, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height); for (const int& pin_num : ipin_list) { /* Create a new node and fill information */ RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x() + width, grid_coordinate.y() + height, IPIN, pin_num, side); @@ -480,15 +482,16 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, + const DeviceGrid& grids, const e_side& io_side, const RRSwitchId& delayless_switch) { SideManager io_side_manager(io_side); /* Set a SOURCE rr_node for each DRIVER class */ - for (size_t iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { /* Set a SINK rr_node for the OPIN */ - if (DRIVER != cur_grid.type->class_inf[iclass].type) { + if (DRIVER != phy_tile_type->class_inf[iclass].type) { continue; } @@ -498,12 +501,12 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), grid_coordinate.y(), - grid_coordinate.x() + cur_grid.type->width - 1, - grid_coordinate.y() + cur_grid.type->height - 1); + grid_coordinate.x() + phy_tile_type->width - 1, + grid_coordinate.y() + phy_tile_type->height - 1); rr_graph_builder.set_node_class_num(node, iclass); /* The capacity should be the number of pins in this class*/ - rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + rr_graph_builder.set_node_capacity(node, phy_tile_type->class_inf[iclass].num_pins); /* cost index is a FIXED value for SOURCE */ rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); @@ -528,15 +531,16 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, const vtr::Point& grid_coordinate, - const t_grid_tile& cur_grid, + const DeviceGrid& grids, const e_side& io_side, const RRSwitchId& delayless_switch) { SideManager io_side_manager(io_side); /* Set a SINK rr_node for each RECEIVER class */ - for (size_t iclass = 0; iclass < cur_grid.type->class_inf.size(); ++iclass) { + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { /* Set a SINK rr_node for the OPIN */ - if (RECEIVER != cur_grid.type->class_inf[iclass].type) { + if (RECEIVER != phy_tile_type->class_inf[iclass].type) { continue; } @@ -546,14 +550,14 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), grid_coordinate.y(), - grid_coordinate.x() + cur_grid.type->width - 1, - grid_coordinate.y() + cur_grid.type->height - 1); + grid_coordinate.x() + phy_tile_type->width - 1, + grid_coordinate.y() + phy_tile_type->height - 1); rr_graph_builder.set_node_class_num(node, iclass); rr_graph_builder.set_node_capacity(node, 1); /* The capacity should be the number of pins in this class*/ - rr_graph_builder.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); + rr_graph_builder.set_node_capacity(node, phy_tile_type->class_inf[iclass].num_pins); /* cost index is a FIXED value for SINK */ rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); @@ -579,13 +583,13 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { /* Skip EMPTY tiles */ - if (true == is_empty_type(grids[ix][iy].type)) { + if (true == is_empty_type(grids.get_physical_type(ix, iy))) { continue; } /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ - if ((0 < grids[ix][iy].width_offset) - || (0 < grids[ix][iy].height_offset)) { + if ((0 < grids.get_width_offset(ix, iy)) + || (0 < grids.get_height_offset(ix, iy))) { continue; } @@ -595,7 +599,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, std::vector wanted_sides{TOP, RIGHT, BOTTOM, LEFT}; /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids[ix][iy].type)) { + if (true == is_io_type(grids.get_physical_type(ix, iy))) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); wanted_sides.clear(); @@ -603,12 +607,12 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, } for (e_side side : wanted_sides) { - for (int width_offset = 0; width_offset < grids[ix][iy].type->width; ++width_offset) { + for (int width_offset = 0; width_offset < grids.get_physical_type(ix, iy)->width; ++width_offset) { int x_tile = ix + width_offset; - for (int height_offset = 0; height_offset < grids[ix][iy].type->height; ++height_offset) { + for (int height_offset = 0; height_offset < grids.get_physical_type(ix, iy)->height; ++height_offset) { int y_tile = iy + height_offset; - rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, OPIN, grids[ix][iy].type->num_pins, side); - rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, IPIN, grids[ix][iy].type->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, OPIN, grids.get_physical_type(ix, iy)->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, IPIN, grids.get_physical_type(ix, iy)->num_pins, side); } } } @@ -618,7 +622,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_node_driver_switches, rr_rc_data, grid_coordinate, - grids[ix][iy], + grids, io_side, delayless_switch); @@ -627,7 +631,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_node_driver_switches, rr_rc_data, grid_coordinate, - grids[ix][iy], + grids, io_side, delayless_switch); @@ -636,7 +640,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_node_driver_switches, rr_rc_data, grid_coordinate, - grids[ix][iy], + grids, io_side, delayless_switch); @@ -645,7 +649,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_node_driver_switches, rr_rc_data, grid_coordinate, - grids[ix][iy], + grids, io_side, wire_to_ipin_switch); } @@ -654,8 +658,8 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, // This ensures that look-ups on non-root locations will still find the correct SOURCE/SINK for (size_t x = 0; x < grids.width(); x++) { for (size_t y = 0; y < grids.height(); y++) { - int width_offset = grids[x][y].width_offset; - int height_offset = grids[x][y].height_offset; + int width_offset = grids.get_width_offset(x, y); + int height_offset = grids.get_height_offset(x, y); if (width_offset != 0 || height_offset != 0) { int root_x = x - width_offset; int root_y = y - height_offset; From 0963c20472e178d6562e40d90727870342035f67 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Jun 2023 20:29:37 -0700 Subject: [PATCH 148/453] [core] fixed a bug due to mis-use of APIs --- vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 556ee8c2348..1f04e5d9c90 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -199,7 +199,7 @@ bool is_chanx_exist(const DeviceGrid& grids, return true; } - return (grids.get_height_offset(chanx_coord.x(), chanx_coord.y()) == grids.get_height_offset(chanx_coord.x(), chanx_coord.y()) - 1); + return (grids.get_height_offset(chanx_coord.x(), chanx_coord.y()) == grids.get_physical_type(chanx_coord.x(), chanx_coord.y())->height - 1); } /************************************************************************ @@ -237,7 +237,7 @@ bool is_chany_exist(const DeviceGrid& grids, return true; } - return (grids.get_width_offset(chany_coord.x(), chany_coord.y()) == grids.get_width_offset(chany_coord.x(), chany_coord.y()) - 1); + return (grids.get_width_offset(chany_coord.x(), chany_coord.y()) == grids.get_physical_type(chany_coord.x(), chany_coord.y())->width - 1); } /************************************************************************ From 5b4cb5d71a25fe32a1dd2a4af721079d2fb23463 Mon Sep 17 00:00:00 2001 From: umariqbal-rs Date: Tue, 25 Jul 2023 15:14:34 +0500 Subject: [PATCH 149/453] added call to .xmle and accept key from CMake macro --- libs/CMakeLists.txt | 1 + libs/libarchfpga/src/read_xml_arch_file.cpp | 4 +- libs/libdecrypt/ README.md | 98 +++++++++++ libs/libdecrypt/CMakeLists.txt | 47 +++++ libs/libdecrypt/config.h.in | 9 + libs/libdecrypt/config.txt | 1 + libs/libdecrypt/private_key.pem | 30 ++++ libs/libdecrypt/src/config.h | 9 + libs/libdecrypt/src/decryption.cpp | 185 ++++++++++++++++++++ libs/libdecrypt/src/decryption.h | 86 +++++++++ libs/libdecrypt/src/obfuscate.h | 185 ++++++++++++++++++++ libs/libencrypt/CMakeLists.txt | 51 ++++++ libs/libencrypt/README.md | 71 ++++++++ libs/libencrypt/config.h.in | 9 + libs/libencrypt/config.txt | 1 + libs/libencrypt/main.cpp | 22 +++ libs/libencrypt/public_key.pem | 9 + libs/libencrypt/src/encryption.cpp | 177 +++++++++++++++++++ libs/libencrypt/src/encryption.h | 70 ++++++++ libs/libencrypt/src/obfuscate.h | 185 ++++++++++++++++++++ libs/libpugiutil/CMakeLists.txt | 3 +- libs/libpugiutil/src/pugixml_loc.cpp | 13 ++ libs/libpugiutil/src/pugixml_loc.hpp | 9 +- libs/libpugiutil/src/pugixml_util.cpp | 48 +++-- 24 files changed, 1305 insertions(+), 18 deletions(-) create mode 100644 libs/libdecrypt/ README.md create mode 100644 libs/libdecrypt/CMakeLists.txt create mode 100644 libs/libdecrypt/config.h.in create mode 100644 libs/libdecrypt/config.txt create mode 100644 libs/libdecrypt/private_key.pem create mode 100644 libs/libdecrypt/src/config.h create mode 100644 libs/libdecrypt/src/decryption.cpp create mode 100644 libs/libdecrypt/src/decryption.h create mode 100644 libs/libdecrypt/src/obfuscate.h create mode 100644 libs/libencrypt/CMakeLists.txt create mode 100644 libs/libencrypt/README.md create mode 100644 libs/libencrypt/config.h.in create mode 100644 libs/libencrypt/config.txt create mode 100644 libs/libencrypt/main.cpp create mode 100644 libs/libencrypt/public_key.pem create mode 100644 libs/libencrypt/src/encryption.cpp create mode 100644 libs/libencrypt/src/encryption.h create mode 100644 libs/libencrypt/src/obfuscate.h diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index 094f7694cad..d0027806766 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -9,6 +9,7 @@ link_libraries(${ADDITIONAL_FLAGS}) add_subdirectory(libarchfpga) add_subdirectory(libvtrutil) add_subdirectory(liblog) +add_subdirectory(libdecrypt) add_subdirectory(libpugiutil) add_subdirectory(libvqm) add_subdirectory(librtlnumber) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index fb84e2cb882..47f546c7251 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -313,10 +313,10 @@ void XmlReadArch(const char* ArchFile, pugi::xml_node Next; ReqOpt POWER_REQD, SWITCHBLOCKLIST_REQD; - if (vtr::check_file_name_extension(ArchFile, ".xml") == false) { + if ((vtr::check_file_name_extension(ArchFile, ".xml") == false) && (vtr::check_file_name_extension(ArchFile, ".xml") == false)) { VTR_LOG_WARN( "Architecture file '%s' may be in incorrect format. " - "Expecting .xml format for architecture files.\n", + "Expecting .xml or .xmle format for architecture files.\n", ArchFile); } diff --git a/libs/libdecrypt/ README.md b/libs/libdecrypt/ README.md new file mode 100644 index 00000000000..e6a4193bf43 --- /dev/null +++ b/libs/libdecrypt/ README.md @@ -0,0 +1,98 @@ + # libdecrypt + +libdecrypt is a C++ library for decrypting encrypted files. It provides a simple interface to decrypt files using OpenSSL for encryption and decryption operations and pugixml for XML parsing. + +## Features + +- Decrypts encrypted files using RSA encryption algorithm. +- Supports loading private key from PEM string. +- Retrieves encrypted data and session key from XML file. +- Decrypts session key using RSA private key. +- Decrypts XML string using the decrypted session key. +- Outputs the decrypted content as a string. + +## Installation + +1. Build the library using CMake + + cd libdecrypt + mkdir build + cd build + cmake .. + make +2. Install the library (optional): + + make install +## Dependencies + +Make sure you have the following dependencies installed on your system: + +- **OpenSSL**: The library depends on OpenSSL for encryption and decryption operations. Make sure you have OpenSSL installed on your system. + +- **pugixml**: The library uses pugixml for XML parsing. It is included as a submodule in the project. + +## Usage + +To use the `libdecrypt` library in your C++ projects, follow the steps below: + +1. Include the `decryption.h` header file in your source code: + + ```cpp + #include "decryption.h" + +2. Create a `Decryption` object with the path to the encrypted file: + + std::string encryptedFile = "path/to/encrypted/file"; + Decryption decryption(encryptedFile); + +3. Decrypt the contents of the encrypted file: + + decryption.decryptFile(); + +4. Retrieve the decrypted content as a string: + + std::string decryptedContent = decryption.getDecryptedContent(); + +5. Optional: Write the decrypted content to a file: + + std::ofstream outputFile("output.txt"); + outputFile << decryptedContent; + outputFile.close(); + +## Configuration + +To configure `libdecrypt` for your specific use case, follow these steps: + +### Private Key: + +- **Option 1: Define `PRIVATE_KEY` in the code:** + - Locate the `decryption.h` file in the project. + - Uncomment the `#define PRIVATE_KEY` line. + - Replace the dummy private key string with your actual private key in PEM format. + +- **Option 2: Provide a `private_key.pem` file:** + - Place your private key file in the project directory. + - Make sure the file is named `private_key.pem`. + - `libdecrypt` will automatically load the private key from this file. + +### Passphrase: + +- **Option 1: Define `PASSPHRASE` in the code:** + - Locate the `decryption.h` file in the project. + - Uncomment the `#define PASSPHRASE` line. + - Replace the empty string with your actual passphrase. + +- **Option 2: Provide a `config.txt` file:** + - Create a plain text file named `config.txt` in the project directory. + - Write your passphrase in the file. + - `libdecrypt` will read the passphrase from this file. + +Make sure to configure the private key and passphrase according to your specific requirements before using the `libdecrypt` library. + +## License + +This project is licensed under the MIT License + +## Contributing + +Contributions are welcome! If you find any issues or have suggestions for improvements, please feel free to open an issue or submit a pull request. We appreciate your contributions to make this project better. diff --git a/libs/libdecrypt/CMakeLists.txt b/libs/libdecrypt/CMakeLists.txt new file mode 100644 index 00000000000..3eaeab363c6 --- /dev/null +++ b/libs/libdecrypt/CMakeLists.txt @@ -0,0 +1,47 @@ +cmake_minimum_required(VERSION 3.16) +project(libdecrypt) + +file(READ "private_key.pem" PRIVATE_KEY_CONTENTS) +file(READ "config.txt" PASSPHRASE_CONTENTS) + +string(REPLACE "\n" "\\n" PRIVATE_KEY_CONTENTS "${PRIVATE_KEY_CONTENTS}") +string(REPLACE "\n" "\\n" PASSPHRASE_CONTENTS "${PASSPHRASE_CONTENTS}") +set(PRIVATE_KEY "${PRIVATE_KEY_CONTENTS}") +set(PASS_PHRASE "${PASSPHRASE_CONTENTS}") +add_compile_definitions(PASS_PHRASE="${PASS_PHRASE}") +add_compile_definitions(PRIVATE_KEY="${PRIVATE_KEY}") +find_package(PkgConfig REQUIRED) +pkg_search_module(OPENSSL REQUIRED openssl) + +if( OPENSSL_FOUND ) + include_directories(${OPENSSL_INCLUDE_DIRS}) + message(STATUS "Using OpenSSL ${OPENSSL_VERSION}") +else() + message("SSL not found") + # Error; with REQUIRED, pkg_search_module() will throw an error by it's own +endif() +# Source files and library +file(GLOB_RECURSE LIB_SOURCES src/*.cpp) +file(GLOB_RECURSE LIB_HEADERS src/*.hpp src/*.h) +set(LIB_INCLUDE_DIRS "") +foreach (_headerFile ${LIB_HEADERS}) + get_filename_component(_dir ${_headerFile} PATH) + list(APPEND LIB_INCLUDE_DIRS ${_dir}) +endforeach () +list(REMOVE_DUPLICATES LIB_INCLUDE_DIRS) + + + +# Create the library +add_library(libdecrypt STATIC + ${LIB_HEADERS} + ${LIB_SOURCES}) +target_include_directories(libdecrypt PUBLIC ${LIB_INCLUDE_DIRS}) +set_target_properties(libdecrypt PROPERTIES PREFIX "") # Avoid extra 'lib' prefix + +target_link_libraries(libdecrypt + libpugixml + ${OPENSSL_LIBRARIES} +) +install(TARGETS libdecrypt DESTINATION bin) +install(FILES ${LIB_HEADERS} DESTINATION include/libdecrypt) \ No newline at end of file diff --git a/libs/libdecrypt/config.h.in b/libs/libdecrypt/config.h.in new file mode 100644 index 00000000000..25df8342f97 --- /dev/null +++ b/libs/libdecrypt/config.h.in @@ -0,0 +1,9 @@ + +#ifndef CONFIG_H +#define CONFIG_H + +#define PRIVATE_KEY "@PRIVATE_KEY@" +#define PASSPHRASE "@PASS_PHRASE@" +// Add more configuration variables as needed + +#endif // CONFIG_H diff --git a/libs/libdecrypt/config.txt b/libs/libdecrypt/config.txt new file mode 100644 index 00000000000..85df50785d6 --- /dev/null +++ b/libs/libdecrypt/config.txt @@ -0,0 +1 @@ +abcd \ No newline at end of file diff --git a/libs/libdecrypt/private_key.pem b/libs/libdecrypt/private_key.pem new file mode 100644 index 00000000000..f93621227a2 --- /dev/null +++ b/libs/libdecrypt/private_key.pem @@ -0,0 +1,30 @@ +-----BEGIN ENCRYPTED PRIVATE KEY----- +MIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQIxiWq9/gKEI4CAggA +MAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBCM12wmpHSRMA8no6WSnyiRBIIE +0HWEpZCWG230mIezxiEQGtR/W0HliJIU/fkJukt7hyqt6ECwcr9te80KIcqftUsH +64d8GBwCAfIpP5gDtojsm2XwM6acdGyFO4ZFyF2yO+kO9kdUVPQbe6Um2wYFGpXq +wMeMclkL+ZRxhttu6j9RsB9iQKqh13/Nw2x7y2xCDK0lkbHKprdO466C92Vqygvb +6Yz7VoawwJT9Wpn7Z6//vSQ1QI7ePf2P1CrZp+z0Nr+kJqxCoSuQ7wavnsEgF+pA +qqx9WRU6twtG97LHeOeYoZZmSN5i3KAFiwWIlxka96VTl86lREPzDJYa4pHR2FNm +186rrKjAIlDlF9UC6zZMIGUtNdo5miuhpjR6BUFQlDIMW6y2nubyj3awBVvM7F45 +QDh0Mzr4x0Ohqaw5+CphkcUKozRHLXA5/31bJLNIGYB6J3uRdJAVVr1R4ouNeI2U ++2Z60WhMIDROVIXn4AwdoukiUy2uBHNPJp8HPyX+aD7I6FgmcLtuZWrjCnOYU44I +8yBVDGbFb/dsjaJbNDNfyl4db6RcPlOjIhIv7kPF3T4AAY2VRZAGQJBNPZ5XO0U9 +nK5q5wgyagsiIWnIhtx7k9texnnVJpOmaF2mS3Wh/PyxJ01wav8yd5TYu8V8vbUV +7dcM/qIUkkYr1Q6llXrSOeA6kGdOfbRSDqgu+9n3NfH4T5msKQQN6u6b1Z/0ayev +pJgFjaxZITh+7T20BEgULuuv3+sCNYPpEmf+fi7V8AKjjdB3iol2XIFKtKYzInwP +Jb/sageAS/u0MHYt4s9XMi69998CAnlt+qZD2wekI6/AOXyxXxkx9WLaxP6Gb6L+ +e/EEui/gKw+AjKlwHrQHFTo2byJy0dOMfJDaCdb8TXouGLrw0iDcoVm/mxN/66WH +ncFSeVqiYOl7lc2y9cfmMNffdw8E92ab6k1bxy4wdmcskVqXsUskveQ4IbAxdaOp +R6B/FZuRvUpjIHlKb0wpmLxvaY1i1bWDXfE5hbIv6zDSMAdgpLeE9Om1xdhOvm2p +dndJguGR6Nk8tYGvJFXREwLxdEU5z3/Cdv/hTV2kmdz1I/JKcEB2cmgqLV1jBpIl +Mzebwl7Dwtxc2VYIDgrij3bU2ekRw1s6dV+RlJdbEX+j5/pxi/sh67szP0JZ4Lfk +87Pk1pmUksqKc6ybU+KCqHmTvlKu1fMrAj4DVG2qLMKl3nVXLnYCm8J7jh5CNXZe +/Qptee/KaT86bP4POQ6w8fKwF2EMT0HrvL5tUoHt6cwH8Hn6pHmrYRI8dbaG9PH2 +wtOvgzRzCalkCh0hAJDrYehnmDCMTFxDC0y8O3l5Ngz/0vhXEsiMUoEk4J9ZbkuZ +yjLl8DSeA8tcCh5XmQ99QMrhdtPCcak+LmbmbEVPWV91FYowcvTTegC9qaJvE5HK +T5X/JkJtw2ZzC/P0CJuAnfLD+mDBayb71/44PqlzOnuPB/6qqldktw4utH0Yjmdx +kri2neh2tJswe/d8pm2g6RJXquxgmszIBh7O6AZ38hjQVVAiQbxuUviB8K4Q7w3B +bTEB2xM7/4uW/QJbPShAA9pd6iMVm8dWMqXJ3zLg+P+qUGQbI9XKx2Ramsy91Xk6 +o6hYZncsAZoVO6HnCoH7WhBozoyFKiZlA9WqqMGL83lU +-----END ENCRYPTED PRIVATE KEY----- diff --git a/libs/libdecrypt/src/config.h b/libs/libdecrypt/src/config.h new file mode 100644 index 00000000000..c01a0dce535 --- /dev/null +++ b/libs/libdecrypt/src/config.h @@ -0,0 +1,9 @@ + +#ifndef CONFIG_H +#define CONFIG_H + +#define PRIVATE_KEY "-----BEGIN ENCRYPTED PRIVATE KEY-----\nMIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQIxiWq9/gKEI4CAggA\nMAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBCM12wmpHSRMA8no6WSnyiRBIIE\n0HWEpZCWG230mIezxiEQGtR/W0HliJIU/fkJukt7hyqt6ECwcr9te80KIcqftUsH\n64d8GBwCAfIpP5gDtojsm2XwM6acdGyFO4ZFyF2yO+kO9kdUVPQbe6Um2wYFGpXq\nwMeMclkL+ZRxhttu6j9RsB9iQKqh13/Nw2x7y2xCDK0lkbHKprdO466C92Vqygvb\n6Yz7VoawwJT9Wpn7Z6//vSQ1QI7ePf2P1CrZp+z0Nr+kJqxCoSuQ7wavnsEgF+pA\nqqx9WRU6twtG97LHeOeYoZZmSN5i3KAFiwWIlxka96VTl86lREPzDJYa4pHR2FNm\n186rrKjAIlDlF9UC6zZMIGUtNdo5miuhpjR6BUFQlDIMW6y2nubyj3awBVvM7F45\nQDh0Mzr4x0Ohqaw5+CphkcUKozRHLXA5/31bJLNIGYB6J3uRdJAVVr1R4ouNeI2U\n+2Z60WhMIDROVIXn4AwdoukiUy2uBHNPJp8HPyX+aD7I6FgmcLtuZWrjCnOYU44I\n8yBVDGbFb/dsjaJbNDNfyl4db6RcPlOjIhIv7kPF3T4AAY2VRZAGQJBNPZ5XO0U9\nnK5q5wgyagsiIWnIhtx7k9texnnVJpOmaF2mS3Wh/PyxJ01wav8yd5TYu8V8vbUV\n7dcM/qIUkkYr1Q6llXrSOeA6kGdOfbRSDqgu+9n3NfH4T5msKQQN6u6b1Z/0ayev\npJgFjaxZITh+7T20BEgULuuv3+sCNYPpEmf+fi7V8AKjjdB3iol2XIFKtKYzInwP\nJb/sageAS/u0MHYt4s9XMi69998CAnlt+qZD2wekI6/AOXyxXxkx9WLaxP6Gb6L+\ne/EEui/gKw+AjKlwHrQHFTo2byJy0dOMfJDaCdb8TXouGLrw0iDcoVm/mxN/66WH\nncFSeVqiYOl7lc2y9cfmMNffdw8E92ab6k1bxy4wdmcskVqXsUskveQ4IbAxdaOp\nR6B/FZuRvUpjIHlKb0wpmLxvaY1i1bWDXfE5hbIv6zDSMAdgpLeE9Om1xdhOvm2p\ndndJguGR6Nk8tYGvJFXREwLxdEU5z3/Cdv/hTV2kmdz1I/JKcEB2cmgqLV1jBpIl\nMzebwl7Dwtxc2VYIDgrij3bU2ekRw1s6dV+RlJdbEX+j5/pxi/sh67szP0JZ4Lfk\n87Pk1pmUksqKc6ybU+KCqHmTvlKu1fMrAj4DVG2qLMKl3nVXLnYCm8J7jh5CNXZe\n/Qptee/KaT86bP4POQ6w8fKwF2EMT0HrvL5tUoHt6cwH8Hn6pHmrYRI8dbaG9PH2\nwtOvgzRzCalkCh0hAJDrYehnmDCMTFxDC0y8O3l5Ngz/0vhXEsiMUoEk4J9ZbkuZ\nyjLl8DSeA8tcCh5XmQ99QMrhdtPCcak+LmbmbEVPWV91FYowcvTTegC9qaJvE5HK\nT5X/JkJtw2ZzC/P0CJuAnfLD+mDBayb71/44PqlzOnuPB/6qqldktw4utH0Yjmdx\nkri2neh2tJswe/d8pm2g6RJXquxgmszIBh7O6AZ38hjQVVAiQbxuUviB8K4Q7w3B\nbTEB2xM7/4uW/QJbPShAA9pd6iMVm8dWMqXJ3zLg+P+qUGQbI9XKx2Ramsy91Xk6\no6hYZncsAZoVO6HnCoH7WhBozoyFKiZlA9WqqMGL83lU\n-----END ENCRYPTED PRIVATE KEY-----\n" +#define PASSPHRASE "abcd" +// Add more configuration variables as needed + +#endif // CONFIG_H diff --git a/libs/libdecrypt/src/decryption.cpp b/libs/libdecrypt/src/decryption.cpp new file mode 100644 index 00000000000..2a745cfd5bf --- /dev/null +++ b/libs/libdecrypt/src/decryption.cpp @@ -0,0 +1,185 @@ +#include "decryption.h" + +#ifdef PASS_PHRASE +std::string passphrase = PASS_PHRASE; +#else +std::string passphrase = ""; // Set your PEM pass phrase here +#endif + +/** + * @brief Constructs a Decryption object with the specified encrypted file. + * + * @param encryptedFile The path to the encrypted file. + */ +Decryption::Decryption(const std::string& encryptedFile) + : encryptedFile_(encryptedFile) { + decryptFile(); +} + +/** + * @brief Decrypts the contents of the encrypted file. + * + * This function performs the decryption process, including loading the private key, + * retrieving the encrypted data and session key from the XML file, decrypting the + * session key, and decrypting the XML string. + */ +void Decryption::decryptFile() { +#ifdef PRIVATE_KEY + const char* privateKeyString = AY_OBFUSCATE(PRIVATE_KEY); +#else + const char* privateKeyString = AY_OBFUSCATE( + "-----BEGIN RSA PRIVATE KEY-----\n" + "dummykey\n" + "-----END RSA PRIVATE KEY-----\n"); // Replace with your private key string +#endif + RSA* privateKey = loadPrivateKey(privateKeyString); + if (!privateKey) { + return; + } + + // Load encrypted data and session key from XML file + pugi::xml_document encryptedDocLoaded; + pugi::xml_parse_result result = encryptedDocLoaded.load_file(encryptedFile_.c_str()); + if (!result) { + std::cerr << "XML parse error: " << result.description() << std::endl; + RSA_free(privateKey); + return; + } + + pugi::xml_node root = encryptedDocLoaded.child("EncryptedData"); + std::string base64EncryptedSessionKeyLoaded = root.child_value("SessionKey"); + std::string base64EncryptedLoaded = root.child_value("Data"); + + // Base64 decode encrypted session key and data + std::string encryptedSessionKeyLoaded = base64_decode(base64EncryptedSessionKeyLoaded); + std::string encryptedLoaded = base64_decode(base64EncryptedLoaded); + + // Decrypt session key + std::string decryptedSessionKey = decryptSessionKey(encryptedSessionKeyLoaded, privateKey); + + // Decrypt XML string + std::string decrypted = decrypt(encryptedLoaded, privateKey); + + // Write the decrypted data to a file + // std::ofstream decryptedFile("decrypted.xml"); + // decryptedFile << decrypted; + // decryptedFile.close(); + + decryptedContent_ = decrypted; + RSA_free(privateKey); +} + +/** + * @brief Retrieves the decrypted content. + * + * @return The decrypted content as a string. + */ +std::string Decryption::getDecryptedContent() const { + return decryptedContent_; +} + +/** + * @brief Decrypts the given ciphertext using the provided RSA key. + * + * @param ciphertext The ciphertext to decrypt. + * @param key The RSA key for decryption. + * @return The decrypted plaintext. + */ +std::string Decryption::decrypt(const std::string& ciphertext, RSA* key) { + int rsaLen = RSA_size(key); + int len = ciphertext.size(); + std::string plaintext; + + for (int i = 0; i < len; i += rsaLen) { + std::vector buffer(rsaLen); + std::string substr = ciphertext.substr(i, rsaLen); + + int result = RSA_private_decrypt(substr.size(), reinterpret_cast(substr.data()), buffer.data(), key, RSA_PKCS1_OAEP_PADDING); + if (result == -1) { + std::cerr << "Decryption error: " << ERR_error_string(ERR_get_error(), NULL) << std::endl; + return ""; + } + + plaintext.append(reinterpret_cast(buffer.data()), result); + } + + return plaintext; +} + +/** + * @brief Decodes the given base64-encoded string. + * + * @param input The base64-encoded input string. + * @return The decoded output string. + */ +std::string Decryption::base64_decode(const std::string& input) { + BIO* b64 = BIO_new(BIO_f_base64()); + BIO_set_flags(b64, BIO_FLAGS_BASE64_NO_NL); + + BIO* bmem = BIO_new_mem_buf(input.data(), input.size()); + b64 = BIO_push(b64, bmem); + + std::string output; + output.resize(input.size()); + + int decoded_size = BIO_read(b64, &output[0], input.size()); + output.resize(decoded_size); + BIO_free_all(b64); + + return output; +} + +/** + * @brief Loads the private key from the given PEM string. + * + * @param privateKeyString The PEM string representing the private key. + * @return The loaded RSA private key. + */ +RSA* Decryption::loadPrivateKey(const std::string& privateKeyString) { + RSA* key = nullptr; + BIO* privateKeyBio = BIO_new_mem_buf(privateKeyString.data(), privateKeyString.size()); + + if (!privateKeyBio) { + std::cerr << "Error creating BIO for private key" << std::endl; + return nullptr; + } + + if (!PEM_read_bio_RSAPrivateKey(privateKeyBio, &key, NULL, (void*)passphrase.c_str())) { + std::cerr << "Error reading private key" << std::endl; + BIO_free(privateKeyBio); + return nullptr; + } + + BIO_free(privateKeyBio); + return key; +} + +/** + * @brief Decrypts the given encrypted session key using the provided RSA key. + * + * @param encryptedSessionKey The encrypted session key. + * @param key The RSA key for decryption. + * @return The decrypted session key. + */ +std::string Decryption::decryptSessionKey(const std::string& encryptedSessionKey, RSA* key) { + std::vector decryptedSessionKey(RSA_size(key)); + if (RSA_private_decrypt(encryptedSessionKey.size(), reinterpret_cast(encryptedSessionKey.data()), decryptedSessionKey.data(), key, RSA_PKCS1_OAEP_PADDING) == -1) { + std::cerr << "Session key decryption error: " << ERR_error_string(ERR_get_error(), NULL) << std::endl; + return ""; + } + + return std::string(reinterpret_cast(decryptedSessionKey.data()), decryptedSessionKey.size()); +} + +// int main(int argc, char* argv[]) { +// if (argc < 2) { +// std::cerr << "Usage: " << argv[0] << " \n"; +// return -1; +// } + +// std::string encryptedFile = argv[1]; + +// Decryption decryption(encryptedFile); + +// return 0; +// } diff --git a/libs/libdecrypt/src/decryption.h b/libs/libdecrypt/src/decryption.h new file mode 100644 index 00000000000..52d3023dd93 --- /dev/null +++ b/libs/libdecrypt/src/decryption.h @@ -0,0 +1,86 @@ +#ifndef DECRYPTION_H +#define DECRYPTION_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pugixml.hpp" +#include "obfuscate.h" + +/** + * @brief The Decryption class for decrypting encrypted files. + */ +class Decryption +{ +public: + /** + * @brief Constructs a Decryption object with the specified encrypted file. + * + * @param encryptedFile The path to the encrypted file. + */ + Decryption(const std::string &encryptedFile); + + /** + * @brief Decrypts the contents of the encrypted file. + * + * This function performs the decryption process, including loading the private key, + * retrieving the encrypted data and session key from the XML file, decrypting the + * session key, and decrypting the XML string. + */ + void decryptFile(); + + /** + * @brief Retrieves the decrypted content. + * + * @return The decrypted content as a string. + */ + std::string getDecryptedContent() const; + +private: + std::string encryptedFile_; /**< The path to the encrypted file. */ + std::string decryptedContent_; /**< The decrypted content of the file. */ + + /** + * @brief Decrypts the given ciphertext using the provided RSA key. + * + * @param ciphertext The ciphertext to decrypt. + * @param key The RSA key for decryption. + * @return The decrypted plaintext. + */ + static std::string decrypt(const std::string &ciphertext, RSA *key); + + /** + * @brief Decodes the given base64-encoded string. + * + * @param input The base64-encoded input string. + * @return The decoded output string. + */ + static std::string base64_decode(const std::string &input); + + /** + * @brief Loads the private key from the given PEM string. + * + * @param privateKeyString The PEM string representing the private key. + * @return The loaded RSA private key. + */ + static RSA *loadPrivateKey(const std::string &privateKeyString); + + /** + * @brief Decrypts the given encrypted session key using the provided RSA key. + * + * @param encryptedSessionKey The encrypted session key. + * @param key The RSA key for decryption. + * @return The decrypted session key. + */ + static std::string decryptSessionKey(const std::string &encryptedSessionKey, RSA *key); +}; + +#endif // DECRYPTION_H diff --git a/libs/libdecrypt/src/obfuscate.h b/libs/libdecrypt/src/obfuscate.h new file mode 100644 index 00000000000..5450eb44f01 --- /dev/null +++ b/libs/libdecrypt/src/obfuscate.h @@ -0,0 +1,185 @@ +#ifndef OBFUSCATE_H +#define OBFUSCATE_H + +#ifdef _MSC_VER + #define AY_CAT(X,Y) AY_CAT2(X,Y) + #define AY_CAT2(X,Y) X##Y + #define AY_LINE int(AY_CAT(__LINE__,U)) +#else + #define AY_LINE __LINE__ +#endif + +#ifndef AY_OBFUSCATE_DEFAULT_KEY + // The default 64 bit key to obfuscate strings with. + // This can be user specified by defining AY_OBFUSCATE_DEFAULT_KEY before + // including obfuscate.h + #define AY_OBFUSCATE_DEFAULT_KEY ay::generate_key(AY_LINE) +#endif + +namespace ay +{ + using size_type = unsigned long long; + using key_type = unsigned long long; + + // Generate a pseudo-random key that spans all 8 bytes + constexpr key_type generate_key(key_type seed) + { + // Use the MurmurHash3 64-bit finalizer to hash our seed + key_type key = seed; + key ^= (key >> 33); + key *= 0xff51afd7ed558ccd; + key ^= (key >> 33); + key *= 0xc4ceb9fe1a85ec53; + key ^= (key >> 33); + + // Make sure that a bit in each byte is set + key |= 0x0101010101010101ull; + + return key; + } + + // Obfuscates or deobfuscates data with key + constexpr void cipher(char* data, size_type size, key_type key) + { + // Obfuscate with a simple XOR cipher based on key + for (size_type i = 0; i < size; i++) + { + data[i] ^= char(key >> ((i % 8) * 8)); + } + } + + // Obfuscates a string at compile time + template + class obfuscator + { + public: + // Obfuscates the string 'data' on construction + constexpr obfuscator(const char* data) + { + // Copy data + for (size_type i = 0; i < N; i++) + { + m_data[i] = data[i]; + } + + // On construction each of the characters in the string is + // obfuscated with an XOR cipher based on key + cipher(m_data, N, KEY); + } + + constexpr const char* data() const + { + return &m_data[0]; + } + + constexpr size_type size() const + { + return N; + } + + constexpr key_type key() const + { + return KEY; + } + + private: + + char m_data[N]{}; + }; + + // Handles decryption and re-encryption of an encrypted string at runtime + template + class obfuscated_data + { + public: + obfuscated_data(const obfuscator& obfuscator) + { + // Copy obfuscated data + for (size_type i = 0; i < N; i++) + { + m_data[i] = obfuscator.data()[i]; + } + } + + ~obfuscated_data() + { + // Zero m_data to remove it from memory + for (size_type i = 0; i < N; i++) + { + m_data[i] = 0; + } + } + + // Returns a pointer to the plain text string, decrypting it if + // necessary + operator char*() + { + decrypt(); + return m_data; + } + + // Manually decrypt the string + void decrypt() + { + if (m_encrypted) + { + cipher(m_data, N, KEY); + m_encrypted = false; + } + } + + // Manually re-encrypt the string + void encrypt() + { + if (!m_encrypted) + { + cipher(m_data, N, KEY); + m_encrypted = true; + } + } + + // Returns true if this string is currently encrypted, false otherwise. + bool is_encrypted() const + { + return m_encrypted; + } + + private: + + // Local storage for the string. Call is_encrypted() to check whether or + // not the string is currently obfuscated. + char m_data[N]; + + // Whether data is currently encrypted + bool m_encrypted{ true }; + }; + + // This function exists purely to extract the number of elements 'N' in the + // array 'data' + template + constexpr auto make_obfuscator(const char(&data)[N]) + { + return obfuscator(data); + } +} + +// Obfuscates the string 'data' at compile-time and returns a reference to a +// ay::obfuscated_data object with global lifetime that has functions for +// decrypting the string and is also implicitly convertable to a char* +#define AY_OBFUSCATE(data) AY_OBFUSCATE_KEY(data, AY_OBFUSCATE_DEFAULT_KEY) + +// Obfuscates the string 'data' with 'key' at compile-time and returns a +// reference to a ay::obfuscated_data object with global lifetime that has +// functions for decrypting the string and is also implicitly convertable to a +// char* +#define AY_OBFUSCATE_KEY(data, key) \ + []() -> ay::obfuscated_data& { \ + static_assert(sizeof(decltype(key)) == sizeof(ay::key_type), "key must be a 64 bit unsigned integer"); \ + static_assert((key) >= (1ull << 56), " must span all 8 bytes"); \ + constexpr auto n = sizeof(data)/sizeof(data[0]); \ + constexpr auto obfuscator = ay::make_obfuscator(data); \ + static auto obfuscated_data = ay::obfuscated_data(obfuscator); \ + return obfuscated_data; \ + }() + +#endif diff --git a/libs/libencrypt/CMakeLists.txt b/libs/libencrypt/CMakeLists.txt new file mode 100644 index 00000000000..243ab0d2397 --- /dev/null +++ b/libs/libencrypt/CMakeLists.txt @@ -0,0 +1,51 @@ +cmake_minimum_required(VERSION 3.16) +project(libencrypt) + +find_package(PkgConfig REQUIRED) +pkg_search_module(OPENSSL REQUIRED openssl) + +#file(READ "public_key.pem" PUBLIC_KEY_CONTENTS) +file(READ "config.txt" PASSPHRASE_CONTENTS) + +#string(REPLACE "\n" "\\n" PUBLIC_KEY_CONTENTS "${PUBLIC_KEY_CONTENTS}") +string(REPLACE "\n" "\\n" PASSPHRASE_CONTENTS "${PASSPHRASE_CONTENTS}") +#set(PUBLIC_KEY "${PUBLIC_KEY_CONTENTS}") +set(PASS_PHRASE "${PASSPHRASE_CONTENTS}") +add_compile_definitions(PASS_PHRASE="${PASS_PHRASE}") + +if(OPENSSL_FOUND) + include_directories(${OPENSSL_INCLUDE_DIRS}) + message(STATUS "Using OpenSSL ${OPENSSL_VERSION}") +else() + message(FATAL_ERROR "OpenSSL not found") +endif() + +# Source files for the library +file(GLOB_RECURSE LIB_SOURCES src/*.cpp ../EXTERNAL/libpugixml/src/*.cpp) +file(GLOB_RECURSE LIB_HEADERS src/*.hpp src/*.h ../EXTERNAL/libpugixml/src/*.hpp) +set(LIB_INCLUDE_DIRS "") +foreach(_headerFile ${LIB_HEADERS}) + get_filename_component(_dir ${_headerFile} PATH) + list(APPEND LIB_INCLUDE_DIRS ${_dir}) +endforeach() +list(REMOVE_DUPLICATES LIB_INCLUDE_DIRS) + +# Create the library +#add_library(libencrypt STATIC ${LIB_HEADERS} ${LIB_SOURCES}) +#target_include_directories(libencrypt PUBLIC ${LIB_INCLUDE_DIRS}) +#set_target_properties(libencrypt PROPERTIES PREFIX "") # Avoid extra 'lib' prefix + +#target_link_libraries(libencrypt PRIVATE ${OPENSSL_LIBRARIES}) + +# Add executable +add_executable(encrypt main.cpp ${LIB_HEADERS} ${LIB_SOURCES} ) + +# Include directories containing the header files +target_include_directories(encrypt PRIVATE + ${CMAKE_CURRENT_SOURCE_DIR}/../EXTERNAL/libpugixml/src/ + ${CMAKE_CURRENT_SOURCE_DIR}/src +) +target_link_libraries(encrypt PRIVATE ${OPENSSL_LIBRARIES}) + +#install(TARGETS libencrypt DESTINATION bin) +#install(FILES ${LIB_HEADERS} DESTINATION include/libencrypt) diff --git a/libs/libencrypt/README.md b/libs/libencrypt/README.md new file mode 100644 index 00000000000..e61004cffc1 --- /dev/null +++ b/libs/libencrypt/README.md @@ -0,0 +1,71 @@ + # libencrypt (XML Encryption) + +libencrypt is a C++ library that provides XML encryption functionality using the RSA encryption algorithm. It allows you to encrypt XML data and files using a public key, perform encryption-related operations, and save the encrypted data in an XML format. + +## Prerequisites + +Before using the libencrypt library, make sure you have the following prerequisites installed: + +- C++ compiler with C++17 support +- OpenSSL library (version 1.1 or higher) + +## Installation + +To use the libencrypt library in your project, follow these steps: + +1. Clone the libencrypt repository or download the source code. + +2. Configure the library by replacing the contents of the `public_key.pem` file with your own RSA public key. Also, update the `config.txt` file with your desired passphrase. + +3. Build the library using CMake: + + ```bash + cmake . + make + +## Usage + +To use the libencrypt library in your code, follow these steps: + +1. Include the `encryption.h` header in your source file. + +2. Use the provided functions to perform XML encryption operations: + + - `loadPublicKey`: Loads a public key from a file. + - `encryptSessionKey`: Encrypts a session key using the provided public key. + - `encrypt`: Encrypts XML data using the provided public key. + - `base64_encode`: Base64 encodes a string. + - `encryptFile`: Encrypts an XML file using the provided public key. + +3. Customize the encryption process as needed based on your XML structure and encryption requirements. + +## Example + +Here's an example of how to use the libencrypt library to encrypt an XML file: + +```cpp +#include "encryption.h" + +int main() { + std::string filePath = "data.xml"; + + // Encrypt the XML file using the provided public key + bool success = Encryption::encryptFile(filePath); + + if (success) { + std::cout << "XML file encryption successful!" << std::endl; + } else { + std::cerr << "XML file encryption failed." << std::endl; + } + + return 0; + } + + +##License + +This project is licensed under the MIT License + +##Contributing + +Contributions are welcome! If you find any issues or have suggestions for improvements, please feel free to open an issue or submit a pull request. We appreciate your contributions to make this project better. \ No newline at end of file diff --git a/libs/libencrypt/config.h.in b/libs/libencrypt/config.h.in new file mode 100644 index 00000000000..709a632078f --- /dev/null +++ b/libs/libencrypt/config.h.in @@ -0,0 +1,9 @@ + +#ifndef CONFIG_H +#define CONFIG_H + +#define PUBLIC_KEY "@PUBLIC_KEY@" +#define PASSPHRASE "@PASS_PHRASE@" +// Add more configuration variables as needed + +#endif // CONFIG_H diff --git a/libs/libencrypt/config.txt b/libs/libencrypt/config.txt new file mode 100644 index 00000000000..85df50785d6 --- /dev/null +++ b/libs/libencrypt/config.txt @@ -0,0 +1 @@ +abcd \ No newline at end of file diff --git a/libs/libencrypt/main.cpp b/libs/libencrypt/main.cpp new file mode 100644 index 00000000000..e454dc56ed5 --- /dev/null +++ b/libs/libencrypt/main.cpp @@ -0,0 +1,22 @@ +#include +#include "encryption.h" + +int main(int argc, char* argv[]) { + if (argc < 2) { + std::cerr << "Usage: " << argv[0] << " \n"; + return -1; + } + + + std::string publicKeyFile = argv[1]; + std::string filePath = argv[2]; + + if (Encryption::encryptFile(publicKeyFile,filePath)) { + std::cout << "Encryption completed successfully." << std::endl; + return 0; + } else { + std::cerr << "Encryption failed." << std::endl; + return -1; + } +} + diff --git a/libs/libencrypt/public_key.pem b/libs/libencrypt/public_key.pem new file mode 100644 index 00000000000..a166d5329f9 --- /dev/null +++ b/libs/libencrypt/public_key.pem @@ -0,0 +1,9 @@ +-----BEGIN PUBLIC KEY----- +MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAqZGiAzN24Hao44eCxVgv +EBxsR8OAI7hNp7uqzPF85QNafQKCJqeGKtY7NM/w1vkaxm0uHTBCMsjdi48v0Eof +m18v3n9OBczDeTJVjwGhRz8ePurp68gLmXLBK2hFgEZUY4+08cb+K63i+BqRP7iJ +wP5iVofHY9HDpIHk+jwFSTWIArgR2+4RM95qF3i+/6zl+4uIN6oI9q9v/TqmiLTY +bzIynGeDpYhh0kM33nfxBz9xKz78kGS885HMT0ZoGrFiJmJ8AkqsNUSWF0DinA7b +MHCBrurqhmBsWFa3Rk0V74F7ofQFIK7jD/tNpXVhEqeqr0gHXzJ27xNILJ8b+rGF +LwIDAQAB +-----END PUBLIC KEY----- diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp new file mode 100644 index 00000000000..07bdae5c220 --- /dev/null +++ b/libs/libencrypt/src/encryption.cpp @@ -0,0 +1,177 @@ +#include "encryption.h" +#ifdef PASSPHRASE +std::string passphrase_enc = PASSPHRASE; +#else +std::string passphrase_enc = ""; // Set your PEM pass phrase here +#endif +/** + * @brief Loads a public key from a file. + * + * @param filename The name of the file containing the public key. + * @return RSA* A pointer to the loaded public key. + * Returns nullptr if the key file cannot be opened or there is an error reading the key. + */ +RSA* Encryption::loadPublicKey(const std::string& filename) { + + RSA* key = nullptr; + FILE* keyFile = fopen(filename.c_str(), "r"); + if (!keyFile) { + std::cerr << "Unable to open key file: " << filename << std::endl; + return nullptr; + } + + if (!PEM_read_RSA_PUBKEY(keyFile, &key, NULL, (void*)passphrase_enc.c_str())) { + std::cerr << "Error reading public key from file: " << filename << std::endl; + fclose(keyFile); + return nullptr; + } + + fclose(keyFile); + return key; +} + +/** + * @brief Encrypts a session key using the provided public key. + * + * @param key The public key used for encryption. + * @return std::string The encrypted session key. + * Returns an empty string if there is an error generating or encrypting the session key. + */ +std::string Encryption::encryptSessionKey(RSA* key) { + unsigned char sessionKey[128]; + if (!RAND_bytes(sessionKey, sizeof(sessionKey))) { + std::cerr << "Error generating session key" << std::endl; + return ""; + } + + std::vector encryptedSessionKey(RSA_size(key)); + if (RSA_public_encrypt(sizeof(sessionKey), sessionKey, encryptedSessionKey.data(), key, RSA_PKCS1_OAEP_PADDING) == -1) { + std::cerr << "Session key encryption error: " << ERR_error_string(ERR_get_error(), nullptr) << std::endl; + return ""; + } + + return std::string(reinterpret_cast(encryptedSessionKey.data()), encryptedSessionKey.size()); +} + +/** + * @brief Encrypts the given plaintext using the provided public key. + * + * @param plaintext The plaintext to be encrypted. + * @param key The public key used for encryption. + * @return std::string The encrypted ciphertext. + * Returns an empty string if there is an error during encryption. + */ +std::string Encryption::encrypt(const std::string& plaintext, RSA* key) { + int rsaLen = RSA_size(key); + int blockLen = rsaLen - 42; // PKCS1_OAEP_PADDING reduces max data length + int len = plaintext.size(); + std::string ciphertext; + + for (int i = 0; i < len; i += blockLen) { + std::vector buffer(rsaLen); + std::string substr = plaintext.substr(i, blockLen); + + if (RSA_public_encrypt(substr.size(), reinterpret_cast(substr.data()), buffer.data(), key, RSA_PKCS1_OAEP_PADDING) == -1) { + std::cerr << "Encryption error: " << ERR_error_string(ERR_get_error(), nullptr) << std::endl; + return ""; + } + + ciphertext.append(reinterpret_cast(buffer.data()), rsaLen); + } + + return ciphertext; +} + +/** + * @brief Base64 encodes the given input string. + * + * @param input The input string to be encoded. + * @return std::string The base64-encoded string. + */ +std::string Encryption::base64_encode(const std::string& input) { + BIO* b64 = BIO_new(BIO_f_base64()); + BIO_set_flags(b64, BIO_FLAGS_BASE64_NO_NL); + + BIO* bmem = BIO_new(BIO_s_mem()); + b64 = BIO_push(b64, bmem); + + BIO_write(b64, input.data(), input.size()); + BIO_flush(b64); + + BUF_MEM* bptr; + BIO_get_mem_ptr(b64, &bptr); + + std::string output(bptr->data, bptr->length); + BIO_free_all(b64); + + return output; +} + +/** + * @brief Encrypts a file using the provided public key. + * + * @param filePath The path to the file to be encrypted. + * @param publicKeyFile The path to the file containing the public key. + * @return bool True if the file encryption is successful, false otherwise. + */ +bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& filePath ) { + + // Load public key + RSA* publicKey = loadPublicKey(publicKeyFile); + if (!publicKey) { + return false; + } + + // Read file contents + std::ifstream file(filePath, std::ios::binary); + if (!file) { + std::cerr << "Unable to open file: " << filePath << std::endl; + RSA_free(publicKey); + return false; + } + + std::string plaintext((std::istreambuf_iterator(file)), std::istreambuf_iterator()); + file.close(); + + // Encrypt session key + std::string encryptedSessionKey = encryptSessionKey(publicKey); + if (encryptedSessionKey.empty()) { + RSA_free(publicKey); + return false; + } + + // Base64 encode session key + std::string base64EncryptedSessionKey = base64_encode(encryptedSessionKey); + + // Encrypt file contents + std::string encrypted = encrypt(plaintext, publicKey); + RSA_free(publicKey); + + // Base64 encode encrypted data + std::string base64Encrypted = base64_encode(encrypted); + + // Create an XML document for the encrypted data and session key + pugi::xml_document encryptedDoc; + auto root = encryptedDoc.append_child("EncryptedData"); + auto sessionKeyNode = root.append_child("SessionKey"); + sessionKeyNode.append_child(pugi::node_pcdata).set_value(base64EncryptedSessionKey.c_str()); + auto dataNode = root.append_child("Data"); + dataNode.append_child(pugi::node_pcdata).set_value(base64Encrypted.c_str()); + + + size_t lastDotPos = filePath.find_last_of('.'); + + if (lastDotPos != std::string::npos && filePath.substr(lastDotPos) == ".xml") { + // Remove the .xml extension + filePath.erase(lastDotPos); + // Append the .xmle extension + filePath.append(".xmle"); + } + // Save the encrypted data to a new file + std::string encryptedFilePath = filePath; + encryptedDoc.save_file(encryptedFilePath.c_str(), " "); + + std::cout << "File encrypted successfully. Encrypted file saved as: " << encryptedFilePath << std::endl; + + return true; +} diff --git a/libs/libencrypt/src/encryption.h b/libs/libencrypt/src/encryption.h new file mode 100644 index 00000000000..daedcdbcba2 --- /dev/null +++ b/libs/libencrypt/src/encryption.h @@ -0,0 +1,70 @@ +#ifndef ENCRYPTION_H +#define ENCRYPTION_H + +#include +#include +#include +#include +#include +#include +#include "pugixml.hpp" +#include +#include +#include +#include +#include +#include "obfuscate.h" +//#include "config.h" +/** + * @class Encryption + * @brief Provides encryption and decryption functionality using RSA encryption algorithm. + */ +class Encryption { +public: + /** + * @brief Loads a public key from a file. + * + * @param filename The name of the file containing the public key. + * @return RSA* A pointer to the loaded public key. + * Returns nullptr if the key file cannot be opened or there is an error reading the key. + */ + static RSA *loadPublicKey(const std::string &filename); + + /** + * @brief Encrypts a session key using the provided public key. + * + * @param key The public key used for encryption. + * @return std::string The encrypted session key. + * Returns an empty string if there is an error generating or encrypting the session key. + */ + static std::string encryptSessionKey(RSA *key); + + /** + * @brief Encrypts the given plaintext using the provided public key. + * + * @param plaintext The plaintext to be encrypted. + * @param key The public key used for encryption. + * @return std::string The encrypted ciphertext. + * Returns an empty string if there is an error during encryption. + */ + static std::string encrypt(const std::string &plaintext, RSA *key); + + /** + * @brief Base64 encodes the given input string. + * + * @param input The input string to be encoded. + * @return std::string The base64-encoded string. + */ + static std::string base64_encode(const std::string &input); + + /** + * @brief Encrypts a file using the provided public key. + * + * @param filePath The path to the file to be encrypted. + * @param publicKeyFile The path to the file containing the public key. + * @return bool True if the file encryption is successful, false otherwise. + */ + static bool encryptFile(const std::string& publicKeyFile, std::string &filePath); +}; + +#endif // ENCRYPTION_H diff --git a/libs/libencrypt/src/obfuscate.h b/libs/libencrypt/src/obfuscate.h new file mode 100644 index 00000000000..5450eb44f01 --- /dev/null +++ b/libs/libencrypt/src/obfuscate.h @@ -0,0 +1,185 @@ +#ifndef OBFUSCATE_H +#define OBFUSCATE_H + +#ifdef _MSC_VER + #define AY_CAT(X,Y) AY_CAT2(X,Y) + #define AY_CAT2(X,Y) X##Y + #define AY_LINE int(AY_CAT(__LINE__,U)) +#else + #define AY_LINE __LINE__ +#endif + +#ifndef AY_OBFUSCATE_DEFAULT_KEY + // The default 64 bit key to obfuscate strings with. + // This can be user specified by defining AY_OBFUSCATE_DEFAULT_KEY before + // including obfuscate.h + #define AY_OBFUSCATE_DEFAULT_KEY ay::generate_key(AY_LINE) +#endif + +namespace ay +{ + using size_type = unsigned long long; + using key_type = unsigned long long; + + // Generate a pseudo-random key that spans all 8 bytes + constexpr key_type generate_key(key_type seed) + { + // Use the MurmurHash3 64-bit finalizer to hash our seed + key_type key = seed; + key ^= (key >> 33); + key *= 0xff51afd7ed558ccd; + key ^= (key >> 33); + key *= 0xc4ceb9fe1a85ec53; + key ^= (key >> 33); + + // Make sure that a bit in each byte is set + key |= 0x0101010101010101ull; + + return key; + } + + // Obfuscates or deobfuscates data with key + constexpr void cipher(char* data, size_type size, key_type key) + { + // Obfuscate with a simple XOR cipher based on key + for (size_type i = 0; i < size; i++) + { + data[i] ^= char(key >> ((i % 8) * 8)); + } + } + + // Obfuscates a string at compile time + template + class obfuscator + { + public: + // Obfuscates the string 'data' on construction + constexpr obfuscator(const char* data) + { + // Copy data + for (size_type i = 0; i < N; i++) + { + m_data[i] = data[i]; + } + + // On construction each of the characters in the string is + // obfuscated with an XOR cipher based on key + cipher(m_data, N, KEY); + } + + constexpr const char* data() const + { + return &m_data[0]; + } + + constexpr size_type size() const + { + return N; + } + + constexpr key_type key() const + { + return KEY; + } + + private: + + char m_data[N]{}; + }; + + // Handles decryption and re-encryption of an encrypted string at runtime + template + class obfuscated_data + { + public: + obfuscated_data(const obfuscator& obfuscator) + { + // Copy obfuscated data + for (size_type i = 0; i < N; i++) + { + m_data[i] = obfuscator.data()[i]; + } + } + + ~obfuscated_data() + { + // Zero m_data to remove it from memory + for (size_type i = 0; i < N; i++) + { + m_data[i] = 0; + } + } + + // Returns a pointer to the plain text string, decrypting it if + // necessary + operator char*() + { + decrypt(); + return m_data; + } + + // Manually decrypt the string + void decrypt() + { + if (m_encrypted) + { + cipher(m_data, N, KEY); + m_encrypted = false; + } + } + + // Manually re-encrypt the string + void encrypt() + { + if (!m_encrypted) + { + cipher(m_data, N, KEY); + m_encrypted = true; + } + } + + // Returns true if this string is currently encrypted, false otherwise. + bool is_encrypted() const + { + return m_encrypted; + } + + private: + + // Local storage for the string. Call is_encrypted() to check whether or + // not the string is currently obfuscated. + char m_data[N]; + + // Whether data is currently encrypted + bool m_encrypted{ true }; + }; + + // This function exists purely to extract the number of elements 'N' in the + // array 'data' + template + constexpr auto make_obfuscator(const char(&data)[N]) + { + return obfuscator(data); + } +} + +// Obfuscates the string 'data' at compile-time and returns a reference to a +// ay::obfuscated_data object with global lifetime that has functions for +// decrypting the string and is also implicitly convertable to a char* +#define AY_OBFUSCATE(data) AY_OBFUSCATE_KEY(data, AY_OBFUSCATE_DEFAULT_KEY) + +// Obfuscates the string 'data' with 'key' at compile-time and returns a +// reference to a ay::obfuscated_data object with global lifetime that has +// functions for decrypting the string and is also implicitly convertable to a +// char* +#define AY_OBFUSCATE_KEY(data, key) \ + []() -> ay::obfuscated_data& { \ + static_assert(sizeof(decltype(key)) == sizeof(ay::key_type), "key must be a 64 bit unsigned integer"); \ + static_assert((key) >= (1ull << 56), " must span all 8 bytes"); \ + constexpr auto n = sizeof(data)/sizeof(data[0]); \ + constexpr auto obfuscator = ay::make_obfuscator(data); \ + static auto obfuscated_data = ay::obfuscated_data(obfuscator); \ + return obfuscated_data; \ + }() + +#endif diff --git a/libs/libpugiutil/CMakeLists.txt b/libs/libpugiutil/CMakeLists.txt index b7c2640c549..183afc81dad 100644 --- a/libs/libpugiutil/CMakeLists.txt +++ b/libs/libpugiutil/CMakeLists.txt @@ -17,7 +17,8 @@ target_include_directories(libpugiutil PUBLIC ${LIB_INCLUDE_DIRS}) set_target_properties(libpugiutil PROPERTIES PREFIX "") #Avoid extra 'lib' prefix target_link_libraries(libpugiutil - libpugixml) + libpugixml + libdecrypt) install(TARGETS libpugiutil DESTINATION bin) install(FILES ${LIB_HEADERS} DESTINATION include/libpugiutil) diff --git a/libs/libpugiutil/src/pugixml_loc.cpp b/libs/libpugiutil/src/pugixml_loc.cpp index b773b410b53..9be9f4f7df5 100644 --- a/libs/libpugiutil/src/pugixml_loc.cpp +++ b/libs/libpugiutil/src/pugixml_loc.cpp @@ -46,4 +46,17 @@ void loc_data::build_loc_data() { fclose(f); } + +void loc_data::build_loc_data_from_string(char* filename_val, size_t buffersize) { + std::ptrdiff_t offset = 0; + char buffer[1024]; + std::size_t size; + for (std::size_t i = 0; i < buffersize; ++i) { + if (filename_val[i] == '\0') + break; + else if (filename_val[i] == '\n') { + offsets_.push_back( i); + } + } + } } // namespace pugiutil diff --git a/libs/libpugiutil/src/pugixml_loc.hpp b/libs/libpugiutil/src/pugixml_loc.hpp index 0f597a593b1..b8e11fded7d 100644 --- a/libs/libpugiutil/src/pugixml_loc.hpp +++ b/libs/libpugiutil/src/pugixml_loc.hpp @@ -7,7 +7,8 @@ #include #include "pugixml.hpp" - +#include "decryption.h" +#include namespace pugiutil { //pugi offset to line/col data based on: https://stackoverflow.com/questions/21003471/convert-pugixmls-result-offset-to-column-line @@ -20,6 +21,10 @@ class loc_data { build_loc_data(); } + loc_data(char* filename_val, size_t buffersize) { + build_loc_data_from_string(filename_val, buffersize); + } + //The filename this location data is for const std::string& filename() const { return filename_; } const char* filename_c_str() const { return filename_.c_str(); } @@ -42,7 +47,7 @@ class loc_data { private: void build_loc_data(); - + void build_loc_data_from_string(char* filename_val, size_t buffersize); std::string filename_; std::vector offsets_; }; diff --git a/libs/libpugiutil/src/pugixml_util.cpp b/libs/libpugiutil/src/pugixml_util.cpp index d4d2a398246..8002ce620ff 100644 --- a/libs/libpugiutil/src/pugixml_util.cpp +++ b/libs/libpugiutil/src/pugixml_util.cpp @@ -8,21 +8,43 @@ namespace pugiutil { //Returns loc_data look-up for xml node line numbers loc_data load_xml(pugi::xml_document& doc, //Document object to be loaded with file contents const std::string filename) { //Filename to load from - auto location_data = loc_data(filename); - - auto load_result = doc.load_file(filename.c_str()); - if (!load_result) { - std::string msg = load_result.description(); - auto line = location_data.line(load_result.offset); - auto col = location_data.col(load_result.offset); - throw XmlError("Unable to load XML file '" + filename + "', " + msg - + " (line: " + std::to_string(line) + " col: " + std::to_string(col) + ")", - filename.c_str(), line); + //store the position of last '.' in the file name + int position = filename.find_last_of("."); + //store the characters after the '.' from the file_name string + std::string result = filename.substr(position); + if (result == ".xmle") { + Decryption E1(filename); + std::string fn_file = E1.getDecryptedContent(); + size_t buffersize = fn_file.size(); + char* final = new char[buffersize]; + strcpy(final, fn_file.c_str()); + auto location_data = loc_data(final, buffersize); + auto load_result = doc.load_buffer(final, buffersize); + if (!load_result) { + std::string msg = load_result.description(); + auto line = location_data.line(load_result.offset); + auto col = location_data.col(load_result.offset); + throw XmlError("Unable to load XML file '" + filename + "', " + msg + + " (line: " + std::to_string(line) + " col: " + std::to_string(col) + ")", + filename.c_str(), line); + } + delete (final); + return location_data; + } else { + //auto location_data = loc_data(end_result_fname); + auto location_data = loc_data(filename); + auto load_result = doc.load_file(filename.c_str()); + if (!load_result) { + std::string msg = load_result.description(); + auto line = location_data.line(load_result.offset); + auto col = location_data.col(load_result.offset); + throw XmlError("Unable to load XML file '" + filename + "', " + msg + + " (line: " + std::to_string(line) + " col: " + std::to_string(col) + ")", + filename.c_str(), line); + } + return location_data; } - - return location_data; } - //Gets the first child element of the given name and returns it. // // node - The parent xml node From 590e509df8c7d0428e089b048fd192f102cc300e Mon Sep 17 00:00:00 2001 From: Nadeem Yaseen <86344264+nadeemyaseen-rs@users.noreply.github.com> Date: Tue, 25 Jul 2023 15:35:00 +0500 Subject: [PATCH 150/453] Update install_dependencies.sh to install openssl --- .github/scripts/install_dependencies.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/scripts/install_dependencies.sh b/.github/scripts/install_dependencies.sh index e0acc3255db..6f936c0cd60 100755 --- a/.github/scripts/install_dependencies.sh +++ b/.github/scripts/install_dependencies.sh @@ -56,7 +56,8 @@ sudo apt install -y \ clang-13 \ clang-14 \ clang-format-14 \ - libtbb-dev + libtbb-dev \ + openssl pip install -r requirements.txt From a64640fefa6d682cb2c7a9fefcafbd17a3e4051a Mon Sep 17 00:00:00 2001 From: behzadmehmood-rs Date: Mon, 31 Jul 2023 12:26:57 +0500 Subject: [PATCH 151/453] Code formatting --- libs/libpugiutil/src/pugixml_loc.cpp | 11 +++++------ .../tileable_rr_graph/rr_graph_builder_utils.cpp | 15 ++++++++++----- .../tileable_rr_graph/rr_graph_builder_utils.h | 15 ++++++++++----- 3 files changed, 25 insertions(+), 16 deletions(-) diff --git a/libs/libpugiutil/src/pugixml_loc.cpp b/libs/libpugiutil/src/pugixml_loc.cpp index 9be9f4f7df5..5a86d3f3409 100644 --- a/libs/libpugiutil/src/pugixml_loc.cpp +++ b/libs/libpugiutil/src/pugixml_loc.cpp @@ -46,17 +46,16 @@ void loc_data::build_loc_data() { fclose(f); } - void loc_data::build_loc_data_from_string(char* filename_val, size_t buffersize) { std::ptrdiff_t offset = 0; char buffer[1024]; std::size_t size; for (std::size_t i = 0; i < buffersize; ++i) { - if (filename_val[i] == '\0') - break; - else if (filename_val[i] == '\n') { - offsets_.push_back( i); - } + if (filename_val[i] == '\0') + break; + else if (filename_val[i] == '\n') { + offsets_.push_back(i); } } +} } // namespace pugiutil diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 1f04e5d9c90..6388b07e5a7 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -31,7 +31,8 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width) { * Get the class index of a grid pin ***********************************************************************/ int get_grid_pin_class_index(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const int pin_index) { /* check */ t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); @@ -64,7 +65,8 @@ e_side determine_io_grid_pin_side(const vtr::Point& device_size, /* Deteremine the side of a pin of a grid */ std::vector find_grid_pin_sides(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const size_t& pin_id) { std::vector pin_sides; @@ -86,7 +88,8 @@ std::vector find_grid_pin_sides(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ std::vector get_grid_side_pins(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, @@ -112,7 +115,8 @@ std::vector get_grid_side_pins(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ size_t get_grid_num_pins(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const e_pin_type& pin_type, const e_side& io_side) { size_t num_pins = 0; @@ -143,7 +147,8 @@ size_t get_grid_num_pins(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ size_t get_grid_num_classes(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const e_pin_type& pin_type) { size_t num_classes = 0; diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index a3e6bd71375..acdd16841ad 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -15,30 +15,35 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width); int get_grid_pin_class_index(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const int pin_index); std::vector find_grid_pin_sides(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const size_t& pin_id); e_side determine_io_grid_pin_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate); std::vector get_grid_side_pins(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, const int& pin_height); size_t get_grid_num_pins(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const e_pin_type& pin_type, const e_side& io_side); size_t get_grid_num_classes(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& x, + const size_t& y, const e_pin_type& pin_type); bool is_chanx_exist(const DeviceGrid& grids, From 457df492e9bdcfe0b68415a67f9e3d035c402174 Mon Sep 17 00:00:00 2001 From: Nadeem Yaseen <86344264+nadeemyaseen-rs@users.noreply.github.com> Date: Mon, 31 Jul 2023 15:39:14 +0500 Subject: [PATCH 152/453] Update CMakeLists.txt to 3.5 --- libs/EXTERNAL/capnproto/c++/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/EXTERNAL/capnproto/c++/CMakeLists.txt b/libs/EXTERNAL/capnproto/c++/CMakeLists.txt index 548dfd1fe7a..92534f800c7 100644 --- a/libs/EXTERNAL/capnproto/c++/CMakeLists.txt +++ b/libs/EXTERNAL/capnproto/c++/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.4) +cmake_minimum_required(VERSION 3.5) project("Cap'n Proto" CXX) set(VERSION 0.9.1) From e4bbcf5c143fd3542009b7909564a04a483b486d Mon Sep 17 00:00:00 2001 From: Nadeem Yaseen <86344264+nadeemyaseen-rs@users.noreply.github.com> Date: Mon, 31 Jul 2023 15:50:20 +0500 Subject: [PATCH 153/453] Update CMakeLists.txt to bump the minimum version --- abc/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc/CMakeLists.txt b/abc/CMakeLists.txt index 7cf6f19af1e..e03f49ff0af 100644 --- a/abc/CMakeLists.txt +++ b/abc/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.3.0) +cmake_minimum_required(VERSION 3.5) include(CMakeParseArguments) include(CheckCCompilerFlag) From c8f515070ab13d68c05e1f65473f2cdc04de54cb Mon Sep 17 00:00:00 2001 From: Nadeem Yaseen <86344264+nadeemyaseen-rs@users.noreply.github.com> Date: Mon, 31 Jul 2023 15:51:37 +0500 Subject: [PATCH 154/453] Update CMakeLists.txt to bump the version --- abc/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc/CMakeLists.txt b/abc/CMakeLists.txt index 7cf6f19af1e..e03f49ff0af 100644 --- a/abc/CMakeLists.txt +++ b/abc/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.3.0) +cmake_minimum_required(VERSION 3.5) include(CMakeParseArguments) include(CheckCCompilerFlag) From 0f4d83ca1d98693e41f3cd6141a88bd10923f862 Mon Sep 17 00:00:00 2001 From: Nadeem Yaseen <86344264+nadeemyaseen-rs@users.noreply.github.com> Date: Mon, 31 Jul 2023 16:11:47 +0500 Subject: [PATCH 155/453] Update CMakeLists.txt to bump the CMake version --- libs/EXTERNAL/capnproto/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/EXTERNAL/capnproto/CMakeLists.txt b/libs/EXTERNAL/capnproto/CMakeLists.txt index eb40764019a..02c082aa277 100644 --- a/libs/EXTERNAL/capnproto/CMakeLists.txt +++ b/libs/EXTERNAL/capnproto/CMakeLists.txt @@ -1,3 +1,3 @@ -cmake_minimum_required(VERSION 3.4) +cmake_minimum_required(VERSION 3.5) project("Cap'n Proto Root" CXX) add_subdirectory(c++) From 00ebcfe176fa737b7162cb5560b33598424b7d18 Mon Sep 17 00:00:00 2001 From: Nadeem Yaseen <86344264+nadeemyaseen-rs@users.noreply.github.com> Date: Tue, 1 Aug 2023 12:17:38 +0500 Subject: [PATCH 156/453] Update hostsetup.sh to install openssl --- .github/scripts/hostsetup.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/scripts/hostsetup.sh b/.github/scripts/hostsetup.sh index 48f56a066a9..1a69181dc4a 100755 --- a/.github/scripts/hostsetup.sh +++ b/.github/scripts/hostsetup.sh @@ -69,7 +69,8 @@ apt install -y \ default-jdk \ g++-9 \ gcc-9 \ - wget + wget \ + openssl # installing the latest version of cmake apt install -y apt-transport-https ca-certificates gnupg From 62cf03427cdc5a14b5268f188c38c15cc33476eb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Aug 2023 21:23:42 -0700 Subject: [PATCH 157/453] [lib] syntax due to the layer support --- libs/librrgraph/src/base/rr_graph_builder.cpp | 15 ++++++++------- libs/librrgraph/src/base/rr_graph_builder.h | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 1f7f98d96b7..ec7d66cab18 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -72,7 +72,7 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { } } -RRNodeId RRGraphBuilder::create_node(int x, int y, t_rr_type type, int ptc, e_side side) { +RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side) { e_side node_side = SIDES[0]; /* Only OPIN and IPIN nodes have sides, otherwise force to use a default side */ if (OPIN == type || IPIN == type) { @@ -81,6 +81,7 @@ RRNodeId RRGraphBuilder::create_node(int x, int y, t_rr_type type, int ptc, e_si node_storage_.emplace_back(); node_ptc_nums_.emplace_back(); RRNodeId new_node = RRNodeId(node_storage_.size() - 1); + node_storage_.set_node_layer(new_node, layer); node_storage_.set_node_type(new_node, type); node_storage_.set_node_coordinates(new_node, x, y, x, y); node_storage_.set_node_ptc_num(new_node, ptc); @@ -89,9 +90,9 @@ RRNodeId RRGraphBuilder::create_node(int x, int y, t_rr_type type, int ptc, e_si } /* Special for CHANX, being consistent with the rule in find_node() */ if (CHANX == type) { - node_lookup_.add_node(new_node, y, x, type, ptc, node_side); + node_lookup_.add_node(new_node, layer, y, x, type, ptc, node_side); } else { - node_lookup_.add_node(new_node, x, y, type, ptc, node_side); + node_lookup_.add_node(new_node, layer, x, y, type, ptc, node_side); } return new_node; @@ -189,8 +190,8 @@ void RRGraphBuilder::reorder_nodes(e_rr_node_reorder_algorithm reorder_rr_graph_ }); } -void RRGraphBuilder::create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch) { - edges_to_build_.emplace_back(src, dest, size_t(edge_switch)); +void RRGraphBuilder::create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch, bool remapped) { + edges_to_build_.emplace_back(src, dest, size_t(edge_switch), remapped); is_edge_dirty_ = true; /* Adding a new edge revokes the flag */ is_incoming_edge_dirty_ = true; } @@ -273,10 +274,10 @@ void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { */ if (CHANX == node_storage_.node_type(node)) { ptc = node_ptc_nums_[node][x - node_storage_.node_xlow(node)]; - node_lookup_.add_node(node, y, x, CHANX, ptc); + node_lookup_.add_node(node, node_storage_.node_layer(node), y, x, CHANX, ptc); } else if (CHANY == node_storage_.node_type(node)) { ptc = node_ptc_nums_[node][y - node_storage_.node_ylow(node)]; - node_lookup_.add_node(node, x, y, CHANY, ptc); + node_lookup_.add_node(node, node_storage_.node_layer(node), x, y, CHANY, ptc); } } } diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index ebede4da95c..5a505c7dd43 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -122,7 +122,7 @@ class RRGraphBuilder { /** @brief Create a new rr_node in the node storage and register it to the node look-up. * Return a valid node id if succeed. Otherwise, return an invalid id. */ - RRNodeId create_node(int x, int y, t_rr_type type, int ptc, e_side side = NUM_SIDES); + RRNodeId create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side = NUM_SIDES); /** * @brief Add an existing rr_node in the node storage to the node look-up * @@ -233,7 +233,7 @@ class RRGraphBuilder { /** @brief Add a new edge to the cache of edges to be built * .. note:: This will not add an edge to storage! You need to call build_edges() after all the edges are cached! */ - void create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch); + void create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch, bool remapped); /** @brief Allocate and build actual edges in storage. * Once called, the cached edges will be uniquified and added to routing resource nodes, From cd82740c8d8026a986b6f06def0796e0d875d35d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Aug 2023 21:26:46 -0700 Subject: [PATCH 158/453] [core] remove dead data type (not sure why git merge does not apply automatically) --- vpr/src/base/vpr_types.h | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 34904773707..9c9e862517d 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1644,33 +1644,6 @@ constexpr bool is_pin(e_rr_type type) { return (type == IPIN || type == OPIN); } constexpr bool is_chan(e_rr_type type) { return (type == CHANX || type == CHANY); } constexpr bool is_src_sink(e_rr_type type) { return (type == SOURCE || type == SINK); } -/** - * @brief Basic element used to store the traceback (routing) of each net. - * - * @param index Array index (ID) of this routing resource node. - * @param net_pin_index: Net pin index associated with the node. This value - * ranges from 1 to fanout [1..num_pins-1]. For cases when - * different speed paths are taken to the same SINK for - * different pins, node index cannot uniquely identify - * each SINK, so the net pin index guarantees an unique - * identification for each SINK node. For non-SINK nodes - * and for SINK nodes with no associated net pin index - * (i.e. special SINKs like the source of a clock tree - * which do not correspond to an actual netlist connection), - * the value for this member should be set to OPEN (-1). - * @param iswitch Index of the switch type used to go from this rr_node to - * the next one in the routing. OPEN if there is no next node - * (i.e. this node is the last one (a SINK) in a branch of the - * net's routing). - * @param next Pointer to the next traceback element in this route. - */ -struct t_trace { - t_trace* next; - int index; - int net_pin_index = OPEN; - short iswitch; -}; - /** * @brief Extra information about each rr_node needed only during routing * (i.e. during the maze expansion). From af4588ca49d5550bae2bb6732ee2413782c1c7d0 Mon Sep 17 00:00:00 2001 From: umariqbal-rs Date: Tue, 8 Aug 2023 10:27:02 +0500 Subject: [PATCH 159/453] resolving conflicts --- abc/CMakeLists.txt | 2 +- libs/EXTERNAL/capnproto/CMakeLists.txt | 2 +- libs/EXTERNAL/capnproto/c++/CMakeLists.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/abc/CMakeLists.txt b/abc/CMakeLists.txt index e03f49ff0af..300ce808cbb 100644 --- a/abc/CMakeLists.txt +++ b/abc/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.3.0...3.13) # ! This line is edited to get rid of a CMake deprecation error include(CMakeParseArguments) include(CheckCCompilerFlag) diff --git a/libs/EXTERNAL/capnproto/CMakeLists.txt b/libs/EXTERNAL/capnproto/CMakeLists.txt index 02c082aa277..17f12819f94 100644 --- a/libs/EXTERNAL/capnproto/CMakeLists.txt +++ b/libs/EXTERNAL/capnproto/CMakeLists.txt @@ -1,3 +1,3 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.4...3.13) # ! This line is edited to get rid of a CMake deprecation error project("Cap'n Proto Root" CXX) add_subdirectory(c++) diff --git a/libs/EXTERNAL/capnproto/c++/CMakeLists.txt b/libs/EXTERNAL/capnproto/c++/CMakeLists.txt index 92534f800c7..2acc7811582 100644 --- a/libs/EXTERNAL/capnproto/c++/CMakeLists.txt +++ b/libs/EXTERNAL/capnproto/c++/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.4...3.13) # ! This line is edited to get rid of a CMake deprecation error project("Cap'n Proto" CXX) set(VERSION 0.9.1) From 30aa1b8de6196a16649da9cfe6c4b20bc67e2240 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Aug 2023 22:53:00 -0700 Subject: [PATCH 160/453] [core] adapting tileable rr_graph to layers --- libs/librrgraph/src/base/rr_graph_builder.h | 5 - .../rr_graph_builder_utils.cpp | 46 +++--- .../rr_graph_builder_utils.h | 16 +- .../tileable_rr_graph/rr_graph_view_util.cpp | 16 +- .../tileable_rr_graph/rr_graph_view_util.h | 1 + .../tileable_rr_graph_builder.cpp | 8 +- .../tileable_rr_graph_edge_builder.cpp | 37 +++-- .../tileable_rr_graph_edge_builder.h | 4 + .../tileable_rr_graph_gsb.cpp | 43 +++-- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 1 + .../tileable_rr_graph_node_builder.cpp | 154 ++++++++++-------- .../tileable_rr_graph_node_builder.h | 3 +- 12 files changed, 196 insertions(+), 138 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 5a505c7dd43..e36b70449e0 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -197,11 +197,6 @@ class RRGraphBuilder { node_storage_.set_node_ptc_num(id, new_ptc_num); } - /** @brief set the layer number at which RRNodeId is located at */ - inline void set_node_layer(RRNodeId id, int layer){ - node_storage_.set_node_layer(id, layer); - } - /** @brief set_node_pin_num() is designed for logic blocks, which are IPIN and OPIN nodes */ inline void set_node_pin_num(RRNodeId id, int new_pin_num) { node_storage_.set_node_pin_num(id, new_pin_num); diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 1f04e5d9c90..3aa3289bf9a 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -31,10 +31,11 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width) { * Get the class index of a grid pin ***********************************************************************/ int get_grid_pin_class_index(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const int pin_index) { /* check */ - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + t_physical_tile_loc tile_loc(x, y, layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); VTR_ASSERT(pin_index < phy_tile_type->num_pins); return phy_tile_type->pin_class[pin_index]; } @@ -64,13 +65,14 @@ e_side determine_io_grid_pin_side(const vtr::Point& device_size, /* Deteremine the side of a pin of a grid */ std::vector find_grid_pin_sides(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const size_t& pin_id) { std::vector pin_sides; - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); - int width_offset = grids.get_width_offset(x, y); - int height_offset = grids.get_height_offset(x, y); + t_physical_tile_loc tile_loc(x, y, layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); + int width_offset = grids.get_width_offset(tile_loc); + int height_offset = grids.get_height_offset(tile_loc); for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { if (true == phy_tile_type->pinloc[width_offset][height_offset][size_t(side)][pin_id]) { pin_sides.push_back(side); @@ -86,7 +88,7 @@ std::vector find_grid_pin_sides(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ std::vector get_grid_side_pins(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, @@ -95,7 +97,7 @@ std::vector get_grid_side_pins(const DeviceGrid& grids, /* Make sure a clear start */ pin_list.clear(); - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); for (int ipin = 0; ipin < phy_tile_type->num_pins; ++ipin) { int class_id = phy_tile_type->pin_class[ipin]; if ((1 == phy_tile_type->pinloc[pin_width][pin_height][pin_side][ipin]) @@ -112,13 +114,13 @@ std::vector get_grid_side_pins(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ size_t get_grid_num_pins(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& io_side) { size_t num_pins = 0; /* For IO_TYPE sides */ - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { /* skip unwanted sides */ if ((true == is_io_type(phy_tile_type)) @@ -128,7 +130,7 @@ size_t get_grid_num_pins(const DeviceGrid& grids, /* Get pin list */ for (int width = 0; width < phy_tile_type->width; ++width) { for (int height = 0; height < phy_tile_type->height; ++height) { - std::vector pin_list = get_grid_side_pins(grids, x, y, pin_type, side, width, height); + std::vector pin_list = get_grid_side_pins(grids, layer, x, y, pin_type, side, width, height); num_pins += pin_list.size(); } } @@ -143,11 +145,11 @@ size_t get_grid_num_pins(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ size_t get_grid_num_classes(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type) { size_t num_classes = 0; - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { /* Bypass unmatched pin_type */ if (pin_type != phy_tile_type->class_inf[iclass].type) { @@ -185,6 +187,7 @@ size_t get_grid_num_classes(const DeviceGrid& grids, * When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block ***********************************************************************/ bool is_chanx_exist(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel) { if ((1 > chanx_coord.x()) || (chanx_coord.x() > grids.width() - 2)) { @@ -199,7 +202,7 @@ bool is_chanx_exist(const DeviceGrid& grids, return true; } - return (grids.get_height_offset(chanx_coord.x(), chanx_coord.y()) == grids.get_physical_type(chanx_coord.x(), chanx_coord.y())->height - 1); + return (grids.get_height_offset(t_physical_tile_loc(chanx_coord.x(), chanx_coord.y(), layer)) == grids.get_physical_type(t_physical_tile_loc(chanx_coord.x(), chanx_coord.y(), layer))->height - 1); } /************************************************************************ @@ -223,6 +226,7 @@ bool is_chanx_exist(const DeviceGrid& grids, * unless it falls out of the grid array ***********************************************************************/ bool is_chany_exist(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel) { if (chany_coord.x() > grids.width() - 2) { @@ -237,7 +241,7 @@ bool is_chany_exist(const DeviceGrid& grids, return true; } - return (grids.get_width_offset(chany_coord.x(), chany_coord.y()) == grids.get_physical_type(chany_coord.x(), chany_coord.y())->width - 1); + return (grids.get_width_offset(t_physical_tile_loc(chany_coord.x(), chany_coord.y(), layer)) == grids.get_physical_type(t_physical_tile_loc(chany_coord.x(), chany_coord.y(), layer))->width - 1); } /************************************************************************ @@ -254,6 +258,7 @@ bool is_chany_exist(const DeviceGrid& grids, * +-----------------+ ***********************************************************************/ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel) { VTR_ASSERT(0 < chanx_coord.x()); @@ -267,7 +272,7 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ vtr::Point left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y()); - if (false == is_chanx_exist(grids, left_chanx_coord)) { + if (false == is_chanx_exist(grids, layer, left_chanx_coord)) { return true; } } @@ -289,6 +294,7 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, * +-----------------+ ***********************************************************************/ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel) { VTR_ASSERT(chanx_coord.x() < grids.width() - 1); @@ -302,7 +308,7 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ vtr::Point right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y()); - if (false == is_chanx_exist(grids, right_chanx_coord)) { + if (false == is_chanx_exist(grids, layer, right_chanx_coord)) { return true; } } @@ -329,6 +335,7 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, * +-----------------+ ***********************************************************************/ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel) { VTR_ASSERT(0 < chany_coord.y()); @@ -342,7 +349,7 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the bottom neighbor of chany, if it does not exist, the chany is top to a multi-height grid */ vtr::Point bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1); - if (false == is_chany_exist(grids, bottom_chany_coord)) { + if (false == is_chany_exist(grids, layer, bottom_chany_coord)) { return true; } } @@ -369,6 +376,7 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, * ***********************************************************************/ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel) { VTR_ASSERT(chany_coord.y() < grids.height() - 1); @@ -382,7 +390,7 @@ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */ vtr::Point top_chany_coord(chany_coord.x(), chany_coord.y() + 1); - if (false == is_chany_exist(grids, top_chany_coord)) { + if (false == is_chany_exist(grids, layer, top_chany_coord)) { return true; } } diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index a3e6bd71375..c21f3419cc2 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -15,53 +15,59 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width); int get_grid_pin_class_index(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const int pin_index); std::vector find_grid_pin_sides(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const size_t& pin_id); e_side determine_io_grid_pin_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate); std::vector get_grid_side_pins(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, const int& pin_height); size_t get_grid_num_pins(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& io_side); size_t get_grid_num_classes(const DeviceGrid& grids, - const size_t& x, const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type); bool is_chanx_exist(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel = false); bool is_chany_exist(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel = false); bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel); bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel); bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel); bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel); diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 4266420be52..025fb75992f 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -88,6 +88,7 @@ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, **********************************************************************/ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const DeviceGrid& device_grid, + const size_t& layer, const int& x, const int& y, const t_rr_type& rr_type, @@ -104,23 +105,24 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, VTR_ASSERT(side != NUM_SIDES); /* Find all the pins on the side of the grid */ - int width_offset = device_grid.get_width_offset(x, y); - int height_offset = device_grid.get_height_offset(x, y); - for (int pin = 0; pin < device_grid.get_physical_type(x, y)->num_pins; ++pin) { + t_physical_tile_loc tile_loc(x, y, layer); + int width_offset = device_grid.get_width_offset(tile_loc); + int height_offset = device_grid.get_height_offset(tile_loc); + for (int pin = 0; pin < device_grid.get_physical_type(tile_loc)->num_pins; ++pin) { /* Skip those pins have been ignored during rr_graph build-up */ - if (true == device_grid.get_physical_type(x, y)->is_ignored_pin[pin]) { + if (true == device_grid.get_physical_type(tile_loc)->is_ignored_pin[pin]) { /* If specified, force to include all the clock pins */ - if (!include_clock || std::find(device_grid.get_physical_type(x, y)->get_clock_pins_indices().begin(), device_grid.get_physical_type(x, y)->get_clock_pins_indices().end(), pin) == device_grid.get_physical_type(x, y)->get_clock_pins_indices().end()) { + if (!include_clock || std::find(device_grid.get_physical_type(tile_loc)->get_clock_pins_indices().begin(), device_grid.get_physical_type(tile_loc)->get_clock_pins_indices().end(), pin) == device_grid.get_physical_type(tile_loc)->get_clock_pins_indices().end()) { continue; } } - if (false == device_grid.get_physical_type(x, y)->pinloc[width_offset][height_offset][side][pin]) { + if (false == device_grid.get_physical_type(tile_loc)->pinloc[width_offset][height_offset][side][pin]) { /* Not the pin on this side, we skip */ continue; } /* Try to find the rr node */ - RRNodeId rr_node_index = rr_graph.node_lookup().find_node(x, y, rr_type, pin, side); + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(layer, x, y, rr_type, pin, side); if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); } diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.h b/vpr/src/tileable_rr_graph/rr_graph_view_util.h index ec7d352aa49..1e194816eaf 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.h +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.h @@ -26,6 +26,7 @@ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const DeviceGrid& device_grid, + const size_t& layer, const int& x, const int& y, const t_rr_type& rr_type, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index bcb8c7b0690..d200a27f822 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -148,7 +148,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ ************************/ alloc_tileable_rr_graph_nodes(device_ctx.rr_graph_builder, rr_node_driver_switches, - grids, + grids, 0, device_chan_width, segment_inf, through_channel); @@ -161,7 +161,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ rr_node_driver_switches, rr_node_track_ids, device_ctx.rr_rc_data, - grids, + grids, 0, device_chan_width, segment_inf, wire_to_ipin_rr_switch, @@ -234,7 +234,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ build_rr_graph_edges(device_ctx.rr_graph, device_ctx.rr_graph_builder, rr_node_driver_switches, - grids, + grids, 0, device_chan_width, segment_inf, Fc_in, Fc_out, @@ -257,7 +257,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ clb2clb_directs.push_back(clb_to_clb_directs[idirect]); } - build_rr_graph_direct_connections(device_ctx.rr_graph, device_ctx.rr_graph_builder, device_ctx.grid, delayless_rr_switch, + build_rr_graph_direct_connections(device_ctx.rr_graph, device_ctx.rr_graph_builder, device_ctx.grid, 0, delayless_rr_switch, arch_directs, clb2clb_directs); /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 3c409ee01fb..b9ee74830c1 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -23,6 +23,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const size_t& layer, size_t& num_edges_to_create) { size_t edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { @@ -33,16 +34,18 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, /* Now, we have an OPIN node, we get the source node index */ short xlow = rr_graph.node_xlow(node); short ylow = rr_graph.node_ylow(node); - short src_node_class_num = get_grid_pin_class_index(grids, xlow, ylow, + short src_node_class_num = get_grid_pin_class_index(grids, layer, xlow, ylow, rr_graph.node_pin_num(node)); /* Create edges between SOURCE and OPINs */ - RRNodeId src_node = rr_graph.node_lookup().find_node(xlow - grids.get_width_offset(xlow, ylow), - ylow - grids.get_height_offset(xlow, ylow), + t_physical_tile_loc tile_loc(xlow, ylow, layer); + RRNodeId src_node = rr_graph.node_lookup().find_node(layer, + xlow - grids.get_width_offset(tile_loc), + ylow - grids.get_height_offset(tile_loc), SOURCE, src_node_class_num); VTR_ASSERT(true == rr_graph.valid_node(src_node)); /* add edges to the src_node */ - rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node]); + rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node], false); edge_count++; } /* Allocate edges for all the source nodes */ @@ -58,6 +61,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const size_t& layer, size_t& num_edges_to_create) { size_t edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { @@ -68,16 +72,18 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, /* Now, we have an OPIN node, we get the source node index */ short xlow = rr_graph.node_xlow(node); short ylow = rr_graph.node_ylow(node); - short sink_node_class_num = get_grid_pin_class_index(grids, xlow, ylow, + short sink_node_class_num = get_grid_pin_class_index(grids, layer, xlow, ylow, rr_graph.node_pin_num(node)); /* 1. create edges between IPINs and SINKs */ - const RRNodeId& sink_node = rr_graph.node_lookup().find_node(xlow - grids.get_width_offset(xlow, ylow), - ylow - grids.get_height_offset(xlow, ylow), + t_physical_tile_loc tile_loc(xlow, ylow, 0); + const RRNodeId& sink_node = rr_graph.node_lookup().find_node(layer, + xlow - grids.get_width_offset(tile_loc), + ylow - grids.get_height_offset(tile_loc), SINK, sink_node_class_num, SIDES[0]); VTR_ASSERT(true == rr_graph.valid_node(sink_node)); /* add edges to connect the IPIN node to SINK nodes */ - rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node]); + rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node], false); edge_count++; } /* Allocate edges for all the source nodes */ @@ -99,6 +105,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, const std::vector>& Fc_in, @@ -110,8 +117,8 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const bool& wire_opposite_side) { size_t num_edges_to_create = 0; /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ - build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, num_edges_to_create); - build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, num_edges_to_create); + build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); @@ -156,24 +163,26 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, void build_rr_graph_direct_connections(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, + const size_t& layer, const RRSwitchId& delayless_switch, const std::vector& directs, const std::vector& clb_to_clb_directs) { for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); /* Skip EMPTY tiles */ - if (true == is_empty_type(grids.get_physical_type(ix, iy))) { + if (true == is_empty_type(grids.get_physical_type(tile_loc))) { continue; } /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(ix, iy)) - || (0 < grids.get_height_offset(ix, iy))) { + if ((0 < grids.get_width_offset(tile_loc)) + || (0 < grids.get_height_offset(tile_loc))) { continue; } vtr::Point from_grid_coordinate(ix, iy); build_direct_connections_for_one_gsb(rr_graph, rr_graph_builder, - grids, + grids, layer, from_grid_coordinate, delayless_switch, directs, clb_to_clb_directs); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 9e56e33ca19..d1e66a3c1b5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -24,6 +24,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, const std::vector>& Fc_in, @@ -37,6 +38,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, void build_rr_graph_direct_connections(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, + const size_t& layer, const RRSwitchId& delayless_switch, const std::vector& directs, const std::vector& clb_to_clb_directs); @@ -45,12 +47,14 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const size_t& layer, size_t& num_edges_to_create); void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const size_t& layer, size_t& num_edges_to_create); #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 335f9e2c0d9..eedbc972678 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -937,7 +937,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ /* add edges to the opin_node */ for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) { - rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]); + rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node], false); edge_count++; } } @@ -952,7 +952,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { - rr_graph_builder.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]); + rr_graph_builder.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node], false); edge_count++; } } @@ -962,7 +962,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { - rr_graph_builder.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]); + rr_graph_builder.create_edge(chan_node, track_node, rr_node_driver_switches[track_node], false); edge_count++; } } @@ -1212,12 +1212,13 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, /* Find the ipin/opin nodes */ for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); + t_physical_tile_loc ipin_node_phy_tile_loc(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node), 0); /* Skip EMPTY type */ - if (true == is_empty_type(grids.get_physical_type(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node)))) { + if (true == is_empty_type(grids.get_physical_type(ipin_node_phy_tile_loc))) { continue; } - int grid_type_index = grids.get_physical_type(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node))->index; + int grid_type_index = grids.get_physical_type(ipin_node_phy_tile_loc)->index; /* Get Fc of the ipin */ /* skip Fc = 0 or unintialized, those pins are in the */ bool skip_conn2track = true; @@ -1291,11 +1292,12 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, /* Find the ipin/opin nodes */ for (size_t inode = 0; inode < num_opin_nodes; ++inode) { const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode); + t_physical_tile_loc opin_node_phy_tile_loc(rr_graph.node_xlow(opin_node), rr_graph.node_ylow(opin_node), 0); /* Skip EMPTY type */ - if (true == is_empty_type(grids.get_physical_type(rr_graph.node_xlow(opin_node), rr_graph.node_ylow(opin_node)))) { + if (true == is_empty_type(grids.get_physical_type(opin_node_phy_tile_loc))) { continue; } - int grid_type_index = grids.get_physical_type(rr_graph.node_xlow(opin_node), rr_graph.node_ylow(opin_node))->index; + int grid_type_index = grids.get_physical_type(opin_node_phy_tile_loc)->index; /* Get Fc of the ipin */ /* skip Fc = 0 or unintialized, those pins are in the */ @@ -1338,13 +1340,14 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& from_grid_coordinate, const RRSwitchId& delayless_switch, const std::vector& directs, const std::vector& clb_to_clb_directs) { VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); - t_physical_tile_type_ptr grid_type = grids.get_physical_type(from_grid_coordinate.x(), from_grid_coordinate.y()); + t_physical_tile_type_ptr grid_type = grids.get_physical_type(t_physical_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer)); /* Iterate through all direct connections */ for (size_t i = 0; i < directs.size(); ++i) { @@ -1360,7 +1363,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, from_grid_coordinate.y() + directs[i].y_offset); /* Bypass unmatched direct clb-to-clb connections */ - t_physical_tile_type_ptr to_grid_type = grids.get_physical_type(to_grid_coordinate.x(), to_grid_coordinate.y()); + t_physical_tile_type_ptr to_grid_type = grids.get_physical_type(t_physical_tile_loc(to_grid_coordinate.x(), to_grid_coordinate.y(), layer)); /* Check if to_grid if the same grid */ if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { continue; @@ -1403,30 +1406,34 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, } /* Get the pin index in the rr_graph */ - int from_grid_width_ofs = grids.get_width_offset(from_grid_coordinate.x(), from_grid_coordinate.y()); - int from_grid_height_ofs = grids.get_height_offset(from_grid_coordinate.x(), from_grid_coordinate.y()); - int to_grid_width_ofs = grids.get_width_offset(to_grid_coordinate.x(), to_grid_coordinate.y()); - int to_grid_height_ofs = grids.get_height_offset(to_grid_coordinate.x(), to_grid_coordinate.y()); + t_physical_tile_loc from_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer); + int from_grid_width_ofs = grids.get_width_offset(from_tile_loc); + int from_grid_height_ofs = grids.get_height_offset(from_tile_loc); + t_physical_tile_loc to_tile_loc(to_grid_coordinate.x(), to_grid_coordinate.y(), layer); + int to_grid_width_ofs = grids.get_width_offset(to_tile_loc); + int to_grid_height_ofs = grids.get_height_offset(to_tile_loc); /* Find the side of grid pins, the pin location should be unique! * Pin location is required by searching a node in rr_graph */ - std::vector opin_grid_side = find_grid_pin_sides(grids, from_grid_coordinate.x(), from_grid_coordinate.y(), opin); + std::vector opin_grid_side = find_grid_pin_sides(grids, layer, from_grid_coordinate.x(), from_grid_coordinate.y(), opin); VTR_ASSERT(1 == opin_grid_side.size()); - std::vector ipin_grid_side = find_grid_pin_sides(grids, to_grid_coordinate.x(), to_grid_coordinate.y(), ipin); + std::vector ipin_grid_side = find_grid_pin_sides(grids, layer, to_grid_coordinate.x(), to_grid_coordinate.y(), ipin); VTR_ASSERT(1 == ipin_grid_side.size()); - RRNodeId opin_node_id = rr_graph.node_lookup().find_node(from_grid_coordinate.x() - from_grid_width_ofs, + RRNodeId opin_node_id = rr_graph.node_lookup().find_node(layer, + from_grid_coordinate.x() - from_grid_width_ofs, from_grid_coordinate.y() - from_grid_height_ofs, OPIN, opin, opin_grid_side[0]); - RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(to_grid_coordinate.x() - to_grid_width_ofs, + RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(layer, + to_grid_coordinate.x() - to_grid_width_ofs, to_grid_coordinate.y() - to_grid_height_ofs, IPIN, ipin, ipin_grid_side[0]); /* add edges to the opin_node */ VTR_ASSERT(opin_node_id && ipin_node_id); - rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch); + rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch, false); } } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 9e1d63963ed..7a04a2a35ce 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -69,6 +69,7 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& from_grid_coordinate, const RRSwitchId& delayless_switch, const std::vector& directs, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 902c4db258d..7424cc611f4 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -25,26 +25,28 @@ * Find the number output pins by considering all the grid ***********************************************************************/ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, + const size_t& layer, const t_rr_type& node_type) { size_t num_grid_rr_nodes = 0; for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); /* Skip EMPTY tiles */ - if (true == is_empty_type(grids.get_physical_type(ix, iy))) { + if (true == is_empty_type(grids.get_physical_type(tile_loc))) { continue; } /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(ix, iy)) - || (0 < grids.get_height_offset(ix, iy))) { + if ((0 < grids.get_width_offset(tile_loc)) + || (0 < grids.get_height_offset(tile_loc))) { continue; } enum e_side io_side = NUM_SIDES; /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids.get_physical_type(ix, iy))) { + if (true == is_io_type(grids.get_physical_type(tile_loc))) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); vtr::Point grid_coordinate(ix, iy); io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); @@ -53,19 +55,19 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, switch (node_type) { case OPIN: /* get the number of OPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids, ix, iy, DRIVER, io_side); + num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, DRIVER, io_side); break; case IPIN: /* get the number of IPINs */ - num_grid_rr_nodes += get_grid_num_pins(grids, ix, iy, RECEIVER, io_side); + num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, RECEIVER, io_side); break; case SOURCE: /* SOURCE: number of classes whose type is DRIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids, ix, iy, DRIVER); + num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, DRIVER); break; case SINK: /* SINK: number of classes whose type is RECEIVER */ - num_grid_rr_nodes += get_grid_num_classes(grids, ix, iy, RECEIVER); + num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, RECEIVER); break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -172,6 +174,7 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, * ***********************************************************************/ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, + const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, const bool& through_channel) { @@ -183,7 +186,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, /* Bypass if the routing channel does not exist when through channels are not allowed */ if ((false == through_channel) - && (false == is_chanx_exist(grids, chanx_coord))) { + && (false == is_chanx_exist(grids, layer, chanx_coord))) { continue; } @@ -194,7 +197,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_start = true; } @@ -202,7 +205,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_end = true; } @@ -224,6 +227,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, * Refer to the detailed explanation there ***********************************************************************/ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, + const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, const bool& through_channel) { @@ -235,7 +239,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, /* Bypass if the routing channel does not exist when through channel are not allowed */ if ((false == through_channel) - && (false == is_chany_exist(grids, chany_coord))) { + && (false == is_chany_exist(grids, layer, chany_coord))) { continue; } @@ -246,7 +250,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_start = true; } @@ -254,7 +258,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_end = true; } @@ -273,6 +277,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, const bool& through_channel) { @@ -282,10 +287,10 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, /** * 1 Find number of rr nodes related to grids */ - num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN); - num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN); - num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE); - num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK); + num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, OPIN); + num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN); + num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE); + num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK); /** * 2. Assign the segments for each routing channel, @@ -302,11 +307,11 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, * in X-direction and Y-direction channels!!! * So we will load segment details for different channels */ - num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, + num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, layer, chan_width.x(), segment_infs, through_channel); - num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, + num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, layer, chan_width.y(), segment_infs, through_channel); @@ -324,12 +329,14 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, const bool& through_channel) { VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + layer, chan_width, segment_infs, through_channel); @@ -355,6 +362,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, + const size_t& layer, const vtr::Point& grid_coordinate, const DeviceGrid& grids, const e_side& io_side, @@ -364,7 +372,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder /* Walk through the width height of each grid, * get pins and configure the rr_nodes */ - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); for (int width = 0; width < phy_tile_type->width; ++width) { for (int height = 0; height < phy_tile_type->height; ++height) { /* Walk through sides */ @@ -377,11 +385,11 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder } /* Find OPINs */ /* Configure pins by pins */ - std::vector opin_list = get_grid_side_pins(grids, grid_coordinate.x(), grid_coordinate.y(), DRIVER, side_manager.get_side(), + std::vector opin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), DRIVER, side_manager.get_side(), width, height); for (const int& pin_num : opin_list) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x() + width, grid_coordinate.y() + height, OPIN, pin_num, side); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, OPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -392,6 +400,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_pin_num(node, pin_num); rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_layer(node, layer); /* cost index is a FIXED value for OPIN */ rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); @@ -418,6 +427,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, + const size_t& layer, const vtr::Point& grid_coordinate, const DeviceGrid& grids, const e_side& io_side, @@ -427,7 +437,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder /* Walk through the width and height of each grid, * get pins and configure the rr_nodes */ - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); for (int width = 0; width < phy_tile_type->width; ++width) { for (int height = 0; height < phy_tile_type->height; ++height) { /* Walk through sides */ @@ -441,10 +451,10 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder /* Find IPINs */ /* Configure pins by pins */ - std::vector ipin_list = get_grid_side_pins(grids, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height); + std::vector ipin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height); for (const int& pin_num : ipin_list) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x() + width, grid_coordinate.y() + height, IPIN, pin_num, side); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, IPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -455,6 +465,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_pin_num(node, pin_num); rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_layer(node, layer); /* cost index is a FIXED value for OPIN */ rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); @@ -481,6 +492,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, + const size_t& layer, const vtr::Point& grid_coordinate, const DeviceGrid& grids, const e_side& io_side, @@ -488,7 +500,8 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build SideManager io_side_manager(io_side); /* Set a SOURCE rr_node for each DRIVER class */ - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + t_physical_tile_loc tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { /* Set a SINK rr_node for the OPIN */ if (DRIVER != phy_tile_type->class_inf[iclass].type) { @@ -496,7 +509,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build } /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -504,6 +517,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build grid_coordinate.x() + phy_tile_type->width - 1, grid_coordinate.y() + phy_tile_type->height - 1); rr_graph_builder.set_node_class_num(node, iclass); + rr_graph_builder.set_node_layer(node, (int)layer); /* The capacity should be the number of pins in this class*/ rr_graph_builder.set_node_capacity(node, phy_tile_type->class_inf[iclass].num_pins); @@ -530,6 +544,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, + const size_t& layer, const vtr::Point& grid_coordinate, const DeviceGrid& grids, const e_side& io_side, @@ -537,7 +552,8 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder SideManager io_side_manager(io_side); /* Set a SINK rr_node for each RECEIVER class */ - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); + t_physical_tile_loc tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { /* Set a SINK rr_node for the OPIN */ if (RECEIVER != phy_tile_type->class_inf[iclass].type) { @@ -545,7 +561,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder } /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -553,6 +569,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder grid_coordinate.x() + phy_tile_type->width - 1, grid_coordinate.y() + phy_tile_type->height - 1); rr_graph_builder.set_node_class_num(node, iclass); + rr_graph_builder.set_node_layer(node, layer); rr_graph_builder.set_node_capacity(node, 1); @@ -578,18 +595,20 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, const DeviceGrid& grids, + const size_t& layer, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch) { for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { + t_physical_tile_loc tile_loc(ix, iy, layer); /* Skip EMPTY tiles */ - if (true == is_empty_type(grids.get_physical_type(ix, iy))) { + if (true == is_empty_type(grids.get_physical_type(tile_loc))) { continue; } /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ - if ((0 < grids.get_width_offset(ix, iy)) - || (0 < grids.get_height_offset(ix, iy))) { + if ((0 < grids.get_width_offset(tile_loc)) + || (0 < grids.get_height_offset(tile_loc))) { continue; } @@ -599,7 +618,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, std::vector wanted_sides{TOP, RIGHT, BOTTOM, LEFT}; /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids.get_physical_type(ix, iy))) { + if (true == is_io_type(grids.get_physical_type(tile_loc))) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); wanted_sides.clear(); @@ -607,12 +626,12 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, } for (e_side side : wanted_sides) { - for (int width_offset = 0; width_offset < grids.get_physical_type(ix, iy)->width; ++width_offset) { + for (int width_offset = 0; width_offset < grids.get_physical_type(tile_loc)->width; ++width_offset) { int x_tile = ix + width_offset; - for (int height_offset = 0; height_offset < grids.get_physical_type(ix, iy)->height; ++height_offset) { + for (int height_offset = 0; height_offset < grids.get_physical_type(tile_loc)->height; ++height_offset) { int y_tile = iy + height_offset; - rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, OPIN, grids.get_physical_type(ix, iy)->num_pins, side); - rr_graph_builder.node_lookup().reserve_nodes(x_tile, y_tile, IPIN, grids.get_physical_type(ix, iy)->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, OPIN, grids.get_physical_type(tile_loc)->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, IPIN, grids.get_physical_type(tile_loc)->num_pins, side); } } } @@ -621,7 +640,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, load_one_grid_source_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, rr_rc_data, - grid_coordinate, + layer, grid_coordinate, grids, io_side, delayless_switch); @@ -630,7 +649,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, load_one_grid_sink_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, rr_rc_data, - grid_coordinate, + layer, grid_coordinate, grids, io_side, delayless_switch); @@ -639,7 +658,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, load_one_grid_opin_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, rr_rc_data, - grid_coordinate, + layer, grid_coordinate, grids, io_side, delayless_switch); @@ -648,7 +667,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, load_one_grid_ipin_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, rr_rc_data, - grid_coordinate, + layer, grid_coordinate, grids, io_side, wire_to_ipin_switch); @@ -658,17 +677,20 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, // This ensures that look-ups on non-root locations will still find the correct SOURCE/SINK for (size_t x = 0; x < grids.width(); x++) { for (size_t y = 0; y < grids.height(); y++) { - int width_offset = grids.get_width_offset(x, y); - int height_offset = grids.get_height_offset(x, y); + t_physical_tile_loc tile_loc(x, y, 0); + int width_offset = grids.get_width_offset(tile_loc); + int height_offset = grids.get_height_offset(tile_loc); if (width_offset != 0 || height_offset != 0) { int root_x = x - width_offset; int root_y = y - height_offset; - rr_graph_builder.node_lookup().mirror_nodes(vtr::Point(root_x, root_y), + rr_graph_builder.node_lookup().mirror_nodes(0, + vtr::Point(root_x, root_y), vtr::Point(x, y), SOURCE, SIDES[0]); - rr_graph_builder.node_lookup().mirror_nodes(vtr::Point(root_x, root_y), + rr_graph_builder.node_lookup().mirror_nodes(0, + vtr::Point(root_x, root_y), vtr::Point(x, y), SINK, SIDES[0]); @@ -686,6 +708,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, + const size_t& layer, const vtr::Point& chan_coordinate, const t_rr_type& chan_type, ChanNodeDetails& chan_details, @@ -704,13 +727,14 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, || ((true == chan_details.is_track_end(itrack)) && (Direction::DEC == chan_details.get_track_direction(itrack)))) { /* Create a new chan rr_node */ - RRNodeId node = rr_graph_builder.create_node(chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); + RRNodeId node = rr_graph_builder.create_node(layer, chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); rr_graph_builder.add_node_track_num(node, chan_coordinate, itrack); rr_node_track_ids[node].push_back(itrack); rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_layer(node, layer); /* assign switch id */ size_t seg_id = chan_details.get_track_segment_id(itrack); @@ -797,7 +821,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, + const DeviceGrid& grids, const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, const bool& through_channel) { @@ -811,7 +835,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, /* Bypass if the routing channel does not exist when through channels are not allowed */ if ((false == through_channel) - && (false == is_chanx_exist(grids, chanx_coord))) { + && (false == is_chanx_exist(grids, layer, chanx_coord))) { continue; } @@ -822,7 +846,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) { + if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_start = true; } @@ -830,7 +854,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) { + if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_end = true; } @@ -858,7 +882,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, * track0 ----->+-----------------------------+----> track0 * | | */ - if (true == is_chanx_exist(grids, chanx_coord, through_channel)) { + if (true == is_chanx_exist(grids, layer, chanx_coord, through_channel)) { /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D @@ -885,7 +909,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, - chanx_coord, CHANX, + layer, chanx_coord, CHANX, chanx_details, segment_infs, CHANX_COST_INDEX_START); @@ -904,7 +928,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, + const DeviceGrid& grids, const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, const bool& through_channel) { @@ -918,7 +942,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, /* Bypass if the routing channel does not exist when through channel are not allowed */ if ((false == through_channel) - && (false == is_chany_exist(grids, chany_coord))) { + && (false == is_chany_exist(grids, layer, chany_coord))) { continue; } @@ -929,7 +953,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) { + if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_start = true; } @@ -937,7 +961,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) { + if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_end = true; } @@ -969,7 +993,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, * | | * we should rotate only once at the bottom side of a grid */ - if (true == is_chany_exist(grids, chany_coord, through_channel)) { + if (true == is_chany_exist(grids, layer, chany_coord, through_channel)) { /* Rotate the chany_details by an offset of 1*/ /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D @@ -995,7 +1019,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, - chany_coord, CHANY, + layer, chany_coord, CHANY, chany_details, segment_infs, CHANX_COST_INDEX_START + segment_infs.size()); @@ -1037,7 +1061,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, std::vector& rr_rc_data, - const DeviceGrid& grids, + const DeviceGrid& grids, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, @@ -1052,16 +1076,16 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, * When comment the following block out, you will see errors */ for (t_rr_type rr_type : RR_TYPES) { if (rr_type == CHANX) { - rr_graph_builder.node_lookup().resize_nodes(grids.height(), grids.width(), rr_type, NUM_SIDES); + rr_graph_builder.node_lookup().resize_nodes(layer, grids.height(), grids.width(), rr_type, NUM_SIDES); } else { - rr_graph_builder.node_lookup().resize_nodes(grids.width(), grids.height(), rr_type, NUM_SIDES); + rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_SIDES); } } load_grid_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, rr_rc_data, - grids, + grids, layer, wire_to_ipin_switch, delayless_switch); @@ -1069,7 +1093,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, - grids, + grids, layer, chan_width.x(), segment_infs, through_channel); @@ -1078,7 +1102,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, - grids, + grids, layer, chan_width.y(), segment_infs, through_channel); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 1372513200a..0934162337e 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -23,6 +23,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& driver_switches, const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, const bool& through_channel); @@ -32,7 +33,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, std::vector& rr_rc_data, - const DeviceGrid& grids, + const DeviceGrid& grids, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, From e1fd296abf43eb94b6e47e12d179f13c1d411693 Mon Sep 17 00:00:00 2001 From: Nadeem Yaseen <86344264+nadeemyaseen-rs@users.noreply.github.com> Date: Tue, 8 Aug 2023 11:15:13 +0500 Subject: [PATCH 161/453] Update hostsetup.sh to install dev package of openssl --- .github/scripts/hostsetup.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/scripts/hostsetup.sh b/.github/scripts/hostsetup.sh index 1a69181dc4a..2dfd0c141c5 100755 --- a/.github/scripts/hostsetup.sh +++ b/.github/scripts/hostsetup.sh @@ -70,7 +70,8 @@ apt install -y \ g++-9 \ gcc-9 \ wget \ - openssl + openssl \ + libssl-dev # installing the latest version of cmake apt install -y apt-transport-https ca-certificates gnupg From c7ffb751effc51ce39548321ffa9da1cdd2e10e6 Mon Sep 17 00:00:00 2001 From: umariqbal-rs Date: Tue, 8 Aug 2023 11:40:01 +0500 Subject: [PATCH 162/453] resolving conflicts --- .../rr_graph_builder_utils.cpp | 51 ++++++++++--------- .../rr_graph_builder_utils.h | 21 ++++---- 2 files changed, 38 insertions(+), 34 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 6388b07e5a7..3aa3289bf9a 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -31,11 +31,11 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width) { * Get the class index of a grid pin ***********************************************************************/ int get_grid_pin_class_index(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const int pin_index) { /* check */ - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + t_physical_tile_loc tile_loc(x, y, layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); VTR_ASSERT(pin_index < phy_tile_type->num_pins); return phy_tile_type->pin_class[pin_index]; } @@ -65,14 +65,14 @@ e_side determine_io_grid_pin_side(const vtr::Point& device_size, /* Deteremine the side of a pin of a grid */ std::vector find_grid_pin_sides(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const size_t& pin_id) { std::vector pin_sides; - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); - int width_offset = grids.get_width_offset(x, y); - int height_offset = grids.get_height_offset(x, y); + t_physical_tile_loc tile_loc(x, y, layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); + int width_offset = grids.get_width_offset(tile_loc); + int height_offset = grids.get_height_offset(tile_loc); for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { if (true == phy_tile_type->pinloc[width_offset][height_offset][size_t(side)][pin_id]) { pin_sides.push_back(side); @@ -88,8 +88,7 @@ std::vector find_grid_pin_sides(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ std::vector get_grid_side_pins(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, @@ -98,7 +97,7 @@ std::vector get_grid_side_pins(const DeviceGrid& grids, /* Make sure a clear start */ pin_list.clear(); - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); for (int ipin = 0; ipin < phy_tile_type->num_pins; ++ipin) { int class_id = phy_tile_type->pin_class[ipin]; if ((1 == phy_tile_type->pinloc[pin_width][pin_height][pin_side][ipin]) @@ -115,14 +114,13 @@ std::vector get_grid_side_pins(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ size_t get_grid_num_pins(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& io_side) { size_t num_pins = 0; /* For IO_TYPE sides */ - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { /* skip unwanted sides */ if ((true == is_io_type(phy_tile_type)) @@ -132,7 +130,7 @@ size_t get_grid_num_pins(const DeviceGrid& grids, /* Get pin list */ for (int width = 0; width < phy_tile_type->width; ++width) { for (int height = 0; height < phy_tile_type->height; ++height) { - std::vector pin_list = get_grid_side_pins(grids, x, y, pin_type, side, width, height); + std::vector pin_list = get_grid_side_pins(grids, layer, x, y, pin_type, side, width, height); num_pins += pin_list.size(); } } @@ -147,12 +145,11 @@ size_t get_grid_num_pins(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ size_t get_grid_num_classes(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type) { size_t num_classes = 0; - t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(x, y); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { /* Bypass unmatched pin_type */ if (pin_type != phy_tile_type->class_inf[iclass].type) { @@ -190,6 +187,7 @@ size_t get_grid_num_classes(const DeviceGrid& grids, * When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block ***********************************************************************/ bool is_chanx_exist(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel) { if ((1 > chanx_coord.x()) || (chanx_coord.x() > grids.width() - 2)) { @@ -204,7 +202,7 @@ bool is_chanx_exist(const DeviceGrid& grids, return true; } - return (grids.get_height_offset(chanx_coord.x(), chanx_coord.y()) == grids.get_physical_type(chanx_coord.x(), chanx_coord.y())->height - 1); + return (grids.get_height_offset(t_physical_tile_loc(chanx_coord.x(), chanx_coord.y(), layer)) == grids.get_physical_type(t_physical_tile_loc(chanx_coord.x(), chanx_coord.y(), layer))->height - 1); } /************************************************************************ @@ -228,6 +226,7 @@ bool is_chanx_exist(const DeviceGrid& grids, * unless it falls out of the grid array ***********************************************************************/ bool is_chany_exist(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel) { if (chany_coord.x() > grids.width() - 2) { @@ -242,7 +241,7 @@ bool is_chany_exist(const DeviceGrid& grids, return true; } - return (grids.get_width_offset(chany_coord.x(), chany_coord.y()) == grids.get_physical_type(chany_coord.x(), chany_coord.y())->width - 1); + return (grids.get_width_offset(t_physical_tile_loc(chany_coord.x(), chany_coord.y(), layer)) == grids.get_physical_type(t_physical_tile_loc(chany_coord.x(), chany_coord.y(), layer))->width - 1); } /************************************************************************ @@ -259,6 +258,7 @@ bool is_chany_exist(const DeviceGrid& grids, * +-----------------+ ***********************************************************************/ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel) { VTR_ASSERT(0 < chanx_coord.x()); @@ -272,7 +272,7 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ vtr::Point left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y()); - if (false == is_chanx_exist(grids, left_chanx_coord)) { + if (false == is_chanx_exist(grids, layer, left_chanx_coord)) { return true; } } @@ -294,6 +294,7 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, * +-----------------+ ***********************************************************************/ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel) { VTR_ASSERT(chanx_coord.x() < grids.width() - 1); @@ -307,7 +308,7 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ vtr::Point right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y()); - if (false == is_chanx_exist(grids, right_chanx_coord)) { + if (false == is_chanx_exist(grids, layer, right_chanx_coord)) { return true; } } @@ -334,6 +335,7 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, * +-----------------+ ***********************************************************************/ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel) { VTR_ASSERT(0 < chany_coord.y()); @@ -347,7 +349,7 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the bottom neighbor of chany, if it does not exist, the chany is top to a multi-height grid */ vtr::Point bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1); - if (false == is_chany_exist(grids, bottom_chany_coord)) { + if (false == is_chany_exist(grids, layer, bottom_chany_coord)) { return true; } } @@ -374,6 +376,7 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, * ***********************************************************************/ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel) { VTR_ASSERT(chany_coord.y() < grids.height() - 1); @@ -387,7 +390,7 @@ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */ vtr::Point top_chany_coord(chany_coord.x(), chany_coord.y() + 1); - if (false == is_chany_exist(grids, top_chany_coord)) { + if (false == is_chany_exist(grids, layer, top_chany_coord)) { return true; } } diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index acdd16841ad..c21f3419cc2 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -15,58 +15,59 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width); int get_grid_pin_class_index(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const int pin_index); std::vector find_grid_pin_sides(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const size_t& pin_id); e_side determine_io_grid_pin_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate); std::vector get_grid_side_pins(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, const int& pin_height); size_t get_grid_num_pins(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type, const e_side& io_side); size_t get_grid_num_classes(const DeviceGrid& grids, - const size_t& x, - const size_t& y, + const size_t& layer, const size_t& x, const size_t& y, const e_pin_type& pin_type); bool is_chanx_exist(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel = false); bool is_chany_exist(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel = false); bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel); bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chanx_coord, const bool& through_channel); bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel); bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chany_coord, const bool& through_channel); From 5bea5da827600c06990be740b580213eebae6263 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Aug 2023 10:05:35 -0700 Subject: [PATCH 163/453] [core] fixed broken API call due to layer upgrades --- .../rr_graph_builder_utils.cpp | 20 +++++++++--- .../rr_graph_builder_utils.h | 20 +++++++++--- .../tileable_rr_graph/rr_graph_view_util.cpp | 8 +++-- .../tileable_rr_graph/rr_graph_view_util.h | 2 ++ .../tileable_rr_graph_edge_builder.cpp | 2 +- .../tileable_rr_graph_gsb.cpp | 32 ++++++++++--------- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 1 + .../tileable_rr_graph_node_builder.cpp | 9 ++++-- .../tileable_rr_graph_node_builder.h | 3 +- 9 files changed, 64 insertions(+), 33 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 3aa3289bf9a..9fb6981bf85 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -31,7 +31,9 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width) { * Get the class index of a grid pin ***********************************************************************/ int get_grid_pin_class_index(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const int pin_index) { /* check */ t_physical_tile_loc tile_loc(x, y, layer); @@ -65,7 +67,9 @@ e_side determine_io_grid_pin_side(const vtr::Point& device_size, /* Deteremine the side of a pin of a grid */ std::vector find_grid_pin_sides(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const size_t& pin_id) { std::vector pin_sides; @@ -88,7 +92,9 @@ std::vector find_grid_pin_sides(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ std::vector get_grid_side_pins(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, @@ -114,7 +120,9 @@ std::vector get_grid_side_pins(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ size_t get_grid_num_pins(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const e_pin_type& pin_type, const e_side& io_side) { size_t num_pins = 0; @@ -145,7 +153,9 @@ size_t get_grid_num_pins(const DeviceGrid& grids, * For others, we consider all the sides ***********************************************************************/ size_t get_grid_num_classes(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const e_pin_type& pin_type) { size_t num_classes = 0; diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index c21f3419cc2..a6ff1b38de0 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -15,30 +15,40 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width); int get_grid_pin_class_index(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const int pin_index); std::vector find_grid_pin_sides(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const size_t& pin_id); e_side determine_io_grid_pin_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate); std::vector get_grid_side_pins(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const e_pin_type& pin_type, const e_side& pin_side, const int& pin_width, const int& pin_height); size_t get_grid_num_pins(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const e_pin_type& pin_type, const e_side& io_side); size_t get_grid_num_classes(const DeviceGrid& grids, - const size_t& layer, const size_t& x, const size_t& y, + const size_t& layer, + const size_t& x, + const size_t& y, const e_pin_type& pin_type); bool is_chanx_exist(const DeviceGrid& grids, diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 025fb75992f..eee1d94b740 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -35,6 +35,7 @@ std::vector find_rr_graph_switches(const RRGraphView& rr_graph, * of a specific IPIN/OPIN at a specific grid tile (x,y) location. **********************************************************************/ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, + const size_t& layer, const int& x, const int& y, const t_rr_type& rr_type, @@ -45,7 +46,7 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, //For pins we need to look at all the sides of the current grid tile for (e_side side : SIDES) { - RRNodeId rr_node_index = rr_graph.node_lookup().find_node(x, y, rr_type, ptc, side); + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(layer, x, y, rr_type, ptc, side); if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); @@ -53,7 +54,7 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, } } else { //Sides do not effect non-pins so there should only be one per ptc - RRNodeId rr_node_index = rr_graph.node_lookup().find_node(x, y, rr_type, ptc); + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(layer, x, y, rr_type, ptc); if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); @@ -67,6 +68,7 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, * Find a list of rr nodes in a routing channel at (x,y) **********************************************************************/ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, + const size_t& layer, const int& x, const int& y, const t_rr_type& rr_type) { @@ -74,7 +76,7 @@ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); - for (const RRNodeId& rr_node_index : rr_graph.node_lookup().find_channel_nodes(x, y, rr_type)) { + for (const RRNodeId& rr_node_index : rr_graph.node_lookup().find_channel_nodes(layer, x, y, rr_type)) { if (rr_node_index != RRNodeId::INVALID()) { indices.push_back(rr_node_index); } diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.h b/vpr/src/tileable_rr_graph/rr_graph_view_util.h index 1e194816eaf..4ccb1c614e1 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.h +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.h @@ -14,12 +14,14 @@ std::vector find_rr_graph_switches(const RRGraphView& rr_graph, const RRNodeId& to_node); std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, + const size_t& layer, const int& x, const int& y, const t_rr_type& rr_type, const int& ptc); std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, + const size_t& layer, const int& x, const int& y, const t_rr_type& rr_type); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index b9ee74830c1..0abc22034ea 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -131,7 +131,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* Create a GSB object */ const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, device_chan_width, segment_inf, - gsb_coord); + layer, gsb_coord); /* adapt the track_to_ipin_lookup for the GSB nodes */ t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index eedbc972678..8d5f5686fa3 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -534,7 +534,8 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, } /* Build a RRChan Object with the given channel type and coorindators */ -static RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordinate, +static RRChan build_one_tileable_rr_chan(const size_t& layer, + const vtr::Point& chan_coordinate, const t_rr_type& chan_type, const RRGraphView& rr_graph, const ChanNodeDetails& chan_details) { @@ -548,7 +549,7 @@ static RRChan build_one_tileable_rr_chan(const vtr::Point& chan_coordina /* Collect rr_nodes for this channel */ chan_rr_nodes = find_rr_graph_chan_nodes(rr_graph, - chan_coordinate.x(), chan_coordinate.y(), + layer, chan_coordinate.x(), chan_coordinate.y(), chan_type); /* Reserve */ @@ -619,6 +620,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const RRGraphView& rr_graph, const vtr::Point& device_chan_width, const std::vector& segment_inf, + const size_t& layer, const vtr::Point& gsb_coordinate) { /* Create an object to return */ RRGSB rr_gsb; @@ -662,7 +664,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Routing channels*/ /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANY, rr_graph, chany_details); chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ @@ -675,11 +677,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Build the Switch block: opin and opin_grid_side */ /* Include Grid[x][y+1] RIGHT side outputs pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x(), gsb_coordinate.y() + 1, + layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, OPIN, opin_grid_side[0]); /* Include Grid[x+1][y+1] Left side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, + layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, OPIN, opin_grid_side[1]); break; @@ -693,7 +695,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANX, rr_graph, chanx_details); chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ @@ -706,11 +708,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Build the Switch block: opin and opin_grid_side */ /* include Grid[x+1][y+1] Bottom side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, + layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, OPIN, opin_grid_side[0]); /* include Grid[x+1][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x() + 1, gsb_coordinate.y(), + layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ @@ -723,7 +725,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANY, rr_graph, chany_details); chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ @@ -736,11 +738,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Build the Switch block: opin and opin_grid_side */ /* include Grid[x+1][y] Left side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x() + 1, gsb_coordinate.y(), + layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), OPIN, opin_grid_side[0]); /* include Grid[x][y] Right side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x(), gsb_coordinate.y(), + layer, gsb_coordinate.x(), gsb_coordinate.y(), OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ @@ -753,7 +755,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for left: chanx[x][y] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANX, rr_graph, chanx_details); chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ @@ -765,11 +767,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Build the Switch block: opin and opin_grid_side */ /* include Grid[x][y+1] Bottom side outputs pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x(), gsb_coordinate.y() + 1, + layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, OPIN, opin_grid_side[0]); /* include Grid[x][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, - gsb_coordinate.x(), gsb_coordinate.y(), + layer, gsb_coordinate.x(), gsb_coordinate.y(), OPIN, opin_grid_side[1]); break; @@ -899,7 +901,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, } /* Collect IPIN rr_nodes*/ temp_ipin_rr_nodes = find_rr_graph_grid_nodes(rr_graph, grids, - ix, iy, IPIN, ipin_rr_node_grid_side); + layer, ix, iy, IPIN, ipin_rr_node_grid_side); /* Fill the ipin nodes of RRGSB */ for (const RRNodeId& inode : temp_ipin_rr_nodes) { rr_gsb.add_ipin_node(inode, side_manager.get_side()); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 7a04a2a35ce..579309358a2 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -44,6 +44,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const RRGraphView& rr_graph, const vtr::Point& device_chan_width, const std::vector& segment_inf, + const size_t& layer, const vtr::Point& gsb_coordinate); void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 7424cc611f4..0d93e4b5735 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -821,7 +821,8 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, const size_t& layer, + const DeviceGrid& grids, + const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, const bool& through_channel) { @@ -928,7 +929,8 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, - const DeviceGrid& grids, const size_t& layer, + const DeviceGrid& grids, + const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, const bool& through_channel) { @@ -1061,7 +1063,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, std::vector& rr_rc_data, - const DeviceGrid& grids, const size_t& layer, + const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 0934162337e..85cd0e69e79 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -33,7 +33,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, std::vector& rr_rc_data, - const DeviceGrid& grids, const size_t& layer, + const DeviceGrid& grids, + const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, From 62e9990b882fd09b3a1e3f74113a5270571190fc Mon Sep 17 00:00:00 2001 From: Nadeem Yaseen <86344264+nadeemyaseen-rs@users.noreply.github.com> Date: Thu, 10 Aug 2023 12:14:35 +0500 Subject: [PATCH 164/453] Update install_apt_packages.sh to install openssl package --- install_apt_packages.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/install_apt_packages.sh b/install_apt_packages.sh index 533fdf608d5..17d9aa49425 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -9,7 +9,9 @@ sudo apt-get install -y \ bison \ flex \ python3-dev \ - python3-venv + python3-venv \ + openssl \ + libssl-dev # Required for graphics sudo apt-get install -y \ From 25b9537da131dfc47354d763855e9960157ac5c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Aug 2023 16:19:12 -0700 Subject: [PATCH 165/453] [core] add support on shrink boundary on device grid when building tileable routing resource graph --- libs/libarchfpga/src/read_xml_arch_file.cpp | 1 + libs/libvtrutil/src/vtr_geometry.h | 12 +- libs/libvtrutil/src/vtr_strong_id.h | 4 +- vpr/src/base/SetupVPR.cpp | 1 + vpr/src/route/rr_graph.cpp | 1 + .../device_grid_annotation.cpp | 113 ++++++++++++++++++ .../device_grid_annotation.h | 51 ++++++++ .../tileable_rr_graph_builder.cpp | 9 ++ .../tileable_rr_graph_builder.h | 1 + .../tileable_rr_graph_node_builder.cpp | 63 ++++++++++ .../tileable_rr_graph_node_builder.h | 5 + 11 files changed, 253 insertions(+), 8 deletions(-) create mode 100644 vpr/src/tileable_rr_graph/device_grid_annotation.cpp create mode 100644 vpr/src/tileable_rr_graph/device_grid_annotation.h diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 2e4d7afe8e8..4842d67a657 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2523,6 +2523,7 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti //expect_only_attributes(layout_tag, {}, loc_data); arch->tileable = get_attribute(layout_tag, "tileable", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->shrink_boundary = get_attribute(layout_tag, "shrink_boundary", loc_data, ReqOpt::OPTIONAL).as_bool(false); arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false); //Count the number of or tags diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 1e11f87e1d7..f5bdb24bfff 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -74,10 +74,10 @@ class Point { T y() const; ///@brief == operator - friend bool operator== <>(Point lhs, Point rhs); + friend bool operator==<>(Point lhs, Point rhs); ///@brief != operator - friend bool operator!= <>(Point lhs, Point rhs); + friend bool operator!=<>(Point lhs, Point rhs); ///@brief < operator friend bool operator< <>(Point lhs, Point rhs); @@ -175,10 +175,10 @@ class Rect { bool empty() const; ///@brief == operator - friend bool operator== <>(const Rect& lhs, const Rect& rhs); + friend bool operator==<>(const Rect& lhs, const Rect& rhs); ///@brief != operator - friend bool operator!= <>(const Rect& lhs, const Rect& rhs); + friend bool operator!=<>(const Rect& lhs, const Rect& rhs); public: //Mutators ///@brief set xmin to a point @@ -299,10 +299,10 @@ class RectUnion { * * Note: does not check whether the representations they are equivalent */ - friend bool operator== <>(const RectUnion& lhs, const RectUnion& rhs); + friend bool operator==<>(const RectUnion& lhs, const RectUnion& rhs); ///@brief != operator - friend bool operator!= <>(const RectUnion& lhs, const RectUnion& rhs); + friend bool operator!=<>(const RectUnion& lhs, const RectUnion& rhs); private: // Note that a union of rectanges may have holes and may not be contiguous diff --git a/libs/libvtrutil/src/vtr_strong_id.h b/libs/libvtrutil/src/vtr_strong_id.h index 4f3849df094..14ac6c31cb0 100644 --- a/libs/libvtrutil/src/vtr_strong_id.h +++ b/libs/libvtrutil/src/vtr_strong_id.h @@ -209,9 +209,9 @@ class StrongId { * Note that since these are templated functions we provide an empty set of template parameters * after the function name (i.e. <>) */ - friend constexpr bool operator== <>(const StrongId& lhs, const StrongId& rhs); + friend constexpr bool operator==<>(const StrongId& lhs, const StrongId& rhs); ///@brief != operator - friend constexpr bool operator!= <>(const StrongId& lhs, const StrongId& rhs); + friend constexpr bool operator!=<>(const StrongId& lhs, const StrongId& rhs); ///@brief < operator friend constexpr bool operator< <>(const StrongId& lhs, const StrongId& rhs); diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 73e73a2c2e2..efef48ed4c1 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -410,6 +410,7 @@ static void SetupRoutingArch(const t_arch& Arch, /* Copy the tileable routing setting */ RoutingArch->tileable = Arch.tileable; + RoutingArch->shrink_boundary = Arch.shrink_boundary; RoutingArch->through_channel = Arch.through_channel; } diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 7ac5c5b03c2..c19a84b6c6d 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -720,6 +720,7 @@ void create_rr_graph(const t_graph_type graph_type, router_opts.base_cost_type, directs, num_directs, &det_routing_arch->wire_to_rr_ipin_switch, + det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ false, /* Do not allow passing tracks to be wired to the same routing channels */ Warnings); diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp new file mode 100644 index 00000000000..e0f28fb6f00 --- /dev/null +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -0,0 +1,113 @@ +#include "device_grid_annotation.h" + +/* Begin namespace openfpga */ +namespace openfpga { + +DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid, const bool& shrink) { + alloc(grid); + init(grid, shrink); +} + +void DeviceGridAnnotation::alloc(const DeviceGrid& grid) { + /* Allocate */ + borderline_types_.resize({grid.width(), grid.height()}); +} + +void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& shrink) { + /* If shrink is not considered, perimeters are the borderlines */ + for (size_t ix = 0; ix < grid.width(); ++ix) { + for (size_t iy = 0; iy < grid.height(); ++iy) { + for (e_side side : SIDES) { + borderline_types_[ix][iy][side] = is_empty_zone(grid, vtr::Point(ix, iy), side, shrink); + } + } + } +} + +bool DeviceGridAnnotation::is_empty_zone(const DeviceGrid& grid, const vtr::Point& coord, const e_side& side, const bool& shrink) const { + bool empty_zone = true; + /* With the given side, expand on the direction */ + if (side == TOP) { + if (iy == grid.height() - 1) { + return empty_zone; + } + if (shrink) { + for (iy = coord.y() + 1; iy < grid.height(); ++iy) { + if (!is_empty_type(grid.get_physical_type({coord.x(), iy, 0}))) { + empty_zone = false; + break; + } + } + } + } else if (side == RIGHT) { + if (ix == grid.width() - 1) { + return empty_zone; + } + if (shrink) { + for (ix = coord.x() + 1; ix < grid.height(); ++ix) { + if (!is_empty_type(grid.get_physical_type({ix, coord.y(), 0}))) { + empty_zone = false; + break; + } + } + } + } else if (side == BOTTOM) { + if (iy == 0) { + return empty_zone; + } + if (shrink) { + for (iy = coord.y() - 1; iy >= 0; --iy) { + if (!is_empty_type(grid.get_physical_type({coord.x(), iy, 0}))) { + empty_zone = false; + break; + } + } + } + } else if (side == LEFT) { + if (ix == 0) { + return empty_zone; + } + if (shrink) { + for (ix = coord.x() - 1; ix >= 0; --ix) { + if (!is_empty_type(grid.get_physical_type({ix, coord.y(), 0}))) { + empty_zone = false; + break; + } + } + } + } + + return empty_zone; +} + +bool DeviceGridAnnotation::is_chanx_exist(const vtr::Point& coord) const { + if (coord.y() == borderline_types_.dim_size(2) - 1) { + return false; + } + return !borderline_types[coord.x()][coord.y()][TOP] || !borderline_types[coord.x()][coord.y() + 1][BOTTOM]; +} + +bool DeviceGridAnnotation::is_chany_exist(const vtr::Point& coord) const { + if (coord.x() == borderline_types_.dim_size(1) - 1) { + return false; + } + return !borderline_types[coord.x()][coord.y()][RIGHT] || !borderline_types[coord.x() + 1][coord.y()][LEFT]; +} + +bool DeviceGridAnnotation::borderline(const vtr::Point& coord, const e_side& side) const { + /* Check boundary */ + if (coord.x() >= borderline_types_.dim_size(1) || coord.y() >= borderline_types_.dim_size(2)) { + VTR_LOG_ERROR("Given coordinate (%lu, %lu) is out of device grid size (%lu, %lu)!\n", + coord.x(), coord.y(), borderline_types_.dim_size(1), borderline_types_.dim_size(2)); + exit(1); + } + if (side == NUM_SIDES) { + VTR_LOG_ERROR("Invalid side. Expect [TOP|RIGHT|BOTTOM|LEFT]!\n"); + exit(1); + } + return borderline_types_[coord.x()][coord.y()][side]; +} + +} /* End namespace openfpga*/ + +#endif diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.h b/vpr/src/tileable_rr_graph/device_grid_annotation.h new file mode 100644 index 00000000000..1fd288db8b7 --- /dev/null +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.h @@ -0,0 +1,51 @@ +#ifndef DEVICE_GRID_ANNOTATION_H +#define DEVICE_GRID_ANNOTATION_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +#include +#include "vtr_geometry.h" +#include "vtr_ndmatrix.h" +#include "physical_types.h" +#include "device_grid.h" + +/* Begin namespace openfpga */ +namespace openfpga { + +/** @brief This is the data structure to provide additional data for the device grid: + * - Border of the device grid (check where the empty types cover the perimeters) + */ +class DeviceGridAnnotation { + public: /* Constructor */ + /** @brief Build the annotation. When shrink is enable, a boundary line is drawn when all the empty types are found between the line and the perimeter. For example + * boundry line perimeter + * v v + * clb | empty empty empty | + * Otherwise, the boundary line is just the perimeter. + */ + DeviceGridAnnotation(const DeviceGrid& grid, const bool& shrink); + + private: /* Private mutators */ + void alloc(const DeviceGrid& grid); + void init(const DeviceGrid& grid, const bool& shrink); + + public: /* Public accessors */ + /** @brief Check if a given coordinate is on the borderline w.r.t. a given side of the device grid. For example, border(vtr::Point(5,4), TOP) will check if any empty types are above the y=4. If there are at least 1 non-empty type, this is not a border line. Otherwise, it is. */ + bool borderline(const vtr::Point& coord, const e_side& side) const; + /** @brief Check if at a given coordinate, a X-direction routing channel should exist or not */ + bool is_chanx_exist(const vtr::Point& coord) const; + /** @brief Check if at a given coordinate, a Y-direction routing channel should exist or not */ + bool is_chany_exist(const vtr::Point& coord) const; + + private: /* Private validators */ + /** @brief Check all the adjacent grid until perimeter. To be an empty zone with a given side, there should be all empty types from the given side to the perimeter */ + bool is_empty_zone(const DeviceGrid& grid, const vtr::Point& coord, const bool& shrink) const; + + private: /* Internal data */ + vtr::NdMatrix, 2> borderline_types_; +}; + +} /* End namespace openfpga*/ + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index d200a27f822..58ed206d3b2 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -18,6 +18,7 @@ #include "rr_graph.h" #include "check_rr_graph.h" #include "get_parallel_segs.h" +#include "device_grid_annotation.h" #include "rr_graph_builder_utils.h" #include "tileable_chan_details_builder.h" @@ -83,6 +84,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const t_direct_inf* directs, const int& num_directs, int* wire_to_rr_ipin_switch, + const bool& shrink_boundary, const bool& through_channel, const bool& wire_opposite_side, int* Warnings) { @@ -101,6 +103,9 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* Get a mutable device ctx so that we have a mutable rr_graph */ DeviceContext& device_ctx = g_vpr_ctx.mutable_device(); + /* Annotate the device grid on the boundry */ + DeviceGridAnnotation device_grid_annotation(device_ctx.grid, shrink_boundary); + /* The number of segments are in general small, reserve segments may not bring * significant memory efficiency */ device_ctx.rr_graph_builder.reserve_segments(segment_inf.size()); @@ -151,6 +156,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ grids, 0, device_chan_width, segment_inf, + device_grid_annotation, + shrink_boundary, through_channel); /************************ @@ -166,6 +173,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ segment_inf, wire_to_ipin_rr_switch, delayless_rr_switch, + device_grid_annotation, + shrink_boundary, through_channel); /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h index c5275e1d0a7..089dcb7a7c4 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -29,6 +29,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const t_direct_inf* directs, const int& num_directs, int* wire_to_rr_ipin_switch, + const bool& shrink_boundary, const bool& through_channel, const bool& wire_opposite_side, int* Warnings); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 0d93e4b5735..2b7e6a93a7a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -177,6 +177,8 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel) { size_t num_chanx_rr_nodes = 0; @@ -189,6 +191,10 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, && (false == is_chanx_exist(grids, layer, chanx_coord))) { continue; } + /* Bypass if the routing channel does not exist when a shrink boundary is considered */ + if (shrink_boundary && !device_grid_annotation.is_chanx_exist(chanx_coord)) { + continue; + } bool force_start = false; bool force_end = false; @@ -200,6 +206,9 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_start = true; } + if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, LEFT)) { + force_start = true; + } /* All the tracks have to end when * - the routing channel touch the LEFT side a heterogeneous block @@ -208,6 +217,9 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_end = true; } + if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, RIGHT)) { + force_end = true; + } /* Evaluate if the routing channel locates in the middle of a grid */ ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); @@ -230,6 +242,8 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel) { size_t num_chany_rr_nodes = 0; @@ -243,6 +257,11 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, continue; } + /* Bypass if the routing channel does not exist when a shrink boundary is considered */ + if (shrink_boundary && !device_grid_annotation.is_chany_exist(chany_coord)) { + continue; + } + bool force_start = false; bool force_end = false; @@ -253,6 +272,9 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_start = true; } + if (shrink_boundary && device_grid_annotation.borderline(chany_coord, BOTTOM)) { + force_start = true; + } /* All the tracks have to end when * - the routing channel touch the BOTTOM side a heterogeneous block @@ -261,6 +283,9 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_end = true; } + if (shrink_boundary && device_grid_annotation.borderline(chany_coord, TOP)) { + force_end = true; + } ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ @@ -280,6 +305,8 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel) { /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); @@ -310,10 +337,12 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, layer, chan_width.x(), segment_infs, + device_grid_annotation, through_channel); num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, layer, chan_width.y(), segment_infs, + device_grid_annotation, through_channel); return num_rr_nodes_per_type; @@ -332,6 +361,8 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel) { VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); @@ -339,6 +370,8 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, layer, chan_width, segment_infs, + device_grid_annotation, + shrink_boundary, through_channel); /* Reserve the number of node to be memory efficient */ @@ -825,6 +858,8 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel) { /* For X-direction Channel: CHANX */ for (size_t iy = 0; iy < grids.height() - 1; ++iy) { @@ -839,6 +874,10 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, && (false == is_chanx_exist(grids, layer, chanx_coord))) { continue; } + /* Bypass if the routing channel does not exist when a shrink boundary is considered */ + if (shrink_boundary && !device_grid_annotation.is_chanx_exist(chanx_coord)) { + continue; + } bool force_start = false; bool force_end = false; @@ -850,6 +889,9 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_start = true; } + if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, LEFT)) { + force_start = true; + } /* All the tracks have to end when * - the routing channel touch the LEFT side a heterogeneous block @@ -858,6 +900,9 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_end = true; } + if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, RIGHT)) { + force_end = true; + } ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); @@ -933,6 +978,8 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel) { /* For Y-direction Channel: CHANY */ for (size_t ix = 0; ix < grids.width() - 1; ++ix) { @@ -947,6 +994,10 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, && (false == is_chany_exist(grids, layer, chany_coord))) { continue; } + /* Bypass if the routing channel does not exist when a shrink boundary is considered */ + if (shrink_boundary && !device_grid_annotation.is_chany_exist(chany_coord)) { + continue; + } bool force_start = false; bool force_end = false; @@ -958,6 +1009,9 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_start = true; } + if (shrink_boundary && device_grid_annotation.borderline(chany_coord, BOTTOM)) { + force_start = true; + } /* All the tracks have to end when * - the routing channel touch the BOTTOM side a heterogeneous block @@ -966,6 +1020,9 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_end = true; } + if (shrink_boundary && device_grid_annotation.borderline(chany_coord, TOP)) { + force_end = true; + } ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); @@ -1069,6 +1126,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel) { /* Allocates and loads all the structures needed for fast lookups of the * * index of an rr_node. rr_node_indices is a matrix containing the index * @@ -1099,6 +1158,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, grids, layer, chan_width.x(), segment_infs, + device_grid_annotation, + shrink_boundary, through_channel); load_chany_rr_nodes_basic_info(rr_graph, @@ -1108,6 +1169,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, grids, layer, chan_width.y(), segment_infs, + device_grid_annotation, + shrink_boundary, through_channel); reverse_dec_chan_rr_node_track_ids(rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 85cd0e69e79..c52198196da 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -12,6 +12,7 @@ /* Headers from vpr library */ #include "device_grid.h" +#include "device_grid_annotation.h" #include "rr_node_types.h" #include "rr_graph_view.h" #include "rr_graph_builder.h" @@ -26,6 +27,8 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel); void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, @@ -39,6 +42,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const std::vector& segment_infs, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, const bool& through_channel); #endif From a367a3ffd28e6b1381a471b30c344e1b244ef305 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Aug 2023 19:37:35 -0700 Subject: [PATCH 166/453] [core] debugging --- libs/libarchfpga/src/physical_types.h | 1 + vpr/src/base/vpr_types.h | 1 + .../device_grid_annotation.cpp | 65 +++++++++++-------- .../device_grid_annotation.h | 7 +- .../tileable_rr_graph_node_builder.cpp | 8 +++ 5 files changed, 48 insertions(+), 34 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index ddbf7ad98a6..2999b3357ce 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1963,6 +1963,7 @@ struct t_arch { /* Xifan Tang: options for tileable routing architectures */ bool tileable; + bool shrink_boundary; bool through_channel; t_chan_width_dist Chans; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 9c9e862517d..7b98cc2c0e0 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1482,6 +1482,7 @@ struct t_det_routing_arch { /* Xifan Tang: tileable routing */ bool tileable; + bool shrink_boundary; bool through_channel; short global_route_switch; diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp index e0f28fb6f00..d1e8237a01c 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -1,7 +1,6 @@ #include "device_grid_annotation.h" - -/* Begin namespace openfpga */ -namespace openfpga { +#include "vtr_log.h" +#include "vpr_utils.h" DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid, const bool& shrink) { alloc(grid); @@ -19,6 +18,9 @@ void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& shrink) { for (size_t iy = 0; iy < grid.height(); ++iy) { for (e_side side : SIDES) { borderline_types_[ix][iy][side] = is_empty_zone(grid, vtr::Point(ix, iy), side, shrink); + if (borderline_types_[ix][iy][side]) { + VTR_LOG("[%lu][%lu][%s] is set as empty zone\n", ix, iy, SIDE_STRING[side]); + } } } } @@ -28,11 +30,8 @@ bool DeviceGridAnnotation::is_empty_zone(const DeviceGrid& grid, const vtr::Poin bool empty_zone = true; /* With the given side, expand on the direction */ if (side == TOP) { - if (iy == grid.height() - 1) { - return empty_zone; - } if (shrink) { - for (iy = coord.y() + 1; iy < grid.height(); ++iy) { + for (size_t iy = coord.y(); iy < grid.height(); ++iy) { if (!is_empty_type(grid.get_physical_type({coord.x(), iy, 0}))) { empty_zone = false; break; @@ -40,11 +39,8 @@ bool DeviceGridAnnotation::is_empty_zone(const DeviceGrid& grid, const vtr::Poin } } } else if (side == RIGHT) { - if (ix == grid.width() - 1) { - return empty_zone; - } if (shrink) { - for (ix = coord.x() + 1; ix < grid.height(); ++ix) { + for (size_t ix = coord.x(); ix < grid.width(); ++ix) { if (!is_empty_type(grid.get_physical_type({ix, coord.y(), 0}))) { empty_zone = false; break; @@ -52,11 +48,8 @@ bool DeviceGridAnnotation::is_empty_zone(const DeviceGrid& grid, const vtr::Poin } } } else if (side == BOTTOM) { - if (iy == 0) { - return empty_zone; - } if (shrink) { - for (iy = coord.y() - 1; iy >= 0; --iy) { + for (size_t iy = coord.y(); iy >= 0; --iy) { if (!is_empty_type(grid.get_physical_type({coord.x(), iy, 0}))) { empty_zone = false; break; @@ -64,11 +57,8 @@ bool DeviceGridAnnotation::is_empty_zone(const DeviceGrid& grid, const vtr::Poin } } } else if (side == LEFT) { - if (ix == 0) { - return empty_zone; - } if (shrink) { - for (ix = coord.x() - 1; ix >= 0; --ix) { + for (size_t ix = coord.x(); ix >= 0; --ix) { if (!is_empty_type(grid.get_physical_type({ix, coord.y(), 0}))) { empty_zone = false; break; @@ -84,30 +74,49 @@ bool DeviceGridAnnotation::is_chanx_exist(const vtr::Point& coord) const if (coord.y() == borderline_types_.dim_size(2) - 1) { return false; } - return !borderline_types[coord.x()][coord.y()][TOP] || !borderline_types[coord.x()][coord.y() + 1][BOTTOM]; + return !borderline_types_[coord.x()][coord.y()][TOP]; } bool DeviceGridAnnotation::is_chany_exist(const vtr::Point& coord) const { if (coord.x() == borderline_types_.dim_size(1) - 1) { return false; } - return !borderline_types[coord.x()][coord.y()][RIGHT] || !borderline_types[coord.x() + 1][coord.y()][LEFT]; + return !borderline_types_[coord.x() + 1][coord.y()][LEFT]; } bool DeviceGridAnnotation::borderline(const vtr::Point& coord, const e_side& side) const { /* Check boundary */ - if (coord.x() >= borderline_types_.dim_size(1) || coord.y() >= borderline_types_.dim_size(2)) { + if (coord.x() >= borderline_types_.dim_size(0) || coord.y() >= borderline_types_.dim_size(1)) { VTR_LOG_ERROR("Given coordinate (%lu, %lu) is out of device grid size (%lu, %lu)!\n", - coord.x(), coord.y(), borderline_types_.dim_size(1), borderline_types_.dim_size(2)); + coord.x(), coord.y(), borderline_types_.dim_size(0), borderline_types_.dim_size(1)); exit(1); } if (side == NUM_SIDES) { VTR_LOG_ERROR("Invalid side. Expect [TOP|RIGHT|BOTTOM|LEFT]!\n"); exit(1); } - return borderline_types_[coord.x()][coord.y()][side]; -} - -} /* End namespace openfpga*/ + vtr::Point neighbor_coord(coord.x(), coord.y()); + if (side == LEFT) { + if (coord.x() == 0) { + return true; + } + neighbor_coord.set_x(coord.x() - 1); + } else if (side == RIGHT) { + if (coord.x() == borderline_types_.dim_size(0) - 1) { + return true; + } + neighbor_coord.set_x(coord.x() + 1); + } else if (side == TOP) { + if (coord.y() == borderline_types_.dim_size(1) - 1) { + return true; + } + neighbor_coord.set_y(coord.y() + 1); + } else if (side == BOTTOM) { + if (coord.y() == 0) { + return true; + } + neighbor_coord.set_y(coord.y() - 1); + } -#endif + return borderline_types_[coord.x()][coord.y()][side] != borderline_types_[neighbor_coord.x()][neighbor_coord.y()][side]; +} diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.h b/vpr/src/tileable_rr_graph/device_grid_annotation.h index 1fd288db8b7..9663e9e8ede 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.h +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.h @@ -10,9 +10,6 @@ #include "physical_types.h" #include "device_grid.h" -/* Begin namespace openfpga */ -namespace openfpga { - /** @brief This is the data structure to provide additional data for the device grid: * - Border of the device grid (check where the empty types cover the perimeters) */ @@ -40,12 +37,10 @@ class DeviceGridAnnotation { private: /* Private validators */ /** @brief Check all the adjacent grid until perimeter. To be an empty zone with a given side, there should be all empty types from the given side to the perimeter */ - bool is_empty_zone(const DeviceGrid& grid, const vtr::Point& coord, const bool& shrink) const; + bool is_empty_zone(const DeviceGrid& grid, const vtr::Point& coord, const e_side& side, const bool& shrink) const; private: /* Internal data */ vtr::NdMatrix, 2> borderline_types_; }; -} /* End namespace openfpga*/ - #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 2b7e6a93a7a..70d17eda616 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -338,11 +338,13 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, chan_width.x(), segment_infs, device_grid_annotation, + shrink_boundary, through_channel); num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, layer, chan_width.y(), segment_infs, device_grid_annotation, + shrink_boundary, through_channel); return num_rr_nodes_per_type; @@ -876,6 +878,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, } /* Bypass if the routing channel does not exist when a shrink boundary is considered */ if (shrink_boundary && !device_grid_annotation.is_chanx_exist(chanx_coord)) { + VTR_LOG("Skip chanx[%lu][%lu] as it is in empty zone\n", ix, iy); continue; } @@ -890,6 +893,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, force_start = true; } if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, LEFT)) { + VTR_LOG("Force to start chanx[%lu][%lu]\n", ix, iy); force_start = true; } @@ -901,6 +905,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, force_end = true; } if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, RIGHT)) { + VTR_LOG("Force to end chanx[%lu][%lu]\n", ix, iy); force_end = true; } @@ -996,6 +1001,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, } /* Bypass if the routing channel does not exist when a shrink boundary is considered */ if (shrink_boundary && !device_grid_annotation.is_chany_exist(chany_coord)) { + VTR_LOG("Skip chany[%lu][%lu] as it is in empty zone\n", ix, iy); continue; } @@ -1010,6 +1016,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, force_start = true; } if (shrink_boundary && device_grid_annotation.borderline(chany_coord, BOTTOM)) { + VTR_LOG("Force to start chany[%lu][%lu]\n", ix, iy); force_start = true; } @@ -1021,6 +1028,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, force_end = true; } if (shrink_boundary && device_grid_annotation.borderline(chany_coord, TOP)) { + VTR_LOG("Force to end chany[%lu][%lu]\n", ix, iy); force_end = true; } From d33d1a09902e0ce63965ab08904b0750d41c9698 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Aug 2023 19:39:29 -0700 Subject: [PATCH 167/453] [core] code format --- .../device_grid_annotation.cpp | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp index d1e8237a01c..6fa91c9f32b 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -19,7 +19,7 @@ void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& shrink) { for (e_side side : SIDES) { borderline_types_[ix][iy][side] = is_empty_zone(grid, vtr::Point(ix, iy), side, shrink); if (borderline_types_[ix][iy][side]) { - VTR_LOG("[%lu][%lu][%s] is set as empty zone\n", ix, iy, SIDE_STRING[side]); + VTR_LOG("[%lu][%lu][%s] is set as empty zone\n", ix, iy, SIDE_STRING[side]); } } } @@ -97,25 +97,25 @@ bool DeviceGridAnnotation::borderline(const vtr::Point& coord, const e_s } vtr::Point neighbor_coord(coord.x(), coord.y()); if (side == LEFT) { - if (coord.x() == 0) { - return true; - } - neighbor_coord.set_x(coord.x() - 1); + if (coord.x() == 0) { + return true; + } + neighbor_coord.set_x(coord.x() - 1); } else if (side == RIGHT) { - if (coord.x() == borderline_types_.dim_size(0) - 1) { - return true; - } - neighbor_coord.set_x(coord.x() + 1); + if (coord.x() == borderline_types_.dim_size(0) - 1) { + return true; + } + neighbor_coord.set_x(coord.x() + 1); } else if (side == TOP) { - if (coord.y() == borderline_types_.dim_size(1) - 1) { - return true; - } - neighbor_coord.set_y(coord.y() + 1); + if (coord.y() == borderline_types_.dim_size(1) - 1) { + return true; + } + neighbor_coord.set_y(coord.y() + 1); } else if (side == BOTTOM) { - if (coord.y() == 0) { - return true; - } - neighbor_coord.set_y(coord.y() - 1); + if (coord.y() == 0) { + return true; + } + neighbor_coord.set_y(coord.y() - 1); } return borderline_types_[coord.x()][coord.y()][side] != borderline_types_[neighbor_coord.x()][neighbor_coord.y()][side]; From 26adc8522beb5dfda33fdfe7cb0f977aae760060 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Aug 2023 20:36:52 -0700 Subject: [PATCH 168/453] [core] now shrink boundary is working --- .../device_grid_annotation.cpp | 82 +++++++++++-------- .../device_grid_annotation.h | 10 ++- .../tileable_rr_graph_node_builder.cpp | 16 ++-- 3 files changed, 64 insertions(+), 44 deletions(-) diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp index 6fa91c9f32b..0455d3a034e 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -9,19 +9,20 @@ DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid, const bool& s void DeviceGridAnnotation::alloc(const DeviceGrid& grid) { /* Allocate */ - borderline_types_.resize({grid.width(), grid.height()}); + chanx_existence_.resize({grid.width(), grid.height()}, false); + chany_existence_.resize({grid.width(), grid.height()}, false); } void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& shrink) { /* If shrink is not considered, perimeters are the borderlines */ - for (size_t ix = 0; ix < grid.width(); ++ix) { - for (size_t iy = 0; iy < grid.height(); ++iy) { - for (e_side side : SIDES) { - borderline_types_[ix][iy][side] = is_empty_zone(grid, vtr::Point(ix, iy), side, shrink); - if (borderline_types_[ix][iy][side]) { - VTR_LOG("[%lu][%lu][%s] is set as empty zone\n", ix, iy, SIDE_STRING[side]); - } - } + for (size_t iy = 0; iy < grid.height() - 1; ++iy) { + for (size_t ix = 1; ix < grid.width() - 1; ++ix) { + chanx_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({ix, iy + 1, 0})); + } + } + for (size_t ix = 0; ix < grid.width() - 1; ++ix) { + for (size_t iy = 1; iy < grid.height() - 1; ++iy) { + chany_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({ix, iy, 0})); } } } @@ -71,52 +72,67 @@ bool DeviceGridAnnotation::is_empty_zone(const DeviceGrid& grid, const vtr::Poin } bool DeviceGridAnnotation::is_chanx_exist(const vtr::Point& coord) const { - if (coord.y() == borderline_types_.dim_size(2) - 1) { - return false; - } - return !borderline_types_[coord.x()][coord.y()][TOP]; + return chanx_existence_[coord.x()][coord.y()]; } bool DeviceGridAnnotation::is_chany_exist(const vtr::Point& coord) const { - if (coord.x() == borderline_types_.dim_size(1) - 1) { - return false; + return chany_existence_[coord.x()][coord.y()]; +} + +bool DeviceGridAnnotation::is_chanx_start(const vtr::Point& coord) const { + vtr::Point neighbor_coord = get_neighbor_coord(coord, LEFT); + if (neighbor_coord == coord) { + return true; } - return !borderline_types_[coord.x() + 1][coord.y()][LEFT]; + return chanx_existence_[coord.x()][coord.y()] != chanx_existence_[neighbor_coord.x()][neighbor_coord.y()]; } -bool DeviceGridAnnotation::borderline(const vtr::Point& coord, const e_side& side) const { - /* Check boundary */ - if (coord.x() >= borderline_types_.dim_size(0) || coord.y() >= borderline_types_.dim_size(1)) { - VTR_LOG_ERROR("Given coordinate (%lu, %lu) is out of device grid size (%lu, %lu)!\n", - coord.x(), coord.y(), borderline_types_.dim_size(0), borderline_types_.dim_size(1)); - exit(1); +bool DeviceGridAnnotation::is_chanx_end(const vtr::Point& coord) const { + vtr::Point neighbor_coord = get_neighbor_coord(coord, RIGHT); + if (neighbor_coord == coord) { + return true; } - if (side == NUM_SIDES) { - VTR_LOG_ERROR("Invalid side. Expect [TOP|RIGHT|BOTTOM|LEFT]!\n"); - exit(1); + return chanx_existence_[coord.x()][coord.y()] != chanx_existence_[neighbor_coord.x()][neighbor_coord.y()]; +} + +bool DeviceGridAnnotation::is_chany_start(const vtr::Point& coord) const { + vtr::Point neighbor_coord = get_neighbor_coord(coord, BOTTOM); + if (neighbor_coord == coord) { + return true; + } + return chany_existence_[coord.x()][coord.y()] != chany_existence_[neighbor_coord.x()][neighbor_coord.y()]; +} + +bool DeviceGridAnnotation::is_chany_end(const vtr::Point& coord) const { + vtr::Point neighbor_coord = get_neighbor_coord(coord, TOP); + if (neighbor_coord == coord) { + return true; } + return chany_existence_[coord.x()][coord.y()] != chany_existence_[neighbor_coord.x()][neighbor_coord.y()]; +} + +vtr::Point DeviceGridAnnotation::get_neighbor_coord(const vtr::Point& coord, const e_side& side) const { vtr::Point neighbor_coord(coord.x(), coord.y()); if (side == LEFT) { if (coord.x() == 0) { - return true; + return coord; } neighbor_coord.set_x(coord.x() - 1); } else if (side == RIGHT) { - if (coord.x() == borderline_types_.dim_size(0) - 1) { - return true; + if (coord.x() == chanx_existence_.dim_size(0) - 1) { + return coord; } neighbor_coord.set_x(coord.x() + 1); } else if (side == TOP) { - if (coord.y() == borderline_types_.dim_size(1) - 1) { - return true; + if (coord.y() == chanx_existence_.dim_size(1) - 1) { + return coord; } neighbor_coord.set_y(coord.y() + 1); } else if (side == BOTTOM) { if (coord.y() == 0) { - return true; + return coord; } neighbor_coord.set_y(coord.y() - 1); } - - return borderline_types_[coord.x()][coord.y()][side] != borderline_types_[neighbor_coord.x()][neighbor_coord.y()][side]; + return neighbor_coord; } diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.h b/vpr/src/tileable_rr_graph/device_grid_annotation.h index 9663e9e8ede..e05a97a8be6 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.h +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.h @@ -28,19 +28,23 @@ class DeviceGridAnnotation { void init(const DeviceGrid& grid, const bool& shrink); public: /* Public accessors */ - /** @brief Check if a given coordinate is on the borderline w.r.t. a given side of the device grid. For example, border(vtr::Point(5,4), TOP) will check if any empty types are above the y=4. If there are at least 1 non-empty type, this is not a border line. Otherwise, it is. */ - bool borderline(const vtr::Point& coord, const e_side& side) const; /** @brief Check if at a given coordinate, a X-direction routing channel should exist or not */ bool is_chanx_exist(const vtr::Point& coord) const; + bool is_chanx_start(const vtr::Point& coord) const; + bool is_chanx_end(const vtr::Point& coord) const; /** @brief Check if at a given coordinate, a Y-direction routing channel should exist or not */ bool is_chany_exist(const vtr::Point& coord) const; + bool is_chany_start(const vtr::Point& coord) const; + bool is_chany_end(const vtr::Point& coord) const; private: /* Private validators */ /** @brief Check all the adjacent grid until perimeter. To be an empty zone with a given side, there should be all empty types from the given side to the perimeter */ bool is_empty_zone(const DeviceGrid& grid, const vtr::Point& coord, const e_side& side, const bool& shrink) const; + vtr::Point get_neighbor_coord(const vtr::Point& coord, const e_side& side) const; private: /* Internal data */ - vtr::NdMatrix, 2> borderline_types_; + vtr::NdMatrix chanx_existence_; + vtr::NdMatrix chany_existence_; }; #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 70d17eda616..f42f18cab52 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -206,7 +206,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_start = true; } - if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, LEFT)) { + if (shrink_boundary && device_grid_annotation.is_chanx_start(chanx_coord)) { force_start = true; } @@ -217,7 +217,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_end = true; } - if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, RIGHT)) { + if (shrink_boundary && device_grid_annotation.is_chanx_end(chanx_coord)) { force_end = true; } @@ -272,7 +272,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_start = true; } - if (shrink_boundary && device_grid_annotation.borderline(chany_coord, BOTTOM)) { + if (shrink_boundary && device_grid_annotation.is_chany_start(chany_coord)) { force_start = true; } @@ -283,7 +283,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_end = true; } - if (shrink_boundary && device_grid_annotation.borderline(chany_coord, TOP)) { + if (shrink_boundary && device_grid_annotation.is_chany_end(chany_coord)) { force_end = true; } @@ -892,7 +892,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_start = true; } - if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, LEFT)) { + if (shrink_boundary && device_grid_annotation.is_chanx_start(chanx_coord)) { VTR_LOG("Force to start chanx[%lu][%lu]\n", ix, iy); force_start = true; } @@ -904,7 +904,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { force_end = true; } - if (shrink_boundary && device_grid_annotation.borderline(chanx_coord, RIGHT)) { + if (shrink_boundary && device_grid_annotation.is_chanx_end(chanx_coord)) { VTR_LOG("Force to end chanx[%lu][%lu]\n", ix, iy); force_end = true; } @@ -1015,7 +1015,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_start = true; } - if (shrink_boundary && device_grid_annotation.borderline(chany_coord, BOTTOM)) { + if (shrink_boundary && device_grid_annotation.is_chany_start(chany_coord)) { VTR_LOG("Force to start chany[%lu][%lu]\n", ix, iy); force_start = true; } @@ -1027,7 +1027,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { force_end = true; } - if (shrink_boundary && device_grid_annotation.borderline(chany_coord, TOP)) { + if (shrink_boundary && device_grid_annotation.is_chany_end(chany_coord)) { VTR_LOG("Force to end chany[%lu][%lu]\n", ix, iy); force_end = true; } From a261464ffd70471bb94efd12d8db427dbd34dd33 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Aug 2023 23:23:05 -0700 Subject: [PATCH 169/453] [core] code format and clean up warnings --- .../device_grid_annotation.cpp | 54 ++----------------- .../device_grid_annotation.h | 12 +---- .../tileable_rr_graph_builder.cpp | 2 +- 3 files changed, 8 insertions(+), 60 deletions(-) diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp index 0455d3a034e..e389af027ed 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -2,9 +2,9 @@ #include "vtr_log.h" #include "vpr_utils.h" -DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid, const bool& shrink) { +DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid) { alloc(grid); - init(grid, shrink); + init(grid); } void DeviceGridAnnotation::alloc(const DeviceGrid& grid) { @@ -13,64 +13,20 @@ void DeviceGridAnnotation::alloc(const DeviceGrid& grid) { chany_existence_.resize({grid.width(), grid.height()}, false); } -void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& shrink) { +void DeviceGridAnnotation::init(const DeviceGrid& grid) { /* If shrink is not considered, perimeters are the borderlines */ for (size_t iy = 0; iy < grid.height() - 1; ++iy) { for (size_t ix = 1; ix < grid.width() - 1; ++ix) { - chanx_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({ix, iy + 1, 0})); + chanx_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({(int)ix, (int)iy + 1, 0})); } } for (size_t ix = 0; ix < grid.width() - 1; ++ix) { for (size_t iy = 1; iy < grid.height() - 1; ++iy) { - chany_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({ix, iy, 0})); + chany_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({(int)ix, (int)iy, 0})); } } } -bool DeviceGridAnnotation::is_empty_zone(const DeviceGrid& grid, const vtr::Point& coord, const e_side& side, const bool& shrink) const { - bool empty_zone = true; - /* With the given side, expand on the direction */ - if (side == TOP) { - if (shrink) { - for (size_t iy = coord.y(); iy < grid.height(); ++iy) { - if (!is_empty_type(grid.get_physical_type({coord.x(), iy, 0}))) { - empty_zone = false; - break; - } - } - } - } else if (side == RIGHT) { - if (shrink) { - for (size_t ix = coord.x(); ix < grid.width(); ++ix) { - if (!is_empty_type(grid.get_physical_type({ix, coord.y(), 0}))) { - empty_zone = false; - break; - } - } - } - } else if (side == BOTTOM) { - if (shrink) { - for (size_t iy = coord.y(); iy >= 0; --iy) { - if (!is_empty_type(grid.get_physical_type({coord.x(), iy, 0}))) { - empty_zone = false; - break; - } - } - } - } else if (side == LEFT) { - if (shrink) { - for (size_t ix = coord.x(); ix >= 0; --ix) { - if (!is_empty_type(grid.get_physical_type({ix, coord.y(), 0}))) { - empty_zone = false; - break; - } - } - } - } - - return empty_zone; -} - bool DeviceGridAnnotation::is_chanx_exist(const vtr::Point& coord) const { return chanx_existence_[coord.x()][coord.y()]; } diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.h b/vpr/src/tileable_rr_graph/device_grid_annotation.h index e05a97a8be6..377c850909b 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.h +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.h @@ -15,17 +15,11 @@ */ class DeviceGridAnnotation { public: /* Constructor */ - /** @brief Build the annotation. When shrink is enable, a boundary line is drawn when all the empty types are found between the line and the perimeter. For example - * boundry line perimeter - * v v - * clb | empty empty empty | - * Otherwise, the boundary line is just the perimeter. - */ - DeviceGridAnnotation(const DeviceGrid& grid, const bool& shrink); + DeviceGridAnnotation(const DeviceGrid& grid); private: /* Private mutators */ void alloc(const DeviceGrid& grid); - void init(const DeviceGrid& grid, const bool& shrink); + void init(const DeviceGrid& grid); public: /* Public accessors */ /** @brief Check if at a given coordinate, a X-direction routing channel should exist or not */ @@ -38,8 +32,6 @@ class DeviceGridAnnotation { bool is_chany_end(const vtr::Point& coord) const; private: /* Private validators */ - /** @brief Check all the adjacent grid until perimeter. To be an empty zone with a given side, there should be all empty types from the given side to the perimeter */ - bool is_empty_zone(const DeviceGrid& grid, const vtr::Point& coord, const e_side& side, const bool& shrink) const; vtr::Point get_neighbor_coord(const vtr::Point& coord, const e_side& side) const; private: /* Internal data */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 58ed206d3b2..b34ad4bfa9a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -104,7 +104,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ DeviceContext& device_ctx = g_vpr_ctx.mutable_device(); /* Annotate the device grid on the boundry */ - DeviceGridAnnotation device_grid_annotation(device_ctx.grid, shrink_boundary); + DeviceGridAnnotation device_grid_annotation(device_ctx.grid); /* The number of segments are in general small, reserve segments may not bring * significant memory efficiency */ From c92a92fe36c68f9c595157a7703d6632cc170ee8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 11 Aug 2023 11:50:46 -0700 Subject: [PATCH 170/453] [core] remove debugging messages --- .../tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 6 ------ 1 file changed, 6 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index f42f18cab52..db813e34b22 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -878,7 +878,6 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, } /* Bypass if the routing channel does not exist when a shrink boundary is considered */ if (shrink_boundary && !device_grid_annotation.is_chanx_exist(chanx_coord)) { - VTR_LOG("Skip chanx[%lu][%lu] as it is in empty zone\n", ix, iy); continue; } @@ -893,7 +892,6 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, force_start = true; } if (shrink_boundary && device_grid_annotation.is_chanx_start(chanx_coord)) { - VTR_LOG("Force to start chanx[%lu][%lu]\n", ix, iy); force_start = true; } @@ -905,7 +903,6 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, force_end = true; } if (shrink_boundary && device_grid_annotation.is_chanx_end(chanx_coord)) { - VTR_LOG("Force to end chanx[%lu][%lu]\n", ix, iy); force_end = true; } @@ -1001,7 +998,6 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, } /* Bypass if the routing channel does not exist when a shrink boundary is considered */ if (shrink_boundary && !device_grid_annotation.is_chany_exist(chany_coord)) { - VTR_LOG("Skip chany[%lu][%lu] as it is in empty zone\n", ix, iy); continue; } @@ -1016,7 +1012,6 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, force_start = true; } if (shrink_boundary && device_grid_annotation.is_chany_start(chany_coord)) { - VTR_LOG("Force to start chany[%lu][%lu]\n", ix, iy); force_start = true; } @@ -1028,7 +1023,6 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, force_end = true; } if (shrink_boundary && device_grid_annotation.is_chany_end(chany_coord)) { - VTR_LOG("Force to end chany[%lu][%lu]\n", ix, iy); force_end = true; } From 8f4c5567f4ff92db0659d54dd1eb6435d3b7a9f6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 11 Aug 2023 12:19:06 -0700 Subject: [PATCH 171/453] [lib] code format --- libs/libvtrutil/src/vtr_geometry.h | 12 ++++++------ libs/libvtrutil/src/vtr_strong_id.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index f5bdb24bfff..1e11f87e1d7 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -74,10 +74,10 @@ class Point { T y() const; ///@brief == operator - friend bool operator==<>(Point lhs, Point rhs); + friend bool operator== <>(Point lhs, Point rhs); ///@brief != operator - friend bool operator!=<>(Point lhs, Point rhs); + friend bool operator!= <>(Point lhs, Point rhs); ///@brief < operator friend bool operator< <>(Point lhs, Point rhs); @@ -175,10 +175,10 @@ class Rect { bool empty() const; ///@brief == operator - friend bool operator==<>(const Rect& lhs, const Rect& rhs); + friend bool operator== <>(const Rect& lhs, const Rect& rhs); ///@brief != operator - friend bool operator!=<>(const Rect& lhs, const Rect& rhs); + friend bool operator!= <>(const Rect& lhs, const Rect& rhs); public: //Mutators ///@brief set xmin to a point @@ -299,10 +299,10 @@ class RectUnion { * * Note: does not check whether the representations they are equivalent */ - friend bool operator==<>(const RectUnion& lhs, const RectUnion& rhs); + friend bool operator== <>(const RectUnion& lhs, const RectUnion& rhs); ///@brief != operator - friend bool operator!=<>(const RectUnion& lhs, const RectUnion& rhs); + friend bool operator!= <>(const RectUnion& lhs, const RectUnion& rhs); private: // Note that a union of rectanges may have holes and may not be contiguous diff --git a/libs/libvtrutil/src/vtr_strong_id.h b/libs/libvtrutil/src/vtr_strong_id.h index 14ac6c31cb0..4f3849df094 100644 --- a/libs/libvtrutil/src/vtr_strong_id.h +++ b/libs/libvtrutil/src/vtr_strong_id.h @@ -209,9 +209,9 @@ class StrongId { * Note that since these are templated functions we provide an empty set of template parameters * after the function name (i.e. <>) */ - friend constexpr bool operator==<>(const StrongId& lhs, const StrongId& rhs); + friend constexpr bool operator== <>(const StrongId& lhs, const StrongId& rhs); ///@brief != operator - friend constexpr bool operator!=<>(const StrongId& lhs, const StrongId& rhs); + friend constexpr bool operator!= <>(const StrongId& lhs, const StrongId& rhs); ///@brief < operator friend constexpr bool operator< <>(const StrongId& lhs, const StrongId& rhs); From 62fa48399eabb8788844ad852fca6cdec800accf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Aug 2023 11:36:41 -0700 Subject: [PATCH 172/453] [lib] fixed a bug when supporting subtile index in custom pin location --- libs/libarchfpga/src/read_xml_arch_file.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 4842d67a657..7983cadc085 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -3549,7 +3549,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, //A pin specification should contain only the block name, and not any instance count information //A pin specification may contain instance count, but should be in the range of capacity int inst_lsb = 0; - int inst_msb = PhysicalTileType->capacity - 1; + int inst_msb = SubTile->capacity.total() - 1; if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) { /* Extract range numbers */ inst_lsb = inst_port.instance_low_index(); @@ -3558,10 +3558,10 @@ static void ProcessPinLocations(pugi::xml_node Locations, std::swap(inst_lsb, inst_msb); } /* Check if we have a valid range */ - if (inst_lsb < 0 || inst_msb > PhysicalTileType->capacity - 1) { + if (inst_lsb < 0 || inst_msb > SubTile->capacity.total() - 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Pin location specification '%s' contain an out-of-range instance. Expect [%d:%d]", - token.c_str(), 0, PhysicalTileType->capacity - 1); + token.c_str(), 0, SubTile->capacity.total() - 1); } } @@ -3599,7 +3599,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, VTR_ASSERT(pin_low_idx >= 0); VTR_ASSERT(pin_high_idx >= 0); - for (int iinst = inst_lsb; iinst <= inst_msb; ++iinst) { + for (int iinst = inst_lsb + SubTile->capacity.low; iinst <= inst_msb + SubTile->capacity.low; ++iinst) { for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) { //Record that the pin has it's location specified port_pins_with_specified_locations[iinst][inst_port.port_name()].insert(ipin); @@ -3612,7 +3612,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, } //Check for any pins missing location specs - for (int iinst = 0; iinst < PhysicalTileType->capacity; ++iinst) { + for (int iinst = SubTile->capacity.low; iinst < SubTile->capacity.high; ++iinst) { for (const auto& port : SubTile->ports) { for (int ipin = 0; ipin < port.num_pins; ++ipin) { if (!port_pins_with_specified_locations[iinst][port.name].count(ipin)) { From 442d0eb9032f0ddea29a9108989f19520642a121 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Aug 2023 14:58:35 -0700 Subject: [PATCH 173/453] [core] tileable rr graph builder supports different segments in x and Y axis --- .../librrgraph/src/base/get_parallel_segs.cpp | 9 ++-- libs/librrgraph/src/base/get_parallel_segs.h | 5 ++- .../tileable_chan_details_builder.cpp | 5 ++- .../tileable_rr_graph_builder.cpp | 15 ++++--- .../tileable_rr_graph_edge_builder.cpp | 4 +- .../tileable_rr_graph_edge_builder.h | 3 ++ .../tileable_rr_graph_gsb.cpp | 9 ++-- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 10 +++-- .../tileable_rr_graph_node_builder.cpp | 41 ++++++++++++++----- .../tileable_rr_graph_node_builder.h | 9 +++- 10 files changed, 76 insertions(+), 34 deletions(-) diff --git a/libs/librrgraph/src/base/get_parallel_segs.cpp b/libs/librrgraph/src/base/get_parallel_segs.cpp index d20b3066992..adc3bce4f64 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.cpp +++ b/libs/librrgraph/src/base/get_parallel_segs.cpp @@ -4,14 +4,17 @@ *Segments that have BOTH_AXIS attribute value are always included in the returned vector.*/ std::vector get_parallel_segs(const std::vector& segment_inf, t_unified_to_parallel_seg_index& seg_index_map, - enum e_parallel_axis parallel_axis) { + enum e_parallel_axis parallel_axis, + bool keep_original_index) { std::vector result; for (size_t i = 0; i < segment_inf.size(); ++i) { if (segment_inf[i].parallel_axis == parallel_axis || segment_inf[i].parallel_axis == BOTH_AXIS) { result.push_back(segment_inf[i]); - result[result.size() - 1].seg_index = i; + if (!keep_original_index) { + result[result.size() - 1].seg_index = i; + } seg_index_map.insert(std::make_pair(i, std::make_pair(result.size() - 1, parallel_axis))); } } return result; -} \ No newline at end of file +} diff --git a/libs/librrgraph/src/base/get_parallel_segs.h b/libs/librrgraph/src/base/get_parallel_segs.h index c88b2c88701..70539863dda 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.h +++ b/libs/librrgraph/src/base/get_parallel_segs.h @@ -6,6 +6,7 @@ std::vector get_parallel_segs(const std::vector& segment_inf, t_unified_to_parallel_seg_index& seg_index_map, - enum e_parallel_axis parallel_axis); + enum e_parallel_axis parallel_axis, + bool keep_original_index = false); -#endif \ No newline at end of file +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index 1dbdb7a3917..c0def1dfa69 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -200,9 +200,10 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, /* Since this is a unidirectional routing architecture, * Add a pair of tracks, 1 INC track and 1 DEC track */ - chan_node_details.add_track(cur_track, Direction::INC, iseg, seg_len, seg_start, seg_end); + int seg_index = segment_inf[iseg].seg_index; + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len, seg_start, seg_end); cur_track++; - chan_node_details.add_track(cur_track, Direction::DEC, iseg, seg_len, seg_start, seg_end); + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len, seg_start, seg_end); cur_track++; } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index b34ad4bfa9a..40feca7d518 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -148,6 +148,11 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* A temp data about the track ids for each CHANX and CHANY rr_node */ std::map> rr_node_track_ids; + /* Get the routing segments on X-axis and Y-axis separately */ + t_unified_to_parallel_seg_index segment_index_map; + std::vector segment_inf_x = get_parallel_segs(segment_inf, segment_index_map, X_AXIS, true); + std::vector segment_inf_y = get_parallel_segs(segment_inf, segment_index_map, Y_AXIS, true); + /************************ * Allocate the rr_nodes ************************/ @@ -155,7 +160,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ rr_node_driver_switches, grids, 0, device_chan_width, - segment_inf, + segment_inf_x, segment_inf_y, segment_index_map, device_grid_annotation, shrink_boundary, through_channel); @@ -170,7 +175,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ device_ctx.rr_rc_data, grids, 0, device_chan_width, - segment_inf, + segment_inf_x, segment_inf_y, + segment_index_map, wire_to_ipin_rr_switch, delayless_rr_switch, device_grid_annotation, @@ -245,7 +251,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ rr_node_driver_switches, grids, 0, device_chan_width, - segment_inf, + segment_inf, segment_inf_x, segment_inf_y, Fc_in, Fc_out, sb_type, Fs, sb_subtype, subFs, wire_opposite_side); @@ -289,9 +295,6 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * a. cost_index * b. RC tree ***********************************************************************/ - t_unified_to_parallel_seg_index segment_index_map; - std::vector segment_inf_x = get_parallel_segs(segment_inf, segment_index_map, X_AXIS); - std::vector segment_inf_y = get_parallel_segs(segment_inf, segment_index_map, Y_AXIS); rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 0abc22034ea..36aab795680 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -108,6 +108,8 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, const std::vector>& Fc_in, const std::vector>& Fc_out, const e_switch_block_type& sb_type, @@ -130,7 +132,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, vtr::Point gsb_coord(ix, iy); /* Create a GSB object */ const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, - device_chan_width, segment_inf, + device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord); /* adapt the track_to_ipin_lookup for the GSB nodes */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index d1e66a3c1b5..7cbf219fb0f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -13,6 +13,7 @@ #include "physical_types.h" #include "device_grid.h" #include "rr_graph_obj.h" +#include "rr_graph_type.h" #include "rr_graph_view.h" #include "rr_graph.h" @@ -27,6 +28,8 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, const std::vector>& Fc_in, const std::vector>& Fc_out, const e_switch_block_type& sb_type, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 8d5f5686fa3..fca7d569dfc 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -619,7 +619,8 @@ static RRChan build_one_tileable_rr_chan(const size_t& layer, RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const RRGraphView& rr_graph, const vtr::Point& device_chan_width, - const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, const size_t& layer, const vtr::Point& gsb_coordinate) { /* Create an object to return */ @@ -650,9 +651,9 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, * We do not care starting and ending points here, so set chan_side as NUM_SIDES */ ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width.x(), grids.width() - 1, - false, false, segment_inf); + false, false, segment_inf_x); ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width.y(), grids.height() - 1, - false, false, segment_inf); + false, false, segment_inf_y); switch (side) { case TOP: /* TOP = 0 */ @@ -1238,7 +1239,7 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, continue; } - VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size()); + //VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size()); /* Build track2ipin_map for this IPIN */ build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc_out, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 579309358a2..521aa01ec45 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -38,12 +38,14 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const e_switch_block_type& sb_subtype, const int& subFs, const bool& wire_opposite_side, - const std::vector& segment_inf); + const std::vector& segment_inf_x, + const std::vector& segment_inf_y); RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const RRGraphView& rr_graph, const vtr::Point& device_chan_width, - const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, const size_t& layer, const vtr::Point& gsb_coordinate); @@ -58,7 +60,9 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, - const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const t_unified_to_parallel_seg_index& segment_index_map, const std::vector>& Fc_in); t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index db813e34b22..f45e67d6b2e 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -304,7 +304,9 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chan_width, - const std::vector& segment_infs, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const t_unified_to_parallel_seg_index& segment_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& through_channel) { @@ -336,13 +338,13 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, */ num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, layer, chan_width.x(), - segment_infs, + segment_inf_x, device_grid_annotation, shrink_boundary, through_channel); num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, layer, chan_width.y(), - segment_infs, + segment_inf_y, device_grid_annotation, shrink_boundary, through_channel); @@ -362,7 +364,9 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const size_t& layer, const vtr::Point& chan_width, - const std::vector& segment_infs, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const t_unified_to_parallel_seg_index& segment_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& through_channel) { @@ -371,7 +375,9 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, layer, chan_width, - segment_infs, + segment_inf_x, + segment_inf_y, + segment_index_map, device_grid_annotation, shrink_boundary, through_channel); @@ -748,6 +754,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, const t_rr_type& chan_type, ChanNodeDetails& chan_details, const std::vector& segment_infs, + const t_unified_to_parallel_seg_index& seg_index_map, const int& cost_index_offset) { /* Check each node_id(potential ptc_num) in the channel : * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num @@ -773,13 +780,15 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, /* assign switch id */ size_t seg_id = chan_details.get_track_segment_id(itrack); - rr_node_driver_switches[node] = RRSwitchId(segment_infs[seg_id].arch_opin_switch); + e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + size_t parallel_seg_id = get_parallel_seg_index(seg_id, seg_index_map, wanted_axis); + rr_node_driver_switches[node] = RRSwitchId(segment_infs[parallel_seg_id].arch_opin_switch); /* Update chan_details with node_id */ chan_details.set_track_node_id(itrack, size_t(node)); /* cost index depends on the segment index */ - rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_id)); + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + parallel_seg_id)); /* Finish here, go to next */ } @@ -860,6 +869,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, + const t_unified_to_parallel_seg_index& segment_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& through_channel) { @@ -960,6 +970,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, layer, chanx_coord, CHANX, chanx_details, segment_infs, + segment_index_map, CHANX_COST_INDEX_START); /* Get a copy of node_ids */ track_node_ids = chanx_details.get_track_node_ids(); @@ -980,6 +991,8 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, const size_t& layer, const size_t& chan_width, const std::vector& segment_infs, + const size_t& num_segment_x, + const t_unified_to_parallel_seg_index& seg_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& through_channel) { @@ -1083,7 +1096,8 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, layer, chany_coord, CHANY, chany_details, segment_infs, - CHANX_COST_INDEX_START + segment_infs.size()); + seg_index_map, + CHANX_COST_INDEX_START + num_segment_x); /* Get a copy of node_ids */ track_node_ids = chany_details.get_track_node_ids(); } @@ -1125,7 +1139,9 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const DeviceGrid& grids, const size_t& layer, const vtr::Point& chan_width, - const std::vector& segment_infs, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const t_unified_to_parallel_seg_index& segment_index_map, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, const DeviceGridAnnotation& device_grid_annotation, @@ -1159,7 +1175,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, rr_node_track_ids, grids, layer, chan_width.x(), - segment_infs, + segment_inf_x, + segment_index_map, device_grid_annotation, shrink_boundary, through_channel); @@ -1170,7 +1187,9 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, rr_node_track_ids, grids, layer, chan_width.y(), - segment_infs, + segment_inf_y, + segment_inf_x.size(), + segment_index_map, device_grid_annotation, shrink_boundary, through_channel); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index c52198196da..dbd5a823515 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -14,6 +14,7 @@ #include "device_grid.h" #include "device_grid_annotation.h" #include "rr_node_types.h" +#include "rr_graph_type.h" #include "rr_graph_view.h" #include "rr_graph_builder.h" @@ -26,7 +27,9 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const size_t& layer, const vtr::Point& chan_width, - const std::vector& segment_infs, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const t_unified_to_parallel_seg_index& segment_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& through_channel); @@ -39,7 +42,9 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const DeviceGrid& grids, const size_t& layer, const vtr::Point& chan_width, - const std::vector& segment_infs, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const t_unified_to_parallel_seg_index& segment_index_map, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, const DeviceGridAnnotation& device_grid_annotation, From ec634df07a5be186a0e7b66f2789c4daf2e4b44c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Aug 2023 15:15:22 -0700 Subject: [PATCH 174/453] [core] syntax --- .../tileable_rr_graph/rr_graph_builder_utils.cpp | 15 +++++++++++++++ .../tileable_rr_graph/rr_graph_builder_utils.h | 6 ++++++ .../tileable_rr_graph_builder.cpp | 2 +- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 7 ++----- .../tileable_rr_graph_node_builder.cpp | 5 +---- .../tileable_rr_graph_node_builder.h | 1 - 6 files changed, 25 insertions(+), 11 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 9fb6981bf85..a515e55f218 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -574,3 +574,18 @@ void print_rr_graph_mux_stats(const RRGraph& rr_graph) { find_rr_graph_average_fan_in(rr_graph, cb_node_types)); VTR_LOG("------------------------------------------------\n"); } + +int find_parallel_seg_index(const int abs_index, + const t_unified_to_parallel_seg_index& index_map, + const e_parallel_axis parallel_axis) { + int index = -1; + auto itr_pair = index_map.equal_range(abs_index); + + for (auto itr = itr_pair.first; itr != itr_pair.second; ++itr) { + if (itr->second.second == parallel_axis) { + index = itr->second.first; + } + } + + return index; +} diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index a6ff1b38de0..f53b350de45 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -6,6 +6,7 @@ *******************************************************************/ #include "device_grid.h" #include "rr_graph_obj.h" +#include "rr_graph_type.h" #include "vtr_geometry.h" /******************************************************************** @@ -110,4 +111,9 @@ short find_rr_graph_average_fan_in(const RRGraph& rr_graph, void print_rr_graph_mux_stats(const RRGraph& rr_graph); +/* A copy of the function from rr_graph2.cpp; This is keep tilable rr_graph builder self-contained */ +int find_parallel_seg_index(const int abs_index, + const t_unified_to_parallel_seg_index& index_map, + const e_parallel_axis parallel_axis); + #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 40feca7d518..7a42967952f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -160,7 +160,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ rr_node_driver_switches, grids, 0, device_chan_width, - segment_inf_x, segment_inf_y, segment_index_map, + segment_inf_x, segment_inf_y, device_grid_annotation, shrink_boundary, through_channel); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 521aa01ec45..6c1208ebf46 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -38,8 +38,7 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const e_switch_block_type& sb_subtype, const int& subFs, const bool& wire_opposite_side, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y); + const std::vector& segment_inf); RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const RRGraphView& rr_graph, @@ -60,9 +59,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - const t_unified_to_parallel_seg_index& segment_index_map, + const std::vector& segment_inf, const std::vector>& Fc_in); t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index f45e67d6b2e..ce87b037c83 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -306,7 +306,6 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, const vtr::Point& chan_width, const std::vector& segment_inf_x, const std::vector& segment_inf_y, - const t_unified_to_parallel_seg_index& segment_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& through_channel) { @@ -366,7 +365,6 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const vtr::Point& chan_width, const std::vector& segment_inf_x, const std::vector& segment_inf_y, - const t_unified_to_parallel_seg_index& segment_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& through_channel) { @@ -377,7 +375,6 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, chan_width, segment_inf_x, segment_inf_y, - segment_index_map, device_grid_annotation, shrink_boundary, through_channel); @@ -781,7 +778,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, /* assign switch id */ size_t seg_id = chan_details.get_track_segment_id(itrack); e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; - size_t parallel_seg_id = get_parallel_seg_index(seg_id, seg_index_map, wanted_axis); + size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); rr_node_driver_switches[node] = RRSwitchId(segment_infs[parallel_seg_id].arch_opin_switch); /* Update chan_details with node_id */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index dbd5a823515..27fea172338 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -29,7 +29,6 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const vtr::Point& chan_width, const std::vector& segment_inf_x, const std::vector& segment_inf_y, - const t_unified_to_parallel_seg_index& segment_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& through_channel); From 6c63a3150a900f2d7580913923f94ef35a621fdf Mon Sep 17 00:00:00 2001 From: umariqbal-rs Date: Thu, 24 Aug 2023 12:19:40 +0500 Subject: [PATCH 175/453] updating CMAKE in libencrypt to take libpugixml as linking library --- libs/CMakeLists.txt | 1 + libs/libdecrypt/config.h.in | 9 --------- libs/libencrypt/CMakeLists.txt | 17 +++-------------- libs/libencrypt/config.h.in | 9 --------- libs/libencrypt/main.cpp | 2 +- 5 files changed, 5 insertions(+), 33 deletions(-) delete mode 100644 libs/libdecrypt/config.h.in delete mode 100644 libs/libencrypt/config.h.in diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index d0027806766..a02d6ae1cc7 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -9,6 +9,7 @@ link_libraries(${ADDITIONAL_FLAGS}) add_subdirectory(libarchfpga) add_subdirectory(libvtrutil) add_subdirectory(liblog) +add_subdirectory(libencrypt) add_subdirectory(libdecrypt) add_subdirectory(libpugiutil) add_subdirectory(libvqm) diff --git a/libs/libdecrypt/config.h.in b/libs/libdecrypt/config.h.in deleted file mode 100644 index 25df8342f97..00000000000 --- a/libs/libdecrypt/config.h.in +++ /dev/null @@ -1,9 +0,0 @@ - -#ifndef CONFIG_H -#define CONFIG_H - -#define PRIVATE_KEY "@PRIVATE_KEY@" -#define PASSPHRASE "@PASS_PHRASE@" -// Add more configuration variables as needed - -#endif // CONFIG_H diff --git a/libs/libencrypt/CMakeLists.txt b/libs/libencrypt/CMakeLists.txt index 243ab0d2397..23a589415ac 100644 --- a/libs/libencrypt/CMakeLists.txt +++ b/libs/libencrypt/CMakeLists.txt @@ -4,12 +4,8 @@ project(libencrypt) find_package(PkgConfig REQUIRED) pkg_search_module(OPENSSL REQUIRED openssl) -#file(READ "public_key.pem" PUBLIC_KEY_CONTENTS) file(READ "config.txt" PASSPHRASE_CONTENTS) - -#string(REPLACE "\n" "\\n" PUBLIC_KEY_CONTENTS "${PUBLIC_KEY_CONTENTS}") string(REPLACE "\n" "\\n" PASSPHRASE_CONTENTS "${PASSPHRASE_CONTENTS}") -#set(PUBLIC_KEY "${PUBLIC_KEY_CONTENTS}") set(PASS_PHRASE "${PASSPHRASE_CONTENTS}") add_compile_definitions(PASS_PHRASE="${PASS_PHRASE}") @@ -21,8 +17,8 @@ else() endif() # Source files for the library -file(GLOB_RECURSE LIB_SOURCES src/*.cpp ../EXTERNAL/libpugixml/src/*.cpp) -file(GLOB_RECURSE LIB_HEADERS src/*.hpp src/*.h ../EXTERNAL/libpugixml/src/*.hpp) +file(GLOB_RECURSE LIB_SOURCES src/*.cpp ) +file(GLOB_RECURSE LIB_HEADERS src/*.hpp src/*.h) set(LIB_INCLUDE_DIRS "") foreach(_headerFile ${LIB_HEADERS}) get_filename_component(_dir ${_headerFile} PATH) @@ -30,22 +26,15 @@ foreach(_headerFile ${LIB_HEADERS}) endforeach() list(REMOVE_DUPLICATES LIB_INCLUDE_DIRS) -# Create the library -#add_library(libencrypt STATIC ${LIB_HEADERS} ${LIB_SOURCES}) -#target_include_directories(libencrypt PUBLIC ${LIB_INCLUDE_DIRS}) -#set_target_properties(libencrypt PROPERTIES PREFIX "") # Avoid extra 'lib' prefix -#target_link_libraries(libencrypt PRIVATE ${OPENSSL_LIBRARIES}) # Add executable add_executable(encrypt main.cpp ${LIB_HEADERS} ${LIB_SOURCES} ) -# Include directories containing the header files target_include_directories(encrypt PRIVATE - ${CMAKE_CURRENT_SOURCE_DIR}/../EXTERNAL/libpugixml/src/ ${CMAKE_CURRENT_SOURCE_DIR}/src ) -target_link_libraries(encrypt PRIVATE ${OPENSSL_LIBRARIES}) +target_link_libraries(encrypt PRIVATE ${OPENSSL_LIBRARIES} libpugixml) #install(TARGETS libencrypt DESTINATION bin) #install(FILES ${LIB_HEADERS} DESTINATION include/libencrypt) diff --git a/libs/libencrypt/config.h.in b/libs/libencrypt/config.h.in deleted file mode 100644 index 709a632078f..00000000000 --- a/libs/libencrypt/config.h.in +++ /dev/null @@ -1,9 +0,0 @@ - -#ifndef CONFIG_H -#define CONFIG_H - -#define PUBLIC_KEY "@PUBLIC_KEY@" -#define PASSPHRASE "@PASS_PHRASE@" -// Add more configuration variables as needed - -#endif // CONFIG_H diff --git a/libs/libencrypt/main.cpp b/libs/libencrypt/main.cpp index e454dc56ed5..9e798b00613 100644 --- a/libs/libencrypt/main.cpp +++ b/libs/libencrypt/main.cpp @@ -3,7 +3,7 @@ int main(int argc, char* argv[]) { if (argc < 2) { - std::cerr << "Usage: " << argv[0] << " \n"; + std::cerr << "Usage: " << argv[0] << " \n"; return -1; } From 4014b3297d8cd3e12d52a44a42d1809ea4147729 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Aug 2023 14:50:36 -0700 Subject: [PATCH 176/453] [core] add corner case to judge the existence of switch block in gsb --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 30 ++++++++++++++++++++++++---- vpr/src/tileable_rr_graph/rr_gsb.h | 4 ++-- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 901a9c0bef7..05c1175bf80 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -383,19 +383,41 @@ bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const { } /* check if the SB exist in this GSB */ -bool RRGSB::is_sb_exist() const { - /* if all the channel width is zero and number of OPINs are zero, there is no SB */ +bool RRGSB::is_sb_exist(const RRGraphView& rr_graph) const { + /* Count the number of sides that there are routing wires or opin nodes */ + size_t num_sides_contain_routing_wires = 0; + size_t num_sides_contain_opin_nodes = 0; for (size_t side = 0; side < get_num_sides(); ++side) { SideManager side_manager(side); if (0 != get_chan_width(side_manager.get_side())) { - return true; + num_sides_contain_routing_wires++; } if (0 != get_num_opin_nodes(side_manager.get_side())) { + num_sides_contain_opin_nodes++; + } + } + /* When there are zero nodes, the sb does not exist */ + if (num_sides_contain_routing_wires == 0 && num_sides_contain_opin_nodes == 0) { + return false; + } + /* If there is only 1 side of nodes and there are 0 opin nodes, and there are no incoming edges, this is also an empty switch block */ + if (num_sides_contain_routing_wires == 1 && num_sides_contain_opin_nodes == 0) { + size_t num_incoming_edges = 0; + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + for (size_t itrack = 0; itrack < get_chan_width(side_manager.get_side()); ++itrack) { + if (OUT_PORT != get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + num_sides_contain_routing_wires += get_chan_node_in_edges(rr_graph, side_manager.get_side(), itrack).size(); + } + } + if (num_incoming_edges) { return true; } } - return false; + return true; } /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 77f7b192cd0..7b0e62b2b09 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -128,8 +128,8 @@ class RRGSB { /* check if the connect block exists in the GSB */ bool is_cb_exist(const t_rr_type& cb_type) const; - /* check if the switch block exists in the GSB */ - bool is_sb_exist() const; + /* check if the switch block exists in the GSB, this function checks if a switch block physically exists (no routing wires, no OPIN nodes, and no interconnecting wires) */ + bool is_sb_exist(const RRGraphView& rr_graph) const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */ bool is_sb_node_passing_wire(const RRGraphView& rr_graph, const e_side& node_side, const size_t& track_id) const; From 825a88ef9b9d4f8b4233c8bf3d27eb58f699b1d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Aug 2023 15:22:48 -0700 Subject: [PATCH 177/453] [core] fixed a bug --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 05c1175bf80..754f506185b 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -412,9 +412,7 @@ bool RRGSB::is_sb_exist(const RRGraphView& rr_graph) const { num_sides_contain_routing_wires += get_chan_node_in_edges(rr_graph, side_manager.get_side(), itrack).size(); } } - if (num_incoming_edges) { - return true; - } + return num_incoming_edges ? true : false; } return true; From 690f7cbe80060e911f007146db73db7c0452b9e1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Aug 2023 15:23:10 -0700 Subject: [PATCH 178/453] [core] format --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 754f506185b..09488fc197d 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -412,7 +412,7 @@ bool RRGSB::is_sb_exist(const RRGraphView& rr_graph) const { num_sides_contain_routing_wires += get_chan_node_in_edges(rr_graph, side_manager.get_side(), itrack).size(); } } - return num_incoming_edges ? true : false; + return num_incoming_edges ? true : false; } return true; From 3273c292ea75010409c325ec573d95ebec19ae67 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Aug 2023 15:36:37 -0700 Subject: [PATCH 179/453] [core] fixed a bug --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 09488fc197d..f58a7b8dbc3 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -409,7 +409,7 @@ bool RRGSB::is_sb_exist(const RRGraphView& rr_graph) const { if (OUT_PORT != get_chan_node_direction(side_manager.get_side(), itrack)) { continue; } - num_sides_contain_routing_wires += get_chan_node_in_edges(rr_graph, side_manager.get_side(), itrack).size(); + num_incoming_edges += get_chan_node_in_edges(rr_graph, side_manager.get_side(), itrack).size(); } } return num_incoming_edges ? true : false; From b4a41b588cd5c33ad11ad5c2b72a6343c3029c61 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 14 Sep 2023 10:37:55 -0700 Subject: [PATCH 180/453] [core] fixed a bug in build where tbb is not used. --- vpr/src/base/vpr_api.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index c987b7b739a..92fca012677 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -373,7 +373,9 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { /* Set this here, because tbb::global_control doesn't control anything once it's out of scope * (contrary to the name). */ +#ifdef VPR_USE_TBB tbb::global_control c(tbb::global_control::max_allowed_parallelism, vpr_setup.num_workers); +#endif { //Pack bool pack_success = vpr_pack_flow(vpr_setup, arch); From 8bb5d875a8ead5fd7d1a51e6517cc524c36e2d50 Mon Sep 17 00:00:00 2001 From: coolbreeze413 Date: Thu, 12 Oct 2023 01:57:43 +0530 Subject: [PATCH 181/453] Add 'not found' check for finding file extension of arch xml --- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- libs/libpugiutil/src/pugixml_util.cpp | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 978865ec6de..368105d68ff 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -317,7 +317,7 @@ void XmlReadArch(const char* ArchFile, pugi::xml_node Next; ReqOpt POWER_REQD, SWITCHBLOCKLIST_REQD; - if ((vtr::check_file_name_extension(ArchFile, ".xml") == false) && (vtr::check_file_name_extension(ArchFile, ".xml") == false)) { + if ((vtr::check_file_name_extension(ArchFile, ".xml") == false) && (vtr::check_file_name_extension(ArchFile, ".xmle") == false)) { VTR_LOG_WARN( "Architecture file '%s' may be in incorrect format. " "Expecting .xml or .xmle format for architecture files.\n", diff --git a/libs/libpugiutil/src/pugixml_util.cpp b/libs/libpugiutil/src/pugixml_util.cpp index 8002ce620ff..68badf0e3f3 100644 --- a/libs/libpugiutil/src/pugixml_util.cpp +++ b/libs/libpugiutil/src/pugixml_util.cpp @@ -9,9 +9,12 @@ namespace pugiutil { loc_data load_xml(pugi::xml_document& doc, //Document object to be loaded with file contents const std::string filename) { //Filename to load from //store the position of last '.' in the file name - int position = filename.find_last_of("."); - //store the characters after the '.' from the file_name string - std::string result = filename.substr(position); + size_t position = filename.find_last_of("."); + std::string result = ""; + if(position != std::string::npos) { + //store the characters after the '.' from the file_name string + result = filename.substr(position); + } if (result == ".xmle") { Decryption E1(filename); std::string fn_file = E1.getDecryptedContent(); From 5d2977df2f7adb82fe04c5a08aedc0f7f61e2098 Mon Sep 17 00:00:00 2001 From: coolbreeze413 Date: Thu, 12 Oct 2023 11:59:35 +0530 Subject: [PATCH 182/453] Fix clang-14 formatting complaints --- libs/libpugiutil/src/pugixml_util.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libpugiutil/src/pugixml_util.cpp b/libs/libpugiutil/src/pugixml_util.cpp index 68badf0e3f3..b1597d34963 100644 --- a/libs/libpugiutil/src/pugixml_util.cpp +++ b/libs/libpugiutil/src/pugixml_util.cpp @@ -11,7 +11,7 @@ loc_data load_xml(pugi::xml_document& doc, //Document object to be loaded w //store the position of last '.' in the file name size_t position = filename.find_last_of("."); std::string result = ""; - if(position != std::string::npos) { + if (position != std::string::npos) { //store the characters after the '.' from the file_name string result = filename.substr(position); } From 86ecab70b4d38019b96ea79c797a24f670488c35 Mon Sep 17 00:00:00 2001 From: coolbreeze413 Date: Thu, 12 Oct 2023 12:00:16 +0530 Subject: [PATCH 183/453] Fix missing separator in .github/scripts/hostsetup.sh --- .github/scripts/hostsetup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/hostsetup.sh b/.github/scripts/hostsetup.sh index b274953f791..835c3e95c81 100755 --- a/.github/scripts/hostsetup.sh +++ b/.github/scripts/hostsetup.sh @@ -71,7 +71,7 @@ apt install -y \ gcc-9 \ wget \ openssl \ - libssl-dev + libssl-dev \ libtbb-dev # installing the latest version of cmake From a7d6bfe7e2a4520dd36e7a0f7a8ba73b93c9c382 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 Nov 2023 15:40:07 -0700 Subject: [PATCH 184/453] [core] remove tbb lines --- vpr/src/base/vpr_api.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 63879b5383f..23935a664a2 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -375,9 +375,7 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { /* Set this here, because tbb::global_control doesn't control anything once it's out of scope * (contrary to the name). */ -#ifdef VPR_USE_TBB tbb::global_control c(tbb::global_control::max_allowed_parallelism, vpr_setup.num_workers); -#endif { //Pack bool pack_success = vpr_pack_flow(vpr_setup, arch); From 2be89f98a8735907ddf263d0856879f755c69bd5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 Nov 2023 15:54:38 -0700 Subject: [PATCH 185/453] [core] syntax --- vpr/src/base/vpr_api.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 23935a664a2..b918306ef46 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -376,6 +376,7 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { /* Set this here, because tbb::global_control doesn't control anything once it's out of scope * (contrary to the name). */ tbb::global_control c(tbb::global_control::max_allowed_parallelism, vpr_setup.num_workers); +#endif { //Pack bool pack_success = vpr_pack_flow(vpr_setup, arch); From 81a956f9e13c0ebdb8fa1ff78dc4ad8953a417aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 10:50:06 -0800 Subject: [PATCH 186/453] [vpr] support a new option `opin2all_sides`` for tileable routing architecture --- libs/libarchfpga/src/physical_types.h | 1 + libs/libarchfpga/src/read_xml_arch_file.cpp | 1 + vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/vpr_types.h | 1 + vpr/src/route/rr_graph.cpp | 1 + .../tileable_rr_graph_builder.cpp | 2 ++ .../tileable_rr_graph_builder.h | 1 + .../tileable_rr_graph_edge_builder.cpp | 3 ++- .../tileable_rr_graph_edge_builder.h | 1 + .../tileable_rr_graph_gsb.cpp | 20 ++++++++++++++----- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 3 ++- 11 files changed, 28 insertions(+), 7 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 2999b3357ce..e862ca518ad 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1965,6 +1965,7 @@ struct t_arch { bool tileable; bool shrink_boundary; bool through_channel; + bool opin2all_sides; t_chan_width_dist Chans; enum e_switch_block_type SBType; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 368105d68ff..5895e697d19 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2525,6 +2525,7 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti arch->tileable = get_attribute(layout_tag, "tileable", loc_data, ReqOpt::OPTIONAL).as_bool(false); arch->shrink_boundary = get_attribute(layout_tag, "shrink_boundary", loc_data, ReqOpt::OPTIONAL).as_bool(false); arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->opin2all_sides = get_attribute(layout_tag, "opin2all_sides", loc_data, ReqOpt::OPTIONAL).as_bool(false); //Count the number of or tags size_t auto_layout_cnt = 0; diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index bb063d7a9cf..9917d31568a 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -412,6 +412,7 @@ static void SetupRoutingArch(const t_arch& Arch, RoutingArch->tileable = Arch.tileable; RoutingArch->shrink_boundary = Arch.shrink_boundary; RoutingArch->through_channel = Arch.through_channel; + RoutingArch->opin2all_sides = Arch.opin2all_sides; } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index c6607689612..739537ba58e 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1543,6 +1543,7 @@ struct t_det_routing_arch { bool tileable; bool shrink_boundary; bool through_channel; + bool opin2all_sides; short global_route_switch; short delayless_switch; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 584cf268c86..2658035bac7 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -723,6 +723,7 @@ void create_rr_graph(const t_graph_type graph_type, &det_routing_arch->wire_to_rr_ipin_switch, det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ + det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ false, /* Do not allow passing tracks to be wired to the same routing channels */ Warnings); } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 7a42967952f..8b17e960ed9 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -86,6 +86,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ int* wire_to_rr_ipin_switch, const bool& shrink_boundary, const bool& through_channel, + const bool& opin2all_sides, const bool& wire_opposite_side, int* Warnings) { vtr::ScopedStartFinishTimer timer("Build tileable routing resource graph"); @@ -254,6 +255,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ segment_inf, segment_inf_x, segment_inf_y, Fc_in, Fc_out, sb_type, Fs, sb_subtype, subFs, + opin2all_sides, wire_opposite_side); /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h index 089dcb7a7c4..52a497a7e15 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -31,6 +31,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ int* wire_to_rr_ipin_switch, const bool& shrink_boundary, const bool& through_channel, + const bool& opin2all_sides, const bool& wire_opposite_side, int* Warnings); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 36aab795680..d41cb66c9f9 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -116,6 +116,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const int& Fs, const e_switch_block_type& sb_subtype, const int& subFs, + const bool& opin2all_sides, const bool& wire_opposite_side) { size_t num_edges_to_create = 0; /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ @@ -141,7 +142,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* adapt the opin_to_track_map for the GSB nodes */ t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ - opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out); + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); /* adapt the switch_block_conn for the GSB nodes */ t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 7cbf219fb0f..c5a0e731a90 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -36,6 +36,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const int& Fs, const e_switch_block_type& sb_subtype, const int& subFs, + const bool& opin2all_sides, const bool& wire_opposite_side); void build_rr_graph_direct_connections(const RRGraphView& rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index fca7d569dfc..cf3293c122c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1271,7 +1271,8 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, const std::vector& segment_inf, - const std::vector>& Fc_out) { + const std::vector>& Fc_out, + const bool& opin2all_sides) { t_pin2track_map opin2track_map; /* Resize the matrix */ opin2track_map.resize(rr_gsb.get_num_sides()); @@ -1321,10 +1322,19 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, VTR_ASSERT(opin_Fc_out.size() == segment_inf.size()); /* Build track2ipin_map for this IPIN */ - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, - /* Give an offset for the first track that this ipin will connect to */ - offset[side_manager.to_size_t()], - segment_inf, opin2track_map); + if (opin2all_sides) { + for (e_side track_side : SIDES) { + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, track_side, inode, opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); + } + } else { + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); + } /* update offset: aim to rotate starting tracks by 1*/ offset[side_manager.to_size_t()] += 1; } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 6c1208ebf46..17fdfe0ffa1 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -66,7 +66,8 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, const std::vector& segment_inf, - const std::vector>& Fc_out); + const std::vector>& Fc_out, + const bool& opin2all_sides); void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, From 1364df8b86dae3e0563384fca6f4b72765f3f694 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 10:50:52 -0800 Subject: [PATCH 187/453] [core] code format --- vpr/src/route/rr_graph.cpp | 2 +- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 2658035bac7..0e74b7765ae 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -723,7 +723,7 @@ void create_rr_graph(const t_graph_type graph_type, &det_routing_arch->wire_to_rr_ipin_switch, det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ - det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ + det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ false, /* Do not allow passing tracks to be wired to the same routing channels */ Warnings); } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index cf3293c122c..f95ee197812 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1330,10 +1330,10 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, segment_inf, opin2track_map); } } else { - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, - /* Give an offset for the first track that this ipin will connect to */ - offset[side_manager.to_size_t()], - segment_inf, opin2track_map); + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); } /* update offset: aim to rotate starting tracks by 1*/ offset[side_manager.to_size_t()] += 1; From 71efc948732b01eaaf2ce22e9f577276792afbfb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 11:46:51 -0800 Subject: [PATCH 188/453] [core] add a new option ``concat_pass_wire`` to tileable rr graph generator --- libs/libarchfpga/src/physical_types.h | 2 ++ libs/libarchfpga/src/read_xml_arch_file.cpp | 2 ++ vpr/src/base/SetupVPR.cpp | 2 ++ vpr/src/base/vpr_types.h | 2 ++ vpr/src/route/rr_graph.cpp | 3 ++- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 3 ++- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h | 1 + vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 3 ++- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 1 + vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 5 +++-- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 1 + 11 files changed, 20 insertions(+), 5 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index e862ca518ad..15b1b82a596 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1966,6 +1966,8 @@ struct t_arch { bool shrink_boundary; bool through_channel; bool opin2all_sides; + bool concat_wire; + bool concat_pass_wire; t_chan_width_dist Chans; enum e_switch_block_type SBType; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 5895e697d19..d54b6967748 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2526,6 +2526,8 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti arch->shrink_boundary = get_attribute(layout_tag, "shrink_boundary", loc_data, ReqOpt::OPTIONAL).as_bool(false); arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false); arch->opin2all_sides = get_attribute(layout_tag, "opin2all_sides", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->concat_wire = get_attribute(layout_tag, "concat_wire", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->concat_pass_wire = get_attribute(layout_tag, "concat_pass_wire", loc_data, ReqOpt::OPTIONAL).as_bool(false); //Count the number of or tags size_t auto_layout_cnt = 0; diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 9917d31568a..cff7179b701 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -413,6 +413,8 @@ static void SetupRoutingArch(const t_arch& Arch, RoutingArch->shrink_boundary = Arch.shrink_boundary; RoutingArch->through_channel = Arch.through_channel; RoutingArch->opin2all_sides = Arch.opin2all_sides; + RoutingArch->concat_wire = Arch.concat_wire; + RoutingArch->concat_pass_wire = Arch.concat_pass_wire; } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 739537ba58e..a7528f8c8fe 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1544,6 +1544,8 @@ struct t_det_routing_arch { bool shrink_boundary; bool through_channel; bool opin2all_sides; + bool concat_wire; + bool concat_pass_wire; short global_route_switch; short delayless_switch; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 0e74b7765ae..c277ec24936 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -724,7 +724,8 @@ void create_rr_graph(const t_graph_type graph_type, det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ - false, /* Do not allow passing tracks to be wired to the same routing channels */ + det_routing_arch->concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ + det_routing_arch->concat_pass_wire, /* Allow passing tracks to be wired to the routing tracks in the same direction in a switch block. It means that a pass wire can jump in the same direction to another */ Warnings); } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 8b17e960ed9..a527c900099 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -87,6 +87,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const bool& shrink_boundary, const bool& through_channel, const bool& opin2all_sides, + const bool& concat_wire, const bool& wire_opposite_side, int* Warnings) { vtr::ScopedStartFinishTimer timer("Build tileable routing resource graph"); @@ -255,7 +256,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ segment_inf, segment_inf_x, segment_inf_y, Fc_in, Fc_out, sb_type, Fs, sb_subtype, subFs, - opin2all_sides, + opin2all_sides, concat_wire, wire_opposite_side); /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h index 52a497a7e15..af188e12af5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -32,6 +32,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const bool& shrink_boundary, const bool& through_channel, const bool& opin2all_sides, + const bool& concat_wire, const bool& wire_opposite_side, int* Warnings); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index d41cb66c9f9..c34cfce3e03 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -117,6 +117,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const e_switch_block_type& sb_subtype, const int& subFs, const bool& opin2all_sides, + const bool& concat_wire, const bool& wire_opposite_side) { size_t num_edges_to_create = 0; /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ @@ -147,7 +148,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* adapt the switch_block_conn for the GSB nodes */ t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, sb_subtype, subFs, wire_opposite_side, + sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, segment_inf); /* Build edges for a GSB */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index c5a0e731a90..1e2dcf46ecd 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -37,6 +37,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const e_switch_block_type& sb_subtype, const int& subFs, const bool& opin2all_sides, + const bool& concat_wire, const bool& wire_opposite_side); void build_rr_graph_direct_connections(const RRGraphView& rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index f95ee197812..e5e6cee45c6 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -346,7 +346,7 @@ static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, continue; } /* Bypass those from_side is opposite to to_side if required */ - if ((true == wire_opposite_side) + if (!wire_opposite_side && (to_side_manager.get_opposite() == from_side)) { continue; } @@ -441,6 +441,7 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const int& Fs, const e_switch_block_type& sb_subtype, const int& subFs, + const bool& concat_wire, const bool& wire_opposite_side, const std::vector& segment_inf) { t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ @@ -513,7 +514,7 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, /* For Group 1: we build connections between end_tracks and start_tracks*/ build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, sb_type, Fs, - true, /* End tracks should always to wired to start tracks */ + concat_wire, /* End tracks should always to wired to start tracks */ end_tracks, start_tracks, track2track_map); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 17fdfe0ffa1..27bc8c0bd00 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -37,6 +37,7 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const int& Fs, const e_switch_block_type& sb_subtype, const int& subFs, + const bool& concat_wire, const bool& wire_opposite_side, const std::vector& segment_inf); From b77ad082b6fcc49642e19e70fc039c92b242a114 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 11:47:45 -0800 Subject: [PATCH 189/453] [core] code format --- vpr/src/route/rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index c277ec24936..2db9a8deb5e 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -724,8 +724,8 @@ void create_rr_graph(const t_graph_type graph_type, det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ - det_routing_arch->concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ - det_routing_arch->concat_pass_wire, /* Allow passing tracks to be wired to the routing tracks in the same direction in a switch block. It means that a pass wire can jump in the same direction to another */ + det_routing_arch->concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ + det_routing_arch->concat_pass_wire, /* Allow passing tracks to be wired to the routing tracks in the same direction in a switch block. It means that a pass wire can jump in the same direction to another */ Warnings); } } From 5d41e33cc89a34d0481550728f855252a63ac704 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 13:57:04 -0800 Subject: [PATCH 190/453] [core] resolve conflicts --- libs/EXTERNAL/libcatch2 | 1 + 1 file changed, 1 insertion(+) create mode 160000 libs/EXTERNAL/libcatch2 diff --git a/libs/EXTERNAL/libcatch2 b/libs/EXTERNAL/libcatch2 new file mode 160000 index 00000000000..01cac90c629 --- /dev/null +++ b/libs/EXTERNAL/libcatch2 @@ -0,0 +1 @@ +Subproject commit 01cac90c6298f8d5cda34eebda24412f644142f8 From 229e43e30bd7a99bf34239179ad957ca6e00f8da Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 14:20:44 -0800 Subject: [PATCH 191/453] [core] fixed a bug --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index e5e6cee45c6..b63605a5b73 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1324,8 +1324,9 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, /* Build track2ipin_map for this IPIN */ if (opin2all_sides) { - for (e_side track_side : SIDES) { - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, track_side, inode, opin_Fc_out, + for (size_t track_side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager track_side_mgr(track_side); + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, track_side_mgr.get_side(), inode, opin_Fc_out, /* Give an offset for the first track that this ipin will connect to */ offset[side_manager.to_size_t()], segment_inf, opin2track_map); From c19af24e9319e147e75da4da91018a6662ec8e9d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 14:45:04 -0800 Subject: [PATCH 192/453] [core] fixing the bug --- .../tileable_rr_graph_gsb.cpp | 395 +++++++++++++++++- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 2 +- 2 files changed, 389 insertions(+), 8 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index b63605a5b73..5b97cfb8d21 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -938,11 +938,16 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); - /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ - /* add edges to the opin_node */ - for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) { - rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node], false); - edge_count++; + for (size_t to_side = 0; to_side < rr_gsb.get_num_sides(); ++to_side) { + SideManager to_side_mgr(to_side); + enum e_side gsb_to_side = to_side_mgr.get_side(); + + /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ + /* add edges to the opin_node */ + for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][gsb_to_side]) { + rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node], false); + edge_count++; + } } } @@ -1082,15 +1087,17 @@ static void build_gsb_one_opin_pin2track_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const enum e_side& opin_side, const size_t& opin_node_id, + const enum e_side& chan_side, + const size_t& opin_node_id, const std::vector& Fc, const size_t& offset, const std::vector& segment_inf, t_pin2track_map& opin2track_map) { /* Get a list of segment_ids*/ std::vector seg_list = rr_gsb.get_chan_segment_ids(opin_side); - enum e_side chan_side = opin_side; size_t chan_width = rr_gsb.get_chan_width(chan_side); SideManager opin_side_manager(opin_side); + SideManager chan_side_manager(chan_side); for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { /* Get a list of node that have the segment id */ @@ -1144,7 +1151,7 @@ static void build_gsb_one_opin_pin2track_map(const RRGraphView& rr_graph, size_t actual_itrack = itrack % actual_track_list.size(); size_t track_index = actual_track_list[actual_itrack]; const RRNodeId& track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index); - opin2track_map[opin_side_index][opin_node_id].push_back(track_rr_node_index); + opin2track_map[opin_side_index][opin_node_id][chan_side_manager.to_size_t()].push_back(track_rr_node_index); /* update track counter */ track_cnt++; /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. @@ -1364,6 +1371,380 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, t_physical_tile_type_ptr grid_type = grids.get_physical_type(t_physical_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer)); + /* Iterate through all direct connections */ + for (size_t i = 0; i < directs.size(); ++i) { + /* Bypass unmatched direct clb-to-clb connections */ + if (grid_type != clb_to_clb_directs[i].from_clb_type) { + continue; + } + + /* This opin is specified to connect directly to an ipin, + * now compute which ipin to connect to + */ + vtr::Point to_grid_coordinate(from_grid_coordinate.x() + directs[i].x_offset, + from_grid_coordinate.y() + directs[i].y_offset); + + /* Bypass unmatched direct clb-to-clb connections */ + t_physical_tile_type_ptr to_grid_type = grids.get_physical_type(t_physical_tile_loc(to_grid_coordinate.x(), to_grid_coordinate.y(), layer)); + /* Check if to_grid if the same grid */ + if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { + continue; + } + + bool swap; + int max_index, min_index; + /* Compute index of opin with regards to given pins */ + if (clb_to_clb_directs[i].from_clb_pin_start_index + > clb_to_clb_directs[i].from_clb_pin_end_index) { + swap = true; + max_index = clb_to_clb_directs[i].from_clb_pin_start_index; + min_index = clb_to_clb_directs[i].from_clb_pin_end_index; + } else { + swap = false; + min_index = clb_to_clb_directs[i].from_clb_pin_start_index; + max_index = clb_to_clb_directs[i].from_clb_pin_end_index; + } + + /* get every opin in the range */ + for (int opin = min_index; opin <= max_index; ++opin) { + int offset = opin - min_index; + + if ((to_grid_coordinate.x() < grids.width() - 1) + && (to_grid_coordinate.y() < grids.height() - 1)) { + int ipin = OPEN; + if (clb_to_clb_directs[i].to_clb_pin_start_index + > clb_to_clb_directs[i].to_clb_pin_end_index) { + if (true == swap) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; + } + } else { + if (true == swap) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; + } + } + + /* Get the pin index in the rr_graph */ + t_physical_tile_loc from_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer); + int from_grid_width_ofs = grids.get_width_offset(from_tile_loc); + int from_grid_height_ofs = grids.get_height_offset(from_tile_loc); + t_physical_tile_loc to_tile_loc(to_grid_coordinate.x(), to_grid_coordinate.y(), layer); + int to_grid_width_ofs = grids.get_width_offset(to_tile_loc); + int to_grid_height_ofs = grids.get_height_offset(to_tile_loc); + + /* Find the side of grid pins, the pin location should be unique! + * Pin location is required by searching a node in rr_graph + */ + std::vector opin_grid_side = find_grid_pin_sides(grids, layer, from_grid_coordinate.x(), from_grid_coordinate.y(), opin); + VTR_ASSERT(1 == opin_grid_side.size()); + + std::vector ipin_grid_side = find_grid_pin_sides(grids, layer, to_grid_coordinate.x(), to_grid_coordinate.y(), ipin); + VTR_ASSERT(1 == ipin_grid_side.size()); + + RRNodeId opin_node_id = rr_graph.node_lookup().find_node(layer, + from_grid_coordinate.x() - from_grid_width_ofs, + from_grid_coordinate.y() - from_grid_height_ofs, + OPIN, opin, opin_grid_side[0]); + RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(layer, + to_grid_coordinate.x() - to_grid_width_ofs, + to_grid_coordinate.y() - to_grid_height_ofs, + IPIN, ipin, ipin_grid_side[0]); + + /* add edges to the opin_node */ + VTR_ASSERT(opin_node_id && ipin_node_id); + rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch, false); + } + } + } + /* Build actual edges */ + rr_graph_builder.build_edges(true); +} + const std::vector& Fc, + const size_t& offset, + const std::vector& segment_inf, + t_pin2track_map& opin2track_map) { + /* Get a list of segment_ids*/ + std::vector seg_list = rr_gsb.get_chan_segment_ids(opin_side); + enum e_side chan_side = opin_side; + size_t chan_width = rr_gsb.get_chan_width(chan_side); + SideManager opin_side_manager(opin_side); + + for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { + /* Get a list of node that have the segment id */ + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); + /* Refine the track_list: keep those will have connection blocks in the GSB */ + std::vector actual_track_list; + for (size_t inode = 0; inode < track_list.size(); ++inode) { + /* Check if tracks allow connection blocks in the GSB*/ + if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) { + continue; /* Bypass condition */ + } + if (TRACK_START != determine_track_status_of_gsb(rr_graph, rr_gsb, chan_side, track_list[inode])) { + continue; /* Bypass condition */ + } + /* Push the node to actual_track_list */ + actual_track_list.push_back(track_list[inode]); + } + + /* Go the next segment if offset is zero or actual_track_list is empty */ + if (0 == actual_track_list.size()) { + continue; + } + + /* Scale Fc */ + int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); + /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ + actual_Fc = std::max(1, actual_Fc); + /* Compute the step between two connection from this IPIN to tracks: + * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + */ + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); + /* Track step mush be a multiple of 2!!!*/ + /* Make sure step should be at least 1 */ + track_step = std::max(1, (int)track_step); + /* Adapt offset to the range of actual_track_list */ + size_t actual_offset = offset % actual_track_list.size(); + + /* No need to rotate if offset is zero */ + if (0 < actual_offset) { + /* rotate the track list by an offset */ + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } + + /* Assign tracks */ + int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ + for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { + /* Update pin2track map */ + size_t opin_side_index = opin_side_manager.to_size_t(); + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + size_t track_index = actual_track_list[actual_itrack]; + const RRNodeId& track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index); + opin2track_map[opin_side_index][opin_node_id].push_back(track_rr_node_index); + /* update track counter */ + track_cnt++; + /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. + * So I comment it. And we just make sure its track_cnt >= actual_Fc + * if (actual_Fc == track_cnt) { + * break; + * } + */ + } + + /* Ensure the number of tracks is similar to Fc */ + /* Give a warning if Fc is < track_cnt */ + /* + * if (actual_Fc != track_cnt) { + * vpr_printf(TIO_MESSAGE_INFO, + * "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + * opin_node_id, track_cnt, actual_Fc); + * } + */ + } +} + +/************************************************************************ + * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] + * based on the existing routing resources in the General Switch Block (GSB) + * This function supports both X-directional and Y-directional tracks + * The mapping is done in the following steps: + * 1. Build ipin_to_track_map[gsb_side][0..num_ipin_nodes-1][track_indices] + * For each IPIN, we ensure at least one connection to the tracks. + * Then, we assign IPINs to tracks evenly while satisfying the actual_Fc + * 2. Convert the ipin_to_track_map to track_to_ipin_map + ***********************************************************************/ +t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_in) { + t_track2pin_map track2ipin_map; + /* Resize the matrix */ + track2ipin_map.resize(rr_gsb.get_num_sides()); + + /* offset counter: it aims to balance the track-to-IPIN for each connection block */ + size_t offset_size = 0; + std::vector offset; + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side ipin_side = side_manager.get_side(); + /* Get the chan_side */ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + /* resize offset to the maximum chan_side*/ + offset_size = std::max(offset_size, chan_side_manager.to_size_t() + 1); + } + /* Initial offset */ + offset.resize(offset_size); + offset.assign(offset.size(), 0); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side ipin_side = side_manager.get_side(); + /* Get the chan_side */ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ + /* Get channel width and resize the matrix */ + size_t chan_width = rr_gsb.get_chan_width(chan_side); + track2ipin_map[chan_side_manager.to_size_t()].resize(chan_width); + /* Find the ipin/opin nodes */ + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { + const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); + t_physical_tile_loc ipin_node_phy_tile_loc(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node), 0); + /* Skip EMPTY type */ + if (true == is_empty_type(grids.get_physical_type(ipin_node_phy_tile_loc))) { + continue; + } + + int grid_type_index = grids.get_physical_type(ipin_node_phy_tile_loc)->index; + /* Get Fc of the ipin */ + /* skip Fc = 0 or unintialized, those pins are in the */ + bool skip_conn2track = true; + std::vector ipin_Fc_out; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)][iseg]; + ipin_Fc_out.push_back(ipin_Fc); + if (0 != ipin_Fc) { + skip_conn2track = false; + continue; + } + } + + if (true == skip_conn2track) { + continue; + } + + //VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size()); + + /* Build track2ipin_map for this IPIN */ + build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[chan_side_manager.to_size_t()], + segment_inf, track2ipin_map); + /* update offset */ + offset[chan_side_manager.to_size_t()] += 2; + //printf("offset[%lu]=%lu\n", chan_side_manager.to_size_t(), offset[chan_side_manager.to_size_t()]); + } + } + + return track2ipin_map; +} + +/************************************************************************ + * Build the opin_to_track_map[gsb_side][0..num_opin_nodes-1][track_indices] + * based on the existing routing resources in the General Switch Block (GSB) + * This function supports both X-directional and Y-directional tracks + * The mapping is done in the following steps: + * 1. Build a list of routing tracks whose starting points locate at this GSB + * (xlow - gsb_x == 0) + * 2. Divide the routing tracks by segment types, so that we can balance + * the connections between OPINs and different types of routing tracks. + * 3. Scale the Fc of each pin to the actual number of routing tracks + * actual_Fc = (int) Fc * num_tracks / chan_width + ***********************************************************************/ +t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_out, + const bool& opin2all_sides) { + t_pin2track_map opin2track_map; + /* Resize the matrix */ + opin2track_map.resize(rr_gsb.get_num_sides()); + + /* offset counter: it aims to balance the OPIN-to-track for each switch block */ + std::vector offset; + /* Get the chan_side: which is the same as the opin side */ + offset.resize(rr_gsb.get_num_sides()); + /* Initial offset */ + offset.assign(offset.size(), 0); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side opin_side = side_manager.get_side(); + /* Get the chan_side */ + /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ + /* Get channel width and resize the matrix */ + size_t num_opin_nodes = rr_gsb.get_num_opin_nodes(opin_side); + opin2track_map[side].resize(num_opin_nodes); + /* Find the ipin/opin nodes */ + for (size_t inode = 0; inode < num_opin_nodes; ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode); + t_physical_tile_loc opin_node_phy_tile_loc(rr_graph.node_xlow(opin_node), rr_graph.node_ylow(opin_node), 0); + /* Skip EMPTY type */ + if (true == is_empty_type(grids.get_physical_type(opin_node_phy_tile_loc))) { + continue; + } + int grid_type_index = grids.get_physical_type(opin_node_phy_tile_loc)->index; + + /* Get Fc of the ipin */ + /* skip Fc = 0 or unintialized, those pins are in the */ + bool skip_conn2track = true; + std::vector opin_Fc_out; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)][iseg]; + opin_Fc_out.push_back(opin_Fc); + if (0 != opin_Fc) { + skip_conn2track = false; + continue; + } + } + + if (true == skip_conn2track) { + continue; + } + VTR_ASSERT(opin_Fc_out.size() == segment_inf.size()); + + /* Build track2ipin_map for this IPIN */ + opin2track_map[side][inode].resize(rr_gsb.get_num_sides()); + if (opin2all_sides) { + for (size_t track_side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager track_side_mgr(track_side); + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, track_side_mgr.get_side(), opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); + } + } else { + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_side, opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); + } + /* update offset: aim to rotate starting tracks by 1*/ + offset[side_manager.to_size_t()] += 1; + } + + /* Check: + * 1. We want to ensure that each OPIN will drive at least one track + * 2. We want to ensure that each track will be driven by at least 1 OPIN */ + } + + return opin2track_map; +} + +/************************************************************************ + * Add all direct clb-pin-to-clb-pin edges to given opin + ***********************************************************************/ +void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& from_grid_coordinate, + const RRSwitchId& delayless_switch, + const std::vector& directs, + const std::vector& clb_to_clb_directs) { + VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); + + t_physical_tile_type_ptr grid_type = grids.get_physical_type(t_physical_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer)); + /* Iterate through all direct connections */ for (size_t i = 0; i < directs.size(); ++i) { /* Bypass unmatched direct clb-to-clb connections */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 27bc8c0bd00..87bdc7893e6 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -26,7 +26,7 @@ ***********************************************************************/ typedef std::vector>> t_track2track_map; typedef std::vector>> t_track2pin_map; -typedef std::vector>> t_pin2track_map; +typedef std::vector>>> t_pin2track_map; /************************************************************************ * Functions From 45883aab3e89b63086cd3960ec944e95aa5108a6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 14:58:10 -0800 Subject: [PATCH 193/453] [core] syntax --- .../tileable_rr_graph_gsb.cpp | 374 ------------------ 1 file changed, 374 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 5b97cfb8d21..93575338c60 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1371,380 +1371,6 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, t_physical_tile_type_ptr grid_type = grids.get_physical_type(t_physical_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer)); - /* Iterate through all direct connections */ - for (size_t i = 0; i < directs.size(); ++i) { - /* Bypass unmatched direct clb-to-clb connections */ - if (grid_type != clb_to_clb_directs[i].from_clb_type) { - continue; - } - - /* This opin is specified to connect directly to an ipin, - * now compute which ipin to connect to - */ - vtr::Point to_grid_coordinate(from_grid_coordinate.x() + directs[i].x_offset, - from_grid_coordinate.y() + directs[i].y_offset); - - /* Bypass unmatched direct clb-to-clb connections */ - t_physical_tile_type_ptr to_grid_type = grids.get_physical_type(t_physical_tile_loc(to_grid_coordinate.x(), to_grid_coordinate.y(), layer)); - /* Check if to_grid if the same grid */ - if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { - continue; - } - - bool swap; - int max_index, min_index; - /* Compute index of opin with regards to given pins */ - if (clb_to_clb_directs[i].from_clb_pin_start_index - > clb_to_clb_directs[i].from_clb_pin_end_index) { - swap = true; - max_index = clb_to_clb_directs[i].from_clb_pin_start_index; - min_index = clb_to_clb_directs[i].from_clb_pin_end_index; - } else { - swap = false; - min_index = clb_to_clb_directs[i].from_clb_pin_start_index; - max_index = clb_to_clb_directs[i].from_clb_pin_end_index; - } - - /* get every opin in the range */ - for (int opin = min_index; opin <= max_index; ++opin) { - int offset = opin - min_index; - - if ((to_grid_coordinate.x() < grids.width() - 1) - && (to_grid_coordinate.y() < grids.height() - 1)) { - int ipin = OPEN; - if (clb_to_clb_directs[i].to_clb_pin_start_index - > clb_to_clb_directs[i].to_clb_pin_end_index) { - if (true == swap) { - ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; - } else { - ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; - } - } else { - if (true == swap) { - ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; - } else { - ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; - } - } - - /* Get the pin index in the rr_graph */ - t_physical_tile_loc from_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer); - int from_grid_width_ofs = grids.get_width_offset(from_tile_loc); - int from_grid_height_ofs = grids.get_height_offset(from_tile_loc); - t_physical_tile_loc to_tile_loc(to_grid_coordinate.x(), to_grid_coordinate.y(), layer); - int to_grid_width_ofs = grids.get_width_offset(to_tile_loc); - int to_grid_height_ofs = grids.get_height_offset(to_tile_loc); - - /* Find the side of grid pins, the pin location should be unique! - * Pin location is required by searching a node in rr_graph - */ - std::vector opin_grid_side = find_grid_pin_sides(grids, layer, from_grid_coordinate.x(), from_grid_coordinate.y(), opin); - VTR_ASSERT(1 == opin_grid_side.size()); - - std::vector ipin_grid_side = find_grid_pin_sides(grids, layer, to_grid_coordinate.x(), to_grid_coordinate.y(), ipin); - VTR_ASSERT(1 == ipin_grid_side.size()); - - RRNodeId opin_node_id = rr_graph.node_lookup().find_node(layer, - from_grid_coordinate.x() - from_grid_width_ofs, - from_grid_coordinate.y() - from_grid_height_ofs, - OPIN, opin, opin_grid_side[0]); - RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(layer, - to_grid_coordinate.x() - to_grid_width_ofs, - to_grid_coordinate.y() - to_grid_height_ofs, - IPIN, ipin, ipin_grid_side[0]); - - /* add edges to the opin_node */ - VTR_ASSERT(opin_node_id && ipin_node_id); - rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch, false); - } - } - } - /* Build actual edges */ - rr_graph_builder.build_edges(true); -} - const std::vector& Fc, - const size_t& offset, - const std::vector& segment_inf, - t_pin2track_map& opin2track_map) { - /* Get a list of segment_ids*/ - std::vector seg_list = rr_gsb.get_chan_segment_ids(opin_side); - enum e_side chan_side = opin_side; - size_t chan_width = rr_gsb.get_chan_width(chan_side); - SideManager opin_side_manager(opin_side); - - for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { - /* Get a list of node that have the segment id */ - std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); - /* Refine the track_list: keep those will have connection blocks in the GSB */ - std::vector actual_track_list; - for (size_t inode = 0; inode < track_list.size(); ++inode) { - /* Check if tracks allow connection blocks in the GSB*/ - if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) { - continue; /* Bypass condition */ - } - if (TRACK_START != determine_track_status_of_gsb(rr_graph, rr_gsb, chan_side, track_list[inode])) { - continue; /* Bypass condition */ - } - /* Push the node to actual_track_list */ - actual_track_list.push_back(track_list[inode]); - } - - /* Go the next segment if offset is zero or actual_track_list is empty */ - if (0 == actual_track_list.size()) { - continue; - } - - /* Scale Fc */ - int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); - /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ - actual_Fc = std::max(1, actual_Fc); - /* Compute the step between two connection from this IPIN to tracks: - * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in - */ - size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); - /* Track step mush be a multiple of 2!!!*/ - /* Make sure step should be at least 1 */ - track_step = std::max(1, (int)track_step); - /* Adapt offset to the range of actual_track_list */ - size_t actual_offset = offset % actual_track_list.size(); - - /* No need to rotate if offset is zero */ - if (0 < actual_offset) { - /* rotate the track list by an offset */ - std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); - } - - /* Assign tracks */ - int track_cnt = 0; - /* Keep assigning until we meet the Fc requirement */ - for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { - /* Update pin2track map */ - size_t opin_side_index = opin_side_manager.to_size_t(); - /* itrack may exceed the size of actual_track_list, adapt it */ - size_t actual_itrack = itrack % actual_track_list.size(); - size_t track_index = actual_track_list[actual_itrack]; - const RRNodeId& track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index); - opin2track_map[opin_side_index][opin_node_id].push_back(track_rr_node_index); - /* update track counter */ - track_cnt++; - /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. - * So I comment it. And we just make sure its track_cnt >= actual_Fc - * if (actual_Fc == track_cnt) { - * break; - * } - */ - } - - /* Ensure the number of tracks is similar to Fc */ - /* Give a warning if Fc is < track_cnt */ - /* - * if (actual_Fc != track_cnt) { - * vpr_printf(TIO_MESSAGE_INFO, - * "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", - * opin_node_id, track_cnt, actual_Fc); - * } - */ - } -} - -/************************************************************************ - * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] - * based on the existing routing resources in the General Switch Block (GSB) - * This function supports both X-directional and Y-directional tracks - * The mapping is done in the following steps: - * 1. Build ipin_to_track_map[gsb_side][0..num_ipin_nodes-1][track_indices] - * For each IPIN, we ensure at least one connection to the tracks. - * Then, we assign IPINs to tracks evenly while satisfying the actual_Fc - * 2. Convert the ipin_to_track_map to track_to_ipin_map - ***********************************************************************/ -t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, - const RRGSB& rr_gsb, - const DeviceGrid& grids, - const std::vector& segment_inf, - const std::vector>& Fc_in) { - t_track2pin_map track2ipin_map; - /* Resize the matrix */ - track2ipin_map.resize(rr_gsb.get_num_sides()); - - /* offset counter: it aims to balance the track-to-IPIN for each connection block */ - size_t offset_size = 0; - std::vector offset; - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - enum e_side ipin_side = side_manager.get_side(); - /* Get the chan_side */ - enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); - SideManager chan_side_manager(chan_side); - /* resize offset to the maximum chan_side*/ - offset_size = std::max(offset_size, chan_side_manager.to_size_t() + 1); - } - /* Initial offset */ - offset.resize(offset_size); - offset.assign(offset.size(), 0); - - /* Walk through each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - enum e_side ipin_side = side_manager.get_side(); - /* Get the chan_side */ - enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); - SideManager chan_side_manager(chan_side); - /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ - /* Get channel width and resize the matrix */ - size_t chan_width = rr_gsb.get_chan_width(chan_side); - track2ipin_map[chan_side_manager.to_size_t()].resize(chan_width); - /* Find the ipin/opin nodes */ - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { - const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); - t_physical_tile_loc ipin_node_phy_tile_loc(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node), 0); - /* Skip EMPTY type */ - if (true == is_empty_type(grids.get_physical_type(ipin_node_phy_tile_loc))) { - continue; - } - - int grid_type_index = grids.get_physical_type(ipin_node_phy_tile_loc)->index; - /* Get Fc of the ipin */ - /* skip Fc = 0 or unintialized, those pins are in the */ - bool skip_conn2track = true; - std::vector ipin_Fc_out; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)][iseg]; - ipin_Fc_out.push_back(ipin_Fc); - if (0 != ipin_Fc) { - skip_conn2track = false; - continue; - } - } - - if (true == skip_conn2track) { - continue; - } - - //VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size()); - - /* Build track2ipin_map for this IPIN */ - build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc_out, - /* Give an offset for the first track that this ipin will connect to */ - offset[chan_side_manager.to_size_t()], - segment_inf, track2ipin_map); - /* update offset */ - offset[chan_side_manager.to_size_t()] += 2; - //printf("offset[%lu]=%lu\n", chan_side_manager.to_size_t(), offset[chan_side_manager.to_size_t()]); - } - } - - return track2ipin_map; -} - -/************************************************************************ - * Build the opin_to_track_map[gsb_side][0..num_opin_nodes-1][track_indices] - * based on the existing routing resources in the General Switch Block (GSB) - * This function supports both X-directional and Y-directional tracks - * The mapping is done in the following steps: - * 1. Build a list of routing tracks whose starting points locate at this GSB - * (xlow - gsb_x == 0) - * 2. Divide the routing tracks by segment types, so that we can balance - * the connections between OPINs and different types of routing tracks. - * 3. Scale the Fc of each pin to the actual number of routing tracks - * actual_Fc = (int) Fc * num_tracks / chan_width - ***********************************************************************/ -t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, - const RRGSB& rr_gsb, - const DeviceGrid& grids, - const std::vector& segment_inf, - const std::vector>& Fc_out, - const bool& opin2all_sides) { - t_pin2track_map opin2track_map; - /* Resize the matrix */ - opin2track_map.resize(rr_gsb.get_num_sides()); - - /* offset counter: it aims to balance the OPIN-to-track for each switch block */ - std::vector offset; - /* Get the chan_side: which is the same as the opin side */ - offset.resize(rr_gsb.get_num_sides()); - /* Initial offset */ - offset.assign(offset.size(), 0); - - /* Walk through each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager side_manager(side); - enum e_side opin_side = side_manager.get_side(); - /* Get the chan_side */ - /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ - /* Get channel width and resize the matrix */ - size_t num_opin_nodes = rr_gsb.get_num_opin_nodes(opin_side); - opin2track_map[side].resize(num_opin_nodes); - /* Find the ipin/opin nodes */ - for (size_t inode = 0; inode < num_opin_nodes; ++inode) { - const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode); - t_physical_tile_loc opin_node_phy_tile_loc(rr_graph.node_xlow(opin_node), rr_graph.node_ylow(opin_node), 0); - /* Skip EMPTY type */ - if (true == is_empty_type(grids.get_physical_type(opin_node_phy_tile_loc))) { - continue; - } - int grid_type_index = grids.get_physical_type(opin_node_phy_tile_loc)->index; - - /* Get Fc of the ipin */ - /* skip Fc = 0 or unintialized, those pins are in the */ - bool skip_conn2track = true; - std::vector opin_Fc_out; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)][iseg]; - opin_Fc_out.push_back(opin_Fc); - if (0 != opin_Fc) { - skip_conn2track = false; - continue; - } - } - - if (true == skip_conn2track) { - continue; - } - VTR_ASSERT(opin_Fc_out.size() == segment_inf.size()); - - /* Build track2ipin_map for this IPIN */ - opin2track_map[side][inode].resize(rr_gsb.get_num_sides()); - if (opin2all_sides) { - for (size_t track_side = 0; side < rr_gsb.get_num_sides(); ++side) { - SideManager track_side_mgr(track_side); - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, track_side_mgr.get_side(), opin_Fc_out, - /* Give an offset for the first track that this ipin will connect to */ - offset[side_manager.to_size_t()], - segment_inf, opin2track_map); - } - } else { - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_side, opin_Fc_out, - /* Give an offset for the first track that this ipin will connect to */ - offset[side_manager.to_size_t()], - segment_inf, opin2track_map); - } - /* update offset: aim to rotate starting tracks by 1*/ - offset[side_manager.to_size_t()] += 1; - } - - /* Check: - * 1. We want to ensure that each OPIN will drive at least one track - * 2. We want to ensure that each track will be driven by at least 1 OPIN */ - } - - return opin2track_map; -} - -/************************************************************************ - * Add all direct clb-pin-to-clb-pin edges to given opin - ***********************************************************************/ -void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grids, - const size_t& layer, - const vtr::Point& from_grid_coordinate, - const RRSwitchId& delayless_switch, - const std::vector& directs, - const std::vector& clb_to_clb_directs) { - VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); - - t_physical_tile_type_ptr grid_type = grids.get_physical_type(t_physical_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer)); - /* Iterate through all direct connections */ for (size_t i = 0; i < directs.size(); ++i) { /* Bypass unmatched direct clb-to-clb connections */ From a668e393859ecbc85a113d54800f0ffd2272bbca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:01:28 -0800 Subject: [PATCH 194/453] [core] syntax --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 93575338c60..db07cc7238a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1088,7 +1088,6 @@ static void build_gsb_one_opin_pin2track_map(const RRGraphView& rr_graph, const enum e_side& opin_side, const size_t& opin_node_id, const enum e_side& chan_side, - const size_t& opin_node_id, const std::vector& Fc, const size_t& offset, const std::vector& segment_inf, @@ -1333,13 +1332,13 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, if (opin2all_sides) { for (size_t track_side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager track_side_mgr(track_side); - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, track_side_mgr.get_side(), inode, opin_Fc_out, + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, track_side_mgr.get_side(), opin_Fc_out, /* Give an offset for the first track that this ipin will connect to */ offset[side_manager.to_size_t()], segment_inf, opin2track_map); } } else { - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_side, opin_Fc_out, /* Give an offset for the first track that this ipin will connect to */ offset[side_manager.to_size_t()], segment_inf, opin2track_map); From 320ab25a5a8f8f7559f27cb87f8feafa8dca0903 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:11:06 -0800 Subject: [PATCH 195/453] [core] syntaxc --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index db07cc7238a..689dc1dafa5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1329,6 +1329,7 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, VTR_ASSERT(opin_Fc_out.size() == segment_inf.size()); /* Build track2ipin_map for this IPIN */ + opin2track_map[side][inode].resize(rr_gsb.get_num_sides()); if (opin2all_sides) { for (size_t track_side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager track_side_mgr(track_side); From 7b5d47bd1ddbb3843c6638f89f2faa531bd31dad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:31:10 -0800 Subject: [PATCH 196/453] [core] fixed a bug --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 689dc1dafa5..88797c7d042 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1331,7 +1331,7 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, /* Build track2ipin_map for this IPIN */ opin2track_map[side][inode].resize(rr_gsb.get_num_sides()); if (opin2all_sides) { - for (size_t track_side = 0; side < rr_gsb.get_num_sides(); ++side) { + for (size_t track_side = 0; track_side < rr_gsb.get_num_sides(); ++track_side) { SideManager track_side_mgr(track_side); build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, track_side_mgr.get_side(), opin_Fc_out, /* Give an offset for the first track that this ipin will connect to */ From d65c0546ac34f53f0713d841004a003aa1131e9f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:34:00 -0800 Subject: [PATCH 197/453] [core] fixed a bug --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 88797c7d042..05a5990ee4d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -940,11 +940,10 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, for (size_t to_side = 0; to_side < rr_gsb.get_num_sides(); ++to_side) { SideManager to_side_mgr(to_side); - enum e_side gsb_to_side = to_side_mgr.get_side(); /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ /* add edges to the opin_node */ - for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][gsb_to_side]) { + for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][to_side_mgr.to_size_t()]) { rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node], false); edge_count++; } From 2818f1b0c64d206826d57a6b32d234a81d0c6fdd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:37:18 -0800 Subject: [PATCH 198/453] [core] fixed a bug --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 05a5990ee4d..98bfedaf2eb 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -938,12 +938,10 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); - for (size_t to_side = 0; to_side < rr_gsb.get_num_sides(); ++to_side) { - SideManager to_side_mgr(to_side); - + for (size_t to_side = 0; to_side < opin2track_map[gsb_side][inode]; ++to_side) { /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ /* add edges to the opin_node */ - for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][to_side_mgr.to_size_t()]) { + for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][to_side]) { rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node], false); edge_count++; } From eb9722851bd3de03df7fb9ace5bdfb9cb078ca83 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:38:24 -0800 Subject: [PATCH 199/453] [core] debug --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 98bfedaf2eb..66c193a8e74 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -938,7 +938,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); - for (size_t to_side = 0; to_side < opin2track_map[gsb_side][inode]; ++to_side) { + for (size_t to_side = 0; to_side < opin2track_map[gsb_side][inode].size(); ++to_side) { /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ /* add edges to the opin_node */ for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][to_side]) { From 84870b3c8ae22e15dcc3b9dc801d51c3d773f52f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Apr 2024 16:06:51 -0700 Subject: [PATCH 200/453] [vpr] add missing support on tileable routing --- vpr/src/route/route.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index dbf07569250..767418cb936 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -42,6 +42,10 @@ bool route(const Netlist<>& net_list, graph_directionality = GRAPH_BIDIR; } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); } From 32409963fedd69fd63e60cd4d8f7933b4f033bfa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 10:36:33 -0700 Subject: [PATCH 201/453] [vpr] now use the switch index from direct defintion --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 2 +- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 2 -- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 1 - vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 3 +-- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 1 - 5 files changed, 2 insertions(+), 7 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index a527c900099..2632fd94a2f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -275,7 +275,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ clb2clb_directs.push_back(clb_to_clb_directs[idirect]); } - build_rr_graph_direct_connections(device_ctx.rr_graph, device_ctx.rr_graph_builder, device_ctx.grid, 0, delayless_rr_switch, + build_rr_graph_direct_connections(device_ctx.rr_graph, device_ctx.rr_graph_builder, device_ctx.grid, 0, arch_directs, clb2clb_directs); /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index c34cfce3e03..93612de2fcc 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -168,7 +168,6 @@ void build_rr_graph_direct_connections(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const size_t& layer, - const RRSwitchId& delayless_switch, const std::vector& directs, const std::vector& clb_to_clb_directs) { for (size_t ix = 0; ix < grids.width(); ++ix) { @@ -188,7 +187,6 @@ void build_rr_graph_direct_connections(const RRGraphView& rr_graph, rr_graph_builder, grids, layer, from_grid_coordinate, - delayless_switch, directs, clb_to_clb_directs); } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 1e2dcf46ecd..06b3a1f3f64 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -44,7 +44,6 @@ void build_rr_graph_direct_connections(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const size_t& layer, - const RRSwitchId& delayless_switch, const std::vector& directs, const std::vector& clb_to_clb_directs); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 66c193a8e74..c84e6ad6e1a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1361,7 +1361,6 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, const DeviceGrid& grids, const size_t& layer, const vtr::Point& from_grid_coordinate, - const RRSwitchId& delayless_switch, const std::vector& directs, const std::vector& clb_to_clb_directs) { VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); @@ -1452,7 +1451,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, /* add edges to the opin_node */ VTR_ASSERT(opin_node_id && ipin_node_id); - rr_graph_builder.create_edge(opin_node_id, ipin_node_id, delayless_switch, false); + rr_graph_builder.create_edge(opin_node_id, ipin_node_id, clb_to_clb_directs[i].switch_index, false); } } } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 87bdc7893e6..4d3bbfdcc67 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -75,7 +75,6 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, const DeviceGrid& grids, const size_t& layer, const vtr::Point& from_grid_coordinate, - const RRSwitchId& delayless_switch, const std::vector& directs, const std::vector& clb_to_clb_directs); From 5d428ecc8f86e29fe6b8f0fec3eba9ef8c839d1a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 10:42:03 -0700 Subject: [PATCH 202/453] [test] remove out-of-date koios entry --- vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 127a8207371..eb8a900c155 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -1,4 +1,3 @@ -regression_tests/vtr_reg_strong/koios regression_tests/vtr_reg_strong/strong_absorb_buffers regression_tests/vtr_reg_strong/strong_analysis_only regression_tests/vtr_reg_strong/strong_analytic_placer From 83ac18fede076907ed4cc00bffec86131596ff32 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 11:58:21 -0700 Subject: [PATCH 203/453] [vpr] syntax and sanity checks --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 2 ++ vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 2632fd94a2f..e22ac4d63a8 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -272,6 +272,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ std::vector clb2clb_directs; for (int idirect = 0; idirect < num_directs; ++idirect) { arch_directs.push_back(directs[idirect]); + /* Sanity checks on rr switch id */ + VTR_ASSERT(true == device_ctx.rr_graph.valid_switch(RRSwitchId(clb_to_clb_directs[idirect].switch_index))); clb2clb_directs.push_back(clb_to_clb_directs[idirect]); } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index c84e6ad6e1a..79f4166e190 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1451,7 +1451,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, /* add edges to the opin_node */ VTR_ASSERT(opin_node_id && ipin_node_id); - rr_graph_builder.create_edge(opin_node_id, ipin_node_id, clb_to_clb_directs[i].switch_index, false); + rr_graph_builder.create_edge(opin_node_id, ipin_node_id, RRSwitchId(clb_to_clb_directs[i].switch_index), false); } } } From 5fc437b9b793db6d9c8ee8a5ee4ced14e57ef3cb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 15:31:43 -0700 Subject: [PATCH 204/453] [lib] support multiple ptc number for rr graph I/O --- libs/librrgraph/src/base/rr_graph_builder.cpp | 25 +++ libs/librrgraph/src/base/rr_graph_builder.h | 6 + libs/librrgraph/src/io/rr_graph.xsd | 2 +- .../src/io/rr_graph_uxsdcxx_serializer.h | 12 +- libs/librrgraph/src/utils/vtr_tokenizer.cpp | 167 ++++++++++++++++++ libs/librrgraph/src/utils/vtr_tokenizer.h | 70 ++++++++ 6 files changed, 276 insertions(+), 6 deletions(-) create mode 100644 libs/librrgraph/src/utils/vtr_tokenizer.cpp create mode 100644 libs/librrgraph/src/utils/vtr_tokenizer.h diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 44528e9d535..e7228b8910e 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -2,6 +2,7 @@ #include "vtr_log.h" #include "rr_graph_builder.h" #include "vtr_time.h" +#include "vtr_tokenizer.h" #include #include //#include @@ -237,6 +238,30 @@ std::vector RRGraphBuilder::node_in_edges(RRNodeId node) const { return node_in_edges_[node]; } +void RRGraphBuilder::set_node_ptc_nums(RRNodeId node, const std::string& ptc_str) { + VTR_ASSERT(size_t(node) < node_storage_.size()); + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); + std::vector ptc_tokens = vtr::StringToken(ptc_str).split(","); + VTR_ASSERT(ptc_tokens.size() >= 1); + set_node_ptc_num(node, std::stoi(ptc_tokens[0])); + node_ptc_nums_[node].resize(ptc_tokens.size()); + for (size_t iptc = 0; iptc < ptc_tokens.size(); iptc++) { + node_ptc_nums_[node].push_back(std::stoi(ptc_tokens[iptc])); + } +} + +std::string RRGraphBuilder::node_ptc_nums_to_string(RRNodeId node) const { + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); + std::string ret; + for (size_t iptc = 0; iptc < node_ptc_nums_[node].size(); iptc++) { + ret += std::to_string(node_ptc_nums_[node][iptc]) + ","; + } + /* Remove the last comma */ + ret.pop_back(); + return ret; +} + + void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id) { VTR_ASSERT(size_t(node) < node_storage_.size()); VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 20df1e163db..45ff0294581 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -226,6 +226,12 @@ class RRGraphBuilder { node_storage_.set_node_class_num(id, new_class_num); } + /** @brief Add a list of ptc number in string (split by comma) to a given node. This function is used by rr graph reader only. Not suggested for internal builder!!! */ + void set_node_ptc_nums(RRNodeId node, const std::string& ptc_str); + + /** @brief With a given node, output ptc numbers into a string (use comma as delima). This function is used by rr graph writer only. Not suggested for internal builder!!! */ + std::string node_ptc_nums_to_string(RRNodeId node) const; + /** @brief Set the node direction; The node direction is only available of routing channel nodes, such as x-direction routing tracks (CHANX) and y-direction routing tracks (CHANY). For other nodes types, this value is not meaningful and should be set to NONE. */ inline void set_node_direction(RRNodeId id, Direction new_direction) { node_storage_.set_node_direction(id, new_direction); diff --git a/libs/librrgraph/src/io/rr_graph.xsd b/libs/librrgraph/src/io/rr_graph.xsd index 6b6650e100c..dd7af495225 100644 --- a/libs/librrgraph/src/io/rr_graph.xsd +++ b/libs/librrgraph/src/io/rr_graph.xsd @@ -265,7 +265,7 @@ - + diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 736ea358a81..9632edb5de5 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -688,18 +688,20 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { * * * - * + * * */ - inline int init_node_loc(int& inode, int ptc, int xhigh, int xlow, int yhigh, int ylow) final { + inline int init_node_loc(int& inode, std::string ptc, int xhigh, int xlow, int yhigh, int ylow) final { auto node = (*rr_nodes_)[inode]; RRNodeId node_id = node.id(); rr_graph_builder_->set_node_coordinates(node_id, xlow, ylow, xhigh, yhigh); // We set the layer num 0 - If it is specified in the XML, it will be overwritten rr_graph_builder_->set_node_layer(node_id, 0); - rr_graph_builder_->set_node_ptc_num(node_id, ptc); + /* Split the ptc with delima ',' if there is only one ptc, use regular method, otherwise, use node track num */ + rr_graph_builder_->set_node_ptc_nums(node_id, ptc); + return inode; } inline void finish_node_loc(int& /*inode*/) final {} @@ -707,8 +709,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { return node; } - inline int get_node_loc_ptc(const t_rr_node& node) final { - return rr_graph_->node_ptc_num(node.id()); + inline std::string get_node_loc_ptc(const t_rr_node& node) final { + return rr_graph_builder_->node_ptc_nums_to_string(node.id()); } inline int get_node_loc_layer(const t_rr_node& node) final { return rr_graph_->node_layer(node.id()); diff --git a/libs/librrgraph/src/utils/vtr_tokenizer.cpp b/libs/librrgraph/src/utils/vtr_tokenizer.cpp new file mode 100644 index 00000000000..1dc34270b15 --- /dev/null +++ b/libs/librrgraph/src/utils/vtr_tokenizer.cpp @@ -0,0 +1,167 @@ +/************************************************************************ + * Member functions for StringToken class + ***********************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_tokenizer.h" +#include "vtr_assert.h" + +/* namespace openfpga begins */ +namespace vtr { + +/************************************************************************ + * Constructors + ***********************************************************************/ +StringToken::StringToken(const std::string& data) { set_data(data); } + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +/* Get the data string */ +std::string StringToken::data() const { return data_; } + +/* Split the string using a given delim */ +std::vector StringToken::split(const std::string& delims) const { + /* Return vector */ + std::vector ret; + + /* Get a writable char array */ + char* tmp = new char[data_.size() + 1]; + std::copy(data_.begin(), data_.end(), tmp); + tmp[data_.size()] = '\0'; + /* Split using strtok */ + char* result = std::strtok(tmp, delims.c_str()); + while (NULL != result) { + std::string result_str(result); + /* Store the token */ + ret.push_back(result_str); + /* Got to next */ + result = std::strtok(NULL, delims.c_str()); + } + + /* Free the tmp */ + delete[] tmp; + + return ret; +} + +/* Split the string using a given delim */ +std::vector StringToken::split(const char& delim) const { + /* Create delims */ + std::string delims(1, delim); + + return split(delims); +} + +/* Split the string using a given delim */ +std::vector StringToken::split(const char* delim) const { + /* Create delims */ + std::string delims(delim); + + return split(delims); +} + +/* Split the string using a given delim */ +std::vector StringToken::split( + const std::vector& delims) const { + /* Create delims */ + std::string delims_str; + for (const auto& delim : delims) { + delims_str.push_back(delim); + } + + return split(delims_str); +} + +/* Split the string */ +std::vector StringToken::split() { + /* Add a default delim */ + if (true == delims_.empty()) { + add_default_delim(); + } + /* Create delims */ + std::string delims; + for (const auto& delim : delims_) { + delims.push_back(delim); + } + + return split(delims); +} + +std::vector StringToken::find_positions(const char& delim) const { + std::vector anchors; + size_t found = data_.find(delim); + while (std::string::npos != found) { + anchors.push_back(found); + found = data_.find(delim, found + 1); + } + return anchors; +} + +std::vector StringToken::split_by_chunks( + const char& chunk_delim, const bool& split_odd_chunk) const { + size_t chunk_idx_mod = 0; + if (split_odd_chunk) { + chunk_idx_mod = 1; + } + std::vector tokens; + /* There are pairs of quotes, identify the chunk which should be split*/ + std::vector token_chunks = split(chunk_delim); + for (size_t ichunk = 0; ichunk < token_chunks.size(); ichunk++) { + /* Chunk with even index (including the first) is always out of two quote -> + * Split! Chunk with odd index is always between two quotes -> Do not split! + */ + if (ichunk % 2 == chunk_idx_mod) { + StringToken chunk_tokenizer(token_chunks[ichunk]); + for (std::string curr_token : chunk_tokenizer.split()) { + tokens.push_back(curr_token); + } + } else { + tokens.push_back(token_chunks[ichunk]); + } + } + return tokens; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void StringToken::set_data(const std::string& data) { + data_ = data; + return; +} + +/* Add a delima to the list */ +void StringToken::add_delim(const char& delim) { delims_.push_back(delim); } + +/* Remove the string repeated at the beginning of string */ +void StringToken::ltrim(const std::string& sensitive_word) { + size_t start = data_.find_first_not_of(sensitive_word); + data_ = (start == std::string::npos) ? "" : data_.substr(start); + return; +} + +/* Remove the string repeated at the end of string */ +void StringToken::rtrim(const std::string& sensitive_word) { + size_t end = data_.find_last_not_of(sensitive_word); + data_ = (end == std::string::npos) ? "" : data_.substr(0, end + 1); + return; +} + +void StringToken::trim() { + rtrim(" "); + ltrim(" "); + return; +} + +/************************************************************************ + * Internal Mutators + ***********************************************************************/ +void StringToken::add_default_delim() { + VTR_ASSERT_SAFE(true == delims_.empty()); + delims_.push_back(' '); + return; +} + +} // namespace openfpga diff --git a/libs/librrgraph/src/utils/vtr_tokenizer.h b/libs/librrgraph/src/utils/vtr_tokenizer.h new file mode 100644 index 00000000000..2c70906413f --- /dev/null +++ b/libs/librrgraph/src/utils/vtr_tokenizer.h @@ -0,0 +1,70 @@ +#ifndef VTR_TOKENIZER_H +#define VTR_TOKENIZER_H + +/******************************************************************** + * Include header files that are required by data structure declaration + *******************************************************************/ +#include +#include + +/* namespace openfpga begins */ +namespace vtr { + +/************************************************************************ + * This file includes a tokenizer for string objects + * It splits a string with given delima and return a vector of tokens + * It can accept different delima in splitting strings + ***********************************************************************/ + +class StringToken { + public: /* Constructors*/ + StringToken(const std::string& data); + + public: /* Public Accessors */ + std::string data() const; + std::vector split(const std::string& delims) const; + std::vector split(const char& delim) const; + std::vector split(const char* delim) const; + std::vector split(const std::vector& delim) const; + std::vector split(); + /** @brief Find the position (i-th charactor) in a string for a given + * delimiter, it will return a list of positions For example, to find the + * position of all quotes (") in a string: "we" are good The following code is + * suggested: StringToken tokenizer("\"we\" are good"); std::vector + * anchors = tokenizer.find_positions('\"') The following vector will be + * returned: [0, 3] */ + std::vector find_positions(const char& delim) const; + /** @brief split the string for each chunk. This is useful where there are + * chunks of substring should not be splitted by the given delimiter For + * example, to split the string with quotes (") in a string: source "cmdA + * --opt1 val1;cmdB --opt2 val2" --verbose where the string between the two + * quotes should not be splitted The following code is suggested: StringToken + * tokenizer("source \"cmdA --opt1 val1;cmdB --opt2 val2\" --verbose"); + * std::vector tokenizer.split_by_chunks('\"', true); + * The following vector will be returned: + * ["source" "cmdA --opt1 val1;cmdB --opt2 val2" "--verbose"] + * + * .. note:: The option ``split_odd_chunk`` is useful when the chunk delimiter + * appears at the beginning of the string. + */ + std::vector split_by_chunks( + const char& chunk_delim, const bool& split_odd_chunk = false) const; + + public: /* Public Mutators */ + void set_data(const std::string& data); + void add_delim(const char& delim); + void ltrim(const std::string& sensitive_word); + void rtrim(const std::string& sensitive_word); + void trim(); + + private: /* Private Mutators */ + void add_default_delim(); + + private: /* Internal data */ + std::string data_; /* Lines to be splited */ + std::vector delims_; +}; + +} // namespace openfpga + +#endif From 54d9715033f4eddba459753f35bb160e3a043b4b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 15:33:56 -0700 Subject: [PATCH 205/453] [lib] update rr graph I/O auto-gen files --- libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h | 20 +++++++++---------- .../src/io/gen/rr_graph_uxsdcxx_capnp.h | 9 +++++---- .../src/io/gen/rr_graph_uxsdcxx_interface.h | 13 ++++++------ .../gen/rr_graph_uxsdcxx.capnp | 10 +++++----- 4 files changed, 26 insertions(+), 26 deletions(-) diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index 5099e2309e8..f452ad75857 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx/uxsdcxx.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42 + * Cmdline: uxsdcxx/uxsdcxx.py /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: f935bdbc0ff49d1ba93705b68f1db6dc */ #include @@ -87,7 +87,7 @@ template inline void load_grid_locs(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); template inline void load_node_loc(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); -inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * ptc, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function * report_error); +inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function * report_error); template inline void load_node_timing(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); inline void load_node_timing_required_attributes(const pugi::xml_node &root, float * C, float * R, const std::function * report_error); @@ -2346,7 +2346,7 @@ inline void load_grid_loc_required_attributes(const pugi::xml_node &root, int * if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_grid_loc, report_error); } -inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * ptc, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function * report_error){ +inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function * report_error){ std::bitset<8> astate = 0; for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ atok_t_node_loc in = lex_attr_t_node_loc(attr.name(), report_error); @@ -2357,7 +2357,7 @@ inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * /* Attribute layer set after element init */ break; case atok_t_node_loc::PTC: - *ptc = load_int(attr.value(), report_error); + /* Attribute ptc set after element init */ break; case atok_t_node_loc::SIDE: /* Attribute side set after element init */ @@ -3287,7 +3287,7 @@ inline void load_node_loc(const pugi::xml_node &root, T &out, Context &context, out.set_node_loc_layer(load_int(attr.value(), report_error), context); break; case atok_t_node_loc::PTC: - /* Attribute ptc is already set */ + out.set_node_loc_ptc(attr.value(), context); break; case atok_t_node_loc::SIDE: out.set_node_loc_side(lex_enum_loc_side(attr.value(), true, report_error), context); @@ -3470,8 +3470,6 @@ inline void load_node(const pugi::xml_node &root, T &out, Context &context, cons switch(in){ case gtok_t_node::LOC: { - int node_loc_ptc; - memset(&node_loc_ptc, 0, sizeof(node_loc_ptc)); int node_loc_xhigh; memset(&node_loc_xhigh, 0, sizeof(node_loc_xhigh)); int node_loc_xlow; @@ -3480,8 +3478,8 @@ inline void load_node(const pugi::xml_node &root, T &out, Context &context, cons memset(&node_loc_yhigh, 0, sizeof(node_loc_yhigh)); int node_loc_ylow; memset(&node_loc_ylow, 0, sizeof(node_loc_ylow)); - load_node_loc_required_attributes(node, &node_loc_ptc, &node_loc_xhigh, &node_loc_xlow, &node_loc_yhigh, &node_loc_ylow, report_error); - auto child_context = out.init_node_loc(context, node_loc_ptc, node_loc_xhigh, node_loc_xlow, node_loc_yhigh, node_loc_ylow); + load_node_loc_required_attributes(node, &node_loc_xhigh, &node_loc_xlow, &node_loc_yhigh, &node_loc_ylow, report_error); + auto child_context = out.init_node_loc(context, node_loc_xhigh, node_loc_xlow, node_loc_yhigh, node_loc_ylow); load_node_loc(node, out, child_context, report_error, offset_debug); out.finish_node_loc(child_context); } diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h index c523a6d7f42..062a33835cf 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx/uxsdcap.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42 + * Cmdline: uxsdcxx/uxsdcap.py /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: f935bdbc0ff49d1ba93705b68f1db6dc */ #include @@ -706,6 +706,7 @@ inline void load_node_loc_capnp_type(const ucap::NodeLoc::Reader &root, T &out, (void)stack; out.set_node_loc_layer(root.getLayer(), context); + out.set_node_loc_ptc(root.getPtc().cStr(), context); out.set_node_loc_side(conv_enum_loc_side(root.getSide(), report_error), context); out.set_node_loc_twist(root.getTwist(), context); } @@ -778,7 +779,7 @@ inline void load_node_capnp_type(const ucap::Node::Reader &root, T &out, Context stack->push_back(std::make_pair("getLoc", 0)); if (root.hasLoc()) { auto child_el = root.getLoc(); - auto child_context = out.init_node_loc(context, child_el.getPtc(), child_el.getXhigh(), child_el.getXlow(), child_el.getYhigh(), child_el.getYlow()); + auto child_context = out.init_node_loc(context, child_el.getXhigh(), child_el.getXlow(), child_el.getYhigh(), child_el.getYlow()); load_node_loc_capnp_type(child_el, out, child_context, report_error, stack); out.finish_node_loc(child_context); } diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h index 1fa575acf1a..b832527d52a 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx/uxsdcxx.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42 + * Cmdline: uxsdcxx/uxsdcxx.py /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: f935bdbc0ff49d1ba93705b68f1db6dc */ #include @@ -367,13 +367,14 @@ class RrGraphBase { * * * - * + * * * */ virtual inline int get_node_loc_layer(typename ContextTypes::NodeLocReadContext &ctx) = 0; virtual inline void set_node_loc_layer(int layer, typename ContextTypes::NodeLocWriteContext &ctx) = 0; - virtual inline int get_node_loc_ptc(typename ContextTypes::NodeLocReadContext &ctx) = 0; + virtual inline const char * get_node_loc_ptc(typename ContextTypes::NodeLocReadContext &ctx) = 0; + virtual inline void set_node_loc_ptc(const char * ptc, typename ContextTypes::NodeLocWriteContext &ctx) = 0; virtual inline enum_loc_side get_node_loc_side(typename ContextTypes::NodeLocReadContext &ctx) = 0; virtual inline void set_node_loc_side(enum_loc_side side, typename ContextTypes::NodeLocWriteContext &ctx) = 0; virtual inline int get_node_loc_twist(typename ContextTypes::NodeLocReadContext &ctx) = 0; @@ -445,7 +446,7 @@ class RrGraphBase { virtual inline void set_node_direction(enum_node_direction direction, typename ContextTypes::NodeWriteContext &ctx) = 0; virtual inline unsigned int get_node_id(typename ContextTypes::NodeReadContext &ctx) = 0; virtual inline enum_node_type get_node_type(typename ContextTypes::NodeReadContext &ctx) = 0; - virtual inline typename ContextTypes::NodeLocWriteContext init_node_loc(typename ContextTypes::NodeWriteContext &ctx, int ptc, int xhigh, int xlow, int yhigh, int ylow) = 0; + virtual inline typename ContextTypes::NodeLocWriteContext init_node_loc(typename ContextTypes::NodeWriteContext &ctx, int xhigh, int xlow, int yhigh, int ylow) = 0; virtual inline void finish_node_loc(typename ContextTypes::NodeLocWriteContext &ctx) = 0; virtual inline typename ContextTypes::NodeLocReadContext get_node_loc(typename ContextTypes::NodeReadContext &ctx) = 0; virtual inline typename ContextTypes::NodeTimingWriteContext init_node_timing(typename ContextTypes::NodeWriteContext &ctx, float C, float R) = 0; diff --git a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp index bba305feef1..8ef3bb1542a 100644 --- a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp +++ b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp @@ -2,11 +2,11 @@ # https://github.com/duck2/uxsdcxx # Modify only if your build process doesn't involve regenerating this file. # -# Cmdline: uxsdcxx/uxsdcap.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# md5sum of input file: bf49388f038e0d0e4a12403ebb964b42 +# Cmdline: uxsdcxx/uxsdcap.py /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# Input file: /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# md5sum of input file: f935bdbc0ff49d1ba93705b68f1db6dc -@0xf7009c96d0510b05; +@0xbd5af3032a028420; using Cxx = import "/capnp/c++.capnp"; $Cxx.namespace("ucap"); @@ -163,7 +163,7 @@ struct GridLocs { struct NodeLoc { layer @0 :Int32 = 0; - ptc @1 :Int32; + ptc @1 :Text; side @2 :LocSide; twist @3 :Int32; xhigh @4 :Int32; From 87ddc762cb605e45d82e5366aac68faa925cf17c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 15:51:51 -0700 Subject: [PATCH 206/453] [lib] update rr graph reader --- .../librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 13 ++++++++----- libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp | 2 +- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 9632edb5de5..025d473a1cf 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -692,15 +692,13 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { * */ - inline int init_node_loc(int& inode, std::string ptc, int xhigh, int xlow, int yhigh, int ylow) final { + inline int init_node_loc(int& inode, int xhigh, int xlow, int yhigh, int ylow) final { auto node = (*rr_nodes_)[inode]; RRNodeId node_id = node.id(); rr_graph_builder_->set_node_coordinates(node_id, xlow, ylow, xhigh, yhigh); // We set the layer num 0 - If it is specified in the XML, it will be overwritten rr_graph_builder_->set_node_layer(node_id, 0); - /* Split the ptc with delima ',' if there is only one ptc, use regular method, otherwise, use node track num */ - rr_graph_builder_->set_node_ptc_nums(node_id, ptc); return inode; } @@ -708,9 +706,14 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline const t_rr_node get_node_loc(const t_rr_node& node) final { return node; } + inline void set_node_loc_ptc(const char* ptc, int& inode) final { + auto node = (*rr_nodes_)[inode]; + RRNodeId node_id = node.id(); + return rr_graph_builder_->set_node_ptc_nums(node_id, std::string(ptc)); + } - inline std::string get_node_loc_ptc(const t_rr_node& node) final { - return rr_graph_builder_->node_ptc_nums_to_string(node.id()); + inline const char* get_node_loc_ptc(const t_rr_node& node) final { + return rr_graph_builder_->node_ptc_nums_to_string(node.id()).c_str(); } inline int get_node_loc_layer(const t_rr_node& node) final { return rr_graph_->node_layer(node.id()); diff --git a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp index 8ef3bb1542a..1a2a3c1ae53 100644 --- a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp +++ b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp @@ -6,7 +6,7 @@ # Input file: /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd # md5sum of input file: f935bdbc0ff49d1ba93705b68f1db6dc -@0xbd5af3032a028420; +@0xd574e99855680699; using Cxx = import "/capnp/c++.capnp"; $Cxx.namespace("ucap"); From 1088c3c2279f895c992cc5fc79c81d38494a802a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 16:01:45 -0700 Subject: [PATCH 207/453] [lib] fixed a few bugs --- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 025d473a1cf..88453b69124 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1791,6 +1791,10 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { for (size_t inode = 0; inode < rr_nodes_->size(); inode++) { auto node = (*rr_nodes_)[inode]; rr_graph_builder.add_node_to_all_locs(node.id()); + /* Set track numbers as a node may have multiple ptc */ + if (CHANX == rr_graph_->node_type(node.id()) || CHANY == rr_graph_->node_type(node.id())) { + rr_graph_builder.add_track_node_to_lookup(node.id()); + } } } From da0d678fd5e7e868b3439dc98bf0cd893c30f440 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 16:58:39 -0700 Subject: [PATCH 208/453] [vpr] fixed a bug where rr graph I/O always require node_ptc_nums --- libs/librrgraph/src/base/rr_graph_builder.cpp | 32 +++++++++++++------ libs/librrgraph/src/base/rr_graph_builder.h | 3 ++ .../src/io/rr_graph_uxsdcxx_serializer.h | 6 ++-- 3 files changed, 29 insertions(+), 12 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index e7228b8910e..dbe0b35e63b 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -240,27 +240,39 @@ std::vector RRGraphBuilder::node_in_edges(RRNodeId node) const { void RRGraphBuilder::set_node_ptc_nums(RRNodeId node, const std::string& ptc_str) { VTR_ASSERT(size_t(node) < node_storage_.size()); - VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); std::vector ptc_tokens = vtr::StringToken(ptc_str).split(","); VTR_ASSERT(ptc_tokens.size() >= 1); set_node_ptc_num(node, std::stoi(ptc_tokens[0])); - node_ptc_nums_[node].resize(ptc_tokens.size()); - for (size_t iptc = 0; iptc < ptc_tokens.size(); iptc++) { - node_ptc_nums_[node].push_back(std::stoi(ptc_tokens[iptc])); + if (ptc_tokens.size() > 1) { + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); + node_ptc_nums_[node].resize(ptc_tokens.size()); + for (size_t iptc = 0; iptc < ptc_tokens.size(); iptc++) { + node_ptc_nums_[node][iptc] = std::stoi(ptc_tokens[iptc]); + } } } std::string RRGraphBuilder::node_ptc_nums_to_string(RRNodeId node) const { - VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); std::string ret; - for (size_t iptc = 0; iptc < node_ptc_nums_[node].size(); iptc++) { - ret += std::to_string(node_ptc_nums_[node][iptc]) + ","; + if (node_ptc_nums_.empty()) { + ret = std::to_string(node_storage_.node_ptc_num(node)); + } else { + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); + for (size_t iptc = 0; iptc < node_ptc_nums_[node].size(); iptc++) { + ret += std::to_string(node_ptc_nums_[node][iptc]) + ","; + } + /* Remove the last comma */ + ret.pop_back(); } - /* Remove the last comma */ - ret.pop_back(); return ret; } - + +bool RRGraphBuilder::node_contain_multiple_ptc(RRNodeId node) const { + if (node_ptc_nums_.empty()) { + return false; + } + return node_ptc_nums_[node].size() > 1; +} void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id) { VTR_ASSERT(size_t(node) < node_storage_.size()); diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 45ff0294581..505f476a30f 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -232,6 +232,9 @@ class RRGraphBuilder { /** @brief With a given node, output ptc numbers into a string (use comma as delima). This function is used by rr graph writer only. Not suggested for internal builder!!! */ std::string node_ptc_nums_to_string(RRNodeId node) const; + /** @brief Identify if a node contains multiple ptc numbers. Mainly used by I/O reader only. Not suggest for internal builder */ + bool node_contain_multiple_ptc(RRNodeId node) const; + /** @brief Set the node direction; The node direction is only available of routing channel nodes, such as x-direction routing tracks (CHANX) and y-direction routing tracks (CHANY). For other nodes types, this value is not meaningful and should be set to NONE. */ inline void set_node_direction(RRNodeId id, Direction new_direction) { node_storage_.set_node_direction(id, new_direction); diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 88453b69124..a685aca6b4c 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1792,8 +1792,10 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { auto node = (*rr_nodes_)[inode]; rr_graph_builder.add_node_to_all_locs(node.id()); /* Set track numbers as a node may have multiple ptc */ - if (CHANX == rr_graph_->node_type(node.id()) || CHANY == rr_graph_->node_type(node.id())) { - rr_graph_builder.add_track_node_to_lookup(node.id()); + if (rr_graph_builder.node_contain_multiple_ptc(node.id())) { + if (CHANX == rr_graph_->node_type(node.id()) || CHANY == rr_graph_->node_type(node.id())) { + rr_graph_builder.add_track_node_to_lookup(node.id()); + } } } } From f9bfe6dafa8f60142527c775939899ba724aa802 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 17:30:36 -0700 Subject: [PATCH 209/453] [vpr] debugging --- libs/librrgraph/src/base/rr_graph_builder.cpp | 1 + libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h | 1 + libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 1 + 3 files changed, 3 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index dbe0b35e63b..4595f9b9a0f 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -256,6 +256,7 @@ std::string RRGraphBuilder::node_ptc_nums_to_string(RRNodeId node) const { std::string ret; if (node_ptc_nums_.empty()) { ret = std::to_string(node_storage_.node_ptc_num(node)); +// VTR_LOG("Node ptc single: %d -> string %s\n", node_storage_.node_ptc_num(node), ret.c_str()); } else { VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); for (size_t iptc = 0; iptc < node_ptc_nums_[node].size(); iptc++) { diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index f452ad75857..cf6f08d9fd6 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -4021,6 +4021,7 @@ inline void write_node(T &in, std::ostream &os, Context &context){ os << " { } inline const char* get_node_loc_ptc(const t_rr_node& node) final { +// VTR_LOG("RR graph writer ptc: %s\n", rr_graph_builder_->node_ptc_nums_to_string(node.id()).c_str()); return rr_graph_builder_->node_ptc_nums_to_string(node.id()).c_str(); } inline int get_node_loc_layer(const t_rr_node& node) final { From f8ed27ab99c95985c9d0bc71078e7fa54de18503 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 17:47:41 -0700 Subject: [PATCH 210/453] [lib] debugging --- libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h | 1 - libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 4 ++-- libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index cf6f08d9fd6..f452ad75857 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -4021,7 +4021,6 @@ inline void write_node(T &in, std::ostream &os, Context &context){ os << " { } inline const char* get_node_loc_ptc(const t_rr_node& node) final { -// VTR_LOG("RR graph writer ptc: %s\n", rr_graph_builder_->node_ptc_nums_to_string(node.id()).c_str()); - return rr_graph_builder_->node_ptc_nums_to_string(node.id()).c_str(); + std::string ret = rr_graph_builder_->node_ptc_nums_to_string(node.id()); + return ret.c_str(); } inline int get_node_loc_layer(const t_rr_node& node) final { return rr_graph_->node_layer(node.id()); diff --git a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp index 1a2a3c1ae53..89590cf4a3a 100644 --- a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp +++ b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp @@ -6,7 +6,7 @@ # Input file: /home/xifan/github/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd # md5sum of input file: f935bdbc0ff49d1ba93705b68f1db6dc -@0xd574e99855680699; +@0xf6fcbf56b4532db5; using Cxx = import "/capnp/c++.capnp"; $Cxx.namespace("ucap"); From d687349b5970426ee78051139f5b13eba6220142 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 18:13:36 -0700 Subject: [PATCH 211/453] [lib] fixed the bug in I/O of rrgraph. Seems that the ostream require std:string after to_string conversion --- libs/librrgraph/src/base/rr_graph_builder.cpp | 18 ++++++++++-------- libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h | 2 +- .../src/io/rr_graph_uxsdcxx_serializer.h | 3 +-- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 4595f9b9a0f..fcab757367d 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -255,16 +255,18 @@ void RRGraphBuilder::set_node_ptc_nums(RRNodeId node, const std::string& ptc_str std::string RRGraphBuilder::node_ptc_nums_to_string(RRNodeId node) const { std::string ret; if (node_ptc_nums_.empty()) { - ret = std::to_string(node_storage_.node_ptc_num(node)); + return std::to_string(node_storage_.node_ptc_num(node)); // VTR_LOG("Node ptc single: %d -> string %s\n", node_storage_.node_ptc_num(node), ret.c_str()); - } else { - VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); - for (size_t iptc = 0; iptc < node_ptc_nums_[node].size(); iptc++) { - ret += std::to_string(node_ptc_nums_[node][iptc]) + ","; - } - /* Remove the last comma */ - ret.pop_back(); } + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); + if (node_ptc_nums_[node].empty()) { + return std::to_string(node_storage_.node_ptc_num(node)); + } + for (size_t iptc = 0; iptc < node_ptc_nums_[node].size(); iptc++) { + ret += std::to_string(node_ptc_nums_[node][iptc]) + ","; + } + /* Remove the last comma */ + ret.pop_back(); return ret; } diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index f452ad75857..1ed1ef597c6 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -4020,7 +4020,7 @@ inline void write_node(T &in, std::ostream &os, Context &context){ auto child_context = in.get_node_loc(context); os << " { } inline const char* get_node_loc_ptc(const t_rr_node& node) final { - std::string ret = rr_graph_builder_->node_ptc_nums_to_string(node.id()); - return ret.c_str(); + return rr_graph_builder_->node_ptc_nums_to_string(node.id()).c_str(); } inline int get_node_loc_layer(const t_rr_node& node) final { return rr_graph_->node_layer(node.id()); From 616629d184a88a206fd444f04a7a922d85004a61 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 3 May 2024 22:39:16 -0700 Subject: [PATCH 212/453] [lib] add resize for ptc nums --- libs/librrgraph/src/base/rr_graph_builder.cpp | 8 ++++---- libs/librrgraph/src/base/rr_graph_builder.h | 5 +++++ libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 1 + 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index fcab757367d..26cddaf0518 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -253,17 +253,17 @@ void RRGraphBuilder::set_node_ptc_nums(RRNodeId node, const std::string& ptc_str } std::string RRGraphBuilder::node_ptc_nums_to_string(RRNodeId node) const { - std::string ret; if (node_ptc_nums_.empty()) { - return std::to_string(node_storage_.node_ptc_num(node)); + return std::to_string(size_t(node_storage_.node_ptc_num(node))); // VTR_LOG("Node ptc single: %d -> string %s\n", node_storage_.node_ptc_num(node), ret.c_str()); } VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); if (node_ptc_nums_[node].empty()) { - return std::to_string(node_storage_.node_ptc_num(node)); + return std::to_string(size_t(node_storage_.node_ptc_num(node))); } + std::string ret; for (size_t iptc = 0; iptc < node_ptc_nums_[node].size(); iptc++) { - ret += std::to_string(node_ptc_nums_[node][iptc]) + ","; + ret += std::to_string(size_t(node_ptc_nums_[node][iptc])) + ","; } /* Remove the last comma */ ret.pop_back(); diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 505f476a30f..84b5222c881 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -343,6 +343,11 @@ class RRGraphBuilder { inline void resize_nodes(size_t size) { node_storage_.resize(size); } + /** @brief This function resize node ptc nums. Only used by RR graph I/O reader and writers. Do not use for internal builder */ + inline void resize_node_ptc_nums(size_t size) { + node_ptc_nums_.resize(size); + } + /** @brief This function resize node ptc twist increment; Since it is only used for tileable rr-graph, we don't put it in general resize function*/ inline void resize_ptc_twist_incr(size_t size){ diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index a685aca6b4c..9cddee7e79f 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -880,6 +880,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { */ inline void preallocate_rr_nodes_node(void*& /*ctx*/, size_t size) final { rr_graph_builder_->reserve_nodes(size); + rr_graph_builder_->resize_node_ptc_nums(size); } inline int add_rr_nodes_node(void*& /*ctx*/, unsigned int capacity, unsigned int id, uxsd::enum_node_type type) final { // make_room_in_vector will not allocate if preallocate_rr_nodes_node From 9e87fb47d61a9ca8051b68dfdc18c63a73da7d28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 4 May 2024 12:46:54 -0700 Subject: [PATCH 213/453] [lib] fixed the bug on rr graph io. Should use temp_string_ --- libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h | 2 +- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index 1ed1ef597c6..f452ad75857 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -4020,7 +4020,7 @@ inline void write_node(T &in, std::ostream &os, Context &context){ auto child_context = in.get_node_loc(context); os << " { } inline const char* get_node_loc_ptc(const t_rr_node& node) final { - return rr_graph_builder_->node_ptc_nums_to_string(node.id()).c_str(); + temp_string_ = rr_graph_builder_->node_ptc_nums_to_string(node.id()); + return temp_string_.c_str(); } inline int get_node_loc_layer(const t_rr_node& node) final { return rr_graph_->node_layer(node.id()); From e62d84a4be7e29d89d04271990991eb6ef461e1f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 4 May 2024 22:40:20 -0700 Subject: [PATCH 214/453] [lib] fixed a bug on node lookup assignment in RR graph I/O when supporting multiple ptc --- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 94d0481f3cb..e258e300863 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1792,13 +1792,14 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { /* Add the correct node into the vector */ for (size_t inode = 0; inode < rr_nodes_->size(); inode++) { auto node = (*rr_nodes_)[inode]; - rr_graph_builder.add_node_to_all_locs(node.id()); /* Set track numbers as a node may have multiple ptc */ if (rr_graph_builder.node_contain_multiple_ptc(node.id())) { if (CHANX == rr_graph_->node_type(node.id()) || CHANY == rr_graph_->node_type(node.id())) { rr_graph_builder.add_track_node_to_lookup(node.id()); } - } + } else { + rr_graph_builder.add_node_to_all_locs(node.id()); + } } } From 695c05342fd76786f1a8f310ecfb9ae1b0af3f81 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 5 May 2024 12:51:02 -0700 Subject: [PATCH 215/453] [lib] now add rc data for CHANX and CHANY nodes in tileable rr graph --- .../tileable_rr_graph_node_builder.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index ce87b037c83..f1e66134e9c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -746,6 +746,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, + std::vector& rr_rc_data, const size_t& layer, const vtr::Point& chan_coordinate, const t_rr_type& chan_type, @@ -815,6 +816,11 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_node_track_ids[rr_node_id].push_back(itrack); rr_graph_builder.add_node_track_num(rr_node_id, chan_coordinate, itrack); } + /* Finish node RC attributes */ + size_t seg_id = chan_details.get_track_segment_id(itrack); + float node_R = rr_graph.node_length(rr_node_id) * segment_infs[seg_id].Rmetal; + float node_C = rr_graph.node_length(rr_node_id) * segment_infs[seg_id].Cmetal; + rr_graph_builder.set_node_rc_index(rr_node_id, NodeRCIndex(find_create_rr_rc_data(node_R, node_C, rr_rc_data))); /* Finish here, go to next */ } @@ -862,6 +868,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, + std::vector& rr_rc_data, const DeviceGrid& grids, const size_t& layer, const size_t& chan_width, @@ -964,6 +971,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, + rr_rc_data, layer, chanx_coord, CHANX, chanx_details, segment_infs, @@ -984,6 +992,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::map>& rr_node_track_ids, + std::vector& rr_rc_data, const DeviceGrid& grids, const size_t& layer, const size_t& chan_width, @@ -1090,6 +1099,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, + rr_rc_data, layer, chany_coord, CHANY, chany_details, segment_infs, @@ -1170,6 +1180,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, + rr_rc_data, grids, layer, chan_width.x(), segment_inf_x, @@ -1182,6 +1193,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, rr_graph_builder, rr_node_driver_switches, rr_node_track_ids, + rr_rc_data, grids, layer, chan_width.y(), segment_inf_y, From 1ba4766d0d00c87e6f86b688d941d731072a3909 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 5 May 2024 13:05:13 -0700 Subject: [PATCH 216/453] [test] now use L1 and L4 in the tileable arch --- vtr_flow/arch/timing/k4_N4_tileable_90nm.xml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml b/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml index 5193264205e..6e97691e42d 100644 --- a/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml +++ b/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml @@ -73,11 +73,16 @@ - + 1 1 1 + + + 1 1 1 1 1 + 1 1 1 1 + From d8def01fbea3de329d0f88c35a22620ef072f5d2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 5 May 2024 13:11:47 -0700 Subject: [PATCH 217/453] [test] add new testcases for tileable rr graph --- .../config/config.txt | 30 +++++++++++++++++++ .../config/golden_results.txt | 4 +++ .../config/config.txt | 30 +++++++++++++++++++ .../config/golden_results.txt | 4 +++ .../vtr_reg_strong/task_list.txt | 2 ++ 5 files changed, 70 insertions(+) create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/config.txt new file mode 100755 index 00000000000..a37a1a874db --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/config.txt @@ -0,0 +1,30 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/4 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=diffeq.blif +circuit_list_add=ex5p.blif +circuit_list_add=s298.blif + +# Add architectures to list to sweep +arch_list_add=k4_N4_tileable_90nm.xml + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt +parse_file=vpr_parse_second_file.txt + +# How to parse QoR info +qor_parse_file=qor_rr_graph.txt + +# Pass requirements +pass_requirements_file=pass_requirements_verify_rr_graph.txt + +script_params=-starting_stage vpr -verify_rr_graph --route_chan_width 60 -track_memory_usage + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt new file mode 100644 index 00000000000..8576e7f7dc7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 +k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 +k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/config.txt new file mode 100755 index 00000000000..aa015e865a0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/config.txt @@ -0,0 +1,30 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/4 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=diffeq.blif +circuit_list_add=ex5p.blif +circuit_list_add=s298.blif + +# Add architectures to list to sweep +arch_list_add=k4_N4_tileable_90nm.xml + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt +parse_file=vpr_parse_second_file.txt + +# How to parse QoR info +qor_parse_file=qor_rr_graph.txt + +# Pass requirements +pass_requirements_file=pass_requirements_verify_rr_graph.txt + +script_params=-starting_stage vpr -verify_rr_graph -rr_graph_ext .bin --route_chan_width 100 -track_memory_usage + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt new file mode 100644 index 00000000000..8576e7f7dc7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 +k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 +k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index eb8a900c155..d69600ece22 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -84,5 +84,7 @@ regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail regression_tests/vtr_reg_strong/strong_vpr_constraint regression_tests/vtr_reg_strong/strong_tileable_rr_graph +regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify +regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router From 26bac8cbac6b0140aee84c30dc2683506c1073cb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 May 2024 17:04:14 -0700 Subject: [PATCH 218/453] [core] fixed a bug where Y-axis segments may not be found --- .../tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index f1e66134e9c..35fd30101ce 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -818,8 +818,10 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, } /* Finish node RC attributes */ size_t seg_id = chan_details.get_track_segment_id(itrack); - float node_R = rr_graph.node_length(rr_node_id) * segment_infs[seg_id].Rmetal; - float node_C = rr_graph.node_length(rr_node_id) * segment_infs[seg_id].Cmetal; + e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); + float node_R = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Rmetal; + float node_C = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Cmetal; rr_graph_builder.set_node_rc_index(rr_node_id, NodeRCIndex(find_create_rr_rc_data(node_R, node_C, rr_rc_data))); /* Finish here, go to next */ } From 7b78e57ec9609086d13a450bd325ac0767fa7987 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 19 May 2024 14:08:49 -0700 Subject: [PATCH 219/453] [core] add methods to identify opins for connection blocks --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 95 ++++++++++++++++++++++++++++ vpr/src/tileable_rr_graph/rr_gsb.h | 18 +++++- 2 files changed, 111 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index f58a7b8dbc3..dd5628dc414 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -27,6 +27,7 @@ RRGSB::RRGSB() { ipin_node_.clear(); opin_node_.clear(); + cb_opin_node_.clear(); } /************************************************************************ @@ -97,6 +98,31 @@ std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) cons return ipin_sides; } +/* Get the sides of ipin_nodes belong to the cb */ +std::vector RRGSB::get_cb_opin_sides(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + + std::vector opin_sides; + + /* Make sure a clean start */ + opin_sides.clear(); + + switch (cb_type) { + case CHANX: + case CHANY: + opin_sides.push_back(TOP); + opin_sides.push_back(RIGHT); + opin_sides.push_back(BOTTOM); + opin_sides.push_back(LEFT); + break; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } + + return opin_sides; +} + /* Get the direction of a rr_node at a given side and track_id */ enum PORTS RRGSB::get_chan_node_direction(const e_side& side, const size_t& track_id) const { SideManager side_manager(side); @@ -257,6 +283,29 @@ RRNodeId RRGSB::get_opin_node(const e_side& side, const size_t& node_id) const { return opin_node_[side_manager.to_size_t()][node_id]; } +/* Get the number of OPIN rr_nodes on a side */ +size_t RRGSB::get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + size_t icb_type = get_cb_opin_type_id(cb_type); + return cb_opin_node_[icb_type][side_manager.to_size_t()].size(); +} + +/* get a opin_node at a given side and track_id */ +RRNodeId RRGSB::get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_cb_opin_node_id(cb_type, side, node_id)); + + size_t icb_type = get_cb_opin_type_id(cb_type); + return cb_opin_node_[icb_type][side_manager.to_size_t()][node_id]; +} + /* Get the node index of a routing track of a connection block, return -1 if not found */ int RRGSB::get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const { enum e_side chan_side = get_cb_chan_side(cb_type); @@ -921,6 +970,37 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { } } +void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { + for (t_rr_type cb_type : {CHANX, CHANY}) { + size_t icb_type = cb_type == CHANX ? 0 : 1; + std::vector cb_opin_sides = rr_gsb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); + ++inode) { + std::vector driver_rr_edges = + get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); + for (const RREdgeId curr_edge : driver_rr_edges) { + RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); + if (OPIN != rr_graph.node_type(cand_node)) { + continue; + } + enum e_side cb_opin_side = NUM_SIDES; + int cb_opin_index = -1; + rr_gsb.get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, + cb_opin_index); + VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); + + if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == + std::find(cb_opin_node_[icb_type][size_t(cb_opin_side)].begin(), cb_opin_node_[icb_type][size_t(cb_opin_side)].end(), cand_node)) { + cb_opin_node_[icb_type][size_t(cb_opin_side)] = cand_node; + } + } + } + } + } +} + /************************************************************************ * Public Mutators: clean-up functions ***********************************************************************/ @@ -1031,6 +1111,15 @@ bool RRGSB::validate_opin_node_id(const e_side& side, const size_t& node_id) con return (node_id < opin_node_[size_t(side)].size()); } +/* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ +bool RRGSB::validate_cb_opin_node_id(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const { + if (false == validate_side(side)) { + return false; + } + size_t icb_type = get_cb_opin_type_id(cb_type); + return (node_id < cb_opin_node_[icb_type][size_t(side)].size()); +} + /* Check the ipin_node_id is valid for opin_node_ and opin_node_grid_side_ */ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) const { if (false == validate_side(side)) { @@ -1042,3 +1131,9 @@ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) con bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { return ((CHANX == cb_type) || (CHANY == cb_type)); } + +size_t RRGSB::get_cb_opin_type_id(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + return cb_type == CHANX ? 0 : 1; +} + diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 7b0e62b2b09..0a44100f23e 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -72,6 +72,8 @@ class RRGSB { /* Get the sides of CB ipins in the array */ std::vector get_cb_ipin_sides(const t_rr_type& cb_type) const; + /* Get the sides of CB opins in the array, OPINs can only be at the same sides of IPINs. Differently, they are inputs to a connection block */ + std::vector get_cb_opin_sides(const t_rr_type& cb_type) const; /* Get the direction of a rr_node at a given side and track_id */ enum PORTS get_chan_node_direction(const e_side& side, const size_t& track_id) const; @@ -107,9 +109,13 @@ class RRGSB { /* Get the number of OPIN rr_nodes on a side */ size_t get_num_opin_nodes(const e_side& side) const; + /* Get the number of OPIN rr_nodes on a side of a connection block */ + size_t get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const; /* get a rr_node at a given side and track_id */ - RRNodeId get_opin_node(const e_side& side, const size_t& node_id) const; + RRNodeId get_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + /* get a rr_node at a given side and track_id for a connection block */ + RRNodeId get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; int get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const; @@ -184,6 +190,8 @@ class RRGSB { void sort_chan_node_in_edges(const RRGraphView& rr_graph); /* Sort all the incoming edges for input pin rr_node */ void sort_ipin_node_in_edges(const RRGraphView& rr_graph); + /* Build the lists of opin node for connection blocks. This is required after adding all the nodes */ + void build_cb_opin_nodes(const RRGraphView& rr_graph); public: /* Mutators: cleaners */ void clear(); @@ -210,7 +218,6 @@ class RRGSB { void sort_ipin_node_in_edges(const RRGraphView& rr_graph, const e_side& chan_side, const size_t& ipin_id); - private: /* internal functions */ size_t get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const; @@ -218,9 +225,11 @@ class RRGSB { bool validate_num_sides() const; bool validate_side(const e_side& side) const; bool validate_track_id(const e_side& side, const size_t& track_id) const; + bool validate_cb_opin_node_id(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; bool validate_opin_node_id(const e_side& side, const size_t& node_id) const; bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const; bool validate_cb_type(const t_rr_type& cb_type) const; + size_t get_cb_opin_type_id(const t_rr_type& cb_type) const; private: /* Internal Data */ /* Coordinator */ @@ -255,6 +264,11 @@ class RRGSB { /* Logic Block Outputs data */ std::vector> opin_node_; + /* Logic block outputs which directly drive IPINs in connection block, + * CBX -> array[0], CBY -> array[1] + * Each CB may have OPINs from all sides + */ + std::array, NUM_SIDES>, 2> cb_opin_node_; }; #endif From 76e9bc1142ef61af10a9d91d3336646e85070a3f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 19 May 2024 14:20:31 -0700 Subject: [PATCH 220/453] [core] syntax --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 16 ++++++++++------ vpr/src/tileable_rr_graph/rr_gsb.h | 2 +- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index dd5628dc414..b11a80d5d86 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -27,7 +27,11 @@ RRGSB::RRGSB() { ipin_node_.clear(); opin_node_.clear(); - cb_opin_node_.clear(); + for (size_t icb_type = 0; icb_type < 2; icb_type++) { + for (size_t iside = 0; iside < NUM_SIDES; iside++) { + cb_opin_node_[icb_type][iside].clear(); + } + } } /************************************************************************ @@ -973,10 +977,10 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { for (t_rr_type cb_type : {CHANX, CHANY}) { size_t icb_type = cb_type == CHANX ? 0 : 1; - std::vector cb_opin_sides = rr_gsb.get_cb_ipin_sides(cb_type); + std::vector cb_ipin_sides = get_cb_ipin_sides(cb_type); for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); + for (size_t inode = 0; inode < get_num_ipin_nodes(cb_ipin_side); ++inode) { std::vector driver_rr_edges = get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); @@ -987,13 +991,13 @@ void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { } enum e_side cb_opin_side = NUM_SIDES; int cb_opin_index = -1; - rr_gsb.get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, - cb_opin_index); + get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, + cb_opin_index); VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == std::find(cb_opin_node_[icb_type][size_t(cb_opin_side)].begin(), cb_opin_node_[icb_type][size_t(cb_opin_side)].end(), cand_node)) { - cb_opin_node_[icb_type][size_t(cb_opin_side)] = cand_node; + cb_opin_node_[icb_type][size_t(cb_opin_side)].push_back(cand_node); } } } diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 0a44100f23e..bdbe3da91e0 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -113,7 +113,7 @@ class RRGSB { size_t get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const; /* get a rr_node at a given side and track_id */ - RRNodeId get_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + RRNodeId get_opin_node(const e_side& side, const size_t& node_id) const; /* get a rr_node at a given side and track_id for a connection block */ RRNodeId get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; From c27caa39bf4efd1614857d7c7e60590ac3d5c896 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 20 May 2024 13:32:04 -0700 Subject: [PATCH 221/453] [core] fixed a bug on rr gsb when sorting edges from OPINs --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 56 +++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index b11a80d5d86..e6e6f8c9fab 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -893,6 +893,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const e_side& ipin_side, const size_t& ipin_id) { std::map from_track_edge_map; + std::array, NUM_SIDES> from_opin_edge_map; e_side chan_side = get_cb_chan_side(ipin_side); @@ -905,14 +906,21 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, * and cache these. Then we will use the data to sort the edge in the * following sequence: * 0----------------------------------------------------------------> num_in_edges() + * |<---------------------------1st part routing tracks -------------> + * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| + * |<---------------------------2nd part IPINs -------------> * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| * For each side, the edge will be sorted by the node index starting from 0 - * For each side, the edge from grid pins will be the 1st part - * while the edge from routing tracks will be the 2nd part + * For each side, the edge from grid pins will be the 2nd part (sorted by ptc number) + * while the edge from routing tracks will be the 1st part */ for (const RREdgeId& edge : rr_graph.node_in_edges(ipin_node)) { /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); + /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ + if (CHANX != rr_graph.node_type(src_node) && CHANY != rr_graph.node_type(src_node)) { + continue; + } /* The driver routing channel node can be either an input or an output to the GSB. * Just try to find a qualified one. */ int index = OPEN; @@ -949,6 +957,42 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, edge_counter++; } + for (const RREdgeId& edge : rr_graph.node_in_edges(ipin_node)) { + /* We care the source node of this edge, and it should be an input of the GSB!!! */ + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ + if (OPIN != rr_graph.node_type(src_node)) { + continue; + } + enum e_side cb_opin_side = NUM_SIDES; + int cb_opin_index = -1; + get_node_side_and_index(rr_graph, src_node, IN_PORT, cb_opin_side, + cb_opin_index); + VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); + /* Must have valid side and index */ + if (OPEN == cb_opin_index || NUM_SIDES == cb_opin_side) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(src_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(src_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + VTR_LOG("\n----------------------------------\n"); + VTR_LOG("IPIN node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(ipin_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(ipin_node)); + VTR_LOG("Fan-in nodes:\n"); + for (const auto& temp_edge : rr_graph.node_in_edges(ipin_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(temp_edge)).c_str()); + } + } + from_opin_edge_map[size_t(cb_opin_side)][cb_opin_index] = edge; + edge_counter++; + } + /* Store the sorted edge */ for (size_t itrack = 0; itrack < chan_node_[size_t(chan_side)].get_chan_width(); ++itrack) { if (0 < from_track_edge_map.count(itrack)) { @@ -956,6 +1000,14 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, } } + for (e_side iside : {TOP, RIGHT, BOTTOM, LEFT}) { + for (size_t ipin = 0; ipin < get_num_opin_nodes(iside); ++ipin) { + if (0 < from_opin_edge_map[size_t(iside)].count(ipin)) { + ipin_node_in_edges_[size_t(ipin_side)][ipin_id].push_back(from_opin_edge_map[size_t(iside)][ipin]); + } + } + } + VTR_ASSERT(edge_counter == ipin_node_in_edges_[size_t(ipin_side)][ipin_id].size()); } From ec85a468b0452ed63c62acb466366368a9ac89e5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 20 May 2024 17:16:17 -0700 Subject: [PATCH 222/453] [core] add more debuggin messages --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index e6e6f8c9fab..7911ebd68de 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -1045,6 +1045,17 @@ void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { int cb_opin_index = -1; get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, cb_opin_index); + if ((-1 == cb_opin_index) || (NUM_SIDES == cb_opin_side)) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(cand_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(cand_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(cand_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + } VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == From b49f82f657ead5e76af41f963d0dbc067348b110 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 11:15:38 +0800 Subject: [PATCH 223/453] Update device_grid_annotation.cpp --- vpr/src/tileable_rr_graph/device_grid_annotation.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp index e389af027ed..b675f92fe3c 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -2,7 +2,7 @@ #include "vtr_log.h" #include "vpr_utils.h" -DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid) { +DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid) { alloc(grid); init(grid); } From 7cdb3f734f56f4772af32c9ad7e8b31796834db5 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 11:53:52 +0800 Subject: [PATCH 224/453] Update tileable_chan_details_builder.cpp Add bend wires --- .../tileable_chan_details_builder.cpp | 109 ++++++++++++++---- 1 file changed, 87 insertions(+), 22 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index c0def1dfa69..7413507bf14 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -180,31 +180,96 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, /* Add node to ChanNodeDetails */ size_t cur_track = 0; for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - /* segment length will be set to maxium segment length if this is a longwire */ - size_t seg_len = segment_inf[iseg].length; - if (true == segment_inf[iseg].longline) { - seg_len = max_seg_length; + if (!segment_inf[iseg].isbend){ + /* segment length will be set to maxium segment length if this is a longwire */ + size_t seg_len = segment_inf[iseg].length; + if (true == segment_inf[iseg].longline) { + seg_len = max_seg_length; + } + for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { + bool seg_start = false; + bool seg_end = false; + /* Every first track of a group of Length-N wires, we set a starting point */ + if (0 == itrack % seg_len) { + seg_start = true; + } + /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ + if ((seg_len - 1 == itrack % seg_len) + || (itrack == num_tracks[iseg] - 1)) { + seg_end = true; + } + /* Since this is a unidirectional routing architecture, + * Add a pair of tracks, 1 INC track and 1 DEC track + */ + int seg_index = segment_inf[iseg].seg_index; + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len, seg_start, seg_end); + cur_track++; + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len, seg_start, seg_end); + cur_track++; + } } - for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { - bool seg_start = false; - bool seg_end = false; - /* Every first track of a group of Length-N wires, we set a starting point */ - if (0 == itrack % seg_len) { - seg_start = true; + else{ + bend_num++; + VTR_ASSERT(segment_inf[iseg].isbend); + std::vector seg_len = segment_inf[iseg].part_len; + std::vector bend = segment_inf[iseg].bend; + VTR_ASSERT(seg_len.size() == 2); + + std::vector num_tracks_bend; + for(size_t i = 0; i < seg_len.size(); i++) + num_tracks_bend.push_back(num_tracks[iseg] * seg_len[i] / segment_inf[iseg].length); + + VTR_ASSERT(num_tracks_bend[0] + num_tracks_bend[1] == num_tracks[iseg]); + + for (size_t itrack = 0; itrack < num_tracks_bend[0]; ++itrack) { + + bool seg_start = false; + bool seg_end = false; + size_t seg_bend_start = 0; + size_t seg_bend_end = 0; + + if (0 == itrack % seg_len[0]) { + seg_start = true; + } + + if ((seg_len[0] - 1 == itrack % seg_len[0]) + || (itrack == num_tracks_bend[0] - 1)) { + seg_end = true; + seg_bend_end = bend_num; + } + int seg_index = segment_inf[iseg].seg_index; + + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + } - /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ - if ((seg_len - 1 == itrack % seg_len) - || (itrack == num_tracks[iseg] - 1)) { - seg_end = true; + for (size_t itrack = 0; itrack < num_tracks_bend[1]; ++itrack) { + + bool seg_start = false; + bool seg_end = false; + size_t seg_bend_start = 0; + size_t seg_bend_end = 0; + + if (0 == itrack % seg_len[1]) { + seg_start = true; + seg_bend_start = bend_num; + } + + if ((seg_len[1] - 1 == itrack % seg_len[1]) + || (itrack == num_tracks_bend[1] - 1)) { + seg_end = true; + } + int seg_index = segment_inf[iseg].seg_index; + + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + } - /* Since this is a unidirectional routing architecture, - * Add a pair of tracks, 1 INC track and 1 DEC track - */ - int seg_index = segment_inf[iseg].seg_index; - chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len, seg_start, seg_end); - cur_track++; - chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len, seg_start, seg_end); - cur_track++; } } /* Check if all the tracks have been satisified */ From c8d6be8907832abf627c01b7c019da761fb8c427 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 12:42:34 +0800 Subject: [PATCH 225/453] Update tileable_rr_graph_node_builder.cpp --- .../tileable_rr_graph_node_builder.cpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 35fd30101ce..4b417fca325 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -787,6 +787,13 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, /* cost index depends on the segment index */ rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + parallel_seg_id)); + + if (chan_details.is_track_start(itrack)) { + rr_graph_builder.set_node_bend_start(node, chan_details.get_track_bend_start(itrack)); + } + if (chan_details.is_track_end(itrack)) { + rr_graph_builder.set_node_bend_end(node, chan_details.get_track_bend_end(itrack)); + } /* Finish here, go to next */ } @@ -823,6 +830,13 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, float node_R = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Rmetal; float node_C = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Cmetal; rr_graph_builder.set_node_rc_index(rr_node_id, NodeRCIndex(find_create_rr_rc_data(node_R, node_C, rr_rc_data))); + + if (chan_details.is_track_start(itrack)) { + rr_graph_builder.set_node_bend_start(rr_node_id, chan_details.get_track_bend_start(itrack)); + } + if (chan_details.is_track_end(itrack)) { + rr_graph_builder.set_node_bend_end(rr_node_id, chan_details.get_track_bend_end(itrack)); + } /* Finish here, go to next */ } From f328220171c02514c666b8ca585264f1474f63a8 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 12:44:19 +0800 Subject: [PATCH 226/453] Update tileable_rr_graph_gsb.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 4d3bbfdcc67..bfb40eafea4 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -24,6 +24,7 @@ /************************************************************************ * Data stuctures related to the functions ***********************************************************************/ +typedef std::map t_bend_track2track_map; typedef std::vector>> t_track2track_map; typedef std::vector>> t_track2pin_map; typedef std::vector>>> t_pin2track_map; From 8a83ee931124f356601755922e19908ee36a8863 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 12:47:17 +0800 Subject: [PATCH 227/453] Update tileable_rr_graph_edge_builder.cpp --- .../tileable_rr_graph_edge_builder.cpp | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 93612de2fcc..032e361f164 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -118,7 +118,8 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const int& subFs, const bool& opin2all_sides, const bool& concat_wire, - const bool& wire_opposite_side) { + const bool& wire_opposite_side, + const RRSwitchId& delayless_switch) { size_t num_edges_to_create = 0; /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); @@ -132,6 +133,13 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); vtr::Point gsb_coord(ix, iy); + + /* adapt the bend_conn */ + t_bend_track2track_map sb_bend_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + sb_bend_conn = build_bend_track_to_track_map(grids, rr_graph_builder, rr_graph, + device_chan_width, segment_inf, + layer, gsb_coord, delayless_switch, rr_node_driver_switches); + /* Create a GSB object */ const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, device_chan_width, segment_inf_x, segment_inf_y, @@ -153,7 +161,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* Build edges for a GSB */ build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, - track2ipin_map, opin2track_map, + sb_bend_conn, track2ipin_map, opin2track_map, sb_conn, rr_node_driver_switches, num_edges_to_create); /* Finish this GSB, go to the next*/ rr_graph_builder.build_edges(true); From 5e23e1b7d954737eee3786f5dcfe1eca3c53f0c5 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 12:51:26 +0800 Subject: [PATCH 228/453] Update tileable_rr_graph_gsb.cpp --- .../tileable_rr_graph_gsb.cpp | 257 ++++++++++++++++++ 1 file changed, 257 insertions(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 79f4166e190..6356cc00bca 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -534,6 +534,257 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, return track2track_map; } +t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, + RRGraphBuilder& rr_graph_builder, + const RRGraphView& rr_graph, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const RRSwitchId& delayless_switch, + vtr::vector& rr_node_driver_switches) { + + std::vector>>> chan_rr_nodes_all_sides; //[side][bend_num][start/end][node] + chan_rr_nodes_all_sides.resize(4); + + int bend_seg_num = 0; + std::vector bend_seg_type; //bend type: 1: U; 2: D + for (size_t iseg = 0; iseg < segment_inf.size(); iseg++) { + if (segment_inf[iseg].isbend) { + bend_seg_num++; + + for (size_t i = 0; i < segment_inf[iseg].bend.size(); i++) { + if (segment_inf[iseg].bend[i] != 0) { + bend_seg_type.push_back(segment_inf[iseg].bend[i]); + break; + } + } + } + } + VTR_ASSERT(bend_seg_num == int(bend_seg_type.size())); + for (size_t side = 0; side < 4; ++side) { + std::vector rr_nodes; + switch (side) { + case TOP: /* TOP = 0 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.y() == grids.height() - 2) { + + break; + } + + chan_rr_nodes_all_sides[0].resize(bend_seg_num); + for (int i = 0; i < bend_seg_num; i++){ + chan_rr_nodes_all_sides[0][i].resize(2); //start/end track for bend + } + + rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, + CHANY); + + for (auto inode : rr_nodes) { + VTR_ASSERT(rr_graph.node_type(inode) ==CHANY); + Direction direction = rr_graph.node_direction(inode); + size_t xlow = rr_graph.node_xlow(inode); + size_t xhigh = rr_graph.node_xhigh(inode); + size_t ylow = rr_graph.node_ylow(inode); + size_t yhigh = rr_graph.node_yhigh(inode); + int bend_start = rr_graph.node_bend_start(inode); + int bend_end = rr_graph.node_bend_end(inode); + + VTR_ASSERT((bend_start <= bend_seg_num) && (bend_end <= bend_seg_num)); + if (direction == Direction::INC && bend_start != 0 && xlow == gsb_coordinate.x() && (ylow == gsb_coordinate.y() + 1)) { + VTR_ASSERT(bend_end == 0); + chan_rr_nodes_all_sides[0][bend_start - 1][0].push_back(inode); + } + if (direction == Direction::DEC && bend_end != 0 && xlow == gsb_coordinate.x() && (ylow == gsb_coordinate.y() + 1)) { + VTR_ASSERT(bend_start == 0); + chan_rr_nodes_all_sides[0][bend_end - 1][1].push_back(inode); + } + + } + + break; + case RIGHT: /* RIGHT = 1 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.x() == grids.width() - 2) { + + break; + } + + chan_rr_nodes_all_sides[1].resize(bend_seg_num); + for (int i = 0; i < bend_seg_num; i++){ + chan_rr_nodes_all_sides[1][i].resize(2); //start/end track for bend + } + + rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), + CHANX); + + for (auto inode : rr_nodes) { + VTR_ASSERT(rr_graph.node_type(inode) == CHANX); + Direction direction = rr_graph.node_direction(inode); + size_t xlow = rr_graph.node_xlow(inode); + size_t xhigh = rr_graph.node_xhigh(inode); + size_t ylow = rr_graph.node_ylow(inode); + size_t yhigh = rr_graph.node_yhigh(inode); + int bend_start = rr_graph.node_bend_start(inode); + int bend_end = rr_graph.node_bend_end(inode); + + VTR_ASSERT((bend_start <= bend_seg_num) && (bend_end <= bend_seg_num)); + if (direction == Direction::INC && bend_start != 0 && (xlow == gsb_coordinate.x() + 1) && ylow == gsb_coordinate.y()) { + VTR_ASSERT(bend_end == 0); + chan_rr_nodes_all_sides[1][bend_start - 1][0].push_back(inode); + } + if (direction == Direction::DEC && bend_end != 0 && (xlow == gsb_coordinate.x() + 1) && ylow == gsb_coordinate.y()) { + VTR_ASSERT(bend_start == 0); + chan_rr_nodes_all_sides[1][bend_end - 1][1].push_back(inode); + } + + } + break; + case BOTTOM: /* BOTTOM = 2 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.y() == 0) { + + break; + } + + chan_rr_nodes_all_sides[2].resize(bend_seg_num); + for (int i = 0; i < bend_seg_num; i++){ + chan_rr_nodes_all_sides[2][i].resize(2); //start/end track for bend + } + + rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, gsb_coordinate.x(), gsb_coordinate.y(), + CHANY); + + for (auto inode : rr_nodes) { + VTR_ASSERT(rr_graph.node_type(inode) == CHANY); + Direction direction = rr_graph.node_direction(inode); + size_t xlow = rr_graph.node_xlow(inode); + size_t xhigh = rr_graph.node_xhigh(inode); + size_t ylow = rr_graph.node_ylow(inode); + size_t yhigh = rr_graph.node_yhigh(inode); + int bend_start = rr_graph.node_bend_start(inode); + int bend_end = rr_graph.node_bend_end(inode); + + VTR_ASSERT((bend_start <= bend_seg_num) && (bend_end <= bend_seg_num)); + if (direction == Direction::INC && bend_end != 0 && xhigh == gsb_coordinate.x() && yhigh == gsb_coordinate.y()) { + VTR_ASSERT(bend_start == 0); + chan_rr_nodes_all_sides[2][bend_end - 1][1].push_back(inode); + } + if (direction == Direction::DEC && bend_start != 0 && xhigh == gsb_coordinate.x() && yhigh == gsb_coordinate.y()) { + VTR_ASSERT(bend_end == 0); + chan_rr_nodes_all_sides[2][bend_start - 1][0].push_back(inode); + } + + } + break; + case LEFT: /* BOTTOM = 2 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.x() == 0) { + + break; + } + + chan_rr_nodes_all_sides[3].resize(bend_seg_num); + for (int i = 0; i < bend_seg_num; i++){ + chan_rr_nodes_all_sides[3][i].resize(2); //start/end track for bend + } + + rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, gsb_coordinate.x(), gsb_coordinate.y(), + CHANX); + + for (auto inode : rr_nodes) { + VTR_ASSERT(rr_graph.node_type(inode) == CHANX); + Direction direction = rr_graph.node_direction(inode); + size_t xlow = rr_graph.node_xlow(inode); + size_t xhigh = rr_graph.node_xhigh(inode); + size_t ylow = rr_graph.node_ylow(inode); + size_t yhigh = rr_graph.node_yhigh(inode); + int bend_start = rr_graph.node_bend_start(inode); + int bend_end = rr_graph.node_bend_end(inode); + + VTR_ASSERT((bend_start <= bend_seg_num) && (bend_end <= bend_seg_num)); + if (direction == Direction::INC && bend_end != 0 && xhigh == gsb_coordinate.x() && yhigh == gsb_coordinate.y()) { + VTR_ASSERT(bend_start == 0); + chan_rr_nodes_all_sides[3][bend_end - 1][1].push_back(inode); + } + if (direction == Direction::DEC && bend_start != 0 && xhigh == gsb_coordinate.x() && yhigh == gsb_coordinate.y()) { + VTR_ASSERT(bend_end == 0); + chan_rr_nodes_all_sides[3][bend_start - 1][0].push_back(inode); + } + + } + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid side index!\n"); + exit(1); + + } + } + std::map bend_seg_head2bend_seg_end_map; + for (size_t ibend_seg = 0; ibend_seg < bend_seg_num; ibend_seg++) { + int bend_type = bend_seg_type[ibend_seg]; //bend_type 1:U 2:D + VTR_ASSERT(bend_type == 1 || bend_type == 2); + + if (bend_type == 1) { //bend type U + for (size_t side = 0; side < 4; side++){ + size_t to_side = (side + 1) % 4; + if (chan_rr_nodes_all_sides[side].size() > 0) + for (size_t inode = 0; inode < chan_rr_nodes_all_sides[side][ibend_seg][1].size(); inode++) { + + if (chan_rr_nodes_all_sides[to_side].size() > 0) { + VTR_ASSERT(chan_rr_nodes_all_sides[side][ibend_seg][1].size() == chan_rr_nodes_all_sides[to_side][ibend_seg][0].size()); + bend_seg_head2bend_seg_end_map.emplace(std::make_pair(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode])); + rr_node_driver_switches[chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode]] = delayless_switch; + } + else { + rr_graph_builder.set_node_bend_end(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], 0); + } + } + else { + if (chan_rr_nodes_all_sides[to_side].size() > 0) { + for (size_t inode = 0; inode < chan_rr_nodes_all_sides[to_side][ibend_seg][0].size(); inode++) { + rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); + } + } + } + } + + } + else if (bend_type == 2) { //bend type D + for (size_t side = 0; side < 4; side++){ + size_t to_side = (side + 3) % 4; + if (chan_rr_nodes_all_sides[side].size() > 0) + for (size_t inode = 0; inode < chan_rr_nodes_all_sides[side][ibend_seg][1].size(); inode++) { + + if (chan_rr_nodes_all_sides[to_side].size() > 0) { + VTR_ASSERT(chan_rr_nodes_all_sides[side][ibend_seg][1].size() == chan_rr_nodes_all_sides[to_side][ibend_seg][0].size()); + bend_seg_head2bend_seg_end_map.emplace(std::make_pair(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode])); + rr_node_driver_switches[chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode]] = delayless_switch; + } + else { + rr_graph_builder.set_node_bend_end(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], 0); + } + } + else { + if (chan_rr_nodes_all_sides[to_side].size() > 0) { + for (size_t inode = 0; inode < chan_rr_nodes_all_sides[to_side][ibend_seg][0].size(); inode++) { + rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); + } + } + } + } + } + + } + + return bend_seg_head2bend_seg_end_map; +} + /* Build a RRChan Object with the given channel type and coorindators */ static RRChan build_one_tileable_rr_chan(const size_t& layer, const vtr::Point& chan_coordinate, @@ -923,6 +1174,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, ***********************************************************************/ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRGSB& rr_gsb, + const t_bend_track2track_map& sb_bend_conn, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, @@ -973,6 +1225,11 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, } } } + /* Create edges between bend nodes */ + for (auto iter = sb_bend_conn.begin(); iter != sb_bend_conn.end(); ++iter) { + rr_graph_builder.create_edge(iter->first, iter->second, rr_node_driver_switches[iter->second], false); + edge_count++; + } num_edges_to_create += edge_count; } From 063a13d22f4c323fcdd844ca701c6acf3dbdcf3f Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 12:52:06 +0800 Subject: [PATCH 229/453] Update tileable_rr_graph_gsb.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index bfb40eafea4..b45df574c3f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -52,6 +52,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRGSB& rr_gsb, + const t_bend_track2track_map& sb_bend_conn, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, From 48df84d87315183b64add01526f44ab39d1dc954 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 12:54:01 +0800 Subject: [PATCH 230/453] Update tileable_rr_graph_builder.cpp --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index e22ac4d63a8..2a9852d3328 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -257,7 +257,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ Fc_in, Fc_out, sb_type, Fs, sb_subtype, subFs, opin2all_sides, concat_wire, - wire_opposite_side); + wire_opposite_side, + delayless_rr_switch); /************************************************************************ * Build direction connection lists From 9e11eb823ccdb8b49a6ffa9090093753868ccce5 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 13:00:23 +0800 Subject: [PATCH 231/453] Update read_xml_arch_file.cpp --- libs/libarchfpga/src/read_xml_arch_file.cpp | 84 +++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index d54b6967748..9a1f3b54fed 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -263,6 +263,7 @@ static void ProcessSegments(pugi::xml_node Parent, const pugiutil::loc_data& loc_data); static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiutil::loc_data& loc_data); static void ProcessCB_SB(pugi::xml_node Node, std::vector& list, const pugiutil::loc_data& loc_data); +static void ProcessBend(pugi::xml_node Node, std::vector& list, std::vector& part_len, bool& isbend, const int len, const pugiutil::loc_data& loc_data); static void ProcessPower(pugi::xml_node parent, t_power_arch* power_arch, const pugiutil::loc_data& loc_data); @@ -4019,6 +4020,15 @@ static void ProcessSegments(pugi::xml_node Parent, ProcessCB_SB(SubElem, Segs[i].sb, loc_data); } + /* Setup the bend list if they give one, otherwise use default */ + if (length > 1) { + Segs[i].isbend = false; + SubElem = get_single_child(Node, "bend", loc_data, ReqOpt::OPTIONAL); + if (SubElem) { + ProcessBend(SubElem, Segs[i].bend, Segs[i].part_len, Segs[i].isbend, (length - 1), loc_data); + } + } + /*Store the index of this segment in Segs vector*/ Segs[i].seg_index = i; /* Get next Node */ @@ -4031,6 +4041,80 @@ static void ProcessSegments(pugi::xml_node Parent, "Atleast one segment per-axis needs to get specified if no segments with non-specified (default) axis attribute exist."); } } + +static void ProcessBend(pugi::xml_node Node, std::vector& list, std::vector& part_len, bool& isbend, const int len, const pugiutil::loc_data& loc_data) { + const char* tmp = nullptr; + int i; + + tmp = get_attribute(Node, "type", loc_data).value(); + if (0 == strcmp(tmp, "pattern")) { + i = 0; + + /* Get the content string */ + tmp = Node.child_value(); + while (*tmp) { + switch (*tmp) { + case ' ': + case '\t': + case '\n': + break; + case '-': + list.push_back(0); + break; + case 'U': + list.push_back(1); + isbend = true; + break; + case 'D': + list.push_back(2); + isbend = true; + break; + case 'B': + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "B pattern is not supported in current version\n", + *tmp); + // list.push_back(3); + // isbend = true; + break; + default: + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "Invalid character %c in CB or SB depopulation list.\n", + *tmp); + } + ++tmp; + } + + if (list.size() != size_t(len)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "Wrong length of bend list (%d). Expect %d symbols.\n", + i, len); + } + } + + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "'%s' is not a valid type for specifying bend list.\n", + tmp); + } + + int tmp_len = 1; + int sum_len = 0; + for(size_t i_len = 0; i_len < list.size(); i_len++){ + if (list[i_len] == 0) { + tmp_len++; + } else if (list[i_len] != 0) { + VTR_ASSERT(tmp_len < (int) list.size()+1); + part_len.push_back(tmp_len); + sum_len += tmp_len; + tmp_len = 1; + } + } + + // add the last clip of segment + if (sum_len < (int) list.size()+1) + part_len.push_back(list.size() + 1 - sum_len); +} + /* Processes the switchblocklist section from the xml architecture file. * See vpr/SRC/route/build_switchblocks.c for a detailed description of this * switch block format */ From 9c6fc7a88194b38bec1dc3e55ad51f893444feb9 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 13:01:05 +0800 Subject: [PATCH 232/453] Update physical_types.h --- libs/libarchfpga/src/physical_types.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 15b1b82a596..1b4073dc851 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1580,6 +1580,9 @@ struct t_segment_inf { enum e_parallel_axis parallel_axis; std::vector cb; std::vector sb; + bool isbend; + std::vector bend; + std::vector part_len; int seg_index; //float Cmetal_per_m; /* Wire capacitance (per meter) */ }; From b7c24d6117716d4d4de5752811c2b7001275021a Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:07:56 +0800 Subject: [PATCH 233/453] Update tileable_chan_details_builder.cpp --- vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index 7413507bf14..be3a9b3e84f 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -179,6 +179,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, /* Add node to ChanNodeDetails */ size_t cur_track = 0; + size_t bend_num = 0; for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { if (!segment_inf[iseg].isbend){ /* segment length will be set to maxium segment length if this is a longwire */ From e9e7bfe1c14ec6674c705286553bc751da9ff422 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:11:13 +0800 Subject: [PATCH 234/453] Update chan_node_details.cpp --- vpr/src/tileable_rr_graph/chan_node_details.cpp | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/chan_node_details.cpp b/vpr/src/tileable_rr_graph/chan_node_details.cpp index ca8c6915734..6d420464c3c 100644 --- a/vpr/src/tileable_rr_graph/chan_node_details.cpp +++ b/vpr/src/tileable_rr_graph/chan_node_details.cpp @@ -76,6 +76,16 @@ bool ChanNodeDetails::is_track_end(const size_t& track_id) const { return track_end_[track_id]; } +size_t ChanNodeDetails::get_track_bend_start(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_bend_start_[track_id]; +} + +size_t ChanNodeDetails::get_track_bend_end(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_bend_end_[track_id]; +} + /* Track_id is the starting point of group (whose is_start should be true) * This function will try to find the track_ids with the same directionality as track_id and seg_length * A group size is the number of such nodes between the starting points (include the 1st starting point) @@ -168,13 +178,15 @@ void ChanNodeDetails::reserve(const size_t& chan_width) { } /* Add a track to the channel */ -void ChanNodeDetails::add_track(const size_t& track_node_id, const Direction& track_direction, const size_t& seg_id, const size_t& seg_length, const size_t& is_start, const size_t& is_end) { +void ChanNodeDetails::add_track(const size_t& track_node_id, const Direction& track_direction, const size_t& seg_id, const size_t& seg_length, const size_t& is_start, const size_t& is_end, const size_t& seg_bend_start, const size_t& seg_bend_end) { track_node_ids_.push_back(track_node_id); track_direction_.push_back(track_direction); seg_ids_.push_back(seg_id); seg_length_.push_back(seg_length); track_start_.push_back(is_start); track_end_.push_back(is_end); + track_bend_start_.push_back(seg_bend_start); + track_bend_end_.push_back(seg_bend_end); } /* Update the node_id of a given track */ From 260572e10fa621ee2a1b8393ee7e67b67c17fea1 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:14:49 +0800 Subject: [PATCH 235/453] Update chan_node_details.h --- vpr/src/tileable_rr_graph/chan_node_details.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h index e322b5c6d73..6768f84ebf0 100644 --- a/vpr/src/tileable_rr_graph/chan_node_details.h +++ b/vpr/src/tileable_rr_graph/chan_node_details.h @@ -40,6 +40,8 @@ class ChanNodeDetails { size_t get_track_segment_id(const size_t& track_id) const; bool is_track_start(const size_t& track_id) const; bool is_track_end(const size_t& track_id) const; + size_t get_track_bend_start(const size_t& track_id) const; + size_t get_track_bend_end(const size_t& track_id) const; std::vector get_seg_group(const size_t& track_id) const; std::vector get_seg_group_node_id(const std::vector& seg_group) const; size_t get_num_starting_tracks(const Direction& track_direction) const; @@ -47,7 +49,7 @@ class ChanNodeDetails { public: /* Mutators */ void reserve(const size_t& chan_width); /* Reserve the capacitcy of vectors */ - void add_track(const size_t& track_node_id, const Direction& track_direction, const size_t& seg_id, const size_t& seg_length, const size_t& is_start, const size_t& is_end); + void add_track(const size_t& track_node_id, const Direction& track_direction, const size_t& seg_id, const size_t& seg_length, const size_t& is_start, const size_t& is_end, const size_t& seg_bend_start = 0, const size_t& seg_bend_end = 0); void set_track_node_id(const size_t& track_index, const size_t& track_node_id); void set_track_node_ids(const std::vector& track_node_ids); void set_tracks_start(const Direction& track_direction); @@ -68,6 +70,8 @@ class ChanNodeDetails { std::vector seg_length_; /* Length of each segment */ std::vector track_start_; /* flag to identify if this is the starting point of the track */ std::vector track_end_; /* flag to identify if this is the ending point of the track */ + std::vector track_bend_start_; /* flag to identify if this is the starting point of the track after bend. 0 means it is not a bend start. Int number means the corresponding bend group */ + std::vector track_bend_end_; }; #endif From ce1b3b4fb462b722fbb2bce3566cd74dc5c5c67b Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:17:14 +0800 Subject: [PATCH 236/453] Update tileable_rr_graph_edge_builder.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 06b3a1f3f64..b3f1ab2e8be 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -38,7 +38,8 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const int& subFs, const bool& opin2all_sides, const bool& concat_wire, - const bool& wire_opposite_side); + const bool& wire_opposite_side, + const RRSwitchId& delayless_switch); void build_rr_graph_direct_connections(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, From dc6aa86f2aa563ca53a32a554b3ae393334b3ef6 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:23:23 +0800 Subject: [PATCH 237/453] Update tileable_rr_graph_edge_builder.cpp --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 032e361f164..bb1407bdbdd 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -103,7 +103,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, ***********************************************************************/ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, - const vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, const size_t& layer, const vtr::Point& device_chan_width, From 6a1f9f88ed0c0a6da110bb6ba08877cb2a02c37b Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:23:40 +0800 Subject: [PATCH 238/453] Update tileable_rr_graph_edge_builder.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index b3f1ab2e8be..56489089dbf 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -23,7 +23,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, - const vtr::vector& rr_node_driver_switches, + vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, const size_t& layer, const vtr::Point& device_chan_width, From 0d9e9fd90225e17b5a69c7730f407b15ac9341fa Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:25:09 +0800 Subject: [PATCH 239/453] Update tileable_rr_graph_gsb.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index b45df574c3f..3eeb26fcad8 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -42,6 +42,16 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const bool& wire_opposite_side, const std::vector& segment_inf); +t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, + RRGraphBuilder& rr_graph_builder, + const RRGraphView& rr_graph, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const RRSwitchId& delayless_switch, + vtr::vector& rr_node_driver_switches); + RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const RRGraphView& rr_graph, const vtr::Point& device_chan_width, From 042bef402d332219a5a67386c04e6ac4f0820d5f Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:28:59 +0800 Subject: [PATCH 240/453] Update rr_graph_view.h --- libs/librrgraph/src/base/rr_graph_view.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 1a75ee2404b..59680348eff 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -166,6 +166,13 @@ class RRGraphView { inline short node_layer(RRNodeId node) const { return node_storage_.node_layer(node); } + + inline short node_bend_start(RRNodeId node) const { + return node_storage_.node_bend_start(node); + } + inline short node_bend_end(RRNodeId node) const { + return node_storage_.node_bend_end(node); + } /** @brief Get the ptc number twist of a routing resource node. This function is inlined for runtime optimization. */ inline short node_ptc_twist(RRNodeId node) const{ From 77f802e988a18502fabd4f37a0fe4e46061b2a76 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:32:37 +0800 Subject: [PATCH 241/453] Update rr_graph_storage.h --- libs/librrgraph/src/base/rr_graph_storage.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 407c5ae02d0..1bba4432746 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -51,7 +51,7 @@ * side: The side of a grid location where an IPIN or OPIN is located. * * This field is valid only for IPINs and OPINs and should be ignored * * otherwise. */ -struct alignas(16) t_rr_node_data { +struct alignas(64) t_rr_node_data { int16_t cost_index_ = -1; int16_t rc_index_ = -1; @@ -60,6 +60,9 @@ struct alignas(16) t_rr_node_data { int16_t xhigh_ = -1; int16_t yhigh_ = -1; + size_t node_bend_start_ = 0; + size_t node_bend_end_ = 0; + t_rr_type type_ = NUM_RR_TYPES; /* The character is a hex number which is a 4-bit truth table for node sides @@ -83,8 +86,8 @@ struct alignas(16) t_rr_node_data { // t_rr_node_data is a key data structure, so fail at compile time if the // structure gets bigger than expected (16 bytes right now). Developers // should only expand it after careful consideration and measurement. -static_assert(sizeof(t_rr_node_data) == 16, "Check t_rr_node_data size"); -static_assert(alignof(t_rr_node_data) == 16, "Check t_rr_node_data size"); +static_assert(sizeof(t_rr_node_data) == 64, "Check t_rr_node_data size"); +static_assert(alignof(t_rr_node_data) == 64, "Check t_rr_node_data size"); /* t_rr_node_ptc_data is cold data is therefore kept seperate from * t_rr_node_data. @@ -184,6 +187,13 @@ class t_rr_graph_storage { return node_storage_[id].yhigh_; } + short node_bend_start(RRNodeId id) const { + return node_storage_[id].node_bend_start_; + } + short node_bend_end(RRNodeId id) const { + return node_storage_[id].node_bend_end_; + } + short node_capacity(RRNodeId id) const { return node_storage_[id].capacity_; } @@ -554,6 +564,8 @@ class t_rr_graph_storage { void set_node_layer(RRNodeId id, short layer); void set_node_ptc_twist_incr(RRNodeId id, short twist); void set_node_cost_index(RRNodeId, RRIndexedDataId new_cost_index); + void set_node_bend_start(RRNodeId id, size_t bend_start); + void set_node_bend_end(RRNodeId id, size_t bend_end); void set_node_rc_index(RRNodeId, NodeRCIndex new_rc_index); void set_node_capacity(RRNodeId, short new_capacity); void set_node_direction(RRNodeId, Direction new_direction); From ba5cd698f722a5b76fde7e109b015f89e78c2123 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:34:17 +0800 Subject: [PATCH 242/453] Update rr_graph_storage.cpp --- libs/librrgraph/src/base/rr_graph_storage.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index f4bd739e751..402e605abe6 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -745,6 +745,16 @@ void t_rr_graph_storage::set_node_coordinates(RRNodeId id, short x1, short y1, s } } +void t_rr_graph_storage::set_node_bend_start(RRNodeId id, size_t bend_start) { + auto& node = node_storage_[id]; + node.node_bend_start_ = bend_start; +} + +void t_rr_graph_storage::set_node_bend_end(RRNodeId id, size_t bend_end) { + auto& node = node_storage_[id]; + node.node_bend_end_ = bend_end; +} + void t_rr_graph_storage::set_node_cost_index(RRNodeId id, RRIndexedDataId new_cost_index) { auto& node = node_storage_[id]; if ((size_t)new_cost_index >= std::numeric_limits::max()) { From 7ffd299745fec40298ba35a089143246a01b979b Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 14:36:26 +0800 Subject: [PATCH 243/453] Update rr_graph_builder.h --- libs/librrgraph/src/base/rr_graph_builder.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 84b5222c881..8b6af64aef0 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -178,6 +178,14 @@ class RRGraphBuilder { node_storage_.set_node_coordinates(id, x1, y1, x2, y2); } + inline void set_node_bend_start(RRNodeId id, size_t bend_start) { + node_storage_.set_node_bend_start(id, bend_start); + } + + inline void set_node_bend_end(RRNodeId id, size_t bend_end) { + node_storage_.set_node_bend_end(id, bend_end); + } + /** @brief The ptc_num carries different meanings for different node types * (true in VPR RRG that is currently supported, may not be true in customized RRG) * CHANX or CHANY: the track id in routing channels From 155716f7843fa85f28513d812ccc582fcb7b213d Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 26 May 2024 15:24:02 +0800 Subject: [PATCH 244/453] Update read_xml_arch_file.cpp --- libs/libarchfpga/src/read_xml_arch_file.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 9a1f3b54fed..69eb758735a 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -3915,6 +3915,7 @@ static void ProcessSegments(pugi::xml_node Parent, //Unidir requires the following tags expected_subtags.push_back("mux"); + expected_subtags.push_back("bend"); expected_subtags.push_back("mux_inter_die"); } From 91e62d5f89e5fd9c88764f427825353a95035ed5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 4 Jun 2024 12:04:57 -0700 Subject: [PATCH 245/453] [vpr] bypass 0-fan-in node in power estimator --- vpr/src/power/power.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 94d55479580..431166f6ee4 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -924,6 +924,9 @@ static void power_usage_routing(t_power_usage* power_usage, int seg_index = device_ctx.rr_indexed_data[rr_graph.node_cost_index(rr_id)].seg_index; C_wire = wire_length * rr_graph.rr_segments(RRSegmentId(seg_index)).Cmetal; //(double)power_ctx.commonly_used->tile_length); + if (node_fan_in == 0) { + continue; // Bypass some nodes with 0 fan-in + } VTR_ASSERT(node_power->selected_input < node_fan_in); /* Multiplexor */ From d8cd3db91760728a5cf3d0a3b6c85597a4d36773 Mon Sep 17 00:00:00 2001 From: Tao Li Date: Wed, 5 Jun 2024 21:42:47 -0700 Subject: [PATCH 246/453] resolve merge conflicts. --- ...nstraint.cpp => route_constraint.cpp_back} | 0 ...e_constraint.h => route_constraint.h_back} | 0 vpr/src/base/vpr_api.cpp | 3 -- vpr/src/base/vpr_constraints.cpp_back | 18 +++++++ vpr/src/base/vpr_constraints.h | 6 +-- vpr/src/base/vpr_constraints_reader.cpp | 49 +++++-------------- vpr/src/base/vpr_constraints_reader.h | 2 +- vpr/src/base/vpr_constraints_serializer.h | 40 ++------------- vpr/src/base/vpr_constraints_writer.cpp | 44 ----------------- .../tileable_rr_graph_builder.cpp | 2 +- vpr/src/util/vpr_utils.cpp | 16 ------ 11 files changed, 38 insertions(+), 142 deletions(-) rename vpr/src/base/{route_constraint.cpp => route_constraint.cpp_back} (100%) rename vpr/src/base/{route_constraint.h => route_constraint.h_back} (100%) create mode 100644 vpr/src/base/vpr_constraints.cpp_back diff --git a/vpr/src/base/route_constraint.cpp b/vpr/src/base/route_constraint.cpp_back similarity index 100% rename from vpr/src/base/route_constraint.cpp rename to vpr/src/base/route_constraint.cpp_back diff --git a/vpr/src/base/route_constraint.h b/vpr/src/base/route_constraint.h_back similarity index 100% rename from vpr/src/base/route_constraint.h rename to vpr/src/base/route_constraint.h_back diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 0deedc7674f..ed3c68b8603 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -421,9 +421,6 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { vpr_analysis_flow(router_net_list, vpr_setup, arch, route_status, is_flat); } - // write out constratins - write_vpr_constraints(vpr_setup); - //close the graphics vpr_close_graphics(vpr_setup); diff --git a/vpr/src/base/vpr_constraints.cpp_back b/vpr/src/base/vpr_constraints.cpp_back new file mode 100644 index 00000000000..9ae678c94e0 --- /dev/null +++ b/vpr/src/base/vpr_constraints.cpp_back @@ -0,0 +1,18 @@ +#include "vpr_constraints.h" + + +UserPlaceConstraints& VprConstraints::mutable_place_constraints() { + return placement_constraints_; +} + +UserRouteConstraints& VprConstraints::mutable_route_constraints() { + return route_constraints_; +} + +const UserPlaceConstraints& VprConstraints::place_constraints() const { + return placement_constraints_; +} + +const UserRouteConstraints& VprConstraints::route_constraints() const { + return route_constraints_; +} diff --git a/vpr/src/base/vpr_constraints.h b/vpr/src/base/vpr_constraints.h index afb9da92c79..6ac53af783b 100644 --- a/vpr/src/base/vpr_constraints.h +++ b/vpr/src/base/vpr_constraints.h @@ -51,21 +51,21 @@ class VprConstraints { * * @param net_name the route constraint */ - void add_route_constraint(RouteConstraint rc); + void add_route_constraint(UserRouteConstraints rc); /** * @brief returns route constraint by index * * @param index the constraint index */ - const RouteConstraint get_route_constraint_by_idx(std::size_t index) const; + const UserRouteConstraints get_route_constraint_by_idx(std::size_t index) const; /** * @brief returns route constraint of a specific net * * @param net_name the net name */ - const RouteConstraint get_route_constraint_by_net_name(std::string net_name); + const UserRouteConstraints get_route_constraint_by_net_name(std::string net_name); /** * @brief returns number of route constraints diff --git a/vpr/src/base/vpr_constraints_reader.cpp b/vpr/src/base/vpr_constraints_reader.cpp index cd0c39785b0..9bb8dccf9bd 100644 --- a/vpr/src/base/vpr_constraints_reader.cpp +++ b/vpr/src/base/vpr_constraints_reader.cpp @@ -10,51 +10,26 @@ #include #include "vpr_constraints_reader.h" -#include "vtr_token.h" void load_vpr_constraints_file(const char* read_vpr_constraints_name) { vtr::ScopedStartFinishTimer timer("Reading VPR constraints from " + std::string(read_vpr_constraints_name)); VprConstraintsSerializer reader; - // file name from arguments could be a serial of files, seperated by colon ":" - // at this point, caller has already checked that the required constraint file name is not emtpy - int num_tokens = 0, num_file_read = 0; - bool found_file = false; - t_token* tokens = GetTokensFromString(read_vpr_constraints_name, &num_tokens); - std::string in_tokens(""); - for (int i = 0; i < num_tokens; i++) { - if ((tokens[i].type == TOKEN_COLON)) { // end of one input file - found_file = true; - } else if (i == num_tokens - 1) { // end of inputs, append token anyway - in_tokens += std::string(tokens[i].data); - found_file = true; - } else { - in_tokens += std::string(tokens[i].data); - } - if (found_file) { - const char* file_name = in_tokens.c_str(); - if (vtr::check_file_name_extension(file_name, ".xml")) { - try { - std::ifstream file(file_name); - void* context; - uxsd::load_vpr_constraints_xml(reader, context, file_name, file); - } catch (pugiutil::XmlError& e) { - vpr_throw(VPR_ERROR_ROUTE, file_name, e.line(), "%s", e.what()); - } - } else { - VTR_LOG_WARN( - "VPR constraints file '%s' may be in incorrect format. " - "Expecting .xml format. Not reading file.\n", - file_name); - } - in_tokens.clear(); - num_file_read++; - found_file = false; + if (vtr::check_file_name_extension(read_vpr_constraints_name, ".xml")) { + try { + std::ifstream file(read_vpr_constraints_name); + void* context; + uxsd::load_vpr_constraints_xml(reader, context, read_vpr_constraints_name, file); + } catch (pugiutil::XmlError& e) { + vpr_throw(VPR_ERROR_ROUTE, read_vpr_constraints_name, e.line(), "%s", e.what()); } + } else { + VTR_LOG_WARN( + "VPR constraints file '%s' may be in incorrect format. " + "Expecting .xml format. Not reading file.\n", + read_vpr_constraints_name); } - VTR_LOG("Read in '%d' constraint file(s) successfully.\n", num_file_read); - freeTokens(tokens, num_tokens); //Update the floorplanning constraints in the floorplanning constraints context auto& floorplanning_ctx = g_vpr_ctx.mutable_floorplanning(); diff --git a/vpr/src/base/vpr_constraints_reader.h b/vpr/src/base/vpr_constraints_reader.h index 130baabc720..9740825836d 100644 --- a/vpr/src/base/vpr_constraints_reader.h +++ b/vpr/src/base/vpr_constraints_reader.h @@ -5,6 +5,6 @@ #ifndef VPR_CONSTRAINTS_READER_H_ #define VPR_CONSTRAINTS_READER_H_ -void load_vpr_constraints_files(const char* read_vpr_constraints_name); +void load_vpr_constraints_file(const char* read_vpr_constraints_name); #endif /* VPR_CONSTRAINTS_READER_H_ */ diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index 3f95b78b6e4..9ab4c3bd96f 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -2,7 +2,6 @@ #define VPR_CONSTRAINTS_SERIALIZER_H_ #include "region.h" -#include "route_constraint.h" #include "vpr_constraints.h" #include "partition.h" #include "partition_region.h" @@ -442,53 +441,21 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase::max_digits10); - void* context; - uxsd::write_vpr_constraints_xml(writer, context, fp); - } else { - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, - "Unknown extension on output %s", - file_name.c_str()); - } - } - return; -} - void write_vpr_floorplan_constraints(const char* file_name, int expand, bool subtile, int horizontal_partitions, int vertical_partitions) { VprConstraints constraints; diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index e22ac4d63a8..58d58e27226 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -316,7 +316,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } /* No clock network support yet; Does not support flatten rr_graph yet */ - check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, device_ctx.chan_width, GRAPH_UNIDIR, OPEN, false); + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, device_ctx.chan_width, GRAPH_UNIDIR, false); /************************************************************************ * Free all temp stucts diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index eac7d9d7087..b995c4da985 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2289,22 +2289,6 @@ bool is_inter_cluster_node(const RRGraphView& rr_graph_view, } } -void apply_route_constraints(VprConstraints& vpr_constraint) { - ClusteringContext& mutable_cluster_ctx = g_vpr_ctx.mutable_clustering(); - for (auto net_id : mutable_cluster_ctx.clb_nlist.nets()) { - std::string net_name = mutable_cluster_ctx.clb_nlist.net_name(net_id); - const RouteConstraint rc = vpr_constraint.get_route_constraint_by_net_name(net_name); - if (rc.is_valid()) { - mutable_cluster_ctx.clb_nlist.set_net_is_global(net_id, true); - if (rc.route_model() == "route") { - mutable_cluster_ctx.clb_nlist.set_net_is_ignored(net_id, false); - } else { - mutable_cluster_ctx.clb_nlist.set_net_is_ignored(net_id, true); - } - } - } -} - int get_rr_node_max_ptc(const RRGraphView& rr_graph_view, RRNodeId node_id, bool is_flat) { From 7bd0433b10450f8d52f5c23e062f4e4926f6b278 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 15:59:57 +0800 Subject: [PATCH 247/453] Update physical_types.h Add vib info --- libs/libarchfpga/src/physical_types.h | 90 +++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 1b4073dc851..cd7972487fb 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -372,6 +372,32 @@ struct t_grid_loc_def { // that come from a common definition. }; +struct t_vib_grid_loc_def { + t_vib_grid_loc_def(std::string block_type_val, int priority_val) + : block_type(block_type_val) + , priority(priority_val) + , x("0", "W-1", "max(w+1,W)", "w") //Fill in x direction, no repeat, incr by block width + , y("0", "H-1", "max(h+1,H)", "h") //Fill in y direction, no repeat, incr by block height + {} + + std::string block_type; //The block type name + + int priority = 0; //Priority of the specification. + // In case of conflicting specifications + // the largest priority wins. + + t_grid_loc_spec x; //Horizontal location specification + t_grid_loc_spec y; //Veritcal location specification + + // When 1 metadata tag is split among multiple t_grid_loc_def, one + // t_grid_loc_def is arbitrarily chosen to own the metadata, and the other + // t_grid_loc_def point to the owned version. + std::unique_ptr owned_meta; + t_metadata_dict* meta = nullptr; // Metadata for this location definition. This + // metadata may be shared with multiple grid_locs + // that come from a common definition. +}; + enum GridDefType { AUTO, FIXED @@ -381,6 +407,10 @@ struct t_layer_def { std::vector loc_defs; //The list of block location definitions for this layer specification }; +struct t_vib_layer_def { + std::vector loc_defs; //The list of block location definitions for this layer specification +}; + struct t_grid_def { GridDefType grid_type = GridDefType::AUTO; //The type of this grid specification @@ -394,6 +424,19 @@ struct t_grid_def { std::vector layers; }; +struct t_vib_grid_def { + GridDefType grid_type = GridDefType::AUTO; //The type of this grid specification + + std::string name = ""; //The name of this device + + int width = -1; //Fixed device width (only valid for grid_type == FIXED) + int height = -1; //Fixed device height (only valid for grid_type == FIXED) + + float aspect_ratio = 1.; //Aspect ratio for auto-sized devices (only valid for + //grid_type == AUTO) + std::vector layers; +}; + /************************* POWER ***********************************/ /* Global clock architecture */ @@ -1957,6 +2000,47 @@ struct t_noc_inf { std::string noc_router_tile_name; }; +/* for vib tag */ +struct t_seg_group { + std::string name; + int seg_index; + int track_num; +}; + +enum e_multistage_mux_from_or_to_type { + PB = 0, + SEGMENT, + MUX +}; + +struct t_from_or_to_inf { + std::string type_name; + e_multistage_mux_from_or_to_type from_type; //from_or_to_type + int type_index = -1; + int phy_pin_index = -1; + char seg_dir = ' '; + int seg_index = -1; +}; + +struct t_first_stage_mux_inf { + std::string mux_name; + std::vector froms; +}; + +struct t_second_stage_mux_inf : t_first_stage_mux_inf { + std::vector to; // for io type, port[pin] may map to several sinks +}; + +struct t_vib_inf { + std::string name; /* vib name */ + std::string pbtype_name; /* pbtype name of vib */ + int seg_group_num; /* seg group number of vib */ + int switch_idx; /* vib switch index */ + std::vector seg_groups; + std::vector first_stages; + std::vector second_stages; +}; + /* Detailed routing architecture */ struct t_arch { mutable vtr::string_internment strings; @@ -2030,10 +2114,16 @@ struct t_arch { std::vector grid_layouts; //Set of potential device layouts + std::vector vib_grid_layouts; + t_clock_arch_spec clock_arch; // Clock related data types // if we have an embedded NoC in the architecture, then we store it here t_noc_inf* noc = nullptr; + + // added for vib + bool is_vib_arch = false; + std::vector vib_infs; }; #endif From a0ecbce69e9b5dd35b27335eee7e76a89da26fd9 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:00:53 +0800 Subject: [PATCH 248/453] Update read_xml_arch_file.cpp Add vib info --- libs/libarchfpga/src/read_xml_arch_file.cpp | 765 ++++++++++++++++++++ 1 file changed, 765 insertions(+) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 69eb758735a..bcdee254405 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -224,8 +224,24 @@ static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pu static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data); static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::set& port_names, const pugiutil::loc_data& loc_data); static void ProcessLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data, int& num_of_avail_layer); + +/* Added for vib_layout*/ +static void ProcessVibLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data); + static t_grid_def ProcessGridLayout(vtr::string_internment* strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); + +/* Added for vib_layout*/ +static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment* strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); + static void ProcessBlockTypeLocs(t_grid_def& grid_def, int die_number, vtr::string_internment* strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); + +/* Added for vib_layout*/ +static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, + int die_number, + vtr::string_internment* strings, + pugi::xml_node layout_block_type_tag, + const pugiutil::loc_data& loc_data); + static int get_number_of_layers(pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data); static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data); static void ProcessComplexBlocks(vtr::string_internment* strings, pugi::xml_node Node, std::vector& LogicalBlockTypes, t_arch& arch, const bool timing_enabled, const pugiutil::loc_data& loc_data); @@ -301,6 +317,14 @@ static void update_router_info_in_arch(int router_id, bool router_updated_as_a_c static void verify_noc_topology(std::map>& routers_in_arch_info); +/* for vib arch */ +static void ProcessVibArch(pugi::xml_node Parent, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data); +static void ProcessVib(pugi::xml_node Vib_node, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data); +static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector segments, std::vector& first_stages, const pugiutil::loc_data& loc_data); +static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector segments, std::vector& second_stages, const pugiutil::loc_data& loc_data); +static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector segments, std::vector& froms); +void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); + /* * * @@ -361,6 +385,12 @@ void XmlReadArch(const char* ArchFile, Next = get_single_child(architecture, "layout", loc_data); ProcessLayout(Next, arch, loc_data, num_of_avail_layers); + /* Precess vib_layout */ + Next = get_single_child(architecture, "vib_layout", loc_data, ReqOpt::OPTIONAL); + if (Next) { + ProcessVibLayout(Next, arch, loc_data); + } + /* Process device */ Next = get_single_child(architecture, "device", loc_data); ProcessDevice(Next, arch, arch_def_fc, loc_data); @@ -403,6 +433,12 @@ void XmlReadArch(const char* ArchFile, loc_data); } + /* Process vib_arch */ + Next = get_single_child(architecture, "vib_arch", loc_data, ReqOpt::OPTIONAL); + if (Next) { + ProcessVibArch(Next, PhysicalTileTypes, arch, loc_data); + } + /* Process Clock Networks */ Next = get_single_child(architecture, "clocknetworks", loc_data, ReqOpt::OPTIONAL); if (Next) { @@ -5406,3 +5442,732 @@ static void verify_noc_topology(std::map>& routers_in_a return; } + +/* for vib arch*/ +static void ProcessVibArch(pugi::xml_node Parent, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data) { + pugi::xml_node Node; + //pugi::xml_node SubElem; + + arch->is_vib_arch = true; + int num_vibs = count_children(Parent, "vib", loc_data); + arch->vib_infs.reserve(num_vibs); + Node = get_first_child(Parent, "vib", loc_data); + + for (int i_vib = 0; i_vib < num_vibs; i_vib++) { + ProcessVib(Node, PhysicalTileTypes, arch, loc_data); + Node = Node.next_sibling(Node.name()); + } +} + +static void ProcessVib(pugi::xml_node Vib_node, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data) { + pugi::xml_node Node; + pugi::xml_node SubElem; + const char* tmp; + int itmp; + + t_vib_inf vib; + std::vector segments = arch->Segments; + t_arch_switch_inf* switches = arch->Switches; + + tmp = get_attribute(Vib_node, "name", loc_data).as_string(nullptr); + if (tmp) { + vib.name = tmp; + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Vib_node), + "No name specified for the vib!\n"); + } + + tmp = get_attribute(Vib_node, "pbtype_name", loc_data).as_string(nullptr); + if (tmp) { + vib.pbtype_name = tmp; + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Vib_node), + "No pbtype_name specified for the vib!\n"); + } + + vib.seg_group_num = get_attribute(Vib_node, "vib_seg_group", loc_data).as_int(1); + + tmp = get_attribute(Vib_node, "arch_vib_switch", loc_data).as_string(nullptr); + + if (tmp) { + for (int i_switch = 0; i_switch < arch->num_switches; i_switch++) { + if (!strcmp(tmp, switches[i_switch].name.c_str())) { + vib.switch_idx = i_switch; + break; + } + } + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Vib_node), + "No switch specified for the vib!\n"); + } + + expect_only_children(Vib_node, {"seg_group", "multistage_muxs"}, loc_data); + + int group_num = count_children(Vib_node, "seg_group", loc_data); + VTR_ASSERT(vib.seg_group_num == group_num); + vib.seg_groups.reserve(group_num); + Node = get_first_child(Vib_node, "seg_group", loc_data); + for (int i_group = 0; i_group < group_num; i_group++) { + t_seg_group seg_group; + + tmp = get_attribute(Node, "name", loc_data).as_string(nullptr); + + if (tmp) { + seg_group.name = tmp; + for (int i_seg = 0; i_seg < (int)segments.size(); i_seg++) { + if (segments[i_seg].name == seg_group.name) { + seg_group.seg_index = i_seg; + break; + } + } + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "No name specified for the vib seg group!\n"); + } + + itmp = get_attribute(Node, "track_nums", loc_data).as_int(); + if (itmp) { + seg_group.track_num = itmp; + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "No track_num specified for the vib seg group!\n"); + } + + vib.seg_groups.push_back(seg_group); + + Node = Node.next_sibling(Node.name()); + } + + Node = get_single_child(Vib_node, "multistage_muxs", loc_data); + expect_only_children(Node, {"first_stage", "second_stage"}, loc_data); + + SubElem = get_single_child(Node, "first_stage", loc_data); + if (SubElem) { + std::vector first_stages; + ProcessFirstStage(SubElem, PhysicalTileTypes, segments, first_stages, loc_data); + + for (auto first_stage : first_stages) { + vib.first_stages.push_back(first_stage); + } + + } + + SubElem = get_single_child(Node, "second_stage", loc_data); + if (SubElem) { + std::vector second_stages; + ProcessSecondStage(SubElem, PhysicalTileTypes, segments, second_stages, loc_data); + + for (auto second_stage : second_stages) { + vib.second_stages.push_back(second_stage); + } + + } + + arch->vib_infs.push_back(vib); +} + +static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector segments, std::vector& first_stages, const pugiutil::loc_data& loc_data) { + pugi::xml_node Node; + pugi::xml_node SubElem; + //pugi::xml_node Cur; + //const char* tmp; + + expect_only_children(Stage_node, {"mux"}, loc_data); + int num_mux = count_children(Stage_node, "mux", loc_data); + first_stages.reserve(num_mux); + Node = get_first_child(Stage_node, "mux", loc_data); + for (int i_mux = 0; i_mux < num_mux; i_mux++) { + t_first_stage_mux_inf first_stage_mux; + first_stage_mux.mux_name = get_attribute(Node, "name", loc_data).as_string(); + + expect_only_children(Node, {"from"}, loc_data); + SubElem = get_first_child(Node, "from", loc_data); + int from_num = count_children(Node, "from", loc_data); + for (int i_from = 0; i_from < from_num; i_from++) { + std::vector from_tokens = vtr::split(SubElem.child_value()); + ProcessFromOrToTokens(from_tokens, PhysicalTileTypes, segments, first_stage_mux.froms); + SubElem = SubElem.next_sibling(SubElem.name()); + } + first_stages.push_back(first_stage_mux); + + Node = Node.next_sibling(Node.name()); + } +} + +static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector segments, std::vector& second_stages, const pugiutil::loc_data& loc_data) { + pugi::xml_node Node; + pugi::xml_node SubElem; + //pugi::xml_node Cur; + //const char* tmp; + + expect_only_children(Stage_node, {"mux"}, loc_data); + int num_mux = count_children(Stage_node, "mux", loc_data); + second_stages.reserve(num_mux); + Node = get_first_child(Stage_node, "mux", loc_data); + for (int i_mux = 0; i_mux < num_mux; i_mux++) { + t_second_stage_mux_inf second_stage_mux; + second_stage_mux.mux_name = get_attribute(Node, "name", loc_data).as_string(); + + expect_only_children(Node, {"to", "from"}, loc_data); + + SubElem = get_first_child(Node, "to", loc_data); + int to_num = count_children(Node, "to", loc_data); + VTR_ASSERT(to_num == 1); + std::vector to_tokens = vtr::split(SubElem.child_value()); + VTR_ASSERT(to_tokens.size() == 1); + std::vector tos; + ProcessFromOrToTokens(to_tokens, PhysicalTileTypes, segments, tos); + for (auto to : tos) { + VTR_ASSERT(to.from_type == SEGMENT || to.from_type == PB); + second_stage_mux.to.push_back(to); + } + + + + + SubElem = get_first_child(Node, "from", loc_data); + int from_num = count_children(Node, "from", loc_data); + for (int i_from = 0; i_from < from_num; i_from++) { + std::vector from_tokens = vtr::split(SubElem.child_value()); + ProcessFromOrToTokens(from_tokens, PhysicalTileTypes, segments, second_stage_mux.froms); + SubElem = SubElem.next_sibling(SubElem.name()); + } + + second_stages.push_back(second_stage_mux); + + Node = Node.next_sibling(Node.name()); + } +} + +static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector segments, std::vector& froms) { + for (int i_token = 0; i_token < (int)Tokens.size(); i_token++) { + std::string Token = Tokens[i_token]; + const char* Token_char = Token.c_str(); + auto token = vtr::split(Token, "."); + if (token.size() == 1) { + t_from_or_to_inf from_inf; + from_inf.type_name = token[0]; + from_inf.from_type = MUX; + froms.push_back(from_inf); + } + else if (token.size() == 2) { + std::string from_type_name = token[0]; + e_multistage_mux_from_or_to_type from_type; + for (int i_phy_type = 0; i_phy_type < (int)PhysicalTileTypes.size(); i_phy_type++) { + if (from_type_name == PhysicalTileTypes[i_phy_type].name) { + from_type = PB; + int start_pin_index, end_pin_index; + char *pb_type_name, *port_name; + pb_type_name = nullptr; + port_name = nullptr; + pb_type_name = new char[strlen(Token_char)]; + port_name = new char[strlen(Token_char)]; + parse_pin_name((char*)Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); + + for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { + //int sub_tile_index = sub_tile.index; + int sub_tile_capacity = sub_tile.capacity.total(); + + int i_port = 0; + for (; i_port < (int)sub_tile.ports.size(); ++i_port) { + + if (!strcmp(sub_tile.ports[i_port].name, port_name)) { + if (start_pin_index == end_pin_index && start_pin_index < 0) { + start_pin_index = 0; + end_pin_index = sub_tile.ports[i_port].num_pins - 1; + } + start_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + end_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + break; + } + } + + if (i_port == (int)sub_tile.ports.size()) { + continue; + } + + for (int pin_num = start_pin_index; pin_num <= end_pin_index; ++pin_num) { + VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); + for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { + int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; + int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; + t_from_or_to_inf from_inf; + from_inf.type_name = from_type_name; + from_inf.from_type = from_type; + from_inf.type_index = i_phy_type; + from_inf.phy_pin_index = physical_pin_index; + froms.push_back(from_inf); + } + } + } + + } + } + for (int i_seg_type = 0; i_seg_type < (int)segments.size(); i_seg_type++) { + if (from_type_name == segments[i_seg_type].name) { + from_type = SEGMENT; + std::string from_detail = token[1]; + if (from_detail.length() >= 2) { + char dir = from_detail.c_str()[0]; + from_detail.erase(from_detail.begin()); + int seg_index = std::stoi(from_detail); + + t_from_or_to_inf from_inf; + from_inf.type_name = from_type_name; + from_inf.from_type = from_type; + from_inf.type_index = i_seg_type; + from_inf.seg_dir = dir; + from_inf.seg_index = seg_index; + froms.push_back(from_inf); + } + + break; + } + } + VTR_ASSERT(from_type == PB || from_type == SEGMENT); + + } + else { + std::string msg = vtr::string_fmt("Failed to parse vib mux from information '%s'", Token.c_str()); + throw ArchFpgaError(msg); + } + } +} + +void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name) { + /* Parses out the pb_type_name and port_name * + * If the start_pin_index and end_pin_index is specified, parse them too. * + * Return the values parsed by reference. */ + + char source_string[128]; + char* find_format = nullptr; + int ichar, match_count; + + // parse out the pb_type and port name, possibly pin_indices + find_format = strstr(src_string, "["); + if (find_format == nullptr) { + /* Format "pb_type_name.port_name" */ + *start_pin_index = *end_pin_index = -1; + + + strcpy(source_string, src_string); + + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s", pb_type_name, port_name); + if (match_count != 2) { + VTR_LOG_ERROR( + "Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + src_string); + exit(1); + } + } else { + /* Format "pb_type_name.port_name[end_pin_index:start_pin_index]" */ + strcpy(source_string, src_string); + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + //Need white space between the components when using %s with + //sscanf + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + if (source_string[ichar] == '[') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s %d:%d]", + pb_type_name, port_name, + end_pin_index, start_pin_index); + if (match_count != 4) { + match_count = sscanf(source_string, "%s %s %d]", + pb_type_name, port_name, + end_pin_index); + *start_pin_index = *end_pin_index; + if (match_count != 3) { + VTR_LOG_ERROR( + "Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + src_string); + exit(1); + } + } + if (*end_pin_index < 0 || *start_pin_index < 0) { + VTR_LOG_ERROR( + "Invalid pin - %s, the pin_index in " + "[end_pin_index:start_pin_index] should not be a negative value.\n", + src_string); + exit(1); + } + if (*end_pin_index < *start_pin_index) { + int temp; + temp = *end_pin_index; + *end_pin_index = *start_pin_index; + *start_pin_index = temp; + } + } +} + +/* Process vib layout */ +static void ProcessVibLayout(pugi::xml_node vib_layout_tag, t_arch* arch, const pugiutil::loc_data& loc_data) { + VTR_ASSERT(vib_layout_tag.name() == std::string("vib_layout")); + + size_t auto_layout_cnt = 0; + size_t fixed_layout_cnt = 0; + for (auto layout_type_tag : vib_layout_tag.children()) { + if (layout_type_tag.name() == std::string("auto_layout")) { + ++auto_layout_cnt; + } else if (layout_type_tag.name() == std::string("fixed_layout")) { + ++fixed_layout_cnt; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag), + "Unexpected tag type '<%s>', expected '' or ''", layout_type_tag.name()); + } + } + + if (auto_layout_cnt == 0 && fixed_layout_cnt == 0) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(vib_layout_tag), + "Expected either an or tag"); + } + if (auto_layout_cnt > 1) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(vib_layout_tag), + "Expected at most one tag"); + } + VTR_ASSERT_MSG(auto_layout_cnt == 0 || auto_layout_cnt == 1, " may appear at most once"); + + // for (auto vib_layout_type_tag : vib_layout_tag.children()) { + // for (auto grid_layout : arch->grid_layouts) { + // std::string layout_name = grid_layout.name; + // } + // } + + int num_of_avail_layer; + + for (auto vib_layout_type_tag : vib_layout_tag.children()) { + t_vib_grid_def grid_def = ProcessVibGridLayout(&arch->strings, vib_layout_type_tag, loc_data, arch, num_of_avail_layer); + + arch->vib_grid_layouts.emplace_back(std::move(grid_def)); + } + +} + +static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment* strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer) { + t_vib_grid_def grid_def; + num_of_avail_layer = get_number_of_layers(layout_type_tag, loc_data); + bool has_layer = layout_type_tag.child("layer"); + + //Determine the grid specification type + if (layout_type_tag.name() == std::string("auto_layout")) { + //expect_only_attributes(layout_type_tag, {"aspect_ratio"}, loc_data); + + grid_def.grid_type = GridDefType::AUTO; + grid_def.name = "auto"; + + for (size_t i = 0;i < arch->grid_layouts.size(); i++) { + if (arch->grid_layouts[i].name == grid_def.name) { + grid_def.aspect_ratio = arch->grid_layouts[i].aspect_ratio; + } + } + //grid_def.aspect_ratio = get_attribute(layout_type_tag, "aspect_ratio", loc_data, ReqOpt::OPTIONAL).as_float(1.); + + } else if (layout_type_tag.name() == std::string("fixed_layout")) { + expect_only_attributes(layout_type_tag, {"name"}, loc_data); + + grid_def.grid_type = GridDefType::FIXED; + //grid_def.width = get_attribute(layout_type_tag, "width", loc_data).as_int(); + //grid_def.height = get_attribute(layout_type_tag, "height", loc_data).as_int(); + std::string name = get_attribute(layout_type_tag, "name", loc_data).value(); + + if (name == "auto") { + //We name as 'auto', so don't allow a user to specify it + archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag), + "The name '%s' is reserved for auto-sized layouts; please choose another name"); + } + + for (size_t i = 0; i < arch->grid_layouts.size(); i++) { + if (arch->grid_layouts[i].name == name) { + grid_def.width = arch->grid_layouts[i].width; + grid_def.height = arch->grid_layouts[i].height; + } + } + grid_def.name = name; + + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag), + "Unexpected tag '<%s>'. Expected '' or ''.", + layout_type_tag.name()); + } + + grid_def.layers.resize(num_of_avail_layer); + arch->layer_global_routing.resize(num_of_avail_layer); + //No layer tag is specified (only one die is specified in the arch file) + //Need to process layout_type_tag children to get block types locations in the grid + if (has_layer) { + std::set seen_die_numbers; //Check that die numbers in the specific layout tag are unique + //One or more than one layer tag is specified + auto layer_tag_specified = layout_type_tag.children("layer"); + for (auto layer_child : layer_tag_specified) { + int die_number; + bool has_global_routing; + //More than one layer tag is specified, meaning that multi-die FPGA is specified in the arch file + //Need to process each tag children to get block types locations for each grid + die_number = get_attribute(layer_child, "die", loc_data).as_int(0); + has_global_routing = get_attribute(layer_child, "has_prog_routing", loc_data, ReqOpt::OPTIONAL).as_bool(true); + arch->layer_global_routing.at(die_number) = has_global_routing; + VTR_ASSERT(die_number >= 0 && die_number < num_of_avail_layer); + auto insert_res = seen_die_numbers.insert(die_number); + VTR_ASSERT_MSG(insert_res.second, "Two different layers with a same die number may have been specified in the Architecture file"); + ProcessVibBlockTypeLocs(grid_def, die_number, strings, layer_child, loc_data); + } + } else { + //if only one die is available, then global routing resources must exist in that die + int die_number = 0; + arch->layer_global_routing.at(die_number) = true; + ProcessVibBlockTypeLocs(grid_def, die_number, strings, layout_type_tag, loc_data); + } + return grid_def; +} + +static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, + int die_number, + vtr::string_internment* strings, + pugi::xml_node layout_block_type_tag, + const pugiutil::loc_data& loc_data) { + //Process all the block location specifications + for (auto loc_spec_tag : layout_block_type_tag.children()) { + auto loc_type = loc_spec_tag.name(); + auto type_name = get_attribute(loc_spec_tag, "type", loc_data).value(); + int priority = get_attribute(loc_spec_tag, "priority", loc_data).as_int(); + t_metadata_dict meta = ProcessMetadata(strings, loc_spec_tag, loc_data); + + if (loc_type == std::string("perimeter")) { + expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); + + //The edges + t_vib_grid_loc_def left_edge(type_name, priority); //Including corners + left_edge.x.start_expr = "0"; + left_edge.x.end_expr = "0"; + left_edge.y.start_expr = "0"; + left_edge.y.end_expr = "H - 1"; + + t_vib_grid_loc_def right_edge(type_name, priority); //Including corners + right_edge.x.start_expr = "W - 1"; + right_edge.x.end_expr = "W - 1"; + right_edge.y.start_expr = "0"; + right_edge.y.end_expr = "H - 1"; + + t_vib_grid_loc_def bottom_edge(type_name, priority); //Exclucing corners + bottom_edge.x.start_expr = "1"; + bottom_edge.x.end_expr = "W - 2"; + bottom_edge.y.start_expr = "0"; + bottom_edge.y.end_expr = "0"; + + t_vib_grid_loc_def top_edge(type_name, priority); //Excluding corners + top_edge.x.start_expr = "1"; + top_edge.x.end_expr = "W - 2"; + top_edge.y.start_expr = "H - 1"; + top_edge.y.end_expr = "H - 1"; + + left_edge.owned_meta = std::make_unique(meta); + left_edge.meta = left_edge.owned_meta.get(); + right_edge.meta = left_edge.owned_meta.get(); + top_edge.meta = left_edge.owned_meta.get(); + bottom_edge.meta = left_edge.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(left_edge)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(right_edge)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_edge)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_edge)); + + } else if (loc_type == std::string("corners")) { + expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); + + //The corners + t_vib_grid_loc_def bottom_left(type_name, priority); + bottom_left.x.start_expr = "0"; + bottom_left.x.end_expr = "0"; + bottom_left.y.start_expr = "0"; + bottom_left.y.end_expr = "0"; + + t_vib_grid_loc_def top_left(type_name, priority); + top_left.x.start_expr = "0"; + top_left.x.end_expr = "0"; + top_left.y.start_expr = "H-1"; + top_left.y.end_expr = "H-1"; + + t_vib_grid_loc_def bottom_right(type_name, priority); + bottom_right.x.start_expr = "W-1"; + bottom_right.x.end_expr = "W-1"; + bottom_right.y.start_expr = "0"; + bottom_right.y.end_expr = "0"; + + t_vib_grid_loc_def top_right(type_name, priority); + top_right.x.start_expr = "W-1"; + top_right.x.end_expr = "W-1"; + top_right.y.start_expr = "H-1"; + top_right.y.end_expr = "H-1"; + + bottom_left.owned_meta = std::make_unique(meta); + bottom_left.meta = bottom_left.owned_meta.get(); + top_left.meta = bottom_left.owned_meta.get(); + bottom_right.meta = bottom_left.owned_meta.get(); + top_right.meta = bottom_left.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_left)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_left)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_right)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_right)); + + } else if (loc_type == std::string("fill")) { + expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); + + t_vib_grid_loc_def fill(type_name, priority); + fill.x.start_expr = "0"; + fill.x.end_expr = "W - 1"; + fill.y.start_expr = "0"; + fill.y.end_expr = "H - 1"; + + fill.owned_meta = std::make_unique(meta); + fill.meta = fill.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(fill)); + + } else if (loc_type == std::string("single")) { + expect_only_attributes(loc_spec_tag, {"type", "priority", "x", "y"}, loc_data); + + t_vib_grid_loc_def single(type_name, priority); + single.x.start_expr = get_attribute(loc_spec_tag, "x", loc_data).value(); + single.y.start_expr = get_attribute(loc_spec_tag, "y", loc_data).value(); + single.x.end_expr = single.x.start_expr + " + w - 1"; + single.y.end_expr = single.y.start_expr + " + h - 1"; + + single.owned_meta = std::make_unique(meta); + single.meta = single.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(single)); + + } else if (loc_type == std::string("col")) { + expect_only_attributes(loc_spec_tag, {"type", "priority", "startx", "repeatx", "starty", "incry"}, loc_data); + + t_vib_grid_loc_def col(type_name, priority); + + auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data); + + col.x.start_expr = startx_attr.value(); + col.x.end_expr = startx_attr.value() + std::string(" + w - 1"); //end is inclusive so need to include block width + + auto repeat_attr = get_attribute(loc_spec_tag, "repeatx", loc_data, ReqOpt::OPTIONAL); + if (repeat_attr) { + col.x.repeat_expr = repeat_attr.value(); + } + + auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data, ReqOpt::OPTIONAL); + if (starty_attr) { + col.y.start_expr = starty_attr.value(); + } + + auto incry_attr = get_attribute(loc_spec_tag, "incry", loc_data, ReqOpt::OPTIONAL); + if (incry_attr) { + col.y.incr_expr = incry_attr.value(); + } + + col.owned_meta = std::make_unique(meta); + col.meta = col.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(col)); + + } else if (loc_type == std::string("row")) { + expect_only_attributes(loc_spec_tag, {"type", "priority", "starty", "repeaty", "startx", "incrx"}, loc_data); + + t_vib_grid_loc_def row(type_name, priority); + + auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data); + + row.y.start_expr = starty_attr.value(); + row.y.end_expr = starty_attr.value() + std::string(" + h - 1"); //end is inclusive so need to include block height + + auto repeat_attr = get_attribute(loc_spec_tag, "repeaty", loc_data, ReqOpt::OPTIONAL); + if (repeat_attr) { + row.y.repeat_expr = repeat_attr.value(); + } + + auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data, ReqOpt::OPTIONAL); + if (startx_attr) { + row.x.start_expr = startx_attr.value(); + } + + auto incrx_attr = get_attribute(loc_spec_tag, "incrx", loc_data, ReqOpt::OPTIONAL); + if (incrx_attr) { + row.x.incr_expr = incrx_attr.value(); + } + + row.owned_meta = std::make_unique(meta); + row.meta = row.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(row)); + } else if (loc_type == std::string("region")) { + expect_only_attributes(loc_spec_tag, + {"type", "priority", + "startx", "endx", "repeatx", "incrx", + "starty", "endy", "repeaty", "incry"}, + loc_data); + t_vib_grid_loc_def region(type_name, priority); + + auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data, ReqOpt::OPTIONAL); + if (startx_attr) { + region.x.start_expr = startx_attr.value(); + } + + auto endx_attr = get_attribute(loc_spec_tag, "endx", loc_data, ReqOpt::OPTIONAL); + if (endx_attr) { + region.x.end_expr = endx_attr.value(); + } + + auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data, ReqOpt::OPTIONAL); + if (starty_attr) { + region.y.start_expr = starty_attr.value(); + } + + auto endy_attr = get_attribute(loc_spec_tag, "endy", loc_data, ReqOpt::OPTIONAL); + if (endy_attr) { + region.y.end_expr = endy_attr.value(); + } + + auto repeatx_attr = get_attribute(loc_spec_tag, "repeatx", loc_data, ReqOpt::OPTIONAL); + if (repeatx_attr) { + region.x.repeat_expr = repeatx_attr.value(); + } + + auto repeaty_attr = get_attribute(loc_spec_tag, "repeaty", loc_data, ReqOpt::OPTIONAL); + if (repeaty_attr) { + region.y.repeat_expr = repeaty_attr.value(); + } + + auto incrx_attr = get_attribute(loc_spec_tag, "incrx", loc_data, ReqOpt::OPTIONAL); + if (incrx_attr) { + region.x.incr_expr = incrx_attr.value(); + } + + auto incry_attr = get_attribute(loc_spec_tag, "incry", loc_data, ReqOpt::OPTIONAL); + if (incry_attr) { + region.y.incr_expr = incry_attr.value(); + } + + region.owned_meta = std::make_unique(meta); + region.meta = region.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(region)); + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(loc_spec_tag), + "Unrecognized grid location specification type '%s'\n", loc_type); + } + } +} From 16ab23888a2e2f39f1fdf2311ae379827dddec6e Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:09:21 +0800 Subject: [PATCH 249/453] Update SetupGrid.cpp Add vib info --- vpr/src/base/SetupGrid.cpp | 403 +++++++++++++++++++++++++++++++++++++ 1 file changed, 403 insertions(+) diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index 11ac2e52694..c45c92a3fae 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -33,6 +33,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); static bool grid_satisfies_instance_counts(const DeviceGrid& grid, const std::map& instance_counts, float maximum_utilization); static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, const std::vector& limiting_resources = std::vector()); +static vtr::NdMatrix build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range = true); static void CheckGrid(const DeviceGrid& grid); @@ -45,6 +46,15 @@ static void set_grid_block_type(int priority, vtr::NdMatrix& grid_priorities, const t_metadata_dict* meta); +static void set_vib_grid_block_type(int priority, + const t_vib_inf* type, + int layer_num, + size_t x_root, + size_t y_root, + vtr::NdMatrix& vib_grid, + vtr::NdMatrix& grid_priorities, + const t_metadata_dict* meta); + ///@brief Create the device grid based on resource requirements DeviceGrid create_device_grid(std::string layout_name, const std::vector& grid_layouts, const std::map& minimum_instance_counts, float target_device_utilization) { if (layout_name == "auto") { @@ -138,6 +148,37 @@ DeviceGrid create_device_grid(std::string layout_name, const std::vector create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts) { + if (layout_name == "auto") { + //We do not support auto layout now + // + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); + + } else { + //Use the specified device + + //Find the matching grid definition + auto cmp = [&](const t_vib_grid_def& grid_def) { + return grid_def.name == layout_name; + }; + + auto iter = std::find_if(vib_grid_layouts.begin(), vib_grid_layouts.end(), cmp); + if (iter == vib_grid_layouts.end()) { + //Not found + std::string valid_names; + for (size_t i = 0; i < vib_grid_layouts.size(); ++i) { + if (i != 0) { + valid_names += ", "; + } + valid_names += "'" + vib_grid_layouts[i].name + "'"; + } + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find grid layout named '%s' (valid grid layouts: %s)\n", layout_name.c_str(), valid_names.c_str()); + } + + return build_vib_device_grid(*iter, iter->width, iter->height); + } +} + /** * @brief Create a device grid which satisfies the minimum block counts * @@ -548,6 +589,227 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt return device_grid; } +///@brief Build the specified device grid +static vtr::NdMatrix build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range) { + if (grid_def.grid_type == GridDefType::FIXED) { + if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "Requested grid size (%zu%zu) does not match fixed device size (%dx%d)", + grid_width, grid_height, grid_def.width, grid_def.height); + } + } + + auto& device_ctx = g_vpr_ctx.device(); + + //Initialize the grid and each location priority based on available dies in the architecture file + vtr::NdMatrix vib_grid; + vtr::NdMatrix grid_priorities; + int num_layers = (int)grid_def.layers.size(); + vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); + //Track the current priority for each grid location + // Note that we initialize it to the lowest (i.e. most negative) possible value, so + // any user-specified priority will override the default empty grid + grid_priorities.resize(std::array{(size_t)num_layers, grid_width, grid_height}, std::numeric_limits::lowest()); + + //Initialize the device to all empty blocks + const t_vib_inf* empty_type = nullptr; + //VTR_ASSERT(empty_type != nullptr); + for (int layer = 0; layer < num_layers; ++layer) { + for (size_t x = 0; x < grid_width; ++x) { + for (size_t y = 0; y < grid_height; ++y) { + set_vib_grid_block_type(std::numeric_limits::lowest() + 1, //+1 so it overrides without warning + empty_type, + layer, x, y, + vib_grid, grid_priorities, + /*meta=*/nullptr); + } + } + } + + FormulaParser p; + std::set seen_types; + for (int layer = 0; layer < num_layers; layer++) { + for (const auto& grid_loc_def : grid_def.layers.at(layer).loc_defs) { + //Fill in the block types according to the specification + //auto type = find_tile_type_by_name(grid_loc_def.block_type, device_ctx.physical_tile_types); + const t_vib_inf* type = nullptr; + for (size_t vib_type = 0; vib_type < device_ctx.arch->vib_infs.size(); vib_type++) { + if (grid_loc_def.block_type == device_ctx.arch->vib_infs[vib_type].name) { + type = &device_ctx.arch->vib_infs[vib_type]; + break; + } + } + + if (!type) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Failed to find block type '%s' for grid location specification", + grid_loc_def.block_type.c_str()); + } + + seen_types.insert(type); + + t_formula_data vars; + vars.set_var_value("W", grid_width); + vars.set_var_value("H", grid_height); + vars.set_var_value("w", 1); + vars.set_var_value("h", 1); + + //Load the x specification + auto& xspec = grid_loc_def.x; + + VTR_ASSERT_MSG(!xspec.start_expr.empty(), "x start position must be specified"); + VTR_ASSERT_MSG(!xspec.end_expr.empty(), "x end position must be specified"); + VTR_ASSERT_MSG(!xspec.incr_expr.empty(), "x increment must be specified"); + VTR_ASSERT_MSG(!xspec.repeat_expr.empty(), "x repeat must be specified"); + + size_t startx = p.parse_formula(xspec.start_expr, vars); + size_t endx = p.parse_formula(xspec.end_expr, vars); + size_t incrx = p.parse_formula(xspec.incr_expr, vars); + size_t repeatx = p.parse_formula(xspec.repeat_expr, vars); + + //Load the y specification + auto& yspec = grid_loc_def.y; + + VTR_ASSERT_MSG(!yspec.start_expr.empty(), "y start position must be specified"); + VTR_ASSERT_MSG(!yspec.end_expr.empty(), "y end position must be specified"); + VTR_ASSERT_MSG(!yspec.incr_expr.empty(), "y increment must be specified"); + VTR_ASSERT_MSG(!yspec.repeat_expr.empty(), "y repeat must be specified"); + + size_t starty = p.parse_formula(yspec.start_expr, vars); + size_t endy = p.parse_formula(yspec.end_expr, vars); + size_t incry = p.parse_formula(yspec.incr_expr, vars); + size_t repeaty = p.parse_formula(yspec.repeat_expr, vars); + + //Check start against the device dimensions + // Start locations outside the device will never create block instances + if (startx > grid_width - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", + type->name, xspec.start_expr.c_str(), startx, 0, grid_width - 1); + } + continue; //No instances will be created + } + + if (starty > grid_height - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", + type->name, yspec.start_expr.c_str(), starty, 0, grid_height - 1); + } + continue; //No instances will be created + } + + //Check end against the device dimensions + if (endx > grid_width - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", + type->name, xspec.end_expr.c_str(), endx, 0, grid_width - 1); + } + } + + if (endy > grid_height - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", + type->name, yspec.end_expr.c_str(), endy, 0, grid_height - 1); + } + } + + //The end must fall after (or equal) to the start + if (endx < startx) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", + xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->name); + } + + if (endy < starty) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", + yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->name); + } + + //The minimum increment is the block dimension + //VTR_ASSERT(type->width > 0); + if (incrx < 1/*size_t(type->width)*/) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification incrx for block type '%s' must be at least" + " block width (%d) to avoid overlapping instances (was %s = %d)", + type->name, 1, xspec.incr_expr.c_str(), incrx); + } + + //VTR_ASSERT(type->height > 0); + if (incry < 1/*size_t(type->height)*/) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification incry for block type '%s' must be at least" + " block height (%d) to avoid overlapping instances (was %s = %d)", + type->name, 1, yspec.incr_expr.c_str(), incry); + } + + //The minimum repeat is the region dimension + size_t region_width = endx - startx + 1; //+1 since start/end are both inclusive + if (repeatx < region_width) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification repeatx for block type '%s' must be at least" + " the region width (%d) to avoid overlapping instances (was %s = %d)", + type->name, region_width, xspec.repeat_expr.c_str(), repeatx); + } + + size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive + if (repeaty < region_height) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification repeaty for block type '%s' must be at least" + " the region height (%d) to avoid overlapping instances (was %s = %d)", + type->name, region_height, xspec.repeat_expr.c_str(), repeaty); + } + + //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", + // type->name, grid_loc_def.priority, + // xspec.start_expr.c_str(), startx, xspec.end_expr.c_str(), endx, + // yspec.start_expr.c_str(), starty, yspec.end_expr.c_str(), endy); + + size_t x_end = 0; + for (size_t kx = 0; x_end < grid_width; ++kx) { //Repeat in x direction + size_t x_start = startx + kx * repeatx; + x_end = endx + kx * repeatx; + + size_t y_end = 0; + for (size_t ky = 0; y_end < grid_height; ++ky) { //Repeat in y direction + size_t y_start = starty + ky * repeaty; + y_end = endy + ky * repeaty; + + size_t x_max = std::min(x_end, grid_width - 1); + size_t y_max = std::min(y_end, grid_height - 1); + + //Fill in the region + for (size_t x = x_start; x <= x_max; x += incrx) { + for (size_t y = y_start; y <= y_max; y += incry) { + set_vib_grid_block_type(grid_loc_def.priority, + type, + layer, x, y, + vib_grid, grid_priorities, + grid_loc_def.meta); + } + } + } + } + } + } + + //Warn if any types were not specified in the grid layout + // for (auto const& type : device_ctx.physical_tile_types) { + // if (&type == empty_type) continue; //Don't worry if empty hasn't been specified + + // if (!seen_types.count(&type)) { + // VTR_LOG_WARN("Block type '%s' was not specified in device grid layout\n", + // type.name); + // } + // } + + // auto device_grid = DeviceGrid(grid_def.name, grid, limiting_resources); + + // CheckGrid(device_grid); + + return vib_grid; +} + static void set_grid_block_type(int priority, const t_physical_tile_type* type, int layer_num, @@ -688,6 +950,147 @@ static void set_grid_block_type(int priority, } } +static void set_vib_grid_block_type(int priority, + const t_vib_inf* type, + int layer_num, + size_t x_root, + size_t y_root, + vtr::NdMatrix& vib_grid, + vtr::NdMatrix& grid_priorities, + const t_metadata_dict* meta) { + struct TypeLocation { + TypeLocation(size_t x_val, size_t y_val, const t_vib_inf* type_val, int priority_val) + : x(x_val) + , y(y_val) + , type(type_val) + , priority(priority_val) {} + size_t x; + size_t y; + const t_vib_inf* type; + int priority; + + bool operator<(const TypeLocation& rhs) const { + return x < rhs.x || y < rhs.y || type < rhs.type; + } + }; + + //Collect locations effected by this block + std::set target_locations; + for (size_t x = x_root; x < x_root + 1; ++x) { + for (size_t y = y_root; y < y_root + 1; ++y) { + target_locations.insert(TypeLocation(x, y, vib_grid[layer_num][x][y], grid_priorities[layer_num][x][y])); + } + } + + //Record the highest priority of all effected locations + auto iter = target_locations.begin(); + TypeLocation max_priority_type_loc = *iter; + for (; iter != target_locations.end(); ++iter) { + if (iter->priority > max_priority_type_loc.priority) { + max_priority_type_loc = *iter; + } + } + + if (priority < max_priority_type_loc.priority) { + //Lower priority, do not override +#ifdef VERBOSE + VTR_LOG("Not creating block '%s' at (%zu,%zu) since overlaps block '%s' at (%zu,%zu) with higher priority (%d > %d)\n", + type->name, x_root, y_root, max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, + max_priority_type_loc.priority, priority); +#endif + return; + } + + if (priority == max_priority_type_loc.priority) { + //Ambiguous case where current grid block and new specification have equal priority + // + //We arbitrarily decide to take the 'last applied' wins approach, and warn the user + //about the potential ambiguity + VTR_LOG_WARN( + "Ambiguous block type specification at grid location (%zu,%zu)." + " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." + " The last specification will apply.\n", + x_root, y_root, + max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, + priority, type->name); + } + + //Mark all the grid tiles 'covered' by this block with the appropriate type + //and width/height offsets + std::set root_blocks_to_rip_up; + auto& device_ctx = g_vpr_ctx.device(); + for (size_t x = x_root; x < x_root + 1; ++x) { + VTR_ASSERT(x < vib_grid.end_index(1)); + + //size_t x_offset = x - x_root; + for (size_t y = y_root; y < y_root + 1; ++y) { + VTR_ASSERT(y < vib_grid.end_index(2)); + //size_t y_offset = y - y_root; + + auto& grid_tile = vib_grid[layer_num][x][y]; + VTR_ASSERT(grid_priorities[layer_num][x][y] <= priority); + + if (grid_tile != nullptr + //&& grid_tile.type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE + ) { + //We are overriding a non-empty block, we need to be careful + //to ensure we remove any blocks which will be invalidated when we + //overwrite part of their locations + + size_t orig_root_x = x; + size_t orig_root_y = y; + + root_blocks_to_rip_up.insert(TypeLocation(orig_root_x, + orig_root_y, + vib_grid[layer_num][x][y], + grid_priorities[layer_num][x][y])); + } + + vib_grid[layer_num][x][y] = type; + //grid[layer_num][x][y].width_offset = x_offset; + //grid[layer_num][x][y].height_offset = y_offset; + //grid[layer_num][x][y].meta = meta; + + grid_priorities[layer_num][x][y] = priority; + } + } + + //Rip-up any invalidated blocks + for (auto invalidated_root : root_blocks_to_rip_up) { + //Mark all the grid locations used by this root block as empty + for (size_t x = invalidated_root.x; x < invalidated_root.x + 1; ++x) { + int x_offset = x - invalidated_root.x; + for (size_t y = invalidated_root.y; y < invalidated_root.y + 1; ++y) { + int y_offset = y - invalidated_root.y; + + if (vib_grid[layer_num][x][y] == invalidated_root.type + && 0 == x_offset + && 0 == y_offset) { + //This is a left-over invalidated block, mark as empty + // Note: that we explicitly check the type and offsets, since the original block + // may have been completely overwritten, and we don't want to change anything + // in that case + //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->width == 1); + //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->height == 1); + +#ifdef VERBOSE + VTR_LOG("Ripping up block '%s' at (%d,%d) offset (%d,%d). Overlapped by '%s' at (%d,%d)\n", + invalidated_root.type->name, invalidated_root.x, invalidated_root.y, + x_offset, y_offset, + type->name, x_root, y_root); +#endif + + vib_grid[layer_num][x][y] = nullptr; + //grid[layer_num][x][y].width_offset = 0; + //grid[layer_num][x][y].height_offset = 0; + + grid_priorities[layer_num][x][y] = std::numeric_limits::lowest(); + } + } + } + } +} + ///@brief Check grid is valid static void CheckGrid(const DeviceGrid& grid) { for (int layer_num = 0; layer_num < grid.get_num_layers(); layer_num++) { //Check each die individually From 35cccdc2e0e2e1beaf6122637787d549481fc0fd Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:10:22 +0800 Subject: [PATCH 250/453] Update vpr_context.h --- vpr/src/base/vpr_context.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 448667c7f2e..a77f7bb844c 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -149,6 +149,9 @@ struct DeviceContext : public Context { * This represents the physical layout of the device. To get the physical tile at each location (layer_num, x, y) the helper functions in this data structure should be used. */ DeviceGrid grid; + + vtr::NdMatrix vib_grid; + /* * Empty types */ From 7af8feb0b84f2a2481046f90219b89bc805fae23 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:11:10 +0800 Subject: [PATCH 251/453] Update SetupGrid.h --- vpr/src/base/SetupGrid.h | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index cfde1e523d8..0a8e924bae0 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -20,6 +20,7 @@ DeviceGrid create_device_grid(std::string layout_name, ///@brief Find the device close in size to the specified dimensions DeviceGrid create_device_grid(std::string layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); +vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts); /** * @brief Calculate the device utilization From 56a7e686aba0e9f3fa8e771ca15d382c01a1ef4f Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:12:01 +0800 Subject: [PATCH 252/453] Update vpr_api.cpp --- vpr/src/base/vpr_api.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 15afc7e4e11..251b917c3bf 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -459,6 +459,9 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { //Build the device float target_device_utilization = vpr_setup.PackerOpts.target_device_utilization; device_ctx.grid = create_device_grid(vpr_setup.device_layout, Arch.grid_layouts, num_type_instances, target_device_utilization); + if (Arch.is_vib_arch) { + device_ctx.vib_grid = create_vib_device_grid(vpr_setup.device_layout, Arch.vib_grid_layouts); + } VTR_ASSERT_MSG(device_ctx.grid.get_num_layers() <= MAX_NUM_LAYERS, "Number of layers should be less than MAX_NUM_LAYERS. If you need more layers, please increase the value of MAX_NUM_LAYERS in vpr_types.h"); From 98e7992dbb2d4caa9c5d6f54dbe71425f81b1461 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:14:05 +0800 Subject: [PATCH 253/453] Update tileable_rr_graph_edge_builder.cpp --- .../tileable_rr_graph_edge_builder.cpp | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index bb1407bdbdd..b74d8768e26 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -105,6 +105,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, @@ -119,7 +120,33 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const bool& opin2all_sides, const bool& concat_wire, const bool& wire_opposite_side, - const RRSwitchId& delayless_switch) { + const RRSwitchId& delayless_switch, + const bool& is_vib_arch) { + /* Create map from medium mux name to index */ + std::vector>>> medium_mux_name2medium_index; + + if (is_vib_arch) { + medium_mux_name2medium_index.resize(vib_grid.dim_size(0)); + for (size_t i_layer = 0; i_layer < vib_grid.dim_size(0); i_layer++) { + medium_mux_name2medium_index[i_layer].resize(vib_grid.dim_size(1)); + + for (size_t ix = 0; ix < vib_grid.dim_size(1); ix++) { + medium_mux_name2medium_index[i_layer][ix].resize(vib_grid.dim_size(2)); + + for (size_t iy = 0; iy < vib_grid.dim_size(2); iy++) { + std::map mux_name_map; + + for (size_t i_mux; i_mux < vib_grid[i_layer][ix][iy]->first_stages.size(); i_mux++) { + mux_name_map.emplace(vib_grid[i_layer][ix][iy]->first_stages[i_mux].mux_name, i_mux); + } + medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; + } + } + } + + } + + size_t num_edges_to_create = 0; /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); From 5b32f84fde634099f4a51f946711fbb0fdbd3e88 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:14:49 +0800 Subject: [PATCH 254/453] Update tileable_rr_graph_builder.cpp --- .../tileable_rr_graph_builder.cpp | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 2a9852d3328..97a968e4123 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -155,17 +155,22 @@ void build_tileable_unidir_rr_graph(const std::vector& typ std::vector segment_inf_x = get_parallel_segs(segment_inf, segment_index_map, X_AXIS, true); std::vector segment_inf_y = get_parallel_segs(segment_inf, segment_index_map, Y_AXIS, true); + /* Get vib grid */ + const auto& vib_grid = device_ctx.vib_grid; + const bool is_vib_arch = device_ctx.arch->is_vib_arch; + /************************ * Allocate the rr_nodes ************************/ alloc_tileable_rr_graph_nodes(device_ctx.rr_graph_builder, rr_node_driver_switches, - grids, 0, + grids, vib_grid, 0, device_chan_width, segment_inf_x, segment_inf_y, device_grid_annotation, shrink_boundary, - through_channel); + through_channel, + is_vib_arch); /************************ * Create all the rr_nodes @@ -175,7 +180,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ rr_node_driver_switches, rr_node_track_ids, device_ctx.rr_rc_data, - grids, 0, + grids, vib_grid, 0, device_chan_width, segment_inf_x, segment_inf_y, segment_index_map, @@ -183,7 +188,8 @@ void build_tileable_unidir_rr_graph(const std::vector& typ delayless_rr_switch, device_grid_annotation, shrink_boundary, - through_channel); + through_channel, + is_vib_arch); /************************************************************************ * Create the connectivity of OPINs @@ -251,14 +257,15 @@ void build_tileable_unidir_rr_graph(const std::vector& typ build_rr_graph_edges(device_ctx.rr_graph, device_ctx.rr_graph_builder, rr_node_driver_switches, - grids, 0, + grids, vib_grid, 0, device_chan_width, segment_inf, segment_inf_x, segment_inf_y, Fc_in, Fc_out, sb_type, Fs, sb_subtype, subFs, opin2all_sides, concat_wire, wire_opposite_side, - delayless_rr_switch); + delayless_rr_switch, + is_vib_arch); /************************************************************************ * Build direction connection lists From 87d4b59eceda26534808536d615f54ca4c2a53dc Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:15:34 +0800 Subject: [PATCH 255/453] Update tileable_rr_graph_edge_builder.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 56489089dbf..379a5805ef4 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -25,6 +25,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, @@ -39,7 +40,8 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const bool& opin2all_sides, const bool& concat_wire, const bool& wire_opposite_side, - const RRSwitchId& delayless_switch); + const RRSwitchId& delayless_switch, + const bool& is_vib_arch); void build_rr_graph_direct_connections(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, From c23795c41d32c378a6016aa75d85e10ed7daa1a8 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:16:17 +0800 Subject: [PATCH 256/453] Update tileable_rr_graph_node_builder.cpp --- .../tileable_rr_graph_node_builder.cpp | 125 ++++++++++++++++-- 1 file changed, 117 insertions(+), 8 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 4b417fca325..914a77f28af 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -80,6 +80,42 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, return num_grid_rr_nodes; } +static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, + const size_t& layer) { + size_t num_grid_rr_nodes = 0; + + VTR_ASSERT(grids.width() == vib_grid.dim_size(1) && grids.height() == vib_grid.dim_size(2)); + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + + const t_vib_inf* vib = vib_grid[layer][ix][iy]; + if (vib == nullptr) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "VIB at (%d, %d) is EMPTY!\n", ix, iy); + exit(1); + continue; + } + + size_t count = 0; + for (size_t i_first_stage = 0; i_first_stage < vib->first_stages.size(); i_first_stage++) { + auto first_stage = vib->first_stages[i_first_stage]; + if (first_stage.froms.size() == 0) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "VIB first stage '%s' at (%d, %d) has no from!\n", first_stage.mux_name, ix, iy); + exit(1); + } + count++; + } + + VTR_ASSERT(count == vib->first_stages.size()); + num_grid_rr_nodes += count; + } + } + + return num_grid_rr_nodes; +} + /************************************************************************ * For X-direction Channel: CHANX * We pair each x-direction routing channel to the grid below it @@ -302,13 +338,15 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, const std::vector& segment_inf_y, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, - const bool& through_channel) { + const bool& through_channel, + const bool& is_vib_arch) { /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); @@ -319,7 +357,10 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN); num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE); num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK); - + if (is_vib_arch) + num_rr_nodes_per_type[MEDIUM] = estimate_num_medium_rr_nodes(grids, vib_grid, layer); + else + num_rr_nodes_per_type[MEDIUM] = 0; /** * 2. Assign the segments for each routing channel, * To be specific, for each routing track, we assign a routing segment. @@ -361,23 +402,27 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, const std::vector& segment_inf_y, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, - const bool& through_channel) { + const bool& through_channel, + const bool& is_vib_arch) { VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + vib_grid, layer, chan_width, segment_inf_x, segment_inf_y, device_grid_annotation, shrink_boundary, - through_channel); + through_channel, + is_vib_arch); /* Reserve the number of node to be memory efficient */ size_t num_nodes = 0; @@ -626,6 +671,41 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder } /* End of class enumeration */ } +static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, + const size_t& layer, + const vtr::Point& grid_coordinate, + const vtr::NdMatrix& vib_grid) { + + const t_vib_inf* vib = vib_grid[layer][grid_coordinate.x()][grid_coordinate.y()]; + size_t num_medium_nodes = vib->first_stages.size(); + for (size_t i_medium = 0; i_medium < num_medium_nodes; i_medium++) { + /* Create a new node and fill information */ + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), MEDIUM, i_medium, SIDES[0]); + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x(), + grid_coordinate.y()); + //rr_graph_builder.add_node_side(node, SIDES[0]); + rr_graph_builder.set_node_medium_num(node, i_medium); + + rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_layer(node, layer); + + /* cost index is a FIXED value for MEDIUM */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(MEDIUM_COST_INDEX)); + + /* Switch info */ + rr_node_driver_switches[node] = RRSwitchId(vib->switch_idx); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + } + +} + /************************************************************************ * Create all the rr_nodes for grids ***********************************************************************/ @@ -633,9 +713,11 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, const size_t& layer, const RRSwitchId& wire_to_ipin_switch, - const RRSwitchId& delayless_switch) { + const RRSwitchId& delayless_switch, + const bool& is_vib_arch) { for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { t_physical_tile_loc tile_loc(ix, iy, layer); @@ -711,6 +793,30 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, wire_to_ipin_switch); } } + + if (is_vib_arch) { + /* Create medium nodes */ + VTR_ASSERT(grids.width() == vib_grid.dim_size(1) && grids.height() == vib_grid.dim_size(2)); + for (size_t iy = 0; iy < grids.height(); ++iy) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + + t_physical_tile_loc tile_loc(ix, iy, layer); + VTR_ASSERT(vib_grid[layer][ix][iy]->pbtype_name == grids.get_physical_type(tile_loc)->name); + vtr::Point grid_coordinate(ix, iy); + + rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, MEDIUM, vib_grid[layer][ix][iy]->first_stages.size(), SIDES[0]); + + load_one_grid_medium_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + rr_rc_data, + layer, grid_coordinate, + vib_grid); + + } + } + } + + //Copy the SOURCE/SINK nodes to all offset positions for blocks with width > 1 and/or height > 1 // This ensures that look-ups on non-root locations will still find the correct SOURCE/SINK for (size_t x = 0; x < grids.width(); x++) { @@ -1160,6 +1266,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, std::map>& rr_node_track_ids, std::vector& rr_rc_data, const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, @@ -1169,7 +1276,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const RRSwitchId& delayless_switch, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, - const bool& through_channel) { + const bool& through_channel, + const bool& is_vib_arch) { /* Allocates and loads all the structures needed for fast lookups of the * * index of an rr_node. rr_node_indices is a matrix containing the index * * of the *first* rr_node at a given (i,j) location. */ @@ -1188,9 +1296,10 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, load_grid_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, rr_rc_data, - grids, layer, + grids, vib_grid, layer, wire_to_ipin_switch, - delayless_switch); + delayless_switch, + is_vib_arch); load_chanx_rr_nodes_basic_info(rr_graph, rr_graph_builder, From 873469feaab1bc869c24ed9f693fd789647a0fa7 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 9 Jun 2024 16:16:48 +0800 Subject: [PATCH 257/453] Update tileable_rr_graph_node_builder.h --- .../tileable_rr_graph/tileable_rr_graph_node_builder.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 27fea172338..1cd7ad2abd3 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -25,13 +25,15 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& driver_switches, const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, const std::vector& segment_inf_y, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, - const bool& through_channel); + const bool& through_channel, + const bool& is_vib_arch); void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, @@ -39,6 +41,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, std::map>& rr_node_track_ids, std::vector& rr_rc_data, const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, @@ -48,6 +51,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const RRSwitchId& delayless_switch, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, - const bool& through_channel); + const bool& through_channel, + const bool& is_vib_arch); #endif From 307fb0b2b32cbe48b0df5fedff779c9b79b375ee Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:15:53 +0800 Subject: [PATCH 258/453] Update read_xml_arch_file.cpp Change vib parser --- libs/libarchfpga/src/read_xml_arch_file.cpp | 80 ++++++++++++++++----- 1 file changed, 63 insertions(+), 17 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index bcdee254405..f129fba0c01 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -5669,42 +5669,88 @@ static void ProcessFromOrToTokens(const std::vector Tokens, std::ve port_name = new char[strlen(Token_char)]; parse_pin_name((char*)Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); + std::vector all_sub_tile_to_tile_pin_indices; for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { - //int sub_tile_index = sub_tile.index; int sub_tile_capacity = sub_tile.capacity.total(); + int start = 0; + int end = 0; int i_port = 0; for (; i_port < (int)sub_tile.ports.size(); ++i_port) { - if (!strcmp(sub_tile.ports[i_port].name, port_name)) { - if (start_pin_index == end_pin_index && start_pin_index < 0) { - start_pin_index = 0; - end_pin_index = sub_tile.ports[i_port].num_pins - 1; - } - start_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; - end_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + start = sub_tile.ports[i_port].absolute_first_pin_index; + end = start + sub_tile.ports[i_port].num_pins - 1; break; } } - if (i_port == (int)sub_tile.ports.size()) { continue; } - - for (int pin_num = start_pin_index; pin_num <= end_pin_index; ++pin_num) { + for (int pin_num = start; pin_num <= end; ++pin_num) { VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; - t_from_or_to_inf from_inf; - from_inf.type_name = from_type_name; - from_inf.from_type = from_type; - from_inf.type_index = i_phy_type; - from_inf.phy_pin_index = physical_pin_index; - froms.push_back(from_inf); + all_sub_tile_to_tile_pin_indices.push_back(physical_pin_index); } } } + + if (start_pin_index == end_pin_index && start_pin_index < 0) { + start_pin_index = 0; + end_pin_index = all_sub_tile_to_tile_pin_indices.size() - 1; + } + + if ((int)all_sub_tile_to_tile_pin_indices.size() <= start_pin_index || (int)all_sub_tile_to_tile_pin_indices.size() <= end_pin_index) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "The index of pbtype %s : port %s exceeds its total number!\n", pb_type_name, port_name); + } + + for (int i = start_pin_index; i <= end_pin_index; i++) { + t_from_or_to_inf from_inf; + from_inf.type_name = from_type_name; + from_inf.from_type = from_type; + from_inf.type_index = i_phy_type; + from_inf.phy_pin_index = all_sub_tile_to_tile_pin_indices[i]; + froms.push_back(from_inf); + } + + // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { + // //int sub_tile_index = sub_tile.index; + // int sub_tile_capacity = sub_tile.capacity.total(); + + // int i_port = 0; + // for (; i_port < (int)sub_tile.ports.size(); ++i_port) { + + // if (!strcmp(sub_tile.ports[i_port].name, port_name)) { + // if (start_pin_index == end_pin_index && start_pin_index < 0) { + // start_pin_index = 0; + // end_pin_index = sub_tile.ports[i_port].num_pins - 1; + // } + // start_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + // end_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + // break; + // } + // } + + // if (i_port == (int)sub_tile.ports.size()) { + // continue; + // } + + // for (int pin_num = start_pin_index; pin_num <= end_pin_index; ++pin_num) { + // VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); + // for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { + // int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; + // int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; + // t_from_or_to_inf from_inf; + // from_inf.type_name = from_type_name; + // from_inf.from_type = from_type; + // from_inf.type_index = i_phy_type; + // from_inf.phy_pin_index = physical_pin_index; + // froms.push_back(from_inf); + // } + // } + // } } } From 77dfbe9a6b612b4cfa925f25fd64abeff04a5178 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:17:00 +0800 Subject: [PATCH 259/453] Update tileable_rr_graph_builder.cpp --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 97a968e4123..c9b35ac2838 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -324,7 +324,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ } /* No clock network support yet; Does not support flatten rr_graph yet */ - check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, device_ctx.chan_width, GRAPH_UNIDIR, OPEN, false); + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, vib_grid, device_ctx.chan_width, GRAPH_UNIDIR, OPEN, false); /************************************************************************ * Free all temp stucts From 55c4835b10a58ca38e3ac0613fcbeb4b397232ee Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:18:19 +0800 Subject: [PATCH 260/453] Update check_rr_graph.cpp --- libs/librrgraph/src/base/check_rr_graph.cpp | 31 +++++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 104e069af65..729a0f314ce 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -51,6 +51,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const std::vector& types, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, + const vtr::NdMatrix& vib_grid, const t_chan_width& chan_width, const t_graph_type graph_type, const int virtual_clock_network_root_idx, @@ -83,7 +84,7 @@ void check_rr_graph(const RRGraphView& rr_graph, t_rr_type rr_type = rr_graph.node_type(rr_node); int num_edges = rr_graph.num_edges(RRNodeId(inode)); - check_rr_node(rr_graph, rr_indexed_data, grid, chan_width, route_type, inode, is_flat); + check_rr_node(rr_graph, rr_indexed_data, grid, vib_grid, chan_width, route_type, inode, is_flat); /* Check all the connectivity (edges, etc.) information. */ edges.resize(0); @@ -270,7 +271,8 @@ void check_rr_graph(const RRGraphView& rr_graph, || (rr_graph.node_xhigh(rr_node) == int(grid.width()) - 2) || (rr_graph.node_yhigh(rr_node) == int(grid.height()) - 2)); bool is_wire = (rr_graph.node_type(rr_node) == CHANX - || rr_graph.node_type(rr_node) == CHANY); + || rr_graph.node_type(rr_node) == CHANY + || rr_graph.node_type(rr_node) == MEDIUM); if (!is_chain && !is_fringe && !is_wire) { if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) { @@ -331,6 +333,7 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device void check_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, + const vtr::NdMatrix& vib_grid, const t_chan_width& chan_width, const enum e_route_type route_type, const int inode, @@ -387,6 +390,13 @@ void check_rr_node(const RRGraphView& rr_graph, /* Check that the segment is within the array and such. */ type = grid.get_physical_type({xlow, ylow, layer_num}); + const t_vib_inf* vib_type; + if (vib_grid.dim_size(0) > 0) { + vib_type = vib_grid[layer_num][xlow][ylow]; + } + else { + vib_type = nullptr; + } switch (rr_type) { case SOURCE: @@ -400,6 +410,7 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", inode, rr_type, xlow, ylow, xhigh, yhigh); } break; + case MEDIUM: case IPIN: case OPIN: if (type == nullptr) { @@ -443,6 +454,10 @@ void check_rr_node(const RRGraphView& rr_graph, int class_max_ptc = get_tile_class_max_ptc(type, is_flat); int pin_max_ptc = get_tile_pin_max_ptc(type, is_flat); + int medium_max_ptc = -1; + if (vib_type) { + medium_max_ptc = (int)vib_type->first_stages.size(); + } e_pin_type class_type = OPEN; int class_num_pins = -1; switch (rr_type) { @@ -460,7 +475,17 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: inode %d (type %d) had a capacity of %d.\n", inode, rr_type, capacity); } break; - + case MEDIUM: + VTR_ASSERT(medium_max_ptc >= 0); + if (ptc_num >= medium_max_ptc) { + VPR_ERROR(VPR_ERROR_ROUTE, + "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); + } + if (capacity != 1) { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, + "in check_rr_node: inode %d (type %d) has a capacity of %d.\n", inode, rr_type, capacity); + } + break; case OPIN: case IPIN: class_type = get_pin_type_from_pin_physical_num(type, ptc_num); From 82151d457d83b7daffed2f69ffd9e356232d44cd Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:19:51 +0800 Subject: [PATCH 261/453] Update check_route.cpp --- vpr/src/route/check_route.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index cf18d894efa..d01fa95b56c 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -576,6 +576,7 @@ static void check_node_and_range(RRNodeId inode, check_rr_node(device_ctx.rr_graph, device_ctx.rr_indexed_data, device_ctx.grid, + device_ctx.vib_grid, device_ctx.chan_width, route_type, size_t(inode), From fffdc02a4ca4484449b60226f009a07aba2e6357 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:20:51 +0800 Subject: [PATCH 262/453] Update rr_graph_uxsdcxx_serializer.h --- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index e258e300863..bfadca34771 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1763,10 +1763,12 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { read_rr_graph_filename_->assign(read_rr_graph_name_); if (do_check_rr_graph_) { + const vtr::NdMatrix vib_grid_; check_rr_graph(*rr_graph_, physical_tile_types_, *rr_indexed_data_, grid_, + vib_grid_, *chan_width_, graph_type_, virtual_clock_network_root_idx_, @@ -1931,6 +1933,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { return OPIN; case uxsd::enum_node_type::IPIN: return IPIN; + case uxsd::enum_node_type::MEDIUM: + return MEDIUM; default: report_error( "Invalid node type %d", @@ -1951,6 +1955,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { return uxsd::enum_node_type::OPIN; case IPIN: return uxsd::enum_node_type::IPIN; + case MEDIUM: + return uxsd::enum_node_type::MEDIUM; default: report_error( "Invalid type %d", type); From 71c60e2c558fc92662b6090e4bbf47936e8b7347 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:21:51 +0800 Subject: [PATCH 263/453] Update rr_graph_uxsdcxx_interface.h --- libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h index b832527d52a..d1ad5347910 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h @@ -25,7 +25,7 @@ enum class enum_switch_type {UXSD_INVALID = 0, MUX, TRISTATE, PASS_GATE, SHORT, enum class enum_pin_type {UXSD_INVALID = 0, OPEN, OUTPUT, INPUT}; -enum class enum_node_type {UXSD_INVALID = 0, CHANX, CHANY, SOURCE, SINK, OPIN, IPIN}; +enum class enum_node_type {UXSD_INVALID = 0, CHANX, CHANY, SOURCE, SINK, OPIN, IPIN, MEDIUM}; enum class enum_node_direction {UXSD_INVALID = 0, INC_DIR, DEC_DIR, BI_DIR}; From 14eeddaf795503f685a20e255e3e33c63f5c374a Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:23:21 +0800 Subject: [PATCH 264/453] Update rr_graph.cpp --- vpr/src/route/rr_graph.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 9eff646d2ea..72453d1c3e6 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1400,11 +1400,13 @@ static void build_rr_graph(const t_graph_type graph_type, device_ctx.chan_width = nodes_per_chan; rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); - + + const vtr::NdMatrix vib_grid; check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grid, + vib_grid, device_ctx.chan_width, graph_type, device_ctx.virtual_clock_network_root_idx, @@ -1496,10 +1498,12 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, rr_graph_builder.clear_temp_storage(); + const vtr::NdMatrix vib_grid; check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grid, + vib_grid, device_ctx.chan_width, graph_type, device_ctx.virtual_clock_network_root_idx, From ac8c197e3b541feaad887ba0bbe1057ce8752d6e Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:24:35 +0800 Subject: [PATCH 265/453] Update rr_graph2.cpp --- vpr/src/route/rr_graph2.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 48cc553f44b..4cbc36d8a45 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1490,7 +1490,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, y, describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } - } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) { + } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK || rr_graph.node_type(inode) == MEDIUM) { //Sources have co-ordintes covering the entire block they are in if (!rr_graph.x_in_node_range(x, inode)) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", @@ -1559,7 +1559,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, auto& rr_node = rr_nodes[size_t(inode)]; - if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) { + if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK || rr_graph.node_type(inode) == MEDIUM) { int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1); int rr_height = (rr_graph.node_yhigh(rr_node.id()) - rr_graph.node_ylow(rr_node.id()) + 1); int rr_area = rr_width * rr_height; @@ -2818,4 +2818,4 @@ static bool should_apply_switch_override(int switch_override) { inline int get_chan_width(enum e_side side, const t_chan_width* nodes_per_chan) { return (side == TOP || side == BOTTOM ? nodes_per_chan->y_max : nodes_per_chan->x_max); -} \ No newline at end of file +} From ed15d8abdd1a62c51ac893a3768aef1fdbd1c1e6 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:26:42 +0800 Subject: [PATCH 266/453] Update vpr_utils.cpp --- vpr/src/util/vpr_utils.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index cda599c1712..f7d1aba9273 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2275,10 +2275,14 @@ std::vector get_all_pb_graph_node_primitives(const t_pb_ } bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, + const t_vib_inf* vib, t_rr_type node_type, int node_ptc) { if (node_type == CHANX || node_type == CHANY) { return true; + } else if (node_type == MEDIUM) { + VTR_ASSERT(vib != nullptr); + return (node_ptc < (int)vib->first_stages.size()); } else { VTR_ASSERT(node_type == IPIN || node_type == SINK || node_type == OPIN || node_type == SOURCE); if (node_type == IPIN || node_type == OPIN) { From e5085288b0b673c6e954a5e460f0335f3d3e71cf Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:27:37 +0800 Subject: [PATCH 267/453] Update connection_router.cpp --- vpr/src/route/connection_router.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index 956a4864854..4763b9e1018 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -1133,7 +1133,16 @@ static inline void update_router_stats(RouterStats* router_stats, rr_graph->node_ylow(rr_node_id), rr_graph->node_layer(rr_node_id)}); + const t_vib_inf* vib; + if (device_ctx.arch->is_vib_arch) { + vib = device_ctx.vib_grid[rr_graph->node_layer(rr_node_id)][rr_graph->node_xlow(rr_node_id)][rr_graph->node_ylow(rr_node_id)]; + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph->node_layer(rr_node_id)][rr_graph->node_xlow(rr_node_id)][rr_graph->node_ylow(rr_node_id)]; if (is_inter_cluster_node(physical_type, + vib, node_type, rr_graph->node_ptc_num(rr_node_id))) { if (is_push) { From 08268fe544cbe13dbbae7d96ff3667af081a67c3 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:28:29 +0800 Subject: [PATCH 268/453] Update overuse_report.cpp --- vpr/src/route/overuse_report.cpp | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 077401d7289..87b7a3cf999 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -220,9 +220,16 @@ static void report_overused_ipin_opin(std::ostream& os, "Non-track RR node should not span across multiple grid blocks."); t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({grid_x, grid_y, grid_layer}); - + const t_vib_inf* vib; + if (device_ctx.arch->is_vib_arch) { + vib = device_ctx.vib_grid[grid_layer][grid_x][grid_y]; + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[grid_layer][grid_x][grid_y]; os << "Pin physical number = " << rr_graph.node_pin_num(node_id) << '\n'; - if (is_inter_cluster_node(physical_tile, rr_graph.node_type(node_id), rr_graph.node_ptc_num(node_id))) { + if (is_inter_cluster_node(physical_tile, vib, rr_graph.node_type(node_id), rr_graph.node_ptc_num(node_id))) { os << "On Tile Pin" << "\n"; } else { From 6abd0b7f9d422c89f0dc77f9b2658adcb788e00c Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:29:10 +0800 Subject: [PATCH 269/453] Update vpr_utils.h --- vpr/src/util/vpr_utils.h | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index d05236f5a2d..8bbd081167c 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -259,6 +259,7 @@ void print_timing_stats(const std::string& name, std::vector get_all_pb_graph_node_primitives(const t_pb_graph_node* pb_graph_node); bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, + const t_vib_inf* vib, t_rr_type node_type, int node_ptc); From f80e4c3a4344390426446ebe97174fc173afcdb1 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:30:20 +0800 Subject: [PATCH 270/453] Update router_lookahead_map_utils.cpp --- vpr/src/route/router_lookahead_map_utils.cpp | 29 +++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 3094c97e4d5..9b28157cb96 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -384,8 +384,17 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { const std::vector& rr_nodes_at_loc = device_ctx.rr_graph.node_lookup().find_grid_nodes_at_all_sides(sample_loc.layer_num, sample_loc.x, sample_loc.y, rr_type); for (RRNodeId node_id : rr_nodes_at_loc) { int ptc = rr_graph.node_ptc_num(node_id); + const t_vib_inf* vib; + if (device_ctx.arch->is_vib_arch) { + vib = device_ctx.vib_grid[sample_loc.layer_num][sample_loc.x][sample_loc.y]; + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[sample_loc.layer_num][sample_loc.x][sample_loc.y]; // For the time being, we decide to not let the lookahead explore the node inside the clusters if (!is_inter_cluster_node(&device_ctx.physical_tile_types[itile], + vib, rr_type, ptc)) { continue; @@ -977,7 +986,7 @@ static void dijkstra_flood_to_wires(int itile, src_opin_delays[root_layer_num][itile][ptc][curr_layer_num][seg_index].congestion = curr.congestion; } - } else if (curr_rr_type == SOURCE || curr_rr_type == OPIN || curr_rr_type == IPIN) { + } else if (curr_rr_type == SOURCE || curr_rr_type == OPIN || curr_rr_type == IPIN || curr_rr_type == MEDIUM) { //We allow expansion through SOURCE/OPIN/IPIN types auto cost_index = rr_graph.node_cost_index(curr.node); float incr_cong = device_ctx.rr_indexed_data[cost_index].base_cost; //Current nodes congestion cost @@ -991,7 +1000,16 @@ static void dijkstra_flood_to_wires(int itile, t_physical_tile_type_ptr physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(next_node), rr_graph.node_ylow(next_node), rr_graph.node_layer(next_node)}); + const t_vib_inf* vib; + if (device_ctx.arch->is_vib_arch) { + vib = device_ctx.vib_grid[rr_graph.node_layer(next_node)][rr_graph.node_xlow(next_node)][rr_graph.node_ylow(next_node)]; + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(next_node)][rr_graph.node_xlow(next_node)][rr_graph.node_ylow(next_node)]; if (!is_inter_cluster_node(physical_type, + vib, rr_graph.node_type(next_node), rr_graph.node_ptc_num(next_node))) { // Don't go inside the clusters @@ -1357,7 +1375,16 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, rr_graph.node_ylow(child_node), rr_graph.node_layer(child_node)}); + const t_vib_inf* vib; + if (device_ctx.arch->is_vib_arch) { + vib = device_ctx.vib_grid[rr_graph.node_layer(child_node)][rr_graph.node_xlow(child_node)][rr_graph.node_ylow(child_node)]; + } + else { + vib = nullptr; + } + if (!is_inter_cluster_node(physical_type, + vib, rr_graph.node_type(child_node), rr_graph.node_ptc_num(child_node))) { continue; From 92fd5afd2f8ed3a38c116ddfa8c24be361199819 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:31:14 +0800 Subject: [PATCH 271/453] Update router_lookahead_map.cpp --- vpr/src/route/router_lookahead_map.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index c8666a1829a..7cc1ba4aad3 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -208,6 +208,14 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI t_physical_tile_type_ptr from_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node), rr_graph.node_layer(current_node)}); + const t_vib_inf* vib; + if (device_ctx.arch->is_vib_arch) { + vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; int from_node_ptc_num = rr_graph.node_ptc_num(current_node); t_physical_tile_type_ptr to_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(target_node), rr_graph.node_ylow(target_node), @@ -229,6 +237,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } else if (from_rr_type == OPIN) { if (is_inter_cluster_node(from_physical_type, + vib, from_rr_type, from_node_ptc_num)) { // Similar to CHANX and CHANY From faf2ef34cc141419341735c7ef7d15ec1ff981b2 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:32:21 +0800 Subject: [PATCH 272/453] Update rr_graph_uxsdcxx.h --- libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index f452ad75857..85b55873e2d 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -1576,7 +1576,7 @@ template /* Lookup tables for enums. */ constexpr const char *lookup_switch_type[] = {"UXSD_INVALID", "mux", "tristate", "pass_gate", "short", "buffer"}; constexpr const char *lookup_pin_type[] = {"UXSD_INVALID", "OPEN", "OUTPUT", "INPUT"}; -constexpr const char *lookup_node_type[] = {"UXSD_INVALID", "CHANX", "CHANY", "SOURCE", "SINK", "OPIN", "IPIN"}; +constexpr const char *lookup_node_type[] = {"UXSD_INVALID", "CHANX", "CHANY", "SOURCE", "SINK", "OPIN", "IPIN", "MEDIUM"}; constexpr const char *lookup_node_direction[] = {"UXSD_INVALID", "INC_DIR", "DEC_DIR", "BI_DIR"}; constexpr const char *lookup_loc_side[] = {"UXSD_INVALID", "LEFT", "RIGHT", "TOP", "BOTTOM", "RIGHT_LEFT", "RIGHT_BOTTOM", "RIGHT_BOTTOM_LEFT", "TOP_RIGHT", "TOP_BOTTOM", "TOP_LEFT", "TOP_RIGHT_BOTTOM", "TOP_RIGHT_LEFT", "TOP_BOTTOM_LEFT", "TOP_RIGHT_BOTTOM_LEFT", "BOTTOM_LEFT"}; From 601718a9bacce6b4eef12ec5a6b1339212ba0e9b Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:33:09 +0800 Subject: [PATCH 273/453] Update rr_spatial_lookup.cpp --- libs/librrgraph/src/base/rr_spatial_lookup.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 37b4c314470..1bca3015abb 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -195,8 +195,8 @@ std::vector RRSpatialLookup::find_grid_nodes_at_all_sides(int layer, int x, int y, t_rr_type rr_type) const { - VTR_ASSERT(rr_type == SOURCE || rr_type == OPIN || rr_type == IPIN || rr_type == SINK); - if (rr_type == SOURCE || rr_type == SINK) { + VTR_ASSERT(rr_type == SOURCE || rr_type == OPIN || rr_type == IPIN || rr_type == SINK || rr_type == MEDIUM); + if (rr_type == SOURCE || rr_type == SINK || rr_type == MEDIUM) { return find_nodes(layer,x, y, rr_type); } From 0541865eff28b73d31ee6ce2959854d13df6b888 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:33:54 +0800 Subject: [PATCH 274/453] Update check_rr_graph.h --- libs/librrgraph/src/base/check_rr_graph.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libs/librrgraph/src/base/check_rr_graph.h b/libs/librrgraph/src/base/check_rr_graph.h index 46e5a80486c..5547571513b 100644 --- a/libs/librrgraph/src/base/check_rr_graph.h +++ b/libs/librrgraph/src/base/check_rr_graph.h @@ -9,6 +9,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const std::vector& types, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, + const vtr::NdMatrix& vib_grid, const t_chan_width& chan_width, const t_graph_type graph_type, const int virtual_clock_network_root_idx, @@ -17,6 +18,7 @@ void check_rr_graph(const RRGraphView& rr_graph, void check_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, + const vtr::NdMatrix& vib_grid, const t_chan_width& chan_width, const enum e_route_type route_type, const int inode, From a2777e6d06cd1e815bca1682fe2aff93ca6922a3 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:35:02 +0800 Subject: [PATCH 275/453] Update tileable_rr_graph_edge_builder.cpp --- .../tileable_rr_graph_edge_builder.cpp | 135 +++++++++++++++--- 1 file changed, 114 insertions(+), 21 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index b74d8768e26..717d8b8069f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -136,7 +136,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, for (size_t iy = 0; iy < vib_grid.dim_size(2); iy++) { std::map mux_name_map; - for (size_t i_mux; i_mux < vib_grid[i_layer][ix][iy]->first_stages.size(); i_mux++) { + for (size_t i_mux = 0; i_mux < vib_grid[i_layer][ix][iy]->first_stages.size(); i_mux++) { mux_name_map.emplace(vib_grid[i_layer][ix][iy]->first_stages[i_mux].mux_name, i_mux); } medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; @@ -172,27 +172,120 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord); - /* adapt the track_to_ipin_lookup for the GSB nodes */ - t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ - track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); - - /* adapt the opin_to_track_map for the GSB nodes */ - t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ - opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); - - /* adapt the switch_block_conn for the GSB nodes */ - t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ - sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, - segment_inf); - - /* Build edges for a GSB */ - build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, - sb_bend_conn, track2ipin_map, opin2track_map, - sb_conn, rr_node_driver_switches, num_edges_to_create); - /* Finish this GSB, go to the next*/ - rr_graph_builder.build_edges(true); + if (is_vib_arch) { + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord, medium_mux_name2medium_index); + build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + + rr_graph_builder.build_edges(true); + } + else { + /* adapt the track_to_ipin_lookup for the GSB nodes */ + t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); + + /* adapt the opin_to_track_map for the GSB nodes */ + t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + + /* adapt the switch_block_conn for the GSB nodes */ + t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, + segment_inf); + + /* Build edges for a GSB */ + build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, + sb_bend_conn, track2ipin_map, opin2track_map, + sb_conn, rr_node_driver_switches, num_edges_to_create); + /* Finish this GSB, go to the next*/ + rr_graph_builder.build_edges(true); + } + } + } + + /* Process boundary */ + if (is_vib_arch) { + size_t ix, iy; + // process top boundary + iy = grids.height() - 1; + for (ix = 0; ix < grids.width() - 2; ++ix) { + vtr::Point actual_coord(ix, iy); + vtr::Point gsb_coord(ix, iy - 1); + + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord); + + + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + size_t edge_count = 0; + for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + for (auto to_node : iter->second) { + rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + edge_count++; + } + } + num_edges_to_create += edge_count; + //rr_graph_builder.build_edges(true); + + } + + // process right boundary + ix = grids.width() - 1; + for (iy = 0; iy < grids.height() - 2; ++iy) { + vtr::Point actual_coord(ix, iy); + vtr::Point gsb_coord(ix - 1, iy); + + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord); + + + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + size_t edge_count = 0; + for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + for (auto to_node : iter->second) { + rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + edge_count++; + } + } + num_edges_to_create += edge_count; + //rr_graph_builder.build_edges(true); + + } + + // process right-top corner + ix = grids.width() - 1; + iy = grids.height() - 1; + + vtr::Point actual_coord(ix, iy); + vtr::Point gsb_coord(ix - 1, iy - 1); + + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord); + + + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + size_t edge_count = 0; + for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + for (auto to_node : iter->second) { + rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + edge_count++; + } } + num_edges_to_create += edge_count; + rr_graph_builder.build_edges(true); } } From 58dce81a0f80e1f5dab630693ad258ff08a1e047 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:35:56 +0800 Subject: [PATCH 276/453] Update tileable_rr_graph_gsb.cpp --- .../tileable_rr_graph_gsb.cpp | 315 ++++++++++++++++++ 1 file changed, 315 insertions(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 6356cc00bca..1a05e7e613a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1715,3 +1715,318 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, /* Build actual edges */ rr_graph_builder.build_edges(true); } + +/* Vib edge builder */ +t_vib_map build_vib_map(const RRGraphView& rr_graph, + const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, + const RRGSB& rr_gsb, + const std::vector& segment_inf, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const vtr::Point& actual_coordinate, + std::vector>>> medium_mux_name2medium_index) { + VTR_ASSERT(rr_gsb.get_x() == gsb_coordinate.x() && rr_gsb.get_y() == gsb_coordinate.y()); + + t_vib_map vib_map; + + const t_vib_inf* vib = vib_grid[layer][actual_coordinate.x()][actual_coordinate.y()]; + auto phy_type = grids.get_physical_type({(int)actual_coordinate.x(), (int)actual_coordinate.y(), (int)layer}); + VTR_ASSERT(!strcmp(vib->pbtype_name.c_str(), phy_type->name)); + const std::vector first_stages = vib->first_stages; + for (size_t i_first_stage = 0; i_first_stage < first_stages.size(); i_first_stage++) { + std::vector froms = first_stages[i_first_stage].froms; + RRNodeId to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, i_first_stage); + VTR_ASSERT(to_node.is_valid()); + for (auto from : froms) { + RRNodeId from_node; + if (from.from_type == PB) { + + if (from.type_name != vib->pbtype_name) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type name!\n"); + exit(1); + } + + for (e_side side : SIDES) { + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); + if (from_node.is_valid()) + break; + } + if (!from_node.is_valid()) { + VTR_LOGF_WARN(__FILE__, __LINE__, + "Can not find from node %s:%d!\n", from.type_name, from.phy_pin_index); + continue; + } + } + else if (from.from_type == SEGMENT) { + char from_dir = from.seg_dir; + //int from_index = from.seg_index; + t_segment_inf segment = segment_inf[from.type_index]; + VTR_ASSERT(segment.name == from.type_name); + t_seg_group seg_group; + for (auto seg : vib->seg_groups) { + if (seg.name == segment.name) { + seg_group = seg; + break; + } + } + VTR_ASSERT(from.seg_index < seg_group.track_num * segment.length); + e_side side; + if (from_dir == 'W') side = RIGHT; + else if (from_dir == 'E') side = LEFT; + else if (from_dir == 'N') side = BOTTOM; + else if (from_dir == 'S') side = TOP; + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong segment from direction!\n"); + exit(1); + } + + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); + if (track_list.size() == 0) continue; + else { + VTR_ASSERT((int)track_list.size() >= (from.seg_index + 1) * 2); + size_t seg_id; + if (side == LEFT || side == BOTTOM) { //INC + seg_id = from.seg_index * 2; + } + else { //DEC + VTR_ASSERT(side == RIGHT || side == TOP); + seg_id = from.seg_index * 2 + 1; + } + from_node = rr_gsb.get_chan_node(side, track_list[seg_id]); + VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + } + + + } + else if (from.from_type == MUX) { + size_t from_mux_index = medium_mux_name2medium_index[layer][actual_coordinate.x()][actual_coordinate.y()][from.type_name]; + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + } + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type!\n"); + exit(1); + } + VTR_ASSERT(from_node.is_valid()); + auto iter = vib_map.begin(); + for (; iter != vib_map.end(); ++iter) { + if (iter->first == from_node) { + vib_map[from_node].push_back(to_node); + } + } + if (iter == vib_map.end()) { + std::vector to_nodes; + to_nodes.push_back(to_node); + vib_map.emplace(std::make_pair(from_node, to_nodes)); + } + + + } + } + /* Second stages*/ + const std::vector second_stages = vib->second_stages; + for (size_t i_second_stage = 0; i_second_stage < second_stages.size(); i_second_stage++) { + std::vector froms = second_stages[i_second_stage].froms; + std::vector tos = second_stages[i_second_stage].to; + + std::vector to_nodes; + for (auto to : tos) { + RRNodeId to_node; + if (to.from_type == PB) { + + if (to.type_name != vib->pbtype_name) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong to type name!\n"); + exit(1); + } + + for (e_side side : SIDES) { + to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), IPIN, to.phy_pin_index, side); + if (to_node.is_valid()) + break; + } + if (!to_node.is_valid()) { + VTR_LOGF_WARN(__FILE__, __LINE__, + "Can not find from node %s:%d!\n", to.type_name, to.phy_pin_index); + continue; + } + } + else if (to.from_type == SEGMENT) { + char to_dir = to.seg_dir; + //int from_index = from.seg_index; + t_segment_inf segment = segment_inf[to.type_index]; + VTR_ASSERT(segment.name == to.type_name); + t_seg_group seg_group; + for (auto seg : vib->seg_groups) { + if (seg.name == segment.name) { + seg_group = seg; + break; + } + } + VTR_ASSERT(to.seg_index < seg_group.track_num * segment.length); + e_side side; + if (to_dir == 'W') side = LEFT; + else if (to_dir == 'E') side = RIGHT; + else if (to_dir == 'N') side = TOP; + else if (to_dir == 'S') side = BOTTOM; + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong segment from direction!\n"); + exit(1); + } + + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); + if (track_list.size() == 0) continue; + else { + //enum e_track_status track_status = determine_track_status_of_gsb + VTR_ASSERT((int)track_list.size() >= (to.seg_index + 1) * 2); + size_t seg_id; + if (side == LEFT || side == BOTTOM) { //DEC + seg_id = to.seg_index * 2 + 1; + } + else { //INC + VTR_ASSERT(side == RIGHT || side == TOP); + seg_id = to.seg_index * 2; + } + enum e_track_status track_status = determine_track_status_of_gsb(rr_graph, rr_gsb, side, track_list[seg_id]); + VTR_ASSERT(track_status == TRACK_START); + to_node = rr_gsb.get_chan_node(side, track_list[seg_id]); + VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + } + + + } + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type!\n"); + exit(1); + } + VTR_ASSERT(to_node.is_valid()); + to_nodes.push_back(to_node); + } + + + + std::vector from_nodes; + for (auto from : froms) { + RRNodeId from_node; + if (from.from_type == PB) { + + if (from.type_name != vib->pbtype_name) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type name!\n"); + exit(1); + } + + for (e_side side : SIDES) { + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); + if (from_node.is_valid()) + break; + } + if (!from_node.is_valid()) { + VTR_LOGF_WARN(__FILE__, __LINE__, + "Can not find from node %s:%d!\n", from.type_name, from.phy_pin_index); + continue; + } + } + else if (from.from_type == SEGMENT) { + char from_dir = from.seg_dir; + //int from_index = from.seg_index; + t_segment_inf segment = segment_inf[from.type_index]; + VTR_ASSERT(segment.name == from.type_name); + t_seg_group seg_group; + for (auto seg : vib->seg_groups) { + if (seg.name == segment.name) { + seg_group = seg; + break; + } + } + VTR_ASSERT(from.seg_index < seg_group.track_num * segment.length); + e_side side; + if (from_dir == 'W') side = RIGHT; + else if (from_dir == 'E') side = LEFT; + else if (from_dir == 'N') side = BOTTOM; + else if (from_dir == 'S') side = TOP; + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong segment from direction!\n"); + exit(1); + } + + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); + if (track_list.size() == 0) continue; + else { + VTR_ASSERT((int)track_list.size() >= (from.seg_index + 1) * 2); + size_t seg_id; + if (side == LEFT || side == BOTTOM) { //INC + seg_id = from.seg_index * 2; + } + else { //DEC + VTR_ASSERT(side == RIGHT || side == TOP); + seg_id = from.seg_index * 2 + 1; + } + from_node = rr_gsb.get_chan_node(side, track_list[seg_id]); + VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + } + + + } + else if (from.from_type == MUX) { + size_t from_mux_index = medium_mux_name2medium_index[layer][actual_coordinate.x()][actual_coordinate.y()][from.type_name]; + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + } + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type!\n"); + exit(1); + } + VTR_ASSERT(from_node.is_valid()); + from_nodes.push_back(from_node); + } + + if (to_nodes.size() > 0 && from_nodes.size() > 0) { + for (auto from_node : from_nodes) { + auto iter = vib_map.begin(); + for (; iter != vib_map.end(); ++iter) { + if (iter->first == from_node) { + for (auto to_node : to_nodes) { + vib_map[from_node].push_back(to_node); + } + + } + } + if (iter == vib_map.end()) { + vib_map.emplace(std::make_pair(from_node, to_nodes)); + } + } + } + else { + VTR_LOGF_WARN(__FILE__, __LINE__, + "This medium mux has no from or to nodes!\n"); + } + } + return vib_map; +} + +void build_edges_for_one_tileable_vib(RRGraphBuilder& rr_graph_builder, + const t_vib_map& vib_map, + const t_bend_track2track_map& sb_bend_conn, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges_to_create) { + + size_t edge_count = 0; + for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + for (auto to_node : iter->second) { + rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + edge_count++; + } + } + for (auto iter = sb_bend_conn.begin(); iter != sb_bend_conn.end(); ++iter) { + rr_graph_builder.create_edge(iter->first, iter->second, rr_node_driver_switches[iter->second], false); + edge_count++; + } + num_edges_to_create += edge_count; +} From 5bb56c7941fa388b9fc0817ba4fe143cf9a5fafd Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 19:36:30 +0800 Subject: [PATCH 277/453] Update tileable_rr_graph_gsb.h --- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 3eeb26fcad8..dc052292ac1 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -25,6 +25,7 @@ * Data stuctures related to the functions ***********************************************************************/ typedef std::map t_bend_track2track_map; +typedef std::map> t_vib_map; typedef std::vector>> t_track2track_map; typedef std::vector>> t_track2pin_map; typedef std::vector>>> t_pin2track_map; @@ -41,7 +42,7 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const bool& concat_wire, const bool& wire_opposite_side, const std::vector& segment_inf); - + t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, RRGraphBuilder& rr_graph_builder, const RRGraphView& rr_graph, @@ -90,4 +91,19 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, const std::vector& directs, const std::vector& clb_to_clb_directs); +t_vib_map build_vib_map(const RRGraphView& rr_graph, + const DeviceGrid& grids, + const vtr::NdMatrix& vib_grid, + const RRGSB& rr_gsb, + const std::vector& segment_inf, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const vtr::Point& actual_coordinate, + std::vector>>> medium_mux_name2medium_index); + +void build_edges_for_one_tileable_vib(RRGraphBuilder& rr_graph_builder, + const t_vib_map& vib_map, + const t_bend_track2track_map& sb_bend_conn, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges_to_create); #endif From 0929cd0aded1da2f9ba9e4cd7c4a4e1fb9e5d9f8 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 20:47:39 +0800 Subject: [PATCH 278/453] Update rr_node_types.h --- libs/librrgraph/src/base/rr_node_types.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index 56c2b97c3e6..aa872633b19 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -24,11 +24,12 @@ typedef enum e_rr_type : unsigned char { OPIN, ///Output pin of a block CHANX, ///x-directed routing wire, or an x-directed segment of a channel for global routing CHANY, ///y-directed routing wire, or a y-directed segment of a channel for global routing + MEDIUM, NUM_RR_TYPES } t_rr_type; -constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; -constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; +constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY, MEDIUM}}; +constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY", "MEDIUM"}}; /* * Direction::INC: wire driver is positioned at the low-coordinate end of the wire. From 61214230e1d75021dcf5b8ef0d7833d62fb4fc23 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 21:16:02 +0800 Subject: [PATCH 279/453] Update rr_graph_builder.h --- libs/librrgraph/src/base/rr_graph_builder.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 8b6af64aef0..eeea5e2a783 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -177,7 +177,7 @@ class RRGraphBuilder { inline void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2) { node_storage_.set_node_coordinates(id, x1, y1, x2, y2); } - + inline void set_node_bend_start(RRNodeId id, size_t bend_start) { node_storage_.set_node_bend_start(id, bend_start); } @@ -234,6 +234,11 @@ class RRGraphBuilder { node_storage_.set_node_class_num(id, new_class_num); } + /** @brief set_node_medium_num() is designed for routing medium nodes */ + inline void set_node_medium_num(RRNodeId id, int new_class_num) { + node_storage_.set_node_medium_num(id, new_class_num); + } + /** @brief Add a list of ptc number in string (split by comma) to a given node. This function is used by rr graph reader only. Not suggested for internal builder!!! */ void set_node_ptc_nums(RRNodeId node, const std::string& ptc_str); From 1d0be82ae62dbf72fb475dc31e29c698a7bcec5f Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 21:18:33 +0800 Subject: [PATCH 280/453] Update rr_graph_storage.cpp --- libs/librrgraph/src/base/rr_graph_storage.cpp | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 402e605abe6..c029eb23ac7 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -666,6 +666,13 @@ void t_rr_graph_storage::set_node_class_num(RRNodeId id, int new_class_num) { node_ptc_[id].ptc_.class_num = new_class_num; } +void t_rr_graph_storage::set_node_medium_num(RRNodeId id, int new_medium_num) { + if (node_type(id) != MEDIUM) { + VTR_LOG_ERROR("Attempted to set RR node 'medium_num' for non-MEDIUM type '%s'\n", node_type_string(id)); + } + node_ptc_[id].ptc_.medium_num = new_medium_num; +} + int t_rr_graph_storage::node_ptc_num(RRNodeId id) const { return node_ptc_[id].ptc_.pin_num; } @@ -703,6 +710,17 @@ static int get_node_class_num( return node_ptc[id].ptc_.class_num; } +static int get_node_medium_num( + vtr::array_view_id node_storage, + vtr::array_view_id node_ptc, + RRNodeId id) { + auto node_type = node_storage[id].type_; + if (node_type != MEDIUM) { + VTR_LOG_ERROR("Attempted to access RR node 'medium_num' for non-MEDIUM type '%s'\n", rr_node_typename[node_type]); + } + return node_ptc[id].ptc_.medium_num; +} + int t_rr_graph_storage::node_pin_num(RRNodeId id) const { return get_node_pin_num( vtr::make_const_array_view_id(node_storage_), @@ -721,6 +739,12 @@ int t_rr_graph_storage::node_class_num(RRNodeId id) const { vtr::make_const_array_view_id(node_ptc_), id); } +int t_rr_graph_storage::node_medium_num(RRNodeId id) const { + return get_node_medium_num( + vtr::make_const_array_view_id(node_storage_), + vtr::make_const_array_view_id(node_ptc_), + id); +} void t_rr_graph_storage::set_node_type(RRNodeId id, t_rr_type new_type) { node_storage_[id].type_ = new_type; @@ -804,6 +828,9 @@ int t_rr_graph_view::node_track_num(RRNodeId id) const { int t_rr_graph_view::node_class_num(RRNodeId id) const { return get_node_class_num(node_storage_, node_ptc_, id); } +int t_rr_graph_view::node_medium_num(RRNodeId id) const { + return get_node_medium_num(node_storage_, node_ptc_, id); +} t_rr_graph_view t_rr_graph_storage::view() const { From e904c864b57deb70a0eafbd0beedb97359b831e8 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 21:19:46 +0800 Subject: [PATCH 281/453] Update rr_graph_storage.h --- libs/librrgraph/src/base/rr_graph_storage.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 1bba4432746..28dca6abc66 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -59,7 +59,7 @@ struct alignas(64) t_rr_node_data { int16_t ylow_ = -1; int16_t xhigh_ = -1; int16_t yhigh_ = -1; - + size_t node_bend_start_ = 0; size_t node_bend_end_ = 0; @@ -99,6 +99,7 @@ struct t_rr_node_ptc_data { int pin_num; int track_num; int class_num; + int medium_num; } ptc_; }; @@ -186,7 +187,7 @@ class t_rr_graph_storage { short node_yhigh(RRNodeId id) const { return node_storage_[id].yhigh_; } - + short node_bend_start(RRNodeId id) const { return node_storage_[id].node_bend_start_; } @@ -231,6 +232,7 @@ class t_rr_graph_storage { int node_pin_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_track_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_class_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent + int node_medium_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent /** @brief Retrieve fan_in for RRNodeId, init_fan_in must have been called first. */ t_edge_size fan_in(RRNodeId id) const { @@ -558,6 +560,7 @@ class t_rr_graph_storage { void set_node_pin_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_track_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_class_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent + void set_node_medium_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_type(RRNodeId id, t_rr_type new_type); void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2); @@ -918,6 +921,7 @@ class t_rr_graph_view { int node_pin_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_track_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_class_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent + int node_medium_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent /* Retrieve fan_in for RRNodeId. */ t_edge_size fan_in(RRNodeId id) const { From 25b096dee403f8bdc3a56baf52a45aa0050aeb96 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 15 Jun 2024 21:22:05 +0800 Subject: [PATCH 282/453] Update rr_graph_cost.h --- libs/librrgraph/src/base/rr_graph_cost.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_graph_cost.h b/libs/librrgraph/src/base/rr_graph_cost.h index 00c14c912c2..6ad8be9e1b8 100644 --- a/libs/librrgraph/src/base/rr_graph_cost.h +++ b/libs/librrgraph/src/base/rr_graph_cost.h @@ -15,9 +15,10 @@ enum e_base_cost_type { enum e_cost_indices { SOURCE_COST_INDEX = 0, SINK_COST_INDEX, + MEDIUM_COST_INDEX, OPIN_COST_INDEX, IPIN_COST_INDEX, CHANX_COST_INDEX_START }; -#endif \ No newline at end of file +#endif From 115d237e422d050b3d31f09c5becde9aa35f67c3 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Tue, 25 Jun 2024 11:14:02 +0500 Subject: [PATCH 283/453] Removing warnings from libencrypt and libdecrypt --- libs/libdecrypt/src/decryption.cpp | 3 ++- libs/libencrypt/src/encryption.cpp | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/libs/libdecrypt/src/decryption.cpp b/libs/libdecrypt/src/decryption.cpp index 2a745cfd5bf..9c115c7e798 100644 --- a/libs/libdecrypt/src/decryption.cpp +++ b/libs/libdecrypt/src/decryption.cpp @@ -144,7 +144,8 @@ RSA* Decryption::loadPrivateKey(const std::string& privateKeyString) { return nullptr; } - if (!PEM_read_bio_RSAPrivateKey(privateKeyBio, &key, NULL, (void*)passphrase.c_str())) { + char* passphrase_cstr = const_cast(passphrase.c_str()); + if (!PEM_read_bio_RSAPrivateKey(privateKeyBio, &key, NULL, passphrase_cstr)) { std::cerr << "Error reading private key" << std::endl; BIO_free(privateKeyBio); return nullptr; diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp index 07bdae5c220..a92e6f8f155 100644 --- a/libs/libencrypt/src/encryption.cpp +++ b/libs/libencrypt/src/encryption.cpp @@ -20,7 +20,8 @@ RSA* Encryption::loadPublicKey(const std::string& filename) { return nullptr; } - if (!PEM_read_RSA_PUBKEY(keyFile, &key, NULL, (void*)passphrase_enc.c_str())) { + char* passphrase_cstr = const_cast(passphrase_enc.c_str()); + if (!PEM_read_RSA_PUBKEY(keyFile, &key, NULL, passphrase_cstr)) { std::cerr << "Error reading public key from file: " << filename << std::endl; fclose(keyFile); return nullptr; From e4ddd25d28f600e194ab1512236a8c4a8135d4ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 10:54:13 -0700 Subject: [PATCH 284/453] [vpr] add a new option to enable perimeter cbx and cby --- libs/libarchfpga/src/physical_types.h | 1 + libs/libarchfpga/src/read_xml_arch_file.cpp | 3 ++- vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/vpr_types.h | 1 + vpr/src/route/rr_graph.cpp | 1 + 5 files changed, 6 insertions(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index e056da44390..938cac03f29 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -2009,6 +2009,7 @@ struct t_arch { /* Xifan Tang: options for tileable routing architectures */ bool tileable; + bool perimeter_cb; bool shrink_boundary; bool through_channel; bool opin2all_sides; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index f9fd157ed94..85b240fa548 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -2535,6 +2535,7 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti //expect_only_attributes(layout_tag, {}, loc_data); arch->tileable = get_attribute(layout_tag, "tileable", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->perimeter_cb = get_attribute(layout_tag, "perimeter_cb", loc_data, ReqOpt::OPTIONAL).as_bool(false); arch->shrink_boundary = get_attribute(layout_tag, "shrink_boundary", loc_data, ReqOpt::OPTIONAL).as_bool(false); arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false); arch->opin2all_sides = get_attribute(layout_tag, "opin2all_sides", loc_data, ReqOpt::OPTIONAL).as_bool(false); @@ -4903,4 +4904,4 @@ static T* get_type_by_name(const char* type_name, std::vector& types) { archfpga_throw(__FILE__, __LINE__, "Could not find type: %s\n", type_name); -} \ No newline at end of file +} diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index df5d14ba1dc..ccc90e181b5 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -423,6 +423,7 @@ static void SetupRoutingArch(const t_arch& Arch, /* Copy the tileable routing setting */ RoutingArch->tileable = Arch.tileable; + RoutingArch->perimeter_cb = Arch.perimeter_cb; RoutingArch->shrink_boundary = Arch.shrink_boundary; RoutingArch->through_channel = Arch.through_channel; RoutingArch->opin2all_sides = Arch.opin2all_sides; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index cbbe0cd560d..de287b0dab2 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1576,6 +1576,7 @@ struct t_det_routing_arch { /* Xifan Tang: tileable routing */ bool tileable; + bool perimeter_cb; bool shrink_boundary; bool through_channel; bool opin2all_sides; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index e238accf734..70c068137c0 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -721,6 +721,7 @@ void create_rr_graph(const t_graph_type graph_type, directs, num_directs, &det_routing_arch->wire_to_rr_ipin_switch, det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ + det_routing_arch->perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ det_routing_arch->concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ From 691ae6d0b1d35763c57f98b4ebcc908ad6334e0e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 10:55:41 -0700 Subject: [PATCH 285/453] [vpr] updating tileable rr graph generator --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 1 + vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h | 1 + 2 files changed, 2 insertions(+) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 58d58e27226..0059042c9d1 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -85,6 +85,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const int& num_directs, int* wire_to_rr_ipin_switch, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel, const bool& opin2all_sides, const bool& concat_wire, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h index af188e12af5..f18a1ae93d9 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -30,6 +30,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const int& num_directs, int* wire_to_rr_ipin_switch, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel, const bool& opin2all_sides, const bool& concat_wire, From 619e94e386e09b0831baada120ead88545031dfd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 14:15:30 -0700 Subject: [PATCH 286/453] [vpr] upgraded tileable rr_graph to support perimeter cb --- .../device_grid_annotation.cpp | 22 +++- .../device_grid_annotation.h | 2 +- .../rr_graph_builder_utils.cpp | 64 ++++++++--- .../rr_graph_builder_utils.h | 2 + .../tileable_rr_graph_builder.cpp | 5 +- .../tileable_rr_graph_edge_builder.cpp | 4 + .../tileable_rr_graph_edge_builder.h | 1 + .../tileable_rr_graph_node_builder.cpp | 105 ++++++++++++++---- .../tileable_rr_graph_node_builder.h | 2 + 9 files changed, 162 insertions(+), 45 deletions(-) diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp index e389af027ed..66ab365b42a 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -2,9 +2,9 @@ #include "vtr_log.h" #include "vpr_utils.h" -DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid) { +DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid, const bool& perimeter_cb) { alloc(grid); - init(grid); + init(grid, perimeter_cb); } void DeviceGridAnnotation::alloc(const DeviceGrid& grid) { @@ -13,15 +13,27 @@ void DeviceGridAnnotation::alloc(const DeviceGrid& grid) { chany_existence_.resize({grid.width(), grid.height()}, false); } -void DeviceGridAnnotation::init(const DeviceGrid& grid) { +void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& perimeter_cb) { /* If shrink is not considered, perimeters are the borderlines */ + size_t start_x = 1; + size_t end_x = grid.width() - 1; + if (perimeter_cb) { + start_x = 0; + end_x = grid.width(); + } for (size_t iy = 0; iy < grid.height() - 1; ++iy) { - for (size_t ix = 1; ix < grid.width() - 1; ++ix) { + for (size_t ix = start_x; ix < end_x; ++ix) { chanx_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({(int)ix, (int)iy + 1, 0})); } } + size_t start_y = 1; + size_t end_y = grid.height() - 1; + if (perimeter_cb) { + start_y = 0; + end_y = grid.height(); + } for (size_t ix = 0; ix < grid.width() - 1; ++ix) { - for (size_t iy = 1; iy < grid.height() - 1; ++iy) { + for (size_t iy = start_y; iy < end_y; ++iy) { chany_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({(int)ix, (int)iy, 0})); } } diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.h b/vpr/src/tileable_rr_graph/device_grid_annotation.h index 377c850909b..85e1156f60d 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.h +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.h @@ -15,7 +15,7 @@ */ class DeviceGridAnnotation { public: /* Constructor */ - DeviceGridAnnotation(const DeviceGrid& grid); + DeviceGridAnnotation(const DeviceGrid& grid, const bool& perimeter_cb); private: /* Private mutators */ void alloc(const DeviceGrid& grid); diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index a515e55f218..fa757afe6fe 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -199,8 +199,15 @@ size_t get_grid_num_classes(const DeviceGrid& grids, bool is_chanx_exist(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chanx_coord, + const bool& perimeter_cb, const bool& through_channel) { - if ((1 > chanx_coord.x()) || (chanx_coord.x() > grids.width() - 2)) { + size_t chanx_start = 1; + size_t chanx_end = grids.width() - 2; + if (perimeter_cb) { + chanx_start = 0; + chanx_end = grids.width() - 1; + } + if ((chanx_start > chanx_coord.x()) || (chanx_coord.x() > chanx_end)) { return false; } @@ -238,12 +245,19 @@ bool is_chanx_exist(const DeviceGrid& grids, bool is_chany_exist(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chany_coord, + const bool& perimeter_cb, const bool& through_channel) { + size_t chany_start = 1; + size_t chany_end = grids.height() - 2; + if (perimeter_cb) { + chany_start = 0; + chany_end = grids.height() - 1; + } if (chany_coord.x() > grids.width() - 2) { return false; } - if ((1 > chany_coord.y()) || (chany_coord.y() > grids.height() - 2)) { + if ((chany_start > chany_coord.y()) || (chany_coord.y() > chany_end)) { return false; } @@ -270,9 +284,14 @@ bool is_chany_exist(const DeviceGrid& grids, bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chanx_coord, + const bool& perimeter_cb, const bool& through_channel) { - VTR_ASSERT(0 < chanx_coord.x()); - if (1 == chanx_coord.x()) { + VTR_ASSERT(0 <= chanx_coord.x()); + size_t start_x = 1; + if (perimeter_cb) { + start_x = 0; + } + if (start_x == chanx_coord.x()) { /* This is already the LEFT side of FPGA fabric, * it is the same results as chanx is right to a multi-height grid */ @@ -282,7 +301,7 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ vtr::Point left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y()); - if (false == is_chanx_exist(grids, layer, left_chanx_coord)) { + if (false == is_chanx_exist(grids, layer, left_chanx_coord, perimeter_cb)) { return true; } } @@ -306,9 +325,15 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chanx_coord, + const bool& perimeter_cb, const bool& through_channel) { - VTR_ASSERT(chanx_coord.x() < grids.width() - 1); - if (grids.width() - 2 == chanx_coord.x()) { + VTR_ASSERT(chanx_coord.x() <= grids.width() - 1); + size_t end_x = grids.width() - 2; + if (perimeter_cb) { + end_x = grids.width() - 1; + } + + if (end_x == chanx_coord.x()) { /* This is already the RIGHT side of FPGA fabric, * it is the same results as chanx is right to a multi-height grid */ @@ -318,7 +343,7 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ vtr::Point right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y()); - if (false == is_chanx_exist(grids, layer, right_chanx_coord)) { + if (false == is_chanx_exist(grids, layer, right_chanx_coord, perimeter_cb)) { return true; } } @@ -347,9 +372,14 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chany_coord, + const bool& perimeter_cb, const bool& through_channel) { - VTR_ASSERT(0 < chany_coord.y()); - if (1 == chany_coord.y()) { + VTR_ASSERT(0 <= chany_coord.y()); + size_t start_y = 1; + if (perimeter_cb) { + start_y = 0; + } + if (start_y == chany_coord.y()) { /* This is already the BOTTOM side of FPGA fabric, * it is the same results as chany is at the top of a multi-width grid */ @@ -359,7 +389,7 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the bottom neighbor of chany, if it does not exist, the chany is top to a multi-height grid */ vtr::Point bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1); - if (false == is_chany_exist(grids, layer, bottom_chany_coord)) { + if (false == is_chany_exist(grids, layer, bottom_chany_coord, perimeter_cb)) { return true; } } @@ -388,9 +418,15 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chany_coord, + const bool& perimeter_cb, const bool& through_channel) { - VTR_ASSERT(chany_coord.y() < grids.height() - 1); - if (grids.height() - 2 == chany_coord.y()) { + VTR_ASSERT(chany_coord.y() <= grids.height() - 1); + size_t end_y = grids.height() - 2; + if (perimeter_cb) { + end_y = grids.height() - 1; + } + + if (end_y == chany_coord.y()) { /* This is already the TOP side of FPGA fabric, * it is the same results as chany is at the bottom of a multi-width grid */ @@ -400,7 +436,7 @@ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, if (false == through_channel) { /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */ vtr::Point top_chany_coord(chany_coord.x(), chany_coord.y() + 1); - if (false == is_chany_exist(grids, layer, top_chany_coord)) { + if (false == is_chany_exist(grids, layer, top_chany_coord, perimeter_cb)) { return true; } } diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index f53b350de45..382694f7ef4 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -55,11 +55,13 @@ size_t get_grid_num_classes(const DeviceGrid& grids, bool is_chanx_exist(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chanx_coord, + const bool& perimeter_cb, const bool& through_channel = false); bool is_chany_exist(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chany_coord, + const bool& perimeter_cb, const bool& through_channel = false); bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 0059042c9d1..113927cc471 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -107,7 +107,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ DeviceContext& device_ctx = g_vpr_ctx.mutable_device(); /* Annotate the device grid on the boundry */ - DeviceGridAnnotation device_grid_annotation(device_ctx.grid); + DeviceGridAnnotation device_grid_annotation(device_ctx.grid, perimeter_cb); /* The number of segments are in general small, reserve segments may not bring * significant memory efficiency */ @@ -166,6 +166,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ segment_inf_x, segment_inf_y, device_grid_annotation, shrink_boundary, + perimeter_cb, through_channel); /************************ @@ -184,6 +185,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ delayless_rr_switch, device_grid_annotation, shrink_boundary, + perimeter_cb, through_channel); /************************************************************************ @@ -257,6 +259,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ segment_inf, segment_inf_x, segment_inf_y, Fc_in, Fc_out, sb_type, Fs, sb_subtype, subFs, + perimeter_cb, opin2all_sides, concat_wire, wire_opposite_side); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 93612de2fcc..e974db8c8b3 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -116,6 +116,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const int& Fs, const e_switch_block_type& sb_subtype, const int& subFs, + const bool& perimeter_cb, const bool& opin2all_sides, const bool& concat_wire, const bool& wire_opposite_side) { @@ -125,6 +126,9 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); + if (perimeter_cb) { + gsb_range.set(grids.width() - 1, grids.height() - 1); + } /* Go Switch Block by Switch Block */ for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 06b3a1f3f64..8d91829415d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -36,6 +36,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const int& Fs, const e_switch_block_type& sb_subtype, const int& subFs, + const bool& perimeter_cb, const bool& opin2all_sides, const bool& concat_wire, const bool& wire_opposite_side); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 35fd30101ce..58df142e0b7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -179,16 +179,28 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, const std::vector& segment_infs, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel) { size_t num_chanx_rr_nodes = 0; + /* Default x-channel boundary box */ + size_t start_x = 1; + size_t end_x = grids.width() - 1; + if (perimeter_cb) { + start_x = 0; + end_x = grids.width(); + } + size_t max_seg_length = grids.width() - 2; + if (perimeter_cb) { + max_seg_length = grids.width(); + } for (size_t iy = 0; iy < grids.height() - 1; ++iy) { - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t ix = start_x; ix < end_x; ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are not allowed */ if ((false == through_channel) - && (false == is_chanx_exist(grids, layer, chanx_coord))) { + && (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } /* Bypass if the routing channel does not exist when a shrink boundary is considered */ @@ -203,7 +215,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { + if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, perimeter_cb, through_channel)) { force_start = true; } if (shrink_boundary && device_grid_annotation.is_chanx_start(chanx_coord)) { @@ -214,7 +226,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { + if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, perimeter_cb, through_channel)) { force_end = true; } if (shrink_boundary && device_grid_annotation.is_chanx_end(chanx_coord)) { @@ -222,7 +234,7 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, } /* Evaluate if the routing channel locates in the middle of a grid */ - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, max_seg_length, force_start, force_end, segment_infs); /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ @@ -244,16 +256,28 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, const std::vector& segment_infs, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel) { size_t num_chany_rr_nodes = 0; + /* Default x-channel boundary box */ + size_t start_y = 1; + size_t end_y = grids.height() - 1; + if (perimeter_cb) { + start_y = 0; + end_y = grids.height(); + } + size_t max_seg_length = grids.height() - 2; + if (perimeter_cb) { + max_seg_length = grids.height(); + } for (size_t ix = 0; ix < grids.width() - 1; ++ix) { - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + for (size_t iy = start_y; iy < end_y; ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are not allowed */ if ((false == through_channel) - && (false == is_chany_exist(grids, layer, chany_coord))) { + && (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } @@ -269,7 +293,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { + if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, perimeter_cb, through_channel)) { force_start = true; } if (shrink_boundary && device_grid_annotation.is_chany_start(chany_coord)) { @@ -280,14 +304,14 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { + if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, perimeter_cb, through_channel)) { force_end = true; } if (shrink_boundary && device_grid_annotation.is_chany_end(chany_coord)) { force_end = true; } - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, seg_max_length, force_start, force_end, segment_infs); /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ @@ -308,6 +332,7 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, const std::vector& segment_inf_y, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel) { /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); @@ -340,12 +365,14 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, segment_inf_x, device_grid_annotation, shrink_boundary, + perimeter_cb, through_channel); num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, layer, chan_width.y(), segment_inf_y, device_grid_annotation, shrink_boundary, + perimeter_cb, through_channel); return num_rr_nodes_per_type; @@ -367,6 +394,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const std::vector& segment_inf_y, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel) { VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); @@ -377,6 +405,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, segment_inf_y, device_grid_annotation, shrink_boundary, + perimeter_cb, through_channel); /* Reserve the number of node to be memory efficient */ @@ -878,18 +907,30 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, const t_unified_to_parallel_seg_index& segment_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel) { + size_t start_x = 1; + size_t end_x = grids.width() - 1; + if (perimeter_cb) { + start_x = 0; + end_x = grids.width(); + } + size_t max_seg_length = grids.width() - 2; + if (perimeter_cb) { + max_seg_length = grids.width(); + } + /* For X-direction Channel: CHANX */ for (size_t iy = 0; iy < grids.height() - 1; ++iy) { /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ std::vector track_node_ids; - for (size_t ix = 1; ix < grids.width() - 1; ++ix) { + for (size_t ix = start_x; ix < end_x; ++ix) { vtr::Point chanx_coord(ix, iy); /* Bypass if the routing channel does not exist when through channels are not allowed */ if ((false == through_channel) - && (false == is_chanx_exist(grids, layer, chanx_coord))) { + && (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { continue; } /* Bypass if the routing channel does not exist when a shrink boundary is considered */ @@ -904,7 +945,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, * - the routing channel touch the RIGHT side a heterogeneous block * - the routing channel touch the LEFT side of FPGA */ - if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { + if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, perimeter_cb, through_channel)) { force_start = true; } if (shrink_boundary && device_grid_annotation.is_chanx_start(chanx_coord)) { @@ -915,14 +956,14 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, * - the routing channel touch the LEFT side a heterogeneous block * - the routing channel touch the RIGHT side of FPGA */ - if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, through_channel)) { + if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, perimeter_cb, through_channel)) { force_end = true; } if (shrink_boundary && device_grid_annotation.is_chanx_end(chanx_coord)) { force_end = true; } - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, max_seg_length, force_start, force_end, segment_infs); /* Force node_ids from the previous chanx */ if (0 < track_node_ids.size()) { @@ -930,7 +971,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, * Tracks on the borders are not regularly started and ended, * which causes the node_rotation malfunction */ - ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2, + ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, max_seg_length, false, false, segment_infs); chanx_details_tt.set_track_node_ids(track_node_ids); @@ -946,7 +987,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, * track0 ----->+-----------------------------+----> track0 * | | */ - if (true == is_chanx_exist(grids, layer, chanx_coord, through_channel)) { + if (true == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb, through_channel)) { /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D @@ -1003,18 +1044,31 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, const t_unified_to_parallel_seg_index& seg_index_map, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel) { + /* Default y-channel boundary box */ + size_t start_y = 1; + size_t end_y = grids.height() - 1; + if (perimeter_cb) { + start_y = 0; + end_y = grids.height(); + } + size_t max_seg_length = grids.height() - 2; + if (perimeter_cb) { + max_seg_length = grids.height(); + } + /* For Y-direction Channel: CHANY */ for (size_t ix = 0; ix < grids.width() - 1; ++ix) { /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ std::vector track_node_ids; - for (size_t iy = 1; iy < grids.height() - 1; ++iy) { + for (size_t iy = start_y; iy < end_y; ++iy) { vtr::Point chany_coord(ix, iy); /* Bypass if the routing channel does not exist when through channel are not allowed */ if ((false == through_channel) - && (false == is_chany_exist(grids, layer, chany_coord))) { + && (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { continue; } /* Bypass if the routing channel does not exist when a shrink boundary is considered */ @@ -1029,7 +1083,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, * - the routing channel touch the TOP side a heterogeneous block * - the routing channel touch the BOTTOM side of FPGA */ - if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { + if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, perimeter_cb, through_channel)) { force_start = true; } if (shrink_boundary && device_grid_annotation.is_chany_start(chany_coord)) { @@ -1040,14 +1094,14 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, * - the routing channel touch the BOTTOM side a heterogeneous block * - the routing channel touch the TOP side of FPGA */ - if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, through_channel)) { + if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, perimeter_cb, through_channel)) { force_end = true; } if (shrink_boundary && device_grid_annotation.is_chany_end(chany_coord)) { force_end = true; } - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, max_seg_length, force_start, force_end, segment_infs); /* Force node_ids from the previous chany * This will not be applied when the routing channel is cut off (force to start) @@ -1057,7 +1111,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, * Tracks on the borders are not regularly started and ended, * which causes the node_rotation malfunction */ - ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2, + ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, max_seg_length, false, false, segment_infs); chany_details_tt.set_track_node_ids(track_node_ids); @@ -1075,7 +1129,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, * | | * we should rotate only once at the bottom side of a grid */ - if (true == is_chany_exist(grids, layer, chany_coord, through_channel)) { + if (true == is_chany_exist(grids, layer, chany_coord, perimeter_cb, through_channel)) { /* Rotate the chany_details by an offset of 1*/ /* For INC_DIRECTION, we use clockwise rotation * node_id A ----> -----> node_id D @@ -1155,6 +1209,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const RRSwitchId& delayless_switch, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel) { /* Allocates and loads all the structures needed for fast lookups of the * * index of an rr_node. rr_node_indices is a matrix containing the index * @@ -1189,6 +1244,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, segment_index_map, device_grid_annotation, shrink_boundary, + perimeter_cb, through_channel); load_chany_rr_nodes_basic_info(rr_graph, @@ -1203,6 +1259,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, segment_index_map, device_grid_annotation, shrink_boundary, + perimeter_cb, through_channel); reverse_dec_chan_rr_node_track_ids(rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 27fea172338..b8165d1f658 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -31,6 +31,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const std::vector& segment_inf_y, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel); void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, @@ -48,6 +49,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const RRSwitchId& delayless_switch, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, + const bool& perimeter_cb, const bool& through_channel); #endif From e4e158db9e2c74a65795e0c4521c1ebfa59caf38 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 14:20:36 -0700 Subject: [PATCH 287/453] [vpr] syntax --- vpr/src/tileable_rr_graph/device_grid_annotation.h | 2 +- vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp | 6 ++++-- vpr/src/tileable_rr_graph/rr_graph_builder_utils.h | 4 ++++ .../tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 2 +- 4 files changed, 10 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.h b/vpr/src/tileable_rr_graph/device_grid_annotation.h index 85e1156f60d..6f3f3bad343 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.h +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.h @@ -19,7 +19,7 @@ class DeviceGridAnnotation { private: /* Private mutators */ void alloc(const DeviceGrid& grid); - void init(const DeviceGrid& grid); + void init(const DeviceGrid& grid, const bool& perimeter_cb); public: /* Public accessors */ /** @brief Check if at a given coordinate, a X-direction routing channel should exist or not */ diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index fa757afe6fe..cc6f2900b7c 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -286,10 +286,11 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, const vtr::Point& chanx_coord, const bool& perimeter_cb, const bool& through_channel) { - VTR_ASSERT(0 <= chanx_coord.x()); size_t start_x = 1; if (perimeter_cb) { start_x = 0; + } else { + VTR_ASSERT(0 < chanx_coord.x()); } if (start_x == chanx_coord.x()) { /* This is already the LEFT side of FPGA fabric, @@ -374,10 +375,11 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, const vtr::Point& chany_coord, const bool& perimeter_cb, const bool& through_channel) { - VTR_ASSERT(0 <= chany_coord.y()); size_t start_y = 1; if (perimeter_cb) { start_y = 0; + } else { + VTR_ASSERT(0 < chany_coord.y()); } if (start_y == chany_coord.y()) { /* This is already the BOTTOM side of FPGA fabric, diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index 382694f7ef4..2740dddd160 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -67,21 +67,25 @@ bool is_chany_exist(const DeviceGrid& grids, bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chanx_coord, + const bool& perimeter_cb, const bool& through_channel); bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chanx_coord, + const bool& perimeter_cb, const bool& through_channel); bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chany_coord, + const bool& perimeter_cb, const bool& through_channel); bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, const size_t& layer, const vtr::Point& chany_coord, + const bool& perimeter_cb, const bool& through_channel); short get_rr_node_actual_track_id(const RRGraph& rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 58df142e0b7..c2c9f00ea4d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -311,7 +311,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, force_end = true; } - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, seg_max_length, force_start, force_end, segment_infs); + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, max_seg_length, force_start, force_end, segment_infs); /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ From 57dc489abf9c4a33f57642548c050936a58c4e77 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 14:38:59 -0700 Subject: [PATCH 288/453] [test] add perimeter_cb to strong test --- .../k4_N4_tileable_perimeter_cb_90nm.xml | 199 ++++++++++++++++++ .../vtr_reg_strong/task_list.txt | 3 +- 2 files changed, 201 insertions(+), 1 deletion(-) create mode 100644 vtr_flow/arch/timing/k4_N4_tileable_perimeter_cb_90nm.xml diff --git a/vtr_flow/arch/timing/k4_N4_tileable_perimeter_cb_90nm.xml b/vtr_flow/arch/timing/k4_N4_tileable_perimeter_cb_90nm.xml new file mode 100644 index 00000000000..33eab099c51 --- /dev/null +++ b/vtr_flow/arch/timing/k4_N4_tileable_perimeter_cb_90nm.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2.253000e-10 + 2.253000e-10 + 2.253000e-10 + 2.253000e-10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 93d5c3dda79..a6fc3bc3a3c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -84,8 +84,9 @@ regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail regression_tests/vtr_reg_strong/strong_vpr_constraint regression_tests/vtr_reg_strong/strong_tileable_rr_graph +regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router -regression_tests/vtr_reg_strong/strong_routing_constraints \ No newline at end of file +regression_tests/vtr_reg_strong/strong_routing_constraints From 46dd4bfc7afb646557cbe487baba535432c8ce7b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 14:47:22 -0700 Subject: [PATCH 289/453] [test] add new test --- .../config/config.txt | 29 +++++++++++++++++++ .../config/golden_results.txt | 4 +++ 2 files changed, 33 insertions(+) create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/config.txt new file mode 100755 index 00000000000..f06f65791c8 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/config.txt @@ -0,0 +1,29 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/4 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=diffeq.blif +circuit_list_add=ex5p.blif +circuit_list_add=s298.blif + +# Add architectures to list to sweep +arch_list_add=k4_N4_tileable_perimeter_cb_90nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +script_params=-starting_stage vpr -track_memory_usage + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt new file mode 100644 index 00000000000..8576e7f7dc7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 +k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 +k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 From c1f3c802c32d287adb4b88b1670322580415892d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 15:11:16 -0700 Subject: [PATCH 290/453] [vpr] fixed a bug on access invalid grid nodes --- vpr/src/tileable_rr_graph/rr_graph_view_util.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index eee1d94b740..9a1a1361274 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -101,7 +101,9 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); /* Ensure that (x, y) is a valid location in grids */ - VTR_ASSERT(size_t(x) <= device_grid.width() && size_t(y) <= device_grid.height()); + if (size_t(x) > device_grid.width() - 1 || size_t(y) > device_grid.height() - 1) { + return indices; + } /* Ensure we have a valid side */ VTR_ASSERT(side != NUM_SIDES); @@ -110,6 +112,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, t_physical_tile_loc tile_loc(x, y, layer); int width_offset = device_grid.get_width_offset(tile_loc); int height_offset = device_grid.get_height_offset(tile_loc); + for (int pin = 0; pin < device_grid.get_physical_type(tile_loc)->num_pins; ++pin) { /* Skip those pins have been ignored during rr_graph build-up */ if (true == device_grid.get_physical_type(tile_loc)->is_ignored_pin[pin]) { From 76d69fb9542bcf7f69554f2ca15c2a4ab344688b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 15:16:21 -0700 Subject: [PATCH 291/453] [lib] relax check_rr_node on (x, y) range as now CHANX and CHANY can occur at perimeter --- libs/librrgraph/src/base/check_rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index ec452383f70..f9015c36e56 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -412,7 +412,7 @@ void check_rr_node(const RRGraphView& rr_graph, break; case CHANX: - if (xlow < 1 || xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 2 || yhigh != ylow) { + if (xhigh > int(grid.width()) - 1 || yhigh > int(grid.height()) - 2 || yhigh != ylow) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); } @@ -423,7 +423,7 @@ void check_rr_node(const RRGraphView& rr_graph, break; case CHANY: - if (xhigh > int(grid.width()) - 2 || ylow < 1 || yhigh > int(grid.height()) - 2 || xlow != xhigh) { + if (xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 1 || xlow != xhigh) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Error in check_rr_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); } From 64bbd2454e81ea4790b27a7846cd5e454f5bc3f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 21:47:41 -0700 Subject: [PATCH 292/453] [vpr] typo on debug string --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 7911ebd68de..123481fb569 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -519,7 +519,7 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, VTR_LOG("Cannot find a node on the opposite side to GSB[%lu][%lu] track node[%lu] at %s!\nDetailed node information:\n", get_x(), get_y(), track_id, SIDE_STRING[node_side]); VTR_LOG("Node type: %s\n", rr_graph.node_type_string(track_node)); - VTR_LOG("Node coordinate: %d\n", rr_graph.node_coordinate_to_string(track_node).c_str()); + VTR_LOG("Node coordinate: %s\n", rr_graph.node_coordinate_to_string(track_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(track_node)); } VTR_ASSERT(true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)); From 7aa23041f18ce07a10b62fa7459166f613d039d2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 22:27:42 -0700 Subject: [PATCH 293/453] [vpr] fix minor bug where sort edge is not applicable to boundary gsbs when perimeter_cb is on --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 123481fb569..1f611a7dc22 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -878,6 +878,10 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph) { for (size_t side = 0; side < get_num_sides(); ++side) { SideManager side_manager(side); + /* Bypass boundary GSBs here. When perimeter_cb option is on, Some GSBs may have only 1 side of CHANX or CHANY. There are no edges in the GSB, so we should skip them */ + if (chan_node_[side_manager.get_opposite()].get_chan_width() == 0) { + continue; + } chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width()); for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) { /* Only sort the output nodes and bypass passing wires */ From 97c106cd89bcd3c4a6d29dfea5101cd15554d3f3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 22:33:21 -0700 Subject: [PATCH 294/453] [vpr] fixing a bug where sorted edges are not located --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 1f611a7dc22..365ef410586 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -879,10 +879,10 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph) { for (size_t side = 0; side < get_num_sides(); ++side) { SideManager side_manager(side); /* Bypass boundary GSBs here. When perimeter_cb option is on, Some GSBs may have only 1 side of CHANX or CHANY. There are no edges in the GSB, so we should skip them */ + chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width()); if (chan_node_[side_manager.get_opposite()].get_chan_width() == 0) { continue; } - chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width()); for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) { /* Only sort the output nodes and bypass passing wires */ if ((OUT_PORT == chan_node_direction_[side][track_id]) From b172d26a0c75dbabdaf78fc37d6260f74f22ff4c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:15:39 -0700 Subject: [PATCH 295/453] [vpr] now when cb on perimeter, I/O pins can access three sides --- .../rr_graph_builder_utils.cpp | 61 +++++++++++++------ .../rr_graph_builder_utils.h | 7 ++- .../tileable_rr_graph_node_builder.cpp | 57 ++++++----------- 3 files changed, 64 insertions(+), 61 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index cc6f2900b7c..6b8aa9d8e5d 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -43,26 +43,54 @@ int get_grid_pin_class_index(const DeviceGrid& grids, } /* Deteremine the side of a io grid */ -e_side determine_io_grid_pin_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate) { +std::vector determine_io_grid_pin_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate, + const bool& perimeter_cb) { + std::vector pin_sides; /* TOP side IO of FPGA */ if (device_size.y() == grid_coordinate.y()) { - return BOTTOM; /* Such I/O has only Bottom side pins */ + /* Such I/O has only bottom side pins */ + pin_sides.push_back(BOTTOM); + /* If cbs are allowed around boundary I/Os, add two more sides */ + if (perimeter_cb) { + pin_sides.push_back(LEFT); + pin_sides.push_back(RIGHT); + } } else if (device_size.x() == grid_coordinate.x()) { /* RIGHT side IO of FPGA */ - return LEFT; /* Such I/O has only Left side pins */ + /* Such I/O has only Left side pins */ + pin_sides.push_back(LEFT); + /* If cbs are allowed around boundary I/Os, add two more sides */ + if (perimeter_cb) { + pin_sides.push_back(TOP); + pin_sides.push_back(BOTTOM); + } } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ - return TOP; /* Such I/O has only Top side pins */ + /* Such I/O has only Top side pins */ + pin_sides.push_back(TOP); + /* If cbs are allowed around boundary I/Os, add two more sides */ + if (perimeter_cb) { + pin_sides.push_back(LEFT); + pin_sides.push_back(RIGHT); + } } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ - return RIGHT; /* Such I/O has only Right side pins */ + /* Such I/O has only Right side pins */ + pin_sides.push_back(RIGHT); + /* If cbs are allowed around boundary I/Os, add two more sides */ + if (perimeter_cb) { + pin_sides.push_back(TOP); + pin_sides.push_back(BOTTOM); + } } else if ((grid_coordinate.x() < device_size.x()) && (grid_coordinate.y() < device_size.y())) { /* I/O grid in the center grid */ return NUM_SIDES; - } - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n", - grid_coordinate.x(), grid_coordinate.y(), - device_size.x(), device_size.y()); - exit(1); + } else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n", + grid_coordinate.x(), grid_coordinate.y(), + device_size.x(), device_size.y()); + exit(1); + } + return pin_sides; } /* Deteremine the side of a pin of a grid */ @@ -124,17 +152,12 @@ size_t get_grid_num_pins(const DeviceGrid& grids, const size_t& x, const size_t& y, const e_pin_type& pin_type, - const e_side& io_side) { + const std::vector& io_side) { size_t num_pins = 0; /* For IO_TYPE sides */ t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); - for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { - /* skip unwanted sides */ - if ((true == is_io_type(phy_tile_type)) - && (side != io_side) && (NUM_SIDES != io_side)) { - continue; - } + for (const e_side& side : io_side) { /* Get pin list */ for (int width = 0; width < phy_tile_type->width; ++width) { for (int height = 0; height < phy_tile_type->height; ++height) { diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index 2740dddd160..c73ebb8206f 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -27,8 +27,9 @@ std::vector find_grid_pin_sides(const DeviceGrid& grids, const size_t& y, const size_t& pin_id); -e_side determine_io_grid_pin_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate); +std::vector determine_io_grid_pin_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate, + const bool& perimeter_cb); std::vector get_grid_side_pins(const DeviceGrid& grids, const size_t& layer, @@ -44,7 +45,7 @@ size_t get_grid_num_pins(const DeviceGrid& grids, const size_t& x, const size_t& y, const e_pin_type& pin_type, - const e_side& io_side); + const std::vector& io_side); size_t get_grid_num_classes(const DeviceGrid& grids, const size_t& layer, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index c2c9f00ea4d..b74ba94d83f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -26,7 +26,8 @@ ***********************************************************************/ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, const size_t& layer, - const t_rr_type& node_type) { + const t_rr_type& node_type, + const bool& perimeter_cb) { size_t num_grid_rr_nodes = 0; for (size_t ix = 0; ix < grids.width(); ++ix) { @@ -43,13 +44,13 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, continue; } - enum e_side io_side = NUM_SIDES; + std::vector io_side = {TOP, RIGHT, BOTTOM, LEFT}; /* If this is the block on borders, we consider IO side */ if (true == is_io_type(grids.get_physical_type(tile_loc))) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); vtr::Point grid_coordinate(ix, iy); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb); } switch (node_type) { @@ -340,10 +341,10 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, /** * 1 Find number of rr nodes related to grids */ - num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, OPIN); - num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN); - num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE); - num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK); + num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, OPIN, perimeter_cb); + num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN, perimeter_cb); + num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE, perimeter_cb); + num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK, perimeter_cb); /** * 2. Assign the segments for each routing channel, @@ -432,10 +433,8 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder const size_t& layer, const vtr::Point& grid_coordinate, const DeviceGrid& grids, - const e_side& io_side, + const std::vector& wanted_sides, const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - /* Walk through the width height of each grid, * get pins and configure the rr_nodes */ @@ -443,13 +442,8 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder for (int width = 0; width < phy_tile_type->width; ++width) { for (int height = 0; height < phy_tile_type->height; ++height) { /* Walk through sides */ - for (e_side side : SIDES) { + for (e_side side : wanted_sides) { SideManager side_manager(side); - /* skip unwanted sides */ - if ((true == is_io_type(phy_tile_type)) - && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { - continue; - } /* Find OPINs */ /* Configure pins by pins */ std::vector opin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), DRIVER, side_manager.get_side(), @@ -497,7 +491,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder const size_t& layer, const vtr::Point& grid_coordinate, const DeviceGrid& grids, - const e_side& io_side, + const std::vector& wanted_sides, const RRSwitchId& wire_to_ipin_switch) { SideManager io_side_manager(io_side); @@ -508,14 +502,8 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder for (int width = 0; width < phy_tile_type->width; ++width) { for (int height = 0; height < phy_tile_type->height; ++height) { /* Walk through sides */ - for (e_side side : SIDES) { + for (e_side side : wanted_sides) { SideManager side_manager(side); - /* skip unwanted sides */ - if ((true == is_io_type(phy_tile_type)) - && (side != io_side_manager.to_size_t()) && (NUM_SIDES != io_side)) { - continue; - } - /* Find IPINs */ /* Configure pins by pins */ std::vector ipin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height); @@ -562,10 +550,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build const size_t& layer, const vtr::Point& grid_coordinate, const DeviceGrid& grids, - const e_side& io_side, const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - /* Set a SOURCE rr_node for each DRIVER class */ t_physical_tile_loc tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer); t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); @@ -614,10 +599,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder const size_t& layer, const vtr::Point& grid_coordinate, const DeviceGrid& grids, - const e_side& io_side, const RRSwitchId& delayless_switch) { - SideManager io_side_manager(io_side); - /* Set a SINK rr_node for each RECEIVER class */ t_physical_tile_loc tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer); t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); @@ -664,7 +646,8 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, const DeviceGrid& grids, const size_t& layer, const RRSwitchId& wire_to_ipin_switch, - const RRSwitchId& delayless_switch) { + const RRSwitchId& delayless_switch, + const bool& perimeter_cb) { for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { t_physical_tile_loc tile_loc(ix, iy, layer); @@ -687,9 +670,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, /* If this is the block on borders, we consider IO side */ if (true == is_io_type(grids.get_physical_type(tile_loc))) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate); - wanted_sides.clear(); - wanted_sides.push_back(io_side); + wanted_sides = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb); } for (e_side side : wanted_sides) { @@ -709,7 +690,6 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_rc_data, layer, grid_coordinate, grids, - io_side, delayless_switch); /* Configure sink rr_nodes for this grid */ @@ -718,7 +698,6 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_rc_data, layer, grid_coordinate, grids, - io_side, delayless_switch); /* Configure opin rr_nodes for this grid */ @@ -727,7 +706,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_rc_data, layer, grid_coordinate, grids, - io_side, + wanted_sides, delayless_switch); /* Configure ipin rr_nodes for this grid */ @@ -736,7 +715,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_rc_data, layer, grid_coordinate, grids, - io_side, + wanted_sides, wire_to_ipin_switch); } } @@ -1231,7 +1210,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, rr_rc_data, grids, layer, wire_to_ipin_switch, - delayless_switch); + delayless_switch, perimeter_cb); load_chanx_rr_nodes_basic_info(rr_graph, rr_graph_builder, From ae9eb2dbb0e685d6a2bff11d01713498f12e2b27 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:18:02 -0700 Subject: [PATCH 296/453] [vpr] syntax --- vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 6b8aa9d8e5d..3b9e21bab9b 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -82,7 +82,7 @@ std::vector determine_io_grid_pin_side(const vtr::Point& device_ } } else if ((grid_coordinate.x() < device_size.x()) && (grid_coordinate.y() < device_size.y())) { /* I/O grid in the center grid */ - return NUM_SIDES; + return {TOP, RIGHT, BOTTOM, LEFT}; } else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n", From b9bc0cbcdee0684ed0c0feb49d12f74cff304e36 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:19:15 -0700 Subject: [PATCH 297/453] [vpr] syntax --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index b74ba94d83f..7063fce6623 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -493,8 +493,6 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder const DeviceGrid& grids, const std::vector& wanted_sides, const RRSwitchId& wire_to_ipin_switch) { - SideManager io_side_manager(io_side); - /* Walk through the width and height of each grid, * get pins and configure the rr_nodes */ From 159bea4ff7e2df8eedaa219cf1765b5dee1921f1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 12:20:03 -0700 Subject: [PATCH 298/453] [vpr] syntax --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 7063fce6623..e9510133acd 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -661,8 +661,6 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, } vtr::Point grid_coordinate(ix, iy); - enum e_side io_side = NUM_SIDES; - std::vector wanted_sides{TOP, RIGHT, BOTTOM, LEFT}; /* If this is the block on borders, we consider IO side */ From fbbf53d8207d55df8c6c62e1a0505f94ccba612a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 13:15:09 -0700 Subject: [PATCH 299/453] [vpr] fixed a bug where perimeter cb are not connected to adjancet sbs --- .../tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 2 +- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 7 ++++--- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 3 ++- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index e974db8c8b3..471f68ad49c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -139,7 +139,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* Create a GSB object */ const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, device_chan_width, segment_inf_x, segment_inf_y, - layer, gsb_coord); + layer, gsb_coord, perimeter_cb); /* adapt the track_to_ipin_lookup for the GSB nodes */ t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 79f4166e190..01682243754 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -623,7 +623,8 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const std::vector& segment_inf_x, const std::vector& segment_inf_y, const size_t& layer, - const vtr::Point& gsb_coordinate) { + const vtr::Point& gsb_coordinate, + const bool& perimeter_cb) { /* Create an object to return */ RRGSB rr_gsb; @@ -719,7 +720,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case BOTTOM: /* BOTTOM = 2*/ /* For the bording, we should take special care */ - if (gsb_coordinate.y() == 0) { + if (!perimeter_cb && gsb_coordinate.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -749,7 +750,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case LEFT: /* LEFT = 3 */ /* For the bording, we should take special care */ - if (gsb_coordinate.x() == 0) { + if (!perimeter_cb && gsb_coordinate.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 4d3bbfdcc67..ca17517a8d9 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -47,7 +47,8 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const std::vector& segment_inf_x, const std::vector& segment_inf_y, const size_t& layer, - const vtr::Point& gsb_coordinate); + const vtr::Point& gsb_coordinate, + const bool& perimeter_cb); void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRGSB& rr_gsb, From 19fa43cc62bf7a38e4151c1c3867a760ba683719 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:46:35 -0700 Subject: [PATCH 300/453] [vpr] fixing some bugs in rr gsb --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 365ef410586..c04200f67ab 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -597,30 +597,12 @@ vtr::Point RRGSB::get_sb_coordinate() const { /* get the x coordinate of this X/Y-direction block */ size_t RRGSB::get_cb_x(const t_rr_type& cb_type) const { - VTR_ASSERT(validate_cb_type(cb_type)); - switch (cb_type) { - case CHANX: - return get_side_block_coordinate(LEFT).x(); - case CHANY: - return get_side_block_coordinate(TOP).x(); - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } + return get_cb_coordinate(cb_type).x(); } /* get the y coordinate of this X/Y-direction block */ size_t RRGSB::get_cb_y(const t_rr_type& cb_type) const { - VTR_ASSERT(validate_cb_type(cb_type)); - switch (cb_type) { - case CHANX: - return get_side_block_coordinate(LEFT).y(); - case CHANY: - return get_side_block_coordinate(TOP).y(); - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } + return get_cb_coordinate(cb_type).y(); } /* Get the coordinate of the X/Y-direction CB */ @@ -628,9 +610,9 @@ vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); switch (cb_type) { case CHANX: - return get_side_block_coordinate(LEFT); + return get_side_block_coordinate(BOTTOM); case CHANY: - return get_side_block_coordinate(TOP); + return get_side_block_coordinate(RIGHT); default: VTR_LOG("Invalid type of connection block!\n"); exit(1); From 589b6bcd8bd37ac445c55239af02c757223f5d4f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2024 14:54:29 -0700 Subject: [PATCH 301/453] [core] debug --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index c04200f67ab..21b06888d3e 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -610,9 +610,9 @@ vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); switch (cb_type) { case CHANX: - return get_side_block_coordinate(BOTTOM); + return get_side_block_coordinate(LEFT); case CHANY: - return get_side_block_coordinate(RIGHT); + return get_side_block_coordinate(TOP); default: VTR_LOG("Invalid type of connection block!\n"); exit(1); From e9d5647e06ef1dd1352864d7e7fc720c66fe3958 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 09:08:15 -0700 Subject: [PATCH 302/453] [vpr] now change to a simpler rr gsb coordinate system: grid is moved to the bottom-left corner --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 15 +++------------ vpr/src/tileable_rr_graph/rr_gsb.h | 11 +++++------ 2 files changed, 8 insertions(+), 18 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 21b06888d3e..6ae0b9425db 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -610,9 +610,9 @@ vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); switch (cb_type) { case CHANX: - return get_side_block_coordinate(LEFT); + return coordinate_; case CHANY: - return get_side_block_coordinate(TOP); + return coordinate_; default: VTR_LOG("Invalid type of connection block!\n"); exit(1); @@ -682,10 +682,7 @@ vtr::Point RRGSB::get_side_block_coordinate(const e_side& side) const { } vtr::Point RRGSB::get_grid_coordinate() const { - vtr::Point ret(get_sb_x(), get_sb_y()); - ret.set_y(ret.y() + 1); - - return ret; + return coordinate_; } /************************************************************************ @@ -1184,9 +1181,3 @@ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) con bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { return ((CHANX == cb_type) || (CHANY == cb_type)); } - -size_t RRGSB::get_cb_opin_type_id(const t_rr_type& cb_type) const { - VTR_ASSERT(validate_cb_type(cb_type)); - return cb_type == CHANX ? 0 : 1; -} - diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index bdbe3da91e0..539b8b2b09b 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -17,11 +17,6 @@ * 2. A X-direction Connection block locates at the left side of the switch block * 2. A Y-direction Connection block locates at the top side of the switch block * - * +-------------+ +---------------------------------+ - * | | | Y-direction CB | - * | Grid | | [x][y + 1] | - * | [x][y+1] | +---------------------------------+ - * +-------------+ * TOP SIDE * +-------------+ +---------------------------------+ * | | | OPIN_NODE CHAN_NODES OPIN_NODES | @@ -38,6 +33,11 @@ * | | | OPIN_NODE CHAN_NODES OPIN_NODES | * +-------------+ +---------------------------------+ * BOTTOM SIDE + * +-------------+ +---------------------------------+ + * | Grid | | Y-direction CB | + * | [x][y] | | [x][y] | + * +-------------+ +---------------------------------+ + * * num_sides: number of sides of this switch block * chan_rr_node: a collection of rr_nodes as routing tracks locating at each side of the Switch block <0..num_sides-1><0..chan_width-1> * chan_rr_node_direction: Indicate if this rr_node is an input or an output of the Switch block <0..num_sides-1><0..chan_width-1> @@ -229,7 +229,6 @@ class RRGSB { bool validate_opin_node_id(const e_side& side, const size_t& node_id) const; bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const; bool validate_cb_type(const t_rr_type& cb_type) const; - size_t get_cb_opin_type_id(const t_rr_type& cb_type) const; private: /* Internal Data */ /* Coordinator */ From d338952c3768e808e6511b9a8e32a1967b1a947b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:09:15 -0700 Subject: [PATCH 303/453] [vpr] update gsb builder in tileable rr graph for changing the coordindate system of gsb --- .../tileable_rr_graph_edge_builder.cpp | 5 +- .../tileable_rr_graph_gsb.cpp | 46 ++++++++++++++----- 2 files changed, 36 insertions(+), 15 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 471f68ad49c..baa97d8d348 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -125,10 +125,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); - vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); - if (perimeter_cb) { - gsb_range.set(grids.width() - 1, grids.height() - 1); - } + vtr::Point gsb_range(grids.width() - 1, grids.height() - 1); /* Go Switch Block by Switch Block */ for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 01682243754..429abaddd90 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -625,6 +625,30 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const size_t& layer, const vtr::Point& gsb_coordinate, const bool& perimeter_cb) { + /* Bounding box for GSB ranges on routing tracks. + * Note that when perimeter connection blocks are not allowed, + * - top side routing tracks for any GSB exist on y = [0, H-2) + * - right side routing tracks for any GSB exist on x = [0, W-2) + * - bottom side routing tracks for any GSB exist on y = [1, H-1) + * - left side routing tracks for any GSB exist on x = [1, W-1) + * Note that when perimeter connection blocks are allowed, + * - top side routing tracks for any GSB exist on y = [0, H-1) + * - right side routing tracks for any GSB exist on x = [0, W-1) + * - bottom side routing tracks for any GSB exist on y = [0, H) + * - left side routing tracks for any GSB exist on x = [0, W) + */ + size_t std::map> track_range; + track_range[TOP] = vtr:Point(0, grids.height() - 2); + track_range[RIGHT] = vtr:Point(0, grids.width() - 2); + track_range[BOTTOM] = vtr:Point(1, grids.height() - 2); + track_range[LEFT] = vtr:Point(1, grids.width() - 2); + if (perimeter_cb) { + track_range[TOP] = vtr:Point(0, grids.height() - 1); + track_range[RIGHT] = vtr:Point(0, grids.width() - 1); + track_range[BOTTOM] = vtr:Point(0, grids.height()); + track_range[LEFT] = vtr:Point(0, grids.width()); + } + /* Create an object to return */ RRGSB rr_gsb; @@ -659,8 +683,8 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, switch (side) { case TOP: /* TOP = 0 */ - /* For the bording, we should take special care */ - if (gsb_coordinate.y() == grids.height() - 1) { + /* For the border, we should take special care. The top column (H-1) does not have any top side routing channel. Any lower column may have (<= H-2) */ + if (track_range[side].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -689,8 +713,8 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case RIGHT: /* RIGHT = 1 */ - /* For the bording, we should take special care */ - if (gsb_coordinate.x() == grids.width() - 1) { + /* For the border, we should take special care. The rightmost column (W-1) does not have any right side routing channel. If perimeter connection block is not enabled, even the last second rightmost column (W-2) does not have any right side routing channel */ + if (track_range[side].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -719,8 +743,8 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - /* For the bording, we should take special care */ - if (!perimeter_cb && gsb_coordinate.y() == 0) { + /* For the border, we should take special care */ + if (track_range[side].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -749,8 +773,8 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - /* For the bording, we should take special care */ - if (!perimeter_cb && gsb_coordinate.x() == 0) { + /* For the border, we should take special care */ + if (track_range[side].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -846,7 +870,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, * - The concept of top/bottom side of connection block in GSB domain: * * ---------------+ +---------------------- ... ---------------------+ +---------------- - * Grid[x][y+1] |->| Y- Connection Block Y- Connection Block |<-| Grid[x+1][y+1] + * Grid[x][y] |->| Y- Connection Block Y- Connection Block |<-| Grid[x+1][y] * RIGHT side | | LEFT side ... RIGHT side | | LEFT side * --------------+ +---------------------- ... ---------------------+ +---------------- * @@ -873,7 +897,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, chan_side = TOP; /* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */ ix = rr_gsb.get_sb_x() + 1; - iy = rr_gsb.get_sb_y() + 1; + iy = rr_gsb.get_sb_y(); ipin_rr_node_grid_side = LEFT; break; case BOTTOM: @@ -889,7 +913,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, chan_side = TOP; /* The input pins of the routing channel come from the right side of Grid[x][y+1] */ ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; + iy = rr_gsb.get_sb_y(); ipin_rr_node_grid_side = RIGHT; break; default: From ba0576d43d1a019ff76d350b01332f0cc7bd32e3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:16:13 -0700 Subject: [PATCH 304/453] [vpr] syntax --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 5 ++++ vpr/src/tileable_rr_graph/rr_gsb.h | 1 + .../tileable_rr_graph_gsb.cpp | 26 +++++++++---------- 3 files changed, 19 insertions(+), 13 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 6ae0b9425db..8dc91462feb 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -1181,3 +1181,8 @@ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) con bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { return ((CHANX == cb_type) || (CHANY == cb_type)); } + +size_t RRGSB::get_cb_opin_type_id(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + return cb_type == CHANX ? 0 : 1; +} diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 539b8b2b09b..7a5206b48b5 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -229,6 +229,7 @@ class RRGSB { bool validate_opin_node_id(const e_side& side, const size_t& node_id) const; bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const; bool validate_cb_type(const t_rr_type& cb_type) const; + size_t get_cb_opin_type_id(const t_rr_type& cb_type) const; private: /* Internal Data */ /* Coordinator */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 429abaddd90..3c3f3b4aabe 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -637,16 +637,16 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, * - bottom side routing tracks for any GSB exist on y = [0, H) * - left side routing tracks for any GSB exist on x = [0, W) */ - size_t std::map> track_range; - track_range[TOP] = vtr:Point(0, grids.height() - 2); - track_range[RIGHT] = vtr:Point(0, grids.width() - 2); - track_range[BOTTOM] = vtr:Point(1, grids.height() - 2); - track_range[LEFT] = vtr:Point(1, grids.width() - 2); + std::map> track_range; + track_range[TOP] = vtr::Point(0, grids.height() - 2); + track_range[RIGHT] = vtr::Point(0, grids.width() - 2); + track_range[BOTTOM] = vtr::Point(1, grids.height() - 2); + track_range[LEFT] = vtr::Point(1, grids.width() - 2); if (perimeter_cb) { - track_range[TOP] = vtr:Point(0, grids.height() - 1); - track_range[RIGHT] = vtr:Point(0, grids.width() - 1); - track_range[BOTTOM] = vtr:Point(0, grids.height()); - track_range[LEFT] = vtr:Point(0, grids.width()); + track_range[TOP] = vtr::Point(0, grids.height() - 1); + track_range[RIGHT] = vtr::Point(0, grids.width() - 1); + track_range[BOTTOM] = vtr::Point(0, grids.height()); + track_range[LEFT] = vtr::Point(0, grids.width()); } /* Create an object to return */ @@ -684,7 +684,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, switch (side) { case TOP: /* TOP = 0 */ /* For the border, we should take special care. The top column (H-1) does not have any top side routing channel. Any lower column may have (<= H-2) */ - if (track_range[side].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -714,7 +714,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case RIGHT: /* RIGHT = 1 */ /* For the border, we should take special care. The rightmost column (W-1) does not have any right side routing channel. If perimeter connection block is not enabled, even the last second rightmost column (W-2) does not have any right side routing channel */ - if (track_range[side].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -744,7 +744,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case BOTTOM: /* BOTTOM = 2*/ /* For the border, we should take special care */ - if (track_range[side].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -774,7 +774,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case LEFT: /* LEFT = 3 */ /* For the border, we should take special care */ - if (track_range[side].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } From 826a10be4e6e45976f64ea3a0f6503516a8d777d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 10:51:59 -0700 Subject: [PATCH 305/453] [vpr] debugging --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index baa97d8d348..39ec645694f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -125,7 +125,10 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); - vtr::Point gsb_range(grids.width() - 1, grids.height() - 1); + vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); + if (perimeter_cb) { + gsb_range.set(grids.width() - 1, grids.height() - 1); + } /* Go Switch Block by Switch Block */ for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { From b06f2ee34036a8c981a2c202ec06251c1bb2b81a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:01:04 -0700 Subject: [PATCH 306/453] [core] fixed a bug where gsb nodes are not correctly added --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 3c3f3b4aabe..6fdc46c31af 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -684,7 +684,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, switch (side) { case TOP: /* TOP = 0 */ /* For the border, we should take special care. The top column (H-1) does not have any top side routing channel. Any lower column may have (<= H-2) */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -714,7 +714,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case RIGHT: /* RIGHT = 1 */ /* For the border, we should take special care. The rightmost column (W-1) does not have any right side routing channel. If perimeter connection block is not enabled, even the last second rightmost column (W-2) does not have any right side routing channel */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -744,7 +744,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case BOTTOM: /* BOTTOM = 2*/ /* For the border, we should take special care */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -774,7 +774,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case LEFT: /* LEFT = 3 */ /* For the border, we should take special care */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) { + if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() > track_range[side_manager.get_side()].y()) { rr_gsb.clear_one_side(side_manager.get_side()); break; } From de0d0bc214419cae53c10e6a1349d4ae251625f8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:15:42 -0700 Subject: [PATCH 307/453] [core] debug --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 6fdc46c31af..f157304a896 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -640,13 +640,13 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, std::map> track_range; track_range[TOP] = vtr::Point(0, grids.height() - 2); track_range[RIGHT] = vtr::Point(0, grids.width() - 2); - track_range[BOTTOM] = vtr::Point(1, grids.height() - 2); - track_range[LEFT] = vtr::Point(1, grids.width() - 2); + track_range[BOTTOM] = vtr::Point(0, grids.height() - 2); + track_range[LEFT] = vtr::Point(0, grids.width() - 2); if (perimeter_cb) { track_range[TOP] = vtr::Point(0, grids.height() - 1); track_range[RIGHT] = vtr::Point(0, grids.width() - 1); - track_range[BOTTOM] = vtr::Point(0, grids.height()); - track_range[LEFT] = vtr::Point(0, grids.width()); + track_range[BOTTOM] = vtr::Point(0, grids.height() - 1); + track_range[LEFT] = vtr::Point(0, grids.width() - 1); } /* Create an object to return */ From 0a1bc20b08da6ad0d0fbf5fe9e931b1bbdac09a1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 11:46:19 -0700 Subject: [PATCH 308/453] [core] debugging --- .../tileable_rr_graph_edge_builder.cpp | 5 +-- .../tileable_rr_graph_gsb.cpp | 36 +++---------------- 2 files changed, 6 insertions(+), 35 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 39ec645694f..baa97d8d348 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -125,10 +125,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); - vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); - if (perimeter_cb) { - gsb_range.set(grids.width() - 1, grids.height() - 1); - } + vtr::Point gsb_range(grids.width() - 1, grids.height() - 1); /* Go Switch Block by Switch Block */ for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index f157304a896..7ec8c756a08 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -625,30 +625,6 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, const size_t& layer, const vtr::Point& gsb_coordinate, const bool& perimeter_cb) { - /* Bounding box for GSB ranges on routing tracks. - * Note that when perimeter connection blocks are not allowed, - * - top side routing tracks for any GSB exist on y = [0, H-2) - * - right side routing tracks for any GSB exist on x = [0, W-2) - * - bottom side routing tracks for any GSB exist on y = [1, H-1) - * - left side routing tracks for any GSB exist on x = [1, W-1) - * Note that when perimeter connection blocks are allowed, - * - top side routing tracks for any GSB exist on y = [0, H-1) - * - right side routing tracks for any GSB exist on x = [0, W-1) - * - bottom side routing tracks for any GSB exist on y = [0, H) - * - left side routing tracks for any GSB exist on x = [0, W) - */ - std::map> track_range; - track_range[TOP] = vtr::Point(0, grids.height() - 2); - track_range[RIGHT] = vtr::Point(0, grids.width() - 2); - track_range[BOTTOM] = vtr::Point(0, grids.height() - 2); - track_range[LEFT] = vtr::Point(0, grids.width() - 2); - if (perimeter_cb) { - track_range[TOP] = vtr::Point(0, grids.height() - 1); - track_range[RIGHT] = vtr::Point(0, grids.width() - 1); - track_range[BOTTOM] = vtr::Point(0, grids.height() - 1); - track_range[LEFT] = vtr::Point(0, grids.width() - 1); - } - /* Create an object to return */ RRGSB rr_gsb; @@ -683,8 +659,8 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, switch (side) { case TOP: /* TOP = 0 */ - /* For the border, we should take special care. The top column (H-1) does not have any top side routing channel. Any lower column may have (<= H-2) */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() > track_range[side_manager.get_side()].y()) { + /* For the border, we should take special care. */ + if (gsb_coordinate.y() == grids.height() - 1) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -714,7 +690,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case RIGHT: /* RIGHT = 1 */ /* For the border, we should take special care. The rightmost column (W-1) does not have any right side routing channel. If perimeter connection block is not enabled, even the last second rightmost column (W-2) does not have any right side routing channel */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() > track_range[side_manager.get_side()].y()) { + if (gsb_coordinate.x() == grids.width() - 1) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -743,8 +719,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - /* For the border, we should take special care */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() > track_range[side_manager.get_side()].y()) { + if (!perimeter_cb && gsb_coordinate.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -773,8 +748,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - /* For the border, we should take special care */ - if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() > track_range[side_manager.get_side()].y()) { + if (!perimeter_cb && gsb_coordinate.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } From 4da28ffbccf4eb2b31a57ec36a3c135225ef40f9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:12:46 -0700 Subject: [PATCH 309/453] [core] debug --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 8dc91462feb..b154ea30936 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -625,7 +625,7 @@ e_side RRGSB::get_cb_chan_side(const t_rr_type& cb_type) const { case CHANX: return LEFT; case CHANY: - return TOP; + return BOTTOM; default: VTR_LOG("Invalid type of connection block!\n"); exit(1); @@ -638,11 +638,11 @@ e_side RRGSB::get_cb_chan_side(const e_side& ipin_side) const { case TOP: return LEFT; case RIGHT: - return TOP; + return BOTTOM; case BOTTOM: return LEFT; case LEFT: - return TOP; + return BOTTOM; default: VTR_LOG("Invalid type of ipin_side!\n"); exit(1); From c71c3b9d3a1a17b6865511b29e5d2e14f5e9fe15 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 12:20:33 -0700 Subject: [PATCH 310/453] [core] debug --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 7ec8c756a08..4fb4c1b2c76 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -868,7 +868,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case RIGHT: /* Consider the routing channel that is connected to the top side of the switch block */ - chan_side = TOP; + chan_side = BOTTOM; /* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */ ix = rr_gsb.get_sb_x() + 1; iy = rr_gsb.get_sb_y(); @@ -884,7 +884,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, break; case LEFT: /* Consider the routing channel that is connected to the top side of the switch block */ - chan_side = TOP; + chan_side = BOTTOM; /* The input pins of the routing channel come from the right side of Grid[x][y+1] */ ix = rr_gsb.get_sb_x(); iy = rr_gsb.get_sb_y(); From d2be1c8b2629069479863826695ed317bf88618a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2024 13:41:16 -0700 Subject: [PATCH 311/453] [core] fixed a critical bug --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index b154ea30936..2ad75efe745 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -859,9 +859,6 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph) { SideManager side_manager(side); /* Bypass boundary GSBs here. When perimeter_cb option is on, Some GSBs may have only 1 side of CHANX or CHANY. There are no edges in the GSB, so we should skip them */ chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width()); - if (chan_node_[side_manager.get_opposite()].get_chan_width() == 0) { - continue; - } for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) { /* Only sort the output nodes and bypass passing wires */ if ((OUT_PORT == chan_node_direction_[side][track_id]) From 3eca1f611e2c471e752a8126907114e053ab1657 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Mon, 8 Jul 2024 17:13:09 +0500 Subject: [PATCH 312/453] Updating libencryption/libdecryption for compatibility with openssl3 --- libs/libdecrypt/src/decryption.cpp | 199 ++++++++++++++----------- libs/libdecrypt/src/decryption.h | 29 ++-- libs/libencrypt/CMakeLists.txt | 5 - libs/libencrypt/src/encryption.cpp | 225 +++++++++++++++++++---------- libs/libencrypt/src/encryption.h | 57 +++++--- 5 files changed, 315 insertions(+), 200 deletions(-) diff --git a/libs/libdecrypt/src/decryption.cpp b/libs/libdecrypt/src/decryption.cpp index 9c115c7e798..60711cd9674 100644 --- a/libs/libdecrypt/src/decryption.cpp +++ b/libs/libdecrypt/src/decryption.cpp @@ -32,7 +32,7 @@ void Decryption::decryptFile() { "dummykey\n" "-----END RSA PRIVATE KEY-----\n"); // Replace with your private key string #endif - RSA* privateKey = loadPrivateKey(privateKeyString); + EVP_PKEY *privateKey = loadPrivateKey(privateKeyString); if (!privateKey) { return; } @@ -42,7 +42,7 @@ void Decryption::decryptFile() { pugi::xml_parse_result result = encryptedDocLoaded.load_file(encryptedFile_.c_str()); if (!result) { std::cerr << "XML parse error: " << result.description() << std::endl; - RSA_free(privateKey); + EVP_PKEY_free(privateKey); return; } @@ -50,23 +50,19 @@ void Decryption::decryptFile() { std::string base64EncryptedSessionKeyLoaded = root.child_value("SessionKey"); std::string base64EncryptedLoaded = root.child_value("Data"); - // Base64 decode encrypted session key and data - std::string encryptedSessionKeyLoaded = base64_decode(base64EncryptedSessionKeyLoaded); - std::string encryptedLoaded = base64_decode(base64EncryptedLoaded); - // Decrypt session key - std::string decryptedSessionKey = decryptSessionKey(encryptedSessionKeyLoaded, privateKey); + std::string decryptedSessionKey = decryptSessionKey(base64EncryptedSessionKeyLoaded, privateKey); // Decrypt XML string - std::string decrypted = decrypt(encryptedLoaded, privateKey); + std::string decrypted = decryptData(base64EncryptedLoaded, reinterpret_cast(decryptedSessionKey.c_str())); // Write the decrypted data to a file - // std::ofstream decryptedFile("decrypted.xml"); - // decryptedFile << decrypted; - // decryptedFile.close(); + std::ofstream decryptedFile("decrypted.xml"); + decryptedFile << decrypted; + decryptedFile.close(); decryptedContent_ = decrypted; - RSA_free(privateKey); + EVP_PKEY_free(privateKey); } /** @@ -79,108 +75,147 @@ std::string Decryption::getDecryptedContent() const { } /** - * @brief Decrypts the given ciphertext using the provided RSA key. + * @brief Loads the private key from the given PEM string. * - * @param ciphertext The ciphertext to decrypt. - * @param key The RSA key for decryption. - * @return The decrypted plaintext. + * @param privateKeyString The PEM string representing the private key. + * @return The loaded EVP private key. */ -std::string Decryption::decrypt(const std::string& ciphertext, RSA* key) { - int rsaLen = RSA_size(key); - int len = ciphertext.size(); - std::string plaintext; - - for (int i = 0; i < len; i += rsaLen) { - std::vector buffer(rsaLen); - std::string substr = ciphertext.substr(i, rsaLen); - - int result = RSA_private_decrypt(substr.size(), reinterpret_cast(substr.data()), buffer.data(), key, RSA_PKCS1_OAEP_PADDING); - if (result == -1) { - std::cerr << "Decryption error: " << ERR_error_string(ERR_get_error(), NULL) << std::endl; - return ""; - } - - plaintext.append(reinterpret_cast(buffer.data()), result); +EVP_PKEY *Decryption::loadPrivateKey(const std::string& privateKeyString) { + EVP_PKEY *pkey = nullptr; + BIO* privateKeyBio = BIO_new_mem_buf(privateKeyString.data(), privateKeyString.size()); + + if (!privateKeyBio) { + std::cerr << "Error creating BIO for private key" << std::endl; + return nullptr; + } + + char* passphrase_cstr = const_cast(passphrase.c_str()); + if (!PEM_read_bio_PrivateKey(privateKeyBio, &pkey, NULL, passphrase_cstr)) { + std::cerr << "Error reading private key" << std::endl; + BIO_free(privateKeyBio); + return nullptr; } - return plaintext; + BIO_free(privateKeyBio); + return pkey; } /** - * @brief Decodes the given base64-encoded string. + * @brief * - * @param input The base64-encoded input string. - * @return The decoded output string. + * @param encoded he base64-encoded input string. + * @return std::vector The decoded dynamic array of characters. */ -std::string Decryption::base64_decode(const std::string& input) { +std::vector Decryption::base64Decode(const std::string& encoded) { + BIO* bio = BIO_new_mem_buf(encoded.data(), -1); BIO* b64 = BIO_new(BIO_f_base64()); BIO_set_flags(b64, BIO_FLAGS_BASE64_NO_NL); + bio = BIO_push(b64, bio); - BIO* bmem = BIO_new_mem_buf(input.data(), input.size()); - b64 = BIO_push(b64, bmem); - - std::string output; - output.resize(input.size()); - - int decoded_size = BIO_read(b64, &output[0], input.size()); - output.resize(decoded_size); - BIO_free_all(b64); + std::vector decoded(encoded.length()); + int decodedLen = BIO_read(bio, decoded.data(), encoded.length()); + decoded.resize(decodedLen); - return output; + BIO_free_all(bio); + return decoded; } /** - * @brief Loads the private key from the given PEM string. + * @brief Decrypts the given encrypted session key using the provided EVP key. * - * @param privateKeyString The PEM string representing the private key. - * @return The loaded RSA private key. + * @param encryptedSessionKey The encrypted session key. + * @param privateKey The EVP key for decryption. + * @return The decrypted session key. */ -RSA* Decryption::loadPrivateKey(const std::string& privateKeyString) { - RSA* key = nullptr; - BIO* privateKeyBio = BIO_new_mem_buf(privateKeyString.data(), privateKeyString.size()); +std::string Decryption::decryptSessionKey(const std::string& encryptedSessionKey, EVP_PKEY* privateKey) { + std::vector decodedKey = base64Decode(encryptedSessionKey); - if (!privateKeyBio) { - std::cerr << "Error creating BIO for private key" << std::endl; - return nullptr; + EVP_PKEY_CTX* ctx = EVP_PKEY_CTX_new(privateKey, NULL); + if (!ctx) { + std::cerr << "Failed to create EVP_PKEY_CTX" << std::endl; + return ""; } - char* passphrase_cstr = const_cast(passphrase.c_str()); - if (!PEM_read_bio_RSAPrivateKey(privateKeyBio, &key, NULL, passphrase_cstr)) { - std::cerr << "Error reading private key" << std::endl; - BIO_free(privateKeyBio); - return nullptr; + if (EVP_PKEY_decrypt_init(ctx) <= 0) { + std::cerr << "EVP_PKEY_decrypt_init failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; } - BIO_free(privateKeyBio); - return key; + if (EVP_PKEY_CTX_set_rsa_padding(ctx, RSA_PKCS1_OAEP_PADDING) <= 0) { + std::cerr << "EVP_PKEY_CTX_set_rsa_padding failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + size_t outLen; + if (EVP_PKEY_decrypt(ctx, NULL, &outLen, decodedKey.data(), decodedKey.size()) <= 0) { + std::cerr << "EVP_PKEY_decrypt (determine length) failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + std::vector out(outLen); + if (EVP_PKEY_decrypt(ctx, out.data(), &outLen, decodedKey.data(), decodedKey.size()) <= 0) { + std::cerr << "EVP_PKEY_decrypt failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + EVP_PKEY_CTX_free(ctx); + + return std::string(out.begin(), out.begin() + outLen); } /** - * @brief Decrypts the given encrypted session key using the provided RSA key. + * @brief * - * @param encryptedSessionKey The encrypted session key. - * @param key The RSA key for decryption. - * @return The decrypted session key. + * @param encryptedData The encrypted data to decrypt. + * @param sessionKey The session key for data decryption. + * @return std::string The decrypted plaintext. */ -std::string Decryption::decryptSessionKey(const std::string& encryptedSessionKey, RSA* key) { - std::vector decryptedSessionKey(RSA_size(key)); - if (RSA_private_decrypt(encryptedSessionKey.size(), reinterpret_cast(encryptedSessionKey.data()), decryptedSessionKey.data(), key, RSA_PKCS1_OAEP_PADDING) == -1) { - std::cerr << "Session key decryption error: " << ERR_error_string(ERR_get_error(), NULL) << std::endl; +std::string Decryption::decryptData(const std::string& encryptedData, const unsigned char* sessionKey) { + std::vector decodedData = base64Decode(encryptedData); + + // Extract the IV from the decoded data + unsigned char iv[EVP_MAX_IV_LENGTH]; + int iv_len = EVP_CIPHER_iv_length(EVP_aes_128_cbc()); + std::copy(decodedData.begin(), decodedData.begin() + iv_len, iv); + const unsigned char* ciphertext = decodedData.data() + iv_len; + size_t ciphertextLen = decodedData.size() - iv_len; + + EVP_CIPHER_CTX* ctx = EVP_CIPHER_CTX_new(); + if (!ctx) { + std::cerr << "Failed to create EVP_CIPHER_CTX" << std::endl; return ""; } - return std::string(reinterpret_cast(decryptedSessionKey.data()), decryptedSessionKey.size()); -} + if (EVP_DecryptInit_ex(ctx, EVP_aes_128_cbc(), NULL, sessionKey, iv) != 1) { + std::cerr << "EVP_DecryptInit_ex failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + + std::vector plaintext(ciphertextLen + EVP_CIPHER_block_size(EVP_aes_128_cbc())); + int len = 0; + int plaintextLen = 0; -// int main(int argc, char* argv[]) { -// if (argc < 2) { -// std::cerr << "Usage: " << argv[0] << " \n"; -// return -1; -// } + if (EVP_DecryptUpdate(ctx, plaintext.data(), &len, ciphertext, ciphertextLen) != 1) { + std::cerr << "EVP_DecryptUpdate failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + plaintextLen += len; -// std::string encryptedFile = argv[1]; + if (EVP_DecryptFinal_ex(ctx, plaintext.data() + plaintextLen, &len) != 1) { + std::cerr << "EVP_DecryptFinal_ex failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + plaintextLen += len; + plaintext.resize(plaintextLen); -// Decryption decryption(encryptedFile); + EVP_CIPHER_CTX_free(ctx); -// return 0; -// } + return std::string(plaintext.begin(), plaintext.end()); +} \ No newline at end of file diff --git a/libs/libdecrypt/src/decryption.h b/libs/libdecrypt/src/decryption.h index 52d3023dd93..acac951e903 100644 --- a/libs/libdecrypt/src/decryption.h +++ b/libs/libdecrypt/src/decryption.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -49,38 +50,38 @@ class Decryption std::string decryptedContent_; /**< The decrypted content of the file. */ /** - * @brief Decrypts the given ciphertext using the provided RSA key. + * @brief * - * @param ciphertext The ciphertext to decrypt. - * @param key The RSA key for decryption. - * @return The decrypted plaintext. + * @param encryptedData The encrypted data to decrypt. + * @param sessionKey The session key for data decryption. + * @return std::string The decrypted plaintext. */ - static std::string decrypt(const std::string &ciphertext, RSA *key); + static std::string decryptData(const std::string& encryptedData, const unsigned char* sessionKey); /** - * @brief Decodes the given base64-encoded string. + * @brief * - * @param input The base64-encoded input string. - * @return The decoded output string. + * @param encoded he base64-encoded input string. + * @return std::vector The decoded dynamic array of characters. */ - static std::string base64_decode(const std::string &input); + static std::vector base64Decode(const std::string& encoded); /** * @brief Loads the private key from the given PEM string. * * @param privateKeyString The PEM string representing the private key. - * @return The loaded RSA private key. + * @return The loaded EVP private key. */ - static RSA *loadPrivateKey(const std::string &privateKeyString); + static EVP_PKEY* loadPrivateKey(const std::string& privateKeyString); /** - * @brief Decrypts the given encrypted session key using the provided RSA key. + * @brief Decrypts the given encrypted session key using the provided EVP key. * * @param encryptedSessionKey The encrypted session key. - * @param key The RSA key for decryption. + * @param privateKey The EVP key for decryption. * @return The decrypted session key. */ - static std::string decryptSessionKey(const std::string &encryptedSessionKey, RSA *key); + static std::string decryptSessionKey(const std::string& encryptedSessionKey, EVP_PKEY* privateKey); }; #endif // DECRYPTION_H diff --git a/libs/libencrypt/CMakeLists.txt b/libs/libencrypt/CMakeLists.txt index 23a589415ac..aedb25896ff 100644 --- a/libs/libencrypt/CMakeLists.txt +++ b/libs/libencrypt/CMakeLists.txt @@ -4,11 +4,6 @@ project(libencrypt) find_package(PkgConfig REQUIRED) pkg_search_module(OPENSSL REQUIRED openssl) -file(READ "config.txt" PASSPHRASE_CONTENTS) -string(REPLACE "\n" "\\n" PASSPHRASE_CONTENTS "${PASSPHRASE_CONTENTS}") -set(PASS_PHRASE "${PASSPHRASE_CONTENTS}") -add_compile_definitions(PASS_PHRASE="${PASS_PHRASE}") - if(OPENSSL_FOUND) include_directories(${OPENSSL_INCLUDE_DIRS}) message(STATUS "Using OpenSSL ${OPENSSL_VERSION}") diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp index a92e6f8f155..9b4bf641da8 100644 --- a/libs/libencrypt/src/encryption.cpp +++ b/libs/libencrypt/src/encryption.cpp @@ -1,111 +1,175 @@ #include "encryption.h" -#ifdef PASSPHRASE -std::string passphrase_enc = PASSPHRASE; -#else -std::string passphrase_enc = ""; // Set your PEM pass phrase here -#endif + +/** + * @brief Generates random session key + * + * @param sessionKey A pointer to session key + * @param keySize Session key length (128 bits for AES-128) + */ +void Encryption::generateSessionKey(unsigned char* sessionKey, size_t keySize) { + if (RAND_bytes(sessionKey, keySize) != 1) { + std::cerr << "Error generating session key." << std::endl; + exit(1); + } +} + /** * @brief Loads a public key from a file. * * @param filename The name of the file containing the public key. - * @return RSA* A pointer to the loaded public key. + * @return EVP_PKEY* A pointer to the loaded public key. * Returns nullptr if the key file cannot be opened or there is an error reading the key. */ -RSA* Encryption::loadPublicKey(const std::string& filename) { - - RSA* key = nullptr; +EVP_PKEY* Encryption::loadPublicKey(const std::string& filename) { + EVP_PKEY *key = nullptr; FILE* keyFile = fopen(filename.c_str(), "r"); if (!keyFile) { std::cerr << "Unable to open key file: " << filename << std::endl; return nullptr; } - char* passphrase_cstr = const_cast(passphrase_enc.c_str()); - if (!PEM_read_RSA_PUBKEY(keyFile, &key, NULL, passphrase_cstr)) { - std::cerr << "Error reading public key from file: " << filename << std::endl; + // Create a BIO object from the file + BIO* keyBio = BIO_new_fp(keyFile, BIO_NOCLOSE); + if (!keyBio) { + std::cerr << "Error creating BIO from file" << std::endl; fclose(keyFile); return nullptr; } + // Use PEM_read_bio_PUBKEY + key = PEM_read_bio_PUBKEY(keyBio, nullptr, nullptr, nullptr); + + BIO_free(keyBio); fclose(keyFile); + if (!key) { + std::cerr << "Error reading public key from file: " << filename << std::endl; + return nullptr; + } return key; } /** - * @brief Encrypts a session key using the provided public key. - * - * @param key The public key used for encryption. - * @return std::string The encrypted session key. - * Returns an empty string if there is an error generating or encrypting the session key. + * @brief + * + * @param sessionKey Key to be encrypted + * @param keySize Session key length + * @param publicKey The public key used for encryption + * @return std::string Encrypted session key */ -std::string Encryption::encryptSessionKey(RSA* key) { - unsigned char sessionKey[128]; - if (!RAND_bytes(sessionKey, sizeof(sessionKey))) { - std::cerr << "Error generating session key" << std::endl; +std::string Encryption::encryptSessionKey(const unsigned char* sessionKey, size_t keySize, EVP_PKEY* publicKey) { + EVP_PKEY_CTX* ctx = EVP_PKEY_CTX_new(publicKey, NULL); + if (!ctx) { + std::cerr << "Failed to create EVP_PKEY_CTX" << std::endl; return ""; } - std::vector encryptedSessionKey(RSA_size(key)); - if (RSA_public_encrypt(sizeof(sessionKey), sessionKey, encryptedSessionKey.data(), key, RSA_PKCS1_OAEP_PADDING) == -1) { - std::cerr << "Session key encryption error: " << ERR_error_string(ERR_get_error(), nullptr) << std::endl; + if (EVP_PKEY_encrypt_init(ctx) <= 0) { + std::cerr << "EVP_PKEY_encrypt_init failed" << std::endl; + EVP_PKEY_CTX_free(ctx); return ""; } - return std::string(reinterpret_cast(encryptedSessionKey.data()), encryptedSessionKey.size()); -} + if (EVP_PKEY_CTX_set_rsa_padding(ctx, RSA_PKCS1_OAEP_PADDING) <= 0) { + std::cerr << "EVP_PKEY_CTX_set_rsa_padding failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } -/** - * @brief Encrypts the given plaintext using the provided public key. - * - * @param plaintext The plaintext to be encrypted. - * @param key The public key used for encryption. - * @return std::string The encrypted ciphertext. - * Returns an empty string if there is an error during encryption. - */ -std::string Encryption::encrypt(const std::string& plaintext, RSA* key) { - int rsaLen = RSA_size(key); - int blockLen = rsaLen - 42; // PKCS1_OAEP_PADDING reduces max data length - int len = plaintext.size(); - std::string ciphertext; - - for (int i = 0; i < len; i += blockLen) { - std::vector buffer(rsaLen); - std::string substr = plaintext.substr(i, blockLen); - - if (RSA_public_encrypt(substr.size(), reinterpret_cast(substr.data()), buffer.data(), key, RSA_PKCS1_OAEP_PADDING) == -1) { - std::cerr << "Encryption error: " << ERR_error_string(ERR_get_error(), nullptr) << std::endl; - return ""; - } + size_t outLen; + if (EVP_PKEY_encrypt(ctx, NULL, &outLen, sessionKey, keySize) <= 0) { + std::cerr << "EVP_PKEY_encrypt (determine length) failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } - ciphertext.append(reinterpret_cast(buffer.data()), rsaLen); + std::vector out(outLen); + if (EVP_PKEY_encrypt(ctx, out.data(), &outLen, sessionKey, keySize) <= 0) { + std::cerr << "EVP_PKEY_encrypt failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; } - return ciphertext; + EVP_PKEY_CTX_free(ctx); + + std::string base64EncryptedSessionKey = base64Encode(out.data(), out.size()); + return base64EncryptedSessionKey; } /** - * @brief Base64 encodes the given input string. - * - * @param input The input string to be encoded. - * @return std::string The base64-encoded string. + * @brief + * + * @param buffer pointer to data to be encoded + * @param length data length + * @return std::string encoded data */ -std::string Encryption::base64_encode(const std::string& input) { +std::string Encryption::base64Encode(const unsigned char* buffer, size_t length) { + BIO* bio = BIO_new(BIO_s_mem()); BIO* b64 = BIO_new(BIO_f_base64()); BIO_set_flags(b64, BIO_FLAGS_BASE64_NO_NL); - - BIO* bmem = BIO_new(BIO_s_mem()); - b64 = BIO_push(b64, bmem); - - BIO_write(b64, input.data(), input.size()); + BIO_push(b64, bio); + BIO_write(b64, buffer, length); BIO_flush(b64); - BUF_MEM* bptr; - BIO_get_mem_ptr(b64, &bptr); + BUF_MEM* bufferPtr; + BIO_get_mem_ptr(b64, &bufferPtr); - std::string output(bptr->data, bptr->length); + std::string encoded(bufferPtr->data, bufferPtr->length); BIO_free_all(b64); + return encoded; +} + +/** + * @brief + * + * @param plaintext The plaintext to be encrypted. + * @param sessionKey The session key used for encryption. + * @param iv Initialization vector. + * @return std::string The encrypted ciphertext. + * Returns an empty string if there is an error during encryption. + */ +std::string Encryption::encryptData(const std::string& plaintext, const unsigned char* sessionKey, const unsigned char* iv) { + EVP_CIPHER_CTX* ctx = EVP_CIPHER_CTX_new(); + if (!ctx) { + std::cerr << "Failed to create EVP_CIPHER_CTX" << std::endl; + return ""; + } - return output; + // Initialize the encryption operation with AES-128-CBC + if (EVP_EncryptInit_ex(ctx, EVP_aes_128_cbc(), NULL, sessionKey, iv) != 1) { + std::cerr << "EVP_EncryptInit_ex failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + + std::vector ciphertext(plaintext.size() + EVP_CIPHER_block_size(EVP_aes_128_cbc())); + int len = 0; + int ciphertextLen = 0; + + // Encrypt the data in chunks + if (EVP_EncryptUpdate(ctx, ciphertext.data(), &len, reinterpret_cast(plaintext.data()), plaintext.size()) != 1) { + std::cerr << "EVP_EncryptUpdate failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + ciphertextLen += len; + + // Finalize the encryption + if (EVP_EncryptFinal_ex(ctx, ciphertext.data() + ciphertextLen, &len) != 1) { + std::cerr << "EVP_EncryptFinal_ex failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + ciphertextLen += len; + ciphertext.resize(ciphertextLen); + + EVP_CIPHER_CTX_free(ctx); + + // Combine IV and ciphertext into a single string + std::vector combinedData(iv, iv + EVP_MAX_IV_LENGTH); + combinedData.insert(combinedData.end(), ciphertext.begin(), ciphertext.end()); + + // Base64 encode the combined data + return base64Encode(combinedData.data(), combinedData.size()); } /** @@ -117,9 +181,15 @@ std::string Encryption::base64_encode(const std::string& input) { */ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& filePath ) { - // Load public key - RSA* publicKey = loadPublicKey(publicKeyFile); + OpenSSL_add_all_algorithms(); + ERR_load_crypto_strings(); + unsigned char sessionKey[16]; + generateSessionKey(sessionKey, sizeof(sessionKey)); + + //load public key + EVP_PKEY* publicKey = loadPublicKey(publicKeyFile); if (!publicKey) { + std::cout << "Unable to open publicKey: " << filePath << std::endl; return false; } @@ -127,7 +197,7 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file std::ifstream file(filePath, std::ios::binary); if (!file) { std::cerr << "Unable to open file: " << filePath << std::endl; - RSA_free(publicKey); + EVP_PKEY_free(publicKey); return false; } @@ -135,29 +205,28 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file file.close(); // Encrypt session key - std::string encryptedSessionKey = encryptSessionKey(publicKey); + std::string encryptedSessionKey = encryptSessionKey(sessionKey, sizeof(sessionKey), publicKey); if (encryptedSessionKey.empty()) { - RSA_free(publicKey); + EVP_PKEY_free(publicKey); return false; } - // Base64 encode session key - std::string base64EncryptedSessionKey = base64_encode(encryptedSessionKey); + unsigned char iv[EVP_MAX_IV_LENGTH]; + if (RAND_bytes(iv, sizeof(iv)) != 1) { + std::cerr << "Error generating IV." << std::endl; + return -1; + } // Encrypt file contents - std::string encrypted = encrypt(plaintext, publicKey); - RSA_free(publicKey); - - // Base64 encode encrypted data - std::string base64Encrypted = base64_encode(encrypted); + std::string encrypted = encryptData(plaintext, sessionKey, iv); // Create an XML document for the encrypted data and session key pugi::xml_document encryptedDoc; auto root = encryptedDoc.append_child("EncryptedData"); auto sessionKeyNode = root.append_child("SessionKey"); - sessionKeyNode.append_child(pugi::node_pcdata).set_value(base64EncryptedSessionKey.c_str()); + sessionKeyNode.append_child(pugi::node_pcdata).set_value(encryptedSessionKey.c_str()); auto dataNode = root.append_child("Data"); - dataNode.append_child(pugi::node_pcdata).set_value(base64Encrypted.c_str()); + dataNode.append_child(pugi::node_pcdata).set_value(encrypted.c_str()); size_t lastDotPos = filePath.find_last_of('.'); diff --git a/libs/libencrypt/src/encryption.h b/libs/libencrypt/src/encryption.h index daedcdbcba2..d937e9ddad8 100644 --- a/libs/libencrypt/src/encryption.h +++ b/libs/libencrypt/src/encryption.h @@ -14,6 +14,10 @@ #include #include #include "obfuscate.h" +#include +#include +#include +#include //#include "config.h" /** * @class Encryption @@ -21,41 +25,52 @@ */ class Encryption { public: + /** + * @brief Generates random session key + * + * @param sessionKey A pointer to session key + * @param keySize Session key length (128 bits for AES-128) + */ + static void generateSessionKey(unsigned char* sessionKey, size_t keySize); + /** * @brief Loads a public key from a file. * * @param filename The name of the file containing the public key. - * @return RSA* A pointer to the loaded public key. + * @return EVP_PKEY* A pointer to the loaded public key. * Returns nullptr if the key file cannot be opened or there is an error reading the key. */ - static RSA *loadPublicKey(const std::string &filename); + static EVP_PKEY* loadPublicKey(const std::string& filename); /** - * @brief Encrypts a session key using the provided public key. - * - * @param key The public key used for encryption. - * @return std::string The encrypted session key. - * Returns an empty string if there is an error generating or encrypting the session key. + * @brief + * + * @param sessionKey Key to be encrypted + * @param keySize Session key length + * @param publicKey The public key used for encryption + * @return std::string Encrypted session key */ - static std::string encryptSessionKey(RSA *key); + static std::string encryptSessionKey(const unsigned char* sessionKey, size_t keySize, EVP_PKEY* publicKey); /** - * @brief Encrypts the given plaintext using the provided public key. - * - * @param plaintext The plaintext to be encrypted. - * @param key The public key used for encryption. - * @return std::string The encrypted ciphertext. - * Returns an empty string if there is an error during encryption. + * @brief + * + * @param buffer pointer to data to be encoded + * @param length data length + * @return std::string encoded data */ - static std::string encrypt(const std::string &plaintext, RSA *key); + static std::string base64Encode(const unsigned char* buffer, size_t length); /** - * @brief Base64 encodes the given input string. - * - * @param input The input string to be encoded. - * @return std::string The base64-encoded string. + * @brief + * + * @param plaintext The plaintext to be encrypted. + * @param sessionKey The session key used for encryption. + * @param iv Initialization vector. + * @return std::string The encrypted ciphertext. + * Returns an empty string if there is an error during encryption. */ - static std::string base64_encode(const std::string &input); + static std::string encryptData(const std::string& plaintext, const unsigned char* sessionKey, const unsigned char* iv); /** * @brief Encrypts a file using the provided public key. @@ -64,7 +79,7 @@ class Encryption { * @param publicKeyFile The path to the file containing the public key. * @return bool True if the file encryption is successful, false otherwise. */ - static bool encryptFile(const std::string& publicKeyFile, std::string &filePath); + static bool encryptFile(const std::string& publicKeyFile, std::string& filePath); }; #endif // ENCRYPTION_H From abf1ce6b0e92ecc389daec268f72e2cef831ca95 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Mon, 8 Jul 2024 17:20:14 +0500 Subject: [PATCH 313/453] Not dumping decrypted xml --- libs/libdecrypt/src/decryption.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/libdecrypt/src/decryption.cpp b/libs/libdecrypt/src/decryption.cpp index 60711cd9674..835950a755b 100644 --- a/libs/libdecrypt/src/decryption.cpp +++ b/libs/libdecrypt/src/decryption.cpp @@ -57,9 +57,9 @@ void Decryption::decryptFile() { std::string decrypted = decryptData(base64EncryptedLoaded, reinterpret_cast(decryptedSessionKey.c_str())); // Write the decrypted data to a file - std::ofstream decryptedFile("decrypted.xml"); - decryptedFile << decrypted; - decryptedFile.close(); + // std::ofstream decryptedFile("decrypted.xml"); + // decryptedFile << decrypted; + // decryptedFile.close(); decryptedContent_ = decrypted; EVP_PKEY_free(privateKey); From 2f82dd7005ce786c501ebf0f85452958111ac4da Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Mon, 8 Jul 2024 17:47:21 +0500 Subject: [PATCH 314/453] Commenting unused variables in pugixml_loc.cpp --- libs/libpugiutil/src/pugixml_loc.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/libpugiutil/src/pugixml_loc.cpp b/libs/libpugiutil/src/pugixml_loc.cpp index 5a86d3f3409..4b4c7bf506a 100644 --- a/libs/libpugiutil/src/pugixml_loc.cpp +++ b/libs/libpugiutil/src/pugixml_loc.cpp @@ -47,9 +47,9 @@ void loc_data::build_loc_data() { } void loc_data::build_loc_data_from_string(char* filename_val, size_t buffersize) { - std::ptrdiff_t offset = 0; - char buffer[1024]; - std::size_t size; + //std::ptrdiff_t offset = 0; + //char buffer[1024]; + //std::size_t size; for (std::size_t i = 0; i < buffersize; ++i) { if (filename_val[i] == '\0') break; From 2040d43bd8dc6f9485358cac0635af0882c66ed0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 13:31:55 -0700 Subject: [PATCH 315/453] [core] fixed a bug where sb may go out of boundary --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index baa97d8d348..4d75b7b40e5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -144,7 +144,9 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* adapt the opin_to_track_map for the GSB nodes */ t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ - opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + if (ix < gsb_range.x() && iy < gsb_range.y()) { + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + } /* adapt the switch_block_conn for the GSB nodes */ t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ From 5ca82e54c4a2fa007fa7c43e9e91e582b7cf03fe Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 13:32:31 -0700 Subject: [PATCH 316/453] [core] code format --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 4d75b7b40e5..82f3a69d2a6 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -145,7 +145,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* adapt the opin_to_track_map for the GSB nodes */ t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ if (ix < gsb_range.x() && iy < gsb_range.y()) { - opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); } /* adapt the switch_block_conn for the GSB nodes */ From ddc3ac408aa123dc8d4da1685c6dec7e65038646 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2024 13:39:37 -0700 Subject: [PATCH 317/453] [core] debugging --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 4 +--- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 3 +++ 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 82f3a69d2a6..baa97d8d348 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -144,9 +144,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* adapt the opin_to_track_map for the GSB nodes */ t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ - if (ix < gsb_range.x() && iy < gsb_range.y()) { - opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); - } + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); /* adapt the switch_block_conn for the GSB nodes */ t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 4fb4c1b2c76..b97454f1559 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1318,6 +1318,9 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, continue; } } + if (rr_gsb.get_sb_x() == grids.width() - 1 || rr_gsb.get_sb_y() == grids.height() - 1) { + skip_conn2track = true; + } if (true == skip_conn2track) { continue; From 67fe7a3ff529e2cb48ec124f919829ee657da2cf Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Tue, 9 Jul 2024 11:18:40 +0500 Subject: [PATCH 318/453] Minor changes for code clean-up --- libs/libdecrypt/src/decryption.cpp | 2 +- libs/libencrypt/CMakeLists.txt | 3 +++ libs/libencrypt/src/encryption.cpp | 10 ++++++++-- libs/libpugiutil/src/pugixml_loc.cpp | 3 --- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/libs/libdecrypt/src/decryption.cpp b/libs/libdecrypt/src/decryption.cpp index 835950a755b..625cfd7bdf9 100644 --- a/libs/libdecrypt/src/decryption.cpp +++ b/libs/libdecrypt/src/decryption.cpp @@ -103,7 +103,7 @@ EVP_PKEY *Decryption::loadPrivateKey(const std::string& privateKeyString) { /** * @brief * - * @param encoded he base64-encoded input string. + * @param encoded The base64-encoded input string. * @return std::vector The decoded dynamic array of characters. */ std::vector Decryption::base64Decode(const std::string& encoded) { diff --git a/libs/libencrypt/CMakeLists.txt b/libs/libencrypt/CMakeLists.txt index aedb25896ff..507abb227de 100644 --- a/libs/libencrypt/CMakeLists.txt +++ b/libs/libencrypt/CMakeLists.txt @@ -4,6 +4,9 @@ project(libencrypt) find_package(PkgConfig REQUIRED) pkg_search_module(OPENSSL REQUIRED openssl) +set(SESSION_KEY_SIZE 16) +add_definitions(-DSESSION_KEY_SIZE=${SESSION_KEY_SIZE}) + if(OPENSSL_FOUND) include_directories(${OPENSSL_INCLUDE_DIRS}) message(STATUS "Using OpenSSL ${OPENSSL_VERSION}") diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp index 9b4bf641da8..5c97d976282 100644 --- a/libs/libencrypt/src/encryption.cpp +++ b/libs/libencrypt/src/encryption.cpp @@ -1,5 +1,11 @@ #include "encryption.h" +#ifdef SESSION_KEY_SIZE +unsigned sessionKeySize = SESSION_KEY_SIZE; +#else +unsigned sessionKeySize = 16; +#endif + /** * @brief Generates random session key * @@ -183,7 +189,7 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file OpenSSL_add_all_algorithms(); ERR_load_crypto_strings(); - unsigned char sessionKey[16]; + unsigned char sessionKey[sessionKeySize]; generateSessionKey(sessionKey, sizeof(sessionKey)); //load public key @@ -214,7 +220,7 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file unsigned char iv[EVP_MAX_IV_LENGTH]; if (RAND_bytes(iv, sizeof(iv)) != 1) { std::cerr << "Error generating IV." << std::endl; - return -1; + return false; } // Encrypt file contents diff --git a/libs/libpugiutil/src/pugixml_loc.cpp b/libs/libpugiutil/src/pugixml_loc.cpp index 4b4c7bf506a..edb5405bcd0 100644 --- a/libs/libpugiutil/src/pugixml_loc.cpp +++ b/libs/libpugiutil/src/pugixml_loc.cpp @@ -47,9 +47,6 @@ void loc_data::build_loc_data() { } void loc_data::build_loc_data_from_string(char* filename_val, size_t buffersize) { - //std::ptrdiff_t offset = 0; - //char buffer[1024]; - //std::size_t size; for (std::size_t i = 0; i < buffersize; ++i) { if (filename_val[i] == '\0') break; From e8b2ac74df2f8f3b728a051d2ba6f86c50b80669 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Tue, 9 Jul 2024 12:10:21 +0500 Subject: [PATCH 319/453] Updating code to avoid possible memory leaks --- libs/libencrypt/src/encryption.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp index 5c97d976282..cb58863b873 100644 --- a/libs/libencrypt/src/encryption.cpp +++ b/libs/libencrypt/src/encryption.cpp @@ -220,6 +220,7 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file unsigned char iv[EVP_MAX_IV_LENGTH]; if (RAND_bytes(iv, sizeof(iv)) != 1) { std::cerr << "Error generating IV." << std::endl; + EVP_PKEY_free(publicKey); return false; } @@ -249,5 +250,7 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file std::cout << "File encrypted successfully. Encrypted file saved as: " << encryptedFilePath << std::endl; + EVP_PKEY_free(publicKey); + return true; } From 24825068bfa7fb5d1ee1ed0188f4232be6d66005 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Tue, 9 Jul 2024 12:57:36 +0500 Subject: [PATCH 320/453] Dynamically allocating memory for session key --- libs/libencrypt/src/encryption.cpp | 17 +++++++++-------- libs/libencrypt/src/encryption.h | 4 ++-- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp index cb58863b873..80455f0e9a5 100644 --- a/libs/libencrypt/src/encryption.cpp +++ b/libs/libencrypt/src/encryption.cpp @@ -62,7 +62,7 @@ EVP_PKEY* Encryption::loadPublicKey(const std::string& filename) { * @param publicKey The public key used for encryption * @return std::string Encrypted session key */ -std::string Encryption::encryptSessionKey(const unsigned char* sessionKey, size_t keySize, EVP_PKEY* publicKey) { +std::string Encryption::encryptSessionKey(std::vector& sessionKey, EVP_PKEY* publicKey) { EVP_PKEY_CTX* ctx = EVP_PKEY_CTX_new(publicKey, NULL); if (!ctx) { std::cerr << "Failed to create EVP_PKEY_CTX" << std::endl; @@ -82,14 +82,15 @@ std::string Encryption::encryptSessionKey(const unsigned char* sessionKey, size_ } size_t outLen; - if (EVP_PKEY_encrypt(ctx, NULL, &outLen, sessionKey, keySize) <= 0) { + size_t keySize = sessionKey.size(); + if (EVP_PKEY_encrypt(ctx, NULL, &outLen, sessionKey.data(), keySize) <= 0) { std::cerr << "EVP_PKEY_encrypt (determine length) failed" << std::endl; EVP_PKEY_CTX_free(ctx); return ""; } std::vector out(outLen); - if (EVP_PKEY_encrypt(ctx, out.data(), &outLen, sessionKey, keySize) <= 0) { + if (EVP_PKEY_encrypt(ctx, out.data(), &outLen, sessionKey.data(), keySize) <= 0) { std::cerr << "EVP_PKEY_encrypt failed" << std::endl; EVP_PKEY_CTX_free(ctx); return ""; @@ -133,7 +134,7 @@ std::string Encryption::base64Encode(const unsigned char* buffer, size_t length) * @return std::string The encrypted ciphertext. * Returns an empty string if there is an error during encryption. */ -std::string Encryption::encryptData(const std::string& plaintext, const unsigned char* sessionKey, const unsigned char* iv) { +std::string Encryption::encryptData(const std::string& plaintext, std::vector& sessionKey, const unsigned char* iv) { EVP_CIPHER_CTX* ctx = EVP_CIPHER_CTX_new(); if (!ctx) { std::cerr << "Failed to create EVP_CIPHER_CTX" << std::endl; @@ -141,7 +142,7 @@ std::string Encryption::encryptData(const std::string& plaintext, const unsigned } // Initialize the encryption operation with AES-128-CBC - if (EVP_EncryptInit_ex(ctx, EVP_aes_128_cbc(), NULL, sessionKey, iv) != 1) { + if (EVP_EncryptInit_ex(ctx, EVP_aes_128_cbc(), NULL, sessionKey.data(), iv) != 1) { std::cerr << "EVP_EncryptInit_ex failed" << std::endl; EVP_CIPHER_CTX_free(ctx); return ""; @@ -189,8 +190,8 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file OpenSSL_add_all_algorithms(); ERR_load_crypto_strings(); - unsigned char sessionKey[sessionKeySize]; - generateSessionKey(sessionKey, sizeof(sessionKey)); + std::vector sessionKey(sessionKeySize); + generateSessionKey(sessionKey.data(), sessionKey.size()); //load public key EVP_PKEY* publicKey = loadPublicKey(publicKeyFile); @@ -211,7 +212,7 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file file.close(); // Encrypt session key - std::string encryptedSessionKey = encryptSessionKey(sessionKey, sizeof(sessionKey), publicKey); + std::string encryptedSessionKey = encryptSessionKey(sessionKey, publicKey); if (encryptedSessionKey.empty()) { EVP_PKEY_free(publicKey); return false; diff --git a/libs/libencrypt/src/encryption.h b/libs/libencrypt/src/encryption.h index d937e9ddad8..340d4b5e55d 100644 --- a/libs/libencrypt/src/encryption.h +++ b/libs/libencrypt/src/encryption.h @@ -50,7 +50,7 @@ class Encryption { * @param publicKey The public key used for encryption * @return std::string Encrypted session key */ - static std::string encryptSessionKey(const unsigned char* sessionKey, size_t keySize, EVP_PKEY* publicKey); + static std::string encryptSessionKey(std::vector& sessionKey, EVP_PKEY* publicKey); /** * @brief @@ -70,7 +70,7 @@ class Encryption { * @return std::string The encrypted ciphertext. * Returns an empty string if there is an error during encryption. */ - static std::string encryptData(const std::string& plaintext, const unsigned char* sessionKey, const unsigned char* iv); + static std::string encryptData(const std::string& plaintext, std::vector& sessionKey, const unsigned char* iv); /** * @brief Encrypts a file using the provided public key. From 7f1df6738c6cc97586210d9a0889434e3bbeba66 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Wed, 10 Jul 2024 15:14:04 +0500 Subject: [PATCH 321/453] Adding test for XML encryption/decryption --- .github/workflows/test.yml | 13 ++++++++++++ libs/libdecrypt/CMakeLists.txt | 4 +++- libs/libdecrypt/test/CMakeLists.txt | 19 +++++++++++++++++ libs/libdecrypt/test/src/main.cpp | 33 +++++++++++++++++++++++++++++ libs/libdecrypt/test/src/test.cpp | 22 +++++++++++++++++++ libs/libdecrypt/test/src/test.h | 14 ++++++++++++ 6 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 libs/libdecrypt/test/CMakeLists.txt create mode 100644 libs/libdecrypt/test/src/main.cpp create mode 100644 libs/libdecrypt/test/src/test.cpp create mode 100644 libs/libdecrypt/test/src/test.h diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 748d19b80c9..740ac53a3f6 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -497,3 +497,16 @@ jobs: run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" ./.github/scripts/build.sh + + test_xml_encryption: + name: 'Encryption/Decryption test' + strategy: + fail-fast: false + needs: Build + runs-on: ubuntu-22.04 + + steps: + - name: Test_Encryption_Decryption + shell: bash + run: | + valgrind ./build/libs/libdecrypt/test/test_encrypt_decrypt \ No newline at end of file diff --git a/libs/libdecrypt/CMakeLists.txt b/libs/libdecrypt/CMakeLists.txt index 3eaeab363c6..c02e48a658c 100644 --- a/libs/libdecrypt/CMakeLists.txt +++ b/libs/libdecrypt/CMakeLists.txt @@ -44,4 +44,6 @@ target_link_libraries(libdecrypt ${OPENSSL_LIBRARIES} ) install(TARGETS libdecrypt DESTINATION bin) -install(FILES ${LIB_HEADERS} DESTINATION include/libdecrypt) \ No newline at end of file +install(FILES ${LIB_HEADERS} DESTINATION include/libdecrypt) + +add_subdirectory(test) \ No newline at end of file diff --git a/libs/libdecrypt/test/CMakeLists.txt b/libs/libdecrypt/test/CMakeLists.txt new file mode 100644 index 00000000000..8a44053acd3 --- /dev/null +++ b/libs/libdecrypt/test/CMakeLists.txt @@ -0,0 +1,19 @@ +cmake_minimum_required(VERSION 3.10) +project(EncryptionDecryptionTest) + +# Find OpenSSL +find_package(OpenSSL REQUIRED) + +add_executable(test_encrypt_decrypt src/test.cpp src/main.cpp) + +set(PUBLIC_KEY_FILE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/../../libencrypt/public_key.pem") +target_compile_definitions(test_encrypt_decrypt PRIVATE PUBLIC_KEY_FILE="${PUBLIC_KEY_FILE_PATH}") + +include_directories("${CMAKE_CURRENT_SOURCE_DIR}/../../libencrypt/src" + "${CMAKE_CURRENT_SOURCE_DIR}/../libdecrypt/src" + "${CMAKE_CURRENT_SOURCE_DIR}/src") + +target_link_libraries(test_encrypt_decrypt + libpugixml + libdecrypt + libencrypt) diff --git a/libs/libdecrypt/test/src/main.cpp b/libs/libdecrypt/test/src/main.cpp new file mode 100644 index 00000000000..bef37480be1 --- /dev/null +++ b/libs/libdecrypt/test/src/main.cpp @@ -0,0 +1,33 @@ +#include "test.h" + +int main() { + std::string testFilePath = "test.xml"; + std::string publicKeyFile = PUBLIC_KEY_FILE; // Path to your public key file + std::string encryptedFilePath = "test.xmle"; + + // Step 1: Create a test XML file + createTestXMLFile(testFilePath); + + std::string originalContent = readFileToString(testFilePath); + + // Step 2: Encrypt XML content + Encryption encryption; + if (!encryption.encryptFile(publicKeyFile, testFilePath)) { + std::cerr << "Encryption failed" << std::endl; + return 1; + } + + // Step 3: Decrypt XML content + Decryption decryption(encryptedFilePath); + std::string decryptedContent = decryption.getDecryptedContent(); + + // Step 4: Compare original XML content with decrypted XML content + if (decryptedContent == originalContent) { + std::cout << "Test passed: Decrypted content matches original content" << std::endl; + } else { + std::cerr << "Test failed: Decrypted content does not match original content" << std::endl; + return 1; + } + + return 0; +} \ No newline at end of file diff --git a/libs/libdecrypt/test/src/test.cpp b/libs/libdecrypt/test/src/test.cpp new file mode 100644 index 00000000000..e88b7cc1675 --- /dev/null +++ b/libs/libdecrypt/test/src/test.cpp @@ -0,0 +1,22 @@ +#include "test.h" + +#ifndef PUBLIC_KEY_FILE +#define PUBLIC_KEY_FILE "public_key.pem" // Default public key file +#endif + +// Function to create a sample XML file for testing +void createTestXMLFile(const std::string& filePath) { + std::ofstream outFile(filePath); + outFile << "\n"; + outFile << " Encryption Data\n"; + outFile << ""; + outFile.close(); +} + +// Function to read the contents of a file into a string +std::string readFileToString(const std::string& filePath) { + std::ifstream inFile(filePath); + std::string content((std::istreambuf_iterator(inFile)), std::istreambuf_iterator()); + inFile.close(); + return content; +} \ No newline at end of file diff --git a/libs/libdecrypt/test/src/test.h b/libs/libdecrypt/test/src/test.h new file mode 100644 index 00000000000..7b1c0ffe068 --- /dev/null +++ b/libs/libdecrypt/test/src/test.h @@ -0,0 +1,14 @@ +#ifndef TEST_H +#define TEST_H + +#include +#include +#include +#include "encryption.h" +#include "decryption.h" + +void createTestXMLFile(const std::string& filePath); +std::string readFileToString(const std::string& filePath); + + +#endif // TEST_H \ No newline at end of file From 18be453e40c1992e87f5127c3469a79e2bd218fd Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Wed, 10 Jul 2024 15:42:28 +0500 Subject: [PATCH 322/453] Updating CMake for libencrypt --- libs/libencrypt/CMakeLists.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/libs/libencrypt/CMakeLists.txt b/libs/libencrypt/CMakeLists.txt index 507abb227de..56faac3acab 100644 --- a/libs/libencrypt/CMakeLists.txt +++ b/libs/libencrypt/CMakeLists.txt @@ -24,14 +24,17 @@ foreach(_headerFile ${LIB_HEADERS}) endforeach() list(REMOVE_DUPLICATES LIB_INCLUDE_DIRS) +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/src) +add_library(libencrypt ${LIB_HEADERS} ${LIB_SOURCES}) + +set_target_properties(libencrypt PROPERTIES PREFIX "") + +target_link_libraries(libencrypt PRIVATE ${OPENSSL_LIBRARIES} libpugixml) # Add executable add_executable(encrypt main.cpp ${LIB_HEADERS} ${LIB_SOURCES} ) -target_include_directories(encrypt PRIVATE - ${CMAKE_CURRENT_SOURCE_DIR}/src -) target_link_libraries(encrypt PRIVATE ${OPENSSL_LIBRARIES} libpugixml) #install(TARGETS libencrypt DESTINATION bin) From 6537c7394d0ea3784faa7375a78fa5aa2a5cacc1 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Wed, 10 Jul 2024 16:22:07 +0500 Subject: [PATCH 323/453] Correcting typo and removing valgrind call from workflow file --- .github/workflows/test.yml | 2 +- libs/libdecrypt/test/CMakeLists.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 740ac53a3f6..77bfa6fafe5 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -509,4 +509,4 @@ jobs: - name: Test_Encryption_Decryption shell: bash run: | - valgrind ./build/libs/libdecrypt/test/test_encrypt_decrypt \ No newline at end of file + ./build/libs/libdecrypt/test/test_encrypt_decrypt \ No newline at end of file diff --git a/libs/libdecrypt/test/CMakeLists.txt b/libs/libdecrypt/test/CMakeLists.txt index 8a44053acd3..3e1f27ee6d7 100644 --- a/libs/libdecrypt/test/CMakeLists.txt +++ b/libs/libdecrypt/test/CMakeLists.txt @@ -10,7 +10,7 @@ set(PUBLIC_KEY_FILE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/../../libencrypt/public_ke target_compile_definitions(test_encrypt_decrypt PRIVATE PUBLIC_KEY_FILE="${PUBLIC_KEY_FILE_PATH}") include_directories("${CMAKE_CURRENT_SOURCE_DIR}/../../libencrypt/src" - "${CMAKE_CURRENT_SOURCE_DIR}/../libdecrypt/src" + "${CMAKE_CURRENT_SOURCE_DIR}/../src" "${CMAKE_CURRENT_SOURCE_DIR}/src") target_link_libraries(test_encrypt_decrypt From dd5e47088ed44ac8fb4aed92259438145fcf9e19 Mon Sep 17 00:00:00 2001 From: behzadmehmood Date: Wed, 10 Jul 2024 17:46:49 +0500 Subject: [PATCH 324/453] Updating build path for Test_Encryption_Decryption --- .github/workflows/test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 77bfa6fafe5..a12c0130709 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -509,4 +509,4 @@ jobs: - name: Test_Encryption_Decryption shell: bash run: | - ./build/libs/libdecrypt/test/test_encrypt_decrypt \ No newline at end of file + /root/vtr-verilog-to-routing/vtr-verilog-to-routing/build/libs/libdecrypt/test/test_encrypt_decrypt \ No newline at end of file From 75e867653d5f465b2a987b9cc4495373ae7c1f8c Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 13 Jul 2024 13:49:03 +0800 Subject: [PATCH 325/453] Update alloc_and_load_rr_indexed_data.cpp --- libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 7eb6ded1579..0bbe3e01bcd 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -350,6 +350,7 @@ static void load_rr_indexed_data_base_costs(const RRGraphView& rr_graph, rr_indexed_data[RRIndexedDataId(SOURCE_COST_INDEX)].base_cost = delay_normalization_fac; rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost = 0.; + rr_indexed_data[RRIndexedDataId(MEDIUM_COST_INDEX)].base_cost = delay_normalization_fac; rr_indexed_data[RRIndexedDataId(OPIN_COST_INDEX)].base_cost = delay_normalization_fac; // If the SPEC_CPU flag is set, we need to make sure that all floating point numbers are perfectly representable in // binary format. Thus, we changed the IPIN_COST_INDEX base cost from 0.95 to 0.875. From 0f81e9492596be30e80caccbce7a85a00cd1a281 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 13 Jul 2024 13:54:20 +0800 Subject: [PATCH 326/453] Update read_route.cpp --- vpr/src/base/read_route.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index 495350dc761..84ccdbf5814 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -628,6 +628,10 @@ void print_route(const Netlist<>& net_list, } break; + case MEDIUM: + fprintf(fp, " INDEX: "); + break; + default: VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in print_route: Unexpected traceback element type: %d (%s).\n", From 9e0ae2859a3461202b428999d40d2950007cc91c Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 13 Jul 2024 13:58:24 +0800 Subject: [PATCH 327/453] Update describe_rr_node.cpp --- libs/librrgraph/src/utils/describe_rr_node.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/libs/librrgraph/src/utils/describe_rr_node.cpp b/libs/librrgraph/src/utils/describe_rr_node.cpp index a4982cce8f7..00f4159058a 100644 --- a/libs/librrgraph/src/utils/describe_rr_node.cpp +++ b/libs/librrgraph/src/utils/describe_rr_node.cpp @@ -37,6 +37,11 @@ std::string describe_rr_node(const RRGraphView& rr_graph, msg += vtr::string_fmt(" pin: %d pin_name: %s", rr_graph.node_pin_num(inode), pin_name.c_str()); + } else if (rr_graph.node_type(inode) == MEDIUM) { + auto index = rr_graph.node_ptc_num(inode); + + msg += vtr::string_fmt(" medium index: %d", + index); } else { VTR_ASSERT(rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK); @@ -50,4 +55,4 @@ std::string describe_rr_node(const RRGraphView& rr_graph, msg += " " + rr_graph.node_coordinate_to_string(inode); return msg; -} \ No newline at end of file +} From b65a8e24330a8d8a81bfd2081528ff8c3988cde5 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 13 Jul 2024 14:00:21 +0800 Subject: [PATCH 328/453] Update check_route.cpp --- vpr/src/route/check_route.cpp | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index d01fa95b56c..e13d8ca3ba5 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -328,7 +328,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { case OPIN: from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); - if (to_type == CHANX || to_type == CHANY) { + if (to_type == CHANX || to_type == CHANY || to_type == MEDIUM) { num_adj += 1; //adjacent } else if (is_flat) { VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster @@ -403,6 +403,8 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } } else if (to_type == CHANY) { num_adj += chanx_chany_adjacent(from_node, to_node); + } else if (to_type == MEDIUM) { + num_adj += 1; } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_adjacent: %d and %d are not adjacent", from_node, to_node); @@ -435,12 +437,28 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } } else if (to_type == CHANX) { num_adj += chanx_chany_adjacent(to_node, from_node); + } else if (to_type == MEDIUM) { + num_adj += 1; } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_adjacent: %d and %d are not adjacent", from_node, to_node); } break; + case MEDIUM: + //from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); + if (to_type == CHANX || to_type == CHANY || to_type == MEDIUM) { + num_adj += 1; //adjacent + } else if (is_flat) { + VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster + return true; + } else { + VTR_ASSERT(to_type == IPIN); + num_adj += 1; + } + + break; + default: break; } From abaec29b3f35ff07b15d523f2503ec1c49852e93 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 13 Jul 2024 14:04:14 +0800 Subject: [PATCH 329/453] Update rr_graph_area.cpp --- vpr/src/route/rr_graph_area.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp index 3ac736eebd8..75d99f2fde2 100644 --- a/vpr/src/route/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_area.cpp @@ -377,6 +377,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* from_rr_type = rr_graph.node_type(from_rr_node); switch (from_rr_type) { + case MEDIUM: case CHANX: case CHANY: num_edges = rr_graph.num_edges(RRNodeId(from_node)); @@ -392,6 +393,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* } switch (to_rr_type) { + case MEDIUM: case CHANX: case CHANY: if (!chan_node_switch_done[size_t(to_node)]) { @@ -465,7 +467,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* for (i = rr_graph.node_xlow(from_rr_node); i <= rr_graph.node_xhigh(from_rr_node); i++) cblock_counted[i] = false; - } else { /* CHANY */ + } else if (from_rr_type == CHANY) { /* CHANY */ for (j = rr_graph.node_ylow(from_rr_node); j <= rr_graph.node_yhigh(from_rr_node); j++) cblock_counted[j] = false; From e6b7e7d0687250fde0c6b40d0fb04da51348a06a Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 13 Jul 2024 14:07:12 +0800 Subject: [PATCH 330/453] Update tileable_rr_graph_edge_builder.cpp --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 717d8b8069f..bd9925338bc 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -209,7 +209,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, size_t ix, iy; // process top boundary iy = grids.height() - 1; - for (ix = 0; ix < grids.width() - 2; ++ix) { + for (ix = 0; ix < grids.width() - 1; ++ix) { vtr::Point actual_coord(ix, iy); vtr::Point gsb_coord(ix, iy - 1); @@ -236,7 +236,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // process right boundary ix = grids.width() - 1; - for (iy = 0; iy < grids.height() - 2; ++iy) { + for (iy = 0; iy < grids.height() - 1; ++iy) { vtr::Point actual_coord(ix, iy); vtr::Point gsb_coord(ix - 1, iy); From 30dae5ac08adf59e3f470dfb4249efdad55defc9 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 13 Jul 2024 18:17:40 +0800 Subject: [PATCH 331/453] Update tileable_chan_details_builder.cpp --- .../tileable_chan_details_builder.cpp | 37 ++++++++++++++++++- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index be3a9b3e84f..78c88043156 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -221,8 +221,41 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, num_tracks_bend.push_back(num_tracks[iseg] * seg_len[i] / segment_inf[iseg].length); VTR_ASSERT(num_tracks_bend[0] + num_tracks_bend[1] == num_tracks[iseg]); + + for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { + bool seg_start = false; + bool seg_end = false; + size_t seg_bend_start = 0; + size_t seg_bend_end = 0; + + if (0 == itrack % segment_inf[iseg].length) { + seg_start = true; + } + + if (seg_len[0] == int(itrack) % segment_inf[iseg].length) { + seg_start = true; + seg_bend_start = bend_num; + } + + if (seg_len[0] - 1 == int(itrack) % segment_inf[iseg].length) { + seg_end = true; + seg_bend_end = bend_num; + } + + if ((segment_inf[iseg].length - 1 == int(itrack) % segment_inf[iseg].length) + || (itrack == num_tracks[iseg] - 1)) { + seg_end = true; + } + + int seg_index = segment_inf[iseg].seg_index; + + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + } - for (size_t itrack = 0; itrack < num_tracks_bend[0]; ++itrack) { + /*for (size_t itrack = 0; itrack < num_tracks_bend[0]; ++itrack) { bool seg_start = false; bool seg_end = false; @@ -270,7 +303,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); cur_track++; - } + }*/ } } /* Check if all the tracks have been satisified */ From 6d1dd98b8d1098e6c9a28a9f0f84073f3310189d Mon Sep 17 00:00:00 2001 From: NadeemYaseen Date: Sat, 13 Jul 2024 09:10:24 -0700 Subject: [PATCH 332/453] added unit test for libdecryption --- .github/workflows/test.yml | 13 ------------- libs/libdecrypt/test/CMakeLists.txt | 2 ++ 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index a12c0130709..748d19b80c9 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -497,16 +497,3 @@ jobs: run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" ./.github/scripts/build.sh - - test_xml_encryption: - name: 'Encryption/Decryption test' - strategy: - fail-fast: false - needs: Build - runs-on: ubuntu-22.04 - - steps: - - name: Test_Encryption_Decryption - shell: bash - run: | - /root/vtr-verilog-to-routing/vtr-verilog-to-routing/build/libs/libdecrypt/test/test_encrypt_decrypt \ No newline at end of file diff --git a/libs/libdecrypt/test/CMakeLists.txt b/libs/libdecrypt/test/CMakeLists.txt index 3e1f27ee6d7..919d87ce183 100644 --- a/libs/libdecrypt/test/CMakeLists.txt +++ b/libs/libdecrypt/test/CMakeLists.txt @@ -17,3 +17,5 @@ target_link_libraries(test_encrypt_decrypt libpugixml libdecrypt libencrypt) + +add_test(NAME test_encrypt_decrypt COMMAND test_encrypt_decrypt) \ No newline at end of file From cc8816a543c32f2c59aad8e81f34ca71770a5982 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 14 Jul 2024 12:30:49 +0800 Subject: [PATCH 333/453] Update read_xml_arch_file.cpp --- libs/libarchfpga/src/read_xml_arch_file.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 0d0d90392c1..8ee4dac32b6 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -306,12 +306,12 @@ static void ProcessLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc static void ProcessVibLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data); /* Added for vib_layout*/ -static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment* strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); +static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); /* Added for vib_layout*/ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, int die_number, - vtr::string_internment* strings, + vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); @@ -5698,14 +5698,14 @@ static void ProcessVibLayout(pugi::xml_node vib_layout_tag, t_arch* arch, const int num_of_avail_layer; for (auto vib_layout_type_tag : vib_layout_tag.children()) { - t_vib_grid_def grid_def = ProcessVibGridLayout(&arch->strings, vib_layout_type_tag, loc_data, arch, num_of_avail_layer); + t_vib_grid_def grid_def = ProcessVibGridLayout(arch->strings, vib_layout_type_tag, loc_data, arch, num_of_avail_layer); arch->vib_grid_layouts.emplace_back(std::move(grid_def)); } } -static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment* strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer) { +static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer) { t_vib_grid_def grid_def; num_of_avail_layer = get_number_of_layers(layout_type_tag, loc_data); bool has_layer = layout_type_tag.child("layer"); @@ -5784,7 +5784,7 @@ static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment* strings, pugi static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, int die_number, - vtr::string_internment* strings, + vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data) { //Process all the block location specifications From 70e4f5a127c8c471933b4c3de5e60fecd9359c0c Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 14 Jul 2024 13:22:15 +0800 Subject: [PATCH 334/453] Update vpr_utils.h --- vpr/src/util/vpr_utils.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 68f1c351b77..27d8bc81e2b 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -260,6 +260,9 @@ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, t_rr_type node_type, int node_ptc); +bool is_inter_cluster_node(const RRGraphView& rr_graph_view, + RRNodeId node_id); + int get_rr_node_max_ptc(const RRGraphView& rr_graph_view, RRNodeId node_id, bool is_flat); From cabf2ea59950540e692adf75560787e8df8d6f6a Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 14 Jul 2024 13:23:20 +0800 Subject: [PATCH 335/453] Update vpr_utils.cpp --- vpr/src/util/vpr_utils.cpp | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index d4b45a24cd8..6de083390bd 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2279,6 +2279,26 @@ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, } } +bool is_inter_cluster_node(const RRGraphView& rr_graph_view, + RRNodeId node_id) { + auto node_type = rr_graph_view.node_type(node_id); + if (node_type == CHANX || node_type == CHANY) { + return true; + } else { + int x_low = rr_graph_view.node_xlow(node_id); + int y_low = rr_graph_view.node_ylow(node_id); + int layer = rr_graph_view.node_layer(node_id); + int node_ptc = rr_graph_view.node_ptc_num(node_id); + const t_physical_tile_type_ptr physical_tile = g_vpr_ctx.device().grid.get_physical_type({x_low, y_low, layer}); + if (node_type == IPIN || node_type == OPIN) { + return is_pin_on_tile(physical_tile, node_ptc); + } else { + VTR_ASSERT_DEBUG(node_type == SINK || node_type == SOURCE); + return is_class_on_tile(physical_tile, node_ptc); + } + } +} + int get_rr_node_max_ptc(const RRGraphView& rr_graph_view, RRNodeId node_id, bool is_flat) { From 0ead1a887ea311f5a479db15fb634d3f4d1cbd30 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 14 Jul 2024 13:54:01 +0800 Subject: [PATCH 336/453] Update router_lookahead_map_utils.cpp --- vpr/src/route/router_lookahead_map_utils.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index f35bb2cee3d..b337e842d52 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -1409,7 +1409,9 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, for (t_edge_size edge : rr_graph.edges(parent)) { RRNodeId child_node = rr_graph.edge_sink_node(parent, edge); // For the time being, we decide to not let the lookahead explore the node inside the clusters - + t_physical_tile_type_ptr physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(child_node), + rr_graph.node_ylow(child_node), + rr_graph.node_layer(child_node)}); const t_vib_inf* vib; if (device_ctx.arch->is_vib_arch) { vib = device_ctx.vib_grid[rr_graph.node_layer(child_node)][rr_graph.node_xlow(child_node)][rr_graph.node_ylow(child_node)]; From 07627be77d0723fa068b2338705fc9b2474d3890 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 14 Jul 2024 14:05:19 +0800 Subject: [PATCH 337/453] Update tileable_rr_graph_builder.cpp --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 222571acab6..a5949aa1c0e 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -325,7 +325,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* No clock network support yet; Does not support flatten rr_graph yet */ - check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, vib_grid, device_ctx.chan_width, GRAPH_UNIDIR, OPEN, false); + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, vib_grid, device_ctx.chan_width, GRAPH_UNIDIR, false); /************************************************************************ From efb99fce6d40a222e4bf85e4d1884fe464872f14 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 14 Jul 2024 14:10:08 +0800 Subject: [PATCH 338/453] Update vpr_utils.cpp --- vpr/src/util/vpr_utils.cpp | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 6de083390bd..7bc70551868 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2265,15 +2265,11 @@ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, VTR_ASSERT(vib != nullptr); return (node_ptc < (int)vib->first_stages.size()); } else { - int x_low = rr_graph_view.node_xlow(node_id); - int y_low = rr_graph_view.node_ylow(node_id); - int layer = rr_graph_view.node_layer(node_id); - int node_ptc = rr_graph_view.node_ptc_num(node_id); - const t_physical_tile_type_ptr physical_tile = g_vpr_ctx.device().grid.get_physical_type({x_low, y_low, layer}); + VTR_ASSERT(node_type == IPIN || node_type == OPIN || node_type == SINK || node_type == SOURCE); if (node_type == IPIN || node_type == OPIN) { return is_pin_on_tile(physical_tile, node_ptc); } else { - VTR_ASSERT_DEBUG(node_type == SINK || node_type == SOURCE); + VTR_ASSERT(node_type == SINK || node_type == SOURCE); return is_class_on_tile(physical_tile, node_ptc); } } From 510f4e2559023945eefce82724d7a3c38f1538c6 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 14 Jul 2024 15:10:23 +0800 Subject: [PATCH 339/453] Update SetupGrid.h --- vpr/src/base/SetupGrid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 12cab1408ab..98fe1e0ac51 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -21,7 +21,7 @@ DeviceGrid create_device_grid(const std::string& layout_name, ///@brief Find the device close in size to the specified dimensions -DeviceGrid create_device_grid(std::string layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); +DeviceGrid create_device_grid(std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts); /** From 993aca5ec94b0c3954ae3cdec1c6706b1c3e4d3b Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sun, 14 Jul 2024 15:17:48 +0800 Subject: [PATCH 340/453] Update SetupGrid.h --- vpr/src/base/SetupGrid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 98fe1e0ac51..2f3ab6bc1b1 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -21,7 +21,7 @@ DeviceGrid create_device_grid(const std::string& layout_name, ///@brief Find the device close in size to the specified dimensions -DeviceGrid create_device_grid(std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); +DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts); /** From 9ddf4ca42db3a0f833a264a21eafcc0b93d1bf85 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 13:57:02 -0700 Subject: [PATCH 341/453] [core] adapt to side var changes --- libs/librrgraph/src/base/rr_graph_builder.cpp | 2 +- libs/librrgraph/src/base/rr_graph_builder.h | 2 +- vpr/src/route/rr_graph.cpp | 1 + .../openfpga_rr_graph_utils.cpp | 6 ++--- .../openfpga_side_manager.cpp | 12 ++++----- .../tileable_rr_graph/rr_graph_view_util.cpp | 4 +-- vpr/src/tileable_rr_graph/rr_gsb.cpp | 26 +++++++++---------- vpr/src/tileable_rr_graph/rr_gsb.h | 2 +- .../tileable_rr_graph_edge_builder.cpp | 2 +- .../tileable_rr_graph_gsb.cpp | 6 ++--- .../tileable_rr_graph_node_builder.cpp | 8 +++--- 11 files changed, 36 insertions(+), 35 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 9fbf40cb719..fbf442e1972 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -78,7 +78,7 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { } RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side) { - e_side node_side = SIDES[0]; + e_side node_side = TOTAL_2D_SIDES[0]; /* Only OPIN and IPIN nodes have sides, otherwise force to use a default side */ if (OPIN == type || IPIN == type) { node_side = side; diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 5ef11b45a43..d44ad3e972f 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -131,7 +131,7 @@ class RRGraphBuilder { /** @brief Create a new rr_node in the node storage and register it to the node look-up. * Return a valid node id if succeed. Otherwise, return an invalid id. */ - RRNodeId create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side = NUM_SIDES); + RRNodeId create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side = NUM_2D_SIDES); /** @brief Set the node name with a given valid id */ inline void set_node_name(RRNodeId id, std::string name) { diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 3cd2b5f2a01..623b3eb5918 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -744,6 +744,7 @@ void create_rr_graph(const t_graph_type graph_type, det_routing_arch->global_route_switch, det_routing_arch->wire_to_arch_ipin_switch, det_routing_arch->wire_to_arch_ipin_switch_between_dice, + router_opts.custom_3d_sb_fanin_fanout, det_routing_arch->delayless_switch, det_routing_arch->R_minW_nmos, det_routing_arch->R_minW_pmos, diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index ea3b52a5440..a73ff2f15d5 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -188,14 +188,14 @@ bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, * Note that this function expect one valid side to be got. Otherwise, it will fail! */ e_side get_rr_graph_single_node_side(const RRGraphView& rr_graph, const RRNodeId& node) { - e_side node_side = NUM_SIDES; + e_side node_side = NUM_2D_SIDES; int num_sides = 0; - for (e_side candidate_side : SIDES) { + for (e_side candidate_side : TOTAL_2D_SIDES) { if (rr_graph.is_node_on_specific_side(node, candidate_side)) { node_side = candidate_side; num_sides++; } } - VTR_ASSERT(1 == num_sides && node_side != NUM_SIDES); + VTR_ASSERT(1 == num_sides && node_side != NUM_2D_SIDES); return node_side; } diff --git a/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp b/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp index 3b1ee1ec404..ebef0dd0a9c 100644 --- a/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp @@ -9,7 +9,7 @@ SideManager::SideManager(enum e_side side) { } SideManager::SideManager() { - side_ = NUM_SIDES; + side_ = NUM_2D_SIDES; } SideManager::SideManager(size_t side) { @@ -32,7 +32,7 @@ enum e_side SideManager::get_opposite() const { case LEFT: return RIGHT; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } @@ -47,7 +47,7 @@ enum e_side SideManager::get_rotate_clockwise() const { case LEFT: return TOP; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } @@ -62,12 +62,12 @@ enum e_side SideManager::get_rotate_counterclockwise() const { case LEFT: return BOTTOM; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } bool SideManager::validate() const { - if (NUM_SIDES == side_) { + if (NUM_2D_SIDES == side_) { return false; } return true; @@ -144,7 +144,7 @@ void SideManager::set_side(size_t side) { side_ = LEFT; return; default: - side_ = NUM_SIDES; + side_ = NUM_2D_SIDES; return; } } diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 9a1a1361274..9698ac03b45 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -45,7 +45,7 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, if (rr_type == IPIN || rr_type == OPIN) { //For pins we need to look at all the sides of the current grid tile - for (e_side side : SIDES) { + for (e_side side : TOTAL_2D_SIDES) { RRNodeId rr_node_index = rr_graph.node_lookup().find_node(layer, x, y, rr_type, ptc, side); if (rr_node_index != RRNodeId::INVALID()) { @@ -106,7 +106,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, } /* Ensure we have a valid side */ - VTR_ASSERT(side != NUM_SIDES); + VTR_ASSERT(side != NUM_2D_SIDES); /* Find all the pins on the side of the grid */ t_physical_tile_loc tile_loc(x, y, layer); diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 2ad75efe745..64401b7d5e2 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -28,7 +28,7 @@ RRGSB::RRGSB() { opin_node_.clear(); for (size_t icb_type = 0; icb_type < 2; icb_type++) { - for (size_t iside = 0; iside < NUM_SIDES; iside++) { + for (size_t iside = 0; iside < NUM_2D_SIDES; iside++) { cb_opin_node_[icb_type][iside].clear(); } } @@ -401,7 +401,7 @@ void RRGSB::get_node_side_and_index(const RRGraphView& rr_graph, if (side == get_num_sides()) { /* we find nothing, return NUM_SIDES, and a OPEN node (-1) */ - node_side = NUM_SIDES; + node_side = NUM_2D_SIDES; VTR_ASSERT(-1 == node_index); return; } @@ -517,7 +517,7 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, */ if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) { VTR_LOG("Cannot find a node on the opposite side to GSB[%lu][%lu] track node[%lu] at %s!\nDetailed node information:\n", - get_x(), get_y(), track_id, SIDE_STRING[node_side]); + get_x(), get_y(), track_id, TOTAL_2D_SIDE_STRINGS[node_side]); VTR_LOG("Node type: %s\n", rr_graph.node_type_string(track_node)); VTR_LOG("Node coordinate: %s\n", rr_graph.node_coordinate_to_string(track_node).c_str()); VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(track_node)); @@ -790,12 +790,12 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) { /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); - e_side side = NUM_SIDES; + e_side side = NUM_2D_SIDES; int index = 0; get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index); /* Must have valid side and index */ - if (NUM_SIDES == side) { + if (NUM_2D_SIDES == side) { VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG("----------------------------------\n"); VTR_LOG("SRC node:\n"); @@ -815,7 +815,7 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, } } - VTR_ASSERT(NUM_SIDES != side); + VTR_ASSERT(NUM_2D_SIDES != side); VTR_ASSERT(OPEN != index); if (OPIN == rr_graph.node_type(src_node)) { @@ -873,7 +873,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const e_side& ipin_side, const size_t& ipin_id) { std::map from_track_edge_map; - std::array, NUM_SIDES> from_opin_edge_map; + std::array, NUM_2D_SIDES> from_opin_edge_map; e_side chan_side = get_cb_chan_side(ipin_side); @@ -944,13 +944,13 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, if (OPIN != rr_graph.node_type(src_node)) { continue; } - enum e_side cb_opin_side = NUM_SIDES; + enum e_side cb_opin_side = NUM_2D_SIDES; int cb_opin_index = -1; get_node_side_and_index(rr_graph, src_node, IN_PORT, cb_opin_side, cb_opin_index); - VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); + VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); /* Must have valid side and index */ - if (OPEN == cb_opin_index || NUM_SIDES == cb_opin_side) { + if (OPEN == cb_opin_index || NUM_2D_SIDES == cb_opin_side) { VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG("----------------------------------\n"); VTR_LOG("SRC node:\n"); @@ -1021,11 +1021,11 @@ void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { if (OPIN != rr_graph.node_type(cand_node)) { continue; } - enum e_side cb_opin_side = NUM_SIDES; + enum e_side cb_opin_side = NUM_2D_SIDES; int cb_opin_index = -1; get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, cb_opin_index); - if ((-1 == cb_opin_index) || (NUM_SIDES == cb_opin_side)) { + if ((-1 == cb_opin_index) || (NUM_2D_SIDES == cb_opin_side)) { VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG("----------------------------------\n"); VTR_LOG("SRC node:\n"); @@ -1036,7 +1036,7 @@ void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); } } - VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); + VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == std::find(cb_opin_node_[icb_type][size_t(cb_opin_side)].begin(), cb_opin_node_[icb_type][size_t(cb_opin_side)].end(), cand_node)) { diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 7a5206b48b5..fce23ac2415 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -268,7 +268,7 @@ class RRGSB { * CBX -> array[0], CBY -> array[1] * Each CB may have OPINs from all sides */ - std::array, NUM_SIDES>, 2> cb_opin_node_; + std::array, NUM_2D_SIDES>, 2> cb_opin_node_; }; #endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index baa97d8d348..d6b8a5e57f7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -79,7 +79,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, const RRNodeId& sink_node = rr_graph.node_lookup().find_node(layer, xlow - grids.get_width_offset(tile_loc), ylow - grids.get_height_offset(tile_loc), - SINK, sink_node_class_num, SIDES[0]); + SINK, sink_node_class_num, TOTAL_2D_SIDES[0]); VTR_ASSERT(true == rr_graph.valid_node(sink_node)); /* add edges to connect the IPIN node to SINK nodes */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index b97454f1559..b831eeb9e87 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -646,7 +646,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, vtr::Point coordinate = rr_gsb.get_side_block_coordinate(side_manager.get_side()); RRChan rr_chan; std::vector> temp_opin_rr_nodes(2); - enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; + enum e_side opin_grid_side[2] = {NUM_2D_SIDES, NUM_2D_SIDES}; enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ /* Build a segment details, where we need the segment ids for building rr_chan @@ -817,8 +817,8 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Clear the temp data */ temp_opin_rr_nodes[0].clear(); temp_opin_rr_nodes[1].clear(); - opin_grid_side[0] = NUM_SIDES; - opin_grid_side[1] = NUM_SIDES; + opin_grid_side[0] = NUM_2D_SIDES; + opin_grid_side[1] = NUM_2D_SIDES; } /* Add IPIN nodes from adjacent grids: the 4 grids sitting on the 4 corners of the Switch Block diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index e9510133acd..38ac52efc53 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -730,12 +730,12 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::Point(root_x, root_y), vtr::Point(x, y), SOURCE, - SIDES[0]); + TOTAL_2D_SIDES[0]); rr_graph_builder.node_lookup().mirror_nodes(0, vtr::Point(root_x, root_y), vtr::Point(x, y), SINK, - SIDES[0]); + TOTAL_2D_SIDES[0]); } } } @@ -1195,9 +1195,9 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, * When comment the following block out, you will see errors */ for (t_rr_type rr_type : RR_TYPES) { if (rr_type == CHANX) { - rr_graph_builder.node_lookup().resize_nodes(layer, grids.height(), grids.width(), rr_type, NUM_SIDES); + rr_graph_builder.node_lookup().resize_nodes(layer, grids.height(), grids.width(), rr_type, NUM_2D_SIDES); } else { - rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_SIDES); + rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_2D_SIDES); } } From 585bd4fb2bc334e1a3881642c2bdfbbdeb04c78a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 15:52:25 -0700 Subject: [PATCH 342/453] [core] fixed a bug where sink node cannot be mirror --- libs/librrgraph/src/base/rr_spatial_lookup.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 79353bb0ac5..47cf74f5daf 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -316,7 +316,7 @@ void RRSpatialLookup::mirror_nodes(const int layer, const vtr::Point& des_coord, t_rr_type type, e_side side) { - VTR_ASSERT(SOURCE == type); + VTR_ASSERT(SOURCE == type || SINK == type); resize_nodes(layer, des_coord.x(), des_coord.y(), type, side); rr_node_indices_[type][layer][des_coord.x()][des_coord.y()][side] = rr_node_indices_[type][layer][src_coord.x()][src_coord.y()][side]; } From 876311af4b7ae2e9d4f667da43921495bad8fb5c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Oct 2024 12:25:51 -0700 Subject: [PATCH 343/453] [core] fix the bug where skip sync-routing results are not applicable to flat routing --- vpr/src/base/vpr_api.cpp | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index bb384c7d3da..9a697da4891 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1482,19 +1482,19 @@ bool vpr_analysis_flow(const Netlist<>& net_list, * for packer (default verbosity is set to 2 for compact logs) */ if (route_status.success()) { - if (is_flat) { - sync_netlists_to_routing_flat(); - } else { - if (!analysis_opts.skip_sync_clustering_and_routing_results) { - sync_netlists_to_routing(net_list, - g_vpr_ctx.device(), - g_vpr_ctx.mutable_atom(), - g_vpr_ctx.mutable_clustering(), - g_vpr_ctx.placement(), - vpr_setup.PackerOpts.pack_verbosity > 2); + if (!analysis_opts.skip_sync_clustering_and_routing_results) { + if (is_flat) { + sync_netlists_to_routing_flat(); } else { - VTR_LOG_WARN("Sychronization between packing and routing results is not applied due to users select to skip it\n"); + sync_netlists_to_routing(net_list, + g_vpr_ctx.device(), + g_vpr_ctx.mutable_atom(), + g_vpr_ctx.mutable_clustering(), + g_vpr_ctx.placement(), + vpr_setup.PackerOpts.pack_verbosity > 2); } + } else { + VTR_LOG_WARN("Sychronization between packing and routing results is not applied due to users select to skip it\n"); } std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing"; From 1afa2f58f9f3037ec1617fc3d1b7e064f91a2795 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:08:10 +0800 Subject: [PATCH 344/453] Create vib_inf.cpp --- libs/libarchfpga/src/vib_inf.cpp | 109 +++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 libs/libarchfpga/src/vib_inf.cpp diff --git a/libs/libarchfpga/src/vib_inf.cpp b/libs/libarchfpga/src/vib_inf.cpp new file mode 100644 index 00000000000..89dbab16355 --- /dev/null +++ b/libs/libarchfpga/src/vib_inf.cpp @@ -0,0 +1,109 @@ +#include "vib_inf.h" +// #include "vtr_math.h" +// #include "vtr_util.h" +// #include "vtr_log.h" + +// #include "arch_util.h" + +VibInf::VibInf() { + name_.clear(); + pbtype_name_.clear(); + seg_group_num_ = 0; + switch_idx_ = -1; + seg_groups_.clear(); + first_stages_.clear(); + second_stages_.clear(); +} + +void VibInf::set_name(const std::string name) { + VTR_ASSERT(!name.empty()); + name_ = name; +} + +void VibInf::set_pbtype_name(const std::string pbtype_name) { + VTR_ASSERT(!pbtype_name.empty()); + pbtype_name_ = pbtype_name; +} + +void VibInf::set_seg_group_num(const int seg_group_num) { + VTR_ASSERT(seg_group_num >= 0); + seg_group_num_ = seg_group_num; +} + +void VibInf::set_switch_idx(const int switch_idx) { + VTR_ASSERT(switch_idx != -1); + switch_idx_ = switch_idx; +} + +void VibInf::set_seg_groups(const std::vector seg_groups) { + VTR_ASSERT(!seg_groups.empty()); + for(auto seg_group : seg_groups) { + seg_groups_.push_back(seg_group); + } +} + +void VibInf::push_seg_group(const t_seg_group seg_group) { + VTR_ASSERT(!seg_group.name.empty()); + seg_groups_.push_back(seg_group); +} + +void VibInf::set_first_stages(const std::vector first_stages) { + VTR_ASSERT(!first_stages.empty()); + for(auto first_stage : first_stages) { + first_stages_.push_back(first_stage); + } +} + +void VibInf::push_first_stage(const t_first_stage_mux_inf first_stage) { + VTR_ASSERT(!first_stage.mux_name.empty()); + first_stages_.push_back(first_stage); +} + +void VibInf::set_second_stages(const std::vector second_stages) { + VTR_ASSERT(!second_stages.empty()); + for(auto second_stage : second_stages) { + second_stages_.push_back(second_stage); + } +} + +void VibInf::push_second_stage(const t_second_stage_mux_inf second_stage) { + VTR_ASSERT(!second_stage.mux_name.empty()); + second_stages_.push_back(second_stage); +} + + + +std::string VibInf::get_name() const{ + VTR_ASSERT(!name_.empty()); + return name_; +} + +std::string VibInf::get_pbtype_name() const{ + VTR_ASSERT(!pbtype_name_.empty()); + return pbtype_name_; +} + +int VibInf::get_seg_group_num() const{ + VTR_ASSERT(seg_group_num_ >= 0); + return seg_group_num_; +} + +int VibInf::get_switch_idx() const{ + VTR_ASSERT(switch_idx_ != -1); + return switch_idx_; +} + +std::vector VibInf::get_seg_groups() const{ + VTR_ASSERT(!seg_groups_.empty()); + return seg_groups_; +} + +std::vector VibInf::get_first_stages() const{ + VTR_ASSERT(!first_stages_.empty()); + return first_stages_; +} + +std::vector VibInf::get_second_stages() const{ + VTR_ASSERT(!second_stages_.empty()); + return second_stages_; +} From f3deaa61a11b1973adca78175b9a38df12c7ed6a Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:08:41 +0800 Subject: [PATCH 345/453] Create vib_inf.h --- libs/libarchfpga/src/vib_inf.h | 104 +++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 libs/libarchfpga/src/vib_inf.h diff --git a/libs/libarchfpga/src/vib_inf.h b/libs/libarchfpga/src/vib_inf.h new file mode 100644 index 00000000000..73dcba8b284 --- /dev/null +++ b/libs/libarchfpga/src/vib_inf.h @@ -0,0 +1,104 @@ +#ifndef VIB_INF_H +#define VIB_INF_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vtr_ndmatrix.h" +#include "vtr_hash.h" +#include "vtr_bimap.h" +#include "vtr_string_interning.h" + +#include "logic_types.h" +#include "clock_types.h" + +//#include "physical_types.h" + + + +/* for vib tag */ +struct t_seg_group { + std::string name; + int seg_index; + int track_num; +}; + +enum e_multistage_mux_from_or_to_type { + PB = 0, + SEGMENT, + MUX +}; + +struct t_from_or_to_inf { + std::string type_name; + e_multistage_mux_from_or_to_type from_type; //from_or_to_type + int type_index = -1; + int phy_pin_index = -1; + char seg_dir = ' '; + int seg_index = -1; +}; + +struct t_first_stage_mux_inf { + std::string mux_name; + std::vector froms; +}; + +struct t_second_stage_mux_inf : t_first_stage_mux_inf { + std::vector to; // for io type, port[pin] may map to several sinks +}; + +// struct t_vib_inf { +// std::string name; /* vib name */ +// std::string pbtype_name; /* pbtype name of vib */ +// int seg_group_num; /* seg group number of vib */ +// int switch_idx; /* vib switch index */ +// std::vector seg_groups; +// std::vector first_stages; +// std::vector second_stages; +// }; + +class VibInf { + public: + VibInf(); + + public: + void set_name(const std::string name); + void set_pbtype_name(const std::string pbtype_name); + void set_seg_group_num(const int seg_group_num); + void set_switch_idx(const int switch_idx); + void set_seg_groups(const std::vector seg_groups); + void push_seg_group(const t_seg_group seg_group); + void set_first_stages(const std::vector first_stages); + void push_first_stage(const t_first_stage_mux_inf first_stage); + void set_second_stages(const std::vector second_stages); + void push_second_stage(const t_second_stage_mux_inf second_stage); + + std::string get_name() const; + std::string get_pbtype_name() const; + int get_seg_group_num() const; + int get_switch_idx() const; + std::vector get_seg_groups() const; + std::vector get_first_stages() const; + std::vector get_second_stages() const; + + + private: + std::string name_; /* vib name */ + std::string pbtype_name_; /* pbtype name of vib */ + int seg_group_num_; /* seg group number of vib */ + int switch_idx_; /* vib switch index */ + std::vector seg_groups_; + std::vector first_stages_; + std::vector second_stages_; +}; + +#endif From ccb5b56ffe78b6887deba37a73d6808ffcf2cbea Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:10:28 +0800 Subject: [PATCH 346/453] Update rr_graph_storage.h --- libs/librrgraph/src/base/rr_graph_storage.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 01327247578..8c472952673 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -53,7 +53,7 @@ * side: The side of a grid location where an IPIN or OPIN is located. * * This field is valid only for IPINs and OPINs and should be ignored * * otherwise. */ -struct alignas(64) t_rr_node_data { +struct alignas(32) t_rr_node_data { int16_t cost_index_ = -1; int16_t rc_index_ = -1; @@ -62,8 +62,8 @@ struct alignas(64) t_rr_node_data { int16_t xhigh_ = -1; int16_t yhigh_ = -1; - size_t node_bend_start_ = 0; - size_t node_bend_end_ = 0; + int16_t node_bend_start_ = 0; + int16_t node_bend_end_ = 0; t_rr_type type_ = NUM_RR_TYPES; @@ -88,8 +88,8 @@ struct alignas(64) t_rr_node_data { // t_rr_node_data is a key data structure, so fail at compile time if the // structure gets bigger than expected (16 bytes right now). Developers // should only expand it after careful consideration and measurement. -static_assert(sizeof(t_rr_node_data) == 64, "Check t_rr_node_data size"); -static_assert(alignof(t_rr_node_data) == 64, "Check t_rr_node_data size"); +static_assert(sizeof(t_rr_node_data) == 32, "Check t_rr_node_data size"); +static_assert(alignof(t_rr_node_data) == 32, "Check t_rr_node_data size"); /* t_rr_node_ptc_data is cold data is therefore kept seperate from * t_rr_node_data. From 3769b62659530b886df85b14ee8be1cfb1ec2a8b Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:11:21 +0800 Subject: [PATCH 347/453] Update physical_types.h --- libs/libarchfpga/src/physical_types.h | 108 ++++++++++---------------- 1 file changed, 42 insertions(+), 66 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index cf57ee710fb..c6d21d58793 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -47,6 +47,8 @@ #include "logic_types.h" #include "clock_types.h" +#include "vib_inf.h" + //Forward declarations struct t_clock_arch; struct t_clock_network; @@ -373,6 +375,31 @@ struct t_grid_loc_def { // that come from a common definition. }; +enum GridDefType { + AUTO, + FIXED +}; + +struct t_layer_def { + std::vector loc_defs; //The list of block location definitions for this layer specification +}; + +struct t_grid_def { + GridDefType grid_type = GridDefType::AUTO; //The type of this grid specification + + std::string name = ""; //The name of this device + + int width = -1; //Fixed device width (only valid for grid_type == FIXED) + int height = -1; //Fixed device height (only valid for grid_type == FIXED) + + float aspect_ratio = 1.; //Aspect ratio for auto-sized devices (only valid for + //grid_type == AUTO) + std::vector layers; +}; + +/************************* VIB_GRID ***********************************/ +/* Describe different VIB type on different locations by immitating t_grid_loc_def. */ + struct t_vib_grid_loc_def { t_vib_grid_loc_def(std::string block_type_val, int priority_val) : block_type(block_type_val) @@ -399,32 +426,10 @@ struct t_vib_grid_loc_def { // that come from a common definition. }; -enum GridDefType { - AUTO, - FIXED -}; - -struct t_layer_def { - std::vector loc_defs; //The list of block location definitions for this layer specification -}; - struct t_vib_layer_def { std::vector loc_defs; //The list of block location definitions for this layer specification }; -struct t_grid_def { - GridDefType grid_type = GridDefType::AUTO; //The type of this grid specification - - std::string name = ""; //The name of this device - - int width = -1; //Fixed device width (only valid for grid_type == FIXED) - int height = -1; //Fixed device height (only valid for grid_type == FIXED) - - float aspect_ratio = 1.; //Aspect ratio for auto-sized devices (only valid for - //grid_type == AUTO) - std::vector layers; -}; - struct t_vib_grid_def { GridDefType grid_type = GridDefType::AUTO; //The type of this grid specification @@ -438,6 +443,7 @@ struct t_vib_grid_def { std::vector layers; }; + /************************* POWER ***********************************/ /* Global clock architecture */ @@ -1639,7 +1645,16 @@ enum e_Fc_type { * For backward compatibility, this attribute is optional. If not * * specified, the resource type for the segment is considered to * * be GENERAL. * - * meta: Table storing extra arbitrary metadata attributes. */ + * meta: Table storing extra arbitrary metadata attributes. * + * + * + * New added parameters for bend wires: * + * isbend: This segment is bend or not * + * bend: The bend type of the segment, "-"-0, "U"-1, "D"-2 * + * For example: bend pattern <- - U ->; corresponding bend: [0,0,1,0] * + * part_len: Divide the segment into several parts based on bend position. * + * For example: length-5 bend segment: <- - U ->; * + * Corresponding part_len: [3,2] */ struct t_segment_inf { std::string name; int frequency; @@ -1656,7 +1671,7 @@ struct t_segment_inf { enum e_parallel_axis parallel_axis; std::vector cb; std::vector sb; - bool isbend; + bool isbend; std::vector bend; std::vector part_len; int seg_index; @@ -2044,48 +2059,9 @@ struct t_noc_inf { std::string noc_router_tile_name; }; -/* for vib tag */ -struct t_seg_group { - std::string name; - int seg_index; - int track_num; -}; - -enum e_multistage_mux_from_or_to_type { - PB = 0, - SEGMENT, - MUX -}; - -struct t_from_or_to_inf { - std::string type_name; - e_multistage_mux_from_or_to_type from_type; //from_or_to_type - int type_index = -1; - int phy_pin_index = -1; - char seg_dir = ' '; - int seg_index = -1; -}; - -struct t_first_stage_mux_inf { - std::string mux_name; - std::vector froms; -}; -struct t_second_stage_mux_inf : t_first_stage_mux_inf { - std::vector to; // for io type, port[pin] may map to several sinks -}; - -struct t_vib_inf { - std::string name; /* vib name */ - std::string pbtype_name; /* pbtype name of vib */ - int seg_group_num; /* seg group number of vib */ - int switch_idx; /* vib switch index */ - std::vector seg_groups; - std::vector first_stages; - std::vector second_stages; -}; -/* Detailed routing architecture */ +/* Detailed routing architecture */ struct t_arch { /** Stores unique strings used as key and values in tags, * i.e. implements a flyweight pattern to save memory.*/ @@ -2170,8 +2146,8 @@ struct t_arch { t_noc_inf* noc = nullptr; // added for vib - bool is_vib_arch = false; - std::vector vib_infs; + //bool is_vib_arch = false; + std::vector vib_infs; }; #endif From 9e521a04f80a6ff7606bdb51ca87228cf8252049 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:12:02 +0800 Subject: [PATCH 348/453] Update read_xml_arch_file.cpp --- libs/libarchfpga/src/read_xml_arch_file.cpp | 22 ++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index a912b2e2a2a..33880cacb44 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -5248,7 +5248,7 @@ static void ProcessVibArch(pugi::xml_node Parent, std::vectoris_vib_arch = true; + //arch->is_vib_arch = true; int num_vibs = count_children(Parent, "vib", loc_data); arch->vib_infs.reserve(num_vibs); Node = get_first_child(Parent, "vib", loc_data); @@ -5265,13 +5265,13 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vector segments = arch->Segments; t_arch_switch_inf* switches = arch->Switches; tmp = get_attribute(Vib_node, "name", loc_data).as_string(nullptr); if (tmp) { - vib.name = tmp; + vib.set_name(tmp); } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Vib_node), @@ -5280,21 +5280,21 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vectornum_switches; i_switch++) { if (!strcmp(tmp, switches[i_switch].name.c_str())) { - vib.switch_idx = i_switch; + vib.set_switch_idx(i_switch); break; } } @@ -5307,8 +5307,8 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vector Date: Tue, 22 Oct 2024 13:13:11 +0800 Subject: [PATCH 349/453] Update check_rr_graph.cpp --- libs/librrgraph/src/base/check_rr_graph.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 10f952e02b8..50e5679d44a 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -51,7 +51,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const std::vector& types, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const t_chan_width& chan_width, const t_graph_type graph_type, bool is_flat) { @@ -332,7 +332,7 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device void check_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const t_chan_width& chan_width, const enum e_route_type route_type, const int inode, @@ -389,7 +389,7 @@ void check_rr_node(const RRGraphView& rr_graph, /* Check that the segment is within the array and such. */ type = grid.get_physical_type({xlow, ylow, layer_num}); - const t_vib_inf* vib_type; + const VibInf* vib_type; if (vib_grid.dim_size(0) > 0) { vib_type = vib_grid[layer_num][xlow][ylow]; } @@ -455,7 +455,7 @@ void check_rr_node(const RRGraphView& rr_graph, int pin_max_ptc = get_tile_pin_max_ptc(type, is_flat); int medium_max_ptc = -1; if (vib_type) { - medium_max_ptc = (int)vib_type->first_stages.size(); + medium_max_ptc = (int)vib_type->get_first_stages().size(); } e_pin_type class_type = OPEN; int class_num_pins = -1; From 487ed26a4b13a73514513f572877fa8c02d7f3af Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:15:57 +0800 Subject: [PATCH 350/453] Update check_rr_graph.h --- libs/librrgraph/src/base/check_rr_graph.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.h b/libs/librrgraph/src/base/check_rr_graph.h index f4e5600d356..facdb6ea75c 100644 --- a/libs/librrgraph/src/base/check_rr_graph.h +++ b/libs/librrgraph/src/base/check_rr_graph.h @@ -9,7 +9,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const std::vector& types, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const t_chan_width& chan_width, const t_graph_type graph_type, bool is_flat); @@ -17,7 +17,7 @@ void check_rr_graph(const RRGraphView& rr_graph, void check_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const t_chan_width& chan_width, const enum e_route_type route_type, const int inode, From 6382aaf7f231f8b7e9519071f88482265ccfa2ed Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:16:53 +0800 Subject: [PATCH 351/453] Update rr_graph_uxsdcxx_serializer.h --- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 7e3964ad6c5..a28750345ba 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1827,7 +1827,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { read_rr_graph_filename_->assign(read_rr_graph_name_); if (do_check_rr_graph_) { - const vtr::NdMatrix vib_grid_; + const vtr::NdMatrix vib_grid_; check_rr_graph(*rr_graph_, physical_tile_types_, *rr_indexed_data_, From bb2d5cf46b096a9bb09c1b09c12934f3f56dd704 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:18:14 +0800 Subject: [PATCH 352/453] Update SetupGrid.cpp --- vpr/src/base/SetupGrid.cpp | 52 +++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index f0e827a898a..d1d6c7633c9 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -33,7 +33,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); static bool grid_satisfies_instance_counts(const DeviceGrid& grid, const std::map& instance_counts, float maximum_utilization); static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, const std::vector& limiting_resources = std::vector()); -static vtr::NdMatrix build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range = true); +static vtr::NdMatrix build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range = true); static void CheckGrid(const DeviceGrid& grid); @@ -47,11 +47,11 @@ static void set_grid_block_type(int priority, const t_metadata_dict* meta); static void set_vib_grid_block_type(int priority, - const t_vib_inf* type, + const VibInf* type, int layer_num, size_t x_root, size_t y_root, - vtr::NdMatrix& vib_grid, + vtr::NdMatrix& vib_grid, vtr::NdMatrix& grid_priorities, const t_metadata_dict* meta); @@ -148,7 +148,7 @@ DeviceGrid create_device_grid(const std::string& layout_name, const std::vector< } } -vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts) { +vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts) { if (layout_name == "auto") { //We do not support auto layout now // @@ -591,7 +591,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt } ///@brief Build the specified device grid -static vtr::NdMatrix build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range) { +static vtr::NdMatrix build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range) { if (grid_def.grid_type == GridDefType::FIXED) { if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, @@ -603,7 +603,7 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid auto& device_ctx = g_vpr_ctx.device(); //Initialize the grid and each location priority based on available dies in the architecture file - vtr::NdMatrix vib_grid; + vtr::NdMatrix vib_grid; vtr::NdMatrix grid_priorities; int num_layers = (int)grid_def.layers.size(); vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); @@ -613,7 +613,7 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid grid_priorities.resize(std::array{(size_t)num_layers, grid_width, grid_height}, std::numeric_limits::lowest()); //Initialize the device to all empty blocks - const t_vib_inf* empty_type = nullptr; + const VibInf* empty_type = nullptr; //VTR_ASSERT(empty_type != nullptr); for (int layer = 0; layer < num_layers; ++layer) { for (size_t x = 0; x < grid_width; ++x) { @@ -628,14 +628,14 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid } FormulaParser p; - std::set seen_types; + std::set seen_types; for (int layer = 0; layer < num_layers; layer++) { for (const auto& grid_loc_def : grid_def.layers.at(layer).loc_defs) { //Fill in the block types according to the specification //auto type = find_tile_type_by_name(grid_loc_def.block_type, device_ctx.physical_tile_types); - const t_vib_inf* type = nullptr; + const VibInf* type = nullptr; for (size_t vib_type = 0; vib_type < device_ctx.arch->vib_infs.size(); vib_type++) { - if (grid_loc_def.block_type == device_ctx.arch->vib_infs[vib_type].name) { + if (grid_loc_def.block_type == device_ctx.arch->vib_infs[vib_type].get_name()) { type = &device_ctx.arch->vib_infs[vib_type]; break; } @@ -686,7 +686,7 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid if (startx > grid_width - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", - type->name, xspec.start_expr.c_str(), startx, 0, grid_width - 1); + type->get_name(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); } continue; //No instances will be created } @@ -694,7 +694,7 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid if (starty > grid_height - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", - type->name, yspec.start_expr.c_str(), starty, 0, grid_height - 1); + type->get_name(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); } continue; //No instances will be created } @@ -703,14 +703,14 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid if (endx > grid_width - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", - type->name, xspec.end_expr.c_str(), endx, 0, grid_width - 1); + type->get_name(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); } } if (endy > grid_height - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", - type->name, yspec.end_expr.c_str(), endy, 0, grid_height - 1); + type->get_name(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); } } @@ -718,13 +718,13 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid if (endx < startx) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", - xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->name); + xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->get_name()); } if (endy < starty) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", - yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->name); + yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->get_name()); } //The minimum increment is the block dimension @@ -733,7 +733,7 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incrx for block type '%s' must be at least" " block width (%d) to avoid overlapping instances (was %s = %d)", - type->name, 1, xspec.incr_expr.c_str(), incrx); + type->get_name(), 1, xspec.incr_expr.c_str(), incrx); } //VTR_ASSERT(type->height > 0); @@ -741,7 +741,7 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incry for block type '%s' must be at least" " block height (%d) to avoid overlapping instances (was %s = %d)", - type->name, 1, yspec.incr_expr.c_str(), incry); + type->get_name(), 1, yspec.incr_expr.c_str(), incry); } //The minimum repeat is the region dimension @@ -750,7 +750,7 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification repeatx for block type '%s' must be at least" " the region width (%d) to avoid overlapping instances (was %s = %d)", - type->name, region_width, xspec.repeat_expr.c_str(), repeatx); + type->get_name(), region_width, xspec.repeat_expr.c_str(), repeatx); } size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive @@ -758,7 +758,7 @@ static vtr::NdMatrix build_vib_device_grid(const t_vib_grid VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification repeaty for block type '%s' must be at least" " the region height (%d) to avoid overlapping instances (was %s = %d)", - type->name, region_height, xspec.repeat_expr.c_str(), repeaty); + type->get_name(), region_height, xspec.repeat_expr.c_str(), repeaty); } //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", @@ -952,22 +952,22 @@ static void set_grid_block_type(int priority, } static void set_vib_grid_block_type(int priority, - const t_vib_inf* type, + const VibInf* type, int layer_num, size_t x_root, size_t y_root, - vtr::NdMatrix& vib_grid, + vtr::NdMatrix& vib_grid, vtr::NdMatrix& grid_priorities, const t_metadata_dict* meta) { struct TypeLocation { - TypeLocation(size_t x_val, size_t y_val, const t_vib_inf* type_val, int priority_val) + TypeLocation(size_t x_val, size_t y_val, const VibInf* type_val, int priority_val) : x(x_val) , y(y_val) , type(type_val) , priority(priority_val) {} size_t x; size_t y; - const t_vib_inf* type; + const VibInf* type; int priority; bool operator<(const TypeLocation& rhs) const { @@ -1012,8 +1012,8 @@ static void set_vib_grid_block_type(int priority, " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." " The last specification will apply.\n", x_root, y_root, - max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, - priority, type->name); + max_priority_type_loc.type->get_name(), max_priority_type_loc.x, max_priority_type_loc.y, + priority, type->get_name()); } //Mark all the grid tiles 'covered' by this block with the appropriate type From b3bb7c8f7310d03ef61da40af61f824ddf475cc1 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:18:44 +0800 Subject: [PATCH 353/453] Update SetupGrid.h --- vpr/src/base/SetupGrid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 2f3ab6bc1b1..d9be152263a 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -22,7 +22,7 @@ DeviceGrid create_device_grid(const std::string& layout_name, ///@brief Find the device close in size to the specified dimensions DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); -vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts); +vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts); /** * @brief Calculate the device utilization From 5b27ab8452b538558cea6395e7361d022840bf0d Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:19:31 +0800 Subject: [PATCH 354/453] Update vpr_api.cpp --- vpr/src/base/vpr_api.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 9129c820d80..dd8c3df3415 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -457,7 +457,7 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { //Build the device float target_device_utilization = vpr_setup.PackerOpts.target_device_utilization; device_ctx.grid = create_device_grid(vpr_setup.device_layout, Arch.grid_layouts, num_type_instances, target_device_utilization); - if (Arch.is_vib_arch) { + if (!Arch.vib_infs.empty()) { device_ctx.vib_grid = create_vib_device_grid(vpr_setup.device_layout, Arch.vib_grid_layouts); } From 345a27c04258b4220f4de021f9cc6d1a61cb2787 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:20:04 +0800 Subject: [PATCH 355/453] Update vpr_context.h --- vpr/src/base/vpr_context.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index bb0147913ee..ec4fc150483 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -161,7 +161,7 @@ struct DeviceContext : public Context { */ DeviceGrid grid; - vtr::NdMatrix vib_grid; + vtr::NdMatrix vib_grid; /* * Empty types From eeb448ad43201e0b3adcb4f6f94e07f2cdeffe74 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:20:55 +0800 Subject: [PATCH 356/453] Update connection_router.cpp --- vpr/src/route/connection_router.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index b608f0381c0..40b0baa2bd2 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -1073,8 +1073,8 @@ static inline void update_router_stats(RouterStats* router_stats, VTR_ASSERT(node_type != NUM_RR_TYPES); - const t_vib_inf* vib; - if (device_ctx.arch->is_vib_arch) { + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid[rr_graph->node_layer(rr_node_id)][rr_graph->node_xlow(rr_node_id)][rr_graph->node_ylow(rr_node_id)]; } else { From 0d7cacd0ab7938d7c9118a6c6fac51d9a2a5f7bd Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:21:41 +0800 Subject: [PATCH 357/453] Update overuse_report.cpp --- vpr/src/route/overuse_report.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 78a846752aa..5c308fcdc2d 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -220,8 +220,8 @@ static void report_overused_ipin_opin(std::ostream& os, "Non-track RR node should not span across multiple grid blocks."); t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({grid_x, grid_y, grid_layer}); - const t_vib_inf* vib; - if (device_ctx.arch->is_vib_arch) { + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid[grid_layer][grid_x][grid_y]; } else { From 6f773cd490de3bab4613b8f2a8e95920d3131070 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:22:33 +0800 Subject: [PATCH 358/453] Update router_lookahead_map_utils.cpp --- vpr/src/route/router_lookahead_map_utils.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index b337e842d52..93757daf325 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -420,8 +420,8 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { const std::vector& rr_nodes_at_loc = device_ctx.rr_graph.node_lookup().find_grid_nodes_at_all_sides(sample_loc.layer_num, sample_loc.x, sample_loc.y, rr_type); for (RRNodeId node_id : rr_nodes_at_loc) { int ptc = rr_graph.node_ptc_num(node_id); - const t_vib_inf* vib; - if (device_ctx.arch->is_vib_arch) { + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid[sample_loc.layer_num][sample_loc.x][sample_loc.y]; } else { @@ -1040,8 +1040,8 @@ static void dijkstra_flood_to_wires(int itile, t_physical_tile_type_ptr physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(next_node), rr_graph.node_ylow(next_node), rr_graph.node_layer(next_node)}); - const t_vib_inf* vib; - if (device_ctx.arch->is_vib_arch) { + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid[rr_graph.node_layer(next_node)][rr_graph.node_xlow(next_node)][rr_graph.node_ylow(next_node)]; } else { @@ -1412,8 +1412,8 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, t_physical_tile_type_ptr physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(child_node), rr_graph.node_ylow(child_node), rr_graph.node_layer(child_node)}); - const t_vib_inf* vib; - if (device_ctx.arch->is_vib_arch) { + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid[rr_graph.node_layer(child_node)][rr_graph.node_xlow(child_node)][rr_graph.node_ylow(child_node)]; } else { From f7427aae6007229a1627036c69180e3dfa53581e Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:23:07 +0800 Subject: [PATCH 359/453] Update router_lookahead_map.cpp --- vpr/src/route/router_lookahead_map.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index ff7da4bc136..f5446c71f5f 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -204,8 +204,8 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI t_physical_tile_type_ptr from_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node), rr_graph.node_layer(current_node)}); - const t_vib_inf* vib; - if (device_ctx.arch->is_vib_arch) { + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; } else { From d91bd9f8c2d99dc004fe6f82343daa62a2860d49 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:23:59 +0800 Subject: [PATCH 360/453] Update rr_graph.cpp --- vpr/src/route/rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 9c607d4def4..82fc658dcaf 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1401,7 +1401,7 @@ static void build_rr_graph(const t_graph_type graph_type, rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); - const vtr::NdMatrix vib_grid; + const vtr::NdMatrix vib_grid; check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, @@ -1495,7 +1495,7 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, rr_graph_builder.clear_temp_storage(); - const vtr::NdMatrix vib_grid; + const vtr::NdMatrix vib_grid; check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, From ce412a4e05d2b88532c9d069916b63f7cbc1dda8 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:25:18 +0800 Subject: [PATCH 361/453] Update tileable_rr_graph_builder.cpp --- vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 7cf188cb6cc..ae8d3102777 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -158,7 +158,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* Get vib grid */ const auto& vib_grid = device_ctx.vib_grid; - const bool is_vib_arch = device_ctx.arch->is_vib_arch; + const bool is_vib_arch = !device_ctx.arch->vib_infs.empty(); /************************ * Allocate the rr_nodes From d0f19a0b298807b002e86849650f894228087f64 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:26:09 +0800 Subject: [PATCH 362/453] Update tileable_rr_graph_edge_builder.cpp --- .../tileable_rr_graph_edge_builder.cpp | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 01cf950e313..e77a3b5339a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -105,7 +105,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, @@ -137,8 +137,8 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, for (size_t iy = 0; iy < vib_grid.dim_size(2); iy++) { std::map mux_name_map; - for (size_t i_mux = 0; i_mux < vib_grid[i_layer][ix][iy]->first_stages.size(); i_mux++) { - mux_name_map.emplace(vib_grid[i_layer][ix][iy]->first_stages[i_mux].mux_name, i_mux); + for (size_t i_mux = 0; i_mux < vib_grid[i_layer][ix][iy]->get_first_stages().size(); i_mux++) { + mux_name_map.emplace(vib_grid[i_layer][ix][iy]->get_first_stages()[i_mux].mux_name, i_mux); } medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; } @@ -153,7 +153,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); - vtr::Point gsb_range(grids.width() - 1, grids.height() - 1); + vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); /* Go Switch Block by Switch Block */ for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { @@ -209,15 +209,15 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, if (is_vib_arch) { size_t ix, iy; // process top boundary - iy = grids.height() - 1; - for (ix = 0; ix < grids.width() - 1; ++ix) { + iy = gsb_range.y() + 1; // == grids.height() - 1 + for (ix = 0; ix < gsb_range.x() + 1; ++ix) { vtr::Point actual_coord(ix, iy); vtr::Point gsb_coord(ix, iy - 1); /* Create a GSB object */ const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, device_chan_width, segment_inf_x, segment_inf_y, - layer, gsb_coord); + layer, gsb_coord, perimeter_cb); t_vib_map vib_map; @@ -236,15 +236,15 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, } // process right boundary - ix = grids.width() - 1; - for (iy = 0; iy < grids.height() - 1; ++iy) { + ix = gsb_range.x() + 1; + for (iy = 0; iy < gsb_range.y() + 1; ++iy) { vtr::Point actual_coord(ix, iy); vtr::Point gsb_coord(ix - 1, iy); /* Create a GSB object */ const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, device_chan_width, segment_inf_x, segment_inf_y, - layer, gsb_coord); + layer, gsb_coord, perimeter_cb); t_vib_map vib_map; @@ -263,8 +263,8 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, } // process right-top corner - ix = grids.width() - 1; - iy = grids.height() - 1; + ix = gsb_range.x() + 1; + iy = gsb_range.y() + 1; vtr::Point actual_coord(ix, iy); vtr::Point gsb_coord(ix - 1, iy - 1); @@ -272,7 +272,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, /* Create a GSB object */ const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, device_chan_width, segment_inf_x, segment_inf_y, - layer, gsb_coord); + layer, gsb_coord, perimeter_cb); t_vib_map vib_map; From f117218628ead691fde535ad47617579489e1cfb Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:26:40 +0800 Subject: [PATCH 363/453] Update tileable_rr_graph_edge_builder.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index e42f585b9a7..0aa3b5a0310 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -25,7 +25,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, From 0e0c9af6bd9a998d25817bb6ab231bf617d5e391 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:27:08 +0800 Subject: [PATCH 364/453] Update tileable_rr_graph_gsb.cpp --- .../tileable_rr_graph_gsb.cpp | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index b701bea23a7..02fbda0d83a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1721,7 +1721,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, /* Vib edge builder */ t_vib_map build_vib_map(const RRGraphView& rr_graph, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const RRGSB& rr_gsb, const std::vector& segment_inf, const size_t& layer, @@ -1732,10 +1732,10 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, t_vib_map vib_map; - const t_vib_inf* vib = vib_grid[layer][actual_coordinate.x()][actual_coordinate.y()]; + const VibInf* vib = vib_grid[layer][actual_coordinate.x()][actual_coordinate.y()]; auto phy_type = grids.get_physical_type({(int)actual_coordinate.x(), (int)actual_coordinate.y(), (int)layer}); - VTR_ASSERT(!strcmp(vib->pbtype_name.c_str(), phy_type->name)); - const std::vector first_stages = vib->first_stages; + VTR_ASSERT(!strcmp(vib->get_pbtype_name().c_str(), phy_type->name)); + const std::vector first_stages = vib->get_first_stages(); for (size_t i_first_stage = 0; i_first_stage < first_stages.size(); i_first_stage++) { std::vector froms = first_stages[i_first_stage].froms; RRNodeId to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, i_first_stage); @@ -1744,7 +1744,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, RRNodeId from_node; if (from.from_type == PB) { - if (from.type_name != vib->pbtype_name) { + if (from.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type name!\n"); exit(1); @@ -1767,7 +1767,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, t_segment_inf segment = segment_inf[from.type_index]; VTR_ASSERT(segment.name == from.type_name); t_seg_group seg_group; - for (auto seg : vib->seg_groups) { + for (auto seg : vib->get_seg_groups()) { if (seg.name == segment.name) { seg_group = seg; break; @@ -1829,7 +1829,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } } /* Second stages*/ - const std::vector second_stages = vib->second_stages; + const std::vector second_stages = vib->get_second_stages(); for (size_t i_second_stage = 0; i_second_stage < second_stages.size(); i_second_stage++) { std::vector froms = second_stages[i_second_stage].froms; std::vector tos = second_stages[i_second_stage].to; @@ -1839,7 +1839,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, RRNodeId to_node; if (to.from_type == PB) { - if (to.type_name != vib->pbtype_name) { + if (to.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong to type name!\n"); exit(1); @@ -1862,7 +1862,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, t_segment_inf segment = segment_inf[to.type_index]; VTR_ASSERT(segment.name == to.type_name); t_seg_group seg_group; - for (auto seg : vib->seg_groups) { + for (auto seg : vib->get_seg_groups()) { if (seg.name == segment.name) { seg_group = seg; break; @@ -1917,7 +1917,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, RRNodeId from_node; if (from.from_type == PB) { - if (from.type_name != vib->pbtype_name) { + if (from.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type name!\n"); exit(1); @@ -1940,7 +1940,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, t_segment_inf segment = segment_inf[from.type_index]; VTR_ASSERT(segment.name == from.type_name); t_seg_group seg_group; - for (auto seg : vib->seg_groups) { + for (auto seg : vib->get_seg_groups()) { if (seg.name == segment.name) { seg_group = seg; break; From 9b8a3f22a964da3c45357337026879ea8e66472a Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:27:30 +0800 Subject: [PATCH 365/453] Update tileable_rr_graph_gsb.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index adb33f921d3..67bea11d5d5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -94,7 +94,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, t_vib_map build_vib_map(const RRGraphView& rr_graph, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const RRGSB& rr_gsb, const std::vector& segment_inf, const size_t& layer, From ca9e9f1b0eb1b2d922983b4c2119e16ea332d598 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:27:59 +0800 Subject: [PATCH 366/453] Update tileable_rr_graph_node_builder.cpp --- .../tileable_rr_graph_node_builder.cpp | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 458ce1a3d78..710f6824ac0 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -82,7 +82,7 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, } static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer) { size_t num_grid_rr_nodes = 0; @@ -90,7 +90,7 @@ static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { - const t_vib_inf* vib = vib_grid[layer][ix][iy]; + const VibInf* vib = vib_grid[layer][ix][iy]; if (vib == nullptr) { VTR_LOGF_ERROR(__FILE__, __LINE__, "VIB at (%d, %d) is EMPTY!\n", ix, iy); @@ -99,8 +99,8 @@ static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, } size_t count = 0; - for (size_t i_first_stage = 0; i_first_stage < vib->first_stages.size(); i_first_stage++) { - auto first_stage = vib->first_stages[i_first_stage]; + for (size_t i_first_stage = 0; i_first_stage < vib->get_first_stages().size(); i_first_stage++) { + auto first_stage = vib->get_first_stages()[i_first_stage]; if (first_stage.froms.size() == 0) { VTR_LOGF_ERROR(__FILE__, __LINE__, "VIB first stage '%s' at (%d, %d) has no from!\n", first_stage.mux_name, ix, iy); @@ -109,7 +109,7 @@ static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, count++; } - VTR_ASSERT(count == vib->first_stages.size()); + VTR_ASSERT(count == vib->get_first_stages().size()); num_grid_rr_nodes += count; } } @@ -363,7 +363,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, @@ -434,7 +434,7 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, @@ -689,10 +689,10 @@ static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_build std::vector& rr_rc_data, const size_t& layer, const vtr::Point& grid_coordinate, - const vtr::NdMatrix& vib_grid) { + const vtr::NdMatrix& vib_grid) { - const t_vib_inf* vib = vib_grid[layer][grid_coordinate.x()][grid_coordinate.y()]; - size_t num_medium_nodes = vib->first_stages.size(); + const VibInf* vib = vib_grid[layer][grid_coordinate.x()][grid_coordinate.y()]; + size_t num_medium_nodes = vib->get_first_stages().size(); for (size_t i_medium = 0; i_medium < num_medium_nodes; i_medium++) { /* Create a new node and fill information */ RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), MEDIUM, i_medium, SIDES[0]); @@ -711,7 +711,7 @@ static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_build rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(MEDIUM_COST_INDEX)); /* Switch info */ - rr_node_driver_switches[node] = RRSwitchId(vib->switch_idx); + rr_node_driver_switches[node] = RRSwitchId(vib->get_switch_idx()); /* RC data */ rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); @@ -726,11 +726,11 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, - const bool& perimeter_cb + const bool& perimeter_cb, const bool& is_vib_arch) { for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { @@ -809,10 +809,10 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, for (size_t ix = 0; ix < grids.width(); ++ix) { t_physical_tile_loc tile_loc(ix, iy, layer); - VTR_ASSERT(vib_grid[layer][ix][iy]->pbtype_name == grids.get_physical_type(tile_loc)->name); + VTR_ASSERT(vib_grid[layer][ix][iy]->get_pbtype_name() == grids.get_physical_type(tile_loc)->name); vtr::Point grid_coordinate(ix, iy); - rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, MEDIUM, vib_grid[layer][ix][iy]->first_stages.size(), SIDES[0]); + rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, MEDIUM, vib_grid[layer][ix][iy]->get_first_stages().size(), SIDES[0]); load_one_grid_medium_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, @@ -1299,7 +1299,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, std::map>& rr_node_track_ids, std::vector& rr_rc_data, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, From 3f5633b1b7fd7c0fa7b293e94a158ef142d367b2 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:54:14 +0800 Subject: [PATCH 367/453] Update tileable_rr_graph_node_builder.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 8776562b2e9..b40bec09273 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -25,7 +25,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& driver_switches, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, @@ -42,7 +42,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, std::map>& rr_node_track_ids, std::vector& rr_rc_data, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const vtr::NdMatrix& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, From 317e2fe579b1fb7557b3e8dfe955bc49be9fce28 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:57:59 +0800 Subject: [PATCH 368/453] Update vpr_utils.cpp --- vpr/src/util/vpr_utils.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 4d6cb831b65..3e6237b5096 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2255,15 +2255,15 @@ std::vector get_all_pb_graph_node_primitives(const t_pb_ } bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, - const t_vib_inf* vib, + const VibInf* vib, t_rr_type node_type, int node_ptc) { if (node_type == CHANX || node_type == CHANY) { return true; - } else if (node_type == MEDIUM) { + } else if (node_type == MEDIUM) { // This function will check all types of nodes. MEDIUM is added for avoiding errors. VTR_ASSERT(vib != nullptr); - return (node_ptc < (int)vib->first_stages.size()); + return (node_ptc < (int)vib->get_first_stages().size()); } else { VTR_ASSERT(node_type == IPIN || node_type == OPIN || node_type == SINK || node_type == SOURCE); if (node_type == IPIN || node_type == OPIN) { From 4b91e0244ad157674e32ba3e79552072c9820677 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:58:32 +0800 Subject: [PATCH 369/453] Update vpr_utils.h --- vpr/src/util/vpr_utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 27d8bc81e2b..0eec7f7d63a 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -256,7 +256,7 @@ void print_timing_stats(const std::string& name, std::vector get_all_pb_graph_node_primitives(const t_pb_graph_node* pb_graph_node); bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, - const t_vib_inf* vib, + const VibInf* vib, t_rr_type node_type, int node_ptc); From 0f3445526220e5244c95fac7f39bdaec587b96b2 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 22 Oct 2024 13:59:10 +0800 Subject: [PATCH 370/453] Update tileable_chan_details_builder.cpp --- .../tileable_chan_details_builder.cpp | 24 ++++++++++++------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index 78c88043156..c1334d81d96 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -179,7 +179,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, /* Add node to ChanNodeDetails */ size_t cur_track = 0; - size_t bend_num = 0; + size_t bend_num = 0; // The index for bend segments for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { if (!segment_inf[iseg].isbend){ /* segment length will be set to maxium segment length if this is a longwire */ @@ -209,14 +209,17 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, cur_track++; } } - else{ + else{ // bend segment bend_num++; VTR_ASSERT(segment_inf[iseg].isbend); std::vector seg_len = segment_inf[iseg].part_len; std::vector bend = segment_inf[iseg].bend; - VTR_ASSERT(seg_len.size() == 2); + VTR_ASSERT(seg_len.size() == 2); // Only support one bend position for a segment. std::vector num_tracks_bend; + /* Each bend part tracks number * + * For example, a length-5 segment with bend pattern: <- - U -> has 20 tracks. * + * Its num_tracks_bend is [20 * 3/5, 20 * 2/5] = [12, 8] */ for(size_t i = 0; i < seg_len.size(); i++) num_tracks_bend.push_back(num_tracks[iseg] * seg_len[i] / segment_inf[iseg].length); @@ -225,23 +228,26 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { bool seg_start = false; bool seg_end = false; - size_t seg_bend_start = 0; - size_t seg_bend_end = 0; - + size_t seg_bend_start = 0; // seg_bend_start = 0 means not a bend start. + // seg_bend_start = i (i > 0) means a bend start for bend segment i. + size_t seg_bend_end = 0; // The same as seg_bend_start. + // Tracks has same seg_bend_start and seg_bend_end values will be + // connected by a delayless switch. + /* Every first track of a group of Length-N wires, we set a starting point */ if (0 == itrack % segment_inf[iseg].length) { seg_start = true; } - + /* Number seg_len[0] track of a group of Length-N wires, we set a bend start point */ if (seg_len[0] == int(itrack) % segment_inf[iseg].length) { seg_start = true; seg_bend_start = bend_num; } - + /* Number seg_len[0] - 1 track of a group of Length-N wires, we set a bend end point */ if (seg_len[0] - 1 == int(itrack) % segment_inf[iseg].length) { seg_end = true; seg_bend_end = bend_num; } - + /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ if ((segment_inf[iseg].length - 1 == int(itrack) % segment_inf[iseg].length) || (itrack == num_tracks[iseg] - 1)) { seg_end = true; From 3a3f24e9b450dd351b56231e342682ce5c3b163f Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:28:07 +0800 Subject: [PATCH 371/453] Update tileable_rr_graph_gsb.cpp --- .../tileable_rr_graph_gsb.cpp | 43 ++++++++++++++++--- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 3992e8d54f3..d4bf448796c 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1162,6 +1162,33 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, temp_ipin_rr_nodes.clear(); } + /* Find all MEDIUM rr_nodes */ + std::vector medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y(), MEDIUM); + for (auto medium_rr_node : medium_rr_nodes) { + rr_gsb.add_medium_node(medium_rr_node); + } + /* For TOP and RIGHT borders, we need to add extra medium nodes. */ + if (gsb_coordinate.y() == grids.height() - 2) { + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, MEDIUM); + for (auto medium_rr_node : extra_medium_rr_nodes) { + rr_gsb.add_medium_node(medium_rr_node); + } + } + + if (gsb_coordinate.x() == grids.width() - 2) { + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), MEDIUM); + for (auto medium_rr_node : extra_medium_rr_nodes) { + rr_gsb.add_medium_node(medium_rr_node); + } + } + + if ((gsb_coordinate.x() == grids.width() - 2) && (gsb_coordinate.y() == grids.height() - 2)) { + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, MEDIUM); + for (auto medium_rr_node : extra_medium_rr_nodes) { + rr_gsb.add_medium_node(medium_rr_node); + } + } + return rr_gsb; } @@ -1721,7 +1748,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, /* Vib edge builder */ t_vib_map build_vib_map(const RRGraphView& rr_graph, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const RRGSB& rr_gsb, const std::vector& segment_inf, const size_t& layer, @@ -1732,7 +1759,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, t_vib_map vib_map; - const VibInf* vib = vib_grid[layer][actual_coordinate.x()][actual_coordinate.y()]; + const VibInf* vib = vib_grid.get_vib(layer, actual_coordinate.x(), actual_coordinate.y()); auto phy_type = grids.get_physical_type({(int)actual_coordinate.x(), (int)actual_coordinate.y(), (int)layer}); VTR_ASSERT(!strcmp(vib->get_pbtype_name().c_str(), phy_type->name)); const std::vector first_stages = vib->get_first_stages(); @@ -1740,6 +1767,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, std::vector froms = first_stages[i_first_stage].froms; RRNodeId to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, i_first_stage); VTR_ASSERT(to_node.is_valid()); + VTR_ASSERT(rr_gsb.is_medium_node(to_node)); for (auto from : froms) { RRNodeId from_node; if (from.from_type == PB) { @@ -1750,7 +1778,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, exit(1); } - for (e_side side : SIDES) { + for (e_side side : TOTAL_2D_SIDES) { from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); if (from_node.is_valid()) break; @@ -1799,6 +1827,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } from_node = rr_gsb.get_chan_node(side, track_list[seg_id]); VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + VTR_ASSERT(rr_gsb.is_chan_node(from_node)); } @@ -1806,6 +1835,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, else if (from.from_type == MUX) { size_t from_mux_index = medium_mux_name2medium_index[layer][actual_coordinate.x()][actual_coordinate.y()][from.type_name]; from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + VTR_ASSERT(rr_gsb.is_medium_node(from_node)); } else { VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -1845,7 +1875,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, exit(1); } - for (e_side side : SIDES) { + for (e_side side : TOTAL_2D_SIDES) { to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), IPIN, to.phy_pin_index, side); if (to_node.is_valid()) break; @@ -1897,6 +1927,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, VTR_ASSERT(track_status == TRACK_START); to_node = rr_gsb.get_chan_node(side, track_list[seg_id]); VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + VTR_ASSERT(rr_gsb.is_chan_node(to_node)); } @@ -1923,7 +1954,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, exit(1); } - for (e_side side : SIDES) { + for (e_side side : TOTAL_2D_SIDES) { from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); if (from_node.is_valid()) break; @@ -1972,6 +2003,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } from_node = rr_gsb.get_chan_node(side, track_list[seg_id]); VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + VTR_ASSERT(rr_gsb.is_chan_node(from_node)); } @@ -1979,6 +2011,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, else if (from.from_type == MUX) { size_t from_mux_index = medium_mux_name2medium_index[layer][actual_coordinate.x()][actual_coordinate.y()][from.type_name]; from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + VTR_ASSERT(rr_gsb.is_medium_node(from_node)); } else { VTR_LOGF_ERROR(__FILE__, __LINE__, From a75725438de9633b6cc0d187d1b05b8c7c41e858 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:29:05 +0800 Subject: [PATCH 372/453] Update rr_spatial_lookup.cpp --- libs/librrgraph/src/base/rr_spatial_lookup.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 12c0d9394ea..474a90935a9 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -218,14 +218,14 @@ std::vector RRSpatialLookup::find_grid_nodes_at_all_sides(int layer, t_rr_type rr_type) const { VTR_ASSERT(rr_type == SOURCE || rr_type == OPIN || rr_type == IPIN || rr_type == SINK || rr_type == MEDIUM); if (rr_type == SOURCE || rr_type == SINK || rr_type == MEDIUM) { - return find_nodes(layer,x, y, rr_type); + return find_nodes(layer, x, y, rr_type); } std::vector nodes; /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; for (e_side node_side : TOTAL_2D_SIDES) { - num_nodes += find_nodes(layer,x, y, rr_type, node_side).size(); + num_nodes += find_nodes(layer, x, y, rr_type, node_side).size(); } nodes.reserve(num_nodes); From b447186753f746ad90bde5dfd19bcf79485102b5 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:29:47 +0800 Subject: [PATCH 373/453] Update rr_gsb.cpp --- vpr/src/tileable_rr_graph/rr_gsb.cpp | 66 ++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 64401b7d5e2..36663b21e2a 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -27,6 +27,8 @@ RRGSB::RRGSB() { ipin_node_.clear(); opin_node_.clear(); + + medium_node_.clear(); for (size_t icb_type = 0; icb_type < 2; icb_type++) { for (size_t iside = 0; iside < NUM_2D_SIDES; iside++) { cb_opin_node_[icb_type][iside].clear(); @@ -310,6 +312,18 @@ RRNodeId RRGSB::get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, c return cb_opin_node_[icb_type][side_manager.to_size_t()][node_id]; } +/* Get the number of MEDIUM rr_nodes */ +size_t RRGSB::get_num_medium_nodes() const { + VTR_ASSERT(!medium_node_.empty()); + return medium_node_.size(); +} + +/* get a rr_node at a given ptc number */ +RRNodeId RRGSB::get_medium_node(const size_t& ptc) const { + VTR_ASSERT(!medium_node_.empty() && medium_node_.size() > ptc); + return medium_node_[ptc]; +} + /* Get the node index of a routing track of a connection block, return -1 if not found */ int RRGSB::get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const { enum e_side chan_side = get_cb_chan_side(cb_type); @@ -429,6 +443,52 @@ bool RRGSB::is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, return (-1 != index); } +bool RRGSB::is_opin_node(const RRNodeId& node) const { + std::vector sides = {TOP, RIGHT, BOTTOM, LEFT}; + for (e_side side : sides) { + for (auto opin_node : opin_node_[side]) { + if (node == opin_node) { + return true; + } + } + } + return false; +} + +bool RRGSB::is_ipin_node(const RRNodeId& node) const { + std::vector sides = {TOP, RIGHT, BOTTOM, LEFT}; + for (e_side side : sides) { + for (auto ipin_node : ipin_node_[side]) { + if (node == ipin_node) { + return true; + } + } + } + return false; +} + +bool RRGSB::is_medium_node(const RRNodeId& node) const { + for (auto medium_node : medium_node_) { + if (node == medium_node) { + return true; + } + } + return false; +} + +bool RRGSB::is_chan_node(const RRNodeId& node) const { + std::vector sides = {TOP, RIGHT, BOTTOM, LEFT}; + for (e_side side : sides) { + RRChan rr_chan = chan_node_[side]; + for (size_t inode = 0; inode < rr_chan.get_chan_width(); ++inode) { + if (node == rr_chan.get_node(inode)) { + return true; + } + } + } + return false; +} + /* check if the CB exist in this GSB */ bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const { /* if channel width is zero, there is no CB */ @@ -767,6 +827,12 @@ void RRGSB::add_opin_node(const RRNodeId& node, const e_side& node_side) { opin_node_[size_t(node_side)].push_back(node); } +/* Add a node to the medium_node_ */ +void RRGSB::add_medium_node(const RRNodeId& medium_node) { + /* push pack the dedicated element in the vector */ + medium_node_.push_back(medium_node); +} + void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, const e_side& chan_side, const size_t& track_id) { From 35b42009b89fc3c3bb67883418ce8ec107ede449 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:30:17 +0800 Subject: [PATCH 374/453] Update tileable_rr_graph_gsb.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 67bea11d5d5..0e94622cc97 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -94,7 +94,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, t_vib_map build_vib_map(const RRGraphView& rr_graph, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const RRGSB& rr_gsb, const std::vector& segment_inf, const size_t& layer, From d5d2372e2b1ae19829f4a95a5598cf54623ca7e1 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:30:54 +0800 Subject: [PATCH 375/453] Update tileable_rr_graph_node_builder.cpp --- .../tileable_rr_graph_node_builder.cpp | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index b1bd7101e01..be325cfe352 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -82,15 +82,15 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, } static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer) { size_t num_grid_rr_nodes = 0; - VTR_ASSERT(grids.width() == vib_grid.dim_size(1) && grids.height() == vib_grid.dim_size(2)); + VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { - const VibInf* vib = vib_grid[layer][ix][iy]; + const VibInf* vib = vib_grid.get_vib(layer, ix, iy); if (vib == nullptr) { VTR_LOGF_ERROR(__FILE__, __LINE__, "VIB at (%d, %d) is EMPTY!\n", ix, iy); @@ -363,7 +363,7 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, @@ -434,7 +434,7 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, @@ -689,13 +689,13 @@ static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_build std::vector& rr_rc_data, const size_t& layer, const vtr::Point& grid_coordinate, - const vtr::NdMatrix& vib_grid) { + const VibDeviceGrid& vib_grid) { - const VibInf* vib = vib_grid[layer][grid_coordinate.x()][grid_coordinate.y()]; + const VibInf* vib = vib_grid.get_vib(layer, grid_coordinate.x(), grid_coordinate.y()); size_t num_medium_nodes = vib->get_first_stages().size(); for (size_t i_medium = 0; i_medium < num_medium_nodes; i_medium++) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), MEDIUM, i_medium, SIDES[0]); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), MEDIUM, i_medium, TOTAL_2D_SIDES[0]); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), grid_coordinate.y(), @@ -726,7 +726,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, std::vector& rr_rc_data, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, @@ -804,15 +804,15 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, if (is_vib_arch) { /* Create medium nodes */ - VTR_ASSERT(grids.width() == vib_grid.dim_size(1) && grids.height() == vib_grid.dim_size(2)); + VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { t_physical_tile_loc tile_loc(ix, iy, layer); - VTR_ASSERT(vib_grid[layer][ix][iy]->get_pbtype_name() == grids.get_physical_type(tile_loc)->name); + VTR_ASSERT(vib_grid.vib_pbtype_name(layer, ix, iy) == grids.get_physical_type(tile_loc)->name); vtr::Point grid_coordinate(ix, iy); - rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, MEDIUM, vib_grid[layer][ix][iy]->get_first_stages().size(), SIDES[0]); + rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, MEDIUM, vib_grid.num_medium_nodes(layer, ix, iy), TOTAL_2D_SIDES[0]); load_one_grid_medium_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, @@ -1299,7 +1299,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, std::map>& rr_node_track_ids, std::vector& rr_rc_data, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, From 8afea46145fd138aa25212d449a123888f2547d9 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:31:22 +0800 Subject: [PATCH 376/453] Update tileable_rr_graph_node_builder.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index b40bec09273..1c5643b4416 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -25,7 +25,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, vtr::vector& driver_switches, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, @@ -42,7 +42,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, std::map>& rr_node_track_ids, std::vector& rr_rc_data, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer, const vtr::Point& chan_width, const std::vector& segment_inf_x, From 1d45f3b9b077dda5ac2d2774ed48fc8b78d9c1c3 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:32:08 +0800 Subject: [PATCH 377/453] Update check_rr_graph.cpp --- libs/librrgraph/src/base/check_rr_graph.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 36e4e37a71c..d3b0e23d043 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -52,7 +52,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const std::vector& types, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, const t_graph_type graph_type, bool is_flat) { @@ -333,7 +333,7 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device void check_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, const enum e_route_type route_type, const int inode, @@ -391,8 +391,8 @@ void check_rr_node(const RRGraphView& rr_graph, /* Check that the segment is within the array and such. */ type = grid.get_physical_type({xlow, ylow, layer_num}); const VibInf* vib_type; - if (vib_grid.dim_size(0) > 0) { - vib_type = vib_grid[layer_num][xlow][ylow]; + if (vib_grid.get_num_layers() > 0) { + vib_type = vib_grid.get_vib(layer_num, xlow, ylow); } else { vib_type = nullptr; From e8c88fabdbe6e484ec849f1d60b8f945d4086020 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:32:33 +0800 Subject: [PATCH 378/453] Update check_rr_graph.h --- libs/librrgraph/src/base/check_rr_graph.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/librrgraph/src/base/check_rr_graph.h b/libs/librrgraph/src/base/check_rr_graph.h index facdb6ea75c..65f7d7c60d1 100644 --- a/libs/librrgraph/src/base/check_rr_graph.h +++ b/libs/librrgraph/src/base/check_rr_graph.h @@ -9,7 +9,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const std::vector& types, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, const t_graph_type graph_type, bool is_flat); @@ -17,7 +17,7 @@ void check_rr_graph(const RRGraphView& rr_graph, void check_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, const enum e_route_type route_type, const int inode, From 7c6d85cd597b553e613f6ffd5fbccf825658d2ad Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:33:10 +0800 Subject: [PATCH 379/453] Update vib_inf.h --- libs/libarchfpga/src/vib_inf.h | 180 +++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/libs/libarchfpga/src/vib_inf.h b/libs/libarchfpga/src/vib_inf.h index 73dcba8b284..c7ac9a0d204 100644 --- a/libs/libarchfpga/src/vib_inf.h +++ b/libs/libarchfpga/src/vib_inf.h @@ -26,8 +26,15 @@ /* for vib tag */ +enum e_parallel_axis_vib { + X, + Y, + BOTH_DIR +}; + struct t_seg_group { std::string name; + e_parallel_axis_vib axis; int seg_index; int track_num; }; @@ -49,10 +56,12 @@ struct t_from_or_to_inf { struct t_first_stage_mux_inf { std::string mux_name; + std::vector> from_tokens; std::vector froms; }; struct t_second_stage_mux_inf : t_first_stage_mux_inf { + std::vector to_tokens; std::vector to; // for io type, port[pin] may map to several sinks }; @@ -66,6 +75,58 @@ struct t_second_stage_mux_inf : t_first_stage_mux_inf { // std::vector second_stages; // }; +/* VibInf is used to reserve the VIB information. * + * For example, a VIB is described: * + * + + + + + + + L1.E0 L1.E1 + clb.O[0] L1.E2 + + + clb.I[0] MUX0 MUX1 + L1.N0 MUX0 MUX1 + + + + + Its corresponding figure is shown: + + * | L1.N0 + * +-----------------|-------+ + * L1.E0-----------------|>|\ MUX-1 _| vib0|----------\ + * L1.E1-----------------|>| |----| /__\ |... } l1: 20 tracks + * | |/ | | | | / + * | MUX0 |-------| | |----------\ + * L1.E2-----------------|>|\ | | |... } l2: 20 tracks + * | | |--| | | | / + * |------------------|>|/ | | | |----------\ + * | | MUX1 |-|---------| |... } l4: 16 tracks + * | | | | | / + * | ... | | | |----------\ + * | | _|_| |... } l8: 16 tracks + * | | \__/ MUX-0 | / + * | +-------------------------+ + * O[0]| | + * +-------------+ | + * | |<---------------------- + * | clb | I[0] + * +-------------+ + * + * Attributes: + * name_: The name of the VIB type, "vib0" in the example. + * pbtype_name_: The pbtype of the VIB, "clb" in the example. + * seg_group_num_: The number of segment groups. + * seg_groups_: The segments applied in the VIB. Their names correspond to segment names in . + * switch_name_:The name of the switch type used in the VIB, "mux0" in the example. + * switch_idx_: The index of corresponding switch in . + * first_stages_: The info of first stage MUXes, including the names of the MUXes and their from info. + * second_stages_: The info of second stage MUXes, including the names of the MUXes and their from/to info.*/ + class VibInf { public: VibInf(); @@ -75,6 +136,7 @@ class VibInf { void set_pbtype_name(const std::string pbtype_name); void set_seg_group_num(const int seg_group_num); void set_switch_idx(const int switch_idx); + void set_switch_name(const std::string switch_name); void set_seg_groups(const std::vector seg_groups); void push_seg_group(const t_seg_group seg_group); void set_first_stages(const std::vector first_stages); @@ -86,6 +148,7 @@ class VibInf { std::string get_pbtype_name() const; int get_seg_group_num() const; int get_switch_idx() const; + std::string get_switch_name() const; std::vector get_seg_groups() const; std::vector get_first_stages() const; std::vector get_second_stages() const; @@ -96,9 +159,126 @@ class VibInf { std::string pbtype_name_; /* pbtype name of vib */ int seg_group_num_; /* seg group number of vib */ int switch_idx_; /* vib switch index */ + std::string switch_name_; /* vib switch name */ std::vector seg_groups_; std::vector first_stages_; std::vector second_stages_; }; +/************************* VIB_GRID ***********************************/ +/* Describe different VIB type on different locations by immitating t_grid_loc_def. */ + +struct t_vib_grid_loc_spec { + t_vib_grid_loc_spec(std::string start, std::string end, std::string repeat, std::string incr) + : start_expr(std::move(start)) + , end_expr(std::move(end)) + , repeat_expr(std::move(repeat)) + , incr_expr(std::move(incr)) {} + + std::string start_expr; //Starting position (inclusive) + std::string end_expr; //Ending position (inclusive) + + std::string repeat_expr; //Distance between repeated + // region instances + + std::string incr_expr; //Distance between block instantiations + // with the region +}; + +enum VibGridDefType { + VIB_AUTO, + VIB_FIXED +}; + +struct t_vib_grid_loc_def { + t_vib_grid_loc_def(std::string block_type_val, int priority_val) + : block_type(block_type_val) + , priority(priority_val) + , x("0", "W-1", "max(w+1,W)", "w") //Fill in x direction, no repeat, incr by block width + , y("0", "H-1", "max(h+1,H)", "h") //Fill in y direction, no repeat, incr by block height + {} + + std::string block_type; //The block type name + + int priority = 0; //Priority of the specification. + // In case of conflicting specifications + // the largest priority wins. + + t_vib_grid_loc_spec x; //Horizontal location specification + t_vib_grid_loc_spec y; //Veritcal location specification + +}; + +struct t_vib_layer_def { + std::vector loc_defs; //The list of block location definitions for this layer specification +}; + +struct t_vib_grid_def { + VibGridDefType grid_type = VibGridDefType::VIB_AUTO; //The type of this grid specification + + std::string name = ""; //The name of this device + + int width = -1; //Fixed device width (only valid for grid_type == FIXED) + int height = -1; //Fixed device height (only valid for grid_type == FIXED) + + float aspect_ratio = 1.; //Aspect ratio for auto-sized devices (only valid for + //grid_type == AUTO) + std::vector layers; +}; + +///@brief DeviceGrid represents the FPGA fabric. It is used to get information about different layers and tiles. +// TODO: All of the function that use helper functions of this class should pass the layer_num to the functions, and the default value of layer_num should be deleted eventually. +class VibDeviceGrid { + public: + VibDeviceGrid() = default; + VibDeviceGrid(std::string grid_name, vtr::NdMatrix vib_grid); + + const std::string& name() const { return name_; } + + ///@brief Return the number of layers(number of dies) + inline int get_num_layers() const { + return (int)vib_grid_.dim_size(0); + } + + ///@brief Return the width of the grid at the specified layer + size_t width() const { return vib_grid_.dim_size(1); } + ///@brief Return the height of the grid at the specified layer + size_t height() const { return vib_grid_.dim_size(2); } + + ///@brief Return the size of the flattened grid on the given layer + inline size_t grid_size() const { + return vib_grid_.size(); + } + + const VibInf* get_vib(size_t layer, size_t x, size_t y) const { + return vib_grid_[layer][x][y]; + } + + size_t num_medium_nodes(size_t layer, size_t x, size_t y) const { + return vib_grid_[layer][x][y]->get_first_stages().size(); + } + + std::string medium_node_name(size_t layer, size_t x, size_t y, size_t medium_index) const { + return vib_grid_[layer][x][y]->get_first_stages()[medium_index].mux_name; + } + + std::string vib_pbtype_name(size_t layer, size_t x, size_t y) const { + return vib_grid_[layer][x][y]->get_pbtype_name(); + } + + private: + + std::string name_; + + /** + * @brief grid_ is a 3D matrix that represents the grid of the FPGA chip. + * @note The first dimension is the layer number (grid_[0] corresponds to the bottom layer), the second dimension is the x coordinate, and the third dimension is the y coordinate. + * @note Note that vtr::Matrix operator[] returns and intermediate type + * @note which can be used for indexing in the second dimension, allowing + * @note traditional 2-d indexing to be used + */ + vtr::NdMatrix vib_grid_; //This stores the grid of complex blocks. It is a 3D matrix: [0..num_layers-1][0..grid.width()-1][0..grid_height()-1] + +}; + #endif From 6075e312d81c51f1f428e29d39a5ca95e80107f1 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:33:46 +0800 Subject: [PATCH 380/453] Update physical_types.h --- libs/libarchfpga/src/physical_types.h | 47 --------------------------- 1 file changed, 47 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 2777a413d60..b228607d100 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -415,53 +415,6 @@ struct t_grid_def { std::vector layers; }; -/************************* VIB_GRID ***********************************/ -/* Describe different VIB type on different locations by immitating t_grid_loc_def. */ - -struct t_vib_grid_loc_def { - t_vib_grid_loc_def(std::string block_type_val, int priority_val) - : block_type(block_type_val) - , priority(priority_val) - , x("0", "W-1", "max(w+1,W)", "w") //Fill in x direction, no repeat, incr by block width - , y("0", "H-1", "max(h+1,H)", "h") //Fill in y direction, no repeat, incr by block height - {} - - std::string block_type; //The block type name - - int priority = 0; //Priority of the specification. - // In case of conflicting specifications - // the largest priority wins. - - t_grid_loc_spec x; //Horizontal location specification - t_grid_loc_spec y; //Veritcal location specification - - // When 1 metadata tag is split among multiple t_grid_loc_def, one - // t_grid_loc_def is arbitrarily chosen to own the metadata, and the other - // t_grid_loc_def point to the owned version. - std::unique_ptr owned_meta; - t_metadata_dict* meta = nullptr; // Metadata for this location definition. This - // metadata may be shared with multiple grid_locs - // that come from a common definition. -}; - -struct t_vib_layer_def { - std::vector loc_defs; //The list of block location definitions for this layer specification -}; - -struct t_vib_grid_def { - GridDefType grid_type = GridDefType::AUTO; //The type of this grid specification - - std::string name = ""; //The name of this device - - int width = -1; //Fixed device width (only valid for grid_type == FIXED) - int height = -1; //Fixed device height (only valid for grid_type == FIXED) - - float aspect_ratio = 1.; //Aspect ratio for auto-sized devices (only valid for - //grid_type == AUTO) - std::vector layers; -}; - - /************************* POWER ***********************************/ /* Global clock architecture */ From 3941eef4d5a641debeb7a9dd6e48b427226e65d1 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:34:18 +0800 Subject: [PATCH 381/453] Update vib_inf.cpp --- libs/libarchfpga/src/vib_inf.cpp | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/libs/libarchfpga/src/vib_inf.cpp b/libs/libarchfpga/src/vib_inf.cpp index 89dbab16355..1c80677bf6b 100644 --- a/libs/libarchfpga/src/vib_inf.cpp +++ b/libs/libarchfpga/src/vib_inf.cpp @@ -35,8 +35,14 @@ void VibInf::set_switch_idx(const int switch_idx) { switch_idx_ = switch_idx; } +void VibInf::set_switch_name(const std::string switch_name) { + VTR_ASSERT(!switch_name.empty()); + switch_name_ = switch_name; +} + void VibInf::set_seg_groups(const std::vector seg_groups) { VTR_ASSERT(!seg_groups.empty()); + seg_groups_.clear(); for(auto seg_group : seg_groups) { seg_groups_.push_back(seg_group); } @@ -49,6 +55,7 @@ void VibInf::push_seg_group(const t_seg_group seg_group) { void VibInf::set_first_stages(const std::vector first_stages) { VTR_ASSERT(!first_stages.empty()); + first_stages_.clear(); for(auto first_stage : first_stages) { first_stages_.push_back(first_stage); } @@ -61,6 +68,7 @@ void VibInf::push_first_stage(const t_first_stage_mux_inf first_stage) { void VibInf::set_second_stages(const std::vector second_stages) { VTR_ASSERT(!second_stages.empty()); + second_stages_.clear(); for(auto second_stage : second_stages) { second_stages_.push_back(second_stage); } @@ -71,8 +79,6 @@ void VibInf::push_second_stage(const t_second_stage_mux_inf second_stage) { second_stages_.push_back(second_stage); } - - std::string VibInf::get_name() const{ VTR_ASSERT(!name_.empty()); return name_; @@ -93,6 +99,11 @@ int VibInf::get_switch_idx() const{ return switch_idx_; } +std::string VibInf::get_switch_name() const{ + VTR_ASSERT(!switch_name_.empty()); + return switch_name_; +} + std::vector VibInf::get_seg_groups() const{ VTR_ASSERT(!seg_groups_.empty()); return seg_groups_; @@ -107,3 +118,10 @@ std::vector VibInf::get_second_stages() const{ VTR_ASSERT(!second_stages_.empty()); return second_stages_; } + + +VibDeviceGrid::VibDeviceGrid(std::string grid_name, vtr::NdMatrix vib_grid) + : name_(std::move(grid_name)) + , vib_grid_(std::move(vib_grid)) { + +} From 6be2c9a7fbdd92a5390d51871d149ee06a5cdfd8 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:34:47 +0800 Subject: [PATCH 382/453] Update read_xml_arch_file.cpp --- libs/libarchfpga/src/read_xml_arch_file.cpp | 813 ++++++++++---------- 1 file changed, 415 insertions(+), 398 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index ab8d8d900e3..3153dd93f84 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -397,20 +397,20 @@ static e_side string_to_side(const std::string& side_str); template static T* get_type_by_name(const char* type_name, std::vector& types); -static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, double mesh_region_start_x, double mesh_region_end_x, double mesh_region_start_y, double mesh_region_end_y, int mesh_size); +// static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, double mesh_region_start_x, double mesh_region_end_x, double mesh_region_start_y, double mesh_region_end_y, int mesh_size); -static bool parse_noc_router_connection_list(pugi::xml_node router_tag, const pugiutil::loc_data& loc_data, int router_id, std::vector& connection_list, std::string connection_list_attribute_value, std::map>& routers_in_arch_info); +// static bool parse_noc_router_connection_list(pugi::xml_node router_tag, const pugiutil::loc_data& loc_data, int router_id, std::vector& connection_list, std::string connection_list_attribute_value, std::map>& routers_in_arch_info); -static void update_router_info_in_arch(int router_id, bool router_updated_as_a_connection, std::map>& routers_in_arch_info); +// static void update_router_info_in_arch(int router_id, bool router_updated_as_a_connection, std::map>& routers_in_arch_info); -static void verify_noc_topology(std::map>& routers_in_arch_info); +// static void verify_noc_topology(std::map>& routers_in_arch_info); /* for vib arch */ static void ProcessVibArch(pugi::xml_node Parent, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data); static void ProcessVib(pugi::xml_node Vib_node, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data); -static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector segments, std::vector& first_stages, const pugiutil::loc_data& loc_data); -static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector segments, std::vector& second_stages, const pugiutil::loc_data& loc_data); -static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector segments, std::vector& froms); +static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& first_stages, const pugiutil::loc_data& loc_data); +static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& second_stages, const pugiutil::loc_data& loc_data); +// static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector& froms); void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); /* @@ -5170,212 +5170,212 @@ static T* get_type_by_name(const char* type_name, std::vector& types) { "Could not find type: %s\n", type_name); } -/* - * Create routers and set their properties so that a mesh grid of routers is created. Then connect the routers together so that a mesh topology is created. - */ -static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, double mesh_region_start_x, double mesh_region_end_x, double mesh_region_start_y, double mesh_region_end_y, int mesh_size) { - // check that the mesh size of the router is not 0 - if (mesh_size == 0) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), - "The NoC mesh size cannot be 0."); - } - - // calculating the vertical horizontal distances between routers in the supplied region - // we decrease the mesh size by 1 when calculating the spacing so that the first and last routers of each row or column are positioned on the mesh boundary - /* - * For example: - * - If we had a mesh size of 3, then using 3 would result in a spacing that would result in one router positions being placed in either the start of the reigion or end of the region. This is because the distance calculation resulted in having 3 spaces between the ends of the region - * - * start end - *** *** *** *** - * - * - if we instead used 2 in the distance calculation, the the resulting positions would result in having 2 routers positioned on the start and end of the region. This is beacuse we now specified 2 spaces between the region and this allows us to place 2 routers on the regions edges and one router in the center. - * - * start end - *** *** *** - * - * THe reasoning for this is to reduce the number of calculated router positions. - */ - double vertical_router_separation = (mesh_region_end_y - mesh_region_start_y) / (mesh_size - 1); - double horizontal_router_separation = (mesh_region_end_x - mesh_region_start_x) / (mesh_size - 1); - - t_router temp_router; - - // improper region check - if ((vertical_router_separation <= 0) || (horizontal_router_separation <= 0)) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), - "The NoC region is invalid."); - } - - // create routers and their connections - // start with router id 0 (bottom left of the chip) to the maximum router id (top right of the chip) - for (int j = 0; j < mesh_size; j++) { - for (int i = 0; i < mesh_size; i++) { - // assign router id - temp_router.id = (mesh_size * j) + i; - - // calculate router position - /* The first and last router of each column or row will be located on the mesh region boundary, the remaining routers will be placed within the region and seperated from other routers using the distance calculated previously. - */ - temp_router.device_x_position = (i * horizontal_router_separation) + mesh_region_start_x; - temp_router.device_y_position = (j * vertical_router_separation) + mesh_region_start_y; - - // assign connections - // check if there is a router to the left - if ((i - 1) >= 0) { - // add the left router as a connection - temp_router.connection_list.push_back((mesh_size * j) + i - 1); - } - - // check if there is a router to the top - if ((j + 1) <= (mesh_size - 1)) { - // add the top router as a connection - temp_router.connection_list.push_back((mesh_size * (j + 1)) + i); - } - - // check if there is a router to the right - if ((i + 1) <= (mesh_size - 1)) { - // add the router located to the right - temp_router.connection_list.push_back((mesh_size * j) + i + 1); - } - - // check of there is a router below - if ((j - 1) >= (0)) { - // add the bottom router as a connection - temp_router.connection_list.push_back((mesh_size * (j - 1)) + i); - } - - // add the router to the list - noc_ref->router_list.push_back(temp_router); - - // clear the current router information for the next router - temp_router.connection_list.clear(); - } - } - - return; -} - -/* - * THe user provides the list of routers any given router is connected to by the router ids seperated by spaces. For example: - * - * connections= 1 2 3 4 5 - * - * Go through the connections here and store them. Also make sure the list is legal. - */ -static bool parse_noc_router_connection_list(pugi::xml_node router_tag, const pugiutil::loc_data& loc_data, int router_id, std::vector& connection_list, std::string connection_list_attribute_value, std::map>& routers_in_arch_info) { - // we wil be modifying the string so store it in a temporary variable - // additinally, we peocess substrings seperated by spaces, so we add a space at the end of the string to be able to process the last sub-string - std::string modified_attribute_value = connection_list_attribute_value + " "; - std::string delimiter = " "; - std::stringstream single_connection; - int converted_connection; - - size_t position = 0; - - bool result = true; - - // find the position of the first space in the connection list string - while ((position = modified_attribute_value.find(delimiter)) != std::string::npos) { - // the string upto the space represent a single connection, so grab the substring - single_connection << modified_attribute_value.substr(0, position); - - // convert the connection to an integer - single_connection >> converted_connection; - - /* we expect the connection list to be a string of integers seperated by spaces, where each integer represents a router id that the current router is connected to. So we make sure that the router id was an integer. - */ - if (single_connection.fail()) { - // if we are here, then an integer was not supplied - result = false; - break; - } - - // check the case where a duplicate connection was provided - if (std::find(connection_list.begin(), connection_list.end(), converted_connection) != connection_list.end()) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(router_tag), - "The router with id:'%d' was included multiple times in the connection list for another router.", converted_connection); - } - - // make sure that the current router isn't connected to itself - if (router_id == converted_connection) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(router_tag), - "The router with id:%d was added to its own connection list. A router cannot connect to itself.", router_id); - } - - // if we are here then a legal router id was supplied, so store it - connection_list.push_back(converted_connection); - // update the connection information for the current router in the connection list - update_router_info_in_arch(converted_connection, true, routers_in_arch_info); - - // before we process the next router connection, we need to delete the substring (current router connection) - modified_attribute_value.erase(0, position + delimiter.length()); - // clear the buffer that stores the router connection in a string format for the next iteration - single_connection.clear(); - } - - return result; -} - -/* Each router needs a sperate tag in the architecture description - * to declare it. The number of declarations for each router in the - * architecture file is updated here. - * - * Additionally, for any given topology, a router can connect to other routers. - * THe number of connections for each router is also updated here. - * - */ -static void update_router_info_in_arch(int router_id, bool router_updated_as_a_connection, std::map>& routers_in_arch_info) { - // get the corresponding router info for the given router id - std::map>::iterator curr_router_info = routers_in_arch_info.find(router_id); - - // check if the router previously existed in the router indo database - if (curr_router_info == routers_in_arch_info.end()) { - // case where the router did not exist previosuly, so we add it here and also get a reference to it - // initially a router has no declarations or connections - curr_router_info = routers_in_arch_info.insert(std::pair>(router_id, std::pair(0, 0))).first; - } - - // case where the current router was provided while parsing the connections of another router - if (router_updated_as_a_connection) { - // since we are within the case where the current router is being processed as a connection to another router we just increment its number of connections - (curr_router_info->second.second)++; - - } else { - // since we are within the case where the current router is processed from a tag, we just increment its number of declarations - (curr_router_info->second.first)++; - } - - return; -} - -/* - * Verify each router in the noc by checking whether they satisfy the following conditions: - * - The router has only one declaration in the arch file - * - The router has atleast one connection to another router - * If any of the conditions above are not met, then an error is thrown. - */ -static void verify_noc_topology(std::map>& routers_in_arch_info) { - for (auto router_info = routers_in_arch_info.begin(); router_info != routers_in_arch_info.end(); router_info++) { - // case where the router was included in the architecture and had no connections to other routers - if ((router_info->second.first == 1) && (router_info->second.second == 0)) { - archfpga_throw("", -1, - "The router with id:'%d' is not connected to any other router in the NoC.", router_info->first); - - } // case where a router was found to be connected to another router but not declared using the tag in the arch file (ie. missing) - else if ((router_info->second.first == 0) && (router_info->second.second > 0)) { - archfpga_throw("", -1, - "The router with id:'%d' was found to be connected to another router but missing in the architecture file. Add the router using the tag.", router_info->first); - - } // case where the router was delcared multiple times in the architecture file (multiple tags for the same router) - else if (router_info->second.first > 1) { - archfpga_throw("", -1, - "The router with id:'%d' was included more than once in the architecture file. Routers should only be declared once.", router_info->first); - } - } - - return; -} +// /* +// * Create routers and set their properties so that a mesh grid of routers is created. Then connect the routers together so that a mesh topology is created. +// */ +// static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, double mesh_region_start_x, double mesh_region_end_x, double mesh_region_start_y, double mesh_region_end_y, int mesh_size) { +// // check that the mesh size of the router is not 0 +// if (mesh_size == 0) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), +// "The NoC mesh size cannot be 0."); +// } + +// // calculating the vertical horizontal distances between routers in the supplied region +// // we decrease the mesh size by 1 when calculating the spacing so that the first and last routers of each row or column are positioned on the mesh boundary +// /* +// * For example: +// * - If we had a mesh size of 3, then using 3 would result in a spacing that would result in one router positions being placed in either the start of the reigion or end of the region. This is because the distance calculation resulted in having 3 spaces between the ends of the region +// * +// * start end +// *** *** *** *** +// * +// * - if we instead used 2 in the distance calculation, the the resulting positions would result in having 2 routers positioned on the start and end of the region. This is beacuse we now specified 2 spaces between the region and this allows us to place 2 routers on the regions edges and one router in the center. +// * +// * start end +// *** *** *** +// * +// * THe reasoning for this is to reduce the number of calculated router positions. +// */ +// double vertical_router_separation = (mesh_region_end_y - mesh_region_start_y) / (mesh_size - 1); +// double horizontal_router_separation = (mesh_region_end_x - mesh_region_start_x) / (mesh_size - 1); + +// t_router temp_router; + +// // improper region check +// if ((vertical_router_separation <= 0) || (horizontal_router_separation <= 0)) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), +// "The NoC region is invalid."); +// } + +// // create routers and their connections +// // start with router id 0 (bottom left of the chip) to the maximum router id (top right of the chip) +// for (int j = 0; j < mesh_size; j++) { +// for (int i = 0; i < mesh_size; i++) { +// // assign router id +// temp_router.id = (mesh_size * j) + i; + +// // calculate router position +// /* The first and last router of each column or row will be located on the mesh region boundary, the remaining routers will be placed within the region and seperated from other routers using the distance calculated previously. +// */ +// temp_router.device_x_position = (i * horizontal_router_separation) + mesh_region_start_x; +// temp_router.device_y_position = (j * vertical_router_separation) + mesh_region_start_y; + +// // assign connections +// // check if there is a router to the left +// if ((i - 1) >= 0) { +// // add the left router as a connection +// temp_router.connection_list.push_back((mesh_size * j) + i - 1); +// } + +// // check if there is a router to the top +// if ((j + 1) <= (mesh_size - 1)) { +// // add the top router as a connection +// temp_router.connection_list.push_back((mesh_size * (j + 1)) + i); +// } + +// // check if there is a router to the right +// if ((i + 1) <= (mesh_size - 1)) { +// // add the router located to the right +// temp_router.connection_list.push_back((mesh_size * j) + i + 1); +// } + +// // check of there is a router below +// if ((j - 1) >= (0)) { +// // add the bottom router as a connection +// temp_router.connection_list.push_back((mesh_size * (j - 1)) + i); +// } + +// // add the router to the list +// noc_ref->router_list.push_back(temp_router); + +// // clear the current router information for the next router +// temp_router.connection_list.clear(); +// } +// } + +// return; +// } + +// /* +// * THe user provides the list of routers any given router is connected to by the router ids seperated by spaces. For example: +// * +// * connections= 1 2 3 4 5 +// * +// * Go through the connections here and store them. Also make sure the list is legal. +// */ +// static bool parse_noc_router_connection_list(pugi::xml_node router_tag, const pugiutil::loc_data& loc_data, int router_id, std::vector& connection_list, std::string connection_list_attribute_value, std::map>& routers_in_arch_info) { +// // we wil be modifying the string so store it in a temporary variable +// // additinally, we peocess substrings seperated by spaces, so we add a space at the end of the string to be able to process the last sub-string +// std::string modified_attribute_value = connection_list_attribute_value + " "; +// std::string delimiter = " "; +// std::stringstream single_connection; +// int converted_connection; + +// size_t position = 0; + +// bool result = true; + +// // find the position of the first space in the connection list string +// while ((position = modified_attribute_value.find(delimiter)) != std::string::npos) { +// // the string upto the space represent a single connection, so grab the substring +// single_connection << modified_attribute_value.substr(0, position); + +// // convert the connection to an integer +// single_connection >> converted_connection; + +// /* we expect the connection list to be a string of integers seperated by spaces, where each integer represents a router id that the current router is connected to. So we make sure that the router id was an integer. +// */ +// if (single_connection.fail()) { +// // if we are here, then an integer was not supplied +// result = false; +// break; +// } + +// // check the case where a duplicate connection was provided +// if (std::find(connection_list.begin(), connection_list.end(), converted_connection) != connection_list.end()) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(router_tag), +// "The router with id:'%d' was included multiple times in the connection list for another router.", converted_connection); +// } + +// // make sure that the current router isn't connected to itself +// if (router_id == converted_connection) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(router_tag), +// "The router with id:%d was added to its own connection list. A router cannot connect to itself.", router_id); +// } + +// // if we are here then a legal router id was supplied, so store it +// connection_list.push_back(converted_connection); +// // update the connection information for the current router in the connection list +// update_router_info_in_arch(converted_connection, true, routers_in_arch_info); + +// // before we process the next router connection, we need to delete the substring (current router connection) +// modified_attribute_value.erase(0, position + delimiter.length()); +// // clear the buffer that stores the router connection in a string format for the next iteration +// single_connection.clear(); +// } + +// return result; +// } + +// /* Each router needs a sperate tag in the architecture description +// * to declare it. The number of declarations for each router in the +// * architecture file is updated here. +// * +// * Additionally, for any given topology, a router can connect to other routers. +// * THe number of connections for each router is also updated here. +// * +// */ +// static void update_router_info_in_arch(int router_id, bool router_updated_as_a_connection, std::map>& routers_in_arch_info) { +// // get the corresponding router info for the given router id +// std::map>::iterator curr_router_info = routers_in_arch_info.find(router_id); + +// // check if the router previously existed in the router indo database +// if (curr_router_info == routers_in_arch_info.end()) { +// // case where the router did not exist previosuly, so we add it here and also get a reference to it +// // initially a router has no declarations or connections +// curr_router_info = routers_in_arch_info.insert(std::pair>(router_id, std::pair(0, 0))).first; +// } + +// // case where the current router was provided while parsing the connections of another router +// if (router_updated_as_a_connection) { +// // since we are within the case where the current router is being processed as a connection to another router we just increment its number of connections +// (curr_router_info->second.second)++; + +// } else { +// // since we are within the case where the current router is processed from a tag, we just increment its number of declarations +// (curr_router_info->second.first)++; +// } + +// return; +// } + +// /* +// * Verify each router in the noc by checking whether they satisfy the following conditions: +// * - The router has only one declaration in the arch file +// * - The router has atleast one connection to another router +// * If any of the conditions above are not met, then an error is thrown. +// */ +// static void verify_noc_topology(std::map>& routers_in_arch_info) { +// for (auto router_info = routers_in_arch_info.begin(); router_info != routers_in_arch_info.end(); router_info++) { +// // case where the router was included in the architecture and had no connections to other routers +// if ((router_info->second.first == 1) && (router_info->second.second == 0)) { +// archfpga_throw("", -1, +// "The router with id:'%d' is not connected to any other router in the NoC.", router_info->first); + +// } // case where a router was found to be connected to another router but not declared using the tag in the arch file (ie. missing) +// else if ((router_info->second.first == 0) && (router_info->second.second > 0)) { +// archfpga_throw("", -1, +// "The router with id:'%d' was found to be connected to another router but missing in the architecture file. Add the router using the tag.", router_info->first); + +// } // case where the router was delcared multiple times in the architecture file (multiple tags for the same router) +// else if (router_info->second.first > 1) { +// archfpga_throw("", -1, +// "The router with id:'%d' was included more than once in the architecture file. Routers should only be declared once.", router_info->first); +// } +// } + +// return; +// } /* for vib arch*/ static void ProcessVibArch(pugi::xml_node Parent, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data) { @@ -5400,8 +5400,8 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vector segments = arch->Segments; - t_arch_switch_inf* switches = arch->Switches; + // std::vector segments = arch->Segments; + // t_arch_switch_inf* switches = arch->Switches; tmp = get_attribute(Vib_node, "name", loc_data).as_string(nullptr); if (tmp) { @@ -5426,12 +5426,15 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vectornum_switches; i_switch++) { - if (!strcmp(tmp, switches[i_switch].name.c_str())) { - vib.set_switch_idx(i_switch); - break; - } - } + std::string str_tmp; + str_tmp = tmp; + vib.set_switch_name(str_tmp); + // for (int i_switch = 0; i_switch < arch->num_switches; i_switch++) { + // if (!strcmp(tmp, switches[i_switch].name.c_str())) { + // vib.set_switch_idx(i_switch); + // break; + // } + // } } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Vib_node), @@ -5451,18 +5454,31 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vector first_stages; - ProcessFirstStage(SubElem, PhysicalTileTypes, segments, first_stages, loc_data); + ProcessFirstStage(SubElem, PhysicalTileTypes, first_stages, loc_data); for (auto first_stage : first_stages) { vib.push_first_stage(first_stage); @@ -5494,7 +5510,7 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vector second_stages; - ProcessSecondStage(SubElem, PhysicalTileTypes, segments, second_stages, loc_data); + ProcessSecondStage(SubElem, PhysicalTileTypes, second_stages, loc_data); for (auto second_stage : second_stages) { vib.push_second_stage(second_stage); @@ -5505,7 +5521,7 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vectorvib_infs.push_back(vib); } -static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector segments, std::vector& first_stages, const pugiutil::loc_data& loc_data) { +static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& first_stages, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; pugi::xml_node SubElem; //pugi::xml_node Cur; @@ -5524,7 +5540,8 @@ static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector from_tokens = vtr::split(SubElem.child_value()); - ProcessFromOrToTokens(from_tokens, PhysicalTileTypes, segments, first_stage_mux.froms); + first_stage_mux.from_tokens.push_back(from_tokens); + //ProcessFromOrToTokens(from_tokens, PhysicalTileTypes, segments, first_stage_mux.froms); SubElem = SubElem.next_sibling(SubElem.name()); } first_stages.push_back(first_stage_mux); @@ -5533,7 +5550,7 @@ static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector segments, std::vector& second_stages, const pugiutil::loc_data& loc_data) { +static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& second_stages, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; pugi::xml_node SubElem; //pugi::xml_node Cur; @@ -5554,21 +5571,21 @@ static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector to_tokens = vtr::split(SubElem.child_value()); VTR_ASSERT(to_tokens.size() == 1); - std::vector tos; - ProcessFromOrToTokens(to_tokens, PhysicalTileTypes, segments, tos); - for (auto to : tos) { - VTR_ASSERT(to.from_type == SEGMENT || to.from_type == PB); - second_stage_mux.to.push_back(to); - } - + second_stage_mux.to_tokens = to_tokens; + // std::vector tos; + + // ProcessFromOrToTokens(to_tokens, PhysicalTileTypes, segments, tos); + // for (auto to : tos) { + // //VTR_ASSERT(to.from_type == SEGMENT || to.from_type == PB); + // second_stage_mux.to.push_back(to); + // } - - SubElem = get_first_child(Node, "from", loc_data); int from_num = count_children(Node, "from", loc_data); for (int i_from = 0; i_from < from_num; i_from++) { std::vector from_tokens = vtr::split(SubElem.child_value()); - ProcessFromOrToTokens(from_tokens, PhysicalTileTypes, segments, second_stage_mux.froms); + second_stage_mux.from_tokens.push_back(from_tokens); + //ProcessFromOrToTokens(from_tokens, PhysicalTileTypes, segments, second_stage_mux.froms); SubElem = SubElem.next_sibling(SubElem.name()); } @@ -5578,153 +5595,153 @@ static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector Tokens, std::vector& PhysicalTileTypes, std::vector segments, std::vector& froms) { - for (int i_token = 0; i_token < (int)Tokens.size(); i_token++) { - std::string Token = Tokens[i_token]; - const char* Token_char = Token.c_str(); - auto token = vtr::split(Token, "."); - if (token.size() == 1) { - t_from_or_to_inf from_inf; - from_inf.type_name = token[0]; - from_inf.from_type = MUX; - froms.push_back(from_inf); - } - else if (token.size() == 2) { - std::string from_type_name = token[0]; - e_multistage_mux_from_or_to_type from_type; - for (int i_phy_type = 0; i_phy_type < (int)PhysicalTileTypes.size(); i_phy_type++) { - if (from_type_name == PhysicalTileTypes[i_phy_type].name) { - from_type = PB; - int start_pin_index, end_pin_index; - char *pb_type_name, *port_name; - pb_type_name = nullptr; - port_name = nullptr; - pb_type_name = new char[strlen(Token_char)]; - port_name = new char[strlen(Token_char)]; - parse_pin_name((char*)Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); +// static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector segments, std::vector& froms) { +// for (int i_token = 0; i_token < (int)Tokens.size(); i_token++) { +// std::string Token = Tokens[i_token]; +// const char* Token_char = Token.c_str(); +// auto token = vtr::split(Token, "."); +// if (token.size() == 1) { +// t_from_or_to_inf from_inf; +// from_inf.type_name = token[0]; +// from_inf.from_type = MUX; +// froms.push_back(from_inf); +// } +// else if (token.size() == 2) { +// std::string from_type_name = token[0]; +// e_multistage_mux_from_or_to_type from_type; +// for (int i_phy_type = 0; i_phy_type < (int)PhysicalTileTypes.size(); i_phy_type++) { +// if (from_type_name == PhysicalTileTypes[i_phy_type].name) { +// from_type = PB; +// int start_pin_index, end_pin_index; +// char *pb_type_name, *port_name; +// pb_type_name = nullptr; +// port_name = nullptr; +// pb_type_name = new char[strlen(Token_char)]; +// port_name = new char[strlen(Token_char)]; +// parse_pin_name((char*)Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); - std::vector all_sub_tile_to_tile_pin_indices; - for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { - int sub_tile_capacity = sub_tile.capacity.total(); - - int start = 0; - int end = 0; - int i_port = 0; - for (; i_port < (int)sub_tile.ports.size(); ++i_port) { - if (!strcmp(sub_tile.ports[i_port].name, port_name)) { - start = sub_tile.ports[i_port].absolute_first_pin_index; - end = start + sub_tile.ports[i_port].num_pins - 1; - break; - } - } - if (i_port == (int)sub_tile.ports.size()) { - continue; - } - for (int pin_num = start; pin_num <= end; ++pin_num) { - VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); - for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { - int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; - int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; - all_sub_tile_to_tile_pin_indices.push_back(physical_pin_index); - } - } - } - - if (start_pin_index == end_pin_index && start_pin_index < 0) { - start_pin_index = 0; - end_pin_index = all_sub_tile_to_tile_pin_indices.size() - 1; - } - - if ((int)all_sub_tile_to_tile_pin_indices.size() <= start_pin_index || (int)all_sub_tile_to_tile_pin_indices.size() <= end_pin_index) { - VTR_LOGF_ERROR(__FILE__, __LINE__, - "The index of pbtype %s : port %s exceeds its total number!\n", pb_type_name, port_name); - } - - for (int i = start_pin_index; i <= end_pin_index; i++) { - t_from_or_to_inf from_inf; - from_inf.type_name = from_type_name; - from_inf.from_type = from_type; - from_inf.type_index = i_phy_type; - from_inf.phy_pin_index = all_sub_tile_to_tile_pin_indices[i]; - froms.push_back(from_inf); - } +// std::vector all_sub_tile_to_tile_pin_indices; +// for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { +// int sub_tile_capacity = sub_tile.capacity.total(); + +// int start = 0; +// int end = 0; +// int i_port = 0; +// for (; i_port < (int)sub_tile.ports.size(); ++i_port) { +// if (!strcmp(sub_tile.ports[i_port].name, port_name)) { +// start = sub_tile.ports[i_port].absolute_first_pin_index; +// end = start + sub_tile.ports[i_port].num_pins - 1; +// break; +// } +// } +// if (i_port == (int)sub_tile.ports.size()) { +// continue; +// } +// for (int pin_num = start; pin_num <= end; ++pin_num) { +// VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); +// for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { +// int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; +// int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; +// all_sub_tile_to_tile_pin_indices.push_back(physical_pin_index); +// } +// } +// } + +// if (start_pin_index == end_pin_index && start_pin_index < 0) { +// start_pin_index = 0; +// end_pin_index = all_sub_tile_to_tile_pin_indices.size() - 1; +// } + +// if ((int)all_sub_tile_to_tile_pin_indices.size() <= start_pin_index || (int)all_sub_tile_to_tile_pin_indices.size() <= end_pin_index) { +// VTR_LOGF_ERROR(__FILE__, __LINE__, +// "The index of pbtype %s : port %s exceeds its total number!\n", pb_type_name, port_name); +// } + +// for (int i = start_pin_index; i <= end_pin_index; i++) { +// t_from_or_to_inf from_inf; +// from_inf.type_name = from_type_name; +// from_inf.from_type = from_type; +// from_inf.type_index = i_phy_type; +// from_inf.phy_pin_index = all_sub_tile_to_tile_pin_indices[i]; +// froms.push_back(from_inf); +// } - // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { - // //int sub_tile_index = sub_tile.index; - // int sub_tile_capacity = sub_tile.capacity.total(); +// // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { +// // //int sub_tile_index = sub_tile.index; +// // int sub_tile_capacity = sub_tile.capacity.total(); - // int i_port = 0; - // for (; i_port < (int)sub_tile.ports.size(); ++i_port) { +// // int i_port = 0; +// // for (; i_port < (int)sub_tile.ports.size(); ++i_port) { - // if (!strcmp(sub_tile.ports[i_port].name, port_name)) { - // if (start_pin_index == end_pin_index && start_pin_index < 0) { - // start_pin_index = 0; - // end_pin_index = sub_tile.ports[i_port].num_pins - 1; - // } - // start_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; - // end_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; - // break; - // } - // } - - // if (i_port == (int)sub_tile.ports.size()) { - // continue; - // } - - // for (int pin_num = start_pin_index; pin_num <= end_pin_index; ++pin_num) { - // VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); - // for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { - // int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; - // int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; - // t_from_or_to_inf from_inf; - // from_inf.type_name = from_type_name; - // from_inf.from_type = from_type; - // from_inf.type_index = i_phy_type; - // from_inf.phy_pin_index = physical_pin_index; - // froms.push_back(from_inf); - // } - // } - // } +// // if (!strcmp(sub_tile.ports[i_port].name, port_name)) { +// // if (start_pin_index == end_pin_index && start_pin_index < 0) { +// // start_pin_index = 0; +// // end_pin_index = sub_tile.ports[i_port].num_pins - 1; +// // } +// // start_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; +// // end_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; +// // break; +// // } +// // } + +// // if (i_port == (int)sub_tile.ports.size()) { +// // continue; +// // } + +// // for (int pin_num = start_pin_index; pin_num <= end_pin_index; ++pin_num) { +// // VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); +// // for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { +// // int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; +// // int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; +// // t_from_or_to_inf from_inf; +// // from_inf.type_name = from_type_name; +// // from_inf.from_type = from_type; +// // from_inf.type_index = i_phy_type; +// // from_inf.phy_pin_index = physical_pin_index; +// // froms.push_back(from_inf); +// // } +// // } +// // } - } - } - for (int i_seg_type = 0; i_seg_type < (int)segments.size(); i_seg_type++) { - if (from_type_name == segments[i_seg_type].name) { - from_type = SEGMENT; - std::string from_detail = token[1]; - if (from_detail.length() >= 2) { - char dir = from_detail.c_str()[0]; - from_detail.erase(from_detail.begin()); - int seg_index = std::stoi(from_detail); - - t_from_or_to_inf from_inf; - from_inf.type_name = from_type_name; - from_inf.from_type = from_type; - from_inf.type_index = i_seg_type; - from_inf.seg_dir = dir; - from_inf.seg_index = seg_index; - froms.push_back(from_inf); - } +// } +// } +// for (int i_seg_type = 0; i_seg_type < (int)segments.size(); i_seg_type++) { +// if (from_type_name == segments[i_seg_type].name) { +// from_type = SEGMENT; +// std::string from_detail = token[1]; +// if (from_detail.length() >= 2) { +// char dir = from_detail.c_str()[0]; +// from_detail.erase(from_detail.begin()); +// int seg_index = std::stoi(from_detail); + +// t_from_or_to_inf from_inf; +// from_inf.type_name = from_type_name; +// from_inf.from_type = from_type; +// from_inf.type_index = i_seg_type; +// from_inf.seg_dir = dir; +// from_inf.seg_index = seg_index; +// froms.push_back(from_inf); +// } - break; - } - } - VTR_ASSERT(from_type == PB || from_type == SEGMENT); +// break; +// } +// } +// VTR_ASSERT(from_type == PB || from_type == SEGMENT); - } - else { - std::string msg = vtr::string_fmt("Failed to parse vib mux from information '%s'", Token.c_str()); - throw ArchFpgaError(msg); - } - } -} +// } +// else { +// std::string msg = vtr::string_fmt("Failed to parse vib mux from information '%s'", Token.c_str()); +// throw ArchFpgaError(msg); +// } +// } +// } void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name) { /* Parses out the pb_type_name and port_name * * If the start_pin_index and end_pin_index is specified, parse them too. * * Return the values parsed by reference. */ - char source_string[128]; + char* source_string = nullptr; char* find_format = nullptr; int ichar, match_count; @@ -5848,7 +5865,7 @@ static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi if (layout_type_tag.name() == std::string("auto_layout")) { //expect_only_attributes(layout_type_tag, {"aspect_ratio"}, loc_data); - grid_def.grid_type = GridDefType::AUTO; + grid_def.grid_type = VibGridDefType::VIB_AUTO; grid_def.name = "auto"; for (size_t i = 0;i < arch->grid_layouts.size(); i++) { @@ -5861,7 +5878,7 @@ static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi } else if (layout_type_tag.name() == std::string("fixed_layout")) { expect_only_attributes(layout_type_tag, {"name"}, loc_data); - grid_def.grid_type = GridDefType::FIXED; + grid_def.grid_type = VibGridDefType::VIB_FIXED; //grid_def.width = get_attribute(layout_type_tag, "width", loc_data).as_int(); //grid_def.height = get_attribute(layout_type_tag, "height", loc_data).as_int(); std::string name = get_attribute(layout_type_tag, "name", loc_data).value(); @@ -5956,11 +5973,11 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, top_edge.y.start_expr = "H - 1"; top_edge.y.end_expr = "H - 1"; - left_edge.owned_meta = std::make_unique(meta); - left_edge.meta = left_edge.owned_meta.get(); - right_edge.meta = left_edge.owned_meta.get(); - top_edge.meta = left_edge.owned_meta.get(); - bottom_edge.meta = left_edge.owned_meta.get(); + // left_edge.owned_meta = std::make_unique(meta); + // left_edge.meta = left_edge.owned_meta.get(); + // right_edge.meta = left_edge.owned_meta.get(); + // top_edge.meta = left_edge.owned_meta.get(); + // bottom_edge.meta = left_edge.owned_meta.get(); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(left_edge)); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(right_edge)); @@ -5995,11 +6012,11 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, top_right.y.start_expr = "H-1"; top_right.y.end_expr = "H-1"; - bottom_left.owned_meta = std::make_unique(meta); - bottom_left.meta = bottom_left.owned_meta.get(); - top_left.meta = bottom_left.owned_meta.get(); - bottom_right.meta = bottom_left.owned_meta.get(); - top_right.meta = bottom_left.owned_meta.get(); + // bottom_left.owned_meta = std::make_unique(meta); + // bottom_left.meta = bottom_left.owned_meta.get(); + // top_left.meta = bottom_left.owned_meta.get(); + // bottom_right.meta = bottom_left.owned_meta.get(); + // top_right.meta = bottom_left.owned_meta.get(); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_left)); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_left)); @@ -6015,8 +6032,8 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, fill.y.start_expr = "0"; fill.y.end_expr = "H - 1"; - fill.owned_meta = std::make_unique(meta); - fill.meta = fill.owned_meta.get(); + // fill.owned_meta = std::make_unique(meta); + // fill.meta = fill.owned_meta.get(); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(fill)); @@ -6029,8 +6046,8 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, single.x.end_expr = single.x.start_expr + " + w - 1"; single.y.end_expr = single.y.start_expr + " + h - 1"; - single.owned_meta = std::make_unique(meta); - single.meta = single.owned_meta.get(); + // single.owned_meta = std::make_unique(meta); + // single.meta = single.owned_meta.get(); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(single)); @@ -6059,8 +6076,8 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, col.y.incr_expr = incry_attr.value(); } - col.owned_meta = std::make_unique(meta); - col.meta = col.owned_meta.get(); + // col.owned_meta = std::make_unique(meta); + // col.meta = col.owned_meta.get(); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(col)); @@ -6089,8 +6106,8 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, row.x.incr_expr = incrx_attr.value(); } - row.owned_meta = std::make_unique(meta); - row.meta = row.owned_meta.get(); + // row.owned_meta = std::make_unique(meta); + // row.meta = row.owned_meta.get(); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(row)); } else if (loc_type == std::string("region")) { @@ -6141,8 +6158,8 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, region.y.incr_expr = incry_attr.value(); } - region.owned_meta = std::make_unique(meta); - region.meta = region.owned_meta.get(); + // region.owned_meta = std::make_unique(meta); + // region.meta = region.owned_meta.get(); grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(region)); } else { From 391d0443306c7ebb3a99a6c9e20011226ed1549e Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:35:30 +0800 Subject: [PATCH 383/453] Update SetupVPR.cpp --- vpr/src/base/SetupVPR.cpp | 284 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 284 insertions(+) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 49833d5f354..6c42bae7df8 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -49,6 +49,16 @@ static void SetupSwitches(const t_arch& Arch, static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysis_opts); static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch); +static void SetupVibInf(const std::vector& PhysicalTileTypes, + const int num_switches, + const t_arch_switch_inf* Switches, + const std::vector& Segments, + std::vector& vib_infs); + +static void ProcessFromOrToTokens(const std::vector Tokens, const std::vector& PhysicalTileTypes, const std::vector segments, std::vector& froms); +static void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); + + /** * @brief Identify which switch must be used for *track* to *IPIN* connections based on architecture file specification. * @param Arch Architecture file specification @@ -239,6 +249,8 @@ void SetupVPR(const t_options* options, routingArch->write_rr_graph_filename = options->write_rr_graph_file; routingArch->read_rr_graph_filename = options->read_rr_graph_file; + SetupVibInf(device_ctx.physical_tile_types, arch->num_switches, arch->Switches, arch->Segments, arch->vib_infs); + for (auto has_global_routing : arch->layer_global_routing) { device_ctx.inter_cluster_prog_routing_resources.emplace_back(has_global_routing); } @@ -1045,3 +1057,275 @@ static void do_reachability_analysis(t_physical_tile_type* physical_tile, } } } + +static void SetupVibInf(const std::vector& PhysicalTileTypes, + const int num_switches, + const t_arch_switch_inf* Switches, + const std::vector& Segments, + std::vector& vib_infs) { + VTR_ASSERT(!vib_infs.empty()); + for (auto& vib_inf : vib_infs) { + for (int i_switch = 0; i_switch < num_switches; i_switch++) { + if (vib_inf.get_switch_name() == Switches[i_switch].name) { + vib_inf.set_switch_idx(i_switch); + break; + } + } + + std::vector seg_groups = vib_inf.get_seg_groups(); + for (auto& seg_group : seg_groups) { + for (int i_seg = 0; i_seg < (int)Segments.size(); i_seg++) { + if (Segments[i_seg].name == seg_group.name) { + seg_group.seg_index = i_seg; + break; + } + } + } + vib_inf.set_seg_groups(seg_groups); + + std::vector first_stages = vib_inf.get_first_stages(); + for (auto& first_stage : first_stages) { + auto& from_tokens = first_stage.from_tokens; + for (const auto& from_token : from_tokens) { + ProcessFromOrToTokens(from_token, PhysicalTileTypes, Segments, first_stage.froms); + } + } + vib_inf.set_first_stages(first_stages); + + auto second_stages = vib_inf.get_second_stages(); + for (auto& second_stage : second_stages) { + std::vector tos; + + ProcessFromOrToTokens(second_stage.to_tokens, PhysicalTileTypes, Segments, tos); + for (auto& to : tos) { + VTR_ASSERT(to.from_type == SEGMENT || to.from_type == PB); + second_stage.to.push_back(to); + } + + auto from_tokens = second_stage.from_tokens; + for (const auto& from_token : from_tokens) { + ProcessFromOrToTokens(from_token, PhysicalTileTypes, Segments, second_stage.froms); + } + } + vib_inf.set_second_stages(second_stages); + + } +} + +static void ProcessFromOrToTokens(const std::vector Tokens, const std::vector& PhysicalTileTypes, const std::vector segments, std::vector& froms) { + for (int i_token = 0; i_token < (int)Tokens.size(); i_token++) { + std::string Token = Tokens[i_token]; + const char* Token_char = Token.c_str(); + auto token = vtr::split(Token, "."); + if (token.size() == 1) { + t_from_or_to_inf from_inf; + from_inf.type_name = token[0]; + from_inf.from_type = MUX; + froms.push_back(from_inf); + } + else if (token.size() == 2) { + std::string from_type_name = token[0]; + e_multistage_mux_from_or_to_type from_type; + for (int i_phy_type = 0; i_phy_type < (int)PhysicalTileTypes.size(); i_phy_type++) { + if (from_type_name == PhysicalTileTypes[i_phy_type].name) { + from_type = PB; + int start_pin_index, end_pin_index; + char *pb_type_name, *port_name; + pb_type_name = nullptr; + port_name = nullptr; + pb_type_name = new char[strlen(Token_char)]; + port_name = new char[strlen(Token_char)]; + parse_pin_name((char*)Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); + + std::vector all_sub_tile_to_tile_pin_indices; + for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { + int sub_tile_capacity = sub_tile.capacity.total(); + + int start = 0; + int end = 0; + int i_port = 0; + for (; i_port < (int)sub_tile.ports.size(); ++i_port) { + if (!strcmp(sub_tile.ports[i_port].name, port_name)) { + start = sub_tile.ports[i_port].absolute_first_pin_index; + end = start + sub_tile.ports[i_port].num_pins - 1; + break; + } + } + if (i_port == (int)sub_tile.ports.size()) { + continue; + } + for (int pin_num = start; pin_num <= end; ++pin_num) { + VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); + for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { + int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; + int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; + all_sub_tile_to_tile_pin_indices.push_back(physical_pin_index); + } + } + } + + if (start_pin_index == end_pin_index && start_pin_index < 0) { + start_pin_index = 0; + end_pin_index = all_sub_tile_to_tile_pin_indices.size() - 1; + } + + if ((int)all_sub_tile_to_tile_pin_indices.size() <= start_pin_index || (int)all_sub_tile_to_tile_pin_indices.size() <= end_pin_index) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "The index of pbtype %s : port %s exceeds its total number!\n", pb_type_name, port_name); + } + + for (int i = start_pin_index; i <= end_pin_index; i++) { + t_from_or_to_inf from_inf; + from_inf.type_name = from_type_name; + from_inf.from_type = from_type; + from_inf.type_index = i_phy_type; + from_inf.phy_pin_index = all_sub_tile_to_tile_pin_indices[i]; + froms.push_back(from_inf); + } + + // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { + // //int sub_tile_index = sub_tile.index; + // int sub_tile_capacity = sub_tile.capacity.total(); + + // int i_port = 0; + // for (; i_port < (int)sub_tile.ports.size(); ++i_port) { + + // if (!strcmp(sub_tile.ports[i_port].name, port_name)) { + // if (start_pin_index == end_pin_index && start_pin_index < 0) { + // start_pin_index = 0; + // end_pin_index = sub_tile.ports[i_port].num_pins - 1; + // } + // start_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + // end_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + // break; + // } + // } + + // if (i_port == (int)sub_tile.ports.size()) { + // continue; + // } + + // for (int pin_num = start_pin_index; pin_num <= end_pin_index; ++pin_num) { + // VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); + // for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { + // int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; + // int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; + // t_from_or_to_inf from_inf; + // from_inf.type_name = from_type_name; + // from_inf.from_type = from_type; + // from_inf.type_index = i_phy_type; + // from_inf.phy_pin_index = physical_pin_index; + // froms.push_back(from_inf); + // } + // } + // } + + } + } + for (int i_seg_type = 0; i_seg_type < (int)segments.size(); i_seg_type++) { + if (from_type_name == segments[i_seg_type].name) { + from_type = SEGMENT; + std::string from_detail = token[1]; + if (from_detail.length() >= 2) { + char dir = from_detail.c_str()[0]; + from_detail.erase(from_detail.begin()); + int seg_index = std::stoi(from_detail); + + t_from_or_to_inf from_inf; + from_inf.type_name = from_type_name; + from_inf.from_type = from_type; + from_inf.type_index = i_seg_type; + from_inf.seg_dir = dir; + from_inf.seg_index = seg_index; + froms.push_back(from_inf); + } + + break; + } + } + VTR_ASSERT(from_type == PB || from_type == SEGMENT); + + } + else { + std::string msg = vtr::string_fmt("Failed to parse vib mux from information '%s'", Token.c_str()); + VTR_LOGF_ERROR(__FILE__, __LINE__, msg.c_str()); + } + } +} + +static void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name) { + /* Parses out the pb_type_name and port_name * + * If the start_pin_index and end_pin_index is specified, parse them too. * + * Return the values parsed by reference. */ + + char source_string[128]; + char* find_format = nullptr; + int ichar, match_count; + + // parse out the pb_type and port name, possibly pin_indices + find_format = strstr(src_string, "["); + if (find_format == nullptr) { + /* Format "pb_type_name.port_name" */ + *start_pin_index = *end_pin_index = -1; + + + strcpy(source_string, src_string); + + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s", pb_type_name, port_name); + if (match_count != 2) { + VTR_LOG_ERROR( + "Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + src_string); + exit(1); + } + } else { + /* Format "pb_type_name.port_name[end_pin_index:start_pin_index]" */ + strcpy(source_string, src_string); + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + //Need white space between the components when using %s with + //sscanf + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + if (source_string[ichar] == '[') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s %d:%d]", + pb_type_name, port_name, + end_pin_index, start_pin_index); + if (match_count != 4) { + match_count = sscanf(source_string, "%s %s %d]", + pb_type_name, port_name, + end_pin_index); + *start_pin_index = *end_pin_index; + if (match_count != 3) { + VTR_LOG_ERROR( + "Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + src_string); + exit(1); + } + } + if (*end_pin_index < 0 || *start_pin_index < 0) { + VTR_LOG_ERROR( + "Invalid pin - %s, the pin_index in " + "[end_pin_index:start_pin_index] should not be a negative value.\n", + src_string); + exit(1); + } + if (*end_pin_index < *start_pin_index) { + int temp; + temp = *end_pin_index; + *end_pin_index = *start_pin_index; + *start_pin_index = temp; + } + } +} From 6f681c2bb611bf7579334a1dc76b0e5653a8eb8d Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:36:06 +0800 Subject: [PATCH 384/453] Update SetupGrid.cpp --- vpr/src/base/SetupGrid.cpp | 793 ++++++++++++++++++------------------- 1 file changed, 395 insertions(+), 398 deletions(-) diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index d1d6c7633c9..0d9b3138f0f 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -33,7 +33,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); static bool grid_satisfies_instance_counts(const DeviceGrid& grid, const std::map& instance_counts, float maximum_utilization); static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, const std::vector& limiting_resources = std::vector()); -static vtr::NdMatrix build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range = true); +// static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range = true); static void CheckGrid(const DeviceGrid& grid); @@ -46,14 +46,13 @@ static void set_grid_block_type(int priority, vtr::NdMatrix& grid_priorities, const t_metadata_dict* meta); -static void set_vib_grid_block_type(int priority, - const VibInf* type, - int layer_num, - size_t x_root, - size_t y_root, - vtr::NdMatrix& vib_grid, - vtr::NdMatrix& grid_priorities, - const t_metadata_dict* meta); +// static void set_vib_grid_block_type(int priority, +// const VibInf* type, +// int layer_num, +// size_t x_root, +// size_t y_root, +// vtr::NdMatrix& vib_grid, +// vtr::NdMatrix& grid_priorities); ///@brief Create the device grid based on resource requirements DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, const std::map& minimum_instance_counts, float target_device_utilization) { @@ -148,36 +147,36 @@ DeviceGrid create_device_grid(const std::string& layout_name, const std::vector< } } -vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts) { - if (layout_name == "auto") { - //We do not support auto layout now - // - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); +// VibDeviceGrid create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts) { +// if (layout_name == "auto") { +// //We do not support auto layout now +// // +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); - } else { - //Use the specified device - - //Find the matching grid definition - auto cmp = [&](const t_vib_grid_def& grid_def) { - return grid_def.name == layout_name; - }; - - auto iter = std::find_if(vib_grid_layouts.begin(), vib_grid_layouts.end(), cmp); - if (iter == vib_grid_layouts.end()) { - //Not found - std::string valid_names; - for (size_t i = 0; i < vib_grid_layouts.size(); ++i) { - if (i != 0) { - valid_names += ", "; - } - valid_names += "'" + vib_grid_layouts[i].name + "'"; - } - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find grid layout named '%s' (valid grid layouts: %s)\n", layout_name.c_str(), valid_names.c_str()); - } - - return build_vib_device_grid(*iter, iter->width, iter->height); - } -} +// } else { +// //Use the specified device + +// //Find the matching grid definition +// auto cmp = [&](const t_vib_grid_def& grid_def) { +// return grid_def.name == layout_name; +// }; + +// auto iter = std::find_if(vib_grid_layouts.begin(), vib_grid_layouts.end(), cmp); +// if (iter == vib_grid_layouts.end()) { +// //Not found +// std::string valid_names; +// for (size_t i = 0; i < vib_grid_layouts.size(); ++i) { +// if (i != 0) { +// valid_names += ", "; +// } +// valid_names += "'" + vib_grid_layouts[i].name + "'"; +// } +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find grid layout named '%s' (valid grid layouts: %s)\n", layout_name.c_str(), valid_names.c_str()); +// } + +// return build_vib_device_grid(*iter, iter->width, iter->height); +// } +// } /** * @brief Create a device grid which satisfies the minimum block counts @@ -590,226 +589,225 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt return device_grid; } -///@brief Build the specified device grid -static vtr::NdMatrix build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range) { - if (grid_def.grid_type == GridDefType::FIXED) { - if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { - VPR_FATAL_ERROR(VPR_ERROR_OTHER, - "Requested grid size (%zu%zu) does not match fixed device size (%dx%d)", - grid_width, grid_height, grid_def.width, grid_def.height); - } - } - - auto& device_ctx = g_vpr_ctx.device(); - - //Initialize the grid and each location priority based on available dies in the architecture file - vtr::NdMatrix vib_grid; - vtr::NdMatrix grid_priorities; - int num_layers = (int)grid_def.layers.size(); - vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); - //Track the current priority for each grid location - // Note that we initialize it to the lowest (i.e. most negative) possible value, so - // any user-specified priority will override the default empty grid - grid_priorities.resize(std::array{(size_t)num_layers, grid_width, grid_height}, std::numeric_limits::lowest()); - - //Initialize the device to all empty blocks - const VibInf* empty_type = nullptr; - //VTR_ASSERT(empty_type != nullptr); - for (int layer = 0; layer < num_layers; ++layer) { - for (size_t x = 0; x < grid_width; ++x) { - for (size_t y = 0; y < grid_height; ++y) { - set_vib_grid_block_type(std::numeric_limits::lowest() + 1, //+1 so it overrides without warning - empty_type, - layer, x, y, - vib_grid, grid_priorities, - /*meta=*/nullptr); - } - } - } - - FormulaParser p; - std::set seen_types; - for (int layer = 0; layer < num_layers; layer++) { - for (const auto& grid_loc_def : grid_def.layers.at(layer).loc_defs) { - //Fill in the block types according to the specification - //auto type = find_tile_type_by_name(grid_loc_def.block_type, device_ctx.physical_tile_types); - const VibInf* type = nullptr; - for (size_t vib_type = 0; vib_type < device_ctx.arch->vib_infs.size(); vib_type++) { - if (grid_loc_def.block_type == device_ctx.arch->vib_infs[vib_type].get_name()) { - type = &device_ctx.arch->vib_infs[vib_type]; - break; - } - } - - if (!type) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "Failed to find block type '%s' for grid location specification", - grid_loc_def.block_type.c_str()); - } - - seen_types.insert(type); - - t_formula_data vars; - vars.set_var_value("W", grid_width); - vars.set_var_value("H", grid_height); - vars.set_var_value("w", 1); - vars.set_var_value("h", 1); - - //Load the x specification - auto& xspec = grid_loc_def.x; - - VTR_ASSERT_MSG(!xspec.start_expr.empty(), "x start position must be specified"); - VTR_ASSERT_MSG(!xspec.end_expr.empty(), "x end position must be specified"); - VTR_ASSERT_MSG(!xspec.incr_expr.empty(), "x increment must be specified"); - VTR_ASSERT_MSG(!xspec.repeat_expr.empty(), "x repeat must be specified"); - - size_t startx = p.parse_formula(xspec.start_expr, vars); - size_t endx = p.parse_formula(xspec.end_expr, vars); - size_t incrx = p.parse_formula(xspec.incr_expr, vars); - size_t repeatx = p.parse_formula(xspec.repeat_expr, vars); - - //Load the y specification - auto& yspec = grid_loc_def.y; - - VTR_ASSERT_MSG(!yspec.start_expr.empty(), "y start position must be specified"); - VTR_ASSERT_MSG(!yspec.end_expr.empty(), "y end position must be specified"); - VTR_ASSERT_MSG(!yspec.incr_expr.empty(), "y increment must be specified"); - VTR_ASSERT_MSG(!yspec.repeat_expr.empty(), "y repeat must be specified"); - - size_t starty = p.parse_formula(yspec.start_expr, vars); - size_t endy = p.parse_formula(yspec.end_expr, vars); - size_t incry = p.parse_formula(yspec.incr_expr, vars); - size_t repeaty = p.parse_formula(yspec.repeat_expr, vars); - - //Check start against the device dimensions - // Start locations outside the device will never create block instances - if (startx > grid_width - 1) { - if (warn_out_of_range) { - VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", - type->get_name(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); - } - continue; //No instances will be created - } - - if (starty > grid_height - 1) { - if (warn_out_of_range) { - VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", - type->get_name(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); - } - continue; //No instances will be created - } - - //Check end against the device dimensions - if (endx > grid_width - 1) { - if (warn_out_of_range) { - VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", - type->get_name(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); - } - } - - if (endy > grid_height - 1) { - if (warn_out_of_range) { - VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", - type->get_name(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); - } - } - - //The end must fall after (or equal) to the start - if (endx < startx) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", - xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->get_name()); - } - - if (endy < starty) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", - yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->get_name()); - } - - //The minimum increment is the block dimension - //VTR_ASSERT(type->width > 0); - if (incrx < 1/*size_t(type->width)*/) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "Grid location specification incrx for block type '%s' must be at least" - " block width (%d) to avoid overlapping instances (was %s = %d)", - type->get_name(), 1, xspec.incr_expr.c_str(), incrx); - } - - //VTR_ASSERT(type->height > 0); - if (incry < 1/*size_t(type->height)*/) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "Grid location specification incry for block type '%s' must be at least" - " block height (%d) to avoid overlapping instances (was %s = %d)", - type->get_name(), 1, yspec.incr_expr.c_str(), incry); - } - - //The minimum repeat is the region dimension - size_t region_width = endx - startx + 1; //+1 since start/end are both inclusive - if (repeatx < region_width) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "Grid location specification repeatx for block type '%s' must be at least" - " the region width (%d) to avoid overlapping instances (was %s = %d)", - type->get_name(), region_width, xspec.repeat_expr.c_str(), repeatx); - } - - size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive - if (repeaty < region_height) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "Grid location specification repeaty for block type '%s' must be at least" - " the region height (%d) to avoid overlapping instances (was %s = %d)", - type->get_name(), region_height, xspec.repeat_expr.c_str(), repeaty); - } - - //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", - // type->name, grid_loc_def.priority, - // xspec.start_expr.c_str(), startx, xspec.end_expr.c_str(), endx, - // yspec.start_expr.c_str(), starty, yspec.end_expr.c_str(), endy); - - size_t x_end = 0; - for (size_t kx = 0; x_end < grid_width; ++kx) { //Repeat in x direction - size_t x_start = startx + kx * repeatx; - x_end = endx + kx * repeatx; - - size_t y_end = 0; - for (size_t ky = 0; y_end < grid_height; ++ky) { //Repeat in y direction - size_t y_start = starty + ky * repeaty; - y_end = endy + ky * repeaty; - - size_t x_max = std::min(x_end, grid_width - 1); - size_t y_max = std::min(y_end, grid_height - 1); - - //Fill in the region - for (size_t x = x_start; x <= x_max; x += incrx) { - for (size_t y = y_start; y <= y_max; y += incry) { - set_vib_grid_block_type(grid_loc_def.priority, - type, - layer, x, y, - vib_grid, grid_priorities, - grid_loc_def.meta); - } - } - } - } - } - } - - //Warn if any types were not specified in the grid layout - // for (auto const& type : device_ctx.physical_tile_types) { - // if (&type == empty_type) continue; //Don't worry if empty hasn't been specified - - // if (!seen_types.count(&type)) { - // VTR_LOG_WARN("Block type '%s' was not specified in device grid layout\n", - // type.name); - // } - // } - - // auto device_grid = DeviceGrid(grid_def.name, grid, limiting_resources); - - // CheckGrid(device_grid); - - return vib_grid; -} +// ///@brief Build the specified device grid +// static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range) { +// if (grid_def.grid_type == VibGridDefType::VIB_FIXED) { +// if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { +// VPR_FATAL_ERROR(VPR_ERROR_OTHER, +// "Requested grid size (%zu%zu) does not match fixed device size (%dx%d)", +// grid_width, grid_height, grid_def.width, grid_def.height); +// } +// } + +// auto& device_ctx = g_vpr_ctx.device(); + +// //Initialize the grid and each location priority based on available dies in the architecture file +// vtr::NdMatrix vib_grid; +// vtr::NdMatrix grid_priorities; +// int num_layers = (int)grid_def.layers.size(); +// vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); + +// //Track the current priority for each grid location +// // Note that we initialize it to the lowest (i.e. most negative) possible value, so +// // any user-specified priority will override the default empty grid +// grid_priorities.resize(std::array{(size_t)num_layers, grid_width, grid_height}, std::numeric_limits::lowest()); + +// //Initialize the device to all empty blocks +// const VibInf* empty_type = nullptr; +// //VTR_ASSERT(empty_type != nullptr); +// for (int layer = 0; layer < num_layers; ++layer) { +// for (size_t x = 0; x < grid_width; ++x) { +// for (size_t y = 0; y < grid_height; ++y) { +// set_vib_grid_block_type(std::numeric_limits::lowest() + 1, //+1 so it overrides without warning +// empty_type, +// layer, x, y, +// vib_grid, grid_priorities); +// } +// } +// } + +// FormulaParser p; +// std::set seen_types; +// for (int layer = 0; layer < num_layers; layer++) { +// for (const auto& grid_loc_def : grid_def.layers.at(layer).loc_defs) { +// //Fill in the block types according to the specification +// //auto type = find_tile_type_by_name(grid_loc_def.block_type, device_ctx.physical_tile_types); +// const VibInf* type = nullptr; +// for (size_t vib_type = 0; vib_type < device_ctx.arch->vib_infs.size(); vib_type++) { +// if (grid_loc_def.block_type == device_ctx.arch->vib_infs[vib_type].get_name()) { +// type = &device_ctx.arch->vib_infs[vib_type]; +// break; +// } +// } + +// if (!type) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Failed to find block type '%s' for grid location specification", +// grid_loc_def.block_type.c_str()); +// } + +// seen_types.insert(type); + +// t_formula_data vars; +// vars.set_var_value("W", grid_width); +// vars.set_var_value("H", grid_height); +// vars.set_var_value("w", 1); +// vars.set_var_value("h", 1); + +// //Load the x specification +// auto& xspec = grid_loc_def.x; + +// VTR_ASSERT_MSG(!xspec.start_expr.empty(), "x start position must be specified"); +// VTR_ASSERT_MSG(!xspec.end_expr.empty(), "x end position must be specified"); +// VTR_ASSERT_MSG(!xspec.incr_expr.empty(), "x increment must be specified"); +// VTR_ASSERT_MSG(!xspec.repeat_expr.empty(), "x repeat must be specified"); + +// size_t startx = p.parse_formula(xspec.start_expr, vars); +// size_t endx = p.parse_formula(xspec.end_expr, vars); +// size_t incrx = p.parse_formula(xspec.incr_expr, vars); +// size_t repeatx = p.parse_formula(xspec.repeat_expr, vars); + +// //Load the y specification +// auto& yspec = grid_loc_def.y; + +// VTR_ASSERT_MSG(!yspec.start_expr.empty(), "y start position must be specified"); +// VTR_ASSERT_MSG(!yspec.end_expr.empty(), "y end position must be specified"); +// VTR_ASSERT_MSG(!yspec.incr_expr.empty(), "y increment must be specified"); +// VTR_ASSERT_MSG(!yspec.repeat_expr.empty(), "y repeat must be specified"); + +// size_t starty = p.parse_formula(yspec.start_expr, vars); +// size_t endy = p.parse_formula(yspec.end_expr, vars); +// size_t incry = p.parse_formula(yspec.incr_expr, vars); +// size_t repeaty = p.parse_formula(yspec.repeat_expr, vars); + +// //Check start against the device dimensions +// // Start locations outside the device will never create block instances +// if (startx > grid_width - 1) { +// if (warn_out_of_range) { +// VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", +// type->get_name(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); +// } +// continue; //No instances will be created +// } + +// if (starty > grid_height - 1) { +// if (warn_out_of_range) { +// VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", +// type->get_name(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); +// } +// continue; //No instances will be created +// } + +// //Check end against the device dimensions +// if (endx > grid_width - 1) { +// if (warn_out_of_range) { +// VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", +// type->get_name(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); +// } +// } + +// if (endy > grid_height - 1) { +// if (warn_out_of_range) { +// VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", +// type->get_name(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); +// } +// } + +// //The end must fall after (or equal) to the start +// if (endx < startx) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", +// xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->get_name()); +// } + +// if (endy < starty) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", +// yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->get_name()); +// } + +// //The minimum increment is the block dimension +// //VTR_ASSERT(type->width > 0); +// if (incrx < 1/*size_t(type->width)*/) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification incrx for block type '%s' must be at least" +// " block width (%d) to avoid overlapping instances (was %s = %d)", +// type->get_name(), 1, xspec.incr_expr.c_str(), incrx); +// } + +// //VTR_ASSERT(type->height > 0); +// if (incry < 1/*size_t(type->height)*/) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification incry for block type '%s' must be at least" +// " block height (%d) to avoid overlapping instances (was %s = %d)", +// type->get_name(), 1, yspec.incr_expr.c_str(), incry); +// } + +// //The minimum repeat is the region dimension +// size_t region_width = endx - startx + 1; //+1 since start/end are both inclusive +// if (repeatx < region_width) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification repeatx for block type '%s' must be at least" +// " the region width (%d) to avoid overlapping instances (was %s = %d)", +// type->get_name(), region_width, xspec.repeat_expr.c_str(), repeatx); +// } + +// size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive +// if (repeaty < region_height) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification repeaty for block type '%s' must be at least" +// " the region height (%d) to avoid overlapping instances (was %s = %d)", +// type->get_name(), region_height, xspec.repeat_expr.c_str(), repeaty); +// } + +// //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", +// // type->name, grid_loc_def.priority, +// // xspec.start_expr.c_str(), startx, xspec.end_expr.c_str(), endx, +// // yspec.start_expr.c_str(), starty, yspec.end_expr.c_str(), endy); + +// size_t x_end = 0; +// for (size_t kx = 0; x_end < grid_width; ++kx) { //Repeat in x direction +// size_t x_start = startx + kx * repeatx; +// x_end = endx + kx * repeatx; + +// size_t y_end = 0; +// for (size_t ky = 0; y_end < grid_height; ++ky) { //Repeat in y direction +// size_t y_start = starty + ky * repeaty; +// y_end = endy + ky * repeaty; + +// size_t x_max = std::min(x_end, grid_width - 1); +// size_t y_max = std::min(y_end, grid_height - 1); + +// //Fill in the region +// for (size_t x = x_start; x <= x_max; x += incrx) { +// for (size_t y = y_start; y <= y_max; y += incry) { +// set_vib_grid_block_type(grid_loc_def.priority, +// type, +// layer, x, y, +// vib_grid, grid_priorities); +// } +// } +// } +// } +// } +// } + +// //Warn if any types were not specified in the grid layout +// // for (auto const& type : device_ctx.physical_tile_types) { +// // if (&type == empty_type) continue; //Don't worry if empty hasn't been specified + +// // if (!seen_types.count(&type)) { +// // VTR_LOG_WARN("Block type '%s' was not specified in device grid layout\n", +// // type.name); +// // } +// // } + +// auto vib_device_grid = VibDeviceGrid(grid_def.name, vib_grid); + +// // CheckGrid(device_grid); + +// return vib_device_grid; +// } static void set_grid_block_type(int priority, const t_physical_tile_type* type, @@ -951,146 +949,145 @@ static void set_grid_block_type(int priority, } } -static void set_vib_grid_block_type(int priority, - const VibInf* type, - int layer_num, - size_t x_root, - size_t y_root, - vtr::NdMatrix& vib_grid, - vtr::NdMatrix& grid_priorities, - const t_metadata_dict* meta) { - struct TypeLocation { - TypeLocation(size_t x_val, size_t y_val, const VibInf* type_val, int priority_val) - : x(x_val) - , y(y_val) - , type(type_val) - , priority(priority_val) {} - size_t x; - size_t y; - const VibInf* type; - int priority; - - bool operator<(const TypeLocation& rhs) const { - return x < rhs.x || y < rhs.y || type < rhs.type; - } - }; - - //Collect locations effected by this block - std::set target_locations; - for (size_t x = x_root; x < x_root + 1; ++x) { - for (size_t y = y_root; y < y_root + 1; ++y) { - target_locations.insert(TypeLocation(x, y, vib_grid[layer_num][x][y], grid_priorities[layer_num][x][y])); - } - } - - //Record the highest priority of all effected locations - auto iter = target_locations.begin(); - TypeLocation max_priority_type_loc = *iter; - for (; iter != target_locations.end(); ++iter) { - if (iter->priority > max_priority_type_loc.priority) { - max_priority_type_loc = *iter; - } - } - - if (priority < max_priority_type_loc.priority) { - //Lower priority, do not override -#ifdef VERBOSE - VTR_LOG("Not creating block '%s' at (%zu,%zu) since overlaps block '%s' at (%zu,%zu) with higher priority (%d > %d)\n", - type->name, x_root, y_root, max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, - max_priority_type_loc.priority, priority); -#endif - return; - } - - if (priority == max_priority_type_loc.priority) { - //Ambiguous case where current grid block and new specification have equal priority - // - //We arbitrarily decide to take the 'last applied' wins approach, and warn the user - //about the potential ambiguity - VTR_LOG_WARN( - "Ambiguous block type specification at grid location (%zu,%zu)." - " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." - " The last specification will apply.\n", - x_root, y_root, - max_priority_type_loc.type->get_name(), max_priority_type_loc.x, max_priority_type_loc.y, - priority, type->get_name()); - } - - //Mark all the grid tiles 'covered' by this block with the appropriate type - //and width/height offsets - std::set root_blocks_to_rip_up; - auto& device_ctx = g_vpr_ctx.device(); - for (size_t x = x_root; x < x_root + 1; ++x) { - VTR_ASSERT(x < vib_grid.end_index(1)); - - //size_t x_offset = x - x_root; - for (size_t y = y_root; y < y_root + 1; ++y) { - VTR_ASSERT(y < vib_grid.end_index(2)); - //size_t y_offset = y - y_root; - - auto& grid_tile = vib_grid[layer_num][x][y]; - VTR_ASSERT(grid_priorities[layer_num][x][y] <= priority); - - if (grid_tile != nullptr - //&& grid_tile.type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE - ) { - //We are overriding a non-empty block, we need to be careful - //to ensure we remove any blocks which will be invalidated when we - //overwrite part of their locations - - size_t orig_root_x = x; - size_t orig_root_y = y; - - root_blocks_to_rip_up.insert(TypeLocation(orig_root_x, - orig_root_y, - vib_grid[layer_num][x][y], - grid_priorities[layer_num][x][y])); - } - - vib_grid[layer_num][x][y] = type; - //grid[layer_num][x][y].width_offset = x_offset; - //grid[layer_num][x][y].height_offset = y_offset; - //grid[layer_num][x][y].meta = meta; - - grid_priorities[layer_num][x][y] = priority; - } - } - - //Rip-up any invalidated blocks - for (auto invalidated_root : root_blocks_to_rip_up) { - //Mark all the grid locations used by this root block as empty - for (size_t x = invalidated_root.x; x < invalidated_root.x + 1; ++x) { - int x_offset = x - invalidated_root.x; - for (size_t y = invalidated_root.y; y < invalidated_root.y + 1; ++y) { - int y_offset = y - invalidated_root.y; - - if (vib_grid[layer_num][x][y] == invalidated_root.type - && 0 == x_offset - && 0 == y_offset) { - //This is a left-over invalidated block, mark as empty - // Note: that we explicitly check the type and offsets, since the original block - // may have been completely overwritten, and we don't want to change anything - // in that case - //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->width == 1); - //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->height == 1); - -#ifdef VERBOSE - VTR_LOG("Ripping up block '%s' at (%d,%d) offset (%d,%d). Overlapped by '%s' at (%d,%d)\n", - invalidated_root.type->name, invalidated_root.x, invalidated_root.y, - x_offset, y_offset, - type->name, x_root, y_root); -#endif - - vib_grid[layer_num][x][y] = nullptr; - //grid[layer_num][x][y].width_offset = 0; - //grid[layer_num][x][y].height_offset = 0; - - grid_priorities[layer_num][x][y] = std::numeric_limits::lowest(); - } - } - } - } -} +// static void set_vib_grid_block_type(int priority, +// const VibInf* type, +// int layer_num, +// size_t x_root, +// size_t y_root, +// vtr::NdMatrix& vib_grid, +// vtr::NdMatrix& grid_priorities) { +// struct TypeLocation { +// TypeLocation(size_t x_val, size_t y_val, const VibInf* type_val, int priority_val) +// : x(x_val) +// , y(y_val) +// , type(type_val) +// , priority(priority_val) {} +// size_t x; +// size_t y; +// const VibInf* type; +// int priority; + +// bool operator<(const TypeLocation& rhs) const { +// return x < rhs.x || y < rhs.y || type < rhs.type; +// } +// }; + +// //Collect locations effected by this block +// std::set target_locations; +// for (size_t x = x_root; x < x_root + 1; ++x) { +// for (size_t y = y_root; y < y_root + 1; ++y) { +// target_locations.insert(TypeLocation(x, y, vib_grid[layer_num][x][y], grid_priorities[layer_num][x][y])); +// } +// } + +// //Record the highest priority of all effected locations +// auto iter = target_locations.begin(); +// TypeLocation max_priority_type_loc = *iter; +// for (; iter != target_locations.end(); ++iter) { +// if (iter->priority > max_priority_type_loc.priority) { +// max_priority_type_loc = *iter; +// } +// } + +// if (priority < max_priority_type_loc.priority) { +// //Lower priority, do not override +// #ifdef VERBOSE +// VTR_LOG("Not creating block '%s' at (%zu,%zu) since overlaps block '%s' at (%zu,%zu) with higher priority (%d > %d)\n", +// type->name, x_root, y_root, max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, +// max_priority_type_loc.priority, priority); +// #endif +// return; +// } + +// if (priority == max_priority_type_loc.priority) { +// //Ambiguous case where current grid block and new specification have equal priority +// // +// //We arbitrarily decide to take the 'last applied' wins approach, and warn the user +// //about the potential ambiguity +// VTR_LOG_WARN( +// "Ambiguous block type specification at grid location (%zu,%zu)." +// " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." +// " The last specification will apply.\n", +// x_root, y_root, +// max_priority_type_loc.type->get_name(), max_priority_type_loc.x, max_priority_type_loc.y, +// priority, type->get_name()); +// } + +// //Mark all the grid tiles 'covered' by this block with the appropriate type +// //and width/height offsets +// std::set root_blocks_to_rip_up; +// auto& device_ctx = g_vpr_ctx.device(); +// for (size_t x = x_root; x < x_root + 1; ++x) { +// VTR_ASSERT(x < vib_grid.end_index(1)); + +// //size_t x_offset = x - x_root; +// for (size_t y = y_root; y < y_root + 1; ++y) { +// VTR_ASSERT(y < vib_grid.end_index(2)); +// //size_t y_offset = y - y_root; + +// auto& grid_tile = vib_grid[layer_num][x][y]; +// VTR_ASSERT(grid_priorities[layer_num][x][y] <= priority); + +// if (grid_tile != nullptr +// //&& grid_tile.type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE +// ) { +// //We are overriding a non-empty block, we need to be careful +// //to ensure we remove any blocks which will be invalidated when we +// //overwrite part of their locations + +// size_t orig_root_x = x; +// size_t orig_root_y = y; + +// root_blocks_to_rip_up.insert(TypeLocation(orig_root_x, +// orig_root_y, +// vib_grid[layer_num][x][y], +// grid_priorities[layer_num][x][y])); +// } + +// vib_grid[layer_num][x][y] = type; +// //grid[layer_num][x][y].width_offset = x_offset; +// //grid[layer_num][x][y].height_offset = y_offset; +// //grid[layer_num][x][y].meta = meta; + +// grid_priorities[layer_num][x][y] = priority; +// } +// } + +// //Rip-up any invalidated blocks +// for (auto invalidated_root : root_blocks_to_rip_up) { +// //Mark all the grid locations used by this root block as empty +// for (size_t x = invalidated_root.x; x < invalidated_root.x + 1; ++x) { +// int x_offset = x - invalidated_root.x; +// for (size_t y = invalidated_root.y; y < invalidated_root.y + 1; ++y) { +// int y_offset = y - invalidated_root.y; + +// if (vib_grid[layer_num][x][y] == invalidated_root.type +// && 0 == x_offset +// && 0 == y_offset) { +// //This is a left-over invalidated block, mark as empty +// // Note: that we explicitly check the type and offsets, since the original block +// // may have been completely overwritten, and we don't want to change anything +// // in that case +// //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->width == 1); +// //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->height == 1); + +// #ifdef VERBOSE +// VTR_LOG("Ripping up block '%s' at (%d,%d) offset (%d,%d). Overlapped by '%s' at (%d,%d)\n", +// invalidated_root.type->name, invalidated_root.x, invalidated_root.y, +// x_offset, y_offset, +// type->name, x_root, y_root); +// #endif + +// vib_grid[layer_num][x][y] = nullptr; +// //grid[layer_num][x][y].width_offset = 0; +// //grid[layer_num][x][y].height_offset = 0; + +// grid_priorities[layer_num][x][y] = std::numeric_limits::lowest(); +// } +// } +// } +// } +// } ///@brief Check grid is valid static void CheckGrid(const DeviceGrid& grid) { From 463bdd08a399901e61f8282096d32339a20c34b5 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:36:26 +0800 Subject: [PATCH 385/453] Update SetupGrid.h --- vpr/src/base/SetupGrid.h | 1 - 1 file changed, 1 deletion(-) diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 8cb2fee86d0..53b4cdbf71d 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -24,7 +24,6 @@ DeviceGrid create_device_grid(const std::string& layout_name, ///@brief Find the device close in size to the specified dimensions DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); -vtr::NdMatrix create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts); /** * @brief Calculate the device utilization From 6359b5c5174e955f35b88f090b414f4e2c7a1381 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:37:31 +0800 Subject: [PATCH 386/453] Create SetupVibGrid.cpp --- vpr/src/base/SetupVibGrid.cpp | 421 ++++++++++++++++++++++++++++++++++ 1 file changed, 421 insertions(+) create mode 100644 vpr/src/base/SetupVibGrid.cpp diff --git a/vpr/src/base/SetupVibGrid.cpp b/vpr/src/base/SetupVibGrid.cpp new file mode 100644 index 00000000000..9b26ed60d24 --- /dev/null +++ b/vpr/src/base/SetupVibGrid.cpp @@ -0,0 +1,421 @@ +#include +#include +#include +#include +#include + +#include "vtr_assert.h" +#include "vtr_math.h" +#include "vtr_log.h" + +#include "vpr_types.h" +#include "vpr_error.h" +#include "vpr_utils.h" + +#include "globals.h" +#include "SetupGrid.h" +#include "vtr_expr_eval.h" + +using vtr::FormulaParser; +using vtr::t_formula_data; + +static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range = true); + +static void set_vib_grid_block_type(int priority, + const VibInf* type, + int layer_num, + size_t x_root, + size_t y_root, + vtr::NdMatrix& vib_grid, + vtr::NdMatrix& grid_priorities); + +VibDeviceGrid create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts) { + if (layout_name == "auto") { + //We do not support auto layout now + // + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); + + } else { + //Use the specified device + + //Find the matching grid definition + auto cmp = [&](const t_vib_grid_def& grid_def) { + return grid_def.name == layout_name; + }; + + auto iter = std::find_if(vib_grid_layouts.begin(), vib_grid_layouts.end(), cmp); + if (iter == vib_grid_layouts.end()) { + //Not found + std::string valid_names; + for (size_t i = 0; i < vib_grid_layouts.size(); ++i) { + if (i != 0) { + valid_names += ", "; + } + valid_names += "'" + vib_grid_layouts[i].name + "'"; + } + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find grid layout named '%s' (valid grid layouts: %s)\n", layout_name.c_str(), valid_names.c_str()); + } + + return build_vib_device_grid(*iter, iter->width, iter->height); + } +} + +///@brief Build the specified device grid +static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range) { + if (grid_def.grid_type == VibGridDefType::VIB_FIXED) { + if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "Requested grid size (%zu%zu) does not match fixed device size (%dx%d)", + grid_width, grid_height, grid_def.width, grid_def.height); + } + } + + auto& device_ctx = g_vpr_ctx.device(); + + //Initialize the grid and each location priority based on available dies in the architecture file + vtr::NdMatrix vib_grid; + vtr::NdMatrix grid_priorities; + int num_layers = (int)grid_def.layers.size(); + vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); + + //Track the current priority for each grid location + // Note that we initialize it to the lowest (i.e. most negative) possible value, so + // any user-specified priority will override the default empty grid + grid_priorities.resize(std::array{(size_t)num_layers, grid_width, grid_height}, std::numeric_limits::lowest()); + + //Initialize the device to all empty blocks + const VibInf* empty_type = nullptr; + //VTR_ASSERT(empty_type != nullptr); + for (int layer = 0; layer < num_layers; ++layer) { + for (size_t x = 0; x < grid_width; ++x) { + for (size_t y = 0; y < grid_height; ++y) { + set_vib_grid_block_type(std::numeric_limits::lowest() + 1, //+1 so it overrides without warning + empty_type, + layer, x, y, + vib_grid, grid_priorities); + } + } + } + + FormulaParser p; + std::set seen_types; + for (int layer = 0; layer < num_layers; layer++) { + for (const auto& grid_loc_def : grid_def.layers.at(layer).loc_defs) { + //Fill in the block types according to the specification + //auto type = find_tile_type_by_name(grid_loc_def.block_type, device_ctx.physical_tile_types); + const VibInf* type = nullptr; + for (size_t vib_type = 0; vib_type < device_ctx.arch->vib_infs.size(); vib_type++) { + if (grid_loc_def.block_type == device_ctx.arch->vib_infs[vib_type].get_name()) { + type = &device_ctx.arch->vib_infs[vib_type]; + break; + } + } + + if (!type) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Failed to find block type '%s' for grid location specification", + grid_loc_def.block_type.c_str()); + } + + seen_types.insert(type); + + t_formula_data vars; + vars.set_var_value("W", grid_width); + vars.set_var_value("H", grid_height); + vars.set_var_value("w", 1); + vars.set_var_value("h", 1); + + //Load the x specification + auto& xspec = grid_loc_def.x; + + VTR_ASSERT_MSG(!xspec.start_expr.empty(), "x start position must be specified"); + VTR_ASSERT_MSG(!xspec.end_expr.empty(), "x end position must be specified"); + VTR_ASSERT_MSG(!xspec.incr_expr.empty(), "x increment must be specified"); + VTR_ASSERT_MSG(!xspec.repeat_expr.empty(), "x repeat must be specified"); + + size_t startx = p.parse_formula(xspec.start_expr, vars); + size_t endx = p.parse_formula(xspec.end_expr, vars); + size_t incrx = p.parse_formula(xspec.incr_expr, vars); + size_t repeatx = p.parse_formula(xspec.repeat_expr, vars); + + //Load the y specification + auto& yspec = grid_loc_def.y; + + VTR_ASSERT_MSG(!yspec.start_expr.empty(), "y start position must be specified"); + VTR_ASSERT_MSG(!yspec.end_expr.empty(), "y end position must be specified"); + VTR_ASSERT_MSG(!yspec.incr_expr.empty(), "y increment must be specified"); + VTR_ASSERT_MSG(!yspec.repeat_expr.empty(), "y repeat must be specified"); + + size_t starty = p.parse_formula(yspec.start_expr, vars); + size_t endy = p.parse_formula(yspec.end_expr, vars); + size_t incry = p.parse_formula(yspec.incr_expr, vars); + size_t repeaty = p.parse_formula(yspec.repeat_expr, vars); + + //Check start against the device dimensions + // Start locations outside the device will never create block instances + if (startx > grid_width - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", + type->get_name(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); + } + continue; //No instances will be created + } + + if (starty > grid_height - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", + type->get_name(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); + } + continue; //No instances will be created + } + + //Check end against the device dimensions + if (endx > grid_width - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", + type->get_name(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); + } + } + + if (endy > grid_height - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", + type->get_name(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); + } + } + + //The end must fall after (or equal) to the start + if (endx < startx) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", + xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->get_name()); + } + + if (endy < starty) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", + yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->get_name()); + } + + //The minimum increment is the block dimension + //VTR_ASSERT(type->width > 0); + if (incrx < 1/*size_t(type->width)*/) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification incrx for block type '%s' must be at least" + " block width (%d) to avoid overlapping instances (was %s = %d)", + type->get_name(), 1, xspec.incr_expr.c_str(), incrx); + } + + //VTR_ASSERT(type->height > 0); + if (incry < 1/*size_t(type->height)*/) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification incry for block type '%s' must be at least" + " block height (%d) to avoid overlapping instances (was %s = %d)", + type->get_name(), 1, yspec.incr_expr.c_str(), incry); + } + + //The minimum repeat is the region dimension + size_t region_width = endx - startx + 1; //+1 since start/end are both inclusive + if (repeatx < region_width) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification repeatx for block type '%s' must be at least" + " the region width (%d) to avoid overlapping instances (was %s = %d)", + type->get_name(), region_width, xspec.repeat_expr.c_str(), repeatx); + } + + size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive + if (repeaty < region_height) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification repeaty for block type '%s' must be at least" + " the region height (%d) to avoid overlapping instances (was %s = %d)", + type->get_name(), region_height, xspec.repeat_expr.c_str(), repeaty); + } + + //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", + // type->name, grid_loc_def.priority, + // xspec.start_expr.c_str(), startx, xspec.end_expr.c_str(), endx, + // yspec.start_expr.c_str(), starty, yspec.end_expr.c_str(), endy); + + size_t x_end = 0; + for (size_t kx = 0; x_end < grid_width; ++kx) { //Repeat in x direction + size_t x_start = startx + kx * repeatx; + x_end = endx + kx * repeatx; + + size_t y_end = 0; + for (size_t ky = 0; y_end < grid_height; ++ky) { //Repeat in y direction + size_t y_start = starty + ky * repeaty; + y_end = endy + ky * repeaty; + + size_t x_max = std::min(x_end, grid_width - 1); + size_t y_max = std::min(y_end, grid_height - 1); + + //Fill in the region + for (size_t x = x_start; x <= x_max; x += incrx) { + for (size_t y = y_start; y <= y_max; y += incry) { + set_vib_grid_block_type(grid_loc_def.priority, + type, + layer, x, y, + vib_grid, grid_priorities); + } + } + } + } + } + } + + //Warn if any types were not specified in the grid layout + // for (auto const& type : device_ctx.physical_tile_types) { + // if (&type == empty_type) continue; //Don't worry if empty hasn't been specified + + // if (!seen_types.count(&type)) { + // VTR_LOG_WARN("Block type '%s' was not specified in device grid layout\n", + // type.name); + // } + // } + + auto vib_device_grid = VibDeviceGrid(grid_def.name, vib_grid); + + // CheckGrid(device_grid); + + return vib_device_grid; +} + +static void set_vib_grid_block_type(int priority, + const VibInf* type, + int layer_num, + size_t x_root, + size_t y_root, + vtr::NdMatrix& vib_grid, + vtr::NdMatrix& grid_priorities) { + struct TypeLocation { + TypeLocation(size_t x_val, size_t y_val, const VibInf* type_val, int priority_val) + : x(x_val) + , y(y_val) + , type(type_val) + , priority(priority_val) {} + size_t x; + size_t y; + const VibInf* type; + int priority; + + bool operator<(const TypeLocation& rhs) const { + return x < rhs.x || y < rhs.y || type < rhs.type; + } + }; + + //Collect locations effected by this block + std::set target_locations; + for (size_t x = x_root; x < x_root + 1; ++x) { + for (size_t y = y_root; y < y_root + 1; ++y) { + target_locations.insert(TypeLocation(x, y, vib_grid[layer_num][x][y], grid_priorities[layer_num][x][y])); + } + } + + //Record the highest priority of all effected locations + auto iter = target_locations.begin(); + TypeLocation max_priority_type_loc = *iter; + for (; iter != target_locations.end(); ++iter) { + if (iter->priority > max_priority_type_loc.priority) { + max_priority_type_loc = *iter; + } + } + + if (priority < max_priority_type_loc.priority) { + //Lower priority, do not override +#ifdef VERBOSE + VTR_LOG("Not creating block '%s' at (%zu,%zu) since overlaps block '%s' at (%zu,%zu) with higher priority (%d > %d)\n", + type->name, x_root, y_root, max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, + max_priority_type_loc.priority, priority); +#endif + return; + } + + if (priority == max_priority_type_loc.priority) { + //Ambiguous case where current grid block and new specification have equal priority + // + //We arbitrarily decide to take the 'last applied' wins approach, and warn the user + //about the potential ambiguity + VTR_LOG_WARN( + "Ambiguous block type specification at grid location (%zu,%zu)." + " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." + " The last specification will apply.\n", + x_root, y_root, + max_priority_type_loc.type->get_name(), max_priority_type_loc.x, max_priority_type_loc.y, + priority, type->get_name()); + } + + //Mark all the grid tiles 'covered' by this block with the appropriate type + //and width/height offsets + std::set root_blocks_to_rip_up; + auto& device_ctx = g_vpr_ctx.device(); + for (size_t x = x_root; x < x_root + 1; ++x) { + VTR_ASSERT(x < vib_grid.end_index(1)); + + //size_t x_offset = x - x_root; + for (size_t y = y_root; y < y_root + 1; ++y) { + VTR_ASSERT(y < vib_grid.end_index(2)); + //size_t y_offset = y - y_root; + + auto& grid_tile = vib_grid[layer_num][x][y]; + VTR_ASSERT(grid_priorities[layer_num][x][y] <= priority); + + if (grid_tile != nullptr + //&& grid_tile.type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE + ) { + //We are overriding a non-empty block, we need to be careful + //to ensure we remove any blocks which will be invalidated when we + //overwrite part of their locations + + size_t orig_root_x = x; + size_t orig_root_y = y; + + root_blocks_to_rip_up.insert(TypeLocation(orig_root_x, + orig_root_y, + vib_grid[layer_num][x][y], + grid_priorities[layer_num][x][y])); + } + + vib_grid[layer_num][x][y] = type; + //grid[layer_num][x][y].width_offset = x_offset; + //grid[layer_num][x][y].height_offset = y_offset; + //grid[layer_num][x][y].meta = meta; + + grid_priorities[layer_num][x][y] = priority; + } + } + + //Rip-up any invalidated blocks + for (auto invalidated_root : root_blocks_to_rip_up) { + //Mark all the grid locations used by this root block as empty + for (size_t x = invalidated_root.x; x < invalidated_root.x + 1; ++x) { + int x_offset = x - invalidated_root.x; + for (size_t y = invalidated_root.y; y < invalidated_root.y + 1; ++y) { + int y_offset = y - invalidated_root.y; + + if (vib_grid[layer_num][x][y] == invalidated_root.type + && 0 == x_offset + && 0 == y_offset) { + //This is a left-over invalidated block, mark as empty + // Note: that we explicitly check the type and offsets, since the original block + // may have been completely overwritten, and we don't want to change anything + // in that case + //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->width == 1); + //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->height == 1); + +#ifdef VERBOSE + VTR_LOG("Ripping up block '%s' at (%d,%d) offset (%d,%d). Overlapped by '%s' at (%d,%d)\n", + invalidated_root.type->name, invalidated_root.x, invalidated_root.y, + x_offset, y_offset, + type->name, x_root, y_root); +#endif + + vib_grid[layer_num][x][y] = nullptr; + //grid[layer_num][x][y].width_offset = 0; + //grid[layer_num][x][y].height_offset = 0; + + grid_priorities[layer_num][x][y] = std::numeric_limits::lowest(); + } + } + } + } +} From c0a273608e40ee45316be87376cd00274d1ec770 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:38:01 +0800 Subject: [PATCH 387/453] Create SetupVibGrid.h --- vpr/src/base/SetupVibGrid.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 vpr/src/base/SetupVibGrid.h diff --git a/vpr/src/base/SetupVibGrid.h b/vpr/src/base/SetupVibGrid.h new file mode 100644 index 00000000000..ddb1f8b7697 --- /dev/null +++ b/vpr/src/base/SetupVibGrid.h @@ -0,0 +1,17 @@ +#ifndef SETUPVIBGRID_H +#define SETUPVIBGRID_H + +/** + * @file + * @author Jason Luu + * @date October 8, 2008 + * + * @brief Initializes and allocates the physical logic block grid for VPR. + */ + +#include +#include "physical_types.h" + +VibDeviceGrid create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts); + +#endif From 52edaf9bfe4ad83728ead85998de0e5521876480 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:38:40 +0800 Subject: [PATCH 388/453] Update vpr_api.cpp --- vpr/src/base/vpr_api.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index e18f32d5360..23debde995b 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -35,6 +35,7 @@ #include "pack.h" #include "place.h" #include "SetupGrid.h" +#include "SetupVibGrid.h" #include "setup_clocks.h" #include "setup_noc.h" #include "read_xml_noc_traffic_flows_file.h" From 60bc5a04a043a162d542acbb7a48006374648724 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:39:16 +0800 Subject: [PATCH 389/453] Update vpr_context.h --- vpr/src/base/vpr_context.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index bedc15755cc..aa3863ccc9e 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -143,7 +143,7 @@ struct DeviceContext : public Context { */ DeviceGrid grid; - vtr::NdMatrix vib_grid; + VibDeviceGrid vib_grid; /* * Empty types From b9d587edb50d2f5b50ad4d753ee8353a4e837a25 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:39:50 +0800 Subject: [PATCH 390/453] Update rr_graph.xsd --- libs/librrgraph/src/io/rr_graph.xsd | 1 + 1 file changed, 1 insertion(+) diff --git a/libs/librrgraph/src/io/rr_graph.xsd b/libs/librrgraph/src/io/rr_graph.xsd index 17c680b2ee5..8894d96fab2 100644 --- a/libs/librrgraph/src/io/rr_graph.xsd +++ b/libs/librrgraph/src/io/rr_graph.xsd @@ -233,6 +233,7 @@ + From 5ad23297f820902a8a9e319834b565842bd55bd8 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:40:34 +0800 Subject: [PATCH 391/453] Update tileable_rr_graph_edge_builder.cpp --- .../tileable_rr_graph_edge_builder.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index a4b20285a4d..babd9430563 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -105,7 +105,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, @@ -127,18 +127,18 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, std::vector>>> medium_mux_name2medium_index; if (is_vib_arch) { - medium_mux_name2medium_index.resize(vib_grid.dim_size(0)); - for (size_t i_layer = 0; i_layer < vib_grid.dim_size(0); i_layer++) { - medium_mux_name2medium_index[i_layer].resize(vib_grid.dim_size(1)); + medium_mux_name2medium_index.resize(vib_grid.get_num_layers()); + for (size_t i_layer = 0; i_layer < vib_grid.get_num_layers(); i_layer++) { + medium_mux_name2medium_index[i_layer].resize(vib_grid.width()); - for (size_t ix = 0; ix < vib_grid.dim_size(1); ix++) { - medium_mux_name2medium_index[i_layer][ix].resize(vib_grid.dim_size(2)); + for (size_t ix = 0; ix < vib_grid.width(); ix++) { + medium_mux_name2medium_index[i_layer][ix].resize(vib_grid.height()); - for (size_t iy = 0; iy < vib_grid.dim_size(2); iy++) { + for (size_t iy = 0; iy < vib_grid.height(); iy++) { std::map mux_name_map; - for (size_t i_mux = 0; i_mux < vib_grid[i_layer][ix][iy]->get_first_stages().size(); i_mux++) { - mux_name_map.emplace(vib_grid[i_layer][ix][iy]->get_first_stages()[i_mux].mux_name, i_mux); + for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { + mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); } medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; } From cbcdf0e7d0faabb2abd4a312222428a3038a4853 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:41:40 +0800 Subject: [PATCH 392/453] Update tileable_rr_graph_edge_builder.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 0aa3b5a0310..2731949918f 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -25,7 +25,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, vtr::vector& rr_node_driver_switches, const DeviceGrid& grids, - const vtr::NdMatrix& vib_grid, + const VibDeviceGrid& vib_grid, const size_t& layer, const vtr::Point& device_chan_width, const std::vector& segment_inf, From 84faf4351557db3937d42bdec6f20b9db29c2f4e Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:42:43 +0800 Subject: [PATCH 393/453] Update rr_graph.cpp --- vpr/src/route/rr_graph.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 2c779f6bae1..d689c5695df 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1542,7 +1542,7 @@ static void build_rr_graph(const t_graph_type graph_type, rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); - const vtr::NdMatrix vib_grid; + const VibDeviceGrid vib_grid; check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, @@ -1638,7 +1638,7 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, rr_graph_builder.clear_temp_storage(); - const vtr::NdMatrix vib_grid; + const VibDeviceGrid vib_grid; check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, From 4e046ef0d6c6ca8c205e7ce58abaedf680ec0eba Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:44:46 +0800 Subject: [PATCH 394/453] Update rr_graph_uxsdcxx_serializer.h --- libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 348e9c4df4b..1af1a8a6ec4 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1837,7 +1837,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { read_rr_graph_filename_->assign(read_rr_graph_name_); if (do_check_rr_graph_) { - const vtr::NdMatrix vib_grid_; + const VibDeviceGrid vib_grid_; check_rr_graph(*rr_graph_, physical_tile_types_, *rr_indexed_data_, From 60bee8f6d179ae3d208ac68d6f2b01686a548bb9 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:45:32 +0800 Subject: [PATCH 395/453] Update overuse_report.cpp --- vpr/src/route/overuse_report.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index a7d550f2150..271cde2f59a 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -222,7 +222,7 @@ static void report_overused_ipin_opin(std::ostream& os, t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({grid_x, grid_y, grid_layer}); const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { - vib = device_ctx.vib_grid[grid_layer][grid_x][grid_y]; + vib = device_ctx.vib_grid.get_vib(grid_layer, grid_x, grid_y); } else { vib = nullptr; From 0b4cfc20108e6f778de48ea748cc471124fd44f2 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:46:05 +0800 Subject: [PATCH 396/453] Update router_lookahead_map.cpp --- vpr/src/route/router_lookahead_map.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 727292fce9c..00444c3748e 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -206,7 +206,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI rr_graph.node_layer(current_node)}); const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { - vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; + vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(current_node), rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node)); } else { vib = nullptr; From a182a7689fc79ea98da8ac7f3f1f3977637927d2 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:46:30 +0800 Subject: [PATCH 397/453] Update router_lookahead_map_utils.cpp --- vpr/src/route/router_lookahead_map_utils.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 03840a8565b..bf2a9585101 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -422,7 +422,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { int ptc = rr_graph.node_ptc_num(node_id); const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { - vib = device_ctx.vib_grid[sample_loc.layer_num][sample_loc.x][sample_loc.y]; + vib = device_ctx.vib_grid.get_vib(sample_loc.layer_num, sample_loc.x, sample_loc.y); } else { vib = nullptr; @@ -1042,7 +1042,7 @@ static void dijkstra_flood_to_wires(int itile, rr_graph.node_layer(next_node)}); const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { - vib = device_ctx.vib_grid[rr_graph.node_layer(next_node)][rr_graph.node_xlow(next_node)][rr_graph.node_ylow(next_node)]; + vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(next_node), rr_graph.node_xlow(next_node), rr_graph.node_ylow(next_node)); } else { vib = nullptr; @@ -1414,7 +1414,7 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, rr_graph.node_layer(child_node)}); const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { - vib = device_ctx.vib_grid[rr_graph.node_layer(child_node)][rr_graph.node_xlow(child_node)][rr_graph.node_ylow(child_node)]; + vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(child_node), rr_graph.node_xlow(child_node), rr_graph.node_ylow(child_node)); } else { vib = nullptr; From 6343061d7744693360014f4299dce29766fc17c4 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 4 Nov 2024 10:49:06 +0800 Subject: [PATCH 398/453] Update rr_gsb.h --- vpr/src/tileable_rr_graph/rr_gsb.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index fce23ac2415..bc4d9c0cb6a 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -117,6 +117,12 @@ class RRGSB { /* get a rr_node at a given side and track_id for a connection block */ RRNodeId get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + /* Get the number of MEDIUM rr_nodes */ + size_t get_num_medium_nodes() const; + + /* get a rr_node at a given ptc number */ + RRNodeId get_medium_node(const size_t& ptc) const; + int get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const; int get_chan_node_index(const e_side& node_side, const RRNodeId& node) const; @@ -130,6 +136,11 @@ class RRGSB { /* Check if the node exist in the opposite side of this Switch Block */ bool is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side) const; + bool is_opin_node(const RRNodeId& node) const; + bool is_ipin_node(const RRNodeId& node) const; + bool is_medium_node(const RRNodeId& node) const; + bool is_chan_node(const RRNodeId& node) const; + public: /* Accessors: to identify mirrors */ /* check if the connect block exists in the GSB */ bool is_cb_exist(const t_rr_type& cb_type) const; @@ -186,6 +197,9 @@ class RRGSB { void add_opin_node(const RRNodeId& node, const e_side& node_side); + /* Add a node to the medium_node_ */ + void add_medium_node(const RRNodeId& medium_node); + /* Sort all the incoming edges for routing channel rr_node */ void sort_chan_node_in_edges(const RRGraphView& rr_graph); /* Sort all the incoming edges for input pin rr_node */ @@ -269,6 +283,9 @@ class RRGSB { * Each CB may have OPINs from all sides */ std::array, NUM_2D_SIDES>, 2> cb_opin_node_; + + /* Medium Nodes Data */ + std::vector medium_node_; }; #endif From d0f15b1431f89bc21bcd930d9d841761734a6fde Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 12 Nov 2024 16:44:40 -0800 Subject: [PATCH 399/453] [lib] syntax --- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index b4ca4b73cfa..c82d0e73775 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -765,7 +765,7 @@ static std::pair ProcessInstanceString(pugi::xml_node Locations, int token_index = 0; auto token = tokens[token_index]; - if (token.type != TOKEN_STRING || 0 != strcmp(token.data, type->name)) { + if (token.type != TOKEN_STRING || 0 != strcmp(token.data, type->name.c_str())) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Wrong physical type name of the port: %s\n", pin_loc_string); } From 66927762c08e19053b164df696607521a559334f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 12 Nov 2024 16:57:54 -0800 Subject: [PATCH 400/453] [core] resolve conflicts --- vpr/src/route/rr_graph.cpp | 12 ++---------- vpr/src/route/rr_graph.h | 2 +- .../tileable_rr_graph/tileable_rr_graph_builder.cpp | 13 +++++-------- .../tileable_rr_graph/tileable_rr_graph_builder.h | 3 +-- 4 files changed, 9 insertions(+), 21 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 7ce84f5d8ea..2988494a98d 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -593,14 +593,6 @@ static void alloc_rr_switch_inf(RRGraphBuilder& rr_graph_builder, t_arch_switch_fanin& arch_switch_fanins, const std::map& arch_sw_map); -static void rr_graph_externals(const std::vector& segment_inf, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - int wire_to_rr_ipin_switch, - enum e_base_cost_type base_cost_type); - -static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); - static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, int* num_seg_details = nullptr); @@ -838,7 +830,7 @@ void create_rr_graph(const t_graph_type graph_type, det_routing_arch->R_minW_nmos, det_routing_arch->R_minW_pmos, router_opts.base_cost_type, - directs, directs.size(), + directs, &det_routing_arch->wire_to_rr_ipin_switch, det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ det_routing_arch->perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ @@ -4348,7 +4340,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * This data structure supplements the the info in the "directs" data structure * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one */ -static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { +t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { t_clb_to_clb_directs* clb_to_clb_directs; t_physical_tile_type_ptr physical_tile = nullptr; t_physical_tile_port tile_port; diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index 5c692aa800a..0d074f95bb8 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -62,7 +62,7 @@ void rr_graph_externals(const std::vector& segment_inf, int wire_to_rr_ipin_switch, enum e_base_cost_type base_cost_type); -t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch); +t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); std::vector> alloc_and_load_actual_fc(const std::vector& types, const int max_pins, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index 113927cc471..8b5a2ab6238 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -81,8 +81,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const float R_minW_nmos, const float R_minW_pmos, const enum e_base_cost_type& base_cost_type, - const t_direct_inf* directs, - const int& num_directs, + const std::vector& directs, int* wire_to_rr_ipin_switch, const bool& shrink_boundary, const bool& perimeter_cb, @@ -269,20 +268,18 @@ void build_tileable_unidir_rr_graph(const std::vector& typ ***********************************************************************/ /* Create data structure of direct-connections */ t_clb_to_clb_directs* clb_to_clb_directs = NULL; - if (num_directs > 0) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs, delayless_switch); + if (!directs.empty()) { + clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); } - std::vector arch_directs; std::vector clb2clb_directs; - for (int idirect = 0; idirect < num_directs; ++idirect) { - arch_directs.push_back(directs[idirect]); + for (size_t idirect = 0; idirect < directs.size(); ++idirect) { /* Sanity checks on rr switch id */ VTR_ASSERT(true == device_ctx.rr_graph.valid_switch(RRSwitchId(clb_to_clb_directs[idirect].switch_index))); clb2clb_directs.push_back(clb_to_clb_directs[idirect]); } build_rr_graph_direct_connections(device_ctx.rr_graph, device_ctx.rr_graph_builder, device_ctx.grid, 0, - arch_directs, clb2clb_directs); + directs, clb2clb_directs); /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h index f18a1ae93d9..2dd4d78b75e 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -26,8 +26,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ const float R_minW_nmos, const float R_minW_pmos, const enum e_base_cost_type& base_cost_type, - const t_direct_inf* directs, - const int& num_directs, + const std::vector& directs, int* wire_to_rr_ipin_switch, const bool& shrink_boundary, const bool& perimeter_cb, From 8178b71295d2579c38403529765c95432c44bd0c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 12 Nov 2024 19:31:27 -0800 Subject: [PATCH 401/453] [lib] clang syntax --- libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index c82d0e73775..381dd83fc3f 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -3624,7 +3624,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, //Missing archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", - SubTile->name, iinst, port.name, ipin); + SubTile->name.c_str(), iinst, port.name, ipin); } } } From 3bb906885be9fd510fbc7db4d9cf5d8bd739dbb0 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:48:27 +0800 Subject: [PATCH 402/453] Update tileable_rr_graph_node_builder.cpp --- .../tileable_rr_graph_node_builder.cpp | 24 +++++++------------ 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index be325cfe352..eec63682481 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -91,7 +91,7 @@ static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, for (size_t iy = 0; iy < grids.height(); ++iy) { const VibInf* vib = vib_grid.get_vib(layer, ix, iy); - if (vib == nullptr) { + if (!vib) { VTR_LOGF_ERROR(__FILE__, __LINE__, "VIB at (%d, %d) is EMPTY!\n", ix, iy); exit(1); @@ -371,8 +371,7 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& perimeter_cb, - const bool& through_channel, - const bool& is_vib_arch) { + const bool& through_channel) { /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); @@ -380,7 +379,7 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, /** * 1 Find number of rr nodes related to grids */ - if (is_vib_arch) + if (!vib_grid.is_empty()) num_rr_nodes_per_type[MEDIUM] = estimate_num_medium_rr_nodes(grids, vib_grid, layer); else num_rr_nodes_per_type[MEDIUM] = 0; @@ -442,8 +441,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& perimeter_cb, - const bool& through_channel, - const bool& is_vib_arch) { + const bool& through_channel) { VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, @@ -455,8 +453,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, device_grid_annotation, shrink_boundary, perimeter_cb, - through_channel, - is_vib_arch); + through_channel); /* Reserve the number of node to be memory efficient */ size_t num_nodes = 0; @@ -730,8 +727,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, const size_t& layer, const RRSwitchId& wire_to_ipin_switch, const RRSwitchId& delayless_switch, - const bool& perimeter_cb, - const bool& is_vib_arch) { + const bool& perimeter_cb) { for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { t_physical_tile_loc tile_loc(ix, iy, layer); @@ -802,7 +798,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, } } - if (is_vib_arch) { + if (!vib_grid.is_empty()) { /* Create medium nodes */ VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); for (size_t iy = 0; iy < grids.height(); ++iy) { @@ -1310,8 +1306,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& perimeter_cb, - const bool& through_channel, - const bool& is_vib_arch) { + const bool& through_channel) { /* Allocates and loads all the structures needed for fast lookups of the * * index of an rr_node. rr_node_indices is a matrix containing the index * * of the *first* rr_node at a given (i,j) location. */ @@ -1332,8 +1327,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, rr_rc_data, grids, vib_grid, layer, wire_to_ipin_switch, - delayless_switch, perimeter_cb, - is_vib_arch); + delayless_switch, perimeter_cb); load_chanx_rr_nodes_basic_info(rr_graph, rr_graph_builder, From be709d2a0d612a7e1c6de61ffc951b090ae0d99b Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:49:12 +0800 Subject: [PATCH 403/453] Update SetupVibGrid.cpp --- vpr/src/base/SetupVibGrid.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/base/SetupVibGrid.cpp b/vpr/src/base/SetupVibGrid.cpp index 9b26ed60d24..8892e7056f8 100644 --- a/vpr/src/base/SetupVibGrid.cpp +++ b/vpr/src/base/SetupVibGrid.cpp @@ -14,6 +14,7 @@ #include "globals.h" #include "SetupGrid.h" +#include "SetupVibGrid.h" #include "vtr_expr_eval.h" using vtr::FormulaParser; From d7d93c90e3dd3e86542be28f6e9b9c3b72bdc13d Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:49:50 +0800 Subject: [PATCH 404/453] Update tileable_rr_graph_node_builder.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h index 1c5643b4416..0dd69ac2aff 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -33,8 +33,7 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& perimeter_cb, - const bool& through_channel, - const bool& is_vib_arch); + const bool& through_channel); void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, @@ -53,7 +52,6 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, const DeviceGridAnnotation& device_grid_annotation, const bool& shrink_boundary, const bool& perimeter_cb, - const bool& through_channel, - const bool& is_vib_arch); + const bool& through_channel); #endif From 91960e2d588f315a1ba9d0e667c741f7dd3ff3f6 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:50:18 +0800 Subject: [PATCH 405/453] Update tileable_rr_graph_builder.cpp --- .../tileable_rr_graph/tileable_rr_graph_builder.cpp | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index ae8d3102777..12dc294eef7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -158,7 +158,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* Get vib grid */ const auto& vib_grid = device_ctx.vib_grid; - const bool is_vib_arch = !device_ctx.arch->vib_infs.empty(); + //const bool is_vib_arch = !device_ctx.arch->vib_infs.empty(); /************************ * Allocate the rr_nodes @@ -171,8 +171,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ device_grid_annotation, shrink_boundary, perimeter_cb, - through_channel, - is_vib_arch); + through_channel); /************************ * Create all the rr_nodes @@ -191,8 +190,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ device_grid_annotation, shrink_boundary, perimeter_cb, - through_channel, - is_vib_arch); + through_channel); /************************************************************************ * Create the connectivity of OPINs @@ -268,8 +266,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ perimeter_cb, opin2all_sides, concat_wire, wire_opposite_side, - delayless_rr_switch, - is_vib_arch); + delayless_rr_switch); /************************************************************************ * Build direction connection lists From 729ae804eb873e855e676e498a8e1e96d1254726 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:51:11 +0800 Subject: [PATCH 406/453] Update tileable_rr_graph_edge_builder.cpp --- .../tileable_rr_graph_edge_builder.cpp | 553 +++++++++++++----- 1 file changed, 421 insertions(+), 132 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index babd9430563..17a1c8cb9a5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -121,33 +121,291 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const bool& opin2all_sides, const bool& concat_wire, const bool& wire_opposite_side, - const RRSwitchId& delayless_switch, - const bool& is_vib_arch) { + const RRSwitchId& delayless_switch) { + + if (!vib_grid.is_empty()) { + build_rr_graph_vib_edges(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + grids, + vib_grid, + layer, + device_chan_width, + segment_inf, + segment_inf_x, + segment_inf_y, + Fc_in, + Fc_out, + sb_type, + Fs, + sb_subtype, + subFs, + perimeter_cb, + opin2all_sides, + concat_wire, + wire_opposite_side, + delayless_switch); + } + else { + build_rr_graph_regular_edges(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + grids, + layer, + device_chan_width, + segment_inf, + segment_inf_x, + segment_inf_y, + Fc_in, + Fc_out, + sb_type, + Fs, + sb_subtype, + subFs, + perimeter_cb, + opin2all_sides, + concat_wire, + wire_opposite_side); + } /* Create map from medium mux name to index */ - std::vector>>> medium_mux_name2medium_index; + // std::vector>>> medium_mux_name2medium_index; - if (is_vib_arch) { - medium_mux_name2medium_index.resize(vib_grid.get_num_layers()); - for (size_t i_layer = 0; i_layer < vib_grid.get_num_layers(); i_layer++) { - medium_mux_name2medium_index[i_layer].resize(vib_grid.width()); + // if (!vib_grid.is_empty()) { + // medium_mux_name2medium_index.resize(vib_grid.get_num_layers()); + // for (size_t i_layer = 0; i_layer < vib_grid.get_num_layers(); i_layer++) { + // medium_mux_name2medium_index[i_layer].resize(vib_grid.width()); - for (size_t ix = 0; ix < vib_grid.width(); ix++) { - medium_mux_name2medium_index[i_layer][ix].resize(vib_grid.height()); + // for (size_t ix = 0; ix < vib_grid.width(); ix++) { + // medium_mux_name2medium_index[i_layer][ix].resize(vib_grid.height()); - for (size_t iy = 0; iy < vib_grid.height(); iy++) { - std::map mux_name_map; + // for (size_t iy = 0; iy < vib_grid.height(); iy++) { + // std::map mux_name_map; - for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { - mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); - } - medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; - } - } - } + // for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { + // mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); + // } + // medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; + // } + // } + // } - } + // } + // size_t num_edges_to_create = 0; + // /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ + // build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + // build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + + // vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); + + // /* Go Switch Block by Switch Block */ + // for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { + // for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { + // //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); + + // vtr::Point gsb_coord(ix, iy); + + // /* adapt the bend_conn */ + // t_bend_track2track_map sb_bend_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + // sb_bend_conn = build_bend_track_to_track_map(grids, rr_graph_builder, rr_graph, + // device_chan_width, segment_inf, + // layer, gsb_coord, delayless_switch, rr_node_driver_switches); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + // if (!vib_grid.is_empty()) { + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord, medium_mux_name2medium_index); + // build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + + // rr_graph_builder.build_edges(true); + // } + // else { + // /* adapt the track_to_ipin_lookup for the GSB nodes */ + // t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + // track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); + + // /* adapt the opin_to_track_map for the GSB nodes */ + // t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + // opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + + // /* adapt the switch_block_conn for the GSB nodes */ + // t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + // sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + // sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, + // segment_inf); + + // /* Build edges for a GSB */ + // build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, + // sb_bend_conn, track2ipin_map, opin2track_map, + // sb_conn, rr_node_driver_switches, num_edges_to_create); + // /* Finish this GSB, go to the next*/ + // rr_graph_builder.build_edges(true); + // } + // } + // } + + // /* Process boundary */ + // if (!vib_grid.is_empty()) { + // size_t ix, iy; + // // process top boundary + // iy = gsb_range.y() + 1; // == grids.height() - 1 + // for (ix = 0; ix < gsb_range.x() + 1; ++ix) { + // vtr::Point actual_coord(ix, iy); + // vtr::Point gsb_coord(ix, iy - 1); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + // size_t edge_count = 0; + // for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + // for (auto to_node : iter->second) { + // rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + // edge_count++; + // } + // } + // num_edges_to_create += edge_count; + // //rr_graph_builder.build_edges(true); + + // } + + // // process right boundary + // ix = gsb_range.x() + 1; + // for (iy = 0; iy < gsb_range.y() + 1; ++iy) { + // vtr::Point actual_coord(ix, iy); + // vtr::Point gsb_coord(ix - 1, iy); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + // size_t edge_count = 0; + // for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + // for (auto to_node : iter->second) { + // rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + // edge_count++; + // } + // } + // num_edges_to_create += edge_count; + // //rr_graph_builder.build_edges(true); + + // } + + // // process right-top corner + // ix = gsb_range.x() + 1; + // iy = gsb_range.y() + 1; + + // vtr::Point actual_coord(ix, iy); + // vtr::Point gsb_coord(ix - 1, iy - 1); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + // size_t edge_count = 0; + // for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + // for (auto to_node : iter->second) { + // rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + // edge_count++; + // } + // } + // num_edges_to_create += edge_count; + // rr_graph_builder.build_edges(true); + // } +} + +/************************************************************************ + * Build direct edges for Grids * + ***********************************************************************/ +void build_rr_graph_direct_connections(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grids, + const size_t& layer, + const std::vector& directs, + const std::vector& clb_to_clb_directs) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids.get_physical_type(tile_loc))) { + continue; + } + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ((0 < grids.get_width_offset(tile_loc)) + || (0 < grids.get_height_offset(tile_loc))) { + continue; + } + vtr::Point from_grid_coordinate(ix, iy); + build_direct_connections_for_one_gsb(rr_graph, + rr_graph_builder, + grids, layer, + from_grid_coordinate, + directs, clb_to_clb_directs); + } + } +} + +void build_rr_graph_vib_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& perimeter_cb, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side, + const RRSwitchId& delayless_switch) { + /* Create map from medium mux name to index */ + // std::vector>>> medium_mux_name2medium_index; + // medium_mux_name2medium_index.resize(vib_grid.get_num_layers()); + // for (size_t i_layer = 0; i_layer < vib_grid.get_num_layers(); i_layer++) { + // medium_mux_name2medium_index[i_layer].resize(vib_grid.width()); + + // for (size_t ix = 0; ix < vib_grid.width(); ix++) { + // medium_mux_name2medium_index[i_layer][ix].resize(vib_grid.height()); + + // for (size_t iy = 0; iy < vib_grid.height(); iy++) { + // std::map mux_name_map; + + // for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { + // mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); + // } + // medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; + // } + // } + // } + size_t num_edges_to_create = 0; /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); @@ -173,110 +431,82 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord, perimeter_cb); - if (is_vib_arch) { - t_vib_map vib_map; - vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord, medium_mux_name2medium_index); - build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord); + build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); - rr_graph_builder.build_edges(true); - } - else { - /* adapt the track_to_ipin_lookup for the GSB nodes */ - t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ - track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); - - /* adapt the opin_to_track_map for the GSB nodes */ - t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ - opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); - - /* adapt the switch_block_conn for the GSB nodes */ - t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ - sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, - segment_inf); - - /* Build edges for a GSB */ - build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, - sb_bend_conn, track2ipin_map, opin2track_map, - sb_conn, rr_node_driver_switches, num_edges_to_create); - /* Finish this GSB, go to the next*/ - rr_graph_builder.build_edges(true); - } - } - } + rr_graph_builder.build_edges(true); + + // else { + // /* adapt the track_to_ipin_lookup for the GSB nodes */ + // t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + // track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); - /* Process boundary */ - if (is_vib_arch) { - size_t ix, iy; - // process top boundary - iy = gsb_range.y() + 1; // == grids.height() - 1 - for (ix = 0; ix < gsb_range.x() + 1; ++ix) { - vtr::Point actual_coord(ix, iy); - vtr::Point gsb_coord(ix, iy - 1); + // /* adapt the opin_to_track_map for the GSB nodes */ + // t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + // opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); - /* Create a GSB object */ - const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, - device_chan_width, segment_inf_x, segment_inf_y, - layer, gsb_coord, perimeter_cb); + // /* adapt the switch_block_conn for the GSB nodes */ + // t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + // sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + // sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, + // segment_inf); - - t_vib_map vib_map; - vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); - //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); - size_t edge_count = 0; - for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { - for (auto to_node : iter->second) { - rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); - edge_count++; - } - } - num_edges_to_create += edge_count; - //rr_graph_builder.build_edges(true); - + // /* Build edges for a GSB */ + // build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, + // sb_bend_conn, track2ipin_map, opin2track_map, + // sb_conn, rr_node_driver_switches, num_edges_to_create); + // /* Finish this GSB, go to the next*/ + // rr_graph_builder.build_edges(true); + // } } + } - // process right boundary - ix = gsb_range.x() + 1; - for (iy = 0; iy < gsb_range.y() + 1; ++iy) { - vtr::Point actual_coord(ix, iy); - vtr::Point gsb_coord(ix - 1, iy); + /* Process boundary */ + + size_t ix, iy; + // process top boundary + iy = gsb_range.y() + 1; // == grids.height() - 1 + for (ix = 0; ix < gsb_range.x() + 1; ++ix) { + vtr::Point actual_coord(ix, iy); + vtr::Point gsb_coord(ix, iy - 1); - /* Create a GSB object */ - const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, - device_chan_width, segment_inf_x, segment_inf_y, - layer, gsb_coord, perimeter_cb); + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord, perimeter_cb); - - t_vib_map vib_map; - vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); - //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); - size_t edge_count = 0; - for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { - for (auto to_node : iter->second) { - rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); - edge_count++; - } + + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord); + //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + size_t edge_count = 0; + for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + for (auto to_node : iter->second) { + rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + edge_count++; } - num_edges_to_create += edge_count; - //rr_graph_builder.build_edges(true); - } + num_edges_to_create += edge_count; + //rr_graph_builder.build_edges(true); + + } - // process right-top corner - ix = gsb_range.x() + 1; - iy = gsb_range.y() + 1; - + // process right boundary + ix = gsb_range.x() + 1; + for (iy = 0; iy < gsb_range.y() + 1; ++iy) { vtr::Point actual_coord(ix, iy); - vtr::Point gsb_coord(ix - 1, iy - 1); + vtr::Point gsb_coord(ix - 1, iy); /* Create a GSB object */ const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord, perimeter_cb); - + t_vib_map vib_map; - vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord); //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); size_t edge_count = 0; for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { @@ -286,37 +516,96 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, } } num_edges_to_create += edge_count; - rr_graph_builder.build_edges(true); + //rr_graph_builder.build_edges(true); + } + + // process right-top corner + // ix = gsb_range.x() + 1; + // iy = gsb_range.y() + 1; + + // vtr::Point actual_coord(ix, iy); + // vtr::Point gsb_coord(ix - 1, iy - 1); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + // size_t edge_count = 0; + // for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + // for (auto to_node : iter->second) { + // rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + // edge_count++; + // } + // } + // num_edges_to_create += edge_count; + rr_graph_builder.build_edges(true); + } -/************************************************************************ - * Build direct edges for Grids * - ***********************************************************************/ -void build_rr_graph_direct_connections(const RRGraphView& rr_graph, - RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grids, - const size_t& layer, - const std::vector& directs, - const std::vector& clb_to_clb_directs) { - for (size_t ix = 0; ix < grids.width(); ++ix) { - for (size_t iy = 0; iy < grids.height(); ++iy) { - t_physical_tile_loc tile_loc(ix, iy, layer); - /* Skip EMPTY tiles */ - if (true == is_empty_type(grids.get_physical_type(tile_loc))) { - continue; - } - /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ - if ((0 < grids.get_width_offset(tile_loc)) - || (0 < grids.get_height_offset(tile_loc))) { - continue; - } - vtr::Point from_grid_coordinate(ix, iy); - build_direct_connections_for_one_gsb(rr_graph, - rr_graph_builder, - grids, layer, - from_grid_coordinate, - directs, clb_to_clb_directs); +void build_rr_graph_regular_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& perimeter_cb, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side) { + size_t num_edges_to_create = 0; + /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ + build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + + vtr::Point gsb_range(grids.width() - 1, grids.height() - 1); + + /* Go Switch Block by Switch Block */ + for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { + for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { + //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); + + vtr::Point gsb_coord(ix, iy); + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord, perimeter_cb); + + /* adapt the track_to_ipin_lookup for the GSB nodes */ + t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); + + /* adapt the opin_to_track_map for the GSB nodes */ + t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + + /* adapt the switch_block_conn for the GSB nodes */ + t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, + segment_inf); + + /* Build edges for a GSB */ + /* Build edges for a GSB */ + build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, + track2ipin_map, opin2track_map, + sb_conn, rr_node_driver_switches, num_edges_to_create); + /* Finish this GSB, go to the next*/ + rr_graph_builder.build_edges(true); } } } From 7a0dfbc66ba32658cd2f6f229a336a0822670cda Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:51:44 +0800 Subject: [PATCH 407/453] Update tileable_rr_graph_gsb.cpp --- .../tileable_rr_graph_gsb.cpp | 115 ++++++++++++++++-- 1 file changed, 105 insertions(+), 10 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index d4bf448796c..73696405eb9 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1200,7 +1200,6 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, ***********************************************************************/ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRGSB& rr_gsb, - const t_bend_track2track_map& sb_bend_conn, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, @@ -1251,6 +1250,67 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, } } } + // /* Create edges between bend nodes */ + // for (auto iter = sb_bend_conn.begin(); iter != sb_bend_conn.end(); ++iter) { + // rr_graph_builder.create_edge(iter->first, iter->second, rr_node_driver_switches[iter->second], false); + // edge_count++; + // } + num_edges_to_create += edge_count; +} + +void build_edges_for_one_tileable_rr_gsb_vib(RRGraphBuilder& rr_graph_builder, + const RRGSB& rr_gsb, + const t_bend_track2track_map& sb_bend_conn, + const t_track2pin_map& track2ipin_map, + const t_pin2track_map& opin2track_map, + const t_track2track_map& track2track_map, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges_to_create) { + size_t edge_count = 0; + /* Walk through each sides */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side gsb_side = side_manager.get_side(); + + /* Find OPINs */ + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); + + for (size_t to_side = 0; to_side < opin2track_map[gsb_side][inode].size(); ++to_side) { + /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ + /* add edges to the opin_node */ + for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][to_side]) { + rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node], false); + edge_count++; + } + } + } + + /* Find CHANX or CHANY */ + /* For TRACKs to IPINs, we only care LEFT and TOP sides + * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs + */ + if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { + /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { + rr_graph_builder.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node], false); + edge_count++; + } + } + } + + /* 3. create edges between CHANX|CHANY and CHANX|CHANY, using track2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { + rr_graph_builder.create_edge(chan_node, track_node, rr_node_driver_switches[track_node], false); + edge_count++; + } + } + } /* Create edges between bend nodes */ for (auto iter = sb_bend_conn.begin(); iter != sb_bend_conn.end(); ++iter) { rr_graph_builder.create_edge(iter->first, iter->second, rr_node_driver_switches[iter->second], false); @@ -1753,8 +1813,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, const std::vector& segment_inf, const size_t& layer, const vtr::Point& gsb_coordinate, - const vtr::Point& actual_coordinate, - std::vector>>> medium_mux_name2medium_index) { + const vtr::Point& actual_coordinate) { VTR_ASSERT(rr_gsb.get_x() == gsb_coordinate.x() && rr_gsb.get_y() == gsb_coordinate.y()); t_vib_map vib_map; @@ -1788,6 +1847,11 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, "Can not find from node %s:%d!\n", from.type_name, from.phy_pin_index); continue; } + if (!rr_gsb.is_opin_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Opin node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } } else if (from.from_type == SEGMENT) { char from_dir = from.seg_dir; @@ -1827,15 +1891,24 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } from_node = rr_gsb.get_chan_node(side, track_list[seg_id]); VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); - VTR_ASSERT(rr_gsb.is_chan_node(from_node)); + if (!rr_gsb.is_chan_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wire node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + } } else if (from.from_type == MUX) { - size_t from_mux_index = medium_mux_name2medium_index[layer][actual_coordinate.x()][actual_coordinate.y()][from.type_name]; + size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); - VTR_ASSERT(rr_gsb.is_medium_node(from_node)); + if (!rr_gsb.is_medium_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } } else { VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -1885,6 +1958,11 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, "Can not find from node %s:%d!\n", to.type_name, to.phy_pin_index); continue; } + if (!rr_gsb.is_ipin_node(to_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } } else if (to.from_type == SEGMENT) { char to_dir = to.seg_dir; @@ -1927,7 +2005,11 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, VTR_ASSERT(track_status == TRACK_START); to_node = rr_gsb.get_chan_node(side, track_list[seg_id]); VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); - VTR_ASSERT(rr_gsb.is_chan_node(to_node)); + if (!rr_gsb.is_chan_node(to_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } } @@ -1964,6 +2046,11 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, "Can not find from node %s:%d!\n", from.type_name, from.phy_pin_index); continue; } + if (!rr_gsb.is_opin_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } } else if (from.from_type == SEGMENT) { char from_dir = from.seg_dir; @@ -2003,15 +2090,23 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } from_node = rr_gsb.get_chan_node(side, track_list[seg_id]); VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); - VTR_ASSERT(rr_gsb.is_chan_node(from_node)); + if (!rr_gsb.is_chan_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } } } else if (from.from_type == MUX) { - size_t from_mux_index = medium_mux_name2medium_index[layer][actual_coordinate.x()][actual_coordinate.y()][from.type_name]; + size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); - VTR_ASSERT(rr_gsb.is_medium_node(from_node)); + if (!rr_gsb.is_medium_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } } else { VTR_LOGF_ERROR(__FILE__, __LINE__, From 2e50bfbef7db570b5752d0e02982c6104309b0af Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:52:15 +0800 Subject: [PATCH 408/453] Update rr_gsb.h --- vpr/src/tileable_rr_graph/rr_gsb.h | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index bc4d9c0cb6a..37b2dcc6f9d 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -286,6 +286,7 @@ class RRGSB { /* Medium Nodes Data */ std::vector medium_node_; + std::map medium_node_name_map_; }; #endif From 9dac8c4d6243681b967852855f573ab8b09f2877 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:52:42 +0800 Subject: [PATCH 409/453] Update tileable_rr_graph_gsb.h --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 0e94622cc97..66a50524df7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -64,13 +64,21 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, const RRGSB& rr_gsb, - const t_bend_track2track_map& sb_bend_conn, const t_track2pin_map& track2ipin_map, const t_pin2track_map& opin2track_map, const t_track2track_map& track2track_map, const vtr::vector& rr_node_driver_switches, size_t& num_edges); +void build_edges_for_one_tileable_rr_gsb_vib(RRGraphBuilder& rr_graph_builder, + const RRGSB& rr_gsb, + const t_bend_track2track_map& sb_bend_conn, + const t_track2pin_map& track2ipin_map, + const t_pin2track_map& opin2track_map, + const t_track2track_map& track2track_map, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges); + t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, const RRGSB& rr_gsb, const DeviceGrid& grids, @@ -99,8 +107,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, const std::vector& segment_inf, const size_t& layer, const vtr::Point& gsb_coordinate, - const vtr::Point& actual_coordinate, - std::vector>>> medium_mux_name2medium_index); + const vtr::Point& actual_coordinate); void build_edges_for_one_tileable_vib(RRGraphBuilder& rr_graph_builder, const t_vib_map& vib_map, From a4479e565bd46d1768a76c96f9db56d1df798d40 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:53:14 +0800 Subject: [PATCH 410/453] Update tileable_rr_graph_edge_builder.h --- .../tileable_rr_graph_edge_builder.h | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 2731949918f..0028cfd0e93 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -41,8 +41,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, const bool& opin2all_sides, const bool& concat_wire, const bool& wire_opposite_side, - const RRSwitchId& delayless_switch, - const bool& is_vib_arch); + const RRSwitchId& delayless_switch); void build_rr_graph_direct_connections(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_builder, @@ -65,4 +64,46 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, const size_t& layer, size_t& num_edges_to_create); +void build_rr_graph_vib_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& perimeter_cb, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side, + const RRSwitchId& delayless_switch); + +void build_rr_graph_regular_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& perimeter_cb, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side); + #endif From 9ae8a995db749ba6eed3d46337144a9c970ddec8 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:54:27 +0800 Subject: [PATCH 411/453] Update vib_inf.h --- libs/libarchfpga/src/vib_inf.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/libs/libarchfpga/src/vib_inf.h b/libs/libarchfpga/src/vib_inf.h index c7ac9a0d204..d4766fb7f88 100644 --- a/libs/libarchfpga/src/vib_inf.h +++ b/libs/libarchfpga/src/vib_inf.h @@ -17,6 +17,7 @@ #include "vtr_hash.h" #include "vtr_bimap.h" #include "vtr_string_interning.h" +#include "vtr_log.h" #include "logic_types.h" #include "clock_types.h" @@ -152,6 +153,7 @@ class VibInf { std::vector get_seg_groups() const; std::vector get_first_stages() const; std::vector get_second_stages() const; + size_t medium_mux_index_by_name(const std::string& name) const; private: @@ -266,6 +268,10 @@ class VibDeviceGrid { return vib_grid_[layer][x][y]->get_pbtype_name(); } + bool is_empty() const { + return vib_grid_.empty(); + } + private: std::string name_; From 230fe0f9840f1bd73910261fa9ff4a5fe721c85c Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 18:54:44 +0800 Subject: [PATCH 412/453] Update vib_inf.cpp --- libs/libarchfpga/src/vib_inf.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/libs/libarchfpga/src/vib_inf.cpp b/libs/libarchfpga/src/vib_inf.cpp index 1c80677bf6b..33b77a17f59 100644 --- a/libs/libarchfpga/src/vib_inf.cpp +++ b/libs/libarchfpga/src/vib_inf.cpp @@ -119,6 +119,15 @@ std::vector VibInf::get_second_stages() const{ return second_stages_; } +size_t VibInf::medium_mux_index_by_name(const std::string& name) const{ + for (size_t i_medium = 0; i_medium < first_stages_.size(); ++i_medium) { + if (name == first_stages_[i_medium].mux_name) { + return i_medium; + } + } + VTR_LOG_ERROR("No medium mux named %s!", name); +} + VibDeviceGrid::VibDeviceGrid(std::string grid_name, vtr::NdMatrix vib_grid) : name_(std::move(grid_name)) From 1678907ff4edf74821b1fd26e1f3b87c7ba81140 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Mon, 25 Nov 2024 19:34:36 +0800 Subject: [PATCH 413/453] Update tileable_rr_graph_gsb.cpp --- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 73696405eb9..a6633cfdd42 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -2133,10 +2133,6 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } } } - else { - VTR_LOGF_WARN(__FILE__, __LINE__, - "This medium mux has no from or to nodes!\n"); - } } return vib_map; } From cfe7c2af53deb69fb71e706a08cb08b684e38974 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Fri, 29 Nov 2024 10:29:18 +0800 Subject: [PATCH 414/453] Update index.rst --- doc/src/vpr/index.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/src/vpr/index.rst b/doc/src/vpr/index.rst index 61d60030bdb..ceefa3debaa 100644 --- a/doc/src/vpr/index.rst +++ b/doc/src/vpr/index.rst @@ -60,3 +60,5 @@ The purpose of VPR is to make the packing, placement, and routing stages of the file_formats debug_aids + + VIB From 35a82e7022ccf1a4b7fde81ca95a7c0ebf81e548 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Fri, 29 Nov 2024 10:30:09 +0800 Subject: [PATCH 415/453] Create VIB.rst --- doc/src/vpr/VIB.rst | 173 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 doc/src/vpr/VIB.rst diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst new file mode 100644 index 00000000000..29012ccfb94 --- /dev/null +++ b/doc/src/vpr/VIB.rst @@ -0,0 +1,173 @@ +.. _VIB: + +VIB +============ +The VIB architecture adds modeling support for double-level MUX topology and bent wires. + +.. figure:: ../Images/VIB.png + :align: center + :height: 300 + + VIB architecture. The connections between the inputs and outputs of the LB and the routing wires are all implemented within the VIB. + +.. figure:: ../Images/double-level.png + :align: center + + Double-level MUX topology. + +.. figure:: ../Images/bent_wires.png + :align: center + + Presentation for bent wires. + +FPGA Architecture File Modification (.xml) +-------------------------- +For original tags of FPGA architecture file see :ref:`fpga_architecture_description`. + +Modification for ```` Tag +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The content within the ```` tag consists of a group of ```` tags. +The ```` tag and its contents are described below. + +.. arch:tag:: content + + :req_param content: + The switch names and the depopulation pattern as described below. + +.. arch:tag:: int list + +.. arch:tag:: int list + +.. arch:tag:: + +For bent wires, a new content ```` is added in the ```` tag. + +.. arch:tag:: bent pattern list + + This tag describes the bent pattern for this particular wire segment. + For example, a length 4 wire has a bent pattern of ``- - U``. + A ``-`` indicates no bent at this position and a ``U`` indicates a conterclockwise bent at the position. (``D`` indicates a clockwise bent.) + + .. note:: A bent wire should remain consistent in both the x and y axes. + +New Added Top Level Tag ```` +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The content within the ```` tag consists of a group of ```` tags. Different ```` tags describe the paradigms of VIB, which apply to different positions. + +.. arch:tag:: content + + :req_param name: + A unique alphanumeric name to identify this VIB type. + + :req_param pbtype_name: + The name of the block type (e.g. clb, memory) that this VIB connects to. + + :req_param vib_seg_group: + The number of the segment types in this VIB. + + :req_param arch_vib_switch: + Name of the mux switch type used to drive wires in the VIB by default, and a custom switch can override this switch type for specific connections if desired. + + :req_param content: + The segment groups and the multistage MUX topology as described below. + +The ``content`` of ```` tag consists of several ```` tags and a ```` tag. +For example: + +.. code-block:: xml + + + + + + + + + + ... + + + ... + + + + + ... + + + +.. arch:tag:: + + :req_param name: + The name of the segment in this VIB described in ````. + + :req_param track_nums: + The track number of the segment in this VIB. + + .. note:: When using unidirectional segments, the track number of the segment represents the number for one direction. For example, the ``track_nums`` is ``10``, which means total ``20`` tracks of the segment in the channel for both (INC & DEC) directions. + +.. arch:tag:: content + + :req_param content: + The detaild information for first and second MUXes. + +The ``content`` of ```` tag consists of a ```` tag and a ```` tag. + +.. arch:tag:: content + + :req_param switch_name: + Name of the mux switch type used to drive first stage MUXes in the VIB. + + :req_param content: + The details of each MUX. + +For example: + +.. code-block:: xml + + + + clb.O[0] clb.O[8] clb.O[12:16] + + + L1.E2 L1.W2 L1.S8 L1.N8 + + ... + + +The ```` tag in ```` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.E2`` means the track ``2`` in the ``East`` direction of ``L1`` segment. + +.. arch:tag:: content + + :req_param content: + The details of each MUX. + +For example: + +.. code-block:: xml + + + + clb.I[0] + clb.O[0] clb.O[8] f_mux_0 + + + L1.S1 + L1.E1 L1.W1 f_mux_0 f_mux_1 + + ... + + +The ```` tag describes the node this MUX connects to. ``clb.I[*]`` means input pin(s); ``L1.S1`` means the track ``1`` in the ``South`` direction of ``L1`` segment. The ```` tag in ```` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.E2`` means the track ``2`` in the ``East`` direction of ``L1`` segment. ``f_mux_0`` means the name of the specific first stage MUX. + +New Added Top Level Tag ```` +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Content inside this tag specifies VIB grid layout to describe different VIBs applied on different locations. + +.. arch:tag:: content + + :req_param name: + The name identifying this VIB grid layout. It should be the same as the corresponding layout name inside the ```` tag. + + :req_param content: + The content should contain a set of grid location tags. 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Running :option:`vpr --help` will display all the available options and their usage information. +VPR has a lot of options. Running :option:`vpr --help` will display all the available options and their usage information. .. option:: -h, --help Display help message then exit. - + The options most people will be interested in are: * :option:`--route_chan_width` (route at a fixed channel width), and @@ -208,7 +208,7 @@ General Options * Any string matching ``name`` attribute of a device layout defined with a ```` tag in the :ref:`arch_grid_layout` section of the architecture file. If the value specified is neither ``auto`` nor matches the ``name`` attribute value of a ```` tag, VPR issues an error. - + .. note:: If the only layout in the architecture file is a single device specified using ````, it is recommended to always specify the ``--device`` option; this prevents the value ``--device auto`` from interfering with operations supported only for ```` grids. **Default:** ``auto`` @@ -223,6 +223,12 @@ General Options If this option is not specified it may be set from the ``VPR_NUM_WORKERS`` environment variable; otherwise the default is used. + If this option is set to something other than 1, the following algorithms can be run in parallel: + + * Timing Analysis + * Routing (If routing algorithm is set to parallel or parallel_decomp; See :option:`--router_algorithm`) + * Portions of analytical placement (If using the analytical placement flow and compiled VPR with Eigen enabled; See :option:`--analytical_place`) + .. note:: To compile VPR to allow the usage of parallel workers, ``libtbb-dev`` must be installed in the system. **Default:** ``1`` @@ -569,7 +575,7 @@ For people not working on CAD, you can probably leave all the options to their d **Default**: ``auto`` -.. option:: --alpha_clustering +.. option:: --timing_gain_weight A parameter that weights the optimization of timing vs area. @@ -577,7 +583,7 @@ For people not working on CAD, you can probably leave all the options to their d **Default**: ``0.75`` -.. option:: --beta_clustering +.. option:: --connection_gain_weight A tradeoff parameter that controls the optimization of smaller net absorption vs. the optimization of signal sharing. @@ -900,7 +906,7 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe .. option:: --place_agent_algorithm {e_greedy | softmax} - Controls which placement RL agent is used. + Controls which placement RL agent is used. **Default:** ``softmax`` @@ -922,10 +928,10 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe .. option:: --place_reward_fun {basic | nonPenalizing_basic | runtime_aware | WLbiased_runtime_aware} - The reward function used by the placement RL agent to learn the best action at each anneal stage. + The reward function used by the placement RL agent to learn the best action at each anneal stage. + + .. note:: The latter two are only available for timing-driven placement. - .. note:: The latter two are only available for timing-driven placement. - **Default:** ``WLbiased_runtime_aware`` .. option:: --place_agent_space {move_type | move_block_type} @@ -935,20 +941,20 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe **Default:** ``move_block_type`` .. option:: --place_quench_only {on | off} - + If this option is set to ``on``, the placement will skip the annealing phase and only perform the placement quench. - This option is useful when the the quality of initial placement is good enough and there is no need to perform the + This option is useful when the the quality of initial placement is good enough and there is no need to perform the annealing phase. **Default:** ``off`` .. option:: --placer_debug_block - + .. note:: This option is likely only of interest to developers debugging the placement algorithm - Controls which block the placer produces detailed debug information for. - + Controls which block the placer produces detailed debug information for. + If the block being moved has the same ID as the number assigned to this parameter, the placer will print debugging information about it. * For values >= 0, the value is the block ID for which detailed placer debug information should be produced. @@ -960,7 +966,7 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe **Default:** ``-2`` .. option:: --placer_debug_net - + .. note:: This option is likely only of interest to developers debugging the placement algorithm Controls which net the placer produces detailed debug information for. @@ -1004,7 +1010,7 @@ The following options are only valid when the placement engine is in timing-driv .. option:: --quench_recompute_divider - Controls how many times the placer performs a timing analysis to update its criticality estimates during a quench. + Controls how many times the placer performs a timing analysis to update its criticality estimates during a quench. If unspecified, uses the value from --inner_loop_recompute_divider. **Default:** ``0`` @@ -1088,7 +1094,7 @@ The following options are only valid when the placement engine is in timing-driv NoC Options ^^^^^^^^^^^^^^ -The following options are only used when FPGA device and netlist contain a NoC router. +The following options are only used when FPGA device and netlist contain a NoC router. .. option:: --noc {on | off} @@ -1098,7 +1104,7 @@ The following options are only used when FPGA device and netlist contain a NoC r **Default:** ``off`` .. option:: --noc_flows_file - + XML file containing the list of traffic flows within the NoC (communication between routers). .. note:: noc_flows_file are required to specify if NoC optimization is turned on (--noc on). @@ -1106,7 +1112,7 @@ The following options are only used when FPGA device and netlist contain a NoC r .. option:: --noc_routing_algorithm {xy_routing | bfs_routing | west_first_routing | north_last_routing | negative_first_routing | odd_even_routing} Controls the algorithm used by the NoC to route packets. - + * ``xy_routing`` Uses the direction oriented routing algorithm. This is recommended to be used with mesh NoC topologies. * ``bfs_routing`` Uses the breadth first search algorithm. The objective is to find a route that uses a minimum number of links. This algorithm is not guaranteed to generate deadlock-free traffic flow routes, but can be used with any NoC topology. * ``west_first_routing`` Uses the west-first routing algorithm. This is recommended to be used with mesh NoC topologies. @@ -1119,11 +1125,11 @@ The following options are only used when FPGA device and netlist contain a NoC r .. option:: --noc_placement_weighting Controls the importance of the NoC placement parameters relative to timing and wirelength of the design. - + * ``noc_placement_weighting = 0`` means the placement is based solely on timing and wirelength. * ``noc_placement_weighting = 1`` means noc placement is considered equal to timing and wirelength. * ``noc_placement_weighting > 1`` means the placement is increasingly dominated by NoC parameters. - + **Default:** ``5.0`` .. option:: --noc_aggregate_bandwidth_weighting @@ -1141,7 +1147,7 @@ The following options are only used when FPGA device and netlist contain a NoC r Other positive numbers specify the importance of meeting latency constraints compared to other NoC-related cost terms. Weighting factors for NoC-related cost terms are normalized internally. Therefore, their absolute values are not important, and only their relative ratios determine the importance of each cost term. - + **Default:** ``0.6`` .. option:: --noc_latency_weighting @@ -1151,7 +1157,7 @@ The following options are only used when FPGA device and netlist contain a NoC r Other positive numbers specify the importance of minimizing aggregate latency compared to other NoC-related cost terms. Weighting factors for NoC-related cost terms are normalized internally. Therefore, their absolute values are not important, and only their relative ratios determine the importance of each cost term. - + **Default:** ``0.02`` .. option:: --noc_congestion_weighting @@ -1167,11 +1173,11 @@ The following options are only used when FPGA device and netlist contain a NoC r .. option:: --noc_swap_percentage Sets the minimum fraction of swaps attempted by the placer that are NoC blocks. - This value is an integer ranging from [0-100]. - - * ``0`` means NoC blocks will be moved at the same rate as other blocks. + This value is an integer ranging from [0-100]. + + * ``0`` means NoC blocks will be moved at the same rate as other blocks. * ``100`` means all swaps attempted by the placer are NoC router blocks. - + **Default:** ``0`` .. option:: --noc_placement_file_name @@ -1257,7 +1263,7 @@ Analytical Placement is generally split into three stages: * ``none`` Do not use any Detailed Placer. - * ``annealer`` Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer. + * ``annealer`` Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer. **Default:** ``annealer`` @@ -1270,6 +1276,49 @@ Analytical Placement is generally split into three stages: **Default:** ``0.5`` +.. option:: --appack_max_dist_th { auto | :, } + + Sets the maximum candidate distance thresholds for the logical block types + used by APPack. APPack uses the primitive-level placement produced by the + global placer to cluster primitives together. APPack uses the thresholds + here to ignore primitives which are too far away from the cluster being formed. + + When this option is set to "auto", VPR will select good values for these + thresholds based on the primitives contained within each logical block type. + + Using this option, the user can set the maximum candidate distance threshold + of logical block types to something else. The strings passed in by the user + should be of the form ``:,`` where the regex string is + used to match the name of the logical block type to set, the first float + is a scaling term, and the second float is an offset. The threshold will + be set to max(scale * (W + H), offset), where W and H are the width and height + of the device. This allows the user to specify a threshold based on the + size of the device, while also preventing the number from going below "offset". + When multiple strings are provided, the thresholds are set from left to right, + and any logical block types which have been unset will be set to their "auto" + values. + + For example: + + .. code-block:: none + + --appack_max_dist_th .*:0.1,0 "clb|memory:0,5" + + Would set all logical block types to be 0.1 * (W + H), except for the clb and + memory block, which will be set to a fixed value of 5. + + Another example: + + .. code-block:: none + + --appack_max_dist_th "clb|LAB:0.2,5" + + This will set all of the logical block types to their "auto" thresholds, except + for logical blocks with the name clb/LAB which will be set to 0.2 * (W + H) or + 5 (whichever is larger). + + **Default:** ``auto`` + .. option:: --ap_verbosity Controls the verbosity of the AP flow output. @@ -1343,8 +1392,8 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout .. option:: --max_pres_fac - Sets the maximum present overuse penalty factor that can ever result during routing. Should always be less than 1e25 or so to prevent overflow. - Smaller values may help prevent circuitous routing in difficult routing problems, but may increase + Sets the maximum present overuse penalty factor that can ever result during routing. Should always be less than 1e25 or so to prevent overflow. + Smaller values may help prevent circuitous routing in difficult routing problems, but may increase the number of routing iterations needed and hence runtime. **Default:** ``1000.0`` @@ -1423,7 +1472,7 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout .. option:: --router_algorithm {timing_driven | parallel | parallel_decomp} - Selects which router algorithm to use. + Selects which router algorithm to use. * ``timing_driven`` is the default single-threaded PathFinder algorithm. @@ -1474,6 +1523,35 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout * `swns` - setup Worst Negative Slack (sWNS) [ns] * `stns` - Setup Total Negative Slack (sTNS) [ns] + +.. option:: --generate_net_timing_report {on | off} + + Generates a report that lists the bounding box, slack, and delay of every routed connection in a design in CSV format (``report_net_timing.csv``). Each row in the CSV corresponds to a single net. + + The report can later be used by other tools to enable further optimizations. For example, the Synopsys synthesis tool (Synplify) can use this information to re-synthesize the design and improve the Quality of Results (QoR). + + Fields in the report are: + + .. code-block:: none + + netname : The name assigned to the net in the atom netlist + Fanout : Net's fanout (number of sinks) + bb_xmin : X coordinate of the net's bounding box's bottom-left corner + bb_ymin : Y coordinate of the net's bounding box's bottom-left corner + bb_layer_min : Lowest layer number of the net's bounding box + bb_xmax : X coordinate of the net's bounding box's top-right corner + bb_ymax : Y coordinate of the net's bounding box's top-right corner + bb_layer_max : Highest layer number of the net's bounding box + src_pin_name : Name of the net's source pin + src_pin_slack : Setup slack of the net's source pin + sinks : A semicolon-separated list of sink pin entries, each in the format: + ,, + + Example value for the ``sinks`` field: + ``"U2.B,0.12,0.5;U3.C,0.10,0.6;U4.D,0.08,0.7"`` + + **Default:** ``off`` + .. option:: --route_verbosity Controls the verbosity of routing output. @@ -1505,13 +1583,90 @@ The following options are only valid when the router is in timing-driven mode (t **Default:** ``0.0`` .. option:: --router_profiler_astar_fac - + Controls the directedness of the timing-driven router's exploration when doing router delay profiling of an architecture. The router delay profiling step is currently used to calculate the place delay matrix lookup. Values between 1 and 2 are resonable; higher values trade some quality for reduced run-time. **Default:** ``1.2`` +.. option:: --enable_parallel_connection_router {on | off} + + Controls whether the MultiQueue-based parallel connection router is used during a single connection routing. + + When enabled, the parallel connection router accelerates the path search for individual source-sink connections using + multi-threading without altering the net routing order. + + **Default:** ``off`` + +.. option:: --post_target_prune_fac + + Controls the post-target pruning heuristic calculation in the parallel connection router. + + This parameter is used as a multiplicative factor applied to the VPR heuristic (not guaranteed to be admissible, i.e., + might over-predict the cost to the sink) to calculate the 'stopping heuristic' when pruning nodes after the target has + been reached. The 'stopping heuristic' must be admissible for the path search algorithm to guarantee optimal paths and + be deterministic. + + Values of this parameter are architecture-specific and have to be empirically found. + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``1.2`` + +.. option:: --post_target_prune_offset + + Controls the post-target pruning heuristic calculation in the parallel connection router. + + This parameter is used as a subtractive offset together with :option:`--post_target_prune_fac` to apply an affine + transformation on the VPR heuristic to calculate the 'stopping heuristic'. The 'stopping heuristic' must be admissible + for the path search algorithm to guarantee optimal paths and be deterministic. + + Values of this parameter are architecture-specific and have to be empirically found. + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``0.0`` + +.. option:: --multi_queue_num_threads + + Controls the number of threads used by MultiQueue-based parallel connection router. + + If not explicitly specified, defaults to 1, implying the parallel connection router works in 'serial' mode using only + one main thread to route. + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``1`` + +.. option:: --multi_queue_num_queues + + Controls the number of queues used by MultiQueue in the parallel connection router. + + Must be set >= 2. A common configuration for this parameter is the number of threads used by MultiQueue * 4 (the number + of queues per thread). + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``2`` + +.. option:: --multi_queue_direct_draining {on | off} + + Controls whether to enable queue draining optimization for MultiQueue-based parallel connection router. + + When enabled, queues can be emptied quickly by draining all elements if no further solutions need to be explored after + the target is reached in the path search. + + Note: For this optimization to maintain optimality and deterministic results, the 'ordering heuristic' (calculated by + :option:`--astar_fac` and :option:`--astar_offset`) must be admissible to ensure emptying queues of entries with higher + costs does not prune possibly superior solutions. However, you can still enable this optimization regardless of whether + optimality and determinism are required for your specific use case (in such cases, the 'ordering heuristic' can be + inadmissible). + + This parameter has no effect if :option:`--enable_parallel_connection_router` is not set. + + **Default:** ``off`` + .. option:: --max_criticality Sets the maximum fraction of routing cost that can come from delay (vs. coming from routability) for any net. @@ -1710,6 +1865,16 @@ Analysis Options **Default:** ``off`` +.. option:: --gen_post_implementation_sdc { on | off } + + Generates an SDC file including a list of constraints that would + replicate the timing constraints that the timing analysis within + VPR followed during the flow. This can be helpful for flows that + use external timing analysis tools that have additional capabilities + or more detailed delay models than what VPR uses. + + **Default:** ``off`` + .. option:: --post_synth_netlist_unconn_inputs { unconnected | nets | gnd | vcc } Controls how unconnected input cell ports are handled in the post-synthesis netlist @@ -1730,6 +1895,16 @@ Analysis Options **Default:** ``unconnected`` +.. option:: --post_synth_netlist_module_parameters { on | off } + + Controls whether the post-synthesis netlist output by VTR can use Verilog parameters + or not. When using the post-synthesis netlist for external timing analysis, + some tools cannot accept the netlist if it contains parameters. By setting + this option to ``off``, VPR will try to represent the netlist using non-parameterized + modules. + + **Default:** ``on`` + .. option:: --timing_report_npaths Controls how many timing paths are reported. diff --git a/doc/src/zreferences.rst b/doc/src/zreferences.rst index 76df654a14a..af178fe070a 100644 --- a/doc/src/zreferences.rst +++ b/doc/src/zreferences.rst @@ -1,5 +1,18 @@ Publications & References ========================= +How to cite +----------- +`M. A. Elgammal`, `A. Mohaghegh`, `S. G. Shahrouz`, `F. Mahmoudi`, `F. Kosar`, `K. Talaei`, `J. Fife`, `D. Khadivi`, `K. Murray`, `A. Boutros`, `K. B. Kent`, `J. Goeders`, and `V. Betz`, "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration," *ACM TRETS*, 2025. [`PDF `__] + +Previous Publications +--------------------- +* `K. E. Murray`, `O. Petelin`, `S. Zhong`, `J. M. Wang`, `M. ElDafrawy`, `J.-P. Legault`, `E. Sha`, `A. G. Graham`, `J. Wu`, `M. J. P. Walker`, `H. Zeng`, `P. Patros`, `J. Luu`, `K. B. Kent` and `V. Betz`, "VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling", *ACM TRETS*, 2020. + +* `J. LUU`, `J. Goeders`, `M. Wainberg`, `A. Somerville`, `T. Yu`, `K. Nasartschuk`, `M. Nasr`, `S. Wang`, `T. L`, `N. Ahmed`, `K. B. Kent`, `J. Anderson`, `J. Rose`, `V. Betz`, "VTR 7.0: Next Generation Architecture and CAD System for FPGAs", *ACM TRETS*, 2014. + +References +---------- + .. bibliography:: z_references.bib :all: diff --git a/install_apt_packages.sh b/install_apt_packages.sh index ede554a197c..c3cba57f777 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -13,6 +13,10 @@ sudo apt-get install -y \ openssl \ libssl-dev +# Packages for more complex features of VTR that most people will use. +sudo apt-get install -y \ + libtbb-dev + # Required for graphics sudo apt-get install -y \ libgtk-3-dev \ @@ -42,3 +46,13 @@ sudo apt-get install -y \ # Required to build the documentation sudo apt-get install -y \ sphinx-common + +# Required for code formatting +# NOTE: clang-format-18 may only be found on specific distributions. Only +# install it if the distribution has this version of clang format. +if apt-cache search '^clang-format-18$' | grep -q 'clang-format-18'; then + sudo apt-get install -y \ + clang-format-18 +else + echo "clang-format-18 not found in apt-cache. Skipping installation." +fi diff --git a/libs/EXTERNAL/libblifparse/CMakeLists.txt b/libs/EXTERNAL/libblifparse/CMakeLists.txt index 57f33eb2e57..f38652308c8 100644 --- a/libs/EXTERNAL/libblifparse/CMakeLists.txt +++ b/libs/EXTERNAL/libblifparse/CMakeLists.txt @@ -13,7 +13,7 @@ if(${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_CURRENT_SOURCE_DIR}) endif() #Flex and Bison are used to generate the parser -find_package(BISON REQUIRED 3.0) +find_package(BISON REQUIRED 3.3) find_package(FLEX REQUIRED) file(GLOB_RECURSE LIB_SOURCES src/blif*.cpp) diff --git a/libs/EXTERNAL/libblifparse/src/blif_parser.y b/libs/EXTERNAL/libblifparse/src/blif_parser.y index 2b51dd7cc7e..495d495b6d8 100644 --- a/libs/EXTERNAL/libblifparse/src/blif_parser.y +++ b/libs/EXTERNAL/libblifparse/src/blif_parser.y @@ -1,5 +1,5 @@ -/* C++ parsers require Bison 3 */ -%require "3.0" +/* C++ parsers require Bison 3.3 */ +%require "3.3" %language "C++" /* Write-out tokens header file */ @@ -34,7 +34,7 @@ %define api.namespace {blifparse} /* Name the parser class */ -%define parser_class_name {Parser} +%define api.parser.class {Parser} /* Match the flex prefix */ %define api.prefix {blifparse_} diff --git a/libs/EXTERNAL/libsdcparse/CMakeLists.txt b/libs/EXTERNAL/libsdcparse/CMakeLists.txt index 24a7b2973c8..5afc97f3117 100644 --- a/libs/EXTERNAL/libsdcparse/CMakeLists.txt +++ b/libs/EXTERNAL/libsdcparse/CMakeLists.txt @@ -13,7 +13,7 @@ if(${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_CURRENT_SOURCE_DIR}) endif() #Flex and Bison are used to generate the parser -find_package(BISON REQUIRED 3.0) +find_package(BISON REQUIRED 3.3) find_package(FLEX REQUIRED) file(GLOB_RECURSE LIB_SOURCES src/sdc*.cpp) diff --git a/libs/EXTERNAL/libsdcparse/src/sdc_parser.y b/libs/EXTERNAL/libsdcparse/src/sdc_parser.y index 1dadaee3745..686173392bf 100644 --- a/libs/EXTERNAL/libsdcparse/src/sdc_parser.y +++ b/libs/EXTERNAL/libsdcparse/src/sdc_parser.y @@ -1,5 +1,5 @@ -/* C++ parsers require Bison 3 */ -%require "3.0" +/* C++ parsers require Bison 3.3 */ +%require "3.3" %language "C++" /* Write-out tokens header file */ @@ -34,7 +34,7 @@ %define api.namespace {sdcparse} /* Name the parser class */ -%define parser_class_name {Parser} +%define api.parser.class {Parser} /* Match the flex prefix */ %define api.prefix {sdcparse_} diff --git a/libs/libarchfpga/src/arch_check.cpp b/libs/libarchfpga/src/arch_check.cpp index 5360d6e4c02..75c96aa3cfb 100644 --- a/libs/libarchfpga/src/arch_check.cpp +++ b/libs/libarchfpga/src/arch_check.cpp @@ -1,14 +1,14 @@ #include -#include +#include "logic_types.h" #include "vtr_log.h" #include "arch_error.h" #include "arch_check.h" -bool check_model_clocks(t_model* model, const char* file, uint32_t line) { +bool check_model_clocks(const t_model& model, const char* file, uint32_t line) { //Collect the ports identified as clocks std::set clocks; - for (t_model_ports* ports : {model->inputs, model->outputs}) { + for (t_model_ports* ports : {model.inputs, model.outputs}) { for (t_model_ports* port = ports; port != nullptr; port = port->next) { if (port->is_clock) { clocks.insert(port->name); @@ -17,41 +17,41 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line) { } //Check that any clock references on the ports are to identified clock ports - for (t_model_ports* ports : {model->inputs, model->outputs}) { + for (t_model_ports* ports : {model.inputs, model.outputs}) { for (t_model_ports* port = ports; port != nullptr; port = port->next) { if (!port->clock.empty() && !clocks.count(port->clock)) { archfpga_throw(file, line, "No matching clock port '%s' on model '%s', required for port '%s'", - port->clock.c_str(), model->name, port->name); + port->clock.c_str(), model.name, port->name); } } } return true; } -bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line) { +bool check_model_combinational_sinks(const t_model& model, const char* file, uint32_t line) { //Outputs should have no combinational sinks - for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.outputs; port != nullptr; port = port->next) { if (!port->combinational_sink_ports.empty()) { archfpga_throw(file, line, "Model '%s' output port '%s' can not have combinational sink ports", - model->name, port->name); + model.name, port->name); } } //Record the output ports std::map output_ports; - for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.outputs; port != nullptr; port = port->next) { output_ports.insert({port->name, port}); } - for (t_model_ports* port = model->inputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.inputs; port != nullptr; port = port->next) { for (const std::string& sink_port_name : port->combinational_sink_ports) { //Check that the input port combinational sinks are all outputs if (!output_ports.count(sink_port_name)) { archfpga_throw(file, line, "Model '%s' input port '%s' can not be combinationally connected to '%s' (not an output port of the model)", - model->name, port->name, sink_port_name.c_str()); + model.name, port->name, sink_port_name.c_str()); } //Check that any output combinational sinks are not clocks @@ -61,7 +61,7 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin archfpga_throw(file, line, "Model '%s' output port '%s' can not be both: a clock source (is_clock=\"%d\")," " and combinationally connected to input port '%s' (acting as a clock buffer).", - model->name, sink_port->name, sink_port->is_clock, port->name); + model.name, sink_port->name, sink_port->is_clock, port->name); } } } @@ -69,28 +69,28 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin return true; } -void warn_model_missing_timing(const t_model* model, const char* file, uint32_t line) { +void warn_model_missing_timing(const t_model& model, const char* file, uint32_t line) { //Check whether there are missing edges and warn the user std::set comb_connected_outputs; - for (t_model_ports* port = model->inputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.inputs; port != nullptr; port = port->next) { if (port->clock.empty() //Not sequential && port->combinational_sink_ports.empty() //Doesn't drive any combinational outputs && !port->is_clock //Not an input clock ) { VTR_LOGF_WARN(file, line, - "Model '%s' input port '%s' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\n", model->name, port->name); + "Model '%s' input port '%s' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\n", model.name, port->name); } comb_connected_outputs.insert(port->combinational_sink_ports.begin(), port->combinational_sink_ports.end()); } - for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) { + for (t_model_ports* port = model.outputs; port != nullptr; port = port->next) { if (port->clock.empty() //Not sequential && !comb_connected_outputs.count(port->name) //Not combinationally driven && !port->is_clock //Not an output clock ) { VTR_LOGF_WARN(file, line, - "Model '%s' output port '%s' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\n", model->name, port->name); + "Model '%s' output port '%s' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\n", model.name, port->name); } } } @@ -144,23 +144,13 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar } //Find the matching model - const t_model* model = nullptr; - - for (const t_model* models : {arch.models, arch.model_library}) { - for (model = models; model != nullptr; model = model->next) { - if (std::string(model->name) == blif_model) { - break; - } - } - if (model != nullptr) { - break; - } - } - if (model == nullptr) { + LogicalModelId blif_model_id = arch.models.get_model_by_name(blif_model); + if (!blif_model_id.is_valid()) { archfpga_throw(get_arch_file_name(), -1, "Unable to find model for blif_model '%s' found on pb_type '%s'", blif_model.c_str(), pb_type->name); } + const t_model& model = arch.models.get_model(blif_model_id); //Now that we have the model we can compare the timing annotations @@ -185,7 +175,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Find the model port const t_model_ports* model_port = nullptr; - for (const t_model_ports* ports : {model->inputs, model->outputs}) { + for (const t_model_ports* ports : {model.inputs, model.outputs}) { for (const t_model_ports* port = ports; port != nullptr; port = port->next) { if (port->name == annot_port.port_name()) { model_port = port; @@ -206,13 +196,13 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar archfpga_throw(get_arch_file_name(), annot->line_num, " timing-annotation/ mismatch on port '%s' of model '%s', model specifies" " no clock but timing annotation specifies '%s'", - annot_port.port_name().c_str(), model->name, annot_clock.port_name().c_str()); + annot_port.port_name().c_str(), model.name, annot_clock.port_name().c_str()); } if (model_port->clock != annot_clock.port_name()) { archfpga_throw(get_arch_file_name(), annot->line_num, " timing-annotation/ mismatch on port '%s' of model '%s', model specifies" " clock as '%s' but timing annotation specifies '%s'", - annot_port.port_name().c_str(), model->name, model_clock.c_str(), annot_clock.port_name().c_str()); + annot_port.port_name().c_str(), model.name, model_clock.c_str(), annot_clock.port_name().c_str()); } } } @@ -227,7 +217,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Find the input model port const t_model_ports* model_port = nullptr; - for (const t_model_ports* port = model->inputs; port != nullptr; port = port->next) { + for (const t_model_ports* port = model.inputs; port != nullptr; port = port->next) { if (port->name == annot_in.port_name()) { model_port = port; break; @@ -248,7 +238,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar archfpga_throw(get_arch_file_name(), annot->line_num, " timing-annotation/ mismatch on port '%s' of model '%s', timing annotation" " specifies combinational connection to port '%s' but the connection does not exist in the model", - model_port->name, model->name, annot_out.port_name().c_str()); + model_port->name, model.name, annot_out.port_name().c_str()); } } } @@ -260,7 +250,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Build a list of combinationally connected sinks std::set comb_connected_outputs; - for (t_model_ports* model_ports : {model->inputs, model->outputs}) { + for (t_model_ports* model_ports : {model.inputs, model.outputs}) { for (t_model_ports* model_port = model_ports; model_port != nullptr; model_port = model_port->next) { comb_connected_outputs.insert(model_port->combinational_sink_ports.begin(), model_port->combinational_sink_ports.end()); } @@ -270,7 +260,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar // // This ensures that the pb_type has annotations for all delays/values // required by the model - for (t_model_ports* model_ports : {model->inputs, model->outputs}) { + for (t_model_ports* model_ports : {model.inputs, model.outputs}) { for (t_model_ports* model_port = model_ports; model_port != nullptr; model_port = model_port->next) { //If the model port has no timing specification don't check anything (e.g. architectures with no timing info) if (model_port->clock.empty() @@ -288,10 +278,10 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " port is a sequential input but has neither T_setup nor T_hold specified"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -305,11 +295,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " port is a sequential input with internal combinational connects but has neither"; msg << " min nor max T_clock_to_Q specified"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -325,10 +315,10 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " port is a sequential output but has neither min nor max T_clock_to_Q specified"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -342,11 +332,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " port is a sequential output with internal combinational connections but has"; msg << " neither T_setup nor T_hold specified"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -363,11 +353,11 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar if (find_combinational_annotation(pb_type, model_port->name, sink_port) == nullptr) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; - msg << " port '" << model_port->name << "' of model '" << model->name << "',"; + msg << " port '" << model_port->name << "' of model '" << model.name << "',"; msg << " input port '" << model_port->name << "' has combinational connections to"; msg << " port '" << sink_port.c_str() << "'; specified in model, but no combinational delays found on pb_type"; - if (is_library_model(model)) { + if (arch.models.is_library_model(blif_model_id)) { //Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture) VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str()); } else { @@ -383,15 +373,16 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar } void check_models(t_arch* arch) { - for (t_model* model = arch->models; model != nullptr; model = model->next) { - if (model->pb_types == nullptr) { + for (LogicalModelId model_id : arch->models.user_models()) { + const t_model& model = arch->models.get_model(model_id); + if (model.pb_types == nullptr) { archfpga_throw(get_arch_file_name(), 0, - "No pb_type found for model %s\n", model->name); + "No pb_type found for model %s\n", model.name); } int clk_count, input_count, output_count; clk_count = input_count = output_count = 0; - for (auto ports : {model->inputs, model->outputs}) { + for (auto ports : {model.inputs, model.outputs}) { for (auto port = ports; port != nullptr; port = port->next) { int index; switch (port->dir) { @@ -403,7 +394,7 @@ void check_models(t_arch* arch) { break; default: archfpga_throw(get_arch_file_name(), 0, - "Port %s of model %s, has an unrecognized type %s\n", port->name, model->name); + "Port %s of model %s, has an unrecognized type %s\n", port->name, model.name); } port->index = index; diff --git a/libs/libarchfpga/src/arch_check.h b/libs/libarchfpga/src/arch_check.h index 20b3ad30d4b..b057cbde347 100644 --- a/libs/libarchfpga/src/arch_check.h +++ b/libs/libarchfpga/src/arch_check.h @@ -26,7 +26,7 @@ extern "C" { * @param file architecture file * @param line line in the architecture file that generates the failure */ -bool check_model_clocks(t_model* model, const char* file, uint32_t line); +bool check_model_clocks(const t_model& model, const char* file, uint32_t line); /** * @brief Checks the correctness of the combinational sinks in the model inputs to outputs connections @@ -35,7 +35,7 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line); * @param file architecture file * @param line line in the architecture file that generates the failure */ -bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line); +bool check_model_combinational_sinks(const t_model& model, const char* file, uint32_t line); /** * @brief Checks whether the I/O ports can have timing specifications based on their connectivity. @@ -47,7 +47,7 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin * @param file architecture file * @param line line in the architecture file that generates the failure */ -void warn_model_missing_timing(const t_model* model, const char* file, uint32_t line); +void warn_model_missing_timing(const t_model& model, const char* file, uint32_t line); /** * @brief Checks the consistency of the mappings between a logical block and the corresponding physical tile. diff --git a/libs/libarchfpga/src/arch_types.h b/libs/libarchfpga/src/arch_types.h index 69ac28ae479..bc2e65a4ca2 100644 --- a/libs/libarchfpga/src/arch_types.h +++ b/libs/libarchfpga/src/arch_types.h @@ -16,20 +16,11 @@ #define TOKENS " \t\n" /* Value for UNDEFINED data */ -constexpr int UNDEFINED = -1; - -/** The total number of predefined blif models */ -constexpr int NUM_MODELS_IN_LIBRARY = 4; +constexpr int ARCH_FPGA_UNDEFINED_VAL = -1; /* Maximum value for minimum channel width to avoid overflows of short data type. */ constexpr int MAX_CHANNEL_WIDTH = 8000; -/* Built-in library models */ -constexpr const char* MODEL_NAMES = ".names"; -constexpr const char* MODEL_LATCH = ".latch"; -constexpr const char* MODEL_INPUT = ".input"; -constexpr const char* MODEL_OUTPUT = ".output"; - enum class e_arch_format { VTR, /// #include +#include +#include "logic_types.h" #include "vtr_assert.h" +#include "vtr_list.h" #include "vtr_memory.h" #include "vtr_util.h" @@ -10,7 +13,6 @@ #include "arch_error.h" #include "read_xml_arch_file.h" -#include "read_xml_util.h" /******************** Subroutine declarations ********************************/ @@ -152,7 +154,7 @@ void free_arch(t_arch* arch) { return; } - free_arch_models(arch->models); + arch->models.clear_models(); vtr::release_memory(arch->switches); @@ -160,36 +162,6 @@ void free_arch(t_arch* arch) { vtr::free(arch->architecture_id); - if (arch->model_library) { - for (int i = 0; i < 4; ++i) { - vtr::t_linked_vptr* vptr = arch->model_library[i].pb_types; - while (vptr) { - vtr::t_linked_vptr* vptr_prev = vptr; - vptr = vptr->next; - vtr::free(vptr_prev); - } - } - - vtr::free(arch->model_library[0].name); - vtr::free(arch->model_library[0].outputs->name); - delete[] arch->model_library[0].outputs; - vtr::free(arch->model_library[1].inputs->name); - delete[] arch->model_library[1].inputs; - vtr::free(arch->model_library[1].name); - vtr::free(arch->model_library[2].name); - vtr::free(arch->model_library[2].inputs[0].name); - vtr::free(arch->model_library[2].inputs[1].name); - delete[] arch->model_library[2].inputs; - vtr::free(arch->model_library[2].outputs->name); - delete[] arch->model_library[2].outputs; - vtr::free(arch->model_library[3].name); - vtr::free(arch->model_library[3].inputs->name); - delete[] arch->model_library[3].inputs; - vtr::free(arch->model_library[3].outputs->name); - delete[] arch->model_library[3].outputs; - delete[] arch->model_library; - } - if (arch->clocks) { vtr::free(arch->clocks->clock_inf); } @@ -197,58 +169,6 @@ void free_arch(t_arch* arch) { delete (arch->noc); } -//Frees all models in the linked list -void free_arch_models(t_model* models) { - t_model* model = models; - while (model) { - model = free_arch_model(model); - } -} - -//Frees the specified model, and returns the next model (if any) in the linked list -t_model* free_arch_model(t_model* model) { - if (!model) return nullptr; - - t_model* next_model = model->next; - - free_arch_model_ports(model->inputs); - free_arch_model_ports(model->outputs); - - vtr::t_linked_vptr* vptr = model->pb_types; - while (vptr) { - vtr::t_linked_vptr* vptr_prev = vptr; - vptr = vptr->next; - vtr::free(vptr_prev); - } - - if (model->instances) - vtr::free(model->instances); - vtr::free(model->name); - delete model; - - return next_model; -} - -//Frees all the model ports in a linked list -void free_arch_model_ports(t_model_ports* model_ports) { - t_model_ports* model_port = model_ports; - while (model_port) { - model_port = free_arch_model_port(model_port); - } -} - -//Frees the specified model_port, and returns the next model_port (if any) in the linked list -t_model_ports* free_arch_model_port(t_model_ports* model_port) { - if (!model_port) return nullptr; - - t_model_ports* next_port = model_port->next; - - vtr::free(model_port->name); - delete model_port; - - return next_port; -} - void free_type_descriptors(std::vector& type_descriptors) { for (t_physical_tile_type& type : type_descriptors) { vtr::release_memory(type.name); @@ -524,7 +444,7 @@ t_physical_tile_type get_empty_physical_type(const char* name /*= EMPTY_BLOCK_NA type.capacity = 0; type.num_drivers = 0; type.num_receivers = 0; - type.area = UNDEFINED; + type.area = ARCH_FPGA_UNDEFINED_VAL; type.switchblock_locations = vtr::Matrix({{size_t(type.width), size_t(type.height)}}, e_sb_type::FULL); type.switchblock_switch_overrides = vtr::Matrix({{size_t(type.width), size_t(type.height)}}, DEFAULT_SWITCH); type.is_input_type = false; @@ -565,7 +485,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->blif_model = vtr::strdup(pb_type->blif_model); copy->class_type = pb_type->class_type; copy->depth = pb_type->depth; - copy->model = pb_type->model; + copy->model_id = pb_type->model_id; copy->modes = nullptr; copy->num_modes = 0; copy->num_clock_pins = pb_type->num_clock_pins; @@ -799,7 +719,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { free(lut_pb_type->blif_model); lut_pb_type->blif_model = nullptr; - lut_pb_type->model = nullptr; + lut_pb_type->model_id = LogicalModelId::INVALID(); } /* populate special memory class */ @@ -848,7 +768,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { free(mem_pb_type->blif_model); mem_pb_type->blif_model = nullptr; - mem_pb_type->model = nullptr; + mem_pb_type->model_id = LogicalModelId::INVALID(); mem_pb_type->modes[0].num_interconnect = mem_pb_type->num_ports * num_pb; VTR_ASSERT(mem_pb_type->modes[0].num_interconnect > 0); @@ -990,105 +910,6 @@ e_power_estimation_method power_method_inherited(e_power_estimation_method paren } } -void CreateModelLibrary(t_arch* arch) { - t_model* model_library; - - model_library = new t_model[4]; - - //INPAD - model_library[0].name = vtr::strdup(MODEL_INPUT); - model_library[0].index = 0; - model_library[0].inputs = nullptr; - model_library[0].instances = nullptr; - model_library[0].next = &model_library[1]; - model_library[0].outputs = new t_model_ports[1]; - model_library[0].outputs->dir = OUT_PORT; - model_library[0].outputs->name = vtr::strdup("inpad"); - model_library[0].outputs->next = nullptr; - model_library[0].outputs->size = 1; - model_library[0].outputs->min_size = 1; - model_library[0].outputs->index = 0; - model_library[0].outputs->is_clock = false; - - //OUTPAD - model_library[1].name = vtr::strdup(MODEL_OUTPUT); - model_library[1].index = 1; - model_library[1].inputs = new t_model_ports[1]; - model_library[1].inputs->dir = IN_PORT; - model_library[1].inputs->name = vtr::strdup("outpad"); - model_library[1].inputs->next = nullptr; - model_library[1].inputs->size = 1; - model_library[1].inputs->min_size = 1; - model_library[1].inputs->index = 0; - model_library[1].inputs->is_clock = false; - model_library[1].instances = nullptr; - model_library[1].next = &model_library[2]; - model_library[1].outputs = nullptr; - - //LATCH - model_library[2].name = vtr::strdup(MODEL_LATCH); - model_library[2].index = 2; - model_library[2].inputs = new t_model_ports[2]; - - model_library[2].inputs[0].dir = IN_PORT; - model_library[2].inputs[0].name = vtr::strdup("D"); - model_library[2].inputs[0].next = &model_library[2].inputs[1]; - model_library[2].inputs[0].size = 1; - model_library[2].inputs[0].min_size = 1; - model_library[2].inputs[0].index = 0; - model_library[2].inputs[0].is_clock = false; - model_library[2].inputs[0].clock = "clk"; - - model_library[2].inputs[1].dir = IN_PORT; - model_library[2].inputs[1].name = vtr::strdup("clk"); - model_library[2].inputs[1].next = nullptr; - model_library[2].inputs[1].size = 1; - model_library[2].inputs[1].min_size = 1; - model_library[2].inputs[1].index = 0; - model_library[2].inputs[1].is_clock = true; - - model_library[2].instances = nullptr; - model_library[2].next = &model_library[3]; - - model_library[2].outputs = new t_model_ports[1]; - model_library[2].outputs[0].dir = OUT_PORT; - model_library[2].outputs[0].name = vtr::strdup("Q"); - model_library[2].outputs[0].next = nullptr; - model_library[2].outputs[0].size = 1; - model_library[2].outputs[0].min_size = 1; - model_library[2].outputs[0].index = 0; - model_library[2].outputs[0].is_clock = false; - model_library[2].outputs[0].clock = "clk"; - - //NAMES - model_library[3].name = vtr::strdup(MODEL_NAMES); - model_library[3].index = 3; - - model_library[3].inputs = new t_model_ports[1]; - model_library[3].inputs[0].dir = IN_PORT; - model_library[3].inputs[0].name = vtr::strdup("in"); - model_library[3].inputs[0].next = nullptr; - model_library[3].inputs[0].size = 1; - model_library[3].inputs[0].min_size = 1; - model_library[3].inputs[0].index = 0; - model_library[3].inputs[0].is_clock = false; - model_library[3].inputs[0].combinational_sink_ports = {"out"}; - - model_library[3].instances = nullptr; - model_library[3].next = nullptr; - - model_library[3].outputs = new t_model_ports[1]; - model_library[3].outputs[0].dir = OUT_PORT; - model_library[3].outputs[0].name = vtr::strdup("out"); - model_library[3].outputs[0].next = nullptr; - model_library[3].outputs[0].size = 1; - model_library[3].outputs[0].min_size = 1; - model_library[3].outputs[0].index = 0; - model_library[3].outputs[0].is_clock = false; - - arch->model_library = model_library; -} - void SyncModelsPbTypes(t_arch* arch, const std::vector& Types) { for (auto& Type : Types) { @@ -1100,16 +921,10 @@ void SyncModelsPbTypes(t_arch* arch, void SyncModelsPbTypes_rec(t_arch* arch, t_pb_type* pb_type) { - t_model *model_match_prim, *cur_model; - t_model_ports* model_port; - vtr::t_linked_vptr* old; - char* blif_model_name = nullptr; - - bool found; if (pb_type->blif_model != nullptr) { /* get actual name of subckt */ - blif_model_name = pb_type->blif_model; + char* blif_model_name = pb_type->blif_model; if (strstr(blif_model_name, ".subckt ") == blif_model_name) { blif_model_name = strchr(blif_model_name, ' '); ++blif_model_name; //Advance past space @@ -1120,39 +935,24 @@ void SyncModelsPbTypes_rec(t_arch* arch, pb_type->blif_model, pb_type->name); } - /* There are two sets of models to consider, the standard library of models and the user defined models */ - if (is_library_model(blif_model_name)) { - cur_model = arch->model_library; - } else { - cur_model = arch->models; - } - /* Determine the logical model to use */ - found = false; - model_match_prim = nullptr; - while (cur_model && !found) { - /* blif model always starts with .subckt so need to skip first 8 characters */ - if (strcmp(blif_model_name, cur_model->name) == 0) { - found = true; - model_match_prim = cur_model; - } - cur_model = cur_model->next; - } - if (!found) { + LogicalModelId model_match_prim_id = arch->models.get_model_by_name(blif_model_name); + if (!model_match_prim_id.is_valid()) { archfpga_throw(get_arch_file_name(), 0, "No matching model for pb_type %s\n", pb_type->blif_model); } + t_model& model_match_prim = arch->models.get_model(model_match_prim_id); - pb_type->model = model_match_prim; - old = model_match_prim->pb_types; - model_match_prim->pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr)); - model_match_prim->pb_types->next = old; - model_match_prim->pb_types->data_vptr = pb_type; + pb_type->model_id = model_match_prim_id; + vtr::t_linked_vptr* old = model_match_prim.pb_types; + model_match_prim.pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr)); + model_match_prim.pb_types->next = old; + model_match_prim.pb_types->data_vptr = pb_type; for (int p = 0; p < pb_type->num_ports; p++) { - found = false; + bool found = false; /* TODO: Parse error checking - check if INPUT matches INPUT and OUTPUT matches OUTPUT (not yet done) */ - model_port = model_match_prim->inputs; + t_model_ports* model_port = model_match_prim.inputs; while (model_port && !found) { if (strcmp(model_port->name, pb_type->ports[p].name) == 0) { if (model_port->size < pb_type->ports[p].num_pins) { @@ -1177,7 +977,7 @@ void SyncModelsPbTypes_rec(t_arch* arch, } model_port = model_port->next; } - model_port = model_match_prim->outputs; + model_port = model_match_prim.outputs; while (model_port && !found) { if (strcmp(model_port->name, pb_type->ports[p].name) == 0) { if (model_port->size < pb_type->ports[p].num_pins) { @@ -1261,20 +1061,6 @@ bool segment_exists(const t_arch* arch, std::string_view name) { return find_segment(arch, name) != nullptr; } -bool is_library_model(const char* model_name) { - if (model_name == std::string(MODEL_NAMES) - || model_name == std::string(MODEL_LATCH) - || model_name == std::string(MODEL_INPUT) - || model_name == std::string(MODEL_OUTPUT)) { - return true; - } - return false; -} - -bool is_library_model(const t_model* model) { - return is_library_model(model->name); -} - //Returns true if the specified block type contains the specified blif model name // // TODO: Remove block_type_contains_blif_model / pb_type_contains_blif_model @@ -1292,7 +1078,7 @@ bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::string& bl if (pb_type->blif_model != nullptr) { //Leaf pb_type - VTR_ASSERT(pb_type->num_modes == 0); + VTR_ASSERT(pb_type->is_primitive()); if (blif_model_name == pb_type->blif_model || ".subckt " + blif_model_name == pb_type->blif_model) { return true; diff --git a/libs/libarchfpga/src/arch_util.h b/libs/libarchfpga/src/arch_util.h index fb251bffe10..fb87262878c 100644 --- a/libs/libarchfpga/src/arch_util.h +++ b/libs/libarchfpga/src/arch_util.h @@ -52,10 +52,6 @@ class InstPort { }; void free_arch(t_arch* arch); -void free_arch_models(t_model* models); -t_model* free_arch_model(t_model* model); -void free_arch_model_ports(t_model_ports* model_ports); -t_model_ports* free_arch_model_port(t_model_ports* model_port); void free_type_descriptors(std::vector& type_descriptors); void free_type_descriptors(std::vector& type_descriptors); @@ -84,8 +80,6 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type); e_power_estimation_method power_method_inherited(e_power_estimation_method parent_power_method); -void CreateModelLibrary(t_arch* arch); - void SyncModelsPbTypes(t_arch* arch, const std::vector& Types); @@ -97,8 +91,6 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, bool segment_exists(const t_arch* arch, std::string_view name); const t_segment_inf* find_segment(const t_arch* arch, std::string_view name); -bool is_library_model(const char* model_name); -bool is_library_model(const t_model* model); //Returns true if the specified block type contains the specified blif model name bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::string& blif_model_name); diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index edceeb748fb..2e08c196946 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -1,24 +1,22 @@ #include #include #include -#include #include "echo_arch.h" -#include "arch_types.h" #include "arch_util.h" +#include "logic_types.h" #include "vtr_list.h" #include "vtr_util.h" #include "vtr_memory.h" #include "vtr_assert.h" -using vtr::t_linked_vptr; - /// @brief indices to lookup IPIN connection block switch name constexpr int ipin_cblock_switch_index_within_die = 0; constexpr int ipin_cblock_switch_index_between_dice = 1; void PrintArchInfo(FILE* Echo, const t_arch* arch); -static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level); +static void print_model(FILE* echo, const t_model& model); +static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models); static void PrintPb_types_recPower(FILE* Echo, const t_pb_type* pb_type, const char* tabs); @@ -29,55 +27,21 @@ void EchoArch(const char* EchoFile, const std::vector& PhysicalTileTypes, const std::vector& LogicalBlockTypes, const t_arch* arch) { - int i, j; - FILE* Echo; - t_model* cur_model; - t_model_ports* model_port; - t_linked_vptr* cur_vptr; - Echo = vtr::fopen(EchoFile, "w"); - cur_model = nullptr; + FILE* Echo = vtr::fopen(EchoFile, "w"); //Print all layout device switch/segment list info first PrintArchInfo(Echo, arch); //Models fprintf(Echo, "*************************************************\n"); - for (j = 0; j < 2; j++) { - if (j == 0) { - fprintf(Echo, "Printing user models \n"); - cur_model = arch->models; - } else if (j == 1) { - fprintf(Echo, "Printing library models \n"); - cur_model = arch->model_library; - } - while (cur_model) { - fprintf(Echo, "Model: \"%s\"\n", cur_model->name); - model_port = cur_model->inputs; - while (model_port) { - fprintf(Echo, "\tInput Ports: \"%s\" \"%d\" min_size=\"%d\"\n", - model_port->name, model_port->size, - model_port->min_size); - model_port = model_port->next; - } - model_port = cur_model->outputs; - while (model_port) { - fprintf(Echo, "\tOutput Ports: \"%s\" \"%d\" min_size=\"%d\"\n", - model_port->name, model_port->size, - model_port->min_size); - model_port = model_port->next; - } - cur_vptr = cur_model->pb_types; - i = 0; - while (cur_vptr != nullptr) { - fprintf(Echo, "\tpb_type %d: \"%s\"\n", i, - ((t_pb_type*)cur_vptr->data_vptr)->name); - cur_vptr = cur_vptr->next; - i++; - } - - cur_model = cur_model->next; - } + fprintf(Echo, "Printing library models \n"); + for (LogicalModelId model_id : arch->models.library_models()) { + print_model(Echo, arch->models.get_model(model_id)); + } + fprintf(Echo, "Printing user models \n"); + for (LogicalModelId model_id : arch->models.user_models()) { + print_model(Echo, arch->models.get_model(model_id)); } fprintf(Echo, "*************************************************\n\n"); fprintf(Echo, "*************************************************\n"); @@ -122,7 +86,7 @@ void EchoArch(const char* EchoFile, for (auto& LogicalBlock : LogicalBlockTypes) { if (LogicalBlock.pb_type) { - PrintPb_types_rec(Echo, LogicalBlock.pb_type, 2); + PrintPb_types_rec(Echo, LogicalBlock.pb_type, 2, arch->models); } fprintf(Echo, "\n"); } @@ -390,7 +354,33 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { fprintf(Echo, "*************************************************\n\n"); } -static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { +static void print_model(FILE* echo, const t_model& model) { + fprintf(echo, "Model: \"%s\"\n", model.name); + t_model_ports* input_model_port = model.inputs; + while (input_model_port) { + fprintf(echo, "\tInput Ports: \"%s\" \"%d\" min_size=\"%d\"\n", + input_model_port->name, input_model_port->size, + input_model_port->min_size); + input_model_port = input_model_port->next; + } + t_model_ports* output_model_port = model.outputs; + while (output_model_port) { + fprintf(echo, "\tOutput Ports: \"%s\" \"%d\" min_size=\"%d\"\n", + output_model_port->name, output_model_port->size, + output_model_port->min_size); + output_model_port = output_model_port->next; + } + vtr::t_linked_vptr* cur_vptr = model.pb_types; + int i = 0; + while (cur_vptr != nullptr) { + fprintf(echo, "\tpb_type %d: \"%s\"\n", i, + ((t_pb_type*)cur_vptr->data_vptr)->name); + cur_vptr = cur_vptr->next; + i++; + } +} + +static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models) { char* tabs; tabs = (char*)vtr::malloc((level + 1) * sizeof(char)); @@ -415,7 +405,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { fprintf(Echo, "%s\tmode %s:\n", tabs, pb_type->modes[i].name); for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { PrintPb_types_rec(Echo, &pb_type->modes[i].pb_type_children[j], - level + 2); + level + 2, models); } for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) { fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs, @@ -447,9 +437,10 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { * I/O has no annotations to be displayed * All other library or user models may have delays specificied, e.g. Tsetup and Tcq * Display the additional information*/ - if (strcmp(pb_type->model->name, MODEL_NAMES) - && strcmp(pb_type->model->name, MODEL_INPUT) - && strcmp(pb_type->model->name, MODEL_OUTPUT)) { + std::string pb_type_model_name = models.get_model(pb_type->model_id).name; + if (pb_type_model_name != LogicalModels::MODEL_NAMES + && pb_type_model_name != LogicalModels::MODEL_INPUT + && pb_type_model_name != LogicalModels::MODEL_OUTPUT) { for (int k = 0; k < pb_type->num_annotations; k++) { fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs, pb_type->annotations[k].clock, diff --git a/libs/libarchfpga/src/logic_types.cpp b/libs/libarchfpga/src/logic_types.cpp new file mode 100644 index 00000000000..dc4801d3347 --- /dev/null +++ b/libs/libarchfpga/src/logic_types.cpp @@ -0,0 +1,171 @@ +/** + * @file + * @author Alex Singer + * @date April 2025 + * @brief Implementation of the LogicalModels data structure. + */ + +#include "logic_types.h" +#include "vtr_assert.h" +#include "vtr_util.h" + +/** + * @brief Frees all the model ports in a linked list + */ +static void free_arch_model_ports(t_model_ports* model_ports); + +/** + * @brief Frees the specified model_port, and returns the next model_port (if + * any) in the linked list + */ +static t_model_ports* free_arch_model_port(t_model_ports* model_port); + +LogicalModels::LogicalModels() { + // Create the logical models. These must be created first and stored at the + // start of the list of models. + VTR_ASSERT_MSG(all_models().size() == 0, + "The first models created must be the library models"); + //INPAD + { + LogicalModelId inpad_model_id = create_logical_model(MODEL_INPUT); + t_model& inpad_model = get_model(inpad_model_id); + + inpad_model.inputs = nullptr; + + inpad_model.instances = nullptr; + + inpad_model.outputs = new t_model_ports; + inpad_model.outputs->dir = OUT_PORT; + inpad_model.outputs->name = vtr::strdup("inpad"); + inpad_model.outputs->next = nullptr; + inpad_model.outputs->size = 1; + inpad_model.outputs->min_size = 1; + inpad_model.outputs->index = 0; + inpad_model.outputs->is_clock = false; + } + + //OUTPAD + { + LogicalModelId outpad_model_id = create_logical_model(MODEL_OUTPUT); + t_model& outpad_model = get_model(outpad_model_id); + + outpad_model.inputs = new t_model_ports; + outpad_model.inputs->dir = IN_PORT; + outpad_model.inputs->name = vtr::strdup("outpad"); + outpad_model.inputs->next = nullptr; + outpad_model.inputs->size = 1; + outpad_model.inputs->min_size = 1; + outpad_model.inputs->index = 0; + outpad_model.inputs->is_clock = false; + + outpad_model.instances = nullptr; + + outpad_model.outputs = nullptr; + } + + //LATCH + { + LogicalModelId latch_model_id = create_logical_model(MODEL_LATCH); + t_model& latch_model = get_model(latch_model_id); + t_model_ports* latch_model_input_port_1 = new t_model_ports; + t_model_ports* latch_model_input_port_2 = new t_model_ports; + + latch_model.inputs = latch_model_input_port_1; + latch_model_input_port_1->dir = IN_PORT; + latch_model_input_port_1->name = vtr::strdup("D"); + latch_model_input_port_1->next = latch_model_input_port_2; + latch_model_input_port_1->size = 1; + latch_model_input_port_1->min_size = 1; + latch_model_input_port_1->index = 0; + latch_model_input_port_1->is_clock = false; + latch_model_input_port_1->clock = "clk"; + + latch_model_input_port_2->dir = IN_PORT; + latch_model_input_port_2->name = vtr::strdup("clk"); + latch_model_input_port_2->next = nullptr; + latch_model_input_port_2->size = 1; + latch_model_input_port_2->min_size = 1; + latch_model_input_port_2->index = 0; + latch_model_input_port_2->is_clock = true; + + latch_model.instances = nullptr; + + latch_model.outputs = new t_model_ports; + latch_model.outputs->dir = OUT_PORT; + latch_model.outputs->name = vtr::strdup("Q"); + latch_model.outputs->next = nullptr; + latch_model.outputs->size = 1; + latch_model.outputs->min_size = 1; + latch_model.outputs->index = 0; + latch_model.outputs->is_clock = false; + latch_model.outputs->clock = "clk"; + } + + //NAMES + { + LogicalModelId names_model_id = create_logical_model(MODEL_NAMES); + t_model& names_model = get_model(names_model_id); + + names_model.inputs = new t_model_ports; + names_model.inputs->dir = IN_PORT; + names_model.inputs->name = vtr::strdup("in"); + names_model.inputs->next = nullptr; + names_model.inputs->size = 1; + names_model.inputs->min_size = 1; + names_model.inputs->index = 0; + names_model.inputs->is_clock = false; + names_model.inputs->combinational_sink_ports = {"out"}; + + names_model.instances = nullptr; + + names_model.outputs = new t_model_ports; + names_model.outputs->dir = OUT_PORT; + names_model.outputs->name = vtr::strdup("out"); + names_model.outputs->next = nullptr; + names_model.outputs->size = 1; + names_model.outputs->min_size = 1; + names_model.outputs->index = 0; + names_model.outputs->is_clock = false; + } + + // Checks to ensure that all library models have been successfully created + // and the number of library models matches the NUM_MODELS_IN_LIBRARY variable. + VTR_ASSERT_MSG(all_models().size() == library_models().size(), + "The only models that have been created should be the library models"); + VTR_ASSERT_MSG(library_models().size() == NUM_MODELS_IN_LIBRARY, + "The number of models in the library must be the expected number"); +} + +void LogicalModels::free_model_data(t_model& model) { + free_arch_model_ports(model.inputs); + free_arch_model_ports(model.outputs); + + vtr::t_linked_vptr* vptr = model.pb_types; + while (vptr) { + vtr::t_linked_vptr* vptr_prev = vptr; + vptr = vptr->next; + vtr::free(vptr_prev); + } + + if (model.instances) + vtr::free(model.instances); + vtr::free(model.name); +} + +static void free_arch_model_ports(t_model_ports* model_ports) { + t_model_ports* model_port = model_ports; + while (model_port) { + model_port = free_arch_model_port(model_port); + } +} + +static t_model_ports* free_arch_model_port(t_model_ports* model_port) { + if (!model_port) return nullptr; + + t_model_ports* next_port = model_port->next; + + vtr::free(model_port->name); + delete model_port; + + return next_port; +} diff --git a/libs/libarchfpga/src/logic_types.h b/libs/libarchfpga/src/logic_types.h index 4427b85016f..0a23b23d8e9 100644 --- a/libs/libarchfpga/src/logic_types.h +++ b/libs/libarchfpga/src/logic_types.h @@ -5,12 +5,22 @@ * * Date: February 19, 2009 * Authors: Jason Luu and Kenneth Kent + * + * Updated with the LogicalModels data structure by Alex Singer + * Date: April, 2025 */ #ifndef LOGIC_TYPES_H #define LOGIC_TYPES_H +#include "vtr_assert.h" #include "vtr_list.h" +#include "vtr_memory.h" +#include "vtr_range.h" +#include "vtr_strong_id.h" +#include "vtr_util.h" +#include "vtr_vector_map.h" +#include #include #include @@ -40,18 +50,223 @@ struct t_model_ports { int index = -1; /* indexing for array look-up */ }; +/** + * @brief Struct containing the information stored for a logical model in the + * LogicalModels storage class below. + */ struct t_model { - char* name = nullptr; /* name of this logic model */ - t_model_ports* inputs = nullptr; /* linked list of input/clock ports */ - t_model_ports* outputs = nullptr; /* linked list of output ports */ - void* instances = nullptr; - int used = 0; - vtr::t_linked_vptr* pb_types = nullptr; /* Physical block types that implement this model */ - t_model* next = nullptr; /* next model (linked list) */ + char* name = nullptr; ///< name of this logic model + t_model_ports* inputs = nullptr; ///< linked list of input/clock ports + t_model_ports* outputs = nullptr; ///< linked list of output ports + void* instances = nullptr; ///< TODO: Remove this. This is only used in the Parmys plugin and should be moved into there. + int used = 0; ///< TODO: Remove this. This is only used in the Parmys plugin and should be moved into there. + vtr::t_linked_vptr* pb_types = nullptr; ///< Physical block types that implement this model + bool never_prune = false; ///< Don't remove from the netlist even if a block of this type has no output ports used and, therefore, unconnected to the rest of the netlist +}; + +// Tag for the logical model ID +struct logical_model_id_tag; +// A unique ID that represents a logical model in the architecture. +typedef vtr::StrongId LogicalModelId; + +/** + * @brief A storage class containing all of the logical models in an FPGA + * architecture. + * + * This class manages creating, storing, and destroying logical models. It also + * contains helper methods to parse the logical models. + * + * A logical model is the definition of a type of primitive block that can occur + * in the atom netlist for a given FPGA architecture; it stores data that all + * block instances of that type share. + * + * There are two types of logical models: + * 1) Library Models: These are models that all architectures share. These are + * created in the construtor of this class. + * 2) User Models: These are models defined by the user and are created outside + * of this class (usually by parsing an architecture file). + */ +class LogicalModels { + public: + // The total number of predefined blif models. + static constexpr size_t NUM_MODELS_IN_LIBRARY = 4; + + // Built-in library model names. + static constexpr const char* MODEL_NAMES = ".names"; + static constexpr const char* MODEL_LATCH = ".latch"; + static constexpr const char* MODEL_INPUT = ".input"; + static constexpr const char* MODEL_OUTPUT = ".output"; + + // Iterator for the logical model IDs array. + typedef typename vtr::vector_map::const_iterator model_iterator; + + // A range of model IDs within the logical model IDs array. + typedef typename vtr::Range model_range; + + public: + // Since this class maintaines pointers and these pointers are freed upon + // destruction, this class cannot (and should not) be copied. + LogicalModels(const LogicalModels&) = delete; + LogicalModels& operator=(const LogicalModels&) = delete; + + /** + * @brief The constructor of the LogicalModels class. + * + * This populates the library models. + */ + LogicalModels(); + + ~LogicalModels() { + // Free the data of all models. + clear_models(); + } + + /** + * @brief Returns a range of logical model IDs representing all models in + * the architecture (both library and user models). + */ + inline model_range all_models() const { + return vtr::make_range(logical_model_ids_.begin(), logical_model_ids_.end()); + } + + /** + * @brief Returns a range of logical model IDs representing all library + * models in the architecture. + */ + inline model_range library_models() const { + VTR_ASSERT_SAFE_MSG(logical_model_ids_.size() >= NUM_MODELS_IN_LIBRARY, + "Library models missing"); + // The library models are created in the constructor, thus they must be + // the first L models in the IDs (where L is the number of library models). + return vtr::make_range(logical_model_ids_.begin(), + logical_model_ids_.begin() + NUM_MODELS_IN_LIBRARY); + } + + /** + * @brief Returns a range of logical model IDs representing all user models + * in the architecture. + */ + inline model_range user_models() const { + VTR_ASSERT_SAFE_MSG(logical_model_ids_.size() >= NUM_MODELS_IN_LIBRARY, + "Library models missing"); + + // The user models will always be located after the library models since + // the library models were added in the constructor. + return vtr::make_range(logical_model_ids_.begin() + NUM_MODELS_IN_LIBRARY, + logical_model_ids_.end()); + } + + /** + * @brief Returns true if the given model ID represents a library model. + */ + inline bool is_library_model(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Invalid model ID"); + // The first L model IDs must be the library models. Where L is the + // number of models in the library + if ((size_t)model_id < NUM_MODELS_IN_LIBRARY) + return true; + + return false; + } + + /** + * @brief Create a logical model with the given name. + * + * This method will construct a t_model object with the given name. This + * object can be accessed and modified using the get_model method. + * + * @return The ID of the newly created model. + */ + inline LogicalModelId create_logical_model(const std::string& model_name) { + VTR_ASSERT_MSG(model_name_to_logical_model_id_.count(model_name) == 0, + "A model with the given name already exists"); + // Create the new model. + t_model new_model; + new_model.name = vtr::strdup(model_name.c_str()); + + // Create the new model's ID + LogicalModelId new_model_id = LogicalModelId(logical_model_ids_.size()); + + // Update the internal state. + logical_models_.push_back(std::move(new_model)); + logical_model_ids_.push_back(new_model_id); + model_name_to_logical_model_id_[model_name] = new_model_id; + + return new_model_id; + } + + /** + * @brief Immutable accessor to the underlying model data structure for the + * given model ID. + */ + inline const t_model& get_model(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Cannot get model of invalid model ID"); + return logical_models_[model_id]; + } + + /** + * @brief Mutable accessor to the underlying model data structure for the + * given model ID. + */ + inline t_model& get_model(LogicalModelId model_id) { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Cannot get model of invalid model ID"); + return logical_models_[model_id]; + } + + /** + * @brief Returns the name of the given model. + */ + inline std::string model_name(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Cannot get name of invalid model ID"); + return logical_models_[model_id].name; + } + + /** + * @brief Returns the ID of the model with the given name. If no model has + * the given name, the invalid model ID will be returned. + * + * This method has O(1) time complexity. + */ + inline LogicalModelId get_model_by_name(std::string model_name) const { + auto itr = model_name_to_logical_model_id_.find(model_name); + if (itr == model_name_to_logical_model_id_.end()) + return LogicalModelId::INVALID(); + return itr->second; + } + + /** + * @brief Destroys all of the models. This frees all internal model data. + */ + void clear_models() { + // Free the model data of all models. + for (LogicalModelId model_id : all_models()) { + free_model_data(logical_models_[model_id]); + } + // Clear all data structures. + logical_model_ids_.clear(); + logical_models_.clear(); + model_name_to_logical_model_id_.clear(); + } + + private: + /** + * @brief Helper method for freeing the internal data of the given model. + */ + void free_model_data(t_model& model); + + private: + /// @brief A list of all logical model IDs. + vtr::vector_map logical_model_ids_; - bool never_prune = false; /* Don't remove from the netlist even if a block of this type has no output ports used and, therefore, unconnected to the rest of the netlist */ + /// @brief A list of a logical models. + vtr::vector_map logical_models_; - int index = -1; + /// @brief A lookup between the name of a logical model and its ID. + std::unordered_map model_name_to_logical_model_id_; }; #endif diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 9b72cb95758..6032bcb6d26 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -252,7 +252,71 @@ const t_port* t_logical_block_type::get_port_by_pin(int pin) const { return nullptr; } -/** +/* + * t_pb_type + */ + +int t_pb_type::get_max_primitives() const { + int max_size; + + if (modes == nullptr) { + max_size = 1; + } else { + max_size = 0; + int temp_size = 0; + for (int i = 0; i < num_modes; i++) { + for (int j = 0; j < modes[i].num_pb_type_children; j++) { + temp_size += modes[i].pb_type_children[j].num_pb * modes[i].pb_type_children[j].get_max_primitives(); + } + if (temp_size > max_size) { + max_size = temp_size; + } + } + } + + return max_size; +} + +/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */ +int t_pb_type::get_max_nets() const { + int max_nets; + if (modes == nullptr) { + max_nets = num_output_pins; + } else { + max_nets = 0; + + for (int i = 0; i < num_modes; i++) { + int temp_nets = 0; + for (int j = 0; j < modes[i].num_pb_type_children; j++) { + temp_nets += modes[i].pb_type_children[j].num_pb * modes[i].pb_type_children[j].get_max_nets(); + } + + if (temp_nets > max_nets) { + max_nets = temp_nets; + } + } + } + + if (is_root()) { + max_nets += num_input_pins + num_output_pins + num_clock_pins; + } + + return max_nets; +} + +int t_pb_type::get_max_depth() const { + int max_depth = depth; + + for (int i = 0; i < num_modes; i++) { + for (int j = 0; j < modes[i].num_pb_type_children; j++) { + int temp_depth = modes[i].pb_type_children[j].get_max_depth(); + max_depth = std::max(max_depth, temp_depth); + } + } + return max_depth; +} + +/* * t_pb_graph_node */ diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 19a625db601..f5ffa481395 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -730,6 +730,11 @@ struct t_physical_tile_type { ///@brief Is this t_physical_tile_type an empty type? bool is_empty() const; + ///@brief Returns true if the physical tile type can implement either a .input or .output block type + inline bool is_io() const { + return is_input_type || is_output_type; + } + ///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port int find_pin(std::string_view port_name, int pin_index_in_port) const; @@ -1047,7 +1052,7 @@ struct t_pb_type { char* name = nullptr; int num_pb = 0; char* blif_model = nullptr; - t_model* model = nullptr; + LogicalModelId model_id; enum e_pb_type_class class_type = UNKNOWN_CLASS; t_mode* modes = nullptr; /* [0..num_modes-1] */ @@ -1073,6 +1078,29 @@ struct t_pb_type { t_pb_type_power* pb_type_power = nullptr; t_metadata_dict meta; + + /** + * @brief Check if t_pb_type is the root of the pb graph. Root pb_types correspond to a single top level block type and map to a particular type + * of location in the FPGA device grid (e.g. Logic, DSP, RAM etc.) + * + * @return if t_pb_type is root ot not + */ + inline bool is_root() const { + return parent_mode == nullptr; + } + + /** + * @brief Check if t_pb_type is a primitive block or equivalently a leaf of the pb graph. + * + * @return if t_pb_type is primitive/leaf ot not + */ + inline bool is_primitive() const { + return num_modes == 0; + } + + int get_max_primitives() const; + int get_max_depth() const; + int get_max_nets() const; }; /** Describes an operational mode of a clustered logic block @@ -1358,7 +1386,7 @@ class t_pb_graph_node { t_interconnect_pins** interconnect_pins; /* [0..num_modes-1][0..num_interconnect_in_mode] */ // Returns true if this pb_graph_node represents a primitive type (primitives have 0 modes) - bool is_primitive() const { return this->pb_type->num_modes == 0; } + bool is_primitive() const { return this->pb_type->is_primitive(); } // Returns true if this pb_graph_node represents a root graph node (ex. clb) bool is_root() const { return this->parent_pb_graph_node == nullptr; } @@ -1629,65 +1657,65 @@ enum e_Fc_type { */ struct t_segment_inf { /** - * @brief The name of the segment type + * @brief The name of the segment type */ std::string name; /** - * @brief ratio of tracks which are of this segment type. + * @brief ratio of tracks which are of this segment type. */ int frequency; /** - * @brief Length (in clbs) of the segment. + * @brief Length (in clbs) of the segment. */ int length; /** - * @brief Index of the switch type that connects other wires to this segment. - * Note that this index is in relation to the switches from the architecture file, - * not the expanded list of switches that is built at the end of build_rr_graph. + * @brief Index of the switch type that connects other wires to this segment. + * Note that this index is in relation to the switches from the architecture file, + * not the expanded list of switches that is built at the end of build_rr_graph. */ short arch_wire_switch; /** - * @brief Index of the switch type that connects output pins to this segment. - * Note that this index is in relation to the switches from the architecture file, - * not the expanded list of switches that is built at the end of build_rr_graph. + * @brief Index of the switch type that connects output pins to this segment. + * Note that this index is in relation to the switches from the architecture file, + * not the expanded list of switches that is built at the end of build_rr_graph. */ short arch_opin_switch; /** - * @brief Same as arch_wire_switch but used only for decremental tracks if it is - * specified in the architecture file. If -1, this value was not set in the - * architecture file and arch_wire_switch should be used for "DEC_DIR" wire segments. + * @brief Same as arch_wire_switch but used only for decremental tracks if it is + * specified in the architecture file. If -1, this value was not set in the + * architecture file and arch_wire_switch should be used for "DEC_DIR" wire segments. */ short arch_wire_switch_dec = -1; /** - * @brief Same as arch_opin_switch but used only for decremental tracks if - * it is specified in the architecture file. If -1, this value was not set in - * the architecture file and arch_opin_switch should be used for "DEC_DIR" wire segments. + * @brief Same as arch_opin_switch but used only for decremental tracks if + * it is specified in the architecture file. If -1, this value was not set in + * the architecture file and arch_opin_switch should be used for "DEC_DIR" wire segments. */ short arch_opin_switch_dec = -1; /** - * @brief Index of the switch type that connects output pins (OPINs) to this - * segment from another die (layer). Note that this index is in relation to - * the switches from the architecture file, not the expanded list of switches - * that is built at the end of build_rr_graph. + * @brief Index of the switch type that connects output pins (OPINs) to this + * segment from another die (layer). Note that this index is in relation to + * the switches from the architecture file, not the expanded list of switches + * that is built at the end of build_rr_graph. */ short arch_inter_die_switch = -1; /** - * @brief The fraction of logic blocks along its length to which this segment can connect. - * (i.e. internal population). + * @brief The fraction of logic blocks along its length to which this segment can connect. + * (i.e. internal population). */ float frac_cb; /** - * @brief The fraction of the length + 1 switch blocks along the segment to which the segment can connect. - * Segments that aren't long lines must connect to at least two switch boxes. + * @brief The fraction of the length + 1 switch blocks along the segment to which the segment can connect. + * Segments that aren't long lines must connect to at least two switch boxes. */ float frac_sb; @@ -1704,18 +1732,18 @@ struct t_segment_inf { enum e_directionality directionality; /** - * @brief Defines what axis the segment is parallel to. See e_parallel_axis - * comments for more details on the values. + * @brief Defines what axis the segment is parallel to. See e_parallel_axis + * comments for more details on the values. */ enum e_parallel_axis parallel_axis; /** - * @brief A vector of booleans indicating whether the segment can connect to a logic block. + * @brief A vector of booleans indicating whether the segment can connect to a logic block. */ std::vector cb; /** - * @brief A vector of booleans indicating whether the segment can connect to a switch block. + * @brief A vector of booleans indicating whether the segment can connect to a switch block. */ std::vector sb; @@ -1739,10 +1767,10 @@ struct t_segment_inf { /** * @brief The index of the segment as stored in the appropriate Segs list. - * Upon loading the architecture, we use this field to keep track of the - * segment's index in the unified segment_inf vector. This is useful when - * building the rr_graph for different Y & X channels in terms of track - * distribution and segment type. + * Upon loading the architecture, we use this field to keep track of the + * segment's index in the unified segment_inf vector. This is useful when + * building the rr_graph for different Y & X channels in terms of track + * distribution and segment type. */ int seg_index; @@ -1751,7 +1779,7 @@ struct t_segment_inf { * Possible values are: * - GENERAL: The segment is part of the general routing resources. * - GCLK: The segment is part of the global routing network. - * For backward compatibility, this attribute is optional. If not specified, + * For backward compatibility, this attribute is optional. If not specified, * the resource type for the segment is considered to be GENERAL. */ enum SegResType res_type = SegResType::GENERAL; @@ -2214,8 +2242,7 @@ struct t_arch { /// Contains information about all direct chain connections in the architecture std::vector directs; - t_model* models = nullptr; - t_model* model_library = nullptr; + LogicalModels models; t_power_arch* power = nullptr; t_clock_arch* clocks = nullptr; diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 2ecc7fbd41c..74ad3aa6f1e 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -637,21 +637,6 @@ bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from return false; } -// TODO: Remove is_input_type / is_output_type / is_io_type as part of -// https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193 -bool is_input_type(t_physical_tile_type_ptr type) { - return type->is_input_type; -} - -bool is_output_type(t_physical_tile_type_ptr type) { - return type->is_output_type; -} - -bool is_io_type(t_physical_tile_type_ptr type) { - return is_input_type(type) - || is_output_type(type); -} - std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_physical_num, bool is_flat) { int max_ptc = get_tile_pin_max_ptc(type, is_flat); VTR_ASSERT(pin_physical_num < max_ptc); diff --git a/libs/libarchfpga/src/physical_types_util.h b/libs/libarchfpga/src/physical_types_util.h index a081683faeb..84cad62a845 100644 --- a/libs/libarchfpga/src/physical_types_util.h +++ b/libs/libarchfpga/src/physical_types_util.h @@ -120,13 +120,6 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type); ///@brief Returns true if the specified pin is located at "from_layer" and it is connected to "to_layer" bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer, int num_of_avail_layer); -///@brief Returns true if the given physical tile type can implement a .input block type -bool is_input_type(t_physical_tile_type_ptr type); -///@brief Returns true if the given physical tile type can implement a .output block type -bool is_output_type(t_physical_tile_type_ptr type); -///@brief Returns true if the given physical tile type can implement either a .input or .output block type -bool is_io_type(t_physical_tile_type_ptr type); - /** * @brief Returns the corresponding physical pin based on the input parameters: * diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 50840cbb948..265991c23f2 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -1,7 +1,7 @@ #include "read_fpga_interchange_arch.h" -#include "vtr_error.h" +#include "logic_types.h" #ifdef VTR_ENABLE_CAPNPROTO @@ -19,14 +19,12 @@ #include "vtr_assert.h" #include "vtr_digest.h" -#include "vtr_log.h" #include "vtr_memory.h" #include "vtr_util.h" #include "arch_check.h" #include "arch_error.h" #include "arch_util.h" -#include "arch_types.h" /* * FPGA Interchange Device frontend @@ -161,32 +159,28 @@ static float get_corner_value(Device::CornerModel::Reader model, const char* spe } /** @brief Returns the port corresponding to the given model in the architecture */ -static t_model_ports* get_model_port(t_arch* arch, std::string model, std::string port, bool fail = true) { - for (t_model* m : {arch->models, arch->model_library}) { - for (; m != nullptr; m = m->next) { - if (std::string(m->name) != model) - continue; - - for (t_model_ports* p : {m->inputs, m->outputs}) - for (; p != nullptr; p = p->next) - if (std::string(p->name) == port) - return p; - } +static t_model_ports* get_model_port(t_arch* arch, std::string model_name, std::string port, bool fail = true) { + LogicalModelId model_id = arch->models.get_model_by_name(model_name); + if (model_id.is_valid()) { + const t_model& model = arch->models.get_model(model_id); + for (t_model_ports* p : {model.inputs, model.outputs}) + for (; p != nullptr; p = p->next) + if (std::string(p->name) == port) + return p; } if (fail) archfpga_throw(__FILE__, __LINE__, - "Could not find model port: %s (%s)\n", port.c_str(), model.c_str()); + "Could not find model port: %s (%s)\n", port.c_str(), model_name.c_str()); return nullptr; } /** @brief Returns the specified architecture model */ -static t_model* get_model(t_arch* arch, std::string model) { - for (t_model* m : {arch->models, arch->model_library}) - for (; m != nullptr; m = m->next) - if (std::string(m->name) == model) - return m; +static LogicalModelId get_model(t_arch* arch, std::string model) { + LogicalModelId model_id = arch->models.get_model_by_name(model); + if (model_id.is_valid()) + return model_id; archfpga_throw(__FILE__, __LINE__, "Could not find model: %s\n", model.c_str()); @@ -914,16 +908,9 @@ struct ArchReader { // Model processing void process_models() { - // Populate the common library, namely .inputs, .outputs, .names, .latches - CreateModelLibrary(arch_); - - t_model* temp = nullptr; std::map model_name_map; std::pair::iterator, bool> ret_map_name; - int model_index = NUM_MODELS_IN_LIBRARY; - arch_->models = nullptr; - auto primLib = ar_.getPrimLibs(); for (auto primitive : primLib.getCellDecls()) { if (str(primitive.getLib()) == std::string("primitives")) { @@ -951,38 +938,31 @@ struct ArchReader { continue; try { - temp = new t_model; - temp->index = model_index++; - - temp->never_prune = true; - temp->name = vtr::strdup(prim_name.c_str()); - - ret_map_name = model_name_map.insert(std::pair(temp->name, 0)); + ret_map_name = model_name_map.insert(std::pair(prim_name, 0)); if (!ret_map_name.second) { archfpga_throw(arch_file_, __LINE__, - "Duplicate model name: '%s'.\n", temp->name); + "Duplicate model name: '%s'.\n", prim_name.c_str()); } - if (!process_model_ports(temp, primitive)) { - free_arch_model(temp); + LogicalModelId new_model_id = arch_->models.create_logical_model(prim_name); + t_model& new_model = arch_->models.get_model(new_model_id); + new_model.never_prune = true; + + if (!process_model_ports(new_model, primitive)) { continue; } - check_model_clocks(temp, arch_file_, __LINE__); - check_model_combinational_sinks(temp, arch_file_, __LINE__); - warn_model_missing_timing(temp, arch_file_, __LINE__); - + check_model_clocks(new_model, arch_file_, __LINE__); + check_model_combinational_sinks(new_model, arch_file_, __LINE__); + warn_model_missing_timing(new_model, arch_file_, __LINE__); } catch (ArchFpgaError& e) { - free_arch_model(temp); throw; } - temp->next = arch_->models; - arch_->models = temp; } } } - bool process_model_ports(t_model* model, Netlist::CellDeclaration::Reader primitive) { + bool process_model_ports(t_model& model, Netlist::CellDeclaration::Reader primitive) { auto primLib = ar_.getPrimLibs(); auto portList = primLib.getPortList(); @@ -1040,12 +1020,12 @@ struct ArchReader { port_names.insert(std::pair(model_port->name, dir)); //Add the port if (dir == IN_PORT) { - model_port->next = model->inputs; - model->inputs = model_port; + model_port->next = model.inputs; + model.inputs = model_port; } else if (dir == OUT_PORT) { - model_port->next = model->outputs; - model->outputs = model_port; + model_port->next = model.outputs; + model.outputs = model_port; } } @@ -1309,13 +1289,13 @@ struct ArchReader { lut->num_pb = 1; lut->parent_mode = mode; - lut->blif_model = vtr::strdup(MODEL_NAMES); - lut->model = get_model(arch_, std::string(MODEL_NAMES)); + lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES); + lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES); lut->num_ports = 2; lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port)); - lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", MODEL_NAMES, width); - lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", MODEL_NAMES); + lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", LogicalModels::MODEL_NAMES, width); + lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", LogicalModels::MODEL_NAMES); lut->ports[0].equivalent = PortEquivalence::FULL; @@ -1416,10 +1396,10 @@ struct ArchReader { num_ports = 1; opad->num_ports = num_ports; opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); - opad->blif_model = vtr::strdup(MODEL_OUTPUT); - opad->model = get_model(arch_, std::string(MODEL_OUTPUT)); + opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT); + opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT); - opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", MODEL_OUTPUT); + opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", LogicalModels::MODEL_OUTPUT); omode->pb_type_children[0] = *opad; // IPAD mode @@ -1438,10 +1418,10 @@ struct ArchReader { num_ports = 1; ipad->num_ports = num_ports; ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); - ipad->blif_model = vtr::strdup(MODEL_INPUT); - ipad->model = get_model(arch_, std::string(MODEL_INPUT)); + ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT); + ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT); - ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", MODEL_INPUT); + ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", LogicalModels::MODEL_INPUT); imode->pb_type_children[0] = *ipad; // Handle interconnects @@ -1566,7 +1546,7 @@ struct ArchReader { leaf->num_ports = num_ports; leaf->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); leaf->blif_model = vtr::strdup((std::string(".subckt ") + name).c_str()); - leaf->model = get_model(arch_, name); + leaf->model_id = get_model(arch_, name); mode->num_interconnect = num_ports; mode->interconnect = new t_interconnect[num_ports]; @@ -2140,7 +2120,7 @@ struct ArchReader { leaf_pb_type->num_ports = num_ports; leaf_pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); leaf_pb_type->blif_model = vtr::strdup(const_cell.first.c_str()); - leaf_pb_type->model = get_model(arch_, const_cell.first); + leaf_pb_type->model_id = get_model(arch_, const_cell.first); leaf_pb_type->ports[0] = get_generic_port(arch_, leaf_pb_type, OUT_PORT, const_cell.second, const_cell.first); pb_type->ports[count] = get_generic_port(arch_, leaf_pb_type, OUT_PORT, const_cell.first + "_" + const_cell.second); @@ -2170,11 +2150,10 @@ struct ArchReader { // Create constant models for (auto const_cell : const_cells) { - t_model* model = new t_model; - model->index = arch_->models->index + 1; + LogicalModelId new_model_id = arch_->models.create_logical_model(const_cell.first); + t_model& new_model = arch_->models.get_model(new_model_id); - model->never_prune = true; - model->name = vtr::strdup(const_cell.first.c_str()); + new_model.never_prune = true; t_model_ports* model_port = new t_model_ports; model_port->dir = OUT_PORT; @@ -2182,11 +2161,8 @@ struct ArchReader { model_port->min_size = 1; model_port->size = 1; - model_port->next = model->outputs; - model->outputs = model_port; - - model->next = arch_->models; - arch_->models = model; + model_port->next = new_model.outputs; + new_model.outputs = model_port; } } diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 5e6c96fbfa0..a4c0200d053 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -43,6 +43,7 @@ #include #include +#include "logic_types.h" #include "pugixml.hpp" #include "pugixml_util.hpp" @@ -300,7 +301,7 @@ static void ProcessChanWidthDistr(pugi::xml_node Node, const pugiutil::loc_data& loc_data); static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pugiutil::loc_data& loc_data); static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data); -static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::set& port_names, const pugiutil::loc_data& loc_data); +static void ProcessModelPorts(pugi::xml_node port_group, t_model& model, std::set& port_names, const pugiutil::loc_data& loc_data); static void ProcessLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data, int& num_of_avail_layer); /* Added for vib_layout*/ @@ -471,7 +472,6 @@ void XmlReadArch(const char* ArchFile, /* Process models */ Next = get_single_child(architecture, "models", loc_data); ProcessModels(Next, arch, loc_data); - CreateModelLibrary(arch); /* Process layout */ int num_of_avail_layers = 0; @@ -1576,7 +1576,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, pb_type->pb_type_power->leakage_default_mode = 0; int mode_idx = 0; - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* The pb_type operates in an implied one mode */ pb_type->num_modes = 1; pb_type->modes = new t_mode[pb_type->num_modes]; @@ -2406,15 +2406,9 @@ static void ProcessSwitchblockLocations(pugi::xml_node switchblock_locations, * child type objects. */ static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data) { pugi::xml_node p; - t_model* temp = nullptr; - int L_index; /* std::maps for checking duplicates */ std::map model_name_map; - std::pair::iterator, bool> ret_map_name; - L_index = NUM_MODELS_IN_LIBRARY; - - arch->models = nullptr; for (pugi::xml_node model : Node.children()) { //Process each model if (model.name() != std::string("model")) { @@ -2422,27 +2416,25 @@ static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc } try { - temp = new t_model; - temp->index = L_index; - L_index++; - //Process the tag attributes + bool new_model_never_prune = false; + std::string new_model_name; for (pugi::xml_attribute attr : model.attributes()) { if (attr.name() == std::string("never_prune")) { auto model_type_str = vtr::strdup(attr.value()); if (std::strcmp(model_type_str, "true") == 0) { - temp->never_prune = true; + new_model_never_prune = true; } else if (std::strcmp(model_type_str, "false") == 0) { - temp->never_prune = false; + new_model_never_prune = false; } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(model), "Unsupported never prune attribute value."); } } else if (attr.name() == std::string("name")) { - if (!temp->name) { + if (new_model_name.empty()) { //First name attr. seen - temp->name = vtr::strdup(attr.value()); + new_model_name = attr.value(); } else { //Duplicate name archfpga_throw(loc_data.filename_c_str(), loc_data.line(model), @@ -2454,41 +2446,41 @@ static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc } /* Try insert new model, check if already exist at the same time */ - ret_map_name = model_name_map.insert(std::pair(temp->name, 0)); + auto ret_map_name = model_name_map.insert(std::pair(new_model_name, 0)); if (!ret_map_name.second) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(model), - "Duplicate model name: '%s'.\n", temp->name); + "Duplicate model name: '%s'.\n", new_model_name.c_str()); } + // Create the model in the model storage class + LogicalModelId new_model_id = arch->models.create_logical_model(new_model_name); + t_model& new_model = arch->models.get_model(new_model_id); + new_model.never_prune = new_model_never_prune; + //Process the ports std::set port_names; for (pugi::xml_node port_group : model.children()) { if (port_group.name() == std::string("input_ports")) { - ProcessModelPorts(port_group, temp, port_names, loc_data); + ProcessModelPorts(port_group, new_model, port_names, loc_data); } else if (port_group.name() == std::string("output_ports")) { - ProcessModelPorts(port_group, temp, port_names, loc_data); + ProcessModelPorts(port_group, new_model, port_names, loc_data); } else { bad_tag(port_group, loc_data, model, {"input_ports", "output_ports"}); } } //Sanity check the model - check_model_clocks(temp, loc_data.filename_c_str(), loc_data.line(model)); - check_model_combinational_sinks(temp, loc_data.filename_c_str(), loc_data.line(model)); - warn_model_missing_timing(temp, loc_data.filename_c_str(), loc_data.line(model)); + check_model_clocks(new_model, loc_data.filename_c_str(), loc_data.line(model)); + check_model_combinational_sinks(new_model, loc_data.filename_c_str(), loc_data.line(model)); + warn_model_missing_timing(new_model, loc_data.filename_c_str(), loc_data.line(model)); } catch (ArchFpgaError& e) { - free_arch_model(temp); throw; } - - //Add the model - temp->next = arch->models; - arch->models = temp; } return; } -static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::set& port_names, const pugiutil::loc_data& loc_data) { +static void ProcessModelPorts(pugi::xml_node port_group, t_model& model, std::set& port_names, const pugiutil::loc_data& loc_data) { for (pugi::xml_attribute attr : port_group.attributes()) { bad_attribute(attr, port_group, loc_data); } @@ -2562,14 +2554,14 @@ static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::se //Add the port if (dir == IN_PORT) { - model_port->next = model->inputs; - model->inputs = model_port; + model_port->next = model.inputs; + model.inputs = model_port; } else { VTR_ASSERT(dir == OUT_PORT); - model_port->next = model->outputs; - model->outputs = model_port; + model_port->next = model.outputs; + model.outputs = model_port; } } } @@ -3087,7 +3079,7 @@ static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pu "Unknown property %s for chan_width_distr x\n", Prop); } - chan->peak = get_attribute(Node, "peak", loc_data).as_float(UNDEFINED); + chan->peak = get_attribute(Node, "peak", loc_data).as_float(ARCH_FPGA_UNDEFINED_VAL); chan->width = get_attribute(Node, "width", loc_data, hasWidth).as_float(0); chan->xpeak = get_attribute(Node, "xpeak", loc_data, hasXpeak).as_float(0); chan->dc = get_attribute(Node, "dc", loc_data, hasDc).as_float(0); @@ -3167,14 +3159,14 @@ static void MarkIoTypes(std::vector& PhysicalTileTypes) { auto equivalent_sites = get_equivalent_sites_set(&type); for (const auto& equivalent_site : equivalent_sites) { - if (block_type_contains_blif_model(equivalent_site, MODEL_INPUT)) { + if (block_type_contains_blif_model(equivalent_site, LogicalModels::MODEL_INPUT)) { type.is_input_type = true; break; } } for (const auto& equivalent_site : equivalent_sites) { - if (block_type_contains_blif_model(equivalent_site, MODEL_OUTPUT)) { + if (block_type_contains_blif_model(equivalent_site, LogicalModels::MODEL_OUTPUT)) { type.is_output_type = true; break; } @@ -3194,7 +3186,7 @@ static void ProcessTileProps(pugi::xml_node Node, /* Load properties */ PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1); PhysicalTileType->height = get_attribute(Node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1); - PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED); + PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); if (atof(Prop) < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), @@ -4564,8 +4556,8 @@ static std::vector ProcessSwitches(pugi::xml_node Parent, static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data) { /* check if switch node has the Tdel property */ bool has_Tdel_prop = false; - float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED); - if (Tdel_prop_value != UNDEFINED) { + float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL); + if (Tdel_prop_value != ARCH_FPGA_UNDEFINED_VAL) { has_Tdel_prop = true; } diff --git a/libs/libarchfpga/src/write_models_bb.cpp b/libs/libarchfpga/src/write_models_bb.cpp index a48c0b1ab9f..0ea43f3ebc5 100644 --- a/libs/libarchfpga/src/write_models_bb.cpp +++ b/libs/libarchfpga/src/write_models_bb.cpp @@ -1,12 +1,12 @@ -#include // std::all_of +#include +#include +#include "logic_types.h" #include "vtr_util.h" // vtr::fopen #include "vtr_assert.h" // VTR ASSERT #include "write_models_bb.h" -using vtr::t_linked_vptr; - /* the output file description */ #define OUTPUT_HEADER_COMMENT(Echo, ArchFile) \ { \ @@ -26,20 +26,9 @@ using vtr::t_linked_vptr; /* a comment for the body of black box modules */ const char* HARD_BLOCK_COMMENT = "/* the body of the complex block module is empty since it should be seen as a black box */"; -/* list of vtr primitives blocks */ -static constexpr short num_vtr_primitives = 8; -static constexpr const char* vtr_primitives[num_vtr_primitives] = { - "LUT_K", - "DFF", - "fpga_interconnect", - "mux", - "adder", - "multiply", - "single_port_ram", - "dual_port_ram"}; /* declarations */ -void DeclareModel_bb(FILE* Echo, const t_model* model); +void DeclareModel_bb(FILE* Echo, const t_model& model); /** * (function: WriteModels_bb) @@ -58,21 +47,35 @@ void WriteModels_bb(const char* ArchFile, VTR_ASSERT(arch); FILE* Echo = vtr::fopen(VEchoFile, "w"); - t_model* cur_model = arch->models; /* the output file description */ OUTPUT_HEADER_COMMENT(Echo, ArchFile) + // Collect the model IDs of all the vtr primitives. + std::set vtr_primitives; + std::vector vtr_primitive_names = { + "LUT_K", + "DFF", + "fpga_interconnect", + "mux", + "adder", + "multiply", + "single_port_ram", + "dual_port_ram"}; + for (const std::string& primitive_name : vtr_primitive_names) { + LogicalModelId primitive_model_id = arch->models.get_model_by_name(primitive_name); + if (!primitive_model_id.is_valid()) + continue; + vtr_primitives.insert(primitive_model_id); + } + // iterate over models - while (cur_model) { + for (LogicalModelId model_id : arch->models.all_models()) { // avoid printing vtr primitives - if (std::all_of(vtr_primitives, - vtr_primitives + num_vtr_primitives, - [&](const auto& e) { return strcmp(e, cur_model->name); })) - DeclareModel_bb(Echo, cur_model); + if (vtr_primitives.count(model_id) != 0) + continue; - // moving forward with the next complex block - cur_model = cur_model->next; + DeclareModel_bb(Echo, arch->models.get_model(model_id)); } // CLEAN UP @@ -88,22 +91,19 @@ void WriteModels_bb(const char* ArchFile, * @param Echo pointer output file * @param model pointer to the complex block t_model */ -void DeclareModel_bb(FILE* Echo, const t_model* model) { - // validate the blackbox name - VTR_ASSERT(model); - +void DeclareModel_bb(FILE* Echo, const t_model& model) { // module - fprintf(Echo, "module %s(\n", model->name); + fprintf(Echo, "module %s(\n", model.name); // input/output ports - t_model_ports* input_port = model->inputs; + t_model_ports* input_port = model.inputs; while (input_port) { fprintf(Echo, "\tinput\t[%d:0]\t%s,\n", input_port->size - 1, input_port->name); // move forward until the end of input ports' list input_port = input_port->next; } - t_model_ports* output_port = model->outputs; + t_model_ports* output_port = model.outputs; while (output_port) { fprintf(Echo, "\toutput\t[%d:0]\t%s,\n", output_port->size - 1, output_port->name); // move forward until the end of output ports' list diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 6bea36e299c..06bb22e3566 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -81,7 +81,7 @@ void check_rr_graph(const RRGraphView& rr_graph, continue; } - t_rr_type rr_type = rr_graph.node_type(rr_node); + e_rr_type rr_type = rr_graph.node_type(rr_node); int num_edges = rr_graph.num_edges(RRNodeId(inode)); check_rr_node(rr_graph, rr_indexed_data, grid, vib_grid, chan_width, route_type, inode, is_flat); @@ -138,7 +138,7 @@ void check_rr_graph(const RRGraphView& rr_graph, VTR_ASSERT_MSG(num_edges_to_node > 1, "Expect multiple edges"); - t_rr_type to_rr_type = rr_graph.node_type(RRNodeId(to_node)); + e_rr_type to_rr_type = rr_graph.node_type(RRNodeId(to_node)); /* It is unusual to have more than one programmable switch (in the same direction) between a from_node and a to_node, * as the duplicate switch doesn't add more routing flexibility. @@ -155,12 +155,12 @@ void check_rr_graph(const RRGraphView& rr_graph, * - CHAN -> IPIN connections (unique rr_node for IPIN nodes on multiple sides) * - OPIN -> CHAN connections (unique rr_node for OPIN nodes on multiple sides) */ - bool is_chan_to_chan = (rr_type == CHANX || rr_type == CHANY) && (to_rr_type == CHANY || to_rr_type == CHANX); - bool is_chan_to_ipin = (rr_type == CHANX || rr_type == CHANY) && to_rr_type == IPIN; - bool is_opin_to_chan = rr_type == OPIN && (to_rr_type == CHANX || to_rr_type == CHANY); + bool is_chan_to_chan = (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) && (to_rr_type == e_rr_type::CHANY || to_rr_type == e_rr_type::CHANX); + bool is_chan_to_ipin = (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) && to_rr_type == e_rr_type::IPIN; + bool is_opin_to_chan = rr_type == e_rr_type::OPIN && (to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY); bool is_internal_edge = false; if (is_flat) { - is_internal_edge = (rr_type == IPIN && to_rr_type == IPIN) || (rr_type == OPIN && to_rr_type == OPIN); + is_internal_edge = (rr_type == e_rr_type::IPIN && to_rr_type == e_rr_type::IPIN) || (rr_type == e_rr_type::OPIN && to_rr_type == e_rr_type::OPIN); } if (!(is_chan_to_chan || is_chan_to_ipin || is_opin_to_chan || is_internal_edge)) { VPR_ERROR(VPR_ERROR_ROUTE, @@ -169,8 +169,8 @@ void check_rr_graph(const RRGraphView& rr_graph, } //Between two wire segments - VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY || to_rr_type == IPIN, "Expect channel type or input pin type"); - VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY || rr_type == OPIN, "Expect channel type or output pin type"); + VTR_ASSERT_MSG(to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY || to_rr_type == e_rr_type::IPIN, "Expect channel type or input pin type"); + VTR_ASSERT_MSG(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY || rr_type == e_rr_type::OPIN, "Expect channel type or output pin type"); //While multiple connections between the same wires can be electrically legal, //they are redundant if they are of the same switch type. @@ -191,8 +191,8 @@ void check_rr_graph(const RRGraphView& rr_graph, /* Redundant edges are not allowed for chan <-> chan connections * but allowed for input pin <-> chan or output pin <-> chan connections */ - if ((to_rr_type == CHANX || to_rr_type == CHANY) - && (rr_type == CHANX || rr_type == CHANY)) { + if ((to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY) + && (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY)) { auto switch_type = rr_graph.rr_switch_inf(RRSwitchId(kv.first)).type(); VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)", @@ -231,9 +231,9 @@ void check_rr_graph(const RRGraphView& rr_graph, * now I check that everything is reachable. */ bool is_fringe_warning_sent = false; - for (const RRNodeId& rr_node : rr_graph.nodes()) { + for (const RRNodeId rr_node : rr_graph.nodes()) { size_t inode = (size_t)rr_node; - t_rr_type rr_type = rr_graph.node_type(rr_node); + e_rr_type rr_type = rr_graph.node_type(rr_node); int ptc_num = rr_graph.node_ptc_num(rr_node); int layer_num = rr_graph.node_layer(rr_node); int xlow = rr_graph.node_xlow(rr_node); @@ -241,7 +241,7 @@ void check_rr_graph(const RRGraphView& rr_graph, t_physical_tile_type_ptr type = grid.get_physical_type({xlow, ylow, layer_num}); - if (rr_type == IPIN || rr_type == OPIN) { + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { // #TODO: No edges are added for internal pins. However, they need to be checked somehow! if (ptc_num >= type->num_pins) { VTR_LOG_ERROR("in check_rr_graph: node %d (%s) type: %s is internal node.\n", @@ -249,14 +249,14 @@ void check_rr_graph(const RRGraphView& rr_graph, } } - if (rr_type != SOURCE) { + if (rr_type != e_rr_type::SOURCE) { if (total_edges_to_node[inode] < 1 && !rr_node_is_global_clb_ipin(rr_graph, grid, rr_node)) { /* A global CLB input pin will not have any edges, and neither will * * a SOURCE or the start of a carry-chain. Anything else is an error. * For simplicity, carry-chain input pin are entirely ignored in this test */ bool is_chain = false; - if (rr_type == IPIN) { + if (rr_type == e_rr_type::IPIN) { for (const t_fc_specification& fc_spec : types[type->index].fc_specs) { if (fc_spec.fc_value == 0 && fc_spec.seg_index == 0) { is_chain = true; @@ -264,18 +264,18 @@ void check_rr_graph(const RRGraphView& rr_graph, } } - const auto& node = rr_graph.rr_nodes()[inode]; + const t_rr_node& node = rr_graph.rr_nodes()[inode]; bool is_fringe = ((rr_graph.node_xlow(rr_node) == 1) || (rr_graph.node_ylow(rr_node) == 1) || (rr_graph.node_xhigh(rr_node) == int(grid.width()) - 2) || (rr_graph.node_yhigh(rr_node) == int(grid.height()) - 2)); - bool is_wire = (rr_graph.node_type(rr_node) == CHANX - || rr_graph.node_type(rr_node) == CHANY - || rr_graph.node_type(rr_node) == MEDIUM); + bool is_wire = (rr_graph.node_type(rr_node) == e_rr_type::CHANX + || rr_graph.node_type(rr_node) == e_rr_type::CHANY + || rr_graph.node_type(rr_node) == e_rr_type::MEDIUM); if (!is_chain && !is_fringe && !is_wire) { - if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) { + if (rr_graph.node_type(rr_node) == e_rr_type::IPIN || rr_graph.node_type(rr_node) == e_rr_type::OPIN) { if (has_adjacent_channel(rr_graph, grid, node)) { auto block_type = grid.get_physical_type({rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), @@ -314,18 +314,14 @@ void check_rr_graph(const RRGraphView& rr_graph, static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const DeviceGrid& grid, RRNodeId inode) { /* Returns true if inode refers to a global CLB input pin node. */ + t_physical_tile_type_ptr type = grid.get_physical_type({rr_graph.node_xlow(inode), + rr_graph.node_ylow(inode), + rr_graph.node_layer(inode)}); - int ipin; - t_physical_tile_type_ptr type; - - type = grid.get_physical_type({rr_graph.node_xlow(inode), - rr_graph.node_ylow(inode), - rr_graph.node_layer(inode)}); - - if (rr_graph.node_type(inode) != IPIN) + if (rr_graph.node_type(inode) != e_rr_type::IPIN) return (false); - ipin = rr_graph.node_pin_num(inode); + int ipin = rr_graph.node_pin_num(inode); return type->is_ignored_pin[ipin]; } @@ -344,24 +340,20 @@ void check_rr_node(const RRGraphView& rr_graph, //Make sure over-flow doesn't happen VTR_ASSERT(inode >= 0); - int xlow, ylow, xhigh, yhigh, layer_num, ptc_num, capacity; - t_rr_type rr_type; - t_physical_tile_type_ptr type; int nodes_per_chan, tracks_per_node; - RRIndexedDataId cost_index; float C, R; RRNodeId rr_node = RRNodeId(inode); - rr_type = rr_graph.node_type(rr_node); - xlow = rr_graph.node_xlow(rr_node); - xhigh = rr_graph.node_xhigh(rr_node); - ylow = rr_graph.node_ylow(rr_node); - yhigh = rr_graph.node_yhigh(rr_node); - layer_num = rr_graph.node_layer(rr_node); - ptc_num = rr_graph.node_ptc_num(rr_node); - capacity = rr_graph.node_capacity(rr_node); - cost_index = rr_graph.node_cost_index(rr_node); - type = nullptr; + e_rr_type rr_type = rr_graph.node_type(rr_node); + int xlow = rr_graph.node_xlow(rr_node); + int xhigh = rr_graph.node_xhigh(rr_node); + int ylow = rr_graph.node_ylow(rr_node); + int yhigh = rr_graph.node_yhigh(rr_node); + int layer_num = rr_graph.node_layer(rr_node); + int ptc_num = rr_graph.node_ptc_num(rr_node); + int capacity = rr_graph.node_capacity(rr_node); + RRIndexedDataId cost_index = rr_graph.node_cost_index(rr_node); + t_physical_tile_type_ptr type = nullptr; if (xlow > xhigh || ylow > yhigh) { VPR_ERROR(VPR_ERROR_ROUTE, @@ -399,7 +391,7 @@ void check_rr_node(const RRGraphView& rr_graph, } switch (rr_type) { - case SOURCE: + case e_rr_type::SOURCE: if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -410,8 +402,7 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", inode, rr_type, xlow, ylow, xhigh, yhigh); } break; - - case SINK: { + case e_rr_type::SINK: { if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -424,9 +415,9 @@ void check_rr_node(const RRGraphView& rr_graph, } break; } - case MEDIUM: - case IPIN: - case OPIN: + case e_rr_type::MEDIUM: + case e_rr_type::IPIN: + case e_rr_type::OPIN: if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow); @@ -437,7 +428,7 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case CHANX: + case e_rr_type::CHANX: if (xhigh > int(grid.width()) - 1 || yhigh > int(grid.height()) - 2 || yhigh != ylow) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); @@ -448,7 +439,7 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case CHANY: + case e_rr_type::CHANY: if (xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 1 || xlow != xhigh) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Error in check_rr_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); @@ -475,12 +466,12 @@ void check_rr_node(const RRGraphView& rr_graph, e_pin_type class_type = OPEN; int class_num_pins = -1; switch (rr_type) { - case SOURCE: - case SINK: + case e_rr_type::SOURCE: + case e_rr_type::SINK: class_type = get_class_type_from_class_physical_num(type, ptc_num); class_num_pins = get_class_num_pins_from_class_physical_num(type, ptc_num); if (ptc_num >= class_max_ptc - || class_type != ((rr_type == SOURCE) ? DRIVER : RECEIVER)) { + || class_type != ((rr_type == e_rr_type::SOURCE) ? DRIVER : RECEIVER)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); } @@ -489,7 +480,7 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: inode %d (type %d) had a capacity of %d.\n", inode, rr_type, capacity); } break; - case MEDIUM: + case e_rr_type::MEDIUM: VTR_ASSERT(medium_max_ptc >= 0); if (ptc_num >= medium_max_ptc) { VPR_ERROR(VPR_ERROR_ROUTE, @@ -500,11 +491,11 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: inode %d (type %d) has a capacity of %d.\n", inode, rr_type, capacity); } break; - case OPIN: - case IPIN: + case e_rr_type::OPIN: + case e_rr_type::IPIN: class_type = get_pin_type_from_pin_physical_num(type, ptc_num); if (ptc_num >= pin_max_ptc - || class_type != ((rr_type == OPIN) ? DRIVER : RECEIVER)) { + || class_type != ((rr_type == e_rr_type::OPIN) ? DRIVER : RECEIVER)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); } @@ -514,14 +505,14 @@ void check_rr_node(const RRGraphView& rr_graph, } break; - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: if (route_type == DETAILED) { nodes_per_chan = chan_width.max; tracks_per_node = 1; } else { nodes_per_chan = 1; - tracks_per_node = ((rr_type == CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]); + tracks_per_node = ((rr_type == e_rr_type::CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]); } //if a chanx/chany has length 0, it means it is used to connect different dice together @@ -548,7 +539,7 @@ void check_rr_node(const RRGraphView& rr_graph, C = rr_graph.node_C(rr_node); R = rr_graph.node_R(rr_node); - if (rr_type == CHANX || rr_type == CHANY) { + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { if (C < 0. || R < 0.) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d of type %d has R = %g and C = %g.\n", inode, rr_type, R, C); @@ -566,12 +557,12 @@ static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) { * bidirectional. It may be a slow check, so don't use it all the time. */ int from_edge, to_node, to_edge, from_num_edges, to_num_edges; - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; short from_switch_type; bool trans_matched; from_rr_type = rr_graph.node_type(RRNodeId(from_node)); - if (from_rr_type != CHANX && from_rr_type != CHANY) + if (from_rr_type != e_rr_type::CHANX && from_rr_type != e_rr_type::CHANY) return; from_num_edges = rr_graph.num_edges(RRNodeId(from_node)); @@ -580,7 +571,7 @@ static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) { to_node = size_t(rr_graph.edge_sink_node(RRNodeId(from_node), from_edge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type != CHANX && to_rr_type != CHANY) + if (to_rr_type != e_rr_type::CHANX && to_rr_type != e_rr_type::CHANY) continue; from_switch_type = rr_graph.edge_switch(RRNodeId(from_node), from_edge); @@ -618,7 +609,7 @@ static bool has_adjacent_channel(const RRGraphView& rr_graph, const DeviceGrid& /* TODO: this function should be reworked later to adapt RRGraphView interface * once xlow(), ylow(), side() APIs are implemented */ - VTR_ASSERT(rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN); + VTR_ASSERT(rr_graph.node_type(node.id()) == e_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN); if ((rr_graph.node_xlow(node.id()) == 0 && !rr_graph.is_node_on_specific_side(node.id(), RIGHT)) //left device edge connects only along block's right side || (rr_graph.node_ylow(node.id()) == int(grid.height() - 1) && !rr_graph.is_node_on_specific_side(node.id(), BOTTOM)) //top device edge connects only along block's bottom side diff --git a/libs/librrgraph/src/base/check_rr_graph_obj.cpp b/libs/librrgraph/src/base/check_rr_graph_obj.cpp index d78a6ea266e..9ab1d7f2a3d 100644 --- a/libs/librrgraph/src/base/check_rr_graph_obj.cpp +++ b/libs/librrgraph/src/base/check_rr_graph_obj.cpp @@ -94,7 +94,7 @@ static bool check_rr_graph_source_nodes(const RRGraph& rr_graph) { */ for (auto node : rr_graph.nodes()) { /* Pass nodes whose types are not SOURCE */ - if (SOURCE != rr_graph.node_type(node)) { + if (e_rr_type::SOURCE != rr_graph.node_type(node)) { continue; } if ((0 != rr_graph.node_fan_in(node)) @@ -123,7 +123,7 @@ static bool check_rr_graph_sink_nodes(const RRGraph& rr_graph) { */ for (auto node : rr_graph.nodes()) { /* Pass nodes whose types are not SINK */ - if (SINK != rr_graph.node_type(node)) { + if (e_rr_type::SINK != rr_graph.node_type(node)) { continue; } if ((0 == rr_graph.node_fan_in(node)) diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index fbf442e1972..33ea035f0fe 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -39,36 +39,34 @@ vtr::vector>& RRGraphBuilder::node_ptc_storage() { } void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { - t_rr_type node_type = node_storage_.node_type(node); + e_rr_type node_type = node_storage_.node_type(node); short node_ptc_num = node_storage_.node_ptc_num(node); short node_layer = node_storage_.node_layer(node); short node_twist = node_storage_.node_ptc_twist(node); int node_offset = 0; + for (int ix = node_storage_.node_xlow(node); ix <= node_storage_.node_xhigh(node); ix++) { for (int iy = node_storage_.node_ylow(node); iy <= node_storage_.node_yhigh(node); iy++) { node_ptc_num += node_twist * node_offset; node_offset++; + switch (node_type) { - case SOURCE: - case SINK: - case CHANY: + case e_rr_type::SOURCE: + case e_rr_type::SINK: + case e_rr_type::CHANY: + case e_rr_type::CHANX: node_lookup_.add_node(node, node_layer, ix, iy, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); break; - case CHANX: - /* Currently need to swap x and y for CHANX because of chan, seg convention - * TODO: Once the builders is reworked for use consistent (x, y) convention, - * the following swapping can be removed - */ - node_lookup_.add_node(node, node_layer, iy, ix, node_type, node_ptc_num, TOTAL_2D_SIDES[0]); - break; - case OPIN: - case IPIN: - for (const e_side& side : TOTAL_2D_SIDES) { + + case e_rr_type::OPIN: + case e_rr_type::IPIN: + for (const e_side side : TOTAL_2D_SIDES) { if (node_storage_.is_node_on_specific_side(node, side)) { node_lookup_.add_node(node,node_layer, ix, iy, node_type, node_ptc_num, side); } } break; + default: VTR_LOG_ERROR("Invalid node type for node '%lu' in the routing resource graph file", size_t(node)); break; @@ -77,10 +75,10 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { } } -RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side) { +RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, e_rr_type type, int ptc, e_side side) { e_side node_side = TOTAL_2D_SIDES[0]; /* Only OPIN and IPIN nodes have sides, otherwise force to use a default side */ - if (OPIN == type || IPIN == type) { + if (e_rr_type::OPIN == type || e_rr_type::IPIN == type) { node_side = side; } node_storage_.emplace_back(); @@ -90,15 +88,11 @@ RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, t_rr_type type, in node_storage_.set_node_type(new_node, type); node_storage_.set_node_coordinates(new_node, x, y, x, y); node_storage_.set_node_ptc_num(new_node, ptc); - if (OPIN == type || IPIN == type) { + if (e_rr_type::OPIN == type || e_rr_type::IPIN == type) { node_storage_.add_node_side(new_node, node_side); } /* Special for CHANX, being consistent with the rule in find_node() */ - if (CHANX == type) { - node_lookup_.add_node(new_node, layer, y, x, type, ptc, node_side); - } else { - node_lookup_.add_node(new_node, layer, x, y, type, ptc, node_side); - } + node_lookup_.add_node(new_node, layer, x, y, type, ptc, node_side); return new_node; } @@ -280,7 +274,7 @@ bool RRGraphBuilder::node_contain_multiple_ptc(RRNodeId node) const { void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id) { VTR_ASSERT(size_t(node) < node_storage_.size()); VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); - VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes"); + VTR_ASSERT_MSG(node_storage_.node_type(node) == e_rr_type::CHANX || node_storage_.node_type(node) == e_rr_type::CHANY, "Track number valid only for CHANX/CHANY RR nodes"); size_t node_length = std::abs(node_storage_.node_xhigh(node) - node_storage_.node_xlow(node)) + std::abs(node_storage_.node_yhigh(node) - node_storage_.node_ylow(node)); @@ -295,7 +289,7 @@ void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_o } void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { - VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Update track node look-up is only valid to CHANX/CHANY nodes"); + VTR_ASSERT_MSG(node_storage_.node_type(node) == e_rr_type::CHANX || node_storage_.node_type(node) == e_rr_type::CHANY, "Update track node look-up is only valid to CHANX/CHANY nodes"); /* Compute the track id based on the (x, y) coordinate */ size_t x_start = std::min(node_storage_.node_xlow(node), node_storage_.node_xhigh(node)); @@ -312,16 +306,14 @@ void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { for (const size_t& x : node_x) { for (const size_t& y : node_y) { size_t ptc = node_storage_.node_ptc_num(node); + e_rr_type node_type = node_storage_.node_type(node); /* Routing channel nodes may have different ptc num * Find the track ids using the x/y offset * FIXME: Special case on assigning CHANX (x,y) should be changed to a natural way! */ - if (CHANX == node_storage_.node_type(node)) { - ptc = node_ptc_nums_[node][x - node_storage_.node_xlow(node)]; - node_lookup_.add_node(node, node_storage_.node_layer(node), y, x, CHANX, ptc); - } else if (CHANY == node_storage_.node_type(node)) { - ptc = node_ptc_nums_[node][y - node_storage_.node_ylow(node)]; - node_lookup_.add_node(node, node_storage_.node_layer(node), x, y, CHANY, ptc); + if (e_rr_type::CHANX == node_type || e_rr_type::CHANY == node_type) { + ptc = node_type == e_rr_type::CHANX ? node_ptc_nums_[node][x - node_storage_.node_xlow(node)] : node_ptc_nums_[node][y - node_storage_.node_ylow(node)]; + node_lookup_.add_node(node, node_storage_.node_layer(node), x, y, node_type, ptc); } } } diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 07e23cfb449..576d28c2101 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -124,14 +124,14 @@ class RRGraphBuilder { } /** @brief Set the type of a node with a given valid id */ - inline void set_node_type(RRNodeId id, t_rr_type type) { + inline void set_node_type(RRNodeId id, e_rr_type type) { node_storage_.set_node_type(id, type); } /** @brief Create a new rr_node in the node storage and register it to the node look-up. * Return a valid node id if succeed. Otherwise, return an invalid id. */ - RRNodeId create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side = NUM_2D_SIDES); + RRNodeId create_node(int layer, int x, int y, e_rr_type type, int ptc, e_side side = NUM_2D_SIDES); /** @brief Set the node name with a given valid id */ inline void set_node_name(RRNodeId id, std::string name) { diff --git a/libs/librrgraph/src/base/rr_graph_obj.cpp b/libs/librrgraph/src/base/rr_graph_obj.cpp index fae02caf26e..211c49990bf 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.cpp +++ b/libs/librrgraph/src/base/rr_graph_obj.cpp @@ -32,7 +32,7 @@ RRGraph::segment_range RRGraph::segments() const { } //Node attributes -t_rr_type RRGraph::node_type(const RRNodeId& node) const { +e_rr_type RRGraph::node_type(const RRNodeId& node) const { VTR_ASSERT_SAFE(valid_node_id(node)); return node_types_[node]; } @@ -81,7 +81,7 @@ vtr::Rect RRGraph::node_bounding_box(const RRNodeId& node) const { ***********************************************************************/ vtr::Point RRGraph::node_start_coordinate(const RRNodeId& node) const { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == node_type(node)) || (CHANY == node_type(node))); + VTR_ASSERT((e_rr_type::CHANX == node_type(node)) || (e_rr_type::CHANY == node_type(node))); vtr::Point start_coordinate(node_xlow(node), node_ylow(node)); @@ -105,7 +105,7 @@ vtr::Point RRGraph::node_start_coordinate(const RRNodeId& node) const { ***********************************************************************/ vtr::Point RRGraph::node_end_coordinate(const RRNodeId& node) const { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == node_type(node)) || (CHANY == node_type(node))); + VTR_ASSERT((e_rr_type::CHANX == node_type(node)) || (e_rr_type::CHANY == node_type(node))); vtr::Point end_coordinate(node_xhigh(node), node_yhigh(node)); @@ -135,19 +135,19 @@ short RRGraph::node_ptc_num(const RRNodeId& node) const { } short RRGraph::node_pin_num(const RRNodeId& node) const { - VTR_ASSERT_MSG(node_type(node) == IPIN || node_type(node) == OPIN, + VTR_ASSERT_MSG(node_type(node) == e_rr_type::IPIN || node_type(node) == e_rr_type::OPIN, "Pin number valid only for IPIN/OPIN RR nodes"); return node_ptc_num(node); } short RRGraph::node_track_num(const RRNodeId& node) const { - VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, + VTR_ASSERT_MSG(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY, "Track number valid only for CHANX/CHANY RR nodes"); return node_ptc_num(node); } short RRGraph::node_class_num(const RRNodeId& node) const { - VTR_ASSERT_MSG(node_type(node) == SOURCE || node_type(node) == SINK, "Class number valid only for SOURCE/SINK RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::SOURCE || node_type(node) == e_rr_type::SINK, "Class number valid only for SOURCE/SINK RR nodes"); return node_ptc_num(node); } @@ -158,13 +158,13 @@ RRIndexedDataId RRGraph::node_cost_index(const RRNodeId& node) const { Direction RRGraph::node_direction(const RRNodeId& node) const { VTR_ASSERT_SAFE(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, "Direction valid only for CHANX/CHANY RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY, "Direction valid only for CHANX/CHANY RR nodes"); return node_directions_[node]; } e_side RRGraph::node_side(const RRNodeId& node) const { VTR_ASSERT_SAFE(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == IPIN || node_type(node) == OPIN, "Side valid only for IPIN/OPIN RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::IPIN || node_type(node) == e_rr_type::OPIN, "Side valid only for IPIN/OPIN RR nodes"); return node_sides_[node]; } @@ -372,11 +372,11 @@ std::vector RRGraph::find_edges(const RRNodeId& src_node, const RRNode return matching_edges; } -RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& type, const int& ptc, const e_side& side) const { +RRNodeId RRGraph::find_node(const short& x, const short& y, const e_rr_type type, const int& ptc, const e_side& side) const { initialize_fast_node_lookup(); - size_t itype = type; - size_t iside = side; + const size_t itype = (size_t)type; + const size_t iside = side; /* Check if x, y, type and ptc, side is valid */ if ((x < 0) /* See if x is smaller than the index of first element */ @@ -401,14 +401,14 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ /* Check if x, y, type and ptc, side is valid */ if ((ptc < 0) /* See if ptc is smaller than the index of first element */ - || (size_t(ptc) > node_lookup_[x][y][type].size() - 1)) { /* See if ptc is large than the index of last element */ + || (size_t(ptc) > node_lookup_[x][y][itype].size() - 1)) { /* See if ptc is large than the index of last element */ /* Return a zero range! */ return RRNodeId::INVALID(); } /* Check if x, y, type and ptc, side is valid */ /* iside is always larger than -1, we can skip checking */ - if (iside > node_lookup_[x][y][type][ptc].size() - 1) { /* See if side is large than the index of last element */ + if (iside > node_lookup_[x][y][itype][ptc].size() - 1) { /* See if side is large than the index of last element */ /* Return a zero range! */ return RRNodeId::INVALID(); } @@ -417,9 +417,9 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ } /* Find the channel width (number of tracks) of a channel [x][y] */ -short RRGraph::chan_num_tracks(const short& x, const short& y, const t_rr_type& type) const { +short RRGraph::chan_num_tracks(const short& x, const short& y, const e_rr_type& type) const { /* Must be CHANX or CHANY */ - VTR_ASSERT_MSG(CHANX == type || CHANY == type, + VTR_ASSERT_MSG(e_rr_type::CHANX == type || e_rr_type::CHANY == type, "Required node_type to be CHANX or CHANY!"); initialize_fast_node_lookup(); @@ -432,18 +432,18 @@ short RRGraph::chan_num_tracks(const short& x, const short& y, const t_rr_type& /* Check if x, y, type and ptc is valid */ if ((y < 0) /* See if y is smaller than the index of first element */ - || (size_t(y) > node_lookup_[x].size() - 1)) { /* See if y is large than the index of last element */ + || (size_t(y) > node_lookup_[x].size() - 1)) { /* See if y is larger than the index of last element */ /* Return a zero range! */ return 0; } /* Check if x, y, type and ptc is valid */ - if ((size_t(type) > node_lookup_[x][y].size() - 1)) { /* See if type is large than the index of last element */ + if ((size_t(type) > node_lookup_[x][y].size() - 1)) { /* See if type is larger than the index of last element */ /* Return a zero range! */ return 0; } - const auto& matching_nodes = node_lookup_[x][y][type]; + const auto& matching_nodes = node_lookup_[x][y][(size_t)type]; return vtr::make_range(matching_nodes.begin(), matching_nodes.end()).size(); } @@ -465,8 +465,8 @@ void RRGraph::print_node(const RRNodeId& node) const { bool RRGraph::validate_node_segment(const RRNodeId& node) const { VTR_ASSERT_SAFE(valid_node_id(node)); /* Only CHANX and CHANY requires a valid segment id */ - if ((CHANX == node_type(node)) - || (CHANY == node_type(node))) { + if ((e_rr_type::CHANX == node_type(node)) + || (e_rr_type::CHANY == node_type(node))) { return valid_segment_id(node_segments_[node]); } else { return true; @@ -477,7 +477,7 @@ bool RRGraph::validate_node_segment(const RRNodeId& node) const { bool RRGraph::validate_node_segments() const { bool all_valid = true; for (auto node : nodes()) { - if (true == validate_node_segment(node)) { + if (validate_node_segment(node)) { continue; } /* Reach here it means we find an invalid segment id */ @@ -499,7 +499,7 @@ bool RRGraph::validate_edge_switch(const RREdgeId& edge) const { bool RRGraph::validate_edge_switches() const { bool all_valid = true; for (auto edge : edges()) { - if (true == validate_edge_switch(edge)) { + if (validate_edge_switch(edge)) { continue; } /* Reach here it means we find an invalid segment id */ @@ -798,7 +798,7 @@ void RRGraph::reserve_segments(const int& num_segments) { } /* Mutators */ -RRNodeId RRGraph::create_node(const t_rr_type& type) { +RRNodeId RRGraph::create_node(const e_rr_type& type) { //Allocate an ID RRNodeId node_id = RRNodeId(node_ids_.size()); @@ -971,21 +971,24 @@ void RRGraph::set_node_ptc_num(const RRNodeId& node, const short& ptc) { void RRGraph::set_node_pin_num(const RRNodeId& node, const short& pin_id) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == IPIN || node_type(node) == OPIN, "Pin number valid only for IPIN/OPIN RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::IPIN || node_type(node) == e_rr_type::OPIN, + "Pin number valid only for IPIN/OPIN RR nodes"); set_node_ptc_num(node, pin_id); } void RRGraph::set_node_track_num(const RRNodeId& node, const short& track_id) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY, + "Track number valid only for CHANX/CHANY RR nodes"); set_node_ptc_num(node, track_id); } void RRGraph::set_node_class_num(const RRNodeId& node, const short& class_id) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == SOURCE || node_type(node) == SINK, "Class number valid only for SOURCE/SINK RR nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::SOURCE || node_type(node) == e_rr_type::SINK, + "Class number valid only for SOURCE/SINK RR nodes"); set_node_ptc_num(node, class_id); } @@ -997,14 +1000,14 @@ void RRGraph::set_node_cost_index(const RRNodeId& node, const RRIndexedDataId& c void RRGraph::set_node_direction(const RRNodeId& node, const Direction& direction) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, "Direct can only be specified on CHANX/CNAY rr nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY, "Direct can only be specified on CHANX/CNAY rr nodes"); node_directions_[node] = direction; } void RRGraph::set_node_side(const RRNodeId& node, const e_side& side) { VTR_ASSERT(valid_node_id(node)); - VTR_ASSERT_MSG(node_type(node) == IPIN || node_type(node) == OPIN, "Side can only be specified on IPIN/OPIN rr nodes"); + VTR_ASSERT_MSG(node_type(node) == e_rr_type::IPIN || node_type(node) == e_rr_type::OPIN, "Side can only be specified on IPIN/OPIN rr nodes"); node_sides_[node] = side; } @@ -1028,8 +1031,8 @@ void RRGraph::set_node_segment(const RRNodeId& node, const RRSegmentId& segment_ VTR_ASSERT(valid_node_id(node)); /* Only CHANX and CHANY requires a valid segment id */ - if ((CHANX == node_type(node)) - || (CHANY == node_type(node))) { + if ((e_rr_type::CHANX == node_type(node)) + || (e_rr_type::CHANY == node_type(node))) { VTR_ASSERT(valid_segment_id(segment_id)); } @@ -1119,7 +1122,7 @@ void RRGraph::build_fast_node_lookup() const { node_lookup_[x].resize(y + 1); } - size_t itype = node_type(node); + size_t itype = (size_t)node_type(node); if (itype >= node_lookup_[x][y].size()) { node_lookup_[x][y].resize(itype + 1); } @@ -1130,7 +1133,7 @@ void RRGraph::build_fast_node_lookup() const { } size_t iside = -1; - if (node_type(node) == OPIN || node_type(node) == IPIN) { + if (node_type(node) == e_rr_type::OPIN || node_type(node) == e_rr_type::IPIN) { iside = node_side(node); } else { iside = NUM_2D_SIDES; diff --git a/libs/librrgraph/src/base/rr_graph_obj.h b/libs/librrgraph/src/base/rr_graph_obj.h index 5ad31ba7f01..f3a3f8c8477 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.h +++ b/libs/librrgraph/src/base/rr_graph_obj.h @@ -60,7 +60,7 @@ * // Get the unique node id that you may get * // from other data structures or functions * RRNodeId node_id; - * t_rr_type node_type = rr_graph.node_type(node_id); + * e_rr_type node_type = rr_graph.node_type(node_id); * * // Access all the fan-out edges from a given node * for (const RREdgeId& out_edge_id : rr_graph.node_out_edges(node_id)) { @@ -257,9 +257,9 @@ class RRGraph { /* get the type of a RRGraph node : types of each node, can be channel wires (CHANX or CHANY) or * logic block pins(OPIN or IPIN) or virtual nodes (SOURCE or SINK) - * see t_rr_type definition for more details + * see e_rr_type definition for more details */ - t_rr_type node_type(const RRNodeId& node) const; + e_rr_type node_type(const RRNodeId& node) const; /* Get coordinate of a node. (xlow, xhigh, ylow, yhigh): * For OPIN/IPIN/SOURCE/SINK, xlow = xhigh and ylow = yhigh @@ -510,9 +510,9 @@ class RRGraph { /* Find the edges connecting two nodes */ std::vector find_edges(const RRNodeId& src_node, const RRNodeId& sink_node) const; /* Find a node with given features from internal fast look-up */ - RRNodeId find_node(const short& x, const short& y, const t_rr_type& type, const int& ptc, const e_side& side = NUM_2D_SIDES) const; + RRNodeId find_node(const short& x, const short& y, const e_rr_type type, const int& ptc, const e_side& side = NUM_2D_SIDES) const; /* Find the number of routing tracks in a routing channel with a given coordinate */ - short chan_num_tracks(const short& x, const short& y, const t_rr_type& type) const; + short chan_num_tracks(const short& x, const short& y, const e_rr_type& type) const; /* This flag is raised when the RRgraph contains invalid nodes/edges etc. * Invalid nodes/edges exist when users remove nodes/edges from RRGraph @@ -589,7 +589,7 @@ class RRGraph { * RRNodeId node = create_node(); * set_node_xlow(node, 0); */ - RRNodeId create_node(const t_rr_type& type); + RRNodeId create_node(const e_rr_type& type); /* Add a edge to the RRGraph, by providing the source and sink node * This function will automatically create a node and * configure the nodes and edges in connection @@ -782,7 +782,7 @@ class RRGraph { private: /* Internal Data */ /* Node related data */ vtr::vector node_ids_; /* Unique identifiers for the nodes */ - vtr::vector node_types_; + vtr::vector node_types_; vtr::vector> node_bounding_boxes_; diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 124fd81036b..8ff99e1513a 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -467,7 +467,7 @@ size_t t_rr_graph_storage::count_rr_switches( if (arch_switch_inf[iswitch].fixed_Tdel()) { //If delay is independent of fanin drop the unique fanin info - fanin = UNDEFINED; + fanin = ARCH_FPGA_UNDEFINED_VAL; } if (arch_switch_fanins[iswitch].count(fanin) == 0) { //New fanin for this switch @@ -485,7 +485,7 @@ size_t t_rr_graph_storage::count_rr_switches( for(size_t iswitch = 0; iswitch < arch_switch_counts.size(); ++iswitch) { if(arch_switch_fanins[iswitch].empty()){ if(arch_switch_inf[iswitch].fixed_Tdel()){ - arch_switch_fanins[iswitch][UNDEFINED] = num_rr_switches++; + arch_switch_fanins[iswitch][ARCH_FPGA_UNDEFINED_VAL] = num_rr_switches++; } } } @@ -507,8 +507,8 @@ void t_rr_graph_storage::remap_rr_node_switch_indices(const t_arch_switch_fanin& int switch_index = edge_switch_[edge]; int fanin = node_fan_in_[to_node]; - if (switch_fanin[switch_index].count(UNDEFINED) == 1) { - fanin = UNDEFINED; + if (switch_fanin[switch_index].count(ARCH_FPGA_UNDEFINED_VAL) == 1) { + fanin = ARCH_FPGA_UNDEFINED_VAL; } auto itr = switch_fanin[switch_index].find(fanin); @@ -653,28 +653,28 @@ void t_rr_graph_storage::set_node_ptc_num(RRNodeId id, int new_ptc_num) { node_ptc_[id].ptc_.pin_num = new_ptc_num; //TODO: eventually remove } void t_rr_graph_storage::set_node_pin_num(RRNodeId id, int new_pin_num) { - if (node_type(id) != IPIN && node_type(id) != OPIN) { - VTR_LOG_ERROR("Attempted to set RR node 'pin_num' for non-IPIN/OPIN type '%s'\n", node_type_string(id)); + if (node_type(id) != e_rr_type::IPIN && node_type(id) != e_rr_type::OPIN) { + VTR_LOG_ERROR("Attempted to set RR node 'pin_num' for non-IPIN/OPIN type '%s'", node_type_string(id)); } node_ptc_[id].ptc_.pin_num = new_pin_num; } void t_rr_graph_storage::set_node_track_num(RRNodeId id, int new_track_num) { - if (node_type(id) != CHANX && node_type(id) != CHANY) { - VTR_LOG_ERROR("Attempted to set RR node 'track_num' for non-CHANX/CHANY type '%s'\n", node_type_string(id)); + if (node_type(id) != e_rr_type::CHANX && node_type(id) != e_rr_type::CHANY) { + VTR_LOG_ERROR("Attempted to set RR node 'track_num' for non-CHANX/CHANY type '%s'", node_type_string(id)); } node_ptc_[id].ptc_.track_num = new_track_num; } void t_rr_graph_storage::set_node_class_num(RRNodeId id, int new_class_num) { - if (node_type(id) != SOURCE && node_type(id) != SINK) { - VTR_LOG_ERROR("Attempted to set RR node 'class_num' for non-SOURCE/SINK type '%s'\n", node_type_string(id)); + if (node_type(id) != e_rr_type::SOURCE && node_type(id) != e_rr_type::SINK) { + VTR_LOG_ERROR("Attempted to set RR node 'class_num' for non-SOURCE/SINK type '%s'", node_type_string(id)); } node_ptc_[id].ptc_.class_num = new_class_num; } void t_rr_graph_storage::set_node_medium_num(RRNodeId id, int new_medium_num) { - if (node_type(id) != MEDIUM) { + if (node_type(id) != e_rr_type::MEDIUM) { VTR_LOG_ERROR("Attempted to set RR node 'medium_num' for non-MEDIUM type '%s'\n", node_type_string(id)); } node_ptc_[id].ptc_.medium_num = new_medium_num; @@ -688,9 +688,9 @@ static int get_node_pin_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - auto node_type = node_storage[id].type_; - if (node_type != IPIN && node_type != OPIN) { - VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'\n", rr_node_typename[node_type]); + e_rr_type node_type = node_storage[id].type_; + if (node_type != e_rr_type::IPIN && node_type != e_rr_type::OPIN) { + VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'", rr_node_typename[node_type]); } return node_ptc[id].ptc_.pin_num; } @@ -699,9 +699,9 @@ static int get_node_track_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - auto node_type = node_storage[id].type_; - if (node_type != CHANX && node_type != CHANY) { - VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'\n", rr_node_typename[node_type]); + e_rr_type node_type = node_storage[id].type_; + if (node_type != e_rr_type::CHANX && node_type != e_rr_type::CHANY) { + VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'", rr_node_typename[node_type]); } return node_ptc[id].ptc_.track_num; } @@ -710,9 +710,9 @@ static int get_node_class_num( vtr::array_view_id node_storage, vtr::array_view_id node_ptc, RRNodeId id) { - auto node_type = node_storage[id].type_; - if (node_type != SOURCE && node_type != SINK) { - VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'\n", rr_node_typename[node_type]); + e_rr_type node_type = node_storage[id].type_; + if (node_type != e_rr_type::SOURCE && node_type != e_rr_type::SINK) { + VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'", rr_node_typename[node_type]); } return node_ptc[id].ptc_.class_num; } @@ -722,7 +722,7 @@ static int get_node_medium_num( vtr::array_view_id node_ptc, RRNodeId id) { auto node_type = node_storage[id].type_; - if (node_type != MEDIUM) { + if (node_type != e_rr_type::MEDIUM) { VTR_LOG_ERROR("Attempted to access RR node 'medium_num' for non-MEDIUM type '%s'\n", rr_node_typename[node_type]); } return node_ptc[id].ptc_.medium_num; @@ -753,11 +753,11 @@ int t_rr_graph_storage::node_medium_num(RRNodeId id) const { id); } -void t_rr_graph_storage::set_node_type(RRNodeId id, t_rr_type new_type) { +void t_rr_graph_storage::set_node_type(RRNodeId id, e_rr_type new_type) { node_storage_[id].type_ = new_type; } -void t_rr_graph_storage::set_node_name(RRNodeId id, std::string new_name) { +void t_rr_graph_storage::set_node_name(RRNodeId id, const std::string& new_name) { node_name_.insert(std::make_pair(id, new_name)); } void t_rr_graph_storage::set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2) { @@ -808,15 +808,15 @@ void t_rr_graph_storage::set_node_capacity(RRNodeId id, short new_capacity) { } void t_rr_graph_storage::set_node_direction(RRNodeId id, Direction new_direction) { - if (node_type(id) != CHANX && node_type(id) != CHANY) { - VTR_LOG_ERROR("Attempted to set RR node 'direction' for non-channel type '%s'\n", node_type_string(id)); + if (node_type(id) != e_rr_type::CHANX && node_type(id) != e_rr_type::CHANY) { + VTR_LOG_ERROR("Attempted to set RR node 'direction' for non-channel type '%s'", node_type_string(id)); } node_storage_[id].dir_side_.direction = new_direction; } void t_rr_graph_storage::add_node_side(RRNodeId id, e_side new_side) { - if (node_type(id) != IPIN && node_type(id) != OPIN) { - VTR_LOG_ERROR("Attempted to set RR node 'side' for non-channel type '%s'\n", node_type_string(id)); + if (node_type(id) != e_rr_type::IPIN && node_type(id) != e_rr_type::OPIN) { + VTR_LOG_ERROR("Attempted to set RR node 'side' for non-channel type '%s'", node_type_string(id)); } std::bitset side_bits = node_storage_[id].dir_side_.sides; side_bits[size_t(new_side)] = true; diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 39134554718..255b9535e35 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -25,10 +25,10 @@ * parallel rr_node_* structures. * * * * This structure should **only** contain data used in the inner loop of the * - * router. This data is consider "hot" and the router performance is * + * router. This data is considered "hot" and the router performance is * * sensitive to layout and size of this "hot" data. * - * Cold data should be stored seperately in t_rr_graph_storage. * + * Cold data should be stored separately in t_rr_graph_storage. * * * * xlow, xhigh, ylow, yhigh: Integer coordinates (see route.c for * * coordinate system) of the ends of this routing resource. * @@ -66,7 +66,7 @@ struct alignas(32) t_rr_node_data { int16_t node_bend_start_ = 0; int16_t node_bend_end_ = 0; - t_rr_type type_ = NUM_RR_TYPES; + e_rr_type type_ = e_rr_type::NUM_RR_TYPES; /* The character is a hex number which is a 4-bit truth table for node sides * The 4-bits in serial represent 4 sides on which a node could appear @@ -168,7 +168,7 @@ class t_rr_graph_storage { * Node methods * ****************/ - t_rr_type node_type(RRNodeId id) const { + e_rr_type node_type(RRNodeId id) const { return node_storage_[id].type_; } const char* node_type_string(RRNodeId id) const; @@ -644,8 +644,8 @@ class t_rr_graph_storage { void set_node_class_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_medium_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent - void set_node_type(RRNodeId id, t_rr_type new_type); - void set_node_name(RRNodeId id, std::string new_name); + void set_node_type(RRNodeId id, e_rr_type new_type); + void set_node_name(RRNodeId id, const std::string& new_name); void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2); void set_node_layer(RRNodeId id, short layer); void set_node_ptc_twist_incr(RRNodeId id, short twist); @@ -808,7 +808,7 @@ class t_rr_graph_storage { const RRNodeId& id, const e_side& side) { auto& node_data = node_storage[id]; - if (node_data.type_ != IPIN && node_data.type_ != OPIN) { + if (node_data.type_ != e_rr_type::IPIN && node_data.type_ != e_rr_type::OPIN) { VTR_LOG_ERROR("Attempted to access RR node 'side' for non-IPIN/OPIN type '%s'", rr_node_typename[node_data.type_]); } @@ -1010,7 +1010,7 @@ class t_rr_graph_view { return node_storage_.size(); } - t_rr_type node_type(RRNodeId id) const { + e_rr_type node_type(RRNodeId id) const { return node_storage_[id].type_; } const char* node_type_string(RRNodeId id) const; diff --git a/libs/librrgraph/src/base/rr_graph_utils.cpp b/libs/librrgraph/src/base/rr_graph_utils.cpp index 1769d1cae5f..6a76ac6bac2 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.cpp +++ b/libs/librrgraph/src/base/rr_graph_utils.cpp @@ -75,8 +75,8 @@ std::vector find_rr_graph_switches(const RRGraph& rr_graph, return switches; } -int seg_index_of_cblock(const RRGraphView& rr_graph, t_rr_type from_rr_type, int to_node) { - if (from_rr_type == CHANX) +int seg_index_of_cblock(const RRGraphView& rr_graph, e_rr_type from_rr_type, int to_node) { + if (from_rr_type == e_rr_type::CHANX) return (rr_graph.node_xlow(RRNodeId(to_node))); else /* CHANY */ @@ -84,15 +84,15 @@ int seg_index_of_cblock(const RRGraphView& rr_graph, t_rr_type from_rr_type, int } int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) { - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; from_rr_type = rr_graph.node_type(RRNodeId(from_node)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (from_rr_type == CHANX) { - if (to_rr_type == CHANY) { + if (from_rr_type == e_rr_type::CHANX) { + if (to_rr_type == e_rr_type::CHANY) { return (rr_graph.node_xlow(RRNodeId(to_node))); - } else if (to_rr_type == CHANX) { + } else if (to_rr_type == e_rr_type::CHANX) { if (rr_graph.node_xlow(RRNodeId(to_node)) > rr_graph.node_xlow(RRNodeId(from_node))) { /* Going right */ return (rr_graph.node_xhigh(RRNodeId(from_node))); } else { /* Going left */ @@ -106,10 +106,10 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) } } /* End from_rr_type is CHANX */ - else if (from_rr_type == CHANY) { - if (to_rr_type == CHANX) { + else if (from_rr_type == e_rr_type::CHANY) { + if (to_rr_type == e_rr_type::CHANX) { return (rr_graph.node_ylow(RRNodeId(to_node))); - } else if (to_rr_type == CHANY) { + } else if (to_rr_type == e_rr_type::CHANY) { if (rr_graph.node_ylow(RRNodeId(to_node)) > rr_graph.node_ylow(RRNodeId(from_node))) { /* Going up */ return (rr_graph.node_yhigh(RRNodeId(from_node))); } else { /* Going down */ @@ -218,17 +218,17 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil } // Remove old locations from lookup - VTR_ASSERT(rr_graph_builder.node_lookup().find_node(node_layer, new_loc.x(), new_loc.y(), SINK, node_ptc) != RRNodeId::INVALID()); + VTR_ASSERT(rr_graph_builder.node_lookup().find_node(node_layer, new_loc.x(), new_loc.y(), e_rr_type::SINK, node_ptc) != RRNodeId::INVALID()); for (int x = tile_bb.xmin(); x <= tile_bb.xmax(); ++x) { for (int y = tile_bb.ymin(); y <= tile_bb.ymax(); ++y) { if (x == new_loc.x() && y == new_loc.y()) /* The new sink location */ continue; - if (rr_graph_builder.node_lookup().find_node(node_layer, x, y, SINK, node_ptc) == RRNodeId::INVALID()) /* Already removed */ + if (rr_graph_builder.node_lookup().find_node(node_layer, x, y, e_rr_type::SINK, node_ptc) == RRNodeId::INVALID()) /* Already removed */ continue; - bool removed_successfully = rr_graph_builder.node_lookup().remove_node(node_id, node_layer, x, y, SINK, node_ptc); + bool removed_successfully = rr_graph_builder.node_lookup().remove_node(node_id, node_layer, x, y, e_rr_type::SINK, node_ptc); VTR_ASSERT(removed_successfully); } } diff --git a/libs/librrgraph/src/base/rr_graph_utils.h b/libs/librrgraph/src/base/rr_graph_utils.h index e3f2d3cdfb9..63288b09f3b 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.h +++ b/libs/librrgraph/src/base/rr_graph_utils.h @@ -76,7 +76,7 @@ void rr_set_sink_locs(const RRGraphView& rr_graph, RRGraphBuilder& rr_graph_buil * @brief Returns the segment number (distance along the channel) of the connection box from from_rr_type (CHANX or * CHANY) to to_node (IPIN). */ -int seg_index_of_cblock(const RRGraphView& rr_graph, t_rr_type from_rr_type, int to_node); +int seg_index_of_cblock(const RRGraphView& rr_graph, e_rr_type from_rr_type, int to_node); /** * @brief Returns the segment number (distance along the channel) of the switch box from from_node (CHANX or CHANY) to diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index f7e6803c98c..2e18db1ce06 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -130,7 +130,7 @@ class RRGraphView { /** @brief Return the type of a specified node. */ - inline t_rr_type node_type(RRNodeId node) const { + inline e_rr_type node_type(RRNodeId node) const { return node_storage_.node_type(node); } @@ -257,7 +257,7 @@ class RRGraphView { * @note node_length() only applies to CHANX or CHANY and is always a positive number */ inline int node_length(RRNodeId node) const { - VTR_ASSERT(node_type(node) == CHANX || node_type(node) == CHANY); + VTR_ASSERT(node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY); if (node_direction(node) == Direction::NONE) { return 0; //length zero wire } @@ -269,7 +269,7 @@ class RRGraphView { /** @brief Check if a routing resource node is initialized. */ inline bool node_is_initialized(RRNodeId node) const { - return !((node_type(node) == NUM_RR_TYPES) + return !((node_type(node) == e_rr_type::NUM_RR_TYPES) && (node_xlow(node) == -1) && (node_ylow(node) == -1) && (node_xhigh(node) == -1) && (node_yhigh(node) == -1)); } @@ -278,7 +278,7 @@ class RRGraphView { * @note This function performs error checking by determining whether two nodes are physically adjacent based on their geometry. It does not verify the routing edges to confirm if a connection is feasible within the current routing graph. */ inline bool nodes_are_adjacent(RRNodeId chanx_node, RRNodeId chany_node) const { - VTR_ASSERT(node_type(chanx_node) == CHANX && node_type(chany_node) == CHANY); + VTR_ASSERT(node_type(chanx_node) == e_rr_type::CHANX && node_type(chany_node) == e_rr_type::CHANY); if (node_ylow(chany_node) > node_ylow(chanx_node) + 1 || // verifies that chany_node is not more than one unit above chanx_node node_yhigh(chany_node) < node_ylow(chanx_node)) // verifies that chany_node is not more than one unit beneath chanx_node return false; @@ -331,7 +331,7 @@ class RRGraphView { coordinate_string += ":" + std::to_string(size_t(node)) + " "; //add the index of the routing resource node int node_layer_num = node_layer(node); - if (node_type(node) == OPIN || node_type(node) == IPIN) { + if (node_type(node) == e_rr_type::OPIN || node_type(node) == e_rr_type::IPIN) { coordinate_string += "side: ("; //add the side of the routing resource node for (const e_side& node_side : TOTAL_2D_SIDES) { if (!is_node_on_specific_side(node, node_side)) { @@ -345,12 +345,12 @@ class RRGraphView { start_x = " (" + std::to_string(node_xhigh(node)) + ","; //start and end coordinates are the same for OPINs and IPINs start_y = std::to_string(node_yhigh(node)) + ","; start_layer_str = std::to_string(node_layer_num) + ")"; - } else if (node_type(node) == SOURCE || node_type(node) == SINK) { + } else if (node_type(node) == e_rr_type::SOURCE || node_type(node) == e_rr_type::SINK) { // For SOURCE and SINK the starting and ending coordinate are identical, so just use start start_x = " (" + std::to_string(node_xhigh(node)) + ","; start_y = std::to_string(node_yhigh(node)) + ","; start_layer_str = std::to_string(node_layer_num) + ")"; - } else if (node_type(node) == CHANX || node_type(node) == CHANY) { //for channels, we would like to describe the component with segment specific information + } else if (node_type(node) == e_rr_type::CHANX || node_type(node) == e_rr_type::CHANY) { //for channels, we would like to describe the component with segment specific information RRIndexedDataId cost_index = node_cost_index(node); int seg_index = rr_indexed_data_[cost_index].seg_index; coordinate_string += rr_segments(RRSegmentId(seg_index)).name; //Write the segment name @@ -363,7 +363,7 @@ class RRGraphView { start_x = " (" + std::to_string(node_xhigh(node)) + ","; //start coordinates have large value start_y = std::to_string(node_yhigh(node)) + ","; - start_layer_str = std::to_string(node_layer_num); + start_layer_str = std::to_string(node_layer_num) + ")"; end_x = " (" + std::to_string(node_xlow(node)) + ","; //end coordinates have smaller value end_y = std::to_string(node_ylow(node)) + ","; end_layer_str = std::to_string(node_layer_num) + ")"; @@ -372,7 +372,7 @@ class RRGraphView { else { // signal travels in increasing direction, stays at same point, or can travel both directions start_x = " (" + std::to_string(node_xlow(node)) + ","; //start coordinates have smaller value start_y = std::to_string(node_ylow(node)) + ","; - start_layer_str = std::to_string(node_layer_num); + start_layer_str = std::to_string(node_layer_num) + ")"; end_x = " (" + std::to_string(node_xhigh(node)) + ","; //end coordinates have larger value end_y = std::to_string(node_yhigh(node)) + ","; end_layer_str = std::to_string(node_layer_num) + ")"; //layer number diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index 8d318921593..e38e78686f5 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -1,5 +1,4 @@ -#ifndef RR_NODE_TYPES_H -#define RR_NODE_TYPES_H +#pragma once #include #include @@ -8,7 +7,9 @@ #include #include #include + #include "vtr_range.h" +#include "vtr_array.h" #include "vtr_ndmatrix.h" #include "rr_graph_fwd.h" @@ -21,7 +22,7 @@ * - SOURCE * - SINK */ -typedef enum e_rr_type : unsigned char { +enum class e_rr_type : unsigned char { SOURCE = 0, /// RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY, MEDIUM}}; -constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY", "MEDIUM"}}; +/// Used to iterate for different e_rr_type values in range-based for loops. +constexpr std::array RR_TYPES = {{e_rr_type::SOURCE, e_rr_type::SINK, e_rr_type::IPIN, + e_rr_type::OPIN, e_rr_type::CHANX, e_rr_type::CHANY, e_rr_type::MEDIUM}}; -/* - * Direction::INC: wire driver is positioned at the low-coordinate end of the wire. - * Direction::DEC: wire_driver is positioned at the high-coordinate end of the wire. - * Direction::BIDIR: wire has multiple drivers, so signals can travel either way along the wire - * Direction::NONE: node does not have a direction, such as IPIN/OPIN +constexpr vtr::array rr_node_typename {"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY", "MEDIUM"}; + +/** + * @enum Direction + * @brief Represents the wire direction for a routing resource node. */ enum class Direction : unsigned char { - INC = 0, - DEC = 1, - BIDIR = 2, - NONE = 3, + INC = 0, ///< wire driver is positioned at the low-coordinate end of the wire. + DEC = 1, ///< wire_driver is positioned at the high-coordinate end of the wire. + BIDIR = 2, ///< wire has multiple drivers, so signals can travel either way along the wire + NONE = 3, ///< node does not have a direction, such as IPIN/OPIN NUM_DIRECTIONS }; + constexpr std::array(Direction::NUM_DIRECTIONS)> DIRECTION_STRING = {{"INC_DIRECTION", "DEC_DIRECTION", "BI_DIRECTION", "NONE"}}; //this array is used in rr_graph_storage.cpp so that node_direction_string() can return a const std::string& @@ -125,6 +128,4 @@ struct t_rr_rc_data { // This is the data type of fast lookups of an rr-node given an (rr_type, layer, x, y, and the side) //[0..num_rr_types-1][0..num_layer-1][0..grid_width-1][0..grid_height-1][0..NUM_2D_SIDES-1][0..max_ptc-1] -typedef std::array, 4>, NUM_RR_TYPES> t_rr_node_indices; - -#endif +typedef vtr::array, 4>, (size_t)e_rr_type::NUM_RR_TYPES> t_rr_node_indices; diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index fb1780e72ce..a27f9b6b088 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -2,13 +2,10 @@ #include "vtr_log.h" #include "rr_spatial_lookup.h" -RRSpatialLookup::RRSpatialLookup() { -} - RRNodeId RRSpatialLookup::find_node(int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side) const { /* Find actual side to be used @@ -22,10 +19,10 @@ RRNodeId RRSpatialLookup::find_node(int layer, * Please note that in the add_node function, we should keep the SAME convention! */ e_side node_side = side; - if (type == IPIN || type == OPIN) { + if (type == e_rr_type::IPIN || type == e_rr_type::OPIN) { VTR_ASSERT_MSG(side != NUM_2D_SIDES, "IPIN/OPIN must specify desired side (can not be default NUM_2D_SIDES)"); } else { - VTR_ASSERT_SAFE(type != IPIN && type != OPIN); + VTR_ASSERT_SAFE(type != e_rr_type::IPIN && type != e_rr_type::OPIN); node_side = TOTAL_2D_SIDES[0]; } @@ -34,18 +31,6 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - /* Currently need to swap x and y for CHANX because of chan, seg convention - * This is due to that the fast look-up builders uses (y, x) coordinate when - * registering a CHANX node in the look-up - * TODO: Once the builders is reworked for use consistent (x, y) convention, - * the following swapping can be removed - */ - size_t node_x = x; - size_t node_y = y; - if (type == CHANX) { - std::swap(node_x, node_y); - } - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* Sanity check to ensure the layer, x, y, side and ptc are in range @@ -60,11 +45,11 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - if (node_x >= rr_node_indices_[type].dim_size(1)) { + if (size_t(x) >= rr_node_indices_[type].dim_size(1)) { return RRNodeId::INVALID(); } - if(node_y >= rr_node_indices_[type].dim_size(2)){ + if (size_t(y) >= rr_node_indices_[type].dim_size(2)){ return RRNodeId::INVALID(); } @@ -72,11 +57,11 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - if (size_t(ptc) >= rr_node_indices_[type][layer][node_x][node_y][node_side].size()) { + if (size_t(ptc) >= rr_node_indices_[type][layer][x][y][node_side].size()) { return RRNodeId::INVALID(); } - return rr_node_indices_[type][layer][node_x][node_y][node_side][ptc]; + return rr_node_indices_[type][layer][x][y][node_side][ptc]; } std::vector RRSpatialLookup::find_nodes_in_range(int layer, @@ -84,7 +69,7 @@ std::vector RRSpatialLookup::find_nodes_in_range(int layer, int ylow, int xhigh, int yhigh, - t_rr_type type, + e_rr_type type, int ptc, e_side side) const { std::set nodes; @@ -103,7 +88,7 @@ std::vector RRSpatialLookup::find_nodes_in_range(int layer, std::vector RRSpatialLookup::find_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, e_side side) const { /* TODO: The implementation of this API should be worked * when rr_node_indices adapts RRNodeId natively! @@ -115,18 +100,6 @@ std::vector RRSpatialLookup::find_nodes(int layer, return nodes; } - /* Currently need to swap x and y for CHANX because of chan, seg convention - * This is due to that the fast look-up builders uses (y, x) coordinate when - * registering a CHANX node in the look-up - * TODO: Once the builders is reworked for use consistent (x, y) convention, - * the following swapping can be removed - */ - size_t node_x = x; - size_t node_y = y; - if (type == CHANX) { - std::swap(node_x, node_y); - } - VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* Sanity check to ensure the x, y, side are in range @@ -141,11 +114,11 @@ std::vector RRSpatialLookup::find_nodes(int layer, return nodes; } - if (node_x >= rr_node_indices_[type].dim_size(1)) { + if (size_t(x) >= rr_node_indices_[type].dim_size(1)) { return nodes; } - if(node_y >= rr_node_indices_[type].dim_size(2)){ + if (size_t(y) >= rr_node_indices_[type].dim_size(2)){ return nodes; } @@ -155,14 +128,14 @@ std::vector RRSpatialLookup::find_nodes(int layer, /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; - for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { + for (RRNodeId node : rr_node_indices_[type][layer][x][y][side]) { if (node.is_valid()) { num_nodes++; } } nodes.reserve(num_nodes); - for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { + for (RRNodeId node : rr_node_indices_[type][layer][x][y][side]) { if (node.is_valid()) { nodes.emplace_back(node); } @@ -174,9 +147,9 @@ std::vector RRSpatialLookup::find_nodes(int layer, std::vector RRSpatialLookup::find_channel_nodes(int layer, int x, int y, - t_rr_type type) const { + e_rr_type type) const { /* Pre-check: node type should be routing tracks! */ - if (type != CHANX && type != CHANY) { + if (type != e_rr_type::CHANX && type != e_rr_type::CHANY) { return std::vector(); } @@ -186,12 +159,12 @@ std::vector RRSpatialLookup::find_channel_nodes(int layer, std::vector RRSpatialLookup::find_nodes_at_all_sides(int layer, int x, int y, - t_rr_type rr_type, + e_rr_type rr_type, int ptc) const { std::vector indices; /* TODO: Consider to access the raw data like find_node() rather than calling find_node() many times, which hurts runtime */ - if (rr_type == IPIN || rr_type == OPIN) { + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { indices.reserve(NUM_2D_SIDES); //For pins, we need to look at all the sides of the current grid tile for (e_side side : TOTAL_2D_SIDES) { @@ -215,10 +188,10 @@ std::vector RRSpatialLookup::find_nodes_at_all_sides(int layer, std::vector RRSpatialLookup::find_grid_nodes_at_all_sides(int layer, int x, int y, - t_rr_type rr_type) const { - VTR_ASSERT(rr_type == SOURCE || rr_type == OPIN || rr_type == IPIN || rr_type == SINK || rr_type == MEDIUM); - if (rr_type == SOURCE || rr_type == SINK || rr_type == MEDIUM) { - return find_nodes(layer, x, y, rr_type); + e_rr_type rr_type) const { + VTR_ASSERT(rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::OPIN || rr_type == e_rr_type::IPIN || rr_type == e_rr_type::SINK || rr_type == e_rr_type::MEDIUM); + if (rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::SINK || rr_type == e_rr_type::MEDIUM) { + return find_nodes(layer,x, y, rr_type); } std::vector nodes; @@ -239,13 +212,13 @@ std::vector RRSpatialLookup::find_grid_nodes_at_all_sides(int layer, void RRSpatialLookup::reserve_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, int num_nodes, e_side side) { VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* For non-IPIN/OPIN nodes, the side should always be the TOP side which follows the convention in find_node() API! */ - if (type != IPIN && type != OPIN) { + if (type != e_rr_type::IPIN && type != e_rr_type::OPIN) { VTR_ASSERT(side == TOTAL_2D_SIDES[0]); } @@ -258,14 +231,14 @@ void RRSpatialLookup::add_node(RRNodeId node, int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side) { VTR_ASSERT(node.is_valid()); /* Must have a valid node id to be added */ VTR_ASSERT_SAFE(4 == rr_node_indices_[type].ndims()); /* For non-IPIN/OPIN nodes, the side should always be the TOP side which follows the convention in find_node() API! */ - if (type != IPIN && type != OPIN) { + if (type != e_rr_type::IPIN && type != e_rr_type::OPIN) { VTR_ASSERT(side == TOTAL_2D_SIDES[0]); } @@ -284,7 +257,7 @@ bool RRSpatialLookup::remove_node(RRNodeId node, int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side) { VTR_ASSERT(node.is_valid()); @@ -292,12 +265,12 @@ bool RRSpatialLookup::remove_node(RRNodeId node, VTR_ASSERT_SAFE(layer >= 0); VTR_ASSERT_SAFE(x >= 0); VTR_ASSERT_SAFE(y >= 0); - VTR_ASSERT_SAFE(type != NUM_RR_TYPES); + VTR_ASSERT_SAFE(type != e_rr_type::NUM_RR_TYPES); VTR_ASSERT_SAFE(ptc >= 0); VTR_ASSERT_SAFE(side != NUM_2D_SIDES); // Check if the node given is in the spatial lookup at the given indices - if (type >= rr_node_indices_.size()) return false; + if ((size_t)type >= rr_node_indices_.size()) return false; if ((size_t)layer >= rr_node_indices_[type].dim_size(0)) return false; if ((size_t)x >= rr_node_indices_[type].dim_size(1)) return false; if ((size_t)y >= rr_node_indices_[type].dim_size(2)) return false; @@ -314,9 +287,9 @@ bool RRSpatialLookup::remove_node(RRNodeId node, void RRSpatialLookup::mirror_nodes(const int layer, const vtr::Point& src_coord, const vtr::Point& des_coord, - t_rr_type type, + e_rr_type type, e_side side) { - VTR_ASSERT(SOURCE == type || SINK == type); + VTR_ASSERT(e_rr_type::SOURCE == type || e_rr_type::SINK == type); resize_nodes(layer, des_coord.x(), des_coord.y(), type, side); rr_node_indices_[type][layer][des_coord.x()][des_coord.y()][side] = rr_node_indices_[type][layer][src_coord.x()][src_coord.y()][side]; } @@ -324,13 +297,13 @@ void RRSpatialLookup::mirror_nodes(const int layer, void RRSpatialLookup::resize_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, e_side side) { /* Expand the fast look-up if the new node is out-of-range * This may seldom happen because the rr_graph building function * should ensure the fast look-up well organized */ - VTR_ASSERT(type < rr_node_indices_.size()); + VTR_ASSERT((size_t)type < rr_node_indices_.size()); VTR_ASSERT(x >= 0); VTR_ASSERT(y >= 0); VTR_ASSERT(layer >= 0); @@ -339,21 +312,21 @@ void RRSpatialLookup::resize_nodes(int layer, || (x >= int(rr_node_indices_[type].dim_size(1))) || (y >= int(rr_node_indices_[type].dim_size(2))) || (size_t(side) >= rr_node_indices_[type].dim_size(3))) { - rr_node_indices_[type].resize({std::max(rr_node_indices_[type].dim_size(0),size_t(layer)+1), + rr_node_indices_[type].resize({std::max(rr_node_indices_[type].dim_size(0), size_t(layer)+1), std::max(rr_node_indices_[type].dim_size(1), size_t(x) + 1), std::max(rr_node_indices_[type].dim_size(2), size_t(y) + 1), std::max(rr_node_indices_[type].dim_size(3), size_t(side) + 1)}); } } -void RRSpatialLookup::reorder(const vtr::vector dest_order) { +void RRSpatialLookup::reorder(const vtr::vector& dest_order) { // update rr_node_indices, a map to optimize rr_index lookups for (auto& grid : rr_node_indices_) { for(size_t l = 0; l < grid.dim_size(0); l++) { for (size_t x = 0; x < grid.dim_size(1); x++) { for (size_t y = 0; y < grid.dim_size(2); y++) { for (size_t s = 0; s < grid.dim_size(3); s++) { - for (auto &node: grid[l][x][y][s]) { + for (RRNodeId &node: grid[l][x][y][s]) { if (node.is_valid()) { node = dest_order[node]; } diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.h b/libs/librrgraph/src/base/rr_spatial_lookup.h index 6a4ca5f1b1c..c69f34b791a 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.h +++ b/libs/librrgraph/src/base/rr_spatial_lookup.h @@ -1,5 +1,4 @@ -#ifndef RR_SPATIAL_LOOKUP_H -#define RR_SPATIAL_LOOKUP_H +#pragma once /** * @file @@ -25,7 +24,7 @@ class RRSpatialLookup { /* -- Constructors -- */ public: /* Explicitly define the only way to create an object */ - explicit RRSpatialLookup(); + explicit RRSpatialLookup() = default; /* Disable copy constructors and copy assignment operator * This is to avoid accidental copy because it could be an expensive operation considering that the @@ -71,7 +70,7 @@ class RRSpatialLookup { RRNodeId find_node(int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side = NUM_2D_SIDES) const; @@ -94,7 +93,7 @@ class RRSpatialLookup { int ylow, int xhigh, int yhigh, - t_rr_type type, + e_rr_type type, int ptc, e_side side = e_side::NUM_2D_SIDES) const; @@ -116,7 +115,7 @@ class RRSpatialLookup { std::vector find_channel_nodes(int layer, int x, int y, - t_rr_type type) const; + e_rr_type type) const; /** * @brief Like find_node() but returns all matching nodes on all the sides. @@ -127,7 +126,7 @@ class RRSpatialLookup { std::vector find_nodes_at_all_sides(int layer, int x, int y, - t_rr_type rr_type, + e_rr_type rr_type, int ptc) const; /** @@ -138,7 +137,7 @@ class RRSpatialLookup { std::vector find_grid_nodes_at_all_sides(int layer, int x, int y, - t_rr_type rr_type) const; + e_rr_type rr_type) const; /* -- Mutators -- */ public: @@ -146,7 +145,7 @@ class RRSpatialLookup { void reserve_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, int num_nodes, e_side side = TOTAL_2D_SIDES[0]); @@ -179,7 +178,7 @@ class RRSpatialLookup { int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side = TOTAL_2D_SIDES[0]); @@ -203,7 +202,7 @@ class RRSpatialLookup { int layer, int x, int y, - t_rr_type type, + e_rr_type type, int ptc, e_side side = TOTAL_2D_SIDES[0]); @@ -249,7 +248,7 @@ class RRSpatialLookup { void mirror_nodes(const int layer, const vtr::Point& src_coord, const vtr::Point& des_coord, - t_rr_type type, + e_rr_type type, e_side side); /** @@ -266,11 +265,11 @@ class RRSpatialLookup { void resize_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, e_side side); /** @brief Reorder the internal look up to be more memory efficient */ - void reorder(const vtr::vector dest_order); + void reorder(const vtr::vector& dest_order); /** @brief Clear all the data inside */ void clear(); @@ -285,7 +284,7 @@ class RRSpatialLookup { std::vector find_nodes(int layer, int x, int y, - t_rr_type type, + e_rr_type type, e_side side = TOTAL_2D_SIDES[0]) const; /* -- Internal data storage -- */ @@ -293,5 +292,3 @@ class RRSpatialLookup { /* Fast look-up: TODO: Should rework the data type. Currently it is based on a 3-dimensional array mater where some dimensions must always be accessed with a specific index. Such limitation should be overcome */ t_rr_node_indices rr_node_indices_; }; - -#endif diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index afc5d180c3d..81e2ead5ef7 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -750,7 +750,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { if (uxsd::enum_loc_side::UXSD_INVALID == side) { // node_loc.side is only expected on IPIN/OPIN. - if (rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN) { + if (rr_graph.node_type(node.id()) == e_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN) { report_error( "inode %d is type %d, which requires a side, but no side was supplied.", inode, rr_graph.node_type(node.id())); @@ -773,7 +773,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline uxsd::enum_loc_side get_node_loc_side(const t_rr_node& node) final { const auto& rr_graph = (*rr_graph_); - if (rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN) { + if (rr_graph.node_type(node.id()) == e_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN) { std::bitset sides_bitset; for (const e_side& side : TOTAL_2D_SIDES) { if (rr_graph.is_node_on_specific_side(node.id(), side)) { @@ -831,11 +831,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { if (e_graph_type::GLOBAL == graph_type_) { rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(0)); - } else if (rr_graph.node_type(node.id()) == CHANX) { + } else if (rr_graph.node_type(node.id()) == e_rr_type::CHANX) { int seg_ind_x = find_segment_index_along_axis(segment_id, X_AXIS); rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(CHANX_COST_INDEX_START + seg_ind_x)); seg_index_[rr_graph.node_cost_index(node.id())] = segment_id; - } else if (rr_graph.node_type(node.id()) == CHANY) { + } else if (rr_graph.node_type(node.id()) == e_rr_type::CHANY) { int seg_ind_y = find_segment_index_along_axis(segment_id, Y_AXIS); rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(CHANX_COST_INDEX_START + segment_inf_x_.size() + seg_ind_y)); seg_index_[rr_graph.node_cost_index(node.id())] = segment_id; @@ -896,20 +896,20 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { rr_graph_builder_->set_node_capacity(node_id, capacity); switch (rr_graph.node_type(node.id())) { - case CHANX: + case e_rr_type::CHANX: break; - case CHANY: + case e_rr_type::CHANY: break; - case SOURCE: + case e_rr_type::SOURCE: rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(SOURCE_COST_INDEX)); break; - case SINK: + case e_rr_type::SINK: rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(SINK_COST_INDEX)); break; - case OPIN: + case e_rr_type::OPIN: rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(OPIN_COST_INDEX)); break; - case IPIN: + case e_rr_type::IPIN: rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(IPIN_COST_INDEX)); break; default: @@ -969,7 +969,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { RRNodeId node_id = node.id(); if (direction == uxsd::enum_node_direction::UXSD_INVALID) { - if (rr_graph.node_type(node.id()) == CHANX || rr_graph.node_type(node.id()) == CHANY) { + if (rr_graph.node_type(node.id()) == e_rr_type::CHANX || rr_graph.node_type(node.id()) == e_rr_type::CHANY) { report_error( "inode %d is type %d, which requires a direction, but no direction was supplied.", inode, rr_graph.node_type(node.id())); @@ -980,7 +980,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { } inline uxsd::enum_node_direction get_node_direction(const t_rr_node& node) final { const auto& rr_graph = (*rr_graph_); - if (rr_graph.node_type(node.id()) == CHANX || rr_graph.node_type(node.id()) == CHANY) { + if (rr_graph.node_type(node.id()) == e_rr_type::CHANX || rr_graph.node_type(node.id()) == e_rr_type::CHANY) { return to_uxsd_node_direction(rr_graph.node_direction(node.id())); } else { return uxsd::enum_node_direction::UXSD_INVALID; @@ -1165,8 +1165,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { /*Keeps track of the number of the specific type of switch that connects a wire to an ipin * use the pair data structure to keep the maximum*/ - if (rr_graph.node_type(node.id()) == CHANX || rr_graph.node_type(node.id()) == CHANY) { - if(rr_graph.node_type(RRNodeId(sink_node)) == IPIN){ + if (rr_graph.node_type(node.id()) == e_rr_type::CHANX || rr_graph.node_type(node.id()) == e_rr_type::CHANY) { + if(rr_graph.node_type(RRNodeId(sink_node)) == e_rr_type::IPIN){ if (rr_graph.node_layer(RRNodeId(sink_node)) == rr_graph.node_layer(RRNodeId(source_node))) { count_for_wire_to_ipin_switches[switch_id]++; if (count_for_wire_to_ipin_switches[switch_id] > most_frequent_switch.second) { @@ -1856,20 +1856,15 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { auto& rr_graph_builder = (*rr_graph_builder_); /* Alloc the lookup table */ - for (t_rr_type rr_type : RR_TYPES) { - if (rr_type == CHANX) { - rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.height(), grid_.width(), rr_type, NUM_2D_SIDES); - } else { - rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.width(), grid_.height(), rr_type, NUM_2D_SIDES); - } + for (e_rr_type rr_type : RR_TYPES) { + rr_graph_builder.node_lookup().resize_nodes(grid_.get_num_layers(), grid_.width(), grid_.height(), rr_type, NUM_2D_SIDES); } /* Add the correct node into the vector */ - for (size_t inode = 0; inode < rr_nodes_->size(); inode++) { - auto node = (*rr_nodes_)[inode]; + for (const t_rr_node& node : *rr_nodes_) { /* Set track numbers as a node may have multiple ptc */ if (rr_graph_builder.node_contain_multiple_ptc(node.id())) { - if (CHANX == rr_graph_->node_type(node.id()) || CHANY == rr_graph_->node_type(node.id())) { + if (rr_graph_->node_type(node.id()) == e_rr_type::CHANX || rr_graph_->node_type(node.id()) == e_rr_type::CHANY) { rr_graph_builder.add_track_node_to_lookup(node.id()); } } else { @@ -2020,43 +2015,43 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { } } - t_rr_type from_uxsd_node_type(uxsd::enum_node_type type) { + e_rr_type from_uxsd_node_type(uxsd::enum_node_type type) { switch (type) { case uxsd::enum_node_type::CHANX: - return CHANX; + return e_rr_type::CHANX; case uxsd::enum_node_type::CHANY: - return CHANY; + return e_rr_type::CHANY; case uxsd::enum_node_type::SOURCE: - return SOURCE; + return e_rr_type::SOURCE; case uxsd::enum_node_type::SINK: - return SINK; + return e_rr_type::SINK; case uxsd::enum_node_type::OPIN: - return OPIN; + return e_rr_type::OPIN; case uxsd::enum_node_type::IPIN: - return IPIN; + return e_rr_type::IPIN; case uxsd::enum_node_type::MEDIUM: - return MEDIUM; + return e_rr_type::MEDIUM; default: report_error( "Invalid node type %d", type); } } - uxsd::enum_node_type to_uxsd_node_type(t_rr_type type) { + uxsd::enum_node_type to_uxsd_node_type(e_rr_type type) { switch (type) { - case CHANX: + case e_rr_type::CHANX: return uxsd::enum_node_type::CHANX; - case CHANY: + case e_rr_type::CHANY: return uxsd::enum_node_type::CHANY; - case SOURCE: + case e_rr_type::SOURCE: return uxsd::enum_node_type::SOURCE; - case SINK: + case e_rr_type::SINK: return uxsd::enum_node_type::SINK; - case OPIN: + case e_rr_type::OPIN: return uxsd::enum_node_type::OPIN; - case IPIN: + case e_rr_type::IPIN: return uxsd::enum_node_type::IPIN; - case MEDIUM: + case e_rr_type::MEDIUM: return uxsd::enum_node_type::MEDIUM; default: report_error( diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 3fd98a700aa..c7fb3a254b1 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -190,16 +190,16 @@ std::vector find_ortho_cost_index(const RRGraphView& rr_graph, for (const RRNodeId& rr_node : rr_graph.nodes()) { for (size_t iedge = 0; iedge < rr_graph.num_edges(rr_node); ++iedge) { RRNodeId to_node = rr_graph.edge_sink_node(rr_node, iedge); - t_rr_type from_node_type = rr_graph.node_type(rr_node); - t_rr_type to_node_type = rr_graph.node_type(to_node); + e_rr_type from_node_type = rr_graph.node_type(rr_node); + e_rr_type to_node_type = rr_graph.node_type(to_node); size_t from_node_cost_index = (size_t)rr_graph.node_cost_index(rr_node); size_t to_node_cost_index = (size_t)rr_graph.node_cost_index(to_node); //if the type is smaller than start index, means destination is not a CHAN type node. - if ((from_node_type == CHANX && to_node_type == CHANY) || (from_node_type == CHANY && to_node_type == CHANX)) { - if (to_node_type == CHANY) { + if ((from_node_type == e_rr_type::CHANX && to_node_type == e_rr_type::CHANY) || (from_node_type == e_rr_type::CHANY && to_node_type == e_rr_type::CHANX)) { + if (to_node_type == e_rr_type::CHANY) { dest_nodes_count[from_node_cost_index - CHANX_COST_INDEX_START][to_node_cost_index - (CHANX_COST_INDEX_START + segment_inf_x.size())]++; } else { dest_nodes_count[from_node_cost_index - CHANX_COST_INDEX_START][to_node_cost_index - CHANX_COST_INDEX_START]++; @@ -431,7 +431,7 @@ static std::vector count_rr_segment_types(const RRGraphView& rr_graph, c std::vector rr_segment_type_counts; for (const RRNodeId& id : rr_graph.nodes()) { - if (rr_graph.node_type(id) != CHANX && rr_graph.node_type(id) != CHANY) continue; + if (rr_graph.node_type(id) != e_rr_type::CHANX && rr_graph.node_type(id) != e_rr_type::CHANY) continue; auto cost_index = rr_graph.node_cost_index(id); @@ -517,7 +517,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, vtr::vector> switch_R_total(rr_indexed_data.size()); vtr::vector> switch_T_total(rr_indexed_data.size()); vtr::vector> switch_Cinternal_total(rr_indexed_data.size()); - vtr::vector switches_buffered(rr_indexed_data.size(), UNDEFINED); + vtr::vector switches_buffered(rr_indexed_data.size(), ARCH_FPGA_UNDEFINED_VAL); /* * Walk through the RR graph and collect all R and C values of all the nodes, @@ -527,9 +527,9 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, * data. */ for (const RRNodeId& rr_id : rr_graph.nodes()) { - t_rr_type rr_type = rr_graph.node_type(rr_id); + e_rr_type rr_type = rr_graph.node_type(rr_id); - if (rr_type != CHANX && rr_type != CHANY) { + if (rr_type != e_rr_type::CHANX && rr_type != e_rr_type::CHANY) { continue; } @@ -543,7 +543,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, double avg_switch_Cinternal = 0; int num_switches = 0; int num_shorts = 0; - short buffered = UNDEFINED; + short buffered = ARCH_FPGA_UNDEFINED_VAL; calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list); if (num_switches == 0) { @@ -562,13 +562,13 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, switch_R_total[cost_index].push_back(avg_switch_R); switch_T_total[cost_index].push_back(avg_switch_T); switch_Cinternal_total[cost_index].push_back(avg_switch_Cinternal); - if (buffered == UNDEFINED) { + if (buffered == ARCH_FPGA_UNDEFINED_VAL) { /* this segment does not have any outgoing edges to other general routing wires */ continue; } /* need to make sure all wire switches of a given wire segment type have the same 'buffered' value */ - if (switches_buffered[cost_index] == UNDEFINED) { + if (switches_buffered[cost_index] == ARCH_FPGA_UNDEFINED_VAL) { switches_buffered[cost_index] = buffered; } else { if (switches_buffered[cost_index] != buffered) { @@ -645,10 +645,10 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou avg_switch_Cinternal = 0; num_switches = 0; num_shorts = 0; - buffered = UNDEFINED; + buffered = ARCH_FPGA_UNDEFINED_VAL; for (const auto& edge : fan_in_list[node]) { /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */ - if (rr_graph.node_type(node) == CHANX || rr_graph.node_type(node) == CHANY) { + if (rr_graph.node_type(node) == e_rr_type::CHANX || rr_graph.node_type(node) == e_rr_type::CHANY) { int switch_index = rr_graph.rr_nodes().edge_switch(edge); if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type() == SwitchType::SHORT) { @@ -660,7 +660,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou avg_switch_T += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Tdel; avg_switch_Cinternal += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cinternal; - if (buffered == UNDEFINED) { + if (buffered == ARCH_FPGA_UNDEFINED_VAL) { if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).buffered()) { buffered = 1; } else { diff --git a/libs/librrgraph/src/utils/describe_rr_node.cpp b/libs/librrgraph/src/utils/describe_rr_node.cpp index fb1f1a0c172..80ee74027c5 100644 --- a/libs/librrgraph/src/utils/describe_rr_node.cpp +++ b/libs/librrgraph/src/utils/describe_rr_node.cpp @@ -11,7 +11,7 @@ std::string describe_rr_node(const RRGraphView& rr_graph, bool is_flat) { std::string msg = vtr::string_fmt("RR node: %d", inode); - if (rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) { + if (rr_graph.node_type(inode) == e_rr_type::CHANX || rr_graph.node_type(inode) == e_rr_type::CHANY) { auto cost_index = rr_graph.node_cost_index(inode); int seg_index = rr_indexed_data[cost_index].seg_index; @@ -26,7 +26,7 @@ std::string describe_rr_node(const RRGraphView& rr_graph, rr_graph.node_track_num(inode), seg_index); } - } else if (rr_graph.node_type(inode) == IPIN || rr_graph.node_type(inode) == OPIN) { + } else if (rr_graph.node_type(inode) == e_rr_type::IPIN || rr_graph.node_type(inode) == e_rr_type::OPIN) { auto type = grid.get_physical_type({rr_graph.node_xlow(inode), rr_graph.node_ylow(inode), rr_graph.node_layer(inode)}); @@ -36,13 +36,13 @@ std::string describe_rr_node(const RRGraphView& rr_graph, msg += vtr::string_fmt(" pin: %d pin_name: %s", rr_graph.node_pin_num(inode), pin_name.c_str()); - } else if (rr_graph.node_type(inode) == MEDIUM) { + } else if (rr_graph.node_type(inode) == e_rr_type::MEDIUM) { auto index = rr_graph.node_ptc_num(inode); msg += vtr::string_fmt(" medium index: %d", index); } else { - VTR_ASSERT(rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK); msg += vtr::string_fmt(" class: %d", rr_graph.node_class_num(inode)); } diff --git a/libs/libvtrutil/src/vtr_array.h b/libs/libvtrutil/src/vtr_array.h new file mode 100644 index 00000000000..7866bd07c41 --- /dev/null +++ b/libs/libvtrutil/src/vtr_array.h @@ -0,0 +1,105 @@ +#pragma once + +#include +#include +#include + +namespace vtr { + +/** + * @brief A std::array wrapper that can be indexed by a vtr::StrongId. + * + * @tparam K Key type (e.g., vtr::StrongId) + * @tparam V Value type + * @tparam N Number of elements + */ +template +class array { + public: + using key_type = K; + using value_type = V; + using size_type = std::size_t; + using reference = V&; + using const_reference = const V&; + using iterator = typename std::array::iterator; + using const_iterator = typename std::array::const_iterator; + + /** + * @brief Construct a vtr::array from a list of values. + * + * This constructor allows direct brace-initialization of the array: + * @code + * vtr::array arr{1, 2, 3}; + * @endcode + * + * @tparam Args Types of the values being passed. All must be convertible to V. + * @param args The values to initialize the array with. Must match the array size. + */ + template...>>> + constexpr array(Args&&... args) + : data_{{std::forward(args)...}} {} + + /** + * @brief Fill the array with a single value + * + * This constructor initializes all elements to the given value. + * + * @param value The value to assign to all elements + */ + constexpr explicit array(const V& value) { + data_.fill(value); + } + + array() = default; + + ///@brief Access element with strong ID + reference operator[](K id) { + return data_[static_cast(id)]; + } + + ///@brief Access element with strong ID (const) + const_reference operator[](K id) const { + return data_[static_cast(id)]; + } + + ///@brief Access element with bounds checking + reference at(K id) { + return data_.at(static_cast(id)); + } + + ///@brief Access element with bounds checking (const) + const_reference at(K id) const { + return data_.at(static_cast(id)); + } + + // Iterators + iterator begin() { return data_.begin(); } + iterator end() { return data_.end(); } + const_iterator begin() const { return data_.begin(); } + const_iterator end() const { return data_.end(); } + const_iterator cbegin() const { return data_.cbegin(); } + const_iterator cend() const { return data_.cend(); } + + // Size + constexpr size_type size() const { return N; } + constexpr bool empty() const { return N == 0; } + + // Data + V* data() { return data_.data(); } + const V* data() const { return data_.data(); } + + // Front/Back + reference front() { return data_.front(); } + const_reference front() const { return data_.front(); } + reference back() { return data_.back(); } + const_reference back() const { return data_.back(); } + + // Fill + void fill(const V& value) { data_.fill(value); } + + private: + std::array data_; +}; + +} // namespace vtr diff --git a/libs/libvtrutil/src/vtr_array_view.h b/libs/libvtrutil/src/vtr_array_view.h index 0bb48f65eec..4f1ca034fac 100644 --- a/libs/libvtrutil/src/vtr_array_view.h +++ b/libs/libvtrutil/src/vtr_array_view.h @@ -1,5 +1,4 @@ -#ifndef _VTR_ARRAY_VIEW_H -#define _VTR_ARRAY_VIEW_H +#pragma once #include #include @@ -263,5 +262,3 @@ array_view_id LOGIC_VALUE_STRING = {{"false", "true", "don't care", "unknown"}}; +constexpr std::array LOGIC_VALUE_STRING = {{"false", "true", "don't care", "unknown"}}; } // namespace vtr diff --git a/libs/libvtrutil/src/vtr_ndmatrix.h b/libs/libvtrutil/src/vtr_ndmatrix.h index a9a41ff41b4..7c3eb5d7c49 100644 --- a/libs/libvtrutil/src/vtr_ndmatrix.h +++ b/libs/libvtrutil/src/vtr_ndmatrix.h @@ -248,7 +248,7 @@ class NdMatrixBase { public: //Mutators ///@brief Set all elements to 'value' void fill(T value) { - std::fill(data_.get(), data_.get() + size(), value); + std::generate(data_.get(), data_.get() + size(), [=]() { return value; }); } /** diff --git a/libs/libvtrutil/src/vtr_vector.h b/libs/libvtrutil/src/vtr_vector.h index 921238a77d7..bcf195c40a4 100644 --- a/libs/libvtrutil/src/vtr_vector.h +++ b/libs/libvtrutil/src/vtr_vector.h @@ -1,5 +1,5 @@ -#ifndef VTR_VECTOR -#define VTR_VECTOR +#pragma once + #include #include #include @@ -250,4 +250,3 @@ class vector : private std::vector { key_iterator key_end() const { return key_iterator(key_type(size())); } }; } // namespace vtr -#endif diff --git a/odin_ii/src/core/adders.cpp b/odin_ii/src/core/adders.cpp index ed6ecdb3f1c..4dce94d3758 100644 --- a/odin_ii/src/core/adders.cpp +++ b/odin_ii/src/core/adders.cpp @@ -26,6 +26,7 @@ #include #include +#include "logic_types.h" #include "odin_types.h" #include "odin_util.h" #include "node_creation_library.h" @@ -107,17 +108,18 @@ void report_add_distribution() { * (function: find_hard_adders) *-------------------------------------------------------------------------*/ void find_hard_adders() { - hard_adders = Arch.models; //Disable the size in configuration file.(The threshold for the extra bits). //min_add = configuration.min_hard_adder; min_threshold_adder = configuration.min_threshold_adder; - while (hard_adders != NULL) { + hard_adders = NULL; + for (LogicalModelId model_id : Arch.models.user_models()) { + hard_adders = &Arch.models.get_model(model_id); if (strcmp(hard_adders->name, "adder") == 0) { init_add_distribution(); return; } else { - hard_adders = hard_adders->next; + hard_adders = NULL; } } diff --git a/odin_ii/src/core/hard_blocks.cpp b/odin_ii/src/core/hard_blocks.cpp index ebdd39e4401..e920d54fead 100644 --- a/odin_ii/src/core/hard_blocks.cpp +++ b/odin_ii/src/core/hard_blocks.cpp @@ -26,6 +26,7 @@ #include #include +#include "logic_types.h" #include "odin_types.h" #include "odin_util.h" #include "odin_globals.h" @@ -55,14 +56,11 @@ t_model_ports* get_model_port(t_model_ports* ports, const char* name) { } void cache_hard_block_names() { - t_model* hard_blocks = NULL; - - hard_blocks = Arch.models; hard_block_names = sc_new_string_cache(); - while (hard_blocks) { + for (LogicalModelId model_id : Arch.models.user_models()) { + t_model* hard_blocks = &Arch.models.get_model(model_id); int sc_spot = sc_add_string(hard_block_names, hard_blocks->name); hard_block_names->data[sc_spot] = (void*)hard_blocks; - hard_blocks = hard_blocks->next; } } @@ -112,14 +110,9 @@ void deregister_hard_blocks() { } t_model* find_hard_block(const char* name) { - t_model* hard_blocks; - - hard_blocks = Arch.models; - while (hard_blocks) - if (!strcmp(hard_blocks->name, name)) - return hard_blocks; - else - hard_blocks = hard_blocks->next; + LogicalModelId hard_block_model_id = Arch.models.get_model_by_name(name); + if (hard_block_model_id.is_valid()) + return &Arch.models.get_model(hard_block_model_id); return NULL; } @@ -208,19 +201,17 @@ void define_hard_block(nnode_t* node, FILE* out) { void output_hard_blocks(FILE* out) { t_model_ports* hb_ports; - t_model* hard_blocks; char buffer[MAX_BUF]; int count; int i; oassert(out != NULL); - hard_blocks = Arch.models; - while (hard_blocks != NULL) { + for (LogicalModelId model_id : Arch.models.user_models()) { + t_model* hard_blocks = &Arch.models.get_model(model_id); if (hard_blocks->used == 1) /* Hard Block is utilized */ { //IF the hard_blocks is an adder or a multiplier, we ignore it.(Already print out in add_the_blackbox_for_adds and add_the_blackbox_for_mults) if (strcmp(hard_blocks->name, "adder") == 0 || strcmp(hard_blocks->name, "multiply") == 0) { - hard_blocks = hard_blocks->next; break; } @@ -261,7 +252,6 @@ void output_hard_blocks(FILE* out) { fprintf(out, "\n.blackbox\n.end\n\n"); } - hard_blocks = hard_blocks->next; } return; diff --git a/odin_ii/src/core/multipliers.cpp b/odin_ii/src/core/multipliers.cpp index a14eaa86781..6b62c93e751 100644 --- a/odin_ii/src/core/multipliers.cpp +++ b/odin_ii/src/core/multipliers.cpp @@ -29,6 +29,7 @@ #include #include +#include "logic_types.h" #include "odin_types.h" #include "odin_util.h" #include "node_creation_library.h" @@ -297,14 +298,15 @@ void report_mult_distribution() { * (function: find_hard_multipliers) *-------------------------------------------------------------------------*/ void find_hard_multipliers() { - hard_multipliers = Arch.models; + hard_multipliers = NULL; min_mult = configuration.min_hard_multiplier; - while (hard_multipliers != NULL) { + for (LogicalModelId model_id : Arch.models.user_models()) { + hard_multipliers = &Arch.models.get_model(model_id); if (strcmp(hard_multipliers->name, "multiply") == 0) { init_mult_distribution(); return; } else { - hard_multipliers = hard_multipliers->next; + hard_multipliers = NULL; } } diff --git a/odin_ii/src/verilog/verilog_writer.cpp b/odin_ii/src/verilog/verilog_writer.cpp index 623f16de861..51499a20c56 100644 --- a/odin_ii/src/verilog/verilog_writer.cpp +++ b/odin_ii/src/verilog/verilog_writer.cpp @@ -25,6 +25,7 @@ #include //std::stringstream +#include "logic_types.h" #include "verilog.h" #include "odin_globals.h" #include "hard_blocks.h" @@ -59,15 +60,12 @@ void verilog::writer::_write(const netlist_t* netlist) { } // print out the rest od models, including DSPs in the target architecture - t_model* model = Arch.models; - - while (model) { + for (LogicalModelId model_id : Arch.models.user_models()) { int sc_spot; - if ((sc_spot = sc_lookup_string(this->models_declaration, model->name)) != -1) { + if ((sc_spot = sc_lookup_string(this->models_declaration, Arch.models.model_name(model_id).c_str())) != -1) { fprintf(this->output_file, "%s", (char*)this->models_declaration->data[sc_spot]); fflush(this->output_file); } - model = model->next; } } diff --git a/parmys/parmys-plugin/core/adder.cc b/parmys/parmys-plugin/core/adder.cc index fa184b34c54..ae5cc6ef26d 100644 --- a/parmys/parmys-plugin/core/adder.cc +++ b/parmys/parmys-plugin/core/adder.cc @@ -16,6 +16,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "adder.h" +#include "logic_types.h" #include "multiplier.h" #include "netlist_utils.h" #include "node_utils.h" @@ -96,17 +97,18 @@ void report_add_distribution() *-------------------------------------------------------------------------*/ void find_hard_adders() { - hard_adders = Arch.models; // Disable the size in configuration file.(The threshold for the extra bits). // min_add = configuration.min_hard_adder; min_threshold_adder = configuration.min_threshold_adder; - while (hard_adders != NULL) { + hard_adders = NULL; + for (LogicalModelId model_id : Arch.models.user_models()) { + hard_adders = &Arch.models.get_model(model_id); if (strcmp(hard_adders->name, "adder") == 0) { init_add_distribution(); return; } else { - hard_adders = hard_adders->next; + hard_adders = NULL; } } @@ -1405,4 +1407,4 @@ nnode_t *check_missing_ports(nnode_t *node, uintptr_t traverse_mark_number, netl } return new_node; -} \ No newline at end of file +} diff --git a/parmys/parmys-plugin/core/hard_block.cc b/parmys/parmys-plugin/core/hard_block.cc index a7437518f78..cfadd5b0dac 100644 --- a/parmys/parmys-plugin/core/hard_block.cc +++ b/parmys/parmys-plugin/core/hard_block.cc @@ -15,9 +15,11 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include "hard_block.h" +#include "logic_types.h" #include "memory.h" #include "netlist_utils.h" #include "odin_globals.h" @@ -53,14 +55,17 @@ t_model_ports *get_model_port(t_model_ports *ports, const char *name) void cache_hard_block_names() { - t_model *hard_blocks = NULL; - - hard_blocks = Arch.models; hard_block_names = sc_new_string_cache(); - while (hard_blocks) { + // After a change to the construction of the user models, the order was + // reversed, which slightly changed the results. Reversing them back to + // attain the same results, simplifying my testing. + // TODO: Regenerate the golden solutions to use the new model order. + std::vector user_models(Arch.models.user_models().begin(), Arch.models.user_models().end()); + std::reverse(user_models.begin(), user_models.end()); + for (LogicalModelId model_id : user_models) { + t_model* hard_blocks = &Arch.models.get_model(model_id); int sc_spot = sc_add_string(hard_block_names, hard_blocks->name); hard_block_names->data[sc_spot] = (void *)hard_blocks; - hard_blocks = hard_blocks->next; } } @@ -98,14 +103,9 @@ void register_hard_blocks() t_model *find_hard_block(const char *name) { - t_model *hard_blocks; - - hard_blocks = Arch.models; - while (hard_blocks) - if (!strcmp(hard_blocks->name, name)) - return hard_blocks; - else - hard_blocks = hard_blocks->next; + LogicalModelId hard_block_model_id = Arch.models.get_model_by_name(name); + if (hard_block_model_id.is_valid()) + return &Arch.models.get_model(hard_block_model_id); return NULL; } @@ -201,16 +201,20 @@ void cell_hard_block(nnode_t *node, Yosys::Module *module, netlist_t *netlist, Y void output_hard_blocks_yosys(Yosys::Design *design) { t_model_ports *hb_ports; - t_model *hard_blocks; - hard_blocks = Arch.models; - while (hard_blocks != NULL) { + // After a change to the construction of the user models, the order was + // reversed, which slightly changed the results. Reversing them back to + // attain the same results, simplifying my testing. + // TODO: Regenerate the golden solutions to use the new model order. + std::vector user_models(Arch.models.user_models().begin(), Arch.models.user_models().end()); + std::reverse(user_models.begin(), user_models.end()); + for (LogicalModelId model_id : user_models) { + t_model* hard_blocks = &Arch.models.get_model(model_id); if (hard_blocks->used == 1) /* Hard Block is utilized */ { // IF the hard_blocks is an adder or a multiplier, we ignore it.(Already print out in add_the_blackbox_for_adds and // add_the_blackbox_for_mults) if (strcmp(hard_blocks->name, "adder") == 0 || strcmp(hard_blocks->name, "multiply") == 0) { - hard_blocks = hard_blocks->next; break; } @@ -277,8 +281,6 @@ void output_hard_blocks_yosys(Yosys::Design *design) module->attributes[Yosys::ID::blackbox] = Yosys::RTLIL::Const(1); } - - hard_blocks = hard_blocks->next; } return; diff --git a/parmys/parmys-plugin/core/multiplier.cc b/parmys/parmys-plugin/core/multiplier.cc index befb0b337bd..3a411217f25 100644 --- a/parmys/parmys-plugin/core/multiplier.cc +++ b/parmys/parmys-plugin/core/multiplier.cc @@ -16,6 +16,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "multiplier.h" +#include "logic_types.h" #include "netlist_utils.h" #include "node_utils.h" #include "odin_globals.h" @@ -544,14 +545,15 @@ void report_mult_distribution() *-------------------------------------------------------------------------*/ void find_hard_multipliers() { - hard_multipliers = Arch.models; + hard_multipliers = NULL; min_mult = configuration.min_hard_multiplier; - while (hard_multipliers != NULL) { + for (LogicalModelId model_id : Arch.models.user_models()) { + hard_multipliers = &Arch.models.get_model(model_id); if (strcmp(hard_multipliers->name, "multiply") == 0) { init_mult_distribution(); return; } else { - hard_multipliers = hard_multipliers->next; + hard_multipliers = NULL; } } diff --git a/parmys/parmys-plugin/parmys.cc b/parmys/parmys-plugin/parmys.cc index 910f7711dee..158db0253b8 100644 --- a/parmys/parmys-plugin/parmys.cc +++ b/parmys/parmys-plugin/parmys.cc @@ -1159,9 +1159,8 @@ struct ParMYSPass : public Pass { free_netlist(transformed); - if (Arch.models) { + if (!Arch.models.all_models().empty()) { free_arch(&Arch); - Arch.models = nullptr; } free_type_descriptors(logical_block_types); @@ -1183,4 +1182,4 @@ struct ParMYSPass : public Pass { } } ParMYSPass; -PRIVATE_NAMESPACE_END \ No newline at end of file +PRIVATE_NAMESPACE_END diff --git a/parmys/parmys-plugin/parmys_arch.cc b/parmys/parmys-plugin/parmys_arch.cc index 97a8591ab60..995c9356264 100644 --- a/parmys/parmys-plugin/parmys_arch.cc +++ b/parmys/parmys-plugin/parmys_arch.cc @@ -120,15 +120,19 @@ struct ParmysArchPass : public Pass { const char *arch_info_file = "arch.info"; EchoArch(arch_info_file, physical_tile_types, logical_block_types, &arch); - t_model *hb = arch.models; - while (hb) { + // After a change to the construction of the user models, the order was + // reversed, which slightly changed the results. Reversing them back to + // attain the same results. + // TODO: Regenerate the golden solutions to use the new model order. + std::vector user_models(arch.models.user_models().begin(), arch.models.user_models().end()); + std::reverse(user_models.begin(), user_models.end()); + for (LogicalModelId model_id : user_models) { + t_model* hb = &arch.models.get_model(model_id); if (strcmp(hb->name, SINGLE_PORT_RAM_string) && strcmp(hb->name, DUAL_PORT_RAM_string) && strcmp(hb->name, "multiply") && strcmp(hb->name, "adder")) { add_hb_to_design(hb, design); log("Hard block added to the Design ---> `%s`\n", hb->name); } - - hb = hb->next; } // CLEAN UP diff --git a/utils/fasm/src/fasm.cpp b/utils/fasm/src/fasm.cpp index 2785c1149e8..9a10808cdb1 100644 --- a/utils/fasm/src/fasm.cpp +++ b/utils/fasm/src/fasm.cpp @@ -591,14 +591,16 @@ void FasmWriterVisitor::check_for_param(const t_pb *atom) { void FasmWriterVisitor::check_for_lut(const t_pb* atom) { auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; auto atom_blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_blk_id == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.netlist().block_model(atom_blk_id); - if (model->name == std::string(MODEL_NAMES)) { + LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); + LogicalModelId model_id = atom_ctx.netlist().block_model(atom_blk_id); + if (model_id == names_model_id) { VTR_ASSERT(atom->pb_graph_node != nullptr); const auto *lut_definition = find_lut(atom->pb_graph_node); VTR_ASSERT(lut_definition->num_inputs == *atom->pb_graph_node->num_input_pins); diff --git a/utils/fasm/test/test_fasm.cpp b/utils/fasm/test/test_fasm.cpp index 9ee9a142b48..6411dd97f06 100644 --- a/utils/fasm/test/test_fasm.cpp +++ b/utils/fasm/test/test_fasm.cpp @@ -7,13 +7,11 @@ #include "rr_metadata.h" #include "fasm.h" #include "fasm_utils.h" -#include "arch_util.h" #include "rr_graph_writer.h" #include #include #include #include -#include #include "post_routing_pb_pin_fixup.h" #include "sync_netlists_to_routing_flat.h" @@ -77,7 +75,7 @@ TEST_CASE("substitute_tags_correct", "[fasm]") { auto result = fasm::substitute_tags(feature, tags); - REQUIRE(result.compare("LCLB_X7Y8_SLICE") == 0); + REQUIRE(result == "LCLB_X7Y8_SLICE"); } TEST_CASE("substitute_tags_undef", "[fasm]") { @@ -270,7 +268,7 @@ TEST_CASE("fasm_integration_test", "[fasm]") { // Add additional features to edges that go to CLB.I[11:0] pins // to correlate them with features of CLB input mux later. auto sink_type = rr_graph.node_type(RRNodeId(sink_inode)); - if (sink_type == IPIN) { + if (sink_type == e_rr_type::IPIN) { auto pin_feature = get_pin_feature(sink_inode); value = value + "\n" + pin_feature; } @@ -368,8 +366,8 @@ TEST_CASE("fasm_integration_test", "[fasm]") { continue; } - if (line.find("#") != std::string::npos) { - auto init_pos = line.find("#"); + if (line.find('#') != std::string::npos) { + auto init_pos = line.find('#'); lut_def = line.substr(init_pos+2); continue; } diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index 5074d79cc09..e9a8ccd3a87 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -97,7 +97,7 @@ static void do_one_route(const Netlist<>& net_list, segment_inf, is_flat); - ConnectionRouter router( + SerialConnectionRouter router( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -185,7 +185,7 @@ static void profile_source(const Netlist<>& net_list, VTR_ASSERT(sink_ptc != OPEN); //TODO: should pass layer_num instead of 0 to node_lookup once the multi-die FPGAs support is completed - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(0, sink_x, sink_y, SINK, sink_ptc); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(0, sink_x, sink_y, e_rr_type::SINK, sink_ptc); if (directconnect_exists(source_rr_node, sink_rr_node)) { //Skip if we shouldn't measure direct connects and a direct connect exists @@ -292,7 +292,7 @@ int main(int argc, const char **argv) { alloc_routing_structs(chan_width, vpr_setup.RouterOpts, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, Arch.directs, is_flat); diff --git a/utils/vqm2blif/src/base/hard_block_recog.cpp b/utils/vqm2blif/src/base/hard_block_recog.cpp index 60be10d9457..f16f8ebfa3d 100644 --- a/utils/vqm2blif/src/base/hard_block_recog.cpp +++ b/utils/vqm2blif/src/base/hard_block_recog.cpp @@ -124,6 +124,7 @@ #include "hard_block_recog.h" +#include "logic_types.h" //============================================================================================ // INTERNAL FUNCTION DECLARATIONS @@ -133,7 +134,7 @@ static void initialize_hard_block_models(t_arch* main_arch, std::vector* hard_block_type_name_list, t_hard_block_recog* module_hard_block_node_refs_and_info); -static bool create_and_initialize_all_hard_block_ports(t_model* hard_block_arch_model, t_hard_block_recog* storage_of_hard_block_info); +static bool create_and_initialize_all_hard_block_ports(const t_model& hard_block_arch_model, t_hard_block_recog* storage_of_hard_block_info); static void create_hard_block_port_info_structure(t_hard_block_recog* storage_of_hard_block_info, std::string hard_block_type_name); @@ -323,7 +324,6 @@ void add_hard_blocks_to_netlist(t_module* main_module, t_arch* main_arch, std::v */ static void initialize_hard_block_models(t_arch* main_arch, std::vector* hard_block_type_names, t_hard_block_recog* storage_of_hard_block_info) { - t_model* hard_block_model = NULL; std::vector::iterator hard_block_type_name_traverser; bool single_hard_block_init_result = false; @@ -331,15 +331,16 @@ static void initialize_hard_block_models(t_arch* main_arch, std::vectorbegin(); hard_block_type_name_traverser != hard_block_type_names->end(); hard_block_type_name_traverser++) { // get the corresponding model for each hard block name - hard_block_model = find_arch_model_by_name(*hard_block_type_name_traverser, main_arch->models); + LogicalModelId hard_block_model_id = main_arch->models.get_model_by_name(*hard_block_type_name_traverser); // a check to see if the model was found within the FPGA architecture - if (hard_block_model == NULL) + if (!hard_block_model_id.is_valid()) { throw vtr::VtrError("The provided hard block model: '" + *hard_block_type_name_traverser + "' was not found within the corresponding FPGA architecture."); } else - { + { + const t_model& hard_block_model = main_arch->models.get_model(hard_block_model_id); // store the port information for the current hard block model single_hard_block_init_result = create_and_initialize_all_hard_block_ports(hard_block_model, storage_of_hard_block_info); @@ -478,15 +479,15 @@ static void process_module_nodes_and_create_hard_blocks(t_module* main_module, s * the FPGA had any ports. * */ -static bool create_and_initialize_all_hard_block_ports(t_model* hard_block_arch_model, t_hard_block_recog* storage_of_hard_block_info) +static bool create_and_initialize_all_hard_block_ports(const t_model& hard_block_arch_model, t_hard_block_recog* storage_of_hard_block_info) { int hard_block_port_index = 0; - std::string hard_block_arch_model_name = hard_block_arch_model->name; + std::string hard_block_arch_model_name = hard_block_arch_model.name; bool result = true; // get the hard block ports - t_model_ports* input_ports = hard_block_arch_model->inputs; - t_model_ports* output_ports = hard_block_arch_model->outputs; + t_model_ports* input_ports = hard_block_arch_model.inputs; + t_model_ports* output_ports = hard_block_arch_model.outputs; //initialize a hard block node port array create_hard_block_port_info_structure(storage_of_hard_block_info,hard_block_arch_model_name); diff --git a/utils/vqm2blif/src/base/preprocess.cpp b/utils/vqm2blif/src/base/preprocess.cpp index 8ae41297d23..092d8a67180 100644 --- a/utils/vqm2blif/src/base/preprocess.cpp +++ b/utils/vqm2blif/src/base/preprocess.cpp @@ -2,6 +2,7 @@ // INCLUDES //============================================================================================ #include "preprocess.h" +#include "logic_types.h" #include "vqm_common.h" #include "lut_stats.h" #include "vtr_memory.h" @@ -9,7 +10,6 @@ #include "vtr_assert.h" #include "vqm2blif_util.h" #include "physical_types.h" -#include //============================================================================================ @@ -19,9 +19,9 @@ //Functions to identify and decompose inout pins void decompose_inout_pins(t_module* module, t_arch* arch, string device); -t_model* find_model_in_architecture(t_model* arch_models, t_node* node, string device); +LogicalModelId find_model_in_architecture(const LogicalModels& arch_models, t_node* node, string device); -t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_association* node_port); +t_model_ports* find_port_in_architecture_model(const t_model& arch_model, t_node_port_association* node_port); char* prefix_string(const char* prefix, const char* base); @@ -314,11 +314,11 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ */ //Architecture pointers - t_model* arch_model; t_model_ports* arch_model_port; //Find the model - arch_model = find_model_in_architecture(arch->models, node, device); + LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); + const t_model& arch_model = arch->models.get_model(arch_model_id); //Find the architecure model port arch_model_port = find_port_in_architecture_model(arch_model, node_port); @@ -372,7 +372,7 @@ void decompose_inout_pins(t_module* module, t_arch* arch, string device){ cout << "\t>> Decomposed " << number_of_inout_pins_found << " 'inout' pin(s), moving " << number_of_nets_moved << " net(s)" << endl; } -t_model* find_model_in_architecture(t_model* arch_models, t_node* node, string device) { +LogicalModelId find_model_in_architecture(const LogicalModels& arch_models, t_node* node, string device) { /* * Finds the archtecture module corresponding to the node type * @@ -387,20 +387,15 @@ t_model* find_model_in_architecture(t_model* arch_models, t_node* node, string d string elaborated_name = generate_opname(node, arch_models, device); //Find the correct model, by name matching - t_model* arch_model = arch_models; - while((arch_model) && (strcmp(elaborated_name.c_str(), arch_model->name) != 0)) { - //Move to the next model - arch_model = arch_model->next; - } + LogicalModelId arch_model_id = arch_models.get_model_by_name(elaborated_name); //The model must be in the arch file - if (arch_model == NULL) { + if (!arch_model_id.is_valid()) { cout << "Error: could not find model in architecture file for '" << node->type << "'\n"; exit(1); } - VTR_ASSERT(arch_model != NULL); - return arch_model; + return arch_model_id; } char* prefix_string(const char* prefix, const char* base) { @@ -416,7 +411,7 @@ char* prefix_string(const char* prefix, const char* base) { return new_string; } -t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_association* node_port) { +t_model_ports* find_port_in_architecture_model(const t_model& arch_model, t_node_port_association* node_port) { /* * Finds the module port corresponding to the port name * @@ -435,7 +430,7 @@ t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_ //Check inputs //Find the correct port, by name matching - t_model_ports* arch_model_port = arch_model->inputs; + t_model_ports* arch_model_port = arch_model.inputs; //Until NULL or a matching port name while ((arch_model_port) && (strcmp(arch_model_port->name, node_port->port_name) != 0)) { @@ -451,7 +446,7 @@ t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_ //Not an input should be an output //Check outputs - arch_model_port = arch_model->outputs; + arch_model_port = arch_model.outputs; //Until NULL or a matching port name while ((arch_model_port) && (strcmp(arch_model_port->name, node_port->port_name) != 0)) { @@ -465,7 +460,7 @@ t_model_ports* find_port_in_architecture_model(t_model* arch_model, t_node_port_ //arch_model_port must be either an input or an output, // hence it should never be NULL at this point if (arch_model_port == NULL) { - cout << "Error: could not find port '" << node_port->port_name << "' on model '" << arch_model->name << "' in architecture file\n"; + cout << "Error: could not find port '" << node_port->port_name << "' on model '" << arch_model.name << "' in architecture file\n"; exit(1); } } @@ -1496,7 +1491,8 @@ void check_and_fix_clock_to_normal_port_connections(t_module* module, t_arch* ar //check whether it is the driver //Find the model - t_model* arch_model = find_model_in_architecture(arch->models, node, device); + LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); + const t_model& arch_model = arch->models.get_model(arch_model_id); //Look-up the arch model port t_model_ports* arch_model_port = find_port_in_architecture_model(arch_model, node_port); @@ -1618,7 +1614,8 @@ void check_and_fix_clock_to_normal_port_connections(t_module* module, t_arch* ar t_node_port_association* node_port = node->array_of_ports[j]; //Find the model - t_model* arch_model = find_model_in_architecture(arch->models, node, device); + LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); + const t_model& arch_model = arch->models.get_model(arch_model_id); //Look-up the arch model port t_model_ports* arch_model_port = find_port_in_architecture_model(arch_model, node_port); @@ -2516,11 +2513,11 @@ t_net_driver_map identify_net_drivers(t_module* module, t_arch* arch, t_global_p */ //Architecture pointers - t_model* arch_model; t_model_ports* arch_model_port; //Find the model - arch_model = find_model_in_architecture(arch->models, node, device); + LogicalModelId arch_model_id = find_model_in_architecture(arch->models, node, device); + const t_model& arch_model = arch->models.get_model(arch_model_id); //Find the architecure model port arch_model_port = find_port_in_architecture_model(arch_model, node_port); diff --git a/utils/vqm2blif/src/base/vqm2blif.h b/utils/vqm2blif/src/base/vqm2blif.h index e206ba11d7c..c855dc7b200 100644 --- a/utils/vqm2blif/src/base/vqm2blif.h +++ b/utils/vqm2blif/src/base/vqm2blif.h @@ -56,6 +56,7 @@ // INCLUDES //============================================================================================ +#include "logic_types.h" #include "vqm2blif_util.h" #include "lutmask.h" #include "cleanup.h" @@ -74,7 +75,7 @@ struct t_subckt_param_attr { typedef struct s_blif_subckt{ string inst_name; - t_model* model_type; + LogicalModelId model_type; portmap input_cnxns; diff --git a/utils/vqm2blif/src/base/vqm2blif_util.cpp b/utils/vqm2blif/src/base/vqm2blif_util.cpp index dbee284a5f7..d2bd322c5a2 100644 --- a/utils/vqm2blif/src/base/vqm2blif_util.cpp +++ b/utils/vqm2blif/src/base/vqm2blif_util.cpp @@ -1,6 +1,6 @@ #include "vqm2blif_util.h" +#include "logic_types.h" #include "vtr_util.h" -#include "vtr_memory.h" #include "vtr_assert.h" #define dsp_clock_count 15 @@ -215,7 +215,7 @@ string get_wire_name(t_pin_def* net, int index){ //============================================================================================ //============================================================================================ -string generate_opname (t_node* vqm_node, t_model* arch_models, string device){ +string generate_opname (t_node* vqm_node, const LogicalModels& arch_models, string device){ //Add support for different architectures here. // Currently only support Stratix IV and Stratix 10 string mode_hash; @@ -225,7 +225,8 @@ string generate_opname (t_node* vqm_node, t_model* arch_models, string device){ mode_hash = generate_opname_stratixiv(vqm_node, arch_models); //Final sanity check - if (NULL == find_arch_model_by_name(mode_hash, arch_models)){ + LogicalModelId arch_model_id = arch_models.get_model_by_name(mode_hash); + if (!arch_model_id.is_valid()) { cout << "Error: could not find primitive '" << mode_hash << "' in architecture file" << endl; exit(1); } @@ -234,7 +235,7 @@ string generate_opname (t_node* vqm_node, t_model* arch_models, string device){ } -string generate_opname_stratixiv (t_node* vqm_node, t_model* arch_models){ +string generate_opname_stratixiv (t_node* vqm_node, const LogicalModels& arch_models){ /* Generates a mode-hash string based on a node's name and parameter set * * ARGUMENTS @@ -281,16 +282,14 @@ string generate_opname_stratixiv (t_node* vqm_node, t_model* arch_models){ * DSP Block Multipliers */ if(strcmp(vqm_node->type, "stratixiv_mac_mult") == 0) { - generate_opname_stratixiv_dsp_mult(vqm_node, arch_models, mode_hash); - + generate_opname_stratixiv_dsp_mult(vqm_node, mode_hash); } /* * DSP Block Output (MAC) */ if(strcmp(vqm_node->type, "stratixiv_mac_out") == 0) { - generate_opname_stratixiv_dsp_out(vqm_node, arch_models, mode_hash); - + generate_opname_stratixiv_dsp_out(vqm_node, mode_hash); } /* @@ -303,7 +302,7 @@ string generate_opname_stratixiv (t_node* vqm_node, t_model* arch_models){ return mode_hash; } -void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, t_model* /*arch_models*/, string& mode_hash) { +void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, string& mode_hash) { //We check for all mac_mult's input ports to see if any use a clock // if so, we set ALL input ports to be registered. While this is an approximation, // it would be very unusually to have only some of the ports registered. @@ -413,7 +412,7 @@ void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, t_model* /*arch_model } } -void generate_opname_stratixiv_dsp_out (t_node* vqm_node, t_model* /*arch_models*/, string& mode_hash) { +void generate_opname_stratixiv_dsp_out (t_node* vqm_node, string& mode_hash) { //It is not practical to model all of the internal registers of the mac_out block, as this // would significantly increase the size of the architecture description. As a result, we // only identify whether the input or output registers are used. @@ -525,7 +524,7 @@ void generate_opname_stratixiv_dsp_out (t_node* vqm_node, t_model* /*arch_models } -void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_hash, string device) { +void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, string& mode_hash, string device) { if(device == "stratixiv") VTR_ASSERT(strcmp(vqm_node->type, "stratixiv_ram_block") == 0); @@ -607,7 +606,8 @@ void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_h //Only print the address width, the data widths are handled by the VPR memory class mode_hash.append(".port_a_address_width{" + std::to_string(ram_info.port_a_addr_width) + "}"); - if (find_arch_model_by_name(mode_hash, arch_models) == NULL){ + LogicalModelId arch_model_id = arch_models.get_model_by_name(mode_hash); + if (!arch_model_id.is_valid()) { cout << "Error: could not find single port memory primitive '" << mode_hash << "' in architecture file" << endl; exit(1); } @@ -623,7 +623,8 @@ void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_h mode_hash.append(".port_a_address_width{" + std::to_string(ram_info.port_a_addr_width) + "}"); mode_hash.append(".port_b_address_width{" + std::to_string(ram_info.port_b_addr_width) + "}"); - if (find_arch_model_by_name(mode_hash, arch_models) == NULL){ + LogicalModelId arch_model_id = arch_models.get_model_by_name(mode_hash); + if (!arch_model_id.is_valid()) { cout << "Error: could not find dual port (non-mixed_width) memory primitive '" << mode_hash << "' in architecture file"; exit(1); } @@ -644,7 +645,8 @@ void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_h tmp_mode_hash.append(".port_a_data_width{" + std::to_string(ram_info.port_a_data_width) + "}"); tmp_mode_hash.append(".port_b_data_width{" + std::to_string(ram_info.port_b_data_width) + "}"); - if (find_arch_model_by_name(tmp_mode_hash, arch_models) == NULL){ + LogicalModelId arch_model_id = arch_models.get_model_by_name(tmp_mode_hash); + if (!arch_model_id.is_valid()) { //3a) Not found, use the default name (no specific address/data widths) ; // do nothing } else { @@ -655,7 +657,7 @@ void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_h } } -string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models){ +string generate_opname_stratix10 (t_node* vqm_node, const LogicalModels& arch_models){ /* Generates a mode-hash string based on a node's name and parameter set * * ARGUMENTS @@ -707,7 +709,7 @@ string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models){ * DSP Block - fixed point */ if(strcmp(vqm_node->type, "fourteennm_mac") == 0) { - generate_opname_stratix10_dsp(vqm_node, arch_models, mode_hash, 0); + generate_opname_stratix10_dsp(vqm_node, mode_hash, 0); } @@ -715,7 +717,7 @@ string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models){ * DSP Block - floating point */ if(strcmp(vqm_node->type, "fourteennm_fp_mac") == 0) { - generate_opname_stratix10_dsp(vqm_node, arch_models, mode_hash, 1); + generate_opname_stratix10_dsp(vqm_node, mode_hash, 1); } @@ -729,7 +731,7 @@ string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models){ return mode_hash; } -void generate_opname_stratix10_dsp (t_node* vqm_node, t_model* /*arch_models*/, string& mode_hash, bool dsp_mode) { +void generate_opname_stratix10_dsp (t_node* vqm_node, string& mode_hash, bool dsp_mode) { // // It is not practical to model all of the internal registers of the mac block, as this // would significantly increase the size of the architecture description. As a result, we @@ -904,28 +906,6 @@ void clean_name(char* name) { } } -//============================================================================================ -//============================================================================================ -t_model* find_arch_model_by_name(string model_name, t_model* arch_models) { - /* - * Finds the archtecture module corresponding to the model_name string - * - * model_name : the model name to match - * arch_models: the head of the linked list of architecture models - * - * Returns: A pointer to the corresponding model (or NULL if not found) - */ - - //Find the correct model, by name matching - t_model* arch_model = arch_models; - while((arch_model) && (strcmp(model_name.c_str(), arch_model->name) != 0)) { - //Move to the next model - arch_model = arch_model->next; - } - - return arch_model; -} - //============================================================================================ //============================================================================================ diff --git a/utils/vqm2blif/src/base/vqm2blif_util.h b/utils/vqm2blif/src/base/vqm2blif_util.h index 314724e6226..45cc5adedf4 100644 --- a/utils/vqm2blif/src/base/vqm2blif_util.h +++ b/utils/vqm2blif/src/base/vqm2blif_util.h @@ -13,6 +13,7 @@ //these assignments are not observed. Buses in a VQM File are flattened into 1-bit wide assigns. //NOTE: The functionality of this option is untested. +#include "logic_types.h" #define MAX_LEN 350 //maximum length of a port/net name #define MAX_PPL 10 //maximum number of ports that can be put into one line of a BLIF @@ -175,22 +176,19 @@ void construct_filename (char* filename, const char* path, const char* ext); //c //Naming Conventions -string generate_opname (t_node* vqm_node, t_model* arch_models, string device); //generates a mode-hashed name for a subcircuit instance +string generate_opname (t_node* vqm_node, const LogicalModels& arch_models, string device); //generates a mode-hashed name for a subcircuit instance -void generate_opname_ram (t_node* vqm_node, t_model* arch_models, string& mode_hash, string device); //mode-hash for RAM blocks +void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, string& mode_hash, string device); //mode-hash for RAM blocks -string generate_opname_stratixiv (t_node* vqm_node, t_model* arch_models); //mode-hash for Stratix IV -void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, t_model* arch_models, string& mode_hash); //mode-hash for Stratix IV DSP Multiplers -void generate_opname_stratixiv_dsp_out (t_node* vqm_node, t_model* arch_models, string& mode_hash); //mode-hash for Stratix IV DSP Output (MAC) +string generate_opname_stratixiv (t_node* vqm_node, const LogicalModels& arch_models); //mode-hash for Stratix IV +void generate_opname_stratixiv_dsp_mult (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix IV DSP Multiplers +void generate_opname_stratixiv_dsp_out (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix IV DSP Output (MAC) -string generate_opname_stratix10 (t_node* vqm_node, t_model* arch_models); //mode-hash for Stratix 10 -void generate_opname_stratix10_ram (t_node* vqm_node, t_model* arch_models, string& mode_hash); //mode-hash for Stratix 10 RAM blocks -void generate_opname_stratix10_dsp (t_node* vqm_node, t_model* arch_models, string& mode_hash, bool dsp_mode); //mode-hash for Stratix 10 DSP fixed point Multiplers +string generate_opname_stratix10 (t_node* vqm_node, const LogicalModels& arch_models); //mode-hash for Stratix 10 +void generate_opname_stratix10_dsp (t_node* vqm_node, string& mode_hash, bool dsp_mode); //mode-hash for Stratix 10 DSP fixed point Multiplers void generate_opname_stratix10_lut (t_node* vqm_node, string& mode_hash); //mode-hash for Stratix 10 LUTs void remap_lut_ports(t_node* vqm_node); // remaps the input ports of the LUT atom to the ports [dataa-datae] -t_model* find_arch_model_by_name(string model_name, t_model* arch_models); //returns the pointer to a module from the arch file, searches by name - string get_wire_name(t_pin_def* net, int index); //returns a string with the appropriate wire name string append_index_to_str (string busname, int index); //appends an integer index to the end of a string diff --git a/utils/vqm2blif/src/main.cpp b/utils/vqm2blif/src/main.cpp index 36c30b57e07..20e82c0ac2f 100644 --- a/utils/vqm2blif/src/main.cpp +++ b/utils/vqm2blif/src/main.cpp @@ -77,11 +77,13 @@ * For more, see "logic_types.h", "read_xml_arch_file.h" and "read_xml_arch_file.c" in libvpr *********************************************************************************************/ +#include "logic_types.h" #include "vqm2blif.h" #include "lut_stats.h" #include "vtr_error.h" #include "physical_types.h" #include "hard_block_recog.h" +#include "vtr_vector.h" #include @@ -97,8 +99,8 @@ lut_support_map supported_luts; //map structure for verifying a VQM primitive ag //LUT configurations (see lut_regoc.h & lut_recog.cpp) -int* model_count; //array of flags indicating whether a model read from - //the architecture was instantiated in the .vqm file. +vtr::vector model_count; //array of flags indicating whether a model read from + //the architecture was instantiated in the .vqm file. t_boolean debug_mode; //user-set flag causing the creation of intermediate files //with debug information. @@ -157,19 +159,19 @@ void cmd_line_parse (int argc, char** argv, string* sourcefile, string* archfile //Execution Functions void init_blif_models(t_blif_model* my_model, t_module* my_module, t_arch* arch, string device); - void subckt_prep(t_model* cur_model); + void subckt_prep(const LogicalModels& models); void init_blif_subckts (t_node **vqm_nodes, int number_of_vqm_nodes, - t_model *arch_models, t_blif_model* my_model, string device); + const LogicalModels& models, t_blif_model* my_model, string device); //1-to-1 Subcircuit Function //Translates one VQM Node into one BLIF Subcircuit, appends a mode-hash based on //parameters if elab_mode is MODES or MODES_TIMING. - void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_subckts, string device); + void push_node_1_to_1 (t_node* vqm_node, const LogicalModels& models, scktvec* blif_subckts, string device); //Atomize Subcircuit Function //Uses select parameters and a dictionary to atomize each block and //name it as the dictionary says. - void push_node_atomize (t_node* vqm_node, t_model* arch_models, scktvec* blif_subckts); + void push_node_atomize (t_node* vqm_node, const LogicalModels& models, scktvec* blif_subckts); //General Subcircuit Initialization //No matter the translation, models from the architecture get turned into @@ -187,7 +189,7 @@ void init_blif_models(t_blif_model* my_model, t_module* my_module, t_arch* arch, void dump_blif (char* blif_file, t_blif_model* main_model, t_arch* arch, t_boolean print_unused_subckt_pins); -void dump_main_model(t_blif_model* model, ofstream& outfile, t_boolean print_unused_subckt_pins, t_boolean eblif_format, t_boolean debug); +void dump_main_model(t_blif_model* model, ofstream& outfile, const LogicalModels& models, t_boolean print_unused_subckt_pins, t_boolean eblif_format, t_boolean debug); void dump_portlist (ofstream& outfile, pinvec ports, t_boolean debug); void dump_assignments(ofstream& outfile, t_blif_model* model, t_boolean eblif_format, t_boolean debug); @@ -208,7 +210,7 @@ void dump_wire_assign(ofstream& outfile, string target_name, void dump_luts (ofstream& outfile, lutvec* blif_luts, t_boolean eblif_format, t_boolean debug); -void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pins, t_boolean eblif_format, t_boolean debug); +void dump_subckts(ofstream& outfile, scktvec* subckts, const LogicalModels& models, t_boolean print_unused_pins, t_boolean eblif_format, t_boolean debug); void dump_subckt_map (ofstream& outfile, portmap* map, t_model_ports* temp_port, const char* inst_name, const char* maptype, int s_index, t_boolean print_unused_pins, t_boolean debug, bool last); @@ -216,7 +218,7 @@ size_t count_print_pins(t_model_ports* temp_port, portmap* map, t_boolean print_ void dump_subckt_portlist(ofstream& outfile, t_model_ports* port, string indent, t_boolean debug); -void dump_subckt_models(t_model* temp_model, ofstream& outfile, t_boolean debug); +void dump_subckt_models(const LogicalModels& models, ofstream& outfile, t_boolean debug); //Debug functions void echo_module (char* echo_file, const char* vqm_filename, t_module* my_module); @@ -224,7 +226,7 @@ void echo_module_pins (ofstream& outfile, t_module* module); void echo_module_assigns (ofstream& outfile, t_module* module); void echo_module_nodes (ofstream& outfile, t_module* module); void echo_blif_model (char* echo_file, const char* vqm_filename, - t_blif_model* my_model, t_model* temp_model); + t_blif_model* my_model, const LogicalModels& models); //Other Functions @@ -335,7 +337,7 @@ int main(int argc, char* argv[]) numTypes = logical_block_types.size(); VTR_ASSERT((types) && (numTypes > 0)); - VTR_ASSERT(arch.models != NULL); + VTR_ASSERT(!arch.models.user_models().empty()); //Pre-process the netlist // Currently this just 'cleans up' bi-directional inout pins @@ -858,7 +860,7 @@ void init_blif_models(t_blif_model* my_model, t_module* my_module, t_arch* arch, //============================================================================================ void init_blif_subckts ( t_node **vqm_nodes, int number_of_vqm_nodes, - t_model *arch_models, + const LogicalModels& models, t_blif_model* my_model, string device){ /* Initializes the subcircuits vector within a t_blif_model based on a t_node array. * @@ -876,8 +878,7 @@ void init_blif_subckts ( t_node **vqm_nodes, t_node* temp_node; //from vqm_dll.h //Preparations before the subcircuits can be assigned. - VTR_ASSERT(arch_models != NULL); - subckt_prep(arch_models); + subckt_prep(models); VTR_ASSERT((vqm_nodes != NULL)&&(vqm_nodes[0] != NULL)&&(number_of_vqm_nodes >= 0)); @@ -896,9 +897,9 @@ void init_blif_subckts ( t_node **vqm_nodes, if ((lut_mode == BLIF)&&(is_lut(temp_node))){ push_lut ( temp_node, &(my_model->luts) ); } else if ((elab_mode == NONE)||(elab_mode == MODES)||(elab_mode == MODES_TIMING)){ - push_node_1_to_1 (temp_node, arch_models, &(my_model->subckts), device); + push_node_1_to_1 (temp_node, models, &(my_model->subckts), device); } else if (elab_mode == ATOMS){ - push_node_atomize (temp_node, arch_models, &(my_model->subckts)); + push_node_atomize (temp_node, models, &(my_model->subckts)); } else { //Should never get here; a bad elab_mode should be rejected at parse-time cout << "\nERROR: Corrupted Elaboration Mode.\n" ; @@ -910,7 +911,7 @@ void init_blif_subckts ( t_node **vqm_nodes, //============================================================================================ //============================================================================================ -void subckt_prep(t_model* cur_model){ +void subckt_prep(const LogicalModels& models){ /* Accomplishes preparatory tasks before the subcircuits of a blif_model can be initialized. * * ARGUMENTS @@ -918,24 +919,10 @@ void subckt_prep(t_model* cur_model){ * Linked list containing all model information from the Architecture file. */ -//TASK 1: Find the maximum index among the models in the Architecture. - int max_model_index; - max_model_index = cur_model->index; - while(cur_model){ - //Cycle through the list, save the highest index. - if (cur_model->index > max_model_index){ - max_model_index = cur_model->index; - } - cur_model = cur_model->next; - } +//TASK 1: Allocate and initialize the model_count array (global). + model_count = vtr::vector(models.all_models().size(), 0); -//TASK 2: Allocate and initialize the model_count array (global). - model_count = (int*)malloc((max_model_index + 1)*sizeof(int)); - for (int i = 0; i <= max_model_index; i++){ - model_count[i] = 0; - } - -//TASK 3: Initialize the unconn and open_port structures. +//TASK 2: Initialize the unconn and open_port structures. unconn.name = strdup("unconn"); unconn.indexed = T_FALSE; unconn.type = PIN_WIRE; @@ -951,7 +938,7 @@ void subckt_prep(t_model* cur_model){ //============================================================================================ //============================================================================================ -void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_subckts, string device){ +void push_node_1_to_1 (t_node* vqm_node, const LogicalModels& models, scktvec* blif_subckts, string device){ /* Interprets each VQM block as a single instance of a BLIF subcircuit. Depending on * the global elab_mode, the Architecture will be searched either for the VQM block name as-is * or a name appended with a special mode-hash, generated from parameters of the VQM block. @@ -967,16 +954,12 @@ void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_sub //temporary process variables t_blif_subckt temp_subckt; //from vqm2blif.h - t_model* cur_model; //from physical_types.h boolvec vqm_ports_found; //verification flags indicating that all ports //found in the VQM were mapped. string search; //temporary variable to construct a desired block name within. - cur_model = arch_models; //search for the corresponding model in the list from the architecture. - VTR_ASSERT(cur_model != NULL); - temp_subckt.inst_name = (string)vqm_node->name; //copy the instance name VTR_ASSERT( !temp_subckt.inst_name.empty() ); @@ -987,7 +970,7 @@ void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_sub } else if (elab_mode == MODES || elab_mode == MODES_TIMING){ //search for an Architecture model based on the block name and the parameters - search = generate_opname(vqm_node, arch_models, device); //generate the simple mode-hashed name based on parameters. + search = generate_opname(vqm_node, models, device); //generate the simple mode-hashed name based on parameters. } else { //should never get here, based on condition in init_blif_subckts() @@ -1008,100 +991,100 @@ void push_node_1_to_1 (t_node* vqm_node, t_model* arch_models, scktvec* blif_sub cout << "\n\t\t>> Blackbox Identified." ; cout << "\n\t\t>> Searching Architecture for Model Data \""<< search << "\"" ; } - while ((cur_model)&&(strcmp(cur_model->name, search.c_str()) != 0)){ - cur_model = cur_model->next; - } + LogicalModelId model_id = models.get_model_by_name(search); //cur_model now points to either NULL or the appropriate Architecture model. - if (!cur_model){ + if (!model_id.is_valid()){ //cur_model == NULL if the end of the model list was reached without success. cout << "\n\nERROR: Model name " << search << " was not found in the architecture.\n" ; exit(1); - } else { - if (verbose_mode){ - cout << "\n\t\t>> Model " << search << " identified.\n" ; - } - temp_subckt.model_type = cur_model; //initialize model_type - model_count[cur_model->index]++; //increment the instance count of the model - temp_subckt.input_cnxns.clear(); //reset the input and output maps - temp_subckt.output_cnxns.clear(); - - //map the input ports of the model read from the architecture - //to the corresponding external pin as per the vqm - init_subckt_map( &(temp_subckt.input_cnxns), - temp_subckt.model_type->inputs, - vqm_node, &vqm_ports_found); - //vqm_ports_found entries are set as ports are mapped - - VTR_ASSERT(!temp_subckt.input_cnxns.empty()); //all blocks must have an input - - //now map the output ports - init_subckt_map( &(temp_subckt.output_cnxns), - temp_subckt.model_type->outputs, - vqm_node, &vqm_ports_found); - //vqm_ports_found entries are set as ports are mapped - - VTR_ASSERT(!temp_subckt.output_cnxns.empty()); //all blocks must have an output - - //Pass through parameters - for (int iparam = 0; iparam < vqm_node->number_of_params; ++iparam) { - t_subckt_param_attr param; - t_node_parameter* vqm_param = vqm_node->array_of_params[iparam]; - param.name = vqm_param->name; - - if (vqm_param->type == NODE_PARAMETER_STRING) { - param.value = vqm_param->value.string_value; - } else { - VTR_ASSERT(vqm_param->type == NODE_PARAMETER_INTEGER); - param.value = std::to_string(vqm_param->value.integer_value); - } - temp_subckt.params.push_back(param); + } + + if (verbose_mode){ + cout << "\n\t\t>> Model " << search << " identified.\n" ; + } + temp_subckt.model_type = model_id; //initialize model_type + model_count[model_id]++; //increment the instance count of the model + temp_subckt.input_cnxns.clear(); //reset the input and output maps + temp_subckt.output_cnxns.clear(); + + const t_model& model = models.get_model(model_id); + + //map the input ports of the model read from the architecture + //to the corresponding external pin as per the vqm + init_subckt_map( &(temp_subckt.input_cnxns), + model.inputs, + vqm_node, &vqm_ports_found); + //vqm_ports_found entries are set as ports are mapped + + VTR_ASSERT(!temp_subckt.input_cnxns.empty()); //all blocks must have an input + + //now map the output ports + init_subckt_map( &(temp_subckt.output_cnxns), + model.outputs, + vqm_node, &vqm_ports_found); + //vqm_ports_found entries are set as ports are mapped + + VTR_ASSERT(!temp_subckt.output_cnxns.empty()); //all blocks must have an output + + //Pass through parameters + for (int iparam = 0; iparam < vqm_node->number_of_params; ++iparam) { + t_subckt_param_attr param; + t_node_parameter* vqm_param = vqm_node->array_of_params[iparam]; + param.name = vqm_param->name; + + if (vqm_param->type == NODE_PARAMETER_STRING) { + param.value = vqm_param->value.string_value; + } else { + VTR_ASSERT(vqm_param->type == NODE_PARAMETER_INTEGER); + param.value = std::to_string(vqm_param->value.integer_value); } + temp_subckt.params.push_back(param); + } - //Verify that all ports specified in the VQM node were successfully mapped before - //committing the subcircuit to the BLIF structure. + //Verify that all ports specified in the VQM node were successfully mapped before + //committing the subcircuit to the BLIF structure. + if (verbose_mode){ + cout << "\t\tVQM Port Verification:\n" ; + } + for (int i = 0; i < vqm_node->number_of_ports; i++){ + /* The mapping process maps all ports of the architecture either to the open port or + * a port in the VQM. If a port appeared in the VQM and not in the + * architecture, the association's corresponding entry in vqm_ports_found would + * remain T_FALSE through the mapping process. + */ if (verbose_mode){ - cout << "\t\tVQM Port Verification:\n" ; - } - for (int i = 0; i < vqm_node->number_of_ports; i++){ - /* The mapping process maps all ports of the architecture either to the open port or - * a port in the VQM. If a port appeared in the VQM and not in the - * architecture, the association's corresponding entry in vqm_ports_found would - * remain T_FALSE through the mapping process. - */ - if (verbose_mode){ - //Print whether the port was mapped explicitly - //Prints "Port (port)[index] = [ mapped | unmapped ]" - cout << "\t\t\tPort " << vqm_node->array_of_ports[i]->port_name ; - - if (vqm_node->array_of_ports[i]->port_index >= 0){ - cout << "[" << vqm_node->array_of_ports[i]->port_index << "]" ; - } + //Print whether the port was mapped explicitly + //Prints "Port (port)[index] = [ mapped | unmapped ]" + cout << "\t\t\tPort " << vqm_node->array_of_ports[i]->port_name ; - cout <<"= " << ((vqm_ports_found[i])? "mapped":"unmapped") << endl; + if (vqm_node->array_of_ports[i]->port_index >= 0){ + cout << "[" << vqm_node->array_of_ports[i]->port_index << "]" ; } - if (vqm_ports_found[i] == T_FALSE){ - cout << "\n\nERROR: Port " << vqm_node->array_of_ports[i]->port_name ; - if (vqm_node->array_of_ports[i]->port_index >= 0){ - cout << "[" << vqm_node->array_of_ports[i]->port_index << "]" ; - } - cout << " not found in architecture for " << search << endl ; - exit(1); - } + cout <<"= " << ((vqm_ports_found[i])? "mapped":"unmapped") << endl; } - if (verbose_mode){ - cout << endl ; + + if (vqm_ports_found[i] == T_FALSE){ + cout << "\n\nERROR: Port " << vqm_node->array_of_ports[i]->port_name ; + if (vqm_node->array_of_ports[i]->port_index >= 0){ + cout << "[" << vqm_node->array_of_ports[i]->port_index << "]" ; + } + cout << " not found in architecture for " << search << endl ; + exit(1); } - //push the temp_subckt into the subckt vector - blif_subckts->push_back(temp_subckt); } + if (verbose_mode){ + cout << endl ; + } + //push the temp_subckt into the subckt vector + blif_subckts->push_back(temp_subckt); } //============================================================================================ //============================================================================================ -void push_node_atomize (t_node* /*vqm_node*/, t_model* /*arch_models*/, scktvec* /*blif_subckts*/ /*, FILE* dict*/){ +void push_node_atomize (t_node* /*vqm_node*/, const LogicalModels& /*models*/, scktvec* /*blif_subckts*/ /*, FILE* dict*/){ /* Interprets each VQM block and its parameter set, then expands that block into its smaller * atomic constituents based on a "Dictionary" document. * @@ -1336,7 +1319,7 @@ void dump_blif (char* blif_file, t_blif_model* main_model, t_arch* arch, t_boole blif_out << "\n#MAIN MODEL\n" ; //completely dump the top-level model - dump_main_model(main_model, blif_out, print_unused_subckt_pins_local, eblif_format, T_FALSE); + dump_main_model(main_model, blif_out, arch->models, print_unused_subckt_pins_local, eblif_format, T_FALSE); //now dump the subckt models from the architecture //that were used in the vqm @@ -1352,7 +1335,7 @@ void dump_blif (char* blif_file, t_blif_model* main_model, t_arch* arch, t_boole //============================================================================================ //============================================================================================ -void dump_main_model(t_blif_model* model, ofstream& outfile, t_boolean print_unused_subckt_pins_local, t_boolean eblif_format_local, t_boolean debug){ +void dump_main_model(t_blif_model* model, ofstream& outfile, const LogicalModels& models, t_boolean print_unused_subckt_pins_local, t_boolean eblif_format_local, t_boolean debug){ /* Dumps information stored in a model structure in proper BLIF syntax. * * ARGUMENTS @@ -1408,7 +1391,7 @@ void dump_main_model(t_blif_model* model, ofstream& outfile, t_boolean print_unu //Print Subcircuit Variable information if (model->subckts.size() > 0){ - dump_subckts(outfile, &(model->subckts), print_unused_subckt_pins_local, eblif_format_local, debug); + dump_subckts(outfile, &(model->subckts), models, print_unused_subckt_pins_local, eblif_format_local, debug); } //Printing the model data is complete. @@ -1718,7 +1701,7 @@ void dump_luts (ofstream& outfile, lutvec* blif_luts, t_boolean eblif_format_loc //============================================================================================ //============================================================================================ -void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pins, t_boolean eblif_format_local, t_boolean debug){ +void dump_subckts(ofstream& outfile, scktvec* subckts, const LogicalModels& models, t_boolean print_unused_pins, t_boolean eblif_format_local, t_boolean debug){ /* Traverse the subcircuit vector, printing the names and connections * of each instantiated subcircuit in the main model. * @@ -1738,15 +1721,16 @@ void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pi for(int i = 0; i < limit; i++){ //print each subcircuit's name, port, and connectivity information temp_subckt = &(subckts->at(i)); + const t_model& model_type = models.get_model(temp_subckt->model_type); if (debug){ outfile << "\nSubcircuit Number: " << i << endl; outfile << "Instance Name: " << temp_subckt->inst_name << endl; - outfile << "Type: " << temp_subckt->model_type->name << endl ; + outfile << "Type: " << model_type.name << endl ; } else { if (!eblif_format_local) { outfile << "\n# Subckt " << i << ": " << temp_subckt->inst_name << " \n"; } - outfile << ".subckt " << temp_subckt->model_type->name << " \\\n" ; + outfile << ".subckt " << model_type.name << " \\\n" ; } @@ -1754,13 +1738,13 @@ void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pi outfile << "Input Map:\n" ; } - size_t num_print_output_pins = count_print_pins(temp_subckt->model_type->outputs, &(temp_subckt->output_cnxns), print_unused_pins); + size_t num_print_output_pins = count_print_pins(model_type.outputs, &(temp_subckt->output_cnxns), print_unused_pins); //dump the input map containing connectivity data bool last = (num_print_output_pins == 0); dump_subckt_map(outfile, &(temp_subckt->input_cnxns), - temp_subckt->model_type->inputs, + model_type.inputs, temp_subckt->inst_name.c_str(), "input", i, print_unused_pins, @@ -1775,7 +1759,7 @@ void dump_subckts(ofstream& outfile, scktvec* subckts, t_boolean print_unused_pi last = true; dump_subckt_map(outfile, &(temp_subckt->output_cnxns), - temp_subckt->model_type->outputs, + model_type.outputs, temp_subckt->inst_name.c_str(), "output", i, print_unused_pins, @@ -1925,7 +1909,7 @@ size_t count_print_pins(t_model_ports* temp_port, portmap* map, t_boolean print_ //============================================================================================ //============================================================================================ -void dump_subckt_models(t_model* temp_model, ofstream& outfile, t_boolean debug){ +void dump_subckt_models(const LogicalModels& models, ofstream& outfile, t_boolean debug){ /* Cycles through all models declared in the architecture * and dumps the ones used by the VQM as blackbox models * at the end of the .blif file @@ -1938,27 +1922,29 @@ void dump_subckt_models(t_model* temp_model, ofstream& outfile, t_boolean debug) * flag to indicate whether to print in DEBUG or BLIF format. */ unsigned long total_block_count = 0; - while(temp_model){ - if (model_count[temp_model->index] > 0){ - //Count the number of blocks - total_block_count += model_count[temp_model->index]; - - //dump all .subckt models declared in the architecture - //Use the model_count array to only output the models that were used. - if (!debug){ - cout << "\t>> Introduced " << model_count[temp_model->index] << " instances of blackbox " << temp_model->name << endl; - } - outfile << ((debug)? "\n Model: " : "\n.model ") << temp_model->name << endl ; - - outfile << ((debug)? "Inputs:\n" : ".inputs \\\n") ; //cycle through all inputs - dump_subckt_portlist(outfile, temp_model->inputs, " ", debug); + for (LogicalModelId model_id : models.user_models()) { + if (model_count[model_id] == 0) + continue; + + //Count the number of blocks + total_block_count += model_count[model_id]; + + const t_model& model = models.get_model(model_id); - outfile << ((debug)? "Outputs:\n" : ".outputs \\\n") ; //cycle through all outputs - dump_subckt_portlist(outfile, temp_model->outputs, " ", debug); + //dump all .subckt models declared in the architecture + //Use the model_count array to only output the models that were used. + if (!debug){ + cout << "\t>> Introduced " << model_count[model_id] << " instances of blackbox " << model.name << endl; + } + outfile << ((debug)? "\n Model: " : "\n.model ") << model.name << endl ; + + outfile << ((debug)? "Inputs:\n" : ".inputs \\\n") ; //cycle through all inputs + dump_subckt_portlist(outfile, model.inputs, " ", debug); + + outfile << ((debug)? "Outputs:\n" : ".outputs \\\n") ; //cycle through all outputs + dump_subckt_portlist(outfile, model.outputs, " ", debug); - outfile << ((debug)? "\nEND MODEL\n" : ".blackbox\n.end\n") ; - } - temp_model = temp_model->next; + outfile << ((debug)? "\nEND MODEL\n" : ".blackbox\n.end\n") ; } cout << "\t>> Total Block Count: " << total_block_count; } @@ -2013,8 +1999,8 @@ void all_data_cleanup(){ */ vqm_data_cleanup();//found in ../LIB/vqm_dll.h, frees parser-allocated memory - free(model_count); - + model_count.clear(); + return; } @@ -2253,7 +2239,7 @@ void echo_module_nodes (ofstream& outfile, t_module* module){ //============================================================================================ void echo_blif_model (char* echo_file, const char* vqm_filename, - t_blif_model* my_model, t_model* temp_model) { + t_blif_model* my_model, const LogicalModels& models) { /* Prints all model data into a .txt for debugging * Used to ensure correct population of the parser data into the model. * @@ -2278,14 +2264,14 @@ void echo_blif_model (char* echo_file, const char* vqm_filename, model_out << "\n\tMAIN MODEL\n" ; //completely dump the top-level model in DEBUG format - dump_main_model(my_model, model_out, T_TRUE, T_TRUE, T_TRUE); + dump_main_model(my_model, model_out, models, T_TRUE, T_TRUE, T_TRUE); model_out << "\n\tSUBCKT MODELS\n"; //now dump the subckt models from the architecture //that were used in the VQM file, in DEBUG format. if (my_model->subckts.size() > 0){ - dump_subckt_models(temp_model, model_out, T_TRUE); + dump_subckt_models(models, model_out, T_TRUE); } // Close file. diff --git a/utils/vqm2blif/test/netlists/carpat/carpat_stratixiv_arch_timing.blif b/utils/vqm2blif/test/netlists/carpat/carpat_stratixiv_arch_timing.blif index 90a7e92bcfa..190d8cf395b 100644 --- a/utils/vqm2blif/test/netlists/carpat/carpat_stratixiv_arch_timing.blif +++ b/utils/vqm2blif/test/netlists/carpat/carpat_stratixiv_arch_timing.blif @@ -1,4 +1,4 @@ -#BLIF OUTPUT: titan_release_dev/benchmarks/other_benchmarks/carpat/netlists/carpat_stratixiv_arch_timing.blif +#BLIF OUTPUT: ./utils/vqm2blif/test/scripts/../netlists/carpat/carpat_stratixiv.golden.blif #MAIN MODEL @@ -264730,87 +264730,497 @@ #SUBCKT MODELS -.model stratixiv_pll.opmode{normal} +.model stratixiv_lcell_comb .inputs \ - scandata \ - scanclkena \ - scanclk \ - phaseupdown \ - phasestep \ - phasecounterselect[0] \ - phasecounterselect[1] \ - phasecounterselect[2] \ - phasecounterselect[3] \ - pfdena \ - inclk \ - fbin \ - configupdate \ - clkswitch \ - areset + sharein \ + cin \ + datag \ + dataf \ + datae \ + datad \ + datac \ + datab \ + dataa .outputs \ - vcounderrange \ - vcooverrange \ - scandone \ - scandataout \ - phasedone \ - locked \ - fbout \ - clkbad[0] \ - clkbad[1] \ - clk[0] \ - clk[1] \ - clk[2] \ - clk[3] \ - clk[4] \ - clk[5] \ - clk[6] \ - clk[7] \ - clk[8] \ - clk[9] \ - activeclock + shareout \ + cout \ + sumout \ + combout .blackbox .end -.model stratixiv_io_obuf +.model dffeas .inputs \ - parallelterminationcontrol[0] \ - parallelterminationcontrol[1] \ - parallelterminationcontrol[2] \ - parallelterminationcontrol[3] \ - parallelterminationcontrol[4] \ - parallelterminationcontrol[5] \ - parallelterminationcontrol[6] \ - parallelterminationcontrol[7] \ - parallelterminationcontrol[8] \ - parallelterminationcontrol[9] \ - parallelterminationcontrol[10] \ - parallelterminationcontrol[11] \ - parallelterminationcontrol[12] \ - parallelterminationcontrol[13] \ - seriesterminationcontrol[0] \ - seriesterminationcontrol[1] \ - seriesterminationcontrol[2] \ - seriesterminationcontrol[3] \ - seriesterminationcontrol[4] \ - seriesterminationcontrol[5] \ - seriesterminationcontrol[6] \ - seriesterminationcontrol[7] \ - seriesterminationcontrol[8] \ - seriesterminationcontrol[9] \ - seriesterminationcontrol[10] \ - seriesterminationcontrol[11] \ - seriesterminationcontrol[12] \ - seriesterminationcontrol[13] \ - dynamicterminationcontrol \ - oe \ - i + devpor \ + devclrn \ + d \ + sclr \ + sload \ + aload \ + asdata \ + clrn \ + prn \ + ena \ + clk .outputs \ - obar \ - o + q .blackbox .end -.model stratixiv_mac_out.opmode{double}.input_type{reg}.output_type{comb} +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddr[3] \ + portbaddr[4] \ + portbaddr[5] \ + portbaddr[6] \ + portbaddr[7] \ + portbaddr[8] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddr[6] \ + portaaddr[7] \ + portaaddr[8] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddr[3] \ + portbaddr[4] \ + portbaddr[5] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddr[3] \ + portbaddr[4] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddr[3] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddr[2] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2} +.inputs \ + portbaddr[0] \ + portbaddr[1] \ + portbaddrstall \ + portawe \ + clk_portbout \ + portbre \ + portaaddr[0] \ + portaaddr[1] \ + portaaddrstall \ + clk_portaout \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + clk_portain \ + portabyteenamasks[0] \ + portabyteenamasks[1] \ + portabyteenamasks[2] \ + portabyteenamasks[3] \ + portabyteenamasks[4] \ + portabyteenamasks[5] \ + portabyteenamasks[6] \ + portabyteenamasks[7] \ + clk_portbin \ + clr0 \ + clr1 \ + portadatain +.outputs \ + eccstatus[0] \ + eccstatus[1] \ + eccstatus[2] \ + portbdataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{10} +.inputs \ + clk_portaout \ + clk_portain \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddr[6] \ + portaaddr[7] \ + portaaddr[8] \ + portaaddr[9] \ + portaaddrstall \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + portare \ + clr0 \ + clr1 +.outputs \ + portadataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{9} +.inputs \ + clk_portaout \ + clk_portain \ + portaaddr[0] \ + portaaddr[1] \ + portaaddr[2] \ + portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddr[6] \ + portaaddr[7] \ + portaaddr[8] \ + portaaddrstall \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + portare \ + clr0 \ + clr1 +.outputs \ + portadataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{1} +.inputs \ + clk_portaout \ + clk_portain \ + portaaddr \ + portaaddrstall \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + portare \ + clr0 \ + clr1 +.outputs \ + portadataout +.blackbox +.end + +.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{0} +.inputs \ + clk_portaout \ + clk_portain \ + portaaddr \ + portaaddrstall \ + ena1 \ + ena0 \ + ena3 \ + ena2 \ + portare \ + clr0 \ + clr1 +.outputs \ + portadataout +.blackbox +.end + +.model stratixiv_mac_mult.input_type{comb} +.inputs \ + devpor \ + devclrn \ + aclr[0] \ + aclr[1] \ + aclr[2] \ + aclr[3] \ + ena[0] \ + ena[1] \ + ena[2] \ + ena[3] \ + signb \ + signa \ + datab[0] \ + datab[1] \ + datab[2] \ + datab[3] \ + datab[4] \ + datab[5] \ + datab[6] \ + datab[7] \ + datab[8] \ + datab[9] \ + datab[10] \ + datab[11] \ + datab[12] \ + datab[13] \ + datab[14] \ + datab[15] \ + datab[16] \ + datab[17] \ + dataa[0] \ + dataa[1] \ + dataa[2] \ + dataa[3] \ + dataa[4] \ + dataa[5] \ + dataa[6] \ + dataa[7] \ + dataa[8] \ + dataa[9] \ + dataa[10] \ + dataa[11] \ + dataa[12] \ + dataa[13] \ + dataa[14] \ + dataa[15] \ + dataa[16] \ + dataa[17] +.outputs \ + dataout[0] \ + dataout[1] \ + dataout[2] \ + dataout[3] \ + dataout[4] \ + dataout[5] \ + dataout[6] \ + dataout[7] \ + dataout[8] \ + dataout[9] \ + dataout[10] \ + dataout[11] \ + dataout[12] \ + dataout[13] \ + dataout[14] \ + dataout[15] \ + dataout[16] \ + dataout[17] \ + dataout[18] \ + dataout[19] \ + dataout[20] \ + dataout[21] \ + dataout[22] \ + dataout[23] \ + dataout[24] \ + dataout[25] \ + dataout[26] \ + dataout[27] \ + dataout[28] \ + dataout[29] \ + dataout[30] \ + dataout[31] \ + dataout[32] \ + dataout[33] \ + dataout[34] \ + dataout[35] \ + scanouta[0] \ + scanouta[1] \ + scanouta[2] \ + scanouta[3] \ + scanouta[4] \ + scanouta[5] \ + scanouta[6] \ + scanouta[7] \ + scanouta[8] \ + scanouta[9] \ + scanouta[10] \ + scanouta[11] \ + scanouta[12] \ + scanouta[13] \ + scanouta[14] \ + scanouta[15] \ + scanouta[16] \ + scanouta[17] +.blackbox +.end + +.model stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{comb} .inputs \ devpor \ devclrn \ @@ -264818,7 +265228,6 @@ aclr[1] \ aclr[2] \ aclr[3] \ - clk \ ena[0] \ ena[1] \ ena[2] \ @@ -265025,11 +265434,28 @@ dataout[51] \ dataout[52] \ dataout[53] \ - dataout[54] + dataout[54] \ + dataout[55] \ + dataout[56] \ + dataout[57] \ + dataout[58] \ + dataout[59] \ + dataout[60] \ + dataout[61] \ + dataout[62] \ + dataout[63] \ + dataout[64] \ + dataout[65] \ + dataout[66] \ + dataout[67] \ + dataout[68] \ + dataout[69] \ + dataout[70] \ + dataout[71] .blackbox .end -.model stratixiv_mac_out.opmode{double}.input_type{comb}.output_type{comb} +.model stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{reg} .inputs \ devpor \ devclrn \ @@ -265037,6 +265463,7 @@ aclr[1] \ aclr[2] \ aclr[3] \ + clk \ ena[0] \ ena[1] \ ena[2] \ @@ -265243,11 +265670,28 @@ dataout[51] \ dataout[52] \ dataout[53] \ - dataout[54] + dataout[54] \ + dataout[55] \ + dataout[56] \ + dataout[57] \ + dataout[58] \ + dataout[59] \ + dataout[60] \ + dataout[61] \ + dataout[62] \ + dataout[63] \ + dataout[64] \ + dataout[65] \ + dataout[66] \ + dataout[67] \ + dataout[68] \ + dataout[69] \ + dataout[70] \ + dataout[71] .blackbox .end -.model stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{reg} +.model stratixiv_mac_out.opmode{double}.input_type{comb}.output_type{comb} .inputs \ devpor \ devclrn \ @@ -265255,7 +265699,6 @@ aclr[1] \ aclr[2] \ aclr[3] \ - clk \ ena[0] \ ena[1] \ ena[2] \ @@ -265462,28 +265905,11 @@ dataout[51] \ dataout[52] \ dataout[53] \ - dataout[54] \ - dataout[55] \ - dataout[56] \ - dataout[57] \ - dataout[58] \ - dataout[59] \ - dataout[60] \ - dataout[61] \ - dataout[62] \ - dataout[63] \ - dataout[64] \ - dataout[65] \ - dataout[66] \ - dataout[67] \ - dataout[68] \ - dataout[69] \ - dataout[70] \ - dataout[71] + dataout[54] .blackbox .end -.model stratixiv_mac_out.opmode{36_bit_multiply}.input_type{comb}.output_type{comb} +.model stratixiv_mac_out.opmode{double}.input_type{reg}.output_type{comb} .inputs \ devpor \ devclrn \ @@ -265491,6 +265917,7 @@ aclr[1] \ aclr[2] \ aclr[3] \ + clk \ ena[0] \ ena[1] \ ena[2] \ @@ -265697,513 +266124,86 @@ dataout[51] \ dataout[52] \ dataout[53] \ - dataout[54] \ - dataout[55] \ - dataout[56] \ - dataout[57] \ - dataout[58] \ - dataout[59] \ - dataout[60] \ - dataout[61] \ - dataout[62] \ - dataout[63] \ - dataout[64] \ - dataout[65] \ - dataout[66] \ - dataout[67] \ - dataout[68] \ - dataout[69] \ - dataout[70] \ - dataout[71] -.blackbox -.end - -.model stratixiv_mac_mult.input_type{comb} -.inputs \ - devpor \ - devclrn \ - aclr[0] \ - aclr[1] \ - aclr[2] \ - aclr[3] \ - ena[0] \ - ena[1] \ - ena[2] \ - ena[3] \ - signb \ - signa \ - datab[0] \ - datab[1] \ - datab[2] \ - datab[3] \ - datab[4] \ - datab[5] \ - datab[6] \ - datab[7] \ - datab[8] \ - datab[9] \ - datab[10] \ - datab[11] \ - datab[12] \ - datab[13] \ - datab[14] \ - datab[15] \ - datab[16] \ - datab[17] \ - dataa[0] \ - dataa[1] \ - dataa[2] \ - dataa[3] \ - dataa[4] \ - dataa[5] \ - dataa[6] \ - dataa[7] \ - dataa[8] \ - dataa[9] \ - dataa[10] \ - dataa[11] \ - dataa[12] \ - dataa[13] \ - dataa[14] \ - dataa[15] \ - dataa[16] \ - dataa[17] -.outputs \ - dataout[0] \ - dataout[1] \ - dataout[2] \ - dataout[3] \ - dataout[4] \ - dataout[5] \ - dataout[6] \ - dataout[7] \ - dataout[8] \ - dataout[9] \ - dataout[10] \ - dataout[11] \ - dataout[12] \ - dataout[13] \ - dataout[14] \ - dataout[15] \ - dataout[16] \ - dataout[17] \ - dataout[18] \ - dataout[19] \ - dataout[20] \ - dataout[21] \ - dataout[22] \ - dataout[23] \ - dataout[24] \ - dataout[25] \ - dataout[26] \ - dataout[27] \ - dataout[28] \ - dataout[29] \ - dataout[30] \ - dataout[31] \ - dataout[32] \ - dataout[33] \ - dataout[34] \ - dataout[35] \ - scanouta[0] \ - scanouta[1] \ - scanouta[2] \ - scanouta[3] \ - scanouta[4] \ - scanouta[5] \ - scanouta[6] \ - scanouta[7] \ - scanouta[8] \ - scanouta[9] \ - scanouta[10] \ - scanouta[11] \ - scanouta[12] \ - scanouta[13] \ - scanouta[14] \ - scanouta[15] \ - scanouta[16] \ - scanouta[17] -.blackbox -.end - -.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{0} -.inputs \ - clk_portaout \ - clk_portain \ - portaaddr \ - portaaddrstall \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - portare \ - clr0 \ - clr1 -.outputs \ - portadataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{1} -.inputs \ - clk_portaout \ - clk_portain \ - portaaddr \ - portaaddrstall \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - portare \ - clr0 \ - clr1 -.outputs \ - portadataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{9} -.inputs \ - clk_portaout \ - clk_portain \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddr[6] \ - portaaddr[7] \ - portaaddr[8] \ - portaaddrstall \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - portare \ - clr0 \ - clr1 -.outputs \ - portadataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{rom}.output_type{reg}.port_a_address_width{10} -.inputs \ - clk_portaout \ - clk_portain \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddr[6] \ - portaaddr[7] \ - portaaddr[8] \ - portaaddr[9] \ - portaaddrstall \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - portare \ - clr0 \ - clr1 -.outputs \ - portadataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{2}.port_b_address_width{2} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{3}.port_b_address_width{3} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{4}.port_b_address_width{4} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddr[3] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{5}.port_b_address_width{5} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddr[3] \ - portbaddr[4] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{6}.port_b_address_width{6} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddr[3] \ - portbaddr[4] \ - portbaddr[5] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout -.blackbox -.end - -.model stratixiv_ram_block.opmode{dual_port}.output_type{reg}.port_a_address_width{9}.port_b_address_width{9} -.inputs \ - portbaddr[0] \ - portbaddr[1] \ - portbaddr[2] \ - portbaddr[3] \ - portbaddr[4] \ - portbaddr[5] \ - portbaddr[6] \ - portbaddr[7] \ - portbaddr[8] \ - portbaddrstall \ - portawe \ - clk_portbout \ - portbre \ - portaaddr[0] \ - portaaddr[1] \ - portaaddr[2] \ - portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddr[6] \ - portaaddr[7] \ - portaaddr[8] \ - portaaddrstall \ - clk_portaout \ - ena1 \ - ena0 \ - ena3 \ - ena2 \ - clk_portain \ - portabyteenamasks[0] \ - portabyteenamasks[1] \ - portabyteenamasks[2] \ - portabyteenamasks[3] \ - portabyteenamasks[4] \ - portabyteenamasks[5] \ - portabyteenamasks[6] \ - portabyteenamasks[7] \ - clk_portbin \ - clr0 \ - clr1 \ - portadatain -.outputs \ - eccstatus[0] \ - eccstatus[1] \ - eccstatus[2] \ - portbdataout + dataout[54] .blackbox .end -.model dffeas +.model stratixiv_io_obuf .inputs \ - devpor \ - devclrn \ - d \ - sclr \ - sload \ - aload \ - asdata \ - clrn \ - prn \ - ena \ - clk + parallelterminationcontrol[0] \ + parallelterminationcontrol[1] \ + parallelterminationcontrol[2] \ + parallelterminationcontrol[3] \ + parallelterminationcontrol[4] \ + parallelterminationcontrol[5] \ + parallelterminationcontrol[6] \ + parallelterminationcontrol[7] \ + parallelterminationcontrol[8] \ + parallelterminationcontrol[9] \ + parallelterminationcontrol[10] \ + parallelterminationcontrol[11] \ + parallelterminationcontrol[12] \ + parallelterminationcontrol[13] \ + seriesterminationcontrol[0] \ + seriesterminationcontrol[1] \ + seriesterminationcontrol[2] \ + seriesterminationcontrol[3] \ + seriesterminationcontrol[4] \ + seriesterminationcontrol[5] \ + seriesterminationcontrol[6] \ + seriesterminationcontrol[7] \ + seriesterminationcontrol[8] \ + seriesterminationcontrol[9] \ + seriesterminationcontrol[10] \ + seriesterminationcontrol[11] \ + seriesterminationcontrol[12] \ + seriesterminationcontrol[13] \ + dynamicterminationcontrol \ + oe \ + i .outputs \ - q + obar \ + o .blackbox .end -.model stratixiv_lcell_comb +.model stratixiv_pll.opmode{normal} .inputs \ - sharein \ - cin \ - datag \ - dataf \ - datae \ - datad \ - datac \ - datab \ - dataa + scandata \ + scanclkena \ + scanclk \ + phaseupdown \ + phasestep \ + phasecounterselect[0] \ + phasecounterselect[1] \ + phasecounterselect[2] \ + phasecounterselect[3] \ + pfdena \ + inclk \ + fbin \ + configupdate \ + clkswitch \ + areset .outputs \ - shareout \ - cout \ - sumout \ - combout + vcounderrange \ + vcooverrange \ + scandone \ + scandataout \ + phasedone \ + locked \ + fbout \ + clkbad[0] \ + clkbad[1] \ + clk[0] \ + clk[1] \ + clk[2] \ + clk[3] \ + clk[4] \ + clk[5] \ + clk[6] \ + clk[7] \ + clk[8] \ + clk[9] \ + activeclock .blackbox .end diff --git a/utils/vqm2blif/test/netlists/murax/murax_stratixiv_arch_timing.blif b/utils/vqm2blif/test/netlists/murax/murax_stratixiv_arch_timing.blif index 8ae3d5e3def..5d4fad42dde 100644 --- a/utils/vqm2blif/test/netlists/murax/murax_stratixiv_arch_timing.blif +++ b/utils/vqm2blif/test/netlists/murax/murax_stratixiv_arch_timing.blif @@ -1,4 +1,4 @@ -#BLIF OUTPUT: titan_release_dev/benchmarks/other_benchmarks/murax/netlists/murax_stratixiv_arch_timing.blif +#BLIF OUTPUT: ./utils/vqm2blif/test/scripts/../netlists/murax/murax_stratixiv.golden.blif #MAIN MODEL @@ -18187,12 +18187,55 @@ #SUBCKT MODELS -.model stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4} +.model stratixiv_lcell_comb +.inputs \ + sharein \ + cin \ + datag \ + dataf \ + datae \ + datad \ + datac \ + datab \ + dataa +.outputs \ + shareout \ + cout \ + sumout \ + combout +.blackbox +.end + +.model dffeas +.inputs \ + devpor \ + devclrn \ + d \ + sclr \ + sload \ + aload \ + asdata \ + clrn \ + prn \ + ena \ + clk +.outputs \ + q +.blackbox +.end + +.model stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10} .inputs \ portbaddr[0] \ portbaddr[1] \ portbaddr[2] \ portbaddr[3] \ + portbaddr[4] \ + portbaddr[5] \ + portbaddr[6] \ + portbaddr[7] \ + portbaddr[8] \ + portbaddr[9] \ portbaddrstall \ portawe \ clk_portbout \ @@ -18201,6 +18244,12 @@ portaaddr[1] \ portaaddr[2] \ portaaddr[3] \ + portaaddr[4] \ + portaaddr[5] \ + portaaddr[6] \ + portaaddr[7] \ + portaaddr[8] \ + portaaddr[9] \ portaaddrstall \ clk_portaout \ ena1 \ @@ -18271,18 +18320,12 @@ .blackbox .end -.model stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{10}.port_b_address_width{10} +.model stratixiv_ram_block.opmode{dual_port}.output_type{comb}.port_a_address_width{4}.port_b_address_width{4} .inputs \ portbaddr[0] \ portbaddr[1] \ portbaddr[2] \ portbaddr[3] \ - portbaddr[4] \ - portbaddr[5] \ - portbaddr[6] \ - portbaddr[7] \ - portbaddr[8] \ - portbaddr[9] \ portbaddrstall \ portawe \ clk_portbout \ @@ -18291,12 +18334,6 @@ portaaddr[1] \ portaaddr[2] \ portaaddr[3] \ - portaaddr[4] \ - portaaddr[5] \ - portaaddr[6] \ - portaaddr[7] \ - portaaddr[8] \ - portaaddr[9] \ portaaddrstall \ clk_portaout \ ena1 \ @@ -18323,40 +18360,3 @@ portbdataout .blackbox .end - -.model dffeas -.inputs \ - devpor \ - devclrn \ - d \ - sclr \ - sload \ - aload \ - asdata \ - clrn \ - prn \ - ena \ - clk -.outputs \ - q -.blackbox -.end - -.model stratixiv_lcell_comb -.inputs \ - sharein \ - cin \ - datag \ - dataf \ - datae \ - datad \ - datac \ - datab \ - dataa -.outputs \ - shareout \ - cout \ - sumout \ - combout -.blackbox -.end diff --git a/utils/vqm2blif/test/netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv_arch_timing.blif b/utils/vqm2blif/test/netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv_arch_timing.blif index a7ed3f84596..cab3e1222dc 100644 --- a/utils/vqm2blif/test/netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv_arch_timing.blif +++ b/utils/vqm2blif/test/netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv_arch_timing.blif @@ -1,4 +1,4 @@ -#BLIF OUTPUT: titan_release_dev/benchmarks/other_benchmarks/ucsb_152_tap_fir/netlists/ucsb_152_tap_fir_stratixiv_arch_timing.blif +#BLIF OUTPUT: ./utils/vqm2blif/test/scripts/../netlists/ucsb_152_tap_fir/ucsb_152_tap_fir_stratixiv.golden.blif #MAIN MODEL @@ -132420,24 +132420,6 @@ #SUBCKT MODELS -.model dffeas -.inputs \ - devpor \ - devclrn \ - d \ - sclr \ - sload \ - aload \ - asdata \ - clrn \ - prn \ - ena \ - clk -.outputs \ - q -.blackbox -.end - .model stratixiv_lcell_comb .inputs \ sharein \ @@ -132456,3 +132438,21 @@ combout .blackbox .end + +.model dffeas +.inputs \ + devpor \ + devclrn \ + d \ + sclr \ + sload \ + aload \ + asdata \ + clrn \ + prn \ + ena \ + clk +.outputs \ + q +.blackbox +.end diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt index 4e3ccc0b12c..530928ac612 100644 --- a/vpr/CMakeLists.txt +++ b/vpr/CMakeLists.txt @@ -12,6 +12,8 @@ set_property(CACHE VPR_PGO_CONFIG PROPERTY STRINGS prof_gen prof_use none) set(VPR_PGO_DATA_DIR "." CACHE PATH "Where to store and retrieve PGO data") +set(VPR_ENABLE_OPEN_MP "on" CACHE STRING "Enable OpenMP when compiling VPR") + #Handle graphics setup set(GRAPHICS_DEFINES "") @@ -89,21 +91,6 @@ else () message(STATUS "Eigen3: Not Found. Some features may be disabled.") endif (TARGET Eigen3::Eigen) -#VPR_ANALYTIC_PLACE is initialized in the root CMakeLists -# NOTE: This is the cluster-level Analytical Placement which existed before the -# flat Analytical Placement flow. -if(${VPR_ANALYTIC_PLACE}) - message(STATUS "VPR Analytic Placement: Requested") - if (TARGET Eigen3::Eigen) - message(STATUS "VPR Analytic Placement dependency (Eigen3): Found") - message(STATUS "VPR Analytic Placement: Enabled") - target_compile_definitions(libvpr PUBLIC -DENABLE_ANALYTIC_PLACE) - else () - message(STATUS "VPR Analytic Placement dependency (Eigen3): Not Found (Download manually with sudo apt install libeigen3-dev, and rebuild)") - message(STATUS "VPR Analytic Placement: Disabled") - endif(TARGET Eigen3::Eigen) -endif() - if (${VPR_ENABLE_NOC_SAT_ROUTING}) message(STATUS "VPR NoC SAT Routing: Requested") find_package(ortools CONFIG REQUIRED) @@ -295,6 +282,21 @@ else() message(FATAL_ERROR "VPR: Unrecognized execution engine '${VPR_USE_EXECUTION_ENGINE}'") endif() +# +# OpenMP configuration +# +if (VPR_ENABLE_OPEN_MP STREQUAL "on") + find_package(OpenMP) + if (OpenMP_CXX_FOUND) + target_link_libraries(libvpr OpenMP::OpenMP_CXX) + message(STATUS "OpenMP: Enabled") + else() + message(STATUS "OpenMP: Disabled (requested but not found)") + endif() +else() + message(STATUS "OpenMP: Disabled") +endif() + # # Signal handler configuration # diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 542269395c5..eeffe27e01a 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -1,9 +1,14 @@ #include "timing_reports.h" -#include "vtr_log.h" +#include +#include + +#include "timing_reports.h" +#include "rr_graph.h" #include "tatum/TimingReporter.hpp" +#include "vtr_version.h" #include "vpr_types.h" #include "globals.h" @@ -12,6 +17,117 @@ #include "VprTimingGraphResolver.h" +/** + * @brief Get the bounding box of a routed net. + * If the net is completely absorbed into a cluster block, return the bounding box of the cluster block. + * Otherwise, return the bounding box of the net's route tree. + * + * @param atom_net_id The id of the atom net to get the bounding box of. + * + * @return The bounding box of the net. If the net is not routed, a bounding box + * is returned with default values (OPEN). + */ +static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { + const auto& route_trees = g_vpr_ctx.routing().route_trees; + const auto& rr_graph = g_vpr_ctx.device().rr_graph; + + // Lambda to get the bounding box of a route tree + auto route_tree_bb = [&](const RouteTree& route_tree) { + t_bb bb; + + // Set the initial bounding box to the root node's location + RRNodeId route_tree_root = route_tree.root().inode; + bb.xmin = rr_graph.node_xlow(route_tree_root); + bb.xmax = rr_graph.node_xhigh(route_tree_root); + bb.ymin = rr_graph.node_ylow(route_tree_root); + bb.ymax = rr_graph.node_yhigh(route_tree_root); + bb.layer_min = rr_graph.node_layer(route_tree_root); + bb.layer_max = rr_graph.node_layer(route_tree_root); + + // Iterate over all nodes in the route tree and update the bounding box + for (auto& rt_node : route_tree.all_nodes()) { + RRNodeId inode = rt_node.inode; + + bb.xmin = std::min(static_cast(rr_graph.node_xlow(inode)), bb.xmin); + bb.xmax = std::max(static_cast(rr_graph.node_xhigh(inode)), bb.xmax); + + bb.ymin = std::min(static_cast(rr_graph.node_ylow(inode)), bb.ymin); + bb.ymax = std::max(static_cast(rr_graph.node_yhigh(inode)), bb.ymax); + + bb.layer_min = std::min(static_cast(rr_graph.node_layer(inode)), bb.layer_min); + bb.layer_max = std::max(static_cast(rr_graph.node_layer(inode)), bb.layer_max); + } + return bb; + }; + + if (g_vpr_ctx.routing().is_flat) { + // If flat router is used, route tree data structure can be used + // directly to get the bounding box of the net + const auto& route_tree = route_trees[atom_net_id]; + if (!route_tree) + return t_bb(); + return route_tree_bb(*route_tree); + } else { + // If two-stage router is used, we need to first get the cluster net id + // corresponding to the atom net and then get the bounding box of the net + // from the route tree. If the net is completely absorbed into a cluster block, + const auto& atom_lookup = g_vpr_ctx.atom().lookup(); + const auto& cluster_net_id = atom_lookup.clb_nets(atom_net_id); + std::vector bbs; + t_bb max_bb; + // There maybe multiple cluster nets corresponding to a single atom net. + // We iterate over all cluster nets and the final bounding box is the union + // of all cluster net bounding boxes + if (cluster_net_id != vtr::nullopt) { + for (const auto& clb_net_id : *cluster_net_id) { + const auto& route_tree = route_trees[clb_net_id]; + if (!route_tree) + continue; + bbs.push_back(route_tree_bb(*route_tree)); + } + if (bbs.empty()) { + return t_bb(); + } + // Assign the first cluster net's bounding box to the final bounding box + // and then iteratively update it with the union of bounding boxes of + // all cluster nets + max_bb = bbs[0]; + for (size_t i = 1; i < bbs.size(); ++i) { + max_bb.xmin = std::min(bbs[i].xmin, max_bb.xmin); + max_bb.xmax = std::max(bbs[i].xmax, max_bb.xmax); + max_bb.ymin = std::min(bbs[i].ymin, max_bb.ymin); + max_bb.ymax = std::max(bbs[i].ymax, max_bb.ymax); + max_bb.layer_min = std::min(bbs[i].layer_min, max_bb.layer_min); + max_bb.layer_max = std::max(bbs[i].layer_max, max_bb.layer_max); + } + return max_bb; + } else { + // If there is no cluster net corresponding to the atom net, + // it means the net is completely absorbed into a cluster block. + // In that case, we set the bounding box the cluster block's bounding box + const auto& atom_ctx = g_vpr_ctx.atom(); + const auto& atom_nlist = atom_ctx.netlist(); + AtomPinId source_pin = atom_nlist.net_driver(atom_net_id); + + AtomBlockId atom_block = atom_nlist.pin_block(source_pin); + VTR_ASSERT(atom_block != AtomBlockId::INVALID()); + ClusterBlockId cluster_block = atom_lookup.atom_clb(atom_block); + VTR_ASSERT(cluster_block != ClusterBlockId::INVALID()); + + const t_pl_loc& cluster_block_loc = g_vpr_ctx.placement().block_locs()[cluster_block].loc; + const auto& grid = g_vpr_ctx.device().grid; + vtr::Rect tile_bb = grid.get_tile_bb({cluster_block_loc.x, cluster_block_loc.y, cluster_block_loc.layer}); + const int block_layer = cluster_block_loc.layer; + return t_bb(tile_bb.xmin(), + tile_bb.xmax(), + tile_bb.ymin(), + tile_bb.ymax(), + block_layer, + block_layer); + } + } +} + void generate_setup_timing_stats(const std::string& prefix, const SetupTimingInfo& timing_info, const AnalysisDelayCalculator& delay_calc, @@ -20,10 +136,11 @@ void generate_setup_timing_stats(const std::string& prefix, const BlkLocRegistry& blk_loc_registry) { auto& timing_ctx = g_vpr_ctx.timing(); auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; print_setup_timing_summary(*timing_ctx.constraints, *timing_info.setup_analyzer(), "Final ", analysis_opts.write_timing_summary); - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); @@ -45,10 +162,11 @@ void generate_hold_timing_stats(const std::string& prefix, const BlkLocRegistry& blk_loc_registry) { auto& timing_ctx = g_vpr_ctx.timing(); auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; print_hold_timing_summary(*timing_ctx.constraints, *timing_info.hold_analyzer(), "Final "); - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); @@ -61,3 +179,55 @@ void generate_hold_timing_stats(const std::string& prefix, timing_reporter.report_unconstrained_hold(prefix + "report_unconstrained_timing.hold.rpt", *timing_info.hold_analyzer()); } + +void generate_net_timing_report(const std::string& prefix, + const SetupHoldTimingInfo& timing_info, + const AnalysisDelayCalculator& delay_calc) { + std::ofstream os(prefix + "report_net_timing.csv"); + const auto& atom_netlist = g_vpr_ctx.atom().netlist(); + const auto& atom_lookup = g_vpr_ctx.atom().lookup(); + const auto& timing_ctx = g_vpr_ctx.timing(); + const auto& timing_graph = timing_ctx.graph; + + // Write CSV header + os << "netname,Fanout,bb_xmin,bb_ymin,bb_layer_min," + << "bb_xmax,bb_ymax,bb_layer_max," + << "src_pin_name,src_pin_slack,sinks" << std::endl; + + for (const auto& net : atom_netlist.nets()) { + const auto& net_name = atom_netlist.net_name(net); + const auto& source_pin = *atom_netlist.net_pins(net).begin(); + // for the driver/source, this is the worst slack to any fanout. + auto source_pin_slack = timing_info.setup_pin_slack(source_pin); + auto tg_source_node = atom_lookup.atom_pin_tnode(source_pin); + VTR_ASSERT(tg_source_node.is_valid()); + + const size_t fanout = atom_netlist.net_sinks(net).size(); + const auto& net_bb = get_net_bounding_box(net); + + os << "\"" << net_name << "\"," // netname (quoted for safety) + << fanout << "," + << net_bb.xmin << "," << net_bb.ymin << "," << net_bb.layer_min << "," + << net_bb.xmax << "," << net_bb.ymax << "," << net_bb.layer_max << "," + << "\"" << atom_netlist.pin_name(source_pin) << "\"," << source_pin_slack << ","; + + // Write sinks column (quoted, semicolon-delimited, each sink: name,slack,delay) + os << "\""; + for (size_t i = 0; i < fanout; ++i) { + const auto& pin = *(atom_netlist.net_pins(net).begin() + i + 1); + auto tg_sink_node = atom_lookup.atom_pin_tnode(pin); + VTR_ASSERT(tg_sink_node.is_valid()); + + auto tg_edge_id = timing_graph->find_edge(tg_source_node, tg_sink_node); + VTR_ASSERT(tg_edge_id.is_valid()); + + auto pin_setup_slack = timing_info.setup_pin_slack(pin); + auto pin_delay = delay_calc.max_edge_delay(*timing_graph, tg_edge_id); + const auto& pin_name = atom_netlist.pin_name(pin); + + os << pin_name << "," << pin_setup_slack << "," << pin_delay; + if (i != fanout - 1) os << ";"; + } + os << "\"" << std::endl; // Close quoted sinks field and finish the row + } +} diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index 72e1013dece..f8ae0c6fc67 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -21,4 +21,29 @@ void generate_hold_timing_stats(const std::string& prefix, bool is_flat, const BlkLocRegistry& blk_loc_registry); +/** + * @brief Generates a CSV report of timing information for each net in the atom netlist. + * + * Each row in the CSV corresponds to a single net and includes: + * - Net name + * - Fanout count + * - Bounding box (xmin, ymin, layer_min, xmax, ymax, layer_max) + * - Source pin name and slack + * - A single "sinks" field that encodes information for all sink pins + * + * The "sinks" field is a semicolon-separated list of all sink pins. + * Each sink pin is represented as a comma-separated triple: + * ,, + * + * Example row: + * netA,2,0,0,0,5,5,1,U1.A,0.25,"U2.B,0.12,0.5;U3.C,0.10,0.6" + * + * @param prefix Prefix for the output file name (report will be saved as report_net_timing.csv) + * @param timing_info Timing analysis results (slacks) + * @param delay_calc Delay calculator used to extract delay between nodes + */ +void generate_net_timing_report(const std::string& prefix, + const SetupHoldTimingInfo& timing_info, + const AnalysisDelayCalculator& delay_calc); + #endif diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index 853f4cb2f02..cd07b601198 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -144,6 +144,7 @@ static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, device_ctx.physical_tile_types, pre_cluster_timing_manager, ap_opts.ap_timing_tradeoff, + ap_opts.num_threads, ap_opts.log_verbosity); return global_placer->place(); } @@ -159,7 +160,7 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { const UserPlaceConstraints& constraints = g_vpr_ctx.floorplanning().constraints; // Run the prepacker - const Prepacker prepacker(atom_nlist, device_ctx.logical_block_types); + const Prepacker prepacker(atom_nlist, device_ctx.arch->models, device_ctx.logical_block_types); // Create the ap netlist from the atom netlist using the result from the // prepacker. diff --git a/vpr/src/analytical_place/analytical_solver.cpp b/vpr/src/analytical_place/analytical_solver.cpp index 22a846d43ea..0c9467a3435 100644 --- a/vpr/src/analytical_place/analytical_solver.cpp +++ b/vpr/src/analytical_place/analytical_solver.cpp @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include "PreClusterTimingManager.h" @@ -32,6 +33,7 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wnull-dereference" +#include #include #include #include @@ -48,7 +50,22 @@ std::unique_ptr make_analytical_solver(e_ap_analytical_solver const AtomNetlist& atom_netlist, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity) { +#ifdef EIGEN_INSTALLED + // Set the number of threads that Eigen can use. + unsigned eigen_num_threads = num_threads; + if (num_threads == 0) { + eigen_num_threads = std::thread::hardware_concurrency(); + } + // Set the number of threads globally used by Eigen (if OpenMP is enabled). + // NOTE: Since this is a global update, all solvers will have this number + // of threads. + Eigen::setNbThreads(eigen_num_threads); +#else + (void)num_threads; +#endif // EIGEN_INSTALLED + // Based on the solver type passed in, build the solver. switch (solver_type) { case e_ap_analytical_solver::QP_Hybrid: @@ -819,13 +836,22 @@ void B2BSolver::store_solution_into_placement(Eigen::VectorXd& x_soln, for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { // Since we are capping the number of iterations, the solver may not // have enough time to converge on a solution that is on the device. - // We just clamp the solution to zero for now. + // Set the solution to be within the device grid. To prevent round-off + // errors causing the position to move outside of the device, we add a + // small buffer (epsilon) to the position. + // TODO: Create a helper method to clamp a position to just within the + // device grid. // TODO: Should handle this better. If the solution is very negative // it may indicate a bug. - if (x_soln[row_id_idx] < 0.0) - x_soln[row_id_idx] = 0.0; - if (y_soln[row_id_idx] < 0.0) - y_soln[row_id_idx] = 0.0; + double epsilon = 0.0001; + if (x_soln[row_id_idx] < epsilon) + x_soln[row_id_idx] = epsilon; + if (x_soln[row_id_idx] >= device_grid_width_) + x_soln[row_id_idx] = device_grid_width_ - epsilon; + if (y_soln[row_id_idx] < epsilon) + y_soln[row_id_idx] = epsilon; + if (y_soln[row_id_idx] >= device_grid_height_) + y_soln[row_id_idx] = device_grid_height_ - epsilon; APRowId row_id = APRowId(row_id_idx); APBlockId blk_id = row_id_to_blk_id_[row_id]; diff --git a/vpr/src/analytical_place/analytical_solver.h b/vpr/src/analytical_place/analytical_solver.h index 2d748e2a493..2209349fdaf 100644 --- a/vpr/src/analytical_place/analytical_solver.h +++ b/vpr/src/analytical_place/analytical_solver.h @@ -138,6 +138,7 @@ std::unique_ptr make_analytical_solver(e_ap_analytical_solver const AtomNetlist& atom_netlist, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity); // The Eigen library is used to solve matrix equations in the following solvers. diff --git a/vpr/src/analytical_place/detailed_placer.cpp b/vpr/src/analytical_place/detailed_placer.cpp index 75001fe4c42..9b84e1cf6f9 100644 --- a/vpr/src/analytical_place/detailed_placer.cpp +++ b/vpr/src/analytical_place/detailed_placer.cpp @@ -65,7 +65,7 @@ AnnealerDetailedPlacer::AnnealerDetailedPlacer(const BlkLocRegistry& curr_cluste place_delay_model = PlacementDelayModelCreator::create_delay_model(vpr_setup.PlacerOpts, vpr_setup.RouterOpts, (const Netlist<>&)clustered_netlist, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, arch.Chans, arch.directs, diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp index c99aaf29339..3581c4ce868 100644 --- a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp @@ -25,9 +25,9 @@ * TODO: This will be made more complicated later. Models may be weighted based * on some factors. */ -static float get_model_mass(const t_model* model) { +static float get_model_mass(LogicalModelId model_id) { // Currently, all models have a mass of one. - (void)model; + (void)model_id; return 1.f; } @@ -68,11 +68,10 @@ static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) { // capacities as if the pb could choose either one. PrimitiveVector capacity; // If this is a leaf / primitive, create the base PrimitiveVector capacity. - if (pb_type->num_modes == 0) { - const t_model* model = pb_type->model; - VTR_ASSERT(model != nullptr); - VTR_ASSERT_DEBUG(model->index >= 0); - capacity.add_val_to_dim(get_model_mass(model), model->index); + if (pb_type->is_primitive()) { + LogicalModelId model_id = pb_type->model_id; + VTR_ASSERT(model_id.is_valid()); + capacity.add_val_to_dim(get_model_mass(model_id), (size_t)model_id); return capacity; } // For now, we simply mix the capacities of modes by taking the max of each @@ -167,9 +166,9 @@ static PrimitiveVector calc_block_mass(APBlockId blk_id, // safely be ignored. if (!atom_blk_id.is_valid()) continue; - const t_model* model = atom_netlist.block_model(atom_blk_id); - VTR_ASSERT_DEBUG(model->index >= 0); - mass.add_val_to_dim(get_model_mass(model), model->index); + LogicalModelId model_id = atom_netlist.block_model(atom_blk_id); + VTR_ASSERT(model_id.is_valid()); + mass.add_val_to_dim(get_model_mass(model_id), (size_t)model_id); } return mass; } @@ -182,38 +181,22 @@ static void print_capacities(const std::vector& logical_block_t const std::vector& physical_tile_type_capacities, const std::vector& logical_block_types, const std::vector& physical_tile_types) { - // Get a linear list of all models. - // TODO: I do not like using the global context here, but these models - // should be stable in VTR. If they were stored better, we may be - // able to pass them in. - std::vector all_models; - t_model* curr_model = g_vpr_ctx.device().arch->models; - while (curr_model != nullptr) { - if (curr_model->index >= (int)all_models.size()) - all_models.resize(curr_model->index + 1); - all_models[curr_model->index] = curr_model; - curr_model = curr_model->next; - } - curr_model = g_vpr_ctx.device().arch->model_library; - while (curr_model != nullptr) { - if (curr_model->index >= (int)all_models.size()) - all_models.resize(curr_model->index + 1); - all_models[curr_model->index] = curr_model; - curr_model = curr_model->next; - } + // TODO: Pass these into this function. + const LogicalModels& models = g_vpr_ctx.device().arch->models; + // Print the capacities. VTR_LOG("Logical Block Type Capacities:\n"); VTR_LOG("------------------------------\n"); VTR_LOG("name\t"); - for (t_model* model : all_models) { - VTR_LOG("%s\t", model->name); + for (LogicalModelId model_id : models.all_models()) { + VTR_LOG("%s\t", models.get_model(model_id).name); } VTR_LOG("\n"); for (const t_logical_block_type& block_type : logical_block_types) { const PrimitiveVector& capacity = logical_block_type_capacities[block_type.index]; VTR_LOG("%s\t", block_type.name.c_str()); - for (t_model* model : all_models) { - VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); + for (LogicalModelId model_id : models.all_models()) { + VTR_LOG("%.2f\t", capacity.get_dim_val((size_t)model_id)); } VTR_LOG("\n"); } @@ -221,15 +204,15 @@ static void print_capacities(const std::vector& logical_block_t VTR_LOG("Physical Tile Type Capacities:\n"); VTR_LOG("------------------------------\n"); VTR_LOG("name\t"); - for (t_model* model : all_models) { - VTR_LOG("%s\t", model->name); + for (LogicalModelId model_id : models.all_models()) { + VTR_LOG("%s\t", models.get_model(model_id).name); } VTR_LOG("\n"); for (const t_physical_tile_type& tile_type : physical_tile_types) { const PrimitiveVector& capacity = physical_tile_type_capacities[tile_type.index]; VTR_LOG("%s\t", tile_type.name.c_str()); - for (t_model* model : all_models) { - VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); + for (LogicalModelId model_id : models.all_models()) { + VTR_LOG("%.2f\t", capacity.get_dim_val((size_t)model_id)); } VTR_LOG("\n"); } diff --git a/vpr/src/analytical_place/full_legalizer.cpp b/vpr/src/analytical_place/full_legalizer.cpp index 767ac67e3d9..369ef53510c 100644 --- a/vpr/src/analytical_place/full_legalizer.cpp +++ b/vpr/src/analytical_place/full_legalizer.cpp @@ -249,7 +249,7 @@ class APClusterPlacer { static LegalizationClusterId create_new_cluster(PackMoleculeId seed_molecule_id, const Prepacker& prepacker, ClusterLegalizer& cluster_legalizer, - const std::map>& primitive_candidate_block_types) { + const vtr::vector>& primitive_candidate_block_types) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); // This was stolen from pack/cluster_util.cpp:start_new_cluster // It tries to find a block type and mode for the given molecule. @@ -260,11 +260,11 @@ static LegalizationClusterId create_new_cluster(PackMoleculeId seed_molecule_id, VTR_ASSERT(seed_molecule_id.is_valid()); const t_pack_molecule& seed_molecule = prepacker.get_molecule(seed_molecule_id); AtomBlockId root_atom = seed_molecule.atom_block_ids[seed_molecule.root]; - const t_model* root_model = atom_ctx.netlist().block_model(root_atom); + LogicalModelId root_model_id = atom_ctx.netlist().block_model(root_atom); - auto itr = primitive_candidate_block_types.find(root_model); - VTR_ASSERT(itr != primitive_candidate_block_types.end()); - const std::vector& candidate_types = itr->second; + VTR_ASSERT(root_model_id.is_valid()); + VTR_ASSERT(!primitive_candidate_block_types[root_model_id].empty()); + const std::vector& candidate_types = primitive_candidate_block_types[root_model_id]; for (t_logical_block_type_ptr type : candidate_types) { int num_modes = type->pb_graph_head->pb_type->num_modes; @@ -295,6 +295,7 @@ void NaiveFullLegalizer::create_clusters(const PartialPlacement& p_placement) { high_fanout_thresholds, ClusterLegalizationStrategy::FULL, vpr_setup_.PackerOpts.enable_pin_feasibility_filter, + arch_.models, vpr_setup_.PackerOpts.pack_verbosity); // Create clusters for each tile. // Start by giving each root tile a unique ID. @@ -328,7 +329,7 @@ void NaiveFullLegalizer::create_clusters(const PartialPlacement& p_placement) { blocks_in_tiles[tile_id].push_back(ap_blk_id); } // Create the legalized clusters per tile. - std::map> + vtr::vector> primitive_candidate_block_types = identify_primitive_candidate_block_types(); for (size_t tile_id_idx = 0; tile_id_idx < num_device_tiles; tile_id_idx++) { DeviceTileId tile_id = DeviceTileId(tile_id_idx); @@ -519,6 +520,7 @@ void APPack::legalize(const PartialPlacement& p_placement) { // Run the Packer stage with the flat placement as a hint. try_pack(vpr_setup_.PackerOpts, vpr_setup_.AnalysisOpts, + vpr_setup_.APOpts, arch_, vpr_setup_.PackerRRGraph, prepacker_, diff --git a/vpr/src/analytical_place/global_placer.cpp b/vpr/src/analytical_place/global_placer.cpp index d9131e85308..ebf506a3432 100644 --- a/vpr/src/analytical_place/global_placer.cpp +++ b/vpr/src/analytical_place/global_placer.cpp @@ -37,6 +37,7 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic const std::vector& physical_tile_types, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity) { return std::make_unique(analytical_solver_type, partial_legalizer_type, @@ -48,6 +49,7 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic physical_tile_types, pre_cluster_timing_manager, ap_timing_tradeoff, + num_threads, log_verbosity); } @@ -61,6 +63,7 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty const std::vector& physical_tile_types, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity) : GlobalPlacer(ap_netlist, log_verbosity) { // This can be a long method. Good to time this to see how long it takes to @@ -75,6 +78,7 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty atom_netlist, pre_cluster_timing_manager, ap_timing_tradeoff, + num_threads, log_verbosity_); // Build the density manager used by the partial legalizer. diff --git a/vpr/src/analytical_place/global_placer.h b/vpr/src/analytical_place/global_placer.h index 7772aa302bb..6b59484db65 100644 --- a/vpr/src/analytical_place/global_placer.h +++ b/vpr/src/analytical_place/global_placer.h @@ -83,6 +83,7 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic const std::vector& physical_tile_types, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity); /** @@ -148,6 +149,7 @@ class SimPLGlobalPlacer : public GlobalPlacer { const std::vector& physical_tile_types, const PreClusterTimingManager& pre_cluster_timing_manager, float ap_timing_tradeoff, + unsigned num_threads, int log_verbosity); /** diff --git a/vpr/src/analytical_place/model_grouper.cpp b/vpr/src/analytical_place/model_grouper.cpp index 0aca963c96a..1c74c7cdac3 100644 --- a/vpr/src/analytical_place/model_grouper.cpp +++ b/vpr/src/analytical_place/model_grouper.cpp @@ -8,7 +8,6 @@ #include "model_grouper.h" #include -#include #include #include #include "cad_types.h" @@ -16,6 +15,7 @@ #include "prepack.h" #include "vtr_assert.h" #include "vtr_log.h" +#include "vtr_vector.h" /** * @brief Recursive helper function which gets the models in the given pattern @@ -30,7 +30,7 @@ * been visited. */ static void get_pattern_models_recurr(t_pack_pattern_block* pattern_block, - std::unordered_set& models, + std::unordered_set& models, std::vector& block_visited) { // If the pattern block is invalid or this block has been visited, return. if (pattern_block == nullptr || block_visited[pattern_block->block_id]) { @@ -39,7 +39,7 @@ static void get_pattern_models_recurr(t_pack_pattern_block* pattern_block, // Mark this block as visited and insert its model into the models vector. block_visited[pattern_block->block_id] = true; - models.insert(pattern_block->pb_type->model->index); + models.insert(pattern_block->pb_type->model_id); // Go through this block's connections and get their pattern models. t_pack_pattern_connections* connection = pattern_block->connections; @@ -54,8 +54,8 @@ static void get_pattern_models_recurr(t_pack_pattern_block* pattern_block, * @brief Entry point into the recursive function above. Gets the models in * the given pack pattern. */ -static std::unordered_set get_pattern_models(const t_pack_patterns& pack_pattern) { - std::unordered_set models_in_pattern; +static std::unordered_set get_pattern_models(const t_pack_patterns& pack_pattern) { + std::unordered_set models_in_pattern; // Initialize the visited flags for each block to false. std::vector block_visited(pack_pattern.num_blocks, false); @@ -66,8 +66,7 @@ static std::unordered_set get_pattern_models(const t_pack_patterns& pack_pa } ModelGrouper::ModelGrouper(const Prepacker& prepacker, - t_model* user_models, - t_model* library_models, + const LogicalModels& models, int log_verbosity) { /** * Group the models together based on their pack patterns. If model A and @@ -80,26 +79,10 @@ ModelGrouper::ModelGrouper(const Prepacker& prepacker, * the connected sub-graphs which will be the groups. */ - // Get the number of models - // TODO: Clean up the models vectors in VTR. - std::unordered_map model_name; - unsigned num_models = 0; - t_model* model = library_models; - while (model != nullptr) { - model_name[model->index] = model->name; - num_models++; - model = model->next; - } - model = user_models; - while (model != nullptr) { - model_name[model->index] = model->name; - num_models++; - model = model->next; - } - // Create an adjacency list for the edges. An edge is formed where two // models share a pack pattern together. - std::vector> adj_list(num_models); + size_t num_models = models.all_models().size(); + vtr::vector> adj_list(num_models); for (const t_pack_patterns& pack_pattern : prepacker.get_all_pack_patterns()) { // Get the models within this pattern. auto models_in_pattern = get_pattern_models(pack_pattern); @@ -108,8 +91,8 @@ ModelGrouper::ModelGrouper(const Prepacker& prepacker, // Debug print the models within the pattern. if (log_verbosity >= 20) { VTR_LOG("Pattern: %s\n\t", pack_pattern.name); - for (int model_idx : models_in_pattern) { - VTR_LOG("%s ", model_name[model_idx]); + for (LogicalModelId model_id : models_in_pattern) { + VTR_LOG("%s ", models.model_name(model_id).c_str()); } VTR_LOG("\n"); } @@ -117,8 +100,8 @@ ModelGrouper::ModelGrouper(const Prepacker& prepacker, // Connect each of the models to the first model in the pattern. Since // we only care if there exist a path from each model to another, we do // not need to connect the models in a clique. - int first_model_idx = *models_in_pattern.begin(); - for (int model_idx : models_in_pattern) { + LogicalModelId first_model_idx = *models_in_pattern.begin(); + for (LogicalModelId model_idx : models_in_pattern) { adj_list[model_idx].insert(first_model_idx); adj_list[first_model_idx].insert(model_idx); } @@ -127,57 +110,57 @@ ModelGrouper::ModelGrouper(const Prepacker& prepacker, // Perform BFS to group the models. VTR_LOGV(log_verbosity >= 20, "Finding model groups...\n"); - std::queue node_queue; + std::queue node_queue; model_group_id_.resize(num_models, ModelGroupId::INVALID()); - for (int model_idx = 0; model_idx < (int)num_models; model_idx++) { + for (LogicalModelId model_id : models.all_models()) { // If this model is already in a group, skip it. - if (model_group_id_[model_idx].is_valid()) { + if (model_group_id_[model_id].is_valid()) { VTR_LOGV(log_verbosity >= 20, - "\t(%d -> %d)\n", model_idx, model_group_id_[model_idx]); + "\t(%zu -> %zu)\n", model_id, model_group_id_[model_id]); continue; } ModelGroupId group_id = ModelGroupId(group_ids_.size()); // Put the model in this group and push to the queue. - model_group_id_[model_idx] = group_id; - node_queue.push(model_idx); + model_group_id_[model_id] = group_id; + node_queue.push(model_id); while (!node_queue.empty()) { // Pop a node from the queue, and explore its neighbors. - int node_model_idx = node_queue.front(); + LogicalModelId node_model_id = node_queue.front(); node_queue.pop(); - for (int neighbor_model_idx : adj_list[node_model_idx]) { + for (LogicalModelId neighbor_model_id : adj_list[node_model_id]) { // If this neighbor is already in this group, skip it. - if (model_group_id_[neighbor_model_idx].is_valid()) { - VTR_ASSERT_SAFE(model_group_id_[neighbor_model_idx] == group_id); + if (model_group_id_[neighbor_model_id].is_valid()) { + VTR_ASSERT_SAFE(model_group_id_[neighbor_model_id] == group_id); continue; } // Put the neighbor in this group and push it to the queue. - model_group_id_[neighbor_model_idx] = group_id; - node_queue.push(neighbor_model_idx); + model_group_id_[neighbor_model_id] = group_id; + node_queue.push(neighbor_model_id); } } VTR_LOGV(log_verbosity >= 20, - "\t(%d -> %d)\n", model_idx, model_group_id_[model_idx]); + "\t(%zu -> %zu)\n", model_id, model_group_id_[model_id]); group_ids_.push_back(group_id); } // Create a lookup between each group and the models it contains. groups_.resize(groups().size()); - for (int model_idx = 0; model_idx < (int)num_models; model_idx++) { - groups_[model_group_id_[model_idx]].push_back(model_idx); + for (LogicalModelId model_id : models.all_models()) { + groups_[model_group_id_[model_id]].push_back(model_id); } // Debug printing for each group. if (log_verbosity >= 20) { for (ModelGroupId group_id : groups()) { - const std::vector& group = groups_[group_id]; + const std::vector& group = groups_[group_id]; VTR_LOG("Group %zu:\n", group_id); VTR_LOG("\tSize = %zu\n", group.size()); VTR_LOG("\tContained models:\n"); - for (int model_idx : group) { - VTR_LOG("\t\t%s\n", model_name[model_idx]); + for (LogicalModelId model_id : group) { + VTR_LOG("\t\t%s\n", models.model_name(model_id).c_str()); } } } diff --git a/vpr/src/analytical_place/model_grouper.h b/vpr/src/analytical_place/model_grouper.h index d5a9113d6c1..6e9e56ce03a 100644 --- a/vpr/src/analytical_place/model_grouper.h +++ b/vpr/src/analytical_place/model_grouper.h @@ -9,6 +9,7 @@ #pragma once #include +#include "logic_types.h" #include "vtr_assert.h" #include "vtr_range.h" #include "vtr_strong_id.h" @@ -17,7 +18,6 @@ // Forward declarations. class Prepacker; -struct t_model; /// @brief Tag for the ModelGroupId struct model_group_id_tag; @@ -69,8 +69,7 @@ class ModelGrouper { * The verbosity of log messages in the grouper class. */ ModelGrouper(const Prepacker& prepacker, - t_model* user_models, - t_model* library_models, + const LogicalModels& models, int log_verbosity); /** @@ -83,10 +82,10 @@ class ModelGrouper { /** * @brief Gets the group ID of the given model. */ - inline ModelGroupId get_model_group_id(int model_index) const { - VTR_ASSERT_SAFE_MSG(model_index < (int)model_group_id_.size(), + inline ModelGroupId get_model_group_id(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), "Model index outside of range for model_group_id_"); - ModelGroupId group_id = model_group_id_[model_index]; + ModelGroupId group_id = model_group_id_[model_id]; VTR_ASSERT_SAFE_MSG(group_id.is_valid(), "Model is not in a group"); return group_id; @@ -95,7 +94,7 @@ class ModelGrouper { /** * @brief Gets the models in the given group. */ - inline const std::vector& get_models_in_group(ModelGroupId group_id) const { + inline const std::vector& get_models_in_group(ModelGroupId group_id) const { VTR_ASSERT_SAFE_MSG(group_id.is_valid(), "Invalid group id"); VTR_ASSERT_SAFE_MSG(groups_[group_id].size() != 0, @@ -108,8 +107,8 @@ class ModelGrouper { vtr::vector_map group_ids_; /// @brief A lookup between models and the group ID that contains them. - std::vector model_group_id_; + vtr::vector model_group_id_; /// @brief A lookup between each group ID and the models in that group. - vtr::vector> groups_; + vtr::vector> groups_; }; diff --git a/vpr/src/analytical_place/partial_legalizer.cpp b/vpr/src/analytical_place/partial_legalizer.cpp index 7021734f8d5..38e585ae1b1 100644 --- a/vpr/src/analytical_place/partial_legalizer.cpp +++ b/vpr/src/analytical_place/partial_legalizer.cpp @@ -66,27 +66,6 @@ std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer return nullptr; } -/** - * @brief Get the number of models in the device architecture. - * - * FIXME: These are stored in such an annoying way. It should be much easier - * to get this information! - */ -static inline size_t get_num_models() { - size_t num_models = 0; - t_model* curr_model = g_vpr_ctx.device().arch->models; - while (curr_model != nullptr) { - num_models++; - curr_model = curr_model->next; - } - curr_model = g_vpr_ctx.device().arch->model_library; - while (curr_model != nullptr) { - num_models++; - curr_model = curr_model->next; - } - return num_models; -} - /** * @brief Helper method to get the direct neighbors of the given bin. * @@ -142,7 +121,7 @@ static inline vtr::Point get_center_of_rect(vtr::Rect rect) { return rect.bottom_left() + vtr::Point(rect.width() / 2.0, rect.height() / 2.0); } -void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, size_t num_models) { +void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, const LogicalModels& models) { // Make sure that this bin does not already have neighbors. VTR_ASSERT_DEBUG(bin_neighbors_.size() == 0); @@ -165,10 +144,11 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, // Flags to check if a specific model has been found in the given direction. // In this case, direction is the direction of the largest component of the // manhattan distance between the source bin and the target bin. - std::vector up_found(num_models, false); - std::vector down_found(num_models, false); - std::vector left_found(num_models, false); - std::vector right_found(num_models, false); + size_t num_models = models.all_models().size(); + vtr::vector up_found(num_models, false); + vtr::vector down_found(num_models, false); + vtr::vector left_found(num_models, false); + vtr::vector right_found(num_models, false); // Flags to check if all models have been found in a given direction. bool all_up_found = false; bool all_down_found = false; @@ -186,17 +166,17 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, // type. This method returns true if every model has been found in the given // direction (i.e. dir_found is now all true). auto add_neighbor_if_new_dir = [&](FlatPlacementBinId target_bin_id, - std::vector& dir_found) { + vtr::vector& dir_found) { bool all_found = true; // Go through all possible models - for (size_t i = 0; i < num_models; i++) { + for (LogicalModelId model_id : models.all_models()) { // If this model has been found in this direction, continue. - if (dir_found[i]) + if (dir_found[model_id]) continue; // If this bin has this model in its capacity, we found a neighbor! const PrimitiveVector& target_bin_capacity = density_manager_->get_bin_capacity(target_bin_id); - if (target_bin_capacity.get_dim_val(i) > 0) { - dir_found[i] = true; + if (target_bin_capacity.get_dim_val((size_t)model_id) > 0) { + dir_found[model_id] = true; neighbors.insert(target_bin_id); } else { all_found = false; @@ -271,9 +251,9 @@ FlowBasedLegalizer::FlowBasedLegalizer(const APNetlist& netlist, , bin_neighbors_(density_manager_->flat_placement_bins().bins().size()) { // Connect the bins. - size_t num_models = get_num_models(); for (FlatPlacementBinId bin_id : density_manager_->flat_placement_bins().bins()) { - compute_neighbors_of_bin(bin_id, num_models); + // TODO: Pass the models in. + compute_neighbors_of_bin(bin_id, g_vpr_ctx.device().arch->models); } } @@ -703,42 +683,27 @@ void FlowBasedLegalizer::legalize(PartialPlacement& p_placement) { } PerModelPrefixSum2D::PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, - t_model* user_models, - t_model* library_models, - std::function lookup) { - // Get the number of models in the architecture. - // TODO: We really need to clean up how models are stored in VPR... - t_model* cur = user_models; - int num_models = 0; - while (cur != nullptr) { - num_models++; - cur = cur->next; - } - cur = library_models; - while (cur != nullptr) { - num_models++; - cur = cur->next; - } - + const LogicalModels& models, + std::function lookup) { // Get the size that the prefix sums should be. size_t width, height, layers; std::tie(width, height, layers) = density_manager.get_overall_placeable_region_size(); // Create each of the prefix sums. - model_prefix_sum_.resize(num_models); - for (int model_index = 0; model_index < num_models; model_index++) { - model_prefix_sum_[model_index] = vtr::PrefixSum2D( + model_prefix_sum_.resize(models.all_models().size()); + for (LogicalModelId model_id : models.all_models()) { + model_prefix_sum_[model_id] = vtr::PrefixSum2D( width, height, [&](size_t x, size_t y) { - return lookup(model_index, x, y); + return lookup(model_id, x, y); }); } } -float PerModelPrefixSum2D::get_model_sum(int model_index, +float PerModelPrefixSum2D::get_model_sum(LogicalModelId model_index, const vtr::Rect& region) const { - VTR_ASSERT_SAFE(model_index < (int)model_prefix_sum_.size() && model_index >= 0); + VTR_ASSERT_SAFE(model_index.is_valid()); // Get the sum over the given region. return model_prefix_sum_[model_index].get_sum(region.xmin(), region.ymin(), @@ -746,12 +711,12 @@ float PerModelPrefixSum2D::get_model_sum(int model_index, region.ymax() - 1); } -PrimitiveVector PerModelPrefixSum2D::get_sum(const std::vector& model_indices, +PrimitiveVector PerModelPrefixSum2D::get_sum(const std::vector& model_indices, const vtr::Rect& region) const { PrimitiveVector res; - for (int model_index : model_indices) { - VTR_ASSERT_SAFE(res.get_dim_val(model_index) == 0.0f); - res.set_dim_val(model_index, get_model_sum(model_index, region)); + for (LogicalModelId model_index : model_indices) { + VTR_ASSERT_SAFE(res.get_dim_val((size_t)model_index) == 0.0f); + res.set_dim_val((size_t)model_index, get_model_sum(model_index, region)); } return res; } @@ -765,19 +730,17 @@ BiPartitioningPartialLegalizer::BiPartitioningPartialLegalizer( , density_manager_(density_manager) , model_grouper_(prepacker, g_vpr_ctx.device().arch->models, - g_vpr_ctx.device().arch->model_library, log_verbosity) { // Compute the capacity prefix sum. Capacity is assumed to not change // between iterations of the partial legalizer. capacity_prefix_sum_ = PerModelPrefixSum2D( *density_manager, g_vpr_ctx.device().arch->models, - g_vpr_ctx.device().arch->model_library, - [&](int model_index, size_t x, size_t y) { + [&](LogicalModelId model_index, size_t x, size_t y) { // Get the bin at this grid location. FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); // Get the capacity of the bin for this model. - float cap = density_manager_->get_bin_capacity(bin_id).get_dim_val(model_index); + float cap = density_manager_->get_bin_capacity(bin_id).get_dim_val((size_t)model_index); VTR_ASSERT_SAFE(cap >= 0.0f); // Bins may be large, but the prefix sum assumes a 1x1 grid of // values. Normalize by the area of the bin to turn this into @@ -831,7 +794,7 @@ void BiPartitioningPartialLegalizer::legalize(PartialPlacement& p_placement) { std::vector overfilled_models = overfill.get_non_zero_dims(); // For each model, insert its group into the set. Set will handle dupes. for (int model_index : overfilled_models) { - groups_to_spread.insert(model_grouper_.get_model_group_id(model_index)); + groups_to_spread.insert(model_grouper_.get_model_group_id((LogicalModelId)model_index)); } } @@ -905,9 +868,9 @@ static bool is_vector_in_group(const PrimitiveVector& vec, ModelGroupId group_id, const ModelGrouper& model_grouper) { VTR_ASSERT_SAFE(vec.is_non_negative()); - const std::vector& models_in_group = model_grouper.get_models_in_group(group_id); - for (int model_index : models_in_group) { - float dim_val = vec.get_dim_val(model_index); + const std::vector& models_in_group = model_grouper.get_models_in_group(group_id); + for (LogicalModelId model_index : models_in_group) { + float dim_val = vec.get_dim_val((size_t)model_index); if (dim_val != 0.0f) return true; } @@ -1010,9 +973,9 @@ std::vector BiPartitioningPartialLegalizer::get_overfil static bool is_region_overfilled(const vtr::Rect& region, const PerModelPrefixSum2D& capacity_prefix_sum, const PerModelPrefixSum2D& utilization_prefix_sum, - const std::vector& model_indices) { + const std::vector& model_indices) { // Go through each model in the model group we are interested in. - for (int model_index : model_indices) { + for (LogicalModelId model_index : model_indices) { // Get the capacity of this region for this model. float region_model_capacity = capacity_prefix_sum.get_model_sum(model_index, region); @@ -1052,13 +1015,12 @@ std::vector BiPartitioningPartialLegalizer::get_min_windows_aro PerModelPrefixSum2D utilization_prefix_sum( *density_manager_, g_vpr_ctx.device().arch->models, - g_vpr_ctx.device().arch->model_library, - [&](int model_index, size_t x, size_t y) { + [&](LogicalModelId model_index, size_t x, size_t y) { FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); // This is computed the same way as the capacity prefix sum above. const vtr::Rect& bin_region = density_manager_->flat_placement_bins().bin_region(bin_id); float bin_area = bin_region.width() * bin_region.height(); - float util = density_manager_->get_bin_utilization(bin_id).get_dim_val(model_index); + float util = density_manager_->get_bin_utilization(bin_id).get_dim_val((size_t)model_index); VTR_ASSERT_SAFE(util >= 0.0f); return util / bin_area; }); @@ -1271,7 +1233,7 @@ void BiPartitioningPartialLegalizer::spread_over_windows(std::vectorverify()); } -PartitionedWindow BiPartitioningPartialLegalizer::partition_window(SpreadingWindow& window) { +PartitionedWindow BiPartitioningPartialLegalizer::partition_window( + SpreadingWindow& window, + ModelGroupId group_id) { + + // Search for the ideal partition line on the window. Here, we attempt each + // partition and measure how well this cuts the capacity of the region in + // half. Cutting the capacity of the region in half should allow the blocks + // within the region to also be cut in half (assuming a good initial window + // was chosen). This should allow the spreader to spread things more evenly + // and converge faster. Hence, it is worth spending more time trying to find + // better partition lines. + // + // Here, we compute the score of a partition as a number between 0 and 1 + // which represents how balanced the partition is. 0 means that all of the + // capacity is on one side of the partition, 1 means that the capacities of + // the two partitions are perfectly balanced (equal on both sides). + float best_score = -1.0f; PartitionedWindow partitioned_window; + const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); - // Select the partition direction. - // To keep it simple, we partition the direction which would cut the - // region the most. - // TODO: Should explore making the partition line based on the capacity - // of the two partitioned regions. We may want to cut the - // region in half such that the mass of the atoms contained within - // the two future regions is equal. - partitioned_window.partition_dir = e_partition_dir::VERTICAL; - if (window.region.height() > window.region.width()) - partitioned_window.partition_dir = e_partition_dir::HORIZONTAL; - - // To keep it simple, just cut the space in half. - // TODO: Should investigate other cutting techniques. Cutting perfectly - // in half may not be the most efficient technique. - SpreadingWindow& lower_window = partitioned_window.lower_window; - SpreadingWindow& upper_window = partitioned_window.upper_window; - partitioned_window.pivot_pos = 0.f; - if (partitioned_window.partition_dir == e_partition_dir::VERTICAL) { - // Find the x-coordinate of a cut line directly in the middle of the - // region. We floor this to prevent fractional cut lines. - double pivot_x = std::floor((window.region.xmin() + window.region.xmax()) / 2.0); + // First, try all of the vertical partitions. + double min_pivot_x = std::floor(window.region.xmin()) + 1.0; + double max_pivot_x = std::ceil(window.region.xmax()) - 1.0; + for (double pivot_x = min_pivot_x; pivot_x <= max_pivot_x; pivot_x++) { + // Cut the region at this cut line. + auto lower_region = vtr::Rect(vtr::Point(window.region.xmin(), + window.region.ymin()), + vtr::Point(pivot_x, + window.region.ymax())); + + auto upper_region = vtr::Rect(vtr::Point(pivot_x, + window.region.ymin()), + vtr::Point(window.region.xmax(), + window.region.ymax())); + + // Compute the capacity of each partition for the models that we care + // about. + // TODO: This can be made better by looking at the mass of all blocks + // within the window and scaling the capacity based on that. + float lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, lower_region).manhattan_norm(); + lower_window_capacity = std::max(lower_window_capacity, 0.0f); + float upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, upper_region).manhattan_norm(); + upper_window_capacity = std::max(upper_window_capacity, 0.0f); + + // Compute the score of this partition line. The score is simply just + // the minimum of the two capacities dividided by the maximum of the + // two capacities. + float smaller_capacity = std::min(lower_window_capacity, upper_window_capacity); + float larger_capacity = std::max(lower_window_capacity, upper_window_capacity); + float cut_score = smaller_capacity / larger_capacity; + + // If this is the best cut we have ever seen, save it as the result. + if (cut_score > best_score) { + best_score = cut_score; + partitioned_window.partition_dir = e_partition_dir::VERTICAL; + partitioned_window.pivot_pos = pivot_x; + partitioned_window.lower_window.region = lower_region; + partitioned_window.upper_window.region = upper_region; + } + } + // Next, try all of the horizontal partitions. + double min_pivot_y = std::floor(window.region.ymin()) + 1.0; + double max_pivot_y = std::ceil(window.region.ymax()) - 1.0; + for (double pivot_y = min_pivot_y; pivot_y <= max_pivot_y; pivot_y++) { // Cut the region at this cut line. - lower_window.region = vtr::Rect(vtr::Point(window.region.xmin(), - window.region.ymin()), - vtr::Point(pivot_x, - window.region.ymax())); - - upper_window.region = vtr::Rect(vtr::Point(pivot_x, - window.region.ymin()), - vtr::Point(window.region.xmax(), - window.region.ymax())); - partitioned_window.pivot_pos = pivot_x; - } else { - VTR_ASSERT(partitioned_window.partition_dir == e_partition_dir::HORIZONTAL); - // Similarly in the y direction, find the non-fractional y coordinate - // to make a horizontal cut. - double pivot_y = std::floor((window.region.ymin() + window.region.ymax()) / 2.0); - - // Then cut the window. - lower_window.region = vtr::Rect(vtr::Point(window.region.xmin(), - window.region.ymin()), - vtr::Point(window.region.xmax(), - pivot_y)); - - upper_window.region = vtr::Rect(vtr::Point(window.region.xmin(), - pivot_y), - vtr::Point(window.region.xmax(), - window.region.ymax())); - partitioned_window.pivot_pos = pivot_y; + auto lower_region = vtr::Rect(vtr::Point(window.region.xmin(), + window.region.ymin()), + vtr::Point(window.region.xmax(), + pivot_y)); + + auto upper_region = vtr::Rect(vtr::Point(window.region.xmin(), + pivot_y), + vtr::Point(window.region.xmax(), + window.region.ymax())); + + // Compute the capacity of each partition for the models that we care + // about. + // TODO: This can be made better by looking at the mass of all blocks + // within the window and scaling the capacity based on that. + float lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, lower_region).manhattan_norm(); + lower_window_capacity = std::max(lower_window_capacity, 0.0f); + float upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, upper_region).manhattan_norm(); + upper_window_capacity = std::max(upper_window_capacity, 0.0f); + + // Compute the score of this partition line. The score is simply just + // the minimum of the two capacities dividided by the maximum of the + // two capacities. + float smaller_capacity = std::min(lower_window_capacity, upper_window_capacity); + float larger_capacity = std::max(lower_window_capacity, upper_window_capacity); + float cut_score = smaller_capacity / larger_capacity; + + // If this is the best cut we have ever seen, save it as the result. + if (cut_score > best_score) { + best_score = cut_score; + partitioned_window.partition_dir = e_partition_dir::HORIZONTAL; + partitioned_window.pivot_pos = pivot_y; + partitioned_window.lower_window.region = lower_region; + partitioned_window.upper_window.region = upper_region; + } } + VTR_ASSERT_MSG(best_score >= 0.0f, + "Could not find a partition line for given window"); + return partitioned_window; } @@ -1379,7 +1391,7 @@ void BiPartitioningPartialLegalizer::partition_blocks_in_window( SpreadingWindow& upper_window = partitioned_window.upper_window; // Get the capacity of each window partition. - const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); + const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); PrimitiveVector lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, lower_window.region); PrimitiveVector upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, @@ -1475,7 +1487,7 @@ void BiPartitioningPartialLegalizer::partition_blocks_in_window( // NOTE: This needs to be an int in case the pivot is 0. for (int i = window.contained_blocks.size() - 1; i >= (int)pivot; i--) { const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(window.contained_blocks[i]); - VTR_ASSERT_SAFE(lower_window_underfill.is_non_negative()); + VTR_ASSERT_SAFE(upper_window_underfill.is_non_negative()); upper_window_underfill -= blk_mass; if (upper_window_underfill.is_non_negative()) upper_window.contained_blocks.push_back(window.contained_blocks[i]); @@ -1490,8 +1502,6 @@ void BiPartitioningPartialLegalizer::partition_blocks_in_window( // windows. To do this we sort the unplaced blocks by largest mass to // smallest mass. Then we place each block in the bin with the highest // underfill. - // FIXME: Above was the intuition; however, after experimentation, found that - // sorting by smallest mass to largest mass worked better... // FIXME: I think large blocks (like carry chains) need to be handled special // early on. If they are put into a partition too late, they may have // to create overfill! Perhaps the partitions can hold two lists. @@ -1500,20 +1510,20 @@ void BiPartitioningPartialLegalizer::partition_blocks_in_window( [&](APBlockId a, APBlockId b) { const auto& blk_a_mass = density_manager_->mass_calculator().get_block_mass(a); const auto& blk_b_mass = density_manager_->mass_calculator().get_block_mass(b); - return blk_a_mass.manhattan_norm() < blk_b_mass.manhattan_norm(); + return blk_a_mass.manhattan_norm() > blk_b_mass.manhattan_norm(); }); for (APBlockId blk_id : unplaced_blocks) { // Project the underfill from each window onto the mass. This gives us // the overfill in the dimensions the mass cares about. const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(blk_id); PrimitiveVector projected_lower_window_underfill = lower_window_underfill; - lower_window_underfill.project(blk_mass); + projected_lower_window_underfill.project(blk_mass); PrimitiveVector projected_upper_window_underfill = upper_window_underfill; - upper_window_underfill.project(blk_mass); + projected_upper_window_underfill.project(blk_mass); // Put the block in the window with a higher underfill. This tries to // balance the overfill as much as possible. This works even if the // overfill becomes negative. - if (projected_lower_window_underfill.manhattan_norm() >= projected_upper_window_underfill.manhattan_norm()) { + if (projected_lower_window_underfill.sum() >= projected_upper_window_underfill.sum()) { lower_window.contained_blocks.push_back(blk_id); lower_window_underfill -= blk_mass; } else { diff --git a/vpr/src/analytical_place/partial_legalizer.h b/vpr/src/analytical_place/partial_legalizer.h index 2eb4e5771da..3920194eee0 100644 --- a/vpr/src/analytical_place/partial_legalizer.h +++ b/vpr/src/analytical_place/partial_legalizer.h @@ -20,6 +20,7 @@ #include "ap_flow_enums.h" #include "flat_placement_bins.h" #include "flat_placement_density_manager.h" +#include "logic_types.h" #include "model_grouper.h" #include "primitive_vector.h" #include "vtr_geometry.h" @@ -181,7 +182,7 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param src_bin_id The bin to compute the neighbors for. * @param num_models The number of models in the architecture. */ - void compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, size_t num_models); + void compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, const LogicalModels& models); /** * @brief Debugging method which verifies that all the bins are valid. @@ -316,26 +317,25 @@ class PerModelPrefixSum2D { * the model index, x, and y to be populated. */ PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, - t_model* user_models, - t_model* library_models, - std::function lookup); + const LogicalModels& models, + std::function lookup); /** * @brief Get the sum for a given model over the given region. */ - float get_model_sum(int model_index, + float get_model_sum(LogicalModelId model_index, const vtr::Rect& region) const; /** * @brief Get the multi-dimensional sum over the given model indices over * the given region. */ - PrimitiveVector get_sum(const std::vector& model_indices, + PrimitiveVector get_sum(const std::vector& model_indices, const vtr::Rect& region) const; private: /// @brief Per-Model Prefix Sums - std::vector> model_prefix_sum_; + vtr::vector> model_prefix_sum_; }; /** @@ -483,7 +483,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { * the direction of the partition (vertical / horizontal) and the position * of the cut. */ - PartitionedWindow partition_window(SpreadingWindow& window); + PartitionedWindow partition_window(SpreadingWindow& window, ModelGroupId group_id); /** * @brief Partition the blocks in the given window into the partitioned diff --git a/vpr/src/analytical_place/primitive_vector.h b/vpr/src/analytical_place/primitive_vector.h index d76ae8b509d..52b0cb8a560 100644 --- a/vpr/src/analytical_place/primitive_vector.h +++ b/vpr/src/analytical_place/primitive_vector.h @@ -266,6 +266,20 @@ class PrimitiveVector { return mag; } + /** + * @brief Computes the sum across all dimensions of the vector. + * + * This is similar to manhattan_norm, however this does not take the + * absolute value of each dimension. + */ + inline float sum() const { + float sum = 0.f; + for (const auto& p : data_) { + sum += p.second; + } + return sum; + } + /** * @brief Project this vector onto the given vector. * diff --git a/vpr/src/base/CheckArch.cpp b/vpr/src/base/CheckArch.cpp index 93e77db3429..e37ec0a21f4 100644 --- a/vpr/src/base/CheckArch.cpp +++ b/vpr/src/base/CheckArch.cpp @@ -1,8 +1,6 @@ +#include "arch_util.h" #include "vpr_types.h" #include "vpr_error.h" -#include "globals.h" -#include "echo_files.h" -#include "read_xml_arch_file.h" #include "CheckArch.h" /******** Function Prototypes ********/ diff --git a/vpr/src/base/CheckArch.h b/vpr/src/base/CheckArch.h index d4a617cea32..5b47ded2acb 100644 --- a/vpr/src/base/CheckArch.h +++ b/vpr/src/base/CheckArch.h @@ -1,6 +1,8 @@ #ifndef CHECKARCH_H #define CHECKARCH_H +#include "physical_types.h" + void CheckArch(const t_arch& Arch); #endif diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 3f2568d673f..9686f1b7546 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -24,7 +24,6 @@ DeviceGrid create_device_grid(const std::string& layout_name, ///@brief Find the device close in size to the specified dimensions DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); - /** * @brief Returns the effective size of the device * (size of the bounding box of non-empty grid tiles) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 000e1ba2b59..6824d388864 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -1,6 +1,7 @@ #include #include +#include "SetupVPR.h" #include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_util.h" @@ -14,7 +15,6 @@ #include "globals.h" #include "read_xml_arch_file.h" #include "read_fpga_interchange_arch.h" -#include "SetupVPR.h" #include "pb_type_graph.h" #include "pack_types.h" #include "lb_type_rr_graph.h" @@ -38,10 +38,12 @@ static void SetupNocOpts(const t_options& Options, t_noc_opts* NocOpts); static void SetupServerOpts(const t_options& Options, t_server_opts* ServerOpts); -static void SetupRoutingArch(const t_arch& Arch, t_det_routing_arch* RoutingArch); + +static void SetupRoutingArch(const t_arch& Arch, t_det_routing_arch& RoutingArch); + static void SetupTiming(const t_options& Options, const bool TimingEnabled, t_timing_inf* Timing); static void SetupSwitches(const t_arch& Arch, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, const std::vector& arch_switches); static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysis_opts); static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch); @@ -97,8 +99,6 @@ void SetupVPR(const t_options* options, const bool readArchFile, t_file_name_opts* fileNameOpts, t_arch* arch, - t_model** user_models, - t_model** library_models, t_netlist_opts* netlistOpts, t_packer_opts* packerOpts, t_placer_opts* placerOpts, @@ -107,7 +107,7 @@ void SetupVPR(const t_options* options, t_analysis_opts* analysisOpts, t_noc_opts* nocOpts, t_server_opts* serverOpts, - t_det_routing_arch* routingArch, + t_det_routing_arch& routingArch, std::vector** packerRRGraphs, std::vector& segments, t_timing_inf* timing, @@ -121,6 +121,8 @@ void SetupVPR(const t_options* options, auto& device_ctx = g_vpr_ctx.mutable_device(); + device_ctx.arch = arch; + if (options->CircuitName.value().empty()) { VPR_FATAL_ERROR(VPR_ERROR_BLIF_F, "No blif file found in arguments (did you specify an architecture file?)\n"); @@ -185,9 +187,6 @@ void SetupVPR(const t_options* options, } VTR_LOG("\n"); - *user_models = arch->models; - *library_models = arch->model_library; - device_ctx.EMPTY_PHYSICAL_TILE_TYPE = nullptr; int num_inputs = 0; int num_outputs = 0; @@ -242,9 +241,9 @@ void SetupVPR(const t_options* options, SetupTiming(*options, timingenabled, timing); SetupPackerOpts(*options, packerOpts); SetupAPOpts(*options, *apOpts); - routingArch->write_rr_graph_filename = options->write_rr_graph_file; - routingArch->read_rr_graph_filename = options->read_rr_graph_file; - routingArch->read_rr_edge_override_filename = options->read_rr_edge_override_file; + routingArch.write_rr_graph_filename = options->write_rr_graph_file; + routingArch.read_rr_graph_filename = options->read_rr_graph_file; + routingArch.read_rr_edge_override_filename = options->read_rr_edge_override_file; if (!arch->vib_infs.empty()) { SetupVibInf(device_ctx.physical_tile_types, arch->switches, arch->Segments, arch->vib_infs); @@ -370,17 +369,17 @@ static void SetupTiming(const t_options& Options, const bool TimingEnabled, t_ti * from the arch file with the special switches that VPR needs. */ static void SetupSwitches(const t_arch& Arch, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, const std::vector& arch_switches) { auto& device_ctx = g_vpr_ctx.mutable_device(); int switches_to_copy = (int)arch_switches.size(); int num_arch_switches = (int)arch_switches.size(); - find_ipin_cblock_switch_index(Arch, RoutingArch->wire_to_arch_ipin_switch, RoutingArch->wire_to_arch_ipin_switch_between_dice); + find_ipin_cblock_switch_index(Arch, RoutingArch.wire_to_arch_ipin_switch, RoutingArch.wire_to_arch_ipin_switch_between_dice); /* Depends on device_ctx.num_arch_switches */ - RoutingArch->delayless_switch = num_arch_switches++; + RoutingArch.delayless_switch = num_arch_switches++; /* Alloc the list now that we know the final num_arch_switches value */ device_ctx.arch_switch_inf.resize(num_arch_switches); @@ -392,32 +391,32 @@ static void SetupSwitches(const t_arch& Arch, } /* Delayless switch for connecting sinks and sources with their pins. */ - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].set_type(SwitchType::MUX); - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].name = std::string(VPR_DELAYLESS_SWITCH_NAME); - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].R = 0.; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].Cin = 0.; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].Cout = 0.; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.); - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].mux_trans_size = 0.; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].buf_size_type = BufferSize::ABSOLUTE; - device_ctx.arch_switch_inf[RoutingArch->delayless_switch].buf_size = 0.; - VTR_ASSERT_MSG(device_ctx.arch_switch_inf[RoutingArch->delayless_switch].buffered(), "Delayless switch expected to be buffered (isolating)"); - VTR_ASSERT_MSG(device_ctx.arch_switch_inf[RoutingArch->delayless_switch].configurable(), "Delayless switch expected to be configurable"); + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].set_type(SwitchType::MUX); + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].name = std::string(VPR_DELAYLESS_SWITCH_NAME); + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].R = 0.; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].Cin = 0.; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].Cout = 0.; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.); + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].mux_trans_size = 0.; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].buf_size_type = BufferSize::ABSOLUTE; + device_ctx.arch_switch_inf[RoutingArch.delayless_switch].buf_size = 0.; + VTR_ASSERT_MSG(device_ctx.arch_switch_inf[RoutingArch.delayless_switch].buffered(), "Delayless switch expected to be buffered (isolating)"); + VTR_ASSERT_MSG(device_ctx.arch_switch_inf[RoutingArch.delayless_switch].configurable(), "Delayless switch expected to be configurable"); - device_ctx.all_sw_inf[RoutingArch->delayless_switch] = device_ctx.arch_switch_inf[RoutingArch->delayless_switch]; + device_ctx.all_sw_inf[RoutingArch.delayless_switch] = device_ctx.arch_switch_inf[RoutingArch.delayless_switch]; - RoutingArch->global_route_switch = RoutingArch->delayless_switch; + RoutingArch.global_route_switch = RoutingArch.delayless_switch; - device_ctx.delayless_switch_idx = RoutingArch->delayless_switch; + device_ctx.delayless_switch_idx = RoutingArch.delayless_switch; //Warn about non-zero Cout values for the ipin switch, since these values have no effect. //VPR do not model the R/C's of block internal routing connection. // //Note that we don't warn about the R value as it may be used to size the buffer (if buf_size_type is AUTO) - if (device_ctx.arch_switch_inf[RoutingArch->wire_to_arch_ipin_switch].Cout != 0.) { + if (device_ctx.arch_switch_inf[RoutingArch.wire_to_arch_ipin_switch].Cout != 0.) { VTR_LOG_WARN("Non-zero switch output capacitance (%g) has no effect when switch '%s' is used for connection block inputs\n", - device_ctx.arch_switch_inf[RoutingArch->wire_to_arch_ipin_switch].Cout, Arch.ipin_cblock_switch_name[0].c_str()); + device_ctx.arch_switch_inf[RoutingArch.wire_to_arch_ipin_switch].Cout, Arch.ipin_cblock_switch_name[0].c_str()); } } @@ -427,29 +426,29 @@ static void SetupSwitches(const t_arch& Arch, * Since checks are already done, this just copies values across */ static void SetupRoutingArch(const t_arch& Arch, - t_det_routing_arch* RoutingArch) { - RoutingArch->switch_block_type = Arch.SBType; - RoutingArch->switch_block_subtype = Arch.SBSubType; - RoutingArch->R_minW_nmos = Arch.R_minW_nmos; - RoutingArch->R_minW_pmos = Arch.R_minW_pmos; - RoutingArch->Fs = Arch.Fs; - RoutingArch->subFs = Arch.subFs; - RoutingArch->directionality = BI_DIRECTIONAL; + t_det_routing_arch& RoutingArch) { + RoutingArch.switch_block_type = Arch.SBType; + RoutingArch.switch_block_subtype = Arch.SBSubType; + RoutingArch.R_minW_nmos = Arch.R_minW_nmos; + RoutingArch.R_minW_pmos = Arch.R_minW_pmos; + RoutingArch.Fs = Arch.Fs; + RoutingArch.subFs = Arch.subFs; + RoutingArch.directionality = BI_DIRECTIONAL; if (!Arch.Segments.empty()) { - RoutingArch->directionality = Arch.Segments[0].directionality; + RoutingArch.directionality = Arch.Segments[0].directionality; } /* copy over the switch block information */ - RoutingArch->switchblocks = Arch.switchblocks; + RoutingArch.switchblocks = Arch.switchblocks; /* Copy the tileable routing setting */ - RoutingArch->tileable = Arch.tileable; - RoutingArch->perimeter_cb = Arch.perimeter_cb; - RoutingArch->shrink_boundary = Arch.shrink_boundary; - RoutingArch->through_channel = Arch.through_channel; - RoutingArch->opin2all_sides = Arch.opin2all_sides; - RoutingArch->concat_wire = Arch.concat_wire; - RoutingArch->concat_pass_wire = Arch.concat_pass_wire; + RoutingArch.tileable = Arch.tileable; + RoutingArch.perimeter_cb = Arch.perimeter_cb; + RoutingArch.shrink_boundary = Arch.shrink_boundary; + RoutingArch.through_channel = Arch.through_channel; + RoutingArch.opin2all_sides = Arch.opin2all_sides; + RoutingArch.concat_wire = Arch.concat_wire; + RoutingArch.concat_pass_wire = Arch.concat_pass_wire; } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { @@ -457,6 +456,12 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->astar_fac = Options.astar_fac; RouterOpts->astar_offset = Options.astar_offset; RouterOpts->router_profiler_astar_fac = Options.router_profiler_astar_fac; + RouterOpts->enable_parallel_connection_router = Options.enable_parallel_connection_router; + RouterOpts->post_target_prune_fac = Options.post_target_prune_fac; + RouterOpts->post_target_prune_offset = Options.post_target_prune_offset; + RouterOpts->multi_queue_num_threads = Options.multi_queue_num_threads; + RouterOpts->multi_queue_num_queues = Options.multi_queue_num_queues; + RouterOpts->multi_queue_direct_draining = Options.multi_queue_direct_draining; RouterOpts->bb_factor = Options.bb_factor; RouterOpts->criticality_exp = Options.criticality_exp; RouterOpts->max_criticality = Options.max_criticality; @@ -581,6 +586,8 @@ void SetupAPOpts(const t_options& options, apOpts.full_legalizer_type = options.ap_full_legalizer.value(); apOpts.detailed_placer_type = options.ap_detailed_placer.value(); apOpts.ap_timing_tradeoff = options.ap_timing_tradeoff.value(); + apOpts.appack_max_dist_th = options.appack_max_dist_th.value(); + apOpts.num_threads = options.num_workers.value(); apOpts.log_verbosity = options.ap_verbosity.value(); } @@ -601,15 +608,12 @@ void SetupPackerOpts(const t_options& Options, PackerOpts->doPacking = STAGE_DO; } - //TODO: document? - PackerOpts->global_clocks = true; /* DEFAULT */ - PackerOpts->allow_unrelated_clustering = Options.allow_unrelated_clustering; PackerOpts->connection_driven = Options.connection_driven_clustering; PackerOpts->timing_driven = Options.timing_driven_clustering; PackerOpts->cluster_seed_type = Options.cluster_seed_type; - PackerOpts->alpha = Options.alpha_clustering; - PackerOpts->beta = Options.beta_clustering; + PackerOpts->timing_gain_weight = Options.timing_gain_weight; + PackerOpts->connection_gain_weight = Options.connection_gain_weight; PackerOpts->pack_verbosity = Options.pack_verbosity; PackerOpts->enable_pin_feasibility_filter = Options.enable_clustering_pin_feasibility_filter; PackerOpts->balance_block_type_utilization = Options.balance_block_type_utilization; @@ -619,13 +623,10 @@ void SetupPackerOpts(const t_options& Options, PackerOpts->high_fanout_threshold = Options.pack_high_fanout_threshold; PackerOpts->transitive_fanout_threshold = Options.pack_transitive_fanout_threshold; PackerOpts->feasible_block_array_size = Options.pack_feasible_block_array_size; - PackerOpts->use_attraction_groups = Options.use_attraction_groups; PackerOpts->device_layout = Options.device_layout; PackerOpts->timing_update_type = Options.timing_update_type; - PackerOpts->pack_num_moves = Options.pack_num_moves; - PackerOpts->pack_move_type = Options.pack_move_type; } static void SetupNetlistOpts(const t_options& Options, t_netlist_opts& NetlistOpts) { @@ -700,7 +701,6 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts) PlacerOpts->effort_scaling = Options.place_effort_scaling; PlacerOpts->timing_update_type = Options.timing_update_type; - PlacerOpts->enable_analytic_placer = Options.enable_analytic_placer; PlacerOpts->place_static_move_prob = vtr::vector(Options.place_static_move_prob.value().begin(), Options.place_static_move_prob.value().end()); PlacerOpts->place_high_fanout_net = Options.place_high_fanout_net; @@ -734,6 +734,7 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.gen_post_synthesis_netlist = Options.Generate_Post_Synthesis_Netlist; analysis_opts.gen_post_implementation_merged_netlist = Options.Generate_Post_Implementation_Merged_Netlist; + analysis_opts.gen_post_implementation_sdc = Options.generate_post_implementation_sdc.value(); analysis_opts.timing_report_npaths = Options.timing_report_npaths; analysis_opts.timing_report_detail = Options.timing_report_detail; @@ -742,11 +743,12 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.post_synth_netlist_unconn_input_handling = Options.post_synth_netlist_unconn_input_handling; analysis_opts.post_synth_netlist_unconn_output_handling = Options.post_synth_netlist_unconn_output_handling; + analysis_opts.post_synth_netlist_module_parameters = Options.post_synth_netlist_module_parameters.value(); analysis_opts.timing_update_type = Options.timing_update_type; analysis_opts.write_timing_summary = Options.write_timing_summary; - analysis_opts.skip_sync_clustering_and_routing_results = Options.skip_sync_clustering_and_routing_results; + analysis_opts.generate_net_timing_report = Options.generate_net_timing_report; } static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch) { diff --git a/vpr/src/base/SetupVPR.h b/vpr/src/base/SetupVPR.h index 45bf510c18c..7470a1fd0c8 100644 --- a/vpr/src/base/SetupVPR.h +++ b/vpr/src/base/SetupVPR.h @@ -1,7 +1,6 @@ #ifndef SETUPVPR_H #define SETUPVPR_H #include -#include "logic_types.h" #include "read_options.h" #include "physical_types.h" #include "vpr_types.h" @@ -11,8 +10,6 @@ void SetupVPR(const t_options* Options, const bool readArchFile, t_file_name_opts* FileNameOpts, t_arch* Arch, - t_model** user_models, - t_model** library_models, t_netlist_opts* NetlistOpts, t_packer_opts* PackerOpts, t_placer_opts* PlacerOpts, @@ -21,7 +18,7 @@ void SetupVPR(const t_options* Options, t_analysis_opts* AnalysisOpts, t_noc_opts* NocOpts, t_server_opts* ServerOpts, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, std::vector** PackerRRGraphs, std::vector& Segments, t_timing_inf* Timing, diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index f21200e97ee..ccf900f8ef8 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -135,7 +135,7 @@ ClusteredNetlistStats::ClusteredNetlistStats() { auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); auto physical_tile = pick_physical_type(logical_block); num_blocks_type[logical_block->index]++; - if (is_io_type(physical_tile)) { + if (physical_tile->is_io()) { for (int j = 0; j < logical_block->pb_type->num_pins; j++) { int physical_pin = get_physical_pin(physical_tile, logical_block, j); @@ -379,6 +379,12 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) { VTR_LOG("RouterOpts.astar_fac: %f\n", RouterOpts.astar_fac); VTR_LOG("RouterOpts.astar_offset: %f\n", RouterOpts.astar_offset); VTR_LOG("RouterOpts.router_profiler_astar_fac: %f\n", RouterOpts.router_profiler_astar_fac); + VTR_LOG("RouterOpts.enable_parallel_connection_router: %s\n", RouterOpts.enable_parallel_connection_router ? "true" : "false"); + VTR_LOG("RouterOpts.post_target_prune_fac: %f\n", RouterOpts.post_target_prune_fac); + VTR_LOG("RouterOpts.post_target_prune_offset: %f\n", RouterOpts.post_target_prune_offset); + VTR_LOG("RouterOpts.multi_queue_num_threads: %d\n", RouterOpts.multi_queue_num_threads); + VTR_LOG("RouterOpts.multi_queue_num_queues: %d\n", RouterOpts.multi_queue_num_queues); + VTR_LOG("RouterOpts.multi_queue_direct_draining: %s\n", RouterOpts.multi_queue_direct_draining ? "true" : "false"); VTR_LOG("RouterOpts.criticality_exp: %f\n", RouterOpts.criticality_exp); VTR_LOG("RouterOpts.max_criticality: %f\n", RouterOpts.max_criticality); VTR_LOG("RouterOpts.init_wirelength_abort_threshold: %f\n", RouterOpts.init_wirelength_abort_threshold); @@ -671,6 +677,8 @@ static void ShowNetlistOpts(const t_netlist_opts& NetlistOpts) { static void ShowAnalysisOpts(const t_analysis_opts& AnalysisOpts) { VTR_LOG("AnalysisOpts.gen_post_synthesis_netlist: %s\n", (AnalysisOpts.gen_post_synthesis_netlist) ? "true" : "false"); + VTR_LOG("AnalysisOpts.gen_post_implementation_merged_netlist: %s\n", AnalysisOpts.gen_post_implementation_merged_netlist ? "true" : "false"); + VTR_LOG("AnalysisOpts.gen_post_implementation_sdc: %s\n", AnalysisOpts.gen_post_implementation_sdc ? "true" : "false"); VTR_LOG("AnalysisOpts.timing_report_npaths: %d\n", AnalysisOpts.timing_report_npaths); VTR_LOG("AnalysisOpts.timing_report_skew: %s\n", AnalysisOpts.timing_report_skew ? "true" : "false"); VTR_LOG("AnalysisOpts.echo_dot_timing_graph_node: %s\n", AnalysisOpts.echo_dot_timing_graph_node.c_str()); @@ -717,6 +725,7 @@ static void ShowAnalysisOpts(const t_analysis_opts& AnalysisOpts) { VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown post_synth_netlist_unconn_handling\n"); } } + VTR_LOG("AnalysisOpts.post_synth_netlist_module_parameters: %s\n", AnalysisOpts.post_synth_netlist_module_parameters ? "on" : "off"); VTR_LOG("\n"); } @@ -731,8 +740,8 @@ static void ShowPackerOpts(const t_packer_opts& PackerOpts) { } else { VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown packer allow_unrelated_clustering\n"); } - VTR_LOG("PackerOpts.alpha_clustering: %f\n", PackerOpts.alpha); - VTR_LOG("PackerOpts.beta_clustering: %f\n", PackerOpts.beta); + VTR_LOG("PackerOpts.timing_gain_weight: %f\n", PackerOpts.timing_gain_weight); + VTR_LOG("PackerOpts.connection_gain_weight: %f\n", PackerOpts.connection_gain_weight); VTR_LOG("PackerOpts.cluster_seed_type: "); switch (PackerOpts.cluster_seed_type) { case e_cluster_seed::TIMING: @@ -757,7 +766,6 @@ static void ShowPackerOpts(const t_packer_opts& PackerOpts) { VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown packer cluster_seed_type\n"); } VTR_LOG("PackerOpts.connection_driven: %s", (PackerOpts.connection_driven ? "true\n" : "false\n")); - VTR_LOG("PackerOpts.global_clocks: %s", (PackerOpts.global_clocks ? "true\n" : "false\n")); VTR_LOG("PackerOpts.timing_driven: %s", (PackerOpts.timing_driven ? "true\n" : "false\n")); VTR_LOG("PackerOpts.target_external_pin_util: %s", vtr::join(PackerOpts.target_external_pin_util, " ").c_str()); VTR_LOG("\n"); diff --git a/vpr/src/base/atom_lookup.h b/vpr/src/base/atom_lookup.h index 8a218fae207..0eedbc7dc41 100644 --- a/vpr/src/base/atom_lookup.h +++ b/vpr/src/base/atom_lookup.h @@ -2,15 +2,11 @@ #define ATOM_LOOKUP_H #include "atom_lookup_fwd.h" -#include - -#include "vtr_bimap.h" #include "vtr_vector_map.h" #include "vtr_range.h" #include "atom_netlist_fwd.h" #include "clustered_netlist_fwd.h" -#include "vpr_types.h" #include "tatum/TimingGraphFwd.hpp" #include "vtr_optional.h" diff --git a/vpr/src/base/atom_netlist.cpp b/vpr/src/base/atom_netlist.cpp index 1cbd2232f1f..c0453db3c65 100644 --- a/vpr/src/base/atom_netlist.cpp +++ b/vpr/src/base/atom_netlist.cpp @@ -1,13 +1,10 @@ -#include #include -#include -#include #include "atom_netlist.h" - -#include "vtr_assert.h" -#include "vtr_log.h" +#include "logic_types.h" +#include "netlist_utils.h" #include "vpr_error.h" +#include "vtr_assert.h" /* * @@ -18,27 +15,27 @@ */ AtomNetlist::AtomNetlist(std::string name, std::string id) : Netlist(name, id) - , inpad_model_(nullptr) - , outpad_model_(nullptr) {} + , inpad_model_(LogicalModelId::INVALID()) + , outpad_model_(LogicalModelId::INVALID()) {} /* * * Blocks * */ -void AtomNetlist::set_block_types(const t_model* inpad, const t_model* outpad) { - VTR_ASSERT(inpad != nullptr); - VTR_ASSERT(outpad != nullptr); +void AtomNetlist::set_block_types(LogicalModelId inpad, LogicalModelId outpad) { + VTR_ASSERT(inpad.is_valid()); + VTR_ASSERT(outpad.is_valid()); inpad_model_ = inpad; outpad_model_ = outpad; } AtomBlockType AtomNetlist::block_type(const AtomBlockId id) const { - VTR_ASSERT(inpad_model_ != nullptr); - VTR_ASSERT(outpad_model_ != nullptr); + VTR_ASSERT(inpad_model_.is_valid()); + VTR_ASSERT(outpad_model_.is_valid()); - const t_model* blk_model = block_model(id); + LogicalModelId blk_model = block_model(id); AtomBlockType type = AtomBlockType::BLOCK; if (blk_model == inpad_model_) { @@ -51,7 +48,7 @@ AtomBlockType AtomNetlist::block_type(const AtomBlockId id) const { return type; } -const t_model* AtomNetlist::block_model(const AtomBlockId id) const { +LogicalModelId AtomNetlist::block_model(const AtomBlockId id) const { VTR_ASSERT_SAFE(valid_block_id(id)); return block_models_[id]; @@ -137,7 +134,7 @@ std::unordered_set AtomNetlist::net_aliases(const std::string& net_ * Mutators * */ -AtomBlockId AtomNetlist::create_block(const std::string& name, const t_model* model, const TruthTable& truth_table) { +AtomBlockId AtomNetlist::create_block(const std::string& name, LogicalModelId model, const TruthTable& truth_table) { AtomBlockId blk_id = Netlist::create_block(name); //Initialize the data diff --git a/vpr/src/base/atom_netlist.h b/vpr/src/base/atom_netlist.h index b40e18d2d18..639af85c428 100644 --- a/vpr/src/base/atom_netlist.h +++ b/vpr/src/base/atom_netlist.h @@ -68,7 +68,6 @@ #include #include -#include "vtr_range.h" #include "vtr_logic.h" #include "vtr_vector_map.h" @@ -97,13 +96,13 @@ class AtomNetlist : public Netlist block_models_; //Architecture model of each block + vtr::vector_map block_models_; //Architecture model of each block vtr::vector_map block_truth_tables_; //Truth tables of each block // Input IOs and output IOs always exist and have their own architecture @@ -270,8 +269,8 @@ class AtomNetlist : public Netlist port_models_; //Architecture port models of each port diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index 5172db9261a..a56ea9ceb44 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -1,16 +1,16 @@ #include "atom_netlist_utils.h" -#include #include #include #include #include #include +#include "logic_types.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vpr_error.h" -#include "vpr_utils.h" +#include "vtr_vector_map.h" /** * @brief Marks primitive output pins constant if all inputs to the block are constant @@ -18,15 +18,15 @@ * Since marking one block constant may cause a downstream block to also be constant, * marking is repated until there is no further change */ -int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, int verbosity); +int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity); ///@brief Marks all primtive output pins which have no combinationally connected inputs as constant pins int mark_undriven_primitive_outputs_as_constant(AtomNetlist& netlist, int verbosity); ///@brief Marks all primtive output pins of blk which have only constant inputs as constant pins -int infer_and_mark_block_pins_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, int verbosity); +int infer_and_mark_block_pins_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity); int infer_and_mark_block_combinational_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, int verbosity); -int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, int verbosity); +int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity); ///@brief Returns the set of input ports which are combinationally connected to output_port std::vector find_combinationally_connected_input_ports(const AtomNetlist& netlist, AtomPortId output_port); @@ -34,27 +34,27 @@ std::vector find_combinationally_connected_input_ports(const AtomNet ///@brief Returns the set of clock ports which are combinationally connected to output_port std::vector find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port); -bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk); -bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); -bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); +bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models); +bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr); +bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr); bool is_removable_output(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); /** * @brief Attempts to remove the specified buffer LUT blk from the netlist. * @return true if successful */ -bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity); +bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, const LogicalModels& models, int verbosity); std::string make_unconn(size_t& unconn_count, PinType type); void cube_to_minterms_recurr(std::vector cube, std::vector& minterms); -void print_netlist_as_blif(std::string filename, const AtomNetlist& netlist) { +void print_netlist_as_blif(std::string filename, const AtomNetlist& netlist, const LogicalModels& models) { FILE* f = std::fopen(filename.c_str(), "w"); - print_netlist_as_blif(f, netlist); + print_netlist_as_blif(f, netlist, models); std::fclose(f); } -void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { +void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalModels& models) { constexpr const char* INDENT = " "; size_t unconn_count = 0; @@ -137,10 +137,11 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { } //Latch + LogicalModelId latch_model = models.get_model_by_name(LogicalModels::MODEL_LATCH); for (auto blk_id : netlist.blocks()) { if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) { - const t_model* blk_model = netlist.block_model(blk_id); - if (blk_model->name != std::string(MODEL_LATCH)) continue; + LogicalModelId blk_model = netlist.block_model(blk_id); + if (blk_model != latch_model) continue; //Nets std::string d_net; @@ -224,10 +225,11 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { } //Names + LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES); for (auto blk_id : netlist.blocks()) { if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) { - const t_model* blk_model = netlist.block_model(blk_id); - if (blk_model->name != std::string(MODEL_NAMES)) continue; + LogicalModelId blk_model = netlist.block_model(blk_id); + if (blk_model != names_model) continue; std::vector nets; @@ -290,14 +292,15 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { } //Subckt - - std::set subckt_models; + LogicalModelId input_model = models.get_model_by_name(LogicalModels::MODEL_INPUT); + LogicalModelId output_model = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); + std::set subckt_models; for (auto blk_id : netlist.blocks()) { - const t_model* blk_model = netlist.block_model(blk_id); - if (blk_model->name == std::string(MODEL_LATCH) - || blk_model->name == std::string(MODEL_NAMES) - || blk_model->name == std::string(MODEL_INPUT) - || blk_model->name == std::string(MODEL_OUTPUT)) { + LogicalModelId blk_model = netlist.block_model(blk_id); + if (blk_model == latch_model + || blk_model == names_model + || blk_model == input_model + || blk_model == output_model) { continue; } @@ -363,11 +366,12 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { fprintf(f, "\n"); //The subckt models - for (const t_model* model : subckt_models) { - fprintf(f, ".model %s\n", model->name); + for (LogicalModelId model_id : subckt_models) { + const t_model& model = models.get_model(model_id); + fprintf(f, ".model %s\n", model.name); fprintf(f, ".inputs"); - const t_model_ports* port = model->inputs; + const t_model_ports* port = model.inputs; while (port) { VTR_ASSERT(port->size >= 0); if (port->size == 1) { @@ -384,7 +388,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { fprintf(f, "\n"); fprintf(f, ".outputs"); - port = model->outputs; + port = model.outputs; while (port) { VTR_ASSERT(port->size >= 0); if (port->size == 1) { @@ -407,26 +411,11 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) { } } -std::string atom_pin_arch_name(const AtomNetlist& netlist, const AtomPinId pin) { - std::string arch_name; - - AtomBlockId blk = netlist.pin_block(pin); - AtomPortId port = netlist.pin_port(pin); - arch_name += netlist.block_model(blk)->name; - arch_name += "."; - arch_name += netlist.port_model(port)->name; - arch_name += "["; - arch_name += std::to_string(netlist.pin_port_bit(pin)); - arch_name += "]"; - - return arch_name; -} - -int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, int verbosity) { +int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) { int num_undriven_pins_marked_const = mark_undriven_primitive_outputs_as_constant(netlist, verbosity); VTR_LOGV(verbosity > 0, "Inferred %4d additional primitive pins as constant generators since they have no combinationally connected inputs\n", num_undriven_pins_marked_const); - int num_inferred_pins_marked_const = infer_and_mark_constant_pins(netlist, const_gen_inference_method, verbosity); + int num_inferred_pins_marked_const = infer_and_mark_constant_pins(netlist, const_gen_inference_method, models, verbosity); VTR_LOGV(verbosity > 0, "Inferred %4d additional primitive pins as constant generators due to constant inputs\n", num_inferred_pins_marked_const); return num_undriven_pins_marked_const + num_inferred_pins_marked_const; @@ -489,7 +478,7 @@ int mark_undriven_primitive_outputs_as_constant(AtomNetlist& netlist, int verbos return num_pins_marked_constant; } -int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, int verbosity) { +int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) { size_t num_pins_inferred_constant = 0; //It is possible that by marking one constant generator @@ -505,7 +494,7 @@ int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference con for (auto blk : netlist.blocks()) { if (!blk) continue; - num_pins_marked += infer_and_mark_block_pins_constant(netlist, blk, const_gen_inference_method, verbosity); + num_pins_marked += infer_and_mark_block_pins_constant(netlist, blk, const_gen_inference_method, models, verbosity); } num_pins_inferred_constant += num_pins_marked; @@ -514,12 +503,12 @@ int infer_and_mark_constant_pins(AtomNetlist& netlist, e_const_gen_inference con return num_pins_inferred_constant; } -int infer_and_mark_block_pins_constant(AtomNetlist& netlist, AtomBlockId block, e_const_gen_inference const_gen_inference_method, int verbosity) { +int infer_and_mark_block_pins_constant(AtomNetlist& netlist, AtomBlockId block, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) { size_t num_pins_marked_constant = 0; num_pins_marked_constant += infer_and_mark_block_combinational_outputs_constant(netlist, block, const_gen_inference_method, verbosity); - num_pins_marked_constant += infer_and_mark_block_sequential_outputs_constant(netlist, block, const_gen_inference_method, verbosity); + num_pins_marked_constant += infer_and_mark_block_sequential_outputs_constant(netlist, block, const_gen_inference_method, models, verbosity); return num_pins_marked_constant; } @@ -581,7 +570,7 @@ int infer_and_mark_block_combinational_outputs_constant(AtomNetlist& netlist, At return num_pins_marked_constant; } -int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, int verbosity) { +int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomBlockId blk, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity) { //Only if sequential constant generator inference enabled if (const_gen_inference_method != e_const_gen_inference::COMB_SEQ) { return 0; @@ -639,7 +628,7 @@ int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomB VTR_LOGV(verbosity > 1, "Marking sequential pin '%s' as constant since all inputs to block '%s' (%s) are constant\n", netlist.pin_name(output_pin).c_str(), netlist.block_name(blk).c_str(), - netlist.block_model(blk)->name); + models.get_model(netlist.block_model(blk)).name); netlist.set_pin_is_constant(output_pin, true); ++num_pins_marked_constant; } @@ -692,7 +681,7 @@ std::vector find_combinationally_connected_clock_ports(const AtomNet return upstream_ports; } -void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { +void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int verbosity) { //First we look through the netlist to find LUTs with identity logic functions //we then remove those luts, replacing the net's they drove with the inputs to the //buffer lut @@ -701,8 +690,8 @@ void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { //Remove the buffer luts for (auto blk : netlist.blocks()) { - if (is_buffer_lut(netlist, blk)) { - if (remove_buffer_lut(netlist, blk, verbosity)) { + if (is_buffer_lut(netlist, blk, models)) { + if (remove_buffer_lut(netlist, blk, models, verbosity)) { ++removed_buffer_count; } } @@ -712,11 +701,10 @@ void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { //TODO: absorb inverter LUTs? } -bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk) { +bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models) { if (netlist.block_type(blk) == AtomBlockType::BLOCK) { - const t_model* blk_model = netlist.block_model(blk); - - if (blk_model->name != std::string(MODEL_NAMES)) return false; + const LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES); + if (netlist.block_model(blk) != names_model) return false; auto input_ports = netlist.block_input_ports(blk); auto output_ports = netlist.block_output_ports(blk); @@ -773,7 +761,7 @@ bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk) { return false; } -bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { +bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, const LogicalModels& models, int verbosity) { //General net connectivity, numbers equal pin ids // // 1 in 2 ----- m+1 out @@ -822,13 +810,23 @@ bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { auto input_net = netlist.pin_net(input_pin); auto output_net = netlist.pin_net(output_pin); - VTR_LOGV_WARN(verbosity > 1, "Attempting to remove buffer '%s' (%s) from net '%s' to net '%s'\n", netlist.block_name(blk).c_str(), netlist.block_model(blk)->name, netlist.net_name(input_net).c_str(), netlist.net_name(output_net).c_str()); + VTR_LOGV_WARN(verbosity > 1, + "Attempting to remove buffer '%s' (%s) from net '%s' to net '%s'\n", + netlist.block_name(blk).c_str(), + models.model_name(netlist.block_model(blk)).c_str(), + netlist.net_name(input_net).c_str(), + netlist.net_name(output_net).c_str()); //Collect the new driver and sink pins AtomPinId new_driver = netlist.net_driver(input_net); if (!new_driver) { - VTR_LOGV_WARN(verbosity > 2, "Buffer '%s' has no input and will not be absorbed (left to be swept)\n", netlist.block_name(blk).c_str(), netlist.block_model(blk)->name, netlist.net_name(input_net).c_str(), netlist.net_name(output_net).c_str()); + VTR_LOGV_WARN(verbosity > 2, + "Buffer '%s' has no input and will not be absorbed (left to be swept)\n", + netlist.block_name(blk).c_str(), + models.model_name(netlist.block_model(blk)).c_str(), + netlist.net_name(input_net).c_str(), + netlist.net_name(output_net).c_str()); return false; //Dangling/undriven input, leave buffer to be swept } @@ -909,7 +907,7 @@ bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { return true; } -bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk_id, std::string* reason) { +bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk_id, const LogicalModels& models, std::string* reason) { //Any block with no fanout is removable for (AtomPinId pin_id : netlist.block_output_pins(blk_id)) { if (!pin_id) continue; @@ -923,7 +921,7 @@ bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk_id, st //If the model relative to this block is has the never prune flag set //it cannot be removed, even if it does not have a fanout auto blk_model = netlist.block_model(blk_id); - if (blk_model->never_prune == true) { + if (models.get_model(blk_model).never_prune == true) { return false; } @@ -931,13 +929,13 @@ bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk_id, st return true; } -bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk_id, std::string* reason) { +bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk_id, const LogicalModels& models, std::string* reason) { AtomBlockType type = netlist.block_type(blk_id); //Only return true if an INPAD if (type != AtomBlockType::INPAD) return false; - return is_removable_block(netlist, blk_id, reason); + return is_removable_block(netlist, blk_id, models, reason); } bool is_removable_output(const AtomNetlist& netlist, const AtomBlockId blk_id, std::string* reason) { @@ -996,6 +994,7 @@ size_t sweep_iterative(AtomNetlist& netlist, bool should_sweep_blocks, bool should_sweep_constant_primary_outputs, e_const_gen_inference const_gen_inference_method, + const LogicalModels& models, int verbosity) { size_t dangling_nets_swept = 0; size_t dangling_blocks_swept = 0; @@ -1023,12 +1022,12 @@ size_t sweep_iterative(AtomNetlist& netlist, pass_constant_generators_marked = 0; if (should_sweep_ios) { - pass_dangling_inputs_swept += sweep_inputs(netlist, verbosity); + pass_dangling_inputs_swept += sweep_inputs(netlist, models, verbosity); pass_dangling_outputs_swept += sweep_outputs(netlist, verbosity); } if (should_sweep_blocks) { - pass_dangling_blocks_swept += sweep_blocks(netlist, verbosity); + pass_dangling_blocks_swept += sweep_blocks(netlist, models, verbosity); } if (should_sweep_nets) { @@ -1039,7 +1038,7 @@ size_t sweep_iterative(AtomNetlist& netlist, pass_constant_outputs_swept += sweep_constant_primary_outputs(netlist, verbosity); } - pass_constant_generators_marked += mark_constant_generators(netlist, const_gen_inference_method, verbosity); + pass_constant_generators_marked += mark_constant_generators(netlist, const_gen_inference_method, models, verbosity); dangling_nets_swept += pass_dangling_nets_swept; dangling_blocks_swept += pass_dangling_blocks_swept; @@ -1070,7 +1069,7 @@ size_t sweep_iterative(AtomNetlist& netlist, + constant_outputs_swept; } -size_t sweep_blocks(AtomNetlist& netlist, int verbosity) { +size_t sweep_blocks(AtomNetlist& netlist, const LogicalModels& models, int verbosity) { //Identify any blocks (not inputs or outputs) for removal std::unordered_set blocks_to_remove; for (auto blk_id : netlist.blocks()) { @@ -1083,7 +1082,7 @@ size_t sweep_blocks(AtomNetlist& netlist, int verbosity) { //We remove any blocks with no fanout std::string reason; - if (is_removable_block(netlist, blk_id, &reason)) { + if (is_removable_block(netlist, blk_id, models, &reason)) { blocks_to_remove.insert(blk_id); VTR_LOGV_WARN(verbosity > 1, "Block '%s' will be swept (%s)\n", netlist.block_name(blk_id).c_str(), reason.c_str()); @@ -1098,14 +1097,14 @@ size_t sweep_blocks(AtomNetlist& netlist, int verbosity) { return blocks_to_remove.size(); } -size_t sweep_inputs(AtomNetlist& netlist, int verbosity) { +size_t sweep_inputs(AtomNetlist& netlist, const LogicalModels& models, int verbosity) { //Identify any inputs for removal std::unordered_set inputs_to_remove; for (auto blk_id : netlist.blocks()) { if (!blk_id) continue; std::string reason; - if (is_removable_input(netlist, blk_id, &reason)) { + if (is_removable_input(netlist, blk_id, models, &reason)) { inputs_to_remove.insert(blk_id); VTR_LOGV_WARN(verbosity > 1, "Primary input '%s' will be swept (%s)\n", netlist.block_name(blk_id).c_str(), reason.c_str()); @@ -1333,10 +1332,10 @@ void cube_to_minterms_recurr(std::vector cube, std::vector find_netlist_physical_clock_nets(const AtomNetlist& netlist) { +std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist, const LogicalModels& models) { std::set clock_nets; //The clock nets - std::map> clock_gen_ports; //Records info about clock generating ports + vtr::vector_map> clock_gen_ports; //Records info about clock generating ports //Look through all the blocks (except I/Os) to find sink clock pins, or //clock generators @@ -1350,18 +1349,19 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) if (type != AtomBlockType::BLOCK) continue; //Save any clock generating ports on this model type - const t_model* model = netlist.block_model(blk_id); - VTR_ASSERT(model); - if (clock_gen_ports.find(model) == clock_gen_ports.end()) { + LogicalModelId model_id = netlist.block_model(blk_id); + VTR_ASSERT(model_id.is_valid()); + if (clock_gen_ports.find(model_id) == clock_gen_ports.end()) { //First time we've seen this model, initialize it - clock_gen_ports[model] = {}; + clock_gen_ports.insert(model_id, {}); //Look at all the ports to find clock generators - for (const t_model_ports* model_port = model->outputs; model_port; model_port = model_port->next) { + const t_model& model = models.get_model(model_id); + for (const t_model_ports* model_port = model.outputs; model_port; model_port = model_port->next) { VTR_ASSERT(model_port->dir == OUT_PORT); if (model_port->is_clock) { //Clock generator - clock_gen_ports[model].push_back(model_port); + clock_gen_ports[model_id].push_back(model_port); } } } @@ -1377,11 +1377,11 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) } //Look for any generated clocks - if (!clock_gen_ports[model].empty()) { + if (!clock_gen_ports[model_id].empty()) { //This is a clock generator //Check all the clock generating ports - for (const t_model_ports* model_port : clock_gen_ports[model]) { + for (const t_model_ports* model_port : clock_gen_ports[model_id]) { AtomPortId clk_gen_port = netlist.find_atom_port(blk_id, model_port); if (!clk_gen_port) continue; //Port not connected on this block @@ -1402,8 +1402,8 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) } ///@brief Finds all logical clock drivers in the netlist (by back-tracing through logic) -std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist) { - std::set clock_nets = find_netlist_physical_clock_nets(netlist); +std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist, const LogicalModels& models) { + std::set clock_nets = find_netlist_physical_clock_nets(netlist, models); //We now have a set of nets which drive clock pins // @@ -1412,6 +1412,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis //to find the true source size_t assumed_buffer_count = 0; std::set prev_clock_nets; + LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); while (prev_clock_nets != clock_nets) { //Still tracing back prev_clock_nets = clock_nets; clock_nets.clear(); @@ -1423,7 +1424,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis std::vector upstream_ports; - if (netlist.block_model(driver_blk)->name == std::string(".names")) { + if (netlist.block_model(driver_blk) == names_model_id) { //For .names we allow tracing back through data connections //which allows us to traceback through white-box .names buffers upstream_ports = find_combinationally_connected_input_ports(netlist, driver_port); @@ -1448,7 +1449,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis VTR_ASSERT(upstream_net); VTR_LOG_WARN("Assuming clocks may propagate through %s (%s) from pin %s to %s (assuming a non-inverting buffer).\n", - netlist.block_name(driver_blk).c_str(), netlist.block_model(driver_blk)->name, + netlist.block_name(driver_blk).c_str(), models.model_name(netlist.block_model(driver_blk)).c_str(), netlist.pin_name(upstream_pin).c_str(), netlist.pin_name(driver_pin).c_str()); clock_nets.insert(upstream_net); @@ -1483,8 +1484,8 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis } ///@brief Print information about clocks -void print_netlist_clock_info(const AtomNetlist& netlist) { - std::set netlist_clock_drivers = find_netlist_logical_clock_drivers(netlist); +void print_netlist_clock_info(const AtomNetlist& netlist, const LogicalModels& models) { + std::set netlist_clock_drivers = find_netlist_logical_clock_drivers(netlist, models); VTR_LOG("Netlist contains %zu clocks\n", netlist_clock_drivers.size()); //Print out pin/block fanout info for each block @@ -1500,9 +1501,3 @@ void print_netlist_clock_info(const AtomNetlist& netlist) { VTR_LOG(" Netlist Clock '%s' Fanout: %zu pins (%.1f%%), %zu blocks (%.1f%%)\n", netlist.net_name(net_id).c_str(), fanout, 100. * float(fanout) / netlist.pins().size(), clk_blks.size(), 100 * float(clk_blks.size()) / netlist.blocks().size()); } } - -bool is_buffer(const AtomNetlist& netlist, const AtomBlockId blk) { - //For now only support LUT buffers - //TODO: In the future could add support for non-LUT buffers - return is_buffer_lut(netlist, blk); -} diff --git a/vpr/src/base/atom_netlist_utils.h b/vpr/src/base/atom_netlist_utils.h index aaa559d4a73..5bf0791bfad 100644 --- a/vpr/src/base/atom_netlist_utils.h +++ b/vpr/src/base/atom_netlist_utils.h @@ -9,16 +9,18 @@ * @brief Useful utilities for working with the AtomNetlist class */ +class LogicalModels; + /** * @brief Walk through the netlist detecting constant generators * * @note Initial constant generators (e.g. vcc/gnd) should have already * been marked on the netlist. */ -int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, int verbosity); +int mark_constant_generators(AtomNetlist& netlist, e_const_gen_inference const_gen_inference_method, const LogicalModels& models, int verbosity); ///@brief Modifies the netlist by absorbing buffer LUTs -void absorb_buffer_luts(AtomNetlist& netlist, int verbosity); +void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int verbosity); /* * Modify the netlist by sweeping away unused nets/blocks/inputs @@ -35,16 +37,17 @@ size_t sweep_iterative(AtomNetlist& netlist, bool should_sweep_dangling_nets, bool should_sweep_constant_primary_outputs, e_const_gen_inference const_gen_inference_method, + const LogicalModels& models, int verbosity); ///@brief Sweeps blocks that have no fanout -size_t sweep_blocks(AtomNetlist& netlist, int verbosity); +size_t sweep_blocks(AtomNetlist& netlist, const LogicalModels& models, int verbosity); ///@brief Sweeps nets with no drivers and/or no sinks size_t sweep_nets(AtomNetlist& netlist, int verbosity); ///@brief Sweeps primary-inputs with no fanout -size_t sweep_inputs(AtomNetlist& netlist, int verbosity); +size_t sweep_inputs(AtomNetlist& netlist, const LogicalModels& models, int verbosity); ///@brief Sweeps primary-outputs with no fanin size_t sweep_outputs(AtomNetlist& netlist, int verbosity); @@ -55,9 +58,6 @@ size_t sweep_constant_primary_outputs(AtomNetlist& netlist, int verbosity); * Truth-table operations */ -///@brief Returns true if the specified block is a logical buffer -bool is_buffer(const AtomNetlist& netlist, const AtomBlockId blk); - /** * @brief Deterimine whether a truth table encodes the logic functions 'On' set (returns true) * or 'Off' set (returns false) @@ -96,11 +96,8 @@ std::vector cube_to_minterms(std::vector cube); /* * Print the netlist for debugging */ -void print_netlist_as_blif(std::string filename, const AtomNetlist& netlist); -void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist); - -///@brief Returns a user-friendly architectural identifier for the specified atom pin -std::string atom_pin_arch_name(const AtomNetlist& netlist, const AtomPinId pin); +void print_netlist_as_blif(std::string filename, const AtomNetlist& netlist, const LogicalModels& models); +void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalModels& models); /* * Identify all clock nets @@ -112,7 +109,7 @@ std::string atom_pin_arch_name(const AtomNetlist& netlist, const AtomPinId pin); * @note The returned nets may be logically equivalent (e.g. driven by buffers * connected to a common net) */ -std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist); +std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist, const LogicalModels& models); /** * @brief Returns the set of pins which logically drive unique clocks in the netlist @@ -121,8 +118,8 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) * so logically unique should be viewed as true only to the extent of VPR's * understanding */ -std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist); +std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist, const LogicalModels& models); ///@brief Prints out information about netlist clocks -void print_netlist_clock_info(const AtomNetlist& netlist); +void print_netlist_clock_info(const AtomNetlist& netlist, const LogicalModels& models); #endif diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index a80e3d7d76c..d8ad7fab6f6 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -7,6 +7,7 @@ #include #include +#include "logic_types.h" #include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -109,8 +110,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi int log_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id); int pin_index = get_physical_pin(physical_type, logical_type, log_index); - if (physical_type->is_ignored_pin[pin_index] != net_is_ignored - && !is_io_type(physical_type)) { + if (physical_type->is_ignored_pin[pin_index] != net_is_ignored && !physical_type->is_io()) { VTR_LOGV_WARN(verbosity > 2, "Global net '%s' connects to non-global architecture pin '%s' (netlist pin '%s')\n", cluster_ctx.clb_nlist.net_name(net_id).c_str(), @@ -128,6 +128,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi static int check_clb_conn(ClusterBlockId iblk, int num_conn) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& clb_nlist = cluster_ctx.clb_nlist; + const LogicalModels& models = g_vpr_ctx.device().arch->models; int error = 0; t_logical_block_type_ptr type = clb_nlist.block_type(iblk); @@ -136,7 +137,7 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) { for (auto pin_id : clb_nlist.block_pins(iblk)) { auto pin_type = clb_nlist.pin_type(pin_id); - if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk)) { + if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk, models)) { //Input only and not a Primary-Output block VTR_LOG_WARN( "Logic block #%d (%s) has only 1 input pin '%s'" @@ -144,7 +145,7 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) { iblk, clb_nlist.block_name(iblk).c_str(), clb_nlist.pin_name(pin_id).c_str()); } - if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk)) { + if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk, models)) { //Output only and not a Primary-Input block VTR_LOG_WARN( "Logic block #%d (%s) has only 1 output pin '%s'." diff --git a/vpr/src/base/clock_modeling.cpp b/vpr/src/base/clock_modeling.cpp index 3873aca4310..e8d70d69bbd 100644 --- a/vpr/src/base/clock_modeling.cpp +++ b/vpr/src/base/clock_modeling.cpp @@ -1,5 +1,6 @@ #include "clock_modeling.h" #include "globals.h" +#include "vpr_utils.h" #include "vtr_assert.h" void ClockModeling::treat_clock_pins_as_non_globals() { diff --git a/vpr/src/base/clustered_netlist.cpp b/vpr/src/base/clustered_netlist.cpp index 2f2fce860a4..9bd350b2f9b 100644 --- a/vpr/src/base/clustered_netlist.cpp +++ b/vpr/src/base/clustered_netlist.cpp @@ -1,8 +1,11 @@ #include "clustered_netlist.h" #include "globals.h" +#include "logic_types.h" #include "physical_types_util.h" +#include "vpr_utils.h" #include "vtr_assert.h" +#include #include /** @@ -57,16 +60,18 @@ ClusterPinId ClusteredNetlist::block_pin(const ClusterBlockId blk, const int log return block_logical_pins_[blk][logical_pin_index]; } -bool ClusteredNetlist::block_contains_primary_input(const ClusterBlockId blk) const { +bool ClusteredNetlist::block_contains_primary_input(const ClusterBlockId blk, const LogicalModels& models) const { const t_pb* pb = block_pb(blk); - const t_pb* primary_input_pb = pb->find_pb_for_model(".input"); + LogicalModelId input_model_id = models.get_model_by_name(LogicalModels::MODEL_INPUT); + const t_pb* primary_input_pb = pb->find_pb_for_model(input_model_id); return primary_input_pb != nullptr; } ///@brief Returns true if the specified block contains a primary output (e.g. BLIF .output primitive) -bool ClusteredNetlist::block_contains_primary_output(const ClusterBlockId blk) const { +bool ClusteredNetlist::block_contains_primary_output(const ClusterBlockId blk, const LogicalModels& models) const { const t_pb* pb = block_pb(blk); - const t_pb* primary_output_pb = pb->find_pb_for_model(".output"); + LogicalModelId output_model_id = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); + const t_pb* primary_output_pb = pb->find_pb_for_model(output_model_id); return primary_output_pb != nullptr; } diff --git a/vpr/src/base/clustered_netlist.h b/vpr/src/base/clustered_netlist.h index a32e371741c..c711b13262a 100644 --- a/vpr/src/base/clustered_netlist.h +++ b/vpr/src/base/clustered_netlist.h @@ -106,9 +106,6 @@ * */ #include "vpr_types.h" -#include "vpr_utils.h" - -#include "vtr_util.h" #include "netlist.h" #include "clustered_netlist_fwd.h" @@ -144,10 +141,10 @@ class ClusteredNetlist : public Netlist + enum e_echo_files { //Input netlist diff --git a/vpr/src/base/netlist.h b/vpr/src/base/netlist.h index 0eb0cb536b6..2af6b3e378f 100644 --- a/vpr/src/base/netlist.h +++ b/vpr/src/base/netlist.h @@ -417,13 +417,9 @@ #include #include #include "vtr_range.h" -#include "vtr_logic.h" #include "vtr_vector_map.h" -#include "logic_types.h" - #include "netlist_fwd.h" -#include "netlist_utils.h" //Forward declaration for private methods template diff --git a/vpr/src/base/netlist.tpp b/vpr/src/base/netlist.tpp index 3987670aa63..5b5563ff16f 100644 --- a/vpr/src/base/netlist.tpp +++ b/vpr/src/base/netlist.tpp @@ -1,6 +1,7 @@ #include #include +#include "netlist_utils.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vpr_error.h" diff --git a/vpr/src/base/netlist_walker.cpp b/vpr/src/base/netlist_walker.cpp index 3411210f3cb..4539ed078af 100644 --- a/vpr/src/base/netlist_walker.cpp +++ b/vpr/src/base/netlist_walker.cpp @@ -42,7 +42,7 @@ void NetlistWalker::walk_blocks(const t_pb_routes& top_pb_route, const t_pb* pb) //Recurse const t_pb_type* pb_type = pb->pb_graph_node->pb_type; - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { const t_mode* mode = &pb_type->modes[pb->mode]; for (int i = 0; i < mode->num_pb_type_children; i++) { for (int j = 0; j < mode->pb_type_children[i].num_pb; j++) { diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index 53e79a871d9..8a02b9a7be1 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -72,6 +72,7 @@ #include #include "atom_netlist.h" #include "atom_netlist_utils.h" +#include "clock_modeling.h" #include "globals.h" #include "logic_vec.h" #include "netlist_walker.h" @@ -275,7 +276,7 @@ class LutInst : public Instance { std::map> port_conns, /// timing_arc_values, /// port_conns, ///first << "(" << escape_verilog_identifier(iter->second) << ")"; @@ -607,6 +631,7 @@ class LatchInst : public Instance { DelayTriple tcq_delay_triple_; ///second)) { - prefix << iter->second.length() << "'b"; - } + os << indent(depth) << type_name_; + + // Print the parameters if any are provided. + if (params_.size() > 0) { + if (opts_.post_synth_netlist_module_parameters) { + os << " #(\n"; + + //Verilog parameters + for (auto iter = params_.begin(); iter != params_.end(); ++iter) { + /* Prepend a prefix if needed */ + std::stringstream prefix; + if (is_binary_param(iter->second)) { + prefix << iter->second.length() << "'b"; + } - os << indent(depth + 1) << "." << iter->first << "(" << prefix.str() << iter->second << ")"; - if (iter != --params_.end()) { - os << ","; + os << indent(depth + 1) << "." << iter->first << "(" << prefix.str() << iter->second << ")"; + if (iter != --params_.end()) { + os << ","; + } + os << "\n"; + } + os << indent(depth) << ")"; + } else { + // TODO: RAMs are considered black box instructions. These can + // probably be handled similar to LUTs. + VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, + "Cannot generate black box instruction of type %s " + "without using parameters.", + type_name_.c_str()); } - os << "\n"; } //Instance name - os << indent(depth) << ") " << escape_verilog_identifier(inst_name_) << " (\n"; + os << " " << escape_verilog_identifier(inst_name_) << " (\n"; //Input Port connections for (auto iter = input_port_conns_.begin(); iter != input_port_conns_.end(); ++iter) { @@ -851,11 +891,13 @@ class NetlistWriterVisitor : public NetlistVisitor { std::ostream& blif_os, /// delay_calc, + const LogicalModels& models, struct t_analysis_opts opts) : verilog_os_(verilog_os) , blif_os_(blif_os) , sdf_os_(sdf_os) , delay_calc_(delay_calc) + , models_(models) , opts_(opts) { auto& atom_ctx = g_vpr_ctx.atom(); @@ -896,23 +938,24 @@ class NetlistWriterVisitor : public NetlistVisitor { if (atom_pb == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.netlist().block_model(atom_pb); + LogicalModelId model_id = atom_ctx.netlist().block_model(atom_pb); + std::string model_name = models_.model_name(model_id); - if (model->name == std::string(MODEL_INPUT)) { + if (model_name == LogicalModels::MODEL_INPUT) { inputs_.emplace_back(make_io(atom, PortType::INPUT)); - } else if (model->name == std::string(MODEL_OUTPUT)) { + } else if (model_name == LogicalModels::MODEL_OUTPUT) { outputs_.emplace_back(make_io(atom, PortType::OUTPUT)); - } else if (model->name == std::string(MODEL_NAMES)) { + } else if (model_name == LogicalModels::MODEL_NAMES) { cell_instances_.push_back(make_lut_instance(atom)); - } else if (model->name == std::string(MODEL_LATCH)) { + } else if (model_name == LogicalModels::MODEL_LATCH) { cell_instances_.push_back(make_latch_instance(atom)); - } else if (model->name == std::string("single_port_ram")) { + } else if (model_name == std::string("single_port_ram")) { cell_instances_.push_back(make_ram_instance(atom)); - } else if (model->name == std::string("dual_port_ram")) { + } else if (model_name == std::string("dual_port_ram")) { cell_instances_.push_back(make_ram_instance(atom)); - } else if (model->name == std::string("multiply")) { + } else if (model_name == std::string("multiply")) { cell_instances_.push_back(make_multiply_instance(atom)); - } else if (model->name == std::string("adder")) { + } else if (model_name == std::string("adder")) { cell_instances_.push_back(make_adder_instance(atom)); } else { cell_instances_.push_back(make_blackbox_instance(atom)); @@ -1275,7 +1318,10 @@ class NetlistWriterVisitor : public NetlistVisitor { //Add the single output connection { - auto atom_net_id = top_pb_route[sink_cluster_pin_idx].atom_net_id; //Connected net in atom netlist + /* Check if the output is connected */ + AtomNetId atom_net_id = AtomNetId::INVALID(); + if (top_pb_route.count(sink_cluster_pin_idx)) + atom_net_id = top_pb_route[sink_cluster_pin_idx].atom_net_id; //Connected net in atom netlist std::string net; if (!atom_net_id) { @@ -1325,6 +1371,9 @@ class NetlistWriterVisitor : public NetlistVisitor { double tsu = pb_graph_node->input_pins[0][0].tsu; DelayTriple tsu_triple(tsu, tsu, tsu); + double thld = pb_graph_node->input_pins[0][0].thld; + DelayTriple thld_triple(thld, thld, thld); + //Output (Q) int output_cluster_pin_idx = pb_graph_node->output_pins[0][0].pin_count_in_cluster; //Unique pin index in cluster VTR_ASSERT(top_pb_route.count(output_cluster_pin_idx)); @@ -1346,7 +1395,7 @@ class NetlistWriterVisitor : public NetlistVisitor { LatchInst::Type type = LatchInst::Type::RISING_EDGE; vtr::LogicValue init_value = vtr::LogicValue::FALSE; - return std::make_shared(inst_name, port_conns, type, init_value, tcq_triple, tsu_triple); + return std::make_shared(inst_name, port_conns, type, init_value, tcq_triple, tsu_triple, thld_triple, opts_); } /** @@ -1361,7 +1410,7 @@ class NetlistWriterVisitor : public NetlistVisitor { VTR_ASSERT(pb_type->class_type == MEMORY_CLASS); - std::string type = pb_type->model->name; + std::string type = models_.model_name(pb_type->model_id); std::string inst_name = join_identifier(type, atom->name); std::map params; std::map attrs; @@ -1506,7 +1555,7 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb_graph_node* pb_graph_node = atom->pb_graph_node; const t_pb_type* pb_type = pb_graph_node->pb_type; - std::string type_name = pb_type->model->name; + std::string type_name = models_.model_name(pb_type->model_id); std::string inst_name = join_identifier(type_name, atom->name); std::map params; std::map attrs; @@ -1601,7 +1650,7 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb_graph_node* pb_graph_node = atom->pb_graph_node; const t_pb_type* pb_type = pb_graph_node->pb_type; - std::string type_name = pb_type->model->name; + std::string type_name = models_.model_name(pb_type->model_id); std::string inst_name = join_identifier(type_name, atom->name); std::map params; std::map attrs; @@ -1698,7 +1747,7 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb_type* pb_type = pb_graph_node->pb_type; auto& timing_ctx = g_vpr_ctx.timing(); - std::string type_name = pb_type->model->name; + std::string type_name = models_.model_name(pb_type->model_id); std::string inst_name = join_identifier(type_name, atom->name); std::map params; std::map attrs; @@ -1879,8 +1928,9 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb* atom) { //LUT primitive auto& atom_ctx = g_vpr_ctx.atom(); - const t_model* model = atom_ctx.netlist().block_model(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom)); - VTR_ASSERT(model->name == std::string(MODEL_NAMES)); + LogicalModelId model_id = atom_ctx.netlist().block_model(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom)); + std::string model_name = models_.model_name(model_id); + VTR_ASSERT(model_name == LogicalModels::MODEL_NAMES); #ifdef DEBUG_LUT_MASK std::cout << "Loading LUT mask for: " << atom->name << std::endl; @@ -2159,6 +2209,11 @@ class NetlistWriterVisitor : public NetlistVisitor { std::map, tatum::NodeId> pin_id_to_tnode_lookup_; std::shared_ptr delay_calc_; + + protected: + const LogicalModels& models_; + + private: struct t_analysis_opts opts_; }; @@ -2173,8 +2228,9 @@ class MergedNetlistWriterVisitor : public NetlistWriterVisitor { std::ostream& blif_os, /// delay_calc, + const LogicalModels& models, struct t_analysis_opts opts) - : NetlistWriterVisitor(verilog_os, blif_os, sdf_os, delay_calc, opts) {} + : NetlistWriterVisitor(verilog_os, blif_os, sdf_os, delay_calc, models, opts) {} std::map portmap; @@ -2185,27 +2241,28 @@ class MergedNetlistWriterVisitor : public NetlistWriterVisitor { if (atom_pb == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.netlist().block_model(atom_pb); + LogicalModelId model_id = atom_ctx.netlist().block_model(atom_pb); + std::string model_name = models_.model_name(model_id); - if (model->name == std::string(MODEL_INPUT)) { + if (model_name == LogicalModels::MODEL_INPUT) { auto merged_io_name = make_io(atom, PortType::INPUT); if (merged_io_name != "") inputs_.emplace_back(merged_io_name); - } else if (model->name == std::string(MODEL_OUTPUT)) { + } else if (model_name == LogicalModels::MODEL_OUTPUT) { auto merged_io_name = make_io(atom, PortType::OUTPUT); if (merged_io_name != "") outputs_.emplace_back(merged_io_name); - } else if (model->name == std::string(MODEL_NAMES)) { + } else if (model_name == LogicalModels::MODEL_NAMES) { cell_instances_.push_back(make_lut_instance(atom)); - } else if (model->name == std::string(MODEL_LATCH)) { + } else if (model_name == LogicalModels::MODEL_LATCH) { cell_instances_.push_back(make_latch_instance(atom)); - } else if (model->name == std::string("single_port_ram")) { + } else if (model_name == std::string("single_port_ram")) { cell_instances_.push_back(make_ram_instance(atom)); - } else if (model->name == std::string("dual_port_ram")) { + } else if (model_name == std::string("dual_port_ram")) { cell_instances_.push_back(make_ram_instance(atom)); - } else if (model->name == std::string("multiply")) { + } else if (model_name == std::string("multiply")) { cell_instances_.push_back(make_multiply_instance(atom)); - } else if (model->name == std::string("adder")) { + } else if (model_name == std::string("adder")) { cell_instances_.push_back(make_adder_instance(atom)); } else { cell_instances_.push_back(make_blackbox_instance(atom)); @@ -2588,6 +2645,147 @@ std::string join_identifier(std::string lhs, std::string rhs) { return lhs + '_' + rhs; } +/** + * @brief Add the original SDC constraints that VPR used during its flow to the + * given SDC file. + * + * @param sdc_os + * Output stream for the target SDC file. The original SDC file passed into + * VPR will be appended to this file. + * @param timing_info + * Information on the timing within VPR. This is used to get the file path + * to the original SDC file. + */ +void add_original_sdc_to_post_implemented_sdc_file(std::ofstream& sdc_os, + const t_timing_inf& timing_info) { + // Open the original SDC file provided to VPR. + std::ifstream original_sdc_file; + original_sdc_file.open(timing_info.SDCFile); + if (!original_sdc_file.is_open()) { + // TODO: VPR automatically creates SDC constraints by default if no SDC + // file is provided. These can be replicated here if needed. + VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, + "No SDC files provided to VPR; currently cannot generate " + "post-implementation SDC file without it"); + } + + // Write a header to declare where these commands came from. + sdc_os << "\n"; + sdc_os << "#******************************************************************************#\n"; + sdc_os << "# The following SDC commands were provided to VPR from the given SDC file:\n"; + sdc_os << "# \t" << timing_info.SDCFile << "\n"; + sdc_os << "#******************************************************************************#\n"; + + // Append the original SDC file to the post-implementation SDC file. + sdc_os << original_sdc_file.rdbuf(); +} + +/** + * @brief Add propagated clock commands to the given SDC file based on the set + * clock modeling. + * + * This is necessary since VPR decides if clocks are routed or not, which has + * affects on how timing analysis is performed on the clocks. + * + * @param sdc_os + * The file stream to add the propagated clock commands to. + * @param clock_modeling + * The type of clock modeling used by VPR during the CAD flow. + */ +void add_propagated_clocks_to_sdc_file(std::ofstream& sdc_os, + e_clock_modeling clock_modeling) { + + // Ideal and routed clocks are handled by the code below. Other clock models + // like dedicated routing are not supported yet. + // TODO: Supporting dedicated routing should be simple; however it should + // be investigated. Tried quickly but found that the delays produced + // were off by 0.003 ns. Need to investigate why. + if (clock_modeling != e_clock_modeling::ROUTED_CLOCK && clock_modeling != e_clock_modeling::IDEAL_CLOCK) { + VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, + "Only ideal and routed clock modeling are currentlt " + "supported for post-implementation SDC file generation"); + } + + // The timing constraints contain information on all the clocks in the circuit + // (provided by the user-provided SDC file). + const auto timing_constraints = g_vpr_ctx.timing().constraints; + + // Collect the non-virtual clocks. Virtual clocks are not routed and + // do not get propageted. + std::vector non_virtual_clocks; + for (tatum::DomainId clock_domain_id : timing_constraints->clock_domains()) { + if (!timing_constraints->is_virtual_clock(clock_domain_id)) { + non_virtual_clocks.push_back(clock_domain_id); + } + } + + // If there are no non-virtual clocks, no extra commands needed. Virtual + // clocks are ideal. + if (non_virtual_clocks.empty()) { + return; + } + + // Append a header to explain why these commands are added. + sdc_os << "\n"; + sdc_os << "#******************************************************************************#\n"; + sdc_os << "# The following are clock domains in VPR which have delays on their edges.\n"; + sdc_os << "#\n"; + sdc_os << "# Any non-virtual clock has its delay determined and written out as part of a"; + sdc_os << "# propagated clock command. If VPR was instructed not to route the clock, this"; + sdc_os << "# delay will be an underestimate.\n"; + sdc_os << "#\n"; + sdc_os << "# Note: Virtual clocks do not get routed and are treated as ideal.\n"; + sdc_os << "#******************************************************************************#\n"; + + // Add the SDC commands to set the non-virtual clocks as propagated (non-ideal); + // Note: It was decided that "ideal" (dont route) clock modeling in VPR should still + // set the clocks as propagated to allow for the input pad delays of + // clocks to be included. The SDF delay annotations on clock signals + // should make this safe to do. + for (tatum::DomainId clock_domain_id : non_virtual_clocks) { + sdc_os << "set_propagated_clock "; + sdc_os << timing_constraints->clock_domain_name(clock_domain_id); + sdc_os << "\n"; + } +} + +/** + * @brief Generates a post-implementation SDC file with the given file name + * based on the timing info and clock modeling set for VPR. + * + * @param sdc_filename + * The file name of the SDC file to generate. + * @param timing_info + * Information on the timing used in the VPR flow. + * @param clock_modeling + * The type of clock modeling used by VPR during its flow. + */ +void generate_post_implementation_sdc(const std::string& sdc_filename, + const t_timing_inf& timing_info, + e_clock_modeling clock_modeling) { + if (!timing_info.timing_analysis_enabled) { + VTR_LOG_WARN("Timing analysis is disabled. Post-implementation SDC file " + "will not be generated.\n"); + return; + } + + // Begin writing the post-implementation SDC file. + std::ofstream sdc_os(sdc_filename); + + // Print a header declaring that this file is auto-generated and what version + // of VTR produced it. + sdc_os << "#******************************************************************************#\n"; + sdc_os << "# SDC automatically generated by VPR from a post-place-and-route implementation.\n"; + sdc_os << "#\tVersion: " << vtr::VERSION << "\n"; + sdc_os << "#******************************************************************************#\n"; + + // Add the original SDC that VPR used during its flow. + add_original_sdc_to_post_implemented_sdc_file(sdc_os, timing_info); + + // Add propagated clocks to SDC file if needed. + add_propagated_clocks_to_sdc_file(sdc_os, clock_modeling); +} + } // namespace // @@ -2595,7 +2793,12 @@ std::string join_identifier(std::string lhs, std::string rhs) { // ///@brief Main routine for this file. See netlist_writer.h for details. -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { +void netlist_writer(const std::string basename, + std::shared_ptr delay_calc, + const LogicalModels& models, + const t_timing_inf& timing_info, + e_clock_modeling clock_modeling, + t_analysis_opts opts) { std::string verilog_filename = basename + "_post_synthesis.v"; std::string blif_filename = basename + "_post_synthesis.blif"; std::string sdf_filename = basename + "_post_synthesis.sdf"; @@ -2603,20 +2806,29 @@ void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { +void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, t_analysis_opts opts) { std::string verilog_filename = basename + "_merged_post_implementation.v"; VTR_LOG("Writing Merged Implementation Netlist: %s\n", verilog_filename.c_str()); @@ -2626,7 +2838,7 @@ void merged_netlist_writer(const std::string basename, std::shared_ptr #include "AnalysisDelayCalculator.h" +class LogicalModels; + /** * @brief Writes out the post-synthesis implementation netlists in BLIF and Verilog formats, * along with an SDF for delay annotations. @@ -13,8 +15,26 @@ * * All written filenames end in {basename}_post_synthesis.{fmt} where {basename} is the * basename argument and {fmt} is the file format (e.g. v, blif, sdf) + * + * @param basename + * The basename prefix used for the generated files. + * @param delay_calc + * The delay calculator used to get the timing of edges in the timing graph. + * @param models + * The logical models in the architecture. + * @param timing_info + * Information on the timing used in the VPR flow. + * @param clock_modeling + * The type of clock modeling used in the VPR flow. + * @param opts + * The analysis options. */ -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, t_analysis_opts opts); +void netlist_writer(const std::string basename, + std::shared_ptr delay_calc, + const LogicalModels& models, + const t_timing_inf& timing_info, + e_clock_modeling clock_modeling, + t_analysis_opts opts); /** * @brief Writes out the post implementation netlist in Verilog format. @@ -26,4 +46,4 @@ void netlist_writer(const std::string basename, std::shared_ptr delay_calc, t_analysis_opts opts); +void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, t_analysis_opts opts); diff --git a/vpr/src/base/old_traceback.cpp b/vpr/src/base/old_traceback.cpp index a1bb21be232..29531cb29dc 100644 --- a/vpr/src/base/old_traceback.cpp +++ b/vpr/src/base/old_traceback.cpp @@ -36,13 +36,13 @@ void TracebackCompat::traceback_to_route_tree_x(t_trace* trace, RouteTree& tree, new_node->R_upstream = std::numeric_limits::quiet_NaN(); new_node->C_downstream = std::numeric_limits::quiet_NaN(); new_node->Tdel = std::numeric_limits::quiet_NaN(); - auto node_type = rr_graph.node_type(inode); - if (node_type == IPIN || node_type == SINK) + e_rr_type node_type = rr_graph.node_type(inode); + if (node_type == e_rr_type::IPIN || node_type == e_rr_type::SINK) new_node->re_expand = false; else new_node->re_expand = true; - if (rr_graph.node_type(inode) == SINK) { + if (rr_graph.node_type(inode) == e_rr_type::SINK) { /* The traceback returns to the previous branch point if there is more than one SINK, otherwise we are at the last SINK */ if (trace->next) { RRNodeId next_rr_node = RRNodeId(trace->next->index); diff --git a/vpr/src/base/partition.h b/vpr/src/base/partition.h index 9c8984b8c86..1772d47a0fc 100644 --- a/vpr/src/base/partition.h +++ b/vpr/src/base/partition.h @@ -4,9 +4,8 @@ #include #include "vtr_strong_id.h" -#include "region.h" -#include "atom_netlist_fwd.h" #include "partition_region.h" + /** * @file * @brief This file defines the data for a partition: a grouping of atoms that are constrained to a portion of an FPGA. diff --git a/vpr/src/base/partition_region.h b/vpr/src/base/partition_region.h index 2e9949fceea..80f3a2f36a7 100644 --- a/vpr/src/base/partition_region.h +++ b/vpr/src/base/partition_region.h @@ -2,7 +2,6 @@ #define PARTITION_REGIONS_H #include "region.h" -#include "atom_netlist_fwd.h" #include "vpr_types.h" /** diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index 9fcf2a78ff5..5153e0a0587 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -48,7 +48,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, const t_arch* arch, bool verify_binary_search, int min_chan_width_hint, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, NetPinsMatrix& net_delay, const std::shared_ptr& timing_info, @@ -83,17 +83,17 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, graph_type = e_graph_type::GLOBAL; graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); /* Branch on tileable routing */ - if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + if (det_routing_arch.directionality == UNI_DIRECTIONAL && det_routing_arch.tileable) { graph_type = e_graph_type::UNIDIR_TILEABLE; } - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } VTR_ASSERT(!net_delay.empty()); - if (det_routing_arch->directionality == BI_DIRECTIONAL) + if (det_routing_arch.directionality == BI_DIRECTIONAL) udsd_multiplier = 1; else udsd_multiplier = 2; @@ -120,14 +120,14 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, } /* Constraints must be checked to not break rr_graph generator */ - if (det_routing_arch->directionality == UNI_DIRECTIONAL) { + if (det_routing_arch.directionality == UNI_DIRECTIONAL) { if (current % 2 != 0) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Tried odd chan width (%d) in uni-directional routing architecture (chan width must be even).\n", current); } } else { - if (det_routing_arch->Fs % 3) { + if (det_routing_arch.Fs % 3) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Fs must be three in bidirectional mode.\n"); } @@ -162,7 +162,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, } } - if ((current * 3) < det_routing_arch->Fs) { + if ((current * 3) < det_routing_arch.Fs) { VTR_LOG("Width factor is now below specified Fs. Stop search.\n"); final = high; break; @@ -354,7 +354,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, prev2_success = prev_success; prev_success = success; current--; - if (det_routing_arch->directionality == UNI_DIRECTIONAL) { + if (det_routing_arch.directionality == UNI_DIRECTIONAL) { current--; /* width must be even */ } } diff --git a/vpr/src/base/place_and_route.h b/vpr/src/base/place_and_route.h index e595a2cdedb..935f678841e 100644 --- a/vpr/src/base/place_and_route.h +++ b/vpr/src/base/place_and_route.h @@ -9,7 +9,6 @@ #include "vpr_types.h" #include "timing_info.h" #include "RoutingDelayCalculator.h" -#include "rr_graph.h" struct t_fmap_cell { int fs; ///& placement_net_list, const t_arch* arch, bool verify_binary_search, int min_chan_width_hint, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, NetPinsMatrix& net_delay, const std::shared_ptr& timing_info, diff --git a/vpr/src/base/read_blif.cpp b/vpr/src/base/read_blif.cpp index ef767444bf6..9e0668e39d1 100644 --- a/vpr/src/base/read_blif.cpp +++ b/vpr/src/base/read_blif.cpp @@ -18,41 +18,36 @@ #include #include #include -#include #include //std::isdigit +#include //std::regex #include "blifparse.hpp" #include "atom_netlist.h" +#include "logic_types.h" #include "vtr_assert.h" #include "vtr_util.h" #include "vtr_log.h" #include "vtr_logic.h" -#include "vtr_time.h" #include "vtr_digest.h" -#include "vpr_types.h" #include "vpr_error.h" -#include "globals.h" #include "read_blif.h" -#include "arch_types.h" -#include "echo_files.h" #include "hash.h" vtr::LogicValue to_vtr_logic_value(blifparse::LogicValue); struct BlifAllocCallback : public blifparse::Callback { public: - BlifAllocCallback(e_circuit_format blif_format, AtomNetlist& main_netlist, const std::string netlist_id, const t_model* user_models, const t_model* library_models) + BlifAllocCallback(e_circuit_format blif_format, AtomNetlist& main_netlist, const std::string netlist_id, const LogicalModels& models) : main_netlist_(main_netlist) , netlist_id_(netlist_id) - , user_arch_models_(user_models) - , library_arch_models_(library_models) + , models_(models) , blif_format_(blif_format) { VTR_ASSERT(blif_format_ == e_circuit_format::BLIF || blif_format_ == e_circuit_format::EBLIF); - inpad_model_ = find_model(MODEL_INPUT); - outpad_model_ = find_model(MODEL_OUTPUT); + inpad_model_ = models.get_model_by_name(LogicalModels::MODEL_INPUT); + outpad_model_ = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); main_netlist_.set_block_types(inpad_model_, outpad_model_); } @@ -81,17 +76,18 @@ struct BlifAllocCallback : public blifparse::Callback { } void inputs(std::vector input_names) override { - const t_model* blk_model = find_model(MODEL_INPUT); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_INPUT); + const t_model& blk_model = models_.get_model(blk_model_id); - VTR_ASSERT_MSG(!blk_model->inputs, "Inpad model has an input port"); - VTR_ASSERT_MSG(blk_model->outputs, "Inpad model has no output port"); - VTR_ASSERT_MSG(blk_model->outputs->size == 1, "Inpad model has non-single-bit output port"); - VTR_ASSERT_MSG(!blk_model->outputs->next, "Inpad model has multiple output ports"); + VTR_ASSERT_MSG(!blk_model.inputs, "Inpad model has an input port"); + VTR_ASSERT_MSG(blk_model.outputs, "Inpad model has no output port"); + VTR_ASSERT_MSG(blk_model.outputs->size == 1, "Inpad model has non-single-bit output port"); + VTR_ASSERT_MSG(!blk_model.outputs->next, "Inpad model has multiple output ports"); - std::string pin_name = blk_model->outputs->name; + std::string pin_name = blk_model.outputs->name; for (const auto& input : input_names) { - AtomBlockId blk_id = curr_model().create_block(input, blk_model); - AtomPortId port_id = curr_model().create_port(blk_id, blk_model->outputs); + AtomBlockId blk_id = curr_model().create_block(input, blk_model_id); + AtomPortId port_id = curr_model().create_port(blk_id, blk_model.outputs); AtomNetId net_id = curr_model().create_net(input); curr_model().create_pin(port_id, 0, net_id, PinType::DRIVER); } @@ -99,19 +95,20 @@ struct BlifAllocCallback : public blifparse::Callback { } void outputs(std::vector output_names) override { - const t_model* blk_model = find_model(MODEL_OUTPUT); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_OUTPUT); + const t_model& blk_model = models_.get_model(blk_model_id); - VTR_ASSERT_MSG(!blk_model->outputs, "Outpad model has an output port"); - VTR_ASSERT_MSG(blk_model->inputs, "Outpad model has no input port"); - VTR_ASSERT_MSG(blk_model->inputs->size == 1, "Outpad model has non-single-bit input port"); - VTR_ASSERT_MSG(!blk_model->inputs->next, "Outpad model has multiple input ports"); + VTR_ASSERT_MSG(!blk_model.outputs, "Outpad model has an output port"); + VTR_ASSERT_MSG(blk_model.inputs, "Outpad model has no input port"); + VTR_ASSERT_MSG(blk_model.inputs->size == 1, "Outpad model has non-single-bit input port"); + VTR_ASSERT_MSG(!blk_model.inputs->next, "Outpad model has multiple input ports"); - std::string pin_name = blk_model->inputs->name; + std::string pin_name = blk_model.inputs->name; for (const auto& output : output_names) { //Since we name blocks based on their drivers we need to uniquify outpad names, //which we do with a prefix - AtomBlockId blk_id = curr_model().create_block(OUTPAD_NAME_PREFIX + output, blk_model); - AtomPortId port_id = curr_model().create_port(blk_id, blk_model->inputs); + AtomBlockId blk_id = curr_model().create_block(OUTPAD_NAME_PREFIX + output, blk_model_id); + AtomPortId port_id = curr_model().create_port(blk_id, blk_model.inputs); AtomNetId net_id = curr_model().create_net(output); curr_model().create_pin(port_id, 0, net_id, PinType::SINK); } @@ -119,20 +116,21 @@ struct BlifAllocCallback : public blifparse::Callback { } void names(std::vector nets, std::vector> so_cover) override { - const t_model* blk_model = find_model(MODEL_NAMES); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_NAMES); + const t_model& blk_model = models_.get_model(blk_model_id); VTR_ASSERT_MSG(nets.size() > 0, "BLIF .names has no connections"); - VTR_ASSERT_MSG(blk_model->inputs, ".names model has no input port"); - VTR_ASSERT_MSG(!blk_model->inputs->next, ".names model has multiple input ports"); - if (static_cast(nets.size()) - 1 > blk_model->inputs->size) { + VTR_ASSERT_MSG(blk_model.inputs, ".names model has no input port"); + VTR_ASSERT_MSG(!blk_model.inputs->next, ".names model has multiple input ports"); + if (static_cast(nets.size()) - 1 > blk_model.inputs->size) { vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "BLIF .names input size (%zu) greater than .names model input size (%d)", - nets.size() - 1, blk_model->inputs->size); + nets.size() - 1, blk_model.inputs->size); } - VTR_ASSERT_MSG(blk_model->outputs, ".names has no output port"); - VTR_ASSERT_MSG(!blk_model->outputs->next, ".names model has multiple output ports"); - VTR_ASSERT_MSG(blk_model->outputs->size == 1, ".names model has non-single-bit output"); + VTR_ASSERT_MSG(blk_model.outputs, ".names has no output port"); + VTR_ASSERT_MSG(!blk_model.outputs->next, ".names model has multiple output ports"); + VTR_ASSERT_MSG(blk_model.outputs->size == 1, ".names model has non-single-bit output"); //Convert the single-output cover to a netlist truth table AtomNetlist::TruthTable truth_table; @@ -143,11 +141,11 @@ struct BlifAllocCallback : public blifparse::Callback { } } - AtomBlockId blk_id = curr_model().create_block(nets[nets.size() - 1], blk_model, truth_table); + AtomBlockId blk_id = curr_model().create_block(nets[nets.size() - 1], blk_model_id, truth_table); set_curr_block(blk_id); //Create inputs - AtomPortId input_port_id = curr_model().create_port(blk_id, blk_model->inputs); + AtomPortId input_port_id = curr_model().create_port(blk_id, blk_model.inputs); for (size_t i = 0; i < nets.size() - 1; ++i) { AtomNetId net_id = curr_model().create_net(nets[i]); @@ -187,7 +185,7 @@ struct BlifAllocCallback : public blifparse::Callback { //Create output AtomNetId net_id = curr_model().create_net(nets[nets.size() - 1]); - AtomPortId output_port_id = curr_model().create_port(blk_id, blk_model->outputs); + AtomPortId output_port_id = curr_model().create_port(blk_id, blk_model.outputs); curr_model().create_pin(output_port_id, 0, net_id, PinType::DRIVER, output_is_const); } @@ -202,17 +200,18 @@ struct BlifAllocCallback : public blifparse::Callback { vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Latch must have a clock\n"); } - const t_model* blk_model = find_model(MODEL_LATCH); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_LATCH); + const t_model& blk_model = models_.get_model(blk_model_id); - VTR_ASSERT_MSG(blk_model->inputs, "Has one input port"); - VTR_ASSERT_MSG(blk_model->inputs->next, "Has two input port"); - VTR_ASSERT_MSG(!blk_model->inputs->next->next, "Has no more than two input port"); - VTR_ASSERT_MSG(blk_model->outputs, "Has one output port"); - VTR_ASSERT_MSG(!blk_model->outputs->next, "Has no more than one input port"); + VTR_ASSERT_MSG(blk_model.inputs, "Has one input port"); + VTR_ASSERT_MSG(blk_model.inputs->next, "Has two input port"); + VTR_ASSERT_MSG(!blk_model.inputs->next->next, "Has no more than two input port"); + VTR_ASSERT_MSG(blk_model.outputs, "Has one output port"); + VTR_ASSERT_MSG(!blk_model.outputs->next, "Has no more than one input port"); - const t_model_ports* d_model_port = blk_model->inputs; - const t_model_ports* clk_model_port = blk_model->inputs->next; - const t_model_ports* q_model_port = blk_model->outputs; + const t_model_ports* d_model_port = blk_model.inputs; + const t_model_ports* clk_model_port = blk_model.inputs->next; + const t_model_ports* q_model_port = blk_model.outputs; VTR_ASSERT(d_model_port->name == std::string("D")); VTR_ASSERT(clk_model_port->name == std::string("clk")); @@ -226,7 +225,7 @@ struct BlifAllocCallback : public blifparse::Callback { AtomNetlist::TruthTable truth_table(1); truth_table[0].push_back(to_vtr_logic_value(init)); - AtomBlockId blk_id = curr_model().create_block(output, blk_model, truth_table); + AtomBlockId blk_id = curr_model().create_block(output, blk_model_id, truth_table); set_curr_block(blk_id); //The input @@ -248,7 +247,8 @@ struct BlifAllocCallback : public blifparse::Callback { void subckt(std::string subckt_model, std::vector ports, std::vector nets) override { VTR_ASSERT(ports.size() == nets.size()); - const t_model* blk_model = find_model(subckt_model); + LogicalModelId blk_model_id = models_.get_model_by_name(subckt_model); + const t_model& blk_model = models_.get_model(blk_model_id); //We name the subckt based on the net it's first output pin drives std::string subckt_name; @@ -269,21 +269,21 @@ struct BlifAllocCallback : public blifparse::Callback { //Since this is unusual, warn the user VTR_LOGF_WARN(filename_.c_str(), lineno_, "Subckt of type '%s' at %s:%d has no output pins, and has been named '%s'\n", - blk_model->name, filename_.c_str(), lineno_, subckt_name.c_str()); + blk_model.name, filename_.c_str(), lineno_, subckt_name.c_str()); } //The name for every block should be unique, check that there is no name conflict AtomBlockId blk_id = curr_model().find_block(subckt_name); if (blk_id) { - const t_model* conflicting_model = curr_model().block_model(blk_id); + LogicalModelId conflicting_model = curr_model().block_model(blk_id); vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Duplicate blocks named '%s' found in netlist." " Existing block of type '%s' conflicts with subckt of type '%s'.", - subckt_name.c_str(), conflicting_model->name, subckt_model.c_str()); + subckt_name.c_str(), models_.get_model(conflicting_model).name, subckt_model.c_str()); } //Create the block - blk_id = curr_model().create_block(subckt_name, blk_model); + blk_id = curr_model().create_block(subckt_name, blk_model_id); set_curr_block(blk_id); for (size_t i = 0; i < ports.size(); ++i) { @@ -443,30 +443,7 @@ struct BlifAllocCallback : public blifparse::Callback { } private: - const t_model* find_model(std::string_view name) { - const t_model* arch_model = nullptr; - for (const t_model* arch_models : {user_arch_models_, library_arch_models_}) { - arch_model = arch_models; - while (arch_model) { - if (name == arch_model->name) { - //Found it - break; - } - arch_model = arch_model->next; - } - if (arch_model) { - //Found it - break; - } - } - if (!arch_model) { - vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Failed to find matching architecture model for '%s'\n", - name.data()); - } - return arch_model; - } - - const t_model_ports* find_model_port(const t_model* blk_model, const std::string& port_name) { + const t_model_ports* find_model_port(const t_model& blk_model, const std::string& port_name) { //We need to handle both single, and multi-bit port names // //By convention multi-bit port names have the bit index stored in square brackets @@ -485,7 +462,7 @@ struct BlifAllocCallback : public blifparse::Callback { VTR_ASSERT(bit_index >= 0); //We now look through all the ports on the model looking for the matching port - for (const t_model_ports* ports : {blk_model->inputs, blk_model->outputs}) { + for (const t_model_ports* ports : {blk_model.inputs, blk_model.outputs}) { const t_model_ports* curr_port = ports; while (curr_port) { if (trimmed_port_name == curr_port->name) { @@ -497,7 +474,7 @@ struct BlifAllocCallback : public blifparse::Callback { //Out of range vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Port '%s' on architecture model '%s' exceeds port width (%d bits)\n", - port_name.c_str(), blk_model->name, curr_port->size); + port_name.c_str(), blk_model.name, curr_port->size); } } curr_port = curr_port->next; @@ -507,7 +484,7 @@ struct BlifAllocCallback : public blifparse::Callback { //No match vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Found no matching port '%s' on architecture model '%s'\n", - port_name.c_str(), blk_model->name); + port_name.c_str(), blk_model.name); return nullptr; } @@ -563,7 +540,8 @@ struct BlifAllocCallback : public blifparse::Callback { } bool verify_blackbox_model(AtomNetlist& blif_model) { - const t_model* arch_model = find_model(blif_model.netlist_name()); + LogicalModelId arch_model_id = models_.get_model_by_name(blif_model.netlist_name()); + const t_model& arch_model = models_.get_model(arch_model_id); //Verify each port on the model // @@ -639,10 +617,9 @@ struct BlifAllocCallback : public blifparse::Callback { AtomNetlist& main_netlist_; /// #include "atom_netlist_fwd.h" #include "read_circuit.h" +class LogicalModels; + bool is_string_param(const std::string& param); bool is_binary_param(const std::string& param); bool is_real_param(const std::string& param); AtomNetlist read_blif(e_circuit_format circuit_format, const char* blif_file, - const t_model* user_models, - const t_model* library_models); + const LogicalModels& models); #endif /*READ_BLIF_H*/ diff --git a/vpr/src/base/read_circuit.cpp b/vpr/src/base/read_circuit.cpp index 4d6fab3f25d..f1112d92016 100644 --- a/vpr/src/base/read_circuit.cpp +++ b/vpr/src/base/read_circuit.cpp @@ -1,4 +1,5 @@ #include "read_circuit.h" +#include "logic_types.h" #include "read_blif.h" #include "read_interchange_netlist.h" #include "atom_netlist.h" @@ -16,15 +17,14 @@ static void process_circuit(AtomNetlist& netlist, bool should_sweep_dangling_nets, bool should_sweep_dangling_blocks, bool should_sweep_constant_primary_outputs, + const LogicalModels& models, int verbosity); -static void show_circuit_stats(const AtomNetlist& netlist); +static void show_circuit_stats(const AtomNetlist& netlist, const LogicalModels& models); AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch) { // Options const char* circuit_file = vpr_setup.PackerOpts.circuit_file_name.c_str(); - const t_model* user_models = vpr_setup.user_models; - const t_model* library_models = vpr_setup.library_models; e_const_gen_inference const_gen_inference = vpr_setup.NetlistOpts.const_gen_inference; bool should_absorb_buffers = vpr_setup.NetlistOpts.absorb_buffer_luts; bool should_sweep_dangling_primary_ios = vpr_setup.NetlistOpts.sweep_dangling_primary_ios; @@ -54,7 +54,7 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu switch (circuit_format) { case e_circuit_format::BLIF: case e_circuit_format::EBLIF: - netlist = read_blif(circuit_format, circuit_file, user_models, library_models); + netlist = read_blif(circuit_format, circuit_file, arch.models); break; case e_circuit_format::FPGA_INTERCHANGE: netlist = read_interchange_netlist(circuit_file, arch); @@ -68,7 +68,7 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu } if (isEchoFileEnabled(E_ECHO_ATOM_NETLIST_ORIG)) { - print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_ORIG), netlist); + print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_ORIG), netlist, arch.models); } process_circuit(netlist, @@ -78,13 +78,14 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu should_sweep_dangling_nets, should_sweep_dangling_blocks, should_sweep_constant_primary_outputs, + arch.models, verbosity); if (isEchoFileEnabled(E_ECHO_ATOM_NETLIST_CLEANED)) { - print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_CLEANED), netlist); + print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_CLEANED), netlist, arch.models); } - show_circuit_stats(netlist); + show_circuit_stats(netlist, arch.models); return netlist; } @@ -96,13 +97,14 @@ static void process_circuit(AtomNetlist& netlist, bool should_sweep_dangling_nets, bool should_sweep_dangling_blocks, bool should_sweep_constant_primary_outputs, + const LogicalModels& models, int verbosity) { { vtr::ScopedStartFinishTimer t("Clean circuit"); //Clean-up lut buffers if (should_absorb_buffers) { - absorb_buffer_luts(netlist, verbosity); + absorb_buffer_luts(netlist, models, verbosity); } //Remove the special 'unconn' net @@ -126,6 +128,7 @@ static void process_circuit(AtomNetlist& netlist, should_sweep_dangling_blocks, should_sweep_constant_primary_outputs, const_gen_inference_method, + models, verbosity); } @@ -142,17 +145,19 @@ static void process_circuit(AtomNetlist& netlist, } } -static void show_circuit_stats(const AtomNetlist& netlist) { +static void show_circuit_stats(const AtomNetlist& netlist, const LogicalModels& models) { // Count the block statistics std::map block_type_counts; std::map lut_size_counts; + LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); for (auto blk_id : netlist.blocks()) { // For each model, count the number of occurrences in the netlist. - const t_model* blk_model = netlist.block_model(blk_id); - ++block_type_counts[blk_model->name]; + LogicalModelId blk_model_id = netlist.block_model(blk_id); + std::string blk_model_name = models.get_model(blk_model_id).name; + ++block_type_counts[blk_model_name]; // If this block is a LUT, also count the occurences of this size of LUT // for more logging information. - if (blk_model->name == std::string(MODEL_NAMES)) { + if (blk_model_id == names_model_id) { // May have zero (no input LUT) or one input port auto in_ports = netlist.block_input_ports(blk_id); VTR_ASSERT(in_ports.size() <= 1 && "Expected number of input ports for LUT to be 0 or 1"); @@ -205,7 +210,7 @@ static void show_circuit_stats(const AtomNetlist& netlist) { VTR_LOG(" %-*s: %7zu\n", max_block_type_len, kv.first.c_str(), kv.second); // If this block is a LUT, print the different sizes of LUTs in the // design. - if (kv.first == std::string(MODEL_NAMES)) { + if (kv.first == LogicalModels::MODEL_NAMES) { for (const auto& lut_kv : lut_size_counts) { VTR_LOG(" %-*s: %7zu\n", max_lut_size_len, lut_kv.first.c_str(), lut_kv.second); } @@ -215,7 +220,7 @@ static void show_circuit_stats(const AtomNetlist& netlist) { for (const auto& kv : net_stats) { VTR_LOG(" %-*s: %7.1f\n", max_net_type_len, kv.first.c_str(), kv.second); } - VTR_LOG(" Netlist Clocks: %zu\n", find_netlist_logical_clock_drivers(netlist).size()); + VTR_LOG(" Netlist Clocks: %zu\n", find_netlist_logical_clock_drivers(netlist, models).size()); if (netlist.blocks().empty()) { VTR_LOG_WARN("Netlist contains no blocks\n"); diff --git a/vpr/src/base/read_circuit.h b/vpr/src/base/read_circuit.h index 90be01a3891..89f42f7ec61 100644 --- a/vpr/src/base/read_circuit.h +++ b/vpr/src/base/read_circuit.h @@ -1,8 +1,10 @@ #ifndef VPR_READ_CIRCUIT_H #define VPR_READ_CIRCUIT_H -#include "logic_types.h" + #include "atom_netlist_fwd.h" -#include "vpr_types.h" + +struct t_vpr_setup; +struct t_arch; enum class e_circuit_format { AUTO, ///outputs); + blk_id = main_netlist_.create_block(port_name, input_model_id); + port_id = main_netlist_.create_port(blk_id, input_model.outputs); net_id = main_netlist_.create_net(port_name); main_netlist_.create_pin(port_id, 0, net_id, PinType::DRIVER); break; case LogicalNetlist::Netlist::Direction::OUTPUT: - blk_id = main_netlist_.create_block(port_name, output_model); - port_id = main_netlist_.create_port(blk_id, output_model->inputs); + blk_id = main_netlist_.create_block(port_name, output_model_id); + port_id = main_netlist_.create_port(blk_id, output_model.inputs); net_id = main_netlist_.create_net(port_name); main_netlist_.create_pin(port_id, 0, net_id, PinType::SINK); break; @@ -188,13 +187,14 @@ struct NetlistReader { } void read_names() { - const t_model* blk_model = find_model(MODEL_NAMES); + LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_NAMES); + const t_model& blk_model = models_.get_model(blk_model_id); // Set the max size of the LUT int lut_size = 0; for (auto lut : arch_.lut_cells) lut_size = std::max((int)lut.inputs.size(), lut_size); - blk_model->inputs[0].size = lut_size; + blk_model.inputs[0].size = lut_size; auto top_cell = nr_.getCellList()[nr_.getTopInst().getCell()]; auto decl_list = nr_.getCellDecls(); @@ -317,10 +317,10 @@ struct NetlistReader { VTR_LOG("Found constant-one generator '%s'\n", inst_name.c_str()); } - AtomBlockId blk_id = main_netlist_.create_block(inst_name, blk_model, truth_table); + AtomBlockId blk_id = main_netlist_.create_block(inst_name, blk_model_id, truth_table); - AtomPortId iport_id = main_netlist_.create_port(blk_id, blk_model->inputs); - AtomPortId oport_id = main_netlist_.create_port(blk_id, blk_model->outputs); + AtomPortId iport_id = main_netlist_.create_port(blk_id, blk_model.inputs); + AtomPortId oport_id = main_netlist_.create_port(blk_id, blk_model.outputs); auto cell_lib = decl_list[inst_list[inst_idx].getCell()]; auto port_net_map = port_net_maps_.at(inst_idx); @@ -373,7 +373,8 @@ struct NetlistReader { auto cell_idx = inst_pair.second; auto model_name = str_list[decl_list[cell_idx].getName()]; - const t_model* blk_model = find_model(model_name); + LogicalModelId blk_model_id = models_.get_model_by_name(model_name); + const t_model& blk_model = models_.get_model(blk_model_id); std::string inst_name = str_list[inst_list[inst_idx].getName()]; VTR_ASSERT(inst_name.empty() == 0); @@ -381,11 +382,11 @@ struct NetlistReader { //The name for every block should be unique, check that there is no name conflict AtomBlockId blk_id = main_netlist_.find_block(inst_name); if (blk_id) { - const t_model* conflicting_model = main_netlist_.block_model(blk_id); + LogicalModelId conflicting_model = main_netlist_.block_model(blk_id); vpr_throw(VPR_ERROR_IC_NETLIST_F, netlist_file_, -1, "Duplicate blocks named '%s' found in netlist." " Existing block of type '%s' conflicts with subckt of type '%s'.", - inst_name.c_str(), conflicting_model->name, blk_model->name); + inst_name.c_str(), models_.get_model(conflicting_model).name, blk_model.name); } auto port_net_map = port_net_maps_.at(inst_idx); @@ -400,7 +401,7 @@ struct NetlistReader { continue; //Create the block - blk_id = main_netlist_.create_block(inst_name, blk_model); + blk_id = main_netlist_.create_block(inst_name, blk_model_id); std::unordered_set added_ports; for (auto port_net : port_net_map) { @@ -440,7 +441,7 @@ struct NetlistReader { } // Bind unconnected ports to VCC by default - for (const t_model_ports* ports : {blk_model->inputs, blk_model->outputs}) { + for (const t_model_ports* ports : {blk_model.inputs, blk_model.outputs}) { for (const t_model_ports* port = ports; port != nullptr; port = port->next) { AtomPortId port_id = main_netlist_.create_port(blk_id, port); @@ -465,18 +466,9 @@ struct NetlistReader { // // Utilities // - const t_model* find_model(std::string name) { - for (const auto models : {arch_.models, arch_.model_library}) - for (const t_model* model = models; model != nullptr; model = model->next) - if (name == model->name) - return model; - - vpr_throw(VPR_ERROR_IC_NETLIST_F, netlist_file_, -1, "Failed to find matching architecture model for '%s'\n", name.c_str()); - } - - const t_model_ports* find_model_port(const t_model* blk_model, std::string name) { + const t_model_ports* find_model_port(const t_model& blk_model, std::string name) { //We now look through all the ports on the model looking for the matching port - for (const t_model_ports* ports : {blk_model->inputs, blk_model->outputs}) + for (const t_model_ports* ports : {blk_model.inputs, blk_model.outputs}) for (const t_model_ports* port = ports; port != nullptr; port = port->next) if (name == std::string(port->name)) return port; @@ -484,7 +476,7 @@ struct NetlistReader { //No match vpr_throw(VPR_ERROR_IC_NETLIST_F, netlist_file_, -1, "Found no matching port '%s' on architecture model '%s'\n", - name.c_str(), blk_model->name); + name.c_str(), blk_model.name); return nullptr; } @@ -568,7 +560,7 @@ AtomNetlist read_interchange_netlist(const char* ic_netlist_file, auto netlist_reader = message_reader.getRoot(); - NetlistReader reader(netlist, netlist_reader, netlist_id, ic_netlist_file, arch); + NetlistReader reader(netlist, netlist_reader, netlist_id, ic_netlist_file, arch.models, arch); return netlist; diff --git a/vpr/src/base/read_interchange_netlist.h b/vpr/src/base/read_interchange_netlist.h index 1b17b86ea5d..02a7546c660 100644 --- a/vpr/src/base/read_interchange_netlist.h +++ b/vpr/src/base/read_interchange_netlist.h @@ -1,8 +1,9 @@ #ifndef READ_INTERCHANGE_NETLIST_H #define READ_INTERCHANGE_NETLIST_H -#include "logic_types.h" + #include "atom_netlist_fwd.h" -#include "read_circuit.h" + +struct t_arch; AtomNetlist read_interchange_netlist(const char* ic_netlist_file, t_arch& arch); diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index 9c648607cae..eb2638ee4c0 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -463,7 +463,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p VTR_ASSERT(clb_nlist->block_ports(index).size() == (unsigned)pb_type->num_ports); } - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* A primitive type */ AtomBlockId blk_id = atom_ctx.netlist().find_block(pb->name); if (!blk_id) { @@ -823,7 +823,7 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route, //Why does this not use the output pin used to deterimine the rr node index? pb_route.insert(std::make_pair(rr_node_index, t_pb_route())); pb_route[rr_node_index].driver_pb_pin_id = pin_node[0][0]->pin_count_in_cluster; - pb_route[rr_node_index].pb_graph_pin = pin_node[0][0]; + pb_route[rr_node_index].pb_graph_pin = &pb->pb_graph_node->output_pins[out_port][i]; found = false; for (j = 0; j < pin_node[0][0]->num_output_edges; j++) { @@ -1092,7 +1092,7 @@ static size_t mark_constant_generators_rec(const t_pb* pb, const t_pb_routes& pb } } } - } else if (strcmp(pb->pb_graph_node->pb_type->blif_model, MODEL_INPUT) != 0) { + } else if (strcmp(pb->pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT) != 0) { const_gen = true; for (i = 0; i < pb->pb_graph_node->num_input_ports && const_gen == true; i++) { for (j = 0; j < pb->pb_graph_node->num_input_pins[i] && const_gen == true; j++) { @@ -1184,7 +1184,7 @@ static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { VTR_ASSERT_MSG(pb, "Atom block must have a matching PB"); const t_pb_graph_node* gnode = pb->pb_graph_node; - VTR_ASSERT_MSG(gnode->pb_type->model == atom_ctx.netlist().block_model(blk), + VTR_ASSERT_MSG(gnode->pb_type->model_id == atom_ctx.netlist().block_model(blk), "Atom block PB must match BLIF model"); for (int iport = 0; iport < gnode->num_input_ports; ++iport) { diff --git a/vpr/src/base/read_netlist.h b/vpr/src/base/read_netlist.h index e430f278bd5..090ded87a08 100644 --- a/vpr/src/base/read_netlist.h +++ b/vpr/src/base/read_netlist.h @@ -10,7 +10,9 @@ #ifndef READ_NETLIST_H #define READ_NETLIST_H -#include "vpr_types.h" +#include "atom_netlist_fwd.h" +#include "clustered_netlist_fwd.h" +#include "physical_types.h" ClusteredNetlist read_netlist(const char* net_file, const t_arch* arch, diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index aa6d52eb93e..75bf7385b61 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1945,6 +1945,31 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("0.5") .show_in(argparse::ShowIn::HELP_ONLY); + ap_grp.add_argument(args.appack_max_dist_th, "--appack_max_dist_th") + .help( + "Sets the maximum candidate distance thresholds for the logical block types" + "used by APPack. APPack uses the primitive-level placement produced by the" + "global placer to cluster primitives together. APPack uses the thresholds" + "here to ignore primitives which are too far away from the cluster being formed." + "\n" + "When this option is set to auto, VPR will select good values for these" + "thresholds based on the primitives contained within each logical block type." + "\n" + "Using this option, the user can set the maximum candidate distance threshold" + "of logical block types to something else. The strings passed in by the user" + "should be of the form :, where the regex string is" + "used to match the name of the logical block type to set, the first float" + "is a scaling term, and the second float is an offset. The threshold will" + "be set to max(scale * (W + H), offset), where W and H are the width and height" + "of the device. This allows the user to specify a threshold based on the" + "size of the device, while also preventing the number from going below offset" + "When multiple strings are provided, the thresholds are set from left to right," + "and any logical block types which have been unset will be set to their auto" + "values.") + .nargs('+') + .default_value({"auto"}) + .show_in(argparse::ShowIn::HELP_ONLY); + ap_grp.add_argument(args.ap_verbosity, "--ap_verbosity") .help( "Controls how verbose the AP flow's log messages will be. Higher " @@ -1972,14 +1997,14 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("auto") .show_in(argparse::ShowIn::HELP_ONLY); - pack_grp.add_argument(args.alpha_clustering, "--alpha_clustering") + pack_grp.add_argument(args.timing_gain_weight, "--timing_gain_weight") .help( "Parameter that weights the optimization of timing vs area. 0.0 focuses solely on" " area, 1.0 solely on timing.") .default_value("0.75") .show_in(argparse::ShowIn::HELP_ONLY); - pack_grp.add_argument(args.beta_clustering, "--beta_clustering") + pack_grp.add_argument(args.connection_gain_weight, "--connection_gain_weight") .help( "Parameter that weights the absorption of small nets vs signal sharing." " 0.0 focuses solely on sharing, 1.0 solely on small net absoprtion." @@ -2101,24 +2126,6 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("2") .show_in(argparse::ShowIn::HELP_ONLY); - pack_grp.add_argument(args.use_attraction_groups, "--use_attraction_groups") - .help("Whether attraction groups are used to make it easier to pack primitives in the same floorplan region together.") - .default_value("on") - .show_in(argparse::ShowIn::HELP_ONLY); - - pack_grp.add_argument(args.pack_num_moves, "--pack_num_moves") - .help( - "The number of moves that can be tried in packing stage") - .default_value("100000") - .show_in(argparse::ShowIn::HELP_ONLY); - - pack_grp.add_argument(args.pack_move_type, "--pack_move_type") - .help( - "The move type used in packing." - "The available values are: randomSwap, semiDirectedSwap, semiDirectedSameTypeSwap") - .default_value("semiDirectedSwap") - .show_in(argparse::ShowIn::HELP_ONLY); - auto& place_grp = parser.add_argument_group("placement options"); place_grp.add_argument(args.Seed, "--seed") @@ -2237,13 +2244,6 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); - place_grp.add_argument(args.enable_analytic_placer, "--enable_analytic_placer") - .help( - "Enables the analytic placer. " - "Once analytic placement is done, the result is passed through the quench phase of the annealing placer for local improvement") - .default_value("false") - .show_in(argparse::ShowIn::HELP_ONLY); - place_grp.add_argument(args.place_static_move_prob, "--place_static_move_prob") .help( "The percentage probabilities of different moves in Simulated Annealing placement. " @@ -2716,6 +2716,66 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("1.2") .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.enable_parallel_connection_router, "--enable_parallel_connection_router") + .help( + "Controls whether the MultiQueue-based parallel connection router is used during a single connection" + " routing. When enabled, the parallel connection router accelerates the path search for individual" + " source-sink connections using multi-threading without altering the net routing order.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.post_target_prune_fac, "--post_target_prune_fac") + .help( + "Controls the post-target pruning heuristic calculation in the parallel connection router." + " This parameter is used as a multiplicative factor applied to the VPR heuristic" + " (not guaranteed to be admissible, i.e., might over-predict the cost to the sink)" + " to calculate the 'stopping heuristic' when pruning nodes after the target has been" + " reached. The 'stopping heuristic' must be admissible for the path search algorithm" + " to guarantee optimal paths and be deterministic. Values of this parameter are" + " architecture-specific and have to be empirically found." + " This parameter has no effect if --enable_parallel_connection_router is not set.") + .default_value("1.2") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.post_target_prune_offset, "--post_target_prune_offset") + .help( + "Controls the post-target pruning heuristic calculation in the parallel connection router." + " This parameter is used as a subtractive offset together with --post_target_prune_fac" + " to apply an affine transformation on the VPR heuristic to calculate the 'stopping" + " heuristic'. The 'stopping heuristic' must be admissible for the path search" + " algorithm to guarantee optimal paths and be deterministic. Values of this" + " parameter are architecture-specific and have to be empirically found." + " This parameter has no effect if --enable_parallel_connection_router is not set.") + .default_value("0.0") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.multi_queue_num_threads, "--multi_queue_num_threads") + .help( + "Controls the number of threads used by MultiQueue-based parallel connection router." + " If not explicitly specified, defaults to 1, implying the parallel connection router" + " works in 'serial' mode using only one main thread to route." + " This parameter has no effect if --enable_parallel_connection_router is not set.") + .default_value("1") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.multi_queue_num_queues, "--multi_queue_num_queues") + .help( + "Controls the number of queues used by MultiQueue in the parallel connection router." + " Must be set >= 2. A common configuration for this parameter is the number of threads" + " used by MultiQueue * 4 (the number of queues per thread)." + " This parameter has no effect if --enable_parallel_connection_router is not set.") + .default_value("2") + .show_in(argparse::ShowIn::HELP_ONLY); + + route_timing_grp.add_argument(args.multi_queue_direct_draining, "--multi_queue_direct_draining") + .help( + "Controls whether to enable queue draining optimization for MultiQueue-based parallel connection" + " router. When enabled, queues can be emptied quickly by draining all elements if no further" + " solutions need to be explored in the path search to guarantee optimality or determinism after" + " reaching the target. This parameter has no effect if --enable_parallel_connection_router is not set.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.max_criticality, "--max_criticality") .help( "Sets the maximum fraction of routing cost derived from delay (vs routability) for any net." @@ -2945,6 +3005,16 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.generate_post_implementation_sdc, "--gen_post_implementation_sdc") + .help( + "Generates an SDC file including a list of constraints that would " + "replicate the timing constraints that the timing analysis within " + "VPR followed during the flow. This can be helpful for flows that " + "use external timing analysis tools that have additional capabilities " + "or more detailed delay models than what VPR uses") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.timing_report_npaths, "--timing_report_npaths") .help("Controls how many timing paths are reported.") .default_value("100") @@ -2997,6 +3067,16 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("unconnected") .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.post_synth_netlist_module_parameters, "--post_synth_netlist_module_parameters") + .help( + "Controls whether the post-synthesis netlist output by VTR can use Verilog parameters " + "or not. When using the post-synthesis netlist for external timing analysis, " + "some tools cannot accept the netlist if it contains parameters. By setting " + "this option to off, VPR will try to represent the netlist using non-parameterized " + "modules\n") + .default_value("on") + .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.write_timing_summary, "--write_timing_summary") .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); @@ -3004,7 +3084,13 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio analysis_grp.add_argument(args.skip_sync_clustering_and_routing_results, "--skip_sync_clustering_and_routing_results") .help( "Select to skip the synchronization on clustering results based on routing optimization results." - "Note that when this sync-up is disabled, clustering results may be wrong (leading to incorrect bitstreams)!") + "Note that when this sync-up is disabled, clustering results may be wrong (leading to incorrect bitstreams)!"); + + analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") + .help( + "Generates a net timing report in CSV format, reporting the delay and slack\n" + "for every routed connection in the design.\n" + "The report is saved as 'report_net_timing.csv'.") .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 42ce1f5c359..03153ac1446 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -1,7 +1,8 @@ #ifndef READ_OPTIONS_H #define READ_OPTIONS_H -#include "read_blif.h" +#include "arch_types.h" +#include "read_circuit.h" #include "vpr_types.h" #include "constant_nets.h" #include "ap_flow_enums.h" @@ -102,14 +103,15 @@ struct t_options { argparse::ArgValue ap_partial_legalizer; argparse::ArgValue ap_full_legalizer; argparse::ArgValue ap_detailed_placer; + argparse::ArgValue> appack_max_dist_th; argparse::ArgValue ap_verbosity; argparse::ArgValue ap_timing_tradeoff; /* Clustering options */ argparse::ArgValue connection_driven_clustering; argparse::ArgValue allow_unrelated_clustering; - argparse::ArgValue alpha_clustering; - argparse::ArgValue beta_clustering; + argparse::ArgValue timing_gain_weight; + argparse::ArgValue connection_gain_weight; argparse::ArgValue timing_driven_clustering; argparse::ArgValue cluster_seed_type; argparse::ArgValue enable_clustering_pin_feasibility_filter; @@ -120,9 +122,6 @@ struct t_options { argparse::ArgValue pack_feasible_block_array_size; argparse::ArgValue> pack_high_fanout_threshold; argparse::ArgValue pack_verbosity; - argparse::ArgValue use_attraction_groups; - argparse::ArgValue pack_num_moves; - argparse::ArgValue pack_move_type; /* Placement options */ argparse::ArgValue Seed; argparse::ArgValue ShowPlaceTiming; @@ -140,7 +139,6 @@ struct t_options { argparse::ArgValue placement_saves_per_temperature; argparse::ArgValue place_effort_scaling; argparse::ArgValue place_delta_delay_matrix_calculation_method; - argparse::ArgValue enable_analytic_placer; argparse::ArgValue> place_static_move_prob; argparse::ArgValue place_high_fanout_net; argparse::ArgValue place_bounding_box_mode; @@ -233,6 +231,12 @@ struct t_options { argparse::ArgValue astar_fac; argparse::ArgValue astar_offset; argparse::ArgValue router_profiler_astar_fac; + argparse::ArgValue enable_parallel_connection_router; + argparse::ArgValue post_target_prune_fac; + argparse::ArgValue post_target_prune_offset; + argparse::ArgValue multi_queue_num_threads; + argparse::ArgValue multi_queue_num_queues; + argparse::ArgValue multi_queue_direct_draining; argparse::ArgValue max_criticality; argparse::ArgValue criticality_exp; argparse::ArgValue router_init_wirelength_abort_threshold; @@ -259,14 +263,17 @@ struct t_options { argparse::ArgValue full_stats; argparse::ArgValue Generate_Post_Synthesis_Netlist; argparse::ArgValue Generate_Post_Implementation_Merged_Netlist; + argparse::ArgValue generate_post_implementation_sdc; argparse::ArgValue timing_report_npaths; argparse::ArgValue timing_report_detail; argparse::ArgValue timing_report_skew; argparse::ArgValue echo_dot_timing_graph_node; argparse::ArgValue post_synth_netlist_unconn_input_handling; argparse::ArgValue post_synth_netlist_unconn_output_handling; + argparse::ArgValue post_synth_netlist_module_parameters; argparse::ArgValue write_timing_summary; argparse::ArgValue skip_sync_clustering_and_routing_results; + argparse::ArgValue generate_net_timing_report; }; argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_options& args); diff --git a/vpr/src/base/read_place.h b/vpr/src/base/read_place.h index 9fa6eee6328..dbce07b77ef 100644 --- a/vpr/src/base/read_place.h +++ b/vpr/src/base/read_place.h @@ -6,6 +6,8 @@ #include class PlacerState; +class BlkLocRegistry; +class DeviceGrid; class ClusterBlockId; struct t_block_loc; diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index ead89961aa1..597aee2f002 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -13,11 +13,8 @@ * other file's information */ -#include #include #include -#include -#include #include #include @@ -47,7 +44,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN static void process_nets(const Netlist<>& net_list, std::ifstream& fp, ClusterNetId inet, std::string name, std::vector input_tokens, const char* filename, int& lineno, bool is_flat); static void process_global_blocks(const Netlist<>& net_list, std::ifstream& fp, ClusterNetId inet, const char* filename, int& lineno, bool is_flat); static void format_coordinates(int& layer_num, int& x, int& y, std::string coord, ClusterNetId net, const char* filename, const int lineno); -static void format_pin_info(std::string& pb_name, std::string& port_name, int& pb_pin_num, std::string input); +static void format_pin_info(std::string& pb_name, std::string& port_name, int& pb_pin_num, const std::string& input); static std::string format_name(std::string name); static bool check_rr_graph_connectivity(RRNodeId prev_node, RRNodeId node); void print_route(const Netlist<>& net_list, FILE* fp, bool is_flat); @@ -299,7 +296,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN /* Verify types and ptc*/ if (tokens[2] == "SOURCE" || tokens[2] == "SINK" || tokens[2] == "OPIN" || tokens[2] == "IPIN") { const auto& type = device_ctx.grid.get_physical_type({x, y, layer_num}); - if (tokens[4 + offset] == "Pad:" && !is_io_type(type)) { + if (tokens[4 + offset] == "Pad:" && !type->is_io()) { vpr_throw(VPR_ERROR_ROUTE, filename, lineno, "Node %d is of the wrong type", inode); } @@ -322,7 +319,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN if (tokens[6 + offset] != "Switch:") { /*This is an opin or ipin, process its pin nums*/ auto type = device_ctx.grid.get_physical_type({x, y, layer_num}); - if (!is_io_type(type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) { + if (!type->is_io() && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) { int pin_num = rr_graph.node_pin_num(RRNodeId(inode)); int width_offset = device_ctx.grid.get_width_offset({x, y, layer_num}); int height_offset = device_ctx.grid.get_height_offset({x, y, layer_num}); @@ -497,7 +494,7 @@ static void format_coordinates(int& layer_num, int& x, int& y, std::string coord * @brief Parse the pin info in the form of pb_name.port_name[pb_pin_num] * into its appropriate variables */ -static void format_pin_info(std::string& pb_name, std::string& port_name, int& pb_pin_num, std::string input) { +static void format_pin_info(std::string& pb_name, std::string& port_name, int& pb_pin_num, const std::string& input) { std::stringstream pb_info(input); std::getline(pb_info, pb_name, '.'); std::getline(pb_info, port_name, '['); @@ -519,7 +516,7 @@ static std::string format_name(std::string name) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "%s should be enclosed by parenthesis", name.c_str()); - return nullptr; + return {}; } } @@ -536,7 +533,7 @@ static bool check_rr_graph_connectivity(RRNodeId prev_node, RRNodeId node) { auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; // If it's starting a new sub branch this is ok - if (rr_graph.node_type(prev_node) == SINK) return true; + if (rr_graph.node_type(prev_node) == e_rr_type::SINK) return true; for (RREdgeId edge : rr_graph.edge_range(prev_node)) { //If the sink node is reachable by previous node return true @@ -582,7 +579,7 @@ void print_route(const Netlist<>& net_list, while (tptr != nullptr) { RRNodeId inode = RRNodeId(tptr->index); - t_rr_type rr_type = rr_graph.node_type(inode); + e_rr_type rr_type = rr_graph.node_type(inode); int ilow = rr_graph.node_xlow(inode); int jlow = rr_graph.node_ylow(inode); int layer_num = rr_graph.node_layer(inode); @@ -595,31 +592,34 @@ void print_route(const Netlist<>& net_list, fprintf(fp, "to (%d,%d,%d) ", rr_graph.node_xhigh(inode), rr_graph.node_yhigh(inode), layer_num); + t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num}); + switch (rr_type) { - case IPIN: - case OPIN: - if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) { + case e_rr_type::IPIN: + case e_rr_type::OPIN: + + if (physical_tile->is_io()) { fprintf(fp, " Pad: "); } else { /* IO Pad. */ fprintf(fp, " Pin: "); } break; - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: fprintf(fp, " Track: "); break; - case SOURCE: - case SINK: - if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) { + case e_rr_type::SOURCE: + case e_rr_type::SINK: + if (physical_tile->is_io()) { fprintf(fp, " Pad: "); } else { /* IO Pad. */ fprintf(fp, " Class: "); } break; - case MEDIUM: + case e_rr_type::MEDIUM: fprintf(fp, " INDEX: "); break; @@ -632,8 +632,7 @@ void print_route(const Netlist<>& net_list, fprintf(fp, "%d ", rr_graph.node_ptc_num(inode)); - auto physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num}); - if (!is_io_type(physical_tile) && (rr_type == IPIN || rr_type == OPIN)) { + if (!physical_tile->is_io() && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) { int pin_num = rr_graph.node_pin_num(inode); int xoffset = device_ctx.grid.get_width_offset({ilow, jlow, layer_num}); int yoffset = device_ctx.grid.get_height_offset({ilow, jlow, layer_num}); @@ -658,7 +657,7 @@ void print_route(const Netlist<>& net_list, fprintf(fp, "Switch: %d", int(tptr->iswitch)); //Save net pin index for sinks - if (rr_type == SINK) { + if (rr_type == e_rr_type::SINK) { fprintf(fp, " Net_pin_index: %d", tptr->net_pin_index); } diff --git a/vpr/src/base/read_route.h b/vpr/src/base/read_route.h index 226a104a0b3..4758b0cf646 100644 --- a/vpr/src/base/read_route.h +++ b/vpr/src/base/read_route.h @@ -5,13 +5,10 @@ * This is used to perform --analysis only */ -#ifndef READ_ROUTE_H -#define READ_ROUTE_H +#pragma once #include "netlist.h" #include "vpr_types.h" bool read_route(const char* route_file, const t_router_opts& RouterOpts, bool verify_file_digests, bool is_flat); void print_route(const Netlist<>& net_list, const char* placement_file, const char* route_file, bool is_flat); - -#endif /* READ_ROUTE_H */ diff --git a/vpr/src/base/setup_noc.h b/vpr/src/base/setup_noc.h index 9b728e0f0ab..4b11f59259a 100644 --- a/vpr/src/base/setup_noc.h +++ b/vpr/src/base/setup_noc.h @@ -32,7 +32,6 @@ */ #include -#include #include "device_grid.h" #include "vpr_context.h" diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp index 774235bf2cc..08927b500ea 100644 --- a/vpr/src/base/stats.cpp +++ b/vpr/src/base/stats.cpp @@ -6,8 +6,10 @@ #include #include +#include "physical_types.h" #include "physical_types_util.h" #include "route_tree.h" +#include "vpr_utils.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_ndmatrix.h" @@ -89,10 +91,7 @@ void routing_stats(const Netlist<>& net_list, auto type = device_ctx.grid.get_physical_type({i, j, layer_num}); int width_offset = device_ctx.grid.get_width_offset({i, j, layer_num}); int height_offset = device_ctx.grid.get_height_offset({i, j, layer_num}); - if (width_offset == 0 - && height_offset == 0 - && !is_io_type(type) - && type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + if (width_offset == 0 && height_offset == 0 && !type->is_io() && !type->is_empty()) { if (type->area == UNDEFINED) { area += grid_logic_tile_area * type->width * type->height; } else { @@ -109,7 +108,7 @@ void routing_stats(const Netlist<>& net_list, for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { t_pl_loc block_loc = block_locs[blk_id].loc; auto type = physical_tile_type(block_loc); - if (!is_io_type(type)) { + if (!type->is_io()) { if (type->area == UNDEFINED) { used_area += grid_logic_tile_area * type->width * type->height; } else { @@ -310,13 +309,13 @@ static void load_channel_occupancies(const Netlist<>& net_list, for (const RouteTreeNode& rt_node : tree.value().all_nodes()) { RRNodeId inode = rt_node.inode; - t_rr_type rr_type = rr_graph.node_type(inode); + e_rr_type rr_type = rr_graph.node_type(inode); - if (rr_type == CHANX) { + if (rr_type == e_rr_type::CHANX) { int j = rr_graph.node_ylow(inode); for (int i = rr_graph.node_xlow(inode); i <= rr_graph.node_xhigh(inode); i++) chanx_occ[i][j]++; - } else if (rr_type == CHANY) { + } else if (rr_type == e_rr_type::CHANY) { int i = rr_graph.node_xlow(inode); for (int j = rr_graph.node_ylow(inode); j <= rr_graph.node_yhigh(inode); j++) chany_occ[i][j]++; @@ -344,7 +343,7 @@ void get_num_bends_and_length(ParentNetId inet, int* bends_ptr, int* len_ptr, in "in get_num_bends_and_length: net #%lu has no routing.\n", size_t(inet)); } - t_rr_type prev_type = rr_graph.node_type(tree->root().inode); + e_rr_type prev_type = rr_graph.node_type(tree->root().inode); RouteTree::iterator it = tree->all_nodes().begin(); RouteTree::iterator end = tree->all_nodes().end(); ++it; /* start from the next node after source */ @@ -352,18 +351,18 @@ void get_num_bends_and_length(ParentNetId inet, int* bends_ptr, int* len_ptr, in for (; it != end; ++it) { const RouteTreeNode& rt_node = *it; RRNodeId inode = rt_node.inode; - t_rr_type curr_type = rr_graph.node_type(inode); + e_rr_type curr_type = rr_graph.node_type(inode); - if (curr_type == CHANX || curr_type == CHANY) { + if (curr_type == e_rr_type::CHANX || curr_type == e_rr_type::CHANY) { segments++; length += rr_graph.node_length(inode); - if (curr_type != prev_type && (prev_type == CHANX || prev_type == CHANY)) + if (curr_type != prev_type && (prev_type == e_rr_type::CHANX || prev_type == e_rr_type::CHANY)) bends++; } /* The all_nodes iterator walks all nodes in the tree. If we are at a leaf and going back to the top, prev_type is invalid: just set it to SINK */ - prev_type = rt_node.is_leaf() ? SINK : curr_type; + prev_type = rt_node.is_leaf() ? e_rr_type::SINK : curr_type; } *bends_ptr = bends; @@ -471,7 +470,7 @@ void print_lambda() { t_pl_loc block_loc = block_locs[blk_id].loc; auto type = physical_tile_type(block_loc); VTR_ASSERT(type != nullptr); - if (!is_io_type(type)) { + if (!type->is_io()) { for (int ipin = 0; ipin < type->num_pins; ipin++) { if (get_pin_type_from_pin_physical_num(type, ipin) == RECEIVER) { ClusterNetId net_id = cluster_ctx.clb_nlist.block_net(blk_id, ipin); diff --git a/vpr/src/base/stats.h b/vpr/src/base/stats.h index 5f9e50e0700..eb79a2c3946 100644 --- a/vpr/src/base/stats.h +++ b/vpr/src/base/stats.h @@ -1,9 +1,11 @@ #pragma once + +#include #include -#include -#include -#include "vpr_types.h" #include "netlist.h" +#include "rr_graph_type.h" + +class DeviceGrid; /** * @brief Prints out various statistics about the current routing. diff --git a/vpr/src/base/user_route_constraints.cpp b/vpr/src/base/user_route_constraints.cpp index b6d3f1b0384..fa97ed6163c 100644 --- a/vpr/src/base/user_route_constraints.cpp +++ b/vpr/src/base/user_route_constraints.cpp @@ -1,4 +1,6 @@ #include "user_route_constraints.h" +#include +#include "vpr_error.h" void UserRouteConstraints::add_route_constraint(std::string net_name, RoutingScheme route_scheme) { route_constraints_.insert({net_name, route_scheme}); diff --git a/vpr/src/base/user_route_constraints.h b/vpr/src/base/user_route_constraints.h index 62ba08cda1d..0510072a36a 100644 --- a/vpr/src/base/user_route_constraints.h +++ b/vpr/src/base/user_route_constraints.h @@ -2,9 +2,8 @@ #define USER_ROUTE_CONSTRAINTS_H #include "clock_modeling.h" -#include "vpr_error.h" +#include #include -#include /** * @brief This class specifies a routing scheme for a global net. diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 6b2acb57dcf..7eda86f8dd6 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -112,6 +112,12 @@ static void free_complex_block_types(); static void free_device(const t_det_routing_arch& routing_arch); static void free_circuit(); +/** Set all port equivalences in the architecture to NONE. This is used in the + * case of the flat router where port equivalence does not make sense. + * We could just keep it set and ignore it, but that prevents compatibility + * with OpenFPGA which takes it seriously. */ +static void unset_port_equivalences(DeviceContext& device_ctx); + /* Local subroutines end */ ///@brief Display general VPR information @@ -280,8 +286,6 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a true, &vpr_setup->FileNameOpts, arch, - &vpr_setup->user_models, - &vpr_setup->library_models, &vpr_setup->NetlistOpts, &vpr_setup->PackerOpts, &vpr_setup->PlacerOpts, @@ -290,7 +294,7 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a &vpr_setup->AnalysisOpts, &vpr_setup->NocOpts, &vpr_setup->ServerOpts, - &vpr_setup->RoutingArch, + vpr_setup->RoutingArch, &vpr_setup->PackerRRGraph, vpr_setup->Segments, &vpr_setup->Timing, @@ -331,17 +335,17 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a auto& timing_ctx = g_vpr_ctx.mutable_timing(); { vtr::ScopedStartFinishTimer t("Build Timing Graph"); - timing_ctx.graph = TimingGraphBuilder(atom_ctx.netlist(), atom_ctx.mutable_lookup()).timing_graph(options->allow_dangling_combinational_nodes); + timing_ctx.graph = TimingGraphBuilder(atom_ctx.netlist(), atom_ctx.mutable_lookup(), arch->models).timing_graph(options->allow_dangling_combinational_nodes); VTR_LOG(" Timing Graph Nodes: %zu\n", timing_ctx.graph->nodes().size()); VTR_LOG(" Timing Graph Edges: %zu\n", timing_ctx.graph->edges().size()); VTR_LOG(" Timing Graph Levels: %zu\n", timing_ctx.graph->levels().size()); } { - print_netlist_clock_info(atom_ctx.netlist()); + print_netlist_clock_info(atom_ctx.netlist(), arch->models); } { vtr::ScopedStartFinishTimer t("Load Timing Constraints"); - timing_ctx.constraints = read_sdc(vpr_setup->Timing, atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph); + timing_ctx.constraints = read_sdc(vpr_setup->Timing, atom_ctx.netlist(), atom_ctx.lookup(), arch->models, *timing_ctx.graph); } { set_terminate_if_timing_fails(options->terminate_if_timing_fails); @@ -366,6 +370,25 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a device_ctx.pad_loc_type = vpr_setup->PlacerOpts.pad_loc_type; } +/** Port equivalence does not make sense during flat routing. + * Remove port equivalence from all ports in the architecture */ +static void unset_port_equivalences(DeviceContext& device_ctx) { + for (auto& physical_type : device_ctx.physical_tile_types) { + for (auto& sub_tile : physical_type.sub_tiles) { + for (auto& port : sub_tile.ports) { + port.equivalent = PortEquivalence::NONE; + } + } + } + for (auto& logical_type : device_ctx.logical_block_types) { + if (!logical_type.pb_type) + continue; + for (int i = 0; i < logical_type.pb_type->num_ports; i++) { + logical_type.pb_type->ports[i].equivalent = PortEquivalence::NONE; + } + } +} + bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { if (vpr_setup.exit_before_pack) { VTR_LOG_WARN("Exiting before packing as requested.\n"); @@ -444,6 +467,10 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { bool is_flat = vpr_setup.RouterOpts.flat_routing; const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + if (is_flat) { + VTR_LOG_WARN("Disabling port equivalence in the architecture since flat routing is enabled.\n"); + unset_port_equivalences(g_vpr_ctx.mutable_device()); + } RouteStatus route_status; { //Route route_status = vpr_route_flow(router_net_list, vpr_setup, arch, is_flat); @@ -484,8 +511,6 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.mutable_device(); - device_ctx.arch = &Arch; - /* *Load the device grid */ @@ -623,6 +648,7 @@ bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) { // The Prepacker object performs prepacking and stores the pack molecules. // As long as the molecules are used, this object must persist. const Prepacker prepacker(g_vpr_ctx.atom().netlist(), + arch.models, g_vpr_ctx.device().logical_block_types); // Setup pre-clustering timing analysis @@ -636,7 +662,7 @@ bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) { vpr_setup.PackerOpts.device_layout, vpr_setup.AnalysisOpts); - return try_pack(vpr_setup.PackerOpts, vpr_setup.AnalysisOpts, + return try_pack(vpr_setup.PackerOpts, vpr_setup.AnalysisOpts, vpr_setup.APOpts, arch, vpr_setup.PackerRRGraph, prepacker, @@ -707,7 +733,6 @@ bool vpr_load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { // set up the device grid for the legalizer auto& device_ctx = g_vpr_ctx.mutable_device(); - device_ctx.arch = &arch; device_ctx.grid = create_device_grid(vpr_setup.device_layout, arch.grid_layouts); if (device_ctx.grid.get_num_layers() > 1) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Legalizer currently only supports single layer devices.\n"); @@ -809,7 +834,7 @@ void vpr_place(const Netlist<>& net_list, vpr_setup.AnalysisOpts, vpr_setup.NocOpts, arch.Chans, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, arch.directs, g_vpr_ctx.atom().flat_placement_info(), @@ -827,7 +852,7 @@ void vpr_place(const Netlist<>& net_list, } void vpr_load_placement(t_vpr_setup& vpr_setup, - const std::vector directs) { + const std::vector& directs) { vtr::ScopedStartFinishTimer timer("Load Placement"); const auto& device_ctx = g_vpr_ctx.device(); @@ -1023,7 +1048,7 @@ RouteStatus vpr_route_fixed_W(const Netlist<>& net_list, fixed_channel_width, vpr_setup.RouterOpts, vpr_setup.AnalysisOpts, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, net_delay, timing_info, @@ -1060,7 +1085,7 @@ RouteStatus vpr_route_min_W(const Netlist<>& net_list, &arch, router_opts.verify_binary_search, router_opts.min_channel_width_hint, - &vpr_setup.RoutingArch, + vpr_setup.RoutingArch, vpr_setup.Segments, net_delay, timing_info, @@ -1100,7 +1125,7 @@ RouteStatus vpr_load_routing(t_vpr_setup& vpr_setup, void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_width_fac, bool is_flat) { auto& device_ctx = g_vpr_ctx.mutable_device(); - auto det_routing_arch = &vpr_setup.RoutingArch; + t_det_routing_arch& det_routing_arch = vpr_setup.RoutingArch; auto& router_opts = vpr_setup.RouterOpts; e_graph_type graph_type; @@ -1109,12 +1134,11 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi graph_type = e_graph_type::GLOBAL; graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); - /* Branch on tileable routing */ - if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + if (det_routing_arch.directionality == UNI_DIRECTIONAL && det_routing_arch.tileable) { graph_type = e_graph_type::UNIDIR_TILEABLE; } - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } t_chan_width chan_width = init_chan(chan_width_fac, arch.Chans, graph_directionality); @@ -1268,8 +1292,6 @@ void vpr_setup_vpr(t_options* Options, const bool readArchFile, t_file_name_opts* FileNameOpts, t_arch* Arch, - t_model** user_models, - t_model** library_models, t_netlist_opts* NetlistOpts, t_packer_opts* PackerOpts, t_placer_opts* PlacerOpts, @@ -1278,7 +1300,7 @@ void vpr_setup_vpr(t_options* Options, t_analysis_opts* AnalysisOpts, t_noc_opts* NocOpts, t_server_opts* ServerOpts, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, std::vector** PackerRRGraph, std::vector& Segments, t_timing_inf* Timing, @@ -1293,8 +1315,6 @@ void vpr_setup_vpr(t_options* Options, readArchFile, FileNameOpts, Arch, - user_models, - library_models, NetlistOpts, PackerOpts, PlacerOpts, @@ -1392,8 +1412,7 @@ bool vpr_analysis_flow(const Netlist<>& net_list, } std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing"; - write_packing_results_to_xml(vpr_setup.PackerOpts.global_clocks, - Arch.architecture_id, + write_packing_results_to_xml(Arch.architecture_id, post_routing_packing_output_file_name.c_str()); } else { VTR_LOG_WARN("Synchronization between packing and routing results is not applied due to illegal circuit implementation\n"); @@ -1460,12 +1479,16 @@ void vpr_analysis(const Netlist<>& net_list, //Write the post-synthesis netlist if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) { netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, - vpr_setup.AnalysisOpts); + Arch.models, vpr_setup.Timing, vpr_setup.clock_modeling, vpr_setup.AnalysisOpts); } //Write the post-implementation merged netlist if (vpr_setup.AnalysisOpts.gen_post_implementation_merged_netlist) { - merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, vpr_setup.AnalysisOpts); + merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, Arch.models, vpr_setup.AnalysisOpts); + } + + if (vpr_setup.AnalysisOpts.generate_net_timing_report) { + generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc); } //Do power analysis @@ -1511,7 +1534,7 @@ void vpr_power_estimation(const t_vpr_setup& vpr_setup, /* Initialize the power module */ bool power_error = power_init(vpr_setup.FileNameOpts.PowerFile.c_str(), - vpr_setup.FileNameOpts.CmosTechFile.c_str(), &Arch, &vpr_setup.RoutingArch); + vpr_setup.FileNameOpts.CmosTechFile.c_str(), &Arch, vpr_setup.RoutingArch); if (power_error) { VTR_LOG_ERROR("Power initialization failed.\n"); } @@ -1522,8 +1545,7 @@ void vpr_power_estimation(const t_vpr_setup& vpr_setup, VTR_LOG("Running power estimation\n"); /* Run power estimation */ - e_power_ret_code power_ret_code = power_total(&power_runtime_s, vpr_setup, - &Arch, &vpr_setup.RoutingArch); + e_power_ret_code power_ret_code = power_total(&power_runtime_s, vpr_setup, &Arch, vpr_setup.RoutingArch); /* Check for errors/warnings */ if (power_ret_code == POWER_RET_CODE_ERRORS) { diff --git a/vpr/src/base/vpr_api.h b/vpr/src/base/vpr_api.h index 7eda169ba5e..02fb56a46b4 100644 --- a/vpr/src/base/vpr_api.h +++ b/vpr/src/base/vpr_api.h @@ -31,10 +31,6 @@ #include "physical_types.h" #include "vpr_types.h" #include "read_options.h" -#include "globals.h" -#include "read_xml_arch_file.h" -#include "vpr_utils.h" -#include "place_macro.h" #include "timing_info_fwd.h" #include "echo_files.h" #include "RoutingDelayCalculator.h" @@ -82,7 +78,7 @@ void vpr_place(const Netlist<>& net_list, ///@brief Loads a previous placement void vpr_load_placement(t_vpr_setup& vpr_setup, - const std::vector directs); + const std::vector& directs); /* Routing */ @@ -178,8 +174,6 @@ void vpr_setup_vpr(t_options* Options, const bool readArchFile, t_file_name_opts* FileNameOpts, t_arch* Arch, - t_model** user_models, - t_model** library_models, t_netlist_opts* NetlistOpts, t_packer_opts* PackerOpts, t_placer_opts* PlacerOpts, @@ -188,7 +182,7 @@ void vpr_setup_vpr(t_options* Options, t_analysis_opts* AnalysisOpts, t_noc_opts* NocOpts, t_server_opts* ServerOpts, - t_det_routing_arch* RoutingArch, + t_det_routing_arch& RoutingArch, std::vector** PackerRRGraph, std::vector& Segments, t_timing_inf* Timing, diff --git a/vpr/src/base/vpr_constraints_reader.cpp b/vpr/src/base/vpr_constraints_reader.cpp index 57c17d73019..f4a806deeb3 100644 --- a/vpr/src/base/vpr_constraints_reader.cpp +++ b/vpr/src/base/vpr_constraints_reader.cpp @@ -1,3 +1,4 @@ +#include "constraints_load.h" #include "vpr_constraints_serializer.h" #include "vpr_constraints_uxsdcxx.h" diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index 409a7702661..08d6bee73cb 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -1,14 +1,12 @@ #ifndef VPR_CONSTRAINTS_SERIALIZER_H_ #define VPR_CONSTRAINTS_SERIALIZER_H_ +#include #include "region.h" #include "vpr_constraints.h" #include "partition.h" #include "partition_region.h" -#include "echo_files.h" -#include "constraints_load.h" #include "vtr_log.h" -#include "vtr_error.h" #include "globals.h" //for the g_vpr_ctx #include "clock_modeling.h" diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index dcab8832f53..47dd84843d4 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -11,6 +11,7 @@ #include "user_place_constraints.h" #include "user_route_constraints.h" #include "vpr_types.h" +#include "vtr_cache.h" #include "vtr_optional.h" #include "vtr_vector.h" #include "vtr_vector_map.h" diff --git a/vpr/src/base/vpr_types.cpp b/vpr/src/base/vpr_types.cpp index 22a644a2d07..84437530f1c 100644 --- a/vpr/src/base/vpr_types.cpp +++ b/vpr/src/base/vpr_types.cpp @@ -2,6 +2,8 @@ #include #include "vpr_types.h" #include "globals.h" +#include "logic_types.h" +#include "vpr_utils.h" t_ext_pin_util_targets::t_ext_pin_util_targets(float default_in_util, float default_out_util) { defaults_.input_pin_util = default_in_util; @@ -362,10 +364,10 @@ t_pb* t_pb::find_mutable_pb(const t_pb_graph_node* gnode) { return nullptr; //Not found } -const t_pb* t_pb::find_pb_for_model(const std::string& blif_model) const { +const t_pb* t_pb::find_pb_for_model(LogicalModelId blif_model_id) const { //Base case - const t_model* model = pb_graph_node->pb_type->model; - if (model && model->name == blif_model) { + LogicalModelId model_id = pb_graph_node->pb_type->model_id; + if (model_id.is_valid() && model_id == blif_model_id) { return this; } @@ -376,7 +378,7 @@ const t_pb* t_pb::find_pb_for_model(const std::string& blif_model) const { for (int ipb = 0; ipb < get_num_children_of_type(ichild_type); ++ipb) { const t_pb* child_pb = &child_pbs[ichild_type][ipb]; - const t_pb* matching_pb = child_pb->find_pb_for_model(blif_model); + const t_pb* matching_pb = child_pb->find_pb_for_model(blif_model_id); if (matching_pb) { return this; } diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 44d12cedf36..f96a9a8346b 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -21,16 +21,12 @@ * The t_pb hierarchy follows what is described by t_pb_graph_node */ -#ifndef VPR_TYPES_H -#define VPR_TYPES_H +#pragma once #include -#include -#include #include #include #include "ap_flow_enums.h" -#include "arch_types.h" #include "atom_netlist_fwd.h" #include "clustered_netlist_fwd.h" #include "constant_nets.h" @@ -38,18 +34,12 @@ #include "heap_type.h" #include "vtr_assert.h" -#include "vtr_ndmatrix.h" #include "vtr_vector.h" -#include "vtr_util.h" #include "vtr_flat_map.h" -#include "vtr_cache.h" -#include "vtr_string_view.h" -#include "vtr_dynamic_bitset.h" #include "rr_node_types.h" #include "rr_graph_fwd.h" #include "rr_graph_cost.h" #include "rr_graph_type.h" -#include "vtr_vector_map.h" /******************************************************************************* * Global data types and constants @@ -312,7 +302,7 @@ class t_pb { */ t_pb* find_mutable_pb(const t_pb_graph_node* gnode); - const t_pb* find_pb_for_model(const std::string& blif_model) const; + const t_pb* find_pb_for_model(LogicalModelId blif_model_id) const; ///@brief Returns the root pb containing this pb const t_pb* root_pb() const; @@ -706,17 +696,75 @@ enum e_stage_action { /** * @brief Options for packing * - * TODO: document each packing parameter + * @param circuit_file_name + * Path to technology mapped user circuit in BLIF format. + * @param output_file + * Path to packed user circuit in net format. + * @param timing_driven + * Whether or not to do timing driven clustering. (Default: on) + * @param timing_gain_weight + * Controls the optimization of timing vs area in timing driven + * clustering. + * A value of 0 focuses only on area; 1 focuses only on timing. + * (Default: 0.75) + * @param connection_gain_weight + * Controls the optimization of smaller net absorption vs. signal + * sharing in connection driven clustering. + * A value of 0 focuses solely on signal sharing; a value of 1 + * focuses solely on absorbing smaller nets into a cluster. + * (Default: 0.9) + * @param cluster_seed_type + * Selection algorithm for selecting next seed. (Default: blend2 if + * timing_driven is on; max_inputs otherwise) + * @param target_device_utilization + * Sets the target device utilization. (Default: 1.0) + * @param allow_unrelated_clustering + * Allows primitives which have no attraction to the given cluster + * to be packed into it. (Default: auto) + * @param connection_driven + * Controls whether or not packing prioritizes the absorption of nets + * with fewer connections into a complex logic block over nets with + * more connections. (Default: on) + * @param pack_verbosity + * Controls how verbose clustering's output is. (Default: 2) + * @param enable_pin_feasibility_filter + * Counts the number of available pins in groups/classes of mutually + * connected pins within a cluster, then filters out candidate + * primitives/atoms/molecules for which the cluster has insufficient + * pins to route (without performing a full routing). (Default: on) + * @param balance_block_type_utilization + * If enabled, when a primitive can potentially be mapped to multiple + * block types the packer will pick the block type which (currently) + * has the lowest utilization. (Default: auto) + * @param target_external_pin_util + * Sets the external pin utilization target. (Default: auto) + * @param prioritize_transitive_connectivity + * Whether transitive connectivity is prioritized over high-fanout + * connectivity. (Default: on) + * @param feasible_block_array_size + * Max size of the priority queue for candidates that pass the early + * filter legality test, but not the more detailed routing test. + * (Default: 30) + * @param doPacking + * Run packing stage. + * @param device_layout + * Controls which device layout/floorplan is used from the + * architecture file. (Default: smallest device which satisfies the + * circuit's resource requirements) + * @param timing_update_type + * Controls how timing analysis updates are performed. (Default: auto) + * @param load_flat_placement + * Whether to reconstruct a packing solution from a flat placement + * file. (Default: off; on if is on) */ struct t_packer_opts { std::string circuit_file_name; std::string sdc_file_name; std::string output_file; - bool global_clocks; bool timing_driven; enum e_cluster_seed cluster_seed_type; - float alpha; - float beta; + float timing_gain_weight; + float connection_gain_weight; float target_device_utilization; e_unrelated_clustering allow_unrelated_clustering; bool connection_driven; @@ -731,9 +779,6 @@ struct t_packer_opts { e_stage_action doPacking; std::string device_layout; e_timing_update_type timing_update_type; - bool use_attraction_groups; - int pack_num_moves; - std::string pack_move_type; bool load_flat_placement = false; }; @@ -1026,14 +1071,6 @@ struct t_placer_opts { std::string allowed_tiles_for_delay_model; e_place_delta_delay_algorithm place_delta_delay_matrix_calculation_method; - - /* - * @brief enables the analytic placer. - * - * Once analytic placement is done, the result is passed through the quench phase - * of the annealing placer for local improvement - */ - bool enable_analytic_placer; }; /****************************************************************** @@ -1059,6 +1096,11 @@ struct t_placer_opts { * @param ap_timing_tradeoff * A trade-off parameter used to decide how focused the AP flow * should be on optimizing timing over wirelength. + * @param appack_max_dist_th + * Array of string passed by the user to configure the max candidate + * distance thresholds. + * @param num_threads + * The number of threads the AP flow can use. * @param log_verbosity * The verbosity level of log messages in the AP flow, with higher * values leading to more verbose messages. @@ -1076,6 +1118,10 @@ struct t_ap_opts { float ap_timing_tradeoff; + std::vector appack_max_dist_th; + + unsigned num_threads; + int log_verbosity; }; @@ -1215,6 +1261,12 @@ struct t_router_opts { float astar_fac; float astar_offset; float router_profiler_astar_fac; + bool enable_parallel_connection_router; + float post_target_prune_fac; + float post_target_prune_offset; + int multi_queue_num_threads; + int multi_queue_num_queues; + bool multi_queue_direct_draining; float max_criticality; float criticality_exp; float init_wirelength_abort_threshold; @@ -1279,14 +1331,17 @@ struct t_analysis_opts { bool gen_post_synthesis_netlist; bool gen_post_implementation_merged_netlist; + bool gen_post_implementation_sdc; e_post_synth_netlist_unconn_handling post_synth_netlist_unconn_input_handling; e_post_synth_netlist_unconn_handling post_synth_netlist_unconn_output_handling; + bool post_synth_netlist_module_parameters; int timing_report_npaths; e_timing_report_detail timing_report_detail; bool timing_report_skew; std::string echo_dot_timing_graph_node; std::string write_timing_summary; + bool generate_net_timing_report; e_timing_update_type timing_update_type; bool skip_sync_clustering_and_routing_results = false; @@ -1379,9 +1434,9 @@ struct t_det_routing_arch { std::string read_rr_edge_override_filename; }; -constexpr bool is_pin(e_rr_type type) { return (type == IPIN || type == OPIN); } -constexpr bool is_chan(e_rr_type type) { return (type == CHANX || type == CHANY); } -constexpr bool is_src_sink(e_rr_type type) { return (type == SOURCE || type == SINK); } +constexpr bool is_pin(e_rr_type type) { return (type == e_rr_type::IPIN || type == e_rr_type::OPIN); } +constexpr bool is_chan(e_rr_type type) { return (type == e_rr_type::CHANX || type == e_rr_type::CHANY); } +constexpr bool is_src_sink(e_rr_type type) { return (type == e_rr_type::SOURCE || type == e_rr_type::SINK); } /** * @brief Extra information about each rr_node needed only during routing @@ -1520,8 +1575,6 @@ struct t_server_opts { struct t_vpr_setup { bool TimingEnabled; ///>> t_clb_opins_used; //[0..num_blocks-1][0..class-1][0..used_pins-1] typedef std::vector> t_arch_switch_fanin; - -struct pair_hash { - std::size_t operator()(const std::pair& p) const noexcept { - return std::hash()(p.first) ^ (std::hash()(p.second) << 1); - } -}; - -#endif diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 5dc0c09523e..0f3ec5902fe 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -623,7 +623,7 @@ int get_track_num(int inode, const vtr::OffsetMatrix& chanx_track, const vt /* Returns the track number of this routing resource node. */ int i, j; - t_rr_type rr_type; + e_rr_type rr_type; auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; RRNodeId rr_node = RRNodeId(inode); @@ -638,10 +638,10 @@ int get_track_num(int inode, const vtr::OffsetMatrix& chanx_track, const vt j = rr_graph.node_ylow(rr_node); /* length channel segments. */ switch (rr_type) { - case CHANX: + case e_rr_type::CHANX: return (chanx_track[i][j]); - case CHANY: + case e_rr_type::CHANY: return (chany_track[i][j]); default: diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 2981dd308aa..82e0fa134ca 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -351,13 +351,13 @@ void draw_congestion(ezgl::renderer* g) { color.alpha = transparency_factor; switch (rr_graph.node_type(inode)) { - case CHANX: //fallthrough - case CHANY: + case e_rr_type::CHANX: //fallthrough + case e_rr_type::CHANY: draw_rr_chan(inode, color, g); break; - case IPIN: //fallthrough - case OPIN: + case e_rr_type::IPIN: //fallthrough + case e_rr_type::OPIN: draw_rr_pin(inode, color, g); break; default: @@ -651,15 +651,15 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren ezgl::color color = draw_state->draw_rr_node[inode].color; switch (rr_type) { - case OPIN: { + case e_rr_type::OPIN: { draw_rr_pin(inode, color, g); break; } - case IPIN: { + case e_rr_type::IPIN: { draw_rr_pin(inode, color, g); if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); - if (rr_graph.node_type(prev_node) == OPIN) { + if (rr_graph.node_type(prev_node) == e_rr_type::OPIN) { draw_pin_to_pin(prev_node, inode, g); } else { draw_pin_to_chan_edge(inode, prev_node, g); @@ -667,7 +667,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren } break; } - case CHANX: { + case e_rr_type::CHANX: { if (draw_state->draw_route_type == GLOBAL) chanx_track[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)]++; @@ -675,15 +675,15 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); switch (prev_type) { - case CHANX: { + case e_rr_type::CHANX: { draw_chanx_to_chanx_edge(prev_node, inode, switch_type, g); break; } - case CHANY: { + case e_rr_type::CHANY: { draw_chanx_to_chany_edge(inode, prev_node, FROM_Y_TO_X, switch_type, g); break; } - case OPIN: { + case e_rr_type::OPIN: { draw_pin_to_chan_edge(prev_node, inode, g); break; } @@ -697,7 +697,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren break; } - case CHANY: { + case e_rr_type::CHANY: { if (draw_state->draw_route_type == GLOBAL) chany_track[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)]++; @@ -706,17 +706,17 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren if (edge_visibility.visible) { g->set_color(color, edge_visibility.alpha); switch (prev_type) { - case CHANX: { + case e_rr_type::CHANX: { draw_chanx_to_chany_edge(prev_node, inode, FROM_X_TO_Y, switch_type, g); break; } - case CHANY: { + case e_rr_type::CHANY: { draw_chany_to_chany_edge(RRNodeId(prev_node), RRNodeId(inode), switch_type, g); break; } - case OPIN: { + case e_rr_type::OPIN: { draw_pin_to_chan_edge(prev_node, inode, g); break; @@ -839,11 +839,11 @@ void draw_routing_util(ezgl::renderer* g) { t_draw_coords* draw_coords = get_draw_coords_vars(); auto& device_ctx = g_vpr_ctx.device(); - auto chanx_usage = calculate_routing_usage(CHANX, draw_state->is_flat, false); - auto chany_usage = calculate_routing_usage(CHANY, draw_state->is_flat, false); + auto chanx_usage = calculate_routing_usage(e_rr_type::CHANX, draw_state->is_flat, false); + auto chany_usage = calculate_routing_usage(e_rr_type::CHANY, draw_state->is_flat, false); - auto chanx_avail = calculate_routing_avail(CHANX); - auto chany_avail = calculate_routing_avail(CHANY); + auto chanx_avail = calculate_routing_avail(e_rr_type::CHANX); + auto chany_avail = calculate_routing_avail(e_rr_type::CHANY); float min_util = 0.; float max_util = -std::numeric_limits::infinity(); diff --git a/vpr/src/draw/draw_rr.cpp b/vpr/src/draw/draw_rr.cpp index a47c76d3032..d9c6c71c5f3 100644 --- a/vpr/src/draw/draw_rr.cpp +++ b/vpr/src/draw/draw_rr.cpp @@ -62,20 +62,20 @@ void draw_rr(ezgl::renderer* g) { if (!draw_state->draw_rr_node[inode].node_highlighted) { /* If not highlighted node, assign color based on type. */ switch (rr_graph.node_type(inode)) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR; break; - case OPIN: + case e_rr_type::OPIN: draw_state->draw_rr_node[inode].color = ezgl::PINK; break; - case IPIN: + case e_rr_type::IPIN: draw_state->draw_rr_node[inode].color = blk_LIGHTSKYBLUE; break; - case SOURCE: + case e_rr_type::SOURCE: draw_state->draw_rr_node[inode].color = ezgl::PLUM; break; - case SINK: + case e_rr_type::SINK: draw_state->draw_rr_node[inode].color = ezgl::DARK_SLATE_BLUE; break; default: @@ -90,30 +90,30 @@ void draw_rr(ezgl::renderer* g) { /* Now call drawing routines to draw the node. */ switch (rr_graph.node_type(inode)) { - case SINK: + case e_rr_type::SINK: draw_rr_src_sink(inode, draw_state->draw_rr_node[inode].color, g); break; - case SOURCE: + case e_rr_type::SOURCE: draw_rr_edges(inode, g); draw_rr_src_sink(inode, draw_state->draw_rr_node[inode].color, g); break; - case CHANX: + case e_rr_type::CHANX: draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case CHANY: + case e_rr_type::CHANY: draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case IPIN: + case e_rr_type::IPIN: draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; - case OPIN: + case e_rr_type::OPIN: draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); draw_rr_edges(inode, g); break; @@ -133,9 +133,9 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { int transparency_factor = get_rr_node_transparency(inode); - t_rr_type type = rr_graph.node_type(inode); + e_rr_type type = rr_graph.node_type(inode); - VTR_ASSERT(type == CHANX || type == CHANY); + VTR_ASSERT(type == e_rr_type::CHANX || type == e_rr_type::CHANY); ezgl::rectangle bound_box = draw_get_rr_chan_bbox(inode); Direction dir = rr_graph.node_direction(inode); @@ -163,7 +163,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { e_side mux_dir = TOP; int coord_min = -1; int coord_max = -1; - if (type == CHANX) { + if (type == e_rr_type::CHANX) { coord_min = rr_graph.node_xlow(inode); coord_max = rr_graph.node_xhigh(inode); if (dir == Direction::INC) { @@ -172,7 +172,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { mux_dir = LEFT; } } else { - VTR_ASSERT(type == CHANY); + VTR_ASSERT(type == e_rr_type::CHANY); coord_min = rr_graph.node_ylow(inode); coord_max = rr_graph.node_yhigh(inode); if (dir == Direction::INC) { @@ -201,7 +201,7 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g) { ezgl::point2d arrow_loc_min(0, 0); ezgl::point2d arrow_loc_max(0, 0); - if (type == CHANX) { + if (type == e_rr_type::CHANX) { float sb_xmin = draw_coords->tile_x[k]; arrow_loc_min = {sb_xmin + arrow_offset, start.y}; @@ -281,14 +281,14 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { int transparency_factor = get_rr_node_transparency(rr_node); - t_rr_type from_type, to_type; + e_rr_type from_type, to_type; short switch_type; from_type = rr_graph.node_type(rr_node); if ((draw_state->draw_rr_toggle == DRAW_NODES_RR) - || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == OPIN || from_type == SOURCE || from_type == IPIN)) - || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == SOURCE || from_type == IPIN))) { + || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == e_rr_type::OPIN || from_type == e_rr_type::SOURCE || from_type == e_rr_type::IPIN)) + || (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == e_rr_type::SOURCE || from_type == e_rr_type::IPIN))) { return; /* Nothing to draw. */ } @@ -301,10 +301,10 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { continue; // skip drawing if edge is not valid to draw switch (from_type) { - case OPIN: + case e_rr_type::OPIN: switch (to_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { // If OPIN was clicked on, set color to fan-out ezgl::color color = draw_state->draw_rr_node[to_node].color; @@ -318,7 +318,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } draw_pin_to_chan_edge(inode, to_node, g); break; - case IPIN: + case e_rr_type::IPIN: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -338,9 +338,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } break; - case CHANX: /* from_type */ + case e_rr_type::CHANX: /* from_type */ switch (to_type) { - case IPIN: + case e_rr_type::IPIN: if (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR) { break; } @@ -365,7 +365,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { draw_pin_to_chan_edge(to_node, inode, g); break; - case CHANX: + case e_rr_type::CHANX: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -383,7 +383,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { switch_type, g); break; - case CHANY: + case e_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -408,9 +408,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { } break; - case CHANY: /* from_type */ + case e_rr_type::CHANY: /* from_type */ switch (to_type) { - case IPIN: + case e_rr_type::IPIN: if (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR) { break; } @@ -435,7 +435,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { draw_pin_to_chan_edge(to_node, inode, g); break; - case CHANX: + case e_rr_type::CHANX: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -453,7 +453,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { FROM_Y_TO_X, switch_type, g); break; - case CHANY: + case e_rr_type::CHANY: if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) { ezgl::color color = draw_state->draw_rr_node[to_node].color; g->set_color(color, transparency_factor); @@ -478,9 +478,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { break; } break; - case IPIN: // from_type + case e_rr_type::IPIN: // from_type switch (to_type) { - case SINK: + case e_rr_type::SINK: g->set_color(ezgl::DARK_SLATE_BLUE, transparency_factor); draw_pin_to_sink(inode, to_node, g); break; @@ -492,9 +492,9 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) { break; } break; - case SOURCE: // from_type + case e_rr_type::SOURCE: // from_type switch (to_type) { - case OPIN: + case e_rr_type::OPIN: g->set_color(ezgl::PLUM, transparency_factor); draw_source_to_pin(inode, to_node, g); break; @@ -686,8 +686,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { continue; /* Don't check RR nodes on currently invisible layers*/ } switch (rr_graph.node_type(inode)) { - case IPIN: - case OPIN: { + case e_rr_type::IPIN: + case e_rr_type::OPIN: { int i = rr_graph.node_xlow(inode); int j = rr_graph.node_ylow(inode); t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({i, j, layer_num}); @@ -709,8 +709,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { } break; } - case SOURCE: - case SINK: { + case e_rr_type::SOURCE: + case e_rr_type::SINK: { float xcen, ycen; draw_get_rr_src_sink_coords(rr_graph.rr_nodes()[size_t(inode)], &xcen, &ycen); @@ -721,8 +721,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { } break; } - case CHANX: - case CHANY: { + case e_rr_type::CHANX: + case e_rr_type::CHANY: { bound_box = draw_get_rr_chan_bbox(inode); // Check if we clicked on this wire, with 30% @@ -815,22 +815,22 @@ void draw_rr_costs(ezgl::renderer* g, const vtr::vector& rr_cos color.alpha = transparency_factor; switch (rr_graph.node_type(inode)) { - case CHANX: //fallthrough - case CHANY: + case e_rr_type::CHANX: //fallthrough + case e_rr_type::CHANY: draw_rr_chan(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case IPIN: //fallthrough + case e_rr_type::IPIN: //fallthrough draw_rr_pin(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case OPIN: + case e_rr_type::OPIN: draw_rr_pin(inode, color, g); if (with_edges) draw_rr_edges(inode, g); break; - case SOURCE: - case SINK: + case e_rr_type::SOURCE: + case e_rr_type::SINK: color.alpha *= 0.8; draw_rr_src_sink(inode, color, g); if (with_edges) draw_rr_edges(inode, g); diff --git a/vpr/src/draw/draw_rr_edges.cpp b/vpr/src/draw/draw_rr_edges.cpp index 793487d04ab..2aff5c3d35c 100644 --- a/vpr/src/draw/draw_rr_edges.cpp +++ b/vpr/src/draw/draw_rr_edges.cpp @@ -281,10 +281,10 @@ void draw_chanx_to_chany_edge(RRNodeId chanx_node, RRNodeId chany_node, enum e_e void draw_pin_to_pin(RRNodeId opin_node, RRNodeId ipin_node, ezgl::renderer* g) { /* This routine draws an edge from the opin rr node to the ipin rr node */ - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - VTR_ASSERT(rr_graph.node_type(opin_node) == OPIN); - VTR_ASSERT(rr_graph.node_type(ipin_node) == IPIN); + VTR_ASSERT(rr_graph.node_type(opin_node) == e_rr_type::OPIN); + VTR_ASSERT(rr_graph.node_type(ipin_node) == e_rr_type::IPIN); /* FIXME: May use a smarter strategy * Currently, we use the last side found for both OPIN and IPIN @@ -434,18 +434,18 @@ void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer * Any rr_node of a grid should have at least 1 side!!! */ e_side pin_side = NUM_2D_SIDES; - const t_rr_type channel_type = rr_graph.node_type(chan_node); + const e_rr_type channel_type = rr_graph.node_type(chan_node); if (1 == pin_candidate_sides.size()) { pin_side = pin_candidate_sides[0]; } else { VTR_ASSERT(1 < pin_candidate_sides.size()); - if (CHANX == channel_type && rr_graph.node_ylow(pin_node) <= rr_graph.node_ylow(chan_node)) { + if (e_rr_type::CHANX == channel_type && rr_graph.node_ylow(pin_node) <= rr_graph.node_ylow(chan_node)) { pin_side = TOP; - } else if (CHANX == channel_type && rr_graph.node_ylow(pin_node) - 1 >= rr_graph.node_ylow(chan_node)) { + } else if (e_rr_type::CHANX == channel_type && rr_graph.node_ylow(pin_node) - 1 >= rr_graph.node_ylow(chan_node)) { pin_side = BOTTOM; - } else if (CHANY == channel_type && rr_graph.node_xlow(pin_node) <= rr_graph.node_xlow(chan_node)) { + } else if (e_rr_type::CHANY == channel_type && rr_graph.node_xlow(pin_node) <= rr_graph.node_xlow(chan_node)) { pin_side = RIGHT; - } else if (CHANY == channel_type && rr_graph.node_xlow(pin_node) - 1 >= rr_graph.node_xlow(chan_node)) { + } else if (e_rr_type::CHANY == channel_type && rr_graph.node_xlow(pin_node) - 1 >= rr_graph.node_xlow(chan_node)) { pin_side = LEFT; } /* The inferred side must be in the list of sides of the pin rr_node!!! */ @@ -494,7 +494,7 @@ void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer float x2 = 0, y2 = 0; const Direction chan_rr_direction = rr_graph.node_direction(chan_node); switch (channel_type) { - case CHANX: { + case e_rr_type::CHANX: { y1 += draw_pin_offset; y2 = chan_bbox.bottom(); x2 = x1; @@ -507,7 +507,7 @@ void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer } break; } - case CHANY: { + case e_rr_type::CHANY: { x1 += draw_pin_offset; x2 = chan_bbox.left(); y2 = y1; diff --git a/vpr/src/draw/draw_searchbar.cpp b/vpr/src/draw/draw_searchbar.cpp index 270435fe04f..28f174a50dd 100644 --- a/vpr/src/draw/draw_searchbar.cpp +++ b/vpr/src/draw/draw_searchbar.cpp @@ -38,7 +38,7 @@ ezgl::rectangle draw_get_rr_chan_bbox(RRNodeId inode) { const auto& rr_graph = device_ctx.rr_graph; switch (rr_graph.node_type(inode)) { - case CHANX: + case e_rr_type::CHANX: left = draw_coords->tile_x[rr_graph.node_xlow(inode)]; right = draw_coords->tile_x[rr_graph.node_xhigh(inode)] + draw_coords->get_tile_width(); @@ -49,7 +49,7 @@ ezgl::rectangle draw_get_rr_chan_bbox(RRNodeId inode) { + draw_coords->get_tile_width() + (1. + rr_graph.node_track_num(inode)); break; - case CHANY: + case e_rr_type::CHANY: left = draw_coords->tile_x[rr_graph.node_xlow(inode)] + draw_coords->get_tile_width() + (1. + rr_graph.node_track_num(inode)); diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index 375eee6f151..48993eaf8a7 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -202,8 +202,8 @@ static int draw_internal_find_max_lvl(const t_pb_type& pb_type) { t_mode mode; int max_levels = 0; - /* If no modes, we have reached the end of pb_graph */ - if (pb_type.num_modes == 0) + /* If pb_type is a primitive, we have reached the end of pb_graph */ + if (pb_type.is_primitive()) return (pb_type.depth); for (i = 0; i < pb_type.num_modes; ++i) { @@ -221,30 +221,25 @@ static int draw_internal_find_max_lvl(const t_pb_type& pb_type) { * calls helper function to compute bounding box values. */ static void draw_internal_load_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, float parent_width, float parent_height) { - int i, j, k; - t_pb_type* pb_type; - int num_modes, num_children, num_pb; - t_mode mode; float blk_width = 0.; float blk_height = 0.; - /* Get information about the pb_type */ - pb_type = pb_graph_node->pb_type; - num_modes = pb_type->num_modes; - - /* If no modes, we have reached the end of pb_graph */ - if (num_modes == 0) + t_pb_type* pb_type = pb_graph_node->pb_type; + int num_modes = pb_type->num_modes; + /* If pb_type is primitive, we have reached the end of pb_graph */ + if (pb_type->is_primitive()) { return; + } - for (i = 0; i < num_modes; ++i) { - mode = pb_type->modes[i]; - num_children = mode.num_pb_type_children; + for (int i = 0; i < num_modes; ++i) { + t_mode mode = pb_type->modes[i]; + int num_children = mode.num_pb_type_children; - for (j = 0; j < num_children; ++j) { + for (int j = 0; j < num_children; ++j) { /* Find the number of instances for each child pb_type. */ - num_pb = mode.pb_type_children[j].num_pb; + int num_pb = mode.pb_type_children[j].num_pb; - for (k = 0; k < num_pb; ++k) { + for (int k = 0; k < num_pb; ++k) { /* Compute bound box for block. Don't call if pb_type is root-level pb. */ draw_internal_calc_coords(type_descrip_index, &pb_graph_node->child_pb_graph_nodes[i][j][k], @@ -626,6 +621,7 @@ void draw_logical_connections(ezgl::renderer* g) { */ void find_pin_index_at_model_scope(const AtomPinId pin_id, const AtomBlockId blk_id, int* pin_index, int* total_pins) { auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; AtomPortId port_id = atom_ctx.netlist().pin_port(pin_id); const t_model_ports* model_port = atom_ctx.netlist().port_model(port_id); @@ -634,8 +630,8 @@ void find_pin_index_at_model_scope(const AtomPinId pin_id, const AtomBlockId blk // Note that we do this on the model since the atom netlist doesn't include unused ports int pin_cnt = 0; *pin_index = -1; //initialize - const t_model* model = atom_ctx.netlist().block_model(blk_id); - for (const t_model_ports* port : {model->inputs, model->outputs}) { + const t_model& model = models.get_model(atom_ctx.netlist().block_model(blk_id)); + for (const t_model_ports* port : {model.inputs, model.outputs}) { while (port) { if (port == model_port) { //This is the port the pin is associated with, record it's index @@ -720,7 +716,7 @@ t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const // and if pb is dud if (pb_type->depth + 1 > max_depth || pb->child_pbs == nullptr - || pb_type->num_modes == 0) { + || pb_type->is_primitive()) { return nullptr; } diff --git a/vpr/src/draw/search_bar.cpp b/vpr/src/draw/search_bar.cpp index 9a93be2274d..46261da44d5 100644 --- a/vpr/src/draw/search_bar.cpp +++ b/vpr/src/draw/search_bar.cpp @@ -231,8 +231,8 @@ void auto_zoom_rr_node(RRNodeId rr_node_id) { // find the location of the node switch (rr_graph.node_type(rr_node_id)) { - case IPIN: - case OPIN: { + case e_rr_type::IPIN: + case e_rr_type::OPIN: { t_physical_tile_loc tile_loc = { rr_graph.node_xlow(rr_node_id), rr_graph.node_ylow(rr_node_id), @@ -253,8 +253,8 @@ void auto_zoom_rr_node(RRNodeId rr_node_id) { } break; } - case CHANX: - case CHANY: { + case e_rr_type::CHANX: + case e_rr_type::CHANY: { rr_node = draw_get_rr_chan_bbox(rr_node_id); break; } diff --git a/vpr/src/pack/appack_context.h b/vpr/src/pack/appack_context.h index 0461f26b320..4235fb1fd95 100644 --- a/vpr/src/pack/appack_context.h +++ b/vpr/src/pack/appack_context.h @@ -8,12 +8,12 @@ #pragma once -#include -#include +#include "appack_max_dist_th_manager.h" #include "device_grid.h" #include "flat_placement_types.h" #include "physical_types.h" #include "vpr_context.h" +#include "vpr_types.h" #include "vpr_utils.h" /** @@ -25,29 +25,10 @@ */ struct t_appack_options { // Constructor for the appack options. - t_appack_options(const FlatPlacementInfo& flat_placement_info, - const DeviceGrid& device_grid) { + t_appack_options(const FlatPlacementInfo& flat_placement_info) { // If the flat placement info is valid, we want to use APPack. // TODO: Should probably check that all the information is valid here. use_appack = flat_placement_info.valid; - - // Set the max candidate distance as being some fraction of the longest - // distance on the device (from the bottom corner to the top corner). - // We also use an offset for the minimum this distance can be to prevent - // small devices from finding candidates. - float max_candidate_distance_scale = 0.1f; - float max_candidate_distance_offset = 15.0f; - // Longest L1 distance on the device. - float longest_distance = device_grid.width() + device_grid.height(); - max_candidate_distance = std::max(max_candidate_distance_scale * longest_distance, - max_candidate_distance_offset); - - // Infer the logical block type in the architecture. This will be used - // for the max candidate distance optimization to use a more aggressive - // distance. - t_logical_block_type_ptr logic_block_type = infer_logic_block_type(device_grid); - if (logic_block_type != nullptr) - logic_block_type_index = logic_block_type->index; } // Whether to use APPack or not. @@ -88,22 +69,6 @@ struct t_appack_options { // Squared scaling factor for the quadratic decay term. static constexpr float quad_fac_sqr = (1.0f - attenuation_th) / (dist_th * dist_th); - // =========== Candidate selection distance ============================ // - // When selecting candidates, what distance from the cluster will we - // consider? Any candidate beyond this distance will not be proposed. - // This is set in the constructor. - // TODO: It may be a good idea to have max different distances for different - // types of molecules / clusters. For example, CLBs vs DSPs - float max_candidate_distance = std::numeric_limits::max(); - - // A scaling applied to the max candidate distance of all clusters that are - // not logic blocks. - static constexpr float max_candidate_distance_non_lb_scale = 3.5f; - - // TODO: This should be an option similar to the target pin utilization - // so we can specify the max distance per block type! - int logic_block_type_index = -1; - // =========== Unrelated clustering ==================================== // // After searching for candidates by connectivity and timing, the user may // turn on unrelated clustering, which will allow molecules which are @@ -144,9 +109,21 @@ struct APPackContext : public Context { /** * @brief Constructor for the APPack context. */ - APPackContext(const FlatPlacementInfo& fplace_info, const DeviceGrid& device_grid) - : appack_options(fplace_info, device_grid) - , flat_placement_info(fplace_info) {} + APPackContext(const FlatPlacementInfo& fplace_info, + const t_ap_opts& ap_opts, + const std::vector logical_block_types, + const DeviceGrid& device_grid) + : appack_options(fplace_info) + , flat_placement_info(fplace_info) { + + // If the flat placement info has been provided, calculate max distance + // thresholds for all logical block types. + if (fplace_info.valid) { + max_distance_threshold_manager.init(ap_opts.appack_max_dist_th, + logical_block_types, + device_grid); + } + } /** * @brief Options used to configure APPack. @@ -157,4 +134,8 @@ struct APPackContext : public Context { * @brief The flat placement information passed into APPack. */ const FlatPlacementInfo& flat_placement_info; + + // When selecting candidates, what distance from the cluster will we + // consider? Any candidate beyond this distance will not be proposed. + APPackMaxDistThManager max_distance_threshold_manager; }; diff --git a/vpr/src/pack/appack_max_dist_th_manager.cpp b/vpr/src/pack/appack_max_dist_th_manager.cpp new file mode 100644 index 00000000000..c5c9b685b73 --- /dev/null +++ b/vpr/src/pack/appack_max_dist_th_manager.cpp @@ -0,0 +1,271 @@ +/** + * @file + * @author Alex Singer + * @date May 2025 + * @breif Definition of the max distance threshold manager class. + */ + +#include "appack_max_dist_th_manager.h" +#include +#include +#include +#include +#include "device_grid.h" +#include "physical_types.h" +#include "physical_types_util.h" +#include "vpr_error.h" +#include "vpr_utils.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +/** + * @brief Helper method to convert a string into a float with error checking. + */ +static float str_to_float_or_error(const std::string& str); + +/** + * @brief Helper method to parse one term of the user-provided max distance + * threshold string. + * + * This method decomposes the user string of the form ":," + * into its three components. + */ +static std::tuple parse_max_dist_th(const std::string& max_dist_th); + +/** + * @brief Recursive helper method to deduce if the given pb_type is or contains + * pb_types which are of the memory class. + * + * TODO: This should be a graph traversal instead of a recursive function. + */ +static bool has_memory_pbs(const t_pb_type* pb_type); + +void APPackMaxDistThManager::init(const std::vector& max_dist_ths, + const std::vector& logical_block_types, + const DeviceGrid& device_grid) { + // Automatically set the max distance thresholds. + auto_set_max_distance_thresholds(logical_block_types, device_grid); + + // If the max distance threshold strings have been set (they are not set to + // auto), set the max distance thresholds based on the user-provided strings. + VTR_ASSERT(!max_dist_ths.empty()); + if (max_dist_ths.size() != 1 || max_dist_ths[0] != "auto") { + set_max_distance_thresholds_from_strings(max_dist_ths, logical_block_types, device_grid); + } + + // Set the initilized flag to true. + is_initialized_ = true; + + // Log the max distance thresholds for each logical block type. This is + // similar to how the input and output pin utilizations are printed. + VTR_LOG("APPack is using max distance thresholds: "); + for (const t_logical_block_type& lb_ty : logical_block_types) { + if (lb_ty.is_empty()) + continue; + VTR_LOG("%s:%g ", + lb_ty.name.c_str(), + get_max_dist_threshold(lb_ty)); + } + VTR_LOG("\n"); +} + +void APPackMaxDistThManager::auto_set_max_distance_thresholds(const std::vector& logical_block_types, + const DeviceGrid& device_grid) { + // Compute the max device distance based on the width and height of the + // device. This is the L1 (manhattan) distance. + float max_device_distance = device_grid.width() + device_grid.height(); + + // Compute the max distance thresholds of the different logical block types. + float default_max_distance_th = std::max(default_max_dist_th_scale_ * max_device_distance, + default_max_dist_th_offset_); + float logic_block_max_distance_th = std::max(logic_block_max_dist_th_scale_ * max_device_distance, + logic_block_max_dist_th_offset_); + float memory_max_distance_th = std::max(memory_max_dist_th_scale_ * max_device_distance, + memory_max_dist_th_offset_); + float io_block_max_distance_th = std::max(io_max_dist_th_scale_ * max_device_distance, + io_max_dist_th_offset_); + + // Set all logical block types to have the default max distance threshold. + logical_block_dist_thresholds_.resize(logical_block_types.size(), default_max_distance_th); + + // Find which (if any) of the logical block types most looks like a CLB block. + t_logical_block_type_ptr logic_block_type = infer_logic_block_type(device_grid); + + // Go through each of the logical block types. + for (const t_logical_block_type& lb_ty : logical_block_types) { + // Skip the empty logical block type. This should not have any blocks. + if (lb_ty.is_empty()) + continue; + + // Find which type(s) this logical block type looks like. + bool has_memory = has_memory_pbs(lb_ty.pb_type); + bool is_logic_block_type = (lb_ty.index == logic_block_type->index); + bool is_io_block = pick_physical_type(&lb_ty)->is_io(); + + // Update the max distance threshold based on the type. If the logical + // block type looks like many block types at the same time (for example + // a CLB which has memory slices within it), then take the average + // of the max distance thresholds of those types. + float max_distance_th_sum = 0.0f; + unsigned block_category_count = 0; + if (is_logic_block_type) { + max_distance_th_sum += logic_block_max_distance_th; + block_category_count++; + } + if (has_memory) { + max_distance_th_sum += memory_max_distance_th; + block_category_count++; + } + if (is_io_block) { + max_distance_th_sum += io_block_max_distance_th; + block_category_count++; + } + if (block_category_count > 0) { + logical_block_dist_thresholds_[lb_ty.index] = max_distance_th_sum / static_cast(block_category_count); + } + } +} + +static bool has_memory_pbs(const t_pb_type* pb_type) { + if (pb_type == nullptr) + return false; + + // Check if this pb_type is a memory class. If so return true. This acts as + // a base case for the recursion. + if (pb_type->class_type == e_pb_type_class::MEMORY_CLASS) + return true; + + // Go through all modes of this pb_type and check if any of those modes' + // children have memory pb_types, if so return true. + for (int mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { + const t_mode& mode = pb_type->modes[mode_idx]; + for (int child_idx = 0; child_idx < mode.num_pb_type_children; child_idx++) { + if (has_memory_pbs(&mode.pb_type_children[child_idx])) + return true; + } + } + + // If this pb_type is not a memory and its modes do not have memory pbs in + // them, then this pb_type is not a memory. + return false; +} + +void APPackMaxDistThManager::set_max_distance_thresholds_from_strings( + const std::vector& max_dist_ths, + const std::vector& logical_block_types, + const DeviceGrid& device_grid) { + + // Go through each of the user-provided strings. + for (const std::string& max_dist_th : max_dist_ths) { + // If any of them are the word "auto", this was a user error and should + // be flagged. + // TODO: Maybe move this and other semantic checks up to the checker of + // VPR's command line. + if (max_dist_th == "auto") { + VPR_FATAL_ERROR(VPR_ERROR_PACK, + "APPack: Cannot provide both auto and other max distance threshold strings"); + } + + // Parse the string for the regex, scale, and offset. + std::string logical_block_regex_str; + float logical_block_max_dist_th_scale; + float logical_block_max_dist_th_offset; + std::tie(logical_block_regex_str, + logical_block_max_dist_th_scale, + logical_block_max_dist_th_offset) = parse_max_dist_th(max_dist_th); + + // Setup the regex for the logical blocks the user wants to set the + // thresholds for. + std::regex logical_block_regex(logical_block_regex_str); + + // Compute the max distance threshold the user selected. + float max_device_distance = device_grid.width() + device_grid.height(); + float logical_block_max_dist_th = std::max(max_device_distance * logical_block_max_dist_th_scale, + logical_block_max_dist_th_offset); + + // Search through all logical blocks and set the thresholds of any matches + // to the threshold the user selected. + bool found_match = false; + for (const t_logical_block_type& lb_ty : logical_block_types) { + bool is_match = std::regex_match(lb_ty.name, logical_block_regex); + if (!is_match) + continue; + + logical_block_dist_thresholds_[lb_ty.index] = logical_block_max_dist_th; + found_match = true; + } + // If no match is found, send a warning to the user. + if (!found_match) { + VTR_LOG_WARN("Unable to find logical block type for max distance threshold regex string: %s\n", + logical_block_regex_str.c_str()); + } + } +} + +static std::tuple parse_max_dist_th(const std::string& max_dist_th) { + // Verify the format of the string. It must have one and only one colon. + unsigned colon_count = 0; + for (char c : max_dist_th) { + if (c == ':') + colon_count++; + } + if (colon_count != 1) { + VTR_LOG_ERROR("Invalid max distance threshold string: %s\n", + max_dist_th.c_str()); + VPR_FATAL_ERROR(VPR_ERROR_PACK, + "Error when parsing APPack max distance threshold string"); + } + + // Split the string along the colon. + auto del_pos = max_dist_th.find(':'); + std::string logical_block_regex_str = max_dist_th.substr(0, del_pos); + std::string lb_max_dist_th_str = max_dist_th.substr(del_pos + 1, std::string::npos); + + // Split along the comma for the scale/offset. + // Verify that the comma only appears once in the scale/offset string. + unsigned comma_count = 0; + for (char c : lb_max_dist_th_str) { + if (c == ',') + comma_count++; + } + if (comma_count != 1) { + VTR_LOG_ERROR("Invalid max distance threshold string: %s\n", + max_dist_th.c_str()); + VPR_FATAL_ERROR(VPR_ERROR_PACK, + "Error when parsing APPack max distance threshold string"); + } + + // Split the string along the comma. + auto comma_pos = lb_max_dist_th_str.find(','); + std::string lb_max_dist_th_scale_str = lb_max_dist_th_str.substr(0, comma_pos); + std::string lb_max_dist_th_offset_str = lb_max_dist_th_str.substr(comma_pos + 1, std::string::npos); + + // Convert the scale and offset into floats (error checking to be safe). + float lb_max_dist_th_scale = str_to_float_or_error(lb_max_dist_th_scale_str); + float lb_max_dist_th_offset = str_to_float_or_error(lb_max_dist_th_offset_str); + + // Return the results as a tuple. + return std::make_tuple(logical_block_regex_str, lb_max_dist_th_scale, lb_max_dist_th_offset); +} + +static float str_to_float_or_error(const std::string& str) { + float val = -1; + try { + val = std::stof(str); + } catch (const std::invalid_argument& e) { + VTR_LOG_ERROR("Error while parsing max distance threshold value: %s\n" + "Failed with invalid argument: %s\n", + str.c_str(), + e.what()); + } catch (const std::out_of_range& e) { + VTR_LOG_ERROR("Error while parsing max distance threshold value: %s\n" + "Failed with out of range: %s\n", + str.c_str(), + e.what()); + } + if (val < 0.0f) { + VPR_FATAL_ERROR(VPR_ERROR_PACK, + "Error when parsing APPack max distance threshold string"); + } + return val; +} diff --git a/vpr/src/pack/appack_max_dist_th_manager.h b/vpr/src/pack/appack_max_dist_th_manager.h new file mode 100644 index 00000000000..558b224c56b --- /dev/null +++ b/vpr/src/pack/appack_max_dist_th_manager.h @@ -0,0 +1,118 @@ +/** + * @file + * @author Alex Singer + * @date May 2025 + * @brief Declaration of a class that manages the max candidate distance + * thresholding optimization used within APPack. + */ + +#pragma once + +#include +#include +#include "physical_types.h" +#include "vtr_assert.h" + +// Forward declarations. +class DeviceGrid; + +/** + * @brief Manager class which manages parsing and getting the max candidate + * distance thresholds for each of the logical block types in the + * architecture. + * + * The initializer of this class will set the max candidate distance thresholds + * based on the arguments passed by the user. + * + * Within the packer, the get_max_dist_threshold method can be used to get the + * max distance threshold for a given logical block type. + */ +class APPackMaxDistThManager { + // To compute the max distance threshold, we use two numbers to compute it: + // - Scale: This is what fraction of the device the distance should be. + // i.e. the max distance threshold will be scale * (W + H) since + // W+H is the farthes L1 distance possible on the device. + // - Offset: This is the minimum threshold it can have. This prevents small + // devices with small scales having thresholds that are too small. + // The following scales and offsets are set for interesting logical blocks + // when the "auto" selection mode is used. The following numbers were + // empirically found to work well. + + // This is the default scale and offset. Logical blocks that we do not + // recognize as being of the special categories will have this threshold. + static constexpr float default_max_dist_th_scale_ = 0.35f; + static constexpr float default_max_dist_th_offset_ = 15.0f; + + // Logic blocks (such as CLBs and LABs) tend to have more resources on the + // device, thus they have tighter thresholds. This was found to work well. + static constexpr float logic_block_max_dist_th_scale_ = 0.1f; + static constexpr float logic_block_max_dist_th_offset_ = 15.0f; + + // Memory blocks (i.e. blocks that contain pb_types of the memory class) + // seem to have very touchy packing; thus these do not have the max + // threshold to prevent them from creating too many clusters. + static constexpr float memory_max_dist_th_scale_ = 1.0f; + static constexpr float memory_max_dist_th_offset_ = 0.0f; + + // IO blocks tend to have very sparse resources and setting the offset too + // low can create too many blocks. Set this to a higher value. + static constexpr float io_max_dist_th_scale_ = 0.5f; + static constexpr float io_max_dist_th_offset_ = 15.0f; + + public: + APPackMaxDistThManager() = default; + + /** + * @brief Initializer for the manager class. The thresholds for each logical + * block type is selected here. + * + * @param should_initialize + * Whether to compute the thresholds for each logical block or not. This + * is to allow the class to be passed around without AP being enabled. + * @param max_dist_ths + * An array of strings representing the user-defined max distance + * thresholds. This is passed from the command line. + * @param logical_block_types + * An array of all logical block types in the architecture. + * @param device_grid + */ + void init(const std::vector& max_dist_ths, + const std::vector& logical_block_types, + const DeviceGrid& device_grid); + + /** + * @brief Get the max distance threshold of the given lobical block type. + */ + inline float get_max_dist_threshold(const t_logical_block_type& logical_block_ty) const { + VTR_ASSERT_SAFE_MSG(is_initialized_, + "APPackMaxDistThManager has not been initialized, cannot call this method"); + VTR_ASSERT_SAFE_MSG((size_t)logical_block_ty.index < logical_block_dist_thresholds_.size(), + "Logical block type does not have a max distance threshold"); + + return logical_block_dist_thresholds_[logical_block_ty.index]; + } + + private: + /** + * @brief Helper method that initializes the thresholds of all logical + * block types to reasonable numbers based on the characteristics + * of the logical block type. + */ + void auto_set_max_distance_thresholds(const std::vector& logical_block_types, + const DeviceGrid& device_grid); + + /** + * @brief Helper method that sets the thresholds based on the user-provided + * strings. + */ + void set_max_distance_thresholds_from_strings(const std::vector& max_dist_ths, + const std::vector& logical_block_types, + const DeviceGrid& device_grid); + + /// @brief A flag which shows if the thesholds have been computed or not. + bool is_initialized_ = false; + + /// @brief The max distance thresholds of all logical blocks in the architecture. + /// This is initialized in the constructor and accessed during packing. + std::vector logical_block_dist_thresholds_; +}; diff --git a/vpr/src/pack/atom_pb_bimap.cpp b/vpr/src/pack/atom_pb_bimap.cpp index df837cfea6b..bb9cb70946f 100644 --- a/vpr/src/pack/atom_pb_bimap.cpp +++ b/vpr/src/pack/atom_pb_bimap.cpp @@ -8,7 +8,6 @@ */ #include "atom_pb_bimap.h" -#include "atom_netlist.h" AtomPBBimap::AtomPBBimap(const vtr::bimap& atom_to_pb) { atom_to_pb_ = atom_to_pb; diff --git a/vpr/src/pack/cluster_feasibility_filter.cpp b/vpr/src/pack/cluster_feasibility_filter.cpp index dec597aa41e..86e4d13906b 100644 --- a/vpr/src/pack/cluster_feasibility_filter.cpp +++ b/vpr/src/pack/cluster_feasibility_filter.cpp @@ -28,16 +28,12 @@ */ #include +#include "physical_types.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_memory.h" -#include "read_xml_arch_file.h" -#include "vpr_types.h" -#include "globals.h" #include "hash.h" #include "cluster_feasibility_filter.h" -#include "vpr_utils.h" /* header functions that identify pin classes */ static void alloc_pin_classes_in_pb_graph_node(t_pb_graph_node* pb_graph_node); diff --git a/vpr/src/pack/cluster_feasibility_filter.h b/vpr/src/pack/cluster_feasibility_filter.h index b6c9cebffd5..e56f3a67a90 100644 --- a/vpr/src/pack/cluster_feasibility_filter.h +++ b/vpr/src/pack/cluster_feasibility_filter.h @@ -21,7 +21,8 @@ #ifndef CLUSTER_FEASIBILITY_CHECK_H #define CLUSTER_FEASIBILITY_CHECK_H -#include "arch_types.h" + +class t_pb_graph_node; void load_pin_classes_in_pb_graph_head(t_pb_graph_node* pb_graph_node); diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index 282b0fe8d1c..7256a2c84f7 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -65,7 +65,7 @@ static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set& const AtomContext& atom_ctx = g_vpr_ctx.atom(); const t_pb_type* pb_type = pb->pb_graph_node->pb_type; - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* primitive */ AtomBlockId blk_id = atom_pb_lookup.pb_atom(pb); if (blk_id) { @@ -323,6 +323,7 @@ static enum e_block_pack_status check_chain_root_placement_feasibility(const t_p */ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_type, const AtomBlockId sibling_blk_id) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; VTR_ASSERT(cur_pb_type->class_type == MEMORY_CLASS); @@ -343,8 +344,8 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ //Since the atom netlist stores only in-use ports, we iterate over the model to ensure //all ports are compared - const t_model* model = cur_pb_type->model; - for (t_model_ports* port : {model->inputs, model->outputs}) { + const t_model& model = models.get_model(cur_pb_type->model_id); + for (t_model_ports* port : {model.inputs, model.outputs}) { for (; port; port = port->next) { if (data_ports.count(port)) { //Don't check data ports @@ -395,7 +396,7 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb, const AtomPBBimap& atom_to_pb) { const t_pb_type* cur_pb_type = cur_pb->pb_graph_node->pb_type; - VTR_ASSERT(cur_pb_type->num_modes == 0); /* primitive */ + VTR_ASSERT(cur_pb_type->is_primitive()); /* primitive */ AtomBlockId cur_pb_blk_id = atom_to_pb.pb_atom(cur_pb); if (cur_pb_blk_id && cur_pb_blk_id != blk_id) { @@ -441,6 +442,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, const vtr::vector_map& clustering_chain_info, AtomPBBimap& atom_to_pb) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; VTR_ASSERT_SAFE(cb != nullptr); e_block_pack_status block_pack_status = e_block_pack_status::BLK_PASSED; @@ -509,9 +511,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, return e_block_pack_status::BLK_FAILED_FEASIBLE; } - bool is_primitive = (pb_type->num_modes == 0); - - if (is_primitive) { + if (pb_type->is_primitive()) { VTR_ASSERT(!atom_to_pb.pb_atom(pb) && atom_to_pb.atom_pb(blk_id) == nullptr && atom_cluster[blk_id] == LegalizationClusterId::INVALID()); @@ -553,7 +553,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, VTR_LOGV(verbosity > 4 && block_pack_status == e_block_pack_status::BLK_PASSED, "\t\t\tPlaced atom '%s' (%s) at %s\n", atom_ctx.netlist().block_name(blk_id).c_str(), - atom_ctx.netlist().block_model(blk_id)->name, + models.model_name(atom_ctx.netlist().block_model(blk_id)).c_str(), pb->hierarchical_type_name().c_str()); } @@ -574,7 +574,7 @@ static void reset_lookahead_pins_used(t_pb* cur_pb) { return; /* No pins used, no need to continue */ } - if (pb_type->num_modes > 0 && cur_pb->name != nullptr) { + if (!pb_type->is_primitive() && cur_pb->name != nullptr) { for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { cur_pb->pb_stats->lookahead_input_pins_used[i].clear(); } @@ -819,7 +819,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, const AtomPBBimap& atom_to_pb) { // run recursively till a leaf (primitive) pb block is reached const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type; - if (pb_type->num_modes > 0 && cur_pb->name != nullptr) { + if (!pb_type->is_primitive() && cur_pb->name != nullptr) { if (cur_pb->child_pbs != nullptr) { for (int i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; i++) { if (cur_pb->child_pbs[i] != nullptr) { @@ -846,7 +846,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, static bool check_lookahead_pins_used(t_pb* cur_pb, t_ext_pin_util max_external_pin_util) { const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type; - if (pb_type->num_modes > 0 && cur_pb->name) { + if (!pb_type->is_primitive() && cur_pb->name) { for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { size_t class_size = cur_pb->pb_graph_node->input_pin_class_size[i]; @@ -1013,7 +1013,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id, static void commit_lookahead_pins_used(t_pb* cur_pb) { const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type; - if (pb_type->num_modes > 0 && cur_pb->name) { + if (!pb_type->is_primitive() && cur_pb->name) { for (int i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { VTR_ASSERT(cur_pb->pb_stats->lookahead_input_pins_used[i].size() <= (unsigned int)cur_pb->pb_graph_node->input_pin_class_size[i]); for (size_t j = 0; j < cur_pb->pb_stats->lookahead_input_pins_used[i].size(); j++) { @@ -1074,7 +1074,7 @@ static bool cleanup_pb(t_pb* pb) { t_pb_type* pb_type = pb_child->pb_graph_node->pb_type; /* Primitive, check occupancy */ - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { if (pb_child->name != nullptr) { can_free = false; } @@ -1133,6 +1133,8 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(PackMoleculeId molecule_ // constraints. const FloorplanningContext& floorplanning_ctx = g_vpr_ctx.floorplanning(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; + // Get the molecule object. const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); @@ -1140,7 +1142,7 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(PackMoleculeId molecule_ AtomBlockId root_atom = molecule.atom_block_ids[molecule.root]; VTR_LOG("\t\tTry pack molecule: '%s' (%s)", atom_ctx.netlist().block_name(root_atom).c_str(), - atom_ctx.netlist().block_model(root_atom)->name); + models.model_name(atom_ctx.netlist().block_model(root_atom)).c_str()); VTR_LOGV(molecule.pack_pattern, " molecule_type %s molecule_size %zu", molecule.pack_pattern->name, @@ -1571,8 +1573,7 @@ void ClusterLegalizer::clean_cluster(LegalizationClusterId cluster_id) { // Load the pb_route so we can free the cluster router data. // The pb_route is used when creating a netlist from the legalized clusters. std::vector* saved_lb_nets = cluster.router_data->saved_lb_nets; - t_pb_graph_node* pb_graph_node = cluster.pb->pb_graph_node; - cluster.pb->pb_route = alloc_and_load_pb_route(saved_lb_nets, pb_graph_node); + cluster.pb->pb_route = alloc_and_load_pb_route(saved_lb_nets, cluster.type, intra_lb_pb_pin_lookup_); // Free the router data. free_router_data(cluster.router_data); cluster.router_data = nullptr; @@ -1601,6 +1602,7 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, const t_pack_high_fanout_thresholds& high_fanout_thresholds, ClusterLegalizationStrategy cluster_legalization_strategy, bool enable_pin_feasibility_filter, + const LogicalModels& models, int log_verbosity) : prepacker_(prepacker) { // Verify that the inputs are valid. @@ -1621,7 +1623,7 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, // Get a reference to the rr graphs. lb_type_rr_graphs_ = lb_type_rr_graphs; // Find all NoC router atoms. - std::vector noc_atoms = find_noc_router_atoms(atom_netlist); + std::vector noc_atoms = find_noc_router_atoms(atom_netlist, models); update_noc_reachability_partitions(noc_atoms, atom_netlist, high_fanout_thresholds, @@ -1632,6 +1634,7 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, log_verbosity_ = log_verbosity; VTR_ASSERT(g_vpr_ctx.atom().lookup().atom_pb_bimap().is_empty()); atom_pb_lookup_ = AtomPBBimap(); + intra_lb_pb_pin_lookup_ = IntraLbPbPinLookup(g_vpr_ctx.device().logical_block_types); } void ClusterLegalizer::reset() { diff --git a/vpr/src/pack/cluster_legalizer.h b/vpr/src/pack/cluster_legalizer.h index 67bc00a95ec..8cdd42df298 100644 --- a/vpr/src/pack/cluster_legalizer.h +++ b/vpr/src/pack/cluster_legalizer.h @@ -23,9 +23,11 @@ #include "vtr_vector.h" #include "vtr_vector_map.h" #include "atom_pb_bimap.h" +#include "vpr_utils.h" // Forward declarations class Prepacker; +class LogicalModels; class t_intra_cluster_placement_stats; class t_pb_graph_node; struct t_lb_router_data; @@ -268,6 +270,7 @@ class ClusterLegalizer { * performed. * @param enable_pin_feasibility_filter * A flag to turn on/off the check for pin usage feasibility. + * @param models * @param log_verbosity * Controls how verbose the log messages will be within this class. */ @@ -278,6 +281,7 @@ class ClusterLegalizer { const t_pack_high_fanout_thresholds& high_fanout_thresholds, ClusterLegalizationStrategy cluster_legalization_strategy, bool enable_pin_feasibility_filter, + const LogicalModels& models, int log_verbosity); // This class allocates and deallocates memory within. This class should not @@ -524,6 +528,8 @@ class ClusterLegalizer { inline const AtomPBBimap& atom_pb_lookup() const { return atom_pb_lookup_; } inline AtomPBBimap& mutable_atom_pb_lookup() { return atom_pb_lookup_; } + inline const IntraLbPbPinLookup& intra_lb_pb_pin_lookup() const { return intra_lb_pb_pin_lookup_; } + /// @brief Destructor of the class. Frees allocated data. ~ClusterLegalizer(); @@ -595,4 +601,7 @@ class ClusterLegalizer { /// @brief A two way map between AtomBlockIds and pb types. This is a copy /// of the AtomPBBimap in the global context's AtomLookup AtomPBBimap atom_pb_lookup_; + + /// @brief A lookup table for the pin mapping of the intra-lb pb pins. + IntraLbPbPinLookup intra_lb_pb_pin_lookup_; }; diff --git a/vpr/src/pack/cluster_placement.cpp b/vpr/src/pack/cluster_placement.cpp index 297212c4ff1..fb2cb5298f5 100644 --- a/vpr/src/pack/cluster_placement.cpp +++ b/vpr/src/pack/cluster_placement.cpp @@ -21,7 +21,6 @@ #include "hash.h" #include "physical_types.h" #include "prepack.h" -#include "vpr_types.h" #include "vpr_utils.h" #include "vtr_assert.h" diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 92d4b183dc5..1f08f5d3ea1 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -24,7 +24,6 @@ #include "vpr_error.h" #include "vpr_types.h" -#include "echo_files.h" #include "physical_types.h" #include "globals.h" @@ -108,7 +107,23 @@ static bool is_route_success(t_lb_router_data* router_data); static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index); static void reset_explored_node_tb(t_lb_router_data* router_data); static void save_and_reset_lb_route(t_lb_router_data* router_data); -static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace); + +/** + * @brief Recurse through route tree trace to populate pb pin to atom net lookup array. + * + * @param pb_route Array of pb pin to atom net lookup to be populated in this routine. + * @param net_id Atom net ID of the current net. + * @param prev_pin_id ID of the previous pin in the route tree trace. + * @param trace Current trace node in the route tree. + * @param logic_block_type Logic block type of the current cluster. + * @param intra_lb_pb_pin_lookup Intra-logic block pin lookup to get t_pb_graph_pin from a pin ID. + */ +static void load_trace_to_pb_route(t_pb_routes& pb_route, + const AtomNetId net_id, + const int prev_pin_id, + const t_lb_trace* trace, + t_logical_block_type_ptr logic_block_type, + const IntraLbPbPinLookup& intra_lb_pb_pin_lookup); static std::string describe_lb_type_rr_node(int inode, const t_lb_router_data* router_data); @@ -543,15 +558,14 @@ bool try_intra_lb_route(t_lb_router_data* router_data, * Accessor Functions ******************************************************************************************/ -/* Creates an array [0..num_pb_graph_pins-1] lookup for intra-logic block routing. Given pb_graph_pin id for clb, lookup atom net that uses that pin. - * If pin is not used, stores OPEN at that pin location */ -t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_pb_graph_node* pb_graph_head) { +t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, + t_logical_block_type_ptr logic_block_type, + const IntraLbPbPinLookup& intra_lb_pb_pin_lookup) { const std::vector& lb_nets = *intra_lb_nets; - int total_pins = pb_graph_head->total_pb_pins; t_pb_routes pb_route; - for (int inet = 0; inet < (int)lb_nets.size(); inet++) { - load_trace_to_pb_route(pb_route, total_pins, lb_nets[inet].atom_net_id, OPEN, lb_nets[inet].rt_tree); + for (const auto& lb_net : lb_nets) { + load_trace_to_pb_route(pb_route, lb_net.atom_net_id, OPEN, lb_net.rt_tree, logic_block_type, intra_lb_pb_pin_lookup); } return pb_route; @@ -581,11 +595,16 @@ void free_intra_lb_nets(std::vector* intra_lb_nets) { * Internal Functions ****************************************************************************/ -/* Recurse through route tree trace to populate pb pin to atom net lookup array */ -static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace) { +static void load_trace_to_pb_route(t_pb_routes& pb_route, + const AtomNetId net_id, + const int prev_pin_id, + const t_lb_trace* trace, + t_logical_block_type_ptr logic_block_type, + const IntraLbPbPinLookup& intra_lb_pb_pin_lookup) { int ipin = trace->current_node; int driver_pb_pin_id = prev_pin_id; int cur_pin_id = OPEN; + const int total_pins = logic_block_type->pb_graph_head->total_pb_pins; if (ipin < total_pins) { /* This routing node corresponds with a pin. This node is virtual (ie. sink or source node) */ cur_pin_id = ipin; @@ -593,12 +612,14 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, pb_route.insert(std::make_pair(cur_pin_id, t_pb_route())); pb_route[cur_pin_id].atom_net_id = net_id; pb_route[cur_pin_id].driver_pb_pin_id = driver_pb_pin_id; + const t_pb_graph_pin* pb_graph_pin = intra_lb_pb_pin_lookup.pb_gpin(logic_block_type->index, cur_pin_id); + pb_route[cur_pin_id].pb_graph_pin = pb_graph_pin; } else { VTR_ASSERT(pb_route[cur_pin_id].atom_net_id == net_id); } } - for (int itrace = 0; itrace < (int)trace->next_nodes.size(); itrace++) { - load_trace_to_pb_route(pb_route, total_pins, net_id, cur_pin_id, &trace->next_nodes[itrace]); + for (const auto& nxt_trace : trace->next_nodes) { + load_trace_to_pb_route(pb_route, net_id, cur_pin_id, &nxt_trace, logic_block_type, intra_lb_pb_pin_lookup); } } diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index 0b40f84c627..40d689b514d 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -6,9 +6,13 @@ */ #ifndef CLUSTER_ROUTER_H #define CLUSTER_ROUTER_H + #include #include "atom_netlist_fwd.h" +#include "atom_pb_bimap.h" #include "pack_types.h" +#include "vpr_types.h" +#include "vpr_utils.h" /* Constructors/Destructors */ t_lb_router_data* alloc_and_load_router_data(std::vector* lb_type_graph, t_logical_block_type_ptr type); @@ -22,8 +26,19 @@ void set_reset_pb_modes(t_lb_router_data* router_data, const t_pb* pb, const boo bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_selection_status* mode_status); void reset_intra_lb_route(t_lb_router_data* router_data); -/* Accessor Functions */ -t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, t_pb_graph_node* pb_graph_head); +/** + * @brief Creates an array [0..num_pb_graph_pins-1] for intra-logic block routing lookup. + * Given a pb_graph_pin ID for a CLB, this lookup returns t_pb_route corresponding to that + * pin. + * + * @param intra_lb_nets Vector of intra-logic block nets. + * @param logic_block_type Logic block type of the current cluster. + * @param intra_lb_pb_pin_lookup Intra-logic block pin lookup to get t_pb_graph_pin from a pin ID. + * @return t_pb_routes An array [0..num_pb_graph_pins-1] for intra-logic block routing lookup. + */ +t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_nets, + t_logical_block_type_ptr logic_block_type, + const IntraLbPbPinLookup& intra_lb_pb_pin_lookup); void free_pb_route(t_pb_route* free_pb_route); #endif diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index dd307168a36..60c67f3c7d1 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -7,9 +7,11 @@ #include "cluster_legalizer.h" #include "clustered_netlist.h" #include "globals.h" +#include "logic_types.h" #include "output_clustering.h" #include "prepack.h" #include "vpr_context.h" +#include "vtr_vector.h" /*Print the contents of each cluster to an echo file*/ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legalizer) { @@ -74,7 +76,6 @@ void check_and_output_clustering(ClusterLegalizer& cluster_legalizer, } output_clustering(&cluster_legalizer, - packer_opts.global_clocks, is_clock, arch->architecture_id, packer_opts.output_file.c_str(), @@ -151,26 +152,29 @@ void rebuild_attraction_groups(AttractionInfo& attraction_groups, /*****************************************/ -std::map> identify_primitive_candidate_block_types() { - std::map> model_candidates; +vtr::vector> identify_primitive_candidate_block_types() { const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); const DeviceContext& device_ctx = g_vpr_ctx.device(); + const LogicalModels& models = device_ctx.arch->models; + size_t num_models = models.all_models().size(); + vtr::vector> model_candidates(num_models); - std::set unique_models; + std::set unique_models; // Find all logic models used in the netlist for (auto blk : atom_nlist.blocks()) { - auto model = atom_nlist.block_model(blk); + LogicalModelId model = atom_nlist.block_model(blk); unique_models.insert(model); } /* For each technology-mapped logic model, find logical block types * that can accommodate that logic model */ - for (auto model : unique_models) { - model_candidates[model] = {}; + for (LogicalModelId model : unique_models) { + VTR_ASSERT(model.is_valid()); + VTR_ASSERT(model_candidates[model].empty()); for (auto const& type : device_ctx.logical_block_types) { - if (block_type_contains_blif_model(&type, model->name)) { + if (block_type_contains_blif_model(&type, models.model_name(model))) { model_candidates[model].push_back(&type); } } @@ -209,7 +213,7 @@ size_t update_pb_type_count(const t_pb* pb, std::map& pb_type_c pb_type_count[pb_type]++; - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { for (int i = 0; i < mode->num_pb_type_children; i++) { for (int j = 0; j < mode->pb_type_children[i].num_pb; j++) { if (pb->child_pbs[i] && pb->child_pbs[i][j].name) { @@ -268,16 +272,15 @@ void print_pb_type_count(const ClusteredNetlist& clb_nlist) { VTR_LOG("\n"); } -t_logical_block_type_ptr identify_logic_block_type(const std::map>& primitive_candidate_block_types) { - std::string lut_name = ".names"; +t_logical_block_type_ptr identify_logic_block_type(const vtr::vector>& primitive_candidate_block_types, + const LogicalModels& models) { + LogicalModelId lut_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); - for (auto& model : primitive_candidate_block_types) { - std::string model_name(model.first->name); - if (model_name == lut_name) - return model.second[0]; - } + VTR_ASSERT(lut_model_id.is_valid()); + if (primitive_candidate_block_types[lut_model_id].size() == 0) + return nullptr; - return nullptr; + return primitive_candidate_block_types[lut_model_id][0]; } t_pb_type* identify_le_block_type(t_logical_block_type_ptr logic_block_type) { @@ -360,7 +363,7 @@ bool pb_used_for_blif_model(const t_pb* pb, const std::string& blif_model_name) } } - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { for (int i = 0; i < mode->num_pb_type_children; i++) { for (int j = 0; j < mode->pb_type_children[i].num_pb; j++) { if (pb->child_pbs[i] && pb->child_pbs[i][j].name) { diff --git a/vpr/src/pack/cluster_util.h b/vpr/src/pack/cluster_util.h index 4f4c2b5bec8..82fcf805047 100644 --- a/vpr/src/pack/cluster_util.h +++ b/vpr/src/pack/cluster_util.h @@ -4,6 +4,7 @@ #include #include #include "cluster_legalizer.h" +#include "logic_types.h" #include "vtr_vector.h" class AtomNetId; @@ -54,7 +55,7 @@ void print_pack_status(int tot_num_molecules, void rebuild_attraction_groups(AttractionInfo& attraction_groups, const ClusterLegalizer& cluster_legalizer); -std::map> identify_primitive_candidate_block_types(); +vtr::vector> identify_primitive_candidate_block_types(); /** * @brief Identify which nets in the atom netlist are driven by the same atom @@ -90,7 +91,8 @@ void print_pb_type_count(const ClusteredNetlist& clb_nlist); * @brief This function identifies the logic block type which is defined by the * block type which has a lut primitive. */ -t_logical_block_type_ptr identify_logic_block_type(const std::map>& primitive_candidate_block_types); +t_logical_block_type_ptr identify_logic_block_type(const vtr::vector>& primitive_candidate_block_types, + const LogicalModels& models); /* * @brief This function returns the pb_type that is similar to Logic Element (LE) diff --git a/vpr/src/pack/greedy_candidate_selector.cpp b/vpr/src/pack/greedy_candidate_selector.cpp index b202035ec59..0ae3972140b 100644 --- a/vpr/src/pack/greedy_candidate_selector.cpp +++ b/vpr/src/pack/greedy_candidate_selector.cpp @@ -19,12 +19,14 @@ #include "cluster_legalizer.h" #include "cluster_placement.h" #include "greedy_clusterer.h" +#include "logic_types.h" #include "prepack.h" #include "timing_info.h" #include "vpr_types.h" #include "vtr_assert.h" #include "vtr_ndmatrix.h" #include "vtr_vector.h" +#include "vtr_vector_map.h" /* * @brief Get gain of packing molecule into current cluster. @@ -62,7 +64,6 @@ static void add_molecule_to_pb_stats_candidates( PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, t_logical_block_type_ptr cluster_type, - int max_queue_size, AttractionInfo& attraction_groups, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -86,13 +87,14 @@ GreedyCandidateSelector::GreedyCandidateSelector( const t_packer_opts& packer_opts, bool allow_unrelated_clustering, const t_molecule_stats& max_molecule_stats, - const std::map>& primitive_candidate_block_types, + const vtr::vector>& primitive_candidate_block_types, const t_pack_high_fanout_thresholds& high_fanout_thresholds, const std::unordered_set& is_clock, const std::unordered_set& is_global, const std::unordered_set& net_output_feeds_driving_block_input, const PreClusterTimingManager& pre_cluster_timing_manager, const APPackContext& appack_ctx, + const LogicalModels& models, int log_verbosity) : atom_netlist_(atom_netlist) , prepacker_(prepacker) @@ -110,7 +112,7 @@ GreedyCandidateSelector::GreedyCandidateSelector( // Initialize unrelated clustering data if unrelated clustering is enabled. if (allow_unrelated_clustering_) { - initialize_unrelated_clustering_data(max_molecule_stats); + initialize_unrelated_clustering_data(max_molecule_stats, models); } /* TODO: This is memory inefficient, fix if causes problems */ @@ -119,7 +121,7 @@ GreedyCandidateSelector::GreedyCandidateSelector( clb_inter_blk_nets_.resize(atom_netlist.blocks().size()); } -void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molecule_stats& max_molecule_stats) { +void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molecule_stats& max_molecule_stats, const LogicalModels& models) { // Create a sorted list of molecules, sorted on decreasing molecule base // gain. (Highest gain). std::vector molecules_vector; @@ -177,7 +179,7 @@ void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molec t_flat_pl_loc mol_pos = get_molecule_pos(mol_id, prepacker_, appack_ctx_); //Figure out how many external inputs are used by this molecule - t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_); + t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_, models); int ext_inps = molecule_stats.num_used_ext_inputs; //Insert the molecule into the unclustered lists by number of external inputs @@ -196,7 +198,7 @@ void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molec // molecules for each number of used external inputs. for (PackMoleculeId mol_id : molecules_vector) { //Figure out how many external inputs are used by this molecule - t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_); + t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_, models); int ext_inps = molecule_stats.num_used_ext_inputs; //Insert the molecule into the unclustered lists by number of external inputs @@ -216,13 +218,11 @@ ClusterGainStats GreedyCandidateSelector::create_cluster_gain_stats( // Initialize the cluster gain stats. ClusterGainStats cluster_gain_stats; cluster_gain_stats.seed_molecule_id = cluster_seed_mol_id; - cluster_gain_stats.num_feasible_blocks = NOT_VALID; cluster_gain_stats.has_done_connectivity_and_timing = false; - // TODO: The reason this is being resized and not reserved is due to legacy - // code which should be updated. - cluster_gain_stats.feasible_blocks.resize(packer_opts_.feasible_block_array_size); - for (int i = 0; i < packer_opts_.feasible_block_array_size; i++) - cluster_gain_stats.feasible_blocks[i] = PackMoleculeId::INVALID(); + cluster_gain_stats.initial_search_for_feasible_blocks = true; + cluster_gain_stats.num_candidates_proposed = 0; + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; + cluster_gain_stats.feasible_blocks.clear(); cluster_gain_stats.tie_break_high_fanout_net = AtomNetId::INVALID(); cluster_gain_stats.explore_transitive_fanout = true; @@ -285,8 +285,10 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); /* reset list of feasible blocks */ - cluster_gain_stats.num_feasible_blocks = NOT_VALID; cluster_gain_stats.has_done_connectivity_and_timing = false; + cluster_gain_stats.initial_search_for_feasible_blocks = true; + cluster_gain_stats.num_candidates_proposed = 0; + cluster_gain_stats.feasible_blocks.clear(); /* TODO: Allow clusters to have more than one attraction group. */ if (atom_grp_id.is_valid()) cluster_gain_stats.attraction_grp_id = atom_grp_id; @@ -296,7 +298,7 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( AtomNetId net_id = atom_netlist_.pin_net(pin_id); e_gain_update gain_flag = e_gain_update::NO_GAIN; - if (!is_clock_.count(net_id) || !packer_opts_.global_clocks) + if (!is_clock_.count(net_id)) gain_flag = e_gain_update::GAIN; mark_and_update_partial_gain(cluster_gain_stats, @@ -324,13 +326,9 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( for (AtomPinId pin_id : atom_netlist_.block_clock_pins(blk_id)) { AtomNetId net_id = atom_netlist_.pin_net(pin_id); - e_gain_update gain_flag = e_gain_update::GAIN; - if (packer_opts_.global_clocks) - gain_flag = e_gain_update::NO_GAIN; - mark_and_update_partial_gain(cluster_gain_stats, net_id, - gain_flag, + e_gain_update::NO_GAIN, blk_id, cluster_legalizer, high_fanout_net_threshold, @@ -620,9 +618,9 @@ void GreedyCandidateSelector::update_total_gain(ClusterGainStats& cluster_gain_s VTR_ASSERT(num_used_pins > 0); if (packer_opts_.connection_driven) { /*try to absorb as many connections as possible*/ - cluster_gain_stats.gain[blk_id] = ((1 - packer_opts_.beta) + cluster_gain_stats.gain[blk_id] = ((1 - packer_opts_.connection_gain_weight) * (float)cluster_gain_stats.sharing_gain[blk_id] - + packer_opts_.beta * (float)cluster_gain_stats.connection_gain[blk_id]) + + packer_opts_.connection_gain_weight * (float)cluster_gain_stats.connection_gain[blk_id]) / (num_used_pins); } else { cluster_gain_stats.gain[blk_id] = ((float)cluster_gain_stats.sharing_gain[blk_id]) @@ -631,9 +629,9 @@ void GreedyCandidateSelector::update_total_gain(ClusterGainStats& cluster_gain_s /* Add in timing driven cost into cost function */ if (packer_opts_.timing_driven) { - cluster_gain_stats.gain[blk_id] = packer_opts_.alpha + cluster_gain_stats.gain[blk_id] = packer_opts_.timing_gain_weight * cluster_gain_stats.timing_gain[blk_id] - + (1.0 - packer_opts_.alpha) * (float)cluster_gain_stats.gain[blk_id]; + + (1.0 - packer_opts_.timing_gain_weight) * (float)cluster_gain_stats.gain[blk_id]; } } } @@ -681,8 +679,8 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( */ // 1. Find unpacked molecules based on criticality and strong connectedness (connected by low fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == NOT_VALID) { - cluster_gain_stats.num_feasible_blocks = 0; + if (cluster_gain_stats.initial_search_for_feasible_blocks) { + cluster_gain_stats.initial_search_for_feasible_blocks = false; add_cluster_molecule_candidates_by_connectivity_and_timing(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -692,7 +690,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( if (packer_opts_.prioritize_transitive_connectivity) { // 2. Find unpacked molecules based on transitive connections (eg. 2 hops away) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -700,7 +698,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 3. Find unpacked molecules based on weak connectedness (connected by high fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -708,7 +706,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } } else { //Reverse order // 3. Find unpacked molecules based on weak connectedness (connected by high fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -716,7 +714,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 2. Find unpacked molecules based on transitive connections (eg. 2 hops away) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -725,7 +723,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 4. Find unpacked molecules based on attraction group of the current cluster (if the cluster has an attraction group) - if (cluster_gain_stats.num_feasible_blocks == 0) { + if (cluster_gain_stats.feasible_blocks.empty()) { add_cluster_molecule_candidates_by_attraction_group(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -733,15 +731,25 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } /* Grab highest gain molecule */ - // If this was a vector, this would just be a pop_back. PackMoleculeId best_molecule = PackMoleculeId::INVALID(); - if (cluster_gain_stats.num_feasible_blocks > 0) { - cluster_gain_stats.num_feasible_blocks--; - int index = cluster_gain_stats.num_feasible_blocks; - best_molecule = cluster_gain_stats.feasible_blocks[index]; + // If there are feasible blocks being proposed and the number of suggestions did not reach the limit. + // Get the block with highest gain from the top of the priority queue. + if (!cluster_gain_stats.feasible_blocks.empty() && !cluster_gain_stats.current_stage_candidates_proposed_limit_reached()) { + best_molecule = cluster_gain_stats.feasible_blocks.pop().first; + VTR_ASSERT(best_molecule != PackMoleculeId::INVALID()); + cluster_gain_stats.num_candidates_proposed++; VTR_ASSERT(!cluster_legalizer.is_mol_clustered(best_molecule)); } + // If we have no feasible blocks, or we have reached the limit of number of pops, + // then we need to clear the feasible blocks list and reset the number of pops. + // This ensures that we can continue searching for feasible blocks for the remaining + // steps (2.transitive, 3.high fanout, 4.attraction group). + if (cluster_gain_stats.feasible_blocks.empty() || cluster_gain_stats.current_stage_candidates_proposed_limit_reached()) { + cluster_gain_stats.feasible_blocks.clear(); + cluster_gain_stats.num_candidates_proposed = 0; + } + // If we are allowing unrelated clustering and no molecule has been found, // get unrelated candidate for cluster. if (allow_unrelated_clustering_ && best_molecule == PackMoleculeId::INVALID()) { @@ -775,7 +783,9 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_connectivity_an LegalizationClusterId legalization_cluster_id, const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups) { - cluster_gain_stats.explore_transitive_fanout = true; /* If no legal molecules found, enable exploration of molecules two hops away */ + + cluster_gain_stats.explore_transitive_fanout = true; /* If no legal molecules found, enable exploration of molecules two hops away */ + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; // set the limit of candidates to propose for (AtomBlockId blk_id : cluster_gain_stats.marked_blocks) { // Get the molecule that contains this block. @@ -786,7 +796,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_connectivity_an add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -802,6 +811,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_transitive_conn AttractionInfo& attraction_groups) { //TODO: For now, only done by fan-out; should also consider fan-in cluster_gain_stats.explore_transitive_fanout = false; + cluster_gain_stats.candidates_propose_limit = std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_TRANSITIVE_EXPLORE); // set the limit of candidates to propose /* First time finding transitive fanout candidates therefore alloc and load them */ load_transitive_fanout_candidates(cluster_gain_stats, @@ -815,8 +825,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_transitive_conn add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - std::min(packer_opts_.feasible_block_array_size, - AAPACK_MAX_TRANSITIVE_EXPLORE), attraction_groups, prepacker_, atom_netlist_, @@ -835,6 +843,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn * related blocks */ AtomNetId net_id = cluster_gain_stats.tie_break_high_fanout_net; + cluster_gain_stats.candidates_propose_limit = std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_TRANSITIVE_EXPLORE); // set the limit of candidates to propose int count = 0; for (AtomPinId pin_id : atom_netlist_.net_pins(net_id)) { @@ -849,8 +858,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - std::min(packer_opts_.feasible_block_array_size, - AAPACK_MAX_HIGH_FANOUT_EXPLORE), attraction_groups, prepacker_, atom_netlist_, @@ -878,6 +885,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou * group molecules for candidate molecules. */ AttractGroupId grp_id = cluster_gain_stats.attraction_grp_id; + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; // set the limit of candidates to propose if (grp_id == AttractGroupId::INVALID()) { return; } @@ -885,10 +893,10 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou AttractionGroup& group = attraction_groups.get_attraction_group_info(grp_id); std::vector available_atoms; for (AtomBlockId atom_id : group.group_atoms) { - const auto& atom_model = atom_netlist_.block_model(atom_id); - auto itr = primitive_candidate_block_types_.find(atom_model); - VTR_ASSERT(itr != primitive_candidate_block_types_.end()); - const std::vector& candidate_types = itr->second; + LogicalModelId atom_model = atom_netlist_.block_model(atom_id); + VTR_ASSERT(atom_model.is_valid()); + VTR_ASSERT(!primitive_candidate_block_types_[atom_model].empty()); + const auto& candidate_types = primitive_candidate_block_types_[atom_model]; //Only consider molecules that are unpacked and of the correct type if (!cluster_legalizer.is_atom_clustered(atom_id) @@ -910,7 +918,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -932,7 +939,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -947,7 +953,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, t_logical_block_type_ptr cluster_type, - int max_queue_size, AttractionInfo& attraction_groups, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -961,11 +966,7 @@ static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, // distance. Was found to create too many RAM blocks. if (!cluster_gain_stats.is_memory) { // Get the max dist for this block type. - float max_dist = appack_ctx.appack_options.max_candidate_distance; - // If this cluster is anything but a logic block type, then scale - // up the max distance. - if (cluster_type->index != appack_ctx.appack_options.logic_block_type_index) - max_dist *= appack_ctx.appack_options.max_candidate_distance_non_lb_scale; + float max_dist = appack_ctx.max_distance_threshold_manager.get_max_dist_threshold(*cluster_type); // If the distance from the cluster to the candidate is too large, // do not add this molecule to the list of candidates. @@ -1001,45 +1002,18 @@ static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, } } - for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { - return; // already in queue, do nothing - } + // if already in queue, do nothing + if (cluster_gain_stats.feasible_blocks.contains(molecule_id)) { + return; } - if (cluster_gain_stats.num_feasible_blocks >= max_queue_size - 1) { - /* maximum size for array, remove smallest gain element and sort */ - if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(cluster_gain_stats.feasible_blocks[0], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - /* single loop insertion sort */ - int j; - for (j = 0; j < cluster_gain_stats.num_feasible_blocks - 1; j++) { - if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) <= get_molecule_gain(cluster_gain_stats.feasible_blocks[j + 1], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - cluster_gain_stats.feasible_blocks[j] = molecule_id; - break; - } else { - cluster_gain_stats.feasible_blocks[j] = cluster_gain_stats.feasible_blocks[j + 1]; - } - } - if (j == cluster_gain_stats.num_feasible_blocks - 1) { - cluster_gain_stats.feasible_blocks[j] = molecule_id; - } - } - } else { - /* Expand array and single loop insertion sort */ - int j; - for (j = cluster_gain_stats.num_feasible_blocks - 1; j >= 0; j--) { - if (get_molecule_gain(cluster_gain_stats.feasible_blocks[j], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - cluster_gain_stats.feasible_blocks[j + 1] = cluster_gain_stats.feasible_blocks[j]; - } else { - cluster_gain_stats.feasible_blocks[j + 1] = molecule_id; - break; - } - } - if (j < 0) { - cluster_gain_stats.feasible_blocks[0] = molecule_id; - } - cluster_gain_stats.num_feasible_blocks++; + for (std::pair& feasible_block : cluster_gain_stats.feasible_blocks.heap) { + VTR_ASSERT_DEBUG(get_molecule_gain(feasible_block.first, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) == feasible_block.second); } + + // Insert the molecule into the queue sorted by gain, and maintain the heap property + float molecule_gain = get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx); + cluster_gain_stats.feasible_blocks.push(molecule_id, molecule_gain); } /* @@ -1050,27 +1024,7 @@ static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, */ static void remove_molecule_from_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats) { - int molecule_index; - bool found_molecule = false; - - //find the molecule index - for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { - found_molecule = true; - molecule_index = i; - } - } - - //if it is not in the array, return - if (found_molecule == false) { - return; - } - - //Otherwise, shift the molecules while removing the specified molecule - for (int j = molecule_index; j < cluster_gain_stats.num_feasible_blocks - 1; j++) { - cluster_gain_stats.feasible_blocks[j] = cluster_gain_stats.feasible_blocks[j + 1]; - } - cluster_gain_stats.num_feasible_blocks--; + cluster_gain_stats.feasible_blocks.remove_at_pop_time(molecule_id); } /* diff --git a/vpr/src/pack/greedy_candidate_selector.h b/vpr/src/pack/greedy_candidate_selector.h index 2b3eb23a1f5..b39ad469b45 100644 --- a/vpr/src/pack/greedy_candidate_selector.h +++ b/vpr/src/pack/greedy_candidate_selector.h @@ -16,11 +16,14 @@ #include "attraction_groups.h" #include "cluster_legalizer.h" #include "greedy_clusterer.h" +#include "logic_types.h" #include "physical_types.h" #include "prepack.h" #include "vtr_ndmatrix.h" #include "vtr_vector.h" #include "vtr_random.h" +#include "vtr_vector_map.h" +#include "lazy_pop_unique_priority_queue.h" // Forward declarations class AtomNetlist; @@ -29,7 +32,6 @@ class FlatPlacementInfo; class PreClusterTimingManager; class Prepacker; class t_pack_high_fanout_thresholds; -struct t_model; struct t_molecule_stats; struct t_packer_opts; @@ -96,13 +98,6 @@ struct ClusterGainStats { /// with the cluster. AttractGroupId attraction_grp_id; - /// @brief Array of feasible blocks to select from [0..max_array_size-1] - /// - /// Sorted in ascending gain order so that the last cluster_ctx.blocks is - /// the most desirable (this makes it easy to pop blocks off the list. - std::vector feasible_blocks; - int num_feasible_blocks; - /// @brief The flat placement location of this cluster. /// /// This is some function of the positions of the molecules which have been @@ -125,6 +120,25 @@ struct ClusterGainStats { /// set when the stats are created based on the primitive pb type /// of the seed. bool is_memory = false; + + /// @brief List of feasible block and its gain pairs. + /// The list is maintained in heap structure with the highest gain block + /// at the front. + LazyPopUniquePriorityQueue feasible_blocks; + + /// @brief Indicator for the initial search for feasible blocks. + bool initial_search_for_feasible_blocks; + + /// @brief Limit for the number of candiate proposed at each stage. + unsigned candidates_propose_limit; + + /// @brief Counter for the number of candiate proposed at each stage. + unsigned num_candidates_proposed; + + /// @brief Check if the current stage candidates proposed limit is reached. + bool current_stage_candidates_proposed_limit_reached() { + return num_candidates_proposed >= candidates_propose_limit; + } }; /** @@ -240,13 +254,14 @@ class GreedyCandidateSelector { const t_packer_opts& packer_opts, bool allow_unrelated_clustering, const t_molecule_stats& max_molecule_stats, - const std::map>& primitive_candidate_block_types, + const vtr::vector>& primitive_candidate_block_types, const t_pack_high_fanout_thresholds& high_fanout_thresholds, const std::unordered_set& is_clock, const std::unordered_set& is_global, const std::unordered_set& net_output_feeds_driving_block_input, const PreClusterTimingManager& pre_cluster_timing_manager, const APPackContext& appack_ctx, + const LogicalModels& models, int log_verbosity); /** @@ -375,7 +390,8 @@ class GreedyCandidateSelector { * clustering. */ void initialize_unrelated_clustering_data( - const t_molecule_stats& max_molecule_stats); + const t_molecule_stats& max_molecule_stats, + const LogicalModels& models); // ===================================================================== // // Cluster Gain Stats Updating @@ -441,7 +457,7 @@ class GreedyCandidateSelector { // Cluster Candidate Selection // ===================================================================== // - /* + /** * @brief Add molecules with strong connectedness to the current cluster to * the list of feasible blocks. */ @@ -468,7 +484,7 @@ class GreedyCandidateSelector { LegalizationClusterId legalization_cluster_id, const ClusterLegalizer& cluster_legalizer); - /* + /** * @brief Add molecules based on transitive connections (eg. 2 hops away) * with current cluster. */ @@ -478,7 +494,7 @@ class GreedyCandidateSelector { const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups); - /* + /** * @brief Add molecules based on weak connectedness (connected by high * fanout nets) with current cluster. */ @@ -488,7 +504,7 @@ class GreedyCandidateSelector { const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups); - /* + /** * @brief If the current cluster being packed has an attraction group * associated with it (i.e. there are atoms in it that belong to an * attraction group), this routine adds molecules from the associated @@ -547,7 +563,7 @@ class GreedyCandidateSelector { /// @brief Pre-computed vector of logical block types that could implement /// the given model in the architecture. - const std::map>& primitive_candidate_block_types_; + const vtr::vector>& primitive_candidate_block_types_; /// @brief The high-fanout thresholds per logical block type. Used to ignore /// certain nets when calculating the gain for the next candidate diff --git a/vpr/src/pack/greedy_clusterer.cpp b/vpr/src/pack/greedy_clusterer.cpp index 7673005af93..b7845c4f564 100644 --- a/vpr/src/pack/greedy_clusterer.cpp +++ b/vpr/src/pack/greedy_clusterer.cpp @@ -49,11 +49,11 @@ #include "cluster_util.h" #include "greedy_candidate_selector.h" #include "greedy_seed_selector.h" +#include "logic_types.h" #include "physical_types.h" #include "prepack.h" #include "vpr_context.h" #include "vtr_math.h" -#include "vtr_vector.h" namespace { @@ -116,7 +116,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, clustering_stats.num_molecules = prepacker.molecules().size(); // Calculate the max molecule stats, which is used for gain calculation. - const t_molecule_stats max_molecule_stats = prepacker.calc_max_molecule_stats(atom_netlist_); + const t_molecule_stats max_molecule_stats = prepacker.calc_max_molecule_stats(atom_netlist_, arch_.models); // Create the greedy candidate selector. This will be used to select // candidate molecules to add to the clusters. @@ -132,6 +132,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, net_output_feeds_driving_block_input_, pre_cluster_timing_manager_, appack_ctx_, + arch_.models, log_verbosity_); // Create the greedy seed selector. @@ -139,6 +140,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, prepacker, packer_opts_.cluster_seed_type, max_molecule_stats, + arch_.models, pre_cluster_timing_manager_); // Pick the first seed molecule. @@ -366,11 +368,10 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( /* Allocate a dummy initial cluster and load a atom block as a seed and check if it is legal */ AtomBlockId root_atom = seed_mol.atom_block_ids[seed_mol.root]; const std::string& root_atom_name = atom_netlist_.block_name(root_atom); - const t_model* root_model = atom_netlist_.block_model(root_atom); - - auto itr = primitive_candidate_block_types_.find(root_model); - VTR_ASSERT(itr != primitive_candidate_block_types_.end()); - std::vector candidate_types = itr->second; + LogicalModelId root_model_id = atom_netlist_.block_model(root_atom); + VTR_ASSERT(root_model_id.is_valid()); + VTR_ASSERT(!primitive_candidate_block_types_[root_model_id].empty()); + std::vector candidate_types = primitive_candidate_block_types_[root_model_id]; if (balance_block_type_utilization) { //We sort the candidate types in ascending order by their current utilization. @@ -395,7 +396,7 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( } if (log_verbosity_ > 2) { - VTR_LOG("\tSeed: '%s' (%s)", root_atom_name.c_str(), root_model->name); + VTR_LOG("\tSeed: '%s' (%s)", root_atom_name.c_str(), arch_.models.get_model(root_model_id).name); VTR_LOGV(seed_mol.pack_pattern, " molecule_type %s molecule_size %zu", seed_mol.pack_pattern->name, seed_mol.atom_block_ids.size()); VTR_LOG("\n"); @@ -435,7 +436,7 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( VPR_FATAL_ERROR(VPR_ERROR_PACK, "Can not find any logic block that can implement molecule.\n" "\tAtom %s (%s)\n", - root_atom_name.c_str(), root_model->name); + root_atom_name.c_str(), arch_.models.model_name(root_model_id).c_str()); } } @@ -510,8 +511,9 @@ bool GreedyClusterer::try_add_candidate_mol_to_cluster(PackMoleculeId candidate_ AtomBlockId blk_id = candidate_mol.atom_block_ids[candidate_mol.root]; VTR_ASSERT(blk_id.is_valid()); std::string blk_name = atom_netlist_.block_name(blk_id); - const t_model* blk_model = atom_netlist_.block_model(blk_id); - VTR_LOG("'%s' (%s)", blk_name.c_str(), blk_model->name); + LogicalModelId blk_model_id = atom_netlist_.block_model(blk_id); + std::string blk_model_name = arch_.models.model_name(blk_model_id); + VTR_LOG("'%s' (%s)", blk_name.c_str(), blk_model_name.c_str()); VTR_LOGV(candidate_mol.pack_pattern, " molecule %s molecule_size %zu", candidate_mol.pack_pattern->name, candidate_mol.atom_block_ids.size()); @@ -524,7 +526,7 @@ bool GreedyClusterer::try_add_candidate_mol_to_cluster(PackMoleculeId candidate_ void GreedyClusterer::report_le_physical_block_usage(const ClusterLegalizer& cluster_legalizer) { // find the cluster type that has lut primitives - auto logic_block_type = identify_logic_block_type(primitive_candidate_block_types_); + auto logic_block_type = identify_logic_block_type(primitive_candidate_block_types_, arch_.models); // find a LE pb_type within the found logic_block_type auto le_pb_type = identify_le_block_type(logic_block_type); diff --git a/vpr/src/pack/greedy_clusterer.h b/vpr/src/pack/greedy_clusterer.h index 4c805ffa594..cb92a0dbccf 100644 --- a/vpr/src/pack/greedy_clusterer.h +++ b/vpr/src/pack/greedy_clusterer.h @@ -12,8 +12,10 @@ #include #include #include "cluster_legalizer.h" +#include "logic_types.h" #include "physical_types.h" #include "prepack.h" +#include "vtr_vector.h" // Forward declarations class APPackContext; @@ -247,7 +249,7 @@ class GreedyClusterer { const APPackContext& appack_ctx_; /// @brief Pre-computed logical block types for each model in the architecture. - const std::map> primitive_candidate_block_types_; + const vtr::vector> primitive_candidate_block_types_; /// @brief The verbosity of log messages produced by the clusterer. /// diff --git a/vpr/src/pack/greedy_seed_selector.cpp b/vpr/src/pack/greedy_seed_selector.cpp index c9d1b9397c5..9850500400a 100644 --- a/vpr/src/pack/greedy_seed_selector.cpp +++ b/vpr/src/pack/greedy_seed_selector.cpp @@ -10,19 +10,16 @@ #include #include #include "PreClusterTimingManager.h" -#include "flat_placement_types.h" #include "atom_netlist.h" #include "cluster_legalizer.h" -#include "device_grid.h" #include "echo_files.h" -#include "globals.h" #include "greedy_clusterer.h" +#include "logic_types.h" #include "prepack.h" #include "vpr_error.h" #include "vpr_types.h" #include "vtr_assert.h" #include "vtr_math.h" -#include "vtr_ndmatrix.h" #include "vtr_vector.h" /** @@ -34,6 +31,7 @@ static inline float get_seed_gain(AtomBlockId blk_id, const AtomNetlist& atom_netlist, const Prepacker& prepacker, + const LogicalModels& models, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, const vtr::vector& atom_criticality) { @@ -49,7 +47,7 @@ static inline float get_seed_gain(AtomBlockId blk_id, // instead. case e_cluster_seed::MAX_INPUTS: { PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist, models); return molecule_stats.num_used_ext_inputs; } // By blended gain (criticality and inputs used). @@ -60,7 +58,7 @@ static inline float get_seed_gain(AtomBlockId blk_id, float seed_blend_fac = 0.5f; PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist, models); VTR_ASSERT(max_molecule_stats.num_used_ext_inputs > 0); float used_ext_input_pin_ratio = vtr::safe_ratio(molecule_stats.num_used_ext_inputs, max_molecule_stats.num_used_ext_inputs); @@ -74,7 +72,7 @@ static inline float get_seed_gain(AtomBlockId blk_id, // harder to pack. case e_cluster_seed::MAX_PINS: { PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist, models); return molecule_stats.num_pins; } // By input pins per molecule (i.e. available pins on primitives, not pins in use). @@ -82,12 +80,12 @@ static inline float get_seed_gain(AtomBlockId blk_id, // harder to pack. case e_cluster_seed::MAX_INPUT_PINS: { PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist, models); return molecule_stats.num_input_pins; } case e_cluster_seed::BLEND2: { PackMoleculeId mol_id = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol_id, atom_netlist); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol_id, atom_netlist, models); float pin_ratio = vtr::safe_ratio(molecule_stats.num_pins, max_molecule_stats.num_pins); float input_pin_ratio = vtr::safe_ratio(molecule_stats.num_input_pins, max_molecule_stats.num_input_pins); @@ -134,7 +132,8 @@ static inline void print_seed_gains(const char* fname, const std::vector& seed_atoms, const vtr::vector& atom_gain, const vtr::vector& atom_criticality, - const AtomNetlist& atom_netlist) { + const AtomNetlist& atom_netlist, + const LogicalModels& models) { FILE* fp = vtr::fopen(fname, "w"); // For pretty formatting determine the maximum name length @@ -143,8 +142,8 @@ static inline void print_seed_gains(const char* fname, for (auto blk_id : atom_netlist.blocks()) { max_name_len = std::max(max_name_len, (int)atom_netlist.block_name(blk_id).size()); - const t_model* model = atom_netlist.block_model(blk_id); - max_type_len = std::max(max_type_len, (int)strlen(model->name)); + std::string model_name = models.model_name(atom_netlist.block_model(blk_id)); + max_type_len = std::max(max_type_len, model_name.size()); } fprintf(fp, "%-*s %-*s %8s %8s\n", max_name_len, "atom_block_name", max_type_len, "atom_block_type", "gain", "criticality"); @@ -153,8 +152,8 @@ static inline void print_seed_gains(const char* fname, std::string name = atom_netlist.block_name(blk_id); fprintf(fp, "%-*s ", max_name_len, name.c_str()); - const t_model* model = atom_netlist.block_model(blk_id); - fprintf(fp, "%-*s ", max_type_len, model->name); + std::string model_name = models.model_name(atom_netlist.block_model(blk_id)); + fprintf(fp, "%-*s ", max_type_len, model_name.c_str()); fprintf(fp, "%*f ", std::max((int)strlen("gain"), 8), atom_gain[blk_id]); fprintf(fp, "%*f ", std::max((int)strlen("criticality"), 8), atom_criticality[blk_id]); @@ -168,6 +167,7 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, const Prepacker& prepacker, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, + const LogicalModels& models, const PreClusterTimingManager& pre_cluster_timing_manager) : seed_atoms_(atom_netlist.blocks().begin(), atom_netlist.blocks().end()) { // Seed atoms list is initialized with all atoms in the atom netlist. @@ -193,6 +193,7 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, atom_gains[blk_id] = get_seed_gain(blk_id, atom_netlist, prepacker, + models, seed_type, max_molecule_stats, atom_criticality); @@ -214,7 +215,7 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, // Print the seed gains if requested. if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES)) { print_seed_gains(getEchoFileName(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES), - seed_atoms_, atom_gains, atom_criticality, atom_netlist); + seed_atoms_, atom_gains, atom_criticality, atom_netlist, models); } // Set the starting seed index (the index of the first molecule to propose). diff --git a/vpr/src/pack/greedy_seed_selector.h b/vpr/src/pack/greedy_seed_selector.h index 5f152f65236..0207949bef1 100644 --- a/vpr/src/pack/greedy_seed_selector.h +++ b/vpr/src/pack/greedy_seed_selector.h @@ -14,6 +14,7 @@ // Forward declarations class AtomNetlist; class ClusterLegalizer; +class LogicalModels; class PreClusterTimingManager; struct t_molecule_stats; @@ -53,6 +54,7 @@ class GreedySeedSelector { const Prepacker& prepacker, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, + const LogicalModels& models, const PreClusterTimingManager& pre_cluster_timing_manager); /** diff --git a/vpr/src/pack/lb_type_rr_graph.cpp b/vpr/src/pack/lb_type_rr_graph.cpp index 12082386275..bb93177ffd2 100644 --- a/vpr/src/pack/lb_type_rr_graph.cpp +++ b/vpr/src/pack/lb_type_rr_graph.cpp @@ -23,8 +23,8 @@ #include #include +#include "vpr_utils.h" #include "vtr_assert.h" -#include "vtr_memory.h" #include "vtr_util.h" #include "physical_types.h" @@ -296,7 +296,7 @@ static void alloc_and_load_lb_type_rr_graph_for_pb_graph_node(const t_pb_graph_n parent_node = pb_graph_node->parent_pb_graph_node; int num_modes; - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* This pb_graph_node is a terminating leaf node (primitive) */ /* alloc and load input pins that connect to sinks */ diff --git a/vpr/src/pack/noc_aware_cluster_util.cpp b/vpr/src/pack/noc_aware_cluster_util.cpp index aba034992f2..27ef2a49e94 100644 --- a/vpr/src/pack/noc_aware_cluster_util.cpp +++ b/vpr/src/pack/noc_aware_cluster_util.cpp @@ -2,21 +2,23 @@ #include "noc_aware_cluster_util.h" #include "atom_netlist.h" #include "globals.h" +#include "logic_types.h" #include "vpr_types.h" +#include "vpr_utils.h" #include -std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist) { +std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist, const LogicalModels& models) { // NoC router atoms are expected to have a specific blif model - const std::string noc_router_blif_model_name = "noc_router_adapter_block"; + LogicalModelId noc_route_blif_model_id = models.get_model_by_name("noc_router_adapter_block"); // stores found NoC router atoms std::vector noc_router_atoms; // iterate over all atoms and find those whose blif model matches for (auto atom_id : atom_netlist.blocks()) { - const t_model* model = atom_netlist.block_model(atom_id); - if (noc_router_blif_model_name == model->name) { + LogicalModelId model_id = atom_netlist.block_model(atom_id); + if (model_id == noc_route_blif_model_id) { noc_router_atoms.push_back(atom_id); } } diff --git a/vpr/src/pack/noc_aware_cluster_util.h b/vpr/src/pack/noc_aware_cluster_util.h index a414d147bcf..dbdb79d5785 100644 --- a/vpr/src/pack/noc_aware_cluster_util.h +++ b/vpr/src/pack/noc_aware_cluster_util.h @@ -22,6 +22,7 @@ class AtomNetlist; class AtomBlockId; +class LogicalModels; class t_pack_high_fanout_thresholds; /** @@ -30,7 +31,7 @@ class t_pack_high_fanout_thresholds; * * @return The atom block IDs of the NoC router blocks in the netlist. */ -std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist); +std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist, const LogicalModels& models); /** * @brief Runs BFS starting from NoC routers to find all connected diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index 60a371aee46..9cdc27ac399 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -229,7 +229,7 @@ static std::string clustering_xml_interconnect_text(t_logical_block_type_ptr typ if (prev_node == OPEN) { /* No previous driver implies that this is either a top-level input pin or a primitive output pin */ const t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, inode); - VTR_ASSERT(cur_pin->parent_node->pb_type->parent_mode == nullptr || (cur_pin->is_primitive_pin() && cur_pin->port->type == OUT_PORT)); + VTR_ASSERT(cur_pin->parent_node->pb_type->is_root() || (cur_pin->is_primitive_pin() && cur_pin->port->type == OUT_PORT)); return clustering_xml_net_text(pb_route[inode].atom_net_id); } else { const t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, inode); @@ -291,7 +291,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo for (j = 0; j < pb_type->ports[i].num_pins; j++) { const t_pb_graph_pin* pin = &pb_graph_node->output_pins[port_index][j]; node_index = pin->pin_count_in_cluster; - if (pb_type->num_modes > 0 && pb_route.count(node_index) && pb_route[node_index].atom_net_id) { + if (!pb_type->is_primitive() && pb_route.count(node_index) && pb_route[node_index].atom_net_id) { prev_node = pb_route[node_index].driver_pb_pin_id; const t_pb_graph_pin* prev_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, prev_node); const t_pb_graph_edge* edge = get_edge_between_pins(prev_pin, pin); @@ -330,7 +330,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo for (j = 0; j < pb_type->ports[i].num_pins; j++) { node_index = pb_graph_node->input_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id)); } else { pins.push_back(clustering_xml_interconnect_text(type, pb_graph_pin_lookup_from_index_by_type, node_index, pb_route)); @@ -371,7 +371,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo std::vector pins; for (j = 0; j < pb_type->ports[i].num_pins; j++) { node_index = pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id)); } else { pins.push_back(clustering_xml_interconnect_text(type, pb_graph_pin_lookup_from_index_by_type, node_index, pb_route)); @@ -382,7 +382,7 @@ static void clustering_xml_open_block(pugi::xml_node& parent_node, t_logical_blo } } - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { for (i = 0; i < mode->num_pb_type_children; i++) { child_pb_type = &mode->pb_type_children[i]; for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { @@ -426,7 +426,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty block_node.append_attribute("name") = pb->name; block_node.append_attribute("instance") = vtr::string_fmt("%s[%d]", pb_type->name, pb_index).c_str(); - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { block_node.append_attribute("mode") = mode->name; } else { const auto& atom_ctx = g_vpr_ctx.atom(); @@ -460,7 +460,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty for (j = 0; j < pb_type->ports[i].num_pins; j++) { node_index = pb->pb_graph_node->input_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { if (pb_route.count(node_index)) { pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id)); } else { @@ -475,7 +475,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty //The cluster router may have rotated equivalent pins (e.g. LUT inputs), //record the resulting rotation here so it can be unambigously mapped //back to the atom netlist - if (pb_type->ports[i].equivalent != PortEquivalence::NONE && pb_type->parent_mode != nullptr && pb_type->num_modes == 0) { + if (pb_type->ports[i].equivalent != PortEquivalence::NONE && pb_type->parent_mode != nullptr && pb_type->is_primitive()) { //This is a primitive with equivalent inputs auto& atom_ctx = g_vpr_ctx.atom(); @@ -560,7 +560,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty std::vector pins; for (j = 0; j < pb_type->ports[i].num_pins; j++) { node_index = pb->pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == nullptr) { + if (pb_type->is_root()) { if (pb_route.count(node_index)) { pins.push_back(clustering_xml_net_text(pb_route[node_index].atom_net_id)); } else { @@ -575,7 +575,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty } } - if (pb_type->num_modes > 0) { + if (!pb_type->is_primitive()) { for (i = 0; i < mode->num_pb_type_children; i++) { for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { /* If child pb is not used but routing is used, I must print things differently */ @@ -640,7 +640,7 @@ static void clustering_xml_blocks_from_netlist(pugi::xml_node& block_node, /* This routine dumps out the output netlist in a format suitable for * * input to vpr. This routine also dumps out the internal structure of * * the cluster, in essentially a graph based format. */ -void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_clocks, const std::unordered_set& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering, bool from_legalizer) { +void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, const std::unordered_set& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering, bool from_legalizer) { const DeviceContext& device_ctx = g_vpr_ctx.device(); const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); @@ -689,17 +689,15 @@ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_cloc block_node.append_child("inputs").text().set(vtr::join(inputs.begin(), inputs.end(), " ").c_str()); block_node.append_child("outputs").text().set(vtr::join(outputs.begin(), outputs.end(), " ").c_str()); - if (global_clocks) { - std::vector clocks; - for (auto net_id : atom_nlist.nets()) { - if (is_clock.count(net_id)) { - clocks.push_back(atom_nlist.net_name(net_id)); - } + std::vector clocks; + for (auto net_id : atom_nlist.nets()) { + if (is_clock.count(net_id)) { + clocks.push_back(atom_nlist.net_name(net_id)); } - - block_node.append_child("clocks").text().set(vtr::join(clocks.begin(), clocks.end(), " ").c_str()); } + block_node.append_child("clocks").text().set(vtr::join(clocks.begin(), clocks.end(), " ").c_str()); + if (skip_clustering == false) { if (from_legalizer) { VTR_ASSERT(cluster_legalizer_ptr != nullptr); @@ -724,15 +722,13 @@ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_cloc * As such, this function is expected to be a standard API * which can be called anytime and anywhere after packing is finished. ********************************************************************/ -void write_packing_results_to_xml(const bool& global_clocks, - const std::string& architecture_id, +void write_packing_results_to_xml(const std::string& architecture_id, const char* out_fname) { std::unordered_set is_clock = alloc_and_load_is_clock(); // Since the cluster legalizer is not being used to output the clustering // (from_legalizer is false), passing in nullptr. output_clustering(nullptr, - global_clocks, is_clock, architecture_id, out_fname, diff --git a/vpr/src/pack/output_clustering.h b/vpr/src/pack/output_clustering.h index 92d734248d1..c7537ee8c39 100644 --- a/vpr/src/pack/output_clustering.h +++ b/vpr/src/pack/output_clustering.h @@ -17,15 +17,13 @@ class ClusterLegalizer; /// clustered netlist. If from_legalizer is false, the clustered netlist currently /// in the global scope will be used. void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, - bool global_clocks, const std::unordered_set& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering, bool from_legalizer); -void write_packing_results_to_xml(const bool& global_clocks, - const std::string& architecture_id, +void write_packing_results_to_xml(const std::string& architecture_id, const char* out_fname); #endif diff --git a/vpr/src/pack/pack.cpp b/vpr/src/pack/pack.cpp index ec96e7c4d7c..57ee96a1a7f 100644 --- a/vpr/src/pack/pack.cpp +++ b/vpr/src/pack/pack.cpp @@ -29,6 +29,7 @@ static bool try_size_device_grid(const t_arch& arch, bool try_pack(const t_packer_opts& packer_opts, const t_analysis_opts& analysis_opts, + const t_ap_opts& ap_opts, const t_arch& arch, std::vector* lb_type_rr_graphs, const Prepacker& prepacker, @@ -120,12 +121,16 @@ bool try_pack(const t_packer_opts& packer_opts, high_fanout_thresholds, ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, packer_opts.enable_pin_feasibility_filter, + arch.models, packer_opts.pack_verbosity); VTR_LOG("Packing with pin utilization targets: %s\n", cluster_legalizer.get_target_external_pin_util().to_string().c_str()); VTR_LOG("Packing with high fanout thresholds: %s\n", high_fanout_thresholds.to_string().c_str()); // Construct the APPack Context. - APPackContext appack_ctx(flat_placement_info, device_ctx.grid); + APPackContext appack_ctx(flat_placement_info, + ap_opts, + device_ctx.logical_block_types, + device_ctx.grid); // Initialize the greedy clusterer. GreedyClusterer clusterer(packer_opts, diff --git a/vpr/src/pack/pack.h b/vpr/src/pack/pack.h index 64189ea4ee9..f484146ac66 100644 --- a/vpr/src/pack/pack.h +++ b/vpr/src/pack/pack.h @@ -9,6 +9,7 @@ class FlatPlacementInfo; class PreClusterTimingManager; class Prepacker; struct t_analysis_opts; +struct t_ap_opts; struct t_arch; struct t_lb_type_rr_node; struct t_packer_opts; @@ -37,6 +38,7 @@ struct t_packer_opts; */ bool try_pack(const t_packer_opts& packer_opts, const t_analysis_opts& analysis_opts, + const t_ap_opts& ap_opts, const t_arch& arch, std::vector* lb_type_rr_graphs, const Prepacker& prepacker, diff --git a/vpr/src/pack/pack_report.cpp b/vpr/src/pack/pack_report.cpp index 2dded7cda8b..154b75258a0 100644 --- a/vpr/src/pack/pack_report.cpp +++ b/vpr/src/pack/pack_report.cpp @@ -2,7 +2,6 @@ #include "vtr_ostream_guard.h" -#include "vpr_types.h" #include "vpr_utils.h" #include "histogram.h" diff --git a/vpr/src/pack/pack_types.h b/vpr/src/pack/pack_types.h index 8ebaf22b26b..994dbd73f1f 100644 --- a/vpr/src/pack/pack_types.h +++ b/vpr/src/pack/pack_types.h @@ -10,9 +10,8 @@ #include #include -#include "arch_types.h" #include "atom_netlist_fwd.h" -#include "attraction_groups.h" +#include "physical_types.h" struct t_pack_molecule; diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 02784e4321a..62055d7e192 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -13,7 +13,6 @@ #include #include -#include #include #include "vtr_util.h" @@ -23,17 +22,13 @@ #include "vtr_token.h" #include "vpr_error.h" -#include "vpr_types.h" -#include "arch_types.h" #include "physical_types.h" #include "globals.h" #include "vpr_utils.h" #include "pb_type_graph.h" #include "pb_type_graph_annotations.h" #include "cluster_feasibility_filter.h" -#include "power.h" -#include "read_xml_arch_file.h" /* variable global to this section that indexes each pb graph pin within a cluster */ static vtr::t_linked_vptr* edges_head; @@ -282,7 +277,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node, pb_graph_node->pin_num_range.low = pin_count_in_cluster; for (i = 0; i < pb_type->num_ports; i++) { if (pb_type->ports[i].model_port) { - VTR_ASSERT(pb_type->num_modes == 0); + VTR_ASSERT(pb_type->is_primitive()); } else { VTR_ASSERT(pb_type->num_modes != 0 || pb_type->ports[i].is_clock); } @@ -295,7 +290,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node, pb_graph_node->input_pins[i_input][j].parent_node = pb_graph_node; pb_graph_node->input_pins[i_input][j].pin_count_in_cluster = pin_count_in_cluster; if (pb_graph_node->pb_type->blif_model != nullptr) { - if (strcmp(pb_graph_node->pb_type->blif_model, MODEL_OUTPUT) == 0) { + if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_OUTPUT) == 0) { pb_graph_node->input_pins[i_input][j].type = PB_PIN_OUTPAD; } else if (pb_graph_node->num_clock_ports != 0) { pb_graph_node->input_pins[i_input][j].type = PB_PIN_SEQUENTIAL; @@ -315,7 +310,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node, pb_graph_node->output_pins[i_output][j].parent_node = pb_graph_node; pb_graph_node->output_pins[i_output][j].pin_count_in_cluster = pin_count_in_cluster; if (pb_graph_node->pb_type->blif_model != nullptr) { - if (strcmp(pb_graph_node->pb_type->blif_model, MODEL_INPUT) == 0) { + if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT) == 0) { pb_graph_node->output_pins[i_output][j].type = PB_PIN_INPAD; } else if (pb_graph_node->num_clock_ports != 0) { pb_graph_node->output_pins[i_output][j].type = PB_PIN_SEQUENTIAL; @@ -1646,7 +1641,7 @@ static void echo_pb_rec(const t_pb_graph_node* pb_graph_node, const int level, F } fprintf(fp, "\n"); - if (pb_graph_node->pb_type->num_modes > 0) { + if (!pb_graph_node->pb_type->is_primitive()) { print_tabs(fp, level); fprintf(fp, "Children:\n"); } diff --git a/vpr/src/pack/pb_type_graph.h b/vpr/src/pack/pb_type_graph.h index f2d8cdeb5d9..cda5bdf1696 100644 --- a/vpr/src/pack/pb_type_graph.h +++ b/vpr/src/pack/pb_type_graph.h @@ -1,6 +1,8 @@ #ifndef PB_TYPE_GRAPH_H #define PB_TYPE_GRAPH_H +#include "physical_types.h" + struct t_pb_graph_edge_comparator { int input_pin_id_in_cluster; int output_pin_id_in_cluster; diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index 63a60188f20..e0988af7143 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -2,24 +2,20 @@ * April 15, 2011 * Loads statistical information (min/max delays, power) onto the pb_graph. */ +#include #include #include #include +#include "arch_util.h" #include "vtr_assert.h" #include "vtr_util.h" -#include "vtr_memory.h" #include "vtr_token.h" -#include "vpr_types.h" #include "vpr_error.h" -#include "arch_types.h" -#include "globals.h" -#include "vpr_utils.h" #include "pb_type_graph.h" #include "pb_type_graph_annotations.h" -#include "read_xml_arch_file.h" static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const char* value); @@ -47,7 +43,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { pb_type = pb_graph_node->pb_type; /* Load primitive critical path delays */ - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { annotations = pb_type->annotations; for (i = 0; i < pb_type->num_annotations; i++) { if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) { diff --git a/vpr/src/pack/pb_type_graph_annotations.h b/vpr/src/pack/pb_type_graph_annotations.h index 3f93d96fa14..317f63b394c 100644 --- a/vpr/src/pack/pb_type_graph_annotations.h +++ b/vpr/src/pack/pb_type_graph_annotations.h @@ -7,6 +7,8 @@ #ifndef PB_TYPE_GRAPH_ANNOTATIONS_H #define PB_TYPE_GRAPH_ANNOTATIONS_H +class t_pb_graph_node; + void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node); #endif diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.cpp b/vpr/src/pack/post_routing_pb_pin_fixup.cpp index d217f07a83d..eb71dabc48e 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.cpp +++ b/vpr/src/pack/post_routing_pb_pin_fixup.cpp @@ -124,17 +124,17 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li auto pin_type = get_pin_type_from_pin_physical_num(physical_tile, physical_pin); - t_rr_type rr_node_type; + e_rr_type rr_node_type; if (pin_type == DRIVER) { - rr_node_type = OPIN; + rr_node_type = e_rr_type::OPIN; } else { VTR_ASSERT(pin_type == RECEIVER); - rr_node_type = IPIN; + rr_node_type = e_rr_type::IPIN; } std::vector pinloc_sides = find_physical_tile_pin_side(physical_tile, physical_pin); /* As some grid has height/width offset, we may not have the pin on any side */ - if (0 == pinloc_sides.size()) { + if (pinloc_sides.empty()) { continue; } @@ -752,7 +752,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom t_pb_graph_pin* new_sink_pb_pin_to_add = sink_pb_pin_to_add; VTR_ASSERT(is_single_fanout_pb_pin(const_cast(new_sink_pb_pin_to_add))); int new_driver_pb_pin = pb_graph_pin->pin_count_in_cluster; - while (1) { + while (true) { int new_sink_pb_route_id = new_sink_pb_pin_to_add->pin_count_in_cluster; new_pb_routes.insert(std::make_pair(new_sink_pb_route_id, t_pb_route())); new_pb_routes[new_sink_pb_route_id].atom_net_id = remapped_net; @@ -1033,6 +1033,7 @@ void sync_netlists_to_routing(const Netlist<>& net_list, /* Create net-to-rr_node mapping */ vtr::vector rr_node_nets = annotate_rr_node_nets(clustering_ctx, device_ctx, + atom_ctx, verbose); IntraLbPbPinLookup intra_lb_pb_pin_lookup(device_ctx.logical_block_types); diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 6f80d5927a5..1f9f1a717bc 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -21,6 +21,7 @@ #include "atom_netlist.h" #include "echo_files.h" +#include "logic_types.h" #include "physical_types.h" #include "vpr_error.h" #include "vpr_types.h" @@ -70,7 +71,8 @@ static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_ static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, const std::multimap& atom_molecules, - const AtomNetlist& atom_nlist); + const AtomNetlist& atom_nlist, + const LogicalModels& models); static void print_pack_molecules(const char* fname, const std::vector& list_of_pack_patterns, @@ -97,7 +99,17 @@ static void find_all_equivalent_chains(t_pack_patterns* chain_pattern, const t_p static void update_chain_root_pins(t_pack_patterns* chain_pattern, const std::vector& chain_input_pins); -static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector& connected_primitive_pins); +/** + * @brief Get all primitive pins connected to the given cluster input pin + * + * @param cluster_input_pin Cluster input pin to get connected primitive pins from + * @param pattern_blocks Set of pb_types in the pack pattern. Pins on the blocks in this set will + * be added to the connected_primitive_pins vector + * @param connected_primitive_pins Vector to store connected primitive pins + */ +static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, + const std::unordered_set& pattern_blocks, + std::vector& connected_primitive_pins); static void init_molecule_chain_info(const AtomBlockId blk_id, t_pack_molecule& molecule, @@ -108,12 +120,21 @@ static void init_molecule_chain_info(const AtomBlockId blk_id, static AtomBlockId get_sink_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, - const AtomNetlist& atom_nlist); + const AtomNetlist& atom_nlist, + const LogicalModels& models); static AtomBlockId get_driving_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, const AtomNetlist& atom_nlist); +/** + * @brief Get an unordered set of all pb_types in the given pack pattern + * + * @param pack_pattern Pack pattern to get pb_types from + * @return std::unordered_set Set of pb_types in the pack pattern + */ +static std::unordered_set get_pattern_blocks(const t_pack_patterns& pack_pattern); + static void print_chain_starting_points(t_pack_patterns* chain_pattern); /*****************************************/ @@ -723,7 +744,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans // check if this input pin of the expansion edge has no driving pin if (expansion_edge->input_pins[i]->num_input_edges == 0) { // check if this input pin of the expansion edge belongs to a root block (i.e doesn't have a parent block) - if (expansion_edge->input_pins[i]->parent_node->pb_type->parent_mode == nullptr) { + if (expansion_edge->input_pins[i]->parent_node->pb_type->is_root()) { // This pack pattern extends to CLB (root pb block) input pin, // thus it extends across multiple logic blocks, treat as a chain packing_pattern.is_chain = true; @@ -775,6 +796,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans */ void Prepacker::alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, const AtomNetlist& atom_nlist, + const LogicalModels& models, const std::vector& logical_block_types) { std::vector is_used(list_of_pack_patterns.size(), false); @@ -811,7 +833,8 @@ void Prepacker::alloc_and_load_pack_molecules(std::multimapname); + models.get_model(atom_nlist.block_model(blk_id)).name); } VTR_ASSERT_SAFE(nullptr != best); @@ -920,7 +943,8 @@ static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_ PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, AtomBlockId blk_id, std::multimap& atom_molecules_multimap, - const AtomNetlist& atom_nlist) { + const AtomNetlist& atom_nlist, + const LogicalModels& models) { auto pack_pattern = &list_of_pack_patterns[pack_pattern_index]; // Check pack pattern validity @@ -944,7 +968,7 @@ PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, molecule.root = pack_pattern->root_block->block_id; molecule.chain_id = MoleculeChainId::INVALID(); - if (!try_expand_molecule(molecule, blk_id, atom_molecules_multimap, atom_nlist)) { + if (!try_expand_molecule(molecule, blk_id, atom_molecules_multimap, atom_nlist, models)) { // Failed to create molecule return PackMoleculeId::INVALID(); } @@ -988,7 +1012,8 @@ PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, const std::multimap& atom_molecules, - const AtomNetlist& atom_nlist) { + const AtomNetlist& atom_nlist, + const LogicalModels& models) { // root block of the pack pattern, which is the starting point of this pattern const auto pattern_root_block = molecule.pack_pattern->root_block; // bool array indicating whether a position in a pack pattern is optional or should @@ -1045,7 +1070,7 @@ static bool try_expand_molecule(t_pack_molecule& molecule, // this block is the driver of this connection if (block_connection->from_block == pattern_block) { // find the block this connection is driving and add it to the queue - auto sink_blk_id = get_sink_block(block_id, *block_connection, atom_nlist); + auto sink_blk_id = get_sink_block(block_id, *block_connection, atom_nlist, models); // add this sink block id with its corresponding pattern block to the queue pattern_block_queue.push(std::make_pair(block_connection->to_block, sink_blk_id)); // this block is being driven by this connection @@ -1077,7 +1102,8 @@ static bool try_expand_molecule(t_pack_molecule& molecule, */ static AtomBlockId get_sink_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, - const AtomNetlist& atom_nlist) { + const AtomNetlist& atom_nlist, + const LogicalModels& models) { const t_model_ports* from_port_model = connections.from_pin->port->model_port; const int from_pin_number = connections.from_pin->pin_number; auto from_port_id = atom_nlist.find_atom_port(block_id, from_port_model); @@ -1099,10 +1125,11 @@ static AtomBlockId get_sink_block(const AtomBlockId block_id, // Iterate through all sink blocks and check whether any of them // is compatible with the block specified in the pack pattern. bool connected_to_latch = false; + LogicalModelId latch_model_id = models.get_model_by_name(LogicalModels::MODEL_LATCH); AtomBlockId pattern_sink_block_id = AtomBlockId::INVALID(); for (const auto& sink_pin_id : net_sinks) { auto sink_block_id = atom_nlist.pin_block(sink_pin_id); - if (atom_nlist.block_model(sink_block_id)->name == std::string(MODEL_LATCH)) { + if (atom_nlist.block_model(sink_block_id) == latch_model_id) { connected_to_latch = true; } if (primitive_type_feasible(sink_block_id, to_pb_type)) { @@ -1163,6 +1190,51 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, return AtomBlockId::INVALID(); } +static std::unordered_set get_pattern_blocks(const t_pack_patterns& pack_pattern) { + std::unordered_set pattern_blocks; + + t_pack_pattern_connections* connections = pack_pattern.root_block->connections; + if (connections == nullptr) { + return pattern_blocks; + } + std::unordered_set visited_from_pins; + std::unordered_set visited_to_pins; + std::queue pack_pattern_blocks; + pack_pattern_blocks.push(connections->from_block); + + /** Start from the root block of the pack pattern and add the connected block to the queue */ + while (!pack_pattern_blocks.empty()) { + t_pack_pattern_block* current_pattern_block = pack_pattern_blocks.front(); + pack_pattern_blocks.pop(); + t_pack_pattern_connections* current_connenction = current_pattern_block->connections; + /* + * Iterate through all the connections of the current pattern block to + * add the connected block to the queue + */ + while (current_connenction != nullptr) { + if (visited_from_pins.find(current_connenction->from_pin) != visited_from_pins.end()) { + if (visited_to_pins.find(current_connenction->to_pin) != visited_to_pins.end()) { + /* We've already seen this connection */ + current_connenction = current_connenction->next; + continue; + } + } + /* + * To avoid visiting the same connection twice, since it is both stored in from_pin and to_pin, + * add the from_pin and to_pin to the visited sets + */ + visited_from_pins.insert(current_connenction->from_pin); + visited_to_pins.insert(current_connenction->to_pin); + + /* The from_pin block belongs to the pattern block */ + pattern_blocks.insert(current_connenction->from_pin->port->parent_pb_type); + pack_pattern_blocks.push(current_connenction->to_block); + current_connenction = current_connenction->next; + } + } + return pattern_blocks; +} + static void print_pack_molecules(const char* fname, const std::vector& list_of_pack_patterns, const int num_pack_patterns, @@ -1555,9 +1627,10 @@ static void update_chain_root_pins(t_pack_patterns* chain_pattern, const std::vector& chain_input_pins) { std::vector> primitive_input_pins; + std::unordered_set pattern_blocks = get_pattern_blocks(*chain_pattern); for (const auto pin_ptr : chain_input_pins) { std::vector connected_primitive_pins; - get_all_connected_primitive_pins(pin_ptr, connected_primitive_pins); + get_all_connected_primitive_pins(pin_ptr, pattern_blocks, connected_primitive_pins); /** * It is required that the chain pins are connected inside a complex @@ -1581,7 +1654,9 @@ static void update_chain_root_pins(t_pack_patterns* chain_pattern, * the Cin pin of all the adder primitives connected to this pin. Which is for typical architectures * will be only one pin connected to the very first adder in the cluster. */ -static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector& connected_primitive_pins) { +static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, + const std::unordered_set& pattern_blocks, + std::vector& connected_primitive_pins) { /* Skip pins for modes that are disabled for packing*/ if ((nullptr != cluster_input_pin->parent_node->pb_type->parent_mode) && (true == cluster_input_pin->parent_node->pb_type->parent_mode->disable_packing)) { @@ -1592,9 +1667,12 @@ static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input const auto& output_edge = cluster_input_pin->output_edges[iedge]; for (int ipin = 0; ipin < output_edge->num_output_pins; ipin++) { if (output_edge->output_pins[ipin]->is_primitive_pin()) { - connected_primitive_pins.push_back(output_edge->output_pins[ipin]); + /** Add the output pin to the vector only if it belongs to a pb_type registered in the pattern_blocks set */ + if (pattern_blocks.find(output_edge->output_pins[ipin]->parent_node->pb_type) != pattern_blocks.end()) { + connected_primitive_pins.push_back(output_edge->output_pins[ipin]); + } } else { - get_all_connected_primitive_pins(output_edge->output_pins[ipin], connected_primitive_pins); + get_all_connected_primitive_pins(output_edge->output_pins[ipin], pattern_blocks, connected_primitive_pins); } } } @@ -1680,6 +1758,7 @@ static void print_chain_starting_points(t_pack_patterns* chain_pattern) { } Prepacker::Prepacker(const AtomNetlist& atom_nlist, + const LogicalModels& models, const std::vector& logical_block_types) { vtr::ScopedStartFinishTimer prepacker_timer("Prepacker"); @@ -1690,6 +1769,7 @@ Prepacker::Prepacker(const AtomNetlist& atom_nlist, expected_lowest_cost_pb_gnode.resize(atom_nlist.blocks().size(), nullptr); alloc_and_load_pack_molecules(atom_molecules_multimap, atom_nlist, + models, logical_block_types); // The multimap is a legacy thing. Since blocks can be part of multiple pack @@ -1709,7 +1789,8 @@ Prepacker::Prepacker(const AtomNetlist& atom_nlist, // this information and store it in the prepacker class. This may be // expensive to calculate for large molecules. t_molecule_stats Prepacker::calc_molecule_stats(PackMoleculeId molecule_id, - const AtomNetlist& atom_nlist) const { + const AtomNetlist& atom_nlist, + const LogicalModels& models) const { VTR_ASSERT(molecule_id.is_valid()); t_molecule_stats molecule_stats; @@ -1721,13 +1802,14 @@ t_molecule_stats Prepacker::calc_molecule_stats(PackMoleculeId molecule_id, ++molecule_stats.num_blocks; //Record number of valid blocks in molecule - const t_model* model = atom_nlist.block_model(blk); + LogicalModelId model_id = atom_nlist.block_model(blk); + const t_model& model = models.get_model(model_id); - for (const t_model_ports* input_port = model->inputs; input_port != nullptr; input_port = input_port->next) { + for (const t_model_ports* input_port = model.inputs; input_port != nullptr; input_port = input_port->next) { molecule_stats.num_input_pins += input_port->size; } - for (const t_model_ports* output_port = model->outputs; output_port != nullptr; output_port = output_port->next) { + for (const t_model_ports* output_port = model.outputs; output_port != nullptr; output_port = output_port->next) { molecule_stats.num_output_pins += output_port->size; } } @@ -1780,11 +1862,11 @@ t_molecule_stats Prepacker::calc_molecule_stats(PackMoleculeId molecule_id, return molecule_stats; } -t_molecule_stats Prepacker::calc_max_molecule_stats(const AtomNetlist& atom_nlist) const { +t_molecule_stats Prepacker::calc_max_molecule_stats(const AtomNetlist& atom_nlist, const LogicalModels& models) const { t_molecule_stats max_molecules_stats; for (PackMoleculeId molecule_id : molecules()) { //Calculate per-molecule statistics - t_molecule_stats cur_molecule_stats = calc_molecule_stats(molecule_id, atom_nlist); + t_molecule_stats cur_molecule_stats = calc_molecule_stats(molecule_id, atom_nlist, models); //Record the maximums (member-wise) over all molecules max_molecules_stats.num_blocks = std::max(max_molecules_stats.num_blocks, cur_molecule_stats.num_blocks); diff --git a/vpr/src/pack/prepack.h b/vpr/src/pack/prepack.h index 5222046ddb6..08c960f3105 100644 --- a/vpr/src/pack/prepack.h +++ b/vpr/src/pack/prepack.h @@ -20,6 +20,7 @@ // Forward declarations class t_pack_molecule; +class LogicalModels; struct t_logical_block_type; // A unique ID used to identify a molecule generated by the prepacker. @@ -192,9 +193,11 @@ class Prepacker { * necessary data strucutres. * * @param atom_nlist The atom netlist to prepack. + * @param models * @param logical_block_types A list of the logical block types on the device. */ Prepacker(const AtomNetlist& atom_nlist, + const LogicalModels& models, const std::vector& logical_block_types); /** @@ -236,12 +239,14 @@ class Prepacker { * @brief Calculates molecule statistics for a single molecule. */ t_molecule_stats calc_molecule_stats(PackMoleculeId molecule_id, - const AtomNetlist& atom_netlist) const; + const AtomNetlist& atom_netlist, + const LogicalModels& models) const; /** * @brief Calculates maximum molecule statistics accross all molecules, */ - t_molecule_stats calc_max_molecule_stats(const AtomNetlist& netlist) const; + t_molecule_stats calc_max_molecule_stats(const AtomNetlist& netlist, + const LogicalModels& models) const; /** * @brief Gets the largest number of blocks (atoms) that any molecule contains. @@ -303,6 +308,7 @@ class Prepacker { */ void alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, const AtomNetlist& atom_nlist, + const LogicalModels& models, const std::vector& logical_block_types); /** @@ -321,7 +327,8 @@ class Prepacker { PackMoleculeId try_create_molecule(const int pack_pattern_index, AtomBlockId blk_id, std::multimap& atom_molecules_multimap, - const AtomNetlist& atom_nlist); + const AtomNetlist& atom_nlist, + const LogicalModels& models); private: /** diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 0e6be438300..1e1a6830492 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -42,23 +42,6 @@ static void fixup_atom_pb_graph_pin_mapping(void); /* Function definitions */ -/** Is the clock net found in the routing results? - * (If not, clock_modeling is probably ideal and we should preserve clock routing while rebuilding.) */ -inline bool is_clock_net_routed(void) { - auto& atom_ctx = g_vpr_ctx.atom(); - auto& route_ctx = g_vpr_ctx.routing(); - - for (auto net_id : atom_ctx.netlist().nets()) { - auto& tree = route_ctx.route_trees[net_id]; - if (!tree) - continue; - if (route_ctx.is_clock_net[net_id]) /* Clock net has routing */ - return true; - } - - return false; -} - /** Get the ClusterBlockId for a given RRNodeId. */ inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode) { auto& device_ctx = g_vpr_ctx.device(); @@ -100,7 +83,7 @@ static void get_intra_cluster_connections(const RouteTree& tree, std::vectorinode); - if ((type == IPIN || type == OPIN) && (parent_type == IPIN || parent_type == OPIN)) { + if ((type == e_rr_type::IPIN || type == e_rr_type::OPIN) && (parent_type == e_rr_type::IPIN || parent_type == e_rr_type::OPIN)) { auto clb = get_cluster_block_from_rr_node(node.inode); auto parent_clb = get_cluster_block_from_rr_node(parent->inode); if (clb == parent_clb) @@ -185,18 +168,22 @@ static void sync_pb_routes_to_routing(void) { auto& route_ctx = g_vpr_ctx.routing(); auto& rr_graph = device_ctx.rr_graph; - /* Was the clock net routed? */ - bool clock_net_is_routed = is_clock_net_routed(); - /* Clear out existing pb_routes: they were made by the intra cluster router and are invalid now */ for (ClusterBlockId clb_blk_id : cluster_ctx.clb_nlist.blocks()) { - /* If we don't have routing for the clock net, don't erase entries associated with a clock net. - * Otherwise we won't have data to rebuild them */ + /* Don't erase entries for nets without routing in place (clocks, globals...) */ std::vector pins_to_erase; - auto& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; + t_pb_routes& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; for (auto& [pin, pb_route] : pb_routes) { - if (clock_net_is_routed || !route_ctx.is_clock_net[pb_route.atom_net_id]) - pins_to_erase.push_back(pin); + /* + * Given that this function is called when flat routing is enabled, + * we can safely assume that the net IDs to index into route_ctx.route_trees + * correspond to the atom net IDs. + */ + if (!route_ctx.route_trees[pb_route.atom_net_id]) { + /* No route tree: no routing in place, it is global or clock */ + continue; + } + pins_to_erase.push_back(pin); } for (int pin : pins_to_erase) { @@ -276,37 +263,37 @@ static void sync_clustered_netlist_to_routing(void) { auto& atom_ctx = g_vpr_ctx.mutable_atom(); auto& atom_lookup = atom_ctx.lookup(); - bool clock_net_is_routed = is_clock_net_routed(); - /* 1. Remove all nets, pins and ports from the clustered netlist. - * If the clock net is not routed, don't remove entries for the clock net - * otherwise we won't have data to rebuild them. */ + * Do not remove entries for nets without an existing route tree, + * since we don't have the information to rebuild those parts. */ std::vector nets_to_remove; std::vector pins_to_remove; std::vector ports_to_remove; for (auto net_id : clb_netlist.nets()) { auto atom_net_id = atom_lookup.atom_net(net_id); - if (!clock_net_is_routed && route_ctx.is_clock_net[atom_net_id]) + if (!route_ctx.route_trees[atom_net_id]) continue; nets_to_remove.push_back(net_id); } - for (auto pin_id : clb_netlist.pins()) { - ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); - auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if (!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) - continue; - - pins_to_remove.push_back(pin_id); - } + /* Mark ports and pins for removal. Don't remove a port if + * it has at least one pin remaining */ for (auto port_id : clb_netlist.ports()) { - ClusterNetId clb_net_id = clb_netlist.port_net(port_id, 0); - auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if (!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) - continue; + size_t skipped_pins = 0; + + for (auto pin_id : clb_netlist.port_pins(port_id)) { + ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); + auto atom_net_id = atom_lookup.atom_net(clb_net_id); + if (atom_net_id && !route_ctx.route_trees[atom_net_id]) { + skipped_pins++; + } else { + pins_to_remove.push_back(pin_id); + } + } - ports_to_remove.push_back(port_id); + if (!skipped_pins) // All pins have been removed, remove port + ports_to_remove.push_back(port_id); } /* ClusteredNetlist's iterators rely on internal lookups, so we mark for removal @@ -336,7 +323,7 @@ static void sync_clustered_netlist_to_routing(void) { int clb_nets_so_far = 0; for (auto& rt_node : tree->all_nodes()) { auto node_type = rr_graph.node_type(rt_node.inode); - if (node_type != IPIN && node_type != OPIN) + if (node_type != e_rr_type::IPIN && node_type != e_rr_type::OPIN) continue; auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rt_node.inode), @@ -353,7 +340,7 @@ static void sync_clustered_netlist_to_routing(void) { /* OPIN on the tile: create a new clb_net_id and add all ports & pins into here * Due to how the route tree is traversed, all nodes until the next OPIN on the tile will * be under this OPIN, so this is valid (we don't need to get the branch explicitly) */ - if (node_type == OPIN) { + if (node_type == e_rr_type::OPIN) { std::string net_name; net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); clb_net_id = clb_netlist.create_net(net_name); @@ -363,6 +350,7 @@ static void sync_clustered_netlist_to_routing(void) { t_pb_graph_pin* pb_graph_pin = get_pb_graph_node_pin_from_block_pin(clb, pin_index); + /* Get or create port */ ClusterPortId port_id = clb_netlist.find_port(clb, pb_graph_pin->port->name); if (!port_id) { PortType port_type; @@ -376,8 +364,17 @@ static void sync_clustered_netlist_to_routing(void) { VTR_ASSERT_MSG(false, "Unsupported port type"); port_id = clb_netlist.create_port(clb, pb_graph_pin->port->name, pb_graph_pin->port->num_pins, port_type); } - PinType pin_type = node_type == OPIN ? PinType::DRIVER : PinType::SINK; - + PinType pin_type = node_type == e_rr_type::OPIN ? PinType::DRIVER : PinType::SINK; + + /* Pin already exists. This means a global net that was not routed (i.e. 'ideal' mode). */ + if (clb_netlist.port_pin(port_id, pb_graph_pin->pin_number)) { + VTR_LOG_WARN("Pin %s of block %s has a global or clock net" + " connected and it has a routing clash with the flat router." + " This may cause inconsistent results.\n", + pb_graph_pin->to_string().c_str(), + clb_netlist.block_name(clb).c_str()); + continue; + } ClusterPinId new_pin = clb_netlist.create_pin(port_id, pb_graph_pin->pin_number, clb_net_id, pin_type, pb_graph_pin->pin_count_in_cluster); clb_netlist.set_pin_net(new_pin, pin_type, clb_net_id); } @@ -419,6 +416,12 @@ static void fixup_atom_pb_graph_pin_mapping(void) { /* Find atom port from pbg pin's model port */ AtomPortId atom_port = atom_ctx.netlist().find_atom_port(atb, atom_pbg_pin->port->model_port); + + /* Not an equivalent port, so no need to do fixup */ + if (atom_pbg_pin->port->equivalent != PortEquivalence::FULL) { + continue; + } + for (AtomPinId atom_pin : atom_ctx.netlist().port_pins(atom_port)) { /* Match net IDs from pb_route and atom netlist and connect in lookup */ if (pb_route.atom_net_id == atom_ctx.netlist().pin_net(atom_pin)) { diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.h b/vpr/src/pack/sync_netlists_to_routing_flat.h index 0c1bc7d77d3..ef6b743fe30 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.h +++ b/vpr/src/pack/sync_netlists_to_routing_flat.h @@ -1,5 +1,3 @@ -#include "netlist.h" - /******************************************************************** * Top-level function to synchronize packing results to routing results. * Flat routing invalidates the ClusteredNetlist since nets may be routed diff --git a/vpr/src/pack/verify_flat_placement.cpp b/vpr/src/pack/verify_flat_placement.cpp index 76a893d66a6..59bb36bbbf8 100644 --- a/vpr/src/pack/verify_flat_placement.cpp +++ b/vpr/src/pack/verify_flat_placement.cpp @@ -4,7 +4,6 @@ #include "atom_netlist.h" #include "atom_netlist_fwd.h" #include "prepack.h" -#include "vpr_types.h" #include "vtr_log.h" unsigned verify_flat_placement_for_packing(const FlatPlacementInfo& flat_placement_info, diff --git a/vpr/src/place/analytic_placer.cpp b/vpr/src/place/analytic_placer.cpp deleted file mode 100644 index a0897af6785..00000000000 --- a/vpr/src/place/analytic_placer.cpp +++ /dev/null @@ -1,865 +0,0 @@ -#include "place_macro.h" -#ifdef ENABLE_ANALYTIC_PLACE - -#include "analytic_placer.h" - -// The eigen library contains a warning in GCC13 for a null dereference. This -// causes the CI build to fail due to the warning. Ignoring the warning for -// these include files. Using push to return to the state of GCC diagnostics. -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wnull-dereference" -#include -#include -// Pop the GCC diagnostics state back to what it was before. -#pragma GCC diagnostic pop - -#include -#include -#include - -#include "vpr_types.h" -#include "vtr_time.h" -#include "read_place.h" -#include "globals.h" -#include "vtr_log.h" -#include "cut_spreader.h" -#include "vpr_utils.h" -#include "place_util.h" - -// Templated struct for constructing and solving matrix equations in analytic placer -template -struct EquationSystem { - EquationSystem(size_t rows, size_t cols) { - A.resize(cols); - rhs.resize(rows); - } - - // A[col] is an entire column of the sparse matrix - // each entry in A[col][index] is a pair with {row_number, matrix value}. - // - // The strategy of skipping 0 row entries in each column enables easy conversion to - // Compressed Column Storage scheme supported by Eigen to reduce memory consumption - // and increase performance - std::vector>> A; - // right hand side vector, i.e. b in Ax = b - std::vector rhs; - - // System of equation is reset by: - // Clearing all entries in A's column, but size of A (number of columns) is preserved - // right hand side vector is set to default value of its templated type - void reset() { - for (auto& col : A) - col.clear(); - std::fill(rhs.begin(), rhs.end(), T()); - } - - // Add val to the matrix entry at (row, col) - // create entry if it doesn't exist - void add_coeff(int row, int col, T val) { - auto& A_col = A.at(col); - // Binary search for the row entry in column col - int begin_i = 0, end_i = int(A_col.size()) - 1; - while (begin_i <= end_i) { - int i = (begin_i + end_i) / 2; - if (A_col.at(i).first == row) { - A_col.at(i).second += val; - return; - } - if (A_col.at(i).first > row) - end_i = i - 1; - else - begin_i = i + 1; - } - A_col.insert(A_col.begin() + begin_i, std::make_pair(row, val)); - } - - // Add val to the "row"-th entry of right hand side vector - void add_rhs(int row, T val) { rhs[row] += val; } - - // Solving Ax = b, using current x as an initial guess, returns x by reference. - // (x must be of correct size, A and rhs must have their entries filled in) - // tolerance is residual error from solver: |Ax-b|/|b|, 1e-5 works well, - // can be tuned in ap_cfg in AnalyticPlacer constructor - void solve(std::vector& x, float tolerance) { - using namespace Eigen; - - VTR_ASSERT(x.size() == A.size()); - - // Converting A into SparseMatrix format from Eigen - VectorXd vec_x_guess(x.size()), vec_rhs(rhs.size()); - SparseMatrix mat(A.size(), A.size()); - - std::vector colnnz; // vector containing number of entries in each column - for (auto& A_col : A) - colnnz.push_back(int(A_col.size())); - mat.reserve(colnnz); // reserve memory for mat depending on number of entries in each row - for (int col = 0; col < int(A.size()); col++) { - auto& A_col = A.at(col); - for (auto& row_entry : A_col) - mat.insert(row_entry.first, col) = row_entry.second; - } - - // use current value of x as guess for iterative solver - for (int i_row = 0; i_row < int(x.size()); i_row++) - vec_x_guess[i_row] = x.at(i_row); - - for (int i_row = 0; i_row < int(rhs.size()); i_row++) - vec_rhs[i_row] = rhs.at(i_row); - - ConjugateGradient, Lower | Upper> solver; - solver.setTolerance(tolerance); - VectorXd x_res = solver.compute(mat).solveWithGuess(vec_rhs, vec_x_guess); - for (int i_row = 0; i_row < int(x.size()); i_row++) - x.at(i_row) = x_res[i_row]; - } -}; - -// Stop optimizing once this many iterations of solve-legalize lead to negligible wirelength improvement -constexpr int HEAP_STALLED_ITERATIONS_STOP = 15; - -/* - * AnalyticPlacer constructor - * Currently only initializing AP configuration parameters - * Placement & device info is accessed via g_vpr_ctx - */ - -AnalyticPlacer::AnalyticPlacer(BlkLocRegistry& blk_loc_registry, - const PlaceMacros& place_macros) - : blk_loc_registry_ref_(blk_loc_registry) - , place_macros_(place_macros) { - //Eigen::initParallel(); - - // TODO: PlacerHeapCfg should be externally configured & supplied - // TODO: tune these parameters for better performance - ap_cfg.alpha = 0.1; // anchoring strength, after first AP iteration the legal position of each block - // becomes anchors. In the next AP iteration, pseudo-connection between each blocks - // current location and its anchor is formed with strength (alph * iter) - // @see build_equations() - - ap_cfg.beta = 1; // utilization factor, <= 1, used to determine if a cut-spreading region is - // overutilized with the formula: bool overutilized = (num_blks / num_tiles) > beta - // for beta < 1, a region must have more tiles than logical blks to not be overutilized - - ap_cfg.solverTolerance = 1e-5; // solver parameter, refers to residual error from solver, defined as |Ax-b|/|b| - - ap_cfg.buildSolveIter = 5; // number of build-solve iteration when calculating placement, used in - // build_solve_direction() - // for each build-solve iteration, the solution from previous build-solve iteration - // is used as a guess for the iterative solver. therefore more buildSolveIter should - // should improve result at the expense of runtime - - // following two parameters are used in CutSpreader::expand_regions(). - // they determine the number of steps to expand in x or y direction before switching to expand in the other direction. - ap_cfg.spread_scale_x = 1; - ap_cfg.spread_scale_y = 1; - - // following two timing parameters are used to add timing weights in matrix equation, currently not used - // see comment in add_pin_to_pin_connection() for usage - ap_cfg.criticalityExponent = 1; - ap_cfg.timingWeight = 10; -} - -/* - * Main function of analytic placement - * Takes the random initial placement from place.cpp through g_vpr_ctx - * Repeat the following until stopping criteria is met: - * * Formulate and solve equations in x & y directions for 1 type of logical block - * * Instantiate CutSpreader to spread and strict_legalize - * - * The final legal placement is passed back to annealer in g_vpr_ctx.mutable_placement() - */ -void AnalyticPlacer::ap_place() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - vtr::ScopedStartFinishTimer timer("Analytic Placement"); - - init(); // transfer placement from g_vpr_ctx to AnalyticPlacer data members - build_legal_locations(); - int hpwl = total_hpwl(); - VTR_LOG("Creating analytic placement for %d cells, random placement hpwl = %d.\n", - int(clb_nlist.blocks().size()), int(hpwl)); - - // the order in which different logical block types are placed; - // going through ap_runs once completes 1 iteration of AP - std::vector ap_runs; - std::unordered_set all_blktypes; // set of all logical block types - - // setup ap_runs, run build/solve/legalize once for every block type - // each type is placed separately, but influenced by the current location of other types - for (auto blk : place_blks) { - if (!all_blktypes.count(clb_nlist.block_type(blk))) { - ap_runs.push_back(clb_nlist.block_type(blk)); - all_blktypes.insert(clb_nlist.block_type(blk)); - } - } - - // setup and solve matrix multiple times for all logic block types before main loop - // this helps eliminating randomness from initial placement (when placing one block type, the random placement - // of the other types may have residual effect on the result, since not all blocks are solved at the same time) - for (int i = 0; i < 1; i++) { // can tune number of iterations - for (auto run : ap_runs) { - build_solve_type(run, -1); - } - } - - int iter = 0, stalled = 0; - // variables for stats - int solved_hpwl = 0, spread_hpwl = 0, legal_hpwl = 0, best_hpwl = std::numeric_limits::max(); - float iter_start, iter_t, run_start, run_t, solve_t, spread_start, spread_t, legal_start, legal_t; - - print_AP_status_header(); - - // main loop for AP - // stopping criteria: stop after HEAP_STALLED_ITERATIONS_STOP iterations of no improvement - while (stalled < HEAP_STALLED_ITERATIONS_STOP) { - // TODO: investigate better stopping criteria - iter_start = timer.elapsed_sec(); - for (auto blk_type : ap_runs) { // for each type of logic blocks - run_start = timer.elapsed_sec(); - - // lower bound placement for blk_type - // build and solve matrix equation for blocks of type "blk_type" in both x and y directions - build_solve_type(blk_type, iter); - solve_t = timer.elapsed_sec() - run_start; - solved_hpwl = total_hpwl(); - // lower bound placement complete - - // upper bound placement - // cut-spreading logic blocks of type "blk_type", this will mostly legalize lower bound placement - spread_start = timer.elapsed_sec(); - CutSpreader spreader{this, blk_type}; // Legalizer - if (blk_type->name != "io") { - /* skip cut-spreading for IO blocks; they tend to cluster on 1 edge of the FPGA due to how cut-spreader works - * in HeAP, cut-spreading is invoked only on LUT, DSP, RAM etc. - * here, greedy legalization by spreader.strict_legalize() should be sufficient for IOs - */ - spreader.cutSpread(); - update_macros(); - spread_hpwl = total_hpwl(); - spread_t = timer.elapsed_sec() - spread_start; - } else { - spread_hpwl = -1; - spread_t = 0; - } - - // greedy legalizer for fully legal placement - legal_start = timer.elapsed_sec(); - spreader.strict_legalize(); // greedy legalization snaps blocks to the closest legal location - update_macros(); - legal_t = timer.elapsed_sec() - legal_start; - legal_hpwl = total_hpwl(); - - // upper bound placement complete - - run_t = timer.elapsed_sec() - run_start; - print_run_stats(iter, timer.elapsed_sec(), run_t, blk_type->name.c_str(), solve_blks.size(), solve_t, - spread_t, legal_t, solved_hpwl, spread_hpwl, legal_hpwl); - } - - // TODO: update timing info here after timing weights are implemented in build_equations() - - if (legal_hpwl < best_hpwl) { - best_hpwl = legal_hpwl; - stalled = 0; - } else { - ++stalled; - } - - // update legal locations for all blocks for pseudo-connections in next iteration - for (auto& bl : blk_locs) { - bl.legal_loc = bl.loc; - } - iter_t = timer.elapsed_sec() - iter_start; - print_iter_stats(iter, iter_t, timer.elapsed_sec(), best_hpwl, stalled); - ++iter; - } -} - -// build matrix equations and solve for block type "run" in both x and y directions -// macro member positions are updated after solving -void AnalyticPlacer::build_solve_type(t_logical_block_type_ptr run, int iter) { - setup_solve_blks(run); - // build and solve matrix equation for both x, y - // passing -1 as iter to build_solve_direction() signals build_equation() not to add pseudo-connections - build_solve_direction(false, (iter == 0) ? -1 : iter, ap_cfg.buildSolveIter); - build_solve_direction(true, (iter == 0) ? -1 : iter, ap_cfg.buildSolveIter); - update_macros(); // update macro member locations, since only macro head is solved -} - -// build legal_pos similar to initial_placement.cpp -// Go through the placement grid and saving all legal positions for each type of sub_tile -// (stored in legal_pos). For a type of sub_tile_t found in tile_t, legal_pos[tile_t][sub_tile_t] -// gives a vector containing all positions (t_pl_loc type) for this sub_tile_t. -void AnalyticPlacer::build_legal_locations() { - // invoking same function used in initial_placement.cpp (can ignore function name) - alloc_and_load_legal_placement_locations(legal_pos); -} - -// transfer initial placement from g_vpr_ctx to AnalyticPlacer data members, such as: blk_locs, place_blks -// initialize other data members -void AnalyticPlacer::init() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - auto& init_block_locs = blk_loc_registry_ref_.block_locs(); - - for (auto blk_id : clb_nlist.blocks()) { - blk_locs.insert(blk_id, BlockLocation{}); - blk_locs[blk_id].loc = init_block_locs[blk_id].loc; // transfer of initial placement - row_num.insert(blk_id, DONT_SOLVE); // no blocks are moved by default, until they are setup in setup_solve_blks() - } - - // only blocks with connections are considered - auto has_connections = [&](ClusterBlockId blk_id) { - for (auto pin : clb_nlist.block_pins(blk_id)) { - int logical_pin_index = clb_nlist.pin_logical_index(pin); - if (clb_nlist.block_net(blk_id, logical_pin_index) != ClusterNetId::INVALID()) - return true; - } - return false; - }; - - for (auto blk_id : clb_nlist.blocks()) { - if (!init_block_locs[blk_id].is_fixed && has_connections(blk_id)) - // not fixed and has connections - // matrix equation is formulated based on connections, so requires at least one connection - if (place_macros_.get_imacro_from_iblk(blk_id) == NO_MACRO || place_macros_.macro_head(blk_id) == blk_id) { - // not in macro or head of macro - // for macro, only the head (base) block of the macro is a free variable, the location of other macro - // blocks can be calculated using offset of the head. They are not free variables in the equation system - place_blks.push_back(blk_id); - } - } -} - -// get hpwl of a net, taken from place.cpp get_bb_from_scratch() -// TODO: factor out this function from place.cpp and put into vpr_util -int AnalyticPlacer::get_net_hpwl(ClusterNetId net_id) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - // position is not accurate for tiles spanning multiple grid locations - // need to add pin offset in that case: physical_tile_type(bnum)->pin_width_offset[pnum] - // see place.cpp get_non_updateable_bb(); - // TODO: map net_pin to tile_pin and add pin offset to x, y locations (refer to place.cpp) - ClusterBlockId bnum = clb_nlist.net_driver_block(net_id); - int x = std::max(std::min(blk_locs[bnum].loc.x, max_x - 1), 1); - int y = std::max(std::min(blk_locs[bnum].loc.y, max_y - 1), 1); - - vtr::Rect bb = {x, y, x, y}; - - for (auto pin_id : clb_nlist.net_sinks(net_id)) { - bnum = clb_nlist.pin_block(pin_id); - x = std::max(std::min(blk_locs[bnum].loc.x, max_x - 1), 1); - y = std::max(std::min(blk_locs[bnum].loc.y, max_y - 1), 1); - - bb.expand_bounding_box({x, y, x, y}); - } - - return (bb.ymax() - bb.ymin()) + (bb.xmax() - bb.xmin()); -} - -// get hpwl for all nets -int AnalyticPlacer::total_hpwl() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - int hpwl = 0; - for (auto net_id : clb_nlist.nets()) { - if (!clb_nlist.net_is_ignored(net_id)) { - hpwl += get_net_hpwl(net_id); - } - } - return hpwl; -} - -/* - * Setup the blocks of type blkTypes (ex. clb, io) to be solved. These blocks are put into - * solve_blks vector. Each of them is a free variable in the matrix equation (thus excluding - * macro members, as they are formulated into the equation for the macro's head) - * A row number is assigned to each of these blocks, which corresponds to its equation in - * the matrix (the equation acquired from differentiating the objective function w.r.t its - * x or y location). - */ -void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - int row = 0; - solve_blks.clear(); - // clear row_num of all cells, so no blocks are solved - for (auto& blk : row_num) { - blk = DONT_SOLVE; - } - // update blks to be solved/placed, excluding macro members (macro head included) - for (auto blk_id : place_blks) { // find blocks of type blkTypes in place_blks - if (blkTypes == (clb_nlist.block_type(blk_id))) { - row_num[blk_id] = row++; - solve_blks.push_back(blk_id); - } - } - // update row_num of macro members - for (auto& macro : place_macros_.macros()) { - for (auto& member : macro.members) { - row_num[member.blk_index] = row_num[place_macros_.macro_head(member.blk_index)]; - } - } -} - -/* - * Update the location of all members of all macros based on location of macro_head - * since only macro_head is solved (connections to macro members are also taken into account - * when formulating the matrix equations), an update for members is necessary - */ -void AnalyticPlacer::update_macros() { - for (auto& macro : place_macros_.macros()) { - ClusterBlockId head_id = macro.members[0].blk_index; - bool mac_can_be_placed = macro_can_be_placed(macro, blk_locs[head_id].loc, true, blk_loc_registry_ref_); - - //if macro can not be placed in this head pos, change the head pos - if (!mac_can_be_placed) { - size_t macro_size = macro.members.size(); - blk_locs[head_id].loc -= macro.members[macro_size - 1].offset; - } - - //macro should be placed successfully after changing the head position - VTR_ASSERT(macro_can_be_placed(macro, blk_locs[head_id].loc, true, blk_loc_registry_ref_)); - - //update other member's location based on head pos - for (auto member = ++macro.members.begin(); member != macro.members.end(); ++member) { - blk_locs[member->blk_index].loc = blk_locs[head_id].loc + member->offset; - } - } -} - -/* - * Build and solve in one direction - * Solved solutions are written back to block_locs[blk].rawx/rawy for double float raw solution, - * rounded int solutions are written back to block_locs[blk].loc, for each blk in solve_blks - * - * yaxis chooses x or y location of each block from blk_locs to formulate the matrix equation. - * true for y-directed, false for x-directed - * - * iter is the number of AnalyticPlacement iterations (solving and legalizing all types of logic - * blocks once). When iter != -1, at least one iteration has completed. It signals build_equations() - * to create pseudo-connections between each block and its prior legal position. - * - * build_solve_iter determines number of iterations of building and solving for the iterative solver, - * the solution from the previous build-solve iteration is used as a guess for the iterative solver. - * More build_solve_iter means better result, with runtime tradeoff. This parameter can be - * tuned for better performance. - */ -void AnalyticPlacer::build_solve_direction(bool yaxis, int iter, int build_solve_iter) { - for (int i = 0; i < build_solve_iter; i++) { - EquationSystem esx(solve_blks.size(), solve_blks.size()); - build_equations(esx, yaxis, iter); - solve_equations(esx, yaxis); - } -} - -/* - * stamp 1 weight for a connection on matrix or rhs vector. - * - * Block "eqn" specifies which equation (row in matrix system) the weight is added into. - * let eqn have row_num i, var have row_num j (which is also the column in eqn that corresponds to var). - * - * if eqn is not movable, return (eqn doesn't really have an equation as it's not a free variable) - * if var is movable, weight is added in matrix [j][i] - * if var is not movable, (var_pos * weight) is added in rhs vector[j] - * if var is a macro member, weight is added in matrix [j][i], and (-offset_from_head_block * weight) is added to rhs vector[j] - * - * for detailed derivation see comment for add_pin_to_pin_connection() - */ -void AnalyticPlacer::stamp_weight_on_matrix(EquationSystem& es, - bool dir, - ClusterBlockId var, - ClusterBlockId eqn, - double weight) { - // Return the x or y position of a block - auto blk_p = [&](ClusterBlockId blk_id) { return dir ? blk_locs[blk_id].loc.y : blk_locs[blk_id].loc.x; }; - - int eqn_row = row_num[eqn]; - if (eqn_row == DONT_SOLVE) // if eqn is not of the right type or is locked down - return; - int v_pos = blk_p(var); - int var_row = row_num[var]; - if (var_row != DONT_SOLVE) { // var is movable, stamp weight on matrix - es.add_coeff(eqn_row, var_row, weight); - } else { // var is not movable, stamp weight on rhs vector - es.add_rhs(eqn_row, -v_pos * weight); - } - if (place_macros_.get_imacro_from_iblk(var) != NO_MACRO) { // var is part of a macro, stamp on rhs vector - auto& members = place_macros_[place_macros_.get_imacro_from_iblk(var)].members; - for (auto& member : members) { // go through macro members to find the right member block - if (member.blk_index == var) - es.add_rhs(eqn_row, -(dir ? member.offset.y : member.offset.x) * weight); - } - } -} - -/* - * Add weights to matrix for the pin-to-pin connection between bound_blk and this_blk (bound2bound model) - * - * The matrix A in system of equation Ax=b is a symmetric sparse matrix. - * Each row of A corresponds to an equation for a free variable. This equation is acquired by differentiating - * the objective function with respect to the free variable (movable block's x or y location) and setting it - * to 0. - * - * Pin-to-pin connection between 2 movable blocks (call them b1 and b2, with connection weight W12) is the - * simplest case. Differentiating with respect to b1 and setting to 0 produces W12 * b1 - W12 * b2 = 0, where - * b1, b2 are the location variables to calculate. When cast into matrix form, the row number of this equation - * corresponds to b1. Let's assume b1 and b2's equations are in rows i, j. Row number for each free variable also - * indicates its position in other variable's equation. In our example, assume there are 5 free variables (free - * blocks), and i=2, j=4. Then, after adding weights to b1's equation, the system will look like the following: - * | x x x x x | |x | = | x | - * | 0 W12 0 -W12 0 | |b1| = | 0 | - * | x x x x x | * |x | = | x | - * | x x x x x | |b2| = | x | - * | x x x x x | |x | = | x | - * Differentiating with respect to b2 will result in same equation except flipped signs for the weight. This creates - * symmetry in the matrix, resulting in: - * | x x x x x | |x | = | x | - * | 0 W12 0 -W12 0 | |b1| = | 0 | - * | x x x x x | * |x | = | x | - * | 0 -W12 0 W12 0 | |b2| = | 0 | - * | x x x x x | |x | = | x | - * To generalize, for movable blocks b1, b2 in row i,j, with connection weight W, the W is added to matrix position - * [i][i] and [j][j], -W added to [i][j] and [j][i]. This is why stamp_weight_on_matrix is invoked 4 times below. - * - * Special Case: immovable/fixed block. - * Assume b2 in the above example is fixed, then it does not have an equation in the system as it's not a free variable. - * The new equation is now W12 * b1 = W12 * b2, where b2 is just a constant. (This makes sense as b1=b2 is optimal, - * since it has wirelength of 0). The matrix equation now looks like the following: - * | x x x x x | |x | = | x | - * | 0 W12 0 0 0 | |b1| = |W12*b2| - * | x x x x x | * |x | = | x | - * | x x x x x | |x | = | x | - * | x x x x x | |x | = | x | - * - * Special Case: connection to macro member. - * Assume b1 is the head block of a macro, b3 is its macro member with offset d. b3 has a connection with movable block - * b2, with weight W23. b3's location is then (b1 + d). The new equation w.r.t. b1 is W23 * (b1 + d - b2) = 0. - * New equation w.r.t. b3 is symmetrical, producing matrix: - * | x x x x x | |x | = | x | - * | 0 W23 0 -W23 0 | |b1| = |-W23*d| - * | x x x x x | * |x | = | x | - * | 0 -W23 0 W23 0 | |b2| = | W23*d| - * | x x x x x | |x | = | x | - * As shown here, connection to macro members are formulated into macro's head block's equation. This is why macro members - * are not formulated in equation system. - * - * EquationSystem is passed in for adding weights, dir selects x/y direction, num_pins is used in weight calculation - * (bound2bound model). bound_pin and this_pin specifies the 2 pins in the connection (one of them is always bound_pin). - */ -void AnalyticPlacer::add_pin_to_pin_connection(EquationSystem& es, - bool dir, - int num_pins, - ClusterPinId bound_pin, - ClusterPinId this_pin) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - if (this_pin == bound_pin) - // no connection if 2 pins are the same - return; - - // this_blk and bound_blk locations may not be accurate for larger tiles spanning multiple grid locations - // need block_locs[blk_id].loc.x + physical_tile_type(bnum)->pin_width_offset[pnum] - // however, in order to do so, need place_sync_external_block_connections(blk_id) for all blocks - // TODO: map logical pin to physical pin and add this offset for more accurate pin location - ClusterBlockId this_blk = clb_nlist.pin_block(this_pin); - int this_pos = dir ? blk_locs[this_blk].loc.y : blk_locs[this_blk].loc.x; - ClusterBlockId bound_blk = clb_nlist.pin_block(bound_pin); - int bound_pos = dir ? blk_locs[bound_blk].loc.y : blk_locs[bound_blk].loc.x; - // implementing the bound-to-bound net model detailed in HeAP paper, where each bound blk has (num_pins - 1) connections - // (bound_pos - this_pos) in the denominator "linearizes" the quadratic term (bound_pos - this_pos)^2 in the objective function - // This ensures that the objective function target HPWL, rather than quadratic wirelength. - double weight = 1.0 / ((num_pins - 1) * std::max(1, std::abs(bound_pos - this_pos))); - - /* - * TODO: adding timing weights to matrix entries - *if (this_pin != 0){ - * weight *= (1.0 + tmpCfg.timingWeight * std::pow(place_crit.criticality(net_id, this_pin), tmgCfg.criticalityExponent)); - * } - */ - - stamp_weight_on_matrix(es, dir, this_blk, this_blk, weight); - stamp_weight_on_matrix(es, dir, this_blk, bound_blk, -weight); - stamp_weight_on_matrix(es, dir, bound_blk, bound_blk, weight); - stamp_weight_on_matrix(es, dir, bound_blk, this_blk, -weight); -} - -// Build the system of equations for either X or Y -void AnalyticPlacer::build_equations(EquationSystem& es, bool yaxis, int iter) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - // Return the x or y position of a block - auto blk_p = [&](ClusterBlockId blk_id) { return yaxis ? blk_locs[blk_id].loc.y : blk_locs[blk_id].loc.x; }; - // Return legal position from legalization, after first iteration - auto legal_p = [&](ClusterBlockId blk_id) { return yaxis ? blk_locs[blk_id].legal_loc.y : blk_locs[blk_id].legal_loc.x; }; - es.reset(); - - /* - * Bound2bound model is used in HeAP: - * For each net, the left-most and right-most (or down, up in y direction) are bound blocks - * These 2 blocks form connections with each other and all the other blocks (internal blocks) - * These connections are used to formulate the matrix equation - */ - for (auto net_id : clb_nlist.nets()) { - if (clb_nlist.net_is_ignored(net_id) - || clb_nlist.net_driver(net_id) == ClusterPinId::INVALID() - || clb_nlist.net_sinks(net_id).empty()) { - // ensure net is not ignored (ex. clk nets), has valid driver, has at least 1 sink - continue; - } - - // find the 2 bound pins (min and max pin) - ClusterPinId min_pin = ClusterPinId::INVALID(), max_pin = ClusterPinId::INVALID(); - int min_pos = std::numeric_limits::max(), max_pos = std::numeric_limits::min(); - for (auto pin_id : clb_nlist.net_pins(net_id)) { - int pos = blk_p(clb_nlist.pin_block(pin_id)); - if (pos < min_pos) { - min_pos = pos; - min_pin = pin_id; - } - if (pos > max_pos) { - max_pos = pos; - max_pin = pin_id; - } - } - VTR_ASSERT(min_pin != ClusterPinId::INVALID()); - VTR_ASSERT(max_pin != ClusterPinId::INVALID()); - - int num_pins = clb_nlist.net_pins(net_id).size(); - for (int ipin = 0; ipin < num_pins; ipin++) { - ClusterPinId pin_id = clb_nlist.net_pin(net_id, ipin); - // for each pin in net, connect to 2 bound pins (bound2bound model) - add_pin_to_pin_connection(es, yaxis, num_pins, min_pin, pin_id); - if (pin_id != min_pin) - // avoid adding min_pin to max_pin connection twice - add_pin_to_pin_connection(es, yaxis, num_pins, max_pin, pin_id); - } - } - - // Add pseudo-connections to anchor points (legalized position for each block) after first iteration - // These pseudo-connections pull blocks towards their legal locations, which tends to reduce overlaps in the placement, - // also so that the next iteration of build-solving matrix doesn't destroy the placement from last iteration. - // As weight increases with number of iterations, solver's solution converges with the legal placement. - if (iter != -1) { // if not the first AP iteration - for (size_t row = 0; row < solve_blks.size(); row++) { - int l_pos = legal_p(solve_blks.at(row)); // legalized position from last iteration (anchors) - int solver_blk_pos = blk_p(solve_blks.at(row)); // matrix solved block position from last iteration - - // weight increases with iteration --> psudo-connection strength increases to force convergence to legal placement - // weight is also higher for blocks that haven't moved much from their solver location to their legal location - double weight = ap_cfg.alpha * iter / std::max(1, std::abs(l_pos - solver_blk_pos)); - - // Adding coefficient to Matrix[row][row] and adding weight to rhs vector is equivalent to adding connection - // to an immovable block at legal position. - // The equation becomes Weight * (blk_pos - legal_pos) = 0, where blk_pos is the variable to solve in rhs[row], - // legal_pos is a constant - // see comment for add_pin_to_pin_connection() -> special_case: immovable/fixed block - es.add_coeff(row, row, weight); - es.add_rhs(row, weight * l_pos); - } - } -} - -/* - * Solve the system of equations - * A formulated system of equation es is passed in - * yaxis represents if it's x-directed or y-directed location problem - * Solved solution is moved to loc, rawx, rawy in blk_locs for each block - */ -void AnalyticPlacer::solve_equations(EquationSystem& es, bool yaxis) { - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - auto blk_pos = [&](ClusterBlockId blk_id) { return yaxis ? blk_locs[blk_id].rawy : blk_locs[blk_id].rawx; }; - std::vector solve_blks_pos; // each row of solve_blks_pos is a free variable (movable block of the right type to be placed) - // put current location of solve_blks into solve_blks_pos as guess for iterative solver - std::transform(solve_blks.begin(), solve_blks.end(), std::back_inserter(solve_blks_pos), blk_pos); - es.solve(solve_blks_pos, ap_cfg.solverTolerance); - - // move solved locations of solve_blks from solve_blks_pos into blk_locs - // ensure that new location is strictly within [0, grid.width/height - 1]; - for (size_t i_row = 0; i_row < solve_blks_pos.size(); i_row++) - if (yaxis) { - blk_locs[solve_blks.at(i_row)].rawy = std::max(0.0, solve_blks_pos.at(i_row)); - blk_locs[solve_blks.at(i_row)].loc.y = std::min(max_y - 1, std::max(0, int(solve_blks_pos.at(i_row) + 0.5))); - } else { - blk_locs[solve_blks.at(i_row)].rawx = std::max(0.0, solve_blks_pos.at(i_row)); - blk_locs[solve_blks.at(i_row)].loc.x = std::min(max_x - 1, std::max(0, int(solve_blks_pos.at(i_row) + 0.5))); - } -} - -// Debug use, finds # of blocks on each tile location -void AnalyticPlacer::find_overlap(vtr::Matrix& overlap) { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - size_t max_x = g_vpr_ctx.device().grid.width(); - size_t max_y = g_vpr_ctx.device().grid.height(); - - overlap.resize({max_y, max_x}, 0); - - for (auto blk : clb_nlist.blocks()) { - overlap[blk_locs[blk].loc.y][blk_locs[blk].loc.x] += 1; - } -} - -// prints a simple figure of FPGA fabric, with numbers on each tile showing usage -// called in AnalyticPlacer::print_place() -std::string AnalyticPlacer::print_overlap(vtr::Matrix& overlap, FILE* fp) { - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - std::string out = ""; - fprintf(fp, "%5s", ""); - for (int i = 0; i < max_x; i++) { - fprintf(fp, "%-5d", i); - } - fprintf(fp, "\n%4s", ""); - fprintf(fp, "%s\n", std::string(5 * max_x + 2, '-').c_str()); - for (int i = 0; i < max_y; i++) { - fprintf(fp, "%-4d|", i); - for (int j = 0; j < max_x; j++) { - int count = overlap[i][j]; - fprintf(fp, "%-5s", ((count == 0) ? "0" : std::to_string(count)).c_str()); - } - fprintf(fp, "|\n"); - } - fprintf(fp, "%4s", ""); - fprintf(fp, "%s\n", std::string(5 * max_x + 2, '-').c_str()); - return out; -} - -/* - * Prints the location of each block, and a simple drawing of FPGA fabric, showing num of blocks on each tile - * Very useful for debugging - * Usage: - * std::string filename = vtr::string_fmt("%s.post_AP.place", clb_nlist.netlist_name().substr(0, clb_nlist.netlist_name().size()-4).c_str()); - * print_place(filename.c_str()); - */ -void AnalyticPlacer::print_place(const char* place_file) { - const DeviceContext& device_ctx = g_vpr_ctx.device(); - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - auto& block_locs = blk_loc_registry_ref_.block_locs(); - - FILE* fp; - - fp = fopen(place_file, "w"); - - fprintf(fp, "Netlist_File: %s Netlist_ID: %s\n", - clb_nlist.netlist_name().c_str(), - clb_nlist.netlist_id().c_str()); - fprintf(fp, "Array size: %zu x %zu logic blocks\n\n", device_ctx.grid.width(), device_ctx.grid.height()); - fprintf(fp, "%-25s %-18s %-12s %-25s %-5s %-5s %-10s %-14s %-8s\n", - "block name", - "logic block type", - "pb_type", - "pb_name", - "x", - "y", - "subblk", - "block number", - "is_fixed"); - fprintf(fp, "%-25s %-18s %-12s %-25s %-5s %-5s %-10s %-14s %-8s\n", - "----------", - "----------------", - "-------", - "-------", - "--", - "--", - "------", - "------------", - "--------"); - - if (!block_locs.empty()) { //Only if placement exists - for (auto blk_id : clb_nlist.blocks()) { - fprintf(fp, "%-25s %-18s %-12s %-25s %-5d %-5d %-10d #%-13zu %-8s\n", - clb_nlist.block_name(blk_id).c_str(), - clb_nlist.block_type(blk_id)->name.c_str(), - clb_nlist.block_type(blk_id)->pb_type->name, - clb_nlist.block_pb(blk_id)->name, - blk_locs[blk_id].loc.x, - blk_locs[blk_id].loc.y, - blk_locs[blk_id].loc.sub_tile, - size_t(blk_id), - (block_locs[blk_id].is_fixed ? "true" : "false")); - } - fprintf(fp, "\ntotal_HPWL: %d\n", total_hpwl()); - vtr::Matrix overlap; - find_overlap(overlap); - fprintf(fp, "Occupancy diagram: \n"); - print_overlap(overlap, fp); - } - fclose(fp); -} - -void AnalyticPlacer::print_AP_status_header() { - VTR_LOG("\n"); - VTR_LOG("---- ------ ------ -------- ------- | ------ --------- ------ ------ ------ ------ -------- -------- --------\n"); - VTR_LOG("Iter Time Iter Best Stall | Run BlockType Solve Solve Spread Legal Solved Spread Legal\n"); - VTR_LOG(" Time hpwl | Time Block Time Time Time hpwl hpwl hpwl\n"); - VTR_LOG(" (sec) (sec) | (sec) Num (sec) (sec) (sec) \n"); - VTR_LOG("---- ------ ------ -------- ------- | ------ --------- ------ ------ ------ ------ -------- -------- --------\n"); -} - -void AnalyticPlacer::print_run_stats(const int iter, - const float time, - const float runTime, - const char* blockType, - const int blockNum, - const float solveTime, - const float spreadTime, - const float legalTime, - const int solvedHPWL, - const int spreadHPWL, - const int legalHPWL) { - VTR_LOG( - "%4zu " - "%6.3f " - " | " - "%6.3f " - "%9s " - "%6d " - "%6.3f " - "%6.3f " - "%6.3f " - "%8d " - "%8d " - "%8d \n", - iter, - time, - runTime, - blockType, - blockNum, - solveTime, - spreadTime, - legalTime, - solvedHPWL, - spreadHPWL, - legalHPWL); -} - -void AnalyticPlacer::print_iter_stats(const int iter, - const float iterTime, - const float time, - const int bestHPWL, - const int stall) { - VTR_LOG( - "%4zu " - "%6.3f " - "%6.3f " - "%8d " - "%7d |\n", - iter, - time, - iterTime, - bestHPWL, - stall); - VTR_LOG(" |\n"); -} - -// sentinel for blks not solved in current iteration -int DONT_SOLVE = std::numeric_limits::max(); - -// sentinel for blks not part of a placement macro -int NO_MACRO = -1; - -#endif /* ENABLE_ANALYTIC_PLACE */ diff --git a/vpr/src/place/analytic_placer.h b/vpr/src/place/analytic_placer.h deleted file mode 100644 index 86e31481858..00000000000 --- a/vpr/src/place/analytic_placer.h +++ /dev/null @@ -1,326 +0,0 @@ -#ifndef VPR_ANALYTIC_PLACEMENT_H -#define VPR_ANALYTIC_PLACEMENT_H - -#ifdef ENABLE_ANALYTIC_PLACE -/** - * @file - * @brief This file implements the analytic placer, described as lower-bound placement in SimPL. It formulates - * the placement problem into a set of linear equations, in the form of a matrix equation. Solving the matrix - * equation gives the minimum of the objective function, in this case wirelength. The result placement, although - * most optimal in terms of optimization, thus the name lower-bound placement, almost always is not legal. This - * lower-bound solution is then legalized using Cut-Spreading (@see cut_spreader.h). - * - ************************************************************************************************************** - * Algorithm Overview * - ************************************************************************************************************** - * - * The most common objective function for placement is the sum of half-perimeter wirelengths (HPWL) over all nets. - * Efficient AP techniques approximate this objective function with a function that can be minimized efficiently. - * - * First, all multi-pin nets are converted into a set of 2-pin connections. In SimPL/HeAP, the Bound2bound net - * model is used. For each multi-pin net, the blocks with the minimum and maximum locations (in either x or y directon - * as build-solve operates on only 1 direction at a time) on a net (so-called bound-blocks) are connected to each - * other and to each internal block on the net. In other words, for a p-terminal net, each internal block has 2 connections, - * one to each bound block, and each bound block has p-1 connections, one to every block other than itself. - * - * Then, the weighted sum of the squared lengths of these 2-pin connections are minimized. This objective function - * can be separated into x and y components and cast in matrix form. To minimize this degree-2 polynomial, partial - * derivative is taken with respect to each variable. Setting the resulting system of linear equations to 0 gives - * the following equation (only x direction shown): - * Qx = -c - * where Q is a matrix capturing all connection between movable objects (objects to solve), x is a vector of all - * movable block locations (free variables), and c is a vector representing connections between movable and fixed objects. - * *** for detailed derivation and an example, refer to comments for add_pin_to_pin_connection() in analytic_placer.cpp. - * - * After formulating Q and c, a standard off-the-shelf solver (Eigen package) is used to solve for x. This completes - * the lower-bound placement. - * - * However, since the objective function does not take placement constraints into consideration, the generated - * solution is not legal. It generally has many blocks overlapping with one another, and the blocks may be on - * incompatible physical tiles. To legalize this solution, a geometric partitioning and spreading technique, introduced - * in SimPL, is used (@see cut_sreader.h). This completes the upper-bound placement. - * - * After the completion of 1 iteration of lower-bound & upper-bound placement, artificial pseudo connections are created - * between each block and its target location in the legalized overlap-free placement. When the mathematical system is - * again formulated and solved, the pseudo connections pull blocks towards their target locations, which tends to reduce - * overlaps in the placement. The strength of pseudo-connections increase with iterations, making lower-bound and - * upper-bound solutions converge. - * - * This process of formulating the system, solving, and legalizing is repeated until sufficiently good placement is - * acquired. Currently the stopping criterion is HEAP_STALLED_ITERATIONS_STOP iterations without improvement in total_hpwl. - * - * - * Parameters to tweak & things to try out - * ======================================= - * Currently the QoR of AP+quench combination is slightly worse than SA. See PR #1504 for comparison. - * The following parameters/things can be tweaked to find the best configuration: - * - * * Stopping criteria when to stop AP iterations, see (AnalyticPlacer::ap_place()) - * * PlacerHeapCfg.alpha anchoring strength of pseudo-connection - * * PlacerHeapCfg.beta overutilization factor (@see CutSpreader::SpreaderRegion.overused()) - * * PlacerHeapCfg.timingWeight implement timing in AP (@see AnalyticPlacer::build_equations()) - * * PlacerHeapCfg.criticality same as above - * * Interaction with SA: - * * init_t Initial temperature of annealer after AP (currently init_t = 0) - * * quench inner_num how much swapping in quenching to attemp - * * quench_recompute_limit frequency of criticality update in quenching to improve quench results - * - * @cite SimPL - * Original analytic placer with cut-spreading legalizing was intended for ASIC design, proposed in SimPL. - * SimPL: An Effective Placement Algorithm, Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov - * http://www.ece.umich.edu/cse/awards/pdfs/iccad10-simpl.pdf - * - * @cite HeAP - * FPGA adaptation of SimPL, targeting FPGAs with heterogeneous blocks located at discrete locations. - * Analytical Placement for Heterogeneous FPGAs, Marcel Gort and Jason H. Anderson - * https://janders.eecg.utoronto.ca/pdfs/marcelfpl12.pdf - * - * @cite nextpnr - * An implementation of HeAP, which the cut-spreader and legalizer here is based off of. Implementation details - * have been modified for the architecture and netlist specification of VTR, and better performance. - * nextpnr -- Next Generation Place and Route, placer_heap, David Shah - * https://github.com/YosysHQ/nextpnr - */ - -#include "vpr_context.h" -#include "PlacementDelayCalculator.h" - -class PlaceMacros; - -/* - * @brief Templated struct for constructing and solving matrix equations in analytic placer - * Eigen library is used in EquationSystem::solve() - */ -template -struct EquationSystem; - -// sentinel for blks not solved in current iteration -extern int DONT_SOLVE; - -// sentinel for blks not part of a placement macro -extern int NO_MACRO; - -class AnalyticPlacer { - public: - /* - * @brief Constructor of AnalyticPlacer, currently initializes AnalyticPlacerCfg for the analytic placer - * To tune these parameters, change directly in constructor - */ - AnalyticPlacer() = delete; - explicit AnalyticPlacer(BlkLocRegistry& blk_loc_registry, const PlaceMacros& place_macros); - - /* - * @brief main function of analytic placement - * Takes the random initial placement from place.cpp through g_vpr_ctx - * Repeat the following until stopping criteria is met: - * * Formulate and solve equations in x, y directions for 1 type of logial block - * * Instantiate CutSpreader to spread and strict_legalize() to strictly legalize - * - * The final legal placement is passed back to annealer in g_vpr_ctx.mutable_placement() - */ - void ap_place(); - - private: - // for CutSpreader to access placement info from solver (legal_pos, block_locs, etc). - friend class CutSpreader; - - // AP parameters that can influence it's behavior - struct AnalyticPlacerCfg { - float alpha; // anchoring strength of pseudo-connections - float beta; // over-utilization factor - int criticalityExponent; // not currently used, @see build_equations() - int timingWeight; // not currently used, @see build_equations() - float solverTolerance; // parameter of the solver - int buildSolveIter; // build_solve iterations for iterative solver - int spread_scale_x, spread_scale_y; // see CutSpreader::expand_regions() - }; - - AnalyticPlacerCfg ap_cfg; // TODO: PlacerHeapCfg should be externally configured & supplied - - // Lokup of all sub_tiles by sub_tile type - // legal_pos[0..device_ctx.num_block_types-1][0..num_sub_tiles - 1][0..num_legal - 1] = t_pl_loc for a single - // placement location of the proper tile type and sub_tile type. - std::vector>> legal_pos; - - // row number in the system of linear equations for each block - // which corresponds to the equation produced by differentiating objective function w.r.t that block location - vtr::vector_map row_num; - - // Encapsulates 3 types of locations for each logic block - struct BlockLocation { - t_pl_loc loc; // real, up-to-date location of the logic block in the AP process - // first initiated with initial random placement from g_vpr_ctx - // then, eath time after solving equations, it's updated with rounded - // raw solutions from solver - // finally, it is accessed and modified by legalizer to store legal placement - // at the end of each AP iteration - - t_pl_loc legal_loc; // legalized location, used to create psudo connections in the next AP iteration - // updated in AP main loop in ap_place() at the end of each iteration - - double rawx, rawy; // raw location storing float result from matrix solver - // used by cut_speader to spread out logic blocks using linear interpolation - }; - - // Lookup from blockID to block location - vtr::vector_map blk_locs; - - // reference to the placement location variables - BlkLocRegistry& blk_loc_registry_ref_; - - // Reference to the placement macros. - const PlaceMacros& place_macros_; - - /* - * The set of blks of different types to be placed by AnalyticPlacement process, - * i.e. the free variable blocks. - * Excludes non-head macro blocks (blocks part of placement macros but not the head), fixed blocks, and blocks - * with no connections. - */ - std::vector place_blks; - - // blocks of the same type to be solved in the current formulation of matrix equation - // which are a subset of place_blks - std::vector solve_blks; - - /* - * Prints the location of each block, and a simple drawing of FPGA fabric, showing num of blocks on each tile - * Very useful for debugging - * See implementation for usage - */ - void print_place(const char* place_file); - - //build fast lookup of compatible tiles/subtiles by tile, x, y, subtiles - void build_fast_tiles(); - - // build legal_pos - void build_legal_locations(); - - // build blk_locs based on initial placement from place_ctx. - // put blocks that needs to be placed in place_blks; - void init(); - - // get hpwl for a net - int get_net_hpwl(ClusterNetId net_id); - - // get hpwl for all nets - int total_hpwl(); - - // build matrix equations and solve for block type "run" in both x and y directions - // macro member positions are updated after solving - // iter is used to determine pseudo-connection strength - void build_solve_type(t_logical_block_type_ptr run, int iter); - - /* - * Setup the blocks of type blkTypes (ex. clb, io) to be solved. These blocks are put into - * solve_blks vector. Each of them is a free variable in the matrix equation (thus excluding - * macro members, as they are formulated into the equation for the macro's head) - * A row number is assigned to each of these blocks, which corresponds to its equation in - * the matrix (the equation acquired from differentiating the objective function w.r.t its - * x or y location). - */ - void setup_solve_blks(t_logical_block_type_ptr blkTypes); - - /* - * Update the location of all members of all macros based on location of macro_head - * since only macro_head is solved (connections to macro members are also taken into account - * when formulating the matrix equations), a location update for members is necessary - */ - void update_macros(); - - /* - * Build and solve in one direction - * yaxis chooses x or y location of each block from blk_locs to formulate the matrix equation - * Solved solutions are written back to block_locs[blk].rawx/rawy for double float raw solution, - * rounded int solutions are written back to block_locs[blk].loc, for each blk in solve_blks - * - * iter is the number of AnalyticPlacement iterations (solving and legalizing all types of logic - * blocks once). When iter != -1, at least one iteration has completed. It signals build_equations() - * to create pseudo-connections between each block and its prior legal position. - * - * build_solve_iter determines number of iterations of building and solving for the iterative solver - * (i.e. more build_solve_iter means better result, with runtime tradeoff. This parameter can be - * tuned for better performance) - * the solution from the previous build-solve iteration is used as a guess for the iterative solver - */ - void build_solve_direction(bool yaxis, int iter, int build_solve_iter); - - /* - * Stamp 1 weight for 1 connection on matrix or rhs vector - * if var is movable objects, weight is added on matrix - * if var is immovable objects, weight*-var_pos is added on rhs - * if var is a macro member (not macro head), weight*-offset_from_macro_head is added on rhs - * - * for detailed derivation and examples, see comments for add_pin_to_pin_connection() in analytic_placer.cpp - */ - void stamp_weight_on_matrix(EquationSystem& es, - bool dir, - ClusterBlockId var, - ClusterBlockId eqn, - double weight); - - /* - * Add weights for connection between bound_pin and this_pin into matrix - * Calculate weight for connection and stamp them into appropriate position in matrix by invoking - * stamp_weight_on_matrix() multiple times. For more detail, see comments in implementation. - */ - void add_pin_to_pin_connection(EquationSystem& es, - bool dir, - int num_pins, - ClusterPinId bound_pin, - ClusterPinId this_pin); - - /* - * Build the system of equations for either X or Y - * When iter != -1, for each block, psudo-conenction to its prior legal location is formed, - * the strength is determined by ap_cfg.alpha and iter - */ - void build_equations(EquationSystem& es, bool yaxis, int iter = -1); - - /* - * Solve the system of equations passed in by es, for the set of blocks in data member solve_blks - * yaxis is used to select current x or y location of these blocks from blk_locs - * this current location is provided to iterative solver as a guess - * the solved location is written back to blk_locs, and is used as guess for the next - * iteration of solving (@see build_solve_direct()) - */ - void solve_equations(EquationSystem& es, bool yaxis); - - /* - * Debug use - * finds # of blocks on each tile location, returned in overlap matrix - */ - void find_overlap(vtr::Matrix& overlap); - - /* - * Debug use - * prints a simple figure of FPGA fabric, with numbers on each tile showing usage. - * called in AnalyticPlacer::print_place() - */ - std::string print_overlap(vtr::Matrix& overlap, FILE* fp); - - // header of VTR_LOG for AP - void print_AP_status_header(); - - void print_run_stats(const int iter, - const float time, - const float runTime, - const char* blockType, - const int blockNum, - const float solveTime, - const float spreadTime, - const float legalTime, - const int solvedHPWL, - const int spreadHPWL, - const int legalHPWL); - - void print_iter_stats(const int iter, - const float iterTime, - const float time, - const int bestHPWL, - const int stall); -}; - -#endif /* ENABLE_ANALYTIC_PLACE */ - -#endif /* VPR_ANALYTIC_PLACEMENT_H */ diff --git a/vpr/src/place/compressed_grid.h b/vpr/src/place/compressed_grid.h index 6f9575fb670..8d6ecd9097b 100644 --- a/vpr/src/place/compressed_grid.h +++ b/vpr/src/place/compressed_grid.h @@ -5,7 +5,6 @@ #include "physical_types.h" #include "vtr_assert.h" -#include "vtr_geometry.h" #include "vtr_flat_map.h" struct t_compressed_block_grid { diff --git a/vpr/src/place/cut_spreader.cpp b/vpr/src/place/cut_spreader.cpp deleted file mode 100644 index 9dfe17f83c6..00000000000 --- a/vpr/src/place/cut_spreader.cpp +++ /dev/null @@ -1,1174 +0,0 @@ -#include "place_macro.h" -#ifdef ENABLE_ANALYTIC_PLACE - -#include "cut_spreader.h" -#include -#include -#include -#include - -#include "analytic_placer.h" -#include "vpr_types.h" -#include "vtr_time.h" -#include "globals.h" -#include "vtr_log.h" -#include "place_util.h" -#include "grid_block.h" - -// sentinel for base case in CutSpreader (i.e. only 1 block left in region) -constexpr std::pair BASE_CASE = {-2, -2}; - -// sentinel for cut-spreading fail, the other direction is run next -constexpr std::pair CUT_FAIL = {-1, -1}; - -// sentinel for a grid location that is not covered by any regions, for reg_id_at_grid data member -constexpr int AP_NO_REGION = -1; - -/* - * Constructor of CutSpreader - * @param analytic_placer: used to access AnalyticPlacer data members (lower-bound solutions) - * @param blk_t: logical block type to legalize - */ -CutSpreader::CutSpreader(AnalyticPlacer* analytic_placer, t_logical_block_type_ptr blk_t) - : ap(analytic_placer) - , blk_type(blk_t) { - // builds n_subtiles_at_location data member, which is a quick lookup of number of compatible subtiles at x, y. - size_t max_x = g_vpr_ctx.device().grid.width(); - size_t max_y = g_vpr_ctx.device().grid.height(); - subtiles_at_location.resize({max_x, max_y}); - for (auto& tile : blk_type->equivalent_tiles) { - for (auto sub_tile : tile->sub_tiles) { - // find all sub_tile types compatible with blk_t - auto result = std::find(sub_tile.equivalent_sites.begin(), sub_tile.equivalent_sites.end(), blk_type); - if (result != sub_tile.equivalent_sites.end()) { - for (auto loc : ap->legal_pos.at(tile->index).at(sub_tile.index)) { - subtiles_at_location[loc.x][loc.y].push_back(loc); - } - } - } - } -} - -/* - * @brief: Executes the cut-spreader algorithm described in algorithm overview in header file. - * Does not include strict_legalize so placement result is not guaranteed to be legal. - * Strict_legalize must be run after for legal placement result, and for legal placement to - * be passed to annealer through vpr_ctx. - * - * Input placement is passed by data members (blk_locs) in analytic_placer - * - * @return result placement is passed to strict legalizer by modifying blk_locs in analytic_placer - */ -void CutSpreader::cutSpread() { - init(); // initialize data members based on solved solutions from AnalyticPlacer - find_overused_regions(); //find all overused regions bordered by non-overused regions - expand_regions(); // expand overused regions until they have enough sub_tiles to accommodate their logic blks - - /* - * workqueue is a FIFO queue used to recursively cut-spread. - * - * In the region vector, the regions not in merged_regions (not absorbed in expansion process) - * are the initial regions placed in workqueue to cut-spread. - * - * After each of these initial regions are cut and spread, their child sub-regions - * (left and right) are placed at the back of workqueue, with alternated cut direction. - * This process continues until base case of region with only 1 block is reached, - * indicated by BASE_CASE return value. - * - * Return value of CUT_FAIL indicates that cutting is unsuccessful. This usually happens - * when regions are quite small: for example, region only has 1 column so a vertical cut - * is impossible. In this case cut in the other direction is attempted. - */ - std::queue> workqueue; - - // put initial regions into workqueue - for (auto& r : regions) { - if (!merged_regions.count(r.id)) - workqueue.emplace(r.id, false); - } - - while (!workqueue.empty()) { - auto front = workqueue.front(); - workqueue.pop(); - auto& r = regions.at(front.first); - - auto res = cut_region(r, front.second); - if (res == BASE_CASE) // only 1 block left, base case - continue; - if (res != CUT_FAIL) { // cut-spread successful - // place children regions in workqueue - workqueue.emplace(res.first, !front.second); - workqueue.emplace(res.second, !front.second); - } else { // cut-spread unsuccessful - auto res2 = cut_region(r, !front.second); // try other direction - if (res2 != CUT_FAIL) { - // place children regions in workqueue - workqueue.emplace(res2.first, front.second); - workqueue.emplace(res2.second, front.second); - } - } - } -} - -// setup CutSpreader data structures using information from AnalyticPlacer -void CutSpreader::init() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->place_macros_; - - size_t max_x = g_vpr_ctx.device().grid.width(); - size_t max_y = g_vpr_ctx.device().grid.height(); - - occupancy.resize({max_x, max_y}, 0); - macro_extent.resize({max_x, max_y}); - reg_id_at_grid.resize({max_x, max_y}, AP_NO_REGION); - blk_extents.resize(ap->blk_locs.size(), vtr::Rect{-1, -1, -1, -1}); - blks_at_location.resize({max_x, max_y}, std::vector{}); - - // Initialize occupancy matrix, reg_id_at_grid and macros matrix - for (int x = 0; x < (int)max_x; x++) { - for (int y = 0; y < (int)max_y; y++) { - occupancy[x][y] = 0; - reg_id_at_grid[x][y] = AP_NO_REGION; - macro_extent[x][y] = {x, y, x, y}; - } - } - - // lambda function to absorb x, y in blk's macro's extent - auto set_macro_ext = [&](ClusterBlockId blk, int x, int y) { - if (blk_extents[blk] == vtr::Rect{-1, -1, -1, -1}) { - blk_extents.update(blk, {x, y, x, y}); - } else { - blk_extents[blk].expand_bounding_box({x, y, x, y}); - } - }; - - for (size_t i = 0; i < ap->blk_locs.size(); i++) { // loop through ap->blk_locs - auto blk = ClusterBlockId{(int)i}; - if (clb_nlist.block_type(blk) == blk_type) { - auto loc = ap->blk_locs[blk].loc; - occupancy[loc.x][loc.y]++; - // compute extent of macro member - if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // if blk is a macro member - // only update macro heads' extent in blk_extents - set_macro_ext(place_macros.macro_head(blk), loc.x, loc.y); - } - } - } - - for (size_t i = 0; i < ap->blk_locs.size(); i++) { // loop through ap->blk_locs - ClusterBlockId blk = ClusterBlockId{(int)i}; - if (clb_nlist.block_type(blk) == blk_type) { - // Transfer macro extents to the actual macros structure; - if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // if blk is a macro member - // update macro_extent for all macro members in macros - // for single blocks (not in macro), macros[x][y] = {x, y, x, y} - vtr::Rect& me = blk_extents[place_macros.macro_head(blk)]; - auto loc = ap->blk_locs[blk].loc; - auto& lme = macro_extent[loc.x][loc.y]; - lme.expand_bounding_box(me); - } - } - } - - // get solved_solution from AnalyticPlacer - for (auto blk : ap->solve_blks) { - if (clb_nlist.block_type(blk) == blk_type) - blks_at_location[ap->blk_locs[blk].loc.x][ap->blk_locs[blk].loc.y].push_back(blk); - } -} - -int CutSpreader::occ_at(int x, int y) { - //TODO: layer_num should be passed - if (!is_loc_on_chip({x, y, 0})) { - return 0; - } - return occupancy[x][y]; -} - -int CutSpreader::tiles_at(int x, int y) { - //TODO: layer_num should be passed - if (!is_loc_on_chip({x, y, 0})) { - return 0; - } - return int(subtiles_at_location[x][y].size()); -} - -/* - * When expanding a region, it might overlap with another region, one of them (merger) will absorb - * the other (mergee) by merging. @see expand_regions() below; - * - * Merge mergee into merged by: - * * change group id at mergee grids to merged id - * * adds all n_blks and n_tiles from mergee to merged region - * * grow merged to include all mergee grids - */ -void CutSpreader::merge_regions(SpreaderRegion& merged, SpreaderRegion& mergee) { - for (int x = mergee.bb.xmin(); x <= mergee.bb.xmax(); x++) - for (int y = mergee.bb.ymin(); y <= mergee.bb.ymax(); y++) { - //TODO: layer_num should be passed - if (!is_loc_on_chip({x, y, 0})) { //location is not within the chip - continue; - } - //x and y might belong to "merged" region already, no further action is required - if (merged.id == reg_id_at_grid[x][y]) { - continue; - } - reg_id_at_grid[x][y] = merged.id; //change group id at mergee grids to merged id - //adds all n_blks and n_tiles from mergee to merged region - merged.n_blks += occ_at(x, y); - merged.n_tiles += tiles_at(x, y); - } - merged_regions.insert(mergee.id); // all merged_regions are ignored in main loop - grow_region(merged, mergee.bb); // grow merged to include all mergee grids -} - -/* - * grow r to include a rectangular region rect_to_include - * - * when init == true, grow_region() initializes SpreaderRegion r - * in this case, both r and rect_to_include contains the same 1 tile location: the initial overused tile - * see find_overused_regions where SpreaderRegion r is created. - * this tile location is processed although it's technically included. - */ -void CutSpreader::grow_region(SpreaderRegion& r, vtr::Rect rect_to_include, bool init) { - // when given location is within SpreaderRegion - if ((r.bb.contains(rect_to_include)) && !init) - return; - - vtr::Rect r_old = r.bb; - r_old.set_xmin(r.bb.xmin() + (init ? 1 : 0)); // ensure the initial location is processed in the for-loop later, when init == 1 - r.bb.expand_bounding_box(rect_to_include); - - auto process_location = [&](int x, int y) { - //x and y should represent a location on the chip, otherwise no processing is required - //TODO: layer_num should be passed - if (!is_loc_on_chip({x, y, 0})) { - return; - } - // kicks in only when grid is not claimed, claimed by another region, or part of a macro - // Merge with any overlapping regions - if (reg_id_at_grid[x][y] == AP_NO_REGION) { - r.n_tiles += tiles_at(x, y); - r.n_blks += occ_at(x, y); - } - if (reg_id_at_grid[x][y] != AP_NO_REGION && reg_id_at_grid[x][y] != r.id) - merge_regions(r, regions.at(reg_id_at_grid[x][y])); - reg_id_at_grid[x][y] = r.id; - // Grow to cover any macros - auto& macro_bb = macro_extent[x][y]; - grow_region(r, macro_bb); - }; - // process new areas after including rect_to_include, while avoiding double counting old region - for (int x = r.bb.xmin(); x < r_old.xmin(); x++) - for (int y = r.bb.ymin(); y <= r.bb.ymax(); y++) - process_location(x, y); - for (int x = r_old.xmax() + 1; x <= r.bb.xmax(); x++) - for (int y = r.bb.ymin(); y <= r.bb.ymax(); y++) - process_location(x, y); - for (int y = r.bb.ymin(); y < r_old.ymin(); y++) - for (int x = r.bb.xmin(); x <= r.bb.xmax(); x++) - process_location(x, y); - for (int y = r_old.ymax() + 1; y <= r.bb.ymax(); y++) - for (int x = r.bb.xmin(); x <= r.bb.xmax(); x++) - process_location(x, y); -} - -// Find overutilized regions surrounded by non-overutilized regions -void CutSpreader::find_overused_regions() { - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - for (int x = 0; x < max_x; x++) - for (int y = 0; y < max_y; y++) { - if (reg_id_at_grid[x][y] != AP_NO_REGION || (occ_at(x, y) <= tiles_at(x, y))) - // already in a region or not over-utilized - continue; - - // create new overused region - int id = int(regions.size()); - reg_id_at_grid[x][y] = id; - SpreaderRegion reg; - reg.id = id; - reg.bb = {x, y, x, y}; - reg.n_tiles = reg.n_blks = 0; - reg.n_tiles += tiles_at(x, y); - reg.n_blks += occ_at(x, y); - - // initialize reg and ensure it covers macros - grow_region(reg, {x, y, x, y}, true); - - bool expanded = true; - while (expanded) { - expanded = false; - // keep expanding in x and y, until expansion in x, y cannot find overutilised blks - - // try expanding in x - if (reg.bb.xmax() < max_x - 1) { - bool over_occ_x = false; - for (int y1 = reg.bb.ymin(); y1 <= reg.bb.ymax(); y1++) { - if (occ_at(reg.bb.xmax() + 1, y1) > tiles_at(reg.bb.xmax() + 1, y1)) { - over_occ_x = true; - break; - } - } - if (over_occ_x) { - expanded = true; - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin(), reg.bb.xmax() + 1, reg.bb.ymax()}); - } - } - // try expanding in y - if (reg.bb.ymax() < max_y - 1) { - bool over_occ_y = false; - for (int x1 = reg.bb.xmin(); x1 <= reg.bb.xmax(); x1++) { - if (occ_at(x1, reg.bb.ymax() + 1) > tiles_at(x1, reg.bb.ymax() + 1)) { - over_occ_y = true; - break; - } - } - if (over_occ_y) { - expanded = true; - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin(), reg.bb.xmax(), reg.bb.ymax() + 1}); - } - } - } - regions.push_back(reg); - } -} - -/* - * Expand all utilized regions until they satisfy n_tiles * beta >= n_blocks - * If overutilized regions overlap in this process, they are merged - */ -void CutSpreader::expand_regions() { - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - std::queue overused_regions; - float beta = ap->ap_cfg.beta; - for (auto& r : regions) - // if region is not merged and is overused, move into overused_regions queue - if (!merged_regions.count(r.id) && r.overused(beta)) - overused_regions.push(r.id); - - while (!overused_regions.empty()) { // expand all overused regions - int rid = overused_regions.front(); - overused_regions.pop(); - if (merged_regions.count(rid)) - continue; - auto& reg = regions.at(rid); - while (reg.overused(beta)) { - bool changed = false; - - // spread_scale determines steps in x or y direction to expand each time - for (int j = 0; j < ap->ap_cfg.spread_scale_x; j++) { - if (reg.bb.xmin() > 0) { // expand in -x direction - grow_region(reg, {reg.bb.xmin() - 1, reg.bb.ymin(), reg.bb.xmax(), reg.bb.ymax()}); - changed = true; - if (!reg.overused(beta)) - break; - } - if (reg.bb.xmax() < max_x - 1) { // expand in +x direction - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin(), reg.bb.xmax() + 1, reg.bb.ymax()}); - changed = true; - if (!reg.overused(beta)) - break; - } - } - - for (int j = 0; j < ap->ap_cfg.spread_scale_y; j++) { - if (reg.bb.ymin() > 0) { // expand in -y direction - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin() - 1, reg.bb.xmax(), reg.bb.ymax()}); - changed = true; - if (!reg.overused(beta)) - break; - } - if (reg.bb.ymax() < max_y - 1) { // expand in +y direction - grow_region(reg, {reg.bb.xmin(), reg.bb.ymin(), reg.bb.xmax(), reg.bb.ymax() + 1}); - changed = true; - if (!reg.overused(beta)) - break; - } - } - VTR_ASSERT(changed || reg.n_tiles >= reg.n_blks); - } - VTR_ASSERT(reg.n_blks <= reg.n_tiles); - } -} - -/* - * Recursive cut-based spreading in HeAP paper - * "left" denotes "-x, -y", "right" denotes "+x, +y" depending on dir - * - * @param r region to cut & spread - * @param dir direction, true for y, false for x - * - * @return a pair of sub-region IDs created from cutting region r. - * BASE_CASE if base case is reached - * CUT_FAIL if cut unsuccessful, need to cut in the other direction - */ -std::pair CutSpreader::cut_region(SpreaderRegion& r, bool dir) { - const DeviceContext& device_ctx = g_vpr_ctx.device(); - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->place_macros_; - - // TODO: CutSpreader is not compatible with 3D FPGA - VTR_ASSERT(device_ctx.grid.get_num_layers() == 1); - int layer_num = 0; - - std::vector cut_blks; - init_cut_blks(r, cut_blks); // copy all logic blocks to cut into cut_blks - - // Trim the boundaries of the region in axis-of-interest, skipping any rows/cols without any tiles of the right type - int trimmed_l, trimmed_r; - std::pair(trimmed_l, trimmed_r) = trim_region(r, dir); - - // base case (only 1 block left in region) - if (cut_blks.size() == 1) { - // ensure placement of last block is on right type of tile - auto blk = cut_blks.at(0); - auto& tiles_type = clb_nlist.block_type(blk)->equivalent_tiles; - auto loc = ap->blk_locs[blk].loc; - if (std::find(tiles_type.begin(), tiles_type.end(), device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer})) == tiles_type.end()) { - // logic block type doesn't match tile type - // exhaustive search for tile of right type - // this search should be fast as region must be small at this point (only 1 logic block left) - for (int x = r.bb.xmin(); x <= r.bb.xmax(); x++) - for (int y = r.bb.ymin(); y <= r.bb.ymax(); y++) { - if (std::find(tiles_type.begin(), tiles_type.end(), device_ctx.grid.get_physical_type({x, y, layer_num})) != tiles_type.end()) { - VTR_ASSERT(blks_at_location[x][y].empty()); - ap->blk_locs[blk].rawx = x; - ap->blk_locs[blk].rawy = y; - ap->blk_locs[blk].loc.x = x; - ap->blk_locs[blk].loc.y = y; - blks_at_location[x][y].push_back(blk); - blks_at_location[loc.x][loc.y].clear(); - return BASE_CASE; - } - } - } - return BASE_CASE; - } - - // sort blks based on raw location - std::stable_sort(cut_blks.begin(), cut_blks.end(), [&](const ClusterBlockId a, const ClusterBlockId b) { - return dir ? (ap->blk_locs[a].rawy < ap->blk_locs[b].rawy) : (ap->blk_locs[a].rawx < ap->blk_locs[b].rawx); - }); - - /* - * Generate initial source cut. It cuts logic blocks in region r into 2 partitions. - * Initially, ensure that both partitions have similar numbers of logic blocks. - * Find the midpoint (in terms of total block size, including macros) in sorted cut_blks - * This is the initial source cut - */ - int clearance_l, clearance_r; - int pivot = initial_source_cut(r, cut_blks, dir, clearance_l, clearance_r); - - /* - * Generate initial target cut. It cuts the physical tiles into 2 sub-areas, into which - * the 2 partitions of logic blocks will be placed. - * - * The difference in utilization (# blocks / # tiles) should be smallest, while meeting - * clearance requirement for macros - */ - int left_blks_n, right_blks_n, left_tiles_n, right_tiles_n; - int best_tgt_cut = initial_target_cut(r, cut_blks, pivot, dir, trimmed_l, trimmed_r, - clearance_l, clearance_r, left_blks_n, right_blks_n, left_tiles_n, right_tiles_n); - if (best_tgt_cut == -1) // target cut fails clearance requirement for macros - return CUT_FAIL; - - // Once target_cut is acquired, define left and right subareas - // The boundaries are defined using the trimmed edges and best target cut - // The n_tiles will be final while n_blks may change by perturbing the source cut to eliminate - // overutilization in subareas - SpreaderRegion rl, rr; - rl.id = int(regions.size()); - rl.bb = dir ? vtr::Rect{r.bb.xmin(), trimmed_l, r.bb.xmax(), best_tgt_cut} - : vtr::Rect{trimmed_l, r.bb.ymin(), best_tgt_cut, r.bb.ymax()}; - rl.n_blks = left_blks_n; - rl.n_tiles = left_tiles_n; - rr.id = int(regions.size()) + 1; - rr.bb = dir ? vtr::Rect{r.bb.xmin(), best_tgt_cut + 1, r.bb.xmax(), trimmed_r} - : vtr::Rect{best_tgt_cut + 1, r.bb.ymin(), trimmed_r, r.bb.ymax()}; - rr.n_blks = right_blks_n; - rr.n_tiles = right_tiles_n; - // change the region IDs in each subarea's grid location to subarea's id - for (int x = rl.bb.xmin(); x <= rl.bb.xmax(); x++) - for (int y = rl.bb.ymin(); y <= rl.bb.ymax(); y++) - reg_id_at_grid[x][y] = rl.id; - for (int x = rr.bb.xmin(); x <= rr.bb.xmax(); x++) - for (int y = rr.bb.ymin(); y <= rr.bb.ymax(); y++) - reg_id_at_grid[x][y] = rr.id; - - /* - * Perturb source cut to eliminate over-utilization - * This is done by moving logic blocks from overused subarea to the other subarea one at a time - * until they are no longer overused. - */ - // while left subarea is over-utilized, move logic blocks to the right subarea one at a time - while (pivot > 0 && rl.overused(ap->ap_cfg.beta)) { - auto& move_blk = cut_blks.at(pivot); - int size = (place_macros.get_imacro_from_iblk(move_blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(move_blk)].members.size() : 1; - rl.n_blks -= size; - rr.n_blks += size; - pivot--; - } - // while right subarea is over-utilized, move logic blocks to the left subarea one at a time - while (pivot < int(cut_blks.size()) - 1 && rr.overused(ap->ap_cfg.beta)) { - auto& move_blk = cut_blks.at(pivot + 1); - int size = (place_macros.get_imacro_from_iblk(move_blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(move_blk)].members.size() : 1; - rl.n_blks += size; - rr.n_blks -= size; - pivot++; - } - - // within each subarea, spread the logic blocks into bins to make them more evenly spread out - linear_spread_subarea(cut_blks, dir, 0, pivot + 1, rl); - linear_spread_subarea(cut_blks, dir, pivot + 1, cut_blks.size(), rr); - - // push subareas back to regions so that they can be accessed by their IDs later - regions.push_back(rl); - regions.push_back(rr); - - return std::make_pair(rl.id, rr.id); -} - -// copy all logic blocks to cut into cut_blks -void CutSpreader::init_cut_blks(SpreaderRegion& r, std::vector& cut_blks) { - cut_blks.clear(); - for (int x = r.bb.xmin(); x <= r.bb.xmax(); x++) { - for (int y = r.bb.ymin(); y <= r.bb.ymax(); y++) { - std::copy(blks_at_location[x][y].begin(), blks_at_location[x][y].end(), std::back_inserter(cut_blks)); - } - } -} - -/* - * Trim the boundaries of the region r in axis-of-interest dir, skipping any rows/cols without - * tiles of the right type. - * Afterwards, move blocks in trimmed locations to new trimmed boundaries - */ -std::pair CutSpreader::trim_region(SpreaderRegion& r, bool dir) { - int bb_min = dir ? r.bb.ymin() : r.bb.xmin(); - int bb_max = dir ? r.bb.ymax() : r.bb.xmax(); - int trimmed_l = bb_min, trimmed_r = bb_max; - bool have_tiles = false; - while (trimmed_l < bb_max && !have_tiles) { // trim from left - for (int i = bb_min; i <= bb_max; i++) - if (tiles_at(dir ? i : trimmed_l, dir ? trimmed_l : i) > 0) { - have_tiles = true; - break; - } - if (!have_tiles) // trim when the row/col doesn't have tiles - trimmed_l++; - } - - have_tiles = false; - while (trimmed_r > bb_min && !have_tiles) { // trim from right - for (int i = bb_min; i <= bb_max; i++) - if (tiles_at(dir ? i : trimmed_r, dir ? trimmed_r : i) > 0) { - have_tiles = true; - break; - } - if (!have_tiles) // trim when the row/col doesn't have tiles - trimmed_r--; - } - - // move blocks from trimmed locations to new boundaries - for (int x = r.bb.xmin(); x < (dir ? r.bb.xmax() + 1 : trimmed_l); x++) { - for (int y = r.bb.ymin(); y < (dir ? trimmed_l : r.bb.ymax() + 1); y++) { - for (auto& blk : blks_at_location[x][y]) { - // new location is the closest trimmed boundary - int blk_new_x = dir ? x : trimmed_l, blk_new_y = dir ? trimmed_l : y; - ap->blk_locs[blk].rawx = blk_new_x; - ap->blk_locs[blk].rawy = blk_new_y; - ap->blk_locs[blk].loc.x = blk_new_x; - ap->blk_locs[blk].loc.y = blk_new_y; - blks_at_location[blk_new_x][blk_new_y].push_back(blk); - } - blks_at_location[x][y].clear(); // clear blocks at old location - } - } - - for (int x = (dir ? r.bb.xmin() : trimmed_r + 1); x <= r.bb.xmax(); x++) { - for (int y = (dir ? trimmed_r + 1 : r.bb.ymin()); y <= r.bb.ymax(); y++) { - for (auto& blk : blks_at_location[x][y]) { - // new location is the closest trimmed boundary - int blk_new_x = dir ? x : trimmed_r, blk_new_y = dir ? trimmed_r : y; - ap->blk_locs[blk].rawx = blk_new_x; - ap->blk_locs[blk].rawy = blk_new_y; - ap->blk_locs[blk].loc.x = blk_new_x; - ap->blk_locs[blk].loc.y = blk_new_y; - blks_at_location[blk_new_x][blk_new_y].push_back(blk); - } - blks_at_location[x][y].clear(); // clear blocks at old location - } - } - - return {trimmed_l, trimmed_r}; -} - -/* - * generate the initial source_cut for region r, ensure there is enough clearance on either side of the - * initial cut to accommodate macros - * returns the initial source cut (index into cut_blks) - * returns the clearance in clearance_l, clearance_r - * returns -1 if cannot generate initial source_cut (not enough clearance for macros) - * - * see CutSpreader::cut_region() invocation of initial_source_cut for more detail - */ -int CutSpreader::initial_source_cut(SpreaderRegion& r, - std::vector& cut_blks, - bool dir, - int& clearance_l, - int& clearance_r) { - const auto& place_macros = ap->place_macros_; - - // pivot is the midpoint of cut_blks in terms of total block size (counting macro members) - // this ensures the initial partitions have similar number of blocks - int pivot_blks = 0; // midpoint in terms of total number of blocks - int pivot = 0; // midpoint in terms of index of cut_blks - for (auto& blk : cut_blks) { - // if blk is part of macro (only macro heads in cut_blks, no macro members), add that macro's size - pivot_blks += (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(blk)].members.size() : 1; - if (pivot_blks >= r.n_blks / 2) - break; - pivot++; - } - if (pivot >= int(cut_blks.size())) - pivot = int(cut_blks.size()) - 1; - - // Find clearance required on either side of the pivot - // i.e. minimum distance from left and right bounds of region to pivot - // (no cut within clearance to accommodate macros) - clearance_l = 0, clearance_r = 0; - for (size_t i = 0; i < cut_blks.size(); i++) { - int size; - if (blk_extents.count(cut_blks.at(i))) { - auto& be = blk_extents[cut_blks.at(i)]; - size = dir ? (be.ymax() - be.ymin() + 1) : (be.xmax() - be.xmin() + 1); - } else { - size = 1; - } - if (int(i) < pivot) - clearance_l = std::max(clearance_l, size); - else - clearance_r = std::max(clearance_r, size); - } - return pivot; -} - -/* - * generate the initial target_cut for region r, ensure that utilization in 2 subareas are closest possible - * while meeting clearance requirements for macros - * returns best target cut - */ -int CutSpreader::initial_target_cut(SpreaderRegion& r, - std::vector& cut_blks, - int init_source_cut, - bool dir, - int trimmed_l, - int trimmed_r, - int clearance_l, - int clearance_r, - int& left_blks_n, - int& right_blks_n, - int& left_tiles_n, - int& right_tiles_n) { - const auto& place_macros = ap->place_macros_; - - // To achieve smallest difference in utilization, first move all tiles to right partition - left_blks_n = 0, right_blks_n = 0; - left_tiles_n = 0, right_tiles_n = r.n_tiles; - // count number of blks in each partition, from initial source cut - for (int i = 0; i <= init_source_cut; i++) - left_blks_n += (place_macros.get_imacro_from_iblk(cut_blks.at(i)) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(cut_blks.at(i))].members.size() : 1; - for (int i = init_source_cut + 1; i < int(cut_blks.size()); i++) - right_blks_n += (place_macros.get_imacro_from_iblk(cut_blks.at(i)) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(cut_blks.at(i))].members.size() : 1; - - int best_tgt_cut = -1; - double best_deltaU = std::numeric_limits::max(); - - // sweep source cut from left to right, moving tiles from right partition to the left - // calculate the difference in utilization for all target cuts, return the best result - for (int i = trimmed_l; i <= trimmed_r; i++) { - int slither_tiles = 0; - for (int j = dir ? r.bb.xmin() : r.bb.ymin(); j <= (dir ? r.bb.xmax() : r.bb.ymax()); j++) { - slither_tiles += dir ? tiles_at(j, i) : tiles_at(i, j); - } - - left_tiles_n += slither_tiles; - right_tiles_n -= slither_tiles; - - if (((i - trimmed_l) + 1) >= clearance_l && ((trimmed_r - i) + 1) >= clearance_r) { - // if solution accommodates macro clearances - // compare difference in utilization - double tmpU = std::abs(double(left_blks_n) / double(std::max(left_tiles_n, 1)) - double(right_blks_n) / double(std::max(right_tiles_n, 1))); - if (tmpU < best_deltaU) { - best_deltaU = tmpU; - best_tgt_cut = i; - } - } - } - - if (best_tgt_cut == -1) // failed clearance requirement for macros - return best_tgt_cut; - - // update number of tiles for each subarea - left_tiles_n = 0, right_tiles_n = 0; - for (int x = r.bb.xmin(); x <= (dir ? r.bb.xmax() : best_tgt_cut); x++) - for (int y = r.bb.ymin(); y <= (dir ? best_tgt_cut : r.bb.ymax()); y++) - left_tiles_n += tiles_at(x, y); - for (int x = dir ? r.bb.xmin() : (best_tgt_cut + 1); x <= r.bb.xmax(); x++) - for (int y = dir ? (best_tgt_cut + 1) : r.bb.ymin(); y <= r.bb.ymax(); y++) - right_tiles_n += tiles_at(x, y); - - if (left_tiles_n == 0 || right_tiles_n == 0) - // target cut failed since all tiles are still in one subarea - return -1; - - return best_tgt_cut; -} - -/* - * Spread blocks in subarea by linear interpolation - * blks_start and blks_end are indices into cut_blks. The blks between these indices will be spread by: - * * first split the subarea boundaries (area_l and area_r) - * into min(number_of_logic_blocks_in_subarea, 10) number of bins. - * * split the logic blocks into the corresponding number of groups - * * place the logic blocks from their group to their bin, by linear interpolation using their original - * locations to map to a new location in the bin. - */ -void CutSpreader::linear_spread_subarea(std::vector& cut_blks, - bool dir, - int blks_start, - int blks_end, - SpreaderRegion& sub_area) { - double area_l = dir ? sub_area.bb.ymin() : sub_area.bb.xmin(); // left boundary - double area_r = dir ? sub_area.bb.ymax() : sub_area.bb.xmax(); // right boundary - int N = blks_end - blks_start; // number of logic blocks in subarea - if (N <= 2) { // only 1 bin, skip binning and directly linear interpolate - for (int i = blks_start; i < blks_end; i++) { - auto& pos = dir ? ap->blk_locs[cut_blks.at(i)].rawy - : ap->blk_locs[cut_blks.at(i)].rawx; - pos = area_l + (i - blks_start) * ((area_r - area_l) / N); - } - } else { - // Split tiles into K bins, split blocks into K groups - // Since cut_blks are sorted, to specify block groups, only need the index of the left and right block - // Each block group has its original left and right bounds, the goal is to map this group's bound into - // bin's bounds, and assign new locations to blocks using linear interpolation - int K = std::min(N, 10); // number of bins/groups - std::vector> bin_bounds; // (0-th group's first block, 0-th bin's left bound) - bin_bounds.emplace_back(blks_start, area_l); - for (int i_bin = 1; i_bin < K; i_bin++) - // find i-th group's first block, i-th bin's left bound - bin_bounds.emplace_back(blks_start + (N * i_bin) / K, area_l + ((area_r - area_l + 0.99) * i_bin) / K); - bin_bounds.emplace_back(blks_end, area_r + 0.99); // find K-th group's last block, K-th bin's right bound - for (int i_bin = 0; i_bin < K; i_bin++) { - auto &bl = bin_bounds.at(i_bin), br = bin_bounds.at(i_bin + 1); // i-th bin's left and right bound - // i-th group's original bounds (left and right most block's original location) - double group_left = dir ? ap->blk_locs[cut_blks.at(bl.first)].rawy - : ap->blk_locs[cut_blks.at(bl.first)].rawx; - double group_right = dir ? ap->blk_locs[cut_blks.at(br.first - 1)].rawy - : ap->blk_locs[cut_blks.at(br.first - 1)].rawx; - double bin_left = bl.second; - double bin_right = br.second; - // mapping from i-th block group's original bounds to i-th bin's bounds - double mapping = (bin_right - bin_left) / std::max(0.00001, group_right - group_left); // prevent division by 0 - // map blks in i-th group to new location in i-th bin using linear interpolation - for (int i_blk = bl.first; i_blk < br.first; i_blk++) { - // new location is stored back into rawx/rawy - auto& blk_pos = dir ? ap->blk_locs[cut_blks.at(i_blk)].rawy - : ap->blk_locs[cut_blks.at(i_blk)].rawx; - - blk_pos = bin_left + mapping * (blk_pos - group_left); // linear interpolation - } - } - } - - // Update blks_at_location for each block with their new location - for (int x = sub_area.bb.xmin(); x <= sub_area.bb.xmax(); x++) - for (int y = sub_area.bb.ymin(); y <= sub_area.bb.ymax(); y++) { - blks_at_location[x][y].clear(); - } - for (int i_blk = blks_start; i_blk < blks_end; i_blk++) { - auto& bl = ap->blk_locs[cut_blks[i_blk]]; - bl.loc.x = std::min(sub_area.bb.xmax(), std::max(sub_area.bb.xmin(), int(bl.rawx))); - bl.loc.y = std::min(sub_area.bb.ymax(), std::max(sub_area.bb.ymin(), int(bl.rawy))); - blks_at_location[bl.loc.x][bl.loc.y].push_back(cut_blks[i_blk]); - } -} - -/* - * @brief: Greedy strict legalize using algorithm described in algorithm overview above. - * - * Input illegal placement from data members (blk_locs) in analytic_placer - * - * @return: both ap->blk_locs and vpr_ctx.mutable_placement() are modified with legal placement, - * to be used in next solve/spread/legalize iteration or to pass back to annealer. - */ -void CutSpreader::strict_legalize() { - auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& block_locs = ap->blk_loc_registry_ref_.block_locs(); - const auto& place_macros = ap->place_macros_; - int max_x = g_vpr_ctx.device().grid.width(); - int max_y = g_vpr_ctx.device().grid.height(); - - // clear the location of all blocks in place_ctx - for (auto blk : clb_nlist.blocks()) { - if (!block_locs[blk].is_fixed && (ap->row_num[blk] != DONT_SOLVE || (place_macros.get_imacro_from_iblk(blk) != NO_MACRO && ap->row_num[place_macros.macro_head(blk)] != DONT_SOLVE))) { - unbind_tile(block_locs[blk].loc); - } - } - - // Greedy largest-macro-first approach - // put all blocks being placed in current AP in priority_queue "remaining" with the priority being the - // length of the macro they are in (for single blocks, priority = 1). - // This prioritizes the placement of longest macros over single blocks - std::priority_queue> remaining; - for (ClusterBlockId blk : ap->solve_blks) { - if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // blk is head block of a macro (only head blks are solved) - remaining.emplace(place_macros[place_macros.get_imacro_from_iblk(blk)].members.size(), blk); - } else { - remaining.emplace(1, blk); - } - } - - /* - * ripup_radius determines at which point already placed single logic blocks will be "ripped up" for placement of - * the current block. Specifically, when radius of random selection (determined by availability of compatible sub_tiles) - * is larger than ripup_radius, occupied sub_tiles are also considered for blk's placement (not just unoccupied sub_tiles). - * - * Therefore, a small ripup_radius honors the current location of blk (from spreading) more, as it allows placement at - * occupied sub_tiles when random selection radius around current location is still small. When ripup_radius is large, - * blk can only search unoccupied sub_tiles in a large area before it can rip up placed blks. This will make blk more likely - * to stray far from current location. - * - * ripup_radius is doubled every time outer while-loop executes (ap->solve_blks.size()) times, - * i.e. after trying to place each block once, if there's still block to place (some block displaced/ripped up other blocks), - * ripup_radius is doubled, allowing these ripped up blocks to look for unoccupied sub_tiles in a larger area. - * - * Only applies for single blocks - */ - int ripup_radius = 2; - // num of iters of outer most while loop, cleared when it equals the number of blocks that needs to be place for this - // build-solve-legalize iteration. When cleared, ripup_radius is doubled. - int total_iters = 0; - // total_iters without clearing, used for time-out - int total_iters_noreset = 0; - - // outer while loop, each loop iteration aims to place one solve_blk (either single blk or head blk of a macro) - while (!remaining.empty()) { - auto top = remaining.top(); - remaining.pop(); - ClusterBlockId blk = top.second; - - if (is_placed(blk)) // ignore if already placed - continue; - - int radius = 0; // radius of 0 means initial candidate location is the current location of blk after spreading - int iter = 0; // iterations of the inner while-loop, used for timeout - - /* - * iter_at_radius: number of inner-loop iterations (number of proposed candidate locations) at current radius - * used to determine whether to explore more candidate locations (iter_at_radius < explore limit) - * or take the current best_subtile for blk - * - * only applies for single blocks - */ - int iter_at_radius = 0; - bool placed = false; // flag for inner-loop - t_pl_loc best_subtile = t_pl_loc{}; // current best candidate with smallest best_inp_len, only for single blocks - int best_inp_len = std::numeric_limits::max(); // used to choose best_subtile, only for single blocks - - total_iters++; - total_iters_noreset++; - - // clear total_iters and double ripup_radius when all solve_blks have been attempted to place once - if (total_iters > int(ap->solve_blks.size())) { - total_iters = 0; - ripup_radius = std::min(std::max(max_x - 1, max_y - 1), ripup_radius * 2); - } - - // timeout - // VTR_ASSERT(total_iters_noreset <= std::max(5000, 8 * int(clb_nlist.blocks().size()))); - - while (!placed) { // while blk is not placed - // timeout - VTR_ASSERT(iter <= std::max(10000, 3 * int(clb_nlist.blocks().size()))); - - // randomly choose a location within radius around current location (given by spreading) - int nx = rand() % (2 * radius + 1) + std::max(ap->blk_locs[blk].loc.x - radius, 0); - int ny = rand() % (2 * radius + 1) + std::max(ap->blk_locs[blk].loc.y - radius, 0); - - iter++; - iter_at_radius++; - if (iter >= (10 * (radius + 1))) { // a heuristic to determine when to increase radius - // check if there's sub_tiles of right type within radius. - // If no, increase radius until at least 1 compatible sub_tile is found - radius = std::min(std::max(max_x - 1, max_y - 1), radius + 1); - while (radius < std::max(max_x - 1, max_y - 1)) { - // search every location within radius for compatible sub_tiles - for (int x = std::max(0, ap->blk_locs[blk].loc.x - radius); - x <= std::min(max_x - 1, ap->blk_locs[blk].loc.x + radius); - x++) { - for (int y = std::max(0, ap->blk_locs[blk].loc.y - radius); - y <= std::min(max_y - 1, ap->blk_locs[blk].loc.y + radius); - y++) { - if (subtiles_at_location[x][y].size() > 0) // compatible sub_tiles found within radius - goto notempty; - } - } - // no sub_tiles found, increase radius - radius = std::min(std::max(max_x - 1, max_y - 1), radius + 1); - } - notempty: - iter_at_radius = 0; - iter = 0; - } - - if (nx < 0 || nx >= max_x || ny < 0 || ny >= max_y || subtiles_at_location[nx][ny].empty()) - // try another random location if candidate location is illegal or has no sub_tiles - continue; - - /* - * explore_limit determines when to stop exploring for better sub_tiles for blk - * When explore_limit is not met (iter_at_radius < explore_limit), each candidate sub_tile is evaluated based on - * their resulting total input wirelength (a heuristic) for blk. - * When explore_limit is met and a best_sub_tile is found, blk is placed there. - * - * Only applies for single blocks - * @see comments for try_place_blk() - */ - int explore_limit = 2 * radius; - - // if blk is not a macro member - if (place_macros.get_imacro_from_iblk(blk) == NO_MACRO) { - placed = try_place_blk(blk, - nx, - ny, - radius > ripup_radius, // bool ripup_radius_met - iter_at_radius >= explore_limit, // bool exceeds_explore_limit - best_inp_len, - best_subtile, - remaining); - } else { - placed = try_place_macro(blk, - nx, - ny, - remaining); - } - } - } -} - -/* - * Helper function in strict_legalize() - * Place blk on sub_tile location by modifying place_ctx.grid_blocks, place_ctx.block_locs, and ap->blk_locs[blk].loc - */ -void CutSpreader::bind_tile(t_pl_loc sub_tile, ClusterBlockId blk) { - auto& grid_blocks = ap->blk_loc_registry_ref_.mutable_grid_blocks(); - auto& block_locs = ap->blk_loc_registry_ref_.mutable_block_locs(); - - VTR_ASSERT(grid_blocks.block_at_location(sub_tile) == ClusterBlockId::INVALID()); - VTR_ASSERT(block_locs[blk].is_fixed == false); - grid_blocks.set_block_at_location(sub_tile, blk); - block_locs[blk].loc = sub_tile; - grid_blocks.increment_usage({sub_tile.x, sub_tile.y, sub_tile.layer}); - ap->blk_locs[blk].loc = sub_tile; -} - -/* - * Helper function in strict_legalize() - * Remove placement at sub_tile location by clearing place_ctx.block_locs and place_Ctx.grid_blocks - */ -void CutSpreader::unbind_tile(t_pl_loc sub_tile) { - auto& grid_blocks = ap->blk_loc_registry_ref_.mutable_grid_blocks(); - auto& block_locs = ap->blk_loc_registry_ref_.mutable_block_locs(); - - VTR_ASSERT(grid_blocks.block_at_location(sub_tile) != ClusterBlockId::INVALID()); - ClusterBlockId blk = grid_blocks.block_at_location(sub_tile); - VTR_ASSERT(block_locs[blk].is_fixed == false); - block_locs[blk].loc = t_pl_loc{}; - grid_blocks.set_block_at_location(sub_tile, ClusterBlockId::INVALID()); - grid_blocks.decrement_usage({sub_tile.x, sub_tile.y, sub_tile.layer}); -} - -/* - * Helper function in strict_legalze() - * Check if the block is placed in place_ctx (place_ctx.block_locs[blk] has a location that matches - * the block in place_ctx.grid_blocks) - */ -bool CutSpreader::is_placed(ClusterBlockId blk) { - const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); - const auto& block_locs = ap->blk_loc_registry_ref_.block_locs(); - - if (block_locs[blk].loc != t_pl_loc{}) { - auto loc = block_locs[blk].loc; - VTR_ASSERT(grid_blocks.block_at_location(loc) == blk); - return true; - } - return false; -} - -/* - * Sub-routine of strict_legalize() - * Tries to place a single block "blk" at a candidate location nx, ny. Returns whether the blk is successfully placed. - * - * If number of iterations at current radius has exceeded the exploration limit (exceeds_explore_limit), - * and a candidate sub_tile is already found (best_subtile), then candidate location is ignored, and blk is - * placed in best_subtile. - * - * Else, if exploration limit is not exceeded, the sub_tiles at nx, ny are evaluated on the blk's resulting total - * input wirelength (a heuristic). If this total input wirelength is shorter than current best_inp_len, it becomes - * the new best_subtile. - * If exploration limit is exceeded and no candidate sub_tile is available in (best_subtile), then blk is placed at - * next compatible sub_tile at candidate location nx, ny. - * - * If blk displaces a logic block by taking its sub_tile, the displaced logic block is put back into remaining queue. - */ -bool CutSpreader::try_place_blk(ClusterBlockId blk, - int nx, - int ny, - bool ripup_radius_met, - bool exceeds_explore_limit, - int& best_inp_len, - t_pl_loc& best_subtile, - std::priority_queue>& remaining) { - const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->place_macros_; - - // iteration at current radius has exceeded exploration limit, and a candidate sub_tile (best_subtile) is found - // then blk is placed in best_subtile - if (exceeds_explore_limit && best_subtile != t_pl_loc{}) { - // find the logic block bound to (placed on) best_subtile - ClusterBlockId bound_blk = grid_blocks.block_at_location(best_subtile); - if (bound_blk) { // if best_subtile has a logic block - unbind_tile(best_subtile); // clear bound_block and best_subtile's placement info - remaining.emplace(1, bound_blk); // put bound_blk back into remaining blocks to place - } - bind_tile(best_subtile, blk); // place blk on best_subtile - return true; - } - - // if exploration limit is not met or a candidate sub_tile is not found yet - for (auto sub_t : subtiles_at_location[nx][ny]) { // for each available sub_tile at random location - ClusterBlockId bound_blk = grid_blocks.block_at_location(sub_t); // logic blk at [nx, ny] - if (bound_blk == ClusterBlockId::INVALID() - || ripup_radius_met - || rand() % (20000) < 10) { - /* conditions when a sub_tile at nx, ny is considered: - * - sub_tile is not occupied (no bound_blk) - * - occupied sub_tile is considered when: - * 1) current radius > ripup-radius. (see strict_legalize() for more details) - * OR - * 2) a 0.05% chance of acceptance. - */ - if (bound_blk && place_macros.get_imacro_from_iblk(bound_blk) != NO_MACRO) - // do not sub_tiles when the block placed on it is part of a macro, as they have higher priority - continue; - if (!exceeds_explore_limit) { // if still in exploration phase, find best_subtile with smallest best_inp_len - int input_len = 0; - // find all input pins and add up input wirelength - for (auto pin : clb_nlist.block_input_pins(blk)) { - ClusterNetId net = clb_nlist.pin_net(pin); - if (net == ClusterNetId::INVALID() - || clb_nlist.net_is_ignored(net) - || clb_nlist.net_driver(net) == ClusterPinId::INVALID()) - continue; - ClusterBlockId driver = clb_nlist.pin_block(clb_nlist.net_driver(net)); - auto driver_loc = ap->blk_locs[driver].loc; - input_len += std::abs(driver_loc.x - nx) + std::abs(driver_loc.y - ny); - } - if (input_len < best_inp_len) { - // update best_subtile - best_inp_len = input_len; - best_subtile = sub_t; - } - break; - } else { // exploration phase passed and still no best_subtile yet, choose the next compatible sub_tile - if (bound_blk) { - remaining.emplace(1, bound_blk); - unbind_tile(sub_t); // remove bound_blk and place blk on sub_t - } - bind_tile(sub_t, blk); - return true; - } - } - } - return false; -} - -/* - * Sub-routine of strict_legalize() - * - * Tries to place the macro with the head block on candidate location nx, ny. Returns if the macro is successfully placed. - * - * For each possible macro placement starting from nx, ny, if any block's position in the macro does not have compatible - * sub_tiles or overlaps with another macro, the placement is impossible. - * - * If a possible placement is found, it's applied to all blocks. - */ -bool CutSpreader::try_place_macro(ClusterBlockId blk, - int nx, - int ny, - std::priority_queue>& remaining) { - const auto& place_macros = ap->place_macros_; - const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - for (auto sub_t : subtiles_at_location[nx][ny]) { - std::vector> targets; // contains the target placement location for each macro block - std::queue> visit; // visit goes through all macro members once - visit.emplace(blk, sub_t); // push head block and target sub_tile first - bool placement_impossible = false; // once set to true, break while loop and try next sub_t - while (!visit.empty()) { // go through every macro block - ClusterBlockId visit_blk = visit.front().first; - VTR_ASSERT(!is_placed(visit_blk)); - t_pl_loc target = visit.front().second; // target location - visit.pop(); - - // ensure the target location has compatible tile - auto blk_t = clb_nlist.block_type(blk); - auto result = std::find(blk_t->equivalent_tiles.begin(), blk_t->equivalent_tiles.end(), g_vpr_ctx.device().grid.get_physical_type({target.x, target.y, target.layer})); - if (result == blk_t->equivalent_tiles.end()) { - placement_impossible = true; - break; - } - - // if the target location has a logic block, ensure it's not part of a macro - // because a macro placed before the current one has higher priority (longer chain) - ClusterBlockId bound = grid_blocks.block_at_location(target); - if (bound && place_macros.get_imacro_from_iblk(bound) != NO_MACRO) { - placement_impossible = true; - break; - } - // place macro block into target vector along with its target location - targets.emplace_back(visit_blk, target); - if (place_macros.macro_head(visit_blk) == visit_blk) { // if visit_blk is the head block of the macro - // push all macro members to visit queue along with their calculated positions - const std::vector& members = place_macros[place_macros.get_imacro_from_iblk(blk)].members; - for (auto member = members.begin() + 1; member != members.end(); ++member) { - t_pl_loc mloc = target + member->offset; // calculate member_loc using (head blk location + offset) - visit.emplace(member->blk_index, mloc); - } - } - } - - if (!placement_impossible) { // if placement is possible, apply this placement - for (auto& target : targets) { - ClusterBlockId bound = grid_blocks.block_at_location(target.second); - if (bound) { - // if target location has a logic block, displace it and put it in remaining queue to be placed later - unbind_tile(target.second); - remaining.emplace(1, bound); - } - bind_tile(target.second, target.first); - } - return true; - } - } - return false; -} - -#endif /* ENABLE_ANALYTIC_PLACE */ diff --git a/vpr/src/place/cut_spreader.h b/vpr/src/place/cut_spreader.h deleted file mode 100644 index 5be5f0ed79d..00000000000 --- a/vpr/src/place/cut_spreader.h +++ /dev/null @@ -1,378 +0,0 @@ -#ifndef VPR_SRC_PLACE_LEGALIZER_H_ -#define VPR_SRC_PLACE_LEGALIZER_H_ - -#ifdef ENABLE_ANALYTIC_PLACE - -/** - * @file - * @brief This file defines the cut-spreader class with a greedy legalizer as a member method. - * Cut-spreader roughly legalizes overutilized tiles present in illegal placement from the matrix equation - * solution (lower-bound placement), using geometric partitioning to recursively cut and spread tiles within - * these regions, eliminating most overutilizations. - * Legalizer then strictly legalizes the placement using a greedy strategy, ensuring logic block to physical - * subtile type-matching and eliminating all overutilizations. This completes the lower-bound placement. - * - ************************************************************************************************************** - * Algorithm Overview * - ************************************************************************************************************** - * The solution produced by the solver almost always contains 2 types of illegality: overutilization and - * logical-physical type mismatch. - * - * Cut-Spreader - * ============ - * To resolve overutilization, a recursive partitioning-style placement approach is used. It consists of the following - * steps: - * - * find_overused_regions & expand_regions - * -------------------------------------- - * @see find_overused_regions() - * @see expand_regions() - * The first step is to find an area of the FPGA that is overutilized for which the blocks contained within - * must be spread to a larger area. To obtain this overutilized area, adjacent locations on the FPGA that are - * occupied by more than one block (also overutilized) are repeatedly clustered together, until all clusters - * are bordered on all sides by non-overutilized locations. Next, the area is expanded in both the x and y - * directions until it's large enough to accommodate all blocks contained. Overutilization is defined as follows: - * (Occupancy / Capacity) > beta, where beta is a constant <=1, currently defined in AnalyticPlacer::PlacerHeapCfg. - * - * cut_region - * ---------- - * @see cut_region() - * @see run() - * In the second step, two cuts are generated: a source cut and a target cut. The source cut pertains to the blocks - * being placed; the target cut pertains to the area into which the blocks are placed. The source cut splits the - * blocks into two partitions, while the target cut splits the area into two sub-areas, into which the blocks in - * each partition are spread. Two objectives are minimized during this process: the imbalance between the number of - * blocks in each partition, and the difference in the utilization (Occupancy / Capacity) of each subarea. - * - * To generate the source cut, the logic blocks are sorted by their raw_x or raw_y location, depending on the - * orientation of the desired cut. After sorting, a pivot is chosen, all blocks to the left of the pivot are - * assigned to the left partition, and all blocks to the right are assigned to the right partition (we use left - * for left/top, right for right/bottom in x/y directions respectively in the implementation). - * - * The target cut is an x or y cut of the area such that all blocks in each partition fit in their respective - * subareas, and the difference in utilization is minimized. This is difficult due to the discrete nature of FPGA - * architecture. To achieve this, first assign all tiles to right region, then move tiles to the left one by one, - * calculating the difference in utilization for each move. The move with smallest delta_utilization is chosen as - * the target cut. To eliminate possible overutilization in either subarea, perturb the source cut by moving a - * single block from the over-utilized sub-area to the other, until neither is overutilized. - * - * Next, the blocks in sub-areas are spread to distribute them evenly. We split the sub-area into 10 equally-sized - * bins and logic blocks into 10 equal-capacity source bins. Then linearly interpolate to map blocks from their - * original locations in their source bins to new spread location in target bins. - * - * This cutting and spreading is repeated recursively. The cut-spreading process returns the left and right - * (or top and bottom) subareas, which are pushed into a workqueue FIFO. Their direction of cut in the next - * cut-spreading process is alternated, i.e. if the first cut is in y direction, the resulting left and right - * sub-areas are further cut in x direction, each producing 2 subareas top and bottom, and so forth. - * The first region in the FIFO is then popped and goes through cut-spreading. This process is repeated until the base - * case of only 1 block in the region is reached. At this point the placement is mostly not overutilized and ready - * for strict legalization. - * - * ************************************************************************************************************** - * - * Strict Legalizer - * ================ - * @see strict_legalize() - * Strict Legalizer ensures that the placement is strictly legal. It does so using a greedy approach. - * - * All blocks are sorted in descending macro lengths order and put in a priority queue (only macro heads are - * considered, while the rest of the macro members are ignored; single blocks have length 1). Each block goes through - * the following procedure: - * - * * Find all compatible sub_tile types, based on which all potential sub_tile locations are found (this process is - * made computationally cheap by legal_pos data member in AnalyticPlacer) - * * Within a radius (starting from 0) of the block's currently location, randomly choose a location as candidate. - * * If the block is a single block (not in macro), multiple candidates are potentially chosen, and the one that - * results in the smallest input wirelength (sum of wirelengths to its inputs) for the block is chosen. - * * If the block is a macro head, the location for all member blocks are calculated using member offsets. If all - * member locations have compatible sub_tile and does not overlap with another macro, then place the macro. - * * In either case, if the candidate fails to satisfy legality constraints, the radius may increase (depending on - * number of iterations at current radius), and a new candidate will be chosen. - * - * - * @cite SimPL - * Original analytic placer with cut-spreading legalizing was intended for ASIC design, proposed in SimPL. - * SimPL: An Effective Placement Algorithm, Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov - * http://www.ece.umich.edu/cse/awards/pdfs/iccad10-simpl.pdf - * - * @cite HeAP - * FPGA adaptation of SimPL, targeting FPGAs with heterogeneous blocks located at discrete locations. - * Analytical Placement for Heterogeneous FPGAs, Marcel Gort and Jason H. Anderson - * https://janders.eecg.utoronto.ca/pdfs/marcelfpl12.pdf - * - * @cite nextpnr - * An implementation of HeAP, which the cut-spreader and legalizer here is based off of. Implementation details - * have been modified for the architecture and netlist specification of VTR, and better performance. - * nextpnr -- Next Generation Place and Route, placer_heap, David Shah - * https://github.com/YosysHQ/nextpnr - * - */ -#include "vpr_context.h" -#include - -// declaration of used types; -class AnalyticPlacer; -struct t_logical_block_type; - -// Cut-spreader, as described in HeAP/SimPL papers -class CutSpreader { - public: - /* - * @brief: Constructor of CutSpreader - * - * @param analytic_placer pointer to the analytic_placer that invokes this instance of CutSpreader. - * passed for CutSpreader to directly access data members in analytic_placer such as - * blk_locs, blk_info, solve_blks, etc, without re-packaging the data to pass to - * CutSpreader. - * - * @param blk_t logical_block_type for CutSpreader to legalize. Currently can only legalize one - * type each time. - */ - CutSpreader(AnalyticPlacer* analytic_placer, t_logical_block_type_ptr blk_t); - - /* - * @brief: Executes the cut-spreader algorithm described in algorithm overview above. - * Does not include strict_legalize so placement result is not guaranteed to be legal. - * Strict_legalize must run after for legal placement result, and for legal placement to - * be passed to annealer through vpr_ctx. - * - * Input placement is passed by data members (blk_locs) in analytic_placer - * - * @return result placement is passed to strict legalizer by modifying blk_locs in analytic_placer - */ - void cutSpread(); - - /* - * @brief: Greedy strict legalize using algorithm described in algorithm overview above. - * - * Input illegal placement from data members (blk_locs) in analytic_placer, - * previously modified by cut_spreader - * - * @return: both ap->blk_locs and vpr_ctx.mutable_placement() are modified with legal placement, - * to be used in next solve/spread/legalize iteration or to pass back to annealer. - */ - void strict_legalize(); - - private: - // pointer to analytic_placer to access its data members - AnalyticPlacer* ap; - - // block type to legalize - t_logical_block_type_ptr blk_type; - - // struct describing regions on FPGA to cut_spread - struct SpreaderRegion { - int id; // index of regions in regions vector - vtr::Rect bb; // bounding box of the region - int n_blks, n_tiles; // number of netlist blocks and compatible tiles (placement locations) - bool overused(float beta) const { - // determines whether region is overutilized: overused = (Occupancy / Capacity) > beta - if (n_blks > beta * n_tiles) - return true; - else - return false; - } - }; - - // Utilization of each tile, indexed by x, y - vtr::Matrix occupancy; - - // Region ID of each tile, indexed by x, y. AP_NO_REGION if not covered by any region - // Used to check ownership of a grid position by region. - vtr::Matrix reg_id_at_grid; - - // Extent of macro at x, y location. If blk is not in any macros, it only covers a single location - vtr::Matrix> macro_extent; - - // List of logic blocks of blk_type at x, y location, indexed by x, y - // ex. to find all logic blocks occupying location x, y, blks_at_location[x][y] gives a vector of - // block IDs at that location - vtr::Matrix> blks_at_location; - - // List of all compatible sub_tiles for the type of blocks being cut-spread, at location x, y. - // usage: subtiles_at_location[x][y] - vtr::Matrix> subtiles_at_location; - - // List of all SpreaderRegion, index of vector members is the id of the region - std::vector regions; - - // List of all merged_regions, these regions are merged in larger regions and should be skipped when - // recursively cut_spreading. Each entry is the region's ID, which is also the index into the regions vector - std::unordered_set merged_regions; - - // Lookup of macro's extent by block ID. If block is a single block, it contains only 1 tile location - vtr::vector_map> blk_extents; - - // Setup CutSpreader data structures using information from AnalyticPlacer - // including blks_at_location, macros, groups, etc. - void init(); - - // Returns number of logical blocks at x, y location - int occ_at(int x, int y); - - // Returns number of compatible sub_tiles at x, y location - int tiles_at(int x, int y); - - /* - * When expanding a region, it might overlap with another region, one of them (merger) will absorb - * the other (mergee) by merging. @see expand_regions() below; - * - * Merge mergee into merged by: - * * change group id at mergee grids to merged id - * * adds all n_blks and n_tiles from mergee to merged region - * * grow merged to include all mergee grids - */ - void merge_regions(SpreaderRegion& merged, SpreaderRegion& mergee); - - /* - * Grow region r to include a rectangular region - * Pass init = true if first time calling for a newly created region - */ - void grow_region(SpreaderRegion& r, vtr::Rect rect_to_include, bool init = false); - - /* - * Expand all over-utilized regions until they satisfy n_tiles * beta >= n_blocks - * If overutilized regions overlap in this process, they are merged - */ - void expand_regions(); - - /* - * Find overutilized regions surrounded by non-overutilized regions - * Start off at an overutilized tile and expand in x, y directions 1 step at a time in both directions - * until the region is surrounded by non-overutilized regions. - */ - void find_overused_regions(); - - // copy all logic blocks that needs to be cut into cut_blks - void init_cut_blks(SpreaderRegion& r, std::vector& cut_blks); - - /* - * generate the initial source_cut for region r, ensure there is enough clearance on either side of the - * initial cut to accommodate macros - * returns the initial source cut (index into cut_blks) - * returns the clearance in clearance_l, clearance_r - * returns -1 if cannot generate initial source_cut (not enough clearance for macros) - */ - int initial_source_cut(SpreaderRegion& r, - std::vector& cut_blks, - bool dir, - int& clearance_l, - int& clearance_r); - - /* - * generate the initial target_cut for region r, ensure that utilization in 2 subareas are closest possible - * while meeting clearance requirements for macros - * returns best target cut - * returns the resulting number of blocks in left and right partitions in left_blks_n, right_blks_n - * returns the resulting number of tiles in left and right subareas in left_tiles_n, right_tiles_n - */ - int initial_target_cut(SpreaderRegion& r, - std::vector& cut_blks, - int init_source_cut, - bool dir, - int trimmed_l, - int trimmed_r, - int clearance_l, - int clearance_r, - int& left_blks_n, - int& right_blks_n, - int& left_tiles_n, - int& right_tiles_n); - - /* - * Trim the boundaries of the region in axis-of-interest, skipping any rows/cols without any tiles - * of the right type. - * Afterwards, move blocks in trimmed locations to new trimmed boundaries - */ - std::pair trim_region(SpreaderRegion& r, bool dir); - - /* - * Spread blocks in subarea by linear interpolation - * blks_start and blks_end are indices into cut_blks. The blks between these indices will be spread by: - * * first split the subarea (between boundaries area_l and area_r) into - * min(number_of_logic_blocks_in_subarea, 10) number of bins. - * * split the logic blocks into the corresponding number of groups - * * place the logic blocks from their group to their bin, by linear interpolation using their original - * locations to map to a new location in the bin. - */ - void linear_spread_subarea(std::vector& cut_blks, - bool dir, - int blks_start, - int blks_end, - SpreaderRegion& sub_area); - - /* - * Recursive cut-based spreading in HeAP paper - * "left" denotes "-x, -y", "right" denotes "+x, +y" depending on dir - * - * @param r region to cut & spread - * @param dir direction, true for y, false for x - * - * @return a pair of sub-region IDs created from cutting region r. - * BASE_CASE if base case is reached - * CUT_FAIL if cut unsuccessful, need to cut in the other direction - */ - std::pair cut_region(SpreaderRegion& r, bool dir); - - /* - * Helper function in strict_legalize() - * Place blk on sub_tile location by modifying place_ctx.grid_blocks and place_ctx.block_locs - */ - void bind_tile(t_pl_loc sub_tile, ClusterBlockId blk); - - /* - * Helper function in strict_legalize() - * Remove placement at sub_tile location by clearing place_ctx.block_locs and place_Ctx.grid_blocks - */ - void unbind_tile(t_pl_loc sub_tile); - - /* - * Helper function in strict_legalize() - * Check if the block is placed in place_ctx (place_ctx.block_locs[blk] has a location that matches - * the block in place_ctx.grid_blocks) - */ - bool is_placed(ClusterBlockId blk); - - /* - * Sub-routine of strict_legalize() - * Tries to place a single block "blk" at a candidate location nx, ny. Returns whether the blk is succesfully placed. - * - * If number of iterations at current radius has exceeded the exploration limit (exceeds_explore_limit), - * and a candidate sub_tile is already found (best_subtile), then candidate location is ignored, and blk is - * placed in best_subtile. - * - * Else, if exploration limit is not exceeded, the subtiles at nx, ny are evaluated on the blk's resulting total - * input wirelength (a heuristic). If this total input wirelength is shorter than current best_inp_len, it becomes - * the new best_subtile. - * If exploration limit is exceeded and no candidate sub_tile is available in (best_subtile), then blk is placed at - * next sub_tile at candidate location nx, ny. - * - * If blk displaces a logic block by taking its sub_tile, the displaced logic block is put back into remaining queue. - */ - bool try_place_blk(ClusterBlockId blk, - int nx, - int ny, - bool ripup_radius_met, - bool exceeds_need_to_explore, - int& best_inp_len, - t_pl_loc& best_subtile, - std::priority_queue>& remaining); - - /* - * Sub-routine of strict_legalize() - * - * Tries to place the macro with the head block on candidate location nx, ny. Returns if the macro is successfully placed. - * - * For each possible macro placement starting from nx, ny, if any block's position in the macro does not have compatible - * sub_tiles or overlaps with another macro, the placement is impossible. - * - * If a possible placement is found, it's applied to all blocks. - */ - bool try_place_macro(ClusterBlockId blk, - int nx, - int ny, - std::priority_queue>& remaining); -}; -#endif /* ENABLE_ANALYTIC_PLACE */ - -#endif /* VPR_SRC_PLACE_LEGALIZER_H_ */ diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp index e58cb4b9539..1ec59f4ed10 100644 --- a/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp @@ -27,9 +27,9 @@ std::unique_ptr PlacementDelayModelCreator::create_delay_model(const t_placer_opts& placer_opts, const t_router_opts& router_opts, const Netlist<>& net_list, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, - t_chan_width_dist chan_width_dist, + const t_chan_width_dist& chan_width_dist, const std::vector& directs, bool is_flat) { vtr::ScopedStartFinishTimer timer("Computing placement delta delay look-up"); @@ -38,7 +38,7 @@ PlacementDelayModelCreator::create_delay_model(const t_placer_opts& placer_opts, alloc_routing_structs(chan_width, router_opts, det_routing_arch, segment_inf, directs, is_flat); - const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, + const RouterLookahead* router_lookahead = get_cached_router_lookahead(det_routing_arch, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.h b/vpr/src/place/delay_model/PlacementDelayModelCreator.h index c92b67d4854..c003d85e034 100644 --- a/vpr/src/place/delay_model/PlacementDelayModelCreator.h +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.h @@ -22,9 +22,9 @@ class PlacementDelayModelCreator { static std::unique_ptr create_delay_model(const t_placer_opts& placer_opts, const t_router_opts& router_opts, const Netlist<>& net_list, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, - t_chan_width_dist chan_width_dist, + const t_chan_width_dist& chan_width_dist, const std::vector& directs, bool is_flat); }; diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp index bb1232d2778..17b866c6330 100644 --- a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp @@ -532,7 +532,7 @@ static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*rou auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); for (int driver_ptc : best_driver_ptcs) { VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, SOURCE, driver_ptc); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, e_rr_type::SOURCE, driver_ptc); VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts, is_flat); @@ -566,7 +566,7 @@ static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*rou auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); for (int sink_ptc : best_sink_ptcs) { VTR_ASSERT(sink_ptc != OPEN); - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, SINK, sink_ptc); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, e_rr_type::SINK, sink_ptc); if (sink_rr_node == RRNodeId::INVALID()) continue; @@ -651,13 +651,13 @@ static float route_connection_delay(RouterDelayProfiler& route_profiler, for (int driver_ptc : best_driver_ptcs) { VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, SOURCE, driver_ptc); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, e_rr_type::SOURCE, driver_ptc); VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); for (int sink_ptc : best_sink_ptcs) { VTR_ASSERT(sink_ptc != OPEN); - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(sink_layer, sink_x, sink_y, SINK, sink_ptc); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(sink_layer, sink_x, sink_y, e_rr_type::SINK, sink_ptc); if (sink_rr_node == RRNodeId::INVALID()) continue; @@ -846,10 +846,10 @@ bool find_direct_connect_sample_locations(const t_direct_inf* direct, //(with multi-width/height blocks pins may not exist at all locations) bool from_pin_found = false; if (direct->from_side != NUM_2D_SIDES) { - RRNodeId from_pin_rr = node_lookup.find_node(layer_num, x, y, OPIN, from_pin, direct->from_side); + RRNodeId from_pin_rr = node_lookup.find_node(layer_num, x, y, e_rr_type::OPIN, from_pin, direct->from_side); from_pin_found = from_pin_rr.is_valid(); } else { - from_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, x, y, OPIN, from_pin).empty()); + from_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, x, y, e_rr_type::OPIN, from_pin).empty()); } if (!from_pin_found) continue; @@ -862,10 +862,10 @@ bool find_direct_connect_sample_locations(const t_direct_inf* direct, //(with multi-width/height blocks pins may not exist at all locations) bool to_pin_found = false; if (direct->to_side != NUM_2D_SIDES) { - RRNodeId to_pin_rr = node_lookup.find_node(layer_num, to_x, to_y, IPIN, to_pin, direct->to_side); + RRNodeId to_pin_rr = node_lookup.find_node(layer_num, to_x, to_y, e_rr_type::IPIN, to_pin, direct->to_side); to_pin_found = (to_pin_rr != RRNodeId::INVALID()); } else { - to_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, to_x, to_y, IPIN, to_pin).empty()); + to_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, to_x, to_y, e_rr_type::IPIN, to_pin).empty()); } if (!to_pin_found) continue; @@ -903,13 +903,13 @@ bool find_direct_connect_sample_locations(const t_direct_inf* direct, // Find a source/sink RR node associated with the pins of the direct { - RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, SOURCE, from_pin_class); + RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, e_rr_type::SOURCE, from_pin_class); VTR_ASSERT(src_rr_candidate); out_src_node = src_rr_candidate; } { - RRNodeId sink_rr_candidate = node_lookup.find_node(found_layer_num, to_x, to_y, SINK, to_pin_class); + RRNodeId sink_rr_candidate = node_lookup.find_node(found_layer_num, to_x, to_y, e_rr_type::SINK, to_pin_class); VTR_ASSERT(sink_rr_candidate); out_sink_node = sink_rr_candidate; } diff --git a/vpr/src/place/grid_tile_lookup.cpp b/vpr/src/place/grid_tile_lookup.cpp index 45aad729647..aef14f286a2 100644 --- a/vpr/src/place/grid_tile_lookup.cpp +++ b/vpr/src/place/grid_tile_lookup.cpp @@ -1,4 +1,5 @@ #include "grid_tile_lookup.h" +#include "globals.h" #include "physical_types_util.h" GridTileLookup::GridTileLookup() diff --git a/vpr/src/place/grid_tile_lookup.h b/vpr/src/place/grid_tile_lookup.h index b155bf99410..74b858d6238 100644 --- a/vpr/src/place/grid_tile_lookup.h +++ b/vpr/src/place/grid_tile_lookup.h @@ -1,8 +1,11 @@ #ifndef VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ #define VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ -#include "place_util.h" -#include "globals.h" +#include +#include "physical_types.h" +#include "vtr_ndmatrix.h" + +class Region; /** * @class GridTileLookup diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index 2c97ee4f788..40376e3a187 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -8,13 +8,8 @@ #include "noc_place_checkpoint.h" #include "place_constraints.h" -#include "sat_routing.h" - -#include "vtr_math.h" #include "vtr_time.h" -#include - /** * @brief Evaluates whether a NoC router swap should be accepted or not. * If delta cost is non-positive, the move is always accepted. If the cost diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index aac91e0fd65..bcf6e3b7094 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -579,6 +580,43 @@ static t_flat_pl_loc find_centroid_loc_from_flat_placement(const t_pl_macro& pl_ if (acc_weight > 0.f) { centroid /= acc_weight; } + + // If the root cluster is constrained, project the centroid onto its + // partition region. This will move the centroid position to the closest + // position within the partition region. + ClusterBlockId head_cluster_id = pl_macro.members[0].blk_index; + if (is_cluster_constrained(head_cluster_id)) { + // Get the partition region of the head. This is the partition region + // that affects the entire macro. + const PartitionRegion& head_pr = g_vpr_ctx.floorplanning().cluster_constraints[head_cluster_id]; + // For each region, find the closest point in that region to the centroid + // and save the closest of all regions. + t_flat_pl_loc best_projected_pos = centroid; + float best_distance = std::numeric_limits::max(); + VTR_ASSERT_MSG(centroid.layer == 0, + "3D FPGAs not supported for this part of the code yet"); + for (const Region& region : head_pr.get_regions()) { + const vtr::Rect& rect = region.get_rect(); + // Note: We add 0.999 here since the partition region is in grid + // space, so it treats tile positions as having size 0x0 when + // they really are 1x1. + float proj_x = std::clamp(centroid.x, rect.xmin(), rect.xmax() + 0.999); + float proj_y = std::clamp(centroid.y, rect.ymin(), rect.ymax() + 0.999); + float dx = std::abs(proj_x - centroid.x); + float dy = std::abs(proj_y - centroid.y); + float dist = dx + dy; + if (dist < best_distance) { + best_projected_pos.x = proj_x; + best_projected_pos.y = proj_y; + best_distance = dist; + } + } + VTR_ASSERT_SAFE(best_distance != std::numeric_limits::max()); + // Return the point within the partition region that is closest to the + // original centroid. + return best_projected_pos; + } + return centroid; } @@ -742,12 +780,10 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat // floorplanning constraints and compatibility for all // members of the macro. This prevents some macros being // placed where they obviously cannot be implemented. - // Note: The check_all_legality flag is poorly named. false means - // that it WILL check all legality... t_pl_loc new_loc = t_pl_loc(grid_loc.x, grid_loc.y, new_sub_tile, grid_loc.layer_num); bool site_legal_for_macro = macro_can_be_placed(pl_macro, new_loc, - false /*check_all_legality*/, + true /*check_all_legality*/, blk_loc_registry); if (site_legal_for_macro) { // Update the best solition. @@ -976,10 +1012,10 @@ static inline void fix_IO_block_types(const t_pl_macro& pl_macro, vtr::vector_map& block_locs) { const auto& device_ctx = g_vpr_ctx.device(); - //If the user marked the IO block pad_loc_type as RANDOM, that means it should be randomly - //placed and then stay fixed to that location, which is why the macro members are marked as fixed. - const auto& type = device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer}); - if (is_io_type(type) && pad_loc_type == e_pad_loc_type::RANDOM) { + // If the user marked the IO block pad_loc_type as RANDOM, that means it should be randomly + // placed and then stay fixed to that location, which is why the macro members are marked as fixed. + const t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer}); + if (type->is_io() && pad_loc_type == e_pad_loc_type::RANDOM) { for (const t_pl_macro_member& pl_macro_member : pl_macro.members) { block_locs[pl_macro_member.blk_index].is_fixed = true; } @@ -1210,10 +1246,7 @@ bool try_place_macro(const t_pl_macro& pl_macro, return macro_placed; } - bool mac_can_be_placed = macro_can_be_placed(pl_macro, head_pos, /*check_all_legality=*/false, blk_loc_registry); - - if (mac_can_be_placed) { - // Place down the macro + if (macro_can_be_placed(pl_macro, head_pos, /*check_all_legality=*/true, blk_loc_registry)) { macro_placed = true; VTR_LOGV_DEBUG(f_placer_debug, "\t\t\t\tMacro is placed at the given location\n"); for (const t_pl_macro_member& pl_macro_member : pl_macro.members) { @@ -1594,6 +1627,7 @@ static inline void place_all_blocks_ap(enum e_pad_loc_type pad_loc_type, const FlatPlacementInfo& flat_placement_info) { const ClusteredNetlist& cluster_netlist = g_vpr_ctx.clustering().clb_nlist; const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + const auto& cluster_constraints = g_vpr_ctx.floorplanning().cluster_constraints; // Create a list of clusters to place. std::vector clusters_to_place; @@ -1615,6 +1649,7 @@ static inline void place_all_blocks_ap(enum e_pad_loc_type pad_loc_type, constexpr float macro_size_weight = 1.0f; constexpr float std_dev_weight = 4.0f; vtr::vector cluster_score(cluster_netlist.blocks().size(), 0.0f); + vtr::vector cluster_constr_area(cluster_netlist.blocks().size(), std::numeric_limits::max()); for (ClusterBlockId blk_id : cluster_netlist.blocks()) { // Compute the standard deviation of the positions of all atoms in the // given macro. This is a measure of how much the atoms "want" to be @@ -1642,9 +1677,32 @@ static inline void place_all_blocks_ap(enum e_pad_loc_type pad_loc_type, // should be placed first. cluster_score[blk_id] = (macro_size_weight * normalized_macro_size) + (std_dev_weight * (1.0f - normalized_std_dev)); + + // If the cluster is constrained, compute how much area its constrained + // region takes up. This will be used to place "more constrained" blocks + // first. + // TODO: The cluster constrained area can be incorperated into the cost + // somehow. + if (is_cluster_constrained(blk_id)) { + const PartitionRegion& pr = cluster_constraints[blk_id]; + float area = 0.0f; + for (const Region& region : pr.get_regions()) { + const vtr::Rect region_rect = region.get_rect(); + // Note: Add 1 here since the width is in grid space (i.e. width + // of 0 means it can only be placed in 1 x coordinate). + area += (region_rect.width() + 1) * (region_rect.height() + 1); + } + cluster_constr_area[blk_id] = area; + } } std::stable_sort(clusters_to_place.begin(), clusters_to_place.end(), [&](ClusterBlockId lhs, ClusterBlockId rhs) { - // Sort list such that higher score clusters are placed first. + // Sort the list such that: + // 1) Clusters that are constrained to less area on the device are placed + // first. + if (cluster_constr_area[lhs] != cluster_constr_area[rhs]) { + return cluster_constr_area[lhs] < cluster_constr_area[rhs]; + } + // 2) Higher score clusters are placed first. return cluster_score[lhs] > cluster_score[rhs]; }); diff --git a/vpr/src/place/move_transactions.h b/vpr/src/place/move_transactions.h index ce1095c365d..78cde262e54 100644 --- a/vpr/src/place/move_transactions.h +++ b/vpr/src/place/move_transactions.h @@ -2,7 +2,6 @@ #define VPR_MOVE_TRANSACTIONS_H #include "vpr_types.h" -#include "clustered_netlist_utils.h" class BlkLocRegistry; class GridBlock; diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index f3cc457d0bb..88dd5505777 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -7,9 +7,6 @@ #include "place_macro.h" #include "vtr_random.h" -#include "draw_debug.h" -#include "draw.h" - #include "place_constraints.h" #include "placer_state.h" #include "PlacerCriticalities.h" diff --git a/vpr/src/place/noc_place_checkpoint.h b/vpr/src/place/noc_place_checkpoint.h index e794e3e2d65..963acee281c 100644 --- a/vpr/src/place/noc_place_checkpoint.h +++ b/vpr/src/place/noc_place_checkpoint.h @@ -1,8 +1,6 @@ #ifndef VTR_ROUTERPLACEMENTCHECKPOINT_H #define VTR_ROUTERPLACEMENTCHECKPOINT_H -class NocCostHandler; - /** * @brief NoC router placement checkpoint * @@ -20,6 +18,8 @@ class NocCostHandler; #include "vpr_types.h" #include "place_util.h" +class NocCostHandler; + /** * @brief A NoC router placement checkpoint * diff --git a/vpr/src/place/place.cpp b/vpr/src/place/place.cpp index 646e2a6deed..39d6cd24f82 100644 --- a/vpr/src/place/place.cpp +++ b/vpr/src/place/place.cpp @@ -33,8 +33,8 @@ void try_place(const Netlist<>& net_list, const t_router_opts& router_opts, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, - t_chan_width_dist chan_width_dist, - t_det_routing_arch* det_routing_arch, + const t_chan_width_dist& chan_width_dist, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, const FlatPlacementInfo& flat_placement_info, diff --git a/vpr/src/place/place.h b/vpr/src/place/place.h index c7c3d9f8758..235dbc0042c 100644 --- a/vpr/src/place/place.h +++ b/vpr/src/place/place.h @@ -10,8 +10,8 @@ void try_place(const Netlist<>& net_list, const t_router_opts& router_opts, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, - t_chan_width_dist chan_width_dist, - t_det_routing_arch* det_routing_arch, + const t_chan_width_dist& chan_width_dist, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, const FlatPlacementInfo& flat_placement_info, diff --git a/vpr/src/place/place_checkpoint.h b/vpr/src/place/place_checkpoint.h index 9a3fe76d5d8..86700c9dd44 100644 --- a/vpr/src/place/place_checkpoint.h +++ b/vpr/src/place/place_checkpoint.h @@ -1,11 +1,9 @@ #ifndef PLACE_CHECKPOINT_H #define PLACE_CHECKPOINT_H -#include "vtr_util.h" #include "vpr_types.h" #include "vtr_vector_map.h" #include "place_util.h" -#include "globals.h" #include "timing_info.h" #include "place_delay_model.h" diff --git a/vpr/src/place/place_constraints.h b/vpr/src/place/place_constraints.h index 77952144795..b1d2b5a556f 100644 --- a/vpr/src/place/place_constraints.h +++ b/vpr/src/place/place_constraints.h @@ -8,9 +8,9 @@ * Created on: Mar. 1, 2021 * Author: khalid88 */ +#include "globals.h" #include "move_transactions.h" #include "region.h" -#include "clustered_netlist_utils.h" #include "partition_region.h" #include "place_macro.h" #include "grid_tile_lookup.h" diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index 4a8ccb62666..b4ddc01c247 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -59,7 +59,7 @@ static bool try_combine_macros(std::vector>& pl_macr * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * * Otherwise, mark down all the pins in that port. */ static void mark_direct_of_ports(int idirect, - int direct_type, + e_pin_type direct_type, std::string_view pb_type_name, std::string_view port_name, int end_pin_index, @@ -67,7 +67,7 @@ static void mark_direct_of_ports(int idirect, std::string_view src_string, int line, std::vector>& idirect_from_blk_pin, - std::vector>& direct_type_from_blk_pin, + std::vector>& direct_type_from_blk_pin, const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin); @@ -82,8 +82,8 @@ static void mark_direct_of_pins(int start_pin_index, int iport, std::vector>& idirect_from_blk_pin, int idirect, - std::vector>& direct_type_from_blk_pin, - int direct_type, + std::vector>& direct_type_from_blk_pin, + e_pin_type direct_type, int line, std::string_view src_string, const std::vector& physical_tile_types, @@ -200,7 +200,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, ClusterNetId to_net_id = clb_nlist.block_net(blk_id, to_iblk_pin); int to_idirect = idirect_from_blk_pin_[physical_tile->index][to_physical_pin]; - int to_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][to_physical_pin]; + e_pin_type to_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][to_physical_pin]; // Identify potential macro head blocks (i.e. start of a macro) // @@ -211,20 +211,20 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // Note that the restriction that constant nets are not driven from another direct ensures that // blocks in the middle of a chain with internal constant signals are not detected as potential // head blocks. - if (to_src_or_sink == SINK && to_idirect != OPEN + if (to_src_or_sink == RECEIVER && to_idirect != OPEN && (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id, atom_lookup, atom_nlist) && !net_is_driven_by_direct_(to_net_id, clb_nlist)))) { for (int from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); ClusterNetId from_net_id = clb_nlist.block_net(blk_id, from_iblk_pin); int from_idirect = idirect_from_blk_pin_[physical_tile->index][from_physical_pin]; - int from_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][from_physical_pin]; + e_pin_type from_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][from_physical_pin]; // Confirm whether this is a head macro // // The output SOURCE (from_pin) of a true head macro will: // * drive another block with the same direct connection - if (from_src_or_sink == SOURCE && to_idirect == from_idirect && from_net_id != ClusterNetId::INVALID()) { + if (from_src_or_sink == DRIVER && to_idirect == from_idirect && from_net_id != ClusterNetId::INVALID()) { // Mark down that this is the first block in the macro pl_macro_member_blk_num_of_this_blk[0] = blk_id; pl_macro_idirect[num_macro] = to_idirect; @@ -249,7 +249,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // Assume that the from_iblk_pin index is the same for the next block VTR_ASSERT(idirect_from_blk_pin_[physical_tile->index][from_physical_pin] == from_idirect - && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == SOURCE); + && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == DRIVER); next_net_id = clb_nlist.block_net(next_blk_id, from_iblk_pin); // Mark down this block as a member of the macro @@ -448,7 +448,7 @@ void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector>& idirect_from_blk_pin, - std::vector>& direct_type_from_blk_pin, + std::vector>& direct_type_from_blk_pin, const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin) { /* Go through all the ports in all the blocks to find the port that has the same * @@ -536,8 +536,8 @@ static void mark_direct_of_pins(int start_pin_index, int iport, std::vector>& idirect_from_blk_pin, int idirect, - std::vector>& direct_type_from_blk_pin, - int direct_type, + std::vector>& direct_type_from_blk_pin, + e_pin_type direct_type, int line, std::string_view src_string, const std::vector& physical_tile_types, @@ -630,10 +630,10 @@ void PlaceMacros::write_place_macros_(std::string filename, int itype = type.index; for (int ipin = 0; ipin < type.num_pins; ++ipin) { if (idirect_from_blk_pin_[itype][ipin] != OPEN) { - if (direct_type_from_blk_pin_[itype][ipin] == SOURCE) { + if (direct_type_from_blk_pin_[itype][ipin] == DRIVER) { fprintf(f, "%-9s %-9d true SOURCE \n", type.name.c_str(), ipin); } else { - VTR_ASSERT(direct_type_from_blk_pin_[itype][ipin] == SINK); + VTR_ASSERT(direct_type_from_blk_pin_[itype][ipin] == RECEIVER); fprintf(f, "%-9s %-9d true SINK \n", type.name.c_str(), ipin); } } else { diff --git a/vpr/src/place/place_macro.h b/vpr/src/place/place_macro.h index 0b5988c7c61..188fbbdab46 100644 --- a/vpr/src/place/place_macro.h +++ b/vpr/src/place/place_macro.h @@ -208,12 +208,12 @@ class PlaceMacros { std::vector> idirect_from_blk_pin_; /** - * @brief This array stores the value SOURCE if the pin is the from_pin, - * SINK if the pin is the to_pin in the direct connection as specified in the arch file, + * @brief This array stores the value DRIVER if the pin is the from_pin, + * RECEIVER if the pin is the to_pin in the direct connection as specified in the arch file, * OPEN (-1) is stored for pins that could not be part of a direct chain connection. * [0...device_ctx.num_block_types-1][0...num_pins-1] */ - std::vector> direct_type_from_blk_pin_; + std::vector> direct_type_from_blk_pin_; /** * @brief Maps a blk_num to the corresponding macro index. diff --git a/vpr/src/place/place_util.cpp b/vpr/src/place/place_util.cpp index 1ac0899fbdf..7fdf3383a06 100644 --- a/vpr/src/place/place_util.cpp +++ b/vpr/src/place/place_util.cpp @@ -191,7 +191,7 @@ bool macro_can_be_placed(const t_pl_macro& pl_macro, * floorplan constraint is not supported by analytical placement yet, * hence, if macro_can_be_placed is called from analytical placer, no further actions are required. */ - if (check_all_legality) { + if (!check_all_legality) { continue; } diff --git a/vpr/src/place/place_util.h b/vpr/src/place/place_util.h index 14cf44455c6..f21761b9e31 100644 --- a/vpr/src/place/place_util.h +++ b/vpr/src/place/place_util.h @@ -7,11 +7,7 @@ #ifndef PLACE_UTIL_H #define PLACE_UTIL_H -#include - #include "vpr_types.h" -#include "vtr_util.h" -#include "vtr_vector_map.h" #include "globals.h" /** @@ -261,7 +257,7 @@ inline bool is_loc_on_chip(t_physical_tile_loc loc) { * determines whether the routine should check all legality constraint * Analytic placer does not require to check block's capacity or * floorplanning constraints. However, initial placement or SA-based approach - * require to check for all legality constraints. + * require checking all legality constraints. * @param blk_loc_registry Placement block location information. * */ diff --git a/vpr/src/place/placement_log_printer.cpp b/vpr/src/place/placement_log_printer.cpp index 1ce8c239dc7..f4fccecbcc1 100644 --- a/vpr/src/place/placement_log_printer.cpp +++ b/vpr/src/place/placement_log_printer.cpp @@ -314,8 +314,9 @@ void generate_post_place_timing_reports(const t_placer_opts& placer_opts, const BlkLocRegistry& blk_loc_registry) { const auto& timing_ctx = g_vpr_ctx.timing(); const auto& atom_ctx = g_vpr_ctx.atom(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); diff --git a/vpr/src/place/placement_log_printer.h b/vpr/src/place/placement_log_printer.h index e349fbe051f..56d18835078 100644 --- a/vpr/src/place/placement_log_printer.h +++ b/vpr/src/place/placement_log_printer.h @@ -10,7 +10,6 @@ #pragma once -#include #include #include "timing_info_fwd.h" diff --git a/vpr/src/place/placer.cpp b/vpr/src/place/placer.cpp index d850fb0144b..b2ea7078e95 100644 --- a/vpr/src/place/placer.cpp +++ b/vpr/src/place/placer.cpp @@ -11,7 +11,6 @@ #include "vtr_time.h" #include "draw.h" #include "read_place.h" -#include "analytic_placer.h" #include "initial_placement.h" #include "load_flat_place.h" #include "concrete_timing_info.h" @@ -94,19 +93,6 @@ Placer::Placer(const Netlist<>& net_list, print_place(nullptr, nullptr, placer_opts.write_initial_place_file.c_str(), placer_state_.block_locs()); } -#ifdef ENABLE_ANALYTIC_PLACE - /* - * Cluster-level Analytic Placer: - * Passes in the initial_placement via vpr_context, and passes its placement back via locations marked on - * both the clb_netlist and the gird. - * Most of anneal is disabled later by setting initial temperature to 0 and only further optimizes in quench - */ - if (placer_opts.enable_analytic_placer) { - AnalyticPlacer{blk_loc_registry, place_macros}.ap_place(); - } - -#endif /* ENABLE_ANALYTIC_PLACE */ - // Update physical pin values for (const ClusterBlockId block_id : cluster_ctx.clb_nlist.blocks()) { blk_loc_registry.place_sync_external_block_connections(block_id); @@ -291,12 +277,6 @@ void Placer::place() { const auto& timing_ctx = g_vpr_ctx.timing(); const auto& cluster_ctx = g_vpr_ctx.clustering(); bool analytic_place_enabled = false; -#ifdef ENABLE_ANALYTIC_PLACE - // Cluster-level analytic placer: when enabled, skip most of the annealing and go straight to quench - if (placer_opts_.enable_analytic_placer) { - analytic_place_enabled = true; - } -#endif if (!analytic_place_enabled && !quench_only_) { // Table header diff --git a/vpr/src/place/placer_breakpoint.cpp b/vpr/src/place/placer_breakpoint.cpp index d71430f2090..4ca967ab85d 100644 --- a/vpr/src/place/placer_breakpoint.cpp +++ b/vpr/src/place/placer_breakpoint.cpp @@ -1,4 +1,9 @@ #include "placer_breakpoint.h" +#include "breakpoint_state_globals.h" +#include "draw.h" +#include "draw_debug.h" +#include "draw_global.h" +#include "vtr_expr_eval.h" //map of the available move types and their corresponding type number std::map available_move_types = { diff --git a/vpr/src/place/placer_breakpoint.h b/vpr/src/place/placer_breakpoint.h index 159e9c40b38..d23e927ae7f 100644 --- a/vpr/src/place/placer_breakpoint.h +++ b/vpr/src/place/placer_breakpoint.h @@ -1,11 +1,7 @@ #pragma once -#include "globals.h" -#include "vpr_types.h" #include "move_utils.h" -#include "breakpoint.h" -#include "draw.h" //transforms the vector moved_blocks to a vector of ints and adds it in glob_breakpoint_state void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected); diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 669133f5a01..92e24020675 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -7,7 +7,7 @@ * or email: * vtr.power.estimation@gmail.com * - * If you are using power estimation for your researach please cite: + * If you are using power estimation for your research please cite: * * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation * for Diverse FPGA Architectures. In International Conference on @@ -65,7 +65,7 @@ static t_rr_node_power* rr_node_power; /************************* Function Declarations ********************/ /* Routing */ static void power_usage_routing(t_power_usage* power_usage, - const t_det_routing_arch* routing_arch, + const t_det_routing_arch& routing_arch, bool is_flat); /* Tiles */ @@ -111,7 +111,7 @@ void power_init_pb_pins_rec(t_pb_graph_node* pb_node); void power_uninit_pb_pins_rec(t_pb_graph_node* pb_node); void power_pb_pins_init(); void power_pb_pins_uninit(); -void power_routing_init(const t_det_routing_arch* routing_arch); +void power_routing_init(const t_det_routing_arch& routing_arch); /************************* FUNCTION DEFINITIONS *********************/ /** @@ -133,7 +133,7 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra auto& device_ctx = g_vpr_ctx.device(); auto& power_ctx = g_vpr_ctx.power(); - if (strcmp(pb_graph_node->pb_type->blif_model, MODEL_NAMES) == 0) { + if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_NAMES) == 0) { /* LUT */ std::string SRAM_values; @@ -174,7 +174,7 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra power_add_usage(power_usage, &sub_power_usage); delete[] input_probabilities; delete[] input_densities; - } else if (strcmp(pb_graph_node->pb_type->blif_model, MODEL_LATCH) == 0) { + } else if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_LATCH) == 0) { /* Flip-Flop */ t_pb_graph_pin* D_pin = &pb_graph_node->input_pins[0][0]; @@ -783,7 +783,7 @@ static void dealloc_mux_graph_rec(t_mux_node* node) { * Calculates the power of the entire routing fabric (not local routing */ static void power_usage_routing(t_power_usage* power_usage, - const t_det_routing_arch* routing_arch, + const t_det_routing_arch& routing_arch, bool is_flat) { auto& power_ctx = g_vpr_ctx.power(); auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -835,9 +835,9 @@ static void power_usage_routing(t_power_usage* power_usage, t_rr_node_power* next_node_power = &rr_node_power[next_node_id]; switch (rr_graph.node_type(RRNodeId(next_node_id))) { - case CHANX: - case CHANY: - case IPIN: { + case e_rr_type::CHANX: + case e_rr_type::CHANY: + case e_rr_type::IPIN: { if (next_node_power->net_num == node_power->net_num) { next_node_power->selected_input = next_node_power->num_inputs; } @@ -875,12 +875,12 @@ static void power_usage_routing(t_power_usage* power_usage, const t_edge_size node_fan_in = rr_graph.node_fan_in(rr_id); switch (rr_graph.node_type(rr_id)) { - case SOURCE: - case SINK: - case OPIN: + case e_rr_type::SOURCE: + case e_rr_type::SINK: + case e_rr_type::OPIN: /* No power usage for these types */ break; - case IPIN: + case e_rr_type::IPIN: /* This is part of the connectionbox. The connection box is comprised of: * - Driver (accounted for at end of CHANX/Y - see below) * - Multiplexor */ @@ -901,8 +901,8 @@ static void power_usage_routing(t_power_usage* power_usage, POWER_COMPONENT_ROUTE_CB); } break; - case CHANX: - case CHANY: { + case e_rr_type::CHANX: + case e_rr_type::CHANY: { /* This is a wire driven by a switchbox, which includes: * - The Multiplexor at the beginning of the wire * - A buffer, after the mux to drive the wire @@ -912,9 +912,9 @@ static void power_usage_routing(t_power_usage* power_usage, VTR_ASSERT(node_power->in_prob); wire_length = 0; - if (rr_graph.node_type(rr_id) == CHANX) { + if (rr_graph.node_type(rr_id) == e_rr_type::CHANX) { wire_length = rr_graph.node_xhigh(rr_id) - rr_graph.node_xlow(rr_id) + 1; - } else if (rr_graph.node_type(rr_id) == CHANY) { + } else if (rr_graph.node_type(rr_id) == e_rr_type::CHANY) { wire_length = rr_graph.node_yhigh(rr_id) - rr_graph.node_ylow(rr_id) + 1; } int seg_index = device_ctx.rr_indexed_data[rr_graph.node_cost_index(rr_id)].seg_index; @@ -991,9 +991,9 @@ static void power_usage_routing(t_power_usage* power_usage, connectionbox_fanout = 0; switchbox_fanout = 0; for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) { - if (rr_graph.edge_switch(rr_id, iedge) == routing_arch->wire_to_rr_ipin_switch) { + if (rr_graph.edge_switch(rr_id, iedge) == routing_arch.wire_to_rr_ipin_switch) { connectionbox_fanout++; - } else if (rr_graph.edge_switch(rr_id, iedge) == routing_arch->delayless_switch) { + } else if (rr_graph.edge_switch(rr_id, iedge) == routing_arch.delayless_switch) { /* Do nothing */ } else { switchbox_fanout++; @@ -1183,7 +1183,7 @@ void power_pb_pins_uninit() { } } -void power_routing_init(const t_det_routing_arch* routing_arch) { +void power_routing_init(const t_det_routing_arch& routing_arch) { t_edge_size max_fanin; t_edge_size max_IPIN_fanin; t_edge_size max_seg_to_IPIN_fanout; @@ -1222,7 +1222,7 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { const t_edge_size node_fan_in = rr_graph.node_fan_in(rr_node_idx); switch (rr_graph.node_type(rr_node_idx)) { - case IPIN: + case e_rr_type::IPIN: max_IPIN_fanin = std::max(max_IPIN_fanin, node_fan_in); max_fanin = std::max(max_fanin, node_fan_in); @@ -1234,12 +1234,12 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { } break; - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_node_idx); iedge++) { - if (rr_graph.edge_switch(rr_node_idx, iedge) == routing_arch->wire_to_rr_ipin_switch) { + if (rr_graph.edge_switch(rr_node_idx, iedge) == routing_arch.wire_to_rr_ipin_switch) { fanout_to_IPIN++; - } else if (rr_graph.edge_switch(rr_node_idx, iedge) != routing_arch->delayless_switch) { + } else if (rr_graph.edge_switch(rr_node_idx, iedge) != routing_arch.delayless_switch) { fanout_to_seg++; } } @@ -1287,8 +1287,8 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) { switch (rr_graph.node_type(rr_node_idx)) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: if (rr_graph.num_edges(rr_node_idx) > max_seg_fanout) { max_seg_fanout = rr_graph.num_edges(rr_node_idx); } @@ -1307,7 +1307,7 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { bool power_init(const char* power_out_filepath, const char* cmos_tech_behavior_filepath, const t_arch* arch, - const t_det_routing_arch* routing_arch) { + const t_det_routing_arch& routing_arch) { auto& power_ctx = g_vpr_ctx.mutable_power(); bool error = false; @@ -1375,9 +1375,9 @@ bool power_uninit() { t_rr_node_power* node_power = &rr_node_power[(size_t)rr_id]; switch (rr_graph.node_type(rr_id)) { - case CHANX: - case CHANY: - case IPIN: + case e_rr_type::CHANX: + case e_rr_type::CHANY: + case e_rr_type::IPIN: delete[] node_power->in_dens; delete[] node_power->in_prob; break; @@ -1389,8 +1389,7 @@ bool power_uninit() { delete[] rr_node_power; /* Free mux architectures */ - for (std::map::iterator it = power_ctx.commonly_used->mux_info.begin(); - it != power_ctx.commonly_used->mux_info.end(); it++) { + for (auto it = power_ctx.commonly_used->mux_info.begin(); it != power_ctx.commonly_used->mux_info.end(); it++) { t_power_mux_info* mux_info = it->second; for (mux_size = 1; mux_size <= mux_info->mux_arch_max_size; mux_size++) { dealloc_mux_graph(mux_info->mux_arch[mux_size].mux_graph_head); @@ -1713,7 +1712,7 @@ static void power_print_summary(FILE* fp, const t_vpr_setup& vpr_setup) { * and prints it to the output file * - run_time_s: (Return value) The total runtime in seconds (us accuracy) */ -e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch* routing_arch) { +e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch& routing_arch) { t_power_usage total_power; t_power_usage sub_power_usage; clock_t t_start; @@ -1725,7 +1724,7 @@ e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, co power_zero_usage(&total_power); - if (routing_arch->directionality == BI_DIRECTIONAL) { + if (routing_arch.directionality == BI_DIRECTIONAL) { power_log_msg(POWER_LOG_ERROR, "Cannot calculate routing power for bi-directional architectures"); return POWER_RET_CODE_ERRORS; diff --git a/vpr/src/power/power.h b/vpr/src/power/power.h index 42191fafe2d..36630921b03 100644 --- a/vpr/src/power/power.h +++ b/vpr/src/power/power.h @@ -1,3 +1,5 @@ +#pragma once + /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -19,9 +21,6 @@ * This is the top-level file for power estimation in VTR */ -#ifndef __POWER_H__ -#define __POWER_H__ - /************************* INCLUDES *********************************/ #include @@ -308,11 +307,9 @@ struct t_mux_node { bool power_init(const char* power_out_filepath, const char* cmos_tech_behavior_filepath, const t_arch* arch, - const t_det_routing_arch* routing_arch); + const t_det_routing_arch& routing_arch); bool power_uninit(); /* Top-Level Function */ -e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch* routing_arch); - -#endif /* __POWER_H__ */ +e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, const t_arch* arch, const t_det_routing_arch& routing_arch); diff --git a/vpr/src/power/power_callibrate.h b/vpr/src/power/power_callibrate.h index eb387b4e3d9..48852da4ea9 100644 --- a/vpr/src/power/power_callibrate.h +++ b/vpr/src/power/power_callibrate.h @@ -19,8 +19,7 @@ * againt SPICE. */ -#ifndef __POWER_MISC_H__ -#define __POWER_MISC_H__ +#pragma once /************************* INCLUDES *********************************/ #include "power.h" @@ -49,4 +48,3 @@ float power_usage_mux_for_callibration(int num_inputs, float transistor_size); float power_usage_lut_for_callibration(int num_inputs, float transistor_size); float power_usage_ff_for_callibration(int num_inputs, float transistor_size); void power_print_callibration(); -#endif diff --git a/vpr/src/power/power_sizing.cpp b/vpr/src/power/power_sizing.cpp index 914bf13afde..37f06028dc3 100644 --- a/vpr/src/power/power_sizing.cpp +++ b/vpr/src/power/power_sizing.cpp @@ -24,6 +24,8 @@ #include #include +#include "arch_types.h" +#include "logic_types.h" #include "vtr_util.h" #include "vtr_assert.h" #include "vtr_memory.h" @@ -311,7 +313,7 @@ static double power_count_transistors_pb_node(t_pb_graph_node* pb_node) { t_pb_type* pb_type = pb_node->pb_type; /* Check if this is a leaf node, or whether it has children */ - if (pb_type->num_modes == 0) { + if (pb_type->is_primitive()) { /* Leaf node */ tc_interc_max = 0; tc_children_max = power_count_transistors_primitive(pb_type); @@ -404,11 +406,11 @@ static double power_count_transistors_primitive(t_pb_type* pb_type) { auto& power_ctx = g_vpr_ctx.power(); - if (strcmp(pb_type->blif_model, MODEL_NAMES) == 0) { + if (strcmp(pb_type->blif_model, LogicalModels::MODEL_NAMES) == 0) { /* LUT */ transistor_cnt = power_count_transistors_LUT(pb_type->num_input_pins, power_ctx.arch->LUT_transistor_size); - } else if (strcmp(pb_type->blif_model, MODEL_LATCH) == 0) { + } else if (strcmp(pb_type->blif_model, LogicalModels::MODEL_LATCH) == 0) { /* Latch */ transistor_cnt = power_count_transistors_FF(power_ctx.arch->FF_size); } else { diff --git a/vpr/src/route/DecompNetlistRouter.h b/vpr/src/route/DecompNetlistRouter.h index a41d656c240..e670bc5597d 100644 --- a/vpr/src/route/DecompNetlistRouter.h +++ b/vpr/src/route/DecompNetlistRouter.h @@ -85,11 +85,11 @@ class DecompNetlistRouter : public NetlistRouter { /** A single task to route nets inside a PartitionTree node and add tasks for its child nodes to task group \p g. */ void route_partition_tree_node(tbb::task_group& g, PartitionTreeNode& node); - ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + SerialConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - return ConnectionRouter( + return SerialConnectionRouter( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -101,8 +101,8 @@ class DecompNetlistRouter : public NetlistRouter { } /* Context fields. Most of them will be forwarded to route_net (see route_net.tpp) */ - /** Per-thread storage for ConnectionRouters. */ - tbb::enumerable_thread_specific> _routers_th; + /** Per-thread storage for SerialConnectionRouter. */ + tbb::enumerable_thread_specific> _routers_th; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/DecompNetlistRouter.tpp b/vpr/src/route/DecompNetlistRouter.tpp index 228cf428ef6..21d800ec0b3 100644 --- a/vpr/src/route/DecompNetlistRouter.tpp +++ b/vpr/src/route/DecompNetlistRouter.tpp @@ -204,12 +204,12 @@ void DecompNetlistRouter::route_partition_tree_node(tbb::task_group& g route_ctx.route_bb[net_id], false); if (!flags.success && !flags.retry_with_full_bb) { - /* Disconnected RRG and ConnectionRouter doesn't think growing the BB will work */ + /* Disconnected RRG and SerialConnectionRouter doesn't think growing the BB will work */ _results_th.local().is_routable = false; return; } if (flags.retry_with_full_bb) { - /* ConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ + /*SerialConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ route_ctx.route_bb[net_id] = full_device_bb(); _results_th.local().bb_updated_nets.push_back(net_id); /* Disable decomposition for nets like this: they're already problematic */ diff --git a/vpr/src/route/NestedNetlistRouter.h b/vpr/src/route/NestedNetlistRouter.h index 6870842af8f..e776d0a42da 100644 --- a/vpr/src/route/NestedNetlistRouter.h +++ b/vpr/src/route/NestedNetlistRouter.h @@ -4,6 +4,9 @@ #include "netlist_routers.h" #include "vtr_optional.h" #include "vtr_thread_pool.h" +#include "serial_connection_router.h" +#include "parallel_connection_router.h" +#include #include /* Add cmd line option for this later */ @@ -67,19 +70,38 @@ class NestedNetlistRouter : public NetlistRouter { /** Route all nets in a PartitionTree node and add its children to the task queue. */ void route_partition_tree_node(PartitionTreeNode& node); - ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + std::unique_ptr _make_router(const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - return ConnectionRouter( - device_ctx.grid, - *router_lookahead, - device_ctx.rr_graph.rr_nodes(), - &device_ctx.rr_graph, - device_ctx.rr_rc_data, - device_ctx.rr_graph.rr_switch(), - route_ctx.rr_node_route_inf, - is_flat); + if (!router_opts.enable_parallel_connection_router) { + // Serial Connection Router + return std::make_unique>( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat); + } else { + // Parallel Connection Router + return std::make_unique>( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat, + router_opts.multi_queue_num_threads, + router_opts.multi_queue_num_queues, + router_opts.multi_queue_direct_draining); + } } /* Context fields. Most of them will be forwarded to route_net (see route_net.tpp) */ @@ -109,19 +131,19 @@ class NestedNetlistRouter : public NetlistRouter { /* Thread-local storage. * These are maps because thread::id is a random integer instead of 1, 2, ... */ - std::unordered_map> _routers_th; + std::unordered_map> _routers_th; std::unordered_map _results_th; std::mutex _storage_mutex; /** Get a thread-local ConnectionRouter. We lock the id->router lookup, but this is * accessed once per partition so the overhead should be small */ - ConnectionRouter& get_thread_router() { + ConnectionRouterInterface& get_thread_router() { auto id = std::this_thread::get_id(); std::lock_guard lock(_storage_mutex); if (!_routers_th.count(id)) { - _routers_th.emplace(id, _make_router(_router_lookahead, _is_flat)); + _routers_th.emplace(id, _make_router(_router_lookahead, _router_opts, _is_flat)); } - return _routers_th.at(id); + return *_routers_th.at(id); } RouteIterResults& get_thread_results() { diff --git a/vpr/src/route/NestedNetlistRouter.tpp b/vpr/src/route/NestedNetlistRouter.tpp index 333be28ea3b..ec4b1fe0aa6 100644 --- a/vpr/src/route/NestedNetlistRouter.tpp +++ b/vpr/src/route/NestedNetlistRouter.tpp @@ -66,10 +66,9 @@ void NestedNetlistRouter::route_partition_tree_node(PartitionTreeNode& /* Route all nets in this node serially */ for (auto net_id : nets) { auto& results = get_thread_results(); - auto& router = get_thread_router(); auto flags = route_net( - router, + get_thread_router(), _net_list, net_id, _itry, @@ -131,7 +130,7 @@ void NestedNetlistRouter::handle_bb_updated_nets(const std::vector void NestedNetlistRouter::set_rcv_enabled(bool x) { for (auto& [_, router] : _routers_th) { - router.set_rcv_enabled(x); + router->set_rcv_enabled(x); } } diff --git a/vpr/src/route/ParallelNetlistRouter.h b/vpr/src/route/ParallelNetlistRouter.h index e77fdf8344e..68b240321b2 100644 --- a/vpr/src/route/ParallelNetlistRouter.h +++ b/vpr/src/route/ParallelNetlistRouter.h @@ -15,7 +15,7 @@ #include /** Parallel impl for NetlistRouter. - * Holds enough context members to glue together ConnectionRouter and net routing functions, + * Holds enough context members to glue together SerialConnectionRouter and net routing functions, * such as \ref route_net. Keeps the members in thread-local storage where needed, * i.e. ConnectionRouters and RouteIterResults-es. * See \ref route_net. */ @@ -62,11 +62,11 @@ class ParallelNetlistRouter : public NetlistRouter { /** A single task to route nets inside a PartitionTree node and add tasks for its child nodes to task group \p g. */ void route_partition_tree_node(tbb::task_group& g, PartitionTreeNode& node); - ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + SerialConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - return ConnectionRouter( + return SerialConnectionRouter( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -79,7 +79,7 @@ class ParallelNetlistRouter : public NetlistRouter { /* Context fields. Most of them will be forwarded to route_net (see route_net.tpp) */ /** Per-thread storage for ConnectionRouters. */ - tbb::enumerable_thread_specific> _routers_th; + tbb::enumerable_thread_specific> _routers_th; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/ParallelNetlistRouter.tpp b/vpr/src/route/ParallelNetlistRouter.tpp index c845be8518d..dfdbac0cc29 100644 --- a/vpr/src/route/ParallelNetlistRouter.tpp +++ b/vpr/src/route/ParallelNetlistRouter.tpp @@ -79,12 +79,12 @@ void ParallelNetlistRouter::route_partition_tree_node(tbb::task_group& route_ctx.route_bb[net_id]); if (!flags.success && !flags.retry_with_full_bb) { - /* Disconnected RRG and ConnectionRouter doesn't think growing the BB will work */ + /* Disconnected RRG and SerialConnectionRouter doesn't think growing the BB will work */ _results_th.local().is_routable = false; return; } if (flags.retry_with_full_bb) { - /* ConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ + /* SerialConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ route_ctx.route_bb[net_id] = full_device_bb(); _results_th.local().bb_updated_nets.push_back(net_id); continue; diff --git a/vpr/src/route/SerialNetlistRouter.h b/vpr/src/route/SerialNetlistRouter.h index 352de125b68..d56414d00af 100644 --- a/vpr/src/route/SerialNetlistRouter.h +++ b/vpr/src/route/SerialNetlistRouter.h @@ -3,6 +3,8 @@ /** @file Serial case for \ref NetlistRouter: just loop through nets */ #include "netlist_routers.h" +#include "serial_connection_router.h" +#include "parallel_connection_router.h" template class SerialNetlistRouter : public NetlistRouter { @@ -20,7 +22,7 @@ class SerialNetlistRouter : public NetlistRouter { const RoutingPredictor& routing_predictor, const vtr::vector>>& choking_spots, bool is_flat) - : _router(_make_router(router_lookahead, is_flat)) + : _router(_make_router(router_lookahead, router_opts, is_flat)) , _net_list(net_list) , _router_opts(router_opts) , _connections_inf(connections_inf) @@ -40,22 +42,41 @@ class SerialNetlistRouter : public NetlistRouter { void set_timing_info(std::shared_ptr timing_info); private: - ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + std::unique_ptr _make_router(const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); - return ConnectionRouter( - device_ctx.grid, - *router_lookahead, - device_ctx.rr_graph.rr_nodes(), - &device_ctx.rr_graph, - device_ctx.rr_rc_data, - device_ctx.rr_graph.rr_switch(), - route_ctx.rr_node_route_inf, - is_flat); + if (!router_opts.enable_parallel_connection_router) { + // Serial Connection Router + return std::make_unique>( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat); + } else { + // Parallel Connection Router + return std::make_unique>( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat, + router_opts.multi_queue_num_threads, + router_opts.multi_queue_num_queues, + router_opts.multi_queue_direct_draining); + } } /* Context fields */ - ConnectionRouter _router; + std::unique_ptr _router; const Netlist<>& _net_list; const t_router_opts& _router_opts; CBRR& _connections_inf; diff --git a/vpr/src/route/SerialNetlistRouter.tpp b/vpr/src/route/SerialNetlistRouter.tpp index 63497d7d394..b84acfbd58f 100644 --- a/vpr/src/route/SerialNetlistRouter.tpp +++ b/vpr/src/route/SerialNetlistRouter.tpp @@ -22,7 +22,7 @@ inline RouteIterResults SerialNetlistRouter::route_netlist(int itry, f for (size_t inet = 0; inet < sorted_nets.size(); inet++) { ParentNetId net_id = sorted_nets[inet]; NetResultFlags flags = route_net( - _router, + *_router, _net_list, net_id, itry, @@ -42,7 +42,7 @@ inline RouteIterResults SerialNetlistRouter::route_netlist(int itry, f route_ctx.route_bb[net_id]); if (!flags.success && !flags.retry_with_full_bb) { - /* Disconnected RRG and ConnectionRouter doesn't think growing the BB will work */ + /* Disconnected RRG and SerialConnectionRouter doesn't think growing the BB will work */ out.is_routable = false; return out; } @@ -74,7 +74,7 @@ void SerialNetlistRouter::handle_bb_updated_nets(const std::vector void SerialNetlistRouter::set_rcv_enabled(bool x) { - _router.set_rcv_enabled(x); + _router->set_rcv_enabled(x); } template diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 6f20d2e873d..71c78a2498c 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -15,11 +15,13 @@ vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, const DeviceContext& device_ctx, + const AtomContext& atom_ctx, const bool& verbose) { size_t counter = 0; vtr::ScopedStartFinishTimer timer("Annotating rr_node with routed nets"); const auto& rr_graph = device_ctx.rr_graph; + auto& atom_lookup = atom_ctx.lookup(); auto& netlist = cluster_ctx.clb_nlist; vtr::vector rr_node_nets; @@ -41,17 +43,23 @@ vtr::vector annotate_rr_node_nets(const ClusteringContex for (auto& rt_node : tree->all_nodes()) { const RRNodeId rr_node = rt_node.inode; /* Ignore source and sink nodes, they are the common node multiple starting and ending points */ - if ((SOURCE != rr_graph.node_type(rr_node)) - && (SINK != rr_graph.node_type(rr_node))) { + if ((e_rr_type::SOURCE != rr_graph.node_type(rr_node)) + && (e_rr_type::SINK != rr_graph.node_type(rr_node))) { /* Sanity check: ensure we do not revoke any net mapping * In some routing architectures, node capacity is more than 1 * which allows a node to be mapped by multiple nets * Therefore, the sanity check should focus on the nodes - * whose capacity is 1 - */ + * whose capacity is 1. + * Flat routing may create two clustered nets from a single + * atom net if the atom net ended up exiting the block through + * different pins. Those clustered nets will point to the same + * atom net routing. Ignore clashes if that is the case. */ + AtomNetId my_atom = atom_lookup.atom_net(net_id); + AtomNetId existing_atom = atom_lookup.atom_net(rr_node_nets[rr_node]); if ((rr_node_nets[rr_node]) && (1 == rr_graph.node_capacity(rr_node)) - && (net_id != rr_node_nets[rr_node])) { + && (net_id != rr_node_nets[rr_node]) + && (my_atom != existing_atom)) { VPR_FATAL_ERROR(VPR_ERROR_ANALYSIS, "Detect two nets '%s' and '%s' that are mapped to the same rr_node '%ld'!\n%s\n", netlist.net_name(net_id).c_str(), diff --git a/vpr/src/route/annotate_routing.h b/vpr/src/route/annotate_routing.h index d12bf313a74..e00be549259 100644 --- a/vpr/src/route/annotate_routing.h +++ b/vpr/src/route/annotate_routing.h @@ -12,6 +12,7 @@ *******************************************************************/ vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, const DeviceContext& device_ctx, + const AtomContext& atom_ctx, const bool& verbose); #endif diff --git a/vpr/src/route/channel_stats.cpp b/vpr/src/route/channel_stats.cpp index f95275db9f4..e0f1483d456 100644 --- a/vpr/src/route/channel_stats.cpp +++ b/vpr/src/route/channel_stats.cpp @@ -4,9 +4,9 @@ #include "globals.h" void print_channel_stats(bool is_flat) { - std::vector histogram; + const auto& device_ctx = g_vpr_ctx.device(); - auto& device_ctx = g_vpr_ctx.device(); + std::vector histogram; //Bins by 10%, with final > 1 bin histogram.emplace_back(0., 0.1); @@ -20,11 +20,11 @@ void print_channel_stats(bool is_flat) { histogram.emplace_back(0.9, 1.0); histogram.emplace_back(1.0, std::numeric_limits::infinity()); - auto chanx_usage = calculate_routing_usage(CHANX, is_flat, true); - auto chany_usage = calculate_routing_usage(CHANY, is_flat, true); + auto chanx_usage = calculate_routing_usage(e_rr_type::CHANX, is_flat, true); + auto chany_usage = calculate_routing_usage(e_rr_type::CHANY, is_flat, true); - auto chanx_avail = calculate_routing_avail(CHANX); - auto chany_avail = calculate_routing_avail(CHANY); + auto chanx_avail = calculate_routing_avail(e_rr_type::CHANX); + auto chany_avail = calculate_routing_avail(e_rr_type::CHANY); auto comp = [](const HistogramBucket& bucket, float value) { return bucket.max_value < value; diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index ab2aad9a281..ac553aae092 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -3,6 +3,7 @@ #include "physical_types_util.h" #include "route_common.h" +#include "vpr_utils.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_time.h" @@ -100,7 +101,7 @@ void check_route(const Netlist<>& net_list, recompute_occupancy_from_scratch(net_list, is_flat); const bool valid = feasible_routing(); - if (valid == false) { + if (!valid) { VPR_ERROR(VPR_ERROR_ROUTE, "Error in check_route -- routing resources are overused.\n"); } @@ -157,7 +158,7 @@ void check_route(const Netlist<>& net_list, } } - if (rr_graph.node_type(inode) == SINK) { + if (rr_graph.node_type(inode) == e_rr_type::SINK) { check_sink(net_list, inode, net_pin_index, net_id, pin_done.get()); num_sinks += 1; } @@ -171,7 +172,7 @@ void check_route(const Netlist<>& net_list, } for (size_t ipin = 0; ipin < net_list.net_pins(net_id).size(); ipin++) { - if (pin_done[ipin] == false) { + if (!pin_done[ipin]) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_route: net %zu does not connect to pin %d.\n", size_t(net_id), ipin); } @@ -200,7 +201,7 @@ static void check_sink(const Netlist<>& net_list, auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - VTR_ASSERT(rr_graph.node_type(inode) == SINK); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::SINK); if (net_pin_index == OPEN) { /* If there is no legal net pin index associated with this sink node */ VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -222,8 +223,8 @@ static void check_source(const Netlist<>& net_list, auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type rr_type = rr_graph.node_type(inode); - if (rr_type != SOURCE) { + e_rr_type rr_type = rr_graph.node_type(inode); + if (rr_type != e_rr_type::SOURCE) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_source: net %d begins with a node of type %d.\n", size_t(net_id), rr_type); } @@ -276,7 +277,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { int from_layer, from_xlow, from_ylow, to_layer, to_xlow, to_ylow, from_ptc, to_ptc, iclass; int num_adj, to_xhigh, to_yhigh, from_xhigh, from_yhigh; bool reached; - t_rr_type from_type, to_type; + e_rr_type from_type, to_type; t_physical_tile_type_ptr from_grid_type, to_grid_type; auto& device_ctx = g_vpr_ctx.device(); @@ -319,7 +320,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { // If to_node is a SINK, it could be anywhere within its containing device grid tile, and it is reasonable for // any input pins or within-cluster pins to reach it. Hence, treat its size as that of its containing tile. - if (to_type == SINK) { + if (to_type == e_rr_type::SINK) { vtr::Rect tile_bb = device_ctx.grid.get_tile_bb({to_xlow, to_ylow, to_layer}); to_xlow = tile_bb.xmin(); @@ -331,8 +332,8 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { // Layer numbers are should not be more than one layer apart for connected nodes VTR_ASSERT(abs(from_layer - to_layer) <= 1); switch (from_type) { - case SOURCE: - VTR_ASSERT(to_type == OPIN); + case e_rr_type::SOURCE: + VTR_ASSERT(to_type == e_rr_type::OPIN); //The OPIN should be contained within the bounding box of it's connected source if (from_xlow <= to_xlow @@ -349,34 +350,34 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case SINK: + case e_rr_type::SINK: /* SINKS are adjacent to not connected */ break; - case OPIN: + case e_rr_type::OPIN: from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); - if (to_type == CHANX || to_type == CHANY || to_type == MEDIUM) { + if (to_type == e_rr_type::CHANX || to_type == e_rr_type::CHANY || to_type == e_rr_type::MEDIUM) { num_adj += 1; //adjacent } else if (is_flat) { - VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster + VTR_ASSERT(to_type == e_rr_type::OPIN || to_type == e_rr_type::IPIN); // If pin is located inside a cluster return true; } else { - VTR_ASSERT(to_type == IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */ - return true; /* Special case, direct OPIN to IPIN connections need not be adjacent */ + VTR_ASSERT(to_type == e_rr_type::IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */ + return true; /* Special case, direct OPIN to IPIN connections need not be adjacent */ } break; - case IPIN: + case e_rr_type::IPIN: from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); if (is_flat) { - VTR_ASSERT(to_type == OPIN || to_type == IPIN || to_type == SINK); + VTR_ASSERT(to_type == e_rr_type::OPIN || to_type == e_rr_type::IPIN || to_type == e_rr_type::SINK); } else { - VTR_ASSERT(to_type == SINK); + VTR_ASSERT(to_type == e_rr_type::SINK); } //An IPIN should be contained within the bounding box of its connected sink's tile - if (to_type == SINK) { + if (to_type == e_rr_type::SINK) { if (from_xlow >= to_xlow && from_ylow >= to_ylow && from_xhigh <= to_xhigh @@ -403,10 +404,10 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case CHANX: - if (to_type == IPIN) { + case e_rr_type::CHANX: + if (to_type == e_rr_type::IPIN) { num_adj += 1; //adjacent - } else if (to_type == CHANX) { + } else if (to_type == e_rr_type::CHANX) { from_xhigh = rr_graph.node_xhigh(from_node); to_xhigh = rr_graph.node_xhigh(to_node); if (from_ylow == to_ylow) { @@ -428,9 +429,9 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } /* UDSD Modification by WMF End */ } - } else if (to_type == CHANY) { + } else if (to_type == e_rr_type::CHANY) { num_adj += chanx_chany_adjacent(from_node, to_node); - } else if (to_type == MEDIUM) { + } else if (to_type == e_rr_type::MEDIUM) { num_adj += 1; } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -438,10 +439,10 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case CHANY: - if (to_type == IPIN) { + case e_rr_type::CHANY: + if (to_type == e_rr_type::IPIN) { num_adj += 1; //adjacent - } else if (to_type == CHANY) { + } else if (to_type == e_rr_type::CHANY) { from_yhigh = rr_graph.node_yhigh(from_node); to_yhigh = rr_graph.node_yhigh(to_node); if (from_xlow == to_xlow) { @@ -462,9 +463,9 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } /* UDSD Modification by WMF End */ } - } else if (to_type == CHANX) { + } else if (to_type == e_rr_type::CHANX) { num_adj += chanx_chany_adjacent(to_node, from_node); - } else if (to_type == MEDIUM) { + } else if (to_type == e_rr_type::MEDIUM) { num_adj += 1; } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -472,15 +473,15 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } break; - case MEDIUM: + case e_rr_type::MEDIUM: //from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); - if (to_type == CHANX || to_type == CHANY || to_type == MEDIUM) { + if (to_type == e_rr_type::CHANX || to_type == e_rr_type::CHANY || to_type == e_rr_type::MEDIUM) { num_adj += 1; //adjacent } else if (is_flat) { - VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster + VTR_ASSERT(to_type == e_rr_type::OPIN || to_type == e_rr_type::IPIN); // If pin is located inside a cluster return true; } else { - VTR_ASSERT(to_type == IPIN); + VTR_ASSERT(to_type == e_rr_type::IPIN); num_adj += 1; } @@ -569,7 +570,7 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_ bool is_flat) { /* Checks that enough OPINs on CLBs have been set aside (used up) to make a * * legal routing if subblocks connect to OPINs directly. */ - t_rr_type rr_type; + e_rr_type rr_type; auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.device(); @@ -589,7 +590,7 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_ /* Now check that node is an OPIN of the right type. */ rr_type = rr_graph.node_type(RRNodeId(inode)); - if (rr_type != OPIN) { + if (rr_type != e_rr_type::OPIN) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_locally_used_opins: block #%lu (%s)\n" "\tClass %d local OPIN is wrong rr_type -- rr_node #%d of type %d.\n", @@ -902,7 +903,7 @@ bool StubFinder::RecurseTree(const RouteTreeNode& rt_node) { if (rt_node.is_leaf()) { //If a leaf of the route tree is not a SINK, then it is a stub - if (rr_graph.node_type(rt_node.inode) != SINK) { + if (rr_graph.node_type(rt_node.inode) != e_rr_type::SINK) { return true; //It is the current root of this stub } else { return false; diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp deleted file mode 100644 index 664553995a4..00000000000 --- a/vpr/src/route/connection_router.cpp +++ /dev/null @@ -1,1129 +0,0 @@ -#include "connection_router.h" - -#include -#include "rr_graph.h" -#include "rr_graph_fwd.h" - -/** Used for the flat router. The node isn't relevant to the target if - * it is an intra-block node outside of our target block */ -static bool relevant_node_to_target(const RRGraphView* rr_graph, - RRNodeId node_to_add, - RRNodeId target_node); - -static void update_router_stats(RouterStats* router_stats, - bool is_push, - RRNodeId rr_node_id, - const RRGraphView* rr_graph); - -/** return tuple */ -template -std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RouterStats& router_stats, - const ConnectionParameters& conn_params) { - router_stats_ = &router_stats; - conn_params_ = &conn_params; - - bool retry = false; - retry = timing_driven_route_connection_common_setup(rt_root, sink_node, cost_params, bounding_box); - - if (!std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - // Only the `index`, `prev_edge`, and `rcv_path_backward_delay` fields of `out` - // are used after this function returns. - RTExploredNode out; - out.index = sink_node; - out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; - if (rcv_path_manager.is_enabled()) { - out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; - rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); - rcv_path_manager.empty_heap(); - } - heap_.empty_heap(); - return std::make_tuple(true, /*retry=*/false, out); - } else { - reset_path_costs(); - clear_modified_rr_node_info(); - heap_.empty_heap(); - rcv_path_manager.empty_heap(); - return std::make_tuple(false, retry, RTExploredNode()); - } -} - -/** Return whether to retry with full bb */ -template -bool ConnectionRouter::timing_driven_route_connection_common_setup( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { - //Re-add route nodes from the existing route tree to the heap. - //They need to be repushed onto the heap since each node's cost is target specific. - - add_route_tree_to_heap(rt_root, sink_node, cost_params, bounding_box); - heap_.build_heap(); // via sifting down everything - - RRNodeId source_node = rt_root.inode; - - if (heap_.is_empty_heap()) { - VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return false; - } - - VTR_LOGV_DEBUG(router_debug_, " Routing to %d as normal net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, - bounding_box.layer_min, bounding_box.xmin, bounding_box.ymin, - bounding_box.layer_max, bounding_box.xmax, bounding_box.ymax); - - timing_driven_route_connection_from_heap(sink_node, - cost_params, - bounding_box); - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - // No path found within the current bounding box. - // - // If the bounding box is already max size, just fail - if (bounding_box.xmin == 0 - && bounding_box.ymin == 0 - && bounding_box.xmax == (int)(grid_.width() - 1) - && bounding_box.ymax == (int)(grid_.height() - 1) - && bounding_box.layer_min == 0 - && bounding_box.layer_max == (int)(grid_.get_num_layers() - 1)) { - VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return false; - } - - // Otherwise, leave unrouted and bubble up a signal to retry this net with a full-device bounding box - VTR_LOG_WARN("No routing path for connection to sink_rr %d, leaving unrouted to retry later\n", sink_node); - return true; - } - - return false; -} - -// Finds a path from the route tree rooted at rt_root to sink_node for a high fanout net. -// -// Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree -// which is spatially close to the sink is added to the heap. -// Returns a tuple of */ -template -std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( - const RouteTreeNode& rt_root, - RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bounding_box, - const SpatialRouteTreeLookup& spatial_rt_lookup, - RouterStats& router_stats, - const ConnectionParameters& conn_params) { - router_stats_ = &router_stats; - conn_params_ = &conn_params; - - // re-explore route tree from root to add any new nodes (buildheap afterwards) - // route tree needs to be repushed onto the heap since each node's cost is target specific - t_bb high_fanout_bb = add_high_fanout_route_tree_to_heap(rt_root, sink_node, cost_params, spatial_rt_lookup, net_bounding_box); - heap_.build_heap(); - - RRNodeId source_node = rt_root.inode; - - if (heap_.is_empty_heap()) { - VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - return std::make_tuple(false, false, RTExploredNode()); - } - - VTR_LOGV_DEBUG(router_debug_, " Routing to %d as high fanout net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, - high_fanout_bb.layer_min, high_fanout_bb.xmin, high_fanout_bb.ymin, - high_fanout_bb.layer_max, high_fanout_bb.xmax, high_fanout_bb.ymax); - - bool retry_with_full_bb = false; - timing_driven_route_connection_from_heap(sink_node, - cost_params, - high_fanout_bb); - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - //Found no path, that may be due to an unlucky choice of existing route tree sub-set, - //try again with the full route tree to be sure this is not an artifact of high-fanout routing - VTR_LOG_WARN("No routing path found in high-fanout mode for net %zu connection (to sink_rr %d), retrying with full route tree\n", size_t(conn_params.net_id_), sink_node); - - //Reset any previously recorded node costs so timing_driven_route_connection() - //starts over from scratch. - reset_path_costs(); - clear_modified_rr_node_info(); - - retry_with_full_bb = timing_driven_route_connection_common_setup(rt_root, - sink_node, - cost_params, - net_bounding_box); - } - - if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { - VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); - - heap_.empty_heap(); - rcv_path_manager.empty_heap(); - return std::make_tuple(false, retry_with_full_bb, RTExploredNode()); - } - - RTExploredNode out; - out.index = sink_node; - out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; - if (rcv_path_manager.is_enabled()) { - out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; - rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); - rcv_path_manager.empty_heap(); - } - heap_.empty_heap(); - - return std::make_tuple(true, retry_with_full_bb, out); -} - -// Finds a path to sink_node, starting from the elements currently in the heap. -// This is the core maze routing routine. -template -void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { - VTR_ASSERT_SAFE(heap_.is_valid()); - - if (heap_.is_empty_heap()) { //No source - VTR_LOGV_DEBUG(router_debug_, " Initial heap empty (no source)\n"); - } - - const auto& device_ctx = g_vpr_ctx.device(); - auto& route_ctx = g_vpr_ctx.mutable_routing(); - - // Get bounding box for sink node used in timing_driven_expand_neighbour - VTR_ASSERT_SAFE(sink_node != RRNodeId::INVALID()); - - t_bb target_bb; - if (rr_graph_->node_type(sink_node) == SINK) { // We need to get a bounding box for the sink's entire tile - vtr::Rect tile_bb = grid_.get_tile_bb({rr_graph_->node_xlow(sink_node), - rr_graph_->node_ylow(sink_node), - rr_graph_->node_layer(sink_node)}); - - target_bb.xmin = tile_bb.xmin(); - target_bb.ymin = tile_bb.ymin(); - target_bb.xmax = tile_bb.xmax(); - target_bb.ymax = tile_bb.ymax(); - } else { - target_bb.xmin = rr_graph_->node_xlow(sink_node); - target_bb.ymin = rr_graph_->node_ylow(sink_node); - target_bb.xmax = rr_graph_->node_xhigh(sink_node); - target_bb.ymax = rr_graph_->node_yhigh(sink_node); - } - - target_bb.layer_min = rr_graph_->node_layer(RRNodeId(sink_node)); - target_bb.layer_max = rr_graph_->node_layer(RRNodeId(sink_node)); - - // Start measuring path search time - std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); - - HeapNode cheapest; - while (heap_.try_pop(cheapest)) { - // inode with the cheapest total cost in current route tree to be expanded on - const auto& [new_total_cost, inode] = cheapest; - update_router_stats(router_stats_, - /*is_push=*/false, - inode, - rr_graph_); - - VTR_LOGV_DEBUG(router_debug_, " Popping node %d (cost: %g)\n", - inode, new_total_cost); - - // Have we found the target? - if (inode == sink_node) { - // If we're running RCV, the path will be stored in the path_data->path_rr vector - // This is then placed into the traceback so that the correct path is returned - // TODO: This can be eliminated by modifying the actual traceback function in route_timing - if (rcv_path_manager.is_enabled()) { - rcv_path_manager.insert_backwards_path_into_traceback(rcv_path_data[inode], - rr_node_route_inf_[inode].path_cost, - rr_node_route_inf_[inode].backward_path_cost, - route_ctx); - } - VTR_LOGV_DEBUG(router_debug_, " Found target %8d (%s)\n", inode, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); - break; - } - - // If not, keep searching - timing_driven_expand_cheapest(inode, - new_total_cost, - sink_node, - cost_params, - bounding_box, - target_bb); - } - - // Stop measuring path search time - std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); - path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); -} - -// Find shortest paths from specified route tree to all nodes in the RR graph -template -vtr::vector ConnectionRouter::timing_driven_find_all_shortest_paths_from_route_tree( - const RouteTreeNode& rt_root, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RouterStats& router_stats, - const ConnectionParameters& conn_params) { - router_stats_ = &router_stats; - conn_params_ = &conn_params; - - // Add the route tree to the heap with no specific target node - RRNodeId target_node = RRNodeId::INVALID(); - add_route_tree_to_heap(rt_root, target_node, cost_params, bounding_box); - heap_.build_heap(); // via sifting down everything - - auto res = timing_driven_find_all_shortest_paths_from_heap(cost_params, bounding_box); - heap_.empty_heap(); - - return res; -} - -// Find shortest paths from current heap to all nodes in the RR graph -// -// Since there is no single *target* node this uses Dijkstra's algorithm -// with a modified exit condition (runs until heap is empty). -template -vtr::vector ConnectionRouter::timing_driven_find_all_shortest_paths_from_heap( - const t_conn_cost_params& cost_params, - const t_bb& bounding_box) { - vtr::vector cheapest_paths(rr_nodes_.size()); - - VTR_ASSERT_SAFE(heap_.is_valid()); - - if (heap_.is_empty_heap()) { // No source - VTR_LOGV_DEBUG(router_debug_, " Initial heap empty (no source)\n"); - } - - // Start measuring path search time - std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); - - HeapNode cheapest; - while (heap_.try_pop(cheapest)) { - // inode with the cheapest total cost in current route tree to be expanded on - const auto& [new_total_cost, inode] = cheapest; - update_router_stats(router_stats_, - /*is_push=*/false, - inode, - rr_graph_); - - VTR_LOGV_DEBUG(router_debug_, " Popping node %d (cost: %g)\n", - inode, new_total_cost); - - // Since we want to find shortest paths to all nodes in the graph - // we do not specify a target node. - // - // By setting the target_node to INVALID in combination with the NoOp router - // lookahead we can re-use the node exploration code from the regular router - RRNodeId target_node = RRNodeId::INVALID(); - - timing_driven_expand_cheapest(inode, - new_total_cost, - target_node, - cost_params, - bounding_box, - t_bb()); - - if (cheapest_paths[inode].index == RRNodeId::INVALID() || cheapest_paths[inode].total_cost >= new_total_cost) { - VTR_LOGV_DEBUG(router_debug_, " Better cost to node %d: %g (was %g)\n", inode, new_total_cost, cheapest_paths[inode].total_cost); - // Only the `index` and `prev_edge` fields of `cheapest_paths[inode]` are used after this function returns - cheapest_paths[inode].index = inode; - cheapest_paths[inode].prev_edge = rr_node_route_inf_[inode].prev_edge; - } else { - VTR_LOGV_DEBUG(router_debug_, " Worse cost to node %d: %g (better %g)\n", inode, new_total_cost, cheapest_paths[inode].total_cost); - } - } - - // Stop measuring path search time - std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); - path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); - - return cheapest_paths; -} - -template -void ConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_node, - float new_total_cost, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - const t_bb& target_bb) { - float best_total_cost = rr_node_route_inf_[from_node].path_cost; - if (best_total_cost == new_total_cost) { - // Explore from this node, since its total cost is exactly the same as - // the best total cost ever seen for this node. Otherwise, prune this node - // to reduce redundant work (i.e., unnecessary neighbor exploration). - // `new_total_cost` is used here as an identifier to detect if the pair - // (from_node or inode, new_total_cost) was the most recently pushed - // element for the corresponding node. - // - // Note: For RCV, it often isn't searching for a shortest path; it is - // searching for a path in the target delay range. So it might find a - // path to node n that has a higher `backward_path_cost` but the `total_cost` - // (including expected delay to sink, going through a cost function that - // checks that against the target delay) might be lower than the previously - // stored value. In that case we want to re-expand the node so long as - // it doesn't create a loop. That `rcv_path_manager` should store enough - // info for us to avoid loops. - RTExploredNode current; - current.index = from_node; - current.backward_path_cost = rr_node_route_inf_[from_node].backward_path_cost; - current.prev_edge = rr_node_route_inf_[from_node].prev_edge; - current.R_upstream = rr_node_route_inf_[from_node].R_upstream; - - VTR_LOGV_DEBUG(router_debug_, " Better cost to %d\n", from_node); - VTR_LOGV_DEBUG(router_debug_, " New total cost: %g\n", new_total_cost); - VTR_LOGV_DEBUG(router_debug_ && (current.prev_edge != RREdgeId::INVALID()), - " Setting path costs for associated node %d (from %d edge %zu)\n", - from_node, - static_cast(rr_graph_->edge_src_node(current.prev_edge)), - static_cast(current.prev_edge)); - - timing_driven_expand_neighbours(current, cost_params, bounding_box, target_node, target_bb); - } else { - // Post-heap prune, do not re-explore from the current/new partial path as it - // has worse cost than the best partial path to this node found so far - VTR_LOGV_DEBUG(router_debug_, " Worse cost to %d\n", from_node); - VTR_LOGV_DEBUG(router_debug_, " Old total cost: %g\n", best_total_cost); - VTR_LOGV_DEBUG(router_debug_, " New total cost: %g\n", new_total_cost); - } -} - -template -void ConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RRNodeId target_node, - const t_bb& target_bb) { - /* Puts all the rr_nodes adjacent to current on the heap. */ - - // For each node associated with the current heap element, expand all of it's neighbors - auto edges = rr_nodes_.edge_range(current.index); - - // This is a simple prefetch that prefetches: - // - RR node data reachable from this node - // - rr switch data to reach those nodes from this node. - // - // This code will be a NOP on compiler targets that do not have a - // builtin to emit prefetch instructions. - // - // This code will be a NOP on CPU targets that lack prefetch instructions. - // All modern x86 and ARM64 platforms provide prefetch instructions. - // - // This code delivers ~6-8% reduction in wallclock time when running Titan - // benchmarks, and was specifically measured against the gsm_switch and - // directrf vtr_reg_weekly running in high effort. - // - // - directrf_stratixiv_arch_timing.blif - // - gsm_switch_stratixiv_arch_timing.blif - // - for (RREdgeId from_edge : edges) { - RRNodeId to_node = rr_nodes_.edge_sink_node(from_edge); - rr_nodes_.prefetch_node(to_node); - - int switch_idx = rr_nodes_.edge_switch(from_edge); - VTR_PREFETCH(&rr_switch_inf_[switch_idx], 0, 0); - } - - for (RREdgeId from_edge : edges) { - RRNodeId to_node = rr_nodes_.edge_sink_node(from_edge); - timing_driven_expand_neighbour(current, - from_edge, - to_node, - cost_params, - bounding_box, - target_node, - target_bb); - } -} - -// Conditionally adds to_node to the router heap (via path from from_node via from_edge). -// RR nodes outside the expanded bounding box specified in bounding_box are not added -// to the heap. -template -void ConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, - RREdgeId from_edge, - RRNodeId to_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RRNodeId target_node, - const t_bb& target_bb) { - VTR_ASSERT(bounding_box.layer_max < g_vpr_ctx.device().grid.get_num_layers()); - - const RRNodeId& from_node = current.index; - - // BB-pruning - // Disable BB-pruning if RCV is enabled, as this can make it harder for circuits with high negative hold slack to resolve this - // TODO: Only disable pruning if the net has negative hold slack, maybe go off budgets - if (!inside_bb(to_node, bounding_box) - && !rcv_path_manager.is_enabled()) { - VTR_LOGV_DEBUG(router_debug_, - " Pruned expansion of node %d edge %zu -> %d" - " (to node location %d,%d,%d x %d,%d,%d outside of expanded" - " net bounding box %d,%d,%d x %d,%d,%d)\n", - from_node, size_t(from_edge), size_t(to_node), - rr_graph_->node_xlow(to_node), rr_graph_->node_ylow(to_node), rr_graph_->node_layer(to_node), - rr_graph_->node_xhigh(to_node), rr_graph_->node_yhigh(to_node), rr_graph_->node_layer(to_node), - bounding_box.xmin, bounding_box.ymin, bounding_box.layer_min, - bounding_box.xmax, bounding_box.ymax, bounding_box.layer_max); - return; /* Node is outside (expanded) bounding box. */ - } - - /* Prune away IPINs that lead to blocks other than the target one. Avoids * - * the issue of how to cost them properly so they don't get expanded before * - * more promising routes, but makes route-through (via CLBs) impossible. * - * Change this if you want to investigate route-throughs. */ - if (target_node != RRNodeId::INVALID()) { - t_rr_type to_type = rr_graph_->node_type(to_node); - if (to_type == IPIN) { - // Check if this IPIN leads to the target block - // IPIN's of the target block should be contained within it's bounding box - int to_xlow = rr_graph_->node_xlow(to_node); - int to_ylow = rr_graph_->node_ylow(to_node); - int to_layer = rr_graph_->node_layer(to_node); - int to_xhigh = rr_graph_->node_xhigh(to_node); - int to_yhigh = rr_graph_->node_yhigh(to_node); - if (to_xlow < target_bb.xmin - || to_ylow < target_bb.ymin - || to_xhigh > target_bb.xmax - || to_yhigh > target_bb.ymax - || to_layer < target_bb.layer_min - || to_layer > target_bb.layer_max) { - VTR_LOGV_DEBUG(router_debug_, - " Pruned expansion of node %d edge %zu -> %d" - " (to node is IPIN at %d,%d,%d x %d,%d,%d which does not" - " lead to target block %d,%d,%d x %d,%d,%d)\n", - from_node, size_t(from_edge), size_t(to_node), - to_xlow, to_ylow, to_layer, - to_xhigh, to_yhigh, to_layer, - target_bb.xmin, target_bb.ymin, target_bb.layer_min, - target_bb.xmax, target_bb.ymax, target_bb.layer_max); - return; - } - } - } - - VTR_LOGV_DEBUG(router_debug_, " Expanding node %d edge %zu -> %d\n", - from_node, size_t(from_edge), size_t(to_node)); - - // Check if the node exists in the route tree when RCV is enabled - // Other pruning methods have been disabled when RCV is on, so this method is required to prevent "loops" from being created - bool node_exists = false; - if (rcv_path_manager.is_enabled()) { - node_exists = rcv_path_manager.node_exists_in_tree(rcv_path_data[from_node], - to_node); - } - - if (!node_exists || !rcv_path_manager.is_enabled()) { - timing_driven_add_to_heap(cost_params, - current, - to_node, - from_edge, - target_node); - } -} - -// Add to_node to the heap, and also add any nodes which are connected by non-configurable edges -template -void ConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, - const RTExploredNode& current, - RRNodeId to_node, - const RREdgeId from_edge, - RRNodeId target_node) { - const auto& device_ctx = g_vpr_ctx.device(); - const RRNodeId& from_node = current.index; - - // Initialized to current - RTExploredNode next; - next.R_upstream = current.R_upstream; - next.index = to_node; - next.prev_edge = from_edge; - next.total_cost = std::numeric_limits::infinity(); // Not used directly - next.backward_path_cost = current.backward_path_cost; - - // Initalize RCV data struct if needed, otherwise it's set to nullptr - rcv_path_manager.alloc_path_struct(next.path_data); - // path_data variables are initialized to current values - if (rcv_path_manager.is_enabled() && rcv_path_data[from_node]) { - next.path_data->backward_cong = rcv_path_data[from_node]->backward_cong; - next.path_data->backward_delay = rcv_path_data[from_node]->backward_delay; - } - - evaluate_timing_driven_node_costs(&next, - cost_params, - from_node, - target_node); - - float best_total_cost = rr_node_route_inf_[to_node].path_cost; - float best_back_cost = rr_node_route_inf_[to_node].backward_path_cost; - - float new_total_cost = next.total_cost; - float new_back_cost = next.backward_path_cost; - - // We need to only expand this node if it is a better path. And we need to - // update its `rr_node_route_inf` data as we put it into the heap; there may - // be other (previously explored) paths to this node in the heap already, - // but they will be pruned when we pop those heap nodes later as we'll see - // they have inferior costs to what is in the `rr_node_route_inf` data for - // this node. - // FIXME: Adding a link to the FPT paper when it is public - // - // When RCV is enabled, prune based on the RCV-specific total path cost (see - // in `compute_node_cost_using_rcv` in `evaluate_timing_driven_node_costs`) - // to allow detours to get better QoR. - if ((!rcv_path_manager.is_enabled() && best_back_cost > new_back_cost) || (rcv_path_manager.is_enabled() && best_total_cost > new_total_cost)) { - VTR_LOGV_DEBUG(router_debug_, " Expanding to node %d (%s)\n", to_node, - describe_rr_node(device_ctx.rr_graph, - device_ctx.grid, - device_ctx.rr_indexed_data, - to_node, - is_flat_) - .c_str()); - VTR_LOGV_DEBUG(router_debug_, " New Total Cost %g New back Cost %g\n", new_total_cost, new_back_cost); - //Add node to the heap only if the cost via the current partial path is less than the - //best known cost, since there is no reason for the router to expand more expensive paths. - // - //Pre-heap prune to keep the heap small, by not putting paths which are known to be - //sub-optimal (at this point in time) into the heap. - - update_cheapest(next, from_node); - - heap_.add_to_heap({new_total_cost, to_node}); - update_router_stats(router_stats_, - /*is_push=*/true, - to_node, - rr_graph_); - - } else { - VTR_LOGV_DEBUG(router_debug_, " Didn't expand to %d (%s)\n", to_node, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to_node, is_flat_).c_str()); - VTR_LOGV_DEBUG(router_debug_, " Prev Total Cost %g Prev back Cost %g \n", best_total_cost, best_back_cost); - VTR_LOGV_DEBUG(router_debug_, " New Total Cost %g New back Cost %g \n", new_total_cost, new_back_cost); - } - - if (rcv_path_manager.is_enabled() && next.path_data != nullptr) { - rcv_path_manager.free_path_struct(next.path_data); - } -} - -#ifdef VTR_ASSERT_SAFE_ENABLED - -//Returns true if both nodes are part of the same non-configurable edge set -static bool same_non_config_node_set(RRNodeId from_node, RRNodeId to_node) { - auto& device_ctx = g_vpr_ctx.device(); - - auto from_itr = device_ctx.rr_node_to_non_config_node_set.find(from_node); - auto to_itr = device_ctx.rr_node_to_non_config_node_set.find(to_node); - - if (from_itr == device_ctx.rr_node_to_non_config_node_set.end() - || to_itr == device_ctx.rr_node_to_non_config_node_set.end()) { - return false; //Not part of a non-config node set - } - - return from_itr->second == to_itr->second; //Check for same non-config set IDs -} - -#endif - -template -float ConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_params cost_params, - RRNodeId to_node, - RRNodeId target_node, - float backwards_delay, - float backwards_cong, - float R_upstream) { - float expected_delay; - float expected_cong; - - const t_conn_delay_budget* delay_budget = cost_params.delay_budget; - // TODO: This function is not tested for is_flat == true - VTR_ASSERT(is_flat_ != true); - std::tie(expected_delay, expected_cong) = router_lookahead_.get_expected_delay_and_cong(to_node, target_node, cost_params, R_upstream); - - float expected_total_delay_cost; - float expected_total_cong_cost; - - float expected_total_cong = expected_cong + backwards_cong; - float expected_total_delay = expected_delay + backwards_delay; - - //If budgets specified calculate cost as described by RCV paper: - // R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While - // Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of - // Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008. - - // Normalization constant defined in RCV paper cited above - constexpr float NORMALIZATION_CONSTANT = 100e-12; - - expected_total_delay_cost = expected_total_delay; - expected_total_delay_cost += (delay_budget->short_path_criticality + cost_params.criticality) * std::max(0.f, delay_budget->target_delay - expected_total_delay); - // expected_total_delay_cost += std::pow(std::max(0.f, expected_total_delay - delay_budget->max_delay), 2) / NORMALIZATION_CONSTANT; - expected_total_delay_cost += std::pow(std::max(0.f, delay_budget->min_delay - expected_total_delay), 2) / NORMALIZATION_CONSTANT; - expected_total_cong_cost = expected_total_cong; - - float total_cost = expected_total_delay_cost + expected_total_cong_cost; - - return total_cost; -} - -// Empty the route tree set node, use this after each net is routed -template -void ConnectionRouter::empty_rcv_route_tree_set() { - rcv_path_manager.empty_route_tree_nodes(); -} - -// Enable or disable RCV -template -void ConnectionRouter::set_rcv_enabled(bool enable) { - rcv_path_manager.set_enabled(enable); - if (enable) { - rcv_path_data.resize(rr_node_route_inf_.size()); - } -} - -//Calculates the cost of reaching to_node (i.e., to->index) -template -void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, - const t_conn_cost_params& cost_params, - RRNodeId from_node, - RRNodeId target_node) { - /* new_costs.backward_cost: is the "known" part of the cost to this node -- the - * congestion cost of all the routing resources back to the existing route - * plus the known delay of the total path back to the source. - * - * new_costs.total_cost: is this "known" backward cost + an expected cost to get to the target. - * - * new_costs.R_upstream: is the upstream resistance at the end of this node - */ - - //Info for the switch connecting from_node to_node (i.e., to->index) - int iswitch = rr_nodes_.edge_switch(to->prev_edge); - bool switch_buffered = rr_switch_inf_[iswitch].buffered(); - bool reached_configurably = rr_switch_inf_[iswitch].configurable(); - float switch_R = rr_switch_inf_[iswitch].R; - float switch_Tdel = rr_switch_inf_[iswitch].Tdel; - float switch_Cinternal = rr_switch_inf_[iswitch].Cinternal; - - //To node info - auto rc_index = rr_graph_->node_rc_index(to->index); - float node_C = rr_rc_data_[rc_index].C; - float node_R = rr_rc_data_[rc_index].R; - - //From node info - float from_node_R = rr_rc_data_[rr_graph_->node_rc_index(from_node)].R; - - //Update R_upstream - if (switch_buffered) { - to->R_upstream = 0.; //No upstream resistance - } else { - //R_Upstream already initialized - } - - to->R_upstream += switch_R; //Switch resistance - to->R_upstream += node_R; //Node resistance - - //Calculate delay - float Rdel = to->R_upstream - 0.5 * node_R; //Only consider half node's resistance for delay - float Tdel = switch_Tdel + Rdel * node_C; - - //Depending on the switch used, the Tdel of the upstream node (from_node) may change due to - //increased loading from the switch's internal capacitance. - // - //Even though this delay physically affects from_node, we make the adjustment (now) on the to_node, - //since only once we've reached to to_node do we know the connection used (and the switch enabled). - // - //To adjust for the time delay, we compute the product of the Rdel associated with from_node and - //the internal capacitance of the switch. - // - //First, we will calculate Rdel_adjust (just like in the computation for Rdel, we consider only - //half of from_node's resistance). - float Rdel_adjust = to->R_upstream - 0.5 * from_node_R; - - //Second, we adjust the Tdel to account for the delay caused by the internal capacitance. - Tdel += Rdel_adjust * switch_Cinternal; - - float cong_cost = 0.; - if (reached_configurably) { - cong_cost = get_rr_cong_cost(to->index, cost_params.pres_fac); - } else { - //Reached by a non-configurable edge. - //Therefore the from_node and to_node are part of the same non-configurable node set. -#ifdef VTR_ASSERT_SAFE_ENABLED - VTR_ASSERT_SAFE_MSG(same_non_config_node_set(from_node, to->index), - "Non-configurably connected edges should be part of the same node set"); -#endif - - //The congestion cost of all nodes in the set has already been accounted for (when - //the current path first expanded a node in the set). Therefore do *not* re-add the congestion - //cost. - cong_cost = 0.; - } - if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == IPIN) { - auto find_res = conn_params_->connection_choking_spots_.find(to->index); - if (find_res != conn_params_->connection_choking_spots_.end()) { - cong_cost = cong_cost / pow(2, (float)find_res->second); - } - } - - //Update the backward cost (upstream already included) - to->backward_path_cost += (1. - cost_params.criticality) * cong_cost; //Congestion cost - to->backward_path_cost += cost_params.criticality * Tdel; //Delay cost - - if (cost_params.bend_cost != 0.) { - t_rr_type from_type = rr_graph_->node_type(from_node); - t_rr_type to_type = rr_graph_->node_type(to->index); - if ((from_type == CHANX && to_type == CHANY) || (from_type == CHANY && to_type == CHANX)) { - to->backward_path_cost += cost_params.bend_cost; //Bend cost - } - } - - float total_cost = 0.; - - if (rcv_path_manager.is_enabled() && to->path_data != nullptr) { - to->path_data->backward_delay += cost_params.criticality * Tdel; - to->path_data->backward_cong += (1. - cost_params.criticality) * get_rr_cong_cost(to->index, cost_params.pres_fac); - - total_cost = compute_node_cost_using_rcv(cost_params, to->index, target_node, to->path_data->backward_delay, to->path_data->backward_cong, to->R_upstream); - } else { - const auto& device_ctx = g_vpr_ctx.device(); - //Update total cost - float expected_cost = router_lookahead_.get_expected_cost(to->index, target_node, cost_params, to->R_upstream); - VTR_LOGV_DEBUG(router_debug_ && !std::isfinite(expected_cost), - " Lookahead from %s (%s) to %s (%s) is non-finite, expected_cost = %f, to->R_upstream = %f\n", - rr_node_arch_name(to->index, is_flat_).c_str(), - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to->index, is_flat_).c_str(), - rr_node_arch_name(target_node, is_flat_).c_str(), - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(), - expected_cost, to->R_upstream); - total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); - } - to->total_cost = total_cost; -} - -//Adds the route tree rooted at rt_node to the heap, preparing it to be -//used as branch-points for further routing. -template -void ConnectionRouter::add_route_tree_to_heap( - const RouteTreeNode& rt_node, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bb) { - /* Puts the entire partial routing below and including rt_node onto the heap * - * (except for those parts marked as not to be expanded) by calling itself * - * recursively. */ - - /* Pre-order depth-first traversal */ - // IPINs and SINKS are not re_expanded - if (rt_node.re_expand) { - add_route_tree_node_to_heap(rt_node, - target_node, - cost_params, - net_bb); - } - - for (const RouteTreeNode& child_node : rt_node.child_nodes()) { - if (is_flat_) { - if (relevant_node_to_target(rr_graph_, - child_node.inode, - target_node)) { - add_route_tree_to_heap(child_node, - target_node, - cost_params, - net_bb); - } - } else { - add_route_tree_to_heap(child_node, - target_node, - cost_params, - net_bb); - } - } -} - -//Unconditionally adds rt_node to the heap -// -//Note that if you want to respect rt_node.re_expand that is the caller's -//responsibility. -template -void ConnectionRouter::add_route_tree_node_to_heap( - const RouteTreeNode& rt_node, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bb) { - const auto& device_ctx = g_vpr_ctx.device(); - const RRNodeId inode = rt_node.inode; - float backward_path_cost = cost_params.criticality * rt_node.Tdel; - float R_upstream = rt_node.R_upstream; - - /* Don't push to heap if not in bounding box: no-op for serial router, important for parallel router */ - if (!inside_bb(rt_node.inode, net_bb)) - return; - - // after budgets are loaded, calculate delay cost as described by RCV paper - /* R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While - * Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of - * Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008.*/ - // float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); - - if (!rcv_path_manager.is_enabled()) { - // tot_cost = backward_path_cost + cost_params.astar_fac * expected_cost; - float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); - float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); - VTR_LOGV_DEBUG(router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", - inode, - tot_cost, - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); - - if (tot_cost > rr_node_route_inf_[inode].path_cost) { - return; - } - add_to_mod_list(inode); - rr_node_route_inf_[inode].path_cost = tot_cost; - rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); - rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; - rr_node_route_inf_[inode].R_upstream = R_upstream; - heap_.push_back({tot_cost, inode}); - - // push_back_node(&heap_, rr_node_route_inf_, - // inode, tot_cost, RREdgeId::INVALID(), - // backward_path_cost, R_upstream); - } else { - float expected_total_cost = compute_node_cost_using_rcv(cost_params, inode, target_node, rt_node.Tdel, 0, R_upstream); - - add_to_mod_list(inode); - rr_node_route_inf_[inode].path_cost = expected_total_cost; - rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); - rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; - rr_node_route_inf_[inode].R_upstream = R_upstream; - - rcv_path_manager.alloc_path_struct(rcv_path_data[inode]); - rcv_path_data[inode]->backward_delay = rt_node.Tdel; - - heap_.push_back({expected_total_cost, inode}); - - // push_back_node_with_info(&heap_, inode, expected_total_cost, - // backward_path_cost, R_upstream, rt_node.Tdel, &rcv_path_manager); - } - - update_router_stats(router_stats_, - /*is_push=*/true, - inode, - rr_graph_); - - if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - router_stats_->rt_node_pushes[rr_graph_->node_type(inode)]++; - } -} - -/* Expand bb by inode's extents and clip against net_bb */ -inline void expand_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb, RRNodeId inode, const RRGraphView* rr_graph) { - bb.xmin = std::max(net_bb.xmin, std::min(bb.xmin, rr_graph->node_xlow(inode))); - bb.ymin = std::max(net_bb.ymin, std::min(bb.ymin, rr_graph->node_ylow(inode))); - bb.xmax = std::min(net_bb.xmax, std::max(bb.xmax, rr_graph->node_xhigh(inode))); - bb.ymax = std::min(net_bb.ymax, std::max(bb.ymax, rr_graph->node_yhigh(inode))); - bb.layer_min = std::min(bb.layer_min, rr_graph->node_layer(inode)); - bb.layer_max = std::max(bb.layer_max, rr_graph->node_layer(inode)); -} - -/* Expand bb by HIGH_FANOUT_BB_FAC and clip against net_bb */ -inline void adjust_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb) { - constexpr int HIGH_FANOUT_BB_FAC = 3; - - bb.xmin = std::max(net_bb.xmin, bb.xmin - HIGH_FANOUT_BB_FAC); - bb.ymin = std::max(net_bb.ymin, bb.ymin - HIGH_FANOUT_BB_FAC); - bb.xmax = std::min(net_bb.xmax, bb.xmax + HIGH_FANOUT_BB_FAC); - bb.ymax = std::min(net_bb.ymax, bb.ymax + HIGH_FANOUT_BB_FAC); - bb.layer_min = std::min(net_bb.layer_min, bb.layer_min); - bb.layer_max = std::max(net_bb.layer_max, bb.layer_max); -} - -template -t_bb ConnectionRouter::add_high_fanout_route_tree_to_heap( - const RouteTreeNode& rt_root, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const SpatialRouteTreeLookup& spatial_rt_lookup, - const t_bb& net_bounding_box) { - //For high fanout nets we only add those route tree nodes which are spatially close - //to the sink. - // - //Based on: - // J. Swartz, V. Betz, J. Rose, "A Fast Routability-Driven Router for FPGAs", FPGA, 1998 - // - //We rely on a grid-based spatial look-up which is maintained for high fanout nets by - //update_route_tree(), which allows us to add spatially close route tree nodes without traversing - //the entire route tree (which is likely large for a high fanout net). - - //Determine which bin the target node is located in - - int target_bin_x = grid_to_bin_x(rr_graph_->node_xlow(target_node), spatial_rt_lookup); - int target_bin_y = grid_to_bin_y(rr_graph_->node_ylow(target_node), spatial_rt_lookup); - - auto target_layer = rr_graph_->node_layer(target_node); - - int chan_nodes_added = 0; - - t_bb highfanout_bb; - highfanout_bb.xmin = rr_graph_->node_xlow(target_node); - highfanout_bb.xmax = rr_graph_->node_xhigh(target_node); - highfanout_bb.ymin = rr_graph_->node_ylow(target_node); - highfanout_bb.ymax = rr_graph_->node_yhigh(target_node); - highfanout_bb.layer_min = target_layer; - highfanout_bb.layer_max = target_layer; - - //Add existing routing starting from the target bin. - //If the target's bin has insufficient existing routing add from the surrounding bins - constexpr int SINGLE_BIN_MIN_NODES = 2; - bool done = false; - bool found_node_on_same_layer = false; - for (int dx : {0, -1, +1}) { - size_t bin_x = target_bin_x + dx; - - if (bin_x > spatial_rt_lookup.dim_size(0) - 1) continue; //Out of range - - for (int dy : {0, -1, +1}) { - size_t bin_y = target_bin_y + dy; - - if (bin_y > spatial_rt_lookup.dim_size(1) - 1) continue; //Out of range - - for (const RouteTreeNode& rt_node : spatial_rt_lookup[bin_x][bin_y]) { - if (!rt_node.re_expand) // Some nodes (like IPINs) shouldn't be re-expanded - continue; - RRNodeId rr_node_to_add = rt_node.inode; - - /* Flat router: don't go into clusters other than the target one */ - if (is_flat_) { - if (!relevant_node_to_target(rr_graph_, rr_node_to_add, target_node)) - continue; - } - - /* In case of the parallel router, we may be dealing with a virtual net - * so prune the nodes from the HF lookup against the bounding box just in case */ - if (!inside_bb(rr_node_to_add, net_bounding_box)) - continue; - - auto rt_node_layer_num = rr_graph_->node_layer(rr_node_to_add); - if (rt_node_layer_num == target_layer) - found_node_on_same_layer = true; - - // Put the node onto the heap - add_route_tree_node_to_heap(rt_node, target_node, cost_params, net_bounding_box); - - // Expand HF BB to include the node (clip by original BB) - expand_highfanout_bounding_box(highfanout_bb, net_bounding_box, rr_node_to_add, rr_graph_); - - if (rr_graph_->node_type(rr_node_to_add) == CHANY || rr_graph_->node_type(rr_node_to_add) == CHANX) { - chan_nodes_added++; - } - } - - if (dx == 0 && dy == 0 && chan_nodes_added > SINGLE_BIN_MIN_NODES && found_node_on_same_layer) { - //Target bin contained at least minimum amount of routing - // - //We require at least SINGLE_BIN_MIN_NODES to be added. - //This helps ensure we don't end up with, for example, a single - //routing wire running in the wrong direction which may not be - //able to reach the target within the bounding box. - done = true; - break; - } - } - if (done) break; - } - /* If we didn't find enough nodes to branch off near the target - * or they are on the wrong grid layer, just add the full route tree */ - if (chan_nodes_added <= SINGLE_BIN_MIN_NODES || !found_node_on_same_layer) { - add_route_tree_to_heap(rt_root, target_node, cost_params, net_bounding_box); - return net_bounding_box; - } else { - //We found nearby routing, replace original bounding box to be localized around that routing - adjust_highfanout_bounding_box(highfanout_bb, net_bounding_box); - return highfanout_bb; - } -} - -static inline bool relevant_node_to_target(const RRGraphView* rr_graph, - RRNodeId node_to_add, - RRNodeId target_node) { - VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == t_rr_type::SINK); - auto node_to_add_type = rr_graph->node_type(node_to_add); - return node_to_add_type != t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); -} - -static inline void update_router_stats(RouterStats* router_stats, - bool is_push, - RRNodeId rr_node_id, - const RRGraphView* rr_graph) { - if (is_push) { - router_stats->heap_pushes++; - } else { - router_stats->heap_pops++; - } - - auto node_type = rr_graph->node_type(rr_node_id); - VTR_ASSERT(node_type != NUM_RR_TYPES); - - /* TODO: Eliminate the use of global var here!!! */ - const VibInf* vib; - if (!g_vpr_ctx.device().arch->vib_infs.empty()) { - vib = g_vpr_ctx.device().vib_grid.get_vib(rr_graph->node_layer(rr_node_id), rr_graph->node_xlow(rr_node_id), rr_graph->node_ylow(rr_node_id)); - } else { - vib = nullptr; - } - if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - t_physical_tile_type_ptr physical_type = g_vpr_ctx.device().grid.get_physical_type({rr_graph->node_xlow(rr_node_id), rr_graph->node_ylow(rr_node_id), rr_graph->node_layer(rr_node_id)}); - if (is_inter_cluster_node(physical_type, vib, node_type, rr_graph->node_ptc_num(rr_node_id))) { - if (is_push) { - router_stats->inter_cluster_node_pushes++; - router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; - } else { - router_stats->inter_cluster_node_pops++; - router_stats->inter_cluster_node_type_cnt_pops[node_type]++; - } - } else { - if (is_push) { - router_stats->intra_cluster_node_pushes++; - router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; - } else { - router_stats->intra_cluster_node_pops++; - router_stats->intra_cluster_node_type_cnt_pops[node_type]++; - } - } - } -} - -std::unique_ptr make_connection_router(e_heap_type heap_type, - const DeviceGrid& grid, - const RouterLookahead& router_lookahead, - const t_rr_graph_storage& rr_nodes, - const RRGraphView* rr_graph, - const std::vector& rr_rc_data, - const vtr::vector& rr_switch_inf, - vtr::vector& rr_node_route_inf, - bool is_flat) { - switch (heap_type) { - case e_heap_type::BINARY_HEAP: - return std::make_unique>( - grid, - router_lookahead, - rr_nodes, - rr_graph, - rr_rc_data, - rr_switch_inf, - rr_node_route_inf, - is_flat); - case e_heap_type::FOUR_ARY_HEAP: - return std::make_unique>( - grid, - router_lookahead, - rr_nodes, - rr_graph, - rr_rc_data, - rr_switch_inf, - rr_node_route_inf, - is_flat); - default: - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Unknown heap_type %d", - heap_type); - } -} diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h index 0de6d508991..f5bb7c57aa9 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/connection_router.h @@ -1,6 +1,26 @@ #ifndef _CONNECTION_ROUTER_H #define _CONNECTION_ROUTER_H +/** + * @file + * @brief This file defines the ConnectionRouter class. + * + * Overview + * ======== + * The ConnectionRouter represents the timing-driven connection routers, which + * route from some initial set of sources (via the input rt tree) to a particular + * sink. VPR supports two timing-driven connection routers, including the serial + * connection router and the MultiQueue-based parallel connection router. This + * class defines the interface for the two connection routers and encapsulates + * the common member variables and helper functions for them. + * + * @note + * When the ConnectionRouter is used, it mutates the provided rr_node_route_inf. + * The routed path can be found by tracing from the sink node (which is returned) + * through the rr_node_route_inf. See update_traceback as an example of this tracing. + * + */ + #include "connection_router_interface.h" #include "rr_graph_storage.h" #include "route_common.h" @@ -10,16 +30,10 @@ #include "router_stats.h" #include "spatial_route_tree_lookup.h" -#include "d_ary_heap.h" - -// This class encapsulates the timing driven connection router. This class -// routes from some initial set of sources (via the input rt tree) to a -// particular sink. -// -// When the ConnectionRouter is used, it mutates the provided -// rr_node_route_inf. The routed path can be found by tracing from the sink -// node (which is returned) through the rr_node_route_inf. See -// update_traceback as an example of this tracing. +/** + * @class ConnectionRouter defines the interface for the serial and parallel connection + * routers and encapsulates the common variables and helper functions for the two routers + */ template class ConnectionRouter : public ConnectionRouterInterface { public: @@ -46,40 +60,36 @@ class ConnectionRouter : public ConnectionRouterInterface { , router_debug_(false) , path_search_cumulative_time(0) { heap_.init_heap(grid); - only_opin_inter_layer = (grid.get_num_layers() > 1) && inter_layer_connections_limited_to_opin(*rr_graph); - } - - ~ConnectionRouter() { - VTR_LOG("Serial Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", - std::chrono::duration(path_search_cumulative_time).count()); - } - - // Clear's the modified list. Should be called after reset_path_costs - // have been called. - void clear_modified_rr_node_info() final { - modified_rr_node_inf_.clear(); - } - - // Reset modified data in rr_node_route_inf based on modified_rr_node_inf. - void reset_path_costs() final { - // Reset the node info stored in rr_node_route_inf variable - ::reset_path_costs(modified_rr_node_inf_); - // Reset the node info stored inside the connection router - if (rcv_path_manager.is_enabled()) { - for (const auto& node : modified_rr_node_inf_) { - rcv_path_data[node] = nullptr; - } - } } - /** Finds a path from the route tree rooted at rt_root to sink_node. - * This is used when you want to allow previous routing of the same net to - * serve as valid start locations for the current connection. - * - * Returns a tuple of: - * bool: path exists? (hard failure, rr graph disconnected) - * bool: should retry with full bounding box? (only used in parallel routing) - * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ + virtual ~ConnectionRouter() {} + + /** + * @brief Clears the modified list + * @note Should be called after reset_path_costs have been called + */ + virtual void clear_modified_rr_node_info() = 0; + + /** + * @brief Resets modified data in rr_node_route_inf based on modified_rr_node_inf + */ + virtual void reset_path_costs() = 0; + + /** + * @brief Finds a path from the route tree rooted at rt_root to sink_node + * @note This is used when you want to allow previous routing of the same + * net to serve as valid start locations for the current connection. + * @param rt_root RouteTreeNode describing the current routing state + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param router_stats Update router statistics + * @param conn_params Parameters to guide the routing of the given connection + * @return A tuple of: + * - bool: path exists? (hard failure, rr graph disconnected) + * - bool: should retry with full bounding box? (only used in parallel routing) + * - RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing + */ std::tuple timing_driven_route_connection_from_route_tree( const RouteTreeNode& rt_root, RRNodeId sink_node, @@ -88,16 +98,22 @@ class ConnectionRouter : public ConnectionRouterInterface { RouterStats& router_stats, const ConnectionParameters& conn_params) final; - /** Finds a path from the route tree rooted at rt_root to sink_node for a - * high fanout net. - * - * Unlike timing_driven_route_connection_from_route_tree(), only part of - * the route tree which is spatially close to the sink is added to the heap. - * - * Returns a tuple of: - * bool: path exists? (hard failure, rr graph disconnected) - * bool: should retry with full bounding box? (only used in parallel routing) - * RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing */ + /** + * @brief Finds a path from the route tree rooted at rt_root to sink_node for a high fanout net + * @note Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree which + * is spatially close to the sink is added to the heap. + * @param rt_root RouteTreeNode describing the current routing state + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param net_bounding_box Keep search confined to this bounding box + * @param spatial_rt_lookup Route tree spatial lookup + * @param router_stats Update router statistics + * @param conn_params Parameters to guide the routing of the given connection + * @return A tuple of: + * - bool: path exists? (hard failure, rr graph disconnected) + * - bool: should retry with full bounding box? (only used in parallel routing) + * - RTExploredNode: the explored sink node, from which the cheapest path can be found via back-tracing + */ std::tuple timing_driven_route_connection_from_route_tree_high_fanout( const RouteTreeNode& rt_root, RRNodeId sink_node, @@ -107,159 +123,150 @@ class ConnectionRouter : public ConnectionRouterInterface { RouterStats& router_stats, const ConnectionParameters& conn_params) final; - // Finds a path from the route tree rooted at rt_root to all sinks - // available. - // - // Each element of the returned vector is a reachable sink. - // - // If cost_params.astar_fac is set to 0, this effectively becomes - // Dijkstra's algorithm with a modified exit condition (runs until heap is - // empty). When using cost_params.astar_fac = 0, for efficiency the - // RouterLookahead used should be the NoOpLookahead. - // - // Note: This routine is currently used only to generate information that - // may be helpful in debugging an architecture. - vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( + /** + * @brief Finds shortest paths from the route tree rooted at rt_root to all sinks available + * @note Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree which + * is spatially close to the sink is added to the heap. + * @note If cost_params.astar_fac is set to 0, this effectively becomes Dijkstra's algorithm with a + * modified exit condition (runs until heap is empty). When using cost_params.astar_fac = 0, for + * efficiency the RouterLookahead used should be the NoOpLookahead. + * @note This routine is currently used only to generate information that may be helpful in debugging + * an architecture. + * @param rt_root RouteTreeNode describing the current routing state + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param router_stats Update router statistics + * @param conn_params Parameters to guide the routing of the given connection + * @return A vector where each element is a reachable sink + */ + virtual vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( const RouteTreeNode& rt_root, const t_conn_cost_params& cost_params, const t_bb& bounding_box, RouterStats& router_stats, - const ConnectionParameters& conn_params) final; + const ConnectionParameters& conn_params) = 0; + /** + * @brief Sets router debug option + * @param router_debug Router debug option + */ void set_router_debug(bool router_debug) final { router_debug_ = router_debug; } - // Empty the route tree set used for RCV node detection - // Will return if RCV is disabled - // Called after each net is finished routing to flush the set - void empty_rcv_route_tree_set() final; - - // Enable or disable RCV in connection router - // Enabling this will utilize extra path structures, as well as the RCV cost function - // - // Ensure route budgets have been calculated before enabling this - void set_rcv_enabled(bool enable) final; - - private: - // Mark that data associated with rr_node "inode" has been modified, and - // needs to be reset in reset_path_costs. - void add_to_mod_list(RRNodeId inode) { - if (std::isinf(rr_node_route_inf_[inode].path_cost)) { - modified_rr_node_inf_.push_back(inode); - } - } - - // Update the route path to the node `cheapest.index` via the path from - // `from_node` via `cheapest.prev_edge`. - inline void update_cheapest(RTExploredNode& cheapest, const RRNodeId& from_node) { - const RRNodeId& inode = cheapest.index; - add_to_mod_list(inode); - rr_node_route_inf_[inode].prev_edge = cheapest.prev_edge; - rr_node_route_inf_[inode].path_cost = cheapest.total_cost; - rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; - - // Use the already created next path structure pointer when RCV is enabled - if (rcv_path_manager.is_enabled()) { - rcv_path_manager.move(rcv_path_data[inode], cheapest.path_data); - - rcv_path_data[inode]->path_rr = rcv_path_data[from_node]->path_rr; - rcv_path_data[inode]->edge = rcv_path_data[from_node]->edge; - rcv_path_data[inode]->path_rr.push_back(from_node); - rcv_path_data[inode]->edge.push_back(cheapest.prev_edge); - } + /** + * @brief Empties the route tree set used for RCV node detection + * @note Will immediately return if RCV is disabled. Called after + * each net is finished routing to flush the set. + */ + void empty_rcv_route_tree_set() final { + rcv_path_manager.empty_route_tree_nodes(); } - /** Common logic from timing_driven_route_connection_from_route_tree and + /** + * @brief Enables or disables RCV in connection router + * @note Enabling this will utilize extra path structures, as well as + * the RCV cost function. Ensure route budgets have been calculated + * before enabling this. + * @param enable Whether enabling RCV or not + */ + virtual void set_rcv_enabled(bool enable) = 0; + + protected: + /** + * @brief Common logic from timing_driven_route_connection_from_route_tree and * timing_driven_route_connection_from_route_tree_high_fanout for running * the connection router. - * @param[in] rt_root RouteTreeNode describing the current routing state - * @param[in] sink_node Sink node ID to route to - * @param[in] cost_params - * @param[in] bounding_box Keep search confined to this bounding box - * @return bool Signal to retry this connection with a full-device bounding box */ + * @param rt_root RouteTreeNode describing the current routing state + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @return bool signal to retry this connection with a full-device bounding box + */ bool timing_driven_route_connection_common_setup( const RouteTreeNode& rt_root, RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box); - // Finds a path to sink_node, starting from the elements currently in the - // heap. - // - // If the path is not found, which means that the path_cost of sink_node in - // RR node route info has never been updated, `rr_node_route_inf_[sink_node] - // .path_cost` will be the initial value (i.e., float infinity). This case - // can be detected by `std::isinf(rr_node_route_inf_[sink_node].path_cost)`. - // - // This is the core maze routing routine. - // - // Note: For understanding the connection router, start here. + /** + * @brief Finds a path to sink_node, starting from the elements currently in the heap + * @note If the path is not found, which means that the path_cost of sink_node in RR + * node route info has never been updated, `rr_node_route_inf_[sink_node].path_cost` + * will be the initial value (i.e., float infinity). This case can be detected by + * `std::isinf(rr_node_route_inf_[sink_node].path_cost)`. + * @note This is the core maze routing routine. For understanding the connection + * router, start here. + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + */ void timing_driven_route_connection_from_heap( RRNodeId sink_node, const t_conn_cost_params& cost_params, const t_bb& bounding_box); - // Expand this current node if it is a cheaper path. - void timing_driven_expand_cheapest( - RRNodeId from_node, - float new_total_cost, - RRNodeId target_node, + /** + * @brief Finds the single shortest path from current heap to the sink node in the RR graph + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ + virtual void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) = 0; + + /** + * @brief Finds shortest paths from current heap to all nodes in the RR graph + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @return A vector where each element contains the shortest route to a specific sink node + */ + virtual vtr::vector timing_driven_find_all_shortest_paths_from_heap( const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - const t_bb& target_bb); - - // Expand each neighbor of the current node. - void timing_driven_expand_neighbours( - const RTExploredNode& current, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, + const t_bb& bounding_box) = 0; + + /** + * @brief Unconditionally adds rt_node to the heap + * @note If you want to respect rt_node->re_expand that is the caller's responsibility. + * @todo Consider moving this function into the ConnectionRouter class after checking + * the different prune functions of the serial and parallel connection routers. + * @param rt_node RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param net_bb Do not push to heap if not in bounding box + */ + virtual void add_route_tree_node_to_heap( + const RouteTreeNode& rt_node, RRNodeId target_node, - const t_bb& target_bb); - - // Conditionally adds to_node to the router heap (via path from current.index - // via from_edge). - // - // RR nodes outside bounding box specified in bounding_box are not added - // to the heap. - void timing_driven_expand_neighbour( - const RTExploredNode& current, - RREdgeId from_edge, - RRNodeId to_node, const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - RRNodeId target_node, - const t_bb& target_bb); - - // Add to_node to the heap, and also add any nodes which are connected by - // non-configurable edges - void timing_driven_add_to_heap( - const t_conn_cost_params& cost_params, - const RTExploredNode& current, - RRNodeId to_node, - RREdgeId from_edge, - RRNodeId target_node); - - // Calculates the cost of reaching to_node + const t_bb& net_bb) = 0; + + /** + * @brief Calculates the cost of reaching to_node + * @param to Neighbor node to calculate costs before being expanded + * @param cost_params Cost function parameters + * @param from_node Current node ID being explored + * @param target_node Target node ID to route to + */ void evaluate_timing_driven_node_costs( RTExploredNode* to, const t_conn_cost_params& cost_params, RRNodeId from_node, RRNodeId target_node); - // Find paths from current heap to all nodes in the RR graph - vtr::vector timing_driven_find_all_shortest_paths_from_heap( - const t_conn_cost_params& cost_params, - const t_bb& bounding_box); - - //Adds the route tree rooted at rt_node to the heap, preparing it to be - //used as branch-points for further routing. - void add_route_tree_to_heap(const RouteTreeNode& rt_node, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bb); - - // Evaluate node costs using the RCV algorith + /** + * @brief Evaluate node costs using the RCV algorithm + * @param cost_params Cost function parameters + * @param to_node Neighbor node to calculate costs before being expanded + * @param target_node Target node ID to route to + * @param backwards_delay "Known" delay up to and including to_node + * @param backwards_cong "Known" congestion up to and including to_node + * @param R_upstream Upstream resistance to ground from to_node + * @return Node cost using RCV + */ float compute_node_cost_using_rcv(const t_conn_cost_params cost_params, RRNodeId to_node, RRNodeId target_node, @@ -267,16 +274,27 @@ class ConnectionRouter : public ConnectionRouterInterface { float backwards_cong, float R_upstream); - //Unconditionally adds rt_node to the heap - // - //Note that if you want to respect rt_node->re_expand that is the caller's - //responsibility. - void add_route_tree_node_to_heap( - const RouteTreeNode& rt_node, - RRNodeId target_node, - const t_conn_cost_params& cost_params, - const t_bb& net_bb); - + /** + * @brief Adds the route tree rooted at rt_node to the heap, preparing + * it to be used as branch-points for further routing + * @param rt_node RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param net_bb Do not push to heap if not in bounding box + */ + void add_route_tree_to_heap(const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb); + /** + * @brief For high fanout nets, adds only route tree nodes which are + * spatially close to the sink + * @param rt_root RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param spatial_route_tree_lookup Route tree spatial lookup + * @param net_bounding_box Do not push to heap if not in bounding box + */ t_bb add_high_fanout_route_tree_to_heap( const RouteTreeNode& rt_root, RRNodeId target_node, @@ -284,47 +302,59 @@ class ConnectionRouter : public ConnectionRouterInterface { const SpatialRouteTreeLookup& spatial_route_tree_lookup, const t_bb& net_bounding_box); + /** Device grid */ const DeviceGrid& grid_; + + /** Router lookahead */ const RouterLookahead& router_lookahead_; + + /** RR node data */ const t_rr_graph_view rr_nodes_; + + /** RR graph */ const RRGraphView* rr_graph_; + + /** RR node resistance/capacitance data */ vtr::array_view rr_rc_data_; + + /** RR switch data */ vtr::array_view rr_switch_inf_; + + //@{ + /** Net terminal groups */ const vtr::vector>>& net_terminal_groups; const vtr::vector>& net_terminal_group_num; + //@} + + /** RR node extra information needed during routing */ vtr::vector& rr_node_route_inf_; + + /** Is flat router enabled or not? */ bool is_flat_; - std::vector modified_rr_node_inf_; + + /** Router statistics (e.g., heap push/pop counts) */ RouterStats* router_stats_; + + /** Parameters to guide the routing of the given connection */ const ConnectionParameters* conn_params_; + + /** Templated heap instance (e.g., binary heap, 4-ary heap, MultiQueue-based parallel heap) */ HeapImplementation heap_; - bool router_debug_; - bool only_opin_inter_layer; + /** Router debug option */ + bool router_debug_; - // Cumulative time spent in the path search part of the connection router. + /** Cumulative time spent in the path search part of the connection router */ std::chrono::microseconds path_search_cumulative_time; - // The path manager for RCV, keeps track of the route tree as a set, also - // manages the allocation of `rcv_path_data`. + //@{ + /** The path manager for RCV, keeps track of the route tree as a set, also + * manages the allocation of `rcv_path_data`. */ PathManager rcv_path_manager; vtr::vector rcv_path_data; + //@} }; -/** Construct a connection router that uses the specified heap type. - * This function is not used, but removing it will result in "undefined reference" - * errors since heap type specializations won't get emitted from connection_router.cpp - * without it. - * The alternative is moving all ConnectionRouter fn implementations into the header. */ -std::unique_ptr make_connection_router( - e_heap_type heap_type, - const DeviceGrid& grid, - const RouterLookahead& router_lookahead, - const t_rr_graph_storage& rr_nodes, - const RRGraphView* rr_graph, - const std::vector& rr_rc_data, - const vtr::vector& rr_switch_inf, - vtr::vector& rr_node_route_inf, - bool is_flat); +#include "connection_router.tpp" #endif /* _CONNECTION_ROUTER_H */ diff --git a/vpr/src/route/connection_router.tpp b/vpr/src/route/connection_router.tpp new file mode 100644 index 00000000000..f74b213235f --- /dev/null +++ b/vpr/src/route/connection_router.tpp @@ -0,0 +1,546 @@ +#pragma once + +#include "connection_router.h" + +#include +#include "describe_rr_node.h" +#include "rr_graph_fwd.h" +#include "vpr_utils.h" + +/** Used for the flat router. The node isn't relevant to the target if + * it is an intra-block node outside of our target block */ +inline bool relevant_node_to_target(const RRGraphView* rr_graph, + RRNodeId node_to_add, + RRNodeId target_node); + +template +std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) { + router_stats_ = &router_stats; + conn_params_ = &conn_params; + + bool retry = false; + retry = timing_driven_route_connection_common_setup(rt_root, sink_node, cost_params, bounding_box); + + if (!std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + // Only the `index`, `prev_edge`, and `rcv_path_backward_delay` fields of `out` + // are used after this function returns. + RTExploredNode out; + out.index = sink_node; + out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; + if (rcv_path_manager.is_enabled()) { + out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; + rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); + rcv_path_manager.empty_heap(); + } + heap_.empty_heap(); + return std::make_tuple(true, /*retry=*/false, out); + } else { + reset_path_costs(); + clear_modified_rr_node_info(); + heap_.empty_heap(); + rcv_path_manager.empty_heap(); + return std::make_tuple(false, retry, RTExploredNode()); + } +} + +template +std::tuple ConnectionRouter::timing_driven_route_connection_from_route_tree_high_fanout( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bounding_box, + const SpatialRouteTreeLookup& spatial_rt_lookup, + RouterStats& router_stats, + const ConnectionParameters& conn_params) { + router_stats_ = &router_stats; + conn_params_ = &conn_params; + + // re-explore route tree from root to add any new nodes (buildheap afterwards) + // route tree needs to be repushed onto the heap since each node's cost is target specific + t_bb high_fanout_bb = add_high_fanout_route_tree_to_heap(rt_root, sink_node, cost_params, spatial_rt_lookup, net_bounding_box); + heap_.build_heap(); + + RRNodeId source_node = rt_root.inode; + + if (heap_.is_empty_heap()) { + VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return std::make_tuple(false, false, RTExploredNode()); + } + + VTR_LOGV_DEBUG(router_debug_, " Routing to %d as high fanout net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, + high_fanout_bb.layer_min, high_fanout_bb.xmin, high_fanout_bb.ymin, + high_fanout_bb.layer_max, high_fanout_bb.xmax, high_fanout_bb.ymax); + + bool retry_with_full_bb = false; + timing_driven_route_connection_from_heap(sink_node, cost_params, high_fanout_bb); + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + //Found no path, that may be due to an unlucky choice of existing route tree sub-set, + //try again with the full route tree to be sure this is not an artifact of high-fanout routing + VTR_LOG_WARN("No routing path found in high-fanout mode for net %zu connection (to sink_rr %d), retrying with full route tree\n", size_t(conn_params.net_id_), sink_node); + + //Reset any previously recorded node costs so timing_driven_route_connection() + //starts over from scratch. + reset_path_costs(); + clear_modified_rr_node_info(); + + retry_with_full_bb = timing_driven_route_connection_common_setup(rt_root, sink_node, cost_params, net_bounding_box); + } + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + + heap_.empty_heap(); + rcv_path_manager.empty_heap(); + return std::make_tuple(false, retry_with_full_bb, RTExploredNode()); + } + + RTExploredNode out; + out.index = sink_node; + out.prev_edge = rr_node_route_inf_[sink_node].prev_edge; + if (rcv_path_manager.is_enabled()) { + out.rcv_path_backward_delay = rcv_path_data[sink_node]->backward_delay; + rcv_path_manager.update_route_tree_set(rcv_path_data[sink_node]); + rcv_path_manager.empty_heap(); + } + heap_.empty_heap(); + + return std::make_tuple(true, retry_with_full_bb, out); +} + +template +bool ConnectionRouter::timing_driven_route_connection_common_setup( + const RouteTreeNode& rt_root, + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { + //Re-add route nodes from the existing route tree to the heap. + //They need to be repushed onto the heap since each node's cost is target specific. + + add_route_tree_to_heap(rt_root, sink_node, cost_params, bounding_box); + heap_.build_heap(); // via sifting down everything + + RRNodeId source_node = rt_root.inode; + + if (heap_.is_empty_heap()) { + VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return false; + } + + VTR_LOGV_DEBUG(router_debug_, " Routing to %d as normal net (BB: %d,%d,%d x %d,%d,%d)\n", sink_node, + bounding_box.layer_min, bounding_box.xmin, bounding_box.ymin, + bounding_box.layer_max, bounding_box.xmax, bounding_box.ymax); + + timing_driven_route_connection_from_heap(sink_node, cost_params, bounding_box); + + if (std::isinf(rr_node_route_inf_[sink_node].path_cost)) { + // No path found within the current bounding box. + // + // If the bounding box is already max size, just fail + if (bounding_box.xmin == 0 + && bounding_box.ymin == 0 + && bounding_box.xmax == (int)(grid_.width() - 1) + && bounding_box.ymax == (int)(grid_.height() - 1) + && bounding_box.layer_min == 0 + && bounding_box.layer_max == (int)(grid_.get_num_layers() - 1)) { + VTR_LOG("%s\n", describe_unrouteable_connection(source_node, sink_node, is_flat_).c_str()); + return false; + } + + // Otherwise, leave unrouted and bubble up a signal to retry this net with a full-device bounding box + VTR_LOG_WARN("No routing path for connection to sink_rr %d, leaving unrouted to retry later\n", sink_node); + return true; + } + + return false; +} + +template +void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { + VTR_ASSERT_SAFE(heap_.is_valid()); + + if (heap_.is_empty_heap()) { //No source + VTR_LOGV_DEBUG(router_debug_, " Initial heap empty (no source)\n"); + } + + // Get bounding box for sink node used in timing_driven_expand_neighbour + VTR_ASSERT_SAFE(sink_node != RRNodeId::INVALID()); + + t_bb target_bb; + if (rr_graph_->node_type(sink_node) == e_rr_type::SINK) { // We need to get a bounding box for the sink's entire tile + vtr::Rect tile_bb = grid_.get_tile_bb({rr_graph_->node_xlow(sink_node), + rr_graph_->node_ylow(sink_node), + rr_graph_->node_layer(sink_node)}); + + target_bb.xmin = tile_bb.xmin(); + target_bb.ymin = tile_bb.ymin(); + target_bb.xmax = tile_bb.xmax(); + target_bb.ymax = tile_bb.ymax(); + } else { + target_bb.xmin = rr_graph_->node_xlow(sink_node); + target_bb.ymin = rr_graph_->node_ylow(sink_node); + target_bb.xmax = rr_graph_->node_xhigh(sink_node); + target_bb.ymax = rr_graph_->node_yhigh(sink_node); + } + + target_bb.layer_min = rr_graph_->node_layer(RRNodeId(sink_node)); + target_bb.layer_max = rr_graph_->node_layer(RRNodeId(sink_node)); + + // Start measuring path search time + std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); + + timing_driven_find_single_shortest_path_from_heap(sink_node, cost_params, bounding_box, target_bb); + + // Stop measuring path search time + std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); + path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); +} + +#ifdef VTR_ASSERT_SAFE_ENABLED + +//Returns true if both nodes are part of the same non-configurable edge set +inline bool same_non_config_node_set(RRNodeId from_node, RRNodeId to_node) { + auto& device_ctx = g_vpr_ctx.device(); + + auto from_itr = device_ctx.rr_node_to_non_config_node_set.find(from_node); + auto to_itr = device_ctx.rr_node_to_non_config_node_set.find(to_node); + + if (from_itr == device_ctx.rr_node_to_non_config_node_set.end() + || to_itr == device_ctx.rr_node_to_non_config_node_set.end()) { + return false; //Not part of a non-config node set + } + + return from_itr->second == to_itr->second; //Check for same non-config set IDs +} + +#endif + +template +float ConnectionRouter::compute_node_cost_using_rcv(const t_conn_cost_params cost_params, + RRNodeId to_node, + RRNodeId target_node, + float backwards_delay, + float backwards_cong, + float R_upstream) { + float expected_delay; + float expected_cong; + + const t_conn_delay_budget* delay_budget = cost_params.delay_budget; + // TODO: This function is not tested for is_flat == true + VTR_ASSERT(is_flat_ != true); + std::tie(expected_delay, expected_cong) = router_lookahead_.get_expected_delay_and_cong(to_node, target_node, cost_params, R_upstream); + + float expected_total_delay_cost; + float expected_total_cong_cost; + + float expected_total_cong = expected_cong + backwards_cong; + float expected_total_delay = expected_delay + backwards_delay; + + //If budgets specified calculate cost as described by RCV paper: + // R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While + // Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of + // Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008. + + // Normalization constant defined in RCV paper cited above + constexpr float NORMALIZATION_CONSTANT = 100e-12; + + expected_total_delay_cost = expected_total_delay; + expected_total_delay_cost += (delay_budget->short_path_criticality + cost_params.criticality) * std::max(0.f, delay_budget->target_delay - expected_total_delay); + // expected_total_delay_cost += std::pow(std::max(0.f, expected_total_delay - delay_budget->max_delay), 2) / NORMALIZATION_CONSTANT; + expected_total_delay_cost += std::pow(std::max(0.f, delay_budget->min_delay - expected_total_delay), 2) / NORMALIZATION_CONSTANT; + expected_total_cong_cost = expected_total_cong; + + float total_cost = expected_total_delay_cost + expected_total_cong_cost; + + return total_cost; +} + +template +void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* to, + const t_conn_cost_params& cost_params, + RRNodeId from_node, + RRNodeId target_node) { + /* new_costs.backward_cost: is the "known" part of the cost to this node -- the + * congestion cost of all the routing resources back to the existing route + * plus the known delay of the total path back to the source. + * + * new_costs.total_cost: is this "known" backward cost + an expected cost to get to the target. + * + * new_costs.R_upstream: is the upstream resistance at the end of this node + */ + + //Info for the switch connecting from_node to_node (i.e., to->index) + int iswitch = rr_nodes_.edge_switch(to->prev_edge); + bool switch_buffered = rr_switch_inf_[iswitch].buffered(); + bool reached_configurably = rr_switch_inf_[iswitch].configurable(); + float switch_R = rr_switch_inf_[iswitch].R; + float switch_Tdel = rr_switch_inf_[iswitch].Tdel; + float switch_Cinternal = rr_switch_inf_[iswitch].Cinternal; + + //To node info + auto rc_index = rr_graph_->node_rc_index(to->index); + float node_C = rr_rc_data_[rc_index].C; + float node_R = rr_rc_data_[rc_index].R; + + //From node info + float from_node_R = rr_rc_data_[rr_graph_->node_rc_index(from_node)].R; + + //Update R_upstream + if (switch_buffered) { + to->R_upstream = 0.; //No upstream resistance + } else { + //R_Upstream already initialized + } + + to->R_upstream += switch_R; //Switch resistance + to->R_upstream += node_R; //Node resistance + + //Calculate delay + float Rdel = to->R_upstream - 0.5 * node_R; //Only consider half node's resistance for delay + float Tdel = switch_Tdel + Rdel * node_C; + + //Depending on the switch used, the Tdel of the upstream node (from_node) may change due to + //increased loading from the switch's internal capacitance. + // + //Even though this delay physically affects from_node, we make the adjustment (now) on the to_node, + //since only once we've reached to to_node do we know the connection used (and the switch enabled). + // + //To adjust for the time delay, we compute the product of the Rdel associated with from_node and + //the internal capacitance of the switch. + // + //First, we will calculate Rdel_adjust (just like in the computation for Rdel, we consider only + //half of from_node's resistance). + float Rdel_adjust = to->R_upstream - 0.5 * from_node_R; + + //Second, we adjust the Tdel to account for the delay caused by the internal capacitance. + Tdel += Rdel_adjust * switch_Cinternal; + + float cong_cost = 0.; + if (reached_configurably) { + cong_cost = get_rr_cong_cost(to->index, cost_params.pres_fac); + } else { + //Reached by a non-configurable edge. + //Therefore the from_node and to_node are part of the same non-configurable node set. +#ifdef VTR_ASSERT_SAFE_ENABLED + VTR_ASSERT_SAFE_MSG(same_non_config_node_set(from_node, to->index), + "Non-configurably connected edges should be part of the same node set"); +#endif + + //The congestion cost of all nodes in the set has already been accounted for (when + //the current path first expanded a node in the set). Therefore do *not* re-add the congestion + //cost. + cong_cost = 0.; + } + if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == e_rr_type::IPIN) { + auto find_res = conn_params_->connection_choking_spots_.find(to->index); + if (find_res != conn_params_->connection_choking_spots_.end()) { + cong_cost = cong_cost / pow(2, (float)find_res->second); + } + } + + //Update the backward cost (upstream already included) + to->backward_path_cost += (1. - cost_params.criticality) * cong_cost; //Congestion cost + to->backward_path_cost += cost_params.criticality * Tdel; //Delay cost + + if (cost_params.bend_cost != 0.) { + e_rr_type from_type = rr_graph_->node_type(from_node); + e_rr_type to_type = rr_graph_->node_type(to->index); + if ((from_type == e_rr_type::CHANX && to_type == e_rr_type::CHANY) || (from_type == e_rr_type::CHANY && to_type == e_rr_type::CHANX)) { + to->backward_path_cost += cost_params.bend_cost; //Bend cost + } + } + + float total_cost = 0.; + + if (rcv_path_manager.is_enabled() && to->path_data != nullptr) { + to->path_data->backward_delay += cost_params.criticality * Tdel; + to->path_data->backward_cong += (1. - cost_params.criticality) * get_rr_cong_cost(to->index, cost_params.pres_fac); + + total_cost = compute_node_cost_using_rcv(cost_params, to->index, target_node, to->path_data->backward_delay, to->path_data->backward_cong, to->R_upstream); + } else { + const auto& device_ctx = g_vpr_ctx.device(); + //Update total cost + float expected_cost = router_lookahead_.get_expected_cost(to->index, target_node, cost_params, to->R_upstream); + VTR_LOGV_DEBUG(router_debug_ && !std::isfinite(expected_cost), + " Lookahead from %s (%s) to %s (%s) is non-finite, expected_cost = %f, to->R_upstream = %f\n", + rr_node_arch_name(to->index, is_flat_).c_str(), + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to->index, is_flat_).c_str(), + rr_node_arch_name(target_node, is_flat_).c_str(), + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(), + expected_cost, to->R_upstream); + total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); + } + to->total_cost = total_cost; +} + +template +void ConnectionRouter::add_route_tree_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) { + /* Puts the entire partial routing below and including rt_node onto the heap * + * (except for those parts marked as not to be expanded) by calling itself * + * recursively. */ + + /* Pre-order depth-first traversal */ + // IPINs and SINKS are not re_expanded + if (rt_node.re_expand) { + add_route_tree_node_to_heap(rt_node, target_node, cost_params, net_bb); + } + + for (const RouteTreeNode& child_node : rt_node.child_nodes()) { + if (is_flat_) { + if (relevant_node_to_target(rr_graph_, child_node.inode, target_node)) { + add_route_tree_to_heap(child_node, target_node, cost_params, net_bb); + } + } else { + add_route_tree_to_heap(child_node, target_node, cost_params, net_bb); + } + } +} + +/* Expand bb by inode's extents and clip against net_bb */ +inline void expand_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb, RRNodeId inode, const RRGraphView* rr_graph) { + bb.xmin = std::max(net_bb.xmin, std::min(bb.xmin, rr_graph->node_xlow(inode))); + bb.ymin = std::max(net_bb.ymin, std::min(bb.ymin, rr_graph->node_ylow(inode))); + bb.xmax = std::min(net_bb.xmax, std::max(bb.xmax, rr_graph->node_xhigh(inode))); + bb.ymax = std::min(net_bb.ymax, std::max(bb.ymax, rr_graph->node_yhigh(inode))); + bb.layer_min = std::min(bb.layer_min, rr_graph->node_layer(inode)); + bb.layer_max = std::max(bb.layer_max, rr_graph->node_layer(inode)); +} + +/* Expand bb by HIGH_FANOUT_BB_FAC and clip against net_bb */ +inline void adjust_highfanout_bounding_box(t_bb& bb, const t_bb& net_bb) { + constexpr int HIGH_FANOUT_BB_FAC = 3; + + bb.xmin = std::max(net_bb.xmin, bb.xmin - HIGH_FANOUT_BB_FAC); + bb.ymin = std::max(net_bb.ymin, bb.ymin - HIGH_FANOUT_BB_FAC); + bb.xmax = std::min(net_bb.xmax, bb.xmax + HIGH_FANOUT_BB_FAC); + bb.ymax = std::min(net_bb.ymax, bb.ymax + HIGH_FANOUT_BB_FAC); + bb.layer_min = std::min(net_bb.layer_min, bb.layer_min); + bb.layer_max = std::max(net_bb.layer_max, bb.layer_max); +} + +template +t_bb ConnectionRouter::add_high_fanout_route_tree_to_heap( + const RouteTreeNode& rt_root, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const SpatialRouteTreeLookup& spatial_rt_lookup, + const t_bb& net_bounding_box) { + //For high fanout nets we only add those route tree nodes which are spatially close + //to the sink. + // + //Based on: + // J. Swartz, V. Betz, J. Rose, "A Fast Routability-Driven Router for FPGAs", FPGA, 1998 + // + //We rely on a grid-based spatial look-up which is maintained for high fanout nets by + //update_route_tree(), which allows us to add spatially close route tree nodes without traversing + //the entire route tree (which is likely large for a high fanout net). + + //Determine which bin the target node is located in + + int target_bin_x = grid_to_bin_x(rr_graph_->node_xlow(target_node), spatial_rt_lookup); + int target_bin_y = grid_to_bin_y(rr_graph_->node_ylow(target_node), spatial_rt_lookup); + + auto target_layer = rr_graph_->node_layer(target_node); + + int chan_nodes_added = 0; + + t_bb highfanout_bb; + highfanout_bb.xmin = rr_graph_->node_xlow(target_node); + highfanout_bb.xmax = rr_graph_->node_xhigh(target_node); + highfanout_bb.ymin = rr_graph_->node_ylow(target_node); + highfanout_bb.ymax = rr_graph_->node_yhigh(target_node); + highfanout_bb.layer_min = target_layer; + highfanout_bb.layer_max = target_layer; + + //Add existing routing starting from the target bin. + //If the target's bin has insufficient existing routing add from the surrounding bins + constexpr int SINGLE_BIN_MIN_NODES = 2; + bool done = false; + bool found_node_on_same_layer = false; + for (int dx : {0, -1, +1}) { + size_t bin_x = target_bin_x + dx; + + if (bin_x > spatial_rt_lookup.dim_size(0) - 1) continue; //Out of range + + for (int dy : {0, -1, +1}) { + size_t bin_y = target_bin_y + dy; + + if (bin_y > spatial_rt_lookup.dim_size(1) - 1) continue; //Out of range + + for (const RouteTreeNode& rt_node : spatial_rt_lookup[bin_x][bin_y]) { + if (!rt_node.re_expand) // Some nodes (like IPINs) shouldn't be re-expanded + continue; + RRNodeId rr_node_to_add = rt_node.inode; + + /* Flat router: don't go into clusters other than the target one */ + if (is_flat_) { + if (!relevant_node_to_target(rr_graph_, rr_node_to_add, target_node)) + continue; + } + + /* In case of the parallel router, we may be dealing with a virtual net + * so prune the nodes from the HF lookup against the bounding box just in case */ + if (!inside_bb(rr_node_to_add, net_bounding_box)) + continue; + + auto rt_node_layer_num = rr_graph_->node_layer(rr_node_to_add); + if (rt_node_layer_num == target_layer) + found_node_on_same_layer = true; + + // Put the node onto the heap + add_route_tree_node_to_heap(rt_node, target_node, cost_params, net_bounding_box); + + // Expand HF BB to include the node (clip by original BB) + expand_highfanout_bounding_box(highfanout_bb, net_bounding_box, rr_node_to_add, rr_graph_); + + if (rr_graph_->node_type(rr_node_to_add) == e_rr_type::CHANY || rr_graph_->node_type(rr_node_to_add) == e_rr_type::CHANX) { + chan_nodes_added++; + } + } + + if (dx == 0 && dy == 0 && chan_nodes_added > SINGLE_BIN_MIN_NODES && found_node_on_same_layer) { + //Target bin contained at least minimum amount of routing + // + //We require at least SINGLE_BIN_MIN_NODES to be added. + //This helps ensure we don't end up with, for example, a single + //routing wire running in the wrong direction which may not be + //able to reach the target within the bounding box. + done = true; + break; + } + } + if (done) break; + } + /* If we didn't find enough nodes to branch off near the target + * or they are on the wrong grid layer, just add the full route tree */ + if (chan_nodes_added <= SINGLE_BIN_MIN_NODES || !found_node_on_same_layer) { + add_route_tree_to_heap(rt_root, target_node, cost_params, net_bounding_box); + return net_bounding_box; + } else { + //We found nearby routing, replace original bounding box to be localized around that routing + adjust_highfanout_bounding_box(highfanout_bb, net_bounding_box); + return highfanout_bb; + } +} + +/** Used for the flat router. The node isn't relevant to the target if + * it is an intra-block node outside of our target block */ +inline bool relevant_node_to_target(const RRGraphView* rr_graph, + RRNodeId node_to_add, + RRNodeId target_node) { + VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == e_rr_type::SINK); + auto node_to_add_type = rr_graph->node_type(node_to_add); + return node_to_add_type != e_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node); +} diff --git a/vpr/src/route/connection_router_interface.h b/vpr/src/route/connection_router_interface.h index 96ef278833a..178768bf5d5 100644 --- a/vpr/src/route/connection_router_interface.h +++ b/vpr/src/route/connection_router_interface.h @@ -24,6 +24,8 @@ struct t_conn_cost_params { float criticality = 1.; float astar_fac = 1.2; float astar_offset = 0.f; + float post_target_prune_fac = 1.2f; + float post_target_prune_offset = 0.f; float bend_cost = 1.; float pres_fac = 1.; const t_conn_delay_budget* delay_budget = nullptr; diff --git a/vpr/src/route/d_ary_heap.h b/vpr/src/route/d_ary_heap.h index c52cd702d13..ed10b0157bd 100644 --- a/vpr/src/route/d_ary_heap.h +++ b/vpr/src/route/d_ary_heap.h @@ -21,6 +21,8 @@ template class DAryHeap : public HeapInterface { public: + static constexpr unsigned arg_D = D; + using priority_queue = customized_d_ary_priority_queue, HeapNodeComparator>; DAryHeap() {} diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h new file mode 100644 index 00000000000..5a49dadae50 --- /dev/null +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -0,0 +1,133 @@ +/******************************************************************** + * MultiQueue Implementation + * + * Originally authored by Guozheng Zhang, Gilead Posluns, and Mark C. Jeffrey + * Published at the 36th ACM Symposium on Parallelism in Algorithms and + * Architectures (SPAA), June 2024 + * + * Original source: https://github.com/mcj-group/cps + * + * This implementation and interface has been modified from the original to: + * - Support queue draining functionality + * - Enable integration with the VTR project + * + * The MultiQueue data structure provides an efficient concurrent priority + * queue implementation designed for parallel processing applications. + * + * Modified: February 2025 + ********************************************************************/ + +#ifndef _MULTI_QUEUE_D_ARY_HEAP_H +#define _MULTI_QUEUE_D_ARY_HEAP_H + +#include "device_grid.h" +#include "heap_type.h" +#include "multi_queue_d_ary_heap.tpp" +#include +#include + +// FIXME: Use unified heap node struct (HeapNodeId) and comparator (HeapNodeComparator) +// defined in heap_type.h. Currently, the MQ_IO is not compatible with them. Need a lot +// of refactoring in MQ_IO to make it work, which is left for another PR to clean it up. +using MQHeapNode = std::tuple; + +struct MQHeapNodeTupleComparator /* FIXME: Use HeapNodeComparator */ { + bool operator()(const MQHeapNode& u, const MQHeapNode& v) { + return std::get<0>(u) > std::get<0>(v); + } +}; + +template +class MultiQueueDAryHeap { + public: + using MQ_IO = MultiQueueIO; + + MultiQueueDAryHeap() { + set_num_threads_and_queues(1, 2); // Serial (#threads=1, #queues=2) by default + } + + MultiQueueDAryHeap(size_t num_threads, size_t num_queues) { + set_num_threads_and_queues(num_threads, num_queues); + } + + ~MultiQueueDAryHeap() {} + + void set_num_threads_and_queues(size_t num_threads, size_t num_queues) { + pq_.reset(); + // Note: BE AWARE that in MQ_IO interface, `num_queues` comes first, then `num_threads`! + pq_ = std::make_unique(num_queues, num_threads, 0 /*Dont care (batch size for only popBatch)*/); + } + + void init_heap(const DeviceGrid& grid) { + (void)grid; + // TODO: Reserve storage for MQ_IO + // Note: This function could be called before setting num_threads/num_queues + } + + bool try_pop(HeapNode& heap_node) { + auto tmp = pq_->tryPop(); + if (!tmp.has_value()) { + return false; + } else { + uint32_t node_id; + std::tie(heap_node.prio, node_id) = tmp.value(); // FIXME: eliminate type cast by modifying MQ_IO + heap_node.node = RRNodeId(node_id); + return true; + } + } + + void add_to_heap(const HeapNode& heap_node) { + HeapNodePriority prio = heap_node.prio; + uint32_t node = size_t(heap_node.node); + pq_->push({prio, node}); + } + + void push_back(const HeapNode& heap_node) { + HeapNodePriority prio = heap_node.prio; + uint32_t node = size_t(heap_node.node); + pq_->push({prio, node}); // FIXME: add to heap without maintaining the heap property + } + + void build_heap() { + // FIXME: restore the heap property after pushing back nodes + } + + bool is_valid() const { + return true; // FIXME: checking if the heap property is maintained or not + } + + void empty_heap() { + pq_->reset(); // TODO: check if adding clear function for MQ_IO is necessary + } + + bool is_empty_heap() const { + return (bool)(pq_->empty()); + } + + uint64_t get_num_pushes() const { + return pq_->getNumPushes(); + } + + uint64_t get_num_pops() const { + return pq_->getNumPops(); + } + + uint64_t get_heap_occupancy() const { + return pq_->getQueueOccupancy(); + } + + void reset() { + pq_->reset(); + } + +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + void set_min_priority_for_pop(const HeapNodePriority& minPrio) { + pq_->setMinPrioForPop(minPrio); + } +#endif + + private: + std::unique_ptr pq_; +}; + +#endif diff --git a/vpr/src/route/multi_queue_d_ary_heap.tpp b/vpr/src/route/multi_queue_d_ary_heap.tpp new file mode 100644 index 00000000000..7168762577e --- /dev/null +++ b/vpr/src/route/multi_queue_d_ary_heap.tpp @@ -0,0 +1,438 @@ +/******************************************************************** + * MultiQueue Implementation + * + * Originally authored by Guozheng Zhang, Gilead Posluns, and Mark C. Jeffrey + * Published at the 36th ACM Symposium on Parallelism in Algorithms and + * Architectures (SPAA), June 2024 + * + * Original source: https://github.com/mcj-group/cps + * + * This implementation and interface has been modified from the original to: + * - Support queue draining functionality + * - Enable integration with the VTR project + * + * The MultiQueue data structure provides an efficient concurrent priority + * queue implementation designed for parallel processing applications. + * + * Modified: February 2025 + ********************************************************************/ + +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include +#include "d_ary_heap.tpp" + +#define CACHELINE 64 + +// #define PERF 1 +#define MQ_IO_ENABLE_CLEAR_FOR_POP + +template< + unsigned D, + typename PQElement, + typename Comparator, + typename PrioType> +class MultiQueueIO { + using PQ = customized_d_ary_priority_queue, Comparator>; + Comparator compare; + + // Special value used to signify that there is no 'min' element in a PQ + // container. The user should ensure that they do not use this priority + // while using the MQ. + static constexpr PrioType EMPTY_PRIO = std::numeric_limits::max(); + + struct PQContainer { + uint64_t pushes = 0; + uint64_t pops = 0; + PQ pq; + std::atomic_flag queueLock = ATOMIC_FLAG_INIT; + std::atomic min{EMPTY_PRIO}; + + void lock() { + while (queueLock.test_and_set(std::memory_order_acquire)) + ; + } + bool try_lock() { return queueLock.test_and_set(std::memory_order_acquire); } + void unlock() { queueLock.clear(std::memory_order_release); } + + } __attribute__((aligned(CACHELINE))); + + std::vector< + PQContainer + // FIXME: Disabled this due to VTR not using Boost. There is a C++ way + // of doing this, but it requires making an aligned allocator + // class. May be a good idea to add to VTR util in the future. + // Should profile for performance first; may not be worth it. + // , boost::alignment::aligned_allocator + > + queues; + uint64_t NUM_QUEUES; + + // Termination: + // - numIdle records the number of threads that believe + // there are no more work to do. + // -numEmpty records number of queues that are empty + uint64_t threadNum; + std::atomic numIdle{0}; + std::atomic numEmpty; +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + std::atomic minPrioForPop{std::numeric_limits::max()}; +#endif + + uint64_t batchSize; + + public: + MultiQueueIO(uint64_t numQueues, uint64_t numThreads, uint64_t batch) + : queues(numQueues) + , NUM_QUEUES(numQueues) + , threadNum(numThreads) + , numEmpty(numQueues) + , batchSize(batch) { + assert((numQueues >= 2) && "numQueues must be set >= 2"); + } + +#ifdef PERF + uint64_t __attribute__((noinline)) ThreadLocalRandom() { +#else + uint64_t ThreadLocalRandom() { +#endif + // static thread_local std::mt19937_64 generator; + // std::uniform_real_distribution<> distribution(min,max); + // return distribution(generator); + static uint64_t modMask = NUM_QUEUES - 1; + static thread_local uint64_t x = pthread_self(); + uint64_t z = (x += UINT64_C(0x9E3779B97F4A7C15)); + z = (z ^ (z >> 30)) * UINT64_C(0xBF58476D1CE4E5B9); + z = (z ^ (z >> 27)) * UINT64_C(0x94D049BB133111EB); + return (z ^ (z >> 31)) & modMask; + } + +#ifdef PERF + void __attribute__((noinline)) pushInt(uint64_t queue, PQElement item) { + queues[queue].pq.push(item); + } +#endif + +#ifdef PERF + void __attribute__((noinline)) push(PQElement item) { +#else + inline void push(PQElement item) { +#endif + uint64_t queue; + while (true) { + queue = ThreadLocalRandom(); + if (!queues[queue].try_lock()) break; + } + auto& q = queues[queue]; + q.pushes++; + if (q.pq.empty()) + numEmpty.fetch_sub(1, std::memory_order_relaxed); +#ifdef PERF + pushInt(queue, item); +#else + q.pq.push(item); +#endif + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release); + q.unlock(); + } + +#ifdef PERF + void __attribute__((noinline)) pushBatch(uint64_t size, PQElement* items) { +#else + inline void pushBatch(uint64_t size, PQElement* items) { +#endif + uint64_t queue; + while (true) { + queue = ThreadLocalRandom(); + if (!queues[queue].try_lock()) break; + } + auto& q = queues[queue]; + q.pushes += size; + if (q.pq.empty()) + numEmpty.fetch_sub(1, std::memory_order_relaxed); + for (uint64_t i = 0; i < size; i++) { +#ifdef PERF + pushInt(queue, items[i]); +#else + q.pq.push(items[i]); +#endif + } + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release); + q.unlock(); + } + + // Simplified Termination detection idea from the 2021 MultiQueue paper: + // Repeatedly try popping and stop when numIdle >= threadNum, + // That is, stop when all threads agree that there are no more work +#ifdef PERF + boost::optional __attribute__((noinline)) tryPop() { +#else + inline std::optional tryPop() { +#endif + auto item = pop(); + if (item) return item; + + // increment count and keep on trying to pop + uint64_t num = numIdle.fetch_add(1, std::memory_order_relaxed) + 1; + do { + item = pop(); + if (item) break; + if (num >= threadNum) return {}; + + num = numIdle.load(std::memory_order_relaxed); + + } while (true); + + numIdle.fetch_sub(1, std::memory_order_relaxed); + return item; + } + +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + inline void setMinPrioForPop(PrioType newMinPrio) { + PrioType oldMinPrio = minPrioForPop.load(std::memory_order_relaxed); + while (compare({oldMinPrio, 0}, {newMinPrio, 0}) /* old > new */ && !minPrioForPop.compare_exchange_weak(oldMinPrio, newMinPrio)) + ; + } +#endif + +#ifdef PERF + boost::optional __attribute__((noinline)) pop() { +#else + inline std::optional pop() { +#endif + uint64_t poppingQueue = NUM_QUEUES; + while (true) { + // Pick the higher priority max of queue i and j + uint64_t i = ThreadLocalRandom(); + uint64_t j = ThreadLocalRandom(); + while (j == i) { + j = ThreadLocalRandom(); + } + + PrioType minI = queues[i].min.load(std::memory_order_acquire); + PrioType minJ = queues[j].min.load(std::memory_order_acquire); + + if (minI == EMPTY_PRIO && minJ == EMPTY_PRIO) { + uint64_t emptyQueues = numEmpty.load(std::memory_order_relaxed); + if (emptyQueues >= queues.size()) + break; + else + continue; + } + + if (minI != EMPTY_PRIO && minJ != EMPTY_PRIO) { + poppingQueue = compare({minJ, 0}, {minI, 0}) ? i : j; + } else if (minJ == EMPTY_PRIO) { + poppingQueue = i; + } else { + poppingQueue = j; + } + if (queues[poppingQueue].try_lock()) continue; + auto& q = queues[poppingQueue]; + if (!q.pq.empty()) { +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + PrioType minPrio = minPrioForPop.load(std::memory_order_acquire); + if (compare(q.pq.top(), {minPrio, 0})) { + q.pq.clear(); + // do not add `q.pops` on purpose + numEmpty.fetch_add(1, std::memory_order_relaxed); + q.min.store(EMPTY_PRIO, std::memory_order_release); + } else { +#endif + PQElement retItem = q.pq.top(); + q.pq.pop(); + q.pops++; + if (q.pq.empty()) + numEmpty.fetch_add(1, std::memory_order_relaxed); + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release); + q.unlock(); + return retItem; +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + } +#endif + } + q.unlock(); + } + return {}; + } + +#ifdef PERF + boost::optional __attribute__((noinline)) tryPopBatch(PQElement* ret) { +#else + inline std::optional tryPopBatch(PQElement* ret) { +#endif + auto item = popBatch(ret); + if (item) return item; + + // increment count and keep on trying to pop + uint64_t num = numIdle.fetch_add(1, std::memory_order_relaxed) + 1; + do { + item = popBatch(ret); + if (item) break; + if (num >= threadNum) return {}; + + num = numIdle.load(std::memory_order_relaxed); + + } while (true); + + numIdle.fetch_sub(1, std::memory_order_relaxed); + return item; + } + +#ifdef PERF + void __attribute__((noinline)) popInt(uint64_t queue, PQElement* ret) { + auto& q = queues[queue]; + *ret = q.pq.top(); + q.pq.pop(); + } +#endif + +#ifdef PERF + boost::optional __attribute__((noinline)) popBatch(PQElement* ret){ +#else + inline std::optional popBatch(PQElement* ret) { +#endif + uint64_t poppingQueue = NUM_QUEUES; + while (true) { + // Pick the higher priority max of queue i and j + uint64_t i = ThreadLocalRandom(); + uint64_t j = ThreadLocalRandom(); + while (j == i) { + j = ThreadLocalRandom(); + } + + PrioType minI = queues[i].min.load(std::memory_order_acquire); + PrioType minJ = queues[j].min.load(std::memory_order_acquire); + + if (minI == EMPTY_PRIO && minJ == EMPTY_PRIO) { + uint64_t emptyQueues = numEmpty.load(std::memory_order_relaxed); + if (emptyQueues >= queues.size()) + break; + else + continue; + } + + if (minI != EMPTY_PRIO && minJ != EMPTY_PRIO) { + poppingQueue = compare({minJ, 0}, {minI, 0}) ? i : j; + } else if (minJ == EMPTY_PRIO) { + poppingQueue = i; + } else { + poppingQueue = j; + } + if (queues[poppingQueue].try_lock()) continue; + auto& q = queues[poppingQueue]; + if (q.pq.empty()) { + q.unlock(); + continue; + } + + uint64_t num = 0; + for (num = 0; num < batchSize; num++) { + if (q.pq.empty()) break; +#ifdef PERF + popInt(poppingQueue, &ret[num]); +#else + ret[num] = q.pq.top(); + q.pq.pop(); +#endif + } + q.pops += num; + if (q.pq.empty()) + numEmpty.fetch_add(1, std::memory_order_relaxed); + q.min.store( + q.pq.size() > 0 + ? std::get<0>(q.pq.top()) + : EMPTY_PRIO, + std::memory_order_release); + q.unlock(); + if (num == 0) continue; + + return num; + } + return {}; +} + +inline uint64_t +getQueueOccupancy() const { + uint64_t maxOccupancy = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + maxOccupancy = std::max(maxOccupancy, queues[i].pq.size()); + } + return maxOccupancy; +} + +// Get the number of pushes to all queues. +// Note: this is not lock protected. +inline uint64_t getNumPushes() const { + uint64_t totalPushes = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + totalPushes += queues[i].pushes; + } + return totalPushes; +} + +// Get the number of pops to all queues. +// Note: this is not lock protected. +inline uint64_t getNumPops() const { + uint64_t totalPops = 0; + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + totalPops += queues[i].pops; + } + return totalPops; +} + +inline void stat() const { + std::cout << "total pushes " << getNumPushes() << "\n"; + std::cout << "total pops " << getNumPops() << "\n"; +} + +// Note: this is only called at the end of algorithm as a +// sanity check, therefore it is not lock protected. +inline bool empty() const { + for (uint i = 0; i < NUM_QUEUES; i++) { + if (!queues[i].pq.empty()) { + return false; + } + } + return true; +} + +// Resets the MultiQueue to a state as if it was reinitialized. +// This must be called before using the MQ again after using TypPop(). +// Note: this assumes the queues are already empty and unlocked. +inline void reset() { + for (uint64_t i = 0; i < NUM_QUEUES; i++) { + assert(queues[i].pq.empty() && "reset() assumes empty queues"); + assert((queues[i].queueLock.test(std::memory_order_relaxed) == 0) + && "reset() assumes unlocked queues"); + queues[i].pushes = 0; + queues[i].pops = 0; + queues[i].min.store(EMPTY_PRIO, std::memory_order_relaxed); + } + numIdle.store(0, std::memory_order_relaxed); + numEmpty.store(NUM_QUEUES, std::memory_order_relaxed); +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + minPrioForPop.store(std::numeric_limits::max(), std::memory_order_relaxed); +#endif +} +} +; diff --git a/vpr/src/route/netlist_routers.h b/vpr/src/route/netlist_routers.h index d64477f03ad..eb8a220f51f 100644 --- a/vpr/src/route/netlist_routers.h +++ b/vpr/src/route/netlist_routers.h @@ -3,7 +3,7 @@ /** @file Interface for a netlist router. * * A NetlistRouter manages the required bits of state to complete the netlist routing process, - * which requires finding a path for every connection in the netlist using a ConnectionRouter. + * which requires finding a path for every connection in the netlist using a SerialConnectionRouter. * This needs to be an interface because there may be different netlist routing schedules, * i.e. parallel or net-decomposing routers. * @@ -19,7 +19,6 @@ #include "NetPinTimingInvalidator.h" #include "clustered_netlist_utils.h" #include "connection_based_routing_fwd.h" -#include "connection_router.h" #include "globals.h" #include "heap_type.h" #include "netlist_fwd.h" diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 618f4edc67b..24913fad6d5 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -2,6 +2,7 @@ #include #include "physical_types_util.h" +#include "vpr_utils.h" #include "vtr_log.h" /** @@ -130,8 +131,8 @@ void report_overused_nodes(const Netlist<>& net_list, int y = rr_graph.node_ylow(node_id); int layer_num = rr_graph.node_layer(node_id); switch (node_type) { - case IPIN: - case OPIN: + case e_rr_type::IPIN: + case e_rr_type::OPIN: report_overused_ipin_opin(os, node_id, rr_node_to_net_map); @@ -139,12 +140,12 @@ void report_overused_nodes(const Netlist<>& net_list, x -= g_vpr_ctx.device().grid.get_physical_type({x, y, layer_num})->width; y -= g_vpr_ctx.device().grid.get_physical_type({x, y, layer_num})->width; break; - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: report_overused_chanx_chany(os, node_id); break; - case SOURCE: - case SINK: + case e_rr_type::SOURCE: + case e_rr_type::SINK: report_overused_source_sink(os, node_id); report_sinks = true; break; @@ -493,7 +494,7 @@ static void print_block_pins_nets(std::ostream& os, } for (int pin = pin_num_range.low; pin <= pin_num_range.high; pin++) { - t_rr_type rr_type = (get_pin_type_from_pin_physical_num(physical_type, pin) == DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN; + e_rr_type rr_type = (get_pin_type_from_pin_physical_num(physical_type, pin) == DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; RRNodeId node_id = get_pin_rr_node_id(rr_graph.node_lookup(), physical_type, layer, root_x, root_y, pin); // When flat router is enabled, RR Node chains collapse into a single node. Thus, when // looking up the RR Node ID, it may return an invalid node ID. In this case, we skip @@ -503,10 +504,10 @@ static void print_block_pins_nets(std::ostream& os, } VTR_ASSERT(node_id.is_valid()); auto search_result = rr_node_to_net_map.find(node_id); - if (rr_type == t_rr_type::OPIN) { + if (rr_type == e_rr_type::OPIN) { os << " OPIN - "; } else { - VTR_ASSERT(rr_type == t_rr_type::IPIN); + VTR_ASSERT(rr_type == e_rr_type::IPIN); os << " IPIN - "; } os << "RRNodeId: " << size_t(node_id) << " - Physical Num: " << pin << "\n"; diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp new file mode 100644 index 00000000000..f3111f156f0 --- /dev/null +++ b/vpr/src/route/parallel_connection_router.cpp @@ -0,0 +1,489 @@ +#include "parallel_connection_router.h" + +#include +#include "route_tree.h" +#include "rr_graph_fwd.h" + +/** Post-target pruning: Prune a given node (do not explore it) if the cost of + * the best possible path from the source, through the node, to the target is + * higher than the cost of the best path found to the target so far. Cited from + * the FPT'24 conference paper (more details can also be found there). */ +static inline bool post_target_prune_node(float new_total_cost, + float new_back_cost, + float best_back_cost_to_target, + const t_conn_cost_params& params) { + // Divide out the astar_fac, then multiply to get determinism + // This is a correction factor to the forward cost to make the total + // cost an under-estimate. + // TODO: Should investigate creating a heuristic function that is + // gaurenteed to be an under-estimate. + // NOTE: Found experimentally that using the original heuristic to order + // the nodes in the queue and then post-target pruning based on the + // under-estimating heuristic has better runtime. + float expected_cost = new_total_cost - new_back_cost; + float new_expected_cost = expected_cost; + // h1 = (h - offset) * fac + // Protection for division by zero + if (params.astar_fac > 0.001) + // To save time, does not recompute the heuristic, just divideds out + // the astar_fac. + new_expected_cost /= params.astar_fac; + new_expected_cost = new_expected_cost - params.post_target_prune_offset; + // Max function to prevent the heuristic from going negative + new_expected_cost = std::max(0.f, new_expected_cost); + new_expected_cost *= params.post_target_prune_fac; + if ((new_back_cost + new_expected_cost) > best_back_cost_to_target) + return true; + // NOTE: we do NOT check for equality here. Equality does not matter for + // determinism when draining the queues (may just lead to a bit more work). + return false; +} + +/** Pre-push pruning: when iterating over the neighbors of u, this function + * determines whether a path through u to its neighbor node v has a better + * backward cost than the best path to v found so far (breaking ties if needed). + * Cited from the FPT'24 conference paper (more details can also be found there). + */ +// TODO: Once we have a heap node struct, clean this up! +static inline bool prune_node(RRNodeId inode, + float new_total_cost, + float new_back_cost, + RREdgeId new_prev_edge, + RRNodeId target_node, + vtr::vector& rr_node_route_inf_, + const t_conn_cost_params& params) { + // Post-target pruning: After the target is reached the first time, should + // use the heuristic to help drain the queues. + if (inode != target_node) { + t_rr_node_route_inf* target_route_inf = &rr_node_route_inf_[target_node]; + float best_back_cost_to_target = target_route_inf->backward_path_cost; + if (post_target_prune_node(new_total_cost, new_back_cost, best_back_cost_to_target, params)) + return true; + } + + // Backwards Pruning + // NOTE: When going to the target, we only want to prune on the truth. + // The queues handle using the heuristic to explore nodes faster. + t_rr_node_route_inf* route_inf = &rr_node_route_inf_[inode]; + float best_back_cost = route_inf->backward_path_cost; + if (new_back_cost > best_back_cost) + return true; + // In the case of a tie, need to be picky about whether to prune or not in + // order to get determinism. + // FIXME: This may not be thread safe. If the best node changes while this + // function is being called, we may have the new_back_cost and best + // prev_edge's being from different heap nodes! + // TODO: Move this to within the lock (the rest can stay for performance). + if (new_back_cost == best_back_cost) { +#ifndef NON_DETERMINISTIC_PRUNING + // With deterministic pruning, cannot always prune on ties. + // In the case of a true tie, just prune, no need to explore neightbors + RREdgeId best_prev_edge = route_inf->prev_edge; + if (new_prev_edge == best_prev_edge) + return true; + // When it comes to invalid edge IDs, in the case of a tied back cost, + // always try to keep the invalid edge ID (likely the start node). + // TODO: Verify this. + // If the best previous edge is invalid, prune + if (!best_prev_edge.is_valid()) + return true; + // If the new previous edge is invalid (assuming the best is not), accept + if (!new_prev_edge.is_valid()) + return false; + // Finally, if this node is not coming from a preferred edge, prune + // Deterministic version prefers a given EdgeID, so a unique path is returned since, + // in the case of a tie, a determinstic path wins. + // Is first preferred over second? + auto is_preferred_edge = [](RREdgeId first, RREdgeId second) { + return first < second; + }; + if (!is_preferred_edge(new_prev_edge, best_prev_edge)) + return true; +#else + std::ignore = new_prev_edge; + // When we do not care about determinism, always prune on equality. + return true; +#endif + } + + // If all above passes, do not prune. + return false; +} + +/** Post-pop pruning: After node u is popped from the queue, this function + * decides whether to explore the neighbors of u or to prune. Initially, it + * performs Post-Target Pruning based on the stopping criterion. Then, the + * current total estimated cost of the path through node u (f_u) is compared + * to the best total cost so far (most recently pushed) for that node and, + * if the two are different, the node u is pruned. During the wave expansion, + * u may be pushed to the queue multiple times. For example, node u may be + * pushed to the queue and then, before u is popped from the queue, a better + * path to u may be found and pushed to the queue. Here we are using f_u as + * an optimistic identifier to check if the pair (u, f_u) is the most recently + * pushed element for node u. This reduces redundant work. + * Cited from the FPT'24 conference paper (more details can also be found there). + */ +static inline bool should_not_explore_neighbors(RRNodeId inode, + float new_total_cost, + float new_back_cost, + RRNodeId target_node, + vtr::vector& rr_node_route_inf_, + const t_conn_cost_params& params) { +#ifndef NON_DETERMINISTIC_PRUNING + // For deterministic pruning, cannot enforce anything on the total cost since + // traversal order is not gaurenteed. However, since total cost is used as a + // "key" to signify that this node is the last node that was pushed, we can + // just check for equality. There is a chance this may cause some duplicates + // for the deterministic case, but thats ok they will be handled. + // TODO: Maybe consider having the non-deterministic version do this too. + if (new_total_cost != rr_node_route_inf_[inode].path_cost) + return true; +#else + // For non-deterministic pruning, can greadily just ignore nodes with higher + // total cost. + if (new_total_cost > rr_node_route_inf_[inode].path_cost) + return true; +#endif + // Perform post-target pruning. If this is not done, there is a chance that + // several duplicates of a node is in the queue that will never reach the + // target better than what we found and they will explore all of their + // neighbors which is not good. This is done before obtaining the lock to + // prevent lock contention where possible. + if (inode != target_node) { + float best_back_cost_to_target = rr_node_route_inf_[target_node].backward_path_cost; + if (post_target_prune_node(new_total_cost, new_back_cost, best_back_cost_to_target, params)) + return true; + } + return false; +} + +template +void ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) { + // Assign the thread task function parameters to atomic variables + this->sink_node_ = &sink_node; + this->cost_params_ = const_cast(&cost_params); + this->bounding_box_ = const_cast(&bounding_box); + this->target_bb_ = const_cast(&target_bb); + + // Synchronize at the barrier before executing a new thread task + this->thread_barrier_.wait(); + + // Main thread executes a new thread task (helper threads are doing the same in the background) + this->timing_driven_find_single_shortest_path_from_heap_thread_func(*this->sink_node_, + *this->cost_params_, + *this->bounding_box_, + *this->target_bb_, 0); + + // Synchronize at the barrier before resetting the heap + this->thread_barrier_.wait(); + + // Collect the number of heap pushes and pops + this->router_stats_->heap_pushes += this->heap_.get_num_pushes(); + this->router_stats_->heap_pops += this->heap_.get_num_pops(); + + // Reset the heap for the next connection + this->heap_.reset(); +} + +template +void ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper(const size_t thread_idx) { + this->thread_barrier_.init(); + while (true) { + this->thread_barrier_.wait(); + if (this->is_router_destroying_ == true) { + return; + } else { + timing_driven_find_single_shortest_path_from_heap_thread_func(*this->sink_node_, + *this->cost_params_, + *this->bounding_box_, + *this->target_bb_, + thread_idx); + } + this->thread_barrier_.wait(); + } +} + +template +void ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap_thread_func(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb, + const size_t thread_idx) { + HeapNode cheapest; + while (this->heap_.try_pop(cheapest)) { + // Pop a new inode with the cheapest total cost in current route tree to be expanded on + const auto& [new_total_cost, inode] = cheapest; + + // Check if we should explore the neighbors of this node + if (should_not_explore_neighbors(inode, new_total_cost, this->rr_node_route_inf_[inode].backward_path_cost, sink_node, this->rr_node_route_inf_, cost_params)) { + continue; + } + + // Get the current RR node info within a critical section to prevent data races + obtainSpinLock(inode); + + RTExploredNode current; + current.index = inode; + current.backward_path_cost = this->rr_node_route_inf_[inode].backward_path_cost; + current.prev_edge = this->rr_node_route_inf_[inode].prev_edge; + current.R_upstream = this->rr_node_route_inf_[inode].R_upstream; + + releaseLock(inode); + + // Double check now just to be sure that we should still explore neighbors + // NOTE: A good question is what happened to the uniqueness pruning. The idea + // is that at this point it does not matter. Basically any duplicates + // will act like they were the last one pushed in. This may create some + // duplicates, but it is a simple way of handling this situation. + // It may be worth investigating a better way to do this in the future. + // TODO: This is still doing post-target pruning. May want to investigate + // if this is worth doing. + // TODO: should try testing without the pruning below and see if anything changes. + if (should_not_explore_neighbors(inode, new_total_cost, current.backward_path_cost, sink_node, this->rr_node_route_inf_, cost_params)) { + continue; + } + + // Adding nodes to heap + timing_driven_expand_neighbours(current, cost_params, bounding_box, sink_node, target_bb, thread_idx); + } +} + +template +void ParallelConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx) { + /* Puts all the rr_nodes adjacent to current on the heap. */ + + // For each node associated with the current heap element, expand all of it's neighbors + auto edges = this->rr_nodes_.edge_range(current.index); + + // This is a simple prefetch that prefetches: + // - RR node data reachable from this node + // - rr switch data to reach those nodes from this node. + // + // This code will be a NOP on compiler targets that do not have a + // builtin to emit prefetch instructions. + // + // This code will be a NOP on CPU targets that lack prefetch instructions. + // All modern x86 and ARM64 platforms provide prefetch instructions. + // + // This code delivers ~6-8% reduction in wallclock time when running Titan + // benchmarks, and was specifically measured against the gsm_switch and + // directrf vtr_reg_weekly running in high effort. + // + // - directrf_stratixiv_arch_timing.blif + // - gsm_switch_stratixiv_arch_timing.blif + // + for (RREdgeId from_edge : edges) { + RRNodeId to_node = this->rr_nodes_.edge_sink_node(from_edge); + this->rr_nodes_.prefetch_node(to_node); + + int switch_idx = this->rr_nodes_.edge_switch(from_edge); + VTR_PREFETCH(&this->rr_switch_inf_[switch_idx], 0, 0); + } + + for (RREdgeId from_edge : edges) { + RRNodeId to_node = this->rr_nodes_.edge_sink_node(from_edge); + timing_driven_expand_neighbour(current, + from_edge, + to_node, + cost_params, + bounding_box, + target_node, + target_bb, + thread_idx); + } +} + +template +void ParallelConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, + RREdgeId from_edge, + RRNodeId to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx) { + // BB-pruning + // Disable BB-pruning if RCV is enabled, as this can make it harder for circuits with high negative hold slack to resolve this + // TODO: Only disable pruning if the net has negative hold slack, maybe go off budgets + if (!inside_bb(to_node, bounding_box)) { + // Note: Logging are disabled for parallel connection router + return; /* Node is outside (expanded) bounding box. */ + } + + /* Prune away IPINs that lead to blocks other than the target one. Avoids * + * the issue of how to cost them properly so they don't get expanded before * + * more promising routes, but makes route-through (via CLBs) impossible. * + * Change this if you want to investigate route-throughs. */ + if (target_node != RRNodeId::INVALID()) { + e_rr_type to_type = this->rr_graph_->node_type(to_node); + if (to_type == e_rr_type::IPIN) { + // Check if this IPIN leads to the target block + // IPIN's of the target block should be contained within it's bounding box + int to_xlow = this->rr_graph_->node_xlow(to_node); + int to_ylow = this->rr_graph_->node_ylow(to_node); + int to_layer = this->rr_graph_->node_layer(to_node); + int to_xhigh = this->rr_graph_->node_xhigh(to_node); + int to_yhigh = this->rr_graph_->node_yhigh(to_node); + if (to_xlow < target_bb.xmin + || to_ylow < target_bb.ymin + || to_xhigh > target_bb.xmax + || to_yhigh > target_bb.ymax + || to_layer < target_bb.layer_min + || to_layer > target_bb.layer_max) { + // Note: Logging are disabled for parallel connection router + return; + } + } + } + // Note: Logging are disabled for parallel connection router + + timing_driven_add_to_heap(cost_params, + current, + to_node, + from_edge, + target_node, + thread_idx); +} + +template +void ParallelConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, + const RTExploredNode& current, + RRNodeId to_node, + const RREdgeId from_edge, + RRNodeId target_node, + size_t thread_idx) { + const RRNodeId& from_node = current.index; + + // Initialize the neighbor RTExploredNode + RTExploredNode next; + next.R_upstream = current.R_upstream; + next.index = to_node; + next.prev_edge = from_edge; + next.total_cost = std::numeric_limits::infinity(); // Not used directly + next.backward_path_cost = current.backward_path_cost; + + this->evaluate_timing_driven_node_costs(&next, cost_params, from_node, target_node); + + float new_total_cost = next.total_cost; + float new_back_cost = next.backward_path_cost; + + // To further reduce lock contention, we add a cheap read-only check before acquiring the lock, motivated by Shun et al. + if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, this->rr_node_route_inf_, cost_params)) { + return; + } + + obtainSpinLock(to_node); + + if (prune_node(to_node, new_total_cost, new_back_cost, from_edge, target_node, this->rr_node_route_inf_, cost_params)) { + releaseLock(to_node); + return; + } + + update_cheapest(next, thread_idx); + + releaseLock(to_node); + + if (to_node == target_node) { +#ifdef MQ_IO_ENABLE_CLEAR_FOR_POP + if (multi_queue_direct_draining_) { + this->heap_.set_min_priority_for_pop(new_total_cost); + } +#endif + return; + } + this->heap_.add_to_heap({new_total_cost, to_node}); +} + +template +void ParallelConnectionRouter::add_route_tree_node_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) { + const auto& device_ctx = g_vpr_ctx.device(); + const RRNodeId inode = rt_node.inode; + float backward_path_cost = cost_params.criticality * rt_node.Tdel; + float R_upstream = rt_node.R_upstream; + + /* Don't push to heap if not in bounding box: no-op for serial router, important for parallel router */ + if (!inside_bb(rt_node.inode, net_bb)) + return; + + // After budgets are loaded, calculate delay cost as described by RCV paper + /* R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While + * Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of + * Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008.*/ + + if (!this->rcv_path_manager.is_enabled()) { + float expected_cost = this->router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); + float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); + VTR_LOGV_DEBUG(this->router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", + inode, + tot_cost, + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, this->is_flat_).c_str()); + + if (prune_node(inode, tot_cost, backward_path_cost, RREdgeId::INVALID(), target_node, this->rr_node_route_inf_, cost_params)) { + return; + } + add_to_mod_list(inode, 0 /*main thread*/); + this->rr_node_route_inf_[inode].path_cost = tot_cost; + this->rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); + this->rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; + this->rr_node_route_inf_[inode].R_upstream = R_upstream; + this->heap_.push_back({tot_cost, inode}); + } + // Note: RCV is not supported by parallel connection router +} + +std::unique_ptr make_parallel_connection_router(e_heap_type heap_type, + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat, + int multi_queue_num_threads, + int multi_queue_num_queues, + bool multi_queue_direct_draining) { + switch (heap_type) { + case e_heap_type::BINARY_HEAP: + return std::make_unique>( + grid, + router_lookahead, + rr_nodes, + rr_graph, + rr_rc_data, + rr_switch_inf, + rr_node_route_inf, + is_flat, + multi_queue_num_threads, + multi_queue_num_queues, + multi_queue_direct_draining); + case e_heap_type::FOUR_ARY_HEAP: + return std::make_unique>( + grid, + router_lookahead, + rr_nodes, + rr_graph, + rr_rc_data, + rr_switch_inf, + rr_node_route_inf, + is_flat, + multi_queue_num_threads, + multi_queue_num_queues, + multi_queue_direct_draining); + default: + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Unknown heap_type %d", + heap_type); + } +} diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h new file mode 100644 index 00000000000..18d873e0c6e --- /dev/null +++ b/vpr/src/route/parallel_connection_router.h @@ -0,0 +1,443 @@ +#ifndef _PARALLEL_CONNECTION_ROUTER_H +#define _PARALLEL_CONNECTION_ROUTER_H + +#include "connection_router.h" + +#include "d_ary_heap.h" +#include "multi_queue_d_ary_heap.h" + +#include +#include +#include +#include + +/** + * @brief Spin lock implementation using std::atomic_flag + * + * It is used per RR node for protecting the update to node costs + * to prevent data races. Since different threads rarely work on + * the same node simultaneously, this fine-grained locking strategy + * of one lock per node reduces contention. + */ +class spin_lock_t { + /** Atomic flag used for the lock implementation */ + std::atomic_flag lock_ = ATOMIC_FLAG_INIT; + + public: + /** + * @brief Acquires the spin lock, repeatedly attempting until successful + */ + void acquire() { + while (std::atomic_flag_test_and_set_explicit(&lock_, std::memory_order_acquire)) + ; + } + + /** + * @brief Releases the spin lock, allowing other threads to acquire it + */ + void release() { + std::atomic_flag_clear_explicit(&lock_, std::memory_order_release); + } +}; + +/** + * @brief Thread barrier implementation using std::mutex + * + * It ensures all participating threads reach a synchronization point + * before any are allowed to proceed further. It uses a mutex and + * condition variable to coordinate thread synchronization. + */ +class barrier_mutex_t { + // FIXME: Try std::barrier (since C++20) to replace this mutex barrier + std::mutex mutex_; + std::condition_variable cv_; + size_t count_; + size_t max_count_; + size_t generation_ = 0; + + public: + /** + * @brief Constructs a barrier for a specific number of threads + * @param num_threads Number of threads that must call wait() before + * any thread is allowed to proceed + */ + explicit barrier_mutex_t(size_t num_threads) + : count_(num_threads) + , max_count_(num_threads) {} + + /** + * @brief Blocks the calling thread until all threads have called wait() + * + * When the specified number of threads have called this method, all + * threads are unblocked and the barrier is reset for the next use. + */ + void wait() { + std::unique_lock lock{mutex_}; + size_t gen = generation_; + if (--count_ == 0) { + generation_++; + count_ = max_count_; + cv_.notify_all(); + } else { + cv_.wait(lock, [this, &gen] { return gen != generation_; }); + } + } +}; + +/** + * @brief Spin-based thread barrier implementation using std::atomic + * + * It ensures all participating threads reach a synchronization point + * before any are allowed to proceed further. It uses atomic operations + * to implement Sense-Reversing Centralized Barrier (from Section 5.2.1 + * of Michael L. Scott's textbook) without using mutex locks. + */ +class barrier_spin_t { + /** Number of threads that must reach the barrier */ + size_t num_threads_ = 1; + + /** Atomic counter tracking the number of threads that have arrived at the barrier */ + std::atomic count_ = 0; + + /** Global sense shared by all participating threads */ + std::atomic sense_ = false; + + /** Thread-local sense value for each participating thread */ + inline static thread_local bool local_sense_ = false; + + public: + /** + * @brief Constructs a barrier for a specific number of threads + * @param num_threads Number of threads that must call wait() before + * any thread is allowed to proceed + */ + explicit barrier_spin_t(size_t num_threads) { num_threads_ = num_threads; } + + /** + * @brief Initializes the thread-local sense flag + * @note Should be called by each thread before first using the barrier. + */ + void init() { + local_sense_ = false; + } + + /** + * @brief Blocks the calling thread until all threads have called wait() + * + * Uses a sense-reversing algorithm to synchronize threads. The last thread + * to arrive unblocks all waiting threads. This method avoids using locks or + * condition variables, making it potentially more efficient for short waits. + */ + void wait() { + bool s = !local_sense_; + local_sense_ = s; + size_t num_arrivals = count_.fetch_add(1) + 1; + if (num_arrivals == num_threads_) { + count_.store(0); + sense_.store(s); + } else { + while (sense_.load() != s) + ; // spin until the last thread arrives + } + } +}; + +using barrier_t = barrier_spin_t; // Using the spin-based thread barrier + +/** + * @class ParallelConnectionRouter implements the MultiQueue-based parallel connection + * router (FPT'24) based on the ConnectionRouter interface. + * @details The details of the algorithm can be found from the conference paper: + * A. Singer, H. Yan, G. Zhang, M. Jeffrey, M. Stojilovic and V. Betz, "MultiQueue-Based FPGA Routing: + * Relaxed A* Priority Ordering for Improved Parallelism," Int. Conf. on Field-Programmable Technology, + * Dec. 2024. + */ +template +class ParallelConnectionRouter : public ConnectionRouter> { + public: + ParallelConnectionRouter( + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat, + int multi_queue_num_threads, + int multi_queue_num_queues, + bool multi_queue_direct_draining) + : ConnectionRouter>(grid, router_lookahead, rr_nodes, rr_graph, rr_rc_data, rr_switch_inf, rr_node_route_inf, is_flat) + , modified_rr_node_inf_(multi_queue_num_threads) + , thread_barrier_(multi_queue_num_threads) + , is_router_destroying_(false) + , locks_(rr_node_route_inf.size()) + , multi_queue_direct_draining_(multi_queue_direct_draining) { + // Set the MultiQueue parameters + this->heap_.set_num_threads_and_queues(multi_queue_num_threads, multi_queue_num_queues); + // Initialize the thread barrier + this->thread_barrier_.init(); + // Instantiate (multi_queue_num_threads - 1) helper threads + this->sub_threads_.resize(multi_queue_num_threads - 1); + for (int i = 0; i < multi_queue_num_threads - 1; ++i) { + this->sub_threads_[i] = std::thread(&ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper, this, i + 1 /*0: main thread*/); + this->sub_threads_[i].detach(); + } + } + + ~ParallelConnectionRouter() { + this->is_router_destroying_ = true; // signal the helper threads to exit + this->thread_barrier_.wait(); // wait until all threads reach the barrier + + VTR_LOG("Parallel Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", + std::chrono::duration(this->path_search_cumulative_time).count()); + } + + /** + * @brief Clears the modified list per thread + * @note Should be called after reset_path_costs have been called + */ + void clear_modified_rr_node_info() final { + for (auto& thread_visited_rr_nodes : this->modified_rr_node_inf_) { + thread_visited_rr_nodes.clear(); + } + } + + /** + * @brief Resets modified data in rr_node_route_inf based on modified_rr_node_inf + */ + void reset_path_costs() final { + // Reset the node info stored in rr_node_route_inf variable + for (const auto& thread_visited_rr_nodes : this->modified_rr_node_inf_) { + ::reset_path_costs(thread_visited_rr_nodes); + } + } + + /** + * @brief [Not supported] Enables RCV feature + * @note RCV for parallel connection router has not been implemented yet. + * Thus this function is not expected to be called. + */ + void set_rcv_enabled(bool) final { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "RCV for parallel connection router not yet implemented. Not expected to be called."); + } + + /** + * @brief [Not supported] Finds shortest paths from the route tree rooted at rt_root to all sinks available + * @note This function has not been implemented yet and is not the focus of parallel connection router. + * Thus this function is not expected to be called. + */ + vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( + const RouteTreeNode&, + const t_conn_cost_params&, + const t_bb&, + RouterStats&, + const ConnectionParameters&) final { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_route_tree not yet implemented (nor is the focus of the parallel connection router). Not expected to be called."); + } + + protected: + /** + * @brief Marks that data associated with rr_node 'inode' has + * been modified, and needs to be reset in reset_path_costs + */ + inline void add_to_mod_list(RRNodeId inode, size_t thread_idx) { + if (std::isinf(this->rr_node_route_inf_[inode].path_cost)) { + this->modified_rr_node_inf_[thread_idx].push_back(inode); + } + } + + /** + * @brief Updates the route path to the node `cheapest.index` + * via the path from `from_node` via `cheapest.prev_edge` + */ + inline void update_cheapest(RTExploredNode& cheapest, size_t thread_idx) { + const RRNodeId& inode = cheapest.index; + add_to_mod_list(inode, thread_idx); + this->rr_node_route_inf_[inode].prev_edge = cheapest.prev_edge; + this->rr_node_route_inf_[inode].path_cost = cheapest.total_cost; + this->rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; + } + + /** + * @brief Obtains the per-node spin locks for protecting node cost updates + */ + inline void obtainSpinLock(const RRNodeId& inode) { + this->locks_[size_t(inode)].acquire(); + } + + /** + * @brief Releases the per-node spin lock, allowing other + * threads working on the same node to obtain it + */ + inline void releaseLock(const RRNodeId& inode) { + this->locks_[size_t(inode)].release(); + } + + /** + * @brief Finds the single shortest path from current heap to the sink node in the RR graph + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ + void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) final; + + /** + * @brief Helper thread wrapper function, passed to std::thread instantiation and running a + * while-loop to obtain and execute new helper thread tasks until the main thread signals the + * threads to exit + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ + void timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper( + const size_t thread_idx); + + /** + * @brief Helper thread task function to find the single shortest path from current heap to + * the sink node in the RR graph + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ + void timing_driven_find_single_shortest_path_from_heap_thread_func( + RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb, + const size_t thread_idx); + + /** + * @brief Expands each neighbor of the current node in the wave expansion + * @param current Current node being explored + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_node Target node ID to route to + * @param target_bb Prune IPINs that lead to blocks other than the target block + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ + void timing_driven_expand_neighbours( + const RTExploredNode& current, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx); + + /** + * @brief Conditionally adds to_node to the router heap (via path from current.index via from_edge) + * @note RR nodes outside bounding box specified in bounding_box are not added to the heap. + * @param current Current node being explored + * @param from_edge Edge between the current node and the neighbor node + * @param to_node Neighbor node to be expanded + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_node Target node ID to route to + * @param target_bb Prune IPINs that lead to blocks other than the target block + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ + void timing_driven_expand_neighbour( + const RTExploredNode& current, + RREdgeId from_edge, + RRNodeId to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb, + size_t thread_idx); + + /** + * @brief Adds to_node to the heap, and also adds any nodes which are connected by non-configurable edges + * @param cost_params Cost function parameters + * @param current Current node being explored + * @param to_node Neighbor node to be expanded + * @param from_edge Edge between the current node and the neighbor node + * @param target_node Target node ID to route to + * @param thread_idx Thread ID (0 means main thread; 1 to #threads-1 means helper threads) + */ + void timing_driven_add_to_heap( + const t_conn_cost_params& cost_params, + const RTExploredNode& current, + RRNodeId to_node, + RREdgeId from_edge, + RRNodeId target_node, + size_t thread_idx); + + /** + * @brief Unconditionally adds rt_node to the heap + * @note If you want to respect rt_node->re_expand that is the caller's responsibility. + * @todo Consider moving this function into the ConnectionRouter class after checking + * the different prune functions of the serial and parallel connection routers. + * @param rt_node RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param net_bb Do not push to heap if not in bounding box + */ + void add_route_tree_node_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) final; + + /** + * @brief [Not supported] Finds shortest paths from current heap to all nodes in the RR graph + * @note This function has not been implemented yet and is not the focus of parallel connection router. + * Thus this function is not expected to be called. + */ + vtr::vector timing_driven_find_all_shortest_paths_from_heap( + const t_conn_cost_params&, + const t_bb&) final { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "timing_driven_find_all_shortest_paths_from_heap not yet implemented (nor is the focus of this project). Not expected to be called."); + } + + /** Node IDs of modified nodes in rr_node_route_inf for each thread*/ + std::vector> modified_rr_node_inf_; + + /** Helper threads */ + std::vector sub_threads_; + + /** Thread barrier for synchronization */ + barrier_t thread_barrier_; + + /** Signal for helper threads to exit */ + std::atomic is_router_destroying_; + + /** Fine-grained locks per RR node */ + std::vector locks_; + + /** Is queue draining optimization enabled? */ + bool multi_queue_direct_draining_; + + //@{ + /** Atomic parameters of thread task functions to pass from main thread to helper threads */ + std::atomic sink_node_; + std::atomic cost_params_; + std::atomic bounding_box_; + std::atomic target_bb_; + //@} +}; + +/** Construct a parallel connection router that uses the specified heap type. + * This function is not used, but removing it will result in "undefined reference" + * errors since heap type specializations won't get emitted from parallel_connection_router.cpp + * without it. + * The alternative is moving all ParallelConnectionRouter fn implementations into the header. */ +std::unique_ptr make_parallel_connection_router( + e_heap_type heap_type, + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat, + int multi_queue_num_threads, + int multi_queue_num_queues, + bool multi_queue_direct_draining); + +#endif /* _PARALLEL_CONNECTION_ROUTER_H */ diff --git a/vpr/src/route/partition_tree.cpp b/vpr/src/route/partition_tree.cpp index 38ee7abc2dd..497f887cf74 100644 --- a/vpr/src/route/partition_tree.cpp +++ b/vpr/src/route/partition_tree.cpp @@ -44,7 +44,7 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& * Do this for every step with only given nets, because each cutline takes some nets out * of the game, so if we just built a global lookup it wouldn't yield accurate results. * - * VPR's bounding boxes include the borders (see ConnectionRouter::timing_driven_expand_neighbour()) + * VPR's bounding boxes include the borders (see SerialConnectionRouter::timing_driven_expand_neighbour()) * so try to include x=bb.xmax, y=bb.ymax etc. when calculating things. */ int width = x2 - x1 + 1; int height = y2 - y1 + 1; diff --git a/vpr/src/route/partition_tree.h b/vpr/src/route/partition_tree.h index 6bf68be04b8..d30d5121492 100644 --- a/vpr/src/route/partition_tree.h +++ b/vpr/src/route/partition_tree.h @@ -1,6 +1,6 @@ #pragma once -#include "connection_router.h" +#include "serial_connection_router.h" #include "netlist_fwd.h" #include "router_stats.h" @@ -27,7 +27,7 @@ inline Side operator!(const Side& rhs) { } /** Part of a net in the context of the \ref DecompNetlistRouter. Sinks and routing resources - * routable/usable by the \ref ConnectionRouter are constrained to ones inside clipped_bb + * routable/usable by the \ref SerialConnectionRouter are constrained to ones inside clipped_bb * (\see inside_bb()) */ class VirtualNet { public: diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index 098ae85ba5e..e5c3284426a 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -7,16 +7,16 @@ #include "route.h" #include "route_common.h" #include "route_debug.h" -#include "route_export.h" #include "route_profiling.h" #include "route_utils.h" +#include "rr_graph.h" #include "vtr_time.h" bool route(const Netlist<>& net_list, int width_fac, const t_router_opts& router_opts, const t_analysis_opts& analysis_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, NetPinsMatrix& net_delay, std::shared_ptr timing_info, @@ -40,12 +40,11 @@ bool route(const Netlist<>& net_list, graph_type = e_graph_type::GLOBAL; graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); - /* Branch on tileable routing */ - if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + if (det_routing_arch.directionality == UNI_DIRECTIONAL && det_routing_arch.tileable) { graph_type = e_graph_type::UNIDIR_TILEABLE; } - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } /* Set the channel widths */ @@ -123,7 +122,7 @@ bool route(const Netlist<>& net_list, route_budgets budgeting_inf(net_list, is_flat); // This needs to be called before filling intra-cluster lookahead maps to ensure that the intra-cluster lookahead maps are initialized. - const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, + const RouterLookahead* router_lookahead = get_cached_router_lookahead(det_routing_arch, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, @@ -143,7 +142,7 @@ bool route(const Netlist<>& net_list, mut_router_lookahead->compute_intra_tile(); } route_ctx.cached_router_lookahead_.set(cache_key, std::move(mut_router_lookahead)); - router_lookahead = get_cached_router_lookahead(*det_routing_arch, + router_lookahead = get_cached_router_lookahead(det_routing_arch, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, @@ -622,12 +621,13 @@ bool route(const Netlist<>& net_list, "total_internal_heap_pushes: %zu total_internal_heap_pops: %zu total_external_heap_pushes: %zu total_external_heap_pops: %zu ", router_stats.intra_cluster_node_pushes, router_stats.intra_cluster_node_pops, router_stats.inter_cluster_node_pushes, router_stats.inter_cluster_node_pops); - for (int node_type_idx = 0; node_type_idx < t_rr_type::NUM_RR_TYPES; node_type_idx++) { - VTR_LOG("total_external_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.inter_cluster_node_type_cnt_pushes[node_type_idx]); - VTR_LOG("total_external_%s_pops: %zu ", rr_node_typename[node_type_idx], router_stats.inter_cluster_node_type_cnt_pops[node_type_idx]); - VTR_LOG("total_internal_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.intra_cluster_node_type_cnt_pushes[node_type_idx]); - VTR_LOG("total_internal_%s_pops: %zu ", rr_node_typename[node_type_idx], router_stats.intra_cluster_node_type_cnt_pops[node_type_idx]); - VTR_LOG("rt_node_%s_pushes: %zu ", rr_node_typename[node_type_idx], router_stats.rt_node_pushes[node_type_idx]); + + for (e_rr_type rr_type : RR_TYPES) { + VTR_LOG("total_external_%s_pushes: %zu ", rr_node_typename[rr_type], router_stats.inter_cluster_node_type_cnt_pushes[rr_type]); + VTR_LOG("total_external_%s_pops: %zu ", rr_node_typename[rr_type], router_stats.inter_cluster_node_type_cnt_pops[rr_type]); + VTR_LOG("total_internal_%s_pushes: %zu ", rr_node_typename[rr_type], router_stats.intra_cluster_node_type_cnt_pushes[rr_type]); + VTR_LOG("total_internal_%s_pops: %zu ", rr_node_typename[rr_type], router_stats.intra_cluster_node_type_cnt_pops[rr_type]); + VTR_LOG("rt_node_%s_pushes: %zu ", rr_node_typename[rr_type], router_stats.rt_node_pushes[rr_type]); } } VTR_LOG("\n"); diff --git a/vpr/src/route/route.h b/vpr/src/route/route.h index 082a417008e..5d519228d0d 100644 --- a/vpr/src/route/route.h +++ b/vpr/src/route/route.h @@ -21,7 +21,7 @@ bool route(const Netlist<>& net_list, int width_fac, const t_router_opts& router_opts, const t_analysis_opts& analysis_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, NetPinsMatrix& net_delay, std::shared_ptr timing_info, diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 3b720c5d76f..3f6d574b601 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -3,8 +3,8 @@ #include "atom_netlist_utils.h" #include "connection_router_interface.h" #include "describe_rr_node.h" -#include "draw_global.h" #include "route_common.h" +#include "logic_types.h" #include "physical_types_util.h" #include "route_export.h" @@ -64,6 +64,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally(); static void adjust_one_rr_occ_and_acc_cost(RRNodeId inode, int add_or_sub, float acc_fac); static vtr::vector load_is_clock_net(const Netlist<>& net_list, + const LogicalModels& models, bool is_flat); static bool classes_in_same_block(ParentBlockId blk_id, int first_class_ptc_num, int second_class_ptc_num, bool is_flat); @@ -98,13 +99,11 @@ void restore_routing(vtr::vector>& best_ro * Use this number as a routing serial number to ensure that programming * * changes do not break the router. */ void get_serial_num(const Netlist<>& net_list) { - int serial_num; - - auto& route_ctx = g_vpr_ctx.routing(); - auto& device_ctx = g_vpr_ctx.device(); + const auto& route_ctx = g_vpr_ctx.routing(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - serial_num = 0; + int serial_num = 0; for (auto net_id : net_list.nets()) { if (!route_ctx.route_trees[net_id]) @@ -117,7 +116,7 @@ void get_serial_num(const Netlist<>& net_list) { serial_num -= rr_graph.node_ptc_num(inode) * (size_t(net_id) + 1) * 10; - serial_num -= rr_graph.node_type(inode) * (size_t(net_id) + 1) * 100; + serial_num -= (size_t)rr_graph.node_type(inode) * (size_t(net_id) + 1) * 100; serial_num %= 2000000000; /* Prevent overflow */ } } @@ -268,7 +267,7 @@ void init_route_structs(const Netlist<>& net_list, net_list, is_flat); - route_ctx.is_clock_net = load_is_clock_net(net_list, is_flat); + route_ctx.is_clock_net = load_is_clock_net(net_list, device_ctx.arch->models, is_flat); route_ctx.route_bb = load_route_bb(net_list, bb_factor); route_ctx.rr_blk_source = load_rr_clb_sources(device_ctx.rr_graph, @@ -359,7 +358,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() { clb_opins_used_locally[blk_id].resize((int)type->class_inf.size()); - if (is_io_type(type)) continue; + if (type->is_io()) continue; const auto [pin_low, pin_high] = get_pin_range_for_block(blk_id); @@ -465,7 +464,7 @@ static vtr::vector> load_net_rr_terminals(con inode = rr_graph.node_lookup().find_node(blk_loc.loc.layer, blk_loc.loc.x, blk_loc.loc.y, - SOURCE, + e_rr_type::SOURCE, iclass); } else { vtr::Rect tile_bb = grid.get_tile_bb({blk_loc.loc.x, @@ -476,7 +475,7 @@ static vtr::vector> load_net_rr_terminals(con tile_bb.ymin(), tile_bb.xmax(), tile_bb.ymax(), - SINK, + e_rr_type::SINK, iclass); VTR_ASSERT_SAFE(sink_nodes.size() == 1); inode = sink_nodes[0]; @@ -568,7 +567,7 @@ static vtr::vector> load_rr_clb_sources(con bool is_flat) { vtr::vector> rr_blk_source; - t_rr_type rr_type; + e_rr_type rr_type; rr_blk_source.resize(net_list.blocks().size()); @@ -583,10 +582,10 @@ static vtr::vector> load_rr_clb_sources(con blk_loc = get_block_loc(blk_id, is_flat); auto class_type = get_class_type_from_class_physical_num(type, iclass); if (class_type == DRIVER) { - rr_type = SOURCE; + rr_type = e_rr_type::SOURCE; } else { VTR_ASSERT(class_type == RECEIVER); - rr_type = SINK; + rr_type = e_rr_type::SINK; } RRNodeId inode = rr_graph.node_lookup().find_node(blk_loc.loc.layer, @@ -605,11 +604,12 @@ static vtr::vector> load_rr_clb_sources(con } static vtr::vector load_is_clock_net(const Netlist<>& net_list, + const LogicalModels& models, bool is_flat) { vtr::vector is_clock_net(net_list.nets().size()); auto& atom_ctx = g_vpr_ctx.atom(); - std::set clock_nets = find_netlist_physical_clock_nets(atom_ctx.netlist()); + std::set clock_nets = find_netlist_physical_clock_nets(atom_ctx.netlist(), models); for (auto net_id : net_list.nets()) { std::size_t net_id_num = std::size_t(net_id); @@ -706,7 +706,7 @@ t_bb load_net_route_bb(const Netlist<>& net_list, bb_factor = std::min(bb_factor, max_dim); RRNodeId driver_rr = RRNodeId(route_ctx.net_rr_terminals[net_id][0]); - VTR_ASSERT(rr_graph.node_type(driver_rr) == SOURCE); + VTR_ASSERT(rr_graph.node_type(driver_rr) == e_rr_type::SOURCE); VTR_ASSERT(rr_graph.node_xlow(driver_rr) <= rr_graph.node_xhigh(driver_rr)); VTR_ASSERT(rr_graph.node_ylow(driver_rr) <= rr_graph.node_yhigh(driver_rr)); @@ -721,7 +721,7 @@ t_bb load_net_route_bb(const Netlist<>& net_list, auto net_sinks = net_list.net_sinks(net_id); for (size_t ipin = 1; ipin < net_sinks.size() + 1; ++ipin) { //Start at 1 since looping through sinks RRNodeId sink_rr = RRNodeId(route_ctx.net_rr_terminals[net_id][ipin]); - VTR_ASSERT(rr_graph.node_type(sink_rr) == SINK); + VTR_ASSERT(rr_graph.node_type(sink_rr) == e_rr_type::SINK); VTR_ASSERT(rr_graph.node_xlow(sink_rr) <= rr_graph.node_xhigh(sink_rr)); VTR_ASSERT(rr_graph.node_ylow(sink_rr) <= rr_graph.node_yhigh(sink_rr)); @@ -842,7 +842,7 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f for (iconn = 0; iconn < num_edges; iconn++) { RRNodeId to_node = rr_graph.edge_sink_node(RRNodeId(from_node), iconn); - VTR_ASSERT(rr_graph.node_type(RRNodeId(to_node)) == OPIN); + VTR_ASSERT(rr_graph.node_type(RRNodeId(to_node)) == e_rr_type::OPIN); //Add the OPIN to the heap according to it's congestion cost cost = get_rr_cong_cost(to_node, pres_fac); @@ -857,7 +857,7 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f VTR_ASSERT(heap->try_pop(heap_head_node)); const RRNodeId& inode = heap_head_node.node; - VTR_ASSERT(rr_graph.node_type(inode) == OPIN); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::OPIN); adjust_one_rr_occ_and_acc_cost(inode, 1, acc_fac); route_ctx.clb_opins_used_locally[blk_id][iclass][ipin] = inode; diff --git a/vpr/src/route/route_net.cpp b/vpr/src/route/route_net.cpp index b8ba1227322..4d89ae04cfe 100644 --- a/vpr/src/route/route_net.cpp +++ b/vpr/src/route/route_net.cpp @@ -228,8 +228,8 @@ size_t calculate_wirelength_available() { size_t available_wirelength = 0; // But really what's happening is that this for loop iterates over every node and determines the available wirelength for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { - const t_rr_type channel_type = rr_graph.node_type(rr_id); - if (channel_type == CHANX || channel_type == CHANY) { + const e_rr_type channel_type = rr_graph.node_type(rr_id); + if (channel_type == e_rr_type::CHANX || channel_type == e_rr_type::CHANY) { available_wirelength += rr_graph.node_capacity(rr_id) * rr_graph.node_length(rr_id); } } diff --git a/vpr/src/route/route_net.tpp b/vpr/src/route/route_net.tpp index 0e8c4c268a5..1a5715b7341 100644 --- a/vpr/src/route/route_net.tpp +++ b/vpr/src/route/route_net.tpp @@ -17,7 +17,7 @@ /** Attempt to route a single net. * - * @param router The ConnectionRouter instance + * @param router The ConnectionRouterType instance * @param net_list Input netlist * @param net_id * @param itry # of iteration @@ -40,8 +40,8 @@ * @param should_setup Should we reset/prune the existing route tree first? * @param sink_mask Which sinks to route? Assumed all sinks if nullopt, otherwise a mask of [1..num_sinks+1] where set bits request the sink to be routed * @return NetResultFlags for this net */ -template -inline NetResultFlags route_net(ConnectionRouter& router, +template +inline NetResultFlags route_net(ConnectionRouterType& router, const Netlist<>& net_list, const ParentNetId& net_id, int itry, @@ -140,6 +140,8 @@ inline NetResultFlags route_net(ConnectionRouter& router, t_conn_cost_params cost_params; cost_params.astar_fac = router_opts.astar_fac; cost_params.astar_offset = router_opts.astar_offset; + cost_params.post_target_prune_fac = router_opts.post_target_prune_fac; + cost_params.post_target_prune_offset = router_opts.post_target_prune_offset; cost_params.bend_cost = router_opts.bend_cost; cost_params.pres_fac = pres_fac; cost_params.delay_budget = ((budgeting_inf.if_set()) ? &conn_delay_budget : nullptr); @@ -285,8 +287,8 @@ inline NetResultFlags route_net(ConnectionRouter& router, /** Route to a "virtual sink" in the netlist which corresponds to the start point * of the global clock network. */ -template -inline NetResultFlags pre_route_to_clock_root(ConnectionRouter& router, +template +inline NetResultFlags pre_route_to_clock_root(ConnectionRouterType& router, ParentNetId net_id, const Netlist<>& net_list, RRNodeId sink_node, @@ -382,7 +384,7 @@ inline NetResultFlags pre_route_to_clock_root(ConnectionRouter& router, * In the process, update global pathfinder costs, rr_node_route_inf and extend the global RouteTree * for this net. * - * @param router The ConnectionRouter instance + * @param router The ConnectionRouterType instance * @param net_list Input netlist * @param net_id * @param itarget # of this connection in the net (only used for debug output) @@ -399,8 +401,8 @@ inline NetResultFlags pre_route_to_clock_root(ConnectionRouter& router, * @param is_flat * @param net_bb Bounding box for the net (Routing resources outside net_bb will not be used) * @return NetResultFlags for this sink to be bubbled up through route_net */ -template -inline NetResultFlags route_sink(ConnectionRouter& router, +template +inline NetResultFlags route_sink(ConnectionRouterType& router, const Netlist<>& net_list, ParentNetId net_id, unsigned itarget, diff --git a/vpr/src/route/route_profiling.cpp b/vpr/src/route/route_profiling.cpp index 7ae6f7c813e..dd87ee57e28 100644 --- a/vpr/src/route/route_profiling.cpp +++ b/vpr/src/route/route_profiling.cpp @@ -148,7 +148,7 @@ struct Congested_node_types { void congestion_analysis() { #if 0 // each type indexes into array which holds the congestion for that type - std::vector congestion_per_type((size_t)NUM_RR_TYPES, 0); + std::vector congestion_per_type((size_t)e_rr_type::NUM_RR_TYPES, 0); // print out specific node information if congestion for type is low enough int total_congestion = 0; @@ -164,7 +164,7 @@ void congestion_analysis() { constexpr int specific_node_print_threshold = 5; Congested_node_types congested; - for (int type = SOURCE; type < NUM_RR_TYPES; ++type) { + for (int type = SOURCE; type < e_rr_type::NUM_RR_TYPES; ++type) { float congestion_percentage = (float)congestion_per_type[type] / (float) total_congestion * 100; VTR_LOG(" %6s: %10.6f %\n", node_typename[type], congestion_percentage); // nodes of that type need specific printing diff --git a/vpr/src/route/route_tree.cpp b/vpr/src/route/route_tree.cpp index 799fa185fbd..cc8f5a8fee3 100644 --- a/vpr/src/route/route_tree.cpp +++ b/vpr/src/route/route_tree.cpp @@ -29,7 +29,7 @@ RouteTreeNode::RouteTreeNode(RRNodeId _inode, RRSwitchId _parent_switch, RouteTr } /** Print information about this subtree to stdout. */ -void RouteTreeNode::print(void) const { +void RouteTreeNode::print() const { print_x(0); } @@ -360,7 +360,7 @@ vtr::optional RouteTree::find_by_rr_id(RRNodeId rr_node) c * - invalid timing values * - congested SINKs * Returns true if OK. */ -bool RouteTree::is_valid(void) const { +bool RouteTree::is_valid() const { return is_valid_x(*_root); } @@ -396,7 +396,7 @@ bool RouteTree::is_valid_x(const RouteTreeNode& rt_node) const { return false; } - if (rr_graph.node_type(inode) == SINK) { // sink, must not be congested and must not have fanouts + if (rr_graph.node_type(inode) == e_rr_type::SINK) { // sink, must not be congested and must not have fanouts int occ = route_ctx.rr_node_route_inf[inode].occ(); int capacity = rr_graph.node_capacity(inode); if (rt_node._next != nullptr && rt_node._next->_parent == &rt_node) { @@ -563,9 +563,9 @@ RouteTree::add_subtree_from_heap(RTExploredNode* hptr, int target_net_pin_index, e_rr_type node_type = rr_graph.node_type(new_branch_inodes[i]); // If is_flat is enabled, IPINs should be added, since they are used for intra-cluster routing - if (node_type == IPIN && !is_flat) { + if (node_type == e_rr_type::IPIN && !is_flat) { new_node->re_expand = false; - } else if (node_type == SINK) { + } else if (node_type == e_rr_type::SINK) { new_node->re_expand = false; new_node->net_pin_index = target_net_pin_index; // net pin index is invalid for non-SINK nodes } else { @@ -626,7 +626,7 @@ void RouteTree::add_non_configurable_nodes(RouteTreeNode* rt_node, add_node(rt_node, new_node); new_node->net_pin_index = OPEN; - if (rr_graph.node_type(to_rr_node) == IPIN && !is_flat) { + if (rr_graph.node_type(to_rr_node) == e_rr_type::IPIN && !is_flat) { new_node->re_expand = false; } else { new_node->re_expand = true; @@ -650,7 +650,7 @@ RouteTree::prune(CBRR& connections_inf, std::vector* non_config_node_set_us std::unique_lock write_lock(_write_mutex); - VTR_ASSERT_MSG(rr_graph.node_type(root().inode) == SOURCE, "Root of route tree must be SOURCE"); + VTR_ASSERT_MSG(rr_graph.node_type(root().inode) == e_rr_type::SOURCE, "Root of route tree must be SOURCE"); VTR_ASSERT_MSG(_net_id, "RouteTree must be constructed using a ParentNetId"); @@ -709,7 +709,7 @@ RouteTree::prune_x(RouteTreeNode& rt_node, CBRR& connections_inf, bool force_pru } }); - if (rr_graph.node_type(rt_node.inode) == SINK) { + if (rr_graph.node_type(rt_node.inode) == e_rr_type::SINK) { if (!force_prune) { //Valid path to sink @@ -824,7 +824,7 @@ RouteTree::prune_x(RouteTreeNode& rt_node, CBRR& connections_inf, bool force_pru /** Remove all sinks and mark the remaining nodes as un-expandable. * This is used after routing a clock net. * TODO: is this function doing anything? Try running without it */ -void RouteTree::freeze(void) { +void RouteTree::freeze() { std::unique_lock write_lock(_write_mutex); return freeze_x(*_root); } @@ -835,7 +835,7 @@ void RouteTree::freeze_x(RouteTreeNode& rt_node) { const auto& rr_graph = device_ctx.rr_graph; remove_child_if(rt_node, [&](RouteTreeNode& child) { - if (rr_graph.node_type(child.inode) == SINK) { + if (rr_graph.node_type(child.inode) == e_rr_type::SINK) { VTR_LOGV_DEBUG(f_router_debug, "Removing sink %d from route tree\n", child.inode); return true; @@ -860,7 +860,7 @@ void RouteTree::freeze_x(RouteTreeNode& rt_node) { * "to" a sink is a usage of the set, but the code used to check if the * edge "from" the SINK, which shouldn't exist, was "configurable". This * might be some faulty code / unnecessary check carried over.) */ -std::vector RouteTree::get_non_config_node_set_usage(void) const { +std::vector RouteTree::get_non_config_node_set_usage() const { auto& device_ctx = g_vpr_ctx.device(); std::vector usage(device_ctx.rr_non_config_node_sets.size(), 0); @@ -871,7 +871,7 @@ std::vector RouteTree::get_non_config_node_set_usage(void) const { if (it == rr_to_nonconf.end()) continue; - if (device_ctx.rr_graph.node_type(rt_node.inode) == SINK) { + if (device_ctx.rr_graph.node_type(rt_node.inode) == e_rr_type::SINK) { if (device_ctx.rr_graph.rr_switch_inf(rt_node.parent_switch).configurable()) { usage[it->second] += 1; } diff --git a/vpr/src/route/route_utilization.cpp b/vpr/src/route/route_utilization.cpp index 66b03751451..bb9c5e736e3 100644 --- a/vpr/src/route/route_utilization.cpp +++ b/vpr/src/route/route_utilization.cpp @@ -1,15 +1,14 @@ #include "route_utilization.h" #include "globals.h" -#include "draw_types.h" -#include "draw_global.h" +#include "vpr_utils.h" -vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool is_print) { - VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); +vtr::Matrix calculate_routing_usage(e_rr_type rr_type, bool is_flat, bool is_print) { + VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& route_ctx = g_vpr_ctx.routing(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& route_ctx = g_vpr_ctx.routing(); vtr::Matrix usage({{device_ctx.grid.width(), device_ctx.grid.height()}}, 0.); @@ -41,8 +40,8 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool (void)is_print; #endif - if (rr_type == CHANX) { - VTR_ASSERT(rr_graph.node_type(rr_node) == CHANX); + if (rr_type == e_rr_type::CHANX) { + VTR_ASSERT(rr_graph.node_type(rr_node) == e_rr_type::CHANX); VTR_ASSERT(rr_graph.node_ylow(rr_node) == rr_graph.node_yhigh(rr_node)); int y = rr_graph.node_ylow(rr_node); @@ -50,8 +49,8 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool usage[x][y] += route_ctx.rr_node_route_inf[rr_node].occ(); } } else { - VTR_ASSERT(rr_type == CHANY); - VTR_ASSERT(rr_graph.node_type(rr_node) == CHANY); + VTR_ASSERT(rr_type == e_rr_type::CHANY); + VTR_ASSERT(rr_graph.node_type(rr_node) == e_rr_type::CHANY); VTR_ASSERT(rr_graph.node_xlow(rr_node) == rr_graph.node_xhigh(rr_node)); int x = rr_graph.node_xlow(rr_node); @@ -63,9 +62,9 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool return usage; } -vtr::Matrix calculate_routing_avail(t_rr_type rr_type) { +vtr::Matrix calculate_routing_avail(e_rr_type rr_type) { //Calculate the number of available resources in each x/y channel - VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); + VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; @@ -74,16 +73,16 @@ vtr::Matrix calculate_routing_avail(t_rr_type rr_type) { for (const RRNodeId& rr_node : rr_graph.nodes()) { const short& rr_node_capacity = rr_graph.node_capacity(rr_node); - if (rr_graph.node_type(rr_node) == CHANX && rr_type == CHANX) { - VTR_ASSERT(rr_graph.node_type(rr_node) == CHANX); + if (rr_graph.node_type(rr_node) == e_rr_type::CHANX && rr_type == e_rr_type::CHANX) { + VTR_ASSERT(rr_graph.node_type(rr_node) == e_rr_type::CHANX); VTR_ASSERT(rr_graph.node_ylow(rr_node) == rr_graph.node_yhigh(rr_node)); int y = rr_graph.node_ylow(rr_node); for (int x = rr_graph.node_xlow(rr_node); x <= rr_graph.node_xhigh(rr_node); ++x) { avail[x][y] += rr_node_capacity; } - } else if (rr_graph.node_type(rr_node) == CHANY && rr_type == CHANY) { - VTR_ASSERT(rr_graph.node_type(rr_node) == CHANY); + } else if (rr_graph.node_type(rr_node) == e_rr_type::CHANY && rr_type == e_rr_type::CHANY) { + VTR_ASSERT(rr_graph.node_type(rr_node) == e_rr_type::CHANY); VTR_ASSERT(rr_graph.node_xlow(rr_node) == rr_graph.node_xhigh(rr_node)); int x = rr_graph.node_xlow(rr_node); diff --git a/vpr/src/route/route_utilization.h b/vpr/src/route/route_utilization.h index ba8d6995738..194df6deb14 100644 --- a/vpr/src/route/route_utilization.h +++ b/vpr/src/route/route_utilization.h @@ -4,7 +4,7 @@ #include "draw_types.h" #include "draw_global.h" -vtr::Matrix calculate_routing_avail(t_rr_type rr_type); +vtr::Matrix calculate_routing_avail(e_rr_type rr_type); /** * @brief: Calculates and returns the usage over the entire grid for the specified @@ -15,7 +15,7 @@ vtr::Matrix calculate_routing_avail(t_rr_type rr_type); * @param only_visible: If true, only record the usage of rr_nodes on layers that are visible according to the current * drawing settings. */ -vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool is_print); +vtr::Matrix calculate_routing_usage(e_rr_type rr_type, bool is_flat, bool is_print); float routing_util(float used, float avail); #endif diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index aab9e952315..198d64197e7 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -15,6 +15,7 @@ #include "route_debug.h" #include "VprTimingGraphResolver.h" +#include "rr_graph.h" #include "tatum/TimingReporter.hpp" bool check_net_delays(const Netlist<>& net_list, NetPinsMatrix& net_delay) { @@ -219,8 +220,9 @@ void generate_route_timing_reports(const t_router_opts& router_opts, auto& timing_ctx = g_vpr_ctx.timing(); auto& atom_ctx = g_vpr_ctx.atom(); const auto& blk_loc_registry = g_vpr_ctx.placement().blk_loc_registry(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); @@ -465,7 +467,7 @@ vtr::vector>> set_net /** Wrapper for create_rr_graph() with extra checks */ void try_graph(int width_fac, const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, const std::vector& directs, @@ -478,8 +480,8 @@ void try_graph(int width_fac, graph_type = e_graph_type::GLOBAL; graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } /* Set the channel widths */ diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index 19f14e7cdb2..5cac4fbb045 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -143,7 +143,7 @@ vtr::vector>> set_net /** Wrapper for create_rr_graph() with extra checks */ void try_graph(int width_fac, const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, const std::vector& directs, diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index d88b0024517..30180eb7e14 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -88,6 +88,8 @@ bool RouterDelayProfiler::calculate_delay(RRNodeId source_node, cost_params.criticality = 1.; cost_params.astar_fac = router_opts.router_profiler_astar_fac; cost_params.astar_offset = router_opts.astar_offset; + cost_params.post_target_prune_fac = router_opts.post_target_prune_fac; + cost_params.post_target_prune_offset = router_opts.post_target_prune_offset; cost_params.bend_cost = router_opts.bend_cost; route_budgets budgeting_inf(net_list_, is_flat_); @@ -101,9 +103,6 @@ bool RouterDelayProfiler::calculate_delay(RRNodeId source_node, -1, false, std::unordered_map()); - if (size_t(sink_node) == 778060 && size_t(source_node) == 14) { - router_.set_router_debug(true); - } std::tie(found_path, std::ignore, cheapest) = router_.timing_driven_route_connection_from_route_tree( tree.root(), sink_node, @@ -163,6 +162,8 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src cost_params.criticality = 1.; cost_params.astar_fac = router_opts.astar_fac; cost_params.astar_offset = router_opts.astar_offset; + cost_params.post_target_prune_fac = router_opts.post_target_prune_fac; + cost_params.post_target_prune_offset = router_opts.post_target_prune_offset; cost_params.bend_cost = router_opts.bend_cost; /* This function is called during placement. Thus, the flat routing option should be disabled. */ //TODO: Placement is run with is_flat=false. However, since is_flat is passed, det_routing_arch should @@ -174,7 +175,7 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src /*segment_inf=*/{}, is_flat); - ConnectionRouter router( + SerialConnectionRouter router( device_ctx.grid, *router_lookahead, device_ctx.rr_graph.rr_nodes(), @@ -244,7 +245,7 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src void alloc_routing_structs(const t_chan_width& chan_width, const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, bool is_flat) { @@ -256,9 +257,9 @@ void alloc_routing_structs(const t_chan_width& chan_width, if (router_opts.route_type == GLOBAL) { graph_type = e_graph_type::GLOBAL; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_type = (det_routing_arch.directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); /* Branch on tileable routing */ - if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + if (det_routing_arch.directionality == UNI_DIRECTIONAL && det_routing_arch.tileable) { graph_type = e_graph_type::UNIDIR_TILEABLE; } } diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h index ca855720d85..082349a9a07 100644 --- a/vpr/src/route/router_delay_profiling.h +++ b/vpr/src/route/router_delay_profiling.h @@ -2,7 +2,7 @@ #define ROUTER_DELAY_PROFILING_H_ #include "vpr_types.h" -#include "connection_router.h" +#include "serial_connection_router.h" #include @@ -43,7 +43,7 @@ class RouterDelayProfiler { private: const Netlist<>& net_list_; RouterStats router_stats_; - ConnectionRouter router_; + SerialConnectionRouter router_; vtr::NdMatrix min_delays_; // [physical_type_idx][from_layer][to_layer][dx][dy] bool is_flat_; }; @@ -54,7 +54,7 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src void alloc_routing_structs(const t_chan_width& chan_width, const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, std::vector& segment_inf, const std::vector& directs, bool is_flat); diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead/router_lookahead.cpp similarity index 97% rename from vpr/src/route/router_lookahead.cpp rename to vpr/src/route/router_lookahead/router_lookahead.cpp index 240aeafbd61..fb2849cecf6 100644 --- a/vpr/src/route/router_lookahead.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead.cpp @@ -71,9 +71,9 @@ std::pair ClassicLookahead::get_expected_delay_and_cong(RRNodeId n auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type rr_type = rr_graph.node_type(node); + e_rr_type rr_type = rr_graph.node_type(node); - if (rr_type == CHANX || rr_type == CHANY) { + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { auto [num_segs_same_dir, num_segs_ortho_dir] = get_expected_segs_to_target(node, target_node); auto cost_index = rr_graph.node_cost_index(node); @@ -97,7 +97,7 @@ std::pair ClassicLookahead::get_expected_delay_and_cong(RRNodeId n + ipin_data.T_linear; return std::make_pair(params.criticality * Tdel, (1 - params.criticality) * cong_cost); - } else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (rr_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return std::make_pair(0., device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ @@ -139,9 +139,9 @@ static std::pair get_expected_segs_to_target(RRNodeId inode, RRNodeId float inv_length = device_ctx.rr_indexed_data[cost_index].inv_length; int ortho_cost_index = device_ctx.rr_indexed_data[cost_index].ortho_cost_index; float ortho_inv_length = device_ctx.rr_indexed_data[RRIndexedDataId(ortho_cost_index)].inv_length; - t_rr_type rr_type = rr_graph.node_type(inode); + e_rr_type rr_type = rr_graph.node_type(inode); - if (rr_type == CHANX) { + if (rr_type == e_rr_type::CHANX) { ylow = rr_graph.node_ylow(inode); xhigh = rr_graph.node_xhigh(inode); xlow = rr_graph.node_xlow(inode); diff --git a/vpr/src/route/router_lookahead.h b/vpr/src/route/router_lookahead/router_lookahead.h similarity index 100% rename from vpr/src/route/router_lookahead.h rename to vpr/src/route/router_lookahead/router_lookahead.h diff --git a/vpr/src/route/router_lookahead_compressed_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp similarity index 96% rename from vpr/src/route/router_lookahead_compressed_map.cpp rename to vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp index 4c50beb175e..e45593f68e8 100644 --- a/vpr/src/route/router_lookahead_compressed_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp @@ -146,14 +146,14 @@ static void compute_router_wire_compressed_lookahead(const std::vector> sample_nodes; + std::map> sample_nodes; std::vector chan_types; if (segment_inf.parallel_axis == X_AXIS) - chan_types.push_back(CHANX); + chan_types.push_back(e_rr_type::CHANX); else if (segment_inf.parallel_axis == Y_AXIS) - chan_types.push_back(CHANY); + chan_types.push_back(e_rr_type::CHANY); else //Both for BOTH_AXIS segments and special segments such as clock_networks we want to search in both directions. - chan_types.insert(chan_types.end(), {CHANX, CHANY}); + chan_types.insert(chan_types.end(), {e_rr_type::CHANX, e_rr_type::CHANY}); for (e_rr_type chan_type : chan_types) { util::t_routing_cost_map routing_cost_map = util::get_routing_cost_map(longest_seg_length, @@ -180,7 +180,7 @@ static void compute_router_wire_compressed_lookahead(const std::vector CompressedMapLookahead::get_expected_delay_and_cong(RRNo float expected_cong_cost = std::numeric_limits::infinity(); e_rr_type from_type = rr_graph.node_type(from_node); - if (from_type == SOURCE || from_type == OPIN) { + if (from_type == e_rr_type::SOURCE || from_type == e_rr_type::OPIN) { //When estimating costs from a SOURCE/OPIN we look-up to find which wire types (and the //cost to reach them) in src_opin_delays. Once we know what wire types are //reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final @@ -472,7 +472,7 @@ std::pair CompressedMapLookahead::get_expected_delay_and_cong(RRNo .c_str()) .c_str()); - } else if (from_type == CHANX || from_type == CHANY) { + } else if (from_type == e_rr_type::CHANX || from_type == e_rr_type::CHANY) { //When estimating costs from a wire, we directly look-up the result in the wire lookahead (f_wire_cost_map) auto from_cost_index = rr_graph.node_cost_index(from_node); @@ -502,7 +502,7 @@ std::pair CompressedMapLookahead::get_expected_delay_and_cong(RRNo .c_str()); expected_delay_cost = cost_entry.delay * params.criticality; expected_cong_cost = cost_entry.congestion * (1 - params.criticality); - } else if (from_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (from_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return std::make_pair(0., device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ return std::make_pair(0., 0.); diff --git a/vpr/src/route/router_lookahead_compressed_map.h b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h similarity index 100% rename from vpr/src/route/router_lookahead_compressed_map.h rename to vpr/src/route/router_lookahead/router_lookahead_compressed_map.h diff --git a/vpr/src/route/router_lookahead_cost_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_cost_map.cpp similarity index 100% rename from vpr/src/route/router_lookahead_cost_map.cpp rename to vpr/src/route/router_lookahead/router_lookahead_cost_map.cpp diff --git a/vpr/src/route/router_lookahead_cost_map.h b/vpr/src/route/router_lookahead/router_lookahead_cost_map.h similarity index 100% rename from vpr/src/route/router_lookahead_cost_map.h rename to vpr/src/route/router_lookahead/router_lookahead_cost_map.h diff --git a/vpr/src/route/router_lookahead_extended_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp similarity index 97% rename from vpr/src/route/router_lookahead_extended_map.cpp rename to vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp index 2f3964b47b5..0dabadb438b 100644 --- a/vpr/src/route/router_lookahead_extended_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_extended_map.cpp @@ -2,18 +2,15 @@ #include #include -#include #include "connection_router_interface.h" -#include "rr_node.h" +#include "describe_rr_node.h" #include "router_lookahead_map_utils.h" #include "router_lookahead_sampling.h" #include "globals.h" -#include "vtr_math.h" +#include "vpr_utils.h" #include "vtr_time.h" #include "vtr_geometry.h" -#include "echo_files.h" -#include "rr_graph.h" #include "route_common.h" #include "route_debug.h" @@ -113,7 +110,7 @@ std::pair ExtendedMapLookahead::get_src_opin_cost(RRNodeId from_no const util::t_reachable_wire_inf& reachable_wire_inf = kv.second; util::Cost_Entry cost_entry; - if (reachable_wire_inf.wire_rr_type == SINK) { + if (reachable_wire_inf.wire_rr_type == e_rr_type::SINK) { //Some pins maybe reachable via a direct (OPIN -> IPIN) connection. //In the lookahead, we treat such connections as 'special' wire types //with no delay/congestion cost @@ -153,7 +150,7 @@ float ExtendedMapLookahead::get_chan_ipin_delays(RRNodeId to_node) const { auto& rr_graph = device_ctx.rr_graph; e_rr_type to_type = rr_graph.node_type(to_node); - VTR_ASSERT(to_type == SINK || to_type == IPIN); + VTR_ASSERT(to_type == e_rr_type::SINK || to_type == e_rr_type::IPIN); auto to_tile_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(to_node), rr_graph.node_ylow(to_node), @@ -202,9 +199,9 @@ std::pair ExtendedMapLookahead::get_expected_delay_and_cong(RRNode dy = to_y - from_y; e_rr_type from_type = rr_graph.node_type(from_node); - if (from_type == SOURCE || from_type == OPIN) { + if (from_type == e_rr_type::SOURCE || from_type == e_rr_type::OPIN) { return this->get_src_opin_cost(from_node, dx, dy, to_layer_num, params); - } else if (from_type == IPIN) { + } else if (from_type == e_rr_type::IPIN) { return std::make_pair(0., 0.); } @@ -406,7 +403,7 @@ std::pair ExtendedMapLookahead::run_dijkstra(RRNodeId start_node, } /* if this node is an ipin record its congestion/delay in the routing_cost_map */ - if (rr_graph.node_type(node) == IPIN) { + if (rr_graph.node_type(node) == e_rr_type::IPIN) { // the last cost should be the highest max_cost = current.cost(); @@ -587,15 +584,15 @@ float ExtendedMapLookahead::get_expected_cost( auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type rr_type = rr_graph.node_type(current_node); + e_rr_type rr_type = rr_graph.node_type(current_node); - if (rr_type == CHANX || rr_type == CHANY || rr_type == SOURCE || rr_type == OPIN) { + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY || rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::OPIN) { float delay_cost, cong_cost; // Get the total cost using the combined delay and congestion costs std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); return delay_cost + cong_cost; - } else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (rr_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ // This is to return only the cost between the IPIN and SINK. No need to // query the cost map, as the routing of this connection is almost done. return device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost; diff --git a/vpr/src/route/router_lookahead_extended_map.h b/vpr/src/route/router_lookahead/router_lookahead_extended_map.h similarity index 100% rename from vpr/src/route/router_lookahead_extended_map.h rename to vpr/src/route/router_lookahead/router_lookahead_extended_map.h diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_map.cpp similarity index 96% rename from vpr/src/route/router_lookahead_map.cpp rename to vpr/src/route/router_lookahead/router_lookahead_map.cpp index d11f216c8ee..5d8671aa468 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_map.cpp @@ -89,7 +89,7 @@ static void compute_tiles_lookahead(std::unordered_map cost * @param physical_tile * @param det_routing_arch @@ -167,18 +167,18 @@ float MapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId target_nod auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type from_rr_type = rr_graph.node_type(current_node); + e_rr_type from_rr_type = rr_graph.node_type(current_node); - VTR_ASSERT_SAFE(rr_graph.node_type(target_node) == t_rr_type::SINK); + VTR_ASSERT_SAFE(rr_graph.node_type(target_node) == e_rr_type::SINK); if (is_flat_) { return get_expected_cost_flat_router(current_node, target_node, params, R_upstream); } else { - if (from_rr_type == CHANX || from_rr_type == CHANY || from_rr_type == SOURCE || from_rr_type == OPIN) { + if (from_rr_type == e_rr_type::CHANX || from_rr_type == e_rr_type::CHANY || from_rr_type == e_rr_type::SOURCE || from_rr_type == e_rr_type::OPIN) { // Get the total cost using the combined delay and congestion costs auto [delay_cost, cong_cost] = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); return delay_cost + cong_cost; - } else if (from_rr_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (from_rr_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return (device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ return (0.); @@ -190,9 +190,9 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - t_rr_type from_rr_type = rr_graph.node_type(current_node); + e_rr_type from_rr_type = rr_graph.node_type(current_node); - VTR_ASSERT_SAFE(rr_graph.node_type(target_node) == t_rr_type::SINK); + VTR_ASSERT_SAFE(rr_graph.node_type(target_node) == e_rr_type::SINK); float delay_cost = 0.; float cong_cost = 0.; @@ -200,13 +200,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI t_physical_tile_type_ptr from_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node), rr_graph.node_layer(current_node)}); - const VibInf* vib; - if (!device_ctx.arch->vib_infs.empty()) { - vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(current_node), rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node)); - } else { - vib = nullptr; - } - //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; + int from_node_ptc_num = rr_graph.node_ptc_num(current_node); t_physical_tile_type_ptr to_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(target_node), rr_graph.node_ylow(target_node), @@ -217,7 +211,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI int to_layer_num = rr_graph.node_layer(target_node); // We have not checked the multi-layer FPGA for flat routing VTR_ASSERT(rr_graph.node_layer(current_node) == rr_graph.node_layer(target_node)); - if (from_rr_type == CHANX || from_rr_type == CHANY) { + if (from_rr_type == e_rr_type::CHANX || from_rr_type == e_rr_type::CHANY) { std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); // delay_cost and cong_cost only represent the cost to get to the root-level pins. The below offsets are used to represent the intra-cluster cost @@ -226,13 +220,8 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion; return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; - } else if (from_rr_type == OPIN) { - - if (is_inter_cluster_node(from_physical_type, - vib, - from_rr_type, - from_node_ptc_num)) { - + } else if (from_rr_type == e_rr_type::OPIN) { + if (is_inter_cluster_node(rr_graph, current_node)) { // Similar to CHANX and CHANY std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); @@ -271,7 +260,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI } return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } - } else if (from_rr_type == IPIN) { + } else if (from_rr_type == e_rr_type::IPIN) { // we assume that route-through is not enabled. VTR_ASSERT(node_in_same_physical_tile(current_node, target_node)); const auto& pin_delays = intra_tile_pin_primitive_pin_delay.at(from_physical_type->index)[from_node_ptc_num]; @@ -284,7 +273,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI cong_cost = (1. - params.criticality) * pin_delay_itr->second.congestion; } return delay_cost + cong_cost; - } else if (from_rr_type == SOURCE) { + } else if (from_rr_type == e_rr_type::SOURCE) { if (node_in_same_physical_tile(current_node, target_node)) { delay_cost = 0.; cong_cost = 0.; @@ -302,7 +291,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI } return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } else { - VTR_ASSERT(from_rr_type == SINK); + VTR_ASSERT(from_rr_type == e_rr_type::SINK); return (0.); } } @@ -324,7 +313,7 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ float expected_cong_cost = std::numeric_limits::infinity(); e_rr_type from_type = rr_graph.node_type(from_node); - if (from_type == SOURCE || from_type == OPIN) { + if (from_type == e_rr_type::SOURCE || from_type == e_rr_type::OPIN) { //When estimating costs from a SOURCE/OPIN we look-up to find which wire types (and the //cost to reach them) in src_opin_delays. Once we know what wire types are //reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final @@ -369,7 +358,7 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ .c_str()) .c_str()); - } else if (from_type == CHANX || from_type == CHANY) { + } else if (from_type == e_rr_type::CHANX || from_type == e_rr_type::CHANY) { //When estimating costs from a wire, we directly look-up the result in the wire lookahead (f_wire_cost_map) auto from_cost_index = rr_graph.node_cost_index(from_node); @@ -399,7 +388,7 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ .c_str()); expected_delay_cost = cost_entry.delay * params.criticality; expected_cong_cost = cost_entry.congestion * (1 - params.criticality); - } else if (from_type == IPIN) { /* Change if you're allowing route-throughs */ + } else if (from_type == e_rr_type::IPIN) { /* Change if you're allowing route-throughs */ return std::make_pair(0., device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost); } else { /* Change this if you want to investigate route-throughs */ return std::make_pair(0., 0.); @@ -490,10 +479,10 @@ float MapLookahead::get_opin_distance_min_delay(int physical_tile_idx, int from_ /******** Function Definitions ********/ static util::Cost_Entry get_wire_cost_entry(e_rr_type rr_type, int seg_index, int from_layer_num, int delta_x, int delta_y, int to_layer_num) { - VTR_ASSERT_SAFE(rr_type == CHANX || rr_type == CHANY); + VTR_ASSERT_SAFE(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); int chan_index = 0; - if (rr_type == CHANY) { + if (rr_type == e_rr_type::CHANY) { chan_index = 1; } @@ -531,11 +520,11 @@ static void compute_router_wire_lookahead(const std::vector& segm for (const auto& segment_inf : segment_inf_vec) { std::vector chan_types; if (segment_inf.parallel_axis == X_AXIS) - chan_types.push_back(CHANX); + chan_types.push_back(e_rr_type::CHANX); else if (segment_inf.parallel_axis == Y_AXIS) - chan_types.push_back(CHANY); + chan_types.push_back(e_rr_type::CHANY); else //Both for BOTH_AXIS segments and special segments such as clock_networks we want to search in both directions. - chan_types.insert(chan_types.end(), {CHANX, CHANY}); + chan_types.insert(chan_types.end(), {e_rr_type::CHANX, e_rr_type::CHANY}); for (e_rr_type chan_type : chan_types) { util::t_routing_cost_map routing_cost_map = util::get_routing_cost_map(longest_seg_length, @@ -562,7 +551,7 @@ static void compute_router_wire_lookahead(const std::vector& segm /* sets the lookahead cost map entries based on representative cost entries from routing_cost_map */ static void set_lookahead_map_costs(int from_layer_num, int segment_index, e_rr_type chan_type, util::t_routing_cost_map& routing_cost_map) { - int chan_index = (chan_type == CHANX) ? 0 : 1; + int chan_index = (chan_type == e_rr_type::CHANX) ? 0 : 1; /* set the lookahead cost map entries with a representative cost entry from routing_cost_map */ for (unsigned to_layer = 0; to_layer < routing_cost_map.dim_size(0); to_layer++) { @@ -578,7 +567,7 @@ static void set_lookahead_map_costs(int from_layer_num, int segment_index, e_rr_ /* fills in missing lookahead map entries by copying the cost of the closest valid entry */ static void fill_in_missing_lookahead_entries(int segment_index, e_rr_type chan_type) { - int chan_index = (chan_type == CHANX) ? 0 : 1; + int chan_index = (chan_type == e_rr_type::CHANX) ? 0 : 1; auto& device_ctx = g_vpr_ctx.device(); @@ -855,7 +844,7 @@ static void min_opin_distance_cost_map(const util::t_src_opin_delays& src_opin_d } else { for (const auto& kv : layer_src_opin_delay_map) { const util::t_reachable_wire_inf& reachable_wire_inf = kv.second; - if (reachable_wire_inf.wire_rr_type == SINK) { + if (reachable_wire_inf.wire_rr_type == e_rr_type::SINK) { continue; } util::Cost_Entry wire_cost_entry; diff --git a/vpr/src/route/router_lookahead_map.h b/vpr/src/route/router_lookahead/router_lookahead_map.h similarity index 100% rename from vpr/src/route/router_lookahead_map.h rename to vpr/src/route/router_lookahead/router_lookahead_map.h diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp similarity index 97% rename from vpr/src/route/router_lookahead_map_utils.cpp rename to vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp index c64e97f85c3..b07c48df96f 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp @@ -14,6 +14,7 @@ #include "globals.h" #include "physical_types_util.h" #include "vpr_context.h" +#include "vpr_utils.h" #include "vtr_math.h" #include "vtr_time.h" #include "route_common.h" @@ -395,7 +396,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { if (device_ctx.grid.num_instances(&device_ctx.physical_tile_types[itile], from_layer_num) == 0) { continue; } - for (e_rr_type rr_type : {SOURCE, OPIN}) { + for (e_rr_type rr_type : {e_rr_type::SOURCE, e_rr_type::OPIN}) { t_physical_tile_loc sample_loc(OPEN, OPEN, OPEN); size_t num_sampled_locs = 0; @@ -514,7 +515,7 @@ t_chan_ipins_delays compute_router_chan_ipin_lookahead() { for (int ix = min_x; ix < max_x; ix++) { for (int iy = min_y; iy < max_y; iy++) { - for (auto rr_type : {CHANX, CHANY}) { + for (auto rr_type : {e_rr_type::CHANX, e_rr_type::CHANY}) { for (const RRNodeId& node_id : node_lookup.find_channel_nodes(sample_loc.layer_num, ix, iy, rr_type)) { //Find the IPINs which are reachable from the wires within the bounding box //around the selected tile location @@ -556,20 +557,20 @@ t_ipin_primitive_sink_delays compute_intra_tile_dijkstra(const RRGraphView& rr_g } /* returns index of a node from which to start routing */ -RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset) { +RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int target_y, e_rr_type rr_type, int seg_index, int track_offset) { auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; const auto& node_lookup = rr_graph.node_lookup(); RRNodeId result = RRNodeId::INVALID(); - if (rr_type != CHANX && rr_type != CHANY) { + if (rr_type != e_rr_type::CHANX && rr_type != e_rr_type::CHANY) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Must start lookahead routing from CHANX or CHANY node\n"); } /* determine which direction the wire should go in based on the start & target coordinates */ Direction direction = Direction::INC; - if ((rr_type == CHANX && target_x < start_x) || (rr_type == CHANY && target_y < start_y)) { + if ((rr_type == e_rr_type::CHANX && target_x < start_x) || (rr_type == e_rr_type::CHANY && target_y < start_y)) { direction = Direction::DEC; } @@ -623,7 +624,7 @@ std::pair get_xy_deltas(RRNodeId from_node, RRNodeId to_node) { int from_chan; int to_seg; int to_chan; - if (from_type == CHANY) { + if (from_type == e_rr_type::CHANY) { from_seg_low = rr_graph.node_ylow(from_node); from_seg_high = rr_graph.node_yhigh(from_node); from_chan = rr_graph.node_xlow(from_node); @@ -677,7 +678,7 @@ std::pair get_xy_deltas(RRNodeId from_node, RRNodeId to_node) { // and it is heading towards the outside of the grid, we should // not increment the delta_seg by 1. int max_seg_index = -1; - if (from_type == CHANX) { + if (from_type == e_rr_type::CHANX) { max_seg_index = static_cast(device_ctx.grid.width()) - 1; } else { max_seg_index = static_cast(device_ctx.grid.height()) - 1; @@ -687,7 +688,7 @@ std::pair get_xy_deltas(RRNodeId from_node, RRNodeId to_node) { } } - if (from_type == CHANY) { + if (from_type == e_rr_type::CHANY) { delta_x = delta_chan; delta_y = delta_seg; } else { @@ -744,11 +745,11 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length, std::vector sample_nodes; std::vector chan_types; if (segment_inf.parallel_axis == X_AXIS) - chan_types.push_back(CHANX); + chan_types.push_back(e_rr_type::CHANX); else if (segment_inf.parallel_axis == Y_AXIS) - chan_types.push_back(CHANY); + chan_types.push_back(e_rr_type::CHANY); else //Both for BOTH_AXIS segments and special segments such as clock_networks we want to search in both directions. - chan_types.insert(chan_types.end(), {CHANX, CHANY}); + chan_types.insert(chan_types.end(), {e_rr_type::CHANX, e_rr_type::CHANY}); for (int ref_inc : ref_increments) { int sample_x = ref_x + ref_inc; @@ -873,7 +874,7 @@ std::pair get_cost_from_src_opin(const std::map IPIN) connection. //In the lookahead, we treat such connections as 'special' wire types //with no delay/congestion cost @@ -930,7 +931,7 @@ void dump_readable_router_lookahead_map(const std::string& file_name, const std: for (int from_layer_num = 0; from_layer_num < num_layers; from_layer_num++) { for (int to_layer_num = 0; to_layer_num < num_layers; to_layer_num++) { - for (e_rr_type chan_type : {CHANX, CHANY}) { + for (e_rr_type chan_type : {e_rr_type::CHANX, e_rr_type::CHANY}) { for (int seg_index = 0; seg_index < dim_sizes[3]; seg_index++) { for (int dx = 0; dx < grid_width; dx++) { for (int dy = 0; dy < grid_height; dy++) { @@ -1006,10 +1007,10 @@ static void dijkstra_flood_to_wires(int itile, e_rr_type curr_rr_type = rr_graph.node_type(curr.node); int curr_layer_num = rr_graph.node_layer(curr.node); - if (curr_rr_type == CHANX || curr_rr_type == CHANY || curr_rr_type == SINK) { + if (curr_rr_type == e_rr_type::CHANX || curr_rr_type == e_rr_type::CHANY || curr_rr_type == e_rr_type::SINK) { //We stop expansion at any CHANX/CHANY/SINK int seg_index; - if (curr_rr_type != SINK) { + if (curr_rr_type != e_rr_type::SINK) { //It's a wire, figure out its type auto cost_index = rr_graph.node_cost_index(curr.node); seg_index = device_ctx.rr_indexed_data[cost_index].seg_index; @@ -1034,7 +1035,7 @@ static void dijkstra_flood_to_wires(int itile, src_opin_delays[root_layer_num][itile][ptc][curr_layer_num][seg_index].congestion = curr.congestion; } - } else if (curr_rr_type == SOURCE || curr_rr_type == OPIN || curr_rr_type == IPIN || curr_rr_type == MEDIUM) { + } else if (curr_rr_type == e_rr_type::SOURCE || curr_rr_type == e_rr_type::OPIN || curr_rr_type == e_rr_type::IPIN || curr_rr_type == e_rr_type::MEDIUM) { //We allow expansion through SOURCE/OPIN/IPIN types auto cost_index = rr_graph.node_cost_index(curr.node); float incr_cong = device_ctx.rr_indexed_data[cost_index].base_cost; //Current nodes congestion cost @@ -1128,7 +1129,7 @@ static void dijkstra_flood_to_ipins(RRNodeId node, util::t_chan_ipins_delays& ch pq.pop(); e_rr_type curr_rr_type = rr_graph.node_type(curr.node); - if (curr_rr_type == IPIN) { + if (curr_rr_type == e_rr_type::IPIN) { int node_x = rr_graph.node_xlow(curr.node); int node_y = rr_graph.node_ylow(curr.node); int node_layer = rr_graph.node_layer(curr.node); @@ -1147,7 +1148,7 @@ static void dijkstra_flood_to_ipins(RRNodeId node, util::t_chan_ipins_delays& ch chan_ipins_delays[root_layer][itile][ptc].wire_rr_type = curr_rr_type; chan_ipins_delays[root_layer][itile][ptc].delay = site_pin_delay; chan_ipins_delays[root_layer][itile][ptc].congestion = curr.congestion; - } else if (curr_rr_type == CHANX || curr_rr_type == CHANY) { + } else if (curr_rr_type == e_rr_type::CHANX || curr_rr_type == e_rr_type::CHANY) { if (curr.level >= MAX_EXPANSION_LEVEL) { continue; } @@ -1291,8 +1292,8 @@ static void run_intra_tile_dijkstra(const RRGraphView& rr_graph, node_expanded[curr.node] = true; } auto curr_type = rr_graph.node_type(curr.node); - VTR_ASSERT(curr_type != t_rr_type::CHANX && curr_type != t_rr_type::CHANY); - if (curr_type != SINK) { + VTR_ASSERT(curr_type != e_rr_type::CHANX && curr_type != e_rr_type::CHANY); + if (curr_type != e_rr_type::SINK) { for (RREdgeId edge : rr_graph.edge_range(curr.node)) { RRNodeId next_node = rr_graph.rr_nodes().edge_sink_node(edge); auto cost_index = rr_graph.node_cost_index(next_node); @@ -1366,7 +1367,7 @@ static void run_dijkstra(RRNodeId start_node, //VTR_LOG("Expanding with delay=%10.3g cong=%10.3g (%s)\n", current.delay, current.congestion_upstream, describe_rr_node(rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, curr_node).c_str()); /* if this node is an ipin record its congestion/delay in the routing_cost_map */ - if (rr_graph.node_type(curr_node) == IPIN) { + if (rr_graph.node_type(curr_node) == e_rr_type::IPIN) { VTR_ASSERT_SAFE(rr_graph.node_xlow(curr_node) == rr_graph.node_xhigh(curr_node)); VTR_ASSERT_SAFE(rr_graph.node_ylow(curr_node) == rr_graph.node_yhigh(curr_node)); int ipin_x = rr_graph.node_xlow(curr_node); @@ -1434,7 +1435,7 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, } int switch_ind = size_t(rr_graph.edge_switch(parent, edge)); - if (rr_graph.node_type(child_node) == SINK) return; + if (rr_graph.node_type(child_node) == e_rr_type::SINK) return; /* skip this child if it has already been expanded from */ if (node_expanded[child_node]) { diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead/router_lookahead_map_utils.h similarity index 99% rename from vpr/src/route/router_lookahead_map_utils.h rename to vpr/src/route/router_lookahead/router_lookahead_map_utils.h index 217bd0d2206..6222a71967f 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead/router_lookahead_map_utils.h @@ -325,7 +325,7 @@ t_ipin_primitive_sink_delays compute_intra_tile_dijkstra(const RRGraphView& rr_g int y); /* returns index of a node from which to start routing */ -RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset); +RRNodeId get_start_node(int layer, int start_x, int start_y, int target_x, int target_y, e_rr_type rr_type, int seg_index, int track_offset); /** * @brief Computes the absolute delta_x and delta_y offset diff --git a/vpr/src/route/router_lookahead_sampling.cpp b/vpr/src/route/router_lookahead/router_lookahead_sampling.cpp similarity index 97% rename from vpr/src/route/router_lookahead_sampling.cpp rename to vpr/src/route/router_lookahead/router_lookahead_sampling.cpp index a8ad7dc2f15..c8e71ad6267 100644 --- a/vpr/src/route/router_lookahead_sampling.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_sampling.cpp @@ -130,7 +130,7 @@ static std::tuple get_node_info(const t_rr_node& node, int num_se const auto& rr_graph = device_ctx.rr_graph; RRNodeId rr_node = node.id(); - if (rr_graph.node_type(rr_node) != CHANX && rr_graph.node_type(rr_node) != CHANY) { + if (rr_graph.node_type(rr_node) != e_rr_type::CHANX && rr_graph.node_type(rr_node) != e_rr_type::CHANY) { return std::tuple(OPEN, OPEN, OPEN); } @@ -203,7 +203,7 @@ std::vector find_sample_regions(int num_segments) { // compute bounding boxes for each segment type std::vector> bounding_box_for_segment(num_segments, vtr::Rect()); for (auto& node : rr_graph.rr_nodes()) { - if (rr_graph.node_type(node.id()) != CHANX && rr_graph.node_type(node.id()) != CHANY) continue; + if (rr_graph.node_type(node.id()) != e_rr_type::CHANX && rr_graph.node_type(node.id()) != e_rr_type::CHANY) continue; if (rr_graph.node_capacity(node.id()) == 0 || rr_graph.num_edges(node.id()) == 0) continue; int seg_index = device_ctx.rr_indexed_data[rr_graph.node_cost_index(node.id())].seg_index; diff --git a/vpr/src/route/router_lookahead_sampling.h b/vpr/src/route/router_lookahead/router_lookahead_sampling.h similarity index 100% rename from vpr/src/route/router_lookahead_sampling.h rename to vpr/src/route/router_lookahead/router_lookahead_sampling.h diff --git a/vpr/src/route/router_stats.h b/vpr/src/route/router_stats.h index 4336d419083..32339a98192 100644 --- a/vpr/src/route/router_stats.h +++ b/vpr/src/route/router_stats.h @@ -4,6 +4,7 @@ #include "rr_graph_fwd.h" #include "rr_node_types.h" #include "vtr_assert.h" +#include "vtr_array.h" // This struct instructs the router on how to route the given connection struct ConnectionParameters { @@ -38,13 +39,13 @@ struct RouterStats { size_t inter_cluster_node_pops = 0; size_t intra_cluster_node_pushes = 0; size_t intra_cluster_node_pops = 0; - size_t inter_cluster_node_type_cnt_pushes[t_rr_type::NUM_RR_TYPES] = {0}; - size_t inter_cluster_node_type_cnt_pops[t_rr_type::NUM_RR_TYPES] = {0}; - size_t intra_cluster_node_type_cnt_pushes[t_rr_type::NUM_RR_TYPES] = {0}; - size_t intra_cluster_node_type_cnt_pops[t_rr_type::NUM_RR_TYPES] = {0}; + vtr::array inter_cluster_node_type_cnt_pushes{0}; + vtr::array inter_cluster_node_type_cnt_pops{0}; + vtr::array intra_cluster_node_type_cnt_pushes{0}; + vtr::array intra_cluster_node_type_cnt_pops{0}; // For debugging purposes - size_t rt_node_pushes[t_rr_type::NUM_RR_TYPES] = {0}; + vtr::array rt_node_pushes{0}; /** Add rhs's stats to mine */ void combine(RouterStats& rhs) { @@ -56,12 +57,12 @@ struct RouterStats { heap_pops += rhs.heap_pops; inter_cluster_node_pops += rhs.inter_cluster_node_pops; intra_cluster_node_pops += rhs.intra_cluster_node_pops; - for (int node_type_idx = 0; node_type_idx < t_rr_type::NUM_RR_TYPES; node_type_idx++) { - inter_cluster_node_type_cnt_pushes[node_type_idx] += rhs.inter_cluster_node_type_cnt_pushes[node_type_idx]; - inter_cluster_node_type_cnt_pops[node_type_idx] += rhs.inter_cluster_node_type_cnt_pops[node_type_idx]; - intra_cluster_node_type_cnt_pushes[node_type_idx] += rhs.intra_cluster_node_type_cnt_pushes[node_type_idx]; - intra_cluster_node_type_cnt_pops[node_type_idx] += rhs.intra_cluster_node_type_cnt_pops[node_type_idx]; - rt_node_pushes[node_type_idx] += rhs.rt_node_pushes[node_type_idx]; + for (e_rr_type rr_type : RR_TYPES) { + inter_cluster_node_type_cnt_pushes[rr_type] += rhs.inter_cluster_node_type_cnt_pushes[rr_type]; + inter_cluster_node_type_cnt_pops[rr_type] += rhs.inter_cluster_node_type_cnt_pops[rr_type]; + intra_cluster_node_type_cnt_pushes[rr_type] += rhs.intra_cluster_node_type_cnt_pushes[rr_type]; + intra_cluster_node_type_cnt_pops[rr_type] += rhs.intra_cluster_node_type_cnt_pops[rr_type]; + rt_node_pushes[rr_type] += rhs.rt_node_pushes[rr_type]; } } }; diff --git a/vpr/src/route/build_switchblocks.cpp b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp similarity index 98% rename from vpr/src/route/build_switchblocks.cpp rename to vpr/src/route/rr_graph_generation/build_switchblocks.cpp index a0dbe35bb1c..b9bf8b819cc 100644 --- a/vpr/src/route/build_switchblocks.cpp +++ b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp @@ -229,8 +229,8 @@ static void compute_wireconn_connections( int to_x, int to_y, int to_layer, - t_rr_type from_chan_type, - t_rr_type to_chan_type, + e_rr_type from_chan_type, + e_rr_type to_chan_type, const t_wire_type_sizes* wire_type_sizes_x, const t_wire_type_sizes* wire_type_sizes_y, const t_switchblock_inf* sb, @@ -262,7 +262,7 @@ static int evaluate_num_conns_formula(t_wireconn_scratchpad* scratchpad, std::st static void get_switchpoint_wires( const DeviceGrid& grid, const t_chan_seg_details* chan_details, - t_rr_type chan_type, + e_rr_type chan_type, int x, int y, e_side side, @@ -292,7 +292,7 @@ static void get_switchpoint_wires( * * @return returns the type of channel that we are indexing into (ie, CHANX or CHANY) and channel coordinates and type */ -static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, t_rr_type& chan_type); +static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, e_rr_type& chan_type); /** * @brief check whether a specific track location is valid within the device grid @@ -663,7 +663,7 @@ static void count_wire_type_sizes(const t_chan_seg_details* channel, int nodes_p static void get_switchpoint_wires( const DeviceGrid& grid, const t_chan_seg_details* chan_details, - t_rr_type chan_type, + e_rr_type chan_type, int x, int y, e_side side, @@ -680,7 +680,7 @@ static void get_switchpoint_wires( std::vector& collected_wire_switchpoints = *scratch_wires; int seg_coord = x; - if (chan_type == CHANY) { + if (chan_type == e_rr_type::CHANY) { seg_coord = y; } @@ -773,7 +773,7 @@ static void compute_wire_connections(int x_coord, t_wireconn_scratchpad* scratchpad) { int from_x, from_y, from_layer; /* index into source channel */ int to_x, to_y, to_layer; /* index into destination channel */ - t_rr_type from_chan_type, to_chan_type; /* the type of channel - i.e. CHANX or CHANY */ + e_rr_type from_chan_type, to_chan_type; /* the type of channel - i.e. CHANX or CHANY */ from_x = from_y = to_x = to_y = from_layer = to_layer = UNDEFINED; SB_Side_Connection side_conn(from_side, to_side); /* for indexing into this switchblock's permutation funcs */ @@ -807,10 +807,10 @@ static void compute_wire_connections(int x_coord, const t_wire_type_sizes* wire_type_sizes_from = wire_type_sizes_x; const t_wire_type_sizes* wire_type_sizes_to = wire_type_sizes_x; - if (from_chan_type == CHANY) { + if (from_chan_type == e_rr_type::CHANY) { wire_type_sizes_from = wire_type_sizes_y; } - if (to_chan_type == CHANY) { + if (to_chan_type == e_rr_type::CHANY) { wire_type_sizes_to = wire_type_sizes_y; } @@ -843,8 +843,8 @@ static void compute_wireconn_connections( int to_x, int to_y, int to_layer, - t_rr_type from_chan_type, - t_rr_type to_chan_type, + e_rr_type from_chan_type, + e_rr_type to_chan_type, const t_wire_type_sizes* wire_type_sizes_from, const t_wire_type_sizes* wire_type_sizes_to, const t_switchblock_inf* sb, @@ -1024,8 +1024,8 @@ static int evaluate_num_conns_formula(t_wireconn_scratchpad* scratchpad, std::st return scratchpad->formula_parser.parse_formula(num_conns_formula, vars); } -static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, t_rr_type& chan_type) { - chan_type = CHANX; +static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int tile_layer, enum e_side src_side, enum e_side dest_side, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, int& chan_x, int& chan_y, int& chan_layer, e_rr_type& chan_type) { + chan_type = e_rr_type::CHANX; /* here we use the VPR convention that a tile 'owns' the channels directly to the right * and above it */ switch (src_side) { @@ -1034,7 +1034,7 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int chan_x = tile_x; chan_y = tile_y + 1; chan_layer = tile_layer; - chan_type = CHANY; + chan_type = e_rr_type::CHANY; return chan_details_y; break; case RIGHT: @@ -1042,14 +1042,14 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int chan_x = tile_x + 1; chan_y = tile_y; chan_layer = tile_layer; - chan_type = CHANX; + chan_type = e_rr_type::CHANX; return chan_details_x; break; case BOTTOM: /* this is y-channel on the right of the tile in the same layer */ chan_x = tile_x; chan_y = tile_y; - chan_type = CHANY; + chan_type = e_rr_type::CHANY; chan_layer = tile_layer; return chan_details_y; break; @@ -1057,7 +1057,7 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int /* this is x-channel on top of the tile in the same layer*/ chan_x = tile_x; chan_y = tile_y; - chan_type = CHANX; + chan_type = e_rr_type::CHANX; chan_layer = tile_layer; return chan_details_x; break; @@ -1066,7 +1066,7 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int chan_x = tile_x; chan_y = tile_y; chan_layer = tile_layer + 1; - chan_type = (dest_side == RIGHT || dest_side == LEFT) ? CHANX : CHANY; + chan_type = (dest_side == RIGHT || dest_side == LEFT) ? e_rr_type::CHANX : e_rr_type::CHANY; return (dest_side == RIGHT || dest_side == LEFT) ? chan_details_x : chan_details_y; break; case UNDER: @@ -1074,7 +1074,7 @@ static const t_chan_details& index_into_correct_chan(int tile_x, int tile_y, int chan_x = tile_x; chan_y = tile_y; chan_layer = tile_layer - 1; - chan_type = (dest_side == RIGHT || dest_side == LEFT) ? CHANX : CHANY; + chan_type = (dest_side == RIGHT || dest_side == LEFT) ? e_rr_type::CHANX : e_rr_type::CHANY; return (dest_side == RIGHT || dest_side == LEFT) ? chan_details_x : chan_details_y; break; default: @@ -1093,14 +1093,14 @@ static bool coords_out_of_bounds(const DeviceGrid& grid, int x_coord, int y_coor return result; } - if (CHANX == chan_type) { + if (e_rr_type::CHANX == chan_type) { /* there is no x-channel at x=0 */ if (x_coord <= 0 || x_coord >= int(grid.width()) - 1 || y_coord < 0 || y_coord >= int(grid.height()) - 1) { result = true; } else { result = false; } - } else if (CHANY == chan_type) { + } else if (e_rr_type::CHANY == chan_type) { /* there is no y-channel at y=0 */ if (x_coord < 0 || x_coord >= int(grid.width()) - 1 || y_coord <= 0 || y_coord >= int(grid.height()) - 1) { result = true; @@ -1161,7 +1161,7 @@ int get_wire_segment_length(const DeviceGrid& grid, e_rr_type chan_type, const t int min_seg = 1; int max_seg = grid.width() - 2; //-2 for no perim channels - if (chan_type == CHANY) { + if (chan_type == e_rr_type::CHANY) { max_seg = grid.height() - 2; //-2 for no perim channels } @@ -1194,7 +1194,7 @@ static int get_switchpoint_of_wire(const DeviceGrid& grid, e_rr_type chan_type, /* get the minimum and maximum segment coordinate which a wire in this channel type can take */ int min_seg = 1; int max_seg = grid.width() - 2; //-2 for no perim channels - if (chan_type == CHANY) { + if (chan_type == e_rr_type::CHANY) { max_seg = grid.height() - 2; //-2 for no perim channels } diff --git a/vpr/src/route/build_switchblocks.h b/vpr/src/route/rr_graph_generation/build_switchblocks.h similarity index 100% rename from vpr/src/route/build_switchblocks.h rename to vpr/src/route/rr_graph_generation/build_switchblocks.h diff --git a/vpr/src/route/cb_metrics.cpp b/vpr/src/route/rr_graph_generation/cb_metrics.cpp similarity index 100% rename from vpr/src/route/cb_metrics.cpp rename to vpr/src/route/rr_graph_generation/cb_metrics.cpp diff --git a/vpr/src/route/cb_metrics.h b/vpr/src/route/rr_graph_generation/cb_metrics.h similarity index 100% rename from vpr/src/route/cb_metrics.h rename to vpr/src/route/rr_graph_generation/cb_metrics.h diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp similarity index 96% rename from vpr/src/route/clock_connection_builders.cpp rename to vpr/src/route/rr_graph_generation/clock_connection_builders.cpp index 5a193a159ad..074e3b7565c 100644 --- a/vpr/src/route/clock_connection_builders.cpp +++ b/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp @@ -3,20 +3,22 @@ #include "globals.h" #include "arch_util.h" #include "rr_rc_data.h" +#include "vpr_utils.h" #include -#include +#include +#include /* * RoutingToClockConnection (setters) */ void RoutingToClockConnection::set_clock_name_to_connect_to(std::string clock_name) { - clock_to_connect_to = clock_name; + clock_to_connect_to = std::move(clock_name); } void RoutingToClockConnection::set_clock_switch_point_name(std::string clock_switch_point_name) { - switch_point_name = clock_switch_point_name; + switch_point_name = std::move(clock_switch_point_name); } void RoutingToClockConnection::set_switch_location(int x, int y, int layer /* =0 */) { @@ -57,8 +59,8 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_ rr_graph_builder.set_virtual_clock_network_root_idx(virtual_clock_network_root_idx); // rr_node indices for x and y channel routing wires and clock wires to connect to - auto x_wire_indices = node_lookup.find_channel_nodes(switch_location.layer, switch_location.x, switch_location.y, CHANX); - auto y_wire_indices = node_lookup.find_channel_nodes(switch_location.layer, switch_location.x, switch_location.y, CHANY); + auto x_wire_indices = node_lookup.find_channel_nodes(switch_location.layer, switch_location.x, switch_location.y, e_rr_type::CHANX); + auto y_wire_indices = node_lookup.find_channel_nodes(switch_location.layer, switch_location.x, switch_location.y, e_rr_type::CHANY); auto clock_indices = clock_graph.get_rr_node_indices_at_switch_location( clock_to_connect_to, switch_point_name, switch_location.x, switch_location.y); @@ -96,7 +98,7 @@ RRNodeId RoutingToClockConnection::create_virtual_clock_network_sink_node(int la RRNodeId node_index = RRNodeId(rr_graph.num_nodes() - 1); //Determine a valid PTC - std::vector nodes_at_loc = node_lookup.find_grid_nodes_at_all_sides(layer, x, y, SINK); + std::vector nodes_at_loc = node_lookup.find_grid_nodes_at_all_sides(layer, x, y, e_rr_type::SINK); int max_ptc = 0; for (RRNodeId inode : nodes_at_loc) { @@ -104,7 +106,7 @@ RRNodeId RoutingToClockConnection::create_virtual_clock_network_sink_node(int la } int ptc = max_ptc + 1; - rr_graph_builder.set_node_type(node_index, SINK); + rr_graph_builder.set_node_type(node_index, e_rr_type::SINK); rr_graph_builder.set_node_name(node_index, arch->default_clock_network_name); rr_graph_builder.set_node_class_num(node_index, ptc); rr_graph_builder.set_node_coordinates(node_index, x, y, x, y); @@ -309,7 +311,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra auto clock_pin_node_idx = node_lookup.find_node(layer_num, x, y, - IPIN, + e_rr_type::IPIN, clock_pin_idx, side); diff --git a/vpr/src/route/clock_connection_builders.h b/vpr/src/route/rr_graph_generation/clock_connection_builders.h similarity index 100% rename from vpr/src/route/clock_connection_builders.h rename to vpr/src/route/rr_graph_generation/clock_connection_builders.h diff --git a/vpr/src/route/clock_fwd.h b/vpr/src/route/rr_graph_generation/clock_fwd.h similarity index 100% rename from vpr/src/route/clock_fwd.h rename to vpr/src/route/rr_graph_generation/clock_fwd.h diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/rr_graph_generation/clock_network_builders.cpp similarity index 99% rename from vpr/src/route/clock_network_builders.cpp rename to vpr/src/route/rr_graph_generation/clock_network_builders.cpp index 34dccc4ff29..73932d99f3a 100644 --- a/vpr/src/route/clock_network_builders.cpp +++ b/vpr/src/route/rr_graph_generation/clock_network_builders.cpp @@ -340,7 +340,7 @@ int ClockRib::create_chanx_wire(int layer, auto node_index = rr_nodes->size() - 1; RRNodeId chanx_node = RRNodeId(node_index); - rr_graph_builder.set_node_type(chanx_node, CHANX); + rr_graph_builder.set_node_type(chanx_node, e_rr_type::CHANX); rr_graph_builder.set_node_coordinates(chanx_node, x_start, y, x_end, y); rr_graph_builder.set_node_layer(chanx_node, layer); rr_graph_builder.set_node_capacity(chanx_node, 1); @@ -372,8 +372,7 @@ int ClockRib::create_chanx_wire(int layer, /* TODO: Will replace these codes with an API add_node_to_all_locs() of RRGraphBuilder */ for (int ix = rr_graph.node_xlow(chanx_node); ix <= rr_graph.node_xhigh(chanx_node); ++ix) { for (int iy = rr_graph.node_ylow(chanx_node); iy <= rr_graph.node_yhigh(chanx_node); ++iy) { - //TODO: CHANX uses odd swapped x/y indices here. Will rework once rr_node_indices is shadowed - rr_graph_builder.node_lookup().add_node(chanx_node, layer, iy, ix, rr_graph.node_type(chanx_node), rr_graph.node_track_num(chanx_node)); + rr_graph_builder.node_lookup().add_node(chanx_node, layer, ix, iy, rr_graph.node_type(chanx_node), rr_graph.node_track_num(chanx_node)); } } @@ -682,7 +681,7 @@ int ClockSpine::create_chany_wire(int layer, auto node_index = rr_nodes->size() - 1; RRNodeId chany_node = RRNodeId(node_index); - rr_graph_builder.set_node_type(chany_node, CHANY); + rr_graph_builder.set_node_type(chany_node, e_rr_type::CHANY); rr_graph_builder.set_node_coordinates(chany_node, x, y_start, x, y_end); rr_graph_builder.set_node_layer(chany_node, layer); rr_graph_builder.set_node_capacity(chany_node, 1); diff --git a/vpr/src/route/clock_network_builders.h b/vpr/src/route/rr_graph_generation/clock_network_builders.h similarity index 100% rename from vpr/src/route/clock_network_builders.h rename to vpr/src/route/rr_graph_generation/clock_network_builders.h diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph_generation/rr_graph.cpp similarity index 97% rename from vpr/src/route/rr_graph.cpp rename to vpr/src/route/rr_graph_generation/rr_graph.cpp index baa2ed82021..221183161f3 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph.cpp @@ -35,6 +35,7 @@ #include "tileable_rr_graph_builder.h" #include "rr_types.h" +#include "rr_node_indices.h" //#define VERBOSE //used for getting the exact count of each edge type and printing it to std out. @@ -510,7 +511,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, const int layer, const int x_coord, const int y_coord, - const t_rr_type chan_type, + const e_rr_type chan_type, const t_track_to_pin_lookup& track_to_pin_lookup, t_sb_connection_map* sb_conn_map, const vtr::NdMatrix, 3>& switch_block_conn, @@ -702,7 +703,7 @@ static void build_intra_cluster_rr_graph(e_graph_type graph_type, * @param det_routing_arch Contain the information from architecture file * @param load_rr_graph Indicate whether the RR graph is loaded from a file */ -static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, +static int get_delayless_switch_id(const t_det_routing_arch& det_routing_arch, bool load_rr_graph); /******************* Subroutine definitions *******************************/ @@ -711,7 +712,7 @@ void create_rr_graph(e_graph_type graph_type, const std::vector& block_types, const DeviceGrid& grid, const t_chan_width& nodes_per_chan, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, const std::vector& segment_inf, const t_router_opts& router_opts, const std::vector& directs, @@ -721,7 +722,7 @@ void create_rr_graph(e_graph_type graph_type, auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); bool echo_enabled = getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH_INDEXED_DATA); const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); - bool load_rr_graph = !det_routing_arch->read_rr_graph_filename.empty(); + bool load_rr_graph = !det_routing_arch.read_rr_graph_filename.empty(); if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_graph.empty()) { //No change in channel width, so skip re-building RR graph @@ -733,7 +734,7 @@ void create_rr_graph(e_graph_type graph_type, } } else { if (load_rr_graph) { - if (device_ctx.loaded_rr_graph_filename != det_routing_arch->read_rr_graph_filename) { + if (device_ctx.loaded_rr_graph_filename != det_routing_arch.read_rr_graph_filename) { free_rr_graph(); load_rr_file(&mutable_device_ctx.rr_graph_builder, @@ -748,9 +749,9 @@ void create_rr_graph(e_graph_type graph_type, device_ctx.arch, &mutable_device_ctx.chan_width, router_opts.base_cost_type, - &det_routing_arch->wire_to_rr_ipin_switch, - &det_routing_arch->wire_to_arch_ipin_switch_between_dice, - det_routing_arch->read_rr_graph_filename.c_str(), + &det_routing_arch.wire_to_rr_ipin_switch, + &det_routing_arch.wire_to_arch_ipin_switch_between_dice, + det_routing_arch.read_rr_graph_filename.c_str(), &mutable_device_ctx.loaded_rr_graph_filename, router_opts.read_rr_edge_metadata, router_opts.do_check_rr_graph, @@ -770,21 +771,21 @@ void create_rr_graph(e_graph_type graph_type, block_types, grid, nodes_per_chan, - det_routing_arch->switch_block_type, - det_routing_arch->Fs, - det_routing_arch->switchblocks, + det_routing_arch.switch_block_type, + det_routing_arch.Fs, + det_routing_arch.switchblocks, segment_inf, - det_routing_arch->global_route_switch, - det_routing_arch->wire_to_arch_ipin_switch, - det_routing_arch->wire_to_arch_ipin_switch_between_dice, + det_routing_arch.global_route_switch, + det_routing_arch.wire_to_arch_ipin_switch, + det_routing_arch.wire_to_arch_ipin_switch_between_dice, router_opts.custom_3d_sb_fanin_fanout, - det_routing_arch->delayless_switch, - det_routing_arch->R_minW_nmos, - det_routing_arch->R_minW_pmos, + det_routing_arch.delayless_switch, + det_routing_arch.R_minW_nmos, + det_routing_arch.R_minW_pmos, router_opts.base_cost_type, router_opts.clock_modeling, directs, - &det_routing_arch->wire_to_rr_ipin_switch, + &det_routing_arch.wire_to_rr_ipin_switch, is_flat, Warnings, router_opts.route_verbosity); @@ -794,50 +795,38 @@ void create_rr_graph(e_graph_type graph_type, build_tileable_unidir_rr_graph(block_types, grid, nodes_per_chan, - det_routing_arch->switch_block_type, - det_routing_arch->Fs, - det_routing_arch->switch_block_subtype, - det_routing_arch->subFs, + det_routing_arch.switch_block_type, + det_routing_arch.Fs, + det_routing_arch.switch_block_subtype, + det_routing_arch.subFs, segment_inf, - det_routing_arch->delayless_switch, - det_routing_arch->wire_to_arch_ipin_switch, - det_routing_arch->R_minW_nmos, - det_routing_arch->R_minW_pmos, + det_routing_arch.delayless_switch, + det_routing_arch.wire_to_arch_ipin_switch, + det_routing_arch.R_minW_nmos, + det_routing_arch.R_minW_pmos, router_opts.base_cost_type, directs, - &det_routing_arch->wire_to_rr_ipin_switch, - det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ - det_routing_arch->perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ - router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ - det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ - det_routing_arch->concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ - det_routing_arch->concat_pass_wire, /* Allow passing tracks to be wired to the routing tracks in the same direction in a switch block. It means that a pass wire can jump in the same direction to another */ + &det_routing_arch.wire_to_rr_ipin_switch, + det_routing_arch.shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ + det_routing_arch.perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ + router_opts.trim_obs_channels || det_routing_arch.through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ + det_routing_arch.opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ + det_routing_arch.concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ + det_routing_arch.concat_pass_wire, /* Allow passing tracks to be wired to the routing tracks in the same direction in a switch block. It means that a pass wire can jump in the same direction to another */ Warnings); } } // Check if there is an edge override file to read and that it is not already loaded. - if (!det_routing_arch->read_rr_edge_override_filename.empty() - && det_routing_arch->read_rr_edge_override_filename != device_ctx.loaded_rr_edge_override_filename) { + if (!det_routing_arch.read_rr_edge_override_filename.empty() + && det_routing_arch.read_rr_edge_override_filename != device_ctx.loaded_rr_edge_override_filename) { - load_rr_edge_delay_overrides(det_routing_arch->read_rr_edge_override_filename, + load_rr_edge_delay_overrides(det_routing_arch.read_rr_edge_override_filename, mutable_device_ctx.rr_graph_builder, device_ctx.rr_graph); // Remember the loaded filename to avoid reloading it before the RR graph is cleared. - mutable_device_ctx.loaded_rr_edge_override_filename = det_routing_arch->read_rr_edge_override_filename; - } - - // Check if there is an edge override file to read and that it is not already loaded. - if (!det_routing_arch->read_rr_edge_override_filename.empty() - && det_routing_arch->read_rr_edge_override_filename != device_ctx.loaded_rr_edge_override_filename) { - - load_rr_edge_delay_overrides(det_routing_arch->read_rr_edge_override_filename, - mutable_device_ctx.rr_graph_builder, - device_ctx.rr_graph); - - // Remember the loaded filename to avoid reloading it before the RR graph is cleared. - mutable_device_ctx.loaded_rr_edge_override_filename = det_routing_arch->read_rr_edge_override_filename; + mutable_device_ctx.loaded_rr_edge_override_filename = det_routing_arch.read_rr_edge_override_filename; } } @@ -849,8 +838,8 @@ void create_rr_graph(e_graph_type graph_type, block_types, device_ctx.rr_graph, delayless_switch, - det_routing_arch->R_minW_nmos, - det_routing_arch->R_minW_pmos, + det_routing_arch.R_minW_nmos, + det_routing_arch.R_minW_pmos, mutable_device_ctx.rr_graph_builder, is_flat, load_rr_graph); @@ -881,7 +870,7 @@ void create_rr_graph(e_graph_type graph_type, // When this function is called in any stage other than routing, the is_flat flag passed to this function is false, regardless of the flag passed // through command line. So, the graph corresponding to global resources will be created and written down to file if needed. During routing, if flat-routing // is enabled, intra-cluster resources will be added to the graph, but this new bigger graph will not be written down. - if (!det_routing_arch->write_rr_graph_filename.empty() && !is_flat) { + if (!det_routing_arch.write_rr_graph_filename.empty() && !is_flat) { write_rr_graph(&mutable_device_ctx.rr_graph_builder, &mutable_device_ctx.rr_graph, device_ctx.physical_tile_types, @@ -891,7 +880,7 @@ void create_rr_graph(e_graph_type graph_type, device_ctx.arch_switch_inf, device_ctx.arch, &mutable_device_ctx.chan_width, - det_routing_arch->write_rr_graph_filename.c_str(), + det_routing_arch.write_rr_graph_filename.c_str(), echo_enabled, echo_file_name, is_flat); @@ -1255,12 +1244,11 @@ static void build_rr_graph(e_graph_type graph_type, // Add routing resources to rr_graph lookup table alloc_and_load_rr_node_indices(device_ctx.rr_graph_builder, - &nodes_per_chan, + nodes_per_chan, grid, &num_rr_nodes, chan_details_x, - chan_details_y, - is_flat); + chan_details_y); size_t expected_node_count = num_rr_nodes; if (clock_modeling == DEDICATED_NETWORK) { @@ -1342,11 +1330,10 @@ static void build_rr_graph(e_graph_type graph_type, */ if (grid.get_num_layers() > 1 && sb_type == CUSTOM) { //keep how many nodes each switchblock requires for each x,y location - auto extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map, custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder); + vtr::NdMatrix extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map, custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder); //allocate new nodes in each switchblocks - alloc_and_load_inter_die_rr_node_indices(device_ctx.rr_graph_builder, &nodes_per_chan, grid, extra_nodes_per_switchblock, &num_rr_nodes); + alloc_and_load_inter_die_rr_node_indices(device_ctx.rr_graph_builder, nodes_per_chan, grid, extra_nodes_per_switchblock, &num_rr_nodes); device_ctx.rr_graph_builder.resize_nodes(num_rr_nodes); - extra_nodes_per_switchblock.clear(); } /* START IPIN MAP */ @@ -1467,11 +1454,11 @@ static void build_rr_graph(e_graph_type graph_type, // clock_modeling::DEDICATED_NETWORK will append some rr nodes after // the regular graph. for (int i = 0; i < num_rr_nodes; i++) { - if (rr_graph.node_type(RRNodeId(i)) == CHANX) { + if (rr_graph.node_type(RRNodeId(i)) == e_rr_type::CHANX) { int ylow = rr_graph.node_ylow(RRNodeId(i)); device_ctx.rr_graph_builder.set_node_capacity(RRNodeId(i), nodes_per_chan.x_list[ylow]); } - if (rr_graph.node_type(RRNodeId(i)) == CHANY) { + if (rr_graph.node_type(RRNodeId(i)) == e_rr_type::CHANY) { int xlow = rr_graph.node_xlow(RRNodeId(i)); device_ctx.rr_graph_builder.set_node_capacity(RRNodeId(i), nodes_per_chan.y_list[xlow]); } @@ -1484,7 +1471,7 @@ static void build_rr_graph(e_graph_type graph_type, for (int rr_node_id = 0; rr_node_id < num_rr_nodes; rr_node_id++) { auto node_type = rr_graph.node_type(RRNodeId(rr_node_id)); auto node_dir = rr_graph.node_direction(RRNodeId(rr_node_id)); - if (node_type != CHANX && node_type != CHANY) { //SRC/SINK/IPIN/OPIN + if (node_type != e_rr_type::CHANX && node_type != e_rr_type::CHANY) { //SRC/SINK/IPIN/OPIN device_ctx.rr_graph_builder.set_node_ptc_twist_incr(RRNodeId(rr_node_id), 0); } else { //The current ptc twist increment number in UNDIR TILEABLE RRGraph is 2 and -2 @@ -1609,7 +1596,7 @@ static void build_intra_cluster_rr_graph(e_graph_type graph_type, is_flat); } -static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, +static int get_delayless_switch_id(const t_det_routing_arch& det_routing_arch, bool load_rr_graph) { const auto& device_ctx = g_vpr_ctx.device(); int delayless_switch = OPEN; @@ -1623,7 +1610,7 @@ static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, } } } else { - delayless_switch = static_cast(det_routing_arch->delayless_switch); + delayless_switch = static_cast(det_routing_arch.delayless_switch); } return delayless_switch; @@ -2255,7 +2242,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder if (i > 0) { int tracks_per_chan = ((is_global_graph) ? 1 : chan_width.x_list[j]); - build_rr_chan(rr_graph_builder, layer, i, j, CHANX, track_to_pin_lookup_x, sb_conn_map, + build_rr_chan(rr_graph_builder, layer, i, j, e_rr_type::CHANX, track_to_pin_lookup_x, sb_conn_map, switch_block_conn, num_of_3d_conns_custom_SB, CHANX_COST_INDEX_START, chan_width, grid, tracks_per_chan, @@ -2276,7 +2263,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } if (j > 0) { int tracks_per_chan = ((is_global_graph) ? 1 : chan_width.y_list[i]); - build_rr_chan(rr_graph_builder, layer, i, j, CHANY, track_to_pin_lookup_y, sb_conn_map, + build_rr_chan(rr_graph_builder, layer, i, j, e_rr_type::CHANY, track_to_pin_lookup_y, sb_conn_map, switch_block_conn, num_of_3d_conns_custom_SB, CHANX_COST_INDEX_START + num_seg_types_x, chan_width, grid, tracks_per_chan, @@ -2465,12 +2452,12 @@ static void add_classes_rr_graph(RRGraphBuilder& rr_graph_builder, int class_num_pins = get_class_num_pins_from_class_physical_num(physical_type, class_num); if (class_type == DRIVER) { rr_graph_builder.set_node_cost_index(class_inode, RRIndexedDataId(SOURCE_COST_INDEX)); - rr_graph_builder.set_node_type(class_inode, SOURCE); + rr_graph_builder.set_node_type(class_inode, e_rr_type::SOURCE); } else { VTR_ASSERT(class_type == RECEIVER); rr_graph_builder.set_node_cost_index(class_inode, RRIndexedDataId(SINK_COST_INDEX)); - rr_graph_builder.set_node_type(class_inode, SINK); + rr_graph_builder.set_node_type(class_inode, e_rr_type::SINK); } VTR_ASSERT(class_num_pins <= std::numeric_limits::max()); rr_graph_builder.set_node_capacity(class_inode, (short)class_num_pins); @@ -2505,7 +2492,7 @@ static void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder, int x_offset = x_offset_vec[pin_coord]; int y_offset = y_offset_vec[pin_coord]; e_side pin_side = pin_sides_vec[pin_coord]; - auto node_type = (pin_type == DRIVER) ? OPIN : IPIN; + auto node_type = (pin_type == DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; RRNodeId node_id = node_lookup.find_node(layer, i + x_offset, j + y_offset, @@ -2726,7 +2713,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, total_pin_Fc += Fc[pin_index][iseg]; } - RRNodeId node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, OPIN, pin_index, side); + RRNodeId node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, e_rr_type::OPIN, pin_index, side); VTR_ASSERT(node_index); for (auto connected_layer : get_layers_pin_is_connected_to(type, layer, pin_index)) { @@ -3145,7 +3132,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, const int layer, const int x_coord, const int y_coord, - const t_rr_type chan_type, + const e_rr_type chan_type, const t_track_to_pin_lookup& track_to_pin_lookup, t_sb_connection_map* sb_conn_map, const vtr::NdMatrix, 3>& switch_block_conn, @@ -3176,14 +3163,14 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, int chan_coord = y_coord; //The absolute coordinate of this channel within the device int seg_dimension = device_ctx.grid.width() - 2; //-2 for no perim channels int chan_dimension = device_ctx.grid.height() - 2; //-2 for no perim channels - const t_chan_details& from_chan_details = (chan_type == CHANX) ? chan_details_x : chan_details_y; - const t_chan_details& opposite_chan_details = (chan_type == CHANX) ? chan_details_y : chan_details_x; - t_rr_type opposite_chan_type = CHANY; - if (chan_type == CHANY) { + const t_chan_details& from_chan_details = (chan_type == e_rr_type::CHANX) ? chan_details_x : chan_details_y; + const t_chan_details& opposite_chan_details = (chan_type == e_rr_type::CHANX) ? chan_details_y : chan_details_x; + e_rr_type opposite_chan_type = e_rr_type::CHANY; + if (chan_type == e_rr_type::CHANY) { //Swap values since CHANX was assumed above std::swap(seg_coord, chan_coord); std::swap(seg_dimension, chan_dimension); - opposite_chan_type = CHANX; + opposite_chan_type = e_rr_type::CHANX; } const t_chan_seg_details* seg_details = from_chan_details[x_coord][y_coord].data(); @@ -3212,7 +3199,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(seg_coord == start); const t_chan_seg_details* from_seg_details = nullptr; - if (chan_type == CHANY) { + if (chan_type == e_rr_type::CHANY) { from_seg_details = chan_details_y[x_coord][start].data(); } else { from_seg_details = chan_details_x[start][y_coord].data(); @@ -3233,11 +3220,11 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, if (chan_coord > 0) { const t_chan_seg_details* to_seg_details; int max_opposite_chan_width; - if (chan_type == CHANX) { + if (chan_type == e_rr_type::CHANX) { to_seg_details = chan_details_y[start][y_coord].data(); max_opposite_chan_width = nodes_per_chan.y_max; } else { - VTR_ASSERT(chan_type == CHANY); + VTR_ASSERT(chan_type == e_rr_type::CHANY); to_seg_details = chan_details_x[x_coord][start].data(); max_opposite_chan_width = nodes_per_chan.x_max; } @@ -3253,11 +3240,11 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, if (chan_coord < chan_dimension) { const t_chan_seg_details* to_seg_details; int max_opposite_chan_width = 0; - if (chan_type == CHANX) { + if (chan_type == e_rr_type::CHANX) { to_seg_details = chan_details_y[start][y_coord + 1].data(); max_opposite_chan_width = nodes_per_chan.y_max; } else { - VTR_ASSERT(chan_type == CHANY); + VTR_ASSERT(chan_type == e_rr_type::CHANY); to_seg_details = chan_details_x[x_coord + 1][start].data(); max_opposite_chan_width = nodes_per_chan.x_max; } @@ -3285,11 +3272,11 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, const t_chan_seg_details* to_seg_details; /* AA: Same channel width for straight through connections assuming uniform width distributions along the axis*/ int max_chan_width = 0; - if (chan_type == CHANX) { + if (chan_type == e_rr_type::CHANX) { to_seg_details = chan_details_x[target_seg][y_coord].data(); max_chan_width = nodes_per_chan.x_max; } else { - VTR_ASSERT(chan_type == CHANY); + VTR_ASSERT(chan_type == e_rr_type::CHANY); to_seg_details = chan_details_y[x_coord][target_seg].data(); max_chan_width = nodes_per_chan.y_max; } @@ -3313,10 +3300,10 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + seg_details[track].index())); rr_graph_builder.set_node_capacity(node, 1); /* GLOBAL routing handled elsewhere */ - if (chan_type == CHANX) { + if (chan_type == e_rr_type::CHANX) { rr_graph_builder.set_node_coordinates(node, start, y_coord, end, y_coord); } else { - VTR_ASSERT(chan_type == CHANY); + VTR_ASSERT(chan_type == e_rr_type::CHANY); rr_graph_builder.set_node_coordinates(node, x_coord, start, x_coord, end); } @@ -3359,7 +3346,7 @@ static void build_inter_die_custom_sb_rr_chan(RRGraphBuilder& rr_graph_builder, int offset = 0; while (true) { //going through allocated nodes until no nodes are found within the RRGraph builder - RRNodeId node = rr_graph_builder.node_lookup().find_node(layer, x_coord, y_coord, CHANX, start_track + offset); + RRNodeId node = rr_graph_builder.node_lookup().find_node(layer, x_coord, y_coord, e_rr_type::CHANX, start_track + offset); if (node) { rr_graph_builder.set_node_layer(node, layer); rr_graph_builder.set_node_coordinates(node, x_coord, y_coord, x_coord, y_coord); @@ -3371,7 +3358,7 @@ static void build_inter_die_custom_sb_rr_chan(RRGraphBuilder& rr_graph_builder, rr_graph_builder.set_node_rc_index(node, NodeRCIndex( find_create_rr_rc_data(R, C, mutable_device_ctx.rr_rc_data))); - rr_graph_builder.set_node_type(node, CHANX); + rr_graph_builder.set_node_type(node, e_rr_type::CHANX); rr_graph_builder.set_node_track_num(node, start_track + offset); rr_graph_builder.set_node_direction(node, Direction::NONE); @@ -4221,7 +4208,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, continue; } - RRNodeId opin_node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, OPIN, pin_index, side); + RRNodeId opin_node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, e_rr_type::OPIN, pin_index, side); if (!opin_node_index) continue; //No valid from node for (int iseg = 0; iseg < num_seg_types; iseg++) { @@ -4241,11 +4228,11 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * side is the side of the logic or io block. */ bool vert = ((side == TOP) || (side == BOTTOM)); bool pos_dir = ((side == TOP) || (side == RIGHT)); - t_rr_type chan_type = (vert ? CHANX : CHANY); + e_rr_type chan_type = (vert ? e_rr_type::CHANX : e_rr_type::CHANY); int chan = (vert ? (j) : (i)); int seg = (vert ? (i) : (j)); int max_len = (vert ? grid.width() : grid.height()); - e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + e_parallel_axis wanted_axis = chan_type == e_rr_type::CHANX ? X_AXIS : Y_AXIS; int seg_index = get_parallel_seg_index(iseg, seg_index_map, wanted_axis); /*The segment at index iseg doesn't have the proper adjacency so skip building Fc_out conenctions for it*/ @@ -4271,7 +4258,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, continue; } - const t_chan_seg_details* seg_details = (chan_type == CHANX ? chan_details_x[seg][chan] : chan_details_y[chan][seg]).data(); + const t_chan_seg_details* seg_details = (chan_type == e_rr_type::CHANX ? chan_details_x[seg][chan] : chan_details_y[chan][seg]).data(); if (seg_details[0].length() == 0) continue; @@ -4496,13 +4483,13 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, if (directs[i].to_side != NUM_2D_SIDES) { //Explicit side specified, only create if pin exists on that side - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x + directs[i].x_offset, y + directs[i].y_offset, IPIN, ipin, directs[i].to_side); + RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x + directs[i].x_offset, y + directs[i].y_offset, e_rr_type::IPIN, ipin, directs[i].to_side); if (inode) { inodes.push_back(inode); } } else { //No side specified, get all candidates - inodes = rr_graph_builder.node_lookup().find_nodes_at_all_sides(layer, x + directs[i].x_offset, y + directs[i].y_offset, IPIN, ipin); + inodes = rr_graph_builder.node_lookup().find_nodes_at_all_sides(layer, x + directs[i].x_offset, y + directs[i].y_offset, e_rr_type::IPIN, ipin); } if (inodes.size() > 0) { @@ -4634,7 +4621,7 @@ static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_gr //candidate would be picked (i.e. to minimize the drawn edge length). // //This function attempts to pick the 'best/closest' of the candidates. - VTR_ASSERT(rr_graph.node_type(from_rr) == OPIN); + VTR_ASSERT(rr_graph.node_type(from_rr) == e_rr_type::OPIN); float best_dist = std::numeric_limits::infinity(); RRNodeId best_rr = RRNodeId::INVALID(); @@ -4646,7 +4633,7 @@ static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_gr } for (RRNodeId to_rr : candidate_rr_nodes) { - VTR_ASSERT(rr_graph.node_type(to_rr) == IPIN); + VTR_ASSERT(rr_graph.node_type(to_rr) == e_rr_type::IPIN); float to_dist = std::abs(rr_graph.node_xlow(from_rr) - rr_graph.node_xlow(to_rr)) + std::abs(rr_graph.node_ylow(from_rr) - rr_graph.node_ylow(to_rr)); diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph_generation/rr_graph.h similarity index 98% rename from vpr/src/route/rr_graph.h rename to vpr/src/route/rr_graph_generation/rr_graph.h index b92db8005ea..d57077c1da9 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph_generation/rr_graph.h @@ -25,7 +25,7 @@ void create_rr_graph(e_graph_type graph_type, const std::vector& block_types, const DeviceGrid& grid, const t_chan_width& nodes_per_chan, - t_det_routing_arch* det_routing_arch, + t_det_routing_arch& det_routing_arch, const std::vector& segment_inf, const t_router_opts& router_opts, const std::vector& directs, diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph_generation/rr_graph2.cpp similarity index 75% rename from vpr/src/route/rr_graph2.cpp rename to vpr/src/route/rr_graph_generation/rr_graph2.cpp index 81763f8cdb6..0295a8cca3d 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph2.cpp @@ -1,7 +1,7 @@ #include -#include "describe_rr_node.h" #include "physical_types_util.h" +#include "vpr_utils.h" #include "vtr_util.h" #include "vtr_assert.h" @@ -24,46 +24,13 @@ static void get_switch_type(bool is_from_sb, const int switch_override, short switch_types[2]); -static void load_chan_rr_indices(const int max_chan_width, - const DeviceGrid& grid, - const int chan_len, - const int num_chans, - const t_rr_type type, - const t_chan_details& chan_details, - RRGraphBuilder& rr_graph_builder, - int* index); - -static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grid, - int* index, - bool is_flat); - -static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_type_ptr, - const std::vector& pin_num_vec, - int layer, - int root_x, - int root_y, - int* index, - const std::vector& wanted_sides); - -static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_type_ptr, - const std::vector& class_num_vec, - int layer, - int x, - int y, - int block_width, - int block_height, - int* index); - static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, - const std::vector conn_tracks, + const std::vector& conn_tracks, const int layer, const int to_chan, const int to_seg, const int to_sb, - const t_rr_type to_type, + const e_rr_type to_type, const t_chan_seg_details* seg_details, const bool from_is_sblock, const int from_switch, @@ -78,7 +45,7 @@ static int get_unidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int to_chan, const int to_seg, const int to_sb, - const t_rr_type to_type, + const e_rr_type to_type, const int max_chan_width, const DeviceGrid& grid, const enum e_side from_side, @@ -122,7 +89,7 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder, const e_side to_side, const int to_x, const int to_y, - const t_rr_type to_chan_type, + const e_rr_type to_chan_type, const int switch_override, const int custom_3d_sb_fanin_fanout, const int delayless_switch, @@ -158,7 +125,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int from_track, const int to_chan, const int to_seg, - const t_rr_type to_chan_type, + const e_rr_type to_chan_type, const e_side from_side, const e_side to_side, const int swtich_override, @@ -249,7 +216,7 @@ void dump_seg_details(t_seg_details* seg_details, // from_seg_coord: The horizontal or vertical location along the channel (i.e. y-coord for CHANY, x-coord for CHANX) // from_chan_type: The from channel type // to_chan_type: The to channel type -static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int from_chan_coord, int from_seg_coord, t_rr_type from_chan_type, t_rr_type to_chan_type); +static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int from_chan_coord, int from_seg_coord, e_rr_type from_chan_type, e_rr_type to_chan_type); static bool should_apply_switch_override(int switch_override); @@ -693,7 +660,7 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, int to_switch; int is_connected_track; t_physical_tile_type_ptr type; - t_rr_type to_type; + e_rr_type to_type; auto& device_ctx = g_vpr_ctx.device(); @@ -709,10 +676,10 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, tr_i = ((side == LEFT) ? (i - 1) : i); tr_j = ((side == BOTTOM) ? (j - 1) : j); - to_type = ((side == LEFT) || (side == RIGHT)) ? CHANY : CHANX; + to_type = ((side == LEFT) || (side == RIGHT)) ? e_rr_type::CHANY : e_rr_type::CHANX; - chan = ((to_type == CHANX) ? tr_j : tr_i); - seg = ((to_type == CHANX) ? tr_i : tr_j); + chan = ((to_type == e_rr_type::CHANX) ? tr_j : tr_i); + seg = ((to_type == e_rr_type::CHANX) ? tr_i : tr_j); bool vert = !((side == TOP) || (side == BOTTOM)); @@ -723,10 +690,10 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, if ((tr_j < 0) || (tr_j > int(device_ctx.grid.height() - 2))) { //-2 for no perimeter channels continue; } - if ((CHANX == to_type) && (tr_i < 1)) { + if ((e_rr_type::CHANX == to_type) && (tr_i < 1)) { continue; } - if ((CHANY == to_type) && (tr_j < 1)) { + if ((e_rr_type::CHANY == to_type) && (tr_j < 1)) { continue; } if (opin_to_track_map[type->index].empty()) { @@ -781,7 +748,7 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, const int seg, int Fc, const int seg_type_index, - const t_rr_type chan_type, + const e_rr_type chan_type, const t_chan_seg_details* seg_details, RRNodeId from_rr_node, t_rr_edge_info_set& rr_edges_to_create, @@ -804,15 +771,15 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(Fc % 2 == 0); /* get_rr_node_indices needs x and y coords. */ - x = ((CHANX == chan_type) ? seg : chan); - y = ((CHANX == chan_type) ? chan : seg); + x = ((e_rr_type::CHANX == chan_type) ? seg : chan); + y = ((e_rr_type::CHANX == chan_type) ? chan : seg); /* Get the lists of possible muxes. */ int dummy; std::vector inc_muxes; std::vector dec_muxes; /* AA: Determine the channel width instead of using max channels to not create hanging nodes*/ - int max_chan_width = (CHANX == chan_type) ? nodes_per_chan.x_list[y] : nodes_per_chan.y_list[x]; + int max_chan_width = (e_rr_type::CHANX == chan_type) ? nodes_per_chan.x_list[y] : nodes_per_chan.y_list[x]; label_wire_muxes(chan, seg, seg_details, seg_type_index, max_len, Direction::INC, max_chan_width, true, inc_muxes, &num_inc_muxes, &dummy); @@ -1079,61 +1046,6 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map, } } } -static void load_chan_rr_indices(const int max_chan_width, - const DeviceGrid& grid, - const int chan_len, - const int num_chans, - const t_rr_type type, - const t_chan_details& chan_details, - RRGraphBuilder& rr_graph_builder, - int* index) { - const auto& device_ctx = g_vpr_ctx.device(); - - for (int layer = 0; layer < grid.get_num_layers(); layer++) { - /* Skip the current die if architecture file specifies that it doesn't require global resource routing */ - if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { - continue; - } - for (int chan = 0; chan < num_chans - 1; ++chan) { - for (int seg = 1; seg < chan_len - 1; ++seg) { - /* Assign an inode to the starts of tracks */ - int x = (type == CHANX ? seg : chan); - int y = (type == CHANX ? chan : seg); - const t_chan_seg_details* seg_details = chan_details[x][y].data(); - - /* Reserve nodes in lookup to save memory */ - rr_graph_builder.node_lookup().reserve_nodes(layer, chan, seg, type, max_chan_width); - - for (int track = 0; track < max_chan_width; ++track) { - /* TODO: May let the length() == 0 case go through, to model muxes */ - if (seg_details[track].length() <= 0) - continue; - - int start = get_seg_start(seg_details, track, chan, seg); - - /* TODO: Now we still use the (y, x) convention here for CHANX. Should rework later */ - int node_x = chan; - int node_y = start; - if (CHANX == type) { - std::swap(node_x, node_y); - } - - /* If the start of the wire doesn't have an inode, - * assign one to it. */ - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, node_x, node_y, type, track); - if (!inode) { - inode = RRNodeId(*index); - ++(*index); - rr_graph_builder.node_lookup().add_node(inode, layer, chan, start, type, track); - } - - /* Assign inode of start of wire to current position */ - rr_graph_builder.node_lookup().add_node(inode, layer, chan, seg, type, track); - } - } - } - } -} static bool is_sb_conn_layer_crossing(enum e_side src_side, enum e_side dest_side) { if (src_side < NUM_2D_SIDES && dest_side < NUM_2D_SIDES) { @@ -1181,16 +1093,16 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m //check if both from_node and to_node exists in the rr-graph //CHANY -> CHANX connection if (check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, - conn_vector[iconn].from_wire_layer, CHANY, + conn_vector[iconn].from_wire_layer, e_rr_type::CHANY, conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, - CHANX)) { + e_rr_type::CHANX)) { num_of_3d_conn++; } //CHANX -> CHANY connection if (check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, - conn_vector[iconn].from_wire_layer, CHANX, + conn_vector[iconn].from_wire_layer, e_rr_type::CHANX, conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, - CHANY)) { + e_rr_type::CHANY)) { num_of_3d_conn++; } } @@ -1205,490 +1117,6 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m return extra_nodes_per_switchblocks; } -void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width* nodes_per_chan, - const DeviceGrid& grid, - const vtr::NdMatrix& extra_nodes_per_switchblock, - int* index) { - /* - * In case of multi-die FPGAs, we add extra nodes (could have used either CHANX or CHANY; we chose to use all CHANX) to - * support inter-die communication coming from switch blocks (connection between two tracks in different layers) - * The extra nodes have the following attribute: - * 1) type = CHANX - * 2) length = 0 (xhigh = xlow, yhigh = ylow) - * 3) ptc = [max_chanx_width:max_chanx_width+number_of_connection-1] - * 4) direction = NONE - */ - auto& device_ctx = g_vpr_ctx.device(); - - for (int layer = 0; layer < grid.get_num_layers(); layer++) { - /* Skip the current die if architecture file specifies that it doesn't have global resource routing */ - if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { - continue; - } - for (size_t y = 0; y < grid.height() - 1; ++y) { - for (size_t x = 1; x < grid.width() - 1; ++x) { - //count how many track-to-track connection go from current layer to other layers - int conn_count = extra_nodes_per_switchblock[x][y]; - - //skip if no connection is required - if (conn_count == 0) { - continue; - } - - //reserve extra nodes for inter-die track-to-track connection - rr_graph_builder.node_lookup().reserve_nodes(layer, y, x, CHANX, conn_count + nodes_per_chan->max); - for (int rr_node_offset = 0; rr_node_offset < conn_count; rr_node_offset++) { - RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x, y, CHANX, nodes_per_chan->max + rr_node_offset); - if (!inode) { - inode = RRNodeId(*index); - ++(*index); - rr_graph_builder.node_lookup().add_node(inode, layer, y, x, CHANX, nodes_per_chan->max + rr_node_offset); - } - } - } - } - } -} - -/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder - * TODO: these building functions should only talk to a RRGraphBuilder object - */ -static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grid, - int* index, - bool /*is_flat*/) { - //Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN - for (int layer = 0; layer < grid.get_num_layers(); layer++) { - for (int x = 0; x < (int)grid.width(); x++) { - for (int y = 0; y < (int)grid.height(); y++) { - //Process each block from its root location - if (grid.is_root_location({x, y, layer})) { - t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); - - //Assign indices for SINKs and SOURCEs - // Note that SINKS/SOURCES have no side, so we always use side 0 - std::vector class_num_vec = get_tile_root_classes(physical_type); - std::vector pin_num_vec = get_tile_root_pins(physical_type); - - add_classes_spatial_lookup(rr_graph_builder, - physical_type, - class_num_vec, - layer, - x, - y, - physical_type->width, - physical_type->height, - index); - - /* Limited sides for grids - * The wanted side depends on the location of the grid. - * In particular for perimeter grid, - * ------------------------------------------------------- - * Grid location | IPIN side - * ------------------------------------------------------- - * TOP | BOTTOM - * ------------------------------------------------------- - * RIGHT | LEFT - * ------------------------------------------------------- - * BOTTOM | TOP - * ------------------------------------------------------- - * LEFT | RIGHT - * ------------------------------------------------------- - * TOP-LEFT | BOTTOM & RIGHT - * ------------------------------------------------------- - * TOP-RIGHT | BOTTOM & LEFT - * ------------------------------------------------------- - * BOTTOM-LEFT | TOP & RIGHT - * ------------------------------------------------------- - * BOTTOM-RIGHT | TOP & LEFT - * ------------------------------------------------------- - * Other | First come first fit - * ------------------------------------------------------- - * - * Special for IPINs: - * If there are multiple wanted sides, first come first fit is applied - * This guarantee that there is only a unique rr_node - * for the same input pin on multiple sides, and thus avoid multiple driver problems - */ - std::vector wanted_sides; - if ((int)grid.height() - 1 == y) { /* TOP side */ - wanted_sides.push_back(BOTTOM); - } - if ((int)grid.width() - 1 == x) { /* RIGHT side */ - wanted_sides.push_back(LEFT); - } - if (0 == y) { /* BOTTOM side */ - wanted_sides.push_back(TOP); - } - if (0 == x) { /* LEFT side */ - wanted_sides.push_back(RIGHT); - } - - /* If wanted sides is empty still, this block does not have specific wanted sides, - * Deposit all the sides - */ - if (wanted_sides.empty()) { - for (e_side side : TOTAL_2D_SIDES) { - wanted_sides.push_back(side); - } - } - - add_pins_spatial_lookup(rr_graph_builder, - physical_type, - pin_num_vec, - layer, - x, - y, - index, - wanted_sides); - } - } - } - } -} -static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_type_ptr, - const std::vector& pin_num_vec, - int layer, - int root_x, - int root_y, - int* index, - const std::vector& wanted_sides) { - for (e_side side : wanted_sides) { - for (int width_offset = 0; width_offset < physical_type_ptr->width; ++width_offset) { - int x_tile = root_x + width_offset; - for (int height_offset = 0; height_offset < physical_type_ptr->height; ++height_offset) { - int y_tile = root_y + height_offset; - //only nodes on the tile may be located in a location other than the root-location - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, OPIN, physical_type_ptr->num_pins, side); - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, IPIN, physical_type_ptr->num_pins, side); - } - } - } - - for (const int pin_num : pin_num_vec) { - bool assigned_to_rr_node = false; - const auto [x_offset, y_offset, pin_sides] = get_pin_coordinates(physical_type_ptr, pin_num, wanted_sides); - e_pin_type pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); - for (int pin_coord_idx = 0; pin_coord_idx < (int)pin_sides.size(); pin_coord_idx++) { - int x_tile = root_x + x_offset[pin_coord_idx]; - int y_tile = root_y + y_offset[pin_coord_idx]; - e_side side = pin_sides[pin_coord_idx]; - if (pin_type == DRIVER) { - rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, OPIN, pin_num, side); - assigned_to_rr_node = true; - } else { - VTR_ASSERT(pin_type == RECEIVER); - rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, IPIN, pin_num, side); - assigned_to_rr_node = true; - } - } - /* A pin may locate on multiple sides of a tile. - * Instead of allocating multiple rr_nodes for the pin, - * we just create a rr_node and make it indexable on these sides - * As such, we can avoid redundant rr_node to be allocated - * and multiple nets to be mapped to the pin - * - * Considering that some pin could be just dangling, we do not need - * to create a void rr_node for it. - * As such, we only allocate a rr node when the pin is indeed located - * on at least one side - */ - if (assigned_to_rr_node) { - ++(*index); - } - } -} - -static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_type_ptr, - const std::vector& class_num_vec, - int layer, - int root_x, - int root_y, - int block_width, - int block_height, - int* index) { - for (int x_tile = root_x; x_tile < (root_x + block_width); x_tile++) { - for (int y_tile = root_y; y_tile < (root_y + block_height); y_tile++) { - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, SOURCE, class_num_vec.size(), TOTAL_2D_SIDES[0]); - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, SINK, class_num_vec.size(), TOTAL_2D_SIDES[0]); - } - } - - for (const int class_num : class_num_vec) { - e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); - e_rr_type node_type = SINK; - if (class_type == DRIVER) { - node_type = SOURCE; - } else { - VTR_ASSERT(class_type == RECEIVER); - } - - for (int x_offset = 0; x_offset < block_width; x_offset++) { - for (int y_offset = 0; y_offset < block_height; y_offset++) { - int curr_x = root_x + x_offset; - int curr_y = root_y + y_offset; - - rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, curr_x, curr_y, node_type, class_num); - } - } - - ++(*index); - } -} - -/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder */ -void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width* nodes_per_chan, - const DeviceGrid& grid, - int* index, - const t_chan_details& chan_details_x, - const t_chan_details& chan_details_y, - bool is_flat) { - /* Allocates and loads all the structures needed for fast lookups of the * - * index of an rr_node. rr_node_indices is a matrix containing the index * - * of the *first* rr_node at a given (i,j) location. */ - - /* Alloc the lookup table */ - for (t_rr_type rr_type : RR_TYPES) { - if (rr_type == CHANX) { - rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.height(), grid.width(), rr_type, NUM_2D_SIDES); - } else { - rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES); - } - } - - /* Assign indices for block nodes */ - load_block_rr_indices(rr_graph_builder, grid, index, is_flat); - - /* Load the data for x and y channels */ - load_chan_rr_indices(nodes_per_chan->x_max, grid, grid.width(), grid.height(), - CHANX, chan_details_x, rr_graph_builder, index); - load_chan_rr_indices(nodes_per_chan->y_max, grid, grid.height(), grid.width(), - CHANY, chan_details_y, rr_graph_builder, index); -} - -void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grid, - const vtr::vector& pin_chains, - const vtr::vector>& pin_chains_num, - int* index) { - for (int layer = 0; layer < grid.get_num_layers(); layer++) { - for (int x = 0; x < (int)grid.width(); x++) { - for (int y = 0; y < (int)grid.height(); y++) { - //Process each block from its root location - if (grid.is_root_location({x, y, layer})) { - t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); - //Assign indices for SINKs and SOURCEs - // Note that SINKS/SOURCES have no side, so we always use side 0 - std::vector class_num_vec; - std::vector pin_num_vec; - class_num_vec = get_cluster_netlist_intra_tile_classes_at_loc(layer, x, y, physical_type); - pin_num_vec = get_cluster_netlist_intra_tile_pins_at_loc(layer, - x, - y, - pin_chains, - pin_chains_num, - physical_type); - add_classes_spatial_lookup(rr_graph_builder, - physical_type, - class_num_vec, - layer, - x, - y, - physical_type->width, - physical_type->height, - index); - - std::vector wanted_sides; - wanted_sides.push_back(e_side::TOP); - add_pins_spatial_lookup(rr_graph_builder, - physical_type, - pin_num_vec, - layer, - x, - y, - index, - wanted_sides); - } - } - } - } -} - -/** - * Validate the node look-up matches all the node-level information - * in the storage of a routing resource graph - * This function will check the following aspects: - * - The type of each node matches its type that is indexed in the node look-up - * - For bounding box (xlow, ylow, xhigh, yhigh) of each node is indexable in the node look-up - * - The number of unique indexable nodes in the node look up matches the number of nodes in the storage - * This ensures that every node in the storage is indexable and there are no hidden nodes in the look-up - */ -bool verify_rr_node_indices(const DeviceGrid& grid, - const RRGraphView& rr_graph, - const vtr::vector& rr_indexed_data, - const t_rr_graph_storage& rr_nodes, - bool is_flat) { - std::unordered_map rr_node_counts; - - int width = grid.width(); - int height = grid.height(); - int layer = grid.get_num_layers(); - - for (int l = 0; l < layer; ++l) { - for (int x = 0; x < width; ++x) { - for (int y = 0; y < height; ++y) { - for (t_rr_type rr_type : RR_TYPES) { - /* Get the list of nodes at a specific location (x, y) */ - std::vector nodes_from_lookup; - if (rr_type == CHANX || rr_type == CHANY) { - nodes_from_lookup = rr_graph.node_lookup().find_channel_nodes(l, x, y, rr_type); - } else { - nodes_from_lookup = rr_graph.node_lookup().find_grid_nodes_at_all_sides(l, x, y, rr_type); - } - for (RRNodeId inode : nodes_from_lookup) { - rr_node_counts[inode]++; - - if (rr_graph.node_type(inode) != rr_type) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node type does not match between rr_nodes and rr_node_indices (%s/%s): %s", - rr_node_typename[rr_graph.node_type(inode)], - rr_node_typename[rr_type], - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - if (rr_graph.node_type(inode) == CHANX) { - VTR_ASSERT_MSG(rr_graph.node_ylow(inode) == rr_graph.node_yhigh(inode), "CHANX should be horizontal"); - if (y != rr_graph.node_ylow(inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node y position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", - rr_graph.node_ylow(inode), - y, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - if (!rr_graph.x_in_node_range(x, inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", - rr_graph.node_xlow(inode), - rr_graph.node_xlow(inode), - x, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - } else if (rr_graph.node_type(inode) == CHANY) { - VTR_ASSERT_MSG(rr_graph.node_xlow(inode) == rr_graph.node_xhigh(inode), "CHANY should be veritcal"); - - if (x != rr_graph.node_xlow(inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node x position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", - rr_graph.node_xlow(inode), - x, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - if (!rr_graph.y_in_node_range(y, inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node y positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", - rr_graph.node_ylow(inode), - rr_graph.node_ylow(inode), - y, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK || rr_graph.node_type(inode) == MEDIUM) { - // Sources have co-ordinates covering the entire block they are in, but not sinks - - if (!rr_graph.x_in_node_range(x, inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", - rr_graph.node_xlow(inode), - rr_graph.node_xlow(inode), - x, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - - if (!rr_graph.y_in_node_range(y, inode)) { - VPR_ERROR(VPR_ERROR_ROUTE, "RR node y positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", - rr_graph.node_ylow(inode), - rr_graph.node_ylow(inode), - y, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - } else { - VTR_ASSERT(rr_graph.node_type(inode) == IPIN || rr_graph.node_type(inode) == OPIN); - /* As we allow a pin to be indexable on multiple sides, - * This check code should be invalid - * if (rr_node.xlow() != x) { - * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%d/%d): %s", - * rr_node.xlow(), - * x, - * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); - * } - * - * if (rr_node.ylow() != y) { - * VPR_ERROR(VPR_ERROR_ROUTE, "RR node ylow does not match between rr_nodes and rr_node_indices (%d/%d): %s", - * rr_node.ylow(), - * y, - * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); - * } - */ - } - - if (rr_type == IPIN || rr_type == OPIN) { - /* As we allow a pin to be indexable on multiple sides, - * This check code should be invalid - * if (rr_node.side() != side) { - * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%s/%s): %s", - * TOTAL_2D_SIDE_STRINGS[rr_node.side()], - * TOTAL_2D_SIDE_STRINGS[side], - * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); - * } else { - * VTR_ASSERT(rr_node.side() == side); - * } - */ - } - } - } - } - } - } - - if (rr_node_counts.size() != rr_nodes.size()) { - VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch in number of unique RR nodes in rr_nodes (%zu) and rr_node_indices (%zu)", - rr_nodes.size(), - rr_node_counts.size()); - } - - for (auto kv : rr_node_counts) { - RRNodeId inode = kv.first; - int count = kv.second; - - auto& rr_node = rr_nodes[size_t(inode)]; - - if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK || rr_graph.node_type(inode) == MEDIUM) { - int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1); - int rr_height = (rr_graph.node_yhigh(rr_node.id()) - rr_graph.node_ylow(rr_node.id()) + 1); - int rr_area = rr_width * rr_height; - if (count != rr_area) { - VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node size (%d) and count within rr_node_indices (%d): %s", - rr_area, - rr_node.length(), - count, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - /* As we allow a pin to be indexable on multiple sides, - * This check code should not be applied to input and output pins - */ - } else if ((OPIN != rr_graph.node_type(inode)) && (IPIN != rr_graph.node_type(inode))) { - if (count != rr_node.length() + 1) { - VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node length (%d) and count within rr_node_indices (%d, should be length + 1): %s", - rr_node.length(), - count, - describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); - } - } - } - - return true; -} - int get_track_to_pins(RRGraphBuilder& rr_graph_builder, int layer, int seg, @@ -1722,12 +1150,12 @@ int get_track_to_pins(RRGraphBuilder& rr_graph_builder, if (is_cblock(chan, j, track, seg_details)) { for (pass = 0; pass < 2; ++pass) { //pass == 0 => TOP/RIGHT, pass == 1 => BOTTOM/LEFT e_side side; - if (CHANX == chan_type) { + if (e_rr_type::CHANX == chan_type) { x = j; y = chan + pass; side = (0 == pass ? TOP : BOTTOM); } else { - VTR_ASSERT(CHANY == chan_type); + VTR_ASSERT(e_rr_type::CHANY == chan_type); x = chan + pass; y = j; side = (0 == pass ? RIGHT : LEFT); @@ -1759,7 +1187,7 @@ int get_track_to_pins(RRGraphBuilder& rr_graph_builder, } /* Check there is a connection and Fc map isn't wrong */ - RRNodeId to_node = rr_graph_builder.node_lookup().find_node(layer_index, x, y, IPIN, ipin, side); + RRNodeId to_node = rr_graph_builder.node_lookup().find_node(layer_index, x, y, e_rr_type::IPIN, ipin, side); int switch_type = (layer_index == layer) ? wire_to_ipin_switch : wire_to_pin_between_dice_switch; if (to_node) { rr_edges_to_create.emplace_back(from_rr_node, to_node, switch_type, false); @@ -1796,9 +1224,9 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, const int from_chan, const int from_seg, const int from_track, - const t_rr_type from_type, + const e_rr_type from_type, const int to_seg, - const t_rr_type to_type, + const e_rr_type to_type, const int chan_len, const int max_chan_width, const DeviceGrid& grid, @@ -1842,11 +1270,11 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, int end_sb_seg = get_seg_end(from_seg_details, from_track, from_seg, from_chan, chan_len); /* Figure out the sides of SB the from_wire will use */ - if (CHANX == from_type) { + if (e_rr_type::CHANX == from_type) { from_side_a = RIGHT; from_side_b = LEFT; } else { - VTR_ASSERT(CHANY == from_type); + VTR_ASSERT(e_rr_type::CHANY == from_type); from_side_a = TOP; from_side_b = BOTTOM; } @@ -1901,7 +1329,7 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, /* to_chan_details may correspond to an x-directed or y-directed channel, depending on which * channel type this function is used; so coordinates are reversed as necessary */ - if (to_type == CHANX) { + if (to_type == e_rr_type::CHANX) { to_seg_details = to_chan_details[to_seg][to_chan].data(); } else { to_seg_details = to_chan_details[to_chan][to_seg].data(); @@ -1927,10 +1355,10 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, } /* Figure out which side of the SB the destination segment lies on */ - if (CHANX == to_type) { + if (e_rr_type::CHANX == to_type) { to_side = (is_behind ? RIGHT : LEFT); } else { - VTR_ASSERT(CHANY == to_type); + VTR_ASSERT(e_rr_type::CHANY == to_type); to_side = (is_behind ? TOP : BOTTOM); } @@ -2019,46 +1447,13 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, return num_conn; } -void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_tile, - int layer, - int x, - int y, - int* num_rr_nodes) { - std::vector wanted_sides{TOP, BOTTOM, LEFT, RIGHT}; - auto class_num_range = get_flat_tile_primitive_classes(physical_tile); - auto pin_num_vec = get_flat_tile_pins(physical_tile); - - std::vector class_num_vec(class_num_range.total_num()); - std::iota(class_num_vec.begin(), class_num_vec.end(), class_num_range.low); - - add_classes_spatial_lookup(rr_graph_builder, - physical_tile, - class_num_vec, - layer, - x, - y, - physical_tile->width, - physical_tile->height, - num_rr_nodes); - - add_pins_spatial_lookup(rr_graph_builder, - physical_tile, - pin_num_vec, - layer, - x, - y, - num_rr_nodes, - wanted_sides); -} - static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, - const std::vector conn_tracks, + const std::vector& conn_tracks, const int layer, const int to_chan, const int to_seg, const int to_sb, - const t_rr_type to_type, + const e_rr_type to_type, const t_chan_seg_details* seg_details, const bool from_is_sblock, const int from_switch, @@ -2072,11 +1467,11 @@ static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, short switch_types[2]; /* x, y coords for get_rr_node lookups */ - if (CHANX == to_type) { + if (e_rr_type::CHANX == to_type) { to_x = to_seg; to_y = to_chan; } else { - VTR_ASSERT(CHANY == to_type); + VTR_ASSERT(e_rr_type::CHANY == to_type); to_x = to_chan; to_y = to_seg; } @@ -2127,7 +1522,7 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder, const e_side to_side, const int to_x, const int to_y, - const t_rr_type to_chan_type, + const e_rr_type to_chan_type, const int switch_override, const int custom_3d_sb_fanin_fanout, const int delayless_switch, @@ -2200,8 +1595,8 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder, * * */ int offset = num_of_3d_conns_custom_SB[tile_x][tile_y] / custom_3d_sb_fanin_fanout; - RRNodeId track_to_chanx_node = rr_graph_builder.node_lookup().find_node(layer, tile_x, tile_y, CHANX, max_chan_width + offset); - RRNodeId diff_layer_chanx_node = rr_graph_builder.node_lookup().find_node(to_layer, tile_x, tile_y, CHANX, max_chan_width + offset); + RRNodeId track_to_chanx_node = rr_graph_builder.node_lookup().find_node(layer, tile_x, tile_y, e_rr_type::CHANX, max_chan_width + offset); + RRNodeId diff_layer_chanx_node = rr_graph_builder.node_lookup().find_node(to_layer, tile_x, tile_y, e_rr_type::CHANX, max_chan_width + offset); RRNodeId chanx_to_track_node = rr_graph_builder.node_lookup().find_node(to_layer, to_x, to_y, to_chan_type, to_wire); if (!track_to_chanx_node || !diff_layer_chanx_node || !chanx_to_track_node) { @@ -2240,7 +1635,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int from_wire, const int to_chan, const int to_seg, - const t_rr_type to_chan_type, + const e_rr_type to_chan_type, const e_side from_side, const e_side to_side, const int switch_override, @@ -2256,14 +1651,14 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, int tile_x, tile_y; /* get x/y coordinates from seg/chan coordinates */ - if (CHANX == to_chan_type) { + if (e_rr_type::CHANX == to_chan_type) { to_x = tile_x = to_seg; to_y = tile_y = to_chan; if (RIGHT == to_side) { tile_x--; } } else { - VTR_ASSERT(CHANY == to_chan_type); + VTR_ASSERT(e_rr_type::CHANY == to_chan_type); to_x = tile_x = to_chan; to_y = tile_y = to_seg; if (TOP == to_side) { @@ -2324,7 +1719,7 @@ static int get_unidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, const int to_chan, const int to_seg, const int to_sb, - const t_rr_type to_type, + const e_rr_type to_type, const int max_chan_width, const DeviceGrid& grid, const enum e_side from_side, @@ -2340,11 +1735,11 @@ static int get_unidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, std::vector mux_labels; /* x, y coords for get_rr_node lookups */ - int to_x = (CHANX == to_type ? to_seg : to_chan); - int to_y = (CHANX == to_type ? to_chan : to_seg); - int sb_x = (CHANX == to_type ? to_sb : to_chan); - int sb_y = (CHANX == to_type ? to_chan : to_sb); - int max_len = (CHANX == to_type ? grid.width() : grid.height()) - 2; //-2 for no perimeter channels + int to_x = (e_rr_type::CHANX == to_type ? to_seg : to_chan); + int to_y = (e_rr_type::CHANX == to_type ? to_chan : to_seg); + int sb_x = (e_rr_type::CHANX == to_type ? to_sb : to_chan); + int sb_y = (e_rr_type::CHANX == to_type ? to_chan : to_sb); + int max_len = (e_rr_type::CHANX == to_type ? grid.width() : grid.height()) - 2; //-2 for no perimeter channels enum Direction to_dir = Direction::DEC; if (to_sb < to_seg) { @@ -3001,15 +2396,15 @@ static int find_label_of_track(const std::vector& wire_mux_on_track, return i_label; } -static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int from_chan_coord, int from_seg_coord, t_rr_type from_chan_type, t_rr_type to_chan_type) { +static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int from_chan_coord, int from_seg_coord, e_rr_type from_chan_type, e_rr_type to_chan_type) { //Convert the chan/seg indices to real x/y coordinates int y_coord; int x_coord; - if (from_chan_type == CHANX) { + if (from_chan_type == e_rr_type::CHANX) { y_coord = from_chan_coord; x_coord = from_seg_coord; } else { - VTR_ASSERT(from_chan_type == CHANY); + VTR_ASSERT(from_chan_type == e_rr_type::CHANY); y_coord = from_seg_coord; x_coord = from_chan_coord; } @@ -3027,9 +2422,9 @@ static int should_create_switchblock(const DeviceGrid& grid, int layer_num, int return switch_override; } else if (sb_type == e_sb_type::TURNS && from_chan_type != to_chan_type) { return switch_override; - } else if (sb_type == e_sb_type::HORIZONTAL && from_chan_type == CHANX && to_chan_type == CHANX) { + } else if (sb_type == e_sb_type::HORIZONTAL && from_chan_type == e_rr_type::CHANX && to_chan_type == e_rr_type::CHANX) { return switch_override; - } else if (sb_type == e_sb_type::VERTICAL && from_chan_type == CHANY && to_chan_type == CHANY) { + } else if (sb_type == e_sb_type::VERTICAL && from_chan_type == e_rr_type::CHANY && to_chan_type == e_rr_type::CHANY) { return switch_override; } diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph_generation/rr_graph2.h similarity index 78% rename from vpr/src/route/rr_graph2.h rename to vpr/src/route/rr_graph_generation/rr_graph2.h index 71b7004197f..c4b24569993 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph_generation/rr_graph2.h @@ -1,5 +1,5 @@ -#ifndef RR_GRAPH2_H -#define RR_GRAPH2_H +#pragma once + #include #include "build_switchblocks.h" @@ -14,48 +14,6 @@ /******************* Subroutines exported by rr_graph2.c *********************/ -void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width* nodes_per_chan, - const DeviceGrid& grid, - int* index, - const t_chan_details& chan_details_x, - const t_chan_details& chan_details_y, - bool is_flat); - -/** - * @brief allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs - * - * @param rr_graph_builder RRGraphBuilder data structure which allows data modification on a routing resource graph - * @param nodes_per_chan number of tracks per channel (x, y) - * @param grid device grid - * @param extra_nodes_per_switchblock keeps how many extra length-0 CHANX node is required for each unique (x,y) location within the grid. - * Number of these extra nodes are exactly the same for all layers. Hence, we only keep it for one layer. ([0..grid.width-1][0..grid.height-1) - * @param index RRNodeId that should be assigned to add a new RR node to the RR graph - */ -void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const t_chan_width* nodes_per_chan, - const DeviceGrid& grid, - const vtr::NdMatrix& extra_nodes_per_switchblock, - int* index); - -void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, - t_physical_tile_type_ptr physical_tile, - int layer, - int x, - int y, - int* num_rr_nodes); - -void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, - const DeviceGrid& grid, - const vtr::vector& pin_chains, - const vtr::vector>& pin_chains_num, - int* index); - -bool verify_rr_node_indices(const DeviceGrid& grid, - const RRGraphView& rr_graph, - const vtr::vector& rr_indexed_data, - const t_rr_graph_storage& rr_nodes, - bool is_flat); /** * @brief goes through 3D custom switch blocks and counts how many connections are crossing dice for each switch block. * @@ -139,7 +97,7 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, const int seg, int Fc, const int seg_type_index, - const t_rr_type chan_type, + const e_rr_type chan_type, const t_chan_seg_details* seg_details, RRNodeId from_rr_node, t_rr_edge_info_set& rr_edges_to_create, @@ -169,9 +127,9 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, const int from_chan, const int from_seg, const int from_track, - const t_rr_type from_type, + const e_rr_type from_type, const int to_seg, - const t_rr_type to_type, + const e_rr_type to_type, const int chan_len, const int max_chan_width, const DeviceGrid& grid, @@ -252,4 +210,3 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map, FILE* fp); inline int get_chan_width(enum e_side side, const t_chan_width& nodes_per_channel); -#endif diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_generation/rr_graph_area.cpp similarity index 97% rename from vpr/src/route/rr_graph_area.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_area.cpp index 06b1c5e512d..3443038c82b 100644 --- a/vpr/src/route/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_area.cpp @@ -117,7 +117,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl float* shared_buffer_trans; /* [0..max(device_ctx.grid.width(),device_ctx.grid.height())] */ float *unsharable_switch_trans, *sharable_switch_trans; /* [0..num_switch-1] */ - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; int iedge, num_edges, maxlen; int iswitch, i, j, iseg, max_inputs_to_cblock; float input_cblock_trans, shared_opin_buffer_trans; @@ -175,8 +175,8 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl from_rr_type = rr_graph.node_type(from_rr_node); switch (from_rr_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: num_edges = rr_graph.num_edges(RRNodeId(from_node)); for (iedge = 0; iedge < num_edges; iedge++) { @@ -189,8 +189,8 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl } switch (to_rr_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: iswitch = rr_graph.edge_switch(RRNodeId(from_node), iedge); if (rr_graph.rr_switch_inf(RRSwitchId(iswitch)).buffered()) { @@ -210,7 +210,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl } break; - case IPIN: + case e_rr_type::IPIN: num_inputs_to_cblock[size_t(to_node)]++; max_inputs_to_cblock = std::max(max_inputs_to_cblock, num_inputs_to_cblock[size_t(to_node)]); @@ -237,7 +237,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl /* Now add in the shared buffer transistors, and reset some flags. */ - if (from_rr_type == CHANX) { + if (from_rr_type == e_rr_type::CHANX) { for (i = rr_graph.node_xlow(from_rr_node) - 1; i <= rr_graph.node_xhigh(from_rr_node); i++) { ntrans_sharing += shared_buffer_trans[i]; @@ -261,7 +261,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl } break; - case OPIN: + case e_rr_type::OPIN: num_edges = rr_graph.num_edges(RRNodeId(from_node)); shared_opin_buffer_trans = 0.; @@ -322,7 +322,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* /* corresponding to IPINs will be 0. */ - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; int i, j, iseg, iedge, num_edges, maxlen; int max_inputs_to_cblock; float input_cblock_trans; @@ -377,9 +377,9 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* from_rr_type = rr_graph.node_type(from_rr_node); switch (from_rr_type) { - case MEDIUM: - case CHANX: - case CHANY: + case e_rr_type::MEDIUM: + case e_rr_type::CHANX: + case e_rr_type::CHANY: num_edges = rr_graph.num_edges(RRNodeId(from_node)); /* Increment number of inputs per cblock if IPIN */ @@ -393,9 +393,9 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* } switch (to_rr_type) { - case MEDIUM: - case CHANX: - case CHANY: + case e_rr_type::MEDIUM: + case e_rr_type::CHANX: + case e_rr_type::CHANY: if (!chan_node_switch_done[size_t(to_node)]) { int switch_index = rr_graph.edge_switch(RRNodeId(from_node), iedge); auto switch_type = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type(); @@ -436,7 +436,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* break; - case IPIN: + case e_rr_type::IPIN: num_inputs_to_cblock[size_t(to_node)]++; max_inputs_to_cblock = std::max(max_inputs_to_cblock, num_inputs_to_cblock[size_t(to_node)]); @@ -448,7 +448,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* } break; - case SINK: + case e_rr_type::SINK: break; //ignore virtual sinks default: @@ -463,17 +463,17 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* } /* End for each edge. */ /* Reset some flags */ - if (from_rr_type == CHANX) { + if (from_rr_type == e_rr_type::CHANX) { for (i = rr_graph.node_xlow(from_rr_node); i <= rr_graph.node_xhigh(from_rr_node); i++) cblock_counted[i] = false; - } else if (from_rr_type == CHANY) { /* CHANY */ + } else if (from_rr_type == e_rr_type::CHANY) { /* CHANY */ for (j = rr_graph.node_ylow(from_rr_node); j <= rr_graph.node_yhigh(from_rr_node); j++) cblock_counted[j] = false; } break; - case OPIN: + case e_rr_type::OPIN: break; default: diff --git a/vpr/src/route/rr_graph_area.h b/vpr/src/route/rr_graph_generation/rr_graph_area.h similarity index 100% rename from vpr/src/route/rr_graph_area.h rename to vpr/src/route/rr_graph_generation/rr_graph_area.h diff --git a/vpr/src/route/rr_graph_clock.cpp b/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp similarity index 100% rename from vpr/src/route/rr_graph_clock.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_clock.cpp diff --git a/vpr/src/route/rr_graph_clock.h b/vpr/src/route/rr_graph_generation/rr_graph_clock.h similarity index 100% rename from vpr/src/route/rr_graph_clock.h rename to vpr/src/route/rr_graph_generation/rr_graph_clock.h diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.cpp similarity index 100% rename from vpr/src/route/rr_graph_indexed_data.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_indexed_data.cpp diff --git a/vpr/src/route/rr_graph_indexed_data.h b/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.h similarity index 100% rename from vpr/src/route/rr_graph_indexed_data.h rename to vpr/src/route/rr_graph_generation/rr_graph_indexed_data.h diff --git a/vpr/src/route/rr_graph_sbox.cpp b/vpr/src/route/rr_graph_generation/rr_graph_sbox.cpp similarity index 100% rename from vpr/src/route/rr_graph_sbox.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_sbox.cpp diff --git a/vpr/src/route/rr_graph_sbox.h b/vpr/src/route/rr_graph_generation/rr_graph_sbox.h similarity index 87% rename from vpr/src/route/rr_graph_sbox.h rename to vpr/src/route/rr_graph_generation/rr_graph_sbox.h index 87843f57a1a..d50d9a50edb 100644 --- a/vpr/src/route/rr_graph_sbox.h +++ b/vpr/src/route/rr_graph_generation/rr_graph_sbox.h @@ -6,10 +6,10 @@ std::vector get_switch_box_tracks(const int from_i, const int from_j, const int from_track, - const t_rr_type from_type, + const e_rr_type from_type, const int to_i, const int to_j, - const t_rr_type to_type, + const e_rr_type to_type, const std::vector*** switch_block_conn); vtr::NdMatrix, 3> alloc_and_load_switch_block_conn(t_chan_width* nodes_per_chan, diff --git a/vpr/src/route/rr_graph_timing_params.cpp b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp similarity index 94% rename from vpr/src/route/rr_graph_timing_params.cpp rename to vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp index d2c478dffe6..71316392626 100644 --- a/vpr/src/route/rr_graph_timing_params.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp @@ -26,7 +26,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { size_t to_node; int icblock, isblock, iseg_low, iseg_high; float Cin, Cout; - t_rr_type from_rr_type, to_rr_type; + e_rr_type from_rr_type, to_rr_type; bool* cblock_counted; /* [0..maxlen-1] -- 0th element unused. */ float* buffer_Cin; /* [0..maxlen-1] */ bool buffered; @@ -53,12 +53,12 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { from_rr_type = rr_graph.node_type(rr_id); - if ((from_rr_type == CHANX || from_rr_type == CHANY)) { + if ((from_rr_type == e_rr_type::CHANX || from_rr_type == e_rr_type::CHANY)) { for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) { to_node = size_t(rr_graph.edge_sink_node(rr_id, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type == CHANX || to_rr_type == CHANY) { + if (to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY) { switch_index = rr_graph.edge_switch(rr_id, iedge); Cin = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cin; Cout = rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cout; @@ -99,7 +99,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { } /* End edge to CHANX or CHANY node. */ - else if (to_rr_type == IPIN) { + else if (to_rr_type == e_rr_type::IPIN) { if (INCLUDE_TRACK_BUFFERS) { /* Implements sharing of the track to connection box buffer. * Such a buffer exists at every segment of the wire at which @@ -129,7 +129,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { * } * } */ - if (from_rr_type == CHANX) { + if (from_rr_type == e_rr_type::CHANX) { iseg_low = rr_graph.node_xlow(rr_id); iseg_high = rr_graph.node_xhigh(rr_id); } else { /* CHANY */ @@ -148,13 +148,13 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { } /* End node is CHANX or CHANY */ - else if (from_rr_type == OPIN) { + else if (from_rr_type == e_rr_type::OPIN) { for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) { switch_index = rr_graph.edge_switch(rr_id, iedge); to_node = size_t(rr_graph.edge_sink_node(rr_id, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type != CHANX && to_rr_type != CHANY) + if (to_rr_type != e_rr_type::CHANX && to_rr_type != e_rr_type::CHANY) continue; if (rr_graph.node_direction(RRNodeId(to_node)) == Direction::BIDIR) { @@ -179,7 +179,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { switch_index = rr_graph.edge_switch(inode, iedge); to_node = size_t(rr_graph.edge_sink_node(inode, iedge)); to_rr_type = rr_graph.node_type(RRNodeId(to_node)); - if (to_rr_type == CHANX || to_rr_type == CHANY) { + if (to_rr_type == e_rr_type::CHANX || to_rr_type == e_rr_type::CHANY) { if (rr_graph.node_direction(RRNodeId(to_node)) != Direction::BIDIR) { /* Cout was not added in these cases */ Couts_to_add[to_node] = std::max(Couts_to_add[to_node], rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cout); diff --git a/vpr/src/route/rr_graph_timing_params.h b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.h similarity index 100% rename from vpr/src/route/rr_graph_timing_params.h rename to vpr/src/route/rr_graph_generation/rr_graph_timing_params.h diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp new file mode 100644 index 00000000000..99c1a729e6c --- /dev/null +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -0,0 +1,613 @@ + +#include "rr_node_indices.h" + +#include "describe_rr_node.h" +#include "globals.h" +#include "physical_types_util.h" +#include "vpr_utils.h" + +/** + * @brief Assigns and loads rr_node indices for block-level routing resources (SOURCE, SINK, IPIN, OPIN). + * + * This function walks through the device grid and assigns unique rr_node indices to the routing resources + * associated with each block (tiles). + * + * For SINKs and SOURCEs, it uses side 0 by convention (since they have no geometric side). For IPINs and OPINs, + * it determines the correct sides based on the tile's position in the grid, following special rules for + * edge and corner tiles. + * + * The index counter is passed and updated as rr_nodes are added. + */ +static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grid, + int* index); + +/** + * @brief Populates the lookup indices for channel (CHANX or CHANY) RR nodes. + * + * This function builds part of the RR spatial lookup structure, specifically + * the RR nodes associated with routing channels (CHANX or CHANY). + * + * @param max_chan_width Maximum channel width (number of tracks). + * @param grid Device grid layout. + * @param chan_len Length of the channel being processed. + * @param num_chans Total number of channels in the direction being processed. + * @param type RR node type: should be CHANX or CHANY. + * @param chan_details Channel details used to determine segment and track information. + * @param node_lookup Spatial RR node lookup to be filled by this function. + * @param index The next available RR node index. + */ +static void load_chan_rr_indices(const int max_chan_width, + const DeviceGrid& grid, + const int chan_len, + const int num_chans, + const e_rr_type type, + const t_chan_details& chan_details, + RRSpatialLookup& node_lookup, + int* index); + +static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_type_ptr, + const std::vector& class_num_vec, + int layer, + int x, + int y, + int block_width, + int block_height, + int* index); + +static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_type_ptr, + const std::vector& pin_num_vec, + int layer, + int root_x, + int root_y, + int* index, + const std::vector& wanted_sides); + +/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder + * TODO: these building functions should only talk to a RRGraphBuilder object + */ +static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grid, + int* index) { + // Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN + for (int layer = 0; layer < grid.get_num_layers(); layer++) { + for (int x = 0; x < (int)grid.width(); x++) { + for (int y = 0; y < (int)grid.height(); y++) { + //Process each block from its root location + if (grid.is_root_location({x, y, layer})) { + t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); + + // Assign indices for SINKs and SOURCEs + // Note that SINKS/SOURCES have no side, so we always use side 0 + std::vector class_num_vec = get_tile_root_classes(physical_type); + std::vector pin_num_vec = get_tile_root_pins(physical_type); + + add_classes_spatial_lookup(rr_graph_builder, + physical_type, + class_num_vec, + layer, + x, + y, + physical_type->width, + physical_type->height, + index); + + /* Limited sides for grids + * The wanted side depends on the location of the grid. + * In particular for perimeter grid, + * ------------------------------------------------------- + * Grid location | IPIN side + * ------------------------------------------------------- + * TOP | BOTTOM + * ------------------------------------------------------- + * RIGHT | LEFT + * ------------------------------------------------------- + * BOTTOM | TOP + * ------------------------------------------------------- + * LEFT | RIGHT + * ------------------------------------------------------- + * TOP-LEFT | BOTTOM & RIGHT + * ------------------------------------------------------- + * TOP-RIGHT | BOTTOM & LEFT + * ------------------------------------------------------- + * BOTTOM-LEFT | TOP & RIGHT + * ------------------------------------------------------- + * BOTTOM-RIGHT | TOP & LEFT + * ------------------------------------------------------- + * Other | First come first fit + * ------------------------------------------------------- + * + * Special for IPINs: + * If there are multiple wanted sides, first come first fit is applied + * This guarantee that there is only a unique rr_node + * for the same input pin on multiple sides, and thus avoid multiple driver problems + */ + std::vector wanted_sides; + if ((int)grid.height() - 1 == y) { // TOP side + wanted_sides.push_back(BOTTOM); + } + if ((int)grid.width() - 1 == x) { // RIGHT side + wanted_sides.push_back(LEFT); + } + if (0 == y) { // BOTTOM side + wanted_sides.push_back(TOP); + } + if (0 == x) { // LEFT side + wanted_sides.push_back(RIGHT); + } + + // If wanted sides is empty still, this block does not have specific wanted sides, Deposit all the sides + if (wanted_sides.empty()) { + for (e_side side : TOTAL_2D_SIDES) { + wanted_sides.push_back(side); + } + } + + add_pins_spatial_lookup(rr_graph_builder, + physical_type, + pin_num_vec, + layer, + x, + y, + index, + wanted_sides); + } + } + } + } +} + +static void load_chan_rr_indices(const int max_chan_width, + const DeviceGrid& grid, + const int chan_len, + const int num_chans, + const e_rr_type type, + const t_chan_details& chan_details, + RRSpatialLookup& node_lookup, + int* index) { + const auto& device_ctx = g_vpr_ctx.device(); + + for (int layer = 0; layer < grid.get_num_layers(); layer++) { + // Skip the current die if architecture file specifies that it doesn't require global resource routing + if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { + continue; + } + + for (int chan = 0; chan < num_chans - 1; ++chan) { + for (int seg = 1; seg < chan_len - 1; ++seg) { + // Assign an inode to the starts of tracks + const int x = (type == e_rr_type::CHANX) ? seg : chan; + const int y = (type == e_rr_type::CHANX) ? chan : seg; + const t_chan_seg_details* seg_details = chan_details[x][y].data(); + + // Reserve nodes in lookup to save memory + node_lookup.reserve_nodes(layer, x, y, type, max_chan_width); + + for (int track = 0; track < max_chan_width; ++track) { + /* TODO: May let the length() == 0 case go through, to model muxes */ + if (seg_details[track].length() <= 0) + continue; + + int start = get_seg_start(seg_details, track, chan, seg); + int node_start_x = (type == e_rr_type::CHANX) ? start : chan; + int node_start_y = (type == e_rr_type::CHANX) ? chan : start; + + // If the start of the wire doesn't have an RRNodeId, assign one to it. + RRNodeId inode = node_lookup.find_node(layer, node_start_x, node_start_y, type, track); + if (!inode) { + inode = RRNodeId(*index); + ++(*index); + node_lookup.add_node(inode, layer, node_start_x, node_start_y, type, track); + } + + // Assign RRNodeId of start of wire to current position + node_lookup.add_node(inode, layer, x, y, type, track); + } + } + } + } +} + +static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_type_ptr, + const std::vector& class_num_vec, + int layer, + int root_x, + int root_y, + int block_width, + int block_height, + int* index) { + for (int x_tile = root_x; x_tile < (root_x + block_width); x_tile++) { + for (int y_tile = root_y; y_tile < (root_y + block_height); y_tile++) { + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::SOURCE, class_num_vec.size(), TOTAL_2D_SIDES[0]); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::SINK, class_num_vec.size(), TOTAL_2D_SIDES[0]); + } + } + + for (const int class_num : class_num_vec) { + e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); + e_rr_type node_type = e_rr_type::SINK; + if (class_type == DRIVER) { + node_type = e_rr_type::SOURCE; + } else { + VTR_ASSERT(class_type == RECEIVER); + } + + for (int x_offset = 0; x_offset < block_width; x_offset++) { + for (int y_offset = 0; y_offset < block_height; y_offset++) { + int curr_x = root_x + x_offset; + int curr_y = root_y + y_offset; + + rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, curr_x, curr_y, node_type, class_num); + } + } + + ++(*index); + } +} + +static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_type_ptr, + const std::vector& pin_num_vec, + int layer, + int root_x, + int root_y, + int* index, + const std::vector& wanted_sides) { + for (e_side side : wanted_sides) { + for (int width_offset = 0; width_offset < physical_type_ptr->width; ++width_offset) { + int x_tile = root_x + width_offset; + for (int height_offset = 0; height_offset < physical_type_ptr->height; ++height_offset) { + int y_tile = root_y + height_offset; + // only nodes on the tile may be located in a location other than the root-location + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::OPIN, physical_type_ptr->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::IPIN, physical_type_ptr->num_pins, side); + } + } + } + + for (const int pin_num : pin_num_vec) { + bool assigned_to_rr_node = false; + const auto [x_offset, y_offset, pin_sides] = get_pin_coordinates(physical_type_ptr, pin_num, wanted_sides); + e_pin_type pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); + for (int pin_coord_idx = 0; pin_coord_idx < (int)pin_sides.size(); pin_coord_idx++) { + int x_tile = root_x + x_offset[pin_coord_idx]; + int y_tile = root_y + y_offset[pin_coord_idx]; + e_side side = pin_sides[pin_coord_idx]; + if (pin_type == DRIVER) { + rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::OPIN, pin_num, side); + assigned_to_rr_node = true; + } else { + VTR_ASSERT(pin_type == RECEIVER); + rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::IPIN, pin_num, side); + assigned_to_rr_node = true; + } + } + /* A pin may locate on multiple sides of a tile. + * Instead of allocating multiple rr_nodes for the pin, + * we just create a rr_node and make it indexable on these sides + * As such, we can avoid redundant rr_node to be allocated + * and multiple nets to be mapped to the pin + * + * Considering that some pin could be just dangling, we do not need + * to create a void rr_node for it. + * As such, we only allocate a rr node when the pin is indeed located + * on at least one side + */ + if (assigned_to_rr_node) { + ++(*index); + } + } +} + +void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const t_chan_width& nodes_per_chan, + const DeviceGrid& grid, + int* index, + const t_chan_details& chan_details_x, + const t_chan_details& chan_details_y) { + // Alloc the lookup table + for (e_rr_type rr_type : RR_TYPES) { + rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES); + } + + // Assign indices for block nodes + load_block_rr_indices(rr_graph_builder, grid, index); + + // Load the data for x and y channels + load_chan_rr_indices(nodes_per_chan.x_max, grid, grid.width(), grid.height(), + e_rr_type::CHANX, chan_details_x, rr_graph_builder.node_lookup(), index); + load_chan_rr_indices(nodes_per_chan.y_max, grid, grid.height(), grid.width(), + e_rr_type::CHANY, chan_details_y, rr_graph_builder.node_lookup(), index); +} + +void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const t_chan_width& nodes_per_chan, + const DeviceGrid& grid, + const vtr::NdMatrix& extra_nodes_per_switchblock, + int* index) { + /* + * In case of multi-die FPGAs, we add extra nodes (could have used either CHANX or CHANY; we chose to use all CHANX) to + * support inter-die communication coming from switch blocks (connection between two tracks in different layers) + * The extra nodes have the following attribute: + * 1) type = CHANX + * 2) length = 0 (xhigh = xlow, yhigh = ylow) + * 3) ptc = [max_chanx_width:max_chanx_width+number_of_connection-1] + * 4) direction = NONE + */ + const auto& device_ctx = g_vpr_ctx.device(); + + for (int layer = 0; layer < grid.get_num_layers(); layer++) { + // Skip the current die if architecture file specifies that it doesn't have global resource routing + if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { + continue; + } + + for (size_t y = 0; y < grid.height() - 1; ++y) { + for (size_t x = 1; x < grid.width() - 1; ++x) { + // count how many track-to-track connection go from current layer to other layers + int conn_count = extra_nodes_per_switchblock[x][y]; + + // skip if no connection is required + if (conn_count == 0) { + continue; + } + + // reserve extra nodes for inter-die track-to-track connection + rr_graph_builder.node_lookup().reserve_nodes(layer, x, y, e_rr_type::CHANX, conn_count + nodes_per_chan.max); + for (int rr_node_offset = 0; rr_node_offset < conn_count; rr_node_offset++) { + RRNodeId inode = rr_graph_builder.node_lookup().find_node(layer, x, y, e_rr_type::CHANX, nodes_per_chan.max + rr_node_offset); + if (!inode) { + inode = RRNodeId(*index); + ++(*index); + rr_graph_builder.node_lookup().add_node(inode, layer, x, y, e_rr_type::CHANX, nodes_per_chan.max + rr_node_offset); + } + } + } + } + } +} + +void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_tile, + int layer, + int x, + int y, + int* num_rr_nodes) { + std::vector wanted_sides{TOP, BOTTOM, LEFT, RIGHT}; + auto class_num_range = get_flat_tile_primitive_classes(physical_tile); + auto pin_num_vec = get_flat_tile_pins(physical_tile); + + std::vector class_num_vec(class_num_range.total_num()); + std::iota(class_num_vec.begin(), class_num_vec.end(), class_num_range.low); + + add_classes_spatial_lookup(rr_graph_builder, + physical_tile, + class_num_vec, + layer, + x, + y, + physical_tile->width, + physical_tile->height, + num_rr_nodes); + + add_pins_spatial_lookup(rr_graph_builder, + physical_tile, + pin_num_vec, + layer, + x, + y, + num_rr_nodes, + wanted_sides); +} + +void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grid, + const vtr::vector& pin_chains, + const vtr::vector>& pin_chains_num, + int* index) { + for (int layer = 0; layer < grid.get_num_layers(); layer++) { + for (int x = 0; x < (int)grid.width(); x++) { + for (int y = 0; y < (int)grid.height(); y++) { + // Process each block from its root location + if (grid.is_root_location({x, y, layer})) { + t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); + // Assign indices for SINKs and SOURCEs + // Note that SINKS/SOURCES have no side, so we always use side 0 + std::vector class_num_vec; + std::vector pin_num_vec; + class_num_vec = get_cluster_netlist_intra_tile_classes_at_loc(layer, x, y, physical_type); + pin_num_vec = get_cluster_netlist_intra_tile_pins_at_loc(layer, + x, + y, + pin_chains, + pin_chains_num, + physical_type); + add_classes_spatial_lookup(rr_graph_builder, + physical_type, + class_num_vec, + layer, + x, + y, + physical_type->width, + physical_type->height, + index); + + std::vector wanted_sides; + wanted_sides.push_back(e_side::TOP); + add_pins_spatial_lookup(rr_graph_builder, + physical_type, + pin_num_vec, + layer, + x, + y, + index, + wanted_sides); + } + } + } + } +} + +bool verify_rr_node_indices(const DeviceGrid& grid, + const RRGraphView& rr_graph, + const vtr::vector& rr_indexed_data, + const t_rr_graph_storage& rr_nodes, + bool is_flat) { + std::unordered_map rr_node_counts; + + int width = grid.width(); + int height = grid.height(); + int layer = grid.get_num_layers(); + + for (int l = 0; l < layer; ++l) { + for (int x = 0; x < width; ++x) { + for (int y = 0; y < height; ++y) { + for (e_rr_type rr_type : RR_TYPES) { + // Get the list of nodes at a specific location (x, y) + std::vector nodes_from_lookup; + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { + nodes_from_lookup = rr_graph.node_lookup().find_channel_nodes(l, x, y, rr_type); + } else { + nodes_from_lookup = rr_graph.node_lookup().find_grid_nodes_at_all_sides(l, x, y, rr_type); + } + + for (RRNodeId inode : nodes_from_lookup) { + rr_node_counts[inode]++; + + if (rr_graph.node_type(inode) != rr_type) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node type does not match between rr_nodes and rr_node_indices (%s/%s): %s", + rr_node_typename[rr_graph.node_type(inode)], + rr_node_typename[rr_type], + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + + if (rr_graph.node_type(inode) == e_rr_type::CHANX) { + VTR_ASSERT_MSG(rr_graph.node_ylow(inode) == rr_graph.node_yhigh(inode), "CHANX should be horizontal"); + if (y != rr_graph.node_ylow(inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node y position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", + rr_graph.node_ylow(inode), + y, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + + if (!rr_graph.x_in_node_range(x, inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", + rr_graph.node_xlow(inode), + rr_graph.node_xlow(inode), + x, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + } else if (rr_graph.node_type(inode) == e_rr_type::CHANY) { + VTR_ASSERT_MSG(rr_graph.node_xlow(inode) == rr_graph.node_xhigh(inode), "CHANY should be vertical"); + + if (x != rr_graph.node_xlow(inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node x position does not agree between rr_nodes (%d) and rr_node_indices (%d): %s", + rr_graph.node_xlow(inode), + x, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + + if (!rr_graph.y_in_node_range(y, inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node y positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", + rr_graph.node_ylow(inode), + rr_graph.node_ylow(inode), + y, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { + // Sources have co-ordinates covering the entire block they are in, but not sinks + if (!rr_graph.x_in_node_range(x, inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", + rr_graph.node_xlow(inode), + rr_graph.node_xlow(inode), + x, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + + if (!rr_graph.y_in_node_range(y, inode)) { + VPR_ERROR(VPR_ERROR_ROUTE, "RR node y positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", + rr_graph.node_ylow(inode), + rr_graph.node_ylow(inode), + y, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + } else { + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::IPIN || rr_graph.node_type(inode) == e_rr_type::OPIN); + /* As we allow a pin to be indexable on multiple sides, + * This check code should be invalid + * if (rr_node.xlow() != x) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%d/%d): %s", + * rr_node.xlow(), + * x, + * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); + * } + * + * if (rr_node.ylow() != y) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node ylow does not match between rr_nodes and rr_node_indices (%d/%d): %s", + * rr_node.ylow(), + * y, + * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); + * } + */ + } + + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { + /* As we allow a pin to be indexable on multiple sides, + * This check code should be invalid + * if (rr_node.side() != side) { + * VPR_ERROR(VPR_ERROR_ROUTE, "RR node xlow does not match between rr_nodes and rr_node_indices (%s/%s): %s", + * TOTAL_2D_SIDE_STRINGS[rr_node.side()], + * TOTAL_2D_SIDE_STRINGS[side], + * describe_rr_node(rr_graph, grid, rr_indexed_data, inode).c_str()); + * } else { + * VTR_ASSERT(rr_node.side() == side); + * } + */ + } + } + } + } + } + } + + if (rr_node_counts.size() != rr_nodes.size()) { + VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch in number of unique RR nodes in rr_nodes (%zu) and rr_node_indices (%zu)", + rr_nodes.size(), + rr_node_counts.size()); + } + + for (auto kv : rr_node_counts) { + RRNodeId inode = kv.first; + int count = kv.second; + + const t_rr_node& rr_node = rr_nodes[size_t(inode)]; + + if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { + int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1); + int rr_height = (rr_graph.node_yhigh(rr_node.id()) - rr_graph.node_ylow(rr_node.id()) + 1); + int rr_area = rr_width * rr_height; + if (count != rr_area) { + VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node size (%d) and count within rr_node_indices (%d): %s", + rr_area, + rr_node.length(), + count, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + // As we allow a pin to be indexable on multiple sides, + // This check code should not be applied to input and output pins + + } else if ((e_rr_type::OPIN != rr_graph.node_type(inode)) && (e_rr_type::IPIN != rr_graph.node_type(inode))) { + if (count != rr_node.length() + 1) { + VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node length (%d) and count within rr_node_indices (%d, should be length + 1): %s", + rr_node.length(), + count, + describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); + } + } + } + + return true; +} diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.h b/vpr/src/route/rr_graph_generation/rr_node_indices.h new file mode 100644 index 00000000000..76373c1cc70 --- /dev/null +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.h @@ -0,0 +1,88 @@ +#pragma once + +#include "rr_graph_builder.h" +#include "rr_graph_view.h" +#include "device_grid.h" +#include "rr_types.h" +#include "rr_graph_type.h" +#include "rr_graph_utils.h" +#include "clustered_netlist_fwd.h" + +/** + * @brief Allocates and populates data structures for efficient rr_node index lookups. + * + * This function sets up the `rr_node_indices` structure, which maps a physical location + * and type to the index of the first corresponding rr_node. + * + * @param rr_graph_builder Reference to the RRGraphBuilder used to construct and populate RR node spatial lookups. + * @param nodes_per_chan Specifies the maximum number of routing tracks per channel in the x and y directions. + * @param grid The device grid representing the physical layout of tiles in the FPGA fabric. + * @param index Pointer to the global RR node index counter; incremented as new RR nodes are assigned. + * @param chan_details_x Channel details describing segment and track properties for CHANX (horizontal) routing tracks. + * @param chan_details_y Channel details describing segment and track properties for CHANY (vertical) routing tracks. + */ +void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const t_chan_width& nodes_per_chan, + const DeviceGrid& grid, + int* index, + const t_chan_details& chan_details_x, + const t_chan_details& chan_details_y); + +/** + * @brief Allocates extra nodes within the RR graph to support 3D custom switch blocks for multi-die FPGAs + * + * @param rr_graph_builder RRGraphBuilder data structure which allows data modification on a routing resource graph + * @param nodes_per_chan number of tracks per channel (x, y) + * @param grid The device grid representing the physical layout of tiles in the FPGA fabric. + * @param extra_nodes_per_switchblock keeps how many extra length-0 CHANX node is required for each unique (x,y) location within the grid. + * Number of these extra nodes are exactly the same for all layers. Hence, we only keep it for one layer. ([0..grid.width-1][0..grid.height-1) + * @param index Pointer to the global RR node index counter; incremented as new RR nodes are assigned. + */ +void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const t_chan_width& nodes_per_chan, + const DeviceGrid& grid, + const vtr::NdMatrix& extra_nodes_per_switchblock, + int* index); + +/** + * @brief Allocates and loads RR node indices for a specific tile. + * + * This function assigns RR node IDs to all classes (SOURCE/SINK) and pins (IPIN/OPIN) + * associated with a given physical tile at a specific grid location and layer. + * It is primarily used in scenarios where a standalone tile's routing resources + * need to be initialized independently. + * + * @param rr_graph_builder Reference to the RR graph builder with spatial lookup. + * @param physical_tile Pointer to the physical tile type being processed. + * @param layer Layer index of the tile in the device grid. + * @param x X-coordinate of the tile's root position in the grid. + * @param y Y-coordinate of the tile's root position in the grid. + * @param num_rr_nodes Pointer to the global RR node index counter (will be incremented). + */ +void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, + t_physical_tile_type_ptr physical_tile, + int layer, + int x, + int y, + int* num_rr_nodes); + +void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grid, + const vtr::vector& pin_chains, + const vtr::vector>& pin_chains_num, + int* index); + +/** + * Validate the node look-up matches all the node-level information + * in the storage of a routing resource graph + * This function will check the following aspects: + * - The type of each node matches its type that is indexed in the node look-up + * - For bounding box (xlow, ylow, xhigh, yhigh) of each node is indexable in the node look-up + * - The number of unique indexable nodes in the node look up matches the number of nodes in the storage + * This ensures that every node in the storage is indexable and there are no hidden nodes in the look-up + */ +bool verify_rr_node_indices(const DeviceGrid& grid, + const RRGraphView& rr_graph, + const vtr::vector& rr_indexed_data, + const t_rr_graph_storage& rr_nodes, + bool is_flat); diff --git a/vpr/src/route/rr_types.h b/vpr/src/route/rr_graph_generation/rr_types.h similarity index 99% rename from vpr/src/route/rr_types.h rename to vpr/src/route/rr_graph_generation/rr_types.h index 8e093faca75..620427a2d11 100644 --- a/vpr/src/route/rr_types.h +++ b/vpr/src/route/rr_graph_generation/rr_types.h @@ -1,5 +1,6 @@ #ifndef RR_TYPES_H #define RR_TYPES_H + #include #include "vtr_ndmatrix.h" @@ -14,7 +15,7 @@ typedef std::vector, 5>> t_pin_to_track_lookup; -/* AA: t_pin_to_track_lookup is alloacted first and is then converted to t_track_to_pin lookup by simply redefining the accessing order. +/* AA: t_pin_to_track_lookup is alloacted first and is then converted to t_track_to_pin lookup by simply redefining the accessing order. * As a result, the matrix should be accessed as follow as a result after allocation in rr_graph.cpp: alloc_track_to_pin_lookup (used by unidir and bidir) * [0..device_ctx.physical_tile_types.size()-1][0..max_chan_width-1][0..width][0..height][0..layer-1][0..3] * diff --git a/vpr/src/route/segment_stats.cpp b/vpr/src/route/segment_stats.cpp index f05e0874cdb..3d7de733ce3 100644 --- a/vpr/src/route/segment_stats.cpp +++ b/vpr/src/route/segment_stats.cpp @@ -1,4 +1,3 @@ -#include #include "vtr_log.h" #include "vtr_memory.h" @@ -60,14 +59,14 @@ void get_segment_usage_stats(std::vector& segment_inf) { for (RRNodeId inode : device_ctx.rr_graph.nodes()) { auto node_type = rr_graph.node_type(inode); - if (node_type == CHANX || node_type == CHANY) { + if (node_type == e_rr_type::CHANX || node_type == e_rr_type::CHANY) { cost_index = rr_graph.node_cost_index(inode); size_t seg_type = device_ctx.rr_indexed_data[cost_index].seg_index; int length = segment_inf[seg_type].longline ? LONGLINE : segment_inf[seg_type].length; const short& inode_capacity = rr_graph.node_capacity(inode); int occ = route_ctx.rr_node_route_inf[inode].occ(); - auto ax = (node_type == CHANX) ? X_AXIS : Y_AXIS; + auto ax = (node_type == e_rr_type::CHANX) ? X_AXIS : Y_AXIS; directed_occ_by_length[ax][length] += occ; directed_cap_by_length[ax][length] += inode_capacity; diff --git a/vpr/src/route/serial_connection_router.cpp b/vpr/src/route/serial_connection_router.cpp new file mode 100644 index 00000000000..3bb2d2b64a2 --- /dev/null +++ b/vpr/src/route/serial_connection_router.cpp @@ -0,0 +1,533 @@ +#include "serial_connection_router.h" + +#include +#include "rr_graph.h" +#include "rr_graph_fwd.h" + +/** Used to update router statistics for serial connection router */ +inline void update_serial_router_stats(RouterStats* router_stats, + bool is_push, + RRNodeId rr_node_id, + const RRGraphView* rr_graph); + +template +void SerialConnectionRouter::timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) { + const auto& device_ctx = g_vpr_ctx.device(); + auto& route_ctx = g_vpr_ctx.mutable_routing(); + + HeapNode cheapest; + while (this->heap_.try_pop(cheapest)) { + // Pop a new inode with the cheapest total cost in current route tree to be expanded on + const auto& [new_total_cost, inode] = cheapest; + update_serial_router_stats(this->router_stats_, + /*is_push=*/false, + inode, + this->rr_graph_); + + VTR_LOGV_DEBUG(this->router_debug_, " Popping node %d (cost: %g)\n", + inode, new_total_cost); + + // Have we found the target? + if (inode == sink_node) { + // If we're running RCV, the path will be stored in the path_data->path_rr vector + // This is then placed into the traceback so that the correct path is returned + // TODO: This can be eliminated by modifying the actual traceback function in route_timing + if (this->rcv_path_manager.is_enabled()) { + this->rcv_path_manager.insert_backwards_path_into_traceback(this->rcv_path_data[inode], + this->rr_node_route_inf_[inode].path_cost, + this->rr_node_route_inf_[inode].backward_path_cost, + route_ctx); + } + VTR_LOGV_DEBUG(this->router_debug_, " Found target %8d (%s)\n", inode, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, this->is_flat_).c_str()); + break; + } + + // If not, keep searching + timing_driven_expand_cheapest(inode, + new_total_cost, + sink_node, + cost_params, + bounding_box, + target_bb); + } +} + +template +vtr::vector SerialConnectionRouter::timing_driven_find_all_shortest_paths_from_route_tree( + const RouteTreeNode& rt_root, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) { + this->router_stats_ = &router_stats; + this->conn_params_ = &conn_params; + + // Add the route tree to the heap with no specific target node + RRNodeId target_node = RRNodeId::INVALID(); + this->add_route_tree_to_heap(rt_root, target_node, cost_params, bounding_box); + this->heap_.build_heap(); // via sifting down everything + + auto res = timing_driven_find_all_shortest_paths_from_heap(cost_params, bounding_box); + this->heap_.empty_heap(); + + return res; +} + +template +vtr::vector SerialConnectionRouter::timing_driven_find_all_shortest_paths_from_heap( + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) { + // Since there is no single *target* node this uses Dijkstra's algorithm + // with a modified exit condition (runs until heap is empty). + + vtr::vector cheapest_paths(this->rr_nodes_.size()); + + VTR_ASSERT_SAFE(this->heap_.is_valid()); + + if (this->heap_.is_empty_heap()) { // No source + VTR_LOGV_DEBUG(this->router_debug_, " Initial heap empty (no source)\n"); + } + + // Start measuring path search time + std::chrono::steady_clock::time_point begin_time = std::chrono::steady_clock::now(); + + HeapNode cheapest; + while (this->heap_.try_pop(cheapest)) { + // Pop a new inode with the cheapest total cost in current route tree to be expanded on + const auto& [new_total_cost, inode] = cheapest; + update_serial_router_stats(this->router_stats_, + /*is_push=*/false, + inode, + this->rr_graph_); + + VTR_LOGV_DEBUG(this->router_debug_, " Popping node %d (cost: %g)\n", + inode, new_total_cost); + + // Since we want to find shortest paths to all nodes in the graph + // we do not specify a target node. + // + // By setting the target_node to INVALID in combination with the NoOp router + // lookahead we can re-use the node exploration code from the regular router + RRNodeId target_node = RRNodeId::INVALID(); + + timing_driven_expand_cheapest(inode, + new_total_cost, + target_node, + cost_params, + bounding_box, + t_bb()); + + if (cheapest_paths[inode].index == RRNodeId::INVALID() || cheapest_paths[inode].total_cost >= new_total_cost) { + VTR_LOGV_DEBUG(this->router_debug_, " Better cost to node %d: %g (was %g)\n", inode, new_total_cost, cheapest_paths[inode].total_cost); + // Only the `index` and `prev_edge` fields of `cheapest_paths[inode]` are used after this function returns + cheapest_paths[inode].index = inode; + cheapest_paths[inode].prev_edge = this->rr_node_route_inf_[inode].prev_edge; + } else { + VTR_LOGV_DEBUG(this->router_debug_, " Worse cost to node %d: %g (better %g)\n", inode, new_total_cost, cheapest_paths[inode].total_cost); + } + } + + // Stop measuring path search time + std::chrono::steady_clock::time_point end_time = std::chrono::steady_clock::now(); + this->path_search_cumulative_time += std::chrono::duration_cast(end_time - begin_time); + + return cheapest_paths; +} + +template +void SerialConnectionRouter::timing_driven_expand_cheapest(RRNodeId from_node, + float new_total_cost, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) { + float best_total_cost = this->rr_node_route_inf_[from_node].path_cost; + if (best_total_cost == new_total_cost) { + // Explore from this node, since its total cost is exactly the same as + // the best total cost ever seen for this node. Otherwise, prune this node + // to reduce redundant work (i.e., unnecessary neighbor exploration). + // `new_total_cost` is used here as an identifier to detect if the pair + // (from_node or inode, new_total_cost) was the most recently pushed + // element for the corresponding node. + // + // Note: For RCV, it often isn't searching for a shortest path; it is + // searching for a path in the target delay range. So it might find a + // path to node n that has a higher `backward_path_cost` but the `total_cost` + // (including expected delay to sink, going through a cost function that + // checks that against the target delay) might be lower than the previously + // stored value. In that case we want to re-expand the node so long as + // it doesn't create a loop. That `this->rcv_path_manager` should store enough + // info for us to avoid loops. + RTExploredNode current; + current.index = from_node; + current.backward_path_cost = this->rr_node_route_inf_[from_node].backward_path_cost; + current.prev_edge = this->rr_node_route_inf_[from_node].prev_edge; + current.R_upstream = this->rr_node_route_inf_[from_node].R_upstream; + + VTR_LOGV_DEBUG(this->router_debug_, " Better cost to %d\n", from_node); + VTR_LOGV_DEBUG(this->router_debug_, " New total cost: %g\n", new_total_cost); + VTR_LOGV_DEBUG(this->router_debug_ && (current.prev_edge != RREdgeId::INVALID()), + " Setting path costs for associated node %d (from %d edge %zu)\n", + from_node, + static_cast(this->rr_graph_->edge_src_node(current.prev_edge)), + static_cast(current.prev_edge)); + + timing_driven_expand_neighbours(current, cost_params, bounding_box, target_node, target_bb); + } else { + // Post-heap prune, do not re-explore from the current/new partial path as it + // has worse cost than the best partial path to this node found so far + VTR_LOGV_DEBUG(this->router_debug_, " Worse cost to %d\n", from_node); + VTR_LOGV_DEBUG(this->router_debug_, " Old total cost: %g\n", best_total_cost); + VTR_LOGV_DEBUG(this->router_debug_, " New total cost: %g\n", new_total_cost); + } +} + +template +void SerialConnectionRouter::timing_driven_expand_neighbours(const RTExploredNode& current, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb) { + /* Puts all the rr_nodes adjacent to current on the heap. */ + + // For each node associated with the current heap element, expand all of it's neighbors + auto edges = this->rr_nodes_.edge_range(current.index); + + // This is a simple prefetch that prefetches: + // - RR node data reachable from this node + // - rr switch data to reach those nodes from this node. + // + // This code will be a NOP on compiler targets that do not have a + // builtin to emit prefetch instructions. + // + // This code will be a NOP on CPU targets that lack prefetch instructions. + // All modern x86 and ARM64 platforms provide prefetch instructions. + // + // This code delivers ~6-8% reduction in wallclock time when running Titan + // benchmarks, and was specifically measured against the gsm_switch and + // directrf vtr_reg_weekly running in high effort. + // + // - directrf_stratixiv_arch_timing.blif + // - gsm_switch_stratixiv_arch_timing.blif + // + for (RREdgeId from_edge : edges) { + RRNodeId to_node = this->rr_nodes_.edge_sink_node(from_edge); + this->rr_nodes_.prefetch_node(to_node); + + int switch_idx = this->rr_nodes_.edge_switch(from_edge); + VTR_PREFETCH(&this->rr_switch_inf_[switch_idx], 0, 0); + } + + for (RREdgeId from_edge : edges) { + RRNodeId to_node = this->rr_nodes_.edge_sink_node(from_edge); + timing_driven_expand_neighbour(current, + from_edge, + to_node, + cost_params, + bounding_box, + target_node, + target_bb); + } +} + +template +void SerialConnectionRouter::timing_driven_expand_neighbour(const RTExploredNode& current, + RREdgeId from_edge, + RRNodeId to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb) { + VTR_ASSERT(bounding_box.layer_max < g_vpr_ctx.device().grid.get_num_layers()); + + const RRNodeId& from_node = current.index; + + // BB-pruning + // Disable BB-pruning if RCV is enabled, as this can make it harder for circuits with high negative hold slack to resolve this + // TODO: Only disable pruning if the net has negative hold slack, maybe go off budgets + if (!inside_bb(to_node, bounding_box) + && !this->rcv_path_manager.is_enabled()) { + VTR_LOGV_DEBUG(this->router_debug_, + " Pruned expansion of node %d edge %zu -> %d" + " (to node location %d,%d,%d x %d,%d,%d outside of expanded" + " net bounding box %d,%d,%d x %d,%d,%d)\n", + from_node, size_t(from_edge), size_t(to_node), + this->rr_graph_->node_xlow(to_node), this->rr_graph_->node_ylow(to_node), this->rr_graph_->node_layer(to_node), + this->rr_graph_->node_xhigh(to_node), this->rr_graph_->node_yhigh(to_node), this->rr_graph_->node_layer(to_node), + bounding_box.xmin, bounding_box.ymin, bounding_box.layer_min, + bounding_box.xmax, bounding_box.ymax, bounding_box.layer_max); + return; /* Node is outside (expanded) bounding box. */ + } + + /* Prune away IPINs that lead to blocks other than the target one. Avoids * + * the issue of how to cost them properly so they don't get expanded before * + * more promising routes, but makes route-through (via CLBs) impossible. * + * Change this if you want to investigate route-throughs. */ + if (target_node != RRNodeId::INVALID()) { + e_rr_type to_type = this->rr_graph_->node_type(to_node); + if (to_type == e_rr_type::IPIN) { + // Check if this IPIN leads to the target block + // IPIN's of the target block should be contained within it's bounding box + int to_xlow = this->rr_graph_->node_xlow(to_node); + int to_ylow = this->rr_graph_->node_ylow(to_node); + int to_layer = this->rr_graph_->node_layer(to_node); + int to_xhigh = this->rr_graph_->node_xhigh(to_node); + int to_yhigh = this->rr_graph_->node_yhigh(to_node); + if (to_xlow < target_bb.xmin + || to_ylow < target_bb.ymin + || to_xhigh > target_bb.xmax + || to_yhigh > target_bb.ymax + || to_layer < target_bb.layer_min + || to_layer > target_bb.layer_max) { + VTR_LOGV_DEBUG(this->router_debug_, + " Pruned expansion of node %d edge %zu -> %d" + " (to node is IPIN at %d,%d,%d x %d,%d,%d which does not" + " lead to target block %d,%d,%d x %d,%d,%d)\n", + from_node, size_t(from_edge), size_t(to_node), + to_xlow, to_ylow, to_layer, + to_xhigh, to_yhigh, to_layer, + target_bb.xmin, target_bb.ymin, target_bb.layer_min, + target_bb.xmax, target_bb.ymax, target_bb.layer_max); + return; + } + } + } + + VTR_LOGV_DEBUG(this->router_debug_, " Expanding node %d edge %zu -> %d\n", + from_node, size_t(from_edge), size_t(to_node)); + + // Check if the node exists in the route tree when RCV is enabled + // Other pruning methods have been disabled when RCV is on, so this method is required to prevent "loops" from being created + bool node_exists = false; + if (this->rcv_path_manager.is_enabled()) { + node_exists = this->rcv_path_manager.node_exists_in_tree(this->rcv_path_data[from_node], + to_node); + } + + if (!node_exists || !this->rcv_path_manager.is_enabled()) { + timing_driven_add_to_heap(cost_params, + current, + to_node, + from_edge, + target_node); + } +} + +template +void SerialConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& cost_params, + const RTExploredNode& current, + RRNodeId to_node, + const RREdgeId from_edge, + RRNodeId target_node) { + const auto& device_ctx = g_vpr_ctx.device(); + const RRNodeId& from_node = current.index; + + // Initialize the neighbor RTExploredNode + RTExploredNode next; + next.R_upstream = current.R_upstream; + next.index = to_node; + next.prev_edge = from_edge; + next.total_cost = std::numeric_limits::infinity(); // Not used directly + next.backward_path_cost = current.backward_path_cost; + + // Initialize RCV data struct if needed, otherwise it's set to nullptr + this->rcv_path_manager.alloc_path_struct(next.path_data); + // path_data variables are initialized to current values + if (this->rcv_path_manager.is_enabled() && this->rcv_path_data[from_node]) { + next.path_data->backward_cong = this->rcv_path_data[from_node]->backward_cong; + next.path_data->backward_delay = this->rcv_path_data[from_node]->backward_delay; + } + + this->evaluate_timing_driven_node_costs(&next, cost_params, from_node, target_node); + + float best_total_cost = this->rr_node_route_inf_[to_node].path_cost; + float best_back_cost = this->rr_node_route_inf_[to_node].backward_path_cost; + + float new_total_cost = next.total_cost; + float new_back_cost = next.backward_path_cost; + + // We need to only expand this node if it is a better path. And we need to + // update its `rr_node_route_inf` data as we put it into the heap; there may + // be other (previously explored) paths to this node in the heap already, + // but they will be pruned when we pop those heap nodes later as we'll see + // they have inferior costs to what is in the `rr_node_route_inf` data for + // this node. More details can be found from the FPT'24 parallel connection + // router paper. + // + // When RCV is enabled, prune based on the RCV-specific total path cost (see + // in `compute_node_cost_using_rcv` in `evaluate_timing_driven_node_costs`) + // to allow detours to get better QoR. + if ((!this->rcv_path_manager.is_enabled() && best_back_cost > new_back_cost) || (this->rcv_path_manager.is_enabled() && best_total_cost > new_total_cost)) { + VTR_LOGV_DEBUG(this->router_debug_, " Expanding to node %d (%s)\n", to_node, + describe_rr_node(device_ctx.rr_graph, + device_ctx.grid, + device_ctx.rr_indexed_data, + to_node, + this->is_flat_) + .c_str()); + VTR_LOGV_DEBUG(this->router_debug_, " New Total Cost %g New back Cost %g\n", new_total_cost, new_back_cost); + //Add node to the heap only if the cost via the current partial path is less than the + //best known cost, since there is no reason for the router to expand more expensive paths. + // + //Pre-heap prune to keep the heap small, by not putting paths which are known to be + //sub-optimal (at this point in time) into the heap. + + update_cheapest(next, from_node); + + this->heap_.add_to_heap({new_total_cost, to_node}); + update_serial_router_stats(this->router_stats_, + /*is_push=*/true, + to_node, + this->rr_graph_); + + } else { + VTR_LOGV_DEBUG(this->router_debug_, " Didn't expand to %d (%s)\n", to_node, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to_node, this->is_flat_).c_str()); + VTR_LOGV_DEBUG(this->router_debug_, " Prev Total Cost %g Prev back Cost %g \n", best_total_cost, best_back_cost); + VTR_LOGV_DEBUG(this->router_debug_, " New Total Cost %g New back Cost %g \n", new_total_cost, new_back_cost); + } + + if (this->rcv_path_manager.is_enabled() && next.path_data != nullptr) { + this->rcv_path_manager.free_path_struct(next.path_data); + } +} + +template +void SerialConnectionRouter::add_route_tree_node_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) { + const auto& device_ctx = g_vpr_ctx.device(); + const RRNodeId inode = rt_node.inode; + float backward_path_cost = cost_params.criticality * rt_node.Tdel; + float R_upstream = rt_node.R_upstream; + + /* Don't push to heap if not in bounding box: no-op for serial router, important for parallel router */ + if (!inside_bb(rt_node.inode, net_bb)) + return; + + // After budgets are loaded, calculate delay cost as described by RCV paper + /* R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While + * Repairing Short-Path Violations," in IEEE Transactions on Computer-Aided Design of + * Integrated Circuits and Systems, vol. 27, no. 4, pp. 686-697, April 2008.*/ + // float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); + + if (!this->rcv_path_manager.is_enabled()) { + float expected_cost = this->router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream); + float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); + VTR_LOGV_DEBUG(this->router_debug_, " Adding node %8d to heap from init route tree with cost %g (%s)\n", + inode, + tot_cost, + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, this->is_flat_).c_str()); + + if (tot_cost > this->rr_node_route_inf_[inode].path_cost) { + return; + } + add_to_mod_list(inode); + this->rr_node_route_inf_[inode].path_cost = tot_cost; + this->rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); + this->rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; + this->rr_node_route_inf_[inode].R_upstream = R_upstream; + this->heap_.push_back({tot_cost, inode}); + } else { + float expected_total_cost = this->compute_node_cost_using_rcv(cost_params, inode, target_node, rt_node.Tdel, 0, R_upstream); + + add_to_mod_list(inode); + this->rr_node_route_inf_[inode].path_cost = expected_total_cost; + this->rr_node_route_inf_[inode].prev_edge = RREdgeId::INVALID(); + this->rr_node_route_inf_[inode].backward_path_cost = backward_path_cost; + this->rr_node_route_inf_[inode].R_upstream = R_upstream; + + this->rcv_path_manager.alloc_path_struct(this->rcv_path_data[inode]); + this->rcv_path_data[inode]->backward_delay = rt_node.Tdel; + + this->heap_.push_back({expected_total_cost, inode}); + } + + update_serial_router_stats(this->router_stats_, + /*is_push=*/true, + inode, + this->rr_graph_); + + if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { + this->router_stats_->rt_node_pushes[this->rr_graph_->node_type(inode)]++; + } +} + +std::unique_ptr make_serial_connection_router(e_heap_type heap_type, + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat) { + switch (heap_type) { + case e_heap_type::BINARY_HEAP: + return std::make_unique>( + grid, + router_lookahead, + rr_nodes, + rr_graph, + rr_rc_data, + rr_switch_inf, + rr_node_route_inf, + is_flat); + case e_heap_type::FOUR_ARY_HEAP: + return std::make_unique>( + grid, + router_lookahead, + rr_nodes, + rr_graph, + rr_rc_data, + rr_switch_inf, + rr_node_route_inf, + is_flat); + default: + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Unknown heap_type %d", + heap_type); + } +} + +/** This function is only used for the serial connection router since some + * statistic variables in router_stats are not thread-safe for the parallel + * connection router. To update router_stats (more precisely heap_pushes/pops) + * for parallel connection router, we use the MultiQueue internal statistics + * method instead. */ +inline void update_serial_router_stats(RouterStats* router_stats, + bool is_push, + RRNodeId rr_node_id, + const RRGraphView* rr_graph) { + if (is_push) { + router_stats->heap_pushes++; + } else { + router_stats->heap_pops++; + } + + if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { + auto node_type = rr_graph->node_type(rr_node_id); + VTR_ASSERT(node_type != e_rr_type::NUM_RR_TYPES); + + if (is_inter_cluster_node(*rr_graph, rr_node_id)) { + if (is_push) { + router_stats->inter_cluster_node_pushes++; + router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; + } else { + router_stats->inter_cluster_node_pops++; + router_stats->inter_cluster_node_type_cnt_pops[node_type]++; + } + } else { + if (is_push) { + router_stats->intra_cluster_node_pushes++; + router_stats->intra_cluster_node_type_cnt_pushes[node_type]++; + } else { + router_stats->intra_cluster_node_pops++; + router_stats->intra_cluster_node_type_cnt_pops[node_type]++; + } + } + } +} diff --git a/vpr/src/route/serial_connection_router.h b/vpr/src/route/serial_connection_router.h new file mode 100644 index 00000000000..2cd23f1460e --- /dev/null +++ b/vpr/src/route/serial_connection_router.h @@ -0,0 +1,255 @@ +#ifndef _SERIAL_CONNECTION_ROUTER_H +#define _SERIAL_CONNECTION_ROUTER_H + +#include "connection_router.h" + +#include "d_ary_heap.h" + +/** + * @class SerialConnectionRouter implements the AIR's serial timing-driven connection router + * @details This class routes from some initial set of sources (via the input rt tree) to a + * particular sink using single thread. + */ +template +class SerialConnectionRouter : public ConnectionRouter { + public: + SerialConnectionRouter( + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat) + : ConnectionRouter(grid, router_lookahead, rr_nodes, rr_graph, rr_rc_data, rr_switch_inf, rr_node_route_inf, is_flat) { + } + + ~SerialConnectionRouter() { + VTR_LOG("Serial Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", + std::chrono::duration(this->path_search_cumulative_time).count()); + } + + /** + * @brief Clears the modified list per thread + * @note Should be called after reset_path_costs have been called + */ + void clear_modified_rr_node_info() final { + this->modified_rr_node_inf_.clear(); + } + + /** + * @brief Resets modified data in rr_node_route_inf based on modified_rr_node_inf + */ + void reset_path_costs() final { + // Reset the node info stored in rr_node_route_inf variable + ::reset_path_costs(this->modified_rr_node_inf_); + // Reset the node (RCV-related) info stored inside the connection router + if (this->rcv_path_manager.is_enabled()) { + for (const auto& node : this->modified_rr_node_inf_) { + this->rcv_path_data[node] = nullptr; + } + } + } + + /** + * @brief Enables or disables RCV in connection router + * @note Enabling this will utilize extra path structures, as well as + * the RCV cost function. Ensure route budgets have been calculated + * before enabling this. + * @param enable Whether enabling RCV or not + */ + void set_rcv_enabled(bool enable) final { + this->rcv_path_manager.set_enabled(enable); + if (enable) { + this->rcv_path_data.resize(this->rr_node_route_inf_.size()); + } + } + + /** + * @brief Finds shortest paths from the route tree rooted at rt_root to all sinks available + * @note Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree which + * is spatially close to the sink is added to the heap. + * @note If cost_params.astar_fac is set to 0, this effectively becomes Dijkstra's algorithm with a + * modified exit condition (runs until heap is empty). When using cost_params.astar_fac = 0, for + * efficiency the RouterLookahead used should be the NoOpLookahead. + * @note This routine is currently used only to generate information that may be helpful in debugging + * an architecture. + * @param rt_root RouteTreeNode describing the current routing state + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param router_stats Update router statistics + * @param conn_params Parameters to guide the routing of the given connection + * @return A vector where each element is a reachable sink + */ + vtr::vector timing_driven_find_all_shortest_paths_from_route_tree( + const RouteTreeNode& rt_root, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RouterStats& router_stats, + const ConnectionParameters& conn_params) final; + + protected: + /** + * @brief Marks that data associated with rr_node 'inode' has + * been modified, and needs to be reset in reset_path_costs + */ + inline void add_to_mod_list(RRNodeId inode) { + if (std::isinf(this->rr_node_route_inf_[inode].path_cost)) { + this->modified_rr_node_inf_.push_back(inode); + } + } + + /** + * @brief Updates the route path to the node `cheapest.index` + * via the path from `from_node` via `cheapest.prev_edge` + */ + inline void update_cheapest(RTExploredNode& cheapest, const RRNodeId& from_node) { + const RRNodeId& inode = cheapest.index; + add_to_mod_list(inode); + this->rr_node_route_inf_[inode].prev_edge = cheapest.prev_edge; + this->rr_node_route_inf_[inode].path_cost = cheapest.total_cost; + this->rr_node_route_inf_[inode].backward_path_cost = cheapest.backward_path_cost; + + // Use the already created next path structure pointer when RCV is enabled + if (this->rcv_path_manager.is_enabled()) { + this->rcv_path_manager.move(this->rcv_path_data[inode], cheapest.path_data); + + this->rcv_path_data[inode]->path_rr = this->rcv_path_data[from_node]->path_rr; + this->rcv_path_data[inode]->edge = this->rcv_path_data[from_node]->edge; + this->rcv_path_data[inode]->path_rr.push_back(from_node); + this->rcv_path_data[inode]->edge.push_back(cheapest.prev_edge); + } + } + + /** + * @brief Finds the single shortest path from current heap to the sink node in the RR graph + * @param sink_node Sink node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ + void timing_driven_find_single_shortest_path_from_heap(RRNodeId sink_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb) final; + + /** + * @brief Expands this current node if it is a cheaper path + * @param from_node Current node ID being explored + * @param new_total_cost Identifier popped from the heap to detect if the element (pair) + * (from_node, new_total_cost) was the most recently pushed element for from_node + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ + void timing_driven_expand_cheapest( + RRNodeId from_node, + float new_total_cost, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const t_bb& target_bb); + + /** + * @brief Expands each neighbor of the current node in the wave expansion + * @param current Current node being explored + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_node Target node ID to route to + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ + void timing_driven_expand_neighbours( + const RTExploredNode& current, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb); + + /** + * @brief Conditionally adds to_node to the router heap (via path from current.index via from_edge) + * @note RR nodes outside bounding box specified in bounding_box are not added to the heap. + * @param current Current node being explored + * @param from_edge Edge between the current node and the neighbor node + * @param to_node Neighbor node to be expanded + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @param target_node Target node ID to route to + * @param target_bb Prune IPINs that lead to blocks other than the target block + */ + void timing_driven_expand_neighbour( + const RTExploredNode& current, + RREdgeId from_edge, + RRNodeId to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + RRNodeId target_node, + const t_bb& target_bb); + + /** + * @brief Adds to_node to the heap, and also adds any nodes which are connected by non-configurable edges + * @param cost_params Cost function parameters + * @param current Current node being explored + * @param to_node Neighbor node to be expanded + * @param from_edge Edge between the current node and the neighbor node + * @param target_node Target node ID to route to + */ + void timing_driven_add_to_heap( + const t_conn_cost_params& cost_params, + const RTExploredNode& current, + RRNodeId to_node, + RREdgeId from_edge, + RRNodeId target_node); + + /** + * @brief Unconditionally adds rt_node to the heap + * @note If you want to respect rt_node->re_expand that is the caller's responsibility. + * @todo Consider moving this function into the ConnectionRouter class after checking + * the different prune functions of the serial and parallel connection routers. + * @param rt_node RouteTreeNode to be added to the heap + * @param target_node Target node ID to route to + * @param cost_params Cost function parameters + * @param net_bb Do not push to heap if not in bounding box + */ + void add_route_tree_node_to_heap( + const RouteTreeNode& rt_node, + RRNodeId target_node, + const t_conn_cost_params& cost_params, + const t_bb& net_bb) final; + + /** + * @brief Finds shortest paths from current heap to all nodes in the RR graph + * + * Since there is no single *target* node this uses Dijkstra's algorithm with + * a modified exit condition (runs until heap is empty). + * + * @param cost_params Cost function parameters + * @param bounding_box Keep search confined to this bounding box + * @return A vector where each element contains the shortest route to a specific sink node + */ + vtr::vector timing_driven_find_all_shortest_paths_from_heap( + const t_conn_cost_params& cost_params, + const t_bb& bounding_box) final; + + /** Node IDs of modified nodes in rr_node_route_inf */ + std::vector modified_rr_node_inf_; +}; + +/** Construct a serial connection router that uses the specified heap type. + * This function is not used, but removing it will result in "undefined reference" + * errors since heap type specializations won't get emitted from serial_connection_router.cpp + * without it. + * The alternative is moving all SerialConnectionRouter fn implementations into the header. */ +std::unique_ptr make_serial_connection_router( + e_heap_type heap_type, + const DeviceGrid& grid, + const RouterLookahead& router_lookahead, + const t_rr_graph_storage& rr_nodes, + const RRGraphView* rr_graph, + const std::vector& rr_rc_data, + const vtr::vector& rr_switch_inf, + vtr::vector& rr_node_route_inf, + bool is_flat); + +#endif /* _SERIAL_CONNECTION_ROUTER_H */ diff --git a/vpr/src/server/pathhelper.cpp b/vpr/src/server/pathhelper.cpp index b1f581aa620..aa703f444b0 100644 --- a/vpr/src/server/pathhelper.cpp +++ b/vpr/src/server/pathhelper.cpp @@ -40,12 +40,13 @@ CritPathsResultPtr calc_critical_path(const std::string& report_type, int crit_p auto& timing_ctx = g_vpr_ctx.timing(); auto& atom_ctx = g_vpr_ctx.atom(); const auto& blk_loc_registry = g_vpr_ctx.placement().blk_loc_registry(); + const LogicalModels& models = g_vpr_ctx.device().arch->models; t_analysis_opts analysis_opts; analysis_opts.timing_report_detail = details_level; analysis_opts.timing_report_npaths = crit_path_num; - VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, *routing_delay_calc, is_flat_routing, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), models, *timing_ctx.graph, *routing_delay_calc, is_flat_routing, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index 986339d96a9..cd2de438df8 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -24,8 +24,8 @@ vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node) { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(track_rr_node)) + || (e_rr_type::CHANY == rr_graph.node_type(track_rr_node))); vtr::Point start_coordinator; @@ -50,8 +50,8 @@ vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_grap vtr::Point get_track_rr_node_end_coordinate(const RRGraphView& rr_graph, const RRNodeId& track_rr_node) { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(track_rr_node)) + || (e_rr_type::CHANY == rr_graph.node_type(track_rr_node))); vtr::Point end_coordinator; @@ -141,7 +141,7 @@ std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphVi bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, const RRNodeId& node) { /* We only accept OPIN */ - VTR_ASSERT(OPIN == rr_graph.node_type(node)); + VTR_ASSERT(e_rr_type::OPIN == rr_graph.node_type(node)); if (1 != rr_graph.node_out_edges(node).size()) { return false; @@ -150,7 +150,7 @@ bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, VTR_ASSERT(1 == rr_graph.node_out_edges(node).size()); for (auto edge : rr_graph.node_out_edges(node)) { const RRNodeId& sink_node = rr_graph.edge_sink_node(node, edge); - if (IPIN != rr_graph.node_type(sink_node)) { + if (e_rr_type::IPIN != rr_graph.node_type(sink_node)) { return false; } } @@ -167,7 +167,7 @@ bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, const RRNodeId& node) { /* We only accept IPIN */ - VTR_ASSERT(IPIN == rr_graph.node_type(node)); + VTR_ASSERT(e_rr_type::IPIN == rr_graph.node_type(node)); if (1 != rr_graph.node_in_edges(node).size()) { return false; @@ -176,7 +176,7 @@ bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, VTR_ASSERT(1 == rr_graph.node_in_edges(node).size()); for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { const RRNodeId& src_node = rr_graph.edge_src_node(edge); - if (OPIN != rr_graph.node_type(src_node)) { + if (e_rr_type::OPIN != rr_graph.node_type(src_node)) { return false; } } diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp index c6a991ea524..99bad8645ef 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.cpp +++ b/vpr/src/tileable_rr_graph/rr_chan.cpp @@ -10,7 +10,7 @@ ***********************************************************************/ /* default constructor */ RRChan::RRChan() { - type_ = NUM_RR_TYPES; + type_ = e_rr_type::NUM_RR_TYPES; nodes_.resize(0); node_segments_.resize(0); } @@ -18,7 +18,7 @@ RRChan::RRChan() { /************************************************************************ * Accessors ***********************************************************************/ -t_rr_type RRChan::get_type() const { +e_rr_type RRChan::get_type() const { return type_; } @@ -124,7 +124,7 @@ void RRChan::set(const RRChan& rr_chan) { } /* modify type */ -void RRChan::set_type(const t_rr_type& type) { +void RRChan::set_type(const e_rr_type& type) { VTR_ASSERT(valid_type(type)); type_ = type; } @@ -141,7 +141,7 @@ void RRChan::add_node(const RRGraphView& rr_graph, const RRNodeId& node, const R nodes_.push_back(node); node_segments_.push_back(node_segment); - if (NUM_RR_TYPES == type_) { + if (e_rr_type::NUM_RR_TYPES == type_) { type_ = rr_graph.node_type(node); } else { VTR_ASSERT(type_ == rr_graph.node_type(node)); @@ -160,8 +160,8 @@ void RRChan::clear() { * Internal validators ***********************************************************************/ /* for type, only valid type is CHANX and CHANY */ -bool RRChan::valid_type(const t_rr_type& type) const { - if ((CHANX == type) || (CHANY == type)) { +bool RRChan::valid_type(const e_rr_type& type) const { + if ((e_rr_type::CHANX == type) || (e_rr_type::CHANY == type)) { return true; } return false; @@ -170,7 +170,7 @@ bool RRChan::valid_type(const t_rr_type& type) const { /* Check each node, see if the node type is consistent with the type */ bool RRChan::valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const { valid_type(rr_graph.node_type(node)); - if (NUM_RR_TYPES == type_) { + if (e_rr_type::NUM_RR_TYPES == type_) { return true; } valid_type(type_); diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h index 5ba9bc09af5..727c50e5c1b 100644 --- a/vpr/src/tileable_rr_graph/rr_chan.h +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -40,7 +40,7 @@ class RRChan { RRChan(); public: /* Accessors */ - t_rr_type get_type() const; + e_rr_type get_type() const; size_t get_chan_width() const; /* get the number of tracks in this channel */ int get_node_track_id(const RRNodeId& node) const; /* get the track_id of a node */ RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */ @@ -53,7 +53,7 @@ class RRChan { void set(const RRChan&); /* modify the type of routing channel */ - void set_type(const t_rr_type& type); + void set_type(const e_rr_type& type); /* reseve a number of nodes to the array */ void reserve_node(const size_t& node_size); @@ -66,7 +66,7 @@ class RRChan { private: /* internal functions */ /* For the type of a routing channel, only valid type is CHANX and CHANY */ - bool valid_type(const t_rr_type& type) const; + bool valid_type(const e_rr_type& type) const; /* Check each node, see if the node type is consistent with the type of routing channel */ bool valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const; @@ -75,7 +75,7 @@ class RRChan { bool valid_node_id(const size_t& node_id) const; private: /* Internal Data */ - t_rr_type type_; /* channel type: CHANX or CHANY */ + e_rr_type type_; /* channel type: CHANX or CHANY */ std::vector nodes_; /* rr nodes of each track in the channel */ std::vector node_segments_; /* segment of each track */ }; diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 9bd38254b69..c0f8e7d083c 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -509,8 +509,8 @@ short get_track_rr_node_end_track_id(const RRGraph& rr_graph, const RRNodeId& track_rr_node, const vtr::vector>& tileable_rr_graph_node_track_ids) { /* Make sure we have CHANX or CHANY */ - VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) - || (CHANY == rr_graph.node_type(track_rr_node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(track_rr_node)) + || (e_rr_type::CHANY == rr_graph.node_type(track_rr_node))); if (Direction::INC == rr_graph.node_direction(track_rr_node)) { return tileable_rr_graph_node_track_ids[track_rr_node].back(); @@ -525,7 +525,7 @@ short get_track_rr_node_end_track_id(const RRGraph& rr_graph, * in a routing resource graph ************************************************************************/ short find_rr_graph_num_nodes(const RRGraph& rr_graph, - const std::vector& node_types) { + const std::vector& node_types) { short counter = 0; for (const RRNodeId& node : rr_graph.nodes()) { @@ -544,7 +544,7 @@ short find_rr_graph_num_nodes(const RRGraph& rr_graph, * in a routing resource graph ************************************************************************/ short find_rr_graph_max_fan_in(const RRGraph& rr_graph, - const std::vector& node_types) { + const std::vector& node_types) { short max_fan_in = 0; for (const RRNodeId& node : rr_graph.nodes()) { @@ -563,7 +563,7 @@ short find_rr_graph_max_fan_in(const RRGraph& rr_graph, * in a routing resource graph ************************************************************************/ short find_rr_graph_min_fan_in(const RRGraph& rr_graph, - const std::vector& node_types) { + const std::vector& node_types) { short min_fan_in = 0; for (const RRNodeId& node : rr_graph.nodes()) { @@ -582,7 +582,7 @@ short find_rr_graph_min_fan_in(const RRGraph& rr_graph, * in a routing resource graph ************************************************************************/ short find_rr_graph_average_fan_in(const RRGraph& rr_graph, - const std::vector& node_types) { + const std::vector& node_types) { /* Get the maximum SB mux size */ size_t sum = 0; size_t counter = 0; @@ -605,9 +605,9 @@ short find_rr_graph_average_fan_in(const RRGraph& rr_graph, ************************************************************************/ void print_rr_graph_mux_stats(const RRGraph& rr_graph) { /* Print MUX size distribution */ - std::vector sb_node_types; - sb_node_types.push_back(CHANX); - sb_node_types.push_back(CHANY); + std::vector sb_node_types; + sb_node_types.push_back(e_rr_type::CHANX); + sb_node_types.push_back(e_rr_type::CHANY); /* Print statistics */ VTR_LOG("------------------------------------------------\n"); @@ -622,7 +622,7 @@ void print_rr_graph_mux_stats(const RRGraph& rr_graph) { VTR_LOG("------------------------------------------------\n"); /* Get the maximum CB mux size */ - std::vector cb_node_types(1, IPIN); + std::vector cb_node_types(1, e_rr_type::IPIN); VTR_LOG("------------------------------------------------\n"); VTR_LOG("Total No. of Connection Block Multiplexer size: %d\n", diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index e1869ed4d4a..2b096e4842b 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -105,16 +105,16 @@ short get_track_rr_node_end_track_id(const RRGraph& rr_graph, const vtr::vector>& tileable_rr_graph_node_track_ids); short find_rr_graph_num_nodes(const RRGraph& rr_graph, - const std::vector& node_types); + const std::vector& node_types); short find_rr_graph_max_fan_in(const RRGraph& rr_graph, - const std::vector& node_types); + const std::vector& node_types); short find_rr_graph_min_fan_in(const RRGraph& rr_graph, - const std::vector& node_types); + const std::vector& node_types); short find_rr_graph_average_fan_in(const RRGraph& rr_graph, - const std::vector& node_types); + const std::vector& node_types); void print_rr_graph_mux_stats(const RRGraph& rr_graph); diff --git a/vpr/src/tileable_rr_graph/rr_graph_types.h b/vpr/src/tileable_rr_graph/rr_graph_types.h index ca97d7d38a9..813752d62ed 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_types.h +++ b/vpr/src/tileable_rr_graph/rr_graph_types.h @@ -28,7 +28,7 @@ constexpr std::array DIRECTION_STRING_WRITE_XML = { * -- i.e., the gate that generates a signal. * * SINK: A dummy node that is a logical input within a block * * -- i.e. the gate that needs a signal. */ -typedef enum e_rr_type : unsigned char { +typedef enum class e_rr_type : unsigned char { SOURCE = 0, SINK, IPIN, @@ -36,10 +36,10 @@ typedef enum e_rr_type : unsigned char { CHANX, CHANY, NUM_RR_TYPES -} t_rr_type; +}; #endif -// constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; +// constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; // constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; #endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 7816e46134c..cbc29f4850e 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -38,11 +38,11 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type, + const e_rr_type& rr_type, const int& ptc) { std::vector indices; - if (rr_type == IPIN || rr_type == OPIN) { + if (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN) { //For pins we need to look at all the sides of the current grid tile for (e_side side : TOTAL_2D_SIDES) { @@ -71,10 +71,10 @@ std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type) { + const e_rr_type& rr_type) { std::vector indices; - VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); + VTR_ASSERT(rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY); for (const RRNodeId& rr_node_index : rr_graph.node_lookup().find_channel_nodes(layer, x, y, rr_type)) { if (rr_node_index != RRNodeId::INVALID()) { @@ -93,12 +93,12 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type, + const e_rr_type& rr_type, const e_side& side, bool include_clock) { std::vector indices; - VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); + VTR_ASSERT(rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN); /* Ensure that (x, y) is a valid location in grids */ if (size_t(x) > device_grid.width() - 1 || size_t(y) > device_grid.height() - 1) { diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.h b/vpr/src/tileable_rr_graph/rr_graph_view_util.h index 4ccb1c614e1..e14fc645910 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.h +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.h @@ -17,21 +17,21 @@ std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type, + const e_rr_type& rr_type, const int& ptc); std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type); + const e_rr_type& rr_type); std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, const DeviceGrid& device_grid, const size_t& layer, const int& x, const int& y, - const t_rr_type& rr_type, + const e_rr_type& rr_type, const e_side& side, bool include_clock = false); diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 58c721a06b1..5e5d98c99c2 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -53,7 +53,7 @@ size_t RRGSB::get_chan_width(const e_side& side) const { } /* Get the number of routing tracks on a side */ -t_rr_type RRGSB::get_chan_type(const e_side& side) const { +e_rr_type RRGSB::get_chan_type(const e_side& side) const { SideManager side_manager(side); VTR_ASSERT(side_manager.validate()); return chan_node_[side_manager.to_size_t()].get_type(); @@ -74,12 +74,12 @@ const RRChan& RRGSB::chan(const e_side& chan_side) const { } /* Get the number of routing tracks of a X/Y-direction CB */ -size_t RRGSB::get_cb_chan_width(const t_rr_type& cb_type) const { +size_t RRGSB::get_cb_chan_width(const e_rr_type& cb_type) const { return get_chan_width(get_cb_chan_side(cb_type)); } /* Get the sides of ipin_nodes belong to the cb */ -std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) const { +std::vector RRGSB::get_cb_ipin_sides(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); std::vector ipin_sides; @@ -88,11 +88,11 @@ std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) cons ipin_sides.clear(); switch (cb_type) { - case CHANX: + case e_rr_type::CHANX: ipin_sides.push_back(TOP); ipin_sides.push_back(BOTTOM); break; - case CHANY: + case e_rr_type::CHANY: ipin_sides.push_back(RIGHT); ipin_sides.push_back(LEFT); break; @@ -105,7 +105,7 @@ std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) cons } /* Get the sides of ipin_nodes belong to the cb */ -std::vector RRGSB::get_cb_opin_sides(const t_rr_type& cb_type) const { +std::vector RRGSB::get_cb_opin_sides(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); std::vector opin_sides; @@ -114,8 +114,8 @@ std::vector RRGSB::get_cb_opin_sides(const t_rr_type& cb_type) cons opin_sides.clear(); switch (cb_type) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: opin_sides.push_back(TOP); opin_sides.push_back(RIGHT); opin_sides.push_back(BOTTOM); @@ -290,7 +290,7 @@ RRNodeId RRGSB::get_opin_node(const e_side& side, const size_t& node_id) const { } /* Get the number of OPIN rr_nodes on a side */ -size_t RRGSB::get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const { +size_t RRGSB::get_num_cb_opin_nodes(const e_rr_type& cb_type, const e_side& side) const { SideManager side_manager(side); VTR_ASSERT(side_manager.validate()); size_t icb_type = get_cb_opin_type_id(cb_type); @@ -298,7 +298,7 @@ size_t RRGSB::get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side } /* get a opin_node at a given side and track_id */ -RRNodeId RRGSB::get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const { +RRNodeId RRGSB::get_cb_opin_node(const e_rr_type& cb_type, const e_side& side, const size_t& node_id) const { SideManager side_manager(side); VTR_ASSERT(side_manager.validate()); @@ -325,7 +325,7 @@ RRNodeId RRGSB::get_medium_node(const size_t& ptc) const { } /* Get the node index of a routing track of a connection block, return -1 if not found */ -int RRGSB::get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const { +int RRGSB::get_cb_chan_node_index(const e_rr_type& cb_type, const RRNodeId& node) const { enum e_side chan_side = get_cb_chan_side(cb_type); return get_chan_node_index(chan_side, node); } @@ -349,8 +349,8 @@ int RRGSB::get_node_index(const RRGraphView& rr_graph, /* Depending on the type of rr_node, we search different arrays */ switch (rr_graph.node_type(node)) { - case CHANX: - case CHANY: + case e_rr_type::CHANX: + case e_rr_type::CHANY: for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { if ((node == chan_node_[size_t(node_side)].get_node(inode)) /* Check if direction meets specification */ @@ -361,7 +361,7 @@ int RRGSB::get_node_index(const RRGraphView& rr_graph, } } break; - case IPIN: + case e_rr_type::IPIN: for (size_t inode = 0; inode < get_num_ipin_nodes(node_side); ++inode) { if (node == ipin_node_[size_t(node_side)][inode]) { cnt++; @@ -370,7 +370,7 @@ int RRGSB::get_node_index(const RRGraphView& rr_graph, } } break; - case OPIN: + case e_rr_type::OPIN: for (size_t inode = 0; inode < get_num_opin_nodes(node_side); ++inode) { if (node == opin_node_[size_t(node_side)][inode]) { cnt++; @@ -433,7 +433,7 @@ bool RRGSB::is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, SideManager side_manager(node_side); int index; - VTR_ASSERT((CHANX == rr_graph.node_type(node)) || (CHANY == rr_graph.node_type(node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(node)) || (e_rr_type::CHANY == rr_graph.node_type(node))); /* See if we can find the same src_rr_node in the opposite chan_side * if there is one, it means a shorted wire across the SB @@ -490,7 +490,7 @@ bool RRGSB::is_chan_node(const RRNodeId& node) const { } /* check if the CB exist in this GSB */ -bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const { +bool RRGSB::is_cb_exist(const e_rr_type& cb_type) const { /* if channel width is zero, there is no CB */ return (0 != get_cb_chan_width(cb_type)); } @@ -656,22 +656,22 @@ vtr::Point RRGSB::get_sb_coordinate() const { } /* get the x coordinate of this X/Y-direction block */ -size_t RRGSB::get_cb_x(const t_rr_type& cb_type) const { +size_t RRGSB::get_cb_x(const e_rr_type& cb_type) const { return get_cb_coordinate(cb_type).x(); } /* get the y coordinate of this X/Y-direction block */ -size_t RRGSB::get_cb_y(const t_rr_type& cb_type) const { +size_t RRGSB::get_cb_y(const e_rr_type& cb_type) const { return get_cb_coordinate(cb_type).y(); } /* Get the coordinate of the X/Y-direction CB */ -vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { +vtr::Point RRGSB::get_cb_coordinate(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); switch (cb_type) { - case CHANX: + case e_rr_type::CHANX: return coordinate_; - case CHANY: + case e_rr_type::CHANY: return coordinate_; default: VTR_LOG("Invalid type of connection block!\n"); @@ -679,12 +679,12 @@ vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { } } -e_side RRGSB::get_cb_chan_side(const t_rr_type& cb_type) const { +e_side RRGSB::get_cb_chan_side(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); switch (cb_type) { - case CHANX: + case e_rr_type::CHANX: return LEFT; - case CHANY: + case e_rr_type::CHANY: return BOTTOM; default: VTR_LOG("Invalid type of connection block!\n"); @@ -884,11 +884,11 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, VTR_ASSERT(NUM_2D_SIDES != side); VTR_ASSERT(OPEN != index); - if (OPIN == rr_graph.node_type(src_node)) { + if (e_rr_type::OPIN == rr_graph.node_type(src_node)) { from_grid_edge_map[side][index] = edge; } else { - VTR_ASSERT((CHANX == rr_graph.node_type(src_node)) - || (CHANY == rr_graph.node_type(src_node))); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(src_node)) + || (e_rr_type::CHANY == rr_graph.node_type(src_node))); from_track_edge_map[side][index] = edge; } @@ -964,7 +964,8 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ - if (CHANX != rr_graph.node_type(src_node) && CHANY != rr_graph.node_type(src_node)) { + if ((e_rr_type::CHANX != rr_graph.node_type(src_node)) + && (e_rr_type::CHANY != rr_graph.node_type(src_node))) { continue; } /* The driver routing channel node can be either an input or an output to the GSB. @@ -998,7 +999,8 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, VTR_ASSERT(OPEN != index); - VTR_ASSERT(CHANX == rr_graph.node_type(src_node) || CHANY == rr_graph.node_type(src_node)); + VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(src_node)) + || (e_rr_type::CHANY == rr_graph.node_type(src_node))); from_track_edge_map[index] = edge; edge_counter++; } @@ -1007,7 +1009,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, /* We care the source node of this edge, and it should be an input of the GSB!!! */ const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ - if (OPIN != rr_graph.node_type(src_node)) { + if (e_rr_type::OPIN != rr_graph.node_type(src_node)) { continue; } enum e_side cb_opin_side = NUM_2D_SIDES; @@ -1061,7 +1063,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ ipin_node_in_edges_.resize(get_num_sides()); - for (t_rr_type cb_type : {CHANX, CHANY}) { + for (e_rr_type cb_type : {e_rr_type::CHANX, e_rr_type::CHANY}) { for (e_side ipin_side : get_cb_ipin_sides(cb_type)) { SideManager side_manager(ipin_side); ipin_node_in_edges_[size_t(ipin_side)].resize(ipin_node_[size_t(ipin_side)].size()); @@ -1073,8 +1075,8 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { } void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { - for (t_rr_type cb_type : {CHANX, CHANY}) { - size_t icb_type = cb_type == CHANX ? 0 : 1; + for (e_rr_type cb_type : {e_rr_type::CHANX, e_rr_type::CHANY}) { + size_t icb_type = cb_type == e_rr_type::CHANX ? 0 : 1; std::vector cb_ipin_sides = get_cb_ipin_sides(cb_type); for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { enum e_side cb_ipin_side = cb_ipin_sides[iside]; @@ -1084,7 +1086,7 @@ void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); for (const RREdgeId curr_edge : driver_rr_edges) { RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); - if (OPIN != rr_graph.node_type(cand_node)) { + if (e_rr_type::OPIN != rr_graph.node_type(cand_node)) { continue; } enum e_side cb_opin_side = NUM_2D_SIDES; @@ -1224,7 +1226,7 @@ bool RRGSB::validate_opin_node_id(const e_side& side, const size_t& node_id) con } /* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ -bool RRGSB::validate_cb_opin_node_id(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const { +bool RRGSB::validate_cb_opin_node_id(const e_rr_type& cb_type, const e_side& side, const size_t& node_id) const { if (false == validate_side(side)) { return false; } @@ -1240,11 +1242,11 @@ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) con return (node_id < ipin_node_[size_t(side)].size()); } -bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { - return ((CHANX == cb_type) || (CHANY == cb_type)); +bool RRGSB::validate_cb_type(const e_rr_type& cb_type) const { + return ((e_rr_type::CHANX == cb_type) || (e_rr_type::CHANY == cb_type)); } -size_t RRGSB::get_cb_opin_type_id(const t_rr_type& cb_type) const { +size_t RRGSB::get_cb_opin_type_id(const e_rr_type& cb_type) const { VTR_ASSERT(validate_cb_type(cb_type)); - return cb_type == CHANX ? 0 : 1; + return cb_type == e_rr_type::CHANX ? 0 : 1; } diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 30d8e80372b..c9e49f90609 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -59,21 +59,21 @@ class RRGSB { size_t get_chan_width(const e_side& side) const; /* Get the type of routing tracks on a side */ - t_rr_type get_chan_type(const e_side& side) const; + e_rr_type get_chan_type(const e_side& side) const; /* Get the maximum number of routing tracks on all sides */ size_t get_max_chan_width() const; /* Get the number of routing tracks of a X/Y-direction CB */ - size_t get_cb_chan_width(const t_rr_type& cb_type) const; + size_t get_cb_chan_width(const e_rr_type& cb_type) const; /* Return read-only object of the routing channels with a given side */ const RRChan& chan(const e_side& chan_side) const; /* Get the sides of CB ipins in the array */ - std::vector get_cb_ipin_sides(const t_rr_type& cb_type) const; + std::vector get_cb_ipin_sides(const e_rr_type& cb_type) const; /* Get the sides of CB opins in the array, OPINs can only be at the same sides of IPINs. Differently, they are inputs to a connection block */ - std::vector get_cb_opin_sides(const t_rr_type& cb_type) const; + std::vector get_cb_opin_sides(const e_rr_type& cb_type) const; /* Get the direction of a rr_node at a given side and track_id */ enum PORTS get_chan_node_direction(const e_side& side, const size_t& track_id) const; @@ -110,12 +110,12 @@ class RRGSB { /* Get the number of OPIN rr_nodes on a side */ size_t get_num_opin_nodes(const e_side& side) const; /* Get the number of OPIN rr_nodes on a side of a connection block */ - size_t get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const; + size_t get_num_cb_opin_nodes(const e_rr_type& cb_type, const e_side& side) const; /* get a rr_node at a given side and track_id */ RRNodeId get_opin_node(const e_side& side, const size_t& node_id) const; /* get a rr_node at a given side and track_id for a connection block */ - RRNodeId get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + RRNodeId get_cb_opin_node(const e_rr_type& cb_type, const e_side& side, const size_t& node_id) const; /* Get the number of MEDIUM rr_nodes */ size_t get_num_medium_nodes() const; @@ -123,7 +123,7 @@ class RRGSB { /* get a rr_node at a given ptc number */ RRNodeId get_medium_node(const size_t& ptc) const; - int get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const; + int get_cb_chan_node_index(const e_rr_type& cb_type, const RRNodeId& node) const; int get_chan_node_index(const e_side& node_side, const RRNodeId& node) const; @@ -143,7 +143,7 @@ class RRGSB { public: /* Accessors: to identify mirrors */ /* check if the connect block exists in the GSB */ - bool is_cb_exist(const t_rr_type& cb_type) const; + bool is_cb_exist(const e_rr_type& cb_type) const; /* check if the switch block exists in the GSB, this function checks if a switch block physically exists (no routing wires, no OPIN nodes, and no interconnecting wires) */ bool is_sb_exist(const RRGraphView& rr_graph) const; @@ -162,10 +162,10 @@ class RRGSB { size_t get_sb_x() const; /* get the x coordinate of this switch block */ size_t get_sb_y() const; /* get the y coordinate of this switch block */ vtr::Point get_sb_coordinate() const; /* Get the coordinate of the SB */ - size_t get_cb_x(const t_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */ - size_t get_cb_y(const t_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */ - vtr::Point get_cb_coordinate(const t_rr_type& cb_type) const; /* Get the coordinate of the X/Y-direction CB */ - e_side get_cb_chan_side(const t_rr_type& cb_type) const; /* get the side of a Connection block */ + size_t get_cb_x(const e_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */ + size_t get_cb_y(const e_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */ + vtr::Point get_cb_coordinate(const e_rr_type& cb_type) const; /* Get the coordinate of the X/Y-direction CB */ + e_side get_cb_chan_side(const e_rr_type& cb_type) const; /* get the side of a Connection block */ e_side get_cb_chan_side(const e_side& ipin_side) const; /* get the side of a Connection block */ vtr::Point get_side_block_coordinate(const e_side& side) const; vtr::Point get_grid_coordinate() const; @@ -240,11 +240,11 @@ class RRGSB { bool validate_num_sides() const; bool validate_side(const e_side& side) const; bool validate_track_id(const e_side& side, const size_t& track_id) const; - bool validate_cb_opin_node_id(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + bool validate_cb_opin_node_id(const e_rr_type& cb_type, const e_side& side, const size_t& node_id) const; bool validate_opin_node_id(const e_side& side, const size_t& node_id) const; bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const; - bool validate_cb_type(const t_rr_type& cb_type) const; - size_t get_cb_opin_type_id(const t_rr_type& cb_type) const; + bool validate_cb_type(const e_rr_type& cb_type) const; + size_t get_cb_opin_type_id(const e_rr_type& cb_type) const; private: /* Internal Data */ /* Coordinator */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 4b32fcab7cf..94d2c0dfd9a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -28,7 +28,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, size_t edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non OPIN nodes */ - if (OPIN != rr_graph.node_type(node)) { + if (e_rr_type::OPIN != rr_graph.node_type(node)) { continue; } /* Now, we have an OPIN node, we get the source node index */ @@ -41,7 +41,7 @@ void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, RRNodeId src_node = rr_graph.node_lookup().find_node(layer, xlow - grids.get_width_offset(tile_loc), ylow - grids.get_height_offset(tile_loc), - SOURCE, src_node_class_num); + e_rr_type::SOURCE, src_node_class_num); VTR_ASSERT(true == rr_graph.valid_node(src_node)); /* add edges to the src_node */ @@ -66,7 +66,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, size_t edge_count = 0; for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass all the non IPIN nodes */ - if (IPIN != rr_graph.node_type(node)) { + if (e_rr_type::IPIN != rr_graph.node_type(node)) { continue; } /* Now, we have an OPIN node, we get the source node index */ @@ -79,7 +79,7 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, const RRNodeId& sink_node = rr_graph.node_lookup().find_node(layer, xlow - grids.get_width_offset(tile_loc), ylow - grids.get_height_offset(tile_loc), - SINK, sink_node_class_num, TOTAL_2D_SIDES[0]); + e_rr_type::SINK, sink_node_class_num, TOTAL_2D_SIDES[0]); VTR_ASSERT(true == rr_graph.valid_node(sink_node)); /* add edges to connect the IPIN node to SINK nodes */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index c76320b29c3..410eb3ec0e0 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -578,10 +578,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, - CHANY); + e_rr_type::CHANY); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) == CHANY); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANY); Direction direction = rr_graph.node_direction(inode); size_t xlow = rr_graph.node_xlow(inode); size_t ylow = rr_graph.node_ylow(inode); @@ -614,10 +614,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), - CHANX); + e_rr_type::CHANX); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) == CHANX); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANX); Direction direction = rr_graph.node_direction(inode); size_t xlow = rr_graph.node_xlow(inode); size_t ylow = rr_graph.node_ylow(inode); @@ -649,10 +649,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y(), - CHANY); + e_rr_type::CHANY); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) == CHANY); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANY); Direction direction = rr_graph.node_direction(inode); size_t xhigh = rr_graph.node_xhigh(inode); size_t yhigh = rr_graph.node_yhigh(inode); @@ -684,10 +684,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y(), - CHANX); + e_rr_type::CHANX); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) == CHANX); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANX); Direction direction = rr_graph.node_direction(inode); size_t xhigh = rr_graph.node_xhigh(inode); size_t yhigh = rr_graph.node_yhigh(inode); @@ -770,7 +770,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, /* Build a RRChan Object with the given channel type and coorindators */ static RRChan build_one_tileable_rr_chan(const size_t& layer, const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, + const e_rr_type& chan_type, const RRGraphView& rr_graph, const ChanNodeDetails& chan_details) { std::vector chan_rr_nodes; @@ -900,7 +900,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Routing channels*/ /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANY, rr_graph, chany_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, e_rr_type::CHANY, rr_graph, chany_details); chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ @@ -914,11 +914,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* Include Grid[x][y+1] RIGHT side outputs pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); + e_rr_type::OPIN, opin_grid_side[0]); /* Include Grid[x+1][y+1] Left side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, - OPIN, opin_grid_side[1]); + e_rr_type::OPIN, opin_grid_side[1]); break; case RIGHT: /* RIGHT = 1 */ @@ -931,7 +931,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANX, rr_graph, chanx_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, e_rr_type::CHANX, rr_graph, chanx_details); chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ @@ -945,11 +945,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* include Grid[x+1][y+1] Bottom side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); + e_rr_type::OPIN, opin_grid_side[0]); /* include Grid[x+1][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), - OPIN, opin_grid_side[1]); + e_rr_type::OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ if (!perimeter_cb && gsb_coordinate.y() == 0) { @@ -960,7 +960,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANY, rr_graph, chany_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, e_rr_type::CHANY, rr_graph, chany_details); chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ @@ -974,11 +974,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* include Grid[x+1][y] Left side output pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), - OPIN, opin_grid_side[0]); + e_rr_type::OPIN, opin_grid_side[0]); /* include Grid[x][y] Right side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x(), gsb_coordinate.y(), - OPIN, opin_grid_side[1]); + e_rr_type::OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ if (!perimeter_cb && gsb_coordinate.x() == 0) { @@ -989,7 +989,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ /* Collect rr_nodes for Tracks for left: chanx[x][y] */ /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANX, rr_graph, chanx_details); + rr_chan = build_one_tileable_rr_chan(layer, coordinate, e_rr_type::CHANX, rr_graph, chanx_details); chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ @@ -1002,11 +1002,11 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, /* include Grid[x][y+1] Bottom side outputs pins */ temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, - OPIN, opin_grid_side[0]); + e_rr_type::OPIN, opin_grid_side[0]); /* include Grid[x][y] Top side output pins */ temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, layer, gsb_coordinate.x(), gsb_coordinate.y(), - OPIN, opin_grid_side[1]); + e_rr_type::OPIN, opin_grid_side[1]); break; default: @@ -1135,7 +1135,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, } /* Collect IPIN rr_nodes*/ temp_ipin_rr_nodes = find_rr_graph_grid_nodes(rr_graph, grids, - layer, ix, iy, IPIN, ipin_rr_node_grid_side); + layer, ix, iy, e_rr_type::IPIN, ipin_rr_node_grid_side); /* Fill the ipin nodes of RRGSB */ for (const RRNodeId& inode : temp_ipin_rr_nodes) { rr_gsb.add_ipin_node(inode, side_manager.get_side()); @@ -1145,27 +1145,27 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, } /* Find all MEDIUM rr_nodes */ - std::vector medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y(), MEDIUM); + std::vector medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y(), e_rr_type::MEDIUM); for (auto medium_rr_node : medium_rr_nodes) { rr_gsb.add_medium_node(medium_rr_node); } /* For TOP and RIGHT borders, we need to add extra medium nodes. */ if (gsb_coordinate.y() == grids.height() - 2) { - std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, MEDIUM); + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, e_rr_type::MEDIUM); for (auto medium_rr_node : extra_medium_rr_nodes) { rr_gsb.add_medium_node(medium_rr_node); } } if (gsb_coordinate.x() == grids.width() - 2) { - std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), MEDIUM); + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), e_rr_type::MEDIUM); for (auto medium_rr_node : extra_medium_rr_nodes) { rr_gsb.add_medium_node(medium_rr_node); } } if ((gsb_coordinate.x() == grids.width() - 2) && (gsb_coordinate.y() == grids.height() - 2)) { - std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, MEDIUM); + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, e_rr_type::MEDIUM); for (auto medium_rr_node : extra_medium_rr_nodes) { rr_gsb.add_medium_node(medium_rr_node); } @@ -1211,8 +1211,8 @@ void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, /* For TRACKs to IPINs, we only care LEFT and TOP sides * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs */ - if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) - || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { + if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(e_rr_type::CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(e_rr_type::CHANY))) { /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); @@ -1272,8 +1272,8 @@ void build_edges_for_one_tileable_rr_gsb_vib(RRGraphBuilder& rr_graph_builder, /* For TRACKs to IPINs, we only care LEFT and TOP sides * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs */ - if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) - || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { + if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(e_rr_type::CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(e_rr_type::CHANY))) { /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); @@ -1771,11 +1771,11 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, RRNodeId opin_node_id = rr_graph.node_lookup().find_node(layer, from_grid_coordinate.x() - from_grid_width_ofs, from_grid_coordinate.y() - from_grid_height_ofs, - OPIN, opin, opin_grid_side[0]); + e_rr_type::OPIN, opin, opin_grid_side[0]); RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(layer, to_grid_coordinate.x() - to_grid_width_ofs, to_grid_coordinate.y() - to_grid_height_ofs, - IPIN, ipin, ipin_grid_side[0]); + e_rr_type::IPIN, ipin, ipin_grid_side[0]); /* add edges to the opin_node */ VTR_ASSERT(opin_node_id && ipin_node_id); @@ -1806,7 +1806,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, const std::vector first_stages = vib->get_first_stages(); for (size_t i_first_stage = 0; i_first_stage < first_stages.size(); i_first_stage++) { std::vector froms = first_stages[i_first_stage].froms; - RRNodeId to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, i_first_stage); + RRNodeId to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::MEDIUM, i_first_stage); VTR_ASSERT(to_node.is_valid()); VTR_ASSERT(rr_gsb.is_medium_node(to_node)); for (auto from : froms) { @@ -1820,7 +1820,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } for (e_side side : TOTAL_2D_SIDES) { - from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::OPIN, from.phy_pin_index, side); if (from_node.is_valid()) break; } @@ -1885,7 +1885,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } else if (from.from_type == MUX) { size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); - from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::MEDIUM, from_mux_index); if (!rr_gsb.is_medium_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); @@ -1928,7 +1928,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } for (e_side side : TOTAL_2D_SIDES) { - to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), IPIN, to.phy_pin_index, side); + to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::IPIN, to.phy_pin_index, side); if (to_node.is_valid()) break; } @@ -2015,7 +2015,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } for (e_side side : TOTAL_2D_SIDES) { - from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::OPIN, from.phy_pin_index, side); if (from_node.is_valid()) break; } @@ -2080,7 +2080,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } else if (from.from_type == MUX) { size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); - from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), e_rr_type::MEDIUM, from_mux_index); if (!rr_gsb.is_medium_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 5b48ec0f2e6..887b876defd 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -27,7 +27,7 @@ ***********************************************************************/ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, const size_t& layer, - const t_rr_type& node_type, + const e_rr_type& node_type, const bool& perimeter_cb) { size_t num_grid_rr_nodes = 0; @@ -55,19 +55,19 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, } switch (node_type) { - case OPIN: + case e_rr_type::OPIN: /* get the number of OPINs */ num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, DRIVER, io_side); break; - case IPIN: + case e_rr_type::IPIN: /* get the number of IPINs */ num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, RECEIVER, io_side); break; - case SOURCE: + case e_rr_type::SOURCE: /* SOURCE: number of classes whose type is DRIVER */ num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, DRIVER); break; - case SINK: + case e_rr_type::SINK: /* SINK: number of classes whose type is RECEIVER */ num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, RECEIVER); break; @@ -363,32 +363,32 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, /************************************************************************ * Estimate the number of nodes by each type in a routing resource graph ***********************************************************************/ -static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, - const VibDeviceGrid& vib_grid, - const size_t& layer, - const vtr::Point& chan_width, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - const DeviceGridAnnotation& device_grid_annotation, - const bool& shrink_boundary, - const bool& perimeter_cb, - const bool& through_channel) { +static vtr::vector estimate_num_rr_nodes(const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ - std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); + vtr::vector num_rr_nodes_per_type(static_cast(e_rr_type::NUM_RR_TYPES), 0); /** * 1 Find number of rr nodes related to grids */ if (!vib_grid.is_empty()) - num_rr_nodes_per_type[MEDIUM] = estimate_num_medium_rr_nodes(grids, vib_grid, layer); + num_rr_nodes_per_type[e_rr_type::MEDIUM] = estimate_num_medium_rr_nodes(grids, vib_grid, layer); else - num_rr_nodes_per_type[MEDIUM] = 0; + num_rr_nodes_per_type[e_rr_type::MEDIUM] = 0; - num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, OPIN, perimeter_cb); - num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN, perimeter_cb); - num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE, perimeter_cb); - num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK, perimeter_cb); + num_rr_nodes_per_type[e_rr_type::OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, e_rr_type::OPIN, perimeter_cb); + num_rr_nodes_per_type[e_rr_type::IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, e_rr_type::IPIN, perimeter_cb); + num_rr_nodes_per_type[e_rr_type::SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, e_rr_type::SOURCE, perimeter_cb); + num_rr_nodes_per_type[e_rr_type::SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, e_rr_type::SINK, perimeter_cb); /** * 2. Assign the segments for each routing channel, @@ -405,20 +405,20 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, * in X-direction and Y-direction channels!!! * So we will load segment details for different channels */ - num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, layer, - chan_width.x(), - segment_inf_x, - device_grid_annotation, - shrink_boundary, - perimeter_cb, - through_channel); - num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, layer, - chan_width.y(), - segment_inf_y, - device_grid_annotation, - shrink_boundary, - perimeter_cb, - through_channel); + num_rr_nodes_per_type[e_rr_type::CHANX] = estimate_num_chanx_rr_nodes(grids, layer, + chan_width.x(), + segment_inf_x, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); + num_rr_nodes_per_type[e_rr_type::CHANY] = estimate_num_chany_rr_nodes(grids, layer, + chan_width.y(), + segment_inf_y, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); return num_rr_nodes_per_type; } @@ -444,16 +444,16 @@ void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, const bool& through_channel) { VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); - std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, - vib_grid, - layer, - chan_width, - segment_inf_x, - segment_inf_y, - device_grid_annotation, - shrink_boundary, - perimeter_cb, - through_channel); + vtr::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + vib_grid, + layer, + chan_width, + segment_inf_x, + segment_inf_y, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); /* Reserve the number of node to be memory efficient */ size_t num_nodes = 0; @@ -496,7 +496,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder width, height); for (const int& pin_num : opin_list) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, OPIN, pin_num, side); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, e_rr_type::OPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -553,7 +553,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder std::vector ipin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height); for (const int& pin_num : ipin_list) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, IPIN, pin_num, side); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, e_rr_type::IPIN, pin_num, side); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, @@ -605,7 +605,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build } /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), e_rr_type::SOURCE, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -654,7 +654,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder } /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), e_rr_type::SINK, iclass); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), @@ -692,7 +692,7 @@ static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_build size_t num_medium_nodes = vib->get_first_stages().size(); for (size_t i_medium = 0; i_medium < num_medium_nodes; i_medium++) { /* Create a new node and fill information */ - RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), MEDIUM, i_medium, TOTAL_2D_SIDES[0]); + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), e_rr_type::MEDIUM, i_medium, TOTAL_2D_SIDES[0]); /* node bounding box */ rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), grid_coordinate.y(), @@ -755,8 +755,8 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, int x_tile = ix + width_offset; for (int height_offset = 0; height_offset < grids.get_physical_type(tile_loc)->height; ++height_offset) { int y_tile = iy + height_offset; - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, OPIN, grids.get_physical_type(tile_loc)->num_pins, side); - rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, IPIN, grids.get_physical_type(tile_loc)->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::OPIN, grids.get_physical_type(tile_loc)->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::IPIN, grids.get_physical_type(tile_loc)->num_pins, side); } } } @@ -807,7 +807,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(vib_grid.vib_pbtype_name(layer, ix, iy) == grids.get_physical_type(tile_loc)->name); vtr::Point grid_coordinate(ix, iy); - rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, MEDIUM, vib_grid.num_medium_nodes(layer, ix, iy), TOTAL_2D_SIDES[0]); + rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, e_rr_type::MEDIUM, vib_grid.num_medium_nodes(layer, ix, iy), TOTAL_2D_SIDES[0]); load_one_grid_medium_nodes_basic_info(rr_graph_builder, rr_node_driver_switches, @@ -832,12 +832,12 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_graph_builder.node_lookup().mirror_nodes(0, vtr::Point(root_x, root_y), vtr::Point(x, y), - SOURCE, + e_rr_type::SOURCE, TOTAL_2D_SIDES[0]); rr_graph_builder.node_lookup().mirror_nodes(0, vtr::Point(root_x, root_y), vtr::Point(x, y), - SINK, + e_rr_type::SINK, TOTAL_2D_SIDES[0]); } } @@ -856,7 +856,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, std::vector& rr_rc_data, const size_t& layer, const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, + const e_rr_type& chan_type, ChanNodeDetails& chan_details, const std::vector& segment_infs, const t_unified_to_parallel_seg_index& seg_index_map, @@ -885,7 +885,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, /* assign switch id */ size_t seg_id = chan_details.get_track_segment_id(itrack); - e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + e_parallel_axis wanted_axis = chan_type == e_rr_type::CHANX ? X_AXIS : Y_AXIS; size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); rr_node_driver_switches[node] = RRSwitchId(segment_infs[parallel_seg_id].arch_opin_switch); @@ -932,7 +932,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, } /* Finish node RC attributes */ size_t seg_id = chan_details.get_track_segment_id(itrack); - e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + e_parallel_axis wanted_axis = chan_type == e_rr_type::CHANX ? X_AXIS : Y_AXIS; size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); float node_R = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Rmetal; float node_C = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Cmetal; @@ -1107,7 +1107,7 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_node_driver_switches, rr_node_track_ids, rr_rc_data, - layer, chanx_coord, CHANX, + layer, chanx_coord, e_rr_type::CHANX, chanx_details, segment_infs, segment_index_map, @@ -1248,7 +1248,7 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, rr_node_driver_switches, rr_node_track_ids, rr_rc_data, - layer, chany_coord, CHANY, + layer, chany_coord, e_rr_type::CHANY, chany_details, segment_infs, seg_index_map, @@ -1271,7 +1271,7 @@ static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, // this should call rr_graph_builder to do the job for (const RRNodeId& node : rr_graph.nodes()) { /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ - if (CHANX != rr_graph.node_type(node) && CHANY != rr_graph.node_type(node)) { + if (e_rr_type::CHANX != rr_graph.node_type(node) && e_rr_type::CHANY != rr_graph.node_type(node)) { continue; } /* Reach here, we must have a node of CHANX or CHANY */ @@ -1311,12 +1311,8 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, /* Alloc the lookup table * .. warning: It is mandatory. There are bugs in resize() when called incrementally in RRSpatialLookup. * When comment the following block out, you will see errors */ - for (t_rr_type rr_type : RR_TYPES) { - if (rr_type == CHANX) { - rr_graph_builder.node_lookup().resize_nodes(layer, grids.height(), grids.width(), rr_type, NUM_2D_SIDES); - } else { - rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_2D_SIDES); - } + for (e_rr_type rr_type : RR_TYPES) { + rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_2D_SIDES); } load_grid_nodes_basic_info(rr_graph_builder, @@ -1360,7 +1356,7 @@ void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, /* Update node look-up for CHANX and CHANY nodes */ for (const RRNodeId& rr_node_id : rr_graph.nodes()) { - if (CHANX == rr_graph.node_type(rr_node_id) || CHANY == rr_graph.node_type(rr_node_id)) { + if (e_rr_type::CHANX == rr_graph.node_type(rr_node_id) || e_rr_type::CHANY == rr_graph.node_type(rr_node_id)) { rr_graph_builder.add_track_node_to_lookup(rr_node_id); } } diff --git a/vpr/src/timing/PreClusterDelayCalculator.h b/vpr/src/timing/PreClusterDelayCalculator.h index 069aaa13530..7b7ee903bbb 100644 --- a/vpr/src/timing/PreClusterDelayCalculator.h +++ b/vpr/src/timing/PreClusterDelayCalculator.h @@ -11,17 +11,22 @@ #include "atom_netlist.h" #include "atom_lookup.h" +#include "logic_types.h" #include "physical_types.h" #include "prepack.h" +class LogicalModels; + class PreClusterDelayCalculator : public tatum::DelayCalculator { public: PreClusterDelayCalculator(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, float intercluster_net_delay, const Prepacker& prepacker) noexcept : netlist_(netlist) , netlist_lookup_(netlist_lookup) + , models_(models) , inter_cluster_net_delay_(intercluster_net_delay) , prepacker_(prepacker) { //nop @@ -153,8 +158,8 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { if (!clock_gpin) { AtomBlockId blk = netlist_.pin_block(io_pin); - const t_model* model = netlist_.block_model(blk); - VPR_FATAL_ERROR(VPR_ERROR_TIMING, "Failed to find clock pin associated with pin '%s' (model '%s')", netlist_.pin_name(io_pin).c_str(), model->name); + std::string model_name = models_.get_model(netlist_.block_model(blk)).name; + VPR_FATAL_ERROR(VPR_ERROR_TIMING, "Failed to find clock pin associated with pin '%s' (model '%s')", netlist_.pin_name(io_pin).c_str(), model_name.c_str()); } return clock_gpin; } @@ -162,6 +167,7 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { private: const AtomNetlist& netlist_; const AtomLookup& netlist_lookup_; + const LogicalModels& models_; const float inter_cluster_net_delay_; const Prepacker& prepacker_; }; diff --git a/vpr/src/timing/PreClusterTimingGraphResolver.cpp b/vpr/src/timing/PreClusterTimingGraphResolver.cpp index d1d8c2d8754..665da067646 100644 --- a/vpr/src/timing/PreClusterTimingGraphResolver.cpp +++ b/vpr/src/timing/PreClusterTimingGraphResolver.cpp @@ -5,10 +5,12 @@ PreClusterTimingGraphResolver::PreClusterTimingGraphResolver( const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, const tatum::TimingGraph& timing_graph, const tatum::DelayCalculator& delay_calc) : netlist_(netlist) , netlist_lookup_(netlist_lookup) + , models_(models) , timing_graph_(timing_graph) , delay_calc_(delay_calc) {} @@ -22,7 +24,7 @@ std::string PreClusterTimingGraphResolver::node_type_name(tatum::NodeId node) co AtomPinId pin = netlist_lookup_.tnode_atom_pin(node); AtomBlockId blk = netlist_.pin_block(pin); - std::string name = netlist_.block_model(blk)->name; + std::string name = models_.model_name(netlist_.block_model(blk)); if (detail_level() == e_timing_report_detail::AGGREGATED) { //Annotate primitive grid location, if known @@ -72,7 +74,7 @@ tatum::EdgeDelayBreakdown PreClusterTimingGraphResolver::edge_delay_breakdown(ta //component.inst_name = netlist_.block_name(atom_blk); component.type_name = "primitive '"; - component.type_name += netlist_.block_model(atom_blk)->name; + component.type_name += models_.model_name(netlist_.block_model(atom_blk)); component.type_name += "'"; if (edge_type == tatum::EdgeType::PRIMITIVE_COMBINATIONAL) { diff --git a/vpr/src/timing/PreClusterTimingGraphResolver.h b/vpr/src/timing/PreClusterTimingGraphResolver.h index ce859c1ecd6..6469c4f8b66 100644 --- a/vpr/src/timing/PreClusterTimingGraphResolver.h +++ b/vpr/src/timing/PreClusterTimingGraphResolver.h @@ -6,11 +6,14 @@ #include "atom_lookup.h" #include "AnalysisDelayCalculator.h" +class LogicalModels; + class PreClusterTimingGraphResolver : public tatum::TimingGraphNameResolver { public: PreClusterTimingGraphResolver( const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, const tatum::TimingGraph& timing_graph, const tatum::DelayCalculator& delay_calc); @@ -26,6 +29,7 @@ class PreClusterTimingGraphResolver : public tatum::TimingGraphNameResolver { const AtomNetlist& netlist_; const AtomLookup& netlist_lookup_; + const LogicalModels& models_; const tatum::TimingGraph& timing_graph_; const tatum::DelayCalculator& delay_calc_; e_timing_report_detail detail_level_ = e_timing_report_detail::NETLIST; diff --git a/vpr/src/timing/PreClusterTimingManager.cpp b/vpr/src/timing/PreClusterTimingManager.cpp index 44407d61522..7e9d7a6a0d1 100644 --- a/vpr/src/timing/PreClusterTimingManager.cpp +++ b/vpr/src/timing/PreClusterTimingManager.cpp @@ -78,6 +78,7 @@ PreClusterTimingManager::PreClusterTimingManager(bool timing_driven, // Initialize the timing analyzer clustering_delay_calc_ = std::make_shared(atom_netlist, atom_lookup, + arch.models, inter_cluster_net_delay, prepacker); timing_info_ = make_setup_timing_info(clustering_delay_calc_, timing_update_type); @@ -101,6 +102,7 @@ PreClusterTimingManager::PreClusterTimingManager(bool timing_driven, auto& timing_ctx = g_vpr_ctx.timing(); PreClusterTimingGraphResolver resolver(atom_netlist, atom_lookup, + arch.models, *timing_ctx.graph, *clustering_delay_calc_); resolver.set_detail_level(analysis_opts.timing_report_detail); diff --git a/vpr/src/timing/VprTimingGraphResolver.cpp b/vpr/src/timing/VprTimingGraphResolver.cpp index 791615e5585..d884c3e15ff 100644 --- a/vpr/src/timing/VprTimingGraphResolver.cpp +++ b/vpr/src/timing/VprTimingGraphResolver.cpp @@ -1,15 +1,18 @@ #include "VprTimingGraphResolver.h" #include "atom_netlist.h" #include "atom_lookup.h" +#include "logic_types.h" VprTimingGraphResolver::VprTimingGraphResolver(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, const tatum::TimingGraph& timing_graph, const AnalysisDelayCalculator& delay_calc, bool is_flat, const BlkLocRegistry& blk_loc_registry) : netlist_(netlist) , netlist_lookup_(netlist_lookup) + , models_(models) , timing_graph_(timing_graph) , delay_calc_(delay_calc) , is_flat_(is_flat) @@ -25,7 +28,7 @@ std::string VprTimingGraphResolver::node_type_name(tatum::NodeId node) const { AtomPinId pin = netlist_lookup_.tnode_atom_pin(node); AtomBlockId blk = netlist_.pin_block(pin); - std::string name = netlist_.block_model(blk)->name; + std::string name = models_.model_name(netlist_.block_model(blk)); if (detail_level() == e_timing_report_detail::AGGREGATED || detail_level() == e_timing_report_detail::DETAILED_ROUTING @@ -78,7 +81,7 @@ tatum::EdgeDelayBreakdown VprTimingGraphResolver::edge_delay_breakdown(tatum::Ed //component.inst_name = netlist_.block_name(atom_blk); component.type_name = "primitive '"; - component.type_name += netlist_.block_model(atom_blk)->name; + component.type_name += models_.model_name(netlist_.block_model(atom_blk)); component.type_name += "'"; if (edge_type == tatum::EdgeType::PRIMITIVE_COMBINATIONAL) { @@ -342,11 +345,11 @@ void VprTimingGraphResolver::get_detailed_interconnect_components_helper(std::ve // Process the current interconnect component if it is of type OPIN, CHANX, CHANY, IPIN // Only process SOURCE, SINK in debug report mode auto rr_type = rr_graph.node_type(RRNodeId(current_node->inode)); - if (rr_type == OPIN - || rr_type == IPIN - || rr_type == CHANX - || rr_type == CHANY - || ((rr_type == SOURCE || rr_type == SINK) && (detail_level() == e_timing_report_detail::DEBUG))) { + if (rr_type == e_rr_type::OPIN + || rr_type == e_rr_type::IPIN + || rr_type == e_rr_type::CHANX + || rr_type == e_rr_type::CHANY + || ((rr_type == e_rr_type::SOURCE || rr_type == e_rr_type::SINK) && (detail_level() == e_timing_report_detail::DEBUG))) { tatum::DelayComponent net_component; // declare a new instance of DelayComponent net_component.type_name = rr_graph.node_coordinate_to_string(RRNodeId(current_node->inode)); diff --git a/vpr/src/timing/VprTimingGraphResolver.h b/vpr/src/timing/VprTimingGraphResolver.h index 7bb9eb3ba6a..0f63c3d9370 100644 --- a/vpr/src/timing/VprTimingGraphResolver.h +++ b/vpr/src/timing/VprTimingGraphResolver.h @@ -7,11 +7,13 @@ #include "AnalysisDelayCalculator.h" class BlkLocRegistry; +class LogicalModels; class VprTimingGraphResolver : public tatum::TimingGraphNameResolver { public: VprTimingGraphResolver(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, + const LogicalModels& models, const tatum::TimingGraph& timing_graph, const AnalysisDelayCalculator& delay_calc, bool is_flat, @@ -33,6 +35,7 @@ class VprTimingGraphResolver : public tatum::TimingGraphNameResolver { const AtomNetlist& netlist_; const AtomLookup& netlist_lookup_; + const LogicalModels& models_; const tatum::TimingGraph& timing_graph_; const AnalysisDelayCalculator& delay_calc_; e_timing_report_detail detail_level_ = e_timing_report_detail::NETLIST; diff --git a/vpr/src/timing/read_sdc.cpp b/vpr/src/timing/read_sdc.cpp index e8db27b9a28..02718390946 100644 --- a/vpr/src/timing/read_sdc.cpp +++ b/vpr/src/timing/read_sdc.cpp @@ -19,6 +19,7 @@ void apply_default_timing_constraints(const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingConstraints& timing_constraints); void apply_combinational_default_timing_constraints(const AtomNetlist& netlist, @@ -56,17 +57,19 @@ class SdcParseCallback : public sdcparse::Callback { public: SdcParseCallback(const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingConstraints& timing_constraints, tatum::TimingGraph& tg) : netlist_(netlist) , lookup_(lookup) + , models_(models) , tc_(timing_constraints) , tg_(tg) {} public: //sdcparse::Callback interface //Start of parsing void start_parse() override { - netlist_clock_drivers_ = find_netlist_logical_clock_drivers(netlist_); + netlist_clock_drivers_ = find_netlist_logical_clock_drivers(netlist_, models_); netlist_primary_ios_ = find_netlist_primary_ios(netlist_); } @@ -946,12 +949,11 @@ class SdcParseCallback : public sdcparse::Callback { } } } - - if (!found) { - VTR_LOGF_WARN(fname_.c_str(), lineno_, - "get_clocks target name or pattern '%s' matched no clocks\n", - clock_glob_pattern.c_str()); - } + } + if (!found) { + VTR_LOGF_WARN(fname_.c_str(), lineno_, + "get_clocks target name or pattern '%s' matched no clocks\n", + clock_glob_pattern.c_str()); } } @@ -1036,6 +1038,7 @@ class SdcParseCallback : public sdcparse::Callback { private: const AtomNetlist& netlist_; const AtomLookup& lookup_; + const LogicalModels& models_; tatum::TimingConstraints& tc_; tatum::TimingGraph& tg_; @@ -1060,32 +1063,33 @@ class SdcParseCallback : public sdcparse::Callback { std::unique_ptr read_sdc(const t_timing_inf& timing_inf, const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingGraph& timing_graph) { auto timing_constraints = std::make_unique(); if (!timing_inf.timing_analysis_enabled) { VTR_LOG("\n"); VTR_LOG("Timing analysis off\n"); - apply_default_timing_constraints(netlist, lookup, *timing_constraints); + apply_default_timing_constraints(netlist, lookup, models, *timing_constraints); } else { FILE* sdc_file = fopen(timing_inf.SDCFile.c_str(), "r"); if (sdc_file == nullptr) { //No SDC file VTR_LOG("\n"); VTR_LOG("SDC file '%s' not found\n", timing_inf.SDCFile.c_str()); - apply_default_timing_constraints(netlist, lookup, *timing_constraints); + apply_default_timing_constraints(netlist, lookup, models, *timing_constraints); } else { VTR_ASSERT(sdc_file != nullptr); //Parse the file - SdcParseCallback callback(netlist, lookup, *timing_constraints, timing_graph); + SdcParseCallback callback(netlist, lookup, models, *timing_constraints, timing_graph); sdc_parse_file(sdc_file, callback, timing_inf.SDCFile.c_str()); fclose(sdc_file); if (callback.num_commands() == 0) { VTR_LOG("\n"); VTR_LOG("SDC file '%s' contained no SDC commands\n", timing_inf.SDCFile.c_str()); - apply_default_timing_constraints(netlist, lookup, *timing_constraints); + apply_default_timing_constraints(netlist, lookup, models, *timing_constraints); } else { VTR_LOG("\n"); VTR_LOG("Applied %zu SDC commands from '%s'\n", callback.num_commands(), timing_inf.SDCFile.c_str()); @@ -1119,8 +1123,9 @@ std::unique_ptr read_sdc(const t_timing_inf& timing_in //appropriate to the type of circuit. void apply_default_timing_constraints(const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingConstraints& tc) { - std::set netlist_clock_drivers = find_netlist_logical_clock_drivers(netlist); + std::set netlist_clock_drivers = find_netlist_logical_clock_drivers(netlist, models); if (netlist_clock_drivers.size() == 0) { apply_combinational_default_timing_constraints(netlist, lookup, tc); diff --git a/vpr/src/timing/read_sdc.h b/vpr/src/timing/read_sdc.h index 4e759360f15..bae43206952 100644 --- a/vpr/src/timing/read_sdc.h +++ b/vpr/src/timing/read_sdc.h @@ -9,9 +9,12 @@ #include "atom_lookup_fwd.h" #include "vpr_types.h" +class LogicalModels; + std::unique_ptr read_sdc(const t_timing_inf& timing_inf, const AtomNetlist& netlist, const AtomLookup& lookup, + const LogicalModels& models, tatum::TimingGraph& timing_graph); #endif diff --git a/vpr/src/timing/timing_graph_builder.cpp b/vpr/src/timing/timing_graph_builder.cpp index 78bbbe63ba2..1e183c81289 100644 --- a/vpr/src/timing/timing_graph_builder.cpp +++ b/vpr/src/timing/timing_graph_builder.cpp @@ -218,12 +218,11 @@ */ #include +#include "logic_types.h" #include "vtr_log.h" -#include "vtr_linear_map.h" #include "timing_graph_builder.h" #include "vpr_error.h" -#include "vpr_utils.h" #include "atom_netlist.h" #include "atom_netlist_utils.h" @@ -251,10 +250,11 @@ tatum::util::linear_map remap_valid(const tatum::util::linear_map& d } TimingGraphBuilder::TimingGraphBuilder(const AtomNetlist& netlist, - AtomLookup& netlist_lookup) + AtomLookup& netlist_lookup, + const LogicalModels& models) : netlist_(netlist) , netlist_lookup_(netlist_lookup) - , netlist_clock_drivers_(find_netlist_logical_clock_drivers(netlist_)) { + , netlist_clock_drivers_(find_netlist_logical_clock_drivers(netlist_, models)) { //pass } diff --git a/vpr/src/timing/timing_graph_builder.h b/vpr/src/timing/timing_graph_builder.h index 1f1624eed81..40b571a8bb1 100644 --- a/vpr/src/timing/timing_graph_builder.h +++ b/vpr/src/timing/timing_graph_builder.h @@ -5,6 +5,8 @@ #include "atom_netlist_fwd.h" #include "atom_lookup.h" +class LogicalModels; + /* * Class for constructing a Timing Graph (a tatum::TimingGraph, for use with the Tatum * STA engine) from the provided AtomNetlist. It also updates the provided AtomLookup @@ -19,7 +21,8 @@ class TimingGraphBuilder { public: TimingGraphBuilder(const AtomNetlist& netlist, - AtomLookup& netlist_lookup); + AtomLookup& netlist_lookup, + const LogicalModels& models); std::unique_ptr timing_graph(bool allow_dangling_combinational_nodes); diff --git a/vpr/src/util/lazy_pop_unique_priority_queue.h b/vpr/src/util/lazy_pop_unique_priority_queue.h new file mode 100644 index 00000000000..d375daf19cd --- /dev/null +++ b/vpr/src/util/lazy_pop_unique_priority_queue.h @@ -0,0 +1,216 @@ +/** + * @file + * @author Rongbo Zhang + * @date 2025-04-23 + * @brief This file contains the definition of the LazyPopUniquePriorityQueue class. + * + * The class LazyPopUniquePriorityQueue is a priority queue that allows for lazy deletion of elements. + * The elements are pair of key and sort-value. The key is a unique value to identify the item, and the sort-value is used to sort the item. + * It is implemented using a vector and 2 sets, one set keeps track of the elements in the queue, and the other set keeps track of the elements that are pending deletion, + * so that they can be removed from the queue when they are popped. + * + * Currently, the class supports the following functions: + * LazyPopUniquePriorityQueue::push(): Pushes a key-sort-value (K-SV) pair into the priority queue and adds the key to the tracking set. + * LazyPopUniquePriorityQueue::pop(): Returns the K-SV pair with the highest SV whose key is not pending deletion. + * LazyPopUniquePriorityQueue::remove(): Removes an element from the priority queue immediately. + * LazyPopUniquePriorityQueue::remove_at_pop_time(): Removes an element from the priority queue when it is popped. + * LazyPopUniquePriorityQueue::empty(): Returns whether the queue is empty. + * LazyPopUniquePriorityQueue::clear(): Clears the priority queue vector and the tracking sets. + * LazyPopUniquePriorityQueue::size(): Returns the number of elements in the queue. + * LazyPopUniquePriorityQueue::contains(): Returns true if the key is in the queue, false otherwise. + */ + +#pragma once + +#include +#include +#include + +/** + * @brief Lazy Pop Unique Priority Queue + * + * This is a priority queue that is used to sort items which are identified by the key + * and sorted by the sort value. + * + * It uses a vector to store the key and sort value pair. + * It uses a set to store the keys that are in the vector for uniqueness checking + * and a set to store the delete pending keys which will be removed at pop time. + */ + +template +class LazyPopUniquePriorityQueue { + public: + /** @brief The custom comparsion struct for sorting the items in the priority queue. + * A less than comparison will put the item with the highest sort value to the front of the queue. + * A greater than comparison will put the item with the lowest sort value to the front of the queue. + */ + struct LazyPopUniquePriorityQueueCompare { + bool operator()(const std::pair& a, + const std::pair& b) const { + return a.second < b.second; + } + }; + + /// @brief The vector maintained as heap to store the key and sort value pair. + std::vector> heap; + + /// @brief The set to store the keys that are in the queue. This is used to ensure uniqueness + std::unordered_set content_set; + + /// @brief The set to store the delete pending item from the queue refered by the key. + std::unordered_set delete_pending_set; + + /** + * @brief Push the key and the sort value as a pair into the priority queue. + * + * @param key + * The unique key for the item that will be pushed onto the queue. + * @param value + * The sort value used for sorting the item. + */ + void push(T_key key, T_sort value) { + // Insert the key and sort value pair into the queue if it is not already present + if (content_set.find(key) != content_set.end()) { + // If the key is already in the queue, do nothing + return; + } + // Insert the key and sort value pair into the heap and track the key + // The new item is added to the end of the vector and then the push_heap function is call + // to push the item to the correct position in the heap structure. + heap.emplace_back(key, value); + std::push_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + content_set.insert(key); + } + + /** + * @brief Pop the top item from the priority queue. + * + * @return The key and sort value pair. + */ + std::pair pop() { + std::pair top_pair; + while (heap.size() > 0) { + top_pair = heap.front(); + // Remove the key from the heap and the tracking set. + // The pop_heap function will move the top item in the heap structure to the end of the vector container. + // Then the pop_back function will remove the last item. + std::pop_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + heap.pop_back(); + content_set.erase(top_pair.first); + + // Checking if the key with the highest sort value is in the delete pending set. + // If it is, ignore the current top item and remove the key from the delete pending set. Then get the next top item. + // Otherwise, the top item found, break the loop. + if (delete_pending_set.find(top_pair.first) != delete_pending_set.end()) { + delete_pending_set.erase(top_pair.first); + top_pair = std::pair(); + } else { + break; + } + } + + // If there is zero non-pending-delete item, clear the queue. + if (empty()) { + clear(); + } + + return top_pair; + } + + /** + * @brief Remove the item with matching key value from the priority queue + * This will immediately remove the item and re-heapify the queue. + * + * This function is expensive, as it requires a full re-heapify of the queue. + * The time complexity is O(n log n) for the re-heapify, where n is the size of the queue. + * It is recommended to use remove_at_pop_time() instead. + * @param key + * The key of the item to be delected from the queue. + */ + void remove(T_key key) { + // If the key is in the priority queue, remove it from the heap and reheapify. + // Otherwise, do nothing. + if (content_set.find(key) != content_set.end()) { + content_set.erase(key); + delete_pending_set.erase(key); + for (int i = 0; i < heap.size(); i++) { + if (heap[i].first == key) { + heap.erase(heap.begin() + i); + break; + } + } + + // If this delete caused the queue to have zero non-pending-delete item, clear the queue. + if (empty()) { + clear(); + // Otherwise re-heapify the queue + } else { + std::make_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + } + } + } + + /** + * @brief Remove the item with matching key value from the priority queue at pop time. + * Add the key to the delete pending set for tracking, + * and it will be deleted when it is popped. + * + * This function will not immediately delete the key from the + * priority queue. It will be deleted when it is popped. Thus do not + * expect a size reduction in the priority queue immediately. + * @param key + * The key of the item to be delected from the queue at pop time. + */ + void remove_at_pop_time(T_key key) { + // If the key is in the list, start tracking it in the delete pending list. + // Otherwise, do nothing. + if (content_set.find(key) != content_set.end()) { + delete_pending_set.insert(key); + + // If this marks the last non-pending-delete item as to-be-deleted, clear the queue + if (empty()) { + clear(); + } + } + } + + /** + * @brief Check if the priority queue is empty, i.e. there is zero non-pending-delete item. + * + * @return True if the priority queue is empty, false otherwise. + */ + bool empty() { + return size() == 0; + } + + /** + * @brief Clears the priority queue and the tracking sets. + * + * @return None + */ + void clear() { + heap.clear(); + content_set.clear(); + delete_pending_set.clear(); + } + + /** + * @brief Get the number of non-pending-delete items in the priority queue. + * + * @return The number of non-pending-delete items in the priority queue. + */ + size_t size() { + return heap.size() - delete_pending_set.size(); + } + + /** + * @brief Check if the item referred to the key is in the priority queue. + * + * @param key + * The key of the item. + * @return True if the key is in the priority queue, false otherwise. + */ + bool contains(T_key key) { + return content_set.find(key) != content_set.end(); + } +}; diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index f960f5c8668..bbb57f7c9f1 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -43,38 +43,6 @@ static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::reg /******************** Subroutine definitions *********************************/ -const t_model* find_model(const t_model* models, const std::string& name, bool required) { - for (const t_model* model = models; model != nullptr; model = model->next) { - if (name == model->name) { - return model; - } - } - - if (required) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find architecture modedl '%s'\n", name.c_str()); - } - - return nullptr; -} - -const t_model_ports* find_model_port(const t_model* model, const std::string& name, bool required) { - VTR_ASSERT(model); - - for (const t_model_ports* model_ports : {model->inputs, model->outputs}) { - for (const t_model_ports* port = model_ports; port != nullptr; port = port->next) { - if (port->name == name) { - return port; - } - } - } - - if (required) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find port '%s; on architecture model '%s'\n", name.c_str(), model->name); - } - - return nullptr; -} - /** * print tabs given number of tabs to file */ @@ -91,13 +59,13 @@ std::string rr_node_arch_name(RRNodeId inode, bool is_flat) { auto rr_node = inode; std::string rr_node_arch_name; - if (rr_graph.node_type(inode) == OPIN || rr_graph.node_type(inode) == IPIN) { + if (rr_graph.node_type(inode) == e_rr_type::OPIN || rr_graph.node_type(inode) == e_rr_type::IPIN) { //Pin names auto type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), rr_graph.node_layer(rr_node)}); rr_node_arch_name += block_type_pin_index_to_name(type, rr_graph.node_pin_num(rr_node), is_flat); - } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) { + } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { //Set of pins associated with SOURCE/SINK auto type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), @@ -113,7 +81,7 @@ std::string rr_node_arch_name(RRNodeId inode, bool is_flat) { rr_node_arch_name += pin_names[0]; } } else { - VTR_ASSERT(rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY); + VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::CHANX || rr_graph.node_type(inode) == e_rr_type::CHANY); //Wire segment name auto cost_index = rr_graph.node_cost_index(inode); int seg_index = device_ctx.rr_indexed_data[cost_index].seg_index; @@ -738,7 +706,7 @@ static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::reg if (pb_type->blif_model != nullptr) { //Leaf pb_type - VTR_ASSERT(pb_type->num_modes == 0); + VTR_ASSERT(pb_type->is_primitive()); if (std::regex_match(pb_type->blif_model, blif_model_regex)) { return true; } else { @@ -759,66 +727,6 @@ static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::reg return false; } -int get_max_primitives_in_pb_type(t_pb_type* pb_type) { - int max_size; - if (pb_type->modes == nullptr) { - max_size = 1; - } else { - max_size = 0; - int temp_size = 0; - for (int i = 0; i < pb_type->num_modes; i++) { - for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - temp_size += pb_type->modes[i].pb_type_children[j].num_pb - * get_max_primitives_in_pb_type( - &pb_type->modes[i].pb_type_children[j]); - } - if (temp_size > max_size) { - max_size = temp_size; - } - } - } - return max_size; -} - -/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */ -int get_max_nets_in_pb_type(const t_pb_type* pb_type) { - int max_nets; - if (pb_type->modes == nullptr) { - max_nets = pb_type->num_output_pins; - } else { - max_nets = 0; - for (int i = 0; i < pb_type->num_modes; i++) { - int temp_nets = 0; - for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - temp_nets += pb_type->modes[i].pb_type_children[j].num_pb - * get_max_nets_in_pb_type( - &pb_type->modes[i].pb_type_children[j]); - } - if (temp_nets > max_nets) { - max_nets = temp_nets; - } - } - } - if (pb_type->parent_mode == nullptr) { - max_nets += pb_type->num_input_pins + pb_type->num_output_pins - + pb_type->num_clock_pins; - } - return max_nets; -} - -int get_max_depth_of_pb_type(t_pb_type* pb_type) { - int max_depth = pb_type->depth; - for (int i = 0; i < pb_type->num_modes; i++) { - for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - int temp_depth = get_max_depth_of_pb_type(&pb_type->modes[i].pb_type_children[j]); - if (temp_depth > max_depth) { - max_depth = temp_depth; - } - } - } - return max_depth; -} - /** * given an atom block and physical primitive type, is the mapping legal */ @@ -828,7 +736,7 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t } auto& atom_ctx = g_vpr_ctx.atom(); - if (cur_pb_type->model != atom_ctx.netlist().block_model(blk_id)) { + if (cur_pb_type->model_id != atom_ctx.netlist().block_model(blk_id)) { //Primitive and atom do not match return false; } @@ -985,7 +893,7 @@ const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomPB VTR_ASSERT(pb_gnode); //The graph node and pin/block should agree on the model they represent - VTR_ASSERT(netlist.block_model(blk_id) == pb_gnode->pb_type->model); + VTR_ASSERT(netlist.block_model(blk_id) == pb_gnode->pb_type->model_id); //Get the pin index AtomPortId port_id = netlist.pin_port(pin_id); @@ -1199,7 +1107,7 @@ static void load_pin_id_to_pb_mapping_rec(t_pb* cur_pb, t_pb** pin_id_to_pb_mapp } } - if (pb_type->num_modes == 0 || cur_pb->child_pbs == nullptr) { + if (pb_type->is_primitive() || cur_pb->child_pbs == nullptr) { return; } @@ -1734,20 +1642,20 @@ std::vector get_all_pb_graph_node_primitives(const t_pb_ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, const VibInf* vib, - t_rr_type node_type, + e_rr_type node_type, int node_ptc) { - if (node_type == CHANX || node_type == CHANY) { + if (node_type == e_rr_type::CHANX || node_type == e_rr_type::CHANY) { return true; - } else if (node_type == MEDIUM) { // This function will check all types of nodes. MEDIUM is added for avoiding errors. + } else if (node_type == e_rr_type::MEDIUM) { // This function will check all types of nodes. MEDIUM is added for avoiding errors. VTR_ASSERT(vib != nullptr); return (node_ptc < (int)vib->get_first_stages().size()); } else { - VTR_ASSERT(node_type == IPIN || node_type == OPIN || node_type == SINK || node_type == SOURCE); - if (node_type == IPIN || node_type == OPIN) { + VTR_ASSERT(node_type == e_rr_type::IPIN || node_type == e_rr_type::OPIN || node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE); + if (node_type == e_rr_type::IPIN || node_type == e_rr_type::OPIN) { return is_pin_on_tile(physical_tile, node_ptc); } else { - VTR_ASSERT(node_type == SINK || node_type == SOURCE); + VTR_ASSERT(node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE); return is_class_on_tile(physical_tile, node_ptc); } } @@ -1756,7 +1664,7 @@ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, bool is_inter_cluster_node(const RRGraphView& rr_graph_view, RRNodeId node_id) { auto node_type = rr_graph_view.node_type(node_id); - if (node_type == CHANX || node_type == CHANY) { + if (node_type == e_rr_type::CHANX || node_type == e_rr_type::CHANY || node_type == e_rr_type::MEDIUM) { return true; } else { int x_low = rr_graph_view.node_xlow(node_id); @@ -1764,10 +1672,10 @@ bool is_inter_cluster_node(const RRGraphView& rr_graph_view, int layer = rr_graph_view.node_layer(node_id); int node_ptc = rr_graph_view.node_ptc_num(node_id); const t_physical_tile_type_ptr physical_tile = g_vpr_ctx.device().grid.get_physical_type({x_low, y_low, layer}); - if (node_type == IPIN || node_type == OPIN) { + if (node_type == e_rr_type::IPIN || node_type == e_rr_type::OPIN) { return is_pin_on_tile(physical_tile, node_ptc); } else { - VTR_ASSERT_DEBUG(node_type == SINK || node_type == SOURCE); + VTR_ASSERT_DEBUG(node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE); return is_class_on_tile(physical_tile, node_ptc); } } @@ -1778,14 +1686,14 @@ int get_rr_node_max_ptc(const RRGraphView& rr_graph_view, bool is_flat) { auto node_type = rr_graph_view.node_type(node_id); - VTR_ASSERT(node_type == IPIN || node_type == OPIN || node_type == SINK || node_type == SOURCE); + VTR_ASSERT(node_type == e_rr_type::IPIN || node_type == e_rr_type::OPIN || node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE); const DeviceContext& device_ctx = g_vpr_ctx.device(); auto physical_type = device_ctx.grid.get_physical_type({rr_graph_view.node_xlow(node_id), rr_graph_view.node_ylow(node_id), rr_graph_view.node_layer(node_id)}); - if (node_type == SINK || node_type == SOURCE) { + if (node_type == e_rr_type::SINK || node_type == e_rr_type::SOURCE) { return get_tile_class_max_ptc(physical_type, is_flat); } else { return get_tile_pin_max_ptc(physical_type, is_flat); @@ -1799,7 +1707,7 @@ RRNodeId get_pin_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, const int root_j, int pin_physical_num) { auto pin_type = get_pin_type_from_pin_physical_num(physical_tile, pin_physical_num); - t_rr_type node_type = (pin_type == e_pin_type::DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN; + e_rr_type node_type = (pin_type == e_pin_type::DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; std::vector x_offset; std::vector y_offset; std::vector pin_sides; @@ -1827,22 +1735,22 @@ RRNodeId get_class_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, int class_physical_num) { auto class_type = get_class_type_from_class_physical_num(physical_tile, class_physical_num); VTR_ASSERT(class_type == DRIVER || class_type == RECEIVER); - t_rr_type node_type = (class_type == e_pin_type::DRIVER) ? t_rr_type::SOURCE : t_rr_type::SINK; + e_rr_type node_type = (class_type == e_pin_type::DRIVER) ? e_rr_type::SOURCE : e_rr_type::SINK; return rr_spatial_lookup.find_node(layer, i, j, node_type, class_physical_num); } bool node_in_same_physical_tile(RRNodeId node_first, RRNodeId node_second) { const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - auto first_rr_type = rr_graph.node_type(node_first); + auto firse_rr_type = rr_graph.node_type(node_first); auto second_rr_type = rr_graph.node_type(node_second); // If one of the given node's type is CHANX/Y nodes are definitely not in the same physical tile - if (first_rr_type == t_rr_type::CHANX || first_rr_type == t_rr_type::CHANY || second_rr_type == t_rr_type::CHANX || second_rr_type == t_rr_type::CHANY) { + if (firse_rr_type == e_rr_type::CHANX || firse_rr_type == e_rr_type::CHANY || second_rr_type == e_rr_type::CHANX || second_rr_type == e_rr_type::CHANY) { return false; } else { - VTR_ASSERT(first_rr_type == t_rr_type::IPIN || first_rr_type == t_rr_type::OPIN || first_rr_type == t_rr_type::SINK || first_rr_type == t_rr_type::SOURCE); - VTR_ASSERT(second_rr_type == t_rr_type::IPIN || second_rr_type == t_rr_type::OPIN || second_rr_type == t_rr_type::SINK || second_rr_type == t_rr_type::SOURCE); + VTR_ASSERT(firse_rr_type == e_rr_type::IPIN || firse_rr_type == e_rr_type::OPIN || firse_rr_type == e_rr_type::SINK || firse_rr_type == e_rr_type::SOURCE); + VTR_ASSERT(second_rr_type == e_rr_type::IPIN || second_rr_type == e_rr_type::OPIN || second_rr_type == e_rr_type::SINK || second_rr_type == e_rr_type::SOURCE); int first_layer = rr_graph.node_layer(node_first); int first_x = rr_graph.node_xlow(node_first); int first_y = rr_graph.node_ylow(node_first); @@ -1869,18 +1777,18 @@ bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node) { const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - VTR_ASSERT(rr_graph.node_type(src_rr_node) == SOURCE && rr_graph.node_type(sink_rr_node) == SINK); + VTR_ASSERT(rr_graph.node_type(src_rr_node) == e_rr_type::SOURCE && rr_graph.node_type(sink_rr_node) == e_rr_type::SINK); // A direct connection is defined as a specific path: `SOURCE -> OPIN -> IPIN -> SINK`. //TODO: This is a constant depth search, but still may be too slow for (t_edge_size i_src_edge = 0; i_src_edge < rr_graph.num_edges(src_rr_node); ++i_src_edge) { RRNodeId opin_rr_node = rr_graph.edge_sink_node(src_rr_node, i_src_edge); - if (rr_graph.node_type(opin_rr_node) != OPIN) continue; + if (rr_graph.node_type(opin_rr_node) != e_rr_type::OPIN) continue; for (t_edge_size i_opin_edge = 0; i_opin_edge < rr_graph.num_edges(opin_rr_node); ++i_opin_edge) { RRNodeId ipin_rr_node = rr_graph.edge_sink_node(opin_rr_node, i_opin_edge); - if (rr_graph.node_type(ipin_rr_node) != IPIN) continue; + if (rr_graph.node_type(ipin_rr_node) != e_rr_type::IPIN) continue; for (t_edge_size i_ipin_edge = 0; i_ipin_edge < rr_graph.num_edges(ipin_rr_node); ++i_ipin_edge) { if (sink_rr_node == rr_graph.edge_sink_node(ipin_rr_node, i_ipin_edge)) { diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index aa36ce3f03c..c81b00db08e 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -1,5 +1,4 @@ -#ifndef VPR_UTILS_H -#define VPR_UTILS_H +#pragma once #include "arch_util.h" #include "atom_netlist.h" @@ -15,9 +14,6 @@ class DeviceGrid; class UserRouteConstraints; -const t_model* find_model(const t_model* models, const std::string& name, bool required = true); -const t_model_ports* find_model_port(const t_model* model, const std::string& name, bool required = true); - void print_tabs(FILE* fpout, int num_tab); bool is_clb_external_pin(ClusterBlockId blk_id, int pb_pin_id); @@ -184,9 +180,6 @@ InstPort parse_inst_port(const std::string& str); //Returns the block type which is most likely the logic block t_logical_block_type_ptr infer_logic_block_type(const DeviceGrid& grid); -int get_max_primitives_in_pb_type(t_pb_type* pb_type); -int get_max_depth_of_pb_type(t_pb_type* pb_type); -int get_max_nets_in_pb_type(const t_pb_type* pb_type); bool primitive_type_feasible(AtomBlockId blk_id, const t_pb_type* cur_pb_type); t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* model_port, const int model_pin, const t_pb_graph_node* pb_graph_node); /// @brief Gets the pb_graph_node pin at the given pin index for the given @@ -244,7 +237,7 @@ std::vector get_all_pb_graph_node_primitives(const t_pb_ bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, const VibInf* vib, - t_rr_type node_type, + e_rr_type node_type, int node_ptc); bool is_inter_cluster_node(const RRGraphView& rr_graph_view, @@ -297,13 +290,6 @@ std::vector get_cluster_netlist_intra_tile_classes_at_loc(int layer, /** * @brief Returns the list of pins inside the tile located at (layer, i, j), except for the ones which are on a chain - * @param layer - * @param i - * @param j - * @param pin_chains - * @param pin_chains_num - * @param physical_type - * @return */ std::vector get_cluster_netlist_intra_tile_pins_at_loc(const int layer, const int i, @@ -376,5 +362,3 @@ class PortPinToBlockPinConverter { */ std::vector>>> blk_pin_from_port_pin_; }; - -#endif diff --git a/vpr/test/test_ap_primitive_vector.cpp b/vpr/test/test_ap_primitive_vector.cpp index 425f4e20f35..d3455d7cfe7 100644 --- a/vpr/test/test_ap_primitive_vector.cpp +++ b/vpr/test/test_ap_primitive_vector.cpp @@ -241,6 +241,24 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { vec2 *= -1.f; REQUIRE(vec2.manhattan_norm() == vec1.manhattan_norm()); + // sum: + vec1.clear(); + // Sum of the zero vector is zero. + REQUIRE(vec1.sum() == 0.f); + // Sum of a non-negative vector is the sum of its dims. + vec1.set_dim_val(0, 1.f); + REQUIRE(vec1.sum() == 1.f); + vec1.set_dim_val(1, 2.f); + vec1.set_dim_val(2, 3.f); + vec1.set_dim_val(3, 4.f); + vec1.set_dim_val(4, 5.f); + REQUIRE(vec1.sum() == 15.f); + // Sum of a negative vector is the opposite of the sum of the absolute + // value of its dims. + vec2 = vec1; + vec2 *= -1.f; + REQUIRE(vec2.sum() == -1.f * vec1.sum()); + // Projection: // Basic example: vec1.clear(); diff --git a/vpr/test/test_compressed_grid.cpp b/vpr/test/test_compressed_grid.cpp index 028a1164af9..cd65133ca5c 100644 --- a/vpr/test/test_compressed_grid.cpp +++ b/vpr/test/test_compressed_grid.cpp @@ -1,15 +1,10 @@ +#include "arch_util.h" #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "compressed_grid.h" #include "globals.h" #include "physical_types.h" -// for comparing floats -#include "vtr_math.h" - -#include - namespace { void set_type_tile_to_empty(const int x, const int y, vtr::NdMatrix& grid) { diff --git a/vpr/test/test_connection_router.cpp b/vpr/test/test_connection_router.cpp deleted file mode 100644 index 138e003b04e..00000000000 --- a/vpr/test/test_connection_router.cpp +++ /dev/null @@ -1,194 +0,0 @@ -#include -#include "catch2/catch_test_macros.hpp" - -#include "route_net.h" -#include "rr_graph_fwd.h" -#include "vpr_api.h" -#include "vpr_signal_handler.h" -#include "globals.h" -#include "net_delay.h" -#include "place_and_route.h" -#include "connection_router.h" -#include "router_delay_profiling.h" - -static constexpr const char kArchFile[] = "../../vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml"; -static constexpr int kMaxHops = 10; - -namespace { - -// Route from source_node to sink_node, returning either the delay, or infinity if unroutable. -static float do_one_route(RRNodeId source_node, - RRNodeId sink_node, - const t_det_routing_arch& det_routing_arch, - const t_router_opts& router_opts, - const std::vector& segment_inf) { - bool is_flat = router_opts.flat_routing; - auto& device_ctx = g_vpr_ctx.device(); - - RouteTree tree((RRNodeId(source_node))); - - // Update base costs according to fanout and criticality rules. - update_rr_base_costs(1); - - // Bounding box includes the entire grid. - t_bb bounding_box; - bounding_box.xmin = 0; - bounding_box.xmax = device_ctx.grid.width() + 1; - bounding_box.ymin = 0; - bounding_box.ymax = device_ctx.grid.height() + 1; - bounding_box.layer_min = 0; - bounding_box.layer_max = device_ctx.grid.get_num_layers() - 1; - - t_conn_cost_params cost_params; - cost_params.criticality = router_opts.max_criticality; - cost_params.astar_fac = router_opts.astar_fac; - cost_params.astar_offset = router_opts.astar_offset; - cost_params.bend_cost = router_opts.bend_cost; - - const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - route_budgets budgeting_inf(net_list, is_flat); - - RouterStats router_stats; - auto router_lookahead = make_router_lookahead(det_routing_arch, - router_opts.lookahead_type, - router_opts.write_router_lookahead, - router_opts.read_router_lookahead, - segment_inf, - is_flat); - - ConnectionRouter router( - device_ctx.grid, - *router_lookahead, - device_ctx.rr_graph.rr_nodes(), - &device_ctx.rr_graph, - device_ctx.rr_rc_data, - device_ctx.rr_graph.rr_switch(), - g_vpr_ctx.mutable_routing().rr_node_route_inf, - is_flat); - - // Find the cheapest route if possible. - bool found_path; - RTExploredNode cheapest; - ConnectionParameters conn_params(ParentNetId::INVALID(), - -1, - false, - std::unordered_map()); - std::tie(found_path, std::ignore, cheapest) = router.timing_driven_route_connection_from_route_tree(tree.root(), - sink_node, - cost_params, - bounding_box, - router_stats, - conn_params); - - // Default delay is infinity, which indicates that a route was not found. - float delay = std::numeric_limits::infinity(); - if (found_path) { - // Check that the route goes to the requested sink. - REQUIRE(RRNodeId(cheapest.index) == sink_node); - - // Get the delay - vtr::optional rt_node_of_sink; - std::tie(std::ignore, rt_node_of_sink) = tree.update_from_heap(&cheapest, OPEN, nullptr, router_opts.flat_routing); - delay = rt_node_of_sink.value().Tdel; - } - - // Reset for the next router call. - router.reset_path_costs(); - return delay; -} - -// Find a source and a sink by walking edges. -std::tuple find_source_and_sink() { - auto& device_ctx = g_vpr_ctx.device(); - auto& rr_graph = device_ctx.rr_graph; - - // Current longest walk - std::tuple longest = std::make_tuple(RRNodeId::INVALID(), RRNodeId::INVALID(), 0); - - // Start from each RR node - for (size_t id = 0; id < rr_graph.num_nodes(); id++) { - RRNodeId source(id), sink = source; - for (int hops = 0; hops < kMaxHops; hops++) { - // Take the first edge, if there is one. - auto edge = rr_graph.node_first_edge(sink); - if (edge == rr_graph.node_last_edge(sink)) { - break; - } - sink = rr_graph.rr_nodes().edge_sink_node(edge); - - // If this is the new longest walk, store it. - if (hops > std::get<2>(longest)) { - longest = std::make_tuple(source, sink, hops); - } - } - } - return longest; -} - -// Test that the router can route nets individually, not considering congestion. -// This is a minimal timing driven routing test that can be used as documentation, -// and as a starting point for experimentation. -TEST_CASE("connection_router", "[vpr]") { - // Minimal setup - auto options = t_options(); - auto arch = t_arch(); - auto vpr_setup = t_vpr_setup(); - - vpr_install_signal_handler(); - vpr_initialize_logging(); - - // Command line arguments - const char* argv[] = { - "test_vpr", - kArchFile, - "wire.eblif", - "--route_chan_width", "100"}; - vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); - - vpr_create_device_grid(vpr_setup, arch); - vpr_setup_clock_networks(vpr_setup, arch); - auto det_routing_arch = &vpr_setup.RoutingArch; - auto& router_opts = vpr_setup.RouterOpts; - e_graph_type graph_directionality; - - if (router_opts.route_type == GLOBAL) { - graph_directionality = e_graph_type::BIDIR; - } else { - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); - } - - auto chan_width = init_chan(vpr_setup.RouterOpts.fixed_channel_width, arch.Chans, graph_directionality); - - alloc_routing_structs( - chan_width, - vpr_setup.RouterOpts, - &vpr_setup.RoutingArch, - vpr_setup.Segments, - arch.directs, - router_opts.flat_routing); - - // Find a source and sink to route - RRNodeId source_rr_node, sink_rr_node; - int hops; - std::tie(source_rr_node, sink_rr_node, hops) = find_source_and_sink(); - - // Check that the route will be non-trivial - REQUIRE(source_rr_node != sink_rr_node); - REQUIRE(hops >= 3); - - // Find the route - float delay = do_one_route(source_rr_node, - sink_rr_node, - vpr_setup.RoutingArch, - vpr_setup.RouterOpts, - vpr_setup.Segments); - - // Check that a route was found - REQUIRE(delay < std::numeric_limits::infinity()); - - // Clean up - free_routing_structs(); - vpr_free_all(arch, vpr_setup); -} - -} // namespace diff --git a/vpr/test/test_interchange_device.cpp b/vpr/test/test_interchange_device.cpp index f344adace1b..324d757830a 100644 --- a/vpr/test/test_interchange_device.cpp +++ b/vpr/test/test_interchange_device.cpp @@ -1,8 +1,7 @@ #include "catch2/catch_test_macros.hpp" +#include "logic_types.h" #include "read_fpga_interchange_arch.h" -#include "arch_util.h" -#include "vpr_api.h" #include #include #include @@ -21,21 +20,24 @@ TEST_CASE("read_interchange_models", "[vpr]") { std::unordered_set models = {"IB", "OB", "DFFR", "DFFS", "GND", "VCC"}; // Check that there are exactly the expected models - for (auto* model = arch.models; model != nullptr; model = model->next) { - std::string name = model->name; - REQUIRE(models.find(name) != models.end()); - models.erase(name); + for (LogicalModelId model_id : arch.models.user_models()) { + std::string model_name = arch.models.model_name(model_id); + REQUIRE(models.find(model_name) != models.end()); + models.erase(model_name); } REQUIRE(models.size() == 0); - std::unordered_set lib_models = {MODEL_INPUT, MODEL_OUTPUT, MODEL_LATCH, MODEL_NAMES}; + std::unordered_set lib_models = {LogicalModels::MODEL_INPUT, + LogicalModels::MODEL_OUTPUT, + LogicalModels::MODEL_LATCH, + LogicalModels::MODEL_NAMES}; // Check that there are exactly the expected models - for (auto* model = arch.model_library; model != nullptr; model = model->next) { - std::string name = model->name; - REQUIRE(lib_models.find(name) != lib_models.end()); - lib_models.erase(name); + for (LogicalModelId model_id : arch.models.library_models()) { + std::string model_name = arch.models.model_name(model_id); + REQUIRE(lib_models.find(model_name) != lib_models.end()); + lib_models.erase(model_name); } REQUIRE(lib_models.size() == 0); diff --git a/vpr/test/test_interchange_netlist.cpp b/vpr/test/test_interchange_netlist.cpp index ac1fdfb15f9..1e8804469fb 100644 --- a/vpr/test/test_interchange_netlist.cpp +++ b/vpr/test/test_interchange_netlist.cpp @@ -1,11 +1,10 @@ #include "catch2/catch_test_macros.hpp" +#include "globals.h" #include "read_circuit.h" #include "read_fpga_interchange_arch.h" -#include "arch_util.h" -#include "vpr_api.h" +#include "vpr_types.h" #include -#include #include namespace { @@ -21,8 +20,6 @@ TEST_CASE("read_interchange_netlist", "[vpr]") { FPGAInterchangeReadArch(kArchFile, /*timing_enabled=*/true, &arch, physical_tile_types, logical_block_types); - vpr_setup.user_models = arch.models; - vpr_setup.library_models = arch.model_library; vpr_setup.PackerOpts.circuit_file_name = "lut.netlist"; /* Read blif file and sweep unused components */ diff --git a/vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v b/vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v index 05035b1c749..8bb35ebbcda 100644 --- a/vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v +++ b/vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v @@ -199,8 +199,7 @@ module unconnected ( wire \__vpr__unconn7 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ 1'b0, 1'b0, diff --git a/vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v b/vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v index 4c306642088..f977b09acc4 100644 --- a/vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v +++ b/vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v @@ -204,8 +204,7 @@ module unconnected ( wire \__vpr__unconn12 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ __vpr__unconn0, __vpr__unconn1, diff --git a/vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v b/vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v index 7245c3c9e73..4af549ca9c4 100644 --- a/vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v +++ b/vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v @@ -200,8 +200,7 @@ module unconnected ( wire \__vpr__unconn8 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ 1'bX, 1'bX, diff --git a/vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v b/vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v index 5e8d8202562..595917b0d16 100644 --- a/vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v +++ b/vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v @@ -199,8 +199,7 @@ module unconnected ( wire \__vpr__unconn7 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ 1'bX, 1'bX, diff --git a/vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v b/vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v index 75004405927..c9a6fc5e2d0 100644 --- a/vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v +++ b/vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v @@ -199,8 +199,7 @@ module unconnected ( wire \__vpr__unconn7 ; //Cell instances - dsp #( - ) \dsp_inst ( + dsp \dsp_inst ( .a({ 1'b1, 1'b1, diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index c05d33e54f9..2a4f7a7fc4a 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -71,7 +71,7 @@ TEST_CASE("read_arch_metadata", "[vpr]") { REQUIRE(pb_type_value != nullptr); CHECK_THAT(pb_type_value->as_string().get(&arch.strings), Equals("pb_type = io")); - REQUIRE(type.pb_type->num_modes > 0); + REQUIRE(!type.pb_type->is_primitive()); REQUIRE(type.pb_type->modes != nullptr); for (int imode = 0; imode < type.pb_type->num_modes; ++imode) { @@ -142,7 +142,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { - if ((rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) && rr_graph.num_edges(inode) > 0) { + if ((rr_graph.node_type(inode) == e_rr_type::CHANX || rr_graph.node_type(inode) == e_rr_type::CHANY) && rr_graph.num_edges(inode) > 0) { src_inode = size_t(inode); break; } @@ -267,7 +267,7 @@ TEST_CASE("read_rr_edge_override", "[vpr]") { const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); for (const RRNodeId inode : device_ctx.rr_graph.nodes()) { - if ((rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) && rr_graph.num_edges(inode) > 0) { + if ((rr_graph.node_type(inode) == e_rr_type::CHANX || rr_graph.node_type(inode) == e_rr_type::CHANY) && rr_graph.num_edges(inode) > 0) { src_inode = inode; break; } diff --git a/vtr_flow/parse/parse_config/common/vpr.place.txt b/vtr_flow/parse/parse_config/common/vpr.place.txt index 865a7d2159a..a061a3f2869 100644 --- a/vtr_flow/parse/parse_config/common/vpr.place.txt +++ b/vtr_flow/parse/parse_config/common/vpr.place.txt @@ -1,5 +1,5 @@ #VPR Place Metrics -initial_placed_wirelength_est;vpr.out;Initial placement BB estimate of wirelength:\s*(\d+) +initial_placed_wirelength_est;vpr.out;Initial placement BB estimate of wirelength:\s*(.*) placed_wirelength_est;vpr.out;BB estimate of min-dist \(placement\) wire length: (\d+) #VPR Number of heap operations diff --git a/vtr_flow/primitives.lib b/vtr_flow/primitives.lib new file mode 100644 index 00000000000..0674aca964d --- /dev/null +++ b/vtr_flow/primitives.lib @@ -0,0 +1,370 @@ +/** + * @file + * @author Alex Singer + * @date May 2025 + * @brief A skeleton liberty library used to import the timing connectivity of a + * post-synthesis netlist (from VTR) into OpenSTA. + * + * This file contains just enough information to allow OpenSTA to use a provided + * SDF file for timing analysis of the netlist. + * + * This file only defines the primitives that VPR defines as "library models". + * This includes LUTs (.names) and Flip-Flops (.latch). For user models (the + * models defined in the "models" section of the architecture description file), + * one should create another liberty file. + */ + +library (VTRPrimitives) { + + /* General Attributes */ + delay_model : table_lookup; + + /* Units Attributes */ + time_unit : "1ns"; + + /* Threshold Definitions */ + /* These are the default values according to the Liberty User Manual */ + slew_lower_threshold_pct_fall : 20.00 ; + slew_lower_threshold_pct_rise : 20.00 ; + slew_upper_threshold_pct_fall : 80.00 ; + slew_upper_threshold_pct_rise : 80.00 ; + input_threshold_pct_fall : 50.00 ; + input_threshold_pct_rise : 50.00 ; + output_threshold_pct_fall : 50.00 ; + output_threshold_pct_rise : 50.00 ; + + /* Bus types used for the LUT cells to allow their inputs to be arrays.*/ + type (BUS4) { + base_type: array; + data_type: bit; + bit_width: 4; + bit_from: 3; + bit_to: 0; + } + type (BUS5) { + base_type: array; + data_type: bit; + bit_width: 5; + bit_from: 4; + bit_to: 0; + } + type (BUS6) { + base_type: array; + data_type: bit; + bit_width: 6; + bit_from: 5; + bit_to: 0; + } + type (BUS16) { + base_type: array; + data_type: bit; + bit_width: 16; + bit_from: 15; + bit_to: 0; + } + type (BUS32) { + base_type: array; + data_type: bit; + bit_width: 32; + bit_from: 31; + bit_to: 0; + } + type (BUS64) { + base_type: array; + data_type: bit; + bit_width: 64; + bit_from: 63; + bit_to: 0; + } + + /** + * @brief FPGA interconnect module. This cell acts as a wire in the post- + * implementation netlist to add delays on connections between + * primitives (due to routing delays). + * + * INPUTS: + * datain + * OUPUTS: + * dataout + */ + cell (fpga_interconnect) { + pin (datain) { + direction: input; + } + pin (dataout) { + direction: output; + function: "datain"; + + timing() { + related_pin: "datain"; + timing_sense: positive_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } + + /** + * @brief 4-input LUT module. + * + * INPUTS: + * in: + * The input pins of the LUT, as an array. + * mask: + * The LUT mask that defines the output of the LUT as a function + * of the input. mask[0] is the output if all the inputs are 0, and + * mask[2^k - 1] is the output if all the inputs are 1. + * OUPUTS: + * out + */ + cell (LUT_4) { + bus (mask) { + bus_type: "BUS16"; + direction: input; + } + bus (in) { + bus_type: "BUS4"; + direction: input; + } + pin (out) { + direction: output; + function: "(mask[0] & !in[0] & !in[1] & !in[2] & !in[3]) | (mask[1] & in[0] & !in[1] & !in[2] & !in[3]) | (mask[2] & !in[0] & in[1] & !in[2] & !in[3]) | (mask[3] & in[0] & in[1] & !in[2] & !in[3]) | (mask[4] & !in[0] & !in[1] & in[2] & !in[3]) | (mask[5] & in[0] & !in[1] & in[2] & !in[3]) | (mask[6] & !in[0] & in[1] & in[2] & !in[3]) | (mask[7] & in[0] & in[1] & in[2] & !in[3]) | (mask[8] & !in[0] & !in[1] & !in[2] & in[3]) | (mask[9] & in[0] & !in[1] & !in[2] & in[3]) | (mask[10] & !in[0] & in[1] & !in[2] & in[3]) | (mask[11] & in[0] & in[1] & !in[2] & in[3]) | (mask[12] & !in[0] & !in[1] & in[2] & in[3]) | (mask[13] & in[0] & !in[1] & in[2] & in[3]) | (mask[14] & !in[0] & in[1] & in[2] & in[3]) | (mask[15] & in[0] & in[1] & in[2] & in[3])"; + + timing() { + related_pin: "in"; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } + + /** + * @brief 5-input LUT module. + * + * INPUTS: + * in: + * The input pins of the LUT, as an array. + * mask: + * The LUT mask that defines the output of the LUT as a function + * of the input. mask[0] is the output if all the inputs are 0, and + * mask[2^k - 1] is the output if all the inputs are 1. + * OUPUTS: + * out + */ + cell (LUT_5) { + bus (mask) { + bus_type: "BUS32"; + direction: input; + } + bus (in) { + bus_type: "BUS5"; + direction: input; + } + pin (out) { + direction: output; + function: "(mask[0] & !in[0] & !in[1] & !in[2] & !in[3] & !in[4]) | (mask[1] & in[0] & !in[1] & !in[2] & !in[3] & !in[4]) | (mask[2] & !in[0] & in[1] & !in[2] & !in[3] & !in[4]) | (mask[3] & in[0] & in[1] & !in[2] & !in[3] & !in[4]) | (mask[4] & !in[0] & !in[1] & in[2] & !in[3] & !in[4]) | (mask[5] & in[0] & !in[1] & in[2] & !in[3] & !in[4]) | (mask[6] & !in[0] & in[1] & in[2] & !in[3] & !in[4]) | (mask[7] & in[0] & in[1] & in[2] & !in[3] & !in[4]) | (mask[8] & !in[0] & !in[1] & !in[2] & in[3] & !in[4]) | (mask[9] & in[0] & !in[1] & !in[2] & in[3] & !in[4]) | (mask[10] & !in[0] & in[1] & !in[2] & in[3] & !in[4]) | (mask[11] & in[0] & in[1] & !in[2] & in[3] & !in[4]) | (mask[12] & !in[0] & !in[1] & in[2] & in[3] & !in[4]) | (mask[13] & in[0] & !in[1] & in[2] & in[3] & !in[4]) | (mask[14] & !in[0] & in[1] & in[2] & in[3] & !in[4]) | (mask[15] & in[0] & in[1] & in[2] & in[3] & !in[4]) | (mask[16] & !in[0] & !in[1] & !in[2] & !in[3] & in[4]) | (mask[17] & in[0] & !in[1] & !in[2] & !in[3] & in[4]) | (mask[18] & !in[0] & in[1] & !in[2] & !in[3] & in[4]) | (mask[19] & in[0] & in[1] & !in[2] & !in[3] & in[4]) | (mask[20] & !in[0] & !in[1] & in[2] & !in[3] & in[4]) | (mask[21] & in[0] & !in[1] & in[2] & !in[3] & in[4]) | (mask[22] & !in[0] & in[1] & in[2] & !in[3] & in[4]) | (mask[23] & in[0] & in[1] & in[2] & !in[3] & in[4]) | (mask[24] & !in[0] & !in[1] & !in[2] & in[3] & in[4]) | (mask[25] & in[0] & !in[1] & !in[2] & in[3] & in[4]) | (mask[26] & !in[0] & in[1] & !in[2] & in[3] & in[4]) | (mask[27] & in[0] & in[1] & !in[2] & in[3] & in[4]) | (mask[28] & !in[0] & !in[1] & in[2] & in[3] & in[4]) | (mask[29] & in[0] & !in[1] & in[2] & in[3] & in[4]) | (mask[30] & !in[0] & in[1] & in[2] & in[3] & in[4]) | (mask[31] & in[0] & in[1] & in[2] & in[3] & in[4])"; + + timing() { + related_pin: "in"; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } + + /** + * @brief 6-input LUT module. + * + * INPUTS: + * in: + * The input pins of the LUT, as an array. + * mask: + * The LUT mask that defines the output of the LUT as a function + * of the input. mask[0] is the output if all the inputs are 0, and + * mask[2^k - 1] is the output if all the inputs are 1. + * OUPUTS: + * out + */ + cell (LUT_6) { + bus (mask) { + bus_type: "BUS64"; + direction: input; + } + bus (in) { + bus_type: "BUS6"; + direction: input; + } + pin (out) { + direction: output; + function: "(mask[0] & !in[0] & !in[1] & !in[2] & !in[3] & !in[4] & !in[5]) | (mask[1] & in[0] & !in[1] & !in[2] & !in[3] & !in[4] & !in[5]) | (mask[2] & !in[0] & in[1] & !in[2] & !in[3] & !in[4] & !in[5]) | (mask[3] & in[0] & in[1] & !in[2] & !in[3] & !in[4] & !in[5]) | (mask[4] & !in[0] & !in[1] & in[2] & !in[3] & !in[4] & !in[5]) | (mask[5] & in[0] & !in[1] & in[2] & !in[3] & !in[4] & !in[5]) | (mask[6] & !in[0] & in[1] & in[2] & !in[3] & !in[4] & !in[5]) | (mask[7] & in[0] & in[1] & in[2] & !in[3] & !in[4] & !in[5]) | (mask[8] & !in[0] & !in[1] & !in[2] & in[3] & !in[4] & !in[5]) | (mask[9] & in[0] & !in[1] & !in[2] & in[3] & !in[4] & !in[5]) | (mask[10] & !in[0] & in[1] & !in[2] & in[3] & !in[4] & !in[5]) | (mask[11] & in[0] & in[1] & !in[2] & in[3] & !in[4] & !in[5]) | (mask[12] & !in[0] & !in[1] & in[2] & in[3] & !in[4] & !in[5]) | (mask[13] & in[0] & !in[1] & in[2] & in[3] & !in[4] & !in[5]) | (mask[14] & !in[0] & in[1] & in[2] & in[3] & !in[4] & !in[5]) | (mask[15] & in[0] & in[1] & in[2] & in[3] & !in[4] & !in[5]) | (mask[16] & !in[0] & !in[1] & !in[2] & !in[3] & in[4] & !in[5]) | (mask[17] & in[0] & !in[1] & !in[2] & !in[3] & in[4] & !in[5]) | (mask[18] & !in[0] & in[1] & !in[2] & !in[3] & in[4] & !in[5]) | (mask[19] & in[0] & in[1] & !in[2] & !in[3] & in[4] & !in[5]) | (mask[20] & !in[0] & !in[1] & in[2] & !in[3] & in[4] & !in[5]) | (mask[21] & in[0] & !in[1] & in[2] & !in[3] & in[4] & !in[5]) | (mask[22] & !in[0] & in[1] & in[2] & !in[3] & in[4] & !in[5]) | (mask[23] & in[0] & in[1] & in[2] & !in[3] & in[4] & !in[5]) | (mask[24] & !in[0] & !in[1] & !in[2] & in[3] & in[4] & !in[5]) | (mask[25] & in[0] & !in[1] & !in[2] & in[3] & in[4] & !in[5]) | (mask[26] & !in[0] & in[1] & !in[2] & in[3] & in[4] & !in[5]) | (mask[27] & in[0] & in[1] & !in[2] & in[3] & in[4] & !in[5]) | (mask[28] & !in[0] & !in[1] & in[2] & in[3] & in[4] & !in[5]) | (mask[29] & in[0] & !in[1] & in[2] & in[3] & in[4] & !in[5]) | (mask[30] & !in[0] & in[1] & in[2] & in[3] & in[4] & !in[5]) | (mask[31] & in[0] & in[1] & in[2] & in[3] & in[4] & !in[5]) | (mask[32] & !in[0] & !in[1] & !in[2] & !in[3] & !in[4] & in[5]) | (mask[33] & in[0] & !in[1] & !in[2] & !in[3] & !in[4] & in[5]) | (mask[34] & !in[0] & in[1] & !in[2] & !in[3] & !in[4] & in[5]) | (mask[35] & in[0] & in[1] & !in[2] & !in[3] & !in[4] & in[5]) | (mask[36] & !in[0] & !in[1] & in[2] & !in[3] & !in[4] & in[5]) | (mask[37] & in[0] & !in[1] & in[2] & !in[3] & !in[4] & in[5]) | (mask[38] & !in[0] & in[1] & in[2] & !in[3] & !in[4] & in[5]) | (mask[39] & in[0] & in[1] & in[2] & !in[3] & !in[4] & in[5]) | (mask[40] & !in[0] & !in[1] & !in[2] & in[3] & !in[4] & in[5]) | (mask[41] & in[0] & !in[1] & !in[2] & in[3] & !in[4] & in[5]) | (mask[42] & !in[0] & in[1] & !in[2] & in[3] & !in[4] & in[5]) | (mask[43] & in[0] & in[1] & !in[2] & in[3] & !in[4] & in[5]) | (mask[44] & !in[0] & !in[1] & in[2] & in[3] & !in[4] & in[5]) | (mask[45] & in[0] & !in[1] & in[2] & in[3] & !in[4] & in[5]) | (mask[46] & !in[0] & in[1] & in[2] & in[3] & !in[4] & in[5]) | (mask[47] & in[0] & in[1] & in[2] & in[3] & !in[4] & in[5]) | (mask[48] & !in[0] & !in[1] & !in[2] & !in[3] & in[4] & in[5]) | (mask[49] & in[0] & !in[1] & !in[2] & !in[3] & in[4] & in[5]) | (mask[50] & !in[0] & in[1] & !in[2] & !in[3] & in[4] & in[5]) | (mask[51] & in[0] & in[1] & !in[2] & !in[3] & in[4] & in[5]) | (mask[52] & !in[0] & !in[1] & in[2] & !in[3] & in[4] & in[5]) | (mask[53] & in[0] & !in[1] & in[2] & !in[3] & in[4] & in[5]) | (mask[54] & !in[0] & in[1] & in[2] & !in[3] & in[4] & in[5]) | (mask[55] & in[0] & in[1] & in[2] & !in[3] & in[4] & in[5]) | (mask[56] & !in[0] & !in[1] & !in[2] & in[3] & in[4] & in[5]) | (mask[57] & in[0] & !in[1] & !in[2] & in[3] & in[4] & in[5]) | (mask[58] & !in[0] & in[1] & !in[2] & in[3] & in[4] & in[5]) | (mask[59] & in[0] & in[1] & !in[2] & in[3] & in[4] & in[5]) | (mask[60] & !in[0] & !in[1] & in[2] & in[3] & in[4] & in[5]) | (mask[61] & in[0] & !in[1] & in[2] & in[3] & in[4] & in[5]) | (mask[62] & !in[0] & in[1] & in[2] & in[3] & in[4] & in[5]) | (mask[63] & in[0] & in[1] & in[2] & in[3] & in[4] & in[5])"; + + timing() { + related_pin: "in"; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } + + /** + * @brief D-Flip-Flop module. + * + * INPUTS: + * D: + * The input of the DFF, which will get latched on the rising clock + * edge. + * clock: + * The clock signal for the DFF. + * OUPUTS: + * Q: + * The current value stored in the latch. + * QN: + * The inverse of the current value stored in the latch. + */ + cell (DFF) { + ff (IQ, IQN) { + next_state: "D"; + clocked_on: "clock"; + } + + pin (D) { + direction: input; + + timing() { + related_pin: "clock"; + timing_type: hold_rising; + + fall_constraint(scalar) { + values("0.0"); + } + rise_constraint(scalar) { + values("0.0"); + } + } + + timing() { + related_pin: "clock"; + timing_type: setup_rising; + + fall_constraint(scalar) { + values("0.0"); + } + rise_constraint(scalar) { + values("0.0"); + } + } + } + + pin (clock) { + direction: input; + clock: true; + + timing() { + related_pin: "clock"; + timing_type: min_pulse_width; + + fall_constraint(scalar) { + values("0.0"); + } + rise_constraint(scalar) { + values("0.0"); + } + } + } + + pin (Q) { + direction: output; + function: "IQ"; + + timing() { + related_pin: "clock"; + timing_type: rising_edge; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + + pin (QN) { + direction: output; + function: "IQN"; + + timing() { + related_pin: "clock"; + timing_type: rising_edge; + timing_sense: non_unate; + + cell_fall(scalar) { + values("0.0"); + } + cell_rise(scalar) { + values("0.0"); + } + fall_transition(scalar) { + values("0.0"); + } + rise_transition(scalar) { + values("0.0"); + } + } + } + } +} diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt index a19aa57c938..2af379bd870 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.71 vpr 62.29 MiB -1 -1 0.45 18372 3 0.09 -1 -1 33140 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63780 99 130 353 483 1 222 301 13 13 169 clb auto 22.7 MiB 0.06 730 30541 5185 13290 12066 62.3 MiB 0.05 0.00 28 1583 11 3.33e+06 2.25e+06 384474. 2275.00 0.18 - k4_N10_memSize16384_memData64.xml diffeq1.v common 3.90 vpr 66.30 MiB -1 -1 0.72 23492 23 0.30 -1 -1 34028 -1 -1 77 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67888 162 96 1200 1141 1 675 340 13 13 169 clb auto 25.9 MiB 0.18 5120 92848 24971 61178 6699 66.3 MiB 0.19 0.00 52 9637 13 3.33e+06 2.76e+06 671819. 3975.26 1.14 - k4_N10_memSize16384_memData64.xml single_wire.v common 2.10 vpr 59.81 MiB -1 -1 0.16 16372 1 0.17 -1 -1 29680 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61244 1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 2 3 0 3 0 59.8 MiB 0.01 0.00 2 1 1 30000 0 1489.46 165.495 0.01 - k4_N10_memSize16384_memData64.xml single_ff.v common 2.13 vpr 59.62 MiB -1 -1 0.15 16244 1 0.17 -1 -1 29552 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61048 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 6 9 6 0 3 59.6 MiB 0.01 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.20 vpr 63.47 MiB -1 -1 0.21 18728 3 0.06 -1 -1 32696 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64996 99 130 353 483 1 220 302 13 13 169 clb auto 23.7 MiB 0.03 1748 641 31674 5814 13912 11948 63.5 MiB 0.03 0.00 36 1209 9 3.33e+06 2.28e+06 481319. 2848.04 0.18 +k4_N10_memSize16384_memData64.xml diffeq1.v common 2.73 vpr 66.43 MiB -1 -1 0.30 23332 23 0.24 -1 -1 33444 -1 -1 78 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68020 162 96 1200 1141 1 690 341 14 14 196 clb auto 26.8 MiB 0.11 8696 5304 81261 22686 53433 5142 66.4 MiB 0.09 0.00 46 10726 18 4.32e+06 2.79e+06 735717. 3753.66 1.03 +k4_N10_memSize16384_memData64.xml single_wire.v common 0.51 vpr 61.51 MiB -1 -1 0.06 17188 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62988 1 1 1 2 0 1 2 3 3 9 -1 auto 22.9 MiB 0.00 2 2 3 0 3 0 61.5 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 +k4_N10_memSize16384_memData64.xml single_ff.v common 0.51 vpr 61.52 MiB -1 -1 0.06 17188 1 0.02 -1 -1 29584 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63000 2 1 3 4 1 3 4 3 3 9 -1 auto 22.9 MiB 0.00 6 6 9 6 0 3 61.5 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt index 751bc75b90b..ca1a4d01acd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.47 vpr 63.16 MiB -1 -1 0.44 18236 3 0.17 -1 -1 33188 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 99 130 344 474 1 225 301 13 13 169 clb auto 23.3 MiB 0.09 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128139 0.00121469 0.100824 0.095478 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254103 0.235005 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0312641 0.0288189 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.44 vpr 63.16 MiB -1 -1 0.50 18152 3 0.14 -1 -1 33088 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 99 130 344 474 1 225 301 13 13 169 clb auto 23.2 MiB 0.11 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128481 0.00121739 0.100806 0.0954483 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254201 0.235091 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0311227 0.0286984 - k6_N10_mem32K_40nm.xml diffeq1.v common 9.49 vpr 67.11 MiB -1 -1 0.77 23280 15 0.36 -1 -1 34140 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68724 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.7 MiB 0.29 5596 100404 30167 62963 7274 67.1 MiB 0.72 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332766 0.00312916 0.315543 0.296132 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.42 1.40293 1.28823 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165646 0.152968 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 9.36 vpr 66.73 MiB -1 -1 0.76 23068 15 0.37 -1 -1 34060 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68332 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.4 MiB 0.27 5596 100404 30167 62963 7274 66.7 MiB 0.73 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332438 0.00312633 0.31865 0.29876 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.32 1.38842 1.27429 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165924 0.153299 - k6_N10_mem32K_40nm.xml single_wire.v common 2.19 vpr 61.04 MiB -1 -1 0.10 16040 1 0.17 -1 -1 29628 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62508 1 1 1 2 0 1 2 3 3 9 -1 auto 22.4 MiB 0.03 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0106e-05 6.693e-06 6.7577e-05 4.7955e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00184576 0.00171316 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00130358 0.00127692 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.14 vpr 61.03 MiB -1 -1 0.18 16180 1 0.17 -1 -1 29612 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62496 1 1 1 2 0 1 2 3 3 9 -1 auto 22.5 MiB 0.01 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 3.4991e-05 2.3839e-05 0.000154694 0.000110075 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.01 0.00205152 0.00184775 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106138 0.00103434 - k6_N10_mem32K_40nm.xml single_ff.v common 2.12 vpr 60.94 MiB -1 -1 0.17 16352 1 0.17 -1 -1 29692 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62400 2 1 3 4 1 3 4 3 3 9 -1 auto 22.4 MiB 0.01 6 9 3 5 1 60.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5239e-05 1.148e-05 9.224e-05 7.1486e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00131631 0.00123081 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011347 0.00109647 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.11 vpr 61.02 MiB -1 -1 0.17 16384 1 0.17 -1 -1 29576 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62488 2 1 3 4 1 3 4 3 3 9 -1 auto 22.5 MiB 0.00 6 9 3 5 1 61.0 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.54e-05 1.1599e-05 9.8314e-05 7.6493e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.001247 0.00116724 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00104656 0.00101086 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.47 vpr 65.36 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32736 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66928 99 130 344 474 1 224 302 13 13 169 clb auto 25.8 MiB 0.04 1746 762 68106 19514 34631 13961 65.4 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.11 0.00056191 0.000527319 0.0403153 0.0378126 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.20 0.105519 0.0972534 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.02 0.03 -1 -1 0.01 0.0158349 0.0147659 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.47 vpr 64.98 MiB -1 -1 0.21 18440 3 0.06 -1 -1 32732 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66544 99 130 344 474 1 224 302 13 13 169 clb auto 25.6 MiB 0.04 1746 762 68106 19514 34631 13961 65.0 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.10 0.00055224 0.000517397 0.0404048 0.0379025 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.20 0.106014 0.0977643 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.02 0.03 -1 -1 0.01 0.0156154 0.0145562 +k6_N10_mem32K_40nm.xml diffeq1.v common 4.54 vpr 68.83 MiB -1 -1 0.31 23428 15 0.28 -1 -1 33448 -1 -1 61 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70480 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.1 MiB 0.15 9690 5422 80388 23076 51132 6180 68.8 MiB 0.31 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.17 0.00158429 0.00147162 0.124815 0.116405 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 2.08 0.543747 0.50239 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.22 0.06 -1 -1 0.02 0.0887775 0.0834355 +k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 4.58 vpr 68.39 MiB -1 -1 0.32 23432 15 0.29 -1 -1 33816 -1 -1 61 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70028 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.0 MiB 0.15 9690 5422 80388 23076 51132 6180 68.4 MiB 0.31 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.17 0.00159526 0.00148652 0.124933 0.11659 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 2.09 0.544451 0.503424 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.22 0.06 -1 -1 0.02 0.0856913 0.0804183 +k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 63.12 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64636 1 1 1 2 0 1 2 3 3 9 -1 auto 24.5 MiB 0.00 2 2 3 0 3 0 63.1 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 1.4484e-05 8.56e-06 8.9672e-05 6.0789e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000934459 0.000863394 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000878643 0.000849111 +k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.51 vpr 62.75 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64252 1 1 1 2 0 1 2 3 3 9 -1 auto 24.5 MiB 0.00 2 2 3 0 3 0 62.7 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.879e-06 3.791e-06 5.5775e-05 3.7475e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00087896 0.000824065 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00081755 0.000787937 +k6_N10_mem32K_40nm.xml single_ff.v common 0.51 vpr 62.75 MiB -1 -1 0.06 17284 1 0.02 -1 -1 29580 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64256 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 3 5 1 62.8 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.134e-06 5.954e-06 7.5691e-05 5.6953e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000934593 0.000872745 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000868574 0.000830121 +k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.52 vpr 62.72 MiB -1 -1 0.06 16904 1 0.02 -1 -1 29584 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64224 2 1 3 4 1 3 4 3 3 9 -1 auto 24.1 MiB 0.00 6 6 9 3 5 1 62.7 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 8.915e-06 5.818e-06 7.4453e-05 5.5619e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000952687 0.000889176 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000926898 0.000890064 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt index e5e577a6aa0..614dc34633a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml mkPktMerge.v common 14.27 vpr 75.54 MiB -1 -1 1.67 25360 2 0.13 -1 -1 33796 -1 -1 43 311 15 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77356 311 156 972 1128 1 953 525 28 28 784 memory auto 28.9 MiB 0.44 8505 220693 82593 126911 11189 69.5 MiB 1.24 0.02 3.82651 -4329.36 -3.82651 3.82651 0.84 0.00554225 0.00490893 0.598549 0.528234 -1 -1 -1 -1 40 13414 12 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 6.02 1.94301 1.71815 62360 400487 -1 12485 12 2406 2992 760238 228941 4.26893 4.26893 -4812.21 -4.26893 -13.8425 -0.321515 2.55406e+06 3257.73 0.09 0.29 0.34 -1 -1 0.09 0.16964 0.153486 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml mkPktMerge.v common 6.31 vpr 70.39 MiB -1 -1 0.75 25736 2 0.09 -1 -1 33528 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72080 311 156 972 1128 1 953 525 28 28 784 memory auto 31.2 MiB 0.27 18876 8716 214342 80322 124048 9972 70.4 MiB 0.61 0.01 4.91229 4.39077 -4239.94 -4.39077 4.39077 0.60 0.00262128 0.0023325 0.283495 0.251921 -1 -1 -1 -1 40 13591 16 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 1.96 0.889033 0.801036 62360 400487 -1 12638 13 2518 2949 727753 230227 4.48005 4.48005 -4599.19 -4.48005 -24.1998 -0.322548 2.55406e+06 3257.73 0.08 0.18 0.22 -1 -1 0.08 0.10009 0.0930957 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt index cbe871a6d70..6c901e19f85 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.71 vpr 61.64 MiB -1 -1 0.45 18444 3 0.09 -1 -1 32856 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63120 99 130 353 483 1 222 301 13 13 169 clb auto 21.8 MiB 0.06 723 26509 3069 10019 13421 61.6 MiB 0.04 0.00 28 1598 8 3.33e+06 2.25e+06 384474. 2275.00 0.18 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 1.11 vpr 62.57 MiB -1 -1 0.21 18340 3 0.06 -1 -1 32272 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64072 99 130 353 483 1 221 302 13 13 169 clb auto 22.8 MiB 0.03 1823 708 26614 3324 9855 13435 62.6 MiB 0.02 0.00 28 1654 13 3.33e+06 2.28e+06 384474. 2275.00 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt index 68c5f54f784..513370f5331 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.06 vpr 62.63 MiB 0.05 9228 -1 -1 4 0.26 -1 -1 34628 -1 -1 78 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64132 99 130 378 508 1 260 308 14 14 196 clb auto 23.1 MiB 0.07 836 35634 7872 13338 14424 62.6 MiB 0.06 0.00 30 1863 18 4.32e+06 2.46e+06 504535. 2574.16 1.49 - k4_N10_memSize16384_memData64.xml diffeq1.v common 3.71 vpr 66.76 MiB 0.03 9312 -1 -1 23 0.28 -1 -1 34812 -1 -1 78 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68360 162 96 1214 1147 1 691 341 14 14 196 clb auto 26.3 MiB 0.20 5391 114581 32074 75067 7440 66.8 MiB 0.23 0.00 50 10696 14 4.32e+06 2.79e+06 792225. 4041.96 1.36 - k4_N10_memSize16384_memData64.xml single_wire.v common 0.50 vpr 60.26 MiB 0.03 6196 -1 -1 1 0.02 -1 -1 29884 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61708 1 1 1 2 0 1 2 3 3 9 -1 auto 21.5 MiB 0.00 2 3 0 3 0 60.3 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 - k4_N10_memSize16384_memData64.xml single_ff.v common 0.50 vpr 60.32 MiB 0.01 6248 -1 -1 1 0.02 -1 -1 29888 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61772 2 1 3 4 1 3 4 3 3 9 -1 auto 21.6 MiB 0.00 6 9 6 0 3 60.3 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.37 odin 98.62 MiB 2.09 100992 -1 -1 4 0.20 -1 -1 33712 -1 -1 77 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65108 99 130 378 508 1 264 307 13 13 169 clb auto 23.7 MiB 0.03 2217 834 80002 17611 37329 25062 63.6 MiB 0.06 0.00 38 1591 8 3.33e+06 2.43e+06 504671. 2986.22 0.18 +k4_N10_memSize16384_memData64.xml diffeq1.v common 4.23 odin 85.88 MiB 1.73 87936 -1 -1 23 0.22 -1 -1 34272 -1 -1 78 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68008 162 96 1214 1147 1 683 341 14 14 196 clb auto 26.8 MiB 0.11 8470 5094 83641 22304 55208 6129 66.4 MiB 0.09 0.00 46 10813 38 4.32e+06 2.79e+06 735717. 3753.66 1.06 +k4_N10_memSize16384_memData64.xml single_wire.v common 1.66 vpr 61.51 MiB 1.16 61056 -1 -1 1 0.02 -1 -1 29296 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62984 1 1 1 2 0 1 2 3 3 9 -1 auto 22.9 MiB 0.00 2 2 3 0 3 0 61.5 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 +k4_N10_memSize16384_memData64.xml single_ff.v common 1.59 vpr 61.52 MiB 1.09 61440 -1 -1 1 0.02 -1 -1 29964 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62996 2 1 3 4 1 3 4 3 3 9 -1 auto 22.9 MiB 0.00 6 6 9 6 0 3 61.5 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt index ef84b66a484..ea885b126e3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.50 vpr 64.15 MiB 0.07 9400 -1 -1 3 0.27 -1 -1 34560 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65688 99 130 363 493 1 255 305 13 13 169 clb auto 24.4 MiB 0.09 908 74177 24418 37403 12356 64.1 MiB 0.26 0.00 2.24932 -227.778 -2.24932 2.24932 0.32 0.00128796 0.00121332 0.096703 0.0915143 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.05 0.536952 0.490784 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.11 0.11 0.05 -1 -1 0.11 0.067572 0.0617159 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 4.47 vpr 64.18 MiB 0.07 9504 -1 -1 3 0.27 -1 -1 34508 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65716 99 130 363 493 1 255 305 13 13 169 clb auto 24.4 MiB 0.09 908 74177 24418 37403 12356 64.2 MiB 0.25 0.00 2.24932 -227.778 -2.24932 2.24932 0.33 0.00129519 0.00122409 0.0975081 0.0921414 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.05 0.537515 0.491308 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.10 0.10 0.06 -1 -1 0.10 0.0672906 0.0614343 - k6_N10_mem32K_40nm.xml diffeq1.v common 7.21 vpr 67.98 MiB 0.05 9412 -1 -1 15 0.36 -1 -1 34576 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69616 162 96 999 932 1 661 323 16 16 256 mult_36 auto 27.8 MiB 0.27 5495 75599 21207 48608 5784 68.0 MiB 0.58 0.01 21.6615 -1879.46 -21.6615 21.6615 0.51 0.00360796 0.00340202 0.25554 0.240594 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 3.00 1.1065 1.02126 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.21 0.36 0.12 -1 -1 0.21 0.171024 0.158501 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 7.19 vpr 68.00 MiB 0.05 9256 -1 -1 15 0.38 -1 -1 34544 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69628 162 96 999 932 1 661 323 16 16 256 mult_36 auto 27.8 MiB 0.27 5495 75599 21207 48608 5784 68.0 MiB 0.58 0.01 21.6615 -1879.46 -21.6615 21.6615 0.51 0.00357179 0.00336822 0.255146 0.240275 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 3.02 1.11639 1.03133 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.21 0.36 0.12 -1 -1 0.21 0.171551 0.159214 - k6_N10_mem32K_40nm.xml single_wire.v common 0.52 vpr 61.57 MiB 0.02 6336 -1 -1 1 0.02 -1 -1 29916 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63052 1 1 1 2 0 1 2 3 3 9 -1 auto 23.1 MiB 0.00 2 3 0 3 0 61.6 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0413e-05 6.444e-06 6.9938e-05 4.9915e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00113499 0.00107062 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00114956 0.00110637 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.50 vpr 61.70 MiB 0.01 6288 -1 -1 1 0.02 -1 -1 29852 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63176 1 1 1 2 0 1 2 3 3 9 -1 auto 23.1 MiB 0.00 2 3 0 3 0 61.7 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0828e-05 6.306e-06 8.6241e-05 6.4409e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00147956 0.00135131 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00110491 0.00107479 - k6_N10_mem32K_40nm.xml single_ff.v common 0.51 vpr 61.60 MiB 0.01 6340 -1 -1 1 0.02 -1 -1 29792 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63080 2 1 3 4 1 3 4 3 3 9 -1 auto 23.2 MiB 0.00 6 9 5 1 3 61.6 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5674e-05 1.1879e-05 0.000102525 7.8057e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0012801 0.00119733 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109578 0.00105577 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.52 vpr 61.85 MiB 0.01 6336 -1 -1 1 0.02 -1 -1 29872 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63336 2 1 3 4 1 3 4 3 3 9 -1 auto 23.4 MiB 0.00 6 9 5 1 3 61.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5402e-05 1.1583e-05 0.00010302 8.1368e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00128286 0.00120047 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011085 0.00106995 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.09 odin 100.12 MiB 2.45 102528 -1 -1 3 0.20 -1 -1 33716 -1 -1 75 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67068 99 130 363 493 1 253 305 13 13 169 clb auto 26.0 MiB 0.04 2273 844 74177 21541 39695 12941 65.5 MiB 0.18 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.11 0.00102109 0.000975646 0.0645574 0.0608928 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.23 0.134441 0.124635 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0262126 0.0241565 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.69 odin 99.75 MiB 2.12 102144 -1 -1 3 0.20 -1 -1 33712 -1 -1 75 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67028 99 130 363 493 1 253 305 13 13 169 clb auto 25.6 MiB 0.04 2273 844 74177 21541 39695 12941 65.5 MiB 0.12 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.10 0.000551623 0.00051622 0.043118 0.0403948 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.22 0.113077 0.104115 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0264785 0.0243931 +k6_N10_mem32K_40nm.xml diffeq1.v common 5.96 odin 87.00 MiB 1.89 89088 -1 -1 15 0.28 -1 -1 34196 -1 -1 62 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71044 162 96 999 932 1 663 325 16 16 256 mult_36 auto 29.4 MiB 0.14 9594 5574 90802 23938 58756 8108 69.4 MiB 0.34 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.17 0.00167155 0.00156543 0.146309 0.137079 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.77 0.555231 0.516342 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.23 0.06 -1 -1 0.02 0.0953915 0.0898028 +k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 6.11 odin 87.00 MiB 2.05 89088 -1 -1 15 0.30 -1 -1 34232 -1 -1 62 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71036 162 96 999 932 1 663 325 16 16 256 mult_36 auto 29.4 MiB 0.14 9594 5574 90802 23938 58756 8108 69.4 MiB 0.35 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.17 0.00167453 0.00156692 0.147276 0.137984 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.73 0.548675 0.510684 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.23 0.06 -1 -1 0.02 0.0940813 0.0885938 +k6_N10_mem32K_40nm.xml single_wire.v common 1.64 vpr 62.75 MiB 1.13 62208 -1 -1 1 0.02 -1 -1 29284 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64252 1 1 1 2 0 1 2 3 3 9 -1 auto 24.5 MiB 0.00 2 2 3 0 3 0 62.7 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.926e-06 3.897e-06 5.931e-05 4.0663e-05 -1 -1 -1 -1 14 13 1 53894 0 3251.56 361.284 0.00 0.000930685 0.000857938 318 537 -1 13 1 1 1 42 40 1.13321 nan -1.13321 -1.13321 0 0 4350.07 483.341 0.00 0.00 0.00 -1 -1 0.00 0.000814883 0.000785455 +k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.64 vpr 63.12 MiB 1.13 62208 -1 -1 1 0.02 -1 -1 29544 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64636 1 1 1 2 0 1 2 3 3 9 -1 auto 24.9 MiB 0.00 2 2 3 0 3 0 63.1 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.671e-06 3.657e-06 5.512e-05 3.7177e-05 -1 -1 -1 -1 14 13 1 53894 0 3251.56 361.284 0.00 0.00087693 0.000816732 318 537 -1 13 1 1 1 42 40 1.13321 nan -1.13321 -1.13321 0 0 4350.07 483.341 0.00 0.00 0.00 -1 -1 0.00 0.000823421 0.000793996 +k6_N10_mem32K_40nm.xml single_ff.v common 1.65 vpr 63.12 MiB 1.14 62592 -1 -1 1 0.02 -1 -1 29584 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64640 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 5 1 3 63.1 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.509e-06 6.128e-06 7.8966e-05 5.8678e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000960819 0.000895847 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000868741 0.000828858 +k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.76 vpr 62.75 MiB 1.24 62208 -1 -1 1 0.02 -1 -1 29596 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64252 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 5 1 3 62.7 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.481e-06 6.058e-06 7.5019e-05 5.5752e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000976511 0.00091156 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000882718 0.000844713 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt index 919720b66b9..0969bfb6332 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml mkPktMerge.v common 18.64 vpr 68.68 MiB 0.15 16588 -1 -1 2 0.14 -1 -1 33680 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70328 311 156 972 1128 1 953 525 28 28 784 memory auto 29.0 MiB 0.43 9306 216459 81370 124762 10327 68.7 MiB 1.23 0.02 3.96757 -4422.94 -3.96757 3.96757 1.99 0.0055271 0.00489462 0.594444 0.523451 -1 -1 -1 -1 36 14708 20 4.25198e+07 1.05374e+07 1.86960e+06 2384.70 9.73 2.38769 2.10211 60012 360096 -1 13625 12 2932 3661 921536 275737 4.35536 4.35536 -4857.74 -4.35536 -16.7192 -0.318417 2.30301e+06 2937.52 0.63 0.34 0.31 -1 -1 0.63 0.170436 0.153664 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml mkPktMerge.v common 10.82 odin 620.14 MiB 5.17 635024 -1 -1 2 0.09 -1 -1 34820 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71248 311 156 972 1128 1 953 525 28 28 784 memory auto 30.5 MiB 0.26 18730 9136 197406 68626 118543 10237 69.6 MiB 0.53 0.01 4.81396 3.68545 -4313.24 -3.68545 3.68545 0.58 0.00250062 0.00220291 0.243094 0.21545 -1 -1 -1 -1 40 14133 17 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 1.98 0.801256 0.718483 62360 400487 -1 13372 13 2874 3403 928204 274043 3.86375 3.86375 -4754.06 -3.86375 -26.664 -0.360359 2.55406e+06 3257.73 0.08 0.19 0.21 -1 -1 0.08 0.0937982 0.0869213 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt index f19725cfd85..68933f7a97c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.61 vpr 62.39 MiB 0.07 9224 -1 -1 4 0.25 -1 -1 34556 -1 -1 78 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63888 99 130 378 508 1 260 308 14 14 196 clb auto 23.3 MiB 0.07 836 35634 7872 13338 14424 62.4 MiB 0.06 0.00 30 1863 18 4.32e+06 2.46e+06 504535. 2574.16 0.99 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 1.46 odin 97.50 MiB 0.17 99840 -1 -1 4 0.19 -1 -1 33712 -1 -1 77 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65056 99 130 378 508 1 264 307 13 13 169 clb auto 23.7 MiB 0.03 2217 834 80002 17611 37329 25062 63.5 MiB 0.07 0.00 38 1591 8 3.33e+06 2.43e+06 504671. 2986.22 0.18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt index 6bdbf89bdbe..2946d486557 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt @@ -128,4 +128,4 @@ qor_parse_file=qor_standard.txt # Pass requirements pass_requirements_file=pass_requirements_chain_small.txt -script_params=-lut_size 6 -routing_failure_predictor off -seed 1 +script_params=-lut_size 6 -routing_failure_predictor off -seed 2 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt index 99080e3a8c6..ef10cbea02c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt @@ -1,211 +1,211 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.81 vpr 61.53 MiB -1 -1 0.14 17176 2 0.05 -1 -1 31920 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63004 9 5 28 33 1 17 16 17 17 289 -1 unnamed_device 22.7 MiB 0.01 102 56 22 34 0 61.5 MiB 0.00 0.00 1.25905 -11.4776 -1.25905 1.25905 0.35 8.882e-05 8.0374e-05 0.000503367 0.000460617 -1 -1 -1 -1 20 177 7 6.55708e+06 24110 394039. 1363.46 0.24 0.00338036 0.00301975 19870 87366 -1 145 5 37 42 2127 683 1.13885 1.13885 -10.6853 -1.13885 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00234608 0.00214041 13 6 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.75 vpr 61.79 MiB -1 -1 0.15 17260 2 0.07 -1 -1 31784 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63268 11 6 34 40 1 20 19 17 17 289 -1 unnamed_device 23.1 MiB 0.01 68 419 92 314 13 61.8 MiB 0.01 0.00 1.13885 -12.6274 -1.13885 1.13885 0.36 0.000104018 9.4606e-05 0.00207701 0.00189506 -1 -1 -1 -1 20 166 5 6.55708e+06 24110 394039. 1363.46 0.25 0.00525114 0.0047588 19870 87366 -1 137 4 34 37 1601 538 1.01865 1.01865 -12.5587 -1.01865 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00240353 0.00219298 16 7 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.70 vpr 61.61 MiB -1 -1 0.12 17184 3 0.05 -1 -1 31860 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63088 13 7 41 48 1 27 23 17 17 289 -1 unnamed_device 22.9 MiB 0.01 135 631 147 469 15 61.6 MiB 0.01 0.00 1.37725 -16.6067 -1.37725 1.37725 0.32 0.000129747 0.00011854 0.00286597 0.002624 -1 -1 -1 -1 20 273 10 6.55708e+06 36165 394039. 1363.46 0.25 0.007305 0.00653074 19870 87366 -1 227 7 76 83 3857 1249 1.25705 1.25705 -17.2319 -1.25705 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0033876 0.00303842 19 9 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.80 vpr 61.52 MiB -1 -1 0.13 17272 3 0.04 -1 -1 31840 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62992 15 8 47 55 1 35 27 17 17 289 -1 unnamed_device 23.1 MiB 0.01 246 1107 227 797 83 61.5 MiB 0.01 0.00 1.23151 -21.1845 -1.23151 1.23151 0.32 0.000140574 0.000128754 0.00439077 0.0040239 -1 -1 -1 -1 22 399 8 6.55708e+06 48220 420624. 1455.45 0.33 0.0233791 0.0196844 20158 92377 -1 374 12 138 186 9733 2657 1.23151 1.23151 -21.7797 -1.23151 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00470751 0.00408781 23 10 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.98 vpr 61.69 MiB -1 -1 0.16 17380 3 0.05 -1 -1 32048 -1 -1 6 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63172 17 9 56 65 1 37 32 17 17 289 -1 unnamed_device 23.3 MiB 0.01 141 1132 207 843 82 61.7 MiB 0.01 0.00 1.73785 -23.0011 -1.73785 1.73785 0.32 0.000177397 0.000163282 0.00448382 0.00413693 -1 -1 -1 -1 26 292 10 6.55708e+06 72330 477104. 1650.88 0.34 0.0230579 0.0195262 21022 109990 -1 253 10 116 150 5905 2088 1.73785 1.73785 -22.979 -1.73785 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00488895 0.00427019 26 14 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.00 vpr 61.60 MiB -1 -1 0.17 17588 4 0.08 -1 -1 31936 -1 -1 6 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63080 19 10 60 70 1 46 35 17 17 289 -1 unnamed_device 23.2 MiB 0.02 206 890 192 689 9 61.6 MiB 0.01 0.00 1.83817 -26.8738 -1.83817 1.83817 0.32 0.00018623 0.000172113 0.00345229 0.00318807 -1 -1 -1 -1 24 503 11 6.55708e+06 72330 448715. 1552.65 0.34 0.023586 0.0197806 20734 103517 -1 456 14 189 265 14696 4171 1.79897 1.79897 -29.1306 -1.79897 0 0 554710. 1919.41 0.02 0.02 0.09 -1 -1 0.02 0.00625358 0.00539304 29 13 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.85 vpr 61.68 MiB -1 -1 0.11 17620 4 0.06 -1 -1 31780 -1 -1 7 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63156 21 11 69 80 1 45 39 17 17 289 -1 unnamed_device 23.2 MiB 0.02 234 1425 276 1119 30 61.7 MiB 0.01 0.00 2.00308 -29.8235 -2.00308 2.00308 0.32 0.00021215 0.000195206 0.00517815 0.0047725 -1 -1 -1 -1 20 484 10 6.55708e+06 84385 394039. 1363.46 0.26 0.011519 0.0102836 19870 87366 -1 431 8 137 199 8705 2803 1.8657 1.8657 -30.3926 -1.8657 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00515178 0.00455678 33 17 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.06 vpr 61.65 MiB -1 -1 0.13 17464 5 0.06 -1 -1 32020 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63128 23 12 76 88 1 52 42 17 17 289 -1 unnamed_device 23.1 MiB 0.02 299 2130 460 1580 90 61.6 MiB 0.02 0.00 2.1851 -34.7155 -2.1851 2.1851 0.31 0.000225836 0.000208793 0.00737873 0.0068159 -1 -1 -1 -1 30 557 11 6.55708e+06 84385 526063. 1820.29 0.39 0.0385933 0.032892 21886 126133 -1 477 9 132 177 10121 2634 2.0649 2.0649 -34.6717 -2.0649 0 0 666494. 2306.21 0.03 0.01 0.10 -1 -1 0.03 0.0056861 0.00499978 36 19 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.97 vpr 61.68 MiB -1 -1 0.15 17448 5 0.06 -1 -1 32056 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63164 25 13 83 96 1 61 46 17 17 289 -1 unnamed_device 23.1 MiB 0.03 382 1604 307 1258 39 61.7 MiB 0.02 0.00 2.1433 -40.194 -2.1433 2.1433 0.32 0.0002374 0.000218617 0.00535399 0.0049428 -1 -1 -1 -1 20 750 24 6.55708e+06 96440 394039. 1363.46 0.28 0.0174527 0.0152737 19870 87366 -1 675 11 204 284 17644 4645 2.0231 2.0231 -41.4897 -2.0231 0 0 477104. 1650.88 0.02 0.02 0.08 -1 -1 0.02 0.00708701 0.00625295 39 21 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.98 vpr 61.82 MiB -1 -1 0.12 17548 5 0.06 -1 -1 31808 -1 -1 10 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 27 14 91 105 1 72 51 17 17 289 -1 unnamed_device 23.2 MiB 0.05 487 1931 345 1368 218 61.8 MiB 0.02 0.00 2.31696 -45.6334 -2.31696 2.31696 0.32 0.000303653 0.000273882 0.00640562 0.00591371 -1 -1 -1 -1 26 873 12 6.55708e+06 120550 477104. 1650.88 0.36 0.0365231 0.0313217 21022 109990 -1 816 8 208 332 18433 4780 1.9839 1.9839 -46.0894 -1.9839 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00631768 0.005585 44 24 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.92 vpr 61.82 MiB -1 -1 0.15 17672 6 0.07 -1 -1 32032 -1 -1 10 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 29 15 95 110 1 74 54 17 17 289 -1 unnamed_device 23.2 MiB 0.03 326 1992 324 1638 30 61.8 MiB 0.02 0.00 2.92362 -47.3926 -2.92362 2.92362 0.32 0.000283404 0.000262906 0.00638465 0.00592117 -1 -1 -1 -1 26 681 9 6.55708e+06 120550 477104. 1650.88 0.29 0.0229025 0.019846 21022 109990 -1 645 14 253 412 18759 5604 2.76422 2.76422 -48.0089 -2.76422 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00906397 0.00783781 46 23 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.02 vpr 61.88 MiB -1 -1 0.17 17476 6 0.07 -1 -1 31980 -1 -1 10 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63364 31 16 104 120 1 74 57 17 17 289 -1 unnamed_device 23.2 MiB 0.03 413 2455 496 1792 167 61.9 MiB 0.02 0.00 2.5437 -52.0473 -2.5437 2.5437 0.32 0.000314967 0.000292737 0.00803663 0.00746438 -1 -1 -1 -1 28 797 9 6.55708e+06 120550 500653. 1732.36 0.37 0.0394837 0.0339214 21310 115450 -1 706 7 169 223 12972 3468 2.5437 2.5437 -53.9588 -2.5437 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.0066224 0.00586415 50 27 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.89 vpr 61.88 MiB -1 -1 0.17 17512 7 0.07 -1 -1 32112 -1 -1 10 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63364 33 17 112 129 1 80 60 17 17 289 -1 unnamed_device 23.1 MiB 0.03 455 2400 450 1872 78 61.9 MiB 0.01 0.00 2.77173 -56.4743 -2.77173 2.77173 0.28 0.000151138 0.000138573 0.00382632 0.0035109 -1 -1 -1 -1 22 966 13 6.55708e+06 120550 420624. 1455.45 0.24 0.0223788 0.0192259 20158 92377 -1 820 14 243 337 17062 5047 2.6619 2.6619 -58.7642 -2.6619 0 0 500653. 1732.36 0.02 0.02 0.08 -1 -1 0.02 0.010673 0.0092982 54 30 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.09 vpr 61.96 MiB -1 -1 0.17 17540 7 0.06 -1 -1 31948 -1 -1 13 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63444 37 19 127 146 1 95 69 17 17 289 -1 unnamed_device 23.1 MiB 0.04 580 5286 1128 3575 583 62.0 MiB 0.04 0.00 2.83296 -65.8925 -2.83296 2.83296 0.32 0.000370259 0.000344095 0.0149742 0.013844 -1 -1 -1 -1 28 987 8 6.55708e+06 156715 500653. 1732.36 0.38 0.0517571 0.0451646 21310 115450 -1 947 6 224 327 15796 4347 2.6201 2.6201 -68.3998 -2.6201 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.00692764 0.00618013 63 35 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.16 vpr 61.99 MiB -1 -1 0.15 17432 8 0.07 -1 -1 31996 -1 -1 14 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63480 41 21 139 160 1 106 76 17 17 289 -1 unnamed_device 22.9 MiB 0.04 588 8396 2008 5342 1046 62.0 MiB 0.05 0.00 3.1799 -77.5868 -3.1799 3.1799 0.34 0.000399995 0.000371199 0.0222085 0.0206233 -1 -1 -1 -1 26 1120 12 6.55708e+06 168770 477104. 1650.88 0.38 0.0643844 0.0565876 21022 109990 -1 1022 10 319 425 23447 6363 3.1799 3.1799 -79.2365 -3.1799 0 0 585099. 2024.56 0.03 0.02 0.12 -1 -1 0.03 0.00931512 0.00841851 67 37 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.19 vpr 62.45 MiB -1 -1 0.13 17484 9 0.07 -1 -1 31884 -1 -1 15 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63948 45 23 153 176 1 107 83 17 17 289 -1 unnamed_device 23.1 MiB 0.05 536 7643 1816 4897 930 62.4 MiB 0.05 0.00 4.01419 -88.5998 -4.01419 4.01419 0.32 0.000435711 0.000404292 0.0198098 0.0183771 -1 -1 -1 -1 26 1149 13 6.55708e+06 180825 477104. 1650.88 0.44 0.0661535 0.0580745 21022 109990 -1 1003 13 321 492 25700 7436 3.87922 3.87922 -89.4779 -3.87922 0 0 585099. 2024.56 0.03 0.03 0.10 -1 -1 0.03 0.0114958 0.0102772 73 41 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.19 vpr 62.10 MiB -1 -1 0.13 17776 10 0.07 -1 -1 32012 -1 -1 15 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63588 49 25 166 191 1 117 89 17 17 289 -1 unnamed_device 22.7 MiB 0.04 524 8207 1797 5151 1259 62.1 MiB 0.05 0.00 4.48062 -100.236 -4.48062 4.48062 0.32 0.000471573 0.000438453 0.0210235 0.0195468 -1 -1 -1 -1 26 1157 12 6.55708e+06 180825 477104. 1650.88 0.44 0.070761 0.0623165 21022 109990 -1 1039 10 321 455 24838 7158 4.40948 4.40948 -103.002 -4.40948 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0115319 0.01024 78 44 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.40 vpr 62.41 MiB -1 -1 0.16 17836 11 0.07 -1 -1 32112 -1 -1 20 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 57 29 198 227 1 147 106 17 17 289 -1 unnamed_device 23.0 MiB 0.05 782 8606 1708 6393 505 62.4 MiB 0.06 0.00 4.94665 -134.466 -4.94665 4.94665 0.33 0.000571874 0.000532504 0.0215301 0.0200481 -1 -1 -1 -1 28 1522 13 6.55708e+06 241100 500653. 1732.36 0.43 0.0827513 0.0729032 21310 115450 -1 1371 8 367 517 27034 7537 4.59642 4.59642 -133.949 -4.59642 0 0 612192. 2118.31 0.03 0.03 0.11 -1 -1 0.03 0.0120118 0.0107143 93 56 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.50 vpr 62.60 MiB -1 -1 0.19 17800 13 0.08 -1 -1 32188 -1 -1 20 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 65 33 224 257 1 164 118 17 17 289 -1 unnamed_device 22.9 MiB 0.06 928 17169 4443 10653 2073 62.6 MiB 0.10 0.00 5.28408 -153.681 -5.28408 5.28408 0.36 0.000649312 0.000604542 0.0408491 0.0380181 -1 -1 -1 -1 30 1659 12 6.55708e+06 241100 526063. 1820.29 0.47 0.109688 0.0977858 21886 126133 -1 1555 13 429 584 31745 8729 5.08288 5.08288 -153.594 -5.08288 0 0 666494. 2306.21 0.04 0.03 0.12 -1 -1 0.04 0.016224 0.0145393 107 62 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.63 vpr 63.23 MiB -1 -1 0.20 18112 19 0.10 -1 -1 32232 -1 -1 34 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 97 49 340 389 1 260 180 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1520 22532 5263 15517 1752 63.2 MiB 0.13 0.00 7.62655 -301.388 -7.62655 7.62655 0.29 0.000991752 0.000926486 0.0481233 0.0448481 -1 -1 -1 -1 30 2687 13 6.55708e+06 409870 526063. 1820.29 0.51 0.154423 0.138579 21886 126133 -1 2432 11 662 955 55712 14661 7.28333 7.28333 -297.521 -7.28333 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0249464 0.0224501 165 98 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.24 vpr 63.93 MiB -1 -1 0.28 18296 26 0.13 -1 -1 32396 -1 -1 41 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65464 129 65 453 518 1 334 235 17 17 289 -1 unnamed_device 24.1 MiB 0.10 1951 55259 16458 32932 5869 63.9 MiB 0.28 0.00 10.6369 -487.594 -10.6369 10.6369 0.34 0.00134162 0.00125451 0.10975 0.102432 -1 -1 -1 -1 30 3742 35 6.55708e+06 494255 526063. 1820.29 0.78 0.289369 0.262587 21886 126133 -1 3039 12 909 1148 67590 18881 10.0187 10.0187 -472.64 -10.0187 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0361792 0.0327806 210 131 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.49 abc 29.28 MiB -1 -1 0.10 17348 1 0.02 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.58 abc 29.28 MiB -1 -1 0.12 17328 1 0.03 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23928 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.66 abc 29.27 MiB -1 -1 0.14 17352 1 0.02 -1 -1 29972 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24144 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.66 abc 29.22 MiB -1 -1 0.14 17312 1 0.02 -1 -1 29924 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24024 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.63 abc 29.30 MiB -1 -1 0.14 17436 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.61 abc 29.30 MiB -1 -1 0.15 17384 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24072 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.58 abc 29.34 MiB -1 -1 0.16 17320 1 0.03 -1 -1 30048 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23932 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.55 abc 29.36 MiB -1 -1 0.14 17188 1 0.02 -1 -1 30068 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24076 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.83 abc 29.29 MiB -1 -1 0.16 17156 1 0.02 -1 -1 29992 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.67 abc 29.23 MiB -1 -1 0.15 17352 1 0.02 -1 -1 29936 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23964 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.64 abc 29.44 MiB -1 -1 0.15 17296 1 0.02 -1 -1 30144 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24080 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.82 abc 29.46 MiB -1 -1 0.16 17372 1 0.02 -1 -1 30164 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24028 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.90 abc 29.28 MiB -1 -1 0.16 17348 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24032 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.13 abc 29.58 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30288 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24004 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.11 abc 29.28 MiB -1 -1 0.15 17584 1 0.03 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24108 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 1.33 abc 29.30 MiB -1 -1 0.15 17496 1 0.04 -1 -1 30004 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24068 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 1.13 abc 29.30 MiB -1 -1 0.16 17684 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24012 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.59 abc 29.43 MiB -1 -1 0.16 17528 1 0.02 -1 -1 30140 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24212 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.61 abc 29.43 MiB -1 -1 0.14 17660 1 0.03 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24056 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.60 abc 29.41 MiB -1 -1 0.12 17788 1 0.03 -1 -1 30116 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24088 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.42 abc 29.55 MiB -1 -1 0.21 18072 1 0.03 -1 -1 30256 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24028 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.58 abc 29.32 MiB -1 -1 0.15 17340 1 0.02 -1 -1 30024 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23756 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.56 abc 29.36 MiB -1 -1 0.14 17204 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23848 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.46 abc 29.20 MiB -1 -1 0.08 17420 1 0.02 -1 -1 29904 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23768 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.55 abc 29.36 MiB -1 -1 0.16 17368 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23832 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.50 abc 29.30 MiB -1 -1 0.11 17336 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23792 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.56 abc 29.30 MiB -1 -1 0.14 17268 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23780 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.64 abc 29.29 MiB -1 -1 0.15 17364 1 0.03 -1 -1 29996 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23676 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.77 abc 29.50 MiB -1 -1 0.15 17480 1 0.02 -1 -1 30208 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23908 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.87 abc 29.35 MiB -1 -1 0.13 17308 1 0.03 -1 -1 30056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23860 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.78 abc 29.34 MiB -1 -1 0.15 17316 1 0.02 -1 -1 30044 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23840 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.90 abc 29.28 MiB -1 -1 0.13 17320 1 0.03 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23792 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.55 abc 29.28 MiB -1 -1 0.15 17412 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23760 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.57 abc 29.43 MiB -1 -1 0.14 17428 1 0.02 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23804 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.59 abc 29.38 MiB -1 -1 0.15 17580 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23888 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.59 abc 29.28 MiB -1 -1 0.16 17688 1 0.02 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23704 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.54 abc 29.29 MiB -1 -1 0.14 17696 1 0.02 -1 -1 29988 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23960 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.53 abc 29.36 MiB -1 -1 0.09 17412 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.64 abc 29.38 MiB -1 -1 0.15 17288 1 0.03 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23700 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.68 abc 29.30 MiB -1 -1 0.17 17596 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23696 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.67 abc 29.53 MiB -1 -1 0.14 17704 1 0.03 -1 -1 30236 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.81 abc 29.84 MiB -1 -1 0.22 18144 1 0.04 -1 -1 30556 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23768 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.67 vpr 61.95 MiB -1 -1 0.09 17252 1 0.03 -1 -1 30116 -1 -1 3 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63432 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 23.2 MiB 0.01 145 80 29 46 5 61.9 MiB 0.00 0.00 0.83871 -12.0914 -0.83871 0.83871 0.32 8.9493e-05 8.1196e-05 0.000627793 0.000575929 -1 -1 -1 -1 20 218 6 6.64007e+06 37674 394039. 1363.46 0.25 0.00366787 0.00331915 20530 87850 -1 213 8 56 56 3444 969 0.890248 0.890248 -12.2124 -0.890248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0028001 0.00250588 14 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.81 vpr 61.82 MiB -1 -1 0.15 17384 1 0.02 -1 -1 29928 -1 -1 4 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 23.1 MiB 0.01 179 525 133 355 37 61.8 MiB 0.01 0.00 0.803048 -13.1622 -0.803048 0.803048 0.33 0.000104816 9.5546e-05 0.00232117 0.00211796 -1 -1 -1 -1 20 294 8 6.64007e+06 50232 394039. 1363.46 0.25 0.00578063 0.00517738 20530 87850 -1 279 8 74 74 5640 1476 0.923248 0.923248 -15.592 -0.923248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00307315 0.00274174 17 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.86 vpr 61.86 MiB -1 -1 0.14 17352 1 0.02 -1 -1 30052 -1 -1 5 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63344 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 23.5 MiB 0.01 158 889 183 672 34 61.9 MiB 0.01 0.00 0.825048 -14.9551 -0.825048 0.825048 0.32 0.00012299 0.000112599 0.00344711 0.00315992 -1 -1 -1 -1 22 332 15 6.64007e+06 62790 420624. 1455.45 0.31 0.0177773 0.0149893 20818 92861 -1 288 10 103 103 5874 1694 0.934248 0.934248 -16.7505 -0.934248 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.00384738 0.00340089 20 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.89 vpr 61.98 MiB -1 -1 0.15 17472 1 0.02 -1 -1 30136 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63468 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.6 MiB 0.02 130 827 161 522 144 62.0 MiB 0.01 0.00 1.18536 -16.9426 -1.18536 1.18536 0.32 0.000141038 0.000129717 0.00333865 0.00306739 -1 -1 -1 -1 22 336 15 6.64007e+06 50232 420624. 1455.45 0.34 0.0179109 0.0151424 20818 92861 -1 281 7 118 118 7761 2504 1.08545 1.08545 -19.5322 -1.08545 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.0039426 0.00354868 22 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.04 vpr 61.95 MiB -1 -1 0.14 17348 1 0.02 -1 -1 30048 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63440 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.5 MiB 0.02 156 1759 570 827 362 62.0 MiB 0.02 0.00 1.19636 -19.8289 -1.19636 1.19636 0.32 0.000158366 0.000145724 0.00632531 0.00582349 -1 -1 -1 -1 32 266 11 6.64007e+06 62790 554710. 1919.41 0.38 0.0232912 0.0199009 22834 132086 -1 249 10 97 97 4881 1477 0.834048 0.834048 -18.8492 -0.834048 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00447744 0.00392841 25 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.90 vpr 61.86 MiB -1 -1 0.14 17316 1 0.03 -1 -1 30144 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63348 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.4 MiB 0.02 160 1574 392 922 260 61.9 MiB 0.02 0.00 1.20736 -22.28 -1.20736 1.20736 0.31 0.000177199 0.000163665 0.00559114 0.00516294 -1 -1 -1 -1 22 389 20 6.64007e+06 62790 420624. 1455.45 0.33 0.0271204 0.0230692 20818 92861 -1 335 13 170 170 11128 3516 1.05245 1.05245 -23.8346 -1.05245 0 0 500653. 1732.36 0.03 0.02 0.09 -1 -1 0.03 0.00547305 0.00480176 28 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.93 vpr 62.00 MiB -1 -1 0.15 17268 1 0.03 -1 -1 30160 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63488 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 326 2054 512 1388 154 62.0 MiB 0.02 0.00 1.21836 -28.0305 -1.21836 1.21836 0.32 0.000193986 0.000179202 0.0069198 0.00639758 -1 -1 -1 -1 26 550 12 6.64007e+06 75348 477104. 1650.88 0.35 0.0275302 0.0234892 21682 110474 -1 504 11 163 163 10372 2794 1.00925 1.00925 -29.7279 -1.00925 0 0 585099. 2024.56 0.03 0.02 0.10 -1 -1 0.03 0.00561273 0.00490548 31 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.92 vpr 62.17 MiB -1 -1 0.10 17364 1 0.03 -1 -1 30004 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63660 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.5 MiB 0.02 202 2274 577 1358 339 62.2 MiB 0.02 0.00 1.22936 -27.3302 -1.22936 1.22936 0.32 0.000217044 0.000200805 0.00744746 0.00689241 -1 -1 -1 -1 26 516 20 6.64007e+06 87906 477104. 1650.88 0.37 0.03361 0.0286167 21682 110474 -1 423 19 254 254 15495 4842 1.14165 1.14165 -28.5397 -1.14165 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00847906 0.00723997 35 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.03 vpr 62.03 MiB -1 -1 0.13 17356 1 0.02 -1 -1 30120 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63516 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 23.5 MiB 0.02 225 3162 1067 1505 590 62.0 MiB 0.03 0.00 1.24036 -30.3091 -1.24036 1.24036 0.32 0.000223716 0.000206705 0.00935455 0.00864973 -1 -1 -1 -1 28 585 26 6.64007e+06 100464 500653. 1732.36 0.41 0.0378559 0.0324088 21970 115934 -1 409 25 362 362 24657 7379 1.02145 1.02145 -29.5255 -1.02145 0 0 612192. 2118.31 0.04 0.03 0.10 -1 -1 0.04 0.00908575 0.00781132 38 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.07 vpr 62.03 MiB -1 -1 0.15 17336 1 0.02 -1 -1 30088 -1 -1 9 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63520 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 23.5 MiB 0.02 251 4650 1464 2253 933 62.0 MiB 0.03 0.00 1.25136 -32.7881 -1.25136 1.25136 0.32 0.000239703 0.00022173 0.0129775 0.0119987 -1 -1 -1 -1 32 519 22 6.64007e+06 113022 554710. 1919.41 0.41 0.0419733 0.0362927 22834 132086 -1 437 14 276 276 16327 5300 1.03125 1.03125 -33.0873 -1.03125 0 0 701300. 2426.64 0.03 0.02 0.12 -1 -1 0.03 0.00771732 0.00669493 41 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.96 vpr 62.14 MiB -1 -1 0.15 17348 1 0.02 -1 -1 29924 -1 -1 9 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63628 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 23.5 MiB 0.01 462 4409 1391 2113 905 62.1 MiB 0.03 0.00 1.26236 -39.7652 -1.26236 1.26236 0.32 0.000252152 0.000233455 0.012075 0.0111778 -1 -1 -1 -1 26 812 23 6.64007e+06 113022 477104. 1650.88 0.39 0.0429496 0.0370839 21682 110474 -1 713 17 323 323 26583 6736 1.03125 1.03125 -39.6574 -1.03125 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.00919565 0.00794342 44 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.09 vpr 62.16 MiB -1 -1 0.15 17408 1 0.02 -1 -1 30248 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63656 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.5 MiB 0.03 343 4978 1636 2249 1093 62.2 MiB 0.04 0.00 1.62267 -39.5838 -1.62267 1.62267 0.30 0.000273462 0.000253412 0.0135717 0.0125654 -1 -1 -1 -1 30 686 17 6.64007e+06 113022 526063. 1820.29 0.40 0.0434449 0.0377212 22546 126617 -1 539 11 219 219 10604 3260 0.95891 0.95891 -36.3522 -0.95891 0 0 666494. 2306.21 0.03 0.02 0.10 -1 -1 0.03 0.00745402 0.00655316 46 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.01 vpr 62.13 MiB -1 -1 0.08 17640 1 0.02 -1 -1 30132 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63624 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.4 MiB 0.03 352 6329 2210 2989 1130 62.1 MiB 0.04 0.00 1.63367 -42.2226 -1.63367 1.63367 0.32 0.000292013 0.000271082 0.0171275 0.0158779 -1 -1 -1 -1 28 736 12 6.64007e+06 113022 500653. 1732.36 0.42 0.0478919 0.0418393 21970 115934 -1 618 18 335 335 18999 5605 1.21545 1.21545 -44.5486 -1.21545 0 0 612192. 2118.31 0.03 0.03 0.08 -1 -1 0.03 0.0108162 0.00934396 49 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.08 vpr 62.25 MiB -1 -1 0.14 17540 1 0.02 -1 -1 30084 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.5 MiB 0.03 393 6867 2746 3975 146 62.2 MiB 0.05 0.00 1.65567 -49.3018 -1.65567 1.65567 0.32 0.000329974 0.000306635 0.0176624 0.0164096 -1 -1 -1 -1 30 805 15 6.64007e+06 138138 526063. 1820.29 0.41 0.0534439 0.0465752 22546 126617 -1 630 14 325 325 20407 5991 1.07325 1.07325 -45.7613 -1.07325 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0100761 0.0087606 55 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.04 vpr 62.60 MiB -1 -1 0.13 17640 1 0.03 -1 -1 30388 -1 -1 13 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 23.3 MiB 0.02 587 9239 3659 4903 677 62.6 MiB 0.06 0.00 1.67767 -57.8173 -1.67767 1.67767 0.32 0.000360642 0.000335237 0.0220756 0.0205309 -1 -1 -1 -1 30 1014 13 6.64007e+06 163254 526063. 1820.29 0.42 0.0603789 0.0531045 22546 126617 -1 868 10 304 304 26082 6742 1.02025 1.02025 -52.0508 -1.02025 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.00886711 0.00781227 62 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.27 vpr 62.54 MiB -1 -1 0.16 17708 1 0.02 -1 -1 30284 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64044 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 23.2 MiB 0.03 505 10228 3751 5231 1246 62.5 MiB 0.06 0.00 1.69967 -61.6923 -1.69967 1.69967 0.32 0.000396366 0.000369082 0.0236606 0.0219962 -1 -1 -1 -1 32 1098 29 6.64007e+06 175812 554710. 1919.41 0.53 0.0745634 0.0654141 22834 132086 -1 841 14 524 524 35053 10407 1.18565 1.18565 -55.6154 -1.18565 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0118029 0.0103314 68 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.22 vpr 62.62 MiB -1 -1 0.14 17656 1 0.03 -1 -1 30336 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64128 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.3 MiB 0.04 715 8278 1733 6367 178 62.6 MiB 0.06 0.00 2.07098 -71.4065 -2.07098 2.07098 0.32 0.000425886 0.000396892 0.0193216 0.0179715 -1 -1 -1 -1 30 1249 15 6.64007e+06 175812 526063. 1820.29 0.44 0.0656005 0.0577432 22546 126617 -1 1106 11 343 343 25695 6324 1.09525 1.09525 -65.1787 -1.09525 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0113828 0.0101237 73 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.31 vpr 62.69 MiB -1 -1 0.16 17512 1 0.03 -1 -1 30076 -1 -1 18 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64196 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 23.3 MiB 0.04 774 16452 3708 11655 1089 62.7 MiB 0.10 0.00 2.11498 -86.7435 -2.11498 2.11498 0.32 0.000485084 0.000450927 0.0341069 0.0317077 -1 -1 -1 -1 32 1465 18 6.64007e+06 226044 554710. 1919.41 0.49 0.0895901 0.0796678 22834 132086 -1 1213 17 542 542 36079 10159 1.35645 1.35645 -81.4884 -1.35645 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.016593 0.0145733 86 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.38 vpr 62.91 MiB -1 -1 0.18 17672 1 0.03 -1 -1 30064 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.3 MiB 0.05 1165 18135 6420 10093 1622 62.9 MiB 0.11 0.00 2.50829 -108.778 -2.50829 2.50829 0.32 0.0005667 0.000528433 0.0374509 0.0349335 -1 -1 -1 -1 30 1825 43 6.64007e+06 238602 526063. 1820.29 0.51 0.122573 0.10861 22546 126617 -1 1603 14 500 500 39832 9325 1.21425 1.21425 -91.6209 -1.21425 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.016578 0.0146599 97 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.65 vpr 63.45 MiB -1 -1 0.17 17900 1 0.03 -1 -1 30280 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64976 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.9 MiB 0.07 1660 32449 9442 20195 2812 63.5 MiB 0.20 0.00 3.38291 -180.139 -3.38291 3.38291 0.32 0.000868353 0.000813665 0.0603321 0.056479 -1 -1 -1 -1 30 2741 24 6.64007e+06 364182 526063. 1820.29 0.58 0.167976 0.151769 22546 126617 -1 2404 13 827 827 63818 16162 1.39605 1.39605 -140.523 -1.39605 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0236694 0.0212549 145 2 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.96 vpr 63.93 MiB -1 -1 0.19 18156 1 0.03 -1 -1 30516 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.4 MiB 0.11 2246 49637 16069 29592 3976 63.9 MiB 0.33 0.01 4.25753 -269.223 -4.25753 4.25753 0.32 0.00123279 0.00116168 0.0889312 0.0837218 -1 -1 -1 -1 32 3518 14 6.64007e+06 489762 554710. 1919.41 0.66 0.226555 0.20755 22834 132086 -1 3131 12 959 959 74779 19366 1.56805 1.56805 -190.941 -1.56805 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0304292 0.0275916 193 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.70 vpr 61.73 MiB -1 -1 0.12 17344 1 0.03 -1 -1 29928 -1 -1 3 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63216 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 22.9 MiB 0.01 148 80 29 46 5 61.7 MiB 0.00 0.00 0.83871 -11.7447 -0.83871 0.83871 0.32 8.8927e-05 8.028e-05 0.000604437 0.000548194 -1 -1 -1 -1 20 230 8 6.65987e+06 38034 394039. 1363.46 0.25 0.00388017 0.00347642 20530 87850 -1 214 10 61 61 5414 1452 0.83871 0.83871 -11.8866 -0.83871 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0031468 0.00280409 14 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.72 vpr 61.69 MiB -1 -1 0.14 17312 1 0.02 -1 -1 29920 -1 -1 4 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63168 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 23.0 MiB 0.01 189 525 130 355 40 61.7 MiB 0.01 0.00 0.803048 -13.1363 -0.803048 0.803048 0.32 0.000104272 9.5105e-05 0.00233488 0.00212885 -1 -1 -1 -1 20 304 9 6.65987e+06 50712 394039. 1363.46 0.26 0.00586479 0.00523143 20530 87850 -1 282 10 105 105 8718 2335 0.83871 0.83871 -14.5944 -0.83871 0 0 477104. 1650.88 0.03 0.01 0.08 -1 -1 0.03 0.00378422 0.00342251 17 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.86 vpr 61.82 MiB -1 -1 0.13 17280 1 0.02 -1 -1 29868 -1 -1 5 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 23.4 MiB 0.01 147 1105 244 814 47 61.8 MiB 0.01 0.00 0.830189 -14.844 -0.830189 0.830189 0.33 0.00012577 0.000112704 0.00426613 0.00390409 -1 -1 -1 -1 26 305 15 6.65987e+06 63390 477104. 1650.88 0.34 0.0191538 0.0162467 21682 110474 -1 272 12 128 128 8327 2403 0.950389 0.950389 -16.4625 -0.950389 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00423977 0.00371064 20 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.02 vpr 61.80 MiB -1 -1 0.16 17392 1 0.02 -1 -1 30000 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63288 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.4 MiB 0.01 132 947 214 545 188 61.8 MiB 0.01 0.00 1.20253 -16.9819 -1.20253 1.20253 0.34 0.00014165 0.000130082 0.00397733 0.00363354 -1 -1 -1 -1 32 286 17 6.65987e+06 50712 554710. 1919.41 0.38 0.0203804 0.0172185 22834 132086 -1 207 12 103 103 5880 1787 0.856048 0.856048 -16.2356 -0.856048 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00468142 0.00409653 22 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.96 vpr 61.77 MiB -1 -1 0.14 17420 1 0.02 -1 -1 30048 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63256 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.4 MiB 0.02 169 1039 221 683 135 61.8 MiB 0.01 0.00 1.19636 -19.6785 -1.19636 1.19636 0.34 0.000160216 0.000147534 0.00392966 0.00362469 -1 -1 -1 -1 30 342 14 6.65987e+06 63390 526063. 1820.29 0.37 0.0217562 0.0183847 22546 126617 -1 290 13 143 143 7116 2212 0.823048 0.823048 -19.6378 -0.823048 0 0 666494. 2306.21 0.03 0.01 0.10 -1 -1 0.03 0.00533708 0.00464817 25 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.96 vpr 61.78 MiB -1 -1 0.10 17400 1 0.02 -1 -1 30056 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63264 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.3 MiB 0.02 158 1684 407 960 317 61.8 MiB 0.02 0.00 1.20736 -22.0789 -1.20736 1.20736 0.32 0.000176486 0.000162987 0.00597002 0.0055165 -1 -1 -1 -1 30 316 15 6.65987e+06 63390 526063. 1820.29 0.37 0.0258595 0.0220154 22546 126617 -1 281 20 183 183 9032 2990 1.07445 1.07445 -22.6488 -1.07445 0 0 666494. 2306.21 0.05 0.02 0.14 -1 -1 0.05 0.00796327 0.00683749 28 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.96 vpr 61.98 MiB -1 -1 0.14 17436 1 0.02 -1 -1 30148 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63472 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 335 1865 426 1314 125 62.0 MiB 0.02 0.00 1.21836 -28.0156 -1.21836 1.21836 0.32 0.000195988 0.000181389 0.00640653 0.00592412 -1 -1 -1 -1 26 555 11 6.65987e+06 76068 477104. 1650.88 0.35 0.0272629 0.0232932 21682 110474 -1 547 16 214 214 18567 4835 1.08545 1.08545 -31.2059 -1.08545 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00706697 0.00607694 31 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.03 vpr 62.06 MiB -1 -1 0.16 17404 1 0.02 -1 -1 30128 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63552 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.4 MiB 0.02 204 3498 1194 1551 753 62.1 MiB 0.03 0.00 1.22936 -27.6572 -1.22936 1.22936 0.32 0.000212462 0.000196166 0.0109339 0.0101005 -1 -1 -1 -1 30 454 21 6.65987e+06 88746 526063. 1820.29 0.39 0.0363204 0.0312013 22546 126617 -1 361 18 221 221 11264 3655 1.04739 1.04739 -26.9812 -1.04739 0 0 666494. 2306.21 0.03 0.02 0.10 -1 -1 0.03 0.00812448 0.00696129 35 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.99 vpr 61.94 MiB -1 -1 0.15 17252 1 0.02 -1 -1 29996 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63428 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 23.4 MiB 0.02 266 3244 1063 1597 584 61.9 MiB 0.03 0.00 1.24036 -31.1975 -1.24036 1.24036 0.32 0.000180091 0.000164931 0.00943785 0.00872483 -1 -1 -1 -1 28 564 34 6.65987e+06 101424 500653. 1732.36 0.43 0.046281 0.0393218 21970 115934 -1 503 13 227 227 15114 4347 1.14045 1.14045 -33.3649 -1.14045 0 0 612192. 2118.31 0.03 0.02 0.11 -1 -1 0.03 0.00698344 0.00607333 38 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.09 vpr 62.05 MiB -1 -1 0.15 17416 1 0.02 -1 -1 29976 -1 -1 9 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63544 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 23.4 MiB 0.02 267 4650 1648 2149 853 62.1 MiB 0.04 0.00 1.25136 -33.284 -1.25136 1.25136 0.32 0.000283328 0.000262351 0.0142241 0.0131692 -1 -1 -1 -1 32 627 21 6.65987e+06 114102 554710. 1919.41 0.42 0.0429261 0.0372136 22834 132086 -1 519 21 333 333 18881 5985 1.12945 1.12945 -35.2713 -1.12945 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0149715 0.0126565 41 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.07 vpr 61.92 MiB -1 -1 0.15 17644 1 0.02 -1 -1 29984 -1 -1 9 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63408 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 23.3 MiB 0.02 324 3518 788 2107 623 61.9 MiB 0.03 0.00 1.26236 -35.6797 -1.26236 1.26236 0.32 0.000253071 0.000234583 0.00979541 0.0090734 -1 -1 -1 -1 30 698 25 6.65987e+06 114102 526063. 1820.29 0.42 0.0425967 0.0366082 22546 126617 -1 520 15 327 327 17260 5451 1.02039 1.02039 -33.4205 -1.02039 0 0 666494. 2306.21 0.03 0.02 0.08 -1 -1 0.03 0.00850795 0.00740024 44 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.14 vpr 61.97 MiB -1 -1 0.16 17636 1 0.02 -1 -1 30264 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63460 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.3 MiB 0.02 363 4978 1495 2401 1082 62.0 MiB 0.04 0.00 1.62267 -39.2597 -1.62267 1.62267 0.32 0.000271456 0.000251613 0.0137065 0.0126797 -1 -1 -1 -1 28 787 18 6.65987e+06 114102 500653. 1732.36 0.43 0.0450106 0.0390537 21970 115934 -1 646 20 384 384 28172 7864 1.10039 1.10039 -40.1031 -1.10039 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0116488 0.010003 46 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.15 vpr 61.95 MiB -1 -1 0.15 17460 1 0.02 -1 -1 30056 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63440 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.3 MiB 0.02 358 6329 2576 3638 115 62.0 MiB 0.05 0.00 1.63367 -43.0819 -1.63367 1.63367 0.32 0.000297215 0.00027577 0.0173583 0.0161231 -1 -1 -1 -1 30 697 17 6.65987e+06 114102 526063. 1820.29 0.41 0.0506732 0.0443138 22546 126617 -1 563 18 309 309 15903 4551 0.975189 0.975189 -38.2274 -0.975189 0 0 666494. 2306.21 0.03 0.03 0.09 -1 -1 0.03 0.0107508 0.00928908 49 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.29 vpr 62.15 MiB -1 -1 0.17 17580 1 0.02 -1 -1 30004 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63640 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.3 MiB 0.03 395 6867 2582 3609 676 62.1 MiB 0.05 0.00 1.65567 -48.7086 -1.65567 1.65567 0.32 0.000325622 0.000302353 0.0174514 0.0161951 -1 -1 -1 -1 28 927 37 6.65987e+06 139458 500653. 1732.36 0.49 0.0658178 0.0568171 21970 115934 -1 701 14 374 374 29107 8630 1.23745 1.23745 -49.5635 -1.23745 0 0 612192. 2118.31 0.02 0.02 0.07 -1 -1 0.02 0.00594303 0.00527331 55 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.41 vpr 62.28 MiB -1 -1 0.12 17468 1 0.02 -1 -1 30460 -1 -1 13 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63772 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 23.0 MiB 0.03 491 9081 3707 5187 187 62.3 MiB 0.06 0.00 1.67767 -56.6155 -1.67767 1.67767 0.32 0.00035997 0.000334363 0.0218976 0.020333 -1 -1 -1 -1 30 1037 25 6.65987e+06 164814 526063. 1820.29 0.49 0.0667016 0.0582429 22546 126617 -1 743 15 369 369 22934 6790 1.02419 1.02419 -50.6361 -1.02419 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0117394 0.0102506 62 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 3.61 vpr 62.31 MiB -1 -1 0.11 17580 1 0.02 -1 -1 30308 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 23.1 MiB 0.03 499 10228 3488 4555 2185 62.3 MiB 0.06 0.00 1.69967 -61.5408 -1.69967 1.69967 0.32 0.000393075 0.000365679 0.0237597 0.0221074 -1 -1 -1 -1 30 1113 21 6.65987e+06 177492 526063. 1820.29 1.46 0.127983 0.11047 22546 126617 -1 863 16 593 593 46003 13579 1.18459 1.18459 -55.1595 -1.18459 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.0130362 0.0113889 68 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.71 vpr 62.41 MiB -1 -1 0.16 17728 1 0.02 -1 -1 30344 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.1 MiB 0.03 627 5353 1046 4033 274 62.4 MiB 0.04 0.00 2.07098 -70.3136 -2.07098 2.07098 0.32 0.000433307 0.000403645 0.0129451 0.0120394 -1 -1 -1 -1 32 1170 15 6.65987e+06 177492 554710. 1919.41 0.45 0.0588027 0.0514064 22834 132086 -1 1054 17 432 432 30738 8937 1.32345 1.32345 -69.7201 -1.32345 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0145867 0.0127516 73 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.29 vpr 62.52 MiB -1 -1 0.16 17584 1 0.04 -1 -1 30108 -1 -1 18 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64016 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 23.4 MiB 0.04 750 10596 2249 7776 571 62.5 MiB 0.07 0.00 2.11498 -85.1831 -2.11498 2.11498 0.31 0.000494895 0.000460975 0.0226536 0.02111 -1 -1 -1 -1 32 1479 15 6.65987e+06 228204 554710. 1919.41 0.47 0.0757256 0.0669986 22834 132086 -1 1199 18 520 520 35837 10747 1.36745 1.36745 -82.2692 -1.36745 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0174867 0.0153336 86 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.36 vpr 62.79 MiB -1 -1 0.14 17900 1 0.03 -1 -1 29940 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.2 MiB 0.04 1148 18135 6273 10055 1807 62.8 MiB 0.11 0.00 2.50829 -108.743 -2.50829 2.50829 0.31 0.000567141 0.000528695 0.0376235 0.035098 -1 -1 -1 -1 32 1762 17 6.65987e+06 240882 554710. 1919.41 0.48 0.101169 0.0902369 22834 132086 -1 1641 35 572 572 92037 50076 1.42045 1.42045 -99.1377 -1.42045 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.034255 0.0298774 97 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.76 vpr 62.72 MiB -1 -1 0.15 17948 1 0.04 -1 -1 30296 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64224 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.6 MiB 0.05 1644 32449 9393 19839 3217 62.7 MiB 0.19 0.00 3.38291 -180.76 -3.38291 3.38291 0.32 0.000880433 0.000823692 0.0609751 0.0571335 -1 -1 -1 -1 32 2858 35 6.65987e+06 367662 554710. 1919.41 0.66 0.183589 0.165605 22834 132086 -1 2422 21 853 853 74293 19928 1.63645 1.63645 -152.543 -1.63645 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0343826 0.0306978 145 2 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.04 vpr 63.06 MiB -1 -1 0.22 18240 1 0.04 -1 -1 30524 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.1 MiB 0.07 2278 49637 16106 29325 4206 63.1 MiB 0.32 0.01 4.25753 -269.84 -4.25753 4.25753 0.32 0.00119888 0.00112752 0.0868525 0.0816403 -1 -1 -1 -1 32 3524 24 6.65987e+06 494442 554710. 1919.41 0.71 0.239232 0.218193 22834 132086 -1 3207 15 1082 1082 88606 22556 1.61205 1.61205 -194.499 -1.61205 0 0 701300. 2426.64 0.03 0.09 0.13 -1 -1 0.03 0.0362035 0.0327639 193 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 1.77 vpr 62.61 MiB -1 -1 0.15 17432 1 0.02 -1 -1 30000 -1 -1 1 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64112 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 23.9 MiB 0.02 49 141 51 88 2 62.6 MiB 0.00 0.00 0.723895 -9.92304 -0.723895 0.723895 0.26 8.8052e-05 7.9849e-05 0.000999121 0.000908116 -1 -1 -1 -1 20 98 10 6.95648e+06 14475.7 414966. 1435.87 0.30 0.0111389 0.00932378 23170 95770 -1 97 7 39 39 2258 798 0.74674 0.74674 -9.97418 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00275107 0.00248696 7 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 1.90 vpr 62.60 MiB -1 -1 0.14 17416 1 0.02 -1 -1 29904 -1 -1 1 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 24.1 MiB 0.05 62 455 89 352 14 62.6 MiB 0.01 0.00 0.723895 -12.1764 -0.723895 0.723895 0.34 0.000105243 9.602e-05 0.00245462 0.00224036 -1 -1 -1 -1 20 159 11 6.95648e+06 14475.7 414966. 1435.87 0.28 0.006791 0.00608146 23170 95770 -1 135 8 71 71 4591 1516 0.74674 0.74674 -13.0356 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.10 -1 -1 0.02 0.00316305 0.00283131 8 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 1.98 vpr 62.57 MiB -1 -1 0.14 17264 1 0.02 -1 -1 29984 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64076 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 24.1 MiB 0.05 78 532 113 404 15 62.6 MiB 0.01 0.00 0.802432 -14.5369 -0.802432 0.802432 0.35 0.00012283 0.00011251 0.00266091 0.00244373 -1 -1 -1 -1 22 226 14 6.95648e+06 28951.4 443629. 1535.05 0.33 0.0192559 0.0165149 23458 102101 -1 200 12 93 93 4853 1733 1.04203 1.04203 -16.6837 -1.04203 0 0 531479. 1839.03 0.02 0.01 0.10 -1 -1 0.02 0.00425953 0.003729 10 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 1.92 vpr 62.76 MiB -1 -1 0.09 17224 1 0.03 -1 -1 30004 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.3 MiB 0.03 198 745 185 473 87 62.8 MiB 0.01 0.00 0.852632 -19.2076 -0.852632 0.852632 0.34 0.000140716 0.00012916 0.00337215 0.00309938 -1 -1 -1 -1 26 321 13 6.95648e+06 28951.4 503264. 1741.40 0.36 0.0195341 0.0165326 24322 120374 -1 321 11 126 126 8370 2235 1.09223 1.09223 -20.8791 -1.09223 0 0 618332. 2139.56 0.04 0.01 0.12 -1 -1 0.04 0.00464353 0.00415812 11 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.92 MiB -1 -1 0.15 17404 1 0.02 -1 -1 30132 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 24.4 MiB 0.03 223 1078 298 659 121 62.9 MiB 0.01 0.00 0.852632 -21.5769 -0.852632 0.852632 0.33 0.000157576 0.000145183 0.00461473 0.00425641 -1 -1 -1 -1 30 354 9 6.95648e+06 28951.4 556674. 1926.21 0.39 0.0212789 0.0180897 25186 138497 -1 308 12 127 127 6401 1953 0.959892 0.959892 -22.0373 -0.959892 0 0 706193. 2443.58 0.03 0.01 0.11 -1 -1 0.03 0.00509797 0.00446228 13 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 2.35 vpr 62.62 MiB -1 -1 0.16 17360 1 0.02 -1 -1 30072 -1 -1 4 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 24.1 MiB 0.02 137 2113 694 1199 220 62.6 MiB 0.02 0.00 0.852632 -22.0391 -0.852632 0.852632 0.33 0.000175963 0.000162527 0.0077691 0.00716049 -1 -1 -1 -1 34 351 30 6.95648e+06 57902.7 618332. 2139.56 0.63 0.045466 0.0380876 25762 151098 -1 282 21 287 287 12600 4481 1.08603 1.08603 -23.81 -1.08603 0 0 787024. 2723.27 0.05 0.03 0.14 -1 -1 0.05 0.00901771 0.00775726 15 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 2.12 vpr 62.77 MiB -1 -1 0.16 17304 1 0.03 -1 -1 30060 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 21 11 76 77 1 49 36 17 17 289 -1 unnamed_device 24.3 MiB 0.02 347 1157 244 770 143 62.8 MiB 0.01 0.00 0.896632 -29.3782 -0.896632 0.896632 0.34 0.000195865 0.000181237 0.00446093 0.00413933 -1 -1 -1 -1 32 570 14 6.95648e+06 57902.7 586450. 2029.24 0.45 0.0343905 0.0288988 25474 144626 -1 537 14 225 225 20970 4717 0.993732 0.993732 -31.9978 -0.993732 0 0 744469. 2576.02 0.03 0.02 0.10 -1 -1 0.03 0.00662926 0.0057376 17 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 2.48 vpr 62.92 MiB -1 -1 0.16 17280 1 0.02 -1 -1 30048 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64432 23 12 83 84 1 55 39 17 17 289 -1 unnamed_device 24.3 MiB 0.02 176 2481 826 1259 396 62.9 MiB 0.02 0.00 0.896632 -27.0337 -0.896632 0.896632 0.34 0.000210709 0.000195162 0.00860788 0.00797035 -1 -1 -1 -1 34 483 24 6.95648e+06 57902.7 618332. 2139.56 0.67 0.0520092 0.0437792 25762 151098 -1 363 22 394 394 26948 8701 1.04203 1.04203 -28.5778 -1.04203 0 0 787024. 2723.27 0.04 0.03 0.16 -1 -1 0.04 0.00958538 0.00817473 18 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 2.16 vpr 62.77 MiB -1 -1 0.15 17464 1 0.02 -1 -1 30040 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.1 MiB 0.02 224 1468 277 1132 59 62.8 MiB 0.02 0.00 0.918632 -30.5074 -0.918632 0.918632 0.34 0.000235964 0.000218668 0.00528816 0.00487691 -1 -1 -1 -1 28 585 18 6.95648e+06 72378.4 531479. 1839.03 0.42 0.0314017 0.026693 24610 126494 -1 522 14 291 291 16745 5276 1.13003 1.13003 -35.7088 -1.13003 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00737591 0.00639021 20 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 2.17 vpr 62.77 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30064 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 24.1 MiB 0.03 339 2916 911 1507 498 62.8 MiB 0.02 0.00 0.951632 -33.9905 -0.951632 0.951632 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 57 29 202 203 1 142 95 17 17 289 -1 unnamed_device 23.9 MiB 0.05 722 11543 4832 6610 101 63.3 MiB 0.07 0.00 1.47696 -83.7156 -1.47696 1.47696 0.33 0.000489569 0.000455061 0.0277562 0.0258156 -1 -1 -1 -1 38 1507 49 6.95648e+06 130281 678818. 2348.85 1.12 0.143453 0.125414 26626 170182 -1 1153 19 711 711 52152 13258 1.36523 1.36523 -83.7828 -1.36523 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0185791 0.0163538 44 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_032bits.v common 3.11 vpr 63.55 MiB -1 -1 0.09 17632 1 0.03 -1 -1 30176 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 24.0 MiB 0.08 866 16299 6958 9195 146 63.5 MiB 0.10 0.00 1.88129 -97.7109 -1.88129 1.88129 0.34 0.000573807 0.000535131 0.0384883 0.0358947 -1 -1 -1 -1 42 1631 39 6.95648e+06 130281 744469. 2576.02 1.15 0.166265 0.146237 27202 183097 -1 1355 16 747 747 71025 18381 1.44933 1.44933 -95.5906 -1.44933 0 0 949917. 3286.91 0.04 0.05 0.15 -1 -1 0.04 0.0188154 0.0166379 50 2 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 3.38 vpr 64.11 MiB -1 -1 0.18 17836 1 0.03 -1 -1 30336 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65644 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.3 MiB 0.11 1814 29672 12289 17319 64 64.1 MiB 0.18 0.00 2.41762 -170.667 -2.41762 2.41762 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/home/elgamma8/research/release/vtr-verilog-to-routing 64012 13 7 48 49 1 26 22 17 17 289 -1 unnamed_device 24.0 MiB 0.01 88 442 89 343 10 62.5 MiB 0.02 0.00 0.802432 -14.6238 -0.802432 0.802432 0.33 0.000416283 0.000382138 0.00349914 0.00321787 -1 -1 -1 -1 22 196 8 6.99608e+06 29431.4 443629. 1535.05 0.33 0.0164598 0.0139839 23458 102101 -1 190 12 106 106 6171 2132 0.793379 0.793379 -15.9608 -0.793379 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00429213 0.00376112 10 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 1.96 vpr 62.73 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30052 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.3 MiB 0.01 96 709 205 450 54 62.7 MiB 0.01 0.00 0.859432 -17.7199 -0.859432 0.859432 0.34 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21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 21 11 76 77 1 49 36 17 17 289 -1 unnamed_device 24.1 MiB 0.02 344 1393 312 877 204 62.5 MiB 0.02 0.00 0.857432 -28.7171 -0.857432 0.857432 0.36 0.000195901 0.000181275 0.00523369 0.00484884 -1 -1 -1 -1 26 610 16 6.99608e+06 58862.7 503264. 1741.40 0.40 0.0286559 0.0243167 24322 120374 -1 590 18 316 316 34564 7565 0.938732 0.938732 -31.4793 -0.938732 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00771615 0.00659605 17 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 2.14 vpr 62.64 MiB -1 -1 0.16 17396 1 0.03 -1 -1 30004 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64144 23 12 83 84 1 54 39 17 17 289 -1 unnamed_device 24.1 MiB 0.02 174 2481 746 1270 465 62.6 MiB 0.02 0.00 0.879432 -26.6557 -0.879432 0.879432 0.33 0.00021024 0.000194311 0.00857848 0.00793516 -1 -1 -1 -1 32 441 18 6.99608e+06 58862.7 586450. 2029.24 0.46 0.0332947 0.0284674 25474 144626 -1 372 12 266 266 17399 5603 0.993732 0.993732 -28.012 -0.993732 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00635172 0.00551661 18 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 2.13 vpr 62.57 MiB -1 -1 0.16 17196 1 0.02 -1 -1 30032 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 23.9 MiB 0.03 255 1618 324 1252 42 62.6 MiB 0.02 0.00 0.890432 -31.1278 -0.890432 0.890432 0.34 0.000224588 0.000208394 0.00581343 0.00537445 -1 -1 -1 -1 30 526 13 6.99608e+06 73578.4 556674. 1926.21 0.42 0.0313334 0.0268842 25186 138497 -1 496 10 236 236 16715 4353 0.99734 0.99734 -33.2379 -0.99734 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00608414 0.00533822 20 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 2.17 vpr 62.79 MiB -1 -1 0.16 17396 1 0.02 -1 -1 29940 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 24.2 MiB 0.02 266 2916 905 1615 396 62.8 MiB 0.02 0.00 0.912432 -33.5679 -0.912432 0.912432 0.34 0.000239142 0.000221307 0.00926954 0.00857757 -1 -1 -1 -1 30 707 44 6.99608e+06 73578.4 556674. 1926.21 0.45 0.0465126 0.039743 25186 138497 -1 505 16 384 384 27767 7373 1.11903 1.11903 -36.5295 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30304 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64232 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.0 MiB 0.03 331 4514 1860 2555 99 62.7 MiB 0.03 0.00 1.29476 -39.8517 -1.29476 1.29476 0.33 0.000271418 0.000251586 0.0135538 0.0125405 -1 -1 -1 -1 30 845 48 6.99608e+06 73578.4 556674. 1926.21 0.52 0.0569387 0.0488876 25186 138497 -1 616 19 462 462 34517 8954 1.11703 1.11703 -42.4939 -1.11703 0 0 706193. 2443.58 0.03 0.03 0.12 -1 -1 0.03 0.0108951 0.00939784 24 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 2.18 vpr 62.88 MiB -1 -1 0.09 17568 1 0.02 -1 -1 30068 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64384 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 24.1 MiB 0.03 328 4735 1886 2806 43 62.9 MiB 0.04 0.00 1.31676 -42.6858 -1.31676 1.31676 0.33 0.000291739 0.000270454 0.0141016 0.0130776 -1 -1 -1 -1 30 805 33 6.99608e+06 73578.4 556674. 1926.21 0.49 0.053817 0.046524 25186 138497 -1 641 16 399 399 31520 8272 1.15003 1.15003 -44.2826 -1.15003 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0101561 0.00881561 25 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_018bits.v common 2.07 vpr 62.99 MiB -1 -1 0.13 17664 1 0.03 -1 -1 30056 -1 -1 5 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 24.3 MiB 0.03 364 6541 2695 3784 62 63.0 MiB 0.02 0.00 1.33876 -49.2921 -1.33876 1.33876 0.26 0.000154524 0.000136787 0.00893174 0.00815638 -1 -1 -1 -1 32 939 42 6.99608e+06 73578.4 586450. 2029.24 0.51 0.05855 0.049823 25474 144626 -1 693 12 368 368 26349 7167 1.17203 1.17203 -49.9105 -1.17203 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.00929189 0.00813969 28 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 2.35 vpr 62.70 MiB -1 -1 0.16 17492 1 0.02 -1 -1 30308 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64208 41 21 146 147 1 94 67 17 17 289 -1 unnamed_device 23.7 MiB 0.03 407 6867 2751 4056 60 62.7 MiB 0.05 0.00 1.34976 -54.4321 -1.34976 1.34976 0.33 0.000360265 0.000334878 0.0193038 0.0179451 -1 -1 -1 -1 32 961 35 6.99608e+06 73578.4 586450. 2029.24 0.57 0.0697677 0.0606438 25474 144626 -1 756 15 428 428 30944 8363 1.24903 1.24903 -58.4693 -1.24903 0 0 744469. 2576.02 0.04 0.03 0.12 -1 -1 0.04 0.0117671 0.0102516 31 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 2.27 vpr 62.82 MiB -1 -1 0.16 17528 1 0.03 -1 -1 30348 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64332 45 23 160 161 1 107 74 17 17 289 -1 unnamed_device 23.7 MiB 0.04 530 7514 3084 4380 50 62.8 MiB 0.05 0.00 1.37176 -61.8029 -1.37176 1.37176 0.33 0.000390883 0.000363367 0.0200903 0.0186905 -1 -1 -1 -1 30 1126 15 6.99608e+06 88294.1 556674. 1926.21 0.48 0.0628619 0.0552343 25186 138497 -1 855 18 558 558 40666 10320 1.16968 1.16968 -63.7857 -1.16968 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.014469 0.0126338 34 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 2.94 vpr 63.00 MiB -1 -1 0.14 17580 1 0.02 -1 -1 30244 -1 -1 8 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64512 49 25 174 175 1 118 82 17 17 289 -1 unnamed_device 23.8 MiB 0.04 521 10228 4171 5954 103 63.0 MiB 0.07 0.00 1.39376 -67.8066 -1.39376 1.39376 0.33 0.000422838 0.000393319 0.0255703 0.0237972 -1 -1 -1 -1 34 1390 34 6.99608e+06 117725 618332. 2139.56 1.09 0.117769 0.102435 25762 151098 -1 986 29 736 736 98243 38158 1.36333 1.36333 -70.765 -1.36333 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0224734 0.0194537 38 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 3.07 vpr 63.10 MiB -1 -1 0.16 17624 1 0.03 -1 -1 30008 -1 -1 9 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 57 29 202 203 1 141 95 17 17 289 -1 unnamed_device 23.7 MiB 0.05 724 11543 4737 6716 90 63.1 MiB 0.07 0.00 1.44876 -82.7694 -1.44876 1.44876 0.34 0.000487581 0.000453293 0.0278211 0.0258836 -1 -1 -1 -1 38 1462 37 6.99608e+06 132441 678818. 2348.85 1.07 0.136751 0.119606 26626 170182 -1 1129 17 624 624 44907 12336 1.24188 1.24188 -80.687 -1.24188 0 0 902133. 3121.57 0.03 0.04 0.14 -1 -1 0.03 0.0169488 0.0148993 44 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 3.01 vpr 63.09 MiB -1 -1 0.10 17544 1 0.03 -1 -1 30048 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 23.7 MiB 0.05 873 16299 6945 9215 139 63.1 MiB 0.10 0.00 1.85309 -97.7499 -1.85309 1.85309 0.34 0.000588436 0.000549662 0.0383991 0.0358314 -1 -1 -1 -1 40 1590 25 6.99608e+06 132441 706193. 2443.58 1.10 0.154029 0.135738 26914 176310 -1 1430 16 781 781 64746 16342 1.32403 1.32403 -95.1334 -1.32403 0 0 926341. 3205.33 0.04 0.05 0.14 -1 -1 0.04 0.0186641 0.0164658 50 2 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 3.65 vpr 63.71 MiB -1 -1 0.17 17844 1 0.03 -1 -1 30352 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65236 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.0 MiB 0.08 1811 29672 12269 17337 66 63.7 MiB 0.18 0.00 2.38942 -170.114 -2.38942 2.38942 0.33 0.000881923 0.00082713 0.0624841 0.0585536 -1 -1 -1 -1 44 2886 50 6.99608e+06 206020 787024. 2723.27 1.45 0.277812 0.249067 27778 195446 -1 2550 19 1048 1048 107084 28330 1.70033 1.70033 -166.464 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31964 -1 -1 1 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63244 9 5 28 33 1 16 15 17 17 289 -1 unnamed_device 23.0 MiB 0.01 54 141 47 92 2 61.8 MiB 0.00 0.00 0.883748 -10.0813 -0.883748 0.883748 0.33 8.5414e-05 7.7314e-05 0.000966256 0.000875122 -1 -1 -1 -1 20 116 6 6.79088e+06 13472 414966. 1435.87 0.29 0.0100954 0.00839297 22510 95286 -1 96 7 35 35 1420 501 0.883748 0.883748 -9.8435 -0.883748 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00269658 0.00243975 8 6 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_005bits.v common 1.90 vpr 61.89 MiB -1 -1 0.14 17340 2 0.07 -1 -1 31884 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63376 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 23.2 MiB 0.01 78 394 86 293 15 61.9 MiB 0.01 0.00 1.02368 -13.4328 -1.02368 1.02368 0.36 0.000106267 9.6689e-05 0.00206803 0.0018958 -1 -1 -1 -1 22 194 10 6.79088e+06 26944 443629. 1535.05 0.32 0.0137002 0.0115006 22798 101617 -1 190 9 83 96 4150 1453 1.02368 1.02368 -14.6764 -1.02368 0 0 531479. 1839.03 0.03 0.01 0.09 -1 -1 0.03 0.00336983 0.00298904 10 7 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_006bits.v common 1.81 vpr 61.99 MiB -1 -1 0.15 17184 3 0.06 -1 -1 31848 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 23.3 MiB 0.01 103 562 132 416 14 62.0 MiB 0.01 0.00 1.14898 -15.8855 -1.14898 1.14898 0.33 5.793e-05 5.1492e-05 0.00140278 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0.00452381 13 10 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_008bits.v common 2.16 vpr 61.95 MiB -1 -1 0.16 17260 3 0.06 -1 -1 31924 -1 -1 4 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63432 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 23.5 MiB 0.06 297 1272 281 862 129 61.9 MiB 0.02 0.00 1.56413 -26.212 -1.56413 1.56413 0.34 0.000175567 0.00016209 0.00553938 0.00510909 -1 -1 -1 -1 26 505 11 6.79088e+06 53888 503264. 1741.40 0.36 0.0254124 0.0215936 23662 119890 -1 454 9 113 140 9091 2260 1.31353 1.31353 -26.0895 -1.31353 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00473594 0.00420527 17 14 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_009bits.v common 2.16 vpr 61.99 MiB -1 -1 0.15 17304 4 0.06 -1 -1 31992 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 19 10 60 70 1 46 32 17 17 289 -1 unnamed_device 23.5 MiB 0.07 157 2582 733 1373 476 62.0 MiB 0.02 0.00 1.65028 -26.9205 -1.65028 1.65028 0.34 0.000185515 0.000170984 0.0102122 0.00942314 -1 -1 -1 -1 28 440 24 6.79088e+06 40416 531479. 1839.03 0.40 0.0336774 0.0287458 23950 126010 -1 341 14 189 208 10515 3869 1.68943 1.68943 -27.6328 -1.68943 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00634766 0.00548015 17 13 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_010bits.v common 2.09 vpr 62.10 MiB -1 -1 0.16 17224 4 0.06 -1 -1 31688 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63592 21 11 69 80 1 54 36 17 17 289 -1 unnamed_device 23.6 MiB 0.06 276 1275 269 996 10 62.1 MiB 0.01 0.00 1.56413 -30.7636 -1.56413 1.56413 0.33 0.000211308 0.000195146 0.00522765 0.00483659 -1 -1 -1 -1 22 697 22 6.79088e+06 53888 443629. 1535.05 0.40 0.0360258 0.0302982 22798 101617 -1 574 14 232 281 20802 5741 1.51379 1.51379 -32.6549 -1.51379 0 0 531479. 1839.03 0.02 0.02 0.09 -1 -1 0.02 0.00716795 0.00620991 21 17 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_011bits.v common 1.98 vpr 62.01 MiB -1 -1 0.17 17236 5 0.06 -1 -1 31940 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63496 23 12 76 88 1 60 39 17 17 289 -1 unnamed_device 23.5 MiB 0.06 263 1359 262 1083 14 62.0 MiB 0.02 0.00 1.90432 -34.8738 -1.90432 1.90432 0.33 0.000227626 0.0002106 0.00540807 0.00501505 -1 -1 -1 -1 26 598 16 6.79088e+06 53888 503264. 1741.40 0.38 0.0309708 0.026345 23662 119890 -1 529 13 222 264 13917 4200 1.85054 1.85054 -36.679 -1.85054 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00719778 0.00628971 23 19 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_012bits.v common 2.14 vpr 62.08 MiB -1 -1 0.16 17296 5 0.06 -1 -1 32124 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63568 25 13 83 96 1 65 42 17 17 289 -1 unnamed_device 23.5 MiB 0.10 302 2634 595 2020 19 62.1 MiB 0.02 0.00 1.85398 -39.4801 -1.85398 1.85398 0.33 0.000241404 0.000222109 0.00947024 0.00873055 -1 -1 -1 -1 26 756 25 6.79088e+06 53888 503264. 1741.40 0.42 0.0400931 0.0343115 23662 119890 -1 611 16 260 323 16466 4828 1.76444 1.76444 -40.3833 -1.76444 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00875305 0.00755852 24 21 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_013bits.v common 2.20 vpr 62.27 MiB -1 -1 0.16 17516 5 0.06 -1 -1 31696 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63764 27 14 91 105 1 70 46 17 17 289 -1 unnamed_device 23.7 MiB 0.08 305 1686 354 1296 36 62.3 MiB 0.02 0.00 2.15497 -44.1132 -2.15497 2.15497 0.33 0.00032784 0.000303874 0.00737664 0.00683614 -1 -1 -1 -1 30 642 13 6.79088e+06 67360 556674. 1926.21 0.41 0.0366048 0.0314193 24526 138013 -1 572 14 257 360 19230 5544 1.89323 1.89323 -42.6809 -1.89323 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0153646 0.0131766 28 24 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_014bits.v common 2.32 vpr 62.30 MiB -1 -1 0.17 17720 6 0.06 -1 -1 32036 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63792 29 15 95 110 1 77 49 17 17 289 -1 unnamed_device 23.7 MiB 0.07 324 3342 734 2532 76 62.3 MiB 0.03 0.00 2.42352 -48.7848 -2.42352 2.42352 0.34 0.000283292 0.000262432 0.0115124 0.0106785 -1 -1 -1 -1 26 904 32 6.79088e+06 67360 503264. 1741.40 0.48 0.0553618 0.0473417 23662 119890 -1 757 13 322 384 23522 6789 2.15502 2.15502 -49.648 -2.15502 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00885209 0.00771765 29 23 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_015bits.v common 2.30 vpr 62.27 MiB -1 -1 0.17 17660 6 0.06 -1 -1 32064 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63764 31 16 104 120 1 81 52 17 17 289 -1 unnamed_device 23.5 MiB 0.08 317 3641 1047 1889 705 62.3 MiB 0.03 0.00 2.28032 -49.0709 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63912 41 21 139 160 1 106 71 17 17 289 -1 unnamed_device 23.3 MiB 0.12 468 7517 1635 5720 162 62.4 MiB 0.05 0.00 2.82083 -73.4935 -2.82083 2.82083 0.33 0.000396816 0.000367611 0.0218575 0.0202429 -1 -1 -1 -1 28 1210 23 6.79088e+06 121248 531479. 1839.03 0.51 0.0709664 0.0619985 23950 126010 -1 993 14 403 544 32469 9290 2.64519 2.64519 -75.7719 -2.64519 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0126456 0.0111096 41 37 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_022bits.v common 2.55 vpr 62.49 MiB -1 -1 0.18 17636 9 0.07 -1 -1 31924 -1 -1 9 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 45 23 153 176 1 119 77 17 17 289 -1 unnamed_device 23.3 MiB 0.15 477 7086 2063 3975 1048 62.5 MiB 0.05 0.00 3.57268 -91.263 -3.57268 3.57268 0.36 0.000445506 0.0004138 0.0204716 0.0190194 -1 -1 -1 -1 32 1120 12 6.79088e+06 121248 586450. 2029.24 0.47 0.0666694 0.0586499 24814 144142 -1 908 9 364 474 24629 7210 3.27175 3.27175 -87.1614 -3.27175 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0105039 0.00938562 45 41 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_024bits.v common 2.58 vpr 62.59 MiB -1 -1 0.17 17684 10 0.08 -1 -1 31972 -1 -1 10 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64088 49 25 166 191 1 129 84 17 17 289 -1 unnamed_device 23.3 MiB 0.19 888 10149 2418 6579 1152 62.6 MiB 0.06 0.00 3.52584 -103.921 -3.52584 3.52584 0.33 0.000474217 0.000440445 0.028013 0.0260292 -1 -1 -1 -1 26 1697 15 6.79088e+06 134720 503264. 1741.40 0.43 0.0796154 0.0704286 23662 119890 -1 1585 14 501 640 47109 11368 3.40054 3.40054 -105.083 -3.40054 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.014678 0.0129495 49 44 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_028bits.v common 2.81 vpr 62.74 MiB -1 -1 0.20 17628 11 0.08 -1 -1 32024 -1 -1 12 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64244 57 29 198 227 1 154 98 17 17 289 -1 unnamed_device 23.3 MiB 0.23 831 11348 3274 6773 1301 62.7 MiB 0.07 0.00 4.16358 -130.313 -4.16358 4.16358 0.33 0.000571622 0.000532297 0.0308967 0.0287436 -1 -1 -1 -1 26 1812 27 6.79088e+06 161664 503264. 1741.40 0.54 0.104091 0.0917454 23662 119890 -1 1543 14 611 793 48973 13212 3.94874 3.94874 -129.41 -3.94874 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.0176699 0.0155753 57 56 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_032bits.v common 2.86 vpr 62.93 MiB -1 -1 0.20 17752 13 0.07 -1 -1 32144 -1 -1 11 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64436 65 33 224 257 1 172 109 17 17 289 -1 unnamed_device 23.4 MiB 0.21 818 8689 1747 6820 122 62.9 MiB 0.06 0.00 4.75448 -151.053 -4.75448 4.75448 0.33 0.000651059 0.000607364 0.0238685 0.0222369 -1 -1 -1 -1 30 1902 27 6.79088e+06 148192 556674. 1926.21 0.57 0.106315 0.0936834 24526 138013 -1 1542 15 621 853 49087 13080 4.45354 4.45354 -150.197 -4.45354 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0208553 0.018485 67 62 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_048bits.v common 3.47 vpr 63.47 MiB -1 -1 0.26 18060 19 0.10 -1 -1 32316 -1 -1 20 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64996 97 49 340 389 1 268 166 17 17 289 -1 unnamed_device 23.8 MiB 0.35 1595 32542 9530 19534 3478 63.5 MiB 0.17 0.00 6.87725 -295.573 -6.87725 6.87725 0.33 0.000987348 0.000922056 0.0729955 0.0681292 -1 -1 -1 -1 32 3045 22 6.79088e+06 269440 586450. 2029.24 0.63 0.194659 0.175474 24814 144142 -1 2743 18 968 1302 86378 21246 6.58745 6.58745 -293.066 -6.58745 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0363793 0.0325585 103 98 -1 -1 -1 -1 - fixed_k6_frac_N8_22nm.xml adder_064bits.v common 4.24 vpr 64.23 MiB -1 -1 0.16 18356 26 0.11 -1 -1 32464 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65776 129 65 453 518 1 344 218 17 17 289 -1 unnamed_device 24.5 MiB 0.57 1971 49998 15091 29566 5341 64.2 MiB 0.25 0.00 10.4784 -507.086 -10.4784 10.4784 0.33 0.00132893 0.00124528 0.106245 0.0993901 -1 -1 -1 -1 40 3524 26 6.79088e+06 323328 706193. 2443.58 1.34 0.392274 0.354177 26254 175826 -1 3188 13 1107 1495 97622 26410 9.85193 9.85193 -491.088 -9.85193 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0540559 0.0490496 131 131 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_004bits.v common 1.82 vpr 62.44 MiB -1 -1 0.10 17380 1 0.02 -1 -1 30064 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.6 MiB 0.04 79 296 89 204 3 62.4 MiB 0.01 0.00 0.789073 -10.6008 -0.789073 0.789073 0.34 8.7674e-05 7.9525e-05 0.00159518 0.00144518 -1 -1 -1 -1 20 151 10 6.87369e+06 27947.7 414966. 1435.87 0.28 0.00519648 0.00462685 23170 95770 -1 130 9 79 79 4463 1413 0.789073 0.789073 -11.1729 -0.789073 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00359292 0.00318991 10 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 1.97 vpr 62.37 MiB -1 -1 0.08 17400 1 0.02 -1 -1 29904 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63864 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 23.6 MiB 0.04 163 695 168 481 46 62.4 MiB 0.01 0.00 0.811073 -14.7125 -0.811073 0.811073 0.40 9.2581e-05 8.1117e-05 0.00258582 0.00229127 -1 -1 -1 -1 20 310 13 6.87369e+06 41921.5 414966. 1435.87 0.31 0.00683924 0.00597313 23170 95770 -1 289 11 141 141 13137 3115 1.05067 1.05067 -17.0701 -1.05067 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 24.2 MiB 0.05 134 1128 368 603 157 62.6 MiB 0.01 0.00 1.2044 -18.5156 -1.2044 1.2044 0.35 0.000154596 0.000139466 0.00453151 0.00408993 -1 -1 -1 -1 26 307 17 6.87369e+06 41921.5 503264. 1741.40 0.35 0.021363 0.0179662 24322 120374 -1 267 14 146 146 6496 2236 0.989373 0.989373 -20.3361 -0.989373 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00517942 0.0045165 16 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 1.99 vpr 62.28 MiB -1 -1 0.08 17312 1 0.02 -1 -1 29984 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63776 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.8 MiB 0.05 146 1877 632 931 314 62.3 MiB 0.02 0.00 1.2154 -21.3035 -1.2154 1.2154 0.34 0.000157735 0.000145122 0.00722208 0.00664584 -1 -1 -1 -1 26 297 13 6.87369e+06 41921.5 503264. 1741.40 0.37 0.0248125 0.0212051 24322 120374 -1 273 13 150 150 7334 2479 1.00037 1.00037 -22.2134 -1.00037 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00528613 0.0045942 19 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 2.16 vpr 62.50 MiB -1 -1 0.14 17120 1 0.02 -1 -1 30024 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63996 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 24.1 MiB 0.07 160 2332 796 1082 454 62.5 MiB 0.02 0.00 1.2264 -24.1787 -1.2264 1.2264 0.34 0.000175241 0.000161634 0.008706 0.00803815 -1 -1 -1 -1 32 327 12 6.87369e+06 41921.5 586450. 2029.24 0.41 0.0280777 0.0241535 25474 144626 -1 286 11 164 164 7398 2391 1.01137 1.01137 -24.7636 -1.01137 0 0 744469. 2576.02 0.04 0.01 0.12 -1 -1 0.04 0.00504681 0.00448936 20 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 2.07 vpr 62.51 MiB -1 -1 0.15 17260 1 0.02 -1 -1 30120 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.0 MiB 0.07 175 2101 728 1079 294 62.5 MiB 0.02 0.00 1.2374 -27.2124 -1.2374 1.2374 0.34 0.000193984 0.000179478 0.00761103 0.00704442 -1 -1 -1 -1 30 382 13 6.87369e+06 55895.4 556674. 1926.21 0.41 0.0291491 0.0249416 25186 138497 -1 293 13 196 196 9565 2925 1.01137 1.01137 -26.4753 -1.01137 0 0 706193. 2443.58 0.03 0.01 0.08 -1 -1 0.03 0.00399551 0.00355068 22 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_011bits.v common 2.24 vpr 62.55 MiB -1 -1 0.15 17412 1 0.02 -1 -1 30040 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 24.0 MiB 0.05 194 2488 794 1203 491 62.6 MiB 0.02 0.00 1.2484 -30.0694 -1.2484 1.2484 0.33 0.000210963 0.000194687 0.00835745 0.00773003 -1 -1 -1 -1 32 434 17 6.87369e+06 69869.2 586450. 2029.24 0.45 0.0313966 0.026865 25474 144626 -1 373 20 274 274 18397 5227 1.13667 1.13667 -31.3415 -1.13667 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0135594 0.0114399 24 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_012bits.v common 2.22 vpr 62.56 MiB -1 -1 0.16 17376 1 0.02 -1 -1 30204 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64060 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.0 MiB 0.06 241 3493 1152 1593 748 62.6 MiB 0.03 0.00 1.2594 -33.5756 -1.2594 1.2594 0.34 0.00022384 0.000206819 0.0111138 0.0102745 -1 -1 -1 -1 32 501 21 6.87369e+06 69869.2 586450. 2029.24 0.43 0.0379716 0.0326576 25474 144626 -1 425 8 199 199 11182 3603 0.989373 0.989373 -33.3362 -0.989373 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00518953 0.00458893 26 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 2.80 vpr 62.49 MiB -1 -1 0.15 17308 1 0.02 -1 -1 30232 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.9 MiB 0.06 240 2998 1051 1663 284 62.5 MiB 0.03 0.00 1.2773 -35.5756 -1.2773 1.2773 0.33 0.000246381 0.00022827 0.00947207 0.00876673 -1 -1 -1 -1 30 618 21 6.87369e+06 69869.2 556674. 1926.21 1.12 0.0733815 0.0616699 25186 138497 -1 480 17 350 350 21752 6218 1.04437 1.04437 -34.6874 -1.04437 0 0 706193. 2443.58 0.03 0.02 0.09 -1 -1 0.03 0.00875841 0.00753696 28 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.19 vpr 62.53 MiB -1 -1 0.16 17388 1 0.02 -1 -1 30104 -1 -1 7 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 23.9 MiB 0.07 310 4093 1402 1938 753 62.5 MiB 0.03 0.00 1.2814 -39.7439 -1.2814 1.2814 0.33 0.000252751 0.00023371 0.0117669 0.0108889 -1 -1 -1 -1 28 763 21 6.87369e+06 97816.9 531479. 1839.03 0.43 0.041926 0.0362437 24610 126494 -1 614 12 343 343 23714 6541 1.12567 1.12567 -40.5186 -1.12567 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00730899 0.00637495 31 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 2.29 vpr 62.38 MiB -1 -1 0.15 17576 1 0.02 -1 -1 30264 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63880 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.7 MiB 0.08 337 6389 2578 2834 977 62.4 MiB 0.05 0.00 1.65963 -43.635 -1.65963 1.65963 0.34 0.000271225 0.000250996 0.0184151 0.0170486 -1 -1 -1 -1 32 726 25 6.87369e+06 83843 586450. 2029.24 0.47 0.0547587 0.0475343 25474 144626 -1 583 15 400 400 26645 7674 1.12567 1.12567 -42.064 -1.12567 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.00894667 0.007769 32 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 2.23 vpr 62.55 MiB -1 -1 0.16 17600 1 0.02 -1 -1 30052 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64056 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.9 MiB 0.08 354 5727 2338 3295 94 62.6 MiB 0.04 0.00 1.66373 -46.576 -1.66373 1.66373 0.33 0.00029115 0.000269841 0.0164547 0.0152586 -1 -1 -1 -1 30 765 19 6.87369e+06 83843 556674. 1926.21 0.43 0.0498673 0.043428 25186 138497 -1 646 22 430 430 29960 8573 1.22267 1.22267 -46.6259 -1.22267 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0125804 0.0108044 35 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 2.21 vpr 62.46 MiB -1 -1 0.15 17420 1 0.02 -1 -1 30192 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 23.7 MiB 0.08 390 6188 2490 3601 97 62.5 MiB 0.04 0.00 1.68573 -53.5906 -1.68573 1.68573 0.33 0.000329317 0.000306042 0.0173699 0.0161432 -1 -1 -1 -1 30 851 16 6.87369e+06 97816.9 556674. 1926.21 0.44 0.0537216 0.0467985 25186 138497 -1 693 11 381 381 25789 7299 1.13037 1.13037 -51.5244 -1.13037 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0086009 0.00751161 38 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 2.36 vpr 62.71 MiB -1 -1 0.15 17564 1 0.02 -1 -1 30288 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64220 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.7 MiB 0.08 447 8134 3300 4657 177 62.7 MiB 0.06 0.00 1.70773 -60.3017 -1.70773 1.70773 0.33 0.00036247 0.000336699 0.0215112 0.0200033 -1 -1 -1 -1 32 937 23 6.87369e+06 111791 586450. 2029.24 0.50 0.0651527 0.0569837 25474 144626 -1 774 21 527 527 36101 10508 1.18067 1.18067 -56.9294 -1.18067 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0145839 0.0125579 42 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 2.78 vpr 62.66 MiB -1 -1 0.17 17644 1 0.03 -1 -1 30472 -1 -1 10 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 23.6 MiB 0.11 503 9208 3768 5283 157 62.7 MiB 0.06 0.00 1.72973 -67.8771 -1.72973 1.72973 0.33 0.000386869 0.00035906 0.02257 0.0209781 -1 -1 -1 -1 36 1109 22 6.87369e+06 139738 648988. 2245.63 0.82 0.0992719 0.0860563 26050 158493 -1 898 22 643 643 58388 16256 1.24467 1.24467 -62.8028 -1.24467 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0165817 0.0143669 47 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 2.34 vpr 62.91 MiB -1 -1 0.17 17604 1 0.02 -1 -1 30380 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.7 MiB 0.09 607 6023 1283 4464 276 62.9 MiB 0.05 0.00 2.11206 -76.1943 -2.11206 2.11206 0.33 0.000426528 0.000396958 0.0153869 0.0143251 -1 -1 -1 -1 32 1299 16 6.87369e+06 125765 586450. 2029.24 0.48 0.0620614 0.0543264 25474 144626 -1 1097 14 609 609 45524 12761 1.34167 1.34167 -75.6214 -1.34167 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0127044 0.0111413 51 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 2.41 vpr 62.80 MiB -1 -1 0.17 17660 1 0.03 -1 -1 30076 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.5 MiB 0.09 789 12307 2769 8813 725 62.8 MiB 0.08 0.00 2.15606 -94.5222 -2.15606 2.15606 0.33 0.000492644 0.000458135 0.0286183 0.0266446 -1 -1 -1 -1 32 1559 17 6.87369e+06 153712 586450. 2029.24 0.53 0.0833133 0.0738776 25474 144626 -1 1393 18 688 688 59523 16512 1.49997 1.49997 -95.1329 -1.49997 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0173005 0.0151701 58 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 2.57 vpr 63.14 MiB -1 -1 0.17 17576 1 0.03 -1 -1 30072 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.11 981 17205 4139 12245 821 63.1 MiB 0.11 0.00 2.56039 -112.802 -2.56039 2.56039 0.34 0.0005709 0.000533122 0.0389788 0.0363756 -1 -1 -1 -1 32 1799 22 6.87369e+06 167686 586450. 2029.24 0.56 0.106634 0.0949936 25474 144626 -1 1617 15 720 720 63562 16203 1.47797 1.47797 -105.078 -1.47797 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0173981 0.0153283 67 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 2.89 vpr 63.28 MiB -1 -1 0.15 17828 1 0.03 -1 -1 30264 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 24.0 MiB 0.12 1584 31076 9475 18689 2912 63.3 MiB 0.19 0.00 3.45705 -193.743 -3.45705 3.45705 0.34 0.0008684 0.000814632 0.0625391 0.0585774 -1 -1 -1 -1 32 3068 37 6.87369e+06 251529 586450. 2029.24 0.78 0.189406 0.170897 25474 144626 -1 2611 15 1093 1093 100501 26292 1.79097 1.79097 -171.802 -1.79097 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0264197 0.0236566 99 2 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 3.73 vpr 64.25 MiB -1 -1 0.22 18156 1 0.04 -1 -1 30548 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65796 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.5 MiB 0.14 1992 52618 19565 29996 3057 64.3 MiB 0.34 0.01 4.35372 -280.144 -4.35372 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63760 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 23.6 MiB 0.05 133 1044 310 591 143 62.3 MiB 0.01 0.00 0.833073 -15.9272 -0.833073 0.833073 0.34 0.000124785 0.000114174 0.00422947 0.00386489 -1 -1 -1 -1 26 290 13 6.89349e+06 56375.4 503264. 1741.40 0.36 0.0182724 0.0154763 24322 120374 -1 221 12 125 125 5631 2000 0.94932 0.94932 -16.2556 -0.94932 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.0041284 0.00360823 15 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 2.07 vpr 62.25 MiB -1 -1 0.09 17396 1 0.03 -1 -1 30132 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 23.8 MiB 0.04 133 1204 333 631 240 62.2 MiB 0.01 0.00 1.2044 -18.4031 -1.2044 1.2044 0.34 0.000139573 0.000128145 0.0049121 0.00451093 -1 -1 -1 -1 32 295 12 6.89349e+06 42281.5 586450. 2029.24 0.41 0.0205912 0.0174698 25474 144626 -1 203 14 129 129 5391 1760 0.853073 0.853073 -17.6358 -0.853073 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00488954 0.00422668 16 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 1.99 vpr 62.19 MiB -1 -1 0.15 17216 1 0.02 -1 -1 29988 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63680 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.7 MiB 0.05 147 1877 621 864 392 62.2 MiB 0.02 0.00 1.2154 -21.3086 -1.2154 1.2154 0.33 0.000157194 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0.03 0.01 0.10 -1 -1 0.03 0.0054245 0.00471594 20 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.13 vpr 62.29 MiB -1 -1 0.16 17316 1 0.02 -1 -1 30208 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63788 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 23.8 MiB 0.05 178 2101 697 1026 378 62.3 MiB 0.03 0.00 1.2374 -27.3972 -1.2374 1.2374 0.34 0.000272143 0.000242871 0.014502 0.0134048 -1 -1 -1 -1 26 398 15 6.89349e+06 56375.4 503264. 1741.40 0.41 0.0366146 0.031747 24322 120374 -1 357 12 211 211 13104 3962 1.00232 1.00232 -27.9123 -1.00232 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00586481 0.00508309 22 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 2.14 vpr 62.36 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30020 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63856 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 23.9 MiB 0.05 194 2488 804 1234 450 62.4 MiB 0.02 0.00 1.2484 -29.9141 -1.2484 1.2484 0.34 0.000209881 0.00019386 0.00831107 0.00768353 -1 -1 -1 -1 32 419 16 6.89349e+06 70469.2 586450. 2029.24 0.44 0.0369654 0.0314569 25474 144626 -1 365 14 187 187 12612 3522 1.15867 1.15867 -31.3059 -1.15867 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00694411 0.00599348 24 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 2.17 vpr 62.26 MiB -1 -1 0.16 17436 1 0.02 -1 -1 30088 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63756 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 23.7 MiB 0.05 217 3493 1104 1725 664 62.3 MiB 0.05 0.00 1.2594 -32.5677 -1.2594 1.2594 0.34 0.000304479 0.000281407 0.0209988 0.0194009 -1 -1 -1 -1 32 482 20 6.89349e+06 70469.2 586450. 2029.24 0.43 0.0482192 0.0420835 25474 144626 -1 389 12 280 280 15448 4965 1.02237 1.02237 -32.661 -1.02237 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00656711 0.00568522 26 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 2.48 vpr 62.37 MiB -1 -1 0.16 17368 1 0.02 -1 -1 30088 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63868 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.8 MiB 0.05 241 2998 936 1427 635 62.4 MiB 0.03 0.00 1.2704 -35.731 -1.2704 1.2704 0.34 0.000238318 0.000220139 0.00954251 0.00882072 -1 -1 -1 -1 36 554 23 6.89349e+06 70469.2 648988. 2245.63 0.68 0.0569241 0.0482567 26050 158493 -1 470 11 304 304 20930 6434 1.17597 1.17597 -35.5601 -1.17597 0 0 828058. 2865.25 0.03 0.02 0.15 -1 -1 0.03 0.00655121 0.00571957 28 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 2.30 vpr 62.49 MiB -1 -1 0.15 17252 1 0.03 -1 -1 30068 -1 -1 7 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 23.8 MiB 0.06 311 4093 1430 1919 744 62.5 MiB 0.03 0.00 1.2814 -39.6 -1.2814 1.2814 0.34 0.00025249 0.000233658 0.0117448 0.0108621 -1 -1 -1 -1 32 651 22 6.89349e+06 98656.9 586450. 2029.24 0.45 0.0440558 0.0379748 25474 144626 -1 546 15 298 298 20497 5584 0.96032 0.96032 -37.5765 -0.96032 0 0 744469. 2576.02 0.03 0.02 0.13 -1 -1 0.03 0.00837419 0.00725538 31 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.23 vpr 62.42 MiB -1 -1 0.16 17588 1 0.02 -1 -1 30232 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63916 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.7 MiB 0.07 342 6191 2383 2979 829 62.4 MiB 0.04 0.00 1.65273 -42.5434 -1.65273 1.65273 0.35 0.000272263 0.000252147 0.0177761 0.0164574 -1 -1 -1 -1 28 782 16 6.89349e+06 84563 531479. 1839.03 0.47 0.050838 0.0446254 24610 126494 -1 632 16 412 412 30562 8836 1.09932 1.09932 -43.4614 -1.09932 0 0 648988. 2245.63 0.03 0.03 0.11 -1 -1 0.03 0.00917276 0.00791503 32 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 2.23 vpr 62.59 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30196 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.9 MiB 0.07 355 5727 2349 2359 1019 62.6 MiB 0.04 0.00 1.66373 -46.554 -1.66373 1.66373 0.34 0.00029317 0.000271463 0.0164277 0.0152439 -1 -1 -1 -1 30 761 18 6.89349e+06 84563 556674. 1926.21 0.43 0.0452337 0.0395422 25186 138497 -1 615 14 322 322 20560 5635 1.13667 1.13667 -43.9673 -1.13667 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00900274 0.00782068 35 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 2.26 vpr 62.61 MiB -1 -1 0.15 17668 1 0.02 -1 -1 30096 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64116 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 24.0 MiB 0.07 391 6563 2630 3842 91 62.6 MiB 0.05 0.00 1.68573 -53.2796 -1.68573 1.68573 0.33 0.000328745 0.0003059 0.0180114 0.01674 -1 -1 -1 -1 30 836 17 6.89349e+06 98656.9 556674. 1926.21 0.44 0.0548421 0.0477938 25186 138497 -1 695 15 451 451 29891 8374 1.03337 1.03337 -49.3183 -1.03337 0 0 706193. 2443.58 0.03 0.03 0.13 -1 -1 0.03 0.0118554 0.0102459 38 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.36 vpr 62.61 MiB -1 -1 0.15 17628 1 0.02 -1 -1 30352 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.6 MiB 0.06 444 7702 3109 4434 159 62.6 MiB 0.05 0.00 1.70773 -59.9521 -1.70773 1.70773 0.33 0.000367369 0.000341624 0.0204269 0.0189835 -1 -1 -1 -1 32 990 21 6.89349e+06 112751 586450. 2029.24 0.51 0.0631649 0.0551747 25474 144626 -1 819 18 512 512 38144 10646 1.11467 1.11467 -55.3744 -1.11467 0 0 744469. 2576.02 0.06 0.04 0.12 -1 -1 0.06 0.0153282 0.0133693 42 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.91 vpr 62.58 MiB -1 -1 0.17 17744 1 0.02 -1 -1 30460 -1 -1 10 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 23.5 MiB 0.10 525 9208 3753 5295 160 62.6 MiB 0.06 0.00 1.72973 -67.5033 -1.72973 1.72973 0.34 0.000392949 0.000365341 0.0227959 0.0211971 -1 -1 -1 -1 38 1007 50 6.89349e+06 140938 678818. 2348.85 0.90 0.1159 0.10007 26626 170182 -1 870 15 498 498 29786 8882 1.34722 1.34722 -61.6964 -1.34722 0 0 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64564 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.6 MiB 0.08 791 11419 2578 8125 716 63.1 MiB 0.07 0.00 2.15606 -94.8463 -2.15606 2.15606 0.33 0.000485905 0.00045224 0.0262913 0.0244792 -1 -1 -1 -1 32 1495 15 6.89349e+06 155032 586450. 2029.24 0.50 0.0789967 0.0700395 25474 144626 -1 1370 17 655 655 52543 14035 1.33262 1.33262 -89.2547 -1.33262 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0163034 0.0142892 58 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.53 vpr 63.12 MiB -1 -1 0.17 17808 1 0.03 -1 -1 30108 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.09 986 17205 3974 12341 890 63.1 MiB 0.11 0.00 2.56039 -113.021 -2.56039 2.56039 0.33 0.000575876 0.000537719 0.0387672 0.0362165 -1 -1 -1 -1 30 1859 34 6.89349e+06 169126 556674. 1926.21 0.57 0.116327 0.103243 25186 138497 -1 1589 16 746 746 58837 14814 1.31532 1.31532 -101.149 -1.31532 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0180394 0.0158572 67 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.95 vpr 63.42 MiB -1 -1 0.17 17756 1 0.03 -1 -1 30288 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1569 31076 8349 20038 2689 63.4 MiB 0.19 0.00 3.45705 -193.838 -3.45705 3.45705 0.33 0.000873253 0.000818313 0.0625323 0.0585782 -1 -1 -1 -1 32 3055 34 6.89349e+06 253689 586450. 2029.24 0.75 0.184089 0.166063 25474 144626 -1 2514 15 1003 1003 86721 22065 1.69397 1.69397 -165.636 -1.69397 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0259565 0.0232087 99 2 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 3.51 vpr 63.59 MiB -1 -1 0.17 17944 1 0.03 -1 -1 30596 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.4 MiB 0.15 2051 53273 20114 30300 2859 63.6 MiB 0.35 0.01 4.35372 -281.486 -4.35372 4.35372 0.33 0.00119747 0.00112577 0.101104 0.0950117 -1 -1 -1 -1 34 3564 19 6.89349e+06 338252 618332. 2139.56 1.07 0.340154 0.308577 25762 151098 -1 3156 13 1279 1279 97169 24263 1.63107 1.63107 -202.647 -1.63107 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0325631 0.0294317 131 2 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.21 vpr 63.07 MiB -1 -1 0.08 17216 2 0.04 -1 -1 31888 -1 -1 2 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64584 9 5 28 33 1 17 16 17 17 289 -1 unnamed_device 24.4 MiB 0.00 206 58 316 70 231 15 63.1 MiB 0.00 0.00 1.16527 1.11131 -10.1426 -1.11131 1.11131 0.22 7.9062e-05 7.3069e-05 0.000978869 0.000858061 -1 -1 -1 -1 20 133 6 6.55708e+06 24110 394039. 1363.46 0.14 0.00272539 0.00244507 19870 87366 -1 140 6 54 66 3199 1154 0.991107 0.991107 -10.7779 -0.991107 0 0 477104. 1650.88 0.02 0.00 0.04 -1 -1 0.02 0.00168949 0.00155092 13 6 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.26 vpr 63.08 MiB -1 -1 0.07 17456 2 0.04 -1 -1 31896 -1 -1 2 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64592 11 6 34 40 1 20 19 17 17 289 -1 unnamed_device 24.8 MiB 0.01 235 165 169 43 125 1 63.1 MiB 0.00 0.00 1.15051 1.15051 -14.6176 -1.15051 1.15051 0.23 4.9826e-05 4.3461e-05 0.000576171 0.000516811 -1 -1 -1 -1 20 270 9 6.55708e+06 24110 394039. 1363.46 0.15 0.00298509 0.00268579 19870 87366 -1 254 5 41 49 3983 1060 1.15051 1.15051 -15.5478 -1.15051 0 0 477104. 1650.88 0.02 0.00 0.04 -1 -1 0.02 0.00178452 0.0016474 16 7 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.28 vpr 63.05 MiB -1 -1 0.07 17212 3 0.04 -1 -1 31752 -1 -1 3 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64560 13 7 41 48 1 27 23 17 17 289 -1 unnamed_device 24.4 MiB 0.01 288 154 503 122 377 4 63.0 MiB 0.00 0.00 1.59011 1.34971 -17.0626 -1.34971 1.34971 0.23 5.8081e-05 5.1278e-05 0.001237 0.00110407 -1 -1 -1 -1 20 256 9 6.55708e+06 36165 394039. 1363.46 0.15 0.00391025 0.00350799 19870 87366 -1 243 6 70 92 4668 1412 1.22951 1.22951 -17.2303 -1.22951 0 0 477104. 1650.88 0.02 0.01 0.04 -1 -1 0.02 0.00227019 0.00206149 19 9 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.31 vpr 62.96 MiB -1 -1 0.08 17216 3 0.04 -1 -1 31932 -1 -1 4 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64472 15 8 47 55 1 35 27 17 17 289 -1 unnamed_device 24.8 MiB 0.01 442 155 907 221 612 74 63.0 MiB 0.01 0.00 1.71231 1.23151 -18.0927 -1.23151 1.23151 0.22 6.8894e-05 6.1471e-05 0.0018756 0.00167021 -1 -1 -1 -1 22 378 12 6.55708e+06 48220 420624. 1455.45 0.18 0.010518 0.00892074 20158 92377 -1 337 10 122 167 8236 2616 1.23151 1.23151 -20.8181 -1.23151 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00276206 0.00248152 23 10 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.63 vpr 63.03 MiB -1 -1 0.08 17588 3 0.04 -1 -1 31864 -1 -1 6 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64544 17 9 56 65 1 37 32 17 17 289 -1 unnamed_device 24.3 MiB 0.01 481 161 1132 232 876 24 63.0 MiB 0.01 0.00 1.59011 1.34971 -21.5902 -1.34971 1.34971 0.27 8.0064e-05 7.1661e-05 0.00228018 0.00204205 -1 -1 -1 -1 20 272 12 6.55708e+06 72330 394039. 1363.46 0.40 0.0122381 0.01043 19870 87366 -1 284 12 131 162 7562 2867 1.34971 1.34971 -22.2403 -1.34971 0 0 477104. 1650.88 0.02 0.01 0.04 -1 -1 0.02 0.00331893 0.00293692 26 14 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.75 vpr 63.50 MiB -1 -1 0.08 17588 4 0.04 -1 -1 31948 -1 -1 6 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65028 19 10 60 70 1 46 35 17 17 289 -1 unnamed_device 24.8 MiB 0.01 653 226 1802 440 1080 282 63.5 MiB 0.01 0.00 2.19111 1.83817 -26.7688 -1.83817 1.83817 0.23 8.5661e-05 7.6544e-05 0.00313154 0.00280441 -1 -1 -1 -1 26 408 9 6.55708e+06 72330 477104. 1650.88 0.59 0.0215133 0.0180047 21022 109990 -1 393 12 175 252 11265 3487 1.79897 1.79897 -26.967 -1.79897 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00346704 0.00308223 29 13 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.75 vpr 63.50 MiB -1 -1 0.08 17212 4 0.04 -1 -1 32004 -1 -1 7 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 21 11 69 80 1 45 39 17 17 289 -1 unnamed_device 24.9 MiB 0.01 529 261 897 182 697 18 63.5 MiB 0.01 0.00 2.07857 1.95837 -30.8495 -1.95837 1.95837 0.23 9.6795e-05 8.6472e-05 0.00179586 0.00163169 -1 -1 -1 -1 24 511 10 6.55708e+06 84385 448715. 1552.65 0.60 0.0302311 0.0254077 20734 103517 -1 466 9 123 172 11308 3061 1.83817 1.83817 -31.9733 -1.83817 0 0 554710. 1919.41 0.02 0.01 0.05 -1 -1 0.02 0.00346504 0.0031259 33 17 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.67 vpr 63.26 MiB -1 -1 0.08 17600 5 0.04 -1 -1 32008 -1 -1 7 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64776 23 12 76 88 1 52 42 17 17 289 -1 unnamed_device 25.0 MiB 0.01 771 207 3930 1133 1983 814 63.3 MiB 0.01 0.00 2.7665 2.15756 -32.1287 -2.15756 2.15756 0.22 0.000103351 9.2568e-05 0.00623842 0.00560991 -1 -1 -1 -1 26 473 11 6.55708e+06 84385 477104. 1650.88 0.50 0.0314563 0.0266482 21022 109990 -1 432 10 170 219 11782 3614 1.91716 1.91716 -32.3688 -1.91716 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00374793 0.00337898 36 19 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.79 vpr 63.64 MiB -1 -1 0.08 17216 5 0.04 -1 -1 31832 -1 -1 8 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65172 25 13 83 96 1 61 46 17 17 289 -1 unnamed_device 24.8 MiB 0.01 904 221 1850 356 1231 263 63.6 MiB 0.01 0.00 3.1879 2.1433 -36.3224 -2.1433 2.1433 0.22 0.000113375 0.000102402 0.00306364 0.0027673 -1 -1 -1 -1 30 501 11 6.55708e+06 96440 526063. 1820.29 0.60 0.0373232 0.0313535 21886 126133 -1 359 12 213 299 9554 3461 2.0231 2.0231 -33.1408 -2.0231 0 0 666494. 2306.21 0.02 0.01 0.07 -1 -1 0.02 0.00428155 0.00383391 39 21 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.42 vpr 62.89 MiB -1 -1 0.09 17984 5 0.05 -1 -1 32040 -1 -1 10 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64396 27 14 91 105 1 72 51 17 17 289 -1 unnamed_device 24.4 MiB 0.01 838 348 2213 475 1505 233 62.9 MiB 0.01 0.00 2.93506 2.31696 -40.7652 -2.31696 2.31696 0.22 0.000126183 0.000114202 0.00358244 0.00324098 -1 -1 -1 -1 26 746 16 6.55708e+06 120550 477104. 1650.88 0.21 0.0192314 0.0165318 21022 109990 -1 623 11 208 325 14496 4355 2.1851 2.1851 -42.6532 -2.1851 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00488328 0.00438588 44 24 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.89 vpr 63.12 MiB -1 -1 0.09 17596 6 0.05 -1 -1 31452 -1 -1 10 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64640 29 15 95 110 1 74 54 17 17 289 -1 unnamed_device 24.2 MiB 0.02 840 494 1992 357 1549 86 63.1 MiB 0.01 0.00 3.04382 2.92362 -51.8434 -2.92362 2.92362 0.22 0.00013344 0.000121346 0.0032091 0.0029238 -1 -1 -1 -1 30 838 14 6.55708e+06 120550 526063. 1820.29 0.67 0.0390571 0.0329705 21886 126133 -1 758 10 229 373 18230 5006 2.76422 2.76422 -51.4947 -2.76422 0 0 666494. 2306.21 0.02 0.01 0.07 -1 -1 0.02 0.004325 0.00388466 46 23 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 1.69 vpr 62.89 MiB -1 -1 0.09 17396 6 0.05 -1 -1 32048 -1 -1 10 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64396 31 16 104 120 1 74 57 17 17 289 -1 unnamed_device 24.2 MiB 0.01 941 335 4635 1193 2485 957 62.9 MiB 0.02 0.00 2.87676 2.63636 -51.3629 -2.63636 2.63636 0.23 0.000147029 0.000133637 0.0069038 0.00628263 -1 -1 -1 -1 26 734 12 6.55708e+06 120550 477104. 1650.88 0.48 0.0402772 0.0344133 21022 109990 -1 632 11 267 356 20796 6731 2.63636 2.63636 -51.9456 -2.63636 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00551217 0.00494734 50 27 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.37 vpr 62.72 MiB -1 -1 0.09 17600 7 0.05 -1 -1 31796 -1 -1 10 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64228 33 17 112 129 1 80 60 17 17 289 -1 unnamed_device 24.1 MiB 0.02 916 393 2751 484 2197 70 62.7 MiB 0.01 0.00 3.08137 2.84722 -55.8943 -2.84722 2.84722 0.23 0.000153737 0.000139913 0.00434086 0.00396577 -1 -1 -1 -1 22 827 11 6.55708e+06 120550 420624. 1455.45 0.20 0.0220409 0.0190779 20158 92377 -1 736 10 230 311 16768 5148 2.75456 2.75456 -59.488 -2.75456 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00502704 0.00452521 54 30 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.93 vpr 63.90 MiB -1 -1 0.09 17592 7 0.05 -1 -1 32116 -1 -1 13 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65432 37 19 127 146 1 95 69 17 17 289 -1 unnamed_device 24.8 MiB 0.02 1059 482 6555 1850 3443 1262 63.9 MiB 0.02 0.00 3.04582 2.80542 -63.7105 -2.80542 2.80542 0.22 0.000169604 0.000153899 0.0087697 0.00797272 -1 -1 -1 -1 30 1039 14 6.55708e+06 156715 526063. 1820.29 0.68 0.0419468 0.0361873 21886 126133 -1 800 9 267 408 15759 4770 2.47236 2.47236 -60.7748 -2.47236 0 0 666494. 2306.21 0.02 0.01 0.06 -1 -1 0.02 0.00604123 0.00539192 63 35 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.47 vpr 63.06 MiB -1 -1 0.08 17600 8 0.05 -1 -1 32096 -1 -1 14 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64572 41 21 139 160 1 106 76 17 17 289 -1 unnamed_device 24.1 MiB 0.02 1429 658 5676 1327 3947 402 63.1 MiB 0.02 0.00 3.2211 3.08613 -77.565 -3.08613 3.08613 0.24 0.000189407 0.000172319 0.00739107 0.00673116 -1 -1 -1 -1 26 1251 14 6.55708e+06 168770 477104. 1650.88 0.24 0.0294767 0.0257743 21022 109990 -1 1145 12 324 447 27951 7208 3.03216 3.03216 -79.6098 -3.03216 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00654646 0.00591075 67 37 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.17 vpr 63.80 MiB -1 -1 0.08 17588 9 0.05 -1 -1 31900 -1 -1 15 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65328 45 23 153 176 1 107 83 17 17 289 -1 unnamed_device 24.8 MiB 0.02 1416 456 10163 2618 5720 1825 63.8 MiB 0.04 0.00 4.17308 3.86645 -84.2581 -3.86645 3.86645 0.22 0.000202671 0.000183892 0.0159514 0.0146405 -1 -1 -1 -1 28 1275 49 6.55708e+06 180825 500653. 1732.36 0.90 0.0844012 0.0736509 21310 115450 -1 934 13 398 597 29685 9964 3.49108 3.49108 -83.5456 -3.49108 0 0 612192. 2118.31 0.02 0.02 0.06 -1 -1 0.02 0.00778562 0.00700103 73 41 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 1.53 vpr 63.84 MiB -1 -1 0.09 17600 10 0.07 -1 -1 32116 -1 -1 15 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65368 49 25 166 191 1 117 89 17 17 289 -1 unnamed_device 24.8 MiB 0.02 1324 622 9989 3281 5614 1094 63.8 MiB 0.03 0.00 4.86274 4.50214 -102.635 -4.50214 4.50214 0.22 0.000219308 0.000199911 0.0145069 0.0133229 -1 -1 -1 -1 26 1316 13 6.55708e+06 180825 477104. 1650.88 0.25 0.0398474 0.0353994 21022 109990 -1 1132 10 385 534 31434 9087 4.26174 4.26174 -104.467 -4.26174 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00671496 0.00611543 78 44 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.03 vpr 63.82 MiB -1 -1 0.10 17980 11 0.06 -1 -1 32132 -1 -1 19 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65352 57 29 198 227 1 147 105 17 17 289 -1 unnamed_device 24.2 MiB 0.03 1865 897 17148 5241 9470 2437 63.8 MiB 0.05 0.00 5.5625 4.78174 -135.819 -4.78174 4.78174 0.23 0.000309161 0.000282212 0.0222296 0.020281 -1 -1 -1 -1 30 1478 13 6.55708e+06 229045 526063. 1820.29 0.73 0.0732923 0.0644039 21886 126133 -1 1381 11 414 566 31943 8321 4.56888 4.56888 -136.747 -4.56888 0 0 666494. 2306.21 0.03 0.02 0.06 -1 -1 0.03 0.00870588 0.00791114 93 56 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.08 vpr 64.13 MiB -1 -1 0.10 17984 13 0.06 -1 -1 32136 -1 -1 20 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 65 33 224 257 1 164 118 17 17 289 -1 unnamed_device 24.8 MiB 0.03 2133 854 18036 4497 11205 2334 64.1 MiB 0.05 0.00 5.63431 5.39391 -154.533 -5.39391 5.39391 0.22 0.000289186 0.000264153 0.0195316 0.0178613 -1 -1 -1 -1 26 1787 31 6.55708e+06 241100 477104. 1650.88 0.76 0.105328 0.0921709 21022 109990 -1 1574 16 579 808 44794 13734 5.29574 5.29574 -160.248 -5.29574 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.0113832 0.0102065 107 62 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.43 vpr 65.33 MiB -1 -1 0.11 17984 19 0.07 -1 -1 32452 -1 -1 35 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66896 97 49 340 389 1 260 181 17 17 289 -1 unnamed_device 25.6 MiB 0.05 3161 1513 25731 6373 16876 2482 65.3 MiB 0.07 0.00 8.66304 7.82925 -302.074 -7.82925 7.82925 0.22 0.000446882 0.0004115 0.0244123 0.0224224 -1 -1 -1 -1 28 3205 37 6.55708e+06 421925 500653. 1732.36 0.98 0.141672 0.125872 21310 115450 -1 2662 22 887 1263 95212 33089 7.49619 7.49619 -303.373 -7.49619 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0209549 0.0189331 165 98 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.87 vpr 65.39 MiB -1 -1 0.13 18368 26 0.09 -1 -1 32528 -1 -1 41 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 129 65 453 518 1 334 235 17 17 289 -1 unnamed_device 25.6 MiB 0.05 4103 1668 39331 9780 26838 2713 65.4 MiB 0.10 0.00 12.3513 11.4335 -501.015 -11.4335 11.4335 0.22 0.000599957 0.000554309 0.0352785 0.0325073 -1 -1 -1 -1 30 3050 20 6.55708e+06 494255 526063. 1820.29 0.33 0.110151 0.099848 21886 126133 -1 2684 10 776 1028 53642 15366 11.0729 11.0729 -490.306 -11.0729 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0206695 0.0190116 210 131 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.28 abc 29.74 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30452 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25344 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.26 abc 29.74 MiB -1 -1 0.07 17300 1 0.02 -1 -1 30452 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25444 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.30 abc 29.75 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30460 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24636 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.29 abc 29.81 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30524 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 10.64 abc 29.76 MiB -1 -1 0.08 17148 1 0.02 -1 -1 30472 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.28 abc 29.69 MiB -1 -1 0.08 17156 1 0.02 -1 -1 30400 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.28 abc 29.56 MiB -1 -1 0.06 17296 1 0.02 -1 -1 30272 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25484 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.28 abc 29.83 MiB -1 -1 0.07 17296 1 0.02 -1 -1 30548 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25484 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.29 abc 29.75 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30468 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24860 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.31 abc 29.76 MiB -1 -1 0.11 17256 1 0.02 -1 -1 30472 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25096 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.30 abc 29.76 MiB -1 -1 0.08 16948 1 0.02 -1 -1 30472 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25484 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.30 abc 29.75 MiB -1 -1 0.08 17208 1 0.02 -1 -1 30464 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25248 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.31 abc 29.73 MiB -1 -1 0.09 17540 1 0.02 -1 -1 30440 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25336 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.33 abc 29.90 MiB -1 -1 0.09 17300 1 0.02 -1 -1 30620 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25108 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.30 abc 29.87 MiB -1 -1 0.09 17536 1 0.02 -1 -1 30584 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.30 abc 29.95 MiB -1 -1 0.08 17136 1 0.02 -1 -1 30672 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.30 abc 29.95 MiB -1 -1 0.09 17300 1 0.02 -1 -1 30668 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25432 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.31 abc 29.82 MiB -1 -1 0.10 17684 1 0.02 -1 -1 30540 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.32 abc 29.70 MiB -1 -1 0.10 17684 1 0.02 -1 -1 30412 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25864 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.34 abc 29.71 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30428 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.35 abc 29.98 MiB -1 -1 0.11 18452 1 0.03 -1 -1 30704 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25480 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.30 abc 29.77 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30484 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25148 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.27 abc 29.72 MiB -1 -1 0.08 17296 1 0.02 -1 -1 30432 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24720 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.34 abc 29.74 MiB -1 -1 0.13 17300 1 0.02 -1 -1 30456 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24384 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.30 abc 29.75 MiB -1 -1 0.08 17676 1 0.02 -1 -1 30460 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24624 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 10.63 abc 29.17 MiB -1 -1 0.08 17296 1 0.02 -1 -1 29872 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24712 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.27 abc 29.11 MiB -1 -1 0.07 17156 1 0.02 -1 -1 29804 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25104 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.29 abc 29.55 MiB -1 -1 0.08 17540 1 0.02 -1 -1 30260 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25104 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.27 abc 29.81 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30524 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24716 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.27 abc 29.19 MiB -1 -1 0.07 17296 1 0.02 -1 -1 29892 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25104 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.30 abc 29.74 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30452 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25104 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.29 abc 29.73 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30444 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 9.32 abc 29.75 MiB -1 -1 0.08 17300 1 0.02 -1 -1 30464 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 10.36 abc 29.76 MiB -1 -1 0.08 17296 1 0.02 -1 -1 30472 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 8.29 abc 29.88 MiB -1 -1 0.08 16880 1 0.02 -1 -1 30592 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 7.28 abc 29.87 MiB -1 -1 0.10 17688 1 0.02 -1 -1 30584 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.27 abc 29.92 MiB -1 -1 0.08 17684 1 0.02 -1 -1 30636 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 6.31 abc 29.94 MiB -1 -1 0.11 17296 1 0.02 -1 -1 30660 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 24632 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.40 abc 29.85 MiB -1 -1 0.08 17680 1 0.02 -1 -1 30564 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 1.48 abc 29.79 MiB -1 -1 0.08 17680 1 0.03 -1 -1 30504 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.52 abc 29.88 MiB -1 -1 0.09 17684 1 0.03 -1 -1 30600 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25096 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.57 abc 29.95 MiB -1 -1 0.10 18068 1 0.03 -1 -1 30668 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 25100 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.26 vpr 63.81 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30424 -1 -1 3 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65340 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 25.2 MiB 0.01 238 83 479 97 369 13 63.8 MiB 0.00 0.00 1.07911 0.792048 -9.44301 -0.792048 0.792048 0.23 4.1383e-05 3.5744e-05 0.00119592 0.00104463 -1 -1 -1 -1 20 178 7 6.64007e+06 37674 394039. 1363.46 0.15 0.00330351 0.00295369 20530 87850 -1 166 9 50 50 2813 862 0.890248 0.890248 -11.0134 -0.890248 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00197542 0.00179352 14 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.27 vpr 63.45 MiB -1 -1 0.07 17284 1 0.02 -1 -1 30456 -1 -1 4 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64976 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 25.2 MiB 0.01 284 83 525 102 399 24 63.5 MiB 0.00 0.00 1.03642 0.803048 -11.7481 -0.803048 0.803048 0.23 4.9915e-05 4.3541e-05 0.00119267 0.00105305 -1 -1 -1 -1 20 207 16 6.64007e+06 50232 394039. 1363.46 0.15 0.00416514 0.00365116 20530 87850 -1 179 12 74 74 3381 1262 0.901248 0.901248 -13.0068 -0.901248 0 0 477104. 1650.88 0.02 0.01 0.06 -1 -1 0.02 0.0030862 0.00274485 17 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.46 vpr 63.47 MiB -1 -1 0.10 17288 1 0.02 -1 -1 30456 -1 -1 5 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64996 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 25.2 MiB 0.01 316 197 709 147 526 36 63.5 MiB 0.01 0.00 1.02974 0.825048 -16.3149 -0.825048 0.825048 0.24 5.757e-05 5.0851e-05 0.00154628 0.00138152 -1 -1 -1 -1 20 360 11 6.64007e+06 62790 394039. 1363.46 0.33 0.00741843 0.00641283 20530 87850 -1 333 9 104 104 7584 2093 1.06545 1.06545 -19.3327 -1.06545 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00229516 0.00206885 20 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.72 vpr 63.50 MiB -1 -1 0.08 17288 1 0.03 -1 -1 30444 -1 -1 4 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 25.2 MiB 0.01 380 241 747 123 590 34 63.5 MiB 0.01 0.00 1.30556 1.20253 -19.2264 -1.20253 1.20253 0.23 6.589e-05 5.8596e-05 0.00155102 0.00138614 -1 -1 -1 -1 26 408 8 6.64007e+06 50232 477104. 1650.88 0.57 0.019026 0.0157054 21682 110474 -1 377 11 93 93 6647 1593 0.943248 0.943248 -20.6462 -0.943248 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00274722 0.00246422 22 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.67 vpr 63.86 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30368 -1 -1 5 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65396 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 25.2 MiB 0.01 448 158 991 170 809 12 63.9 MiB 0.01 0.00 1.2443 1.19636 -19.9652 -1.19636 1.19636 0.23 7.3426e-05 6.5481e-05 0.00188453 0.00169911 -1 -1 -1 -1 26 294 8 6.64007e+06 62790 477104. 1650.88 0.51 0.0189528 0.0158979 21682 110474 -1 286 9 116 116 6005 2126 0.943248 0.943248 -20.7144 -0.943248 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00283558 0.00256151 25 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.48 vpr 63.48 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30472 -1 -1 5 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65008 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 25.2 MiB 0.01 540 167 1189 226 945 18 63.5 MiB 0.01 0.00 1.31656 1.20736 -22.026 -1.20736 1.20736 0.23 8.6108e-05 7.6919e-05 0.0023041 0.00208871 -1 -1 -1 -1 20 342 13 6.64007e+06 62790 394039. 1363.46 0.33 0.00978918 0.0084969 20530 87850 -1 302 9 109 109 4692 1639 1.07445 1.07445 -24.2422 -1.07445 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00314492 0.00284337 28 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.38 vpr 62.97 MiB -1 -1 0.08 17284 1 0.02 -1 -1 30528 -1 -1 6 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64480 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 24.5 MiB 0.02 588 250 1424 247 1152 25 63.0 MiB 0.01 0.00 1.53496 1.21836 -25.7297 -1.21836 1.21836 0.24 9.3886e-05 8.4894e-05 0.00269714 0.00244855 -1 -1 -1 -1 26 451 15 6.64007e+06 75348 477104. 1650.88 0.22 0.0156218 0.0133683 21682 110474 -1 439 12 142 142 8932 2498 0.976248 0.976248 -27.5487 -0.976248 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00423404 0.00375273 31 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.59 vpr 63.63 MiB -1 -1 0.09 17288 1 0.02 -1 -1 30448 -1 -1 7 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65156 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 24.8 MiB 0.01 694 363 2058 437 1445 176 63.6 MiB 0.01 0.00 1.45876 1.22936 -31.2131 -1.22936 1.22936 0.23 9.8803e-05 8.8687e-05 0.00322156 0.00291014 -1 -1 -1 -1 20 638 10 6.64007e+06 87906 394039. 1363.46 0.42 0.0137408 0.0118043 20530 87850 -1 598 12 201 201 13848 3537 0.987248 0.987248 -32.0351 -0.987248 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00375482 0.00333808 35 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.63 vpr 63.63 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30452 -1 -1 8 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65160 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 24.9 MiB 0.01 705 317 2014 346 1603 65 63.6 MiB 0.01 0.00 1.31656 1.24036 -30.9039 -1.24036 1.24036 0.23 0.000104565 9.4799e-05 0.00302151 0.0027464 -1 -1 -1 -1 22 629 14 6.64007e+06 100464 420624. 1455.45 0.49 0.0243249 0.0206114 20818 92861 -1 571 11 246 246 13610 4133 1.09645 1.09645 -34.3431 -1.09645 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.0038428 0.00342744 38 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.74 vpr 64.02 MiB -1 -1 0.11 17284 1 0.02 -1 -1 30468 -1 -1 9 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 25.2 MiB 0.01 776 319 2442 536 1861 45 64.0 MiB 0.01 0.00 1.36056 1.25136 -33.5834 -1.25136 1.25136 0.24 0.000111963 0.000101325 0.00345788 0.00313083 -1 -1 -1 -1 26 619 14 6.64007e+06 113022 477104. 1650.88 0.52 0.024544 0.0208915 21682 110474 -1 536 11 194 194 12865 3664 0.976248 0.976248 -34.5053 -0.976248 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00387396 0.00347062 41 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.85 vpr 63.66 MiB -1 -1 0.07 17284 1 0.02 -1 -1 30460 -1 -1 9 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65188 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 24.9 MiB 0.01 943 346 2825 562 2243 20 63.7 MiB 0.01 0.00 1.49176 1.26236 -35.9631 -1.26236 1.26236 0.23 0.000119374 0.000107263 0.00388458 0.00352004 -1 -1 -1 -1 32 650 14 6.64007e+06 113022 554710. 1919.41 0.68 0.0362657 0.0306325 22834 132086 -1 601 14 260 260 16740 4779 0.923248 0.923248 -35.7196 -0.923248 0 0 701300. 2426.64 0.03 0.01 0.07 -1 -1 0.03 0.00481042 0.00427476 44 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 1.77 vpr 63.59 MiB -1 -1 0.08 17032 1 0.02 -1 -1 30592 -1 -1 9 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65112 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 24.7 MiB 0.01 885 425 2624 463 2138 23 63.6 MiB 0.01 0.00 1.81907 1.62267 -41.2599 -1.62267 1.62267 0.27 0.000126365 0.000114358 0.0036587 0.00332959 -1 -1 -1 -1 26 824 14 6.64007e+06 113022 477104. 1650.88 0.56 0.0367738 0.0311986 21682 110474 -1 686 12 288 288 21074 5653 1.13845 1.13845 -42.187 -1.13845 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00463604 0.00415964 46 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.63 vpr 63.80 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30608 -1 -1 9 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65336 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 24.9 MiB 0.02 1007 336 2909 510 2379 20 63.8 MiB 0.01 0.00 2.11447 1.63367 -41.8152 -1.63367 1.63367 0.23 0.000134938 0.000122447 0.00404431 0.00367801 -1 -1 -1 -1 26 643 9 6.64007e+06 113022 477104. 1650.88 0.45 0.0344379 0.0292381 21682 110474 -1 628 11 262 262 16953 5824 1.14945 1.14945 -43.39 -1.14945 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00604138 0.00543869 49 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.43 vpr 64.22 MiB -1 -1 0.09 17288 1 0.02 -1 -1 30616 -1 -1 11 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65764 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 25.2 MiB 0.02 1092 631 6867 1848 4270 749 64.2 MiB 0.02 0.00 2.09247 1.65567 -54.3354 -1.65567 1.65567 0.23 0.000150516 0.000136788 0.00833076 0.00757099 -1 -1 -1 -1 30 954 13 6.64007e+06 138138 526063. 1820.29 0.25 0.0260082 0.0225915 22546 126617 -1 872 10 249 249 16176 4074 0.943248 0.943248 -49.4729 -0.943248 0 0 666494. 2306.21 0.03 0.01 0.07 -1 -1 0.03 0.00490753 0.00440461 55 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.73 vpr 64.02 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30008 -1 -1 13 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65560 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 24.9 MiB 0.01 1366 587 5289 1117 3980 192 64.0 MiB 0.02 0.00 2.26537 1.67767 -57.9414 -1.67767 1.67767 0.23 0.00016969 0.00015493 0.0063347 0.00577518 -1 -1 -1 -1 26 1002 14 6.64007e+06 163254 477104. 1650.88 0.57 0.0471084 0.0403237 21682 110474 -1 921 14 319 319 22239 6031 1.07325 1.07325 -54.9156 -1.07325 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00606186 0.00539542 62 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 1.93 vpr 64.08 MiB -1 -1 0.08 17668 1 0.02 -1 -1 30372 -1 -1 14 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 25.2 MiB 0.02 1511 689 9160 2319 6031 810 64.1 MiB 0.04 0.00 2.04927 1.69967 -64.4248 -1.69967 1.69967 0.24 0.000419429 0.000390405 0.0166561 0.0154299 -1 -1 -1 -1 26 1229 18 6.64007e+06 175812 477104. 1650.88 0.69 0.0630154 0.0552989 21682 110474 -1 1067 12 353 353 25032 6571 1.06425 1.06425 -60.7054 -1.06425 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00732666 0.00664302 68 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.04 vpr 64.16 MiB -1 -1 0.07 18056 1 0.02 -1 -1 30280 -1 -1 14 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65704 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 25.2 MiB 0.02 1533 741 8668 2003 6116 549 64.2 MiB 0.03 0.00 2.57476 2.07098 -72.0156 -2.07098 2.07098 0.25 0.000193021 0.000175805 0.010399 0.00949855 -1 -1 -1 -1 32 1140 10 6.64007e+06 175812 554710. 1919.41 0.75 0.0474016 0.0413394 22834 132086 -1 1085 11 316 316 21511 5658 1.08425 1.08425 -64.8593 -1.08425 0 0 701300. 2426.64 0.03 0.02 0.08 -1 -1 0.03 0.00775127 0.00697508 73 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 1.96 vpr 64.29 MiB -1 -1 0.09 17464 1 0.02 -1 -1 30488 -1 -1 18 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 25.1 MiB 0.02 1840 829 11816 2855 8450 511 64.3 MiB 0.04 0.00 2.53961 2.11498 -86.5248 -2.11498 2.11498 0.24 0.000227555 0.000207967 0.0135972 0.0124764 -1 -1 -1 -1 26 1605 40 6.64007e+06 226044 477104. 1650.88 0.66 0.078404 0.0685372 21682 110474 -1 1388 15 519 519 39851 10566 1.30145 1.30145 -82.4792 -1.30145 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00847999 0.00758602 86 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.25 vpr 64.41 MiB -1 -1 0.09 18056 1 0.02 -1 -1 30212 -1 -1 19 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 25.2 MiB 0.02 2275 1115 20995 6789 12723 1483 64.4 MiB 0.06 0.00 2.92192 2.50829 -107.042 -2.50829 2.50829 0.23 0.000269838 0.000239541 0.0200461 0.0182978 -1 -1 -1 -1 32 1796 15 6.64007e+06 238602 554710. 1919.41 0.92 0.107473 0.0944051 22834 132086 -1 1645 15 498 498 43978 10303 1.19105 1.19105 -92.1495 -1.19105 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.0090664 0.00813003 97 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 1.71 vpr 64.97 MiB -1 -1 0.09 17672 1 0.03 -1 -1 30496 -1 -1 29 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66532 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 25.2 MiB 0.03 2965 1459 32938 9485 20921 2532 65.0 MiB 0.10 0.00 3.61231 3.38291 -175.44 -3.38291 3.38291 0.23 0.000385243 0.000353671 0.0275764 0.0253627 -1 -1 -1 -1 30 2412 19 6.64007e+06 364182 526063. 1820.29 0.32 0.0742998 0.0669359 22546 126617 -1 2173 14 773 773 59114 15483 1.40705 1.40705 -136.475 -1.40705 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0130146 0.0118962 145 2 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.91 vpr 65.57 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30712 -1 -1 39 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67140 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 26.0 MiB 0.04 4074 2039 55365 18789 32218 4358 65.6 MiB 0.18 0.00 4.33373 4.25753 -263.369 -4.25753 4.25753 0.23 0.000546765 0.000505774 0.0441183 0.0408237 -1 -1 -1 -1 32 3283 17 6.64007e+06 489762 554710. 1919.41 0.39 0.116701 0.106346 22834 132086 -1 2968 14 1086 1086 74911 19841 1.69925 1.69925 -193.576 -1.69925 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0170589 0.0155872 193 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.30 vpr 63.25 MiB -1 -1 0.07 17284 1 0.02 -1 -1 30088 -1 -1 3 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64768 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 24.9 MiB 0.01 238 75 479 108 353 18 63.2 MiB 0.01 0.00 1.07911 0.781048 -9.33185 -0.781048 0.781048 0.25 9.357e-05 8.5036e-05 0.0024399 0.00220103 -1 -1 -1 -1 20 165 10 6.65987e+06 38034 394039. 1363.46 0.18 0.00483371 0.00434458 20530 87850 -1 139 11 76 76 3137 1197 0.781048 0.781048 -10.3022 -0.781048 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.0022405 0.00200965 14 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.26 vpr 62.95 MiB -1 -1 0.07 17280 1 0.02 -1 -1 30480 -1 -1 4 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64464 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 24.2 MiB 0.01 284 76 497 85 385 27 63.0 MiB 0.00 0.00 1.03642 0.803048 -11.5739 -0.803048 0.803048 0.23 5.1125e-05 4.4933e-05 0.00124173 0.00111098 -1 -1 -1 -1 20 201 10 6.65987e+06 50712 394039. 1363.46 0.15 0.00386556 0.0034642 20530 87850 -1 181 12 98 98 4502 1632 1.01045 1.01045 -12.8746 -1.01045 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00253061 0.00227035 17 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.58 vpr 63.66 MiB -1 -1 0.07 17284 1 0.02 -1 -1 29688 -1 -1 5 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65188 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 24.9 MiB 0.01 316 183 709 148 526 35 63.7 MiB 0.01 0.00 1.02974 0.814048 -15.1984 -0.814048 0.814048 0.23 5.689e-05 5.0305e-05 0.00165434 0.00147903 -1 -1 -1 -1 20 350 16 6.65987e+06 63390 394039. 1363.46 0.44 0.011756 0.00980949 20530 87850 -1 340 17 187 187 13401 3837 1.03245 1.03245 -17.987 -1.03245 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00334724 0.00293122 20 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.59 vpr 63.19 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30452 -1 -1 4 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64708 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 24.7 MiB 0.01 380 234 747 129 578 40 63.2 MiB 0.01 0.00 1.26156 1.17436 -18.6976 -1.17436 1.17436 0.23 7.043e-05 6.3138e-05 0.00157626 0.00141852 -1 -1 -1 -1 20 409 17 6.65987e+06 50712 394039. 1363.46 0.48 0.0115251 0.00969463 20530 87850 -1 399 16 176 176 12920 3525 1.00339 1.00339 -21.1595 -1.00339 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00358569 0.0031662 22 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.53 vpr 63.68 MiB -1 -1 0.07 17672 1 0.02 -1 -1 30380 -1 -1 5 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65204 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 24.9 MiB 0.01 448 159 847 154 684 9 63.7 MiB 0.01 0.00 1.2443 1.18536 -20.0261 -1.18536 1.18536 0.23 7.5018e-05 6.6775e-05 0.00195393 0.00177282 -1 -1 -1 -1 20 331 15 6.65987e+06 63390 394039. 1363.46 0.43 0.0112967 0.00955005 20530 87850 -1 327 14 169 169 9032 3063 1.12359 1.12359 -22.8425 -1.12359 0 0 477104. 1650.88 0.02 0.01 0.05 -1 -1 0.02 0.00363438 0.00321042 25 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.65 vpr 63.30 MiB -1 -1 0.09 16900 1 0.02 -1 -1 30436 -1 -1 5 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64820 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 24.5 MiB 0.01 540 151 1244 259 970 15 63.3 MiB 0.01 0.00 1.31656 1.19636 -21.7095 -1.19636 1.19636 0.23 8.204e-05 7.3735e-05 0.00227233 0.0020487 -1 -1 -1 -1 22 360 16 6.65987e+06 63390 420624. 1455.45 0.51 0.0229437 0.0193246 20818 92861 -1 325 15 201 201 10796 3958 1.03639 1.03639 -24.3988 -1.03639 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00394271 0.00345528 28 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.37 vpr 63.32 MiB -1 -1 0.08 16892 1 0.02 -1 -1 30556 -1 -1 6 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64840 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 24.4 MiB 0.01 588 210 1802 360 1418 24 63.3 MiB 0.01 0.00 1.53496 1.20736 -25.1457 -1.20736 1.20736 0.23 9.7396e-05 8.8372e-05 0.00306471 0.00276262 -1 -1 -1 -1 26 411 18 6.65987e+06 76068 477104. 1650.88 0.22 0.015302 0.0129969 21682 110474 -1 370 11 159 159 8428 2816 0.894189 0.894189 -25.5941 -0.894189 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00350927 0.00312858 31 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.64 vpr 63.44 MiB -1 -1 0.07 17528 1 0.02 -1 -1 30472 -1 -1 7 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64964 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 24.5 MiB 0.01 694 363 2058 427 1457 174 63.4 MiB 0.01 0.00 1.45876 1.21836 -31.2829 -1.21836 1.21836 0.28 9.8216e-05 8.8456e-05 0.00325418 0.00294842 -1 -1 -1 -1 20 621 11 6.65987e+06 88746 394039. 1363.46 0.45 0.0162828 0.0139309 20530 87850 -1 596 14 234 234 18112 4915 1.15659 1.15659 -34.2526 -1.15659 0 0 477104. 1650.88 0.02 0.01 0.06 -1 -1 0.02 0.00412277 0.00363109 35 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.54 vpr 63.44 MiB -1 -1 0.08 17672 1 0.02 -1 -1 29880 -1 -1 8 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64964 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 24.9 MiB 0.01 705 327 1850 317 1450 83 63.4 MiB 0.01 0.00 1.31656 1.22936 -31.4295 -1.22936 1.22936 0.23 0.000104692 9.4898e-05 0.00285057 0.00259403 -1 -1 -1 -1 26 585 13 6.65987e+06 101424 477104. 1650.88 0.43 0.0296487 0.0250953 21682 110474 -1 556 16 236 236 12670 3863 1.06939 1.06939 -34.3453 -1.06939 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00461984 0.00409 38 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.85 vpr 63.88 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30392 -1 -1 9 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65412 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 25.0 MiB 0.01 776 340 2350 468 1844 38 63.9 MiB 0.01 0.00 1.36056 1.24036 -33.3747 -1.24036 1.24036 0.23 0.000225576 0.000206722 0.00456996 0.00419136 -1 -1 -1 -1 26 667 29 6.65987e+06 114102 477104. 1650.88 0.62 0.0398003 0.0338321 21682 110474 -1 592 33 318 318 57453 37023 1.16759 1.16759 -37.1574 -1.16759 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.00798524 0.00687946 41 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.45 vpr 63.50 MiB -1 -1 0.08 17668 1 0.02 -1 -1 30324 -1 -1 9 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 24.9 MiB 0.01 943 326 3617 739 2832 46 63.5 MiB 0.02 0.00 1.49176 1.25136 -35.1959 -1.25136 1.25136 0.23 0.000117876 0.000106205 0.00908273 0.00834518 -1 -1 -1 -1 30 622 13 6.65987e+06 114102 526063. 1820.29 0.26 0.0265602 0.0232305 22546 126617 -1 537 10 180 180 8588 2556 0.911048 0.911048 -34.1663 -0.911048 0 0 666494. 2306.21 0.03 0.01 0.07 -1 -1 0.03 0.00399448 0.00360108 44 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 1.68 vpr 63.89 MiB -1 -1 0.07 17672 1 0.02 -1 -1 30600 -1 -1 9 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65428 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 24.9 MiB 0.01 885 432 2196 385 1786 25 63.9 MiB 0.01 0.00 1.81907 1.61167 -41.1187 -1.61167 1.61167 0.23 0.000132693 0.000120473 0.00315976 0.00287987 -1 -1 -1 -1 26 834 19 6.65987e+06 114102 477104. 1650.88 0.51 0.0356961 0.0302449 21682 110474 -1 705 14 317 317 23560 6250 1.17145 1.17145 -43.2536 -1.17145 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00504275 0.00448784 46 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.79 vpr 63.63 MiB -1 -1 0.07 17672 1 0.02 -1 -1 30592 -1 -1 9 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65156 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 24.5 MiB 0.01 1007 330 2909 508 2376 25 63.6 MiB 0.01 0.00 2.04847 1.62267 -41.4298 -1.62267 1.62267 0.23 0.000134295 0.00012209 0.00403098 0.00367535 -1 -1 -1 -1 26 681 18 6.65987e+06 114102 477104. 1650.88 0.64 0.0412286 0.0350424 21682 110474 -1 647 15 329 329 18779 6422 1.17145 1.17145 -44.3444 -1.17145 0 0 585099. 2024.56 0.02 0.01 0.06 -1 -1 0.02 0.00551528 0.00487629 49 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.74 vpr 63.64 MiB -1 -1 0.08 17280 1 0.02 -1 -1 30596 -1 -1 11 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65168 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 24.9 MiB 0.01 1092 639 7003 1923 4240 840 63.6 MiB 0.02 0.00 2.01041 1.64467 -53.6697 -1.64467 1.64467 0.25 0.000150212 0.000136199 0.00844271 0.007677 -1 -1 -1 -1 26 1009 16 6.65987e+06 139458 477104. 1650.88 0.49 0.048146 0.0409187 21682 110474 -1 950 11 341 341 27759 6824 1.07325 1.07325 -52.1893 -1.07325 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00698376 0.00620754 55 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.80 vpr 63.86 MiB -1 -1 0.10 17668 1 0.02 -1 -1 30592 -1 -1 13 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65396 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 24.5 MiB 0.01 1366 611 7027 1508 5176 343 63.9 MiB 0.03 0.00 2.18331 1.66667 -58.111 -1.66667 1.66667 0.24 0.000210513 0.000192155 0.0100442 0.00920189 -1 -1 -1 -1 28 1031 18 6.65987e+06 164814 500653. 1732.36 0.56 0.0544942 0.0468751 21970 115934 -1 951 15 335 335 22426 6142 1.04619 1.04619 -54.6103 -1.04619 0 0 612192. 2118.31 0.02 0.01 0.06 -1 -1 0.02 0.00651926 0.00581147 62 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 1.67 vpr 63.94 MiB -1 -1 0.09 17672 1 0.02 -1 -1 30652 -1 -1 14 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 24.5 MiB 0.01 1511 697 11296 3104 7159 1033 63.9 MiB 0.04 0.00 2.04927 1.68867 -64.2361 -1.68867 1.68867 0.34 0.000188214 0.000171549 0.0152014 0.0139715 -1 -1 -1 -1 30 1131 16 6.65987e+06 177492 526063. 1820.29 0.27 0.03732 0.0329728 22546 126617 -1 1055 14 400 400 26633 7013 1.13925 1.13925 -62.1121 -1.13925 0 0 666494. 2306.21 0.03 0.02 0.07 -1 -1 0.03 0.00667388 0.00597021 68 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 1.87 vpr 64.37 MiB -1 -1 0.08 17524 1 0.02 -1 -1 30472 -1 -1 14 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 24.9 MiB 0.02 1533 677 6913 1466 5163 284 64.4 MiB 0.02 0.00 2.57476 2.05998 -69.4146 -2.05998 2.05998 0.25 0.000192377 0.000174998 0.00763626 0.00696582 -1 -1 -1 -1 30 1189 15 6.65987e+06 177492 526063. 1820.29 0.64 0.0624134 0.0538212 22546 126617 -1 1060 16 417 417 26988 7388 1.18125 1.18125 -66.1732 -1.18125 0 0 666494. 2306.21 0.02 0.02 0.07 -1 -1 0.02 0.00762415 0.00679059 73 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.02 vpr 64.11 MiB -1 -1 0.09 17348 1 0.02 -1 -1 30536 -1 -1 18 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65644 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 24.9 MiB 0.02 1840 854 13768 3297 9746 725 64.1 MiB 0.05 0.00 2.47361 2.10398 -86.4997 -2.10398 2.10398 0.23 0.000223154 0.000204405 0.0189329 0.0174562 -1 -1 -1 -1 28 1546 18 6.65987e+06 228204 500653. 1732.36 0.74 0.0955569 0.084111 21970 115934 -1 1419 17 507 507 42865 11070 1.25239 1.25239 -80.7522 -1.25239 0 0 612192. 2118.31 0.02 0.02 0.06 -1 -1 0.02 0.00874457 0.00781608 86 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 1.71 vpr 64.25 MiB -1 -1 0.08 17668 1 0.02 -1 -1 30348 -1 -1 19 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 24.9 MiB 0.02 2275 1131 20995 7082 12088 1825 64.2 MiB 0.06 0.00 2.92192 2.49729 -107.815 -2.49729 2.49729 0.23 0.000269954 0.000247525 0.0201729 0.0184865 -1 -1 -1 -1 32 1743 15 6.65987e+06 240882 554710. 1919.41 0.29 0.0503597 0.0448846 22834 132086 -1 1620 14 569 569 45398 11707 1.21819 1.21819 -93.4248 -1.21819 0 0 701300. 2426.64 0.04 0.04 0.12 -1 -1 0.04 0.0141501 0.012611 97 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 1.77 vpr 65.01 MiB -1 -1 0.10 17840 1 0.03 -1 -1 30556 -1 -1 29 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66572 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 24.9 MiB 0.03 2965 1462 32449 8975 21210 2264 65.0 MiB 0.12 0.00 3.61231 3.37191 -174.437 -3.37191 3.37191 0.23 0.000459966 0.000422715 0.0326052 0.0300627 -1 -1 -1 -1 32 2473 14 6.65987e+06 367662 554710. 1919.41 0.34 0.0846952 0.0763662 22834 132086 -1 2267 29 841 841 81945 29869 1.75665 1.75665 -153.182 -1.75665 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0216654 0.0193591 145 2 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.97 vpr 65.41 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30724 -1 -1 39 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66976 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 26.0 MiB 0.03 4074 1915 54649 18722 31811 4116 65.4 MiB 0.18 0.00 4.32293 4.24653 -259.209 -4.24653 4.24653 0.23 0.00053656 0.000495434 0.0438384 0.040529 -1 -1 -1 -1 32 3348 36 6.65987e+06 494442 554710. 1919.41 0.44 0.136419 0.124283 22834 132086 -1 2938 16 1194 1194 86245 23562 1.69925 1.69925 -191.229 -1.69925 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0204713 0.0188238 193 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 1.71 vpr 64.13 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30164 -1 -1 1 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 25.2 MiB 0.02 186 45 267 64 189 14 64.1 MiB 0.00 0.00 0.942216 0.723895 -9.92048 -0.723895 0.723895 0.24 4.1269e-05 3.5581e-05 0.000857532 0.000748933 -1 -1 -1 -1 26 113 8 6.95648e+06 14475.7 503264. 1741.40 0.48 0.0145841 0.0120035 24322 120374 -1 105 4 30 30 1645 514 0.723895 0.723895 -10.6007 -0.723895 0 0 618332. 2139.56 0.03 0.01 0.08 -1 -1 0.03 0.00235455 0.00212702 7 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 1.49 vpr 64.07 MiB -1 -1 0.07 17292 1 0.02 -1 -1 30244 -1 -1 1 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65612 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 25.2 MiB 0.02 208 70 432 93 307 32 64.1 MiB 0.00 0.00 1.08519 0.701895 -12.2465 -0.701895 0.701895 0.25 4.9405e-05 4.3283e-05 0.00122396 0.00107876 -1 -1 -1 -1 18 161 11 6.95648e+06 14475.7 376052. 1301.22 0.30 0.00523097 0.00453765 22882 88689 -1 141 12 69 69 3460 1174 0.74674 0.74674 -13.0673 -0.74674 0 0 470940. 1629.55 0.02 0.01 0.05 -1 -1 0.02 0.00346806 0.00310217 8 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 1.52 vpr 64.15 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30304 -1 -1 2 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65688 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 25.6 MiB 0.02 291 81 682 180 493 9 64.1 MiB 0.01 0.00 1.08519 0.802432 -14.3707 -0.802432 0.802432 0.24 5.7337e-05 5.0675e-05 0.00163514 0.00145269 -1 -1 -1 -1 20 195 11 6.95648e+06 28951.4 414966. 1435.87 0.33 0.00618855 0.00536814 23170 95770 -1 179 10 70 70 3667 1262 0.74674 0.74674 -15.5357 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00276647 0.00248845 10 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 1.44 vpr 64.15 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30108 -1 -1 2 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 26.0 MiB 0.02 415 108 1105 286 650 169 64.2 MiB 0.01 0.00 1.32908 0.841632 -16.8874 -0.841632 0.841632 0.24 6.9614e-05 6.1942e-05 0.00236817 0.00210352 -1 -1 -1 -1 26 261 20 6.95648e+06 28951.4 503264. 1741.40 0.23 0.0118783 0.0100431 24322 120374 -1 194 17 182 182 7678 2912 1.17833 1.17833 -17.5037 -1.17833 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00353747 0.00310566 11 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.04 vpr 64.20 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30412 -1 -1 2 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 25.8 MiB 0.02 414 113 1330 462 761 107 64.2 MiB 0.01 0.00 1.08519 0.863632 -19.4655 -0.863632 0.863632 0.24 7.1492e-05 6.3673e-05 0.00271864 0.0024388 -1 -1 -1 -1 36 227 19 6.95648e+06 28951.4 648988. 2245.63 0.80 0.0273823 0.0226313 26050 158493 -1 204 24 240 240 9992 3588 0.960732 0.960732 -19.2807 -0.960732 0 0 828058. 2865.25 0.03 0.01 0.09 -1 -1 0.03 0.00475944 0.00413697 13 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 1.82 vpr 64.22 MiB -1 -1 0.07 17676 1 0.02 -1 -1 30504 -1 -1 4 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65760 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 26.0 MiB 0.01 576 162 1437 270 1089 78 64.2 MiB 0.01 0.00 1.21049 0.942216 -22.8893 -0.942216 0.942216 0.25 8.0589e-05 7.247e-05 0.00288505 0.00260561 -1 -1 -1 -1 28 407 14 6.95648e+06 57902.7 531479. 1839.03 0.62 0.0268499 0.0224668 24610 126494 -1 347 11 183 183 9263 3101 1.12523 1.12523 -26.3721 -1.12523 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00342604 0.00307793 15 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 1.86 vpr 64.23 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30580 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65776 21 11 76 77 1 49 36 17 17 289 -1 unnamed_device 26.0 MiB 0.01 520 184 2337 519 1327 491 64.2 MiB 0.02 0.00 1.24794 0.885632 -25.2091 -0.885632 0.885632 0.27 0.000211409 0.000196055 0.00901202 0.00834241 -1 -1 -1 -1 26 462 18 6.95648e+06 57902.7 503264. 1741.40 0.63 0.0323948 0.027762 24322 120374 -1 400 8 187 187 10890 3344 1.13623 1.13623 -29.2443 -1.13623 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00323174 0.00292301 17 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 1.83 vpr 64.69 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30460 -1 -1 4 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66244 23 12 83 84 1 55 39 17 17 289 -1 unnamed_device 26.0 MiB 0.01 534 277 1359 266 994 99 64.7 MiB 0.01 0.00 1.21049 0.896632 -29.2681 -0.896632 0.896632 0.24 0.000102723 9.3049e-05 0.00248701 0.00226248 -1 -1 -1 -1 26 624 17 6.95648e+06 57902.7 503264. 1741.40 0.62 0.0269366 0.0225295 24322 120374 -1 566 15 301 301 22333 5932 1.14723 1.14723 -34.2934 -1.14723 0 0 618332. 2139.56 0.02 0.02 0.07 -1 -1 0.02 0.00643446 0.005649 18 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 1.96 vpr 64.30 MiB -1 -1 0.08 17276 1 0.02 -1 -1 30472 -1 -1 5 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 26.0 MiB 0.01 605 254 1693 316 1360 17 64.3 MiB 0.01 0.00 1.21049 0.918632 -30.3075 -0.918632 0.918632 0.24 0.000103531 9.3425e-05 0.00284467 0.00258122 -1 -1 -1 -1 32 569 15 6.95648e+06 72378.4 586450. 2029.24 0.77 0.0325078 0.0272267 25474 144626 -1 506 14 285 285 22039 5984 1.22853 1.22853 -34.5992 -1.22853 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.00436826 0.00387944 20 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 1.82 vpr 64.32 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30468 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 26.0 MiB 0.01 744 314 2178 458 1695 25 64.3 MiB 0.01 0.00 1.21049 0.951632 -33.9892 -0.951632 0.951632 0.24 0.000114819 0.000103699 0.00366722 0.0033457 -1 -1 -1 -1 28 729 30 6.95648e+06 72378.4 531479. 1839.03 0.59 0.0449713 0.0380416 24610 126494 -1 631 18 403 403 32027 8373 1.22233 1.22233 -40.2654 -1.22233 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00544327 0.00480754 21 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 2.39 vpr 64.40 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30476 -1 -1 5 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 29 15 104 105 1 72 49 17 17 289 -1 unnamed_device 26.0 MiB 0.01 715 246 2719 848 1471 400 64.4 MiB 0.01 0.00 1.08519 0.951632 -35.364 -0.951632 0.951632 0.24 0.000119985 0.00010813 0.00428954 0.00389556 -1 -1 -1 -1 44 533 17 6.95648e+06 72378.4 787024. 2723.27 1.08 0.0446344 0.0377658 27778 195446 -1 386 18 374 374 20041 6339 1.17403 1.17403 -35.3751 -1.17403 0 0 997811. 3452.63 0.04 0.02 0.11 -1 -1 0.04 0.00650777 0.0057225 23 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 1.98 vpr 64.38 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30580 -1 -1 5 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 26.0 MiB 0.02 947 386 4223 898 3239 86 64.4 MiB 0.02 0.00 1.51236 1.33396 -39.9535 -1.33396 1.33396 0.25 0.000125213 0.000113182 0.00606356 0.00550845 -1 -1 -1 -1 32 807 18 6.95648e+06 72378.4 586450. 2029.24 0.72 0.0494094 0.0418264 25474 144626 -1 659 15 387 387 24365 6245 1.18923 1.18923 -44.8721 -1.18923 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.00532077 0.00472633 24 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_016bits.v common 1.92 vpr 63.99 MiB -1 -1 0.07 17292 1 0.02 -1 -1 30592 -1 -1 5 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65524 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 25.5 MiB 0.03 897 292 5359 1572 3749 38 64.0 MiB 0.02 0.00 1.42436 1.34496 -41.6298 -1.34496 1.34496 0.24 0.000146972 0.000133743 0.00895157 0.00818407 -1 -1 -1 -1 28 855 20 6.95648e+06 72378.4 531479. 1839.03 0.68 0.0429958 0.0368254 24610 126494 -1 680 15 441 441 27345 8654 1.25523 1.25523 -49.8608 -1.25523 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00570309 0.00508006 25 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_018bits.v common 1.59 vpr 64.45 MiB -1 -1 0.08 16972 1 0.02 -1 -1 30596 -1 -1 5 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 26.0 MiB 0.04 989 557 3661 811 2737 113 64.4 MiB 0.01 0.00 1.38402 1.36696 -53.7585 -1.36696 1.36696 0.24 0.000151196 0.000137918 0.0054351 0.00496446 -1 -1 -1 -1 32 984 16 6.95648e+06 72378.4 586450. 2029.24 0.28 0.0245897 0.0212458 25474 144626 -1 928 14 431 431 37485 8753 1.19403 1.19403 -57.1717 -1.19403 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00601895 0.00536247 28 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 2.18 vpr 64.49 MiB -1 -1 0.09 17292 1 0.02 -1 -1 30612 -1 -1 5 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 41 21 146 147 1 95 67 17 17 289 -1 unnamed_device 25.6 MiB 0.05 1132 525 3467 777 2624 66 64.5 MiB 0.01 0.00 1.51426 1.38896 -57.0848 -1.38896 1.38896 0.26 0.000165315 0.000150428 0.00501244 0.00458007 -1 -1 -1 -1 32 1043 16 6.95648e+06 72378.4 586450. 2029.24 0.86 0.0505249 0.043321 25474 144626 -1 950 14 459 459 34737 8669 1.26433 1.26433 -61.56 -1.26433 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00639534 0.00570402 31 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 2.13 vpr 64.66 MiB -1 -1 0.08 18056 1 0.02 -1 -1 30392 -1 -1 6 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 45 23 160 161 1 107 74 17 17 289 -1 unnamed_device 26.0 MiB 0.06 1395 720 9374 2928 5809 637 64.7 MiB 0.03 0.00 1.94326 1.41096 -67.4934 -1.41096 1.41096 0.24 0.000179143 0.000161835 0.0118445 0.0107473 -1 -1 -1 -1 32 1231 22 6.95648e+06 86854.1 586450. 2029.24 0.83 0.0574222 0.0494085 25474 144626 -1 1160 21 653 653 58712 13516 1.14573 1.14573 -69.9279 -1.14573 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00885175 0.00782168 34 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_024bits.v common 2.11 vpr 65.07 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30272 -1 -1 8 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 49 25 174 175 1 119 82 17 17 289 -1 unnamed_device 26.0 MiB 0.02 1602 875 11296 4663 6552 81 65.1 MiB 0.03 0.00 1.65536 1.43296 -76.7183 -1.43296 1.43296 0.24 0.000189893 0.000172131 0.0130603 0.0118943 -1 -1 -1 -1 30 1506 17 6.95648e+06 115805 556674. 1926.21 0.83 0.0582935 0.050607 25186 138497 -1 1370 17 571 571 54770 11916 1.28823 1.28823 -81.6474 -1.28823 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00827919 0.00738448 38 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_028bits.v common 2.09 vpr 64.95 MiB -1 -1 0.08 17524 1 0.02 -1 -1 30408 -1 -1 9 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 57 29 202 203 1 142 95 17 17 289 -1 unnamed_device 25.8 MiB 0.03 1871 751 14351 6043 8202 106 64.9 MiB 0.05 0.00 1.69936 1.47696 -84.2177 -1.47696 1.47696 0.26 0.00025281 0.000232884 0.0189336 0.0173294 -1 -1 -1 -1 36 1780 37 6.95648e+06 130281 648988. 2245.63 0.68 0.0738443 0.0650373 26050 158493 -1 1305 15 703 703 67106 17088 1.38723 1.38723 -87.9196 -1.38723 0 0 828058. 2865.25 0.03 0.02 0.08 -1 -1 0.03 0.00845282 0.00760553 44 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_032bits.v common 3.60 vpr 64.95 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30488 -1 -1 9 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66512 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 25.6 MiB 0.04 2158 934 16805 5000 11266 539 65.0 MiB 0.05 0.00 2.38249 1.88129 -98.7696 -1.88129 1.88129 0.24 0.000303935 0.000278354 0.0207064 0.0189746 -1 -1 -1 -1 38 1674 26 6.95648e+06 130281 678818. 2348.85 2.21 0.140338 0.12286 26626 170182 -1 1466 19 712 712 60228 14581 1.42923 1.42923 -101.586 -1.42923 0 0 902133. 3121.57 0.03 0.03 0.09 -1 -1 0.03 0.0124642 0.0111288 50 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 5.32 vpr 65.69 MiB -1 -1 0.09 18056 1 0.03 -1 -1 30676 -1 -1 14 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 26.0 MiB 0.05 3293 1259 31408 11237 18751 1420 65.7 MiB 0.12 0.00 3.01593 2.41762 -155.703 -2.41762 2.41762 0.24 0.000535888 0.000504263 0.0416623 0.0386032 -1 -1 -1 -1 44 2684 47 6.95648e+06 202660 787024. 2723.27 3.76 0.245906 0.220222 27778 195446 -1 1982 16 1061 1061 74106 21007 1.49803 1.49803 -146.918 -1.49803 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0198303 0.0181925 74 2 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 6.94 vpr 66.18 MiB -1 -1 0.11 18060 1 0.03 -1 -1 31072 -1 -1 19 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67772 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 26.7 MiB 0.07 3762 2182 38948 14587 22700 1661 66.2 MiB 0.13 0.00 3.20455 2.95395 -240.326 -2.95395 2.95395 0.26 0.000547665 0.000501165 0.0444461 0.0412839 -1 -1 -1 -1 50 3474 25 6.95648e+06 275038 902133. 3121.57 5.29 0.304726 0.275791 28642 213929 -1 3073 18 1288 1288 126497 27318 1.73803 1.73803 -210.594 -1.73803 0 0 1.08113e+06 3740.92 0.04 0.05 0.12 -1 -1 0.04 0.0218877 0.0200306 98 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_004bits.v common 1.76 vpr 63.88 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30452 -1 -1 1 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 25.2 MiB 0.01 186 45 267 64 194 9 63.9 MiB 0.01 0.00 0.942216 0.583992 -8.95387 -0.583992 0.583992 0.27 9.642e-05 8.6132e-05 0.00173469 0.00157219 -1 -1 -1 -1 26 120 11 6.99608e+06 14715.7 503264. 1741.40 0.55 0.0162204 0.0134467 24322 120374 -1 101 6 38 38 2806 921 0.62144 0.62144 -9.63407 -0.62144 0 0 618332. 2139.56 0.02 0.00 0.06 -1 -1 0.02 0.00190368 0.00176174 7 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_005bits.v common 1.53 vpr 63.97 MiB -1 -1 0.09 17280 1 0.02 -1 -1 30452 -1 -1 1 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65508 11 6 41 42 1 19 18 17 17 289 -1 unnamed_device 25.2 MiB 0.01 206 60 386 72 298 16 64.0 MiB 0.00 0.00 1.08519 0.688132 -11.7579 -0.688132 0.688132 0.24 4.9355e-05 4.3273e-05 0.00110663 0.000977756 -1 -1 -1 -1 20 177 10 6.99608e+06 14715.7 414966. 1435.87 0.36 0.0132997 0.0108769 23170 95770 -1 128 8 54 54 2540 835 0.688132 0.688132 -12.43 -0.688132 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00224508 0.00204327 8 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_006bits.v common 1.74 vpr 64.00 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30444 -1 -1 2 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65540 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 25.2 MiB 0.01 291 91 802 202 586 14 64.0 MiB 0.01 0.00 1.08519 0.791432 -14.38 -0.791432 0.791432 0.24 5.7432e-05 5.0618e-05 0.00186067 0.0016455 -1 -1 -1 -1 24 211 13 6.99608e+06 29431.4 470940. 1629.55 0.58 0.0141922 0.0118181 24034 113901 -1 186 9 62 62 4604 1471 0.74674 0.74674 -15.8342 -0.74674 0 0 586450. 2029.24 0.02 0.01 0.06 -1 -1 0.02 0.00248933 0.00225819 10 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 1.41 vpr 63.98 MiB -1 -1 0.07 17148 1 0.02 -1 -1 30384 -1 -1 2 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65520 15 8 55 56 1 31 25 17 17 289 -1 unnamed_device 25.2 MiB 0.01 413 101 1141 323 690 128 64.0 MiB 0.01 0.00 1.32908 0.813432 -17.1707 -0.813432 0.813432 0.24 6.8128e-05 6.0125e-05 0.00245567 0.00217768 -1 -1 -1 -1 26 236 14 6.99608e+06 29431.4 503264. 1741.40 0.24 0.0112923 0.00955798 24322 120374 -1 213 10 123 123 5123 1883 1.05303 1.05303 -17.8815 -1.05303 0 0 618332. 2139.56 0.02 0.01 0.07 -1 -1 0.02 0.00287929 0.00258091 11 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 2.02 vpr 63.92 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30296 -1 -1 2 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65456 17 9 62 63 1 36 28 17 17 289 -1 unnamed_device 25.2 MiB 0.01 412 114 1036 306 641 89 63.9 MiB 0.01 0.00 1.08519 0.835432 -18.9954 -0.835432 0.835432 0.24 7.2216e-05 6.4252e-05 0.00218686 0.00196004 -1 -1 -1 -1 34 284 21 6.99608e+06 29431.4 618332. 2139.56 0.78 0.0217316 0.0180549 25762 151098 -1 205 20 201 201 7279 2639 1.07503 1.07503 -18.5674 -1.07503 0 0 787024. 2723.27 0.03 0.01 0.08 -1 -1 0.03 0.0047822 0.0041629 13 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 1.68 vpr 64.01 MiB -1 -1 0.08 17176 1 0.02 -1 -1 30448 -1 -1 4 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65544 19 10 69 70 1 43 33 17 17 289 -1 unnamed_device 25.6 MiB 0.01 574 154 1021 173 815 33 64.0 MiB 0.01 0.00 1.21049 0.846432 -22.178 -0.846432 0.846432 0.24 8.0462e-05 7.2111e-05 0.0020042 0.00180492 -1 -1 -1 -1 26 362 13 6.99608e+06 58862.7 503264. 1741.40 0.45 0.0218403 0.0182256 24322 120374 -1 330 13 193 193 10182 3468 0.949732 0.949732 -24.4664 -0.949732 0 0 618332. 2139.56 0.03 0.01 0.07 -1 -1 0.03 0.00473314 0.00420055 15 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_010bits.v common 1.97 vpr 63.70 MiB -1 -1 0.10 17292 1 0.02 -1 -1 29980 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65232 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.9 MiB 0.01 544 162 2809 951 1377 481 63.7 MiB 0.01 0.00 1.28156 0.868432 -24.3114 -0.868432 0.868432 0.24 8.8769e-05 7.9646e-05 0.00476361 0.00427393 -1 -1 -1 -1 28 474 31 6.99608e+06 58862.7 531479. 1839.03 0.72 0.0313156 0.026165 24610 126494 -1 395 21 314 314 24439 8382 1.18933 1.18933 -28.8206 -1.18933 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00500055 0.00434835 17 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 1.83 vpr 64.16 MiB -1 -1 0.07 17288 1 0.02 -1 -1 30468 -1 -1 4 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65700 23 12 83 84 1 54 39 17 17 289 -1 unnamed_device 25.2 MiB 0.02 532 273 1689 330 1171 188 64.2 MiB 0.01 0.00 1.21049 0.879432 -28.131 -0.879432 0.879432 0.25 9.8313e-05 8.8651e-05 0.00296163 0.00268092 -1 -1 -1 -1 26 623 18 6.99608e+06 58862.7 503264. 1741.40 0.58 0.0264777 0.0222433 24322 120374 -1 544 11 270 270 18431 5072 1.06403 1.06403 -32.3971 -1.06403 0 0 618332. 2139.56 0.03 0.01 0.06 -1 -1 0.03 0.00372252 0.00333072 18 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 1.49 vpr 63.78 MiB -1 -1 0.09 17532 1 0.02 -1 -1 29624 -1 -1 5 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 25.2 MiB 0.01 605 273 1918 408 1463 47 63.8 MiB 0.01 0.00 1.21049 0.901432 -30.2851 -0.901432 0.901432 0.24 0.000122347 0.00010992 0.00370936 0.00334849 -1 -1 -1 -1 30 586 14 6.99608e+06 73578.4 556674. 1926.21 0.26 0.0184953 0.0158493 25186 138497 -1 510 14 299 299 21856 6077 0.960732 0.960732 -33.5462 -0.960732 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00446628 0.00395407 20 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 1.54 vpr 64.18 MiB -1 -1 0.08 17532 1 0.02 -1 -1 29884 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 25.2 MiB 0.01 744 364 2014 346 1605 63 64.2 MiB 0.01 0.00 1.21049 0.912432 -34.6536 -0.912432 0.912432 0.25 0.000108566 9.8528e-05 0.00327897 0.00298316 -1 -1 -1 -1 30 765 14 6.99608e+06 73578.4 556674. 1926.21 0.30 0.0179499 0.0154263 25186 138497 -1 657 19 383 383 37818 8969 0.982732 0.982732 -38.8617 -0.982732 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00548102 0.00480409 21 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 2.12 vpr 64.19 MiB -1 -1 0.08 17288 1 0.02 -1 -1 29860 -1 -1 5 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65732 29 15 104 105 1 72 49 17 17 289 -1 unnamed_device 25.2 MiB 0.01 715 308 2897 867 1495 535 64.2 MiB 0.01 0.00 1.08519 0.934432 -37.2603 -0.934432 0.934432 0.33 0.000116353 0.000104472 0.00436136 0.00394087 -1 -1 -1 -1 32 659 19 6.99608e+06 73578.4 586450. 2029.24 0.80 0.0405173 0.0342335 25474 144626 -1 503 15 316 316 16770 4951 1.16303 1.16303 -40.3804 -1.16303 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.0051829 0.00463108 23 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_015bits.v common 1.80 vpr 64.21 MiB -1 -1 0.09 17292 1 0.02 -1 -1 30580 -1 -1 5 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65752 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 25.6 MiB 0.02 947 388 3253 747 2424 82 64.2 MiB 0.01 0.00 1.42821 1.30576 -39.7527 -1.30576 1.30576 0.25 0.000129015 0.00011721 0.00479255 0.00434749 -1 -1 -1 -1 28 808 13 6.99608e+06 73578.4 531479. 1839.03 0.56 0.0401269 0.0342676 24610 126494 -1 760 16 423 423 35677 9110 1.21603 1.21603 -47.1369 -1.21603 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00554708 0.00489858 24 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 1.56 vpr 64.61 MiB -1 -1 0.08 17208 1 0.02 -1 -1 30504 -1 -1 5 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66164 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 25.6 MiB 0.02 897 288 5359 1501 3812 46 64.6 MiB 0.02 0.00 1.30576 1.30576 -40.7923 -1.30576 1.30576 0.25 0.000132561 0.000119799 0.00752722 0.00683641 -1 -1 -1 -1 30 796 21 6.99608e+06 73578.4 556674. 1926.21 0.29 0.0264633 0.0229296 25186 138497 -1 638 17 446 446 28249 8724 1.18303 1.18303 -46.7155 -1.18303 0 0 706193. 2443.58 0.03 0.02 0.08 -1 -1 0.03 0.00605321 0.00534917 25 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_018bits.v common 1.61 vpr 64.26 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30600 -1 -1 5 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65804 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 25.8 MiB 0.02 989 450 4021 893 3044 84 64.3 MiB 0.03 0.00 1.32776 1.32776 -49.3309 -1.32776 1.32776 0.26 0.000194239 0.000178028 0.0126807 0.0117646 -1 -1 -1 -1 32 953 19 6.99608e+06 73578.4 586450. 2029.24 0.31 0.034915 0.0307218 25474 144626 -1 817 18 437 437 34491 8677 1.20503 1.20503 -54.2468 -1.20503 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00691724 0.00608941 28 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 1.98 vpr 64.36 MiB -1 -1 0.09 17672 1 0.02 -1 -1 30592 -1 -1 5 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 41 21 146 147 1 94 67 17 17 289 -1 unnamed_device 25.6 MiB 0.02 1130 644 6459 1750 4153 556 64.4 MiB 0.02 0.00 1.37991 1.36076 -60.916 -1.36076 1.36076 0.24 0.000186114 0.000159098 0.00851737 0.00776238 -1 -1 -1 -1 28 1184 20 6.99608e+06 73578.4 531479. 1839.03 0.70 0.0567692 0.0484959 24610 126494 -1 1093 14 462 462 43065 9987 1.23803 1.23803 -65.8346 -1.23803 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00635108 0.00565899 31 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 1.62 vpr 63.93 MiB -1 -1 0.11 17148 1 0.02 -1 -1 30656 -1 -1 6 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 45 23 160 161 1 108 74 17 17 289 -1 unnamed_device 24.9 MiB 0.03 1397 728 9374 2538 6055 781 63.9 MiB 0.03 0.00 1.83711 1.38276 -66.0973 -1.38276 1.38276 0.24 0.000421305 0.000392051 0.0145023 0.0133388 -1 -1 -1 -1 30 1267 16 6.99608e+06 88294.1 556674. 1926.21 0.31 0.0443588 0.0391372 25186 138497 -1 1146 13 440 440 28479 7142 1.15673 1.15673 -68.519 -1.15673 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00717088 0.00635823 34 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 2.14 vpr 64.93 MiB -1 -1 0.09 17676 1 0.02 -1 -1 30288 -1 -1 8 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66484 49 25 174 175 1 118 82 17 17 289 -1 unnamed_device 25.7 MiB 0.02 1600 609 11118 4682 6348 88 64.9 MiB 0.03 0.00 1.65536 1.40476 -68.6076 -1.40476 1.40476 0.24 0.000192685 0.000175179 0.013002 0.0118038 -1 -1 -1 -1 30 1317 28 6.99608e+06 117725 556674. 1926.21 0.88 0.0663127 0.0573583 25186 138497 -1 982 17 599 599 43750 10782 1.16103 1.16103 -67.9571 -1.16103 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00887636 0.00795704 38 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 2.51 vpr 65.07 MiB -1 -1 0.10 17912 1 0.02 -1 -1 30284 -1 -1 9 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 57 29 202 203 1 141 95 17 17 289 -1 unnamed_device 25.6 MiB 0.02 1869 719 13271 4497 7728 1046 65.1 MiB 0.04 0.00 1.58221 1.43776 -79.3712 -1.43776 1.43776 0.24 0.000217566 0.000198096 0.0173582 0.0159508 -1 -1 -1 -1 34 1601 28 6.99608e+06 132441 618332. 2139.56 1.19 0.099017 0.0862434 25762 151098 -1 1295 17 702 702 53061 13956 1.37433 1.37433 -84.6639 -1.37433 0 0 787024. 2723.27 0.03 0.02 0.08 -1 -1 0.03 0.00914594 0.00817613 44 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 2.77 vpr 65.24 MiB -1 -1 0.08 18056 1 0.02 -1 -1 30492 -1 -1 9 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66804 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 25.6 MiB 0.03 2158 1080 17058 5311 10070 1677 65.2 MiB 0.05 0.00 2.34329 1.84209 -99.1139 -1.84209 1.84209 0.24 0.000250746 0.000228637 0.018226 0.0166736 -1 -1 -1 -1 36 1981 22 6.99608e+06 132441 648988. 2245.63 1.44 0.11215 0.0976804 26050 158493 -1 1764 16 796 796 77458 17982 1.37903 1.37903 -104.657 -1.37903 0 0 828058. 2865.25 0.03 0.03 0.08 -1 -1 0.03 0.00997723 0.00895521 50 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 3.12 vpr 65.53 MiB -1 -1 0.10 17672 1 0.03 -1 -1 30532 -1 -1 14 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67100 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 25.6 MiB 0.05 3293 1263 31408 11283 18785 1340 65.5 MiB 0.10 0.00 2.89877 2.37842 -153.027 -2.37842 2.37842 0.26 0.000379941 0.000348214 0.0356847 0.033099 -1 -1 -1 -1 50 2197 19 6.99608e+06 206020 902133. 3121.57 1.49 0.152329 0.136311 28642 213929 -1 2047 17 1015 1015 78973 21212 1.47368 1.47368 -147.234 -1.47368 0 0 1.08113e+06 3740.92 0.04 0.03 0.17 -1 -1 0.04 0.0150746 0.0136766 74 2 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml adder_064bits.v common 3.03 vpr 65.97 MiB -1 -1 0.10 18060 1 0.03 -1 -1 30700 -1 -1 19 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67556 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 26.0 MiB 0.05 3762 2182 38948 13884 22833 2231 66.0 MiB 0.12 0.00 3.16535 2.91475 -237.268 -2.91475 2.91475 0.24 0.000532882 0.000491782 0.0366132 0.0339179 -1 -1 -1 -1 46 3578 33 6.99608e+06 279598 828058. 2865.25 1.39 0.226092 0.205022 28066 200906 -1 3173 24 1362 1362 170597 51692 1.82318 1.82318 -216.988 -1.82318 0 0 1.01997e+06 3529.29 0.03 0.07 0.11 -1 -1 0.03 0.0289523 0.0263375 98 2 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_004bits.v common 1.36 vpr 63.47 MiB -1 -1 0.08 17672 2 0.04 -1 -1 32076 -1 -1 1 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64992 9 5 28 33 1 16 15 17 17 289 -1 unnamed_device 25.2 MiB 0.01 190 69 267 63 197 7 63.5 MiB 0.00 0.00 0.959892 0.808785 -10.8404 -0.808785 0.808785 0.24 4.0591e-05 3.4926e-05 0.000844916 0.000740121 -1 -1 -1 -1 20 125 6 6.79088e+06 13472 414966. 1435.87 0.18 0.00616629 0.00514699 22510 95286 -1 114 5 38 38 1680 588 0.808785 0.808785 -10.5741 -0.808785 0 0 503264. 1741.40 0.02 0.00 0.05 -1 -1 0.02 0.00198176 0.00182255 8 6 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_005bits.v common 1.49 vpr 63.48 MiB -1 -1 0.08 17676 2 0.04 -1 -1 31880 -1 -1 2 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65000 11 6 34 40 1 22 19 17 17 289 -1 unnamed_device 25.2 MiB 0.01 237 124 294 77 210 7 63.5 MiB 0.00 0.00 1.08519 0.895372 -14.2654 -0.895372 0.895372 0.25 5.1318e-05 4.36e-05 0.000887019 0.00078346 -1 -1 -1 -1 20 223 7 6.79088e+06 26944 414966. 1435.87 0.32 0.00407653 0.00359076 22510 95286 -1 197 9 74 88 4199 1287 0.847985 0.847985 -14.325 -0.847985 0 0 503264. 1741.40 0.03 0.01 0.05 -1 -1 0.03 0.0043613 0.00391642 10 7 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_006bits.v common 1.49 vpr 63.49 MiB -1 -1 0.08 17288 3 0.04 -1 -1 31772 -1 -1 2 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65012 13 7 41 48 1 29 22 17 17 289 -1 unnamed_device 24.9 MiB 0.01 297 103 502 102 394 6 63.5 MiB 0.00 0.00 1.31004 1.18474 -16.2273 -1.18474 1.18474 0.25 5.7959e-05 5.086e-05 0.00129722 0.0011576 -1 -1 -1 -1 20 283 14 6.79088e+06 26944 414966. 1435.87 0.32 0.00607195 0.00526806 22510 95286 -1 218 8 98 101 4560 1562 1.0952 1.0952 -17.4931 -1.0952 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00275122 0.00250367 11 9 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_007bits.v common 1.91 vpr 63.89 MiB -1 -1 0.07 17284 3 0.04 -1 -1 31928 -1 -1 2 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65428 15 8 47 55 1 35 25 17 17 289 -1 unnamed_device 25.2 MiB 0.03 389 109 1105 258 733 114 63.9 MiB 0.01 0.00 1.27433 1.27433 -19.2536 -1.27433 1.27433 0.24 6.8729e-05 6.0936e-05 0.0024328 0.00217642 -1 -1 -1 -1 32 295 19 6.79088e+06 26944 586450. 2029.24 0.68 0.0217585 0.018043 24814 144142 -1 212 12 156 171 7381 2715 1.27433 1.27433 -19.107 -1.27433 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.0030553 0.00271194 13 10 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_008bits.v common 1.44 vpr 63.89 MiB -1 -1 0.08 17288 3 0.04 -1 -1 31768 -1 -1 4 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65420 17 9 56 65 1 41 30 17 17 289 -1 unnamed_device 25.2 MiB 0.04 528 162 904 175 711 18 63.9 MiB 0.01 0.00 2.22292 1.77558 -23.4463 -1.77558 1.77558 0.24 8.5703e-05 7.68e-05 0.00204702 0.0018497 -1 -1 -1 -1 26 384 8 6.79088e+06 53888 503264. 1741.40 0.22 0.0119036 0.0101708 23662 119890 -1 313 8 128 171 7108 2250 1.52498 1.52498 -24.0319 -1.52498 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.0031214 0.00284335 16 14 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_009bits.v common 1.84 vpr 63.89 MiB -1 -1 0.08 17144 4 0.05 -1 -1 31972 -1 -1 3 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65420 19 10 60 70 1 46 32 17 17 289 -1 unnamed_device 25.2 MiB 0.05 575 149 1332 372 880 80 63.9 MiB 0.01 0.00 2.02618 1.65028 -26.6546 -1.65028 1.65028 0.24 0.000198805 0.000183359 0.00372621 0.00341121 -1 -1 -1 -1 26 487 47 6.79088e+06 40416 503264. 1741.40 0.57 0.0391972 0.0328016 23662 119890 -1 356 12 222 252 10601 3951 1.56413 1.56413 -27.5075 -1.56413 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00371953 0.00332621 17 13 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_010bits.v common 1.93 vpr 63.59 MiB -1 -1 0.07 17284 4 0.04 -1 -1 32008 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65112 21 11 69 80 1 55 36 17 17 289 -1 unnamed_device 24.9 MiB 0.07 708 319 1334 274 1048 12 63.6 MiB 0.01 0.00 2.17674 1.77558 -33.7347 -1.77558 1.77558 0.24 9.831e-05 8.865e-05 0.00273705 0.00248438 -1 -1 -1 -1 26 585 13 6.79088e+06 53888 503264. 1741.40 0.68 0.0343214 0.0289106 23662 119890 -1 532 19 211 275 14877 3813 1.72868 1.72868 -33.9654 -1.72868 0 0 618332. 2139.56 0.02 0.02 0.07 -1 -1 0.02 0.00698685 0.00606662 21 17 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_011bits.v common 1.44 vpr 63.59 MiB -1 -1 0.09 17288 5 0.04 -1 -1 31996 -1 -1 4 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65112 23 12 76 88 1 59 39 17 17 289 -1 unnamed_device 25.1 MiB 0.04 647 309 2349 586 1604 159 63.6 MiB 0.01 0.00 2.04408 1.90432 -35.544 -1.90432 1.90432 0.24 0.000118238 0.000107457 0.00490813 0.00447316 -1 -1 -1 -1 26 651 11 6.79088e+06 53888 503264. 1741.40 0.23 0.0188926 0.0162985 23662 119890 -1 557 13 225 288 14298 4157 1.72868 1.72868 -36.0207 -1.72868 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.0045407 0.0040569 23 19 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_012bits.v common 1.82 vpr 63.65 MiB -1 -1 0.08 17516 5 0.05 -1 -1 31860 -1 -1 4 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65180 25 13 83 96 1 65 42 17 17 289 -1 unnamed_device 25.2 MiB 0.07 871 230 2202 525 1546 131 63.7 MiB 0.01 0.00 2.31598 1.85398 -36.7003 -1.85398 1.85398 0.25 0.000112926 0.000101939 0.00483927 0.00441732 -1 -1 -1 -1 20 809 29 6.79088e+06 53888 414966. 1435.87 0.54 0.033559 0.0286641 22510 95286 -1 597 14 328 396 18535 6435 2.01504 2.01504 -43.369 -2.01504 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00495567 0.00441734 24 21 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_013bits.v common 1.99 vpr 63.71 MiB -1 -1 0.08 17672 5 0.05 -1 -1 31776 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65236 27 14 91 105 1 70 46 17 17 289 -1 unnamed_device 24.9 MiB 0.06 882 344 1932 345 1559 28 63.7 MiB 0.01 0.00 2.6855 2.15497 -44.0983 -2.15497 2.15497 0.26 0.00012923 0.000116991 0.00634604 0.00588021 -1 -1 -1 -1 26 843 14 6.79088e+06 67360 503264. 1741.40 0.65 0.046643 0.0397556 23662 119890 -1 678 12 273 372 26621 7251 1.97933 1.97933 -46.0263 -1.97933 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00500649 0.00451197 28 24 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_014bits.v common 1.58 vpr 64.08 MiB -1 -1 0.09 17668 6 0.05 -1 -1 32044 -1 -1 5 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 29 15 95 110 1 77 49 17 17 289 -1 unnamed_device 25.3 MiB 0.05 1027 432 5478 2270 3186 22 64.1 MiB 0.02 0.00 3.53332 2.40562 -50.8745 -2.40562 2.40562 0.24 0.00012953 0.000116903 0.00875141 0.00792578 -1 -1 -1 -1 26 972 22 6.79088e+06 67360 503264. 1741.40 0.27 0.026757 0.0231561 23662 119890 -1 813 31 380 500 68442 36152 2.34404 2.34404 -53.3106 -2.34404 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.00949754 0.00825964 29 23 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_015bits.v common 1.96 vpr 63.75 MiB -1 -1 0.08 17668 6 0.05 -1 -1 32072 -1 -1 6 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65280 31 16 104 120 1 82 53 17 17 289 -1 unnamed_device 25.2 MiB 0.05 1014 332 2825 621 2166 38 63.8 MiB 0.01 0.00 2.52053 2.31609 -50.7794 -2.31609 2.31609 0.24 0.000146686 0.000133027 0.00493021 0.0044852 -1 -1 -1 -1 28 819 17 6.79088e+06 80832 531479. 1839.03 0.68 0.0346292 0.0295211 23950 126010 -1 700 16 321 385 20195 6380 2.14045 2.14045 -51.9148 -2.14045 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00685052 0.00607808 32 27 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_016bits.v common 2.08 vpr 64.12 MiB -1 -1 0.09 17284 7 0.05 -1 -1 31992 -1 -1 6 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65664 33 17 112 129 1 84 56 17 17 289 -1 unnamed_device 25.2 MiB 0.05 981 364 5834 2362 3388 84 64.1 MiB 0.02 0.00 3.03218 2.65628 -57.1434 -2.65628 2.65628 0.24 0.000153552 0.000139165 0.00916918 0.00832645 -1 -1 -1 -1 28 825 26 6.79088e+06 80832 531479. 1839.03 0.76 0.0497422 0.0426136 23950 126010 -1 754 12 389 525 31208 9149 2.35534 2.35534 -56.5683 -2.35534 0 0 648988. 2245.63 0.03 0.02 0.08 -1 -1 0.03 0.00611811 0.00546681 33 30 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_018bits.v common 2.04 vpr 63.85 MiB -1 -1 0.09 17676 7 0.05 -1 -1 32128 -1 -1 8 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65380 37 19 127 146 1 96 64 17 17 289 -1 unnamed_device 25.2 MiB 0.13 1255 408 5906 1307 4456 143 63.8 MiB 0.02 0.00 3.06794 2.69204 -66.697 -2.69204 2.69204 0.24 0.000169757 0.000154163 0.00883051 0.00803267 -1 -1 -1 -1 26 850 20 6.79088e+06 107776 503264. 1741.40 0.64 0.061747 0.0530635 23662 119890 -1 828 12 334 421 23186 6922 2.56674 2.56674 -68.0786 -2.56674 0 0 618332. 2139.56 0.02 0.01 0.07 -1 -1 0.02 0.00646752 0.00580998 38 35 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_020bits.v common 2.29 vpr 63.94 MiB -1 -1 0.09 18052 8 0.05 -1 -1 31900 -1 -1 9 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65472 41 21 139 160 1 108 71 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1178 630 4451 946 3195 310 63.9 MiB 0.02 0.00 3.80452 2.99647 -79.4241 -2.99647 2.99647 0.24 0.000199504 0.000182052 0.00819958 0.00754271 -1 -1 -1 -1 34 1193 25 6.79088e+06 121248 618332. 2139.56 0.97 0.0654025 0.0565595 25102 150614 -1 1046 11 350 457 27043 7039 2.68439 2.68439 -78.9303 -2.68439 0 0 787024. 2723.27 0.03 0.01 0.08 -1 -1 0.03 0.00654397 0.00592552 42 37 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_022bits.v common 2.15 vpr 64.02 MiB -1 -1 0.10 17528 9 0.08 -1 -1 31888 -1 -1 9 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65556 45 23 153 176 1 118 77 17 17 289 -1 unnamed_device 24.9 MiB 0.11 1410 509 4641 949 3407 285 64.0 MiB 0.02 0.00 3.62894 3.32208 -86.6758 -3.32208 3.32208 0.25 0.000206959 0.000188772 0.00822889 0.00760191 -1 -1 -1 -1 28 1187 12 6.79088e+06 121248 531479. 1839.03 0.71 0.0623315 0.0544139 23950 126010 -1 1044 12 432 572 31808 9303 3.14645 3.14645 -89.0297 -3.14645 0 0 648988. 2245.63 0.02 0.02 0.06 -1 -1 0.02 0.00724595 0.00656483 45 41 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_024bits.v common 2.47 vpr 64.10 MiB -1 -1 0.10 17668 10 0.05 -1 -1 32108 -1 -1 10 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65640 49 25 166 191 1 129 84 17 17 289 -1 unnamed_device 24.9 MiB 0.14 1438 732 6672 1366 5033 273 64.1 MiB 0.03 0.00 3.77644 3.52584 -100.737 -3.52584 3.52584 0.24 0.000258531 0.000234864 0.0107348 0.00981197 -1 -1 -1 -1 30 1449 21 6.79088e+06 134720 556674. 1926.21 1.01 0.0803002 0.0698811 24526 138013 -1 1282 14 482 592 37126 9650 3.311 3.311 -102.297 -3.311 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00930377 0.00838084 48 44 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_028bits.v common 2.33 vpr 64.77 MiB -1 -1 0.10 18056 11 0.06 -1 -1 32128 -1 -1 12 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 57 29 198 227 1 154 98 17 17 289 -1 unnamed_device 25.3 MiB 0.17 1929 864 14273 4814 7513 1946 64.8 MiB 0.04 0.00 4.41418 4.16358 -131.462 -4.16358 4.16358 0.24 0.000334761 0.000292296 0.0189418 0.0173284 -1 -1 -1 -1 30 1685 14 6.79088e+06 161664 556674. 1926.21 0.85 0.0902499 0.078844 24526 138013 -1 1424 16 536 704 44687 11240 3.73734 3.73734 -125.06 -3.73734 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.0107723 0.0097122 57 56 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_032bits.v common 1.87 vpr 64.51 MiB -1 -1 0.09 17660 13 0.06 -1 -1 32132 -1 -1 11 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 65 33 224 257 1 173 109 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2161 889 19609 6448 11466 1695 64.5 MiB 0.06 0.00 5.29144 4.91554 -155.687 -4.91554 4.91554 0.24 0.000288751 0.000263615 0.0251435 0.0229999 -1 -1 -1 -1 30 1948 14 6.79088e+06 148192 556674. 1926.21 0.33 0.0638136 0.0568969 24526 138013 -1 1598 11 671 898 50938 14191 4.4893 4.4893 -151.306 -4.4893 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00966942 0.00884341 68 62 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_048bits.v common 2.90 vpr 65.67 MiB -1 -1 0.12 18056 19 0.08 -1 -1 32564 -1 -1 19 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67248 97 49 340 389 1 266 165 17 17 289 -1 unnamed_device 25.6 MiB 0.25 3053 1349 31805 8586 20513 2706 65.7 MiB 0.08 0.00 7.2345 7.17824 -291.108 -7.17824 7.17824 0.24 0.000445752 0.000409263 0.0340212 0.0312669 -1 -1 -1 -1 30 2935 26 6.79088e+06 255968 556674. 1926.21 1.17 0.163293 0.145885 24526 138013 -1 2347 17 983 1280 75466 20764 6.76314 6.76314 -281.839 -6.76314 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0192748 0.0176258 102 98 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml adder_064bits.v common 3.38 vpr 65.30 MiB -1 -1 0.13 18444 26 0.09 -1 -1 32720 -1 -1 25 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66872 129 65 453 518 1 343 219 17 17 289 -1 unnamed_device 25.9 MiB 0.39 4118 1975 48985 14791 29668 4526 65.3 MiB 0.16 0.00 10.9476 10.5717 -512.006 -10.5717 10.5717 0.27 0.000604211 0.000557155 0.0690468 0.0640997 -1 -1 -1 -1 32 4167 26 6.79088e+06 336800 586450. 2029.24 1.29 0.293841 0.266364 24814 144142 -1 3407 11 1203 1624 102575 26684 9.9346 9.9346 -497.018 -9.9346 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0205197 0.0190707 133 131 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_004bits.v common 1.72 vpr 63.71 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30456 -1 -1 2 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65240 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 25.2 MiB 0.03 212 56 376 68 294 14 63.7 MiB 0.00 0.00 1.23249 0.789073 -10.0558 -0.789073 0.789073 0.24 4.1776e-05 3.6353e-05 0.00100959 0.000882855 -1 -1 -1 -1 22 155 9 6.87369e+06 27947.7 443629. 1535.05 0.54 0.00905167 0.00747639 23458 102101 -1 113 8 44 44 2021 661 0.663773 0.663773 -10.1705 -0.663773 0 0 531479. 1839.03 0.02 0.01 0.05 -1 -1 0.02 0.00193781 0.00176492 10 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 1.79 vpr 63.85 MiB -1 -1 0.08 17676 1 0.02 -1 -1 30368 -1 -1 3 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65384 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 25.6 MiB 0.03 337 201 668 148 451 69 63.9 MiB 0.01 0.00 1.11738 0.811073 -14.6592 -0.811073 0.811073 0.25 5.759e-05 5.0553e-05 0.00200373 0.00176382 -1 -1 -1 -1 30 309 9 6.87369e+06 41921.5 556674. 1926.21 0.54 0.0204044 0.0166664 25186 138497 -1 287 8 80 80 5048 1229 0.936373 0.936373 -16.691 -0.936373 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00219224 0.00198208 13 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 1.63 vpr 63.92 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30476 -1 -1 4 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65456 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 25.3 MiB 0.03 296 154 738 162 543 33 63.9 MiB 0.00 0.00 0.981892 1.03835 -16.7722 -1.03835 1.03835 0.24 5.7593e-05 5.0774e-05 0.00155182 0.0013753 -1 -1 -1 -1 20 381 15 6.87369e+06 55895.4 414966. 1435.87 0.48 0.00782866 0.00668543 23170 95770 -1 331 11 113 113 8617 2387 1.08367 1.08367 -19.4324 -1.08367 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00256891 0.00229214 15 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 2.01 vpr 63.78 MiB -1 -1 0.08 17292 1 0.02 -1 -1 30452 -1 -1 3 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 25.0 MiB 0.04 404 127 824 169 639 16 63.8 MiB 0.01 0.00 1.27304 1.2044 -18.2318 -1.2044 1.2044 0.25 9.0894e-05 7.8934e-05 0.00274558 0.00249615 -1 -1 -1 -1 30 286 12 6.87369e+06 41921.5 556674. 1926.21 0.76 0.0250763 0.0208659 25186 138497 -1 237 11 140 140 5141 1808 0.989373 0.989373 -19.8349 -0.989373 0 0 706193. 2443.58 0.03 0.01 0.08 -1 -1 0.03 0.00277701 0.00249233 16 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 1.44 vpr 63.88 MiB -1 -1 0.07 17184 1 0.02 -1 -1 30432 -1 -1 3 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65416 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 25.6 MiB 0.04 469 149 997 232 705 60 63.9 MiB 0.01 0.00 1.3407 1.2154 -21.0785 -1.2154 1.2154 0.24 7.2964e-05 6.5122e-05 0.0020257 0.00181191 -1 -1 -1 -1 26 301 14 6.87369e+06 41921.5 503264. 1741.40 0.22 0.0115931 0.00981649 24322 120374 -1 267 14 141 141 5701 2184 0.978373 0.978373 -22.318 -0.978373 0 0 618332. 2139.56 0.02 0.01 0.07 -1 -1 0.02 0.00381328 0.00334326 19 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 1.50 vpr 63.88 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30356 -1 -1 3 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65416 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 25.6 MiB 0.04 599 160 2832 1028 1250 554 63.9 MiB 0.01 0.00 1.68574 1.2264 -24.1659 -1.2264 1.2264 0.24 8.1862e-05 7.2582e-05 0.00499751 0.00445979 -1 -1 -1 -1 32 342 9 6.87369e+06 41921.5 586450. 2029.24 0.27 0.0174207 0.0148924 25474 144626 -1 282 13 175 175 10291 3253 1.01137 1.01137 -24.6383 -1.01137 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.00353222 0.00312488 20 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 1.98 vpr 63.95 MiB -1 -1 0.08 17288 1 0.02 -1 -1 30540 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65484 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 25.6 MiB 0.04 623 242 2691 801 1272 618 63.9 MiB 0.01 0.00 1.5583 1.2374 -27.5669 -1.2374 1.2374 0.24 8.9243e-05 7.9874e-05 0.00452405 0.00406905 -1 -1 -1 -1 32 469 18 6.87369e+06 55895.4 586450. 2029.24 0.75 0.0254886 0.0214091 25474 144626 -1 417 16 245 245 15919 4276 1.11467 1.11467 -29.6904 -1.11467 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.00414876 0.00363803 22 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_011bits.v common 1.80 vpr 63.95 MiB -1 -1 0.08 17272 1 0.02 -1 -1 30444 -1 -1 5 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65480 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 25.2 MiB 0.04 816 226 1740 328 1393 19 63.9 MiB 0.01 0.00 1.6243 1.2484 -31.1833 -1.2484 1.2484 0.26 0.000189975 0.000173605 0.00398219 0.00362859 -1 -1 -1 -1 30 420 17 6.87369e+06 69869.2 556674. 1926.21 0.52 0.0273873 0.0231806 25186 138497 -1 374 10 175 175 9634 2666 0.886073 0.886073 -29.465 -0.886073 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00346491 0.00310787 24 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_012bits.v common 1.93 vpr 64.02 MiB -1 -1 0.09 17284 1 0.02 -1 -1 30448 -1 -1 5 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 25.6 MiB 0.04 697 203 1918 378 1524 16 64.0 MiB 0.01 0.00 1.31566 1.2594 -32.0153 -1.2594 1.2594 0.25 0.000103272 9.2986e-05 0.00311303 0.00281427 -1 -1 -1 -1 28 507 20 6.87369e+06 69869.2 531479. 1839.03 0.66 0.0324221 0.0271882 24610 126494 -1 465 16 290 290 16133 5368 1.15867 1.15867 -36.1502 -1.15867 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00457912 0.00402788 26 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 1.57 vpr 64.03 MiB -1 -1 0.13 17532 1 0.03 -1 -1 30440 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65564 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 25.6 MiB 0.04 813 341 1686 290 1386 10 64.0 MiB 0.01 0.00 1.32666 1.2704 -36.5095 -1.2704 1.2704 0.24 0.000109773 9.9396e-05 0.00290007 0.00263813 -1 -1 -1 -1 30 655 12 6.87369e+06 69869.2 556674. 1926.21 0.27 0.018653 0.0160027 25186 138497 -1 554 13 288 288 13777 4010 1.18067 1.18067 -39.3299 -1.18067 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00549287 0.00483231 28 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.02 vpr 64.45 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30460 -1 -1 7 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 25.6 MiB 0.05 813 369 2307 425 1796 86 64.4 MiB 0.01 0.00 1.2814 1.2814 -39.6325 -1.2814 1.2814 0.26 0.000117386 0.000106447 0.00385623 0.00350852 -1 -1 -1 -1 30 719 15 6.87369e+06 97816.9 556674. 1926.21 0.74 0.0328918 0.027949 25186 138497 -1 664 16 345 345 22747 5958 1.06637 1.06637 -41.9394 -1.06637 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00503821 0.00443319 31 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 1.87 vpr 64.09 MiB -1 -1 0.07 17292 1 0.02 -1 -1 30596 -1 -1 6 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65628 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 25.6 MiB 0.06 982 485 5399 1393 3244 762 64.1 MiB 0.03 0.00 2.02863 1.65273 -45.9173 -1.65273 1.65273 0.26 0.000164789 0.000150791 0.0115039 0.0105091 -1 -1 -1 -1 30 862 17 6.87369e+06 83843 556674. 1926.21 0.57 0.0508753 0.0437617 25186 138497 -1 828 15 387 387 32478 7816 1.18967 1.18967 -48.8843 -1.18967 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00535564 0.00471064 32 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 1.54 vpr 64.53 MiB -1 -1 0.08 17676 1 0.02 -1 -1 30332 -1 -1 6 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 25.6 MiB 0.06 1128 462 6690 1697 4688 305 64.5 MiB 0.02 0.00 2.29023 1.66373 -49.0046 -1.66373 1.66373 0.24 0.000139914 0.000125894 0.00936706 0.00845406 -1 -1 -1 -1 30 869 12 6.87369e+06 83843 556674. 1926.21 0.29 0.0340396 0.0295893 25186 138497 -1 806 15 402 402 29736 7468 1.06437 1.06437 -48.4603 -1.06437 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00592819 0.00525594 35 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 2.13 vpr 64.18 MiB -1 -1 0.07 17292 1 0.02 -1 -1 30440 -1 -1 7 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65720 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 25.6 MiB 0.06 990 533 3188 655 2384 149 64.2 MiB 0.01 0.00 1.74199 1.68573 -55.8065 -1.68573 1.68573 0.24 0.00015175 0.000137814 0.00450851 0.00411922 -1 -1 -1 -1 32 956 12 6.87369e+06 97816.9 586450. 2029.24 0.88 0.0448108 0.0381352 25474 144626 -1 907 16 422 422 33967 8194 1.13037 1.13037 -56.5331 -1.13037 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00619556 0.00545455 38 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 1.89 vpr 63.81 MiB -1 -1 0.08 17676 1 0.02 -1 -1 30580 -1 -1 8 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65344 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 25.2 MiB 0.06 1415 439 3814 728 2915 171 63.8 MiB 0.02 0.00 1.7716 1.70773 -58.9105 -1.70773 1.70773 0.24 0.000165807 0.000151395 0.00509435 0.00466484 -1 -1 -1 -1 30 943 12 6.87369e+06 111791 556674. 1926.21 0.58 0.042865 0.0367532 25186 138497 -1 817 11 419 419 21319 6697 1.26667 1.26667 -61.1999 -1.26667 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00538129 0.0048225 42 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 2.18 vpr 64.32 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30296 -1 -1 10 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 25.6 MiB 0.08 1570 650 10204 2666 7106 432 64.3 MiB 0.04 0.00 2.07263 1.72973 -70.7265 -1.72973 1.72973 0.24 0.000180482 0.000164557 0.0121811 0.0110423 -1 -1 -1 -1 28 1331 15 6.87369e+06 139738 531479. 1839.03 0.84 0.0675135 0.0586636 24610 126494 -1 1186 15 555 555 41077 10421 1.18067 1.18067 -69.0636 -1.18067 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00682274 0.00605597 47 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 2.13 vpr 64.50 MiB -1 -1 0.10 18060 1 0.02 -1 -1 30260 -1 -1 9 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 25.6 MiB 0.06 1728 753 10163 2514 7290 359 64.5 MiB 0.03 0.00 2.60897 2.11206 -79.0843 -2.11206 2.11206 0.24 0.000198774 0.00018064 0.0116708 0.0106316 -1 -1 -1 -1 28 1443 22 6.87369e+06 125765 531479. 1839.03 0.83 0.0743601 0.0644676 24610 126494 -1 1279 14 625 625 48859 12537 1.21637 1.21637 -75.9973 -1.21637 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00703586 0.00628228 51 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 1.72 vpr 63.97 MiB -1 -1 0.09 18060 1 0.02 -1 -1 30424 -1 -1 11 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65508 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1802 821 10309 2515 7055 739 64.0 MiB 0.04 0.00 2.40666 2.15606 -92.7202 -2.15606 2.15606 0.27 0.000228156 0.000208111 0.0115492 0.0105766 -1 -1 -1 -1 32 1566 13 6.87369e+06 153712 586450. 2029.24 0.34 0.0482663 0.0427322 25474 144626 -1 1367 16 629 629 42642 11312 1.38567 1.38567 -90.5462 -1.38567 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00844629 0.00753366 58 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 1.73 vpr 64.96 MiB -1 -1 0.08 18060 1 0.02 -1 -1 30500 -1 -1 12 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66524 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 25.2 MiB 0.07 1930 880 15627 3694 10983 950 65.0 MiB 0.05 0.00 2.65269 2.56039 -107.701 -2.56039 2.56039 0.24 0.000253236 0.00023166 0.0162425 0.0148662 -1 -1 -1 -1 32 1756 16 6.87369e+06 167686 586450. 2029.24 0.33 0.047179 0.0417844 25474 144626 -1 1493 16 685 685 50430 12966 1.32437 1.32437 -97.9203 -1.32437 0 0 744469. 2576.02 0.03 0.03 0.09 -1 -1 0.03 0.0106361 0.00952148 67 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 1.85 vpr 64.89 MiB -1 -1 0.09 17672 1 0.03 -1 -1 30508 -1 -1 18 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66448 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3166 1519 32420 11737 18188 2495 64.9 MiB 0.10 0.00 3.83296 3.45705 -190.27 -3.45705 3.45705 0.24 0.000392513 0.000360602 0.0298853 0.0274653 -1 -1 -1 -1 32 2673 32 6.87369e+06 251529 586450. 2029.24 0.40 0.093092 0.0839451 25474 144626 -1 2346 12 984 984 82123 21073 1.47437 1.47437 -151.051 -1.47437 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0121083 0.0110706 99 2 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 3.03 vpr 65.89 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30700 -1 -1 24 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67476 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 26.4 MiB 0.09 4215 1893 53273 19656 30087 3530 65.9 MiB 0.17 0.00 4.72962 4.35372 -277.877 -4.35372 4.35372 0.24 0.000536461 0.000495991 0.0453219 0.0419007 -1 -1 -1 -1 36 3520 23 6.87369e+06 335372 648988. 2245.63 1.40 0.224535 0.203023 26050 158493 -1 2967 15 1307 1307 101615 26086 1.75637 1.75637 -205.78 -1.75637 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0180671 0.0165087 131 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_004bits.v common 1.27 vpr 63.64 MiB -1 -1 0.08 17296 1 0.02 -1 -1 30428 -1 -1 2 9 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65172 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 24.8 MiB 0.02 212 58 396 77 301 18 63.6 MiB 0.00 0.00 1.23249 0.789073 -10.1079 -0.789073 0.789073 0.24 4.1089e-05 3.5592e-05 0.0010285 0.000897184 -1 -1 -1 -1 20 157 10 6.89349e+06 28187.7 414966. 1435.87 0.16 0.00332141 0.00293392 23170 95770 -1 126 11 47 47 2750 988 0.91632 0.91632 -11.0957 -0.91632 0 0 503264. 1741.40 0.02 0.01 0.05 -1 -1 0.02 0.00207966 0.00187057 10 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 1.95 vpr 63.29 MiB -1 -1 0.07 17676 1 0.02 -1 -1 30456 -1 -1 3 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64808 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 24.5 MiB 0.02 337 201 668 159 420 89 63.3 MiB 0.01 0.00 1.12358 0.817273 -14.7188 -0.817273 0.817273 0.25 4.9791e-05 4.3821e-05 0.0019764 0.0017713 -1 -1 -1 -1 30 320 35 6.89349e+06 42281.5 556674. 1926.21 0.73 0.0226418 0.0187298 25186 138497 -1 287 8 86 86 6447 1544 0.936373 0.936373 -16.8555 -0.936373 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00218328 0.00194766 13 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 1.69 vpr 63.15 MiB -1 -1 0.06 17676 1 0.02 -1 -1 30428 -1 -1 4 13 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64664 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 25.0 MiB 0.03 296 177 636 142 467 27 63.1 MiB 0.00 0.00 0.981892 0.981892 -17.0458 -0.981892 0.981892 0.25 5.9479e-05 5.0802e-05 0.0013981 0.00123754 -1 -1 -1 -1 22 371 12 6.89349e+06 56375.4 443629. 1535.05 0.47 0.0124495 0.0102737 23458 102101 -1 312 10 102 102 6620 1815 1.06362 1.06362 -18.462 -1.06362 0 0 531479. 1839.03 0.02 0.01 0.05 -1 -1 0.02 0.00244682 0.00219573 15 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 1.76 vpr 63.79 MiB -1 -1 0.08 17672 1 0.02 -1 -1 30472 -1 -1 3 15 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65316 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 25.6 MiB 0.03 404 129 786 171 602 13 63.8 MiB 0.01 0.00 1.27304 1.2044 -18.4111 -1.2044 1.2044 0.24 6.7188e-05 5.9544e-05 0.00170875 0.00152223 -1 -1 -1 -1 24 319 15 6.89349e+06 42281.5 470940. 1629.55 0.52 0.0194585 0.0159981 24034 113901 -1 306 8 149 149 9436 3202 0.989373 0.989373 -21.4638 -0.989373 0 0 586450. 2029.24 0.02 0.01 0.07 -1 -1 0.02 0.00251805 0.00227062 16 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 1.48 vpr 63.77 MiB -1 -1 0.08 17284 1 0.02 -1 -1 30360 -1 -1 3 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 25.1 MiB 0.03 469 149 997 246 695 56 63.8 MiB 0.01 0.00 1.23249 1.2154 -21.0401 -1.2154 1.2154 0.26 7.6619e-05 6.8311e-05 0.00318806 0.00289838 -1 -1 -1 -1 26 339 10 6.89349e+06 42281.5 503264. 1741.40 0.23 0.0125029 0.0106788 24322 120374 -1 242 13 140 140 5387 2137 0.989373 0.989373 -22.2587 -0.989373 0 0 618332. 2139.56 0.02 0.01 0.06 -1 -1 0.02 0.00322621 0.00286052 19 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 2.08 vpr 63.78 MiB -1 -1 0.11 17284 1 0.02 -1 -1 30136 -1 -1 3 19 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 25.2 MiB 0.03 599 160 2832 996 1143 693 63.8 MiB 0.01 0.00 1.65894 1.2264 -24.2203 -1.2264 1.2264 0.24 8.0585e-05 7.2032e-05 0.00504873 0.00451425 -1 -1 -1 -1 32 320 13 6.89349e+06 42281.5 586450. 2029.24 0.72 0.031913 0.0266647 25474 144626 -1 244 13 147 147 6076 2054 0.84402 0.84402 -21.7627 -0.84402 0 0 744469. 2576.02 0.03 0.01 0.09 -1 -1 0.03 0.0037204 0.00328399 20 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.08 vpr 63.39 MiB -1 -1 0.12 17292 1 0.02 -1 -1 30352 -1 -1 4 21 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64912 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.5 MiB 0.03 623 175 2691 919 1290 482 63.4 MiB 0.01 0.00 1.4832 1.2374 -27.1082 -1.2374 1.2374 0.24 8.8467e-05 7.9346e-05 0.00452108 0.00406212 -1 -1 -1 -1 32 382 18 6.89349e+06 56375.4 586450. 2029.24 0.73 0.0326297 0.0272524 25474 144626 -1 292 10 145 145 6986 2360 0.88802 0.88802 -25.1184 -0.88802 0 0 744469. 2576.02 0.03 0.01 0.08 -1 -1 0.03 0.0032407 0.00290434 22 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 1.94 vpr 63.50 MiB -1 -1 0.10 17284 1 0.02 -1 -1 30488 -1 -1 5 23 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 24.8 MiB 0.03 816 189 1604 298 1238 68 63.5 MiB 0.01 0.00 1.6243 1.2484 -30.1698 -1.2484 1.2484 0.25 9.8357e-05 8.8621e-05 0.00279691 0.00253145 -1 -1 -1 -1 26 507 22 6.89349e+06 70469.2 503264. 1741.40 0.60 0.0255841 0.0213855 24322 120374 -1 438 15 281 281 16169 5271 1.14287 1.14287 -32.7732 -1.14287 0 0 618332. 2139.56 0.03 0.01 0.07 -1 -1 0.03 0.00442084 0.00391521 24 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 1.99 vpr 64.18 MiB -1 -1 0.11 17292 1 0.02 -1 -1 30488 -1 -1 5 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65716 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 25.2 MiB 0.03 697 206 1918 387 1516 15 64.2 MiB 0.01 0.00 1.31566 1.2594 -32.1458 -1.2594 1.2594 0.24 0.000103974 9.3764e-05 0.00313121 0.00283186 -1 -1 -1 -1 28 544 24 6.89349e+06 70469.2 531479. 1839.03 0.64 0.0307663 0.0257498 24610 126494 -1 448 15 267 267 13804 4654 1.15867 1.15867 -35.9015 -1.15867 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00479109 0.00417829 26 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 1.94 vpr 63.93 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29900 -1 -1 5 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 25.6 MiB 0.04 813 321 1850 346 1493 11 63.9 MiB 0.01 0.00 1.32666 1.2704 -36.4307 -1.2704 1.2704 0.24 0.000110104 9.961e-05 0.00295105 0.00267871 -1 -1 -1 -1 30 565 14 6.89349e+06 70469.2 556674. 1926.21 0.60 0.0313754 0.0264468 25186 138497 -1 530 12 247 247 12350 3589 1.01137 1.01137 -36.0238 -1.01137 0 0 706193. 2443.58 0.03 0.01 0.07 -1 -1 0.03 0.00411258 0.0036678 28 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 1.93 vpr 63.96 MiB -1 -1 0.10 17288 1 0.02 -1 -1 30552 -1 -1 7 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65492 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 25.2 MiB 0.04 813 384 2495 473 1933 89 64.0 MiB 0.01 0.00 1.2814 1.2814 -40.976 -1.2814 1.2814 0.24 0.000117993 0.000106213 0.00363177 0.00329301 -1 -1 -1 -1 26 810 14 6.89349e+06 98656.9 503264. 1741.40 0.57 0.0258483 0.021987 24322 120374 -1 746 17 370 370 30180 8245 1.06832 1.06832 -43.5975 -1.06832 0 0 618332. 2139.56 0.02 0.01 0.07 -1 -1 0.02 0.00519978 0.00457024 31 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.20 vpr 64.34 MiB -1 -1 0.10 17292 1 0.02 -1 -1 30588 -1 -1 6 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 25.6 MiB 0.05 982 503 3518 892 2197 429 64.3 MiB 0.02 0.00 2.02863 1.65273 -45.7068 -1.65273 1.65273 0.24 0.000135696 0.000123138 0.00665055 0.00611328 -1 -1 -1 -1 32 883 18 6.89349e+06 84563 586450. 2029.24 0.78 0.0483766 0.0414011 25474 144626 -1 792 14 329 329 23739 6157 1.22267 1.22267 -49.194 -1.22267 0 0 744469. 2576.02 0.03 0.02 0.09 -1 -1 0.03 0.00577121 0.00508213 32 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 1.99 vpr 64.39 MiB -1 -1 0.11 17292 1 0.02 -1 -1 30024 -1 -1 6 33 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 25.6 MiB 0.05 1128 419 4229 1016 3090 123 64.4 MiB 0.02 0.00 2.29023 1.66373 -48.1052 -1.66373 1.66373 0.24 0.000164621 0.000150187 0.00610199 0.00553404 -1 -1 -1 -1 28 877 22 6.89349e+06 84563 531479. 1839.03 0.58 0.0431659 0.0366672 24610 126494 -1 727 15 348 348 22785 6153 0.98502 0.98502 -45.8259 -0.98502 0 0 648988. 2245.63 0.02 0.01 0.07 -1 -1 0.02 0.00531759 0.00470243 35 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 1.75 vpr 64.40 MiB -1 -1 0.11 17292 1 0.03 -1 -1 30588 -1 -1 7 37 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 25.6 MiB 0.05 990 527 3813 762 2889 162 64.4 MiB 0.02 0.00 1.74199 1.68573 -55.4954 -1.68573 1.68573 0.24 0.000178041 0.000161664 0.00707604 0.00648495 -1 -1 -1 -1 30 934 16 6.89349e+06 98656.9 556674. 1926.21 0.30 0.0327715 0.0284548 25186 138497 -1 844 17 347 347 24553 5924 0.98502 0.98502 -52.8184 -0.98502 0 0 706193. 2443.58 0.03 0.02 0.07 -1 -1 0.03 0.00792233 0.00685172 38 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.00 vpr 64.10 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29992 -1 -1 8 41 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65640 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 25.2 MiB 0.05 1415 379 3958 843 3047 68 64.1 MiB 0.02 0.00 1.7778 1.70773 -57.6396 -1.70773 1.70773 0.24 0.000164211 0.000149579 0.00520346 0.00475169 -1 -1 -1 -1 30 883 21 6.89349e+06 112751 556674. 1926.21 0.59 0.0441693 0.037646 25186 138497 -1 707 16 445 445 24688 7831 1.13037 1.13037 -55.7432 -1.13037 0 0 706193. 2443.58 0.03 0.02 0.08 -1 -1 0.03 0.00739954 0.00651301 42 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.21 vpr 64.19 MiB -1 -1 0.12 17148 1 0.02 -1 -1 30296 -1 -1 10 45 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 25.2 MiB 0.06 1570 705 9540 2422 6707 411 64.2 MiB 0.03 0.00 1.94928 1.72973 -71.7939 -1.72973 1.72973 0.25 0.000186686 0.000170542 0.0120996 0.011037 -1 -1 -1 -1 32 1241 15 6.89349e+06 140938 586450. 2029.24 0.79 0.0763367 0.0663004 25474 144626 -1 1115 15 480 480 36716 8990 1.28867 1.28867 -71.8206 -1.28867 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.0067221 0.00597853 47 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 1.84 vpr 64.27 MiB -1 -1 0.13 18060 1 0.02 -1 -1 30428 -1 -1 9 49 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 25.0 MiB 0.05 1728 728 7103 1612 5339 152 64.3 MiB 0.03 0.00 2.48562 2.11206 -79.3567 -2.11206 2.11206 0.24 0.000195811 0.000179353 0.0083201 0.0075881 -1 -1 -1 -1 32 1358 40 6.89349e+06 126845 586450. 2029.24 0.39 0.0473056 0.0409139 25474 144626 -1 1164 15 521 521 41703 10584 1.18337 1.18337 -72.8866 -1.18337 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00721607 0.00641475 51 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 1.77 vpr 64.53 MiB -1 -1 0.12 17532 1 0.03 -1 -1 30508 -1 -1 11 57 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 25.4 MiB 0.06 1802 814 11641 2975 7882 784 64.5 MiB 0.04 0.00 2.40666 2.15606 -91.4368 -2.15606 2.15606 0.24 0.000220052 0.000200768 0.0124409 0.0113433 -1 -1 -1 -1 32 1545 15 6.89349e+06 155032 586450. 2029.24 0.29 0.0377863 0.0333776 25474 144626 -1 1324 19 534 534 42118 11208 1.26037 1.26037 -85.4089 -1.26037 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00944336 0.00835962 58 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.47 vpr 64.65 MiB -1 -1 0.14 17676 1 0.03 -1 -1 30504 -1 -1 12 65 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 25.6 MiB 0.06 1930 880 15627 3739 10944 944 64.7 MiB 0.08 0.00 2.56039 2.56039 -107.805 -2.56039 2.56039 0.24 0.000368579 0.000338259 0.0265098 0.0245221 -1 -1 -1 -1 32 1748 15 6.89349e+06 169126 586450. 2029.24 0.94 0.0917662 0.0811116 25474 144626 -1 1533 14 690 690 51852 13576 1.31337 1.31337 -98.3301 -1.31337 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00873069 0.00781067 67 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.00 vpr 64.76 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30692 -1 -1 18 97 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 24.9 MiB 0.07 3166 1546 32420 11579 18441 2400 64.8 MiB 0.11 0.00 3.83296 3.45705 -190.966 -3.45705 3.45705 0.24 0.000935119 0.000875924 0.0327955 0.0302908 -1 -1 -1 -1 32 2917 31 6.89349e+06 253689 586450. 2029.24 0.41 0.0903366 0.0815299 25474 144626 -1 2433 16 997 997 83200 20511 1.65467 1.65467 -160.881 -1.65467 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.013649 0.012318 99 2 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 2.35 vpr 65.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30136 -1 -1 24 129 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67316 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 26.4 MiB 0.07 4215 1897 53273 20437 29644 3192 65.7 MiB 0.17 0.00 4.72962 4.35372 -277.996 -4.35372 4.35372 0.24 0.000538663 0.000498151 0.0466986 0.0432372 -1 -1 -1 -1 32 3892 20 6.89349e+06 338252 586450. 2029.24 0.66 0.134776 0.122282 25474 144626 -1 3201 21 1413 1413 124031 31705 1.75832 1.75832 -211.545 -1.75832 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0230991 0.0209535 131 2 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt index 8d0853d10c4..68bca7c32e2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -1,1025 +1,1025 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 3.42 vpr 62.79 MiB -1 -1 0.38 18688 14 0.25 -1 -1 32944 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64300 32 32 277 309 1 202 103 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1547 9502 2152 6495 855 62.8 MiB 0.09 0.00 8.07544 -169.743 -8.07544 8.07544 0.32 0.000899886 0.000831959 0.0389219 0.0360116 -1 -1 -1 -1 28 3643 25 6.55708e+06 470145 500653. 1732.36 0.98 0.157731 0.138292 21310 115450 -1 3135 20 1428 5029 257339 61759 6.9613 6.9613 -157.642 -6.9613 0 0 612192. 2118.31 0.03 0.10 0.10 -1 -1 0.03 0.0374491 0.0327568 193 183 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 3.20 vpr 63.32 MiB -1 -1 0.41 18644 14 0.27 -1 -1 32760 -1 -1 39 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 30 32 272 304 1 193 101 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1322 7151 1527 4686 938 63.3 MiB 0.08 0.00 8.01406 -160.585 -8.01406 8.01406 0.31 0.000946647 0.000878015 0.0319553 0.0296902 -1 -1 -1 -1 28 3435 28 6.55708e+06 470145 500653. 1732.36 0.76 0.156061 0.136801 21310 115450 -1 2820 19 1177 3615 175609 44433 6.94704 6.94704 -150.651 -6.94704 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0360537 0.0316786 194 184 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 3.34 vpr 62.70 MiB -1 -1 0.34 18168 11 0.24 -1 -1 32492 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64200 32 32 280 312 1 190 104 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1349 9132 2022 6010 1100 62.7 MiB 0.09 0.00 6.82588 -135.752 -6.82588 6.82588 0.32 0.000906573 0.000836187 0.037231 0.0344479 -1 -1 -1 -1 26 3939 32 6.55708e+06 482200 477104. 1650.88 0.95 0.168247 0.147065 21022 109990 -1 3066 20 1319 4861 248158 60039 6.13352 6.13352 -135.053 -6.13352 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0380961 0.0333989 194 186 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 3.31 vpr 63.41 MiB -1 -1 0.36 18248 12 0.31 -1 -1 32832 -1 -1 41 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64932 29 32 275 307 1 193 102 17 17 289 -1 unnamed_device 23.8 MiB 0.09 1321 8432 1770 5951 711 63.4 MiB 0.08 0.00 7.97532 -148.743 -7.97532 7.97532 0.32 0.000904317 0.000838587 0.0356923 0.0329942 -1 -1 -1 -1 22 3603 44 6.55708e+06 494255 420624. 1455.45 0.94 0.186163 0.162104 20158 92377 -1 3227 16 1177 3853 213521 52797 7.1599 7.1599 -148.544 -7.1599 0 0 500653. 1732.36 0.02 0.08 0.08 -1 -1 0.02 0.0323126 0.0284639 200 190 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 3.37 vpr 62.98 MiB -1 -1 0.38 18384 13 0.27 -1 -1 32848 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64488 32 32 302 334 1 214 106 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1672 9856 2131 7054 671 63.0 MiB 0.11 0.00 8.06277 -168.566 -8.06277 8.06277 0.32 0.00100468 0.000929012 0.0474751 0.0438051 -1 -1 -1 -1 32 3848 27 6.55708e+06 506310 554710. 1919.41 0.76 0.185353 0.162891 22174 131602 -1 3263 16 1310 4212 205623 50945 7.27044 7.27044 -162.359 -7.27044 0 0 701300. 2426.64 0.04 0.09 0.11 -1 -1 0.04 0.0385923 0.0343556 217 208 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 3.24 vpr 62.84 MiB -1 -1 0.39 18616 13 0.24 -1 -1 32908 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 32 32 292 324 1 214 105 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1522 10479 2742 6826 911 62.8 MiB 0.11 0.00 8.0037 -160.293 -8.0037 8.0037 0.32 0.000938065 0.000869644 0.0437923 0.0405003 -1 -1 -1 -1 30 3477 18 6.55708e+06 494255 526063. 1820.29 0.74 0.158732 0.139622 21886 126133 -1 2963 16 1237 4638 205817 50427 6.61036 6.61036 -146.138 -6.61036 0 0 666494. 2306.21 0.03 0.09 0.12 -1 -1 0.03 0.0341773 0.0301008 207 198 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 2.76 vpr 62.60 MiB -1 -1 0.28 17976 12 0.19 -1 -1 32644 -1 -1 38 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 27 32 229 261 1 167 97 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1076 6757 1422 4783 552 62.6 MiB 0.06 0.00 7.57737 -131.413 -7.57737 7.57737 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64368 31 32 294 326 1 209 106 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1483 8106 1671 5747 688 62.9 MiB 0.08 0.00 7.93251 -162.97 -7.93251 7.93251 0.32 0.000936563 0.000867003 0.0341907 0.0316389 -1 -1 -1 -1 28 3774 24 6.55708e+06 518365 500653. 1732.36 0.83 0.157127 0.137205 21310 115450 -1 3076 16 1293 4466 214886 52808 7.0371 7.0371 -156.899 -7.0371 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0347474 0.0306354 209 203 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_107.v common 2.71 vpr 63.01 MiB -1 -1 0.32 18088 10 0.17 -1 -1 33092 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64520 29 32 219 251 1 150 92 17 17 289 -1 unnamed_device 23.2 MiB 0.09 1077 6716 1557 4320 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64904 32 32 288 320 1 207 102 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1453 7242 1384 5338 520 63.4 MiB 0.08 0.00 7.59394 -155.783 -7.59394 7.59394 0.29 0.000912161 0.000844874 0.0323359 0.0298935 -1 -1 -1 -1 26 3629 20 6.55708e+06 458090 477104. 1650.88 0.92 0.149908 0.131327 21022 109990 -1 3193 16 1125 4133 211646 50831 6.78904 6.78904 -148.172 -6.78904 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0325848 0.0286863 203 194 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_112.v common 3.18 vpr 63.54 MiB -1 -1 0.41 18664 13 0.28 -1 -1 32844 -1 -1 44 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 31 32 282 314 1 195 107 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1373 8203 1549 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fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_125.v common 2.82 vpr 62.85 MiB -1 -1 0.25 18372 12 0.22 -1 -1 32544 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 32 32 264 296 1 189 102 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1292 11050 2366 7675 1009 62.8 MiB 0.10 0.00 7.4882 -160.311 -7.4882 7.4882 0.32 0.000852834 0.000791169 0.0431371 0.0399693 -1 -1 -1 -1 32 2688 19 6.55708e+06 458090 554710. 1919.41 0.53 0.143565 0.126182 22174 131602 -1 2548 15 967 2908 141203 35435 6.62964 6.62964 -153.549 -6.62964 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0282648 0.0249116 183 170 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_126.v common 2.43 vpr 62.57 MiB -1 -1 0.27 17920 9 0.15 -1 -1 32444 -1 -1 32 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 25 32 183 215 1 133 89 17 17 289 -1 unnamed_device 22.9 MiB 0.07 884 9791 2362 5778 1651 62.6 MiB 0.07 0.00 5.75805 -100.808 -5.75805 5.75805 0.32 0.000611445 0.000567323 0.0322947 0.0299355 -1 -1 -1 -1 24 2013 19 6.55708e+06 385760 448715. 1552.65 0.49 0.102962 0.090186 20734 103517 -1 1761 18 600 1915 90275 23115 5.08326 5.08326 -98.1946 -5.08326 0 0 554710. 1919.41 0.02 0.03 0.06 -1 -1 0.02 0.0141287 0.0126477 118 110 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_127.v common 3.59 vpr 63.02 MiB -1 -1 0.31 18608 12 0.28 -1 -1 32768 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64528 32 32 300 332 1 216 104 17 17 289 -1 unnamed_device 23.9 MiB 0.13 1605 6936 1239 5241 456 63.0 MiB 0.08 0.00 7.69496 -166.719 -7.69496 7.69496 0.31 0.000958724 0.000888992 0.0307105 0.0284931 -1 -1 -1 -1 26 4186 35 6.55708e+06 482200 477104. 1650.88 1.04 0.170469 0.148547 21022 109990 -1 3459 25 1445 4477 264666 74433 6.75244 6.75244 -160.935 -6.75244 0 0 585099. 2024.56 0.03 0.12 0.09 -1 -1 0.03 0.0470212 0.0410556 213 206 -1 -1 -1 -1 - fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_128.v common 4.23 vpr 63.35 MiB -1 -1 0.43 18768 13 0.33 -1 -1 32756 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 31 32 290 322 1 209 102 17 17 289 -1 unnamed_device 23.6 MiB 0.13 1489 11050 2752 7035 1263 63.3 MiB 0.11 0.00 8.23989 -170.094 -8.23989 8.23989 0.32 0.000950408 0.000879111 0.0481654 0.0445422 -1 -1 -1 -1 26 4169 46 6.55708e+06 470145 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 299 247 1 188 95 17 17 289 -1 unnamed_device 23.6 MiB 0.21 995 8519 1888 6283 348 62.8 MiB 0.09 0.00 4.69952 -119.793 -4.69952 4.69952 0.32 0.000629047 0.000585652 0.0270416 0.0251595 -1 -1 -1 -1 26 2703 22 6.64007e+06 389298 477104. 1650.88 0.59 0.103803 0.0908653 21682 110474 -1 2071 19 1134 1713 100741 25334 3.82002 3.82002 -121.448 -3.82002 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0245892 0.021454 129 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.64 vpr 62.60 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30340 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 23.5 MiB 0.07 1008 16445 5394 8747 2304 62.6 MiB 0.16 0.00 4.53207 -121.894 -4.53207 4.53207 0.31 0.000634108 0.000588823 0.0522809 0.04853 -1 -1 -1 -1 32 2067 22 6.64007e+06 389298 554710. 1919.41 0.54 0.127898 0.113171 22834 132086 -1 1877 23 1086 2225 141232 33078 3.54423 3.54423 -113.215 -3.54423 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0281235 0.0244222 132 31 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.70 vpr 62.80 MiB -1 -1 0.23 18252 1 0.03 -1 -1 30416 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1067 12098 3452 7701 945 62.8 MiB 0.13 0.00 4.58601 -133.697 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23651 3.05137 3.05137 -112.229 -3.05137 0 0 701300. 2426.64 0.03 0.06 0.10 -1 -1 0.03 0.0301609 0.0264063 145 58 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.43 vpr 63.12 MiB -1 -1 0.23 18080 1 0.03 -1 -1 30572 -1 -1 21 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64636 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 23.5 MiB 0.08 751 11948 4103 6020 1825 63.1 MiB 0.10 0.00 3.76738 -102.601 -3.76738 3.76738 0.32 0.000553592 0.000515184 0.0404029 0.0376175 -1 -1 -1 -1 28 1527 20 6.64007e+06 263718 500653. 1732.36 0.48 0.10499 0.0926546 21970 115934 -1 1471 20 917 1568 101266 24667 2.74477 2.74477 -95.077 -2.74477 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0224191 0.0194903 97 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 31 32 317 271 1 168 87 17 17 289 -1 unnamed_device 23.5 MiB 0.16 906 5655 1194 4208 253 62.7 MiB 0.07 0.00 3.60222 -117.559 -3.60222 3.60222 0.32 0.000639636 0.000594878 0.0209485 0.0195041 -1 -1 -1 -1 28 2705 33 6.64007e+06 301392 500653. 1732.36 0.81 0.108644 0.0943614 21970 115934 -1 2030 20 1272 1882 135466 32452 3.48643 3.48643 -121.992 -3.48643 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0250351 0.0217808 117 64 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.55 vpr 62.54 MiB -1 -1 0.23 18256 1 0.03 -1 -1 30068 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64036 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 23.5 MiB 0.13 936 12323 3600 6804 1919 62.5 MiB 0.12 0.00 3.85841 -126.873 -3.85841 3.85841 0.32 0.000619093 0.000576413 0.0446968 0.0416188 -1 -1 -1 -1 32 1786 19 6.64007e+06 238602 554710. 1919.41 0.52 0.11678 0.103252 22834 132086 -1 1612 19 841 1348 82679 19678 2.65457 2.65457 -110.251 -2.65457 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0229212 0.0201044 115 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.54 vpr 62.74 MiB -1 -1 0.25 18388 1 0.03 -1 -1 30384 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.6 MiB 0.12 895 11106 3427 6381 1298 62.7 MiB 0.11 0.00 3.83641 -113.668 -3.83641 3.83641 0.32 0.00061658 0.000573067 0.0411971 0.0383264 -1 -1 -1 -1 32 1647 21 6.64007e+06 238602 554710. 1919.41 0.50 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fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 2.65 vpr 62.78 MiB -1 -1 0.13 18376 1 0.03 -1 -1 30344 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64284 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 23.8 MiB 0.21 1145 10803 2724 7364 715 62.8 MiB 0.12 0.00 4.40284 -140.386 -4.40284 4.40284 0.32 0.000709355 0.000659531 0.0383752 0.035603 -1 -1 -1 -1 30 2401 22 6.64007e+06 364182 526063. 1820.29 0.58 0.122776 0.107981 22546 126617 -1 2127 21 1359 2094 110426 27165 3.25703 3.25703 -124.202 -3.25703 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0291253 0.0254331 147 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.80 vpr 63.43 MiB -1 -1 0.16 18368 1 0.03 -1 -1 30268 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.13 989 17873 5923 8850 3100 63.4 MiB 0.17 0.00 4.77444 -137.586 -4.77444 4.77444 0.32 0.000712912 0.000662078 0.0594743 0.0552107 -1 -1 -1 -1 28 2617 24 6.64007e+06 426972 500653. 1732.36 0.75 0.150152 0.13295 21970 115934 -1 2048 20 1394 2351 145782 36264 4.26142 4.26142 -132.668 -4.26142 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.028755 0.0251025 139 61 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.41 vpr 62.78 MiB -1 -1 0.22 18068 1 0.03 -1 -1 30400 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 23.2 MiB 0.08 694 9234 2301 6256 677 62.8 MiB 0.08 0.00 3.09179 -89.0655 -3.09179 3.09179 0.32 0.000541072 0.000503614 0.0294454 0.0273744 -1 -1 -1 -1 28 1661 20 6.64007e+06 288834 500653. 1732.36 0.48 0.0926557 0.0812293 21970 115934 -1 1471 17 793 1316 76428 19287 2.75777 2.75777 -91.0915 -2.75777 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0192396 0.0167673 103 27 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 2.66 vpr 62.93 MiB -1 -1 0.26 18448 1 0.03 -1 -1 30352 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64440 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 23.9 MiB 0.13 1107 16003 5012 8992 1999 62.9 MiB 0.17 0.00 4.0781 -126.952 -4.0781 4.0781 0.32 0.000726709 0.000675037 0.05991 0.0556514 -1 -1 -1 -1 32 2297 19 6.64007e+06 339066 554710. 1919.41 0.57 0.144057 0.127765 22834 132086 -1 2105 20 1422 2537 151704 36359 3.12737 3.12737 -118.814 -3.12737 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0289797 0.0252666 138 58 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 2.89 vpr 62.89 MiB -1 -1 0.26 18396 1 0.03 -1 -1 30152 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64400 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 23.8 MiB 0.23 1061 17066 4730 9821 2515 62.9 MiB 0.17 0.00 4.48406 -140.639 -4.48406 4.48406 0.32 0.000693042 0.000644226 0.059948 0.0557361 -1 -1 -1 -1 32 2314 40 6.64007e+06 351624 554710. 1919.41 0.63 0.161734 0.142937 22834 132086 -1 1983 22 1194 1762 113331 28176 3.19063 3.19063 -122.439 -3.19063 0 0 701300. 2426.64 0.03 0.07 0.11 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 23.6 MiB 0.06 532 9543 2250 6629 664 62.8 MiB 0.07 0.00 2.4343 -77.8363 -2.4343 2.4343 0.31 0.000498159 0.00046299 0.0295526 0.0274642 -1 -1 -1 -1 28 1401 21 6.64007e+06 213486 500653. 1732.36 0.51 0.087921 0.0771578 21970 115934 -1 1137 19 688 980 63827 17614 1.86811 1.86811 -77.6028 -1.86811 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0187935 0.0163088 85 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 2.70 vpr 62.58 MiB -1 -1 0.24 18244 1 0.03 -1 -1 30440 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 31 32 291 243 1 171 88 17 17 289 -1 unnamed_device 23.5 MiB 0.24 847 10423 2562 6326 1535 62.6 MiB 0.10 0.00 5.02597 -142.893 -5.02597 5.02597 0.32 0.000610921 0.000568644 0.0349955 0.0325792 -1 -1 -1 -1 30 1856 17 6.64007e+06 313950 526063. 1820.29 0.53 0.103641 0.09137 22546 126617 -1 1527 13 585 825 49033 12151 3.62042 3.62042 -128.198 -3.62042 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.0183956 0.0162745 127 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.66 vpr 62.75 MiB -1 -1 0.24 18256 1 0.03 -1 -1 30520 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 23.8 MiB 0.07 1134 18196 5105 11197 1894 62.7 MiB 0.17 0.00 4.17176 -133.816 -4.17176 4.17176 0.32 0.000696533 0.000643934 0.0564419 0.0523516 -1 -1 -1 -1 30 2120 18 6.64007e+06 464646 526063. 1820.29 0.54 0.13621 0.120632 22546 126617 -1 1938 22 1156 1962 119310 27378 3.52443 3.52443 -126.017 -3.52443 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.03006 0.0262474 140 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 2.91 vpr 62.91 MiB -1 -1 0.26 18548 1 0.03 -1 -1 30292 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 23.8 MiB 0.23 1260 17591 5360 9925 2306 62.9 MiB 0.19 0.00 4.72719 -143.457 -4.72719 4.72719 0.35 0.000740177 0.000688771 0.0632155 0.0586458 -1 -1 -1 -1 32 2623 20 6.64007e+06 389298 554710. 1919.41 0.56 0.148536 0.131775 22834 132086 -1 2332 17 1286 2056 118473 28953 3.90649 3.90649 -129.764 -3.90649 0 0 701300. 2426.64 0.03 0.06 0.09 -1 -1 0.03 0.0257533 0.0225868 151 62 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.44 vpr 62.62 MiB -1 -1 0.21 18080 1 0.03 -1 -1 30528 -1 -1 20 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 23.2 MiB 0.09 426 10536 3993 4440 2103 62.6 MiB 0.07 0.00 2.50053 -67.6186 -2.50053 2.50053 0.32 0.000436929 0.000400303 0.0290515 0.0268679 -1 -1 -1 -1 32 1026 22 6.64007e+06 251160 554710. 1919.41 0.51 0.0817182 0.0716779 22834 132086 -1 874 18 548 811 45228 13433 1.97731 1.97731 -65.3841 -1.97731 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0152356 0.0132622 81 30 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.53 vpr 62.68 MiB -1 -1 0.22 17864 1 0.03 -1 -1 30276 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 23.6 MiB 0.07 962 6821 1380 5168 273 62.7 MiB 0.08 0.00 4.45587 -122.025 -4.45587 4.45587 0.32 0.000632837 0.000579639 0.0236586 0.0219696 -1 -1 -1 -1 32 2155 19 6.64007e+06 313950 554710. 1919.41 0.55 0.0955033 0.0835082 22834 132086 -1 1903 22 1221 2303 145599 33656 3.56023 3.56023 -116.407 -3.56023 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0269469 0.0234776 125 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.40 vpr 62.68 MiB -1 -1 0.20 17616 1 0.02 -1 -1 30032 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 23.4 MiB 0.05 506 11281 3424 5287 2570 62.7 MiB 0.07 0.00 2.72793 -76.1863 -2.72793 2.72793 0.31 0.000420089 0.000389775 0.0287434 0.0267156 -1 -1 -1 -1 26 1285 37 6.64007e+06 213486 477104. 1650.88 0.54 0.0765327 0.06757 21682 110474 -1 1002 13 438 511 40350 12151 2.30171 2.30171 -75.5155 -2.30171 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0124532 0.0109542 82 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.69 vpr 62.73 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30024 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 23.6 MiB 0.07 883 10031 2317 7175 539 62.7 MiB 0.10 0.00 4.605 -123.934 -4.605 4.605 0.32 0.000638244 0.000593242 0.0318232 0.0295403 -1 -1 -1 -1 26 2558 30 6.64007e+06 389298 477104. 1650.88 0.70 0.116775 0.102232 21682 110474 -1 1879 19 1105 1890 131855 36211 3.61243 3.61243 -115.665 -3.61243 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.024099 0.0210298 126 24 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.58 vpr 62.74 MiB -1 -1 0.23 17940 1 0.03 -1 -1 30444 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64244 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 23.5 MiB 0.06 983 19624 5667 10714 3243 62.7 MiB 0.17 0.00 3.74367 -107.154 -3.74367 3.74367 0.31 0.000643124 0.000596512 0.0541517 0.0501652 -1 -1 -1 -1 30 2029 21 6.64007e+06 489762 526063. 1820.29 0.55 0.129395 0.114647 22546 126617 -1 1826 21 1025 1901 115566 26955 2.81677 2.81677 -97.3789 -2.81677 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0265257 0.0230983 136 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.66 vpr 62.79 MiB -1 -1 0.24 18376 1 0.03 -1 -1 30248 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 32 32 338 277 1 179 99 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1102 15147 4066 9723 1358 62.8 MiB 0.15 0.00 4.9076 -137.928 -4.9076 4.9076 0.32 0.000693713 0.000642192 0.0478832 0.0443651 -1 -1 -1 -1 30 2217 21 6.64007e+06 439530 526063. 1820.29 0.53 0.127985 0.112974 22546 126617 -1 1976 19 975 1710 85252 20817 3.73962 3.73962 -125.26 -3.73962 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0265032 0.0231786 133 50 -1 -1 -1 -1 - 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64044 30 32 262 227 1 135 90 17 17 289 -1 unnamed_device 23.2 MiB 0.04 680 8733 1889 6137 707 62.5 MiB 0.08 0.00 3.24119 -95.6654 -3.24119 3.24119 0.24 0.000566872 0.000527984 0.0264591 0.0246154 -1 -1 -1 -1 32 1467 24 6.64007e+06 351624 554710. 1919.41 0.50 0.0951258 0.0831051 22834 132086 -1 1268 15 541 823 48367 12287 2.78097 2.78097 -89.3799 -2.78097 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0180998 0.0158592 100 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.42 vpr 62.76 MiB -1 -1 0.23 18080 1 0.03 -1 -1 30176 -1 -1 27 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64264 28 32 260 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1231 12606 3242 8430 934 63.5 MiB 0.13 0.00 4.47716 -125.986 -4.47716 4.47716 0.34 0.000742465 0.000690503 0.040033 0.0371622 -1 -1 -1 -1 30 2392 22 6.64007e+06 527436 526063. 1820.29 0.57 0.121338 0.107295 22546 126617 -1 2206 21 1094 2094 127085 27888 3.60143 3.60143 -119.17 -3.60143 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0305183 0.026678 158 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.79 vpr 63.49 MiB -1 -1 0.25 18340 1 0.04 -1 -1 30180 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65012 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1118 12208 2919 8273 1016 63.5 MiB 0.17 0.00 3.91238 -131.369 -3.91238 3.91238 0.32 0.000761885 0.000699352 0.055694 0.0515452 -1 -1 -1 -1 28 2461 21 6.64007e+06 514878 500653. 1732.36 0.57 0.144934 0.12814 21970 115934 -1 2208 19 1586 2620 148161 36739 2.95517 2.95517 -121.08 -2.95517 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0289413 0.0253146 150 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.72 vpr 62.75 MiB -1 -1 0.22 18372 1 0.03 -1 -1 30040 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 23.6 MiB 0.18 947 12938 4038 6585 2315 62.7 MiB 0.13 0.00 4.39563 -129.442 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25914 2.96196 2.96196 -104.515 -2.96196 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0301989 0.0263681 145 61 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 3.01 vpr 63.07 MiB -1 -1 0.27 18336 1 0.03 -1 -1 30264 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 31 32 377 302 1 234 99 17 17 289 -1 unnamed_device 24.2 MiB 0.36 1443 12183 2916 8073 1194 63.1 MiB 0.15 0.00 5.78896 -175.168 -5.78896 5.78896 0.34 0.000730371 0.000678859 0.042079 0.0390942 -1 -1 -1 -1 28 3186 22 6.64007e+06 452088 500653. 1732.36 0.59 0.124257 0.109624 21970 115934 -1 2704 21 1544 2373 159211 37709 4.84135 4.84135 -166.082 -4.84135 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0305437 0.0267185 178 64 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.98 vpr 62.88 MiB -1 -1 0.25 18228 1 0.03 -1 -1 30372 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 23.8 MiB 0.31 1234 12191 3319 7524 1348 62.9 MiB 0.14 0.00 5.10379 -154.62 -5.10379 5.10379 0.32 0.000745353 0.000692519 0.0442067 0.0410231 -1 -1 -1 -1 30 2528 23 6.64007e+06 401856 526063. 1820.29 0.56 0.134313 0.118402 22546 126617 -1 2128 20 1112 1738 94826 23161 4.27288 4.27288 -144.151 -4.27288 0 0 666494. 2306.21 0.04 0.08 0.11 -1 -1 0.04 0.0377662 0.0337785 167 64 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.73 vpr 62.80 MiB -1 -1 0.26 18420 1 0.03 -1 -1 30316 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1115 12860 3466 8442 952 62.8 MiB 0.13 0.00 4.70003 -136.748 -4.70003 4.70003 0.32 0.000715122 0.000665654 0.0417528 0.038773 -1 -1 -1 -1 26 2605 23 6.64007e+06 464646 477104. 1650.88 0.58 0.127608 0.112186 21682 110474 -1 2250 19 1232 2113 125509 30102 3.32883 3.32883 -120.962 -3.32883 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0270422 0.0236199 140 55 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.71 vpr 62.82 MiB -1 -1 0.24 18288 1 0.03 -1 -1 30260 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64332 32 32 291 242 1 179 93 17 17 289 -1 unnamed_device 23.7 MiB 0.17 1061 8073 1866 5827 380 62.8 MiB 0.09 0.00 4.40233 -117.896 -4.40233 4.40233 0.32 0.000615341 0.000573051 0.0259548 0.0241356 -1 -1 -1 -1 26 2518 23 6.64007e+06 364182 477104. 1650.88 0.66 0.102146 0.0893417 21682 110474 -1 2137 18 962 1522 106494 23971 3.50942 3.50942 -116.943 -3.50942 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0231839 0.0203345 125 27 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.03 vpr 63.46 MiB -1 -1 0.27 18732 1 0.03 -1 -1 30432 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 24.6 MiB 0.16 1312 16552 4366 10580 1606 63.5 MiB 0.18 0.00 5.1085 -163.706 -5.1085 5.1085 0.32 0.000866276 0.000805627 0.0599784 0.0556569 -1 -1 -1 -1 26 3108 25 6.64007e+06 539994 477104. 1650.88 0.74 0.169209 0.149122 21682 110474 -1 2610 21 1586 2418 149034 35187 4.18489 4.18489 -152.922 -4.18489 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0364613 0.0317981 176 87 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.51 vpr 62.67 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30204 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 23.4 MiB 0.08 705 8213 2081 5243 889 62.7 MiB 0.08 0.00 3.75024 -98.8591 -3.75024 3.75024 0.32 0.0005679 0.000526595 0.0263248 0.0244408 -1 -1 -1 -1 32 1549 22 6.64007e+06 288834 554710. 1919.41 0.53 0.100546 0.0878178 22834 132086 -1 1406 19 899 1604 92734 23078 2.74057 2.74057 -95.4429 -2.74057 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0216482 0.0188058 104 28 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 2.78 vpr 62.98 MiB -1 -1 0.25 18292 1 0.03 -1 -1 30248 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 24.0 MiB 0.22 1232 11863 3185 7621 1057 63.0 MiB 0.13 0.00 5.0773 -152.378 -5.0773 5.0773 0.32 0.000685702 0.000638075 0.0388617 0.0361442 -1 -1 -1 -1 30 2607 19 6.64007e+06 426972 526063. 1820.29 0.54 0.117632 0.103629 22546 126617 -1 2248 21 1248 1852 100468 23985 3.96729 3.96729 -135.475 -3.96729 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0289625 0.0253341 149 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.99 vpr 62.95 MiB -1 -1 0.17 18472 1 0.03 -1 -1 30352 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64456 32 32 349 284 1 183 102 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1221 11764 2967 7709 1088 62.9 MiB 0.12 0.00 3.95307 -117.525 -3.95307 3.95307 0.32 0.000696024 0.000644408 0.0366916 0.0340243 -1 -1 -1 -1 22 3240 30 6.64007e+06 477204 420624. 1455.45 0.98 0.131608 0.11527 20818 92861 -1 2548 19 1326 2488 176484 42475 3.19957 3.19957 -118.379 -3.19957 0 0 500653. 1732.36 0.02 0.07 0.08 -1 -1 0.02 0.0262585 0.0229142 137 53 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 2.58 vpr 62.59 MiB -1 -1 0.23 17800 1 0.03 -1 -1 30212 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64096 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 23.5 MiB 0.07 900 13147 4476 6141 2530 62.6 MiB 0.13 0.00 4.20356 -122.292 -4.20356 4.20356 0.31 0.000620913 0.00057678 0.0422596 0.0392478 -1 -1 -1 -1 32 2124 24 6.64007e+06 339066 554710. 1919.41 0.57 0.118883 0.104795 22834 132086 -1 1774 20 1016 2010 121136 29266 3.34003 3.34003 -110.91 -3.34003 0 0 701300. 2426.64 0.03 0.06 0.12 -1 -1 0.03 0.0252076 0.0219955 127 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.84 vpr 63.38 MiB -1 -1 0.23 18376 1 0.03 -1 -1 30420 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64904 32 32 353 287 1 198 94 17 17 289 -1 unnamed_device 23.8 MiB 0.24 1217 9679 2220 6521 938 63.4 MiB 0.12 0.00 4.87535 -142.566 -4.87535 4.87535 0.32 0.00070198 0.000652914 0.0343575 0.0319558 -1 -1 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64216 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 23.6 MiB 0.07 1023 10540 2564 7150 826 62.7 MiB 0.10 0.00 4.27093 -125.084 -4.27093 4.27093 0.30 0.000635854 0.000590624 0.0312502 0.0290072 -1 -1 -1 -1 32 2034 20 6.64007e+06 452088 554710. 1919.41 0.53 0.105906 0.0929137 22834 132086 -1 1819 20 1043 1996 118484 27523 3.47223 3.47223 -116.792 -3.47223 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0255077 0.0222584 127 24 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.67 vpr 62.80 MiB -1 -1 0.14 18480 1 0.03 -1 -1 30144 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 319 257 1 198 93 17 17 289 -1 unnamed_device 23.8 MiB 0.21 1094 10173 2429 6748 996 62.8 MiB 0.11 0.00 5.10621 -136.906 -5.10621 5.10621 0.32 0.000655901 0.000609938 0.0340695 0.0316782 -1 -1 -1 -1 32 2080 22 6.64007e+06 364182 554710. 1919.41 0.54 0.113192 0.0993888 22834 132086 -1 1862 19 1043 1542 79123 20468 3.86682 3.86682 -126.192 -3.86682 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0252548 0.0221089 138 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 3.08 vpr 62.86 MiB -1 -1 0.27 18376 1 0.03 -1 -1 30320 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 23.8 MiB 0.20 1155 14373 4323 8054 1996 62.9 MiB 0.17 0.00 5.05909 -147.227 -5.05909 5.05909 0.37 0.000731719 0.000678738 0.0525936 0.0488573 -1 -1 -1 -1 28 3203 22 6.64007e+06 376740 500653. 1732.36 0.81 0.144202 0.127554 21970 115934 -1 2573 21 1432 2292 195574 43376 4.02669 4.02669 -136.225 -4.02669 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0299494 0.0260903 152 62 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.73 vpr 62.93 MiB -1 -1 0.19 18476 1 0.03 -1 -1 30188 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 23.8 MiB 0.15 1136 14147 4526 7649 1972 62.9 MiB 0.16 0.00 4.38816 -135.074 -4.38816 4.38816 0.32 0.000743004 0.000687682 0.0564022 0.052172 -1 -1 -1 -1 30 2565 21 6.64007e+06 313950 526063. 1820.29 0.59 0.145234 0.128316 22546 126617 -1 2247 16 1212 2170 142450 32357 3.63163 3.63163 -128.953 -3.63163 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0246587 0.0216156 141 77 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.63 vpr 63.07 MiB -1 -1 0.22 18120 1 0.03 -1 -1 30300 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 251 219 1 140 94 17 17 289 -1 unnamed_device 23.3 MiB 0.08 923 15643 4702 9042 1899 63.1 MiB 0.13 0.00 3.5543 -104.7 -3.5543 3.5543 0.32 0.00055848 0.000519887 0.0433436 0.0403444 -1 -1 -1 -1 28 1834 21 6.64007e+06 376740 500653. 1732.36 0.56 0.108027 0.0957526 21970 115934 -1 1668 22 937 1393 89639 21079 2.65657 2.65657 -97.5617 -2.65657 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0239942 0.0208508 101 23 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.67 vpr 63.50 MiB -1 -1 0.16 18272 1 0.03 -1 -1 30040 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65020 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 23.9 MiB 0.19 1003 17023 5521 9148 2354 63.5 MiB 0.17 0.00 4.05053 -136.563 -4.05053 4.05053 0.32 0.000667134 0.000619094 0.0589093 0.0547082 -1 -1 -1 -1 32 2363 20 6.64007e+06 339066 554710. 1919.41 0.56 0.140709 0.125069 22834 132086 -1 2016 20 1250 1804 125844 29633 3.39003 3.39003 -130.188 -3.39003 0 0 701300. 2426.64 0.03 0.07 0.09 -1 -1 0.03 0.02694 0.0234839 133 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.84 vpr 62.91 MiB -1 -1 0.26 18464 1 0.03 -1 -1 30344 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 387 293 1 234 99 17 17 289 -1 unnamed_device 24.0 MiB 0.21 1435 16059 4481 10134 1444 62.9 MiB 0.17 0.00 5.58406 -162.308 -5.58406 5.58406 0.31 0.000764097 0.000710561 0.0566155 0.0526078 -1 -1 -1 -1 32 3124 21 6.64007e+06 439530 554710. 1919.41 0.58 0.147297 0.130581 22834 132086 -1 2675 22 1593 2519 150795 35527 4.87408 4.87408 -154.358 -4.87408 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0330463 0.028895 174 31 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.56 vpr 63.39 MiB -1 -1 0.17 18576 1 0.03 -1 -1 30528 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1083 12240 2973 8199 1068 63.4 MiB 0.12 0.00 4.33282 -136.421 -4.33282 4.33282 0.32 0.000691046 0.000642837 0.0380761 0.0353909 -1 -1 -1 -1 32 2036 19 6.64007e+06 477204 554710. 1919.41 0.54 0.117898 0.103855 22834 132086 -1 1889 22 1182 1950 109230 27017 2.85617 2.85617 -116.634 -2.85617 0 0 701300. 2426.64 0.03 0.07 0.10 -1 -1 0.03 0.0294348 0.0256088 141 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.47 vpr 62.55 MiB -1 -1 0.24 18040 1 0.03 -1 -1 30292 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 23.5 MiB 0.05 787 15647 4513 8348 2786 62.6 MiB 0.13 0.00 3.51327 -106.246 -3.51327 3.51327 0.32 0.000603837 0.000561213 0.0453604 0.0421794 -1 -1 -1 -1 32 1767 19 6.64007e+06 414414 554710. 1919.41 0.51 0.113315 0.100197 22834 132086 -1 1434 19 732 1177 64731 16326 2.73257 2.73257 -98.3112 -2.73257 0 0 701300. 2426.64 0.03 0.04 0.12 -1 -1 0.03 0.0169393 0.0148555 111 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.53 vpr 63.23 MiB -1 -1 0.26 18632 1 0.03 -1 -1 30244 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64744 32 32 431 332 1 235 97 17 17 289 -1 unnamed_device 24.4 MiB 0.31 1370 17635 5043 10114 2478 63.2 MiB 0.21 0.00 6.37067 -183.955 -6.37067 6.37067 0.32 0.000827281 0.000769095 0.0686146 0.0637394 -1 -1 -1 -1 26 3739 28 6.64007e+06 414414 477104. 1650.88 1.06 0.183963 0.163024 21682 110474 -1 2914 23 2106 3156 231468 52338 5.05174 5.05174 -171.67 -5.05174 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0364787 0.031749 177 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.78 vpr 62.80 MiB -1 -1 0.24 18536 1 0.03 -1 -1 30456 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1059 19142 5710 10959 2473 62.8 MiB 0.17 0.00 4.53287 -137.071 -4.53287 4.53287 0.35 0.000694142 0.000645825 0.0585836 0.0543714 -1 -1 -1 -1 32 2159 21 6.64007e+06 477204 554710. 1919.41 0.56 0.141425 0.1254 22834 132086 -1 1899 16 1017 1621 90851 21605 3.65443 3.65443 -127.571 -3.65443 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0232201 0.0203952 136 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.57 vpr 62.96 MiB -1 -1 0.21 17880 1 0.05 -1 -1 30276 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 231 199 1 140 93 17 17 289 -1 unnamed_device 23.4 MiB 0.06 697 14793 4064 8312 2417 63.0 MiB 0.12 0.00 3.58247 -96.388 -3.58247 3.58247 0.34 0.000536007 0.000498696 0.0399856 0.0372164 -1 -1 -1 -1 30 1597 22 6.64007e+06 364182 526063. 1820.29 0.51 0.104438 0.0921129 22546 126617 -1 1300 17 603 1018 57376 14793 2.68557 2.68557 -89.2135 -2.68557 0 0 666494. 2306.21 0.03 0.05 0.09 -1 -1 0.03 0.0188683 0.0164977 103 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.72 vpr 63.45 MiB -1 -1 0.13 18472 1 0.03 -1 -1 30204 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1247 19624 5520 11864 2240 63.4 MiB 0.19 0.00 5.68826 -140.03 -5.68826 5.68826 0.39 0.000705253 0.000655769 0.0593179 0.0551102 -1 -1 -1 -1 32 2366 18 6.64007e+06 502320 554710. 1919.41 0.54 0.139797 0.12415 22834 132086 -1 2129 14 824 1693 109078 25009 4.42708 4.42708 -129.323 -4.42708 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.021665 0.0190537 147 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.60 vpr 62.49 MiB -1 -1 0.22 17892 1 0.03 -1 -1 30152 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63992 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 23.2 MiB 0.07 838 15831 5106 8362 2363 62.5 MiB 0.13 0.00 3.5273 -107.609 -3.5273 3.5273 0.34 0.000557504 0.000519197 0.0480485 0.0446917 -1 -1 -1 -1 28 1874 20 6.64007e+06 288834 500653. 1732.36 0.55 0.114684 0.101665 21970 115934 -1 1689 20 1084 1860 116033 27873 2.77177 2.77177 -103.603 -2.77177 0 0 612192. 2118.31 0.03 0.06 0.11 -1 -1 0.03 0.0221893 0.0192968 107 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.88 vpr 62.60 MiB -1 -1 0.26 18212 1 0.02 -1 -1 30088 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 23.5 MiB 0.11 893 14252 4195 7695 2362 62.6 MiB 0.12 0.00 4.06561 -110.624 -4.06561 4.06561 0.32 0.000598189 0.000554889 0.0387015 0.0359501 -1 -1 -1 -1 28 2003 16 6.64007e+06 477204 500653. 1732.36 0.52 0.105135 0.0927138 21970 115934 -1 1666 21 1086 2090 130293 30391 2.82057 2.82057 -103.094 -2.82057 0 0 612192. 2118.31 0.03 0.07 0.13 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64348 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 23.8 MiB 0.11 925 11719 2758 8119 842 62.8 MiB 0.12 0.00 4.42033 -138.276 -4.42033 4.42033 0.32 0.00071589 0.000664168 0.0433359 0.0402562 -1 -1 -1 -1 32 2161 23 6.64007e+06 339066 554710. 1919.41 0.57 0.129395 0.113987 22834 132086 -1 1727 20 1284 1944 114196 28932 3.78702 3.78702 -131.455 -3.78702 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0279344 0.02439 135 54 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.92 vpr 62.80 MiB -1 -1 0.21 18364 1 0.03 -1 -1 30232 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1091 11798 3080 7487 1231 62.8 MiB 0.13 0.00 4.78258 -142.686 -4.78258 4.78258 0.32 0.000714923 0.00066408 0.0396764 0.0368336 -1 -1 -1 -1 32 2192 17 6.64007e+06 426972 554710. 1919.41 0.80 0.12021 0.105957 22834 132086 -1 2011 16 897 1626 93283 22441 3.62362 3.62362 -128.218 -3.62362 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0237017 0.020821 136 51 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.70 vpr 62.63 MiB -1 -1 0.23 18024 1 0.03 -1 -1 30240 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64136 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 23.5 MiB 0.22 888 6701 1459 4931 311 62.6 MiB 0.08 0.00 4.75515 -130.083 -4.75515 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3.24903 -118.128 -3.24903 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0261712 0.0227742 117 64 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.80 vpr 63.27 MiB -1 -1 0.23 18488 1 0.03 -1 -1 30384 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64788 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 23.5 MiB 0.10 943 16973 4825 9365 2783 63.3 MiB 0.16 0.00 3.65867 -98.2101 -3.65867 3.65867 0.36 0.000510479 0.000470115 0.0491293 0.0452299 -1 -1 -1 -1 26 2242 21 6.64007e+06 452088 477104. 1650.88 0.67 0.122474 0.109111 21682 110474 -1 1867 18 917 1784 103434 25819 2.77377 2.77377 -96.2306 -2.77377 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0239279 0.0208916 128 57 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.56 vpr 62.76 MiB -1 -1 0.22 18036 1 0.03 -1 -1 30368 -1 -1 39 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 23.6 MiB 0.07 826 16971 4935 9183 2853 62.8 MiB 0.13 0.00 4.21293 -101.023 -4.21293 4.21293 0.33 0.000596135 0.000555002 0.0460918 0.0427488 -1 -1 -1 -1 28 1907 22 6.64007e+06 489762 500653. 1732.36 0.56 0.117192 0.10326 21970 115934 -1 1601 16 895 1627 90491 22777 3.47223 3.47223 -98.8073 -3.47223 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0195628 0.0171324 122 27 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 2.69 vpr 62.73 MiB -1 -1 0.24 18280 1 0.03 -1 -1 30360 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64232 30 32 317 269 1 152 84 17 17 289 -1 unnamed_device 23.6 MiB 0.13 892 13809 4602 7006 2201 62.7 MiB 0.14 0.00 3.90078 -115.622 -3.90078 3.90078 0.33 0.000645832 0.000599449 0.050946 0.0472279 -1 -1 -1 -1 32 1908 21 6.64007e+06 276276 554710. 1919.41 0.55 0.126734 0.111982 22834 132086 -1 1778 20 1210 2120 133437 31075 2.88777 2.88777 -110.499 -2.88777 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0256155 0.0222677 115 63 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 2.70 vpr 63.13 MiB -1 -1 0.23 18464 1 0.03 -1 -1 30084 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 24.2 MiB 0.20 1023 8934 2025 6373 536 63.1 MiB 0.10 0.00 4.0127 -132.01 -4.0127 4.0127 0.32 0.000666492 0.000619785 0.0319045 0.0296427 -1 -1 -1 -1 32 2101 18 6.64007e+06 326508 554710. 1919.41 0.51 0.108114 0.0949131 22834 132086 -1 1856 21 999 1501 89591 21554 3.43523 3.43523 -127.963 -3.43523 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0271682 0.0236631 127 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.58 vpr 62.80 MiB -1 -1 0.24 17836 1 0.03 -1 -1 30480 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 23.7 MiB 0.07 1062 14252 3702 8136 2414 62.8 MiB 0.13 0.00 4.61901 -130.215 -4.61901 4.61901 0.32 0.00064055 0.000596427 0.041619 0.0387028 -1 -1 -1 -1 32 2215 21 6.64007e+06 464646 554710. 1919.41 0.54 0.116815 0.103213 22834 132086 -1 1898 17 890 1636 102846 23210 3.48123 3.48123 -116.227 -3.48123 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0230624 0.0202398 134 4 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 2.84 vpr 62.77 MiB -1 -1 0.24 18520 1 0.03 -1 -1 30404 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 32 32 350 275 1 209 94 17 17 289 -1 unnamed_device 23.7 MiB 0.24 1264 11809 2906 7681 1222 62.8 MiB 0.15 0.00 5.33287 -167.061 -5.33287 5.33287 0.32 0.000711346 0.000661641 0.0419297 0.0389822 -1 -1 -1 -1 32 2723 21 6.64007e+06 376740 554710. 1919.41 0.55 0.127635 0.112686 22834 132086 -1 2415 23 1397 2174 128896 30488 4.21368 4.21368 -151.829 -4.21368 0 0 701300. 2426.64 0.03 0.08 0.13 -1 -1 0.03 0.0317654 0.0277194 151 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 2.72 vpr 62.87 MiB -1 -1 0.26 18388 1 0.03 -1 -1 30268 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64380 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1057 12556 3111 8883 562 62.9 MiB 0.13 0.00 4.57304 -141.272 -4.57304 4.57304 0.31 0.000744694 0.000690509 0.0434462 0.0401677 -1 -1 -1 -1 32 2404 16 6.64007e+06 464646 554710. 1919.41 0.58 0.125349 0.110487 22834 132086 -1 2052 22 1123 2086 137496 32021 3.42483 3.42483 -130.344 -3.42483 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.029294 0.0260026 143 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.17 vpr 63.51 MiB -1 -1 0.26 18504 1 0.03 -1 -1 30284 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1171 22877 7507 12807 2563 63.5 MiB 0.23 0.00 4.50063 -140.698 -4.50063 4.50063 0.32 0.000749823 0.000696543 0.0707641 0.0655291 -1 -1 -1 -1 28 2865 24 6.64007e+06 539994 500653. 1732.36 0.90 0.167847 0.148857 21970 115934 -1 2354 20 1509 2767 177950 42009 3.57023 3.57023 -133.916 -3.57023 0 0 612192. 2118.31 0.03 0.08 0.12 -1 -1 0.03 0.0272378 0.0238892 147 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 2.60 vpr 62.66 MiB -1 -1 0.23 18124 1 0.03 -1 -1 30212 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64160 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 23.3 MiB 0.11 713 13403 2936 9754 713 62.7 MiB 0.13 0.00 3.93272 -112.862 -3.93272 3.93272 0.31 0.000588042 0.00054711 0.0455557 0.0424041 -1 -1 -1 -1 32 1671 23 6.64007e+06 263718 554710. 1919.41 0.52 0.115722 0.102349 22834 132086 -1 1388 20 927 1637 89572 23518 2.75957 2.75957 -98.8479 -2.75957 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0231273 0.0201238 109 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 3.00 vpr 62.96 MiB -1 -1 0.15 18372 1 0.03 -1 -1 30400 -1 -1 27 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 23.9 MiB 0.14 908 7613 1681 5486 446 63.0 MiB 0.10 0.00 4.75724 -137.047 -4.75724 4.75724 0.33 0.000703115 0.000651164 0.0304087 0.0282733 -1 -1 -1 -1 30 2039 24 6.64007e+06 339066 526063. 1820.29 0.56 0.119796 0.104771 22546 126617 -1 1732 22 1329 2144 119677 29049 3.74463 3.74463 -129.51 -3.74463 0 0 666494. 2306.21 0.03 0.07 0.11 -1 -1 0.03 0.0308961 0.0269019 147 63 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 3.26 vpr 62.89 MiB -1 -1 0.25 18264 1 0.03 -1 -1 30268 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64404 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 23.9 MiB 0.15 1241 16708 5056 9561 2091 62.9 MiB 0.17 0.00 5.42161 -159.498 -5.42161 5.42161 0.32 0.000693499 0.000644788 0.0566391 0.0526498 -1 -1 -1 -1 26 3049 24 6.64007e+06 376740 477104. 1650.88 0.83 0.146388 0.129818 21682 110474 -1 2440 19 1446 2309 162344 36787 4.11869 4.11869 -142.164 -4.11869 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0265234 0.0231856 145 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 3.11 vpr 62.77 MiB -1 -1 0.22 18420 1 0.03 -1 -1 30276 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 23.8 MiB 0.19 1123 13148 3656 8360 1132 62.8 MiB 0.13 0.00 5.23915 -149.423 -5.23915 5.23915 0.31 0.000682659 0.00063482 0.0427424 0.0397167 -1 -1 -1 -1 32 2371 21 6.64007e+06 439530 554710. 1919.41 0.54 0.123323 0.108794 22834 132086 -1 2007 20 1118 1785 91779 24235 4.30908 4.30908 -140.1 -4.30908 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0272733 0.0238268 151 47 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.71 vpr 62.93 MiB -1 -1 0.16 18440 1 0.03 -1 -1 30492 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64440 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 23.9 MiB 0.22 1096 17964 4891 10960 2113 62.9 MiB 0.18 0.00 4.57324 -135.589 -4.57324 4.57324 0.32 0.000715024 0.000664031 0.0584301 0.0540634 -1 -1 -1 -1 32 2160 21 6.64007e+06 477204 554710. 1919.41 0.53 0.142222 0.125744 22834 132086 -1 1911 16 768 1346 77420 19006 3.06843 3.06843 -112.699 -3.06843 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0244076 0.0214461 144 83 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 3.14 vpr 62.87 MiB -1 -1 0.23 18512 1 0.03 -1 -1 30348 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64376 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1118 14939 4252 9072 1615 62.9 MiB 0.17 0.00 5.0668 -145.309 -5.0668 5.0668 0.32 0.000833667 0.000783031 0.0571683 0.0531632 -1 -1 -1 -1 26 2741 21 6.64007e+06 313950 477104. 1650.88 0.64 0.143122 0.126843 21682 110474 -1 2256 19 1322 2385 155087 35915 4.12322 4.12322 -139.521 -4.12322 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0275269 0.0240294 141 57 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 2.60 vpr 63.55 MiB -1 -1 0.22 18320 1 0.02 -1 -1 30212 -1 -1 39 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 29 32 378 310 1 177 100 17 17 289 -1 unnamed_device 23.9 MiB 0.12 968 16340 4628 9035 2677 63.5 MiB 0.15 0.00 4.31346 -118.41 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2.91797 2.91797 -103.429 -2.91797 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0189262 0.0167874 99 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.89 vpr 62.98 MiB -1 -1 0.25 18504 1 0.03 -1 -1 30276 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 23.9 MiB 0.20 1044 14235 4068 7633 2534 63.0 MiB 0.16 0.00 4.71503 -140.381 -4.71503 4.71503 0.32 0.000736638 0.000684303 0.0542958 0.0503407 -1 -1 -1 -1 32 2187 20 6.64007e+06 439530 554710. 1919.41 0.64 0.16213 0.14341 22834 132086 -1 1906 20 1054 1793 106697 26383 3.63163 3.63163 -128.238 -3.63163 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0285345 0.0249014 135 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 2.91 vpr 62.84 MiB -1 -1 0.16 18280 1 0.03 -1 -1 30280 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 23.8 MiB 0.15 1159 10979 2643 7096 1240 62.8 MiB 0.13 0.00 4.8332 -152.333 -4.8332 4.8332 0.31 0.000764668 0.000709401 0.0465756 0.0431972 -1 -1 -1 -1 32 2514 24 6.64007e+06 313950 554710. 1919.41 0.63 0.140961 0.124202 22834 132086 -1 2265 22 1721 2851 169988 41091 3.69343 3.69343 -141.542 -3.69343 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0324477 0.0282823 155 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.86 vpr 62.62 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30408 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64128 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 23.6 MiB 0.19 1035 13157 3525 7788 1844 62.6 MiB 0.12 0.00 4.01361 -116.472 -4.01361 4.01361 0.32 0.000582519 0.00054112 0.0410765 0.0382132 -1 -1 -1 -1 26 2306 22 6.64007e+06 313950 477104. 1650.88 0.58 0.111377 0.0982278 21682 110474 -1 1974 17 851 1156 77563 18531 3.24903 3.24903 -111.931 -3.24903 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0206446 0.0180703 117 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 2.45 vpr 62.66 MiB -1 -1 0.23 17704 1 0.03 -1 -1 30328 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 23.4 MiB 0.06 846 9725 2485 6513 727 62.7 MiB 0.09 0.00 3.92438 -112.401 -3.92438 3.92438 0.32 0.000560266 0.000521845 0.0308085 0.0286528 -1 -1 -1 -1 26 1894 21 6.64007e+06 288834 477104. 1650.88 0.49 0.0963775 0.0845534 21682 110474 -1 1562 19 974 1584 90066 21476 3.02517 3.02517 -107.603 -3.02517 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0214189 0.018672 110 4 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 2.92 vpr 63.04 MiB -1 -1 0.25 18416 1 0.03 -1 -1 30548 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 348 274 1 211 95 17 17 289 -1 unnamed_device 23.9 MiB 0.21 1202 16295 5063 8969 2263 63.0 MiB 0.17 0.00 4.9923 -151.371 -4.9923 4.9923 0.32 0.000724101 0.000665988 0.0564527 0.0523689 -1 -1 -1 -1 28 2863 20 6.64007e+06 389298 500653. 1732.36 0.61 0.14137 0.125434 21970 115934 -1 2461 21 1706 2305 171976 40971 4.39829 4.39829 -154.305 -4.39829 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0290397 0.0253404 151 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 3.39 vpr 62.80 MiB -1 -1 0.26 18292 1 0.03 -1 -1 30352 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64308 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 23.8 MiB 0.57 1281 17021 5038 9582 2401 62.8 MiB 0.17 0.00 5.34218 -153.803 -5.34218 5.34218 0.31 0.000703995 0.000654128 0.0536258 0.0497985 -1 -1 -1 -1 26 2998 23 6.64007e+06 464646 477104. 1650.88 0.69 0.143557 0.127182 21682 110474 -1 2507 20 1387 2164 152866 35335 4.42928 4.42928 -150.345 -4.42928 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0279346 0.0244075 157 56 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.83 vpr 63.50 MiB -1 -1 0.22 18104 1 0.03 -1 -1 30128 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 23.8 MiB 0.08 1267 17817 5114 10804 1899 63.5 MiB 0.17 0.00 5.50127 -148.27 -5.50127 5.50127 0.32 0.000728707 0.000677247 0.0534885 0.0496414 -1 -1 -1 -1 26 3165 21 6.64007e+06 539994 477104. 1650.88 0.75 0.150128 0.133373 21682 110474 -1 2620 21 1637 3007 196047 46131 4.58248 4.58248 -146.607 -4.58248 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0303632 0.0265432 162 3 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.47 vpr 63.33 MiB -1 -1 0.16 18544 1 0.03 -1 -1 30320 -1 -1 35 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 30 32 316 264 1 162 97 17 17 289 -1 unnamed_device 23.6 MiB 0.11 960 10531 2688 6948 895 63.3 MiB 0.10 0.00 3.53527 -104.629 -3.53527 3.53527 0.31 0.000642209 0.000597715 0.0327903 0.0304946 -1 -1 -1 -1 32 2029 21 6.64007e+06 439530 554710. 1919.41 0.53 0.108188 0.0949357 22834 132086 -1 1762 19 983 1688 92821 22824 2.84297 2.84297 -99.6625 -2.84297 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0302453 0.0267024 124 52 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.41 vpr 62.96 MiB -1 -1 0.21 18040 1 0.04 -1 -1 30284 -1 -1 25 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64472 27 32 255 219 1 132 84 17 17 289 -1 unnamed_device 23.4 MiB 0.06 787 11430 3535 6029 1866 63.0 MiB 0.09 0.00 3.4653 -96.8105 -3.4653 3.4653 0.31 0.000547949 0.000510433 0.0361061 0.0336224 -1 -1 -1 -1 26 1657 21 6.64007e+06 313950 477104. 1650.88 0.51 0.100455 0.088336 21682 110474 -1 1422 19 813 1258 87749 20598 2.78277 2.78277 -93.1625 -2.78277 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0211257 0.0183388 100 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 3.07 vpr 63.09 MiB -1 -1 0.27 18656 1 0.03 -1 -1 30364 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64600 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 24.1 MiB 0.23 1365 11573 2824 7922 827 63.1 MiB 0.14 0.00 4.52455 -140.933 -4.52455 4.52455 0.32 0.000801412 0.000743847 0.044303 0.0411451 -1 -1 -1 -1 28 3529 23 6.64007e+06 426972 500653. 1732.36 0.77 0.146905 0.129572 21970 115934 -1 2746 20 1678 2838 184848 42937 3.85503 3.85503 -135.927 -3.85503 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0325576 0.02856 176 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 2.99 vpr 62.80 MiB -1 -1 0.26 18276 1 0.04 -1 -1 30228 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 23.8 MiB 0.39 1024 16371 4802 8876 2693 62.8 MiB 0.16 0.00 5.51727 -159.864 -5.51727 5.51727 0.34 0.000713016 0.000661963 0.0620014 0.0576154 -1 -1 -1 -1 32 2133 17 6.64007e+06 339066 554710. 1919.41 0.54 0.143857 0.128081 22834 132086 -1 1963 20 1100 1863 103525 26373 4.38608 4.38608 -146.744 -4.38608 0 0 701300. 2426.64 0.03 0.08 0.12 -1 -1 0.03 0.0371557 0.0323725 151 64 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 2.77 vpr 62.68 MiB -1 -1 0.25 18380 1 0.04 -1 -1 30364 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 331 280 1 174 87 17 17 289 -1 unnamed_device 23.5 MiB 0.29 989 13335 4742 6776 1817 62.7 MiB 0.13 0.00 4.37915 -137.641 -4.37915 4.37915 0.32 0.000658109 0.000611873 0.048245 0.0448417 -1 -1 -1 -1 32 1903 19 6.64007e+06 288834 554710. 1919.41 0.52 0.124693 0.110299 22834 132086 -1 1693 13 628 883 56758 13715 3.17522 3.17522 -121.439 -3.17522 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0196211 0.017333 130 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.90 vpr 63.40 MiB -1 -1 0.24 18384 1 0.03 -1 -1 30344 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1105 13092 3416 8740 936 63.4 MiB 0.13 0.00 5.28888 -136.917 -5.28888 5.28888 0.32 0.000682744 0.000636151 0.0406021 0.0377399 -1 -1 -1 -1 26 2483 21 6.64007e+06 452088 477104. 1650.88 0.57 0.121401 0.10708 21682 110474 -1 2105 18 1009 1726 98465 23986 3.85982 3.85982 -125.513 -3.85982 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0247052 0.0216352 133 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.03 vpr 63.57 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30372 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 31 32 373 294 1 196 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1122 12321 3316 8274 731 63.6 MiB 0.13 0.00 4.92332 -128.094 -4.92332 4.92332 0.34 0.00073579 0.000681292 0.0411424 0.0381693 -1 -1 -1 -1 26 2511 21 6.64007e+06 477204 477104. 1650.88 0.52 0.127987 0.112686 21682 110474 -1 2210 19 1199 1943 114142 28132 3.83382 3.83382 -125.259 -3.83382 0 0 585099. 2024.56 0.03 0.07 0.08 -1 -1 0.03 0.0283169 0.0247367 151 50 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.79 vpr 63.06 MiB -1 -1 0.21 18440 1 0.03 -1 -1 30380 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 23.9 MiB 0.12 937 16973 5746 8109 3118 63.1 MiB 0.15 0.00 3.65167 -103.348 -3.65167 3.65167 0.31 0.000656815 0.000608992 0.0517459 0.048035 -1 -1 -1 -1 30 2391 26 6.64007e+06 452088 526063. 1820.29 0.71 0.136006 0.120034 22546 126617 -1 1842 21 1098 2007 113299 28167 2.97317 2.97317 -100.808 -2.97317 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0272394 0.0237126 130 51 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 2.84 vpr 62.82 MiB -1 -1 0.16 18264 1 0.03 -1 -1 30432 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64328 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 23.8 MiB 0.20 1238 11759 3130 7729 900 62.8 MiB 0.14 0.00 5.12264 -157.121 -5.12264 5.12264 0.31 0.000705322 0.000655159 0.0413169 0.0383528 -1 -1 -1 -1 30 2872 20 6.64007e+06 389298 526063. 1820.29 0.68 0.124517 0.109659 22546 126617 -1 2332 20 1512 2420 128301 30561 4.07588 4.07588 -141.785 -4.07588 0 0 666494. 2306.21 0.03 0.07 0.12 -1 -1 0.03 0.0280318 0.024467 157 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 2.75 vpr 63.51 MiB -1 -1 0.16 18348 1 0.03 -1 -1 30076 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1118 16856 4639 9867 2350 63.5 MiB 0.19 0.00 4.29207 -131.028 -4.29207 4.29207 0.31 0.000745147 0.000691805 0.0590137 0.0547729 -1 -1 -1 -1 28 2771 25 6.64007e+06 527436 500653. 1732.36 0.64 0.152811 0.135193 21970 115934 -1 2232 22 1473 2458 171773 41912 3.24756 3.24756 -122.119 -3.24756 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0326766 0.0284409 151 62 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 310 266 1 176 89 17 17 289 -1 unnamed_device 23.7 MiB 0.18 1008 13949 3776 8315 1858 62.8 MiB 0.13 0.00 4.57978 -129.405 -4.57978 4.57978 0.32 0.00063151 0.000586933 0.0463927 0.0431298 -1 -1 -1 -1 26 2049 24 6.64007e+06 313950 477104. 1650.88 0.57 0.124264 0.109558 21682 110474 -1 1787 23 1119 1542 99717 24464 3.33023 3.33023 -121.141 -3.33023 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0277593 0.0240193 122 58 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.76 vpr 62.94 MiB -1 -1 0.23 18416 1 0.03 -1 -1 30536 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64452 31 32 326 261 1 177 105 17 17 289 -1 unnamed_device 23.9 MiB 0.07 1024 15666 4440 8933 2293 62.9 MiB 0.14 0.00 4.80044 -126.61 -4.80044 4.80044 0.32 0.000665995 0.000619056 0.0448001 0.0415297 -1 -1 -1 -1 26 2648 22 6.64007e+06 527436 477104. 1650.88 0.79 0.129778 0.11446 21682 110474 -1 2117 22 1383 2618 174651 40558 3.69763 3.69763 -123.591 -3.69763 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.028875 0.0250672 137 33 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 2.68 vpr 62.62 MiB -1 -1 0.20 18064 1 0.03 -1 -1 30432 -1 -1 27 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 29 32 262 224 1 168 88 17 17 289 -1 unnamed_device 23.5 MiB 0.20 847 8863 2227 5955 681 62.6 MiB 0.09 0.00 4.31301 -113.107 -4.31301 4.31301 0.32 0.000579564 0.000534241 0.0276143 0.025686 -1 -1 -1 -1 26 2115 21 6.64007e+06 339066 477104. 1650.88 0.58 0.0947231 0.0829346 21682 110474 -1 1780 21 1043 1394 90173 22397 3.32203 3.32203 -108.26 -3.32203 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0130991 0.0115568 116 31 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.97 vpr 62.67 MiB -1 -1 0.21 18200 1 0.03 -1 -1 30128 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 23.6 MiB 0.16 785 12683 4483 5881 2319 62.7 MiB 0.12 0.00 3.88358 -117.678 -3.88358 3.88358 0.32 0.00060376 0.000561743 0.0445389 0.0414623 -1 -1 -1 -1 26 2436 37 6.64007e+06 238602 477104. 1650.88 0.89 0.131629 0.116039 21682 110474 -1 1800 19 1200 1979 139267 34801 3.02517 3.02517 -113.385 -3.02517 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0227137 0.0197715 111 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.66 vpr 63.21 MiB -1 -1 0.26 18260 1 0.03 -1 -1 30432 -1 -1 40 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 24.2 MiB 0.12 994 11671 2882 8064 725 63.2 MiB 0.12 0.00 4.09378 -121.668 -4.09378 4.09378 0.32 0.000726427 0.000674778 0.0377137 0.034953 -1 -1 -1 -1 26 2376 23 6.64007e+06 502320 477104. 1650.88 0.55 0.125439 0.109976 21682 110474 -1 1958 22 1532 2565 145610 36094 3.06217 3.06217 -117.244 -3.06217 0 0 585099. 2024.56 0.05 0.08 0.10 -1 -1 0.05 0.0315397 0.0275332 141 64 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.73 vpr 62.66 MiB -1 -1 0.23 18040 1 0.03 -1 -1 30328 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 23.7 MiB 0.16 891 10033 2595 6630 808 62.7 MiB 0.10 0.00 4.05756 -122.47 -4.05756 4.05756 0.32 0.000576971 0.000536748 0.0317137 0.029489 -1 -1 -1 -1 26 2157 24 6.64007e+06 313950 477104. 1650.88 0.58 0.107628 0.0941218 21682 110474 -1 1791 17 1028 1508 93693 23016 3.14183 3.14183 -112.031 -3.14183 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0322542 0.0280416 115 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.61 vpr 62.85 MiB -1 -1 0.23 18464 1 0.03 -1 -1 30032 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 928 11851 2930 8165 756 62.8 MiB 0.12 0.00 3.6645 -107.626 -3.6645 3.6645 0.32 0.000692969 0.000644427 0.0379377 0.035255 -1 -1 -1 -1 32 2115 19 6.64007e+06 464646 554710. 1919.41 0.53 0.122566 0.10828 22834 132086 -1 1665 19 935 1662 86651 22815 2.90897 2.90897 -104.818 -2.90897 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0268623 0.0234903 131 57 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.93 vpr 63.59 MiB -1 -1 0.27 18448 1 0.03 -1 -1 30300 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65116 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 23.9 MiB 0.22 976 13095 3017 8881 1197 63.6 MiB 0.16 0.00 4.0221 -123.818 -4.0221 4.0221 0.32 0.000756213 0.000702112 0.0516439 0.047975 -1 -1 -1 -1 30 2145 22 6.64007e+06 452088 526063. 1820.29 0.63 0.143583 0.126812 22546 126617 -1 1877 17 1096 1732 88550 22588 3.14957 3.14957 -120.621 -3.14957 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0260509 0.0228149 145 91 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.56 vpr 62.58 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30280 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 23.5 MiB 0.10 960 12162 3264 7675 1223 62.6 MiB 0.11 0.00 3.3869 -105.779 -3.3869 3.3869 0.32 0.000614672 0.000570831 0.0427904 0.0397298 -1 -1 -1 -1 30 1894 19 6.64007e+06 251160 526063. 1820.29 0.50 0.116751 0.103215 22546 126617 -1 1629 18 769 1207 61799 15365 2.74977 2.74977 -103.907 -2.74977 0 0 666494. 2306.21 0.03 0.05 0.12 -1 -1 0.03 0.0225046 0.0195903 111 57 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.56 vpr 62.65 MiB -1 -1 0.23 18312 1 0.02 -1 -1 30292 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64152 32 32 290 244 1 177 90 17 17 289 -1 unnamed_device 23.5 MiB 0.19 925 8532 1785 6264 483 62.6 MiB 0.09 0.00 4.36984 -131.165 -4.36984 4.36984 0.31 0.00061324 0.000570288 0.0280339 0.026075 -1 -1 -1 -1 28 2708 24 6.64007e+06 326508 500653. 1732.36 0.64 0.104096 0.0910882 21970 115934 -1 1954 20 1359 2003 122646 30886 3.38923 3.38923 -122.625 -3.38923 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0135228 0.0119375 124 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.77 vpr 62.77 MiB -1 -1 0.23 18380 1 0.03 -1 -1 30208 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 23.8 MiB 0.22 1138 15617 4303 9234 2080 62.8 MiB 0.15 0.00 4.77964 -132.452 -4.77964 4.77964 0.34 0.000658273 0.000609711 0.0519544 0.0481265 -1 -1 -1 -1 32 2299 20 6.64007e+06 351624 554710. 1919.41 0.55 0.12943 0.114511 22834 132086 -1 2021 21 1045 1511 98148 22991 3.72382 3.72382 -126.429 -3.72382 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0269217 0.0234482 138 30 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.61 vpr 63.38 MiB -1 -1 0.25 18340 1 0.03 -1 -1 30112 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 23.9 MiB 0.14 1027 8089 1720 5536 833 63.4 MiB 0.08 0.00 4.38084 -119.914 -4.38084 4.38084 0.31 0.00065193 0.000606249 0.0259897 0.0241864 -1 -1 -1 -1 28 2224 20 6.64007e+06 452088 500653. 1732.36 0.49 0.101951 0.0892092 21970 115934 -1 1875 18 849 1396 79670 19823 3.16663 3.16663 -107.118 -3.16663 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0240837 0.0210767 129 55 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 3.04 vpr 63.07 MiB -1 -1 0.24 18336 1 0.03 -1 -1 30404 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 32 32 393 312 1 213 94 17 17 289 -1 unnamed_device 23.9 MiB 0.24 1101 8401 1796 6209 396 63.1 MiB 0.11 0.00 5.62095 -173.541 -5.62095 5.62095 0.31 0.00075665 0.000703659 0.0326673 0.0303426 -1 -1 -1 -1 28 2936 26 6.64007e+06 376740 500653. 1732.36 0.68 0.129571 0.11365 21970 115934 -1 2403 22 1682 2416 167600 40775 4.26009 4.26009 -154.42 -4.26009 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.032093 0.0279958 159 65 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.27 vpr 62.84 MiB -1 -1 0.15 17952 1 0.02 -1 -1 30144 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64348 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 23.3 MiB 0.06 878 12345 3107 8061 1177 62.8 MiB 0.10 0.00 3.46127 -102.488 -3.46127 3.46127 0.32 0.000540828 0.000503904 0.0378018 0.0352175 -1 -1 -1 -1 26 1836 20 6.64007e+06 263718 477104. 1650.88 0.46 0.0997432 0.0881038 21682 110474 -1 1648 19 828 1379 92032 22149 2.88697 2.88697 -102.774 -2.88697 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0204358 0.0177958 100 4 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 2.71 vpr 63.67 MiB -1 -1 0.30 18344 1 0.03 -1 -1 30260 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1132 12791 3491 8287 1013 63.7 MiB 0.15 0.00 4.42516 -144.482 -4.42516 4.42516 0.32 0.000777421 0.000722358 0.0449905 0.0417837 -1 -1 -1 -1 32 2175 23 6.64007e+06 464646 554710. 1919.41 0.56 0.138643 0.121972 22834 132086 -1 1928 20 1161 1813 106830 26306 3.76183 3.76183 -135.978 -3.76183 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0308308 0.0269198 146 90 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.52 vpr 62.92 MiB -1 -1 0.16 18316 1 0.03 -1 -1 30184 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 32 32 376 318 1 155 82 17 17 289 -1 unnamed_device 23.7 MiB 0.14 961 14678 5153 7870 1655 62.9 MiB 0.15 0.00 3.5251 -126.262 -3.5251 3.5251 0.32 0.000716805 0.000665017 0.061699 0.0573065 -1 -1 -1 -1 32 1789 17 6.64007e+06 226044 554710. 1919.41 0.53 0.141368 0.125423 22834 132086 -1 1636 19 1061 1511 101615 23343 2.65957 2.65957 -115.251 -2.65957 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0272319 0.0237407 116 96 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.68 vpr 63.50 MiB -1 -1 0.15 18392 1 0.03 -1 -1 30252 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1040 16059 4498 9094 2467 63.5 MiB 0.16 0.00 4.08563 -122.248 -4.08563 4.08563 0.32 0.000711584 0.000660221 0.0536532 0.0496695 -1 -1 -1 -1 32 2147 19 6.64007e+06 439530 554710. 1919.41 0.54 0.135243 0.119692 22834 132086 -1 1808 17 868 1394 77233 19535 2.86797 2.86797 -103.409 -2.86797 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0262874 0.0231714 134 60 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.76 vpr 63.12 MiB -1 -1 0.24 18356 1 0.05 -1 -1 30316 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 32 32 396 299 1 236 98 17 17 289 -1 unnamed_device 24.1 MiB 0.28 1248 18773 5780 9423 3570 63.1 MiB 0.20 0.00 6.37984 -185.995 -6.37984 6.37984 0.31 0.000780551 0.00072581 0.0680795 0.0632119 -1 -1 -1 -1 36 2761 19 6.64007e+06 426972 612192. 2118.31 1.34 0.222467 0.195692 23410 145293 -1 2234 16 1457 2063 137885 35563 4.99954 4.99954 -163.566 -4.99954 0 0 782063. 2706.10 0.03 0.07 0.12 -1 -1 0.03 0.0263971 0.0232455 177 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.60 vpr 62.75 MiB -1 -1 0.13 18124 1 0.03 -1 -1 30072 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 30 32 224 207 1 138 84 17 17 289 -1 unnamed_device 23.3 MiB 0.14 875 9783 2760 6082 941 62.7 MiB 0.08 0.00 3.31687 -101.206 -3.31687 3.31687 0.32 0.000501429 0.000467021 0.028543 0.0265577 -1 -1 -1 -1 26 1635 15 6.64007e+06 276276 477104. 1650.88 0.53 0.0837799 0.0736315 21682 110474 -1 1407 13 573 768 44589 11004 2.27497 2.27497 -90.5889 -2.27497 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0147089 0.0129252 92 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.45 vpr 62.72 MiB -1 -1 0.23 18136 1 0.03 -1 -1 30324 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 23.3 MiB 0.06 689 6731 1618 4756 357 62.7 MiB 0.08 0.00 4.09512 -115.35 -4.09512 4.09512 0.32 0.000599086 0.000557828 0.0252094 0.023468 -1 -1 -1 -1 30 1441 21 6.64007e+06 238602 526063. 1820.29 0.50 0.0996073 0.0873472 22546 126617 -1 1294 18 678 1174 70897 17025 2.86577 2.86577 -104.274 -2.86577 0 0 666494. 2306.21 0.03 0.05 0.11 -1 -1 0.03 0.0219962 0.0192113 95 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 2.63 vpr 62.67 MiB -1 -1 0.22 18180 1 0.03 -1 -1 30216 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64172 32 32 296 247 1 157 90 17 17 289 -1 unnamed_device 23.6 MiB 0.08 942 12552 3467 7974 1111 62.7 MiB 0.12 0.00 3.49427 -115.718 -3.49427 3.49427 0.32 0.000632151 0.000578248 0.041451 0.0384616 -1 -1 -1 -1 32 2080 20 6.64007e+06 326508 554710. 1919.41 0.62 0.114609 0.101229 22834 132086 -1 1868 22 1056 2009 127408 29897 2.69957 2.69957 -109.166 -2.69957 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0268929 0.0233414 119 34 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.61 vpr 62.79 MiB -1 -1 0.22 18028 1 0.03 -1 -1 30192 -1 -1 31 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 23.3 MiB 0.06 601 13543 4375 6504 2664 62.8 MiB 0.10 0.00 3.43127 -79.9 -3.43127 3.43127 0.32 0.000479119 0.000444893 0.0348322 0.0323139 -1 -1 -1 -1 32 1432 18 6.64007e+06 389298 554710. 1919.41 0.70 0.0896739 0.0790814 22834 132086 -1 1208 16 588 1034 67545 16020 2.66257 2.66257 -76.6177 -2.66257 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0163147 0.0142554 93 29 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 2.82 vpr 63.04 MiB -1 -1 0.25 18376 1 0.03 -1 -1 30224 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 24.0 MiB 0.16 989 17053 6066 7937 3050 63.0 MiB 0.18 0.00 4.31092 -130.251 -4.31092 4.31092 0.31 0.000731429 0.000679409 0.0669288 0.0621536 -1 -1 -1 -1 32 2483 22 6.64007e+06 301392 554710. 1919.41 0.58 0.153804 0.136564 22834 132086 -1 2014 19 1216 2250 133235 32112 3.97023 3.97023 -123.415 -3.97023 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0284099 0.0246596 137 72 -1 -1 -1 -1 - fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 2.87 vpr 62.98 MiB -1 -1 0.26 18340 1 0.03 -1 -1 30340 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64496 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 23.8 MiB 0.14 990 19124 5738 10202 3184 63.0 MiB 0.18 0.00 4.03784 -128.727 -4.03784 4.03784 0.32 0.000592896 0.000545424 0.0601703 0.0557054 -1 -1 -1 -1 30 2237 23 6.64007e+06 527436 526063. 1820.29 0.61 0.143789 0.127519 22546 126617 -1 1757 16 1113 1717 94449 22971 2.92383 2.92383 -113.587 -2.92383 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0263136 0.0230906 148 90 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 2.83 vpr 63.59 MiB -1 -1 0.25 18348 1 0.03 -1 -1 30064 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65120 32 32 354 285 1 202 99 17 17 289 -1 unnamed_device 24.2 MiB 0.17 1293 16743 4634 10568 1541 63.6 MiB 0.10 0.00 5.566 -161.813 -5.566 5.566 0.34 0.000331358 0.000304875 0.025734 0.0237042 -1 -1 -1 -1 32 2763 22 6.65987e+06 443730 554710. 1919.41 0.57 0.112732 0.0983887 22834 132086 -1 2449 19 1084 1699 139737 30053 4.09762 4.09762 -142.938 -4.09762 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0279861 0.0245724 153 50 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.75 vpr 63.43 MiB -1 -1 0.26 18392 1 0.03 -1 -1 30440 -1 -1 30 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 23.7 MiB 0.09 1161 17066 4950 10267 1849 63.4 MiB 0.18 0.00 4.92316 -142.534 -4.92316 4.92316 0.32 0.000711495 0.000661377 0.0607483 0.05633 -1 -1 -1 -1 32 2317 19 6.65987e+06 380340 554710. 1919.41 0.56 0.14224 0.126171 22834 132086 -1 2201 20 1285 1969 141789 31778 3.96643 3.96643 -135.327 -3.96643 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0286017 0.0250073 147 63 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.92 vpr 62.58 MiB -1 -1 0.23 18252 1 0.03 -1 -1 30424 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 299 247 1 188 95 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1005 7223 1515 5389 319 62.6 MiB 0.08 0.00 4.5072 -115.093 -4.5072 4.5072 0.32 0.000638459 0.000593954 0.023343 0.021723 -1 -1 -1 -1 26 2482 19 6.65987e+06 393018 477104. 1650.88 0.57 0.096452 0.084355 21682 110474 -1 2175 22 1225 1807 128173 38231 3.65077 3.65077 -115.591 -3.65077 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0283391 0.0248207 129 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.43 vpr 63.12 MiB -1 -1 0.17 18364 1 0.04 -1 -1 30272 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 23.3 MiB 0.04 1008 16445 5063 9076 2306 63.1 MiB 0.16 0.00 4.28955 -115.789 -4.28955 4.28955 0.31 0.000630792 0.000586242 0.0527628 0.0490015 -1 -1 -1 -1 32 2107 21 6.65987e+06 393018 554710. 1919.41 0.54 0.127475 0.112807 22834 132086 -1 1923 24 1162 2468 162514 37920 3.42191 3.42191 -111.417 -3.42191 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0300343 0.0260368 132 31 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.88 vpr 62.64 MiB -1 -1 0.23 18404 1 0.03 -1 -1 30412 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64144 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 23.6 MiB 0.06 926 17066 4722 10092 2252 62.6 MiB 0.18 0.00 4.32246 -124.084 -4.32246 4.32246 0.31 0.000682381 0.000633432 0.0584903 0.0542653 -1 -1 -1 -1 28 2659 35 6.65987e+06 354984 500653. 1732.36 0.85 0.156528 0.138194 21970 115934 -1 1952 22 1359 2592 155691 39529 3.65631 3.65631 -123.935 -3.65631 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0292856 0.0255564 134 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.51 vpr 62.75 MiB -1 -1 0.15 18452 1 0.03 -1 -1 30268 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 23.6 MiB 0.08 1006 10707 2558 7056 1093 62.7 MiB 0.11 0.00 3.2981 -110.874 -3.2981 3.2981 0.32 0.000715102 0.000664192 0.0344872 0.0320276 -1 -1 -1 -1 32 2059 17 6.65987e+06 494442 554710. 1919.41 0.52 0.114776 0.10094 22834 132086 -1 1766 16 1009 1653 81293 21469 2.93011 2.93011 -107.664 -2.93011 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0244838 0.0214969 145 58 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.33 vpr 62.35 MiB -1 -1 0.16 18212 1 0.03 -1 -1 30572 -1 -1 21 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63844 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 23.0 MiB 0.05 662 8508 2183 5532 793 62.3 MiB 0.08 0.00 3.64612 -97.2036 -3.64612 3.64612 0.32 0.000556352 0.000518731 0.02948 0.0274761 -1 -1 -1 -1 26 1488 20 6.65987e+06 266238 477104. 1650.88 0.46 0.0948889 0.0832974 21682 110474 -1 1285 19 839 1443 84061 21350 2.55211 2.55211 -89.8292 -2.55211 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0217986 0.0189775 97 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.55 vpr 62.41 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30072 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63904 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 23.4 MiB 0.05 879 17198 5694 8745 2759 62.4 MiB 0.14 0.00 3.28184 -95.5565 -3.28184 3.28184 0.36 0.000595736 0.000552841 0.0478346 0.044364 -1 -1 -1 -1 32 2096 17 6.65987e+06 443730 554710. 1919.41 0.52 0.110623 0.0981322 22834 132086 -1 1775 20 943 1802 114464 28225 2.55445 2.55445 -90.648 -2.55445 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0241442 0.0210605 123 4 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.40 vpr 62.57 MiB -1 -1 0.15 18384 1 0.03 -1 -1 30052 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 31 32 317 271 1 168 87 17 17 289 -1 unnamed_device 23.4 MiB 0.09 925 6807 1453 4944 410 62.6 MiB 0.08 0.00 3.3699 -114.313 -3.3699 3.3699 0.32 0.000493922 0.000454414 0.024486 0.0227415 -1 -1 -1 -1 28 2084 19 6.65987e+06 304272 500653. 1732.36 0.51 0.0981972 0.0857413 21970 115934 -1 1840 15 921 1353 95741 23607 2.83031 2.83031 -109.983 -2.83031 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0207326 0.0181803 117 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.56 vpr 62.51 MiB -1 -1 0.22 18156 1 0.03 -1 -1 30016 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 23.4 MiB 0.09 817 6383 1432 4490 461 62.5 MiB 0.08 0.00 3.76232 -120.722 -3.76232 3.76232 0.32 0.000636848 0.000593635 0.024309 0.0226498 -1 -1 -1 -1 26 2054 21 6.65987e+06 240882 477104. 1650.88 0.54 0.0984567 0.0861078 21682 110474 -1 1799 19 1068 1672 105244 26336 2.74751 2.74751 -112.355 -2.74751 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.024046 0.0210051 115 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.55 vpr 62.52 MiB -1 -1 0.20 18352 1 0.03 -1 -1 30424 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.4 MiB 0.12 855 11106 3144 6574 1388 62.5 MiB 0.10 0.00 3.77152 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1021 1396 110915 26979 3.05825 3.05825 -111.367 -3.05825 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.024645 0.0214555 111 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 2.79 vpr 62.86 MiB -1 -1 0.24 18380 1 0.08 -1 -1 30308 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1172 12063 3279 7731 1053 62.9 MiB 0.16 0.00 4.32078 -139.492 -4.32078 4.32078 0.33 0.000703373 0.000645846 0.0505267 0.04694 -1 -1 -1 -1 32 2466 23 6.65987e+06 367662 554710. 1919.41 0.56 0.135329 0.119646 22834 132086 -1 2158 23 1534 2364 144012 35379 3.01857 3.01857 -118.122 -3.01857 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0312134 0.027204 147 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.74 vpr 62.80 MiB -1 -1 0.24 18376 1 0.03 -1 -1 30196 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64308 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.10 971 17873 5392 9032 3449 62.8 MiB 0.19 0.00 4.50383 -130.941 -4.50383 4.50383 0.33 0.000717123 0.000666062 0.0669834 0.0620637 -1 -1 -1 -1 32 2088 18 6.65987e+06 431052 554710. 1919.41 0.57 0.148521 0.131949 22834 132086 -1 1825 20 1420 2352 139941 35041 3.57251 3.57251 -121.811 -3.57251 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0286098 0.0250144 139 61 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.47 vpr 62.38 MiB -1 -1 0.22 18052 1 0.03 -1 -1 30508 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63872 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 23.3 MiB 0.10 694 9600 2464 6430 706 62.4 MiB 0.08 0.00 2.92253 -85.631 -2.92253 2.92253 0.32 0.000543549 0.000506216 0.0305384 0.0284177 -1 -1 -1 -1 26 1711 20 6.65987e+06 291594 477104. 1650.88 0.48 0.0942953 0.0827929 21682 110474 -1 1601 22 1045 1797 119370 29179 2.51431 2.51431 -87.2887 -2.51431 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0234018 0.0202863 103 27 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 2.88 vpr 63.29 MiB -1 -1 0.27 18480 1 0.03 -1 -1 30296 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1152 16003 4822 9403 1778 63.3 MiB 0.16 0.00 4.09572 -126.446 -4.09572 4.09572 0.32 0.000716587 0.000665383 0.0595422 0.055318 -1 -1 -1 -1 32 2400 19 6.65987e+06 342306 554710. 1919.41 0.55 0.143212 0.12709 22834 132086 -1 2078 18 1135 2087 142666 37845 3.04917 3.04917 -116.306 -3.04917 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.0348576 0.0302735 138 58 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 2.65 vpr 62.60 MiB -1 -1 0.24 18544 1 0.03 -1 -1 30216 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1125 12926 3639 7674 1613 62.6 MiB 0.14 0.00 4.394 -141.354 -4.394 4.394 0.32 0.000683149 0.000635418 0.0456382 0.0424188 -1 -1 -1 -1 32 2214 18 6.65987e+06 354984 554710. 1919.41 0.52 0.124369 0.109993 22834 132086 -1 1990 21 1041 1502 96457 23182 2.90037 2.90037 -115.361 -2.90037 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0301769 0.026598 144 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.60 vpr 62.45 MiB -1 -1 0.23 18432 1 0.03 -1 -1 30280 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63944 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 23.4 MiB 0.10 916 7073 1434 5276 363 62.4 MiB 0.08 0.00 2.87664 -103.934 -2.87664 2.87664 0.32 0.000651927 0.000606239 0.0228193 0.0212013 -1 -1 -1 -1 30 1938 19 6.65987e+06 431052 526063. 1820.29 0.52 0.0977233 0.0852682 22546 126617 -1 1660 15 834 1444 83127 19598 2.00611 2.00611 -93.9149 -2.00611 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0208125 0.0182876 115 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.38 vpr 62.62 MiB -1 -1 0.21 18120 1 0.03 -1 -1 30240 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 23.1 MiB 0.05 693 9543 2321 6568 654 62.6 MiB 0.08 0.00 2.23087 -76.8517 -2.23087 2.23087 0.32 0.000503255 0.000468022 0.0298973 0.0278301 -1 -1 -1 -1 28 1420 15 6.65987e+06 215526 500653. 1732.36 0.50 0.0841738 0.0740953 21970 115934 -1 1307 22 674 1015 82701 19377 1.74665 1.74665 -75.5759 -1.74665 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0211611 0.0183274 85 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 2.98 vpr 62.58 MiB -1 -1 0.24 18392 1 0.03 -1 -1 30432 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64080 31 32 291 243 1 171 88 17 17 289 -1 unnamed_device 23.4 MiB 0.20 786 13738 3441 7180 3117 62.6 MiB 0.12 0.00 4.80308 -136.113 -4.80308 4.80308 0.31 0.000610132 0.000568245 0.0452547 0.0421109 -1 -1 -1 -1 32 2211 46 6.65987e+06 316950 554710. 1919.41 0.80 0.142447 0.124997 22834 132086 -1 1576 21 899 1285 88683 23465 3.84671 3.84671 -129.866 -3.84671 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0258407 0.0225526 127 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 3.39 vpr 63.26 MiB -1 -1 0.23 18456 1 0.03 -1 -1 30396 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 23.6 MiB 0.07 1092 18196 6057 9791 2348 63.3 MiB 0.17 0.00 4.25196 -133.154 -4.25196 4.25196 0.31 0.000696776 0.000647631 0.0565156 0.0524726 -1 -1 -1 -1 28 2596 21 6.65987e+06 469086 500653. 1732.36 0.78 0.140877 0.125047 21970 115934 -1 2180 20 1359 2318 167321 39385 3.69683 3.69683 -128.953 -3.69683 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0280309 0.0245652 140 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 3.33 vpr 62.74 MiB -1 -1 0.25 18336 1 0.03 -1 -1 30284 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 23.9 MiB 0.10 1229 17591 4978 10084 2529 62.7 MiB 0.19 0.00 4.43635 -136.819 -4.43635 4.43635 0.31 0.000723595 0.000672722 0.061937 0.0574339 -1 -1 -1 -1 32 2470 18 6.65987e+06 393018 554710. 1919.41 0.54 0.143942 0.127773 22834 132086 -1 2229 19 1285 1974 116123 28589 3.51771 3.51771 -123.874 -3.51771 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0285167 0.0249981 151 62 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.43 vpr 62.46 MiB -1 -1 0.14 18020 1 0.02 -1 -1 30524 -1 -1 20 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63960 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 23.1 MiB 0.07 431 10536 3837 3941 2758 62.5 MiB 0.07 0.00 2.35224 -64.6209 -2.35224 2.35224 0.32 0.000426133 0.000395077 0.0283186 0.0262801 -1 -1 -1 -1 28 1419 31 6.65987e+06 253560 500653. 1732.36 0.63 0.086015 0.075317 21970 115934 -1 1051 21 675 978 69553 19630 2.18965 2.18965 -68.0366 -2.18965 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0179993 0.0156342 81 30 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.46 vpr 63.06 MiB -1 -1 0.19 17944 1 0.03 -1 -1 30196 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 23.4 MiB 0.07 931 6623 1375 5033 215 63.1 MiB 0.07 0.00 4.36895 -119.052 -4.36895 4.36895 0.31 0.000615417 0.000572427 0.0229543 0.0213581 -1 -1 -1 -1 32 2111 24 6.65987e+06 316950 554710. 1919.41 0.56 0.0927906 0.081303 22834 132086 -1 1798 22 1076 2092 127185 31396 3.57251 3.57251 -117.08 -3.57251 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0267629 0.0233198 125 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.41 vpr 62.42 MiB -1 -1 0.16 17732 1 0.02 -1 -1 29972 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63916 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 23.0 MiB 0.04 493 11281 3421 5023 2837 62.4 MiB 0.09 0.00 2.48647 -71.166 -2.48647 2.48647 0.32 0.000878455 0.000815259 0.0342384 0.0317749 -1 -1 -1 -1 26 1361 33 6.65987e+06 215526 477104. 1650.88 0.65 0.0940299 0.082807 21682 110474 -1 922 14 531 645 59854 21541 1.95531 1.95531 -69.4327 -1.95531 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0133639 0.0117264 82 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.59 vpr 62.60 MiB -1 -1 0.16 18212 1 0.03 -1 -1 30044 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 23.5 MiB 0.09 898 10247 2366 7380 501 62.6 MiB 0.10 0.00 4.32789 -118.536 -4.32789 4.32789 0.32 0.000639255 0.000594623 0.0326551 0.0303542 -1 -1 -1 -1 26 2424 21 6.65987e+06 393018 477104. 1650.88 0.66 0.109099 0.0958696 21682 110474 -1 1959 20 1096 1916 134943 33891 3.50931 3.50931 -114.521 -3.50931 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0257508 0.0224904 126 24 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.57 vpr 62.66 MiB -1 -1 0.18 17776 1 0.03 -1 -1 30360 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 23.7 MiB 0.06 986 15527 4364 9095 2068 62.7 MiB 0.15 0.00 3.58941 -102.662 -3.58941 3.58941 0.32 0.00064423 0.000597693 0.0438764 0.0407061 -1 -1 -1 -1 32 2052 20 6.65987e+06 494442 554710. 1919.41 0.53 0.118788 0.104869 22834 132086 -1 1757 21 995 1984 121842 28850 2.78377 2.78377 -93.9889 -2.78377 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0253086 0.0224502 136 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 3.09 vpr 63.31 MiB -1 -1 0.15 18280 1 0.03 -1 -1 30412 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 338 277 1 179 99 17 17 289 -1 unnamed_device 23.7 MiB 0.08 1132 18339 5277 10722 2340 63.3 MiB 0.17 0.00 4.42603 -127.033 -4.42603 4.42603 0.32 0.000658681 0.000604043 0.0579563 0.0536309 -1 -1 -1 -1 26 2599 48 6.65987e+06 443730 477104. 1650.88 0.99 0.178629 0.157321 21682 110474 -1 2284 20 1343 2439 160763 40074 3.65545 3.65545 -127.111 -3.65545 0 0 585099. 2024.56 0.03 0.08 0.12 -1 -1 0.03 0.0273421 0.0238611 133 50 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.53 vpr 62.61 MiB -1 -1 0.21 17996 1 0.03 -1 -1 30100 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 23.5 MiB 0.06 916 11803 2959 7646 1198 62.6 MiB 0.11 0.00 3.02073 -105.462 -3.02073 3.02073 0.32 0.000596715 0.000554699 0.0399084 0.0371012 -1 -1 -1 -1 32 1826 19 6.65987e+06 266238 554710. 1919.41 0.51 0.109723 0.0968338 22834 132086 -1 1610 19 733 1113 70945 17055 2.33411 2.33411 -97.2001 -2.33411 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0233963 0.0204376 107 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.53 vpr 62.37 MiB -1 -1 0.23 18032 1 0.03 -1 -1 30212 -1 -1 28 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63864 30 32 262 227 1 135 90 17 17 289 -1 unnamed_device 23.1 MiB 0.07 668 7728 1645 5488 595 62.4 MiB 0.07 0.00 3.03787 -91.3278 -3.03787 3.03787 0.32 0.000583853 0.000535279 0.0239436 0.0222426 -1 -1 -1 -1 32 1487 23 6.65987e+06 354984 554710. 1919.41 0.52 0.092815 0.0810119 22834 132086 -1 1290 21 811 1389 92421 23927 2.68165 2.68165 -88.0109 -2.68165 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0236845 0.0205772 100 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.47 vpr 62.33 MiB -1 -1 0.22 18144 1 0.03 -1 -1 30148 -1 -1 27 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63824 28 32 260 223 1 140 87 17 17 289 -1 unnamed_device 23.3 MiB 0.06 623 10647 2615 7437 595 62.3 MiB 0.07 0.00 3.37407 -92.2897 -3.37407 3.37407 0.27 0.000565958 0.000526854 0.0191172 0.0175962 -1 -1 -1 -1 32 1558 18 6.65987e+06 342306 554710. 1919.41 0.52 0.0829422 0.0719943 22834 132086 -1 1314 21 834 1522 86562 22322 2.71857 2.71857 -89.5843 -2.71857 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0232677 0.0202501 104 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 2.70 vpr 62.44 MiB -1 -1 0.22 17840 1 0.03 -1 -1 30232 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 23.4 MiB 0.07 733 14035 5318 6638 2079 62.4 MiB 0.12 0.00 3.67009 -108.082 -3.67009 3.67009 0.32 0.000572926 0.000532536 0.0451769 0.0419649 -1 -1 -1 -1 32 1862 31 6.65987e+06 266238 554710. 1919.41 0.57 0.122063 0.107575 22834 132086 -1 1508 20 909 1486 90599 23830 2.64951 2.64951 -100.091 -2.64951 0 0 701300. 2426.64 0.04 0.06 0.10 -1 -1 0.04 0.0273808 0.0243873 116 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.57 vpr 62.43 MiB -1 -1 0.24 18192 1 0.03 -1 -1 30544 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63928 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 23.3 MiB 0.06 765 8199 1674 6237 288 62.4 MiB 0.08 0.00 3.38101 -98.7431 -3.38101 3.38101 0.32 0.000579578 0.000540067 0.0238147 0.0221697 -1 -1 -1 -1 26 1967 21 6.65987e+06 418374 477104. 1650.88 0.55 0.0977505 0.0853359 21682 110474 -1 1633 20 906 1519 84512 22222 2.82071 2.82071 -102.673 -2.82071 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0264682 0.0233523 111 30 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.70 vpr 62.84 MiB -1 -1 0.23 18384 1 0.03 -1 -1 30436 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 919 13961 3585 8809 1567 62.8 MiB 0.12 0.00 3.21564 -100.645 -3.21564 3.21564 0.32 0.000613384 0.000576201 0.0431614 0.0401718 -1 -1 -1 -1 32 1766 19 6.65987e+06 393018 554710. 1919.41 0.53 0.118447 0.104519 22834 132086 -1 1642 21 969 1515 100684 24375 2.21971 2.21971 -90.7495 -2.21971 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0246998 0.0214307 112 54 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 3.00 vpr 63.46 MiB -1 -1 0.24 18424 1 0.03 -1 -1 30404 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64988 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1278 14856 3856 9597 1403 63.5 MiB 0.14 0.00 4.04849 -118.625 -4.04849 4.04849 0.32 0.000738507 0.000685273 0.0468637 0.0434722 -1 -1 -1 -1 32 2520 23 6.65987e+06 532476 554710. 1919.41 0.66 0.128972 0.114192 22834 132086 -1 2343 20 1119 2110 130139 30403 3.27779 3.27779 -111.806 -3.27779 0 0 701300. 2426.64 0.04 0.07 0.11 -1 -1 0.04 0.0316226 0.0278407 158 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.84 vpr 63.34 MiB -1 -1 0.25 18416 1 0.03 -1 -1 30184 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 23.6 MiB 0.12 1103 11467 2726 7797 944 63.3 MiB 0.13 0.00 3.86972 -129.413 -3.86972 3.86972 0.32 0.000757179 0.000703981 0.0381411 0.0354271 -1 -1 -1 -1 28 2395 30 6.65987e+06 519798 500653. 1732.36 0.64 0.13815 0.121188 21970 115934 -1 2157 18 1571 2541 147293 36924 2.81751 2.81751 -115.433 -2.81751 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0280166 0.0245656 150 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.53 vpr 62.52 MiB -1 -1 0.22 18272 1 0.03 -1 -1 30232 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 23.4 MiB 0.09 916 12938 4123 6955 1860 62.5 MiB 0.12 0.00 4.11632 -122.804 -4.11632 4.11632 0.32 0.000592092 0.000550918 0.0429113 0.0399086 -1 -1 -1 -1 32 1802 19 6.65987e+06 291594 554710. 1919.41 0.50 0.112424 0.099407 22834 132086 -1 1621 21 899 1293 89858 21635 2.75411 2.75411 -103.631 -2.75411 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0251542 0.0219007 114 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.66 vpr 62.81 MiB -1 -1 0.25 18388 1 0.03 -1 -1 30428 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64316 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 962 14375 4628 7389 2358 62.8 MiB 0.15 0.00 4.01529 -116.343 -4.01529 4.01529 0.31 0.000715968 0.000664875 0.0525152 0.0487842 -1 -1 -1 -1 32 2097 20 6.65987e+06 367662 554710. 1919.41 0.55 0.136711 0.120978 22834 132086 -1 1740 19 953 1608 91219 23548 2.83077 2.83077 -103.661 -2.83077 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0283605 0.0250845 145 61 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.65 vpr 62.97 MiB -1 -1 0.26 18260 1 0.03 -1 -1 30408 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64480 31 32 377 302 1 234 99 17 17 289 -1 unnamed_device 24.1 MiB 0.07 1386 11043 2787 7293 963 63.0 MiB 0.13 0.00 5.91489 -170.972 -5.91489 5.91489 0.32 0.000736886 0.000685819 0.0385686 0.0358586 -1 -1 -1 -1 32 2873 20 6.65987e+06 456408 554710. 1919.41 0.57 0.124678 0.109747 22834 132086 -1 2486 19 1319 1924 126550 30073 4.39548 4.39548 -152.161 -4.39548 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0287112 0.0251583 178 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 3.22 vpr 63.42 MiB -1 -1 0.26 18348 1 0.03 -1 -1 30388 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 23.9 MiB 0.62 1238 16511 4791 9794 1926 63.4 MiB 0.18 0.00 4.89912 -151.132 -4.89912 4.89912 0.31 0.000738637 0.000685826 0.0591119 0.0549134 -1 -1 -1 -1 30 2429 21 6.65987e+06 405696 526063. 1820.29 0.55 0.146965 0.130343 22546 126617 -1 2186 20 1080 1696 96861 24644 4.08163 4.08163 -142.785 -4.08163 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0299256 0.026234 167 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.87 vpr 62.71 MiB -1 -1 0.19 18260 1 0.03 -1 -1 30456 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64216 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1124 12628 3322 8289 1017 62.7 MiB 0.13 0.00 4.44275 -130.243 -4.44275 4.44275 0.32 0.000707565 0.000658454 0.0406386 0.0377729 -1 -1 -1 -1 26 2643 23 6.65987e+06 469086 477104. 1650.88 0.59 0.126404 0.111239 21682 110474 -1 2328 21 1374 2327 147048 36129 3.16471 3.16471 -119.273 -3.16471 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0291973 0.0254676 140 55 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.83 vpr 62.69 MiB -1 -1 0.19 18456 1 0.03 -1 -1 30480 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 32 32 291 242 1 179 93 17 17 289 -1 unnamed_device 23.5 MiB 0.09 1082 11013 2473 7884 656 62.7 MiB 0.12 0.00 4.18181 -113.104 -4.18181 4.18181 0.32 0.000616948 0.000573587 0.03467 0.0322542 -1 -1 -1 -1 26 2738 25 6.65987e+06 367662 477104. 1650.88 0.84 0.114082 0.100194 21682 110474 -1 2132 19 1206 1813 126827 31200 3.29585 3.29585 -115.875 -3.29585 0 0 585099. 2024.56 0.03 0.06 0.11 -1 -1 0.03 0.024271 0.0212067 125 27 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.21 vpr 63.68 MiB -1 -1 0.27 18528 1 0.05 -1 -1 30400 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65204 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 24.1 MiB 0.22 1325 20094 5499 11953 2642 63.7 MiB 0.21 0.00 4.90518 -159.197 -4.90518 4.90518 0.32 0.000863265 0.00080313 0.0721534 0.0670195 -1 -1 -1 -1 26 3343 24 6.65987e+06 545154 477104. 1650.88 0.81 0.185067 0.163997 21682 110474 -1 2628 21 1646 2583 167664 39327 3.86217 3.86217 -144.748 -3.86217 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0362174 0.0316235 176 87 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.49 vpr 62.46 MiB -1 -1 0.23 18112 1 0.03 -1 -1 30172 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 23.4 MiB 0.09 737 9536 2387 5857 1292 62.5 MiB 0.09 0.00 3.48098 -96.6191 -3.48098 3.48098 0.32 0.000575726 0.000535589 0.0306291 0.0284653 -1 -1 -1 -1 30 1612 20 6.65987e+06 291594 526063. 1820.29 0.52 0.0958834 0.0841792 22546 126617 -1 1405 22 877 1491 83669 20744 2.47931 2.47931 -90.4761 -2.47931 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0247778 0.0215726 104 28 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 3.00 vpr 62.80 MiB -1 -1 0.26 18284 1 0.03 -1 -1 30132 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 23.8 MiB 0.08 1249 13195 3658 8262 1275 62.8 MiB 0.14 0.00 4.79192 -144.824 -4.79192 4.79192 0.34 0.000683955 0.000635929 0.0433617 0.0402853 -1 -1 -1 -1 24 3134 28 6.65987e+06 431052 448715. 1552.65 0.88 0.138378 0.12188 21394 104001 -1 2453 22 1503 2172 141924 34169 4.03451 4.03451 -135.006 -4.03451 0 0 554710. 1919.41 0.02 0.07 0.11 -1 -1 0.02 0.0296631 0.0258945 149 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.75 vpr 62.68 MiB -1 -1 0.24 18408 1 0.03 -1 -1 30420 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 349 284 1 183 102 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1155 13906 3407 9168 1331 62.7 MiB 0.13 0.00 3.8576 -113.911 -3.8576 3.8576 0.32 0.00069067 0.000641422 0.0431406 0.0400046 -1 -1 -1 -1 26 2941 21 6.65987e+06 481764 477104. 1650.88 0.66 0.128273 0.112978 21682 110474 -1 2377 20 1326 2410 166916 39546 3.17931 3.17931 -112.137 -3.17931 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0274615 0.0239703 137 53 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 2.85 vpr 62.54 MiB -1 -1 0.22 17876 1 0.03 -1 -1 30064 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 23.4 MiB 0.26 876 13147 4503 6169 2475 62.5 MiB 0.13 0.00 3.99841 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928 1310 71774 17944 3.20951 3.20951 -118.608 -3.20951 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0274664 0.0240917 142 55 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 2.77 vpr 63.24 MiB -1 -1 0.24 18424 1 0.03 -1 -1 30248 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1054 11189 2726 7692 771 63.2 MiB 0.11 0.00 3.80886 -119.733 -3.80886 3.80886 0.32 0.000712435 0.000662528 0.0358288 0.03325 -1 -1 -1 -1 26 2598 27 6.65987e+06 494442 477104. 1650.88 0.67 0.129506 0.113587 21682 110474 -1 2114 19 1188 2061 125664 30609 3.03311 3.03311 -114.46 -3.03311 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0230767 0.020264 139 55 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.81 vpr 62.77 MiB -1 -1 0.25 18280 1 0.03 -1 -1 30352 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1186 14744 3810 9393 1541 62.8 MiB 0.15 0.00 4.08875 -126.488 -4.08875 4.08875 0.32 0.000742546 0.000689999 0.0475827 0.0441969 -1 -1 -1 -1 26 2813 24 6.65987e+06 507120 477104. 1650.88 0.66 0.141553 0.124844 21682 110474 -1 2375 21 1537 2519 161666 39095 3.04491 3.04491 -117.668 -3.04491 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0308635 0.0269302 149 62 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 2.60 vpr 62.52 MiB -1 -1 0.22 17992 1 0.03 -1 -1 30320 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 23.4 MiB 0.09 1036 11932 2960 7977 995 62.5 MiB 0.11 0.00 3.95041 -117.901 -3.95041 3.95041 0.32 0.000629355 0.000583689 0.0352423 0.0326696 -1 -1 -1 -1 32 2001 21 6.65987e+06 456408 554710. 1919.41 0.54 0.112167 0.0985244 22834 132086 -1 1850 20 1003 1814 115866 27374 3.08765 3.08765 -108.602 -3.08765 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0250013 0.0219994 127 24 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.52 vpr 63.28 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30132 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64800 32 32 319 257 1 198 93 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1087 10383 2461 6851 1071 63.3 MiB 0.12 0.00 4.72526 -131.624 -4.72526 4.72526 0.32 0.000654215 0.000608358 0.0348778 0.0324333 -1 -1 -1 -1 32 2215 22 6.65987e+06 367662 554710. 1919.41 0.53 0.113498 0.0997649 22834 132086 -1 1949 19 1182 1681 99807 25080 3.68471 3.68471 -122.409 -3.68471 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.020965 0.0184721 138 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 2.78 vpr 62.82 MiB -1 -1 0.26 18340 1 0.03 -1 -1 30256 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64324 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 24.0 MiB 0.10 1150 17733 5210 9615 2908 62.8 MiB 0.19 0.00 4.69532 -137.386 -4.69532 4.69532 0.32 0.000727343 0.000676045 0.0638798 0.0592796 -1 -1 -1 -1 32 2496 21 6.65987e+06 380340 554710. 1919.41 0.58 0.150245 0.133328 22834 132086 -1 2250 20 1300 2007 143463 32554 3.78891 3.78891 -127.851 -3.78891 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.029378 0.0257092 152 62 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.75 vpr 63.07 MiB -1 -1 0.26 18400 1 0.03 -1 -1 30340 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 24.0 MiB 0.10 1167 14147 4331 7961 1855 63.1 MiB 0.16 0.00 3.97858 -128.122 -3.97858 3.97858 0.31 0.000748689 0.000687482 0.05575 0.05163 -1 -1 -1 -1 32 2577 21 6.65987e+06 316950 554710. 1919.41 0.57 0.143557 0.126963 22834 132086 -1 2276 19 1356 2418 159825 36180 3.35705 3.35705 -121.283 -3.35705 0 0 701300. 2426.64 0.03 0.07 0.10 -1 -1 0.03 0.0287086 0.0251227 141 77 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.28 vpr 62.30 MiB -1 -1 0.14 17988 1 0.03 -1 -1 30336 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63796 32 32 251 219 1 140 94 17 17 289 -1 unnamed_device 23.0 MiB 0.06 913 15643 4415 9418 1810 62.3 MiB 0.12 0.00 3.35098 -100.668 -3.35098 3.35098 0.32 0.000559149 0.0005199 0.0431236 0.0401111 -1 -1 -1 -1 32 1760 21 6.65987e+06 380340 554710. 1919.41 0.50 0.109026 0.0963947 22834 132086 -1 1658 17 804 1267 80945 19430 2.45125 2.45125 -90.1739 -2.45125 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0198175 0.0173259 101 23 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.75 vpr 62.68 MiB -1 -1 0.25 18244 1 0.03 -1 -1 30092 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64188 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 23.7 MiB 0.08 996 17023 5758 8918 2347 62.7 MiB 0.17 0.00 3.96847 -134.773 -3.96847 3.96847 0.32 0.000673933 0.000625952 0.0586522 0.0544351 -1 -1 -1 -1 28 2722 23 6.65987e+06 342306 500653. 1732.36 0.70 0.142328 0.126048 21970 115934 -1 2070 19 1306 1855 127035 31021 3.38897 3.38897 -128.298 -3.38897 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0258283 0.0225418 133 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.77 vpr 62.88 MiB -1 -1 0.24 18520 1 0.03 -1 -1 30352 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64392 32 32 387 293 1 234 99 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1433 14463 4059 9245 1159 62.9 MiB 0.16 0.00 5.18108 -151.87 -5.18108 5.18108 0.32 0.000764555 0.000710159 0.0512314 0.0475868 -1 -1 -1 -1 32 3076 23 6.65987e+06 443730 554710. 1919.41 0.58 0.144273 0.127505 22834 132086 -1 2769 21 1634 2613 161131 38979 4.04551 4.04551 -142.419 -4.04551 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.032354 0.0283413 174 31 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.52 vpr 62.75 MiB -1 -1 0.24 18392 1 0.03 -1 -1 30380 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64256 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 23.7 MiB 0.08 1064 9622 2158 6803 661 62.8 MiB 0.10 0.00 4.25077 -131.82 -4.25077 4.25077 0.32 0.000689443 0.000641753 0.030528 0.0283813 -1 -1 -1 -1 26 2445 19 6.65987e+06 481764 477104. 1650.88 0.54 0.111197 0.0976738 21682 110474 -1 2100 20 1180 2009 122888 30587 2.98991 2.98991 -119.17 -2.98991 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0282445 0.0247036 141 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.97 vpr 62.47 MiB -1 -1 0.22 18020 1 0.02 -1 -1 30388 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 23.4 MiB 0.06 873 7655 1741 5556 358 62.5 MiB 0.08 0.00 3.46801 -106.861 -3.46801 3.46801 0.29 0.000592529 0.000551119 0.0230086 0.0213939 -1 -1 -1 -1 26 1985 22 6.65987e+06 418374 477104. 1650.88 1.09 0.101588 0.0889863 21682 110474 -1 1566 19 872 1628 93100 23067 2.89891 2.89891 -101.232 -2.89891 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0227936 0.0198726 111 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.74 vpr 63.60 MiB -1 -1 0.27 18632 1 0.03 -1 -1 30348 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 32 32 431 332 1 235 97 17 17 289 -1 unnamed_device 24.1 MiB 0.16 1373 17857 5541 9729 2587 63.6 MiB 0.21 0.00 6.00689 -175.284 -6.00689 6.00689 0.32 0.000829838 0.000770463 0.0699701 0.065028 -1 -1 -1 -1 26 3848 37 6.65987e+06 418374 477104. 1650.88 1.45 0.197086 0.174141 21682 110474 -1 3002 21 1997 2930 217962 52054 5.28897 5.28897 -171.079 -5.28897 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0353896 0.0309506 177 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.72 vpr 62.68 MiB -1 -1 0.23 18428 1 0.03 -1 -1 30384 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 23.7 MiB 0.11 1017 19142 6169 10401 2572 62.7 MiB 0.18 0.00 4.49092 -134.922 -4.49092 4.49092 0.32 0.000688964 0.000639258 0.058669 0.0542224 -1 -1 -1 -1 32 2057 20 6.65987e+06 481764 554710. 1919.41 0.55 0.138961 0.123175 22834 132086 -1 1855 18 1006 1647 91104 22583 3.46031 3.46031 -122.488 -3.46031 0 0 701300. 2426.64 0.05 0.07 0.08 -1 -1 0.05 0.027125 0.0239429 136 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.42 vpr 62.38 MiB -1 -1 0.20 17912 1 0.05 -1 -1 30352 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63880 32 32 231 199 1 140 93 17 17 289 -1 unnamed_device 23.1 MiB 0.06 757 14793 4373 7837 2583 62.4 MiB 0.13 0.00 3.29469 -92.947 -3.29469 3.29469 0.32 0.000538264 0.000501659 0.0461663 0.0429533 -1 -1 -1 -1 30 1671 23 6.65987e+06 367662 526063. 1820.29 0.50 0.111364 0.098657 22546 126617 -1 1389 20 700 1220 66685 16954 2.41305 2.41305 -85.9205 -2.41305 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.021408 0.0186665 103 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.75 vpr 63.34 MiB -1 -1 0.23 18472 1 0.04 -1 -1 30316 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1150 19624 5000 12637 1987 63.3 MiB 0.19 0.00 5.1064 -126.138 -5.1064 5.1064 0.32 0.000704936 0.000655185 0.059793 0.055533 -1 -1 -1 -1 28 2459 23 6.65987e+06 507120 500653. 1732.36 0.57 0.147213 0.130679 21970 115934 -1 2168 22 1287 2791 166610 39959 3.96919 3.96919 -118.971 -3.96919 0 0 612192. 2118.31 0.03 0.08 0.12 -1 -1 0.03 0.0303989 0.0264907 147 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.52 vpr 63.21 MiB -1 -1 0.22 17964 1 0.03 -1 -1 30112 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 23.4 MiB 0.06 872 15831 4931 8734 2166 63.2 MiB 0.14 0.00 3.5083 -107.383 -3.5083 3.5083 0.32 0.000561581 0.00052297 0.050766 0.0471046 -1 -1 -1 -1 32 1802 23 6.65987e+06 291594 554710. 1919.41 0.51 0.118787 0.105164 22834 132086 -1 1692 22 1001 1708 115538 28004 2.61951 2.61951 -100.831 -2.61951 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0241798 0.0210207 107 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.78 vpr 62.54 MiB -1 -1 0.24 18124 1 0.03 -1 -1 30336 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 23.4 MiB 0.11 879 14252 3836 8169 2247 62.5 MiB 0.12 0.00 4.01069 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.62 vpr 63.35 MiB -1 -1 0.23 18572 1 0.04 -1 -1 30276 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 23.7 MiB 0.11 1075 15173 3870 9435 1868 63.3 MiB 0.15 0.00 4.58626 -136.867 -4.58626 4.58626 0.32 0.000705923 0.000655882 0.0503308 0.046744 -1 -1 -1 -1 32 2211 20 6.65987e+06 431052 554710. 1919.41 0.55 0.132979 0.11753 22834 132086 -1 1968 17 847 1531 91027 22240 3.35191 3.35191 -122.638 -3.35191 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0253636 0.0223258 136 51 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.47 vpr 63.35 MiB -1 -1 0.25 18168 1 0.04 -1 -1 30140 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 23.7 MiB 0.10 901 6701 1571 4713 417 63.4 MiB 0.08 0.00 4.569 -127.264 -4.569 4.569 0.32 0.000598546 0.000556821 0.0231644 0.0215639 -1 -1 -1 -1 26 2033 20 6.65987e+06 278916 477104. 1650.88 0.48 0.0923268 0.0807068 21682 110474 -1 1721 21 882 1189 70078 18621 3.26691 3.26691 -112.036 -3.26691 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0140382 0.0124423 107 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.64 vpr 62.48 MiB -1 -1 0.20 18340 1 0.03 -1 -1 30296 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63980 31 32 319 272 1 169 88 17 17 289 -1 unnamed_device 23.6 MiB 0.09 802 16273 4920 8724 2629 62.5 MiB 0.15 0.00 3.75784 -117.415 -3.75784 3.75784 0.32 0.000637111 0.000591828 0.0557216 0.0517767 -1 -1 -1 -1 32 1992 22 6.65987e+06 316950 554710. 1919.41 0.53 0.132251 0.11715 22834 132086 -1 1605 18 979 1470 76824 20417 2.97351 2.97351 -106.635 -2.97351 0 0 701300. 2426.64 0.03 0.06 0.08 -1 -1 0.03 0.0249297 0.0217531 117 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.60 vpr 63.22 MiB -1 -1 0.24 18344 1 0.03 -1 -1 30272 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 23.6 MiB 0.10 889 16973 4879 9089 3005 63.2 MiB 0.15 0.00 3.33409 -93.1785 -3.33409 3.33409 0.32 0.000660544 0.000613972 0.0523942 0.048655 -1 -1 -1 -1 28 2254 24 6.65987e+06 456408 500653. 1732.36 0.56 0.134436 0.118707 21970 115934 -1 1914 19 1124 2027 125753 32278 2.56839 2.56839 -91.7219 -2.56839 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0254975 0.0222664 128 57 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.70 vpr 63.16 MiB -1 -1 0.14 18152 1 0.03 -1 -1 30384 -1 -1 39 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 23.5 MiB 0.07 817 17427 4857 10073 2497 63.2 MiB 0.14 0.00 3.74992 -95.3542 -3.74992 3.74992 0.32 0.00058808 0.000547246 0.0470504 0.0437117 -1 -1 -1 -1 26 2053 33 6.65987e+06 494442 477104. 1650.88 0.77 0.128498 0.112971 21682 110474 -1 1725 24 1318 2503 168666 42857 3.34885 3.34885 -97.8664 -3.34885 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0326863 0.0282768 122 27 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 2.74 vpr 62.59 MiB -1 -1 0.24 18356 1 0.02 -1 -1 30172 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64096 30 32 317 269 1 152 84 17 17 289 -1 unnamed_device 23.4 MiB 0.11 893 13809 4432 6991 2386 62.6 MiB 0.13 0.00 3.80155 -112.624 -3.80155 3.80155 0.32 0.000639961 0.000594619 0.0503891 0.0468642 -1 -1 -1 -1 32 1901 19 6.65987e+06 278916 554710. 1919.41 0.54 0.128986 0.114538 22834 132086 -1 1725 17 1082 1865 121154 29026 2.80571 2.80571 -108.587 -2.80571 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.022801 0.0199622 115 63 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 3.24 vpr 62.56 MiB -1 -1 0.26 18272 1 0.03 -1 -1 30104 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64064 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 23.6 MiB 0.10 976 8532 1791 6388 353 62.6 MiB 0.05 0.00 3.80404 -125.955 -3.80404 3.80404 0.33 0.000297142 0.000274077 0.0143566 0.0132378 -1 -1 -1 -1 32 2168 21 6.65987e+06 329628 554710. 1919.41 0.48 0.0866732 0.0751553 22834 132086 -1 1736 19 958 1411 91359 22142 3.07251 3.07251 -120.561 -3.07251 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0252589 0.022049 127 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 3.11 vpr 62.89 MiB -1 -1 0.22 17928 1 0.03 -1 -1 30320 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64396 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 23.7 MiB 0.06 1091 10540 2548 6838 1154 62.9 MiB 0.11 0.00 4.26866 -122.654 -4.26866 4.26866 0.29 0.000634407 0.000589944 0.031125 0.0289309 -1 -1 -1 -1 28 2517 21 6.65987e+06 469086 500653. 1732.36 0.62 0.10807 0.0950411 21970 115934 -1 2180 23 1405 2540 172113 40649 3.40705 3.40705 -114.855 -3.40705 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0283837 0.0247165 134 4 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 3.53 vpr 62.97 MiB -1 -1 0.23 18332 1 0.07 -1 -1 30300 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64484 32 32 350 275 1 209 94 17 17 289 -1 unnamed_device 24.2 MiB 0.12 1246 10957 2695 7343 919 63.0 MiB 0.14 0.00 4.99112 -158.75 -4.99112 4.99112 0.32 0.000702283 0.000653206 0.0389072 0.0361679 -1 -1 -1 -1 32 2654 21 6.65987e+06 380340 554710. 1919.41 0.57 0.124134 0.10938 22834 132086 -1 2391 19 1400 2095 119781 30173 3.76891 3.76891 -138.842 -3.76891 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0273598 0.0240069 151 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 3.66 vpr 62.86 MiB -1 -1 0.15 18304 1 0.03 -1 -1 30268 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1079 12086 3142 8350 594 62.9 MiB 0.13 0.00 4.38712 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1341 2401 169392 39910 3.57111 3.57111 -125.638 -3.57111 0 0 666494. 2306.21 0.03 0.08 0.10 -1 -1 0.03 0.0298434 0.0261358 147 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 2.59 vpr 63.26 MiB -1 -1 0.23 18128 1 0.03 -1 -1 30188 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 23.7 MiB 0.11 704 8363 1755 6223 385 63.3 MiB 0.09 0.00 3.74343 -108.246 -3.74343 3.74343 0.31 0.000579714 0.000539557 0.0290906 0.0270951 -1 -1 -1 -1 32 1650 19 6.65987e+06 266238 554710. 1919.41 0.52 0.0923774 0.0813121 22834 132086 -1 1345 19 836 1444 76832 20508 2.45585 2.45585 -90.9532 -2.45585 0 0 701300. 2426.64 0.04 0.06 0.13 -1 -1 0.04 0.0289157 0.0251587 109 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 2.81 vpr 62.67 MiB -1 -1 0.26 18508 1 0.03 -1 -1 30404 -1 -1 27 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 23.6 MiB 0.13 1064 12365 3291 6967 2107 62.7 MiB 0.13 0.00 4.67895 -138.029 -4.67895 4.67895 0.31 0.000725007 0.000674131 0.0480908 0.0447495 -1 -1 -1 -1 28 2343 23 6.65987e+06 342306 500653. 1732.36 0.62 0.136452 0.120796 21970 115934 -1 1980 22 1486 2399 145841 36399 3.50937 3.50937 -127.985 -3.50937 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0317457 0.027759 147 63 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 2.65 vpr 63.50 MiB -1 -1 0.23 18316 1 0.03 -1 -1 30344 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1145 13939 3986 8000 1953 63.5 MiB 0.15 0.00 5.09463 -149.184 -5.09463 5.09463 0.29 0.000696151 0.000641679 0.0475882 0.0442297 -1 -1 -1 -1 30 2536 25 6.65987e+06 380340 526063. 1820.29 0.55 0.133121 0.117514 22546 126617 -1 2135 21 1195 1902 103374 25035 3.52651 3.52651 -127.669 -3.52651 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0288516 0.0252219 145 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 3.16 vpr 62.95 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30256 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64464 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 23.9 MiB 0.18 1110 13148 3427 8545 1176 63.0 MiB 0.13 0.00 5.06667 -144.178 -5.06667 5.06667 0.32 0.000692547 0.00064179 0.0430229 0.0399631 -1 -1 -1 -1 34 2291 34 6.65987e+06 443730 585099. 2024.56 0.95 0.190217 0.165664 23122 138558 -1 2068 20 1254 2153 127671 32495 3.93437 3.93437 -132.32 -3.93437 0 0 742403. 2568.87 0.03 0.07 0.11 -1 -1 0.03 0.0277139 0.0242435 151 47 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 3.18 vpr 63.29 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30392 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64808 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 23.6 MiB 0.48 1101 17500 4849 10565 2086 63.3 MiB 0.18 0.00 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2146 22 1289 2236 137417 32546 3.53711 3.53711 -130.489 -3.53711 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0309713 0.0270326 141 57 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 2.70 vpr 62.69 MiB -1 -1 0.27 18380 1 0.03 -1 -1 30324 -1 -1 39 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 29 32 378 310 1 177 100 17 17 289 -1 unnamed_device 23.6 MiB 0.10 929 10076 2437 6533 1106 62.7 MiB 0.11 0.00 4.01172 -111.251 -4.01172 4.01172 0.31 0.000712445 0.000662323 0.0336174 0.0312492 -1 -1 -1 -1 30 1926 20 6.65987e+06 494442 526063. 1820.29 0.52 0.116714 0.10236 22546 126617 -1 1620 16 857 1390 66199 17216 2.81965 2.81965 -101.818 -2.81965 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0244566 0.0214747 137 85 -1 -1 -1 -1 - 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 23.7 MiB 0.14 1014 14691 4446 7278 2967 62.8 MiB 0.14 0.00 4.39152 -132.525 -4.39152 4.39152 0.32 0.000727586 0.00067249 0.0500078 0.046285 -1 -1 -1 -1 32 2332 30 6.65987e+06 443730 554710. 1919.41 0.69 0.146265 0.128769 22834 132086 -1 1872 23 1191 1892 138049 33056 3.67671 3.67671 -122.883 -3.67671 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0328304 0.0289108 135 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 2.92 vpr 62.82 MiB -1 -1 0.27 18284 1 0.04 -1 -1 30228 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64324 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 23.9 MiB 0.24 1125 9989 2357 6341 1291 62.8 MiB 0.12 0.00 4.65798 -147.06 -4.65798 4.65798 0.32 0.000769917 0.000714125 0.0415759 0.0386249 -1 -1 -1 -1 32 2196 23 6.65987e+06 316950 554710. 1919.41 0.57 0.134357 0.118291 22834 132086 -1 1980 20 1409 2358 138276 34236 3.43517 3.43517 -131.636 -3.43517 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0306802 0.0268235 155 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.71 vpr 62.58 MiB -1 -1 0.12 18084 1 0.03 -1 -1 30480 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 23.5 MiB 0.10 914 12761 3862 6624 2275 62.6 MiB 0.11 0.00 3.89235 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919 1562 92559 23224 2.59051 2.59051 -97.3557 -2.59051 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0214232 0.0186898 110 4 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 2.94 vpr 62.69 MiB -1 -1 0.25 18408 1 0.05 -1 -1 30416 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64196 32 32 348 274 1 211 95 17 17 289 -1 unnamed_device 23.9 MiB 0.08 1109 10031 2519 6610 902 62.7 MiB 0.11 0.00 4.87104 -146.551 -4.87104 4.87104 0.29 0.000698444 0.00064888 0.0352578 0.0327197 -1 -1 -1 -1 28 2980 22 6.65987e+06 393018 500653. 1732.36 0.73 0.127295 0.112131 21970 115934 -1 2316 20 1466 1984 138805 34064 3.84923 3.84923 -141.858 -3.84923 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0282332 0.0247056 151 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 3.22 vpr 63.35 MiB -1 -1 0.23 18512 1 0.03 -1 -1 30308 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 23.9 MiB 0.18 1270 17021 5150 9608 2263 63.3 MiB 0.16 0.00 5.06049 -146.913 -5.06049 5.06049 0.32 0.000326262 0.000301131 0.0486664 0.0450209 -1 -1 -1 -1 26 2988 41 6.65987e+06 469086 477104. 1650.88 0.74 0.159099 0.140044 21682 110474 -1 2434 19 1509 2359 161130 37560 4.17677 4.17677 -139.903 -4.17677 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0275016 0.0240929 157 56 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 3.13 vpr 63.51 MiB -1 -1 0.16 18148 1 0.03 -1 -1 30108 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 24.0 MiB 0.09 1310 18070 5249 10836 1985 63.5 MiB 0.18 0.00 5.25009 -142.167 -5.25009 5.25009 0.33 0.000717635 0.000666772 0.0540006 0.0501412 -1 -1 -1 -1 30 2632 26 6.65987e+06 545154 526063. 1820.29 0.63 0.147014 0.130114 22546 126617 -1 2281 21 1345 2651 147508 35512 4.20957 4.20957 -132.922 -4.20957 0 0 666494. 2306.21 0.03 0.08 0.10 -1 -1 0.03 0.0303179 0.0265724 162 3 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.58 vpr 62.57 MiB -1 -1 0.24 18272 1 0.03 -1 -1 30508 -1 -1 35 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 30 32 316 264 1 162 97 17 17 289 -1 unnamed_device 23.4 MiB 0.09 934 10531 2543 7170 818 62.6 MiB 0.10 0.00 3.47521 -102.746 -3.47521 3.47521 0.31 0.000642962 0.000598177 0.0327091 0.0304142 -1 -1 -1 -1 26 2134 21 6.65987e+06 443730 477104. 1650.88 0.52 0.108155 0.0949242 21682 110474 -1 1889 19 1136 2017 124547 30766 2.91491 2.91491 -103.283 -2.91491 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.025205 0.0220948 124 52 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.44 vpr 62.41 MiB -1 -1 0.23 18092 1 0.03 -1 -1 30328 -1 -1 25 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63912 27 32 255 219 1 132 84 17 17 289 -1 unnamed_device 23.1 MiB 0.06 785 11430 3670 6156 1604 62.4 MiB 0.09 0.00 3.4653 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3629 243596 58549 3.77365 3.77365 -132.773 -3.77365 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0224005 0.0199829 176 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 3.09 vpr 62.79 MiB -1 -1 0.27 18324 1 0.03 -1 -1 30420 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 23.7 MiB 0.44 973 17175 6014 8082 3079 62.8 MiB 0.17 0.00 5.18035 -150.464 -5.18035 5.18035 0.32 0.00070932 0.00065886 0.0637335 0.0591838 -1 -1 -1 -1 30 2403 24 6.65987e+06 342306 526063. 1820.29 0.64 0.151557 0.134524 22546 126617 -1 1847 18 1178 1814 98515 25469 4.49437 4.49437 -139.894 -4.49437 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0266933 0.0234329 151 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 2.91 vpr 63.18 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30424 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 32 32 331 280 1 175 87 17 17 289 -1 unnamed_device 23.4 MiB 0.40 1020 11991 3560 6392 2039 63.2 MiB 0.15 0.00 4.25169 -136.039 -4.25169 4.25169 0.32 0.000864673 0.000803635 0.0533516 0.0496012 -1 -1 -1 -1 32 2019 16 6.65987e+06 291594 554710. 1919.41 0.53 0.127172 0.112926 22834 132086 -1 1798 18 782 1100 71252 17324 3.25897 3.25897 -123.619 -3.25897 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0245208 0.0215202 131 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.95 vpr 62.66 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30324 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 23.7 MiB 0.09 1117 12164 3459 7844 861 62.7 MiB 0.12 0.00 4.92174 -128.183 -4.92174 4.92174 0.31 0.00066283 0.000615913 0.0374864 0.0347847 -1 -1 -1 -1 26 2516 22 6.65987e+06 456408 477104. 1650.88 0.54 0.119342 0.104951 21682 110474 -1 2181 18 1043 1793 114022 27754 3.30585 3.30585 -116.367 -3.30585 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0251273 0.0220676 133 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.01 vpr 63.32 MiB -1 -1 0.20 18484 1 0.04 -1 -1 30424 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 31 32 373 294 1 196 101 17 17 289 -1 unnamed_device 23.8 MiB 0.09 1058 9971 2285 7156 530 63.3 MiB 0.12 0.00 4.48315 -116.972 -4.48315 4.48315 0.31 0.000741538 0.000688786 0.0339044 0.0314509 -1 -1 -1 -1 26 2520 24 6.65987e+06 481764 477104. 1650.88 0.66 0.124359 0.108952 21682 110474 -1 2232 24 1463 2428 150433 38162 3.79065 3.79065 -118.424 -3.79065 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0340227 0.0296695 151 50 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 3.16 vpr 63.19 MiB -1 -1 0.26 18300 1 0.04 -1 -1 30248 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 23.7 MiB 0.05 942 16973 5403 7874 3696 63.2 MiB 0.16 0.00 3.53041 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.34 vpr 62.36 MiB -1 -1 0.11 18144 1 0.03 -1 -1 30284 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63860 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 23.4 MiB 0.05 783 14184 4630 8014 1540 62.4 MiB 0.12 0.00 4.07075 -112.394 -4.07075 4.07075 0.32 0.000576339 0.000535755 0.0495872 0.0461609 -1 -1 -1 -1 32 1449 20 6.65987e+06 240882 554710. 1919.41 0.49 0.116661 0.103432 22834 132086 -1 1346 20 716 1069 69828 16923 2.81477 2.81477 -95.7948 -2.81477 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0229956 0.0200317 93 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.80 vpr 62.46 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30332 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63964 32 32 310 266 1 175 89 17 17 289 -1 unnamed_device 23.3 MiB 0.08 1007 13949 3952 8258 1739 62.5 MiB 0.12 0.00 4.24766 -126.418 -4.24766 4.24766 0.32 0.000481589 0.000443594 0.0432888 0.0401085 -1 -1 -1 -1 32 1793 18 6.65987e+06 316950 554710. 1919.41 0.52 0.11537 0.101824 22834 132086 -1 1672 14 756 1020 62601 15811 3.06877 3.06877 -112.763 -3.06877 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0198489 0.017478 122 58 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 3.17 vpr 63.25 MiB -1 -1 0.14 18252 1 0.03 -1 -1 30304 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 31 32 326 261 1 177 105 17 17 289 -1 unnamed_device 23.7 MiB 0.08 926 12208 3208 7327 1673 63.2 MiB 0.12 0.00 4.58372 -118.506 -4.58372 4.58372 0.32 0.000667937 0.000620673 0.0353145 0.0327327 -1 -1 -1 -1 26 2937 44 6.65987e+06 532476 477104. 1650.88 1.20 0.138033 0.120779 21682 110474 -1 2199 22 1468 2656 200310 48980 3.35491 3.35491 -114.974 -3.35491 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0289022 0.0251966 137 33 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 2.43 vpr 62.43 MiB -1 -1 0.25 18116 1 0.03 -1 -1 30216 -1 -1 27 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63924 29 32 262 224 1 168 88 17 17 289 -1 unnamed_device 23.3 MiB 0.07 896 15103 4215 9146 1742 62.4 MiB 0.13 0.00 4.17458 -112.81 -4.17458 4.17458 0.32 0.000565255 0.00052655 0.0458425 0.0426624 -1 -1 -1 -1 26 2150 22 6.65987e+06 342306 477104. 1650.88 0.56 0.115868 0.102438 21682 110474 -1 1818 17 869 1145 81501 19964 3.11697 3.11697 -104.705 -3.11697 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0201079 0.0175635 116 31 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.77 vpr 62.43 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30128 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63924 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 23.4 MiB 0.11 798 11243 4185 5675 1383 62.4 MiB 0.11 0.00 3.71146 -112.967 -3.71146 3.71146 0.31 0.000604244 0.000562734 0.0399845 0.0372544 -1 -1 -1 -1 28 2050 48 6.65987e+06 240882 500653. 1732.36 0.81 0.135941 0.119249 21970 115934 -1 1636 23 1302 2195 133693 34634 2.95805 2.95805 -111.835 -2.95805 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0268582 0.0233235 111 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.34 vpr 63.27 MiB -1 -1 0.25 18380 1 0.03 -1 -1 30168 -1 -1 40 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64788 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 23.6 MiB 0.11 943 8779 1827 6626 326 63.3 MiB 0.06 0.00 4.01172 -118.652 -4.01172 4.01172 0.29 0.000338799 0.000305712 0.0146354 0.0133262 -1 -1 -1 -1 30 1947 20 6.65987e+06 507120 526063. 1820.29 0.43 0.0819746 0.0711925 22546 126617 -1 1728 19 1148 1951 98929 24137 3.06517 3.06517 -108.924 -3.06517 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0279109 0.024443 141 64 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.43 vpr 62.47 MiB -1 -1 0.23 18124 1 0.03 -1 -1 30340 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 23.3 MiB 0.07 930 10228 2669 6535 1024 62.5 MiB 0.10 0.00 3.8161 -117.091 -3.8161 3.8161 0.32 0.000591034 0.000543686 0.0323042 0.0300571 -1 -1 -1 -1 32 1836 21 6.65987e+06 316950 554710. 1919.41 0.49 0.100283 0.0881994 22834 132086 -1 1638 17 808 1220 76603 18529 2.93457 2.93457 -107.171 -2.93457 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0213134 0.0187932 115 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.63 vpr 62.65 MiB -1 -1 0.23 18412 1 0.03 -1 -1 30008 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64156 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1077 18196 4934 11069 2193 62.7 MiB 0.16 0.00 3.54324 -109.963 -3.54324 3.54324 0.32 0.000538895 0.000495325 0.0514617 0.0475687 -1 -1 -1 -1 32 2182 22 6.65987e+06 469086 554710. 1919.41 0.56 0.134851 0.118993 22834 132086 -1 1852 21 982 1748 107334 25210 2.76771 2.76771 -104.243 -2.76771 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0290857 0.025433 131 57 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.95 vpr 63.34 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30416 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 23.6 MiB 0.43 972 13779 3191 9639 949 63.3 MiB 0.14 0.00 3.95996 -122.236 -3.95996 3.95996 0.32 0.000747206 0.000693562 0.0474696 0.044021 -1 -1 -1 -1 28 2311 22 6.65987e+06 456408 500653. 1732.36 0.56 0.141858 0.125311 21970 115934 -1 2026 23 1471 2170 141402 36233 3.06423 3.06423 -122.172 -3.06423 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0405449 0.0360275 145 91 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.71 vpr 62.60 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30252 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 23.5 MiB 0.11 931 10149 2799 6536 814 62.6 MiB 0.10 0.00 3.26564 -102.038 -3.26564 3.26564 0.31 0.000623729 0.00058006 0.0365945 0.0339944 -1 -1 -1 -1 32 1792 21 6.65987e+06 253560 554710. 1919.41 0.51 0.112588 0.0993539 22834 132086 -1 1603 17 732 1143 64605 16743 2.62971 2.62971 -101.046 -2.62971 0 0 701300. 2426.64 0.03 0.05 0.12 -1 -1 0.03 0.0221088 0.0193181 111 57 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.48 vpr 62.46 MiB -1 -1 0.22 18348 1 0.02 -1 -1 30420 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 32 32 290 244 1 177 90 17 17 289 -1 unnamed_device 23.3 MiB 0.08 852 6924 1415 4674 835 62.5 MiB 0.07 0.00 4.16652 -123.951 -4.16652 4.16652 0.32 0.000611583 0.00056898 0.0232007 0.0215469 -1 -1 -1 -1 30 2146 23 6.65987e+06 329628 526063. 1820.29 0.60 0.0975585 0.0850677 22546 126617 -1 1676 20 1036 1560 84668 22482 3.03051 3.03051 -112.2 -3.03051 0 0 666494. 2306.21 0.03 0.06 0.09 -1 -1 0.03 0.0244389 0.0213206 124 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.98 vpr 62.71 MiB -1 -1 0.24 18244 1 0.03 -1 -1 30184 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64212 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1091 8579 1943 6143 493 62.7 MiB 0.09 0.00 4.54938 -126.236 -4.54938 4.54938 0.36 0.000668476 0.000621141 0.0296112 0.0275522 -1 -1 -1 -1 26 2549 22 6.65987e+06 354984 477104. 1650.88 0.56 0.111992 0.0982032 21682 110474 -1 2178 22 1223 1795 118510 28680 3.58451 3.58451 -120.815 -3.58451 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0288121 0.0251317 138 30 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.56 vpr 62.76 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30248 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 23.5 MiB 0.11 1042 6535 1424 4454 657 62.8 MiB 0.07 0.00 4.20872 -115.808 -4.20872 4.20872 0.31 0.000653114 0.000605773 0.021466 0.0199964 -1 -1 -1 -1 30 1967 16 6.65987e+06 456408 526063. 1820.29 0.50 0.0934942 0.0815178 22546 126617 -1 1808 19 714 1267 68406 16641 2.71491 2.71491 -97.6025 -2.71491 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0257432 0.0225677 129 55 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.87 vpr 63.45 MiB -1 -1 0.23 18276 1 0.03 -1 -1 30480 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 393 312 1 213 94 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1136 17773 5438 9801 2534 63.4 MiB 0.19 0.00 5.18709 -160.79 -5.18709 5.18709 0.32 0.000751899 0.000698984 0.0661306 0.0614276 -1 -1 -1 -1 32 2400 22 6.65987e+06 380340 554710. 1919.41 0.61 0.167742 0.148709 22834 132086 -1 2213 22 1428 1987 125431 30881 3.96237 3.96237 -142.636 -3.96237 0 0 701300. 2426.64 0.04 0.10 0.11 -1 -1 0.04 0.0400136 0.0353947 159 65 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.46 vpr 62.59 MiB -1 -1 0.23 17952 1 0.03 -1 -1 30084 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 23.3 MiB 0.07 877 10515 2651 6990 874 62.6 MiB 0.10 0.00 3.28101 -98.7222 -3.28101 3.28101 0.34 0.000534255 0.000496925 0.0325397 0.0303173 -1 -1 -1 -1 26 1877 19 6.65987e+06 266238 477104. 1650.88 0.50 0.0939242 0.0826791 21682 110474 -1 1635 20 877 1459 98976 23834 2.63371 2.63371 -97.6023 -2.63371 0 0 585099. 2024.56 0.03 0.05 0.10 -1 -1 0.03 0.0218513 0.0190899 100 4 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 2.65 vpr 62.72 MiB -1 -1 0.24 18344 1 0.03 -1 -1 30248 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 23.8 MiB 0.09 1128 13026 3490 8482 1054 62.7 MiB 0.15 0.00 4.18264 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1236 1858 105693 26868 2.87077 2.87077 -119.337 -2.87077 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0294216 0.0256661 117 96 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.69 vpr 63.28 MiB -1 -1 0.15 18304 1 0.03 -1 -1 30320 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 23.6 MiB 0.09 987 16059 4384 8773 2902 63.3 MiB 0.15 0.00 3.84552 -115.819 -3.84552 3.84552 0.33 0.000588113 0.000522126 0.0529609 0.0491666 -1 -1 -1 -1 32 2087 20 6.65987e+06 443730 554710. 1919.41 0.55 0.136764 0.121046 22834 132086 -1 1731 18 919 1426 73695 19390 2.62331 2.62331 -97.5338 -2.62331 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0269736 0.023685 134 60 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.78 vpr 63.52 MiB -1 -1 0.15 18496 1 0.03 -1 -1 30488 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65040 32 32 396 299 1 236 98 17 17 289 -1 unnamed_device 23.9 MiB 0.16 1229 18773 5439 9701 3633 63.5 MiB 0.18 0.00 6.00689 -176.035 -6.00689 6.00689 0.34 0.000348158 0.00032017 0.0661284 0.0613889 -1 -1 -1 -1 36 2968 23 6.65987e+06 431052 612192. 2118.31 1.43 0.227075 0.199663 23410 145293 -1 2288 21 1763 2474 164498 42055 4.85537 4.85537 -153.246 -4.85537 0 0 782063. 2706.10 0.04 0.07 0.11 -1 -1 0.04 0.0231769 0.0207501 177 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.52 vpr 62.36 MiB -1 -1 0.16 18020 1 0.03 -1 -1 30244 -1 -1 22 30 0 0 success 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/home/elgamma8/research/release/vtr-verilog-to-routing 64024 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 23.4 MiB 0.13 726 6206 1469 4338 399 62.5 MiB 0.07 0.00 3.83543 -111.011 -3.83543 3.83543 0.37 0.000605709 0.000564518 0.0236706 0.0220708 -1 -1 -1 -1 26 1610 20 6.65987e+06 240882 477104. 1650.88 0.53 0.0949303 0.0830353 21682 110474 -1 1409 23 974 1626 100425 25629 2.75671 2.75671 -100.414 -2.75671 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0268728 0.0233444 95 34 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 2.42 vpr 62.57 MiB -1 -1 0.22 18080 1 0.03 -1 -1 30224 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 32 32 296 247 1 157 90 17 17 289 -1 unnamed_device 23.4 MiB 0.04 895 10743 2661 7468 614 62.6 MiB 0.11 0.00 3.40601 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18 667 1079 58646 15667 2.41205 2.41205 -71.6142 -2.41205 0 0 701300. 2426.64 0.04 0.04 0.11 -1 -1 0.04 0.0162517 0.0144498 93 29 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 2.76 vpr 62.72 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30276 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1096 16858 5655 8603 2600 62.7 MiB 0.19 0.00 4.02912 -126.938 -4.02912 4.02912 0.34 0.000728074 0.000676381 0.0716169 0.0664747 -1 -1 -1 -1 32 2481 19 6.65987e+06 304272 554710. 1919.41 0.57 0.157198 0.140094 22834 132086 -1 2115 20 1266 2266 138051 33347 3.36005 3.36005 -118.607 -3.36005 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.029559 0.0258418 137 72 -1 -1 -1 -1 - fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 2.87 vpr 62.85 MiB -1 -1 0.26 18272 1 0.04 -1 -1 30256 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 23.9 MiB 0.11 987 19124 5334 10330 3460 62.8 MiB 0.19 0.00 3.91658 -124.769 -3.91658 3.91658 0.32 0.000756341 0.000701237 0.0615584 0.0570229 -1 -1 -1 -1 32 2113 20 6.65987e+06 532476 554710. 1919.41 0.60 0.154524 0.136607 22834 132086 -1 1837 19 1226 1995 117145 29196 2.79751 2.79751 -109.839 -2.79751 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0292829 0.0256389 148 90 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_001.v common 11.61 vpr 64.05 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30228 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65588 32 32 354 285 1 191 88 17 17 289 -1 unnamed_device 24.5 MiB 1.20 903 15298 5538 7704 2056 64.1 MiB 0.13 0.00 5.15265 -149.781 -5.15265 5.15265 0.35 0.000701928 0.000652099 0.0579569 0.0538537 -1 -1 -1 -1 40 2487 22 6.95648e+06 347416 706193. 2443.58 8.24 0.381864 0.330066 26914 176310 -1 2069 20 1681 2521 193589 46028 4.70236 4.70236 -152.72 -4.70236 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0283789 0.0248703 85 50 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 6.23 vpr 63.55 MiB -1 -1 0.25 18552 1 0.03 -1 -1 30328 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 30 32 363 293 1 187 80 17 17 289 -1 unnamed_device 24.5 MiB 1.72 822 9540 3866 5233 441 63.5 MiB 0.10 0.00 4.21658 -127.866 -4.21658 4.21658 0.35 0.000715716 0.00066455 0.0428595 0.0398403 -1 -1 -1 -1 40 2503 31 6.95648e+06 260562 706193. 2443.58 1.90 0.201124 0.174937 26914 176310 -1 2075 22 1955 2787 228608 53991 4.26192 4.26192 -142.656 -4.26192 0 0 926341. 3205.33 0.04 0.09 0.15 -1 -1 0.04 0.0315981 0.0277047 79 63 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_003.v common 9.49 vpr 63.92 MiB -1 -1 0.12 18316 1 0.03 -1 -1 30420 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65456 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 24.2 MiB 0.81 857 12542 4298 6587 1657 63.9 MiB 0.11 0.00 3.78245 -113.708 -3.78245 3.78245 0.33 0.000620895 0.000576964 0.0461334 0.0428945 -1 -1 -1 -1 38 2559 29 6.95648e+06 260562 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fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 4.13 vpr 63.91 MiB -1 -1 0.24 18416 1 0.03 -1 -1 30432 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 32 32 336 268 1 167 85 17 17 289 -1 unnamed_device 24.2 MiB 0.30 799 12919 4266 6230 2423 63.9 MiB 0.14 0.00 3.92082 -123.639 -3.92082 3.92082 0.33 0.000689843 0.000640891 0.0579711 0.053704 -1 -1 -1 -1 40 2419 26 6.95648e+06 303989 706193. 2443.58 1.73 0.195597 0.171434 26914 176310 -1 1974 23 1432 2633 220972 49560 4.01942 4.01942 -133.562 -4.01942 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0306242 0.026712 76 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 4.55 vpr 63.35 MiB -1 -1 0.25 18324 1 0.03 -1 -1 30296 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 366 295 1 182 89 17 17 289 -1 unnamed_device 24.5 MiB 0.40 1004 13949 3867 8912 1170 63.3 MiB 0.13 0.00 3.1127 -117.428 -3.1127 3.1127 0.33 0.000898578 0.000838343 0.0537559 0.0498994 -1 -1 -1 -1 34 2773 40 6.95648e+06 361892 618332. 2139.56 2.07 0.217268 0.189412 25762 151098 -1 2255 18 1337 2010 155622 35041 3.22637 3.22637 -127.705 -3.22637 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0266073 0.0233266 81 58 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 6.63 vpr 63.88 MiB -1 -1 0.23 18196 1 0.03 -1 -1 30616 -1 -1 14 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65412 27 32 259 221 1 124 73 17 17 289 -1 unnamed_device 24.3 MiB 2.35 446 7825 3025 3749 1051 63.9 MiB 0.07 0.00 3.35433 -89.8611 -3.35433 3.35433 0.33 0.000554723 0.000515636 0.0305449 0.028442 -1 -1 -1 -1 36 1857 48 6.95648e+06 202660 648988. 2245.63 2.33 0.16939 0.146242 26050 158493 -1 1247 22 1095 1726 134988 35763 3.23827 3.23827 -101.735 -3.23827 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0242115 0.0210147 52 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_008.v common 4.37 vpr 63.25 MiB -1 -1 0.23 17708 1 0.03 -1 -1 30068 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64772 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 24.3 MiB 0.18 837 12552 4747 6820 985 63.3 MiB 0.09 0.00 2.9854 -94.3513 -2.9854 2.9854 0.32 0.000606549 0.000563903 0.0345449 0.0320468 -1 -1 -1 -1 38 2223 36 6.95648e+06 390843 678818. 2348.85 2.18 0.173002 0.150128 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65216 30 32 303 262 1 135 75 17 17 289 -1 unnamed_device 24.3 MiB 0.89 501 7975 2162 4189 1624 63.7 MiB 0.07 0.00 3.32418 -98.7921 -3.32418 3.32418 0.33 0.000626842 0.000583299 0.033361 0.031035 -1 -1 -1 -1 42 1361 50 6.95648e+06 188184 744469. 2576.02 1.38 0.180268 0.155588 27202 183097 -1 1018 21 1057 1561 93379 26253 2.99162 2.99162 -104.394 -2.99162 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0261378 0.022782 54 63 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 4.57 vpr 63.32 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30204 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 276 237 1 161 77 17 17 289 -1 unnamed_device 24.3 MiB 1.18 717 11487 4799 6349 339 63.3 MiB 0.05 0.00 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0.22 18040 1 0.03 -1 -1 30504 -1 -1 18 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 29 32 248 215 1 132 79 17 17 289 -1 unnamed_device 24.2 MiB 0.43 542 11064 3839 5079 2146 63.6 MiB 0.10 0.00 2.93656 -85.9547 -2.93656 2.93656 0.33 0.000543369 0.000504995 0.0449064 0.0417544 -1 -1 -1 -1 38 1739 25 6.95648e+06 260562 678818. 2348.85 1.60 0.163141 0.142452 26626 170182 -1 1156 20 930 1476 86830 22287 2.86467 2.86467 -90.2809 -2.86467 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0219637 0.0191139 55 27 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 9.89 vpr 64.18 MiB -1 -1 0.25 18480 1 0.03 -1 -1 30292 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65720 32 32 370 297 1 178 81 17 17 289 -1 unnamed_device 24.6 MiB 0.55 1116 11456 4128 5618 1710 64.2 MiB 0.11 0.00 3.1427 -121.494 -3.1427 3.1427 0.33 0.000717433 0.000666227 0.0497802 0.0462674 -1 -1 -1 -1 38 2695 25 6.95648e+06 246087 678818. 2348.85 7.13 0.321783 0.277821 26626 170182 -1 2317 20 1511 2426 195538 40467 3.13107 3.13107 -128.649 -3.13107 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.029045 0.0253744 77 58 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 5.39 vpr 64.05 MiB -1 -1 0.23 18332 1 0.03 -1 -1 30084 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65592 32 32 338 269 1 190 81 17 17 289 -1 unnamed_device 24.2 MiB 1.49 1015 13031 4708 5937 2386 64.1 MiB 0.12 0.00 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0.03 -1 -1 30452 -1 -1 14 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 31 32 291 243 1 166 77 17 17 289 -1 unnamed_device 24.2 MiB 1.53 1007 11976 3355 7225 1396 63.3 MiB 0.10 0.00 4.40603 -142.381 -4.40603 4.40603 0.33 0.000608611 0.000566303 0.0470857 0.043836 -1 -1 -1 -1 34 2380 24 6.95648e+06 202660 618332. 2139.56 1.06 0.169043 0.147544 25762 151098 -1 2003 20 1207 1675 119064 27189 3.98032 3.98032 -146.92 -3.98032 0 0 787024. 2723.27 0.03 0.06 0.12 -1 -1 0.03 0.0247293 0.0215758 68 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 4.70 vpr 63.46 MiB -1 -1 0.26 18472 1 0.03 -1 -1 30432 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 342 271 1 172 91 17 17 289 -1 unnamed_device 24.5 MiB 0.23 777 13351 4773 6428 2150 63.5 MiB 0.11 0.00 3.69009 -122.34 -3.69009 3.69009 0.33 0.000688999 0.000639455 0.047794 0.0443687 -1 -1 -1 -1 40 2451 40 6.95648e+06 390843 706193. 2443.58 2.28 0.208193 0.181318 26914 176310 -1 1989 23 1600 2424 223141 68263 3.89406 3.89406 -135.843 -3.89406 0 0 926341. 3205.33 0.04 0.12 0.15 -1 -1 0.04 0.0334966 0.029147 79 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_022.v common 4.94 vpr 63.62 MiB -1 -1 0.25 18268 1 0.03 -1 -1 30280 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65148 32 32 372 300 1 200 80 17 17 289 -1 unnamed_device 24.6 MiB 1.09 929 10228 2968 5474 1786 63.6 MiB 0.10 0.00 4.43786 -126.086 -4.43786 4.43786 0.33 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0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0199648 0.017303 43 30 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_024.v common 8.18 vpr 63.14 MiB -1 -1 0.15 17796 1 0.03 -1 -1 30324 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 285 227 1 159 81 17 17 289 -1 unnamed_device 24.1 MiB 0.45 719 9531 2772 5216 1543 63.1 MiB 0.09 0.00 4.35141 -115.734 -4.35141 4.35141 0.34 0.00062324 0.000578477 0.03622 0.0336562 -1 -1 -1 -1 42 2136 41 6.95648e+06 246087 744469. 2576.02 5.73 0.308778 0.265688 27202 183097 -1 1474 23 1312 2219 179928 44050 4.15656 4.15656 -120.492 -4.15656 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0278794 0.0242966 66 3 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 2.64 vpr 63.15 MiB -1 -1 0.11 17612 1 0.03 -1 -1 29988 -1 -1 10 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 23.8 MiB 0.10 456 10459 4198 5595 666 63.1 MiB 0.07 0.00 2.13126 -69.3153 -2.13126 2.13126 0.31 0.00042468 0.000394535 0.0302253 0.0280834 -1 -1 -1 -1 36 1204 23 6.95648e+06 144757 648988. 2245.63 0.91 0.11542 0.100517 26050 158493 -1 915 21 632 749 65534 16835 2.05118 2.05118 -75.2428 -2.05118 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0176879 0.0153969 43 3 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_026.v common 3.91 vpr 63.34 MiB -1 -1 0.23 18124 1 0.03 -1 -1 30152 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 32 32 300 245 1 159 83 17 17 289 -1 unnamed_device 24.2 MiB 0.46 705 11063 3344 5374 2345 63.3 MiB 0.09 0.00 4.42909 -119.059 -4.42909 4.42909 0.34 0.000632235 0.000588523 0.0414738 0.0385764 -1 -1 -1 -1 42 1926 27 6.95648e+06 275038 744469. 2576.02 1.35 0.176041 0.153466 27202 183097 -1 1512 20 1112 1881 126839 32424 3.69636 3.69636 -116.75 -3.69636 0 0 949917. 3286.91 0.04 0.07 0.15 -1 -1 0.04 0.0258126 0.0225697 67 24 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_027.v common 3.35 vpr 63.43 MiB -1 -1 0.22 17828 1 0.03 -1 -1 30316 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 24.2 MiB 0.18 1111 14983 4654 8769 1560 63.4 MiB 0.12 0.00 2.9965 -108.481 -2.9965 2.9965 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66024 32 32 431 332 1 227 82 17 17 289 -1 unnamed_device 24.8 MiB 1.43 1077 13076 5478 7292 306 64.5 MiB 0.14 0.00 5.30235 -160.109 -5.30235 5.30235 0.33 0.000839666 0.00078032 0.064804 0.0602835 -1 -1 -1 -1 46 3075 31 6.95648e+06 260562 828058. 2865.25 1.52 0.244686 0.214294 28066 200906 -1 2516 23 2235 3373 300793 65578 4.88325 4.88325 -159.437 -4.88325 0 0 1.01997e+06 3529.29 0.04 0.11 0.16 -1 -1 0.04 0.0373225 0.0326244 95 65 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 4.87 vpr 63.32 MiB -1 -1 0.15 18504 1 0.03 -1 -1 30536 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 32 32 336 268 1 169 89 17 17 289 -1 unnamed_device 24.4 MiB 0.98 769 14543 4279 7650 2614 63.3 MiB 0.13 0.00 4.37605 -128.976 -4.37605 4.37605 0.33 0.00068609 0.000637719 0.0529336 0.0491554 -1 -1 -1 -1 36 2640 45 6.95648e+06 361892 648988. 2245.63 1.95 0.220043 0.191748 26050 158493 -1 1899 19 1368 2103 168161 39340 4.52236 4.52236 -147.419 -4.52236 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0268261 0.0234869 75 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_062.v common 3.23 vpr 63.44 MiB -1 -1 0.21 17720 1 0.03 -1 -1 30332 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64964 32 32 231 199 1 136 81 17 17 289 -1 unnamed_device 23.9 MiB 0.17 862 10581 3669 5472 1440 63.4 MiB 0.08 0.00 2.966 -103.091 -2.966 2.966 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 30 32 278 235 1 141 87 17 17 289 -1 unnamed_device 24.3 MiB 0.57 775 12567 4624 6004 1939 63.8 MiB 0.10 0.00 3.23198 -106.153 -3.23198 3.23198 0.35 0.000590718 0.000549282 0.0409618 0.0381017 -1 -1 -1 -1 36 1945 49 6.95648e+06 361892 648988. 2245.63 1.58 0.19865 0.172724 26050 158493 -1 1651 24 1219 1928 159003 35682 3.51472 3.51472 -122.539 -3.51472 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0269613 0.0233639 64 34 -1 -1 -1 -1 - fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 5.16 vpr 63.41 MiB -1 -1 0.25 18380 1 0.03 -1 -1 30368 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65552 32 32 372 300 1 225 84 17 17 289 -1 unnamed_device 24.3 MiB 0.42 1287 11430 3124 6919 1387 64.0 MiB 0.12 0.00 4.28762 -137.056 -4.28762 4.28762 0.34 0.000725791 0.000674218 0.0481271 0.0447389 -1 -1 -1 -1 36 3638 47 6.99608e+06 294314 648988. 2245.63 2.54 0.226737 0.197277 26050 158493 -1 2909 22 2179 3181 270199 57321 4.16172 4.16172 -146.771 -4.16172 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0312828 0.0273115 97 62 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_023.v common 2.73 vpr 63.21 MiB -1 -1 0.19 18128 1 0.03 -1 -1 30684 -1 -1 16 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 26 32 190 182 1 123 74 17 17 289 -1 unnamed_device 23.7 MiB 0.24 509 11389 4872 5794 723 63.2 MiB 0.08 0.00 2.5304 -71.4335 -2.5304 2.5304 0.36 0.000430528 0.000399577 0.0334196 0.0310487 -1 -1 -1 -1 32 1512 40 6.99608e+06 235451 586450. 2029.24 0.67 0.0982233 0.0860666 25474 144626 -1 1053 19 675 830 60421 15815 2.32772 2.32772 -75.6559 -2.32772 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0167778 0.014619 51 30 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_024.v common 10.38 vpr 63.32 MiB -1 -1 0.13 17988 1 0.03 -1 -1 30404 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 285 227 1 160 81 17 17 289 -1 unnamed_device 24.0 MiB 0.46 809 9531 2907 4788 1836 63.3 MiB 0.08 0.00 4.23145 -111.771 -4.23145 4.23145 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 24.0 MiB 0.17 933 10087 2140 7381 566 63.1 MiB 0.09 0.00 2.84195 -100.69 -2.84195 2.84195 0.34 0.000645685 0.000599204 0.0341485 0.0317824 -1 -1 -1 -1 36 2408 26 6.99608e+06 397324 648988. 2245.63 1.49 0.170187 0.148059 26050 158493 -1 1956 25 1433 2511 172697 38909 3.03892 3.03892 -108.258 -3.03892 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0302885 0.0263341 77 3 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_028.v common 4.63 vpr 63.82 MiB -1 -1 0.23 18284 1 0.03 -1 -1 30280 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 338 277 1 204 83 17 17 289 -1 unnamed_device 24.3 MiB 0.52 923 8003 1947 5085 971 63.8 MiB 0.09 0.00 4.17173 -123.211 -4.17173 4.17173 0.36 0.000695055 0.000646514 0.0331131 0.0308269 -1 -1 -1 -1 46 2562 33 6.99608e+06 279598 828058. 2865.25 1.99 0.189042 0.16453 28066 200906 -1 1783 21 1525 2326 154442 36408 3.79266 3.79266 -121.653 -3.79266 0 0 1.01997e+06 3529.29 0.04 0.07 0.16 -1 -1 0.04 0.0283844 0.0247975 86 50 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_029.v common 3.94 vpr 63.37 MiB -1 -1 0.23 18112 1 0.03 -1 -1 30208 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64892 32 32 284 241 1 168 78 17 17 289 -1 unnamed_device 24.1 MiB 0.70 870 11200 3386 5818 1996 63.4 MiB 0.10 0.00 3.16334 -110.479 -3.16334 3.16334 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65552 31 32 365 296 1 229 84 17 17 289 -1 unnamed_device 24.4 MiB 0.41 1271 10515 2847 5946 1722 64.0 MiB 0.11 0.00 5.41693 -155.818 -5.41693 5.41693 0.34 0.000714768 0.000664242 0.0440555 0.0409587 -1 -1 -1 -1 40 2971 24 6.99608e+06 309029 706193. 2443.58 1.68 0.194532 0.169876 26914 176310 -1 2506 19 1927 2738 217010 45892 4.58734 4.58734 -155.424 -4.58734 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0158808 0.0141898 96 64 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_098.v common 3.88 vpr 63.83 MiB -1 -1 0.25 18352 1 0.03 -1 -1 30360 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65364 32 32 331 280 1 215 82 17 17 289 -1 unnamed_device 24.3 MiB 0.41 1019 12898 5003 5774 2121 63.8 MiB 0.12 0.00 4.02148 -135.181 -4.02148 4.02148 0.34 0.000675106 0.000626565 0.0511943 0.0476231 -1 -1 -1 -1 40 2554 27 6.99608e+06 264882 706193. 2443.58 1.32 0.190559 0.166595 26914 176310 -1 2119 21 1505 2040 162418 36238 3.52995 3.52995 -133.179 -3.52995 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0276916 0.0241046 87 65 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_099.v common 3.90 vpr 64.20 MiB -1 -1 0.12 18384 1 0.03 -1 -1 30420 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65736 32 32 326 263 1 198 81 17 17 289 -1 unnamed_device 24.5 MiB 0.35 947 12506 5206 6883 417 64.2 MiB 0.12 0.00 4.17438 -127.536 -4.17438 4.17438 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/home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 386 307 1 240 85 17 17 289 -1 unnamed_device 24.5 MiB 0.41 1172 14779 4944 7940 1895 64.2 MiB 0.14 0.00 3.49383 -123.038 -3.49383 3.49383 0.35 0.000744675 0.000690682 0.0623874 0.0579082 -1 -1 -1 -1 38 3062 42 6.99608e+06 309029 678818. 2348.85 7.53 0.401185 0.347255 26626 170182 -1 2503 21 2030 2756 207605 45774 3.22392 3.22392 -130.363 -3.22392 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0313101 0.0274444 101 62 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.37 vpr 63.54 MiB -1 -1 0.22 18176 1 0.03 -1 -1 30312 -1 -1 17 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 29 32 269 229 1 166 78 17 17 289 -1 unnamed_device 23.9 MiB 0.27 653 11698 4829 5917 952 63.5 MiB 0.10 0.00 3.87612 -110.458 -3.87612 3.87612 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/home/elgamma8/research/release/vtr-verilog-to-routing 64692 31 32 229 197 1 138 78 17 17 289 -1 unnamed_device 23.7 MiB 0.48 649 8378 3363 4684 331 63.2 MiB 0.07 0.00 3.20338 -90.6125 -3.20338 3.20338 0.33 0.000536852 0.000500057 0.0285834 0.0266282 -1 -1 -1 -1 38 1740 26 6.99608e+06 220735 678818. 2348.85 1.36 0.137751 0.119285 26626 170182 -1 1408 23 1078 1745 129004 28747 2.71597 2.71597 -95.6168 -2.71597 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0241496 0.0209859 55 4 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_119.v common 4.78 vpr 64.14 MiB -1 -1 0.26 18268 1 0.03 -1 -1 30284 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65676 32 32 412 334 1 258 87 17 17 289 -1 unnamed_device 24.6 MiB 0.43 1319 11991 3957 5960 2074 64.1 MiB 0.12 0.00 4.93268 -164.708 -4.93268 4.93268 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21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65812 32 32 396 299 1 231 85 17 17 289 -1 unnamed_device 24.5 MiB 0.32 1108 13105 3671 7584 1850 64.3 MiB 0.14 0.00 5.6322 -158.993 -5.6322 5.6322 0.33 0.000777235 0.000722016 0.0575258 0.0534752 -1 -1 -1 -1 44 3147 38 6.99608e+06 309029 787024. 2723.27 9.94 0.396837 0.342694 27778 195446 -1 2287 34 2017 3107 304138 115013 4.85505 4.85505 -154.503 -4.85505 0 0 997811. 3452.63 0.04 0.15 0.16 -1 -1 0.04 0.0485984 0.0422188 99 34 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_123.v common 3.20 vpr 63.57 MiB -1 -1 0.17 18072 1 0.03 -1 -1 30108 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65100 30 32 224 207 1 134 75 17 17 289 -1 unnamed_device 24.1 MiB 0.28 577 10029 4242 5446 341 63.6 MiB 0.08 0.00 2.33546 -85.6612 -2.33546 2.33546 0.33 0.000504067 0.000469255 0.0336791 0.0313571 -1 -1 -1 -1 36 1749 31 6.99608e+06 191304 648988. 2245.63 1.08 0.138424 0.120065 26050 158493 -1 1357 21 893 1110 100119 24717 2.39608 2.39608 -90.4929 -2.39608 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0205929 0.0178716 52 34 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_124.v common 5.20 vpr 63.46 MiB -1 -1 0.12 18016 1 0.03 -1 -1 30352 -1 -1 16 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 30 32 286 239 1 159 78 17 17 289 -1 unnamed_device 24.1 MiB 1.18 829 10868 4869 5663 336 63.5 MiB 0.09 0.00 3.98607 -129.511 -3.98607 3.98607 0.33 0.000597854 0.000554481 0.0409971 0.0380891 -1 -1 -1 -1 36 2107 25 6.99608e+06 235451 648988. 2245.63 2.17 0.233413 0.20137 26050 158493 -1 1748 17 1098 1623 130284 30423 3.71161 3.71161 -136.48 -3.71161 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0214257 0.018737 71 34 -1 -1 -1 -1 - fixed_k6_frac_2uripple_N8_22nm.xml mult_125.v common 4.67 vpr 63.82 MiB -1 -1 0.23 18140 1 0.03 -1 -1 30060 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65348 32 32 296 247 1 182 85 17 17 289 -1 unnamed_device 24.2 MiB 0.32 859 13477 5604 7598 275 63.8 MiB 0.12 0.00 3.71535 -130.45 -3.71535 3.71535 0.36 0.000628988 0.00058134 0.0476797 0.0443348 -1 -1 -1 -1 38 2908 46 6.99608e+06 309029 678818. 2348.85 2.29 0.197424 0.171974 26626 170182 -1 2101 23 1401 2302 222408 54792 4.32052 4.32052 -140.632 -4.32052 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 317 271 1 175 83 17 17 289 -1 unnamed_device 24.0 MiB 1.95 910 8723 2060 6322 341 63.1 MiB 0.09 0.00 3.31917 -111.486 -3.31917 3.31917 0.34 0.00063441 0.000590038 0.0329474 0.0306471 -1 -1 -1 -1 32 2150 19 6.87369e+06 279477 586450. 2029.24 0.58 0.106092 0.093061 25474 144626 -1 1748 20 1043 1565 98545 24803 2.91151 2.91151 -112.578 -2.91151 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0244429 0.0212104 110 64 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_010.v common 6.12 vpr 63.35 MiB -1 -1 0.22 18120 1 0.03 -1 -1 30076 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 32 32 298 248 1 162 81 17 17 289 -1 unnamed_device 23.6 MiB 3.62 974 4631 910 3488 233 63.4 MiB 0.06 0.00 3.98344 -131.884 -3.98344 3.98344 0.33 0.000626678 0.000583326 0.0185195 0.0172494 -1 -1 -1 -1 30 2081 18 6.87369e+06 237555 556674. 1926.21 0.54 0.0883308 0.0768845 25186 138497 -1 1827 21 1179 2019 124096 30001 2.82686 2.82686 -118.966 -2.82686 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0253455 0.0219646 107 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_011.v common 5.19 vpr 63.25 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30308 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 30 32 303 262 1 148 80 17 17 289 -1 unnamed_device 23.6 MiB 2.64 812 9368 2251 6434 683 63.2 MiB 0.10 0.00 3.87398 -114.403 -3.87398 3.87398 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 23.9 MiB 2.12 926 9599 2091 6833 675 63.1 MiB 0.11 0.00 4.83358 -141.45 -4.83358 4.83358 0.33 0.000713803 0.000663884 0.0340711 0.0316564 -1 -1 -1 -1 30 2718 27 6.87369e+06 433189 556674. 1926.21 0.65 0.123589 0.10815 25186 138497 -1 1936 20 1247 1954 117467 30151 4.17226 4.17226 -144.094 -4.17226 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.014747 0.0130134 133 61 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_015.v common 4.22 vpr 63.17 MiB -1 -1 0.23 18132 1 0.03 -1 -1 30400 -1 -1 21 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 29 32 248 215 1 142 82 17 17 289 -1 unnamed_device 23.9 MiB 1.70 711 8982 2096 6475 411 63.2 MiB 0.08 0.00 3.07868 -92.9683 -3.07868 3.07868 0.33 0.000544701 0.000507131 0.0291861 0.0271418 -1 -1 -1 -1 30 1671 24 6.87369e+06 293451 556674. 1926.21 0.54 0.09513 0.0832085 25186 138497 -1 1338 20 791 1267 69154 17413 2.61566 2.61566 -91.2171 -2.61566 0 0 706193. 2443.58 0.04 0.06 0.11 -1 -1 0.04 0.0269583 0.0234237 94 27 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 5.24 vpr 63.32 MiB -1 -1 0.24 18324 1 0.03 -1 -1 30280 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 24.0 MiB 1.91 1084 8668 1982 6147 539 63.3 MiB 0.10 0.00 3.90567 -127.707 -3.90567 3.90567 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 23.7 MiB 0.66 689 12139 3691 7050 1398 63.0 MiB 0.09 0.00 2.38778 -83.5564 -2.38778 2.38778 0.34 0.000495747 0.000461876 0.038516 0.0358607 -1 -1 -1 -1 32 1442 23 6.87369e+06 209608 586450. 2029.24 0.50 0.0985935 0.0870204 25474 144626 -1 1219 18 585 811 57943 14080 2.01382 2.01382 -84.6315 -2.01382 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0179977 0.0155952 71 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 5.39 vpr 63.12 MiB -1 -1 0.24 18340 1 0.03 -1 -1 30384 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 285 227 1 169 87 17 17 289 -1 unnamed_device 23.8 MiB 1.15 1002 13719 4614 6837 2268 63.4 MiB 0.14 0.00 4.57022 -130.066 -4.57022 4.57022 0.33 0.00061934 0.000575759 0.0461905 0.0429273 -1 -1 -1 -1 30 2201 25 6.87369e+06 321398 556674. 1926.21 0.60 0.122115 0.10779 25186 138497 -1 1821 21 1157 2162 119285 29514 3.7041 3.7041 -123.476 -3.7041 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0254677 0.0220817 119 3 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 2.97 vpr 63.02 MiB -1 -1 0.12 17552 1 0.02 -1 -1 30008 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 23.8 MiB 0.62 529 9036 3698 5030 308 63.0 MiB 0.07 0.00 2.64533 -79.7813 -2.64533 2.64533 0.34 0.000423617 0.000392859 0.0254041 0.0235785 -1 -1 -1 -1 28 1296 30 6.87369e+06 167686 531479. 1839.03 0.56 0.0819974 0.0717561 24610 126494 -1 1030 14 522 612 45566 12360 2.19737 2.19737 -79.5748 -2.19737 0 0 648988. 2245.63 0.03 0.05 0.10 -1 -1 0.03 0.0206278 0.0179992 65 3 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 3.58 vpr 63.64 MiB -1 -1 0.23 18288 1 0.03 -1 -1 30140 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65172 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 24.0 MiB 0.98 1049 16069 4575 9607 1887 63.6 MiB 0.15 0.00 4.58208 -129.699 -4.58208 4.58208 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 284 241 1 148 82 17 17 289 -1 unnamed_device 23.7 MiB 0.94 856 12720 4032 6930 1758 63.3 MiB 0.12 0.00 3.07458 -105.313 -3.07458 3.07458 0.33 0.000608 0.000559447 0.0450373 0.0417759 -1 -1 -1 -1 32 1770 20 6.87369e+06 251529 586450. 2029.24 0.53 0.114315 0.100881 25474 144626 -1 1498 21 757 1288 84508 20239 2.64866 2.64866 -104.259 -2.64866 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0130009 0.0114168 101 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.53 vpr 63.14 MiB -1 -1 0.14 18236 1 0.03 -1 -1 30272 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 30 32 262 227 1 138 87 17 17 289 -1 unnamed_device 23.6 MiB 1.11 850 14103 4319 8139 1645 63.1 MiB 0.12 0.00 3.14772 -102.363 -3.14772 3.14772 0.33 0.00056828 0.000529209 0.0435607 0.0405281 -1 -1 -1 -1 32 1755 31 6.87369e+06 349346 586450. 2029.24 0.57 0.118019 0.103831 25474 144626 -1 1498 19 881 1432 93880 22924 2.79396 2.79396 -97.0612 -2.79396 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0210251 0.018223 97 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 3.40 vpr 63.08 MiB -1 -1 0.16 18000 1 0.02 -1 -1 30160 -1 -1 24 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64596 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 23.5 MiB 0.98 762 14175 5132 6824 2219 63.1 MiB 0.12 0.00 3.46791 -98.5079 -3.46791 3.46791 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64712 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 23.6 MiB 2.42 855 9536 2217 6358 961 63.2 MiB 0.09 0.00 3.08002 -99.9202 -3.08002 3.08002 0.34 0.000605347 0.000562439 0.0322847 0.0300207 -1 -1 -1 -1 32 1836 20 6.87369e+06 349346 586450. 2029.24 0.54 0.101683 0.0890847 25474 144626 -1 1618 17 896 1401 87699 22004 2.36147 2.36147 -96.2223 -2.36147 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0208019 0.0180997 105 54 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_035.v common 5.60 vpr 63.82 MiB -1 -1 0.22 18412 1 0.04 -1 -1 30340 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 367 282 1 201 104 17 17 289 -1 unnamed_device 24.2 MiB 2.99 1201 11572 2628 7875 1069 63.8 MiB 0.12 0.00 4.28409 -125.895 -4.28409 4.28409 0.33 0.000745621 0.000691639 0.0376247 0.0349383 -1 -1 -1 -1 32 2850 21 6.87369e+06 558954 586450. 2029.24 0.60 0.123608 0.108597 25474 144626 -1 2283 22 1202 2387 140467 34356 3.5931 3.5931 -122.354 -3.5931 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0309075 0.0268465 156 29 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_036.v common 5.65 vpr 63.77 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30256 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 32 32 391 311 1 194 104 17 17 289 -1 unnamed_device 24.1 MiB 2.85 1115 17428 4398 11199 1831 63.8 MiB 0.18 0.00 4.01296 -135.521 -4.01296 4.01296 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29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 31 32 377 302 1 237 92 17 17 289 -1 unnamed_device 24.3 MiB 3.21 1226 11477 3074 7440 963 63.3 MiB 0.14 0.00 5.94301 -174.677 -5.94301 5.94301 0.33 0.000740882 0.00068947 0.0435873 0.0404978 -1 -1 -1 -1 32 3381 27 6.87369e+06 405241 586450. 2029.24 0.86 0.135821 0.119293 25474 144626 -1 2594 21 2065 3065 259228 59072 4.91379 4.91379 -168.168 -4.91379 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.030074 0.0261518 156 64 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_040.v common 10.36 vpr 63.25 MiB -1 -1 0.13 18256 1 0.03 -1 -1 30432 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 32 32 361 291 1 189 97 17 17 289 -1 unnamed_device 24.1 MiB 2.80 942 18079 4845 10579 2655 63.1 MiB 0.17 0.00 3.80724 -119.205 -3.80724 3.80724 0.33 0.000719091 0.000668366 0.0611155 0.0567946 -1 -1 -1 -1 32 2842 49 6.87369e+06 461137 586450. 2029.24 0.76 0.175295 0.154435 25474 144626 -1 2003 21 1296 2243 161130 40238 3.17181 3.17181 -117.395 -3.17181 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0299406 0.0260509 137 55 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_050.v common 5.43 vpr 63.39 MiB -1 -1 0.26 18356 1 0.03 -1 -1 30236 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 382 305 1 193 99 17 17 289 -1 unnamed_device 24.3 MiB 2.75 1194 15147 4115 8922 2110 63.4 MiB 0.17 0.00 4.12873 -137.061 -4.12873 4.12873 0.33 0.000747128 0.000694047 0.0516993 0.0480117 -1 -1 -1 -1 30 2637 23 6.87369e+06 489084 556674. 1926.21 0.62 0.140245 0.123846 25186 138497 -1 2186 20 1312 2080 127606 30703 3.18081 3.18081 -123.292 -3.18081 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0284563 0.0247655 145 62 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 3.96 vpr 63.45 MiB -1 -1 0.26 18084 1 0.03 -1 -1 30416 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 306 248 1 170 97 17 17 289 -1 unnamed_device 24.3 MiB 0.96 1051 16969 4458 10747 1764 63.4 MiB 0.16 0.00 4.25889 -127.121 -4.25889 4.25889 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22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 387 315 1 194 86 17 17 289 -1 unnamed_device 24.2 MiB 2.41 1107 13883 4421 7374 2088 63.3 MiB 0.15 0.00 4.4264 -134.375 -4.4264 4.4264 0.34 0.00074745 0.000694485 0.0572042 0.0531062 -1 -1 -1 -1 32 2766 23 6.87369e+06 307425 586450. 2029.24 0.63 0.14684 0.129797 25474 144626 -1 2283 20 1421 2543 162506 40189 3.63536 3.63536 -132.707 -3.63536 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0293206 0.0255442 134 77 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 3.49 vpr 63.16 MiB -1 -1 0.22 18112 1 0.03 -1 -1 30340 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 251 219 1 141 87 17 17 289 -1 unnamed_device 23.7 MiB 0.88 781 8151 1829 5687 635 63.2 MiB 0.08 0.00 3.42581 -102.974 -3.42581 3.42581 0.41 0.000559902 0.000521562 0.0254085 0.0236473 -1 -1 -1 -1 28 1904 23 6.87369e+06 321398 531479. 1839.03 0.53 0.0929223 0.0810831 24610 126494 -1 1688 22 1081 1762 117647 29623 2.79596 2.79596 -101.105 -2.79596 0 0 648988. 2245.63 0.03 0.06 0.10 -1 -1 0.03 0.0233409 0.0201884 93 23 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 4.41 vpr 63.22 MiB -1 -1 0.25 18552 1 0.03 -1 -1 30108 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 341 285 1 188 84 17 17 289 -1 unnamed_device 24.0 MiB 1.74 910 13260 3607 7806 1847 63.2 MiB 0.14 0.00 3.77904 -129.086 -3.77904 3.77904 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/home/elgamma8/research/release/vtr-verilog-to-routing 65424 30 32 375 299 1 188 85 17 17 289 -1 unnamed_device 24.0 MiB 3.12 1029 9757 2105 6512 1140 63.9 MiB 0.12 0.00 4.57902 -143.928 -4.57902 4.57902 0.33 0.000730298 0.000678703 0.0403111 0.0374677 -1 -1 -1 -1 28 2535 23 6.87369e+06 321398 531479. 1839.03 0.64 0.127412 0.111966 24610 126494 -1 2307 21 1874 2865 205104 49082 3.9547 3.9547 -144.752 -3.9547 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0166106 0.0146556 137 63 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 5.03 vpr 63.10 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30352 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 23.9 MiB 2.02 1137 13355 3696 8021 1638 63.1 MiB 0.15 0.00 5.16481 -152.482 -5.16481 5.16481 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 32 32 365 294 1 187 86 17 17 289 -1 unnamed_device 24.0 MiB 2.29 977 11804 3582 6996 1226 63.3 MiB 0.15 0.00 4.77578 -141.077 -4.77578 4.77578 0.34 0.000721237 0.000668993 0.0471484 0.0438001 -1 -1 -1 -1 30 2619 21 6.87369e+06 307425 556674. 1926.21 0.66 0.132756 0.116983 25186 138497 -1 2066 20 1426 2450 128813 33448 3.90766 3.90766 -135.71 -3.90766 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0277408 0.024151 132 57 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 5.03 vpr 63.49 MiB -1 -1 0.27 18544 1 0.03 -1 -1 30308 -1 -1 29 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65016 29 32 378 310 1 179 90 17 17 289 -1 unnamed_device 24.2 MiB 2.28 945 16170 4095 11127 948 63.5 MiB 0.16 0.00 4.12999 -122.875 -4.12999 4.12999 0.33 0.000715356 0.000664292 0.0600459 0.055713 -1 -1 -1 -1 32 2398 22 6.87369e+06 405241 586450. 2029.24 0.61 0.145064 0.128358 25474 144626 -1 1959 21 1386 2247 136731 34828 3.12181 3.12181 -115.774 -3.12181 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0291387 0.025244 132 85 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.69 vpr 63.22 MiB -1 -1 0.21 17864 1 0.03 -1 -1 30328 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 23.6 MiB 1.07 892 12542 3412 7235 1895 63.2 MiB 0.11 0.00 3.98264 -119.291 -3.98264 3.98264 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65128 32 32 269 231 1 170 82 17 17 289 -1 unnamed_device 23.9 MiB 2.13 994 9694 2678 5995 1021 63.6 MiB 0.10 0.00 4.37292 -124.998 -4.37292 4.37292 0.33 0.00058825 0.000548397 0.0336292 0.0313019 -1 -1 -1 -1 26 2325 22 6.87369e+06 251529 503264. 1741.40 0.62 0.103077 0.090504 24322 120374 -1 2098 22 1212 1576 117648 28606 3.4928 3.4928 -124.305 -3.4928 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0245323 0.0212581 103 29 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_090.v common 3.70 vpr 63.16 MiB -1 -1 0.23 17880 1 0.03 -1 -1 30368 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64680 31 32 245 205 1 153 84 17 17 289 -1 unnamed_device 23.7 MiB 1.09 879 14358 4211 8419 1728 63.2 MiB 0.13 0.00 3.81898 -115.032 -3.81898 3.81898 0.33 0.000551096 0.000512803 0.0451184 0.0419713 -1 -1 -1 -1 32 1927 21 6.87369e+06 293451 586450. 2029.24 0.58 0.11685 0.103169 25474 144626 -1 1705 21 1147 1895 134417 30219 2.80196 2.80196 -107.148 -2.80196 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226517 0.0196196 100 4 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 5.14 vpr 63.21 MiB -1 -1 0.24 18416 1 0.03 -1 -1 30464 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 24.0 MiB 2.49 1167 13738 4717 6121 2900 63.2 MiB 0.14 0.00 4.82535 -151.45 -4.82535 4.82535 0.34 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65128 30 32 316 264 1 165 96 17 17 289 -1 unnamed_device 24.0 MiB 2.11 882 12798 3427 7781 1590 63.6 MiB 0.12 0.00 3.60295 -105.856 -3.60295 3.60295 0.33 0.000644126 0.000598529 0.0398531 0.0369682 -1 -1 -1 -1 30 1919 24 6.87369e+06 475111 556674. 1926.21 0.60 0.11996 0.10565 25186 138497 -1 1665 19 1031 1845 92885 24170 2.80666 2.80666 -100.682 -2.80666 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0237563 0.0206309 119 52 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_095.v common 3.39 vpr 63.20 MiB -1 -1 0.12 18080 1 0.03 -1 -1 30460 -1 -1 24 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0274458 0.0239019 143 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 5.85 vpr 63.91 MiB -1 -1 0.25 18376 1 0.03 -1 -1 30128 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65444 32 32 386 307 1 196 100 17 17 289 -1 unnamed_device 24.3 MiB 3.01 1086 10308 2517 7280 511 63.9 MiB 0.12 0.00 4.14663 -136.709 -4.14663 4.14663 0.34 0.000747845 0.000694676 0.0358158 0.0332704 -1 -1 -1 -1 28 2852 22 6.87369e+06 503058 531479. 1839.03 0.74 0.128014 0.1121 24610 126494 -1 2345 20 1518 2459 158677 39350 3.26061 3.26061 -128.829 -3.26061 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0293717 0.0255279 148 62 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 4.20 vpr 63.19 MiB -1 -1 0.22 18280 1 0.03 -1 -1 30284 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 29 32 269 229 1 150 81 17 17 289 -1 unnamed_device 23.5 MiB 1.73 676 13381 4841 5719 2821 63.2 MiB 0.12 0.00 3.95844 -115.993 -3.95844 3.95844 0.33 0.000576391 0.00053603 0.0458306 0.0426133 -1 -1 -1 -1 32 1602 21 6.87369e+06 279477 586450. 2029.24 0.54 0.11245 0.0993597 25474 144626 -1 1303 20 1078 1620 101124 24300 3.02726 3.02726 -105.477 -3.02726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226321 0.0196502 101 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 4.33 vpr 63.11 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30284 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 32 32 310 266 1 175 84 17 17 289 -1 unnamed_device 24.0 MiB 1.51 1025 15456 4644 9539 1273 63.1 MiB 0.15 0.00 3.98516 -120.978 -3.98516 3.98516 0.33 0.000629119 0.000584837 0.0550716 0.051179 -1 -1 -1 -1 26 2517 27 6.87369e+06 279477 503264. 1741.40 0.77 0.135191 0.119354 24322 120374 -1 2108 22 1426 1967 170507 40619 3.43941 3.43941 -126.369 -3.43941 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0266223 0.0230652 108 58 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 4.68 vpr 63.76 MiB -1 -1 0.15 18476 1 0.03 -1 -1 30344 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65292 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 24.0 MiB 1.43 987 18428 5110 10243 3075 63.8 MiB 0.17 0.00 4.59612 -128.416 -4.59612 4.59612 0.33 0.00066769 0.000620041 0.0537939 0.049922 -1 -1 -1 -1 26 2846 38 6.87369e+06 544980 503264. 1741.40 1.16 0.153274 0.135079 24322 120374 -1 2300 23 1587 2983 214840 50593 4.066 4.066 -137.302 -4.066 0 0 618332. 2139.56 0.02 0.05 0.07 -1 -1 0.02 0.0152959 0.0134031 135 33 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 4.72 vpr 63.51 MiB -1 -1 0.22 18056 1 0.03 -1 -1 30240 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65032 29 32 262 224 1 168 81 17 17 289 -1 unnamed_device 23.9 MiB 2.21 926 13031 3833 7297 1901 63.5 MiB 0.12 0.00 4.39772 -121.351 -4.39772 4.39772 0.34 0.000564946 0.000526026 0.0438255 0.0407939 -1 -1 -1 -1 26 2366 26 6.87369e+06 279477 503264. 1741.40 0.58 0.115317 0.101479 24322 120374 -1 1950 21 1326 1745 124283 31179 3.5018 3.5018 -119.379 -3.5018 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65392 31 32 373 300 1 185 101 17 17 289 -1 unnamed_device 24.3 MiB 2.52 996 8326 1655 6069 602 63.9 MiB 0.09 0.00 3.95528 -124.82 -3.95528 3.95528 0.33 0.00073019 0.000672729 0.028011 0.0259846 -1 -1 -1 -1 30 2187 19 6.87369e+06 531006 556674. 1926.21 0.58 0.110267 0.0962367 25186 138497 -1 1812 19 1272 2135 103364 26073 2.96596 2.96596 -116.595 -2.96596 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0270136 0.0235073 142 64 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 4.45 vpr 63.19 MiB -1 -1 0.23 18184 1 0.03 -1 -1 30328 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 31 32 265 230 1 169 81 17 17 289 -1 unnamed_device 23.5 MiB 1.98 964 7606 1989 5205 412 63.2 MiB 0.08 0.00 3.71466 -116.831 -3.71466 3.71466 0.33 0.00058092 0.000541652 0.026736 0.0248919 -1 -1 -1 -1 30 2104 20 6.87369e+06 251529 556674. 1926.21 0.54 0.0928595 0.0811791 25186 138497 -1 1736 21 950 1365 79050 19847 3.06461 3.06461 -112.199 -3.06461 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0278341 0.0244082 101 34 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 5.45 vpr 63.81 MiB -1 -1 0.25 18348 1 0.03 -1 -1 29996 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65340 32 32 349 286 1 177 96 17 17 289 -1 unnamed_device 24.1 MiB 2.52 1048 13455 3508 9157 790 63.8 MiB 0.13 0.00 3.8199 -117.926 -3.8199 3.8199 0.34 0.000698483 0.000649166 0.0451115 0.0418957 -1 -1 -1 -1 26 2805 33 6.87369e+06 447163 503264. 1741.40 0.91 0.145167 0.127573 24322 120374 -1 2183 29 1347 2248 170016 40039 3.04151 3.04151 -116.867 -3.04151 0 0 618332. 2139.56 0.03 0.09 0.10 -1 -1 0.03 0.0361119 0.0312691 130 57 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 5.38 vpr 63.44 MiB -1 -1 0.15 18316 1 0.04 -1 -1 30280 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64960 31 32 396 325 1 185 96 17 17 289 -1 unnamed_device 24.4 MiB 2.88 1015 16959 5374 8849 2736 63.4 MiB 0.17 0.00 3.7606 -128.355 -3.7606 3.7606 0.33 0.000748216 0.000694083 0.0605097 0.0561856 -1 -1 -1 -1 32 2262 24 6.87369e+06 461137 586450. 2029.24 0.59 0.150753 0.133203 25474 144626 -1 1821 20 1416 2136 127559 31716 2.80391 2.80391 -117.048 -2.80391 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0156045 0.0137633 138 91 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 4.70 vpr 63.33 MiB -1 -1 0.24 18292 1 0.03 -1 -1 30324 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 303 262 1 154 81 17 17 289 -1 unnamed_device 24.0 MiB 2.09 926 11806 3071 7035 1700 63.3 MiB 0.11 0.00 3.46595 -111.033 -3.46595 3.46595 0.34 0.000626318 0.000581564 0.0441167 0.0410371 -1 -1 -1 -1 32 1999 19 6.87369e+06 237555 586450. 2029.24 0.56 0.115252 0.101659 25474 144626 -1 1755 16 874 1380 84592 21150 2.99146 2.99146 -110.25 -2.99146 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0205676 0.0179449 99 57 -1 -1 -1 -1 - fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 4.69 vpr 63.04 MiB -1 -1 0.23 18180 1 0.03 -1 -1 30264 -1 -1 19 32 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 28 32 260 223 1 163 85 17 17 289 -1 unnamed_device 23.6 MiB 1.23 910 14593 5077 7414 2102 63.1 MiB 0.13 0.00 4.29929 -120.332 -4.29929 4.29929 0.34 0.000557357 0.000518617 0.0461162 0.0428912 -1 -1 -1 -1 32 2100 20 6.89349e+06 352346 586450. 2029.24 0.56 0.111197 0.098241 25474 144626 -1 1696 21 895 1529 95985 22999 3.23235 3.23235 -110.54 -3.23235 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0122668 0.0107644 108 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 3.76 vpr 63.04 MiB -1 -1 0.23 17900 1 0.03 -1 -1 30224 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 23.5 MiB 1.06 749 9160 2232 6447 481 63.0 MiB 0.09 0.00 3.86328 -116.366 -3.86328 3.86328 0.33 0.000573773 0.000532341 0.031373 0.0291874 -1 -1 -1 -1 28 2273 28 6.89349e+06 253689 531479. 1839.03 0.68 0.104099 0.0910894 24610 126494 -1 1785 34 1750 3035 275769 99959 2.87716 2.87716 -113.369 -2.87716 0 0 648988. 2245.63 0.03 0.12 0.10 -1 -1 0.03 0.0338085 0.0290584 101 3 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 3.63 vpr 63.10 MiB -1 -1 0.24 18240 1 0.03 -1 -1 30132 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 31 32 271 231 1 172 84 17 17 289 -1 unnamed_device 23.5 MiB 1.03 896 7770 1848 5501 421 63.1 MiB 0.09 0.00 3.62655 -110.965 -3.62655 3.62655 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64628 32 32 391 311 1 250 93 17 17 289 -1 unnamed_device 24.1 MiB 1.73 1433 15423 4226 9063 2134 63.1 MiB 0.18 0.00 4.56723 -154.163 -4.56723 4.56723 0.33 0.000759097 0.000705105 0.0586858 0.0546043 -1 -1 -1 -1 30 3141 34 6.89349e+06 408721 556674. 1926.21 0.84 0.164331 0.145039 25186 138497 -1 2546 22 2111 2906 187308 44776 3.63025 3.63025 -138.661 -3.63025 0 0 706193. 2443.58 0.03 0.09 0.11 -1 -1 0.03 0.0322373 0.0280504 162 65 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_037.v common 3.71 vpr 63.12 MiB -1 -1 0.24 18508 1 0.03 -1 -1 30236 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 23.6 MiB 1.01 863 12331 3145 7318 1868 63.1 MiB 0.12 0.00 4.00748 -119.789 -4.00748 4.00748 0.34 0.000603096 0.000561509 0.0437123 0.0406478 -1 -1 -1 -1 32 1949 21 6.89349e+06 253689 586450. 2029.24 0.58 0.11396 0.100554 25474 144626 -1 1645 19 873 1326 100623 24502 3.22455 3.22455 -109.63 -3.22455 0 0 744469. 2576.02 0.03 0.06 0.14 -1 -1 0.03 0.0229871 0.0200214 106 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 4.53 vpr 63.14 MiB -1 -1 0.28 18500 1 0.03 -1 -1 30392 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 31 32 370 297 1 235 91 17 17 289 -1 unnamed_device 24.2 MiB 1.85 1334 16615 5524 9183 1908 63.1 MiB 0.18 0.00 4.35803 -138.286 -4.35803 4.35803 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/home/elgamma8/research/release/vtr-verilog-to-routing 64684 32 32 393 312 1 243 90 17 17 289 -1 unnamed_device 24.1 MiB 2.00 1197 8532 1944 6080 508 63.2 MiB 0.11 0.00 5.6615 -176.256 -5.6615 5.6615 0.33 0.000765182 0.000711071 0.034673 0.0322116 -1 -1 -1 -1 32 3572 28 6.89349e+06 366440 586450. 2029.24 0.87 0.132281 0.11584 25474 144626 -1 2640 22 1876 2860 206960 49868 4.38809 4.38809 -163.546 -4.38809 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0314949 0.0273942 161 65 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 3.73 vpr 63.07 MiB -1 -1 0.23 17908 1 0.03 -1 -1 30152 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 23.5 MiB 0.88 858 12156 3731 6704 1721 63.1 MiB 0.11 0.00 3.31865 -102.092 -3.31865 3.31865 0.33 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0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0277509 0.0242359 173 90 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 4.89 vpr 63.25 MiB -1 -1 0.15 18432 1 0.03 -1 -1 30176 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 32 32 376 318 1 259 92 17 17 289 -1 unnamed_device 24.2 MiB 1.84 1293 9614 2367 6489 758 63.2 MiB 0.12 0.00 4.89568 -164.328 -4.89568 4.89568 0.33 0.000704531 0.000653159 0.0352242 0.0326131 -1 -1 -1 -1 32 3167 23 6.89349e+06 394628 586450. 2029.24 0.73 0.122092 0.106854 25474 144626 -1 2517 22 2283 2786 179066 44397 4.21384 4.21384 -161.857 -4.21384 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0296871 0.0257565 155 96 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 4.27 vpr 63.02 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30208 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 32 32 360 293 1 226 91 17 17 289 -1 unnamed_device 23.8 MiB 1.40 1307 13759 4403 8202 1154 63.0 MiB 0.17 0.00 4.10168 -130.557 -4.10168 4.10168 0.33 0.000711311 0.00066117 0.0570836 0.0530446 -1 -1 -1 -1 32 2791 48 6.89349e+06 380534 586450. 2029.24 0.71 0.169513 0.148957 25474 144626 -1 2228 17 1439 1975 125236 30124 2.97891 2.97891 -117.401 -2.97891 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0245511 0.0214454 147 60 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 5.73 vpr 63.15 MiB -1 -1 0.14 18740 1 0.03 -1 -1 30328 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64668 32 32 396 299 1 240 92 17 17 289 -1 unnamed_device 24.1 MiB 2.03 1350 12098 3111 7804 1183 63.2 MiB 0.17 0.00 5.93815 -178.759 -5.93815 5.93815 0.34 0.000774961 0.000720753 0.0484735 0.0450489 -1 -1 -1 -1 30 3179 30 6.89349e+06 394628 556674. 1926.21 1.07 0.154751 0.136253 25186 138497 -1 2629 22 1591 2517 184543 45433 4.56655 4.56655 -159.834 -4.56655 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0173111 0.0152944 167 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 3.42 vpr 63.09 MiB -1 -1 0.18 18056 1 0.03 -1 -1 30168 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 30 32 224 207 1 138 79 17 17 289 -1 unnamed_device 23.6 MiB 0.86 744 11064 2972 6586 1506 63.1 MiB 0.09 0.00 3.06986 -93.837 -3.06986 3.06986 0.33 0.00050022 0.000465468 0.0342512 0.0318795 -1 -1 -1 -1 32 1608 21 6.89349e+06 239595 586450. 2029.24 0.51 0.0930254 0.0819585 25474 144626 -1 1362 19 746 975 64274 15732 2.15637 2.15637 -86.663 -2.15637 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0186802 0.0161973 80 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 4.09 vpr 63.19 MiB -1 -1 0.24 18064 1 0.03 -1 -1 30332 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 30 32 286 239 1 176 85 17 17 289 -1 unnamed_device 23.6 MiB 1.17 970 14221 4684 7353 2184 63.2 MiB 0.13 0.00 4.47457 -139.461 -4.47457 4.47457 0.33 0.000598059 0.000556233 0.0476839 0.0443531 -1 -1 -1 -1 32 2088 19 6.89349e+06 324158 586450. 2029.24 0.57 0.116239 0.102831 25474 144626 -1 1798 19 1209 1755 123419 28254 3.20405 3.20405 -123.196 -3.20405 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0213811 0.0188746 120 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 4.64 vpr 63.24 MiB -1 -1 0.14 18164 1 0.04 -1 -1 30036 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 32 32 296 247 1 187 89 17 17 289 -1 unnamed_device 23.9 MiB 1.81 1127 15137 4309 8906 1922 63.2 MiB 0.15 0.00 4.30299 -142.144 -4.30299 4.30299 0.33 0.000624179 0.000580082 0.0500647 0.0464926 -1 -1 -1 -1 32 2632 22 6.89349e+06 352346 586450. 2029.24 0.65 0.124241 0.109743 25474 144626 -1 2086 21 1194 2198 152487 35249 3.2979 3.2979 -129.639 -3.2979 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0252727 0.0218883 119 34 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 3.81 vpr 63.04 MiB -1 -1 0.23 18076 1 0.03 -1 -1 30284 -1 -1 22 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 25 32 216 194 1 138 79 17 17 289 -1 unnamed_device 23.6 MiB 0.97 598 9881 3477 4123 2281 63.0 MiB 0.07 0.00 3.7089 -85.4656 -3.7089 3.7089 0.33 0.000478077 0.000444482 0.0293864 0.0272887 -1 -1 -1 -1 36 1448 42 6.89349e+06 310065 648988. 2245.63 1.04 0.136492 0.117908 26050 158493 -1 1138 18 657 975 59260 15977 2.93981 2.93981 -80.0624 -2.93981 0 0 828058. 2865.25 0.03 0.03 0.09 -1 -1 0.03 0.00980015 0.00865384 88 29 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 4.99 vpr 63.14 MiB -1 -1 0.15 18352 1 0.03 -1 -1 30352 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64660 32 32 376 307 1 242 90 17 17 289 -1 unnamed_device 24.1 MiB 2.30 1430 16170 4616 9563 1991 63.1 MiB 0.18 0.00 4.51899 -138.857 -4.51899 4.51899 0.33 0.000721273 0.000669662 0.0603201 0.0559474 -1 -1 -1 -1 32 3301 26 6.89349e+06 366440 586450. 2029.24 0.66 0.151815 0.134188 25474 144626 -1 2662 22 1825 2779 185735 42367 3.63286 3.63286 -129.152 -3.63286 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164302 0.0144632 156 72 -1 -1 -1 -1 - fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 5.19 vpr 63.29 MiB -1 -1 0.27 18404 1 0.03 -1 -1 30280 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 31 32 409 331 1 264 96 17 17 289 -1 unnamed_device 24.2 MiB 2.08 1431 11703 3152 7474 1077 63.3 MiB 0.14 0.00 4.84775 -156.008 -4.84775 4.84775 0.33 0.000772559 0.000718063 0.0435525 0.0403604 -1 -1 -1 -1 26 3450 37 6.89349e+06 465097 503264. 1741.40 0.87 0.155585 0.13616 24322 120374 -1 3021 21 2266 3099 239025 58139 4.43869 4.43869 -159.514 -4.43869 0 0 618332. 2139.56 0.03 0.09 0.10 -1 -1 0.03 0.0309079 0.0268354 175 90 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 4.14 vpr 64.34 MiB -1 -1 0.19 18372 14 0.23 -1 -1 32420 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 277 309 1 203 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3169 1468 11328 2379 7541 1408 64.3 MiB 0.07 0.00 10.3228 8.34809 -172.958 -8.34809 8.34809 0.24 0.000458019 0.000420977 0.0267514 0.024586 -1 -1 -1 -1 26 4102 40 6.55708e+06 482200 477104. 1650.88 2.34 0.198273 0.175014 21022 109990 -1 3183 21 1415 4612 232092 56261 7.86483 7.86483 -171.918 -7.86483 0 0 585099. 2024.56 0.05 0.08 0.06 -1 -1 0.05 0.0346821 0.0278328 194 183 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 2.82 vpr 64.72 MiB -1 -1 0.19 18608 14 0.26 -1 -1 32020 -1 -1 39 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66272 30 32 272 304 1 192 101 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2855 1327 6211 1127 4807 277 64.7 MiB 0.04 0.00 10.4229 7.81577 -157.932 -7.81577 7.81577 0.25 0.00044353 0.000407199 0.0145115 0.013339 -1 -1 -1 -1 26 3276 21 6.55708e+06 470145 477104. 1650.88 1.03 0.138339 0.121807 21022 109990 -1 2977 18 1223 3838 191983 48311 7.09678 7.09678 -155.225 -7.09678 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0222913 0.0201627 191 184 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 2.79 vpr 64.70 MiB -1 -1 0.14 17972 11 0.20 -1 -1 32500 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 280 312 1 187 103 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2827 1361 6128 1131 4405 592 64.7 MiB 0.04 0.00 8.30478 6.65392 -136.28 -6.65392 6.65392 0.23 0.000444217 0.000407628 0.0153173 0.0140577 -1 -1 -1 -1 28 3532 22 6.55708e+06 470145 500653. 1732.36 1.13 0.141601 0.124216 21310 115450 -1 2893 19 1295 4984 238971 59050 5.81978 5.81978 -132.978 -5.81978 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.022413 0.0200969 193 186 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 2.40 vpr 64.21 MiB -1 -1 0.16 18368 12 0.29 -1 -1 32700 -1 -1 40 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 29 32 275 307 1 194 101 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2959 1244 8326 1689 5934 703 64.2 MiB 0.05 0.00 9.98698 7.42963 -136.806 -7.42963 7.42963 0.33 0.000442208 0.000402322 0.0186625 0.0171344 -1 -1 -1 -1 22 3463 27 6.55708e+06 482200 420624. 1455.45 0.62 0.111711 0.100638 20158 92377 -1 3149 20 1718 5783 304181 76974 6.67344 6.67344 -140.022 -6.67344 0 0 500653. 1732.36 0.02 0.08 0.05 -1 -1 0.02 0.0253416 0.0228426 200 190 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 2.59 vpr 64.82 MiB -1 -1 0.18 18364 13 0.24 -1 -1 31812 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 302 334 1 214 106 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3277 1472 9856 1982 7031 843 64.8 MiB 0.05 0.00 10.9395 7.98333 -168.064 -7.98333 7.98333 0.23 0.000470534 0.000431442 0.0218695 0.0200206 -1 -1 -1 -1 26 3770 18 6.55708e+06 506310 477104. 1650.88 0.93 0.134458 0.118969 21022 109990 -1 3230 16 1274 3900 187211 47077 7.22463 7.22463 -162.98 -7.22463 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.021449 0.0195803 217 208 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 2.56 vpr 64.45 MiB -1 -1 0.25 18364 13 0.23 -1 -1 32448 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 292 324 1 212 106 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2866 1500 7356 1329 5608 419 64.4 MiB 0.06 0.00 9.67796 7.98192 -159.937 -7.98192 7.98192 0.24 0.0011069 0.0010281 0.0237148 0.0219451 -1 -1 -1 -1 30 3231 22 6.55708e+06 506310 526063. 1820.29 0.67 0.135582 0.121368 21886 126133 -1 2914 15 1161 4203 188301 46205 6.76976 6.76976 -150.378 -6.76976 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0231856 0.0211083 204 198 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 2.26 vpr 64.33 MiB -1 -1 0.17 17984 12 0.18 -1 -1 32260 -1 -1 38 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 27 32 229 261 1 167 97 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2337 1007 8533 2013 5783 737 64.3 MiB 0.04 0.00 9.40566 7.49882 -132.896 -7.49882 7.49882 0.23 0.000357417 0.000327606 0.0166803 0.0152855 -1 -1 -1 -1 22 2846 33 6.55708e+06 458090 420624. 1455.45 0.73 0.0961015 0.0844727 20158 92377 -1 2495 21 936 2825 151732 38675 7.10844 7.10844 -133.129 -7.10844 0 0 500653. 1732.36 0.02 0.05 0.05 -1 -1 0.02 0.0221263 0.0200669 162 150 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 2.26 vpr 63.80 MiB -1 -1 0.15 17980 12 0.16 -1 -1 32388 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65328 31 32 229 261 1 172 99 17 17 289 -1 unnamed_device 24.0 MiB 0.09 2493 1182 11499 2779 7797 923 63.8 MiB 0.05 0.00 7.48917 6.1978 -123.822 -6.1978 6.1978 0.23 0.000357937 0.00032045 0.0200933 0.0182708 -1 -1 -1 -1 26 3022 23 6.55708e+06 433980 477104. 1650.88 0.68 0.0929068 0.0826701 21022 109990 -1 2558 15 983 3146 160300 39339 5.61152 5.61152 -124 -5.61152 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152523 0.0138522 153 138 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 2.12 vpr 64.02 MiB -1 -1 0.18 18368 12 0.15 -1 -1 32260 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 31 32 235 267 1 170 98 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2607 1194 6398 1155 4738 505 64.0 MiB 0.03 0.00 8.76355 7.13011 -140.761 -7.13011 7.13011 0.24 0.000359813 0.000329497 0.0130808 0.0120095 -1 -1 -1 -1 26 2823 45 6.55708e+06 421925 477104. 1650.88 0.53 0.0813171 0.0719305 21022 109990 -1 2481 18 878 2720 142628 35086 6.35464 6.35464 -138.252 -6.35464 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.026961 0.024312 155 144 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_010.v common 2.73 vpr 64.53 MiB -1 -1 0.17 17972 13 0.23 -1 -1 32340 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 250 282 1 190 99 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2595 1285 6255 1073 4701 481 64.5 MiB 0.04 0.00 9.61062 7.56812 -165.213 -7.56812 7.56812 0.26 0.000386406 0.000353879 0.0145749 0.0134141 -1 -1 -1 -1 26 3258 24 6.55708e+06 421925 477104. 1650.88 1.03 0.151248 0.131586 21022 109990 -1 2743 21 1276 3790 183407 45756 6.89358 6.89358 -162.183 -6.89358 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0293242 0.0262182 166 156 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 2.49 vpr 64.09 MiB -1 -1 0.15 17980 12 0.16 -1 -1 32496 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 30 32 216 248 1 160 95 17 17 289 -1 unnamed_device 24.2 MiB 0.07 2363 1089 9383 1996 6576 811 64.1 MiB 0.04 0.00 8.78898 6.99514 -141.661 -6.99514 6.99514 0.25 0.00034128 0.000311808 0.0166983 0.0152604 -1 -1 -1 -1 28 2591 19 6.55708e+06 397815 500653. 1732.36 0.90 0.101924 0.0897543 21310 115450 -1 2231 16 835 2644 129323 32207 6.02864 6.02864 -134.773 -6.02864 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0171828 0.0155916 140 128 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 2.27 vpr 63.82 MiB -1 -1 0.14 17980 12 0.13 -1 -1 32248 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65348 32 32 236 268 1 171 97 17 17 289 -1 unnamed_device 24.0 MiB 0.07 2486 1250 7201 1363 5333 505 63.8 MiB 0.04 0.00 7.92826 6.93051 -150.969 -6.93051 6.93051 0.24 0.000362163 0.000323716 0.0139954 0.0127661 -1 -1 -1 -1 22 3133 21 6.55708e+06 397815 420624. 1455.45 0.80 0.105874 0.0929435 20158 92377 -1 2873 18 1055 3139 174475 42904 6.04852 6.04852 -151.719 -6.04852 0 0 500653. 1732.36 0.02 0.05 0.05 -1 -1 0.02 0.0177045 0.0160033 148 142 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_013.v common 2.11 vpr 64.77 MiB -1 -1 0.17 17904 13 0.22 -1 -1 32380 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 283 315 1 206 102 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2918 1396 8432 1576 6264 592 64.8 MiB 0.05 0.00 10.5047 7.90793 -163.623 -7.90793 7.90793 0.24 0.000463543 0.000426506 0.0209377 0.0192839 -1 -1 -1 -1 26 3470 21 6.55708e+06 458090 477104. 1650.88 0.49 0.0961944 0.0860277 21022 109990 -1 2987 16 1182 3603 185734 44882 6.92916 6.92916 -156.223 -6.92916 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0219292 0.0199363 197 189 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_014.v common 2.97 vpr 64.87 MiB -1 -1 0.17 18364 14 0.28 -1 -1 32428 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 303 335 1 216 103 17 17 289 -1 unnamed_device 25.2 MiB 0.11 3288 1474 6128 1054 4658 416 64.9 MiB 0.04 0.00 12.0727 8.81606 -181.273 -8.81606 8.81606 0.24 0.000504434 0.000449507 0.0154959 0.0142237 -1 -1 -1 -1 28 3839 27 6.55708e+06 470145 500653. 1732.36 1.22 0.163212 0.143995 21310 115450 -1 3197 18 1484 4767 234549 57799 7.60916 7.60916 -170.785 -7.60916 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0274708 0.0249197 214 209 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_015.v common 2.39 vpr 64.35 MiB -1 -1 0.14 17980 11 0.15 -1 -1 32280 -1 -1 39 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 29 32 225 257 1 164 100 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2302 1071 8684 1857 6075 752 64.3 MiB 0.04 0.00 8.12271 6.84055 -135.697 -6.84055 6.84055 0.23 0.000349214 0.000319509 0.0150334 0.013758 -1 -1 -1 -1 30 2348 30 6.55708e+06 470145 526063. 1820.29 0.91 0.137917 0.121515 21886 126133 -1 2011 13 693 2200 90643 23004 5.99144 5.99144 -125.931 -5.99144 0 0 666494. 2306.21 0.02 0.03 0.07 -1 -1 0.02 0.013831 0.012644 154 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_016.v common 3.46 vpr 64.83 MiB -1 -1 0.25 18748 12 0.25 -1 -1 32680 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 32 32 301 333 1 214 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3731 1580 10108 2123 7160 825 64.8 MiB 0.06 0.00 10.4215 7.69506 -165.69 -7.69506 7.69506 0.23 0.00048124 0.000442319 0.023123 0.0211923 -1 -1 -1 -1 28 4238 23 6.55708e+06 482200 500653. 1732.36 1.51 0.193497 0.172492 21310 115450 -1 3402 20 1337 4577 232126 56137 6.59044 6.59044 -157.099 -6.59044 0 0 612192. 2118.31 0.04 0.11 0.11 -1 -1 0.04 0.0451348 0.0409865 211 207 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_017.v common 2.31 vpr 64.70 MiB -1 -1 0.17 18368 14 0.22 -1 -1 32384 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 277 309 1 206 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3035 1443 6528 1220 4877 431 64.7 MiB 0.04 0.00 10.0543 7.86974 -166.415 -7.86974 7.86974 0.24 0.000429846 0.000392749 0.0174185 0.0160311 -1 -1 -1 -1 30 3432 26 6.55708e+06 458090 526063. 1820.29 0.64 0.10171 0.0899918 21886 126133 -1 2807 16 1180 4013 184856 44602 6.94704 6.94704 -156.04 -6.94704 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0206573 0.018835 193 183 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_018.v common 2.73 vpr 64.29 MiB -1 -1 0.20 18360 12 0.14 -1 -1 32224 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 227 259 1 155 96 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2590 1167 9951 2256 6821 874 64.3 MiB 0.07 0.00 9.34738 6.87555 -150.994 -6.87555 6.87555 0.24 0.000849311 0.000790944 0.0342931 0.0321893 -1 -1 -1 -1 26 2790 20 6.55708e+06 385760 477104. 1650.88 1.03 0.160074 0.142578 21022 109990 -1 2381 19 920 3114 159590 38534 6.18098 6.18098 -145.131 -6.18098 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0283522 0.025653 145 133 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_019.v common 1.73 vpr 63.68 MiB -1 -1 0.13 17984 10 0.08 -1 -1 31720 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65204 30 32 175 207 1 133 87 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1817 875 6615 1509 4517 589 63.7 MiB 0.03 0.00 6.36477 5.54003 -124.848 -5.54003 5.54003 0.24 0.000273145 0.000250213 0.0117929 0.0108481 -1 -1 -1 -1 26 1892 14 6.55708e+06 301375 477104. 1650.88 0.37 0.0455235 0.0402896 21022 109990 -1 1707 15 580 1538 75173 19570 4.68146 4.68146 -118.937 -4.68146 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.011085 0.00998996 100 87 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_020.v common 2.61 vpr 64.34 MiB -1 -1 0.26 18368 13 0.16 -1 -1 32248 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 31 32 231 263 1 172 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2551 1219 5133 882 3910 341 64.3 MiB 0.03 0.00 9.56848 7.51354 -158.515 -7.51354 7.51354 0.25 0.00037534 0.000342742 0.011147 0.0102689 -1 -1 -1 -1 26 2914 16 6.55708e+06 397815 477104. 1650.88 0.93 0.10781 0.0949072 21022 109990 -1 2616 16 912 2770 141635 35169 6.50744 6.50744 -149.665 -6.50744 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0166308 0.0151505 151 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_021.v common 3.59 vpr 64.70 MiB -1 -1 0.25 18364 13 0.24 -1 -1 33084 -1 -1 45 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 32 32 304 336 1 215 109 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3300 1520 9729 2088 6855 786 64.7 MiB 0.05 0.00 11.3205 8.3687 -170.208 -8.3687 8.3687 0.36 0.000468055 0.00042951 0.021122 0.0193255 -1 -1 -1 -1 26 4144 38 6.55708e+06 542475 477104. 1650.88 1.62 0.168739 0.149499 21022 109990 -1 3324 16 1386 4558 227561 55685 7.37076 7.37076 -163.235 -7.37076 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0248103 0.0223431 222 210 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_022.v common 3.26 vpr 65.14 MiB -1 -1 0.17 18364 13 0.32 -1 -1 32320 -1 -1 46 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66700 32 32 288 320 1 212 110 17 17 289 -1 unnamed_device 25.2 MiB 0.08 3011 1549 9841 1986 7037 818 65.1 MiB 0.06 0.00 9.94628 8.09001 -170.835 -8.09001 8.09001 0.25 0.000783059 0.000709901 0.0240612 0.0222191 -1 -1 -1 -1 34 3785 46 6.55708e+06 554530 585099. 2024.56 1.41 0.194299 0.171381 22462 138074 -1 3315 18 1268 4764 252706 59815 6.97197 6.97197 -158.757 -6.97197 0 0 742403. 2568.87 0.03 0.07 0.08 -1 -1 0.03 0.0266895 0.0242846 209 194 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_023.v common 1.70 vpr 63.59 MiB -1 -1 0.12 17600 9 0.08 -1 -1 32016 -1 -1 30 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65120 26 32 152 184 1 110 88 17 17 289 -1 unnamed_device 24.0 MiB 0.03 1535 711 7888 1985 4791 1112 63.6 MiB 0.03 0.00 5.98374 4.84 -87.8657 -4.84 4.84 0.23 0.000243053 0.000222729 0.0112522 0.0102964 -1 -1 -1 -1 26 1557 15 6.55708e+06 361650 477104. 1650.88 0.33 0.0419996 0.0368842 21022 109990 -1 1389 17 478 1412 69242 17472 4.2322 4.2322 -86.9531 -4.2322 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0156673 0.0139829 95 76 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_024.v common 2.28 vpr 64.75 MiB -1 -1 0.16 18220 13 0.25 -1 -1 32356 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 287 319 1 209 106 17 17 289 -1 unnamed_device 25.0 MiB 0.07 3188 1475 7356 1240 5841 275 64.8 MiB 0.04 0.00 10.9129 8.3667 -168.117 -8.3667 8.3667 0.24 0.000456208 0.00041319 0.0164859 0.015092 -1 -1 -1 -1 26 3835 20 6.55708e+06 506310 477104. 1650.88 0.65 0.0893791 0.0794058 21022 109990 -1 3121 17 1250 3890 189718 46969 7.40996 7.40996 -160.049 -7.40996 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0207467 0.0188691 204 193 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_025.v common 1.68 vpr 63.57 MiB -1 -1 0.13 17600 8 0.07 -1 -1 32016 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65092 32 32 154 186 1 117 91 17 17 289 -1 unnamed_device 24.0 MiB 0.04 1504 839 6823 1506 4714 603 63.6 MiB 0.03 0.00 4.86674 4.14794 -97.1492 -4.14794 4.14794 0.23 0.000245642 0.000219086 0.00957985 0.00875471 -1 -1 -1 -1 26 1708 16 6.55708e+06 325485 477104. 1650.88 0.35 0.040037 0.0351673 21022 109990 -1 1465 13 445 1124 51583 13618 3.90514 3.90514 -96.8068 -3.90514 0 0 585099. 2024.56 0.02 0.02 0.08 -1 -1 0.02 0.00901111 0.00814501 83 60 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_026.v common 2.70 vpr 64.62 MiB -1 -1 0.19 17980 15 0.21 -1 -1 32384 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 32 32 254 286 1 184 108 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2794 1289 8846 1673 6391 782 64.6 MiB 0.04 0.00 11.4269 8.91249 -179.898 -8.91249 8.91249 0.24 0.000411792 0.000376479 0.0166773 0.0152536 -1 -1 -1 -1 28 3141 22 6.55708e+06 530420 500653. 1732.36 1.05 0.133835 0.117718 21310 115450 -1 2703 19 1085 3420 169095 41588 7.75229 7.75229 -168.555 -7.75229 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0202997 0.0183246 178 160 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_027.v common 3.32 vpr 64.26 MiB -1 -1 0.28 18368 13 0.20 -1 -1 32396 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 32 32 260 292 1 185 101 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2553 1218 6446 1181 4503 762 64.3 MiB 0.04 0.00 8.41804 7.47895 -148.299 -7.47895 7.47895 0.35 0.000420455 0.000384763 0.0146573 0.0134158 -1 -1 -1 -1 28 3650 32 6.55708e+06 446035 500653. 1732.36 1.30 0.141603 0.124407 21310 115450 -1 2721 15 1115 3669 183849 47689 6.42904 6.42904 -144.643 -6.42904 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0184911 0.0168997 177 166 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_028.v common 2.89 vpr 64.74 MiB -1 -1 0.17 18368 13 0.24 -1 -1 32460 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 279 311 1 203 102 17 17 289 -1 unnamed_device 24.8 MiB 0.11 2785 1427 7242 1418 5129 695 64.7 MiB 0.07 0.00 9.58507 7.90558 -164.249 -7.90558 7.90558 0.44 0.000817344 0.000732132 0.0296013 0.0270257 -1 -1 -1 -1 28 3858 46 6.55708e+06 458090 500653. 1732.36 0.87 0.129441 0.116272 21310 115450 -1 3094 16 1193 4031 204357 49925 6.90524 6.90524 -156.112 -6.90524 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0215907 0.0197086 194 185 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_029.v common 2.58 vpr 63.68 MiB -1 -1 0.14 17984 12 0.15 -1 -1 32200 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65212 32 32 238 270 1 175 98 17 17 289 -1 unnamed_device 24.1 MiB 0.07 2532 1229 6623 1196 5108 319 63.7 MiB 0.05 0.00 8.83794 6.95354 -149.945 -6.95354 6.95354 0.34 0.000362825 0.000331699 0.0207453 0.0191131 -1 -1 -1 -1 26 3231 30 6.55708e+06 409870 477104. 1650.88 0.76 0.0914983 0.0816512 21022 109990 -1 2625 20 1044 3327 165434 41832 6.25938 6.25938 -147.249 -6.25938 0 0 585099. 2024.56 0.03 0.08 0.10 -1 -1 0.03 0.0311287 0.0280935 151 144 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_030.v common 2.42 vpr 64.23 MiB -1 -1 0.14 17980 11 0.18 -1 -1 32228 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 30 32 213 245 1 156 94 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2070 1033 7549 1505 5428 616 64.2 MiB 0.04 0.00 8.27041 6.08486 -132.558 -6.08486 6.08486 0.24 0.00033254 0.000298034 0.0137224 0.0125369 -1 -1 -1 -1 26 2273 36 6.55708e+06 385760 477104. 1650.88 0.75 0.10972 0.0956295 21022 109990 -1 2055 14 763 2181 98833 26461 5.43986 5.43986 -127.04 -5.43986 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0168096 0.0153762 136 125 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_031.v common 2.06 vpr 64.36 MiB -1 -1 0.18 17820 11 0.15 -1 -1 32252 -1 -1 38 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 28 32 227 259 1 163 98 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2167 1077 9098 1974 6271 853 64.4 MiB 0.05 0.00 7.98015 6.78919 -130.953 -6.78919 6.78919 0.25 0.000476822 0.000447209 0.0226207 0.0209058 -1 -1 -1 -1 26 2605 24 6.55708e+06 458090 477104. 1650.88 0.46 0.0935539 0.083392 21022 109990 -1 2357 15 882 2746 133141 33518 6.11266 6.11266 -125.603 -6.11266 0 0 585099. 2024.56 0.03 0.05 0.06 -1 -1 0.03 0.0199283 0.0181338 155 145 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_032.v common 2.69 vpr 64.65 MiB -1 -1 0.19 17980 12 0.19 -1 -1 32280 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 32 32 274 306 1 199 103 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3018 1411 6128 1033 4730 365 64.7 MiB 0.04 0.00 9.91223 7.35615 -165.077 -7.35615 7.35615 0.24 0.000661124 0.000624461 0.0141509 0.0130367 -1 -1 -1 -1 28 3428 19 6.55708e+06 470145 500653. 1732.36 1.00 0.123875 0.108623 21310 115450 -1 2862 17 1149 3414 164768 41668 6.35004 6.35004 -156.285 -6.35004 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0208 0.0188528 188 180 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_033.v common 1.97 vpr 64.18 MiB -1 -1 0.14 17976 12 0.14 -1 -1 32240 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 31 32 237 269 1 165 98 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2339 1152 7973 1666 5519 788 64.2 MiB 0.04 0.00 8.83795 7.15214 -144.041 -7.15214 7.15214 0.24 0.000360413 0.000326731 0.0152974 0.0139203 -1 -1 -1 -1 26 2785 21 6.55708e+06 421925 477104. 1650.88 0.42 0.0710706 0.0628035 21022 109990 -1 2478 19 1052 3111 153968 38476 6.22984 6.22984 -139.914 -6.22984 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0257539 0.0230039 161 146 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_034.v common 1.80 vpr 64.32 MiB -1 -1 0.18 17984 10 0.12 -1 -1 32220 -1 -1 33 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 220 252 1 154 94 17 17 289 -1 unnamed_device 24.8 MiB 0.05 2111 1030 5206 950 3856 400 64.3 MiB 0.03 0.00 7.90072 6.31249 -127.587 -6.31249 6.31249 0.23 0.000341905 0.000312898 0.0105515 0.00968785 -1 -1 -1 -1 26 2457 16 6.55708e+06 397815 477104. 1650.88 0.30 0.0550495 0.0487275 21022 109990 -1 2196 16 763 2669 127482 31451 5.50298 5.50298 -123.617 -5.50298 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.015236 0.0138402 146 135 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_035.v common 2.56 vpr 64.93 MiB -1 -1 0.18 18748 13 0.35 -1 -1 32504 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 32 32 315 347 1 220 104 17 17 289 -1 unnamed_device 25.5 MiB 0.09 3359 1629 9132 2182 5924 1026 64.9 MiB 0.05 0.00 10.2396 8.33236 -170.529 -8.33236 8.33236 0.23 0.000496726 0.000454774 0.0221698 0.0202728 -1 -1 -1 -1 26 4005 19 6.55708e+06 482200 477104. 1650.88 0.70 0.0969603 0.0867237 21022 109990 -1 3407 16 1525 5269 261204 63091 6.78964 6.78964 -154.084 -6.78964 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0222822 0.0202409 231 221 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_036.v common 2.68 vpr 64.77 MiB -1 -1 0.17 18752 14 0.34 -1 -1 32288 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 282 314 1 219 107 17 17 289 -1 unnamed_device 24.8 MiB 0.13 3309 1501 7444 1465 5350 629 64.8 MiB 0.04 0.00 9.01512 7.882 -167.76 -7.882 7.882 0.23 0.000457104 0.000413096 0.0160806 0.0147011 -1 -1 -1 -1 30 3451 21 6.55708e+06 518365 526063. 1820.29 0.63 0.114441 0.102052 21886 126133 -1 3012 19 1353 4471 189705 48631 6.82684 6.82684 -156.723 -6.82684 0 0 666494. 2306.21 0.03 0.07 0.08 -1 -1 0.03 0.0272279 0.0246689 199 188 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_037.v common 2.55 vpr 64.40 MiB -1 -1 0.15 17984 12 0.13 -1 -1 32280 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 31 32 241 273 1 176 97 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2615 1203 10087 2397 6601 1089 64.4 MiB 0.07 0.00 10.1954 7.8818 -157.766 -7.8818 7.8818 0.25 0.000373792 0.000342257 0.0315957 0.0290482 -1 -1 -1 -1 26 2814 23 6.55708e+06 409870 477104. 1650.88 0.99 0.145263 0.128418 21022 109990 -1 2492 19 1059 3340 167020 41325 6.94904 6.94904 -150.445 -6.94904 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0178526 0.0160758 161 150 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_038.v common 3.38 vpr 64.19 MiB -1 -1 0.18 18604 12 0.24 -1 -1 32444 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65732 31 32 307 339 1 218 105 17 17 289 -1 unnamed_device 25.2 MiB 0.12 3531 1406 11961 2747 8126 1088 64.2 MiB 0.07 0.00 9.67644 7.34358 -149.686 -7.34358 7.34358 0.23 0.000477874 0.000430677 0.0279143 0.0255112 -1 -1 -1 -1 26 4060 37 6.55708e+06 506310 477104. 1650.88 1.57 0.230868 0.204995 21022 109990 -1 3110 21 1514 5290 250090 63272 6.71064 6.71064 -148.302 -6.71064 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.031789 0.0285672 222 216 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_039.v common 3.01 vpr 64.46 MiB -1 -1 0.19 18748 14 0.30 -1 -1 33004 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 293 325 1 209 103 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3249 1483 8056 1615 5882 559 64.5 MiB 0.10 0.00 11.3501 8.401 -168.472 -8.401 8.401 0.32 0.00120517 0.0011155 0.0430016 0.0397087 -1 -1 -1 -1 24 4160 43 6.55708e+06 482200 448715. 1552.65 1.10 0.163162 0.145601 20734 103517 -1 3341 29 1546 4981 334492 116243 7.72936 7.72936 -165.676 -7.72936 0 0 554710. 1919.41 0.02 0.12 0.06 -1 -1 0.02 0.0390517 0.0352076 211 202 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_040.v common 2.75 vpr 64.60 MiB -1 -1 0.19 18752 13 0.23 -1 -1 32248 -1 -1 49 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 31 32 276 308 1 210 112 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3496 1506 9527 2110 6648 769 64.6 MiB 0.05 0.00 10.2681 8.49401 -167.474 -8.49401 8.49401 0.24 0.000435905 0.000399578 0.0187398 0.0171331 -1 -1 -1 -1 26 4222 41 6.55708e+06 590695 477104. 1650.88 1.06 0.116426 0.103875 21022 109990 -1 3390 31 1362 4459 292331 95208 7.1573 7.1573 -156.188 -7.1573 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.0302454 0.0269603 204 185 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_041.v common 4.13 vpr 64.66 MiB -1 -1 0.18 18368 13 0.33 -1 -1 32428 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 31 32 269 301 1 187 99 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2993 1382 7623 1737 5150 736 64.7 MiB 0.05 0.00 9.77611 7.29977 -148.117 -7.29977 7.29977 0.23 0.000649272 0.000586185 0.0179255 0.0164024 -1 -1 -1 -1 26 3776 30 6.55708e+06 433980 477104. 1650.88 2.36 0.170021 0.150298 21022 109990 -1 2992 18 1097 3889 201560 47848 6.31084 6.31084 -138.606 -6.31084 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0209992 0.0190088 186 178 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_042.v common 2.52 vpr 64.57 MiB -1 -1 0.16 17980 12 0.16 -1 -1 32392 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 264 296 1 182 100 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2787 1178 16572 4143 9707 2722 64.6 MiB 0.08 0.00 8.67103 7.20861 -147.87 -7.20861 7.20861 0.24 0.000396717 0.000362317 0.031655 0.0287685 -1 -1 -1 -1 28 2903 30 6.55708e+06 433980 500653. 1732.36 0.92 0.146414 0.129198 21310 115450 -1 2418 14 944 2858 141962 35987 6.33838 6.33838 -138.315 -6.33838 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0198651 0.0180623 180 170 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_043.v common 3.48 vpr 65.00 MiB -1 -1 0.30 19516 14 0.36 -1 -1 32460 -1 -1 46 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 32 32 324 356 1 237 110 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3588 1767 7474 1429 5523 522 65.0 MiB 0.05 0.00 10.0303 8.51709 -182.069 -8.51709 8.51709 0.23 0.000502932 0.000460485 0.017751 0.0163008 -1 -1 -1 -1 32 4223 21 6.55708e+06 554530 554710. 1919.41 1.49 0.228883 0.201565 22174 131602 -1 3712 19 1425 5225 247788 61833 7.3565 7.3565 -172.567 -7.3565 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0292167 0.0264599 241 230 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_044.v common 1.96 vpr 63.96 MiB -1 -1 0.14 17984 11 0.17 -1 -1 31924 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65500 31 32 249 281 1 175 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2703 1245 9951 2354 6419 1178 64.0 MiB 0.05 0.00 8.92495 6.69552 -142.327 -6.69552 6.69552 0.23 0.000400985 0.000367433 0.020751 0.0189973 -1 -1 -1 -1 26 3314 26 6.55708e+06 397815 477104. 1650.88 0.45 0.0794923 0.0704457 21022 109990 -1 2774 20 1213 4204 218942 54057 5.89112 5.89112 -137.993 -5.89112 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0204148 0.0184373 169 158 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_045.v common 2.79 vpr 64.76 MiB -1 -1 0.17 18368 13 0.24 -1 -1 32256 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 284 316 1 195 106 17 17 289 -1 unnamed_device 24.8 MiB 0.09 2880 1407 6106 991 4788 327 64.8 MiB 0.04 0.00 10.1669 8.04395 -157.61 -8.04395 8.04395 0.23 0.000456389 0.000417669 0.0140646 0.0128906 -1 -1 -1 -1 26 3416 21 6.55708e+06 518365 477104. 1650.88 1.13 0.14093 0.124106 21022 109990 -1 2935 19 1052 3846 213355 60751 7.1573 7.1573 -151.712 -7.1573 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0259928 0.0232535 202 193 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_046.v common 4.22 vpr 64.81 MiB -1 -1 0.16 18364 12 0.23 -1 -1 32416 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 32 32 303 335 1 213 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3637 1510 9620 2142 6549 929 64.8 MiB 0.06 0.00 9.78237 6.97332 -152.142 -6.97332 6.97332 0.23 0.000502106 0.00042931 0.0261794 0.0239064 -1 -1 -1 -1 26 4325 34 6.55708e+06 482200 477104. 1650.88 2.53 0.197744 0.174299 21022 109990 -1 3559 22 2010 7594 396246 94358 6.30318 6.30318 -151.607 -6.30318 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.029183 0.0262317 216 209 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_047.v common 2.16 vpr 64.32 MiB -1 -1 0.15 18364 13 0.24 -1 -1 32524 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 272 304 1 187 98 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2741 1323 5723 957 4337 429 64.3 MiB 0.04 0.00 10.5096 7.47895 -154.869 -7.47895 7.47895 0.24 0.000437137 0.000400272 0.0143062 0.0131723 -1 -1 -1 -1 26 3535 21 6.55708e+06 409870 477104. 1650.88 0.54 0.0847412 0.0755315 21022 109990 -1 2816 18 1335 4235 204307 50601 6.70864 6.70864 -152.349 -6.70864 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.0206862 0.0187005 188 178 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_048.v common 2.55 vpr 64.30 MiB -1 -1 0.16 18368 13 0.19 -1 -1 32404 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 32 32 271 303 1 198 105 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2854 1297 7762 1580 5576 606 64.3 MiB 0.05 0.00 9.09457 7.36601 -155.837 -7.36601 7.36601 0.23 0.000415008 0.000379214 0.0185983 0.0171236 -1 -1 -1 -1 26 3146 23 6.55708e+06 494255 477104. 1650.88 1.01 0.139015 0.12237 21022 109990 -1 2730 15 1086 3278 165110 40936 6.44432 6.44432 -147.717 -6.44432 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184486 0.0168059 189 177 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_049.v common 3.65 vpr 64.80 MiB -1 -1 0.25 18368 12 0.22 -1 -1 32044 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66352 32 32 288 320 1 205 102 17 17 289 -1 unnamed_device 25.0 MiB 0.09 3079 1440 8670 1767 6237 666 64.8 MiB 0.05 0.00 8.89602 7.32135 -155.214 -7.32135 7.32135 0.23 0.000445433 0.000406962 0.0195291 0.0179138 -1 -1 -1 -1 26 3667 27 6.55708e+06 458090 477104. 1650.88 1.92 0.217527 0.191661 21022 109990 -1 3235 22 1404 5425 270682 64761 6.53898 6.53898 -150.672 -6.53898 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.024792 0.0223819 201 194 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_050.v common 3.79 vpr 64.84 MiB -1 -1 0.25 18752 13 0.26 -1 -1 33056 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66400 32 32 306 338 1 222 108 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3151 1541 9617 2019 6835 763 64.8 MiB 0.06 0.00 10.5209 8.10463 -168.591 -8.10463 8.10463 0.23 0.000483588 0.000442669 0.0214407 0.0196021 -1 -1 -1 -1 26 4372 38 6.55708e+06 530420 477104. 1650.88 1.97 0.193338 0.171644 21022 109990 -1 3411 15 1394 4439 211034 53368 7.2801 7.2801 -161.773 -7.2801 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0212496 0.019415 223 212 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_051.v common 2.37 vpr 64.64 MiB -1 -1 0.15 18368 14 0.24 -1 -1 32696 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 262 294 1 188 100 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2763 1363 11700 2683 7233 1784 64.6 MiB 0.06 0.00 11.1513 8.70517 -163.209 -8.70517 8.70517 0.24 0.000445018 0.000409166 0.0237738 0.0217999 -1 -1 -1 -1 26 3751 36 6.55708e+06 433980 477104. 1650.88 0.74 0.097964 0.0871314 21022 109990 -1 2963 18 1219 3929 208524 50182 7.98142 7.98142 -159.654 -7.98142 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0219043 0.0197382 181 168 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_052.v common 3.29 vpr 64.70 MiB -1 -1 0.18 18364 13 0.23 -1 -1 32404 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 32 32 291 323 1 211 107 17 17 289 -1 unnamed_device 24.8 MiB 0.10 3299 1433 10480 2285 7646 549 64.7 MiB 0.08 0.00 11.3728 8.2812 -162.484 -8.2812 8.2812 0.23 0.000456943 0.000419163 0.0319448 0.0295537 -1 -1 -1 -1 26 4249 38 6.55708e+06 518365 477104. 1650.88 1.59 0.201052 0.17736 21022 109990 -1 3257 22 1390 4748 258559 69429 7.1579 7.1579 -156.58 -7.1579 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0241806 0.0217837 211 197 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_053.v common 3.45 vpr 64.82 MiB -1 -1 0.25 18752 13 0.24 -1 -1 32152 -1 -1 44 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 302 334 1 217 107 17 17 289 -1 unnamed_device 24.8 MiB 0.06 3175 1433 9974 2144 6983 847 64.8 MiB 0.06 0.00 10.7693 8.14207 -165.881 -8.14207 8.14207 0.23 0.000463083 0.000424081 0.0213645 0.019549 -1 -1 -1 -1 26 3885 44 6.55708e+06 530420 477104. 1650.88 1.62 0.186609 0.164822 21022 109990 -1 3210 16 1307 4049 198045 49445 7.04936 7.04936 -156.762 -7.04936 0 0 585099. 2024.56 0.02 0.06 0.10 -1 -1 0.02 0.0220925 0.0201608 219 211 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_054.v common 3.00 vpr 64.88 MiB -1 -1 0.25 18748 12 0.28 -1 -1 32588 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66432 32 32 308 340 1 227 107 17 17 289 -1 unnamed_device 25.2 MiB 0.10 3553 1588 8456 1657 6340 459 64.9 MiB 0.05 0.00 10.5054 7.81338 -162.105 -7.81338 7.81338 0.23 0.000467261 0.0004282 0.0190897 0.0174553 -1 -1 -1 -1 30 3533 18 6.55708e+06 518365 526063. 1820.29 1.20 0.175664 0.154749 21886 126133 -1 2975 18 1181 4009 172026 42611 6.9633 6.9633 -152.154 -6.9633 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0281559 0.0255785 222 214 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_055.v common 2.30 vpr 63.96 MiB -1 -1 0.14 17984 11 0.11 -1 -1 32256 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65492 32 32 216 248 1 150 93 17 17 289 -1 unnamed_device 24.0 MiB 0.05 2172 1114 6813 1476 4649 688 64.0 MiB 0.03 0.00 7.67149 6.45472 -142.708 -6.45472 6.45472 0.23 0.000329671 0.000300919 0.0124913 0.0114155 -1 -1 -1 -1 26 2542 22 6.55708e+06 349595 477104. 1650.88 0.90 0.111032 0.0966003 21022 109990 -1 2319 13 784 2335 118482 29614 5.83766 5.83766 -144.011 -5.83766 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0132596 0.0121081 134 122 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_056.v common 2.35 vpr 64.57 MiB -1 -1 0.16 18224 13 0.19 -1 -1 31976 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 254 286 1 184 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2723 1225 8432 1783 5976 673 64.6 MiB 0.04 0.00 9.64721 7.76601 -160.89 -7.76601 7.76601 0.23 0.000398125 0.000364366 0.0168136 0.0153621 -1 -1 -1 -1 26 3260 44 6.55708e+06 458090 477104. 1650.88 0.72 0.0960043 0.0851036 21022 109990 -1 2668 30 1325 4578 317119 107312 7.1573 7.1573 -159.968 -7.1573 0 0 585099. 2024.56 0.02 0.10 0.06 -1 -1 0.02 0.0292682 0.0261828 175 160 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_057.v common 3.52 vpr 65.05 MiB -1 -1 0.19 19136 14 0.39 -1 -1 32632 -1 -1 47 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 338 370 1 243 111 17 17 289 -1 unnamed_device 25.8 MiB 0.09 3926 1767 7559 1351 5612 596 65.1 MiB 0.05 0.00 11.6381 8.88614 -176.77 -8.88614 8.88614 0.23 0.000538484 0.000482436 0.0186713 0.0170975 -1 -1 -1 -1 28 4757 39 6.55708e+06 566585 500653. 1732.36 1.59 0.216624 0.192218 21310 115450 -1 3846 18 1679 5489 285754 69543 7.90101 7.90101 -169.258 -7.90101 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0266501 0.0243171 256 244 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_058.v common 3.29 vpr 64.53 MiB -1 -1 0.19 18220 13 0.25 -1 -1 32408 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 271 303 1 202 100 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2981 1449 7060 1377 5094 589 64.5 MiB 0.04 0.00 9.8853 7.81987 -168.799 -7.81987 7.81987 0.23 0.000432617 0.000395853 0.0160406 0.0146835 -1 -1 -1 -1 26 3590 23 6.55708e+06 433980 477104. 1650.88 1.51 0.144757 0.127716 21022 109990 -1 3059 15 1235 3945 193279 47785 6.8803 6.8803 -158.318 -6.8803 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0195175 0.0177688 186 177 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_059.v common 2.17 vpr 64.32 MiB -1 -1 0.17 17980 11 0.15 -1 -1 32468 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 30 32 224 256 1 152 94 17 17 289 -1 unnamed_device 24.8 MiB 0.09 1968 1020 7762 1726 5530 506 64.3 MiB 0.05 0.00 8.50338 6.74949 -138.67 -6.74949 6.74949 0.26 0.000356161 0.00032542 0.0222888 0.0205686 -1 -1 -1 -1 24 2406 20 6.55708e+06 385760 448715. 1552.65 0.55 0.0898862 0.0798319 20734 103517 -1 2133 14 787 2459 127346 32295 5.93998 5.93998 -132.575 -5.93998 0 0 554710. 1919.41 0.02 0.04 0.06 -1 -1 0.02 0.0148732 0.0136023 150 136 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_060.v common 5.66 vpr 65.20 MiB -1 -1 0.19 19508 15 0.47 -1 -1 32024 -1 -1 49 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66760 32 32 351 383 1 261 113 17 17 289 -1 unnamed_device 25.6 MiB 0.09 3995 2010 11852 2629 8141 1082 65.2 MiB 0.07 0.00 12.8102 9.45181 -192.305 -9.45181 9.45181 0.23 0.000559457 0.000504907 0.027816 0.0253997 -1 -1 -1 -1 28 5547 42 6.55708e+06 590695 500653. 1732.36 3.63 0.240926 0.214838 21310 115450 -1 4448 19 2153 7534 412419 96794 8.64975 8.64975 -185.929 -8.64975 0 0 612192. 2118.31 0.02 0.09 0.06 -1 -1 0.02 0.0302484 0.0276287 261 257 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_061.v common 3.60 vpr 64.78 MiB -1 -1 0.29 18368 13 0.28 -1 -1 32244 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 297 329 1 206 104 17 17 289 -1 unnamed_device 25.2 MiB 0.08 3275 1492 10352 2588 6648 1116 64.8 MiB 0.06 0.00 10.6893 8.11669 -167.863 -8.11669 8.11669 0.24 0.000535712 0.000495888 0.0247164 0.0227451 -1 -1 -1 -1 28 4178 42 6.55708e+06 482200 500653. 1732.36 1.62 0.210555 0.186384 21310 115450 -1 3202 18 1377 4381 237630 56889 6.81096 6.81096 -157.796 -6.81096 0 0 612192. 2118.31 0.04 0.13 0.08 -1 -1 0.04 0.0513009 0.0464052 211 203 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_062.v common 1.74 vpr 64.33 MiB -1 -1 0.13 17980 11 0.11 -1 -1 32248 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 231 263 1 168 96 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2404 1200 5352 1082 3950 320 64.3 MiB 0.03 0.00 7.81172 6.30809 -138.848 -6.30809 6.30809 0.23 0.000345025 0.000315149 0.010973 0.0100535 -1 -1 -1 -1 26 2781 16 6.55708e+06 385760 477104. 1650.88 0.35 0.0549483 0.0486739 21022 109990 -1 2413 18 931 2920 146323 36299 5.79586 5.79586 -136.986 -5.79586 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0199369 0.0179319 149 137 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_063.v common 3.06 vpr 64.87 MiB -1 -1 0.18 18756 12 0.26 -1 -1 32492 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 305 337 1 209 106 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3192 1509 8106 1613 5842 651 64.9 MiB 0.06 0.00 10.8824 7.43184 -153.804 -7.43184 7.43184 0.23 0.000627827 0.000546897 0.025293 0.0233741 -1 -1 -1 -1 30 3226 28 6.55708e+06 506310 526063. 1820.29 1.36 0.221708 0.195832 21886 126133 -1 2895 17 1214 4355 186157 46002 6.47224 6.47224 -143.336 -6.47224 0 0 666494. 2306.21 0.02 0.05 0.07 -1 -1 0.02 0.0218846 0.0199037 224 211 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_064.v common 2.63 vpr 64.36 MiB -1 -1 0.16 17984 12 0.17 -1 -1 32132 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 243 275 1 185 101 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2741 1320 8326 1851 5875 600 64.4 MiB 0.04 0.00 8.98498 7.57401 -157.5 -7.57401 7.57401 0.23 0.000391939 0.000359402 0.0160215 0.0146932 -1 -1 -1 -1 28 3291 20 6.55708e+06 446035 500653. 1732.36 0.96 0.120985 0.106511 21310 115450 -1 2704 18 1002 3193 154404 38429 6.70098 6.70098 -151.983 -6.70098 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0183839 0.0166494 160 149 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_065.v common 2.00 vpr 64.36 MiB -1 -1 0.15 17976 12 0.16 -1 -1 32424 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 30 32 228 260 1 158 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2463 1057 6009 1165 4395 449 64.4 MiB 0.03 0.00 9.70233 7.10808 -144.903 -7.10808 7.10808 0.23 0.000361721 0.000331358 0.0122651 0.0112354 -1 -1 -1 -1 20 2487 24 6.55708e+06 409870 394039. 1363.46 0.49 0.061774 0.0548534 19870 87366 -1 2323 17 852 2864 148607 36739 6.46058 6.46058 -142.134 -6.46058 0 0 477104. 1650.88 0.02 0.04 0.05 -1 -1 0.02 0.0165964 0.0150485 151 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_066.v common 2.62 vpr 64.75 MiB -1 -1 0.18 18364 12 0.25 -1 -1 32836 -1 -1 41 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 29 32 275 307 1 195 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2776 1290 7956 1517 5875 564 64.8 MiB 0.04 0.00 9.75944 6.89912 -129.506 -6.89912 6.89912 0.23 0.000439187 0.000401806 0.0176508 0.016155 -1 -1 -1 -1 26 3296 19 6.55708e+06 494255 477104. 1650.88 0.94 0.140672 0.123405 21022 109990 -1 2817 17 1189 4151 205219 50431 6.27364 6.27364 -125.715 -6.27364 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0217945 0.0198656 198 190 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_067.v common 4.15 vpr 64.46 MiB -1 -1 0.20 18364 13 0.35 -1 -1 32304 -1 -1 50 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 330 362 1 232 114 17 17 289 -1 unnamed_device 25.2 MiB 0.13 3249 1646 11706 2331 8577 798 64.5 MiB 0.07 0.00 10.166 8.087 -174.968 -8.087 8.087 0.23 0.000504128 0.00046231 0.0252032 0.0230892 -1 -1 -1 -1 26 4440 49 6.55708e+06 602750 477104. 1650.88 2.09 0.265695 0.235973 21022 109990 -1 3658 31 2107 6976 387104 114321 7.6773 7.6773 -175.999 -7.6773 0 0 585099. 2024.56 0.02 0.16 0.06 -1 -1 0.02 0.0585253 0.0524828 247 236 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_068.v common 3.05 vpr 64.17 MiB -1 -1 0.20 18364 12 0.21 -1 -1 32352 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 290 322 1 203 104 17 17 289 -1 unnamed_device 24.4 MiB 0.10 3300 1279 10352 2652 6577 1123 64.2 MiB 0.07 0.00 10.7679 7.73832 -150.742 -7.73832 7.73832 0.25 0.000467737 0.000428655 0.0302749 0.0280738 -1 -1 -1 -1 28 3491 20 6.55708e+06 482200 500653. 1732.36 1.23 0.162438 0.144317 21310 115450 -1 2895 16 1315 4243 219437 55418 6.8405 6.8405 -146.978 -6.8405 0 0 612192. 2118.31 0.04 0.09 0.07 -1 -1 0.04 0.035537 0.0323181 206 196 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_069.v common 2.48 vpr 64.25 MiB -1 -1 0.14 17984 12 0.13 -1 -1 32928 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 214 246 1 156 95 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2480 1130 5927 1103 4408 416 64.2 MiB 0.03 0.00 9.31584 7.04661 -144.877 -7.04661 7.04661 0.24 0.000339655 0.000310041 0.0115631 0.010563 -1 -1 -1 -1 26 2534 18 6.55708e+06 373705 477104. 1650.88 1.07 0.122005 0.106406 21022 109990 -1 2279 18 854 2634 133675 33889 5.97718 5.97718 -136.774 -5.97718 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0161625 0.0146372 135 120 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_070.v common 2.62 vpr 64.46 MiB -1 -1 0.16 18368 12 0.19 -1 -1 31944 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 244 276 1 170 98 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2617 1274 6398 1159 4710 529 64.5 MiB 0.03 0.00 9.56447 7.57061 -150.375 -7.57061 7.57061 0.24 0.00038161 0.000349434 0.0132809 0.0121488 -1 -1 -1 -1 28 3024 18 6.55708e+06 421925 500653. 1732.36 1.06 0.135071 0.118552 21310 115450 -1 2560 16 918 3190 159899 38980 6.2813 6.2813 -142.114 -6.2813 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0199613 0.0181369 161 153 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_071.v common 3.01 vpr 64.17 MiB -1 -1 0.26 18368 11 0.17 -1 -1 32488 -1 -1 40 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 30 32 276 308 1 199 102 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2727 1365 7242 1318 5567 357 64.2 MiB 0.05 0.00 8.59664 6.98252 -137.845 -6.98252 6.98252 0.24 0.000452447 0.000411507 0.0193183 0.0178012 -1 -1 -1 -1 26 3630 40 6.55708e+06 482200 477104. 1650.88 1.29 0.156421 0.137889 21022 109990 -1 3067 18 1183 4172 215666 51876 6.07244 6.07244 -134.218 -6.07244 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0227691 0.0204083 194 188 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_072.v common 2.85 vpr 64.55 MiB -1 -1 0.17 17980 11 0.18 -1 -1 32268 -1 -1 36 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 28 32 253 285 1 177 96 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2506 1211 8199 1748 5508 943 64.6 MiB 0.05 0.00 8.69997 6.71295 -129.325 -6.71295 6.71295 0.23 0.00042684 0.000393932 0.0228206 0.0211229 -1 -1 -1 -1 30 2524 16 6.55708e+06 433980 526063. 1820.29 1.18 0.162297 0.142794 21886 126133 -1 2281 16 880 3154 140107 34317 5.85898 5.85898 -123.314 -5.85898 0 0 666494. 2306.21 0.04 0.08 0.08 -1 -1 0.04 0.0371708 0.0335976 176 171 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_073.v common 2.11 vpr 64.43 MiB -1 -1 0.16 18364 13 0.18 -1 -1 31916 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 30 32 235 267 1 166 98 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2275 1124 7748 1646 5543 559 64.4 MiB 0.06 0.00 10.228 7.79233 -143.293 -7.79233 7.79233 0.24 0.000882547 0.000817551 0.0271881 0.0254 -1 -1 -1 -1 26 2682 22 6.55708e+06 433980 477104. 1650.88 0.39 0.0872149 0.0781979 21022 109990 -1 2310 16 922 3336 150513 38472 6.8039 6.8039 -136.548 -6.8039 0 0 585099. 2024.56 0.04 0.06 0.09 -1 -1 0.04 0.0265682 0.0241882 157 147 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_074.v common 2.88 vpr 64.63 MiB -1 -1 0.18 18364 12 0.25 -1 -1 32276 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66180 32 32 264 296 1 187 100 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2846 1273 10540 2582 6897 1061 64.6 MiB 0.05 0.00 9.32034 7.41947 -161.03 -7.41947 7.41947 0.24 0.000416783 0.000381574 0.0215499 0.0196879 -1 -1 -1 -1 28 3178 43 6.55708e+06 433980 500653. 1732.36 1.13 0.150714 0.132237 21310 115450 -1 2752 18 1030 3249 171987 42405 6.2003 6.2003 -148.62 -6.2003 0 0 612192. 2118.31 0.02 0.05 0.08 -1 -1 0.02 0.019547 0.0176734 180 170 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_075.v common 2.19 vpr 64.74 MiB -1 -1 0.16 18000 13 0.26 -1 -1 32444 -1 -1 41 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 278 310 1 197 104 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2948 1285 6204 1121 4455 628 64.7 MiB 0.04 0.00 10.4607 8.33266 -159.321 -8.33266 8.33266 0.23 0.000450174 0.000413364 0.0161966 0.0149247 -1 -1 -1 -1 26 3400 25 6.55708e+06 494255 477104. 1650.88 0.51 0.0828088 0.0735628 21022 109990 -1 2719 17 1068 3376 157383 40304 7.28976 7.28976 -154.47 -7.28976 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0220486 0.0201017 196 187 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_076.v common 2.83 vpr 64.76 MiB -1 -1 0.18 18368 14 0.23 -1 -1 32384 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 290 322 1 201 102 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2948 1449 9860 2172 6855 833 64.8 MiB 0.05 0.00 10.9465 8.71544 -176.837 -8.71544 8.71544 0.34 0.000453693 0.000415773 0.0221562 0.02036 -1 -1 -1 -1 26 3548 21 6.55708e+06 458090 477104. 1650.88 1.07 0.149225 0.13138 21022 109990 -1 2951 16 1100 3513 167818 41879 7.92796 7.92796 -172.589 -7.92796 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0203231 0.0184758 203 196 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_077.v common 2.31 vpr 64.68 MiB -1 -1 0.18 18748 14 0.23 -1 -1 32424 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 269 301 1 187 100 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2291 1303 7756 1442 5636 678 64.7 MiB 0.04 0.00 10.3699 8.36955 -159.159 -8.36955 8.36955 0.23 0.000433687 0.000393612 0.0182587 0.0167452 -1 -1 -1 -1 26 3430 22 6.55708e+06 433980 477104. 1650.88 0.64 0.0842795 0.0747516 21022 109990 -1 2830 19 1184 4577 262704 74075 7.20936 7.20936 -150.018 -7.20936 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0285986 0.0255366 179 175 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_078.v common 3.05 vpr 64.75 MiB -1 -1 0.20 18752 13 0.30 -1 -1 32616 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 296 328 1 216 108 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3246 1544 7561 1452 5398 711 64.7 MiB 0.05 0.00 10.7252 8.52515 -170.673 -8.52515 8.52515 0.24 0.000599389 0.000558386 0.0190979 0.0176173 -1 -1 -1 -1 30 3404 28 6.55708e+06 530420 526063. 1820.29 1.22 0.159177 0.140846 21886 126133 -1 3028 17 1199 4291 182956 46284 7.56735 7.56735 -161.205 -7.56735 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0223292 0.0203908 212 202 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_079.v common 2.70 vpr 64.03 MiB -1 -1 0.16 17984 13 0.16 -1 -1 32448 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65568 30 32 234 266 1 169 96 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2265 1134 4695 742 3633 320 64.0 MiB 0.03 0.00 10.2529 7.95464 -161.944 -7.95464 7.95464 0.24 0.000503181 0.00047225 0.0126481 0.0117035 -1 -1 -1 -1 28 2792 17 6.55708e+06 409870 500653. 1732.36 1.03 0.115548 0.101979 21310 115450 -1 2338 16 791 2338 113501 28721 6.77538 6.77538 -150.108 -6.77538 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0215635 0.0196967 155 146 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_080.v common 3.66 vpr 64.75 MiB -1 -1 0.30 18748 13 0.40 -1 -1 32412 -1 -1 42 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66308 30 32 291 323 1 211 104 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2984 1412 9376 2164 6142 1070 64.8 MiB 0.05 0.00 10.8675 8.7665 -166.076 -8.7665 8.7665 0.25 0.00048301 0.000435282 0.0216956 0.0198322 -1 -1 -1 -1 28 4440 36 6.55708e+06 506310 500653. 1732.36 1.52 0.195156 0.172406 21310 115450 -1 3306 22 1808 6039 308441 75318 8.13116 8.13116 -164.886 -8.13116 0 0 612192. 2118.31 0.02 0.12 0.06 -1 -1 0.02 0.0480109 0.0432038 211 203 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_081.v common 3.33 vpr 64.71 MiB -1 -1 0.17 18364 14 0.36 -1 -1 32276 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 274 306 1 188 100 17 17 289 -1 unnamed_device 24.8 MiB 0.11 2874 1381 6828 1358 4978 492 64.7 MiB 0.04 0.00 10.16 8.0528 -168.058 -8.0528 8.0528 0.26 0.000433477 0.000396437 0.0159878 0.0146877 -1 -1 -1 -1 26 3440 29 6.55708e+06 433980 477104. 1650.88 1.31 0.163675 0.144893 21022 109990 -1 2924 17 1120 4094 202887 49196 7.29236 7.29236 -160.792 -7.29236 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.021869 0.0198747 188 180 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_082.v common 2.44 vpr 64.65 MiB -1 -1 0.17 18368 13 0.20 -1 -1 32416 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 31 32 266 298 1 188 103 17 17 289 -1 unnamed_device 25.2 MiB 0.05 2648 1278 6851 1303 5218 330 64.7 MiB 0.06 0.00 9.79664 7.73626 -147.024 -7.73626 7.73626 0.26 0.000753216 0.000687884 0.0256158 0.0234295 -1 -1 -1 -1 26 3475 22 6.55708e+06 482200 477104. 1650.88 0.78 0.106799 0.0961352 21022 109990 -1 2882 21 1188 3871 201792 49498 6.6419 6.6419 -139.849 -6.6419 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0230652 0.0209088 189 175 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_083.v common 2.84 vpr 64.66 MiB -1 -1 0.17 18368 13 0.19 -1 -1 32276 -1 -1 42 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 30 32 266 298 1 198 104 17 17 289 -1 unnamed_device 25.3 MiB 0.08 3212 1451 7180 1397 5391 392 64.7 MiB 0.04 0.00 9.98558 8.08209 -153.888 -8.08209 8.08209 0.24 0.00041428 0.000379794 0.0146925 0.0134878 -1 -1 -1 -1 30 3135 19 6.55708e+06 506310 526063. 1820.29 1.15 0.133595 0.117686 21886 126133 -1 2656 16 1001 3565 158345 38941 6.8803 6.8803 -143.947 -6.8803 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0190113 0.0173463 188 178 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_084.v common 3.35 vpr 64.14 MiB -1 -1 0.17 18748 14 0.32 -1 -1 32436 -1 -1 45 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 310 342 1 226 109 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3591 1582 8689 1758 6168 763 64.1 MiB 0.06 0.00 10.8164 8.74282 -175.793 -8.74282 8.74282 0.24 0.000619421 0.000577581 0.0244264 0.0226096 -1 -1 -1 -1 28 3859 21 6.55708e+06 542475 500653. 1732.36 1.59 0.224812 0.199302 21310 115450 -1 3320 22 1569 5205 250249 62085 7.80069 7.80069 -168.216 -7.80069 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0269125 0.0242969 225 216 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_085.v common 2.20 vpr 64.32 MiB -1 -1 0.18 18368 11 0.24 -1 -1 32232 -1 -1 44 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 262 294 1 199 105 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3052 1320 8997 1938 5901 1158 64.3 MiB 0.05 0.00 10.039 7.47594 -139.521 -7.47594 7.47594 0.25 0.000443441 0.000400928 0.0210946 0.019397 -1 -1 -1 -1 28 3433 19 6.55708e+06 530420 500653. 1732.36 0.49 0.0838839 0.0748833 21310 115450 -1 2860 19 1167 3779 180535 45529 6.59044 6.59044 -133.662 -6.59044 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0217172 0.0197123 187 177 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_086.v common 1.76 vpr 64.29 MiB -1 -1 0.15 17452 13 0.14 -1 -1 32192 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 222 254 1 166 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2365 1134 8198 1752 5856 590 64.3 MiB 0.04 0.00 9.5772 7.60931 -162.659 -7.60931 7.60931 0.23 0.000354996 0.000325193 0.0199103 0.018532 -1 -1 -1 -1 26 2640 18 6.55708e+06 409870 477104. 1650.88 0.33 0.0653865 0.0584309 21022 109990 -1 2286 15 824 2298 113671 28726 6.82684 6.82684 -156.225 -6.82684 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0146309 0.01333 138 128 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_087.v common 2.89 vpr 64.68 MiB -1 -1 0.16 18752 14 0.32 -1 -1 32396 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 267 299 1 189 101 17 17 289 -1 unnamed_device 24.8 MiB 0.10 2654 1253 5741 1095 4066 580 64.7 MiB 0.03 0.00 10.1014 8.22497 -162.245 -8.22497 8.22497 0.23 0.000420987 0.000385592 0.0129977 0.0119483 -1 -1 -1 -1 28 3525 29 6.55708e+06 446035 500653. 1732.36 1.12 0.138603 0.121855 21310 115450 -1 2791 16 995 3352 161293 40081 7.37336 7.37336 -157.789 -7.37336 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0199676 0.0181409 183 173 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_088.v common 4.09 vpr 65.06 MiB -1 -1 0.18 18740 15 0.41 -1 -1 32468 -1 -1 50 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66624 32 32 334 366 1 242 114 17 17 289 -1 unnamed_device 25.6 MiB 0.10 3845 1754 10878 2260 7829 789 65.1 MiB 0.07 0.00 12.4201 9.30007 -197.166 -9.30007 9.30007 0.25 0.00073948 0.000685983 0.0295529 0.0270958 -1 -1 -1 -1 26 4755 36 6.55708e+06 602750 477104. 1650.88 2.09 0.22201 0.19724 21022 109990 -1 3923 19 1866 5993 314116 76247 8.60335 8.60335 -194.026 -8.60335 0 0 585099. 2024.56 0.02 0.10 0.06 -1 -1 0.02 0.0383912 0.0348739 250 240 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_089.v common 2.17 vpr 64.28 MiB -1 -1 0.18 17984 11 0.14 -1 -1 32264 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 32 32 220 252 1 154 97 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2168 1074 8977 1935 6287 755 64.3 MiB 0.04 0.00 8.59479 6.66858 -139.589 -6.66858 6.66858 0.23 0.000338532 0.000309224 0.0167458 0.015295 -1 -1 -1 -1 26 2415 19 6.55708e+06 397815 477104. 1650.88 0.66 0.0991471 0.0868577 21022 109990 -1 2246 16 755 2442 124269 30281 5.94258 5.94258 -136.678 -5.94258 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0148758 0.0135052 142 126 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_090.v common 2.99 vpr 64.48 MiB -1 -1 0.15 17984 12 0.16 -1 -1 32296 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 31 32 244 276 1 183 99 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2718 1278 7623 1628 5411 584 64.5 MiB 0.04 0.00 9.30618 7.4792 -158.92 -7.4792 7.4792 0.23 0.000382061 0.000343151 0.0153388 0.0139891 -1 -1 -1 -1 26 3486 19 6.55708e+06 433980 477104. 1650.88 1.45 0.150081 0.132485 21022 109990 -1 2982 15 1147 3679 189997 47278 6.26704 6.26704 -150.559 -6.26704 0 0 585099. 2024.56 0.03 0.05 0.07 -1 -1 0.03 0.0191888 0.0175386 165 153 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_091.v common 3.49 vpr 64.71 MiB -1 -1 0.18 18368 12 0.26 -1 -1 32432 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 300 332 1 217 108 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3275 1622 10645 2328 7422 895 64.7 MiB 0.08 0.00 10.2612 7.59364 -164.56 -7.59364 7.59364 0.24 0.000486686 0.000442889 0.0386317 0.0358231 -1 -1 -1 -1 34 3724 22 6.55708e+06 530420 585099. 2024.56 1.66 0.233929 0.207628 22462 138074 -1 3411 16 1421 4778 241051 58262 6.6811 6.6811 -156.408 -6.6811 0 0 742403. 2568.87 0.04 0.10 0.08 -1 -1 0.04 0.03612 0.0328032 217 206 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_092.v common 3.37 vpr 64.69 MiB -1 -1 0.18 18604 12 0.21 -1 -1 32768 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 271 303 1 200 105 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3003 1380 8750 1810 6138 802 64.7 MiB 0.05 0.00 9.79464 7.36891 -159.112 -7.36891 7.36891 0.23 0.000426637 0.000390945 0.017895 0.0164169 -1 -1 -1 -1 24 4116 29 6.55708e+06 494255 448715. 1552.65 1.71 0.160092 0.141723 20734 103517 -1 3365 25 1982 7225 408926 104160 6.75244 6.75244 -158.639 -6.75244 0 0 554710. 1919.41 0.02 0.09 0.06 -1 -1 0.02 0.025969 0.0232829 190 177 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_093.v common 4.60 vpr 64.64 MiB -1 -1 0.18 19136 14 0.42 -1 -1 32440 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 327 359 1 229 108 17 17 289 -1 unnamed_device 25.3 MiB 0.09 3556 1590 6276 1065 4786 425 64.6 MiB 0.05 0.00 11.4017 8.85831 -179.658 -8.85831 8.85831 0.23 0.00100888 0.000964631 0.0195122 0.0181514 -1 -1 -1 -1 26 4696 36 6.55708e+06 530420 477104. 1650.88 2.70 0.216563 0.19256 21022 109990 -1 3722 21 1876 6496 326439 79639 7.96009 7.96009 -172.069 -7.96009 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0285679 0.0258669 239 233 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_094.v common 2.94 vpr 64.52 MiB -1 -1 0.16 18364 12 0.18 -1 -1 32224 -1 -1 35 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 30 32 246 278 1 176 97 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2728 1268 8755 2050 5708 997 64.5 MiB 0.05 0.00 10.0467 7.41486 -143.807 -7.41486 7.41486 0.24 0.00040521 0.000366057 0.0205555 0.0189281 -1 -1 -1 -1 28 3102 24 6.55708e+06 421925 500653. 1732.36 1.32 0.176868 0.155997 21310 115450 -1 2547 27 942 3467 228891 85010 6.50684 6.50684 -134.136 -6.50684 0 0 612192. 2118.31 0.02 0.08 0.06 -1 -1 0.02 0.0271277 0.0243958 166 158 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_095.v common 2.40 vpr 64.17 MiB -1 -1 0.15 17980 11 0.16 -1 -1 31856 -1 -1 31 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 27 32 219 251 1 153 90 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2075 890 11346 2674 7241 1431 64.2 MiB 0.05 0.00 8.56235 6.47229 -119.898 -6.47229 6.47229 0.23 0.000341003 0.000311104 0.0216579 0.0197916 -1 -1 -1 -1 28 2291 17 6.55708e+06 373705 500653. 1732.36 0.84 0.110181 0.0967621 21310 115450 -1 1920 17 832 2771 122094 32173 5.80812 5.80812 -117.51 -5.80812 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0160773 0.0145507 146 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_096.v common 3.17 vpr 65.43 MiB -1 -1 0.30 19132 13 0.39 -1 -1 32616 -1 -1 54 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67004 32 32 380 412 1 274 118 17 17 289 -1 unnamed_device 25.5 MiB 0.10 4655 2221 11100 2341 7945 814 65.4 MiB 0.09 0.00 10.8384 8.21927 -169.077 -8.21927 8.21927 0.23 0.000611341 0.000552744 0.0377977 0.0348813 -1 -1 -1 -1 30 5210 32 6.55708e+06 650970 526063. 1820.29 1.10 0.160347 0.144658 21886 126133 -1 4272 20 1942 7051 322540 77378 7.23124 7.23124 -159.615 -7.23124 0 0 666494. 2306.21 0.02 0.08 0.07 -1 -1 0.02 0.031786 0.028998 289 286 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_097.v common 2.30 vpr 64.73 MiB -1 -1 0.17 18368 14 0.22 -1 -1 32316 -1 -1 41 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 31 32 277 309 1 197 104 17 17 289 -1 unnamed_device 25.2 MiB 0.06 3097 1274 12304 3037 7768 1499 64.7 MiB 0.06 0.00 12.2136 8.62006 -170.085 -8.62006 8.62006 0.24 0.000432138 0.000396089 0.0252147 0.0231002 -1 -1 -1 -1 26 3603 32 6.55708e+06 494255 477104. 1650.88 0.68 0.106179 0.0939771 21022 109990 -1 2789 17 1209 3625 176693 45658 7.45942 7.45942 -162.283 -7.45942 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0202702 0.0183759 202 186 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_098.v common 1.86 vpr 64.37 MiB -1 -1 0.16 18360 12 0.15 -1 -1 32220 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 229 261 1 169 98 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2364 1167 6398 1184 4756 458 64.4 MiB 0.04 0.00 10.1826 7.64801 -160.064 -7.64801 7.64801 0.23 0.00048408 0.000452387 0.0138589 0.0127355 -1 -1 -1 -1 26 2856 21 6.55708e+06 409870 477104. 1650.88 0.37 0.0640324 0.0568082 21022 109990 -1 2410 15 851 2669 125206 31603 6.5589 6.5589 -149.274 -6.5589 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0155306 0.0141676 149 135 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_099.v common 3.16 vpr 64.67 MiB -1 -1 0.18 18364 13 0.25 -1 -1 31888 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 32 32 263 295 1 192 101 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2878 1329 9971 1977 6864 1130 64.7 MiB 0.05 0.00 10.3391 7.91544 -159.644 -7.91544 7.91544 0.23 0.000426804 0.0003908 0.0210623 0.0192623 -1 -1 -1 -1 28 3543 34 6.55708e+06 446035 500653. 1732.36 1.25 0.163021 0.144227 21310 115450 -1 2890 17 1266 4303 210367 52177 6.7993 6.7993 -152.562 -6.7993 0 0 612192. 2118.31 0.02 0.06 0.08 -1 -1 0.02 0.0235242 0.0211813 177 169 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_100.v common 3.61 vpr 64.95 MiB -1 -1 0.17 18748 13 0.29 -1 -1 32496 -1 -1 48 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 31 32 321 353 1 234 111 17 17 289 -1 unnamed_device 25.6 MiB 0.08 3400 1604 9953 2030 7063 860 64.9 MiB 0.06 0.00 9.6468 7.26834 -148.565 -7.26834 7.26834 0.23 0.000503324 0.000461623 0.0225716 0.0206576 -1 -1 -1 -1 26 4462 29 6.55708e+06 578640 477104. 1650.88 1.84 0.204323 0.180668 21022 109990 -1 3651 20 2029 6761 360098 85834 6.67706 6.67706 -150.677 -6.67706 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0263633 0.0238787 242 230 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_101.v common 2.43 vpr 64.31 MiB -1 -1 0.21 17984 11 0.22 -1 -1 32456 -1 -1 43 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 30 32 287 319 1 198 105 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3001 1293 11220 2634 7278 1308 64.3 MiB 0.14 0.00 9.47524 7.25311 -136.619 -7.25311 7.25311 0.25 0.00121921 0.00112523 0.0612861 0.0568716 -1 -1 -1 -1 30 2864 16 6.55708e+06 518365 526063. 1820.29 0.60 0.154135 0.140337 21886 126133 -1 2537 18 972 3930 165233 40913 6.35004 6.35004 -128.389 -6.35004 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0273439 0.0245502 207 199 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_102.v common 2.56 vpr 64.80 MiB -1 -1 0.18 18752 15 0.33 -1 -1 32512 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 296 328 1 208 101 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3400 1425 8326 1756 5851 719 64.8 MiB 0.05 0.00 12.6428 9.11323 -184.154 -9.11323 9.11323 0.23 0.00050701 0.000465418 0.0201741 0.0184292 -1 -1 -1 -1 26 3950 24 6.55708e+06 446035 477104. 1650.88 0.61 0.0902455 0.0803698 21022 109990 -1 3244 16 1338 4712 234668 58393 7.97942 7.97942 -176.46 -7.97942 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0212655 0.0193666 207 202 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_103.v common 3.78 vpr 64.78 MiB -1 -1 0.18 18752 13 0.31 -1 -1 32440 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 285 317 1 204 102 17 17 289 -1 unnamed_device 25.2 MiB 0.12 3131 1495 5338 899 4142 297 64.8 MiB 0.03 0.00 10.6725 8.26703 -174.041 -8.26703 8.26703 0.24 0.000462099 0.000423406 0.0133165 0.0122552 -1 -1 -1 -1 28 4046 41 6.55708e+06 458090 500653. 1732.36 1.93 0.213209 0.188425 21310 115450 -1 3146 16 1246 4278 217929 53207 7.2409 7.2409 -163.588 -7.2409 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0212515 0.0193558 202 191 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_104.v common 2.00 vpr 64.46 MiB -1 -1 0.18 17984 12 0.18 -1 -1 32132 -1 -1 41 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 29 32 239 271 1 178 102 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2844 1190 7956 1682 5619 655 64.5 MiB 0.04 0.00 10.6983 7.98398 -159.232 -7.98398 7.98398 0.24 0.000371108 0.000339729 0.0153222 0.014034 -1 -1 -1 -1 26 3200 29 6.55708e+06 494255 477104. 1650.88 0.45 0.0732874 0.0649933 21022 109990 -1 2709 20 1104 3239 159893 40584 7.1573 7.1573 -156.73 -7.1573 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0188511 0.0170473 168 154 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_105.v common 2.75 vpr 63.94 MiB -1 -1 0.16 18368 11 0.13 -1 -1 32292 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 32 32 235 267 1 176 98 17 17 289 -1 unnamed_device 24.1 MiB 0.05 2767 1260 7298 1447 5288 563 63.9 MiB 0.05 0.00 9.23769 6.98988 -143.739 -6.98988 6.98988 0.34 0.000348314 0.000318582 0.018582 0.0170113 -1 -1 -1 -1 26 3168 19 6.55708e+06 409870 477104. 1650.88 1.13 0.150939 0.133035 21022 109990 -1 2729 16 1008 3088 154235 38775 6.31284 6.31284 -144.7 -6.31284 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0156476 0.0142051 155 141 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_106.v common 2.74 vpr 64.85 MiB -1 -1 0.17 18368 13 0.29 -1 -1 32432 -1 -1 44 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66404 31 32 294 326 1 211 107 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3439 1453 7444 1510 5262 672 64.8 MiB 0.06 0.00 10.2189 7.97431 -160.47 -7.97431 7.97431 0.36 0.000708924 0.000639099 0.0251625 0.0230048 -1 -1 -1 -1 28 3874 29 6.55708e+06 530420 500653. 1732.36 0.63 0.105132 0.0937956 21310 115450 -1 3104 16 1212 4206 205123 50684 7.4003 7.4003 -160.122 -7.4003 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0211131 0.0192249 211 203 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_107.v common 2.44 vpr 64.32 MiB -1 -1 0.20 17972 10 0.18 -1 -1 32220 -1 -1 35 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 219 251 1 150 96 17 17 289 -1 unnamed_device 24.8 MiB 0.06 1946 1061 5790 1112 4104 574 64.3 MiB 0.04 0.00 7.37011 6.00295 -119.764 -6.00295 6.00295 0.25 0.00035911 0.000329803 0.0191472 0.0177945 -1 -1 -1 -1 26 2502 24 6.55708e+06 421925 477104. 1650.88 0.86 0.117586 0.103676 21022 109990 -1 2062 17 806 2797 128453 31706 5.21312 5.21312 -114.473 -5.21312 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0158314 0.0142786 147 134 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_108.v common 2.22 vpr 64.45 MiB -1 -1 0.18 17980 14 0.17 -1 -1 32276 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 239 271 1 173 98 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2734 1213 7073 1458 5059 556 64.5 MiB 0.05 0.00 11.0242 8.4809 -168.731 -8.4809 8.4809 0.33 0.000366617 0.000335327 0.0184044 0.0169477 -1 -1 -1 -1 26 3090 29 6.55708e+06 409870 477104. 1650.88 0.58 0.101652 0.0904075 21022 109990 -1 2658 16 969 3018 149359 37853 7.24455 7.24455 -157.889 -7.24455 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0163044 0.0148298 156 145 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_109.v common 2.81 vpr 64.29 MiB -1 -1 0.18 18752 13 0.24 -1 -1 32408 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 31 32 266 298 1 193 103 17 17 289 -1 unnamed_device 24.8 MiB 0.09 3161 1363 8538 1729 6172 637 64.3 MiB 0.05 0.00 10.4036 7.97301 -166.024 -7.97301 7.97301 0.24 0.000424703 0.000382451 0.024452 0.0226427 -1 -1 -1 -1 26 3263 23 6.55708e+06 482200 477104. 1650.88 1.15 0.195819 0.172559 21022 109990 -1 2818 15 1049 3322 160900 40390 6.8803 6.8803 -152.18 -6.8803 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0178379 0.0162423 188 175 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_110.v common 2.58 vpr 64.30 MiB -1 -1 0.21 17984 12 0.13 -1 -1 32200 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 31 32 225 257 1 161 97 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2415 1133 6757 1438 4598 721 64.3 MiB 0.03 0.00 9.26878 7.00946 -143.372 -7.00946 7.00946 0.23 0.000349322 0.000319975 0.0126652 0.0116002 -1 -1 -1 -1 26 2691 23 6.55708e+06 409870 477104. 1650.88 0.96 0.107657 0.0948875 21022 109990 -1 2292 17 845 2615 133353 32686 6.23184 6.23184 -137.649 -6.23184 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0283693 0.0256193 145 134 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_111.v common 2.97 vpr 64.77 MiB -1 -1 0.22 17980 12 0.18 -1 -1 33052 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 288 320 1 205 105 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3231 1460 9244 1928 6414 902 64.8 MiB 0.07 0.00 9.79864 7.07814 -148.913 -7.07814 7.07814 0.27 0.000569668 0.000527241 0.0282744 0.0260291 -1 -1 -1 -1 28 3623 19 6.55708e+06 494255 500653. 1732.36 1.21 0.175311 0.154218 21310 115450 -1 3038 18 1249 4669 234810 56737 6.41878 6.41878 -147.502 -6.41878 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0237192 0.021482 206 194 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_112.v common 3.31 vpr 64.61 MiB -1 -1 0.19 18740 13 0.29 -1 -1 32356 -1 -1 38 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 31 32 282 314 1 202 101 17 17 289 -1 unnamed_device 24.8 MiB 0.10 3277 1590 6681 1310 4868 503 64.6 MiB 0.04 0.00 10.7471 8.73972 -167.897 -8.73972 8.73972 0.23 0.000460535 0.000422889 0.0162374 0.0149525 -1 -1 -1 -1 28 3932 24 6.55708e+06 458090 500653. 1732.36 1.51 0.16573 0.146424 21310 115450 -1 3256 15 1195 4023 206433 49925 7.28716 7.28716 -157.96 -7.28716 0 0 612192. 2118.31 0.02 0.06 0.07 -1 -1 0.02 0.0254841 0.02301 201 191 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_113.v common 1.99 vpr 64.38 MiB -1 -1 0.19 17984 11 0.16 -1 -1 32248 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 233 265 1 176 99 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2465 1216 7395 1434 5485 476 64.4 MiB 0.04 0.00 8.01481 6.6836 -143.167 -6.6836 6.6836 0.23 0.000354533 0.00032415 0.0139007 0.0127385 -1 -1 -1 -1 26 2889 24 6.55708e+06 421925 477104. 1650.88 0.40 0.0652603 0.0578256 21022 109990 -1 2427 20 1207 3730 171289 43329 5.71184 5.71184 -135.745 -5.71184 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0233234 0.0209333 152 139 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_114.v common 2.17 vpr 64.54 MiB -1 -1 0.22 17980 13 0.22 -1 -1 32172 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 32 32 254 286 1 183 102 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2879 1214 6528 1147 5041 340 64.5 MiB 0.04 0.00 10.6786 7.73627 -160.675 -7.73627 7.73627 0.25 0.000409177 0.000375614 0.0135402 0.0124612 -1 -1 -1 -1 26 2886 16 6.55708e+06 458090 477104. 1650.88 0.39 0.0686872 0.0611683 21022 109990 -1 2556 28 1471 5017 296309 110070 6.74524 6.74524 -153.355 -6.74524 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.0258403 0.0231684 170 160 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_115.v common 3.18 vpr 64.73 MiB -1 -1 0.25 18368 13 0.32 -1 -1 32408 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 32 32 285 317 1 211 105 17 17 289 -1 unnamed_device 25.3 MiB 0.10 3339 1491 8503 1758 5902 843 64.7 MiB 0.05 0.00 10.8748 7.88135 -168.607 -7.88135 7.88135 0.37 0.000513341 0.000475271 0.0182779 0.0167377 -1 -1 -1 -1 28 3856 19 6.55708e+06 494255 500653. 1732.36 1.11 0.135527 0.119597 21310 115450 -1 3156 16 1241 3837 184163 45729 6.9979 6.9979 -160.864 -6.9979 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0198868 0.0181274 203 191 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_116.v common 2.49 vpr 64.50 MiB -1 -1 0.18 18368 11 0.26 -1 -1 32416 -1 -1 36 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 29 32 243 275 1 174 97 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2558 1138 10309 2535 6640 1134 64.5 MiB 0.06 0.00 9.92175 6.74749 -129.645 -6.74749 6.74749 0.30 0.000772465 0.000712951 0.0260806 0.0238587 -1 -1 -1 -1 26 3126 32 6.55708e+06 433980 477104. 1650.88 0.67 0.0939845 0.0839562 21022 109990 -1 2578 17 931 3325 169042 40480 6.05818 6.05818 -124.542 -6.05818 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184457 0.0167471 161 158 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_117.v common 4.27 vpr 64.39 MiB -1 -1 0.29 19136 14 0.31 -1 -1 33084 -1 -1 49 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 318 350 1 238 113 17 17 289 -1 unnamed_device 25.0 MiB 0.10 3835 1720 13490 3177 9101 1212 64.4 MiB 0.09 0.00 11.3374 8.61726 -184.782 -8.61726 8.61726 0.38 0.000531117 0.000488117 0.0381217 0.0350571 -1 -1 -1 -1 26 4747 29 6.55708e+06 590695 477104. 1650.88 1.96 0.210063 0.187395 21022 109990 -1 3847 17 1619 5028 258599 64735 7.6387 7.6387 -177.864 -7.6387 0 0 585099. 2024.56 0.03 0.07 0.10 -1 -1 0.03 0.0264884 0.0241963 237 224 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_118.v common 3.07 vpr 64.34 MiB -1 -1 0.14 17596 12 0.16 -1 -1 32212 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 31 32 222 254 1 168 102 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2680 1201 9146 2230 5919 997 64.3 MiB 0.07 0.00 9.64207 6.86528 -149.041 -6.86528 6.86528 0.27 0.000812538 0.000756576 0.0281269 0.0260777 -1 -1 -1 -1 28 2882 21 6.55708e+06 470145 500653. 1732.36 1.53 0.151684 0.134655 21310 115450 -1 2472 16 858 2767 136347 34084 6.01898 6.01898 -141.29 -6.01898 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0163473 0.014792 148 131 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_119.v common 3.95 vpr 64.73 MiB -1 -1 0.18 18748 13 0.38 -1 -1 33024 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 282 314 1 207 106 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3147 1501 6856 1348 5065 443 64.7 MiB 0.04 0.00 11.0904 8.08861 -162.494 -8.08861 8.08861 0.24 0.000487836 0.00044248 0.0151914 0.0139396 -1 -1 -1 -1 30 3270 24 6.55708e+06 506310 526063. 1820.29 1.81 0.202497 0.178708 21886 126133 -1 2801 17 1152 3849 170213 42169 6.9959 6.9959 -151.51 -6.9959 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0214516 0.0195268 197 188 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_120.v common 2.26 vpr 64.41 MiB -1 -1 0.16 18356 13 0.16 -1 -1 31960 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 238 270 1 177 100 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2839 1155 9612 2317 6234 1061 64.4 MiB 0.06 0.00 10.0742 7.73627 -166.258 -7.73627 7.73627 0.26 0.000577123 0.000544952 0.0229617 0.0211759 -1 -1 -1 -1 26 3028 23 6.55708e+06 433980 477104. 1650.88 0.64 0.0971387 0.0867266 21022 109990 -1 2456 17 990 2796 128129 34060 6.7183 6.7183 -154.301 -6.7183 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0259404 0.0234647 163 144 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_121.v common 2.36 vpr 64.06 MiB -1 -1 0.19 18364 12 0.19 -1 -1 32400 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65600 32 32 269 301 1 185 98 17 17 289 -1 unnamed_device 24.0 MiB 0.07 2537 1263 4823 745 3784 294 64.1 MiB 0.04 0.00 8.39043 7.2824 -152.393 -7.2824 7.2824 0.28 0.000905441 0.000848363 0.0153777 0.0142054 -1 -1 -1 -1 26 3179 19 6.55708e+06 409870 477104. 1650.88 0.52 0.0875654 0.0779802 21022 109990 -1 2833 16 1121 3843 195292 47160 6.33578 6.33578 -144.328 -6.33578 0 0 585099. 2024.56 0.04 0.12 0.08 -1 -1 0.04 0.0502091 0.0457004 181 175 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_122.v common 4.30 vpr 64.66 MiB -1 -1 0.21 19136 15 0.52 -1 -1 32728 -1 -1 53 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 350 382 1 251 117 17 17 289 -1 unnamed_device 25.5 MiB 0.10 4081 1828 11271 2288 8079 904 64.7 MiB 0.08 0.00 12.2654 9.04209 -187.694 -9.04209 9.04209 0.24 0.000564516 0.000516461 0.0316535 0.0292536 -1 -1 -1 -1 34 4381 20 6.55708e+06 638915 585099. 2024.56 1.93 0.266028 0.237356 22462 138074 -1 3819 17 1628 5914 283565 69847 7.93821 7.93821 -172.8 -7.93821 0 0 742403. 2568.87 0.04 0.11 0.13 -1 -1 0.04 0.0448869 0.0406004 267 256 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_123.v common 2.15 vpr 63.67 MiB -1 -1 0.17 17984 10 0.08 -1 -1 31896 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65200 30 32 174 206 1 130 87 17 17 289 -1 unnamed_device 24.1 MiB 0.06 1854 885 5271 1136 3651 484 63.7 MiB 0.03 0.00 6.3165 5.04697 -113.367 -5.04697 5.04697 0.27 0.000281181 0.000256712 0.0096779 0.00890741 -1 -1 -1 -1 22 2009 18 6.55708e+06 301375 420624. 1455.45 0.72 0.0769089 0.067373 20158 92377 -1 1822 15 647 1672 87673 22492 4.69874 4.69874 -113.69 -4.69874 0 0 500653. 1732.36 0.02 0.03 0.05 -1 -1 0.02 0.0113927 0.0102766 101 86 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_124.v common 2.17 vpr 64.31 MiB -1 -1 0.16 17984 13 0.16 -1 -1 32224 -1 -1 35 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65856 30 32 228 260 1 166 97 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2503 1064 8533 2145 5652 736 64.3 MiB 0.05 0.00 9.22658 7.43294 -146.134 -7.43294 7.43294 0.25 0.000684186 0.00061813 0.0193226 0.0176829 -1 -1 -1 -1 26 2779 19 6.55708e+06 421925 477104. 1650.88 0.59 0.0941429 0.083978 21022 109990 -1 2338 20 900 2793 146444 39162 6.62764 6.62764 -141.958 -6.62764 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0212905 0.0192897 158 140 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_125.v common 2.93 vpr 64.61 MiB -1 -1 0.16 17984 12 0.22 -1 -1 32456 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66164 32 32 264 296 1 190 103 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2629 1279 6851 1204 5209 438 64.6 MiB 0.06 0.00 9.58679 7.67078 -160.044 -7.67078 7.67078 0.26 0.00074458 0.000678895 0.0262383 0.0240079 -1 -1 -1 -1 26 3107 22 6.55708e+06 470145 477104. 1650.88 1.18 0.160881 0.142423 21022 109990 -1 2653 17 1110 3493 165297 42443 6.9215 6.9215 -157.739 -6.9215 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.0191677 0.017369 182 170 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_126.v common 1.94 vpr 63.14 MiB -1 -1 0.16 17984 9 0.14 -1 -1 32072 -1 -1 32 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64652 25 32 183 215 1 133 89 17 17 289 -1 unnamed_device 23.7 MiB 0.04 1645 871 9395 2229 5617 1549 63.1 MiB 0.04 0.00 7.61712 5.81412 -100.01 -5.81412 5.81412 0.24 0.000292282 0.000267119 0.0173114 0.0159233 -1 -1 -1 -1 20 2082 17 6.55708e+06 385760 394039. 1363.46 0.46 0.0530832 0.0471797 19870 87366 -1 1921 20 716 2165 117867 32355 5.29412 5.29412 -99.9076 -5.29412 0 0 477104. 1650.88 0.02 0.04 0.05 -1 -1 0.02 0.0149858 0.0134956 117 110 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_127.v common 2.38 vpr 64.78 MiB -1 -1 0.19 18368 12 0.24 -1 -1 32288 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66336 32 32 300 332 1 216 107 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3565 1492 7444 1324 5746 374 64.8 MiB 0.05 0.00 10.0075 7.59118 -168.041 -7.59118 7.59118 0.24 0.000891795 0.000812487 0.0203308 0.0187674 -1 -1 -1 -1 26 3908 24 6.55708e+06 518365 477104. 1650.88 0.63 0.101343 0.0903997 21022 109990 -1 3205 18 1335 4400 213388 52780 6.7621 6.7621 -161.57 -6.7621 0 0 585099. 2024.56 0.03 0.09 0.07 -1 -1 0.03 0.038608 0.0346733 214 206 -1 -1 -1 -1 +fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_128.v common 3.03 vpr 64.82 MiB -1 -1 0.34 18748 13 0.34 -1 -1 32352 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 290 322 1 209 103 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3076 1400 9020 1816 6496 708 64.8 MiB 0.06 0.00 10.9492 8.22447 -168.698 -8.22447 8.22447 0.24 0.000468237 0.000425889 0.0269885 0.0247947 -1 -1 -1 -1 26 4161 44 6.55708e+06 482200 477104. 1650.88 0.88 0.150718 0.134439 21022 109990 -1 3404 19 1491 5035 261566 64544 7.49096 7.49096 -169.674 -7.49096 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0380429 0.0345811 210 199 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 2.05 vpr 64.81 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30188 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 32 32 354 285 1 202 100 17 17 289 -1 unnamed_device 24.9 MiB 0.17 2678 1168 17500 5183 9317 3000 64.8 MiB 0.09 0.00 6.89032 5.76129 -168.782 -5.76129 5.76129 0.25 0.000333333 0.000305308 0.0299479 0.0274962 -1 -1 -1 -1 32 2438 20 6.64007e+06 452088 554710. 1919.41 0.45 0.0846256 0.0753861 22834 132086 -1 2056 19 1088 1723 102004 24911 4.49028 4.49028 -149.555 -4.49028 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0160781 0.0144875 152 50 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.00 vpr 64.81 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29772 -1 -1 30 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2387 1153 13961 4091 8036 1834 64.8 MiB 0.11 0.00 6.11521 5.05541 -146.114 -5.05541 5.05541 0.25 0.000500957 0.000466786 0.0364324 0.0336624 -1 -1 -1 -1 32 2330 19 6.64007e+06 376740 554710. 1919.41 0.43 0.0998543 0.0896451 22834 132086 -1 2183 20 1448 2220 169416 37520 3.76628 3.76628 -132.238 -3.76628 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0177524 0.0158766 147 63 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.62 vpr 64.13 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 32 32 299 247 1 188 94 17 17 289 -1 unnamed_device 24.5 MiB 0.16 2525 988 13087 3736 7613 1738 64.1 MiB 0.07 0.00 5.74935 4.679 -119.362 -4.679 4.679 0.23 0.000294184 0.000268866 0.0198637 0.018188 -1 -1 -1 -1 28 2482 34 6.64007e+06 376740 500653. 1732.36 1.10 0.1219 0.106318 21970 115934 -1 1920 19 1114 1579 102339 24279 3.91102 3.91102 -116.938 -3.91102 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0155755 0.0139714 129 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.18 vpr 64.59 MiB -1 -1 0.19 17668 1 0.03 -1 -1 29756 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2219 999 11684 2867 7870 947 64.6 MiB 0.06 0.00 5.50467 4.50524 -120.656 -4.50524 4.50524 0.23 0.000301757 0.000276843 0.0194556 0.0177984 -1 -1 -1 -1 26 2353 21 6.64007e+06 389298 477104. 1650.88 0.78 0.102845 0.0897238 21682 110474 -1 1996 22 1376 2539 149716 35231 3.78483 3.78483 -117.773 -3.78483 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0206924 0.0183868 132 31 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 1.93 vpr 64.67 MiB -1 -1 0.11 18052 1 0.03 -1 -1 30212 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 25.2 MiB 0.05 2401 1044 13340 3641 8511 1188 64.7 MiB 0.10 0.00 5.52176 4.47681 -129.939 -4.47681 4.47681 0.27 0.000326175 0.000298389 0.0335294 0.031105 -1 -1 -1 -1 26 2714 23 6.64007e+06 351624 477104. 1650.88 0.52 0.0841857 0.0755446 21682 110474 -1 2319 20 1464 2737 194545 44782 3.91083 3.91083 -130.973 -3.91083 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0173489 0.015589 134 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.19 vpr 64.17 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29756 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 24.6 MiB 0.07 2589 1146 13840 3734 8768 1338 64.2 MiB 0.07 0.00 4.20679 3.37156 -118.042 -3.37156 3.37156 0.24 0.000343562 0.000314786 0.0216965 0.0198462 -1 -1 -1 -1 28 2430 24 6.64007e+06 489762 500653. 1732.36 0.79 0.125458 0.109537 21970 115934 -1 2113 20 1219 1980 106732 27236 3.00917 3.00917 -117.621 -3.00917 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0217329 0.0195006 145 58 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.30 vpr 63.78 MiB -1 -1 0.20 17288 1 0.02 -1 -1 30552 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65312 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1585 646 13324 5650 6908 766 63.8 MiB 0.06 0.00 4.47141 3.76738 -100.249 -3.76738 3.76738 0.24 0.000261076 0.000238807 0.0222262 0.0203919 -1 -1 -1 -1 30 1362 22 6.64007e+06 263718 526063. 1820.29 0.89 0.104457 0.0913085 22546 126617 -1 1268 22 886 1557 92007 22640 2.87397 2.87397 -91.7688 -2.87397 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0171266 0.015248 97 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.27 vpr 64.12 MiB -1 -1 0.11 17912 1 0.03 -1 -1 29800 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65656 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2037 1027 15848 4746 8906 2196 64.1 MiB 0.08 0.00 4.0843 3.4441 -101.869 -3.4441 3.4441 0.23 0.000279498 0.000255601 0.0233277 0.0213053 -1 -1 -1 -1 26 2300 22 6.64007e+06 439530 477104. 1650.88 0.94 0.108532 0.0952919 21682 110474 -1 2007 20 1077 1995 121729 28059 2.93817 2.93817 -99.1235 -2.93817 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0142379 0.0126856 123 4 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.53 vpr 64.61 MiB -1 -1 0.13 17908 1 0.03 -1 -1 30172 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 317 271 1 168 88 17 17 289 -1 unnamed_device 24.9 MiB 0.11 2086 995 13543 3931 7670 1942 64.6 MiB 0.06 0.00 3.99239 3.60222 -119.143 -3.60222 3.60222 0.23 0.000300054 0.000274015 0.0225345 0.0206345 -1 -1 -1 -1 32 1822 20 6.64007e+06 313950 554710. 1919.41 0.92 0.11928 0.104086 22834 132086 -1 1636 20 877 1310 79180 19116 2.89043 2.89043 -109.637 -2.89043 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0150146 0.013392 117 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.63 vpr 64.51 MiB -1 -1 0.13 17664 1 0.03 -1 -1 30140 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 24.9 MiB 0.12 1795 817 8003 1790 5827 386 64.5 MiB 0.05 0.00 4.55761 3.87558 -124.983 -3.87558 3.87558 0.24 0.000293751 0.000267622 0.014943 0.0137302 -1 -1 -1 -1 28 1916 23 6.64007e+06 238602 500653. 1732.36 0.99 0.107138 0.0936028 21970 115934 -1 1743 21 1210 1968 117336 30369 2.80477 2.80477 -113.751 -2.80477 0 0 612192. 2118.31 0.02 0.04 0.08 -1 -1 0.02 0.0158551 0.0140681 115 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.40 vpr 64.53 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29796 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 24.5 MiB 0.07 1688 651 12156 4701 5752 1703 64.5 MiB 0.06 0.00 4.55761 3.85358 -107.527 -3.85358 3.85358 0.25 0.000290653 0.000265701 0.0218367 0.0200019 -1 -1 -1 -1 30 1469 20 6.64007e+06 238602 526063. 1820.29 0.83 0.0990725 0.0867591 22546 126617 -1 1254 17 604 926 54157 13941 2.77497 2.77497 -95.1733 -2.77497 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0130171 0.0117058 101 63 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.31 vpr 64.49 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29716 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2346 951 8919 2111 6427 381 64.5 MiB 0.05 0.00 4.97492 3.76035 -118.411 -3.76035 3.76035 0.23 0.000287454 0.000258142 0.0148458 0.0135347 -1 -1 -1 -1 26 2233 26 6.64007e+06 288834 477104. 1650.88 0.90 0.106722 0.0926572 21682 110474 -1 1861 21 1041 1454 89116 22517 3.10837 3.10837 -114.215 -3.10837 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0137714 0.0122685 110 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 1.86 vpr 64.40 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29768 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2572 1221 14583 4808 7640 2135 64.4 MiB 0.09 0.00 4.99767 4.51687 -145.067 -4.51687 4.51687 0.24 0.000323777 0.000296108 0.0247005 0.0224532 -1 -1 -1 -1 30 2687 23 6.64007e+06 364182 526063. 1820.29 0.39 0.0704651 0.0623808 22546 126617 -1 2135 17 1045 1588 103097 22969 3.25883 3.25883 -126.603 -3.25883 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0154776 0.0138331 148 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.07 vpr 64.78 MiB -1 -1 0.14 17696 1 0.03 -1 -1 29780 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2535 922 19223 5837 10520 2866 64.8 MiB 0.11 0.00 5.92827 4.77444 -136.955 -4.77444 4.77444 0.25 0.000376709 0.000347561 0.0371074 0.034053 -1 -1 -1 -1 28 2714 33 6.64007e+06 426972 500653. 1732.36 0.57 0.0952296 0.0848217 21970 115934 -1 2193 22 1709 2838 188317 48152 4.01303 4.01303 -131.661 -4.01303 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0173466 0.0155029 139 61 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.26 vpr 64.13 MiB -1 -1 0.12 17672 1 0.02 -1 -1 30240 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 24.9 MiB 0.05 1651 648 11064 3436 5196 2432 64.1 MiB 0.06 0.00 3.81299 3.12479 -88.8266 -3.12479 3.12479 0.26 0.00026897 0.00023978 0.0232876 0.0215518 -1 -1 -1 -1 32 1369 19 6.64007e+06 288834 554710. 1919.41 0.89 0.105223 0.0919344 22834 132086 -1 1104 15 627 1014 49151 13344 2.77777 2.77777 -84.3561 -2.77777 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.0103697 0.00930164 103 27 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 1.84 vpr 64.30 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2380 942 16819 5830 8106 2883 64.3 MiB 0.09 0.00 4.6791 4.09527 -122.173 -4.09527 4.09527 0.23 0.000346698 0.000316608 0.0307314 0.0280788 -1 -1 -1 -1 32 2367 28 6.64007e+06 339066 554710. 1919.41 0.39 0.0804661 0.0715237 22834 132086 -1 1983 22 1455 2736 169045 42069 3.21356 3.21356 -117.004 -3.21356 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0201019 0.0179187 138 58 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 1.78 vpr 64.36 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29828 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2606 1192 12305 3184 7882 1239 64.4 MiB 0.07 0.00 5.47847 4.60407 -146.257 -4.60407 4.60407 0.23 0.000330363 0.000302451 0.0218624 0.0200378 -1 -1 -1 -1 32 2209 18 6.64007e+06 351624 554710. 1919.41 0.34 0.0628724 0.0559061 22834 132086 -1 2050 16 1144 1644 92509 23959 3.27883 3.27883 -126.125 -3.27883 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0139599 0.012587 144 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.37 vpr 64.11 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29644 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65648 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2093 899 12248 2945 8519 784 64.1 MiB 0.06 0.00 3.59784 2.85064 -103.682 -2.85064 2.85064 0.23 0.00031002 0.000284204 0.0183735 0.0167743 -1 -1 -1 -1 26 2006 25 6.64007e+06 426972 477104. 1650.88 0.82 0.101691 0.0889344 21682 110474 -1 1742 21 1124 1885 120447 29317 2.14431 2.14431 -98.4532 -2.14431 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152302 0.0135505 115 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.13 vpr 64.00 MiB -1 -1 0.11 17528 1 0.02 -1 -1 29752 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65532 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1535 603 7853 2116 5212 525 64.0 MiB 0.04 0.00 2.99233 2.39133 -77.851 -2.39133 2.39133 0.24 0.000231626 0.000212413 0.0147234 0.0135737 -1 -1 -1 -1 32 1129 17 6.64007e+06 213486 554710. 1919.41 0.86 0.0935232 0.0812611 22834 132086 -1 990 20 553 827 48112 12467 1.79471 1.79471 -72.575 -1.79471 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.0110231 0.00979166 85 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 1.76 vpr 64.60 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29800 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 31 32 291 243 1 171 87 17 17 289 -1 unnamed_device 24.5 MiB 0.15 2125 1026 10455 2663 6617 1175 64.6 MiB 0.06 0.00 6.02746 5.0168 -149.308 -5.0168 5.0168 0.23 0.000293444 0.000269173 0.0187775 0.0172066 -1 -1 -1 -1 30 2023 21 6.64007e+06 301392 526063. 1820.29 0.32 0.0582338 0.0515822 22546 126617 -1 1733 20 829 1237 65753 16555 3.62043 3.62043 -133.716 -3.62043 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0181583 0.0162736 127 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.76 vpr 64.73 MiB -1 -1 0.16 18436 1 0.03 -1 -1 29980 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 25.2 MiB 0.04 2331 1141 17961 5691 10386 1884 64.7 MiB 0.11 0.00 5.44296 4.13552 -132.934 -4.13552 4.13552 0.24 0.000351539 0.00032317 0.0368032 0.0340409 -1 -1 -1 -1 26 2527 22 6.64007e+06 464646 477104. 1650.88 1.27 0.152604 0.135082 21682 110474 -1 2212 22 1474 2442 179110 40191 3.73683 3.73683 -133.451 -3.73683 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0173672 0.0155182 140 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 2.89 vpr 64.85 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29712 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66404 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 24.9 MiB 0.25 2693 1197 9383 1945 6894 544 64.8 MiB 0.06 0.00 5.6841 4.62416 -139.043 -4.62416 4.62416 0.24 0.000343386 0.000314627 0.0172008 0.0157806 -1 -1 -1 -1 30 2804 24 6.64007e+06 389298 526063. 1820.29 1.14 0.12124 0.106579 22546 126617 -1 2221 19 1154 1858 115618 26985 3.82228 3.82228 -129.932 -3.82228 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0172664 0.0155995 151 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 1.96 vpr 63.86 MiB -1 -1 0.12 18056 1 0.02 -1 -1 30160 -1 -1 20 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65396 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1349 633 10868 3050 6437 1381 63.9 MiB 0.04 0.00 2.81093 2.39133 -70.7944 -2.39133 2.39133 0.23 0.000198641 0.000181079 0.0142663 0.0130218 -1 -1 -1 -1 26 1233 20 6.64007e+06 251160 477104. 1650.88 0.68 0.070323 0.0614049 21682 110474 -1 1121 19 523 781 49077 12394 1.95411 1.95411 -71.0211 -1.95411 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.0107949 0.00959479 81 30 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 1.78 vpr 64.57 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29764 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2052 991 13751 4633 6453 2665 64.6 MiB 0.07 0.00 4.97861 4.55404 -124.907 -4.55404 4.55404 0.25 0.000298608 0.000273835 0.0228545 0.0209681 -1 -1 -1 -1 32 2035 19 6.64007e+06 313950 554710. 1919.41 0.36 0.0657503 0.0584607 22834 132086 -1 1878 20 1138 2086 138403 31685 3.44803 3.44803 -114.756 -3.44803 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0144217 0.0128571 125 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.04 vpr 63.86 MiB -1 -1 0.11 17664 1 0.02 -1 -1 30076 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65388 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 24.7 MiB 0.03 1447 554 12331 4885 6406 1040 63.9 MiB 0.05 0.00 2.77793 2.35833 -70.3669 -2.35833 2.35833 0.24 0.000401366 0.000368701 0.0176975 0.0162144 -1 -1 -1 -1 28 1254 19 6.64007e+06 213486 500653. 1732.36 0.82 0.074078 0.0649612 21970 115934 -1 991 16 450 533 42691 11758 1.86191 1.86191 -70.1632 -1.86191 0 0 612192. 2118.31 0.02 0.02 0.06 -1 -1 0.02 0.00837099 0.00747193 82 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.55 vpr 64.57 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29764 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2081 918 9383 2172 5914 1297 64.6 MiB 0.05 0.00 5.31627 4.63183 -123.978 -4.63183 4.63183 0.24 0.000306745 0.000280355 0.0150318 0.0138059 -1 -1 -1 -1 30 2001 23 6.64007e+06 389298 526063. 1820.29 1.00 0.115117 0.10028 22546 126617 -1 1617 20 798 1425 79320 19609 3.37283 3.37283 -108.474 -3.37283 0 0 666494. 2306.21 0.04 0.05 0.12 -1 -1 0.04 0.0244901 0.0219357 126 24 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.28 vpr 64.39 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29948 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 24.6 MiB 0.03 2388 1070 19624 5823 11095 2706 64.4 MiB 0.10 0.00 4.70631 3.69341 -108.189 -3.69341 3.69341 0.23 0.000320509 0.00029285 0.0301434 0.0276299 -1 -1 -1 -1 28 2304 20 6.64007e+06 489762 500653. 1732.36 0.89 0.12607 0.111455 21970 115934 -1 2043 19 1110 2038 137544 38662 3.00917 3.00917 -107.4 -3.00917 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0143121 0.0128153 136 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.84 vpr 64.70 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30168 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 338 277 1 179 98 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2303 1088 17423 5246 9519 2658 64.7 MiB 0.09 0.00 5.78707 4.89043 -136.673 -4.89043 4.89043 0.24 0.000327236 0.000299569 0.0274047 0.0250913 -1 -1 -1 -1 26 2626 24 6.64007e+06 426972 477104. 1650.88 1.39 0.158323 0.139377 21682 110474 -1 2086 20 1058 1856 117209 27300 3.85983 3.85983 -129.261 -3.85983 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0157392 0.0140998 132 50 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.00 vpr 64.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29628 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 24.9 MiB 0.05 1848 932 9571 2445 6468 658 64.4 MiB 0.05 0.00 3.79099 3.02179 -103.859 -3.02179 3.02179 0.23 0.000290894 0.000267194 0.0165695 0.0152169 -1 -1 -1 -1 30 1784 18 6.64007e+06 263718 526063. 1820.29 0.65 0.0906451 0.0790376 22546 126617 -1 1601 19 736 1233 74070 17622 2.70797 2.70797 -101.892 -2.70797 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0137793 0.0123494 107 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.26 vpr 64.42 MiB -1 -1 0.12 17668 1 0.02 -1 -1 29852 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65964 30 32 262 227 1 135 86 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1630 675 10103 2270 6949 884 64.4 MiB 0.05 0.00 3.60179 3.24119 -95.5452 -3.24119 3.24119 0.23 0.00034986 0.000321242 0.0196118 0.0180662 -1 -1 -1 -1 30 1518 17 6.64007e+06 301392 526063. 1820.29 0.88 0.10414 0.0913886 22546 126617 -1 1212 20 661 1089 52330 13795 2.56257 2.56257 -89.8228 -2.56257 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0132004 0.0116361 100 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 1.76 vpr 64.43 MiB -1 -1 0.15 17668 1 0.03 -1 -1 29816 -1 -1 24 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 24.3 MiB 0.04 1853 868 11247 3492 5966 1789 64.4 MiB 0.07 0.00 4.1543 3.41886 -98.6687 -3.41886 3.41886 0.25 0.000328088 0.000304966 0.0270155 0.0250108 -1 -1 -1 -1 32 1674 22 6.64007e+06 301392 554710. 1919.41 0.34 0.0669298 0.0597058 22834 132086 -1 1544 22 868 1612 92339 21804 2.72157 2.72157 -97.0146 -2.72157 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0150226 0.0132339 104 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 2.35 vpr 64.43 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29816 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2077 943 13663 4291 7577 1795 64.4 MiB 0.06 0.00 4.55061 3.72021 -112.43 -3.72021 3.72021 0.24 0.00027512 0.000252672 0.0213097 0.0195023 -1 -1 -1 -1 26 2096 19 6.64007e+06 263718 477104. 1650.88 0.79 0.0898311 0.0787572 21682 110474 -1 1871 22 1227 1984 139135 31601 2.85597 2.85597 -110.575 -2.85597 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0139917 0.0124162 116 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.20 vpr 64.48 MiB -1 -1 0.13 17544 1 0.02 -1 -1 30152 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1915 918 11703 2893 8058 752 64.5 MiB 0.06 0.00 3.9659 3.50227 -105.619 -3.50227 3.50227 0.24 0.000276998 0.000253415 0.0163437 0.014946 -1 -1 -1 -1 32 1765 22 6.64007e+06 414414 554710. 1919.41 0.90 0.108379 0.0945088 22834 132086 -1 1550 19 732 1226 65350 16682 2.72157 2.72157 -100.584 -2.72157 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0126351 0.0112682 111 30 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.30 vpr 64.14 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29800 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65676 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2169 773 17273 5937 9206 2130 64.1 MiB 0.18 0.00 3.9379 3.3369 -101.534 -3.3369 3.3369 0.24 0.000761204 0.000704797 0.0671225 0.0623348 -1 -1 -1 -1 26 1968 20 6.64007e+06 389298 477104. 1650.88 0.86 0.144333 0.129123 21682 110474 -1 1572 20 922 1465 89723 22843 2.34097 2.34097 -89.7372 -2.34097 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0136178 0.012134 112 54 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 3.16 vpr 64.87 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29616 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2308 1232 18356 5288 9596 3472 64.9 MiB 0.09 0.00 4.83776 4.37413 -122.59 -4.37413 4.37413 0.25 0.000352344 0.000322425 0.0280539 0.025636 -1 -1 -1 -1 28 2975 26 6.64007e+06 527436 500653. 1732.36 1.76 0.14119 0.125231 21970 115934 -1 2412 18 1248 2439 162377 37472 3.48123 3.48123 -118.393 -3.48123 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.016007 0.0144134 158 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.55 vpr 64.89 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29744 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66448 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 25.5 MiB 0.07 2421 1023 18877 5825 10430 2622 64.9 MiB 0.11 0.00 4.51361 3.87558 -128.529 -3.87558 3.87558 0.23 0.000369261 0.000339114 0.0340034 0.0311586 -1 -1 -1 -1 32 2017 21 6.64007e+06 514878 554710. 1919.41 1.15 0.184919 0.162569 22834 132086 -1 1849 21 1444 2355 125874 31664 2.77177 2.77177 -110.96 -2.77177 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0176566 0.0158237 150 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.42 vpr 64.50 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29780 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 24.5 MiB 0.14 2417 918 9536 2320 6465 751 64.5 MiB 0.06 0.00 5.18307 4.35884 -128.706 -4.35884 4.35884 0.24 0.000284721 0.000261675 0.0198292 0.0182771 -1 -1 -1 -1 32 1849 20 6.64007e+06 288834 554710. 1919.41 0.90 0.111762 0.0974411 22834 132086 -1 1689 20 806 1172 74453 17829 3.22283 3.22283 -115.365 -3.22283 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0134962 0.0120415 114 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 1.89 vpr 64.34 MiB -1 -1 0.13 18052 1 0.04 -1 -1 29788 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65884 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2217 1122 16238 4882 9322 2034 64.3 MiB 0.09 0.00 4.8385 3.9971 -121.388 -3.9971 3.9971 0.23 0.000336917 0.000307579 0.0286334 0.0261744 -1 -1 -1 -1 32 2344 20 6.64007e+06 364182 554710. 1919.41 0.36 0.0728185 0.0646739 22834 132086 -1 2088 23 1449 2642 147498 35841 3.12137 3.12137 -116.821 -3.12137 0 0 701300. 2426.64 0.03 0.05 0.10 -1 -1 0.03 0.0194932 0.0173853 145 61 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.22 vpr 64.95 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29756 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 31 32 377 302 1 233 99 17 17 289 -1 unnamed_device 25.2 MiB 0.24 2995 1421 19707 5440 12139 2128 64.9 MiB 0.11 0.00 7.81519 5.67793 -171.305 -5.67793 5.67793 0.23 0.000346066 0.000316676 0.0325169 0.0297691 -1 -1 -1 -1 28 3277 23 6.64007e+06 452088 500653. 1732.36 0.61 0.104355 0.0932129 21970 115934 -1 2581 21 1555 2326 136329 33259 4.52274 4.52274 -159.537 -4.52274 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.018193 0.0163931 178 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.73 vpr 64.90 MiB -1 -1 0.24 18056 1 0.03 -1 -1 29784 -1 -1 32 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66456 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 25.2 MiB 0.20 2681 1319 14999 4569 8381 2049 64.9 MiB 0.09 0.00 6.40882 5.22399 -160.729 -5.22399 5.22399 0.25 0.000373524 0.000343579 0.0331096 0.0307403 -1 -1 -1 -1 32 2679 17 6.64007e+06 401856 554710. 1919.41 0.96 0.122984 0.109251 22834 132086 -1 2354 19 1056 1619 130226 28911 4.31108 4.31108 -149.075 -4.31108 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0237688 0.0214486 167 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.39 vpr 64.77 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30124 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2150 1128 15412 3921 9377 2114 64.8 MiB 0.08 0.00 5.33427 4.63507 -135.372 -4.63507 4.63507 0.23 0.000329383 0.000301672 0.0241206 0.0220879 -1 -1 -1 -1 30 2296 22 6.64007e+06 464646 526063. 1820.29 0.94 0.132554 0.115834 22546 126617 -1 2016 22 1100 1926 104277 24750 3.19762 3.19762 -115.815 -3.19762 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0177833 0.0158452 140 55 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.60 vpr 64.61 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30148 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 291 242 1 179 91 17 17 289 -1 unnamed_device 24.5 MiB 0.19 2447 1083 8863 2197 6096 570 64.6 MiB 0.05 0.00 5.56996 4.45012 -118.426 -4.45012 4.45012 0.25 0.000299359 0.000274949 0.0144886 0.0132926 -1 -1 -1 -1 32 2169 21 6.64007e+06 339066 554710. 1919.41 0.92 0.11342 0.0992661 22834 132086 -1 1944 22 951 1417 84928 20855 3.51243 3.51243 -111.872 -3.51243 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0149971 0.0133682 124 27 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 2.52 vpr 65.09 MiB -1 -1 0.13 17668 1 0.03 -1 -1 29868 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 25.2 MiB 0.10 3200 1325 22371 6342 13589 2440 65.1 MiB 0.14 0.00 6.26139 5.1195 -164.675 -5.1195 5.1195 0.23 0.0004489 0.000412219 0.0433974 0.0398984 -1 -1 -1 -1 28 3170 21 6.64007e+06 539994 500653. 1732.36 1.01 0.166744 0.147094 21970 115934 -1 2626 19 1703 2722 167391 39031 4.00549 4.00549 -146.496 -4.00549 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0228447 0.0204446 176 87 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 1.70 vpr 64.06 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29676 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65596 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2009 855 10481 2942 6568 971 64.1 MiB 0.06 0.00 4.5869 3.77367 -103.344 -3.77367 3.77367 0.24 0.000271845 0.000248737 0.0209896 0.0193119 -1 -1 -1 -1 32 1689 18 6.64007e+06 288834 554710. 1919.41 0.32 0.0563517 0.0499083 22834 132086 -1 1523 18 785 1365 80306 19202 2.76057 2.76057 -98.8257 -2.76057 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0123234 0.0110592 104 28 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 1.88 vpr 64.25 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30236 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 24.7 MiB 0.15 2890 1252 16081 4637 9397 2047 64.2 MiB 0.10 0.00 6.34307 5.14733 -154.615 -5.14733 5.14733 0.24 0.000368948 0.00034104 0.0275732 0.0253414 -1 -1 -1 -1 30 2475 23 6.64007e+06 426972 526063. 1820.29 0.39 0.0714749 0.0637398 22546 126617 -1 2096 16 1084 1657 88851 21305 3.68189 3.68189 -130.335 -3.68189 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0145065 0.0130876 149 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.98 vpr 64.76 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29612 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 349 284 1 182 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2675 1103 12240 2946 8556 738 64.8 MiB 0.07 0.00 4.99666 3.95307 -115.476 -3.95307 3.95307 0.24 0.000333577 0.000303121 0.0217054 0.0198476 -1 -1 -1 -1 26 2701 22 6.64007e+06 477204 477104. 1650.88 1.63 0.165153 0.14533 21682 110474 -1 2200 19 1260 2288 139167 34153 3.10737 3.10737 -113.433 -3.10737 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0155087 0.0138955 136 53 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 1.77 vpr 64.59 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29776 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1813 1148 12127 3848 6621 1658 64.6 MiB 0.07 0.00 4.79356 4.19256 -126.138 -4.19256 4.19256 0.24 0.000295337 0.000269636 0.0215588 0.0198294 -1 -1 -1 -1 32 2151 21 6.64007e+06 339066 554710. 1919.41 0.43 0.0824346 0.0732441 22834 132086 -1 1914 22 904 1746 107845 24237 3.45223 3.45223 -118.392 -3.45223 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.015861 0.0141677 127 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.07 vpr 64.82 MiB -1 -1 0.14 18052 1 0.03 -1 -1 30168 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 353 287 1 198 95 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2414 1205 15647 4038 9814 1795 64.8 MiB 0.11 0.00 5.52647 4.90352 -143.647 -4.90352 4.90352 0.25 0.0008019 0.000745825 0.0364362 0.033814 -1 -1 -1 -1 28 2686 18 6.64007e+06 389298 500653. 1732.36 0.39 0.0847936 0.0764764 21970 115934 -1 2410 18 1295 1758 111267 27132 3.30283 3.30283 -125.331 -3.30283 0 0 612192. 2118.31 0.02 0.07 0.10 -1 -1 0.02 0.02999 0.026759 142 55 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 2.65 vpr 64.80 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29828 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2461 1024 18178 5514 9376 3288 64.8 MiB 0.09 0.00 4.3595 3.73184 -117.882 -3.73184 3.73184 0.23 0.000342503 0.000313459 0.0274297 0.0250706 -1 -1 -1 -1 28 2934 24 6.64007e+06 489762 500653. 1732.36 1.24 0.134412 0.118217 21970 115934 -1 2157 20 1301 2160 149192 38424 3.16237 3.16237 -119.152 -3.16237 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0170942 0.0152499 139 55 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.02 vpr 64.38 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30240 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 24.9 MiB 0.10 2721 1115 21088 6199 11891 2998 64.4 MiB 0.14 0.00 5.01327 4.29207 -130.428 -4.29207 4.29207 0.25 0.000354017 0.000323912 0.0461859 0.0427932 -1 -1 -1 -1 28 2739 18 6.64007e+06 502320 500653. 1732.36 0.52 0.101778 0.0916839 21970 115934 -1 2203 21 1389 2324 157732 36229 3.12137 3.12137 -119.153 -3.12137 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176308 0.0157409 149 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 3.47 vpr 64.60 MiB -1 -1 0.18 17672 1 0.03 -1 -1 30132 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 25.2 MiB 0.06 1947 873 16108 4476 7806 3826 64.6 MiB 0.07 0.00 4.78256 4.34576 -121.313 -4.34576 4.34576 0.23 0.000306518 0.000280534 0.0227357 0.0207675 -1 -1 -1 -1 30 2090 25 6.64007e+06 452088 526063. 1820.29 1.86 0.113549 0.0993707 22546 126617 -1 1553 21 1051 1873 98927 27703 4.05503 4.05503 -119.589 -4.05503 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0151484 0.0135515 127 24 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 1.86 vpr 64.32 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29572 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 319 257 1 198 92 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2350 1149 11684 3237 7258 1189 64.3 MiB 0.07 0.00 6.11266 5.05904 -138.884 -5.05904 5.05904 0.23 0.000310168 0.000284344 0.0194827 0.0178456 -1 -1 -1 -1 32 2297 18 6.64007e+06 351624 554710. 1919.41 0.33 0.0597045 0.0529702 22834 132086 -1 2103 18 1068 1607 98345 23408 3.70662 3.70662 -126.282 -3.70662 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0145917 0.0131743 137 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 1.83 vpr 64.86 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30156 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2921 1233 9543 2186 6591 766 64.9 MiB 0.07 0.00 6.45652 5.2717 -153.789 -5.2717 5.2717 0.23 0.000341115 0.000312552 0.0185871 0.0170812 -1 -1 -1 -1 28 2872 24 6.64007e+06 376740 500653. 1732.36 0.39 0.0660029 0.0583999 21970 115934 -1 2431 24 1612 2594 167132 39590 4.02948 4.02948 -138.297 -4.02948 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0191265 0.0170798 151 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.47 vpr 64.84 MiB -1 -1 0.13 18048 1 0.03 -1 -1 30132 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2687 1076 16523 6080 8261 2182 64.8 MiB 0.10 0.00 5.30485 4.45447 -137.456 -4.45447 4.45447 0.23 0.000353272 0.000322898 0.0342221 0.0314022 -1 -1 -1 -1 32 2442 17 6.64007e+06 313950 554710. 1919.41 0.97 0.128817 0.11348 22834 132086 -1 2010 18 1272 2259 134813 32070 3.47843 3.47843 -125.006 -3.47843 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0187106 0.0168733 141 77 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 1.60 vpr 64.16 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29792 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65696 32 32 251 219 1 140 91 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1818 889 8659 1974 6034 651 64.2 MiB 0.05 0.00 3.7947 3.57147 -104.095 -3.57147 3.57147 0.23 0.000261867 0.000239075 0.0134388 0.0123337 -1 -1 -1 -1 28 1905 21 6.64007e+06 339066 500653. 1732.36 0.33 0.0523148 0.0459728 21970 115934 -1 1631 21 853 1375 86391 21527 2.77477 2.77477 -97.2385 -2.77477 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0138134 0.0123514 101 23 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.59 vpr 64.23 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29420 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 24.9 MiB 0.18 2440 999 7231 1434 5468 329 64.2 MiB 0.06 0.00 5.00545 4.0787 -137.534 -4.0787 4.0787 0.25 0.000462463 0.000411606 0.0167471 0.0154013 -1 -1 -1 -1 26 2717 42 6.64007e+06 339066 477104. 1650.88 1.09 0.111643 0.0977058 21682 110474 -1 2232 21 1443 2087 144175 36536 3.38903 3.38903 -135.561 -3.38903 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0161341 0.0143439 133 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 1.94 vpr 64.99 MiB -1 -1 0.12 18676 1 0.03 -1 -1 30196 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66548 32 32 387 293 1 234 98 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2841 1439 17873 5142 10318 2413 65.0 MiB 0.11 0.00 6.57692 5.56526 -164.086 -5.56526 5.56526 0.24 0.000362134 0.000331955 0.0320601 0.0294007 -1 -1 -1 -1 32 2821 20 6.64007e+06 426972 554710. 1919.41 0.38 0.0829831 0.0739859 22834 132086 -1 2555 20 1454 2329 127947 31765 4.32308 4.32308 -149.736 -4.32308 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0193231 0.0173864 174 31 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.28 vpr 64.72 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29928 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66276 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2567 1021 10336 2399 7366 571 64.7 MiB 0.06 0.00 5.11912 4.26806 -134.06 -4.26806 4.26806 0.23 0.000334349 0.000304198 0.0160871 0.0147197 -1 -1 -1 -1 30 2164 19 6.64007e+06 477204 526063. 1820.29 0.92 0.113507 0.0996864 22546 126617 -1 1765 18 985 1626 87746 21380 2.84497 2.84497 -113.29 -2.84497 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0148181 0.0133477 141 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 1.72 vpr 64.52 MiB -1 -1 0.18 17672 1 0.02 -1 -1 30240 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2182 743 10679 2942 6832 905 64.5 MiB 0.05 0.00 4.2965 3.52427 -104.21 -3.52427 3.52427 0.25 0.000284469 0.000260517 0.0152668 0.0139714 -1 -1 -1 -1 32 1599 16 6.64007e+06 414414 554710. 1919.41 0.31 0.0492061 0.0433694 22834 132086 -1 1397 17 644 1197 65700 16378 2.71257 2.71257 -96.443 -2.71257 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0125154 0.0112655 111 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.00 vpr 65.11 MiB -1 -1 0.18 18440 1 0.03 -1 -1 29996 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 431 332 1 235 95 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2995 1451 16943 5312 9314 2317 65.1 MiB 0.14 0.00 7.55549 6.37067 -184.872 -6.37067 6.37067 0.25 0.000439913 0.000406748 0.0454496 0.0419737 -1 -1 -1 -1 32 3012 21 6.64007e+06 389298 554710. 1919.41 1.27 0.189098 0.167098 22834 132086 -1 2523 19 1586 2324 142907 33660 5.14455 5.14455 -172.168 -5.14455 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0191733 0.0172741 177 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.58 vpr 64.71 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30356 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1956 1035 13668 3578 8233 1857 64.7 MiB 0.08 0.00 5.19907 4.58683 -138.182 -4.58683 4.58683 0.24 0.000338718 0.000311084 0.0250615 0.0230519 -1 -1 -1 -1 28 2405 23 6.64007e+06 477204 500653. 1732.36 1.17 0.125233 0.110063 21970 115934 -1 2035 19 1349 2237 141237 33242 3.66243 3.66243 -129.496 -3.66243 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0159444 0.0143778 136 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.01 vpr 64.10 MiB -1 -1 0.10 17672 1 0.02 -1 -1 29932 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65640 32 32 231 199 1 140 91 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1906 764 9067 2085 6178 804 64.1 MiB 0.05 0.00 4.2445 3.5653 -97.5026 -3.5653 3.5653 0.23 0.000250471 0.000229596 0.0128699 0.011824 -1 -1 -1 -1 26 1747 20 6.64007e+06 339066 477104. 1650.88 0.78 0.0916771 0.079558 21682 110474 -1 1553 18 736 1243 69356 18200 3.03517 3.03517 -99.0581 -3.03517 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0114051 0.0102012 103 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.25 vpr 64.42 MiB -1 -1 0.11 17912 1 0.03 -1 -1 29820 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2540 1175 11816 2954 8205 657 64.4 MiB 0.07 0.00 6.69892 5.65147 -139.258 -5.65147 5.65147 0.23 0.000343487 0.000315207 0.018729 0.0171086 -1 -1 -1 -1 28 2581 21 6.64007e+06 502320 500653. 1732.36 0.91 0.119022 0.104048 21970 115934 -1 2231 19 1018 2155 132770 30621 4.27588 4.27588 -130.562 -4.27588 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0157386 0.0141662 147 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.20 vpr 64.39 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29800 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2164 893 10263 2683 6663 917 64.4 MiB 0.06 0.00 4.3277 3.5273 -108.396 -3.5273 3.5273 0.24 0.000311698 0.000287949 0.0177608 0.0162611 -1 -1 -1 -1 32 1749 18 6.64007e+06 288834 554710. 1919.41 0.91 0.101392 0.0881871 22834 132086 -1 1533 20 784 1238 71387 17120 2.77177 2.77177 -103.397 -2.77177 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0129162 0.0115158 107 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 1.81 vpr 64.39 MiB -1 -1 0.13 17908 1 0.03 -1 -1 29836 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2117 911 17732 5400 9784 2548 64.4 MiB 0.08 0.00 5.13641 4.09995 -112.419 -4.09995 4.09995 0.28 0.000286035 0.000255044 0.0231712 0.0210843 -1 -1 -1 -1 28 1992 21 6.64007e+06 477204 500653. 1732.36 0.38 0.0635272 0.0563098 21970 115934 -1 1710 18 975 1883 102536 25450 2.74837 2.74837 -101.654 -2.74837 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0128309 0.0114514 110 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 2.43 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 30 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 29 32 355 287 1 198 91 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2698 1076 9679 2548 6094 1037 64.8 MiB 0.06 0.00 5.53367 4.61203 -130.625 -4.61203 4.61203 0.23 0.000338658 0.000311571 0.0192196 0.0176251 -1 -1 -1 -1 32 2459 22 6.64007e+06 376740 554710. 1919.41 0.99 0.129037 0.112919 22834 132086 -1 2073 18 1299 1977 111378 28075 3.37503 3.37503 -116.489 -3.37503 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0154722 0.0139398 146 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 1.96 vpr 64.73 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29784 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1949 947 7639 1677 5525 437 64.7 MiB 0.05 0.00 5.24456 4.53352 -139.004 -4.53352 4.53352 0.25 0.000332698 0.00030496 0.0143265 0.0131711 -1 -1 -1 -1 32 2009 19 6.64007e+06 339066 554710. 1919.41 0.49 0.0942014 0.0834076 22834 132086 -1 1774 21 1241 1905 118138 28466 3.74782 3.74782 -129.815 -3.74782 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0215813 0.0193967 135 54 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 1.84 vpr 64.76 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29752 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 25.2 MiB 0.13 2440 1011 14498 3923 8676 1899 64.8 MiB 0.08 0.00 5.77607 4.82681 -139.307 -4.82681 4.82681 0.23 0.000370343 0.000327299 0.0234924 0.0214514 -1 -1 -1 -1 32 2255 19 6.64007e+06 426972 554710. 1919.41 0.34 0.0668056 0.0594183 22834 132086 -1 1902 18 994 1738 88852 22474 4.06723 4.06723 -132.101 -4.06723 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0149293 0.013428 136 51 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.78 vpr 64.15 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29784 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 24.5 MiB 0.22 1928 770 5189 970 3673 546 64.2 MiB 0.03 0.00 5.21395 4.75032 -127.226 -4.75032 4.75032 0.24 0.000282943 0.000258953 0.0093242 0.0085679 -1 -1 -1 -1 28 2312 21 6.64007e+06 276276 500653. 1732.36 1.22 0.102145 0.0888686 21970 115934 -1 1617 18 803 1095 74187 19482 3.17683 3.17683 -111.986 -3.17683 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0160528 0.0144005 107 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.48 vpr 64.59 MiB -1 -1 0.12 18292 1 0.03 -1 -1 30320 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 31 32 319 272 1 169 86 17 17 289 -1 unnamed_device 25.1 MiB 0.12 2149 981 13694 3750 8080 1864 64.6 MiB 0.07 0.00 4.95096 4.00653 -127.945 -4.00653 4.00653 0.23 0.000296843 0.000271587 0.0257813 0.023674 -1 -1 -1 -1 32 1939 22 6.64007e+06 288834 554710. 1919.41 0.92 0.12807 0.111978 22834 132086 -1 1753 19 1043 1582 90723 22601 3.22583 3.22583 -119.839 -3.22583 0 0 701300. 2426.64 0.03 0.03 0.13 -1 -1 0.03 0.0144012 0.0128713 116 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.22 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30116 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2322 929 9548 2022 6797 729 64.6 MiB 0.05 0.00 4.3867 3.5433 -97.7345 -3.5433 3.5433 0.23 0.000315462 0.000287317 0.0152887 0.0139914 -1 -1 -1 -1 32 1970 20 6.64007e+06 452088 554710. 1919.41 0.89 0.111736 0.0971106 22834 132086 -1 1630 17 815 1410 71619 17962 2.64857 2.64857 -94.6457 -2.64857 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0141874 0.0127433 128 57 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.61 vpr 64.55 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29804 -1 -1 39 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1932 905 16515 4803 9135 2577 64.5 MiB 0.12 0.00 5.16736 4.19576 -104.869 -4.19576 4.19576 0.25 0.000632614 0.000587453 0.0403436 0.0370875 -1 -1 -1 -1 26 2022 22 6.64007e+06 489762 477104. 1650.88 1.09 0.130341 0.115208 21682 110474 -1 1822 20 1097 2083 117673 28230 3.55243 3.55243 -105.89 -3.55243 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0187176 0.0166672 122 27 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 1.68 vpr 64.55 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29788 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 30 32 317 269 1 152 83 17 17 289 -1 unnamed_device 24.5 MiB 0.07 1992 820 8003 2033 5428 542 64.5 MiB 0.05 0.00 4.60481 3.90078 -115.378 -3.90078 3.90078 0.23 0.000302657 0.000277024 0.0153228 0.0140736 -1 -1 -1 -1 32 1752 22 6.64007e+06 263718 554710. 1919.41 0.34 0.0557821 0.0493271 22834 132086 -1 1562 19 1039 1837 109271 27109 2.78277 2.78277 -104.529 -2.78277 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0140966 0.0125822 115 63 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 2.41 vpr 64.68 MiB -1 -1 0.17 18052 1 0.03 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2267 1041 7728 1594 5511 623 64.7 MiB 0.05 0.00 4.51839 3.97836 -130.923 -3.97836 3.97836 0.23 0.000320385 0.000287586 0.0151298 0.0139414 -1 -1 -1 -1 28 2450 20 6.64007e+06 326508 500653. 1732.36 0.96 0.121822 0.106713 21970 115934 -1 2048 20 1250 1844 127691 29643 3.29503 3.29503 -126.978 -3.29503 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0153238 0.0137008 127 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.43 vpr 64.59 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29920 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2060 1087 14716 3609 8495 2612 64.6 MiB 0.08 0.00 5.23607 4.60801 -131.451 -4.60801 4.60801 0.24 0.000305422 0.000279931 0.0231359 0.0211931 -1 -1 -1 -1 30 2215 19 6.64007e+06 464646 526063. 1820.29 1.06 0.136734 0.120549 22546 126617 -1 1958 23 1056 1969 119309 26451 3.47322 3.47322 -117.132 -3.47322 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0158791 0.0141618 134 4 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 1.92 vpr 64.80 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29936 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 350 275 1 209 93 17 17 289 -1 unnamed_device 25.0 MiB 0.15 2681 1037 9753 2581 5955 1217 64.8 MiB 0.07 0.00 6.01073 5.18024 -156.404 -5.18024 5.18024 0.24 0.000336837 0.000308978 0.0215031 0.0199073 -1 -1 -1 -1 32 2480 23 6.64007e+06 364182 554710. 1919.41 0.42 0.0729427 0.0649708 22834 132086 -1 2043 17 1212 1843 105388 26002 4.27189 4.27189 -143.17 -4.27189 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0155817 0.0140506 151 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 2.78 vpr 64.84 MiB -1 -1 0.16 18052 1 0.03 -1 -1 29820 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2633 929 18196 5476 8417 4303 64.8 MiB 0.08 0.00 5.68167 4.5876 -139.046 -4.5876 4.5876 0.23 0.000362423 0.000326394 0.0296245 0.0269269 -1 -1 -1 -1 34 2649 32 6.64007e+06 464646 585099. 2024.56 1.32 0.155351 0.136509 23122 138558 -1 1938 22 1357 2352 167798 52522 3.76663 3.76663 -127.254 -3.76663 0 0 742403. 2568.87 0.03 0.05 0.08 -1 -1 0.03 0.0180392 0.0161401 143 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 2.96 vpr 64.88 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30224 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66436 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2914 1203 17817 4991 10319 2507 64.9 MiB 0.09 0.00 5.86707 4.47484 -142.898 -4.47484 4.47484 0.23 0.000359612 0.000326009 0.0272184 0.0247497 -1 -1 -1 -1 26 2975 23 6.64007e+06 539994 477104. 1650.88 1.56 0.12861 0.113349 21682 110474 -1 2473 21 1636 3093 192512 45419 3.88183 3.88183 -138.131 -3.88183 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.017884 0.0159925 147 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 1.71 vpr 64.47 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29852 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66020 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 24.3 MiB 0.07 1992 827 11963 3673 6023 2267 64.5 MiB 0.06 0.00 4.80601 3.86158 -112.965 -3.86158 3.86158 0.23 0.000449703 0.000425374 0.0237691 0.022019 -1 -1 -1 -1 32 1758 20 6.64007e+06 263718 554710. 1919.41 0.33 0.060739 0.0541405 22834 132086 -1 1584 20 900 1546 91449 21952 2.74357 2.74357 -100.335 -2.74357 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.015396 0.0137804 109 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 2.41 vpr 64.81 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30148 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 24.9 MiB 0.11 2027 1031 14741 4291 8504 1946 64.8 MiB 0.09 0.00 5.46127 4.75724 -139.41 -4.75724 4.75724 0.25 0.00034081 0.000312004 0.0309057 0.0283983 -1 -1 -1 -1 28 2442 23 6.64007e+06 339066 500653. 1732.36 0.80 0.136583 0.120041 21970 115934 -1 2156 21 1668 2701 170774 41593 4.08103 4.08103 -135.525 -4.08103 0 0 612192. 2118.31 0.04 0.08 0.11 -1 -1 0.04 0.0328061 0.0292899 147 63 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 2.69 vpr 64.76 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30236 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2563 1179 8401 1845 5726 830 64.8 MiB 0.05 0.00 6.4762 5.43878 -158.127 -5.43878 5.43878 0.24 0.000339119 0.000311131 0.0150216 0.0138245 -1 -1 -1 -1 28 2965 25 6.64007e+06 376740 500653. 1732.36 1.19 0.120148 0.105622 21970 115934 -1 2377 19 1306 2106 150947 36744 4.09669 4.09669 -142.216 -4.09669 0 0 612192. 2118.31 0.04 0.07 0.09 -1 -1 0.04 0.0253964 0.0228129 145 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 2.49 vpr 64.77 MiB -1 -1 0.15 17852 1 0.03 -1 -1 30196 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 24.9 MiB 0.17 2657 1228 12698 3369 8227 1102 64.8 MiB 0.07 0.00 6.49901 5.45438 -153.019 -5.45438 5.45438 0.24 0.000328689 0.000301312 0.0205704 0.0188312 -1 -1 -1 -1 28 2672 21 6.64007e+06 439530 500653. 1732.36 0.93 0.119834 0.105177 21970 115934 -1 2273 20 1393 2173 133451 33025 4.68168 4.68168 -150.535 -4.68168 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.018244 0.0164405 152 47 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.04 vpr 64.82 MiB -1 -1 0.19 17908 1 0.03 -1 -1 30140 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2368 1088 19124 5773 11033 2318 64.8 MiB 0.10 0.00 5.27727 4.45304 -133.741 -4.45304 4.45304 0.33 0.000340028 0.000311762 0.0308833 0.0282403 -1 -1 -1 -1 32 2027 17 6.64007e+06 477204 554710. 1919.41 0.34 0.0763852 0.0678982 22834 132086 -1 1840 18 828 1458 87897 20192 2.99843 2.99843 -114.489 -2.99843 0 0 701300. 2426.64 0.03 0.03 0.09 -1 -1 0.03 0.0156678 0.0141019 144 83 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 2.56 vpr 64.62 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29764 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 25.2 MiB 0.12 2717 1084 11771 2992 7832 947 64.6 MiB 0.08 0.00 6.07747 5.03001 -142.129 -5.03001 5.03001 0.24 0.000341787 0.000313273 0.0256136 0.0235617 -1 -1 -1 -1 32 2400 18 6.64007e+06 313950 554710. 1919.41 1.03 0.132022 0.115711 22834 132086 -1 2204 17 1217 2211 124731 29809 3.86283 3.86283 -134.875 -3.86283 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152233 0.0137184 141 57 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 1.75 vpr 64.43 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29736 -1 -1 38 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 29 32 378 310 1 177 99 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2434 959 18567 5802 9719 3046 64.4 MiB 0.10 0.00 5.08141 4.25424 -118.37 -4.25424 4.25424 0.24 0.000348555 0.000319788 0.0336972 0.0310577 -1 -1 -1 -1 32 1868 18 6.64007e+06 477204 554710. 1919.41 0.35 0.0778854 0.0696741 22834 132086 -1 1742 19 1067 1824 102169 25222 2.96197 2.96197 -106.132 -2.96197 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0166391 0.0149238 137 85 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 1.62 vpr 64.12 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29928 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65656 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1776 737 8003 1763 5996 244 64.1 MiB 0.04 0.00 4.47141 3.88758 -112.726 -3.88758 3.88758 0.24 0.000260941 0.000238488 0.0130657 0.0119905 -1 -1 -1 -1 28 1687 18 6.64007e+06 238602 500653. 1732.36 0.33 0.0470139 0.0415744 21970 115934 -1 1415 17 749 1150 66721 17748 2.93797 2.93797 -105.31 -2.93797 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0114493 0.0102428 99 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 1.96 vpr 64.79 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29772 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 25.3 MiB 0.11 2455 1051 10131 2558 6985 588 64.8 MiB 0.06 0.00 5.67067 4.66023 -138.505 -4.66023 4.66023 0.23 0.000342724 0.000314219 0.0174902 0.0160199 -1 -1 -1 -1 32 2099 20 6.64007e+06 439530 554710. 1919.41 0.36 0.0663895 0.058967 22834 132086 -1 1859 21 1036 1822 107535 26414 3.73983 3.73983 -129.269 -3.73983 0 0 701300. 2426.64 0.04 0.07 0.12 -1 -1 0.04 0.0301792 0.0272055 135 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 1.84 vpr 64.88 MiB -1 -1 0.13 17444 1 0.03 -1 -1 30116 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66432 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2786 978 14939 5098 7315 2526 64.9 MiB 0.09 0.00 5.96407 4.77924 -147.588 -4.77924 4.77924 0.23 0.000358013 0.000327645 0.0296295 0.0271703 -1 -1 -1 -1 32 2301 21 6.64007e+06 313950 554710. 1919.41 0.36 0.0769698 0.0685732 22834 132086 -1 1890 22 1749 2967 165614 41703 3.75843 3.75843 -135.029 -3.75843 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0205468 0.0184283 155 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 1.73 vpr 64.52 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66068 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 24.5 MiB 0.14 2060 1019 8999 2097 6268 634 64.5 MiB 0.05 0.00 5.08536 4.17772 -116.047 -4.17772 4.17772 0.23 0.000432787 0.000408561 0.0145659 0.0133905 -1 -1 -1 -1 26 2304 22 6.64007e+06 313950 477104. 1650.88 0.31 0.0518409 0.0456961 21682 110474 -1 1979 15 909 1262 86214 21433 3.35623 3.35623 -114.421 -3.35623 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0116363 0.0104526 117 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 2.18 vpr 63.69 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30320 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65216 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 23.9 MiB 0.04 2077 870 15017 4767 7797 2453 63.7 MiB 0.07 0.00 4.82101 3.80732 -109.576 -3.80732 3.80732 0.25 0.000256941 0.000235154 0.022651 0.0207191 -1 -1 -1 -1 30 1774 18 6.64007e+06 288834 526063. 1820.29 0.87 0.101667 0.0884464 22546 126617 -1 1499 20 971 1627 84799 20654 2.75457 2.75457 -100.629 -2.75457 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0128585 0.011425 110 4 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 3.07 vpr 64.81 MiB -1 -1 0.13 17908 1 0.03 -1 -1 30380 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 348 274 1 211 94 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2693 1116 13726 3780 8585 1361 64.8 MiB 0.09 0.00 6.31933 5.03147 -151.742 -5.03147 5.03147 0.26 0.000340195 0.000312031 0.0263611 0.0242555 -1 -1 -1 -1 26 3082 38 6.64007e+06 376740 477104. 1650.88 1.57 0.135113 0.119158 21682 110474 -1 2413 18 1436 1908 121395 30312 4.28008 4.28008 -150.977 -4.28008 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0157398 0.0141925 151 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 3.12 vpr 64.84 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29864 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66400 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 24.9 MiB 0.23 2455 1138 17726 5560 9419 2747 64.8 MiB 0.09 0.00 6.43337 5.25633 -153.723 -5.25633 5.25633 0.24 0.00033534 0.000306284 0.0271419 0.0248337 -1 -1 -1 -1 28 2970 26 6.64007e+06 464646 500653. 1732.36 1.21 0.137274 0.12092 21970 115934 -1 2282 20 1151 1899 136719 33457 4.29708 4.29708 -142.574 -4.29708 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176497 0.0158217 157 56 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.77 vpr 64.82 MiB -1 -1 0.12 17908 1 0.03 -1 -1 30172 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2789 1287 17058 4718 10081 2259 64.8 MiB 0.11 0.00 6.50947 5.53806 -146.188 -5.53806 5.53806 0.34 0.000845223 0.000792687 0.0343809 0.0317838 -1 -1 -1 -1 30 2736 22 6.64007e+06 539994 526063. 1820.29 1.15 0.160837 0.141766 22546 126617 -1 2231 22 1148 2273 135275 29822 4.48228 4.48228 -138.994 -4.48228 0 0 666494. 2306.21 0.04 0.10 0.10 -1 -1 0.04 0.0419782 0.0376554 162 3 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 1.72 vpr 64.60 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30204 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 30 32 316 264 1 162 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2263 842 16298 4881 8912 2505 64.6 MiB 0.08 0.00 4.4797 3.59647 -102.523 -3.59647 3.59647 0.23 0.000307307 0.000280621 0.0251614 0.0229662 -1 -1 -1 -1 32 1785 20 6.64007e+06 452088 554710. 1919.41 0.34 0.0656727 0.0582729 22834 132086 -1 1466 19 1042 1950 89350 23678 2.76377 2.76377 -94.1745 -2.76377 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0187442 0.0167254 124 52 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.16 vpr 63.77 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30148 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 27 32 255 219 1 132 82 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1707 787 11296 3601 6010 1685 63.8 MiB 0.05 0.00 4.4859 3.4653 -97.6029 -3.4653 3.4653 0.23 0.000259889 0.000238275 0.0182365 0.0167452 -1 -1 -1 -1 32 1511 19 6.64007e+06 288834 554710. 1919.41 0.87 0.102496 0.0888358 22834 132086 -1 1326 21 866 1379 78231 19198 2.71397 2.71397 -92.9443 -2.71397 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0130114 0.0115292 100 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 2.68 vpr 65.09 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30116 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66648 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 25.2 MiB 0.14 3118 1444 14498 4090 9211 1197 65.1 MiB 0.10 0.00 5.55196 4.5101 -140.741 -4.5101 4.5101 0.23 0.000398638 0.000366161 0.0272928 0.0249945 -1 -1 -1 -1 30 3465 22 6.64007e+06 426972 526063. 1820.29 1.05 0.136378 0.119849 22546 126617 -1 2722 21 1607 2624 142172 32764 3.65863 3.65863 -130.646 -3.65863 0 0 666494. 2306.21 0.04 0.06 0.12 -1 -1 0.04 0.0258273 0.0233244 176 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 2.80 vpr 64.80 MiB -1 -1 0.13 18044 1 0.03 -1 -1 29768 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 25.2 MiB 0.23 2629 1132 9336 2424 6148 764 64.8 MiB 0.06 0.00 6.80513 5.51727 -161.811 -5.51727 5.51727 0.24 0.000362914 0.000323191 0.0180721 0.016584 -1 -1 -1 -1 28 2466 20 6.64007e+06 339066 500653. 1732.36 1.25 0.174434 0.153503 21970 115934 -1 2101 19 1237 2000 130018 29929 4.16568 4.16568 -143.37 -4.16568 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0161927 0.0145835 151 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 1.88 vpr 64.64 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30324 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 331 280 1 174 87 17 17 289 -1 unnamed_device 24.9 MiB 0.20 2094 1015 14679 4364 8389 1926 64.6 MiB 0.08 0.00 5.09416 4.33009 -141.29 -4.33009 4.33009 0.24 0.000312539 0.000284692 0.0257348 0.0234754 -1 -1 -1 -1 32 1899 18 6.64007e+06 288834 554710. 1919.41 0.32 0.066431 0.0591023 22834 132086 -1 1719 19 831 1221 79113 18762 3.36323 3.36323 -128.856 -3.36323 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0147407 0.0132364 128 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.01 vpr 64.66 MiB -1 -1 0.12 18056 1 0.04 -1 -1 29908 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 24.7 MiB 0.07 2458 1067 12164 3189 8279 696 64.7 MiB 0.07 0.00 6.37057 5.24988 -134.918 -5.24988 5.24988 0.23 0.000320631 0.000287726 0.018401 0.0167501 -1 -1 -1 -1 26 2581 23 6.64007e+06 452088 477104. 1650.88 0.42 0.0642136 0.0567882 21682 110474 -1 2228 21 1099 1899 121927 29754 3.83082 3.83082 -126.562 -3.83082 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.02192 0.0194781 133 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 2.30 vpr 64.30 MiB -1 -1 0.14 17892 1 0.03 -1 -1 29868 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 373 294 1 196 102 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2316 1109 11050 2358 7802 890 64.3 MiB 0.06 0.00 5.64915 5.02635 -128.904 -5.02635 5.02635 0.24 0.00034588 0.00031657 0.0180672 0.0165722 -1 -1 -1 -1 30 2070 21 6.64007e+06 489762 526063. 1820.29 0.90 0.13078 0.114565 22546 126617 -1 1846 16 918 1501 68384 17532 4.07422 4.07422 -121.604 -4.07422 0 0 666494. 2306.21 0.03 0.03 0.08 -1 -1 0.03 0.0168693 0.0152914 151 50 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.26 vpr 64.05 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29844 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65584 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 24.6 MiB 0.07 2399 1037 15848 4616 8805 2427 64.0 MiB 0.08 0.00 4.4759 3.71089 -106.291 -3.71089 3.71089 0.24 0.000314293 0.000287759 0.0254439 0.0233391 -1 -1 -1 -1 32 2018 20 6.64007e+06 452088 554710. 1919.41 0.89 0.106875 0.0936934 22834 132086 -1 1894 20 997 1743 113167 25894 2.73777 2.73777 -99.0335 -2.73777 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0155864 0.013987 130 51 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 2.58 vpr 64.82 MiB -1 -1 0.16 18048 1 0.03 -1 -1 29816 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2711 1355 17159 4707 10238 2214 64.8 MiB 0.11 0.00 6.39133 5.42973 -168.16 -5.42973 5.42973 0.24 0.000333297 0.000305473 0.0305336 0.027931 -1 -1 -1 -1 32 2899 17 6.64007e+06 389298 554710. 1919.41 0.97 0.119619 0.104995 22834 132086 -1 2528 21 1636 2593 168950 38601 4.20469 4.20469 -151.273 -4.20469 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.017333 0.015535 155 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 3.02 vpr 64.88 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29784 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2637 1151 20606 6244 9655 4707 64.9 MiB 0.09 0.00 5.13347 4.30924 -132.442 -4.30924 4.30924 0.26 0.000366994 0.000335366 0.0367992 0.0340036 -1 -1 -1 -1 32 2462 42 6.64007e+06 527436 554710. 1919.41 1.55 0.189485 0.167465 22834 132086 -1 1986 17 1183 1864 116056 30310 3.22157 3.22157 -117.993 -3.22157 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0155732 0.014057 151 62 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.21 vpr 64.13 MiB -1 -1 0.12 18056 1 0.02 -1 -1 29828 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1582 689 11948 3112 7844 992 64.1 MiB 0.06 0.00 4.48041 4.01678 -109.438 -4.01678 4.01678 0.24 0.000455205 0.000431544 0.0247681 0.0228668 -1 -1 -1 -1 32 1385 20 6.64007e+06 238602 554710. 1919.41 0.86 0.10574 0.0924354 22834 132086 -1 1290 19 791 1195 77092 18865 2.88077 2.88077 -97.6008 -2.88077 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0128196 0.0114748 93 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.41 vpr 64.59 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29936 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 310 266 1 175 90 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2235 1059 15969 4938 9075 1956 64.6 MiB 0.07 0.00 5.20036 4.23876 -128.495 -4.23876 4.23876 0.24 0.000299718 0.000274504 0.0251125 0.0229545 -1 -1 -1 -1 32 2001 23 6.64007e+06 326508 554710. 1919.41 1.01 0.131817 0.114808 22834 132086 -1 1797 18 929 1290 89628 20456 3.08203 3.08203 -115.313 -3.08203 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0136287 0.0122168 123 58 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.97 vpr 64.70 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29924 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 31 32 326 261 1 177 106 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2343 905 18606 5361 10083 3162 64.7 MiB 0.09 0.00 5.80407 4.54858 -124.201 -4.54858 4.54858 0.24 0.000312841 0.000285299 0.0289889 0.0265187 -1 -1 -1 -1 28 2713 40 6.64007e+06 539994 500653. 1732.36 1.50 0.168338 0.147939 21970 115934 -1 2157 23 1491 2776 199878 49701 3.88503 3.88503 -124.264 -3.88503 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0168966 0.0150698 138 33 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 1.83 vpr 64.50 MiB -1 -1 0.16 17672 1 0.03 -1 -1 29820 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66044 29 32 262 224 1 168 87 17 17 289 -1 unnamed_device 24.5 MiB 0.14 1937 1016 11799 3172 7074 1553 64.5 MiB 0.06 0.00 4.85327 4.04852 -112.319 -4.04852 4.04852 0.23 0.000270092 0.000247629 0.0179409 0.0164448 -1 -1 -1 -1 26 2153 18 6.64007e+06 326508 477104. 1650.88 0.29 0.0517776 0.0458058 21682 110474 -1 1918 18 889 1186 72681 17751 3.29122 3.29122 -107.623 -3.29122 0 0 585099. 2024.56 0.04 0.06 0.09 -1 -1 0.04 0.0283681 0.0254054 116 31 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.23 vpr 64.48 MiB -1 -1 0.10 18052 1 0.02 -1 -1 29788 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1781 947 10883 2848 6498 1537 64.5 MiB 0.05 0.00 4.52641 4.02095 -125.546 -4.02095 4.02095 0.23 0.00027826 0.000254627 0.0185587 0.0170438 -1 -1 -1 -1 30 1980 22 6.64007e+06 238602 526063. 1820.29 0.93 0.111158 0.096955 22546 126617 -1 1771 19 1115 1979 106566 25643 2.79377 2.79377 -111.145 -2.79377 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0130158 0.0116049 111 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.54 vpr 64.81 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29768 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2560 1034 12876 3096 8656 1124 64.8 MiB 0.07 0.00 4.91801 4.20195 -124.421 -4.20195 4.20195 0.24 0.000360523 0.000329806 0.0257987 0.023957 -1 -1 -1 -1 32 2018 22 6.64007e+06 502320 554710. 1919.41 1.02 0.149989 0.131986 22834 132086 -1 1831 17 1180 1846 100223 25917 2.96877 2.96877 -113.134 -2.96877 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152364 0.0137279 141 64 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.41 vpr 64.49 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29848 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1957 849 12568 3841 6272 2455 64.5 MiB 0.08 0.00 4.49165 3.90436 -116.108 -3.90436 3.90436 0.25 0.000270822 0.000247709 0.0271462 0.0251465 -1 -1 -1 -1 32 1843 22 6.64007e+06 313950 554710. 1919.41 0.99 0.126567 0.110341 22834 132086 -1 1628 20 997 1467 92295 22084 2.90603 2.90603 -105.107 -2.90603 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0130624 0.0116593 113 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.19 vpr 64.75 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2312 1072 14671 3700 9355 1616 64.8 MiB 0.07 0.00 4.37944 3.68167 -112.793 -3.68167 3.68167 0.23 0.000328231 0.000299444 0.0224555 0.0205477 -1 -1 -1 -1 26 2288 20 6.64007e+06 464646 477104. 1650.88 0.82 0.108143 0.0950909 21682 110474 -1 1944 21 1079 1949 120319 27849 2.90097 2.90097 -107.811 -2.90097 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0169673 0.0152162 131 57 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 1.81 vpr 64.74 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30212 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 24.7 MiB 0.13 2484 1002 10815 2483 7746 586 64.7 MiB 0.06 0.00 4.7433 4.0221 -125.424 -4.0221 4.0221 0.24 0.000397566 0.000334154 0.0194519 0.0177821 -1 -1 -1 -1 30 2069 23 6.64007e+06 452088 526063. 1820.29 0.35 0.0685942 0.0607519 22546 126617 -1 1876 21 1394 2192 129190 30545 3.12957 3.12957 -117.777 -3.12957 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0174038 0.015566 145 91 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 1.76 vpr 64.49 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29744 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1814 857 7770 1801 5584 385 64.5 MiB 0.10 0.00 3.8549 3.3869 -105.248 -3.3869 3.3869 0.26 0.000808908 0.000752472 0.036892 0.0342639 -1 -1 -1 -1 30 1717 23 6.64007e+06 251160 526063. 1820.29 0.36 0.0758761 0.0680954 22546 126617 -1 1505 18 707 1177 69640 16846 2.62037 2.62037 -101.98 -2.62037 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0131102 0.0117754 111 57 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 1.88 vpr 64.57 MiB -1 -1 0.11 18436 1 0.02 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 290 244 1 177 89 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2414 1035 16127 4715 9194 2218 64.6 MiB 0.08 0.00 5.19407 4.38701 -135.203 -4.38701 4.38701 0.30 0.000285817 0.00026167 0.0250029 0.0228938 -1 -1 -1 -1 28 2331 19 6.64007e+06 313950 500653. 1732.36 0.35 0.061641 0.0547906 21970 115934 -1 1998 18 1184 1766 112327 26702 3.18183 3.18183 -121.919 -3.18183 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0156723 0.0140089 123 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.90 vpr 64.68 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29532 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2494 951 15617 4720 8033 2864 64.7 MiB 0.08 0.00 5.8041 4.77338 -128.314 -4.77338 4.77338 0.24 0.000322955 0.000295402 0.0258152 0.0235919 -1 -1 -1 -1 30 2411 22 6.64007e+06 351624 526063. 1820.29 1.43 0.116548 0.102484 22546 126617 -1 1780 20 1025 1564 87363 22048 3.81583 3.81583 -122.51 -3.81583 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0154909 0.0139488 138 30 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.09 vpr 64.66 MiB -1 -1 0.14 18044 1 0.03 -1 -1 29808 -1 -1 36 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2020 1028 6757 1470 4618 669 64.7 MiB 0.04 0.00 4.83347 4.36984 -119.357 -4.36984 4.36984 0.24 0.000308469 0.000282152 0.0111219 0.0102283 -1 -1 -1 -1 26 2136 15 6.64007e+06 452088 477104. 1650.88 0.68 0.0886405 0.0772855 21682 110474 -1 1886 18 837 1482 89240 21546 3.02743 3.02743 -103.989 -3.02743 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0143245 0.0128477 129 55 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.68 vpr 64.55 MiB -1 -1 0.22 18440 1 0.03 -1 -1 30148 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66104 32 32 393 312 1 213 93 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2426 1118 15843 4746 8389 2708 64.6 MiB 0.09 0.00 6.27101 5.72815 -176.849 -5.72815 5.72815 0.24 0.000376256 0.00034593 0.0315166 0.028967 -1 -1 -1 -1 32 2546 19 6.64007e+06 364182 554710. 1919.41 1.03 0.159075 0.140221 22834 132086 -1 2255 20 1391 2068 146331 34168 4.58628 4.58628 -155.397 -4.58628 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0179246 0.0161235 158 65 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.12 vpr 64.08 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29692 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 24.3 MiB 0.03 1660 747 7221 1683 5260 278 64.1 MiB 0.04 0.00 3.9861 3.49806 -100.112 -3.49806 3.49806 0.24 0.000247913 0.000227211 0.0112366 0.0103119 -1 -1 -1 -1 30 1664 18 6.64007e+06 263718 526063. 1820.29 0.90 0.0946062 0.0821045 22546 126617 -1 1301 16 550 893 50864 12892 2.64857 2.64857 -91.973 -2.64857 0 0 666494. 2306.21 0.03 0.02 0.07 -1 -1 0.03 0.0106208 0.00956507 100 4 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 1.94 vpr 64.96 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29708 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66516 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2451 1087 18431 5518 10395 2518 65.0 MiB 0.11 0.00 5.50696 4.44233 -144.688 -4.44233 4.44233 0.23 0.00038496 0.000353611 0.0389541 0.0358696 -1 -1 -1 -1 32 2221 20 6.64007e+06 464646 554710. 1919.41 0.39 0.0947235 0.0847517 22834 132086 -1 1905 18 1214 1798 108778 25534 3.75862 3.75862 -135.309 -3.75862 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0201159 0.0182483 146 90 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 1.77 vpr 64.17 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29824 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 376 318 1 155 82 17 17 289 -1 unnamed_device 24.4 MiB 0.12 1766 955 11830 3130 7536 1164 64.2 MiB 0.06 0.00 4.1133 3.5251 -125.052 -3.5251 3.5251 0.24 0.000330759 0.000302081 0.0243994 0.022357 -1 -1 -1 -1 32 1865 20 6.64007e+06 226044 554710. 1919.41 0.36 0.0677556 0.0602023 22834 132086 -1 1684 21 1128 1645 110610 25795 2.66437 2.66437 -115.654 -2.66437 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0168254 0.0150063 116 96 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.72 vpr 64.39 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29776 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2247 944 17427 4836 9376 3215 64.4 MiB 0.13 0.00 4.122 4.04884 -119.999 -4.04884 4.04884 0.23 0.000618313 0.000568585 0.0416241 0.038231 -1 -1 -1 -1 28 2356 26 6.64007e+06 439530 500653. 1732.36 1.26 0.157839 0.139557 21970 115934 -1 1861 17 982 1579 105965 27943 3.13537 3.13537 -108.58 -3.13537 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.015124 0.0136237 134 60 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 2.66 vpr 64.63 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29808 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66180 32 32 396 299 1 236 97 17 17 289 -1 unnamed_device 25.2 MiB 0.18 3069 1434 11863 3029 7657 1177 64.6 MiB 0.10 0.00 7.74409 6.65703 -196.862 -6.65703 6.65703 0.23 0.000392613 0.000361026 0.02616 0.0242474 -1 -1 -1 -1 30 2977 29 6.64007e+06 414414 526063. 1820.29 1.12 0.168442 0.148951 22546 126617 -1 2525 20 1541 2230 119707 29396 5.29994 5.29994 -175.636 -5.29994 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.019447 0.0175604 178 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 1.65 vpr 64.08 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30200 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 30 32 224 207 1 138 85 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1779 825 13663 4108 8029 1526 64.1 MiB 0.05 0.00 3.77619 3.29107 -101.735 -3.29107 3.29107 0.23 0.000232903 0.000213388 0.0185332 0.0169707 -1 -1 -1 -1 26 1653 18 6.64007e+06 288834 477104. 1650.88 0.27 0.0489107 0.0432584 21682 110474 -1 1457 16 625 800 52338 13195 2.38617 2.38617 -94.87 -2.38617 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00980788 0.00878496 93 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.23 vpr 64.48 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30180 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1551 715 8831 2097 6321 413 64.5 MiB 0.04 0.00 4.64461 4.13192 -117.713 -4.13192 4.13192 0.23 0.000283608 0.000257957 0.0163788 0.0150423 -1 -1 -1 -1 32 1455 18 6.64007e+06 238602 554710. 1919.41 0.87 0.0917998 0.0799261 22834 132086 -1 1299 17 693 1155 74739 18315 2.98597 2.98597 -106.773 -2.98597 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0161838 0.0144625 95 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 1.80 vpr 64.14 MiB -1 -1 0.21 17672 1 0.03 -1 -1 29604 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65676 32 32 296 247 1 157 87 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2105 944 14103 4753 7503 1847 64.1 MiB 0.07 0.00 4.1763 3.40707 -111.974 -3.40707 3.40707 0.23 0.000441972 0.000415373 0.023287 0.0213172 -1 -1 -1 -1 32 1961 19 6.64007e+06 288834 554710. 1919.41 0.34 0.0611781 0.0542074 22834 132086 -1 1733 21 1059 1936 116096 28016 2.87177 2.87177 -111.073 -2.87177 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0147393 0.0131377 119 34 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.33 vpr 64.04 MiB -1 -1 0.10 18056 1 0.02 -1 -1 29888 -1 -1 31 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65572 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 24.9 MiB 0.03 1494 591 13153 4635 5984 2534 64.0 MiB 0.05 0.00 4.0913 3.45027 -80.5708 -3.45027 3.45027 0.25 0.000229 0.00020925 0.0176622 0.0161781 -1 -1 -1 -1 28 1498 20 6.64007e+06 389298 500653. 1732.36 1.02 0.117375 0.102145 21970 115934 -1 1204 20 767 1265 67303 18216 2.69777 2.69777 -76.5165 -2.69777 0 0 612192. 2118.31 0.03 0.03 0.08 -1 -1 0.03 0.0133537 0.0119732 93 29 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 2.42 vpr 64.81 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29772 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2264 1161 14323 4312 8018 1993 64.8 MiB 0.10 0.00 5.34776 4.34527 -135.212 -4.34527 4.34527 0.25 0.000775451 0.00072278 0.0348073 0.0320495 -1 -1 -1 -1 26 2998 22 6.64007e+06 301392 477104. 1650.88 0.83 0.118776 0.10489 21682 110474 -1 2499 16 1260 2258 137367 32949 3.70982 3.70982 -129.996 -3.70982 0 0 585099. 2024.56 0.04 0.07 0.07 -1 -1 0.04 0.0305887 0.02766 137 72 -1 -1 -1 -1 +fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 3.06 vpr 64.97 MiB -1 -1 0.14 18056 1 0.04 -1 -1 30020 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66532 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 25.6 MiB 0.11 2647 843 12949 3259 8450 1240 65.0 MiB 0.09 0.00 4.62461 4.03784 -124.693 -4.03784 4.03784 0.24 0.000379639 0.000344151 0.0272347 0.0251462 -1 -1 -1 -1 28 2404 29 6.64007e+06 527436 500653. 1732.36 1.36 0.169941 0.15025 21970 115934 -1 1842 19 1533 2462 139710 38054 3.40377 3.40377 -121.42 -3.40377 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0196062 0.0175902 148 90 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 3.08 vpr 64.26 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29560 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 32 32 354 285 1 202 100 17 17 289 -1 unnamed_device 24.5 MiB 0.11 2680 1148 17500 5750 8438 3312 64.3 MiB 0.09 0.00 6.6478 5.42989 -160.249 -5.42989 5.42989 0.24 0.000335393 0.000306568 0.0277456 0.0253704 -1 -1 -1 -1 30 2512 22 6.65987e+06 456408 526063. 1820.29 1.56 0.126519 0.111713 22546 126617 -1 2013 18 1144 1889 100010 26167 4.13851 4.13851 -142.958 -4.13851 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0214642 0.0194976 152 50 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.48 vpr 64.32 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29772 -1 -1 30 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2387 1221 13961 4223 7808 1930 64.3 MiB 0.10 0.00 5.99396 4.81396 -139.964 -4.81396 4.81396 0.25 0.000338399 0.000310271 0.0346576 0.0320334 -1 -1 -1 -1 28 2736 20 6.65987e+06 380340 500653. 1732.36 1.05 0.148244 0.130948 21970 115934 -1 2265 22 1517 2342 156634 37698 4.01363 4.01363 -138.509 -4.01363 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176982 0.015846 147 63 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 1.88 vpr 64.51 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30216 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 32 32 299 247 1 188 94 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2525 994 9892 2479 6892 521 64.5 MiB 0.06 0.00 5.48484 4.34823 -112.31 -4.34823 4.34823 0.24 0.000492363 0.000456063 0.0191802 0.0176607 -1 -1 -1 -1 26 2792 43 6.65987e+06 380340 477104. 1650.88 0.57 0.0721775 0.0637459 21682 110474 -1 2032 20 1364 1969 121340 31274 3.49631 3.49631 -112.125 -3.49631 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0150753 0.0135285 129 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.22 vpr 64.45 MiB -1 -1 0.15 18056 1 0.03 -1 -1 30124 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2219 1039 14996 4248 8800 1948 64.4 MiB 0.08 0.00 5.26215 4.26714 -116.661 -4.26714 4.26714 0.24 0.000302092 0.000276833 0.0237687 0.02172 -1 -1 -1 -1 26 2187 23 6.65987e+06 393018 477104. 1650.88 0.82 0.105402 0.0923726 21682 110474 -1 1980 24 1460 2740 181180 44106 3.71485 3.71485 -115.237 -3.71485 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0193045 0.0170988 132 31 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.42 vpr 64.53 MiB -1 -1 0.11 18292 1 0.03 -1 -1 30208 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2401 1053 15203 4130 9477 1596 64.5 MiB 0.08 0.00 5.31844 4.32872 -126.669 -4.32872 4.32872 0.23 0.000320268 0.000292697 0.025632 0.0234395 -1 -1 -1 -1 32 2377 17 6.65987e+06 354984 554710. 1919.41 1.04 0.128557 0.112316 22834 132086 -1 2184 20 1318 2611 177400 41362 3.28085 3.28085 -117.499 -3.28085 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0162517 0.0145872 134 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.21 vpr 64.70 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29604 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 25.2 MiB 0.04 2589 1122 12876 3256 8561 1059 64.7 MiB 0.07 0.00 4.08553 3.2871 -114.846 -3.2871 3.2871 0.24 0.000367425 0.000337979 0.0203682 0.018632 -1 -1 -1 -1 26 2486 22 6.65987e+06 494442 477104. 1650.88 0.84 0.116554 0.102469 21682 110474 -1 2096 17 1159 1903 117864 29212 3.03931 3.03931 -115.398 -3.03931 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.016059 0.0145175 145 58 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.22 vpr 64.25 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30136 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1585 699 13324 5476 6895 953 64.2 MiB 0.06 0.00 4.35015 3.70388 -99.5965 -3.70388 3.70388 0.24 0.000265705 0.000243102 0.0220906 0.0202858 -1 -1 -1 -1 32 1384 19 6.65987e+06 266238 554710. 1919.41 0.86 0.104037 0.0904849 22834 132086 -1 1269 20 872 1519 90801 22733 2.68351 2.68351 -90.0723 -2.68351 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0133136 0.0118923 97 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.19 vpr 64.39 MiB -1 -1 0.12 17284 1 0.02 -1 -1 29624 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2037 1041 15848 4643 9032 2173 64.4 MiB 0.08 0.00 3.96304 3.28184 -98.7666 -3.28184 3.28184 0.23 0.000338791 0.000314774 0.0269531 0.0249084 -1 -1 -1 -1 26 2326 21 6.65987e+06 443730 477104. 1650.88 0.83 0.10049 0.0888051 21682 110474 -1 2048 20 1142 2144 140940 33098 2.61165 2.61165 -95.2482 -2.61165 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0141719 0.012715 123 4 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.35 vpr 64.45 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29784 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 31 32 317 271 1 168 88 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2086 993 10423 2723 6384 1316 64.5 MiB 0.07 0.00 3.77724 3.3699 -115.032 -3.3699 3.3699 0.25 0.000671767 0.000645824 0.0231996 0.0214673 -1 -1 -1 -1 32 1809 20 6.65987e+06 316950 554710. 1919.41 0.92 0.127375 0.111058 22834 132086 -1 1615 20 794 1199 70607 17725 2.71311 2.71311 -106.08 -2.71311 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0328717 0.0293078 117 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.60 vpr 64.36 MiB -1 -1 0.19 17660 1 0.03 -1 -1 29748 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1795 844 9983 2313 7049 621 64.4 MiB 0.06 0.00 4.44435 3.77949 -122.028 -3.77949 3.77949 0.23 0.000293552 0.000268791 0.0198136 0.0182461 -1 -1 -1 -1 32 1846 16 6.65987e+06 240882 554710. 1919.41 0.94 0.121669 0.106343 22834 132086 -1 1731 18 979 1642 97359 24956 2.64251 2.64251 -108.37 -2.64251 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0139297 0.0125035 115 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 1.67 vpr 63.78 MiB -1 -1 0.12 18436 1 0.02 -1 -1 29804 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.9 MiB 0.06 1674 802 13206 4528 6671 2007 63.8 MiB 0.06 0.00 4.47555 3.77152 -109.712 -3.77152 3.77152 0.24 0.000293529 0.000268875 0.0245645 0.0225758 -1 -1 -1 -1 32 1549 21 6.65987e+06 240882 554710. 1919.41 0.31 0.0629295 0.0559363 22834 132086 -1 1379 21 624 931 58999 14595 2.67371 2.67371 -95.9888 -2.67371 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0197524 0.0176291 101 63 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.16 vpr 64.39 MiB -1 -1 0.12 17912 1 0.02 -1 -1 29688 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 24.8 MiB 0.05 2346 870 8343 1986 6056 301 64.4 MiB 0.05 0.00 4.65034 3.60712 -112.822 -3.60712 3.60712 0.23 0.00027589 0.000251814 0.013582 0.0124272 -1 -1 -1 -1 30 2025 25 6.65987e+06 291594 526063. 1820.29 0.87 0.0938097 0.0815367 22546 126617 -1 1544 16 760 1070 57907 15189 2.73385 2.73385 -101.25 -2.73385 0 0 666494. 2306.21 0.02 0.03 0.07 -1 -1 0.02 0.0118484 0.0106631 110 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2535 916 19223 6040 10330 2853 64.3 MiB 0.10 0.00 5.72495 4.44986 -128.732 -4.44986 4.44986 0.31 0.000335278 0.000306305 0.0326129 0.0298459 -1 -1 -1 -1 28 2781 28 6.65987e+06 431052 500653. 1732.36 1.60 0.164036 0.144127 21970 115934 -1 2095 22 1720 2855 211888 56822 3.64231 3.64231 -126.124 -3.64231 0 0 612192. 2118.31 0.02 0.07 0.07 -1 -1 0.02 0.0230006 0.0205473 139 61 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.35 vpr 63.86 MiB -1 -1 0.19 17672 1 0.03 -1 -1 29892 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65388 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 24.3 MiB 0.06 1651 644 11064 3432 5040 2592 63.9 MiB 0.05 0.00 3.69173 2.97053 -85.1657 -2.97053 2.97053 0.23 0.000259807 0.000238065 0.0167708 0.015379 -1 -1 -1 -1 32 1255 21 6.65987e+06 291594 554710. 1919.41 0.93 0.10113 0.0875946 22834 132086 -1 1067 19 701 1169 54274 15412 2.52431 2.52431 -81.3486 -2.52431 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0133753 0.0119419 103 27 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 1.85 vpr 64.63 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29772 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66184 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2380 968 16819 5706 8070 3043 64.6 MiB 0.11 0.00 4.6711 4.04346 -120.969 -4.04346 4.04346 0.24 0.000352021 0.000322419 0.0406105 0.0374978 -1 -1 -1 -1 32 2265 23 6.65987e+06 342306 554710. 1919.41 0.38 0.0901688 0.0809194 22834 132086 -1 1906 20 1277 2430 141211 36257 3.18037 3.18037 -113.866 -3.18037 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0169663 0.0152628 138 58 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 2.08 vpr 64.57 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29812 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2606 1180 9821 2681 6536 604 64.6 MiB 0.08 0.00 5.38841 4.32378 -139.417 -4.32378 4.32378 0.25 0.000791528 0.000740611 0.0268259 0.0249583 -1 -1 -1 -1 32 2326 24 6.65987e+06 354984 554710. 1919.41 0.36 0.0762524 0.0683985 22834 132086 -1 2119 19 1135 1613 108552 25602 2.99237 2.99237 -119.109 -2.99237 0 0 701300. 2426.64 0.04 0.06 0.13 -1 -1 0.04 0.0273834 0.0246954 144 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.62 vpr 64.43 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29744 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2090 920 16748 5345 9445 1958 64.4 MiB 0.08 0.00 3.59784 2.86781 -104.206 -2.86781 2.86781 0.24 0.000333852 0.000306347 0.0276424 0.0253042 -1 -1 -1 -1 26 2004 20 6.65987e+06 431052 477104. 1650.88 1.02 0.118539 0.104012 21682 110474 -1 1752 18 988 1648 111876 27246 2.22331 2.22331 -97.4468 -2.22331 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0138236 0.0124016 115 65 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 31 32 291 243 1 171 87 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2125 1025 13911 4279 7725 1907 64.2 MiB 0.09 0.00 5.78495 4.84052 -144.776 -4.84052 4.84052 0.24 0.000318651 0.000293292 0.0318166 0.0293921 -1 -1 -1 -1 32 1975 23 6.65987e+06 304272 554710. 1919.41 0.37 0.0796161 0.0710669 22834 132086 -1 1717 18 884 1286 76003 18888 3.38591 3.38591 -126.147 -3.38591 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0139715 0.012598 127 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.67 vpr 64.59 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29900 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2331 1127 17961 5306 10774 1881 64.6 MiB 0.09 0.00 5.44296 4.25196 -133.571 -4.25196 4.25196 0.24 0.000328108 0.000300221 0.0278798 0.0255437 -1 -1 -1 -1 32 2239 20 6.65987e+06 469086 554710. 1919.41 1.28 0.164041 0.144183 22834 132086 -1 2044 20 1134 1882 137464 30497 3.52443 3.52443 -125.531 -3.52443 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0164691 0.0147989 140 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 1.94 vpr 64.74 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29936 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2693 1105 8735 1790 6509 436 64.7 MiB 0.07 0.00 5.32033 4.24321 -129.182 -4.24321 4.24321 0.24 0.000355888 0.000326787 0.021586 0.0199751 -1 -1 -1 -1 32 2756 25 6.65987e+06 393018 554710. 1919.41 0.41 0.0732554 0.0652145 22834 132086 -1 2171 17 1204 1933 126107 29946 3.40551 3.40551 -121.526 -3.40551 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0163433 0.014756 151 62 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 1.60 vpr 63.71 MiB -1 -1 0.10 17672 1 0.02 -1 -1 29788 -1 -1 20 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65236 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1349 468 11200 4643 5749 808 63.7 MiB 0.04 0.00 2.72887 2.30927 -65.1311 -2.30927 2.30927 0.23 0.000202817 0.000184723 0.0152371 0.0139236 -1 -1 -1 -1 28 1180 20 6.65987e+06 253560 500653. 1732.36 0.32 0.0421095 0.0370717 21970 115934 -1 973 22 671 1041 63401 16945 1.84505 1.84505 -64.3919 -1.84505 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0104773 0.00928288 81 30 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.48 vpr 64.38 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29792 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2052 1025 13751 4494 6800 2457 64.4 MiB 0.09 0.00 4.848 4.36895 -121.042 -4.36895 4.36895 0.24 0.000289177 0.000264542 0.0307812 0.0282922 -1 -1 -1 -1 30 2062 23 6.65987e+06 316950 526063. 1820.29 1.05 0.119757 0.105578 22546 126617 -1 1919 21 1129 2131 143866 32712 3.23591 3.23591 -111.109 -3.23591 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0153198 0.013733 125 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.21 vpr 63.69 MiB -1 -1 0.09 17676 1 0.03 -1 -1 29708 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65220 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 24.1 MiB 0.05 1447 545 12331 4341 5596 2394 63.7 MiB 0.04 0.00 2.73393 2.35833 -70.1665 -2.35833 2.35833 0.24 0.000200135 0.000182493 0.0152465 0.0138979 -1 -1 -1 -1 28 1272 22 6.65987e+06 215526 500653. 1732.36 0.84 0.0753932 0.0656314 21970 115934 -1 1023 19 461 533 38297 10550 1.69971 1.69971 -68.1319 -1.69971 0 0 612192. 2118.31 0.02 0.02 0.09 -1 -1 0.02 0.00930423 0.00823659 82 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.70 vpr 64.46 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30148 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2081 896 13487 3921 6875 2691 64.5 MiB 0.07 0.00 5.05175 4.41269 -119.651 -4.41269 4.41269 0.24 0.000297513 0.000271843 0.0207646 0.019033 -1 -1 -1 -1 30 2108 21 6.65987e+06 393018 526063. 1820.29 1.30 0.141092 0.123292 22546 126617 -1 1652 20 867 1525 86666 21900 3.26785 3.26785 -105.916 -3.26785 0 0 666494. 2306.21 0.03 0.04 0.08 -1 -1 0.03 0.0170098 0.0152863 126 24 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.92 vpr 63.70 MiB -1 -1 0.11 17664 1 0.03 -1 -1 29928 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65232 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 24.1 MiB 0.03 2388 1023 19624 6470 10444 2710 63.7 MiB 0.16 0.00 4.58506 3.64141 -104.769 -3.64141 3.64141 0.25 0.000560476 0.000510967 0.0484126 0.0441709 -1 -1 -1 -1 26 2542 46 6.65987e+06 494442 477104. 1650.88 1.29 0.168586 0.149805 21682 110474 -1 2045 18 1075 2003 124306 31296 3.00917 3.00917 -106.461 -3.00917 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0140512 0.0126467 136 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.79 vpr 64.55 MiB -1 -1 0.21 18044 1 0.04 -1 -1 30164 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 338 277 1 179 98 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2305 1091 18323 5790 9817 2716 64.6 MiB 0.09 0.00 5.46249 4.55003 -127.972 -4.55003 4.55003 0.24 0.000318033 0.000290194 0.0282284 0.0257753 -1 -1 -1 -1 30 2249 26 6.65987e+06 431052 526063. 1820.29 1.08 0.140788 0.122545 22546 126617 -1 1876 22 1106 1999 115126 27433 3.41605 3.41605 -116.12 -3.41605 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0170675 0.0152663 132 50 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.16 vpr 64.35 MiB -1 -1 0.11 18056 1 0.04 -1 -1 29776 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1848 913 13291 3770 7974 1547 64.3 MiB 0.06 0.00 3.57584 2.90053 -103.342 -2.90053 2.90053 0.24 0.000281589 0.000257719 0.0224208 0.0205218 -1 -1 -1 -1 28 1955 21 6.65987e+06 266238 500653. 1732.36 0.80 0.109728 0.0958161 21970 115934 -1 1804 21 1025 1722 112193 27509 2.68265 2.68265 -105.703 -2.68265 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0146769 0.0131164 107 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.40 vpr 64.27 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29776 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65808 30 32 262 227 1 135 86 17 17 289 -1 unnamed_device 24.3 MiB 0.04 1630 651 8969 1996 5970 1003 64.3 MiB 0.06 0.00 3.39847 3.05504 -90.9474 -3.05504 3.05504 0.25 0.000642942 0.000600414 0.0237623 0.0220744 -1 -1 -1 -1 28 1977 31 6.65987e+06 304272 500653. 1732.36 1.09 0.126607 0.110752 21970 115934 -1 1470 22 937 1443 90491 25132 2.67851 2.67851 -92.6094 -2.67851 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.01419 0.0126255 100 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2077 937 13663 4386 7373 1904 64.3 MiB 0.07 0.00 4.42935 3.71432 -111.148 -3.71432 3.71432 0.24 0.000318555 0.000292319 0.0221483 0.0202869 -1 -1 -1 -1 30 1919 20 6.65987e+06 266238 526063. 1820.29 0.76 0.0917732 0.0801906 22546 126617 -1 1728 21 1075 1786 109331 25720 2.65051 2.65051 -104.501 -2.65051 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0142262 0.0127329 116 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 1.97 vpr 64.33 MiB -1 -1 0.12 17668 1 0.03 -1 -1 29800 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1915 835 10827 2687 7563 577 64.3 MiB 0.09 0.00 3.84464 3.33721 -100.19 -3.33721 3.33721 0.35 0.000522039 0.00047658 0.0275881 0.0251882 -1 -1 -1 -1 26 1992 24 6.65987e+06 418374 477104. 1650.88 0.54 0.0791696 0.0702585 21682 110474 -1 1818 16 954 1675 105836 27778 2.82585 2.82585 -102.328 -2.82585 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0117904 0.0105846 111 30 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 1.74 vpr 64.40 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30200 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2169 872 17273 5743 9135 2395 64.4 MiB 0.07 0.00 3.81664 3.21564 -100.08 -3.21564 3.21564 0.24 0.000287972 0.000263067 0.0258344 0.0235912 -1 -1 -1 -1 32 1641 19 6.65987e+06 393018 554710. 1919.41 0.35 0.0669967 0.0594516 22834 132086 -1 1488 14 765 1169 65775 17191 2.31791 2.31791 -88.1097 -2.31791 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0124866 0.0111334 112 54 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 2.12 vpr 64.70 MiB -1 -1 0.16 18436 1 0.03 -1 -1 29616 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2308 1244 18356 5163 9963 3230 64.7 MiB 0.10 0.00 4.39192 3.92829 -113.996 -3.92829 3.92829 0.25 0.000749949 0.000718237 0.0389664 0.0359702 -1 -1 -1 -1 32 2640 24 6.65987e+06 532476 554710. 1919.41 0.44 0.095081 0.0852499 22834 132086 -1 2262 21 1317 2612 179532 41270 3.25579 3.25579 -109.354 -3.25579 0 0 701300. 2426.64 0.03 0.08 0.13 -1 -1 0.03 0.0355269 0.0316882 158 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 1.87 vpr 64.75 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29764 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2421 1098 16654 4458 10225 1971 64.7 MiB 0.10 0.00 4.43155 3.83032 -129.396 -3.83032 3.83032 0.24 0.000365598 0.000334178 0.0332215 0.0304978 -1 -1 -1 -1 28 2395 21 6.65987e+06 519798 500653. 1732.36 0.37 0.0820495 0.0733414 21970 115934 -1 2087 22 1631 2798 163826 40220 2.88617 2.88617 -117.628 -2.88617 0 0 612192. 2118.31 0.03 0.05 0.06 -1 -1 0.03 0.0206196 0.0184833 150 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 1.74 vpr 64.39 MiB -1 -1 0.13 17912 1 0.03 -1 -1 29804 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 24.3 MiB 0.05 2417 954 13883 3379 9484 1020 64.4 MiB 0.07 0.00 4.94055 4.24332 -124.031 -4.24332 4.24332 0.24 0.000288508 0.000262756 0.0228909 0.0208676 -1 -1 -1 -1 32 1963 21 6.65987e+06 291594 554710. 1919.41 0.33 0.0612728 0.0542438 22834 132086 -1 1756 20 823 1155 77844 19870 2.98031 2.98031 -108.773 -2.98031 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0143922 0.0129215 114 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.26 vpr 64.67 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30520 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66224 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2217 1128 16238 4900 9111 2227 64.7 MiB 0.09 0.00 4.7803 3.9389 -118.342 -3.9389 3.9389 0.24 0.000337036 0.000307837 0.0287174 0.0262948 -1 -1 -1 -1 30 2357 17 6.65987e+06 367662 526063. 1820.29 0.85 0.125417 0.110734 22546 126617 -1 2060 20 1126 2079 105239 26274 2.83077 2.83077 -109.668 -2.83077 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0172833 0.0155108 145 61 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.99 vpr 64.78 MiB -1 -1 0.17 18440 1 0.03 -1 -1 29768 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 377 302 1 233 99 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2995 1450 19023 5551 11450 2022 64.8 MiB 0.12 0.00 7.69393 5.6677 -167.985 -5.6677 5.6677 0.32 0.000381638 0.000350701 0.0372226 0.0341246 -1 -1 -1 -1 28 3350 21 6.65987e+06 456408 500653. 1732.36 1.33 0.159215 0.140889 21970 115934 -1 2772 21 1856 2735 170569 41048 4.77703 4.77703 -165.781 -4.77703 0 0 612192. 2118.31 0.03 0.06 0.07 -1 -1 0.03 0.0228982 0.0206184 178 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.97 vpr 64.36 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30132 -1 -1 32 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 24.9 MiB 0.59 2681 1309 14999 4622 8322 2055 64.4 MiB 0.09 0.00 6.28756 5.10273 -157.72 -5.10273 5.10273 0.23 0.00068262 0.00062368 0.0291839 0.0267265 -1 -1 -1 -1 32 2682 21 6.65987e+06 405696 554710. 1919.41 1.01 0.131813 0.116038 22834 132086 -1 2351 17 1068 1598 128922 28801 3.94943 3.94943 -145.575 -3.94943 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0160375 0.0145622 167 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 1.94 vpr 64.62 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29740 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2150 1138 13788 3708 8180 1900 64.6 MiB 0.08 0.00 5.13095 4.43175 -130.78 -4.43175 4.43175 0.23 0.000330854 0.000303241 0.0226578 0.0208034 -1 -1 -1 -1 26 2684 23 6.65987e+06 469086 477104. 1650.88 0.48 0.0706622 0.0628663 21682 110474 -1 2241 22 1376 2290 147550 36455 3.10551 3.10551 -115.897 -3.10551 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0181755 0.0161496 140 55 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 1.78 vpr 64.46 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29580 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66008 32 32 291 242 1 179 91 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2447 1059 9883 2265 7085 533 64.5 MiB 0.06 0.00 5.12624 4.09841 -110.895 -4.09841 4.09841 0.25 0.000296132 0.000272346 0.0176985 0.0162418 -1 -1 -1 -1 26 2556 27 6.65987e+06 342306 477104. 1650.88 0.46 0.0606008 0.0535975 21682 110474 -1 2017 21 1095 1676 106066 26073 3.51731 3.51731 -113.349 -3.51731 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152707 0.0135971 124 27 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 2.51 vpr 64.29 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29856 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3074 1204 12757 3068 8413 1276 64.3 MiB 0.08 0.00 6.1774 4.89901 -154.002 -4.89901 4.89901 0.23 0.000414085 0.000380006 0.0237217 0.0217485 -1 -1 -1 -1 28 3067 37 6.65987e+06 545154 500653. 1732.36 1.06 0.158471 0.138717 21970 115934 -1 2549 21 1787 2650 155948 39478 4.09557 4.09557 -145.446 -4.09557 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.023765 0.0213011 176 87 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.10 vpr 64.28 MiB -1 -1 0.12 17668 1 0.02 -1 -1 29856 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2009 887 11048 2987 7063 998 64.3 MiB 0.06 0.00 4.26232 3.39378 -98.4132 -3.39378 3.39378 0.24 0.000267305 0.000244906 0.020054 0.018467 -1 -1 -1 -1 26 1891 30 6.65987e+06 291594 477104. 1650.88 0.77 0.105782 0.092071 21682 110474 -1 1662 20 1011 1739 107514 26503 2.82891 2.82891 -101.876 -2.82891 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0133012 0.0118709 104 28 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 2.54 vpr 64.61 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30240 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2890 1251 18301 5355 10266 2680 64.6 MiB 0.10 0.00 6.05769 4.76375 -144.29 -4.76375 4.76375 0.25 0.000325031 0.000298013 0.0320046 0.0294245 -1 -1 -1 -1 26 3189 24 6.65987e+06 431052 477104. 1650.88 1.13 0.140561 0.123821 21682 110474 -1 2546 22 1555 2328 159437 38754 4.09251 4.09251 -137.605 -4.09251 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0175959 0.015789 149 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.00 vpr 64.21 MiB -1 -1 0.12 18048 1 0.03 -1 -1 29732 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 32 32 349 284 1 182 102 17 17 289 -1 unnamed_device 24.2 MiB 0.05 2675 1157 12240 3182 8323 735 64.2 MiB 0.08 0.00 4.8754 3.93484 -114.185 -3.93484 3.93484 0.24 0.000330143 0.000300671 0.0222818 0.0204813 -1 -1 -1 -1 26 2757 32 6.65987e+06 481764 477104. 1650.88 0.60 0.0776811 0.0690096 21682 110474 -1 2363 19 1261 2360 164757 38552 3.36871 3.36871 -117.29 -3.36871 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.019165 0.0171186 136 53 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 1.88 vpr 64.40 MiB -1 -1 0.16 17528 1 0.03 -1 -1 30164 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1813 1098 12127 4092 6786 1249 64.4 MiB 0.09 0.00 4.58224 3.99224 -122.075 -3.99224 3.99224 0.25 0.000381717 0.000350442 0.0280412 0.0258922 -1 -1 -1 -1 32 2237 19 6.65987e+06 342306 554710. 1919.41 0.40 0.0682722 0.0610453 22834 132086 -1 2105 20 1119 2098 156985 35010 3.48525 3.48525 -121.639 -3.48525 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0257139 0.0230642 127 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.25 vpr 64.68 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30152 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66232 32 32 353 287 1 198 95 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2414 1201 14783 3737 9111 1935 64.7 MiB 0.09 0.00 5.28395 4.64383 -136.782 -4.64383 4.64383 0.23 0.000330395 0.000300954 0.0254379 0.0232664 -1 -1 -1 -1 28 2543 26 6.65987e+06 393018 500653. 1732.36 0.80 0.120905 0.105969 21970 115934 -1 2251 21 1408 1875 123007 30781 3.10031 3.10031 -118.173 -3.10031 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0168622 0.0151259 142 55 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2721 1179 19868 6240 11195 2433 64.6 MiB 0.21 0.00 4.80995 4.10592 -126.681 -4.10592 4.10592 0.23 0.000537632 0.000496731 0.0705905 0.0653766 -1 -1 -1 -1 26 2816 24 6.65987e+06 507120 477104. 1650.88 0.60 0.128236 0.11589 21682 110474 -1 2357 21 1447 2439 171323 40624 2.93371 2.93371 -116.894 -2.93371 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0178623 0.0160256 149 62 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 3.71 vpr 64.45 MiB -1 -1 0.11 17904 1 0.03 -1 -1 29800 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 25.0 MiB 0.05 1946 873 16108 4349 7937 3822 64.5 MiB 0.07 0.00 4.57124 3.93324 -112.121 -3.93324 3.93324 0.23 0.000306658 0.000280335 0.0248876 0.0228463 -1 -1 -1 -1 30 2274 29 6.65987e+06 456408 526063. 1820.29 2.35 0.120616 0.105943 22546 126617 -1 1515 22 1093 1983 103839 27229 3.38699 3.38699 -106.02 -3.38699 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0177718 0.0157363 127 24 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.23 vpr 63.87 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29584 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 32 32 319 257 1 198 92 17 17 289 -1 unnamed_device 24.5 MiB 0.09 2350 1139 12719 3270 8148 1301 63.9 MiB 0.07 0.00 5.74889 4.74243 -133.951 -4.74243 4.74243 0.24 0.000312147 0.000284437 0.0214525 0.0196459 -1 -1 -1 -1 30 2287 21 6.65987e+06 354984 526063. 1820.29 0.68 0.102014 0.0894369 22546 126617 -1 1970 18 1171 1696 92785 22648 3.49131 3.49131 -121.376 -3.49131 0 0 666494. 2306.21 0.04 0.05 0.12 -1 -1 0.04 0.0187291 0.0169296 137 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 2.62 vpr 64.74 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29800 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2919 1229 8073 1790 5652 631 64.7 MiB 0.06 0.00 6.09275 4.90792 -144.963 -4.90792 4.90792 0.24 0.000354844 0.000325213 0.0163957 0.0150592 -1 -1 -1 -1 26 3109 38 6.65987e+06 380340 477104. 1650.88 1.20 0.150978 0.132741 21682 110474 -1 2584 23 1839 2855 189670 45582 4.00631 4.00631 -139.798 -4.00631 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.019152 0.0170771 151 62 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.92 vpr 64.23 MiB -1 -1 0.17 18056 1 0.03 -1 -1 30108 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2687 1072 16523 5659 7829 3035 64.2 MiB 0.11 0.00 4.94107 4.09069 -129.92 -4.09069 4.09069 0.24 0.000857988 0.000801055 0.0416845 0.0386047 -1 -1 -1 -1 30 2468 19 6.65987e+06 316950 526063. 1820.29 1.40 0.171759 0.152727 22546 126617 -1 1929 19 1275 2194 126979 30184 3.36805 3.36805 -121.211 -3.36805 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0232353 0.0208535 141 77 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66120 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2440 992 6007 1156 4597 254 64.6 MiB 0.04 0.00 4.88419 3.97947 -135.407 -3.97947 3.97947 0.29 0.000328686 0.000301478 0.0111881 0.0102596 -1 -1 -1 -1 28 2655 20 6.65987e+06 342306 500653. 1732.36 0.40 0.0545205 0.04797 21970 115934 -1 2093 23 1541 2202 159522 39777 3.38797 3.38797 -131.381 -3.38797 0 0 612192. 2118.31 0.03 0.05 0.06 -1 -1 0.03 0.0182671 0.0163156 133 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 1.88 vpr 64.34 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29828 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 32 32 387 293 1 234 98 17 17 289 -1 unnamed_device 25.1 MiB 0.06 2841 1434 16523 4655 9834 2034 64.3 MiB 0.11 0.00 6.09189 5.18108 -152.063 -5.18108 5.18108 0.24 0.000363101 0.000332817 0.0361583 0.0334442 -1 -1 -1 -1 32 3145 19 6.65987e+06 431052 554710. 1919.41 0.38 0.0838214 0.0752932 22834 132086 -1 2602 22 1587 2577 157408 37857 4.25491 4.25491 -142.991 -4.25491 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0194226 0.0174853 174 31 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 3.65 vpr 64.57 MiB -1 -1 0.13 18020 1 0.03 -1 -1 29944 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2565 908 17952 4964 9148 3840 64.6 MiB 0.09 0.00 5.03706 4.14283 -126.342 -4.14283 4.14283 0.23 0.000329597 0.000301333 0.0285814 0.0262011 -1 -1 -1 -1 30 2351 28 6.65987e+06 481764 526063. 1820.29 2.07 0.16465 0.145021 22546 126617 -1 1739 20 1039 1780 111645 29043 2.61551 2.61551 -104.065 -2.61551 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0164232 0.0147637 141 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.35 vpr 64.36 MiB -1 -1 0.12 17668 1 0.03 -1 -1 30328 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 24.9 MiB 0.03 2182 907 13703 3856 8397 1450 64.4 MiB 0.07 0.00 4.13824 3.55007 -108.481 -3.55007 3.55007 0.25 0.000293269 0.000263617 0.024289 0.0224368 -1 -1 -1 -1 32 1765 21 6.65987e+06 418374 554710. 1919.41 0.98 0.118204 0.103343 22834 132086 -1 1534 19 670 1228 76480 18288 2.48817 2.48817 -96.8001 -2.48817 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.013599 0.0121795 111 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 2.80 vpr 64.20 MiB -1 -1 0.15 18824 1 0.03 -1 -1 30124 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65744 32 32 431 332 1 235 95 17 17 289 -1 unnamed_device 24.9 MiB 0.16 2995 1435 16943 5441 8966 2536 64.2 MiB 0.11 0.00 7.19172 6.12709 -179.158 -6.12709 6.12709 0.24 0.000402579 0.000368127 0.0338431 0.0310673 -1 -1 -1 -1 32 2968 21 6.65987e+06 393018 554710. 1919.41 1.11 0.166916 0.146566 22834 132086 -1 2576 21 1778 2583 161656 39107 4.64457 4.64457 -161.765 -4.64457 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0204855 0.0183688 177 65 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 231 199 1 140 91 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1906 763 10291 2431 6883 977 64.2 MiB 0.05 0.00 4.00198 3.24072 -93.0898 -3.24072 3.24072 0.24 0.000252957 0.00023204 0.014133 0.0129556 -1 -1 -1 -1 26 1813 19 6.65987e+06 342306 477104. 1650.88 0.90 0.100565 0.0873611 21682 110474 -1 1587 17 924 1601 94219 24609 2.67551 2.67551 -95.133 -2.67551 0 0 585099. 2024.56 0.02 0.03 0.07 -1 -1 0.02 0.0144873 0.0129215 103 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.94 vpr 64.62 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30252 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2540 1184 12792 3130 8784 878 64.6 MiB 0.08 0.00 6.17103 5.12357 -128.342 -5.12357 5.12357 0.24 0.000405648 0.00035247 0.0251103 0.0232583 -1 -1 -1 -1 26 2736 22 6.65987e+06 507120 477104. 1650.88 1.38 0.129295 0.114292 21682 110474 -1 2329 19 1224 2599 181219 41024 3.77199 3.77199 -121.701 -3.77199 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0175625 0.0157507 147 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.20 vpr 64.25 MiB -1 -1 0.23 17912 1 0.02 -1 -1 29776 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 24.1 MiB 0.04 2164 862 9111 2261 6252 598 64.2 MiB 0.05 0.00 4.2295 3.4211 -103.943 -3.4211 3.4211 0.25 0.000272144 0.000249418 0.0165738 0.015236 -1 -1 -1 -1 26 1976 21 6.65987e+06 291594 477104. 1650.88 0.72 0.0817198 0.0712883 21682 110474 -1 1647 22 1171 2052 118500 29809 2.99817 2.99817 -107.951 -2.99817 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0148357 0.0132715 107 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.37 vpr 64.37 MiB -1 -1 0.15 17912 1 0.04 -1 -1 29824 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2117 919 17732 5394 9708 2630 64.4 MiB 0.09 0.00 5.05435 4.00072 -108.105 -4.00072 4.00072 0.25 0.000319002 0.000294923 0.0275487 0.0252902 -1 -1 -1 -1 28 1932 24 6.65987e+06 481764 500653. 1732.36 0.86 0.115273 0.101221 21970 115934 -1 1752 19 902 1787 109885 27332 2.74851 2.74851 -98.5026 -2.74851 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0132408 0.0118756 110 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 2.40 vpr 64.51 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29996 -1 -1 30 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 29 32 355 287 1 198 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2795 1157 13759 4262 7817 1680 64.5 MiB 0.08 0.00 5.46461 4.50718 -131.152 -4.50718 4.50718 0.31 0.000330091 0.000302586 0.0257511 0.0236546 -1 -1 -1 -1 26 2957 22 6.65987e+06 380340 477104. 1650.88 0.51 0.0783395 0.0700172 21682 110474 -1 2345 21 1460 2184 143176 34536 3.37397 3.37397 -119.24 -3.37397 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0287388 0.0256969 146 62 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66128 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2440 995 11573 3131 7196 1246 64.6 MiB 0.07 0.00 5.53355 4.52906 -132.157 -4.52906 4.52906 0.25 0.000337555 0.000309443 0.0200569 0.0183746 -1 -1 -1 -1 32 2149 21 6.65987e+06 431052 554710. 1919.41 0.34 0.0639729 0.0567577 22834 132086 -1 1930 21 1161 1924 112326 28305 3.56431 3.56431 -123.17 -3.56431 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0192602 0.017328 136 51 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.28 vpr 64.37 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29596 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1928 842 5756 1110 4290 356 64.4 MiB 0.04 0.00 5.01063 4.547 -125.133 -4.547 4.547 0.24 0.000281039 0.000257092 0.0108104 0.00993427 -1 -1 -1 -1 26 2746 42 6.65987e+06 278916 477104. 1650.88 0.81 0.0695017 0.0610828 21682 110474 -1 2009 23 1128 1545 124492 32025 3.20671 3.20671 -119.094 -3.20671 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0149363 0.0132929 107 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.31 vpr 64.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29780 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 31 32 319 272 1 169 86 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2087 999 8402 2135 5628 639 64.4 MiB 0.05 0.00 4.70844 3.76401 -122.041 -3.76401 3.76401 0.24 0.000297899 0.000272927 0.0150693 0.0138092 -1 -1 -1 -1 30 2009 19 6.65987e+06 291594 526063. 1820.29 0.77 0.139907 0.122491 22546 126617 -1 1802 22 1049 1597 92062 22220 3.08351 3.08351 -115.52 -3.08351 0 0 666494. 2306.21 0.05 0.05 0.11 -1 -1 0.05 0.023418 0.0209173 116 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.79 vpr 64.51 MiB -1 -1 0.14 18440 1 0.03 -1 -1 30120 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2322 911 10223 2206 7289 728 64.5 MiB 0.06 0.00 4.14418 3.34001 -95.1163 -3.34001 3.34001 0.24 0.000313524 0.000285877 0.0164285 0.0150486 -1 -1 -1 -1 26 2414 22 6.65987e+06 456408 477104. 1650.88 1.37 0.107607 0.0946655 21682 110474 -1 1927 22 1181 2235 140233 36386 2.57639 2.57639 -96.5212 -2.57639 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0200354 0.0178693 128 57 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.64 vpr 64.39 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30184 -1 -1 39 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1932 968 16515 5028 9029 2458 64.4 MiB 0.10 0.00 4.80358 3.82106 -98.9222 -3.82106 3.82106 0.27 0.000295246 0.000271701 0.0370857 0.0343414 -1 -1 -1 -1 30 1920 22 6.65987e+06 494442 526063. 1820.29 1.00 0.146017 0.128722 22546 126617 -1 1687 18 746 1556 78646 19064 3.06345 3.06345 -92.4917 -3.06345 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0156517 0.0140541 122 27 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65604 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2267 1081 11748 2737 7741 1270 64.1 MiB 0.12 0.00 4.27587 3.75301 -127.23 -3.75301 3.75301 0.24 0.000922484 0.000857673 0.046778 0.043576 -1 -1 -1 -1 32 2169 20 6.65987e+06 329628 554710. 1919.41 0.53 0.113914 0.10228 22834 132086 -1 1912 17 1021 1536 95655 22988 3.18891 3.18891 -117.522 -3.18891 0 0 701300. 2426.64 0.04 0.06 0.11 -1 -1 0.04 0.0257491 0.022733 127 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.59 vpr 64.44 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29548 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 25.0 MiB 0.04 2060 1066 14716 3823 8466 2427 64.4 MiB 0.07 0.00 4.86349 4.26143 -121.889 -4.26143 4.26143 0.27 0.000296603 0.000269714 0.0210521 0.0191673 -1 -1 -1 -1 32 2163 21 6.65987e+06 469086 554710. 1919.41 1.11 0.142451 0.124381 22834 132086 -1 1952 18 1051 1980 108284 26406 3.51125 3.51125 -111.09 -3.51125 0 0 701300. 2426.64 0.03 0.04 0.10 -1 -1 0.03 0.0165159 0.0149261 134 4 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 1.98 vpr 64.64 MiB -1 -1 0.12 18048 1 0.03 -1 -1 30360 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 350 275 1 209 93 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2681 1168 10383 2802 6577 1004 64.6 MiB 0.07 0.00 5.68615 4.86192 -151.547 -4.86192 4.86192 0.24 0.000334875 0.000306795 0.0187135 0.0171881 -1 -1 -1 -1 32 2556 25 6.65987e+06 367662 554710. 1919.41 0.49 0.0877671 0.0777807 22834 132086 -1 2143 20 1336 2094 119998 29832 3.72991 3.72991 -134.478 -3.72991 0 0 701300. 2426.64 0.04 0.06 0.08 -1 -1 0.04 0.0242861 0.021965 151 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 4.53 vpr 64.66 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29792 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2633 927 18196 5275 8727 4194 64.7 MiB 0.08 0.00 5.51755 4.47917 -136.038 -4.47917 4.47917 0.23 0.00035799 0.000327422 0.0311637 0.0285323 -1 -1 -1 -1 36 2460 39 6.65987e+06 469086 612192. 2118.31 3.09 0.183338 0.161522 23410 145293 -1 1908 19 1434 2459 149777 39483 3.72051 3.72051 -129.983 -3.72051 0 0 782063. 2706.10 0.03 0.04 0.09 -1 -1 0.03 0.0173432 0.0156109 143 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.52 vpr 64.05 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30240 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2914 1226 13516 3426 8918 1172 64.1 MiB 0.11 0.00 5.66375 4.30832 -138.449 -4.30832 4.30832 0.31 0.000364026 0.000327868 0.0352371 0.0324508 -1 -1 -1 -1 26 3133 37 6.65987e+06 545154 477104. 1650.88 2.01 0.204454 0.180913 21682 110474 -1 2585 21 1659 3001 194586 46671 3.27771 3.27771 -128.625 -3.27771 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184663 0.0164533 147 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 1.84 vpr 64.31 MiB -1 -1 0.22 17672 1 0.03 -1 -1 30260 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65856 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1945 699 9443 2134 6868 441 64.3 MiB 0.06 0.00 4.63389 3.7606 -108.702 -3.7606 3.7606 0.25 0.000274486 0.000250373 0.0202243 0.0186816 -1 -1 -1 -1 32 1712 22 6.65987e+06 266238 554710. 1919.41 0.36 0.0608618 0.0541478 22834 132086 -1 1351 17 754 1264 75034 19152 2.55625 2.55625 -94.2402 -2.55625 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0127318 0.0114779 109 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 1.87 vpr 64.62 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30156 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2028 1003 9395 2078 6561 756 64.6 MiB 0.06 0.00 5.34001 4.72954 -137.554 -4.72954 4.72954 0.23 0.000351356 0.000321724 0.0184561 0.0169463 -1 -1 -1 -1 28 2499 27 6.65987e+06 342306 500653. 1732.36 0.47 0.0711341 0.0630113 21970 115934 -1 2043 19 1375 2121 129278 33516 3.72637 3.72637 -132.273 -3.72637 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0175255 0.0158171 147 63 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 3.56 vpr 64.59 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29852 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2562 1172 8614 1885 5948 781 64.6 MiB 0.06 0.00 6.11242 5.075 -148.312 -5.075 5.075 0.24 0.000324053 0.000296578 0.0159447 0.0146839 -1 -1 -1 -1 28 3045 34 6.65987e+06 380340 500653. 1732.36 2.06 0.139928 0.123519 21970 115934 -1 2409 21 1636 2519 180150 43978 3.77211 3.77211 -133.398 -3.77211 0 0 612192. 2118.31 0.03 0.07 0.07 -1 -1 0.03 0.0233923 0.0209471 145 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 2.64 vpr 64.71 MiB -1 -1 0.16 17524 1 0.04 -1 -1 29784 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 340 275 1 195 98 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2655 1234 13373 3486 8666 1221 64.7 MiB 0.08 0.00 6.2565 5.20087 -146.632 -5.20087 5.20087 0.24 0.000337977 0.000309774 0.0232074 0.0213238 -1 -1 -1 -1 28 2603 23 6.65987e+06 443730 500653. 1732.36 0.95 0.148618 0.130153 21970 115934 -1 2276 21 1462 2381 143787 35641 4.28397 4.28397 -142.339 -4.28397 0 0 612192. 2118.31 0.04 0.07 0.11 -1 -1 0.04 0.0301272 0.0271323 152 47 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.11 vpr 64.64 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30124 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 24.9 MiB 0.37 2368 1078 19356 5734 11269 2353 64.6 MiB 0.11 0.00 5.15601 4.43481 -132.977 -4.43481 4.43481 0.24 0.000356646 0.000327786 0.0400155 0.0371255 -1 -1 -1 -1 32 2034 21 6.65987e+06 481764 554710. 1919.41 0.34 0.0872187 0.0784088 22834 132086 -1 1867 19 1042 1815 109969 26079 3.09757 3.09757 -117.861 -3.09757 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0270637 0.0241799 144 83 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 1.79 vpr 64.22 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29780 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65760 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2717 1028 9989 2368 7036 585 64.2 MiB 0.08 0.00 5.82395 4.80846 -135.83 -4.80846 4.80846 0.25 0.000785676 0.000756889 0.0268928 0.0250003 -1 -1 -1 -1 32 2279 22 6.65987e+06 316950 554710. 1919.41 0.40 0.0816934 0.072869 22834 132086 -1 1969 18 1045 1838 103539 25809 3.51511 3.51511 -124.567 -3.51511 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0162994 0.0147361 141 57 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65756 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 24.1 MiB 0.05 1776 913 13583 3827 8166 1590 64.2 MiB 0.06 0.00 4.36335 3.77952 -113.791 -3.77952 3.77952 0.23 0.000258733 0.000237246 0.0221535 0.0203246 -1 -1 -1 -1 32 1628 18 6.65987e+06 240882 554710. 1919.41 0.86 0.108382 0.0947406 22834 132086 -1 1492 15 568 862 53023 12847 2.73465 2.73465 -99.7426 -2.73465 0 0 701300. 2426.64 0.03 0.02 0.12 -1 -1 0.03 0.0110657 0.0100029 99 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.64 vpr 64.61 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29768 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2442 1018 18339 5915 9603 2821 64.6 MiB 0.09 0.00 5.53955 4.46392 -134.604 -4.46392 4.46392 0.24 0.000350581 0.000320376 0.030238 0.0276861 -1 -1 -1 -1 28 2559 33 6.65987e+06 443730 500653. 1732.36 1.23 0.157921 0.139255 21970 115934 -1 2034 22 1390 2379 155320 38127 3.72251 3.72251 -131.726 -3.72251 0 0 612192. 2118.31 0.03 0.06 0.06 -1 -1 0.03 0.0224972 0.0200975 135 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 1.88 vpr 64.36 MiB -1 -1 0.13 18044 1 0.03 -1 -1 29776 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2649 1042 7415 1478 5399 538 64.4 MiB 0.05 0.00 5.84281 4.69477 -144.735 -4.69477 4.69477 0.25 0.000363804 0.000333298 0.0164987 0.0151272 -1 -1 -1 -1 32 2467 22 6.65987e+06 316950 554710. 1919.41 0.43 0.0723381 0.0642314 22834 132086 -1 2120 20 1640 2746 168107 41989 3.74157 3.74157 -135.95 -3.74157 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0231033 0.0206951 155 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.15 vpr 64.37 MiB -1 -1 0.14 17660 1 0.03 -1 -1 29800 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2060 1041 9791 2284 6736 771 64.4 MiB 0.05 0.00 4.9641 4.13987 -114.14 -4.13987 4.13987 0.23 0.000285581 0.000261993 0.0167929 0.0154416 -1 -1 -1 -1 22 2510 30 6.65987e+06 316950 420624. 1455.45 0.84 0.0995754 0.0866549 20818 92861 -1 2270 19 1086 1462 115592 27496 3.61557 3.61557 -116.563 -3.61557 0 0 500653. 1732.36 0.02 0.04 0.05 -1 -1 0.02 0.0135916 0.0121488 117 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 1.77 vpr 64.24 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29940 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2068 883 14639 5191 7304 2144 64.2 MiB 0.07 0.00 4.81301 3.84841 -109.743 -3.84841 3.84841 0.25 0.000261358 0.000239166 0.0228225 0.0209759 -1 -1 -1 -1 32 1873 20 6.65987e+06 291594 554710. 1919.41 0.33 0.0586236 0.0521393 22834 132086 -1 1716 18 1042 1695 113744 27403 2.66951 2.66951 -100.595 -2.66951 0 0 701300. 2426.64 0.03 0.04 0.09 -1 -1 0.03 0.0131841 0.0117093 110 4 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 24.9 MiB 0.10 2455 1202 17726 5863 9448 2415 64.7 MiB 0.10 0.00 6.19085 4.98326 -147.838 -4.98326 4.98326 0.23 0.000337012 0.00030237 0.0286512 0.0261769 -1 -1 -1 -1 28 2992 31 6.65987e+06 469086 500653. 1732.36 1.28 0.150303 0.13201 21970 115934 -1 2209 22 1417 2227 163353 43256 4.07751 4.07751 -138.323 -4.07751 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0211012 0.0188692 157 56 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.12 vpr 64.40 MiB -1 -1 0.21 18056 1 0.04 -1 -1 29828 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2789 1282 17058 4558 10111 2389 64.4 MiB 0.10 0.00 6.22775 5.25635 -138.9 -5.25635 5.25635 0.24 0.000847755 0.000792737 0.0270822 0.0248474 -1 -1 -1 -1 30 2744 22 6.65987e+06 545154 526063. 1820.29 0.51 0.0787829 0.0704927 22546 126617 -1 2279 19 1165 2296 144567 32446 4.20857 4.20857 -132.092 -4.20857 0 0 666494. 2306.21 0.04 0.09 0.08 -1 -1 0.04 0.0377591 0.0340845 162 3 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.48 vpr 64.46 MiB -1 -1 0.12 17908 1 0.03 -1 -1 29804 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 30 32 316 264 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2263 907 15623 4094 8873 2656 64.5 MiB 0.07 0.00 4.35844 3.46421 -101.49 -3.46421 3.46421 0.23 0.000302285 0.000277318 0.0237892 0.0218542 -1 -1 -1 -1 30 1887 20 6.65987e+06 456408 526063. 1820.29 0.93 0.125269 0.109434 22546 126617 -1 1617 20 923 1599 76990 19613 2.69151 2.69151 -96.3226 -2.69151 0 0 666494. 2306.21 0.04 0.07 0.08 -1 -1 0.04 0.035453 0.0317282 124 52 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.19 vpr 64.24 MiB -1 -1 0.14 17672 1 0.02 -1 -1 30144 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 27 32 255 219 1 132 82 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1707 762 11296 3316 6423 1557 64.2 MiB 0.05 0.00 4.35664 3.48247 -97.7908 -3.48247 3.48247 0.23 0.000254069 0.00023285 0.0176088 0.0161447 -1 -1 -1 -1 32 1498 19 6.65987e+06 291594 554710. 1919.41 0.88 0.0982668 0.0852425 22834 132086 -1 1390 21 750 1239 79737 19491 2.74977 2.74977 -93.2365 -2.74977 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0131444 0.0117322 100 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 3.10 vpr 64.94 MiB -1 -1 0.16 17672 1 0.03 -1 -1 30148 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 25.6 MiB 0.06 3118 1504 18998 5785 11135 2078 64.9 MiB 0.16 0.00 5.30144 4.15341 -134.659 -4.15341 4.15341 0.24 0.000723216 0.00066104 0.048028 0.0441656 -1 -1 -1 -1 32 3347 20 6.65987e+06 431052 554710. 1919.41 1.49 0.187082 0.165648 22834 132086 -1 2852 23 1753 2861 212134 47689 3.41911 3.41911 -128.837 -3.41911 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0239451 0.0214081 176 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 2.76 vpr 64.15 MiB -1 -1 0.14 18044 1 0.03 -1 -1 30148 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 24.9 MiB 0.36 2626 1131 10743 2617 7196 930 64.2 MiB 0.07 0.00 6.52641 5.34958 -160.242 -5.34958 5.34958 0.23 0.000344068 0.000315901 0.0230363 0.0213167 -1 -1 -1 -1 32 2256 22 6.65987e+06 342306 554710. 1919.41 1.04 0.141545 0.124772 22834 132086 -1 2058 19 1267 1995 127981 30724 4.12737 4.12737 -144.115 -4.12737 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0163519 0.0147443 151 64 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 2.49 vpr 64.12 MiB -1 -1 0.12 18052 1 0.02 -1 -1 29692 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65660 32 32 331 280 1 175 87 17 17 289 -1 unnamed_device 24.5 MiB 0.34 2093 1056 11223 2777 6565 1881 64.1 MiB 0.07 0.00 5.5891 4.44586 -136.991 -4.44586 4.44586 0.23 0.000310743 0.00028465 0.0245441 0.0226654 -1 -1 -1 -1 30 2098 21 6.65987e+06 291594 526063. 1820.29 0.83 0.115069 0.101493 22546 126617 -1 1713 17 744 1061 64700 15352 3.42717 3.42717 -125.557 -3.42717 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0188638 0.0169499 129 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 1.99 vpr 64.05 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30332 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2458 1023 12396 3002 8710 684 64.1 MiB 0.06 0.00 5.92474 4.91628 -125.981 -4.91628 4.91628 0.31 0.00031312 0.000285308 0.0186718 0.0170098 -1 -1 -1 -1 26 2519 25 6.65987e+06 456408 477104. 1650.88 0.49 0.0681747 0.0605424 21682 110474 -1 2143 19 1162 2005 137788 34909 3.45605 3.45605 -115.538 -3.45605 0 0 585099. 2024.56 0.04 0.04 0.08 -1 -1 0.04 0.0156747 0.0141323 133 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 2.49 vpr 64.38 MiB -1 -1 0.18 18052 1 0.03 -1 -1 29868 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 31 32 373 294 1 196 102 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2316 1116 9622 2124 6827 671 64.4 MiB 0.07 0.00 5.28538 4.66257 -122.009 -4.66257 4.66257 0.24 0.000500582 0.000470974 0.022367 0.0207019 -1 -1 -1 -1 32 2164 22 6.65987e+06 494442 554710. 1919.41 0.96 0.150679 0.132762 22834 132086 -1 1941 21 1024 1664 98113 24600 3.71045 3.71045 -118.186 -3.71045 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0217 0.0195245 151 50 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.43 vpr 64.50 MiB -1 -1 0.19 18056 1 0.03 -1 -1 30260 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2399 1001 15848 4524 8647 2677 64.5 MiB 0.10 0.00 4.35464 3.6178 -102.686 -3.6178 3.6178 0.25 0.000340058 0.000313523 0.032293 0.0300242 -1 -1 -1 -1 32 2093 22 6.65987e+06 456408 554710. 1919.41 0.91 0.115634 0.10181 22834 132086 -1 1735 20 927 1616 95276 23308 2.75671 2.75671 -93.3009 -2.75671 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152838 0.0137139 130 51 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 2.63 vpr 64.65 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30252 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 25.3 MiB 0.13 2711 1336 11327 3094 7340 893 64.7 MiB 0.08 0.00 6.10595 5.14435 -160.142 -5.14435 5.14435 0.23 0.00035727 0.000327964 0.0199369 0.0183003 -1 -1 -1 -1 32 2855 24 6.65987e+06 393018 554710. 1919.41 1.00 0.118695 0.104006 22834 132086 -1 2484 19 1479 2310 144508 33634 3.96111 3.96111 -144.603 -3.96111 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0177237 0.0159978 155 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65688 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1576 639 12464 3221 8431 812 64.1 MiB 0.09 0.00 4.48041 4.01678 -108.148 -4.01678 4.01678 0.28 0.000480442 0.000438543 0.0373201 0.0341971 -1 -1 -1 -1 30 1486 20 6.65987e+06 240882 526063. 1820.29 0.93 0.126396 0.111447 22546 126617 -1 1234 20 690 1018 70885 16894 2.71377 2.71377 -93.534 -2.71377 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0135202 0.0121234 93 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.28 vpr 63.98 MiB -1 -1 0.13 17908 1 0.03 -1 -1 29936 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65520 32 32 310 266 1 175 90 17 17 289 -1 unnamed_device 24.1 MiB 0.04 2095 940 8331 1938 5650 743 64.0 MiB 0.05 0.00 4.98039 4.1175 -122.325 -4.1175 4.1175 0.25 0.000294899 0.000270139 0.0142154 0.0130403 -1 -1 -1 -1 26 2117 18 6.65987e+06 329628 477104. 1650.88 0.95 0.114865 0.100577 21682 110474 -1 1793 22 1060 1496 105030 24470 3.22317 3.22317 -116.181 -3.22317 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0159831 0.014244 123 58 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.83 vpr 64.54 MiB -1 -1 0.14 18440 1 0.03 -1 -1 29876 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66088 31 32 326 261 1 177 106 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2343 916 18356 4978 9795 3583 64.5 MiB 0.09 0.00 5.52155 4.37352 -119.432 -4.37352 4.37352 0.25 0.000354148 0.000290662 0.0273844 0.0250176 -1 -1 -1 -1 30 2290 33 6.65987e+06 545154 526063. 1820.29 1.40 0.157058 0.137275 22546 126617 -1 1831 24 1339 2530 162695 40201 3.55325 3.55325 -112.175 -3.55325 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0183438 0.0163401 138 33 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 1.69 vpr 64.36 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29796 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 29 32 262 224 1 168 87 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1937 962 8151 2045 5043 1063 64.4 MiB 0.05 0.00 4.73201 3.89047 -108.453 -3.89047 3.89047 0.24 0.000334714 0.000292814 0.0167961 0.0155764 -1 -1 -1 -1 26 2222 19 6.65987e+06 329628 477104. 1650.88 0.37 0.0576277 0.0510664 21682 110474 -1 1935 15 790 1052 70400 17366 3.46957 3.46957 -109.369 -3.46957 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0117647 0.0106224 116 31 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.30 vpr 64.32 MiB -1 -1 0.12 17668 1 0.02 -1 -1 30196 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1781 952 11063 2996 6474 1593 64.3 MiB 0.06 0.00 4.35429 3.84883 -121.23 -3.84883 3.84883 0.23 0.000287209 0.000263087 0.0212423 0.0195714 -1 -1 -1 -1 32 2005 20 6.65987e+06 240882 554710. 1919.41 0.95 0.109571 0.0957045 22834 132086 -1 1812 17 1077 1863 113788 27875 2.76365 2.76365 -109.874 -2.76365 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0124444 0.0111877 111 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 24.2 MiB 0.05 1957 962 7888 1862 5402 624 64.2 MiB 0.04 0.00 4.37039 3.7831 -115.738 -3.7831 3.7831 0.24 0.000271273 0.000248449 0.0127145 0.0116877 -1 -1 -1 -1 32 1927 16 6.65987e+06 316950 554710. 1919.41 0.31 0.0483232 0.0426507 22834 132086 -1 1730 18 773 1167 76810 18412 2.99882 2.99882 -104.533 -2.99882 0 0 701300. 2426.64 0.03 0.03 0.12 -1 -1 0.03 0.0145656 0.0130899 113 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.22 vpr 64.57 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29800 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2312 1008 10206 2347 7231 628 64.6 MiB 0.06 0.00 4.25818 3.54324 -107.169 -3.54324 3.54324 0.23 0.000332085 0.000303616 0.0162243 0.0148741 -1 -1 -1 -1 26 2349 20 6.65987e+06 469086 477104. 1650.88 0.85 0.0996743 0.0869767 21682 110474 -1 2018 17 1073 1917 117571 28694 3.00811 3.00811 -108.65 -3.00811 0 0 585099. 2024.56 0.03 0.04 0.06 -1 -1 0.03 0.0161924 0.0146389 131 57 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.55 vpr 64.71 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30128 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 25.2 MiB 0.31 2511 865 8763 1886 5820 1057 64.7 MiB 0.04 0.00 4.68116 3.95996 -121.43 -3.95996 3.95996 0.23 0.000354374 0.00032327 0.0160355 0.0147464 -1 -1 -1 -1 30 2002 20 6.65987e+06 456408 526063. 1820.29 0.94 0.117387 0.102667 22546 126617 -1 1550 23 1220 1942 99122 25765 3.04517 3.04517 -111.679 -3.04517 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0217423 0.0193783 145 91 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.16 vpr 64.38 MiB -1 -1 0.13 17528 1 0.03 -1 -1 30128 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1814 855 8685 1965 6279 441 64.4 MiB 0.05 0.00 3.73364 3.26564 -102.346 -3.26564 3.26564 0.24 0.000288455 0.000264091 0.0153522 0.0140632 -1 -1 -1 -1 30 1748 23 6.65987e+06 253560 526063. 1820.29 0.85 0.110401 0.0963068 22546 126617 -1 1498 21 732 1205 70856 17065 2.63031 2.63031 -100.894 -2.63031 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.017499 0.0156765 111 57 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.55 vpr 64.08 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29772 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 290 244 1 177 89 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2414 1034 14345 4099 8382 1864 64.1 MiB 0.08 0.00 4.99075 4.16652 -128.649 -4.16652 4.16652 0.23 0.000836935 0.000781281 0.0238684 0.0218989 -1 -1 -1 -1 26 2468 26 6.65987e+06 316950 477104. 1650.88 1.23 0.120498 0.105531 21682 110474 -1 2134 24 1416 2156 157699 36703 3.04751 3.04751 -115.392 -3.04751 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0174596 0.0154964 123 34 -1 -1 -1 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2020 1018 6757 1480 4594 683 64.4 MiB 0.04 0.00 4.63015 4.16652 -114.233 -4.16652 4.16652 0.24 0.000324166 0.00029741 0.0121531 0.0112268 -1 -1 -1 -1 26 2263 17 6.65987e+06 456408 477104. 1650.88 0.81 0.10672 0.0933432 21682 110474 -1 1930 17 916 1609 100571 24369 2.92431 2.92431 -101.278 -2.92431 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0152708 0.0135685 129 55 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 1.83 vpr 64.79 MiB -1 -1 0.17 18044 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 32 32 393 312 1 213 93 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2445 1182 15843 4177 9740 1926 64.8 MiB 0.10 0.00 6.02849 5.60583 -175.338 -5.60583 5.60583 0.24 0.000364198 0.000333706 0.0327777 0.0301651 -1 -1 -1 -1 32 2463 22 6.65987e+06 367662 554710. 1919.41 0.36 0.0842253 0.075097 22834 132086 -1 2221 17 1304 1896 104576 26642 4.22277 4.22277 -152.701 -4.22277 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0167933 0.015254 158 65 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.23 vpr 63.93 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29940 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65468 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1660 797 8502 1949 6085 468 63.9 MiB 0.04 0.00 3.86484 3.31781 -96.9676 -3.31781 3.31781 0.24 0.000251262 0.000230584 0.0130921 0.0120166 -1 -1 -1 -1 32 1566 18 6.65987e+06 266238 554710. 1919.41 0.87 0.0866868 0.0751474 22834 132086 -1 1391 19 657 1075 65111 16588 2.50751 2.50751 -91.4965 -2.50751 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0126917 0.0113845 100 4 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 1.89 vpr 64.77 MiB -1 -1 0.18 18052 1 0.03 -1 -1 29736 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2451 1117 18431 5270 10930 2231 64.8 MiB 0.10 0.00 5.26444 4.25378 -140.231 -4.25378 4.25378 0.23 0.000373417 0.000339939 0.0316981 0.0289474 -1 -1 -1 -1 32 2341 20 6.65987e+06 469086 554710. 1919.41 0.35 0.080619 0.0716735 22834 132086 -1 2008 21 1252 1842 124809 28919 3.67551 3.67551 -132.399 -3.67551 0 0 701300. 2426.64 0.05 0.10 0.07 -1 -1 0.05 0.0452931 0.0406668 146 90 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.82 vpr 64.54 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29804 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66092 32 32 376 318 1 156 82 17 17 289 -1 unnamed_device 24.5 MiB 0.09 1828 704 11118 4283 5586 1249 64.5 MiB 0.06 0.00 4.2335 3.6453 -123.384 -3.6453 3.6453 0.24 0.000342878 0.000313621 0.023058 0.0211148 -1 -1 -1 -1 28 2422 44 6.65987e+06 228204 500653. 1732.36 1.43 0.142219 0.124509 21970 115934 -1 1780 19 1300 1811 145425 37952 3.84337 3.84337 -134.566 -3.84337 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0162809 0.0146439 117 96 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 3.28 vpr 64.64 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29800 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2247 913 17427 4947 8338 4142 64.6 MiB 0.08 0.00 3.91868 3.84552 -113.949 -3.84552 3.84552 0.24 0.000355925 0.00032683 0.0299331 0.027482 -1 -1 -1 -1 30 2270 33 6.65987e+06 443730 526063. 1820.29 1.87 0.141496 0.124872 22546 126617 -1 1646 21 1045 1639 90768 24593 2.74351 2.74351 -97.3413 -2.74351 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0173314 0.0155781 134 60 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.41 vpr 64.84 MiB -1 -1 0.13 18436 1 0.03 -1 -1 30408 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 396 299 1 236 97 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3069 1481 14971 3777 9344 1850 64.8 MiB 0.10 0.00 7.38831 6.08328 -185.229 -6.08328 6.08328 0.24 0.000411097 0.000378951 0.029417 0.0270377 -1 -1 -1 -1 28 3362 36 6.65987e+06 418374 500653. 1732.36 1.91 0.197809 0.176182 21970 115934 -1 2828 20 1964 2892 207521 47864 4.90737 4.90737 -169.574 -4.90737 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0197778 0.0179217 178 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.17 vpr 64.17 MiB -1 -1 0.14 17660 1 0.02 -1 -1 29808 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65708 30 32 224 207 1 138 85 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1779 770 11245 2856 7531 858 64.2 MiB 0.05 0.00 3.68981 3.20901 -98.3536 -3.20901 3.20901 0.25 0.000246513 0.000216211 0.0159507 0.0145994 -1 -1 -1 -1 28 1564 19 6.65987e+06 291594 500653. 1732.36 0.87 0.100704 0.088167 21970 115934 -1 1350 17 651 829 50023 12838 2.20351 2.20351 -87.8269 -2.20351 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0142654 0.0125989 93 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.33 vpr 64.30 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30056 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1551 682 8831 2129 6271 431 64.3 MiB 0.04 0.00 4.40209 3.8416 -111.334 -3.8416 3.8416 0.23 0.000277254 0.000253555 0.0158328 0.0145297 -1 -1 -1 -1 30 1565 17 6.65987e+06 240882 526063. 1820.29 1.00 0.125437 0.109434 22546 126617 -1 1321 19 741 1248 76607 18509 2.86471 2.86471 -106.925 -2.86471 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0139883 0.0125804 95 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 1.67 vpr 64.40 MiB -1 -1 0.11 17672 1 0.04 -1 -1 29780 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 296 247 1 157 87 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2143 845 9303 1922 7070 311 64.4 MiB 0.05 0.00 4.04404 3.39881 -108.793 -3.39881 3.39881 0.23 0.000291844 0.000265742 0.0156435 0.0143167 -1 -1 -1 -1 30 2055 22 6.65987e+06 291594 526063. 1820.29 0.36 0.0577119 0.0509962 22546 126617 -1 1649 20 1059 1884 106086 26424 2.57731 2.57731 -102.381 -2.57731 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0142499 0.0127288 119 34 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 1.66 vpr 63.88 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29940 -1 -1 31 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1494 614 13153 4634 5792 2727 63.9 MiB 0.05 0.00 3.79264 3.36581 -78.5128 -3.36581 3.36581 0.24 0.000221928 0.000202489 0.0164571 0.0150544 -1 -1 -1 -1 32 1365 25 6.65987e+06 393018 554710. 1919.41 0.32 0.0489517 0.0432483 22834 132086 -1 1113 18 614 985 48919 13492 2.53525 2.53525 -71.42 -2.53525 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0126873 0.0114295 93 29 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 1.91 vpr 64.62 MiB -1 -1 0.14 18056 1 0.04 -1 -1 29764 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2264 1147 14323 4224 8035 2064 64.6 MiB 0.10 0.00 5.10524 4.17275 -131.194 -4.17275 4.17275 0.25 0.000342368 0.000312581 0.0307727 0.0283674 -1 -1 -1 -1 32 2473 25 6.65987e+06 304272 554710. 1919.41 0.42 0.0914247 0.0815378 22834 132086 -1 2202 25 1395 2545 160708 39277 3.38805 3.38805 -119.812 -3.38805 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0241588 0.0215803 137 72 -1 -1 -1 -1 +fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 1.77 vpr 64.71 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29792 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2647 860 12702 3275 8213 1214 64.7 MiB 0.08 0.00 4.50335 3.91658 -121.607 -3.91658 3.91658 0.23 0.000366347 0.000329594 0.0216129 0.0197719 -1 -1 -1 -1 32 2045 24 6.65987e+06 532476 554710. 1919.41 0.38 0.0799359 0.0709708 22834 132086 -1 1761 21 1382 2184 119657 31714 2.82571 2.82571 -107.817 -2.82571 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0226136 0.02042 148 90 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_001.v common 4.08 vpr 65.26 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30128 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66828 32 32 354 285 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 0.85 2453 972 10228 4188 5749 291 65.3 MiB 0.06 0.00 6.53897 5.5107 -161.059 -5.5107 5.5107 0.25 0.000360483 0.000330651 0.0301468 0.0280027 -1 -1 -1 -1 48 2385 23 6.95648e+06 231611 865456. 2994.66 1.81 0.152519 0.134344 28354 207349 -1 1961 26 1704 2847 242432 77762 4.53791 4.53791 -149.014 -4.53791 0 0 1.05005e+06 3633.38 0.04 0.08 0.11 -1 -1 0.04 0.0207781 0.0185925 81 50 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 6.05 vpr 64.70 MiB -1 -1 0.13 18444 1 0.03 -1 -1 30380 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 30 32 363 293 1 187 80 17 17 289 -1 unnamed_device 25.5 MiB 1.26 2699 985 12980 3943 7957 1080 64.7 MiB 0.06 0.00 5.32638 4.21658 -134.56 -4.21658 4.21658 0.24 0.000338369 0.000310011 0.0273553 0.0251228 -1 -1 -1 -1 36 2667 32 6.95648e+06 260562 648988. 2245.63 3.39 0.180648 0.159451 26050 158493 -1 2213 23 2112 3019 267785 55858 4.35602 4.35602 -151.278 -4.35602 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0188925 0.0169542 79 63 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_003.v common 3.46 vpr 64.77 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29740 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 25.2 MiB 0.60 2358 1032 12186 3430 7248 1508 64.8 MiB 0.06 0.00 4.71675 3.78245 -119.015 -3.78245 3.78245 0.24 0.000295122 0.000269011 0.022121 0.0202745 -1 -1 -1 -1 40 2414 23 6.95648e+06 260562 706193. 2443.58 1.50 0.121574 0.106131 26914 176310 -1 2051 18 1192 1596 127749 28397 3.76412 3.76412 -125.019 -3.76412 0 0 926341. 3205.33 0.03 0.04 0.09 -1 -1 0.03 0.0170379 0.0152769 74 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_004.v common 3.41 vpr 64.20 MiB -1 -1 0.12 18048 1 0.04 -1 -1 29756 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 29 32 308 248 1 162 84 17 17 289 -1 unnamed_device 25.2 MiB 0.18 2112 720 13077 5176 5901 2000 64.2 MiB 0.06 0.00 4.84222 3.96328 -113.617 -3.96328 3.96328 0.25 0.000302052 0.000274458 0.0235956 0.0215408 -1 -1 -1 -1 40 2085 22 6.95648e+06 332941 706193. 2443.58 1.80 0.148459 0.129635 26914 176310 -1 1621 23 1506 2612 185027 44223 3.91416 3.91416 -121.795 -3.91416 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0165964 0.014824 73 31 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 2.47 vpr 64.86 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29800 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 32 32 336 268 1 167 85 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1783 1032 10315 2877 5917 1521 64.9 MiB 0.05 0.00 4.51952 3.92812 -130.309 -3.92812 3.92812 0.25 0.000322632 0.000292025 0.0200178 0.0182508 -1 -1 -1 -1 38 2695 38 6.95648e+06 303989 678818. 2348.85 0.88 0.0962041 0.0849132 26626 170182 -1 2290 20 1586 2944 220343 47674 3.95326 3.95326 -137.892 -3.95326 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0177714 0.0159486 76 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 2.99 vpr 65.46 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67028 32 32 366 295 1 182 89 17 17 289 -1 unnamed_device 25.6 MiB 0.25 1940 1017 15137 4323 9926 888 65.5 MiB 0.08 0.00 3.4886 3.1127 -116.972 -3.1127 3.1127 0.25 0.0003474 0.00031008 0.0306325 0.0281225 -1 -1 -1 -1 36 2556 21 6.95648e+06 361892 648988. 2245.63 1.35 0.148265 0.129937 26050 158493 -1 2163 22 1481 2233 179619 40338 3.25947 3.25947 -126.143 -3.25947 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0190004 0.0170065 81 58 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 5.15 vpr 64.68 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30108 -1 -1 14 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 27 32 259 221 1 124 73 17 17 289 -1 unnamed_device 25.2 MiB 2.03 1479 544 11169 5105 5436 628 64.7 MiB 0.04 0.00 3.66833 3.46173 -93.1309 -3.46173 3.46173 0.25 0.000261857 0.000239568 0.0209747 0.0192546 -1 -1 -1 -1 38 1555 46 6.95648e+06 202660 678818. 2348.85 1.71 0.145141 0.126544 26626 170182 -1 1272 22 1128 1830 194540 63071 2.72212 2.72212 -92.3383 -2.72212 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0173633 0.0154463 52 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_008.v common 2.44 vpr 65.14 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30192 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 25.2 MiB 0.13 1731 837 13758 3354 9842 562 65.1 MiB 0.06 0.00 3.236 3.0033 -96.4877 -3.0033 3.0033 0.25 0.000283257 0.000257476 0.0224466 0.0205166 -1 -1 -1 -1 38 2185 35 6.95648e+06 390843 678818. 2348.85 0.94 0.0935904 0.0819904 26626 170182 -1 1935 17 1016 1691 155726 37439 2.85232 2.85232 -101.969 -2.85232 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0128395 0.0115411 69 4 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_009.v common 6.46 vpr 65.11 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30160 -1 -1 13 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 31 32 317 271 1 163 76 17 17 289 -1 unnamed_device 25.4 MiB 1.02 2045 984 6476 1579 4344 553 65.1 MiB 0.04 0.00 4.38541 3.20949 -116.851 -3.20949 3.20949 0.25 0.000304035 0.000278359 0.0141149 0.0129919 -1 -1 -1 -1 38 2225 23 6.95648e+06 188184 678818. 2348.85 4.11 0.175878 0.153736 26626 170182 -1 1916 23 1238 1764 156025 32304 3.10437 3.10437 -120.049 -3.10437 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0167635 0.0150094 63 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_010.v common 2.47 vpr 64.80 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29756 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 298 248 1 150 75 17 17 289 -1 unnamed_device 25.2 MiB 0.52 1624 626 11135 4403 5579 1153 64.8 MiB 0.05 0.00 3.54488 3.30308 -115.111 -3.30308 3.30308 0.25 0.000294589 0.000269238 0.0240851 0.0221711 -1 -1 -1 -1 40 1722 35 6.95648e+06 159232 706193. 2443.58 0.62 0.0818033 0.0720409 26914 176310 -1 1420 24 1290 1850 123276 30882 3.09812 3.09812 -112.612 -3.09812 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.0168038 0.0149627 60 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_011.v common 4.11 vpr 64.83 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29584 -1 -1 12 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 30 32 303 262 1 135 74 17 17 289 -1 unnamed_device 25.2 MiB 0.66 1495 729 9064 2569 5999 496 64.8 MiB 0.04 0.00 3.68438 3.28838 -103.976 -3.28838 3.28838 0.24 0.000292096 0.000267169 0.0187869 0.0172538 -1 -1 -1 -1 34 1814 26 6.95648e+06 173708 618332. 2139.56 2.16 0.138849 0.120791 25762 151098 -1 1490 24 1184 1664 130152 30363 3.42052 3.42052 -114.288 -3.42052 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0178223 0.0157866 54 63 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 6.43 vpr 65.00 MiB -1 -1 0.13 17672 1 0.03 -1 -1 30076 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 32 32 276 237 1 161 77 17 17 289 -1 unnamed_device 25.2 MiB 0.89 1858 901 11324 2936 7996 392 65.0 MiB 0.05 0.00 4.14163 3.40773 -113.867 -3.40773 3.40773 0.25 0.000320972 0.000297119 0.0219671 0.0201439 -1 -1 -1 -1 38 2225 33 6.95648e+06 188184 678818. 2348.85 4.06 0.177221 0.15457 26626 170182 -1 1830 23 1206 1558 121613 27198 3.12917 3.12917 -117.675 -3.12917 0 0 902133. 3121.57 0.03 0.04 0.10 -1 -1 0.03 0.0181981 0.0163783 61 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_013.v common 7.28 vpr 64.84 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29752 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 344 272 1 194 81 17 17 289 -1 unnamed_device 25.2 MiB 1.00 2661 1052 13556 4454 6679 2423 64.8 MiB 0.07 0.00 4.95968 4.03143 -135.537 -4.03143 4.03143 0.24 0.000326325 0.000299541 0.0282066 0.0259143 -1 -1 -1 -1 38 2740 31 6.95648e+06 246087 678818. 2348.85 4.74 0.196684 0.172533 26626 170182 -1 2270 20 1490 2238 167680 36771 3.49922 3.49922 -132.659 -3.49922 0 0 902133. 3121.57 0.04 0.07 0.13 -1 -1 0.04 0.0232164 0.0208544 80 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_014.v common 3.32 vpr 65.40 MiB -1 -1 0.19 18056 1 0.04 -1 -1 30120 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66968 32 32 363 295 1 174 89 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2639 1006 16721 5083 10286 1352 65.4 MiB 0.07 0.00 5.50502 4.26608 -134.261 -4.26608 4.26608 0.24 0.000347966 0.00031851 0.0304499 0.0278639 -1 -1 -1 -1 44 2225 22 6.95648e+06 361892 787024. 2723.27 1.60 0.154803 0.135854 27778 195446 -1 2034 24 1656 2393 186636 39712 3.87492 3.87492 -138.683 -3.87492 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0186054 0.0166199 78 61 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_015.v common 3.30 vpr 64.66 MiB -1 -1 0.19 18060 1 0.03 -1 -1 29916 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 29 32 248 215 1 132 79 17 17 289 -1 unnamed_device 25.6 MiB 0.37 1589 651 12078 4589 5218 2271 64.7 MiB 0.05 0.00 3.39735 2.90715 -89.179 -2.90715 2.90715 0.25 0.000252159 0.00023083 0.0201331 0.0184469 -1 -1 -1 -1 32 1836 31 6.95648e+06 260562 586450. 2029.24 1.34 0.118347 0.102735 25474 144626 -1 1503 20 997 1583 125466 28770 3.05702 3.05702 -99.4476 -3.05702 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0205365 0.0182302 55 27 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 2.73 vpr 64.73 MiB -1 -1 0.12 18060 1 0.04 -1 -1 29784 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 370 297 1 178 81 17 17 289 -1 unnamed_device 25.6 MiB 0.39 2049 1029 11981 3954 6378 1649 64.7 MiB 0.06 0.00 3.37235 3.1427 -120.775 -3.1427 3.1427 0.25 0.00035851 0.000328148 0.0268688 0.0246765 -1 -1 -1 -1 36 2643 31 6.95648e+06 246087 648988. 2245.63 0.88 0.10544 0.0937733 26050 158493 -1 2255 24 1811 2949 246149 54989 3.28927 3.28927 -130.375 -3.28927 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0197367 0.0176201 77 58 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 4.33 vpr 65.27 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29808 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66840 32 32 338 269 1 190 81 17 17 289 -1 unnamed_device 26.0 MiB 1.14 2597 1132 10756 3252 6270 1234 65.3 MiB 0.09 0.00 4.76516 3.87916 -128.033 -3.87916 3.87916 0.27 0.000563673 0.000514764 0.0381079 0.0349105 -1 -1 -1 -1 42 2528 39 6.95648e+06 246087 744469. 2576.02 1.76 0.175647 0.154706 27202 183097 -1 2217 22 1720 2455 228601 47027 3.26597 3.26597 -129.76 -3.26597 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0178021 0.0160045 78 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_018.v common 2.86 vpr 64.37 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30132 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 32 32 323 276 1 148 80 17 17 289 -1 unnamed_device 25.1 MiB 0.47 1940 709 13324 5680 7328 316 64.4 MiB 0.06 0.00 2.8806 2.25046 -92.451 -2.25046 2.25046 0.24 0.000321601 0.000294567 0.0263952 0.0242186 -1 -1 -1 -1 38 2063 49 6.95648e+06 231611 678818. 2348.85 1.00 0.109513 0.096137 26626 170182 -1 1469 19 1138 1719 118571 27421 2.31168 2.31168 -99.7954 -2.31168 0 0 902133. 3121.57 0.04 0.04 0.11 -1 -1 0.04 0.0146975 0.0132061 61 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_019.v common 2.39 vpr 64.57 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29840 -1 -1 11 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 30 32 222 206 1 114 73 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1511 777 10865 4570 5988 307 64.6 MiB 0.04 0.00 2.51091 2.19546 -86.0348 -2.19546 2.19546 0.24 0.000228699 0.000208066 0.0176833 0.0161505 -1 -1 -1 -1 30 1680 41 6.95648e+06 159232 556674. 1926.21 1.04 0.0942002 0.0812793 25186 138497 -1 1470 25 872 1208 156123 52175 2.24868 2.24868 -93.6233 -2.24868 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0130512 0.0115238 44 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_020.v common 4.25 vpr 65.08 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29832 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66644 31 32 291 243 1 167 77 17 17 289 -1 unnamed_device 25.2 MiB 1.28 1942 915 11161 3690 6402 1069 65.1 MiB 0.05 0.00 5.06493 4.53133 -147.051 -4.53133 4.53133 0.25 0.000298558 0.000268472 0.0217239 0.0198683 -1 -1 -1 -1 36 2497 27 6.95648e+06 202660 648988. 2245.63 1.65 0.13307 0.116025 26050 158493 -1 2085 22 1516 2176 182935 41144 4.25897 4.25897 -152.532 -4.25897 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0156028 0.0139499 68 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 4.09 vpr 65.23 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30352 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66792 32 32 342 271 1 172 91 17 17 289 -1 unnamed_device 26.0 MiB 0.15 2240 900 16819 7148 9182 489 65.2 MiB 0.09 0.00 4.59829 3.69419 -127.892 -3.69419 3.69419 0.25 0.000327843 0.000299751 0.0411088 0.0379383 -1 -1 -1 -1 36 2377 35 6.95648e+06 390843 648988. 2245.63 2.54 0.186161 0.164863 26050 158493 -1 1845 26 1702 2575 179217 41202 3.87196 3.87196 -134.248 -3.87196 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0217552 0.0194069 79 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_022.v common 7.73 vpr 65.38 MiB -1 -1 0.18 17676 1 0.03 -1 -1 30120 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66948 32 32 372 300 1 200 80 17 17 289 -1 unnamed_device 25.6 MiB 0.78 2415 1121 6444 1474 4751 219 65.4 MiB 0.04 0.00 5.37301 4.45576 -133.655 -4.45576 4.45576 0.26 0.00035798 0.00032954 0.0151061 0.0139068 -1 -1 -1 -1 38 2880 26 6.95648e+06 231611 678818. 2348.85 5.52 0.175453 0.15353 26626 170182 -1 2526 22 1727 2641 222774 46845 4.34031 4.34031 -139.36 -4.34031 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0185616 0.0166569 82 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_023.v common 2.66 vpr 64.47 MiB -1 -1 0.10 18060 1 0.02 -1 -1 30160 -1 -1 15 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66020 26 32 190 182 1 104 73 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1222 421 8281 3372 4348 561 64.5 MiB 0.03 0.00 2.67211 2.19726 -65.4152 -2.19726 2.19726 0.26 0.000228356 0.00020948 0.0126875 0.0116165 -1 -1 -1 -1 34 1125 29 6.95648e+06 217135 618332. 2139.56 1.06 0.0810129 0.0700315 25762 151098 -1 896 17 520 688 56109 14316 2.11048 2.11048 -70.2765 -2.11048 0 0 787024. 2723.27 0.04 0.03 0.12 -1 -1 0.04 0.0133129 0.0119175 44 30 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_024.v common 6.89 vpr 64.69 MiB -1 -1 0.10 17676 1 0.03 -1 -1 29772 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 285 227 1 159 81 17 17 289 -1 unnamed_device 25.2 MiB 0.35 1875 1004 10231 3152 5666 1413 64.7 MiB 0.06 0.00 5.1927 4.35141 -124.49 -4.35141 4.35141 0.25 0.000474772 0.000449994 0.0235867 0.0218554 -1 -1 -1 -1 36 2522 34 6.95648e+06 246087 648988. 2245.63 5.19 0.179034 0.157958 26050 158493 -1 2149 24 1520 2509 215703 44929 4.03036 4.03036 -133.912 -4.03036 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0165415 0.0147724 66 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 2.43 vpr 64.38 MiB -1 -1 0.09 17676 1 0.02 -1 -1 30096 -1 -1 10 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 25.1 MiB 0.07 1407 728 7049 2858 4069 122 64.4 MiB 0.02 0.00 2.65931 2.13126 -73.9387 -2.13126 2.13126 0.35 0.000195657 0.000177916 0.0099747 0.00911854 -1 -1 -1 -1 32 1341 22 6.95648e+06 144757 586450. 2029.24 1.01 0.0883843 0.0759555 25474 144626 -1 1180 22 633 749 76305 16284 2.09038 2.09038 -81.6951 -2.09038 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0107041 0.00951017 43 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_026.v common 5.27 vpr 65.07 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29532 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 300 245 1 159 83 17 17 289 -1 unnamed_device 25.2 MiB 0.32 1864 913 6383 1452 4629 302 65.1 MiB 0.04 0.00 5.25865 4.40051 -125.247 -4.40051 4.40051 0.26 0.000324656 0.000298873 0.0125488 0.0115213 -1 -1 -1 -1 34 2450 32 6.95648e+06 275038 618332. 2139.56 3.53 0.144068 0.12555 25762 151098 -1 1968 22 1275 2064 154484 34551 3.92096 3.92096 -128.528 -3.92096 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0158121 0.0141592 67 24 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_027.v common 3.01 vpr 64.59 MiB -1 -1 0.15 17912 1 0.04 -1 -1 29932 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 25.6 MiB 0.11 1827 924 6823 1513 4978 332 64.6 MiB 0.04 0.00 3.55265 2.9965 -104.682 -2.9965 2.9965 0.25 0.000516058 0.000468551 0.0159334 0.0147054 -1 -1 -1 -1 36 2414 49 6.95648e+06 390843 648988. 2245.63 1.42 0.124523 0.109913 26050 158493 -1 2132 24 1474 2395 199348 43414 3.61137 3.61137 -119.408 -3.61137 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0172033 0.015398 77 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_028.v common 8.45 vpr 64.66 MiB -1 -1 0.12 18036 1 0.04 -1 -1 30072 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 338 277 1 172 87 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2669 874 15063 4561 8642 1860 64.7 MiB 0.07 0.00 5.40282 4.22168 -126.749 -4.22168 4.22168 0.24 0.000319671 0.000291658 0.02712 0.0248042 -1 -1 -1 -1 36 2848 47 6.95648e+06 332941 648988. 2245.63 6.44 0.185299 0.162867 26050 158493 -1 2116 21 1518 2498 224468 49562 4.10051 4.10051 -134.747 -4.10051 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0182949 0.0163777 74 50 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_029.v common 3.03 vpr 64.75 MiB -1 -1 0.19 17676 1 0.02 -1 -1 29812 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 284 241 1 139 79 17 17 289 -1 unnamed_device 25.6 MiB 0.33 1680 676 6670 1523 4966 181 64.7 MiB 0.04 0.00 3.27205 2.9051 -100.648 -2.9051 2.9051 0.24 0.000284299 0.000260273 0.0131353 0.012032 -1 -1 -1 -1 42 1765 28 6.95648e+06 217135 744469. 2576.02 1.26 0.115797 0.100284 27202 183097 -1 1497 22 1119 1800 140720 33242 2.86952 2.86952 -107.095 -2.86952 0 0 949917. 3286.91 0.03 0.04 0.10 -1 -1 0.03 0.0149791 0.0133634 57 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_030.v common 2.72 vpr 64.80 MiB -1 -1 0.14 18060 1 0.02 -1 -1 29852 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 30 32 262 227 1 134 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1538 820 8831 2040 6273 518 64.8 MiB 0.05 0.00 3.47888 3.21595 -101.099 -3.21595 3.21595 0.36 0.000386212 0.000355056 0.0224496 0.020607 -1 -1 -1 -1 32 1847 36 6.95648e+06 275038 586450. 2029.24 1.08 0.108432 0.0945639 25474 144626 -1 1689 22 1091 1749 148756 32107 3.02582 3.02582 -108.609 -3.02582 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0174901 0.0155263 59 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_031.v common 4.82 vpr 64.29 MiB -1 -1 0.14 16988 1 0.03 -1 -1 29608 -1 -1 21 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 28 32 260 223 1 135 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1490 680 8131 2137 5414 580 64.3 MiB 0.04 0.00 3.44925 2.9041 -94.451 -2.9041 2.9041 0.25 0.000306648 0.000271689 0.0168356 0.0155005 -1 -1 -1 -1 36 1823 27 6.95648e+06 303989 648988. 2245.63 3.31 0.15174 0.132313 26050 158493 -1 1652 18 950 1569 148138 33466 3.16212 3.16212 -107.018 -3.16212 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0121723 0.0109062 60 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_032.v common 3.39 vpr 64.12 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29812 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65664 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 24.9 MiB 0.12 1566 824 4152 861 3106 185 64.1 MiB 0.03 0.00 3.63718 3.35753 -114.051 -3.35753 3.35753 0.26 0.000266189 0.000243736 0.0126143 0.0117093 -1 -1 -1 -1 38 1997 21 6.95648e+06 188184 678818. 2348.85 1.83 0.153 0.132863 26626 170182 -1 1719 21 1284 1950 159352 33411 2.89152 2.89152 -114.478 -2.89152 0 0 902133. 3121.57 0.03 0.04 0.12 -1 -1 0.03 0.0157463 0.0139925 59 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_033.v common 3.90 vpr 64.73 MiB -1 -1 0.20 17676 1 0.02 -1 -1 29760 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 31 32 271 231 1 143 80 17 17 289 -1 unnamed_device 25.2 MiB 0.11 1688 869 8680 2729 4472 1479 64.7 MiB 0.04 0.00 3.72648 3.16398 -108.388 -3.16398 3.16398 0.25 0.00027281 0.000249896 0.0156627 0.0143815 -1 -1 -1 -1 34 2179 22 6.95648e+06 246087 618332. 2139.56 2.41 0.131565 0.114533 25762 151098 -1 2014 21 1110 1930 166652 35472 3.09012 3.09012 -116.571 -3.09012 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0141418 0.0126396 60 30 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_034.v common 4.04 vpr 65.15 MiB -1 -1 0.16 18056 1 0.02 -1 -1 29796 -1 -1 20 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 29 32 291 250 1 148 81 17 17 289 -1 unnamed_device 25.2 MiB 0.55 1854 689 13206 5558 7105 543 65.1 MiB 0.06 0.00 2.91366 2.41246 -87.9827 -2.41246 2.41246 0.25 0.000281282 0.000256616 0.0241148 0.0221193 -1 -1 -1 -1 36 2057 43 6.95648e+06 289514 648988. 2245.63 1.88 0.158976 0.138171 26050 158493 -1 1583 29 1369 1971 208107 67819 2.98053 2.98053 -102.288 -2.98053 0 0 828058. 2865.25 0.03 0.07 0.09 -1 -1 0.03 0.0181052 0.0160143 63 54 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_035.v common 7.24 vpr 64.71 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29616 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 367 282 1 193 97 17 17 289 -1 unnamed_device 25.6 MiB 0.21 2526 1025 17413 5779 8975 2659 64.7 MiB 0.08 0.00 5.03788 4.17868 -123.252 -4.17868 4.17868 0.25 0.000357228 0.000325244 0.030235 0.0275701 -1 -1 -1 -1 42 2595 19 6.95648e+06 477698 744469. 2576.02 5.55 0.206893 0.181707 27202 183097 -1 2211 31 1710 2988 296315 99088 3.69472 3.69472 -122.109 -3.69472 0 0 949917. 3286.91 0.03 0.09 0.11 -1 -1 0.03 0.0247971 0.0221375 91 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_036.v common 3.70 vpr 65.41 MiB -1 -1 0.12 18300 1 0.03 -1 -1 29748 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 391 311 1 184 96 17 17 289 -1 unnamed_device 25.6 MiB 0.38 2256 862 16740 6194 8330 2216 65.4 MiB 0.08 0.00 3.74582 3.41048 -122.287 -3.41048 3.41048 0.34 0.000358304 0.000326722 0.0296809 0.0270057 -1 -1 -1 -1 44 2238 38 6.95648e+06 463222 787024. 2723.27 1.75 0.167056 0.145504 27778 195446 -1 1850 25 2011 3068 224363 51977 3.35632 3.35632 -126.689 -3.35632 0 0 997811. 3452.63 0.04 0.06 0.12 -1 -1 0.04 0.0204384 0.0182152 88 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_037.v common 3.57 vpr 64.55 MiB -1 -1 0.12 18052 1 0.02 -1 -1 30172 -1 -1 13 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 31 32 279 237 1 159 76 17 17 289 -1 unnamed_device 25.5 MiB 0.74 1859 944 11436 4031 5937 1468 64.6 MiB 0.05 0.00 4.42062 3.66882 -116.881 -3.66882 3.66882 0.25 0.000536804 0.000511655 0.0225096 0.020716 -1 -1 -1 -1 40 2026 25 6.95648e+06 188184 706193. 2443.58 1.40 0.115557 0.10067 26914 176310 -1 1930 22 1362 1958 174593 39631 3.25737 3.25737 -121.471 -3.25737 0 0 926341. 3205.33 0.03 0.05 0.13 -1 -1 0.03 0.0175896 0.015843 65 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_038.v common 3.50 vpr 64.73 MiB -1 -1 0.13 18060 1 0.04 -1 -1 30156 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 31 32 370 297 1 179 82 17 17 289 -1 unnamed_device 26.0 MiB 0.37 2058 981 11474 4741 6449 284 64.7 MiB 0.06 0.00 4.15263 3.41873 -120.517 -3.41873 3.41873 0.25 0.000343553 0.000314072 0.0242446 0.0222411 -1 -1 -1 -1 36 2791 28 6.95648e+06 275038 648988. 2245.63 1.51 0.113157 0.100064 26050 158493 -1 2313 25 1860 2917 241256 52575 3.29867 3.29867 -128.902 -3.29867 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0199085 0.017774 78 61 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_039.v common 4.99 vpr 65.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29748 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67020 31 32 377 302 1 231 84 17 17 289 -1 unnamed_device 26.0 MiB 1.01 2986 1206 16188 5856 7795 2537 65.4 MiB 0.09 0.00 6.98421 5.23991 -167.77 -5.23991 5.23991 0.24 0.000345786 0.000316332 0.0397705 0.0366514 -1 -1 -1 -1 44 3341 26 6.95648e+06 303989 787024. 2723.27 2.49 0.212114 0.187739 27778 195446 -1 2677 24 2355 3504 330191 67709 4.75275 4.75275 -167.178 -4.75275 0 0 997811. 3452.63 0.04 0.07 0.11 -1 -1 0.04 0.0199259 0.0178701 99 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_040.v common 3.87 vpr 65.04 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30152 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 31 32 383 305 1 201 80 17 17 289 -1 unnamed_device 25.6 MiB 1.19 2460 938 14012 6050 7484 478 65.0 MiB 0.07 0.00 5.07595 4.39319 -147.97 -4.39319 4.39319 0.30 0.000353719 0.000323381 0.0319885 0.0293714 -1 -1 -1 -1 46 2574 33 6.95648e+06 246087 828058. 2865.25 1.19 0.122738 0.108773 28066 200906 -1 2087 21 1723 2601 166326 39721 4.33271 4.33271 -148.753 -4.33271 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0184975 0.0166052 88 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_041.v common 6.56 vpr 63.99 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65524 31 32 352 285 1 177 86 17 17 289 -1 unnamed_device 25.3 MiB 0.61 1905 1063 13505 4619 6904 1982 64.0 MiB 0.07 0.00 3.86153 3.50353 -122.837 -3.50353 3.50353 0.25 0.000334119 0.000306413 0.0260397 0.023895 -1 -1 -1 -1 38 2691 24 6.95648e+06 332941 678818. 2348.85 4.55 0.175979 0.154524 26626 170182 -1 2207 20 1543 2431 175549 38503 3.17607 3.17607 -124.233 -3.17607 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0179781 0.0161697 79 55 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_042.v common 2.72 vpr 65.22 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66788 32 32 291 242 1 173 82 17 17 289 -1 unnamed_device 25.4 MiB 0.58 2234 1084 10050 2925 5856 1269 65.2 MiB 0.05 0.00 5.02688 4.05268 -121.011 -4.05268 4.05268 0.24 0.000289648 0.000264781 0.018507 0.0170161 -1 -1 -1 -1 36 2592 25 6.95648e+06 260562 648988. 2245.63 0.78 0.0776036 0.068171 26050 158493 -1 2252 21 1397 2007 181674 36928 3.91432 3.91432 -125.021 -3.91432 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0149357 0.0133601 70 27 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_043.v common 8.70 vpr 65.39 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30288 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 32 32 457 356 1 214 92 17 17 289 -1 unnamed_device 26.0 MiB 0.61 3011 1199 9614 2248 6243 1123 65.4 MiB 0.06 0.00 5.60998 4.24958 -145.469 -4.24958 4.24958 0.25 0.000422765 0.000388597 0.0221656 0.0203896 -1 -1 -1 -1 36 3239 50 6.95648e+06 405319 648988. 2245.63 6.67 0.281134 0.247038 26050 158493 -1 2666 23 2075 3298 272107 58339 4.23492 4.23492 -151.925 -4.23492 0 0 828058. 2865.25 0.03 0.07 0.09 -1 -1 0.03 0.0229493 0.0205874 97 87 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_044.v common 1.98 vpr 64.71 MiB -1 -1 0.11 17912 1 0.02 -1 -1 30264 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 261 225 1 138 80 17 17 289 -1 unnamed_device 25.6 MiB 0.21 1501 818 9024 2908 5023 1093 64.7 MiB 0.04 0.00 3.4146 3.0387 -101.681 -3.0387 3.0387 0.25 0.000266387 0.000243369 0.0156035 0.0143094 -1 -1 -1 -1 32 2004 40 6.95648e+06 246087 586450. 2029.24 0.49 0.0599967 0.0526947 25474 144626 -1 1709 22 1202 1786 156398 34480 3.27367 3.27367 -111.108 -3.27367 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0143091 0.0127558 58 28 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_045.v common 4.00 vpr 64.32 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29872 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 31 32 337 267 1 199 81 17 17 289 -1 unnamed_device 25.6 MiB 0.71 2145 1112 10931 4151 5627 1153 64.3 MiB 0.06 0.00 4.85719 4.35599 -139.539 -4.35599 4.35599 0.25 0.000344925 0.000316949 0.0228979 0.021019 -1 -1 -1 -1 46 2578 27 6.95648e+06 260562 828058. 2865.25 1.80 0.152247 0.133516 28066 200906 -1 2222 20 1385 2128 175307 36107 4.35122 4.35122 -143.095 -4.35122 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0206612 0.0185831 82 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 5.18 vpr 65.28 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29724 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 349 284 1 175 90 17 17 289 -1 unnamed_device 25.6 MiB 0.32 2157 965 10542 2851 6614 1077 65.3 MiB 0.06 0.00 3.52265 3.1127 -108.745 -3.1127 3.1127 0.24 0.000330891 0.000302135 0.0192964 0.0176786 -1 -1 -1 -1 36 2961 34 6.95648e+06 376368 648988. 2245.63 3.51 0.168227 0.14795 26050 158493 -1 2355 20 1415 2400 212790 47241 3.46317 3.46317 -122.988 -3.46317 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0163403 0.0146583 78 53 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_047.v common 4.70 vpr 65.20 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29816 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 32 32 291 230 1 161 83 17 17 289 -1 unnamed_device 25.6 MiB 0.22 1764 988 11603 4009 6122 1472 65.2 MiB 0.05 0.00 4.66672 3.99627 -123.227 -3.99627 3.99627 0.25 0.000450265 0.000422578 0.0219192 0.0201582 -1 -1 -1 -1 36 2563 29 6.95648e+06 275038 648988. 2245.63 2.93 0.158681 0.13936 26050 158493 -1 2183 22 1428 2520 202696 44123 3.83276 3.83276 -133.9 -3.83276 0 0 828058. 2865.25 0.04 0.08 0.14 -1 -1 0.04 0.0269728 0.0241938 70 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_048.v common 3.77 vpr 65.38 MiB -1 -1 0.17 18056 1 0.04 -1 -1 30056 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 353 287 1 190 80 17 17 289 -1 unnamed_device 25.6 MiB 1.14 2163 1097 11948 3658 6620 1670 65.4 MiB 0.06 0.00 4.63715 4.346 -136.985 -4.346 4.346 0.27 0.000328162 0.000300805 0.0253231 0.0232672 -1 -1 -1 -1 34 2975 47 6.95648e+06 231611 618332. 2139.56 0.96 0.10334 0.0912855 25762 151098 -1 2354 20 1518 2047 175086 38630 3.82676 3.82676 -139.13 -3.82676 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0164645 0.014809 76 55 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_049.v common 2.80 vpr 65.41 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66976 32 32 361 291 1 178 93 17 17 289 -1 unnamed_device 25.6 MiB 0.36 2190 1077 15423 4714 8722 1987 65.4 MiB 0.07 0.00 3.80407 3.1427 -117.276 -3.1427 3.1427 0.24 0.000335494 0.00030613 0.0268972 0.0246316 -1 -1 -1 -1 36 2642 22 6.95648e+06 419795 648988. 2245.63 1.07 0.115534 0.102164 26050 158493 -1 2227 23 1499 2470 188526 40710 3.00577 3.00577 -119.751 -3.00577 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0206086 0.0184721 81 55 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_050.v common 3.78 vpr 65.39 MiB -1 -1 0.21 18056 1 0.04 -1 -1 29324 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66960 32 32 382 305 1 184 92 17 17 289 -1 unnamed_device 26.0 MiB 0.26 1992 927 11891 3545 6012 2334 65.4 MiB 0.06 0.00 4.22719 3.72599 -122.298 -3.72599 3.72599 0.25 0.000354423 0.000324206 0.022889 0.0209982 -1 -1 -1 -1 38 2841 35 6.95648e+06 405319 678818. 2348.85 1.97 0.123296 0.108865 26626 170182 -1 2185 23 1596 2460 203199 45565 3.39842 3.39842 -128.958 -3.39842 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0194308 0.0173982 86 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_051.v common 3.43 vpr 64.74 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29772 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66292 32 32 306 248 1 160 86 17 17 289 -1 unnamed_device 25.2 MiB 0.41 1773 991 12182 3165 8076 941 64.7 MiB 0.06 0.00 4.66977 4.24147 -124.389 -4.24147 4.24147 0.25 0.000303542 0.000277176 0.0212523 0.0194711 -1 -1 -1 -1 44 2187 23 6.95648e+06 318465 787024. 2723.27 1.56 0.130789 0.114575 27778 195446 -1 1919 20 1150 1977 158945 33393 3.70736 3.70736 -126.727 -3.70736 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0150716 0.01354 70 24 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_052.v common 3.63 vpr 64.13 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29560 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 32 32 319 257 1 191 81 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2389 1129 13556 4515 7064 1977 64.1 MiB 0.07 0.00 5.21638 4.27023 -132.909 -4.27023 4.27023 0.25 0.00032728 0.00029993 0.0285934 0.0263253 -1 -1 -1 -1 46 2261 24 6.95648e+06 246087 828058. 2865.25 1.56 0.139003 0.122239 28066 200906 -1 2053 19 1489 2067 148493 32149 3.91922 3.91922 -135.811 -3.91922 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0243854 0.0220312 78 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_053.v common 4.48 vpr 64.78 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29732 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 373 299 1 197 80 17 17 289 -1 unnamed_device 26.0 MiB 0.83 2531 897 9540 3871 5214 455 64.8 MiB 0.05 0.00 5.05188 4.17558 -131.538 -4.17558 4.17558 0.25 0.00034728 0.000317831 0.022077 0.0202609 -1 -1 -1 -1 52 2602 45 6.95648e+06 246087 926341. 3205.33 2.17 0.168751 0.148119 29218 227130 -1 1929 23 1708 2759 217252 49174 3.83221 3.83221 -127.134 -3.83221 0 0 1.14541e+06 3963.36 0.04 0.05 0.12 -1 -1 0.04 0.0187353 0.0168008 84 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_054.v common 8.14 vpr 65.36 MiB -1 -1 0.18 18296 1 0.03 -1 -1 30104 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66928 32 32 387 315 1 182 79 17 17 289 -1 unnamed_device 25.6 MiB 0.44 1967 1073 7177 2229 3943 1005 65.4 MiB 0.04 0.00 4.52855 3.87614 -130.615 -3.87614 3.87614 0.31 0.000389174 0.000358475 0.0179409 0.0165194 -1 -1 -1 -1 36 3074 47 6.95648e+06 217135 648988. 2245.63 6.15 0.265094 0.23242 26050 158493 -1 2610 24 1796 3077 296639 62485 4.18392 4.18392 -145.171 -4.18392 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.020107 0.0180066 76 77 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_055.v common 2.83 vpr 64.64 MiB -1 -1 0.10 17912 1 0.02 -1 -1 29788 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 251 219 1 136 80 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1592 878 8852 2868 4758 1226 64.6 MiB 0.04 0.00 3.87998 3.17038 -103.769 -3.17038 3.17038 0.25 0.000264988 0.00024193 0.0149789 0.0137099 -1 -1 -1 -1 36 2026 24 6.95648e+06 231611 648988. 2245.63 1.46 0.117846 0.102121 26050 158493 -1 1799 19 1076 1732 149430 31991 3.22042 3.22042 -107.606 -3.22042 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0127789 0.0114464 56 23 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_056.v common 3.40 vpr 65.29 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29828 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66860 32 32 341 285 1 183 78 17 17 289 -1 unnamed_device 25.2 MiB 0.73 1846 1064 9706 3019 5412 1275 65.3 MiB 0.05 0.00 3.60009 3.47479 -130.861 -3.47479 3.47479 0.25 0.000773114 0.000715199 0.0212245 0.0194564 -1 -1 -1 -1 40 2587 46 6.95648e+06 202660 706193. 2443.58 1.27 0.118264 0.104074 26914 176310 -1 2232 22 1763 2514 248265 50335 3.32827 3.32827 -135.378 -3.32827 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0173627 0.0155392 72 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_057.v common 4.17 vpr 65.05 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30200 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 32 32 387 293 1 226 82 17 17 289 -1 unnamed_device 25.5 MiB 0.60 2660 1172 13076 5502 7259 315 65.0 MiB 0.07 0.00 5.95448 4.84692 -154.661 -4.84692 4.84692 0.25 0.000367204 0.000336088 0.0295512 0.0270804 -1 -1 -1 -1 46 3443 25 6.95648e+06 260562 828058. 2865.25 2.08 0.175334 0.154048 28066 200906 -1 2694 32 2085 3257 431955 154928 5.30886 5.30886 -163.334 -5.30886 0 0 1.01997e+06 3529.29 0.04 0.12 0.11 -1 -1 0.04 0.0268485 0.0240574 95 31 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_058.v common 3.02 vpr 65.37 MiB -1 -1 0.13 17916 1 0.03 -1 -1 30352 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66936 32 32 340 270 1 174 84 17 17 289 -1 unnamed_device 25.6 MiB 0.40 1785 1004 12162 4142 6583 1437 65.4 MiB 0.06 0.00 3.74951 3.62421 -127.524 -3.62421 3.62421 0.25 0.000328207 0.000300371 0.0237712 0.0218108 -1 -1 -1 -1 34 2614 24 6.95648e+06 289514 618332. 2139.56 1.06 0.099806 0.0878389 25762 151098 -1 2197 22 1673 2441 224418 54031 3.16082 3.16082 -132.565 -3.16082 0 0 787024. 2723.27 0.05 0.10 0.14 -1 -1 0.05 0.0315226 0.0283479 75 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_059.v common 3.39 vpr 64.27 MiB -1 -1 0.12 17532 1 0.02 -1 -1 29796 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 30 32 278 235 1 143 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1631 823 9181 2114 6505 562 64.3 MiB 0.05 0.00 3.34415 2.9573 -102.523 -2.9573 2.9573 0.26 0.00028315 0.000259772 0.0223587 0.0207038 -1 -1 -1 -1 36 1928 25 6.95648e+06 275038 648988. 2245.63 1.83 0.127391 0.111338 26050 158493 -1 1722 21 1126 1816 175406 51035 3.20612 3.20612 -118.395 -3.20612 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0163952 0.0145539 61 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_060.v common 9.47 vpr 65.29 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29820 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66856 32 32 431 332 1 227 82 17 17 289 -1 unnamed_device 25.6 MiB 0.98 2894 1372 10584 3239 6480 865 65.3 MiB 0.07 0.00 6.27232 5.48274 -168.026 -5.48274 5.48274 0.24 0.000400481 0.000366473 0.0260854 0.0239812 -1 -1 -1 -1 40 3261 24 6.95648e+06 260562 706193. 2443.58 7.07 0.217311 0.190731 26914 176310 -1 2808 20 2067 3042 240600 51699 5.01116 5.01116 -171.359 -5.01116 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0201692 0.0181833 94 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 3.66 vpr 64.59 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30340 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 32 32 336 268 1 169 89 17 17 289 -1 unnamed_device 25.2 MiB 0.69 1948 1025 14147 4356 8052 1739 64.6 MiB 0.06 0.00 5.21955 4.32235 -136.289 -4.32235 4.32235 0.26 0.000325361 0.00029643 0.025429 0.0232205 -1 -1 -1 -1 38 2361 27 6.95648e+06 361892 678818. 2348.85 1.59 0.152009 0.133043 26626 170182 -1 2059 21 1422 2085 156669 34906 4.01806 4.01806 -140.938 -4.01806 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0168919 0.0151418 75 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_062.v common 2.95 vpr 64.64 MiB -1 -1 0.10 17680 1 0.02 -1 -1 30328 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 231 199 1 136 80 17 17 289 -1 unnamed_device 25.6 MiB 0.15 1662 643 9368 2123 6903 342 64.6 MiB 0.05 0.00 3.47745 2.966 -95.4204 -2.966 2.966 0.26 0.000417153 0.00039395 0.0187903 0.0172787 -1 -1 -1 -1 36 2034 42 6.95648e+06 231611 648988. 2245.63 1.48 0.11454 0.0994636 26050 158493 -1 1518 21 1006 1688 188499 70294 3.07297 3.07297 -103.979 -3.07297 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0133088 0.0118814 54 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_063.v common 3.62 vpr 64.90 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29928 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66456 32 32 349 273 1 184 95 17 17 289 -1 unnamed_device 25.2 MiB 0.19 2110 1084 13919 4620 7096 2203 64.9 MiB 0.07 0.00 5.666 4.87452 -132.402 -4.87452 4.87452 0.27 0.000367143 0.000334943 0.0266391 0.0244722 -1 -1 -1 -1 36 3030 29 6.95648e+06 448746 648988. 2245.63 2.00 0.123915 0.110447 26050 158493 -1 2425 21 1662 3047 282448 59742 4.65731 4.65731 -144.362 -4.65731 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0173935 0.0156353 85 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_064.v common 2.65 vpr 64.11 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29776 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65652 32 32 247 207 1 142 80 17 17 289 -1 unnamed_device 25.2 MiB 0.16 1515 868 8852 2747 5050 1055 64.1 MiB 0.04 0.00 3.51345 2.9793 -108.005 -2.9793 2.9793 0.24 0.000259585 0.000237221 0.0150162 0.0137528 -1 -1 -1 -1 34 1886 24 6.95648e+06 231611 618332. 2139.56 1.18 0.0966165 0.0838043 25762 151098 -1 1797 19 1169 1788 142635 30918 3.15892 3.15892 -117.991 -3.15892 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0128545 0.0115147 58 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_065.v common 3.50 vpr 64.79 MiB -1 -1 0.16 18060 1 0.02 -1 -1 29840 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66340 30 32 278 235 1 141 87 17 17 289 -1 unnamed_device 25.6 MiB 0.33 1720 753 11223 4264 5738 1221 64.8 MiB 0.05 0.00 3.72028 3.23198 -104.978 -3.23198 3.23198 0.35 0.000279277 0.000254685 0.0198131 0.0182093 -1 -1 -1 -1 38 1855 21 6.95648e+06 361892 678818. 2348.85 1.56 0.133737 0.11684 26626 170182 -1 1614 22 1198 1946 139206 32254 3.38942 3.38942 -117.246 -3.38942 0 0 902133. 3121.57 0.05 0.06 0.14 -1 -1 0.05 0.0223008 0.0199494 64 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 3.75 vpr 65.32 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29760 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66884 29 32 355 287 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 0.71 2234 978 11948 4957 6509 482 65.3 MiB 0.06 0.00 4.18549 3.52127 -111.57 -3.52127 3.52127 0.25 0.000328695 0.000300758 0.0250101 0.0229279 -1 -1 -1 -1 44 2569 26 6.95648e+06 275038 787024. 2723.27 1.60 0.138089 0.120443 27778 195446 -1 2149 23 1910 2895 251904 52894 3.24537 3.24537 -116.207 -3.24537 0 0 997811. 3452.63 0.04 0.08 0.11 -1 -1 0.04 0.0236407 0.0211535 81 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_067.v common 2.87 vpr 65.26 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29760 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66824 32 32 358 289 1 171 83 17 17 289 -1 unnamed_device 26.0 MiB 0.49 2085 843 13943 6117 7487 339 65.3 MiB 0.06 0.00 5.02682 4.14368 -134.376 -4.14368 4.14368 0.24 0.000339146 0.000310561 0.0280627 0.025702 -1 -1 -1 -1 36 2481 34 6.95648e+06 275038 648988. 2245.63 1.03 0.111834 0.0985597 26050 158493 -1 1947 23 1701 2459 192548 45377 4.30012 4.30012 -147.879 -4.30012 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0185936 0.0166696 74 54 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_068.v common 8.00 vpr 65.21 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29752 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66780 32 32 353 285 1 175 84 17 17 289 -1 unnamed_device 25.9 MiB 0.37 1817 988 13443 4741 6786 1916 65.2 MiB 0.06 0.00 4.64078 4.17648 -135.842 -4.17648 4.17648 0.24 0.000324448 0.000296469 0.0260462 0.0238591 -1 -1 -1 -1 36 3048 49 6.95648e+06 289514 648988. 2245.63 6.23 0.203406 0.178319 26050 158493 -1 2385 23 1677 2692 269744 58364 4.16382 4.16382 -145.367 -4.16382 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0195483 0.0175155 77 51 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_069.v common 6.19 vpr 65.02 MiB -1 -1 0.11 17916 1 0.03 -1 -1 29808 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 276 237 1 153 76 17 17 289 -1 unnamed_device 25.6 MiB 1.10 1886 837 9356 2240 6749 367 65.0 MiB 0.05 0.00 4.63212 3.81128 -119.489 -3.81128 3.81128 0.25 0.000277956 0.000254334 0.0212686 0.0195754 -1 -1 -1 -1 38 2203 37 6.95648e+06 173708 678818. 2348.85 3.64 0.151591 0.13123 26626 170182 -1 1790 20 1149 1580 134760 29661 3.38327 3.38327 -119.839 -3.38327 0 0 902133. 3121.57 0.05 0.08 0.10 -1 -1 0.05 0.0324819 0.0289059 59 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_070.v common 3.92 vpr 64.91 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29796 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 31 32 319 272 1 165 77 17 17 289 -1 unnamed_device 25.4 MiB 1.03 1833 985 10672 3667 5493 1512 64.9 MiB 0.05 0.00 4.19022 3.70692 -123.76 -3.70692 3.70692 0.24 0.000301967 0.00027545 0.0222779 0.020474 -1 -1 -1 -1 42 2256 26 6.95648e+06 202660 744469. 2576.02 1.53 0.125605 0.109064 27202 183097 -1 2010 22 1417 2054 188245 38923 3.30947 3.30947 -128.605 -3.30947 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0163974 0.0146881 65 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_071.v common 3.47 vpr 65.02 MiB -1 -1 0.14 17672 1 0.03 -1 -1 30516 -1 -1 29 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66576 30 32 329 273 1 160 91 17 17 289 -1 unnamed_device 25.2 MiB 0.19 1945 745 13351 4198 6604 2549 65.0 MiB 0.08 0.00 3.7091 3.01356 -93.2618 -3.01356 3.01356 0.25 0.000760732 0.000708834 0.035933 0.033495 -1 -1 -1 -1 38 2032 20 6.95648e+06 419795 678818. 2348.85 1.76 0.146264 0.12921 26626 170182 -1 1601 22 1121 1935 125895 29552 3.02112 3.02112 -95.7193 -3.02112 0 0 902133. 3121.57 0.03 0.04 0.18 -1 -1 0.03 0.0161828 0.0144409 75 57 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_072.v common 5.36 vpr 64.51 MiB -1 -1 0.16 17676 1 0.03 -1 -1 30208 -1 -1 30 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 28 32 277 229 1 150 90 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2011 872 12552 3452 7683 1417 64.5 MiB 0.06 0.00 4.66475 3.68024 -105.78 -3.68024 3.68024 0.24 0.000503075 0.000476972 0.0239511 0.0222033 -1 -1 -1 -1 32 2459 50 6.95648e+06 434271 586450. 2029.24 3.79 0.154412 0.135403 25474 144626 -1 2023 22 1254 2170 186743 41740 3.87011 3.87011 -115.393 -3.87011 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0154132 0.0137491 69 27 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_073.v common 2.40 vpr 65.05 MiB -1 -1 0.18 18060 1 0.04 -1 -1 30168 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 30 32 317 269 1 146 75 17 17 289 -1 unnamed_device 25.2 MiB 0.43 1690 920 7501 2498 3863 1140 65.1 MiB 0.04 0.00 3.88478 3.28908 -114.727 -3.28908 3.28908 0.24 0.000297594 0.000272455 0.0159031 0.0146019 -1 -1 -1 -1 32 2138 42 6.95648e+06 188184 586450. 2029.24 0.51 0.0667491 0.0588076 25474 144626 -1 1947 21 1371 2041 175235 41141 3.06372 3.06372 -123.129 -3.06372 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0152027 0.0135917 60 63 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_074.v common 10.45 vpr 64.18 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30184 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 32 32 335 282 1 178 78 17 17 289 -1 unnamed_device 25.2 MiB 0.98 1907 1068 11864 3789 6604 1471 64.2 MiB 0.06 0.00 3.98976 3.26039 -121.807 -3.26039 3.26039 0.25 0.000332258 0.000298989 0.0244042 0.0223413 -1 -1 -1 -1 40 2633 27 6.95648e+06 202660 706193. 2443.58 8.03 0.197614 0.173512 26914 176310 -1 2317 24 1532 2182 220982 44609 3.39857 3.39857 -132.889 -3.39857 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0197269 0.0177008 69 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_075.v common 6.33 vpr 65.14 MiB -1 -1 0.19 17676 1 0.03 -1 -1 29524 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 293 230 1 168 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1954 1022 8863 2079 6129 655 65.1 MiB 0.04 0.00 4.72172 4.01902 -124.512 -4.01902 4.01902 0.24 0.0003344 0.000307698 0.0152924 0.0139831 -1 -1 -1 -1 40 2382 38 6.95648e+06 405319 706193. 2443.58 4.77 0.171303 0.149447 26914 176310 -1 2176 25 1492 2546 211497 46101 3.93111 3.93111 -128.021 -3.93111 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0182985 0.016269 77 4 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_076.v common 8.52 vpr 65.37 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29952 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66940 32 32 350 275 1 201 81 17 17 289 -1 unnamed_device 25.8 MiB 0.86 2386 1198 10231 3183 5327 1721 65.4 MiB 0.06 0.00 5.01638 4.27059 -145.615 -4.27059 4.27059 0.25 0.000347323 0.000318969 0.0270089 0.0251911 -1 -1 -1 -1 38 3178 30 6.95648e+06 246087 678818. 2348.85 6.30 0.188955 0.166547 26626 170182 -1 2598 21 1833 2710 208293 44175 4.12906 4.12906 -152.157 -4.12906 0 0 902133. 3121.57 0.04 0.05 0.09 -1 -1 0.04 0.0179993 0.0161953 83 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_077.v common 4.33 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29768 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 385 308 1 176 91 17 17 289 -1 unnamed_device 25.6 MiB 0.76 2067 860 9067 2994 4608 1465 64.7 MiB 0.05 0.00 5.02252 4.13222 -135.728 -4.13222 4.13222 0.25 0.000357951 0.000322619 0.0220214 0.0203008 -1 -1 -1 -1 52 2139 29 6.95648e+06 390843 926341. 3205.33 2.07 0.163955 0.142438 29218 227130 -1 1758 23 1486 2566 195701 45640 3.61706 3.61706 -133.911 -3.61706 0 0 1.14541e+06 3963.36 0.04 0.05 0.14 -1 -1 0.04 0.0192195 0.0172358 81 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_078.v common 3.00 vpr 65.49 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29848 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67064 32 32 387 309 1 182 98 17 17 289 -1 unnamed_device 26.0 MiB 0.37 2383 1001 14723 3257 11066 400 65.5 MiB 0.07 0.00 4.65582 4.051 -135.3 -4.051 4.051 0.26 0.000364327 0.000329589 0.0259811 0.0236825 -1 -1 -1 -1 46 2674 49 6.95648e+06 492173 828058. 2865.25 1.18 0.131299 0.115986 28066 200906 -1 2258 24 1693 2916 231831 48343 3.79886 3.79886 -135.102 -3.79886 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0221089 0.0198942 88 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_079.v common 2.49 vpr 64.73 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29664 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 30 32 272 232 1 142 75 17 17 289 -1 unnamed_device 25.2 MiB 0.34 1640 871 10503 3905 4899 1699 64.7 MiB 0.05 0.00 4.04631 3.58091 -110.597 -3.58091 3.58091 0.25 0.000271226 0.000247969 0.0204865 0.0188574 -1 -1 -1 -1 40 1905 22 6.95648e+06 188184 706193. 2443.58 0.82 0.0881242 0.0774387 26914 176310 -1 1801 18 1073 1821 136370 29998 2.95232 2.95232 -113.094 -2.95232 0 0 926341. 3205.33 0.03 0.04 0.09 -1 -1 0.03 0.0127374 0.0114172 58 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_080.v common 3.12 vpr 64.73 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29792 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 30 32 375 299 1 179 78 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2263 979 14022 6059 7515 448 64.7 MiB 0.07 0.00 4.96142 3.95902 -134.036 -3.95902 3.95902 0.24 0.000345961 0.000317658 0.0343629 0.0315794 -1 -1 -1 -1 40 2208 27 6.95648e+06 231611 706193. 2443.58 1.48 0.146559 0.128454 26914 176310 -1 1994 23 2050 2994 247756 52238 3.84676 3.84676 -136.997 -3.84676 0 0 926341. 3205.33 0.03 0.08 0.11 -1 -1 0.03 0.0293045 0.0261939 78 63 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_081.v common 4.32 vpr 65.41 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29852 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 340 270 1 193 82 17 17 289 -1 unnamed_device 25.3 MiB 0.83 2252 1135 5422 1105 3974 343 65.4 MiB 0.03 0.00 5.21041 4.51361 -142.408 -4.51361 4.51361 0.25 0.000326717 0.000299349 0.0118588 0.010928 -1 -1 -1 -1 48 2777 21 6.95648e+06 260562 865456. 2994.66 2.04 0.1506 0.131797 28354 207349 -1 2286 24 1653 2579 248336 48799 4.23062 4.23062 -147.459 -4.23062 0 0 1.05005e+06 3633.38 0.04 0.06 0.11 -1 -1 0.04 0.0184952 0.0165578 80 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_082.v common 7.39 vpr 65.29 MiB -1 -1 0.12 18444 1 0.04 -1 -1 29792 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66852 31 32 340 275 1 188 79 17 17 289 -1 unnamed_device 25.4 MiB 0.83 2310 992 9543 2486 6548 509 65.3 MiB 0.06 0.00 6.40554 5.4777 -155.957 -5.4777 5.4777 0.25 0.000327639 0.000300051 0.020285 0.0186377 -1 -1 -1 -1 38 2728 50 6.95648e+06 231611 678818. 2348.85 5.14 0.179636 0.157579 26626 170182 -1 2193 21 1591 2407 184090 43251 4.33266 4.33266 -145.385 -4.33266 0 0 902133. 3121.57 0.04 0.05 0.09 -1 -1 0.04 0.0169823 0.0152252 80 47 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_083.v common 3.68 vpr 64.68 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30372 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 30 32 377 310 1 169 87 17 17 289 -1 unnamed_device 25.6 MiB 1.28 1889 756 14871 5671 7163 2037 64.7 MiB 0.06 0.00 4.34198 4.07348 -128.883 -4.07348 4.07348 0.24 0.000338279 0.000309011 0.0286867 0.0262429 -1 -1 -1 -1 40 2318 30 6.95648e+06 361892 706193. 2443.58 1.01 0.100877 0.0892676 26914 176310 -1 1820 22 1439 2322 207641 51502 3.33982 3.33982 -122.459 -3.33982 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.018083 0.0162233 76 83 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_084.v common 3.78 vpr 65.30 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30156 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66864 32 32 365 294 1 177 79 17 17 289 -1 unnamed_device 26.0 MiB 0.31 1978 1030 12247 4070 6334 1843 65.3 MiB 0.06 0.00 4.70608 4.25858 -140.542 -4.25858 4.25858 0.25 0.000351506 0.000322633 0.0273447 0.0251296 -1 -1 -1 -1 46 2664 29 6.95648e+06 217135 828058. 2865.25 2.04 0.190442 0.16687 28066 200906 -1 2305 22 1743 3062 250592 49506 3.92702 3.92702 -139.174 -3.92702 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0181199 0.016217 74 57 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_085.v common 2.99 vpr 64.88 MiB -1 -1 0.13 18444 1 0.03 -1 -1 30004 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 29 32 378 310 1 170 86 17 17 289 -1 unnamed_device 25.5 MiB 0.38 1806 1002 10670 2920 6625 1125 64.9 MiB 0.05 0.00 3.96908 3.44163 -116.475 -3.44163 3.44163 0.25 0.000347162 0.000317562 0.0214865 0.0197233 -1 -1 -1 -1 36 2578 39 6.95648e+06 361892 648988. 2245.63 1.22 0.118359 0.104523 26050 158493 -1 2261 28 1817 2808 264581 56589 3.83567 3.83567 -128.927 -3.83567 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0211173 0.0187645 78 85 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_086.v common 2.57 vpr 64.28 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30124 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 243 205 1 140 76 17 17 289 -1 unnamed_device 25.2 MiB 0.62 1666 819 5676 1328 4145 203 64.3 MiB 0.04 0.00 3.96613 3.48283 -113.364 -3.48283 3.48283 0.25 0.000466901 0.000444113 0.0149633 0.0138973 -1 -1 -1 -1 34 1869 21 6.95648e+06 173708 618332. 2139.56 0.57 0.0703562 0.0621034 25762 151098 -1 1695 23 1032 1521 123987 26549 3.10097 3.10097 -115.483 -3.10097 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0146156 0.0130885 55 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_087.v common 5.53 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66416 32 32 373 302 1 170 91 17 17 289 -1 unnamed_device 25.0 MiB 2.25 2487 909 14983 5086 7268 2629 64.9 MiB 0.07 0.00 5.45342 4.07722 -130.088 -4.07722 4.07722 0.25 0.000344536 0.000314315 0.0289953 0.0265024 -1 -1 -1 -1 48 2299 22 6.95648e+06 390843 865456. 2994.66 1.80 0.164245 0.143738 28354 207349 -1 1991 19 1367 2167 187733 39323 4.06326 4.06326 -132.586 -4.06326 0 0 1.05005e+06 3633.38 0.04 0.05 0.11 -1 -1 0.04 0.0163677 0.0147465 77 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_088.v common 2.57 vpr 64.77 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 32 32 397 314 1 188 78 17 17 289 -1 unnamed_device 25.5 MiB 0.26 2454 1052 12860 4424 7590 846 64.8 MiB 0.07 0.00 4.96142 3.97692 -145.635 -3.97692 3.97692 0.24 0.000362887 0.000332149 0.0302037 0.0277082 -1 -1 -1 -1 40 2507 27 6.95648e+06 202660 706193. 2443.58 0.88 0.104123 0.0923463 26914 176310 -1 2263 21 2040 3064 258642 54364 3.94116 3.94116 -154.866 -3.94116 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0185875 0.0166838 80 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_089.v common 3.21 vpr 63.55 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30216 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65076 32 32 269 231 1 163 77 17 17 289 -1 unnamed_device 25.0 MiB 0.84 1853 775 10346 4263 5879 204 63.6 MiB 0.05 0.00 3.82363 3.41043 -106.561 -3.41043 3.41043 0.25 0.000274716 0.000250626 0.0190657 0.017461 -1 -1 -1 -1 40 2161 23 6.95648e+06 188184 706193. 2443.58 0.92 0.0905387 0.0795776 26914 176310 -1 1801 21 1327 1750 165546 38654 3.26227 3.26227 -113.791 -3.26227 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0146235 0.0130764 64 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_090.v common 2.68 vpr 64.38 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29944 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 25.2 MiB 0.15 1533 780 8529 3413 4923 193 64.4 MiB 0.04 0.00 3.74228 3.28943 -106.539 -3.28943 3.28943 0.26 0.000258839 0.000236409 0.0154785 0.0142302 -1 -1 -1 -1 34 1921 28 6.95648e+06 231611 618332. 2139.56 1.20 0.108495 0.0938914 25762 151098 -1 1669 23 1353 2052 154963 33971 3.10392 3.10392 -112.189 -3.10392 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143899 0.0127996 59 4 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_091.v common 4.12 vpr 65.40 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 32 32 348 274 1 203 82 17 17 289 -1 unnamed_device 25.6 MiB 0.76 2467 1004 13432 4674 7054 1704 65.4 MiB 0.07 0.00 5.20718 4.12648 -139.222 -4.12648 4.12648 0.25 0.000332018 0.000303875 0.0273176 0.0250357 -1 -1 -1 -1 44 2510 23 6.95648e+06 260562 787024. 2723.27 1.70 0.141425 0.12424 27778 195446 -1 2086 22 1919 2600 212528 45424 4.00852 4.00852 -143.085 -4.00852 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0181433 0.0162844 82 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_092.v common 3.92 vpr 65.39 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29836 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 32 32 356 289 1 193 83 17 17 289 -1 unnamed_device 25.3 MiB 0.70 2587 1001 13943 3775 9769 399 65.4 MiB 0.07 0.00 5.38354 4.77262 -147.362 -4.77262 4.77262 0.25 0.00034617 0.000316777 0.0291289 0.0266296 -1 -1 -1 -1 46 2365 25 6.95648e+06 275038 828058. 2865.25 1.74 0.164581 0.144566 28066 200906 -1 2008 23 1426 2177 149929 33848 4.62936 4.62936 -148.354 -4.62936 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0184672 0.0165355 82 56 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_093.v common 2.94 vpr 65.11 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 25.6 MiB 0.14 2197 1019 15213 5463 7727 2023 65.1 MiB 0.09 0.00 5.73982 4.68117 -141.736 -4.68117 4.68117 0.34 0.000368249 0.000317849 0.0353615 0.0325265 -1 -1 -1 -1 44 2766 38 6.95648e+06 419795 787024. 2723.27 1.13 0.119924 0.107142 27778 195446 -1 2279 21 1815 3185 288567 62270 4.55991 4.55991 -145.102 -4.55991 0 0 997811. 3452.63 0.04 0.07 0.11 -1 -1 0.04 0.0206305 0.0183858 90 3 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_094.v common 2.73 vpr 64.57 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29912 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 30 32 316 264 1 156 89 17 17 289 -1 unnamed_device 25.6 MiB 0.22 1994 761 12563 2870 9117 576 64.6 MiB 0.06 0.00 3.94408 3.31423 -98.4865 -3.31423 3.31423 0.39 0.000306285 0.000278227 0.0224075 0.0205549 -1 -1 -1 -1 36 2264 42 6.95648e+06 390843 648988. 2245.63 0.99 0.131193 0.116194 26050 158493 -1 1901 21 1431 2403 188292 43569 3.19992 3.19992 -108.587 -3.19992 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0162737 0.0145473 71 52 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_095.v common 2.55 vpr 64.66 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30556 -1 -1 19 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 27 32 255 219 1 128 78 17 17 289 -1 unnamed_device 25.4 MiB 0.16 1405 640 9872 2965 6271 636 64.7 MiB 0.04 0.00 3.54465 2.9243 -92.5518 -2.9243 2.9243 0.25 0.000264446 0.000241443 0.0170022 0.0155638 -1 -1 -1 -1 32 1668 25 6.95648e+06 275038 586450. 2029.24 1.07 0.0945713 0.0820646 25474 144626 -1 1378 22 1095 1565 118686 26784 2.92552 2.92552 -98.9985 -2.92552 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0136876 0.0121712 59 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_096.v common 3.68 vpr 65.58 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29744 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67152 32 32 421 327 1 224 82 17 17 289 -1 unnamed_device 26.0 MiB 0.61 2597 1273 12720 3612 7834 1274 65.6 MiB 0.08 0.00 4.73785 3.78655 -136.554 -3.78655 3.78655 0.24 0.000384672 0.000352581 0.0300313 0.0275734 -1 -1 -1 -1 42 3519 29 6.95648e+06 260562 744469. 2576.02 1.63 0.132697 0.117622 27202 183097 -1 3005 22 2080 3405 314185 64432 3.95532 3.95532 -149.527 -3.95532 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.021025 0.0188977 93 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_097.v common 5.44 vpr 64.93 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29760 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 31 32 365 296 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 2.64 2283 1122 12292 4005 7130 1157 64.9 MiB 0.07 0.00 5.96575 5.12445 -155.529 -5.12445 5.12445 0.25 0.000337024 0.000308455 0.0295189 0.0270785 -1 -1 -1 -1 38 2762 45 6.95648e+06 246087 678818. 2348.85 1.37 0.131579 0.116282 26626 170182 -1 2224 21 1531 2248 178571 38503 4.67096 4.67096 -158.865 -4.67096 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0195671 0.0176194 81 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_098.v common 5.12 vpr 64.20 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30128 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65736 32 32 331 280 1 171 77 17 17 289 -1 unnamed_device 25.2 MiB 2.35 2263 831 10346 4372 5809 165 64.2 MiB 0.05 0.00 4.65874 3.66435 -131.027 -3.66435 3.66435 0.24 0.000310938 0.000283553 0.0216721 0.0198615 -1 -1 -1 -1 40 2127 20 6.95648e+06 188184 706193. 2443.58 1.44 0.137458 0.120294 26914 176310 -1 1839 21 1307 1913 170049 36740 3.63446 3.63446 -138.29 -3.63446 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0166748 0.0149375 69 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_099.v common 3.11 vpr 65.18 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30312 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66744 32 32 326 263 1 169 91 17 17 289 -1 unnamed_device 25.6 MiB 0.10 1919 1016 13147 4843 6404 1900 65.2 MiB 0.06 0.00 4.64482 4.16998 -130.262 -4.16998 4.16998 0.24 0.000346533 0.000316496 0.0224885 0.020484 -1 -1 -1 -1 40 2384 25 6.95648e+06 390843 706193. 2443.58 1.56 0.137469 0.119796 26914 176310 -1 2171 22 1287 2054 170952 36008 3.73576 3.73576 -130.81 -3.73576 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0168862 0.0151431 78 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_100.v common 5.22 vpr 64.75 MiB -1 -1 0.22 18060 1 0.03 -1 -1 29868 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66308 31 32 373 294 1 188 89 17 17 289 -1 unnamed_device 25.2 MiB 0.30 1978 1064 14147 4993 7358 1796 64.8 MiB 0.07 0.00 4.83868 4.13778 -125.088 -4.13778 4.13778 0.24 0.000347007 0.000317888 0.0269397 0.0247308 -1 -1 -1 -1 32 2893 42 6.95648e+06 376368 586450. 2029.24 3.43 0.174284 0.153096 25474 144626 -1 2450 24 1685 2597 193336 42653 3.90842 3.90842 -134.368 -3.90842 0 0 744469. 2576.02 0.03 0.06 0.09 -1 -1 0.03 0.0209366 0.0188136 86 50 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_101.v common 2.29 vpr 64.83 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29816 -1 -1 26 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66384 30 32 325 268 1 165 88 17 17 289 -1 unnamed_device 25.2 MiB 0.30 2005 1028 11788 3531 6603 1654 64.8 MiB 0.05 0.00 3.5368 3.13114 -104.094 -3.13114 3.13114 0.25 0.00031141 0.000284959 0.0207535 0.0190534 -1 -1 -1 -1 38 2346 24 6.95648e+06 376368 678818. 2348.85 0.66 0.0754822 0.0665845 26626 170182 -1 2032 19 1160 1908 135098 29773 3.16517 3.16517 -107.895 -3.16517 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0149197 0.013408 73 51 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_102.v common 7.44 vpr 64.93 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29764 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 350 275 1 208 82 17 17 289 -1 unnamed_device 25.6 MiB 0.70 2473 1225 12364 3185 8008 1171 64.9 MiB 0.08 0.00 4.77678 4.16128 -145.153 -4.16128 4.16128 0.26 0.000404071 0.000374789 0.0313753 0.0288088 -1 -1 -1 -1 44 3002 25 6.95648e+06 260562 787024. 2723.27 5.26 0.181151 0.159774 27778 195446 -1 2501 21 1929 2888 254181 52739 4.05232 4.05232 -152.306 -4.05232 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0178059 0.0160364 86 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 3.78 vpr 65.50 MiB -1 -1 0.14 18444 1 0.03 -1 -1 29880 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67076 32 32 386 307 1 187 93 17 17 289 -1 unnamed_device 25.7 MiB 0.43 2024 1035 11643 3723 6128 1792 65.5 MiB 0.06 0.00 3.74723 3.51453 -126.992 -3.51453 3.51453 0.26 0.000359398 0.000328095 0.0219604 0.0201218 -1 -1 -1 -1 38 2497 41 6.95648e+06 419795 678818. 2348.85 1.61 0.171102 0.149711 26626 170182 -1 2126 21 1643 2340 175495 37297 3.06657 3.06657 -126.206 -3.06657 0 0 902133. 3121.57 0.04 0.07 0.13 -1 -1 0.04 0.0262995 0.0235558 89 62 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_104.v common 3.91 vpr 64.29 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29856 -1 -1 13 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 29 32 269 229 1 131 74 17 17 289 -1 unnamed_device 25.2 MiB 1.98 1409 525 11234 4704 6022 508 64.3 MiB 0.06 0.00 4.32326 3.73256 -100.612 -3.73256 3.73256 0.25 0.000454335 0.00043038 0.027869 0.0258546 -1 -1 -1 -1 36 1494 27 6.95648e+06 188184 648988. 2245.63 0.58 0.0907463 0.0799895 26050 158493 -1 1158 19 812 1114 77704 18636 2.78907 2.78907 -96.8024 -2.78907 0 0 828058. 2865.25 0.03 0.03 0.08 -1 -1 0.03 0.0132226 0.0118612 54 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_105.v common 3.50 vpr 65.11 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29916 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 32 32 310 266 1 169 78 17 17 289 -1 unnamed_device 25.2 MiB 0.56 1977 706 10038 3625 5105 1308 65.1 MiB 0.05 0.00 3.7422 3.1157 -108.673 -3.1157 3.1157 0.33 0.000294774 0.000269053 0.0197681 0.0181074 -1 -1 -1 -1 40 1746 31 6.95648e+06 202660 706193. 2443.58 1.49 0.12737 0.110608 26914 176310 -1 1498 22 1422 1863 141586 36360 3.37177 3.37177 -118.821 -3.37177 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.015732 0.0140493 66 58 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_106.v common 3.58 vpr 65.12 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29912 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 31 32 326 261 1 170 94 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2332 811 13087 3914 6088 3085 65.1 MiB 0.05 0.00 4.97742 3.97428 -119.674 -3.97428 3.97428 0.24 0.000315998 0.000287636 0.0230737 0.0211763 -1 -1 -1 -1 40 2279 46 6.95648e+06 448746 706193. 2443.58 2.01 0.173492 0.152007 26914 176310 -1 1762 28 1677 2723 255514 76442 3.96126 3.96126 -125.346 -3.96126 0 0 926341. 3205.33 0.04 0.08 0.10 -1 -1 0.04 0.0227733 0.0202212 80 33 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_107.v common 2.68 vpr 65.11 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29856 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 29 32 262 224 1 162 78 17 17 289 -1 unnamed_device 25.2 MiB 0.53 1704 832 10204 3476 5170 1558 65.1 MiB 0.04 0.00 4.25002 3.76672 -110.108 -3.76672 3.76672 0.24 0.000262567 0.000240474 0.0178239 0.0163649 -1 -1 -1 -1 34 2241 29 6.95648e+06 246087 618332. 2139.56 0.83 0.0787243 0.0694314 25762 151098 -1 1822 23 1401 1800 155915 34217 3.33297 3.33297 -112.31 -3.33297 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.01507 0.0132915 66 31 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_108.v common 4.86 vpr 64.69 MiB -1 -1 0.14 17676 1 0.02 -1 -1 30212 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66244 32 32 278 238 1 144 75 17 17 289 -1 unnamed_device 25.6 MiB 0.71 1586 629 9871 3760 4775 1336 64.7 MiB 0.05 0.00 4.25682 3.85356 -110.478 -3.85356 3.85356 0.25 0.000276118 0.000252385 0.0198227 0.0181798 -1 -1 -1 -1 36 2060 29 6.95648e+06 159232 648988. 2245.63 2.80 0.142247 0.123915 26050 158493 -1 1562 24 1364 2227 179795 40766 3.45952 3.45952 -119.804 -3.45952 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.015841 0.0140933 56 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_109.v common 3.44 vpr 64.82 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29784 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66376 31 32 373 300 1 174 94 17 17 289 -1 unnamed_device 25.5 MiB 0.39 1975 777 12235 3547 6422 2266 64.8 MiB 0.06 0.00 3.92078 3.36072 -113.014 -3.36072 3.36072 0.24 0.000343711 0.000312696 0.0218847 0.0199664 -1 -1 -1 -1 36 2383 29 6.95648e+06 448746 648988. 2245.63 1.69 0.174196 0.152739 26050 158493 -1 1890 23 1823 2630 192141 46427 3.32232 3.32232 -125.254 -3.32232 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0193631 0.0172866 83 64 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_110.v common 4.31 vpr 64.29 MiB -1 -1 0.12 17920 1 0.02 -1 -1 30204 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 31 32 265 230 1 159 77 17 17 289 -1 unnamed_device 24.6 MiB 1.08 1790 729 11813 4928 6553 332 64.3 MiB 0.05 0.00 3.77783 3.40453 -105.323 -3.40453 3.40453 0.25 0.000308872 0.000277629 0.0214596 0.0196707 -1 -1 -1 -1 40 2146 36 6.95648e+06 202660 706193. 2443.58 1.84 0.134082 0.117173 26914 176310 -1 1739 22 1464 2120 189319 43391 3.29247 3.29247 -120.401 -3.29247 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0143602 0.0128295 61 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_111.v common 3.26 vpr 64.05 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29460 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 349 286 1 165 90 17 17 289 -1 unnamed_device 25.4 MiB 0.60 2297 786 16371 5346 8562 2463 64.1 MiB 0.07 0.00 3.67454 3.219 -105.866 -3.219 3.219 0.25 0.000337391 0.000309016 0.0296005 0.0271143 -1 -1 -1 -1 36 2478 41 6.95648e+06 376368 648988. 2245.63 1.24 0.10822 0.0954031 26050 158493 -1 1746 19 1244 2022 141843 33916 3.28147 3.28147 -107.564 -3.28147 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0160826 0.0144954 73 57 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_112.v common 3.73 vpr 64.76 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29768 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 396 325 1 176 83 17 17 289 -1 unnamed_device 25.6 MiB 0.93 2367 760 13403 5641 7157 605 64.8 MiB 0.07 0.00 4.16215 3.42825 -117.829 -3.42825 3.42825 0.24 0.000472934 0.000415205 0.0310469 0.0284745 -1 -1 -1 -1 40 2441 42 6.95648e+06 289514 706193. 2443.58 1.28 0.128029 0.113433 26914 176310 -1 1940 25 1789 2570 188127 47601 3.62427 3.62427 -132.869 -3.62427 0 0 926341. 3205.33 0.03 0.06 0.12 -1 -1 0.03 0.0248133 0.0219353 79 91 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_113.v common 2.56 vpr 64.76 MiB -1 -1 0.12 18056 1 0.04 -1 -1 30116 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 303 262 1 145 75 17 17 289 -1 unnamed_device 25.6 MiB 0.21 1778 712 10977 4578 6228 171 64.8 MiB 0.05 0.00 3.29253 2.84005 -99.7836 -2.84005 2.84005 0.25 0.00042795 0.000388641 0.0239453 0.021948 -1 -1 -1 -1 36 2050 34 6.95648e+06 159232 648988. 2245.63 0.79 0.0853346 0.0750854 26050 158493 -1 1762 20 1194 1822 154899 35238 3.11192 3.11192 -113.612 -3.11192 0 0 828058. 2865.25 0.05 0.07 0.15 -1 -1 0.05 0.0238669 0.0213025 58 57 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_114.v common 3.40 vpr 64.19 MiB -1 -1 0.13 18296 1 0.03 -1 -1 29756 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 32 32 290 244 1 172 78 17 17 289 -1 unnamed_device 25.2 MiB 0.73 1995 861 8378 1972 6153 253 64.2 MiB 0.04 0.00 3.97583 3.49463 -115.332 -3.49463 3.49463 0.26 0.000286549 0.000262684 0.0160968 0.0147723 -1 -1 -1 -1 40 2267 25 6.95648e+06 202660 706193. 2443.58 1.28 0.0945591 0.0830124 26914 176310 -1 1967 21 1553 2292 189903 41785 3.35347 3.35347 -120.801 -3.35347 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0147377 0.0131938 68 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_115.v common 4.63 vpr 64.66 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29772 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 318 257 1 190 81 17 17 289 -1 unnamed_device 25.6 MiB 0.63 1985 868 6206 1328 4710 168 64.7 MiB 0.03 0.00 4.72618 4.25388 -127.376 -4.25388 4.25388 0.24 0.000319888 0.000293074 0.0132111 0.0121845 -1 -1 -1 -1 36 2808 32 6.95648e+06 246087 648988. 2245.63 2.57 0.158635 0.139331 26050 158493 -1 2074 22 1723 2285 180456 42709 4.25992 4.25992 -139.303 -4.25992 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0165456 0.0148185 76 30 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_116.v common 4.11 vpr 64.66 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29780 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 29 32 324 268 1 162 86 17 17 289 -1 unnamed_device 25.0 MiB 0.51 1715 960 12371 3218 7643 1510 64.7 MiB 0.06 0.00 4.12939 3.75349 -109.494 -3.75349 3.75349 0.25 0.000312325 0.000285891 0.0222995 0.0204763 -1 -1 -1 -1 36 2399 29 6.95648e+06 361892 648988. 2245.63 2.08 0.162881 0.143154 26050 158493 -1 2124 24 1309 2223 188987 40183 3.40282 3.40282 -112.56 -3.40282 0 0 828058. 2865.25 0.03 0.05 0.10 -1 -1 0.03 0.0178762 0.0159922 73 55 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_117.v common 10.74 vpr 64.86 MiB -1 -1 0.12 18296 1 0.03 -1 -1 29960 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 32 32 393 312 1 205 80 17 17 289 -1 unnamed_device 25.6 MiB 0.82 2498 877 13324 5609 7307 408 64.9 MiB 0.07 0.00 5.49221 4.58061 -145.903 -4.58061 4.58061 0.25 0.000374154 0.000342411 0.0337134 0.0310037 -1 -1 -1 -1 42 3205 39 6.95648e+06 231611 744469. 2576.02 8.24 0.240569 0.211499 27202 183097 -1 2393 26 2399 3408 288616 65006 4.30292 4.30292 -159.239 -4.30292 0 0 949917. 3286.91 0.05 0.10 0.14 -1 -1 0.05 0.0309125 0.0275603 86 65 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_118.v common 2.34 vpr 64.54 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29936 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 31 32 229 197 1 137 77 17 17 289 -1 unnamed_device 24.9 MiB 0.37 1573 789 7738 2349 3877 1512 64.5 MiB 0.03 0.00 3.62318 3.27643 -101.711 -3.27643 3.27643 0.24 0.000248976 0.000227423 0.0132757 0.0121928 -1 -1 -1 -1 34 1944 27 6.95648e+06 202660 618332. 2139.56 0.69 0.0826342 0.0725114 25762 151098 -1 1657 22 990 1577 151209 32013 3.17312 3.17312 -112.749 -3.17312 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0133466 0.0118792 54 4 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_119.v common 6.20 vpr 65.46 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29756 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67036 32 32 412 334 1 182 92 17 17 289 -1 unnamed_device 25.5 MiB 0.34 2584 779 15410 4873 7828 2709 65.5 MiB 0.07 0.00 4.99926 3.90964 -132.617 -3.90964 3.90964 0.35 0.000367291 0.000335681 0.0295207 0.0270144 -1 -1 -1 -1 54 2048 24 6.95648e+06 405319 949917. 3286.91 4.30 0.220353 0.193683 29506 232905 -1 1646 23 1577 2111 155055 38389 4.14962 4.14962 -142.145 -4.14962 0 0 1.17392e+06 4061.99 0.04 0.06 0.14 -1 -1 0.04 0.0246995 0.0221709 84 90 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_120.v common 4.94 vpr 64.66 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30212 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 32 32 376 318 1 154 75 17 17 289 -1 unnamed_device 25.6 MiB 1.68 1894 675 12083 5157 6591 335 64.7 MiB 0.06 0.00 3.54619 2.94085 -113.533 -2.94085 2.94085 0.25 0.000336191 0.000306852 0.0277439 0.0254059 -1 -1 -1 -1 48 1588 22 6.95648e+06 159232 865456. 2994.66 1.84 0.165957 0.145157 28354 207349 -1 1301 20 1327 1806 124593 28920 3.01532 3.01532 -115.899 -3.01532 0 0 1.05005e+06 3633.38 0.04 0.04 0.11 -1 -1 0.04 0.0165622 0.0148394 62 96 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_121.v common 3.44 vpr 64.68 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30156 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 360 293 1 172 90 17 17 289 -1 unnamed_device 25.3 MiB 0.48 1853 1069 14562 4604 8437 1521 64.7 MiB 0.07 0.00 3.91173 3.53583 -120.704 -3.53583 3.53583 0.25 0.000335501 0.000306033 0.0322582 0.0297118 -1 -1 -1 -1 40 2375 24 6.95648e+06 376368 706193. 2443.58 1.49 0.158921 0.139899 26914 176310 -1 2117 23 1326 2047 179309 38171 3.29717 3.29717 -119.13 -3.29717 0 0 926341. 3205.33 0.05 0.08 0.11 -1 -1 0.05 0.0312325 0.0278867 78 60 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_122.v common 3.18 vpr 65.48 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30192 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67056 32 32 396 299 1 227 83 17 17 289 -1 unnamed_device 25.6 MiB 0.86 2452 1278 10883 3044 6597 1242 65.5 MiB 0.07 0.00 6.40588 5.67799 -169.514 -5.67799 5.67799 0.26 0.000375871 0.000344229 0.0265442 0.0244031 -1 -1 -1 -1 42 3157 23 6.95648e+06 275038 744469. 2576.02 0.83 0.0987754 0.0878873 27202 183097 -1 2714 35 2694 3788 394527 125732 4.9392 4.9392 -169.567 -4.9392 0 0 949917. 3286.91 0.03 0.11 0.10 -1 -1 0.03 0.028617 0.0255556 95 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_123.v common 4.02 vpr 64.68 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29564 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 30 32 224 207 1 132 75 17 17 289 -1 unnamed_device 25.6 MiB 0.54 1627 598 12241 5372 6458 411 64.7 MiB 0.05 0.00 2.90706 2.40586 -87.9482 -2.40586 2.40586 0.25 0.000233649 0.000212956 0.0201236 0.0184129 -1 -1 -1 -1 40 1508 30 6.95648e+06 188184 706193. 2443.58 2.06 0.157661 0.137737 26914 176310 -1 1331 20 901 1144 111930 30811 2.88623 2.88623 -98.6954 -2.88623 0 0 926341. 3205.33 0.03 0.04 0.11 -1 -1 0.03 0.0123386 0.0110566 51 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_124.v common 4.72 vpr 64.19 MiB -1 -1 0.19 17676 1 0.03 -1 -1 30184 -1 -1 12 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 30 32 286 239 1 137 74 17 17 289 -1 unnamed_device 25.1 MiB 0.91 1634 584 10304 2805 7001 498 64.2 MiB 0.04 0.00 3.45258 3.27614 -105.411 -3.27614 3.27614 0.25 0.000284959 0.000261096 0.0205025 0.0187956 -1 -1 -1 -1 34 1944 38 6.95648e+06 173708 618332. 2139.56 2.32 0.143174 0.124606 25762 151098 -1 1413 22 1179 1705 141397 34783 3.09482 3.09482 -117.715 -3.09482 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0150785 0.0134656 56 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 3.29 vpr 65.05 MiB -1 -1 0.11 18064 1 0.02 -1 -1 29768 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 296 247 1 152 83 17 17 289 -1 unnamed_device 25.2 MiB 0.11 1728 922 8723 2565 5365 793 65.1 MiB 0.04 0.00 3.55445 2.9873 -113.256 -2.9873 2.9873 0.25 0.000301223 0.00027349 0.0160763 0.0147241 -1 -1 -1 -1 40 2197 27 6.95648e+06 275038 706193. 2443.58 1.75 0.156743 0.136892 26914 176310 -1 2042 23 1349 2303 218886 48209 3.19827 3.19827 -121.7 -3.19827 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0160692 0.0143372 65 34 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_126.v common 2.84 vpr 64.26 MiB -1 -1 0.12 18060 1 0.02 -1 -1 29828 -1 -1 18 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 25 32 216 194 1 119 75 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1353 690 8449 3120 3872 1457 64.3 MiB 0.03 0.00 3.58218 3.24133 -80.823 -3.24133 3.24133 0.25 0.000224742 0.000205297 0.0131913 0.0120881 -1 -1 -1 -1 32 1648 24 6.95648e+06 260562 586450. 2029.24 1.34 0.123269 0.106366 25474 144626 -1 1400 20 849 1332 99865 22135 2.72602 2.72602 -85.395 -2.72602 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0111245 0.00989695 51 29 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_127.v common 6.84 vpr 64.71 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29796 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 376 307 1 179 78 17 17 289 -1 unnamed_device 26.0 MiB 0.46 1982 1168 8876 2502 5267 1107 64.7 MiB 0.05 0.00 4.59945 3.81054 -129.805 -3.81054 3.81054 0.25 0.000344787 0.000315324 0.0205257 0.0187772 -1 -1 -1 -1 40 2820 23 6.95648e+06 202660 706193. 2443.58 4.95 0.191278 0.167763 26914 176310 -1 2463 25 1559 2688 247418 60274 4.07062 4.07062 -139.096 -4.07062 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0204429 0.0182595 75 72 -1 -1 -1 -1 +fixed_k6_frac_2ripple_N8_22nm.xml mult_128.v common 3.87 vpr 65.58 MiB -1 -1 0.20 18440 1 0.03 -1 -1 29772 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67156 31 32 409 331 1 183 92 17 17 289 -1 unnamed_device 25.6 MiB 0.39 1880 934 14582 5336 7343 1903 65.6 MiB 0.07 0.00 3.75413 3.54189 -123.861 -3.54189 3.54189 0.25 0.000370518 0.000338041 0.0281666 0.0258067 -1 -1 -1 -1 40 2135 23 6.95648e+06 419795 706193. 2443.58 1.67 0.181804 0.159938 26914 176310 -1 1941 23 1958 2686 194478 42954 3.22012 3.22012 -126.025 -3.22012 0 0 926341. 3205.33 0.05 0.09 0.17 -1 -1 0.05 0.0361223 0.0324491 88 90 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_001.v common 3.61 vpr 65.28 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30180 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66844 32 32 354 285 1 206 82 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2477 1104 5956 1234 4454 268 65.3 MiB 0.04 0.00 5.9831 5.0213 -150.404 -5.0213 5.0213 0.25 0.000339429 0.000311214 0.0135732 0.0124946 -1 -1 -1 -1 40 2746 30 6.99608e+06 264882 706193. 2443.58 1.64 0.140449 0.122546 26914 176310 -1 2503 21 1812 2826 219665 47612 4.45375 4.45375 -154.395 -4.45375 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0178176 0.0160479 89 50 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_002.v common 7.00 vpr 64.60 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29756 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 30 32 363 293 1 224 85 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2539 1213 13663 4903 6549 2211 64.6 MiB 0.08 0.00 5.97457 4.74455 -148.167 -4.74455 4.74455 0.25 0.000819983 0.00075946 0.0339081 0.0313222 -1 -1 -1 -1 38 2904 29 6.99608e+06 338461 678818. 2348.85 5.25 0.188274 0.165386 26626 170182 -1 2475 23 2204 3166 262316 53855 4.3292 4.3292 -149.244 -4.3292 0 0 902133. 3121.57 0.03 0.07 0.10 -1 -1 0.03 0.0216333 0.0194628 99 63 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_003.v common 6.20 vpr 64.43 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29800 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2357 1078 12186 3608 6974 1604 64.4 MiB 0.07 0.00 4.53839 3.58799 -116.676 -3.58799 3.58799 0.25 0.000295115 0.00027033 0.0302567 0.0279761 -1 -1 -1 -1 36 2482 30 6.99608e+06 264882 648988. 2245.63 4.46 0.190584 0.167465 26050 158493 -1 2238 23 1374 1912 157043 33421 4.08876 4.08876 -130.004 -4.08876 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0161449 0.0144234 75 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_004.v common 2.49 vpr 63.83 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29748 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65364 29 32 308 248 1 182 80 17 17 289 -1 unnamed_device 24.9 MiB 0.33 2573 764 13496 3536 9305 655 63.8 MiB 0.09 0.00 5.42531 4.05748 -115.939 -4.05748 4.05748 0.24 0.000828626 0.000781172 0.0376447 0.0347493 -1 -1 -1 -1 36 2604 27 6.99608e+06 279598 648988. 2245.63 0.77 0.0932788 0.0829728 26050 158493 -1 1796 20 1431 2220 152925 38511 3.99626 3.99626 -126.688 -3.99626 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.015111 0.0135488 79 31 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_005.v common 3.59 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29848 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 336 268 1 193 80 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2057 952 12464 3721 7118 1625 64.7 MiB 0.06 0.00 5.56057 4.88167 -146.243 -4.88167 4.88167 0.25 0.000331052 0.00030369 0.0256676 0.0235046 -1 -1 -1 -1 44 2790 26 6.99608e+06 235451 787024. 2723.27 1.89 0.151492 0.133144 27778 195446 -1 2240 23 1634 2747 222001 48807 4.40571 4.40571 -143.589 -4.40571 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0197017 0.0177011 86 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_006.v common 2.89 vpr 65.35 MiB -1 -1 0.12 18440 1 0.03 -1 -1 29780 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66916 32 32 366 295 1 222 88 17 17 289 -1 unnamed_device 25.6 MiB 0.24 2506 1118 13933 5613 7680 640 65.3 MiB 0.07 0.00 4.26916 3.42564 -123.507 -3.42564 3.42564 0.25 0.000345196 0.00031104 0.0287072 0.0263298 -1 -1 -1 -1 38 3421 45 6.99608e+06 353176 678818. 2348.85 1.26 0.112321 0.0993323 26626 170182 -1 2462 24 1784 3007 215704 50106 3.76796 3.76796 -132.934 -3.76796 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0195075 0.0174687 99 58 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_007.v common 2.41 vpr 64.68 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30136 -1 -1 18 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 27 32 259 221 1 152 77 17 17 289 -1 unnamed_device 25.2 MiB 0.25 1709 563 9857 3638 4045 2174 64.7 MiB 0.05 0.00 4.67622 3.83492 -100.928 -3.83492 3.83492 0.26 0.000310689 0.000287664 0.022248 0.0206329 -1 -1 -1 -1 38 1948 27 6.99608e+06 264882 678818. 2348.85 0.78 0.0780478 0.0687188 26626 170182 -1 1392 30 1579 2262 176346 42562 3.41652 3.41652 -110.525 -3.41652 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0218746 0.0192852 65 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_008.v common 2.40 vpr 64.66 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29804 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 24.9 MiB 0.11 1776 919 11547 2651 7976 920 64.7 MiB 0.05 0.00 3.1255 2.7565 -95.0074 -2.7565 2.7565 0.26 0.000293209 0.000264748 0.0180705 0.0165422 -1 -1 -1 -1 36 2309 50 6.99608e+06 397324 648988. 2245.63 0.94 0.103789 0.0914604 26050 158493 -1 1978 22 1218 2212 171223 38751 2.65381 2.65381 -102.167 -2.65381 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0148703 0.0132452 69 4 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_009.v common 3.28 vpr 65.09 MiB -1 -1 0.15 18064 1 0.03 -1 -1 29792 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66652 31 32 317 271 1 204 81 17 17 289 -1 unnamed_device 25.3 MiB 0.23 2338 1082 14256 5263 7162 1831 65.1 MiB 0.07 0.00 4.24759 3.13884 -116.913 -3.13884 3.13884 0.29 0.000304151 0.000278446 0.0274291 0.0251884 -1 -1 -1 -1 40 2502 31 6.99608e+06 264882 706193. 2443.58 1.59 0.13523 0.118366 26914 176310 -1 2233 22 1689 2280 192202 40085 3.05882 3.05882 -122.616 -3.05882 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0162855 0.014578 83 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_010.v common 4.75 vpr 64.41 MiB -1 -1 0.14 17676 1 0.03 -1 -1 29648 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 32 32 298 248 1 181 79 17 17 289 -1 unnamed_device 25.3 MiB 0.24 1862 1015 12247 3678 6923 1646 64.4 MiB 0.07 0.00 3.99837 3.64037 -128.737 -3.64037 3.64037 0.25 0.000447112 0.000420921 0.0321216 0.0299558 -1 -1 -1 -1 34 2533 32 6.99608e+06 220735 618332. 2139.56 3.11 0.172253 0.152194 25762 151098 -1 2146 19 1516 1997 164767 35720 3.09382 3.09382 -128.206 -3.09382 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0141017 0.0126303 72 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_011.v common 3.34 vpr 64.45 MiB -1 -1 0.16 18060 1 0.03 -1 -1 29772 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 30 32 303 262 1 186 79 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2266 960 13599 4745 6819 2035 64.4 MiB 0.09 0.00 4.98263 3.86818 -125.247 -3.86818 3.86818 0.28 0.000424381 0.00038739 0.0373622 0.0341447 -1 -1 -1 -1 36 2348 40 6.99608e+06 250167 648988. 2245.63 1.51 0.148585 0.130262 26050 158493 -1 2064 21 1422 1950 168607 36652 3.59731 3.59731 -129.651 -3.59731 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0172651 0.0154663 79 63 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_012.v common 2.79 vpr 64.71 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29692 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 32 32 276 237 1 165 78 17 17 289 -1 unnamed_device 24.9 MiB 0.24 1950 725 8212 1860 5677 675 64.7 MiB 0.05 0.00 4.10243 3.37048 -107.801 -3.37048 3.37048 0.25 0.000669283 0.000624933 0.0224593 0.0208535 -1 -1 -1 -1 38 2443 48 6.99608e+06 206020 678818. 2348.85 1.17 0.109588 0.0965962 26626 170182 -1 1781 21 1241 1639 121264 31618 3.06712 3.06712 -115.463 -3.06712 0 0 902133. 3121.57 0.03 0.04 0.10 -1 -1 0.03 0.0151789 0.0135417 65 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 3.29 vpr 64.48 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29624 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 344 272 1 201 82 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2682 954 13076 5089 6303 1684 64.5 MiB 0.07 0.00 4.83632 3.86972 -128.357 -3.86972 3.86972 0.25 0.000326098 0.000297786 0.0290014 0.0266927 -1 -1 -1 -1 42 2795 25 6.99608e+06 264882 744469. 2576.02 1.57 0.143204 0.125742 27202 183097 -1 2199 24 1772 2664 231395 52184 3.34801 3.34801 -126.15 -3.34801 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0187747 0.0168077 85 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_014.v common 3.13 vpr 65.34 MiB -1 -1 0.20 18060 1 0.03 -1 -1 29688 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66908 32 32 363 295 1 228 85 17 17 289 -1 unnamed_device 25.2 MiB 0.32 2692 1244 14407 4661 7812 1934 65.3 MiB 0.08 0.00 5.90964 4.79277 -149.984 -4.79277 4.79277 0.27 0.000337196 0.000308944 0.0320247 0.0294721 -1 -1 -1 -1 40 2811 20 6.99608e+06 309029 706193. 2443.58 1.17 0.123832 0.110017 26914 176310 -1 2538 20 1946 2619 212273 44432 4.38451 4.38451 -153.65 -4.38451 0 0 926341. 3205.33 0.04 0.05 0.14 -1 -1 0.04 0.017113 0.0153806 96 61 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_015.v common 2.96 vpr 64.60 MiB -1 -1 0.11 18296 1 0.03 -1 -1 30276 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 29 32 248 215 1 150 78 17 17 289 -1 unnamed_device 24.9 MiB 0.31 1740 893 9706 2711 5534 1461 64.6 MiB 0.05 0.00 3.47743 2.91415 -94.4077 -2.91415 2.91415 0.25 0.000254157 0.000232628 0.020588 0.018958 -1 -1 -1 -1 32 2036 22 6.99608e+06 250167 586450. 2029.24 1.29 0.106588 0.0929905 25474 144626 -1 1646 20 1019 1427 101641 22220 2.71507 2.71507 -98.7671 -2.71507 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0128596 0.0114275 62 27 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_016.v common 2.63 vpr 65.34 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66912 32 32 370 297 1 219 83 17 17 289 -1 unnamed_device 25.7 MiB 0.35 2362 1073 15563 6532 7835 1196 65.3 MiB 0.08 0.00 4.16944 3.57294 -125.244 -3.57294 3.57294 0.24 0.000347667 0.000317742 0.0318598 0.0291397 -1 -1 -1 -1 38 2963 48 6.99608e+06 279598 678818. 2348.85 0.89 0.110101 0.0973561 26626 170182 -1 2204 21 1887 2913 199419 44516 3.57851 3.57851 -131.037 -3.57851 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0176817 0.0158624 98 58 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_017.v common 3.04 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29840 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 338 269 1 198 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2635 1084 14431 4177 8907 1347 64.5 MiB 0.08 0.00 4.64181 3.75386 -123.111 -3.75386 3.75386 0.25 0.000409682 0.000377196 0.036391 0.033598 -1 -1 -1 -1 36 2769 26 6.99608e+06 250167 648988. 2245.63 1.27 0.155204 0.138893 26050 158493 -1 2414 20 1701 2429 219821 56511 3.11862 3.11862 -126.555 -3.11862 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0208099 0.0188496 83 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_018.v common 3.89 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29584 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66612 32 32 323 276 1 210 81 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2734 1198 13031 4384 6941 1706 65.1 MiB 0.06 0.00 4.46501 3.1116 -120.136 -3.1116 3.1116 0.27 0.000301401 0.000276115 0.0248043 0.0226518 -1 -1 -1 -1 34 2850 47 6.99608e+06 250167 618332. 2139.56 2.24 0.158245 0.138253 25762 151098 -1 2471 21 1733 2316 195072 42876 3.22062 3.22062 -126.364 -3.22062 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0162061 0.0145209 84 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_019.v common 2.76 vpr 64.13 MiB -1 -1 0.13 18060 1 0.02 -1 -1 29784 -1 -1 14 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 30 32 222 206 1 135 76 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1543 727 10476 3465 5449 1562 64.1 MiB 0.04 0.00 2.68936 2.31346 -87.3083 -2.31346 2.31346 0.25 0.000244077 0.000223557 0.0172966 0.0158483 -1 -1 -1 -1 32 1548 26 6.99608e+06 206020 586450. 2029.24 1.21 0.103854 0.089959 25474 144626 -1 1415 22 733 828 76674 17191 2.18948 2.18948 -92.4069 -2.18948 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0121979 0.0108198 52 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_020.v common 3.85 vpr 63.91 MiB -1 -1 0.12 17712 1 0.03 -1 -1 29792 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65448 31 32 291 243 1 172 78 17 17 289 -1 unnamed_device 24.5 MiB 0.72 2133 838 8046 1881 5711 454 63.9 MiB 0.04 0.00 5.43629 4.06642 -132.88 -4.06642 4.06642 0.35 0.000286595 0.000262175 0.0155859 0.0143043 -1 -1 -1 -1 34 2585 50 6.99608e+06 220735 618332. 2139.56 1.53 0.13142 0.114418 25762 151098 -1 1987 22 1400 2056 153586 36992 3.64846 3.64846 -134.265 -3.64846 0 0 787024. 2723.27 0.04 0.07 0.13 -1 -1 0.04 0.0259421 0.0231603 70 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_021.v common 3.79 vpr 64.61 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30348 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 342 271 1 200 92 17 17 289 -1 unnamed_device 25.2 MiB 0.31 2545 898 17687 6355 8833 2499 64.6 MiB 0.08 0.00 5.23013 4.09659 -137.139 -4.09659 4.09659 0.24 0.000327188 0.000299437 0.0312595 0.0286912 -1 -1 -1 -1 38 2615 31 6.99608e+06 412039 678818. 2348.85 2.03 0.169548 0.152529 26626 170182 -1 1982 23 1854 2804 201893 47345 4.6472 4.6472 -149.149 -4.6472 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0179156 0.0160457 92 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_022.v common 3.69 vpr 64.76 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30104 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 372 300 1 225 84 17 17 289 -1 unnamed_device 25.2 MiB 0.37 2481 1280 13260 3957 7480 1823 64.8 MiB 0.08 0.00 5.12435 4.27615 -135.126 -4.27615 4.27615 0.26 0.000351019 0.000321597 0.0324092 0.0299401 -1 -1 -1 -1 44 3006 22 6.99608e+06 294314 787024. 2723.27 1.86 0.161059 0.14195 27778 195446 -1 2489 20 1768 2665 213136 44814 4.30622 4.30622 -143.652 -4.30622 0 0 997811. 3452.63 0.04 0.05 0.10 -1 -1 0.04 0.0175618 0.0158387 97 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_023.v common 2.37 vpr 64.02 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30140 -1 -1 17 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65556 26 32 190 182 1 123 75 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1496 591 9871 3440 4773 1658 64.0 MiB 0.03 0.00 3.5328 2.5304 -72.9745 -2.5304 2.5304 0.27 0.000201051 0.000183539 0.0137083 0.0125318 -1 -1 -1 -1 30 1434 20 6.99608e+06 250167 556674. 1926.21 0.88 0.0661549 0.0573686 25186 138497 -1 1178 19 742 883 70756 15921 2.30998 2.30998 -75.3621 -2.30998 0 0 706193. 2443.58 0.03 0.03 0.08 -1 -1 0.03 0.0122099 0.0107687 51 30 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_024.v common 6.67 vpr 64.61 MiB -1 -1 0.21 17672 1 0.03 -1 -1 30252 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 285 227 1 160 81 17 17 289 -1 unnamed_device 25.2 MiB 0.35 1881 1025 10231 3161 5849 1221 64.6 MiB 0.07 0.00 5.10855 4.37465 -123.584 -4.37465 4.37465 0.46 0.000291795 0.000266598 0.0320495 0.0296815 -1 -1 -1 -1 34 2652 24 6.99608e+06 250167 618332. 2139.56 4.51 0.160997 0.141917 25762 151098 -1 2217 22 1494 2515 241172 49180 3.78976 3.78976 -130.242 -3.78976 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0154296 0.0137911 66 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_025.v common 1.95 vpr 64.21 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29736 -1 -1 10 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65752 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1439 560 9374 3843 5323 208 64.2 MiB 0.07 0.00 2.54695 2.03911 -69.5392 -2.03911 2.03911 0.28 0.000517782 0.00047721 0.0311304 0.0286357 -1 -1 -1 -1 32 1253 27 6.99608e+06 147157 586450. 2029.24 0.57 0.0745683 0.0659302 25474 144626 -1 1084 17 554 676 57342 13979 1.94502 1.94502 -76.2104 -1.94502 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00875001 0.00782223 43 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_026.v common 3.04 vpr 64.42 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30180 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 32 32 300 245 1 176 79 17 17 289 -1 unnamed_device 24.9 MiB 0.75 2120 991 10050 3166 5397 1487 64.4 MiB 0.05 0.00 5.61451 4.50471 -128.436 -4.50471 4.50471 0.24 0.000301009 0.000274742 0.0212028 0.0195085 -1 -1 -1 -1 34 2653 41 6.99608e+06 220735 618332. 2139.56 0.94 0.100568 0.0883959 25762 151098 -1 2097 19 1258 1913 140387 31529 3.94702 3.94702 -130.561 -3.94702 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143834 0.0129277 73 24 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_027.v common 3.06 vpr 64.92 MiB -1 -1 0.10 17672 1 0.03 -1 -1 29956 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 25.2 MiB 0.10 1823 770 8047 1794 5817 436 64.9 MiB 0.04 0.00 3.17834 2.84195 -96.8757 -2.84195 2.84195 0.25 0.000307522 0.000280239 0.0139893 0.0127846 -1 -1 -1 -1 38 2286 24 6.99608e+06 397324 678818. 2348.85 1.45 0.120098 0.104798 26626 170182 -1 1846 20 1304 2290 140400 35421 2.96851 2.96851 -105.541 -2.96851 0 0 902133. 3121.57 0.05 0.07 0.16 -1 -1 0.05 0.0249902 0.0224145 77 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_028.v common 7.89 vpr 65.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29768 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 338 277 1 204 84 17 17 289 -1 unnamed_device 25.2 MiB 0.46 2724 1022 8136 1841 6065 230 65.1 MiB 0.05 0.00 5.37647 4.14137 -127.473 -4.14137 4.14137 0.36 0.000375091 0.000347255 0.0168054 0.0153915 -1 -1 -1 -1 38 3057 31 6.99608e+06 294314 678818. 2348.85 5.89 0.19333 0.169565 26626 170182 -1 2256 20 1754 2596 181852 41367 3.87782 3.87782 -133.503 -3.87782 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0166011 0.0149371 88 50 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_029.v common 2.51 vpr 64.73 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29804 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 32 32 284 241 1 168 78 17 17 289 -1 unnamed_device 24.9 MiB 0.51 1906 924 9872 3709 5164 999 64.7 MiB 0.05 0.00 3.74453 3.11176 -114.352 -3.11176 3.11176 0.25 0.000287639 0.000263831 0.0210304 0.0193592 -1 -1 -1 -1 34 2359 22 6.99608e+06 206020 618332. 2139.56 0.67 0.0852771 0.0749924 25762 151098 -1 2040 23 1396 2031 159719 34924 3.14212 3.14212 -122.708 -3.14212 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0155618 0.0138549 68 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_030.v common 3.33 vpr 63.88 MiB -1 -1 0.18 17676 1 0.02 -1 -1 29840 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65416 30 32 262 227 1 160 78 17 17 289 -1 unnamed_device 24.9 MiB 0.18 1816 788 8212 1940 5916 356 63.9 MiB 0.04 0.00 4.36766 3.76823 -111.393 -3.76823 3.76823 0.24 0.000268796 0.000246457 0.014825 0.0136157 -1 -1 -1 -1 36 2251 27 6.99608e+06 235451 648988. 2245.63 1.49 0.114612 0.0991656 26050 158493 -1 1776 64 1632 2908 490429 252067 3.39226 3.39226 -111.31 -3.39226 0 0 828058. 2865.25 0.03 0.20 0.15 -1 -1 0.03 0.0388827 0.0341788 65 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_031.v common 2.37 vpr 64.65 MiB -1 -1 0.12 17472 1 0.02 -1 -1 29824 -1 -1 17 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 28 32 260 223 1 152 77 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1683 804 11650 4924 6170 556 64.7 MiB 0.05 0.00 4.26016 3.78259 -116.363 -3.78259 3.78259 0.25 0.000265538 0.000243257 0.0203419 0.0186211 -1 -1 -1 -1 40 1766 19 6.99608e+06 250167 706193. 2443.58 0.64 0.0678464 0.0597412 26914 176310 -1 1619 17 889 1497 109998 24855 3.37506 3.37506 -112.039 -3.37506 0 0 926341. 3205.33 0.05 0.05 0.17 -1 -1 0.05 0.0182635 0.0163129 69 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_032.v common 2.30 vpr 64.55 MiB -1 -1 0.13 17680 1 0.03 -1 -1 29808 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1562 788 6108 1413 4387 308 64.5 MiB 0.03 0.00 3.55103 3.30043 -111.23 -3.30043 3.30043 0.25 0.00031688 0.00027615 0.0131315 0.0120434 -1 -1 -1 -1 36 2159 28 6.99608e+06 191304 648988. 2245.63 0.80 0.0795214 0.0697774 26050 158493 -1 1866 20 1176 1858 150356 33149 3.08997 3.08997 -117.255 -3.08997 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0133256 0.0119122 59 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_033.v common 2.91 vpr 64.66 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30288 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 31 32 271 231 1 164 78 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1729 914 6552 1539 4793 220 64.7 MiB 0.03 0.00 3.64733 3.26948 -110.36 -3.26948 3.26948 0.24 0.000274842 0.000251498 0.0124484 0.0114395 -1 -1 -1 -1 38 2086 22 6.99608e+06 220735 678818. 2348.85 1.41 0.113843 0.0989225 26626 170182 -1 1766 19 1123 1539 113480 24974 2.95762 2.95762 -107.253 -2.95762 0 0 902133. 3121.57 0.03 0.03 0.09 -1 -1 0.03 0.0130744 0.0117173 65 30 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_034.v common 3.02 vpr 65.02 MiB -1 -1 0.23 18060 1 0.03 -1 -1 30260 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 29 32 291 250 1 177 79 17 17 289 -1 unnamed_device 25.1 MiB 0.30 1970 870 12923 5432 7041 450 65.0 MiB 0.06 0.00 3.19185 3.0305 -101.634 -3.0305 3.0305 0.25 0.0002811 0.000256228 0.026476 0.024338 -1 -1 -1 -1 34 2394 43 6.99608e+06 264882 618332. 2139.56 1.28 0.123062 0.107742 25762 151098 -1 1866 20 1335 1783 151180 34619 2.90282 2.90282 -102.948 -2.90282 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0142251 0.0127067 75 54 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_035.v common 5.13 vpr 65.27 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30252 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66840 32 32 367 282 1 214 85 17 17 289 -1 unnamed_device 25.2 MiB 0.22 2522 1172 14035 4232 7971 1832 65.3 MiB 0.17 0.00 4.99868 4.08568 -124.995 -4.08568 4.08568 0.27 0.000960124 0.000884277 0.076292 0.0708771 -1 -1 -1 -1 36 3145 22 6.99608e+06 309029 648988. 2245.63 3.32 0.224409 0.200545 26050 158493 -1 2479 23 1718 2753 202121 45212 3.89121 3.89121 -131.794 -3.89121 0 0 828058. 2865.25 0.03 0.06 0.14 -1 -1 0.03 0.020053 0.0180574 91 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_036.v common 2.64 vpr 65.45 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30308 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67016 32 32 391 311 1 244 85 17 17 289 -1 unnamed_device 25.6 MiB 0.27 3114 1259 14779 4738 7682 2359 65.4 MiB 0.18 0.00 5.22142 3.95648 -143.346 -3.95648 3.95648 0.25 0.000988432 0.000921433 0.0827453 0.0770468 -1 -1 -1 -1 38 3454 34 6.99608e+06 309029 678818. 2348.85 0.82 0.15522 0.140296 26626 170182 -1 2633 24 2431 3409 267181 56072 3.57966 3.57966 -146.352 -3.57966 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0199938 0.017896 103 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_037.v common 3.43 vpr 64.29 MiB -1 -1 0.12 18444 1 0.02 -1 -1 29780 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 31 32 279 237 1 161 77 17 17 289 -1 unnamed_device 24.9 MiB 0.30 1951 789 11976 3042 8492 442 64.3 MiB 0.06 0.00 4.50867 3.52417 -108.752 -3.52417 3.52417 0.26 0.000669405 0.0006251 0.0285923 0.0264143 -1 -1 -1 -1 36 2241 46 6.99608e+06 206020 648988. 2245.63 1.65 0.131689 0.116324 26050 158493 -1 1842 19 1371 2033 165078 39629 3.27322 3.27322 -114.522 -3.27322 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0134904 0.0120612 67 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_038.v common 2.81 vpr 65.36 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29968 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66932 31 32 370 297 1 227 85 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2471 1139 11059 3848 5463 1748 65.4 MiB 0.06 0.00 3.93715 3.60485 -125.992 -3.60485 3.60485 0.24 0.000340222 0.000310302 0.0228227 0.0209047 -1 -1 -1 -1 38 3226 39 6.99608e+06 323745 678818. 2348.85 1.11 0.101109 0.0890899 26626 170182 -1 2488 20 1747 2530 216446 46223 3.50736 3.50736 -133.253 -3.50736 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0172056 0.0154889 98 61 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_039.v common 7.93 vpr 65.27 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30176 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66836 31 32 377 302 1 235 85 17 17 289 -1 unnamed_device 25.6 MiB 0.26 3086 1318 10687 2982 7130 575 65.3 MiB 0.06 0.00 6.44118 5.00244 -160.349 -5.00244 5.00244 0.25 0.000364276 0.000335521 0.022151 0.0203222 -1 -1 -1 -1 38 3194 28 6.99608e+06 323745 678818. 2348.85 6.29 0.176922 0.15499 26626 170182 -1 2740 19 2162 3082 228411 49616 4.82274 4.82274 -169.003 -4.82274 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0170405 0.0153752 101 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_040.v common 3.46 vpr 65.41 MiB -1 -1 0.13 18048 1 0.03 -1 -1 29768 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66980 31 32 383 305 1 232 84 17 17 289 -1 unnamed_device 25.6 MiB 0.68 2998 1211 13809 5832 7618 359 65.4 MiB 0.09 0.00 6.73307 4.94768 -163.914 -4.94768 4.94768 0.26 0.000351527 0.000321331 0.040439 0.0373557 -1 -1 -1 -1 38 3344 24 6.99608e+06 309029 678818. 2348.85 1.31 0.133483 0.119387 26626 170182 -1 2611 24 2258 3370 271018 68504 4.84 4.84 -173.04 -4.84 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.0207315 0.0186332 101 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_041.v common 2.96 vpr 64.58 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29740 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66132 31 32 352 285 1 214 82 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2321 1209 11118 3541 5840 1737 64.6 MiB 0.06 0.00 4.10443 3.47793 -120.035 -3.47793 3.47793 0.25 0.000339383 0.000311035 0.0228619 0.0209898 -1 -1 -1 -1 38 3104 43 6.99608e+06 279598 678818. 2348.85 1.16 0.105384 0.0934951 26626 170182 -1 2395 22 1987 2942 229567 48017 3.36022 3.36022 -127.979 -3.36022 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0181155 0.0162911 90 55 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_042.v common 2.91 vpr 64.39 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 291 242 1 173 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2257 1074 10584 2543 6589 1452 64.4 MiB 0.05 0.00 4.8427 4.02108 -120.371 -4.02108 4.02108 0.24 0.000295137 0.000271181 0.0192343 0.0176373 -1 -1 -1 -1 34 2686 27 6.99608e+06 264882 618332. 2139.56 1.31 0.0984721 0.0865377 25762 151098 -1 2408 21 1352 2027 180812 38694 3.83326 3.83326 -129.933 -3.83326 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0148508 0.0132692 73 27 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_043.v common 8.73 vpr 65.75 MiB -1 -1 0.13 18060 1 0.04 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67328 32 32 457 356 1 282 90 17 17 289 -1 unnamed_device 26.4 MiB 0.34 3052 1509 12753 3455 8062 1236 65.8 MiB 0.08 0.00 6.26717 5.14656 -172.851 -5.14656 5.14656 0.24 0.000438438 0.000399665 0.0312348 0.0287359 -1 -1 -1 -1 40 3984 25 6.99608e+06 382608 706193. 2443.58 6.88 0.245438 0.215822 26914 176310 -1 3415 22 2474 3639 272449 59278 5.07634 5.07634 -175.218 -5.07634 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0225554 0.0203049 127 87 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_044.v common 2.27 vpr 64.58 MiB -1 -1 0.14 17672 1 0.03 -1 -1 29648 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66132 31 32 261 225 1 158 77 17 17 289 -1 unnamed_device 24.8 MiB 0.30 1593 899 7412 1777 4948 687 64.6 MiB 0.04 0.00 3.6621 3.0623 -104.163 -3.0623 3.0623 0.25 0.000597636 0.000555705 0.0176173 0.0163332 -1 -1 -1 -1 32 2111 32 6.99608e+06 206020 586450. 2029.24 0.60 0.0699195 0.0614205 25474 144626 -1 1852 20 1077 1450 120781 26826 3.31142 3.31142 -117.221 -3.31142 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0140206 0.0125371 65 28 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_045.v common 2.66 vpr 65.18 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30228 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66748 31 32 337 267 1 199 81 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2145 1115 11106 4094 5276 1736 65.2 MiB 0.06 0.00 4.77304 4.27184 -135.826 -4.27184 4.27184 0.25 0.000324833 0.000296411 0.0225737 0.0206979 -1 -1 -1 -1 44 2697 25 6.99608e+06 264882 787024. 2723.27 1.00 0.101064 0.0892623 27778 195446 -1 2120 21 1262 1981 149067 31664 4.02291 4.02291 -134.519 -4.02291 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0168417 0.0151147 82 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_046.v common 3.33 vpr 65.23 MiB -1 -1 0.12 18440 1 0.04 -1 -1 30020 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66800 32 32 349 284 1 213 84 17 17 289 -1 unnamed_device 25.2 MiB 0.34 2736 1076 15273 5235 7717 2321 65.2 MiB 0.08 0.00 4.55139 3.66953 -119.489 -3.66953 3.66953 0.24 0.000334283 0.000306338 0.0300208 0.0275113 -1 -1 -1 -1 42 2891 20 6.99608e+06 294314 744469. 2576.02 1.52 0.137871 0.120656 27202 183097 -1 2348 19 1511 2377 177851 40110 3.63266 3.63266 -126.058 -3.63266 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0163287 0.0147117 90 53 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_047.v common 7.22 vpr 64.62 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30168 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 32 32 291 230 1 160 83 17 17 289 -1 unnamed_device 24.9 MiB 0.20 1772 1011 10343 3054 6149 1140 64.6 MiB 0.09 0.00 4.52137 4.01417 -123.961 -4.01417 4.01417 0.29 0.000533086 0.000484878 0.0332193 0.0304525 -1 -1 -1 -1 36 2627 27 6.99608e+06 279598 648988. 2245.63 5.58 0.170154 0.149886 26050 158493 -1 2246 27 1497 2733 298227 86162 3.91606 3.91606 -131.254 -3.91606 0 0 828058. 2865.25 0.03 0.08 0.08 -1 -1 0.03 0.0183437 0.0162826 70 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_048.v common 3.80 vpr 65.15 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29736 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66716 32 32 353 287 1 210 83 17 17 289 -1 unnamed_device 25.8 MiB 0.48 2562 1041 14123 5669 6794 1660 65.2 MiB 0.09 0.00 4.62756 3.95722 -121.021 -3.95722 3.95722 0.25 0.000523358 0.000494676 0.0370832 0.0342115 -1 -1 -1 -1 38 3059 28 6.99608e+06 279598 678818. 2348.85 1.73 0.173229 0.152378 26626 170182 -1 2276 22 1550 2190 162466 35607 3.46336 3.46336 -123.742 -3.46336 0 0 902133. 3121.57 0.05 0.05 0.14 -1 -1 0.05 0.0177621 0.0159143 91 55 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_049.v common 4.27 vpr 65.19 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30164 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66756 32 32 361 291 1 214 85 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2404 1228 14407 4938 7065 2404 65.2 MiB 0.08 0.00 4.47599 3.61653 -127.814 -3.61653 3.61653 0.26 0.000342994 0.000313604 0.0323871 0.0296708 -1 -1 -1 -1 34 3482 45 6.99608e+06 309029 618332. 2139.56 2.58 0.169262 0.149247 25762 151098 -1 2670 20 1670 2442 197737 43022 3.59376 3.59376 -134.576 -3.59376 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0174682 0.0157616 94 55 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_050.v common 2.79 vpr 65.41 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29852 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 382 305 1 237 86 17 17 289 -1 unnamed_device 26.0 MiB 0.28 2390 1306 9725 3245 4874 1606 65.4 MiB 0.06 0.00 4.47137 3.65053 -130.846 -3.65053 3.65053 0.25 0.000352114 0.00032115 0.0220394 0.0202648 -1 -1 -1 -1 40 3093 27 6.99608e+06 323745 706193. 2443.58 1.04 0.110123 0.09724 26914 176310 -1 2643 22 2052 2804 233702 50043 3.29947 3.29947 -131.275 -3.29947 0 0 926341. 3205.33 0.03 0.07 0.11 -1 -1 0.03 0.0235983 0.0212753 101 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_051.v common 6.58 vpr 64.65 MiB -1 -1 0.12 17748 1 0.03 -1 -1 29776 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66200 32 32 306 248 1 175 80 17 17 289 -1 unnamed_device 25.2 MiB 0.41 2053 1074 11776 3968 6127 1681 64.6 MiB 0.07 0.00 5.26523 4.40603 -128.032 -4.40603 4.40603 0.26 0.000728279 0.000680288 0.0316996 0.0293502 -1 -1 -1 -1 34 2691 25 6.99608e+06 235451 618332. 2139.56 4.79 0.197275 0.172981 25762 151098 -1 2202 23 1453 2321 173808 37601 4.15667 4.15667 -136.845 -4.15667 0 0 787024. 2723.27 0.03 0.05 0.09 -1 -1 0.03 0.0195148 0.0174502 74 24 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_052.v common 3.39 vpr 64.48 MiB -1 -1 0.17 17676 1 0.03 -1 -1 29596 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 319 257 1 191 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2287 910 14606 5914 7002 1690 64.5 MiB 0.07 0.00 4.83128 4.09737 -124.66 -4.09737 4.09737 0.24 0.000310375 0.000283813 0.0282189 0.0258265 -1 -1 -1 -1 40 2417 38 6.99608e+06 250167 706193. 2443.58 1.69 0.153958 0.134164 26914 176310 -1 2039 22 1754 2409 172828 40103 4.13556 4.13556 -134.855 -4.13556 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0170663 0.0152923 79 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_053.v common 4.20 vpr 65.36 MiB -1 -1 0.22 18680 1 0.03 -1 -1 29812 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66928 31 32 373 299 1 222 83 17 17 289 -1 unnamed_device 25.3 MiB 0.29 3060 1061 14663 6195 7837 631 65.4 MiB 0.07 0.00 5.29948 4.04648 -128.43 -4.04648 4.04648 0.25 0.000346543 0.000316492 0.0300002 0.0274375 -1 -1 -1 -1 44 3255 35 6.99608e+06 294314 787024. 2723.27 2.28 0.202541 0.177628 27778 195446 -1 2207 24 1922 2925 205658 47391 4.38296 4.38296 -146.891 -4.38296 0 0 997811. 3452.63 0.04 0.05 0.12 -1 -1 0.04 0.0192397 0.0172114 96 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_054.v common 3.78 vpr 65.43 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 387 315 1 239 84 17 17 289 -1 unnamed_device 25.6 MiB 0.36 2489 1239 10515 4270 6030 215 65.4 MiB 0.08 0.00 4.49482 3.93712 -132.475 -3.93712 3.93712 0.26 0.00042534 0.0003946 0.0319843 0.0296844 -1 -1 -1 -1 42 3657 38 6.99608e+06 294314 744469. 2576.02 1.97 0.19167 0.168728 27202 183097 -1 2768 23 2154 3218 251393 54624 3.81701 3.81701 -136.091 -3.81701 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0194698 0.0174518 102 77 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_055.v common 2.78 vpr 64.02 MiB -1 -1 0.16 17916 1 0.03 -1 -1 29788 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65560 32 32 251 219 1 151 77 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1737 727 8879 3608 5056 215 64.0 MiB 0.04 0.00 3.88198 3.25548 -102.196 -3.25548 3.25548 0.28 0.00026341 0.0002409 0.0158008 0.0144687 -1 -1 -1 -1 38 1830 24 6.99608e+06 191304 678818. 2348.85 1.16 0.0983347 0.0862121 26626 170182 -1 1501 21 989 1400 93207 22725 2.96192 2.96192 -100.295 -2.96192 0 0 902133. 3121.57 0.03 0.03 0.09 -1 -1 0.03 0.013285 0.0118673 59 23 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_056.v common 7.37 vpr 65.13 MiB -1 -1 0.18 18056 1 0.03 -1 -1 30212 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66696 32 32 341 285 1 216 81 17 17 289 -1 unnamed_device 25.2 MiB 0.30 2337 1049 10756 3701 4965 2090 65.1 MiB 0.06 0.00 4.38205 3.60289 -133.031 -3.60289 3.60289 0.25 0.000415296 0.000387779 0.0239569 0.0220371 -1 -1 -1 -1 40 2703 23 6.99608e+06 250167 706193. 2443.58 5.55 0.167443 0.147046 26914 176310 -1 2352 23 2080 2820 262366 57085 3.88501 3.88501 -148.748 -3.88501 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0176703 0.015799 89 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_057.v common 4.03 vpr 64.22 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29984 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65764 32 32 387 293 1 225 82 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2656 1174 14144 6001 7737 406 64.2 MiB 0.08 0.00 5.84018 4.78152 -149.199 -4.78152 4.78152 0.32 0.00038237 0.00035059 0.0376424 0.0348163 -1 -1 -1 -1 50 2834 24 6.99608e+06 264882 902133. 3121.57 2.10 0.205741 0.181907 28642 213929 -1 2303 22 2041 3172 224362 48220 4.42076 4.42076 -146.875 -4.42076 0 0 1.08113e+06 3740.92 0.04 0.05 0.12 -1 -1 0.04 0.0197493 0.0177838 96 31 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_058.v common 2.62 vpr 65.04 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30412 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 32 32 340 270 1 205 82 17 17 289 -1 unnamed_device 25.3 MiB 0.24 2003 1157 10406 3036 5903 1467 65.0 MiB 0.05 0.00 4.01546 3.80886 -131.153 -3.80886 3.80886 0.25 0.000332988 0.00030492 0.0213291 0.0195744 -1 -1 -1 -1 36 2842 26 6.99608e+06 264882 648988. 2245.63 0.83 0.0904082 0.079963 26050 158493 -1 2400 20 1865 2578 211228 44537 3.22692 3.22692 -130.367 -3.22692 0 0 828058. 2865.25 0.05 0.08 0.15 -1 -1 0.05 0.0276081 0.0248415 83 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_059.v common 2.73 vpr 64.88 MiB -1 -1 0.19 17676 1 0.03 -1 -1 29812 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 30 32 278 235 1 166 86 17 17 289 -1 unnamed_device 25.6 MiB 0.17 1819 953 11237 3335 6152 1750 64.9 MiB 0.05 0.00 4.46953 3.72455 -123.086 -3.72455 3.72455 0.34 0.000295449 0.000271121 0.0207062 0.0190016 -1 -1 -1 -1 32 2493 41 6.99608e+06 353176 586450. 2029.24 0.99 0.0810683 0.0713788 25474 144626 -1 1945 20 1129 1868 155903 34266 3.66766 3.66766 -130.635 -3.66766 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169198 0.0148726 75 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_060.v common 13.97 vpr 65.62 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29780 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67192 32 32 431 332 1 263 86 17 17 289 -1 unnamed_device 25.6 MiB 0.36 3530 1523 10859 3269 7015 575 65.6 MiB 0.07 0.00 8.11443 6.30909 -191.484 -6.30909 6.30909 0.25 0.000409098 0.000372795 0.0269271 0.024715 -1 -1 -1 -1 40 3812 24 6.99608e+06 323745 706193. 2443.58 12.07 0.275135 0.243556 26914 176310 -1 3230 22 2400 3619 307902 64475 5.46454 5.46454 -183.101 -5.46454 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0224372 0.0202166 113 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_061.v common 2.82 vpr 64.55 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30360 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 336 268 1 199 81 17 17 289 -1 unnamed_device 25.6 MiB 0.33 2220 1042 7256 1709 5288 259 64.5 MiB 0.10 0.00 5.22335 4.47706 -136.26 -4.47706 4.47706 0.26 0.000897643 0.000833199 0.040152 0.0374168 -1 -1 -1 -1 36 2668 31 6.99608e+06 250167 648988. 2245.63 1.01 0.123457 0.110111 26050 158493 -1 2169 22 1855 2587 213043 45510 4.09836 4.09836 -141.679 -4.09836 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0173523 0.015543 82 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_062.v common 3.31 vpr 64.49 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30328 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 231 199 1 136 80 17 17 289 -1 unnamed_device 25.0 MiB 0.14 1667 644 6788 1443 5150 195 64.5 MiB 0.04 0.00 3.3651 2.966 -94.919 -2.966 2.966 0.25 0.000257042 0.000236046 0.0117376 0.0108063 -1 -1 -1 -1 36 1886 27 6.99608e+06 235451 648988. 2245.63 1.77 0.127294 0.111299 26050 158493 -1 1559 19 950 1545 119567 29462 2.94467 2.94467 -105.198 -2.94467 0 0 828058. 2865.25 0.05 0.07 0.09 -1 -1 0.05 0.0278513 0.024845 54 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_063.v common 4.46 vpr 65.26 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30232 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66828 32 32 349 273 1 205 84 17 17 289 -1 unnamed_device 25.6 MiB 0.23 2149 1082 11430 4676 6413 341 65.3 MiB 0.06 0.00 5.75835 4.90682 -134.383 -4.90682 4.90682 0.25 0.000333152 0.000304183 0.0230581 0.0211123 -1 -1 -1 -1 50 2420 28 6.99608e+06 294314 902133. 3121.57 2.75 0.210124 0.185284 28642 213929 -1 2106 23 1498 2570 197970 44240 4.41151 4.41151 -133.222 -4.41151 0 0 1.08113e+06 3740.92 0.04 0.06 0.12 -1 -1 0.04 0.0201727 0.0180905 86 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_064.v common 2.35 vpr 64.20 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29800 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 247 207 1 142 80 17 17 289 -1 unnamed_device 24.9 MiB 0.14 1516 866 8852 2265 5550 1037 64.2 MiB 0.07 0.00 3.3589 2.9481 -106.495 -2.9481 2.9481 0.29 0.000477265 0.000433152 0.0294708 0.0271445 -1 -1 -1 -1 32 1986 23 6.99608e+06 235451 586450. 2029.24 0.76 0.0926109 0.0816633 25474 144626 -1 1818 21 1207 1848 144119 31724 2.97567 2.97567 -114.332 -2.97567 0 0 744469. 2576.02 0.04 0.04 0.14 -1 -1 0.04 0.0132219 0.0117761 58 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_065.v common 4.51 vpr 64.35 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29852 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 30 32 278 235 1 168 79 17 17 289 -1 unnamed_device 24.9 MiB 0.27 1881 846 11740 4899 6478 363 64.3 MiB 0.06 0.00 3.88477 3.61627 -115.385 -3.61627 3.61627 0.38 0.000277943 0.000253538 0.0253803 0.0232971 -1 -1 -1 -1 34 2626 42 6.99608e+06 250167 618332. 2139.56 2.59 0.149488 0.131234 25762 151098 -1 1930 22 1548 2150 173949 38779 3.36322 3.36322 -120.284 -3.36322 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0148292 0.0132602 69 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_066.v common 8.09 vpr 65.30 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29796 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66872 29 32 355 287 1 212 82 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2487 1076 7024 1631 5053 340 65.3 MiB 0.04 0.00 4.65503 4.06423 -126.233 -4.06423 4.06423 0.24 0.0003279 0.00030095 0.0150345 0.0137987 -1 -1 -1 -1 40 2852 44 6.99608e+06 309029 706193. 2443.58 6.39 0.19367 0.169529 26914 176310 -1 2416 21 1657 2448 196716 42818 3.649 3.649 -124.232 -3.649 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0171414 0.0153764 94 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_067.v common 5.18 vpr 65.18 MiB -1 -1 0.12 18440 1 0.03 -1 -1 29760 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66744 32 32 358 289 1 214 83 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2512 1102 12323 3030 8331 962 65.2 MiB 0.06 0.00 5.76244 4.57197 -150.669 -4.57197 4.57197 0.25 0.000340918 0.00031236 0.0265798 0.0243785 -1 -1 -1 -1 40 2617 23 6.99608e+06 279598 706193. 2443.58 3.43 0.182268 0.159744 26914 176310 -1 2263 20 1664 2404 159920 36281 4.4118 4.4118 -149.852 -4.4118 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0170972 0.0153704 93 54 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_068.v common 6.18 vpr 65.29 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30264 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66856 32 32 353 285 1 210 82 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2477 1259 12542 3693 7235 1614 65.3 MiB 0.07 0.00 5.61514 4.67867 -148.606 -4.67867 4.67867 0.26 0.000330558 0.000302788 0.0284666 0.0261654 -1 -1 -1 -1 36 3280 30 6.99608e+06 264882 648988. 2245.63 4.40 0.190601 0.1677 26050 158493 -1 2804 20 1753 2535 251826 52553 4.52301 4.52301 -153.738 -4.52301 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0175652 0.0158305 90 51 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_069.v common 2.87 vpr 64.66 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29796 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 276 237 1 160 77 17 17 289 -1 unnamed_device 25.2 MiB 0.39 2019 874 7412 2163 4944 305 64.7 MiB 0.04 0.00 4.43837 3.56127 -113.067 -3.56127 3.56127 0.25 0.000283865 0.000260375 0.0142326 0.0130747 -1 -1 -1 -1 38 2164 36 6.99608e+06 191304 678818. 2348.85 1.10 0.109947 0.0967195 26626 170182 -1 1847 21 1125 1512 114209 25335 3.29786 3.29786 -114.972 -3.29786 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.016037 0.0142694 65 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_070.v common 2.83 vpr 64.50 MiB -1 -1 0.15 17676 1 0.03 -1 -1 29640 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 31 32 319 272 1 200 80 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2059 1143 8680 2684 4726 1270 64.5 MiB 0.06 0.00 3.74443 3.36163 -119.008 -3.36163 3.36163 0.28 0.000348439 0.000322031 0.0245664 0.02271 -1 -1 -1 -1 36 2725 29 6.99608e+06 250167 648988. 2245.63 1.02 0.131981 0.116646 26050 158493 -1 2415 23 1788 2474 198378 43599 3.45072 3.45072 -132.987 -3.45072 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0175891 0.0157376 83 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_071.v common 3.31 vpr 64.93 MiB -1 -1 0.18 18060 1 0.04 -1 -1 30516 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 30 32 329 273 1 202 84 17 17 289 -1 unnamed_device 25.2 MiB 0.37 2292 985 10698 3333 5234 2131 64.9 MiB 0.05 0.00 3.96185 3.1635 -104.256 -3.1635 3.1635 0.25 0.000310397 0.000283766 0.0202326 0.0185443 -1 -1 -1 -1 38 2681 23 6.99608e+06 323745 678818. 2348.85 1.43 0.133462 0.116748 26626 170182 -1 2079 21 1525 2176 145997 33843 3.15117 3.15117 -108.403 -3.15117 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0163276 0.0146456 88 57 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_072.v common 2.62 vpr 64.30 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29820 -1 -1 20 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 28 32 277 229 1 167 80 17 17 289 -1 unnamed_device 24.6 MiB 0.18 2171 750 13324 5641 6785 898 64.3 MiB 0.06 0.00 4.60235 3.68935 -102.007 -3.68935 3.68935 0.26 0.000280311 0.000256331 0.0262871 0.0241405 -1 -1 -1 -1 38 2095 46 6.99608e+06 294314 678818. 2348.85 1.06 0.0999501 0.0881336 26626 170182 -1 1637 20 1275 2053 133456 31957 3.86712 3.86712 -107.152 -3.86712 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0139935 0.0125284 70 27 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_073.v common 4.06 vpr 64.07 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29780 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65612 30 32 317 269 1 200 80 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2064 1130 10400 3752 5071 1577 64.1 MiB 0.08 0.00 4.54182 3.92332 -130.777 -3.92332 3.92332 0.44 0.000299101 0.00027329 0.0360045 0.0331235 -1 -1 -1 -1 44 2351 40 6.99608e+06 264882 787024. 2723.27 1.79 0.167755 0.146837 27778 195446 -1 2079 50 2714 3757 509029 223795 3.54531 3.54531 -130.146 -3.54531 0 0 997811. 3452.63 0.04 0.17 0.11 -1 -1 0.04 0.0301622 0.0264103 84 63 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 3.55 vpr 64.54 MiB -1 -1 0.20 17672 1 0.03 -1 -1 30204 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66088 32 32 335 282 1 216 82 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2365 1114 12542 4673 5784 2085 64.5 MiB 0.08 0.00 3.99224 3.50894 -127.534 -3.50894 3.50894 0.25 0.000315106 0.000287859 0.034242 0.0315552 -1 -1 -1 -1 42 2677 24 6.99608e+06 264882 744469. 2576.02 1.61 0.152336 0.134508 27202 183097 -1 2084 22 1659 2257 159018 34861 3.14317 3.14317 -124.044 -3.14317 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0187501 0.0166729 87 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_075.v common 8.45 vpr 65.02 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29552 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 31 32 293 230 1 168 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2000 982 10903 2684 7356 863 65.0 MiB 0.05 0.00 4.71072 4.12848 -125.314 -4.12848 4.12848 0.24 0.000299526 0.000273857 0.0177575 0.0162742 -1 -1 -1 -1 40 2473 20 6.99608e+06 412039 706193. 2443.58 6.98 0.188456 0.165444 26914 176310 -1 2209 24 1486 2666 236458 56195 4.03642 4.03642 -129.321 -4.03642 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0170776 0.0152593 77 4 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_076.v common 3.08 vpr 64.80 MiB -1 -1 0.15 17916 1 0.03 -1 -1 29968 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 350 275 1 206 83 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2490 1189 13403 4211 7234 1958 64.8 MiB 0.08 0.00 4.89302 4.14724 -142.136 -4.14724 4.14724 0.26 0.00033104 0.000302573 0.034491 0.0318021 -1 -1 -1 -1 36 3453 42 6.99608e+06 279598 648988. 2245.63 1.35 0.125825 0.111916 26050 158493 -1 2897 21 1884 2802 281160 57735 4.19956 4.19956 -157.838 -4.19956 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0184156 0.0165322 87 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_077.v common 4.17 vpr 64.71 MiB -1 -1 0.21 18060 1 0.04 -1 -1 29772 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 32 32 385 308 1 237 85 17 17 289 -1 unnamed_device 25.8 MiB 0.44 2652 1256 15151 5422 7831 1898 64.7 MiB 0.08 0.00 5.94478 5.006 -165.631 -5.006 5.006 0.25 0.000358141 0.000328231 0.0313961 0.0287286 -1 -1 -1 -1 40 3284 27 6.99608e+06 309029 706193. 2443.58 1.99 0.176264 0.156042 26914 176310 -1 2763 21 2194 3069 284504 58389 4.65534 4.65534 -165.239 -4.65534 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.020252 0.0182285 103 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_078.v common 3.00 vpr 65.43 MiB -1 -1 0.14 18296 1 0.03 -1 -1 29856 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 387 309 1 244 86 17 17 289 -1 unnamed_device 25.6 MiB 0.38 3090 1280 16529 5531 8719 2279 65.4 MiB 0.09 0.00 4.97976 4.22796 -143.885 -4.22796 4.22796 0.26 0.000359741 0.000330081 0.0345095 0.0317078 -1 -1 -1 -1 38 3429 46 6.99608e+06 323745 678818. 2348.85 1.11 0.118587 0.105226 26626 170182 -1 2650 21 2083 3065 220833 47744 4.0125 4.0125 -147.917 -4.0125 0 0 902133. 3121.57 0.03 0.06 0.10 -1 -1 0.03 0.0220048 0.0195822 102 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_079.v common 4.55 vpr 64.08 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29876 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65620 30 32 272 232 1 169 79 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1873 976 10388 2655 6704 1029 64.1 MiB 0.05 0.00 4.35146 3.77996 -115.544 -3.77996 3.77996 0.25 0.000298857 0.000275244 0.019425 0.0178398 -1 -1 -1 -1 32 2668 46 6.99608e+06 250167 586450. 2029.24 2.81 0.171253 0.150186 25474 144626 -1 2156 23 1627 2295 190396 40496 3.16982 3.16982 -119.919 -3.16982 0 0 744469. 2576.02 0.04 0.08 0.14 -1 -1 0.04 0.0250296 0.0223372 68 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_080.v common 7.57 vpr 65.39 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29808 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 30 32 375 299 1 231 83 17 17 289 -1 unnamed_device 25.6 MiB 0.35 2543 1226 12863 4164 7357 1342 65.4 MiB 0.07 0.00 6.19097 4.8136 -157.664 -4.8136 4.8136 0.25 0.000343255 0.000314156 0.0271782 0.0248716 -1 -1 -1 -1 38 3234 41 6.99608e+06 309029 678818. 2348.85 5.75 0.208307 0.182755 26626 170182 -1 2608 23 2337 3366 264876 55857 4.57834 4.57834 -160.67 -4.57834 0 0 902133. 3121.57 0.03 0.06 0.11 -1 -1 0.03 0.0198221 0.0178488 101 63 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_081.v common 10.75 vpr 65.09 MiB -1 -1 0.21 18060 1 0.03 -1 -1 29580 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 340 270 1 197 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2353 1072 9338 2392 6620 326 65.1 MiB 0.05 0.00 5.08705 4.46071 -137.725 -4.46071 4.46071 0.25 0.000326806 0.000298657 0.0201311 0.018525 -1 -1 -1 -1 36 3037 36 6.99608e+06 264882 648988. 2245.63 8.96 0.198441 0.174241 26050 158493 -1 2579 20 1968 3193 317298 64436 4.05906 4.05906 -142.951 -4.05906 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0165587 0.014862 83 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_082.v common 5.09 vpr 65.23 MiB -1 -1 0.14 18444 1 0.03 -1 -1 29780 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66800 31 32 340 275 1 195 82 17 17 289 -1 unnamed_device 25.2 MiB 0.52 2485 1077 6846 1660 4720 466 65.2 MiB 0.04 0.00 5.99233 5.0824 -146.792 -5.0824 5.0824 0.25 0.000332049 0.000305039 0.0153348 0.0141025 -1 -1 -1 -1 36 2949 36 6.99608e+06 279598 648988. 2245.63 2.99 0.163543 0.14333 26050 158493 -1 2436 25 1611 2368 219315 58630 4.22141 4.22141 -143.659 -4.22141 0 0 828058. 2865.25 0.05 0.10 0.14 -1 -1 0.05 0.0345574 0.0311452 87 47 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_083.v common 4.20 vpr 64.68 MiB -1 -1 0.14 18296 1 0.03 -1 -1 30180 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 30 32 377 310 1 234 85 17 17 289 -1 unnamed_device 25.2 MiB 0.40 2527 1287 11803 3693 6222 1888 64.7 MiB 0.07 0.00 4.79242 3.97958 -130.547 -3.97958 3.97958 0.28 0.000341223 0.000312216 0.0298593 0.0275985 -1 -1 -1 -1 46 2907 27 6.99608e+06 338461 828058. 2865.25 2.30 0.188811 0.166861 28066 200906 -1 2352 20 1694 2546 209301 42710 3.4157 3.4157 -127.942 -3.4157 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0172781 0.0155465 105 83 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_084.v common 4.16 vpr 65.34 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29776 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66908 32 32 365 294 1 223 83 17 17 289 -1 unnamed_device 25.2 MiB 0.32 2642 1080 13043 4299 6062 2682 65.3 MiB 0.10 0.00 5.91884 4.65647 -145.605 -4.65647 4.65647 0.28 0.000616403 0.000561375 0.039827 0.0366499 -1 -1 -1 -1 58 2339 29 6.99608e+06 279598 997811. 3452.63 2.26 0.197471 0.173865 30370 251734 -1 1947 23 1549 2349 189783 40720 4.15385 4.15385 -138.843 -4.15385 0 0 1.25153e+06 4330.55 0.04 0.05 0.14 -1 -1 0.04 0.0191202 0.0171213 94 57 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_085.v common 3.96 vpr 65.42 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29244 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66988 29 32 378 310 1 232 84 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2249 1133 10332 4059 5536 737 65.4 MiB 0.06 0.00 4.37595 3.76735 -122.856 -3.76735 3.76735 0.25 0.000806941 0.000751406 0.0263063 0.0242243 -1 -1 -1 -1 40 2918 21 6.99608e+06 338461 706193. 2443.58 2.22 0.200676 0.177945 26914 176310 -1 2367 22 1494 2036 156146 35777 4.04156 4.04156 -134.374 -4.04156 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0229383 0.0205342 106 85 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_086.v common 3.20 vpr 64.49 MiB -1 -1 0.16 17676 1 0.03 -1 -1 30300 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 243 205 1 140 77 17 17 289 -1 unnamed_device 24.9 MiB 0.54 1620 885 6108 1414 4233 461 64.5 MiB 0.04 0.00 3.92693 3.42573 -113.797 -3.42573 3.42573 0.27 0.000262716 0.000240101 0.0155632 0.014418 -1 -1 -1 -1 32 2105 20 6.99608e+06 191304 586450. 2029.24 1.23 0.121706 0.106417 25474 144626 -1 1872 20 1044 1623 134418 28714 3.15892 3.15892 -116.975 -3.15892 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145525 0.0129752 56 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_087.v common 3.10 vpr 65.38 MiB -1 -1 0.13 17916 1 0.04 -1 -1 30272 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 373 302 1 234 85 17 17 289 -1 unnamed_device 25.3 MiB 0.25 2757 1184 15523 6072 7602 1849 65.4 MiB 0.08 0.00 6.55248 4.951 -158.167 -4.951 4.951 0.25 0.000359023 0.000329679 0.0314315 0.0288277 -1 -1 -1 -1 38 3214 39 6.99608e+06 309029 678818. 2348.85 1.29 0.120257 0.106819 26626 170182 -1 2557 23 2159 3151 273144 56610 4.50624 4.50624 -154.678 -4.50624 0 0 902133. 3121.57 0.05 0.10 0.11 -1 -1 0.05 0.0328808 0.0296767 98 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_088.v common 4.56 vpr 64.09 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29748 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 32 32 397 314 1 249 85 17 17 289 -1 unnamed_device 24.5 MiB 0.37 2726 1321 14965 5056 8532 1377 64.1 MiB 0.08 0.00 5.25319 4.65797 -164.783 -4.65797 4.65797 0.25 0.000368298 0.000331202 0.0316858 0.0290061 -1 -1 -1 -1 40 3636 25 6.99608e+06 309029 706193. 2443.58 2.70 0.227798 0.201867 26914 176310 -1 2903 21 2508 3573 301907 62282 4.82971 4.82971 -176.472 -4.82971 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0188725 0.0170092 105 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_089.v common 2.76 vpr 64.69 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29784 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 269 231 1 163 77 17 17 289 -1 unnamed_device 25.5 MiB 0.26 1853 737 10346 4283 5770 293 64.7 MiB 0.05 0.00 3.61613 3.25618 -100.635 -3.25618 3.25618 0.26 0.000294064 0.00026383 0.0250246 0.0231762 -1 -1 -1 -1 40 1864 45 6.99608e+06 191304 706193. 2443.58 1.05 0.104956 0.0924776 26914 176310 -1 1561 25 1244 1653 120205 30029 3.41867 3.41867 -112.985 -3.41867 0 0 926341. 3205.33 0.05 0.04 0.17 -1 -1 0.05 0.0158374 0.0140831 66 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_090.v common 2.08 vpr 64.09 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30324 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 24.9 MiB 0.11 1536 858 8360 2256 5168 936 64.1 MiB 0.04 0.00 3.61893 3.28943 -106.361 -3.28943 3.28943 0.35 0.000256667 0.000234795 0.014228 0.0130658 -1 -1 -1 -1 32 2072 26 6.99608e+06 235451 586450. 2029.24 0.56 0.0580191 0.0509893 25474 144626 -1 1856 19 1171 1959 154991 34293 3.14792 3.14792 -114.535 -3.14792 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0130327 0.0116131 59 4 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_091.v common 3.42 vpr 65.25 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29996 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66820 32 32 348 274 1 209 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2619 1051 8270 2110 5627 533 65.3 MiB 0.05 0.00 4.98867 4.02312 -135.346 -4.02312 4.02312 0.24 0.000356126 0.000327305 0.0175964 0.0161306 -1 -1 -1 -1 40 2752 48 6.99608e+06 264882 706193. 2443.58 1.62 0.131444 0.115935 26914 176310 -1 2412 21 1981 2778 221710 49503 4.01046 4.01046 -144.849 -4.01046 0 0 926341. 3205.33 0.05 0.09 0.16 -1 -1 0.05 0.0312576 0.0282401 85 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_092.v common 3.75 vpr 65.31 MiB -1 -1 0.12 17696 1 0.03 -1 -1 30196 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66876 32 32 356 289 1 215 85 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2661 1142 10687 2890 6795 1002 65.3 MiB 0.06 0.00 5.42227 4.69222 -141.619 -4.69222 4.69222 0.24 0.000331438 0.000303919 0.0213103 0.0195584 -1 -1 -1 -1 36 3081 25 6.99608e+06 309029 648988. 2245.63 1.92 0.196571 0.172762 26050 158493 -1 2497 20 1667 2322 178458 40445 4.59211 4.59211 -151.626 -4.59211 0 0 828058. 2865.25 0.03 0.09 0.12 -1 -1 0.03 0.032519 0.0294266 93 56 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_093.v common 4.75 vpr 64.54 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29808 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66092 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 25.3 MiB 0.13 2109 1015 8913 2758 4385 1770 64.5 MiB 0.04 0.00 5.39397 4.48151 -135.956 -4.48151 4.48151 0.25 0.000344854 0.000313183 0.0166858 0.0152261 -1 -1 -1 -1 46 2960 42 6.99608e+06 426755 828058. 2865.25 3.17 0.188439 0.16599 28066 200906 -1 2212 21 1697 3063 248423 56450 4.31935 4.31935 -140.411 -4.31935 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0181888 0.0163971 90 3 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_094.v common 2.90 vpr 65.11 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29988 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 30 32 316 264 1 191 83 17 17 289 -1 unnamed_device 25.6 MiB 0.38 2606 1009 7823 1822 5457 544 65.1 MiB 0.04 0.00 4.76312 3.58427 -106.995 -3.58427 3.58427 0.25 0.000308712 0.000283316 0.015233 0.0140358 -1 -1 -1 -1 36 2586 30 6.99608e+06 309029 648988. 2245.63 1.08 0.106457 0.0937082 26050 158493 -1 2283 24 1925 2911 230611 48960 3.34252 3.34252 -113.894 -3.34252 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0217187 0.0192677 86 52 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_095.v common 3.04 vpr 64.51 MiB -1 -1 0.11 17916 1 0.03 -1 -1 30168 -1 -1 17 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 27 32 255 219 1 145 76 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1732 742 10956 3486 6732 738 64.5 MiB 0.04 0.00 4.92129 3.75245 -110.833 -3.75245 3.75245 0.24 0.000254695 0.00023279 0.0189859 0.0174081 -1 -1 -1 -1 30 1917 29 6.99608e+06 250167 556674. 1926.21 1.56 0.0982599 0.0857575 25186 138497 -1 1600 18 968 1431 102703 23011 3.61546 3.61546 -115.129 -3.61546 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0121467 0.0108756 67 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_096.v common 10.72 vpr 65.53 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29736 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67100 32 32 421 327 1 263 87 17 17 289 -1 unnamed_device 25.6 MiB 0.32 3139 1454 14487 3900 9094 1493 65.5 MiB 0.13 0.00 5.82494 4.22974 -144.161 -4.22974 4.22974 0.30 0.00039563 0.000362842 0.0564457 0.052421 -1 -1 -1 -1 42 3877 49 6.99608e+06 338461 744469. 2576.02 8.82 0.261665 0.23186 27202 183097 -1 3220 21 2143 3398 291996 60989 4.20031 4.20031 -152.043 -4.20031 0 0 949917. 3286.91 0.04 0.06 0.10 -1 -1 0.04 0.0201234 0.0181126 110 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_097.v common 3.24 vpr 64.75 MiB -1 -1 0.15 18060 1 0.03 -1 -1 29756 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 31 32 365 296 1 229 84 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2811 1262 12894 3886 6900 2108 64.7 MiB 0.07 0.00 6.59169 5.46783 -160.186 -5.46783 5.46783 0.25 0.000339653 0.000311033 0.0258576 0.0236764 -1 -1 -1 -1 40 2874 28 6.99608e+06 309029 706193. 2443.58 1.49 0.140763 0.124371 26914 176310 -1 2401 22 2013 2891 213884 45949 4.54281 4.54281 -157.549 -4.54281 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.018057 0.0162127 97 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_098.v common 3.44 vpr 65.15 MiB -1 -1 0.15 18444 1 0.02 -1 -1 29880 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 32 32 331 280 1 215 82 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2580 1220 8448 2298 5647 503 65.1 MiB 0.05 0.00 4.4353 3.55199 -133.806 -3.55199 3.55199 0.26 0.000319361 0.000292362 0.0213717 0.0197884 -1 -1 -1 -1 36 2753 24 6.99608e+06 264882 648988. 2245.63 1.68 0.158365 0.138772 26050 158493 -1 2346 21 1724 2226 174140 38058 3.49956 3.49956 -137.622 -3.49956 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0165778 0.0149044 86 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_099.v common 3.91 vpr 64.49 MiB -1 -1 0.12 17916 1 0.03 -1 -1 30300 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 326 263 1 198 81 17 17 289 -1 unnamed_device 25.2 MiB 0.24 2007 915 11806 4558 6015 1233 64.5 MiB 0.06 0.00 4.69498 4.19833 -126.153 -4.19833 4.19833 0.35 0.000331511 0.000303973 0.027978 0.0258442 -1 -1 -1 -1 44 2540 49 6.99608e+06 250167 787024. 2723.27 2.16 0.194089 0.170363 27778 195446 -1 1804 19 1192 1636 115903 27473 3.77352 3.77352 -123.719 -3.77352 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0177594 0.0161027 80 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_100.v common 2.91 vpr 65.25 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29868 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66816 31 32 373 294 1 216 84 17 17 289 -1 unnamed_device 25.8 MiB 0.36 2762 1151 14907 5290 7728 1889 65.2 MiB 0.09 0.00 5.40098 4.12378 -127.257 -4.12378 4.12378 0.24 0.000371977 0.000340791 0.0370602 0.0340631 -1 -1 -1 -1 40 2607 25 6.99608e+06 309029 706193. 2443.58 1.10 0.12845 0.114036 26914 176310 -1 2325 22 1845 2733 198743 43453 3.81082 3.81082 -130.703 -3.81082 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.019102 0.0171685 97 50 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_101.v common 3.97 vpr 65.03 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29816 -1 -1 20 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 30 32 325 268 1 197 82 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2275 931 9694 3916 5291 487 65.0 MiB 0.05 0.00 4.37729 3.52894 -109.796 -3.52894 3.52894 0.24 0.000319843 0.00028404 0.0189408 0.017331 -1 -1 -1 -1 46 2439 26 6.99608e+06 294314 828058. 2865.25 2.25 0.144389 0.126734 28066 200906 -1 1870 19 1331 2123 160757 36535 3.48697 3.48697 -114.338 -3.48697 0 0 1.01997e+06 3529.29 0.04 0.04 0.11 -1 -1 0.04 0.0153406 0.0138183 85 51 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_102.v common 3.77 vpr 65.11 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29792 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 32 32 350 275 1 209 82 17 17 289 -1 unnamed_device 25.6 MiB 0.29 2452 1191 11118 2720 7663 735 65.1 MiB 0.06 0.00 4.76098 4.21963 -145.335 -4.21963 4.21963 0.25 0.000357095 0.000307568 0.0240345 0.0221081 -1 -1 -1 -1 42 3059 30 6.99608e+06 264882 744469. 2576.02 1.99 0.183276 0.160905 27202 183097 -1 2646 22 2111 3171 339117 78140 4.30592 4.30592 -150.736 -4.30592 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.0180706 0.0162177 87 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_103.v common 3.22 vpr 65.43 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 386 307 1 240 85 17 17 289 -1 unnamed_device 25.5 MiB 0.28 2544 1330 10687 2581 6972 1134 65.4 MiB 0.06 0.00 4.10857 3.66363 -131.207 -3.66363 3.66363 0.24 0.000358631 0.000328675 0.0233891 0.0214854 -1 -1 -1 -1 40 2913 20 6.99608e+06 309029 706193. 2443.58 1.54 0.146169 0.128078 26914 176310 -1 2609 26 2198 3089 256591 54227 3.46877 3.46877 -133.609 -3.46877 0 0 926341. 3205.33 0.03 0.07 0.09 -1 -1 0.03 0.0247133 0.0222095 102 62 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.89 vpr 64.69 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29992 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 29 32 269 229 1 166 79 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1756 750 8867 3422 4589 856 64.7 MiB 0.04 0.00 4.44376 3.81986 -111.589 -3.81986 3.81986 0.25 0.000268678 0.000245483 0.0157691 0.0144682 -1 -1 -1 -1 32 2228 31 6.99608e+06 264882 586450. 2029.24 2.28 0.125635 0.109629 25474 144626 -1 1667 22 1606 2144 164445 35623 3.43772 3.43772 -115.848 -3.43772 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0143813 0.012807 68 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 4.92 vpr 65.08 MiB -1 -1 0.12 17916 1 0.02 -1 -1 29928 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66640 32 32 310 266 1 186 79 17 17 289 -1 unnamed_device 25.6 MiB 0.25 2114 1072 10388 2745 6664 979 65.1 MiB 0.05 0.00 4.23779 3.56989 -126.273 -3.56989 3.56989 0.25 0.000302879 0.000276572 0.0200515 0.018352 -1 -1 -1 -1 40 2251 27 6.99608e+06 220735 706193. 2443.58 3.29 0.150356 0.131318 26914 176310 -1 2129 19 1386 1859 153495 33604 3.78796 3.78796 -134.796 -3.78796 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0256499 0.0230263 78 58 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_106.v common 3.40 vpr 64.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30268 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65664 31 32 326 261 1 197 83 17 17 289 -1 unnamed_device 25.2 MiB 0.22 2462 1162 13763 5234 6995 1534 64.1 MiB 0.07 0.00 5.08188 4.09932 -130.497 -4.09932 4.09932 0.24 0.000314789 0.000287897 0.02625 0.0240865 -1 -1 -1 -1 46 2358 22 6.99608e+06 294314 828058. 2865.25 1.74 0.147828 0.129695 28066 200906 -1 2124 17 1370 2011 124268 27371 3.74866 3.74866 -129.695 -3.74866 0 0 1.01997e+06 3529.29 0.04 0.04 0.11 -1 -1 0.04 0.0146133 0.0132243 82 33 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_107.v common 4.76 vpr 64.61 MiB -1 -1 0.12 17676 1 0.02 -1 -1 30212 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 29 32 262 224 1 162 78 17 17 289 -1 unnamed_device 24.9 MiB 0.25 1704 837 10204 3081 5451 1672 64.6 MiB 0.05 0.00 4.00332 3.52002 -104.505 -3.52002 3.52002 0.24 0.000266925 0.000244771 0.0181439 0.016651 -1 -1 -1 -1 34 2235 27 6.99608e+06 250167 618332. 2139.56 3.12 0.149414 0.130029 25762 151098 -1 1839 33 1724 2185 236919 81430 3.10977 3.10977 -108.554 -3.10977 0 0 787024. 2723.27 0.03 0.10 0.08 -1 -1 0.03 0.029701 0.0266071 67 31 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 5.46 vpr 63.99 MiB -1 -1 0.13 17676 1 0.02 -1 -1 30164 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 278 238 1 178 79 17 17 289 -1 unnamed_device 24.9 MiB 0.27 2344 802 11233 4665 6317 251 64.0 MiB 0.05 0.00 4.87466 3.81986 -117.727 -3.81986 3.81986 0.25 0.000293201 0.000268469 0.0227949 0.020989 -1 -1 -1 -1 36 2662 38 6.99608e+06 220735 648988. 2245.63 3.82 0.16388 0.143411 26050 158493 -1 1945 22 1737 2335 205163 46980 3.35647 3.35647 -125.635 -3.35647 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0146639 0.0130972 70 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 3.50 vpr 64.76 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 373 300 1 230 85 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2524 1290 13291 4296 7426 1569 64.8 MiB 0.07 0.00 5.14528 3.96644 -137.42 -3.96644 3.96644 0.25 0.000387044 0.000354926 0.0287595 0.0262542 -1 -1 -1 -1 44 2878 34 6.99608e+06 323745 787024. 2723.27 1.73 0.151986 0.133028 27778 195446 -1 2429 20 1825 2644 204826 43184 3.64925 3.64925 -135.828 -3.64925 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0179987 0.0161854 100 64 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_110.v common 2.92 vpr 64.68 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29828 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 31 32 265 230 1 170 78 17 17 289 -1 unnamed_device 25.2 MiB 0.22 1901 926 8378 2454 4499 1425 64.7 MiB 0.05 0.00 3.62338 3.26538 -103.352 -3.26538 3.26538 0.26 0.000272319 0.000249627 0.0194942 0.0180456 -1 -1 -1 -1 38 2049 20 6.99608e+06 220735 678818. 2348.85 1.28 0.102417 0.0892263 26626 170182 -1 1809 21 1209 1714 135631 28455 2.80117 2.80117 -107.376 -2.80117 0 0 902133. 3121.57 0.03 0.04 0.17 -1 -1 0.03 0.0141216 0.0125816 67 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_111.v common 2.51 vpr 65.15 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29804 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 32 32 349 286 1 207 82 17 17 289 -1 unnamed_device 25.6 MiB 0.27 2683 1135 10584 3164 6747 673 65.1 MiB 0.06 0.00 4.36937 3.54449 -120.669 -3.54449 3.54449 0.25 0.000338843 0.000311513 0.0217633 0.0199616 -1 -1 -1 -1 38 2762 21 6.99608e+06 264882 678818. 2348.85 0.89 0.0998171 0.0884553 26626 170182 -1 2311 19 1299 1882 133571 29409 3.16766 3.16766 -121.59 -3.16766 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0163812 0.0147286 89 57 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_112.v common 3.05 vpr 65.50 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29576 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67072 31 32 396 325 1 257 88 17 17 289 -1 unnamed_device 26.0 MiB 0.29 2720 1315 14128 4475 8272 1381 65.5 MiB 0.08 0.00 6.02652 4.44482 -155.897 -4.44482 4.44482 0.26 0.000742385 0.000711038 0.0330194 0.0304111 -1 -1 -1 -1 36 3582 39 6.99608e+06 367892 648988. 2245.63 1.27 0.133571 0.118438 26050 158493 -1 2929 30 2912 4166 446962 115122 4.4407 4.4407 -163.878 -4.4407 0 0 828058. 2865.25 0.03 0.10 0.08 -1 -1 0.03 0.0236603 0.0210998 111 91 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_113.v common 2.45 vpr 65.07 MiB -1 -1 0.11 18052 1 0.02 -1 -1 29604 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 303 262 1 189 80 17 17 289 -1 unnamed_device 25.0 MiB 0.32 1997 1013 12808 5361 7263 184 65.1 MiB 0.06 0.00 4.02834 3.18879 -114.113 -3.18879 3.18879 0.24 0.00029145 0.000266248 0.0237704 0.0217697 -1 -1 -1 -1 40 2271 23 6.99608e+06 235451 706193. 2443.58 0.77 0.0897322 0.0787789 26914 176310 -1 1978 19 1566 2160 160897 35900 2.92196 2.92196 -113.469 -2.92196 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0177855 0.0158654 80 57 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_114.v common 2.89 vpr 64.03 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29764 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65568 32 32 290 244 1 174 79 17 17 289 -1 unnamed_device 25.2 MiB 0.25 2070 991 12078 3761 7335 982 64.0 MiB 0.07 0.00 3.92883 3.42763 -115.198 -3.42763 3.42763 0.25 0.000352015 0.00032687 0.0293293 0.0270993 -1 -1 -1 -1 44 2260 49 6.99608e+06 220735 787024. 2723.27 1.27 0.11646 0.102895 27778 195446 -1 1939 20 1462 2114 176026 37248 3.13262 3.13262 -118.27 -3.13262 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0141357 0.0126608 70 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_115.v common 3.03 vpr 64.48 MiB -1 -1 0.14 17976 1 0.03 -1 -1 29776 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 318 257 1 190 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2008 1061 12156 3939 6984 1233 64.5 MiB 0.06 0.00 4.55868 4.12158 -127.831 -4.12158 4.12158 0.34 0.000319482 0.00029223 0.0286941 0.0265897 -1 -1 -1 -1 36 2636 26 6.99608e+06 250167 648988. 2245.63 1.09 0.120052 0.106785 26050 158493 -1 2264 21 1654 2305 182456 39548 3.99926 3.99926 -138.156 -3.99926 0 0 828058. 2865.25 0.05 0.08 0.14 -1 -1 0.05 0.0252004 0.0226623 79 30 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_116.v common 3.84 vpr 64.70 MiB -1 -1 0.21 18060 1 0.04 -1 -1 30232 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 29 32 324 268 1 193 80 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2038 850 7992 3080 4019 893 64.7 MiB 0.04 0.00 4.14059 3.42459 -102.439 -3.42459 3.42459 0.24 0.000309691 0.000283343 0.0167648 0.0154227 -1 -1 -1 -1 38 2478 27 6.99608e+06 279598 678818. 2348.85 1.97 0.15036 0.131366 26626 170182 -1 1937 19 1363 2005 132397 30881 3.27106 3.27106 -107.497 -3.27106 0 0 902133. 3121.57 0.03 0.04 0.15 -1 -1 0.03 0.0152913 0.0137551 85 55 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_117.v common 4.11 vpr 65.06 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29792 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66624 32 32 393 312 1 234 83 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2763 1341 14303 4864 7770 1669 65.1 MiB 0.08 0.00 6.04713 5.29533 -174.708 -5.29533 5.29533 0.25 0.000363933 0.000332944 0.0312788 0.0287185 -1 -1 -1 -1 48 3515 28 6.99608e+06 279598 865456. 2994.66 2.34 0.196802 0.172935 28354 207349 -1 2907 22 1926 2921 248278 49536 4.46704 4.46704 -168.361 -4.46704 0 0 1.05005e+06 3633.38 0.04 0.07 0.11 -1 -1 0.04 0.0224785 0.02012 102 65 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_118.v common 3.22 vpr 64.43 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29936 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 31 32 229 197 1 138 78 17 17 289 -1 unnamed_device 24.9 MiB 0.38 1665 866 10038 3879 5332 827 64.4 MiB 0.04 0.00 3.45398 3.07808 -95.6005 -3.07808 3.07808 0.25 0.00025341 0.000231039 0.0176736 0.0161604 -1 -1 -1 -1 34 1957 19 6.99608e+06 220735 618332. 2139.56 1.45 0.11107 0.0962653 25762 151098 -1 1727 19 948 1543 115724 25796 2.76232 2.76232 -99.9411 -2.76232 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0119476 0.0106754 55 4 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_119.v common 3.17 vpr 65.16 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30156 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66724 32 32 412 334 1 258 87 17 17 289 -1 unnamed_device 25.6 MiB 0.30 3136 1376 11799 3682 6020 2097 65.2 MiB 0.06 0.00 6.25193 4.95808 -168.612 -4.95808 4.95808 0.35 0.000374179 0.000341467 0.0250565 0.0229553 -1 -1 -1 -1 36 3619 37 6.99608e+06 338461 648988. 2245.63 1.34 0.128163 0.113155 26050 158493 -1 2910 20 2239 2839 225407 51024 5.3834 5.3834 -185.015 -5.3834 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0193173 0.017444 114 90 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_120.v common 8.25 vpr 65.29 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30212 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66852 32 32 376 318 1 253 85 17 17 289 -1 unnamed_device 25.6 MiB 0.30 2503 1284 12919 4933 5948 2038 65.3 MiB 0.07 0.00 5.63182 4.45298 -163.199 -4.45298 4.45298 0.25 0.000344204 0.000305634 0.0255725 0.0233133 -1 -1 -1 -1 36 3534 41 6.99608e+06 309029 648988. 2245.63 6.45 0.227881 0.19988 26050 158493 -1 2786 22 2693 3443 310767 66326 4.37485 4.37485 -164.891 -4.37485 0 0 828058. 2865.25 0.03 0.07 0.17 -1 -1 0.03 0.0187806 0.0168388 105 96 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_121.v common 3.52 vpr 65.28 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 360 293 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.25 2367 1051 11247 3952 5722 1573 65.3 MiB 0.05 0.00 4.26889 3.47593 -117.199 -3.47593 3.47593 0.26 0.000336143 0.000306239 0.022991 0.021056 -1 -1 -1 -1 44 2721 42 6.99608e+06 294314 787024. 2723.27 1.71 0.152173 0.133648 27778 195446 -1 1977 21 1581 2145 160989 36030 3.25147 3.25147 -116.771 -3.25147 0 0 997811. 3452.63 0.05 0.07 0.16 -1 -1 0.05 0.0257259 0.0230873 93 60 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_122.v common 9.91 vpr 65.45 MiB -1 -1 0.13 17840 1 0.03 -1 -1 29812 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67020 32 32 396 299 1 231 85 17 17 289 -1 unnamed_device 26.0 MiB 0.30 2469 1280 14965 4476 8929 1560 65.4 MiB 0.08 0.00 6.28253 5.57594 -163.801 -5.57594 5.57594 0.25 0.000370225 0.000338122 0.0321979 0.0295165 -1 -1 -1 -1 38 3513 25 6.99608e+06 309029 678818. 2348.85 8.19 0.201075 0.176852 26626 170182 -1 2951 22 2194 3313 270278 56814 5.12565 5.12565 -169.601 -5.12565 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0204029 0.0183752 99 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_123.v common 2.18 vpr 64.52 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29792 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 30 32 224 207 1 134 75 17 17 289 -1 unnamed_device 24.9 MiB 0.24 1623 599 8449 2065 6066 318 64.5 MiB 0.04 0.00 2.83666 2.33546 -84.6639 -2.33546 2.33546 0.25 0.000555342 0.00051864 0.0194883 0.0180519 -1 -1 -1 -1 34 1695 48 6.99608e+06 191304 618332. 2139.56 0.65 0.0682305 0.0598421 25762 151098 -1 1398 20 868 1102 100646 25554 2.33678 2.33678 -94.189 -2.33678 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0115737 0.0102789 52 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_124.v common 2.81 vpr 64.67 MiB -1 -1 0.13 17676 1 0.02 -1 -1 29812 -1 -1 15 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 30 32 286 239 1 159 77 17 17 289 -1 unnamed_device 24.9 MiB 0.91 1725 902 8879 3004 4356 1519 64.7 MiB 0.04 0.00 4.10447 3.92803 -130.612 -3.92803 3.92803 0.24 0.000281139 0.000257365 0.0174054 0.0159733 -1 -1 -1 -1 34 2176 27 6.99608e+06 220735 618332. 2139.56 0.56 0.068423 0.0600819 25762 151098 -1 1899 22 1246 1955 169232 36091 3.59731 3.59731 -136.68 -3.59731 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0152632 0.0136748 70 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_125.v common 3.35 vpr 64.34 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29168 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 296 247 1 182 79 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1971 882 13261 5570 7431 260 64.3 MiB 0.09 0.00 4.19149 3.78235 -133.321 -3.78235 3.78235 0.29 0.000445199 0.000403688 0.0373451 0.0341953 -1 -1 -1 -1 38 2651 49 6.99608e+06 220735 678818. 2348.85 1.75 0.126489 0.111927 26626 170182 -1 2020 20 1450 2457 219315 48983 3.62081 3.62081 -134.809 -3.62081 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0146507 0.0131502 74 34 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_126.v common 2.16 vpr 64.50 MiB -1 -1 0.14 18056 1 0.02 -1 -1 29884 -1 -1 19 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 25 32 216 194 1 134 76 17 17 289 -1 unnamed_device 25.0 MiB 0.25 1590 696 11596 3751 6795 1050 64.5 MiB 0.04 0.00 4.10053 3.35753 -84.3952 -3.35753 3.35753 0.25 0.000220573 0.000201876 0.0175116 0.016058 -1 -1 -1 -1 36 1574 20 6.99608e+06 279598 648988. 2245.63 0.51 0.054351 0.0477519 26050 158493 -1 1398 21 929 1335 101544 22940 3.09097 3.09097 -90.8946 -3.09097 0 0 828058. 2865.25 0.04 0.04 0.08 -1 -1 0.04 0.0146461 0.0129751 57 29 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_127.v common 2.88 vpr 65.38 MiB -1 -1 0.13 17528 1 0.04 -1 -1 30176 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 376 307 1 230 83 17 17 289 -1 unnamed_device 25.6 MiB 0.45 2657 1316 7463 1720 5150 593 65.4 MiB 0.05 0.00 4.40039 3.97548 -133.176 -3.97548 3.97548 0.25 0.000350248 0.000315913 0.016928 0.0155579 -1 -1 -1 -1 38 3462 44 6.99608e+06 279598 678818. 2348.85 1.00 0.108019 0.0954574 26626 170182 -1 2797 24 2179 3377 250295 53465 4.20392 4.20392 -145.444 -4.20392 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0211822 0.0189813 99 72 -1 -1 -1 -1 +fixed_k6_frac_2uripple_N8_22nm.xml mult_128.v common 4.42 vpr 65.54 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29820 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67112 31 32 409 331 1 257 86 17 17 289 -1 unnamed_device 25.6 MiB 0.29 3057 1328 14639 4861 7943 1835 65.5 MiB 0.08 0.00 5.90204 4.55497 -151.39 -4.55497 4.55497 0.25 0.00036635 0.000334698 0.0308268 0.0282486 -1 -1 -1 -1 42 3264 47 6.99608e+06 338461 744469. 2576.02 2.69 0.236746 0.209256 27202 183097 -1 2636 21 2145 2960 233871 50459 3.92175 3.92175 -144.746 -3.92175 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0203923 0.0184184 114 90 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_001.v common 4.41 vpr 64.49 MiB -1 -1 0.19 18436 14 0.23 -1 -1 32268 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 277 309 1 196 84 17 17 289 -1 unnamed_device 24.9 MiB 0.78 3031 1205 13626 4599 7190 1837 64.5 MiB 0.16 0.00 11.4241 8.56631 -174.636 -8.56631 8.56631 0.24 0.00119097 0.00110789 0.0820653 0.0761529 -1 -1 -1 -1 40 2941 23 6.79088e+06 269440 706193. 2443.58 1.87 0.27365 0.243248 26254 175826 -1 2711 18 1428 4274 219784 51179 7.12477 7.12477 -158.977 -7.12477 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0219342 0.0199651 135 183 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_002.v common 3.93 vpr 64.29 MiB -1 -1 0.18 18440 14 0.33 -1 -1 32040 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 30 32 272 304 1 199 83 17 17 289 -1 unnamed_device 25.1 MiB 0.45 2323 1121 7283 1658 4725 900 64.3 MiB 0.06 0.00 9.21432 7.55348 -154.172 -7.55348 7.55348 0.25 0.000649361 0.00061241 0.0264904 0.0245894 -1 -1 -1 -1 38 2991 20 6.79088e+06 282912 678818. 2348.85 1.69 0.220787 0.195563 25966 169698 -1 2398 20 1400 3922 178800 44179 6.62003 6.62003 -146.847 -6.62003 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0235963 0.0214056 130 184 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_003.v common 3.30 vpr 64.28 MiB -1 -1 0.15 18052 11 0.20 -1 -1 32452 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 32 32 280 312 1 194 83 17 17 289 -1 unnamed_device 24.9 MiB 0.67 2611 1308 5483 1021 4219 243 64.3 MiB 0.05 0.00 9.0712 6.64585 -143.643 -6.64585 6.64585 0.27 0.000440044 0.000403629 0.0264756 0.0247267 -1 -1 -1 -1 32 4014 47 6.79088e+06 255968 586450. 2029.24 0.98 0.126559 0.113318 24814 144142 -1 2998 23 1611 5320 356143 96112 6.11518 6.11518 -146.285 -6.11518 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0310327 0.0279645 132 186 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_004.v common 5.13 vpr 64.30 MiB -1 -1 0.16 18284 12 0.37 -1 -1 32692 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 29 32 275 307 1 194 86 17 17 289 -1 unnamed_device 25.2 MiB 0.49 2342 1180 5189 1017 3857 315 64.3 MiB 0.04 0.00 9.35225 7.37182 -142.972 -7.37182 7.37182 0.26 0.00044831 0.00041197 0.0190445 0.0176998 -1 -1 -1 -1 32 3270 50 6.79088e+06 336800 586450. 2029.24 2.83 0.273476 0.241544 24814 144142 -1 2476 22 1379 3781 200348 47482 6.53383 6.53383 -138.939 -6.53383 0 0 744469. 2576.02 0.03 0.07 0.09 -1 -1 0.03 0.0330859 0.0298846 141 190 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_005.v common 6.99 vpr 63.98 MiB -1 -1 0.18 18436 13 0.24 -1 -1 32424 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65512 32 32 302 334 1 227 87 17 17 289 -1 unnamed_device 25.2 MiB 0.34 2826 1422 5847 1175 4382 290 64.0 MiB 0.05 0.00 10.4933 7.73127 -164.781 -7.73127 7.73127 0.24 0.000482411 0.000442208 0.0217472 0.0201042 -1 -1 -1 -1 36 3783 23 6.79088e+06 309856 648988. 2245.63 5.01 0.257872 0.227573 25390 158009 -1 3208 19 1670 4461 243005 57993 6.89412 6.89412 -162.383 -6.89412 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0245951 0.0223687 155 208 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_006.v common 3.67 vpr 64.34 MiB -1 -1 0.19 18436 13 0.23 -1 -1 32428 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 292 324 1 217 86 17 17 289 -1 unnamed_device 25.2 MiB 0.66 3136 1331 12560 3423 7370 1767 64.3 MiB 0.07 0.00 9.76013 7.28237 -154.711 -7.28237 7.28237 0.24 0.00046408 0.000424198 0.0337388 0.0309128 -1 -1 -1 -1 32 4210 42 6.79088e+06 296384 586450. 2029.24 1.27 0.132124 0.118043 24814 144142 -1 3323 21 1903 5560 319427 73380 6.75647 6.75647 -158.319 -6.75647 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0269225 0.024456 141 198 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_007.v common 2.75 vpr 64.39 MiB -1 -1 0.15 18052 12 0.17 -1 -1 32268 -1 -1 25 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 27 32 229 261 1 165 84 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1861 902 5757 1286 4119 352 64.4 MiB 0.03 0.00 8.53024 6.95672 -126.14 -6.95672 6.95672 0.25 0.000354372 0.000324783 0.013746 0.0126635 -1 -1 -1 -1 28 2519 27 6.79088e+06 336800 531479. 1839.03 1.09 0.120253 0.106175 23950 126010 -1 2066 18 1046 2497 128398 31899 5.82898 5.82898 -118.677 -5.82898 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0178246 0.0161843 109 150 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_008.v common 6.07 vpr 63.68 MiB -1 -1 0.16 17908 12 0.17 -1 -1 32412 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65212 31 32 229 261 1 181 82 17 17 289 -1 unnamed_device 24.1 MiB 0.28 2040 1181 5956 1284 4146 526 63.7 MiB 0.04 0.00 6.73834 6.21924 -138.39 -6.21924 6.21924 0.24 0.000362618 0.00032571 0.0141613 0.0129176 -1 -1 -1 -1 30 3719 48 6.79088e+06 255968 556674. 1926.21 4.29 0.201748 0.178617 24526 138013 -1 2630 18 1198 3419 188591 45425 5.43491 5.43491 -136.039 -5.43491 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0184844 0.0167371 110 138 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_009.v common 3.21 vpr 64.70 MiB -1 -1 0.15 17668 12 0.19 -1 -1 32372 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 31 32 235 267 1 189 83 17 17 289 -1 unnamed_device 24.9 MiB 0.25 2543 1227 8543 2270 5212 1061 64.7 MiB 0.05 0.00 8.6557 7.27148 -152.778 -7.27148 7.27148 0.24 0.000361802 0.000331237 0.0195722 0.0179241 -1 -1 -1 -1 40 2618 15 6.79088e+06 269440 706193. 2443.58 1.38 0.119766 0.105239 26254 175826 -1 2483 16 1033 2770 145853 34562 6.49468 6.49468 -148.795 -6.49468 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.0170104 0.0154989 110 144 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_010.v common 2.55 vpr 64.77 MiB -1 -1 0.15 17668 13 0.17 -1 -1 32296 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 250 282 1 179 81 17 17 289 -1 unnamed_device 24.9 MiB 0.40 2565 1165 6206 1220 4462 524 64.8 MiB 0.04 0.00 10.5547 7.36881 -166.317 -7.36881 7.36881 0.24 0.000391536 0.000359231 0.016511 0.0152106 -1 -1 -1 -1 28 3160 27 6.79088e+06 229024 531479. 1839.03 0.64 0.0799198 0.0709347 23950 126010 -1 2659 17 1153 2882 165722 40410 6.36594 6.36594 -163.044 -6.36594 0 0 648988. 2245.63 0.03 0.06 0.07 -1 -1 0.03 0.0254959 0.022977 110 156 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_011.v common 3.94 vpr 64.14 MiB -1 -1 0.15 18060 12 0.16 -1 -1 32264 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 216 248 1 163 81 17 17 289 -1 unnamed_device 24.5 MiB 0.58 2068 857 10756 4429 6016 311 64.1 MiB 0.05 0.00 8.56921 6.97458 -139.004 -6.97458 6.97458 0.24 0.000343467 0.000307099 0.0234334 0.0214136 -1 -1 -1 -1 38 2181 21 6.79088e+06 255968 678818. 2348.85 1.84 0.135883 0.119614 25966 169698 -1 1757 15 890 2413 117726 29155 5.82898 5.82898 -125.97 -5.82898 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0154421 0.0141457 101 128 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_012.v common 3.54 vpr 64.31 MiB -1 -1 0.26 18056 12 0.13 -1 -1 32112 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 236 268 1 168 82 17 17 289 -1 unnamed_device 24.5 MiB 0.35 2572 1214 8982 2331 5744 907 64.3 MiB 0.05 0.00 8.22306 6.49083 -156.629 -6.49083 6.49083 0.24 0.000363246 0.000331103 0.0206227 0.0189085 -1 -1 -1 -1 36 2644 29 6.79088e+06 242496 648988. 2245.63 1.41 0.132842 0.116763 25390 158009 -1 2417 16 966 2757 155170 36040 6.09296 6.09296 -155.583 -6.09296 0 0 828058. 2865.25 0.05 0.07 0.15 -1 -1 0.05 0.0296218 0.0271121 104 142 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_013.v common 4.32 vpr 64.31 MiB -1 -1 0.17 18440 13 0.25 -1 -1 32384 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 283 315 1 215 84 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2835 1334 6489 1499 4360 630 64.3 MiB 0.04 0.00 11.6534 8.17439 -174.342 -8.17439 8.17439 0.25 0.000438675 0.000401184 0.0187568 0.0172093 -1 -1 -1 -1 32 3619 35 6.79088e+06 269440 586450. 2029.24 2.19 0.200192 0.177548 24814 144142 -1 3033 18 1340 3636 199882 46955 7.21431 7.21431 -168.629 -7.21431 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0230824 0.0210502 133 189 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_014.v common 5.12 vpr 65.04 MiB -1 -1 0.18 18440 14 0.28 -1 -1 32424 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 32 32 303 335 1 227 86 17 17 289 -1 unnamed_device 25.2 MiB 0.69 3489 1455 10292 2847 6856 589 65.0 MiB 0.07 0.00 11.4534 8.74059 -185.972 -8.74059 8.74059 0.25 0.000488456 0.000447227 0.0303164 0.0277935 -1 -1 -1 -1 40 3374 27 6.79088e+06 296384 706193. 2443.58 2.50 0.277905 0.246685 26254 175826 -1 3075 32 1530 4441 421130 190943 7.41807 7.41807 -171.541 -7.41807 0 0 926341. 3205.33 0.03 0.17 0.10 -1 -1 0.03 0.0436618 0.0390518 156 209 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_015.v common 3.18 vpr 64.39 MiB -1 -1 0.25 18056 11 0.15 -1 -1 32288 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 29 32 225 257 1 169 84 17 17 289 -1 unnamed_device 24.7 MiB 0.34 2298 1064 6855 1570 4646 639 64.4 MiB 0.04 0.00 8.40469 6.70263 -132.295 -6.70263 6.70263 0.25 0.000348348 0.000318449 0.0154087 0.0141195 -1 -1 -1 -1 30 2425 21 6.79088e+06 309856 556674. 1926.21 1.15 0.119115 0.105149 24526 138013 -1 2231 17 985 2602 130423 31578 5.86469 5.86469 -127.664 -5.86469 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0175344 0.0160361 108 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_016.v common 5.96 vpr 65.10 MiB -1 -1 0.19 18436 12 0.24 -1 -1 32692 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 32 32 301 333 1 219 91 17 17 289 -1 unnamed_device 25.2 MiB 0.74 2958 1459 10087 2738 6560 789 65.1 MiB 0.06 0.00 9.40585 7.27585 -159.598 -7.27585 7.27585 0.24 0.000475027 0.000434934 0.0268074 0.0244932 -1 -1 -1 -1 32 4260 32 6.79088e+06 363744 586450. 2029.24 3.49 0.246475 0.218856 24814 144142 -1 3465 23 1720 5638 455130 145122 6.73753 6.73753 -163.315 -6.73753 0 0 744469. 2576.02 0.03 0.12 0.08 -1 -1 0.03 0.0287396 0.026003 152 207 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_017.v common 3.79 vpr 64.29 MiB -1 -1 0.17 18440 14 0.22 -1 -1 32384 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 277 309 1 212 86 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2850 1312 6890 1429 5359 102 64.3 MiB 0.05 0.00 10.5304 7.97872 -168.371 -7.97872 7.97872 0.25 0.000606839 0.000536353 0.0197275 0.018177 -1 -1 -1 -1 36 3500 42 6.79088e+06 296384 648988. 2245.63 1.53 0.148978 0.131812 25390 158009 -1 2790 18 1406 4143 221995 51462 7.21088 7.21088 -159.551 -7.21088 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0218356 0.0197917 131 183 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_018.v common 3.27 vpr 64.32 MiB -1 -1 0.15 18052 12 0.14 -1 -1 31972 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 227 259 1 171 82 17 17 289 -1 unnamed_device 24.5 MiB 0.54 2494 1086 7736 1808 5543 385 64.3 MiB 0.04 0.00 8.77612 6.78318 -155.712 -6.78318 6.78318 0.25 0.000354223 0.000323322 0.018174 0.0166131 -1 -1 -1 -1 30 2715 18 6.79088e+06 242496 556674. 1926.21 1.25 0.12632 0.111156 24526 138013 -1 2226 14 889 2523 130718 31522 5.88818 5.88818 -146.658 -5.88818 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0162673 0.0148851 108 133 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_019.v common 2.55 vpr 64.02 MiB -1 -1 0.14 17908 10 0.10 -1 -1 32064 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65556 30 32 175 207 1 131 75 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1668 806 10503 2849 6815 839 64.0 MiB 0.05 0.00 6.26916 4.98721 -124.709 -4.98721 4.98721 0.26 0.000478461 0.000454715 0.023872 0.02204 -1 -1 -1 -1 32 1826 25 6.79088e+06 175136 586450. 2029.24 0.94 0.0901868 0.0792017 24814 144142 -1 1616 13 591 1361 77271 18739 4.34281 4.34281 -119.196 -4.34281 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0113524 0.0103305 65 87 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_020.v common 3.03 vpr 63.89 MiB -1 -1 0.16 18052 13 0.16 -1 -1 32244 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65428 31 32 231 263 1 178 83 17 17 289 -1 unnamed_device 24.5 MiB 0.50 2365 1084 11783 3551 6465 1767 63.9 MiB 0.06 0.00 8.87866 7.49722 -158.804 -7.49722 7.49722 0.25 0.000362742 0.000331666 0.0270047 0.0247456 -1 -1 -1 -1 28 3316 28 6.79088e+06 269440 531479. 1839.03 0.98 0.0892173 0.0800554 23950 126010 -1 2618 16 1153 2704 167677 39802 6.33372 6.33372 -153.752 -6.33372 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0199065 0.0183664 109 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_021.v common 3.60 vpr 64.00 MiB -1 -1 0.21 18440 13 0.32 -1 -1 33084 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65536 32 32 304 336 1 215 87 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2586 1376 10839 2728 7031 1080 64.0 MiB 0.09 0.00 8.96492 7.91997 -166.691 -7.91997 7.91997 0.25 0.000464279 0.000424653 0.0425461 0.0392674 -1 -1 -1 -1 34 3753 44 6.79088e+06 309856 618332. 2139.56 1.41 0.199259 0.177438 25102 150614 -1 3173 21 1808 5062 277517 63992 7.25767 7.25767 -167.443 -7.25767 0 0 787024. 2723.27 0.03 0.08 0.08 -1 -1 0.03 0.029666 0.0271387 145 210 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_022.v common 5.06 vpr 64.92 MiB -1 -1 0.24 18440 13 0.26 -1 -1 32316 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 32 32 288 320 1 216 86 17 17 289 -1 unnamed_device 25.0 MiB 0.54 3098 1371 8969 2158 5992 819 64.9 MiB 0.06 0.00 10.2409 8.00961 -172.114 -8.00961 8.00961 0.25 0.000455242 0.000416838 0.0273004 0.025115 -1 -1 -1 -1 48 3044 22 6.79088e+06 296384 865456. 2994.66 2.49 0.280748 0.25145 27694 206865 -1 2693 35 1210 3789 333870 151059 6.84611 6.84611 -157.334 -6.84611 0 0 1.05005e+06 3633.38 0.05 0.14 0.20 -1 -1 0.05 0.0416726 0.0377162 144 194 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_023.v common 2.67 vpr 63.91 MiB -1 -1 0.15 17672 9 0.07 -1 -1 32016 -1 -1 19 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65448 26 32 152 184 1 121 77 17 17 289 -1 unnamed_device 24.5 MiB 0.19 1488 617 5782 1436 3916 430 63.9 MiB 0.03 0.00 6.09263 4.97145 -92.9358 -4.97145 4.97145 0.24 0.000244262 0.000223535 0.0101216 0.00930478 -1 -1 -1 -1 26 1806 27 6.79088e+06 255968 503264. 1741.40 1.15 0.100936 0.0879412 23662 119890 -1 1410 16 621 1418 72154 18823 4.40201 4.40201 -92.9496 -4.40201 0 0 618332. 2139.56 0.02 0.03 0.06 -1 -1 0.02 0.01089 0.00983063 70 76 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_024.v common 10.31 vpr 64.41 MiB -1 -1 0.16 18052 13 0.31 -1 -1 32380 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 287 319 1 211 88 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2866 1367 5353 1032 4119 202 64.4 MiB 0.04 0.00 10.0962 7.88173 -161.78 -7.88173 7.88173 0.25 0.000449381 0.000411785 0.015309 0.0141099 -1 -1 -1 -1 38 3405 34 6.79088e+06 323328 678818. 2348.85 8.08 0.267815 0.236873 25966 169698 -1 2807 21 1639 4697 237671 55346 7.00707 7.00707 -156.558 -7.00707 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0252728 0.0228831 137 193 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_025.v common 3.06 vpr 63.40 MiB -1 -1 0.11 17668 8 0.07 -1 -1 32008 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64924 32 32 154 186 1 122 81 17 17 289 -1 unnamed_device 24.1 MiB 0.21 1801 751 10056 3801 5079 1176 63.4 MiB 0.04 0.00 5.37538 4.0417 -97.2106 -4.0417 4.0417 0.25 0.000246317 0.000224443 0.0162963 0.0149155 -1 -1 -1 -1 28 2037 20 6.79088e+06 229024 531479. 1839.03 1.53 0.0849702 0.074266 23950 126010 -1 1607 16 643 1316 83382 21230 3.71266 3.71266 -99.3645 -3.71266 0 0 648988. 2245.63 0.02 0.03 0.07 -1 -1 0.02 0.0106624 0.00961875 64 60 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_026.v common 5.45 vpr 64.21 MiB -1 -1 0.30 18056 15 0.21 -1 -1 32388 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65752 32 32 254 286 1 199 85 17 17 289 -1 unnamed_device 24.9 MiB 0.57 2483 1240 9943 2138 6866 939 64.2 MiB 0.06 0.00 9.80857 8.30542 -172.111 -8.30542 8.30542 0.24 0.000413589 0.000379237 0.0245435 0.0225401 -1 -1 -1 -1 30 3906 37 6.79088e+06 282912 556674. 1926.21 3.13 0.211236 0.18686 24526 138013 -1 2898 17 1285 3527 205171 47925 7.42577 7.42577 -170.534 -7.42577 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0194069 0.0176652 125 160 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_027.v common 5.76 vpr 64.77 MiB -1 -1 0.24 18436 13 0.26 -1 -1 32408 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 260 292 1 195 85 17 17 289 -1 unnamed_device 24.9 MiB 0.59 2809 1235 6223 1362 4311 550 64.8 MiB 0.04 0.00 9.72987 7.14037 -153.834 -7.14037 7.14037 0.25 0.000409309 0.00037536 0.0166027 0.015261 -1 -1 -1 -1 28 3847 37 6.79088e+06 282912 531479. 1839.03 3.35 0.189471 0.167684 23950 126010 -1 3140 18 1510 4391 259846 62056 6.54163 6.54163 -159.303 -6.54163 0 0 648988. 2245.63 0.02 0.07 0.10 -1 -1 0.02 0.0221816 0.0201556 121 166 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_028.v common 3.24 vpr 64.31 MiB -1 -1 0.16 18440 13 0.24 -1 -1 32460 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 279 311 1 197 86 17 17 289 -1 unnamed_device 25.3 MiB 0.42 3092 1312 10670 2502 6881 1287 64.3 MiB 0.06 0.00 10.7137 7.55772 -167.165 -7.55772 7.55772 0.25 0.000496424 0.000437606 0.0278823 0.0255608 -1 -1 -1 -1 34 3511 26 6.79088e+06 296384 618332. 2139.56 1.12 0.149524 0.132934 25102 150614 -1 3012 26 1394 4168 319805 117147 6.53742 6.53742 -161.936 -6.53742 0 0 787024. 2723.27 0.03 0.11 0.08 -1 -1 0.03 0.0306397 0.0275996 137 185 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_029.v common 4.78 vpr 64.34 MiB -1 -1 0.21 18048 12 0.14 -1 -1 32216 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65884 32 32 238 270 1 179 83 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2215 1077 7463 1926 5127 410 64.3 MiB 0.04 0.00 8.90447 7.16817 -157.085 -7.16817 7.16817 0.24 0.000360981 0.000329659 0.0183015 0.016781 -1 -1 -1 -1 30 2953 38 6.79088e+06 255968 556674. 1926.21 2.72 0.213179 0.189075 24526 138013 -1 2363 15 977 2427 125582 30236 6.04043 6.04043 -146.514 -6.04043 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0233315 0.0211966 106 144 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_030.v common 2.66 vpr 63.57 MiB -1 -1 0.15 18056 11 0.13 -1 -1 32052 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65092 30 32 213 245 1 164 83 17 17 289 -1 unnamed_device 24.2 MiB 0.54 2157 906 8903 2145 5507 1251 63.6 MiB 0.05 0.00 8.36704 6.05468 -133.402 -6.05468 6.05468 0.26 0.000335989 0.00030755 0.0246192 0.02286 -1 -1 -1 -1 30 2680 33 6.79088e+06 282912 556674. 1926.21 0.66 0.0826156 0.0734008 24526 138013 -1 2099 20 1066 2662 146556 35824 5.18426 5.18426 -128.437 -5.18426 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0169118 0.0152834 98 125 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_031.v common 2.87 vpr 64.38 MiB -1 -1 0.15 18056 11 0.15 -1 -1 32252 -1 -1 22 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 28 32 227 259 1 169 82 17 17 289 -1 unnamed_device 24.9 MiB 0.19 2381 1026 10050 2724 5924 1402 64.4 MiB 0.05 0.00 8.60731 6.75879 -129.565 -6.75879 6.75879 0.24 0.000355493 0.000325819 0.0222164 0.0203714 -1 -1 -1 -1 32 2423 27 6.79088e+06 296384 586450. 2029.24 1.21 0.137782 0.121045 24814 144142 -1 2131 17 976 2549 133309 32630 5.82893 5.82893 -125.134 -5.82893 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0170262 0.0153374 110 145 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_032.v common 3.22 vpr 64.91 MiB -1 -1 0.14 18052 12 0.23 -1 -1 32352 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 274 306 1 205 88 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2875 1212 13153 3436 7680 2037 64.9 MiB 0.07 0.00 9.54873 6.775 -163.89 -6.775 6.775 0.25 0.000426219 0.000390708 0.0317792 0.0291933 -1 -1 -1 -1 38 3105 28 6.79088e+06 323328 678818. 2348.85 1.00 0.14567 0.129269 25966 169698 -1 2513 19 1288 3419 170230 41113 6.11529 6.11529 -157.306 -6.11529 0 0 902133. 3121.57 0.03 0.05 0.13 -1 -1 0.03 0.0220122 0.0199881 127 180 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_033.v common 2.77 vpr 64.30 MiB -1 -1 0.17 18056 12 0.14 -1 -1 32240 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 31 32 237 269 1 170 84 17 17 289 -1 unnamed_device 24.9 MiB 0.57 2060 1002 6672 1433 5012 227 64.3 MiB 0.04 0.00 7.92332 6.92092 -140.498 -6.92092 6.92092 0.24 0.000365858 0.000335237 0.0155583 0.0142796 -1 -1 -1 -1 34 2714 22 6.79088e+06 282912 618332. 2139.56 0.66 0.0804347 0.070896 25102 150614 -1 2212 17 1038 2779 151082 36854 5.83236 5.83236 -136.839 -5.83236 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0169749 0.0153974 103 146 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_034.v common 4.42 vpr 64.34 MiB -1 -1 0.15 18056 10 0.18 -1 -1 32228 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 29 32 220 252 1 166 80 17 17 289 -1 unnamed_device 24.5 MiB 0.38 2498 1114 12464 4239 6338 1887 64.3 MiB 0.08 0.00 8.45663 5.89864 -127.83 -5.89864 5.89864 0.27 0.000350178 0.000319832 0.0386761 0.0358483 -1 -1 -1 -1 30 2868 39 6.79088e+06 255968 556674. 1926.21 2.44 0.157288 0.139573 24526 138013 -1 2191 15 1009 2745 133799 31948 5.07353 5.07353 -121.877 -5.07353 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0187168 0.0170958 106 135 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_035.v common 4.31 vpr 65.09 MiB -1 -1 0.17 18824 13 0.37 -1 -1 32496 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 315 347 1 231 87 17 17 289 -1 unnamed_device 25.6 MiB 0.82 3406 1501 8151 1916 5443 792 65.1 MiB 0.06 0.00 10.5847 8.3634 -174.549 -8.3634 8.3634 0.25 0.000512226 0.000469738 0.0256547 0.0235679 -1 -1 -1 -1 34 4177 45 6.79088e+06 309856 618332. 2139.56 1.60 0.155047 0.138288 25102 150614 -1 3221 19 1668 4722 270668 63068 7.30036 7.30036 -169.537 -7.30036 0 0 787024. 2723.27 0.03 0.07 0.09 -1 -1 0.03 0.0268631 0.0244829 155 221 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_036.v common 6.21 vpr 64.89 MiB -1 -1 0.17 18680 14 0.29 -1 -1 32488 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66444 32 32 282 314 1 220 85 17 17 289 -1 unnamed_device 25.2 MiB 0.69 2943 1394 7711 1611 5817 283 64.9 MiB 0.05 0.00 10.4967 7.87598 -171.941 -7.87598 7.87598 0.26 0.000454747 0.000412271 0.021847 0.0200618 -1 -1 -1 -1 32 4122 48 6.79088e+06 282912 586450. 2029.24 3.80 0.264087 0.233687 24814 144142 -1 3384 26 1590 4354 315532 91570 6.90989 6.90989 -166.802 -6.90989 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0278672 0.0250781 141 188 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_037.v common 3.47 vpr 64.29 MiB -1 -1 0.27 18048 12 0.18 -1 -1 31904 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 31 32 241 273 1 167 85 17 17 289 -1 unnamed_device 24.9 MiB 0.81 2245 1124 11617 2830 7151 1636 64.3 MiB 0.06 0.00 9.13651 7.16673 -154.158 -7.16673 7.16673 0.24 0.000402222 0.000371053 0.0298095 0.027394 -1 -1 -1 -1 32 2540 25 6.79088e+06 296384 586450. 2029.24 0.75 0.104561 0.0929539 24814 144142 -1 2194 38 912 2526 247643 119222 6.40858 6.40858 -147.26 -6.40858 0 0 744469. 2576.02 0.03 0.11 0.08 -1 -1 0.03 0.0307068 0.027383 109 150 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_038.v common 4.79 vpr 64.44 MiB -1 -1 0.21 18440 12 0.24 -1 -1 32412 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 31 32 307 339 1 224 88 17 17 289 -1 unnamed_device 25.2 MiB 1.02 2945 1333 7108 1597 4418 1093 64.4 MiB 0.06 0.00 9.92626 7.46598 -153.742 -7.46598 7.46598 0.26 0.000482238 0.000434978 0.0278272 0.0257809 -1 -1 -1 -1 44 3306 50 6.79088e+06 336800 787024. 2723.27 2.00 0.23826 0.210092 27118 194962 -1 2867 17 1292 4003 228351 52035 6.84601 6.84601 -149.478 -6.84601 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0229471 0.0209391 149 216 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_039.v common 3.38 vpr 65.07 MiB -1 -1 0.21 18820 14 0.30 -1 -1 33008 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66632 31 32 293 325 1 210 87 17 17 289 -1 unnamed_device 25.2 MiB 0.62 2863 1260 7191 1526 5185 480 65.1 MiB 0.05 0.00 10.7622 8.34339 -164.83 -8.34339 8.34339 0.25 0.000461007 0.000422205 0.0206457 0.0189982 -1 -1 -1 -1 32 4175 47 6.79088e+06 323328 586450. 2029.24 0.99 0.128067 0.114334 24814 144142 -1 2958 17 1420 4068 211841 50823 7.27357 7.27357 -157.701 -7.27357 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0330715 0.026157 145 202 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_040.v common 3.88 vpr 64.86 MiB -1 -1 0.18 18824 13 0.23 -1 -1 32404 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 31 32 276 308 1 215 92 17 17 289 -1 unnamed_device 25.2 MiB 0.64 2522 1348 10856 2834 7113 909 64.9 MiB 0.06 0.00 9.47173 8.62453 -173.004 -8.62453 8.62453 0.29 0.000440966 0.000404379 0.0276626 0.025418 -1 -1 -1 -1 40 2987 28 6.79088e+06 390688 706193. 2443.58 1.54 0.191963 0.16863 26254 175826 -1 2731 15 1325 3511 178012 43029 7.1786 7.1786 -159.768 -7.1786 0 0 926341. 3205.33 0.03 0.05 0.11 -1 -1 0.03 0.0194924 0.0177471 141 185 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_041.v common 8.44 vpr 64.92 MiB -1 -1 0.18 18440 13 0.23 -1 -1 32424 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 31 32 269 301 1 202 87 17 17 289 -1 unnamed_device 25.2 MiB 0.42 2556 1153 5463 969 4379 115 64.9 MiB 0.04 0.00 9.98527 7.53333 -150.109 -7.53333 7.53333 0.24 0.000423469 0.000387405 0.0151339 0.0139092 -1 -1 -1 -1 38 3092 22 6.79088e+06 323328 678818. 2348.85 6.41 0.234781 0.206989 25966 169698 -1 2670 17 1343 3980 206829 49786 6.58427 6.58427 -142.162 -6.58427 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0206137 0.0188038 132 178 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_042.v common 3.53 vpr 64.59 MiB -1 -1 0.15 18056 12 0.16 -1 -1 32384 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 264 296 1 184 83 17 17 289 -1 unnamed_device 24.6 MiB 0.54 2002 1172 9083 2391 5419 1273 64.6 MiB 0.05 0.00 8.49442 7.30279 -160.079 -7.30279 7.30279 0.25 0.000425324 0.000390776 0.0256692 0.0237463 -1 -1 -1 -1 32 3059 44 6.79088e+06 255968 586450. 2029.24 1.35 0.163263 0.143696 24814 144142 -1 2506 18 1001 2650 149679 35783 6.24413 6.24413 -151.681 -6.24413 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0197901 0.0179497 117 170 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_043.v common 4.74 vpr 64.55 MiB -1 -1 0.35 19212 14 0.36 -1 -1 32704 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 324 356 1 233 89 17 17 289 -1 unnamed_device 25.2 MiB 0.53 2721 1387 9593 2160 6158 1275 64.6 MiB 0.06 0.00 10.2498 8.60377 -176.638 -8.60377 8.60377 0.36 0.000519234 0.000475246 0.0287265 0.0263298 -1 -1 -1 -1 42 3697 28 6.79088e+06 336800 744469. 2576.02 2.10 0.220451 0.19538 26542 182613 -1 3213 16 1508 4554 251372 60167 7.8443 7.8443 -173.087 -7.8443 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0253925 0.0232663 166 230 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_044.v common 3.17 vpr 64.68 MiB -1 -1 0.16 18052 11 0.17 -1 -1 32184 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 31 32 249 281 1 182 81 17 17 289 -1 unnamed_device 24.9 MiB 0.36 2383 1234 8831 2136 5283 1412 64.7 MiB 0.06 0.00 9.03977 6.55167 -143.832 -6.55167 6.55167 0.26 0.000390614 0.000357326 0.0306504 0.0284119 -1 -1 -1 -1 34 3424 26 6.79088e+06 242496 618332. 2139.56 1.28 0.149155 0.132617 25102 150614 -1 2799 17 1286 3775 224926 52311 5.53137 5.53137 -138.061 -5.53137 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0185385 0.0168386 116 158 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_045.v common 4.04 vpr 64.32 MiB -1 -1 0.18 18436 13 0.24 -1 -1 32404 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 31 32 284 316 1 189 83 17 17 289 -1 unnamed_device 25.2 MiB 0.59 2583 1227 7823 1987 5336 500 64.3 MiB 0.06 0.00 10.3304 8.2347 -167.362 -8.2347 8.2347 0.25 0.00107463 0.00100212 0.0242496 0.0222372 -1 -1 -1 -1 38 3089 31 6.79088e+06 269440 678818. 2348.85 1.79 0.182563 0.160756 25966 169698 -1 2457 17 1102 3538 183777 43994 6.928 6.928 -151.92 -6.928 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0229341 0.020939 137 193 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_046.v common 5.85 vpr 64.33 MiB -1 -1 0.20 18440 12 0.23 -1 -1 32476 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 303 335 1 211 88 17 17 289 -1 unnamed_device 25.2 MiB 0.72 3276 1368 7303 1652 5036 615 64.3 MiB 0.05 0.00 9.50649 7.04019 -156.99 -7.04019 7.04019 0.28 0.000485597 0.000444829 0.0239096 0.0220685 -1 -1 -1 -1 32 4045 46 6.79088e+06 323328 586450. 2029.24 3.39 0.250211 0.22096 24814 144142 -1 3137 20 1473 4574 259310 60569 6.07958 6.07958 -153.718 -6.07958 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0247197 0.0224238 149 209 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_047.v common 4.57 vpr 64.27 MiB -1 -1 0.19 18432 13 0.33 -1 -1 32428 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 32 32 272 304 1 193 84 17 17 289 -1 unnamed_device 25.2 MiB 1.10 2365 1209 7587 1894 5178 515 64.3 MiB 0.05 0.00 9.74801 7.69207 -163.114 -7.69207 7.69207 0.26 0.000440032 0.000395698 0.0215181 0.0197213 -1 -1 -1 -1 30 3206 26 6.79088e+06 269440 556674. 1926.21 1.49 0.177988 0.157193 24526 138013 -1 2685 19 1329 3576 180486 43057 6.58083 6.58083 -156.048 -6.58083 0 0 706193. 2443.58 0.03 0.06 0.07 -1 -1 0.03 0.0268247 0.0243982 129 178 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_048.v common 4.15 vpr 64.91 MiB -1 -1 0.17 18436 13 0.29 -1 -1 32272 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 271 303 1 208 84 17 17 289 -1 unnamed_device 24.9 MiB 0.36 3179 1230 9417 2549 6214 654 64.9 MiB 0.06 0.00 12.3503 7.56546 -162.927 -7.56546 7.56546 0.24 0.000419777 0.000383264 0.0245488 0.0224769 -1 -1 -1 -1 34 3342 25 6.79088e+06 269440 618332. 2139.56 1.96 0.222507 0.197685 25102 150614 -1 2749 20 1287 3531 194100 46258 6.63461 6.63461 -153.875 -6.63461 0 0 787024. 2723.27 0.03 0.06 0.09 -1 -1 0.03 0.0229001 0.0207611 126 177 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_049.v common 4.41 vpr 64.33 MiB -1 -1 0.29 18440 12 0.22 -1 -1 32072 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 288 320 1 213 85 17 17 289 -1 unnamed_device 25.2 MiB 0.73 3237 1350 6781 1616 4569 596 64.3 MiB 0.05 0.00 9.79309 7.26885 -157.003 -7.26885 7.26885 0.29 0.000453889 0.000415087 0.0228808 0.0209913 -1 -1 -1 -1 36 3641 25 6.79088e+06 282912 648988. 2245.63 1.83 0.204078 0.18037 25390 158009 -1 3026 21 1415 4844 275624 62278 6.33013 6.33013 -152.464 -6.33013 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.0264261 0.0237997 143 194 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_050.v common 3.94 vpr 65.12 MiB -1 -1 0.18 18824 13 0.26 -1 -1 33052 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 306 338 1 225 90 17 17 289 -1 unnamed_device 25.2 MiB 0.43 2993 1412 5718 1172 4154 392 65.1 MiB 0.05 0.00 9.84216 7.93745 -169.253 -7.93745 7.93745 0.26 0.000506572 0.000441632 0.0199996 0.0184984 -1 -1 -1 -1 34 3731 24 6.79088e+06 350272 618332. 2139.56 1.65 0.183595 0.164168 25102 150614 -1 3234 20 1610 4700 250750 58995 6.64794 6.64794 -157.372 -6.64794 0 0 787024. 2723.27 0.03 0.07 0.09 -1 -1 0.03 0.0260849 0.023678 154 212 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_051.v common 4.60 vpr 64.25 MiB -1 -1 0.15 18296 14 0.25 -1 -1 32688 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 262 294 1 194 83 17 17 289 -1 unnamed_device 24.9 MiB 0.48 2657 1180 4583 839 3547 197 64.2 MiB 0.03 0.00 10.6221 8.57741 -169.869 -8.57741 8.57741 0.25 0.000429716 0.000393141 0.0139303 0.012808 -1 -1 -1 -1 28 3338 31 6.79088e+06 255968 531479. 1839.03 2.48 0.181889 0.160377 23950 126010 -1 2914 20 1463 4240 240521 57665 7.62947 7.62947 -166.279 -7.62947 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.022302 0.0202324 126 168 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_052.v common 3.72 vpr 65.03 MiB -1 -1 0.28 18440 13 0.29 -1 -1 32388 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 32 32 291 323 1 211 86 17 17 289 -1 unnamed_device 25.6 MiB 0.57 2869 1258 10481 2943 5987 1551 65.0 MiB 0.07 0.00 10.9668 8.37706 -166.957 -8.37706 8.37706 0.26 0.000452579 0.00041402 0.0351629 0.0326495 -1 -1 -1 -1 32 3983 34 6.79088e+06 296384 586450. 2029.24 1.24 0.15596 0.139386 24814 144142 -1 3104 18 1493 4014 248833 58652 7.1394 7.1394 -164.599 -7.1394 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0277841 0.0252849 141 197 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_053.v common 5.22 vpr 63.88 MiB -1 -1 0.22 18436 13 0.32 -1 -1 32356 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 31 32 302 334 1 219 90 17 17 289 -1 unnamed_device 25.2 MiB 0.71 2984 1375 7929 1755 5579 595 63.9 MiB 0.05 0.00 10.6879 7.80965 -168.49 -7.80965 7.80965 0.26 0.000508235 0.000468038 0.0234246 0.0216387 -1 -1 -1 -1 44 3117 28 6.79088e+06 363744 787024. 2723.27 2.60 0.247217 0.219943 27118 194962 -1 2818 25 1372 3980 318440 129638 6.99593 6.99593 -160.634 -6.99593 0 0 997811. 3452.63 0.04 0.11 0.10 -1 -1 0.04 0.0310593 0.0280909 152 211 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_054.v common 4.83 vpr 65.00 MiB -1 -1 0.31 18824 12 0.27 -1 -1 32268 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 32 32 308 340 1 222 92 17 17 289 -1 unnamed_device 25.6 MiB 0.41 3144 1337 10649 2743 7103 803 65.0 MiB 0.07 0.00 10.1967 7.58252 -163.027 -7.58252 7.58252 0.25 0.000490837 0.000443114 0.0319269 0.0295168 -1 -1 -1 -1 40 3178 19 6.79088e+06 377216 706193. 2443.58 2.41 0.251239 0.223458 26254 175826 -1 3008 22 1701 4827 258713 61668 6.50587 6.50587 -155.351 -6.50587 0 0 926341. 3205.33 0.05 0.11 0.09 -1 -1 0.05 0.0451514 0.0407572 156 214 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_055.v common 2.48 vpr 63.77 MiB -1 -1 0.22 18052 11 0.11 -1 -1 32232 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 32 32 216 248 1 163 81 17 17 289 -1 unnamed_device 24.5 MiB 0.16 2444 1016 13381 3505 8370 1506 63.8 MiB 0.06 0.00 8.71077 6.38377 -127.37 -6.38377 6.38377 0.25 0.000324322 0.000295525 0.0272651 0.0249364 -1 -1 -1 -1 30 2471 48 6.79088e+06 229024 556674. 1926.21 0.77 0.111758 0.0991533 24526 138013 -1 2018 16 855 2033 108403 26277 5.53907 5.53907 -126.438 -5.53907 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0151176 0.0137736 96 122 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_056.v common 3.03 vpr 64.83 MiB -1 -1 0.17 18440 13 0.19 -1 -1 31976 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66384 32 32 254 286 1 192 84 17 17 289 -1 unnamed_device 25.0 MiB 0.79 2200 1130 7953 1961 5244 748 64.8 MiB 0.06 0.00 9.12952 7.64382 -162.069 -7.64382 7.64382 0.26 0.000404932 0.00037113 0.0266925 0.0246854 -1 -1 -1 -1 32 3343 36 6.79088e+06 269440 586450. 2029.24 0.62 0.103698 0.0924632 24814 144142 -1 2509 20 1303 3343 181626 44818 6.83492 6.83492 -156.203 -6.83492 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0210802 0.0190009 117 160 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_057.v common 4.16 vpr 64.23 MiB -1 -1 0.19 19208 14 0.50 -1 -1 32596 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 338 370 1 249 88 17 17 289 -1 unnamed_device 25.6 MiB 0.55 3289 1631 6133 1207 4481 445 64.2 MiB 0.05 0.00 12.1157 8.85191 -183.37 -8.85191 8.85191 0.25 0.00052977 0.00048526 0.0246398 0.0227741 -1 -1 -1 -1 36 4433 25 6.79088e+06 323328 648988. 2245.63 1.60 0.198607 0.176942 25390 158009 -1 3727 23 2320 7287 414178 93236 7.92691 7.92691 -180.612 -7.92691 0 0 828058. 2865.25 0.03 0.09 0.08 -1 -1 0.03 0.0315216 0.0285437 178 244 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_058.v common 4.45 vpr 64.82 MiB -1 -1 0.16 18436 13 0.25 -1 -1 32520 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 271 303 1 213 87 17 17 289 -1 unnamed_device 25.2 MiB 0.41 2695 1357 7767 1632 5687 448 64.8 MiB 0.05 0.00 9.55819 7.43065 -172.005 -7.43065 7.43065 0.26 0.000453633 0.000416022 0.0206436 0.0188543 -1 -1 -1 -1 44 3224 37 6.79088e+06 309856 787024. 2723.27 2.25 0.249436 0.219598 27118 194962 -1 2850 17 1234 3473 205079 46010 6.76533 6.76533 -164.687 -6.76533 0 0 997811. 3452.63 0.06 0.09 0.14 -1 -1 0.06 0.0356138 0.032349 139 177 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_059.v common 5.16 vpr 63.62 MiB -1 -1 0.15 18056 11 0.15 -1 -1 32220 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65144 30 32 224 256 1 165 81 17 17 289 -1 unnamed_device 24.5 MiB 0.28 2111 998 6031 1372 4208 451 63.6 MiB 0.04 0.00 8.95732 6.57733 -140.708 -6.57733 6.57733 0.25 0.000361391 0.000331213 0.0187657 0.0173949 -1 -1 -1 -1 30 2897 39 6.79088e+06 255968 556674. 1926.21 3.36 0.147671 0.130734 24526 138013 -1 2204 19 1182 3397 176175 42450 5.70014 5.70014 -134.673 -5.70014 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0198801 0.0179249 103 136 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_060.v common 5.46 vpr 64.95 MiB -1 -1 0.22 19208 15 0.48 -1 -1 32792 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 32 32 351 383 1 253 89 17 17 289 -1 unnamed_device 25.2 MiB 0.71 3433 1562 7613 1907 5097 609 64.9 MiB 0.10 0.00 11.6801 9.39421 -191.348 -9.39421 9.39421 0.36 0.00106071 0.000968475 0.046627 0.0426776 -1 -1 -1 -1 42 3751 25 6.79088e+06 336800 744469. 2576.02 2.52 0.366544 0.326961 26542 182613 -1 3337 18 1749 5222 274844 63949 8.01666 8.01666 -177.783 -8.01666 0 0 949917. 3286.91 0.04 0.07 0.10 -1 -1 0.04 0.0297378 0.0272194 185 257 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_061.v common 4.20 vpr 64.39 MiB -1 -1 0.17 18440 13 0.28 -1 -1 32436 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 297 329 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2331 1313 3744 580 3016 148 64.4 MiB 0.03 0.00 9.31665 8.10068 -171.378 -8.10068 8.10068 0.25 0.00048237 0.000443634 0.0128747 0.0119037 -1 -1 -1 -1 30 3374 30 6.79088e+06 269440 556674. 1926.21 1.97 0.161087 0.142735 24526 138013 -1 2738 19 1436 3802 177108 45178 7.26121 7.26121 -166.861 -7.26121 0 0 706193. 2443.58 0.03 0.05 0.13 -1 -1 0.03 0.0260456 0.0238074 143 203 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_062.v common 4.84 vpr 64.27 MiB -1 -1 0.14 18056 11 0.17 -1 -1 32236 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 231 263 1 167 82 17 17 289 -1 unnamed_device 24.9 MiB 0.44 2270 1023 7736 2019 5297 420 64.3 MiB 0.04 0.00 8.47541 6.67703 -137.267 -6.67703 6.67703 0.25 0.000362463 0.000328679 0.018534 0.0169718 -1 -1 -1 -1 32 2657 23 6.79088e+06 242496 586450. 2029.24 2.81 0.168016 0.148222 24814 144142 -1 2290 22 939 2390 174462 52299 5.65673 5.65673 -133.532 -5.65673 0 0 744469. 2576.02 0.03 0.05 0.09 -1 -1 0.03 0.0191776 0.0172547 102 137 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_063.v common 4.62 vpr 65.11 MiB -1 -1 0.29 18444 12 0.27 -1 -1 32348 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 305 337 1 213 84 17 17 289 -1 unnamed_device 25.6 MiB 0.45 2891 1443 5757 1168 4018 571 65.1 MiB 0.04 0.00 9.11861 7.63944 -167.73 -7.63944 7.63944 0.25 0.000465144 0.000424934 0.0193417 0.0177798 -1 -1 -1 -1 34 3932 44 6.79088e+06 269440 618332. 2139.56 2.35 0.227299 0.200836 25102 150614 -1 3251 21 1580 4929 276598 63194 6.67032 6.67032 -159.862 -6.67032 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0265715 0.0240576 150 211 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_064.v common 3.39 vpr 64.76 MiB -1 -1 0.14 18052 12 0.17 -1 -1 32236 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 243 275 1 185 85 17 17 289 -1 unnamed_device 24.9 MiB 0.31 2761 1193 9013 2310 6187 516 64.8 MiB 0.06 0.00 9.53525 7.06923 -152.736 -7.06923 7.06923 0.25 0.000831744 0.000771026 0.0259706 0.0239944 -1 -1 -1 -1 32 3476 32 6.79088e+06 282912 586450. 2029.24 1.53 0.163362 0.144355 24814 144142 -1 2663 17 1226 3225 178849 42340 6.24403 6.24403 -150.803 -6.24403 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0181705 0.0165401 116 149 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_065.v common 2.59 vpr 64.29 MiB -1 -1 0.15 18056 12 0.16 -1 -1 32240 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 30 32 228 260 1 164 81 17 17 289 -1 unnamed_device 24.5 MiB 0.38 2420 1052 9006 2359 5756 891 64.3 MiB 0.06 0.00 9.79978 7.51114 -149.061 -7.51114 7.51114 0.26 0.000582199 0.00055125 0.0274052 0.0252224 -1 -1 -1 -1 28 2581 46 6.79088e+06 255968 531479. 1839.03 0.62 0.10047 0.0893174 23950 126010 -1 2268 17 883 2304 127041 31144 6.50931 6.50931 -142.821 -6.50931 0 0 648988. 2245.63 0.02 0.04 0.14 -1 -1 0.02 0.0175122 0.0159131 106 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_066.v common 4.27 vpr 65.00 MiB -1 -1 0.18 18440 12 0.24 -1 -1 33000 -1 -1 27 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 29 32 275 307 1 201 88 17 17 289 -1 unnamed_device 25.2 MiB 0.86 2477 1194 11983 2982 7056 1945 65.0 MiB 0.07 0.00 9.28703 7.29287 -140.54 -7.29287 7.29287 0.25 0.000596237 0.000555455 0.0308238 0.0281961 -1 -1 -1 -1 34 3229 49 6.79088e+06 363744 618332. 2139.56 1.61 0.208 0.183725 25102 150614 -1 2663 18 1246 3691 195920 47061 6.49468 6.49468 -135.021 -6.49468 0 0 787024. 2723.27 0.04 0.08 0.12 -1 -1 0.04 0.031244 0.0281388 141 190 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_067.v common 3.17 vpr 64.52 MiB -1 -1 0.19 18436 13 0.30 -1 -1 32424 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 330 362 1 243 89 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2791 1433 6425 1352 4743 330 64.5 MiB 0.05 0.00 10.3234 8.72856 -182.327 -8.72856 8.72856 0.24 0.000795659 0.000728071 0.0232994 0.0214039 -1 -1 -1 -1 38 3464 26 6.79088e+06 336800 678818. 2348.85 1.14 0.157746 0.140616 25966 169698 -1 2843 20 1580 4086 185601 47097 7.50416 7.50416 -166.392 -7.50416 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.0309614 0.0279604 164 236 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_068.v common 4.63 vpr 63.84 MiB -1 -1 0.30 18440 12 0.30 -1 -1 32376 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65376 32 32 290 322 1 218 87 17 17 289 -1 unnamed_device 24.9 MiB 0.35 2738 1381 6039 1246 4273 520 63.8 MiB 0.04 0.00 10.6331 7.88426 -165.865 -7.88426 7.88426 0.25 0.000465683 0.000427551 0.0179957 0.016611 -1 -1 -1 -1 44 3100 19 6.79088e+06 309856 787024. 2723.27 2.38 0.252406 0.224359 27118 194962 -1 2732 20 1293 3687 194765 45364 7.04976 7.04976 -158.257 -7.04976 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0242765 0.022065 145 196 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_069.v common 3.11 vpr 64.28 MiB -1 -1 0.19 18056 12 0.13 -1 -1 32964 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 214 246 1 158 81 17 17 289 -1 unnamed_device 24.5 MiB 0.65 2402 966 11631 3699 5844 2088 64.3 MiB 0.06 0.00 10.2046 7.4716 -147.486 -7.4716 7.4716 0.31 0.000337689 0.000308377 0.0259086 0.0237764 -1 -1 -1 -1 30 2786 28 6.79088e+06 229024 556674. 1926.21 0.63 0.0863746 0.076974 24526 138013 -1 2052 27 873 2476 167777 62750 6.58427 6.58427 -143.078 -6.58427 0 0 706193. 2443.58 0.03 0.07 0.08 -1 -1 0.03 0.027424 0.0243636 94 120 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_070.v common 3.07 vpr 64.72 MiB -1 -1 0.17 18052 12 0.19 -1 -1 32040 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66276 31 32 244 276 1 178 85 17 17 289 -1 unnamed_device 25.2 MiB 0.54 2184 1042 4921 903 3842 176 64.7 MiB 0.05 0.00 8.68884 7.00394 -143.566 -7.00394 7.00394 0.35 0.000580339 0.000532143 0.0195529 0.0179552 -1 -1 -1 -1 30 3034 24 6.79088e+06 296384 556674. 1926.21 0.78 0.0893686 0.0802788 24526 138013 -1 2491 21 1275 3564 186778 44710 6.22488 6.22488 -141.943 -6.22488 0 0 706193. 2443.58 0.03 0.05 0.12 -1 -1 0.03 0.0205045 0.0184847 113 153 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_071.v common 3.99 vpr 64.89 MiB -1 -1 0.26 18436 11 0.17 -1 -1 32464 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66448 30 32 276 308 1 187 83 17 17 289 -1 unnamed_device 24.9 MiB 0.88 2327 1150 11783 3905 5750 2128 64.9 MiB 0.07 0.00 8.87527 6.95498 -139.11 -6.95498 6.95498 0.25 0.000420157 0.000383828 0.0308821 0.0282508 -1 -1 -1 -1 36 2957 25 6.79088e+06 282912 648988. 2245.63 1.42 0.17502 0.154264 25390 158009 -1 2591 18 1136 3349 191755 44399 5.75396 5.75396 -131.866 -5.75396 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0209723 0.0190357 129 188 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_072.v common 2.83 vpr 64.16 MiB -1 -1 0.15 18292 11 0.18 -1 -1 32256 -1 -1 22 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65704 28 32 253 285 1 172 82 17 17 289 -1 unnamed_device 24.9 MiB 0.41 2569 974 5778 1226 4251 301 64.2 MiB 0.05 0.00 9.47421 6.55419 -124.806 -6.55419 6.55419 0.25 0.000396379 0.000362887 0.0227797 0.0211258 -1 -1 -1 -1 30 2829 21 6.79088e+06 296384 556674. 1926.21 0.90 0.0960849 0.0857142 24526 138013 -1 2180 16 1052 3156 159340 38063 5.81774 5.81774 -121.9 -5.81774 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0180222 0.0164005 120 171 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_073.v common 4.56 vpr 64.36 MiB -1 -1 0.15 18052 13 0.24 -1 -1 32168 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 30 32 235 267 1 170 80 17 17 289 -1 unnamed_device 25.2 MiB 0.73 2387 982 10056 3040 5967 1049 64.4 MiB 0.08 0.00 9.81312 7.63272 -149.917 -7.63272 7.63272 0.26 0.000365681 0.000334243 0.0425039 0.0393652 -1 -1 -1 -1 28 3041 35 6.79088e+06 242496 531479. 1839.03 2.19 0.170005 0.151582 23950 126010 -1 2375 17 1061 2784 162889 39902 6.66693 6.66693 -147.788 -6.66693 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0189454 0.0172721 108 147 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_074.v common 3.17 vpr 64.23 MiB -1 -1 0.22 18436 12 0.17 -1 -1 31628 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 264 296 1 197 84 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2415 1100 7770 2015 4653 1102 64.2 MiB 0.05 0.00 8.61815 6.91588 -153.666 -6.91588 6.91588 0.25 0.000579984 0.000543002 0.0212815 0.0195477 -1 -1 -1 -1 34 3490 32 6.79088e+06 269440 618332. 2139.56 1.09 0.135237 0.119678 25102 150614 -1 2558 21 1284 3364 172397 44534 5.95079 5.95079 -148.444 -5.95079 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0229694 0.020794 123 170 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_075.v common 4.84 vpr 64.97 MiB -1 -1 0.23 18440 13 0.26 -1 -1 32440 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66528 31 32 278 310 1 200 88 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2897 1114 11788 3097 6456 2235 65.0 MiB 0.07 0.00 11.7353 8.38278 -163.21 -8.38278 8.38278 0.25 0.000448414 0.000410921 0.031208 0.0287226 -1 -1 -1 -1 32 3812 34 6.79088e+06 336800 586450. 2029.24 2.47 0.211753 0.186949 24814 144142 -1 2673 22 1312 3766 200576 50238 7.37881 7.37881 -158.541 -7.37881 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0245143 0.0221544 139 187 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_076.v common 4.12 vpr 65.02 MiB -1 -1 0.17 18056 14 0.23 -1 -1 32256 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 290 322 1 211 86 17 17 289 -1 unnamed_device 25.6 MiB 0.40 2838 1263 6323 1281 4818 224 65.0 MiB 0.05 0.00 9.79877 8.51252 -171.88 -8.51252 8.51252 0.30 0.000558009 0.000518729 0.0243299 0.022691 -1 -1 -1 -1 36 3441 45 6.79088e+06 296384 648988. 2245.63 1.72 0.189446 0.168875 25390 158009 -1 2883 25 1619 4804 303117 88801 7.57564 7.57564 -165.101 -7.57564 0 0 828058. 2865.25 0.03 0.09 0.08 -1 -1 0.03 0.0285655 0.0257961 142 196 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_077.v common 5.32 vpr 64.20 MiB -1 -1 0.18 18824 14 0.21 -1 -1 31756 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 269 301 1 198 83 17 17 289 -1 unnamed_device 24.9 MiB 0.76 2866 1248 7823 1994 5588 241 64.2 MiB 0.08 0.00 10.6835 8.05628 -162.217 -8.05628 8.05628 0.44 0.000778824 0.000710335 0.0372945 0.0341344 -1 -1 -1 -1 36 3198 50 6.79088e+06 255968 648988. 2245.63 2.26 0.244666 0.217046 25390 158009 -1 2775 21 1430 4356 266832 59760 7.46142 7.46142 -158.825 -7.46142 0 0 828058. 2865.25 0.05 0.11 0.14 -1 -1 0.05 0.0415661 0.0375795 124 175 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_078.v common 4.92 vpr 64.81 MiB -1 -1 0.17 18820 13 0.29 -1 -1 32464 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 296 328 1 220 88 17 17 289 -1 unnamed_device 24.9 MiB 0.79 3301 1354 9838 2791 5943 1104 64.8 MiB 0.11 0.00 11.6561 8.50014 -174.144 -8.50014 8.50014 0.44 0.000953862 0.000846986 0.050354 0.0460695 -1 -1 -1 -1 40 3071 19 6.79088e+06 323328 706193. 2443.58 1.90 0.242904 0.215911 26254 175826 -1 2921 18 1386 4092 217498 50671 7.4292 7.4292 -164.596 -7.4292 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0236931 0.0216261 148 202 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_079.v common 3.73 vpr 64.04 MiB -1 -1 0.15 18056 13 0.16 -1 -1 32240 -1 -1 20 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65572 30 32 234 266 1 174 82 17 17 289 -1 unnamed_device 24.9 MiB 0.71 2093 1110 11118 3343 5904 1871 64.0 MiB 0.07 0.00 8.34292 7.03168 -146.297 -7.03168 7.03168 0.37 0.000407522 0.000370634 0.0354939 0.0326379 -1 -1 -1 -1 32 3046 36 6.79088e+06 269440 586450. 2029.24 1.25 0.163242 0.144621 24814 144142 -1 2365 20 1188 3012 173307 40703 6.14335 6.14335 -141.075 -6.14335 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0190443 0.0172279 105 146 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_080.v common 4.29 vpr 64.45 MiB -1 -1 0.21 18824 13 0.40 -1 -1 32420 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 30 32 291 323 1 221 84 17 17 289 -1 unnamed_device 24.9 MiB 0.49 2701 1328 5940 1337 4353 250 64.5 MiB 0.08 0.00 9.92372 8.27725 -167.59 -8.27725 8.27725 0.32 0.000471761 0.000432104 0.0419352 0.0390168 -1 -1 -1 -1 40 2990 21 6.79088e+06 296384 706193. 2443.58 1.77 0.216138 0.191906 26254 175826 -1 2793 21 1499 3987 204361 48668 7.05325 7.05325 -158.984 -7.05325 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0270017 0.0245199 148 203 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_081.v common 4.21 vpr 64.30 MiB -1 -1 0.17 18444 14 0.37 -1 -1 32456 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 32 32 274 306 1 198 83 17 17 289 -1 unnamed_device 24.9 MiB 0.42 2766 1310 6203 1436 4242 525 64.3 MiB 0.06 0.00 10.68 7.90813 -170.809 -7.90813 7.90813 0.26 0.000437767 0.000400069 0.0261332 0.0241232 -1 -1 -1 -1 38 3375 23 6.79088e+06 255968 678818. 2348.85 1.97 0.190854 0.168878 25966 169698 -1 2731 20 1307 4212 215589 49236 6.96028 6.96028 -163.001 -6.96028 0 0 902133. 3121.57 0.03 0.06 0.10 -1 -1 0.03 0.0239148 0.021685 132 180 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_082.v common 6.03 vpr 63.70 MiB -1 -1 0.17 18420 13 0.21 -1 -1 32388 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65224 31 32 266 298 1 197 82 17 17 289 -1 unnamed_device 24.9 MiB 0.50 2670 1263 9516 2495 6168 853 63.7 MiB 0.08 0.00 9.28969 7.78026 -159.259 -7.78026 7.78026 0.24 0.000427306 0.000391277 0.0374739 0.0347377 -1 -1 -1 -1 40 3248 40 6.79088e+06 255968 706193. 2443.58 3.11 0.247052 0.219892 26254 175826 -1 2973 78 1765 5797 1115118 678019 6.70192 6.70192 -151.991 -6.70192 0 0 926341. 3205.33 0.05 0.62 0.18 -1 -1 0.05 0.0991482 0.088454 126 175 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_083.v common 6.00 vpr 64.51 MiB -1 -1 0.25 18048 13 0.19 -1 -1 32400 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 30 32 266 298 1 199 87 17 17 289 -1 unnamed_device 24.9 MiB 0.58 3172 1233 7767 1881 5232 654 64.5 MiB 0.05 0.00 10.3598 7.59138 -150.075 -7.59138 7.59138 0.25 0.000417312 0.000382562 0.0197533 0.0181414 -1 -1 -1 -1 30 3483 48 6.79088e+06 336800 556674. 1926.21 3.75 0.181702 0.160413 24526 138013 -1 2860 17 1326 3637 193421 45729 6.80459 6.80459 -149.735 -6.80459 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0204113 0.0184966 131 178 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_084.v common 10.01 vpr 64.36 MiB -1 -1 0.19 18680 14 0.32 -1 -1 32292 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 310 342 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2887 1381 9336 2138 6356 842 64.4 MiB 0.06 0.00 11.5139 8.70357 -178.124 -8.70357 8.70357 0.25 0.00049894 0.000457278 0.02631 0.0241948 -1 -1 -1 -1 32 4103 38 6.79088e+06 350272 586450. 2029.24 7.66 0.268987 0.239194 24814 144142 -1 3266 21 1495 4302 258673 61020 8.00547 8.00547 -175.323 -8.00547 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.026999 0.0245295 158 216 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_085.v common 4.72 vpr 64.77 MiB -1 -1 0.19 18440 11 0.25 -1 -1 32332 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 29 32 262 294 1 200 84 17 17 289 -1 unnamed_device 25.2 MiB 0.67 2793 1203 9966 2546 6206 1214 64.8 MiB 0.06 0.00 9.38772 7.1445 -141.662 -7.1445 7.1445 0.24 0.000419357 0.000383247 0.0259456 0.0238008 -1 -1 -1 -1 28 3470 28 6.79088e+06 309856 531479. 1839.03 2.12 0.187136 0.166118 23950 126010 -1 2930 22 1722 4992 281067 65184 6.54502 6.54502 -143.562 -6.54502 0 0 648988. 2245.63 0.04 0.12 0.12 -1 -1 0.04 0.0430561 0.0387822 138 177 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_086.v common 3.15 vpr 64.34 MiB -1 -1 0.15 18052 13 0.21 -1 -1 31724 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 32 32 222 254 1 179 83 17 17 289 -1 unnamed_device 24.9 MiB 0.55 2069 1200 7283 1764 4531 988 64.3 MiB 0.04 0.00 8.60203 7.14167 -162.348 -7.14167 7.14167 0.25 0.000344035 0.000314977 0.0190755 0.0175703 -1 -1 -1 -1 30 2976 21 6.79088e+06 255968 556674. 1926.21 0.84 0.0752712 0.0674518 24526 138013 -1 2322 18 1104 2731 132385 32111 6.15798 6.15798 -152.89 -6.15798 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0171264 0.0155641 100 128 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_087.v common 4.03 vpr 63.72 MiB -1 -1 0.19 18440 14 0.30 -1 -1 32404 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65252 32 32 267 299 1 192 83 17 17 289 -1 unnamed_device 24.9 MiB 0.66 2378 1170 9443 2925 4513 2005 63.7 MiB 0.06 0.00 10.4435 8.52224 -173.995 -8.52224 8.52224 0.25 0.000566754 0.000498933 0.0287922 0.0265342 -1 -1 -1 -1 34 3483 37 6.79088e+06 255968 618332. 2139.56 1.62 0.18205 0.160753 25102 150614 -1 2712 18 1256 3540 198662 47419 7.38302 7.38302 -165.88 -7.38302 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0210165 0.0191077 127 173 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_088.v common 3.79 vpr 63.94 MiB -1 -1 0.18 18824 15 0.39 -1 -1 32460 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 32 32 334 366 1 249 94 17 17 289 -1 unnamed_device 25.1 MiB 0.67 2997 1457 6271 1114 4893 264 63.9 MiB 0.05 0.00 11.8769 9.02668 -192.137 -9.02668 9.02668 0.24 0.000537557 0.000493455 0.0195073 0.0180239 -1 -1 -1 -1 36 4225 32 6.79088e+06 404160 648988. 2245.63 1.21 0.163429 0.145622 25390 158009 -1 3413 20 1762 4569 244133 58653 8.26721 8.26721 -187.065 -8.26721 0 0 828058. 2865.25 0.03 0.08 0.09 -1 -1 0.03 0.0324314 0.0294256 173 240 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_089.v common 4.34 vpr 64.31 MiB -1 -1 0.14 18052 11 0.14 -1 -1 32388 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 220 252 1 162 82 17 17 289 -1 unnamed_device 24.5 MiB 0.43 1851 1048 4710 962 3444 304 64.3 MiB 0.03 0.00 7.41857 6.65913 -141.007 -6.65913 6.65913 0.25 0.000338577 0.000308878 0.011031 0.0101382 -1 -1 -1 -1 30 2490 34 6.79088e+06 242496 556674. 1926.21 2.37 0.132925 0.116936 24526 138013 -1 2104 20 918 2474 125119 29697 5.77089 5.77089 -135.604 -5.77089 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0227745 0.020516 99 126 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_090.v common 3.59 vpr 64.79 MiB -1 -1 0.14 18056 12 0.16 -1 -1 31716 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 31 32 244 276 1 190 91 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2514 1243 8251 2100 5415 736 64.8 MiB 0.07 0.00 8.41327 6.64151 -151.522 -6.64151 6.64151 0.36 0.000384324 0.000351749 0.030995 0.0286946 -1 -1 -1 -1 36 3288 38 6.79088e+06 377216 648988. 2245.63 1.31 0.171017 0.151396 25390 158009 -1 2786 19 1310 3450 219229 55840 5.77084 5.77084 -147.31 -5.77084 0 0 828058. 2865.25 0.04 0.09 0.15 -1 -1 0.04 0.0326963 0.0295814 120 153 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_091.v common 4.25 vpr 64.96 MiB -1 -1 0.17 18440 12 0.26 -1 -1 32432 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 32 32 300 332 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.58 3008 1362 5208 1021 3853 334 65.0 MiB 0.04 0.00 9.33179 7.30279 -161.797 -7.30279 7.30279 0.24 0.000490485 0.000449616 0.0170101 0.0156458 -1 -1 -1 -1 32 4017 47 6.79088e+06 269440 586450. 2029.24 1.72 0.181491 0.159594 24814 144142 -1 3222 25 1827 5666 393170 111302 6.49473 6.49473 -154.751 -6.49473 0 0 744469. 2576.02 0.05 0.17 0.14 -1 -1 0.05 0.0525904 0.0474923 147 206 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_092.v common 4.94 vpr 64.30 MiB -1 -1 0.17 18440 12 0.21 -1 -1 32704 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 32 32 271 303 1 207 87 17 17 289 -1 unnamed_device 24.9 MiB 0.35 2518 1359 4887 914 3740 233 64.3 MiB 0.04 0.00 9.30843 7.32413 -157.509 -7.32413 7.32413 0.24 0.000422354 0.000385538 0.0141421 0.0129613 -1 -1 -1 -1 42 3546 34 6.79088e+06 309856 744469. 2576.02 2.98 0.184685 0.162721 26542 182613 -1 3075 20 1631 5150 317078 68780 6.32248 6.32248 -151.947 -6.32248 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.0225575 0.0203783 135 177 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_093.v common 4.66 vpr 65.20 MiB -1 -1 0.18 18820 14 0.41 -1 -1 32516 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66760 32 32 327 359 1 232 89 17 17 289 -1 unnamed_device 25.2 MiB 0.91 2902 1486 9197 2044 6238 915 65.2 MiB 0.07 0.00 11.0044 9.05824 -184.444 -9.05824 9.05824 0.24 0.000531234 0.000486752 0.0317284 0.0292755 -1 -1 -1 -1 36 4352 44 6.79088e+06 336800 648988. 2245.63 1.82 0.192183 0.171116 25390 158009 -1 3470 21 2095 6448 340912 77405 7.89475 7.89475 -180.096 -7.89475 0 0 828058. 2865.25 0.03 0.09 0.09 -1 -1 0.03 0.0368876 0.0334178 170 233 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_094.v common 5.07 vpr 64.79 MiB -1 -1 0.16 18052 12 0.18 -1 -1 32312 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 30 32 246 278 1 190 83 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2872 1225 9443 2668 5974 801 64.8 MiB 0.07 0.00 11.0773 8.04235 -151.9 -8.04235 8.04235 0.26 0.000906454 0.000843157 0.0312125 0.0289054 -1 -1 -1 -1 30 3247 21 6.79088e+06 282912 556674. 1926.21 3.09 0.153647 0.13626 24526 138013 -1 2617 19 1174 3385 171181 40726 7.03513 7.03513 -147.434 -7.03513 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0208927 0.0189654 123 158 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_095.v common 3.30 vpr 64.29 MiB -1 -1 0.14 17924 11 0.16 -1 -1 32200 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 27 32 219 251 1 158 80 17 17 289 -1 unnamed_device 24.5 MiB 0.66 2254 914 10228 3057 5550 1621 64.3 MiB 0.06 0.00 9.28609 7.11012 -129.104 -7.11012 7.11012 0.26 0.000834625 0.000778535 0.0290409 0.0268197 -1 -1 -1 -1 32 2363 20 6.79088e+06 282912 586450. 2029.24 1.10 0.132738 0.117693 24814 144142 -1 2014 16 860 2297 118764 28995 6.41202 6.41202 -124.201 -6.41202 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.018655 0.0167893 106 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_096.v common 12.15 vpr 64.09 MiB -1 -1 0.34 19208 13 0.38 -1 -1 32612 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65628 32 32 380 412 1 267 93 17 17 289 -1 unnamed_device 25.2 MiB 0.96 3799 1688 9333 2238 6298 797 64.1 MiB 0.07 0.00 9.85648 8.03891 -164.154 -8.03891 8.03891 0.24 0.000570832 0.000522627 0.0301749 0.0276234 -1 -1 -1 -1 36 4720 50 6.79088e+06 390688 648988. 2245.63 9.12 0.333255 0.295789 25390 158009 -1 4022 18 1939 5882 349528 81642 7.24643 7.24643 -163.259 -7.24643 0 0 828058. 2865.25 0.03 0.09 0.09 -1 -1 0.03 0.0332537 0.0305258 194 286 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_097.v common 5.05 vpr 64.26 MiB -1 -1 0.18 18440 14 0.23 -1 -1 32352 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 31 32 277 309 1 194 84 17 17 289 -1 unnamed_device 25.2 MiB 0.43 2825 1259 8502 2170 5586 746 64.3 MiB 0.05 0.00 10.5434 8.40299 -170.106 -8.40299 8.40299 0.26 0.000438649 0.000401614 0.0240127 0.0220456 -1 -1 -1 -1 28 3607 48 6.79088e+06 282912 531479. 1839.03 2.70 0.212266 0.187267 23950 126010 -1 2799 19 1355 3498 182428 44663 7.5622 7.5622 -166.161 -7.5622 0 0 648988. 2245.63 0.03 0.08 0.07 -1 -1 0.03 0.0331487 0.0300722 135 186 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_098.v common 4.33 vpr 64.66 MiB -1 -1 0.27 18044 12 0.14 -1 -1 32196 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 229 261 1 173 88 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2146 1148 7498 1703 4699 1096 64.7 MiB 0.04 0.00 9.61147 7.37908 -161.709 -7.37908 7.37908 0.25 0.000363041 0.000331373 0.0171253 0.015721 -1 -1 -1 -1 30 2639 20 6.79088e+06 323328 556674. 1926.21 2.24 0.140925 0.124252 24526 138013 -1 2241 16 933 2468 118642 29008 6.35367 6.35367 -152.496 -6.35367 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0215127 0.019597 114 135 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_099.v common 4.34 vpr 64.91 MiB -1 -1 0.18 18056 13 0.26 -1 -1 32468 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 263 295 1 189 86 17 17 289 -1 unnamed_device 24.9 MiB 0.87 2477 1198 6323 1455 4634 234 64.9 MiB 0.04 0.00 9.94771 7.95285 -163.297 -7.95285 7.95285 0.25 0.000419039 0.000383418 0.0192272 0.0177068 -1 -1 -1 -1 30 3038 31 6.79088e+06 296384 556674. 1926.21 1.80 0.189632 0.166804 24526 138013 -1 2547 17 1163 3392 164677 39638 6.92451 6.92451 -155.538 -6.92451 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0206129 0.0187785 132 169 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_100.v common 5.11 vpr 64.46 MiB -1 -1 0.18 18824 13 0.30 -1 -1 32440 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 321 353 1 243 89 17 17 289 -1 unnamed_device 25.5 MiB 0.47 2996 1555 6425 1253 4749 423 64.5 MiB 0.08 0.00 9.44492 8.03594 -170.227 -8.03594 8.03594 0.46 0.00109351 0.000985855 0.037958 0.0348172 -1 -1 -1 -1 36 4372 49 6.79088e+06 350272 648988. 2245.63 2.33 0.288027 0.256154 25390 158009 -1 3542 17 1701 4822 272035 63597 6.79572 6.79572 -158.919 -6.79572 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0243842 0.0223031 162 230 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_101.v common 4.27 vpr 64.99 MiB -1 -1 0.16 18440 11 0.22 -1 -1 32436 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 30 32 287 319 1 199 87 17 17 289 -1 unnamed_device 25.2 MiB 0.86 2711 1222 7191 1645 4976 570 65.0 MiB 0.05 0.00 9.60741 7.06412 -137.725 -7.06412 7.06412 0.24 0.000443175 0.000405281 0.0197344 0.0181089 -1 -1 -1 -1 40 2876 29 6.79088e+06 336800 706193. 2443.58 1.75 0.202725 0.178825 26254 175826 -1 2606 19 1353 4351 224230 52925 5.91852 5.91852 -128.55 -5.91852 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.022852 0.0207243 143 199 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_102.v common 4.55 vpr 64.41 MiB -1 -1 0.27 18440 15 0.33 -1 -1 32440 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 296 328 1 214 86 17 17 289 -1 unnamed_device 25.2 MiB 0.59 3096 1319 6134 1277 4632 225 64.4 MiB 0.04 0.00 11.1915 8.22013 -174.204 -8.22013 8.22013 0.24 0.000481606 0.000431524 0.0187261 0.0171522 -1 -1 -1 -1 34 4119 45 6.79088e+06 296384 618332. 2139.56 2.03 0.178009 0.157929 25102 150614 -1 3072 18 1428 4203 233689 55761 7.32848 7.32848 -170.707 -7.32848 0 0 787024. 2723.27 0.05 0.08 0.14 -1 -1 0.05 0.0306779 0.0281631 148 202 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_103.v common 4.64 vpr 64.37 MiB -1 -1 0.25 18820 13 0.37 -1 -1 32476 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 285 317 1 219 85 17 17 289 -1 unnamed_device 25.2 MiB 0.46 2930 1425 7525 1768 5171 586 64.4 MiB 0.05 0.00 10.4559 8.30966 -180.808 -8.30966 8.30966 0.25 0.000502423 0.000463715 0.0224499 0.0206809 -1 -1 -1 -1 36 3708 27 6.79088e+06 282912 648988. 2245.63 2.23 0.211147 0.187347 25390 158009 -1 3210 17 1367 3795 216510 50749 7.33966 7.33966 -172.69 -7.33966 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0240039 0.0219196 145 191 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_104.v common 3.64 vpr 64.62 MiB -1 -1 0.14 18052 12 0.17 -1 -1 32272 -1 -1 24 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 29 32 239 271 1 185 85 17 17 289 -1 unnamed_device 25.2 MiB 0.48 2084 1062 6595 1474 4636 485 64.6 MiB 0.04 0.00 10.0683 7.87572 -156.471 -7.87572 7.87572 0.40 0.000377318 0.000346308 0.0159074 0.0146289 -1 -1 -1 -1 30 2731 21 6.79088e+06 323328 556674. 1926.21 1.31 0.146981 0.129805 24526 138013 -1 2294 18 1137 2909 136931 33931 6.58776 6.58776 -145.673 -6.58776 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0182257 0.0165595 115 154 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_105.v common 2.40 vpr 64.36 MiB -1 -1 0.14 18056 11 0.13 -1 -1 32284 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 235 267 1 172 82 17 17 289 -1 unnamed_device 24.5 MiB 0.32 2050 1060 6668 1430 4144 1094 64.4 MiB 0.04 0.00 7.79354 6.47149 -144.071 -6.47149 6.47149 0.24 0.000355213 0.000324341 0.0157647 0.0144757 -1 -1 -1 -1 30 2916 41 6.79088e+06 242496 556674. 1926.21 0.65 0.0815988 0.0723604 24526 138013 -1 2303 20 1233 3012 153485 37395 5.85694 5.85694 -146.237 -5.85694 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.018489 0.0167165 105 141 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_106.v common 5.00 vpr 64.54 MiB -1 -1 0.23 18440 13 0.37 -1 -1 32424 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 31 32 294 326 1 211 85 17 17 289 -1 unnamed_device 24.9 MiB 0.70 2712 1384 8455 2000 5617 838 64.5 MiB 0.06 0.00 10.7696 8.27424 -162.337 -8.27424 8.27424 0.24 0.000474087 0.00042731 0.0248337 0.0227038 -1 -1 -1 -1 44 3185 20 6.79088e+06 296384 787024. 2723.27 2.15 0.239145 0.211054 27118 194962 -1 2809 17 1208 3870 211069 47834 7.26465 7.26465 -155.018 -7.26465 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0260052 0.0238743 146 203 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_107.v common 4.01 vpr 64.32 MiB -1 -1 0.15 18056 10 0.23 -1 -1 32416 -1 -1 20 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 219 251 1 164 81 17 17 289 -1 unnamed_device 24.9 MiB 0.41 2040 1050 9181 2635 5082 1464 64.3 MiB 0.05 0.00 8.60248 6.23968 -127.611 -6.23968 6.23968 0.25 0.000341543 0.000311725 0.020299 0.0185793 -1 -1 -1 -1 30 2491 49 6.79088e+06 269440 556674. 1926.21 1.98 0.183649 0.161612 24526 138013 -1 2107 16 952 2430 121433 29267 5.32762 5.32762 -123.296 -5.32762 0 0 706193. 2443.58 0.03 0.04 0.10 -1 -1 0.03 0.0157135 0.0142992 102 134 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_108.v common 3.06 vpr 64.46 MiB -1 -1 0.27 18052 14 0.21 -1 -1 32268 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66008 32 32 239 271 1 181 84 17 17 289 -1 unnamed_device 24.9 MiB 0.73 2315 1098 11430 3365 6228 1837 64.5 MiB 0.06 0.00 10.7127 7.63704 -166.154 -7.63704 7.63704 0.24 0.000386695 0.000354045 0.0270002 0.0247053 -1 -1 -1 -1 30 3052 25 6.79088e+06 269440 556674. 1926.21 0.65 0.0895294 0.0802576 24526 138013 -1 2455 17 1129 3039 153350 36717 6.70624 6.70624 -158.346 -6.70624 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0180472 0.0163852 109 145 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_109.v common 3.80 vpr 64.23 MiB -1 -1 0.19 18440 13 0.30 -1 -1 31856 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 31 32 266 298 1 201 86 17 17 289 -1 unnamed_device 24.9 MiB 0.22 2581 1245 12938 3565 7972 1401 64.2 MiB 0.07 0.00 9.50492 7.70092 -164.904 -7.70092 7.70092 0.25 0.000426903 0.000390675 0.0317082 0.0290071 -1 -1 -1 -1 40 2648 20 6.79088e+06 309856 706193. 2443.58 1.70 0.179053 0.1576 26254 175826 -1 2643 32 1411 4011 312466 112192 6.87412 6.87412 -157.009 -6.87412 0 0 926341. 3205.33 0.03 0.10 0.09 -1 -1 0.03 0.0302607 0.0270951 131 175 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_110.v common 4.15 vpr 64.27 MiB -1 -1 0.15 18056 12 0.13 -1 -1 32216 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 31 32 225 257 1 170 83 17 17 289 -1 unnamed_device 24.9 MiB 0.49 2115 1069 8363 2595 4472 1296 64.3 MiB 0.04 0.00 7.74408 6.38969 -140.212 -6.38969 6.38969 0.35 0.000345596 0.000315547 0.018183 0.0166542 -1 -1 -1 -1 34 2730 27 6.79088e+06 269440 618332. 2139.56 1.95 0.172862 0.151998 25102 150614 -1 2386 18 1076 2987 160528 38621 5.77854 5.77854 -138.465 -5.77854 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0168124 0.0152225 103 134 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_111.v common 7.51 vpr 64.32 MiB -1 -1 0.17 18296 12 0.18 -1 -1 33036 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 32 32 288 320 1 203 88 17 17 289 -1 unnamed_device 25.5 MiB 0.51 3004 1280 11788 3296 6900 1592 64.3 MiB 0.07 0.00 10.2613 7.00869 -152.842 -7.00869 7.00869 0.27 0.000438351 0.000399908 0.031924 0.029294 -1 -1 -1 -1 28 3899 44 6.79088e+06 323328 531479. 1839.03 5.38 0.219573 0.193871 23950 126010 -1 2955 20 1664 4630 280626 64993 6.12648 6.12648 -151.532 -6.12648 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0235006 0.0210914 135 194 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_112.v common 6.17 vpr 64.38 MiB -1 -1 0.19 18828 13 0.26 -1 -1 32432 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 31 32 282 314 1 210 85 17 17 289 -1 unnamed_device 25.2 MiB 0.59 2791 1262 11989 3047 7402 1540 64.4 MiB 0.09 0.00 9.30843 7.42893 -161.431 -7.42893 7.42893 0.28 0.000974651 0.000901685 0.043486 0.040061 -1 -1 -1 -1 30 3449 32 6.79088e+06 296384 556674. 1926.21 3.72 0.235374 0.209057 24526 138013 -1 2705 19 1433 4023 185362 45909 6.48354 6.48354 -153.414 -6.48354 0 0 706193. 2443.58 0.04 0.09 0.09 -1 -1 0.04 0.0421007 0.0381483 146 191 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_113.v common 3.75 vpr 64.15 MiB -1 -1 0.16 18048 11 0.15 -1 -1 32388 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 32 32 233 265 1 180 86 17 17 289 -1 unnamed_device 24.5 MiB 0.41 2072 1111 7835 1720 5449 666 64.2 MiB 0.05 0.00 7.45434 6.20134 -144.716 -6.20134 6.20134 0.32 0.000830303 0.000790451 0.0195382 0.0179662 -1 -1 -1 -1 36 2970 27 6.79088e+06 296384 648988. 2245.63 1.69 0.172648 0.151291 25390 158009 -1 2502 29 1264 3459 234056 74739 5.52096 5.52096 -139.628 -5.52096 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.0240282 0.0214863 110 139 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_114.v common 5.62 vpr 64.79 MiB -1 -1 0.17 18056 13 0.24 -1 -1 32176 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66348 32 32 254 286 1 184 81 17 17 289 -1 unnamed_device 24.9 MiB 1.26 2540 1123 6906 1729 4876 301 64.8 MiB 0.04 0.00 10.5313 7.62596 -162.162 -7.62596 7.62596 0.40 0.000407825 0.000374245 0.018867 0.0173648 -1 -1 -1 -1 38 2722 40 6.79088e+06 229024 678818. 2348.85 2.19 0.276797 0.244307 25966 169698 -1 2249 15 995 2896 146488 34789 6.54512 6.54512 -154.218 -6.54512 0 0 902133. 3121.57 0.05 0.07 0.16 -1 -1 0.05 0.0297021 0.0269232 116 160 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_115.v common 3.89 vpr 63.58 MiB -1 -1 0.16 18436 13 0.24 -1 -1 32396 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65108 32 32 285 317 1 212 85 17 17 289 -1 unnamed_device 24.9 MiB 0.63 2626 1379 8083 1955 5557 571 63.6 MiB 0.07 0.00 9.80963 7.47873 -167.813 -7.47873 7.47873 0.25 0.000461112 0.000414019 0.0308002 0.0282531 -1 -1 -1 -1 34 3779 35 6.79088e+06 282912 618332. 2139.56 1.52 0.160694 0.142529 25102 150614 -1 3127 35 2346 6906 463431 130783 6.64799 6.64799 -160.553 -6.64799 0 0 787024. 2723.27 0.03 0.13 0.08 -1 -1 0.03 0.0366382 0.0328335 141 191 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_116.v common 3.53 vpr 64.07 MiB -1 -1 0.16 18436 11 0.17 -1 -1 32420 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65612 29 32 243 275 1 183 84 17 17 289 -1 unnamed_device 25.0 MiB 0.49 2499 1173 5208 1126 3631 451 64.1 MiB 0.03 0.00 8.34934 6.48043 -132.63 -6.48043 6.48043 0.25 0.000388058 0.000355693 0.0135592 0.0124786 -1 -1 -1 -1 36 2852 31 6.79088e+06 309856 648988. 2245.63 1.48 0.140205 0.122902 25390 158009 -1 2465 15 967 2919 169443 38934 5.75934 5.75934 -130.721 -5.75934 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0215183 0.0194205 118 158 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_117.v common 7.21 vpr 64.50 MiB -1 -1 0.24 18824 14 0.29 -1 -1 33064 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 318 350 1 238 89 17 17 289 -1 unnamed_device 25.6 MiB 0.50 3185 1427 9989 2338 6256 1395 64.5 MiB 0.07 0.00 11.6109 8.7465 -186.455 -8.7465 8.7465 0.33 0.000521333 0.000476424 0.0308609 0.0283334 -1 -1 -1 -1 30 4195 34 6.79088e+06 336800 556674. 1926.21 4.77 0.280847 0.2493 24526 138013 -1 3114 19 1654 4325 208709 51804 7.58672 7.58672 -175.163 -7.58672 0 0 706193. 2443.58 0.03 0.06 0.08 -1 -1 0.03 0.0266528 0.0243323 164 224 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_118.v common 3.55 vpr 64.24 MiB -1 -1 0.14 18052 12 0.13 -1 -1 32232 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 222 254 1 182 84 17 17 289 -1 unnamed_device 24.9 MiB 0.32 2515 1195 7953 1918 5225 810 64.2 MiB 0.10 0.00 9.02976 6.57733 -149.186 -6.57733 6.57733 0.27 0.00096 0.00088875 0.0449597 0.0417068 -1 -1 -1 -1 40 2450 19 6.79088e+06 282912 706193. 2443.58 1.51 0.16322 0.144706 26254 175826 -1 2277 19 1016 2613 138232 32332 5.70014 5.70014 -139.839 -5.70014 0 0 926341. 3205.33 0.03 0.04 0.15 -1 -1 0.03 0.0177558 0.0160847 105 131 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_119.v common 4.23 vpr 64.32 MiB -1 -1 0.31 18824 13 0.26 -1 -1 33012 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 282 314 1 202 87 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2586 1294 11223 2709 7284 1230 64.3 MiB 0.07 0.00 9.80636 7.81522 -163.002 -7.81522 7.81522 0.24 0.000459996 0.000421553 0.0298052 0.027397 -1 -1 -1 -1 32 3772 44 6.79088e+06 309856 586450. 2029.24 1.80 0.216101 0.190564 24814 144142 -1 3139 27 1415 4088 291600 96304 6.80686 6.80686 -159.585 -6.80686 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0326913 0.0294747 141 188 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_120.v common 3.43 vpr 64.70 MiB -1 -1 0.16 18428 13 0.16 -1 -1 32224 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 238 270 1 179 87 17 17 289 -1 unnamed_device 24.9 MiB 0.33 2213 1145 7959 1748 5469 742 64.7 MiB 0.06 0.00 9.57282 7.74786 -170.737 -7.74786 7.74786 0.30 0.000551588 0.000502718 0.0268101 0.0244864 -1 -1 -1 -1 32 2899 40 6.79088e+06 309856 586450. 2029.24 1.46 0.179622 0.159166 24814 144142 -1 2346 15 990 2455 133104 32316 6.67386 6.67386 -160.516 -6.67386 0 0 744469. 2576.02 0.04 0.05 0.10 -1 -1 0.04 0.0230009 0.0211562 112 144 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_121.v common 3.57 vpr 64.93 MiB -1 -1 0.17 18052 12 0.23 -1 -1 32288 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 32 32 269 301 1 193 85 17 17 289 -1 unnamed_device 24.9 MiB 0.83 2838 1258 5665 1169 4247 249 64.9 MiB 0.04 0.00 10.2294 7.48857 -162.185 -7.48857 7.48857 0.27 0.000426859 0.00038986 0.0193522 0.0178721 -1 -1 -1 -1 32 3332 43 6.79088e+06 282912 586450. 2029.24 0.72 0.118284 0.105925 24814 144142 -1 2752 17 1274 3805 210568 50438 6.37282 6.37282 -153.729 -6.37282 0 0 744469. 2576.02 0.04 0.12 0.08 -1 -1 0.04 0.0501828 0.0454932 132 175 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_122.v common 6.84 vpr 64.75 MiB -1 -1 0.20 19208 15 0.56 -1 -1 32720 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 350 382 1 251 89 17 17 289 -1 unnamed_device 25.6 MiB 1.00 3569 1573 10583 2766 6384 1433 64.7 MiB 0.09 0.00 11.6887 9.43481 -197.257 -9.43481 9.43481 0.24 0.000575225 0.00052701 0.0405772 0.0372963 -1 -1 -1 -1 48 3820 22 6.79088e+06 336800 865456. 2994.66 3.48 0.393652 0.351941 27694 206865 -1 3410 19 1843 6055 331838 74371 8.18111 8.18111 -182.275 -8.18111 0 0 1.05005e+06 3633.38 0.04 0.08 0.11 -1 -1 0.04 0.0308149 0.0280731 184 256 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_123.v common 2.87 vpr 64.00 MiB -1 -1 0.15 17668 10 0.10 -1 -1 32064 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65540 30 32 174 206 1 132 75 17 17 289 -1 unnamed_device 24.3 MiB 0.27 1704 689 6079 1358 4541 180 64.0 MiB 0.03 0.00 5.85167 5.06685 -115.513 -5.06685 5.06685 0.25 0.000272135 0.000249038 0.0120598 0.0110675 -1 -1 -1 -1 34 1844 23 6.79088e+06 175136 618332. 2139.56 1.13 0.0922076 0.0806298 25102 150614 -1 1531 16 723 1671 81394 21367 4.46811 4.46811 -112.797 -4.46811 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0119656 0.0108259 66 86 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_124.v common 4.10 vpr 64.34 MiB -1 -1 0.15 18056 13 0.16 -1 -1 32248 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 30 32 228 260 1 170 83 17 17 289 -1 unnamed_device 24.6 MiB 0.72 2214 1013 9083 2607 5166 1310 64.3 MiB 0.05 0.00 9.66643 7.93028 -158.567 -7.93028 7.93028 0.35 0.000357607 0.000326665 0.0206406 0.0189224 -1 -1 -1 -1 34 2709 33 6.79088e+06 282912 618332. 2139.56 1.47 0.155242 0.1373 25102 150614 -1 2341 27 1048 2773 214239 76852 6.87418 6.87418 -150.154 -6.87418 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0227765 0.0204907 108 140 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_125.v common 4.29 vpr 64.83 MiB -1 -1 0.17 18292 12 0.18 -1 -1 32276 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 32 32 264 296 1 193 87 17 17 289 -1 unnamed_device 25.2 MiB 0.53 2664 1204 6039 1295 4393 351 64.8 MiB 0.06 0.00 9.33663 7.42897 -167.088 -7.42897 7.42897 0.45 0.000748074 0.000682446 0.0272169 0.0249518 -1 -1 -1 -1 32 3186 39 6.79088e+06 309856 586450. 2029.24 1.61 0.19246 0.169113 24814 144142 -1 2600 14 1082 2781 153438 36660 6.37287 6.37287 -156.925 -6.37287 0 0 744469. 2576.02 0.05 0.07 0.14 -1 -1 0.05 0.032197 0.0295269 122 170 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_126.v common 2.53 vpr 64.12 MiB -1 -1 0.15 17672 9 0.11 -1 -1 31992 -1 -1 21 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65660 25 32 183 215 1 134 78 17 17 289 -1 unnamed_device 24.5 MiB 0.35 1513 648 7216 2007 4704 505 64.1 MiB 0.05 0.00 5.889 5.1159 -95.0834 -5.1159 5.1159 0.26 0.000290205 0.000265211 0.026009 0.0242288 -1 -1 -1 -1 30 1972 23 6.79088e+06 282912 556674. 1926.21 0.76 0.077457 0.0696231 24526 138013 -1 1532 18 764 2122 115511 30012 4.5968 4.5968 -95.8798 -4.5968 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0140883 0.0127257 88 110 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_127.v common 4.22 vpr 63.79 MiB -1 -1 0.18 18436 12 0.24 -1 -1 32436 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65324 32 32 300 332 1 224 87 17 17 289 -1 unnamed_device 24.8 MiB 0.34 3045 1374 8343 1969 5805 569 63.8 MiB 0.06 0.00 9.97086 7.70352 -168.911 -7.70352 7.70352 0.25 0.000460963 0.000421707 0.0249877 0.0229274 -1 -1 -1 -1 38 3802 30 6.79088e+06 309856 678818. 2348.85 2.16 0.213639 0.188965 25966 169698 -1 3001 21 1702 4852 241275 56642 6.49817 6.49817 -159.124 -6.49817 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.029603 0.0270055 149 206 -1 -1 -1 -1 +fixed_k6_frac_N8_22nm.xml mult_128.v common 8.43 vpr 64.56 MiB -1 -1 0.18 18676 13 0.28 -1 -1 31596 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66108 31 32 290 322 1 214 89 17 17 289 -1 unnamed_device 24.9 MiB 0.67 2884 1321 10979 2886 6026 2067 64.6 MiB 0.06 0.00 10.7249 8.28064 -170.23 -8.28064 8.28064 0.24 0.000458984 0.000419435 0.0290037 0.0265888 -1 -1 -1 -1 30 4442 39 6.79088e+06 350272 556674. 1926.21 5.83 0.209846 0.18645 24526 138013 -1 3137 25 1751 5411 317221 91806 6.76345 6.76345 -158.739 -6.76345 0 0 706193. 2443.58 0.04 0.14 0.11 -1 -1 0.04 0.0497607 0.0449491 152 199 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_001.v common 5.80 vpr 65.13 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66692 32 32 354 285 1 207 93 17 17 289 -1 unnamed_device 25.6 MiB 2.12 2779 1278 16893 5344 9435 2114 65.1 MiB 0.10 0.00 6.98757 5.68891 -164.239 -5.68891 5.68891 0.25 0.000338691 0.000310099 0.0300408 0.0274606 -1 -1 -1 -1 28 3219 28 6.87369e+06 405241 531479. 1839.03 2.22 0.157807 0.138497 24610 126494 -1 2606 22 1750 2807 239588 55064 4.64695 4.64695 -157.22 -4.64695 0 0 648988. 2245.63 0.04 0.10 0.07 -1 -1 0.04 0.0310265 0.0277948 140 50 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_002.v common 4.10 vpr 65.14 MiB -1 -1 0.15 18060 1 0.04 -1 -1 29588 -1 -1 26 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66700 30 32 363 293 1 200 88 17 17 289 -1 unnamed_device 25.2 MiB 2.26 2339 1135 13153 3755 7866 1532 65.1 MiB 0.07 0.00 5.6483 4.6679 -138.364 -4.6679 4.6679 0.25 0.000376387 0.000339735 0.0260552 0.0238597 -1 -1 -1 -1 32 2500 24 6.87369e+06 363320 586450. 2029.24 0.40 0.0720625 0.0638607 25474 144626 -1 2037 21 1653 2504 161353 39229 3.72316 3.72316 -133.558 -3.72316 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.018555 0.0164825 138 63 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_003.v common 4.52 vpr 64.16 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29804 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65700 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 24.8 MiB 1.92 2478 1094 14965 5159 7778 2028 64.2 MiB 0.08 0.00 5.41115 4.32745 -123.858 -4.32745 4.32745 0.26 0.00029771 0.000272503 0.0284356 0.0260371 -1 -1 -1 -1 32 2462 24 6.87369e+06 293451 586450. 2029.24 1.20 0.158071 0.138595 25474 144626 -1 1923 20 1108 1542 96591 24435 3.88596 3.88596 -121.789 -3.88596 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0144447 0.012843 118 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_004.v common 3.08 vpr 64.42 MiB -1 -1 0.12 18064 1 0.04 -1 -1 29732 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 29 32 308 248 1 172 90 17 17 289 -1 unnamed_device 24.9 MiB 0.98 2239 851 8532 2063 5786 683 64.4 MiB 0.06 0.00 5.55862 4.64138 -122.547 -4.64138 4.64138 0.26 0.000307462 0.000282124 0.0164768 0.0151923 -1 -1 -1 -1 32 2081 20 6.87369e+06 405241 586450. 2029.24 0.62 0.0640387 0.056848 25474 144626 -1 1662 22 1299 2371 141246 35332 3.7854 3.7854 -114.536 -3.7854 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0152355 0.0135343 124 31 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_005.v common 3.79 vpr 65.01 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29848 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66568 32 32 336 268 1 181 91 17 17 289 -1 unnamed_device 25.2 MiB 1.26 2579 1028 12331 3533 8153 645 65.0 MiB 0.07 0.00 5.58731 4.58138 -133.975 -4.58138 4.58138 0.25 0.00032842 0.00029842 0.0222301 0.0202265 -1 -1 -1 -1 34 2450 23 6.87369e+06 377294 618332. 2139.56 1.15 0.13371 0.116761 25762 151098 -1 2095 20 1351 2747 172345 43095 3.7624 3.7624 -131.476 -3.7624 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.015162 0.0134923 132 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_006.v common 4.58 vpr 65.02 MiB -1 -1 0.14 18448 1 0.03 -1 -1 29780 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 366 295 1 189 96 17 17 289 -1 unnamed_device 25.6 MiB 1.47 2521 1045 10389 2533 6980 876 65.0 MiB 0.11 0.00 4.09707 3.40153 -116.732 -3.40153 3.40153 0.44 0.000632207 0.000578463 0.0332248 0.0304864 -1 -1 -1 -1 30 2392 22 6.87369e+06 447163 556674. 1926.21 1.17 0.156714 0.137506 25186 138497 -1 1903 19 1087 1810 94547 23615 2.90721 2.90721 -116.443 -2.90721 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0210304 0.0187682 138 58 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_007.v common 4.53 vpr 64.02 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30528 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 27 32 259 221 1 141 80 17 17 289 -1 unnamed_device 24.9 MiB 2.14 1624 653 12120 3521 6665 1934 64.0 MiB 0.09 0.00 4.57488 3.84098 -103.196 -3.84098 3.84098 0.44 0.000480389 0.000439216 0.0357836 0.0328233 -1 -1 -1 -1 30 1522 20 6.87369e+06 293451 556674. 1926.21 0.59 0.0942957 0.0835691 25186 138497 -1 1227 20 894 1556 82299 20516 2.81866 2.81866 -96.2951 -2.81866 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0122356 0.0108607 97 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_008.v common 2.67 vpr 64.45 MiB -1 -1 0.19 17672 1 0.02 -1 -1 29744 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 31 32 271 219 1 164 96 17 17 289 -1 unnamed_device 24.9 MiB 0.68 2063 1017 12798 3323 7724 1751 64.4 MiB 0.06 0.00 4.11555 3.57969 -107.766 -3.57969 3.57969 0.31 0.000280987 0.000257318 0.0179421 0.0164247 -1 -1 -1 -1 32 2056 21 6.87369e+06 461137 586450. 2029.24 0.37 0.0598981 0.0528727 25474 144626 -1 1863 18 869 1628 98904 24067 2.70166 2.70166 -100.41 -2.70166 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0134961 0.0120734 119 4 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_009.v common 3.65 vpr 64.42 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29768 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 31 32 317 271 1 175 83 17 17 289 -1 unnamed_device 24.9 MiB 1.75 2074 1069 13943 3853 8284 1806 64.4 MiB 0.08 0.00 4.71896 3.59126 -121.314 -3.59126 3.59126 0.26 0.000300172 0.000275204 0.0327664 0.030306 -1 -1 -1 -1 32 2340 23 6.87369e+06 279477 586450. 2029.24 0.41 0.0792721 0.0707055 25474 144626 -1 1994 22 1117 1624 122047 28163 2.96331 2.96331 -117.189 -2.96331 0 0 744469. 2576.02 0.05 0.07 0.11 -1 -1 0.05 0.0269692 0.0240161 110 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_010.v common 5.50 vpr 64.53 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29756 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 298 248 1 162 81 17 17 289 -1 unnamed_device 25.1 MiB 2.97 1876 975 12681 3745 6747 2189 64.5 MiB 0.07 0.00 4.66108 3.90928 -131.51 -3.90928 3.90928 0.25 0.00030816 0.000282988 0.0298978 0.0278187 -1 -1 -1 -1 32 2119 22 6.87369e+06 237555 586450. 2029.24 1.04 0.113415 0.0997871 25474 144626 -1 1840 18 1127 1808 118643 28174 3.01796 3.01796 -123.051 -3.01796 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0243406 0.0217732 107 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_011.v common 4.92 vpr 64.09 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29796 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65624 30 32 303 262 1 148 80 17 17 289 -1 unnamed_device 24.9 MiB 2.42 1634 783 11948 4947 6106 895 64.1 MiB 0.05 0.00 4.23198 3.85608 -112.834 -3.85608 3.85608 0.25 0.000296286 0.000271011 0.0217417 0.0199276 -1 -1 -1 -1 28 2153 36 6.87369e+06 251529 531479. 1839.03 1.18 0.116888 0.101806 24610 126494 -1 1655 22 1103 1769 168234 43143 3.01626 3.01626 -112.104 -3.01626 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0149998 0.0130769 99 63 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_012.v common 4.20 vpr 64.57 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29732 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 24.8 MiB 1.84 2449 1027 12898 3673 7248 1977 64.6 MiB 0.07 0.00 4.7813 3.6715 -118.222 -3.6715 3.6715 0.25 0.000276217 0.00025305 0.0233421 0.0213867 -1 -1 -1 -1 32 2217 20 6.87369e+06 251529 586450. 2029.24 0.99 0.121125 0.105513 25474 144626 -1 1865 18 1024 1435 104148 24249 2.77201 2.77201 -111.424 -2.77201 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0124142 0.0110837 102 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_013.v common 6.02 vpr 64.56 MiB -1 -1 0.21 18060 1 0.04 -1 -1 29956 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66108 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 24.9 MiB 2.77 2479 1044 14147 4566 6974 2607 64.6 MiB 0.08 0.00 4.50463 4.21693 -134.575 -4.21693 4.21693 0.30 0.000329492 0.000301485 0.0259677 0.0238215 -1 -1 -1 -1 30 2730 27 6.87369e+06 349346 556674. 1926.21 1.60 0.132473 0.116447 25186 138497 -1 1999 23 1665 2538 150407 37762 3.15591 3.15591 -119.224 -3.15591 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0170917 0.0151913 139 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_014.v common 4.56 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29804 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66292 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 25.4 MiB 2.01 2505 986 14999 4213 8032 2754 64.7 MiB 0.08 0.00 5.95652 4.79778 -139.915 -4.79778 4.79778 0.25 0.000334016 0.000305104 0.0255084 0.0233651 -1 -1 -1 -1 32 2454 25 6.87369e+06 433189 586450. 2029.24 1.07 0.12617 0.110398 25474 144626 -1 1945 22 1516 2402 150206 37108 3.67906 3.67906 -131.28 -3.67906 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0168173 0.0149209 133 61 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_015.v common 3.07 vpr 64.52 MiB -1 -1 0.15 17676 1 0.02 -1 -1 29868 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66068 29 32 248 215 1 142 82 17 17 289 -1 unnamed_device 24.9 MiB 1.40 1696 858 12008 3401 6739 1868 64.5 MiB 0.05 0.00 3.78522 3.15872 -98.3476 -3.15872 3.15872 0.24 0.00026521 0.000242593 0.018962 0.017341 -1 -1 -1 -1 30 1702 24 6.87369e+06 293451 556674. 1926.21 0.33 0.0533522 0.046956 25186 138497 -1 1492 19 693 1109 62576 15355 2.83796 2.83796 -99.8638 -2.83796 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0116954 0.0103542 94 27 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 4.40 vpr 64.64 MiB -1 -1 0.19 18440 1 0.03 -1 -1 30168 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2351 1142 14908 4316 8497 2095 64.6 MiB 0.09 0.00 4.2467 3.7455 -126.819 -3.7455 3.7455 0.30 0.000339557 0.000310568 0.0292364 0.026805 -1 -1 -1 -1 32 2773 22 6.87369e+06 335372 586450. 2029.24 1.07 0.140584 0.122861 25474 144626 -1 2188 19 1521 2634 169491 39910 2.97426 2.97426 -122.17 -2.97426 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0158553 0.0142194 135 58 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 4.43 vpr 65.07 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29816 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 25.2 MiB 2.59 2594 1106 15639 5153 7404 3082 65.1 MiB 0.09 0.00 5.08229 4.18625 -135.173 -4.18625 4.18625 0.24 0.00034271 0.000315029 0.0333882 0.030975 -1 -1 -1 -1 30 2654 25 6.87369e+06 321398 556674. 1926.21 0.39 0.0779122 0.0697554 25186 138497 -1 2046 22 1375 2028 125721 30050 3.0509 3.0509 -118.831 -3.0509 0 0 706193. 2443.58 0.03 0.04 0.10 -1 -1 0.03 0.0182401 0.0161792 136 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 4.70 vpr 64.24 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30116 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 32 32 323 276 1 156 93 17 17 289 -1 unnamed_device 24.7 MiB 2.05 2257 926 17103 5432 9461 2210 64.2 MiB 0.13 0.00 3.68501 2.85191 -105.908 -2.85191 2.85191 0.25 0.000847649 0.000787011 0.0450084 0.0415445 -1 -1 -1 -1 32 2002 22 6.87369e+06 405241 586450. 2029.24 1.10 0.152835 0.134719 25474 144626 -1 1661 17 1142 1944 120028 29235 2.07352 2.07352 -97.0447 -2.07352 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0127224 0.0113475 110 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 2.78 vpr 63.89 MiB -1 -1 0.10 17528 1 0.02 -1 -1 29868 -1 -1 15 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65420 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 24.9 MiB 0.53 1506 681 11976 4667 6344 965 63.9 MiB 0.05 0.00 2.88898 2.40568 -84.2035 -2.40568 2.40568 0.35 0.000230573 0.000210344 0.0181275 0.0165527 -1 -1 -1 -1 34 1276 19 6.87369e+06 209608 618332. 2139.56 0.88 0.0736418 0.0640869 25762 151098 -1 1140 17 567 794 53109 12483 1.81522 1.81522 -81.3143 -1.81522 0 0 787024. 2723.27 0.03 0.02 0.08 -1 -1 0.03 0.00970028 0.00862224 71 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 4.51 vpr 64.20 MiB -1 -1 0.12 18060 1 0.02 -1 -1 29796 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65744 31 32 291 243 1 178 84 17 17 289 -1 unnamed_device 24.9 MiB 2.19 2220 961 14358 5263 6619 2476 64.2 MiB 0.08 0.00 6.07113 5.06873 -151.735 -5.06873 5.06873 0.25 0.000358414 0.000333638 0.0281325 0.0259646 -1 -1 -1 -1 30 2126 21 6.87369e+06 293451 556674. 1926.21 0.97 0.119718 0.104846 25186 138497 -1 1726 21 1006 1462 90107 22146 3.69941 3.69941 -133.261 -3.69941 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0147264 0.013189 114 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 3.28 vpr 64.35 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29956 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 24.9 MiB 0.78 2270 1098 17427 5042 9940 2445 64.3 MiB 0.10 0.00 5.48809 4.18395 -137.714 -4.18395 4.18395 0.25 0.000328306 0.000300353 0.0313602 0.0288796 -1 -1 -1 -1 28 2563 20 6.87369e+06 489084 531479. 1839.03 1.15 0.149045 0.131128 24610 126494 -1 2239 21 1371 2094 147615 35637 4.016 4.016 -141.152 -4.016 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0159409 0.014208 137 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_022.v common 4.53 vpr 64.32 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29916 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 32 32 372 300 1 206 87 17 17 289 -1 unnamed_device 24.9 MiB 1.91 2678 1260 15255 4028 9506 1721 64.3 MiB 0.10 0.00 5.24603 4.32815 -136.261 -4.32815 4.32815 0.25 0.000453897 0.000414665 0.0367843 0.0339982 -1 -1 -1 -1 30 2840 29 6.87369e+06 321398 556674. 1926.21 1.17 0.148596 0.131521 25186 138497 -1 2225 19 1315 2150 129279 30551 3.85476 3.85476 -132.586 -3.85476 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0156418 0.0140089 138 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 3.40 vpr 64.21 MiB -1 -1 0.10 18060 1 0.02 -1 -1 29792 -1 -1 18 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 26 32 190 182 1 108 76 17 17 289 -1 unnamed_device 25.2 MiB 1.35 1317 566 8396 2777 4117 1502 64.2 MiB 0.04 0.00 3.13338 2.41583 -71.9717 -2.41583 2.41583 0.25 0.000203836 0.000182325 0.0145818 0.0134291 -1 -1 -1 -1 26 1284 21 6.87369e+06 251529 503264. 1741.40 0.75 0.0793038 0.0686608 24322 120374 -1 1126 22 717 1085 75720 19389 2.17212 2.17212 -75.7209 -2.17212 0 0 618332. 2139.56 0.02 0.03 0.06 -1 -1 0.02 0.0101223 0.00893365 67 30 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 3.30 vpr 64.92 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30152 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 285 227 1 169 88 17 17 289 -1 unnamed_device 24.9 MiB 0.94 2097 1049 14908 4450 8551 1907 64.9 MiB 0.08 0.00 5.2197 4.59222 -130.8 -4.59222 4.59222 0.24 0.000295354 0.0002705 0.0241002 0.0220402 -1 -1 -1 -1 32 2268 21 6.87369e+06 335372 586450. 2029.24 1.03 0.112059 0.0980207 25474 144626 -1 1966 21 1268 2283 143914 34546 3.7121 3.7121 -127.472 -3.7121 0 0 744469. 2576.02 0.03 0.04 0.09 -1 -1 0.03 0.014224 0.0126546 120 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 2.03 vpr 64.13 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29712 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 25.2 MiB 0.51 1340 735 9836 2832 5893 1111 64.1 MiB 0.03 0.00 2.66305 2.35478 -79.4936 -2.35478 2.35478 0.25 0.000195429 0.000177475 0.0131108 0.011945 -1 -1 -1 -1 28 1349 20 6.87369e+06 167686 531479. 1839.03 0.31 0.0383427 0.0336698 24610 126494 -1 1279 18 595 720 57806 14512 1.93882 1.93882 -81.3285 -1.93882 0 0 648988. 2245.63 0.02 0.03 0.07 -1 -1 0.02 0.011158 0.00985811 64 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 2.88 vpr 63.77 MiB -1 -1 0.12 18056 1 0.02 -1 -1 30152 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 24.9 MiB 0.98 2085 932 9892 2528 6924 440 63.8 MiB 0.11 0.00 5.60262 4.76542 -131.149 -4.76542 4.76542 0.30 0.000296832 0.000272087 0.035253 0.0326811 -1 -1 -1 -1 26 2518 22 6.87369e+06 419215 503264. 1741.40 0.49 0.0786368 0.0705901 24322 120374 -1 2096 32 1737 2939 210434 50691 3.872 3.872 -127.362 -3.872 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0198711 0.0174655 120 24 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 3.39 vpr 64.89 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29944 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66452 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 24.9 MiB 0.79 2474 1054 16727 4817 9341 2569 64.9 MiB 0.09 0.00 4.54391 3.51795 -111.316 -3.51795 3.51795 0.29 0.000303592 0.000276236 0.0266519 0.0242859 -1 -1 -1 -1 28 2471 24 6.87369e+06 433189 531479. 1839.03 1.06 0.125733 0.110248 24610 126494 -1 2110 19 1290 2308 150392 36562 2.98246 2.98246 -112.166 -2.98246 0 0 648988. 2245.63 0.02 0.04 0.14 -1 -1 0.02 0.014283 0.0127629 130 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_028.v common 3.50 vpr 65.02 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29752 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 338 277 1 183 93 17 17 289 -1 unnamed_device 25.0 MiB 1.17 2236 1093 11433 2910 6842 1681 65.0 MiB 0.06 0.00 5.66492 4.81048 -136.943 -4.81048 4.81048 0.25 0.000325641 0.000298897 0.0192171 0.0176088 -1 -1 -1 -1 30 2323 24 6.87369e+06 405241 556674. 1926.21 0.99 0.124524 0.108552 25186 138497 -1 1955 23 1075 1929 108605 26660 3.99996 3.99996 -133.755 -3.99996 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0163959 0.0145775 128 50 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_029.v common 2.55 vpr 64.41 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29808 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 32 32 284 241 1 148 82 17 17 289 -1 unnamed_device 24.9 MiB 0.78 1785 959 11118 3077 6379 1662 64.4 MiB 0.06 0.00 3.63792 3.01142 -107.753 -3.01142 3.01142 0.35 0.000279667 0.000255769 0.0214261 0.019741 -1 -1 -1 -1 32 1994 19 6.87369e+06 251529 586450. 2029.24 0.35 0.0582033 0.0516193 25474 144626 -1 1714 18 879 1436 101674 23709 2.60666 2.60666 -105.374 -2.60666 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.012868 0.011506 101 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.41 vpr 64.49 MiB -1 -1 0.11 17912 1 0.02 -1 -1 29832 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 30 32 262 227 1 138 84 17 17 289 -1 unnamed_device 24.9 MiB 0.91 1644 645 11979 4232 5199 2548 64.5 MiB 0.06 0.00 3.71922 3.04032 -95.3449 -3.04032 3.04032 0.24 0.000643706 0.000601065 0.0220199 0.0202565 -1 -1 -1 -1 34 1737 24 6.87369e+06 307425 618332. 2139.56 1.12 0.115953 0.101499 25762 151098 -1 1305 21 903 1431 87262 23733 2.94926 2.94926 -95.9302 -2.94926 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0131376 0.0116079 95 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 3.63 vpr 63.98 MiB -1 -1 0.18 17676 1 0.03 -1 -1 29688 -1 -1 19 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65516 28 32 260 223 1 140 79 17 17 289 -1 unnamed_device 24.9 MiB 1.12 2176 705 11233 3031 6920 1282 64.0 MiB 0.05 0.00 4.53245 3.58631 -100.001 -3.58631 3.58631 0.24 0.000258351 0.000236282 0.018592 0.0170282 -1 -1 -1 -1 34 1817 24 6.87369e+06 265503 618332. 2139.56 1.09 0.101843 0.0884679 25762 151098 -1 1498 21 1087 2028 123464 32422 2.82496 2.82496 -100.192 -2.82496 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0132302 0.0117007 96 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_032.v common 3.29 vpr 64.43 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30216 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65972 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 24.7 MiB 1.03 2154 721 8092 1745 5645 702 64.4 MiB 0.04 0.00 4.63718 3.86314 -115.034 -3.86314 3.86314 0.26 0.000269999 0.000245848 0.0141003 0.0128609 -1 -1 -1 -1 32 1894 22 6.87369e+06 251529 586450. 2029.24 1.00 0.0989113 0.085688 25474 144626 -1 1497 16 987 1649 88162 23720 2.96326 2.96326 -109.749 -2.96326 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110703 0.00990835 101 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_033.v common 2.78 vpr 64.53 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29760 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 31 32 271 231 1 149 89 17 17 289 -1 unnamed_device 24.9 MiB 0.78 1850 927 12563 3215 8032 1316 64.5 MiB 0.06 0.00 4.00125 3.42265 -107.908 -3.42265 3.42265 0.27 0.000276398 0.000253509 0.0189718 0.0173754 -1 -1 -1 -1 32 1906 22 6.87369e+06 363320 586450. 2029.24 0.42 0.0676784 0.0597762 25474 144626 -1 1629 20 901 1604 91239 22844 2.75166 2.75166 -105.307 -2.75166 0 0 744469. 2576.02 0.04 0.05 0.14 -1 -1 0.04 0.0210922 0.018721 102 30 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 4.49 vpr 64.58 MiB -1 -1 0.18 18060 1 0.03 -1 -1 30212 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66128 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 24.9 MiB 2.38 2244 863 12938 3817 7914 1207 64.6 MiB 0.06 0.00 3.77556 3.08002 -100.294 -3.08002 3.08002 0.25 0.000282356 0.000258955 0.0207796 0.0190526 -1 -1 -1 -1 30 1838 22 6.87369e+06 349346 556674. 1926.21 0.69 0.093284 0.0814168 25186 138497 -1 1561 17 902 1386 82031 19933 2.25347 2.25347 -93.7602 -2.25347 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0118709 0.010591 105 54 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_035.v common 5.18 vpr 65.22 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29612 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 32 32 367 282 1 201 104 17 17 289 -1 unnamed_device 25.2 MiB 2.42 2344 1146 10352 2228 7273 851 65.2 MiB 0.07 0.00 4.92569 4.24719 -123.08 -4.24719 4.24719 0.27 0.000368919 0.000338189 0.0189776 0.0174183 -1 -1 -1 -1 28 2900 23 6.87369e+06 558954 531479. 1839.03 1.33 0.141629 0.123881 24610 126494 -1 2537 22 1665 3171 206581 51344 4.0723 4.0723 -130.143 -4.0723 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0174867 0.0155615 156 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_036.v common 4.25 vpr 64.88 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30132 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 391 311 1 194 104 17 17 289 -1 unnamed_device 24.8 MiB 2.37 2402 1081 18892 5390 10690 2812 64.9 MiB 0.10 0.00 4.68095 4.00848 -135.306 -4.00848 4.00848 0.24 0.000357663 0.00032748 0.0300492 0.0273707 -1 -1 -1 -1 32 2374 22 6.87369e+06 558954 586450. 2029.24 0.39 0.0788336 0.06992 25474 144626 -1 2026 19 1508 2475 143567 35245 3.17446 3.17446 -127.465 -3.17446 0 0 744469. 2576.02 0.03 0.04 0.16 -1 -1 0.03 0.0159635 0.0142608 149 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 3.90 vpr 64.01 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29492 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65544 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 24.9 MiB 1.82 2434 993 8831 2488 5523 820 64.0 MiB 0.05 0.00 4.95083 4.14789 -126.829 -4.14789 4.14789 0.25 0.000284845 0.000261619 0.0156499 0.0143835 -1 -1 -1 -1 32 2206 21 6.87369e+06 251529 586450. 2029.24 0.39 0.0531276 0.0469574 25474 144626 -1 1881 19 958 1525 103993 24504 3.15461 3.15461 -119.875 -3.15461 0 0 744469. 2576.02 0.04 0.05 0.14 -1 -1 0.04 0.0169656 0.0150243 106 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_038.v common 4.62 vpr 65.14 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29212 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 370 297 1 187 89 17 17 289 -1 unnamed_device 25.6 MiB 1.93 2217 1129 14147 4459 7560 2128 65.1 MiB 0.14 0.00 4.3461 3.7686 -123.743 -3.7686 3.7686 0.28 0.000620839 0.000567351 0.0472881 0.0432612 -1 -1 -1 -1 32 2620 20 6.87369e+06 363320 586450. 2029.24 1.22 0.166856 0.146757 25474 144626 -1 2210 20 1429 2447 155773 36552 3.00426 3.00426 -116.646 -3.00426 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0161313 0.0143767 136 61 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_039.v common 6.59 vpr 65.16 MiB -1 -1 0.17 18292 1 0.03 -1 -1 30164 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66720 31 32 377 302 1 237 92 17 17 289 -1 unnamed_device 25.3 MiB 2.75 2915 1335 13547 3729 7970 1848 65.2 MiB 0.09 0.00 6.76692 5.53978 -169.274 -5.53978 5.53978 0.26 0.000351561 0.000322679 0.025746 0.0236688 -1 -1 -1 -1 28 3654 23 6.87369e+06 405241 531479. 1839.03 2.34 0.14442 0.126946 24610 126494 -1 2988 22 2444 3552 326119 72975 5.20869 5.20869 -174.053 -5.20869 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0175115 0.0155948 155 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_040.v common 5.04 vpr 65.22 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29792 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 31 32 383 305 1 212 91 17 17 289 -1 unnamed_device 25.2 MiB 3.04 2741 1334 14575 4470 8160 1945 65.2 MiB 0.09 0.00 6.34854 5.22459 -163.482 -5.22459 5.22459 0.25 0.000351439 0.000321335 0.0270274 0.0247642 -1 -1 -1 -1 32 3169 36 6.87369e+06 391268 586450. 2029.24 0.53 0.0967574 0.0859341 25474 144626 -1 2624 20 1587 2410 208304 44942 4.5599 4.5599 -158.949 -4.5599 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164815 0.0147252 151 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 4.03 vpr 64.61 MiB -1 -1 0.18 18060 1 0.04 -1 -1 29768 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 352 285 1 186 92 17 17 289 -1 unnamed_device 24.9 MiB 2.19 2134 1048 14996 4681 7704 2611 64.6 MiB 0.08 0.00 4.61893 4.13563 -128.575 -4.13563 4.13563 0.24 0.000335656 0.000307486 0.025684 0.0235144 -1 -1 -1 -1 32 2650 22 6.87369e+06 405241 586450. 2029.24 0.39 0.0700836 0.0620377 25474 144626 -1 2076 22 1454 2414 153424 36772 3.09131 3.09131 -118.471 -3.09131 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0166059 0.0147621 133 55 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 4.06 vpr 64.91 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29768 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 291 242 1 183 86 17 17 289 -1 unnamed_device 24.9 MiB 1.85 2477 1095 15206 4442 8662 2102 64.9 MiB 0.08 0.00 5.51278 4.43075 -121.679 -4.43075 4.43075 0.25 0.000292028 0.0002669 0.0253669 0.0232324 -1 -1 -1 -1 28 2503 21 6.87369e+06 307425 531479. 1839.03 0.90 0.105951 0.0925844 24610 126494 -1 2252 18 1382 2015 133917 32844 4.15256 4.15256 -127.257 -4.15256 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0130387 0.0116467 114 27 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_043.v common 5.91 vpr 65.00 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29896 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 32 32 457 356 1 225 104 17 17 289 -1 unnamed_device 25.6 MiB 2.42 3065 1148 12304 2744 8146 1414 65.0 MiB 0.07 0.00 6.15708 4.89003 -155.75 -4.89003 4.89003 0.35 0.000421745 0.000385657 0.023456 0.0215124 -1 -1 -1 -1 30 3162 34 6.87369e+06 558954 556674. 1926.21 1.94 0.208648 0.182713 25186 138497 -1 2244 22 1501 2532 144540 36667 4.07996 4.07996 -146.784 -4.07996 0 0 706193. 2443.58 0.03 0.06 0.08 -1 -1 0.03 0.0238413 0.0212161 173 87 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_044.v common 3.27 vpr 64.49 MiB -1 -1 0.11 16980 1 0.03 -1 -1 29852 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 31 32 261 225 1 148 83 17 17 289 -1 unnamed_device 24.9 MiB 1.60 1997 648 8723 1892 5777 1054 64.5 MiB 0.04 0.00 4.27085 3.54105 -101.242 -3.54105 3.54105 0.24 0.000273941 0.000251112 0.0141802 0.0129943 -1 -1 -1 -1 30 1800 23 6.87369e+06 279477 556674. 1926.21 0.38 0.0500756 0.0439754 25186 138497 -1 1451 23 1102 1888 103072 27957 2.98326 2.98326 -102.512 -2.98326 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0136731 0.0120739 95 28 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_045.v common 5.40 vpr 65.09 MiB -1 -1 0.12 18064 1 0.03 -1 -1 29856 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 25.2 MiB 2.38 2833 1039 9058 2162 5891 1005 65.1 MiB 0.05 0.00 5.78298 4.80948 -141.445 -4.80948 4.80948 0.24 0.000334797 0.000307237 0.0177481 0.0163442 -1 -1 -1 -1 32 3153 40 6.87369e+06 349346 586450. 2029.24 1.70 0.143091 0.124424 25474 144626 -1 2143 18 1358 2000 125184 32958 3.90446 3.90446 -133.851 -3.90446 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0142968 0.0128029 139 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_046.v common 3.83 vpr 64.51 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29712 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 32 32 349 284 1 183 96 17 17 289 -1 unnamed_device 24.8 MiB 1.34 2291 1135 16740 4742 9662 2336 64.5 MiB 0.09 0.00 4.4574 3.7235 -119.349 -3.7235 3.7235 0.24 0.000325745 0.0002983 0.0287406 0.0263737 -1 -1 -1 -1 32 2604 22 6.87369e+06 447163 586450. 2029.24 1.09 0.136222 0.119082 25474 144626 -1 2160 22 1397 2353 160693 37464 2.99951 2.99951 -114.657 -2.99951 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164752 0.014613 133 53 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_047.v common 3.46 vpr 64.45 MiB -1 -1 0.14 17676 1 0.03 -1 -1 29764 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 1.06 1933 1125 13963 5217 7708 1038 64.5 MiB 0.08 0.00 4.86339 4.12259 -128.092 -4.12259 4.12259 0.34 0.000311483 0.000285719 0.023139 0.021179 -1 -1 -1 -1 30 2522 22 6.87369e+06 377294 556674. 1926.21 0.94 0.103938 0.0910827 25186 138497 -1 2070 22 1119 2125 158916 33999 3.6151 3.6151 -123.407 -3.6151 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0149392 0.0132718 123 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_048.v common 4.70 vpr 64.43 MiB -1 -1 0.12 18436 1 0.03 -1 -1 30156 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 353 287 1 203 88 17 17 289 -1 unnamed_device 25.1 MiB 2.35 2449 1198 10033 2856 6133 1044 64.4 MiB 0.08 0.00 5.38385 4.51686 -135.093 -4.51686 4.51686 0.24 0.000807747 0.000754987 0.0265271 0.0244839 -1 -1 -1 -1 28 2785 20 6.87369e+06 335372 531479. 1839.03 1.01 0.122769 0.108079 24610 126494 -1 2415 23 1599 2149 149891 36230 3.45411 3.45411 -130.575 -3.45411 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0173931 0.0154887 133 55 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_049.v common 4.46 vpr 64.64 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29752 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 361 291 1 189 97 17 17 289 -1 unnamed_device 25.2 MiB 2.43 2368 918 12307 3182 8052 1073 64.6 MiB 0.07 0.00 4.4072 3.86034 -120.004 -3.86034 3.86034 0.35 0.00033864 0.000309864 0.0204635 0.0187149 -1 -1 -1 -1 32 2307 29 6.87369e+06 461137 586450. 2029.24 0.44 0.0695487 0.0614194 25474 144626 -1 1780 19 1175 2009 111141 30153 3.17181 3.17181 -113.554 -3.17181 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0255044 0.0228037 137 55 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_050.v common 4.27 vpr 65.20 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30244 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 32 32 382 305 1 193 99 17 17 289 -1 unnamed_device 25.2 MiB 2.29 2780 1180 19251 5845 10953 2453 65.2 MiB 0.11 0.00 4.88053 4.12873 -137.656 -4.12873 4.12873 0.25 0.000352547 0.000322509 0.0316187 0.0288943 -1 -1 -1 -1 30 2658 24 6.87369e+06 489084 556674. 1926.21 0.42 0.0788497 0.0700438 25186 138497 -1 2203 22 1272 2103 125088 30094 3.13881 3.13881 -123.39 -3.13881 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0173831 0.0154972 145 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 3.73 vpr 64.93 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29780 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 306 248 1 170 97 17 17 289 -1 unnamed_device 24.9 MiB 0.73 2039 950 16747 5537 7489 3721 64.9 MiB 0.09 0.00 4.87439 4.39109 -126.937 -4.39109 4.39109 0.24 0.000739823 0.00069028 0.0312699 0.0286694 -1 -1 -1 -1 32 2421 33 6.87369e+06 461137 586450. 2029.24 1.56 0.147368 0.129021 25474 144626 -1 1887 19 1239 2208 161661 39936 3.8374 3.8374 -122.561 -3.8374 0 0 744469. 2576.02 0.04 0.07 0.11 -1 -1 0.04 0.0221875 0.0198695 124 24 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 3.98 vpr 63.73 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29584 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65256 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 24.7 MiB 1.52 2220 1156 13527 3541 8079 1907 63.7 MiB 0.08 0.00 5.73418 4.82931 -141.931 -4.82931 4.82931 0.25 0.00030882 0.000282743 0.0239023 0.0219138 -1 -1 -1 -1 32 2802 25 6.87369e+06 321398 586450. 2029.24 1.00 0.110833 0.096714 25474 144626 -1 2292 20 1462 2137 136001 32714 3.76576 3.76576 -131.742 -3.76576 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0146108 0.0130258 129 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 3.68 vpr 64.53 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 31 32 373 299 1 204 87 17 17 289 -1 unnamed_device 25.0 MiB 1.72 3065 1027 11415 2970 7272 1173 64.5 MiB 0.14 0.00 6.22918 4.75448 -142.391 -4.75448 4.75448 0.28 0.000987483 0.000915055 0.0501293 0.0464441 -1 -1 -1 -1 32 2875 29 6.87369e+06 335372 586450. 2029.24 0.48 0.0988957 0.0888001 25474 144626 -1 2254 24 1603 2664 177040 43531 3.86846 3.86846 -138.859 -3.86846 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0184397 0.0164021 140 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 5.11 vpr 64.59 MiB -1 -1 0.13 18056 1 0.04 -1 -1 30260 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 32 32 387 315 1 194 86 17 17 289 -1 unnamed_device 25.2 MiB 2.03 2512 933 14072 5096 6356 2620 64.6 MiB 0.08 0.00 5.37753 4.33435 -129.429 -4.33435 4.33435 0.26 0.00035546 0.000324775 0.0324406 0.0297238 -1 -1 -1 -1 36 2716 47 6.87369e+06 307425 648988. 2245.63 1.52 0.178156 0.156102 26050 158493 -1 1916 20 1476 2587 164969 42265 3.74066 3.74066 -126.184 -3.74066 0 0 828058. 2865.25 0.03 0.05 0.16 -1 -1 0.03 0.016656 0.0148392 134 77 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 2.54 vpr 64.50 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29788 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 251 219 1 141 87 17 17 289 -1 unnamed_device 24.7 MiB 0.72 1844 681 8727 1897 6216 614 64.5 MiB 0.04 0.00 4.11555 3.50043 -101.627 -3.50043 3.50043 0.24 0.000263113 0.000240025 0.0133071 0.0121657 -1 -1 -1 -1 28 2084 39 6.87369e+06 321398 531479. 1839.03 0.52 0.0574569 0.050311 24610 126494 -1 1578 21 1147 1792 117952 31406 2.70196 2.70196 -100.629 -2.70196 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0127218 0.0112708 93 23 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 3.75 vpr 64.36 MiB -1 -1 0.12 18060 1 0.04 -1 -1 30204 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 341 285 1 188 84 17 17 289 -1 unnamed_device 25.2 MiB 1.54 2256 885 8868 2113 6056 699 64.4 MiB 0.05 0.00 4.91669 4.05749 -134.722 -4.05749 4.05749 0.25 0.000319097 0.00029131 0.0168116 0.0154068 -1 -1 -1 -1 32 2587 38 6.87369e+06 279477 586450. 2029.24 0.66 0.0980793 0.0867185 25474 144626 -1 1878 20 1605 2345 172300 41500 3.30791 3.30791 -127.081 -3.30791 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0359951 0.0321136 120 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 4.72 vpr 65.30 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29816 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66864 32 32 387 293 1 236 93 17 17 289 -1 unnamed_device 25.6 MiB 2.03 2858 1452 14373 4135 8862 1376 65.3 MiB 0.09 0.00 6.54252 5.67053 -168.179 -5.67053 5.67053 0.26 0.000367846 0.000336898 0.0279177 0.0256551 -1 -1 -1 -1 32 3361 38 6.87369e+06 405241 586450. 2029.24 1.27 0.174645 0.153213 25474 144626 -1 2769 22 1643 2597 165910 40569 4.6651 4.6651 -156.548 -4.6651 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0186054 0.0166428 164 31 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_058.v common 3.95 vpr 64.71 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29944 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 340 270 1 185 98 17 17 289 -1 unnamed_device 25.2 MiB 2.19 2646 1109 17198 4503 10702 1993 64.7 MiB 0.09 0.00 5.22181 4.34585 -138.752 -4.34585 4.34585 0.24 0.000328609 0.000299932 0.0269673 0.0246622 -1 -1 -1 -1 32 2400 41 6.87369e+06 475111 586450. 2029.24 0.39 0.0787899 0.0696865 25474 144626 -1 1955 21 1277 2204 125556 30508 2.86466 2.86466 -118.79 -2.86466 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.01591 0.0142043 137 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_059.v common 2.33 vpr 64.59 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29824 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 30 32 278 235 1 150 87 17 17 289 -1 unnamed_device 25.2 MiB 0.61 2187 808 9879 2531 6399 949 64.6 MiB 0.05 0.00 4.30385 3.42675 -104.9 -3.42675 3.42675 0.24 0.000283569 0.000258971 0.0157083 0.0143422 -1 -1 -1 -1 26 2066 25 6.87369e+06 349346 503264. 1741.40 0.40 0.0537143 0.0471404 24322 120374 -1 1867 26 1418 2313 162293 41447 3.43946 3.43946 -116.403 -3.43946 0 0 618332. 2139.56 0.02 0.06 0.07 -1 -1 0.02 0.0217145 0.0191615 104 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_060.v common 5.58 vpr 65.42 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29800 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66992 32 32 431 332 1 239 91 17 17 289 -1 unnamed_device 25.6 MiB 3.74 2820 1401 12535 3692 7672 1171 65.4 MiB 0.08 0.00 6.88686 5.84665 -173.286 -5.84665 5.84665 0.24 0.000419434 0.000387317 0.0280962 0.0259362 -1 -1 -1 -1 32 3289 23 6.87369e+06 377294 586450. 2029.24 0.45 0.0856957 0.0766235 25474 144626 -1 2597 22 1840 2810 199075 44926 4.4923 4.4923 -155.353 -4.4923 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0201657 0.0180183 166 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 4.33 vpr 64.54 MiB -1 -1 0.19 18448 1 0.03 -1 -1 29960 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 24.9 MiB 2.38 2019 1059 12867 3257 7846 1764 64.5 MiB 0.08 0.00 5.26892 4.63938 -140.042 -4.63938 4.63938 0.33 0.000319991 0.000293027 0.0261935 0.0241675 -1 -1 -1 -1 32 2403 25 6.87369e+06 489084 586450. 2029.24 0.40 0.0756114 0.0675688 25474 144626 -1 1978 19 1375 2255 145823 36321 3.5567 3.5567 -129.487 -3.5567 0 0 744469. 2576.02 0.03 0.05 0.09 -1 -1 0.03 0.0171303 0.0153048 135 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_062.v common 2.49 vpr 64.31 MiB -1 -1 0.11 17148 1 0.02 -1 -1 30328 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 25.2 MiB 0.63 1762 855 12512 3348 8365 799 64.3 MiB 0.05 0.00 3.96025 3.6312 -105.59 -3.6312 3.6312 0.24 0.000255426 0.000233116 0.0167194 0.015257 -1 -1 -1 -1 28 1989 22 6.87369e+06 391268 531479. 1839.03 0.34 0.0495916 0.0435939 24610 126494 -1 1736 22 999 1747 115875 28970 2.92726 2.92726 -105.066 -2.92726 0 0 648988. 2245.63 0.04 0.06 0.12 -1 -1 0.04 0.0205974 0.0181628 96 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 4.97 vpr 65.02 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29572 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 349 273 1 191 101 17 17 289 -1 unnamed_device 25.6 MiB 1.72 2736 1219 17491 4613 10519 2359 65.0 MiB 0.10 0.00 6.69567 5.1464 -138.872 -5.1464 5.1464 0.31 0.000341259 0.000311913 0.0305984 0.0281463 -1 -1 -1 -1 26 2928 24 6.87369e+06 517032 503264. 1741.40 1.78 0.151555 0.13355 24322 120374 -1 2550 23 1721 3309 237917 56001 4.68785 4.68785 -144.023 -4.68785 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.017333 0.0153937 145 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 2.60 vpr 64.46 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30196 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 25.2 MiB 0.94 2118 750 9385 2715 5945 725 64.5 MiB 0.05 0.00 4.52145 3.49353 -105.466 -3.49353 3.49353 0.24 0.000265033 0.000242603 0.0146375 0.0133717 -1 -1 -1 -1 32 1967 23 6.87369e+06 293451 586450. 2029.24 0.35 0.0505078 0.0444585 25474 144626 -1 1595 20 1184 2094 130220 31374 2.83596 2.83596 -104.337 -2.83596 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0123439 0.0109405 99 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 4.46 vpr 64.53 MiB -1 -1 0.16 17676 1 0.03 -1 -1 29828 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 30 32 278 235 1 151 96 17 17 289 -1 unnamed_device 25.4 MiB 1.69 2241 719 10608 2312 6839 1457 64.5 MiB 0.07 0.00 4.84748 3.98828 -113.215 -3.98828 3.98828 0.25 0.000391645 0.000367026 0.0289935 0.0271019 -1 -1 -1 -1 28 2331 36 6.87369e+06 475111 531479. 1839.03 1.39 0.12692 0.111488 24610 126494 -1 1678 21 1245 2215 142434 39295 3.33286 3.33286 -116.77 -3.33286 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0160478 0.0141015 109 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 4.89 vpr 65.07 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66632 29 32 355 287 1 200 87 17 17 289 -1 unnamed_device 25.2 MiB 2.10 2696 974 15831 5641 7207 2983 65.1 MiB 0.09 0.00 5.17922 4.15337 -121.297 -4.15337 4.15337 0.24 0.000328376 0.000300502 0.0322937 0.0296945 -1 -1 -1 -1 34 2718 23 6.87369e+06 363320 618332. 2139.56 1.42 0.164397 0.143584 25762 151098 -1 2026 21 1484 2291 146376 37672 3.47616 3.47616 -116.825 -3.47616 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0161593 0.0144132 136 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_067.v common 3.68 vpr 64.94 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29776 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 358 289 1 183 90 17 17 289 -1 unnamed_device 25.0 MiB 1.76 2016 1105 14160 4101 8351 1708 64.9 MiB 0.08 0.00 5.27855 4.41935 -143.334 -4.41935 4.41935 0.24 0.000346002 0.000316456 0.0278664 0.0255617 -1 -1 -1 -1 32 2363 23 6.87369e+06 363320 586450. 2029.24 0.46 0.08495 0.0752392 25474 144626 -1 2046 21 1489 2340 158892 36945 3.6681 3.6681 -134.244 -3.6681 0 0 744469. 2576.02 0.03 0.05 0.16 -1 -1 0.03 0.016676 0.0148494 132 54 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_068.v common 3.76 vpr 65.11 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30160 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 353 285 1 188 93 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2553 1054 11433 3167 7604 662 65.1 MiB 0.07 0.00 5.94852 4.77748 -139.018 -4.77748 4.77748 0.24 0.000334015 0.000305667 0.0198564 0.0181388 -1 -1 -1 -1 32 2558 25 6.87369e+06 405241 586450. 2029.24 0.40 0.0648189 0.0572644 25474 144626 -1 2013 22 1396 2524 151194 37389 3.71836 3.71836 -131.742 -3.71836 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.02815 0.0249344 134 51 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_069.v common 4.73 vpr 64.56 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30160 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66112 32 32 276 237 1 165 82 17 17 289 -1 unnamed_device 24.9 MiB 2.17 1940 852 6668 1493 4863 312 64.6 MiB 0.04 0.00 5.16415 4.88031 -136.568 -4.88031 4.88031 0.33 0.000282263 0.00025852 0.0119638 0.0109757 -1 -1 -1 -1 26 2532 37 6.87369e+06 251529 503264. 1741.40 1.14 0.0984009 0.0854727 24322 120374 -1 1898 19 1074 1463 105865 29212 3.47621 3.47621 -124.999 -3.47621 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.0128064 0.0114271 102 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_070.v common 4.05 vpr 64.92 MiB -1 -1 0.18 18048 1 0.03 -1 -1 30180 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 31 32 319 272 1 176 83 17 17 289 -1 unnamed_device 25.2 MiB 2.04 2174 1028 12503 3213 7830 1460 64.9 MiB 0.07 0.00 4.4732 3.7214 -122.26 -3.7214 3.7214 0.25 0.00040486 0.000356531 0.029162 0.0270087 -1 -1 -1 -1 32 2289 30 6.87369e+06 279477 586450. 2029.24 0.38 0.0734498 0.0653217 25474 144626 -1 1934 22 1164 1724 125099 29725 3.28891 3.28891 -122.449 -3.28891 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0151763 0.0134859 110 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_071.v common 4.41 vpr 64.98 MiB -1 -1 0.18 18436 1 0.03 -1 -1 30304 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66544 30 32 329 273 1 167 96 17 17 289 -1 unnamed_device 25.2 MiB 1.97 2361 965 13236 3751 8252 1233 65.0 MiB 0.07 0.00 4.47245 3.48795 -100.051 -3.48795 3.48795 0.25 0.00036336 0.000336979 0.0214233 0.0195433 -1 -1 -1 -1 30 1999 23 6.87369e+06 475111 556674. 1926.21 1.02 0.112542 0.0980759 25186 138497 -1 1729 16 946 1790 90841 23393 2.93826 2.93826 -100.371 -2.93826 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.0155344 0.0138624 124 57 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_072.v common 3.05 vpr 64.84 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29812 -1 -1 35 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 28 32 277 229 1 156 95 17 17 289 -1 unnamed_device 25.2 MiB 1.29 1945 924 16079 4874 9529 1676 64.8 MiB 0.07 0.00 5.23859 4.10437 -105.39 -4.10437 4.10437 0.25 0.000282598 0.000259458 0.0221159 0.02018 -1 -1 -1 -1 26 2118 21 6.87369e+06 489084 503264. 1741.40 0.47 0.0647093 0.0572097 24322 120374 -1 1838 21 1280 2507 173302 41037 3.6161 3.6161 -108.097 -3.6161 0 0 618332. 2139.56 0.03 0.05 0.06 -1 -1 0.03 0.0148899 0.0133326 117 27 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 5.59 vpr 64.57 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29836 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 30 32 317 269 1 155 80 17 17 289 -1 unnamed_device 24.9 MiB 2.37 2041 784 11088 4549 5689 850 64.6 MiB 0.09 0.00 4.60788 3.85608 -116.241 -3.85608 3.85608 0.26 0.000373926 0.000343506 0.0399959 0.0370619 -1 -1 -1 -1 28 2449 50 6.87369e+06 251529 531479. 1839.03 1.69 0.171036 0.150399 24610 126494 -1 1896 24 1646 2865 221151 58757 3.15776 3.15776 -117.819 -3.15776 0 0 648988. 2245.63 0.02 0.06 0.09 -1 -1 0.02 0.015881 0.0140268 105 63 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 4.14 vpr 65.02 MiB -1 -1 0.15 17916 1 0.03 -1 -1 29628 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 335 282 1 189 84 17 17 289 -1 unnamed_device 25.6 MiB 1.66 2218 967 9966 2748 6633 585 65.0 MiB 0.06 0.00 5.10429 3.99449 -129.503 -3.99449 3.99449 0.25 0.000328462 0.000301649 0.020079 0.0184308 -1 -1 -1 -1 32 2511 25 6.87369e+06 279477 586450. 2029.24 1.09 0.117666 0.102422 25474 144626 -1 2008 18 1211 1757 119685 28936 3.4488 3.4488 -126.894 -3.4488 0 0 744469. 2576.02 0.04 0.06 0.08 -1 -1 0.04 0.023357 0.0207862 118 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_075.v common 3.32 vpr 64.91 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29900 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66468 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.9 MiB 0.79 2036 1158 10170 2450 6680 1040 64.9 MiB 0.06 0.00 5.31102 4.59912 -134.752 -4.59912 4.59912 0.27 0.000342506 0.000316632 0.0162185 0.0148702 -1 -1 -1 -1 32 2499 23 6.87369e+06 461137 586450. 2029.24 1.11 0.129327 0.112575 25474 144626 -1 2100 22 1224 2150 133245 32520 3.6524 3.6524 -124.426 -3.6524 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0168294 0.014975 130 4 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 4.44 vpr 65.12 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29968 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 25.2 MiB 2.45 2819 1040 12178 3350 7228 1600 65.1 MiB 0.09 0.00 5.70484 4.82048 -149.342 -4.82048 4.82048 0.26 0.000400944 0.000372604 0.0283893 0.026235 -1 -1 -1 -1 32 3002 29 6.87369e+06 335372 586450. 2029.24 0.60 0.0908346 0.081116 25474 144626 -1 2195 18 1476 2286 156593 38820 3.90405 3.90405 -139.251 -3.90405 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0148102 0.0132845 141 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 5.94 vpr 65.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30176 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 385 308 1 195 101 17 17 289 -1 unnamed_device 25.6 MiB 3.09 2653 1152 16316 4343 10844 1129 65.1 MiB 0.08 0.00 6.91417 5.25048 -151.042 -5.25048 5.25048 0.24 0.000352849 0.000323511 0.0264732 0.0241542 -1 -1 -1 -1 28 2872 20 6.87369e+06 517032 531479. 1839.03 1.50 0.125407 0.110692 24610 126494 -1 2428 23 1830 3262 241216 56854 3.93035 3.93035 -146.382 -3.93035 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0181598 0.0161266 147 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_078.v common 5.07 vpr 65.23 MiB -1 -1 0.18 18048 1 0.03 -1 -1 30240 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66796 32 32 387 309 1 192 105 17 17 289 -1 unnamed_device 25.2 MiB 2.38 2943 1241 19618 5694 11739 2185 65.2 MiB 0.24 0.00 5.98952 4.52582 -145.898 -4.52582 4.52582 0.24 0.000822808 0.000763121 0.0762442 0.0705218 -1 -1 -1 -1 30 2850 25 6.87369e+06 572927 556674. 1926.21 1.09 0.176382 0.157475 25186 138497 -1 2346 21 1345 2673 179539 40524 3.5128 3.5128 -133.556 -3.5128 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0169879 0.0151336 148 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 3.71 vpr 64.45 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29504 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 30 32 272 232 1 151 80 17 17 289 -1 unnamed_device 24.7 MiB 1.97 2072 788 12808 4627 5785 2396 64.4 MiB 0.06 0.00 4.73318 3.87398 -115.445 -3.87398 3.87398 0.24 0.000270734 0.000246942 0.0216325 0.0197871 -1 -1 -1 -1 32 2109 26 6.87369e+06 251529 586450. 2029.24 0.39 0.0619366 0.0547203 25474 144626 -1 1731 21 1247 2177 152375 36953 2.94096 2.94096 -109.117 -2.94096 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.013509 0.0119628 99 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 5.31 vpr 64.71 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30528 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 30 32 375 299 1 188 85 17 17 289 -1 unnamed_device 25.4 MiB 2.75 2081 1069 9943 2328 6646 969 64.7 MiB 0.07 0.00 5.31292 4.64076 -144.318 -4.64076 4.64076 0.24 0.000345453 0.000316854 0.0247669 0.0228435 -1 -1 -1 -1 26 2497 31 6.87369e+06 321398 503264. 1741.40 1.21 0.124009 0.109075 24322 120374 -1 2213 21 1786 2855 199315 47103 3.8714 3.8714 -142.891 -3.8714 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0221423 0.0198078 137 63 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 4.20 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29864 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 25.7 MiB 1.66 2664 1115 14741 4886 7454 2401 65.1 MiB 0.09 0.00 5.92334 5.22106 -152.202 -5.22106 5.22106 0.25 0.000334817 0.000306968 0.0281764 0.0259055 -1 -1 -1 -1 30 2721 24 6.87369e+06 349346 556674. 1926.21 1.15 0.126827 0.11113 25186 138497 -1 2014 20 1447 2533 138886 35336 3.89246 3.89246 -136.446 -3.89246 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0169656 0.0152085 136 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 4.71 vpr 65.10 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30172 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 31 32 340 275 1 201 93 17 17 289 -1 unnamed_device 25.2 MiB 2.09 2886 1189 10173 2898 6614 661 65.1 MiB 0.06 0.00 6.73744 5.23384 -148.634 -5.23384 5.23384 0.24 0.000333069 0.000305994 0.0175158 0.0160644 -1 -1 -1 -1 26 2895 35 6.87369e+06 419215 503264. 1741.40 1.31 0.132751 0.11687 24322 120374 -1 2483 26 1948 3189 213646 52192 4.5628 4.5628 -152.603 -4.5628 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0183985 0.0163074 139 47 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_083.v common 4.67 vpr 64.75 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30524 -1 -1 31 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 30 32 377 310 1 181 93 17 17 289 -1 unnamed_device 25.3 MiB 2.60 2449 1224 16893 5635 9042 2216 64.7 MiB 0.12 0.00 5.39266 4.94818 -149.82 -4.94818 4.94818 0.25 0.000344756 0.000315816 0.0388335 0.0359078 -1 -1 -1 -1 28 2735 20 6.87369e+06 433189 531479. 1839.03 0.59 0.0915719 0.0819831 24610 126494 -1 2284 25 1446 2485 237805 83948 3.50651 3.50651 -131.776 -3.50651 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0187101 0.0165963 136 83 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 4.69 vpr 64.62 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30168 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 32 32 365 294 1 187 86 17 17 289 -1 unnamed_device 24.9 MiB 2.10 2716 990 11993 3472 6935 1586 64.6 MiB 0.08 0.00 5.90348 4.77578 -139.992 -4.77578 4.77578 0.24 0.000817076 0.000762471 0.0254697 0.0234016 -1 -1 -1 -1 32 2722 28 6.87369e+06 307425 586450. 2029.24 1.25 0.143023 0.125248 25474 144626 -1 2150 18 1396 2412 167928 39620 4.02096 4.02096 -141.443 -4.02096 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0148475 0.0133072 131 57 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 4.17 vpr 64.65 MiB -1 -1 0.20 18056 1 0.03 -1 -1 30008 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 29 32 378 310 1 179 90 17 17 289 -1 unnamed_device 25.2 MiB 1.85 2351 942 10944 2964 7013 967 64.7 MiB 0.08 0.00 5.07613 4.09163 -121.097 -4.09163 4.09163 0.24 0.000344576 0.000316288 0.0268546 0.0247877 -1 -1 -1 -1 30 2041 24 6.87369e+06 405241 556674. 1926.21 0.83 0.118594 0.104208 25186 138497 -1 1616 20 1131 1865 97938 24518 2.87521 2.87521 -106.946 -2.87521 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0165374 0.0147987 132 85 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.34 vpr 64.44 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29956 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 24.9 MiB 0.87 1905 855 8448 2270 5828 350 64.4 MiB 0.07 0.00 4.48878 3.94428 -118.381 -3.94428 3.94428 0.35 0.000389992 0.000357049 0.0201422 0.0184089 -1 -1 -1 -1 30 1821 20 6.87369e+06 251529 556674. 1926.21 1.08 0.110404 0.0961912 25186 138497 -1 1536 18 722 1020 59686 14633 2.76086 2.76086 -104.224 -2.76086 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0114509 0.0102269 96 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_087.v common 5.58 vpr 64.67 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29576 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 32 32 373 302 1 184 98 17 17 289 -1 unnamed_device 25.2 MiB 3.81 2454 1140 11348 2927 7443 978 64.7 MiB 0.06 0.00 5.90822 4.62608 -141.402 -4.62608 4.62608 0.24 0.000359269 0.000329782 0.0201378 0.0184997 -1 -1 -1 -1 32 2643 23 6.87369e+06 475111 586450. 2029.24 0.39 0.0672069 0.0596834 25474 144626 -1 2128 20 1410 2389 151377 37388 3.7954 3.7954 -133.896 -3.7954 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0158466 0.0141663 138 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_088.v common 5.61 vpr 65.12 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30108 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 32 32 397 314 1 197 86 17 17 289 -1 unnamed_device 25.2 MiB 3.49 2187 1055 13694 4095 7104 2495 65.1 MiB 0.10 0.00 5.30372 4.6886 -155.532 -4.6886 4.6886 0.25 0.000362587 0.000331007 0.0357278 0.0329807 -1 -1 -1 -1 32 2864 30 6.87369e+06 307425 586450. 2029.24 0.68 0.12507 0.112141 25474 144626 -1 2190 22 1874 3084 201524 49363 3.9064 3.9064 -149.446 -3.9064 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0279863 0.0250155 142 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_089.v common 4.77 vpr 64.04 MiB -1 -1 0.18 17912 1 0.03 -1 -1 30160 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65576 32 32 269 231 1 170 81 17 17 289 -1 unnamed_device 24.9 MiB 2.01 2026 911 13031 5411 7150 470 64.0 MiB 0.06 0.00 4.68123 4.08363 -117.144 -4.08363 4.08363 0.25 0.000275146 0.000251503 0.021986 0.0201273 -1 -1 -1 -1 32 2111 22 6.87369e+06 237555 586450. 2029.24 1.33 0.11397 0.0992625 25474 144626 -1 1780 20 1174 1591 109623 27308 2.93201 2.93201 -108.593 -2.93201 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0129851 0.0115452 102 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_090.v common 3.15 vpr 64.46 MiB -1 -1 0.12 17676 1 0.02 -1 -1 30324 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 245 205 1 153 85 17 17 289 -1 unnamed_device 25.2 MiB 0.92 2028 920 14407 4467 8027 1913 64.5 MiB 0.09 0.00 4.79248 4.04068 -118.574 -4.04068 4.04068 0.26 0.000267498 0.000244558 0.0312119 0.0289087 -1 -1 -1 -1 28 2103 24 6.87369e+06 307425 531479. 1839.03 0.89 0.116531 0.102508 24610 126494 -1 1895 20 1292 2098 141548 34713 3.03526 3.03526 -115.93 -3.03526 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.012172 0.0107774 100 4 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 4.52 vpr 65.07 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30384 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 25.2 MiB 2.04 2676 1170 8083 1952 5562 569 65.1 MiB 0.06 0.00 5.61368 4.75448 -152.304 -4.75448 4.75448 0.24 0.000340485 0.000312452 0.0175897 0.0162244 -1 -1 -1 -1 28 3115 23 6.87369e+06 335372 531479. 1839.03 1.17 0.121612 0.106252 24610 126494 -1 2580 22 2029 2754 244375 55049 4.10006 4.10006 -153.878 -4.10006 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0170113 0.0151164 141 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_092.v common 4.74 vpr 64.53 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29860 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 356 289 1 201 92 17 17 289 -1 unnamed_device 25.2 MiB 2.09 2208 1201 15203 4959 7948 2296 64.5 MiB 0.09 0.00 6.10904 5.2802 -157.375 -5.2802 5.2802 0.26 0.000329459 0.000300811 0.0303446 0.0279453 -1 -1 -1 -1 32 2749 23 6.87369e+06 391268 586450. 2029.24 1.11 0.143611 0.125949 25474 144626 -1 2240 21 1434 2171 140842 33587 4.39535 4.39535 -145.45 -4.39535 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0163683 0.0146225 137 56 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_093.v common 3.58 vpr 65.16 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30184 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66724 32 32 349 260 1 204 101 17 17 289 -1 unnamed_device 25.1 MiB 0.59 2787 1264 13966 4175 8662 1129 65.2 MiB 0.09 0.00 6.34944 5.29707 -150.39 -5.29707 5.29707 0.25 0.000641819 0.000586368 0.0256625 0.023543 -1 -1 -1 -1 26 3191 27 6.87369e+06 517032 503264. 1741.40 1.55 0.15078 0.133588 24322 120374 -1 2699 24 1873 3447 292705 65551 4.85515 4.85515 -153.959 -4.85515 0 0 618332. 2139.56 0.02 0.07 0.06 -1 -1 0.02 0.018655 0.0166398 158 3 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_094.v common 4.68 vpr 64.82 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29784 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 30 32 316 264 1 165 96 17 17 289 -1 unnamed_device 25.2 MiB 1.81 2174 784 9732 2367 5855 1510 64.8 MiB 0.06 0.00 4.46215 3.60295 -103.566 -3.60295 3.60295 0.24 0.000311867 0.000285473 0.019448 0.0179445 -1 -1 -1 -1 28 2361 29 6.87369e+06 475111 531479. 1839.03 1.46 0.120329 0.105955 24610 126494 -1 1792 22 1436 2513 178226 45465 3.17456 3.17456 -108.253 -3.17456 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0176424 0.0156828 119 52 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_095.v common 3.21 vpr 64.41 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30544 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65956 27 32 255 219 1 139 82 17 17 289 -1 unnamed_device 25.2 MiB 0.82 1612 787 10050 2715 6635 700 64.4 MiB 0.12 0.00 4.33505 3.47585 -98.4683 -3.47585 3.47585 0.24 0.000838006 0.000776448 0.0486502 0.0453067 -1 -1 -1 -1 32 1635 26 6.87369e+06 321398 586450. 2029.24 1.00 0.129214 0.114695 25474 144626 -1 1333 20 839 1234 78424 18728 2.61836 2.61836 -92.7343 -2.61836 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0122542 0.0108438 97 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 6.04 vpr 64.92 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30156 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 421 327 1 233 90 17 17 289 -1 unnamed_device 25.2 MiB 2.48 2919 1374 16371 4730 9445 2196 64.9 MiB 0.15 0.00 5.11591 4.4536 -142.768 -4.4536 4.4536 0.25 0.000385467 0.000353596 0.0502962 0.0461038 -1 -1 -1 -1 28 3929 41 6.87369e+06 363320 531479. 1839.03 2.06 0.199677 0.176685 24610 126494 -1 3169 20 2039 3316 292745 68186 4.14656 4.14656 -145.254 -4.14656 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0200713 0.0178199 162 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_097.v common 7.52 vpr 63.80 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29888 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65336 31 32 365 296 1 202 86 17 17 289 -1 unnamed_device 24.5 MiB 4.65 2567 1117 15395 4375 9100 1920 63.8 MiB 0.14 0.00 6.54132 5.50252 -165.378 -5.50252 5.50252 0.35 0.00094304 0.000877411 0.0550549 0.0509965 -1 -1 -1 -1 32 2527 22 6.87369e+06 321398 586450. 2029.24 1.17 0.172222 0.152753 25474 144626 -1 2171 20 1502 2393 131573 34068 4.315 4.315 -149.599 -4.315 0 0 744469. 2576.02 0.03 0.05 0.16 -1 -1 0.03 0.0215759 0.0193293 137 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_098.v common 6.32 vpr 64.46 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29900 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 331 280 1 185 84 17 17 289 -1 unnamed_device 24.9 MiB 3.54 2356 848 11247 3613 5403 2231 64.5 MiB 0.06 0.00 6.05365 4.34735 -140.957 -4.34735 4.34735 0.25 0.000314113 0.000285916 0.0209042 0.0191109 -1 -1 -1 -1 36 2307 30 6.87369e+06 279477 648988. 2245.63 1.38 0.125955 0.109635 26050 158493 -1 1710 21 1244 1786 130702 34809 3.71381 3.71381 -135.737 -3.71381 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0151241 0.0134502 115 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_099.v common 3.64 vpr 64.93 MiB -1 -1 0.13 18300 1 0.03 -1 -1 29928 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 326 263 1 176 97 17 17 289 -1 unnamed_device 25.2 MiB 1.05 2500 991 17191 5469 8763 2959 64.9 MiB 0.09 0.00 6.23855 4.94131 -133.771 -4.94131 4.94131 0.25 0.000319217 0.000287453 0.0282491 0.0257815 -1 -1 -1 -1 32 2541 23 6.87369e+06 461137 586450. 2029.24 1.16 0.135339 0.118369 25474 144626 -1 1967 20 1134 1814 128657 30637 3.5348 3.5348 -122.778 -3.5348 0 0 744469. 2576.02 0.03 0.04 0.11 -1 -1 0.03 0.0146995 0.0130737 129 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_100.v common 4.05 vpr 65.20 MiB -1 -1 0.19 18444 1 0.03 -1 -1 29872 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66764 31 32 373 294 1 197 97 17 17 289 -1 unnamed_device 25.2 MiB 1.63 2375 1162 12529 3039 8249 1241 65.2 MiB 0.07 0.00 5.24822 4.52085 -131.628 -4.52085 4.52085 0.24 0.000358061 0.000328139 0.0216078 0.0197952 -1 -1 -1 -1 32 2575 27 6.87369e+06 475111 586450. 2029.24 0.97 0.118535 0.103282 25474 144626 -1 2191 21 1428 2414 145484 35797 3.60116 3.60116 -127.313 -3.60116 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.016991 0.0151674 149 50 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_101.v common 3.92 vpr 64.44 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29836 -1 -1 31 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 30 32 325 268 1 172 93 17 17 289 -1 unnamed_device 24.8 MiB 2.07 2526 942 15843 4746 8425 2672 64.4 MiB 0.09 0.00 4.42088 3.6935 -105.372 -3.6935 3.6935 0.24 0.000305767 0.000279253 0.0263327 0.0240824 -1 -1 -1 -1 32 2304 24 6.87369e+06 433189 586450. 2029.24 0.37 0.0677758 0.060063 25474 144626 -1 1855 23 1310 2247 143307 35215 3.26111 3.26111 -104.441 -3.26111 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0191546 0.0170659 124 51 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_102.v common 5.92 vpr 65.10 MiB -1 -1 0.11 18440 1 0.03 -1 -1 29800 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 25.2 MiB 2.99 2913 1092 15883 6638 8299 946 65.1 MiB 0.09 0.00 5.80498 4.83838 -151.498 -4.83838 4.83838 0.24 0.00033385 0.00030469 0.0295813 0.0270307 -1 -1 -1 -1 36 3177 26 6.87369e+06 335372 648988. 2245.63 1.54 0.148107 0.129932 26050 158493 -1 2412 24 2420 3761 269815 66337 4.18536 4.18536 -142.06 -4.18536 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0188696 0.0167907 143 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 4.43 vpr 65.22 MiB -1 -1 0.20 18056 1 0.03 -1 -1 29788 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 32 32 386 307 1 196 100 17 17 289 -1 unnamed_device 25.2 MiB 2.49 2629 1181 18660 5371 11070 2219 65.2 MiB 0.11 0.00 5.00583 4.14663 -139.408 -4.14663 4.14663 0.26 0.000357344 0.000326842 0.0340144 0.0312299 -1 -1 -1 -1 28 2725 24 6.87369e+06 503058 531479. 1839.03 0.46 0.0869383 0.0774914 24610 126494 -1 2433 22 1625 2600 177794 43230 3.30791 3.30791 -131.404 -3.30791 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0177087 0.0157872 148 62 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 3.83 vpr 64.40 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29796 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 29 32 269 229 1 150 80 17 17 289 -1 unnamed_device 24.9 MiB 1.50 1800 855 13152 3903 8012 1237 64.4 MiB 0.06 0.00 4.51078 3.96392 -119.802 -3.96392 3.96392 0.26 0.000278562 0.000250763 0.0228269 0.0208948 -1 -1 -1 -1 28 1573 21 6.87369e+06 265503 531479. 1839.03 0.84 0.102535 0.089372 24610 126494 -1 1449 18 1081 1538 90664 22450 2.84596 2.84596 -105.452 -2.84596 0 0 648988. 2245.63 0.04 0.05 0.12 -1 -1 0.04 0.0194379 0.0172703 101 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 3.61 vpr 64.89 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29720 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66452 32 32 310 266 1 175 84 17 17 289 -1 unnamed_device 24.9 MiB 1.23 1945 989 10881 3547 5830 1504 64.9 MiB 0.06 0.00 4.46846 3.96726 -124.286 -3.96726 3.96726 0.26 0.000539246 0.000491191 0.0218895 0.020114 -1 -1 -1 -1 32 2199 21 6.87369e+06 279477 586450. 2029.24 1.07 0.120443 0.104867 25474 144626 -1 1917 19 1282 1770 134180 30773 3.22347 3.22347 -121.937 -3.22347 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0136307 0.0121427 109 58 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 3.23 vpr 64.45 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30288 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 24.8 MiB 1.16 2369 985 12716 3543 8146 1027 64.4 MiB 0.07 0.00 5.82022 4.63448 -129.081 -4.63448 4.63448 0.25 0.000313758 0.00028752 0.0185202 0.0168858 -1 -1 -1 -1 26 2817 33 6.87369e+06 544980 503264. 1741.40 0.75 0.0722394 0.063921 24322 120374 -1 2199 25 1679 3103 232332 55175 4.5252 4.5252 -139.616 -4.5252 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0171975 0.0152355 135 33 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 3.73 vpr 64.02 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30200 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65560 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.9 MiB 1.93 2013 868 12143 3086 7739 1318 64.0 MiB 0.07 0.00 5.50062 4.39082 -119.863 -4.39082 4.39082 0.26 0.000638417 0.000596436 0.0244094 0.0224743 -1 -1 -1 -1 26 2317 25 6.87369e+06 307425 503264. 1741.40 0.40 0.0704772 0.0627406 24322 120374 -1 1903 21 1304 1681 120177 29907 3.4928 3.4928 -115.033 -3.4928 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.0130638 0.0115815 104 31 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 4.93 vpr 64.00 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30192 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65532 32 32 278 238 1 158 80 17 17 289 -1 unnamed_device 24.9 MiB 2.65 2071 908 11604 3546 6151 1907 64.0 MiB 0.06 0.00 4.62988 3.89598 -123.598 -3.89598 3.89598 0.24 0.00027488 0.00025107 0.0199843 0.0182973 -1 -1 -1 -1 32 2061 26 6.87369e+06 223581 586450. 2029.24 0.99 0.101454 0.0882131 25474 144626 -1 1820 19 1201 2020 146655 33744 2.79301 2.79301 -110.871 -2.79301 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0126783 0.0112607 101 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 4.03 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 31 32 373 300 1 185 100 17 17 289 -1 unnamed_device 25.2 MiB 2.20 2655 991 12396 3296 8295 805 65.0 MiB 0.12 0.00 4.74418 3.88072 -123.81 -3.88072 3.88072 0.24 0.00100784 0.000938791 0.0351059 0.0323701 -1 -1 -1 -1 30 2157 23 6.87369e+06 517032 556674. 1926.21 0.44 0.0812104 0.0724896 25186 138497 -1 1772 22 1406 2370 128493 31312 2.87096 2.87096 -113.357 -2.87096 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.0170484 0.0151613 141 64 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 4.53 vpr 64.52 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30204 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 31 32 265 230 1 169 82 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2006 938 8270 2331 5442 497 64.5 MiB 0.04 0.00 4.2629 3.6763 -117.183 -3.6763 3.6763 0.25 0.00027393 0.000251177 0.0138467 0.0127085 -1 -1 -1 -1 26 2515 27 6.87369e+06 265503 503264. 1741.40 1.38 0.113204 0.0989182 24322 120374 -1 2077 22 1426 2063 144088 35253 3.24491 3.24491 -120.554 -3.24491 0 0 618332. 2139.56 0.02 0.05 0.07 -1 -1 0.02 0.017819 0.0156637 100 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 4.78 vpr 65.08 MiB -1 -1 0.16 18440 1 0.03 -1 -1 29780 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66640 32 32 349 286 1 177 96 17 17 289 -1 unnamed_device 25.0 MiB 2.22 2443 1058 16740 5363 9029 2348 65.1 MiB 0.09 0.00 4.43988 3.7125 -116.005 -3.7125 3.7125 0.26 0.000330638 0.000302394 0.0297324 0.0273204 -1 -1 -1 -1 32 2537 48 6.87369e+06 447163 586450. 2029.24 1.13 0.162075 0.142002 25474 144626 -1 1979 19 985 1660 107053 25693 3.14681 3.14681 -112.185 -3.14681 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0153245 0.0136416 130 57 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 4.16 vpr 64.70 MiB -1 -1 0.15 18060 1 0.03 -1 -1 29768 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 31 32 396 325 1 183 94 17 17 289 -1 unnamed_device 25.2 MiB 2.39 2295 980 16282 5415 8151 2716 64.7 MiB 0.09 0.00 4.1365 3.7606 -126.341 -3.7606 3.7606 0.24 0.000372826 0.000341745 0.0318259 0.0293245 -1 -1 -1 -1 32 2275 22 6.87369e+06 433189 586450. 2029.24 0.38 0.0785981 0.0701866 25474 144626 -1 1857 22 1574 2432 136184 34381 3.09951 3.09951 -122.264 -3.09951 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.017615 0.0156661 136 91 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 4.02 vpr 64.45 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29760 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 303 262 1 154 82 17 17 289 -1 unnamed_device 24.9 MiB 1.70 1892 948 13610 3927 7739 1944 64.5 MiB 0.06 0.00 4.21775 3.46595 -110.85 -3.46595 3.46595 0.25 0.000291981 0.000266784 0.023879 0.0218333 -1 -1 -1 -1 28 2163 25 6.87369e+06 251529 531479. 1839.03 0.99 0.110338 0.0961183 24610 126494 -1 1875 22 1244 1995 152174 36647 2.85796 2.85796 -109.463 -2.85796 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0145337 0.0128796 100 57 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 4.14 vpr 64.85 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30164 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66408 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.9 MiB 1.43 2269 846 15023 5112 7105 2806 64.9 MiB 0.07 0.00 5.53062 4.43872 -133.042 -4.43872 4.43872 0.24 0.000284962 0.000260591 0.0256698 0.023447 -1 -1 -1 -1 34 2491 31 6.87369e+06 265503 618332. 2139.56 1.18 0.131504 0.114323 25762 151098 -1 1812 20 1302 1953 138182 35210 3.43421 3.43421 -119.565 -3.43421 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0182939 0.0160101 110 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 4.58 vpr 64.35 MiB -1 -1 0.11 18300 1 0.03 -1 -1 30164 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 318 257 1 196 86 17 17 289 -1 unnamed_device 25.2 MiB 1.82 2163 1060 11048 3713 5060 2275 64.3 MiB 0.06 0.00 5.70718 4.76478 -133.796 -4.76478 4.76478 0.24 0.000307552 0.000280889 0.0197149 0.0180596 -1 -1 -1 -1 30 2427 22 6.87369e+06 307425 556674. 1926.21 1.43 0.157271 0.137375 25186 138497 -1 2020 20 1254 1731 101663 25086 3.76346 3.76346 -131.36 -3.76346 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0152417 0.0136094 128 30 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 3.95 vpr 64.96 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29816 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 24.9 MiB 2.06 2255 990 10140 2558 6775 807 65.0 MiB 0.07 0.00 4.47163 4.11363 -115.607 -4.11363 4.11363 0.40 0.000313842 0.00028706 0.0212981 0.0195614 -1 -1 -1 -1 30 2125 26 6.87369e+06 405241 556674. 1926.21 0.38 0.0666518 0.0590345 25186 138497 -1 1706 22 856 1609 88635 21834 3.01151 3.01151 -103.493 -3.01151 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0154263 0.0137196 123 55 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 5.65 vpr 65.12 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 393 312 1 215 88 17 17 289 -1 unnamed_device 25.6 MiB 2.55 2550 1006 14713 4986 7296 2431 65.1 MiB 0.09 0.00 5.75531 5.22906 -161.966 -5.22906 5.22906 0.24 0.000362547 0.00033201 0.0299732 0.0274495 -1 -1 -1 -1 34 2714 38 6.87369e+06 335372 618332. 2139.56 1.66 0.174151 0.152107 25762 151098 -1 2202 24 1965 3055 205816 51673 4.28506 4.28506 -150.228 -4.28506 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0195635 0.0173908 148 65 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 3.35 vpr 64.40 MiB -1 -1 0.21 17676 1 0.02 -1 -1 30044 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 24.9 MiB 1.02 1779 625 4631 866 3215 550 64.4 MiB 0.02 0.00 4.01225 3.52895 -101.476 -3.52895 3.52895 0.26 0.000250149 0.000229138 0.00776917 0.00714495 -1 -1 -1 -1 30 1639 23 6.87369e+06 251529 556674. 1926.21 0.93 0.0804275 0.069412 25186 138497 -1 1219 21 737 1159 53687 15362 3.04656 3.04656 -101.409 -3.04656 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0147543 0.0131178 93 4 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 5.06 vpr 65.28 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30124 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 412 334 1 194 99 17 17 289 -1 unnamed_device 25.2 MiB 1.54 2354 1015 18111 5950 8835 3326 65.3 MiB 0.09 0.00 5.55115 4.44135 -143.231 -4.44135 4.44135 0.24 0.00037324 0.000341662 0.0311831 0.0284679 -1 -1 -1 -1 36 2533 50 6.87369e+06 489084 648988. 2245.63 2.14 0.218208 0.192077 26050 158493 -1 2040 21 1539 2249 177726 45330 3.99296 3.99296 -143.127 -3.99296 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0185306 0.0165275 145 90 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 5.27 vpr 64.52 MiB -1 -1 0.12 18300 1 0.03 -1 -1 30220 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 376 318 1 168 82 17 17 289 -1 unnamed_device 25.2 MiB 3.41 2123 865 10762 4115 4722 1925 64.5 MiB 0.07 0.00 4.47325 3.59615 -127.488 -3.59615 3.59615 0.25 0.000337104 0.000308034 0.0274738 0.0253226 -1 -1 -1 -1 32 2183 25 6.87369e+06 251529 586450. 2029.24 0.40 0.0761496 0.0673204 25474 144626 -1 1767 22 1484 2215 152133 36159 3.15446 3.15446 -127.944 -3.15446 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0171901 0.0152467 114 96 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 4.62 vpr 64.23 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 360 293 1 182 97 17 17 289 -1 unnamed_device 24.9 MiB 2.31 2242 1134 8533 1953 5707 873 64.2 MiB 0.09 0.00 4.26762 4.14663 -128.445 -4.14663 4.14663 0.30 0.000656918 0.000603764 0.0275667 0.025307 -1 -1 -1 -1 28 2384 22 6.87369e+06 461137 531479. 1839.03 0.80 0.104875 0.092177 24610 126494 -1 2150 21 1079 1675 108833 27521 3.38591 3.38591 -122.541 -3.38591 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0280771 0.0250376 134 60 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_122.v common 5.89 vpr 65.18 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29804 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66748 32 32 396 299 1 240 91 17 17 289 -1 unnamed_device 25.6 MiB 3.34 2861 1325 10699 2829 6710 1160 65.2 MiB 0.08 0.00 6.83115 5.96543 -180.924 -5.96543 5.96543 0.25 0.000377616 0.000346769 0.0221869 0.020377 -1 -1 -1 -1 30 3159 21 6.87369e+06 377294 556674. 1926.21 1.15 0.128384 0.113301 25186 138497 -1 2486 20 1783 2650 160621 38650 4.9295 4.9295 -162.971 -4.9295 0 0 706193. 2443.58 0.03 0.05 0.09 -1 -1 0.03 0.0179893 0.0161715 166 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_123.v common 3.42 vpr 64.37 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29608 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 30 32 224 207 1 137 79 17 17 289 -1 unnamed_device 25.2 MiB 1.16 1796 583 12754 5340 6497 917 64.4 MiB 0.05 0.00 3.69857 3.16961 -92.7187 -3.16961 3.16961 0.24 0.000234624 0.000214291 0.0192412 0.0176121 -1 -1 -1 -1 30 1782 28 6.87369e+06 237555 556674. 1926.21 1.00 0.0855611 0.0741408 25186 138497 -1 1269 16 770 993 68728 19715 2.63001 2.63001 -90.3813 -2.63001 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0115953 0.0103417 78 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_124.v common 2.65 vpr 64.55 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29832 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66104 30 32 286 239 1 151 83 17 17 289 -1 unnamed_device 24.9 MiB 0.84 1770 758 12863 4724 6383 1756 64.6 MiB 0.06 0.00 4.46678 3.90824 -117.819 -3.90824 3.90824 0.24 0.000282976 0.000258279 0.0218206 0.0199412 -1 -1 -1 -1 32 1677 18 6.87369e+06 293451 586450. 2029.24 0.39 0.0704146 0.0621642 25474 144626 -1 1359 23 1013 1508 94997 23267 2.89296 2.89296 -107.7 -2.89296 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0242749 0.0214518 106 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 2.82 vpr 64.59 MiB -1 -1 0.15 18056 1 0.02 -1 -1 30148 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 296 247 1 158 81 17 17 289 -1 unnamed_device 25.4 MiB 1.05 2174 940 13381 4853 6305 2223 64.6 MiB 0.07 0.00 4.05625 3.42975 -116.374 -3.42975 3.42975 0.24 0.000299088 0.000273989 0.024265 0.0222129 -1 -1 -1 -1 30 2272 22 6.87369e+06 237555 556674. 1926.21 0.41 0.0633576 0.0560039 25186 138497 -1 1909 22 1221 2293 143256 34040 2.85696 2.85696 -116.827 -2.85696 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0147316 0.0130541 106 34 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_126.v common 3.03 vpr 64.39 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29888 -1 -1 29 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 25 32 216 194 1 123 86 17 17 289 -1 unnamed_device 24.9 MiB 0.63 1478 521 12938 4434 5564 2940 64.4 MiB 0.05 0.00 4.10455 3.48943 -81.0717 -3.48943 3.48943 0.24 0.000223717 0.000203889 0.0164858 0.015004 -1 -1 -1 -1 30 1629 41 6.87369e+06 405241 556674. 1926.21 1.12 0.0952124 0.0819646 25186 138497 -1 1166 19 766 1360 77787 20476 2.73796 2.73796 -77.5522 -2.73796 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0101821 0.0089722 87 29 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_127.v common 3.81 vpr 65.07 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30176 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 32 32 376 307 1 192 86 17 17 289 -1 unnamed_device 25.2 MiB 1.93 2245 1110 15017 5165 7384 2468 65.1 MiB 0.09 0.00 5.02315 4.32635 -130.464 -4.32635 4.32635 0.25 0.000345488 0.000315825 0.0292868 0.026788 -1 -1 -1 -1 32 2752 22 6.87369e+06 307425 586450. 2029.24 0.39 0.0749442 0.0663177 25474 144626 -1 2132 20 1326 2357 146716 35875 3.49806 3.49806 -125.919 -3.49806 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0162152 0.0144597 131 72 -1 -1 -1 -1 +fixed_k6_frac_ripple_N8_22nm.xml mult_128.v common 4.21 vpr 64.78 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29828 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 409 331 1 193 97 17 17 289 -1 unnamed_device 25.2 MiB 2.25 2417 956 9199 2038 6732 429 64.8 MiB 0.06 0.00 4.74423 4.19189 -134.468 -4.19189 4.19189 0.25 0.000365815 0.000335309 0.016995 0.0155775 -1 -1 -1 -1 32 2555 23 6.87369e+06 475111 586450. 2029.24 0.40 0.0696073 0.0613481 25474 144626 -1 1959 21 1593 2492 151905 37256 3.18561 3.18561 -123.559 -3.18561 0 0 744469. 2576.02 0.04 0.08 0.13 -1 -1 0.04 0.0315952 0.0282545 145 90 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_001.v common 4.16 vpr 64.96 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29412 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66516 32 32 354 285 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2668 1268 14562 3744 8579 2239 65.0 MiB 0.09 0.00 6.46147 5.42478 -161.939 -5.42478 5.42478 0.27 0.000354138 0.000325872 0.0286551 0.0264431 -1 -1 -1 -1 28 3093 28 6.89349e+06 366440 531479. 1839.03 1.39 0.149217 0.131137 24610 126494 -1 2624 19 1777 2523 168314 41073 4.42749 4.42749 -154.329 -4.42749 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0180098 0.0159135 146 50 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_002.v common 3.13 vpr 64.73 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29756 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 30 32 363 293 1 229 89 17 17 289 -1 unnamed_device 25.0 MiB 1.18 2791 1263 14939 4998 7127 2814 64.7 MiB 0.08 0.00 6.19428 4.98048 -150.88 -4.98048 4.98048 0.25 0.000332168 0.000303056 0.0271095 0.0247833 -1 -1 -1 -1 32 3445 31 6.89349e+06 380534 586450. 2029.24 0.56 0.0865076 0.0767831 25474 144626 -1 2439 21 1808 2625 186782 45091 4.32429 4.32429 -146.227 -4.32429 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164687 0.014674 152 63 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_003.v common 3.92 vpr 63.83 MiB -1 -1 0.16 18060 1 0.03 -1 -1 29808 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65360 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 24.6 MiB 1.12 2478 1102 14965 5131 8043 1791 63.8 MiB 0.10 0.00 5.35819 4.28675 -123.145 -4.28675 4.28675 0.26 0.000327491 0.000280328 0.0326438 0.0301867 -1 -1 -1 -1 38 2116 21 6.89349e+06 295971 678818. 2348.85 1.23 0.129476 0.113859 26626 170182 -1 1908 22 1051 1471 95425 22642 3.6203 3.6203 -116.676 -3.6203 0 0 902133. 3121.57 0.05 0.05 0.14 -1 -1 0.05 0.0196229 0.0174739 119 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_004.v common 3.21 vpr 64.77 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29748 -1 -1 27 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 29 32 308 248 1 195 88 17 17 289 -1 unnamed_device 24.9 MiB 0.81 2689 1112 15493 4685 9183 1625 64.8 MiB 0.08 0.00 6.19768 4.85518 -132.85 -4.85518 4.85518 0.24 0.000305043 0.000279294 0.0254061 0.0232564 -1 -1 -1 -1 32 2525 37 6.89349e+06 380534 586450. 2029.24 1.02 0.125355 0.10906 25474 144626 -1 2095 21 1267 2022 127854 30529 3.81286 3.81286 -122.541 -3.81286 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145113 0.0128994 130 31 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_005.v common 3.38 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29824 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66416 32 32 336 268 1 211 89 17 17 289 -1 unnamed_device 24.8 MiB 1.44 2799 1150 14741 4806 7062 2873 64.9 MiB 0.09 0.00 6.91451 5.19194 -150.686 -5.19194 5.19194 0.24 0.000325479 0.000297988 0.0258125 0.023632 -1 -1 -1 -1 32 3393 21 6.89349e+06 352346 586450. 2029.24 0.46 0.0685243 0.0608933 25474 144626 -1 2453 20 1763 3114 214478 51266 4.54675 4.54675 -150.299 -4.54675 0 0 744469. 2576.02 0.04 0.08 0.11 -1 -1 0.04 0.0249649 0.022335 141 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_006.v common 3.78 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29780 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 366 295 1 231 99 17 17 289 -1 unnamed_device 25.2 MiB 1.70 2831 1275 17883 5747 9425 2711 64.6 MiB 0.12 0.00 4.85631 3.97606 -129.432 -3.97606 3.97606 0.26 0.000347219 0.000318231 0.0368098 0.0340006 -1 -1 -1 -1 32 3207 27 6.89349e+06 493284 586450. 2029.24 0.65 0.101339 0.0899346 25474 144626 -1 2564 21 1683 2745 172590 41903 3.49866 3.49866 -125.251 -3.49866 0 0 744469. 2576.02 0.03 0.06 0.09 -1 -1 0.03 0.0203705 0.0179603 156 58 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_007.v common 2.73 vpr 63.64 MiB -1 -1 0.17 17672 1 0.03 -1 -1 30152 -1 -1 22 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65168 27 32 259 221 1 159 81 17 17 289 -1 unnamed_device 24.1 MiB 0.88 1787 834 12681 4344 6184 2153 63.6 MiB 0.06 0.00 4.91933 4.22379 -114.63 -4.22379 4.22379 0.25 0.000258176 0.000236283 0.020121 0.018441 -1 -1 -1 -1 32 1839 34 6.89349e+06 310065 586450. 2029.24 0.42 0.0705179 0.0621317 25474 144626 -1 1480 21 1046 1586 115082 27270 3.11381 3.11381 -103.863 -3.11381 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.013738 0.0122335 104 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 2.98 vpr 64.40 MiB -1 -1 0.16 17672 1 0.03 -1 -1 29836 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 31 32 271 219 1 164 96 17 17 289 -1 unnamed_device 24.8 MiB 0.58 2064 1021 15426 4233 9006 2187 64.4 MiB 0.08 0.00 4.0124 3.39815 -103.342 -3.39815 3.39815 0.25 0.000304464 0.000279784 0.0290524 0.0266819 -1 -1 -1 -1 32 2265 19 6.89349e+06 465097 586450. 2029.24 0.99 0.12256 0.107042 25474 144626 -1 1863 19 982 1779 108256 26071 2.49221 2.49221 -95.7819 -2.49221 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0130806 0.0116211 119 4 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_009.v common 3.56 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29764 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 317 271 1 207 86 17 17 289 -1 unnamed_device 24.9 MiB 1.03 2257 970 6512 1373 4783 356 64.8 MiB 0.04 0.00 4.58785 3.71075 -120.491 -3.71075 3.71075 0.26 0.000307831 0.000282316 0.0119944 0.0109864 -1 -1 -1 -1 30 2557 25 6.89349e+06 324158 556674. 1926.21 1.21 0.11422 0.0990295 25186 138497 -1 1893 22 1510 2075 128297 33350 3.17321 3.17321 -122.163 -3.17321 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0153599 0.013634 125 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_010.v common 3.21 vpr 64.44 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29780 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 32 32 298 248 1 185 83 17 17 289 -1 unnamed_device 24.9 MiB 1.12 1986 1014 8003 1763 5681 559 64.4 MiB 0.06 0.00 4.79638 4.06248 -133.531 -4.06248 4.06248 0.25 0.000293762 0.000269576 0.0208869 0.019182 -1 -1 -1 -1 30 2247 30 6.89349e+06 267783 556674. 1926.21 0.79 0.0985272 0.0859376 25186 138497 -1 1845 21 1118 1550 104372 24397 2.79711 2.79711 -117.654 -2.79711 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0142957 0.0127128 115 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_011.v common 3.56 vpr 64.48 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29804 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66024 30 32 303 262 1 191 84 17 17 289 -1 unnamed_device 25.2 MiB 1.11 2045 1034 13992 5226 7098 1668 64.5 MiB 0.07 0.00 5.30417 4.58817 -134.271 -4.58817 4.58817 0.25 0.000285823 0.000261664 0.0234962 0.0215034 -1 -1 -1 -1 32 2570 23 6.89349e+06 310065 586450. 2029.24 1.08 0.117321 0.102048 25474 144626 -1 1928 20 1166 1543 112527 25961 3.52775 3.52775 -121.933 -3.52775 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0137984 0.0122887 121 63 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_012.v common 2.79 vpr 64.41 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29740 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65956 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 24.9 MiB 1.00 2463 976 13432 3930 7414 2088 64.4 MiB 0.07 0.00 4.7073 3.6928 -114.983 -3.6928 3.6928 0.25 0.000275071 0.000252008 0.0223127 0.0204555 -1 -1 -1 -1 32 2213 22 6.89349e+06 253689 586450. 2029.24 0.39 0.0611593 0.0541867 25474 144626 -1 1780 22 1007 1381 100176 22972 2.74911 2.74911 -106.8 -2.74911 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0141439 0.0125142 103 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_013.v common 3.51 vpr 64.23 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29796 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65776 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 25.2 MiB 1.38 2413 1094 15335 5171 7707 2457 64.2 MiB 0.10 0.00 4.45968 4.21034 -134.417 -4.21034 4.21034 0.25 0.000329997 0.000301932 0.0308546 0.0282959 -1 -1 -1 -1 32 2902 28 6.89349e+06 352346 586450. 2029.24 0.75 0.12445 0.110508 25474 144626 -1 2293 23 1740 2630 196717 47360 3.47746 3.47746 -126.462 -3.47746 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169096 0.0150531 140 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_014.v common 4.58 vpr 65.01 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66568 32 32 363 295 1 232 90 17 17 289 -1 unnamed_device 24.9 MiB 1.45 2789 1385 9939 2779 6391 769 65.0 MiB 0.06 0.00 6.97451 5.52182 -162.398 -5.52182 5.52182 0.25 0.000335248 0.000306745 0.0184652 0.016897 -1 -1 -1 -1 28 3357 31 6.89349e+06 366440 531479. 1839.03 1.79 0.124115 0.10906 24610 126494 -1 2785 22 1872 2537 229756 59541 4.40835 4.40835 -155.309 -4.40835 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0181619 0.0162326 151 61 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_015.v common 3.42 vpr 64.33 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30272 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 29 32 248 215 1 160 82 17 17 289 -1 unnamed_device 24.9 MiB 0.98 1849 777 10762 2615 7615 532 64.3 MiB 0.05 0.00 4.18032 3.23418 -96.7477 -3.23418 3.23418 0.24 0.000255908 0.00023477 0.0168335 0.0154381 -1 -1 -1 -1 30 1844 21 6.89349e+06 295971 556674. 1926.21 1.12 0.122352 0.106443 25186 138497 -1 1498 22 967 1375 83682 21630 2.89731 2.89731 -98.7482 -2.89731 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.014901 0.0131379 98 27 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_016.v common 5.13 vpr 65.03 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 32 32 370 297 1 234 91 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2606 1335 15187 5552 7119 2516 65.0 MiB 0.11 0.00 5.16764 4.22024 -136.349 -4.22024 4.22024 0.26 0.000412992 0.000382645 0.0361098 0.0332974 -1 -1 -1 -1 30 3279 35 6.89349e+06 380534 556674. 1926.21 1.79 0.162898 0.143544 25186 138497 -1 2450 20 1777 2835 162669 40771 3.68045 3.68045 -133.182 -3.68045 0 0 706193. 2443.58 0.04 0.07 0.11 -1 -1 0.04 0.02568 0.022915 156 58 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_017.v common 3.90 vpr 64.87 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30200 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66424 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 25.2 MiB 1.28 2621 1087 13911 3796 7786 2329 64.9 MiB 0.08 0.00 4.95288 4.09494 -130.17 -4.09494 4.09494 0.24 0.000327812 0.000300274 0.0254079 0.0232692 -1 -1 -1 -1 36 2373 21 6.89349e+06 324158 648988. 2245.63 1.25 0.13221 0.115644 26050 158493 -1 1986 20 1185 1718 122618 29684 3.19801 3.19801 -114.684 -3.19801 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0152461 0.013601 137 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 3.28 vpr 64.84 MiB -1 -1 0.12 17916 1 0.03 -1 -1 30116 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 323 276 1 215 89 17 17 289 -1 unnamed_device 24.8 MiB 1.33 2509 1207 11573 2908 7136 1529 64.8 MiB 0.07 0.00 4.33725 3.64971 -129.543 -3.64971 3.64971 0.25 0.000446323 0.000418476 0.0206661 0.0189407 -1 -1 -1 -1 30 2877 36 6.89349e+06 352346 556674. 1926.21 0.61 0.0867738 0.0767415 25186 138497 -1 2229 18 1150 1585 105826 24515 3.03215 3.03215 -122.568 -3.03215 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0147283 0.0131892 130 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_019.v common 2.68 vpr 64.25 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29816 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 30 32 222 206 1 141 78 17 17 289 -1 unnamed_device 25.2 MiB 0.61 1681 755 9872 2574 6614 684 64.2 MiB 0.04 0.00 3.29613 2.66963 -90.6547 -2.66963 2.66963 0.24 0.000244818 0.000217441 0.016279 0.0149582 -1 -1 -1 -1 28 1581 17 6.89349e+06 225501 531479. 1839.03 0.81 0.0691751 0.060157 24610 126494 -1 1395 17 749 863 62232 15664 2.11002 2.11002 -91.215 -2.11002 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00977148 0.00866811 79 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_020.v common 3.99 vpr 64.46 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30172 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 291 243 1 179 84 17 17 289 -1 unnamed_device 24.7 MiB 1.29 2232 990 14358 5433 7130 1795 64.5 MiB 0.07 0.00 5.72212 4.79672 -142.478 -4.79672 4.79672 0.24 0.00047536 0.000450156 0.0250063 0.0229537 -1 -1 -1 -1 28 2553 26 6.89349e+06 295971 531479. 1839.03 1.37 0.109881 0.0966787 24610 126494 -1 2028 19 1246 1876 131016 32194 3.77545 3.77545 -139.775 -3.77545 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0130579 0.0116135 115 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_021.v common 3.83 vpr 64.80 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29940 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 342 271 1 207 99 17 17 289 -1 unnamed_device 24.8 MiB 1.07 2415 1186 18795 6653 9829 2313 64.8 MiB 0.09 0.00 6.0155 4.63443 -148.243 -4.63443 4.63443 0.25 0.000331482 0.000297849 0.0288279 0.0263868 -1 -1 -1 -1 36 2535 22 6.89349e+06 493284 648988. 2245.63 1.37 0.133607 0.116992 26050 158493 -1 2136 21 1575 2368 182986 42853 4.01424 4.01424 -140.469 -4.01424 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0195265 0.0174675 150 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_022.v common 3.80 vpr 65.02 MiB -1 -1 0.13 18064 1 0.04 -1 -1 29728 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 372 300 1 229 89 17 17 289 -1 unnamed_device 25.2 MiB 1.07 2872 1408 14741 4188 8680 1873 65.0 MiB 0.09 0.00 5.95345 4.79088 -146.55 -4.79088 4.79088 0.24 0.000345743 0.000316106 0.0275037 0.0252196 -1 -1 -1 -1 30 3072 30 6.89349e+06 352346 556674. 1926.21 1.31 0.14375 0.125667 25186 138497 -1 2494 21 1700 2463 172223 38111 3.67269 3.67269 -133.602 -3.67269 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0167697 0.0149365 152 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_023.v common 2.82 vpr 64.13 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30148 -1 -1 19 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 26 32 190 182 1 126 77 17 17 289 -1 unnamed_device 25.2 MiB 0.59 1378 528 11324 4722 5741 861 64.1 MiB 0.04 0.00 2.92131 2.67071 -73.9405 -2.67071 2.67071 0.25 0.000200742 0.000182777 0.0149184 0.0136176 -1 -1 -1 -1 30 1223 26 6.89349e+06 267783 556674. 1926.21 0.88 0.0684971 0.0593734 25186 138497 -1 921 17 565 672 37400 10275 1.85675 1.85675 -65.726 -1.85675 0 0 706193. 2443.58 0.03 0.02 0.13 -1 -1 0.03 0.00849785 0.00758487 72 30 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_024.v common 2.50 vpr 64.45 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29756 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 285 227 1 169 88 17 17 289 -1 unnamed_device 24.9 MiB 0.80 2097 1093 14908 4191 8870 1847 64.4 MiB 0.07 0.00 5.19194 4.58773 -130.119 -4.58773 4.58773 0.24 0.000291779 0.000266841 0.0240118 0.0219813 -1 -1 -1 -1 32 2488 23 6.89349e+06 338252 586450. 2029.24 0.38 0.0638837 0.0566624 25474 144626 -1 2145 20 1144 2016 159814 37055 3.49805 3.49805 -121.157 -3.49805 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0137382 0.0122388 120 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_025.v common 2.49 vpr 64.04 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30104 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65576 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 25.2 MiB 0.50 1343 738 9516 2733 5641 1142 64.0 MiB 0.03 0.00 2.53969 2.22522 -77.1622 -2.22522 2.22522 0.24 0.000194566 0.000176679 0.0126767 0.0115566 -1 -1 -1 -1 26 1456 18 6.89349e+06 169126 503264. 1741.40 0.55 0.0594687 0.0515478 24322 120374 -1 1353 21 670 881 68720 16870 1.77811 1.77811 -79.1079 -1.77811 0 0 618332. 2139.56 0.02 0.03 0.13 -1 -1 0.02 0.00971171 0.00855551 64 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_026.v common 3.48 vpr 64.49 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29588 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 300 245 1 187 86 17 17 289 -1 unnamed_device 24.9 MiB 1.13 2120 1085 9536 2559 6078 899 64.5 MiB 0.05 0.00 5.62618 4.92048 -138.071 -4.92048 4.92048 0.25 0.00030219 0.000276959 0.0167141 0.015329 -1 -1 -1 -1 32 2428 20 6.89349e+06 310065 586450. 2029.24 1.01 0.131882 0.115016 25474 144626 -1 1966 16 1004 1478 88603 22258 3.7112 3.7112 -125.676 -3.7112 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.012272 0.0110367 121 24 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 3.11 vpr 64.46 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29936 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 24.6 MiB 0.69 2474 1043 16727 4808 9374 2545 64.5 MiB 0.08 0.00 4.41543 3.451 -108.699 -3.451 3.451 0.25 0.000307109 0.000276632 0.0248743 0.022735 -1 -1 -1 -1 32 2399 21 6.89349e+06 436909 586450. 2029.24 1.10 0.124692 0.108971 25474 144626 -1 2003 21 1136 2050 128645 30983 2.66571 2.66571 -101.838 -2.66571 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145269 0.0129327 130 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 3.35 vpr 63.82 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29780 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65348 32 32 338 277 1 215 89 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2459 1294 14741 4922 7916 1903 63.8 MiB 0.09 0.00 5.82658 4.85308 -136.949 -4.85308 4.85308 0.24 0.000317563 0.000290569 0.025462 0.0232995 -1 -1 -1 -1 32 2850 43 6.89349e+06 352346 586450. 2029.24 0.61 0.0964175 0.0847986 25474 144626 -1 2288 20 1262 1877 121444 29241 3.65326 3.65326 -130.716 -3.65326 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0153091 0.0136806 139 50 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_029.v common 3.54 vpr 64.44 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29808 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 32 32 284 241 1 177 84 17 17 289 -1 unnamed_device 24.9 MiB 1.26 1936 1067 12894 4344 6614 1936 64.4 MiB 0.07 0.00 4.31105 3.7646 -126.911 -3.7646 3.7646 0.24 0.000281184 0.000257399 0.0213517 0.0195486 -1 -1 -1 -1 32 2226 20 6.89349e+06 281877 586450. 2029.24 0.96 0.0987942 0.0861715 25474 144626 -1 1958 21 1103 1593 110334 26241 2.69186 2.69186 -115.097 -2.69186 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0143842 0.0127846 110 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_030.v common 2.58 vpr 64.37 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30264 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 30 32 262 227 1 161 83 17 17 289 -1 unnamed_device 24.9 MiB 0.86 2301 943 13043 4183 6793 2067 64.4 MiB 0.06 0.00 5.05544 4.00962 -116.333 -4.00962 4.00962 0.25 0.000274696 0.000251996 0.0211122 0.0193502 -1 -1 -1 -1 32 2109 18 6.89349e+06 295971 586450. 2029.24 0.37 0.0588309 0.0520159 25474 144626 -1 1793 21 971 1595 128041 29328 3.30785 3.30785 -109.419 -3.30785 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0162331 0.0145062 103 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_031.v common 3.34 vpr 64.19 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29604 -1 -1 20 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65732 28 32 260 223 1 163 80 17 17 289 -1 unnamed_device 24.7 MiB 1.04 1953 1013 13324 4541 7089 1694 64.2 MiB 0.08 0.00 5.13107 4.43603 -124.612 -4.43603 4.43603 0.26 0.000270744 0.000248135 0.0269024 0.0247709 -1 -1 -1 -1 30 2187 21 6.89349e+06 281877 556674. 1926.21 0.98 0.110529 0.0969537 25186 138497 -1 1819 17 903 1571 100336 23266 3.3055 3.3055 -115.801 -3.3055 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0112853 0.0100418 104 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 3.17 vpr 64.25 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29720 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 24.8 MiB 0.85 2155 955 10228 2872 6411 945 64.2 MiB 0.05 0.00 4.55303 3.92502 -120.982 -3.92502 3.92502 0.24 0.000264604 0.000242521 0.0173918 0.015918 -1 -1 -1 -1 32 2080 26 6.89349e+06 253689 586450. 2029.24 1.01 0.103009 0.0892271 25474 144626 -1 1800 19 1015 1740 120492 28474 2.78381 2.78381 -113.151 -2.78381 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0120413 0.0106721 101 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 3.00 vpr 64.44 MiB -1 -1 0.20 18056 1 0.02 -1 -1 29764 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 31 32 271 231 1 172 84 17 17 289 -1 unnamed_device 24.6 MiB 1.05 2571 955 9966 2827 6447 692 64.4 MiB 0.05 0.00 4.5958 3.73465 -114.886 -3.73465 3.73465 0.25 0.000280398 0.000257313 0.0163776 0.0149922 -1 -1 -1 -1 26 2565 37 6.89349e+06 295971 503264. 1741.40 0.50 0.0627421 0.0550562 24322 120374 -1 2108 18 1121 1641 117820 29274 3.19091 3.19091 -118.654 -3.19091 0 0 618332. 2139.56 0.02 0.03 0.11 -1 -1 0.02 0.0119732 0.0106622 105 30 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 3.97 vpr 63.87 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29848 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 29 32 291 250 1 185 84 17 17 289 -1 unnamed_device 24.7 MiB 1.46 2485 957 12894 3059 8335 1500 63.9 MiB 0.06 0.00 4.26057 3.6185 -104.685 -3.6185 3.6185 0.25 0.000308233 0.000278605 0.0227674 0.0209684 -1 -1 -1 -1 34 2000 20 6.89349e+06 324158 618332. 2139.56 1.16 0.133759 0.116522 25762 151098 -1 1717 18 913 1287 86496 21872 2.65071 2.65071 -97.5528 -2.65071 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0126343 0.0112802 117 54 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_035.v common 4.08 vpr 64.57 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29612 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 367 282 1 224 91 17 17 289 -1 unnamed_device 24.9 MiB 1.04 2453 1261 14371 4620 7204 2547 64.6 MiB 0.09 0.00 5.05875 4.57545 -133.583 -4.57545 4.57545 0.25 0.000352767 0.000323289 0.0269709 0.0247561 -1 -1 -1 -1 36 2825 23 6.89349e+06 380534 648988. 2245.63 1.58 0.178928 0.157203 26050 158493 -1 2396 20 1295 2069 145934 34231 3.97056 3.97056 -127.691 -3.97056 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0167835 0.0150141 154 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_036.v common 4.42 vpr 64.68 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30128 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 391 311 1 250 92 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2644 1340 16238 5326 8855 2057 64.7 MiB 0.10 0.00 4.96607 4.60807 -154.992 -4.60807 4.60807 0.25 0.000361877 0.000331603 0.0308029 0.028253 -1 -1 -1 -1 32 3395 36 6.89349e+06 394628 586450. 2029.24 1.34 0.162449 0.143043 25474 144626 -1 2714 23 2107 3054 238419 53335 3.72925 3.72925 -145.858 -3.72925 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.019568 0.017421 163 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_037.v common 2.66 vpr 64.02 MiB -1 -1 0.12 18052 1 0.02 -1 -1 29812 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 24.9 MiB 0.84 2434 989 8306 2314 5441 551 64.0 MiB 0.05 0.00 4.86668 4.04584 -122.858 -4.04584 4.04584 0.25 0.000282431 0.000258833 0.0169493 0.0155912 -1 -1 -1 -1 32 2127 23 6.89349e+06 253689 586450. 2029.24 0.40 0.0554529 0.0490594 25474 144626 -1 1912 23 1092 1705 138575 32111 3.38461 3.38461 -118.083 -3.38461 0 0 744469. 2576.02 0.04 0.06 0.12 -1 -1 0.04 0.0225944 0.0201313 107 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 4.05 vpr 64.24 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30160 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 370 297 1 235 90 17 17 289 -1 unnamed_device 24.9 MiB 1.59 2670 1289 13155 3308 7952 1895 64.2 MiB 0.08 0.00 5.12349 4.31155 -137.727 -4.31155 4.31155 0.24 0.00034025 0.000311385 0.0239065 0.0219058 -1 -1 -1 -1 30 2812 22 6.89349e+06 380534 556674. 1926.21 1.10 0.121591 0.106877 25186 138497 -1 2328 20 1532 2286 129522 32467 3.41065 3.41065 -129.329 -3.41065 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0161074 0.0143427 154 61 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 3.89 vpr 65.05 MiB -1 -1 0.14 17676 1 0.03 -1 -1 30160 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 31 32 377 302 1 241 91 17 17 289 -1 unnamed_device 25.2 MiB 1.61 2869 1286 10291 2730 6649 912 65.0 MiB 0.07 0.00 6.59857 5.48687 -163.025 -5.48687 5.48687 0.25 0.000347488 0.000319042 0.0195108 0.0178794 -1 -1 -1 -1 32 3330 22 6.89349e+06 394628 586450. 2029.24 0.79 0.0829449 0.0732081 25474 144626 -1 2600 21 1764 2590 214962 46783 4.41735 4.41735 -155.28 -4.41735 0 0 744469. 2576.02 0.04 0.08 0.13 -1 -1 0.04 0.0280281 0.0249912 158 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_040.v common 3.79 vpr 64.29 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 31 32 383 305 1 240 92 17 17 289 -1 unnamed_device 24.9 MiB 1.77 2971 1288 18308 5162 11169 1977 64.3 MiB 0.11 0.00 7.06021 5.82563 -172.459 -5.82563 5.82563 0.24 0.000352762 0.000318106 0.0338824 0.0310012 -1 -1 -1 -1 32 3079 30 6.89349e+06 408721 586450. 2029.24 0.50 0.0862449 0.076668 25474 144626 -1 2614 23 1873 2828 219295 50747 5.21269 5.21269 -171.607 -5.21269 0 0 744469. 2576.02 0.03 0.06 0.16 -1 -1 0.03 0.0202925 0.0181011 160 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_041.v common 3.23 vpr 64.96 MiB -1 -1 0.13 18056 1 0.04 -1 -1 29764 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 31 32 352 285 1 223 90 17 17 289 -1 unnamed_device 25.2 MiB 1.25 2244 1364 13356 3907 7417 2032 65.0 MiB 0.08 0.00 4.56598 4.06478 -129.084 -4.06478 4.06478 0.24 0.000332109 0.000304119 0.0239262 0.0219187 -1 -1 -1 -1 30 3087 26 6.89349e+06 380534 556674. 1926.21 0.48 0.0737516 0.0650058 25186 138497 -1 2499 20 1518 2227 158913 35691 3.44916 3.44916 -121.559 -3.44916 0 0 706193. 2443.58 0.03 0.04 0.13 -1 -1 0.03 0.0158182 0.0140933 147 55 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_042.v common 3.82 vpr 64.50 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30156 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 32 32 291 242 1 188 86 17 17 289 -1 unnamed_device 25.2 MiB 1.22 2505 1019 15017 5391 6893 2733 64.5 MiB 0.07 0.00 5.50703 4.42605 -118.578 -4.42605 4.42605 0.24 0.000290947 0.000266089 0.024837 0.022735 -1 -1 -1 -1 30 2553 47 6.89349e+06 310065 556674. 1926.21 1.26 0.131474 0.114382 25186 138497 -1 1963 19 1069 1508 97270 23623 3.8018 3.8018 -115.623 -3.8018 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0134814 0.012024 114 27 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_043.v common 4.96 vpr 65.33 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29828 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66896 32 32 457 356 1 296 101 17 17 289 -1 unnamed_device 25.6 MiB 2.07 3202 1707 11616 2831 7740 1045 65.3 MiB 0.10 0.00 6.63 5.71166 -180.923 -5.71166 5.71166 0.24 0.000421051 0.000387062 0.029106 0.0268523 -1 -1 -1 -1 32 4457 33 6.89349e+06 521472 586450. 2029.24 1.36 0.174611 0.153493 25474 144626 -1 3340 23 2283 3484 283406 73527 4.54378 4.54378 -163.759 -4.54378 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0244152 0.0218808 199 87 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_044.v common 2.47 vpr 64.36 MiB -1 -1 0.14 17676 1 0.03 -1 -1 30212 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 31 32 261 225 1 171 83 17 17 289 -1 unnamed_device 24.9 MiB 0.78 2305 761 9803 2301 6865 637 64.4 MiB 0.05 0.00 4.9117 3.8019 -108.91 -3.8019 3.8019 0.25 0.000282573 0.000259542 0.0176186 0.0162018 -1 -1 -1 -1 32 2072 23 6.89349e+06 281877 586450. 2029.24 0.35 0.0559811 0.0492287 25474 144626 -1 1627 20 1015 1385 86539 22892 3.18906 3.18906 -107.56 -3.18906 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0125017 0.0110861 101 28 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_045.v common 4.29 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29856 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 24.9 MiB 1.31 2787 1139 8473 1978 5944 551 64.9 MiB 0.06 0.00 5.76922 4.83408 -143.835 -4.83408 4.83408 0.25 0.000323 0.000295931 0.0164862 0.0151597 -1 -1 -1 -1 28 3258 24 6.89349e+06 352346 531479. 1839.03 1.61 0.11073 0.0969671 24610 126494 -1 2479 21 1692 2507 182798 44288 4.1091 4.1091 -145.402 -4.1091 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0160239 0.0143004 139 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_046.v common 3.42 vpr 64.40 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29704 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 349 284 1 222 91 17 17 289 -1 unnamed_device 24.8 MiB 1.38 2669 1235 9475 2196 6793 486 64.4 MiB 0.07 0.00 5.26295 4.39795 -133.209 -4.39795 4.39795 0.26 0.000355222 0.000316909 0.0220287 0.0202872 -1 -1 -1 -1 30 3163 30 6.89349e+06 380534 556674. 1926.21 0.62 0.0861179 0.0762636 25186 138497 -1 2521 38 1868 3138 263695 85979 3.45195 3.45195 -128.059 -3.45195 0 0 706193. 2443.58 0.03 0.08 0.07 -1 -1 0.03 0.0244879 0.0215511 146 53 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_047.v common 3.30 vpr 64.44 MiB -1 -1 0.22 17676 1 0.02 -1 -1 29788 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 0.71 1933 1092 14575 4579 7786 2210 64.4 MiB 0.08 0.00 4.84964 4.24939 -129.722 -4.24939 4.24939 0.24 0.00086745 0.000802011 0.0241679 0.0221141 -1 -1 -1 -1 32 2496 21 6.89349e+06 380534 586450. 2029.24 1.14 0.111521 0.0978012 25474 144626 -1 2102 21 1130 2260 167469 38040 3.607 3.607 -125.377 -3.607 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0144232 0.0128114 123 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 4.01 vpr 64.57 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29752 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 353 287 1 220 90 17 17 289 -1 unnamed_device 24.9 MiB 1.31 2606 1137 13959 4872 6200 2887 64.6 MiB 0.08 0.00 4.99599 4.43611 -128.994 -4.43611 4.43611 0.24 0.000337654 0.000308984 0.0250131 0.0228926 -1 -1 -1 -1 36 2583 24 6.89349e+06 366440 648988. 2245.63 1.32 0.134965 0.117841 26050 158493 -1 2080 19 1418 1940 131258 33952 3.32661 3.32661 -114.202 -3.32661 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0151167 0.0135052 143 55 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_049.v common 4.06 vpr 64.57 MiB -1 -1 0.11 17908 1 0.03 -1 -1 29788 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 361 291 1 231 90 17 17 289 -1 unnamed_device 24.9 MiB 1.46 2568 1471 16773 5286 9456 2031 64.6 MiB 0.11 0.00 5.07339 4.21419 -136.215 -4.21419 4.21419 0.25 0.000340656 0.000312322 0.0401428 0.0371406 -1 -1 -1 -1 26 3247 37 6.89349e+06 366440 503264. 1741.40 1.17 0.154223 0.136036 24322 120374 -1 2794 20 1750 2576 179633 42531 3.67355 3.67355 -137.947 -3.67355 0 0 618332. 2139.56 0.02 0.05 0.06 -1 -1 0.02 0.0159892 0.0142241 149 55 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_050.v common 5.10 vpr 65.05 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29844 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 382 305 1 243 92 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2705 1368 16031 4740 8553 2738 65.1 MiB 0.09 0.00 5.02847 4.40197 -141.012 -4.40197 4.40197 0.36 0.00035782 0.000328643 0.0292191 0.0267664 -1 -1 -1 -1 36 3034 44 6.89349e+06 394628 648988. 2245.63 1.76 0.173531 0.152219 26050 158493 -1 2623 21 1990 2843 215002 49630 3.41336 3.41336 -127.927 -3.41336 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0213513 0.0191552 160 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_051.v common 3.39 vpr 63.93 MiB -1 -1 0.11 18300 1 0.03 -1 -1 29748 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65464 32 32 306 248 1 188 87 17 17 289 -1 unnamed_device 24.7 MiB 0.98 2196 1143 14295 3709 9126 1460 63.9 MiB 0.08 0.00 5.64975 4.52825 -134.553 -4.52825 4.52825 0.25 0.000307577 0.000281552 0.0241934 0.0221636 -1 -1 -1 -1 26 2654 43 6.89349e+06 324158 503264. 1741.40 1.10 0.126441 0.110874 24322 120374 -1 2299 20 1441 2205 153221 36540 4.2106 4.2106 -141.768 -4.2106 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.014174 0.012622 123 24 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_052.v common 2.59 vpr 64.79 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29952 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66348 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 24.9 MiB 0.92 2220 1132 9303 2287 5956 1060 64.8 MiB 0.06 0.00 5.85178 4.86728 -141.077 -4.86728 4.86728 0.24 0.00031178 0.000285633 0.0165258 0.0151309 -1 -1 -1 -1 30 2732 27 6.89349e+06 324158 556674. 1926.21 0.37 0.0623473 0.0549675 25186 138497 -1 2302 22 1328 1944 126115 30047 3.82166 3.82166 -132.023 -3.82166 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.015552 0.0138663 129 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_053.v common 3.46 vpr 64.98 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66536 31 32 373 299 1 227 90 17 17 289 -1 unnamed_device 25.2 MiB 1.38 2459 1142 10944 2981 6313 1650 65.0 MiB 0.07 0.00 5.42896 4.77798 -141.248 -4.77798 4.77798 0.35 0.000351179 0.000321756 0.0206113 0.0188859 -1 -1 -1 -1 32 3654 30 6.89349e+06 380534 586450. 2029.24 0.54 0.0724628 0.0639195 25474 144626 -1 2569 21 1631 2555 180112 43962 4.02469 4.02469 -136.645 -4.02469 0 0 744469. 2576.02 0.03 0.05 0.13 -1 -1 0.03 0.0166904 0.0148941 154 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_054.v common 4.29 vpr 65.09 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29528 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66652 32 32 387 315 1 247 91 17 17 289 -1 unnamed_device 25.2 MiB 1.78 2851 1347 7231 1595 5190 446 65.1 MiB 0.05 0.00 5.65933 4.38345 -134.94 -4.38345 4.38345 0.24 0.000357978 0.000328523 0.0146477 0.0134302 -1 -1 -1 -1 32 3284 25 6.89349e+06 380534 586450. 2029.24 1.09 0.112964 0.0982118 25474 144626 -1 2634 20 2010 2965 184477 44253 3.54626 3.54626 -130.981 -3.54626 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169355 0.0150937 160 77 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_055.v common 4.33 vpr 64.33 MiB -1 -1 0.15 17676 1 0.02 -1 -1 29816 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 251 219 1 156 81 17 17 289 -1 unnamed_device 24.9 MiB 0.98 1772 720 12681 4996 6149 1536 64.3 MiB 0.05 0.00 4.27105 3.55383 -105.248 -3.55383 3.55383 0.35 0.000260874 0.00023824 0.0202907 0.0185529 -1 -1 -1 -1 32 2262 44 6.89349e+06 239595 586450. 2029.24 1.89 0.130372 0.113046 25474 144626 -1 1579 19 952 1380 99711 28807 2.81411 2.81411 -102.252 -2.81411 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0119485 0.0106421 93 23 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_056.v common 3.03 vpr 64.53 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30208 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 341 285 1 219 88 17 17 289 -1 unnamed_device 24.9 MiB 1.23 2681 1141 15103 4277 8627 2199 64.5 MiB 0.09 0.00 5.91853 4.58813 -154.793 -4.58813 4.58813 0.25 0.000320476 0.000293647 0.0265283 0.0242834 -1 -1 -1 -1 32 2780 22 6.89349e+06 338252 586450. 2029.24 0.40 0.0714864 0.0634616 25474 144626 -1 2260 21 1752 2418 177496 42479 3.78384 3.78384 -143.369 -3.78384 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0157346 0.0140365 137 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_057.v common 3.73 vpr 65.04 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29980 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 32 32 387 293 1 237 93 17 17 289 -1 unnamed_device 25.6 MiB 1.16 2868 1359 7443 1583 5363 497 65.0 MiB 0.06 0.00 6.45037 5.51607 -162.931 -5.51607 5.51607 0.24 0.000366596 0.000336094 0.0148177 0.0136169 -1 -1 -1 -1 32 3548 27 6.89349e+06 408721 586450. 2029.24 1.21 0.122099 0.106722 25474 144626 -1 2719 24 1840 2982 202888 48705 4.85635 4.85635 -159.726 -4.85635 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0194438 0.0173392 166 31 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_058.v common 2.75 vpr 64.23 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29948 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 340 270 1 212 88 17 17 289 -1 unnamed_device 25.2 MiB 1.00 2505 1217 15493 4661 8456 2376 64.2 MiB 0.09 0.00 5.54276 4.5126 -143.919 -4.5126 4.5126 0.24 0.000326565 0.000298191 0.0283386 0.0259713 -1 -1 -1 -1 32 2665 26 6.89349e+06 338252 586450. 2029.24 0.38 0.0732243 0.065078 25474 144626 -1 2106 18 1333 1923 122925 29624 2.94921 2.94921 -122.833 -2.94921 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145007 0.0129746 137 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_059.v common 2.83 vpr 64.14 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29820 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 278 235 1 175 94 17 17 289 -1 unnamed_device 25.1 MiB 1.03 2250 1061 16282 4606 9784 1892 64.1 MiB 0.08 0.00 5.16569 4.37039 -131.236 -4.37039 4.37039 0.24 0.000283376 0.000255448 0.0231331 0.021189 -1 -1 -1 -1 30 2166 21 6.89349e+06 451003 556674. 1926.21 0.35 0.0595493 0.0527931 25186 138497 -1 1802 21 1102 1807 103448 25235 3.19625 3.19625 -118.702 -3.19625 0 0 706193. 2443.58 0.04 0.05 0.11 -1 -1 0.04 0.0200294 0.0177972 118 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_060.v common 5.65 vpr 64.85 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29820 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66408 32 32 431 332 1 270 94 17 17 289 -1 unnamed_device 25.2 MiB 1.90 3075 1543 15004 4609 8067 2328 64.9 MiB 0.11 0.00 7.91759 6.34645 -186.607 -6.34645 6.34645 0.34 0.000416403 0.000382506 0.0312082 0.0287208 -1 -1 -1 -1 34 3953 24 6.89349e+06 422815 618332. 2139.56 2.22 0.207421 0.183112 25762 151098 -1 3259 22 2492 3991 303577 69677 5.59473 5.59473 -185.938 -5.59473 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0201136 0.017945 182 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_061.v common 3.31 vpr 64.80 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29956 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 336 268 1 205 88 17 17 289 -1 unnamed_device 24.9 MiB 0.88 2530 936 7303 1455 5167 681 64.8 MiB 0.04 0.00 5.66882 4.76668 -140.932 -4.76668 4.76668 0.24 0.000324361 0.00029737 0.013727 0.0125967 -1 -1 -1 -1 34 2331 26 6.89349e+06 338252 618332. 2139.56 1.13 0.102032 0.089028 25762 151098 -1 1928 21 1515 2171 157974 39480 3.73286 3.73286 -126.515 -3.73286 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0156274 0.0139155 136 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_062.v common 2.77 vpr 63.61 MiB -1 -1 0.13 17676 1 0.02 -1 -1 29944 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65132 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 23.9 MiB 0.53 1762 895 10649 2847 7198 604 63.6 MiB 0.05 0.00 3.9244 3.74796 -105.814 -3.74796 3.74796 0.24 0.000268278 0.000244282 0.0179661 0.0166428 -1 -1 -1 -1 32 1907 18 6.89349e+06 394628 586450. 2029.24 0.90 0.0935599 0.0813927 25474 144626 -1 1683 19 741 1322 94047 22538 2.77811 2.77811 -100.732 -2.77811 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110016 0.00974569 96 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_063.v common 4.11 vpr 64.88 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29820 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 349 273 1 214 91 17 17 289 -1 unnamed_device 24.8 MiB 1.25 3131 1378 18043 5544 10561 1938 64.9 MiB 0.11 0.00 6.94676 5.55938 -147.432 -5.55938 5.55938 0.25 0.000339508 0.000310993 0.0322799 0.0295947 -1 -1 -1 -1 30 2968 27 6.89349e+06 380534 556674. 1926.21 1.36 0.143251 0.126546 25186 138497 -1 2443 20 1275 2357 162480 37915 4.27535 4.27535 -136.057 -4.27535 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0192963 0.0171527 146 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_064.v common 3.12 vpr 64.30 MiB -1 -1 0.10 17668 1 0.03 -1 -1 29808 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 24.9 MiB 0.71 2118 762 14407 5564 6574 2269 64.3 MiB 0.06 0.00 4.4685 3.6244 -108.803 -3.6244 3.6244 0.24 0.000261105 0.000238587 0.0216374 0.0197903 -1 -1 -1 -1 34 1873 19 6.89349e+06 295971 618332. 2139.56 1.12 0.118262 0.102525 25762 151098 -1 1576 20 1144 2018 129507 32747 2.93836 2.93836 -105.161 -2.93836 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0122186 0.0108317 99 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_065.v common 3.40 vpr 64.37 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29832 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 30 32 278 235 1 175 86 17 17 289 -1 unnamed_device 24.7 MiB 1.03 2617 994 11426 3379 7154 893 64.4 MiB 0.06 0.00 5.48567 4.35797 -127.583 -4.35797 4.35797 0.25 0.000284282 0.000261237 0.0182379 0.0167215 -1 -1 -1 -1 30 2087 21 6.89349e+06 338252 556674. 1926.21 1.02 0.105116 0.0921757 25186 138497 -1 1740 21 1006 1535 104945 23844 3.05475 3.05475 -111.469 -3.05475 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0135113 0.011984 110 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_066.v common 4.35 vpr 64.92 MiB -1 -1 0.15 18064 1 0.03 -1 -1 30120 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 29 32 355 287 1 223 90 17 17 289 -1 unnamed_device 25.2 MiB 1.68 3036 1235 16170 4166 10388 1616 64.9 MiB 0.12 0.00 6.20943 4.65473 -135.021 -4.65473 4.65473 0.26 0.000340499 0.000312371 0.0380566 0.0352096 -1 -1 -1 -1 30 2943 33 6.89349e+06 408721 556674. 1926.21 1.24 0.150728 0.132472 25186 138497 -1 2341 19 1282 1890 114886 27835 3.41865 3.41865 -124.026 -3.41865 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0150858 0.0134617 150 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_067.v common 4.30 vpr 64.95 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29764 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 32 32 358 289 1 230 91 17 17 289 -1 unnamed_device 24.9 MiB 1.53 2704 1306 16819 4681 10419 1719 64.9 MiB 0.09 0.00 6.50098 4.98955 -155.576 -4.98955 4.98955 0.32 0.000334926 0.000306435 0.0292019 0.0266694 -1 -1 -1 -1 30 2937 26 6.89349e+06 380534 556674. 1926.21 1.17 0.135449 0.118337 25186 138497 -1 2245 22 1603 2359 152417 37029 4.30739 4.30739 -148.653 -4.30739 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0166872 0.0148652 149 54 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_068.v common 4.36 vpr 64.91 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 353 285 1 227 89 17 17 289 -1 unnamed_device 24.9 MiB 1.57 2686 1321 12959 3747 7875 1337 64.9 MiB 0.08 0.00 6.75127 5.45967 -157.239 -5.45967 5.45967 0.34 0.000333505 0.000305472 0.0233836 0.0214198 -1 -1 -1 -1 30 3232 23 6.89349e+06 352346 556674. 1926.21 1.24 0.13275 0.115861 25186 138497 -1 2671 21 1571 2337 162253 37482 4.45865 4.45865 -150.907 -4.45865 0 0 706193. 2443.58 0.03 0.05 0.12 -1 -1 0.03 0.016106 0.0143412 144 51 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_069.v common 3.50 vpr 64.39 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29756 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 276 237 1 165 82 17 17 289 -1 unnamed_device 24.9 MiB 1.13 1895 1005 11652 3070 6952 1630 64.4 MiB 0.07 0.00 5.1192 4.9044 -138.677 -4.9044 4.9044 0.26 0.000278309 0.000254748 0.0235075 0.0216386 -1 -1 -1 -1 32 2185 33 6.89349e+06 253689 586450. 2029.24 1.01 0.115145 0.100551 25474 144626 -1 1883 14 742 1011 79811 18262 3.27225 3.27225 -119.982 -3.27225 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0114505 0.0102782 103 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_070.v common 3.91 vpr 64.19 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30176 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 31 32 319 272 1 203 85 17 17 289 -1 unnamed_device 25.2 MiB 1.37 2292 1146 15523 5307 8105 2111 64.2 MiB 0.10 0.00 4.5444 3.67535 -123.05 -3.67535 3.67535 0.25 0.000307579 0.000282148 0.0348281 0.0320625 -1 -1 -1 -1 34 2599 23 6.89349e+06 310065 618332. 2139.56 1.15 0.134759 0.118755 25762 151098 -1 2270 20 1476 2059 153853 36261 3.29286 3.29286 -123.024 -3.29286 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143522 0.0127744 125 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_071.v common 4.12 vpr 64.14 MiB -1 -1 0.12 18064 1 0.03 -1 -1 29804 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 329 273 1 213 89 17 17 289 -1 unnamed_device 24.6 MiB 1.51 2646 1203 12761 3384 8201 1176 64.1 MiB 0.07 0.00 4.5069 3.773 -110.836 -3.773 3.773 0.24 0.000311783 0.000285761 0.02181 0.0200015 -1 -1 -1 -1 28 2719 25 6.89349e+06 380534 531479. 1839.03 1.20 0.137278 0.120489 24610 126494 -1 2355 23 1698 2575 179984 42945 3.00476 3.00476 -111.209 -3.00476 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0163353 0.0144894 139 57 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_072.v common 3.37 vpr 64.45 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29840 -1 -1 26 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 28 32 277 229 1 171 86 17 17 289 -1 unnamed_device 25.2 MiB 0.89 2290 995 14639 5073 7461 2105 64.5 MiB 0.07 0.00 5.43839 4.41095 -114.576 -4.41095 4.41095 0.24 0.000281419 0.000258556 0.0248781 0.0228497 -1 -1 -1 -1 30 2148 20 6.89349e+06 366440 556674. 1926.21 1.07 0.103487 0.0905008 25186 138497 -1 1844 17 968 1744 111480 25633 3.44096 3.44096 -108.289 -3.44096 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.011729 0.0104772 116 27 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_073.v common 3.60 vpr 64.80 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29776 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66352 30 32 317 269 1 202 85 17 17 289 -1 unnamed_device 24.9 MiB 1.62 2526 1178 15151 5407 7948 1796 64.8 MiB 0.08 0.00 6.03926 4.84252 -145.079 -4.84252 4.84252 0.36 0.000308102 0.00028241 0.0259855 0.0238032 -1 -1 -1 -1 32 2638 26 6.89349e+06 324158 586450. 2029.24 0.54 0.0727006 0.0644386 25474 144626 -1 2199 17 1333 1877 129448 30773 3.77919 3.77919 -132.955 -3.77919 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0129051 0.0115612 127 63 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_074.v common 3.30 vpr 64.90 MiB -1 -1 0.18 18060 1 0.04 -1 -1 29804 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66460 32 32 335 282 1 222 88 17 17 289 -1 unnamed_device 24.9 MiB 1.19 2501 1336 13543 3628 8253 1662 64.9 MiB 0.08 0.00 4.4454 3.9442 -135.714 -3.9442 3.9442 0.24 0.000315843 0.000288919 0.0231779 0.0211775 -1 -1 -1 -1 32 3103 40 6.89349e+06 338252 586450. 2029.24 0.56 0.0750108 0.066122 25474 144626 -1 2494 23 1598 2140 158708 36808 3.28651 3.28651 -129.749 -3.28651 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0160547 0.0142476 131 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_075.v common 2.57 vpr 64.46 MiB -1 -1 0.13 17676 1 0.03 -1 -1 29532 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.7 MiB 0.63 2002 1084 14769 4409 8006 2354 64.5 MiB 0.07 0.00 5.30012 4.68052 -134.297 -4.68052 4.68052 0.24 0.000295535 0.000269833 0.0214319 0.0196168 -1 -1 -1 -1 28 2586 32 6.89349e+06 465097 531479. 1839.03 0.54 0.0663218 0.0585427 24610 126494 -1 2233 21 1356 2590 184684 43970 3.7486 3.7486 -127.386 -3.7486 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.01425 0.0126423 130 4 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_076.v common 3.30 vpr 64.94 MiB -1 -1 0.11 17744 1 0.03 -1 -1 30352 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 24.9 MiB 1.40 2769 1083 6718 1366 4439 913 64.9 MiB 0.05 0.00 5.69108 4.83188 -148.303 -4.83188 4.83188 0.35 0.000338842 0.000310699 0.0130856 0.0120274 -1 -1 -1 -1 32 2917 37 6.89349e+06 338252 586450. 2029.24 0.48 0.0657926 0.0578615 25474 144626 -1 2309 21 1509 2317 154492 38324 3.91029 3.91029 -139.835 -3.91029 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.016088 0.0143116 142 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_077.v common 5.21 vpr 65.04 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29796 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 32 32 385 308 1 244 92 17 17 289 -1 unnamed_device 25.7 MiB 1.48 2790 1274 17273 5734 8473 3066 65.0 MiB 0.12 0.00 6.85201 5.78412 -176.84 -5.78412 5.78412 0.26 0.000597265 0.000566774 0.0414682 0.0383639 -1 -1 -1 -1 34 3863 36 6.89349e+06 394628 618332. 2139.56 2.28 0.215964 0.190586 25762 151098 -1 2559 23 1887 2646 185724 45717 4.97334 4.97334 -162.157 -4.97334 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0215156 0.0190645 162 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_078.v common 3.67 vpr 64.65 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29836 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66200 32 32 387 309 1 248 93 17 17 289 -1 unnamed_device 25.2 MiB 1.66 3405 1313 11223 3015 7022 1186 64.6 MiB 0.07 0.00 6.15614 4.85896 -154.704 -4.85896 4.85896 0.24 0.000355317 0.000325773 0.0210931 0.0192759 -1 -1 -1 -1 32 3310 32 6.89349e+06 408721 586450. 2029.24 0.54 0.0745848 0.0659313 25474 144626 -1 2572 19 1527 2333 153538 35602 3.68845 3.68845 -137.066 -3.68845 0 0 744469. 2576.02 0.03 0.04 0.13 -1 -1 0.03 0.0166105 0.0147769 163 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_079.v common 3.71 vpr 64.38 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29856 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 30 32 272 232 1 175 84 17 17 289 -1 unnamed_device 25.2 MiB 1.31 2272 918 14724 4804 7694 2226 64.4 MiB 0.07 0.00 5.36037 4.39377 -130.219 -4.39377 4.39377 0.24 0.000287341 0.000264486 0.0234956 0.0215251 -1 -1 -1 -1 30 2227 25 6.89349e+06 310065 556674. 1926.21 1.10 0.108014 0.0941904 25186 138497 -1 1897 16 970 1436 106281 24291 3.2479 3.2479 -115.807 -3.2479 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0114634 0.010241 108 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_080.v common 4.51 vpr 64.62 MiB -1 -1 0.12 18060 1 0.04 -1 -1 30192 -1 -1 29 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 30 32 375 299 1 236 91 17 17 289 -1 unnamed_device 25.2 MiB 1.55 3003 1114 16819 5989 7667 3163 64.6 MiB 0.09 0.00 6.38211 5.54961 -163.139 -5.54961 5.54961 0.25 0.000340617 0.000311648 0.0301202 0.0275803 -1 -1 -1 -1 34 2922 32 6.89349e+06 408721 618332. 2139.56 1.39 0.156699 0.137371 25762 151098 -1 2293 19 1618 2268 162682 39870 4.68838 4.68838 -154.58 -4.68838 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.015856 0.0141856 159 63 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_081.v common 3.54 vpr 64.86 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29880 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 24.9 MiB 0.94 2652 1098 15731 5114 8768 1849 64.9 MiB 0.09 0.00 5.91759 5.21145 -150.283 -5.21145 5.21145 0.24 0.000328416 0.000300997 0.028151 0.0258108 -1 -1 -1 -1 32 2768 22 6.89349e+06 352346 586450. 2029.24 1.20 0.135819 0.119475 25474 144626 -1 2250 20 1419 2440 185945 44358 4.03336 4.03336 -132.792 -4.03336 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0152433 0.0136056 137 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_082.v common 4.27 vpr 64.33 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29652 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 31 32 340 275 1 211 88 17 17 289 -1 unnamed_device 24.7 MiB 1.65 2743 1182 11788 3318 7484 986 64.3 MiB 0.07 0.00 6.23744 5.09779 -147.137 -5.09779 5.09779 0.24 0.000321184 0.000294656 0.021254 0.0194531 -1 -1 -1 -1 32 2731 26 6.89349e+06 352346 586450. 2029.24 1.07 0.113692 0.0993541 25474 144626 -1 2290 19 1442 2154 142174 34243 4.42139 4.42139 -145.725 -4.42139 0 0 744469. 2576.02 0.03 0.04 0.09 -1 -1 0.03 0.0147709 0.0132276 139 47 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 4.19 vpr 64.57 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30520 -1 -1 30 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66120 30 32 377 310 1 239 92 17 17 289 -1 unnamed_device 24.9 MiB 1.58 3065 1308 17480 5851 9201 2428 64.6 MiB 0.11 0.00 6.31486 5.04907 -145.771 -5.04907 5.04907 0.25 0.000363407 0.000333582 0.034511 0.0317521 -1 -1 -1 -1 34 2995 23 6.89349e+06 422815 618332. 2139.56 1.11 0.131067 0.115037 25762 151098 -1 2440 29 2151 3033 223442 62433 3.98754 3.98754 -132.06 -3.98754 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0212267 0.0187147 160 83 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_084.v common 4.21 vpr 64.60 MiB -1 -1 0.14 18444 1 0.03 -1 -1 30172 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 32 32 365 294 1 230 89 17 17 289 -1 unnamed_device 25.1 MiB 1.54 2903 1193 13553 4146 6698 2709 64.6 MiB 0.09 0.00 6.82527 5.54847 -159.396 -5.54847 5.54847 0.24 0.000340769 0.000311467 0.0254812 0.0233158 -1 -1 -1 -1 36 2667 24 6.89349e+06 352346 648988. 2245.63 1.27 0.129417 0.113035 26050 158493 -1 2183 22 1623 2400 146356 36675 4.41775 4.41775 -145.775 -4.41775 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0172307 0.0153579 150 57 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 4.61 vpr 64.64 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30156 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 29 32 378 310 1 246 92 17 17 289 -1 unnamed_device 25.2 MiB 1.49 2857 1221 11684 3249 7028 1407 64.6 MiB 0.07 0.00 5.69689 4.40161 -128.825 -4.40161 4.40161 0.24 0.000347187 0.000318839 0.0212948 0.0195102 -1 -1 -1 -1 30 3093 22 6.89349e+06 436909 556674. 1926.21 1.62 0.150322 0.131694 25186 138497 -1 2297 20 1507 2044 138797 32504 3.501 3.501 -118.443 -3.501 0 0 706193. 2443.58 0.04 0.07 0.12 -1 -1 0.04 0.027885 0.0249954 162 85 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 3.09 vpr 64.28 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30312 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 24.9 MiB 0.72 1910 928 13788 4105 7638 2045 64.3 MiB 0.06 0.00 4.56098 4.02268 -121.319 -4.02268 4.02268 0.25 0.000259422 0.000237335 0.0213947 0.0196035 -1 -1 -1 -1 32 1927 19 6.89349e+06 253689 586450. 2029.24 0.99 0.101249 0.0880851 25474 144626 -1 1681 21 920 1495 107983 25474 2.89716 2.89716 -108.882 -2.89716 0 0 744469. 2576.02 0.04 0.07 0.08 -1 -1 0.04 0.0266531 0.0236216 96 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_087.v common 4.16 vpr 64.99 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29764 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 32 32 373 302 1 241 92 17 17 289 -1 unnamed_device 25.2 MiB 1.26 3226 1286 16652 5101 8812 2739 65.0 MiB 0.10 0.00 7.53678 5.6817 -168.121 -5.6817 5.6817 0.25 0.000349472 0.000320694 0.0296423 0.0271629 -1 -1 -1 -1 34 3248 37 6.89349e+06 394628 618332. 2139.56 1.48 0.155596 0.136385 25762 151098 -1 2485 23 1928 2763 231875 54095 4.63118 4.63118 -153.969 -4.63118 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0185313 0.0165548 156 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_088.v common 3.82 vpr 64.70 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29736 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 397 314 1 256 92 17 17 289 -1 unnamed_device 25.2 MiB 1.82 3241 1349 17066 5543 8987 2536 64.7 MiB 0.11 0.00 6.47017 5.4924 -173.425 -5.4924 5.4924 0.25 0.000365552 0.000330091 0.0320572 0.0293256 -1 -1 -1 -1 32 3371 24 6.89349e+06 394628 586450. 2029.24 0.49 0.0824342 0.0732588 25474 144626 -1 2591 21 1981 2792 182661 43773 4.46865 4.46865 -163.826 -4.46865 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.017704 0.0158097 166 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_089.v common 3.55 vpr 64.38 MiB -1 -1 0.13 17676 1 0.02 -1 -1 30172 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 269 231 1 172 82 17 17 289 -1 unnamed_device 24.9 MiB 1.01 1994 1069 14144 5297 7505 1342 64.4 MiB 0.07 0.00 4.47373 3.85823 -113.356 -3.85823 3.85823 0.25 0.000269263 0.000246111 0.0229361 0.0209552 -1 -1 -1 -1 26 2405 34 6.89349e+06 253689 503264. 1741.40 1.22 0.104104 0.090382 24322 120374 -1 2118 19 1267 1650 143777 33707 3.05266 3.05266 -112.136 -3.05266 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.012389 0.0110027 104 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_090.v common 3.15 vpr 64.09 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30312 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 31 32 245 205 1 153 85 17 17 289 -1 unnamed_device 24.6 MiB 0.82 2028 838 14407 3892 9360 1155 64.1 MiB 0.07 0.00 4.70033 3.85018 -114.048 -3.85018 3.85018 0.24 0.000258947 0.000237202 0.0224492 0.0205414 -1 -1 -1 -1 32 1902 23 6.89349e+06 310065 586450. 2029.24 1.05 0.117197 0.101976 25474 144626 -1 1656 20 933 1613 114014 26385 2.82486 2.82486 -106.443 -2.82486 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.01196 0.0105886 100 4 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_091.v common 3.10 vpr 64.52 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30000 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 24.9 MiB 1.32 2676 1136 9448 2110 6726 612 64.5 MiB 0.06 0.00 5.50572 4.64652 -147.013 -4.64652 4.64652 0.25 0.000337089 0.000309156 0.0178547 0.0163613 -1 -1 -1 -1 32 2903 23 6.89349e+06 338252 586450. 2029.24 0.41 0.0621535 0.0549096 25474 144626 -1 2275 18 1479 2130 167790 37316 3.63095 3.63095 -136.052 -3.63095 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145128 0.0129763 142 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_092.v common 4.39 vpr 64.57 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 356 289 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 1.43 2323 1112 13758 4906 6702 2150 64.6 MiB 0.08 0.00 5.68208 4.94624 -146.779 -4.94624 4.94624 0.25 0.000331787 0.000302979 0.0262302 0.0240273 -1 -1 -1 -1 38 2572 49 6.89349e+06 366440 678818. 2348.85 1.52 0.168236 0.146876 26626 170182 -1 2205 27 1686 2316 190689 61677 4.12995 4.12995 -139.314 -4.12995 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0196348 0.0174401 145 56 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_093.v common 2.83 vpr 64.91 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29788 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 349 260 1 204 101 17 17 289 -1 unnamed_device 24.9 MiB 0.51 2788 1276 12556 3435 8230 891 64.9 MiB 0.09 0.00 6.16499 5.16501 -145.808 -5.16501 5.16501 0.38 0.000394125 0.000363253 0.0265423 0.0244872 -1 -1 -1 -1 32 3172 25 6.89349e+06 521472 586450. 2029.24 0.72 0.0967584 0.0855786 25474 144626 -1 2570 21 1634 3205 242418 55454 4.33309 4.33309 -144.215 -4.33309 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0179264 0.0159944 158 3 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_094.v common 4.27 vpr 64.20 MiB -1 -1 0.17 18440 1 0.03 -1 -1 29780 -1 -1 28 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65736 30 32 316 264 1 208 90 17 17 289 -1 unnamed_device 25.2 MiB 1.21 2512 1137 8934 2329 5933 672 64.2 MiB 0.06 0.00 4.62558 3.87324 -113.147 -3.87324 3.87324 0.26 0.000430676 0.000404412 0.0194294 0.0180078 -1 -1 -1 -1 26 2997 43 6.89349e+06 394628 503264. 1741.40 1.64 0.141375 0.123852 24322 120374 -1 2387 26 1622 2422 199717 53667 3.36211 3.36211 -112.626 -3.36211 0 0 618332. 2139.56 0.02 0.06 0.07 -1 -1 0.02 0.0171514 0.0151399 133 52 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_095.v common 2.50 vpr 64.38 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30560 -1 -1 24 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 27 32 255 219 1 162 83 17 17 289 -1 unnamed_device 24.9 MiB 0.89 1709 895 11423 3598 6289 1536 64.4 MiB 0.06 0.00 5.37186 4.45989 -120.873 -4.45989 4.45989 0.25 0.000258494 0.000236562 0.0197284 0.0181083 -1 -1 -1 -1 32 1885 21 6.89349e+06 338252 586450. 2029.24 0.33 0.0533561 0.0470861 25474 144626 -1 1605 17 829 1207 77343 18883 3.505 3.505 -112.859 -3.505 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110978 0.00988432 104 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_096.v common 5.27 vpr 65.19 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29756 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66756 32 32 421 327 1 271 95 17 17 289 -1 unnamed_device 25.2 MiB 1.78 3336 1650 16943 4550 10611 1782 65.2 MiB 0.17 0.00 5.75687 4.66636 -149.532 -4.66636 4.66636 0.28 0.000384059 0.000352114 0.0541153 0.0500458 -1 -1 -1 -1 32 4257 48 6.89349e+06 436909 586450. 2029.24 1.95 0.218959 0.193276 25474 144626 -1 3241 25 2181 3435 276689 69635 4.34439 4.34439 -149.479 -4.34439 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0212911 0.0189332 181 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_097.v common 3.79 vpr 64.60 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30148 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 31 32 365 296 1 233 89 17 17 289 -1 unnamed_device 24.9 MiB 1.40 2877 1253 10781 3020 6724 1037 64.6 MiB 0.07 0.00 6.6941 5.817 -167.929 -5.817 5.817 0.25 0.000354766 0.00032589 0.0218487 0.0201788 -1 -1 -1 -1 30 2956 23 6.89349e+06 366440 556674. 1926.21 1.02 0.112557 0.0989778 25186 138497 -1 2341 19 1649 2421 144006 35330 4.38675 4.38675 -149.789 -4.38675 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0154389 0.0138086 151 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_098.v common 3.96 vpr 63.84 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29908 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65376 32 32 331 280 1 221 87 17 17 289 -1 unnamed_device 24.9 MiB 1.25 2547 1197 9303 2202 6355 746 63.8 MiB 0.06 0.00 5.09387 4.28945 -141.157 -4.28945 4.28945 0.25 0.00042315 0.000395805 0.019167 0.0177577 -1 -1 -1 -1 28 3036 35 6.89349e+06 324158 531479. 1839.03 1.34 0.126513 0.110677 24610 126494 -1 2512 25 1803 2385 195350 47064 4.2519 4.2519 -146.428 -4.2519 0 0 648988. 2245.63 0.03 0.07 0.07 -1 -1 0.03 0.0238407 0.021067 132 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_099.v common 3.83 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29904 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 326 263 1 203 88 17 17 289 -1 unnamed_device 25.0 MiB 1.30 2319 1186 11593 3417 7038 1138 64.8 MiB 0.07 0.00 6.11951 5.26542 -147.058 -5.26542 5.26542 0.24 0.000321945 0.000295215 0.0228394 0.0210531 -1 -1 -1 -1 30 2530 20 6.89349e+06 338252 556674. 1926.21 1.15 0.135844 0.118798 25186 138497 -1 2079 20 1172 1728 106041 25591 3.68526 3.68526 -129.365 -3.68526 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0173921 0.0156473 131 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_100.v common 3.69 vpr 65.00 MiB -1 -1 0.13 18064 1 0.03 -1 -1 30232 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 31 32 373 294 1 231 91 17 17 289 -1 unnamed_device 25.1 MiB 1.27 2701 1254 13759 3627 8626 1506 65.0 MiB 0.08 0.00 5.36757 4.57215 -129.401 -4.57215 4.57215 0.24 0.000371097 0.000341499 0.0274086 0.0252012 -1 -1 -1 -1 32 2893 23 6.89349e+06 394628 586450. 2029.24 1.04 0.127297 0.11159 25474 144626 -1 2390 20 1697 2539 165581 39636 3.8238 3.8238 -127.582 -3.8238 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0171484 0.0153377 158 50 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_101.v common 3.88 vpr 64.89 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29868 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66444 30 32 325 268 1 210 89 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2500 1222 15731 4428 8998 2305 64.9 MiB 0.09 0.00 5.01568 4.37438 -123.571 -4.37438 4.37438 0.24 0.000307761 0.000281755 0.0263716 0.0241537 -1 -1 -1 -1 34 2819 30 6.89349e+06 380534 618332. 2139.56 1.15 0.118553 0.103653 25762 151098 -1 2471 19 1223 1977 156412 35023 3.48615 3.48615 -117.196 -3.48615 0 0 787024. 2723.27 0.03 0.05 0.09 -1 -1 0.03 0.0169984 0.0150589 134 51 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_102.v common 4.61 vpr 64.93 MiB -1 -1 0.20 18056 1 0.03 -1 -1 29764 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 25.5 MiB 1.70 2913 1236 16468 4324 10879 1265 64.9 MiB 0.10 0.00 5.92998 4.92758 -154.078 -4.92758 4.92758 0.24 0.000375636 0.000345494 0.0296261 0.0271151 -1 -1 -1 -1 32 3235 49 6.89349e+06 338252 586450. 2029.24 1.34 0.160502 0.140912 25474 144626 -1 2641 21 1807 2827 217818 50476 3.81776 3.81776 -142.241 -3.81776 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0167762 0.0149719 143 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_103.v common 4.98 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29592 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 32 32 386 307 1 246 93 17 17 289 -1 unnamed_device 25.2 MiB 1.63 2578 1265 14583 4645 6831 3107 65.0 MiB 0.08 0.00 4.8916 4.45823 -142.35 -4.45823 4.45823 0.24 0.000360905 0.000330749 0.0267126 0.0244643 -1 -1 -1 -1 36 3322 50 6.89349e+06 408721 648988. 2245.63 1.94 0.173141 0.15178 26050 158493 -1 2430 26 2202 3086 217671 55907 3.43671 3.43671 -127.871 -3.43671 0 0 828058. 2865.25 0.03 0.08 0.08 -1 -1 0.03 0.0275492 0.0245357 160 62 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_104.v common 2.65 vpr 64.39 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29828 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 29 32 269 229 1 173 83 17 17 289 -1 unnamed_device 24.9 MiB 0.87 1941 905 12863 3695 7288 1880 64.4 MiB 0.06 0.00 4.94313 4.20923 -126.338 -4.20923 4.20923 0.28 0.000269427 0.000245811 0.0208088 0.0190655 -1 -1 -1 -1 32 1947 26 6.89349e+06 310065 586450. 2029.24 0.38 0.0634184 0.0559623 25474 144626 -1 1640 18 1223 1625 105232 25124 3.02451 3.02451 -110.783 -3.02451 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0116555 0.0103855 108 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_105.v common 3.55 vpr 64.53 MiB -1 -1 0.11 18440 1 0.02 -1 -1 30308 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 310 266 1 198 85 17 17 289 -1 unnamed_device 24.9 MiB 1.00 2331 1018 14593 5365 7180 2048 64.5 MiB 0.07 0.00 5.35099 4.29493 -129.187 -4.29493 4.29493 0.24 0.000296307 0.000271021 0.0248078 0.0226923 -1 -1 -1 -1 34 2466 24 6.89349e+06 295971 618332. 2139.56 1.15 0.108741 0.0947769 25762 151098 -1 1986 19 1370 1939 133873 32096 3.832 3.832 -129.652 -3.832 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0135162 0.0120723 121 58 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_106.v common 3.39 vpr 64.43 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30268 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 31 32 326 261 1 204 89 17 17 289 -1 unnamed_device 24.9 MiB 0.97 2471 1196 14741 4167 8661 1913 64.4 MiB 0.08 0.00 5.98928 4.87948 -139.23 -4.87948 4.87948 0.24 0.000320063 0.000293836 0.024991 0.0228928 -1 -1 -1 -1 26 2979 26 6.89349e+06 366440 503264. 1741.40 1.07 0.104685 0.0918426 24322 120374 -1 2528 23 1727 2832 223076 51486 3.8639 3.8639 -135.445 -3.8639 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0164645 0.0146522 134 33 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_107.v common 3.77 vpr 63.91 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29900 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65440 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.8 MiB 1.12 2013 926 8543 2203 5453 887 63.9 MiB 0.04 0.00 5.29312 4.18332 -115.535 -4.18332 4.18332 0.26 0.000268815 0.00024715 0.0138272 0.0126803 -1 -1 -1 -1 26 2277 48 6.89349e+06 310065 503264. 1741.40 1.30 0.100987 0.0875584 24322 120374 -1 2031 27 1546 2031 172833 51950 3.3714 3.3714 -109.468 -3.3714 0 0 618332. 2139.56 0.02 0.05 0.06 -1 -1 0.02 0.0154285 0.0135584 105 31 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_108.v common 3.52 vpr 63.93 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29880 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 32 32 278 238 1 182 84 17 17 289 -1 unnamed_device 24.7 MiB 1.16 2123 1039 14358 3958 8394 2006 63.9 MiB 0.07 0.00 5.08457 4.36857 -137.465 -4.36857 4.36857 0.24 0.000278263 0.000254499 0.0233188 0.021363 -1 -1 -1 -1 30 2385 23 6.89349e+06 281877 556674. 1926.21 1.07 0.109577 0.0957306 25186 138497 -1 2017 21 1374 2007 134054 31869 3.07751 3.07751 -120.896 -3.07751 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0134373 0.0119178 109 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 3.60 vpr 65.00 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29840 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 31 32 373 300 1 237 92 17 17 289 -1 unnamed_device 25.6 MiB 1.50 2847 1321 9407 2126 6476 805 65.0 MiB 0.06 0.00 5.94996 4.99396 -156.415 -4.99396 4.99396 0.24 0.000346762 0.00031781 0.0173071 0.0158311 -1 -1 -1 -1 28 3256 26 6.89349e+06 408721 531479. 1839.03 0.66 0.0811964 0.0718657 24610 126494 -1 2728 22 2029 2815 203521 48201 3.81684 3.81684 -144.87 -3.81684 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0174056 0.0154965 157 64 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_110.v common 3.81 vpr 63.98 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29852 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65512 31 32 265 230 1 175 83 17 17 289 -1 unnamed_device 24.9 MiB 1.23 1998 822 6203 1282 4444 477 64.0 MiB 0.04 0.00 4.0554 3.59765 -110.566 -3.59765 3.59765 0.26 0.000325594 0.000302519 0.0132653 0.0122948 -1 -1 -1 -1 34 2076 24 6.89349e+06 281877 618332. 2139.56 1.12 0.115819 0.100786 25762 151098 -1 1723 20 1130 1580 102110 25750 2.82336 2.82336 -104.389 -2.82336 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0126467 0.0112452 103 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_111.v common 3.63 vpr 64.95 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30136 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 32 32 349 286 1 221 88 17 17 289 -1 unnamed_device 24.9 MiB 1.25 2652 1326 9253 2409 6050 794 64.9 MiB 0.07 0.00 4.83964 4.21314 -126.908 -4.21314 4.21314 0.26 0.000335167 0.000307637 0.02296 0.0211984 -1 -1 -1 -1 32 2832 23 6.89349e+06 338252 586450. 2029.24 1.03 0.113834 0.099746 25474 144626 -1 2356 20 1336 1987 129392 30987 3.4009 3.4009 -123.821 -3.4009 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0155457 0.0138799 141 57 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_112.v common 4.76 vpr 64.70 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29572 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 31 32 396 325 1 259 94 17 17 289 -1 unnamed_device 25.2 MiB 1.76 2853 1403 14578 4264 8207 2107 64.7 MiB 0.10 0.00 5.59288 4.8279 -156.525 -4.8279 4.8279 0.26 0.000369837 0.000335668 0.0333882 0.0308902 -1 -1 -1 -1 30 3242 26 6.89349e+06 436909 556674. 1926.21 1.56 0.142469 0.12585 25186 138497 -1 2649 19 1916 2730 173100 41045 4.05069 4.05069 -152.083 -4.05069 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0168232 0.0150458 168 91 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_113.v common 3.26 vpr 64.76 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29756 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 303 262 1 200 86 17 17 289 -1 unnamed_device 24.9 MiB 1.33 2386 1003 8213 1905 5885 423 64.8 MiB 0.07 0.00 5.08019 3.80489 -115.807 -3.80489 3.80489 0.25 0.000384058 0.000353865 0.0240162 0.0223341 -1 -1 -1 -1 26 2751 41 6.89349e+06 310065 503264. 1741.40 0.56 0.0757766 0.067046 24322 120374 -1 2325 35 2024 2740 201705 49859 3.37141 3.37141 -124.682 -3.37141 0 0 618332. 2139.56 0.03 0.07 0.07 -1 -1 0.03 0.0273323 0.0239382 121 57 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 3.46 vpr 63.79 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30148 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65324 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.6 MiB 0.81 2269 837 15023 5167 6942 2914 63.8 MiB 0.08 0.00 5.43847 4.34657 -130.295 -4.34657 4.34657 0.24 0.000423514 0.000388067 0.0296063 0.0270771 -1 -1 -1 -1 36 2125 20 6.89349e+06 267783 648988. 2245.63 1.29 0.13798 0.120975 26050 158493 -1 1708 21 1250 1889 158472 38821 3.16246 3.16246 -117.696 -3.16246 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0138878 0.0123302 111 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_115.v common 3.92 vpr 64.39 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29808 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 318 257 1 197 87 17 17 289 -1 unnamed_device 24.9 MiB 1.51 2206 1061 15255 5362 7838 2055 64.4 MiB 0.12 0.00 5.66222 4.93863 -135.261 -4.93863 4.93863 0.38 0.000465778 0.000424965 0.0394743 0.0360442 -1 -1 -1 -1 32 2576 20 6.89349e+06 324158 586450. 2029.24 0.55 0.10291 0.0916188 25474 144626 -1 2067 20 1241 1762 109322 26595 3.75376 3.75376 -127.245 -3.75376 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.014591 0.0129818 130 30 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_116.v common 2.99 vpr 64.83 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30232 -1 -1 28 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 29 32 324 268 1 205 89 17 17 289 -1 unnamed_device 25.2 MiB 1.21 2470 1190 15335 4895 8484 1956 64.8 MiB 0.12 0.00 4.7462 4.04278 -114.91 -4.04278 4.04278 0.25 0.000470059 0.000430443 0.0387134 0.0355344 -1 -1 -1 -1 32 2572 19 6.89349e+06 394628 586450. 2029.24 0.37 0.0791568 0.070506 25474 144626 -1 2079 21 1060 1535 114324 26106 3.1022 3.1022 -107.005 -3.1022 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0151094 0.0134471 136 55 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 3.77 vpr 65.06 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29764 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66620 32 32 393 312 1 243 90 17 17 289 -1 unnamed_device 25.2 MiB 1.77 2982 1296 15567 4292 8859 2416 65.1 MiB 0.11 0.00 6.82244 5.69986 -179.713 -5.69986 5.69986 0.26 0.000519859 0.000488808 0.0338423 0.0310508 -1 -1 -1 -1 32 3149 23 6.89349e+06 366440 586450. 2029.24 0.50 0.0977618 0.086857 25474 144626 -1 2680 23 2091 3202 214974 51581 4.45265 4.45265 -163.975 -4.45265 0 0 744469. 2576.02 0.03 0.06 0.11 -1 -1 0.03 0.0183996 0.016371 162 65 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 3.84 vpr 64.24 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29940 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 24.9 MiB 1.21 1779 858 10231 2722 6503 1006 64.2 MiB 0.07 0.00 3.8889 3.28224 -101.713 -3.28224 3.28224 0.45 0.000385879 0.000354379 0.0241506 0.0220973 -1 -1 -1 -1 30 1861 20 6.89349e+06 253689 556674. 1926.21 0.74 0.0892488 0.0792797 25186 138497 -1 1517 18 846 1343 70273 18201 2.62851 2.62851 -97.2865 -2.62851 0 0 706193. 2443.58 0.04 0.04 0.11 -1 -1 0.04 0.0159301 0.0141792 93 4 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 7.04 vpr 65.12 MiB -1 -1 0.16 18680 1 0.03 -1 -1 30100 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 32 32 412 334 1 269 95 17 17 289 -1 unnamed_device 25.6 MiB 2.35 3112 1429 7871 1651 5611 609 65.1 MiB 0.06 0.00 7.06988 5.66654 -175.904 -5.66654 5.66654 0.34 0.000375537 0.000339759 0.0156753 0.0143834 -1 -1 -1 -1 24 4306 40 6.89349e+06 436909 470940. 1629.55 3.01 0.164231 0.144271 24034 113901 -1 3379 35 3463 4537 442158 133615 5.55244 5.55244 -193.596 -5.55244 0 0 586450. 2029.24 0.02 0.11 0.06 -1 -1 0.02 0.0262324 0.0232024 172 90 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 3.77 vpr 65.05 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30196 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 376 318 1 259 91 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2995 1457 17227 5058 10064 2105 65.1 MiB 0.20 0.00 6.59283 5.06664 -170.928 -5.06664 5.06664 0.28 0.00033737 0.000308852 0.0723416 0.0671243 -1 -1 -1 -1 32 3389 24 6.89349e+06 380534 586450. 2029.24 0.53 0.118774 0.107591 25474 144626 -1 2826 20 2173 2713 238525 51366 4.42408 4.42408 -166.095 -4.42408 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0158806 0.0141647 154 96 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 4.46 vpr 64.99 MiB -1 -1 0.16 18056 1 0.04 -1 -1 30148 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66548 32 32 360 293 1 226 90 17 17 289 -1 unnamed_device 24.9 MiB 1.76 2575 1188 14361 4167 7345 2849 65.0 MiB 0.14 0.00 4.49365 4.14004 -127.133 -4.14004 4.14004 0.44 0.000619044 0.000567785 0.0472235 0.0432217 -1 -1 -1 -1 32 2842 27 6.89349e+06 366440 586450. 2029.24 0.75 0.140806 0.125491 25474 144626 -1 2167 18 1381 1988 128583 31532 3.26765 3.26765 -116.85 -3.26765 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0154305 0.0137976 147 60 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 4.23 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29792 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 396 299 1 240 91 17 17 289 -1 unnamed_device 25.2 MiB 1.61 2868 1421 16615 5234 8988 2393 65.1 MiB 0.10 0.00 6.7782 5.7937 -174.554 -5.7937 5.7937 0.24 0.000377195 0.000345698 0.0328161 0.0301431 -1 -1 -1 -1 32 3522 22 6.89349e+06 380534 586450. 2029.24 1.21 0.139004 0.122484 25474 144626 -1 2816 20 1940 3057 243941 59443 4.77005 4.77005 -160.085 -4.77005 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0206995 0.0185208 167 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 2.39 vpr 63.83 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30220 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65364 30 32 224 207 1 138 79 17 17 289 -1 unnamed_device 24.9 MiB 0.67 1877 553 12416 4327 6159 1930 63.8 MiB 0.05 0.00 3.67846 3.05196 -89.5454 -3.05196 3.05196 0.24 0.000240967 0.000220771 0.0184976 0.0169233 -1 -1 -1 -1 32 1600 50 6.89349e+06 239595 586450. 2029.24 0.41 0.0589787 0.0516028 25474 144626 -1 1097 15 520 670 46236 12957 2.13076 2.13076 -83.1557 -2.13076 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00913946 0.00819187 79 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 2.61 vpr 64.39 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29772 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 30 32 286 239 1 176 85 17 17 289 -1 unnamed_device 25.0 MiB 0.95 1847 961 11617 2788 7841 988 64.4 MiB 0.06 0.00 5.09505 4.48403 -138.191 -4.48403 4.48403 0.24 0.000279345 0.000255614 0.018968 0.0173529 -1 -1 -1 -1 32 1983 22 6.89349e+06 324158 586450. 2029.24 0.36 0.0566188 0.0499704 25474 144626 -1 1730 24 1374 2089 138709 33546 3.26135 3.26135 -120.882 -3.26135 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0151238 0.0133003 120 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 3.15 vpr 64.11 MiB -1 -1 0.12 18064 1 0.02 -1 -1 30120 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65644 32 32 296 247 1 187 86 17 17 289 -1 unnamed_device 24.9 MiB 1.47 2379 1099 6512 1400 4709 403 64.1 MiB 0.04 0.00 5.39489 4.40387 -142.112 -4.40387 4.40387 0.24 0.000297099 0.000272253 0.0116876 0.0106979 -1 -1 -1 -1 32 2461 22 6.89349e+06 310065 586450. 2029.24 0.38 0.049722 0.04369 25474 144626 -1 2000 16 1036 1938 114017 27700 3.4032 3.4032 -130.786 -3.4032 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0118866 0.0106258 117 34 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 2.54 vpr 64.23 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29744 -1 -1 22 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65776 25 32 216 194 1 138 79 17 17 289 -1 unnamed_device 24.9 MiB 0.81 1444 623 8698 3045 3646 2007 64.2 MiB 0.04 0.00 4.2673 3.669 -85.1281 -3.669 3.669 0.24 0.000223849 0.000204642 0.0128618 0.011782 -1 -1 -1 -1 34 1477 40 6.89349e+06 310065 618332. 2139.56 0.48 0.0554996 0.0482709 25762 151098 -1 1167 17 675 1007 65080 17606 2.74431 2.74431 -76.9396 -2.74431 0 0 787024. 2723.27 0.03 0.02 0.08 -1 -1 0.03 0.00963225 0.00859939 88 29 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 4.70 vpr 64.68 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30176 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66232 32 32 376 307 1 242 90 17 17 289 -1 unnamed_device 25.2 MiB 1.91 3246 1394 13155 3589 8227 1339 64.7 MiB 0.10 0.00 5.69179 4.38685 -135.96 -4.38685 4.38685 0.27 0.00035587 0.000326364 0.0317988 0.0292838 -1 -1 -1 -1 28 3647 48 6.89349e+06 366440 531479. 1839.03 1.37 0.175343 0.154197 24610 126494 -1 2835 24 2070 3115 222959 51695 3.94436 3.94436 -138.765 -3.94436 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0182264 0.0161589 155 72 -1 -1 -1 -1 +fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 3.95 vpr 64.75 MiB -1 -1 0.21 18056 1 0.03 -1 -1 29792 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 31 32 409 331 1 264 96 17 17 289 -1 unnamed_device 25.2 MiB 1.66 3421 1405 9951 2248 6876 827 64.8 MiB 0.07 0.00 6.59166 4.95446 -159.482 -4.95446 4.95446 0.26 0.000368094 0.000337513 0.0186641 0.0170676 -1 -1 -1 -1 26 4013 41 6.89349e+06 465097 503264. 1741.40 0.83 0.0913258 0.0808566 24322 120374 -1 3056 21 2358 3239 221980 53983 4.35939 4.35939 -160.133 -4.35939 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0179468 0.0160232 174 90 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt index 2aa73474bd1..d3a8f8c6f9c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 346.85 vpr 1.15 GiB -1 -1 34.22 328308 27 15.05 -1 -1 138296 -1 -1 6514 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1202304 641 128 52026 52154 1 22211 7283 96 96 9216 clb auto 299.9 MiB 22.55 298865 9039475 3705368 5259409 74698 1174.1 MiB 99.58 0.80 15.6652 -38327.4 -15.6652 15.6652 30.26 0.094057 0.0773765 12.1503 10.1571 -1 -1 -1 -1 52 436843 31 2.87242e+08 7.85314e+07 3.22264e+07 3496.79 84.03 34.4054 28.6501 876764 7891077 -1 405234 17 92350 208771 15162225 3092956 14.5295 14.5295 -35310.2 -14.5295 0 0 3.95636e+07 4292.92 2.28 8.25 6.87 -1 -1 2.28 3.81485 3.27893 44137 14777 -1 -1 -1 -1 - k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 4.27 vpr 64.04 MiB -1 -1 0.87 26712 11 0.25 -1 -1 33516 -1 -1 51 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65580 54 51 461 512 1 281 156 11 11 121 clb auto 24.7 MiB 0.16 2356 11469 1919 8714 836 64.0 MiB 0.12 0.00 5.64506 -244.834 -5.64506 5.64506 0.13 0.00146196 0.00133342 0.0458162 0.0422569 -1 -1 -1 -1 48 5066 26 2.09946e+06 614805 317060. 2620.33 1.31 0.36651 0.319953 10252 71876 -1 4625 16 1697 8023 407060 95904 5.13857 5.13857 -230.591 -5.13857 0 0 382250. 3159.09 0.01 0.15 0.06 -1 -1 0.01 0.0499744 0.0448408 351 351 -1 -1 -1 -1 - k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 399.84 vpr 1.07 GiB -1 -1 21.81 218380 1 3.70 -1 -1 145176 -1 -1 5511 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1117152 641 128 55563 47815 1 19087 6280 89 89 7921 clb auto 300.2 MiB 18.05 230047 8461724 3459022 4875110 127592 1091.0 MiB 204.82 1.70 7.09259 -24894.9 -7.09259 7.09259 27.46 0.0722137 0.0620773 11.1205 9.22983 -1 -1 -1 -1 66 309563 40 2.46893e+08 6.92128e+07 3.31523e+07 4185.37 68.55 29.6499 24.5503 846610 8512169 -1 289933 30 70505 114345 10785585 2091912 4.98188 4.98188 -21717.1 -4.98188 0 0 4.13768e+07 5223.69 2.61 7.93 7.55 -1 -1 2.61 4.60052 3.86111 40340 2050 -1 -1 -1 -1 - k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.46 vpr 64.67 MiB -1 -1 0.88 25784 4 0.13 -1 -1 33088 -1 -1 47 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66224 54 51 503 502 1 293 152 10 10 100 clb auto 25.4 MiB 1.53 2207 8657 1268 6725 664 64.7 MiB 0.12 0.00 4.72142 -243.243 -4.72142 4.72142 0.10 0.00138683 0.00126889 0.0371909 0.0344533 -1 -1 -1 -1 44 4688 46 1.94278e+06 590226 231289. 2312.89 1.36 0.376354 0.326721 8470 54129 -1 4028 17 1662 7146 368098 92041 3.78868 3.78868 -208.146 -3.78868 0 0 291571. 2915.71 0.01 0.14 0.05 -1 -1 0.01 0.0559049 0.0498459 310 281 -1 -1 -1 -1 - k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 415.20 vpr 1.04 GiB -1 -1 21.75 218308 1 4.05 -1 -1 145180 -1 -1 5620 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1088640 641 128 55563 47815 1 19638 6389 89 89 7921 clb auto 308.1 MiB 52.99 226704 9072863 3788850 5116203 167810 1063.1 MiB 189.74 1.45 7.32093 -25503.3 -7.32093 7.32093 27.00 0.0695794 0.0596563 11.1854 9.32085 -1 -1 -1 -1 62 301435 41 2.47551e+08 7.12563e+07 3.13221e+07 3954.32 64.63 30.1669 25.0298 822850 7925305 -1 280695 33 74632 110486 9460418 1906659 4.74051 4.74051 -21753 -4.74051 0 0 3.86383e+07 4877.96 2.36 8.35 6.62 -1 -1 2.36 5.11529 4.30965 40780 2050 -1 -1 -1 -1 - k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.14 vpr 64.61 MiB -1 -1 0.49 25988 4 0.16 -1 -1 33144 -1 -1 50 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66164 54 51 503 502 1 302 155 11 11 121 clb auto 25.5 MiB 0.55 2264 11803 2091 8793 919 64.6 MiB 0.15 0.01 4.6074 -231.734 -4.6074 4.6074 0.13 0.00143538 0.00131584 0.0463156 0.0428406 -1 -1 -1 -1 46 4761 36 2.13871e+06 633900 304223. 2514.24 1.58 0.37716 0.328993 10384 69934 -1 4032 15 1433 6356 300467 73316 3.80829 3.80829 -202.73 -3.80829 0 0 371547. 3070.64 0.01 0.12 0.06 -1 -1 0.01 0.0507242 0.0453634 307 281 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 285.87 vpr 1.07 GiB -1 -1 21.15 328044 27 17.19 -1 -1 136772 -1 -1 6530 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1127196 641 128 52026 52154 1 22146 7299 96 96 9216 clb auto 332.2 MiB 15.82 1 293360 9065987 3711370 5281819 72798 1100.8 MiB 87.32 0.64 63.9835 15.6932 -38098.7 -15.6932 15.6932 27.45 0.0673124 0.0602963 10.1706 8.43326 -1 -1 -1 -1 52 432440 35 2.87242e+08 7.87243e+07 3.22264e+07 3496.79 70.10 28.8986 24.6513 876764 7891077 -1 399137 17 95401 216864 15038479 3106649 13.6903 13.6903 -35069.4 -13.6903 0 0 3.95636e+07 4292.92 2.24 7.32 5.18 -1 -1 2.24 3.2763 2.91469 44106 14777 -1 -1 -1 -1 +k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 2.47 vpr 65.25 MiB -1 -1 0.45 26432 11 0.21 -1 -1 33212 -1 -1 50 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66820 54 51 461 512 1 279 155 11 11 121 clb auto 26.2 MiB 0.08 3521 2357 11387 1976 8700 711 65.3 MiB 0.07 0.00 6.1966 5.68811 -245.341 -5.68811 5.68811 0.09 0.000716615 0.0006463 0.0243569 0.0221714 -1 -1 -1 -1 46 5194 30 2.09946e+06 602750 304223. 2514.24 0.73 0.182335 0.162552 10132 69752 -1 4547 19 1747 8058 386967 94105 5.17977 5.17977 -229.771 -5.17977 0 0 371547. 3070.64 0.01 0.10 0.04 -1 -1 0.01 0.0385667 0.0352693 351 351 -1 -1 -1 -1 +k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 339.81 vpr 953.70 MiB -1 -1 13.28 218372 1 3.24 -1 -1 144528 -1 -1 5506 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 976588 641 128 55563 47815 1 19075 6275 89 89 7921 clb auto 330.3 MiB 10.44 1 214102 8568519 3563555 4885647 119317 953.7 MiB 169.32 1.12 17.4207 6.98821 -24570.4 -6.98821 6.98821 25.47 0.0471077 0.041108 9.13248 7.51499 -1 -1 -1 -1 64 294624 49 2.46893e+08 6.915e+07 3.22737e+07 4074.44 78.53 27.676 23.1791 838690 8307980 -1 274225 28 72425 118832 10979794 2166804 4.60329 4.60329 -21219.4 -4.60329 0 0 4.04365e+07 5104.97 2.30 5.71 5.61 -1 -1 2.30 2.97998 2.59225 40344 2050 -1 -1 -1 -1 +k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 4.44 vpr 65.57 MiB -1 -1 0.41 25348 4 0.13 -1 -1 32876 -1 -1 48 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67144 54 51 503 502 1 293 153 10 10 100 clb auto 26.7 MiB 1.29 3063 2216 11196 1953 8114 1129 65.6 MiB 0.14 0.01 5.24197 4.75513 -244.6 -4.75513 4.75513 0.09 0.00169788 0.00158536 0.0530931 0.0496201 -1 -1 -1 -1 50 4239 34 1.94278e+06 602784 264954. 2649.54 1.48 0.359688 0.32242 8770 59529 -1 3822 16 1455 6320 297317 74232 3.99954 3.99954 -212.879 -3.99954 0 0 317040. 3170.40 0.01 0.18 0.04 -1 -1 0.01 0.0756285 0.0693569 310 281 -1 -1 -1 -1 +k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 357.91 vpr 981.56 MiB -1 -1 12.96 218396 1 4.88 -1 -1 144524 -1 -1 5615 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1005120 641 128 55563 47815 1 19621 6384 89 89 7921 clb auto 336.8 MiB 44.88 1 218506 8826737 3646134 5035828 144775 981.6 MiB 155.92 1.22 19.4565 7.31966 -25233.7 -7.31966 7.31966 24.82 0.0474495 0.0415552 8.20397 6.77827 -1 -1 -1 -1 60 294604 45 2.47551e+08 7.11929e+07 3.04132e+07 3839.56 73.27 27.1474 22.801 814930 7734163 -1 276739 33 78983 115921 10759440 2250313 4.51897 4.51897 -21514.2 -4.51897 0 0 3.78426e+07 4777.50 2.27 6.83 4.86 -1 -1 2.27 3.77776 3.25281 40785 2050 -1 -1 -1 -1 +k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 3.71 vpr 65.89 MiB -1 -1 0.41 25352 4 0.13 -1 -1 32860 -1 -1 49 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67476 54 51 503 502 1 301 154 11 11 121 clb auto 26.8 MiB 0.37 3371 2219 12102 2212 9004 886 65.9 MiB 0.08 0.00 5.48793 4.4172 -224.447 -4.4172 4.4172 0.09 0.000674884 0.000607414 0.0249059 0.0227895 -1 -1 -1 -1 46 4716 45 2.13871e+06 621222 304223. 2514.24 1.64 0.233573 0.207329 10384 69934 -1 3942 18 1779 7182 348702 84785 3.54243 3.54243 -193.203 -3.54243 0 0 371547. 3070.64 0.01 0.09 0.04 -1 -1 0.01 0.0361351 0.0331666 307 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt index e0e23492818..10684a36519 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt @@ -1,11 +1,11 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_2ripple_N8_22nm.xml Md5Core.v common 541.33 vpr 770.48 MiB -1 -1 21.57 219052 1 3.94 -1 -1 145160 -1 -1 2904 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 788976 641 128 55563 47815 1 17837 3673 65 65 4225 clb auto 278.4 MiB 280.64 186842 4139415 1628153 2426823 84439 770.5 MiB 80.11 0.65 6.85172 -24425.5 -6.85172 6.85172 17.37 0.0707807 0.0606116 10.8556 9.00171 -1 -1 -1 -1 86 266896 42 1.34217e+08 4.20381e+07 2.31978e+07 5490.61 95.85 37.0767 30.5473 551762 6310377 -1 239670 19 85960 107325 12022295 2121435 5.37037 5.37037 -22498.9 -5.37037 0 0 2.90884e+07 6884.83 1.53 5.92 5.28 -1 -1 1.53 3.24584 2.77988 21038 2050 -1 -1 -1 -1 - k6_frac_2ripple_N8_22nm.xml cordic.v common 7.58 vpr 65.10 MiB -1 -1 0.88 26100 4 0.16 -1 -1 33024 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66664 54 51 503 502 1 316 138 9 9 81 clb auto 26.1 MiB 3.78 1956 11174 2060 8307 807 65.1 MiB 0.13 0.00 4.40854 -233.833 -4.40854 4.40854 0.09 0.00139097 0.00128641 0.0504025 0.0467374 -1 -1 -1 -1 56 4041 27 1.45065e+06 477698 231774. 2861.41 1.17 0.353028 0.308187 7704 54090 -1 3517 18 1771 6187 313268 82102 4.02896 4.02896 -216.237 -4.02896 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0573414 0.0511544 225 281 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml Md5Core.v common 445.49 vpr 768.55 MiB -1 -1 21.93 218372 1 4.17 -1 -1 145216 -1 -1 2904 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 787000 641 128 55563 47815 1 17906 3673 65 65 4225 clb auto 273.5 MiB 187.96 185308 3941126 1565098 2300167 75861 768.6 MiB 89.53 0.80 6.8947 -23916.3 -6.8947 6.8947 17.72 0.0715102 0.0611769 10.6329 8.87437 -1 -1 -1 -1 86 262207 37 1.34928e+08 4.2735e+07 2.31978e+07 5490.61 81.66 34.9922 28.9773 551762 6310377 -1 236506 17 80887 101963 10950479 1939027 5.59715 5.59715 -21989.7 -5.59715 0 0 2.90884e+07 6884.83 1.64 5.62 5.31 -1 -1 1.64 3.04009 2.59505 20989 2050 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml cordic.v common 5.96 vpr 64.87 MiB -1 -1 0.87 26208 4 0.16 -1 -1 33076 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66424 54 51 503 502 1 318 138 9 9 81 clb auto 25.9 MiB 0.40 1964 10462 1843 7559 1060 64.9 MiB 0.13 0.00 4.28518 -225.617 -4.28518 4.28518 0.09 0.00139646 0.00129195 0.0476616 0.0441834 -1 -1 -1 -1 56 4128 31 1.45905e+06 485618 231774. 2861.41 2.57 0.547183 0.474234 7704 54090 -1 3583 18 1731 6262 331465 85566 3.8968 3.8968 -212.026 -3.8968 0 0 286113. 3532.26 0.01 0.14 0.05 -1 -1 0.01 0.058103 0.0518196 225 281 -1 -1 -1 -1 - k6_frac_N8_22nm.xml Md5Core.v common 523.72 vpr 809.32 MiB -1 -1 35.88 328152 27 14.52 -1 -1 138636 -1 -1 3446 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 828744 641 128 52026 52154 1 22420 4215 70 70 4900 clb auto 269.8 MiB 211.66 265423 4326406 1648229 2614689 63488 809.3 MiB 79.80 0.65 14.952 -39387.3 -14.952 14.952 20.28 0.0925834 0.0810563 12.6496 10.7217 -1 -1 -1 -1 84 394620 43 1.54829e+08 4.64245e+07 2.64571e+07 5399.40 108.95 44.8309 37.5465 624050 7235563 -1 356794 20 108067 230531 16879775 3154299 13.0725 13.0725 -36269.1 -13.0725 0 0 3.34846e+07 6833.59 1.94 9.36 5.72 -1 -1 1.94 4.65498 4.01829 24663 14777 -1 -1 -1 -1 - k6_frac_N8_22nm.xml cordic.v common 4.95 vpr 64.28 MiB -1 -1 0.95 26424 11 0.25 -1 -1 33660 -1 -1 34 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65824 54 51 461 512 1 317 139 9 9 81 clb auto 25.0 MiB 0.23 2204 9473 1828 7093 552 64.3 MiB 0.12 0.00 6.42199 -256.014 -6.42199 6.42199 0.09 0.00144714 0.00133734 0.0443724 0.0410787 -1 -1 -1 -1 62 4693 48 1.41552e+06 458048 249781. 3083.72 1.55 0.41392 0.360399 7884 59488 -1 3923 19 2092 8192 403186 97926 5.39904 5.39904 -231.32 -5.39904 0 0 310465. 3832.90 0.01 0.10 0.04 -1 -1 0.01 0.0365187 0.0331706 252 351 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml Md5Core.v common 968.02 vpr 871.61 MiB -1 -1 22.34 218328 1 3.90 -1 -1 145312 -1 -1 3580 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 892524 641 128 55563 47815 1 19465 4349 71 71 5041 clb auto 262.5 MiB 670.29 210279 5114045 1917429 3043210 153406 871.6 MiB 143.83 0.80 7.61884 -24559.3 -7.61884 7.61884 21.38 0.0719772 0.0594682 10.7407 8.89088 -1 -1 -1 -1 72 286581 46 1.58244e+08 5.00245e+07 2.39867e+07 4758.32 62.14 31.0052 25.5746 615390 6416121 -1 266321 24 92304 125385 12396060 2405052 4.93927 4.93927 -21502.9 -4.93927 0 0 3.00078e+07 5952.75 1.71 7.10 5.50 -1 -1 1.71 3.83741 3.21004 25723 2050 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml cordic.v common 5.83 vpr 64.57 MiB -1 -1 0.88 26136 4 0.16 -1 -1 33044 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66124 54 51 503 502 1 304 138 9 9 81 clb auto 25.3 MiB 2.08 2002 12954 2480 9062 1412 64.6 MiB 0.20 0.01 4.43013 -227.708 -4.43013 4.43013 0.09 0.001451 0.0013363 0.0685664 0.0632597 -1 -1 -1 -1 56 4228 32 1.43308e+06 461137 231774. 2861.41 1.26 0.391145 0.341818 7704 54090 -1 3725 17 1917 7166 373067 93632 3.65072 3.65072 -196.427 -3.65072 0 0 286113. 3532.26 0.01 0.09 0.03 -1 -1 0.01 0.0324143 0.0294926 234 281 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml Md5Core.v common 472.40 vpr 866.96 MiB -1 -1 22.33 218376 1 4.13 -1 -1 145204 -1 -1 3485 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 887772 641 128 55563 47815 1 18425 4254 71 71 5041 clb auto 256.6 MiB 191.79 205408 4896722 1844424 2914068 138230 867.0 MiB 129.30 1.04 8.03131 -25587.9 -8.03131 8.03131 21.08 0.0733517 0.0590529 10.6832 8.73949 -1 -1 -1 -1 64 273108 50 1.5868e+08 4.91153e+07 2.16513e+07 4295.04 61.30 30.7872 25.3336 590190 5755241 -1 250871 18 71120 89065 8566793 1619750 5.5524 5.5524 -21928.1 -5.5524 0 0 2.72404e+07 5403.77 1.82 6.19 4.71 -1 -1 1.82 3.42355 2.88442 25749 2050 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml cordic.v common 4.49 vpr 64.21 MiB -1 -1 0.92 26136 4 0.16 -1 -1 33152 -1 -1 35 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65752 54 51 503 502 1 303 140 9 9 81 clb auto 25.4 MiB 0.68 1940 13934 2921 9841 1172 64.2 MiB 0.17 0.00 4.47128 -234.847 -4.47128 4.47128 0.09 0.00140285 0.00129011 0.0597002 0.0551005 -1 -1 -1 -1 56 3999 30 1.43728e+06 493284 231774. 2861.41 1.11 0.375638 0.327858 7704 54090 -1 3545 17 1758 6326 315468 81095 3.68106 3.68106 -203.624 -3.68106 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0539124 0.0479125 251 281 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_2ripple_N8_22nm.xml Md5Core.v common 477.93 vpr 699.03 MiB -1 -1 15.73 218396 1 3.59 -1 -1 144908 -1 -1 2893 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 715804 641 128 55563 47815 1 17875 3662 65 65 4225 clb auto 307.3 MiB 229.77 653595 188180 4010050 1589381 2339755 80914 698.8 MiB 74.46 0.60 15.2096 7.56088 -24817.3 -7.56088 7.56088 15.68 0.0492048 0.042965 7.99151 6.70431 -1 -1 -1 -1 92 259836 45 1.34217e+08 4.18788e+07 2.45933e+07 5820.91 106.38 34.176 28.8777 568658 6739433 -1 238307 25 84571 105591 11115783 1991214 6.27776 6.27776 -22967 -6.27776 0 0 3.06352e+07 7250.94 1.72 5.76 4.59 -1 -1 1.72 3.18855 2.77683 20993 2050 -1 -1 -1 -1 +k6_frac_2ripple_N8_22nm.xml cordic.v common 5.88 vpr 66.43 MiB -1 -1 0.42 25312 4 0.13 -1 -1 32620 -1 -1 34 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68024 54 51 503 502 1 316 139 9 9 81 clb auto 27.1 MiB 2.92 2831 1984 7678 1282 5509 887 66.4 MiB 0.06 0.00 4.51901 4.18969 -226.44 -4.18969 4.18969 0.06 0.000666802 0.000609419 0.0195881 0.0180803 -1 -1 -1 -1 58 4540 50 1.45065e+06 492173 237595. 2933.27 1.32 0.289584 0.254751 7864 57025 -1 3555 20 1939 7105 362500 91101 3.89871 3.89871 -212.35 -3.89871 0 0 298762. 3688.42 0.01 0.10 0.03 -1 -1 0.01 0.0438049 0.0398469 226 281 -1 -1 -1 -1 +k6_frac_2uripple_N8_22nm.xml Md5Core.v common 370.63 vpr 696.85 MiB -1 -1 13.58 217508 1 3.90 -1 -1 144528 -1 -1 2897 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 713572 641 128 55563 47815 1 17888 3666 65 65 4225 clb auto 301.8 MiB 158.38 643219 185056 4072386 1563668 2435367 73351 696.8 MiB 66.14 0.59 16.3713 7.04442 -24207.9 -7.04442 7.04442 16.43 0.055064 0.0485492 7.86424 6.61941 -1 -1 -1 -1 86 262236 34 1.34928e+08 4.2632e+07 2.31978e+07 5490.61 81.10 27.3467 23.1128 551762 6310377 -1 236085 23 81064 102545 11776128 2047879 6.1643 6.1643 -22374.2 -6.1643 0 0 2.90884e+07 6884.83 1.62 5.64 4.36 -1 -1 1.62 3.20849 2.80174 20965 2050 -1 -1 -1 -1 +k6_frac_2uripple_N8_22nm.xml cordic.v common 3.07 vpr 66.24 MiB -1 -1 0.43 25360 4 0.20 -1 -1 32860 -1 -1 33 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67832 54 51 503 502 1 318 138 9 9 81 clb auto 27.1 MiB 0.36 2931 2050 13310 2770 9570 970 66.2 MiB 0.09 0.00 4.3236 4.15816 -225.982 -4.15816 4.15816 0.06 0.000742946 0.000682425 0.0328962 0.0301738 -1 -1 -1 -1 56 4421 38 1.45905e+06 485618 231774. 2861.41 0.93 0.244522 0.218208 7704 54090 -1 3718 18 1920 6861 352217 88853 3.68306 3.68306 -206.395 -3.68306 0 0 286113. 3532.26 0.01 0.09 0.05 -1 -1 0.01 0.03847 0.0354053 227 281 -1 -1 -1 -1 +k6_frac_N8_22nm.xml Md5Core.v common 451.99 vpr 788.38 MiB -1 -1 21.29 328008 27 14.03 -1 -1 137544 -1 -1 3471 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 807304 641 128 52026 52154 1 22539 4240 71 71 5041 clb auto 302.9 MiB 198.91 971668 249965 4292115 1627870 2599391 64854 788.4 MiB 59.25 0.47 52.2374 15.4038 -39114.5 -15.4038 15.4038 28.59 0.0690838 0.0616158 10.1516 8.54447 -1 -1 -1 -1 82 376055 32 1.56446e+08 4.67613e+07 2.66411e+07 5284.89 89.69 34.2976 29.2554 631278 7194181 -1 345823 16 104618 223290 16671777 3186307 13.7481 13.7481 -36094 -13.7481 0 0 3.32761e+07 6601.10 1.86 7.39 4.64 -1 -1 1.86 3.26381 2.92376 24649 14777 -1 -1 -1 -1 +k6_frac_N8_22nm.xml cordic.v common 3.05 vpr 65.40 MiB -1 -1 0.46 26504 11 0.21 -1 -1 33124 -1 -1 33 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 54 51 461 512 1 307 138 9 9 81 clb auto 26.1 MiB 0.13 3103 2218 10462 2076 7758 628 65.4 MiB 0.07 0.00 6.80674 6.00424 -251.72 -6.00424 6.00424 0.06 0.000725644 0.000663618 0.0277173 0.0254463 -1 -1 -1 -1 60 4772 48 1.41552e+06 444576 242836. 2997.97 1.31 0.311025 0.277224 7804 58296 -1 4045 19 1952 7820 394587 97023 5.48514 5.48514 -233.228 -5.48514 0 0 304930. 3764.57 0.01 0.10 0.04 -1 -1 0.01 0.0390285 0.035773 250 351 -1 -1 -1 -1 +k6_frac_ripple_N8_22nm.xml Md5Core.v common 880.65 vpr 786.22 MiB -1 -1 12.64 217632 1 3.52 -1 -1 144524 -1 -1 3573 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 805092 641 128 55563 47815 1 19435 4342 71 71 5041 clb auto 289.0 MiB 580.57 819752 209041 5067686 1879984 3018557 169145 786.2 MiB 123.00 0.77 15.3089 8.61024 -24476.7 -8.61024 8.61024 19.39 0.0540455 0.0439781 8.09228 6.53093 -1 -1 -1 -1 74 282704 34 1.58244e+08 4.99267e+07 2.44980e+07 4859.74 108.08 34.8268 29.2592 620430 6551051 -1 266640 25 86742 116693 12206521 2336167 5.88317 5.88317 -21677.4 -5.88317 0 0 3.04825e+07 6046.92 1.75 5.63 4.53 -1 -1 1.75 2.84807 2.46262 25727 2050 -1 -1 -1 -1 +k6_frac_ripple_N8_22nm.xml cordic.v common 4.85 vpr 65.68 MiB -1 -1 0.75 25352 4 0.19 -1 -1 32876 -1 -1 33 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67252 54 51 503 502 1 305 138 9 9 81 clb auto 26.7 MiB 1.90 2824 1925 10818 2107 7677 1034 65.7 MiB 0.09 0.00 4.87184 4.35815 -225.348 -4.35815 4.35815 0.06 0.000770335 0.000672667 0.0289517 0.0267081 -1 -1 -1 -1 54 4063 43 1.43308e+06 461137 226270. 2793.45 0.99 0.2461 0.216024 7624 52756 -1 3291 17 1788 6579 287632 74898 3.83626 3.83626 -198.879 -3.83626 0 0 280165. 3458.82 0.01 0.09 0.03 -1 -1 0.01 0.0383915 0.0351202 234 281 -1 -1 -1 -1 +k6_frac_uripple_N8_22nm.xml Md5Core.v common 388.87 vpr 781.73 MiB -1 -1 13.78 217608 1 3.59 -1 -1 144908 -1 -1 3472 641 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 800492 641 128 55563 47815 1 18248 4241 71 71 5041 clb auto 285.5 MiB 160.70 748459 205594 4842515 1817314 2868610 156591 781.7 MiB 103.27 0.79 17.6617 8.00284 -25797.5 -8.00284 8.00284 22.43 0.0525316 0.041828 7.49622 6.1714 -1 -1 -1 -1 60 281470 45 1.5868e+08 4.89321e+07 2.04516e+07 4057.04 56.14 22.8967 19.2291 575070 5378021 -1 255823 17 76566 95763 9476991 1821430 5.31054 5.31054 -22200.8 -5.31054 0 0 2.55408e+07 5066.62 1.34 4.26 3.31 -1 -1 1.34 2.0631 1.81096 25722 2050 -1 -1 -1 -1 +k6_frac_uripple_N8_22nm.xml cordic.v common 3.50 vpr 65.62 MiB -1 -1 0.45 25356 4 0.14 -1 -1 32508 -1 -1 35 54 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67200 54 51 503 502 1 301 140 9 9 81 clb auto 26.4 MiB 0.52 2717 2105 7763 1290 5799 674 65.6 MiB 0.06 0.00 4.88573 4.50668 -234.843 -4.50668 4.50668 0.06 0.000670214 0.000611502 0.01904 0.0174694 -1 -1 -1 -1 60 4031 25 1.43728e+06 493284 242836. 2997.97 1.34 0.287424 0.253314 7944 58396 -1 3718 20 1983 8095 422416 104597 3.58761 3.58761 -202.534 -3.58761 0 0 304930. 3764.57 0.01 0.14 0.05 -1 -1 0.01 0.0558313 0.0505463 250 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt index bc4a9702b59..9e219b5070f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt @@ -1,31 +1,31 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.41 vpr 66.85 MiB -1 -1 0.34 22268 3 0.10 -1 -1 37000 -1 54240 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68452 99 130 344 474 1 226 298 12 12 144 clb auto 27.2 MiB 0.07 661 69948 21317 34488 14143 66.8 MiB 0.19 0.00 1.84343 -120.716 -1.84343 1.84343 0.15 0.000836305 0.000777868 0.0624432 0.0579886 -1 -1 -1 -1 48 1234 11 5.66058e+06 4.21279e+06 394078. 2736.65 1.13 0.388411 0.354166 13382 75762 -1 1152 12 449 726 34037 10619 1.91136 1.91136 -134.16 -1.91136 -1.28997 -0.320482 503207. 3494.49 0.02 0.04 0.08 -1 -1 0.02 0.0268156 0.0249636 0.01041 0.2485 0.08202 0.6695 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 11.54 vpr 70.42 MiB -1 -1 0.52 27052 15 0.44 -1 -1 37612 -1 56036 39 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72112 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 30.4 MiB 0.30 5587 92394 30880 53838 7676 70.4 MiB 0.63 0.01 21.0975 -1536.06 -21.0975 21.0975 0.31 0.00264219 0.0024523 0.255431 0.237213 -1 -1 -1 -1 54 12491 42 1.21132e+07 4.08187e+06 835850. 3265.04 5.79 1.11973 1.03745 26248 167850 -1 9804 18 3129 6329 829951 256686 22.2714 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betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 453388 114 102 21994 21904 1 11311 1551 50 50 2500 memory auto 176.8 MiB 37.63 527891 152473 961769 343404 598984 19381 395.1 MiB 22.16 0.26 188.143 78.619 -52094.9 -78.619 78.619 8.49 0.0880813 0.0718688 7.76816 6.30967 -1 -1 -1 -1 96 230097 37 1.47946e+08 9.69225e+07 1.58254e+07 6330.17 146.76 34.5737 28.6409 343768 3324272 -1 205895 21 41994 164446 9667422 1829878 79.5395 79.5395 -63191.9 -79.5395 -18.2976 -0.296573 1.97871e+07 7914.84 0.86 5.21 2.46 -1 -1 0.86 3.20712 2.74314 0.08309 0.4204 0.01144 0.5681 +k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 1.91 vpr 66.28 MiB -1 -1 0.23 18360 3 0.07 -1 -1 32736 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67872 99 130 344 474 1 225 298 12 12 144 clb auto 26.3 MiB 0.10 1615 739 67958 20256 33438 14264 66.3 MiB 0.12 0.00 2.01929 1.59858 -120.502 -1.59858 1.59858 0.11 0.000557558 0.000521981 0.0411842 0.038502 -1 -1 -1 -1 32 1638 22 5.66058e+06 4.21279e+06 295695. 2053.44 0.22 0.118546 0.109119 12440 56522 -1 1436 9 375 579 29706 10063 1.98015 1.98015 -145.204 -1.98015 -0.629583 -0.296573 361905. 2513.23 0.01 0.02 0.03 -1 -1 0.01 0.0161662 0.0151379 0.01017 0.2587 0.06764 0.6737 +k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 6.74 vpr 69.04 MiB -1 -1 0.33 23356 15 0.40 -1 -1 33440 -1 54340 38 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70696 162 96 1009 950 1 700 301 16 16 256 mult_36 auto 29.7 MiB 0.47 9504 5751 92029 29345 55557 7127 69.0 MiB 0.38 0.01 25.1574 21.4416 -1522.86 -21.4416 21.4416 0.20 0.00166215 0.00153914 0.166428 0.154929 -1 -1 -1 -1 46 12599 35 1.21132e+07 4.02797e+06 761464. 2974.47 2.16 0.63689 0.590691 25952 154797 -1 9895 19 3064 6567 851943 250422 22.8964 22.8964 -1711.52 -22.8964 0 0 979054. 3824.43 0.03 0.22 0.10 -1 -1 0.03 0.0911635 0.0860046 0.007797 0.3514 0.01629 0.6323 +k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 632.30 vpr 425.63 MiB -1 -1 52.65 342488 123 67.76 -1 -1 77000 -1 116408 1290 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 435844 114 102 21994 21904 1 11883 1559 50 50 2500 memory auto 174.3 MiB 154.90 542801 148542 977447 334536 618400 24511 425.6 MiB 20.03 0.16 165.745 79.9647 -51541.2 -79.9647 79.9647 9.85 0.0462859 0.0415889 6.23686 4.93392 -1 -1 -1 -1 88 223852 29 1.47946e+08 9.73536e+07 1.53362e+07 6134.50 265.99 24.631 20.2444 343368 3288204 -1 200471 19 40596 158712 8780039 1707271 81.2246 81.2246 -65781.9 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8.10 vpr 69.72 MiB -1 -1 0.36 23352 15 0.30 -1 -1 33820 -1 54340 38 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71392 162 96 1009 950 1 696 301 16 16 256 mult_36 auto 30.0 MiB 0.52 9113 5761 84973 28251 50600 6122 69.7 MiB 0.35 0.01 23.8418 21.6725 -1535.01 -21.6725 21.6725 0.20 0.00167188 0.00155658 0.151533 0.141298 -1 -1 -1 -1 48 12122 33 1.21132e+07 4.02797e+06 791884. 3093.30 3.54 0.808887 0.74702 26208 159478 -1 9984 19 3201 6676 954607 275743 23.0792 23.0792 -1746.36 -23.0792 0 0 1.01413e+06 3961.44 0.03 0.23 0.09 -1 -1 0.03 0.0901325 0.0849653 0.008091 0.3418 0.01583 0.6424 +k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 638.49 vpr 425.22 MiB -1 -1 53.11 340704 123 75.20 -1 -1 77572 -1 116408 1198 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 435424 114 102 21994 21904 1 11199 1467 50 50 2500 memory auto 173.7 MiB 160.18 498306 142361 884659 311124 554810 18725 425.2 MiB 18.63 0.17 175.7 78.9128 -49795.1 -78.9128 78.9128 9.86 0.0494021 0.0446317 6.20357 4.97966 -1 -1 -1 -1 86 212684 30 1.47946e+08 9.23952e+07 1.49824e+07 5992.98 257.20 25.7378 21.2495 340872 3235144 -1 192023 18 37543 153253 8529801 1673802 79.8203 79.8203 -61388.2 -79.8203 -28.4501 -0.29436 1.89069e+07 7562.76 0.79 4.41 2.28 -1 -1 0.79 2.59244 2.28805 0.08429 0.3846 0.01159 0.6038 +k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.13 vpr 66.50 MiB -1 -1 0.23 18748 3 0.07 -1 -1 32700 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68096 99 130 344 474 1 224 298 12 12 144 clb auto 26.7 MiB 0.10 1602 677 71938 23237 33899 14802 66.5 MiB 0.15 0.00 2.12998 1.84564 -120.965 -1.84564 1.84564 0.11 0.000760103 0.000723485 0.0543791 0.0512037 -1 -1 -1 -1 32 1650 13 5.66058e+06 4.21279e+06 307825. 2137.67 0.36 0.184989 0.171256 12860 59602 -1 1400 11 452 691 34201 11876 1.88346 1.88346 -144.078 -1.88346 -0.484813 -0.296573 375846. 2610.04 0.01 0.03 0.04 -1 -1 0.01 0.0208013 0.0193133 0.01053 0.2499 0.06921 0.6809 +k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 8.05 vpr 69.89 MiB -1 -1 0.49 23352 15 0.30 -1 -1 33476 -1 53996 38 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71568 162 96 1009 950 1 704 301 16 16 256 mult_36 auto 30.4 MiB 0.40 9299 5715 87997 27573 53784 6640 69.9 MiB 0.38 0.01 22.6764 20.6663 -1473.39 -20.6663 20.6663 0.22 0.00359067 0.00347295 0.165973 0.155071 -1 -1 -1 -1 46 12065 29 1.21132e+07 4.02797e+06 791147. 3090.42 3.64 0.803986 0.743326 26792 163197 -1 9651 15 2919 6056 796294 221717 22.291 22.291 -1649.91 -22.291 0 0 1.01637e+06 3970.19 0.03 0.20 0.09 -1 -1 0.03 0.0802319 0.0758941 0.008006 0.3497 0.01632 0.6339 +k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 485.23 vpr 463.73 MiB -1 -1 54.58 342120 123 73.41 -1 -1 77576 -1 116408 1282 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 474864 114 102 21994 21904 1 11706 1551 50 50 2500 memory auto 172.6 MiB 183.20 537524 153309 952795 327484 605097 20214 463.7 MiB 19.91 0.17 159.734 79.8376 -52451.3 -79.8376 79.8376 11.27 0.0471696 0.0423752 6.07508 4.93741 -1 -1 -1 -1 88 231712 31 1.47946e+08 9.69225e+07 1.59255e+07 6370.18 72.63 20.3706 16.975 353736 3474828 -1 204409 17 37217 148875 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+k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 8.39 vpr 69.99 MiB -1 -1 0.56 23356 15 0.45 -1 -1 33808 -1 54340 38 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71672 162 96 1009 950 1 704 301 16 16 256 mult_36 auto 30.4 MiB 0.48 9299 5715 87997 27573 53784 6640 70.0 MiB 0.38 0.01 22.6764 20.6663 -1473.39 -20.6663 20.6663 0.21 0.00167207 0.00155769 0.162554 0.151353 -1 -1 -1 -1 46 12397 31 1.21132e+07 4.02797e+06 791147. 3090.42 3.53 0.754145 0.697395 26792 163197 -1 9805 17 3101 6515 893935 246691 22.3382 22.3382 -1672.66 -22.3382 0 0 1.01637e+06 3970.19 0.03 0.22 0.09 -1 -1 0.03 0.0855505 0.0808185 0.008312 0.3386 0.01569 0.6458 +k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 514.51 vpr 468.14 MiB -1 -1 54.59 340880 123 66.74 -1 -1 77192 -1 116412 1189 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 479372 114 102 21994 21904 1 10803 1458 50 50 2500 memory auto 173.6 MiB 205.93 506208 141993 860914 287837 555087 17990 468.1 MiB 19.97 0.18 173.854 77.809 -53343.1 -77.809 77.809 11.37 0.058387 0.052435 6.55994 5.25064 -1 -1 -1 -1 86 210901 20 1.47946e+08 9.19101e+07 1.55613e+07 6224.53 95.11 21.2605 17.5729 351240 3418312 -1 189357 19 34668 146207 8378386 1660456 79.4888 79.4888 -63710.1 -79.4888 -20.6468 -0.292146 1.95825e+07 7833.01 0.82 4.66 2.29 -1 -1 0.82 2.8036 2.44094 0.08776 0.3779 0.01182 0.6103 +k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.92 vpr 66.19 MiB -1 -1 0.31 18744 3 0.10 -1 -1 32740 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67776 99 130 344 474 1 225 298 12 12 144 clb auto 26.3 MiB 0.10 1615 746 67958 18270 34570 15118 66.2 MiB 0.11 0.00 2.01486 1.59858 -123.171 -1.59858 1.59858 0.10 0.000556701 0.000520594 0.0409336 0.0382267 -1 -1 -1 -1 38 1453 18 5.66058e+06 4.21279e+06 319130. 2216.18 0.84 0.240772 0.219266 12522 62564 -1 1256 9 390 597 28390 9347 1.91586 1.91586 -139.414 -1.91586 -0.519581 -0.320482 406292. 2821.48 0.02 0.04 0.07 -1 -1 0.02 0.0249994 0.0232439 0.01048 0.2589 0.07296 0.6681 +k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 7.44 vpr 69.52 MiB -1 -1 0.35 23352 15 0.30 -1 -1 33448 -1 54344 38 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71192 162 96 1009 950 1 700 301 16 16 256 mult_36 auto 29.7 MiB 0.45 9328 5492 86989 27657 51981 7351 69.5 MiB 0.37 0.01 24.0124 21.2051 -1567.83 -21.2051 21.2051 0.19 0.00168462 0.001571 0.159436 0.148658 -1 -1 -1 -1 48 12122 34 1.21132e+07 4.02797e+06 756778. 2956.16 2.79 0.668469 0.620661 25228 149258 -1 9821 21 3409 7006 953600 270168 22.4255 22.4255 -1694.34 -22.4255 0 0 968034. 3781.38 0.03 0.24 0.09 -1 -1 0.03 0.0968556 0.0912177 0.007714 0.3551 0.01683 0.628 +k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 617.65 vpr 395.10 MiB -1 -1 59.81 339204 123 70.26 -1 -1 77108 -1 116408 1325 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 404580 114 102 21994 21904 1 11955 1594 50 50 2500 memory auto 175.0 MiB 120.88 545909 151828 1053285 379121 652784 21380 393.1 MiB 22.00 0.18 211.344 80.3034 -52037 -80.3034 80.3034 8.39 0.0493259 0.0426176 6.56156 5.30077 -1 -1 -1 -1 88 232639 46 1.47946e+08 9.924e+07 1.46563e+07 5862.50 274.59 25.8876 21.3956 331272 3068748 -1 207629 21 45022 171190 9772327 1836347 81.5961 81.5961 -64327.1 -81.5961 -24.5559 -0.29436 1.83775e+07 7351.00 0.80 5.09 2.23 -1 -1 0.80 2.88577 2.49127 0.0801 0.4096 0.01157 0.5789 +k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 2.09 vpr 66.26 MiB -1 -1 0.25 18744 3 0.07 -1 -1 32736 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67848 99 130 344 474 1 225 298 12 12 144 clb auto 26.3 MiB 0.08 1559 664 64973 19384 31587 14002 66.3 MiB 0.11 0.00 1.91921 1.59858 -120.912 -1.59858 1.59858 0.10 0.000570431 0.000533463 0.0398962 0.0373491 -1 -1 -1 -1 48 1146 11 5.66058e+06 4.21279e+06 394078. 2736.65 0.33 0.121566 0.111929 13382 75762 -1 1214 9 433 677 31444 9588 1.94957 1.94957 -134.318 -1.94957 -1.10762 -0.29768 503207. 3494.49 0.01 0.03 0.05 -1 -1 0.01 0.0208467 0.0194099 0.01183 0.2373 0.07076 0.692 +k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 7.46 vpr 69.05 MiB -1 -1 0.34 23360 15 0.46 -1 -1 33808 -1 54344 38 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70704 162 96 1009 950 1 700 301 16 16 256 mult_36 auto 29.6 MiB 0.82 9328 5492 86989 27657 51981 7351 69.0 MiB 0.41 0.01 24.0124 21.2051 -1567.83 -21.2051 21.2051 0.19 0.00457576 0.0042881 0.184297 0.172051 -1 -1 -1 -1 48 12614 43 1.21132e+07 4.02797e+06 756778. 2956.16 2.05 0.671949 0.62339 25228 149258 -1 9813 21 3311 6933 923000 260867 22.3848 22.3848 -1667.23 -22.3848 0 0 968034. 3781.38 0.04 0.38 0.15 -1 -1 0.04 0.162403 0.15266 0.008004 0.3409 0.01625 0.6428 +k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 417.50 vpr 407.57 MiB -1 -1 51.36 340776 123 65.72 -1 -1 77944 -1 116408 1237 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 417356 114 102 21994 21904 1 11319 1506 50 50 2500 memory auto 174.6 MiB 117.47 510273 146262 916180 316752 580447 18981 392.9 MiB 29.07 0.18 165.87 79.0039 -52422.3 -79.0039 79.0039 8.86 0.06359 0.0575998 10.4538 8.54795 -1 -1 -1 -1 88 228519 39 1.47946e+08 9.44971e+07 1.46563e+07 5862.50 80.09 30.4837 25.1306 331272 3068748 -1 202165 20 43563 170190 10468459 1963493 80.5091 80.5091 -64425 -80.5091 -28.7444 -0.217304 1.83775e+07 7351.00 0.78 5.22 2.53 -1 -1 0.78 2.88415 2.48287 0.08172 0.3986 0.01152 0.5898 +k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.51 vpr 66.29 MiB -1 -1 0.35 18748 3 0.07 -1 -1 32164 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67884 99 130 344 474 1 224 298 12 12 144 clb auto 26.3 MiB 0.16 1602 666 71938 23977 33264 14697 66.3 MiB 0.18 0.00 2.12112 1.84343 -121.24 -1.84343 1.84343 0.11 0.000569735 0.000533646 0.0633907 0.0590458 -1 -1 -1 -1 48 1355 18 5.66058e+06 4.21279e+06 394078. 2736.65 0.37 0.185219 0.170081 13382 75762 -1 1110 12 455 720 27368 8107 1.92497 1.92497 -135.097 -1.92497 -1.55249 -0.320482 503207. 3494.49 0.01 0.03 0.05 -1 -1 0.01 0.0195482 0.0182461 0.01038 0.2431 0.0817 0.6752 +k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 9.87 vpr 69.59 MiB -1 -1 0.43 23360 15 0.45 -1 -1 33444 -1 54344 37 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71260 162 96 1009 950 1 700 300 16 16 256 mult_36 auto 30.0 MiB 0.37 9485 5610 94582 32807 54533 7242 69.6 MiB 0.52 0.01 23.4051 20.8518 -1522.69 -20.8518 20.8518 0.19 0.0017459 0.00162984 0.238561 0.22249 -1 -1 -1 -1 56 11497 31 1.21132e+07 3.97408e+06 870502. 3400.40 4.78 1.06486 0.985301 26504 172068 -1 9372 19 3152 6553 767916 254054 22.0135 22.0135 -1616.86 -22.0135 0 0 1.11200e+06 4343.75 0.03 0.26 0.11 -1 -1 0.03 0.121125 0.114779 0.008056 0.36 0.0171 0.6229 +k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 431.79 vpr 403.17 MiB -1 -1 57.52 340456 123 73.46 -1 -1 77196 -1 116412 1313 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 412844 114 102 21994 21904 1 11874 1582 50 50 2500 memory auto 175.5 MiB 127.72 524305 149710 996694 350454 623863 22377 393.6 MiB 26.24 0.20 203.639 80.9643 -51545.9 -80.9643 80.9643 8.39 0.0657084 0.0526311 8.69857 7.16568 -1 -1 -1 -1 94 223929 33 1.47946e+08 9.85932e+07 1.55181e+07 6207.23 67.00 26.1341 21.847 341268 3271592 -1 206441 20 44988 173109 9748126 1854113 82.7058 82.7058 -65880.3 -82.7058 -20.8209 -0.193384 1.95446e+07 7817.85 1.28 7.30 4.37 -1 -1 1.28 4.23242 3.61957 0.08268 0.4153 0.01156 0.5731 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 2.50 vpr 66.00 MiB -1 -1 0.22 17984 3 0.07 -1 -1 32052 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67588 99 130 344 474 1 223 298 12 12 144 clb auto 26.7 MiB 0.09 1533 708 65968 20934 31709 13325 66.0 MiB 0.11 0.00 1.94397 1.59858 -119.385 -1.59858 1.59858 0.10 0.000559731 0.000523779 0.0400831 0.0375076 -1 -1 -1 -1 46 1248 19 5.66058e+06 4.21279e+06 378970. 2631.74 0.79 0.311108 0.284597 13238 73581 -1 1204 9 412 659 29582 9323 1.90944 1.90944 -132.99 -1.90944 -1.05698 -0.322548 486261. 3376.82 0.01 0.03 0.05 -1 -1 0.01 0.0177437 0.0167297 0.01201 0.2303 0.07038 0.6994 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 10.58 vpr 69.70 MiB -1 -1 0.58 22696 15 0.47 -1 -1 33808 -1 54340 37 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71368 162 96 1009 950 1 700 300 16 16 256 mult_36 auto 30.0 MiB 0.55 9485 5610 94582 32808 54547 7227 69.7 MiB 0.39 0.01 23.4051 20.8518 -1522.66 -20.8518 20.8518 0.19 0.00166218 0.00154141 0.169989 0.158279 -1 -1 -1 -1 56 11809 46 1.21132e+07 3.97408e+06 870502. 3400.40 5.43 1.03813 0.961056 26504 172068 -1 9483 23 3566 7596 912328 301551 22.4383 22.4383 -1675.76 -22.4383 0 0 1.11200e+06 4343.75 0.03 0.25 0.11 -1 -1 0.03 0.104618 0.0981207 0.008278 0.3493 0.01636 0.6344 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 567.43 vpr 394.45 MiB -1 -1 51.45 339968 123 70.70 -1 -1 76424 -1 116412 1207 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 403920 114 102 21994 21904 1 11085 1476 50 50 2500 memory auto 173.7 MiB 130.64 491408 141971 866676 294452 552810 19414 391.9 MiB 17.82 0.15 158.585 79.1521 -48519.8 -79.1521 79.1521 8.23 0.0453742 0.0406504 5.90749 4.79132 -1 -1 -1 -1 86 219171 50 1.47946e+08 9.28803e+07 1.43148e+07 5725.91 226.89 25.5151 20.9431 328776 3019144 -1 195661 23 42037 165667 9419021 1798243 80.1516 80.1516 -60422.3 -80.1516 -31.1111 -0.295467 1.81111e+07 7244.46 0.94 6.49 2.12 -1 -1 0.94 3.85264 3.3137 0.08223 0.3879 0.01173 0.6003 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt index 8d6884970eb..276468e2908 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt @@ -1,15 +1,15 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 98.48 parmys 238.48 MiB -1 -1 62.65 244200 13 8.25 -1 -1 47788 -1 49624 326 257 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 95576 257 32 5008 5040 1 2954 615 23 23 529 clb auto 50.5 MiB 2.76 20267 220191 65143 146065 8983 93.3 MiB 2.97 0.04 8.82032 -3904.7 -8.82032 8.82032 0.54 0.0109643 0.0098333 1.02884 0.902188 -1 -1 -1 -1 56 33645 24 2.70004e+07 1.75694e+07 1.92373e+06 3636.54 6.22 3.27588 2.85668 56706 387443 -1 30010 16 11550 36095 972511 199422 9.40635 9.40635 -3964.62 -9.40635 0 0 2.45466e+06 4640.18 0.09 0.82 0.33 -1 -1 0.09 0.508209 0.459137 0.01648 0.4272 0.03377 0.5391 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 94.21 parmys 306.69 MiB -1 -1 21.16 314052 7 13.24 -1 -1 60844 -1 50612 549 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 136868 36 100 6778 6878 1 3144 685 30 30 900 clb auto 67.3 MiB 3.50 42466 287395 83633 184471 19291 113.8 MiB 5.19 0.06 5.74861 -2247.23 -5.74861 5.74861 1.03 0.0222208 0.0200972 1.955 1.66503 -1 -1 -1 -1 66 68658 45 4.8774e+07 2.95878e+07 3.99156e+06 4435.07 27.65 7.52931 6.32406 104036 803752 -1 60922 16 14883 67597 2789200 373708 5.76735 5.76735 -2377.78 -5.76735 0 0 4.95347e+06 5503.86 0.20 1.71 0.69 -1 -1 0.20 0.908064 0.803825 0.02605 0.351 0.06511 0.5839 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 24.14 vpr 68.57 MiB -1 -1 17.73 31664 4 0.24 -1 -1 34328 -1 55248 53 195 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70220 195 193 1087 1280 1 610 442 15 15 225 io auto 28.4 MiB 0.31 3111 131716 33861 86359 11496 68.6 MiB 0.67 0.01 2.49928 -1087.72 -2.49928 2.49928 0.23 0.00362287 0.00338275 0.298018 0.277768 -1 -1 -1 -1 40 5849 18 1.03862e+07 3.40438e+06 568276. 2525.67 1.78 1.09849 1.00863 21262 112936 -1 5416 11 1616 2529 155491 45590 2.72859 2.72859 -1209.59 -2.72859 -0.959406 -0.246 712852. 3168.23 0.02 0.09 0.07 -1 -1 0.02 0.0607763 0.057325 0.01365 0.3769 0.05606 0.567 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.23 vpr 63.89 MiB -1 -1 0.49 18176 3 0.10 -1 -1 33044 -1 53092 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65428 99 130 344 474 1 226 298 12 12 144 clb auto 24.1 MiB 0.08 678 66963 19395 33485 14083 63.9 MiB 0.23 0.00 1.86362 -122.41 -1.86362 1.86362 0.14 0.00130445 0.00123497 0.0907109 0.085881 -1 -1 -1 -1 52 1254 11 5.66058e+06 4.21279e+06 419432. 2912.72 0.65 0.338628 0.310581 13810 82561 -1 1175 7 368 599 29659 8862 1.9806 1.9806 -135.825 -1.9806 -0.309826 -0.0782318 551878. 3832.49 0.02 0.04 0.08 -1 -1 0.02 0.0250196 0.0231993 0.01031 0.263 0.08354 0.6535 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 10.16 vpr 68.16 MiB -1 -1 0.74 23332 15 0.35 -1 -1 34092 -1 54824 39 162 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69796 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 28.2 MiB 0.19 5587 92394 30880 53838 7676 68.2 MiB 0.69 0.01 21.0975 -1536.06 -21.0975 21.0975 0.26 0.00337966 0.00317219 0.323022 0.303359 -1 -1 -1 -1 56 11812 30 1.21132e+07 4.08187e+06 870502. 3400.40 4.17 1.16452 1.07293 26504 172068 -1 9609 16 2935 5927 775463 239759 22.3005 22.3005 -1636.88 -22.3005 0 0 1.11200e+06 4343.75 0.04 0.29 0.15 -1 -1 0.04 0.13141 0.122082 0.007854 0.3765 0.01734 0.6061 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 7.88 vpr 65.00 MiB -1 -1 0.61 21868 16 0.27 -1 -1 33428 -1 53744 25 66 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66560 66 96 616 557 1 415 192 16 16 256 mult_36 auto 25.5 MiB 0.17 3625 36690 9459 22826 4405 65.0 MiB 0.32 0.01 17.203 -935.064 -17.203 17.203 0.26 0.00236496 0.0022302 0.166486 0.157037 -1 -1 -1 -1 40 8373 37 1.21132e+07 3.32735e+06 642278. 2508.90 3.53 0.766237 0.703647 23952 127161 -1 7217 17 2534 5167 951988 292757 18.0101 18.0101 -1019.64 -18.0101 0 0 805949. 3148.24 0.02 0.19 0.08 -1 -1 0.02 0.05209 0.0486566 0.007411 0.3353 0.01978 0.6449 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 440.60 vpr 461.59 MiB -1 -1 84.00 349248 123 64.46 -1 -1 78572 -1 117272 1375 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 472672 114 102 21994 21904 1 11802 1644 50 50 2500 memory auto 155.4 MiB 20.55 160790 1049136 374899 655277 18960 461.6 MiB 26.29 0.22 78.4871 -53143.2 -78.4871 78.4871 9.75 0.0621978 0.0545143 7.35439 6.13837 -1 -1 -1 -1 94 240662 29 1.47946e+08 1.01935e+08 1.55181e+07 6207.23 162.29 28.9908 23.8912 341268 3271592 -1 217509 21 44132 167614 9994098 1867129 81.2261 81.2261 -64082.4 -81.2261 -12.841 -0.29436 1.95446e+07 7817.85 0.86 6.13 3.06 -1 -1 0.86 3.42933 2.93557 0.08134 0.4302 0.01139 0.5585 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 70.13 vpr 332.00 MiB -1 -1 18.29 128412 5 3.25 -1 -1 56812 -1 73340 470 506 47 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 339964 506 553 3055 3608 1 2790 1576 50 50 2500 memory auto 45.7 MiB 4.81 15429 1147451 561958 401565 183928 332.0 MiB 5.51 0.07 7.14518 -1819.3 -7.14518 7.14518 9.87 0.0227758 0.020582 2.93349 2.63053 -1 -1 -1 -1 38 22365 17 1.47946e+08 5.10868e+07 6.86584e+06 2746.33 11.85 8.32526 7.54939 251304 1421084 -1 21433 18 3916 5150 995348 263030 7.69019 7.69019 -2049.85 -7.69019 -5.04137 -0.293253 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28.03 vpr 76.09 MiB -1 -1 9.24 55960 7 2.30 -1 -1 37416 -1 59040 157 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77920 193 205 2234 2439 1 1179 560 20 20 400 memory auto 35.6 MiB 1.10 9842 228953 80249 124571 24133 76.1 MiB 1.72 0.02 5.08439 -2926.08 -5.08439 5.08439 0.43 0.00685575 0.00620383 0.738776 0.665656 -1 -1 -1 -1 48 17744 33 2.07112e+07 1.12014e+07 1.23055e+06 3076.38 6.37 2.5483 2.26983 40448 245963 -1 15329 16 4566 11562 627458 139494 5.47739 5.47739 -3135.16 -5.47739 -11.584 -0.360359 1.57502e+06 3937.55 0.06 0.44 0.22 -1 -1 0.06 0.280677 0.254763 0.02856 0.2221 0.02552 0.7523 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 63.07 vpr 106.00 MiB -1 -1 7.93 68908 27 4.13 -1 -1 38580 -1 61144 234 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 108548 385 394 3906 4237 1 2373 1016 27 27 729 io auto 46.0 MiB 2.92 31525 572776 227317 322407 23052 88.3 MiB 5.07 0.06 14.4133 -13461.7 -14.4133 14.4133 0.83 0.0160926 0.0150256 1.89286 1.74364 -1 -1 -1 -1 78 51645 44 3.93038e+07 1.41032e+07 3.65949e+06 5019.88 29.17 7.69214 7.06424 90401 760319 -1 44396 14 10279 35511 1944665 349659 14.8103 14.8103 -13960.4 -14.8103 0 0 4.63207e+06 6354.00 0.16 1.07 0.66 -1 -1 0.16 0.591618 0.549921 0.02224 0.4637 0.02666 0.5097 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 25.27 vpr 77.84 MiB -1 -1 6.25 46808 8 0.90 -1 -1 37872 -1 60796 133 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79708 235 305 2600 2761 1 1501 680 19 19 361 io auto 36.8 MiB 2.09 12500 263712 91208 158948 13556 77.8 MiB 1.99 0.03 5.38636 -2731.89 -5.38636 5.38636 0.39 0.00825643 0.00765916 0.774605 0.712384 -1 -1 -1 -1 56 23995 47 1.72706e+07 1.00919e+07 1.27879e+06 3542.35 6.04 2.65451 2.42437 38159 255829 -1 20300 15 5879 16147 1393547 361528 5.87661 5.87661 -3009.11 -5.87661 -1.26427 -0.201639 1.63234e+06 4521.70 0.07 0.66 0.22 -1 -1 0.07 0.333764 0.30935 0.02386 0.4083 0.02598 0.5657 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 19.44 vpr 78.34 MiB -1 -1 4.20 47476 21 2.24 -1 -1 40644 -1 45784 147 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80220 38 36 2570 2606 1 1050 221 17 17 289 clb auto 37.3 MiB 1.10 9478 36239 7889 25786 2564 78.3 MiB 0.76 0.01 14.6977 -2591.44 -14.6977 14.6977 0.30 0.00627054 0.00560905 0.378906 0.335347 -1 -1 -1 -1 46 16543 25 1.34605e+07 7.92242e+06 830882. 2875.03 3.43 1.51759 1.31374 28231 166010 -1 13884 15 4024 11917 367875 68444 15.3347 15.3347 -2866.69 -15.3347 0 0 1.06831e+06 3696.59 0.04 0.39 0.14 -1 -1 0.04 0.261218 0.233045 0.006476 0.3635 0.02972 0.6068 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5304.23 vpr 1.66 GiB -1 -1 692.05 1442556 64 3350.31 -1 -1 347144 -1 317188 6851 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1741944 36 356 125423 124208 1 34881 7429 98 98 9604 clb auto 660.2 MiB 73.61 461903 10223866 4318975 5823833 81058 1701.1 MiB 186.47 1.32 63.3139 -299631 -63.3139 63.3139 39.62 0.235404 0.202231 35.8753 30.2278 -1 -1 -1 -1 80 612389 32 5.9175e+08 4.67016e+08 5.28775e+07 5505.77 350.18 119.658 98.779 1236252 11146124 -1 575490 18 116226 373166 21552241 4233065 64.9427 64.9427 -370561 -64.9427 0 0 6.66202e+07 6936.71 3.07 14.93 8.56 -1 -1 3.07 9.99565 8.64031 0.27 0.3629 0.01392 0.6231 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 73.91 parmys 233.23 MiB -1 -1 39.47 238824 13 7.95 -1 -1 46764 -1 48996 327 257 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 96536 257 32 5008 5040 1 2943 616 23 23 529 clb auto 54.8 MiB 2.79 65213 20720 212836 62576 141404 8856 94.3 MiB 2.16 0.03 15.6864 8.68111 -3946.45 -8.68111 8.68111 0.47 0.00900431 0.00825416 0.809596 0.685169 -1 -1 -1 -1 54 36711 43 2.70004e+07 1.76233e+07 1.84580e+06 3489.22 7.98 3.562 3.08331 56178 377761 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0.5746 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 15.19 vpr 70.11 MiB -1 -1 10.61 30332 4 0.19 -1 -1 34124 -1 54840 52 195 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71796 195 193 1087 1280 1 610 441 15 15 225 io auto 30.0 MiB 0.19 7614 3059 146427 37859 95262 13306 70.1 MiB 0.42 0.01 3.20593 2.49928 -1069.9 -2.49928 2.49928 0.17 0.00182089 0.00169146 0.184374 0.171367 -1 -1 -1 -1 38 6113 40 1.03862e+07 3.35049e+06 544128. 2418.35 1.13 0.604765 0.560239 21038 109288 -1 5298 14 1719 2545 149969 42488 2.49938 2.49938 -1173.25 -2.49938 -0.366048 -0.154403 690492. 3068.85 0.02 0.12 0.06 -1 -1 0.02 0.0807398 0.0762167 0.01471 0.3796 0.05512 0.5653 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 2.53 vpr 65.32 MiB -1 -1 0.23 18360 3 0.08 -1 -1 32348 -1 52608 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66884 99 130 344 474 1 225 298 12 12 144 clb auto 25.9 MiB 0.05 1615 746 67958 18270 34570 15118 65.3 MiB 0.13 0.00 2.01486 1.59858 -123.171 -1.59858 1.59858 0.11 0.000556191 0.000520549 0.0495332 0.0464577 -1 -1 -1 -1 38 1499 18 5.66058e+06 4.21279e+06 319130. 2216.18 0.69 0.227149 0.207861 12522 62564 -1 1252 9 384 592 28238 9313 1.91586 1.91586 -140.767 -1.91586 -0.519581 -0.320482 406292. 2821.48 0.02 0.05 0.08 -1 -1 0.02 0.0293074 0.0273435 0.0104 0.2593 0.07351 0.6672 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 8.38 vpr 69.14 MiB -1 -1 0.36 22972 15 0.30 -1 -1 33488 -1 54344 39 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70796 162 96 1009 950 1 708 302 16 16 256 mult_36 auto 30.0 MiB 0.17 9283 5447 78226 20759 50449 7018 69.1 MiB 0.55 0.01 23.1618 21.0975 -1526.6 -21.0975 21.0975 0.21 0.00330278 0.00307022 0.260633 0.24323 -1 -1 -1 -1 46 12326 45 1.21132e+07 4.08187e+06 727248. 2840.81 4.06 0.987618 0.914723 24972 144857 -1 9837 18 3344 6799 857275 248767 22.0372 22.0372 -1631.88 -22.0372 0 0 934704. 3651.19 0.03 0.25 0.09 -1 -1 0.03 0.105117 0.0992267 0.007635 0.3555 0.01709 0.6274 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 6.01 vpr 66.57 MiB -1 -1 0.28 21820 16 0.30 -1 -1 33456 -1 53260 25 66 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68172 66 96 616 557 1 413 192 16 16 256 mult_36 auto 27.8 MiB 0.16 5839 3600 33925 8855 22033 3037 66.6 MiB 0.16 0.00 18.5797 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29.1843 24.0513 326276 2968264 -1 209371 19 45363 173487 10455005 1964601 80.3198 80.3198 -64807.2 -80.3198 -16.7054 -0.295467 1.77686e+07 7107.43 0.90 5.81 2.30 -1 -1 0.90 3.12869 2.68349 0.07831 0.407 0.01163 0.5813 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 52.70 vpr 304.03 MiB -1 -1 11.10 123576 5 4.06 -1 -1 56180 -1 72900 463 506 45 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 311328 506 553 3055 3608 1 2790 1567 50 50 2500 memory auto 51.4 MiB 2.49 38121 16032 1138817 560483 396028 182306 304.0 MiB 4.30 0.05 10.0192 8.1793 -1876.61 -8.1793 8.1793 8.82 0.0151622 0.014182 2.36885 2.18985 -1 -1 -1 -1 38 23425 15 1.47946e+08 4.96135e+07 6.86584e+06 2746.33 9.51 6.26379 5.86537 251304 1421084 -1 22431 19 3940 5274 1035253 269611 8.62851 8.62851 -2150.71 -8.62851 -2.64826 -0.292146 8.69095e+06 3476.38 0.52 0.87 1.07 -1 -1 0.52 0.67084 0.634949 0.1419 0.1545 0.03969 0.8058 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 11.14 vpr 71.76 MiB -1 -1 0.89 25268 2 0.13 -1 -1 33312 -1 59472 29 311 15 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73484 311 156 972 1128 1 953 511 28 28 784 memory auto 31.5 MiB 0.32 19380 8779 212879 80847 122346 9686 70.8 MiB 0.75 0.01 4.64689 4.01099 -4636.11 -4.01099 4.01099 0.72 0.00267918 0.00237848 0.370373 0.330948 -1 -1 -1 -1 46 13615 18 4.25198e+07 9.78293e+06 2.40571e+06 3068.51 4.48 1.46611 1.31834 79818 491339 -1 13091 12 2437 2782 609856 172667 4.39426 4.39426 -4975.9 -4.39426 -18.8574 -0.359474 3.09729e+06 3950.62 0.11 0.22 0.30 -1 -1 0.11 0.114983 0.106778 0.08453 0.1621 0.01936 0.8185 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 20.19 vpr 77.92 MiB -1 -1 5.94 52388 7 2.11 -1 -1 38364 -1 58368 156 193 5 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79792 193 205 2234 2439 1 1179 559 20 20 400 memory auto 38.3 MiB 0.70 19798 9243 232960 80121 128094 24745 77.9 MiB 1.37 0.01 6.68534 4.93811 -2978.4 -4.93811 4.93811 0.33 0.003984 0.00362373 0.591618 0.530389 -1 -1 -1 -1 48 17116 41 2.07112e+07 1.11475e+07 1.23055e+06 3076.38 4.08 1.8516 1.65979 40448 245963 -1 15026 17 4638 11384 567227 126883 5.14369 5.14369 -3220.63 -5.14369 -9.04127 -0.360359 1.57502e+06 3937.55 0.05 0.37 0.15 -1 -1 0.05 0.268917 0.249398 0.02986 0.2145 0.02596 0.7596 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 44.90 vpr 97.20 MiB -1 -1 4.85 67128 27 4.33 -1 -1 41292 -1 60432 239 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 99528 385 394 3906 4237 1 2372 1021 27 27 729 io auto 50.3 MiB 1.86 62812 31588 571450 225577 322746 23127 89.5 MiB 3.55 0.04 20.8327 14.4872 -13369.2 -14.4872 14.4872 0.67 0.0121619 0.0113765 1.35407 1.22514 -1 -1 -1 -1 74 52438 48 3.93038e+07 1.43727e+07 3.51708e+06 4824.52 18.39 4.96637 4.54914 88217 717307 -1 45207 16 10797 38297 2240291 399545 15.587 15.587 -13991.8 -15.587 0 0 4.41327e+06 6053.86 0.17 0.96 0.47 -1 -1 0.17 0.489497 0.455404 0.02143 0.4567 0.02564 0.5177 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 21.43 vpr 79.10 MiB -1 -1 3.27 45264 8 1.18 -1 -1 38148 -1 60352 133 235 1 6 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 80996 235 305 2600 2761 1 1486 680 19 19 361 io auto 39.4 MiB 2.00 26051 12689 254745 87597 153775 13373 79.1 MiB 1.38 0.04 7.908 5.29959 -2839.7 -5.29959 5.29959 0.29 0.012127 0.011067 0.525997 0.479113 -1 -1 -1 -1 58 24404 36 1.72706e+07 1.00919e+07 1.32783e+06 3678.19 7.31 2.15982 1.97301 38879 268173 -1 20459 16 5974 16694 1375263 341705 5.25495 5.25495 -3023.54 -5.25495 0 0 1.69263e+06 4688.74 0.05 0.45 0.16 -1 -1 0.05 0.221912 0.208508 0.02626 0.4113 0.02791 0.5608 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 15.61 vpr 80.29 MiB -1 -1 2.33 46604 21 2.08 -1 -1 40588 -1 44928 147 38 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 82220 38 36 2570 2606 1 1047 221 17 17 289 clb auto 40.5 MiB 0.69 18019 8908 39574 9690 26848 3036 80.3 MiB 0.53 0.01 21.1511 14.3355 -2466.66 -14.3355 14.3355 0.22 0.00360612 0.00322534 0.263315 0.232003 -1 -1 -1 -1 48 15040 24 1.34605e+07 7.92242e+06 864508. 2991.38 3.70 1.49854 1.31021 28519 171069 -1 12978 12 3830 11571 346206 65034 15.2896 15.2896 -2704.54 -15.2896 0 0 1.10659e+06 3829.03 0.05 0.37 0.16 -1 -1 0.05 0.271424 0.248723 0.006497 0.3637 0.03004 0.6063 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5092.02 vpr 1.53 GiB -1 -1 463.82 1402996 65 3505.00 -1 -1 351932 -1 316376 6857 36 159 27 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1606748 36 356 125571 124356 1 35021 7435 98 98 9604 clb auto 758.6 MiB 44.19 2 441443 10017265 4132627 5827470 57168 1569.1 MiB 178.80 1.37 172.807 64.2278 -293929 -64.2278 64.2278 33.55 0.203257 0.163777 30.6282 24.8932 -1 -1 -1 -1 78 591086 48 5.9175e+08 4.6734e+08 5.17038e+07 5383.57 240.84 97.3599 80.2169 1226648 10944044 -1 553448 19 118693 385257 20226886 3989619 65.0797 65.0797 -378350 -65.0797 -0.256508 -0.0326169 6.54025e+07 6809.92 3.27 14.83 7.78 -1 -1 3.27 9.82532 8.5296 0.2679 0.3573 0.01398 0.6288 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt index afc7702ee1c..15ab4719c9e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.59 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65868 14 8 926 934 0 490 100 11 11 121 clb auto 24.6 MiB 0.91 4639 5668 847 4419 402 64.3 MiB 0.16 0.01 4.54815 -31.8355 -4.54815 nan 0.11 0.00249412 0.00221472 0.083083 0.0754962 -1 -1 -1 -1 48 7214 49 4.36541e+06 4.20373e+06 357017. 2950.55 2.04 0.729015 0.623693 12171 71069 -1 6577 19 3324 15359 408061 81134 4.87162 nan -34.7178 -4.87162 0 0 455885. 3767.64 0.01 0.26 0.06 -1 -1 0.01 0.140142 0.125126 - k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 6.95 vpr 65.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 103 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67448 38 3 1113 1116 0 662 144 13 13 169 clb auto 26.3 MiB 1.53 7442 11831 1926 8689 1216 65.9 MiB 0.29 0.01 5.59822 -16.3249 -5.59822 nan 0.16 0.00306728 0.00270237 0.126883 0.113876 -1 -1 -1 -1 64 12841 39 6.52117e+06 5.55108e+06 687872. 4070.25 3.20 0.976549 0.840439 19211 138678 -1 11425 17 4712 23613 728373 121323 5.82519 nan -16.8677 -5.82519 0 0 856291. 5066.81 0.03 0.36 0.11 -1 -1 0.03 0.160453 0.144609 - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.91 vpr 64.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65892 9 19 897 916 0 556 110 12 12 144 clb auto 24.8 MiB 1.46 6252 7474 1266 5720 488 64.3 MiB 0.20 0.01 4.74237 -77.8307 -4.74237 nan 0.14 0.00271417 0.00242922 0.0925149 0.0843887 -1 -1 -1 -1 62 10739 47 5.3894e+06 4.41931e+06 554770. 3852.57 2.59 0.760237 0.654515 15940 110000 -1 9728 17 4391 21118 675575 120995 5.20821 nan -84.4166 -5.20821 0 0 687181. 4772.09 0.02 0.31 0.09 -1 -1 0.02 0.1315 0.118528 - k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 6.12 vpr 65.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67388 229 197 1364 1561 1 539 497 16 16 256 io auto 26.1 MiB 0.83 4504 148022 42306 97632 8084 65.8 MiB 0.82 0.01 2.97254 -656.061 -2.97254 2.97254 0.27 0.00439332 0.00408702 0.35847 0.333653 -1 -1 -1 -1 36 7822 26 1.05632e+07 3.82647e+06 638738. 2495.07 2.60 1.40665 1.28851 24820 128426 -1 7098 11 1611 3987 187232 44731 3.15649 3.15649 -738.429 -3.15649 0 0 786978. 3074.13 0.03 0.19 0.08 -1 -1 0.03 0.132772 0.123936 - k6_frac_N10_40nm.xml clma.pre-vpr.blif common 28.51 vpr 89.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 316 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91500 62 82 3672 3754 1 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2.93 1.43298 1.34768 31748 166456 -1 8164 13 2250 4803 238712 56339 4.07339 nan -791.038 -4.07339 0 0 1.01518e+06 3133.28 0.04 0.21 0.14 -1 -1 0.04 0.139599 0.132291 - k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 3.71 vpr 64.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66072 64 39 1371 1410 1 541 167 10 10 100 clb auto 25.0 MiB 0.50 3623 18986 4100 13819 1067 64.5 MiB 0.29 0.01 5.32461 -1004.72 -5.32461 5.32461 0.09 0.00297013 0.00265425 0.142744 0.129291 -1 -1 -1 -1 50 5495 30 3.44922e+06 3.44922e+06 295697. 2956.97 1.53 0.822979 0.71402 10016 58256 -1 4877 17 1881 5375 141590 30815 5.49357 5.49357 -1059.83 -5.49357 0 0 379824. 3798.24 0.01 0.18 0.05 -1 -1 0.01 0.130986 0.117787 - k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 6.57 vpr 65.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66956 229 197 1362 1559 1 570 496 16 16 256 io auto 25.8 MiB 0.92 5066 137836 36889 92766 8181 65.4 MiB 0.78 0.01 2.91431 -671.379 -2.91431 2.91431 0.27 0.00438808 0.00409538 0.327876 0.305574 -1 -1 -1 -1 36 8862 27 1.05632e+07 3.77258e+06 638738. 2495.07 2.96 1.41434 1.29776 24820 128426 -1 7675 13 1986 5211 265646 63312 3.18697 3.18697 -739.19 -3.18697 0 0 786978. 3074.13 0.03 0.23 0.10 -1 -1 0.03 0.155656 0.14507 - k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 12.40 vpr 77.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 171 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79424 131 114 3421 3535 1 1164 416 16 16 256 clb auto 36.2 MiB 3.40 10474 95088 26501 63930 4657 77.6 MiB 1.19 0.02 7.51043 -4391.12 -7.51043 7.51043 0.26 0.00746347 0.00670247 0.527413 0.462699 -1 -1 -1 -1 56 18313 31 1.05632e+07 9.21587e+06 942187. 3680.42 4.59 2.05209 1.78067 28136 192436 -1 15484 16 5183 22017 710369 128360 7.51944 7.51944 -4543.65 -7.51944 0 0 1.20185e+06 4694.72 0.04 0.55 0.15 -1 -1 0.04 0.349204 0.315387 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 24.75 vpr 82.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83992 10 10 2659 2669 0 1401 305 19 19 361 clb auto 39.3 MiB 4.57 26220 51605 13492 36245 1868 82.0 MiB 1.25 0.02 6.59302 -61.9652 -6.59302 nan 0.39 0.00827542 0.00731978 0.484089 0.41329 -1 -1 -1 -1 90 42829 31 1.55754e+07 1.53598e+07 2.09179e+06 5794.43 14.00 3.32602 2.79995 48131 439069 -1 39158 17 9518 58062 2365838 328796 6.83753 nan -64.8858 -6.83753 0 0 2.60973e+06 7229.16 0.08 1.03 0.29 -1 -1 0.08 0.41705 0.373851 - k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 3.76 vpr 63.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 8 63 761 824 0 435 134 10 10 100 clb auto 23.7 MiB 0.68 3999 11420 2063 8488 869 63.1 MiB 0.20 0.01 3.77984 -169.82 -3.77984 nan 0.09 0.00233479 0.00210219 0.0905659 0.0824737 -1 -1 -1 -1 58 6565 28 3.44922e+06 3.39532e+06 342720. 3427.20 1.56 0.557203 0.48462 10608 68480 -1 5918 16 2541 10577 323005 63220 4.22288 nan -188.35 -4.22288 0 0 435638. 4356.38 0.01 0.19 0.05 -1 -1 0.01 0.102623 0.0927145 - k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 13.58 vpr 77.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 167 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79220 20 116 3175 3291 1 1338 303 15 15 225 clb auto 36.1 MiB 3.06 14602 62340 15718 42273 4349 77.4 MiB 1.17 0.02 8.56273 -4519.63 -8.56273 8.56273 0.22 0.00757247 0.0068348 0.522644 0.463063 -1 -1 -1 -1 80 24018 43 9.10809e+06 9.0003e+06 1.12687e+06 5008.33 6.06 2.41987 2.10801 28171 234221 -1 21050 15 6703 26493 1041429 176822 9.09101 9.09101 -4756.62 -9.09101 0 0 1.41774e+06 6301.08 0.04 0.63 0.19 -1 -1 0.04 0.342199 0.310175 - k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 4.84 vpr 63.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 14 14 828 842 0 475 99 11 11 121 clb auto 24.1 MiB 0.91 4532 5343 748 4219 376 63.7 MiB 0.15 0.01 4.39029 -57.6027 -4.39029 nan 0.11 0.00227799 0.00202987 0.0718845 0.0655562 -1 -1 -1 -1 52 7728 41 4.36541e+06 3.82647e+06 379421. 3135.71 2.05 0.703343 0.603899 12531 77429 -1 6634 16 3040 13763 383785 71279 4.69105 nan -60.7462 -4.69105 0 0 499620. 4129.09 0.01 0.15 0.04 -1 -1 0.01 0.0814211 0.0751261 - k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 26.16 vpr 82.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 272 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84416 16 40 2839 2879 0 1511 328 19 19 361 clb auto 39.8 MiB 3.52 23598 55698 13292 40268 2138 82.4 MiB 1.28 0.02 6.48626 -238.484 -6.48626 nan 0.44 0.00886302 0.00735171 0.491212 0.417579 -1 -1 -1 -1 82 38584 40 1.55754e+07 1.46592e+07 1.91630e+06 5308.30 16.27 3.50905 2.95866 46331 403357 -1 35281 17 9680 52085 1891572 294823 6.8403 nan -243.508 -6.8403 0 0 2.40187e+06 6653.38 0.08 1.01 0.33 -1 -1 0.08 0.437668 0.392311 - k6_frac_N10_40nm.xml s298.pre-vpr.blif common 3.15 vpr 62.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 4 6 726 732 1 395 74 10 10 100 clb auto 23.4 MiB 0.73 3639 2709 340 2252 117 62.8 MiB 0.10 0.00 6.02711 -48.0055 -6.02711 6.02711 0.09 0.00207648 0.0018638 0.0538424 0.0494959 -1 -1 -1 -1 50 5470 24 3.44922e+06 3.44922e+06 295697. 2956.97 1.28 0.507359 0.443613 10016 58256 -1 4992 17 2195 9283 271197 50082 6.42868 6.42868 -51.2874 -6.42868 0 0 379824. 3798.24 0.01 0.12 0.03 -1 -1 0.01 0.0746748 0.0694149 - k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 13.59 vpr 87.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89136 29 106 4782 4888 1 1993 385 18 18 324 clb auto 44.4 MiB 2.46 13385 89985 21640 60579 7766 87.0 MiB 1.52 0.02 5.22969 -3570.14 -5.22969 5.22969 0.34 0.00938818 0.00831247 0.681949 0.588191 -1 -1 -1 -1 50 21612 42 1.37969e+07 1.34735e+07 1.08879e+06 3360.46 5.45 2.95573 2.52337 34656 222912 -1 19075 14 7130 20879 621675 127526 5.31212 5.31212 -3691.5 -5.31212 0 0 1.40279e+06 4329.61 0.05 0.59 0.17 -1 -1 0.05 0.416139 0.374046 - k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 13.45 vpr 85.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 228 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87964 38 304 4422 4726 1 1994 570 18 18 324 clb auto 43.2 MiB 2.50 13819 172996 49998 111442 11556 85.9 MiB 2.01 0.03 4.76683 -2916.88 -4.76683 4.76683 0.35 0.00939228 0.00841165 0.819185 0.712738 -1 -1 -1 -1 58 23055 36 1.37969e+07 1.22878e+07 1.26150e+06 3893.53 4.75 2.90623 2.51915 36592 261672 -1 20398 14 6469 17425 591858 126037 4.97859 4.97859 -3048.53 -4.97859 0 0 1.60510e+06 4954.00 0.05 0.63 0.21 -1 -1 0.05 0.450883 0.410575 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.73 vpr 65.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66644 41 35 1006 1041 0 604 160 12 12 144 clb auto 25.4 MiB 1.22 6515 13180 2173 9685 1322 65.1 MiB 0.26 0.01 4.58553 -134.055 -4.58553 nan 0.14 0.00299227 0.00267516 0.112623 0.102342 -1 -1 -1 -1 64 10841 30 5.3894e+06 4.5271e+06 575115. 3993.85 2.53 0.863068 0.745904 16224 115365 -1 9534 17 3641 17204 511035 92223 4.88481 nan -140.076 -4.88481 0 0 716128. 4973.11 0.02 0.28 0.09 -1 -1 0.02 0.142307 0.128311 - k6_frac_N10_40nm.xml spla.pre-vpr.blif common 15.03 vpr 76.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78680 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.0 MiB 2.88 16089 42000 9359 30203 2438 76.8 MiB 0.95 0.02 5.95204 -207.143 -5.95204 nan 0.30 0.00775355 0.00661099 0.401796 0.349405 -1 -1 -1 -1 68 27700 45 1.21262e+07 1.16411e+07 1.30851e+06 4527.71 7.55 2.17634 1.8524 34227 265321 -1 23554 19 8023 43603 1540936 228530 6.17174 nan -217.21 -6.17174 0 0 1.61843e+06 5600.10 0.05 0.82 0.21 -1 -1 0.05 0.356964 0.321301 - k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 3.30 vpr 65.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66732 52 122 1461 1583 1 472 237 10 10 100 clb auto 25.8 MiB 0.55 2690 30290 6635 22073 1582 65.2 MiB 0.30 0.01 4.95966 -1122.48 -4.95966 4.95966 0.09 0.00309899 0.0028239 0.143089 0.130468 -1 -1 -1 -1 46 4786 25 3.44922e+06 3.39532e+06 276332. 2763.32 1.07 0.637438 0.562157 9816 55112 -1 4250 13 1489 3922 122560 29939 5.00101 5.00101 -1209.26 -5.00101 0 0 354105. 3541.05 0.01 0.16 0.04 -1 -1 0.01 0.119116 0.108599 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.22 vpr 65.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66736 14 8 926 934 0 489 102 11 11 121 clb auto 25.9 MiB 0.87 5716 4667 5814 773 4648 393 65.2 MiB 0.12 0.00 5.1758 4.39004 -31.3924 -4.39004 nan 0.08 0.00178088 0.00159339 0.0633619 0.0585507 -1 -1 -1 -1 52 7329 33 4.36541e+06 4.31152e+06 379421. 3135.71 2.20 0.764911 0.665568 12531 77429 -1 6513 17 2865 12552 316734 63876 5.07045 nan -34.2643 -5.07045 0 0 499620. 4129.09 0.01 0.16 0.04 -1 -1 0.01 0.100679 0.092897 +k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 6.36 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68812 38 3 1113 1116 0 665 142 13 13 169 clb auto 28.1 MiB 1.08 10548 7468 13832 2493 9914 1425 67.2 MiB 0.23 0.01 7.37702 5.32001 -15.73 -5.32001 nan 0.12 0.00232644 0.00203595 0.107932 0.0969942 -1 -1 -1 -1 62 13388 40 6.52117e+06 5.44329e+06 663442. 3925.69 3.52 1.00129 0.877983 18875 132257 -1 11741 18 5422 26877 882518 148818 5.56885 nan -16.3181 -5.56885 0 0 821735. 4862.34 0.02 0.36 0.07 -1 -1 0.02 0.164374 0.151826 +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 6.24 vpr 65.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66700 9 19 897 916 0 559 109 11 11 121 clb auto 26.4 MiB 1.02 7140 6126 6609 990 5282 337 65.1 MiB 0.20 0.00 5.35916 4.63303 -75.5716 -4.63303 nan 0.10 0.00138137 0.00119951 0.0992015 0.0904761 -1 -1 -1 -1 70 9981 48 4.36541e+06 4.36541e+06 511363. 4226.14 3.71 1.03481 0.903319 13971 102581 -1 9236 20 4663 24137 775856 134967 5.15777 nan -81.91 -5.15777 0 0 640906. 5296.74 0.02 0.37 0.06 -1 -1 0.02 0.155463 0.140494 +k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 4.08 vpr 67.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68648 229 197 1364 1561 1 545 498 16 16 256 io auto 27.7 MiB 0.54 8834 4538 160311 47174 104392 8745 67.0 MiB 0.49 0.01 4.09828 3.00075 -655.912 -3.00075 3.00075 0.20 0.00228394 0.00210599 0.199935 0.183794 -1 -1 -1 -1 36 7805 27 1.05632e+07 3.88037e+06 638738. 2495.07 1.70 0.763949 0.703546 24820 128426 -1 7103 12 1701 4682 221888 53122 3.35736 3.35736 -731.549 -3.35736 0 0 786978. 3074.13 0.03 0.13 0.07 -1 -1 0.03 0.0913876 0.0861942 +k6_frac_N10_40nm.xml clma.pre-vpr.blif common 19.63 vpr 90.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 319 62 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 92520 62 82 3672 3754 1 2348 463 20 20 400 clb auto 49.5 MiB 2.88 53167 28547 136503 37288 90480 8735 90.4 MiB 2.11 0.03 11.2331 7.97399 -326.521 -7.97399 7.97399 0.34 0.00875297 0.00797138 0.847567 0.688107 -1 -1 -1 -1 88 44571 35 1.74617e+07 1.71922e+07 2.29517e+06 5737.92 10.39 3.83688 3.1762 53088 483428 -1 41011 17 14832 64712 2253455 355288 8.38548 8.38548 -344.884 -8.38548 0 0 2.86840e+06 7171.00 0.10 1.04 0.30 -1 -1 0.10 0.521148 0.466219 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.69 vpr 64.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 256 245 954 1199 0 584 555 18 18 324 io auto 25.1 MiB 0.19 10217 5340 128235 34840 87101 6294 65.0 MiB 0.34 0.01 4.93688 3.71329 -708.053 -3.71329 nan 0.26 0.00199948 0.00187995 0.119693 0.112603 -1 -1 -1 -1 36 8812 39 1.37969e+07 2.91028e+06 824466. 2544.65 1.82 0.672729 0.63177 31748 166456 -1 7817 13 2215 4847 223176 52694 4.15133 nan -780.347 -4.15133 0 0 1.01518e+06 3133.28 0.03 0.12 0.09 -1 -1 0.03 0.0775895 0.0741275 +k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 2.72 vpr 66.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 65 64 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67680 64 39 1371 1410 1 539 168 11 11 121 clb auto 26.8 MiB 0.33 5584 3554 15910 3123 11816 971 66.1 MiB 0.15 0.00 6.03227 5.37507 -1038.07 -5.37507 5.37507 0.08 0.00156771 0.00139193 0.0747596 0.0677057 -1 -1 -1 -1 44 6185 38 4.36541e+06 3.50311e+06 327165. 2703.84 1.27 0.53243 0.470835 11931 67129 -1 5007 15 2028 5618 150141 32799 5.22952 5.22952 -1076.2 -5.22952 0 0 426099. 3521.48 0.01 0.11 0.04 -1 -1 0.01 0.0857885 0.0796425 +k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 4.92 vpr 68.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69680 229 197 1362 1559 1 570 498 16 16 256 io auto 28.1 MiB 0.74 9108 4889 148473 42778 97578 8117 68.0 MiB 0.47 0.01 4.8348 3.14736 -669.02 -3.14736 3.14736 0.30 0.00226729 0.00207241 0.17999 0.165413 -1 -1 -1 -1 36 8500 42 1.05632e+07 3.88037e+06 638738. 2495.07 2.30 0.957058 0.879549 24820 128426 -1 7656 13 1979 5245 274588 68226 3.45161 3.45161 -741.384 -3.45161 0 0 786978. 3074.13 0.03 0.14 0.07 -1 -1 0.03 0.0922548 0.0865961 +k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 10.27 vpr 80.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 166 131 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 81932 131 114 3421 3535 1 1168 411 15 15 225 clb auto 39.7 MiB 2.11 17765 10281 92031 24314 63237 4480 80.0 MiB 0.79 0.01 8.75467 7.10514 -4204.38 -7.10514 7.10514 0.17 0.00510006 0.00460859 0.376436 0.322116 -1 -1 -1 -1 58 16799 43 9.10809e+06 8.9464e+06 849382. 3775.03 5.12 2.28086 1.94401 25035 174617 -1 14821 15 4952 19579 622719 112047 7.25821 7.25821 -4441.31 -7.25821 0 0 1.08042e+06 4801.85 0.03 0.47 0.10 -1 -1 0.03 0.312728 0.287837 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 19.60 vpr 83.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85448 10 10 2659 2669 0 1441 305 19 19 361 clb auto 42.5 MiB 2.94 32579 26449 48527 11753 35255 1519 83.4 MiB 0.90 0.02 8.51351 6.36561 -61.7098 -6.36561 nan 0.29 0.00762048 0.00590277 0.393677 0.31916 -1 -1 -1 -1 90 44070 44 1.55754e+07 1.53598e+07 2.09179e+06 5794.43 12.11 2.73293 2.25343 48131 439069 -1 39495 18 9987 58249 2505846 334449 6.84682 nan -65.1715 -6.84682 0 0 2.60973e+06 7229.16 0.08 0.99 0.28 -1 -1 0.08 0.39675 0.358216 +k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 3.52 vpr 64.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 61 8 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 8 63 761 824 0 464 132 10 10 100 clb auto 25.1 MiB 0.64 5202 4219 8172 1346 6226 600 64.3 MiB 0.09 0.00 4.68322 3.95136 -171.257 -3.95136 nan 0.06 0.00117832 0.00103729 0.0411713 0.0375951 -1 -1 -1 -1 62 6890 29 3.44922e+06 3.28753e+06 366588. 3665.88 1.84 0.563741 0.499247 10808 71624 -1 6383 18 3263 13910 450723 84886 4.2104 nan -190.423 -4.2104 0 0 454102. 4541.02 0.01 0.16 0.04 -1 -1 0.01 0.0848892 0.0789772 +k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 10.71 vpr 79.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 167 20 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 81228 20 116 3175 3291 1 1354 303 15 15 225 clb auto 39.0 MiB 2.04 21678 14434 62340 15479 42636 4225 79.3 MiB 0.81 0.01 11.5497 8.67217 -4535.6 -8.67217 8.67217 0.17 0.00598961 0.00491716 0.389418 0.339327 -1 -1 -1 -1 78 23275 41 9.10809e+06 9.0003e+06 1.10266e+06 4900.72 5.62 2.16304 1.89205 27947 230153 -1 20596 15 6319 24844 985205 167745 9.14545 9.14545 -4810.82 -9.14545 0 0 1.39226e+06 6187.84 0.04 0.44 0.14 -1 -1 0.04 0.265519 0.24418 +k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 3.65 vpr 64.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 14 14 828 842 0 484 98 11 11 121 clb auto 25.3 MiB 0.70 5838 4589 4598 577 3714 307 64.4 MiB 0.11 0.00 5.13552 4.41862 -57.2342 -4.41862 nan 0.08 0.00216019 0.00187605 0.0527162 0.0474817 -1 -1 -1 -1 54 7371 29 4.36541e+06 3.77258e+06 393282. 3250.26 1.86 0.551705 0.483513 12651 80029 -1 6708 16 2958 13782 384033 69922 4.93716 nan -62.34 -4.93716 0 0 511363. 4226.14 0.01 0.15 0.04 -1 -1 0.01 0.0854717 0.079196 +k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 23.21 vpr 83.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 276 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85224 16 40 2839 2879 0 1524 332 19 19 361 clb auto 43.1 MiB 2.38 33170 23812 55484 13930 38908 2646 83.2 MiB 0.98 0.02 8.45123 6.4916 -240.609 -6.4916 nan 0.30 0.00735271 0.00577674 0.43013 0.346976 -1 -1 -1 -1 82 38872 48 1.55754e+07 1.48747e+07 1.91630e+06 5308.30 15.94 3.73157 3.06855 46331 403357 -1 35345 20 9890 54530 2023172 305290 6.9919 nan -256.124 -6.9919 0 0 2.40187e+06 6653.38 0.07 0.96 0.35 -1 -1 0.07 0.455144 0.414767 +k6_frac_N10_40nm.xml s298.pre-vpr.blif common 2.45 vpr 63.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 4 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65500 4 6 726 732 1 394 72 10 10 100 clb auto 24.7 MiB 0.61 4227 3644 2903 384 2413 106 64.0 MiB 0.07 0.00 6.29092 5.97061 -49.6933 -5.97061 5.97061 0.06 0.0011726 0.00103084 0.0377402 0.0347094 -1 -1 -1 -1 50 5462 25 3.44922e+06 3.34143e+06 295697. 2956.97 0.92 0.356034 0.31648 10016 58256 -1 5052 19 2244 8824 249008 48074 6.12473 6.12473 -52.0854 -6.12473 0 0 379824. 3798.24 0.01 0.12 0.03 -1 -1 0.01 0.080217 0.0746323 +k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 10.95 vpr 87.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 246 29 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 89912 29 106 4782 4888 1 1971 381 18 18 324 clb auto 48.7 MiB 2.66 31912 12914 91461 22158 61224 8079 87.8 MiB 1.14 0.01 9.34045 5.08538 -3515.89 -5.08538 5.08538 0.26 0.00638819 0.00575669 0.565699 0.465182 -1 -1 -1 -1 50 20649 31 1.37969e+07 1.32579e+07 1.08879e+06 3360.46 4.26 2.39167 2.01576 34656 222912 -1 18390 14 6502 17795 514521 108732 5.44467 5.44467 -3642.89 -5.44467 0 0 1.40279e+06 4329.61 0.04 0.42 0.12 -1 -1 0.04 0.333311 0.305973 +k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 12.77 vpr 87.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 229 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 89956 38 304 4422 4726 1 2011 571 18 18 324 clb auto 46.9 MiB 2.05 33483 13735 180539 53183 115745 11611 87.8 MiB 1.66 0.02 7.36291 4.83236 -2990.06 -4.83236 4.83236 0.26 0.00680899 0.00622388 0.730543 0.637641 -1 -1 -1 -1 60 23373 35 1.37969e+07 1.23417e+07 1.30451e+06 4026.26 6.11 3.12581 2.73129 36916 268072 -1 20457 17 6818 18608 617442 129769 5.15119 5.15119 -3122.73 -5.15119 0 0 1.63833e+06 5056.57 0.05 0.48 0.15 -1 -1 0.05 0.367799 0.338547 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.48 vpr 65.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67480 41 35 1006 1041 0 592 161 12 12 144 clb auto 27.0 MiB 0.83 8414 6369 15019 2656 10738 1625 65.9 MiB 0.21 0.00 5.81314 4.61808 -132.961 -4.61808 nan 0.10 0.00201435 0.00179366 0.0926978 0.0839262 -1 -1 -1 -1 64 10589 23 5.3894e+06 4.58099e+06 575115. 3993.85 2.87 0.892311 0.78471 16224 115365 -1 9640 17 3842 18426 545262 97961 4.99365 nan -142.217 -4.99365 0 0 716128. 4973.11 0.03 0.35 0.10 -1 -1 0.03 0.188284 0.172824 +k6_frac_N10_40nm.xml spla.pre-vpr.blif common 13.16 vpr 77.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 215 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79808 16 46 2232 2278 0 1144 277 17 17 289 clb auto 38.2 MiB 1.83 22379 15624 39965 9015 28403 2547 77.9 MiB 0.68 0.01 8.06632 5.82643 -200.335 -5.82643 nan 0.23 0.00653831 0.00547397 0.306995 0.255726 -1 -1 -1 -1 70 24462 32 1.21262e+07 1.15872e+07 1.33894e+06 4633.02 8.07 2.37386 2.02136 34803 275938 -1 23042 19 7242 39793 1366468 212085 6.30161 nan -215.252 -6.30161 0 0 1.67721e+06 5803.51 0.05 0.63 0.16 -1 -1 0.05 0.303222 0.274342 +k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 2.59 vpr 66.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 52 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68136 52 122 1461 1583 1 474 236 10 10 100 clb auto 27.4 MiB 0.37 4398 2714 31583 7033 22612 1938 66.5 MiB 0.18 0.00 5.30829 4.88854 -1118.91 -4.88854 4.88854 0.06 0.00173145 0.00158417 0.0816441 0.0741193 -1 -1 -1 -1 48 4763 22 3.44922e+06 3.34143e+06 287248. 2872.48 1.12 0.524806 0.467815 9916 56712 -1 4187 14 1409 3627 116662 29178 5.05451 5.05451 -1201.54 -5.05451 0 0 366588. 3665.88 0.01 0.10 0.03 -1 -1 0.01 0.0817235 0.0765267 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt index cc7b62c6a7e..06a4bcb6915 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt @@ -1,20 +1,20 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml alu4.pre-vpr.blif common 5.15 vpr 63.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 106 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 14 8 926 934 0 505 128 13 13 169 clb auto 23.7 MiB 0.39 5320 9466 1544 7430 492 63.5 MiB 0.20 0.01 4.98964 -35.546 -4.98964 nan 0.16 0.00251625 0.00223401 0.0945898 0.085379 -1 -1 -1 -1 40 8155 39 2.178e+06 1.908e+06 430798. 2549.10 2.23 0.762692 0.650665 13014 85586 -1 7291 24 4695 18699 612030 108244 5.31783 nan -35.626 -5.31783 0 0 541003. 3201.20 0.02 0.33 0.07 -1 -1 0.02 0.150814 0.13295 - k6_N10_40nm.xml apex2.pre-vpr.blif common 6.81 vpr 64.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 126 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66296 39 3 1113 1117 0 649 168 14 14 196 clb auto 25.0 MiB 0.51 8161 14521 2331 10832 1358 64.7 MiB 0.30 0.01 5.83152 -17.3307 -5.83152 nan 0.19 0.00327303 0.00291207 0.125054 0.112287 -1 -1 -1 -1 56 14649 45 2.592e+06 2.268e+06 683928. 3489.43 3.11 0.783946 0.67859 17100 137604 -1 12055 22 6319 31081 1191742 177825 5.79636 nan -17.0558 -5.79636 0 0 875557. 4467.13 0.03 0.48 0.11 -1 -1 0.03 0.176297 0.156434 - k6_N10_40nm.xml apex4.pre-vpr.blif common 6.12 vpr 63.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 105 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 9 19 897 916 0 543 133 13 13 169 clb auto 23.6 MiB 0.47 6734 11998 2247 9058 693 63.2 MiB 0.26 0.01 5.30224 -88.3937 -5.30224 nan 0.16 0.00277568 0.00248416 0.111245 0.10094 -1 -1 -1 -1 56 11936 45 2.178e+06 1.89e+06 580647. 3435.78 2.98 0.824097 0.708448 14694 116443 -1 10212 27 5690 29063 1167825 181866 5.38635 nan -89.1109 -5.38635 0 0 743711. 4400.66 0.02 0.48 0.09 -1 -1 0.02 0.171957 0.151906 - k6_N10_40nm.xml bigkey.pre-vpr.blif common 6.47 vpr 64.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 93 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 263 197 1372 1603 1 490 553 17 17 289 io auto 24.6 MiB 0.28 4778 170728 50681 109298 10749 64.2 MiB 0.88 0.01 3.19105 -732.6 -3.19105 3.19105 0.29 0.00444133 0.00414189 0.352128 0.327314 -1 -1 -1 -1 34 7398 17 4.05e+06 1.674e+06 688919. 2383.80 2.76 1.3271 1.215 21366 134962 -1 6995 17 2392 10610 509085 104346 3.17804 3.17804 -782.762 -3.17804 0 0 845950. 2927.16 0.03 0.32 0.10 -1 -1 0.03 0.181779 0.167898 - k6_N10_40nm.xml clma.pre-vpr.blif common 30.50 vpr 89.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 436 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91460 383 82 3674 4077 1 2255 901 23 23 529 clb auto 43.8 MiB 1.76 30959 435901 143273 235791 56837 87.8 MiB 4.57 0.05 8.55335 -395.949 -8.55335 8.55335 0.57 0.011521 0.00974146 1.22739 1.05507 -1 -1 -1 -1 70 48766 40 7.938e+06 7.848e+06 2.49953e+06 4725.00 12.64 4.21839 3.57666 52134 511241 -1 43952 24 19574 92605 3927944 550062 8.47101 8.47101 -397.531 -8.47101 0 0 3.12202e+06 5901.73 0.11 1.74 0.41 -1 -1 0.11 0.663416 0.57888 - k6_N10_40nm.xml des.pre-vpr.blif common 5.88 vpr 62.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 102 256 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63636 256 245 954 1199 0 608 603 18 18 324 io auto 23.0 MiB 0.22 5227 148271 39552 101169 7550 62.1 MiB 0.69 0.01 4.37046 -770.45 -4.37046 nan 0.33 0.00429362 0.00409542 0.263968 0.251414 -1 -1 -1 -1 34 7404 17 4.608e+06 1.836e+06 779010. 2404.35 2.41 1.22781 1.15626 24000 152888 -1 6744 14 2452 5473 272585 59901 4.46945 nan -782.102 -4.46945 0 0 956463. 2952.05 0.03 0.22 0.12 -1 -1 0.03 0.141821 0.134018 - k6_N10_40nm.xml diffeq.pre-vpr.blif common 4.62 vpr 63.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 102 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65388 64 39 1371 1410 1 525 205 13 13 169 clb auto 24.1 MiB 0.32 3921 26177 5932 18684 1561 63.9 MiB 0.32 0.01 6.43054 -1169.36 -6.43054 6.43054 0.16 0.00298713 0.00270217 0.145753 0.131572 -1 -1 -1 -1 30 6223 39 2.178e+06 1.836e+06 350324. 2072.92 1.18 0.626373 0.545912 12006 67531 -1 5218 22 3090 9783 337940 60993 6.09481 6.09481 -1163.91 -6.09481 0 0 430798. 2549.10 0.01 0.26 0.05 -1 -1 0.01 0.150744 0.133108 - k6_N10_40nm.xml dsip.pre-vpr.blif common 7.16 vpr 64.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65576 229 197 1370 1567 1 538 523 16 16 256 io auto 24.5 MiB 0.29 5055 147943 44035 96679 7229 64.0 MiB 0.84 0.01 3.2095 -723.52 -3.2095 3.2095 0.25 0.00439778 0.00410483 0.327457 0.304273 -1 -1 -1 -1 34 8590 45 3.528e+06 1.746e+06 604079. 2359.69 3.67 1.47788 1.35056 18880 118149 -1 7508 16 2871 10488 535186 116741 3.28619 3.28619 -773.959 -3.28619 0 0 742044. 2898.61 0.03 0.31 0.09 -1 -1 0.03 0.167166 0.154045 - k6_N10_40nm.xml elliptic.pre-vpr.blif common 17.77 vpr 75.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 242 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77400 131 114 3421 3535 1 1197 487 18 18 324 clb auto 34.5 MiB 0.89 12132 123047 34177 83673 5197 75.6 MiB 1.37 0.02 7.4606 -4613.61 -7.4606 7.4606 0.33 0.00810581 0.00695927 0.560378 0.487409 -1 -1 -1 -1 52 19935 35 4.608e+06 4.356e+06 1.09957e+06 3393.73 5.31 2.48742 2.1439 27876 225772 -1 16865 24 7619 33177 1410533 212600 7.58148 7.58148 -4794.49 -7.58148 0 0 1.44575e+06 4462.18 0.05 0.82 0.17 -1 -1 0.05 0.442646 0.391497 - k6_N10_40nm.xml ex1010.pre-vpr.blif common 25.84 vpr 79.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 322 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81016 10 10 2659 2669 0 1386 342 20 20 400 clb auto 36.7 MiB 1.37 27552 61287 15872 43555 1860 79.1 MiB 1.33 0.02 7.05556 -66.589 -7.05556 nan 0.42 0.00818042 0.00678636 0.481651 0.408035 -1 -1 -1 -1 86 46648 32 5.832e+06 5.796e+06 2.18757e+06 5468.92 16.22 3.3084 2.77524 43296 457864 -1 40817 23 12321 76660 3960652 471991 6.89706 nan -66.7022 -6.89706 0 0 2.74971e+06 6874.27 0.09 1.55 0.38 -1 -1 0.09 0.488654 0.431177 - k6_N10_40nm.xml ex5p.pre-vpr.blif common 4.10 vpr 61.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 98 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 8 63 761 824 0 446 169 12 12 144 clb auto 22.7 MiB 0.28 4942 12778 2101 9758 919 62.0 MiB 0.13 0.01 4.47718 -204.583 -4.47718 nan 0.10 0.00216344 0.00193361 0.0452269 0.0410824 -1 -1 -1 -1 44 8061 45 1.8e+06 1.764e+06 394711. 2741.05 2.19 0.64483 0.556552 11464 79652 -1 6964 19 3697 15748 572693 99319 4.62135 nan -207.386 -4.62135 0 0 511253. 3550.37 0.01 0.17 0.04 -1 -1 0.01 0.0737609 0.0675818 - k6_N10_40nm.xml frisc.pre-vpr.blif common 18.44 vpr 75.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 251 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77320 20 116 3175 3291 1 1188 387 18 18 324 clb auto 34.6 MiB 0.98 15146 84927 21530 58089 5308 75.5 MiB 1.28 0.02 10.0229 -5171.77 -10.0229 10.0229 0.33 0.00873977 0.00797476 0.530643 0.47162 -1 -1 -1 -1 58 25204 50 4.608e+06 4.518e+06 1.23881e+06 3823.48 6.40 2.34822 2.02881 29168 251432 -1 21617 25 8510 38924 1908034 279685 10.0072 10.0072 -5231.56 -10.0072 0 0 1.57021e+06 4846.34 0.05 0.98 0.20 -1 -1 0.05 0.493797 0.440091 - k6_N10_40nm.xml misex3.pre-vpr.blif common 4.74 vpr 63.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 100 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 14 14 828 842 0 489 128 12 12 144 clb auto 23.4 MiB 0.39 5175 7856 1075 6307 474 63.2 MiB 0.17 0.01 4.84801 -64.1454 -4.84801 nan 0.13 0.00237316 0.00211186 0.0763038 0.069521 -1 -1 -1 -1 46 7690 36 1.8e+06 1.8e+06 409728. 2845.33 1.90 0.68048 0.582561 11608 81817 -1 6920 20 4140 18396 605767 102501 4.82071 nan -63.1482 -4.82071 0 0 527971. 3666.47 0.02 0.29 0.06 -1 -1 0.02 0.12603 0.112062 - k6_N10_40nm.xml pdc.pre-vpr.blif common 21.86 vpr 80.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 332 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82088 16 40 2839 2879 0 1508 388 21 21 441 clb auto 37.7 MiB 1.17 25399 76744 19217 54467 3060 80.2 MiB 1.51 0.03 6.92036 -251.161 -6.92036 nan 0.47 0.00885769 0.00740089 0.531173 0.448728 -1 -1 -1 -1 72 40612 31 6.498e+06 5.976e+06 2.09950e+06 4760.78 11.04 2.90977 2.44288 43822 429389 -1 36688 22 12583 72460 3185853 429873 7.06044 nan -257.312 -7.06044 0 0 2.62494e+06 5952.24 0.09 1.30 0.27 -1 -1 0.09 0.47556 0.41731 - k6_N10_40nm.xml s298.pre-vpr.blif common 3.96 vpr 61.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62952 4 6 726 732 1 389 94 12 12 144 clb auto 22.2 MiB 0.25 4089 5206 723 4335 148 61.5 MiB 0.09 0.00 7.44269 -59.1085 -7.44269 7.44269 0.10 0.00104361 0.000914441 0.0377587 0.0345446 -1 -1 -1 -1 40 6786 29 1.8e+06 1.512e+06 360446. 2503.10 1.34 0.413858 0.360142 11036 71301 -1 5886 21 3075 15208 517485 86492 7.26292 7.26292 -60.1433 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65376 41 35 1006 1041 0 592 188 13 13 169 clb auto 24.2 MiB 0.53 7217 15790 2751 11594 1445 63.8 MiB 0.29 0.01 4.98507 -144.608 -4.98507 nan 0.16 0.00308253 0.00273928 0.120489 0.109161 -1 -1 -1 -1 54 11911 44 2.178e+06 2.016e+06 560467. 3316.37 3.24 0.979146 0.844173 14526 113769 -1 10428 30 5280 24638 903866 142828 4.87201 nan -144.017 -4.87201 0 0 730287. 4321.22 0.02 0.46 0.10 -1 -1 0.02 0.199563 0.175824 - k6_N10_40nm.xml spla.pre-vpr.blif common 17.67 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 265 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76688 16 46 2232 2278 0 1137 327 19 19 361 clb auto 33.2 MiB 0.92 17307 56627 13789 39736 3102 74.9 MiB 1.05 0.02 6.63208 -224.84 -6.63208 nan 0.37 0.00697821 0.0058582 0.391341 0.336325 -1 -1 -1 -1 60 30174 42 5.202e+06 4.77e+06 1.43744e+06 3981.82 8.84 2.3335 1.98111 32910 290117 -1 25425 24 9835 57132 2445755 336723 6.52939 nan -226.972 -6.52939 0 0 1.79849e+06 4981.96 0.06 1.13 0.23 -1 -1 0.06 0.404897 0.357661 - k6_N10_40nm.xml tseng.pre-vpr.blif common 3.61 vpr 64.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65656 52 122 1461 1583 1 500 286 13 13 169 clb auto 24.5 MiB 0.22 3158 39808 8713 28658 2437 64.1 MiB 0.20 0.00 6.15771 -1276.75 -6.15771 6.15771 0.12 0.00151949 0.00138677 0.0725931 0.0655934 -1 -1 -1 -1 26 4848 34 2.178e+06 2.016e+06 310759. 1838.81 0.73 0.389324 0.342948 11502 59218 -1 4210 17 2436 6640 243507 54081 5.71256 5.71256 -1266.26 -5.71256 0 0 383419. 2268.75 0.01 0.20 0.05 -1 -1 0.01 0.123184 0.110004 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml alu4.pre-vpr.blif common 4.91 vpr 64.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 106 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 14 8 926 934 0 514 128 13 13 169 clb auto 25.5 MiB 0.26 7083 5448 9788 1646 7588 554 64.7 MiB 0.15 0.00 5.97999 5.05611 -36.7617 -5.05611 nan 0.12 0.00148321 0.00129161 0.0679953 0.0617759 -1 -1 -1 -1 44 7669 23 2.178e+06 1.908e+06 471456. 2789.68 2.75 0.831893 0.720002 13518 95550 -1 7054 22 4067 16637 523317 87764 5.0058 nan -36.2952 -5.0058 0 0 610661. 3613.38 0.02 0.22 0.05 -1 -1 0.02 0.107729 0.0979149 +k6_N10_40nm.xml apex2.pre-vpr.blif common 5.45 vpr 66.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 128 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67684 39 3 1113 1117 0 649 170 14 14 196 clb auto 26.6 MiB 0.33 11306 8269 11920 1732 9182 1006 66.1 MiB 0.22 0.01 7.69377 5.66253 -16.5951 -5.66253 nan 0.14 0.0022649 0.00196723 0.0992103 0.0892723 -1 -1 -1 -1 56 13927 44 2.592e+06 2.304e+06 683928. 3489.43 2.89 0.787426 0.691094 17100 137604 -1 12377 22 5754 26605 1002340 150693 5.6078 nan -16.6372 -5.6078 0 0 875557. 4467.13 0.02 0.32 0.07 -1 -1 0.02 0.136693 0.125427 +k6_N10_40nm.xml apex4.pre-vpr.blif common 4.23 vpr 64.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 105 9 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 9 19 897 916 0 542 133 13 13 169 clb auto 25.3 MiB 0.30 8391 6735 11320 1952 8674 694 64.4 MiB 0.18 0.01 6.17724 5.31226 -86.9474 -5.31226 nan 0.12 0.00238491 0.00209788 0.0788687 0.0719373 -1 -1 -1 -1 56 11713 33 2.178e+06 1.89e+06 580647. 3435.78 2.11 0.543082 0.475032 14694 116443 -1 9840 25 5479 27940 1052585 163171 5.34721 nan -87.0992 -5.34721 0 0 743711. 4400.66 0.02 0.32 0.06 -1 -1 0.02 0.122642 0.110483 +k6_N10_40nm.xml bigkey.pre-vpr.blif common 4.46 vpr 65.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 93 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67288 263 197 1372 1603 1 497 553 17 17 289 io auto 26.4 MiB 0.18 9146 4610 166190 47472 107803 10915 65.7 MiB 0.53 0.01 4.32883 3.19205 -751.534 -3.19205 3.19205 0.22 0.00219749 0.00194794 0.192948 0.175966 -1 -1 -1 -1 34 7284 17 4.05e+06 1.674e+06 688919. 2383.80 1.91 0.747795 0.681917 21366 134962 -1 6861 14 2305 8738 471382 100298 3.29238 3.29238 -791.887 -3.29238 0 0 845950. 2927.16 0.03 0.18 0.07 -1 -1 0.03 0.0886663 0.08254 +k6_N10_40nm.xml clma.pre-vpr.blif common 22.99 vpr 88.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 436 62 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 90652 383 82 3674 4077 1 2242 901 23 23 529 clb auto 47.8 MiB 1.18 60546 31685 440251 147763 235759 56729 88.1 MiB 3.47 0.04 12.5735 9.22505 -390.083 -9.22505 9.22505 0.45 0.00877321 0.00803484 1.08071 0.909904 -1 -1 -1 -1 70 48763 36 7.938e+06 7.848e+06 2.49953e+06 4725.00 10.11 3.40178 2.84763 52134 511241 -1 43533 21 17430 80185 3323118 476163 9.07936 9.07936 -387.93 -9.07936 0 0 3.12202e+06 5901.73 0.10 1.21 0.29 -1 -1 0.10 0.508039 0.448686 +k6_N10_40nm.xml des.pre-vpr.blif common 3.90 vpr 63.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 100 256 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 256 245 954 1199 0 602 601 18 18 324 io auto 24.3 MiB 0.15 10721 5420 140026 39341 93980 6705 63.9 MiB 0.42 0.01 5.97631 4.13264 -765.653 -4.13264 nan 0.25 0.0020053 0.00187678 0.147575 0.139546 -1 -1 -1 -1 34 7666 22 4.608e+06 1.8e+06 779010. 2404.35 1.54 0.633075 0.594925 24000 152888 -1 6972 15 2528 6105 319538 68984 4.28747 nan -801.598 -4.28747 0 0 956463. 2952.05 0.03 0.15 0.08 -1 -1 0.03 0.0834864 0.079197 +k6_N10_40nm.xml diffeq.pre-vpr.blif common 4.46 vpr 65.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 64 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67180 64 39 1371 1410 1 525 204 13 13 169 clb auto 25.8 MiB 0.31 6520 3916 21204 4010 16081 1113 65.6 MiB 0.27 0.01 7.55482 6.06737 -1159.7 -6.06737 6.06737 0.18 0.003443 0.00316736 0.139109 0.12543 -1 -1 -1 -1 30 6125 43 2.178e+06 1.818e+06 350324. 2072.92 1.46 0.788466 0.702487 12006 67531 -1 5178 22 3019 9742 337555 60954 5.95152 5.95152 -1177.43 -5.95152 0 0 430798. 2549.10 0.01 0.19 0.04 -1 -1 0.01 0.11622 0.105207 +k6_N10_40nm.xml dsip.pre-vpr.blif common 4.48 vpr 65.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67132 229 197 1370 1567 1 534 521 16 16 256 io auto 26.2 MiB 0.19 9562 4735 149266 43445 98316 7505 65.6 MiB 0.48 0.01 4.18888 3.1959 -736.239 -3.1959 3.1959 0.19 0.00226564 0.00209541 0.172523 0.158247 -1 -1 -1 -1 34 7794 33 3.528e+06 1.71e+06 604079. 2359.69 2.19 0.758038 0.690657 18880 118149 -1 7160 19 2717 9216 471971 103095 3.3317 3.3317 -798.533 -3.3317 0 0 742044. 2898.61 0.02 0.21 0.06 -1 -1 0.02 0.111339 0.10326 +k6_N10_40nm.xml elliptic.pre-vpr.blif common 13.58 vpr 77.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 241 131 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78864 131 114 3421 3535 1 1197 486 18 18 324 clb auto 37.1 MiB 0.54 22607 11749 126546 34749 85241 6556 77.0 MiB 0.92 0.01 10.1196 7.35398 -4585.48 -7.35398 7.35398 0.25 0.00500688 0.00453694 0.403499 0.341049 -1 -1 -1 -1 50 18922 32 4.608e+06 4.338e+06 1.06618e+06 3290.67 3.44 1.55452 1.32535 27232 214208 -1 16253 19 7367 30536 1267689 193203 7.26105 7.26105 -4670.93 -7.26105 0 0 1.36711e+06 4219.48 0.04 0.61 0.11 -1 -1 0.04 0.339667 0.306043 +k6_N10_40nm.xml ex1010.pre-vpr.blif common 23.28 vpr 81.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 316 10 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 82956 10 10 2659 2669 0 1391 336 20 20 400 clb auto 40.8 MiB 0.87 34173 27378 59853 15980 41901 1972 81.0 MiB 1.02 0.02 9.34252 6.78888 -65.5484 -6.78888 nan 0.31 0.00780115 0.00619201 0.432572 0.349828 -1 -1 -1 -1 88 47872 43 5.832e+06 5.688e+06 2.22978e+06 5574.46 16.41 3.76498 3.11287 43692 465500 -1 40197 24 12700 79693 4033407 473272 6.80998 nan -65.6831 -6.80998 0 0 2.79850e+06 6996.25 0.09 1.26 0.29 -1 -1 0.09 0.421009 0.3711 +k6_N10_40nm.xml ex5p.pre-vpr.blif common 4.03 vpr 63.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 8 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 8 63 761 824 0 447 166 12 12 144 clb auto 24.0 MiB 0.23 6388 4881 13846 2417 10426 1003 63.9 MiB 0.15 0.01 5.38222 4.4446 -201.57 -4.4446 nan 0.10 0.0021612 0.00201166 0.0602991 0.0553309 -1 -1 -1 -1 46 7969 39 1.8e+06 1.71e+06 409728. 2845.33 2.33 0.640527 0.567984 11608 81817 -1 6969 27 3861 16117 591553 100720 4.44193 nan -200.716 -4.44193 0 0 527971. 3666.47 0.01 0.20 0.04 -1 -1 0.01 0.0930208 0.0850464 +k6_N10_40nm.xml frisc.pre-vpr.blif common 15.36 vpr 77.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 249 20 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79300 20 116 3175 3291 1 1155 385 18 18 324 clb auto 37.5 MiB 0.57 23449 14674 85785 22555 57970 5260 77.4 MiB 0.86 0.01 13.9915 9.85955 -5064.76 -9.85955 9.85955 0.36 0.00518812 0.00473015 0.375569 0.324925 -1 -1 -1 -1 54 24717 46 4.608e+06 4.482e+06 1.13978e+06 3517.85 5.34 2.00436 1.71283 28200 234220 -1 20929 29 7959 35697 1712456 256751 9.75974 9.75974 -5111.13 -9.75974 0 0 1.48298e+06 4577.10 0.05 0.71 0.13 -1 -1 0.05 0.381404 0.339549 +k6_N10_40nm.xml misex3.pre-vpr.blif common 3.47 vpr 63.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 99 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65484 14 14 828 842 0 495 127 12 12 144 clb auto 25.1 MiB 0.26 6785 5201 6826 774 5709 343 63.9 MiB 0.10 0.00 6.08887 4.91247 -64.3251 -4.91247 nan 0.10 0.00150222 0.00134616 0.0447251 0.0409107 -1 -1 -1 -1 44 7811 41 1.8e+06 1.782e+06 394711. 2741.05 1.40 0.492209 0.435312 11464 79652 -1 6924 20 4019 17263 551288 95278 5.04493 nan -64.2968 -5.04493 0 0 511253. 3550.37 0.01 0.24 0.05 -1 -1 0.01 0.106579 0.0965979 +k6_N10_40nm.xml pdc.pre-vpr.blif common 17.45 vpr 81.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 330 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83676 16 40 2839 2879 0 1467 386 21 21 441 clb auto 41.2 MiB 0.78 36890 24945 71990 18391 50424 3175 81.7 MiB 1.09 0.02 10.1773 7.09431 -258.357 -7.09431 nan 0.35 0.00651541 0.00583051 0.445898 0.359931 -1 -1 -1 -1 72 42025 42 6.498e+06 5.94e+06 2.09950e+06 4760.78 9.01 2.40714 1.97615 43822 429389 -1 35463 21 12440 72372 3086341 420076 7.18526 nan -260.461 -7.18526 0 0 2.62494e+06 5952.24 0.09 1.13 0.25 -1 -1 0.09 0.428209 0.378195 +k6_N10_40nm.xml s298.pre-vpr.blif common 3.58 vpr 63.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 86 4 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64908 4 6 726 732 1 396 96 12 12 144 clb auto 23.6 MiB 0.20 5047 4214 4476 509 3811 156 63.4 MiB 0.09 0.00 8.22999 7.1626 -56.5861 -7.1626 7.1626 0.10 0.00127359 0.0011384 0.0456131 0.0421391 -1 -1 -1 -1 38 7004 50 1.8e+06 1.548e+06 347776. 2415.11 1.56 0.480843 0.430228 10892 69136 -1 6169 23 3648 19435 701468 113085 7.00833 7.00833 -56.0805 -7.00833 0 0 439064. 3049.06 0.01 0.21 0.03 -1 -1 0.01 0.09092 0.0829136 +k6_N10_40nm.xml s38584.1.pre-vpr.blif common 47.18 vpr 86.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 404 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88680 39 304 4677 4982 1 2045 747 23 23 529 clb auto 46.5 MiB 0.75 45108 15162 254847 76917 164647 13283 86.6 MiB 1.64 0.02 9.61199 5.3655 -3362.15 -5.3655 5.3655 0.44 0.00679555 0.00619652 0.605609 0.521814 -1 -1 -1 -1 36 23003 46 7.938e+06 7.272e+06 1.36659e+06 2583.35 4.11 2.33544 2.00342 39990 270289 -1 20202 25 11198 32005 1222912 235642 5.42021 5.42021 -3467.48 -5.42021 0 0 1.67430e+06 3165.03 0.06 0.75 0.19 -1 -1 0.06 0.46165 0.407176 +k6_N10_40nm.xml seq.pre-vpr.blif common 6.02 vpr 65.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 113 41 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66840 41 35 1006 1041 0 592 189 13 13 169 clb auto 25.8 MiB 0.29 9486 7332 19159 3405 13914 1840 65.3 MiB 0.33 0.01 6.24344 5.08166 -147.244 -5.08166 nan 0.18 0.00313515 0.00279961 0.136721 0.121582 -1 -1 -1 -1 56 11939 50 2.178e+06 2.034e+06 580647. 3435.78 3.52 0.997007 0.871403 14694 116443 -1 10324 20 5127 24770 910918 144801 5.20387 nan -145.39 -5.20387 0 0 743711. 4400.66 0.02 0.29 0.06 -1 -1 0.02 0.117813 0.107036 +k6_N10_40nm.xml spla.pre-vpr.blif common 15.49 vpr 75.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 255 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77688 16 46 2232 2278 0 1142 317 18 18 324 clb auto 36.3 MiB 0.61 24484 16948 51077 11678 36839 2560 75.9 MiB 0.74 0.01 8.85685 6.23263 -214.486 -6.23263 nan 0.25 0.0056626 0.00447365 0.316066 0.258337 -1 -1 -1 -1 62 27299 43 4.608e+06 4.59e+06 1.32550e+06 4091.04 9.17 2.50414 2.08209 29816 263480 -1 24298 20 9391 53871 2167776 305985 6.52956 nan -216.506 -6.52956 0 0 1.62910e+06 5028.10 0.05 0.76 0.15 -1 -1 0.05 0.297609 0.265752 +k6_N10_40nm.xml tseng.pre-vpr.blif common 3.14 vpr 65.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 113 52 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66992 52 122 1461 1583 1 500 287 13 13 169 clb auto 26.4 MiB 0.19 6165 3259 40019 8603 29010 2406 65.4 MiB 0.20 0.00 7.76697 6.20124 -1275.15 -6.20124 6.20124 0.12 0.00156781 0.0014181 0.0808621 0.0730003 -1 -1 -1 -1 26 5124 30 2.178e+06 2.034e+06 310759. 1838.81 0.81 0.447445 0.401543 11502 59218 -1 4548 25 2647 7841 292976 65953 5.87644 5.87644 -1276.67 -5.87644 0 0 383419. 2268.75 0.01 0.18 0.03 -1 -1 0.01 0.116471 0.105499 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt index 9c78b87cb9f..a74307e5813 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu - hard_fpu_arch_timing.xml bfly.v common 10.66 vpr 62.66 MiB -1 -1 0.29 18880 1 0.04 -1 -1 31060 -1 -1 14 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64160 193 64 833 649 1 555 275 30 30 900 block_FPU auto 22.9 MiB 9.06 7227 73501 28110 42559 2832 62.7 MiB 0.24 0.00 2.985 -1449.57 -2.985 2.985 0.00 0.00129076 0.0012041 0.111382 0.10419 -1 -1 -1 -1 10011 18.0704 2627 4.74188 921 1045 352645 96816 1.6779e+06 169623 2.03108e+06 2256.75 6 48532 406344 -1 2.985 2.985 -1492.92 -2.985 -24.3711 -0.0851 0.33 -1 -1 62.7 MiB 0.08 0.141917 0.133178 62.7 MiB -1 0.09 4 - hard_fpu_arch_timing.xml bgm.v common 4.38 vpr 66.29 MiB -1 -1 0.37 19684 1 0.06 -1 -1 31568 -1 -1 0 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67880 257 32 1281 693 1 1048 299 38 38 1444 block_FPU auto 27.1 MiB 1.15 17732 96203 37615 55516 3072 66.3 MiB 0.97 0.01 2.985 -3196.19 -2.985 2.985 0.00 0.0058053 0.00549326 0.572424 0.541944 -1 -1 -1 -1 24861 23.7450 6446 6.15664 1897 2343 998279 268232 2.90196e+06 343832 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3400.32 -2.985 -32.9279 -0.0851 0.72 -1 -1 66.3 MiB 0.27 0.668829 0.633922 66.3 MiB -1 0.18 10 - hard_fpu_arch_timing.xml dscg.v common 11.83 vpr 63.13 MiB -1 -1 0.27 18916 1 0.05 -1 -1 30476 -1 -1 0 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 129 64 769 585 1 513 197 30 30 900 block_FPU auto 23.0 MiB 9.85 7095 47183 20094 26781 308 63.1 MiB 0.42 0.00 2.985 -1443.24 -2.985 2.985 0.00 0.00302745 0.00284785 0.254581 0.239617 -1 -1 -1 -1 9979 19.4902 2627 5.13086 790 910 348267 96422 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1537.32 -2.985 -21.8648 -0.0851 0.44 -1 -1 63.1 MiB 0.11 0.304162 0.286319 63.1 MiB -1 0.10 4 - hard_fpu_arch_timing.xml fir.v common 19.03 vpr 63.21 MiB -1 -1 0.34 19016 1 0.05 -1 -1 32588 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64724 161 32 993 808 1 587 198 32 32 1024 block_FPU auto 23.3 MiB 16.72 9692 44550 18401 25778 371 63.2 MiB 0.41 0.00 2.985 -1407.96 -2.985 2.985 0.00 0.00297922 0.00277214 0.239029 0.222609 -1 -1 -1 -1 12905 22.0222 3330 5.68259 990 1086 448603 120061 2.063e+06 171916 2.37490e+06 2319.23 5 57140 479124 -1 2.985 2.985 -1491.67 -2.985 -38.4653 -0.0851 0.53 -1 -1 63.2 MiB 0.13 0.291694 0.271864 63.2 MiB -1 0.12 5 - hard_fpu_arch_timing.xml mm3.v common 6.50 vpr 61.19 MiB -1 -1 0.23 18328 1 0.04 -1 -1 30736 -1 -1 0 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62656 193 32 545 422 1 386 228 22 22 484 block_FPU auto 21.8 MiB 4.95 4984 53124 22938 29850 336 61.2 MiB 0.32 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00217515 0.00206622 0.171111 0.1626 -1 -1 -1 -1 6454 16.7636 1714 4.45195 565 565 194103 53991 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.472 -2.985 -13.5705 -0.0851 0.24 -1 -1 61.2 MiB 0.07 0.203477 0.193246 61.2 MiB -1 0.05 3 - hard_fpu_arch_timing.xml ode.v common 53.14 vpr 64.66 MiB -1 -1 0.41 19816 1 0.10 -1 -1 34200 -1 -1 141 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66208 130 72 1194 1103 1 571 345 19 19 361 io auto 24.6 MiB 50.95 5001 98274 32566 61072 4636 64.7 MiB 0.54 0.01 2.985 -1384.17 -2.985 2.985 0.00 0.00308436 0.00282904 0.260751 0.239819 -1 -1 -1 -1 6737 11.8193 1762 3.09123 1249 1362 304558 77526 653279 391968 795482. 2203.55 8 19802 160939 -1 2.985 2.985 -1385.47 -2.985 -52.8417 -0.0851 0.18 -1 -1 64.7 MiB 0.13 0.330036 0.303434 64.7 MiB -1 0.04 2 - hard_fpu_arch_timing.xml syn2.v common 3.85 vpr 62.39 MiB -1 -1 0.16 18524 1 0.04 -1 -1 30832 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63892 161 128 641 490 1 475 293 30 30 900 block_FPU auto 23.1 MiB 1.75 8105 81941 35762 45750 429 62.4 MiB 0.54 0.01 2.985 -1571.9 -2.985 2.985 0.00 0.00342016 0.0032503 0.298242 0.283689 -1 -1 -1 -1 10335 21.8038 2743 5.78692 780 976 327494 85675 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1595.62 -2.985 -16.3392 -0.0851 0.44 -1 -1 62.4 MiB 0.11 0.355509 0.338332 62.4 MiB -1 0.10 4 - hard_fpu_arch_timing.xml syn7.v common 7.45 vpr 112.47 MiB -1 -1 0.45 21564 1 0.08 -1 -1 32500 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 115168 161 128 1921 499 1 1760 309 54 54 2916 block_FPU auto 37.0 MiB 0.62 44624 112017 52264 59181 572 112.5 MiB 2.20 0.02 2.985 -8100.96 -2.985 2.985 0.00 0.0120269 0.0114133 1.31427 1.24716 -1 -1 -1 -1 60108 34.1717 15324 8.71177 4214 6760 3339753 839694 6.08571e+06 687663 6.89978e+06 2366.18 9 161598 1383069 -1 2.985 2.985 -8533.86 -2.985 -46.3798 -0.0851 1.55 -1 -1 112.5 MiB 0.90 1.61708 1.53715 112.5 MiB -1 0.39 20 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu +hard_fpu_arch_timing.xml bfly.v common 1.69 vpr 63.78 MiB -1 -1 0.13 18684 1 0.04 -1 -1 30412 -1 -1 0 193 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65312 193 64 833 649 1 513 261 30 30 900 block_FPU auto 24.2 MiB 0.32 11091 7034 74398 32654 41106 638 63.8 MiB 0.28 0.00 2.985 2.985 -1424.43 -2.985 2.985 0.00 0.00159102 0.00149083 0.154903 0.145699 -1 -1 -1 -1 9364 18.2891 2492 4.86719 779 887 316097 86405 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1464.04 -2.985 -27.2716 -0.0851 0.33 -1 -1 63.8 MiB 0.08 0.186823 0.176339 63.8 MiB -1 0.11 4 +hard_fpu_arch_timing.xml bgm.v common 2.89 vpr 66.42 MiB -1 -1 0.21 19836 1 0.05 -1 -1 31084 -1 -1 0 257 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68012 257 32 1281 693 1 999 299 38 38 1444 block_FPU auto 28.3 MiB 0.56 24417 20354 90209 37667 52028 514 66.4 MiB 0.59 0.01 2.985 2.985 -3279.31 -2.985 2.985 0.00 0.00306286 0.00289708 0.339134 0.321404 -1 -1 -1 -1 26869 26.9228 6935 6.94890 1862 2375 1114441 288875 2.90196e+06 343832 3.35777e+06 2325.33 7 79768 674274 -1 2.985 2.985 -3485.89 -2.985 -32.7577 -0.0851 0.55 -1 -1 66.4 MiB 0.24 0.412563 0.392015 66.4 MiB -1 0.17 10 +hard_fpu_arch_timing.xml dscg.v common 2.15 vpr 63.84 MiB -1 -1 0.16 18684 1 0.04 -1 -1 30748 -1 -1 0 129 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65368 129 64 769 585 1 513 198 32 32 1024 block_FPU auto 24.2 MiB 0.74 11272 7736 52614 22764 29600 250 63.8 MiB 0.24 0.00 2.985 2.985 -1450.41 -2.985 2.985 0.00 0.00146576 0.00137209 0.141162 0.132297 -1 -1 -1 -1 11188 21.8516 2890 5.64453 838 1049 418805 112428 2.063e+06 171916 2.37490e+06 2319.23 5 57140 479124 -1 2.985 2.985 -1553.53 -2.985 -21.7856 -0.0851 0.36 -1 -1 63.8 MiB 0.09 0.172509 0.162281 63.8 MiB -1 0.12 5 +hard_fpu_arch_timing.xml fir.v common 8.36 vpr 63.77 MiB -1 -1 0.21 18684 1 0.04 -1 -1 31156 -1 -1 0 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65300 161 32 993 808 1 562 198 32 32 1024 block_FPU auto 24.2 MiB 6.82 11288 7405 51462 21510 29704 248 63.8 MiB 0.24 0.00 2.985 2.985 -1332.96 -2.985 2.985 0.00 0.00145997 0.00135492 0.138155 0.128337 -1 -1 -1 -1 10782 19.2193 2771 4.93939 899 992 433591 120812 2.063e+06 171916 2.37490e+06 2319.23 5 57140 479124 -1 2.985 2.985 -1428.14 -2.985 -40.5929 -0.0851 0.44 -1 -1 63.8 MiB 0.09 0.17082 0.159463 63.8 MiB -1 0.11 5 +hard_fpu_arch_timing.xml mm3.v common 1.38 vpr 62.52 MiB -1 -1 0.12 18296 1 0.03 -1 -1 30628 -1 -1 0 193 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64024 193 32 545 422 1 385 229 30 30 900 block_FPU auto 22.7 MiB 0.18 8272 4968 58329 25699 32293 337 62.5 MiB 0.22 0.00 2.985 2.985 -855.954 -2.985 2.985 0.00 0.00103363 0.000972137 0.116063 0.109526 -1 -1 -1 -1 6670 17.3698 1756 4.57292 533 533 185005 50756 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -882.014 -2.985 -13.6953 -0.0851 0.31 -1 -1 62.5 MiB 0.05 0.136779 0.129322 62.5 MiB -1 0.09 4 +hard_fpu_arch_timing.xml ode.v common 2.88 vpr 64.91 MiB -1 -1 0.19 19452 1 0.07 -1 -1 33584 -1 -1 128 130 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66468 130 72 1194 1103 1 591 333 22 22 484 block_FPU auto 25.4 MiB 1.51 8920 6104 92573 27080 59763 5730 64.9 MiB 0.33 0.00 2.985 2.985 -1423.15 -2.985 2.985 0.00 0.00148876 0.00135475 0.152232 0.139158 -1 -1 -1 -1 8458 14.3356 2267 3.84237 1308 1755 428944 116306 882498 396552 1.07647e+06 2224.11 9 26490 217099 -1 2.985 2.985 -1454.47 -2.985 -48.7964 -0.0851 0.16 -1 -1 64.9 MiB 0.10 0.196644 0.180827 64.9 MiB -1 0.05 3 +hard_fpu_arch_timing.xml syn2.v common 2.86 vpr 62.56 MiB -1 -1 0.12 18680 1 0.03 -1 -1 30532 -1 -1 0 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64060 161 128 641 490 1 479 293 30 30 900 block_FPU auto 23.9 MiB 1.43 10930 8213 81941 35740 45812 389 62.6 MiB 0.29 0.00 2.985 2.985 -1573.71 -2.985 2.985 0.00 0.00170674 0.00161454 0.150112 0.142271 -1 -1 -1 -1 10469 21.9017 2773 5.80126 795 1003 347207 90839 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1600.15 -2.985 -16.078 -0.0851 0.41 -1 -1 62.6 MiB 0.10 0.187774 0.17827 62.6 MiB -1 0.10 4 +hard_fpu_arch_timing.xml syn7.v common 5.27 vpr 111.22 MiB -1 -1 0.24 21372 1 0.07 -1 -1 31944 -1 -1 0 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 113888 161 128 1921 499 1 1761 309 54 54 2916 block_FPU auto 38.1 MiB 0.38 74672 45797 118281 55728 61956 597 111.2 MiB 1.82 0.01 2.985 2.985 -8183.2 -2.985 2.985 0.00 0.00708224 0.00672565 1.09152 1.03992 -1 -1 -1 -1 61720 35.0682 15701 8.92102 4096 6553 3150232 794260 6.08571e+06 687663 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8633.26 -2.985 -40.8482 -0.0851 1.09 -1 -1 111.2 MiB 0.61 1.24899 1.19225 111.2 MiB -1 0.37 20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt index 985745ce71c..f279e94b037 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt @@ -1,8 +1,8 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - soft_fpu_arch_timing.xml bfly.v common 41.34 parmys 121.35 MiB -1 -1 28.71 124260 23 3.25 -1 -1 39816 -1 -1 1065 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84540 193 64 3908 3972 1 2590 1322 35 35 1225 clb auto 40.9 MiB 0.92 23821 566978 183866 374301 8811 82.6 MiB 3.62 0.05 15.2252 -3632.45 -15.2252 15.2252 0.00 0.00893832 0.00809078 0.765101 0.674928 -1 -1 -1 -1 41554 16.0502 10620 4.10197 16398 55146 3818752 563046 2.49624e+06 2.44122e+06 2.83731e+06 2316.17 20 66042 566079 -1 14.3186 14.3186 -3387.7 -14.3186 -31.8712 -0.0851 0.59 -1 -1 82.6 MiB 1.30 1.1781 1.04452 82.6 MiB -1 0.14 - soft_fpu_arch_timing.xml bgm.v common 91.63 parmys 261.79 MiB -1 -1 68.05 268076 18 8.02 -1 -1 47316 -1 -1 1490 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 98376 257 32 6040 6072 1 3862 1779 41 41 1681 clb auto 52.4 MiB 1.35 32284 896104 308252 576620 11232 96.1 MiB 5.96 0.07 12.7604 -5544.74 -12.7604 12.7604 0.00 0.0121239 0.0108644 1.11649 0.963883 -1 -1 -1 -1 53705 13.9132 13764 3.56580 24580 81256 5307364 800086 3.48649e+06 3.41543e+06 3.92715e+06 2336.20 24 90666 782499 -1 12.0246 12.0246 -5156.11 -12.0246 -31.3502 -0.0851 0.78 -1 -1 96.1 MiB 1.91 1.78217 1.54405 96.1 MiB -1 0.19 - soft_fpu_arch_timing.xml dscg.v common 37.96 parmys 121.48 MiB -1 -1 31.02 124396 24 1.46 -1 -1 38668 -1 -1 602 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72036 129 64 2192 2256 1 1525 795 27 27 729 clb auto 30.2 MiB 0.54 13360 240060 66463 162314 11283 70.3 MiB 1.50 0.02 16.4736 -1891.5 -16.4736 16.4736 0.00 0.00522672 0.00478088 0.373681 0.337968 -1 -1 -1 -1 23389 15.7821 5992 4.04318 10665 36046 2530253 367157 1.43263e+06 1.37991e+06 1.65895e+06 2275.65 21 39258 331839 -1 14.938 14.938 -1781.33 -14.938 -9.29425 -0.0851 0.32 -1 -1 70.3 MiB 0.86 0.642834 0.579879 70.3 MiB -1 0.07 - soft_fpu_arch_timing.xml fir.v common 30.01 parmys 107.04 MiB -1 -1 25.31 109604 16 0.75 -1 -1 35824 -1 -1 480 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69144 161 32 2044 2076 1 1154 673 24 24 576 clb auto 27.8 MiB 0.33 7067 186397 50839 130117 5441 67.5 MiB 1.00 0.02 10.7496 -1623.35 -10.7496 10.7496 0.00 0.00400883 0.00360476 0.266889 0.238205 -1 -1 -1 -1 11039 9.58247 2844 2.46875 5647 15675 1030099 156890 1.10943e+06 1.10026e+06 1.29802e+06 2253.51 23 30996 260004 -1 10.1243 10.1243 -1523.31 -10.1243 -41.6788 -0.0851 0.25 -1 -1 67.5 MiB 0.42 0.454829 0.403412 67.5 MiB -1 0.06 - soft_fpu_arch_timing.xml mm3.v common 19.71 parmys 76.30 MiB -1 -1 17.40 78128 11 0.25 -1 -1 34080 -1 -1 188 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62248 193 32 892 924 1 553 413 21 21 441 io auto 21.0 MiB 0.15 2944 81874 21125 56255 4494 60.8 MiB 0.37 0.01 7.4944 -557.676 -7.4944 7.4944 0.00 0.00203025 0.00187301 0.114304 0.105094 -1 -1 -1 -1 4300 7.78986 1136 2.05797 2073 4078 247328 39648 827486 430936 981244. 2225.04 17 23706 196899 -1 6.6809 6.6809 -514.232 -6.6809 -6.91814 -0.0851 0.19 -1 -1 60.8 MiB 0.13 0.187463 0.170377 60.8 MiB -1 0.04 - soft_fpu_arch_timing.xml ode.v common 40.64 parmys 125.57 MiB -1 -1 23.10 128584 24 4.17 -1 -1 44228 -1 -1 1412 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 94024 130 72 5151 5223 1 3426 1614 40 40 1600 clb auto 48.4 MiB 1.33 35991 777580 261625 505362 10593 91.8 MiB 5.34 0.06 15.9431 -5264.37 -15.9431 15.9431 0.00 0.0117408 0.0100826 1.01252 0.875255 -1 -1 -1 -1 60460 17.6732 15462 4.51973 24242 84687 5987586 871715 3.30999e+06 3.23663e+06 3.73324e+06 2333.28 21 86292 744004 -1 14.8488 14.8488 -4929.15 -14.8488 -50.5031 -0.0851 0.74 -1 -1 91.8 MiB 1.94 1.5713 1.36676 91.8 MiB -1 0.19 - soft_fpu_arch_timing.xml syn2.v common 62.84 parmys 154.08 MiB -1 -1 29.55 157776 24 7.67 -1 -1 48164 -1 -1 2381 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 146376 161 128 8330 8458 1 5909 2670 51 51 2601 clb auto 69.8 MiB 2.37 66146 1576445 571349 976282 28814 142.9 MiB 12.22 0.13 17.1016 -8352.63 -17.1016 17.1016 0.00 0.0199685 0.0180821 1.87397 1.60664 -1 -1 -1 -1 113775 19.4487 28920 4.94359 45588 170928 12281742 1779631 5.50353e+06 5.45769e+06 6.13592e+06 2359.06 21 140346 1220799 -1 15.9299 15.9299 -7817.18 -15.9299 -29.0971 -0.0851 1.30 -1 -1 142.9 MiB 4.07 2.89569 2.48638 142.9 MiB -1 0.35 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +soft_fpu_arch_timing.xml bfly.v common 25.70 parmys 119.72 MiB -1 -1 16.23 122596 23 3.17 -1 -1 39160 -1 -1 1061 193 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85484 193 64 3908 3972 1 2576 1318 35 35 1225 clb auto 43.7 MiB 0.48 79910 23275 535820 162842 363780 9198 83.5 MiB 2.37 0.03 26.2008 15.2827 -3619.83 -15.2827 15.2827 0.00 0.00583731 0.00532945 0.539265 0.456016 -1 -1 -1 -1 41486 16.1111 10615 4.12233 21157 75339 5284993 776800 2.49624e+06 2.43205e+06 2.83731e+06 2316.17 22 66042 566079 -1 13.7882 13.7882 -3355.71 -13.7882 -32.1044 -0.0851 0.41 -1 -1 83.5 MiB 1.36 0.900525 0.772298 83.5 MiB -1 0.14 +soft_fpu_arch_timing.xml bgm.v common 60.02 parmys 257.67 MiB -1 -1 43.09 263856 18 7.15 -1 -1 47244 -1 -1 1479 257 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 98424 257 32 6040 6072 1 3846 1768 41 41 1681 clb auto 55.7 MiB 0.67 136608 31559 920764 325700 583886 11178 96.1 MiB 4.28 0.05 28.1556 12.6901 -5506.58 -12.6901 12.6901 0.00 0.00823797 0.00745153 0.848573 0.704986 -1 -1 -1 -1 53037 13.7973 13649 3.55073 23421 74765 4846056 742834 3.48649e+06 3.39022e+06 3.92715e+06 2336.20 20 90666 782499 -1 12.1348 12.1348 -5104.31 -12.1348 -30.6427 -0.0851 0.55 -1 -1 96.1 MiB 1.45 1.31763 1.11876 96.1 MiB -1 0.18 +soft_fpu_arch_timing.xml dscg.v common 21.73 parmys 118.54 MiB -1 -1 17.10 121384 24 1.26 -1 -1 37208 -1 -1 606 129 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73408 129 64 2192 2256 1 1520 799 27 27 729 clb auto 32.0 MiB 0.25 37820 13615 252807 71072 169981 11754 71.7 MiB 1.02 0.01 24.7174 16.2048 -1915.25 -16.2048 16.2048 0.00 0.00319424 0.00292766 0.253046 0.226671 -1 -1 -1 -1 23619 15.9912 6076 4.11374 10729 37676 2562082 383443 1.43263e+06 1.38908e+06 1.65895e+06 2275.65 22 39258 331839 -1 14.4972 14.4972 -1770.59 -14.4972 -8.16584 -0.0851 0.23 -1 -1 71.7 MiB 0.66 0.44222 0.396859 71.7 MiB -1 0.07 +soft_fpu_arch_timing.xml fir.v common 18.98 parmys 104.27 MiB -1 -1 16.05 106772 16 0.65 -1 -1 35424 -1 -1 473 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71212 161 32 2044 2076 1 1153 666 24 24 576 clb auto 29.5 MiB 0.16 22592 6905 180900 49669 126169 5062 69.5 MiB 0.57 0.01 16.2554 10.8177 -1611.57 -10.8177 10.8177 0.00 0.00217865 0.00192073 0.148828 0.132433 -1 -1 -1 -1 10858 9.43354 2814 2.44483 5861 16059 1047087 162683 1.10943e+06 1.08421e+06 1.29802e+06 2253.51 24 30996 260004 -1 10.1035 10.1035 -1503.91 -10.1035 -41.9575 -0.0851 0.18 -1 -1 69.5 MiB 0.27 0.263872 0.235975 69.5 MiB -1 0.05 +soft_fpu_arch_timing.xml mm3.v common 12.80 parmys 74.96 MiB -1 -1 11.19 76756 11 0.24 -1 -1 33096 -1 -1 188 193 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63472 193 32 892 924 1 551 413 21 21 441 io auto 22.3 MiB 0.07 8826 2864 88022 23644 59473 4905 62.0 MiB 0.32 0.00 9.16995 7.25696 -552.465 -7.25696 7.25696 0.00 0.000933453 0.000846072 0.098381 0.0901077 -1 -1 -1 -1 4134 7.53005 1108 2.01821 2160 4743 285352 45613 827486 430936 981244. 2225.04 23 23706 196899 -1 6.70177 6.70177 -514.125 -6.70177 -7.31444 -0.0851 0.13 -1 -1 62.0 MiB 0.10 0.148211 0.135458 62.0 MiB -1 0.05 +soft_fpu_arch_timing.xml ode.v common 26.43 parmys 123.43 MiB -1 -1 13.73 126388 24 3.93 -1 -1 45256 -1 -1 1403 130 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 100336 130 72 5151 5223 1 3359 1605 40 40 1600 clb auto 52.6 MiB 0.64 118795 35523 743652 244138 490210 9304 98.0 MiB 3.58 0.04 28.0949 16.0769 -5246.14 -16.0769 16.0769 0.00 0.00769968 0.00700229 0.751948 0.617028 -1 -1 -1 -1 59826 17.8372 15257 4.54890 23759 85913 6076912 889657 3.30999e+06 3.216e+06 3.73324e+06 2333.28 20 86292 744004 -1 15.2896 15.2896 -4910.83 -15.2896 -56.4251 -0.0851 0.53 -1 -1 98.0 MiB 1.60 1.19686 1.00822 98.0 MiB -1 0.18 +soft_fpu_arch_timing.xml syn2.v common 41.96 parmys 149.56 MiB -1 -1 17.16 153148 24 7.18 -1 -1 43992 -1 -1 2370 161 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 140116 161 128 8330 8458 1 5899 2659 51 51 2601 clb auto 76.2 MiB 1.15 274570 64420 1567764 565755 975262 26747 136.8 MiB 9.02 0.09 39.1135 16.9598 -8268.93 -16.9598 16.9598 0.00 0.0148804 0.0136535 1.56721 1.24827 -1 -1 -1 -1 111825 19.1481 28457 4.87277 45367 166434 11972783 1740291 5.50353e+06 5.43247e+06 6.13592e+06 2359.06 21 140346 1220799 -1 15.9299 15.9299 -7700.02 -15.9299 -28.1506 -0.0851 0.93 -1 -1 136.8 MiB 3.15 2.40226 1.95187 136.8 MiB -1 0.32 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt index 2054d1011a1..c2c54f3903c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt @@ -1,24 +1,24 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 240.41 vpr 1.80 GiB 274 1048 36 59 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1886012 22 252 53001 29054 7 22984 1419 89 66 5874 DSP auto 1200.1 MiB 62.75 248316 1021579 298715 629192 93672 1841.8 MiB 68.63 0.51 7.79847 -44076.4 -6.79847 3.16357 0.04 0.165964 0.147061 22.0804 19.3916 348037 15.1637 76678 3.34080 64297 133419 118695520 34142571 0 0 1.08074e+08 18398.6 17 1714760 18504579 -1 8.25872 3.11653 -42832.7 -7.25872 0 0 39.08 -1 -1 1841.8 MiB 30.91 29.1651 25.7894 1841.8 MiB -1 9.35 - stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 221.39 vpr 1.47 GiB 36 1585 10 10 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1538160 3 33 48977 39238 1 26095 1641 54 40 2160 LAB auto 1221.8 MiB 84.83 286068 978816 295772 657268 25776 1394.2 MiB 66.20 0.76 87.9237 -89444.7 -86.9237 87.9237 0.01 0.146793 0.123189 13.268 11.0829 379754 14.5550 90020 3.45023 82718 219511 74496266 16257762 0 0 3.96436e+07 18353.5 24 632584 6763270 -1 71.937 71.937 -113847 -70.937 0 0 15.28 -1 -1 1448.2 MiB 25.20 20.4884 17.2546 1394.2 MiB -1 3.21 - stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 444.61 vpr 1.93 GiB 211 2277 3 210 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2019520 38 173 62892 59064 3 35370 2701 86 64 5504 M9K auto 1405.6 MiB 170.24 614048 2033317 732647 1250104 50566 1914.9 MiB 137.20 1.11 13.4281 -360550 -12.4281 8.02047 0.05 0.23718 0.189938 28.8989 23.0941 838072 23.6991 190423 5.38481 138127 489921 156343017 30753609 0 0 1.01286e+08 18402.3 18 1602300 17340426 -1 13.7513 7.61228 -381806 -12.7513 0 0 36.15 -1 -1 1914.9 MiB 51.84 41.0998 33.5135 1914.9 MiB -1 8.59 - stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 501.58 vpr 2.01 GiB 574 2786 16 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2102528 4 570 66175 54803 2 39221 3376 91 67 6097 io auto 1442.3 MiB 161.57 637050 2737396 996225 1655508 85663 2024.4 MiB 158.02 1.26 31.0835 -120493 -30.0835 7.14678 0.05 0.240469 0.215113 28.7629 24.2021 899667 22.9413 200386 5.10980 182427 712388 314287781 64497091 0 0 1.12154e+08 18394.9 22 1777086 19206576 -1 31.4681 7.0455 -124410 -30.4681 0 0 40.06 -1 -1 2024.4 MiB 90.83 43.0922 36.5972 2024.4 MiB -1 9.96 - stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 613.83 vpr 4.71 GiB 40 3697 172 1 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 4942100 19 21 171111 96274 1 69059 3910 194 144 27936 DSP auto 1879.7 MiB 115.33 765653 3945030 1609251 2318045 17734 4826.3 MiB 167.87 1.46 6.56186 -137549 -5.56186 3.59168 0.15 0.576478 0.517383 74.0936 66.3885 885829 12.8277 186548 2.70140 135284 168559 115764486 31200317 0 0 5.18916e+08 18575.2 10 8071764 88644687 -1 6.86266 4.08192 -171393 -5.86266 0 0 170.99 -1 -1 4826.3 MiB 38.25 90.8697 81.8728 4826.3 MiB -1 57.03 - stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 331.14 vpr 1.78 GiB 536 1955 7 4 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1867752 227 309 49176 40422 1 28301 2502 85 63 5355 io auto 1275.0 MiB 118.12 297917 2005906 751440 1231297 23169 1824.0 MiB 109.86 1.00 221.816 -136664 -220.816 221.816 0.03 0.177495 0.149764 22.2953 18.9612 392043 13.8546 93134 3.29130 81629 256552 61785790 11540590 0 0 9.84380e+07 18382.4 20 1549486 16842765 -1 194.877 194.877 -143592 -193.877 0 0 35.33 -1 -1 1824.0 MiB 25.15 30.8256 26.312 1824.0 MiB -1 8.89 - stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 254.24 vpr 1.60 GiB 36 1393 8 149 2 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1675928 3 33 52402 39411 1 26961 1588 73 54 3942 M9K auto 1241.5 MiB 98.93 308817 862861 247827 593176 21858 1636.6 MiB 62.77 0.68 18.2872 -344515 -17.2872 18.2872 0.02 0.157897 0.128343 14.8112 12.1152 431314 16.0024 99151 3.67866 81236 209217 91482078 19724978 0 0 7.26311e+07 18424.9 20 1148308 12423798 -1 18.3421 18.3421 -345738 -17.3421 0 0 26.16 -1 -1 1636.6 MiB 29.12 22.8904 19.0386 1636.6 MiB -1 6.51 - stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 112.25 vpr 1.21 GiB 251 955 1 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1271072 55 196 20131 19956 1 8273 1224 44 33 1452 io auto 1086.4 MiB 51.28 121891 590184 190135 382049 18000 1219.0 MiB 16.74 0.19 8.00991 -79285.3 -7.00991 8.00991 0.01 0.0547434 0.0433722 5.31094 4.24309 175526 21.2244 41043 4.96288 27288 110050 30231721 5468094 0 0 2.65070e+07 18255.5 16 423692 4510959 -1 8.24194 8.24194 -78833.9 -7.24194 0 0 10.69 -1 -1 1219.0 MiB 10.21 7.91932 6.48482 1219.0 MiB -1 2.12 - stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 255.51 vpr 1.50 GiB 255 2122 1 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1577872 84 171 36458 36247 3 20327 2406 62 46 2852 LAB auto 1227.6 MiB 129.85 282856 1613906 577988 956437 79481 1496.3 MiB 54.24 0.51 12.7635 -89890.6 -11.7635 4.81564 0.02 0.13392 0.10812 13.9969 11.3761 395367 19.4637 87910 4.32777 59014 216498 49458484 8714433 0 0 5.24492e+07 18390.3 15 836198 8956163 -1 12.8132 4.74014 -89522.7 -11.8132 0 0 19.60 -1 -1 1496.3 MiB 18.50 19.7465 16.2691 1496.3 MiB -1 4.60 - stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 314.95 vpr 2.14 GiB 69 2192 10 295 16 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2241312 36 33 57796 49182 1 19758 2582 105 78 8190 M9K auto 1352.5 MiB 98.71 254549 2375186 921212 1420848 33126 2188.8 MiB 78.05 0.73 9.75634 -115117 -8.75634 9.75634 0.04 0.165792 0.132975 21.7204 17.5791 406833 20.5960 91948 4.65489 55491 166503 116017937 30967034 0 0 1.50983e+08 18435.1 16 2375962 25880196 -1 8.76007 8.76007 -153174 -7.76007 0 0 52.19 -1 -1 2188.8 MiB 36.04 29.2444 24.0731 2188.8 MiB -1 14.84 - stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 253.58 vpr 2.06 GiB 478 1233 1 300 4 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2160324 202 276 35125 30509 3 21219 2016 106 79 8374 M9K auto 1184.1 MiB 78.17 275268 1593266 551386 986614 55266 2109.7 MiB 49.61 0.39 9.2665 -49067 -8.2665 3.57275 0.07 0.132325 0.103283 17.1511 13.6719 420825 19.8381 90110 4.24787 51659 142658 103986450 24159841 0 0 1.54357e+08 18432.8 12 2427254 26454832 -1 9.68883 3.86627 -55338.2 -8.68883 0 0 53.22 -1 -1 2109.7 MiB 28.24 22.2919 18.1524 2109.7 MiB -1 14.60 - stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 138.75 vpr 1.69 GiB 5 333 31 105 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1766856 3 2 14862 10304 26 7583 476 89 66 5874 DSP auto 1033.6 MiB 52.72 124138 182462 49732 129080 3650 1725.4 MiB 10.74 0.10 5.88079 -31819.8 -4.88079 4.5134 0.03 0.0620074 0.052736 6.45505 5.4875 179249 23.7196 37106 4.91015 18387 40581 28916864 7312373 0 0 1.08074e+08 18398.6 14 1714760 18504579 -1 6.28555 4.43959 -39032.4 -5.28555 0 0 38.39 -1 -1 1725.4 MiB 8.42 8.94725 7.69206 1725.4 MiB -1 9.13 - stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 306.68 vpr 2.16 GiB 693 1797 25 16 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2263960 35 658 51416 37539 1 27427 2531 108 80 8640 io auto 1279.4 MiB 81.16 241934 2243861 754419 1344439 145003 2210.9 MiB 89.43 0.73 41.8615 -66574.8 -40.8615 41.8615 0.05 0.188177 0.163426 25.8422 22.4375 341602 13.1806 80002 3.08685 77035 236832 91449571 21610430 0 0 1.59375e+08 18446.1 27 2505018 27321913 -1 38.4065 38.4065 -64812.4 -37.4065 0 0 54.97 -1 -1 2210.9 MiB 32.24 37.3082 32.5377 2210.9 MiB -1 15.05 - stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 210.13 vpr 2.23 GiB 753 1113 5 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2333568 13 740 25173 25306 1 12716 1903 117 87 10179 io auto 1130.7 MiB 61.79 151917 1239643 452352 735278 52013 2278.9 MiB 28.83 0.25 9.32912 -33745.1 -8.32912 8.97758 0.06 0.0738163 0.0638134 8.87581 7.31746 194710 15.3206 43227 3.40129 29693 108615 25829106 4900313 0 0 1.87944e+08 18463.9 12 2952054 32219012 -1 9.94244 8.79357 -35834.6 -8.94244 0 0 64.11 -1 -1 2278.9 MiB 9.60 12.1982 10.2214 2278.9 MiB -1 18.15 - stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 318.93 vpr 1.67 GiB 117 2338 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1755828 79 38 66795 54922 1 35698 2455 65 48 3120 LAB auto 1328.0 MiB 134.18 278809 1724071 544940 1146248 32883 1591.7 MiB 106.67 0.89 10.5464 -202407 -9.54638 10.5464 0.02 0.1746 0.139886 18.8537 15.1957 365710 10.2454 86560 2.42499 84230 195736 44412238 7890024 0 0 5.74574e+07 18415.8 16 913942 9818425 -1 10.2871 10.2871 -211712 -9.28709 0 0 21.78 -1 -1 1628.9 MiB 18.87 26.6694 21.8451 1591.7 MiB -1 4.70 - stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 189.20 vpr 1.66 GiB 213 1565 26 4 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1740300 139 74 57121 41054 1 24001 1808 75 56 4200 DSP auto 1288.3 MiB 56.40 167389 1300988 426055 839266 35667 1699.5 MiB 56.62 0.52 5.92747 -26440.3 -4.92747 5.12571 0.03 0.163778 0.14022 19.7799 16.8165 226209 9.42655 53807 2.24224 52155 95084 47723189 13084284 0 0 7.74167e+07 18432.5 19 1223026 13250712 -1 6.18889 5.28844 -34182.8 -5.18889 0 0 28.00 -1 -1 1699.5 MiB 17.47 27.5967 23.7139 1699.5 MiB -1 6.59 - stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 104.87 vpr 1.18 GiB 54 665 0 40 0 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1232208 2 52 16673 16662 2 12027 760 37 27 999 LAB auto 1064.4 MiB 40.46 185817 260785 68816 184545 7424 1165.1 MiB 13.84 0.17 6.43593 -22019.6 -5.43593 5.34219 0.01 0.0663137 0.0529365 5.36329 4.35061 252094 20.9676 58089 4.83149 56425 171226 68372675 13142469 0 0 1.81123e+07 18130.5 18 291844 3070977 -1 6.97302 5.70366 -28347.4 -5.97302 0 0 7.59 -1 -1 1183.7 MiB 20.02 8.72317 7.23639 1165.1 MiB -1 1.32 - stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 304.15 vpr 1.76 GiB 445 2156 19 52 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1847692 131 314 57881 45152 1 32833 2672 73 54 3942 io auto 1361.0 MiB 91.84 318946 2041412 717468 1272847 51097 1720.0 MiB 112.21 1.13 221.943 -77080.5 -220.943 221.943 0.03 0.22642 0.192763 26.2516 22.5036 431464 13.1709 103995 3.17455 107179 331669 90059672 17820477 0 0 7.26311e+07 18424.9 19 1148308 12423798 -1 191.341 191.341 -83524.8 -190.341 0 0 25.61 -1 -1 1725.7 MiB 33.11 36.9562 31.8075 1720.0 MiB -1 6.07 - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 56.10 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1212332 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1061.2 MiB 12.53 72155 253216 50624 190930 11662 1175.4 MiB 10.11 0.14 5.18599 -5515.92 -4.18599 2.85104 0.01 0.0377892 0.0327694 2.93008 2.45256 84093 6.76152 20141 1.61944 25550 34715 9357710 1681121 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 5.29142 2.82099 -5638.13 -4.29142 0 0 8.59 -1 -1 1175.4 MiB 3.99 4.67756 3.97624 1175.4 MiB -1 1.60 - stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 339.18 vpr 2.90 GiB 964 1119 19 34 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3043528 542 422 37277 26038 1 20403 2136 147 109 16023 io auto 1148.5 MiB 79.64 272838 1734636 659517 1007756 67363 2972.2 MiB 73.93 0.61 8.43041 -42423.1 -7.43041 8.08995 0.09 0.114426 0.101345 15.7114 13.3677 363091 17.7986 78522 3.84912 59722 139345 87871064 23006283 0 0 2.96647e+08 18513.8 19 4640960 50771684 -1 8.69484 7.49966 -42054.1 -7.69484 0 0 99.20 -1 -1 2972.2 MiB 24.86 21.4146 18.4508 2972.2 MiB -1 30.90 - stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 287.28 vpr 3.37 GiB 1107 725 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3531216 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 1059.1 MiB 60.75 187193 1324022 523278 764997 35747 3448.5 MiB 22.39 0.20 12.7682 -23323.6 -11.7682 6.27217 0.13 0.0592033 0.0490591 7.25586 6.09591 231524 27.1328 38817 4.54905 24809 96129 21440863 3812157 0 0 3.84009e+08 18544.0 14 5987112 65598998 -1 12.9996 6.14541 -26165.8 -11.9996 0 0 128.07 -1 -1 3448.5 MiB 8.23 9.74816 8.27075 3448.5 MiB -1 40.93 - stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 104.00 vpr 1.15 GiB 35 739 0 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1206076 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 1055.9 MiB 57.16 84377 244832 62116 178083 4633 1170.5 MiB 9.34 0.14 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0407227 0.0346923 3.31901 2.66458 119256 18.9777 28323 4.50716 18857 88786 20657004 3728094 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 7.35046 7.35046 -45160 -6.35046 0 0 8.61 -1 -1 1170.5 MiB 7.38 5.40776 4.46635 1170.5 MiB -1 1.72 - stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 25.34 vpr 990.99 MiB 35 78 0 8 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1014772 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 952.6 MiB 5.77 10189 9390 1103 7334 953 991.0 MiB 0.58 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00761951 0.00626889 0.283964 0.242647 14035 9.71280 3656 2.53010 3331 8155 2407464 497474 0 0 3.34790e+06 17437.0 10 54372 558374 -1 5.45077 4.46245 -3957.23 -4.45077 0 0 1.88 -1 -1 991.0 MiB 0.85 0.560139 0.494736 991.0 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 178.61 vpr 1.76 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1847720 22 252 53001 29054 7 22943 1413 89 66 5874 DSP auto 1238.2 MiB 42.50 785441 248898 952533 277008 615830 59695 1804.4 MiB 60.09 0.44 11.048 8.33765 -44315.5 -7.33765 3.31053 0.04 0.128285 0.116554 17.2068 14.794 345230 15.0683 75298 3.28654 62048 127819 110428826 31460146 0 0 1.08074e+08 18398.6 15 1714760 18504579 -1 8.80295 3.22112 -43540.1 -7.80295 0 0 18.55 -1 -1 1804.4 MiB 24.74 22.4983 19.5519 1804.4 MiB -1 10.19 +stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 183.59 vpr 1.47 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1544388 3 33 48977 39238 1 26189 1635 54 40 2160 LAB auto 1259.6 MiB 55.70 913357 292251 954807 280946 652655 21206 1395.6 MiB 73.67 0.73 102.633 87.8923 -93476.3 -86.8923 87.8923 0.01 0.118889 0.106403 14.8002 11.9745 394383 15.0614 93195 3.55910 86770 233493 79349155 17261071 0 0 3.96436e+07 18353.5 23 632584 6763270 -1 72.672 72.672 -124485 -71.672 0 0 6.59 -1 -1 1452.7 MiB 22.92 22.128 18.2926 1395.6 MiB -1 3.32 +stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 360.80 vpr 1.93 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2019012 38 173 62892 59064 3 35490 2705 86 64 5504 M9K auto 1470.0 MiB 114.27 1 617052 1999639 700440 1267006 32193 1878.2 MiB 144.11 1.11 27.1546 13.437 -358967 -12.437 8.02334 0.03 0.255174 0.196212 28.7307 22.3941 840456 23.6868 190561 5.37064 140639 501599 160003214 31544854 0 0 1.01286e+08 18402.3 17 1602300 17340426 -1 13.7513 7.61025 -381512 -12.7513 0 0 17.59 -1 -1 1878.2 MiB 44.84 40.0468 32.041 1878.2 MiB -1 9.80 +stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 429.97 vpr 2.01 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2105408 4 570 66175 54803 2 39253 3378 91 67 6097 io auto 1502.0 MiB 105.57 2 646400 2739558 982870 1670046 86642 1985.6 MiB 156.66 1.38 58.3021 30.6995 -120781 -29.6995 6.48152 0.05 0.223098 0.200113 28.6722 23.0036 931853 23.7427 207645 5.29059 202723 808343 408786124 86440105 0 0 1.12154e+08 18394.9 27 1777086 19206576 -1 31.3244 7.0356 -126420 -30.3244 0 0 19.29 -1 -1 1985.6 MiB 106.14 43.9459 35.9936 1985.6 MiB -1 10.50 +stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 461.22 vpr 4.63 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4858904 19 21 171111 96274 1 69189 3920 194 144 27936 DSP auto 2000.7 MiB 72.95 3 736062 3896690 1544963 2334548 17179 4745.0 MiB 155.85 1.54 8.95431 5.9973 -144922 -4.9973 3.38229 0.14 0.421582 0.369844 55.986 49.4464 859407 12.4217 180010 2.60183 139067 172677 119021364 31947616 0 0 5.18916e+08 18575.2 11 8071764 88644687 -1 6.22445 3.66474 -172467 -5.22445 0 0 88.40 -1 -1 4745.0 MiB 32.65 69.5002 61.9431 4745.0 MiB -1 63.83 +stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 260.17 vpr 1.74 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1828096 227 309 49176 40422 1 28286 2492 85 63 5355 io auto 1318.3 MiB 72.97 1 294102 1944612 718689 1202581 23342 1785.2 MiB 111.92 1.21 334.944 219.151 -136355 -218.151 219.151 0.04 0.23177 0.185498 22.1292 17.849 386971 13.6826 91633 3.23998 84451 274893 65203744 12074645 0 0 9.84380e+07 18382.4 20 1549486 16842765 -1 190.784 190.784 -152276 -189.784 0 0 16.46 -1 -1 1785.2 MiB 23.98 31.3417 25.6009 1785.2 MiB -1 8.74 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 201.52 vpr 1.60 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1677448 3 33 52402 39411 1 26915 1592 74 55 4070 M9K auto 1283.6 MiB 64.51 1 313744 856456 241378 601294 13784 1614.5 MiB 64.76 0.67 26.6374 18.392 -352998 -17.392 18.392 0.02 0.161927 0.129227 15.3284 12.2977 436799 16.2337 99324 3.69138 82951 220275 101115757 21740280 0 0 7.49652e+07 18419.0 23 1184216 12823585 -1 18.4565 18.4565 -355164 -17.4565 0 0 12.45 -1 -1 1614.5 MiB 28.40 23.2769 19.1718 1614.5 MiB -1 6.95 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 86.54 vpr 1.22 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1278736 55 196 20131 19956 1 8019 1227 44 33 1452 io auto 1106.9 MiB 34.97 264174 123065 585601 181370 380069 24162 1221.6 MiB 16.77 0.15 11.4541 8.37477 -85221.8 -7.37477 8.37477 0.01 0.0459827 0.0401336 6.12669 4.71993 177766 22.1764 41334 5.15644 28198 129628 35934453 6384347 0 0 2.65070e+07 18255.5 15 423692 4510959 -1 8.33268 8.33268 -83249.9 -7.33269 0 0 4.84 -1 -1 1221.6 MiB 9.62 8.49386 6.75426 1221.6 MiB -1 3.41 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 191.79 vpr 1.52 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1590420 84 171 36458 36247 3 20790 2367 61 45 2745 LAB auto 1267.3 MiB 81.45 720648 283198 1531863 524079 936471 71313 1468.0 MiB 59.69 0.47 18.575 13.0627 -93585.1 -12.0627 4.74826 0.02 0.133751 0.101046 16.6759 12.8291 395382 19.0307 88123 4.24158 61626 220577 49685974 8803747 0 0 5.05019e+07 18397.8 16 806090 8625815 -1 13.3875 4.68835 -94249.2 -12.3875 0 0 8.71 -1 -1 1486.0 MiB 15.75 22.1054 17.4525 1468.0 MiB -1 4.73 +stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 242.56 vpr 2.10 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2203044 36 33 57796 49182 1 19635 2569 105 78 8190 M9K auto 1407.4 MiB 66.69 791464 250120 2359227 910890 1421031 27306 2151.4 MiB 69.03 0.59 16.1586 10.1368 -104381 -9.13679 10.1368 0.04 0.150021 0.116231 19.0365 14.944 404831 20.6231 91490 4.66072 55298 173053 127957013 34281032 0 0 1.50983e+08 18435.1 14 2375962 25880196 -1 9.14404 9.14404 -149500 -8.14404 0 0 26.91 -1 -1 2151.4 MiB 36.76 25.2394 20.3316 2151.4 MiB -1 15.86 +stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 194.04 vpr 2.02 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2120592 202 276 35125 30509 3 21318 2020 106 79 8374 M9K auto 1222.0 MiB 50.40 986671 267666 1508172 523381 949193 35598 2070.9 MiB 49.00 0.39 11.3759 9.26548 -48475.6 -8.26548 3.33529 0.04 0.141226 0.106959 15.9435 12.2592 429424 20.1494 89684 4.20815 53710 152511 120492230 28061271 0 0 1.54357e+08 18432.8 13 2427254 26454832 -1 9.61434 3.56952 -53683.9 -8.61434 0 0 25.62 -1 -1 2070.9 MiB 29.72 20.7976 16.4493 2070.9 MiB -1 16.05 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 85.25 vpr 1.65 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1726980 3 2 14862 10304 26 7561 466 89 66 5874 DSP auto 1055.0 MiB 19.84 270018 117214 172036 45994 123462 2580 1686.5 MiB 10.03 0.10 9.28243 6.01869 -39114.1 -5.01869 4.08518 0.05 0.0630093 0.0580388 6.722 5.63193 170213 22.5896 35826 4.75461 18131 39933 29145420 7349754 0 0 1.08074e+08 18398.6 16 1714760 18504579 -1 6.15886 4.10146 -48278.1 -5.15886 0 0 18.54 -1 -1 1686.5 MiB 8.34 9.0919 7.75971 1686.5 MiB -1 10.44 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 244.08 vpr 2.11 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2215808 35 658 51416 37539 1 27424 2511 108 80 8640 io auto 1315.7 MiB 54.87 1 251917 2152071 724984 1286743 140344 2163.9 MiB 89.22 0.66 74.2949 42.7394 -67262.7 -41.7394 42.7394 0.11 0.164209 0.133322 22.9478 19.0876 358128 13.8204 82658 3.18983 77956 237354 113781969 26958054 0 0 1.59375e+08 18446.1 20 2505018 27321913 -1 40.4536 40.4536 -65567.3 -39.4536 0 0 28.03 -1 -1 2163.9 MiB 29.51 30.9219 26.042 2163.9 MiB -1 17.15 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 150.60 vpr 2.18 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2288012 13 740 25173 25306 1 12838 1890 117 87 10179 io auto 1157.0 MiB 38.37 599292 157888 1216610 423982 737752 54876 2234.4 MiB 31.48 0.38 14.8829 8.76456 -34576 -7.76456 8.70409 0.05 0.180848 0.151857 10.946 8.66397 200775 15.6476 43818 3.41501 31234 113917 27219910 5157022 0 0 1.87944e+08 18463.9 11 2952054 32219012 -1 9.15588 8.09218 -36950.2 -8.15588 0 0 31.40 -1 -1 2234.4 MiB 9.82 14.7216 11.9704 2234.4 MiB -1 19.18 +stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 279.74 vpr 1.68 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1764116 79 38 66795 54922 1 35224 2428 64 47 3008 LAB auto 1380.9 MiB 97.02 1 268287 1649940 503404 1107473 39063 1560.8 MiB 122.78 1.01 22.8938 10.5192 -202497 -9.51918 10.5192 0.03 0.17581 0.134211 21.3606 16.582 359112 10.1960 84742 2.40601 85648 207489 45894038 8018949 0 0 5.53261e+07 18393.0 17 880106 9448176 -1 10.0961 10.0961 -210217 -9.09605 0 0 9.73 -1 -1 1634.6 MiB 17.85 29.5446 23.5411 1560.8 MiB -1 6.71 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betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1232808 2 52 16673 16662 2 11970 759 37 27 999 LAB auto 1087.4 MiB 26.11 329275 182496 253339 66599 180853 5887 1148.2 MiB 14.60 0.17 8.48983 6.31912 -21812.1 -5.31912 5.08034 0.00 0.074231 0.0564117 6.79754 5.19634 250865 20.9648 57898 4.83854 58768 177050 72729449 14016095 0 0 1.81123e+07 18130.5 23 291844 3070977 -1 6.7711 5.47952 -27099.2 -5.7711 0 0 3.13 -1 -1 1183.7 MiB 20.25 10.785 8.59916 1148.2 MiB -1 1.43 +stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 245.81 vpr 1.76 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1844232 131 314 57881 45152 1 32883 2670 73 54 3942 io auto 1411.7 MiB 65.76 1 312017 2002290 686807 1268658 46825 1677.7 MiB 109.35 1.05 300.2 218.773 -77846.7 -217.773 218.773 0.02 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2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 3470396 403 704 15490 16194 1 8443 1837 167 124 20708 io auto 1075.8 MiB 34.73 580890 183895 1261389 465912 759977 35500 3389.1 MiB 18.07 0.17 21.2837 12.8498 -23740.4 -11.8498 6.01594 0.10 0.0528114 0.0410491 6.17736 4.93541 224259 26.5647 38487 4.55899 24297 97387 21330701 3812192 0 0 3.84009e+08 18544.0 15 5987112 65598998 -1 12.926 6.10097 -26548.2 -11.926 0 0 67.11 -1 -1 3389.1 MiB 6.81 8.38896 6.88343 3389.1 MiB -1 42.72 +stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 70.04 vpr 1.15 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1207840 18 17 16969 16357 1 6487 772 39 29 1131 LAB auto 1073.0 MiB 36.26 189359 78593 245032 60572 181809 2651 1152.0 MiB 7.48 0.10 11.1993 7.7388 -41982.4 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a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt index ad32242d902..a5b66d2ee80 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt @@ -1,41 +1,41 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml alu4.blif common 11.61 vpr 67.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 490 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69184 14 8 1536 1544 0 1075 512 25 25 625 clb auto 27.3 MiB 0.36 13907 125379 37375 86426 1578 67.6 MiB 0.92 0.01 13.7808 -101.412 -13.7808 nan 0.38 0.00351706 0.00307653 0.230026 0.203296 -1 -1 -1 -1 26 21244 40 1.587e+07 1.47e+07 -1 -1 7.83 1.39924 1.1896 22338 287359 -1 19467 17 6635 26447 1985465 198804 17.3063 nan -123.659 -17.3063 0 0 -1 -1 0.05 0.39 0.12 -1 -1 0.05 0.105099 0.0941024 - k4_n4_v7_bidir.xml apex2.blif common 22.22 vpr 70.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 626 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71692 38 3 1916 1919 0 1483 667 28 28 784 clb auto 29.5 MiB 0.29 19984 195838 60682 130920 4236 70.0 MiB 1.45 0.02 17.0385 -49.2963 -17.0385 nan 0.49 0.00449691 0.00389108 0.328393 0.287877 -1 -1 -1 -1 28 30181 48 2.028e+07 1.878e+07 -1 -1 17.00 1.80013 1.5249 28758 383844 -1 28376 15 9150 33071 2590424 247096 20.7907 nan -60.2269 -20.7907 0 0 -1 -1 0.07 0.68 0.22 -1 -1 0.07 0.170018 0.15064 - k4_n4_v7_bidir.xml apex4.blif common 9.32 vpr 64.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 434 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66272 9 19 1271 1290 0 989 462 23 23 529 clb auto 25.3 MiB 0.38 13918 105777 29780 74317 1680 64.7 MiB 0.80 0.01 13.9047 -226.083 -13.9047 nan 0.32 0.00309616 0.00274963 0.190094 0.170268 -1 -1 -1 -1 31 20642 28 1.323e+07 1.302e+07 -1 -1 5.45 1.02556 0.874569 20514 283063 -1 19844 22 7738 30852 2604644 234674 16.6245 nan -269.64 -16.6245 0 0 -1 -1 0.05 0.64 0.16 -1 -1 0.05 0.148675 0.128977 - k4_n4_v7_bidir.xml bigkey.blif common 11.94 vpr 70.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 492 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72020 229 197 2152 2349 1 1586 918 29 29 841 io auto 29.9 MiB 0.37 13173 415605 135003 270551 10051 70.3 MiB 2.27 0.03 7.81345 -1868.02 -7.81345 7.81345 0.52 0.0065376 0.00583609 0.598798 0.540386 -1 -1 -1 -1 18 19586 48 2.187e+07 1.476e+07 -1 -1 5.81 2.28089 2.02935 25794 279159 -1 18213 18 8082 24448 1355876 164744 9.41024 9.41024 -2355.47 -9.41024 0 0 -1 -1 0.05 0.56 0.16 -1 -1 0.05 0.23271 0.207395 - k4_n4_v7_bidir.xml clma.blif common 111.22 vpr 201.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2648 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 206200 62 82 8460 8542 1 6288 2792 54 54 2916 clb auto 75.5 MiB 2.26 106658 1830428 722593 1094428 13407 201.4 MiB 14.42 0.15 27.2182 -1339.27 -27.2182 27.2182 2.09 0.0213137 0.0174867 2.12276 1.76542 -1 -1 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-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69484 64 39 1935 1974 1 1077 542 23 23 529 clb auto 28.0 MiB 0.35 10284 139709 36550 99088 4071 67.9 MiB 1.01 0.02 13.3471 -2484.01 -13.3471 13.3471 0.32 0.00419252 0.00369096 0.286261 0.253568 -1 -1 -1 -1 20 14214 22 1.323e+07 1.317e+07 -1 -1 3.69 1.10599 0.957164 16818 186659 -1 13852 17 5686 19604 1108385 127625 15.0107 15.0107 -3068.04 -15.0107 0 0 -1 -1 0.03 0.41 0.10 -1 -1 0.03 0.166567 0.14676 - k4_n4_v7_bidir.xml dsip.blif common 12.60 vpr 68.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 443 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69640 229 197 1815 2012 1 1190 869 29 29 841 io auto 27.9 MiB 0.38 11973 394644 125240 259207 10197 68.0 MiB 2.08 0.03 7.81345 -1864.07 -7.81345 7.81345 0.53 0.00544034 0.00496078 0.530962 0.484759 -1 -1 -1 -1 16 17634 29 2.187e+07 1.329e+07 -1 -1 6.87 1.81366 1.63082 24114 234671 -1 15615 17 6539 22470 1305981 155172 8.39336 8.39336 -2240 -8.39336 0 0 -1 -1 0.05 0.52 0.14 -1 -1 0.05 0.212997 0.192439 - k4_n4_v7_bidir.xml elliptic.blif common 38.32 vpr 90.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 92796 131 114 4855 4969 1 2112 1268 34 34 1156 clb auto 44.4 MiB 0.81 32596 556928 195696 354146 7086 90.6 MiB 3.80 0.04 24.1099 -12023.9 -24.1099 24.1099 0.75 0.0102584 0.0091465 0.934203 0.802866 -1 -1 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66324 9 19 1271 1290 0 989 462 23 23 529 clb auto 25.3 MiB 0.24 13905 125412 38326 85376 1710 64.8 MiB 0.93 0.01 18.3289 -292.406 -18.3289 nan 0.54 0.00295728 0.00263697 0.223166 0.199747 -1 -1 -1 -1 24 15651 33 1.323e+07 1.302e+07 -1 -1 24.88 1.17628 0.99802 39522 283015 -1 14291 16 7091 27457 2432804 329588 18.2498 nan -294.601 -18.2498 0 0 -1 -1 0.06 0.66 0.21 -1 -1 0.06 0.117459 0.103392 - k4_n4_v7_l1_bidir.xml bigkey.blif common 20.11 vpr 79.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 492 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81376 229 197 2152 2349 1 1586 918 29 29 841 io auto 30.2 MiB 0.23 13124 451277 143814 296619 10844 79.3 MiB 2.42 0.03 10.2071 -2455.12 -10.2071 10.2071 0.88 0.005948 0.00536127 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69448 64 39 1935 1974 1 1077 542 23 23 529 clb auto 27.9 MiB 0.36 10163 148545 42077 102375 4093 67.8 MiB 1.08 0.02 12.0441 -2875.38 -12.0441 12.0441 0.56 0.00430479 0.0037965 0.308045 0.272397 -1 -1 -1 -1 16 10332 33 1.323e+07 1.317e+07 -1 -1 6.74 1.30841 1.12025 28434 179743 -1 9483 18 6528 24074 1365996 234850 12.4631 12.4631 -3015.42 -12.4631 0 0 -1 -1 0.04 0.61 0.13 -1 -1 0.04 0.194916 0.171717 - k4_n4_v7_l1_bidir.xml dsip.blif common 18.79 vpr 77.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 443 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79492 229 197 1815 2012 1 1190 869 29 29 841 io auto 28.0 MiB 0.38 12024 411224 134532 266541 10151 77.3 MiB 2.23 0.03 11.1435 -2606.08 -11.1435 11.1435 0.94 0.00566744 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 8 63 1072 1135 0 898 438 22 22 484 clb auto 24.2 MiB 0.28 11915 106806 31455 73557 1794 63.5 MiB 0.77 0.01 16.2558 -718.217 -16.2558 nan 0.47 0.00280855 0.00253426 0.195106 0.176517 -1 -1 -1 -1 24 13413 30 1.2e+07 1.101e+07 -1 -1 17.58 1.01507 0.875233 36000 257712 -1 11900 15 6787 23733 1853955 288518 16.2529 nan -726.803 -16.2529 0 0 -1 -1 0.05 0.53 0.19 -1 -1 0.05 0.103489 0.0915351 - k4_n4_v7_l1_bidir.xml frisc.blif common 94.05 vpr 121.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1094 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 123920 20 116 4445 4561 1 2290 1230 36 36 1296 clb auto 44.1 MiB 0.99 38255 580886 202911 367450 10525 120.6 MiB 4.25 0.05 29.223 -16576.9 -29.223 29.223 1.43 0.0105708 0.00897893 0.999254 0.851085 -1 -1 -1 -1 26 40614 39 3.468e+07 3.282e+07 -1 -1 79.50 4.26322 3.57492 104992 763300 -1 37284 18 13336 60167 5347576 900846 28.6821 28.6821 -16996 -28.6821 0 0 -1 -1 0.20 1.82 0.58 -1 -1 0.20 0.421201 0.366517 - k4_n4_v7_l1_bidir.xml misex3.blif common 17.56 vpr 65.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 450 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67284 14 14 1411 1425 0 1056 478 24 24 576 clb auto 26.1 MiB 0.40 13799 121898 36530 83432 1936 65.7 MiB 0.91 0.01 18.1166 -222.755 -18.1166 nan 0.58 0.00323875 0.00286176 0.229781 0.204181 -1 -1 -1 -1 21 15917 38 1.452e+07 1.35e+07 -1 -1 12.60 1.01596 0.869596 39160 271852 -1 13861 19 6925 26912 1892268 324238 17.8372 nan -222.89 -17.8372 0 0 -1 -1 0.06 0.66 0.21 -1 -1 0.06 0.14886 0.130215 - k4_n4_v7_l1_bidir.xml pdc.blif common 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/home/elgamma8/research/release/vtr-verilog-to-routing 71716 4 6 1942 1948 1 1167 583 26 26 676 clb auto 29.8 MiB 0.37 13721 168529 51547 115716 1266 70.0 MiB 1.27 0.02 26.8992 -206.444 -26.8992 26.8992 0.69 0.00496419 0.00432315 0.361202 0.317423 -1 -1 -1 -1 17 15103 41 1.728e+07 1.719e+07 -1 -1 8.88 1.36971 1.16775 39072 254696 -1 13708 17 7890 40380 2928639 390491 25.7904 25.7904 -205.684 -25.7904 0 0 -1 -1 0.06 0.94 0.21 -1 -1 0.06 0.209805 0.184411 - k4_n4_v7_l1_bidir.xml s38417.blif common 61.66 vpr 189.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1852 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 193636 29 106 7534 7640 1 4623 1987 46 46 2116 clb auto 61.8 MiB 1.63 45682 1150699 423694 711314 15691 189.1 MiB 8.82 0.10 24.016 -14000.6 -24.016 24.016 2.46 0.0169007 0.0139461 1.64128 1.36389 -1 -1 -1 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69.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 567 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71260 41 35 1791 1826 0 1347 643 26 26 676 clb auto 29.0 MiB 0.45 18608 203145 65187 132320 5638 69.6 MiB 1.44 0.02 18.1385 -520.265 -18.1385 nan 0.69 0.00437225 0.00383137 0.338582 0.298021 -1 -1 -1 -1 24 20201 48 1.728e+07 1.701e+07 -1 -1 33.10 1.88123 1.59699 51072 366016 -1 19098 15 8908 34158 2699342 394310 17.881 nan -530.81 -17.881 0 0 -1 -1 0.08 0.83 0.27 -1 -1 0.08 0.160739 0.141136 - k4_n4_v7_l1_bidir.xml spla.blif common 187.45 vpr 130.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1282 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 133456 16 46 3706 3752 0 2852 1344 38 38 1444 clb auto 43.1 MiB 1.08 48851 705674 261242 438237 6195 129.8 MiB 4.82 0.05 28.2789 -928.469 -28.2789 nan 1.62 0.00923375 0.00767658 0.87033 0.724376 -1 -1 -1 -1 30 55651 36 3.888e+07 3.846e+07 -1 -1 170.35 3.95474 3.27046 133344 1000208 -1 49871 15 17906 78246 6885546 1014380 27.1504 nan -941.372 -27.1504 0 0 -1 -1 0.25 2.27 0.77 -1 -1 0.25 0.36105 0.312454 - k4_n4_v7_l1_bidir.xml tseng.blif common 6.87 vpr 64.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 52 122 1483 1605 1 725 466 20 20 400 clb auto 25.0 MiB 0.16 6135 112438 30480 78177 3781 64.4 MiB 0.46 0.01 11.1777 -2780.46 -11.1777 11.1777 0.26 0.00160816 0.00140359 0.112456 0.0992435 -1 -1 -1 -1 14 6150 30 9.72e+06 8.76e+06 -1 -1 4.21 0.681536 0.590913 19872 120996 -1 5573 18 4232 15969 711167 147306 11.3812 11.3812 -3151.62 -11.3812 0 0 -1 -1 0.03 0.34 0.09 -1 -1 0.03 0.138745 0.122462 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml alu4.blif common 10.51 vpr 68.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 493 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70036 14 8 1536 1544 0 1104 515 25 25 625 clb auto 29.0 MiB 0.19 26012 13956 130484 38677 90196 1611 68.4 MiB 0.65 0.01 30.5457 14.3537 -102.59 -14.3537 nan 0.26 0.00281681 0.00240697 0.187334 0.163939 -1 -1 -1 -1 26 20892 39 1.587e+07 1.479e+07 -1 -1 7.59 1.21065 1.03445 22338 287359 -1 19730 15 6783 25798 1828199 189550 17.7661 nan -122.524 -17.7661 0 0 -1 -1 0.05 0.42 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betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67436 9 19 1271 1290 0 978 458 23 23 529 clb auto 26.9 MiB 0.18 23165 13695 104534 29903 73052 1579 65.9 MiB 0.54 0.01 28.8439 13.8799 -228.564 -13.8799 nan 0.22 0.00213336 0.00186974 0.144465 0.12771 -1 -1 -1 -1 30 20988 39 1.323e+07 1.29e+07 -1 -1 3.43 0.645416 0.557775 20514 283063 -1 19517 20 7190 27765 2407390 214953 17.1513 nan -274.971 -17.1513 0 0 -1 -1 0.05 0.52 0.10 -1 -1 0.05 0.121889 0.109083 +k4_n4_v7_bidir.xml bigkey.blif common 7.98 vpr 72.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 495 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74280 229 197 2152 2349 1 1362 921 29 29 841 io auto 32.6 MiB 0.19 35109 13449 426426 141391 275290 9745 72.5 MiB 1.50 0.02 17.7693 8.07704 -1976.29 -8.07704 8.07704 0.38 0.00372809 0.00338054 0.394382 0.338936 -1 -1 -1 -1 17 21055 43 2.187e+07 1.485e+07 -1 -1 3.55 1.31321 1.13689 24954 256911 -1 18767 22 7669 28488 1689811 197748 8.90589 8.90589 -2364.61 -8.90589 0 0 -1 -1 0.05 0.57 0.09 -1 -1 0.05 0.211757 0.182394 +k4_n4_v7_bidir.xml clma.blif common 72.81 vpr 204.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2657 62 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 209040 62 82 8460 8542 1 6311 2801 54 54 2916 clb auto 83.4 MiB 1.21 318304 107423 1818513 710165 1094335 14013 185.0 MiB 11.36 0.12 109.907 27.5529 -1348.77 -27.5529 27.5529 1.54 0.0211071 0.015896 2.13139 1.63007 -1 -1 -1 -1 38 141343 26 8.112e+07 7.971e+07 -1 -1 48.13 10.3163 8.13924 126538 2024156 -1 136720 18 37710 139608 13309903 1205243 31.5727 31.5727 -1662.82 -31.5727 0 0 -1 -1 0.44 3.25 0.76 -1 -1 0.44 0.881408 0.751274 +k4_n4_v7_bidir.xml des.blif common 11.20 vpr 70.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 476 256 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72576 256 245 1847 2092 0 1369 977 34 34 1156 io auto 31.1 MiB 0.21 41834 16325 359581 117023 229258 13300 70.9 MiB 1.19 0.02 35.0204 12.3184 -2297.36 -12.3184 nan 0.54 0.0041646 0.00363216 0.330541 0.290991 -1 -1 -1 -1 19 23462 24 3.072e+07 1.428e+07 -1 -1 6.50 1.75122 1.56086 35364 387024 -1 21500 20 8895 34040 2269814 254049 14.4581 nan -2758.91 -14.4581 0 0 -1 -1 0.07 0.67 0.14 -1 -1 0.07 0.210732 0.193886 +k4_n4_v7_bidir.xml diffeq.blif common 6.94 vpr 70.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71700 64 39 1935 1974 1 1075 541 23 23 529 clb auto 29.9 MiB 0.19 23859 10147 137127 36471 96425 4231 70.0 MiB 0.69 0.01 41.0644 13.3365 -2669.73 -13.3365 13.3365 0.22 0.00307747 0.00279215 0.219066 0.191584 -1 -1 -1 -1 22 15029 23 1.323e+07 1.314e+07 -1 -1 4.23 1.25599 1.07312 17346 200431 -1 14015 19 6333 22933 1286086 145452 15.0001 15.0001 -3348.78 -15.0001 0 0 -1 -1 0.03 0.37 0.07 -1 -1 0.03 0.145127 0.125426 +k4_n4_v7_bidir.xml dsip.blif common 8.58 vpr 69.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 389 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71388 229 197 1815 2012 1 807 815 29 29 841 io auto 30.0 MiB 0.16 25997 11221 343265 110526 223443 9296 69.7 MiB 1.08 0.02 17.1219 7.67764 -1783.63 -7.67764 7.67764 0.36 0.00298296 0.0026384 0.281491 0.250692 -1 -1 -1 -1 16 16775 35 2.187e+07 1.167e+07 -1 -1 5.15 1.02398 0.911506 24114 234671 -1 14644 15 4531 21507 1204494 145014 9.11187 9.11187 -2273.02 -9.11187 0 0 -1 -1 0.04 0.33 0.09 -1 -1 0.04 0.11086 0.100347 +k4_n4_v7_bidir.xml elliptic.blif common 29.82 vpr 87.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 89544 131 114 4855 4969 1 2121 1268 34 34 1156 clb auto 48.7 MiB 0.44 68213 32063 543208 185567 349249 8392 87.4 MiB 2.80 0.03 61.3729 21.5739 -11984.7 -21.5739 21.5739 0.54 0.00803406 0.00736046 0.785189 0.651665 -1 -1 -1 -1 30 48184 36 3.072e+07 3.069e+07 -1 -1 21.83 3.75848 3.07433 44604 633776 -1 42454 19 10655 49988 3826867 357795 25.477 25.477 -14698.3 -25.477 0 0 -1 -1 0.12 1.06 0.22 -1 -1 0.12 0.378996 0.331672 +k4_n4_v7_bidir.xml ex1010.blif common 34.63 vpr 112.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1571 10 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 115556 10 10 4608 4618 0 3567 1591 42 42 1764 clb auto 52.9 MiB 0.62 147879 45540 753595 262722 489179 1694 110.2 MiB 4.73 0.06 52.4545 24.5398 -234.737 -24.5398 nan 0.87 0.010526 0.0078576 0.90398 0.714975 -1 -1 -1 -1 28 65394 19 4.8e+07 4.713e+07 -1 -1 22.87 4.65072 3.73099 64374 881208 -1 63107 16 23300 93509 5730584 607346 28.9188 nan -276.935 -28.9188 0 0 -1 -1 0.18 1.67 0.32 -1 -1 0.18 0.416222 0.360241 +k4_n4_v7_bidir.xml ex5p.blif common 6.78 vpr 64.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 8 63 1072 1135 0 892 433 22 22 484 clb auto 25.5 MiB 0.18 19665 12146 83920 21665 60035 2220 64.5 MiB 0.41 0.01 27.1613 14.1695 -641.804 -14.1695 nan 0.26 0.00194483 0.00175051 0.110247 0.100056 -1 -1 -1 -1 28 18857 41 1.2e+07 1.086e+07 -1 -1 4.37 0.597322 0.524339 17814 232968 -1 17191 17 7020 24726 2122321 206092 17.5715 nan -811.991 -17.5715 0 0 -1 -1 0.04 0.43 0.08 -1 -1 0.04 0.0982758 0.0881937 +k4_n4_v7_bidir.xml frisc.blif common 39.90 vpr 90.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1093 20 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 92668 20 116 4445 4561 1 2268 1229 36 36 1296 clb auto 47.9 MiB 0.52 82225 38746 540789 181172 349115 10502 89.0 MiB 2.95 0.03 92.1602 27.8548 -13906.2 -27.8548 27.8548 0.63 0.00762553 0.00692883 0.766368 0.640122 -1 -1 -1 -1 32 55435 34 3.468e+07 3.279e+07 -1 -1 31.30 4.3095 3.55018 51266 747164 -1 51352 19 12718 59152 4839669 471177 31.6271 31.6271 -16668.9 -31.6271 0 0 -1 -1 0.15 1.25 0.27 -1 -1 0.15 0.39857 0.343255 +k4_n4_v7_bidir.xml misex3.blif common 8.20 vpr 67.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 456 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69504 14 14 1411 1425 0 1058 484 24 24 576 clb auto 28.0 MiB 0.19 25286 13398 116323 33249 81241 1833 67.9 MiB 0.59 0.01 27.5808 12.9766 -166.337 -12.9766 nan 0.24 0.00253725 0.00218076 0.16921 0.146768 -1 -1 -1 -1 27 22296 50 1.452e+07 1.368e+07 -1 -1 5.36 1.0053 0.860066 21174 279108 -1 19502 18 7476 29328 2259232 221453 15.1329 nan -197.55 -15.1329 0 0 -1 -1 0.05 0.50 0.10 -1 -1 0.05 0.123896 0.111321 +k4_n4_v7_bidir.xml pdc.blif common 47.91 vpr 121.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1617 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 124552 16 40 4591 4631 0 3619 1673 43 43 1849 clb auto 55.2 MiB 0.79 148382 72050 825614 301727 519289 4598 115.6 MiB 5.29 0.06 57.6272 23.7689 -838.224 -23.7689 nan 0.93 0.0150982 0.0114412 1.21295 0.93889 -1 -1 -1 -1 42 105308 49 5.043e+07 4.851e+07 -1 -1 33.47 5.76976 4.57688 84090 1373187 -1 98071 20 23761 104231 12283114 1054649 28.8448 nan -1019.25 -28.8448 0 0 -1 -1 0.29 2.87 0.57 -1 -1 0.29 0.621586 0.531079 +k4_n4_v7_bidir.xml s298.blif common 7.14 vpr 71.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 574 4 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73680 4 6 1942 1948 1 1159 584 26 26 676 clb auto 32.4 MiB 0.21 26193 13170 154304 44587 108633 1084 72.0 MiB 0.89 0.01 59.8244 21.6938 -165.88 -21.6938 21.6938 0.29 0.00418138 0.00347077 0.284209 0.236941 -1 -1 -1 -1 22 20764 41 1.728e+07 1.722e+07 -1 -1 3.70 1.0034 0.843428 22122 258376 -1 18543 20 6776 35839 2195452 220622 26.0696 26.0696 -206.718 -26.0696 0 0 -1 -1 0.04 0.56 0.09 -1 -1 0.04 0.167447 0.146467 +k4_n4_v7_bidir.xml s38417.blif common 38.14 vpr 133.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1839 29 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 137148 29 106 7534 7640 1 4625 1974 45 45 2025 clb auto 67.5 MiB 0.93 182366 49147 1115994 411126 689649 15219 131.3 MiB 7.02 0.09 69.8886 18.1305 -11126 -18.1305 18.1305 1.12 0.0167919 0.0133128 1.55146 1.22292 -1 -1 -1 -1 26 62916 18 5.547e+07 5.517e+07 -1 -1 22.18 6.66465 5.36506 71818 959559 -1 61826 21 25212 85364 5272227 577542 22.2241 22.2241 -13589.6 -22.2241 0 0 -1 -1 0.20 1.77 0.35 -1 -1 0.20 0.746813 0.639752 +k4_n4_v7_bidir.xml s38584.1.blif common 26.45 vpr 130.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1785 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 134000 38 304 7475 7779 1 4307 2127 45 45 2025 clb auto 67.2 MiB 0.79 169496 43700 1260043 468320 769335 22388 130.9 MiB 6.66 0.09 46.6882 12.4704 -8838.49 -12.4704 12.4704 1.02 0.0150387 0.011511 1.56356 1.2059 -1 -1 -1 -1 22 57407 29 5.547e+07 5.355e+07 -1 -1 11.74 5.32525 4.24948 65746 795487 -1 53993 24 21202 68197 3819694 436287 15.8262 15.8262 -10638.4 -15.8262 0 0 -1 -1 0.17 1.66 0.29 -1 -1 0.17 0.826696 0.695763 +k4_n4_v7_bidir.xml seq.blif common 11.14 vpr 69.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 563 41 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71080 41 35 1791 1826 0 1358 639 26 26 676 clb auto 30.7 MiB 0.24 34655 19019 179454 52780 121688 4986 69.4 MiB 0.97 0.01 28.2438 14.5406 -418.614 -14.5406 nan 0.30 0.00347682 0.00287878 0.275951 0.233536 -1 -1 -1 -1 31 27432 31 1.728e+07 1.689e+07 -1 -1 7.47 1.4478 1.22337 26172 364912 -1 25996 16 8273 30805 2346654 227901 18.1758 nan -502.399 -18.1758 0 0 -1 -1 0.06 0.53 0.13 -1 -1 0.06 0.140373 0.124717 +k4_n4_v7_bidir.xml spla.blif common 39.46 vpr 96.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1295 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 98848 16 46 3706 3752 0 2830 1357 38 38 1444 clb auto 47.2 MiB 0.58 104307 47860 579550 196916 377929 4705 93.3 MiB 3.12 0.04 52.5658 19.3022 -663.123 -19.3022 nan 0.70 0.00738583 0.00664122 0.704824 0.552684 -1 -1 -1 -1 36 71709 36 3.888e+07 3.885e+07 -1 -1 29.89 3.77665 2.98889 59972 912004 -1 67441 20 18417 83736 8422141 758154 24.4024 nan -837.791 -24.4024 0 0 -1 -1 0.21 1.77 0.32 -1 -1 0.21 0.388862 0.328321 +k4_n4_v7_bidir.xml tseng.blif common 4.87 vpr 65.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67424 52 122 1483 1605 1 721 466 20 20 400 clb auto 26.6 MiB 0.14 14453 6266 110632 29522 77317 3793 65.8 MiB 0.50 0.01 29.8881 13.1236 -2386.51 -13.1236 13.1236 0.16 0.00222333 0.00202089 0.166559 0.150191 -1 -1 -1 -1 18 10091 45 9.72e+06 8.76e+06 -1 -1 2.86 0.749946 0.658853 12348 129228 -1 8546 20 3970 14140 657005 83311 15.2834 15.2834 -3062.53 -15.2834 0 0 -1 -1 0.02 0.22 0.04 -1 -1 0.02 0.101198 0.0913371 +k4_n4_v7_l1_bidir.xml alu4.blif common 10.53 vpr 68.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 493 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70036 14 8 1536 1544 0 1104 515 25 25 625 clb auto 28.8 MiB 0.20 26012 13882 144925 44962 98128 1835 68.4 MiB 0.75 0.01 45.0652 18.3459 -138.341 -18.3459 nan 0.38 0.00307527 0.0026122 0.230228 0.198221 -1 -1 -1 -1 21 14740 32 1.587e+07 1.479e+07 -1 -1 6.92 1.0599 0.899376 42642 296151 -1 13671 16 6751 27151 1578234 268986 18.5341 nan -138.309 -18.5341 0 0 -1 -1 0.07 0.51 0.11 -1 -1 0.07 0.117569 0.10406 +k4_n4_v7_l1_bidir.xml apex2.blif common 34.31 vpr 70.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 625 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72144 38 3 1916 1919 0 1483 666 27 27 729 clb auto 31.4 MiB 0.30 39268 20542 218691 70799 142856 5036 70.5 MiB 1.09 0.01 56.8542 22.1453 -63.6176 -22.1453 nan 0.53 0.003642 0.00303919 0.293084 0.248885 -1 -1 -1 -1 23 23305 46 1.875e+07 1.875e+07 -1 -1 29.32 1.46884 1.22779 52650 371955 -1 21163 16 9774 36558 3184705 468372 21.3859 nan -62.3911 -21.3859 0 0 -1 -1 0.08 0.90 0.23 -1 -1 0.08 0.170377 0.150501 +k4_n4_v7_l1_bidir.xml apex4.blif common 23.46 vpr 66.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 430 9 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67932 9 19 1271 1290 0 978 458 23 23 529 clb auto 27.3 MiB 0.16 23165 13634 123938 37969 84511 1458 66.3 MiB 0.63 0.01 45.8408 17.9211 -294.82 -17.9211 nan 0.31 0.00224286 0.00198234 0.174028 0.153204 -1 -1 -1 -1 23 16880 46 1.323e+07 1.29e+07 -1 -1 20.29 0.875708 0.747308 37674 265803 -1 14265 15 7589 28006 2741318 395062 17.6852 nan -291.991 -17.6852 0 0 -1 -1 0.06 0.63 0.10 -1 -1 0.06 0.0994468 0.0886171 +k4_n4_v7_l1_bidir.xml bigkey.blif common 27.07 vpr 72.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 495 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74276 229 197 2152 2349 1 1362 921 29 29 841 io auto 32.6 MiB 0.19 35109 13408 448821 146189 291712 10920 72.5 MiB 1.54 0.02 28.5192 11.8335 -2618.05 -11.8335 11.8335 0.54 0.00381705 0.00331139 0.415039 0.360706 -1 -1 -1 -1 12 13371 38 2.187e+07 1.485e+07 -1 -1 22.31 1.32942 1.14348 39906 235943 -1 12329 17 6865 26060 1290857 258844 11.6984 11.6984 -2776.31 -11.6984 0 0 -1 -1 0.06 0.54 0.09 -1 -1 0.06 0.172038 0.151618 +k4_n4_v7_l1_bidir.xml clma.blif common 278.12 vpr 238.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2657 62 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 243764 62 82 8460 8542 1 6311 2801 54 54 2916 clb auto 83.5 MiB 1.37 318304 106218 1996137 787385 1191682 17070 225.3 MiB 12.34 0.12 180.571 44.0646 -2121.09 -44.0646 44.0646 2.25 0.0221159 0.0166099 2.32684 1.77283 -1 -1 -1 -1 29 111883 49 8.112e+07 7.971e+07 -1 -1 248.93 9.52343 7.40398 263120 1955672 -1 101313 14 37365 145032 12692939 2064304 42.322 42.322 -2255.16 -42.322 0 0 -1 -1 0.53 3.98 0.79 -1 -1 0.53 0.790771 0.664853 +k4_n4_v7_l1_bidir.xml des.blif common 27.55 vpr 85.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 476 256 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87980 256 245 1847 2092 0 1369 977 34 34 1156 io auto 30.7 MiB 0.22 41834 16291 427425 141277 269635 16513 85.9 MiB 1.40 0.02 55.6616 18.2554 -3058.48 -18.2554 nan 0.79 0.00414944 0.00361335 0.389896 0.341364 -1 -1 -1 -1 12 17178 44 3.072e+07 1.428e+07 -1 -1 22.06 1.59014 1.39836 55296 328128 -1 15463 15 7660 27882 2152148 416875 17.1404 nan -3056.03 -17.1404 0 0 -1 -1 0.08 0.59 0.13 -1 -1 0.08 0.154021 0.14055 +k4_n4_v7_l1_bidir.xml diffeq.blif common 10.69 vpr 70.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71700 64 39 1935 1974 1 1075 541 23 23 529 clb auto 29.9 MiB 0.19 23859 10034 152548 43059 105955 3534 70.0 MiB 0.77 0.01 60.266 12.6666 -3104.5 -12.6666 12.6666 0.32 0.00333395 0.00280831 0.247667 0.211717 -1 -1 -1 -1 15 10658 50 1.323e+07 1.314e+07 -1 -1 7.52 1.08277 0.918032 28434 179743 -1 9183 16 6138 22497 1257215 230883 12.6467 12.6467 -3223.39 -12.6467 0 0 -1 -1 0.04 0.42 0.06 -1 -1 0.04 0.130574 0.116547 +k4_n4_v7_l1_bidir.xml dsip.blif common 23.47 vpr 69.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 389 229 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71388 229 197 1815 2012 1 807 815 29 29 841 io auto 29.7 MiB 0.22 25997 11249 366095 122219 234437 9439 69.7 MiB 1.16 0.02 27.0132 11.1529 -2551.52 -11.1529 11.1529 0.54 0.00305654 0.00270038 0.30737 0.272816 -1 -1 -1 -1 12 11176 33 2.187e+07 1.167e+07 -1 -1 19.30 1.06061 0.935673 39906 235943 -1 10244 13 4283 22052 1030607 200941 10.8718 10.8718 -2615.29 -10.8718 0 0 -1 -1 0.05 0.36 0.09 -1 -1 0.05 0.102932 0.0931994 +k4_n4_v7_l1_bidir.xml elliptic.blif common 111.94 vpr 102.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105300 131 114 4855 4969 1 2121 1268 34 34 1156 clb auto 48.5 MiB 0.47 68213 32052 611808 216720 388087 7001 99.5 MiB 2.86 0.03 93.3266 25.0351 -15271.4 -25.0351 25.0351 0.77 0.00905634 0.00709113 0.855766 0.678841 -1 -1 -1 -1 24 35952 46 3.072e+07 3.069e+07 -1 -1 102.70 3.84755 3.092 89088 639360 -1 31624 16 11873 54886 5140312 855505 24.5872 24.5872 -16149.4 -24.5872 0 0 -1 -1 0.16 1.60 0.24 -1 -1 0.16 0.377302 0.320117 +k4_n4_v7_l1_bidir.xml ex1010.blif common 39.75 vpr 137.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1571 10 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 140920 10 10 4608 4618 0 3567 1591 42 42 1764 clb auto 53.4 MiB 0.67 147879 46435 790731 289845 498934 1952 136.5 MiB 4.98 0.05 83.3245 39.6079 -368.605 -39.6079 nan 1.34 0.00996113 0.00752524 0.973665 0.7587 -1 -1 -1 -1 21 49742 46 4.8e+07 4.713e+07 -1 -1 25.65 3.83175 3.05967 124480 868048 -1 45150 16 22456 89716 4688523 856199 39.8159 nan -369.076 -39.8159 0 0 -1 -1 0.22 1.87 0.43 -1 -1 0.22 0.398072 0.339422 +k4_n4_v7_l1_bidir.xml ex5p.blif common 18.19 vpr 65.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 8 63 1072 1135 0 892 433 22 22 484 clb auto 26.2 MiB 0.16 19665 12180 110112 32722 75037 2353 65.1 MiB 0.52 0.01 42.1132 17.967 -770.979 -17.967 nan 0.28 0.00181833 0.00162281 0.135232 0.122075 -1 -1 -1 -1 23 14643 39 1.2e+07 1.086e+07 -1 -1 15.45 0.747906 0.648695 34320 242040 -1 12274 18 7244 25344 2108210 336035 17.2355 nan -777.274 -17.2355 0 0 -1 -1 0.05 0.49 0.09 -1 -1 0.05 0.0896065 0.0794681 +k4_n4_v7_l1_bidir.xml frisc.blif common 91.55 vpr 110.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1093 20 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 112720 20 116 4445 4561 1 2268 1229 36 36 1296 clb auto 47.9 MiB 0.55 82225 38236 580269 205035 365670 9564 106.0 MiB 3.02 0.03 144.888 28.2628 -15971.6 -28.2628 28.2628 0.97 0.00860906 0.00685372 0.84973 0.678473 -1 -1 -1 -1 26 41144 35 3.468e+07 3.279e+07 -1 -1 81.45 3.93702 3.18952 104992 763300 -1 37445 17 13158 60126 5444826 978154 27.7261 27.7261 -16327.8 -27.7261 0 0 -1 -1 0.18 1.55 0.29 -1 -1 0.18 0.355507 0.299943 +k4_n4_v7_l1_bidir.xml misex3.blif common 25.17 vpr 67.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 456 14 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69212 14 14 1411 1425 0 1058 484 24 24 576 clb auto 28.1 MiB 0.23 25286 14202 129616 40562 86860 2194 67.6 MiB 0.81 0.01 43.4719 17.7771 -224.903 -17.7771 nan 0.34 0.00245431 0.00214229 0.229478 0.20207 -1 -1 -1 -1 22 16796 43 1.452e+07 1.368e+07 -1 -1 21.57 0.930568 0.795872 39160 271852 -1 14502 17 7277 28246 2125959 376090 17.9267 nan -234.908 -17.9267 0 0 -1 -1 0.06 0.57 0.10 -1 -1 0.06 0.111633 0.0985354 +k4_n4_v7_l1_bidir.xml pdc.blif common 116.26 vpr 159.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1617 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 163788 16 40 4591 4631 0 3619 1673 43 43 1849 clb auto 54.7 MiB 0.83 148382 72670 934811 358856 570141 5814 142.3 MiB 5.29 0.05 93.2356 33.3601 -1166.2 -33.3601 nan 1.32 0.0109056 0.00836527 1.08312 0.834952 -1 -1 -1 -1 36 80097 36 5.043e+07 4.851e+07 -1 -1 99.52 5.50726 4.31544 192618 1479219 -1 75456 17 26040 112622 12244803 1822486 32.6929 nan -1148.81 -32.6929 0 0 -1 -1 0.39 3.43 0.60 -1 -1 0.39 0.480142 0.402737 +k4_n4_v7_l1_bidir.xml s298.blif common 31.82 vpr 71.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 574 4 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73172 4 6 1942 1948 1 1159 584 26 26 676 clb auto 31.7 MiB 0.21 26193 13287 168944 51306 116401 1237 71.5 MiB 0.86 0.01 92.2741 24.9723 -196.835 -24.9723 24.9723 0.42 0.00370694 0.00304842 0.284114 0.236343 -1 -1 -1 -1 16 14492 41 1.728e+07 1.722e+07 -1 -1 27.66 1.50279 1.23825 36672 232432 -1 13188 18 8145 41698 2905801 417656 24.2999 24.2999 -196.112 -24.2999 0 0 -1 -1 0.05 0.83 0.09 -1 -1 0.05 0.170401 0.147693 +k4_n4_v7_l1_bidir.xml s38417.blif common 59.52 vpr 160.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1839 29 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 164724 29 106 7534 7640 1 4625 1974 45 45 2025 clb auto 67.7 MiB 0.80 182366 46669 1140750 409193 715103 16454 160.5 MiB 6.67 0.07 113.119 24.123 -13847.4 -24.123 24.123 1.47 0.0158586 0.0120293 1.55666 1.19069 -1 -1 -1 -1 16 43059 47 5.547e+07 5.517e+07 -1 -1 42.79 5.2201 4.09966 113090 722879 -1 40589 15 24470 82387 4406125 874310 22.9241 22.9241 -14764.6 -22.9241 0 0 -1 -1 0.19 1.91 0.31 -1 -1 0.19 0.638183 0.553447 +k4_n4_v7_l1_bidir.xml s38584.1.blif common 63.67 vpr 161.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1785 38 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 165740 38 304 7475 7779 1 4307 2127 45 45 2025 clb auto 67.0 MiB 0.78 169496 44382 1342081 511835 806220 24026 161.9 MiB 6.99 0.07 74.1051 20.5353 -13256.6 -20.5353 20.5353 1.52 0.015181 0.0115929 1.64152 1.2783 -1 -1 -1 -1 16 41197 48 5.547e+07 5.355e+07 -1 -1 47.15 4.91191 3.90833 113090 722879 -1 38058 15 20429 66024 3978003 769268 20.3296 20.3296 -14054.5 -20.3296 0 0 -1 -1 0.19 1.58 0.28 -1 -1 0.19 0.576043 0.5016 +k4_n4_v7_l1_bidir.xml seq.blif common 22.25 vpr 69.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 563 41 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71068 41 35 1791 1826 0 1358 639 26 26 676 clb auto 30.3 MiB 0.24 34655 18585 215217 68324 141286 5607 69.4 MiB 1.04 0.01 42.7606 19.0541 -549.348 -19.0541 nan 0.41 0.00343627 0.00285473 0.287666 0.242426 -1 -1 -1 -1 22 21579 50 1.728e+07 1.689e+07 -1 -1 17.99 1.11907 0.938823 46272 321488 -1 18864 15 8903 34453 2990664 524856 19.8932 nan -572.473 -19.8932 0 0 -1 -1 0.07 0.75 0.12 -1 -1 0.07 0.136318 0.119711 +k4_n4_v7_l1_bidir.xml spla.blif common 181.65 vpr 121.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1295 16 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 124260 16 46 3706 3752 0 2830 1357 38 38 1444 clb auto 47.2 MiB 0.59 104307 48793 654640 238193 412191 4256 116.5 MiB 3.91 0.04 84.8923 28.2789 -955.027 -28.2789 nan 1.02 0.00801147 0.00629725 0.881683 0.69524 -1 -1 -1 -1 30 56845 44 3.888e+07 3.885e+07 -1 -1 169.35 3.86298 3.0794 133344 1000208 -1 50796 19 19477 89020 8037289 1191085 27.773 nan -975.676 -27.773 0 0 -1 -1 0.25 2.48 0.40 -1 -1 0.25 0.407889 0.339434 +k4_n4_v7_l1_bidir.xml tseng.blif common 7.47 vpr 66.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67816 52 122 1483 1605 1 721 466 20 20 400 clb auto 27.0 MiB 0.13 14453 6257 117856 31965 81849 4042 66.2 MiB 0.49 0.01 44.0183 11.512 -2810.26 -11.512 11.512 0.23 0.00229118 0.00204192 0.160486 0.144029 -1 -1 -1 -1 14 6597 40 9.72e+06 8.76e+06 -1 -1 5.23 0.735414 0.639305 19872 120996 -1 5753 18 4097 15290 638053 131747 12.3091 12.3091 -3042.24 -12.3091 0 0 -1 -1 0.03 0.25 0.04 -1 -1 0.03 0.103918 0.0927701 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt index 6a59a733970..07c9b5a2f55 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.88 vpr 105.39 MiB -1 -1 6.79 63484 8 3.06 -1 -1 40704 -1 -1 250 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 107916 385 362 4415 4299 1 2365 1000 26 26 676 io auto 53.4 MiB 8.02 30064 545782 201861 320153 23768 96.5 MiB 5.36 0.06 9.17025 -9814.95 -9.17025 9.17025 0.75 0.0154429 0.0143793 1.79153 1.64504 -1 -1 -1 -1 86 44693 20 3.69863e+07 1.49655e+07 3.69198e+06 5461.52 13.35 6.72204 6.1687 89040 769342 -1 41511 17 9662 32287 1739041 311622 9.36868 9.36868 -10331.7 -9.36868 0 0 4.67059e+06 6909.16 0.16 1.11 0.68 -1 -1 0.16 0.681008 0.635643 - k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 15.44 vpr 81.45 MiB -1 -1 3.43 44504 3 1.23 -1 -1 39800 -1 -1 141 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83404 38 36 2739 2488 1 1022 215 17 17 289 clb auto 40.5 MiB 1.96 8926 42010 10393 28489 3128 81.4 MiB 0.91 0.01 10.0828 -2706.04 -10.0828 10.0828 0.30 0.00541664 0.00477131 0.391772 0.345384 -1 -1 -1 -1 62 13454 38 1.34605e+07 7.59905e+06 1.10657e+06 3828.96 3.45 1.77757 1.52314 31771 216973 -1 12449 21 4102 9497 328915 58876 10.8931 10.8931 -3012.43 -10.8931 0 0 1.37508e+06 4758.06 0.05 0.40 0.19 -1 -1 0.05 0.289893 0.256286 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.74 vpr 70.58 MiB -1 -1 17.86 45828 3 0.69 -1 -1 35540 -1 -1 48 196 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72272 196 193 1201 1346 1 606 438 15 15 225 io auto 31.2 MiB 0.83 3130 146694 39708 93961 13025 70.6 MiB 0.73 0.01 2.24601 -1081.12 -2.24601 2.24601 0.23 0.00356204 0.00332113 0.333364 0.31069 -1 -1 -1 -1 36 6058 29 1.03862e+07 3.13491e+06 520410. 2312.93 1.93 1.18409 1.08635 21110 102306 -1 5134 10 1618 2340 136007 39516 2.56471 2.56471 -1177.45 -2.56471 0 0 643451. 2859.78 0.02 0.14 0.09 -1 -1 0.02 0.102579 0.095844 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 22.86 vpr 83.41 MiB -1 -1 4.78 42380 3 0.69 -1 -1 37656 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85412 236 305 3199 3011 1 1520 677 19 19 361 io auto 42.5 MiB 2.99 12761 268067 88565 164726 14776 83.4 MiB 2.03 0.03 4.74988 -2887.79 -4.74988 4.74988 0.39 0.00859777 0.00794312 0.829104 0.763261 -1 -1 -1 -1 62 24213 37 1.72706e+07 9.87633e+06 1.42198e+06 3939.00 7.32 3.04293 2.76861 40483 281719 -1 20603 18 6062 15441 1381198 347776 4.88181 4.88181 -3127.07 -4.88181 0 0 1.76637e+06 4892.99 0.06 0.66 0.24 -1 -1 0.06 0.38505 0.357195 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 34.15 vpr 101.05 MiB -1 -1 3.84 61860 8 2.89 -1 -1 42304 -1 -1 247 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 103472 385 362 4415 4299 1 2357 997 26 26 676 io auto 57.1 MiB 5.19 60299 29833 558533 214306 321077 23150 97.4 MiB 4.02 0.05 12.9571 9.08653 -9982.73 -9.08653 9.08653 0.60 0.0122951 0.0115891 1.40221 1.25508 -1 -1 -1 -1 86 44651 39 3.69863e+07 1.48038e+07 3.69198e+06 5461.52 12.13 5.63808 5.09536 89040 769342 -1 41400 21 10076 33666 1743244 311635 9.30121 9.30121 -10341.1 -9.30121 0 0 4.67059e+06 6909.16 0.15 0.96 0.52 -1 -1 0.15 0.591543 0.547933 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 9.26 vpr 83.89 MiB -1 -1 1.74 44312 3 1.07 -1 -1 39956 -1 -1 139 38 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85904 38 36 2739 2488 1 1049 213 16 16 256 clb auto 43.6 MiB 1.17 14059 8662 34503 7871 24229 2403 83.9 MiB 0.49 0.01 11.7745 10.1195 -2670 -10.1195 10.1195 0.19 0.0035954 0.00320083 0.224754 0.197673 -1 -1 -1 -1 62 12786 36 1.21132e+07 7.49127e+06 968026. 3781.35 2.14 1.16173 1.01486 28084 189262 -1 11901 21 4007 8912 293191 53923 10.7115 10.7115 -2827.56 -10.7115 0 0 1.20332e+06 4700.46 0.03 0.27 0.11 -1 -1 0.03 0.207459 0.188642 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 14.77 vpr 71.92 MiB -1 -1 9.79 45204 3 0.61 -1 -1 35392 -1 -1 47 196 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73648 196 193 1201 1346 1 592 437 15 15 225 io auto 32.8 MiB 0.58 6911 3057 146253 37880 94608 13765 71.9 MiB 0.39 0.01 3.04383 2.21331 -1098.79 -2.21331 2.21331 0.19 0.00181143 0.00167906 0.171476 0.158363 -1 -1 -1 -1 38 5820 21 1.03862e+07 3.08102e+06 544116. 2418.30 1.62 0.679631 0.627147 21558 109668 -1 4978 10 1591 2448 151620 45926 2.57055 2.57055 -1194.35 -2.57055 0 0 690508. 3068.92 0.02 0.09 0.06 -1 -1 0.02 0.0694194 0.066214 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 15.04 vpr 84.71 MiB -1 -1 2.58 42840 3 0.56 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86744 236 305 3199 3011 1 1523 675 19 19 361 io auto 45.6 MiB 1.97 25195 12600 275862 99499 162512 13851 84.7 MiB 1.30 0.02 6.75568 4.64882 -2837.55 -4.64882 4.64882 0.29 0.00513714 0.00475976 0.519055 0.470381 -1 -1 -1 -1 62 23840 49 1.72706e+07 9.76854e+06 1.42198e+06 3939.00 5.43 1.97221 1.78662 40483 281719 -1 20436 15 5933 14959 1286779 322599 4.8554 4.8554 -3009.05 -4.8554 0 0 1.76637e+06 4892.99 0.06 0.45 0.17 -1 -1 0.06 0.248103 0.234994 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt index 4719bdbbc41..743e4766b3c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt @@ -1,15 +1,15 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 86.33 parmys 237.66 MiB -1 -1 59.56 243368 18 8.03 -1 -1 47792 -1 -1 690 257 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 131604 257 32 6023 6055 1 5218 979 30 30 900 clb auto 50.4 MiB 1.32 30778 384840 112160 259942 12738 128.5 MiB 5.07 0.06 6.21971 -2685.64 -6.21971 6.21971 0.00 0.0121286 0.010889 1.07079 0.930807 -1 -1 -1 -1 48326 9.26495 23261 4.45955 24183 85231 10762077 2437584 4.97244e+06 2.691e+06 9.69309e+06 10770.1 19 207906 1928213 -1 6.7296 6.7296 -2945.08 -6.7296 0 0 3.08 -1 -1 128.5 MiB 2.73 1.64504 1.43517 128.5 MiB -1 1.06 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 69.59 parmys 308.92 MiB -1 -1 20.53 316332 11 11.34 -1 -1 60732 -1 -1 1320 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 232392 36 100 10357 10457 1 9801 1456 41 41 1681 clb auto 78.0 MiB 1.62 84812 768613 262427 482842 23344 226.9 MiB 14.06 0.14 4.39308 -1711.02 -4.39308 4.39308 0.01 0.022016 0.0196054 2.33652 1.96707 -1 -1 -1 -1 138657 14.2256 61058 6.26429 47871 161906 24294871 4760787 8.95136e+06 5.148e+06 1.84779e+07 10992.2 18 392750 3677203 -1 4.59418 4.59418 -1851.22 -4.59418 0 0 6.19 -1 -1 226.9 MiB 6.17 3.45481 2.92361 226.9 MiB -1 2.09 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 20.54 vpr 65.45 MiB -1 -1 16.87 31768 7 0.22 -1 -1 34408 -1 -1 84 195 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67016 195 193 1168 1361 1 833 473 15 15 225 io memory auto 25.1 MiB 0.15 4149 116519 30489 77528 8502 65.4 MiB 0.67 0.01 2.05786 -845.694 -2.05786 2.05786 0.00 0.00358265 0.00334889 0.236637 0.220258 -1 -1 -1 -1 5820 7.04600 2934 3.55206 2158 7108 836065 203922 1.16234e+06 410348 2.18283e+06 9701.45 17 48952 428016 -1 2.20416 2.20416 -941.195 -2.20416 -5.04525 -0.362152 0.68 -1 -1 65.4 MiB 0.28 0.370687 0.343567 65.4 MiB -1 0.15 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU8PEEng.v common 274.74 vpr 777.04 MiB -1 -1 83.07 347172 198 58.46 -1 -1 81260 -1 -1 3007 114 84 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 795688 114 102 27514 27424 1 24905 3315 86 86 7396 memory auto 170.7 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/home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1554604 149 182 51692 43978 1 42908 5018 122 122 14884 mult_36 auto 292.6 MiB 7.71 2 610555 5286884 2218097 3004477 64310 1518.2 MiB 128.70 1.06 42.5031 13.5262 -39704.8 -13.5262 13.5262 0.05 0.0867315 0.0793853 13.2576 11.1988 -1 -1 -1 -1 736583 17.2195 289148 6.75958 207127 529507 77274312 17716707 8.48203e+07 3.88464e+07 1.71497e+08 11522.2 20 3576636 34359014 -1 13.9421 13.9421 -49958.2 -13.9421 0 0 27.45 -1 -1 1518.2 MiB 22.37 18.6002 15.864 1518.2 MiB -1 24.75 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU32PEEng.v common 1564.74 vpr 2.85 GiB -1 -1 169.71 1005424 199 648.07 -1 -1 240660 -1 -1 10127 114 300 32 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2990168 114 102 92654 91988 1 84766 10675 169 169 28561 memory auto 603.0 MiB 16.94 6 1169551 14931524 6314811 8578405 38308 2920.1 MiB 540.32 3.31 183.298 68.4997 -205073 -68.4997 68.4997 0.13 0.224889 0.199606 35.6755 28.4271 -1 -1 -1 -1 1429089 16.8680 637842 7.52865 260993 905980 118710487 27205397 1.64515e+08 6.81223e+07 3.31299e+08 11599.7 23 6883162 66233393 -1 73.0461 73.0461 -408864 -73.0461 -158.391 -0.303936 52.19 -1 -1 2920.1 MiB 45.14 49.5464 39.7886 2920.1 MiB -1 52.32 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mcml.v common 4798.35 vpr 2.99 GiB -1 -1 482.74 1402976 107 3634.95 -1 -1 347088 -1 -1 11481 36 318 27 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 3130736 36 356 138376 137161 1 92319 12218 169 169 28561 memory auto 782.0 MiB 15.53 6 1160463 19704338 8803888 10822718 77732 3057.4 MiB 468.78 2.85 140.602 55.2965 -212224 -55.2965 55.2965 0.09 0.202736 0.179676 33.0622 27.398 -1 -1 -1 -1 1073968 11.6336 502193 5.43993 312182 1239709 147666283 34765349 1.64515e+08 7.43047e+07 3.31299e+08 11599.7 22 6883162 66233393 -1 58.2368 58.2368 -298549 -58.2368 -0.797149 -0.124294 52.65 -1 -1 3057.4 MiB 45.35 44.9196 37.5371 3057.4 MiB -1 47.98 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt index 5fc9ae47bce..52cfffff857 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt @@ -1,22 +1,22 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 237.52 vpr 262.28 MiB -1 -1 32.91 121376 20 45.70 -1 -1 67188 -1 -1 857 133 25 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 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3041 63 63 3969 clb auto 300.2 MiB 92.25 247801 2183219 784650 1370393 28176 712.5 MiB 71.53 0.62 19.785 -25840.1 -19.785 19.785 16.56 0.102779 0.0918008 11.5762 9.76479 -1 -1 -1 -1 72 386360 42 2.36641e+08 1.52081e+08 1.98694e+07 5006.15 110.59 42.9221 35.5891 498330 4113940 -1 362013 19 91449 417245 17088983 2690880 20.0733 20.0733 -26346.1 -20.0733 0 0 2.48734e+07 6266.93 1.16 11.31 3.82 -1 -1 1.16 5.98384 5.18194 - k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 81.79 parmys 261.76 MiB -1 -1 16.25 268040 5 3.83 -1 -1 54936 -1 -1 499 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 144920 36 100 10178 7632 1 2726 635 29 29 841 clb auto 89.3 MiB 20.95 42663 237971 70464 152269 15238 136.4 MiB 5.32 0.05 14.7669 -2473.22 -14.7669 14.7669 0.97 0.0211143 0.0190909 2.35792 2.11102 -1 -1 -1 -1 70 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0.098196 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.63 vpr 65.72 MiB -1 -1 0.47 18896 3 0.09 -1 -1 33312 -1 -1 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67300 99 130 344 474 1 227 298 12 12 144 clb auto 26.5 MiB 0.17 749 71938 22933 33485 15520 65.7 MiB 0.13 0.00 1.86413 -118.59 -1.86413 1.86413 0.10 0.000549638 0.000516276 0.0433027 0.040723 -1 -1 -1 -1 42 1520 10 5.66058e+06 4.21279e+06 345696. 2400.67 0.59 0.187247 0.170993 13090 66981 -1 1349 11 399 648 28156 8528 2.01841 2.01841 -138.411 -2.01841 0 0 434636. 3018.30 0.01 0.05 0.06 -1 -1 0.01 0.0359727 0.0332907 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 9.83 vpr 68.52 MiB -1 -1 0.57 22264 5 0.15 -1 -1 34252 -1 -1 32 162 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70164 162 96 1075 892 1 665 295 16 16 256 mult_36 auto 29.5 MiB 0.47 5186 94471 34661 52400 7410 68.5 MiB 0.71 0.01 15.8635 -1239.63 -15.8635 15.8635 0.26 0.00331121 0.00311453 0.328384 0.30882 -1 -1 -1 -1 58 10489 28 1.21132e+07 3.70461e+06 904541. 3533.36 5.64 1.61544 1.48773 27572 180683 -1 8500 19 2932 4812 741239 227046 17.067 17.067 -1349.92 -17.067 0 0 1.15318e+06 4504.63 0.04 0.31 0.16 -1 -1 0.04 0.144606 0.134419 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 11.47 vpr 67.82 MiB -1 -1 0.42 21216 5 0.11 -1 -1 33532 -1 -1 21 66 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69452 66 96 778 595 1 467 188 16 16 256 mult_36 auto 28.2 MiB 0.61 3552 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k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 24.37 vpr 81.55 MiB -1 -1 6.55 53024 5 1.65 -1 -1 39496 -1 -1 170 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83508 193 205 2718 2652 1 1367 573 20 20 400 memory auto 40.7 MiB 3.02 11072 243231 85018 132684 25529 81.6 MiB 2.05 0.03 5.05891 -2813.63 -5.05891 5.05891 0.43 0.00798011 0.00703653 0.846187 0.756249 -1 -1 -1 -1 52 19118 33 2.07112e+07 1.1902e+07 1.31074e+06 3276.84 6.44 2.84139 2.53272 42580 268535 -1 16450 14 4598 11278 570237 127961 5.38192 5.38192 -3001.18 -5.38192 0 0 1.72518e+06 4312.96 0.06 0.45 0.23 -1 -1 0.06 0.306487 0.281362 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 66.97 vpr 107.66 MiB -1 -1 6.90 62616 8 3.11 -1 -1 40568 -1 -1 250 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 110248 385 362 4415 4299 1 2365 1000 26 26 676 io auto 52.9 MiB 8.14 30064 545782 201861 320153 23768 96.4 MiB 5.58 0.07 9.17025 -9814.95 -9.17025 9.17025 0.80 0.0163028 0.0152115 1.90499 1.74695 -1 -1 -1 -1 86 44693 20 3.69863e+07 1.49655e+07 3.69198e+06 5461.52 35.19 9.11242 8.32756 89040 769342 -1 41511 17 9662 32287 1739041 311622 9.36868 9.36868 -10331.7 -9.36868 0 0 4.67059e+06 6909.16 0.18 1.17 0.69 -1 -1 0.18 0.716853 0.668029 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 22.37 vpr 83.04 MiB -1 -1 4.90 42944 3 0.55 -1 -1 37604 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85036 236 305 3199 3011 1 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7.59905e+06 1.03370e+06 3576.80 5.06 2.06621 1.78557 31195 207102 -1 12451 20 4121 9643 348072 63845 10.9297 10.9297 -2988.87 -10.9297 0 0 1.31783e+06 4559.95 0.04 0.45 0.18 -1 -1 0.04 0.311517 0.277211 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 15.04 vpr 72.55 MiB -1 -1 3.93 32244 16 0.46 -1 -1 34912 -1 -1 60 45 3 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74296 45 32 1192 1151 1 782 141 14 14 196 memory auto 33.0 MiB 2.61 6900 30885 8865 18758 3262 72.6 MiB 0.66 0.01 10.7041 -7102.05 -10.7041 10.7041 0.20 0.00375059 0.00334308 0.345865 0.307399 -1 -1 -1 -1 60 13080 27 9.20055e+06 5.27364e+06 710723. 3626.14 4.65 1.49178 1.29898 21456 140545 -1 11406 14 3518 9267 727533 186037 11.4629 11.4629 -7580.27 -11.4629 0 0 894373. 4563.13 0.03 0.32 0.13 -1 -1 0.03 0.15979 0.145282 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 80.41 vpr 230.75 MiB -1 -1 14.04 99996 5 7.02 -1 -1 66224 -1 -1 721 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 236292 169 197 23225 21365 1 6061 1087 34 34 1156 clb auto 145.3 MiB 11.54 37017 593203 196123 370826 26254 203.3 MiB 8.12 0.08 3.50768 -13965.8 -3.50768 3.50768 1.39 0.0314237 0.026993 3.68019 3.10409 -1 -1 -1 -1 46 58126 45 6.50233e+07 3.88578e+07 3.64223e+06 3150.72 21.83 13.775 11.4226 123264 752332 -1 51405 13 15223 24254 807106 167773 3.87082 3.87082 -15222.1 -3.87082 0 0 4.69209e+06 4058.90 0.20 1.57 0.63 -1 -1 0.20 1.51477 1.34949 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 144.19 vpr 269.33 MiB -1 -1 12.21 122580 3 10.12 -1 -1 74072 -1 -1 768 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 275792 115 145 22864 19301 1 9609 1068 40 40 1600 mult_36 auto 143.1 MiB 11.43 79476 584967 186467 369840 28660 213.0 MiB 10.55 0.11 5.41341 -23480.4 -5.41341 5.41341 2.17 0.0319079 0.0275548 3.94511 3.37191 -1 -1 -1 -1 78 126298 33 9.16046e+07 5.72315e+07 8.23220e+06 5145.12 76.60 16.9981 14.2428 204032 1723206 -1 115064 14 29800 47012 6851687 1564903 5.46393 5.46393 -25542.6 -5.46393 0 0 1.04203e+07 6512.68 0.43 3.13 1.54 -1 -1 0.43 1.68782 1.49543 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 305.89 vpr 1.03 GiB -1 -1 16.73 194960 3 6.23 -1 -1 152176 -1 -1 1699 149 0 179 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1075592 149 182 55415 37074 1 28414 2209 80 80 6400 mult_36 auto 293.3 MiB 30.70 276200 2001029 706104 1220084 74841 1050.4 MiB 59.88 0.40 12.9413 -50214.8 -12.9413 12.9413 28.80 0.0899255 0.0755434 13.3433 11.2726 -1 -1 -1 -1 84 389613 48 3.90281e+08 1.62448e+08 3.63717e+07 5683.08 105.23 42.721 36.1082 857088 7768622 -1 366997 20 100923 120240 14759319 3128518 13.8463 13.8463 -54794.6 -13.8463 0 0 4.62462e+07 7225.96 2.39 8.04 7.35 -1 -1 2.39 4.60189 4.03624 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.86 vpr 65.79 MiB -1 -1 0.98 23176 4 0.13 -1 -1 32552 -1 -1 15 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67372 11 2 303 283 2 78 28 7 7 49 clb auto 26.2 MiB 0.22 262 1078 238 765 75 65.8 MiB 0.04 0.00 2.0391 -163.079 -2.0391 1.90116 0.04 0.00079628 0.000729774 0.0247413 0.0227926 -1 -1 -1 -1 28 333 12 1.07788e+06 808410 72669.7 1483.05 0.17 0.112952 0.0979406 3564 12808 -1 288 8 200 345 4799 1871 2.11979 1.94261 -165.174 -2.11979 0 0 87745.0 1790.71 0.00 0.03 0.01 -1 -1 0.00 0.022123 0.0200623 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 497.88 vpr 611.74 MiB -1 -1 77.76 452540 97 80.96 -1 -1 112748 -1 -1 2151 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 626424 114 102 35834 31925 1 16897 2420 56 56 3136 clb auto 279.1 MiB 70.81 224666 1805060 668533 1109456 27071 611.7 MiB 64.72 0.55 75.1122 -53345.7 -75.1122 75.1122 13.40 0.101362 0.0900982 12.5616 10.6146 -1 -1 -1 -1 88 335261 49 1.8697e+08 1.43756e+08 1.84122e+07 5871.24 134.02 47.1194 39.1334 423474 3861999 -1 307396 22 65997 258491 13780558 2468289 76.0017 76.0017 -64554.6 -76.0017 0 0 2.30976e+07 7365.31 1.10 10.19 3.64 -1 -1 1.10 6.17356 5.28565 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 2692.08 vpr 2.42 GiB -1 -1 242.89 1496112 97 858.98 -1 -1 355104 -1 -1 7513 114 168 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2535652 114 102 120350 108159 1 57345 7929 103 103 10609 clb auto 892.1 MiB 262.75 1003045 9728742 4018902 5663791 46049 2004.2 MiB 480.49 3.14 72.4024 -329114 -72.4024 72.4024 47.02 0.346214 0.301919 48.3359 40.4685 -1 -1 -1 -1 124 1323068 31 6.46441e+08 5.09602e+08 8.61045e+07 8116.18 587.22 199.076 163.111 1699828 18865638 -1 1270470 22 208280 903882 50603811 8413337 73.1548 73.1548 -457667 -73.1548 0 0 1.09063e+08 10280.2 5.97 39.87 20.11 -1 -1 5.97 22.9615 19.528 - k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5532.81 vpr 2.11 GiB -1 -1 301.74 1243688 25 2880.43 -1 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v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 248896 133 179 14228 14085 1 7100 1192 37 37 1369 clb auto 137.3 MiB 29.37 266135 116292 607624 202148 389460 16016 197.5 MiB 11.96 0.11 36.2085 22.0917 -209321 -22.0917 22.0917 1.30 0.0362607 0.0326055 4.24626 3.52876 -1 -1 -1 -1 98 183926 48 7.54166e+07 5.97803e+07 8.55474e+06 6248.90 115.49 17.5043 14.4482 190708 1812325 -1 160975 15 32365 127542 9954229 1823700 23.0474 23.0474 -216590 -23.0474 0 0 1.08529e+07 7927.61 0.42 3.70 1.34 -1 -1 0.42 1.8165 1.60589 +k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 395.52 vpr 711.73 MiB -1 -1 46.70 618468 14 73.53 -1 -1 121516 -1 -1 2726 257 0 11 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute 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27.6725 14.8675 -2411.82 -14.8675 14.8675 0.78 0.0177993 0.0163606 1.88812 1.64858 -1 -1 -1 -1 70 67015 21 4.4999e+07 2.66775e+07 3.87716e+06 4610.18 15.46 5.57727 4.81634 101140 791177 -1 62172 16 12850 65502 2552081 382161 15.0937 15.0937 -2598.2 -15.0937 0 0 4.87732e+06 5799.43 0.26 1.50 0.74 -1 -1 0.26 0.958764 0.852505 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 16.43 vpr 71.90 MiB -1 -1 10.97 44964 3 0.60 -1 -1 35988 -1 -1 47 196 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73624 196 193 1201 1346 1 592 437 15 15 225 io auto 33.2 MiB 0.53 6911 3057 146253 37880 94608 13765 71.9 MiB 0.66 0.01 3.04383 2.21331 -1098.79 -2.21331 2.21331 0.27 0.00361775 0.00339713 0.322435 0.299654 -1 -1 -1 -1 38 5820 21 1.03862e+07 3.08102e+06 544116. 2418.30 1.87 0.930701 0.862606 21558 109668 -1 4978 10 1591 2448 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33800 -1 -1 32 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72196 162 96 1075 892 1 666 295 16 16 256 mult_36 auto 30.9 MiB 0.48 8583 5421 87604 32328 48998 6278 70.5 MiB 0.52 0.01 17.0345 15.9116 -1282.7 -15.9116 15.9116 0.35 0.00161197 0.00150016 0.239728 0.223735 -1 -1 -1 -1 56 11035 40 1.21132e+07 3.70461e+06 870502. 3400.40 4.56 0.816605 0.758167 27064 172478 -1 9127 22 3456 5983 1005760 304802 17.1604 17.1604 -1414.2 -17.1604 0 0 1.11200e+06 4343.75 0.03 0.27 0.11 -1 -1 0.03 0.101075 0.0953089 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 9.29 vpr 68.90 MiB -1 -1 0.31 21540 5 0.14 -1 -1 33800 -1 -1 21 66 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70552 66 96 778 595 1 468 188 16 16 256 mult_36 auto 29.8 MiB 0.57 6929 3851 46456 15752 25638 5066 68.9 MiB 0.28 0.00 13.1599 11.7559 -749.569 -11.7559 11.7559 0.33 0.0011598 0.00108633 0.134145 0.126067 -1 -1 -1 -1 42 9288 42 1.21132e+07 3.11177e+06 666202. 2602.35 6.12 0.737694 0.68405 24768 131944 -1 7591 22 3377 6818 1297563 374051 12.9969 12.9969 -873.1 -12.9969 0 0 835786. 3264.79 0.03 0.28 0.08 -1 -1 0.03 0.0745914 0.0703876 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 50.48 vpr 316.59 MiB -1 -1 11.09 116552 5 3.66 -1 -1 44796 -1 -1 468 506 44 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 324192 506 553 3236 3734 1 2870 1571 50 50 2500 memory auto 57.5 MiB 3.70 42225 16423 1151825 559617 409148 183060 316.6 MiB 3.18 0.04 9.60271 7.54011 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8 2.83 -1 -1 41916 -1 -1 247 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 103224 385 362 4415 4299 1 2357 997 26 26 676 io auto 57.2 MiB 5.42 60299 29833 558533 214306 321077 23150 97.5 MiB 4.08 0.05 12.9571 9.08653 -9982.73 -9.08653 9.08653 0.62 0.0118283 0.0111006 1.51022 1.3448 -1 -1 -1 -1 86 44651 39 3.69863e+07 1.48038e+07 3.69198e+06 5461.52 12.41 5.80252 5.20681 89040 769342 -1 41400 21 10076 33666 1743244 311635 9.30121 9.30121 -10341.1 -9.30121 0 0 4.67059e+06 6909.16 0.16 0.99 0.79 -1 -1 0.16 0.617813 0.571762 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 15.37 vpr 84.48 MiB -1 -1 2.70 42844 3 0.56 -1 -1 36996 -1 -1 127 236 1 6 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86512 236 305 3199 3011 1 1523 675 19 19 361 io auto 45.5 MiB 1.98 25195 12600 275862 99499 162512 13851 84.5 MiB 1.35 0.02 6.75568 4.64882 -2837.55 -4.64882 4.64882 0.31 0.00549613 0.00510822 0.566275 0.514224 -1 -1 -1 -1 62 23840 49 1.72706e+07 9.76854e+06 1.42198e+06 3939.00 5.85 2.24814 2.0487 40483 281719 -1 20436 15 5933 14959 1286779 322599 4.8554 4.8554 -3009.05 -4.8554 0 0 1.76637e+06 4892.99 0.06 0.47 0.17 -1 -1 0.06 0.250698 0.237004 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 9.91 vpr 83.59 MiB -1 -1 2.10 44688 3 1.07 -1 -1 39952 -1 -1 139 38 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85596 38 36 2739 2488 1 1049 213 16 16 256 clb auto 43.3 MiB 1.18 14059 8662 34503 7871 24229 2403 83.6 MiB 0.52 0.01 11.7745 10.1195 -2670 -10.1195 10.1195 0.19 0.00383665 0.00344661 0.246909 0.216894 -1 -1 -1 -1 58 13567 49 1.21132e+07 7.49127e+06 904541. 3533.36 2.69 1.35061 1.18242 27572 180683 -1 12180 19 4139 9511 324475 59593 10.8291 10.8291 -2841.73 -10.8291 0 0 1.15318e+06 4504.63 0.04 0.30 0.11 -1 -1 0.04 0.222745 0.202612 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 16.93 vpr 73.76 MiB -1 -1 1.98 32292 16 0.59 -1 -1 34884 -1 -1 61 45 3 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75528 45 32 1192 1151 1 792 142 14 14 196 memory auto 35.0 MiB 2.68 10043 6565 23822 6254 15540 2028 73.8 MiB 0.59 0.01 13.3138 11.239 -7207.5 -11.239 11.239 0.24 0.00448329 0.00410023 0.332932 0.298965 -1 -1 -1 -1 64 12481 30 9.20055e+06 5.32753e+06 762053. 3888.03 8.48 2.38399 2.14556 22040 150681 -1 10537 14 3342 8767 663858 168108 11.6206 11.6206 -7527.99 -11.6206 0 0 953435. 4864.47 0.04 0.35 0.18 -1 -1 0.04 0.188032 0.175235 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 69.35 vpr 236.99 MiB -1 -1 10.22 98344 5 11.48 -1 -1 65608 -1 -1 723 169 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 242676 169 197 23225 21365 1 6048 1089 34 34 1156 clb auto 158.7 MiB 7.61 135279 37585 577889 189065 363964 24860 205.9 MiB 7.38 0.09 6.79679 3.48144 -13874.2 -3.48144 3.48144 1.20 0.0367946 0.0320323 3.53071 2.995 -1 -1 -1 -1 46 59522 44 6.50233e+07 3.89656e+07 3.64223e+06 3150.72 18.71 11.9208 10.1086 123264 752332 -1 52482 14 15977 25751 857559 179259 3.70894 3.70894 -15069.9 -3.70894 0 0 4.69209e+06 4058.90 0.20 1.32 0.74 -1 -1 0.20 1.26195 1.14674 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 107.97 vpr 304.24 MiB -1 -1 10.05 121396 3 10.65 -1 -1 73876 -1 -1 761 115 0 40 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 311540 115 145 22864 19301 1 9598 1061 40 40 1600 mult_36 auto 157.2 MiB 7.70 216707 80047 579824 190762 365771 23291 228.1 MiB 8.16 0.08 7.82034 5.55779 -23040.2 -5.55779 5.55779 2.29 0.0215767 0.0190627 3.0521 2.59567 -1 -1 -1 -1 82 124601 48 9.16046e+07 5.68542e+07 8.58295e+06 5364.35 54.09 17.337 14.8874 207228 1787768 -1 113911 14 29248 44540 5876852 1327853 5.72835 5.72835 -25879.2 -5.72835 0 0 1.07702e+07 6731.38 0.48 2.39 1.35 -1 -1 0.48 1.37334 1.26744 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 273.92 vpr 939.73 MiB -1 -1 13.85 194876 3 5.84 -1 -1 151880 -1 -1 1693 149 0 179 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 962288 149 182 55415 37074 1 28410 2203 80 80 6400 mult_36 auto 318.0 MiB 25.88 1 279853 2022451 708543 1241399 72509 939.7 MiB 46.68 0.31 27.175 13.8922 -50923.4 -13.8922 13.8922 30.81 0.0656328 0.0591708 10.1964 8.76379 -1 -1 -1 -1 84 384146 39 3.90281e+08 1.62125e+08 3.63717e+07 5683.08 102.27 44.1695 37.9463 857088 7768622 -1 367849 21 98815 117998 14005042 3008515 14.8174 14.8174 -56086.4 -14.8174 0 0 4.62462e+07 7225.96 2.53 7.16 5.76 -1 -1 2.53 4.08161 3.62281 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.16 vpr 66.80 MiB -1 -1 0.44 22692 4 0.11 -1 -1 33008 -1 -1 15 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68408 11 2 303 283 2 85 28 7 7 49 clb auto 27.5 MiB 0.20 462 294 1372 325 946 101 66.8 MiB 0.04 0.00 2.20626 2.0391 -157.497 -2.0391 1.90116 0.04 0.000720929 0.000639654 0.0290609 0.0262716 -1 -1 -1 -1 26 435 16 1.07788e+06 808410 68696.0 1401.96 0.33 0.197388 0.171083 3516 12294 -1 372 15 293 527 8455 3007 2.11125 1.89738 -161.275 -2.11125 0 0 84249.8 1719.38 0.00 0.04 0.01 -1 -1 0.00 0.0298989 0.0270866 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 455.11 vpr 590.73 MiB -1 -1 48.28 451352 97 86.37 -1 -1 110592 -1 -1 2144 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 604904 114 102 35834 31925 1 16899 2413 56 56 3136 clb auto 311.6 MiB 54.53 934215 218876 1830527 680211 1116146 34170 590.7 MiB 76.63 0.49 142.326 73.8063 -53329.6 -73.8063 73.8063 12.23 0.089699 0.0819079 14.4758 11.8124 -1 -1 -1 -1 86 331425 45 1.8697e+08 1.43379e+08 1.79819e+07 5734.03 137.97 42.5414 34.9669 420342 3799571 -1 301758 22 66654 261893 13479107 2432831 73.243 73.243 -66857.7 -73.243 0 0 2.27638e+07 7258.87 1.06 8.85 2.83 -1 -1 1.06 5.46509 4.6883 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 5085.56 vpr 2.00 GiB -1 -1 160.14 1452796 97 895.48 -1 -1 354436 -1 -1 7478 114 168 32 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2093276 114 102 120350 108159 1 57530 7894 102 102 10404 clb auto 1002.8 MiB 178.54 5 937620 9671512 3979219 5647220 45073 1897.7 MiB 498.57 2.88 186.365 72.9848 -317425 -72.9848 72.9848 40.28 0.354498 0.271431 49.7107 39.17 -1 -1 -1 -1 112 1263786 24 6.36957e+08 5.07716e+08 7.72010e+07 7420.32 3176.91 152.247 121.841 1584492 16730607 -1 1213440 21 216534 945339 50802610 8610369 74.2493 74.2493 -440401 -74.2493 0 0 9.78368e+07 9403.76 4.47 30.31 13.30 -1 -1 4.47 18.2361 15.3655 +k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 4271.47 vpr 2.07 GiB -1 -1 192.31 1212884 25 2963.89 -1 -1 367440 -1 -1 6759 36 159 27 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2170912 36 356 185159 159806 1 63407 7337 98 98 9604 clb auto 1175.9 MiB 160.15 4 726368 10055420 3866973 6000930 187517 2081.1 MiB 528.58 3.09 138.532 56.0715 -322739 -56.0715 56.0715 35.68 0.267313 0.237876 43.3544 35.7269 -1 -1 -1 -1 124 951238 25 5.9175e+08 4.62062e+08 7.79543e+07 8116.86 256.86 141.996 117.65 1542384 17086260 -1 922124 23 211344 490899 28645964 5116509 55.8407 55.8407 -362186 -55.8407 0 0 9.87684e+07 10284.1 4.81 23.81 14.26 -1 -1 4.81 17.1091 14.4811 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index cf218b6f42d..8d45c568ac5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,20 +1,20 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 220.60 vpr 258.80 MiB -1 -1 32.77 121676 20 41.63 -1 -1 67228 -1 -1 857 133 25 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 265012 133 179 14228 14085 1 7013 1194 37 37 1369 clb auto 123.2 MiB 52.98 117241 583646 194344 373759 15543 184.7 MiB 13.08 0.13 22.6552 -207062 -22.6552 22.6552 1.62 0.0407574 0.0356824 4.19626 3.54119 -1 -1 -1 -1 102 177496 34 7.54166e+07 5.98881e+07 8.84326e+06 6459.65 56.40 16.9397 14.0699 193444 1864326 -1 162723 14 31022 120994 9555365 1733447 24.3598 24.3598 -215921 -24.3598 0 0 1.10984e+07 8106.95 0.39 4.72 1.75 -1 -1 0.39 2.18738 1.88506 - k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 459.06 vpr 747.54 MiB -1 -1 66.92 634636 14 66.21 -1 -1 121812 -1 -1 2741 257 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 765484 257 32 36080 33722 1 19295 3041 63 63 3969 clb auto 299.9 MiB 91.07 246576 2183219 779788 1375542 27889 747.5 MiB 63.52 0.58 18.719 -25586.3 -18.719 18.719 16.30 0.0997124 0.0890543 11.1519 9.38394 -1 -1 -1 -1 70 390691 45 2.36641e+08 1.52081e+08 1.93981e+07 4887.41 92.61 39.2846 32.3608 494362 4028736 -1 366303 20 98427 446372 17944375 2776232 18.5784 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/home/elgamma8/research/release/vtr-verilog-to-routing 67316 99 130 344 474 1 227 298 12 12 144 clb auto 26.6 MiB 0.27 728 65968 18859 34313 12796 65.7 MiB 0.23 0.00 1.84343 -119.549 -1.84343 1.84343 0.14 0.00129356 0.00122501 0.0899037 0.0850148 -1 -1 -1 -1 38 1521 13 5.66058e+06 4.21279e+06 319126. 2216.15 1.20 0.526166 0.481346 12802 62767 -1 1190 8 347 541 19340 5772 2.02505 2.02505 -132.661 -2.02505 0 0 406307. 2821.58 0.01 0.04 0.06 -1 -1 0.01 0.0292785 0.0272629 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 17.74 vpr 68.76 MiB -1 -1 0.55 22212 5 0.17 -1 -1 34256 -1 -1 32 162 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70408 162 96 1075 892 1 665 295 16 16 256 mult_36 auto 29.5 MiB 0.46 5192 86623 30832 48552 7239 68.8 MiB 0.65 0.01 15.9204 -1248.52 -15.9204 15.9204 0.26 0.00323801 0.00305102 0.296153 0.278827 -1 -1 -1 -1 52 10572 36 1.21132e+07 3.70461e+06 805949. 3148.24 13.61 1.81362 1.666 26552 162987 -1 8855 19 3315 5650 841386 247320 17.1128 17.1128 -1334.38 -17.1128 0 0 1.06067e+06 4143.25 0.03 0.31 0.14 -1 -1 0.03 0.139605 0.129607 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 8.37 vpr 67.73 MiB -1 -1 0.43 21352 5 0.12 -1 -1 33516 -1 -1 21 66 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69356 66 96 778 595 1 467 188 16 16 256 mult_36 auto 28.1 MiB 0.60 3665 46994 16162 26226 4606 67.7 MiB 0.42 0.01 12.0063 -749.927 -12.0063 12.0063 0.26 0.00230616 0.00217938 0.211958 0.200407 -1 -1 -1 -1 66 8504 40 1.21132e+07 3.11177e+06 1035765. 4045.96 4.62 0.810993 0.747228 26044 153858 -1 7152 21 3778 7722 1367723 423082 13.0897 13.0897 -855.954 -13.0897 0 0 1.00276e+06 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44700 -1 -1 482 506 44 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 358112 506 553 3236 3734 1 2871 1585 50 50 2500 memory auto 52.0 MiB 6.68 15936 1193158 577376 425225 190557 349.7 MiB 5.83 0.07 7.10685 -2128.82 -7.10685 7.10685 10.04 0.0231676 0.0209658 3.091 2.77392 -1 -1 -1 -1 38 22888 13 1.47946e+08 5.00895e+07 6.86579e+06 2746.32 11.67 8.40888 7.63323 258216 1426232 -1 22075 13 4031 5658 1086587 273830 7.72559 7.72559 -2477.01 -7.72559 0 0 8.69102e+06 3476.41 0.39 1.00 1.29 -1 -1 0.39 0.799737 0.740311 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 15.42 vpr 80.04 MiB -1 -1 1.42 26020 2 0.13 -1 -1 34232 -1 -1 32 311 15 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81964 311 156 1015 1158 1 965 514 28 28 784 memory auto 31.4 MiB 0.84 8982 206314 76497 119197 10620 72.3 MiB 1.22 0.02 4.5269 -4391.67 -4.5269 4.5269 0.93 0.00579142 0.00513528 0.604532 0.536129 -1 -1 -1 -1 40 14593 15 4.25198e+07 9.94461e+06 2.13295e+06 2720.61 7.26 2.55624 2.26242 78662 432578 -1 13692 13 2679 3112 717136 216657 4.28969 4.28969 -5035.02 -4.28969 0 0 2.67004e+06 3405.67 0.10 0.36 0.37 -1 -1 0.10 0.216825 0.197387 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 39.85 vpr 81.62 MiB -1 -1 8.43 52680 5 1.64 -1 -1 39440 -1 -1 170 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83584 193 205 2718 2652 1 1367 573 20 20 400 memory auto 40.8 MiB 3.01 10921 238473 79955 132805 25713 81.6 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73824 45 32 1192 1151 1 782 141 14 14 196 memory auto 32.6 MiB 2.64 6823 26859 7335 15944 3580 72.1 MiB 0.56 0.01 10.958 -7233.76 -10.958 10.958 0.20 0.00348886 0.00309362 0.282542 0.250806 -1 -1 -1 -1 66 13449 49 9.20055e+06 5.27364e+06 787562. 4018.17 4.34 1.29546 1.12707 22236 154735 -1 10952 14 3335 8795 693161 168301 11.3764 11.3764 -7707.18 -11.3764 0 0 978561. 4992.66 0.03 0.31 0.14 -1 -1 0.03 0.156586 0.142149 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 70.08 vpr 230.16 MiB -1 -1 13.83 100176 5 5.66 -1 -1 66176 -1 -1 721 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 235688 169 197 23225 21365 1 6061 1087 34 34 1156 clb auto 145.2 MiB 11.37 38474 604375 204189 371506 28680 203.8 MiB 8.13 0.08 3.46077 -13892.2 -3.46077 3.46077 1.39 0.03105 0.0265371 3.68938 3.11547 -1 -1 -1 -1 48 59150 27 6.50233e+07 3.88578e+07 3.79520e+06 3283.05 12.78 10.4783 8.76719 124420 775892 -1 52898 13 15534 24900 864227 176456 3.4636 3.4636 -15245.2 -3.4636 0 0 4.86353e+06 4207.21 0.20 1.57 0.65 -1 -1 0.20 1.46742 1.31137 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 290.27 vpr 265.57 MiB -1 -1 11.65 122540 3 9.69 -1 -1 74020 -1 -1 768 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 271948 115 145 22864 19301 1 9609 1068 40 40 1600 mult_36 auto 142.9 MiB 11.46 77552 595881 196750 373726 25405 212.8 MiB 10.18 0.11 5.13349 -22954.5 -5.13349 5.13349 1.96 0.0315004 0.027208 3.80196 3.23508 -1 -1 -1 -1 76 129415 35 9.16046e+07 5.72315e+07 8.06023e+06 5037.64 224.38 20.2923 16.9388 200832 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k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.78 vpr 65.62 MiB -1 -1 0.94 23248 4 0.13 -1 -1 32564 -1 -1 15 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67192 11 2 303 283 2 78 28 7 7 49 clb auto 26.0 MiB 0.21 280 994 173 731 90 65.6 MiB 0.04 0.00 2.0401 -164.361 -2.0401 1.90163 0.03 0.000802622 0.000736286 0.0231253 0.0212941 -1 -1 -1 -1 22 397 12 1.07788e+06 808410 57331.5 1170.03 0.32 0.150968 0.128977 3372 10412 -1 355 11 172 254 4023 1475 2.14906 1.91429 -169.055 -2.14906 0 0 72669.7 1483.05 0.00 0.02 0.01 -1 -1 0.00 0.0172996 0.0159743 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io 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min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 212.47 vpr 279.51 MiB -1 -1 19.33 119976 20 47.22 -1 -1 68076 -1 -1 855 133 25 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 286220 133 179 14228 14085 1 7100 1192 37 37 1369 clb auto 135.8 MiB 30.67 264290 118331 588673 187049 381129 20495 196.5 MiB 10.93 0.10 32.7899 22.873 -208698 -22.873 22.873 1.43 0.0324797 0.0292432 3.84677 3.23963 -1 -1 -1 -1 110 176725 27 7.54166e+07 5.97803e+07 9.46577e+06 6914.37 87.45 21.2205 17.8322 201652 2027183 -1 162249 14 30432 117983 9007020 1696919 24.0504 24.0504 -216487 -24.0504 0 0 1.20852e+07 8827.75 0.45 3.53 1.54 -1 -1 0.45 1.77327 1.56805 +k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 482.62 vpr 710.52 MiB -1 -1 45.25 619668 14 76.05 -1 -1 122284 -1 -1 2726 257 0 11 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 727576 257 32 36080 33722 1 19365 3026 63 63 3969 clb auto 329.7 MiB 70.76 1 246198 2147070 770352 1350261 26457 710.5 MiB 79.70 0.59 60.4933 18.7554 -25815 -18.7554 18.7554 16.05 0.0947419 0.0860547 13.1929 10.7692 -1 -1 -1 -1 72 383970 26 2.36641e+08 1.51273e+08 1.98694e+07 5006.15 146.80 56.49 46.364 498330 4113940 -1 361584 22 95063 428737 17085321 2684393 19.1335 19.1335 -26346.5 -19.1335 0 0 2.48734e+07 6266.93 1.24 12.09 2.89 -1 -1 1.24 6.67177 5.73047 +k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 68.96 parmys 254.32 MiB -1 -1 10.19 260420 5 3.55 -1 -1 54908 -1 -1 495 36 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 143288 36 100 10178 7632 1 2724 631 29 29 841 clb auto 96.0 MiB 15.82 95360 41180 227851 69677 144196 13978 139.9 MiB 4.01 0.04 22.4661 14.8203 -2362.24 -14.8203 14.8203 0.86 0.0174468 0.0161202 1.90119 1.64273 -1 -1 -1 -1 68 66817 22 4.4999e+07 2.66775e+07 3.78783e+06 4503.96 24.80 6.79508 5.87269 99460 760244 -1 60459 14 12442 64371 2376927 356438 15.0178 15.0178 -2542.17 -15.0178 0 0 4.70015e+06 5588.76 0.18 1.64 0.67 -1 -1 0.18 0.999677 0.893759 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 15.71 vpr 71.91 MiB -1 -1 11.65 44576 3 0.60 -1 -1 35600 -1 -1 47 196 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73640 196 193 1201 1346 1 592 437 15 15 225 io auto 33.1 MiB 0.52 7097 3082 141282 36274 93188 11820 71.9 MiB 0.39 0.01 2.88013 2.23271 -1111.45 -2.23271 2.23271 0.17 0.00181996 0.00167433 0.170233 0.157242 -1 -1 -1 -1 38 6015 35 1.03862e+07 3.08102e+06 544116. 2418.30 0.99 0.562766 0.519528 21558 109668 -1 5038 10 1765 2614 165080 48924 2.65248 2.65248 -1216.21 -2.65248 0 0 690508. 3068.92 0.02 0.10 0.06 -1 -1 0.02 0.070957 0.0676966 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.27 vpr 66.99 MiB -1 -1 0.38 18464 3 0.07 -1 -1 33120 -1 -1 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68596 99 130 344 474 1 228 298 12 12 144 clb auto 28.3 MiB 0.16 1708 681 71938 21850 35232 14856 67.0 MiB 0.12 0.00 2.12112 1.86413 -119.258 -1.86413 1.86413 0.10 0.000566216 0.000530411 0.0447479 0.0419328 -1 -1 -1 -1 42 1388 10 5.66058e+06 4.21279e+06 345696. 2400.67 0.67 0.20809 0.190737 13090 66981 -1 1237 10 456 706 29446 8797 1.96058 1.96058 -139.503 -1.96058 0 0 434636. 3018.30 0.01 0.03 0.04 -1 -1 0.01 0.0198907 0.018763 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 6.34 vpr 70.60 MiB -1 -1 0.40 22304 5 0.21 -1 -1 33772 -1 -1 32 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72292 162 96 1075 892 1 666 295 16 16 256 mult_36 auto 31.3 MiB 0.47 8262 5112 85642 26726 51784 7132 70.6 MiB 0.61 0.01 16.5991 15.8982 -1286.15 -15.8982 15.8982 0.35 0.00310373 0.00289519 0.287074 0.267623 -1 -1 -1 -1 52 9636 23 1.21132e+07 3.70461e+06 805949. 3148.24 2.31 0.817068 0.760008 26552 162987 -1 8698 17 2587 4144 731400 221181 17.1356 17.1356 -1376.18 -17.1356 0 0 1.06067e+06 4143.25 0.04 0.37 0.15 -1 -1 0.04 0.174555 0.164858 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 18.31 vpr 68.98 MiB -1 -1 0.20 21540 5 0.09 -1 -1 33460 -1 -1 21 66 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70640 66 96 778 595 1 468 188 16 16 256 mult_36 auto 29.4 MiB 0.36 6204 3763 43766 14011 25945 3810 69.0 MiB 0.21 0.00 13.1588 11.8959 -748.769 -11.8959 11.8959 0.19 0.00113406 0.00106371 0.101179 0.0951234 -1 -1 -1 -1 60 7674 24 1.21132e+07 3.11177e+06 934704. 3651.19 15.60 0.842417 0.781631 27828 185084 -1 6554 21 3570 7405 1259231 373839 12.6374 12.6374 -804.724 -12.6374 0 0 1.17753e+06 4599.72 0.05 0.41 0.19 -1 -1 0.05 0.119941 0.113336 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 397.07 vpr 588.61 MiB -1 -1 47.51 442352 97 87.76 -1 -1 111932 -1 -1 2144 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 602736 114 102 35834 31925 1 16899 2413 56 56 3136 clb auto 309.4 MiB 53.73 920886 213746 1814349 675153 1108132 31064 588.6 MiB 55.30 0.51 154.738 72.3421 -53235.9 -72.3421 72.3421 11.14 0.111004 0.0889287 11.5817 9.28701 -1 -1 -1 -1 86 321106 26 1.8697e+08 1.43379e+08 1.79819e+07 5734.03 92.36 40.2067 32.6519 420342 3799571 -1 296141 22 64120 253670 12914238 2332073 74.2773 74.2773 -68437.4 -74.2773 0 0 2.27638e+07 7258.87 1.70 13.36 4.62 -1 -1 1.70 8.68523 7.49958 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 50.68 vpr 315.80 MiB -1 -1 10.11 117064 5 5.53 -1 -1 44796 -1 -1 468 506 44 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 323384 506 553 3236 3734 1 2870 1571 50 50 2500 memory auto 57.7 MiB 3.71 43258 16890 1151825 563056 405712 183057 315.8 MiB 3.48 0.04 10.3136 6.751 -2071.22 -6.751 6.751 9.71 0.012349 0.0113575 1.79514 1.64399 -1 -1 -1 -1 38 24480 15 1.47946e+08 4.9335e+07 6.86579e+06 2746.32 9.05 5.36946 5.00747 258216 1426232 -1 23492 14 4552 6284 1218142 310467 6.93887 6.93887 -2608.52 -6.93887 0 0 8.69102e+06 3476.41 0.38 0.71 1.07 -1 -1 0.38 0.528311 0.503268 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 8.15 vpr 73.20 MiB -1 -1 0.80 25764 2 0.10 -1 -1 34472 -1 -1 32 311 15 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74952 311 156 1015 1158 1 965 514 28 28 784 memory auto 33.9 MiB 0.79 20788 7954 214546 78290 125007 11249 73.2 MiB 0.67 0.01 5.14999 3.96264 -4383.87 -3.96264 3.96264 0.70 0.00278678 0.00248288 0.315079 0.280645 -1 -1 -1 -1 38 13997 22 4.25198e+07 9.94461e+06 2.03941e+06 2601.29 2.23 0.858239 0.774237 77878 418209 -1 12797 12 2813 3148 647576 204191 4.19809 4.19809 -4942.1 -4.19809 -0.00135869 -0.00135869 2.58563e+06 3298.00 0.09 0.23 0.25 -1 -1 0.09 0.125259 0.116996 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 19.47 vpr 83.66 MiB -1 -1 4.55 51492 5 1.45 -1 -1 39328 -1 -1 166 193 5 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85672 193 205 2718 2652 1 1364 569 20 20 400 memory auto 44.0 MiB 1.94 21635 10677 236269 74431 136781 25057 83.7 MiB 1.26 0.01 6.95823 5.89435 -2880.21 -5.89435 5.89435 0.33 0.00448873 0.00407934 0.520725 0.458822 -1 -1 -1 -1 50 19020 48 2.07112e+07 1.16864e+07 1.26946e+06 3173.65 7.33 2.53112 2.27541 41784 253636 -1 16909 18 4979 12133 652802 138307 6.28852 6.28852 -3109.62 -6.28852 -0.00135869 -0.00135869 1.63222e+06 4080.54 0.05 0.37 0.15 -1 -1 0.05 0.246451 0.229778 +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 112.46 vpr 101.39 MiB -1 -1 3.74 61476 8 2.81 -1 -1 41920 -1 -1 247 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 103820 385 362 4415 4299 1 2357 997 26 26 676 io auto 56.8 MiB 5.49 60367 29168 553555 209559 320264 23732 97.1 MiB 4.21 0.04 12.484 9.22286 -10001.9 -9.22286 9.22286 0.61 0.0109639 0.0102538 1.47142 1.32279 -1 -1 -1 -1 96 41816 25 3.69863e+07 1.48038e+07 4.07810e+06 6032.69 88.96 8.68882 7.83852 93088 846470 -1 40322 20 9413 32446 1640117 290110 9.26797 9.26797 -10463.8 -9.26797 0 0 5.10087e+06 7545.67 0.27 1.53 0.96 -1 -1 0.27 1.0006 0.922311 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 16.70 vpr 84.32 MiB -1 -1 2.91 42012 3 0.56 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86348 236 305 3199 3011 1 1523 675 19 19 361 io auto 45.1 MiB 2.38 25623 12744 275862 97068 164529 14265 84.3 MiB 1.45 0.02 6.4321 4.87079 -2820.2 -4.87079 4.87079 0.30 0.00560063 0.00518298 0.604935 0.553038 -1 -1 -1 -1 60 23814 39 1.72706e+07 9.76854e+06 1.37250e+06 3801.94 6.34 2.17617 1.98275 40123 275431 -1 20936 19 6245 16081 1455169 369652 4.86514 4.86514 -3116.44 -4.86514 0 0 1.72840e+06 4787.81 0.05 0.53 0.17 -1 -1 0.05 0.287741 0.270352 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 14.92 vpr 83.92 MiB -1 -1 2.98 44692 3 1.09 -1 -1 39956 -1 -1 139 38 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85932 38 36 2739 2488 1 1049 213 16 16 256 clb auto 43.6 MiB 1.25 14747 8429 40218 10764 26818 2636 83.9 MiB 0.67 0.01 12.6186 10.0194 -2444.29 -10.0194 10.0194 0.20 0.00478325 0.0044014 0.318391 0.282226 -1 -1 -1 -1 52 14156 42 1.21132e+07 7.49127e+06 805949. 3148.24 6.25 1.87194 1.62272 26552 162987 -1 12220 20 4506 10512 364577 68819 10.9834 10.9834 -2789.57 -10.9834 0 0 1.06067e+06 4143.25 0.03 0.34 0.10 -1 -1 0.03 0.248301 0.225121 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 10.99 vpr 73.14 MiB -1 -1 2.17 32292 16 0.48 -1 -1 34992 -1 -1 61 45 3 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74900 45 32 1192 1151 1 792 142 14 14 196 memory auto 34.6 MiB 2.57 10230 6724 27522 7495 16921 3106 73.1 MiB 0.34 0.00 13.9782 11.2901 -7209.19 -11.2901 11.2901 0.14 0.00197313 0.00176092 0.168386 0.150089 -1 -1 -1 -1 68 12586 25 9.20055e+06 5.32753e+06 806220. 4113.37 3.63 0.879144 0.780585 22432 157909 -1 10569 14 3362 8864 714686 176877 11.347 11.347 -7521.29 -11.347 0 0 1.00082e+06 5106.22 0.03 0.22 0.10 -1 -1 0.03 0.118227 0.11088 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 49.68 vpr 238.52 MiB -1 -1 8.91 99444 5 6.21 -1 -1 65612 -1 -1 723 169 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 244244 169 197 23225 21365 1 6048 1089 34 34 1156 clb auto 159.4 MiB 7.36 138950 37803 566689 185725 358886 22078 206.7 MiB 5.55 0.05 7.50543 3.47733 -14028.3 -3.47733 3.47733 1.08 0.0240631 0.0193328 2.6984 2.20346 -1 -1 -1 -1 46 59195 29 6.50233e+07 3.89656e+07 3.64223e+06 3150.72 9.78 7.53696 6.32877 123264 752332 -1 52144 15 15228 24079 778526 165004 3.95658 3.95658 -15092.4 -3.95658 0 0 4.69209e+06 4058.90 0.19 1.34 0.44 -1 -1 0.19 1.3312 1.21354 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 129.15 vpr 301.43 MiB -1 -1 6.97 121944 3 10.79 -1 -1 73876 -1 -1 761 115 0 40 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 308664 115 145 22864 19301 1 9598 1061 40 40 1600 mult_36 auto 157.2 MiB 8.89 218173 82528 552779 175008 354397 23374 227.7 MiB 12.42 0.08 8.24796 5.97877 -23026.7 -5.97877 5.97877 2.52 0.0296366 0.0232576 5.18169 4.47986 -1 -1 -1 -1 82 129392 40 9.16046e+07 5.68542e+07 8.58295e+06 5364.35 72.16 18.2188 15.5745 207228 1787768 -1 115904 12 29451 44673 6496904 1453626 6.28596 6.28596 -25323 -6.28596 0 0 1.07702e+07 6731.38 0.42 2.40 1.26 -1 -1 0.42 1.27287 1.1697 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 249.03 vpr 927.26 MiB -1 -1 10.71 194260 3 5.49 -1 -1 151880 -1 -1 1693 149 0 179 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 949512 149 182 55415 37074 1 28410 2203 80 80 6400 mult_36 auto 317.6 MiB 24.65 1 282083 1936483 673873 1194432 68178 927.3 MiB 53.04 0.41 29.8396 13.6204 -50663.4 -13.6204 13.6204 26.08 0.0857036 0.0779151 11.8098 10.1507 -1 -1 -1 -1 86 389128 32 3.90281e+08 1.62125e+08 3.72333e+07 5817.70 84.75 35.4904 30.579 863488 7902436 -1 370287 22 99498 118781 13877842 2992969 13.7303 13.7303 -54909.4 -13.7303 0 0 4.71374e+07 7365.22 2.26 7.09 5.78 -1 -1 2.26 4.22602 3.76697 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.81 vpr 66.79 MiB -1 -1 0.48 22692 4 0.11 -1 -1 32964 -1 -1 15 11 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68392 11 2 303 283 2 85 28 7 7 49 clb auto 27.5 MiB 0.12 405 294 1078 210 791 77 66.8 MiB 0.02 0.00 2.07098 2.04849 -155.044 -2.04849 1.9058 0.02 0.000390247 0.00034808 0.0136362 0.0123455 -1 -1 -1 -1 34 389 13 1.07788e+06 808410 84249.8 1719.38 0.24 0.135196 0.115303 3756 15224 -1 348 10 168 283 4715 1617 2.10231 1.90634 -156.224 -2.10231 0 0 103542. 2113.11 0.00 0.03 0.01 -1 -1 0.00 0.025836 0.0238112 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt index 82805da6c73..41f25935228 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 244.09 vpr 1.63 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1710388 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.8 MiB 72.33 204820 846239 237450 497497 111292 1670.3 MiB 74.90 0.65 7.79489 -43439.9 -6.79489 3.28078 0.10 0.145044 0.126909 16.2828 14.2166 303821 13.2372 69243 3.01686 62436 131482 118528064 33642231 0 0 9.32900e+07 21594.9 16 1265168 16897716 -1 7.83099 3.2527 -39766.3 -6.83099 0 0 28.25 -1 -1 1670.3 MiB 34.12 23.3299 20.6779 1670.3 MiB -1 9.52 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 283.46 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1568820 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.9 MiB 100.65 250483 930441 270744 617644 42053 1427.9 MiB 105.66 1.16 88.0477 -77760.6 -87.0477 88.0477 0.04 0.138248 0.121195 14.6541 12.2965 344948 13.2210 84158 3.22556 78118 205246 82686512 15002058 0 0 5.14202e+07 21425.1 21 702232 9282330 -1 70.8752 70.8752 -96523.7 -69.8752 0 0 15.93 -1 -1 1478.1 MiB 30.26 22.7139 19.3696 1427.9 MiB -1 5.06 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 546.32 vpr 1.95 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2047732 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.8 MiB 197.71 509639 1864099 634981 1176586 52532 1902.3 MiB 202.15 1.98 13.0046 -365555 -12.0046 7.96311 0.08 0.240136 0.202587 26.0846 21.1277 742613 20.9997 172139 4.86777 125805 451636 168920802 27374866 0 0 1.14226e+08 21633.7 20 1553068 20716258 -1 12.6705 7.40682 -365097 -11.6705 0 0 34.41 -1 -1 1902.3 MiB 62.35 40.2332 33.4484 1902.3 MiB -1 12.28 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 585.36 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2009276 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.3 MiB 179.14 542870 2585506 917648 1577326 90532 1765.2 MiB 247.87 2.16 32.1444 -118378 -31.1444 6.23584 0.07 0.26061 0.217278 28.1774 23.7022 787384 20.0781 179841 4.58591 168930 665993 263454811 44272964 0 0 8.35478e+07 21555.2 21 1135740 15114436 -1 31.2519 6.12513 -116198 -30.2519 0 0 26.38 -1 -1 1858.7 MiB 86.58 43.2996 37.0968 1765.2 MiB -1 8.44 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 665.68 vpr 4.50 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4722308 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.9 MiB 143.60 659423 3667920 1455149 2188340 24431 4611.6 MiB 189.33 1.99 5.44974 -115422 -4.44974 3.12297 0.45 0.489655 0.429947 60.4384 53.4484 794955 11.5117 173671 2.51493 139983 173257 122973577 32392189 0 0 5.40274e+08 21813.4 12 7186500 97663758 -1 5.74024 3.40489 -147279 -4.74024 0 0 162.31 -1 -1 4611.6 MiB 45.39 79.3348 71.0438 4611.6 MiB -1 68.45 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 369.28 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1705764 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.4 MiB 132.64 278563 1870082 659393 1159933 50756 1577.3 MiB 148.04 1.40 223.632 -132177 -222.632 223.632 0.05 0.153184 0.136333 19.0846 16.0118 379374 13.4069 91772 3.24317 82642 255456 77638931 11638769 0 0 7.07061e+07 21491.2 20 956596 12773992 -1 190.135 190.135 -130112 -189.135 0 0 21.26 -1 -1 1598.5 MiB 30.66 28.1882 24.0263 1577.3 MiB -1 6.97 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 301.91 vpr 1.70 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1787064 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.6 MiB 111.07 267316 798034 216514 557130 24390 1745.2 MiB 83.83 0.97 17.6841 -330571 -16.6841 17.6841 0.08 0.142592 0.123421 13.5697 11.1733 388393 14.4100 90639 3.36285 77554 201450 104702784 19227779 0 0 1.03316e+08 21578.1 23 1396452 18714052 -1 16.8884 16.8884 -322143 -15.8884 0 0 31.36 -1 -1 1745.2 MiB 37.27 22.9987 19.4136 1745.2 MiB -1 9.87 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 129.79 vpr 1.23 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1288736 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 60.90 109402 531288 160105 346309 24874 1229.7 MiB 21.34 0.27 7.65386 -81772.1 -6.65386 7.65386 0.03 0.0542655 0.0415901 4.69487 3.74852 159807 19.3237 38947 4.70943 27112 111164 42415566 5550679 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 7.62538 7.62538 -77759.3 -6.62538 0 0 10.12 -1 -1 1229.7 MiB 15.08 7.2902 6.0554 1229.7 MiB -1 2.80 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 294.21 vpr 1.53 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1605968 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.4 MiB 149.56 245617 1517216 535912 903537 77767 1503.4 MiB 67.74 0.64 12.3707 -91754.7 -11.3707 4.62772 0.04 0.123763 0.0993875 12.5521 10.1851 366533 18.0443 84029 4.13671 58196 217697 65258498 9131006 0 0 6.38257e+07 21490.1 17 866116 11532596 -1 12.1773 4.52077 -87689.2 -11.1773 0 0 19.45 -1 -1 1503.4 MiB 24.63 19.0845 15.7987 1503.4 MiB -1 5.86 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 373.27 vpr 2.31 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2418176 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.2 MiB 113.69 225912 2286656 861887 1362579 62190 2361.5 MiB 99.88 0.94 9.64748 -102230 -8.64748 9.64748 0.14 0.158799 0.128764 21.1153 17.3148 383721 19.4260 88332 4.47183 55000 174045 129359271 32477749 0 0 2.01410e+08 21605.9 18 2701980 36491882 -1 8.6078 8.6078 -177231 -7.6078 0 0 60.49 -1 -1 2361.5 MiB 43.58 29.7071 24.9856 2361.5 MiB -1 22.04 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 287.89 vpr 2.03 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2130704 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.2 MiB 94.47 222406 1491426 518693 900478 72255 2080.8 MiB 60.89 0.53 9.27552 -41609.1 -8.27552 3.17342 0.13 0.131124 0.103107 15.5709 12.4005 371010 17.4897 81992 3.86518 55375 161185 120683489 26150077 0 0 1.70845e+08 21669.8 17 2296616 31015204 -1 9.29871 3.26388 -44629 -8.29871 0 0 50.69 -1 -1 2080.8 MiB 36.84 22.1828 18.2794 2080.8 MiB -1 17.67 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 115.46 vpr 1.42 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1487204 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 45.32 98385 149036 34562 99301 15173 1452.3 MiB 10.21 0.11 5.55968 -32411 -4.55968 4.12503 0.05 0.05808 0.0509959 5.30612 4.48561 158711 21.0019 34047 4.50536 20479 45132 33648692 7897451 0 0 7.61223e+07 21576.6 14 1038076 13772104 -1 5.83812 3.95731 -37986.2 -4.83812 0 0 22.99 -1 -1 1452.3 MiB 10.69 8.06663 7.00321 1452.3 MiB -1 7.95 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 308.79 vpr 1.75 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1838356 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1276.3 MiB 90.95 215620 2002487 658856 1202364 141267 1795.3 MiB 112.04 0.92 42.7601 -66808.9 -41.7601 42.7601 0.09 0.161772 0.13883 20.582 17.6888 320121 12.3518 76529 2.95285 71977 215082 87258601 20096356 0 0 1.07584e+08 21568.7 22 1452444 19486512 -1 38.7113 38.7113 -63596.1 -37.7113 0 0 32.70 -1 -1 1795.3 MiB 31.75 30.3911 26.5086 1795.3 MiB -1 11.75 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 194.32 vpr 1.76 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1848104 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1132.2 MiB 67.11 123583 1109975 381766 683735 44474 1804.8 MiB 39.31 0.39 9.15523 -32316.9 -8.15523 9.15523 0.10 0.0795356 0.0699448 8.32413 7.00496 172751 13.5928 41221 3.24345 30616 114657 28576108 5137032 0 0 1.28005e+08 21615.1 15 1733724 23216534 -1 8.8255 8.62305 -32652.3 -7.8255 0 0 39.07 -1 -1 1804.8 MiB 12.08 12.4456 10.6768 1804.8 MiB -1 13.32 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 379.96 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1788552 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1329.9 MiB 152.43 244085 1624747 493620 1093099 38028 1607.0 MiB 139.05 1.16 10.4142 -184930 -9.41415 10.4142 0.05 0.16033 0.126535 18.0534 14.5425 331959 9.29987 79923 2.23905 99630 253842 70436166 10502572 0 0 7.07061e+07 21491.2 17 956596 12773992 -1 9.6278 9.6278 -188775 -8.6278 0 0 21.47 -1 -1 1660.8 MiB 28.25 26.8951 22.1285 1607.0 MiB -1 7.63 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 241.84 vpr 1.65 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1727976 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.3 MiB 91.18 155434 1168868 372786 754711 41371 1617.1 MiB 70.29 0.65 5.78947 -22744 -4.78947 5.78947 0.06 0.166564 0.140884 17.2708 14.567 220363 9.18294 52613 2.19248 52262 94777 51757158 12255510 0 0 7.61223e+07 21576.6 17 1038076 13772104 -1 6.13383 6.13383 -28632.3 -5.13383 0 0 23.67 -1 -1 1626.7 MiB 20.25 25.2854 21.7301 1617.1 MiB -1 7.50 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 123.74 vpr 1.21 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1272416 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.6 MiB 48.17 156959 264252 69818 174977 19457 1223.8 MiB 19.40 0.22 6.30018 -21278.5 -5.30018 5.08848 0.02 0.0625285 0.0502951 5.37481 4.40679 214370 17.8300 51439 4.27838 52424 159985 69493207 10252744 0 0 3.29272e+07 21437.0 19 447460 5950766 -1 6.55525 5.17583 -23692.3 -5.55525 0 0 10.23 -1 -1 1223.8 MiB 22.52 9.11353 7.72653 1223.8 MiB -1 2.91 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 378.16 vpr 1.77 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1853480 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1362.9 MiB 112.93 299223 1985810 694705 1211569 79536 1665.8 MiB 167.05 1.45 220.781 -74322.2 -219.781 220.781 0.07 0.200934 0.169269 24.1803 20.5128 416847 12.7247 100775 3.07625 94693 283672 85089101 14646952 0 0 7.61223e+07 21576.6 21 1038076 13772104 -1 190.574 190.574 -74796.5 -189.574 0 0 22.90 -1 -1 1729.6 MiB 34.84 36.1614 31.133 1665.8 MiB -1 7.44 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 60.08 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1240452 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1062.9 MiB 15.84 61122 230944 38935 173615 18394 1188.2 MiB 11.81 0.18 4.96737 -5434.49 -3.96737 2.8073 0.02 0.0387336 0.0317178 2.57184 2.12328 72725 5.84747 18233 1.46603 25673 34471 10834392 1619170 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.00956 2.55962 -5093.98 -4.00956 0 0 8.03 -1 -1 1188.2 MiB 4.50 4.29731 3.66237 1188.2 MiB -1 2.18 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 297.39 vpr 2.16 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2263120 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.4 MiB 73.81 204576 1445886 511132 869441 65313 2210.1 MiB 89.30 0.98 8.29539 -39922.7 -7.29539 8.29539 0.17 0.107171 0.0943286 12.3686 10.4512 291171 14.2731 67635 3.31544 59148 140903 91946515 22482953 0 0 1.96207e+08 21685.1 19 2627776 35613460 -1 7.77837 7.50651 -37244.2 -6.77837 0 0 58.79 -1 -1 2210.1 MiB 28.79 18.2832 15.7996 2210.1 MiB -1 21.60 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 209.37 vpr 2.38 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2494924 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.9 MiB 49.01 125640 1144742 417642 695010 32090 2436.4 MiB 27.60 0.29 12.1377 -20404.2 -11.1377 5.98066 0.18 0.0583692 0.0490098 6.35528 5.34844 169403 19.8527 34281 4.01746 23768 95388 22780638 3618006 0 0 2.47896e+08 21669.2 14 3325632 44947178 -1 12.3671 6.09382 -23278.4 -11.3671 0 0 74.30 -1 -1 2436.4 MiB 9.07 9.00673 7.74787 2436.4 MiB -1 27.37 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 116.44 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1231712 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.8 MiB 66.58 77598 237654 57043 175228 5383 1183.4 MiB 12.28 0.19 7.75636 -48829.2 -6.75636 7.75636 0.02 0.0387637 0.0330252 3.16043 2.55192 107783 17.1520 26590 4.23138 18971 91032 29347868 3748700 0 0 2.50861e+07 21331.7 15 342304 4525318 -1 7.25059 7.25059 -44231.5 -6.25059 0 0 7.74 -1 -1 1183.4 MiB 10.12 5.32204 4.46908 1183.4 MiB -1 2.14 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 23.94 vpr 993.17 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1017004 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.6 MiB 6.88 10123 9091 942 7112 1037 993.2 MiB 0.58 0.01 5.30858 -4060.6 -4.30858 4.62312 0.00 0.00627854 0.00548745 0.259054 0.223136 13428 9.29273 3606 2.49550 3290 8079 3159547 482733 0 0 5.17151e+06 19890.4 10 69776 908778 -1 5.28356 4.46405 -3916.13 -4.28356 0 0 1.74 -1 -1 993.2 MiB 1.11 0.547712 0.492658 993.2 MiB -1 0.20 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 165.23 vpr 1.63 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1709648 22 252 53001 29054 7 22943 1413 54 40 4320 DSP auto 1236.1 MiB 40.53 578922 181131 841569 239646 513371 88552 1669.6 MiB 53.63 0.52 11.8556 7.81898 -42319.1 -6.81898 3.29835 0.03 0.135616 0.124385 16.0465 13.8938 277230 12.1003 64381 2.81005 62818 132705 116667443 33165919 0 0 9.32900e+07 21594.9 18 1265168 16897716 -1 7.55982 3.09933 -38446.9 -6.55982 0 0 17.20 -1 -1 1669.6 MiB 26.52 22.7893 20.0135 1669.6 MiB -1 6.41 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 194.29 vpr 1.51 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1578392 3 33 48977 39238 1 26189 1635 40 30 2400 LAB auto 1260.5 MiB 55.04 757873 274435 916295 263230 624392 28673 1444.8 MiB 77.31 0.86 103.199 88.716 -80010.6 -87.716 88.716 0.02 0.137583 0.112092 13.1911 10.6825 374986 14.3206 89842 3.43105 87924 246005 97241593 17317420 0 0 5.14202e+07 21425.1 24 702232 9282330 -1 70.9171 70.9171 -98532.9 -69.9171 0 0 9.76 -1 -1 1487.4 MiB 27.11 20.5289 17.0272 1444.8 MiB -1 3.90 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 377.31 vpr 1.95 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2045912 38 173 62892 59064 3 35490 2705 60 44 5280 M9K auto 1469.8 MiB 114.90 1 523120 1867766 631559 1187077 49130 1908.1 MiB 152.42 1.10 23.156 13.2224 -362193 -12.2224 8.03046 0.05 0.195577 0.167935 25.6333 19.9211 754105 21.2532 173913 4.90144 133627 487188 180124176 29221336 0 0 1.14226e+08 21633.7 18 1553068 20716258 -1 12.6128 7.39073 -357104 -11.6128 0 0 20.95 -1 -1 1908.1 MiB 48.70 36.7578 29.411 1908.1 MiB -1 9.39 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 417.05 vpr 1.91 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2006360 4 570 66175 54803 2 39253 3378 51 38 3876 LAB auto 1498.7 MiB 101.02 1 535331 2587548 913566 1578253 95729 1776.7 MiB 183.46 1.34 45.2277 30.3105 -116990 -29.3105 6.52897 0.04 0.195666 0.174112 25.6084 20.3089 792100 20.1819 180091 4.58854 202831 840406 332686158 55982239 0 0 8.35478e+07 21555.2 23 1135740 15114436 -1 29.4773 6.2883 -117164 -28.4773 0 0 15.61 -1 -1 1855.5 MiB 80.57 38.7669 31.6392 1776.7 MiB -1 5.93 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 443.03 vpr 4.50 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4723060 19 21 171111 96274 1 69189 3920 129 96 24768 DSP auto 2000.8 MiB 71.06 2 636893 3680425 1441522 2221827 17076 4612.4 MiB 140.90 1.75 6.62096 5.38274 -122739 -4.38274 3.41533 0.15 0.428725 0.373986 45.4388 39.5342 777057 11.2314 170068 2.45813 137555 171570 117628280 30536280 0 0 5.40274e+08 21813.4 12 7186500 97663758 -1 5.58128 3.52408 -142033 -4.58128 0 0 98.71 -1 -1 4612.4 MiB 33.17 59.5818 52.6569 4612.4 MiB -1 53.06 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 274.78 vpr 1.63 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1713652 227 309 49176 40422 1 28286 2492 47 35 3290 io auto 1318.4 MiB 72.05 1 275433 1843284 648037 1152717 42530 1590.5 MiB 139.26 1.07 289.572 222.374 -130782 -221.374 222.374 0.02 0.149074 0.117901 20.4499 16.2564 372383 13.1668 90057 3.18425 84611 265316 75779256 12463701 0 0 7.07061e+07 21491.2 21 956596 12773992 -1 190.263 190.263 -132409 -189.263 0 0 12.88 -1 -1 1605.6 MiB 23.30 28.2031 22.9215 1590.5 MiB -1 4.64 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 203.70 vpr 1.70 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1786780 3 33 52402 39411 1 26915 1592 57 42 4788 M9K auto 1285.8 MiB 61.57 876864 264364 791412 212031 554916 24465 1744.9 MiB 65.16 0.65 24.0259 17.4002 -332154 -16.4002 17.4002 0.05 0.142536 0.112127 13.0905 10.2581 382383 14.2113 89662 3.33229 75758 194667 95589814 17130134 0 0 1.03316e+08 21578.1 21 1396452 18714052 -1 16.7321 16.7321 -316694 -15.7321 0 0 19.24 -1 -1 1744.9 MiB 26.75 20.6792 16.8831 1744.9 MiB -1 8.15 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 88.03 vpr 1.23 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1290232 55 196 20131 19956 1 8019 1227 32 24 1536 LAB auto 1105.6 MiB 35.07 223666 106034 533073 154980 351492 26601 1251.9 MiB 15.87 0.20 10.5638 7.98463 -82831 -6.98463 7.98463 0.01 0.0581793 0.0521859 5.06741 3.88947 155185 19.3594 37908 4.72904 26635 120171 44318653 5861047 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 8.10181 8.10181 -79267.3 -7.10181 0 0 6.32 -1 -1 1251.9 MiB 12.19 7.83315 6.28675 1251.9 MiB -1 2.07 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 181.25 vpr 1.53 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1603172 84 171 36458 36247 3 20790 2367 44 33 2904 LAB auto 1268.1 MiB 81.14 599300 255080 1437255 479979 885421 71855 1501.7 MiB 46.87 0.45 17.1545 12.4465 -91330.5 -11.4465 4.45992 0.02 0.120982 0.0894776 12.0224 9.07078 364406 17.5398 83448 4.01656 55999 185251 56555792 7754659 0 0 6.23802e+07 21480.8 16 847384 11269474 -1 12.7357 4.18797 -90999.3 -11.7357 0 0 11.56 -1 -1 1501.7 MiB 16.62 17.272 13.5403 1501.7 MiB -1 4.42 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 249.79 vpr 2.31 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2419068 36 33 57796 49182 1 19635 2569 79 59 9322 M144K auto 1407.1 MiB 63.37 687588 226099 2218531 834530 1355192 28809 2362.4 MiB 68.81 0.68 18.0423 9.78823 -106228 -8.78823 9.78823 0.06 0.156822 0.12818 17.4559 14.0039 383131 19.5176 88177 4.49195 55287 189555 142027050 36001459 0 0 2.01410e+08 21605.9 18 2701980 36491882 -1 8.62869 8.62869 -135986 -7.62869 0 0 36.79 -1 -1 2362.4 MiB 36.89 23.9234 19.6875 2362.4 MiB -1 17.24 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 183.23 vpr 2.03 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2129380 202 276 35125 30509 3 21318 2020 73 54 7884 M9K auto 1220.8 MiB 49.25 782109 226940 1316712 439612 818763 58337 2079.5 MiB 41.20 0.36 10.3029 9.12883 -43356.7 -8.12883 3.36482 0.05 0.110797 0.0823899 12.5992 9.50036 371195 17.4172 82710 3.88091 55579 159944 111563169 23433137 0 0 1.70845e+08 21669.8 15 2296616 31015204 -1 9.1859 3.56835 -47482.5 -8.1859 0 0 30.53 -1 -1 2079.5 MiB 25.86 17.6423 13.833 2079.5 MiB -1 13.21 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 70.27 vpr 1.42 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1485336 3 2 14862 10304 26 7561 466 49 36 3528 DSP auto 1055.8 MiB 19.02 184798 85297 135916 31512 94725 9679 1450.5 MiB 7.99 0.10 7.29278 5.55968 -34908.3 -4.55968 4.09325 0.02 0.0617226 0.0506659 4.97988 4.16457 139805 18.5541 31297 4.15355 18124 38759 27933959 6509280 0 0 7.61223e+07 21576.6 14 1038076 13772104 -1 5.63749 3.99239 -40563.9 -4.63749 0 0 14.25 -1 -1 1450.5 MiB 7.47 7.35481 6.30369 1450.5 MiB -1 5.97 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 241.81 vpr 1.75 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1838024 35 658 51416 37539 1 27424 2511 58 43 4988 io auto 1316.4 MiB 51.04 948323 229942 1896171 635436 1127325 133410 1794.9 MiB 106.03 0.65 67.4142 43.6805 -67218.9 -42.6805 43.6805 0.05 0.147176 0.118236 22.3082 17.9517 337800 13.0359 80019 3.08799 92021 297464 123311075 28490887 0 0 1.07584e+08 21568.7 23 1452444 19486512 -1 38.5807 38.5807 -63507.4 -37.5807 0 0 19.82 -1 -1 1794.9 MiB 33.41 30.8252 25.4394 1794.9 MiB -1 8.55 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 124.50 vpr 1.76 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1844452 13 740 25173 25306 1 12838 1890 63 47 5922 io auto 1153.9 MiB 36.81 511809 123464 1123170 386810 683070 53290 1801.2 MiB 25.01 0.25 14.0109 8.89156 -32729.6 -7.89156 8.89156 0.04 0.0798946 0.060212 7.54908 5.83542 174594 13.6072 41482 3.23295 30417 111693 28104765 5049543 0 0 1.28005e+08 21615.1 12 1733724 23216534 -1 9.312 7.90522 -32948 -8.312 0 0 24.14 -1 -1 1801.2 MiB 8.53 10.4774 8.39933 1801.2 MiB -1 10.73 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 253.88 vpr 1.71 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1795052 79 38 66795 54922 1 35224 2428 47 35 3290 LAB auto 1380.7 MiB 94.09 1 250576 1568380 463687 1064695 39998 1616.6 MiB 99.48 0.83 19.7664 10.4808 -184122 -9.48083 10.4808 0.02 0.157661 0.119423 16.476 12.6508 340352 9.66333 81776 2.32180 86206 207566 53826209 8209764 0 0 7.07061e+07 21491.2 16 956596 12773992 -1 10.0058 10.0058 -194535 -9.00582 0 0 13.02 -1 -1 1666.0 MiB 17.88 23.576 18.6595 1616.6 MiB -1 5.01 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 152.90 vpr 1.65 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1730980 139 74 57121 41054 1 23901 1802 49 36 3528 DSP auto 1330.5 MiB 46.92 523367 148917 1108863 331082 721190 56591 1626.9 MiB 48.59 0.49 7.59102 5.69228 -22418.3 -4.69228 5.69228 0.03 0.128597 0.102115 13.8422 11.2402 213091 8.91706 51264 2.14521 51274 92514 47975319 11532374 0 0 7.61223e+07 21576.6 18 1038076 13772104 -1 6.06924 6.06924 -28283.6 -5.06924 0 0 14.31 -1 -1 1629.7 MiB 14.95 20.3691 17.088 1626.9 MiB -1 5.62 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 78.09 vpr 1.21 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1270700 2 52 16673 16662 2 11970 759 32 24 1536 M9K auto 1087.8 MiB 25.88 316622 151272 249879 62506 169778 17595 1222.8 MiB 12.56 0.16 8.23152 6.10201 -21277.5 -5.10201 5.06369 0.01 0.0608657 0.0448446 4.65112 3.49451 206638 17.2688 49600 4.14508 49955 156078 65896959 9506054 0 0 3.29272e+07 21437.0 17 447460 5950766 -1 5.95759 5.05709 -22801.2 -4.95759 0 0 6.24 -1 -1 1222.8 MiB 16.01 7.6001 6.00867 1222.8 MiB -1 1.96 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 278.89 vpr 1.77 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1856896 131 314 57881 45152 1 32883 2670 49 36 3528 DSP auto 1414.2 MiB 62.82 1 299910 2002290 699814 1233269 69207 1675.6 MiB 138.83 1.39 284.301 222.426 -75627 -221.426 222.426 0.03 0.236157 0.194737 23.5659 19.1088 418537 12.7579 101272 3.08700 110009 337269 96294911 17389823 0 0 7.61223e+07 21576.6 20 1038076 13772104 -1 194.866 194.866 -77192.9 -193.866 0 0 14.01 -1 -1 1735.4 MiB 30.32 33.6401 27.7968 1675.6 MiB -1 5.73 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 39.68 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1240084 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1077.4 MiB 8.17 181772 63669 220151 34297 170189 15665 1190.5 MiB 7.36 0.10 5.43671 4.9834 -5379.72 -3.9834 2.7577 0.01 0.029861 0.0231527 2.09146 1.68198 74208 5.86903 18737 1.48189 26177 36020 11211877 1692426 0 0 2.60031e+07 21349.0 16 354380 4692432 -1 5.06256 2.57234 -4972.33 -4.06256 0 0 4.88 -1 -1 1190.5 MiB 3.58 3.54136 2.96155 1190.5 MiB -1 1.45 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 204.51 vpr 2.16 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2260468 542 422 37277 26038 1 20404 2145 78 58 9048 io auto 1178.0 MiB 40.79 750296 228064 1467913 515344 879432 73137 2207.5 MiB 68.52 0.66 12.737 8.18785 -41350.9 -7.18785 8.18785 0.06 0.0966519 0.0771184 11.0478 8.92438 322744 15.8200 73105 3.58340 59794 137322 91182231 22125715 0 0 1.96207e+08 21685.1 20 2627776 35613460 -1 7.30285 7.27939 -40357.2 -6.30285 0 0 35.70 -1 -1 2207.5 MiB 22.97 16.1253 13.4219 2207.5 MiB -1 15.77 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 134.50 vpr 2.38 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2492860 403 704 15490 16194 1 8443 1837 88 65 11440 io auto 1075.7 MiB 26.81 420969 123874 1171421 444803 693731 32887 2434.4 MiB 18.14 0.17 15.5138 11.646 -20021 -10.646 5.46969 0.09 0.0503342 0.0392748 5.60953 4.44327 169038 20.0235 34647 4.10412 24224 99582 23849257 3883264 0 0 2.47896e+08 21669.2 17 3325632 44947178 -1 11.6834 5.38195 -22298.1 -10.6834 0 0 44.54 -1 -1 2434.4 MiB 7.35 7.87318 6.44077 2434.4 MiB -1 19.44 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 69.67 vpr 1.17 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1229912 18 17 16969 16357 1 6487 772 28 21 1176 LAB auto 1072.8 MiB 35.55 163040 72492 241492 59461 177034 4997 1184.0 MiB 7.88 0.12 10.8841 7.97919 -43930.8 -6.97919 7.97919 0.01 0.0361636 0.0267893 2.69 2.03031 103493 15.9638 25861 3.98905 17521 69428 20784533 3065429 0 0 2.50861e+07 21331.7 13 342304 4525318 -1 7.06018 7.06018 -41291.6 -6.06018 0 0 4.79 -1 -1 1184.0 MiB 5.57 4.20349 3.36329 1184.0 MiB -1 1.39 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 19.55 vpr 995.23 MiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1019120 18 17 2291 2142 1 1462 118 13 10 260 LAB auto 956.8 MiB 4.11 13715 10389 9077 1002 7044 1031 995.2 MiB 0.43 0.01 5.45489 5.30858 -4076.26 -4.30858 4.57983 0.00 0.00509865 0.00456934 0.219625 0.189235 13990 9.58876 3763 2.57916 3281 7657 3126738 496499 0 0 5.17151e+06 19890.4 10 69776 908778 -1 5.24165 4.31206 -3750.06 -4.24165 0 0 1.11 -1 -1 995.2 MiB 0.80 0.440544 0.395044 995.2 MiB -1 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt index 46f57bf760a..8c5e0d1eb21 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 245.62 vpr 1.63 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1710616 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.9 MiB 75.60 184944 854209 237356 546771 70082 1670.5 MiB 72.88 0.69 7.97251 -43075.7 -6.97251 3.30339 0.08 0.146166 0.132698 17.0437 15.0301 301371 13.1305 69191 3.01460 59225 124430 116802792 31972323 0 0 9.32900e+07 21594.9 16 1265168 16897716 -1 8.04852 3.11041 -39249.7 -7.04852 0 0 28.37 -1 -1 1670.5 MiB 33.95 23.995 21.3968 1670.5 MiB -1 9.57 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 270.96 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1570676 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.8 MiB 102.33 228282 920766 279042 595583 46141 1429.0 MiB 88.59 0.94 88.2845 -80659 -87.2845 88.2845 0.04 0.14392 0.1195 14.5711 12.2042 355838 13.6383 86376 3.31057 77310 201105 89811404 15105784 0 0 5.14202e+07 21425.1 24 702232 9282330 -1 70.4773 70.4773 -94845.6 -69.4773 0 0 15.57 -1 -1 1479.9 MiB 33.28 23.5591 20.0191 1429.0 MiB -1 4.91 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 509.62 vpr 1.95 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2047208 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.5 MiB 198.26 451048 1864099 647919 1164574 51606 1901.9 MiB 164.98 1.47 13.1506 -361183 -12.1506 7.9921 0.08 0.247442 0.196485 26.6398 21.6013 732955 20.7266 171188 4.84088 124728 456761 177820618 26065245 0 0 1.14226e+08 21633.7 19 1553068 20716258 -1 12.8769 7.53335 -363190 -11.8769 0 0 34.42 -1 -1 1901.9 MiB 62.40 40.217 33.3925 1901.9 MiB -1 11.90 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 567.58 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2010460 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.8 MiB 182.98 484271 2560191 884458 1582491 93242 1765.5 MiB 199.71 1.77 30.1698 -117772 -29.1698 6.32625 0.06 0.250873 0.209174 27.8047 23.3414 819023 20.8849 185777 4.73728 196681 798495 366587115 55913961 0 0 8.35478e+07 21555.2 22 1135740 15114436 -1 29.383 6.18561 -115406 -28.383 0 0 25.30 -1 -1 1859.5 MiB 114.24 42.8002 36.5375 1765.5 MiB -1 8.24 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 659.64 vpr 4.50 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4722024 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.9 MiB 143.54 633199 3760290 1490720 2235840 33730 4611.4 MiB 182.36 1.64 5.44974 -120174 -4.44974 3.48061 0.38 0.500711 0.446581 64.3668 57.2048 792964 11.4829 169052 2.44804 136130 168139 120657048 30423925 0 0 5.40274e+08 21813.4 11 7186500 97663758 -1 5.66375 3.85682 -156124 -4.66375 0 0 164.59 -1 -1 4611.4 MiB 43.21 81.7626 73.4249 4611.4 MiB -1 67.85 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 346.58 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1706888 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1277.2 MiB 130.96 235454 1785192 630171 1108259 46762 1578.0 MiB 123.59 1.24 223.973 -131867 -222.973 223.973 0.06 0.15399 0.137707 18.3847 15.5681 381869 13.4950 92844 3.28105 78342 247729 91337050 11782368 0 0 7.07061e+07 21491.2 19 956596 12773992 -1 184.913 184.913 -126417 -183.913 0 0 21.19 -1 -1 1599.2 MiB 34.88 27.0233 23.1993 1578.0 MiB -1 6.86 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 293.47 vpr 1.70 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1786932 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.4 MiB 111.19 242706 816556 231855 560850 23851 1745.1 MiB 73.99 0.84 17.4268 -331657 -16.4268 17.4268 0.09 0.152091 0.122991 14.1776 11.6814 398717 14.7930 92932 3.44793 77467 205644 117024334 20394306 0 0 1.03316e+08 21578.1 21 1396452 18714052 -1 16.917 16.917 -320368 -15.917 0 0 31.30 -1 -1 1745.1 MiB 38.71 22.7388 19.2113 1745.1 MiB -1 9.99 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 125.97 vpr 1.23 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1288384 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 59.12 92593 557464 169405 360888 27171 1229.7 MiB 20.18 0.28 7.84939 -78165.6 -6.8494 7.84939 0.02 0.0579092 0.0459609 5.05811 4.04769 159733 19.3148 38820 4.69408 24505 101419 42311105 5071555 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 7.81851 7.81851 -71908.7 -6.81851 0 0 10.15 -1 -1 1229.7 MiB 14.27 7.7811 6.44817 1229.7 MiB -1 2.82 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 281.85 vpr 1.53 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1606428 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.5 MiB 149.46 215765 1517216 518543 921536 77137 1503.3 MiB 58.02 0.60 11.9872 -86085.7 -10.9872 4.67996 0.04 0.124604 0.100056 12.4857 10.1291 368614 18.1467 84927 4.18092 54529 192216 59535264 7516911 0 0 6.38257e+07 21490.1 16 866116 11532596 -1 12.0375 4.6146 -82845.8 -11.0375 0 0 19.13 -1 -1 1503.3 MiB 22.39 18.634 15.5175 1503.3 MiB -1 6.30 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 351.01 vpr 2.30 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2416864 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.1 MiB 113.80 191652 2198126 837039 1305954 55133 2360.2 MiB 85.43 0.84 9.95158 -103978 -8.95158 9.95158 0.14 0.157427 0.126297 20.3063 16.4066 380882 19.2822 88412 4.47588 48910 148956 112086751 26603030 0 0 2.01410e+08 21605.9 17 2701980 36491882 -1 9.01423 9.01423 -137565 -8.01423 0 0 60.43 -1 -1 2360.2 MiB 36.97 28.4438 23.7031 2360.2 MiB -1 21.63 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 283.30 vpr 2.03 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2130904 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.7 MiB 91.45 212379 1465966 513016 878305 74645 2081.0 MiB 57.22 0.51 9.02677 -43039.7 -8.02677 3.39009 0.15 0.130982 0.112127 16.0361 12.8184 388469 18.3128 85167 4.01485 54060 155006 126101728 25409947 0 0 1.70845e+08 21669.8 17 2296616 31015204 -1 9.33987 3.47782 -46390.5 -8.33987 0 0 50.94 -1 -1 2081.0 MiB 38.16 22.6708 18.6622 2081.0 MiB -1 18.21 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 116.04 vpr 1.42 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1487240 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 44.85 91640 143465 34428 97411 11626 1452.4 MiB 9.56 0.11 5.55968 -32627.3 -4.55968 4.03585 0.05 0.0580242 0.0511336 5.23009 4.40266 162858 21.5506 34640 4.58383 20772 47469 39442838 8696473 0 0 7.61223e+07 21576.6 17 1038076 13772104 -1 5.83812 3.81128 -37803.8 -4.83812 0 0 22.95 -1 -1 1452.4 MiB 12.55 8.31954 7.18554 1452.4 MiB -1 7.74 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 307.88 vpr 1.76 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1842824 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1280.9 MiB 92.83 193340 1985246 651294 1194899 139053 1799.6 MiB 104.91 0.90 42.817 -66341.8 -41.817 42.817 0.08 0.174464 0.149553 21.4513 18.52 318648 12.2949 76857 2.96551 72321 215661 101797360 20420450 0 0 1.07584e+08 21568.7 26 1452444 19486512 -1 38.0834 38.0834 -61419.7 -37.0834 0 0 32.89 -1 -1 1799.6 MiB 36.69 32.4273 28.3397 1799.6 MiB -1 11.41 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 191.13 vpr 1.76 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1848728 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1133.0 MiB 66.11 114187 1121763 389127 687964 44672 1805.4 MiB 36.03 0.35 9.10047 -33210.9 -8.10047 9.10047 0.10 0.0829476 0.0672165 8.6028 7.09879 180406 14.1951 42811 3.36856 29439 106878 36794843 4980523 0 0 1.28005e+08 21615.1 13 1733724 23216534 -1 8.86459 8.53756 -33502.4 -7.86459 0 0 39.09 -1 -1 1805.4 MiB 13.39 12.4192 10.5234 1805.4 MiB -1 13.65 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 365.42 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1789484 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.0 MiB 148.46 220034 1575085 472174 1056131 46780 1607.4 MiB 128.88 1.19 10.366 -185682 -9.366 10.366 0.05 0.166017 0.132704 17.7166 14.3298 340742 9.54593 82334 2.30660 86785 211666 72987830 8810844 0 0 7.07061e+07 21491.2 18 956596 12773992 -1 10.3348 10.3348 -186105 -9.33478 0 0 21.58 -1 -1 1659.8 MiB 29.02 26.9646 22.2301 1607.4 MiB -1 7.36 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 236.24 vpr 1.65 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1729420 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1290.4 MiB 89.13 143448 1223918 387573 791889 44456 1618.2 MiB 69.23 0.62 6.15923 -22935.6 -5.15923 6.15923 0.06 0.160924 0.134554 18.8103 16.0328 226941 9.45706 54238 2.26020 51698 93187 54990565 12041480 0 0 7.61223e+07 21576.6 16 1038076 13772104 -1 6.33927 6.33927 -28490.3 -5.33927 0 0 23.07 -1 -1 1627.8 MiB 19.85 26.0631 22.6082 1618.2 MiB -1 7.69 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 121.12 vpr 1.21 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1272616 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.8 MiB 48.71 145866 267719 70212 178005 19502 1223.6 MiB 17.33 0.21 6.32104 -21443.6 -5.32104 5.1317 0.02 0.0642369 0.0519236 5.54676 4.5538 218475 18.1714 52270 4.34750 52154 158487 72130661 9975959 0 0 3.29272e+07 21437.0 17 447460 5950766 -1 6.2459 4.96992 -24617.9 -5.2459 0 0 10.12 -1 -1 1223.6 MiB 22.65 9.07986 7.70719 1223.6 MiB -1 2.99 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 360.73 vpr 1.77 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1854860 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1363.2 MiB 112.86 262777 1930208 669923 1189043 71242 1666.5 MiB 145.10 1.38 223.441 -74881.2 -222.441 223.441 0.05 0.211297 0.180427 24.3293 20.7548 427696 13.0558 103553 3.16106 90894 273726 106018598 14702817 0 0 7.61223e+07 21576.6 21 1038076 13772104 -1 190.035 190.035 -73399.2 -189.035 0 0 23.08 -1 -1 1732.8 MiB 39.37 36.0725 31.1574 1666.5 MiB -1 7.54 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 60.38 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1239040 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1061.9 MiB 15.77 60924 230944 39979 176254 14711 1186.8 MiB 11.56 0.18 5.04063 -5430.36 -4.04063 2.87222 0.02 0.0364742 0.0318647 2.60212 2.17525 74753 6.01053 18783 1.51025 25814 34889 12202224 1634430 0 0 2.60031e+07 21349.0 17 354380 4692432 -1 5.24483 2.65773 -5067.06 -4.24483 0 0 8.10 -1 -1 1186.8 MiB 4.94 4.43218 3.80588 1186.8 MiB -1 2.32 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 296.54 vpr 2.16 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2262908 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.3 MiB 72.90 213411 1459636 524477 868204 66955 2209.9 MiB 84.09 0.87 8.12716 -41041.3 -7.12716 8.12716 0.14 0.11422 0.095868 12.9019 10.9024 322533 15.8104 73202 3.58833 58164 135585 115660664 26279570 0 0 1.96207e+08 21685.1 19 2627776 35613460 -1 7.60563 7.60563 -38875.6 -6.60563 0 0 58.66 -1 -1 2209.9 MiB 34.96 18.71 16.1454 2209.9 MiB -1 20.83 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 209.98 vpr 2.38 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2494688 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.9 MiB 49.31 117261 1200767 458957 708379 33431 2436.2 MiB 25.42 0.26 11.7854 -20675.2 -10.7854 5.73126 0.18 0.0562212 0.0465333 6.50332 5.46368 182292 21.3632 36297 4.25372 22684 88666 28845037 3461649 0 0 2.47896e+08 21669.2 14 3325632 44947178 -1 11.9953 5.82624 -23038.5 -10.9953 0 0 74.42 -1 -1 2436.2 MiB 10.82 9.12659 7.84634 2436.2 MiB -1 27.36 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 115.88 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1230928 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.5 MiB 66.57 64446 230476 54244 170900 5332 1183.1 MiB 10.85 0.17 7.74825 -47724 -6.74825 7.74825 0.02 0.0458274 0.0351245 3.17308 2.53234 105547 16.7961 26043 4.14433 16938 75501 27527280 3256994 0 0 2.50861e+07 21331.7 14 342304 4525318 -1 7.60467 7.60467 -45348.9 -6.60467 0 0 7.98 -1 -1 1183.1 MiB 9.47 5.27867 4.40168 1183.1 MiB -1 2.23 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 23.87 vpr 993.03 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1016864 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.3 MiB 6.57 8979 9091 989 7145 957 993.0 MiB 0.57 0.01 5.30858 -4141.38 -4.30858 4.67064 0.00 0.00654281 0.00572201 0.265779 0.231578 13865 9.59516 3702 2.56194 3278 7822 3354574 494732 0 0 5.17151e+06 19890.4 12 69776 908778 -1 5.46939 4.48287 -3903.7 -4.46939 0 0 1.75 -1 -1 993.0 MiB 1.23 0.606378 0.546433 993.0 MiB -1 0.21 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 163.02 vpr 1.63 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1710280 22 252 53001 29054 7 22943 1413 54 40 4320 DSP auto 1236.7 MiB 39.44 553143 184563 873273 250110 551395 71768 1670.2 MiB 51.56 0.44 11.8556 7.87174 -43548.4 -6.87174 3.3085 0.04 0.123505 0.111445 15.5558 13.296 304060 13.2714 69338 3.02641 61073 128176 122419449 33174955 0 0 9.32900e+07 21594.9 19 1265168 16897716 -1 7.53553 3.06212 -39277 -6.53553 0 0 17.19 -1 -1 1670.2 MiB 28.45 21.8553 18.9725 1670.2 MiB -1 6.50 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 180.22 vpr 1.51 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1579152 3 33 48977 39238 1 26189 1635 40 30 2400 LAB auto 1260.6 MiB 54.69 675596 228461 906667 263743 600906 42018 1445.6 MiB 65.17 0.61 103.199 89.4627 -80347.1 -88.4627 89.4627 0.02 0.123029 0.0986105 14.199 11.4265 356523 13.6155 87289 3.33355 78260 206743 90689914 14925324 0 0 5.14202e+07 21425.1 22 702232 9282330 -1 70.9785 70.9785 -96386.4 -69.9785 0 0 9.85 -1 -1 1487.0 MiB 25.33 21.059 17.3632 1445.6 MiB -1 3.35 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 340.01 vpr 1.95 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2048992 38 173 62892 59064 3 35490 2705 60 44 5280 M9K auto 1470.4 MiB 113.22 1 466891 1867766 638347 1188962 40457 1908.5 MiB 119.16 1.11 23.156 12.9703 -351376 -11.9703 8.02903 0.05 0.215422 0.185865 24.9657 19.578 756272 21.3142 175267 4.93960 128214 464786 184257221 27767301 0 0 1.14226e+08 21633.7 19 1553068 20716258 -1 12.3378 7.46737 -352387 -11.3378 0 0 20.97 -1 -1 1908.5 MiB 48.79 36.2864 29.2693 1908.5 MiB -1 7.98 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 373.89 vpr 1.91 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2007384 4 570 66175 54803 2 39253 3378 51 38 3876 LAB auto 1499.1 MiB 99.87 1 482306 2562213 886867 1580400 94946 1776.8 MiB 144.28 1.36 45.2277 30.0102 -117157 -29.0102 6.49654 0.03 0.212298 0.19009 25.7913 20.7174 808619 20.6028 183919 4.68607 176656 706881 320986661 49813509 0 0 8.35478e+07 21555.2 21 1135740 15114436 -1 29.0374 6.24338 -115391 -28.0374 0 0 15.81 -1 -1 1856.1 MiB 78.25 38.3522 31.5254 1776.8 MiB -1 5.73 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 429.60 vpr 4.50 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4722240 19 21 171111 96274 1 69189 3920 129 96 24768 DSP auto 2001.1 MiB 73.03 2 602918 3649530 1421026 2196167 32337 4611.6 MiB 132.23 1.27 6.62096 5.16746 -108678 -4.16746 3.16445 0.24 0.404496 0.351859 49.8836 43.962 760441 10.9913 164698 2.38051 138720 171477 121850186 30999203 0 0 5.40274e+08 21813.4 12 7186500 97663758 -1 5.18984 3.41724 -137387 -4.18984 0 0 98.44 -1 -1 4611.6 MiB 32.70 63.1285 56.2041 4611.6 MiB -1 49.27 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 217.11 vpr 1.63 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1714264 227 309 49176 40422 1 28286 2492 47 35 3290 io auto 1318.1 MiB 72.14 949337 230310 1809508 633583 1119861 56064 1590.1 MiB 79.93 0.86 289.572 220.521 -127261 -219.521 220.521 0.02 0.156112 0.125918 17.0682 13.7681 371393 13.1318 90754 3.20890 78062 243708 86098619 10967186 0 0 7.07061e+07 21491.2 19 956596 12773992 -1 183.258 183.258 -122529 -182.258 0 0 13.56 -1 -1 1605.5 MiB 23.90 23.9832 19.7076 1590.1 MiB -1 4.56 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 198.54 vpr 1.70 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1786688 3 33 52402 39411 1 26915 1592 57 42 4788 M9K auto 1285.6 MiB 61.21 807202 237745 809996 223571 562388 24037 1744.8 MiB 56.29 0.57 24.0259 17.5288 -339439 -16.5288 17.5288 0.05 0.140741 0.109909 14.9895 12.1055 395902 14.7137 92407 3.43431 79357 212916 121957158 21173533 0 0 1.03316e+08 21578.1 22 1396452 18714052 -1 17.0616 17.0616 -326321 -16.0616 0 0 19.00 -1 -1 1744.8 MiB 31.88 22.557 18.3795 1744.8 MiB -1 7.95 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 81.67 vpr 1.23 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1291604 55 196 20131 19956 1 8019 1227 32 24 1536 LAB auto 1106.5 MiB 34.94 197415 91389 533073 155258 350786 27029 1252.7 MiB 12.28 0.15 10.5638 7.9694 -84401.8 -6.9694 7.9694 0.01 0.0391724 0.0337257 4.13053 3.13542 156922 19.5761 38124 4.75599 24144 106283 43472187 5062582 0 0 3.29272e+07 21437.0 17 447460 5950766 -1 8.0038 8.0038 -76147.9 -7.0038 0 0 6.09 -1 -1 1252.7 MiB 10.82 6.4594 5.1443 1252.7 MiB -1 1.83 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 174.35 vpr 1.53 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1603028 84 171 36458 36247 3 20790 2367 44 33 2904 LAB auto 1266.2 MiB 81.48 546571 214795 1437255 480391 886927 69937 1498.7 MiB 38.24 0.40 17.1545 12.2615 -90825 -11.2615 4.44627 0.02 0.118854 0.087873 11.8695 8.93815 368296 17.7270 84627 4.07331 55785 195975 64857507 8108532 0 0 6.23802e+07 21480.8 14 847384 11269474 -1 12.4986 4.24047 -87839 -11.4986 0 0 11.58 -1 -1 1498.7 MiB 18.31 16.6314 13.0164 1498.7 MiB -1 4.08 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 233.35 vpr 2.31 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2417992 36 33 57796 49182 1 19635 2569 79 59 9322 M144K auto 1406.8 MiB 62.54 653233 192546 2183357 844340 1310310 28707 2361.3 MiB 58.92 0.56 18.0423 9.76693 -96722.1 -8.76693 9.76693 0.06 0.125515 0.0975704 16.3759 12.9715 379198 19.3173 88012 4.48355 51383 170986 126474373 30291745 0 0 2.01410e+08 21605.9 16 2701980 36491882 -1 8.56238 8.56238 -127393 -7.56238 0 0 36.63 -1 -1 2361.3 MiB 32.09 22.3007 18.2177 2361.3 MiB -1 16.38 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 183.95 vpr 2.03 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2129820 202 276 35125 30509 3 21318 2020 73 54 7884 M9K auto 1221.4 MiB 50.16 716729 207560 1380532 469949 847523 63060 2079.9 MiB 35.53 0.34 10.3029 9.20592 -44245.9 -8.20592 3.37783 0.05 0.134527 0.101332 13.395 10.226 376235 17.6537 83221 3.90489 56995 167645 133187361 25954915 0 0 1.70845e+08 21669.8 16 2296616 31015204 -1 9.30202 3.57682 -47252 -8.30202 0 0 31.53 -1 -1 2079.9 MiB 31.26 18.6275 14.7303 2079.9 MiB -1 13.18 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 67.96 vpr 1.42 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1486328 3 2 14862 10304 26 7561 466 49 36 3528 DSP auto 1055.6 MiB 18.96 169108 90003 135916 31625 92700 11591 1451.5 MiB 6.45 0.08 7.29278 5.55968 -33241.7 -4.55968 3.91952 0.02 0.0505029 0.0412837 4.05288 3.36705 161880 21.4837 34654 4.59907 19262 41383 32535712 7242694 0 0 7.61223e+07 21576.6 14 1038076 13772104 -1 5.7478 3.7418 -36662.8 -4.7478 0 0 13.92 -1 -1 1451.5 MiB 7.99 6.02567 5.12234 1451.5 MiB -1 5.58 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 204.01 vpr 1.75 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1838636 35 658 51416 37539 1 27424 2511 58 43 4988 io auto 1316.9 MiB 49.69 873485 208058 1947351 617969 1190949 138433 1795.5 MiB 71.44 0.68 67.4142 43.3331 -66203.9 -42.3331 43.3331 0.05 0.15867 0.129165 19.3481 15.9045 342451 13.2154 80916 3.12260 78710 239308 118664359 23155496 0 0 1.07584e+08 21568.7 28 1452444 19486512 -1 38.8692 38.8692 -61793.9 -37.8692 0 0 19.67 -1 -1 1795.5 MiB 32.19 28.9085 24.1772 1795.5 MiB -1 8.02 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 119.98 vpr 1.76 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1845228 13 740 25173 25306 1 12838 1890 63 47 5922 io auto 1153.9 MiB 36.41 470725 111381 1111490 384644 673635 53211 1802.0 MiB 22.09 0.20 14.0109 8.87029 -33339 -7.87029 8.87029 0.04 0.0714492 0.0529662 7.49782 5.77897 179395 13.9814 42811 3.33653 29405 105946 37157864 4956640 0 0 1.28005e+08 21615.1 12 1733724 23216534 -1 9.27318 8.25275 -33374.7 -8.27318 0 0 23.38 -1 -1 1802.0 MiB 10.17 10.396 8.3228 1802.0 MiB -1 9.19 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 245.62 vpr 1.71 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1796636 79 38 66795 54922 1 35224 2428 47 35 3290 LAB auto 1382.7 MiB 93.98 1 215377 1486820 430516 1012081 44223 1618.4 MiB 86.33 0.85 19.7664 10.4506 -183686 -9.45055 10.4506 0.02 0.156777 0.119319 15.6084 11.9943 339321 9.63405 80812 2.29443 96886 244258 86910997 10095189 0 0 7.07061e+07 21491.2 16 956596 12773992 -1 9.53723 9.53723 -187005 -8.53723 0 0 12.88 -1 -1 1667.2 MiB 23.92 22.6479 18.0205 1618.4 MiB -1 5.24 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 151.40 vpr 1.65 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1731440 139 74 57121 41054 1 23901 1802 49 36 3528 DSP auto 1329.9 MiB 46.56 503320 137704 1108863 333769 717933 57161 1626.9 MiB 43.96 0.51 7.59102 5.46013 -22573.5 -4.46013 5.46013 0.03 0.180195 0.165554 16.5709 13.7008 220251 9.21668 53111 2.22250 52406 96881 61898013 13579685 0 0 7.61223e+07 21576.6 19 1038076 13772104 -1 5.99682 5.99682 -24267.2 -4.99682 0 0 14.28 -1 -1 1630.1 MiB 17.88 23.1986 19.4889 1626.9 MiB -1 5.57 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 75.64 vpr 1.21 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1271256 2 52 16673 16662 2 11970 759 32 24 1536 M9K auto 1088.2 MiB 25.74 287692 137368 242959 60191 164382 18386 1223.0 MiB 10.25 0.13 8.23152 6.34257 -21161.6 -5.34257 5.09376 0.01 0.0560926 0.0414855 4.32633 3.28263 205192 17.1479 49371 4.12594 47973 149300 66746671 9307991 0 0 3.29272e+07 21437.0 18 447460 5950766 -1 6.25468 5.09564 -22684.1 -5.25468 0 0 6.19 -1 -1 1223.0 MiB 15.98 7.17592 5.75226 1223.0 MiB -1 1.87 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 230.76 vpr 1.77 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1856468 131 314 57881 45152 1 32883 2670 49 36 3528 DSP auto 1412.8 MiB 63.31 1 257536 1909715 654346 1173189 82180 1674.1 MiB 92.41 1.05 284.301 220.986 -75834.1 -219.986 220.986 0.02 0.196207 0.158753 21.9219 17.9789 420532 12.8188 102359 3.12013 89184 263712 101905909 14381353 0 0 7.61223e+07 21576.6 20 1038076 13772104 -1 184.902 184.902 -76513.8 -183.902 0 0 13.99 -1 -1 1734.2 MiB 28.86 31.23 26.0791 1674.1 MiB -1 5.28 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 39.93 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1239412 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1076.4 MiB 8.18 177076 60430 220151 37040 166912 16199 1189.7 MiB 7.30 0.11 5.43671 4.98186 -5389.45 -3.98186 2.74369 0.01 0.0330879 0.0259898 2.22718 1.78099 73991 5.85187 18405 1.45563 25780 35867 12871709 1745504 0 0 2.60031e+07 21349.0 14 354380 4692432 -1 5.1649 2.66536 -5084.57 -4.1649 0 0 4.88 -1 -1 1189.7 MiB 3.94 3.62393 3.00964 1189.7 MiB -1 1.45 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 183.79 vpr 2.15 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2259360 542 422 37277 26038 1 20404 2145 78 58 9048 io auto 1178.3 MiB 40.93 718781 204992 1467913 504698 890114 73101 2206.4 MiB 50.27 0.49 12.737 8.21006 -40868.3 -7.21006 8.21006 0.06 0.0958342 0.0782222 10.5753 8.68058 311797 15.2834 70688 3.46493 55201 125849 88584799 20461803 0 0 1.96207e+08 21685.1 17 2627776 35613460 -1 7.63571 7.3669 -38752.7 -6.63571 0 0 36.77 -1 -1 2206.4 MiB 20.74 14.778 12.4345 2206.4 MiB -1 15.04 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 144.61 vpr 2.38 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2493348 403 704 15490 16194 1 8443 1837 88 65 11440 io auto 1076.0 MiB 26.78 391708 113907 1227651 472143 719270 36238 2434.9 MiB 19.47 0.16 15.5138 11.322 -19964.1 -10.322 5.3194 0.08 0.0431255 0.0386447 6.67046 5.26228 181646 21.5169 36609 4.33653 23247 92055 29218683 3595560 0 0 2.47896e+08 21669.2 15 3325632 44947178 -1 11.1981 5.14875 -21508.2 -10.1981 0 0 45.58 -1 -1 2434.9 MiB 8.58 8.83493 7.15206 2434.9 MiB -1 24.64 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 70.10 vpr 1.17 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1229776 18 17 16969 16357 1 6487 772 28 21 1176 LAB auto 1072.2 MiB 36.08 142961 59688 234412 55116 174656 4640 1183.5 MiB 7.02 0.10 10.8841 7.86052 -43530.3 -6.86052 7.86052 0.01 0.0355175 0.0260839 2.6175 1.99269 97980 15.1134 24516 3.78158 16004 64606 24187188 2810280 0 0 2.50861e+07 21331.7 13 342304 4525318 -1 7.19078 7.19078 -42143.8 -6.19078 0 0 4.71 -1 -1 1183.5 MiB 6.19 4.18474 3.37608 1183.5 MiB -1 1.41 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 17.77 vpr 996.36 MiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1020276 18 17 2291 2142 1 1462 118 13 10 260 LAB auto 957.7 MiB 3.86 11981 9290 8499 834 6799 866 996.4 MiB 0.38 0.01 5.45489 5.30858 -4057.33 -4.30858 4.57404 0.00 0.00478301 0.00426942 0.190791 0.165029 13985 9.58533 3795 2.60110 3319 7859 3369135 512682 0 0 5.17151e+06 19890.4 9 69776 908778 -1 5.24356 4.64087 -3951.05 -4.24356 0 0 1.07 -1 -1 996.4 MiB 0.83 0.393205 0.353496 996.4 MiB -1 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt index 1a9fa971299..baf8b675296 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 1172.59 vpr 1.65 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1734316 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.6 MiB 73.64 214653 894059 251005 559264 83790 1693.7 MiB 79.53 0.65 7.70472 -37826.5 -6.70472 3.17657 0.08 0.149615 0.135881 18.4856 16.2276 346942 15.1160 80330 3.49991 71500 157095 1535090931 789230213 0 0 8.89497e+07 20590.2 18 1365594 16211305 -1 7.67229 3.07739 -42724.4 -6.67229 0 0 29.57 -1 -1 1693.7 MiB 940.94 26.0477 23.0694 1693.7 MiB -1 23.96 -3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 329.77 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1576816 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.5 MiB 99.18 252169 969141 295922 624406 48813 1444.1 MiB 90.56 0.89 82.4495 -56586.4 -81.4495 82.4495 0.03 0.133831 0.117153 15.353 12.8639 420916 16.1326 105895 4.05868 118615 321172 291100673 58952034 0 0 4.91306e+07 20471.1 26 758110 8921656 -1 72.0146 72.0146 -132785 -71.0146 0 0 16.42 -1 -1 1484.9 MiB 85.29 24.7756 21.0909 1444.1 MiB -1 12.23 -3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 641.04 vpr 1.96 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2050760 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.2 MiB 203.13 510171 1939307 680820 1206280 52207 1927.9 MiB 173.07 1.61 11.2616 -300285 -10.2616 7.35058 0.09 0.251364 0.202792 27.6684 22.4451 799864 22.6187 198121 5.60249 142256 518619 474643655 110260894 0 0 1.08858e+08 20617.0 17 1675578 19868374 -1 14.7898 8.01616 -421363 -13.7898 0 0 36.05 -1 -1 1927.9 MiB 161.55 40.1269 33.3458 1927.9 MiB -1 29.72 -3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 991.70 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2018452 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.4 MiB 179.88 509692 2712081 968624 1648149 95308 1790.4 MiB 217.33 1.88 26.7071 -106583 -25.7071 4.92953 0.06 0.265658 0.222085 30.753 25.8577 822920 20.9843 201896 5.14831 185617 735052 1296414490 366645497 0 0 7.97022e+07 20563.0 20 1225854 14507865 -1 30.288 6.57341 -120054 -29.288 0 0 26.21 -1 -1 1867.6 MiB 509.93 45.4244 38.8563 1790.4 MiB -1 20.62 -3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 1067.25 vpr 4.62 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4842056 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.7 MiB 144.01 645363 3760290 1509060 2226895 24335 4728.6 MiB 196.62 2.32 6.72849 -100513 -5.72849 2.73028 0.43 0.510597 0.454713 66.2712 58.6699 801246 11.6028 176582 2.55708 136809 169565 554939068 253332108 0 0 5.14406e+08 20769.0 10 7758968 93673935 -1 6.25252 4.02616 -144264 -5.25252 0 0 173.36 -1 -1 4728.6 MiB 346.30 83.0597 74.3223 4728.6 MiB -1 149.18 -3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 397.31 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1713464 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.8 MiB 127.62 267729 1921016 704204 1175385 41427 1599.4 MiB 134.02 1.32 194.73 -111174 -193.73 194.73 0.05 0.16753 0.141447 20.6062 17.3755 409980 14.4885 103027 3.64092 98368 318292 234678586 45271456 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 196.841 196.841 -137573 -195.841 0 0 22.11 -1 -1 1604.7 MiB 66.77 29.7244 25.3562 1599.4 MiB -1 17.48 -3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 413.22 vpr 1.73 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1814172 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.2 MiB 110.44 272716 825817 229328 570617 25872 1771.7 MiB 82.01 0.93 15.8733 -287969 -14.8733 15.8733 0.07 0.156169 0.134842 15.1402 12.4708 427395 15.8570 107058 3.97203 83662 216621 348016314 94876303 0 0 9.85096e+07 20574.3 20 1507654 17957159 -1 18.2989 18.2989 -351435 -17.2989 0 0 32.91 -1 -1 1771.7 MiB 133.99 23.8154 20.073 1771.7 MiB -1 25.41 -3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 136.48 vpr 1.24 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1295860 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 59.84 106751 583640 180621 371614 31405 1246.6 MiB 21.31 0.25 7.0989 -65567.9 -6.0989 7.0989 0.02 0.0579001 0.0443717 5.41731 4.32489 176951 21.3967 45151 5.45961 29990 122737 58119884 11106318 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.58513 8.58513 -82449.9 -7.58513 0 0 10.90 -1 -1 1246.6 MiB 18.17 8.28886 6.85025 1246.6 MiB -1 6.97 -3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 490.96 vpr 1.54 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1612568 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.2 MiB 149.78 250819 1565561 553633 923794 88134 1522.9 MiB 59.74 0.57 10.3141 -74446.1 -9.31412 4.16669 0.05 0.122453 0.0982616 12.7928 10.36 417504 20.5535 99339 4.89042 64295 236643 559755019 162046743 0 0 6.09438e+07 20519.8 16 935204 11078823 -1 14.1009 4.7173 -100461 -13.1009 0 0 19.72 -1 -1 1522.9 MiB 220.56 19.1309 15.8639 1522.9 MiB -1 14.15 -3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 456.82 vpr 2.35 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2459944 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.5 MiB 116.70 208658 2198126 841464 1306315 50347 2402.3 MiB 88.77 0.83 9.15792 -77023.4 -8.15792 9.15792 0.15 0.152102 0.123811 20.4428 16.5197 386740 19.5788 94929 4.80580 57777 193960 262282869 78128583 0 0 1.92002e+08 20596.6 16 2917968 35039980 -1 9.09509 9.09509 -148250 -8.09509 0 0 62.97 -1 -1 2402.3 MiB 105.94 28.2563 23.5085 2402.3 MiB -1 49.55 -3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 391.83 vpr 2.07 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2167360 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.5 MiB 91.51 224050 1542346 541947 927260 73139 2116.6 MiB 59.94 0.50 9.32745 -27918.9 -8.32745 3.0761 0.12 0.131152 0.102135 16.6741 13.2554 393714 18.5600 91424 4.30981 54848 152461 310286597 88766009 0 0 1.62738e+08 20641.5 15 2479452 29744051 -1 9.42064 3.77724 -50913.7 -8.42064 0 0 53.44 -1 -1 2116.6 MiB 114.73 22.9686 18.8221 2116.6 MiB -1 44.42 -3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 148.74 vpr 1.44 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1511644 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1036.2 MiB 45.72 83064 154607 38752 101305 14550 1476.2 MiB 10.09 0.11 5.67702 -19756.2 -4.67702 3.74463 0.05 0.0597777 0.0527936 5.58527 4.74534 152254 20.1474 35176 4.65476 19877 43738 72454580 21374549 0 0 7.26079e+07 20580.5 14 1120110 13214470 -1 5.84516 4.10311 -39834.2 -4.84516 0 0 24.01 -1 -1 1476.2 MiB 28.04 8.35092 7.24512 1476.2 MiB -1 22.29 -3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 346.43 vpr 1.78 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1868112 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1276.9 MiB 93.13 219255 2157656 730879 1273796 152981 1824.3 MiB 109.67 0.89 40.2879 -60979.5 -39.2879 40.2879 0.08 0.170403 0.154539 23.7513 20.5481 349212 13.4742 85186 3.28688 77275 233364 143562765 36702160 0 0 1.02587e+08 20566.7 21 1568252 18700371 -1 38.5591 38.5591 -67167.5 -37.5591 0 0 34.79 -1 -1 1824.3 MiB 50.23 33.5444 29.3581 1824.3 MiB -1 28.83 -3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 218.13 vpr 1.79 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1877276 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1133.0 MiB 66.22 123520 1204279 427315 726664 50300 1833.3 MiB 39.61 0.36 9.02181 -27438.3 -8.02181 9.02181 0.09 0.0790484 0.0694683 9.30633 7.78111 180566 14.2077 43756 3.44291 31272 116811 38575938 8660251 0 0 1.22008e+08 20602.6 13 1871156 22275272 -1 10.1297 8.7558 -37422.6 -9.12975 0 0 40.27 -1 -1 1833.3 MiB 15.13 13.1986 11.2705 1833.3 MiB -1 33.84 -3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 395.83 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1795672 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.1 MiB 147.79 247450 1624747 516348 1068765 39634 1627.6 MiB 129.80 1.19 9.58554 -169343 -8.58554 9.58554 0.05 0.181629 0.143035 18.586 15.0291 368099 10.3123 95475 2.67474 86257 200403 122474916 27418708 0 0 6.75216e+07 20523.3 17 1033138 12274942 -1 10.0787 10.0787 -216795 -9.07872 0 0 22.36 -1 -1 1667.7 MiB 46.86 27.3022 22.6133 1627.6 MiB -1 18.57 -3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 251.39 vpr 1.66 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1735768 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.7 MiB 85.10 145328 1179878 360849 786061 32968 1640.5 MiB 69.36 0.64 5.18803 -16009.3 -4.18803 4.71553 0.06 0.152706 0.134393 18.4109 15.5777 214240 8.92778 54586 2.27470 53253 96856 65663526 17180534 0 0 7.26079e+07 20580.5 19 1120110 13214470 -1 5.62731 5.62731 -28524.3 -4.62731 0 0 23.91 -1 -1 1640.5 MiB 26.16 26.596 22.9352 1640.5 MiB -1 19.18 -3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 136.47 vpr 1.23 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1290392 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1065.8 MiB 47.70 152283 278120 75325 183121 19674 1260.1 MiB 18.99 0.21 5.35599 -16505.5 -4.35599 4.51559 0.02 0.0653283 0.0529731 5.96357 4.87661 239529 19.9226 64112 5.33245 57238 170600 111195486 21263938 0 0 3.14199e+07 20455.7 20 483264 5705245 -1 6.61831 5.4172 -26290.3 -5.61831 0 0 10.52 -1 -1 1260.1 MiB 32.71 9.93276 8.38713 1260.1 MiB -1 7.29 -3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 437.55 vpr 1.78 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1867528 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1362.4 MiB 112.91 292652 2022878 726716 1212218 83944 1695.6 MiB 151.83 1.37 193.523 -65237.6 -192.523 193.523 0.06 0.213557 0.18157 25.9931 22.1715 453070 13.8304 113197 3.45545 117143 365096 327048949 70274290 0 0 7.26079e+07 20580.5 21 1120110 13214470 -1 201.969 201.969 -83602 -200.969 0 0 23.94 -1 -1 1743.7 MiB 97.67 37.8603 32.6631 1695.6 MiB -1 18.81 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 67.95 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1235488 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1063.1 MiB 15.63 63489 256928 52638 188949 15341 1198.2 MiB 13.00 0.16 4.8555 -4307.79 -3.8555 2.47976 0.02 0.0366363 0.0322351 3.02693 2.52688 81757 6.57369 23123 1.85921 26483 36571 27721140 5378093 0 0 2.48366e+07 20391.3 14 382818 4502703 -1 4.99885 2.78104 -5808.83 -3.99885 0 0 8.34 -1 -1 1198.2 MiB 8.51 4.71161 4.0282 1198.2 MiB -1 5.30 -3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 447.54 vpr 2.19 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2300520 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.3 MiB 74.85 225689 1597136 573868 950177 73091 2246.6 MiB 97.02 0.89 7.40155 -34081.7 -6.40155 7.40155 0.16 0.121776 0.101863 14.3979 12.1212 339854 16.6595 81624 4.00118 64892 154040 296022532 107475224 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.54909 8.54909 -42257.7 -7.54909 0 0 62.88 -1 -1 2246.6 MiB 134.16 19.8788 17.0808 2246.6 MiB -1 53.46 -3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 304.70 vpr 2.43 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2550580 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.6 MiB 49.77 123671 1380047 554552 786292 39203 2490.8 MiB 31.02 0.26 10.5993 -16629.2 -9.59931 4.97242 0.18 0.0546677 0.0486849 7.77113 6.51315 175220 20.5344 38433 4.50404 23623 93265 107849323 36421682 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 12.8766 5.81047 -24731 -11.8766 0 0 79.59 -1 -1 2490.8 MiB 52.92 10.6013 9.06122 2490.8 MiB -1 68.45 -3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 117.22 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1225656 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.5 MiB 63.70 72669 252010 65056 180799 6155 1192.1 MiB 11.10 0.16 7.46032 -42922.1 -6.46033 7.46032 0.02 0.0386153 0.0330756 3.3215 2.67044 118105 18.7946 31588 5.02673 19732 92762 36148054 6649139 0 0 2.39639e+07 20377.5 15 369794 4343188 -1 7.99918 7.99918 -51485.8 -6.99918 0 0 8.05 -1 -1 1192.1 MiB 11.26 5.50251 4.59387 1192.1 MiB -1 5.21 -3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 24.11 vpr 992.77 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1016600 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.8 MiB 6.88 9528 9390 1205 7155 1030 992.8 MiB 0.57 0.01 5.30062 -3506.54 -4.30062 4.33661 0.00 0.00633989 0.00552195 0.266113 0.231235 16243 11.2408 5134 3.55294 3509 8574 4051674 833095 0 0 4.97530e+06 19135.8 10 75766 878809 -1 5.2881 4.86207 -4539.08 -4.2881 0 0 1.87 -1 -1 992.8 MiB 1.27 0.557486 0.502971 992.8 MiB -1 0.41 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 262.73 vpr 1.65 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1734948 22 252 53001 29054 7 22943 1413 54 40 4320 DSP auto 1237.0 MiB 40.61 553143 199178 920829 267183 541717 111929 1694.3 MiB 53.87 0.43 9.17101 7.5216 -35787.7 -6.5216 3.21182 0.04 0.16305 0.149822 18.4612 15.68 322466 14.0747 77116 3.36589 65350 138528 312160453 107280244 0 0 8.89497e+07 20590.2 18 1365594 16211305 -1 7.74971 3.11486 -42530.8 -6.74971 0 0 17.72 -1 -1 1694.3 MiB 111.17 24.7092 21.2822 1694.3 MiB -1 18.30 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 218.36 vpr 1.51 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1586640 3 33 48977 39238 1 26189 1635 40 30 2400 LAB auto 1260.7 MiB 55.85 675596 255759 897039 258557 606947 31535 1458.8 MiB 57.70 0.68 88.3086 81.3363 -53562.1 -80.3363 81.3363 0.02 0.116071 0.101917 12.5335 10.2057 414968 15.8475 103107 3.93764 93456 268271 242027202 52796438 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.6061 72.6061 -112440 -71.6061 0 0 9.98 -1 -1 1494.3 MiB 64.92 19.6347 16.356 1458.8 MiB -1 8.68 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 457.48 vpr 1.96 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2060360 38 173 62892 59064 3 35490 2705 60 44 5280 M9K auto 1471.4 MiB 113.33 1 520068 1924283 670353 1216654 37276 1942.0 MiB 131.56 1.10 15.2717 11.5238 -301358 -10.5238 7.39686 0.05 0.213567 0.18504 27.6637 21.7347 817382 23.0365 199937 5.63489 142706 522733 461856750 113156179 0 0 1.08858e+08 20617.0 17 1675578 19868374 -1 13.8204 7.75079 -387049 -12.8204 0 0 22.95 -1 -1 1942.0 MiB 135.56 38.2071 30.7885 1942.0 MiB -1 24.32 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 652.90 vpr 1.93 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2028064 4 570 66175 54803 2 39253 3378 51 38 3876 LAB auto 1499.6 MiB 99.84 1 500409 2638218 943482 1600815 93921 1829.0 MiB 158.67 1.26 33.2636 26.8304 -103428 -25.8304 5.04591 0.03 0.211943 0.190267 27.9403 22.4025 815041 20.7664 199378 5.07995 180000 713197 1112642923 293988107 0 0 7.97022e+07 20563.0 19 1225854 14507865 -1 29.4376 6.2205 -118224 -28.4376 0 0 15.52 -1 -1 1877.4 MiB 329.08 39.5382 32.3284 1829.0 MiB -1 19.13 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 891.67 vpr 4.62 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4842964 19 21 171111 96274 1 69189 3920 129 96 24768 DSP auto 2000.7 MiB 71.30 2 645543 3742215 1460860 2253546 27809 4729.5 MiB 143.23 1.55 6.26745 5.38646 -75141.3 -4.38646 2.661 0.21 0.381461 0.352014 50.6194 44.9049 793742 11.4726 177452 2.56485 138089 170387 641489720 283501353 0 0 5.14406e+08 20769.0 13 7758968 93673935 -1 5.52629 3.53475 -126958 -4.52629 0 0 103.08 -1 -1 4729.5 MiB 405.15 65.0255 58.2156 4729.5 MiB -1 124.42 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 256.11 vpr 1.63 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1714208 227 309 49176 40422 1 28286 2492 47 35 3290 io auto 1318.7 MiB 72.10 949337 273836 1826396 645111 1142297 38988 1612.8 MiB 96.72 0.93 225.36 192.733 -109545 -191.733 192.733 0.02 0.156504 0.126676 20.8925 16.8363 408295 14.4366 100640 3.55845 86047 274415 147097876 28755122 0 0 6.75216e+07 20523.3 21 1033138 12274942 -1 200.665 200.665 -142282 -199.665 0 0 13.32 -1 -1 1612.8 MiB 36.86 29.3018 24.1342 1612.8 MiB -1 13.65 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 269.17 vpr 1.73 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1812688 3 33 52402 39411 1 26915 1592 57 42 4788 M9K auto 1284.6 MiB 61.12 807203 272165 819288 227842 565954 25492 1770.2 MiB 52.22 0.49 18.2161 15.3889 -291282 -14.3889 15.3889 0.05 0.120302 0.107221 13.5276 10.7971 422804 15.7135 103735 3.85532 81547 210905 297118544 78086054 0 0 9.85096e+07 20574.3 19 1507654 17957159 -1 16.9508 16.9508 -333506 -15.9508 0 0 19.51 -1 -1 1770.2 MiB 88.24 20.4969 16.8404 1770.2 MiB -1 24.30 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 89.89 vpr 1.24 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1302480 55 196 20131 19956 1 8019 1227 32 24 1536 LAB auto 1106.6 MiB 34.90 197415 104963 533073 153234 353035 26804 1272.0 MiB 12.26 0.14 8.14098 7.01338 -66863.1 -6.01338 7.01338 0.01 0.039475 0.0343628 4.18838 3.15967 176313 21.9951 44706 5.57710 30256 140591 66330875 12196118 0 0 3.14199e+07 20455.7 18 483264 5705245 -1 8.49466 8.49466 -83973.4 -7.49466 0 0 6.31 -1 -1 1272.0 MiB 15.31 6.65714 5.25964 1272.0 MiB -1 4.97 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 299.01 vpr 1.55 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1621904 84 171 36458 36247 3 20790 2367 44 33 2904 LAB auto 1267.4 MiB 80.84 546571 238344 1484559 494119 911634 78806 1532.2 MiB 40.61 0.36 12.4149 9.92645 -70892.9 -8.92645 4.01682 0.02 0.116517 0.0861493 12.2531 9.24683 412828 19.8704 97692 4.70216 64195 234317 420279392 124136285 0 0 5.95688e+07 20512.7 16 914964 10827114 -1 11.9935 4.50781 -88218.8 -10.9935 0 0 11.79 -1 -1 1532.2 MiB 133.15 17.7182 13.8758 1532.2 MiB -1 11.09 +3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 373.19 vpr 2.35 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2462636 36 33 57796 49182 1 19635 2569 79 59 9322 M144K auto 1407.5 MiB 62.12 653233 219853 2183357 820965 1334147 28245 2404.9 MiB 59.41 0.49 12.995 9.21965 -66996.8 -8.21965 9.21965 0.06 0.128267 0.100412 17.0634 13.614 394289 20.0860 93339 4.75492 57830 186027 364956321 126736164 0 0 1.92002e+08 20596.6 18 2917968 35039980 -1 8.77433 8.77433 -145846 -7.77433 0 0 38.68 -1 -1 2404.9 MiB 142.35 23.6694 19.4579 2404.9 MiB -1 44.19 +3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 392.27 vpr 2.07 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2167316 202 276 35125 30509 3 21318 2020 73 54 7884 M9K auto 1222.1 MiB 49.37 716730 226089 1457116 486885 913306 56925 2116.5 MiB 42.81 0.35 9.52583 8.88073 -26635 -7.88073 3.18285 0.07 0.119653 0.0909611 14.637 11.0787 399097 18.7264 91130 4.27599 54535 154132 519438963 188622732 0 0 1.62738e+08 20641.5 16 2479452 29744051 -1 9.08319 3.80572 -49812 -8.08319 0 0 32.24 -1 -1 2116.5 MiB 209.16 19.8689 15.6003 2116.5 MiB -1 36.86 +3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 85.50 vpr 1.44 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1509716 3 2 14862 10304 26 7561 466 49 36 3528 DSP auto 1056.3 MiB 18.88 169108 85844 135916 30477 93312 12127 1474.3 MiB 6.51 0.07 5.73048 5.557 -19015 -4.557 3.62644 0.03 0.0456596 0.0411065 4.08767 3.43596 157309 20.8771 36213 4.80597 18870 41509 57269136 14229362 0 0 7.26079e+07 20580.5 15 1120110 13214470 -1 5.78387 4.12666 -38218.5 -4.78387 0 0 14.31 -1 -1 1474.3 MiB 14.90 6.20184 5.31676 1474.3 MiB -1 15.38 +3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 248.43 vpr 1.78 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1866084 35 658 51416 37539 1 27424 2511 58 43 4988 io auto 1316.8 MiB 50.40 873485 226954 1964411 652069 1171686 140656 1822.3 MiB 73.09 0.61 49.8814 40.4001 -59333.6 -39.4001 40.4001 0.03 0.158116 0.128524 19.1544 15.9201 355332 13.7125 84607 3.26504 77692 234589 195988135 57038734 0 0 1.02587e+08 20566.7 20 1568252 18700371 -1 38.7069 38.7069 -65173.3 -37.7069 0 0 20.54 -1 -1 1822.3 MiB 56.96 26.6827 22.5702 1822.3 MiB -1 23.14 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 141.37 vpr 1.79 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1874180 13 740 25173 25306 1 12838 1890 63 47 5922 io auto 1153.9 MiB 36.12 470725 123620 1228290 428597 741781 57912 1830.3 MiB 24.74 0.23 10.849 8.56701 -26610 -7.56701 8.56701 0.05 0.083452 0.064458 8.41672 6.65404 186843 14.5618 44606 3.47642 30689 112737 37690136 7677659 0 0 1.22008e+08 20602.6 12 1871156 22275272 -1 9.76611 8.4502 -37527.7 -8.76611 0 0 24.66 -1 -1 1830.3 MiB 11.13 11.422 9.27304 1830.3 MiB -1 26.23 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 285.30 vpr 1.73 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1811880 79 38 66795 54922 1 35224 2428 47 35 3290 LAB auto 1382.5 MiB 92.81 1 237877 1503132 446447 1022533 34152 1655.8 MiB 78.24 0.76 13.2451 9.5537 -149791 -8.5537 9.5537 0.02 0.152306 0.114957 15.7483 12.0158 358747 10.1856 91140 2.58766 88569 216835 204329717 50299933 0 0 6.75216e+07 20523.3 18 1033138 12274942 -1 9.9587 9.9587 -197744 -8.9587 0 0 13.29 -1 -1 1682.4 MiB 65.08 23.1672 18.3775 1655.8 MiB -1 12.44 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 213.89 vpr 1.66 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1740508 139 74 57121 41054 1 23901 1802 49 36 3528 DSP auto 1330.9 MiB 48.02 503320 154131 1174629 363761 769595 41273 1652.4 MiB 45.14 0.39 5.50142 5.06937 -14829.9 -4.06937 4.54902 0.03 0.138834 0.113113 15.68 12.9864 226482 9.47742 56073 2.34645 53387 100788 162800398 52833452 0 0 7.26079e+07 20580.5 19 1120110 13214470 -1 5.71253 5.71253 -26580.8 -4.71253 0 0 14.37 -1 -1 1652.4 MiB 63.76 22.1086 18.5194 1652.4 MiB -1 20.85 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 89.86 vpr 1.23 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1290592 2 52 16673 16662 2 11970 759 32 24 1536 M9K auto 1088.0 MiB 26.43 287692 161090 263719 72038 171536 20145 1260.3 MiB 11.76 0.13 6.37147 5.55664 -16395.7 -4.55664 4.47275 0.01 0.050566 0.0440543 5.03152 3.8482 241810 20.2081 60678 5.07087 57910 175927 97879920 19640107 0 0 3.14199e+07 20455.7 19 483264 5705245 -1 6.59971 5.40287 -26695.4 -5.59971 0 0 6.31 -1 -1 1260.3 MiB 24.34 8.27622 6.64124 1260.3 MiB -1 5.29 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 264.05 vpr 1.77 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1859132 131 314 57881 45152 1 32883 2670 49 36 3528 DSP auto 1415.0 MiB 62.59 1 282089 1946745 666918 1199261 80566 1701.5 MiB 104.89 1.01 225.053 191.914 -65212.8 -190.914 191.914 0.03 0.201041 0.162936 22.616 18.5359 440255 13.4200 111096 3.38645 97832 293933 160920714 33139153 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 194.207 194.207 -87739.7 -193.207 0 0 14.29 -1 -1 1736.8 MiB 41.90 32.0428 26.7006 1701.5 MiB -1 15.35 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 48.49 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1234732 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1076.6 MiB 8.80 177076 64046 227463 40446 173214 13803 1199.8 MiB 8.23 0.15 5.037 4.98027 -4032.99 -3.98027 2.30436 0.01 0.0456958 0.0355344 2.82114 2.35786 82605 6.53314 22481 1.77800 26837 36867 19813331 3639454 0 0 2.48366e+07 20391.3 15 382818 4502703 -1 5.12354 2.59981 -5253.47 -4.12354 0 0 5.41 -1 -1 1199.8 MiB 5.89 4.54065 3.86566 1199.8 MiB -1 4.08 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 272.56 vpr 2.19 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2297736 542 422 37277 26038 1 20404 2145 78 58 9048 io auto 1177.8 MiB 41.32 718781 227527 1550881 568722 914128 68031 2243.9 MiB 60.56 0.59 9.1469 7.25001 -32266.1 -6.25001 7.25001 0.08 0.111702 0.0914081 11.9361 9.76182 338642 16.5993 80909 3.96593 60739 140963 198511353 67181932 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.14337 8.14337 -40401.7 -7.14337 0 0 39.17 -1 -1 2243.9 MiB 66.88 16.2467 13.6205 2243.9 MiB -1 42.87 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 217.37 vpr 2.43 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2549592 403 704 15490 16194 1 8443 1837 88 65 11440 io auto 1076.1 MiB 26.90 391708 129482 1351357 540069 773475 37813 2489.8 MiB 18.66 0.17 12.456 10.282 -15333.7 -9.28198 4.73291 0.06 0.0436402 0.0391903 6.14215 4.89907 181658 21.5184 37765 4.47347 23596 95797 116291029 41210250 0 0 2.36204e+08 20647.2 14 3590540 43137666 -1 12.3059 5.94528 -23194.4 -11.3059 0 0 46.11 -1 -1 2489.8 MiB 49.68 8.25084 6.75286 2489.8 MiB -1 56.27 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 73.98 vpr 1.17 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1223460 18 17 16969 16357 1 6487 772 28 21 1176 LAB auto 1072.6 MiB 35.91 142961 68762 237952 59303 174205 4444 1190.2 MiB 7.64 0.11 8.63391 7.26898 -38694.5 -6.26898 7.26898 0.01 0.0364213 0.0268054 2.9362 2.27444 111711 17.2314 29470 4.54573 17605 69986 22583565 4090868 0 0 2.39639e+07 20377.5 17 369794 4343188 -1 8.03719 8.03719 -45879 -7.03719 0 0 4.86 -1 -1 1190.2 MiB 6.10 4.74059 3.843 1190.2 MiB -1 4.07 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 18.64 vpr 996.46 MiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1020380 18 17 2291 2142 1 1462 118 13 10 260 LAB auto 958.0 MiB 3.90 11981 9495 9077 1082 6988 1007 996.5 MiB 0.40 0.01 5.34371 5.28494 -3500.46 -4.28494 4.32118 0.00 0.00526682 0.00474166 0.209093 0.18422 16213 11.1124 5131 3.51679 3569 8497 3648403 741386 0 0 4.97530e+06 19135.8 10 75766 878809 -1 5.33265 4.71601 -4254.84 -4.33265 0 0 1.12 -1 -1 996.5 MiB 0.87 0.456072 0.414736 996.5 MiB -1 0.26 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt index 08e1f46286a..262c8456a37 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 536.55 vpr 1.66 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1736116 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1203.7 MiB 75.33 195509 902029 259905 557804 84320 1695.4 MiB 84.98 0.74 7.68567 -37648.9 -6.68567 3.28584 0.07 0.153024 0.133083 18.1163 15.7769 347393 15.1356 91110 3.96959 68562 144013 571183324 243523602 0 0 8.89497e+07 20590.2 16 1365594 16211305 -1 7.79531 3.22903 -48240.7 -6.79531 0 0 29.52 -1 -1 1695.4 MiB 297.68 25.2358 22.2605 1695.4 MiB -1 24.01 -3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 315.33 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1577588 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.4 MiB 101.58 259626 940116 279572 621693 38851 1444.2 MiB 104.57 1.20 82.1047 -56021.6 -81.1047 82.1047 0.03 0.137922 0.120416 14.543 12.1914 423885 16.2464 113939 4.36698 96228 253395 185059095 38347475 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.5235 72.5235 -115556 -71.5235 0 0 16.27 -1 -1 1486.1 MiB 54.76 23.4199 19.9723 1444.2 MiB -1 12.10 -3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 679.10 vpr 1.96 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2051156 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.4 MiB 202.36 543821 1995713 704501 1236982 54230 1927.9 MiB 222.49 2.01 11.2639 -298285 -10.2639 7.34492 0.09 0.259679 0.207609 28.5947 23.0535 806716 22.8124 200624 5.67327 143147 517766 456418331 103863687 0 0 1.08858e+08 20617.0 18 1675578 19868374 -1 13.9133 7.76735 -393376 -12.9133 0 0 36.17 -1 -1 1927.9 MiB 150.24 41.7265 34.527 1927.9 MiB -1 29.72 -3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1027.30 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2017832 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.1 MiB 179.29 547789 2661451 958041 1608713 94697 1789.9 MiB 260.36 2.34 27.0929 -106609 -26.0929 5.35183 0.06 0.27456 0.228129 29.5628 24.7422 829210 21.1447 207429 5.28940 184705 723383 1302091086 364260887 0 0 7.97022e+07 20563.0 18 1225854 14507865 -1 30.5677 6.54028 -121409 -29.5677 0 0 25.79 -1 -1 1868.9 MiB 503.91 43.0657 36.7123 1789.9 MiB -1 20.41 -3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 925.95 vpr 4.62 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4842080 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.6 MiB 147.82 619747 3698710 1495912 2184534 18264 4728.6 MiB 198.02 2.37 6.78648 -99082.3 -5.78648 3.44108 0.45 0.48725 0.430185 61.9462 54.5962 814845 11.7998 205031 2.96905 140099 173436 458459419 150453276 0 0 5.14406e+08 20769.0 14 7758968 93673935 -1 6.45787 3.53717 -145075 -5.45787 0 0 172.18 -1 -1 4728.6 MiB 193.32 83.1106 74.2663 4728.6 MiB -1 156.75 -3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 409.69 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1712060 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.6 MiB 131.22 276554 1921016 711963 1138812 70241 1598.4 MiB 145.73 1.42 195.512 -113504 -194.512 195.512 0.05 0.160338 0.134313 19.3452 16.1804 416656 14.7244 107078 3.78408 104021 334271 218912879 40948386 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 198.006 198.006 -143215 -197.006 0 0 22.05 -1 -1 1607.4 MiB 63.92 28.3971 24.123 1598.4 MiB -1 16.81 -3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 443.45 vpr 1.73 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1814380 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.5 MiB 110.53 271211 807295 220659 561442 25194 1771.9 MiB 87.02 0.90 15.8645 -293903 -14.8645 15.8645 0.07 0.137468 0.119486 13.9778 11.464 446897 16.5806 122453 4.54320 84683 217412 421161484 116638965 0 0 9.85096e+07 20574.3 19 1507654 17957159 -1 17.551 17.551 -341289 -16.551 0 0 33.12 -1 -1 1771.9 MiB 157.72 22.3148 18.7943 1771.9 MiB -1 26.51 -3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 141.26 vpr 1.24 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1296500 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.2 MiB 59.31 113956 557464 166863 359124 31477 1246.8 MiB 24.59 0.29 7.08326 -66257.5 -6.08326 7.08326 0.02 0.055314 0.0441799 5.26138 4.20946 182605 22.0804 50112 6.05949 29285 119606 66293828 12593582 0 0 3.14199e+07 20455.7 15 483264 5705245 -1 8.63522 8.63522 -90099.9 -7.63522 0 0 10.47 -1 -1 1246.8 MiB 20.00 8.06464 6.66092 1246.8 MiB -1 7.35 -3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 368.03 vpr 1.54 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1613076 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.2 MiB 152.28 248422 1517216 526978 905843 84395 1523.2 MiB 71.70 0.64 10.4991 -73576.7 -9.49906 4.26563 0.04 0.123293 0.0990031 12.7883 10.3856 402144 19.7974 109429 5.38714 60309 208858 232045575 52278765 0 0 6.09438e+07 20519.8 18 935204 11078823 -1 12.8865 4.78217 -92799.1 -11.8865 0 0 20.13 -1 -1 1523.2 MiB 81.81 19.2634 16.033 1523.2 MiB -1 15.82 -3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 464.20 vpr 2.35 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2461196 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.2 MiB 116.23 224613 2251244 886249 1326045 38950 2403.5 MiB 95.91 0.83 9.49151 -92147.5 -8.49151 9.49151 0.14 0.154631 0.123533 20.7936 16.7804 397126 20.1046 99400 5.03215 58343 180947 261415498 79896454 0 0 1.92002e+08 20596.6 16 2917968 35039980 -1 8.83504 8.83504 -160829 -7.83504 0 0 63.50 -1 -1 2403.5 MiB 101.27 28.5358 23.7007 2403.5 MiB -1 55.56 -3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 411.57 vpr 2.07 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2167564 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.7 MiB 93.64 225707 1580536 560957 948186 71393 2116.8 MiB 74.70 0.59 9.27529 -27528.6 -8.27529 3.13114 0.14 0.130328 0.10251 17.2693 13.6101 391848 18.4721 94302 4.44548 55624 156547 339484601 88142541 0 0 1.62738e+08 20641.5 16 2479452 29744051 -1 9.56018 3.68158 -50102.5 -8.56018 0 0 53.61 -1 -1 2116.8 MiB 117.38 23.7611 19.3642 2116.8 MiB -1 45.57 -3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 144.75 vpr 1.44 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1510544 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 46.50 89280 149036 37755 99315 11966 1475.1 MiB 9.68 0.11 5.67702 -19268.5 -4.67702 3.75675 0.06 0.0566391 0.0498904 5.10516 4.33648 154058 20.3861 37061 4.90419 20488 44948 78925296 21606068 0 0 7.26079e+07 20580.5 14 1120110 13214470 -1 5.90336 3.89257 -40281.1 -4.90336 0 0 23.32 -1 -1 1475.1 MiB 26.78 7.88124 6.86256 1475.1 MiB -1 16.54 -3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 359.04 vpr 1.78 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1871392 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1280.5 MiB 91.15 211809 2071451 692754 1236953 141744 1827.5 MiB 125.31 1.09 40.9771 -61336.3 -39.9771 40.9771 0.07 0.171234 0.145898 21.8018 18.6515 342831 13.2280 87296 3.36829 76962 231011 136781567 33406286 0 0 1.02587e+08 20566.7 22 1568252 18700371 -1 39.0683 39.0683 -66985.6 -38.0683 0 0 34.25 -1 -1 1827.5 MiB 47.65 31.738 27.5672 1827.5 MiB -1 27.89 -3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 229.59 vpr 1.79 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1876484 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1132.6 MiB 66.93 129881 1180703 418671 705083 56949 1832.5 MiB 43.61 0.38 9.05339 -27832.3 -8.05339 9.05339 0.11 0.0813991 0.0719295 9.16919 7.64919 190989 15.0279 45936 3.61445 31437 116923 44250090 9507104 0 0 1.22008e+08 20602.6 13 1871156 22275272 -1 9.68529 8.62738 -38151.5 -8.68529 0 0 40.96 -1 -1 1832.5 MiB 16.73 13.1394 11.2088 1832.5 MiB -1 34.19 -3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 497.04 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1795972 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.1 MiB 155.39 246824 1707517 542100 1124665 40752 1627.5 MiB 155.77 1.28 9.48565 -168709 -8.48565 9.48565 0.05 0.168989 0.135904 19.3486 15.5394 380234 10.6523 107944 3.02407 107615 274456 330281609 74151890 0 0 6.75216e+07 20523.3 18 1033138 12274942 -1 10.455 10.455 -199956 -9.45504 0 0 22.28 -1 -1 1670.4 MiB 111.91 28.4097 23.3845 1627.5 MiB -1 17.60 -3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 327.67 vpr 1.66 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1742392 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.0 MiB 84.58 151125 1190888 390352 769055 31481 1646.6 MiB 73.69 0.67 5.16253 -15574.5 -4.16253 4.57572 0.06 0.14295 0.12611 17.3522 14.6159 255867 10.6625 71175 2.96600 55302 103707 208615694 72938344 0 0 7.26079e+07 20580.5 15 1120110 13214470 -1 5.91719 5.91719 -30815.6 -4.91719 0 0 23.62 -1 -1 1646.6 MiB 95.34 24.5543 21.0784 1646.6 MiB -1 19.49 -3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 139.09 vpr 1.23 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1291272 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.0 MiB 49.80 156611 278120 76189 183016 18915 1261.0 MiB 18.22 0.20 5.5971 -16655.2 -4.5971 4.5816 0.03 0.0587051 0.0472882 5.12731 4.2098 232871 19.3688 64465 5.36181 56972 170063 109738115 20757776 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.60942 5.3536 -26554.6 -5.60942 0 0 10.35 -1 -1 1261.0 MiB 31.51 8.7766 7.46125 1261.0 MiB -1 6.22 -3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 468.75 vpr 1.78 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1866664 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1361.4 MiB 115.86 298766 2022878 721872 1209208 91798 1694.5 MiB 174.52 1.53 192.881 -65340.9 -191.881 192.881 0.06 0.202016 0.181173 25.4109 21.5614 461781 14.0963 121424 3.70658 122316 378159 341015575 70726261 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 198.296 198.296 -88522.8 -197.296 0 0 24.15 -1 -1 1743.6 MiB 98.43 37.004 31.8471 1694.5 MiB -1 19.45 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.67 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1237180 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1063.0 MiB 15.45 60926 230944 41654 173553 15737 1197.6 MiB 9.59 0.15 4.84629 -4259.39 -3.84629 2.46064 0.02 0.0310798 0.0251181 2.06236 1.71947 97856 7.86814 33858 2.72236 28683 39681 30714017 6195766 0 0 2.48366e+07 20391.3 17 382818 4502703 -1 5.05177 2.69405 -5674.91 -4.05177 0 0 8.19 -1 -1 1197.6 MiB 8.55 3.63438 3.14676 1197.6 MiB -1 4.10 -3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 544.98 vpr 2.19 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2300396 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.1 MiB 76.17 219742 1555886 562141 922870 70875 2246.5 MiB 103.91 1.05 7.36593 -33948.8 -6.36593 7.36593 0.16 0.106572 0.0952071 13.4562 11.2916 354299 17.3676 93322 4.57461 68078 159956 457518312 185590185 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.09599 7.40175 -42456.2 -7.09599 0 0 61.24 -1 -1 2246.5 MiB 222.11 18.7938 16.1322 2246.5 MiB -1 52.95 -3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 302.19 vpr 2.43 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2550728 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.8 MiB 47.82 130160 1380047 560321 782548 37178 2490.9 MiB 35.48 0.32 10.5854 -18606.9 -9.58537 4.72024 0.18 0.0600238 0.0497498 7.88269 6.58458 172969 20.2706 38383 4.49818 23174 90029 105109403 34944955 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 11.6218 5.22111 -24845.6 -10.6218 0 0 75.93 -1 -1 2490.9 MiB 48.99 10.7341 9.14711 2490.9 MiB -1 68.06 -3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 124.32 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1226084 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1058.1 MiB 67.46 76143 241243 58815 176856 5572 1192.4 MiB 11.31 0.19 7.29112 -42594.5 -6.29112 7.29112 0.02 0.0414227 0.0316342 2.95997 2.38508 119636 19.0382 33085 5.26496 19940 91849 40304260 7468528 0 0 2.39639e+07 20377.5 15 369794 4343188 -1 7.77921 7.77921 -50567.3 -6.77921 0 0 7.94 -1 -1 1192.4 MiB 12.02 5.00754 4.21584 1192.4 MiB -1 4.51 -3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 27.66 vpr 993.31 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1017148 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.6 MiB 6.88 10156 8194 784 6524 886 993.3 MiB 0.47 0.01 5.3048 -3531.01 -4.3048 4.2956 0.00 0.00511192 0.00432104 0.195587 0.167728 15985 11.0623 5210 3.60554 3642 8882 4445146 900786 0 0 4.97530e+06 19135.8 9 75766 878809 -1 5.28906 4.84614 -4691.92 -4.28906 0 0 1.76 -1 -1 993.3 MiB 1.25 0.451107 0.405755 993.3 MiB -1 0.36 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 334.95 vpr 1.65 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1735176 22 252 53001 29054 7 22943 1413 54 40 4320 DSP auto 1236.8 MiB 39.56 578922 193642 857421 247994 504680 104747 1694.5 MiB 48.13 0.42 9.17101 7.49087 -36142.8 -6.49087 3.19653 0.03 0.125295 0.104169 14.4295 12.058 338207 14.7618 86292 3.76640 66292 141868 450896868 183262088 0 0 8.89497e+07 20590.2 19 1365594 16211305 -1 7.56673 3.20701 -45359.7 -6.56673 0 0 17.56 -1 -1 1694.5 MiB 186.32 20.7375 17.6809 1694.5 MiB -1 23.62 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 229.90 vpr 1.51 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1586264 3 33 48977 39238 1 26189 1635 40 30 2400 LAB auto 1260.0 MiB 55.36 757873 257834 897039 257029 596223 43787 1458.1 MiB 74.24 0.63 88.3086 81.3317 -50053.5 -80.3317 81.3317 0.01 0.105146 0.0940116 13.4495 10.8945 432701 16.5248 116936 4.46576 99467 278823 244875822 51834154 0 0 4.91306e+07 20471.1 23 758110 8921656 -1 71.1894 71.1894 -102916 -70.1894 0 0 9.90 -1 -1 1494.0 MiB 58.04 20.5097 16.9797 1458.1 MiB -1 9.97 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 494.51 vpr 1.96 GiB 211 2281 3 210 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2056344 38 173 62892 59064 3 35490 2705 60 44 5280 M9K auto 1470.1 MiB 116.07 1 558842 1961961 687531 1237166 37264 1941.6 MiB 152.18 1.23 15.2717 11.52 -300506 -10.52 7.39565 0.05 0.236798 0.17913 26.1522 20.084 824365 23.2333 200032 5.63756 146563 541686 515541383 132244076 0 0 1.08858e+08 20617.0 19 1675578 19868374 -1 13.8006 7.7343 -390362 -12.8006 0 0 22.18 -1 -1 1941.6 MiB 149.83 37.4367 29.7549 1941.6 MiB -1 24.01 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 662.52 vpr 1.93 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2026664 4 570 66175 54803 2 39253 3378 51 38 3876 LAB auto 1498.9 MiB 100.63 1 538340 2663553 950678 1615590 97285 1811.8 MiB 189.07 1.51 33.2636 26.617 -103747 -25.617 4.66626 0.04 0.204109 0.182168 26.6617 21.2063 826051 21.0470 204139 5.20126 184571 733534 1066947846 281994208 0 0 7.97022e+07 20563.0 19 1225854 14507865 -1 29.0017 6.47485 -117845 -28.0017 0 0 16.59 -1 -1 1876.0 MiB 304.20 38.0144 31.0233 1811.8 MiB -1 22.95 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 974.86 vpr 4.62 GiB 40 3707 172 1 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 4843184 19 21 171111 96274 1 69189 3920 129 96 24768 DSP auto 2001.6 MiB 69.32 2 693471 3680425 1453106 2210247 17072 4729.7 MiB 146.15 1.30 6.26745 5.16452 -76724.7 -4.16452 2.59078 0.20 0.344722 0.312168 45.7424 39.8709 901905 13.0359 216953 3.13579 142016 174861 855691927 377239464 0 0 5.14406e+08 20769.0 10 7758968 93673935 -1 5.31158 3.88513 -129968 -4.31158 0 0 101.81 -1 -1 4729.7 MiB 487.76 58.3922 51.6098 4729.7 MiB -1 126.58 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 284.01 vpr 1.63 GiB 536 1945 7 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1713088 227 309 49176 40422 1 28286 2492 47 35 3290 io auto 1318.4 MiB 72.69 1 270518 1843284 652509 1144115 46660 1612.7 MiB 112.42 1.09 225.36 192.167 -108313 -191.167 192.167 0.02 0.148363 0.117332 17.6108 14.0433 406382 14.3689 104909 3.70939 100739 322484 200315606 38175430 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 196.52 196.52 -140707 -195.52 0 0 13.37 -1 -1 1612.7 MiB 46.00 25.1451 20.5144 1612.7 MiB -1 14.43 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 286.50 vpr 1.73 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1814284 3 33 52402 39411 1 26915 1592 57 42 4788 M9K auto 1285.8 MiB 60.43 876865 266910 800704 217304 559963 23437 1771.8 MiB 61.41 0.60 18.2161 15.0487 -283662 -14.0487 15.0487 0.03 0.110665 0.0983698 12.2775 9.72807 437688 16.2667 118184 4.39231 80387 205200 336070247 92235784 0 0 9.85096e+07 20574.3 20 1507654 17957159 -1 16.6851 16.6851 -328192 -15.6851 0 0 19.81 -1 -1 1771.8 MiB 101.20 19.235 15.792 1771.8 MiB -1 21.91 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 97.20 vpr 1.24 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1295424 55 196 20131 19956 1 8019 1227 32 24 1536 LAB auto 1107.6 MiB 34.37 223666 104762 559337 165202 365871 28264 1250.3 MiB 15.54 0.18 8.14098 6.99011 -68950.8 -5.99011 6.99011 0.01 0.0412032 0.0359422 5.27129 3.9879 170106 21.2208 45801 5.71370 28180 132530 75236077 14372313 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.3729 8.3729 -83722.3 -7.3729 0 0 6.22 -1 -1 1250.3 MiB 17.56 7.62394 6.01773 1250.3 MiB -1 5.04 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 384.18 vpr 1.54 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1619368 84 171 36458 36247 3 20790 2367 44 33 2904 LAB auto 1265.7 MiB 81.25 599300 249465 1358415 445363 846750 66302 1530.9 MiB 48.88 0.49 12.4149 9.90769 -70053.9 -8.90769 4.01156 0.02 0.125113 0.0930825 11.8346 9.00012 421592 20.2923 115009 5.53567 63988 231128 634239024 190371172 0 0 5.95688e+07 20512.7 14 914964 10827114 -1 12.3773 4.33722 -90025.8 -11.3773 0 0 12.02 -1 -1 1530.9 MiB 205.64 16.8356 13.2434 1530.9 MiB -1 12.70 +3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 364.66 vpr 2.35 GiB 69 2179 10 295 16 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2462692 36 33 57796 49182 1 19635 2569 79 59 9322 M144K auto 1407.8 MiB 61.04 687588 229258 2165770 799905 1343807 22058 2405.0 MiB 66.46 0.56 12.995 9.11916 -68399.8 -8.11916 9.11916 0.05 0.11569 0.101098 16.3766 13.1783 408880 20.8293 101695 5.18059 58162 198761 352431329 112609659 0 0 1.92002e+08 20596.6 16 2917968 35039980 -1 9.21014 9.21014 -149701 -8.21014 0 0 38.27 -1 -1 2405.0 MiB 126.74 22.5268 18.6422 2405.0 MiB -1 45.70 +3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 334.46 vpr 2.07 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2166380 202 276 35125 30509 3 21318 2020 73 54 7884 M9K auto 1221.1 MiB 49.26 782110 235668 1444352 491382 903107 49863 2115.6 MiB 47.98 0.37 9.52583 8.86655 -25610.5 -7.86655 2.99007 0.05 0.113388 0.0837706 13.9235 10.3647 409338 19.2069 95423 4.47743 56405 161834 452534869 126896454 0 0 1.62738e+08 20641.5 17 2479452 29744051 -1 9.06444 3.63902 -49136.6 -8.06444 0 0 32.05 -1 -1 2115.6 MiB 143.44 19.4196 15.1436 2115.6 MiB -1 38.29 +3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 93.02 vpr 1.44 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1509456 3 2 14862 10304 26 7561 466 49 36 3528 DSP auto 1055.2 MiB 18.70 184798 80217 134110 31670 91390 11050 1474.1 MiB 6.31 0.08 5.73048 5.557 -20016.6 -4.557 3.71419 0.02 0.0465293 0.0376548 3.66706 3.03776 144728 19.2074 35518 4.71374 19254 41730 71856535 20086137 0 0 7.26079e+07 20580.5 14 1120110 13214470 -1 5.72459 4.15885 -44268.6 -4.72459 0 0 14.02 -1 -1 1474.1 MiB 23.72 6.15974 5.26532 1474.1 MiB -1 12.92 +3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 241.71 vpr 1.78 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1867272 35 658 51416 37539 1 27424 2511 58 43 4988 io auto 1317.8 MiB 48.90 948323 227264 1964411 655805 1166964 141642 1823.5 MiB 85.85 0.67 49.8814 40.5997 -59715.9 -39.5997 40.5997 0.04 0.133507 0.12216 18.3999 15.2293 359668 13.8798 88521 3.41608 73222 220528 152022396 37203782 0 0 1.02587e+08 20566.7 20 1568252 18700371 -1 40.8996 40.8996 -65115.3 -39.8996 0 0 20.34 -1 -1 1823.5 MiB 39.38 26.0518 21.9742 1823.5 MiB -1 22.82 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 147.75 vpr 1.79 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1876732 13 740 25173 25306 1 12838 1890 63 47 5922 io auto 1156.9 MiB 35.93 511809 124272 1134850 394535 689272 51043 1832.7 MiB 28.51 0.25 10.849 8.55919 -26577.3 -7.55919 8.55919 0.03 0.0667231 0.0595066 7.86607 6.21979 187381 14.6038 45597 3.55366 31219 114564 45280930 9170650 0 0 1.22008e+08 20602.6 12 1871156 22275272 -1 8.85362 8.18245 -36071.1 -7.85362 0 0 23.97 -1 -1 1832.7 MiB 12.64 10.8902 8.85884 1832.7 MiB -1 26.57 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 296.29 vpr 1.73 GiB 117 2311 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1809912 79 38 66795 54922 1 35224 2428 47 35 3290 LAB auto 1382.3 MiB 92.47 1 244493 1601004 478977 1083677 38350 1655.1 MiB 108.35 0.97 13.2451 9.45262 -152441 -8.45262 9.45262 0.02 0.180003 0.141249 17.875 13.8444 383139 10.8781 107986 3.06595 89630 211664 136543668 29891467 0 0 6.75216e+07 20523.3 18 1033138 12274942 -1 10.5596 10.5596 -195977 -9.55964 0 0 13.38 -1 -1 1681.6 MiB 41.09 25.8122 20.6734 1655.1 MiB -1 14.63 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 193.20 vpr 1.66 GiB 213 1559 26 4 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1739984 139 74 57121 41054 1 23901 1802 49 36 3528 DSP auto 1330.9 MiB 45.46 523367 143054 1119824 339931 747988 31905 1653.1 MiB 46.98 0.41 5.50142 5.05519 -14801.7 -4.05519 4.55656 0.03 0.111545 0.100323 13.4118 10.9396 233997 9.79190 63575 2.66038 54368 101664 139712299 42351509 0 0 7.26079e+07 20580.5 19 1120110 13214470 -1 5.90983 5.90983 -28470.6 -4.90983 0 0 14.30 -1 -1 1653.1 MiB 48.30 19.8642 16.6405 1653.1 MiB -1 14.85 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 101.42 vpr 1.22 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1279356 2 52 16673 16662 2 11970 759 32 24 1536 M9K auto 1087.6 MiB 26.11 316622 152696 263719 67846 176857 19016 1238.4 MiB 13.70 0.18 6.37147 5.42709 -16155.6 -4.42709 4.492 0.01 0.0855605 0.0661458 5.59717 4.06858 233040 19.4752 63998 5.34832 55775 171602 116320989 22499207 0 0 3.14199e+07 20455.7 18 483264 5705245 -1 6.05833 5.08903 -23533.3 -5.05833 0 0 6.36 -1 -1 1238.4 MiB 29.49 8.83367 6.8784 1238.4 MiB -1 6.59 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 292.25 vpr 1.77 GiB 445 2154 19 52 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1857400 131 314 57881 45152 1 32883 2670 49 36 3528 DSP auto 1413.6 MiB 63.48 1 297270 2002290 694221 1220745 87324 1700.3 MiB 124.60 1.21 225.053 189.331 -63929.8 -188.331 189.331 0.09 0.21317 0.174938 22.1816 17.9981 462294 14.0918 121369 3.69960 100939 303602 159579775 32291150 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 192.009 192.009 -84741.7 -191.009 0 0 14.68 -1 -1 1735.5 MiB 40.29 31.8982 26.4487 1700.3 MiB -1 21.53 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 44.47 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1236332 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1077.5 MiB 8.12 181772 60454 212839 35803 162171 14865 1200.7 MiB 6.20 0.10 5.037 4.84997 -4107.52 -3.84997 2.38954 0.01 0.0265953 0.0205781 1.71761 1.36841 96083 7.59910 31864 2.52009 28520 38733 28269527 5661726 0 0 2.48366e+07 20391.3 15 382818 4502703 -1 4.9803 2.58263 -5331.74 -3.9803 0 0 4.91 -1 -1 1200.7 MiB 6.11 2.96918 2.47893 1200.7 MiB -1 3.15 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 329.98 vpr 2.19 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2299956 542 422 37277 26038 1 20404 2145 78 58 9048 io auto 1179.3 MiB 39.88 750296 213881 1564709 559535 935357 69817 2246.1 MiB 69.17 0.63 9.1469 7.11198 -32381.7 -6.11198 7.11198 0.08 0.0974836 0.0779271 11.5163 9.28631 341769 16.7526 89371 4.38072 60396 139032 295235636 115037667 0 0 1.86852e+08 20651.1 18 2837414 34147767 -1 7.84316 7.84316 -40742.7 -6.84316 0 0 37.49 -1 -1 2246.1 MiB 117.77 16.1021 13.3782 2246.1 MiB -1 43.62 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 211.58 vpr 2.43 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2549800 403 704 15490 16194 1 8443 1837 88 65 11440 io auto 1076.7 MiB 26.61 420969 124674 1306373 513997 754918 37458 2490.0 MiB 21.13 0.19 12.456 10.0834 -15995.3 -9.08343 4.54503 0.06 0.0524896 0.0408569 6.33274 5.00588 170906 20.2447 36943 4.37610 23908 97711 100577096 33451296 0 0 2.36204e+08 20647.2 14 3590540 43137666 -1 11.8824 5.51915 -23728.3 -10.8824 0 0 46.41 -1 -1 2490.0 MiB 40.76 8.49023 6.9148 2490.0 MiB -1 56.37 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 74.16 vpr 1.17 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1222316 18 17 16969 16357 1 6487 772 28 21 1176 LAB auto 1071.6 MiB 34.98 163040 70478 237952 59222 174028 4702 1189.2 MiB 8.18 0.11 8.63391 7.28108 -38373.3 -6.28108 7.28108 0.01 0.0359793 0.0322549 3.04189 2.44357 109926 16.9560 30088 4.64106 17978 72156 23692991 4307201 0 0 2.39639e+07 20377.5 18 369794 4343188 -1 7.70533 7.70533 -42097.5 -6.70533 0 0 4.95 -1 -1 1189.2 MiB 6.63 5.04612 4.213 1189.2 MiB -1 3.26 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 19.87 vpr 996.40 MiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1020316 18 17 2291 2142 1 1462 118 13 10 260 LAB auto 957.9 MiB 3.90 13715 9496 7921 840 6234 847 996.4 MiB 0.32 0.01 5.34371 5.29372 -3553.58 -4.29372 4.35136 0.00 0.00350229 0.00303545 0.139546 0.120047 16149 11.0685 5505 3.77313 3716 8872 3987965 814573 0 0 4.97530e+06 19135.8 10 75766 878809 -1 5.46481 4.6943 -4312.85 -4.46481 0 0 1.11 -1 -1 996.4 MiB 0.84 0.330704 0.297098 996.4 MiB -1 0.23 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt index 37bf9a4b00b..38d2cb49a09 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt @@ -1,23 +1,23 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 5977.17 vpr 18.15 GiB 373 16802 116 5043 16 0 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan 19027644 178 195 583584 0 2 400505 22350 450 333 149850 -1 titan_extra_large -1 -1 8 13800219 48167472 20323894 27731780 111798 18581.7 MiB 4325.24 9.70 -1 -1 -1 -1 -1 -1 0 0 0 0 14590895 36.4326 2750092 6.86682 839764 1658253 951523382 215783707 0 0 2.82057e+09 18822.7 11 43073670 476336488 -1 -1 -1 -1 -1 -1 -1 786.18 -1 -1 18581.7 MiB 264.68 0 0 18581.7 MiB -1 431.81 -stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6231.23 vpr 12.33 GiB 446 31279 112 1175 0 2 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 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sparcT1_core_stratixiv_arch_timing.blif common 593.70 vpr 2.30 GiB 310 4048 1 127 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 2408112 173 137 91964 0 1 52595 4486 100 74 7400 -1 titan_extra_small -1 -1 1 701026 3665704 1199971 2414430 51303 2342.3 MiB 507.92 0.94 -1 -1 -1 -1 -1 -1 0 0 0 0 933577 17.7516 222529 4.23131 115794 398921 86466898 16450293 0 0 1.36295e+08 18418.2 10 2149958 23360463 -1 -1 -1 -1 -1 -1 -1 23.07 -1 -1 2342.7 MiB 21.26 0 0 2342.3 MiB -1 15.04 +stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 2428.42 vpr 6.32 GiB 451 14815 0 260 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6622024 239 212 299957 0 1 174676 15526 225 167 37575 -1 titan_medium -1 -1 8 3000892 22279641 8949040 13229480 101121 6466.8 MiB 2086.27 5.15 -1 -1 -1 -1 -1 -1 0 0 0 0 3694237 21.1496 850013 4.86634 392535 1469224 301011264 53478430 0 0 6.95906e+08 18520.5 11 10840348 119192345 -1 -1 -1 -1 -1 -1 -1 118.82 -1 -1 6466.8 MiB 75.27 0 0 6466.8 MiB -1 80.99 +stratixiv_arch.timing.xml stap_qrd_stratixiv_arch_timing.blif common 1555.59 vpr 5.68 GiB 150 16236 75 553 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 5958512 68 82 237991 0 1 132235 17014 225 167 37575 -1 titan_medium -1 -1 4 1577017 32169883 12567240 19371382 231261 5818.9 MiB 1258.31 3.41 -1 -1 -1 -1 -1 -1 0 0 0 0 1918789 14.5267 433717 3.28357 242067 559136 213519358 50500725 0 0 6.95906e+08 18520.5 9 10840348 119192345 -1 -1 -1 -1 -1 -1 -1 116.17 -1 -1 5818.9 MiB 47.24 0 0 5818.9 MiB -1 85.73 +stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 384.55 vpr 2.93 GiB 506 3281 77 113 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 3067304 172 334 94412 0 3 58023 3977 150 111 16650 -1 titan_small -1 -1 727715 437837 2933105 904764 1973968 54373 2995.4 MiB 262.89 0.38 -1 -1 -1 -1 -1 -1 0 0 0 0 500495 8.62670 115929 1.99819 109749 157743 47396298 10426845 0 0 3.08275e+08 18515.0 8 4815530 52742011 -1 -1 -1 -1 -1 -1 -1 50.78 -1 -1 2995.4 MiB 10.64 0 0 2995.4 MiB -1 34.16 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt index 718952957d1..eceaa56b4b1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt @@ -1,17 +1,17 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 430.27 vpr 7.22 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7572608 22 252 53001 29054 7 22984 1419 89 66 5874 DSP auto 2999.7 MiB 77.55 248316 1021579 298715 629192 93672 3552.4 MiB 75.43 0.60 7.79847 -44076.4 -6.79847 3.16357 0.04 0.145495 0.126331 19.1685 16.7404 337990 6.38090 73939 1.39589 113486 262947 123939600 20677912 0 0 1.48102e+08 25213.2 18 3168173 32237029 53333 8.13811 2.93957 -42084.8 -7.13811 0 0 30.24 37.78 22.78 7394.9 MiB 150.02 24.6012 21.633 3552.4 MiB 61.30 11.40 -stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 423.49 vpr 6.82 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7148500 3 33 48977 39238 1 26095 1641 54 40 2160 LAB auto 3019.2 MiB 103.15 286068 978816 295772 657268 25776 3171.0 MiB 80.85 0.83 87.9237 -89444.7 -86.9237 87.9237 0.02 0.133548 0.111652 14.7315 12.3725 377246 7.70314 89630 1.83019 136470 456181 107134305 13321542 0 0 5.45421e+07 25251.0 24 2489089 26482784 65639 72.0152 72.0152 -145316 -71.0152 0 0 10.89 30.08 16.61 6981.0 MiB 142.54 20.844 17.5112 3143.2 MiB 62.59 3.96 -stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 711.87 vpr 7.51 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7875556 4 570 66175 54803 2 39221 3376 91 67 6097 io auto 3239.4 MiB 185.13 637050 2737396 996225 1655508 85663 3733.5 MiB 161.80 1.29 31.0835 -120493 -30.0835 7.14678 0.06 0.211633 0.187447 26.5121 22.2855 899864 13.5993 200525 3.03045 250269 1330369 403832098 58432790 0 0 1.53687e+08 25207.0 23 4527063 53934418 131001 31.4743 7.04434 -123107 -30.4743 0 0 31.82 48.91 25.68 7690.6 MiB 229.13 35.3927 29.9033 3733.5 MiB 54.44 12.02 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 490.17 vpr 7.44 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7802588 3 33 52402 39411 1 26961 1588 73 54 3942 M9K auto 3038.9 MiB 115.22 308817 862861 247827 593176 21858 3344.5 MiB 70.28 0.75 18.2872 -344515 -17.2872 18.2872 0.04 0.144193 0.116967 14.4383 11.7329 388387 7.41281 89501 1.70823 127828 482181 86633732 10962711 0 0 9.96402e+07 25276.6 23 3049699 30612935 82279 18.1508 18.1508 -339276 -17.1508 0 0 19.96 46.42 29.95 7619.5 MiB 155.40 20.4894 16.7826 3344.5 MiB 62.62 7.54 -stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 264.87 vpr 6.35 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6658268 55 196 20131 19956 1 8273 1224 44 33 1452 io auto 2885.6 MiB 59.05 121891 590184 190135 382049 18000 3003.9 MiB 21.76 0.23 8.00991 -79285.3 -7.00991 8.00991 0.01 0.0550621 0.0436789 5.54087 4.43725 168265 8.35975 39603 1.96756 52203 214680 35422307 3611930 0 0 3.65459e+07 25169.4 13 1361186 16140321 53661 8.2494 8.2494 -80319.6 -7.2494 0 0 7.63 18.91 10.40 6502.2 MiB 101.02 6.87899 5.53912 2972.4 MiB 65.45 3.08 -stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 461.02 vpr 6.99 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7325496 84 171 36458 36247 3 20327 2406 62 46 2852 LAB auto 3026.4 MiB 149.19 282856 1613906 577988 956437 79481 3228.2 MiB 60.47 0.55 12.7635 -89890.6 -11.7635 4.81564 0.03 0.118349 0.0946709 13.1884 10.6839 385220 10.5702 85805 2.35443 120726 551439 87035965 8547461 0 0 7.20342e+07 25257.4 15 2649463 32096142 68009 12.7106 4.59591 -89170.4 -11.7106 0 0 14.69 35.95 19.46 7153.8 MiB 138.86 16.8557 13.6644 3228.2 MiB 62.61 5.90 -stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 536.44 vpr 7.68 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 8052732 202 276 35125 30509 3 21219 2016 106 79 8374 M9K auto 2979.7 MiB 92.45 275268 1593266 551386 986614 55266 3817.0 MiB 63.87 0.46 9.2665 -49067 -8.2665 3.57275 0.06 0.128588 0.0997349 17.2665 13.8123 330934 9.42322 69644 1.98309 96626 409213 76592480 17612840 0 0 2.11296e+08 25232.4 22 3960168 43100363 65824 7.92317 3.74791 -72552.8 -6.92317 0 0 43.69 57.06 35.19 7864.0 MiB 168.53 22.5205 18.1449 3817.0 MiB 63.34 20.57 -stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 316.30 vpr 6.89 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7222344 3 2 14862 10304 26 7583 476 89 66 5874 DSP auto 2832.3 MiB 45.71 124138 182462 49732 129080 3650 3434.9 MiB 11.57 0.11 5.88079 -31819.8 -4.88079 4.5134 0.05 0.0575387 0.0481419 6.23293 5.24991 151302 10.1983 29977 2.02056 41602 169090 28196463 3392334 0 0 1.48102e+08 25213.2 14 2293667 23918971 38105 5.43555 4.34297 -36900.7 -4.43555 0 0 31.66 30.81 19.91 7053.1 MiB 114.27 8.0475 6.8139 3434.9 MiB 67.70 13.08 -stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 542.79 vpr 7.40 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7764172 35 658 51416 37539 1 27427 2531 108 80 8640 io auto 3075.8 MiB 93.41 241934 2243861 754419 1344439 145003 3917.1 MiB 110.58 0.77 41.8615 -66574.8 -40.8615 41.8615 0.09 0.160304 0.137258 23.4482 20.061 335308 6.71879 78438 1.57171 166276 681051 158387837 20955778 0 0 2.18142e+08 25247.9 25 4407721 50162159 84809 37.8945 37.8945 -63952.6 -36.8945 0 0 44.15 46.45 23.73 7582.2 MiB 178.57 31.4578 26.962 3917.1 MiB 63.71 20.46 -stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 387.65 vpr 7.01 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7354908 13 740 25173 25306 1 12716 1903 117 87 10179 io auto 2928.2 MiB 67.88 151917 1239643 452352 735278 52013 3981.2 MiB 35.57 0.31 9.32912 -33745.1 -8.32912 8.97758 0.07 0.0799309 0.0699705 9.04546 7.55642 187992 7.47008 41392 1.64476 64808 295441 45317315 4493718 0 0 2.57088e+08 25256.7 13 4146271 46119125 60560 9.51895 7.86886 -41989.5 -8.51895 0 0 53.18 36.15 16.47 7182.2 MiB 123.92 11.2875 9.41327 3981.2 MiB 65.19 23.64 -stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 286.07 vpr 6.67 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6992700 2 52 16673 16662 2 12027 760 37 27 999 LAB auto 2863.8 MiB 48.35 185817 260785 68816 184545 7424 2969.0 MiB 17.52 0.22 6.43593 -22019.6 -5.43593 5.34219 0.01 0.0671365 0.0537497 5.45437 4.46867 243748 14.6228 55949 3.35647 70980 378754 80104321 9851562 0 0 2.50403e+07 25065.4 18 1109643 11618783 35248 6.97929 5.65113 -27162.3 -5.97929 0 0 5.11 17.57 11.32 6828.4 MiB 118.26 7.83981 6.43355 2903.7 MiB 66.65 1.88 -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 191.95 vpr 6.21 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6512136 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 2859.5 MiB 15.81 72155 253216 50624 190930 11662 2954.0 MiB 12.28 0.16 5.18599 -5515.92 -4.18599 2.85104 0.01 0.0356803 0.031132 2.85133 2.36966 82362 3.13247 19973 0.759632 54490 69977 15062795 1948535 0 0 2.84316e+07 25138.5 15 1246468 12354669 14284 3.84664 2.85129 -5700.97 -2.84664 0 0 5.78 12.08 6.10 6359.5 MiB 88.58 3.91742 3.26807 2899.6 MiB 66.17 2.25 -stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 545.23 vpr 7.47 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7832592 542 422 37277 26038 1 20403 2136 147 109 16023 io auto 2946.3 MiB 79.74 272838 1734636 659517 1007756 67363 4655.4 MiB 94.94 0.83 8.43041 -42423.1 -7.43041 8.08995 0.12 0.108337 0.0956704 15.1499 12.7644 351764 9.43725 76208 2.04454 89867 266535 93690673 14464239 0 0 4.05150e+08 25285.5 17 5915256 66794449 49681 8.39022 7.49893 -50294.9 -7.39022 0 0 83.08 50.78 21.66 7649.0 MiB 158.81 18.8518 16.0306 4655.4 MiB 64.94 40.50 -stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 445.21 vpr 7.31 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7666364 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 2857.1 MiB 56.44 187193 1324022 523278 764997 35747 5137.0 MiB 26.81 0.24 12.7682 -23323.6 -11.7682 6.27217 0.15 0.0586464 0.0483811 7.15433 5.97963 227077 14.6605 37744 2.43683 40915 222692 34388107 3312547 0 0 5.23918e+08 25300.3 17 6721105 74589014 36638 11.3367 5.96529 -32928.6 -10.3367 0 0 108.17 38.65 9.61 7486.7 MiB 125.03 9.2614 7.7773 5137.0 MiB 64.95 52.28 -stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 247.80 vpr 6.23 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6530136 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 2855.4 MiB 65.95 84377 244832 62116 178083 4633 2954.7 MiB 10.90 0.16 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0380001 0.0324758 3.26975 2.63245 117354 6.91742 28009 1.65099 42731 188939 30663841 3241611 0 0 2.84316e+07 25138.5 16 1092397 12303174 43762 7.24996 7.24996 -46266.9 -6.24996 0 0 5.81 13.06 7.12 6376.9 MiB 93.57 4.60783 3.72572 2904.9 MiB 65.30 2.17 -stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 143.49 vpr 5.89 GiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6175112 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 2752.7 MiB 6.96 10189 9390 1103 7334 953 2822.6 MiB 0.78 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00661338 0.00538061 0.265542 0.227477 13189 5.76442 3423 1.49607 7406 28929 4207039 458732 0 0 4.71840e+06 24575.0 16 154367 1513720 4558 4.32353 4.32353 -3831.79 -3.32353 0 0 1.05 2.34 1.56 6030.2 MiB 71.16 0.476743 0.411197 2791.2 MiB 66.66 0.13 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 307.76 vpr 7.22 GiB 274 1042 36 59 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7570660 22 252 53001 29054 7 22943 1413 89 66 5874 DSP auto 3091.9 MiB 38.56 785441 248898 952533 277008 615830 59695 3553.0 MiB 58.72 0.42 11.048 8.33765 -44315.5 -7.33765 3.31053 0.05 0.113159 0.101872 15.1213 12.8155 335814 6.33982 72558 1.36982 112366 258577 120602969 20086295 0 0 1.48102e+08 25213.2 22 3167005 32167053 52611 8.18405 2.97937 -42387.2 -7.18405 0 0 17.95 20.24 13.22 7393.2 MiB 105.27 20.5108 17.3765 3553.0 MiB 45.06 11.83 +stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 295.25 vpr 6.82 GiB 36 1580 9 10 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7146600 3 33 48977 39238 1 26189 1635 54 40 2160 LAB auto 3111.9 MiB 55.69 913357 292251 954807 280946 652655 21206 3167.9 MiB 64.31 0.69 102.633 87.8923 -93476.3 -86.8923 87.8923 0.01 0.121167 0.109007 12.9627 10.3995 392169 8.00786 92776 1.89443 131896 428998 101231115 12788547 0 0 5.45421e+07 25251.0 22 2488874 26464161 65179 72.6371 72.6371 -155945 -71.6371 0 0 6.58 15.88 9.56 6979.1 MiB 97.37 18.0468 14.5179 3126.4 MiB 44.79 3.09 +stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 613.29 vpr 7.51 GiB 574 2788 16 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7873588 4 570 66175 54803 2 39253 3378 91 67 6097 io auto 3351.8 MiB 97.41 2 646400 2739558 982870 1670046 86642 3736.8 MiB 161.18 1.35 58.3021 30.6995 -120781 -29.6995 6.48152 0.04 0.227064 0.202621 28.3082 22.6242 933895 14.1136 207960 3.14281 243517 1313252 476687912 77203454 0 0 1.53687e+08 25207.0 24 4526159 53918290 131473 29.867 6.58528 -125533 -28.8671 0 0 19.50 30.20 17.91 7689.1 MiB 239.13 39.9958 32.2561 3736.8 MiB 46.13 13.16 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 343.46 vpr 7.45 GiB 36 1395 8 151 2 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7809824 3 33 52402 39411 1 26915 1592 74 55 4070 M9K auto 3137.9 MiB 60.29 1 313744 856456 241378 601294 13784 3367.6 MiB 56.98 0.53 26.6374 18.392 -352998 -17.392 18.392 0.03 0.127652 0.0989751 13.2638 10.4714 393956 7.51911 89554 1.70924 123845 444274 79417493 9945038 0 0 1.02834e+08 25266.3 24 3087425 31058302 82003 18.2351 18.2351 -353089 -17.2351 0 0 12.20 24.60 16.53 7626.8 MiB 102.44 19.149 15.2376 3367.6 MiB 43.75 6.15 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 191.30 vpr 6.35 GiB 251 958 1 17 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6654744 55 196 20131 19956 1 8019 1227 44 33 1452 io auto 2959.2 MiB 34.98 264174 123065 585601 181370 380069 24162 3001.9 MiB 14.48 0.15 11.4541 8.37477 -85221.8 -7.37477 8.37477 0.01 0.0435657 0.0381802 4.91609 3.72033 171879 8.53930 40193 1.99687 53315 220453 36996311 3799813 0 0 3.65459e+07 25169.4 17 1360469 16108772 53595 8.25592 8.25592 -83672.5 -7.25592 0 0 4.49 10.24 6.25 6498.8 MiB 73.99 7.12109 5.46457 2962.2 MiB 47.31 2.36 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 321.12 vpr 6.98 GiB 255 2083 1 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7315800 84 171 36458 36247 3 20790 2367 61 45 2745 LAB auto 3120.3 MiB 80.93 720648 283198 1531863 524079 936471 71313 3240.9 MiB 53.41 0.48 18.575 13.0627 -93585.1 -12.0627 4.74826 0.02 0.135818 0.102003 15.2067 11.7347 383302 10.5176 85503 2.34615 122093 565734 90030158 8803236 0 0 6.93753e+07 25273.3 15 2618803 31747680 67913 12.8798 4.63258 -92475 -11.8798 0 0 8.61 19.57 11.78 7144.3 MiB 97.12 19.0364 14.7691 3240.9 MiB 46.87 5.47 +stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 384.22 vpr 7.68 GiB 478 1237 1 300 4 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 8054852 202 276 35125 30509 3 21318 2020 106 79 8374 M9K auto 3074.5 MiB 51.00 986671 267666 1508172 523381 949193 35598 3817.7 MiB 47.09 0.37 11.3759 9.26548 -48475.6 -8.26548 3.33529 0.04 0.124097 0.0915348 15.1053 11.4683 328144 9.34377 68354 1.94635 96064 399914 79957226 23499170 0 0 2.11296e+08 25232.4 21 3960955 43098624 64956 7.95847 3.473 -71149.3 -6.95847 0 0 26.34 31.74 20.98 7866.1 MiB 120.27 19.7897 15.1067 3817.7 MiB 46.45 15.33 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 209.11 vpr 6.86 GiB 5 323 31 105 0 2 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7192244 3 2 14862 10304 26 7561 466 89 66 5874 DSP auto 2906.5 MiB 19.29 270018 117214 172036 45994 123462 2580 3432.3 MiB 8.33 0.08 9.28243 6.01869 -39114.1 -5.01869 4.08518 0.03 0.0454291 0.0406349 5.15593 4.32319 142371 9.59632 28892 1.94743 41759 169140 29445405 3626320 0 0 1.48102e+08 25213.2 15 2293067 23897973 38057 4.93599 4.08638 -46486.1 -3.93599 0 0 18.14 15.12 10.24 7023.7 MiB 70.97 6.81564 5.74588 3432.3 MiB 44.34 9.65 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 373.15 vpr 7.40 GiB 693 1777 25 16 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7755920 35 658 51416 37539 1 27424 2511 108 80 8640 io auto 3164.2 MiB 50.50 1 251917 2152071 724984 1286743 140344 3911.0 MiB 82.56 0.70 74.2949 42.7394 -67262.7 -41.7394 42.7394 0.07 0.162863 0.131205 20.6635 16.9624 352057 7.05454 81260 1.62829 152474 598323 166291976 23812913 0 0 2.18142e+08 25247.9 24 4403936 50039004 85327 39.992 39.992 -64895.1 -38.992 0 0 26.33 24.60 14.40 7574.1 MiB 123.27 27.3283 22.5689 3911.0 MiB 44.86 15.47 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 273.02 vpr 7.01 GiB 753 1100 5 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7350572 13 740 25173 25306 1 12838 1890 117 87 10179 io auto 3006.8 MiB 37.42 599292 157888 1216610 423982 737752 54876 3977.7 MiB 30.17 0.24 14.8829 8.76456 -34576 -7.76456 8.70409 0.05 0.0816179 0.061816 10.1241 8.14491 194824 7.74156 42136 1.67432 66192 303102 47030761 4682931 0 0 2.57088e+08 25256.7 12 4146225 46138065 61038 9.03984 7.63094 -42209.6 -8.03984 0 0 32.63 17.95 9.14 7177.9 MiB 81.09 12.1021 9.70391 3977.7 MiB 45.61 23.31 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 200.36 vpr 6.67 GiB 54 664 0 40 0 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6988952 2 52 16673 16662 2 11970 759 37 27 999 LAB auto 2939.6 MiB 26.52 329275 182496 253339 66599 180853 5887 2975.1 MiB 13.24 0.15 8.48983 6.31912 -21812.1 -5.31912 5.08034 0.00 0.0629579 0.0470018 5.79269 4.52835 240918 14.4531 55334 3.31958 72352 385020 82634034 10266678 0 0 2.50403e+07 25065.4 19 1109231 11603273 35282 6.63264 5.37296 -26077.9 -5.63264 0 0 3.16 9.01 5.97 6825.1 MiB 80.01 7.98711 6.27754 2941.1 MiB 45.18 1.43 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 138.01 vpr 6.21 GiB 42 749 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6510184 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 2927.9 MiB 8.63 231619 75107 234775 43541 180854 10380 2952.5 MiB 7.46 0.10 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.01 0.0337965 0.0307351 2.48103 2.06348 86091 3.27429 21138 0.803940 55083 69816 15088501 1963151 0 0 2.84316e+07 25138.5 14 1246298 12345793 14184 3.88416 2.98764 -5833.91 -2.88416 0 0 3.69 6.67 3.76 6357.2 MiB 59.58 3.41906 2.82928 2931.6 MiB 45.54 1.83 +stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 346.89 vpr 7.47 GiB 964 1128 19 34 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7832876 542 422 37277 26038 1 20404 2145 147 109 16023 io auto 3028.2 MiB 42.13 995805 278436 1702989 641501 993647 67841 4655.2 MiB 55.90 0.45 15.3312 8.52855 -42700.6 -7.52855 8.52855 0.08 0.0906128 0.0733202 12.1681 9.84201 356776 9.57171 77090 2.06820 91226 273124 91865170 14105223 0 0 4.05150e+08 25285.5 18 5916678 66826775 49123 8.38836 8.09375 -49929.1 -7.38836 0 0 48.82 24.65 12.08 7648.9 MiB 99.97 15.4125 12.5496 4655.2 MiB 43.04 30.94 +stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 299.76 vpr 7.31 GiB 1107 730 0 0 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 7664032 403 704 15490 16194 1 8443 1837 167 124 20708 io auto 2928.3 MiB 31.79 580890 183895 1261389 465912 759977 35500 5134.5 MiB 17.64 0.16 21.2837 12.8498 -23740.4 -11.8498 6.01594 0.10 0.0512241 0.0393914 5.96074 4.75489 219953 14.2006 37215 2.40267 39483 211384 32469655 3103625 0 0 5.23918e+08 25300.3 17 6721158 74643089 37962 12.6526 5.87741 -32674.5 -11.6526 0 0 66.37 18.22 5.91 7484.0 MiB 79.20 7.59275 6.10237 5134.5 MiB 45.29 41.40 +stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 160.44 vpr 6.23 GiB 35 731 0 6 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6528224 18 17 16969 16357 1 6487 772 39 29 1131 LAB auto 2925.7 MiB 35.22 189359 78593 245032 60572 181809 2651 2959.4 MiB 7.11 0.10 11.1993 7.7388 -41982.4 -6.7388 7.7388 0.00 0.0307985 0.0270914 2.63105 2.05162 107149 6.31589 25659 1.51247 41788 165445 26862215 2865069 0 0 2.84316e+07 25138.5 14 1092494 12305361 43638 7.36438 7.36438 -43648.4 -6.36438 0 0 3.64 6.84 4.06 6375.2 MiB 59.12 3.5915 2.81489 2928.7 MiB 43.15 1.47 +stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 106.51 vpr 5.89 GiB 35 75 0 8 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 6171076 18 17 2291 2142 1 1462 118 16 12 192 LAB M9K auto 2808.7 MiB 4.24 14517 10381 9366 1088 7475 803 2819.8 MiB 0.57 0.01 5.48653 5.31416 -4115.07 -4.31416 4.57209 0.00 0.00439936 0.00390185 0.191396 0.163419 13233 5.78365 3460 1.51224 7262 27758 4096440 441394 0 0 4.71840e+06 24575.0 14 154247 1512402 4624 4.15021 4.15021 -3988.57 -3.15021 0 0 0.67 1.23 0.84 6026.4 MiB 47.88 0.339888 0.292276 2809.1 MiB 45.05 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt index f0282e9bf5e..3d0cf31dbb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_k6_frac_N8_22nm.xml single_wire.v common 1.34 vpr 75.71 MiB -1 -1 0.07 20608 1 0.01 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 0 3 75.7 MiB 0.48 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.40 1.4684e-05 9.512e-06 8.1482e-05 5.6821e-05 75.7 MiB 0.48 75.7 MiB 0.07 8 16 1 6.79088e+06 0 166176. 575.005 0.15 0.000912133 0.000836449 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.000776852 0.0007249 - fixed_k6_frac_N8_22nm.xml single_ff.v common 1.51 vpr 75.95 MiB -1 -1 0.08 20852 1 0.02 -1 -1 33716 -1 -1 1 2 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 24 9 1 1 7 76.0 MiB 0.47 0.00 0.930505 0.74674 -1.43836 -0.74674 0.74674 0.39 1.1513e-05 7.851e-06 8.3564e-05 6.0773e-05 76.0 MiB 0.47 76.0 MiB 0.07 20 31 1 6.79088e+06 13472 414966. 1435.87 0.24 0.000928712 0.000851847 22510 95286 -1 32 1 2 2 231 42 0.74674 0.74674 -1.43836 -0.74674 0 0 503264. 1741.40 0.03 0.00 0.08 -1 -1 0.03 0.000833737 0.000775898 - fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 2.74 vpr 76.62 MiB -1 -1 0.26 22392 3 0.07 -1 -1 37308 -1 -1 67 99 1 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78456 99 130 240 229 1 225 297 17 17 289 -1 unnamed_device -1 -1 978 866 19107 2257 1105 15745 76.6 MiB 0.61 0.00 2.26688 1.84068 -122.242 -1.84068 1.84068 0.39 0.000595647 0.000527536 0.0138425 0.0123349 76.6 MiB 0.61 76.6 MiB 0.13 34 1974 43 6.79088e+06 1.45062e+06 618332. 2139.56 0.79 0.175076 0.154945 25102 150614 -1 1739 14 569 895 60631 18120 2.0466 2.0466 -143.082 -2.0466 -0.04337 -0.04337 787024. 2723.27 0.04 0.03 0.13 -1 -1 0.04 0.0355147 0.0319235 - fixed_k6_frac_N8_22nm.xml diffeq1.v common 9.26 vpr 78.62 MiB -1 -1 0.36 26868 15 0.31 -1 -1 37472 -1 -1 47 162 0 5 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 80512 162 96 817 258 1 691 310 17 17 289 -1 unnamed_device -1 -1 7341 6689 25462 269 7038 18155 78.6 MiB 1.27 0.01 22.1608 21.0485 -1573.19 -21.0485 21.0485 0.38 0.00201699 0.00177192 0.0590804 0.052726 78.6 MiB 1.27 78.6 MiB 0.26 54 12827 26 6.79088e+06 2.61318e+06 949917. 3286.91 5.15 0.794403 0.715337 28846 232421 -1 11184 19 3449 7611 967200 252634 20.9913 20.9913 -1571.36 -20.9913 0 0 1.17392e+06 4061.99 0.06 0.26 0.21 -1 -1 0.06 0.158612 0.144189 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_k6_frac_N8_22nm.xml single_wire.v common 1.14 vpr 73.91 MiB -1 -1 0.06 17288 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75684 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 0 3 73.9 MiB 0.33 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.24 6.545e-06 3.49e-06 5.3077e-05 3.5069e-05 73.9 MiB 0.33 73.9 MiB 0.09 8 18 1 6.79088e+06 0 166176. 575.005 0.12 0.000968028 0.000900296 20206 45088 -1 18 1 1 1 110 40 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.02 -1 -1 0.01 0.000884953 0.000829916 +fixed_k6_frac_N8_22nm.xml single_ff.v common 1.16 vpr 74.29 MiB -1 -1 0.07 17668 1 0.02 -1 -1 29808 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76068 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 20 20 9 0 3 6 74.3 MiB 0.32 0.00 0.62144 0.62144 -1.18776 -0.62144 0.62144 0.23 9.46e-06 6.107e-06 7.2338e-05 5.3762e-05 74.3 MiB 0.32 74.3 MiB 0.09 20 27 1 6.79088e+06 13472 414966. 1435.87 0.15 0.000991708 0.000923792 22510 95286 -1 27 1 2 2 155 34 0.74674 0.74674 -1.31306 -0.74674 0 0 503264. 1741.40 0.02 0.00 0.05 -1 -1 0.02 0.000927584 0.000870114 +fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 1.96 vpr 74.95 MiB -1 -1 0.21 18824 3 0.06 -1 -1 33092 -1 -1 67 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76744 99 130 240 229 1 221 297 17 17 289 -1 unnamed_device -1 -1 875 831 15147 1842 1372 11933 74.9 MiB 0.45 0.00 1.77902 1.6707 -126.688 -1.6707 1.6707 0.23 0.000544346 0.000510829 0.0106205 0.0100193 74.9 MiB 0.45 74.9 MiB 0.15 32 1830 14 6.79088e+06 1.45062e+06 586450. 2029.24 0.33 0.0772085 0.0707225 24814 144142 -1 1586 13 517 851 46748 14508 2.0466 2.0466 -137.082 -2.0466 -0.16867 -0.16867 744469. 2576.02 0.03 0.03 0.07 -1 -1 0.03 0.0295429 0.0275638 +fixed_k6_frac_N8_22nm.xml diffeq1.v common 5.43 vpr 76.34 MiB -1 -1 0.31 23432 15 0.29 -1 -1 33828 -1 -1 46 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78168 162 96 817 258 1 692 309 17 17 289 -1 unnamed_device -1 -1 7537 6452 26409 275 7390 18744 76.3 MiB 0.94 0.01 22.1138 21.2087 -1557.26 -21.2087 21.2087 0.23 0.00162614 0.00151896 0.0510239 0.0477515 76.3 MiB 0.94 76.3 MiB 0.23 52 12973 34 6.79088e+06 2.59971e+06 926341. 3205.33 2.07 0.452281 0.419264 28558 226646 -1 11227 22 3275 7622 1002575 262444 20.6757 20.6757 -1527 -20.6757 0 0 1.14541e+06 3963.36 0.04 0.21 0.12 -1 -1 0.04 0.135881 0.127356 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt index 1ccd16490d7..b7420ccf41d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt @@ -38,3 +38,6 @@ pass_requirements_file=pass_requirements.txt script_params_common=-track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel +script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt index 39aa722daca..8d48ba3b7bb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt @@ -1,3 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.38 vpr 77.35 MiB -1 -1 0.36 22280 1 0.10 -1 -1 35580 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79208 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.18 1862 38583 13232 21153 4198 77.4 MiB 0.24 0.00 5.12303 -624.562 -5.12303 5.12303 0.45 0.00115671 0.00104931 0.13445 0.124537 -1 -1 -1 -1 64 3969 9 4.93594e+06 1.0962e+06 976140. 4980.31 5.77 0.971386 0.907233 31408 195022 -1 3606 8 821 857 201107 78801 4.57723 4.57723 -666.876 -4.57723 0 0 1.23909e+06 6321.90 0.06 0.12 0.38 -1 -1 0.06 0.0628918 0.0600921 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 7.77 vpr 77.61 MiB -1 -1 0.36 22212 1 0.08 -1 -1 35140 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79472 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.6 MiB 0.18 1862 38583 13232 21153 4198 77.6 MiB 0.37 0.00 5.12303 -624.562 -5.12303 5.12303 0.55 0.00210597 0.00194049 0.204405 0.191731 -1 -1 -1 -1 64 3993 10 4.93594e+06 1.0962e+06 976140. 4980.31 3.98 0.785401 0.735059 31408 195022 -1 3592 9 794 830 166912 64369 4.57723 4.57723 -658.916 -4.57723 0 0 1.23909e+06 6321.90 0.07 0.13 0.32 -1 -1 0.07 0.068841 0.0645644 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 2.99 vpr 75.31 MiB -1 -1 0.19 18544 1 0.04 -1 -1 31664 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77116 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.2 MiB 0.09 3373 1886 37005 12673 19524 4808 75.3 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.18 0.000888478 0.000830569 0.0676133 0.0633469 -1 -1 -1 -1 80 3637 13 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.12 0.273919 0.254588 33264 246902 -1 3285 7 680 743 143030 53497 4.57723 4.57723 -709.755 -4.57723 0 0 1.50824e+06 7695.10 0.03 0.04 0.16 -1 -1 0.03 0.0237623 0.0226895 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 3.06 vpr 75.10 MiB -1 -1 0.18 18308 1 0.05 -1 -1 31656 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76900 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.0 MiB 0.09 3373 1886 37005 12673 19524 4808 75.1 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.18 0.000947284 0.000887707 0.0714409 0.0669686 -1 -1 -1 -1 80 3614 31 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.17 0.308838 0.28719 33264 246902 -1 3269 7 690 753 144671 54345 4.57723 4.57723 -668.704 -4.57723 0 0 1.50824e+06 7695.10 0.03 0.04 0.16 -1 -1 0.03 0.0243899 0.0232635 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 3.85 vpr 75.10 MiB -1 -1 0.18 18304 1 0.05 -1 -1 31656 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76900 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.0 MiB 0.09 3373 1886 37005 12673 19524 4808 75.1 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.19 0.000947139 0.000884506 0.0718506 0.0673524 -1 -1 -1 -1 80 3571 8 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.78 0.275537 0.25602 33264 246902 -1 3282 7 664 709 751766 751766 4.57723 4.57723 -648.751 -4.57723 0 0 1.50824e+06 7695.10 0.04 0.18 0.18 -1 -1 0.04 0.0251499 0.0240091 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 4.13 vpr 75.70 MiB -1 -1 0.19 18304 1 0.05 -1 -1 31624 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77512 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.6 MiB 0.09 3373 1886 37005 12673 19524 4808 75.7 MiB 0.13 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.19 0.000936676 0.000876234 0.072396 0.0678269 -1 -1 -1 -1 80 3571 8 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 2.01 0.278036 0.258406 33264 246902 -1 3282 7 664 709 746031 746031 4.57723 4.57723 -648.751 -4.57723 0 0 1.50824e+06 7695.10 0.04 0.23 0.17 -1 -1 0.04 0.0252544 0.0240964 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 3.72 vpr 75.19 MiB -1 -1 0.19 18304 1 0.05 -1 -1 31656 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76992 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.1 MiB 0.09 3373 1886 37005 12673 19524 4808 75.2 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.18 0.000925013 0.000865263 0.0715735 0.0670973 -1 -1 -1 -1 80 3571 8 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.68 0.27697 0.257059 33264 246902 -1 3282 7 664 709 739993 283414 4.57723 4.57723 -648.751 -4.57723 0 0 1.50824e+06 7695.10 0.04 0.17 0.17 -1 -1 0.04 0.0248422 0.0236933 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt index 4e167973fd7..65bf790b0e7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.61 vpr 79.62 MiB -1 -1 0.81 23308 1 0.11 -1 -1 37544 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81536 130 40 1147 997 1 585 196 14 14 196 dsp_top auto 40.6 MiB 0.64 2711 47992 15247 26403 6342 79.6 MiB 0.47 0.01 6.04823 -699.558 -6.04823 6.04823 0.48 0.00203985 0.00179993 0.208906 0.186707 -1 -1 -1 -1 108 5255 25 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 4.22 0.825967 0.736098 36552 325092 -1 4721 19 2233 2309 243533 83581 7.64092 7.64092 -760.756 -7.64092 0 0 1.93951e+06 9895.46 0.09 0.19 0.61 -1 -1 0.09 0.108869 0.100506 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 4.52 vpr 78.22 MiB -1 -1 0.40 19840 1 0.06 -1 -1 33392 -1 -1 23 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 80096 130 40 1147 997 1 592 196 14 14 196 dsp_top auto 39.1 MiB 0.28 5185 2742 51406 16747 29054 5605 78.2 MiB 0.20 0.00 7.18035 6.03913 -683.447 -6.03913 6.03913 0.19 0.00100505 0.000908109 0.0981168 0.0895226 -1 -1 -1 -1 118 5148 28 4.93594e+06 1.40315e+06 1.66654e+06 8502.75 1.79 0.409007 0.367667 37820 362924 -1 5094 24 2395 2501 322053 103825 7.0462 7.0462 -729.408 -7.0462 0 0 2.11586e+06 10795.2 0.05 0.11 0.27 -1 -1 0.05 0.0618139 0.0571071 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/config.txt similarity index 79% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/config.txt index 245fb466a3d..54744e0cc01 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/config.txt @@ -16,7 +16,6 @@ archs_dir=arch/multi_die/stratixiv_3d circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif # Add architectures to list to sweep -arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml arch_list_add=3d_full_OPIN_inter_die_stratixiv_arch.timing.xml # Parse info and how to parse @@ -29,7 +28,4 @@ qor_parse_file=qor_vpr_titan.txt pass_requirements_file=pass_requirements_vpr_titan.txt script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -script_params_list_add = --place_bounding_box_mode auto_bb -script_params_list_add = --place_bounding_box_mode cube_bb -script_params_list_add = --place_bounding_box_mode per_layer_bb diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt new file mode 100644 index 00000000000..4a4c7e8c58a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 34.99 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1239896 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1077.1 MiB 7.54 181772 63669 220151 34297 170189 15665 1190.3 MiB 5.82 0.09 5.43671 4.9834 -5379.72 -3.9834 2.7577 0.01 0.0231458 0.0183209 1.51922 1.22818 74208 5.86903 18737 1.48189 26177 36020 11211877 1692426 0 0 2.60031e+07 21349.0 16 354380 4692432 -1 5.06256 2.57234 -4972.33 -4.06256 0 0 4.48 -1 -1 1190.3 MiB 3.13 2.65902 2.23319 1190.3 MiB -1 1.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt new file mode 100644 index 00000000000..1640c383443 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt @@ -0,0 +1,31 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of SDC files to use +sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/multi_die/stratixiv_3d + +# Add circuits to list to sweep +circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt new file mode 100644 index 00000000000..192e82a31ba --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 51.26 vpr 1.36 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1422252 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1077.2 MiB 7.54 177076 58479 231119 40825 176329 13965 1388.9 MiB 5.94 0.09 5.0611 5.01815 -4172.98 -4.01815 2.37031 0.04 0.0219122 0.0175206 1.56983 1.27458 100824 7.97406 32812 2.59506 28894 40551 43377071 9674443 0 0 2.54084e+07 20860.8 17 2001132 6214436 -1 5.14007 2.63151 -5380.59 -4.14007 0 0 6.15 -1 -1 1388.9 MiB 6.89 2.74676 2.32243 1388.9 MiB -1 11.16 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt deleted file mode 100644 index 22cc148a91e..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt +++ /dev/null @@ -1,7 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 83.45 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421664 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.4 MiB 12.25 180137 58272 230944 40790 173771 16383 1388.3 MiB 10.48 0.15 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0444933 0.0387879 3.15031 2.6241 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 12.21 -1 -1 1388.3 MiB 10.28 4.91142 4.17713 1388.3 MiB -1 16.75 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 85.51 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421424 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 12.33 180137 58272 230944 40790 173771 16383 1388.1 MiB 10.48 0.14 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0434223 0.0377288 3.13504 2.6098 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 13.53 -1 -1 1388.1 MiB 10.72 4.93468 4.19984 1388.1 MiB -1 17.21 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 86.05 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421572 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 12.02 186170 63595 242080 43083 181450 17547 1388.3 MiB 12.05 0.17 5.04678 4.86192 -4242.28 -3.86192 2.41884 0.05 0.051916 0.0457829 3.35985 2.75261 103428 8.31615 32795 2.63689 27768 38066 44034475 9785894 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 5.18643 2.65983 -5392.13 -4.18642 0 0 13.06 -1 -1 1388.3 MiB 9.86 5.14157 4.32891 1388.3 MiB -1 18.69 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 57.03 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245688 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.9 MiB 11.85 186170 63157 219808 34278 166444 19086 1216.5 MiB 10.07 0.18 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0545904 0.0489007 2.99902 2.51676 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.46 -1 -1 1216.5 MiB 4.58 4.95133 4.23051 1216.5 MiB -1 1.96 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 56.04 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245528 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 11.88 180137 61714 223520 36703 169137 17680 1216.3 MiB 10.63 0.16 5.41016 4.96403 -5546.44 -3.96403 2.84288 0.01 0.0440263 0.0385965 3.36781 2.8222 75346 6.05821 18897 1.51942 26061 36573 12725206 1711712 0 0 2.60031e+07 21349.0 14 354380 4692432 -1 5.08769 2.56235 -5100.1 -4.08769 0 0 7.77 -1 -1 1216.3 MiB 4.84 5.1781 4.41964 1216.3 MiB -1 1.92 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 58.79 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245324 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 11.84 186170 63157 219808 34278 166444 19086 1216.1 MiB 10.25 0.14 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0422071 0.0368357 2.98723 2.48631 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.89 -1 -1 1216.1 MiB 4.79 4.83395 4.11932 1216.1 MiB -1 1.80 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt index abc45194ec7..72305f830f8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 2.31 vpr 72.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74048 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.2 MiB 1.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00628067 0.00572957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.95 vpr 72.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73772 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.4 MiB 1.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00606424 0.00546366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.00 vpr 70.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 130 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72224 130 150 1169 1319 1 885 365 12 12 144 clb auto 30.3 MiB 0.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00300143 0.00278911 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.03 vpr 69.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 130 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71656 130 150 1216 1366 1 925 374 12 12 144 clb auto 30.2 MiB 0.61 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00277001 0.00256442 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index 94e710b87f5..c2cab91c857 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.05 vpr 66.01 MiB -1 -1 0.86 26896 5 0.23 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67592 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.0 MiB 0.02 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000412775 0.000360271 0.0136111 0.012803 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.04 -1 -1 66.0 MiB 0.03 0.0339384 0.0288063 66.0 MiB -1 0.00 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.21 vpr 69.14 MiB -1 -1 0.76 26288 4 0.18 -1 -1 36060 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70796 11 2 303 283 2 78 28 7 7 49 clb auto 29.6 MiB 0.27 285 784 175 539 70 69.1 MiB 0.05 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000707376 0.000615193 0.0194274 0.0173585 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 69.1 MiB 0.03 0.0450009 0.0414951 69.1 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.09 vpr 64.65 MiB -1 -1 0.42 23048 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 10 2 181 183 1 36 24 6 6 36 clb auto 25.3 MiB 0.02 196 160 398 88 284 26 64.7 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000227686 0.000206782 0.00385417 0.00356609 -1 -1 -1 -1 136 4.12121 61 1.84848 149 320 10235 1961 646728 646728 138825. 3856.24 17 3164 19284 -1 2.10277 2.10277 -91.6521 -2.10277 0 0 0.01 -1 -1 64.7 MiB 0.01 0.0141506 0.0127546 64.7 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.27 vpr 67.25 MiB -1 -1 0.42 22932 4 0.10 -1 -1 33012 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68868 11 2 303 283 2 85 28 7 7 49 clb auto 27.9 MiB 0.11 462 289 1204 263 848 93 67.3 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.00038481 0.000343694 0.0145236 0.0131117 -1 -1 -1 -1 314 3.97468 124 1.56962 130 211 4049 1168 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.02047 1.86775 -152.224 -2.02047 0 0 0.02 -1 -1 67.3 MiB 0.01 0.028669 0.0263845 67.3 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/config.txt deleted file mode 100644 index b1a0c921261..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/config.txt +++ /dev/null @@ -1,28 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics.v - -# Add architectures to list to sweep -arch_list_add=k6_frac_N10_mem32K_40nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt - -# Script parameters -#script_params="" -script_params = -track_memory_usage --enable_analytic_placer true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt deleted file mode 100644 index 7f41d46c079..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.75 vpr 67.64 MiB -1 -1 0.42 22416 3 0.08 -1 -1 36896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69264 99 130 344 474 1 227 298 12 12 144 clb auto 28.8 MiB 0.22 846 1293 248 869 176 67.6 MiB 0.10 0.00 1.87518 -117.076 -1.87518 1.87518 0.33 0.000961535 0.000869555 0.00580355 0.00550747 -1 -1 -1 -1 38 1541 12 5.66058e+06 4.21279e+06 319130. 2216.18 1.43 0.231487 0.210357 12522 62564 -1 1321 9 430 670 30619 10041 1.9175 1.9175 -131.199 -1.9175 -0.126268 -0.104429 406292. 2821.48 0.02 0.04 0.09 -1 -1 0.02 0.0283489 0.0264305 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt index f90dc9de594..52938d917ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.63 vpr 75.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77436 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.56 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00332256 0.00272635 0.0920151 0.0793873 75.6 MiB 3.56 75.6 MiB 2.42 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.47 0.288973 0.25613 75.6 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.81 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78036 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.93 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00365979 0.00331889 0.047619 0.043593 76.2 MiB 0.93 76.2 MiB 0.59 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.37 -1 -1 76.2 MiB 0.25 0.188446 0.174077 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 11.93 vpr 105.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108360 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 9.23 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.00660438 0.00519941 0.309592 0.257376 105.8 MiB 9.23 105.8 MiB 4.50 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.18 -1 -1 105.8 MiB 0.93 0.709043 0.615207 105.8 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.73 vpr 76.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78628 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.59 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.09 0.0040653 0.00347069 0.103188 0.0899686 76.8 MiB 3.59 76.8 MiB 2.31 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.37 -1 -1 76.8 MiB 0.47 0.321818 0.287107 76.8 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.98 vpr 73.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75472 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.7 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00129454 0.00112381 0.0398145 0.0363439 73.7 MiB 1.50 73.7 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.7 MiB 0.20 0.127617 0.117429 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 74.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76044 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.3 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00188121 0.00176936 0.0256359 0.0244673 74.3 MiB 0.45 74.3 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.3 MiB 0.13 0.105433 0.100554 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.07 vpr 103.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106172 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.7 MiB 5.65 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00399056 0.00320166 0.20162 0.170474 103.7 MiB 5.65 103.7 MiB 3.13 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.7 MiB 0.62 0.486586 0.43074 103.7 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.94 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76684 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.9 MiB 1.47 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00146693 0.00126108 0.0415462 0.0377108 74.9 MiB 1.47 74.9 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 74.9 MiB 0.19 0.135186 0.124628 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt index 91c3630a8a8..76465232886 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.88 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.73 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00371221 0.00305644 0.097355 0.0840965 75.4 MiB 3.73 75.4 MiB 2.65 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.4 MiB 0.50 0.299102 0.265267 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.04 vpr 75.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.0 MiB 1.04 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00356373 0.00322411 0.0543939 0.0472155 76.0 MiB 1.04 76.0 MiB 0.69 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.39 -1 -1 76.0 MiB 0.32 0.22263 0.205375 76.0 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 14.50 vpr 105.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108280 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 11.89 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.0066784 0.00535245 0.30231 0.252682 105.7 MiB 11.89 105.7 MiB 7.07 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.11 -1 -1 105.7 MiB 0.94 0.707357 0.615217 105.7 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.83 vpr 76.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78264 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.4 MiB 3.68 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00384755 0.00327555 0.103123 0.0900634 76.4 MiB 3.68 76.4 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.4 MiB 0.48 0.323332 0.288275 76.4 MiB -1 0.11 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.97 vpr 73.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75120 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.4 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00131792 0.00114251 0.0400779 0.0365448 73.4 MiB 1.50 73.4 MiB 0.99 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.4 MiB 0.20 0.127955 0.117552 73.4 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 73.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75720 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 73.9 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00182847 0.00171986 0.0251787 0.0240126 73.9 MiB 0.45 73.9 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 73.9 MiB 0.13 0.107099 0.101914 73.9 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.93 vpr 103.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106292 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.8 MiB 5.52 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00402634 0.00322812 0.200547 0.169453 103.8 MiB 5.52 103.8 MiB 3.00 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.8 MiB 0.62 0.485669 0.429563 103.8 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.99 vpr 75.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77004 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 75.2 MiB 1.48 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00153795 0.00132852 0.0472318 0.0431113 75.2 MiB 1.48 75.2 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 75.2 MiB 0.20 0.147085 0.135687 75.2 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt index e03594be3ed..3917cf290cc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.66 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.54 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00377685 0.0031064 0.0971738 0.0840095 75.4 MiB 3.54 75.4 MiB 2.44 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.35 -1 -1 75.4 MiB 0.49 0.299893 0.266532 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.87 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.95 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.12 0.00361228 0.00324116 0.0472811 0.0432415 76.2 MiB 0.95 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.40 -1 -1 76.2 MiB 0.27 0.192439 0.178374 76.2 MiB -1 0.12 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.92 vpr 105.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108344 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 13.27 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.27 0.0064285 0.00513075 0.474187 0.399734 105.8 MiB 13.27 105.8 MiB 7.54 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.15 -1 -1 105.8 MiB 0.91 0.870133 0.753188 105.8 MiB -1 0.27 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.70 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.7 MiB 3.57 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00387961 0.00328771 0.108944 0.0952913 76.7 MiB 3.57 76.7 MiB 2.29 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.32 -1 -1 76.7 MiB 0.51 0.337895 0.301103 76.7 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.96 vpr 73.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75492 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.7 MiB 1.48 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00133012 0.00115567 0.0399995 0.0365239 73.7 MiB 1.48 73.7 MiB 0.98 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.7 MiB 0.20 0.127012 0.116845 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 74.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76048 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.3 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00182176 0.00171274 0.0250514 0.0238946 74.3 MiB 0.45 74.3 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.3 MiB 0.13 0.104201 0.0993829 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.92 vpr 103.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106000 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.5 MiB 5.51 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00398133 0.00318465 0.201687 0.170276 103.5 MiB 5.51 103.5 MiB 2.97 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.5 MiB 0.63 0.489118 0.432801 103.5 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.93 vpr 75.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76824 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 75.0 MiB 1.46 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00146279 0.00126181 0.0412226 0.0375036 75.0 MiB 1.46 75.0 MiB 0.92 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 75.0 MiB 0.18 0.130876 0.120888 75.0 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt index 260e0e2c056..3759478d8c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 11.76 vpr 75.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77216 9 19 897 28 0 575 109 16 16 256 -1 mcnc_medium -1 -1 7102 6246 3749 356 2360 1033 75.4 MiB 10.60 0.01 5.59875 5.15754 -83.6777 -5.15754 nan 0.09 0.00367809 0.00303729 0.0800582 0.0701494 75.4 MiB 10.60 75.4 MiB 2.58 9765 17.0122 2613 4.55226 4147 20677 658214 114215 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.35541 nan -88.358 -5.35541 0 0 0.32 -1 -1 75.4 MiB 0.48 0.288075 0.253539 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.95 vpr 76.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 57 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77892 256 245 954 501 0 585 558 22 22 484 -1 mcnc_large -1 -1 7568 7468 23518 202 3225 20091 76.1 MiB 1.06 0.02 4.58215 4.06321 -789.076 -4.06321 nan 0.17 0.00395794 0.00352194 0.0546633 0.0494666 76.1 MiB 1.06 76.1 MiB 0.64 10448 17.8598 2871 4.90769 2610 5820 337031 73978 2.15576e+07 3.07196e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.29926 nan -860.162 -4.29926 0 0 0.37 -1 -1 76.1 MiB 0.29 0.21912 0.199431 76.1 MiB -1 0.17 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 34.79 vpr 105.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 284 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108284 10 10 2659 20 0 1371 304 22 22 484 -1 mcnc_large -1 -1 32736 26176 50333 12484 33100 4749 105.7 MiB 32.12 0.02 8.62387 6.83404 -65.9282 -6.83404 nan 0.15 0.0053571 0.00415525 0.333874 0.272699 105.7 MiB 32.12 105.7 MiB 4.39 39078 28.5033 10004 7.29686 9032 54400 2294214 310826 2.15576e+07 1.53059e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.03175 nan -67.1956 -7.03175 0 0 1.19 -1 -1 105.7 MiB 0.86 0.709263 0.607527 105.7 MiB -1 0.15 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 12.51 vpr 76.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78100 41 35 1006 76 0 566 161 16 16 256 -1 mcnc_medium -1 -1 7257 6649 5842 273 2922 2647 76.3 MiB 11.37 0.02 5.58018 4.9431 -137.944 -4.9431 nan 0.09 0.00696141 0.00638215 0.115593 0.094552 76.3 MiB 11.37 76.3 MiB 2.39 10043 17.7438 2739 4.83922 3885 20440 636556 113525 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.06598 nan -144.027 -5.06598 0 0 0.35 -1 -1 76.3 MiB 0.47 0.340764 0.297617 76.3 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.47 vpr 72.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74648 9 19 897 28 0 573 109 16 16 256 -1 mcnc_medium -1 -1 6908 6255 4529 398 2936 1195 72.9 MiB 3.99 0.00 5.79498 4.95412 -82.8956 -4.95412 nan 0.04 0.00131961 0.00114781 0.0384284 0.0351556 72.9 MiB 3.99 72.9 MiB 0.98 9742 17.0315 2618 4.57692 4440 22553 733607 128435 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.29908 nan -85.521 -5.29908 0 0 0.11 -1 -1 72.9 MiB 0.20 0.12869 0.118081 72.9 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.82 vpr 74.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75844 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7554 7460 5137 56 892 4189 74.1 MiB 0.43 0.01 5.01539 4.43785 -787.81 -4.43785 nan 0.05 0.00191044 0.00178051 0.0139785 0.0135099 74.1 MiB 0.43 74.1 MiB 0.31 10209 17.4812 2812 4.81507 2325 5207 293343 64225 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 16 47664 245996 -1 4.5769 nan -866.798 -4.5769 0 0 0.13 -1 -1 74.1 MiB 0.13 0.0965434 0.0922593 74.1 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 17.00 vpr 103.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 281 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106276 10 10 2659 20 0 1385 301 22 22 484 -1 mcnc_large -1 -1 32437 26329 47677 11320 31685 4672 103.8 MiB 15.55 0.01 7.86298 6.97012 -66.6328 -6.97012 nan 0.11 0.00394585 0.0031393 0.234275 0.197015 103.8 MiB 15.55 103.8 MiB 3.13 39327 28.3949 10114 7.30253 9446 56175 2430685 325649 2.15576e+07 1.51442e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.25735 nan -68.7995 -7.25735 0 0 0.36 -1 -1 103.8 MiB 0.66 0.518833 0.45621 103.8 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.58 vpr 74.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76560 41 35 1006 76 0 564 161 16 16 256 -1 mcnc_medium -1 -1 7552 6671 7590 431 3792 3367 74.8 MiB 4.11 0.00 5.51469 5.01871 -140.744 -5.01871 nan 0.04 0.00145908 0.00126433 0.0433791 0.0394286 74.8 MiB 4.11 74.8 MiB 0.92 10043 17.8067 2733 4.84574 3791 19758 636928 113707 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.42495 nan -150.307 -5.42495 0 0 0.11 -1 -1 74.8 MiB 0.18 0.135187 0.124838 74.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt index e9dd4dbf472..595d1c891b5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.77 vpr 75.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77552 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.7 MiB 3.65 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00374471 0.00311178 0.0942637 0.0815881 75.7 MiB 3.65 75.7 MiB 2.54 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.7 MiB 0.49 0.296978 0.264335 75.7 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.14 0.0035648 0.00318679 0.0499558 0.0460383 76.2 MiB 0.98 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.2 MiB 0.27 0.197871 0.183716 76.2 MiB -1 0.14 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.47 vpr 105.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108040 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.5 MiB 12.86 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.29 0.0116739 0.00965721 0.534688 0.455619 105.5 MiB 12.86 105.5 MiB 7.17 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.12 -1 -1 105.5 MiB 1.62 1.25142 1.10117 105.5 MiB -1 0.28 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.88 vpr 76.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78644 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.64 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00418085 0.00352692 0.113479 0.0974767 76.8 MiB 3.64 76.8 MiB 2.34 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.8 MiB 0.56 0.365085 0.323172 76.8 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.97 vpr 74.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75872 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 74.1 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00130604 0.00113413 0.0402888 0.0368028 74.1 MiB 1.50 74.1 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 74.1 MiB 0.20 0.127636 0.117479 74.1 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 74.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76432 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.6 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00183319 0.00172495 0.025168 0.0240182 74.6 MiB 0.45 74.6 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.6 MiB 0.13 0.104876 0.100044 74.6 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.98 vpr 103.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106232 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.7 MiB 5.57 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00463595 0.00382536 0.20651 0.174564 103.7 MiB 5.57 103.7 MiB 3.01 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.7 MiB 0.62 0.493598 0.436694 103.7 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.96 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76684 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.9 MiB 1.49 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00152566 0.00131828 0.0432798 0.0392071 74.9 MiB 1.49 74.9 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 74.9 MiB 0.18 0.133178 0.122788 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt index c179a99eb71..71bbbe6525b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.02 vpr 75.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77392 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.80 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.10 0.00366255 0.00300248 0.0988722 0.0856346 75.6 MiB 3.80 75.6 MiB 2.67 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.58 0.329873 0.296269 75.6 MiB -1 0.10 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77908 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.1 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00361625 0.00323438 0.0481778 0.0440548 76.1 MiB 0.98 76.1 MiB 0.62 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.1 MiB 0.27 0.193703 0.179342 76.1 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.93 vpr 105.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108228 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 13.43 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.25 0.0114469 0.00942196 0.523317 0.437298 105.7 MiB 13.43 105.7 MiB 7.67 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.08 -1 -1 105.7 MiB 1.54 1.21056 1.05802 105.7 MiB -1 0.25 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.95 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.9 MiB 3.70 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00501429 0.0044287 0.113755 0.0975648 76.9 MiB 3.70 76.9 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.9 MiB 0.54 0.357802 0.31714 76.9 MiB -1 0.11 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.98 vpr 73.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75432 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.7 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00133748 0.00116259 0.0408496 0.0373615 73.7 MiB 1.50 73.7 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.7 MiB 0.20 0.128419 0.118238 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.91 vpr 74.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76048 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.3 MiB 0.47 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00308404 0.00296931 0.0300262 0.0287318 74.3 MiB 0.47 74.3 MiB 0.32 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.15 -1 -1 74.3 MiB 0.14 0.119217 0.113274 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.93 vpr 103.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106308 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.8 MiB 5.52 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00404456 0.00321972 0.199444 0.168625 103.8 MiB 5.52 103.8 MiB 3.00 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.8 MiB 0.62 0.481167 0.426392 103.8 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.94 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77068 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 75.3 MiB 1.47 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00148096 0.00128726 0.0413364 0.0376351 75.3 MiB 1.47 75.3 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 75.3 MiB 0.18 0.131688 0.121582 75.3 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt index 5bcf12189e9..f73f554221f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.03 vpr 75.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 114 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77596 9 19 897 28 0 606 142 16 16 256 -1 mcnc_medium -1 -1 6550 6536 3472 155 2648 669 75.8 MiB 3.88 0.01 5.7154 5.4597 -89.3112 -5.4597 nan 0.10 0.00370216 0.00307222 0.0661479 0.0591146 75.8 MiB 3.88 75.8 MiB 2.88 10481 17.3240 2782 4.59835 4539 23483 740476 125213 1.05632e+07 6.14392e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72947 nan -94.1462 -5.72947 0 0 0.32 -1 -1 75.8 MiB 0.50 0.310788 0.282654 75.8 MiB -1 0.10 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.32 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 179 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78468 256 245 954 501 0 742 680 22 22 484 -1 mcnc_large -1 -1 9274 7572 60460 2284 20333 37843 76.6 MiB 2.36 0.02 5.23911 4.2903 -840.323 -4.2903 nan 0.13 0.00384619 0.00344153 0.09353 0.0842417 76.6 MiB 2.36 76.6 MiB 1.70 11049 14.8908 3078 4.14825 2733 6987 297544 68761 2.15576e+07 9.64703e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.65189 nan -884.263 -4.65189 0 0 0.41 -1 -1 76.6 MiB 0.28 0.244915 0.224675 76.6 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.12 vpr 106.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108712 10 10 2659 20 0 1430 382 22 22 484 -1 mcnc_large -1 -1 30097 26681 50242 8485 37651 4106 106.2 MiB 14.49 0.06 9.5895 7.11784 -67.5602 -7.11784 nan 0.29 0.0120588 0.0101618 0.577448 0.487406 106.2 MiB 14.49 106.2 MiB 8.21 40770 28.5105 10462 7.31608 8938 61030 2640427 332495 2.15576e+07 1.95096e+07 3.51389e+06 7260.09 17 64568 594370 -1 7.68543 nan -70.9452 -7.68543 0 0 1.09 -1 -1 106.2 MiB 1.70 1.23429 1.08029 106.2 MiB -1 0.29 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.65 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 124 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 665 200 16 16 256 -1 mcnc_medium -1 -1 8699 7144 11296 577 6471 4248 76.9 MiB 4.33 0.02 6.42009 5.14527 -151.192 -5.14527 nan 0.09 0.0040038 0.00343256 0.111382 0.0964207 76.9 MiB 4.33 76.9 MiB 3.06 11808 17.7564 3134 4.71278 5035 27959 918932 152826 1.05632e+07 6.68286e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.4847 nan -160.203 -5.4847 0 0 0.34 -1 -1 76.9 MiB 0.64 0.362116 0.322037 76.9 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.31 vpr 73.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 119 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75768 9 19 897 28 0 656 147 16 16 256 -1 mcnc_medium -1 -1 9465 7387 7500 653 5233 1614 74.0 MiB 1.83 0.00 6.84375 5.63197 -90.064 -5.63197 nan 0.04 0.00131708 0.00113824 0.0411484 0.0370479 74.0 MiB 1.83 74.0 MiB 1.31 11218 17.1267 2998 4.57710 4710 22969 767847 128278 1.05632e+07 6.41339e+06 1.26944e+06 4958.75 18 28900 206586 -1 6.05963 nan -96.1476 -6.05963 0 0 0.11 -1 -1 74.0 MiB 0.20 0.126178 0.115644 74.0 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.42 vpr 74.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 179 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76388 256 245 954 501 0 743 680 22 22 484 -1 mcnc_large -1 -1 9276 7596 60460 2199 20502 37759 74.6 MiB 1.03 0.01 5.23911 4.36438 -841.143 -4.36438 nan 0.05 0.00189527 0.00178544 0.0499427 0.0473007 74.6 MiB 1.03 74.6 MiB 0.79 10985 14.7847 3053 4.10902 2501 6468 260198 59947 2.15576e+07 9.64703e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.95172 nan -902.835 -4.95172 0 0 0.13 -1 -1 74.6 MiB 0.12 0.126567 0.120415 74.6 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.71 vpr 103.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106412 10 10 2659 20 0 1387 386 22 22 484 -1 mcnc_large -1 -1 28407 25969 52334 9214 38970 4150 103.9 MiB 6.23 0.01 8.84225 6.87893 -67.3793 -6.87893 nan 0.11 0.00413268 0.00332707 0.201364 0.170726 103.9 MiB 6.23 103.9 MiB 3.63 40223 29.0000 10345 7.45854 8587 59599 2538983 323136 2.15576e+07 1.97252e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.19431 nan -69.2992 -7.19431 0 0 0.36 -1 -1 103.9 MiB 0.68 0.492176 0.435586 103.9 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.43 vpr 75.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 125 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76868 41 35 1006 76 0 665 201 16 16 256 -1 mcnc_medium -1 -1 9806 7711 9021 479 5180 3362 75.1 MiB 1.93 0.00 7.51244 5.32876 -152.164 -5.32876 nan 0.04 0.00142804 0.00124551 0.0391378 0.0356815 75.1 MiB 1.93 75.1 MiB 1.39 12022 18.0782 3251 4.88872 4219 22486 741180 125076 1.05632e+07 6.73675e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.72072 nan -160.849 -5.72072 0 0 0.11 -1 -1 75.1 MiB 0.19 0.127975 0.117992 75.1 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt index e8dd91ee6ae..52747da9fdc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt @@ -1,6 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 25.85 vpr 83.03 MiB -1 -1 18.57 47636 3 1.01 -1 -1 38980 -1 -1 48 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85020 196 193 800 0 1 594 438 20 20 400 -1 vtr_extra_small -1 -1 4169 3142 106806 24519 69152 13135 83.0 MiB 3.45 0.01 2.78642 2.3599 -1119.38 -2.3599 2.3599 0.11 0.00336886 0.00290601 0.267623 0.235425 83.0 MiB 3.45 83.0 MiB 1.54 5164 8.82735 1542 2.63590 1808 2713 166829 48700 2.07112e+07 3.13491e+06 1.26946e+06 3173.65 11 38988 203232 -1 2.79177 2.79177 -1205.37 -2.79177 0 0 0.33 -1 -1 83.0 MiB 0.20 0.427611 0.384897 83.0 MiB -1 0.11 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.71 vpr 77.02 MiB -1 -1 0.44 22136 3 0.13 -1 -1 37044 -1 -1 68 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78864 99 130 264 0 1 227 298 20 20 400 -1 vtr_extra_small -1 -1 1534 732 61988 20558 27121 14309 77.0 MiB 1.17 0.01 1.84094 1.63182 -117.029 -1.63182 1.63182 0.10 0.00116098 0.00102609 0.0719437 0.0636329 77.0 MiB 1.17 77.0 MiB 0.48 1289 7.67262 408 2.42857 432 671 35594 10787 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 12 39388 210115 -1 2.0326 2.0326 -137.711 -2.0326 0 0 0.32 -1 -1 77.0 MiB 0.12 0.146262 0.115522 77.0 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.09 vpr 132.19 MiB -1 -1 6.50 65292 8 5.27 -1 -1 44656 -1 -1 246 385 2 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 135364 385 362 3324 0 1 2378 996 30 30 900 -1 vtr_small -1 -1 45961 31243 503168 167206 308523 27439 132.2 MiB 27.49 0.08 11.3485 9.24445 -10104.3 -9.24445 9.24445 0.52 0.0110533 0.00983869 1.90464 1.67809 132.2 MiB 27.49 132.2 MiB 14.11 42437 17.9590 11048 4.67541 10359 33405 1843617 333376 4.8774e+07 1.47499e+07 6.56785e+06 7297.61 17 120772 1084977 -1 9.50495 9.50495 -10508.2 -9.50495 0 0 2.27 -1 -1 132.2 MiB 0.99 2.49904 2.2274 132.2 MiB -1 0.52 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.73 vpr 86.61 MiB -1 -1 3.85 35472 16 0.66 -1 -1 39332 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88684 45 32 936 0 1 764 142 20 20 400 -1 vtr_extra_small -1 -1 7941 6580 16792 4505 10418 1869 86.6 MiB 7.12 0.02 11.8934 10.8778 -6730.96 -10.8778 10.8778 0.15 0.00604523 0.0052746 0.299411 0.249607 86.6 MiB 7.12 86.6 MiB 4.84 11265 14.8029 2859 3.75690 3304 9224 705116 168424 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 16 44576 305072 -1 11.1238 11.1238 -7296.13 -11.1238 0 0 0.55 -1 -1 86.6 MiB 0.49 0.557197 0.483674 86.6 MiB -1 0.15 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.92 vpr 76.71 MiB -1 -1 0.85 26400 4 0.19 -1 -1 36732 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78556 11 2 140 0 2 80 28 20 20 400 -1 vtr_extra_small -1 -1 371 277 994 274 621 99 76.7 MiB 0.79 0.00 2.14417 2.10685 -170.205 -2.10685 1.95087 0.09 0.000829747 0.000696435 0.0253099 0.0218497 76.7 MiB 0.79 76.7 MiB 0.47 484 6.54054 125 1.68919 154 271 5642 1534 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.24362 1.99822 -177.023 -2.24362 0 0 0.28 -1 -1 76.7 MiB 0.04 0.058266 0.0520206 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 10.90 vpr 81.36 MiB -1 -1 8.14 44968 3 0.57 -1 -1 35340 -1 -1 49 196 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83308 196 193 800 0 1 601 439 20 20 400 -1 vtr_extra_small -1 -1 4328 3107 92124 17877 63452 10795 81.4 MiB 1.38 0.00 2.56454 2.37946 -1137.82 -2.37946 2.37946 0.04 0.00170951 0.00159049 0.108014 0.100137 81.4 MiB 1.38 81.4 MiB 0.66 5067 8.55912 1503 2.53885 1660 2444 142383 40675 2.07112e+07 3.18881e+06 1.26946e+06 3173.65 10 38988 203232 -1 2.76727 2.76727 -1220.28 -2.76727 0 0 0.11 -1 -1 81.4 MiB 0.08 0.17114 0.160292 81.4 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.23 vpr 75.47 MiB -1 -1 0.22 18468 3 0.06 -1 -1 33128 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77280 99 130 264 0 1 226 298 20 20 400 -1 vtr_extra_small -1 -1 998 719 42088 12988 22077 7023 75.5 MiB 0.51 0.00 2.00298 1.89487 -117.095 -1.89487 1.89487 0.04 0.000568785 0.000532954 0.0270668 0.0254536 75.5 MiB 0.51 75.5 MiB 0.25 1273 7.62275 391 2.34132 403 645 32624 10084 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 11 39388 210115 -1 2.02782 2.02782 -132.929 -2.02782 0 0 0.12 -1 -1 75.5 MiB 0.03 0.0466214 0.0438046 75.5 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 18.99 vpr 130.75 MiB -1 -1 2.93 61476 8 2.72 -1 -1 42296 -1 -1 244 385 2 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 133892 385 362 3324 0 1 2373 994 30 30 900 -1 vtr_small -1 -1 44934 30685 486878 158175 303508 25195 130.8 MiB 10.73 0.04 10.9569 9.14069 -10026.4 -9.14069 9.14069 0.19 0.0075565 0.00697625 0.821563 0.749283 130.8 MiB 10.73 130.8 MiB 5.59 41636 17.6573 10780 4.57167 10078 33334 1771649 321112 4.8774e+07 1.46421e+07 6.56785e+06 7297.61 16 120772 1084977 -1 9.28426 9.28426 -10368.8 -9.28426 0 0 0.73 -1 -1 130.8 MiB 0.67 1.2751 1.17633 130.8 MiB -1 0.19 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.78 vpr 84.59 MiB -1 -1 1.71 32292 16 0.37 -1 -1 34988 -1 -1 59 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86620 45 32 936 0 1 764 140 20 20 400 -1 vtr_extra_small -1 -1 7967 6824 18290 3791 13097 1402 84.6 MiB 2.77 0.00 11.7422 10.6015 -6978.52 -10.6015 10.6015 0.06 0.00172166 0.00152276 0.108719 0.0971486 84.6 MiB 2.77 84.6 MiB 1.78 11182 14.6938 2948 3.87385 3523 9991 831731 205110 2.07112e+07 5.21975e+06 1.91495e+06 4787.38 14 44576 305072 -1 11.0577 11.0577 -7502.5 -11.0577 0 0 0.18 -1 -1 84.6 MiB 0.20 0.207414 0.189307 84.6 MiB -1 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.46 vpr 74.58 MiB -1 -1 0.41 22932 4 0.10 -1 -1 32968 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76368 11 2 140 0 2 81 28 20 20 400 -1 vtr_extra_small -1 -1 344 282 1246 289 767 190 74.6 MiB 0.35 0.00 2.1429 2.10685 -161.57 -2.10685 1.95087 0.04 0.000382895 0.000341958 0.0148948 0.0134952 74.6 MiB 0.35 74.6 MiB 0.22 481 6.41333 125 1.66667 162 273 5235 1511 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.13367 2.00787 -169.877 -2.13367 0 0 0.10 -1 -1 74.6 MiB 0.02 0.031341 0.0286656 74.6 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt index 9155e1a0c29..9dcd6930755 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.37 vpr 75.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 75.7 MiB 2.52 10470 18.5638 2823 5.00532 4441 21451 721238 120368 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.44204 nan -88.1999 -5.44204 0 0 0.32 -1 -1 75.7 MiB 0.45 0.190621 0.172257 75.7 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.70 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78028 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 76.2 MiB 0.61 10067 17.2380 2785 4.76884 2224 4785 262051 58317 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 14 47664 245996 -1 5.09713 nan -915.356 -5.09713 0 0 0.38 -1 -1 76.2 MiB 0.25 0.146815 0.136123 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.28 vpr 76.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78496 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 76.7 MiB 2.27 10759 18.7766 2936 5.12391 3972 20025 643838 113062 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.52727 nan -151.75 -5.52727 0 0 0.34 -1 -1 76.7 MiB 0.46 0.206081 0.184898 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.88 vpr 73.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75488 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 73.7 MiB 1.38 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.7 MiB 1.38 73.7 MiB 0.99 10384 18.5098 2834 5.05169 4200 20769 686232 118555 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.71537 nan -90.8975 -5.71537 0 0 0.11 -1 -1 73.7 MiB 0.18 0.0873879 0.0807521 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.80 vpr 74.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76432 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 74.6 MiB 0.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.6 MiB 0.35 74.6 MiB 0.31 10173 17.4195 2800 4.79452 2175 4597 261480 57693 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 19 47664 245996 -1 5.19666 nan -941.622 -5.19666 0 0 0.13 -1 -1 74.6 MiB 0.14 0.093956 0.0894993 74.6 MiB -1 0.05 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.86 vpr 75.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77068 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.3 MiB 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.3 MiB 1.34 75.3 MiB 0.93 11092 18.8639 3046 5.18027 4224 20724 680603 119637 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.63987 nan -156.834 -5.63987 0 0 0.11 -1 -1 75.3 MiB 0.19 0.0927209 0.0860572 75.3 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt index bd1a356f7b3..d9de69d6485 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.48 vpr 75.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77452 9 19 897 28 0 613 107 16 16 256 -1 mcnc_medium -1 -1 7227 6446 4661 444 2922 1295 75.6 MiB 3.30 0.01 5.83587 5.20235 -84.7514 -5.20235 nan 0.09 0.00365365 0.00308713 0.0953072 0.0828485 75.6 MiB 3.30 75.6 MiB 2.61 9964 16.2810 2709 4.42647 4690 20859 701687 124089 1.05632e+07 4.25763e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.47836 nan -87.8661 -5.47836 0 0 0.35 -1 -1 75.6 MiB 0.51 0.314162 0.28034 75.6 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.82 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78032 256 245 954 501 0 598 557 22 22 484 -1 mcnc_large -1 -1 8430 8247 28037 277 4264 23496 76.2 MiB 0.95 0.02 5.00844 4.05195 -786.983 -4.05195 nan 0.13 0.00372964 0.0033122 0.0643989 0.0586623 76.2 MiB 0.95 76.2 MiB 0.58 10883 18.1990 2937 4.91137 2442 5565 332488 69751 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.40791 nan -837.951 -4.40791 0 0 0.37 -1 -1 76.2 MiB 0.26 0.206289 0.19121 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.95 vpr 105.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108108 10 10 2659 20 0 1500 308 22 22 484 -1 mcnc_large -1 -1 33647 26777 51219 12453 33951 4815 105.6 MiB 12.21 0.05 7.95426 6.65363 -64.7441 -6.65363 nan 0.32 0.01158 0.00952696 0.683148 0.577318 105.6 MiB 12.21 105.6 MiB 8.23 39550 26.3667 10138 6.75867 10136 56388 2554636 337283 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.10986 nan -67.2122 -7.10986 0 0 1.12 -1 -1 105.6 MiB 1.79 1.41673 1.23449 105.6 MiB -1 0.32 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 3.96 vpr 76.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78624 41 35 1006 76 0 665 161 16 16 256 -1 mcnc_medium -1 -1 7612 6958 7590 343 3947 3300 76.8 MiB 2.84 0.02 6.23108 5.15201 -145.389 -5.15201 nan 0.09 0.00454121 0.00387629 0.099122 0.086103 76.8 MiB 2.84 76.8 MiB 2.13 10685 16.0677 2885 4.33835 4384 18462 592965 106217 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.45169 nan -154.246 -5.45169 0 0 0.32 -1 -1 76.8 MiB 0.51 0.354223 0.314944 76.8 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.79 vpr 74.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75868 9 19 897 28 0 628 108 16 16 256 -1 mcnc_medium -1 -1 7133 6654 3706 357 2411 938 74.1 MiB 1.24 0.00 5.58018 4.92812 -82.703 -4.92812 nan 0.04 0.00130258 0.00113599 0.0349201 0.0320233 74.1 MiB 1.24 74.1 MiB 0.99 10212 16.2871 2746 4.37959 5878 26871 986532 171228 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 26 28900 206586 -1 5.21469 nan -86.576 -5.21469 0 0 0.11 -1 -1 74.1 MiB 0.27 0.144906 0.13215 74.1 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.82 vpr 74.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 57 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76400 256 245 954 501 0 596 558 22 22 484 -1 mcnc_large -1 -1 8442 8222 21222 240 2369 18613 74.6 MiB 0.43 0.01 4.85109 4.26724 -789.819 -4.26724 nan 0.05 0.00183483 0.0017214 0.0271893 0.0259535 74.6 MiB 0.43 74.6 MiB 0.31 10906 18.2987 2932 4.91946 2356 5389 309032 65263 2.15576e+07 3.07196e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.73179 nan -857.452 -4.73179 0 0 0.13 -1 -1 74.6 MiB 0.12 0.0974406 0.0930916 74.6 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.00 vpr 103.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105732 10 10 2659 20 0 1510 309 22 22 484 -1 mcnc_large -1 -1 31802 27364 49377 11982 32709 4686 103.3 MiB 4.45 0.01 8.38409 6.51429 -63.2845 -6.51429 nan 0.11 0.00401015 0.00322611 0.239471 0.201148 103.3 MiB 4.45 103.3 MiB 3.22 40850 27.0530 10492 6.94834 11089 63641 3035099 392249 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 19 64568 594370 -1 6.78146 nan -65.8802 -6.78146 0 0 0.37 -1 -1 103.3 MiB 0.76 0.540944 0.474742 103.3 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.73 vpr 75.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77056 41 35 1006 76 0 678 159 16 16 256 -1 mcnc_medium -1 -1 7799 7097 7039 323 3443 3273 75.2 MiB 1.24 0.00 5.82238 4.98732 -145.614 -4.98732 nan 0.04 0.001505 0.00130537 0.0413734 0.0374728 75.2 MiB 1.24 75.2 MiB 0.95 10391 15.3260 2846 4.19764 4879 22033 706386 126210 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.2747 nan -150.182 -5.2747 0 0 0.12 -1 -1 75.2 MiB 0.20 0.139029 0.127655 75.2 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt index 353d272ff5e..e985dbf5f92 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.96 vpr 75.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77136 9 19 897 28 0 571 109 16 16 256 -1 mcnc_medium -1 -1 6849 6197 3749 306 2447 996 75.3 MiB 3.80 0.01 5.6777 5.15854 -84.4388 -5.15854 nan 0.12 0.00372518 0.00308527 0.0851251 0.0744623 75.3 MiB 3.80 75.3 MiB 2.72 9547 16.7491 2591 4.54561 4007 19117 612422 105847 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.57046 nan -89.3939 -5.57046 0 0 0.36 -1 -1 75.3 MiB 0.45 0.290389 0.260271 75.3 MiB -1 0.12 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.92 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78044 256 245 954 501 0 584 556 22 22 484 -1 mcnc_large -1 -1 7414 7336 16551 117 1750 14684 76.2 MiB 0.96 0.02 4.79868 3.95956 -780.296 -3.95956 nan 0.14 0.0037776 0.00334019 0.0431145 0.0394451 76.2 MiB 0.96 76.2 MiB 0.63 10156 17.3904 2785 4.76884 2499 5829 309976 67350 2.15576e+07 2.96417e+06 1.49107e+06 3080.73 17 47664 245996 -1 4.43922 nan -858.538 -4.43922 0 0 0.40 -1 -1 76.2 MiB 0.31 0.225991 0.20914 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.50 vpr 105.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 263 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108088 10 10 2659 20 0 1335 283 22 22 484 -1 mcnc_large -1 -1 29142 24368 34619 6112 24966 3541 105.6 MiB 14.79 0.04 8.99039 6.64595 -64.2305 -6.64595 nan 0.30 0.011351 0.00921126 0.534655 0.453947 105.6 MiB 14.79 105.6 MiB 8.92 36909 27.6472 9531 7.13933 8973 57196 2436221 318880 2.15576e+07 1.41741e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.07899 nan -66.0192 -7.07899 0 0 1.11 -1 -1 105.6 MiB 1.75 1.29851 1.13315 105.6 MiB -1 0.30 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.12 vpr 76.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78196 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7414 6419 7538 405 3643 3490 76.4 MiB 3.99 0.01 5.66659 5.10396 -142.048 -5.10396 nan 0.09 0.00395858 0.00331812 0.0974473 0.0845959 76.4 MiB 3.99 76.4 MiB 2.72 9920 17.3124 2710 4.72949 3957 20035 633461 111527 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.31293 nan -148.764 -5.31293 0 0 0.36 -1 -1 76.4 MiB 0.47 0.311907 0.278187 76.4 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.02 vpr 73.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75536 9 19 897 28 0 563 111 16 16 256 -1 mcnc_medium -1 -1 7098 5977 5165 481 3314 1370 73.8 MiB 1.56 0.00 5.87393 5.10533 -84.2691 -5.10533 nan 0.04 0.00129553 0.00112415 0.0425662 0.0388316 73.8 MiB 1.56 73.8 MiB 1.05 9429 16.7776 2543 4.52491 4233 21427 685976 119142 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.42217 nan -87.2542 -5.42217 0 0 0.11 -1 -1 73.8 MiB 0.18 0.129552 0.119237 73.8 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.82 vpr 73.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75236 256 245 954 501 0 584 555 22 22 484 -1 mcnc_large -1 -1 7542 7463 5115 58 915 4142 73.5 MiB 0.43 0.01 5.52179 4.5111 -812.738 -4.5111 nan 0.05 0.00187057 0.00175451 0.014083 0.0136228 73.5 MiB 0.43 73.5 MiB 0.31 10180 17.4315 2798 4.79110 2290 5418 289765 61404 2.15576e+07 2.91028e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.73551 nan -877.111 -4.73551 0 0 0.13 -1 -1 73.5 MiB 0.11 0.0874376 0.08384 73.5 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.39 vpr 103.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 269 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105864 10 10 2659 20 0 1330 289 22 22 484 -1 mcnc_large -1 -1 29067 24555 40399 8417 28233 3749 103.4 MiB 5.92 0.01 8.57662 6.48829 -62.7527 -6.48829 nan 0.11 0.00410389 0.00328836 0.220573 0.18529 103.4 MiB 5.92 103.4 MiB 3.36 37342 28.0767 9643 7.25038 9194 59469 2527516 336331 2.15576e+07 1.44975e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.74005 nan -65.3498 -6.74005 0 0 0.36 -1 -1 103.4 MiB 0.67 0.506692 0.445776 103.4 MiB -1 0.11 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.01 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 41 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76688 41 35 1006 76 0 592 159 16 16 256 -1 mcnc_medium -1 -1 7434 6630 6609 294 3295 3020 74.9 MiB 1.52 0.00 5.72346 5.17082 -143.976 -5.17082 nan 0.04 0.00140043 0.0012182 0.0394494 0.0360877 74.9 MiB 1.52 74.9 MiB 0.98 9848 16.6351 2709 4.57601 4387 22649 730292 125901 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.09467 nan -146.142 -5.09467 0 0 0.11 -1 -1 74.9 MiB 0.20 0.135638 0.125011 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt index d7bb035e33d..493089933c3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.78 vpr 83.23 MiB -1 -1 18.50 47880 3 1.03 -1 -1 38848 -1 -1 50 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85228 196 193 800 389 1 591 440 20 20 400 -1 vtr_extra_small -1 -1 3715 3554 3784 38 823 2923 83.2 MiB 2.24 0.02 2.85588 2.57265 -1175.96 -2.57265 2.57265 0.10 0.00362627 0.00313967 0.0281499 0.026191 83.2 MiB 2.24 83.2 MiB 1.59 5468 9.39519 1600 2.74914 1643 2642 175568 48502 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.92546 2.92546 -1279.3 -2.92546 0 0 0.33 -1 -1 83.2 MiB 0.23 0.194282 0.17603 83.2 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.30 vpr 77.05 MiB -1 -1 0.46 21648 3 0.11 -1 -1 36796 -1 -1 69 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78904 99 130 240 229 1 219 299 20 20 400 -1 vtr_extra_small -1 -1 897 855 16283 1900 1766 12617 77.1 MiB 0.85 0.01 1.95754 1.93615 -150.064 -1.93615 1.93615 0.10 0.00114824 0.00101953 0.0225391 0.0202679 77.1 MiB 0.85 77.1 MiB 0.55 1415 8.84375 420 2.62500 390 656 29567 8292 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 10 39388 210115 -1 1.99132 1.99132 -170.793 -1.99132 0 0 0.34 -1 -1 77.1 MiB 0.05 0.0576019 0.0526431 77.1 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.74 vpr 86.56 MiB -1 -1 3.84 35864 16 0.69 -1 -1 39076 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88636 45 32 936 77 1 765 142 20 20 400 -1 vtr_extra_small -1 -1 7990 6993 2362 101 1016 1245 86.6 MiB 6.20 0.02 12.1921 10.5297 -7133.55 -10.5297 10.5297 0.16 0.00556384 0.00434574 0.083545 0.0720334 86.6 MiB 6.20 86.6 MiB 4.77 11420 14.9869 2979 3.90945 3498 9480 737557 180691 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.8282 10.8282 -7490.44 -10.8282 0 0 0.55 -1 -1 86.6 MiB 0.48 0.322984 0.290732 86.6 MiB -1 0.16 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.69 vpr 76.73 MiB -1 -1 0.87 26256 4 0.17 -1 -1 36604 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 425 276 658 98 289 271 76.7 MiB 0.68 0.00 2.38519 2.10685 -169.375 -2.10685 1.95087 0.09 0.000833002 0.000701647 0.018572 0.0162134 76.7 MiB 0.68 76.7 MiB 0.44 404 5.53425 120 1.64384 174 291 5454 1630 2.07112e+07 808410 1.12964e+06 2824.09 11 37792 180905 -1 2.17742 1.95241 -171.997 -2.17742 0 0 0.30 -1 -1 76.7 MiB 0.04 0.0564754 0.0510591 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 10.47 vpr 81.20 MiB -1 -1 8.11 45204 3 0.57 -1 -1 35608 -1 -1 50 196 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83148 196 193 800 389 1 589 440 20 20 400 -1 vtr_extra_small -1 -1 3998 3782 18832 248 3091 15493 81.2 MiB 0.98 0.00 2.85588 2.47185 -1156.3 -2.47185 2.47185 0.04 0.00172364 0.00159607 0.0308341 0.0290834 81.2 MiB 0.98 81.2 MiB 0.63 5632 9.71035 1634 2.81724 1596 2379 162444 45554 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.84177 2.84177 -1268.87 -2.84177 0 0 0.12 -1 -1 81.2 MiB 0.09 0.105167 0.0996991 81.2 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.08 vpr 75.51 MiB -1 -1 0.22 18464 3 0.06 -1 -1 33404 -1 -1 69 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77320 99 130 240 229 1 222 299 20 20 400 -1 vtr_extra_small -1 -1 1001 943 16283 1928 655 13700 75.5 MiB 0.37 0.00 1.95754 1.93615 -151.243 -1.93615 1.93615 0.04 0.000568044 0.000533906 0.0123779 0.0117131 75.5 MiB 0.37 75.5 MiB 0.24 1463 8.97546 433 2.65644 390 644 29549 8534 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 9 39388 210115 -1 1.99132 1.99132 -165.748 -1.99132 0 0 0.12 -1 -1 75.5 MiB 0.02 0.0304031 0.0286853 75.5 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.50 vpr 84.02 MiB -1 -1 1.72 32292 16 0.36 -1 -1 35064 -1 -1 59 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86032 45 32 936 77 1 764 140 20 20 400 -1 vtr_extra_small -1 -1 8308 6790 6311 196 3112 3003 84.0 MiB 2.52 0.00 11.697 10.6608 -7088.74 -10.6608 10.6608 0.06 0.00172403 0.00151742 0.0484196 0.0441323 84.0 MiB 2.52 84.0 MiB 1.83 11366 14.9356 2988 3.92641 3444 9377 809880 202958 2.07112e+07 5.21975e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.968 10.968 -7522.1 -10.968 0 0 0.18 -1 -1 84.0 MiB 0.19 0.146169 0.135428 84.0 MiB -1 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.39 vpr 74.81 MiB -1 -1 0.41 22692 4 0.10 -1 -1 32956 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76604 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 441 361 112 19 45 48 74.8 MiB 0.32 0.00 2.32519 2.16196 -166.836 -2.16196 1.97742 0.04 0.000403733 0.000348452 0.00435748 0.00414137 74.8 MiB 0.32 74.8 MiB 0.21 486 6.65753 142 1.94521 190 278 5599 1612 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.17143 1.9491 -169.271 -2.17143 0 0 0.10 -1 -1 74.8 MiB 0.02 0.0211176 0.0196106 74.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 37ed89929f5..2c66d16fd32 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 1.86 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.08 0.000682102 0.000589331 0.0191204 0.0168271 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.92 0.219017 0.188624 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.09 0.03 -1 -1 0.01 0.0322472 0.0293972 - k4_n4_v7_longline_bidir.xml styr.blif common 1.71 vpr 60.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61932 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.08 1219 4247 600 3483 164 60.5 MiB 0.06 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000822212 0.000745517 0.0200899 0.0175819 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.71 0.217702 0.191181 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.11 0.03 -1 -1 0.02 0.0360271 0.0325274 - k4_n4_v7_l1_bidir.xml styr.blif common 2.28 vpr 61.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62500 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1285 7613 1616 5547 450 61.0 MiB 0.11 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.00083663 0.000735935 0.0404209 0.0365528 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.11 0.183783 0.164876 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0404434 0.0363816 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61916 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.09 1234 4643 666 3821 156 60.5 MiB 0.06 0.00 3.51175 -43.7413 -3.51175 3.51175 0.10 0.000796689 0.00069941 0.0254117 0.0229956 -1 -1 -1 -1 16 1911 27 2.43e+06 2.07e+06 -1 -1 2.14 0.308921 0.270668 3522 30407 -1 1965 30 1263 4698 759011 126866 28.7744 28.7744 -241.883 -28.7744 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0527885 0.0460513 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml styr.blif common 0.99 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1341 4439 719 3525 195 59.0 MiB 0.03 0.00 8.75156 5.95188 -76.2362 -5.95188 5.95188 0.03 0.000369091 0.000332668 0.0100569 0.0091901 -1 -1 -1 -1 14 2179 38 2.43e+06 2.16e+06 -1 -1 0.45 0.0941641 0.0811795 3402 27531 -1 1923 17 1033 3494 176707 22465 7.58177 7.58177 -95.383 -7.58177 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0164104 0.0147275 +k4_n4_v7_longline_bidir.xml styr.blif common 0.93 vpr 58.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60084 10 10 253 263 1 171 92 11 11 121 clb auto 19.5 MiB 0.03 1829 1318 3611 426 3020 165 58.7 MiB 0.02 0.00 5.19817 4.47516 -54.2373 -4.47516 4.47516 0.04 0.000369472 0.000337461 0.00887057 0.00812854 -1 -1 -1 -1 17 2528 41 2.43e+06 2.16e+06 -1 -1 0.36 0.0873451 0.075572 3202 31699 -1 2252 25 1472 4968 313575 40767 9.40236 9.40236 -107.704 -9.40236 0 0 -1 -1 0.01 0.06 0.01 -1 -1 0.01 0.0212313 0.0188588 +k4_n4_v7_l1_bidir.xml styr.blif common 1.05 vpr 58.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59704 10 10 253 263 1 171 92 11 11 121 clb auto 19.1 MiB 0.03 1829 1340 8579 1857 6361 361 58.3 MiB 0.04 0.00 11.3865 6.30908 -81.1511 -6.30908 6.30908 0.04 0.000366977 0.000330995 0.0174482 0.0159247 -1 -1 -1 -1 11 1565 28 2.43e+06 2.16e+06 -1 -1 0.45 0.0856261 0.0746974 4842 26035 -1 1365 23 1309 5061 314893 55846 8.55913 8.55913 -101.511 -8.55913 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0198322 0.0175973 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.29 vpr 59.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60520 10 10 253 263 1 171 92 11 11 121 clb auto 19.6 MiB 0.03 1829 1326 4025 528 3322 175 59.1 MiB 0.02 0.00 4.50889 3.47884 -44.786 -3.47884 3.47884 0.03 0.000378131 0.000339956 0.00936549 0.00859198 -1 -1 -1 -1 16 2193 28 2.43e+06 2.16e+06 -1 -1 0.67 0.09289 0.0804764 3522 30407 -1 2061 19 1236 4213 766518 139225 14.4125 14.4125 -146.898 -14.4125 0 0 -1 -1 0.00 0.12 0.01 -1 -1 0.00 0.017958 0.0160944 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 99bb28a8269..1eefaffbf17 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 2.33 vpr 66.02 MiB -1 -1 0.85 26768 5 0.17 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000423798 0.000369821 0.00844968 0.00761151 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.19 0.07328 0.0645326 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.03 0.01 -1 -1 0.00 0.0168546 0.0152174 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.62 vpr 65.81 MiB -1 -1 0.84 26884 5 0.22 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67392 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.05 152 432 67 335 30 65.8 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.05 0.000430785 0.000371967 0.00760808 0.00673261 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.40 0.162173 0.135998 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.05 0.01 -1 -1 0.00 0.0294148 0.0268014 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.34 vpr 64.70 MiB -1 -1 0.42 23428 5 0.11 -1 -1 33000 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 151 500 122 353 25 64.7 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000227544 0.000206917 0.00459824 0.0042382 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.05 0.0320813 0.0276697 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.010025 0.0089725 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.40 vpr 64.32 MiB -1 -1 0.42 23432 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 151 500 122 353 25 64.3 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000220507 0.000200662 0.0045838 0.00422736 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.12 0.0664389 0.0562702 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.00984711 0.00881128 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt index 5d7f440c1da..9b9daa1ca9d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 2.91 vpr 67.98 MiB -1 -1 0.40 22276 3 0.11 -1 -1 36796 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69616 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.20 0.00 1.86472 -118.834 -1.86472 1.86472 0.22 0.000979117 0.000879056 0.0638803 0.0581045 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.56 0.199818 0.181639 12522 62564 -1 1120 9 399 643 21323 6785 1.90702 1.90702 -133.259 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.0304906 0.0285332 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 1.68 vpr 66.70 MiB -1 -1 0.22 18444 3 0.06 -1 -1 33084 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68304 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.11 1675 704 66963 20370 32791 13802 66.7 MiB 0.12 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000559141 0.000523608 0.0432041 0.0404375 -1 -1 -1 -1 40 1452 18 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.16437 0.150951 12666 64609 -1 1219 12 447 673 30224 10238 2.02932 2.02932 -138.474 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0190203 0.0177879 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt index c1c20666920..62bfe78ec62 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.54 vpr 67.39 MiB -1 -1 0.42 22156 3 0.16 -1 -1 36544 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69008 99 130 344 474 1 225 301 13 13 169 clb auto 27.8 MiB 0.09 709 69853 20089 36202 13562 67.4 MiB 0.23 0.00 2.16096 -124.938 -2.16096 2.16096 0.29 0.000913323 0.000821579 0.0687918 0.0619499 -1 -1 -1 -1 30 1301 10 6.63067e+06 4.37447e+06 308771. 1827.05 1.05 0.343222 0.313014 11444 57198 -1 1153 11 545 813 32907 9964 1.99803 1.99803 -136.313 -1.99803 -0.30784 -0.0857401 382024. 2260.50 0.04 0.06 0.10 -1 -1 0.04 0.0301423 0.0279655 - k6_N10_mem32K_40nm.xml diffeq1.v common 13.02 vpr 70.71 MiB -1 -1 0.61 26808 15 0.59 -1 -1 38128 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72412 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 31.1 MiB 0.36 5686 93732 25708 60129 7895 70.7 MiB 0.92 0.01 21.5854 -1586.88 -21.5854 21.5854 0.47 0.00359311 0.00328994 0.373845 0.344857 -1 -1 -1 -1 42 11019 36 1.21132e+07 5.26753e+06 637230. 2489.18 7.15 1.94736 1.79599 20148 122574 -1 9118 25 3874 8580 1140724 318272 22.5245 22.5245 -1660.58 -22.5245 0 0 799729. 3123.94 0.07 0.71 0.15 -1 -1 0.07 0.298338 0.280888 - k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB -1 -1 0.11 20620 1 0.02 -1 -1 33040 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0264e-05 6.201e-06 6.8769e-05 4.6066e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00116982 0.00111262 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106891 0.001042 - k6_N10_mem32K_40nm.xml single_ff.v common 0.54 vpr 65.06 MiB -1 -1 0.09 21000 1 0.02 -1 -1 33296 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66620 2 1 3 4 1 3 4 3 3 9 -1 auto 26.6 MiB 0.00 6 9 3 5 1 65.1 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.01 2.0617e-05 1.4741e-05 0.000141684 0.000107774 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00168512 0.00158841 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00172391 0.0016612 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.58 vpr 67.37 MiB -1 -1 0.39 22284 3 0.08 -1 -1 36712 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68984 99 130 344 474 1 225 301 19 19 361 o auto 27.9 MiB 0.07 850 78925 21699 38013 19213 67.4 MiB 0.30 0.00 2.16428 -129.737 -2.16428 2.16428 1.74 0.000907451 0.000818758 0.097179 0.0888059 -1 -1 -1 -1 36 1162 10 1.79173e+07 4.37447e+06 833707. 2309.44 1.42 0.329975 0.298327 24998 161561 -1 1074 10 581 868 36231 9318 1.99581 1.99581 -134.677 -1.99581 -0.182839 -0.0660558 1.02328e+06 2834.56 0.12 0.05 0.23 -1 -1 0.12 0.0286893 0.0266338 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 20.39 vpr 77.82 MiB -1 -1 0.54 26812 15 0.47 -1 -1 38260 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79688 162 96 1009 950 1 665 324 24 24 576 i auto 30.8 MiB 0.33 7393 99292 28927 58867 11498 77.8 MiB 1.03 0.02 21.7254 -1657.33 -21.7254 21.7254 3.05 0.00462453 0.00428627 0.416981 0.375188 -1 -1 -1 -1 38 12380 31 3.08128e+07 5.26753e+06 1.42563e+06 2475.05 11.34 2.12533 1.94729 42274 284153 -1 10868 19 3672 8078 1198132 301968 22.4983 22.4983 -1725.65 -22.4983 0 0 1.79535e+06 3116.93 0.13 0.60 0.50 -1 -1 0.13 0.215504 0.199648 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.51 vpr 65.29 MiB -1 -1 0.10 20720 1 0.02 -1 -1 33044 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1044e-05 6.598e-06 7.3231e-05 5.0487e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00113801 0.00107607 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.00158495 0.00154688 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.64 vpr 65.29 MiB -1 -1 0.10 20876 1 0.03 -1 -1 33324 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 2 1 3 4 1 3 4 4 4 16 i auto 27.0 MiB 0.00 7 9 0 1 8 65.3 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.4352e-05 9.526e-06 0.000103801 7.6571e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00161569 0.00152133 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00155787 0.00150496 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.49 vpr 66.48 MiB -1 -1 0.22 18824 3 0.06 -1 -1 33092 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68076 99 130 344 474 1 224 302 13 13 169 clb auto 26.8 MiB 0.04 1746 762 68106 19514 34631 13961 66.5 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.11 0.000545151 0.000510762 0.0399859 0.0374705 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.21 0.10715 0.0986602 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.03 0.03 -1 -1 0.01 0.0162028 0.0151156 +k6_N10_mem32K_40nm.xml diffeq1.v common 4.73 vpr 69.38 MiB -1 -1 0.32 23428 15 0.29 -1 -1 34064 -1 -1 61 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71040 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.7 MiB 0.16 9690 5422 80388 23076 51132 6180 69.4 MiB 0.32 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.18 0.0016374 0.00152032 0.126843 0.118121 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 2.18 0.566686 0.523646 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.23 0.07 -1 -1 0.02 0.0905548 0.0850156 +k6_N10_mem32K_40nm.xml single_wire.v common 0.53 vpr 63.50 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 1 1 1 2 0 1 2 3 3 9 -1 auto 25.2 MiB 0.00 2 2 3 0 3 0 63.5 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.533e-06 3.577e-06 5.4316e-05 3.6591e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000899985 0.000839888 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000879513 0.000848701 +k6_N10_mem32K_40nm.xml single_ff.v common 0.53 vpr 63.50 MiB -1 -1 0.07 17292 1 0.02 -1 -1 29972 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 6 9 3 5 1 63.5 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 1.9086e-05 1.5272e-05 8.8302e-05 6.8383e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000997361 0.00092975 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000928588 0.000891047 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 2.68 vpr 66.09 MiB -1 -1 0.23 18680 3 0.06 -1 -1 33044 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67676 99 130 344 474 1 224 302 19 19 361 o auto 26.0 MiB 0.04 2630 951 69118 18569 36933 13616 66.1 MiB 0.12 0.00 2.44032 1.89487 -136.14 -1.89487 1.89487 0.68 0.000571066 0.000535628 0.0419031 0.0391258 -1 -1 -1 -1 36 1362 12 1.79173e+07 4.42837e+06 833707. 2309.44 0.54 0.158153 0.144928 24998 161561 -1 1242 10 542 821 37855 9195 1.91637 1.91637 -141.984 -1.91637 -0.260117 -0.143334 1.02328e+06 2834.56 0.03 0.03 0.09 -1 -1 0.03 0.0197224 0.0183669 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 5.48 vpr 76.38 MiB -1 -1 0.31 23816 15 0.29 -1 -1 34012 -1 -1 61 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78212 162 96 1009 950 1 667 324 24 24 576 i auto 30.0 MiB 0.16 14162 6905 91508 24620 57078 9810 76.4 MiB 0.36 0.01 26.8808 21.7286 -1710.39 -21.7286 21.7286 1.13 0.00162259 0.00150985 0.144903 0.134733 -1 -1 -1 -1 32 12694 37 3.08128e+07 5.26753e+06 1.24505e+06 2161.54 1.45 0.414682 0.384459 39974 242477 -1 10860 26 4768 10723 1400040 362149 22.9048 22.9048 -1885.36 -22.9048 0 0 1.54255e+06 2678.04 0.05 0.27 0.13 -1 -1 0.05 0.0982135 0.0920022 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.54 vpr 63.39 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64908 1 1 1 2 0 1 2 4 4 16 i auto 25.1 MiB 0.00 3 3 3 0 0 3 63.4 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 7.064e-06 3.953e-06 5.5843e-05 3.7452e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.000937595 0.000878513 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.000868787 0.000834386 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.53 vpr 63.02 MiB -1 -1 0.07 17672 1 0.02 -1 -1 29920 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64528 2 1 3 4 1 3 4 4 4 16 i auto 24.8 MiB 0.00 7 7 9 0 1 8 63.0 MiB 0.00 0.00 0.55247 0.55247 -0.955943 -0.55247 0.55247 0.00 9.672e-06 6.229e-06 7.3202e-05 5.3956e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.00 0.000992269 0.000917558 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00094227 0.000904416 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 278399cb6d8..c7a42e2d8a5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.77 vpr 65.95 MiB -1 -1 0.64 26892 5 0.17 -1 -1 36964 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67536 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 568 210 329 29 66.0 MiB 0.00 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 168 36 646728 646728 19965.4 554.594 0.12 0.0658358 0.0559906 1696 3924 -1 165 24 236 544 12437 3707 2.26842 2.26842 -94.6601 -2.26842 0 0 25971.8 721.439 0.00 0.03 0.00 -1 -1 0.00 0.0200385 0.0180231 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.30 vpr 64.27 MiB -1 -1 0.42 23048 5 0.11 -1 -1 32508 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 165 874 360 491 23 64.3 MiB 0.00 0.00 -1 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 194 14 646728 646728 19965.4 554.594 0.05 0.0268855 0.0229859 1696 3924 -1 170 14 189 408 8500 2615 2.16176 2.16176 -92.1884 -2.16176 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.00914723 0.00823102 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt index b44eab4cd1c..457ca6aae28 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 14.98 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.82 4.4449e-05 3.636e-05 0.000492339 0.000302558 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.14 0.00246861 0.00204917 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00171876 0.00162871 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 17.28 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60472 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.88 4.5558e-05 3.7864e-05 0.000392587 0.000316954 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00226581 0.00204304 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00121674 0.00115171 - sub_tiles.xml sub_tiles.blif common_--check_route_off 16.44 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.05 6.9962e-05 5.8494e-05 0.000570046 0.000472887 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.09 0.00239105 0.00217713 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00134624 0.00127449 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common_--check_route_full 4.62 vpr 57.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58524 6 7 19 26 0 19 26 3 3 9 -1 auto 18.7 MiB 0.00 51 51 216 43 63 110 57.2 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.90 2.1456e-05 1.7214e-05 0.000207128 0.000166346 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00133396 0.00120338 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.0010614 0.00100173 +sub_tiles.xml sub_tiles.blif common_--check_route_quick 4.53 vpr 57.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58908 6 7 19 26 0 19 26 3 3 9 -1 auto 19.1 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.82 2.2115e-05 1.7856e-05 0.000217527 0.000170315 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00124615 0.00111395 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00107232 0.00101111 +sub_tiles.xml sub_tiles.blif common_--check_route_off 4.56 vpr 57.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58520 6 7 19 26 0 19 26 3 3 9 -1 auto 18.7 MiB 0.00 51 51 216 43 63 110 57.1 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.84 2.2198e-05 1.7921e-05 0.000224128 0.000167458 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.0014896 0.00134369 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00102348 0.00096044 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 124aaee2a04..5f3bbb09c0f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.66 vpr 66.09 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33388 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67676 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.65 100 74 24 47 3 66.1 MiB 0.00 0.00 2.48207 -28.4593 -2.48207 2.48207 0.02 0.000164662 0.000145718 0.00164144 0.00155216 -1 -1 -1 -1 38 129 6 151211 75605.7 48493.3 1939.73 0.18 0.0548944 0.0466047 2100 8065 -1 122 13 105 125 3874 2046 2.74837 2.74837 -33.9524 -2.74837 0 0 61632.8 2465.31 0.00 0.01 0.01 -1 -1 0.00 0.00954243 0.00888996 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.19 MiB -1 -1 0.14 21572 1 0.04 -1 -1 34020 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68800 19 18 308 249 1 134 43 5 5 25 clb auto 27.7 MiB 5.80 445 2068 454 1604 10 67.2 MiB 0.04 0.00 4.5386 -91.3528 -4.5386 4.5386 0.02 0.000449316 0.000397091 0.0186893 0.0169167 -1 -1 -1 -1 50 721 33 151211 151211 61632.8 2465.31 0.30 0.144091 0.126311 2268 9834 -1 620 20 733 1185 38218 18241 5.03997 5.03997 -109.631 -5.03997 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0288144 0.0262691 53 83 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.12 vpr 64.71 MiB -1 -1 0.07 17596 1 0.02 -1 -1 30072 -1 -1 3 9 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 9 8 75 70 1 34 20 5 5 25 clb auto 25.5 MiB 0.37 114 98 74 21 50 3 64.7 MiB 0.00 0.00 2.48207 2.48207 -27.0891 -2.48207 2.48207 0.01 0.000107575 9.8776e-05 0.00110372 0.00106107 -1 -1 -1 -1 38 138 12 151211 75605.7 48493.3 1939.73 0.06 0.0197476 0.0166644 2100 8065 -1 119 12 82 91 2625 1383 2.45975 2.45975 -29.6014 -2.45975 0 0 61632.8 2465.31 0.00 0.01 0.00 -1 -1 0.00 0.00468675 0.00431297 13 18 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.60 vpr 65.51 MiB -1 -1 0.09 18364 1 0.03 -1 -1 30608 -1 -1 9 19 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67084 19 18 308 249 1 135 46 6 6 36 clb auto 26.2 MiB 3.56 587 468 1358 299 1048 11 65.5 MiB 0.02 0.00 4.87574 4.8546 -99.0856 -4.8546 4.8546 0.02 0.000300463 0.000275416 0.00787823 0.00739934 -1 -1 -1 -1 40 1040 31 403230 226817 88484.8 2457.91 0.20 0.07778 0.0678958 3734 16003 -1 750 18 631 1001 35065 15346 5.69994 5.69994 -115.447 -5.69994 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0168321 0.0154848 54 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index e2bde77991f..316cb57d442 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.40 vpr 59.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61208 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9684e-05 6.8866e-05 0.000576703 0.000522527 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00940561 0.00796331 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00917782 0.00398665 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.34 vpr 59.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61228 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4384e-05 5.704e-05 0.000402489 0.000366894 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0100179 0.00835542 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00286153 0.00265955 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 59.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61188 1 4 28 32 2 10 9 4 4 16 clb auto 21.1 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4879e-05 5.7282e-05 0.000404422 0.000368079 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00971796 0.00808787 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00303232 0.00280678 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.31 vpr 58.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59868 1 4 28 32 2 10 9 4 4 16 clb auto 19.8 MiB 0.01 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 6.53e-05 5.4819e-05 0.000394918 0.000361284 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0059078 0.00495365 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0017688 0.00164015 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.31 vpr 57.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59208 1 4 28 32 2 10 9 4 4 16 clb auto 19.2 MiB 0.00 22 21 27 10 10 7 57.8 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.7045e-05 4.1525e-05 0.000356415 0.000327846 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00503283 0.0042397 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00176555 0.00162958 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 57.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59112 1 4 28 32 2 10 9 4 4 16 clb auto 19.1 MiB 0.00 22 21 27 10 10 7 57.7 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.1269e-05 3.581e-05 0.000380089 0.000351263 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00490459 0.00412987 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00176255 0.0016337 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index 9d76eedbd00..b227476183e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.31 vpr 59.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61216 2 2 22 24 2 4 6 4 4 16 clb auto 21.3 MiB 0.00 8 15 5 7 3 59.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 5.264e-05 4.5649e-05 0.000308634 0.000273818 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.002301 0.00212354 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00265986 0.00219441 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.29 vpr 58.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59572 2 2 22 24 2 4 6 4 4 16 clb auto 19.5 MiB 0.00 8 8 15 5 7 3 58.2 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.01 3.3312e-05 2.8021e-05 0.000249857 0.000222009 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.00 0.00183223 0.00169467 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00137997 0.0012867 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt index 55f3e1dd3ba..b7e6584d848 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index 948d09b747d..e1f6058b268 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.66 MiB -1 -1 0.07 21096 1 0.02 -1 -1 33168 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 6 3 0 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.5934e-05 1.0639e-05 9.4808e-05 6.8481e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00119359 0.00110751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.27 vpr 59.66 MiB -1 -1 0.08 20840 1 0.02 -1 -1 33340 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 9 9 5 2 2 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.6744e-05 1.0373e-05 9.4261e-05 6.634e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00132946 0.0012632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 31.57 parmys 210.75 MiB -1 -1 25.18 215804 2 1.59 -1 -1 60048 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63168 5 156 191 347 1 163 316 15 15 225 clb auto 22.1 MiB 0.04 31 86316 62145 3320 20851 61.7 MiB 0.22 0.02 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000537912 0.000491594 0.0397632 0.036381 -1 -1 -1 -1 -1 50 5 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0494991 0.045404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 25.71 parmys 210.82 MiB -1 -1 22.20 215880 2 0.99 -1 -1 60300 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62916 5 156 191 347 1 163 316 15 15 225 clb auto 21.9 MiB 0.02 33 86316 61936 3548 20832 61.4 MiB 0.10 0.00 1.51877 -14.6769 -1.51877 1.51877 0.00 0.000236107 0.000213852 0.0263786 0.0239723 -1 -1 -1 -1 -1 59 7 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0328145 0.0299576 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 20748 1 0.02 -1 -1 33304 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 6 2 1 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.6453e-05 1.1342e-05 0.000108728 7.9328e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.0015946 0.00150943 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 21132 1 0.02 -1 -1 33192 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 9 9 5 2 2 65.2 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.8934e-05 1.2137e-05 0.000113982 8.1444e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.00161693 0.00153615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 5.07 vpr 72.77 MiB -1 -1 1.12 29456 2 0.10 -1 -1 37868 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74516 311 156 972 1128 1 953 525 28 28 784 memory auto 32.5 MiB 0.54 8655 197406 67882 119014 10510 72.8 MiB 1.23 0.02 3.83315 -4315.62 -3.83315 3.83315 0.00 0.0052551 0.00459042 0.542684 0.463052 -1 -1 -1 -1 -1 12421 13 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.41 0.761716 0.663478 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 5.34 vpr 72.84 MiB -1 -1 1.44 29580 2 0.14 -1 -1 38000 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74592 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.55 8675 193172 64013 116396 12763 72.8 MiB 0.82 0.01 3.94715 -3504.6 -3.94715 3.94715 0.00 0.00308193 0.00262987 0.364549 0.310746 -1 -1 -1 -1 -1 12709 18 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.33 0.5457 0.474589 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.33 vpr 58.26 MiB -1 -1 0.06 17124 1 0.02 -1 -1 29960 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59656 2 1 3 4 1 3 4 3 3 9 -1 auto 19.5 MiB 0.00 6 6 9 6 3 0 58.3 MiB 0.00 0.00 0.631526 0.55447 -0.91031 -0.55447 0.55447 0.00 9.096e-06 5.714e-06 7.2854e-05 5.3361e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00119026 0.00111378 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.35 vpr 57.88 MiB -1 -1 0.06 17120 1 0.02 -1 -1 29900 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59272 2 1 3 4 1 3 4 3 3 9 -1 auto 19.5 MiB 0.00 9 9 9 5 2 2 57.9 MiB 0.00 0.00 0.50194 0.48631 -0.91031 -0.48631 0.48631 0.00 1.0552e-05 6.177e-06 7.7442e-05 5.6208e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00124162 0.00117322 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 18.39 parmys 207.19 MiB -1 -1 15.30 212160 2 0.89 -1 -1 56412 -1 -1 155 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61752 5 156 191 347 1 163 316 15 15 225 clb auto 20.3 MiB 0.02 93 31 86316 62044 3278 20994 60.3 MiB 0.08 0.00 1.75726 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000224295 0.000210617 0.0190742 0.0179017 -1 -1 -1 -1 -1 46 7 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0245095 0.0229368 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 18.49 parmys 207.43 MiB -1 -1 15.24 212412 2 0.90 -1 -1 56416 -1 -1 155 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61372 5 156 191 347 1 163 316 15 15 225 clb auto 20.6 MiB 0.02 102 33 86316 61971 3553 20792 59.9 MiB 0.07 0.00 1.51873 1.47673 -14.6018 -1.47673 1.47673 0.00 0.000227964 0.000214063 0.0189836 0.0177643 -1 -1 -1 -1 -1 49 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0236295 0.02208 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.38 vpr 63.18 MiB -1 -1 0.06 17272 1 0.02 -1 -1 29964 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64696 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 6 2 1 63.2 MiB 0.00 0.00 0.629525 0.55247 -0.90831 -0.55247 0.55247 0.00 9.944e-06 6.35e-06 7.7389e-05 5.7155e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.00103762 0.000966446 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.36 vpr 63.41 MiB -1 -1 0.06 17128 1 0.02 -1 -1 29980 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64932 2 1 3 4 1 3 4 3 3 9 -1 auto 24.8 MiB 0.00 9 9 9 5 2 2 63.4 MiB 0.00 0.00 0.49994 0.48631 -0.90831 -0.48631 0.48631 0.00 1.0823e-05 6.339e-06 7.8471e-05 5.6828e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.000951333 0.000890977 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 2.92 vpr 70.77 MiB -1 -1 0.75 26116 2 0.09 -1 -1 33620 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72472 311 156 972 1128 1 953 525 28 28 784 memory auto 31.7 MiB 0.27 18876 8963 212225 78866 122905 10454 70.8 MiB 0.61 0.01 4.92557 4.25856 -4308.38 -4.25856 4.25856 0.00 0.00268505 0.00240057 0.286887 0.256005 -1 -1 -1 -1 -1 12922 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.19 0.383503 0.345483 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 2.96 vpr 71.48 MiB -1 -1 0.73 26120 2 0.09 -1 -1 33580 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73192 311 156 972 1128 1 953 525 28 28 784 memory auto 32.0 MiB 0.27 19048 9147 216459 76243 126716 13500 71.5 MiB 0.65 0.01 5.19493 4.54954 -3411.74 -4.54954 4.54954 0.00 0.00270574 0.0024254 0.30082 0.26586 -1 -1 -1 -1 -1 13132 15 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.22 0.424559 0.380762 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt index 9cebacaf785..5bc7bdd18eb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.85 vpr 66.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 8 4 25 28 5 19 19 6 6 36 clb auto 27.5 MiB 0.60 51 194 39 119 36 66.0 MiB 0.01 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 8.3509e-05 6.4713e-05 0.00086545 0.000699438 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.0 MiB 0.00 0.00307466 0.00275514 66.0 MiB -1 0.00 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21296 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.34 vpr 63.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65512 8 4 25 28 5 19 19 6 6 36 clb auto 25.3 MiB 0.17 73 51 194 39 119 36 64.0 MiB 0.00 0.00 1.51369 1.41795 -5.85435 -1.41795 0.545 0.00 3.4898e-05 2.684e-05 0.000448159 0.000363972 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 673 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.00 -1 -1 64.0 MiB 0.00 0.00175021 0.00156962 64.0 MiB -1 0.00 +k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.04 vpr 18.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 18952 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index c751724ac21..feaca68d693 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.30 vpr 65.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66556 -1 2 2 4 0 2 4 4 4 16 clb auto 26.8 MiB 0.00 0 9 0 2 7 65.0 MiB 0.00 0.00 nan 0 0 nan 0.01 9.099e-06 4.802e-06 6.6245e-05 4.4664e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00112148 0.00105568 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00152182 0.00148612 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.32 vpr 63.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65152 -1 2 2 4 0 2 4 4 4 16 clb auto 25.0 MiB 0.00 0 0 9 0 2 7 63.6 MiB 0.00 0.00 nan nan 0 0 nan 0.00 8.028e-06 4.217e-06 6.2739e-05 4.2279e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.000902134 0.000846924 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.000893006 0.000861174 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index 19c7fb784a9..4228b940981 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 36.32 vpr 86.72 MiB -1 -1 4.05 45484 3 0.90 -1 -1 40972 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88800 236 305 3199 3011 1 1520 677 25 25 625 -1 25x25 45.9 MiB 3.77 14108 309661 104995 184095 20571 86.7 MiB 2.82 0.04 4.79923 -2884.9 -4.79923 4.79923 1.31 0.00890658 0.00798503 1.05545 0.927146 -1 -1 -1 -1 58 25094 44 3.19446e+07 9.87633e+06 2.35761e+06 3772.18 18.23 4.76599 4.25993 69363 480205 -1 22477 18 6375 16887 1571491 383129 5.01505 5.01505 -3124.26 -5.01505 0 0 3.00727e+06 4811.63 0.12 0.58 0.43 -1 -1 0.12 0.287158 0.267873 - column_io.xml raygentop.v common 21.72 vpr 86.87 MiB -1 -1 3.94 45412 3 0.59 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88956 236 305 3199 3011 1 1520 677 25 25 625 io auto 46.1 MiB 2.22 12585 268067 93998 147700 26369 86.9 MiB 1.58 0.02 4.73901 -2866.75 -4.73901 4.73901 0.71 0.00580557 0.00496502 0.564483 0.497852 -1 -1 -1 -1 54 26673 50 2.82259e+07 9.87633e+06 2.01770e+06 3228.33 9.11 2.60416 2.32669 60384 399159 -1 22031 17 6221 15823 1566992 390050 4.92063 4.92063 -3214.76 -4.92063 0 0 2.61977e+06 4191.64 0.11 0.57 0.36 -1 -1 0.11 0.283045 0.264698 - multiwidth_blocks.xml raygentop.v common 24.35 vpr 86.45 MiB -1 -1 4.29 45400 3 0.88 -1 -1 40680 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88524 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.5 MiB 3.44 13659 253212 84696 147080 21436 86.4 MiB 2.39 0.03 4.97053 -2888.67 -4.97053 4.97053 0.57 0.0095941 0.00864195 0.904905 0.798443 -1 -1 -1 -1 70 23087 25 1.65001e+07 9.87633e+06 1.31889e+06 3653.42 9.29 3.5266 3.16984 37321 246261 -1 21189 14 5796 14717 1380152 383870 5.13329 5.13329 -3164.24 -5.13329 0 0 1.66774e+06 4619.77 0.06 0.50 0.26 -1 -1 0.06 0.248992 0.232939 - non_column.xml raygentop.v common 55.37 vpr 101.45 MiB -1 -1 4.51 45384 3 0.78 -1 -1 40740 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103880 236 305 3188 3000 1 1523 673 33 33 1089 io auto 46.9 MiB 3.81 15255 254201 81770 140693 31738 97.7 MiB 2.36 0.03 4.86131 -2900.08 -4.86131 4.86131 2.27 0.00977579 0.00884174 0.917497 0.805822 -1 -1 -1 -1 48 30162 49 5.44432e+07 9.66075e+06 2.98548e+06 2741.49 34.00 4.50443 4.0188 95950 575791 -1 25045 20 6804 18118 1664218 433730 5.45028 5.45028 -3158.16 -5.45028 0 0 3.81303e+06 3501.40 0.21 0.95 0.95 -1 -1 0.21 0.482241 0.44347 - non_column_tall_aspect_ratio.xml raygentop.v common 44.05 vpr 108.02 MiB -1 -1 4.73 45644 3 0.86 -1 -1 40856 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110616 236 305 3188 3000 1 1523 673 23 46 1058 io auto 47.3 MiB 3.74 14790 242409 83942 122709 35758 98.8 MiB 2.21 0.03 4.6713 -2947.44 -4.6713 4.6713 2.10 0.00881355 0.00803567 0.866396 0.762137 -1 -1 -1 -1 54 27998 49 5.05849e+07 9.66075e+06 3.28516e+06 3105.07 22.44 5.06657 4.53255 98319 656086 -1 23970 19 6505 16966 1638977 432992 5.05886 5.05886 -3281.32 -5.05886 0 0 4.26512e+06 4031.31 0.30 0.98 1.19 -1 -1 0.30 0.480325 0.442198 - non_column_wide_aspect_ratio.xml raygentop.v common 55.14 vpr 115.98 MiB -1 -1 4.85 45536 3 0.89 -1 -1 40604 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 118764 236 305 3188 3000 1 1523 673 53 27 1431 io auto 47.2 MiB 4.13 15438 292525 96949 170972 24604 116.0 MiB 2.79 0.04 4.87363 -3002.95 -4.87363 4.87363 2.83 0.00999099 0.00902684 1.12807 0.98489 -1 -1 -1 -1 46 32183 50 7.18852e+07 9.66075e+06 3.81039e+06 2662.74 30.50 4.16688 3.69158 125381 744275 -1 26057 24 7716 19635 2034521 534369 5.1816 5.1816 -3336.75 -5.1816 0 0 4.88937e+06 3416.75 0.38 1.34 1.15 -1 -1 0.38 0.614347 0.564321 - custom_sbloc.xml raygentop.v common 26.06 vpr 86.32 MiB -1 -1 4.50 45448 3 1.04 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88392 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 4.20 13741 271038 86813 158916 25309 86.3 MiB 2.67 0.04 4.66207 -2945.67 -4.66207 4.66207 0.62 0.0101306 0.00867476 0.964821 0.865378 -1 -1 -1 -1 68 24218 46 1.65001e+07 9.87633e+06 1.26689e+06 3509.39 7.14 3.30943 2.96886 36601 241349 -1 21082 17 5846 15055 1419293 377571 4.86127 4.86127 -3204.17 -4.86127 0 0 1.57833e+06 4372.12 0.09 0.93 0.49 -1 -1 0.09 0.46499 0.431595 - multiple_io_types.xml raygentop.v common 162.68 vpr 512.77 MiB -1 -1 4.59 44868 3 0.91 -1 -1 40632 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 525072 236 305 3199 3011 1 1520 677 70 70 4900 io_left auto 46.0 MiB 4.88 29540 98720 5114 25125 68481 512.8 MiB 0.75 0.03 4.77694 -3775.91 -4.77694 4.77694 29.11 0.00955143 0.00822118 0.265489 0.23233 -1 -1 -1 -1 46 47171 45 2.76175e+08 9.87633e+06 1.25363e+07 2558.43 103.39 4.74809 4.24216 425698 2387761 -1 40627 18 8645 22202 3622069 899914 5.14884 5.14884 -4109.51 -5.14884 0 0 1.61910e+07 3304.29 1.21 1.53 3.08 -1 -1 1.21 0.445697 0.411568 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_grid.xml raygentop.v common 17.52 vpr 84.87 MiB -1 -1 2.11 42840 3 0.53 -1 -1 37004 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86904 236 305 3199 3011 1 1523 675 25 25 625 -1 25x25 45.9 MiB 1.88 30826 14481 296575 101967 175892 18716 84.9 MiB 1.19 0.02 7.09553 4.79307 -2895.89 -4.79307 4.79307 0.49 0.00404936 0.00373604 0.453796 0.412288 -1 -1 -1 -1 56 27441 32 3.19446e+07 9.76854e+06 2.27235e+06 3635.76 8.42 1.54762 1.41602 68115 457904 -1 23429 18 6422 16721 1633043 414220 4.92066 4.92066 -3228.39 -4.92066 0 0 2.89946e+06 4639.14 0.09 0.43 0.26 -1 -1 0.09 0.228671 0.215662 +column_io.xml raygentop.v common 13.20 vpr 84.73 MiB -1 -1 2.11 42840 3 0.53 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86760 236 305 3199 3011 1 1523 675 25 25 625 io auto 45.5 MiB 1.86 28947 12805 264026 93507 163068 7451 84.7 MiB 1.07 0.02 6.19083 4.92182 -2798.47 -4.92182 4.92182 0.45 0.00386921 0.003551 0.384409 0.349362 -1 -1 -1 -1 54 25735 23 2.82259e+07 9.76854e+06 2.01770e+06 3228.33 4.39 1.3452 1.22801 60384 399159 -1 22144 15 5803 15289 1517391 375232 5.17726 5.17726 -3105.16 -5.17726 0 0 2.61977e+06 4191.64 0.08 0.39 0.23 -1 -1 0.08 0.208718 0.197683 +multiwidth_blocks.xml raygentop.v common 11.01 vpr 85.16 MiB -1 -1 2.10 42644 3 0.51 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87204 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.9 MiB 1.83 27296 13664 243313 79797 144041 19475 85.2 MiB 0.96 0.01 7.04872 4.69621 -2916.6 -4.69621 4.69621 0.21 0.00375866 0.00345546 0.355094 0.322715 -1 -1 -1 -1 70 24143 30 1.65001e+07 9.76854e+06 1.31889e+06 3653.42 3.07 1.33175 1.21367 37321 246261 -1 21464 15 6203 15799 1529026 424169 4.71101 4.71101 -3112.78 -4.71101 0 0 1.66774e+06 4619.77 0.04 0.35 0.16 -1 -1 0.04 0.187972 0.177589 +non_column.xml raygentop.v common 14.99 vpr 98.91 MiB -1 -1 2.24 41936 3 0.48 -1 -1 38412 -1 -1 126 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 101288 236 305 3188 3000 1 1520 674 33 33 1089 io auto 46.7 MiB 1.99 36533 15061 269488 91860 157197 20431 97.4 MiB 1.00 0.01 7.4161 4.90918 -2943.89 -4.90918 4.90918 0.82 0.00384724 0.00350765 0.37964 0.345058 -1 -1 -1 -1 54 27586 33 5.44432e+07 9.71464e+06 3.30487e+06 3034.77 4.75 1.37884 1.25939 100302 649205 -1 23881 20 6491 17318 1529311 414224 6.12281 6.12281 -3223.84 -6.12281 0 0 4.28921e+06 3938.67 0.13 0.43 0.50 -1 -1 0.13 0.232808 0.218578 +non_column_tall_aspect_ratio.xml raygentop.v common 16.02 vpr 97.64 MiB -1 -1 2.30 42268 3 0.49 -1 -1 38420 -1 -1 126 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 99984 236 305 3188 3000 1 1520 674 23 46 1058 io auto 48.2 MiB 1.93 38199 14733 245856 82760 136190 26906 95.4 MiB 0.94 0.01 8.90911 4.95032 -2931.23 -4.95032 4.95032 0.79 0.003732 0.00342402 0.351006 0.319132 -1 -1 -1 -1 52 28730 41 5.05849e+07 9.71464e+06 3.17293e+06 2998.99 5.91 1.39167 1.27101 97261 632982 -1 24184 19 6976 18077 1589447 411584 5.61027 5.61027 -3209.89 -5.61027 0 0 4.15960e+06 3931.57 0.13 0.42 0.46 -1 -1 0.13 0.222476 0.208816 +non_column_wide_aspect_ratio.xml raygentop.v common 16.23 vpr 114.89 MiB -1 -1 2.23 42456 3 0.51 -1 -1 38084 -1 -1 126 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 117652 236 305 3188 3000 1 1520 674 53 27 1431 io auto 47.4 MiB 2.01 41800 15715 293120 96558 176401 20161 114.9 MiB 1.13 0.02 8.75852 4.83208 -2966.14 -4.83208 4.83208 1.11 0.00394946 0.00359569 0.43193 0.391243 -1 -1 -1 -1 50 29305 30 7.18852e+07 9.71464e+06 4.09444e+06 2861.24 5.10 1.45359 1.3252 128243 787897 -1 25411 18 6656 17052 1503266 383226 5.17928 5.17928 -3293.35 -5.17928 0 0 5.23266e+06 3656.65 0.17 0.41 0.52 -1 -1 0.17 0.218658 0.206004 +custom_sbloc.xml raygentop.v common 11.14 vpr 85.09 MiB -1 -1 2.11 42068 3 0.51 -1 -1 36976 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87128 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.9 MiB 1.88 27296 13137 255149 87552 148387 19210 85.1 MiB 1.03 0.02 7.00084 4.99197 -2892.82 -4.99197 4.99197 0.22 0.00391014 0.00357245 0.373695 0.338718 -1 -1 -1 -1 68 22261 27 1.65001e+07 9.76854e+06 1.26689e+06 3509.39 3.06 1.3486 1.22808 36601 241349 -1 20367 15 5668 14466 1281380 334598 4.957 4.957 -3115.31 -4.957 0 0 1.57833e+06 4372.12 0.04 0.34 0.15 -1 -1 0.04 0.197825 0.186835 +multiple_io_types.xml raygentop.v common 38.75 vpr 510.90 MiB -1 -1 2.11 42452 3 0.54 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 523164 236 305 3199 3011 1 1523 675 70 70 4900 io_left auto 45.9 MiB 2.29 68337 27793 95363 4323 24983 66057 510.9 MiB 0.44 0.01 10.4866 5.00659 -3523.06 -5.00659 5.00659 12.29 0.00405701 0.00372146 0.166522 0.152725 -1 -1 -1 -1 52 42943 37 2.76175e+08 9.76854e+06 1.39708e+07 2851.19 12.38 1.27647 1.16971 445294 2682153 -1 37901 18 8291 21706 3271061 840277 5.11058 5.11058 -3856.44 -5.11058 0 0 1.83718e+07 3749.35 0.63 0.68 1.74 -1 -1 0.63 0.221189 0.207674 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index 9ad80c43a91..a52c4e985c2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.93 MiB -1 -1 0.36 22040 3 0.12 -1 -1 36928 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69560 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.23 673 63978 19550 30341 14087 67.9 MiB 0.25 0.01 1.86472 -118.834 -1.86472 1.86472 0.23 0.00124652 0.00114654 0.0791433 0.0725521 -1 -1 -1 -1 38 1384 9 5.66058e+06 4.21279e+06 328943. 2284.32 0.66 0.24355 0.222932 12522 66188 -1 1114 9 395 636 21516 6871 1.90702 1.90702 -133.439 -1.90702 -1.20917 -0.320482 418267. 2904.63 0.04 0.05 0.10 -1 -1 0.04 0.0351893 0.0324309 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 1.65 vpr 66.48 MiB -1 -1 0.22 18444 3 0.06 -1 -1 33100 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68076 99 130 344 474 1 228 298 12 12 144 clb auto 27.1 MiB 0.10 1675 704 66963 20370 32791 13802 66.5 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.10 0.000547023 0.000511318 0.0407422 0.0381484 -1 -1 -1 -1 40 1447 14 5.66058e+06 4.21279e+06 343462. 2385.15 0.33 0.154346 0.141557 12666 68385 -1 1229 9 430 657 29320 9898 2.03042 2.03042 -138.775 -2.03042 -0.436676 -0.298787 431791. 2998.55 0.01 0.02 0.04 -1 -1 0.01 0.0159269 0.0149459 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt index 88d0cc36263..7a201af14f7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 65.74 vpr 1.17 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1222776 13 29 26295 20086 1 12439 800 40 32 1280 -1 EP4SGX110 1063.6 MiB 14.29 72376 238368 44187 187356 6825 1172.1 MiB 12.27 0.21 5.14869 -5574.19 -4.14869 2.7734 0.01 0.0513395 0.0444487 3.37672 2.67885 83490 6.71303 20017 1.60947 25863 35776 9229792 1644713 0 0 2.34683e+07 18334.6 15 375646 4004209 -1 5.37962 2.85331 -5732.11 -4.37962 0 0 7.55 -1 -1 1172.1 MiB 6.09 5.72718 4.67253 1172.1 MiB -1 3.79 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 35.31 vpr 1.17 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1222524 13 29 26295 20086 1 12646 791 40 32 1280 -1 EP4SGX110 1077.3 MiB 7.77 239076 73734 242087 47102 187997 6988 1170.3 MiB 6.30 0.09 5.63444 5.39011 -5538.73 -4.39011 2.81304 0.01 0.0220364 0.0193919 1.79552 1.47773 84889 6.71378 20487 1.62029 25867 34992 8975854 1601365 0 0 2.34683e+07 18334.6 16 375646 4004209 -1 5.63353 2.99154 -5719.81 -4.63353 0 0 3.73 -1 -1 1170.3 MiB 2.72 2.96387 2.51924 1170.3 MiB -1 1.28 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index f8dbe6d76d8..9399e0cc166 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.26 vpr 64.63 MiB -1 -1 0.36 22472 3 0.08 -1 -1 36672 -1 -1 72 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66184 99 130 353 483 1 273 302 15 15 225 memory auto 25.1 MiB 0.03 836 70130 21082 33527 15521 64.6 MiB 0.28 0.00 1.52582 -78.5706 -1.52582 1.52582 0.00 0.00103975 0.000940046 0.0805857 0.0730912 -1 -1 -1 -1 1163 5.43458 640 2.99065 663 1535 177334 49638 1.16234e+06 363548 2.18283e+06 9701.45 10 48952 428016 -1 1.65868 1.65868 -90.7494 -1.65868 -2.16982 -0.309514 0.64 -1 -1 64.6 MiB 0.08 0.105372 0.095866 64.6 MiB -1 0.38 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.29 vpr 62.83 MiB -1 -1 0.27 18364 3 0.06 -1 -1 33116 -1 -1 72 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64340 99 130 353 483 1 273 302 15 15 225 memory auto 23.4 MiB 0.02 2130 858 65070 19636 30261 15173 62.8 MiB 0.12 0.00 1.71828 1.52582 -77.3355 -1.52582 1.52582 0.00 0.00058607 0.000549367 0.0386887 0.0361876 -1 -1 -1 -1 1238 5.78505 678 3.16822 700 1565 188506 51086 1.16234e+06 363548 2.18283e+06 9701.45 11 48952 428016 -1 1.60126 1.60126 -87.5381 -1.60126 -2.22487 -0.375057 0.27 -1 -1 62.8 MiB 0.04 0.0551511 0.0514246 62.8 MiB -1 0.14 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index 01809a06f11..9b0f40005b1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 22.14 vpr 81.82 MiB -1 -1 1.50 29500 2 0.12 -1 -1 37736 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83780 311 156 1015 1158 1 965 514 28 28 784 memory auto 35.0 MiB 0.98 9365 202198 74776 117229 10193 76.8 MiB 1.40 0.02 4.8046 -3913.87 -4.8046 4.8046 1.69 0.00610306 0.00535177 0.650008 0.562031 -1 -1 -1 -1 46 14326 15 4.25198e+07 9.94461e+06 2.42825e+06 3097.26 10.53 2.95135 2.62498 81963 495902 -1 13813 11 2359 2703 832718 314081 4.94363 4.94363 -4384.42 -4.94363 -367.864 -1.26276 3.12000e+06 3979.60 0.25 1.49 0.70 -1 -1 0.25 0.183604 0.168791 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 21.14 vpr 85.34 MiB -1 -1 1.46 29488 2 0.17 -1 -1 37984 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 87384 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.6 MiB 1.02 9365 202198 74776 117229 10193 77.2 MiB 1.49 0.03 4.8046 -3913.87 -4.8046 4.8046 1.72 0.00745529 0.00636204 0.709181 0.610899 -1 -1 -1 -1 46 14531 14 4.25198e+07 9.94461e+06 2.47848e+06 3161.33 10.27 3.22179 2.86209 81963 509322 -1 13895 10 2295 2641 564364 164225 5.2138 5.2138 -4583.26 -5.2138 -149.396 -1.20609 3.17357e+06 4047.92 0.16 0.89 0.46 -1 -1 0.16 0.127663 0.117099 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 25.61 vpr 78.92 MiB -1 -1 1.51 29244 2 0.15 -1 -1 37516 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80812 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.8 MiB 0.83 9442 200140 70475 118412 11253 78.1 MiB 1.44 0.02 4.10149 -3784.12 -4.10149 4.10149 1.51 0.00620655 0.00547017 0.672177 0.575194 -1 -1 -1 -1 40 16586 15 4.25198e+07 9.94461e+06 2.15085e+06 2743.43 14.64 1.95101 1.72006 78831 435812 -1 15579 11 2621 3012 1218850 719774 5.45816 5.45816 -4586.28 -5.45816 -1608.52 -3.17721 2.68809e+06 3428.68 0.23 1.76 0.54 -1 -1 0.23 0.216383 0.199419 15 950 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 7.83 vpr 76.29 MiB -1 -1 0.77 25744 2 0.08 -1 -1 34464 -1 -1 32 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78124 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.3 MiB 0.45 19865 9549 204256 72417 120221 11618 75.2 MiB 0.58 0.01 5.60967 3.86883 -3854.15 -3.86883 3.86883 0.62 0.00251817 0.00223801 0.26652 0.235626 -1 -1 -1 -1 38 15620 13 4.25198e+07 9.94461e+06 2.06185e+06 2629.91 2.65 0.824788 0.739806 78047 421269 -1 14413 13 2666 3203 1457933 704363 4.53757 4.53757 -4350.73 -4.53757 -517.68 -1.45296 2.60823e+06 3326.82 0.08 0.69 0.22 -1 -1 0.08 0.100156 0.0932531 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 7.65 vpr 76.19 MiB -1 -1 0.74 25740 2 0.09 -1 -1 34340 -1 -1 32 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78020 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.3 MiB 0.49 19865 9549 204256 72417 120221 11618 75.1 MiB 0.60 0.01 5.60967 3.86883 -3854.15 -3.86883 3.86883 0.65 0.00269112 0.00240935 0.28253 0.250663 -1 -1 -1 -1 36 16026 28 4.25198e+07 9.94461e+06 2.00618e+06 2558.90 2.54 0.974248 0.877683 76483 403003 -1 14763 13 2964 3560 850058 256440 4.32275 4.32275 -4167.47 -4.32275 -202.025 -1.15486 2.47848e+06 3161.33 0.09 0.52 0.21 -1 -1 0.09 0.103198 0.09627 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 9.40 vpr 77.06 MiB -1 -1 0.72 25744 2 0.08 -1 -1 34472 -1 -1 32 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78912 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.3 MiB 0.45 19865 9322 210430 75479 122755 12196 77.1 MiB 0.61 0.01 5.60967 3.96043 -3633.05 -3.96043 3.96043 0.61 0.00270142 0.00233618 0.287893 0.256515 -1 -1 -1 -1 36 16853 27 4.25198e+07 9.94461e+06 1.96702e+06 2508.96 4.16 0.934384 0.84348 76483 392433 -1 15496 13 2658 3060 1573658 1035121 5.75178 5.75178 -4622.22 -5.75178 -1616.18 -3.24966 2.42368e+06 3091.42 0.11 0.81 0.20 -1 -1 0.11 0.100558 0.0936526 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index 6c7432d3e12..0dbc3e0ca1d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.52 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.33 10472 141533 36950 100839 3744 71.5 MiB 1.36 0.02 7.46482 -1369.01 -7.46482 7.46482 0.53 0.00499636 0.00433729 0.369387 0.30729 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 10.94 2.01193 1.71604 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.85 0.23 -1 -1 0.04 0.262211 0.23364 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 5.00 vpr 70.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71820 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.0 MiB 0.17 24088 10407 135291 36283 95683 3325 70.1 MiB 0.56 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.21 0.00207977 0.00177833 0.142029 0.122896 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.49 0.448442 0.390716 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.31 0.08 -1 -1 0.02 0.092161 0.0837678 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index 15d40a35dda..9ddaee22f6b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 34.16 vpr 84.50 MiB -1 -1 7.12 54432 5 2.11 -1 -1 42788 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86528 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 1.85 10543 233626 82676 126206 24744 84.5 MiB 2.72 0.04 4.85425 -2733.64 -4.85425 4.85425 0.66 0.00818288 0.00722228 1.06716 0.90034 -1 -1 -1 -1 76 20844 33 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 15.57 4.03457 3.54046 52074 423490 -1 18742 16 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.47 0.38 -1 -1 0.11 0.260053 0.24125 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 14.31 vpr 83.68 MiB -1 -1 3.39 52068 5 1.36 -1 -1 39324 -1 -1 152 193 5 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85688 193 205 2718 2652 1 1315 555 20 20 400 memory auto 44.0 MiB 0.95 22187 10660 223995 81694 118286 24015 83.7 MiB 1.00 0.01 7.82756 5.10197 -2914.56 -5.10197 5.10197 0.30 0.00338005 0.00303666 0.361314 0.32297 -1 -1 -1 -1 76 21455 22 2.07112e+07 1.09319e+07 2.02110e+06 5052.76 4.74 1.15276 1.03306 52074 423490 -1 19292 16 5251 14325 1187541 264668 5.21056 5.21056 -3121.27 -5.21056 -9.98113 -0.359474 2.51807e+06 6295.18 0.07 0.30 0.24 -1 -1 0.07 0.177801 0.166764 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index d0e64cbc176..eafba3af010 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.94 vpr 67.99 MiB -1 -1 0.39 22036 3 0.12 -1 -1 36636 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69620 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.21 0.00 1.86472 -118.834 -1.86472 1.86472 0.24 0.000996678 0.000900839 0.0648293 0.0586504 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.58 0.202532 0.183764 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.06 0.09 -1 -1 0.02 0.0346978 0.0324594 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.66 vpr 66.19 MiB -1 -1 0.21 18444 3 0.06 -1 -1 33260 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67776 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.10 1675 704 66963 20370 32791 13802 66.2 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000579768 0.000542374 0.0417708 0.0391511 -1 -1 -1 -1 40 1453 15 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.160171 0.147086 12666 64609 -1 1222 11 442 668 30453 10334 2.02932 2.02932 -138.236 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0178875 0.0167542 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index 2abafbec4a3..eb67e75c426 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 151.16 vpr 252.22 MiB -1 -1 13.65 124444 5 69.06 -1 -1 68628 -1 -1 1352 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 258272 169 197 21117 21314 1 6442 1718 39 39 1521 clb auto 120.8 MiB 5.85 49865 999363 355164 624898 19301 252.2 MiB 12.58 0.10 3.94387 -15329.6 -3.94387 3.94387 5.65 0.0282487 0.0224608 3.71486 2.98245 -1 -1 -1 -1 38 62474 28 2.4642e+07 2.4336e+07 4.29790e+06 2825.71 27.54 18.235 14.9379 119030 883757 -1 58887 28 30785 67364 2647531 463217 3.72242 3.72242 -16216.3 -3.72242 0 0 5.41627e+06 3561.00 0.27 2.70 0.65 -1 -1 0.27 1.99577 1.72788 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 145.25 vpr 237.36 MiB -1 -1 13.92 124256 5 67.78 -1 -1 68500 -1 -1 1342 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 243060 169 197 21117 21314 1 6530 1708 39 39 1521 clb auto 120.5 MiB 3.79 49914 971183 338147 610049 22987 237.4 MiB 14.52 0.10 3.63479 -14732.8 -3.63479 3.63479 5.35 0.02794 0.0220913 4.48744 3.66675 -1 -1 -1 -1 40 62766 41 7.37824e+07 7.23272e+07 4.31957e+06 2839.95 22.87 16.3688 13.4703 120550 875283 -1 59263 24 31348 67380 2546099 475966 3.57863 3.57863 -15572.9 -3.57863 0 0 5.40678e+06 3554.75 0.57 4.00 1.03 -1 -1 0.57 2.85785 2.46864 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml stereovision0.v common 72.53 vpr 246.70 MiB -1 -1 8.23 120932 5 28.98 -1 -1 65024 -1 -1 1352 169 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 252616 169 197 21117 21314 1 6509 1718 39 39 1521 clb auto 132.6 MiB 3.02 188600 47945 958223 329930 610922 17371 246.7 MiB 6.36 0.07 7.48908 3.85395 -15165.3 -3.85395 3.85395 3.42 0.0181451 0.0155648 1.86364 1.5515 -1 -1 -1 -1 36 61910 50 2.4642e+07 2.4336e+07 4.11737e+06 2707.01 12.81 6.8221 5.66675 115990 821377 -1 57410 21 30914 66833 2643745 477357 3.6821 3.6821 -15912.4 -3.6821 0 0 5.03985e+06 3313.51 0.18 1.66 0.40 -1 -1 0.18 1.17936 1.0401 +k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 70.91 vpr 248.29 MiB -1 -1 7.52 121112 5 28.19 -1 -1 65024 -1 -1 1363 169 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 254252 169 197 21117 21314 1 6565 1729 39 39 1521 clb auto 131.8 MiB 2.87 190099 51107 987164 353007 612737 21420 248.3 MiB 6.23 0.06 9.87654 3.59906 -14959.3 -3.59906 3.59906 3.27 0.0160602 0.0137781 1.82077 1.51774 -1 -1 -1 -1 38 67057 39 7.37824e+07 7.3459e+07 4.16760e+06 2740.04 13.11 6.23411 5.17893 119030 845795 -1 61286 30 33152 70295 2804113 519856 3.34587 3.34587 -15492.9 -3.34587 0 0 5.22668e+06 3436.35 0.18 1.99 0.42 -1 -1 0.18 1.42002 1.25013 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 3a5d60de356..473197a68cf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.5 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.3168e-05 1.5881e-05 0.000156154 0.000121512 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00179937 0.00168173 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00151021 0.00147037 - k6_frac_N10_40nm.xml conn_order.eblif common 0.33 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 2 1 4 5 1 3 4 3 3 9 -1 auto 22.1 MiB 0.00 6 9 4 1 4 60.5 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.6567e-05 1.1555e-05 0.000123665 9.5691e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00181279 0.00171778 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154282 0.00150229 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.28 vpr 58.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59984 3 1 5 6 1 4 5 3 3 9 -1 auto 19.8 MiB 0.00 9 9 12 4 4 4 58.6 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.1225e-05 7.794e-06 8.6604e-05 6.6961e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.00 0.00101901 0.000945649 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00092696 0.000891961 +k6_frac_N10_40nm.xml conn_order.eblif common 0.27 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 2 1 4 5 1 3 4 3 3 9 -1 auto 20.2 MiB 0.00 6 6 9 4 1 4 59.0 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0452e-05 7.093e-06 8.2382e-05 6.3346e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.000974719 0.000907358 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00090434 0.000865615 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index 6afcd280a0b..6639b016754 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.28 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.2578e-05 1.4571e-05 0.000133192 9.8031e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00167256 0.00156119 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00133191 0.00129055 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml eblif_write.eblif common 0.26 vpr 57.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58440 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.7 MiB 0.00 16 14 18 7 10 1 57.1 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3418e-05 8.319e-06 9.1048e-05 6.8306e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.0012188 0.00113608 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000858214 0.00082141 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index 826beb46c2f..8c6f8958beb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.94 vpr 66.02 MiB -1 -1 0.82 27148 5 0.18 -1 -1 36836 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.09 152 432 67 335 30 66.0 MiB 0.04 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000434946 0.000380309 0.00759691 0.00679441 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.0281069 0.0251327 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.16 vpr 64.28 MiB -1 -1 0.41 23672 5 0.11 -1 -1 32960 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 10 2 181 183 1 36 24 6 6 36 clb auto 25.3 MiB 0.04 196 151 534 120 387 27 64.3 MiB 0.04 0.00 2.24505 2.14835 -91.7778 -2.14835 2.14835 0.00 0.000220534 0.00020053 0.00485037 0.00446277 -1 -1 -1 -1 -1 141 16 646728 646728 60312.4 1675.34 0.01 0.0147489 0.0132903 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt index 106e5784d60..765891605f6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.33 vpr 58.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60324 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.4 MiB 0.00 9 9 3 6 0 58.9 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 1.5162e-05 1.0275e-05 0.00029282 0.000262472 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00144752 0.00135246 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00148764 0.00144592 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.27 vpr 57.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58436 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 18.3 MiB 0.00 11 9 9 3 6 0 57.1 MiB 0.00 0.00 3.98683 3.8649 -3.8649 -3.8649 nan 0.00 9.355e-06 5.92e-06 6.6641e-05 4.6524e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00114442 0.00107229 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000890675 0.00085789 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index f0909e951de..d07d79cabc3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.12 vpr 65.83 MiB -1 -1 0.80 26828 5 0.17 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67408 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.03 152 432 67 335 30 65.8 MiB 0.01 0.00 2.15218 -93.3318 -2.15218 2.15218 0.04 0.000541794 0.000472344 0.00646942 0.00583397 -1 -1 -1 -1 8 206 22 646728 646728 33486.6 930.184 0.18 0.0650705 0.0566044 1588 8314 -1 169 20 235 523 16218 5641 2.44258 2.44258 -104.337 -2.44258 0 0 42482.2 1180.06 0.00 0.03 0.01 -1 -1 0.00 0.0191215 0.0169186 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.33 vpr 64.04 MiB -1 -1 0.42 23364 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65580 10 2 181 183 1 36 24 6 6 36 clb auto 24.7 MiB 0.02 196 164 398 79 297 22 64.0 MiB 0.01 0.00 2.2508 2.15218 -91.8425 -2.15218 2.15218 0.01 0.000224237 0.000202847 0.00388388 0.0035963 -1 -1 -1 -1 14 175 18 646728 646728 52871.9 1468.66 0.06 0.031454 0.0271745 1728 14180 -1 158 12 158 364 11157 4123 2.26022 2.26022 -100.753 -2.26022 0 0 63794.4 1772.07 0.00 0.01 0.01 -1 -1 0.00 0.00852136 0.00764565 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place index 70ff5b0f62d..84ede063b47 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place @@ -1,175 +1,181 @@ #block name x y subblk layer block number #---------- -- -- ------ ----- ------------ -o_1_ 4 3 0 0 #0 -o_2_ 1 2 1 0 #1 -o_0_ 3 3 4 0 #2 -n_n1827 3 1 5 0 #3 -n_n1829 3 1 0 0 #4 -n_n1812 1 1 3 0 #5 -n_n1866 3 1 3 0 #6 -n_n1865 4 1 5 0 #7 -[493] 5 4 4 0 #8 -n_n544 4 4 3 0 #9 -n_n416 2 2 2 0 #10 -n_n394 2 1 3 0 #11 -n_n391 2 1 0 0 #12 -n_n300 2 1 1 0 #13 -[260] 3 5 3 0 #14 -n_n437 5 1 3 0 #15 -[223] 3 4 2 0 #16 -[79] 3 5 0 0 #17 -[410] 3 5 4 0 #18 -[516] 4 5 4 0 #19 -[245] 5 5 3 0 #20 -[340] 3 3 5 0 #21 -[432] 3 5 1 0 #22 -[80] 4 4 4 0 #23 -[541] 5 4 2 0 #24 -n_n309 2 1 5 0 #25 -[8] 4 5 1 0 #26 -[546] 4 5 3 0 #27 -n_n706 3 1 2 0 #28 -[261] 3 1 4 0 #29 -[463] 5 2 3 0 #30 -n_n1575 4 5 0 0 #31 -n_n1571 3 4 1 0 #32 -[132] 2 5 4 0 #33 -[355] 3 4 0 0 #34 -[214] 5 3 4 0 #35 -[267] 5 4 0 0 #36 -n_n329 5 1 4 0 #37 -[420] 5 3 1 0 #38 -n_n849 3 1 1 0 #39 -[478] 5 5 0 0 #40 -[578] 1 2 5 0 #41 -[253] 2 3 0 0 #42 -[4] 4 2 0 0 #43 -[56] 1 1 2 0 #44 -[226] 2 2 4 0 #45 -[282] 3 3 2 0 #46 -[377] 1 1 0 0 #47 -[71] 1 1 1 0 #48 -[319] 5 2 0 0 #49 -[233] 2 4 3 0 #50 -[246] 2 4 0 0 #51 -[301] 3 5 5 0 #52 -[441] 2 5 1 0 #53 -[608] 5 4 5 0 #54 -[21] 2 1 2 0 #55 -[311] 4 1 4 0 #56 -[344] 3 2 1 0 #57 -[310] 4 1 3 0 #58 -[315] 4 1 1 0 #59 -[29] 3 2 4 0 #60 -[273] 3 4 5 0 #61 -n_n1690 2 4 4 0 #62 -[383] 4 4 1 0 #63 -[390] 3 2 3 0 #64 -[705] 5 4 3 0 #65 -[41] 5 3 2 0 #66 -[351] 5 2 4 0 #67 -[484] 5 2 5 0 #68 -[437] 5 5 1 0 #69 -[349] 2 3 4 0 #70 -[65] 5 5 4 0 #71 -[221] 4 5 5 0 #72 -[402] 2 4 2 0 #73 -[521] 1 2 0 0 #74 -[767] 4 2 3 0 #75 -[133] 2 5 2 0 #76 -[234] 4 3 4 0 #77 -[868] 3 3 3 0 #78 -[904] 4 3 1 0 #79 -[906] 5 3 3 0 #80 -[919] 4 2 1 0 #81 -[1253] 4 1 0 0 #82 -[1283] 1 2 4 0 #83 -[1340] 3 2 0 0 #84 -[1382] 2 2 5 0 #85 -[1404] 3 2 2 0 #86 -[1417] 1 2 3 0 #87 -[1534] 4 4 2 0 #88 -[1615] 2 5 5 0 #89 -[6947] 3 4 4 0 #90 -[7082] 4 4 0 0 #91 -[7159] 5 2 1 0 #92 -[7165] 5 4 1 0 #93 -[7191] 4 3 2 0 #94 -[7319] 1 3 1 0 #95 -[7321] 3 3 0 0 #96 -[7351] 2 3 5 0 #97 -[7388] 2 2 3 0 #98 -[7423] 2 1 4 0 #99 -[7466] 3 2 5 0 #100 -[7782] 4 3 3 0 #101 -[7822] 3 4 3 0 #102 -[7885] 3 5 2 0 #103 -[7888] 4 2 4 0 #104 -[7997] 5 5 2 0 #105 -[8027] 5 3 0 0 #106 -[50] 2 3 3 0 #107 -[288] 2 3 1 0 #108 -[539] 5 3 5 0 #109 -[372] 4 3 5 0 #110 -n_n1584 2 4 5 0 #111 -[196] 2 3 2 0 #112 -[585] 1 3 2 0 #113 -[365] 4 4 5 0 #114 -[492] 4 2 2 0 #115 -[616] 3 3 1 0 #116 -[430] 2 2 1 0 #117 -[663] 2 2 0 0 #118 -[700] 4 2 5 0 #119 -[322] 1 3 5 0 #120 -[739] 1 3 4 0 #121 -[745] 4 1 2 0 #122 -[771] 2 4 1 0 #123 -[95] 4 5 2 0 #124 -[345] 1 2 2 0 #125 -[759] 1 3 0 0 #126 -[1066] 1 4 3 0 #127 -[7199] 5 2 2 0 #128 -[7969] 2 5 3 0 #129 -[7328] 1 3 3 0 #130 -[7559] 1 4 4 0 #131 -out:o_1_ 6 3 3 0 #132 -out:o_2_ 0 2 3 0 #133 -out:o_0_ 3 6 5 0 #134 -i_30_ 3 6 3 0 #135 -i_20_ 6 5 2 0 #136 -i_9_ 2 0 5 0 #137 -i_10_ 4 0 1 0 #138 -i_7_ 3 6 1 0 #139 -i_8_ 2 0 7 0 #140 -i_5_ 2 0 1 0 #141 -i_6_ 3 0 7 0 #142 -i_27_ 4 6 6 0 #143 -i_14_ 4 6 3 0 #144 -i_3_ 4 6 5 0 #145 -i_28_ 3 0 6 0 #146 -i_13_ 4 6 0 0 #147 -i_4_ 6 1 6 0 #148 -i_25_ 2 6 1 0 #149 -i_12_ 2 0 4 0 #150 -i_1_ 6 1 5 0 #151 -i_26_ 4 0 4 0 #152 -i_11_ 2 0 3 0 #153 -i_2_ 6 1 7 0 #154 -i_23_ 3 6 4 0 #155 -i_18_ 2 0 2 0 #156 -i_24_ 3 0 5 0 #157 -i_17_ 3 6 2 0 #158 -i_0_ 4 0 0 0 #159 -i_21_ 4 6 4 0 #160 -i_16_ 3 6 6 0 #161 -i_22_ 2 0 0 0 #162 -i_32_ 3 0 0 0 #163 -i_31_ 3 6 7 0 #164 -i_34_ 3 6 0 0 #165 -i_33_ 3 0 3 0 #166 -i_19_ 2 0 6 0 #167 -i_36_ 5 6 7 0 #168 -i_35_ 3 0 4 0 #169 -i_38_ 3 0 2 0 #170 -i_29_ 4 6 1 0 #171 -i_37_ 4 0 5 0 #172 +o_1_ 4 1 4 0 #0 +o_2_ 4 3 4 0 #1 +o_0_ 2 2 0 0 #2 +n_n1829 3 5 4 0 #3 +n_n1812 5 3 5 0 #4 +n_n1866 4 5 1 0 #5 +n_n1865 4 5 3 0 #6 +[493] 2 1 2 0 #7 +n_n544 3 1 0 0 #8 +n_n416 4 4 0 0 #9 +n_n394 5 4 5 0 #10 +n_n391 5 3 4 0 #11 +n_n300 4 5 5 0 #12 +[260] 3 2 4 0 #13 +[223] 3 1 4 0 #14 +[79] 2 2 4 0 #15 +[410] 1 3 1 0 #16 +[516] 1 3 2 0 #17 +[530] 1 1 1 0 #18 +[245] 1 2 0 0 #19 +[340] 1 4 4 0 #20 +[432] 3 1 2 0 #21 +[533] 2 3 3 0 #22 +[80] 2 2 5 0 #23 +[535] 1 2 1 0 #24 +n_n316 4 2 4 0 #25 +[541] 1 2 5 0 #26 +n_n1563 2 2 1 0 #27 +n_n1585 2 3 4 0 #28 +[38] 2 3 2 0 #29 +n_n706 4 2 3 0 #30 +n_n608 2 1 1 0 #31 +[261] 4 1 0 0 #32 +[463] 5 1 3 0 #33 +n_n1578 1 2 3 0 #34 +[124] 2 3 1 0 #35 +[132] 3 3 2 0 #36 +[227] 1 1 3 0 #37 +[267] 2 2 2 0 #38 +n_n329 2 2 3 0 #39 +n_n849 4 5 0 0 #40 +[478] 2 3 0 0 #41 +[578] 5 5 0 0 #42 +[253] 5 3 2 0 #43 +[4] 5 4 3 0 #44 +[56] 4 4 3 0 #45 +[226] 4 2 5 0 #46 +[282] 5 4 2 0 #47 +[377] 5 5 4 0 #48 +[71] 5 3 3 0 #49 +[246] 3 2 1 0 #50 +[301] 3 1 1 0 #51 +[311] 4 4 4 0 #52 +[344] 4 4 1 0 #53 +[310] 4 2 2 0 #54 +[315] 4 3 0 0 #55 +[78] 3 5 5 0 #56 +[656] 5 3 0 0 #57 +[29] 2 4 1 0 #58 +[273] 3 1 3 0 #59 +[668] 1 2 4 0 #60 +[674] 5 3 1 0 #61 +[74] 1 2 2 0 #62 +n_n1704 4 1 3 0 #63 +[327] 4 5 2 0 #64 +[305] 1 4 3 0 #65 +n_n1702 4 1 5 0 #66 +[351] 5 2 3 0 #67 +[437] 3 3 3 0 #68 +[349] 5 1 5 0 #69 +[65] 1 1 0 0 #70 +[221] 2 1 5 0 #71 +[343] 3 4 5 0 #72 +[406] 5 2 5 0 #73 +[521] 5 4 0 0 #74 +[161] 3 1 5 0 #75 +[189] 2 4 2 0 #76 +[906] 2 4 3 0 #77 +[977] 4 3 5 0 #78 +[1340] 4 4 5 0 #79 +[1426] 5 2 1 0 #80 +[1435] 5 4 1 0 #81 +[1542] 4 3 3 0 #82 +[1615] 3 4 3 0 #83 +[1619] 4 1 2 0 #84 +[6958] 1 4 2 0 #85 +[7025] 5 2 4 0 #86 +[7082] 1 1 5 0 #87 +[7160] 3 2 2 0 #88 +[7319] 3 4 0 0 #89 +[7321] 4 5 4 0 #90 +[7388] 3 3 0 0 #91 +[7390] 3 5 2 0 #92 +[7787] 1 3 3 0 #93 +[7791] 2 3 5 0 #94 +[7811] 2 1 3 0 #95 +[7822] 4 2 0 0 #96 +[7829] 2 1 4 0 #97 +[7885] 3 4 4 0 #98 +[7899] 1 3 5 0 #99 +[7901] 1 1 4 0 #100 +[7997] 1 3 4 0 #101 +[8027] 2 1 0 0 #102 +[8042] 1 4 1 0 #103 +[50] 3 5 3 0 #104 +[307] 3 2 5 0 #105 +[275] 3 2 3 0 #106 +[372] 3 4 1 0 #107 +[503] 3 5 0 0 #108 +[585] 2 4 4 0 #109 +[63] 2 5 3 0 #110 +[431] 5 2 2 0 #111 +[447] 3 3 1 0 #112 +[615] 2 4 5 0 #113 +n_n1716 1 3 0 0 #114 +[254] 4 3 2 0 #115 +[381] 5 4 4 0 #116 +[430] 4 3 1 0 #117 +[276] 4 4 2 0 #118 +[760] 3 4 2 0 #119 +[768] 4 1 1 0 #120 +[792] 2 5 2 0 #121 +[721] 5 2 0 0 #122 +[877] 3 2 0 0 #123 +[884] 4 2 1 0 #124 +[1021] 3 3 5 0 #125 +[1077] 3 3 4 0 #126 +[1700] 1 4 0 0 #127 +[7108] 2 4 0 0 #128 +[7211] 5 1 1 0 #129 +[7516] 2 5 0 0 #130 +[7531] 2 5 4 0 #131 +[7820] 1 4 5 0 #132 +[7917] 2 5 5 0 #133 +[7028] 2 5 1 0 #134 +[7774] 1 5 5 0 #135 +[7778] 1 5 2 0 #136 +[177] 1 1 2 0 #137 +out:o_1_ 4 0 0 0 #138 +out:o_2_ 4 6 1 0 #139 +out:o_0_ 2 0 4 0 #140 +i_30_ 2 6 7 0 #141 +i_20_ 2 0 3 0 #142 +i_9_ 5 6 5 0 #143 +i_10_ 3 6 6 0 #144 +i_7_ 2 0 5 0 #145 +i_8_ 4 6 4 0 #146 +i_5_ 5 6 6 0 #147 +i_6_ 3 0 3 0 #148 +i_27_ 3 0 1 0 #149 +i_14_ 2 0 1 0 #150 +i_3_ 6 4 5 0 #151 +i_28_ 3 0 7 0 #152 +i_13_ 2 0 2 0 #153 +i_4_ 6 2 7 0 #154 +i_25_ 4 6 0 0 #155 +i_12_ 1 0 4 0 #156 +i_1_ 6 2 2 0 #157 +i_26_ 3 6 2 0 #158 +i_11_ 4 0 1 0 #159 +i_2_ 4 6 7 0 #160 +i_23_ 2 0 7 0 #161 +i_18_ 5 6 4 0 #162 +i_24_ 2 0 6 0 #163 +i_17_ 3 0 0 0 #164 +i_0_ 4 0 5 0 #165 +i_21_ 2 6 1 0 #166 +i_16_ 0 3 0 0 #167 +i_22_ 3 6 0 0 #168 +i_32_ 3 6 7 0 #169 +i_31_ 2 6 5 0 #170 +i_34_ 1 0 6 0 #171 +i_33_ 4 0 7 0 #172 +i_19_ 6 4 6 0 #173 +i_36_ 1 0 1 0 #174 +i_35_ 1 0 7 0 #175 +i_38_ 4 6 3 0 #176 +i_29_ 3 6 1 0 #177 +i_37_ 3 0 6 0 #178 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt index e41ab909d3a..98cc3d128ec 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 14.77 vpr 75.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76916 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.4 MiB 4.62 5572 1135 0 0 1135 75.1 MiB 0.08 0.01 5.10521 -15.0504 -5.10521 nan 0.19 0.00530639 0.00465724 0.0561264 0.0529208 -1 -1 -1 -1 164 7542 34 1.34735e+06 7.11401e+06 957298. 19536.7 7.09 2.13567 1.82713 18546 296938 -1 6979 21 5560 22630 961929 323712 5.65021 nan -16.5347 -5.65021 0 0 1.19720e+06 24432.6 0.05 0.66 0.37 -1 -1 0.05 0.343651 0.311264 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fix_clusters_test_arch.xml apex2.blif common 6.23 vpr 73.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 138 38 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75236 38 3 1916 1919 0 1057 179 7 7 49 clb auto 34.1 MiB 2.35 5571 5572 1187 0 0 1187 73.5 MiB 0.04 0.00 4.76188 4.76188 -14.2451 -4.76188 nan 0.08 0.00208545 0.00186173 0.0310117 0.0298705 -1 -1 -1 -1 158 7466 37 1.34735e+06 7.43737e+06 924312. 18863.5 2.34 0.677508 0.587661 18354 286522 -1 7089 17 5844 24589 1071101 337183 5.3663 nan -15.678 -5.3663 0 0 1.15416e+06 23554.3 0.02 0.27 0.14 -1 -1 0.02 0.139789 0.12986 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index c4013f9bc8c..9b948711612 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.09 vpr 66.02 MiB -1 -1 0.81 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67608 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.06 152 364 33 322 9 66.0 MiB 0.01 0.00 2.14643 -90.9948 -2.14643 2.14643 0.04 0.000424487 0.000372936 0.00685813 0.00616631 -1 -1 -1 -1 12 186 21 646728 646728 19965.4 554.594 0.11 0.0652242 0.0564867 1696 3924 -1 174 15 217 480 10553 3153 2.17275 2.17275 -93.6282 -2.17275 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0180304 0.016231 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 64.27 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32964 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 296 27 253 16 64.3 MiB 0.01 0.00 2.24217 2.14643 -91.5793 -2.14643 2.14643 0.01 0.000335492 0.000314689 0.00350594 0.00327742 -1 -1 -1 -1 14 192 17 646728 646728 22986.6 638.518 0.06 0.0356328 0.0309596 1728 4488 -1 182 16 236 481 10669 3290 2.16575 2.16575 -94.0923 -2.16575 0 0 30529.5 848.041 0.00 0.01 0.00 -1 -1 0.00 0.0100937 0.00903234 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt index ce66e9945a6..23f9598f828 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 1.95 vpr 67.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 14 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 14 8 926 934 0 494 101 11 11 121 -1 mcnc_small 28.1 MiB 0.87 4705 3156 292 2673 191 67.8 MiB 0.15 0.01 4.69669 -33.5098 -4.69669 nan 0.00 0.00334751 0.00291356 0.0814872 0.072816 -1 -1 -1 -1 -1 6609 17 4.36541e+06 4.25763e+06 511363. 4226.14 0.32 0.279395 0.254136 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 1.11 vpr 65.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67296 14 8 926 934 0 487 100 11 11 121 -1 mcnc_small 26.7 MiB 0.56 4953 4661 2884 275 2439 170 65.7 MiB 0.06 0.00 4.90946 4.65107 -32.6907 -4.65107 nan 0.00 0.00127156 0.0011063 0.0300633 0.0277592 -1 -1 -1 -1 -1 6424 17 4.36541e+06 4.20373e+06 511363. 4226.14 0.13 0.110566 0.102078 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt index d59d17d4831..19447432645 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/config.txt @@ -27,3 +27,6 @@ pass_requirements_file=pass_requirements.txt script_params_common=-track_memory_usage --route_chan_width 100 --max_router_iterations 100 --router_lookahead map --flat_routing on script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 +script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index e37401667f7..7eb8d053014 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,3 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.85 vpr 79.08 MiB -1 -1 3.58 35500 16 0.65 -1 -1 38580 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80980 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.0 MiB 3.23 6742 28689 8224 17037 3428 79.1 MiB 0.65 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00310914 0.00279648 0.314019 0.270375 -1 -1 -1 -1 -1 10349 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.50 0.423776 0.367585 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 12.82 vpr 78.98 MiB -1 -1 3.48 35500 16 0.73 -1 -1 38088 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80880 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.1 MiB 3.28 6742 28689 8224 17037 3428 79.0 MiB 0.59 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00230907 0.0018852 0.209392 0.171163 -1 -1 -1 -1 -1 10313 15 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.42 0.342057 0.287674 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 6.01 vpr 77.68 MiB -1 -1 1.68 32288 16 0.36 -1 -1 34604 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79540 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.6 MiB 1.58 10043 6801 30482 8149 18842 3491 77.7 MiB 0.34 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00171355 0.00152094 0.162718 0.14447 -1 -1 -1 -1 -1 10299 11 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 0.88 0.202524 0.179111 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.27 vpr 77.15 MiB -1 -1 1.71 32288 16 0.37 -1 -1 34608 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79000 45 32 1192 1151 1 792 142 14 14 196 memory auto 39.9 MiB 1.64 10043 6801 30482 8149 18842 3491 77.1 MiB 0.39 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00214484 0.00195565 0.196008 0.174756 -1 -1 -1 -1 -1 10115 13 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 0.95 0.248675 0.219198 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.25 vpr 77.65 MiB -1 -1 1.66 31904 16 0.35 -1 -1 34608 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79516 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.6 MiB 1.57 10043 6801 30482 8149 18842 3491 77.7 MiB 0.34 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00177126 0.00157234 0.163228 0.145232 -1 -1 -1 -1 -1 10238 12 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 4.18 0.209091 0.185247 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 9.88 vpr 77.00 MiB -1 -1 1.78 31520 16 0.37 -1 -1 34608 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78844 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.0 MiB 1.62 10043 6801 30482 8149 18842 3491 77.0 MiB 0.35 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00173508 0.00153623 0.165626 0.146946 -1 -1 -1 -1 -1 10238 12 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 4.50 0.217008 0.191955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 8.49 vpr 77.91 MiB -1 -1 1.72 31908 16 0.37 -1 -1 34604 -1 -1 61 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79784 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.6 MiB 1.62 10043 6801 30482 8149 18842 3491 77.9 MiB 0.35 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00171847 0.00152015 0.16361 0.145098 -1 -1 -1 -1 -1 10238 12 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 3.23 0.210793 0.186366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 120190057e8..4e9493beb61 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 28.09 vpr 86.75 MiB -1 -1 4.22 45380 3 0.89 -1 -1 40652 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88832 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.9 MiB 3.72 13488 259154 85177 151229 22748 86.8 MiB 1.98 0.02 4.96832 -2863.05 -4.96832 4.96832 0.58 0.00616009 0.0056108 0.73686 0.651724 -1 -1 -1 -1 70 25183 26 1.65001e+07 9.87633e+06 1.20853e+06 3347.73 11.82 3.63311 3.252 37321 249029 -1 22818 16 6009 15172 1561129 440571 5.14889 5.14889 -3166.68 -5.14889 0 0 1.52253e+06 4217.55 0.11 0.96 0.44 -1 -1 0.11 0.466679 0.43649 - buffered_flyover_wires.xml raygentop.v common 23.51 vpr 86.14 MiB -1 -1 4.32 45316 3 0.90 -1 -1 40936 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88212 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 3.23 13888 238357 80681 139370 18306 86.1 MiB 2.42 0.04 5.12299 -3013.43 -5.12299 5.12299 0.55 0.0104225 0.00890059 0.853806 0.753587 -1 -1 -1 -1 68 27200 39 1.65001e+07 9.87633e+06 1.22105e+06 3382.40 7.94 3.27933 2.93318 36601 236909 -1 22538 20 6241 16122 1654804 449740 5.13382 5.13382 -3162.81 -5.13382 0 0 1.52022e+06 4211.15 0.06 0.81 0.27 -1 -1 0.06 0.458331 0.421893 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +shorted_flyover_wires.xml raygentop.v common 11.46 vpr 85.09 MiB -1 -1 2.03 42452 3 0.51 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87132 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.9 MiB 1.81 27296 13779 258108 83434 152259 22415 85.1 MiB 0.97 0.01 7.04327 4.6633 -2876.07 -4.6633 4.6633 0.21 0.00369266 0.0033896 0.35934 0.327445 -1 -1 -1 -1 66 28610 42 1.65001e+07 9.76854e+06 1.15238e+06 3192.19 3.53 1.25456 1.14436 36241 234685 -1 23562 17 7064 18761 2090675 558075 5.13544 5.13544 -3151.56 -5.13544 0 0 1.43513e+06 3975.42 0.04 0.44 0.14 -1 -1 0.04 0.201995 0.190283 +buffered_flyover_wires.xml raygentop.v common 11.12 vpr 85.59 MiB -1 -1 2.02 42076 3 0.51 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87648 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 46.3 MiB 1.81 27785 13427 264026 91487 153189 19350 85.6 MiB 1.03 0.01 6.32496 5.30188 -3110.04 -5.30188 5.30188 0.22 0.00395257 0.00354299 0.383991 0.348239 -1 -1 -1 -1 68 25731 48 1.65001e+07 9.76854e+06 1.22105e+06 3382.40 3.17 1.46185 1.33293 36601 236909 -1 21906 18 6197 16350 1514118 406281 5.17215 5.17215 -3213.24 -5.17215 0 0 1.52022e+06 4211.15 0.04 0.38 0.15 -1 -1 0.04 0.206095 0.194201 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index dabc7597d44..ae490f43ed2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 6.82 vpr 64.38 MiB -1 -1 0.19 22024 1 0.04 -1 -1 33832 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65924 193 32 545 422 1 386 228 22 22 484 block_FPU auto 25.0 MiB 5.38 4984 53124 22938 29850 336 64.4 MiB 0.31 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00244064 0.00235262 0.159831 0.149979 -1 -1 -1 -1 6456 16.7688 1716 4.45714 553 553 191807 53335 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.692 -2.985 -13.5705 -0.0851 0.36 -1 -1 64.4 MiB 0.06 0.186546 0.175569 64.4 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +hard_fpu_arch_timing.xml mm3.v common 1.28 vpr 62.66 MiB -1 -1 0.11 18300 1 0.03 -1 -1 30628 -1 -1 0 193 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64160 193 32 545 422 1 385 229 30 30 900 block_FPU auto 23.1 MiB 0.16 8272 4968 58329 25699 32293 337 62.7 MiB 0.17 0.00 2.985 2.985 -855.954 -2.985 2.985 0.00 0.00102583 0.000966153 0.089769 0.084748 -1 -1 -1 -1 6670 17.3698 1756 4.57292 533 533 185005 50756 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -882.014 -2.985 -13.6953 -0.0851 0.28 -1 -1 62.7 MiB 0.04 0.107853 0.101999 62.7 MiB -1 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index e0477400548..f345fde64cd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.15 vpr 68.14 MiB -1 -1 0.41 22436 3 0.11 -1 -1 37108 -1 -1 67 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69772 99 130 344 474 1 216 297 13 13 169 clb auto 28.7 MiB 1.30 640 27027 4243 10587 12197 68.1 MiB 0.05 0.00 34 1346 6 0 0 460544. 2725.11 1.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.01 vpr 66.15 MiB -1 -1 0.22 18728 3 0.06 -1 -1 33276 -1 -1 67 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67736 99 130 344 474 1 217 297 13 13 169 clb auto 26.3 MiB 0.76 1670 634 27027 2767 7163 17097 66.1 MiB 0.02 0.00 34 1203 16 0 0 460544. 2725.11 0.23 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index cf73f2ff4e0..247acfa46dc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.78 vpr 66.14 MiB -1 -1 0.81 27148 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67724 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000401166 0.00034964 0.00709766 0.00632609 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.027091 0.0241271 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.06 vpr 63.98 MiB -1 -1 0.41 23428 5 0.10 -1 -1 32964 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65516 10 2 181 183 1 36 24 6 6 36 clb auto 24.6 MiB 0.02 196 151 534 120 387 27 64.0 MiB 0.01 0.00 2.24505 2.14835 -91.7778 -2.14835 2.14835 0.00 0.000222636 0.000202558 0.0047703 0.00439302 -1 -1 -1 -1 -1 141 16 646728 646728 60312.4 1675.34 0.01 0.01476 0.0132928 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index f56e6001d52..79a3b00fa18 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.43 vpr 60.44 MiB -1 -1 -1 -1 0 0.02 -1 -1 33044 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61892 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.1 MiB 0.00 0 3 0 0 3 60.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4987e-05 8.361e-06 8.9733e-05 6.0433e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00144709 0.00137547 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.48 vpr 60.32 MiB -1 -1 -1 -1 0 0.02 -1 -1 33032 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61768 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.0 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3826e-05 7.652e-06 8.7137e-05 5.7527e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00164227 0.00157106 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.51 vpr 60.30 MiB -1 -1 -1 -1 0 0.02 -1 -1 33252 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61752 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2976e-05 6.744e-06 7.713e-05 4.9652e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00173371 0.00166423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.39 vpr 60.55 MiB -1 -1 -1 -1 0 0.02 -1 -1 33080 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62004 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2909e-05 6.758e-06 8.8443e-05 5.844e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00166613 0.00149072 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.39 vpr 60.46 MiB -1 -1 -1 -1 1 0.02 -1 -1 33424 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 2 1 3 4 0 3 4 3 3 9 -1 auto 22.1 MiB 0.00 9 9 3 3 3 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.603e-05 1.0932e-05 0.000113667 8.4174e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00156248 0.00148561 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.53 vpr 60.38 MiB -1 -1 -1 -1 1 0.06 -1 -1 35020 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61832 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.4 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.1156e-05 1.5721e-05 0.000164706 0.000132685 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.0021653 0.00196366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.54 vpr 60.58 MiB -1 -1 -1 -1 1 0.06 -1 -1 35532 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 5 1 6 7 0 6 7 3 3 9 -1 auto 22.3 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.769e-05 2.1131e-05 0.000172602 0.000136847 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00216675 0.00196156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.35 vpr 60.45 MiB -1 -1 -1 -1 1 0.02 -1 -1 33200 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61900 3 1 5 6 1 4 5 3 3 9 -1 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17 12 53894 53894 38783.3 4309.26 0.00 0.00342842 0.00312147 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x4.blif common 0.46 vpr 60.50 MiB -1 -1 -1 -1 2 0.06 -1 -1 35480 -1 -1 3 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61952 7 8 22 30 0 15 18 4 4 16 clb auto 22.0 MiB 0.01 51 64 26 37 1 60.5 MiB 0.00 0.00 1.24888 -7.62396 -1.24888 nan 0.00 9.577e-05 8.3665e-05 0.00076909 0.000710256 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00462233 0.00417537 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_4x4.blif common 0.59 vpr 60.60 MiB -1 -1 -1 -1 4 0.09 -1 -1 35628 -1 -1 2 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 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5 1 60.2 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 1.5359e-05 1.1242e-05 0.000119111 9.5167e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00191506 0.00178438 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_2bit.blif common 0.51 vpr 60.47 MiB -1 -1 -1 -1 1 0.06 -1 -1 35224 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61920 5 3 8 11 0 8 9 3 3 9 -1 auto 22.0 MiB 0.00 24 27 21 6 0 60.5 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 5.5301e-05 4.4627e-05 0.000313259 0.000267198 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00296269 0.00261801 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_3bit.blif common 0.50 vpr 60.56 MiB -1 -1 -1 -1 2 0.05 -1 -1 35444 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62016 7 4 12 16 0 11 12 3 3 9 -1 auto 22.1 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 2.6083e-05 2.0859e-05 0.000215587 0.000188913 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00234895 0.0022029 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_4bit.blif common 0.54 vpr 60.64 MiB -1 -1 -1 -1 2 0.06 -1 -1 35364 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62096 9 5 15 20 0 14 15 3 3 9 -1 auto 22.1 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 0.000111332 9.9634e-05 0.000559539 0.000502391 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00351338 0.00318651 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_5bit.blif common 0.52 vpr 60.46 MiB -1 -1 -1 -1 3 0.07 -1 -1 35520 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 11 6 19 25 0 17 18 3 3 9 -1 auto 22.0 MiB 0.01 51 64 33 24 7 60.5 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 0.000697205 8.3358e-05 0.00115444 0.000499005 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00500091 0.00398839 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.35 vpr 58.06 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59452 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.6 MiB 0.00 0 0 3 0 0 3 58.1 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.359e-06 3.476e-06 5.5645e-05 3.585e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000873938 0.000817223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.31 vpr 58.67 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.3e-06 3.512e-06 5.499e-05 3.6206e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000892963 0.000836486 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.35 vpr 58.60 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60008 6 1 1 8 0 1 8 3 3 9 -1 auto 20.2 MiB 0.00 0 0 21 0 10 11 58.6 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.343e-06 3.449e-06 5.5257e-05 3.6332e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00089067 0.000837628 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 vpr 58.66 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 6 1 1 8 0 1 8 3 3 9 -1 auto 19.9 MiB 0.00 0 0 21 0 10 11 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.587e-06 3.716e-06 5.4406e-05 3.4996e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000917158 0.000862935 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.36 vpr 59.04 MiB -1 -1 -1 -1 1 0.02 -1 -1 29952 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 2 1 3 4 0 3 4 3 3 9 -1 auto 20.2 MiB 0.00 9 9 9 3 3 3 59.0 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 8.998e-06 5.729e-06 7.4084e-05 5.5177e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000991073 0.000933863 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.38 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31488 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 5 1 6 7 0 6 7 3 3 9 -1 auto 20.2 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 3.9064e-05 8.628e-06 0.000128172 7.9888e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00115707 0.0010134 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.38 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31844 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 5 1 6 7 0 6 7 3 3 9 -1 auto 20.2 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.2372e-05 8.797e-06 0.000102625 8.1155e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00116441 0.00104858 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.29 vpr 58.64 MiB -1 -1 -1 -1 1 0.02 -1 -1 30396 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60048 3 1 5 6 1 4 5 3 3 9 -1 auto 19.8 MiB 0.00 9 9 12 7 1 4 58.6 MiB 0.00 0.00 0.603526 0.52647 -0.88231 -0.52647 0.52647 0.00 1.0705e-05 7.341e-06 8.8486e-05 6.7399e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000959409 0.00089725 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.39 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31812 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 4 1 4 6 0 4 6 3 3 9 -1 auto 20.5 MiB 0.00 12 12 15 9 3 3 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 9.788e-06 6.583e-06 8.1737e-05 6.1503e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.0010608 0.000952163 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_2x2.blif common 0.39 vpr 58.68 MiB -1 -1 -1 -1 1 0.03 -1 -1 31488 -1 -1 1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60092 4 4 8 12 0 8 9 3 3 9 -1 auto 19.9 MiB 0.00 24 24 27 18 6 3 58.7 MiB 0.00 0.00 0.749366 0.67231 -2.68924 -0.67231 nan 0.00 1.8939e-05 1.3649e-05 0.000162092 0.000138463 -1 -1 -1 -1 -1 12 10 53894 53894 38783.3 4309.26 0.00 0.00140862 0.00128245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.37 vpr 58.71 MiB -1 -1 -1 -1 1 0.04 -1 -1 31968 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60120 6 6 12 18 0 12 13 3 3 9 -1 auto 19.9 MiB 0.00 36 36 43 32 7 4 58.7 MiB 0.00 0.00 0.775365 0.69831 -4.13786 -0.69831 nan 0.00 2.7335e-05 2.2775e-05 0.000258357 0.000231618 -1 -1 -1 -1 -1 15 12 53894 53894 38783.3 4309.26 0.00 0.00192479 0.00174204 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.42 vpr 58.85 MiB -1 -1 -1 -1 2 0.04 -1 -1 32096 -1 -1 3 7 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60264 7 8 22 30 0 15 18 4 4 16 clb auto 20.2 MiB 0.01 62 51 64 26 37 1 58.9 MiB 0.00 0.00 1.24888 1.24888 -7.62396 -1.24888 nan 0.00 4.707e-05 4.1118e-05 0.000466731 0.00043626 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00249603 0.0023213 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.42 vpr 58.89 MiB -1 -1 -1 -1 4 0.05 -1 -1 32476 -1 -1 2 8 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60300 8 8 29 37 0 21 18 4 4 16 clb auto 19.9 MiB 0.01 82 74 64 20 44 0 58.9 MiB 0.00 0.00 2.04839 2.04839 -11.7951 -2.04839 nan 0.00 6.5626e-05 5.6815e-05 0.000641099 0.000602927 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.00 0.00383531 0.00351223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.48 vpr 59.06 MiB -1 -1 -1 -1 4 0.05 -1 -1 32832 -1 -1 4 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60480 10 10 47 57 0 39 24 4 4 16 clb auto 19.9 MiB 0.01 161 149 92 35 57 0 59.1 MiB 0.00 0.00 2.80144 2.73035 -18.1288 -2.73035 nan 0.00 9.8348e-05 8.8676e-05 0.000979759 0.000931858 -1 -1 -1 -1 -1 120 10 215576 215576 99039.1 6189.95 0.01 0.00519014 0.00479486 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.53 vpr 59.55 MiB -1 -1 -1 -1 5 0.08 -1 -1 32920 -1 -1 5 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60984 11 11 61 72 0 49 27 5 5 25 clb auto 20.2 MiB 0.02 227 192 427 90 337 0 59.6 MiB 0.00 0.00 3.28962 3.19291 -21.0185 -3.19291 nan 0.00 0.000128815 0.000117588 0.00236378 0.00220408 -1 -1 -1 -1 -1 193 14 485046 269470 186194. 7447.77 0.01 0.00880785 0.00804809 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.40 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31076 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 3 2 5 7 0 5 6 3 3 9 -1 auto 19.9 MiB 0.00 15 15 15 9 5 1 58.7 MiB 0.00 0.00 0.749366 0.67231 -1.34462 -0.67231 nan 0.00 1.2467e-05 8.835e-06 0.000106543 8.3665e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00119604 0.00107178 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.37 vpr 58.68 MiB -1 -1 -1 -1 1 0.03 -1 -1 32244 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60092 5 3 8 11 0 8 9 3 3 9 -1 auto 20.2 MiB 0.00 24 24 27 21 6 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -2.01693 -0.67231 nan 0.00 1.8254e-05 1.2993e-05 0.000148648 0.000125027 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.0014931 0.0013283 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.38 vpr 58.69 MiB -1 -1 -1 -1 2 0.03 -1 -1 32240 -1 -1 1 7 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60100 7 4 12 16 0 11 12 3 3 9 -1 auto 20.2 MiB 0.00 33 33 38 24 11 3 58.7 MiB 0.00 0.00 1.08437 1.08437 -4.00246 -1.08437 nan 0.00 2.2984e-05 1.8516e-05 0.000207845 0.000175806 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00145538 0.00134835 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.41 vpr 58.46 MiB -1 -1 -1 -1 2 0.04 -1 -1 32252 -1 -1 1 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59868 9 5 15 20 0 14 15 3 3 9 -1 auto 20.1 MiB 0.00 42 42 51 29 17 5 58.5 MiB 0.00 0.00 1.08437 1.00731 -4.36655 -1.00731 nan 0.00 2.742e-05 2.2732e-05 0.000248101 0.000222336 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.0019693 0.00177377 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.38 vpr 58.76 MiB -1 -1 -1 -1 3 0.04 -1 -1 32252 -1 -1 1 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60168 11 6 19 25 0 17 18 3 3 9 -1 auto 19.9 MiB 0.00 51 51 64 36 21 7 58.8 MiB 0.00 0.00 1.41937 1.34231 -6.71386 -1.34231 nan 0.00 3.3633e-05 2.7198e-05 0.000306471 0.000277811 -1 -1 -1 -1 -1 21 11 53894 53894 38783.3 4309.26 0.00 0.00206016 0.00187465 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index b020b50a0e5..1ecd9f11e08 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.27 vpr 60.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61896 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.1 MiB 0.00 0 3 0 0 3 60.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1967e-05 6.442e-06 7.5021e-05 4.7762e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.0014839 0.00141592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2368e-05 6.553e-06 8.0604e-05 5.2726e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00150763 0.00143643 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.26 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4901e-05 1.736e-05 0.000158286 0.000127589 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00189837 0.00180984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4603e-05 1.7125e-05 0.000156465 0.000123185 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00157342 0.00148859 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.34 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 5 1 6 7 0 6 7 3 3 9 -1 auto 22.3 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.3071e-05 1.7468e-05 0.00015565 0.000122418 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00131998 0.0012364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4504e-05 1.843e-05 0.0003637 0.000327179 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00295184 0.00278863 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.23 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.342e-06 3.456e-06 5.6768e-05 3.7362e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000896307 0.000835936 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.23 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.9 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.496e-06 3.551e-06 5.473e-05 3.5509e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000856124 0.000804075 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.22 vpr 58.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59692 6 1 7 8 0 7 8 3 3 9 -1 auto 19.9 MiB 0.00 21 21 21 14 7 0 58.3 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.3219e-05 8.724e-06 9.8134e-05 7.7659e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.000949863 0.000887812 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.22 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 6 1 7 8 0 7 8 3 3 9 -1 auto 20.2 MiB 0.00 21 21 21 14 7 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.3984e-05 9.157e-06 9.9693e-05 7.937e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00102012 0.000957668 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.25 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 5 1 6 7 0 6 7 3 3 9 -1 auto 19.9 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2769e-05 9.287e-06 9.9591e-05 7.789e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.000993215 0.000930904 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.26 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60080 5 1 6 7 0 6 7 3 3 9 -1 auto 19.8 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2704e-05 9.014e-06 9.8711e-05 7.7635e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00102457 0.00096424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index 0122eef07c9..61460af32b8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 2.14 vpr 66.94 MiB -1 -1 0.82 26648 5 0.18 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.08 154 69 23 41 5 66.9 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000368162 0.000336195 0.00306832 0.0028942 -1 -1 -1 -1 8 112 5 646728 377258 -1 -1 0.14 0.0630721 0.0541641 1804 2280 -1 112 3 60 81 2140 1007 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0123441 0.0115171 - x_uniform_y_gaussian.xml stereovision3.v common 2.28 vpr 66.56 MiB -1 -1 0.87 27028 5 0.18 -1 -1 36836 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68156 10 2 181 183 1 37 19 6 6 36 clb auto 27.6 MiB 0.06 139 119 44 63 12 66.6 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000434392 0.000379213 0.00478977 0.00443186 -1 -1 -1 -1 8 108 4 646728 377258 -1 -1 0.14 0.0614636 0.053576 1804 2280 -1 92 5 93 129 3144 1427 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0131686 0.0124064 - x_gaussian_y_gaussian.xml stereovision3.v common 1.95 vpr 66.73 MiB -1 -1 0.78 27032 5 0.16 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 141 69 21 42 6 66.7 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000231421 0.000200473 0.00279286 0.00262007 -1 -1 -1 -1 6 107 4 646728 377258 -1 -1 0.13 0.0525266 0.046082 1804 2280 -1 105 4 77 102 2777 1152 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.0109087 0.0101911 - x_delta_y_uniform.xml stereovision3.v common 2.13 vpr 66.94 MiB -1 -1 0.67 26768 5 0.15 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.07 154 369 96 253 20 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000435432 0.00038302 0.00911423 0.00823072 -1 -1 -1 -1 24 117 4 646728 377258 -1 -1 0.31 0.174316 0.150618 1804 2280 -1 116 2 59 79 2150 954 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153537 0.0147732 - x_delta_y_delta.xml stereovision3.v common 2.28 vpr 66.92 MiB -1 -1 0.81 26892 5 0.18 -1 -1 36968 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68524 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.10 140 544 127 376 41 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000465798 0.000412818 0.0124105 0.0110487 -1 -1 -1 -1 48 106 2 646728 377258 -1 -1 0.23 0.117282 0.102085 1804 2280 -1 106 2 57 77 1975 772 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00952273 0.00912406 - x_uniform_y_delta.xml stereovision3.v common 2.20 vpr 66.74 MiB -1 -1 0.80 27028 5 0.22 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68344 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 127 494 89 373 32 66.7 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000426768 0.000373257 0.0117897 0.0105633 -1 -1 -1 -1 14 88 2 646728 377258 -1 -1 0.16 0.10372 0.0914305 1804 2280 -1 88 2 57 77 1819 773 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00845179 0.00814396 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +x_gaussian_y_uniform.xml stereovision3.v common 1.36 vpr 64.43 MiB -1 -1 0.49 23052 5 0.11 -1 -1 32972 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 10 2 181 183 1 38 19 6 6 36 clb auto 25.4 MiB 0.03 174 128 319 80 215 24 64.4 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000210252 0.000191555 0.00433045 0.0040507 -1 -1 -1 -1 8 83 5 646728 377258 -1 -1 0.05 0.0286843 0.0251732 1804 2280 -1 86 4 94 125 2948 1117 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00698257 0.00662571 +x_uniform_y_gaussian.xml stereovision3.v common 1.34 vpr 65.04 MiB -1 -1 0.41 23292 5 0.10 -1 -1 33008 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66604 10 2 181 183 1 38 19 6 6 36 clb auto 26.0 MiB 0.03 174 125 394 105 261 28 65.0 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000217937 0.000198402 0.00515017 0.00479852 -1 -1 -1 -1 6 93 11 646728 377258 -1 -1 0.07 0.0334088 0.0293253 1804 2280 -1 82 3 62 84 2005 787 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00687978 0.00657072 +x_gaussian_y_gaussian.xml stereovision3.v common 1.31 vpr 65.10 MiB -1 -1 0.41 23440 5 0.11 -1 -1 32940 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 10 2 181 183 1 38 19 6 6 36 clb auto 25.7 MiB 0.03 174 133 319 65 242 12 65.1 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000225609 0.000205573 0.004477 0.00418391 -1 -1 -1 -1 6 107 5 646728 377258 -1 -1 0.06 0.0291106 0.0255214 1804 2280 -1 95 6 98 132 3372 1383 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00753689 0.00707645 +x_delta_y_uniform.xml stereovision3.v common 1.31 vpr 64.97 MiB -1 -1 0.42 23052 5 0.11 -1 -1 32980 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66528 10 2 181 183 1 38 19 6 6 36 clb auto 25.9 MiB 0.03 174 147 69 22 43 4 65.0 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000228718 0.00020709 0.00234451 0.00224898 -1 -1 -1 -1 14 107 3 646728 377258 -1 -1 0.04 0.0265392 0.0232934 1804 2280 -1 107 3 66 90 2381 972 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00673078 0.00642275 +x_delta_y_delta.xml stereovision3.v common 1.32 vpr 65.40 MiB -1 -1 0.41 23432 5 0.11 -1 -1 33148 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 10 2 181 183 1 38 19 6 6 36 clb auto 26.1 MiB 0.03 174 131 269 71 179 19 65.4 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000219412 0.000199508 0.00413631 0.00388102 -1 -1 -1 -1 24 87 3 646728 377258 -1 -1 0.04 0.0278594 0.0245156 1804 2280 -1 86 2 58 78 1869 774 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.0064994 0.00624883 +x_uniform_y_delta.xml stereovision3.v common 1.32 vpr 64.94 MiB -1 -1 0.42 23052 5 0.10 -1 -1 32976 -1 -1 7 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66500 10 2 181 183 1 38 19 6 6 36 clb auto 25.9 MiB 0.03 174 128 369 99 241 29 64.9 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000220849 0.000200914 0.00495943 0.00462535 -1 -1 -1 -1 24 82 2 646728 377258 -1 -1 0.04 0.0283483 0.0249661 1804 2280 -1 82 2 59 79 1850 830 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00721289 0.00692991 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 93fc1046440..83ca6e84d6c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.95 vpr 65.89 MiB -1 -1 0.73 26760 5 0.17 -1 -1 36900 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67476 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.04 153 500 90 382 28 65.9 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000660248 0.000574242 0.010203 0.00905969 -1 -1 -1 -1 6 103 13 646728 646728 -1 -1 0.12 0.059948 0.0525698 1456 2040 -1 101 16 136 266 9131 3659 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0191372 0.0164753 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.99 vpr 66.10 MiB -1 -1 0.79 27276 5 0.17 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67688 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 148 466 75 365 26 66.1 MiB 0.01 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000394392 0.000346251 0.00742774 0.00666175 -1 -1 -1 -1 8 100 16 646728 646728 -1 -1 0.14 0.0718777 0.0632492 1456 2040 -1 101 19 134 278 9113 3613 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0163481 0.014725 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 2.10 vpr 66.14 MiB -1 -1 0.85 26896 5 0.16 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67728 10 2 181 183 1 35 24 6 6 36 clb auto 27.1 MiB 0.05 142 500 108 364 28 66.1 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000538248 0.000486042 0.00902515 0.00805903 -1 -1 -1 -1 4 86 10 646728 646728 -1 -1 0.05 0.0281105 0.0249862 1456 2040 -1 87 9 108 188 5936 2196 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153203 0.0141626 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 64.18 MiB -1 -1 0.40 23288 5 0.11 -1 -1 32972 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 169 92 28 59 5 64.2 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000222832 0.000202358 0.00189553 0.00180424 -1 -1 -1 -1 6 131 18 646728 646728 -1 -1 0.07 0.0299729 0.0258466 1456 2040 -1 122 14 118 244 8464 3501 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00939131 0.00846423 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.30 vpr 64.65 MiB -1 -1 0.40 23432 5 0.10 -1 -1 33060 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 10 2 181 183 1 36 24 6 6 36 clb auto 25.4 MiB 0.02 196 163 296 52 224 20 64.7 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000228208 0.000207579 0.00320945 0.00299815 -1 -1 -1 -1 8 116 21 646728 646728 -1 -1 0.07 0.0318341 0.0274652 1456 2040 -1 116 18 143 312 10670 4334 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0103289 0.00920865 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.40 vpr 64.28 MiB -1 -1 0.48 23288 5 0.11 -1 -1 32952 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 150 398 89 285 24 64.3 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000226121 0.000205896 0.00396848 0.00369334 -1 -1 -1 -1 6 101 8 646728 646728 -1 -1 0.05 0.0290504 0.0252608 1456 2040 -1 102 10 126 245 7156 2526 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00790433 0.00720692 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt index afb5b419a6b..f07c0f7fced 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 5.23 vpr 66.07 MiB -1 -1 0.81 27256 5 0.19 -1 -1 36672 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67656 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 1.88 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000389361 0.000337837 0.00712682 0.00635643 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.83 0.023313 0.0208517 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.46 vpr 64.65 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32960 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66200 10 2 181 183 1 36 24 6 6 36 clb auto 25.3 MiB 0.02 196 160 398 88 284 26 64.6 MiB 1.20 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.00022322 0.000202277 0.00402302 0.00372354 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.60 0.0145321 0.0130932 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index 0cf367e9bdb..6488588daa2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 61.52 MiB -1 -1 0.73 27008 5 0.16 -1 -1 36840 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63000 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.06 123 1025 767 190 68 61.5 MiB 0.03 0.00 2.0306 -84.8829 -2.0306 2.0306 0.02 0.000393487 0.000346106 0.0203419 0.0179997 -1 -1 -1 -1 24 106 9 485046 377258 28445.8 1137.83 0.08 0.0705347 0.0617863 1707 5297 -1 110 10 80 114 1470 618 1.99984 1.99984 -90.3874 -1.99984 0 0 37126.9 1485.07 0.00 0.02 0.01 -1 -1 0.00 0.0158626 0.0146013 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml stereovision3.v common 1.30 vpr 59.75 MiB -1 -1 0.41 23292 5 0.11 -1 -1 32980 -1 -1 7 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61184 10 2 181 183 1 38 19 5 5 25 clb auto 20.2 MiB 0.03 159 125 1025 754 215 56 59.8 MiB 0.02 0.00 2.0306 2.0306 -85.6043 -2.0306 2.0306 0.01 0.00022991 0.000209474 0.0111608 0.0101844 -1 -1 -1 -1 22 124 12 485046 377258 26278.6 1051.14 0.05 0.0381372 0.0332965 1659 4669 -1 117 9 73 106 1326 594 1.98035 1.98035 -88.0122 -1.98035 0 0 33449.3 1337.97 0.00 0.01 0.00 -1 -1 0.00 0.00879543 0.00815896 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 891302c2b5a..b41137fb06f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 17.21 vpr 71.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72880 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.3 MiB 0.39 10472 141533 36950 100839 3744 71.2 MiB 1.37 0.02 7.46482 -1369.01 -7.46482 7.46482 0.56 0.00521343 0.00460525 0.3928 0.329697 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.35 2.1497 1.85535 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.84 0.19 -1 -1 0.04 0.261179 0.233132 - k4_N4_90nm.xml ex5p.blif common 19.31 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68632 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.35 12004 99857 28319 69545 1993 67.0 MiB 0.94 0.02 6.86459 -313.968 -6.86459 nan 0.53 0.00337095 0.00291084 0.218826 0.187023 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 13.54 0.813128 0.698644 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.07 1.22 0.29 -1 -1 0.07 0.185657 0.165735 - k4_N4_90nm.xml s298.blif common 16.74 vpr 73.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 75068 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.1 MiB 0.44 13813 156389 45768 109723 898 73.3 MiB 1.71 0.02 12.2682 -96.384 -12.2682 12.2682 0.97 0.00611806 0.00498358 0.468986 0.387941 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 9.00 1.38473 1.15574 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.09 1.18 0.31 -1 -1 0.09 0.19019 0.169418 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml diffeq.blif common 4.77 vpr 71.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72796 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.6 MiB 0.17 24088 10407 135291 36283 95683 3325 71.1 MiB 0.54 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.20 0.00204037 0.00175241 0.138253 0.119973 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.35 0.423016 0.368466 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.30 0.08 -1 -1 0.02 0.0915204 0.0830254 +k4_N4_90nm.xml ex5p.blif common 6.43 vpr 66.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67608 8 63 1072 1135 0 892 433 22 22 484 clb auto 26.5 MiB 0.13 20089 11891 97016 28068 66779 2169 66.0 MiB 0.40 0.01 11.9965 7.14697 -323.69 -7.14697 nan 0.18 0.00132575 0.00117704 0.0896217 0.0802147 -1 -1 -1 -1 32 16897 50 891726 807012 949946. 1962.70 4.19 0.332063 0.290275 43920 162796 -1 13798 21 8357 30046 2938323 715872 6.93884 nan -322.607 -6.93884 0 0 1.22393e+06 2528.78 0.04 0.44 0.09 -1 -1 0.04 0.0723896 0.0654424 +k4_N4_90nm.xml s298.blif common 8.59 vpr 72.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 579 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73820 4 6 1942 1948 1 1135 589 27 27 729 clb auto 32.0 MiB 0.19 26761 13173 158541 45950 111660 931 72.1 MiB 0.65 0.01 27.8284 12.5893 -95.8017 -12.5893 12.5893 0.28 0.00228242 0.00194389 0.165963 0.143503 -1 -1 -1 -1 24 18368 39 1.39333e+06 1.29078e+06 1.12265e+06 1539.99 5.38 0.550834 0.474162 54650 192211 -1 15957 20 8308 43971 3554658 708435 12.1943 12.1943 -92.9601 -12.1943 0 0 1.47093e+06 2017.74 0.02 0.58 0.11 -1 -1 0.02 0.116729 0.105328 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index 639ae9a9ce5..0e878ef14f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.46 vpr 69.17 MiB -1 -1 0.83 26540 4 0.20 -1 -1 36184 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.25 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.00065953 0.000573934 0.00619824 0.00583905 -1 -1 -1 -1 399 5.32000 131 1.74667 151 217 4511 1215 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.12 0.1152 0.11141 69.2 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.32 vpr 67.17 MiB -1 -1 0.41 23076 4 0.10 -1 -1 32984 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68784 11 2 303 283 2 82 28 7 7 49 clb auto 27.4 MiB 0.11 424 278 994 204 585 205 67.2 MiB 0.02 0.00 4.1851 4.05951 0 0 3.91314 0.00 0.000345438 0.000313951 0.0112699 0.0104324 -1 -1 -1 -1 318 4.18421 118 1.55263 161 242 4599 1282 1.07788e+06 808410 219490. 4479.39 5 5100 32136 -1 4.18749 3.93845 0 0 -197.86 -1.707 0.02 -1 -1 67.2 MiB 0.07 0.0774666 0.0747377 67.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt index dbceb44a4dc..6e72a741485 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt @@ -26,4 +26,8 @@ pass_requirements_file=pass_requirements_multiclock.txt script_params_common=-starting_stage vpr -sdc_file tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/multiclock.sdc script_params_list_add = +script_params_list_add = --route_chan_width 30 -check_incremental_sta_consistency script_params_list_add = --router_algorithm parallel --num_workers 4 +# script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +# script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +# script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 7e566048732..86cec1613d1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,4 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--route_chan_width_30_-check_incremental_sta_consistency 1.3344 0.595 0.781297 -1 -1 0.57 0.757256 -1 1.3344 -1 1.16524 -1 1.77873 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.6593 -1 -1 0.268 3.18526 -1 1.18303 -1 3.40324 -1 -1.46764 -1 -1 -1 -1 k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index 4db4b05c471..a7808c8d24d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.05 vpr 68.36 MiB -1 -1 0.39 22432 3 0.12 -1 -1 36928 -1 -1 65 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70000 99 130 344 474 1 215 295 12 12 144 clb auto 29.2 MiB 0.19 685 24820 3391 8404 13025 68.4 MiB 0.05 0.00 32 1772 8 5.66058e+06 4.05111e+06 305575. 2122.05 1.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.32 vpr 66.69 MiB -1 -1 0.22 18840 3 0.06 -1 -1 33104 -1 -1 65 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68288 99 130 344 474 1 215 295 12 12 144 clb auto 27.3 MiB 0.07 1546 614 23839 3086 6279 14474 66.7 MiB 0.02 0.00 38 1473 8 5.66058e+06 4.05111e+06 345440. 2398.89 0.20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt index 59b02c3fd0e..3a223b5cf9f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links - stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 104.06 vpr 1.07 GiB -1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1126272 2 32 2204 1661 1 1102 107 36 20 720 -1 EP4SGX110 955.6 MiB 4.04 6649 10733 2374 7396 963 1099.9 MiB 0.85 0.01 7.22684 -4978.81 -7.22684 7.22684 14.03 0.00387297 0.00336653 0.329346 0.282395 154 8599 14 0 0 6.94291e+06 9642.93 42.85 2.6403 2.32523 176404 1494154 -1 8630 10 2443 4554 1083511 308854 7.50808 7.50808 -5329.84 -7.50808 0 0 8.91809e+06 12386.2 1.07 0.65 2.72 -1 -1 1.07 0.27806 0.251316 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 +arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links +stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 40.63 vpr 1.07 GiB -1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1124608 2 32 2204 1661 1 1104 108 36 20 720 -1 EP4SGX110 954.6 MiB 2.03 15097 6710 12958 2982 8805 1171 1098.2 MiB 0.42 0.01 8.01944 7.31997 -4968.85 -7.31997 7.31997 5.35 0.00271249 0.00239307 0.162656 0.143711 154 8889 12 0 0 6.94291e+06 9642.93 8.24 0.999967 0.885649 176404 1494154 -1 8829 14 2492 4758 998347 275320 7.64666 7.64666 -5202.88 -7.64666 0 0 8.91809e+06 12386.2 0.44 0.31 1.33 -1 -1 0.44 0.140458 0.130997 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index b67a185d189..08e549a0cfe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.76 vpr 66.03 MiB -1 -1 0.86 26892 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186164 0.0017947 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.10 vpr 64.27 MiB -1 -1 0.42 23432 5 0.11 -1 -1 33216 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00102325 0.000991048 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 153be88f8d6..ced45279053 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.90 vpr 66.02 MiB -1 -1 0.83 26896 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000402396 0.000353615 0.00726063 0.00647248 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00909673 0.00824277 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.08 vpr 64.28 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32960 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 151 500 122 353 25 64.3 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000220907 0.000200935 0.00457561 0.00422076 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00559149 0.00520404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt index 6e6ab2e273c..0495632427e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 0.60 vpr 60.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62244 11 11 59 70 0 48 26 4 4 16 clb auto 22.1 MiB 0.03 179 862 260 602 0 60.8 MiB 0.02 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000312912 0.000279273 0.00803541 0.00727675 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.11 0.0569851 0.0502764 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.01 0.00 -1 -1 0.00 0.0102047 0.00933765 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.06 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23944 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.3 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml mult_5x6.blif common 0.38 vpr 59.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60668 11 11 59 70 0 48 26 4 4 16 clb auto 20.2 MiB 0.02 205 178 672 211 461 0 59.2 MiB 0.01 0.00 2.48509 2.46139 -19.889 -2.46139 nan 0.01 0.000116739 0.000106346 0.00301039 0.00279891 -1 -1 -1 -1 30 215 23 215576 215576 18771.3 1173.21 0.04 0.0201992 0.0174425 1016 3020 -1 186 15 222 505 8959 4790 2.75695 nan -23.0631 -2.75695 0 0 22855.5 1428.47 0.00 0.01 0.00 -1 -1 0.00 0.00609754 0.00553999 +k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 vpr 20.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 21248 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt index 12efb65ec8c..a5132decd03 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 2.54 vpr 77.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78852 33 32 161 193 1 65 97 34 34 1156 -1 32x32 21.4 MiB 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00178122 0.0017245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 1.00 vpr 74.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76400 33 32 161 193 1 65 97 34 34 1156 -1 32x32 18.9 MiB 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000953076 0.000926056 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt index 87ace76c192..675c9ec8c27 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.20 vpr 64.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66472 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.9 MiB 0.00 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 4.3045e-05 2.9263e-05 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common 0.16 vpr 62.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64408 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 24 21 30 9 19 2 62.9 MiB 0.00 0.00 0.739166 0.646042 -3.51892 -0.646042 0.571 0.00 2.3236e-05 1.6158e-05 0.000950924 0.000910209 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000950924 0.000910209 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt index 8361bf1bfe6..63ec0c82585 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.75 vpr 978.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001760 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.46 364 858 131 680 47 978.3 MiB 0.06 0.00 6.37129 -69.6808 -6.37129 6.37129 1.81 0.000551403 0.000481676 0.0153225 0.013705 -1 -1 -1 -1 22 874 22 0 0 110609. 1256.92 1.54 0.247666 0.215864 11258 24748 -1 728 16 428 1746 95453 49745 6.73416 6.73416 -75.7525 -6.73416 0 0 134428. 1527.59 0.01 0.08 0.07 -1 -1 0.01 0.0332471 0.0304495 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 37.57 vpr 978.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001868 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.66 371 950 121 778 51 978.4 MiB 0.07 0.00 6.34606 -69.4373 -6.34606 6.34606 2.32 0.000744808 0.000651566 0.0166971 0.0148799 -1 -1 -1 -1 32 654 12 0 0 153433. 1743.56 0.90 0.149648 0.129506 11830 34246 -1 601 15 249 896 54680 24076 6.61838 6.61838 -74.0379 -6.61838 0 0 205860. 2339.32 0.01 0.07 0.09 -1 -1 0.01 0.0346715 0.0320467 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 34.09 vpr 978.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001652 10 10 168 178 1 68 30 11 8 88 io auto 955.4 MiB 0.44 376 582 74 468 40 978.2 MiB 0.07 0.00 6.26487 -68.7007 -6.26487 6.26487 2.74 0.000593656 0.000520243 0.0126605 0.0115382 -1 -1 -1 -1 28 858 45 0 0 134428. 1527.59 1.21 0.206409 0.180557 11590 29630 -1 614 14 305 1283 69506 33247 6.72367 6.72367 -73.5822 -6.72367 0 0 173354. 1969.93 0.01 0.08 0.06 -1 -1 0.01 0.0327372 0.0302784 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 41.01 vpr 978.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002252 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.60 352 582 88 454 40 978.8 MiB 0.05 0.00 6.37106 -69.2764 -6.37106 6.37106 3.17 0.000446168 0.000388088 0.0115458 0.0104844 -1 -1 -1 -1 22 778 22 0 0 110609. 1256.92 1.84 0.253098 0.220545 11258 24748 -1 690 15 386 1546 88347 46120 6.75259 6.75259 -75.6874 -6.75259 0 0 134428. 1527.59 0.01 0.08 0.06 -1 -1 0.01 0.0310233 0.0286671 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 22.92 vpr 980.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003552 10 10 168 178 1 65 30 11 8 88 io auto 953.5 MiB 0.34 461 363 812 65 683 64 980.0 MiB 0.06 0.00 6.74915 6.53925 -69.3815 -6.53925 6.53925 1.02 0.000306729 0.00027993 0.00872325 0.00811554 -1 -1 -1 -1 18 1016 35 0 0 88979.3 1011.13 0.42 0.0610226 0.0537175 11100 22242 -1 903 21 541 2228 132955 67625 6.88394 6.88394 -78.1788 -6.88394 0 0 114778. 1304.29 0.00 0.06 0.03 -1 -1 0.00 0.0200797 0.0183694 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 22.00 vpr 979.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002788 10 10 168 178 1 65 30 11 8 88 io auto 952.8 MiB 0.32 461 360 766 54 639 73 979.3 MiB 0.06 0.00 6.74915 6.50519 -69.5865 -6.50519 6.50519 0.99 0.000304647 0.000272539 0.00848216 0.00790543 -1 -1 -1 -1 22 737 19 0 0 110609. 1256.92 0.26 0.0516738 0.0459714 11258 24748 -1 741 17 354 1302 73546 39254 6.97435 6.97435 -75.9089 -6.97435 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.017292 0.0159531 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 22.43 vpr 979.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002984 10 10 168 178 1 65 30 11 8 88 io auto 953.0 MiB 0.32 461 374 858 76 722 60 979.5 MiB 0.05 0.00 6.74915 6.37842 -69.0199 -6.37842 6.37842 1.38 0.000304178 0.000276269 0.00897291 0.0083292 -1 -1 -1 -1 18 1028 44 0 0 88979.3 1011.13 0.39 0.0630047 0.0554817 11100 22242 -1 860 17 503 1822 111191 56265 7.04132 7.04132 -78.8721 -7.04132 0 0 114778. 1304.29 0.00 0.06 0.03 -1 -1 0.00 0.0175163 0.0161202 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 22.53 vpr 979.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002948 10 10 168 178 1 65 30 11 8 88 io auto 953.6 MiB 0.32 461 351 812 66 693 53 979.4 MiB 0.06 0.00 6.74915 6.37842 -69.076 -6.37842 6.37842 1.41 0.0006279 0.000600407 0.0105144 0.00982327 -1 -1 -1 -1 18 886 33 0 0 88979.3 1011.13 0.35 0.0596658 0.0528181 11100 22242 -1 779 16 420 1590 93739 47077 6.94344 6.94344 -77.4262 -6.94344 0 0 114778. 1304.29 0.00 0.05 0.03 -1 -1 0.00 0.0171118 0.0158021 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index 10a6cf257aa..3ed02e126a6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 36.65 vpr 978.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002024 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.33 0.000579422 0.00050489 0.0121495 0.01103 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.00 0.197686 0.174013 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.07 0.08 -1 -1 0.01 0.0316604 0.0292377 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 28.63 vpr 978.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001964 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.43 356 628 86 501 41 978.5 MiB 0.06 0.00 6.32784 -69.1369 -6.32784 6.32784 1.45 0.000300815 0.000260189 0.00775385 0.00704586 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 0.78 0.12183 0.106239 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.07 0.04 -1 -1 0.01 0.0278034 0.0259211 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 22.41 vpr 980.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003552 10 10 168 178 1 65 30 11 8 88 io auto 953.5 MiB 0.32 530 354 766 109 603 54 980.0 MiB 0.05 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 0.97 0.000305911 0.00027714 0.00819653 0.00761311 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.28 0.0523692 0.0463301 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0176516 0.0163051 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 22.21 vpr 980.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003548 10 10 168 178 1 65 30 11 8 88 io auto 953.5 MiB 0.33 530 359 766 97 619 50 980.0 MiB 0.05 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 0.99 0.000310412 0.000282703 0.00828685 0.00771023 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0520543 0.046207 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0186146 0.0171176 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt index bee9bf5e15f..6f6380c9b82 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 3.66 vpr 76.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78656 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.7 MiB 2.32 6246 12245 2336 8854 1055 76.8 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.22 0.00367856 0.00299064 0.169598 0.144286 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.174334 0.148491 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.50 vpr 76.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78400 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.21 6248 12409 2316 9051 1042 76.6 MiB 0.36 0.01 5.00015 -217.921 -5.00015 nan 0.26 0.00350625 0.00296092 0.150187 0.130251 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.154752 0.13448 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 4.86 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78576 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.5 MiB 1.80 6557 16051 3559 11939 553 76.7 MiB 0.46 0.01 5.39652 -231.823 -5.39652 nan 1.19 0.00333577 0.00278218 0.186781 0.161087 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.19137 0.165152 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.27 vpr 76.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78592 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.48 6642 53385 10847 39555 2983 76.8 MiB 0.94 0.01 5.30857 -236.309 -5.30857 nan 1.66 0.00199214 0.00171649 0.207463 0.177518 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.212761 0.182102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml ex5p.blif common_--place_effort_scaling_circuit 1.72 vpr 75.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77356 8 63 1072 1135 0 611 133 11 11 121 clb auto 35.8 MiB 1.13 7518 6082 8947 1533 6815 599 75.5 MiB 0.13 0.00 5.94011 5.07653 -213.869 -5.07653 nan 0.08 0.00137467 0.00121391 0.0556444 0.0510707 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0578783 0.0530616 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 1.74 vpr 75.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76912 8 63 1072 1135 0 611 133 11 11 121 clb auto 35.4 MiB 1.14 7518 6142 9355 1631 7067 657 75.1 MiB 0.14 0.00 5.94011 4.97625 -208.188 -4.97625 nan 0.08 0.00136238 0.00119962 0.0598913 0.054887 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0620728 0.0568398 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 3.05 vpr 74.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76600 8 63 1072 1135 0 611 133 27 27 729 -1 auto 34.7 MiB 1.17 17047 6704 22507 6724 13850 1933 74.8 MiB 0.27 0.00 9.03576 5.62812 -248.555 -5.62812 nan 0.62 0.0013434 0.00117795 0.109585 0.098544 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.11189 0.100604 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 3.16 vpr 75.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77312 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.8 MiB 1.12 17047 6681 64488 18508 41026 4954 75.5 MiB 0.50 0.01 9.03576 5.51074 -242.103 -5.51074 nan 0.60 0.00133767 0.00117811 0.100107 0.0904562 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.102225 0.0923579 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt index 344063856f9..395177b0d33 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.31 vpr 66.14 MiB -1 -1 0.81 26892 5 0.20 -1 -1 36924 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.1 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000410176 0.000357432 0.00947888 0.00721552 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.10 0.0626682 0.052856 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0168161 0.0151469 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.34 vpr 63.99 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65528 10 2 181 183 1 36 24 6 6 36 clb auto 24.5 MiB 0.02 196 151 500 122 353 25 64.0 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000235085 0.000214701 0.00476972 0.00440908 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.06 0.03334 0.0288534 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.0100241 0.00897853 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt index a4fadd34b2c..5843e7559a3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.35 vpr 62.50 MiB -1 -1 -1 -1 0 0.02 -1 -1 33168 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64000 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2148e-05 6.319e-06 7.9011e-05 5.1305e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00149016 0.00141935 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.45 vpr 62.59 MiB -1 -1 -1 -1 0 0.03 -1 -1 33140 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 0 3 0 0 3 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2883e-05 7.145e-06 8.5494e-05 5.1608e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00156787 0.00149125 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.37 vpr 62.62 MiB -1 -1 -1 -1 0 0.02 -1 -1 33248 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64128 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4288e-05 8.001e-06 8.7045e-05 5.7557e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.0015153 0.00144219 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.39 vpr 62.59 MiB -1 -1 -1 -1 0 0.02 -1 -1 33208 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64096 6 1 1 8 0 1 8 3 3 9 -1 auto 24.2 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2682e-05 6.827e-06 7.4747e-05 4.546e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00148015 0.0014067 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.37 vpr 62.59 MiB -1 -1 -1 -1 1 0.02 -1 -1 32904 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 2 1 3 4 0 3 4 3 3 9 -1 auto 24.2 MiB 0.00 9 9 5 0 4 62.6 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.5556e-05 1.071e-05 9.7598e-05 7.1292e-05 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.00 0.00159844 0.00147185 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.47 vpr 62.71 MiB -1 -1 -1 -1 2 0.05 -1 -1 34804 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 5 1 7 8 0 7 7 3 3 9 -1 auto 24.3 MiB 0.00 20 18 12 0 6 62.7 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4161e-05 1.7898e-05 0.000147057 0.000117193 -1 -1 -1 -1 -1 8 6 3900 3900 7855.82 872.868 0.00 0.00183362 0.0017084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.53 vpr 62.71 MiB -1 -1 -1 -1 2 0.06 -1 -1 35320 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 5 1 7 8 0 7 7 3 3 9 -1 auto 24.3 MiB 0.00 20 18 13 0 5 62.7 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4929e-05 1.9146e-05 0.000149053 0.000119002 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.00207292 0.001883 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.42 vpr 62.59 MiB -1 -1 -1 -1 1 0.03 -1 -1 33204 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 3 1 5 6 1 4 5 3 3 9 -1 auto 24.2 MiB 0.00 9 12 9 0 3 62.6 MiB 0.00 0.00 0.274843 -0.536407 -0.274843 0.274843 0.00 2.0225e-05 1.4435e-05 0.000138329 0.000106209 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.00194055 0.00179435 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.55 vpr 62.71 MiB -1 -1 -1 -1 1 0.05 -1 -1 35156 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower 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min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.36 vpr 60.43 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 0 0 success v8.0.0-12648-g259ceba57-dirty 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release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62260 5 1 7 8 0 7 7 3 3 9 -1 auto 22.5 MiB 0.00 20 20 18 13 0 5 60.8 MiB 0.00 0.00 0.70303 0.70303 -0.70303 -0.70303 nan 0.00 1.3014e-05 9.636e-06 9.8067e-05 7.8745e-05 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.00117211 0.00105469 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.32 vpr 60.80 MiB -1 -1 -1 -1 1 0.02 -1 -1 29988 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62260 3 1 5 6 1 4 5 3 3 9 -1 auto 22.5 MiB 0.00 9 9 12 9 0 3 60.8 MiB 0.00 0.00 0.274843 0.274843 -0.536407 -0.274843 0.274843 0.00 1.0936e-05 7.525e-06 8.3706e-05 6.3702e-05 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.0011052 0.00100775 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.41 vpr 60.80 MiB -1 -1 -1 -1 1 0.03 -1 -1 31816 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62264 4 1 4 6 0 4 6 3 3 9 -1 auto 22.2 MiB 0.00 12 12 15 11 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.443777 -0.443777 nan 0.00 1.0318e-05 6.84e-06 7.4714e-05 5.4959e-05 -1 -1 -1 -1 -1 7 16 3900 3900 7855.82 872.868 0.00 0.00114292 0.00101594 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.40 vpr 60.80 MiB -1 -1 -1 -1 1 0.03 -1 -1 31872 -1 -1 1 4 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62264 4 4 8 12 0 8 9 3 3 9 -1 auto 22.5 MiB 0.00 25 25 27 23 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -1.77511 -0.443777 nan 0.00 1.7936e-05 1.41e-05 0.000134733 0.000114066 -1 -1 -1 -1 -1 30 13 3900 3900 7855.82 872.868 0.00 0.00140331 0.00125307 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.42 vpr 60.60 MiB -1 -1 -1 -1 3 0.04 -1 -1 32344 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62056 6 6 28 34 0 28 15 5 5 25 clb auto 21.8 MiB 0.00 113 107 51 16 35 0 60.6 MiB 0.00 0.00 1.19848 1.19848 -5.43061 -1.19848 nan 0.00 4.9605e-05 4.359e-05 0.000391617 0.00036093 -1 -1 -1 -1 -1 190 16 23400 11700 33739.5 1349.58 0.01 0.00302204 0.00268104 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.43 vpr 60.45 MiB -1 -1 -1 -1 4 0.04 -1 -1 32088 -1 -1 5 7 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61904 7 8 39 47 0 39 20 5 5 25 clb auto 22.1 MiB 0.01 182 166 236 59 163 14 60.5 MiB 0.00 0.00 1.48602 1.46514 -7.47508 -1.46514 nan 0.00 6.7634e-05 5.9467e-05 0.000923947 0.000839342 -1 -1 -1 -1 -1 326 19 23400 19500 33739.5 1349.58 0.02 0.0046745 0.00410086 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.47 vpr 60.96 MiB -1 -1 -1 -1 8 0.05 -1 -1 32092 -1 -1 6 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62428 8 8 51 59 0 51 22 5 5 25 clb auto 22.5 MiB 0.01 241 211 352 90 254 8 61.0 MiB 0.00 0.00 2.56944 2.55689 -12.2592 -2.55689 nan 0.00 8.5471e-05 7.753e-05 0.00148029 0.00135617 -1 -1 -1 -1 -1 432 21 23400 23400 33739.5 1349.58 0.02 0.00641372 0.00564603 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.54 vpr 61.32 MiB -1 -1 -1 -1 7 0.06 -1 -1 32828 -1 -1 11 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62792 10 10 95 105 0 95 31 6 6 36 clb auto 22.2 MiB 0.01 521 440 511 77 404 30 61.3 MiB 0.01 0.00 2.69967 2.57044 -18.1695 -2.57044 nan 0.00 0.000150117 0.00013686 0.0022957 0.00211495 -1 -1 -1 -1 -1 938 24 165600 42900 61410.5 1705.85 0.05 0.010575 0.00932341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.56 vpr 61.28 MiB -1 -1 -1 -1 8 0.07 -1 -1 32924 -1 -1 11 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62752 11 11 94 105 0 94 33 6 6 36 clb auto 22.2 MiB 0.01 523 447 709 77 581 51 61.3 MiB 0.01 0.00 2.83651 2.78731 -20.9698 -2.78731 nan 0.00 0.000145948 0.000133465 0.00280111 0.00257676 -1 -1 -1 -1 -1 978 22 165600 42900 61410.5 1705.85 0.05 0.0108181 0.0095662 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.40 vpr 60.80 MiB -1 -1 -1 -1 1 0.03 -1 -1 31076 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62264 3 2 5 7 0 5 6 3 3 9 -1 auto 22.5 MiB 0.00 15 15 15 11 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.887553 -0.443777 nan 0.00 1.2426e-05 8.986e-06 0.000101661 8.0396e-05 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.00124405 0.00110619 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.40 vpr 60.58 MiB -1 -1 -1 -1 2 0.03 -1 -1 31864 -1 -1 1 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62036 5 3 9 12 0 9 9 3 3 9 -1 auto 22.1 MiB 0.00 26 26 27 24 0 3 60.6 MiB 0.00 0.00 0.70303 0.70303 -1.84984 -0.70303 nan 0.00 1.6846e-05 1.3184e-05 0.000128485 0.000107138 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.00145588 0.00128914 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.38 vpr 61.18 MiB -1 -1 -1 -1 3 0.03 -1 -1 31860 -1 -1 1 7 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62644 7 4 13 17 0 13 12 3 3 9 -1 auto 22.6 MiB 0.00 37 37 38 34 0 4 61.2 MiB 0.00 0.00 0.962283 0.962283 -3.07137 -0.962283 nan 0.00 2.2173e-05 1.8007e-05 0.000170305 0.000147797 -1 -1 -1 -1 -1 39 18 3900 3900 7855.82 872.868 0.00 0.00176748 0.00156548 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.41 vpr 60.81 MiB -1 -1 -1 -1 4 0.04 -1 -1 31864 -1 -1 1 9 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62268 9 5 17 22 0 17 15 3 3 9 -1 auto 22.2 MiB 0.00 48 48 51 43 0 8 60.8 MiB 0.00 0.00 1.22154 1.22154 -4.55216 -1.22154 nan 0.00 2.7739e-05 2.3216e-05 0.000212345 0.000188425 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.00 0.0020451 0.00180274 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.40 vpr 60.60 MiB -1 -1 -1 -1 4 0.04 -1 -1 31480 -1 -1 2 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62052 11 6 24 30 0 24 19 4 4 16 clb auto 21.9 MiB 0.00 96 81 219 61 139 19 60.6 MiB 0.00 0.00 1.37337 1.3375 -6.59285 -1.3375 nan 0.00 3.6283e-05 3.0702e-05 0.000516197 0.000448261 -1 -1 -1 -1 -1 131 14 7800 7800 17482.0 1092.63 0.01 0.00253984 0.00224901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index def1a137d22..5a0e83cd6e5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.05 vpr 68.39 MiB -1 -1 0.40 21908 3 0.11 -1 -1 37048 -1 54888 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70028 99 130 344 474 1 227 298 12 12 144 clb auto 29.0 MiB 0.23 673 63978 19550 30341 14087 68.4 MiB 0.26 0.00 1.86472 -118.834 -1.86472 1.86472 0.28 0.000886976 0.000801272 0.0813306 0.0745016 -1 -1 -1 -1 38 1393 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.68 0.238994 0.21577 12522 62564 -1 1106 10 397 647 21454 6807 1.90702 1.90702 -131.595 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.03 0.05 0.11 -1 -1 0.03 0.0347348 0.0326652 0.01152 0.2117 0.0667 0.7216 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.51 vpr 71.63 MiB -1 -1 0.57 27156 15 0.44 -1 -1 38000 -1 56764 39 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73348 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 32.3 MiB 0.47 5553 86322 27524 51152 7646 71.6 MiB 0.85 0.01 20.9417 -1607.93 -20.9417 20.9417 0.48 0.003704 0.00340296 0.38455 0.354826 -1 -1 -1 -1 50 10993 26 1.21132e+07 4.08187e+06 780512. 3048.87 3.85 1.2672 1.17071 25484 153448 -1 9617 17 3054 6060 825747 253645 22.1678 22.1678 -1734.75 -22.1678 0 0 1.00276e+06 3917.05 0.06 0.43 0.25 -1 -1 0.06 0.181388 0.170418 0.007894 0.3513 0.0164 0.6323 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.12 vpr 66.85 MiB -1 -1 0.23 18444 3 0.06 -1 -1 32728 -1 52608 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68452 99 130 344 474 1 228 298 12 12 144 clb auto 27.4 MiB 0.10 1675 704 66963 20370 32791 13802 66.8 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000588264 0.00055103 0.0412906 0.0386681 -1 -1 -1 -1 40 1447 16 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.15889 0.145741 12666 64609 -1 1220 8 417 630 29292 10027 2.02932 2.02932 -139.109 -2.02932 -0.436676 -0.298787 419432. 2912.72 0.01 0.02 0.04 -1 -1 0.01 0.0158392 0.0149265 0.01097 0.2173 0.06774 0.7149 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 6.02 vpr 70.39 MiB -1 -1 0.31 23676 15 0.29 -1 -1 33804 -1 54344 39 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72084 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 30.5 MiB 0.18 9745 5422 92394 29404 54877 8113 70.4 MiB 0.35 0.00 23.0626 21.1445 -1627.16 -21.1445 21.1445 0.18 0.00152927 0.00141434 0.152545 0.142035 -1 -1 -1 -1 52 12275 40 1.21132e+07 4.08187e+06 805949. 3148.24 2.13 0.550493 0.509323 25992 162577 -1 9489 19 3386 7023 823162 268347 21.9567 21.9567 -1721.84 -21.9567 0 0 1.06067e+06 4143.25 0.03 0.18 0.10 -1 -1 0.03 0.0804895 0.0759977 0.008009 0.3554 0.01727 0.6273 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index 82620e51799..9639f26e4f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.71 vpr 65.87 MiB -1 -1 0.78 26896 5 0.18 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67448 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00039706 0.000346093 0.00713489 0.00637234 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.03 -1 -1 65.9 MiB 0.02 0.0245431 0.0219785 65.9 MiB -1 0.00 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.90 vpr 68.91 MiB -1 -1 0.73 26796 4 0.18 -1 -1 36100 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70560 11 2 303 283 2 78 28 7 7 49 clb auto 29.2 MiB 0.18 285 784 175 539 70 68.9 MiB 0.03 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000657098 0.000563918 0.0210266 0.0187872 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 68.9 MiB 0.03 0.0456598 0.0418503 68.9 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.15 vpr 64.27 MiB -1 -1 0.46 23432 5 0.10 -1 -1 32588 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 25.1 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000230059 0.000208481 0.00401393 0.00371679 -1 -1 -1 -1 136 4.12121 61 1.84848 149 320 10235 1961 646728 646728 138825. 3856.24 17 3164 19284 -1 2.10277 2.10277 -91.6521 -2.10277 0 0 0.01 -1 -1 64.3 MiB 0.01 0.0145441 0.0130986 64.3 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.26 vpr 67.26 MiB -1 -1 0.40 23072 4 0.10 -1 -1 32604 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68872 11 2 303 283 2 85 28 7 7 49 clb auto 27.9 MiB 0.11 462 289 1204 263 848 93 67.3 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.000392594 0.000350448 0.0146209 0.0131383 -1 -1 -1 -1 314 3.97468 124 1.56962 130 211 4049 1168 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.02047 1.86775 -152.224 -2.02047 0 0 0.02 -1 -1 67.3 MiB 0.01 0.0286825 0.0263238 67.3 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index b3939ae8bad..5f4f5529d11 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 40.08 vpr 84.36 MiB -1 -1 7.36 54308 5 2.17 -1 -1 42700 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86380 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 2.10 10543 233626 82676 126206 24744 84.4 MiB 2.58 0.04 4.85425 -2733.64 -4.85425 4.85425 0.83 0.0094896 0.008538 0.955143 0.814553 -1 -1 -1 -1 76 20844 34 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 19.63 4.86995 4.26704 52074 423490 -1 18742 17 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.70 0.57 -1 -1 0.11 0.429237 0.387696 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 14.68 vpr 84.02 MiB -1 -1 3.34 52052 5 1.33 -1 -1 38940 -1 -1 152 193 5 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86040 193 205 2718 2652 1 1315 555 20 20 400 memory auto 43.9 MiB 0.95 22187 10660 223995 81694 118286 24015 84.0 MiB 1.00 0.01 7.82756 5.10197 -2914.56 -5.10197 5.10197 0.30 0.00326192 0.00293721 0.360015 0.322066 -1 -1 -1 -1 76 20582 44 2.07112e+07 1.09319e+07 2.02110e+06 5052.76 5.14 1.27624 1.14447 52074 423490 -1 19292 17 5251 14325 1187541 264668 5.21056 5.21056 -3121.27 -5.21056 -9.98113 -0.359474 2.51807e+06 6295.18 0.07 0.32 0.24 -1 -1 0.07 0.190256 0.17845 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt index b2a77a6f0e1..ecbe1740334 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.71 vpr 71.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73312 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.45 4992 14048 2664 10357 1027 71.6 MiB 0.29 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00333844 0.00278407 0.128199 0.109732 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.21 -1 -1 71.6 MiB 0.30 0.276888 0.244984 71.6 MiB -1 0.05 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.81 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.47 4992 14048 2664 10357 1027 71.5 MiB 0.31 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00291779 0.00252096 0.133598 0.1169 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.20 -1 -1 71.5 MiB 0.31 0.289515 0.258703 71.5 MiB -1 0.06 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 0.93 vpr 69.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71608 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7035 5048 13708 2494 10216 998 69.9 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.0012128 0.0010607 0.0506511 0.0454061 -1 -1 -1 -1 6826 15.1353 1836 4.07095 3768 15421 585680 92261 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17836 nan -185.935 -4.17836 0 0 0.08 -1 -1 69.9 MiB 0.17 0.129356 0.117175 69.9 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 0.89 vpr 69.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70996 8 63 748 811 0 451 161 14 14 196 clb auto 30.3 MiB 0.22 7035 5048 13708 2494 10216 998 69.3 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.00121456 0.00105201 0.0492265 0.0440361 -1 -1 -1 -1 6906 15.3126 1853 4.10865 3897 16323 609528 97595 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17947 nan -185.454 -4.17947 0 0 0.08 -1 -1 69.3 MiB 0.16 0.125412 0.113776 69.3 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index f0bed076f05..4f76e3d108b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.89 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73344 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.50 4993 17086 3593 12286 1207 71.6 MiB 0.32 0.01 3.65588 -160.421 -3.65588 nan 0.04 0.00302942 0.00252731 0.141328 0.121812 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.15 -1 -1 71.6 MiB 0.43 0.306494 0.271472 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.75 vpr 71.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73176 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.38 4933 15350 2970 11325 1055 71.5 MiB 0.31 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00317678 0.00277359 0.137596 0.118868 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.5 MiB 0.37 0.319312 0.282053 71.5 MiB -1 0.04 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.41 vpr 71.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73128 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.28 0.01 3.77945 -168.167 -3.77945 nan 0.06 0.00517556 0.0043803 0.123856 0.107999 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.14 -1 -1 71.4 MiB 0.56 0.3503 0.312891 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.58 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.7 MiB 0.45 5048 17520 3917 12196 1407 71.5 MiB 0.35 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00283082 0.00243406 0.152931 0.13159 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.10 -1 -1 71.5 MiB 0.60 0.372321 0.328664 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 0.98 vpr 69.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71212 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.23 7019 5149 19389 4557 13188 1644 69.5 MiB 0.16 0.00 5.27085 3.74489 -168.03 -3.74489 nan 0.02 0.00125283 0.0010941 0.0674999 0.0604792 -1 -1 -1 -1 7151 15.8559 1918 4.25277 4270 17535 1282134 224677 9.20055e+06 4.85046e+06 701736. 3580.29 23 16332 105598 -1 4.37015 nan -196.64 -4.37015 0 0 0.06 -1 -1 69.5 MiB 0.22 0.147101 0.13314 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 0.92 vpr 69.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71024 8 63 748 811 0 451 161 14 14 196 clb auto 29.9 MiB 0.24 7019 5029 15019 2779 11014 1226 69.4 MiB 0.13 0.00 5.64572 4.2713 -188.25 -4.2713 nan 0.00 0.00120263 0.00103977 0.0546017 0.0489804 -1 -1 -1 -1 7035 15.5987 1894 4.19956 3783 16134 598321 102284 9.20055e+06 4.85046e+06 701736. 3580.29 20 16332 105598 -1 4.48059 nan -193.333 -4.48059 0 0 0.06 -1 -1 69.4 MiB 0.16 0.131335 0.119172 69.4 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 1.67 vpr 69.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70840 8 63 748 811 0 451 161 14 14 196 clb auto 30.1 MiB 0.23 7019 5066 19826 4740 13454 1632 69.2 MiB 0.16 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00120109 0.00105045 0.0672362 0.0599274 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 69.2 MiB 0.22 0.144275 0.130119 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.74 vpr 69.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71212 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.24 7019 5066 19826 4740 13454 1632 69.5 MiB 0.17 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00118757 0.00104417 0.0682317 0.0610542 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 69.5 MiB 0.22 0.149143 0.134994 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt index 2e384423539..96895dbdd9f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.81 vpr 71.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72996 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.46 5066 14916 2828 10927 1161 71.3 MiB 0.27 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00329282 0.00274638 0.115858 0.0987687 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.40 0.297064 0.262289 71.3 MiB -1 0.03 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.90 vpr 71.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72932 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.47 5066 14916 2828 10927 1161 71.2 MiB 0.34 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00295504 0.00249967 0.137157 0.115922 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.16 -1 -1 71.2 MiB 0.41 0.334676 0.294068 71.2 MiB -1 0.04 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 0.93 vpr 69.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71216 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.23 7035 5098 13271 2309 10001 961 69.5 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00119761 0.00104527 0.0488071 0.0438389 -1 -1 -1 -1 7155 15.8647 1916 4.24834 4312 18456 674497 110334 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.5 MiB 0.17 0.127664 0.116164 69.5 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 0.92 vpr 69.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71600 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.23 7035 5098 13271 2309 10001 961 69.9 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00119935 0.00104077 0.0477462 0.0428434 -1 -1 -1 -1 7141 15.8337 1913 4.24168 4366 18775 685171 111801 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.9 MiB 0.18 0.127342 0.115562 69.9 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt index dda3cef9fb9..30111b74667 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.94 vpr 67.28 MiB -1 -1 0.14 21160 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68892 6 1 16 17 2 10 9 17 17 289 -1 auto 28.8 MiB 0.03 30 162 45 109 8 67.3 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.60 4.7388e-05 3.614e-05 0.00109694 0.000865862 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.37 0.00363015 0.00323679 24098 82050 -1 103 2 14 14 8045 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.04 0.16 0.10 -1 -1 0.04 0.00205247 0.00194107 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.71 vpr 67.09 MiB -1 -1 0.11 20776 1 0.02 -1 -1 33508 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.29 2.6273e-05 2.0281e-05 0.000147698 0.000116195 -1 -1 -1 -1 20 62 1 6.63067e+06 53894 227243. 1344.63 0.21 0.00195838 0.00183532 13251 44387 -1 55 1 4 4 2060 1116 1.77078 1.77078 -1.77078 -1.77078 -0.365681 -0.365681 294987. 1745.49 0.02 0.09 0.06 -1 -1 0.02 0.00158307 0.00153637 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.80 vpr 67.12 MiB -1 -1 0.13 21160 1 0.05 -1 -1 35572 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68728 6 1 16 17 2 10 9 17 17 289 -1 auto 28.7 MiB 0.01 30 162 45 109 8 67.1 MiB 0.00 0.00 1.43377 -4.13192 -1.43377 0.805 0.60 4.8373e-05 3.7154e-05 0.00108209 0.000859607 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.36 0.00311589 0.00272737 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.04 0.17 0.12 -1 -1 0.04 0.00220953 0.00209751 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.66 vpr 67.09 MiB -1 -1 0.12 20904 1 0.02 -1 -1 33532 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.23 2.2312e-05 1.624e-05 0.000140559 0.000108632 -1 -1 -1 -1 20 58 1 6.63067e+06 53894 235789. 1395.20 0.22 0.00172037 0.00159801 13251 46155 -1 59 1 4 4 2248 1144 1.92085 1.92085 -1.92085 -1.92085 -0.365681 -0.365681 303533. 1796.05 0.02 0.10 0.07 -1 -1 0.02 0.00161749 0.00156481 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.79 vpr 67.18 MiB -1 -1 0.14 20780 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68788 6 1 16 17 2 10 9 17 17 289 -1 auto 28.9 MiB 0.02 30 162 45 109 8 67.2 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.52 4.3023e-05 3.3348e-05 0.0010817 0.000870707 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.27 0.00353152 0.00316566 24098 82150 -1 581 2 13 13 6290 3262 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.04 0.17 0.11 -1 -1 0.04 0.00234323 0.00223031 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.63 vpr 67.17 MiB -1 -1 0.08 21164 1 0.02 -1 -1 33664 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68780 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.2 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.27 1.6733e-05 1.1353e-05 0.00024751 0.000102039 -1 -1 -1 -1 20 193 1 6.63067e+06 53894 225153. 1332.26 0.23 0.00204227 0.00181801 13251 44463 -1 186 1 4 4 914 327 2.39001 2.39001 -2.39001 -2.39001 -0.984912 -0.984912 292904. 1733.16 0.02 0.07 0.05 -1 -1 0.02 0.00162703 0.00157897 0 4 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.46 vpr 65.00 MiB -1 -1 0.08 17308 1 0.04 -1 -1 31584 -1 -1 2 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66564 6 1 16 17 2 10 9 17 17 289 -1 auto 26.4 MiB 0.01 128 30 162 45 109 8 65.0 MiB 0.00 0.00 2.32203 1.4327 -4.13089 -1.4327 0.805 0.21 2.6931e-05 1.6557e-05 0.000584509 0.000451852 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.15 0.00187029 0.00164769 24098 82050 -1 103 2 14 14 8045 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.02 0.07 0.04 -1 -1 0.02 0.00128046 0.00121058 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 0.95 vpr 64.76 MiB -1 -1 0.07 17312 1 0.02 -1 -1 29984 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 3 1 5 6 1 4 5 13 13 169 -1 auto 26.5 MiB 0.00 38 25 12 5 6 1 64.8 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.11 1.176e-05 7.373e-06 9.5504e-05 7.1942e-05 -1 -1 -1 -1 20 46 1 6.63067e+06 53894 227243. 1344.63 0.08 0.00102566 0.000948714 13251 44387 -1 49 1 4 4 2037 1117 1.60624 1.60624 -1.60624 -1.60624 -0.386566 -0.386566 294987. 1745.49 0.01 0.04 0.02 -1 -1 0.01 0.000916629 0.000875809 0 4 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.43 vpr 65.00 MiB -1 -1 0.08 17312 1 0.03 -1 -1 31592 -1 -1 2 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 6 1 16 17 2 10 9 17 17 289 -1 auto 26.4 MiB 0.01 128 30 162 45 109 8 65.0 MiB 0.00 0.00 2.32504 1.43377 -4.13192 -1.43377 0.805 0.21 2.2762e-05 1.6724e-05 0.000573962 0.000444673 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.15 0.00187733 0.00165636 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.02 0.07 0.04 -1 -1 0.02 0.0012306 0.00116318 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 0.98 vpr 64.72 MiB -1 -1 0.06 17312 1 0.02 -1 -1 29240 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66272 3 1 5 6 1 4 5 13 13 169 -1 auto 25.9 MiB 0.00 38 25 12 5 6 1 64.7 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.11 2.7322e-05 6.969e-06 0.000108399 6.8796e-05 -1 -1 -1 -1 20 50 1 6.63067e+06 53894 235789. 1395.20 0.08 0.00104947 0.000960311 13251 46155 -1 48 1 4 4 2008 1087 1.59583 1.59583 -1.59583 -1.59583 -0.386566 -0.386566 303533. 1796.05 0.01 0.04 0.02 -1 -1 0.01 0.000933815 0.000894029 0 4 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.43 vpr 65.00 MiB -1 -1 0.08 17308 1 0.03 -1 -1 31608 -1 -1 2 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 6 1 16 17 2 10 9 17 17 289 -1 auto 26.8 MiB 0.01 128 30 162 45 109 8 65.0 MiB 0.00 0.00 2.32203 1.4327 -4.13089 -1.4327 0.805 0.21 2.2521e-05 1.65e-05 0.000581369 0.000454157 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.14 0.00184821 0.00163011 24098 82150 -1 581 2 13 13 6290 3262 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.02 0.07 0.04 -1 -1 0.02 0.00119849 0.00113118 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.00 vpr 65.00 MiB -1 -1 0.07 17308 1 0.02 -1 -1 29972 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 3 1 5 6 1 4 5 13 13 169 -1 auto 26.8 MiB 0.00 38 25 12 5 6 1 65.0 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.12 1.2422e-05 7.808e-06 9.6046e-05 7.2011e-05 -1 -1 -1 -1 20 177 1 6.63067e+06 53894 225153. 1332.26 0.08 0.00102812 0.000944896 13251 44463 -1 180 1 4 4 885 322 2.22548 2.22548 -2.22548 -2.22548 -1.0058 -1.0058 292904. 1733.16 0.01 0.04 0.02 -1 -1 0.01 0.000967633 0.00090832 0 4 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index 5c6245f2fa3..3a7061254a7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 0.74 vpr 59.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61260 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 21.1 MiB 0.24 70 15 4 10 1 59.8 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000194851 0.000170942 0.00110293 0.00100939 -1 -1 -1 -1 27 263 12 133321 74067 -1 -1 0.15 0.0230545 0.019405 1284 5874 -1 260 8 79 79 17257 10064 1.64234 1.64234 -16.7917 -1.64234 0 0 -1 -1 0.00 0.01 0.01 -1 -1 0.00 0.0047943 0.00439499 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +slicem.xml carry_chain.blif common 0.56 vpr 58.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59816 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 19.2 MiB 0.14 70 70 15 4 10 1 58.4 MiB 0.00 0.00 0.552322 0.523836 -5.19346 -0.523836 0.523836 0.00 6.9663e-05 6.2493e-05 0.000564407 0.000524739 -1 -1 -1 -1 27 337 26 133321 74067 -1 -1 0.09 0.0140806 0.0116706 1284 5874 -1 249 10 84 84 16544 9291 1.47622 1.47622 -16.7882 -1.47622 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0056494 0.00499524 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index bcdd78ccdb6..05b6fd95464 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.33 vpr 58.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60252 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.2 MiB 0.00 31 59 13 43 3 58.8 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.7056e-05 2.9732e-05 0.000307367 0.000251846 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00402393 0.00331535 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00212051 0.00200433 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml ndff.blif common 0.27 vpr 57.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58548 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 36 31 59 13 43 3 57.2 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8658e-05 1.4445e-05 0.000175579 0.000141999 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00231473 0.00196653 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00104772 0.000979247 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index 07d413f9696..95dfec9c5ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.89 vpr 69.17 MiB -1 -1 0.74 26544 4 0.19 -1 -1 36136 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.19 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.000817884 0.000697618 0.00655739 0.00606976 -1 -1 -1 -1 398 5.30667 131 1.74667 104 164 3400 907 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.01 0.0209255 0.0197757 69.2 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.24 vpr 66.91 MiB -1 -1 0.41 23076 4 0.10 -1 -1 32604 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68520 11 2 303 283 2 82 28 7 7 49 clb auto 27.1 MiB 0.11 424 278 994 204 585 205 66.9 MiB 0.02 0.00 4.1851 4.05951 0 0 3.91314 0.00 0.000352617 0.000321562 0.011537 0.010684 -1 -1 -1 -1 320 4.21053 119 1.56579 117 192 3627 1005 1.07788e+06 808410 219490. 4479.39 5 5100 32136 -1 4.18749 3.93845 0 0 -197.86 -1.707 0.02 -1 -1 66.9 MiB 0.01 0.0238196 0.022287 66.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index 4625b2401ff..3d8cc9cc7a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.45 vpr 65.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 21 4 65.2 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.03 3.7635e-05 2.9892e-05 0.000225074 0.00018278 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.02 0.00833787 0.0081741 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00218203 0.00181006 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.44 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66812 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.2 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1854e-05 2.4534e-05 0.000226572 0.000187065 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.03 0.00709054 0.0068829 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00198245 0.00170015 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.39 vpr 65.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66832 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 22 3 65.3 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.5201e-05 2.6601e-05 0.00022707 0.000179701 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00304545 0.00286146 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00175316 0.00162725 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.41 vpr 65.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.4 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.0901e-05 3.1228e-05 0.000248936 0.000196898 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00216389 0.0019624 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00684314 0.00669963 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.43 vpr 65.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66876 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.3 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 3.9504e-05 2.6238e-05 0.000255838 0.000203867 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00256208 0.00226692 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00410374 0.00385942 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.30 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66632 5 3 11 14 2 9 10 4 4 16 clb auto 26.7 MiB 0.00 21 30 5 23 2 65.1 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 2.4424e-05 1.8925e-05 0.00016567 0.000135551 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00149783 0.00138533 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00190216 0.00178073 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.32 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 5 21 4 63.5 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 1.912e-05 1.4716e-05 0.000138868 0.000113336 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.00122882 0.00112591 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00108963 0.00101167 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.32 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 5 3 11 14 2 9 10 4 4 16 clb auto 25.2 MiB 0.00 22 22 30 6 14 10 63.5 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.00 1.8239e-05 1.4253e-05 0.000129443 0.000106202 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00121369 0.001109 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00103908 0.000972534 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.33 vpr 63.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64980 5 3 11 14 2 9 10 4 4 16 clb auto 24.8 MiB 0.00 22 21 30 5 22 3 63.5 MiB 0.00 0.00 0.646297 0.646297 -2.19033 -0.646297 0.571 0.00 2.1582e-05 1.6466e-05 0.00015818 0.000130127 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.00 0.00130867 0.00118702 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00114602 0.00105988 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.32 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 7 16 7 63.5 MiB 0.00 0.00 1.64604 1.6463 -5.31965 -1.6463 0.571 0.00 4.4605e-05 3.8769e-05 0.000176185 0.000144336 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.0012431 0.00112184 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00115182 0.00106621 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.33 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65024 5 3 11 14 2 9 10 4 4 16 clb auto 25.4 MiB 0.00 22 22 30 8 15 7 63.5 MiB 0.00 0.00 1.44967 1.44967 -2.9103 -1.44967 0.571 0.00 2.6664e-05 1.7569e-05 0.00016333 0.000129614 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00152422 0.00133207 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00118439 0.00108721 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.32 vpr 63.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65128 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 5 23 2 63.6 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.1111e-05 1.6553e-05 0.000146148 0.000120267 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.0012502 0.00114398 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00116517 0.00107026 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index 3373ba9d87f..6e62fc65a75 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.57 vpr 66.20 MiB -1 -1 0.12 21572 1 0.03 -1 -1 33720 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.67 85 398 116 276 6 66.2 MiB 0.01 0.00 2.48207 -27.4234 -2.48207 2.48207 0.03 0.000168115 0.000148552 0.00382732 0.00348451 -1 -1 -1 -1 26 186 18 151211 75605.7 37105.9 1484.24 0.07 0.0274796 0.0239744 1908 5841 -1 144 14 104 128 3783 2136 2.42625 2.42625 -32.7566 -2.42625 0 0 45067.1 1802.68 0.00 0.01 0.01 -1 -1 0.00 0.00858616 0.00782966 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.85 vpr 66.12 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33420 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67704 11 10 108 97 1 49 23 4 4 16 clb auto 26.9 MiB 2.02 135 87 35 39 13 66.1 MiB 0.00 0.00 3.45122 -42.4992 -3.45122 3.45122 0.01 0.000185565 0.000169189 0.00161119 0.00153779 -1 -1 -1 -1 34 225 26 50403.8 50403.8 21558.4 1347.40 0.10 0.0502132 0.0405962 1020 3049 -1 158 14 151 165 4063 2532 3.88646 3.88646 -47.5118 -3.88646 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00719488 0.00664889 15 27 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.48 vpr 66.58 MiB -1 -1 0.14 21316 1 0.03 -1 -1 33560 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68180 13 12 149 129 1 68 32 6 6 36 clb auto 27.2 MiB 5.18 196 882 281 588 13 66.6 MiB 0.01 0.00 3.49758 -52.6333 -3.49758 3.49758 0.04 0.000188427 0.000167514 0.00680212 0.00627325 -1 -1 -1 -1 40 395 29 403230 176413 88484.8 2457.91 0.24 0.0901214 0.0785509 3734 16003 -1 328 14 283 356 13658 6213 3.44595 3.44595 -58.2463 -3.44595 0 0 110337. 3064.92 0.00 0.04 0.03 -1 -1 0.00 0.0323499 0.0245182 25 38 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.00 vpr 66.86 MiB -1 -1 0.14 21572 1 0.03 -1 -1 33512 -1 -1 7 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 15 14 196 165 1 92 36 6 6 36 clb auto 27.2 MiB 2.65 304 744 159 567 18 66.9 MiB 0.02 0.00 3.62628 -64.4645 -3.62628 3.62628 0.05 0.000406252 0.000363743 0.00800716 0.00737412 -1 -1 -1 -1 52 651 42 403230 176413 110337. 3064.92 0.29 0.109536 0.0955888 4014 20275 -1 496 16 373 551 19804 8423 3.5903 3.5903 -70.6456 -3.5903 0 0 143382. 3982.83 0.00 0.03 0.03 -1 -1 0.00 0.0200523 0.0184119 37 51 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.34 vpr 67.21 MiB -1 -1 0.16 21320 1 0.03 -1 -1 33716 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68824 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 6.96 396 2495 611 1868 16 67.2 MiB 0.04 0.00 3.8369 -73.5721 -3.8369 3.8369 0.03 0.000487285 0.000432143 0.0227482 0.0204679 -1 -1 -1 -1 46 672 23 151211 126010 57775.2 2311.01 0.27 0.134818 0.118379 2220 9391 -1 565 21 712 1067 32893 15487 5.93712 5.93712 -106.904 -5.93712 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0286301 0.0260985 44 66 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.49 vpr 67.34 MiB -1 -1 0.15 21572 1 0.03 -1 -1 33768 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68960 19 18 308 249 1 133 43 5 5 25 clb auto 27.8 MiB 6.09 448 2143 525 1607 11 67.3 MiB 0.04 0.00 4.70186 -94.0493 -4.70186 4.70186 0.03 0.000586405 0.000522924 0.0211391 0.0191781 -1 -1 -1 -1 46 706 50 151211 151211 57775.2 2311.01 0.36 0.18155 0.16007 2220 9391 -1 599 18 697 1112 32896 15750 4.84188 4.84188 -104.71 -4.84188 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0301574 0.0276463 53 83 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.10 vpr 64.34 MiB -1 -1 0.07 17596 1 0.02 -1 -1 30128 -1 -1 3 9 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 9 8 75 70 1 34 20 5 5 25 clb auto 25.2 MiB 0.37 116 87 425 142 281 2 64.3 MiB 0.01 0.00 2.64007 2.48207 -26.067 -2.48207 2.48207 0.01 9.3228e-05 8.39e-05 0.0022793 0.00210862 -1 -1 -1 -1 26 268 23 151211 75605.7 37105.9 1484.24 0.04 0.015438 0.0132379 1908 5841 -1 135 7 69 74 2147 1228 2.87707 2.87707 -32.0609 -2.87707 0 0 45067.1 1802.68 0.00 0.01 0.00 -1 -1 0.00 0.00462719 0.00432137 13 18 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.34 vpr 64.48 MiB -1 -1 0.08 17592 1 0.02 -1 -1 30088 -1 -1 2 11 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 11 10 108 97 1 48 23 4 4 16 clb auto 25.6 MiB 1.57 142 127 279 85 156 38 64.5 MiB 0.00 0.00 3.45122 3.45122 -42.3331 -3.45122 3.45122 0.01 0.000120597 0.000109581 0.00222065 0.00210236 -1 -1 -1 -1 34 218 18 50403.8 50403.8 21558.4 1347.40 0.07 0.0281563 0.0239356 1020 3049 -1 142 9 139 176 4698 2930 3.29429 3.29429 -44.332 -3.29429 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00541739 0.00503817 14 27 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.61 vpr 64.09 MiB -1 -1 0.08 17596 1 0.02 -1 -1 30140 -1 -1 7 13 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 13 12 149 129 1 68 32 6 6 36 clb auto 24.5 MiB 2.75 257 197 732 245 474 13 64.1 MiB 0.01 0.00 3.49758 3.49758 -52.6672 -3.49758 3.49758 0.02 0.000156374 0.000142533 0.00392726 0.00368989 -1 -1 -1 -1 48 388 31 403230 176413 104013. 2889.24 0.11 0.0414693 0.0356383 3910 18599 -1 284 17 330 478 14391 6422 3.69853 3.69853 -57.0037 -3.69853 0 0 131137. 3642.71 0.00 0.01 0.01 -1 -1 0.00 0.00915593 0.00833327 25 38 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.32 vpr 65.20 MiB -1 -1 0.08 17980 1 0.02 -1 -1 30160 -1 -1 6 15 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 15 14 196 165 1 93 35 5 5 25 clb auto 25.2 MiB 1.42 387 299 1118 289 798 31 65.2 MiB 0.01 0.00 3.70693 3.64998 -62.024 -3.64998 3.64998 0.01 0.000202129 0.0001848 0.00594995 0.00555165 -1 -1 -1 -1 38 642 42 151211 151211 48493.3 1939.73 0.14 0.0566763 0.0489294 2100 8065 -1 443 21 562 836 28073 13943 4.5307 4.5307 -77.3289 -4.5307 0 0 61632.8 2465.31 0.00 0.02 0.00 -1 -1 0.00 0.0127536 0.0115505 36 51 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 4.33 vpr 65.36 MiB -1 -1 0.09 17596 1 0.03 -1 -1 30128 -1 -1 5 17 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66932 17 16 251 206 1 120 38 5 5 25 clb auto 25.7 MiB 3.40 485 430 227 58 164 5 65.4 MiB 0.01 0.00 3.91442 3.88071 -76.4934 -3.88071 3.88071 0.01 0.000245396 0.000224553 0.00332248 0.00320063 -1 -1 -1 -1 46 639 28 151211 126010 57775.2 2311.01 0.15 0.061068 0.0527302 2220 9391 -1 566 15 540 892 27101 12502 4.50773 4.50773 -92.5696 -4.50773 0 0 73020.3 2920.81 0.00 0.02 0.01 -1 -1 0.00 0.0138066 0.0127692 45 66 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.46 vpr 65.57 MiB -1 -1 0.09 18360 1 0.03 -1 -1 30076 -1 -1 9 19 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67144 19 18 308 249 1 134 46 6 6 36 clb auto 25.9 MiB 3.44 628 450 3408 877 2509 22 65.6 MiB 0.03 0.00 5.19392 4.85986 -99.9643 -4.85986 4.85986 0.02 0.000293829 0.000269579 0.0149755 0.0138941 -1 -1 -1 -1 56 839 22 403230 226817 117789. 3271.93 0.17 0.0794032 0.0696928 4086 21443 -1 597 17 428 696 24582 10181 4.89622 4.89622 -97.5059 -4.89622 0 0 149557. 4154.36 0.00 0.02 0.01 -1 -1 0.00 0.0165564 0.0152987 54 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt index 900ba99d8f4..9e56ce66f42 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 17.03 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.49 3.9173e-05 3.1698e-05 0.000338068 0.000271828 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00193749 0.00171766 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00201882 0.00189534 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common 4.41 vpr 57.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58528 6 7 19 26 0 19 26 3 3 9 -1 auto 18.3 MiB 0.00 51 51 216 43 63 110 57.2 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.70 2.1988e-05 1.7826e-05 0.000208624 0.000166423 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00147039 0.00133536 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00101656 0.000954631 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt index 160cbfe1388..c6ae836957f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.33 vpr 59.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60416 2 2 4 5 0 4 5 3 3 9 -1 auto 20.7 MiB 0.00 8 12 0 0 12 59.0 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7245e-05 1.217e-05 9.686e-05 7.1239e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.0017081 0.00158045 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00139703 0.00135574 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +heterogeneous_tile.xml sub_tile_directs.blif common 0.27 vpr 56.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58056 2 2 4 5 0 4 5 3 3 9 -1 auto 18.3 MiB 0.00 8 8 12 0 0 12 56.7 MiB 0.00 0.00 1.899 1.899 -3.798 -1.899 nan 0.01 9.727e-06 6.488e-06 6.998e-05 5.1168e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.00 0.00122818 0.00113256 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000846926 0.000812399 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index 6303f27bd50..da0293d8273 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 vpr 66.86 MiB -1 -1 0.36 22284 3 0.10 -1 -1 36712 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 99 73 292 365 1 173 192 8 8 64 io memory auto 27.1 MiB 0.06 704 10699 1176 8237 1286 66.9 MiB 0.06 0.00 2.09255 -114.438 -2.09255 2.09255 0.09 0.000494971 0.000445037 0.0176268 0.0158319 -1 -1 -1 -1 32 1440 34 2.23746e+06 1.57199e+06 106908. 1670.44 0.32 0.14258 0.127902 4378 18911 -1 1142 12 555 876 46439 15775 1.9226 1.9226 -129.963 -1.9226 -0.449924 -0.248875 130676. 2041.82 0.01 0.04 0.02 -1 -1 0.01 0.0280032 0.0259551 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.13 vpr 65.30 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32716 -1 -1 20 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66864 99 73 292 365 1 172 193 8 8 64 io memory auto 25.6 MiB 0.04 1172 675 12447 1623 9101 1723 65.3 MiB 0.03 0.00 1.95866 1.82604 -115.206 -1.82604 1.82604 0.04 0.000448857 0.000413203 0.0118962 0.0110762 -1 -1 -1 -1 32 1268 15 2.23746e+06 1.62588e+06 106908. 1670.44 0.13 0.0638055 0.0575788 4378 18911 -1 1059 9 499 808 37153 12810 1.99391 1.99391 -128.303 -1.99391 -0.246226 -0.119866 130676. 2041.82 0.00 0.02 0.01 -1 -1 0.00 0.0126544 0.0117786 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 9a4d84cf163..4c74c74dc2a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 1.36 vpr 68.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70192 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.18 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000585274 0.000508741 0.0133922 0.0121686 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183472 0.161021 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0299915 0.0274705 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.08 vpr 68.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70320 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.7 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000329127 0.000280288 0.00811479 0.00735661 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.35 0.13039 0.113608 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0216396 0.0198831 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.83 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70724 10 10 168 178 1 162 111 14 14 196 clb auto 29.5 MiB 0.87 1467 5165 686 4267 212 69.1 MiB 0.06 0.00 2.95542 -36.8348 -2.95542 2.95542 0.33 0.000607935 0.000523594 0.0180811 0.0161249 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.224715 0.196946 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.10 -1 -1 0.03 0.0292402 0.0269351 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.85 vpr 68.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69972 10 10 168 178 1 75 33 7 7 49 clb auto 28.8 MiB 0.15 414 605 98 486 21 68.3 MiB 0.01 0.00 2.40687 -27.3475 -2.40687 2.40687 0.04 0.000340986 0.000290037 0.00724905 0.00664099 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.16 0.0618811 0.0547109 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.03 0.01 -1 -1 0.00 0.0207833 0.0191052 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.40 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70700 10 10 168 178 1 163 124 14 14 196 clb auto 29.4 MiB 0.95 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.22 0.000345985 0.000292911 0.012717 0.0113191 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.21 0.0326189 0.0295477 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.08 -1 -1 0.03 0.0265139 0.024324 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.40 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70232 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.6 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000587109 0.000509454 0.0135198 0.0122638 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183086 0.160678 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0347629 0.0319856 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.32 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70240 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.16 399 703 140 536 27 68.6 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.03 0.000756907 0.000658585 0.016978 0.0153763 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.44 0.169468 0.148387 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.03477 0.0320116 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.38 vpr 68.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70504 10 10 168 178 1 162 111 14 14 196 clb auto 29.2 MiB 0.88 1467 5165 686 4267 212 68.9 MiB 0.04 0.00 2.95542 -36.8348 -2.95542 2.95542 0.28 0.000322881 0.000275771 0.0115436 0.0102519 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.09 0.158857 0.137775 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.02 0.05 0.05 -1 -1 0.02 0.0172724 0.0158752 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.48 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70176 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000502609 0.00043998 0.0125423 0.0114378 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.54 0.190745 0.166737 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.07 0.02 -1 -1 0.00 0.0474457 0.0433946 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 30.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30760 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30632 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 30.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31272 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml styr.blif common_--target_ext_pin_util_1 0.71 vpr 66.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67956 10 10 168 178 1 75 32 6 6 36 clb auto 26.7 MiB 0.11 467 424 582 89 470 23 66.4 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000313613 0.000281494 0.00679637 0.00633558 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0534045 0.0470259 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0179228 0.0165339 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.72 vpr 66.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68432 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.11 467 424 582 89 470 23 66.8 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000305552 0.000274195 0.00713015 0.0066753 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.054037 0.0476882 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0176859 0.0162969 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.56 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68816 10 10 168 178 1 162 110 14 14 196 clb auto 27.5 MiB 0.42 2218 1472 5633 779 4632 222 67.2 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.15 0.00031345 0.000281685 0.00904718 0.00829193 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.27 0.0481118 0.0422936 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.01 0.03 0.04 -1 -1 0.01 0.0135904 0.0125798 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.78 vpr 66.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68504 10 10 168 178 1 73 34 7 7 49 clb auto 27.1 MiB 0.13 556 403 749 133 594 22 66.9 MiB 0.01 0.00 2.47538 2.3678 -27.2356 -2.3678 2.3678 0.02 0.000298629 0.000272401 0.00710384 0.00662899 -1 -1 -1 -1 28 1121 29 1.07788e+06 754516 79600.7 1624.51 0.14 0.0554737 0.0489437 3864 14328 -1 1032 22 640 2278 94416 33063 2.98849 2.98849 -34.8096 -2.98849 0 0 95067.4 1940.15 0.00 0.04 0.01 -1 -1 0.00 0.0199587 0.0182086 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.42 vpr 66.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68488 10 10 168 178 1 163 124 14 14 196 clb auto 27.5 MiB 0.44 2325 1534 6922 992 5667 263 66.9 MiB 0.03 0.00 4.16044 3.06133 -37.5377 -3.06133 3.06133 0.14 0.000311352 0.000274658 0.00930477 0.00849636 -1 -1 -1 -1 20 3156 16 9.20055e+06 5.60498e+06 295730. 1508.82 0.15 0.02425 0.0219885 18004 60473 -1 3023 14 646 2892 171027 37325 3.649 3.649 -45.9039 -3.649 0 0 387483. 1976.95 0.01 0.04 0.03 -1 -1 0.01 0.0134846 0.0122796 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 0.69 vpr 66.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68048 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.11 467 424 582 89 470 23 66.5 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000306309 0.000275002 0.00676603 0.00631847 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0532485 0.0469451 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0175558 0.0161696 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 0.73 vpr 66.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68428 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.11 467 424 582 89 470 23 66.8 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000307986 0.000276629 0.0070174 0.00655743 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0545965 0.0481718 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0179832 0.0165712 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 1.50 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68808 10 10 168 178 1 162 110 14 14 196 clb auto 27.5 MiB 0.41 2218 1472 5633 779 4632 222 67.2 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.14 0.000314699 0.000283874 0.00894991 0.00821764 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.26 0.0462803 0.0408134 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.02 0.03 0.04 -1 -1 0.02 0.0139896 0.0128573 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 0.71 vpr 66.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67820 10 10 168 178 1 75 32 6 6 36 clb auto 26.9 MiB 0.11 467 424 582 89 470 23 66.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.01 0.00030683 0.000275575 0.00684586 0.00639772 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0539268 0.047514 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.017759 0.0163694 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 vpr 27.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28308 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 vpr 28.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28940 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.8 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.08 vpr 27.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28552 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.4 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 28.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28768 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt index b99a452bc00..d76b9e88079 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 8.05 vpr 75.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76868 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.4 MiB 3.87 8858 177806 51921 111135 14750 75.1 MiB 1.04 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00614227 0.00545306 0.382618 0.335662 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.30 0.645332 0.579161 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 3.97 vpr 74.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 118 229 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76288 229 197 2152 2349 1 1012 544 16 16 256 io auto 34.5 MiB 1.98 13816 8635 175845 51740 110676 13429 74.5 MiB 0.61 0.01 3.6187 2.93018 -676.548 -2.93018 2.93018 0.00 0.00279674 0.00248348 0.242611 0.219358 -1 -1 -1 -1 -1 11066 15 1.05632e+07 6.35949e+06 4.24953e+06 16599.7 0.17 0.383649 0.351659 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt index dac263af64c..0494e386027 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/config.txt @@ -27,3 +27,6 @@ pass_requirements_file=pass_requirements.txt script_params_common = -track_memory_usage script_params_list_add = script_params_list_add = --router_algorithm parallel --num_workers 4 +script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index b003134057c..996a275157f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,3 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.63 vpr 68.02 MiB -1 -1 0.39 22168 3 0.11 -1 -1 36800 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69656 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.23 0.00 1.86472 -118.834 -1.86472 1.86472 0.15 0.000594963 0.000540506 0.0732034 0.0668337 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.54 0.213559 0.195205 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.08 -1 -1 0.02 0.0300207 0.027912 - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 2.86 vpr 68.12 MiB -1 -1 0.35 22168 3 0.11 -1 -1 36740 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69760 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.1 MiB 0.27 0.00 1.86472 -118.834 -1.86472 1.86472 0.21 0.000644886 0.000574461 0.100184 0.0946805 -1 -1 -1 -1 38 1379 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.64 0.202724 0.187418 12522 62564 -1 1115 10 390 630 21561 6939 1.90702 1.90702 -131.117 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.021384 0.0193317 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.94 vpr 66.48 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32732 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68076 99 130 344 474 1 228 298 12 12 144 clb auto 26.8 MiB 0.10 1675 704 66963 20370 32791 13802 66.5 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000562371 0.000525588 0.0406586 0.038039 -1 -1 -1 -1 40 1453 15 5.66058e+06 4.21279e+06 333335. 2314.82 0.58 0.162361 0.14854 12666 64609 -1 1222 11 442 668 30453 10334 2.02932 2.02932 -138.236 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0185134 0.0173313 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.87 vpr 66.56 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32732 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68156 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.10 1675 704 66963 20370 32791 13802 66.6 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000558315 0.00052341 0.0411328 0.0379157 -1 -1 -1 -1 40 1452 13 5.66058e+06 4.21279e+06 333335. 2314.82 0.54 0.134079 0.119822 12666 64609 -1 1250 11 460 694 31414 10385 2.02932 2.02932 -140.547 -2.02932 -0.436676 -0.298787 419432. 2912.72 0.01 0.02 0.04 -1 -1 0.01 0.0157064 0.0140295 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 2.16 vpr 66.34 MiB -1 -1 0.21 18828 3 0.06 -1 -1 32772 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67932 99 130 344 474 1 228 298 12 12 144 clb auto 26.5 MiB 0.10 1675 704 66963 20370 32791 13802 66.3 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.10 0.000551715 0.000515 0.0404626 0.0378544 -1 -1 -1 -1 40 1412 11 5.66058e+06 4.21279e+06 333335. 2314.82 0.78 0.166185 0.152303 12666 64609 -1 1211 10 419 673 142013 142013 1.98169 1.98169 -135.576 -1.98169 -0.436676 -0.298787 419432. 2912.72 0.01 0.05 0.04 -1 -1 0.01 0.0176156 0.0165382 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 2.23 vpr 66.57 MiB -1 -1 0.22 18444 3 0.06 -1 -1 32724 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68168 99 130 344 474 1 228 298 12 12 144 clb auto 26.8 MiB 0.10 1675 704 66963 20370 32791 13802 66.6 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000570894 0.000535109 0.0411409 0.0385856 -1 -1 -1 -1 40 1412 11 5.66058e+06 4.21279e+06 333335. 2314.82 0.84 0.161192 0.147867 12666 64609 -1 1211 10 419 673 140888 140888 1.98169 1.98169 -135.576 -1.98169 -0.436676 -0.298787 419432. 2912.72 0.01 0.10 0.04 -1 -1 0.01 0.0169308 0.0158811 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 2.12 vpr 66.28 MiB -1 -1 0.21 18444 3 0.06 -1 -1 32736 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67868 99 130 344 474 1 228 298 12 12 144 clb auto 26.5 MiB 0.10 1675 704 66963 20370 32791 13802 66.3 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000568987 0.000532832 0.0407334 0.0381626 -1 -1 -1 -1 40 1412 11 5.66058e+06 4.21279e+06 333335. 2314.82 0.77 0.160479 0.147022 12666 64609 -1 1211 10 419 673 141703 53908 1.98169 1.98169 -135.576 -1.98169 -0.436676 -0.298787 419432. 2912.72 0.01 0.05 0.04 -1 -1 0.01 0.0175063 0.0163964 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt index 7b4fc76c6e6..d74871bcfe5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.55 vpr 67.97 MiB -1 -1 0.42 22420 3 0.14 -1 -1 36800 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69600 99 130 344 474 1 225 298 12 12 144 clb auto 28.5 MiB 0.19 695 57013 16754 28454 11805 68.0 MiB 0.25 0.00 1.84453 -73.0907 -1.84453 1.84453 0.29 0.000572985 0.000494317 0.0593261 0.049655 -1 -1 -1 -1 32 1551 10 5.66058e+06 4.21279e+06 281316. 1953.58 1.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 1.25 vpr 66.54 MiB -1 -1 0.21 18440 3 0.06 -1 -1 32720 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68140 99 130 344 474 1 224 298 12 12 144 clb auto 27.1 MiB 0.09 1590 710 59003 16103 31150 11750 66.5 MiB 0.09 0.00 2.39882 1.86362 -71.5534 -1.86362 1.86362 0.09 0.000538644 0.000497828 0.023206 0.0214651 -1 -1 -1 -1 30 1493 8 5.66058e+06 4.21279e+06 267238. 1855.82 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt index 50b6703de2b..f151570289b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.13 vpr 67.88 MiB -1 -1 0.41 22284 3 0.13 -1 -1 36924 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69508 99 130 344 474 1 218 298 12 12 144 clb auto 28.4 MiB 0.23 632 70943 19608 36161 15174 67.9 MiB 0.23 0.00 2.24009 0 0 2.24009 0.25 0.000717536 0.00062496 0.0508972 0.0435443 -1 -1 -1 -1 32 1480 8 5.66058e+06 4.21279e+06 281316. 1953.58 0.55 0.227253 0.196073 11950 52952 -1 1327 7 304 419 24960 8371 2.42926 2.42926 0 0 0 0 345702. 2400.71 0.03 0.05 0.08 -1 -1 0.03 0.020098 0.0186968 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 1.54 vpr 66.54 MiB -1 -1 0.22 18440 3 0.07 -1 -1 32712 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68132 99 130 344 474 1 220 298 12 12 144 clb auto 26.8 MiB 0.08 1597 670 73928 20988 37298 15642 66.5 MiB 0.10 0.00 2.12094 1.86992 0 0 1.86992 0.09 0.00032505 0.000297593 0.0266159 0.0244779 -1 -1 -1 -1 32 1510 10 5.66058e+06 4.21279e+06 281316. 1953.58 0.24 0.114031 0.0985162 11950 52952 -1 1387 6 289 390 22972 7530 2.02363 2.02363 0 0 0 0 345702. 2400.71 0.01 0.01 0.03 -1 -1 0.01 0.00829442 0.00764588 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt index 79ab5b22460..ae8e519b4a4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt @@ -24,7 +24,10 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common = -starting_stage vpr +script_params_common = -starting_stage vpr --generate_net_timing_report on script_params_list_add=--timing_report_detail netlist script_params_list_add=--timing_report_detail aggregated script_params_list_add=--timing_report_detail detailed +script_params_list_add=--timing_report_detail netlist --flat_routing on +script_params_list_add=--timing_report_detail aggregated --flat_routing on +script_params_list_add=--timing_report_detail detailed --flat_routing on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index a5bee947840..f82233e2459 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.50 vpr 67.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68660 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.6443e-05 3.2529e-05 0.000274786 0.000214986 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00211509 0.0019009 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0017763 0.00169895 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.49 vpr 67.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8016e-05 3.4218e-05 0.000283686 0.000224427 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0022472 0.00206472 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00179634 0.00171755 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.51 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68932 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 6.2523e-05 4.6425e-05 0.000366128 0.000294026 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00236124 0.00216436 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00189537 0.00181322 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.37 vpr 65.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66624 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.4867e-05 1.6785e-05 0.000178305 0.000138626 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0013303 0.00121195 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0010544 0.00100577 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.38 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66628 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5617e-05 1.7506e-05 0.000177134 0.000138581 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0012973 0.00118019 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00105506 0.00100757 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.41 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66628 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.00 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5232e-05 1.7334e-05 0.000170999 0.000134182 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00125289 0.00113927 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00129683 0.00123 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist_--flat_routing_on 0.81 vpr 70.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72112 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.5406e-05 1.7598e-05 0.000175321 0.000137685 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.25 0.00131841 0.00118136 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.12 0.00 0.00 0.11 0.00 0.00103786 0.000967845 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated_--flat_routing_on 0.81 vpr 70.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72492 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5095e-05 1.6967e-05 0.000167727 0.000130306 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.26 0.00127606 0.0011399 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.12 0.00 0.00 0.12 0.00 0.00102446 0.000963839 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed_--flat_routing_on 0.85 vpr 70.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72112 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5982e-05 1.7909e-05 0.000172322 0.000134495 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.26 0.00129831 0.00116036 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.13 0.00 0.00 0.12 0.00 0.00101752 0.000959208 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt index db634e1dc04..f5a70e45013 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.81 vpr 69.01 MiB -1 -1 0.66 26668 4 0.21 -1 -1 35972 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70664 11 2 303 283 2 78 28 7 7 49 clb auto 29.4 MiB 0.25 285 784 175 539 70 69.0 MiB 0.04 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000759025 0.000652417 0.0254764 0.023241 -1 -1 -1 -1 -1 313 6 1.07788e+06 808410 219490. 4479.39 0.03 0.050656 0.046841 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.77 vpr 66.82 MiB -1 -1 0.40 23072 4 0.10 -1 -1 32592 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68428 11 2 303 283 2 85 28 7 7 49 clb auto 27.2 MiB 0.11 462 289 1204 263 848 93 66.8 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.000386086 0.000344716 0.0143127 0.012902 -1 -1 -1 -1 -1 314 6 1.07788e+06 808410 219490. 4479.39 0.01 0.0280135 0.0257414 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt index 17b20f60f24..0b366a2736d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/config.txt @@ -31,3 +31,9 @@ script_params_list_add = --timing_update_type incremental script_params_list_add = --timing_update_type incremental --quench_recompute_divider 999999999 #Do post-move incremental STA during quench script_params_list_add = --timing_update_type incremental --router_algorithm parallel --num_workers 4 # rarely exercised code path script_params_list_add = --timing_update_type full --router_algorithm parallel --num_workers 4 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type incremental --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --timing_update_type full --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index e65df342f6a..0e6c2e24870 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,7 +1,13 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.06 vpr 65.94 MiB -1 -1 0.49 27024 5 0.12 -1 -1 36972 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67520 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000242517 0.000210755 0.00440565 0.00392683 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0164282 0.0146736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.57 vpr 66.14 MiB -1 -1 0.70 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000439525 0.000384869 0.00748551 0.00667971 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.02 0.0256815 0.0230005 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.67 vpr 66.16 MiB -1 -1 0.82 27152 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 3.5959e-05 2.737e-05 0.00308117 0.00275747 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0135928 0.0105523 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.25 vpr 66.16 MiB -1 -1 0.65 27036 5 0.12 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000221863 9.7941e-05 0.00222519 0.00187901 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.00928043 0.00694563 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.74 vpr 66.05 MiB -1 -1 0.84 26784 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67632 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 5.1198e-05 3.2395e-05 0.002938 0.00248994 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.02 0.0136494 0.00987341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 2.01 vpr 66.03 MiB -1 -1 0.85 27040 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67616 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00150082 0.00142957 0.0169996 0.0159511 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.07 0.0553928 0.0438556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.09 vpr 64.27 MiB -1 -1 0.42 23428 5 0.11 -1 -1 32572 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000222766 0.000201734 0.00389424 0.00360389 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.0142381 0.0128197 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.09 vpr 63.95 MiB -1 -1 0.41 23428 5 0.10 -1 -1 32576 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65484 10 2 181 183 1 36 24 6 6 36 clb auto 24.6 MiB 0.02 196 160 398 88 284 26 63.9 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000222779 0.000201937 0.00391759 0.00362401 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.0142174 0.0127941 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.11 vpr 64.30 MiB -1 -1 0.44 23428 5 0.10 -1 -1 32584 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 10 2 181 183 1 36 24 6 6 36 clb auto 24.8 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.0708e-05 1.5231e-05 0.0014017 0.00127195 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.00714763 0.00535987 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.08 vpr 63.74 MiB -1 -1 0.41 23416 5 0.10 -1 -1 32592 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65272 10 2 181 183 1 36 24 6 6 36 clb auto 24.7 MiB 0.02 196 160 398 88 284 26 63.7 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000128757 3.5271e-05 0.00160333 0.00138472 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.00746153 0.00560158 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.13 vpr 63.79 MiB -1 -1 0.41 23800 5 0.10 -1 -1 32580 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65316 10 2 181 183 1 36 24 6 6 36 clb auto 24.8 MiB 0.03 196 160 398 88 284 26 63.8 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 4.2273e-05 3.0292e-05 0.00168368 0.0014329 -1 -1 -1 -1 -1 146 18 646728 646728 138825. 3856.24 0.01 0.00798524 0.00566268 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 1.10 vpr 64.06 MiB -1 -1 0.41 23416 5 0.10 -1 -1 32584 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65596 10 2 181 183 1 36 24 6 6 36 clb auto 24.6 MiB 0.02 196 160 398 88 284 26 64.1 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000395659 0.000368361 0.00601719 0.00558884 -1 -1 -1 -1 -1 146 18 646728 646728 138825. 3856.24 0.02 0.0192173 0.0172102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.08 vpr 64.30 MiB -1 -1 0.40 23048 5 0.10 -1 -1 32596 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.0413e-05 1.4906e-05 0.00139428 0.00126275 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.03 0.00728859 0.00538349 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.15 vpr 64.30 MiB -1 -1 0.41 23428 5 0.10 -1 -1 32624 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.0732e-05 1.524e-05 0.00145249 0.00132501 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.08 0.00760196 0.00568525 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.10 vpr 64.30 MiB -1 -1 0.42 23044 5 0.11 -1 -1 32596 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.1096e-05 1.5558e-05 0.00147388 0.00133793 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.05 0.0075207 0.00563955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.14 vpr 64.30 MiB -1 -1 0.42 23044 5 0.11 -1 -1 32588 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000221012 0.00020011 0.00389967 0.00361209 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.03 0.0153274 0.0137388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.14 vpr 64.28 MiB -1 -1 0.41 23048 5 0.11 -1 -1 32588 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000225132 0.000204043 0.00417724 0.00383718 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.05 0.0187942 0.0167045 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.13 vpr 64.27 MiB -1 -1 0.42 23428 5 0.11 -1 -1 32588 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000223349 0.000202453 0.00387379 0.0035863 -1 -1 -1 -1 -1 145 20 646728 646728 138825. 3856.24 0.04 0.0153058 0.0136886 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index e84a1129700..e88e2fe2f90 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.79 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215864 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.3 MiB 15.63 75097 245792 47628 188491 9673 1158.7 MiB 16.87 0.21 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0552629 0.0482483 4.22516 3.43532 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 5.27 -1 -1 1158.7 MiB 5.35 6.14131 5.12726 1158.7 MiB -1 3.33 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 33.99 vpr 1.16 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1214544 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 1076.9 MiB 7.80 231619 75107 234775 43541 180854 10380 1154.4 MiB 6.01 0.08 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.00 0.0216745 0.0190067 1.74141 1.438 87307 6.90501 21230 1.67906 25811 34329 9106433 1637889 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.36451 2.98815 -5707.14 -4.36451 0 0 3.24 -1 -1 1154.4 MiB 2.59 2.80019 2.37571 1154.4 MiB -1 1.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt index 7d3888ea0e0..b5222df5ce6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 19.43 vpr 384.88 MiB 35 93 0 0 8 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 394112 18 17 2338 2195 1 2035 136 17 13 221 io_cell auto 342.6 MiB 9.23 11597 14096 2127 10583 1386 384.9 MiB 0.99 0.03 3.78594 -3334.96 -2.78594 3.78594 0.00 0.0127693 0.0106573 0.428449 0.35312 12754 6.27657 3971 1.95423 6857 16497 4298918 925978 0 0 3.37726e+06 15281.7 12 52540 541133 -1 3.215 3.215 -2910.24 -2.215 0 0 1.33 -1 -1 384.9 MiB 1.91 0.811838 0.706005 384.9 MiB -1 0.27 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 9.50 vpr 385.09 MiB 35 86 0 0 8 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 394328 18 17 2338 2195 1 2026 129 17 13 221 io_cell auto 344.2 MiB 4.44 19688 12064 13129 2012 9707 1410 385.1 MiB 0.43 0.01 4.85192 3.71062 -3391.61 -2.71062 3.71062 0.00 0.00349484 0.00291013 0.180937 0.154879 13833 6.83786 4143 2.04795 6992 16873 4273349 902603 0 0 3.37726e+06 15281.7 13 52540 541133 -1 3.321 3.321 -2993.48 -2.321 0 0 0.55 -1 -1 385.1 MiB 0.88 0.370237 0.329843 385.1 MiB -1 0.14 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 6ff0e8d886f..2870c0dcfa7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 22.01 vpr 69.98 MiB -1 -1 0.42 25672 5 0.18 -1 -1 37676 -1 -1 17 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 71656 66 96 983 697 1 557 191 16 16 256 mult_27 auto 30.8 MiB 2.52 4520 41915 13784 24449 3682 70.0 MiB 0.47 0.01 16.7771 -983.813 -16.7771 16.7771 0.51 0.00380097 0.00356084 0.223806 0.20783 -1 -1 -1 -1 82 9891 30 4.83877e+06 1.03328e+06 1.63760e+06 6396.87 14.79 1.72784 1.60303 43164 348864 -1 8812 16 2703 5592 1100371 345017 16.7238 16.7238 -1023.47 -16.7238 0 0 2.03272e+06 7940.32 0.12 0.37 0.48 -1 -1 0.12 0.123499 0.117943 138 202 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 5.80 vpr 68.89 MiB -1 -1 0.20 22204 5 0.10 -1 -1 33784 -1 -1 17 66 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70540 66 96 983 697 1 561 191 16 16 256 mult_27 auto 29.3 MiB 0.61 8149 4596 38072 11997 23544 2531 68.9 MiB 0.22 0.00 19.4757 17.0827 -970.661 -17.0827 17.0827 0.21 0.00129546 0.00120683 0.0982081 0.091818 -1 -1 -1 -1 62 12202 30 4.83877e+06 1.03328e+06 1.31386e+06 5132.27 2.93 0.40155 0.371234 39852 267778 -1 9854 19 3552 7322 1583377 471194 17.0705 17.0705 -1067.68 -17.0705 0 0 1.60318e+06 6262.42 0.04 0.25 0.14 -1 -1 0.04 0.0690741 0.0653357 140 202 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index 8a9769fe6bb..5887a04a315 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.48 vpr 65.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66896 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000116029 0.000100823 0.0010942 0.00101432 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.3 MiB 0.01 0.00766251 0.00688033 65.3 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.51 vpr 65.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66796 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000165834 0.000146968 0.00119076 0.00110326 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.00909464 0.00816836 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.24 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000113726 9.7512e-05 0.00114825 0.00106423 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.3 MiB 0.03 -1 -1 65.3 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.24 vpr 65.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66624 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.1 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.00013832 0.000115541 0.000955845 0.00087775 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.1 MiB 0.03 -1 -1 65.1 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.17 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64492 6 8 39 47 1 20 17 5 5 25 clb auto 24.3 MiB 0.01 107 88 59 31 28 0 63.0 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 7.9358e-05 7.06e-05 0.000702625 0.000659908 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.0 MiB 0.01 0.00494254 0.00441175 63.0 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.17 vpr 62.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64364 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.01 107 88 59 31 28 0 62.9 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 7.9701e-05 7.0904e-05 0.000704152 0.00066155 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 62.9 MiB 0.01 0.00497552 0.00444693 62.9 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.18 vpr 63.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64692 6 8 39 47 1 20 17 5 5 25 clb auto 24.9 MiB 0.01 107 88 59 31 28 0 63.2 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.0556e-05 7.1754e-05 0.000710303 0.000667295 -1 -1 -1 -1 -1 -1 -1 -1 656 1029 31338 15241 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.2 MiB 0.02 -1 -1 63.2 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.19 vpr 63.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64668 6 8 39 47 1 20 17 5 5 25 clb auto 24.3 MiB 0.01 107 88 59 31 28 0 63.2 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 7.9004e-05 7.0259e-05 0.000720378 0.000678096 -1 -1 -1 -1 141 7.42105 65 3.42105 656 1029 31338 15241 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9119 -1.84852 0 0 0.00 -1 -1 63.2 MiB 0.02 -1 -1 63.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index cb597e00427..54d5147cb89 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.77 vpr 60.00 MiB -1 -1 0.91 26856 6 0.21 -1 -1 36836 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61436 10 2 186 188 1 48 40 8 8 64 clb auto 20.5 MiB 0.04 230 992 145 785 62 60.0 MiB 0.03 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000447321 0.000382714 0.00843147 0.00745792 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.09 -1 -1 60.0 MiB 0.03 0.0220189 0.0194464 60.0 MiB -1 0.01 - k6_frac_N10_40nm.xml stereovision3.v common 2.04 vpr 61.65 MiB -1 -1 0.81 26884 5 0.16 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.07 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000403252 0.000354056 0.00494195 0.00440924 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.03 -1 -1 61.7 MiB 0.01 0.0168116 0.0156639 61.7 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 1.32 vpr 58.29 MiB -1 -1 0.39 23264 6 0.10 -1 -1 32592 -1 -1 28 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59688 10 2 186 188 1 46 40 8 8 64 clb auto 18.3 MiB 0.01 370 219 1196 185 951 60 58.3 MiB 0.01 0.00 3.46426 2.64808 -111.051 -2.64808 2.64808 0.00 0.000230277 0.000209848 0.00499518 0.00455702 -1 -1 -1 -1 190 4.41860 190 4.41860 181 461 16985 3541 80255.5 62421 276194. 4315.53 13 9480 40228 -1 2.65254 2.65254 -110.961 -2.65254 -0.0734 -0.0734 0.03 -1 -1 58.3 MiB 0.01 0.013254 0.0119008 58.3 MiB -1 0.00 +k6_frac_N10_40nm.xml stereovision3.v common 1.27 vpr 59.75 MiB -1 -1 0.39 23288 5 0.10 -1 -1 32580 -1 -1 7 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61184 10 2 181 183 1 38 19 5 5 25 clb auto 20.0 MiB 0.03 159 121 469 107 323 39 59.8 MiB 0.01 0.00 2.03188 2.03188 -84.6958 -2.03188 2.03188 0.00 0.000218134 0.000198163 0.00575791 0.00533131 -1 -1 -1 -1 105 3.00000 54 1.54286 61 90 1611 507 485046 377258 99699.4 3987.98 6 2523 14238 -1 2.07226 2.07226 -86.1872 -2.07226 0 0 0.01 -1 -1 59.8 MiB 0.01 0.0133683 0.0124329 59.8 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt index 0fde75bd1ed..f0211e745a4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.09 vpr 60.07 MiB -1 -1 0.81 26980 6 0.15 -1 -1 36756 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61512 10 2 186 188 1 48 40 8 8 64 clb auto 20.6 MiB 0.03 230 992 145 785 62 60.1 MiB 0.02 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000430706 0.00037483 0.00785446 0.00688801 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.08 -1 -1 60.1 MiB 0.02 0.0211284 0.0188358 60.1 MiB -1 0.01 - k6_frac_N10_40nm.xml stereovision3.v common 1.94 vpr 61.65 MiB -1 -1 0.77 26880 5 0.18 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.1 MiB 0.06 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000420371 0.000366917 0.00494209 0.00453968 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.02 -1 -1 61.7 MiB 0.01 0.0164382 0.0153894 61.7 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 1.31 vpr 57.90 MiB -1 -1 0.44 23268 6 0.10 -1 -1 32592 -1 -1 28 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59288 10 2 186 188 1 46 40 8 8 64 clb auto 17.9 MiB 0.01 370 219 1196 185 951 60 57.9 MiB 0.01 0.00 3.46426 2.64808 -111.051 -2.64808 2.64808 0.00 0.000227528 0.000206718 0.00514212 0.00468684 -1 -1 -1 -1 190 4.41860 190 4.41860 181 461 16985 3541 80255.5 62421 276194. 4315.53 13 9480 40228 -1 2.65254 2.65254 -110.961 -2.65254 -0.0734 -0.0734 0.03 -1 -1 57.9 MiB 0.01 0.0133773 0.0120246 57.9 MiB -1 0.00 +k6_frac_N10_40nm.xml stereovision3.v common 1.31 vpr 59.16 MiB -1 -1 0.41 23148 5 0.11 -1 -1 32568 -1 -1 7 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60580 10 2 181 183 1 38 19 5 5 25 clb auto 19.7 MiB 0.03 159 121 469 107 323 39 59.2 MiB 0.01 0.00 2.03188 2.03188 -84.6958 -2.03188 2.03188 0.00 0.000227941 0.000207215 0.00601851 0.00558608 -1 -1 -1 -1 105 3.00000 54 1.54286 61 90 1611 507 485046 377258 99699.4 3987.98 6 2523 14238 -1 2.07226 2.07226 -86.1872 -2.07226 0 0 0.01 -1 -1 59.2 MiB 0.01 0.0138386 0.0128888 59.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt index 9a8744d436c..2f0425ccd8e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 32.55 vpr 978.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001924 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.50 371 490 69 397 24 978.4 MiB 0.08 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000745164 0.00064564 0.0121362 0.0109717 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.4 MiB 0.14 0.0524157 0.0489871 978.4 MiB -1 0.02 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml styr.blif common 22.04 vpr 979.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002912 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.33 530 402 720 97 571 52 979.4 MiB 0.06 0.00 6.8225 6.61671 -72.4654 -6.61671 6.61671 0.00 0.000312489 0.00027995 0.00825822 0.00768717 -1 -1 -1 -1 669 10.4531 198 3.09375 255 965 67200 31259 0 0 194014. 2204.70 14 11730 32605 -1 6.73871 6.73871 -74.3689 -6.73871 0 0 0.04 -1 -1 979.4 MiB 0.05 0.0249525 0.0231555 979.4 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 783b9bb6553..8e74dc03ebf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -13,7 +13,6 @@ regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver regression_tests/vtr_reg_strong/strong_absorb_buffers regression_tests/vtr_reg_strong/strong_analysis_only -regression_tests/vtr_reg_strong/strong_analytic_placer regression_tests/vtr_reg_strong/strong_bidir regression_tests/vtr_reg_strong/strong_binary regression_tests/vtr_reg_strong/strong_binary_heap @@ -108,4 +107,5 @@ regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router regression_tests/vtr_reg_strong/strong_routing_constraints regression_tests/vtr_reg_strong/strong_vib -regression_tests/vtr_reg_strong/strong_3d +regression_tests/vtr_reg_strong/strong_3d/3d_cb +regression_tests/vtr_reg_strong/strong_3d/3d_sb diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt index 7b5437463d7..25a87198d21 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 5.51 vpr 77.59 MiB 0.04 8576 -1 -1 1 0.07 -1 -1 35240 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79456 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.13 1890 35427 11493 18934 5000 77.6 MiB 0.27 0.00 5.12303 -647.058 -5.12303 5.12303 0.48 0.00206617 0.00189672 0.14394 0.133207 -1 -1 -1 -1 64 3873 16 4.93594e+06 1.0962e+06 976140. 4980.31 2.20 0.636996 0.595296 31408 195022 -1 3500 9 851 887 209984 82943 4.57723 4.57723 -694.457 -4.57723 0 0 1.23909e+06 6321.90 0.09 0.15 0.39 -1 -1 0.09 0.0903946 0.0866517 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 8.46 odin 122.62 MiB 5.36 125568 -1 -1 1 0.05 -1 -1 32100 -1 -1 12 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77964 130 40 596 562 1 355 185 14 14 196 dsp_top auto 37.0 MiB 0.09 3418 1865 39635 13944 21044 4647 76.1 MiB 0.13 0.00 5.12303 5.12303 -651.76 -5.12303 5.12303 0.19 0.000866185 0.000806089 0.069875 0.0652099 -1 -1 -1 -1 82 3469 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.21 0.315755 0.291609 33448 250998 -1 3353 9 741 768 180939 69062 4.57723 4.57723 -669.54 -4.57723 0 0 1.53308e+06 7821.82 0.03 0.05 0.18 -1 -1 0.03 0.0246455 0.0233771 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt index 23cf7b0b85f..b6ed7b07205 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 14.85 vpr 81.40 MiB 0.10 11392 -1 -1 1 0.12 -1 -1 37676 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83352 130 40 1203 1030 1 586 196 14 14 196 dsp_top auto 41.3 MiB 0.63 2691 46285 14724 25599 5962 81.4 MiB 0.45 0.01 6.58999 -703.566 -6.58999 6.58999 0.48 0.00220042 0.00200207 0.214554 0.193316 -1 -1 -1 -1 108 5210 35 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 10.07 1.93637 1.74105 36552 325092 -1 4641 23 2669 2746 326887 113256 6.77766 6.77766 -770.287 -6.77766 0 0 1.93951e+06 9895.46 0.12 0.27 0.65 -1 -1 0.12 0.138318 0.125698 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 11.04 odin 218.25 MiB 6.64 223488 -1 -1 1 0.07 -1 -1 33976 -1 -1 23 130 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 81316 130 40 1203 1030 1 587 196 14 14 196 dsp_top auto 39.6 MiB 0.32 5039 2615 41733 12907 23223 5603 79.4 MiB 0.17 0.00 7.16349 6.55057 -693.511 -6.55057 6.55057 0.19 0.00100498 0.000913787 0.0833981 0.0763062 -1 -1 -1 -1 120 4838 28 4.93594e+06 1.40315e+06 1.69991e+06 8673.00 1.88 0.40623 0.365025 38028 369366 -1 4452 23 2538 2614 296097 92461 6.77726 6.77726 -734.869 -6.77726 0 0 2.14988e+06 10968.8 0.05 0.10 0.27 -1 -1 0.05 0.0620611 0.0571425 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt index 235e1da0107..1881b26da15 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.88 vpr 72.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74068 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.4 MiB 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00708147 0.00640458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 2.22 vpr 72.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73804 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.3 MiB 1.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00920908 0.00830291 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 0.97 vpr 70.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 130 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72308 130 150 1169 1319 1 885 365 12 12 144 clb auto 30.7 MiB 0.62 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00294981 0.00272321 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 0.95 vpr 70.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 130 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72368 130 150 1216 1366 1 925 374 12 12 144 clb auto 30.9 MiB 0.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00295932 0.00273669 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt index d3c7d61af84..b884d061731 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.36 vpr 66.46 MiB 0.08 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68060 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 425 2283 406 1804 73 66.5 MiB 0.05 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000768694 0.000638603 0.0252644 0.022728 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.5 MiB 0.08 0.0775573 0.0705898 66.5 MiB -1 0.01 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.76 vpr 69.14 MiB 0.09 10368 -1 -1 5 0.19 -1 -1 36576 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70804 11 30 313 321 2 115 55 7 7 49 clb auto 29.7 MiB 0.40 448 1927 352 1502 73 69.1 MiB 0.07 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000863635 0.000740182 0.0221309 0.0195205 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.05 -1 -1 69.1 MiB 0.06 0.0568064 0.051944 69.1 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.40 odin 166.88 MiB 2.47 170880 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67040 11 30 262 292 2 99 61 7 7 49 clb auto 25.4 MiB 0.04 688 437 2341 384 1888 69 65.5 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000377471 0.000327024 0.0100275 0.00887733 -1 -1 -1 -1 434 4.56842 177 1.86316 730 1655 64750 15779 1.07788e+06 1.07788e+06 207176. 4228.08 23 4440 29880 -1 2.44651 2.32748 -175.142 -2.44651 0 0 0.02 -1 -1 65.5 MiB 0.03 0.0315352 0.027637 65.5 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.59 odin 157.12 MiB 2.50 160896 -1 -1 5 0.11 -1 -1 33308 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69568 11 30 313 321 2 114 55 7 7 49 clb auto 28.7 MiB 0.18 671 455 1719 301 1356 62 67.9 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000410886 0.000359843 0.0107195 0.00966653 -1 -1 -1 -1 571 5.28704 218 2.01852 192 380 9910 2908 1.07788e+06 754516 219490. 4479.39 12 5100 32136 -1 2.66069 2.29553 -166.559 -2.66069 0 0 0.02 -1 -1 67.9 MiB 0.02 0.0302329 0.0275299 67.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/config.txt deleted file mode 100644 index 4dd0bc69c73..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/config.txt +++ /dev/null @@ -1,28 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics.v - -# Add architectures to list to sweep -arch_list_add=k6_frac_N10_mem32K_40nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements.txt - -# Script parameters -#script_params="" -script_params =-start odin -track_memory_usage --enable_analytic_placer true diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt deleted file mode 100644 index df63a32e433..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.27 vpr 67.81 MiB 0.06 9984 -1 -1 3 0.40 -1 -1 39908 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.8 MiB 0.14 1080 1293 313 846 134 67.8 MiB 0.06 0.00 2.45187 -223.196 -2.45187 2.45187 0.31 0.000607122 0.000549979 0.00491114 0.00472929 -1 -1 -1 -1 34 2076 26 5.66058e+06 4.21279e+06 293002. 2034.74 1.92 0.386002 0.351306 12094 55633 -1 1662 10 540 720 43948 13958 2.71514 2.71514 -233.572 -2.71514 0 0 360780. 2505.42 0.02 0.06 0.08 -1 -1 0.02 0.0335019 0.0302667 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt index c57ad9bdb40..1d55e8e0081 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 1.89 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.09 0.000707997 0.000614185 0.0204147 0.0180597 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.97 0.236366 0.209157 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.10 0.02 -1 -1 0.01 0.0335803 0.0304927 - k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 60.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61816 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.05 1219 4247 600 3483 164 60.4 MiB 0.05 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000681666 0.000592315 0.0189188 0.016758 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.80 0.256847 0.227018 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.10 0.03 -1 -1 0.02 0.0370258 0.033411 - k4_n4_v7_l1_bidir.xml styr.blif common 2.35 vpr 61.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62632 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1285 7613 1616 5547 450 61.2 MiB 0.12 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.000675324 0.000585254 0.0347554 0.0308708 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.17 0.183607 0.16336 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.13 0.02 -1 -1 0.01 0.0396264 0.0357171 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.49 vpr 60.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61772 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.05 1234 4643 666 3821 156 60.3 MiB 0.09 0.01 3.51175 -43.7413 -3.51175 3.51175 0.09 0.000766831 0.000671887 0.0247522 0.0222268 -1 -1 -1 -1 14 2053 42 2.43e+06 2.07e+06 -1 -1 2.23 0.282741 0.249953 3402 27531 -1 1991 28 1438 5059 778762 132220 26.9853 26.9853 -248.248 -26.9853 0 0 -1 -1 0.01 0.37 0.03 -1 -1 0.01 0.0480187 0.0429407 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml styr.blif common 0.97 vpr 58.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60368 10 10 253 263 1 171 92 11 11 121 clb auto 19.7 MiB 0.03 1829 1341 4439 719 3525 195 59.0 MiB 0.03 0.00 8.75156 5.95188 -76.2362 -5.95188 5.95188 0.03 0.000362225 0.000326331 0.00992626 0.00907431 -1 -1 -1 -1 14 2179 38 2.43e+06 2.16e+06 -1 -1 0.45 0.0943506 0.081458 3402 27531 -1 1923 17 1033 3494 176707 22465 7.58177 7.58177 -95.383 -7.58177 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0158882 0.0142757 +k4_n4_v7_longline_bidir.xml styr.blif common 0.91 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60464 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1318 3611 426 3020 165 59.0 MiB 0.02 0.00 5.19817 4.47516 -54.2373 -4.47516 4.47516 0.04 0.000357538 0.00032632 0.00871064 0.00799197 -1 -1 -1 -1 17 2528 41 2.43e+06 2.16e+06 -1 -1 0.35 0.0835775 0.0724263 3202 31699 -1 2252 25 1472 4968 313575 40767 9.40236 9.40236 -107.704 -9.40236 0 0 -1 -1 0.01 0.06 0.01 -1 -1 0.01 0.0211626 0.0187929 +k4_n4_v7_l1_bidir.xml styr.blif common 1.04 vpr 59.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60436 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1340 8579 1857 6361 361 59.0 MiB 0.04 0.00 11.3865 6.30908 -81.1511 -6.30908 6.30908 0.04 0.000371081 0.000335053 0.0176792 0.0161598 -1 -1 -1 -1 11 1565 28 2.43e+06 2.16e+06 -1 -1 0.44 0.0827522 0.0722935 4842 26035 -1 1365 23 1309 5061 314893 55846 8.55913 8.55913 -101.511 -8.55913 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0191151 0.0170035 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.24 vpr 59.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61052 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1326 4025 528 3322 175 59.6 MiB 0.02 0.00 4.50889 3.47884 -44.786 -3.47884 3.47884 0.03 0.000371134 0.000327233 0.00920502 0.00841011 -1 -1 -1 -1 16 2193 28 2.43e+06 2.16e+06 -1 -1 0.64 0.0871949 0.0752766 3522 30407 -1 2061 19 1236 4213 766518 139225 14.4125 14.4125 -146.898 -14.4125 0 0 -1 -1 0.00 0.11 0.01 -1 -1 0.00 0.0176916 0.0159417 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt index 0bd2ba5a636..5397c667c6c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.92 vpr 66.34 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36540 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000749649 0.00064239 0.0161237 0.0140852 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.28 0.147245 0.127953 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.08 0.01 -1 -1 0.00 0.047308 0.0404063 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.40 vpr 66.13 MiB 0.07 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67716 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.08 427 1815 293 1474 48 66.1 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000744837 0.000636456 0.0185703 0.0149662 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.64 0.298818 0.25277 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.10 0.01 -1 -1 0.00 0.0500747 0.044978 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 3.86 odin 167.25 MiB 2.53 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67272 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 430 2821 451 2299 71 65.7 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000428515 0.000373651 0.0118289 0.0104043 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.18 0.0738407 0.0618149 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0224978 0.0195692 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 4.06 odin 166.88 MiB 2.52 170880 -1 -1 4 0.12 -1 -1 33096 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 430 2821 451 2299 71 65.7 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.00040163 0.000347773 0.0117465 0.0103215 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.40 0.133348 0.110447 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0230397 0.0200505 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt index 7d75ebf7e22..a646b3f38b3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.32 vpr 67.44 MiB 0.07 9856 -1 -1 3 0.36 -1 -1 39552 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69060 99 130 363 493 1 255 305 13 13 169 clb auto 27.9 MiB 0.11 817 73151 23083 37131 12937 67.4 MiB 0.30 0.01 2.36834 -235.63 -2.36834 2.36834 0.29 0.00233393 0.00223993 0.0738859 0.066584 -1 -1 -1 -1 32 1352 17 6.63067e+06 4.59005e+06 323148. 1912.12 0.52 0.196726 0.178694 11612 59521 -1 1138 16 719 1086 65347 22389 2.48507 2.48507 -238.178 -2.48507 0 0 396943. 2348.77 0.02 0.13 0.12 -1 -1 0.02 0.0517727 0.0472555 - k6_N10_mem32K_40nm.xml diffeq1.v common 10.12 vpr 70.60 MiB 0.03 9856 -1 -1 15 0.44 -1 -1 38380 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72292 162 96 999 932 1 661 323 16 16 256 mult_36 auto 31.3 MiB 0.38 5531 95525 26953 60139 8433 70.6 MiB 0.91 0.01 21.9361 -1891.35 -21.9361 21.9361 0.47 0.00396915 0.00366377 0.403824 0.374905 -1 -1 -1 -1 44 11294 43 1.21132e+07 5.21364e+06 665287. 2598.78 5.71 1.78116 1.66467 20656 131250 -1 8771 24 4066 8799 1047369 299882 22.5944 22.5944 -1935.68 -22.5944 0 0 864808. 3378.16 0.04 0.50 0.16 -1 -1 0.04 0.234899 0.221057 - k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB 0.01 6912 -1 -1 1 0.02 -1 -1 32916 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0231e-05 6.013e-06 7.2755e-05 4.8573e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00153872 0.00147005 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109157 0.00106485 - k6_N10_mem32K_40nm.xml single_ff.v common 0.49 vpr 65.16 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33280 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 5 1 3 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5008e-05 1.0331e-05 0.000105161 7.8059e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0016194 0.0015365 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00112886 0.00109032 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.85 vpr 67.48 MiB 0.06 9856 -1 -1 3 0.36 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69100 99 130 363 493 1 255 305 19 19 361 o auto 27.9 MiB 0.10 1043 75203 18688 40447 16068 67.5 MiB 0.27 0.00 2.5827 -243.865 -2.5827 2.5827 1.92 0.000939884 0.00084584 0.0725048 0.0652395 -1 -1 -1 -1 36 1432 20 1.79173e+07 4.59005e+06 833707. 2309.44 1.36 0.302543 0.27272 24998 161561 -1 1342 23 802 1298 88966 26229 2.93129 2.93129 -249.701 -2.93129 0 0 1.02328e+06 2834.56 0.07 0.10 0.15 -1 -1 0.07 0.0554021 0.0511266 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 12.40 vpr 79.29 MiB 0.04 9856 -1 -1 15 0.45 -1 -1 38032 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81188 162 96 999 932 1 661 323 24 24 576 i auto 31.0 MiB 0.28 7114 95525 25526 57948 12051 79.3 MiB 0.94 0.01 21.4854 -1914.4 -21.4854 21.4854 3.35 0.00392701 0.00363416 0.415599 0.386608 -1 -1 -1 -1 32 12804 30 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 3.94 1.18592 1.11276 39974 242477 -1 10817 26 4455 9936 1378660 349639 22.5193 22.5193 -2054.22 -22.5193 0 0 1.54255e+06 2678.04 0.12 0.65 0.37 -1 -1 0.12 0.246186 0.231211 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.47 vpr 65.28 MiB 0.02 6784 -1 -1 1 0.02 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66848 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1306e-05 5.604e-06 7.2139e-05 4.6493e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00155951 0.00148904 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.0014785 0.00144447 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.49 vpr 65.16 MiB 0.02 7040 -1 -1 1 0.02 -1 -1 33288 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 4 4 16 i auto 26.9 MiB 0.00 7 9 0 2 7 65.2 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.6222e-05 1.0832e-05 0.00010458 7.8535e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00166008 0.00157112 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00159511 0.00154443 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.73 odin 99.75 MiB 2.11 102144 -1 -1 3 0.19 -1 -1 34096 -1 -1 75 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67636 99 130 363 493 1 253 305 13 13 169 clb auto 26.3 MiB 0.04 2273 844 74177 21541 39695 12941 66.1 MiB 0.12 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.10 0.000545037 0.000509709 0.0421815 0.0394416 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.22 0.112186 0.103342 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0263727 0.0242585 +k6_N10_mem32K_40nm.xml diffeq1.v common 5.78 odin 87.00 MiB 1.78 89088 -1 -1 15 0.28 -1 -1 34656 -1 -1 62 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71816 162 96 999 932 1 663 325 16 16 256 mult_36 auto 30.1 MiB 0.14 9594 5574 90802 23938 58756 8108 70.1 MiB 0.35 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.17 0.0016689 0.00156792 0.146815 0.137632 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.71 0.542302 0.504589 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.24 0.06 -1 -1 0.02 0.0989663 0.0931558 +k6_N10_mem32K_40nm.xml single_wire.v common 1.85 vpr 63.42 MiB 1.35 62208 -1 -1 1 0.02 -1 -1 29676 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64940 1 1 1 2 0 1 2 3 3 9 -1 auto 25.2 MiB 0.00 2 2 3 0 3 0 63.4 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.563e-06 3.5e-06 5.6873e-05 3.8119e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000892945 0.000838657 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000818035 0.000790317 +k6_N10_mem32K_40nm.xml single_ff.v common 1.65 vpr 63.43 MiB 1.13 62208 -1 -1 1 0.02 -1 -1 29980 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64952 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 6 9 5 1 3 63.4 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.457e-06 6.162e-06 7.5674e-05 5.5802e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000948394 0.000881804 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000868136 0.00083058 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 4.88 odin 100.12 MiB 2.18 102528 -1 -1 3 0.21 -1 -1 34188 -1 -1 75 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67452 99 130 363 493 1 253 305 19 19 361 o auto 26.1 MiB 0.04 3198 975 75203 18286 41793 15124 65.9 MiB 0.12 0.00 3.0814 2.23502 -240.202 -2.23502 2.23502 0.64 0.00056767 0.000530953 0.0438763 0.0412509 -1 -1 -1 -1 36 1305 22 1.79173e+07 4.59005e+06 833707. 2309.44 0.55 0.162802 0.14941 24998 161561 -1 1270 26 731 1078 66382 19258 2.55328 2.55328 -255.132 -2.55328 0 0 1.02328e+06 2834.56 0.03 0.05 0.08 -1 -1 0.03 0.0294887 0.0270957 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 7.03 odin 86.62 MiB 1.78 88704 -1 -1 15 0.28 -1 -1 34628 -1 -1 62 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78268 162 96 999 932 1 663 325 24 24 576 i auto 29.9 MiB 0.14 13908 6960 97504 27766 60997 8741 76.4 MiB 0.37 0.01 27.051 21.3253 -1909.99 -21.3253 21.3253 1.08 0.00180313 0.00169217 0.157695 0.147632 -1 -1 -1 -1 44 10768 25 3.08128e+07 5.32143e+06 1.60659e+06 2789.21 1.63 0.547726 0.510008 44574 325925 -1 10016 19 3329 7120 1011052 264242 21.9724 21.9724 -1931.12 -21.9724 0 0 2.07854e+06 3608.58 0.06 0.19 0.17 -1 -1 0.06 0.0798925 0.0754695 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 1.63 vpr 63.87 MiB 1.12 62208 -1 -1 1 0.02 -1 -1 29672 -1 -1 0 1 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65400 1 1 1 2 0 1 2 4 4 16 i auto 25.6 MiB 0.00 3 3 3 0 0 3 63.9 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.534e-06 3.573e-06 5.5302e-05 3.705e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.000882082 0.000817487 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.000822123 0.000791877 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 1.69 vpr 63.77 MiB 1.15 62208 -1 -1 1 0.02 -1 -1 29988 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65296 2 1 3 4 1 3 4 4 4 16 i auto 24.9 MiB 0.00 7 7 9 0 2 7 63.8 MiB 0.00 0.00 0.55247 0.55247 -0.955943 -0.55247 0.55247 0.00 9.557e-06 6.18e-06 8.3767e-05 6.4375e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.00 0.00096046 0.000887599 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.000877327 0.000830252 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt index a4f4578b4e4..c0c4d5fb80e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.22 vpr 66.21 MiB 0.06 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67796 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 485 3687 781 2795 111 66.2 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 734 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.65 0.239065 0.204044 2616 8308 -1 583 23 761 1801 50764 16568 2.52485 2.36559 -186.102 -2.52485 0 0 59124.6 1206.62 0.00 0.07 0.01 -1 -1 0.00 0.0486043 0.0430292 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 4.05 odin 167.25 MiB 2.81 171264 -1 -1 4 0.12 -1 -1 33076 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 466 3421 681 2621 119 65.7 MiB 0.00 0.00 -1 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 697 29 1.07788e+06 1.07788e+06 45686.6 932.380 0.15 0.0585359 0.0490389 2616 8308 -1 557 36 1075 2921 72281 22541 2.63547 2.45943 -188.872 -2.63547 0 0 59124.6 1206.62 0.00 0.05 0.00 -1 -1 0.00 0.028993 0.0249322 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt index d3b62c629ad..7b3feedaa81 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 14.36 vpr 58.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60212 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.8 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.10 4.6187e-05 3.8396e-05 0.000395937 0.000323618 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00202221 0.00179313 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00173217 0.0016394 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 16.94 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.28 4.6086e-05 3.7994e-05 0.000373556 0.000302701 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00235088 0.00212378 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00221042 0.00197359 - sub_tiles.xml sub_tiles.blif common_--check_route_off 16.20 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60476 6 7 19 26 0 19 26 3 3 9 -1 auto 20.7 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 14.72 4.2295e-05 3.5105e-05 0.000363474 0.000296118 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00229484 0.00207762 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00174454 0.00165562 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common_--check_route_full 4.36 vpr 57.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58904 6 7 19 26 0 19 26 3 3 9 -1 auto 18.7 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.68 2.1665e-05 1.7518e-05 0.000208626 0.000167637 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00147674 0.00134179 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00098867 0.000928688 +sub_tiles.xml sub_tiles.blif common_--check_route_quick 4.36 vpr 57.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59084 6 7 19 26 0 19 26 3 3 9 -1 auto 18.9 MiB 0.00 51 51 216 43 63 110 57.7 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.66 2.2092e-05 1.7777e-05 0.00021225 0.000170395 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00147126 0.00133195 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00102901 0.000969282 +sub_tiles.xml sub_tiles.blif common_--check_route_off 4.38 vpr 57.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58908 6 7 19 26 0 19 26 3 3 9 -1 auto 18.9 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.68 2.1964e-05 1.7853e-05 0.000215424 0.000174304 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00138082 0.00125409 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00102124 0.000958615 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index 7b6b29fbf31..a0b1d2547f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.50 vpr 66.18 MiB 0.01 6912 -1 -1 1 0.03 -1 -1 33524 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67768 9 8 71 66 1 35 20 5 5 25 clb auto 27.2 MiB 0.61 102 641 211 420 10 66.2 MiB 0.01 0.00 2.52843 -27.3721 -2.52843 2.52843 0.02 0.000162932 0.000142933 0.00487777 0.00439017 -1 -1 -1 -1 32 152 12 151211 75605.7 43252.0 1730.08 0.15 0.05219 0.0443549 2004 6761 -1 170 13 131 173 5906 3259 2.68643 2.68643 -34.5837 -2.68643 0 0 52324.5 2092.98 0.00 0.01 0.01 -1 -1 0.00 0.00766663 0.00704697 14 17 16 6 0 0 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.42 vpr 67.07 MiB 0.01 6912 -1 -1 1 0.04 -1 -1 33628 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 19 18 299 240 1 146 45 6 6 36 clb auto 27.6 MiB 4.94 477 2365 468 1860 37 67.1 MiB 0.04 0.00 4.92757 -99.6523 -4.92757 4.92757 0.05 0.000316619 0.0002807 0.0196432 0.0179661 -1 -1 -1 -1 54 1052 25 403230 201615 113905. 3164.04 0.53 0.17427 0.152991 4050 20995 -1 792 24 850 1349 48852 19559 4.89358 4.89358 -108.576 -4.89358 0 0 146644. 4073.44 0.00 0.05 0.03 -1 -1 0.00 0.0285954 0.0259387 62 82 85 13 0 0 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 2.21 vpr 64.45 MiB 1.16 63360 -1 -1 1 0.02 -1 -1 30140 -1 -1 3 9 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 9 8 71 66 1 36 20 5 5 25 clb auto 25.1 MiB 0.31 137 104 641 234 396 11 64.4 MiB 0.01 0.00 2.52843 2.52843 -27.3563 -2.52843 2.52843 0.01 8.3886e-05 7.5678e-05 0.00287988 0.00265606 -1 -1 -1 -1 36 198 14 151211 75605.7 46719.2 1868.77 0.06 0.0208895 0.0176785 2052 7582 -1 134 10 105 135 3075 1640 2.65565 2.65565 -30.2407 -2.65565 0 0 57775.2 2311.01 0.00 0.01 0.00 -1 -1 0.00 0.00421623 0.00386847 14 17 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.88 vpr 65.83 MiB 1.29 66048 -1 -1 1 0.03 -1 -1 30508 -1 -1 8 19 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67412 19 18 299 240 1 146 45 6 6 36 clb auto 26.5 MiB 2.57 653 478 2685 571 2068 46 65.8 MiB 0.02 0.00 4.89372 4.92757 -99.729 -4.92757 4.92757 0.02 0.000299081 0.00027449 0.0126207 0.0117249 -1 -1 -1 -1 54 1009 23 403230 201615 113905. 3164.04 0.18 0.0769279 0.0673934 4050 20995 -1 757 20 679 1069 35690 14737 4.92407 4.92407 -104.302 -4.92407 0 0 146644. 4073.44 0.00 0.03 0.01 -1 -1 0.00 0.0173043 0.0158511 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt index 82e16e68c58..545c792005d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.35 vpr 59.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61244 1 4 28 32 2 10 9 4 4 16 clb auto 21.2 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9876e-05 6.8917e-05 0.000564474 0.000511898 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00933145 0.00790294 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0020437 0.00190467 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.33 vpr 60.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61444 1 4 28 32 2 10 9 4 4 16 clb auto 21.5 MiB 0.01 21 27 10 10 7 60.0 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 9.3379e-05 8.2596e-05 0.000566541 0.000512464 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00867291 0.00731794 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00253268 0.00233063 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.35 vpr 59.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61264 1 4 28 32 2 10 9 4 4 16 clb auto 21.4 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.8562e-05 6.7163e-05 0.000561289 0.000507136 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00963983 0.0081025 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00296634 0.00273132 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.30 vpr 58.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59868 1 4 28 32 2 10 9 4 4 16 clb auto 20.0 MiB 0.01 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.1534e-05 3.5999e-05 0.000369868 0.000335443 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00499499 0.00420054 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0016791 0.00155334 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.31 vpr 58.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59872 1 4 28 32 2 10 9 4 4 16 clb auto 19.8 MiB 0.00 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.9315e-05 4.3528e-05 0.00035389 0.000323547 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0051196 0.00430647 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00175992 0.00162646 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.30 vpr 58.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59868 1 4 28 32 2 10 9 4 4 16 clb auto 20.0 MiB 0.00 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.6269e-05 3.5157e-05 0.000348083 0.000313527 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00483693 0.00405856 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0016602 0.0015331 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt index 17671e26cfa..6445c2b0e4d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.35 vpr 59.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61088 2 2 22 24 2 4 6 4 4 16 clb auto 21.2 MiB 0.01 8 15 5 7 3 59.7 MiB 0.00 0.00 1.297 0 0 1.297 0.01 6.7393e-05 5.6956e-05 0.000402551 0.000351966 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00291274 0.00268287 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00264613 0.00228889 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.29 vpr 58.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59568 2 2 22 24 2 4 6 4 4 16 clb auto 19.8 MiB 0.00 8 8 15 5 7 3 58.2 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.00 3.2501e-05 2.7243e-05 0.000238975 0.000209911 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.00 0.00178494 0.00164738 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00133399 0.0012414 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt index 55f3e1dd3ba..b7e6584d848 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt index c54c9279c53..cf139e11ffa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33484 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 3 5 1 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.4271e-05 9.019e-06 0.000105429 7.7044e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00167801 0.00157995 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33216 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 9 9 3 3 3 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.5585e-05 1.0104e-05 0.000105029 7.6023e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.00153942 0.00144868 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.33 abc 63.01 MiB 0.24 59520 -1 -1 2 1.56 -1 -1 64520 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63024 5 156 191 347 1 163 316 15 15 225 clb auto 22.0 MiB 0.04 29 82016 58904 3157 19955 61.5 MiB 0.15 0.00 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000408132 0.000370067 0.0341355 0.031078 -1 -1 -1 -1 -1 32 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0428942 0.0391583 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.51 abc 63.14 MiB 0.34 59776 -1 -1 2 1.51 -1 -1 64652 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63260 5 156 191 347 1 163 316 15 15 225 clb auto 22.2 MiB 0.02 41 76641 54775 3226 18640 61.8 MiB 0.14 0.00 1.49775 -14.6172 -1.49775 1.49775 0.00 0.000395712 0.000358237 0.0299271 0.0269791 -1 -1 -1 -1 -1 63 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0377601 0.0341837 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.33 vpr 65.29 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33412 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 2 1 3 4 1 3 4 3 3 9 -1 auto 26.8 MiB 0.00 6 9 3 5 1 65.3 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5615e-05 1.0606e-05 0.000109326 8.0241e-05 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00165784 0.00156601 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.25 vpr 65.38 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33208 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 2 1 3 4 1 3 4 3 3 9 -1 auto 27.1 MiB 0.00 9 9 3 3 3 65.4 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.6671e-05 1.1297e-05 0.000111494 8.1284e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00178932 0.0017001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.46 vpr 71.98 MiB 0.15 16896 -1 -1 2 0.16 -1 -1 37600 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73704 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.58 8394 210108 78030 120895 11183 72.0 MiB 1.33 0.02 3.90475 -4339.03 -3.90475 3.90475 0.00 0.00537924 0.00456001 0.565099 0.476317 -1 -1 -1 -1 -1 12247 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.38 0.731735 0.628685 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.57 vpr 72.21 MiB 0.16 17152 -1 -1 2 0.16 -1 -1 37596 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73948 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.52 9639 203757 70988 121974 10795 72.2 MiB 1.36 0.02 4.05379 -3834.49 -4.05379 4.05379 0.00 0.00624609 0.00547423 0.627089 0.535493 -1 -1 -1 -1 -1 13797 11 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.48 0.824983 0.713955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.40 vpr 58.26 MiB 0.08 45312 -1 -1 1 0.02 -1 -1 29944 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59656 2 1 3 4 1 3 4 3 3 9 -1 auto 19.5 MiB 0.00 6 6 9 3 5 1 58.3 MiB 0.00 0.00 0.55447 0.55447 -0.91031 -0.55447 0.55447 0.00 9.136e-06 5.869e-06 7.1791e-05 5.3179e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00118302 0.00110755 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.41 vpr 58.25 MiB 0.08 45312 -1 -1 1 0.02 -1 -1 29640 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59652 2 1 3 4 1 3 4 3 3 9 -1 auto 20.0 MiB 0.00 9 9 9 3 3 3 58.3 MiB 0.00 0.00 0.56425 0.48631 -0.91031 -0.48631 0.48631 0.00 9.58e-06 5.86e-06 7.4441e-05 5.4651e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.001162 0.00108609 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 10.50 odin 789.80 MiB 7.89 808752 -1 -1 2 0.86 -1 -1 50628 -1 -1 155 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62228 5 156 191 347 1 163 316 15 15 225 clb auto 21.0 MiB 0.02 118 29 82016 59012 3139 19865 60.8 MiB 0.07 0.00 1.99335 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000220093 0.000206488 0.0175726 0.0164762 -1 -1 -1 -1 -1 32 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0225735 0.0211146 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 10.56 odin 789.05 MiB 7.83 807988 -1 -1 2 0.87 -1 -1 50628 -1 -1 155 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62228 5 156 191 347 1 163 316 15 15 225 clb auto 21.0 MiB 0.02 126 33 76641 54911 3193 18537 60.8 MiB 0.06 0.00 1.66097 1.47673 -14.6018 -1.47673 1.47673 0.00 0.000216751 0.000203309 0.016441 0.0153792 -1 -1 -1 -1 -1 47 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0210131 0.0196249 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 1.51 vpr 63.88 MiB 1.14 62208 -1 -1 1 0.02 -1 -1 29976 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 2 1 3 4 1 3 4 3 3 9 -1 auto 25.3 MiB 0.00 6 6 9 3 5 1 63.9 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.181e-06 5.927e-06 7.6264e-05 5.5982e-05 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00095459 0.000884928 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 1.51 vpr 63.88 MiB 1.14 62208 -1 -1 1 0.02 -1 -1 30008 -1 -1 1 2 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 2 1 3 4 1 3 4 3 3 9 -1 auto 25.6 MiB 0.00 9 9 9 3 3 3 63.9 MiB 0.00 0.00 0.56425 0.48631 -0.90831 -0.48631 0.48631 0.00 1.0512e-05 6.419e-06 7.8418e-05 5.706e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.000974856 0.000905471 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 7.23 odin 619.65 MiB 5.01 634520 -1 -1 2 0.08 -1 -1 35196 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73164 311 156 972 1128 1 953 525 28 28 784 memory auto 32.0 MiB 0.26 18730 8256 201640 71067 119264 11309 71.4 MiB 0.55 0.01 4.8206 3.69209 -4283.73 -3.69209 3.69209 0.00 0.00248503 0.00221098 0.252544 0.224143 -1 -1 -1 -1 -1 12173 14 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.19 0.35082 0.314831 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 7.11 odin 620.36 MiB 4.85 635252 -1 -1 2 0.08 -1 -1 35200 -1 -1 43 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73164 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.26 19537 8661 201640 66024 123894 11722 71.4 MiB 0.54 0.01 4.71974 3.76482 -3710.64 -3.76482 3.76482 0.00 0.00245698 0.00217799 0.245651 0.216211 -1 -1 -1 -1 -1 12504 13 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.20 0.340896 0.304187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt index 270c7d97d80..a7e3857a45b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.68 vpr 66.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 8 4 25 28 5 19 19 6 6 36 clb auto 27.9 MiB 0.43 51 194 39 119 36 66.2 MiB 0.00 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 6.5511e-05 4.9348e-05 0.000956967 0.000802791 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.2 MiB 0.00 0.00312006 0.00280809 66.2 MiB -1 0.01 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.33 vpr 64.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 8 4 25 28 5 19 19 6 6 36 clb auto 26.0 MiB 0.16 73 51 194 39 119 36 64.7 MiB 0.00 0.00 1.51369 1.41795 -5.85435 -1.41795 0.545 0.00 3.3733e-05 2.5958e-05 0.000434238 0.000352095 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 673 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.00 -1 -1 64.7 MiB 0.00 0.0016542 0.00148021 64.7 MiB -1 0.00 +k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.04 vpr 18.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 18960 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt index a8229d3cc5f..fe67fdd70e7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.39 vpr 65.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 -1 2 2 4 0 2 4 4 4 16 clb auto 27.0 MiB 0.00 0 9 0 2 7 65.3 MiB 0.00 0.00 nan 0 0 nan 0.01 1.324e-05 7.342e-06 8.3458e-05 5.501e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00154065 0.00146112 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00148898 0.00145049 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.31 vpr 63.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64696 -1 2 2 4 0 2 4 4 4 16 clb auto 24.6 MiB 0.00 0 0 9 0 2 7 63.2 MiB 0.00 0.00 nan nan 0 0 nan 0.00 8.207e-06 4.305e-06 6.3919e-05 4.1976e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.000882294 0.00082251 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.000867933 0.000836225 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt index dedf8b436ab..2f44136a1bd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 22.04 vpr 87.12 MiB 0.37 32000 -1 -1 3 1.37 -1 -1 43832 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89216 214 305 2963 2869 1 1444 650 25 25 625 -1 25x25 45.9 MiB 3.49 12196 290492 92452 176193 21847 87.1 MiB 1.73 0.04 4.70145 -2687.49 -4.70145 4.70145 0.77 0.009062 0.00821446 0.664489 0.598586 -1 -1 -1 -1 50 24072 42 3.19446e+07 9.79696e+06 2.03477e+06 3255.63 9.38 3.04543 2.74886 65619 409230 -1 20090 15 5518 12429 1427524 369655 4.84691 4.84691 -2936.69 -4.84691 0 0 2.61863e+06 4189.80 0.13 0.72 0.40 -1 -1 0.13 0.405468 0.382168 - column_io.xml raygentop.v common 30.34 vpr 87.28 MiB 0.43 32000 -1 -1 3 1.83 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89376 214 305 2963 2869 1 1444 650 25 25 625 io auto 46.2 MiB 3.96 11325 239840 77339 132443 30058 87.3 MiB 2.09 0.03 4.40936 -2625.55 -4.40936 4.40936 1.20 0.0090281 0.0081843 0.836879 0.749323 -1 -1 -1 -1 48 24462 25 2.82259e+07 9.79696e+06 1.82181e+06 2914.90 14.53 3.9566 3.54503 57888 355703 -1 20518 17 5996 13599 1716937 426068 4.7409 4.7409 -2939.5 -4.7409 0 0 2.33544e+06 3736.71 0.17 0.92 0.52 -1 -1 0.17 0.442866 0.410518 - multiwidth_blocks.xml raygentop.v common 23.34 vpr 87.11 MiB 0.46 32000 -1 -1 3 1.66 -1 -1 43932 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89196 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.70 10825 234212 78128 135288 20796 87.1 MiB 2.20 0.03 4.45499 -2656.92 -4.45499 4.45499 0.58 0.00914429 0.00826611 0.84541 0.761865 -1 -1 -1 -1 60 22314 37 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 8.15 3.5171 3.1499 34801 210837 -1 18718 16 6372 15066 2125910 636768 4.83864 4.83864 -2933.88 -4.83864 0 0 1.43369e+06 3971.44 0.09 1.02 0.34 -1 -1 0.09 0.423489 0.392785 - non_column.xml raygentop.v common 50.57 vpr 101.43 MiB 0.57 32128 -1 -1 3 1.64 -1 -1 43688 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103864 214 305 2963 2869 1 1444 650 33 33 1089 io auto 47.6 MiB 3.38 13852 267980 91761 149229 26990 98.5 MiB 2.25 0.03 4.81737 -2748.68 -4.81737 4.81737 2.25 0.00871345 0.00790536 0.883704 0.789723 -1 -1 -1 -1 46 27889 41 5.44432e+07 9.79696e+06 2.87196e+06 2637.24 31.91 4.82411 4.34906 94862 558952 -1 23226 19 7179 17098 2136481 565014 5.00295 5.00295 -3094.61 -5.00295 0 0 3.68462e+06 3383.49 0.29 1.11 0.95 -1 -1 0.29 0.492691 0.457205 - non_column_tall_aspect_ratio.xml raygentop.v common 41.13 vpr 107.46 MiB 0.65 32128 -1 -1 3 2.07 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110040 214 305 2963 2869 1 1444 650 23 46 1058 io auto 47.5 MiB 4.75 12924 225770 77986 115287 32497 98.0 MiB 1.99 0.02 4.68258 -2746.61 -4.68258 4.68258 2.17 0.00617553 0.00548634 0.751525 0.668955 -1 -1 -1 -1 50 24702 35 5.05849e+07 9.79696e+06 3.07243e+06 2904.00 20.48 4.80846 4.28853 95149 595581 -1 21346 17 5714 12751 1591343 424414 4.99583 4.99583 -3024.29 -4.99583 0 0 3.91054e+06 3696.17 0.39 1.00 1.06 -1 -1 0.39 0.462953 0.424532 - non_column_wide_aspect_ratio.xml raygentop.v common 40.58 vpr 101.39 MiB 0.68 32000 -1 -1 3 1.80 -1 -1 43696 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103820 214 305 2963 2869 1 1444 650 43 22 946 io auto 47.4 MiB 4.77 13982 276422 90498 164087 21837 95.1 MiB 2.48 0.03 4.68152 -2857.71 -4.68152 4.68152 2.06 0.0081203 0.0072676 0.94579 0.847056 -1 -1 -1 -1 50 26296 34 4.55909e+07 9.79696e+06 2.70028e+06 2854.41 19.21 5.11489 4.60481 84704 520009 -1 22872 18 6244 14195 1614167 427447 4.86473 4.86473 -3155.96 -4.86473 0 0 3.44953e+06 3646.44 0.30 1.16 1.00 -1 -1 0.30 0.501153 0.460019 - custom_sbloc.xml raygentop.v common 25.95 vpr 86.98 MiB 0.39 32000 -1 -1 3 1.58 -1 -1 43804 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89072 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.8 MiB 4.86 11696 245468 82823 140883 21762 87.0 MiB 2.50 0.04 4.53013 -2681.39 -4.53013 4.53013 0.61 0.00909806 0.00824441 0.931511 0.836258 -1 -1 -1 -1 62 22622 49 1.65001e+07 9.79696e+06 1.15634e+06 3203.15 10.71 4.10582 3.71488 35161 219597 -1 19429 17 6137 14618 1898349 506769 4.83748 4.83748 -2977.52 -4.83748 0 0 1.43990e+06 3988.64 0.05 0.92 0.41 -1 -1 0.05 0.399467 0.368878 - multiple_io_types.xml raygentop.v common 148.40 vpr 474.05 MiB 0.38 31872 -1 -1 3 1.46 -1 -1 43604 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 485424 214 305 2963 2869 1 1444 650 67 67 4489 io_left auto 46.2 MiB 5.36 26050 90698 4115 22648 63935 474.0 MiB 0.95 0.03 4.73667 -3563.79 -4.73667 4.73667 26.71 0.00792183 0.00702959 0.36772 0.321766 -1 -1 -1 -1 52 41451 45 2.48753e+08 9.79696e+06 1.27607e+07 2842.65 95.91 4.21007 3.80326 406473 2447650 -1 35770 21 7664 17455 3505363 891802 5.27395 5.27395 -3927.86 -5.27395 0 0 1.67786e+07 3737.72 0.99 1.06 2.69 -1 -1 0.99 0.318577 0.29589 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_grid.xml raygentop.v common 21.99 odin 1.52 GiB 10.24 1591816 -1 -1 3 0.83 -1 -1 40304 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88816 214 305 2963 2869 1 1441 650 25 25 625 -1 25x25 46.7 MiB 2.18 25402 12254 282050 88602 172367 21081 86.7 MiB 0.99 0.01 5.35403 4.41932 -2744.04 -4.41932 4.41932 0.47 0.00359037 0.00330877 0.395607 0.36374 -1 -1 -1 -1 48 24508 46 3.19446e+07 9.79696e+06 1.97188e+06 3155.02 3.94 1.43281 1.32186 64995 397836 -1 20934 15 5849 13951 1555077 389423 4.73647 4.73647 -2992.8 -4.73647 0 0 2.52596e+06 4041.53 0.08 0.37 0.21 -1 -1 0.08 0.18958 0.180028 +column_io.xml raygentop.v common 22.07 odin 1.52 GiB 10.19 1592260 -1 -1 3 0.83 -1 -1 39704 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88780 214 305 2963 2869 1 1441 650 25 25 625 io auto 46.3 MiB 2.17 25737 12044 245468 82104 140823 22541 86.7 MiB 0.89 0.01 5.96169 4.61982 -2725.2 -4.61982 4.61982 0.43 0.00356427 0.0032823 0.345995 0.317544 -1 -1 -1 -1 50 25560 24 2.82259e+07 9.79696e+06 1.88190e+06 3011.03 4.29 1.24128 1.1434 58512 365993 -1 21648 16 6081 14502 1687459 402383 4.72983 4.72983 -3044.61 -4.72983 0 0 2.41964e+06 3871.43 0.07 0.37 0.20 -1 -1 0.07 0.190288 0.180368 +multiwidth_blocks.xml raygentop.v common 21.54 odin 1.54 GiB 11.06 1614276 -1 -1 3 0.82 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88684 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.24 24028 11655 245468 82518 140645 22305 86.6 MiB 0.92 0.01 5.44642 4.52802 -2634.46 -4.52802 4.52802 0.21 0.00362024 0.00333019 0.352063 0.323303 -1 -1 -1 -1 60 24300 34 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 3.19 1.15359 1.06265 34801 210837 -1 20057 19 6400 15852 2295662 663397 4.80907 4.80907 -2946.21 -4.80907 0 0 1.43369e+06 3971.44 0.04 0.46 0.12 -1 -1 0.04 0.210626 0.199034 +non_column.xml raygentop.v common 47.75 odin 1.93 GiB 34.32 2023384 -1 -1 3 0.84 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 102400 214 305 2963 2869 1 1441 650 33 33 1089 io auto 47.7 MiB 2.23 35936 13660 262352 89101 152531 20720 98.5 MiB 0.94 0.01 6.8947 4.81737 -2806.8 -4.81737 4.81737 0.81 0.00362339 0.00334265 0.375896 0.345261 -1 -1 -1 -1 44 28243 27 5.44432e+07 9.79696e+06 2.74036e+06 2516.40 4.20 1.29667 1.19485 93774 543488 -1 22727 18 6328 15147 1605451 431979 4.86083 4.86083 -3079.84 -4.86083 0 0 3.56397e+06 3272.70 0.12 0.42 0.35 -1 -1 0.12 0.213772 0.202022 +non_column_tall_aspect_ratio.xml raygentop.v common 51.79 odin 1.93 GiB 39.18 2023256 -1 -1 3 0.83 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 102100 214 305 2963 2869 1 1441 650 23 46 1058 io auto 48.3 MiB 2.18 34433 12310 253910 86017 138818 29075 97.8 MiB 0.90 0.01 6.20818 4.74318 -2736.15 -4.74318 4.74318 0.80 0.0037281 0.0034064 0.359725 0.330304 -1 -1 -1 -1 52 22487 30 5.05849e+07 9.79696e+06 3.17293e+06 2998.99 3.53 1.28793 1.18725 97261 632982 -1 20510 16 5114 12053 1254371 346946 4.98587 4.98587 -2932.2 -4.98587 0 0 4.15960e+06 3931.57 0.12 0.33 0.42 -1 -1 0.12 0.187592 0.178023 +non_column_wide_aspect_ratio.xml raygentop.v common 50.76 odin 1.93 GiB 38.21 2023656 -1 -1 3 0.84 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 98352 214 305 2963 2869 1 1441 650 43 22 946 io auto 48.4 MiB 2.19 32195 14077 256724 83624 150449 22651 94.9 MiB 0.92 0.01 6.20333 4.54267 -2819.04 -4.54267 4.54267 0.70 0.00362855 0.00334198 0.36694 0.336882 -1 -1 -1 -1 42 27740 26 4.55909e+07 9.79696e+06 2.29725e+06 2428.38 3.62 1.2805 1.17964 79978 445530 -1 23661 21 6769 17034 1969793 532017 5.2623 5.2623 -3159.48 -5.2623 0 0 2.89121e+06 3056.25 0.09 0.47 0.28 -1 -1 0.09 0.224224 0.210925 +custom_sbloc.xml raygentop.v common 20.32 odin 1.51 GiB 10.16 1588048 -1 -1 3 0.82 -1 -1 39876 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88684 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.17 24028 12399 225770 74858 132033 18879 86.6 MiB 0.84 0.01 5.49355 4.39465 -2699.44 -4.39465 4.39465 0.21 0.00358021 0.0033004 0.322189 0.295867 -1 -1 -1 -1 60 25212 46 1.65001e+07 9.79696e+06 1.11685e+06 3093.75 3.18 1.03862 0.957059 34801 214773 -1 20923 16 6158 14594 1766703 471535 4.72432 4.72432 -3000.62 -4.72432 0 0 1.41014e+06 3906.19 0.03 0.37 0.13 -1 -1 0.03 0.187347 0.177768 +multiple_io_types.xml raygentop.v common 83.03 odin 1.54 GiB 10.26 1617740 -1 -1 3 0.83 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 484432 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 47.0 MiB 2.58 60956 25475 99140 5163 24781 69196 473.1 MiB 0.42 0.01 9.23589 4.60777 -3590.83 -4.60777 4.60777 11.18 0.00363304 0.00335274 0.163246 0.151042 -1 -1 -1 -1 38 47769 50 2.48753e+08 9.79696e+06 9.69761e+06 2160.30 49.39 1.31777 1.21279 366081 1845534 -1 38574 21 9565 21545 4981287 1328871 5.11017 5.11017 -4030.7 -5.11017 0 0 1.23326e+07 2747.29 0.44 0.96 1.12 -1 -1 0.44 0.226022 0.212296 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt index 032d95a320e..9ace93e2d4a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.66 MiB 0.06 9856 -1 -1 3 0.38 -1 -1 39496 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69284 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.23 0.00 2.23767 -220.613 -2.23767 2.23767 0.25 0.00122229 0.00116469 0.0742124 0.0677305 -1 -1 -1 -1 38 1639 12 5.66058e+06 4.21279e+06 328943. 2284.32 0.72 0.298961 0.271262 12522 66188 -1 1359 8 559 726 39339 13482 2.60043 2.60043 -237.265 -2.60043 0 0 418267. 2904.63 0.03 0.05 0.11 -1 -1 0.03 0.0322868 0.0303399 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.83 odin 100.50 MiB 2.19 102912 -1 -1 3 0.20 -1 -1 34096 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67960 99 130 363 493 1 252 298 12 12 144 clb auto 27.1 MiB 0.06 2018 885 69948 23010 34855 12083 66.4 MiB 0.11 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.09 0.000518599 0.000485055 0.0395951 0.0370221 -1 -1 -1 -1 40 1651 16 5.66058e+06 4.21279e+06 343462. 2385.15 0.31 0.146639 0.134351 12666 68385 -1 1603 9 533 666 46991 15253 2.5852 2.5852 -243.226 -2.5852 0 0 431791. 2998.55 0.01 0.02 0.04 -1 -1 0.01 0.015929 0.0149791 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt index a65248b7f30..0b0f4fd6adf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.43 vpr 64.82 MiB 0.05 9728 -1 -1 4 0.35 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66380 99 130 378 508 1 307 305 15 15 225 memory auto 25.3 MiB 0.06 1083 69047 24301 32567 12179 64.8 MiB 0.22 0.01 1.63577 -172.755 -1.63577 1.63577 0.00 0.00106212 0.000958102 0.0684136 0.0626923 -1 -1 -1 -1 1479 6.03673 767 3.13061 797 1865 235419 59319 1.16234e+06 375248 2.18283e+06 9701.45 16 48952 428016 -1 1.89463 1.89463 -188.601 -1.89463 -0.194976 -0.108352 0.68 -1 -1 64.8 MiB 0.11 0.107667 0.0986163 64.8 MiB -1 0.37 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 3.02 odin 94.88 MiB 1.73 97152 -1 -1 4 0.19 -1 -1 34104 -1 -1 80 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65108 99 130 378 508 1 307 310 15 15 225 memory auto 24.1 MiB 0.02 2811 1131 73670 26591 35126 11953 63.6 MiB 0.13 0.00 1.90937 1.69007 -171.787 -1.69007 1.69007 0.00 0.000578502 0.000540501 0.0429258 0.0401158 -1 -1 -1 -1 1607 6.55918 824 3.36327 788 1831 251903 61748 1.16234e+06 394748 2.18283e+06 9701.45 13 48952 428016 -1 1.87081 1.87081 -179.525 -1.87081 0 0 0.25 -1 -1 63.6 MiB 0.05 0.0608034 0.0566295 63.6 MiB -1 0.13 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt index c044fb36631..3a232fd7306 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 16.11 vpr 77.95 MiB 0.11 17024 -1 -1 2 0.10 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79820 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.7 MiB 0.63 9390 201609 69489 120331 11789 76.8 MiB 1.40 0.02 4.09817 -3462.19 -4.09817 4.09817 1.75 0.00638402 0.00561878 0.639416 0.550497 -1 -1 -1 -1 36 15662 18 4.25198e+07 9.89071e+06 1.97160e+06 2514.80 6.39 2.29245 2.04057 76483 392267 -1 14444 15 3124 3650 1031496 356426 4.24327 4.24327 -4339.34 -4.24327 -405.202 -1.29702 2.42825e+06 3097.26 0.20 1.56 0.59 -1 -1 0.20 0.278119 0.255639 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.94 vpr 83.35 MiB 0.18 17024 -1 -1 2 0.12 -1 -1 37644 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 85352 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.95 9390 201609 69489 120331 11789 83.4 MiB 0.81 0.01 4.09817 -3462.19 -4.09817 4.09817 1.06 0.00320533 0.00273182 0.351431 0.298654 -1 -1 -1 -1 36 15777 15 4.25198e+07 9.89071e+06 2.00618e+06 2558.90 4.74 1.57738 1.39763 76483 403003 -1 14373 10 2886 3379 762706 219312 4.3954 4.3954 -4595.94 -4.3954 -153.524 -1.32288 2.47848e+06 3161.33 0.22 1.20 0.50 -1 -1 0.22 0.199455 0.182428 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 20.64 vpr 78.23 MiB 0.14 17152 -1 -1 2 0.19 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80112 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.82 8956 201609 71778 118284 11547 78.2 MiB 1.41 0.02 3.73942 -3418.22 -3.73942 3.73942 1.71 0.00607733 0.00531502 0.647808 0.554869 -1 -1 -1 -1 36 16279 32 4.25198e+07 9.89071e+06 1.96702e+06 2508.96 9.86 2.33237 2.04039 76483 392433 -1 15198 14 2704 3167 1739681 1219090 5.58949 5.58949 -4496.49 -5.58949 -1697.62 -3.42836 2.42368e+06 3091.42 0.20 2.25 0.55 -1 -1 0.20 0.242641 0.222883 15 950 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 11.69 odin 621.34 MiB 5.06 636252 -1 -1 2 0.09 -1 -1 33636 -1 -1 31 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78136 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.6 MiB 0.45 18226 8928 193401 64117 117643 11641 75.2 MiB 0.54 0.01 4.81013 3.67388 -3454.23 -3.67388 3.67388 0.61 0.00248748 0.00222031 0.252503 0.224419 -1 -1 -1 -1 40 14778 13 4.25198e+07 9.89071e+06 2.15543e+06 2749.27 2.14 0.803025 0.722118 78831 435646 -1 13800 11 2663 3052 814928 278609 4.53842 4.53842 -4454.28 -4.53842 -315.655 -1.23838 2.69266e+06 3434.52 0.09 0.53 0.23 -1 -1 0.09 0.0944896 0.0883248 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 11.70 odin 620.13 MiB 5.29 635016 -1 -1 2 0.09 -1 -1 33880 -1 -1 31 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 84032 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.6 MiB 0.45 18226 8928 193401 64117 117643 11641 82.1 MiB 0.54 0.01 4.81013 3.67388 -3454.23 -3.67388 3.67388 0.63 0.00245028 0.00217565 0.247052 0.218738 -1 -1 -1 -1 40 14952 13 4.25198e+07 9.89071e+06 2.19000e+06 2793.37 1.99 0.790372 0.708952 78831 446382 -1 13786 11 2650 3108 720747 217033 4.26762 4.26762 -4440.59 -4.26762 -135.258 -1.2599 2.74289e+06 3498.59 0.09 0.50 0.23 -1 -1 0.09 0.089366 0.0832744 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.45 odin 621.68 MiB 4.90 636596 -1 -1 2 0.09 -1 -1 33592 -1 -1 31 311 15 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78660 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.6 MiB 0.45 18226 9203 197505 67339 118442 11724 75.7 MiB 0.57 0.01 4.81013 3.956 -3512.79 -3.956 3.956 0.61 0.00267688 0.0023959 0.268374 0.238465 -1 -1 -1 -1 36 16669 23 4.25198e+07 9.89071e+06 1.96702e+06 2508.96 2.91 0.894838 0.805745 76483 392433 -1 15397 11 2678 3089 1644949 1134599 5.57406 5.57406 -4431.03 -5.57406 -1496.8 -3.14941 2.42368e+06 3091.42 0.08 0.80 0.20 -1 -1 0.08 0.0890233 0.0831689 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt index 3e3e8b64dd5..1c24f6d46d7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.94 vpr 71.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73360 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.5 MiB 0.26 10472 141533 36950 100839 3744 71.6 MiB 1.41 0.02 7.46482 -1369.01 -7.46482 7.46482 0.60 0.00534435 0.00471558 0.398834 0.330633 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.25 2.1497 1.834 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.76 0.21 -1 -1 0.04 0.209487 0.18755 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 4.75 vpr 70.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72680 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.6 MiB 0.17 24088 10407 135291 36283 95683 3325 71.0 MiB 0.54 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.20 0.00206891 0.00176944 0.139634 0.121098 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.35 0.423683 0.369434 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.31 0.07 -1 -1 0.02 0.0912069 0.0826102 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt index 57a8e16dad9..d1aa0e8c66f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 26.42 vpr 86.55 MiB 0.39 29568 -1 -1 4 2.92 -1 -1 43300 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88632 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.3 MiB 1.96 10985 240245 81936 130873 27436 86.6 MiB 2.98 0.04 4.42447 -2617.73 -4.42447 4.42447 0.87 0.010731 0.00973575 1.17585 1.01795 -1 -1 -1 -1 78 21148 32 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 12.21 3.92596 3.45972 52874 439520 -1 19015 16 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.81 0.45 -1 -1 0.19 0.495649 0.459932 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 21.77 odin 1.01 GiB 10.88 1062996 -1 -1 4 1.59 -1 -1 40164 -1 -1 165 193 5 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88044 193 205 2863 2789 1 1378 568 20 20 400 memory auto 45.3 MiB 0.99 22943 10817 247423 86121 133897 27405 86.0 MiB 1.12 0.01 6.47551 5.02579 -2678.97 -5.02579 5.02579 0.30 0.0037987 0.00341071 0.425979 0.382513 -1 -1 -1 -1 76 21112 33 2.07112e+07 1.16325e+07 2.02110e+06 5052.76 3.90 1.38116 1.24918 52074 423490 -1 19105 16 5044 13854 1088699 242536 5.48145 5.48145 -2895.27 -5.48145 -14.3689 -0.360359 2.51807e+06 6295.18 0.07 0.33 0.25 -1 -1 0.07 0.209497 0.196991 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt index 7d3c0c996a1..9c6c4e1f901 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.83 vpr 67.63 MiB 0.09 9984 -1 -1 3 0.34 -1 -1 39772 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69252 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.20 804 66963 21682 33533 11748 67.6 MiB 0.34 0.01 2.23767 -220.613 -2.23767 2.23767 0.27 0.000902266 0.000807045 0.0650955 0.0583605 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 1.19 0.319458 0.291293 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.06 0.09 -1 -1 0.03 0.0273369 0.0256329 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.80 odin 100.12 MiB 2.12 102528 -1 -1 3 0.19 -1 -1 34340 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67576 99 130 363 493 1 252 298 12 12 144 clb auto 27.1 MiB 0.07 2018 885 69948 23010 34855 12083 66.0 MiB 0.12 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.09 0.000549765 0.000514583 0.0413233 0.0386326 -1 -1 -1 -1 40 1646 17 5.66058e+06 4.21279e+06 333335. 2314.82 0.32 0.152035 0.139133 12666 64609 -1 1625 10 525 650 46110 15051 2.57635 2.57635 -244.199 -2.57635 0 0 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0172408 0.0161803 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index ceb027e03e3..56c59c8279b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 198.12 vpr 257.14 MiB 2.00 126464 -1 -1 5 139.65 -1 -1 78708 -1 -1 1337 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 263312 157 197 21024 21221 1 6369 1691 39 39 1521 clb auto 124.7 MiB 6.38 48812 948271 327778 599083 21410 257.1 MiB 9.39 0.13 3.8487 -15314.7 -3.8487 3.8487 8.33 0.0426525 0.0388129 3.00817 2.44576 -1 -1 -1 -1 38 60857 30 2.4642e+07 2.4066e+07 4.29790e+06 2825.71 13.17 9.3436 7.78726 119030 883757 -1 57009 24 29792 62484 2448958 439074 3.78459 3.78459 -15886.2 -3.78459 0 0 5.41627e+06 3561.00 0.27 2.25 0.65 -1 -1 0.27 1.68943 1.4738 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 201.99 vpr 255.40 MiB 2.14 126336 -1 -1 5 142.90 -1 -1 78972 -1 -1 1356 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 261528 157 197 21024 21221 1 6467 1710 39 39 1521 clb auto 124.6 MiB 7.21 49809 962484 334554 607807 20123 255.4 MiB 9.87 0.12 3.26114 -15027.4 -3.26114 3.26114 7.20 0.0351221 0.0281327 3.06287 2.48936 -1 -1 -1 -1 38 63075 34 7.37824e+07 7.30817e+07 4.16760e+06 2740.04 13.41 9.93144 8.27431 119030 845795 -1 59104 24 31762 70331 2621462 488165 3.1068 3.1068 -15929.2 -3.1068 0 0 5.22668e+06 3436.35 0.24 2.20 0.62 -1 -1 0.24 1.62443 1.4202 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml stereovision0.v common 159.89 odin 1.78 GiB 65.32 1868440 -1 -1 5 58.75 -1 -1 75080 -1 -1 1333 157 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 258252 157 197 21024 21221 1 6351 1687 39 39 1521 clb auto 136.7 MiB 2.92 183607 48717 965335 340609 600791 23935 252.2 MiB 6.37 0.06 8.3236 3.67149 -15448.9 -3.67149 3.67149 3.29 0.0168149 0.0146145 1.94454 1.62852 -1 -1 -1 -1 38 62381 33 2.4642e+07 2.3994e+07 4.29790e+06 2825.71 11.96 6.69956 5.60674 119030 883757 -1 57672 22 29914 63381 2482926 444293 3.4728 3.4728 -15928.1 -3.4728 0 0 5.41627e+06 3561.00 0.18 1.64 0.43 -1 -1 0.18 1.19722 1.06601 +k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 158.67 odin 1.79 GiB 64.83 1877584 -1 -1 5 58.24 -1 -1 75848 -1 -1 1329 157 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 259152 157 197 21024 21221 1 6395 1683 39 39 1521 clb auto 137.0 MiB 2.93 182137 48305 952348 332116 600539 19693 253.1 MiB 6.32 0.07 7.71591 3.21097 -14756.9 -3.21097 3.21097 3.24 0.0192976 0.0166812 1.91255 1.59488 -1 -1 -1 -1 38 61719 36 7.37824e+07 7.16265e+07 4.16760e+06 2740.04 11.71 7.21472 6.04706 119030 845795 -1 58052 25 31719 70350 2555452 477654 3.64157 3.64157 -15795.2 -3.64157 0 0 5.22668e+06 3436.35 0.18 1.82 0.42 -1 -1 0.18 1.31991 1.15859 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index 53aa221bde0..fb1ca9776ae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.35 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 6.5921e-05 4.9487e-05 0.000173999 0.000134314 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00172845 0.00161091 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.0015722 0.00153245 - k6_frac_N10_40nm.xml conn_order.eblif common 0.43 vpr 60.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61580 2 1 4 5 1 3 4 3 3 9 -1 auto 21.9 MiB 0.01 6 9 4 1 4 60.1 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.01 1.6713e-05 1.1905e-05 0.000118437 9.2123e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00165899 0.00156225 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00153235 0.00149153 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.27 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 3 1 5 6 1 4 5 3 3 9 -1 auto 20.2 MiB 0.00 9 9 12 4 4 4 59.0 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.0813e-05 7.425e-06 8.2569e-05 6.2814e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.00 0.000987116 0.000914894 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000870274 0.000836286 +k6_frac_N10_40nm.xml conn_order.eblif common 0.28 vpr 58.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60368 2 1 4 5 1 3 4 3 3 9 -1 auto 20.4 MiB 0.00 6 6 9 4 1 4 59.0 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0172e-05 6.799e-06 8.1876e-05 6.3112e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00098864 0.000921289 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000863087 0.000831269 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt index c0c64f8d2c1..4ac9645c21c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.32 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.3959e-05 1.5869e-05 0.000131827 9.7152e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00165685 0.00154691 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00177312 0.00171917 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml eblif_write.eblif common 0.26 vpr 56.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58312 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 16 14 18 7 10 1 56.9 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3321e-05 8.124e-06 8.7295e-05 6.3966e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00108886 0.00100644 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000892955 0.000854475 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt index c750dd52020..1850eda3b9d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.53 vpr 66.67 MiB 0.08 10368 -1 -1 4 0.21 -1 -1 36920 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68272 11 30 262 292 2 99 60 7 7 49 clb auto 27.0 MiB 0.11 431 1932 256 1610 66 66.7 MiB 0.10 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000756181 0.000646522 0.0198618 0.0177275 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0693622 0.0613246 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.93 odin 167.25 MiB 2.90 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66524 11 30 262 292 2 99 61 7 7 49 clb auto 24.9 MiB 0.07 688 427 2461 355 2028 78 65.0 MiB 0.07 0.00 2.92195 2.72416 -177.287 -2.72416 2.43773 0.00 0.000398095 0.00034762 0.0110046 0.00970371 -1 -1 -1 -1 -1 457 20 1.07788e+06 1.07788e+06 90369.8 1844.28 0.03 0.0316159 0.0277496 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt index 41d36d5dda6..f229cdbb877 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.40 vpr 58.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60148 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.5 MiB 0.00 9 9 3 6 0 58.7 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 2.1313e-05 1.5936e-05 0.000108787 8.0593e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00168168 0.00158747 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00146867 0.00143048 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.27 vpr 56.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58320 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 18.6 MiB 0.00 11 9 9 3 6 0 57.0 MiB 0.00 0.00 3.98683 3.8649 -3.8649 -3.8649 nan 0.00 8.943e-06 5.558e-06 6.5235e-05 4.5246e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00118852 0.00111324 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000892854 0.000855363 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt index 41bceae31db..5f0f030f6ff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.46 vpr 66.34 MiB 0.09 10240 -1 -1 4 0.25 -1 -1 36836 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67932 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.10 417 1932 303 1579 50 66.3 MiB 0.03 0.00 2.45862 -181.765 -2.45862 2.33618 0.06 0.000452546 0.000389719 0.0170733 0.0149049 -1 -1 -1 -1 14 566 30 1.07788e+06 1.02399e+06 81563.3 1664.56 0.67 0.279658 0.24196 2472 22196 -1 446 21 890 1897 62387 19776 2.78119 2.51931 -191.416 -2.78119 0 0 98201.7 2004.12 0.00 0.07 0.02 -1 -1 0.00 0.0396875 0.0352228 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 3.79 odin 167.25 MiB 2.51 171264 -1 -1 4 0.12 -1 -1 33108 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67024 11 30 262 292 2 99 61 7 7 49 clb auto 25.5 MiB 0.04 688 429 2941 457 2408 76 65.5 MiB 0.02 0.00 2.93468 2.74942 -180.398 -2.74942 2.45106 0.02 0.000395628 0.000342485 0.0122261 0.0107509 -1 -1 -1 -1 16 538 33 1.07788e+06 1.07788e+06 88828.2 1812.82 0.14 0.0725413 0.0612719 2520 24504 -1 531 31 912 2238 78937 24519 2.94529 2.53849 -196.108 -2.94529 0 0 104221. 2126.97 0.00 0.04 0.01 -1 -1 0.00 0.0270076 0.0233037 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place index 9813ce389c5..84ede063b47 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place @@ -1,175 +1,181 @@ #block name x y subblk layer block number #---------- -- -- ------ ----- ------------ -o_1_ 4 3 2 0 #0 -o_2_ 1 1 2 0 #1 -o_0_ 1 4 4 0 #2 -n_n1827 2 2 3 0 #3 -n_n1829 1 2 5 0 #4 -n_n1812 1 1 3 0 #5 -n_n1866 1 3 4 0 #6 -n_n1865 1 2 4 0 #7 -[493] 4 5 2 0 #8 -n_n544 5 4 5 0 #9 -n_n416 4 1 4 0 #10 -n_n394 2 1 2 0 #11 -n_n391 2 1 3 0 #12 -n_n300 3 1 0 0 #13 -[260] 3 5 3 0 #14 -n_n437 3 3 3 0 #15 -[223] 5 4 1 0 #16 -[79] 3 5 0 0 #17 -[410] 2 4 1 0 #18 -[516] 4 5 4 0 #19 -[245] 3 4 2 0 #20 -[340] 2 5 5 0 #21 -[432] 2 4 5 0 #22 -[80] 3 4 1 0 #23 -[541] 5 3 5 0 #24 -n_n309 2 1 5 0 #25 -[8] 4 5 5 0 #26 -[546] 3 4 5 0 #27 -n_n706 1 2 3 0 #28 -[261] 2 2 1 0 #29 -[463] 4 4 3 0 #30 -n_n1575 3 5 4 0 #31 -n_n1571 2 4 3 0 #32 -[132] 1 5 3 0 #33 -[355] 2 4 2 0 #34 -[214] 4 4 5 0 #35 -[267] 5 4 4 0 #36 -n_n329 3 2 0 0 #37 -[420] 5 2 2 0 #38 -n_n849 2 2 5 0 #39 -[478] 5 4 0 0 #40 -[578] 4 1 3 0 #41 -[253] 4 2 0 0 #42 -[4] 4 1 5 0 #43 -[56] 1 1 4 0 #44 -[226] 3 1 2 0 #45 -[282] 1 3 3 0 #46 -[377] 1 2 1 0 #47 -[71] 1 1 1 0 #48 -[319] 5 2 5 0 #49 -[233] 4 3 1 0 #50 -[246] 3 4 4 0 #51 -[301] 3 5 1 0 #52 -[441] 5 5 0 0 #53 -[608] 5 4 3 0 #54 -[21] 2 1 4 0 #55 -[311] 4 4 1 0 #56 -[344] 3 2 2 0 #57 -[310] 2 2 2 0 #58 -[315] 1 3 2 0 #59 -[29] 1 4 0 0 #60 -[273] 2 4 4 0 #61 -n_n1690 3 4 0 0 #62 -[383] 5 3 1 0 #63 -[390] 2 2 4 0 #64 -[705] 4 4 4 0 #65 -[41] 4 3 5 0 #66 -[351] 4 1 1 0 #67 -[484] 4 2 1 0 #68 -[437] 5 3 4 0 #69 -[349] 3 2 4 0 #70 -[65] 3 5 5 0 #71 -[221] 4 5 1 0 #72 -[402] 2 4 0 0 #73 -[521] 4 1 0 0 #74 -[767] 4 1 2 0 #75 -[133] 2 5 0 0 #76 -[234] 4 3 4 0 #77 -[868] 1 4 3 0 #78 -[904] 4 4 2 0 #79 -[906] 4 2 4 0 #80 -[919] 2 3 3 0 #81 -[1253] 1 3 0 0 #82 -[1283] 3 1 3 0 #83 -[1340] 3 2 3 0 #84 -[1382] 1 1 0 0 #85 -[1404] 3 2 1 0 #86 -[1417] 3 1 1 0 #87 -[1534] 4 3 3 0 #88 -[1615] 3 5 2 0 #89 -[6947] 2 3 2 0 #90 -[7082] 4 3 0 0 #91 -[7159] 4 2 5 0 #92 -[7165] 5 3 2 0 #93 -[7191] 5 3 3 0 #94 -[7319] 3 3 0 0 #95 -[7321] 5 2 0 0 #96 -[7351] 2 3 4 0 #97 -[7388] 1 2 0 0 #98 -[7423] 2 1 0 0 #99 -[7466] 3 2 5 0 #100 -[7782] 4 4 0 0 #101 -[7822] 2 5 4 0 #102 -[7885] 2 5 3 0 #103 -[7888] 2 3 1 0 #104 -[7997] 5 5 2 0 #105 -[8027] 5 2 4 0 #106 -[50] 2 3 0 0 #107 -[288] 3 3 2 0 #108 -[539] 5 2 1 0 #109 -[372] 4 2 3 0 #110 -n_n1584 2 5 1 0 #111 -[196] 2 2 0 0 #112 -[585] 3 3 5 0 #113 -[365] 4 5 3 0 #114 -[492] 1 4 5 0 #115 -[616] 3 3 1 0 #116 -[430] 2 1 1 0 #117 -[663] 1 2 2 0 #118 -[700] 4 2 2 0 #119 -[322] 1 3 5 0 #120 -[739] 3 3 4 0 #121 -[745] 5 3 0 0 #122 -[771] 3 4 3 0 #123 -[95] 4 5 0 0 #124 -[345] 3 1 4 0 #125 -[759] 3 1 5 0 #126 -[1066] 1 3 1 0 #127 -[7199] 5 1 5 0 #128 -[7969] 5 5 3 0 #129 -[7328] 1 4 1 0 #130 -[7559] 5 2 3 0 #131 -out:o_1_ 3 6 1 0 #132 -out:o_2_ 1 0 5 0 #133 -out:o_0_ 1 6 2 0 #134 -i_30_ 3 6 3 0 #135 -i_20_ 4 0 6 0 #136 -i_9_ 3 0 5 0 #137 -i_10_ 0 1 4 0 #138 -i_7_ 2 6 7 0 #139 -i_8_ 3 0 7 0 #140 -i_5_ 2 0 1 0 #141 -i_6_ 3 0 0 0 #142 -i_27_ 4 6 4 0 #143 -i_14_ 2 6 5 0 #144 -i_3_ 3 0 2 0 #145 -i_28_ 2 0 3 0 #146 -i_13_ 2 0 2 0 #147 -i_4_ 3 0 6 0 #148 -i_25_ 1 0 0 0 #149 -i_12_ 2 0 0 0 #150 -i_1_ 4 0 3 0 #151 -i_26_ 1 0 7 0 #152 -i_11_ 4 0 5 0 #153 -i_2_ 3 0 3 0 #154 -i_23_ 4 6 7 0 #155 -i_18_ 4 0 1 0 #156 -i_24_ 2 0 7 0 #157 -i_17_ 4 0 2 0 #158 -i_0_ 2 6 3 0 #159 -i_21_ 5 6 5 0 #160 -i_16_ 4 6 2 0 #161 -i_22_ 1 0 4 0 #162 -i_32_ 4 0 4 0 #163 -i_31_ 2 0 5 0 #164 -i_34_ 3 6 5 0 #165 -i_33_ 1 0 3 0 #166 -i_19_ 6 1 1 0 #167 -i_36_ 3 6 7 0 #168 -i_35_ 2 0 6 0 #169 -i_38_ 3 0 4 0 #170 -i_29_ 2 6 4 0 #171 -i_37_ 4 6 1 0 #172 +o_1_ 4 1 4 0 #0 +o_2_ 4 3 4 0 #1 +o_0_ 2 2 0 0 #2 +n_n1829 3 5 4 0 #3 +n_n1812 5 3 5 0 #4 +n_n1866 4 5 1 0 #5 +n_n1865 4 5 3 0 #6 +[493] 2 1 2 0 #7 +n_n544 3 1 0 0 #8 +n_n416 4 4 0 0 #9 +n_n394 5 4 5 0 #10 +n_n391 5 3 4 0 #11 +n_n300 4 5 5 0 #12 +[260] 3 2 4 0 #13 +[223] 3 1 4 0 #14 +[79] 2 2 4 0 #15 +[410] 1 3 1 0 #16 +[516] 1 3 2 0 #17 +[530] 1 1 1 0 #18 +[245] 1 2 0 0 #19 +[340] 1 4 4 0 #20 +[432] 3 1 2 0 #21 +[533] 2 3 3 0 #22 +[80] 2 2 5 0 #23 +[535] 1 2 1 0 #24 +n_n316 4 2 4 0 #25 +[541] 1 2 5 0 #26 +n_n1563 2 2 1 0 #27 +n_n1585 2 3 4 0 #28 +[38] 2 3 2 0 #29 +n_n706 4 2 3 0 #30 +n_n608 2 1 1 0 #31 +[261] 4 1 0 0 #32 +[463] 5 1 3 0 #33 +n_n1578 1 2 3 0 #34 +[124] 2 3 1 0 #35 +[132] 3 3 2 0 #36 +[227] 1 1 3 0 #37 +[267] 2 2 2 0 #38 +n_n329 2 2 3 0 #39 +n_n849 4 5 0 0 #40 +[478] 2 3 0 0 #41 +[578] 5 5 0 0 #42 +[253] 5 3 2 0 #43 +[4] 5 4 3 0 #44 +[56] 4 4 3 0 #45 +[226] 4 2 5 0 #46 +[282] 5 4 2 0 #47 +[377] 5 5 4 0 #48 +[71] 5 3 3 0 #49 +[246] 3 2 1 0 #50 +[301] 3 1 1 0 #51 +[311] 4 4 4 0 #52 +[344] 4 4 1 0 #53 +[310] 4 2 2 0 #54 +[315] 4 3 0 0 #55 +[78] 3 5 5 0 #56 +[656] 5 3 0 0 #57 +[29] 2 4 1 0 #58 +[273] 3 1 3 0 #59 +[668] 1 2 4 0 #60 +[674] 5 3 1 0 #61 +[74] 1 2 2 0 #62 +n_n1704 4 1 3 0 #63 +[327] 4 5 2 0 #64 +[305] 1 4 3 0 #65 +n_n1702 4 1 5 0 #66 +[351] 5 2 3 0 #67 +[437] 3 3 3 0 #68 +[349] 5 1 5 0 #69 +[65] 1 1 0 0 #70 +[221] 2 1 5 0 #71 +[343] 3 4 5 0 #72 +[406] 5 2 5 0 #73 +[521] 5 4 0 0 #74 +[161] 3 1 5 0 #75 +[189] 2 4 2 0 #76 +[906] 2 4 3 0 #77 +[977] 4 3 5 0 #78 +[1340] 4 4 5 0 #79 +[1426] 5 2 1 0 #80 +[1435] 5 4 1 0 #81 +[1542] 4 3 3 0 #82 +[1615] 3 4 3 0 #83 +[1619] 4 1 2 0 #84 +[6958] 1 4 2 0 #85 +[7025] 5 2 4 0 #86 +[7082] 1 1 5 0 #87 +[7160] 3 2 2 0 #88 +[7319] 3 4 0 0 #89 +[7321] 4 5 4 0 #90 +[7388] 3 3 0 0 #91 +[7390] 3 5 2 0 #92 +[7787] 1 3 3 0 #93 +[7791] 2 3 5 0 #94 +[7811] 2 1 3 0 #95 +[7822] 4 2 0 0 #96 +[7829] 2 1 4 0 #97 +[7885] 3 4 4 0 #98 +[7899] 1 3 5 0 #99 +[7901] 1 1 4 0 #100 +[7997] 1 3 4 0 #101 +[8027] 2 1 0 0 #102 +[8042] 1 4 1 0 #103 +[50] 3 5 3 0 #104 +[307] 3 2 5 0 #105 +[275] 3 2 3 0 #106 +[372] 3 4 1 0 #107 +[503] 3 5 0 0 #108 +[585] 2 4 4 0 #109 +[63] 2 5 3 0 #110 +[431] 5 2 2 0 #111 +[447] 3 3 1 0 #112 +[615] 2 4 5 0 #113 +n_n1716 1 3 0 0 #114 +[254] 4 3 2 0 #115 +[381] 5 4 4 0 #116 +[430] 4 3 1 0 #117 +[276] 4 4 2 0 #118 +[760] 3 4 2 0 #119 +[768] 4 1 1 0 #120 +[792] 2 5 2 0 #121 +[721] 5 2 0 0 #122 +[877] 3 2 0 0 #123 +[884] 4 2 1 0 #124 +[1021] 3 3 5 0 #125 +[1077] 3 3 4 0 #126 +[1700] 1 4 0 0 #127 +[7108] 2 4 0 0 #128 +[7211] 5 1 1 0 #129 +[7516] 2 5 0 0 #130 +[7531] 2 5 4 0 #131 +[7820] 1 4 5 0 #132 +[7917] 2 5 5 0 #133 +[7028] 2 5 1 0 #134 +[7774] 1 5 5 0 #135 +[7778] 1 5 2 0 #136 +[177] 1 1 2 0 #137 +out:o_1_ 4 0 0 0 #138 +out:o_2_ 4 6 1 0 #139 +out:o_0_ 2 0 4 0 #140 +i_30_ 2 6 7 0 #141 +i_20_ 2 0 3 0 #142 +i_9_ 5 6 5 0 #143 +i_10_ 3 6 6 0 #144 +i_7_ 2 0 5 0 #145 +i_8_ 4 6 4 0 #146 +i_5_ 5 6 6 0 #147 +i_6_ 3 0 3 0 #148 +i_27_ 3 0 1 0 #149 +i_14_ 2 0 1 0 #150 +i_3_ 6 4 5 0 #151 +i_28_ 3 0 7 0 #152 +i_13_ 2 0 2 0 #153 +i_4_ 6 2 7 0 #154 +i_25_ 4 6 0 0 #155 +i_12_ 1 0 4 0 #156 +i_1_ 6 2 2 0 #157 +i_26_ 3 6 2 0 #158 +i_11_ 4 0 1 0 #159 +i_2_ 4 6 7 0 #160 +i_23_ 2 0 7 0 #161 +i_18_ 5 6 4 0 #162 +i_24_ 2 0 6 0 #163 +i_17_ 3 0 0 0 #164 +i_0_ 4 0 5 0 #165 +i_21_ 2 6 1 0 #166 +i_16_ 0 3 0 0 #167 +i_22_ 3 6 0 0 #168 +i_32_ 3 6 7 0 #169 +i_31_ 2 6 5 0 #170 +i_34_ 1 0 6 0 #171 +i_33_ 4 0 7 0 #172 +i_19_ 6 4 6 0 #173 +i_36_ 1 0 1 0 #174 +i_35_ 1 0 7 0 #175 +i_38_ 4 6 3 0 #176 +i_29_ 3 6 1 0 #177 +i_37_ 3 0 6 0 #178 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt index 76744275cd6..c02d12cd3b3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 15.55 vpr 74.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76704 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.1 MiB 5.08 5783 1135 0 0 1135 74.9 MiB 0.08 0.01 5.08129 -15.1527 -5.08129 nan 0.20 0.00521387 0.00456397 0.054855 0.0516446 -1 -1 -1 -1 164 7880 41 1.34735e+06 7.11401e+06 957298. 19536.7 8.09 2.3336 2.00198 18546 296938 -1 7311 19 6308 26453 1146687 361661 5.58525 nan -16.6102 -5.58525 0 0 1.19720e+06 24432.6 0.03 0.49 0.23 -1 -1 0.03 0.228213 0.208678 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fix_clusters_test_arch.xml apex2.blif common 6.20 vpr 73.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 138 38 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75236 38 3 1916 1919 0 1057 179 7 7 49 clb auto 34.1 MiB 2.36 5571 5572 1187 0 0 1187 73.5 MiB 0.04 0.00 4.76188 4.76188 -14.2451 -4.76188 nan 0.07 0.0020291 0.00182219 0.0299414 0.0288567 -1 -1 -1 -1 158 7466 37 1.34735e+06 7.43737e+06 924312. 18863.5 2.34 0.677286 0.586504 18354 286522 -1 7089 17 5844 24589 1071101 337183 5.3663 nan -15.678 -5.3663 0 0 1.15416e+06 23554.3 0.02 0.27 0.14 -1 -1 0.02 0.13834 0.128348 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt index 2735c09358a..c05a6c5feab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.00 vpr 66.73 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36456 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.07 499 1698 69 1565 64 66.7 MiB 0.04 0.00 2.45489 -182.908 -2.45489 2.31533 0.06 0.000803566 0.000668095 0.0165762 0.0143795 -1 -1 -1 -1 18 719 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.43 0.155736 0.134195 2616 8308 -1 605 32 901 2129 57619 17801 2.65666 2.40393 -192.483 -2.65666 0 0 59124.6 1206.62 0.00 0.09 0.01 -1 -1 0.00 0.062047 0.0552258 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.83 odin 166.50 MiB 2.52 170496 -1 -1 4 0.12 -1 -1 33108 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 25.5 MiB 0.04 688 531 1981 91 1813 77 65.7 MiB 0.02 0.00 2.92675 2.71243 -182.607 -2.71243 2.42504 0.02 0.000399329 0.000342509 0.00938853 0.00827764 -1 -1 -1 -1 18 741 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.17 0.0698213 0.0586341 2616 8308 -1 669 22 765 1836 62890 21794 2.72374 2.48096 -195.552 -2.72374 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0213747 0.0186684 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt index 03193b42990..bb3ec60f9df 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 26.23 vpr 87.18 MiB 0.37 31744 -1 -1 3 1.50 -1 -1 43564 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89276 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 46.2 MiB 4.36 11021 242654 80011 140532 22111 87.2 MiB 2.29 0.03 4.72515 -2651.47 -4.72515 4.72515 0.68 0.00870927 0.00789125 0.867466 0.775905 -1 -1 -1 -1 58 24978 46 1.65001e+07 9.79696e+06 1.00638e+06 2787.76 11.26 3.56546 3.21933 34441 208101 -1 21032 16 5966 14058 1826516 536884 5.22938 5.22938 -3010.82 -5.22938 0 0 1.28387e+06 3556.43 0.10 1.10 0.34 -1 -1 0.10 0.47794 0.447984 - buffered_flyover_wires.xml raygentop.v common 23.64 vpr 87.26 MiB 0.39 31872 -1 -1 3 1.51 -1 -1 43828 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89352 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.72 11369 231398 74152 135293 21953 87.3 MiB 2.16 0.03 4.81413 -2746.12 -4.81413 4.81413 0.60 0.00796315 0.00714187 0.791566 0.711054 -1 -1 -1 -1 64 23029 28 1.65001e+07 9.79696e+06 1.15406e+06 3196.84 8.51 3.3002 2.94744 35881 226057 -1 19740 15 5519 12704 1627954 469106 4.80072 4.80072 -2914.34 -4.80072 0 0 1.44847e+06 4012.38 0.10 0.92 0.36 -1 -1 0.10 0.422967 0.392398 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +shorted_flyover_wires.xml raygentop.v common 21.34 odin 1.51 GiB 10.42 1588180 -1 -1 3 0.82 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88708 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.19 24028 11417 245468 84522 140289 20657 86.6 MiB 0.91 0.01 5.44161 4.44985 -2711.83 -4.44985 4.44985 0.22 0.0036036 0.00332323 0.350101 0.321011 -1 -1 -1 -1 62 24833 45 1.65001e+07 9.79696e+06 1.07728e+06 2984.15 3.72 1.37948 1.27017 35161 217957 -1 21028 18 6730 15878 2433481 654279 5.215 5.215 -3026.13 -5.215 0 0 1.33769e+06 3705.50 0.04 0.49 0.13 -1 -1 0.04 0.202402 0.191487 +buffered_flyover_wires.xml raygentop.v common 21.52 odin 1.54 GiB 10.85 1614668 -1 -1 3 0.83 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88816 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.7 MiB 2.17 24520 12150 245468 84299 140070 21099 86.7 MiB 0.91 0.01 5.76052 4.50441 -2846.22 -4.50441 4.50441 0.22 0.0036495 0.00331524 0.34963 0.320924 -1 -1 -1 -1 64 25856 29 1.65001e+07 9.79696e+06 1.15406e+06 3196.84 3.52 1.26975 1.16892 35881 226057 -1 21156 15 6633 15933 2219536 617587 4.97633 4.97633 -3163.74 -4.97633 0 0 1.44847e+06 4012.38 0.04 0.44 0.14 -1 -1 0.04 0.182386 0.172674 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt index b90ac6049e3..43da8d8e85b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 3.31 vpr 64.39 MiB 0.03 7296 -1 -1 1 0.04 -1 -1 34228 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65940 193 32 545 422 1 289 227 21 21 441 io auto 25.0 MiB 1.91 3735 46591 19762 26388 441 64.4 MiB 0.33 0.00 2.985 -824.634 -2.985 2.985 0.00 0.00288823 0.00269357 0.190083 0.178688 -1 -1 -1 -1 4590 15.9375 1212 4.20833 431 431 162323 43530 809148 68766.3 979092. 2220.16 5 24050 197379 -1 2.985 2.985 -813.802 -2.985 -21.7856 -0.0851 0.43 -1 -1 64.4 MiB 0.09 0.239729 0.22641 64.4 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +hard_fpu_arch_timing.xml mm3.v common 2.92 odin 76.88 MiB 1.75 78720 -1 -1 1 0.03 -1 -1 30624 -1 -1 0 193 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64292 193 32 545 422 1 289 227 21 21 441 io auto 23.2 MiB 0.38 5010 3747 45899 19410 26043 446 62.8 MiB 0.13 0.00 2.985 2.985 -824.872 -2.985 2.985 0.00 0.00102822 0.000970656 0.0710574 0.0670693 -1 -1 -1 -1 4610 16.0069 1211 4.20486 431 431 145305 38673 809148 68766.3 979092. 2220.16 6 24050 197379 -1 2.985 2.985 -813.692 -2.985 -21.8252 -0.0851 0.13 -1 -1 62.8 MiB 0.03 0.0906843 0.085784 62.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt index 356e91ccb39..91c6bc9bce7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 3.01 vpr 67.75 MiB 0.06 9728 -1 -1 3 0.26 -1 -1 39908 -1 -1 69 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69380 99 130 363 493 1 251 299 13 13 169 clb auto 28.2 MiB 0.66 756 79220 19640 31087 28493 67.8 MiB 0.16 0.00 36 1238 7 0 0 481804. 2850.91 0.62 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.04 odin 102.38 MiB 2.28 104832 -1 -1 3 0.20 -1 -1 34096 -1 -1 71 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68324 99 130 363 493 1 251 301 13 13 169 clb auto 26.7 MiB 0.40 2129 766 78925 23058 31147 24720 66.7 MiB 0.06 0.00 34 1460 7 0 0 460544. 2725.11 0.23 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt index a8ea9747374..b2d02f39e8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.21 vpr 66.19 MiB 0.08 10368 -1 -1 4 0.19 -1 -1 36516 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67780 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.09 431 1932 256 1610 66 66.2 MiB 0.04 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000582727 0.000489391 0.0185537 0.0162573 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0660847 0.0581726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.41 odin 167.25 MiB 2.50 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 427 2461 355 2028 78 65.7 MiB 0.02 0.00 2.92195 2.72416 -177.287 -2.72416 2.43773 0.00 0.000399205 0.000348503 0.0106789 0.00938853 -1 -1 -1 -1 -1 457 20 1.07788e+06 1.07788e+06 90369.8 1844.28 0.03 0.0308402 0.0270103 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt index 265af1c4b6f..a39697152a5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.39 vpr 60.20 MiB -1 -1 -1 -1 0 0.02 -1 -1 33040 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61648 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.2 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1661e-05 6.33e-06 7.7033e-05 5.0742e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00147387 0.00140823 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.38 vpr 60.24 MiB -1 -1 -1 -1 0 0.02 -1 -1 32912 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61684 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.2 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1339e-05 5.859e-06 8.8591e-05 5.8829e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00162493 0.00154875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.37 vpr 60.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 32868 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3541e-05 7.635e-06 8.6471e-05 5.7499e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00150205 0.00143129 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.38 vpr 60.58 MiB -1 -1 -1 -1 0 0.02 -1 -1 32612 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 6 1 1 8 0 1 8 3 3 9 -1 auto 22.3 MiB 0.00 0 21 0 10 11 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.7003e-05 9.772e-06 9.7802e-05 6.5568e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00166482 0.00158779 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.39 vpr 60.29 MiB -1 -1 -1 -1 1 0.03 -1 -1 33040 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61732 2 1 3 4 0 3 4 3 3 9 -1 auto 21.9 MiB 0.00 9 9 3 3 3 60.3 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.5758e-05 1.1048e-05 0.000114967 8.6726e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00169019 0.00161423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.50 vpr 60.59 MiB -1 -1 -1 -1 1 0.05 -1 -1 34804 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.5271e-05 1.9684e-05 0.000266101 0.000119821 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00203214 0.00174712 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.51 vpr 60.46 MiB -1 -1 -1 -1 1 0.05 -1 -1 35364 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.0382e-05 1.5156e-05 0.000144485 0.00011379 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00203203 0.0018606 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.35 vpr 60.57 MiB -1 -1 -1 -1 1 0.02 -1 -1 33216 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 3 1 5 6 1 4 5 3 3 9 -1 auto 22.1 MiB 0.00 9 12 7 1 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.8755e-05 1.3531e-05 0.00012903 9.8796e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00153901 0.00145183 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.50 vpr 60.45 MiB -1 -1 -1 -1 1 0.06 -1 -1 35348 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61904 4 1 4 6 0 4 6 3 3 9 -1 auto 22.1 MiB 0.00 12 15 9 3 3 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.3369e-05 1.7039e-05 0.000173745 0.000138562 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00205463 0.00186426 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_2x2.blif common 0.47 vpr 60.48 MiB -1 -1 -1 -1 1 0.06 -1 -1 35020 -1 -1 1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61928 4 4 8 12 0 8 9 3 3 9 -1 auto 22.1 MiB 0.00 24 27 18 6 3 60.5 MiB 0.00 0.00 0.67231 -2.68924 -0.67231 nan 0.00 3.869e-05 2.9429e-05 0.000257326 0.00021682 -1 -1 -1 -1 -1 10 10 53894 53894 38783.3 4309.26 0.00 0.00244349 0.00222744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x3.blif common 0.51 vpr 60.62 MiB -1 -1 -1 -1 1 0.07 -1 -1 36084 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62076 6 6 12 18 0 12 13 3 3 9 -1 auto 22.1 MiB 0.01 36 43 32 7 4 60.6 MiB 0.00 0.00 0.69831 -4.13786 -0.69831 nan 0.00 7.4526e-05 6.3137e-05 0.000498869 0.000443741 -1 -1 -1 -1 -1 17 12 53894 53894 38783.3 4309.26 0.00 0.00383316 0.00343212 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x4.blif common 0.55 vpr 60.62 MiB -1 -1 -1 -1 2 0.07 -1 -1 35568 -1 -1 3 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62076 7 8 22 30 0 15 18 4 4 16 clb auto 22.1 MiB 0.01 51 64 26 37 1 60.6 MiB 0.00 0.00 1.24888 -7.62396 -1.24888 nan 0.00 9.8331e-05 8.571e-05 0.000766204 0.000700688 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00447879 0.00416054 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_4x4.blif common 0.55 vpr 60.55 MiB -1 -1 -1 -1 4 0.08 -1 -1 35668 -1 -1 2 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62004 8 8 29 37 0 21 18 4 4 16 clb auto 22.0 MiB 0.02 74 64 20 44 0 60.6 MiB 0.00 0.00 2.04839 -11.7951 -2.04839 nan 0.00 0.000135237 0.000115292 0.00112979 0.00104286 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.01 0.00691358 0.00626039 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x5.blif common 0.61 vpr 60.96 MiB -1 -1 -1 -1 4 0.10 -1 -1 36048 -1 -1 4 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62424 10 10 47 57 0 39 24 4 4 16 clb auto 22.1 MiB 0.02 149 92 35 57 0 61.0 MiB 0.00 0.00 2.73035 -18.1288 -2.73035 nan 0.00 0.000225575 0.000203726 0.00149243 0.00139063 -1 -1 -1 -1 -1 123 10 215576 215576 99039.1 6189.95 0.01 0.00763482 0.00712644 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x6.blif common 0.83 vpr 60.83 MiB -1 -1 -1 -1 5 0.15 -1 -1 36408 -1 -1 5 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62288 11 11 61 72 0 51 27 5 5 25 clb auto 21.9 MiB 0.03 192 547 116 431 0 60.8 MiB 0.01 0.00 3.17925 -21.2667 -3.17925 nan 0.00 0.000354484 0.000320379 0.00678629 0.00617992 -1 -1 -1 -1 -1 163 16 485046 269470 186194. 7447.77 0.02 0.0240229 0.0219824 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_1bit.blif common 0.49 vpr 60.46 MiB -1 -1 -1 -1 1 0.06 -1 -1 34452 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.5 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 3.2064e-05 2.4155e-05 0.000200579 0.000160863 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00242941 0.00220554 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_2bit.blif common 0.46 vpr 60.28 MiB -1 -1 -1 -1 1 0.06 -1 -1 35352 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61728 5 3 8 11 0 8 9 3 3 9 -1 auto 21.9 MiB 0.00 24 27 21 6 0 60.3 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 3.5791e-05 2.5977e-05 0.000240831 0.000201092 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00270512 0.00243979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_3bit.blif common 0.52 vpr 60.61 MiB -1 -1 -1 -1 2 0.06 -1 -1 35400 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62060 7 4 12 16 0 11 12 3 3 9 -1 auto 22.3 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 4.7612e-05 3.9433e-05 0.000326091 0.000287024 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00528941 0.00513278 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_4bit.blif common 0.64 vpr 60.55 MiB -1 -1 -1 -1 2 0.07 -1 -1 35520 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62008 9 5 15 20 0 14 15 3 3 9 -1 auto 22.2 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 8.1588e-05 7.0424e-05 0.000516653 0.000461489 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.01 0.00432254 0.00385687 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_5bit.blif common 0.56 vpr 60.67 MiB -1 -1 -1 -1 3 0.07 -1 -1 35440 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62124 11 6 19 25 0 17 18 3 3 9 -1 auto 22.1 MiB 0.01 51 64 33 24 7 60.7 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 5.6728e-05 4.4391e-05 0.000433977 0.000387108 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00412344 0.0036326 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.34 vpr 58.67 MiB -1 -1 -1 -1 0 0.02 -1 -1 29684 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.089e-06 3.317e-06 5.6683e-05 3.778e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000889494 0.000836499 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.34 vpr 59.04 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 59.0 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.199e-06 3.438e-06 5.6499e-05 3.6758e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00086748 0.000809475 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.35 vpr 58.36 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59760 6 1 1 8 0 1 8 3 3 9 -1 auto 19.5 MiB 0.00 0 0 21 0 10 11 58.4 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.125e-06 3.333e-06 5.6385e-05 3.6627e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000917244 0.000850516 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 vpr 58.55 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59956 6 1 1 8 0 1 8 3 3 9 -1 auto 19.7 MiB 0.00 0 0 21 0 10 11 58.6 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.243e-06 3.368e-06 5.7388e-05 3.8084e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000924173 0.000870894 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.34 vpr 59.04 MiB -1 -1 -1 -1 1 0.02 -1 -1 29952 -1 -1 1 2 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 2 1 3 4 0 3 4 3 3 9 -1 auto 20.6 MiB 0.00 9 9 9 3 3 3 59.0 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 8.568e-06 5.408e-06 7.134e-05 5.2207e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000943335 0.000884471 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.40 vpr 58.47 MiB -1 -1 -1 -1 1 0.03 -1 -1 31872 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59876 5 1 6 7 0 6 7 3 3 9 -1 auto 20.0 MiB 0.00 18 18 18 13 5 0 58.5 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.1859e-05 8.393e-06 9.4908e-05 7.4463e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00118215 0.00106723 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.38 vpr 58.44 MiB -1 -1 -1 -1 1 0.03 -1 -1 31456 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59840 5 1 6 7 0 6 7 3 3 9 -1 auto 19.6 MiB 0.00 18 18 18 13 5 0 58.4 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.1739e-05 8.203e-06 0.000106965 8.6112e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.0011722 0.00105647 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.31 vpr 58.76 MiB -1 -1 -1 -1 1 0.02 -1 -1 29888 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60172 3 1 5 6 1 4 5 3 3 9 -1 auto 20.3 MiB 0.00 9 9 12 7 1 4 58.8 MiB 0.00 0.00 0.603526 0.52647 -0.88231 -0.52647 0.52647 0.00 1.1008e-05 7.698e-06 8.9061e-05 6.8418e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00102668 0.000965951 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.39 vpr 59.05 MiB -1 -1 -1 -1 1 0.03 -1 -1 31816 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60464 4 1 4 6 0 4 6 3 3 9 -1 auto 20.2 MiB 0.00 12 12 15 9 3 3 59.0 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.0053e-05 6.686e-06 8.6436e-05 6.5007e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00107231 0.000965027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_2x2.blif common 0.40 vpr 59.06 MiB -1 -1 -1 -1 1 0.03 -1 -1 31488 -1 -1 1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60476 4 4 8 12 0 8 9 3 3 9 -1 auto 20.6 MiB 0.00 24 24 27 18 6 3 59.1 MiB 0.00 0.00 0.749366 0.67231 -2.68924 -0.67231 nan 0.00 1.9318e-05 1.3972e-05 0.000158654 0.000133247 -1 -1 -1 -1 -1 12 10 53894 53894 38783.3 4309.26 0.00 0.00140163 0.00127272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.37 vpr 59.46 MiB -1 -1 -1 -1 1 0.04 -1 -1 31964 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60884 6 6 12 18 0 12 13 3 3 9 -1 auto 20.6 MiB 0.00 36 36 43 32 7 4 59.5 MiB 0.00 0.00 0.775365 0.69831 -4.13786 -0.69831 nan 0.00 2.7042e-05 2.2564e-05 0.000247601 0.000221527 -1 -1 -1 -1 -1 15 12 53894 53894 38783.3 4309.26 0.00 0.00183205 0.00165112 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.44 vpr 58.50 MiB -1 -1 -1 -1 2 0.04 -1 -1 32092 -1 -1 3 7 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59908 7 8 22 30 0 15 18 4 4 16 clb auto 19.9 MiB 0.01 62 51 64 26 37 1 58.5 MiB 0.00 0.00 1.24888 1.24888 -7.62396 -1.24888 nan 0.00 4.8704e-05 4.2552e-05 0.000465724 0.000435078 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.0025176 0.00234313 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.43 vpr 58.89 MiB -1 -1 -1 -1 4 0.04 -1 -1 32472 -1 -1 2 8 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60308 8 8 29 37 0 21 18 4 4 16 clb auto 20.2 MiB 0.01 82 74 64 20 44 0 58.9 MiB 0.00 0.00 2.04839 2.04839 -11.7951 -2.04839 nan 0.00 6.6449e-05 5.7293e-05 0.000651925 0.000612325 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.00 0.00383257 0.00350913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.48 vpr 59.43 MiB -1 -1 -1 -1 4 0.06 -1 -1 32828 -1 -1 4 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60860 10 10 47 57 0 39 24 4 4 16 clb auto 20.2 MiB 0.01 161 149 92 35 57 0 59.4 MiB 0.00 0.00 2.80144 2.73035 -18.1288 -2.73035 nan 0.00 9.807e-05 8.8114e-05 0.000986347 0.000939221 -1 -1 -1 -1 -1 120 10 215576 215576 99039.1 6189.95 0.01 0.00527492 0.00488366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.55 vpr 59.18 MiB -1 -1 -1 -1 5 0.07 -1 -1 32492 -1 -1 5 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60604 11 11 61 72 0 49 27 5 5 25 clb auto 20.2 MiB 0.02 227 192 427 90 337 0 59.2 MiB 0.00 0.00 3.28962 3.19291 -21.0185 -3.19291 nan 0.00 0.000132308 0.000120709 0.00247373 0.00230808 -1 -1 -1 -1 -1 193 14 485046 269470 186194. 7447.77 0.01 0.00907418 0.0082901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.39 vpr 58.82 MiB -1 -1 -1 -1 1 0.03 -1 -1 31076 -1 -1 1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60236 3 2 5 7 0 5 6 3 3 9 -1 auto 20.0 MiB 0.00 15 15 15 9 5 1 58.8 MiB 0.00 0.00 0.749366 0.67231 -1.34462 -0.67231 nan 0.00 1.2937e-05 9.527e-06 0.000111053 8.9028e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00124373 0.00111746 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.37 vpr 59.06 MiB -1 -1 -1 -1 1 0.03 -1 -1 32248 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60476 5 3 8 11 0 8 9 3 3 9 -1 auto 20.6 MiB 0.00 24 24 27 21 6 0 59.1 MiB 0.00 0.00 0.749366 0.67231 -2.01693 -0.67231 nan 0.00 1.8848e-05 1.3648e-05 0.000147542 0.000123211 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00160521 0.0014395 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.40 vpr 59.07 MiB -1 -1 -1 -1 2 0.03 -1 -1 32248 -1 -1 1 7 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60488 7 4 12 16 0 11 12 3 3 9 -1 auto 20.3 MiB 0.00 33 33 38 24 11 3 59.1 MiB 0.00 0.00 1.08437 1.08437 -4.00246 -1.08437 nan 0.00 2.2911e-05 1.8441e-05 0.000197494 0.000174107 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00143759 0.00133696 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.39 vpr 58.84 MiB -1 -1 -1 -1 2 0.04 -1 -1 32248 -1 -1 1 9 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60252 9 5 15 20 0 14 15 3 3 9 -1 auto 20.0 MiB 0.00 42 42 51 29 17 5 58.8 MiB 0.00 0.00 1.08437 1.00731 -4.36655 -1.00731 nan 0.00 2.7047e-05 2.2343e-05 0.000265248 0.00023853 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00193659 0.00174421 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.41 vpr 58.64 MiB -1 -1 -1 -1 3 0.03 -1 -1 32248 -1 -1 1 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60048 11 6 19 25 0 17 18 3 3 9 -1 auto 19.8 MiB 0.00 51 51 64 36 21 7 58.6 MiB 0.00 0.00 1.41937 1.34231 -6.71386 -1.34231 nan 0.00 3.3381e-05 2.6743e-05 0.000296707 0.000268415 -1 -1 -1 -1 -1 21 11 53894 53894 38783.3 4309.26 0.00 0.00209724 0.00191061 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt index 33183dc0a9f..9c8f24bb57f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.33 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3821e-05 7.858e-06 8.9635e-05 6.0426e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00127569 0.00120513 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61760 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.0 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2203e-05 6.662e-06 7.9048e-05 5.258e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00167909 0.00160437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.30 vpr 60.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61712 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.3 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 3.2696e-05 2.3426e-05 0.000197822 0.000159059 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.0018336 0.0017293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 6 1 7 8 0 7 8 3 3 9 -1 auto 22.3 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.7376e-05 1.9376e-05 0.000172772 0.000138442 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00173443 0.0016423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.26 vpr 60.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61804 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.4 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.1966e-05 1.6158e-05 0.000132177 0.000102284 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00191949 0.00184253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.5373e-05 1.8911e-05 0.000175189 0.000138808 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00175813 0.00166803 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.23 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.41e-06 3.582e-06 5.4963e-05 3.5971e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000865124 0.000812185 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.21 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 -1 1 1 2 0 1 2 3 3 9 -1 auto 20.2 MiB 0.00 0 0 3 0 0 3 59.0 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.345e-06 3.614e-06 5.5264e-05 3.6499e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000882878 0.000829048 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.23 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 6 1 7 8 0 7 8 3 3 9 -1 auto 20.2 MiB 0.00 21 21 21 14 7 0 59.0 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.3883e-05 9.097e-06 9.7954e-05 7.7169e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00101724 0.000957538 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.22 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60464 6 1 7 8 0 7 8 3 3 9 -1 auto 20.2 MiB 0.00 21 21 21 14 7 0 59.0 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.4054e-05 9.237e-06 0.000103459 8.117e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00100695 0.000945272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.24 vpr 58.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59720 5 1 6 7 0 6 7 3 3 9 -1 auto 19.5 MiB 0.00 18 18 18 13 5 0 58.3 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2891e-05 9.225e-06 0.000102343 8.0654e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00102367 0.000961224 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.25 vpr 59.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60844 5 1 6 7 0 6 7 3 3 9 -1 auto 20.7 MiB 0.00 18 18 18 13 5 0 59.4 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.213e-05 8.696e-06 0.000106784 8.1447e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.000983793 0.000910586 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index eaf5555874c..049137ed642 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 1.83 vpr 66.90 MiB 0.07 10496 -1 -1 4 0.18 -1 -1 36452 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68504 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.20 415 2196 413 1711 72 66.9 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.0007561 0.000646489 0.0218848 0.0192021 -1 -1 -1 -1 12 302 11 1.07788e+06 700622 -1 -1 0.20 0.128028 0.113742 2680 3516 -1 297 3 164 241 11232 5767 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0191965 0.0182163 - x_uniform_y_gaussian.xml stereovision3.v common 1.88 vpr 67.18 MiB 0.07 10624 -1 -1 4 0.21 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 11 30 262 292 2 110 54 7 7 49 clb auto 28.1 MiB 0.13 404 2298 458 1774 66 67.2 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.00 0.000687045 0.000583062 0.0174363 0.0155371 -1 -1 -1 -1 12 308 8 1.07788e+06 700622 -1 -1 0.31 0.110517 0.0976349 2680 3516 -1 297 3 168 247 11340 5786 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0178597 0.0169935 - x_gaussian_y_gaussian.xml stereovision3.v common 1.87 vpr 66.84 MiB 0.06 10496 -1 -1 4 0.16 -1 -1 36536 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68444 11 30 262 292 2 110 54 7 7 49 clb auto 27.9 MiB 0.18 410 2298 443 1773 82 66.8 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000756768 0.000647761 0.0255781 0.0225686 -1 -1 -1 -1 14 303 4 1.07788e+06 700622 -1 -1 0.40 0.162052 0.141633 2680 3516 -1 295 3 165 244 11438 5780 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0211596 0.0200797 - x_delta_y_uniform.xml stereovision3.v common 1.95 vpr 67.15 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36504 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68764 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.14 450 3012 620 2301 91 67.2 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000754694 0.000686961 0.028 0.0247412 -1 -1 -1 -1 48 342 3 1.07788e+06 700622 -1 -1 0.49 0.268135 0.232895 2680 3516 -1 342 3 170 251 11060 5468 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0196307 0.0186303 - x_delta_y_delta.xml stereovision3.v common 2.11 vpr 67.59 MiB 0.07 10496 -1 -1 4 0.22 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69212 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.13 519 3012 615 2292 105 67.6 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000782235 0.000651544 0.0273675 0.0237579 -1 -1 -1 -1 54 442 17 1.07788e+06 700622 -1 -1 0.52 0.268766 0.234157 2680 3516 -1 431 4 215 308 16404 8615 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0214181 0.0202532 - x_uniform_y_delta.xml stereovision3.v common 2.05 vpr 67.14 MiB 0.07 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68756 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.15 435 2502 457 1952 93 67.1 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000965335 0.000843275 0.027473 0.0239971 -1 -1 -1 -1 34 323 16 1.07788e+06 700622 -1 -1 0.51 0.30529 0.26214 2680 3516 -1 317 16 376 682 28098 12512 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0352499 0.0319547 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +x_gaussian_y_uniform.xml stereovision3.v common 3.79 odin 167.62 MiB 2.53 171648 -1 -1 4 0.12 -1 -1 33076 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67216 11 30 262 292 2 107 54 7 7 49 clb auto 26.7 MiB 0.06 616 394 1788 342 1398 48 65.6 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000394558 0.000343514 0.00983066 0.00882096 -1 -1 -1 -1 10 309 8 1.07788e+06 700622 -1 -1 0.14 0.0540553 0.0467468 2680 3516 -1 281 3 216 332 13740 6540 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0110537 0.0104942 +x_uniform_y_gaussian.xml stereovision3.v common 3.74 odin 167.25 MiB 2.55 171264 -1 -1 4 0.12 -1 -1 33232 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67052 11 30 262 292 2 107 54 7 7 49 clb auto 26.5 MiB 0.06 616 416 1584 291 1249 44 65.5 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000398166 0.000347484 0.00915684 0.00820103 -1 -1 -1 -1 14 315 2 1.07788e+06 700622 -1 -1 0.07 0.0511739 0.044167 2680 3516 -1 312 2 155 239 9997 5015 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.0106007 0.0101553 +x_gaussian_y_gaussian.xml stereovision3.v common 4.09 odin 167.62 MiB 2.87 171648 -1 -1 4 0.12 -1 -1 33092 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66724 11 30 262 292 2 107 54 7 7 49 clb auto 26.2 MiB 0.07 616 414 2094 382 1620 92 65.2 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000407004 0.00035303 0.0114405 0.0101707 -1 -1 -1 -1 14 297 3 1.07788e+06 700622 -1 -1 0.07 0.0544621 0.0470729 2680 3516 -1 298 16 183 323 13761 7064 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0194151 0.0174723 +x_delta_y_uniform.xml stereovision3.v common 3.79 odin 167.62 MiB 2.50 171648 -1 -1 4 0.12 -1 -1 33076 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67272 11 30 262 292 2 107 54 7 7 49 clb auto 26.4 MiB 0.06 616 433 2604 491 2026 87 65.7 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000398035 0.000342425 0.013054 0.0115899 -1 -1 -1 -1 38 323 9 1.07788e+06 700622 -1 -1 0.15 0.0912421 0.0775499 2680 3516 -1 318 3 165 251 11417 5738 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0116648 0.0110807 +x_delta_y_delta.xml stereovision3.v common 3.94 odin 167.62 MiB 2.63 171648 -1 -1 4 0.13 -1 -1 33080 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67316 11 30 262 292 2 107 54 7 7 49 clb auto 26.4 MiB 0.06 616 488 3114 640 2376 98 65.7 MiB 0.03 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000397581 0.000346847 0.0150194 0.0132722 -1 -1 -1 -1 54 378 8 1.07788e+06 700622 -1 -1 0.15 0.0912923 0.077708 2680 3516 -1 377 4 186 272 12468 6162 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0121325 0.0114634 +x_uniform_y_delta.xml stereovision3.v common 3.83 odin 167.62 MiB 2.54 171648 -1 -1 4 0.12 -1 -1 33108 -1 -1 13 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67272 11 30 262 292 2 107 54 7 7 49 clb auto 26.4 MiB 0.07 616 423 2196 403 1708 85 65.7 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000402032 0.0003504 0.0118642 0.0105316 -1 -1 -1 -1 38 306 15 1.07788e+06 700622 -1 -1 0.15 0.0944893 0.0801165 2680 3516 -1 305 15 191 335 14110 6670 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.018365 0.0165829 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt index a4fce4cf22f..3cbac41fce1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 2.02 vpr 67.00 MiB 0.08 10496 -1 -1 4 0.20 -1 -1 36452 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68608 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.11 419 1815 318 1436 61 67.0 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000706488 0.000606458 0.0228093 0.0209659 -1 -1 -1 -1 8 283 18 1.07788e+06 1.02399e+06 -1 -1 0.38 0.186498 0.171178 2100 3116 -1 280 18 572 1139 59841 29637 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.0346595 0.0310733 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 2.04 vpr 66.32 MiB 0.07 10496 -1 -1 4 0.26 -1 -1 36580 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67916 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 428 1698 248 1401 49 66.3 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000764131 0.000648712 0.0183265 0.0161998 -1 -1 -1 -1 10 297 21 1.07788e+06 1.02399e+06 -1 -1 0.45 0.176554 0.15406 2100 3116 -1 286 18 539 1058 53794 27022 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.0402826 0.0356284 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.99 vpr 66.21 MiB 0.09 10368 -1 -1 4 0.24 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67800 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 447 1815 292 1481 42 66.2 MiB 0.07 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.00090328 0.000782565 0.0181809 0.0161296 -1 -1 -1 -1 16 296 17 1.07788e+06 1.02399e+06 -1 -1 0.25 0.115099 0.100427 2100 3116 -1 300 17 545 1102 57605 27890 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.12 0.01 -1 -1 0.00 0.0397962 0.0356125 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 3.96 odin 167.25 MiB 2.71 171264 -1 -1 4 0.12 -1 -1 33208 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 439 1981 340 1577 64 65.7 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000388075 0.000339041 0.00890656 0.00797424 -1 -1 -1 -1 8 310 17 1.07788e+06 1.07788e+06 -1 -1 0.15 0.0572597 0.0490883 2100 3116 -1 300 19 436 776 44386 23435 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.018872 0.0167477 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 4.23 odin 167.25 MiB 2.96 171264 -1 -1 4 0.13 -1 -1 33100 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67188 11 30 262 292 2 99 61 7 7 49 clb auto 26.2 MiB 0.05 688 420 1741 256 1424 61 65.6 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000396128 0.000345351 0.00833909 0.00744772 -1 -1 -1 -1 14 287 20 1.07788e+06 1.07788e+06 -1 -1 0.11 0.0588694 0.0501538 2100 3116 -1 283 20 516 944 48724 24190 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.04 0.00 -1 -1 0.00 0.0200585 0.0177613 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 3.74 odin 167.25 MiB 2.53 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67648 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 446 2341 306 1971 64 66.1 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000390978 0.000340979 0.0100418 0.00894967 -1 -1 -1 -1 16 306 15 1.07788e+06 1.07788e+06 -1 -1 0.10 0.0586835 0.0503287 2100 3116 -1 315 15 490 966 53909 27396 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0167801 0.0150028 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt index e6884fa004e..d1fcdc4c422 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 6.17 vpr 66.89 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36612 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68492 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.11 425 2283 406 1804 73 66.9 MiB 2.36 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.00076202 0.000633481 0.0213386 0.0169977 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 1.35 0.0886305 0.079884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 5.87 odin 167.62 MiB 2.55 171648 -1 -1 4 0.12 -1 -1 33104 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67040 11 30 262 292 2 99 61 7 7 49 clb auto 25.4 MiB 0.04 688 437 2341 384 1888 69 65.5 MiB 1.26 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.00040053 0.000347422 0.0103465 0.00915139 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.64 0.0330431 0.0289561 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt index b4a9052cd04..931ceee65ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 2.01 vpr 61.71 MiB 0.06 10112 -1 -1 4 0.22 -1 -1 36708 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63196 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 442 4182 3410 664 108 61.7 MiB 0.07 0.00 2.55648 -171.707 -2.55648 2.31607 0.04 0.000697499 0.000590032 0.035108 0.0301305 -1 -1 -1 -1 36 688 16 862304 700622 64877.6 1802.15 0.32 0.199199 0.171554 2900 12076 -1 568 12 312 493 15436 6065 2.62572 2.28031 -177.78 -2.62572 0 0 80896.3 2247.12 0.00 0.04 0.02 -1 -1 0.00 0.0300653 0.0274931 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml stereovision3.v common 2.73 odin 151.50 MiB 1.45 155136 -1 -1 4 0.12 -1 -1 33076 -1 -1 13 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61812 11 30 262 292 2 107 54 6 6 36 clb auto 21.0 MiB 0.06 561 417 4182 3406 658 118 60.4 MiB 0.04 0.00 2.44705 2.32039 -170.792 -2.32039 2.20653 0.01 0.000401205 0.0003469 0.019576 0.0171142 -1 -1 -1 -1 36 788 25 862304 700622 64877.6 1802.15 0.19 0.107302 0.0903116 2900 12076 -1 552 14 362 618 15589 5868 2.33898 2.20362 -179.305 -2.33898 0 0 80896.3 2247.12 0.00 0.02 0.01 -1 -1 0.00 0.0188673 0.0170516 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt index 8d2903c2d48..a50dd42d5d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 18.17 vpr 71.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72740 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.53 10472 141533 36950 100839 3744 71.0 MiB 1.46 0.02 7.46482 -1369.01 -7.46482 7.46482 0.64 0.00605549 0.00528423 0.429203 0.364085 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.91 2.29628 1.96589 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.03 0.83 0.15 -1 -1 0.03 0.252853 0.225541 - k4_N4_90nm.xml ex5p.blif common 20.35 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68624 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.32 12004 99857 28319 69545 1993 67.0 MiB 1.07 0.02 6.86459 -313.968 -6.86459 nan 0.52 0.0035933 0.00315668 0.2475 0.211473 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 14.36 0.89434 0.759948 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.08 1.43 0.30 -1 -1 0.08 0.237816 0.212077 - k4_N4_90nm.xml s298.blif common 19.44 vpr 73.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74984 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.0 MiB 0.49 13813 156389 45768 109723 898 73.2 MiB 1.80 0.03 12.2682 -96.384 -12.2682 12.2682 0.93 0.0106993 0.00945176 0.491739 0.389383 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 10.93 1.63745 1.34189 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.10 1.48 0.31 -1 -1 0.10 0.297955 0.263351 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml diffeq.blif common 4.83 vpr 71.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73060 64 39 1935 1974 1 1075 542 23 23 529 clb auto 31.1 MiB 0.17 24088 10407 135291 36283 95683 3325 71.3 MiB 0.54 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.20 0.00206649 0.00175858 0.139723 0.120994 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.40 0.433146 0.377372 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.30 0.07 -1 -1 0.02 0.0892118 0.0808294 +k4_N4_90nm.xml ex5p.blif common 6.43 vpr 66.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67716 8 63 1072 1135 0 892 433 22 22 484 clb auto 26.3 MiB 0.13 20089 11891 97016 28068 66779 2169 66.1 MiB 0.40 0.01 11.9965 7.14697 -323.69 -7.14697 nan 0.18 0.00134043 0.00119147 0.0897746 0.080448 -1 -1 -1 -1 32 16897 50 891726 807012 949946. 1962.70 4.19 0.334258 0.292305 43920 162796 -1 13798 21 8357 30046 2938323 715872 6.93884 nan -322.607 -6.93884 0 0 1.22393e+06 2528.78 0.04 0.44 0.09 -1 -1 0.04 0.0716204 0.0648027 +k4_N4_90nm.xml s298.blif common 8.54 vpr 73.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 579 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74816 4 6 1942 1948 1 1135 589 27 27 729 clb auto 33.1 MiB 0.18 26761 13173 158541 45950 111660 931 73.1 MiB 0.66 0.01 27.8284 12.5893 -95.8017 -12.5893 12.5893 0.28 0.00244424 0.00207476 0.168219 0.145073 -1 -1 -1 -1 24 18368 39 1.39333e+06 1.29078e+06 1.12265e+06 1539.99 5.30 0.547643 0.470994 54650 192211 -1 15957 20 8308 43971 3554658 708435 12.1943 12.1943 -92.9601 -12.1943 0 0 1.47093e+06 2017.74 0.02 0.60 0.11 -1 -1 0.02 0.121878 0.109788 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt index 4db936a1dd3..542dfe84888 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.78 vpr 69.28 MiB 0.09 10496 -1 -1 5 0.19 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70944 11 30 313 321 2 114 55 7 7 49 clb auto 29.8 MiB 0.39 459 2031 574 1374 83 69.3 MiB 0.03 0.00 4.6413 0 0 4.31525 0.00 0.000635584 0.000552586 0.0173645 0.0155707 -1 -1 -1 -1 570 5.27778 228 2.11111 239 439 10467 3202 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 69.3 MiB 0.14 0.147679 0.140851 69.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 4.04 odin 157.12 MiB 2.89 160896 -1 -1 5 0.11 -1 -1 33304 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69500 11 30 313 321 2 115 55 7 7 49 clb auto 28.6 MiB 0.17 671 430 3071 674 1846 551 67.9 MiB 0.03 0.00 4.73611 4.6413 0 0 4.32062 0.00 0.000385155 0.000350825 0.0148038 0.0136631 -1 -1 -1 -1 568 5.21101 230 2.11009 310 604 14151 4248 1.07788e+06 754516 219490. 4479.39 9 5100 32136 -1 4.69675 4.35776 0 0 -164.736 -1.707 0.02 -1 -1 67.9 MiB 0.08 0.0926108 0.0891897 67.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt index 19fe5d4556f..bcb0b5d161b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt index 8285cf5d7b5..2a360b9ec50 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 2.66 vpr 68.27 MiB 0.06 9984 -1 -1 3 0.36 -1 -1 39780 -1 -1 66 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69908 99 130 363 493 1 250 296 12 12 144 clb auto 29.2 MiB 0.21 805 57484 15208 21002 21274 68.3 MiB 0.11 0.00 40 1774 10 5.66058e+06 4.105e+06 360333. 2502.31 0.52 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 4.11 odin 100.88 MiB 2.60 103296 -1 -1 3 0.20 -1 -1 34072 -1 -1 66 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67788 99 130 363 493 1 256 296 12 12 144 clb auto 26.8 MiB 0.09 2010 809 75232 21521 28755 24956 66.2 MiB 0.06 0.00 48 1681 14 5.66058e+06 4.105e+06 424682. 2949.18 0.24 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt index 735a18dab2b..0b6e20be258 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.45 vpr 66.93 MiB 0.09 10368 -1 -1 4 0.22 -1 -1 36756 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68532 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00571426 0.00556672 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.38 odin 167.25 MiB 2.52 171264 -1 -1 4 0.12 -1 -1 33292 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 11 30 262 292 2 99 61 7 7 49 clb auto 25.3 MiB 0.04 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00122021 0.00115346 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt index 402ade22624..630005b88fb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.29 vpr 66.33 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36632 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67920 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.05 0.000892007 0.00076546 0.0179963 0.0157273 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0202445 0.0178347 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.62 odin 167.25 MiB 2.66 171264 -1 -1 4 0.12 -1 -1 33108 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 430 2821 451 2299 71 65.7 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000405286 0.000352219 0.0118962 0.0104836 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0130883 0.0116044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt index 8bf865796ba..93796b474f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 0.57 vpr 60.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62456 11 11 59 70 0 48 26 4 4 16 clb auto 22.0 MiB 0.04 179 862 260 602 0 61.0 MiB 0.01 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000234107 0.000208327 0.0069198 0.00625105 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.10 0.0507337 0.0443992 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.02 0.00 -1 -1 0.00 0.0119559 0.010883 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.07 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23940 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml mult_5x6.blif common 0.38 vpr 59.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61048 11 11 59 70 0 48 26 4 4 16 clb auto 20.2 MiB 0.02 205 178 672 211 461 0 59.6 MiB 0.01 0.00 2.48509 2.46139 -19.889 -2.46139 nan 0.00 0.000113648 0.000103358 0.00299057 0.00277639 -1 -1 -1 -1 30 215 23 215576 215576 18771.3 1173.21 0.04 0.0197788 0.0170591 1016 3020 -1 186 15 222 505 8959 4790 2.75695 nan -23.0631 -2.75695 0 0 22855.5 1428.47 0.00 0.01 0.00 -1 -1 0.00 0.00593139 0.0053815 +k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 vpr 21.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 21872 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt index af7706738c0..60a3dab3584 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.24 vpr 64.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66340 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.8 MiB 0.01 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 6.4699e-05 4.5848e-05 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common 0.16 vpr 63.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64788 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 24 21 30 9 19 2 63.3 MiB 0.00 0.00 0.739166 0.646042 -3.51892 -0.646042 0.571 0.00 2.3495e-05 1.6333e-05 0.000928287 0.000887308 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000928287 0.000887308 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt index 25609b75a68..b70afe597bd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 40.74 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.79 0.000585035 0.000506509 0.0125856 0.0113967 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.17 0.202681 0.177336 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.09 0.08 -1 -1 0.01 0.0322374 0.0298184 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 42.57 vpr 978.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001668 10 10 168 178 1 68 30 11 8 88 io auto 955.1 MiB 0.58 356 628 86 501 41 978.2 MiB 0.08 0.00 6.32784 -69.1369 -6.32784 6.32784 2.79 0.00106817 0.000941606 0.0173949 0.0157097 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.41 0.24274 0.212439 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.08 0.08 -1 -1 0.01 0.0393492 0.0368597 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 41.18 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.77 378 628 92 504 32 978.5 MiB 0.06 0.00 6.37842 -68.9795 -6.37842 6.37842 3.93 0.000461318 0.000398366 0.0135017 0.0123478 -1 -1 -1 -1 30 740 27 0 0 144567. 1642.81 1.27 0.212409 0.18717 11730 32605 -1 579 10 219 802 50034 22946 6.80801 6.80801 -73.0986 -6.80801 0 0 194014. 2204.70 0.01 0.06 0.10 -1 -1 0.01 0.0272644 0.0255028 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 43.49 vpr 978.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002044 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.67 353 582 71 475 36 978.6 MiB 0.10 0.00 6.2342 -69.2052 -6.2342 6.2342 4.26 0.00126519 0.00120018 0.0174025 0.0162066 -1 -1 -1 -1 22 762 19 0 0 110609. 1256.92 0.57 0.121021 0.108951 11258 24748 -1 710 14 413 1547 91286 47129 6.80216 6.80216 -76.023 -6.80216 0 0 134428. 1527.59 0.01 0.08 0.05 -1 -1 0.01 0.0301878 0.0279201 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 22.09 vpr 980.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003660 10 10 168 178 1 65 30 11 8 88 io auto 953.7 MiB 0.32 530 354 766 109 603 54 980.1 MiB 0.05 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 0.98 0.00031125 0.000282067 0.00812631 0.00755584 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.28 0.0526186 0.0466377 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0174048 0.0160478 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 22.04 vpr 980.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003680 10 10 168 178 1 65 30 11 8 88 io auto 953.7 MiB 0.32 530 359 766 97 619 50 980.2 MiB 0.05 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 0.99 0.000319106 0.000291575 0.0081832 0.0076106 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0523685 0.0465314 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0173368 0.0159174 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 22.55 vpr 980.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003972 10 10 168 178 1 65 30 11 8 88 io auto 954.0 MiB 0.32 530 349 674 94 530 50 980.4 MiB 0.05 0.00 6.77016 6.47558 -68.8469 -6.47558 6.47558 1.38 0.000298307 0.000270422 0.00750644 0.00701996 -1 -1 -1 -1 20 861 19 0 0 100248. 1139.18 0.29 0.050198 0.0445509 11180 23751 -1 680 16 330 1259 70362 36922 6.87801 6.87801 -76.1492 -6.87801 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0169506 0.0156205 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 22.55 vpr 979.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003392 10 10 168 178 1 65 30 11 8 88 io auto 953.4 MiB 0.33 530 348 720 100 579 41 979.9 MiB 0.05 0.00 6.77016 6.34606 -69.0457 -6.34606 6.34606 1.41 0.000302169 0.000275003 0.00785604 0.00733066 -1 -1 -1 -1 20 851 21 0 0 100248. 1139.18 0.27 0.0516757 0.0458386 11180 23751 -1 743 16 380 1503 81107 41070 6.53785 6.53785 -75.082 -6.53785 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0170992 0.0157992 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt index de612c1c661..ee5d462d98b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 41.99 vpr 978.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001688 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.85 385 628 76 517 35 978.2 MiB 0.09 0.00 6.37842 -68.9926 -6.37842 6.37842 2.49 0.000740479 0.000647957 0.0145497 0.0133659 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.45 0.22055 0.192568 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.11 0.10 -1 -1 0.01 0.0358167 0.033477 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 41.03 vpr 978.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001836 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.66 356 628 86 501 41 978.4 MiB 0.10 0.00 6.32784 -69.1369 -6.32784 6.32784 2.55 0.000491141 0.000429611 0.0148781 0.0136279 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.47 0.229896 0.203057 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.11 0.09 -1 -1 0.01 0.0316333 0.0293122 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 22.15 vpr 979.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003264 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.33 530 354 766 109 603 54 979.8 MiB 0.05 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 0.97 0.000321472 0.000271532 0.00806108 0.00747147 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.28 0.05278 0.0466501 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0173118 0.0159829 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 22.13 vpr 979.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003148 10 10 168 178 1 65 30 11 8 88 io auto 953.4 MiB 0.32 530 359 766 97 619 50 979.6 MiB 0.06 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 0.99 0.000295946 0.000268265 0.00820091 0.00762383 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0515235 0.045775 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0174113 0.0159753 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt index be79764ceb1..fa723315ce7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.26 vpr 76.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78288 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.83 6246 12245 2336 8854 1055 76.5 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.27 0.00393519 0.00333322 0.167205 0.141172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.170495 0.143929 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.34 vpr 76.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78408 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.32 6248 12409 2316 9051 1042 76.6 MiB 0.27 0.01 5.00015 -217.921 -5.00015 nan 0.18 0.00183948 0.00156955 0.109821 0.0973753 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.11472 0.101715 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 6.81 vpr 76.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78560 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.45 6557 16051 3559 11939 553 76.7 MiB 0.47 0.01 5.39652 -231.823 -5.39652 nan 1.67 0.00368316 0.00300979 0.191413 0.165252 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.196386 0.169658 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.69 vpr 76.65 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78492 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.4 MiB 2.51 6642 53385 10847 39555 2983 76.7 MiB 1.06 0.02 5.30857 -236.309 -5.30857 nan 1.91 0.00201874 0.00161249 0.24975 0.219272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.258981 0.227848 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml ex5p.blif common_--place_effort_scaling_circuit 1.80 vpr 75.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77676 8 63 1072 1135 0 611 133 11 11 121 clb auto 35.8 MiB 1.19 7518 6082 8947 1533 6815 599 75.9 MiB 0.13 0.00 5.94011 5.07653 -213.869 -5.07653 nan 0.08 0.00138085 0.00120833 0.0557598 0.0510581 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.058042 0.0530968 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 1.84 vpr 75.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77592 8 63 1072 1135 0 611 133 11 11 121 clb auto 36.1 MiB 1.21 7518 6142 9355 1631 7067 657 75.8 MiB 0.15 0.00 5.94011 4.97625 -208.188 -4.97625 nan 0.08 0.00138735 0.00121011 0.0616278 0.0561673 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0639105 0.0582109 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 3.02 vpr 75.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77316 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.8 MiB 1.16 17047 6704 22507 6724 13850 1933 75.5 MiB 0.27 0.00 9.03576 5.62812 -248.555 -5.62812 nan 0.63 0.00138573 0.00121317 0.11031 0.0991692 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.112545 0.10117 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 3.29 vpr 75.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77316 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.8 MiB 1.17 17047 6681 64488 18508 41026 4954 75.5 MiB 0.52 0.01 9.03576 5.51074 -242.103 -5.51074 nan 0.64 0.00137865 0.00122309 0.103759 0.0934135 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.105985 0.0954026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt index b0056cc1abc..3c0cb5f8c63 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.86 vpr 66.93 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68536 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.9 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.00072366 0.000614909 0.0157761 0.0136171 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.27 0.140412 0.11741 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.06 0.01 -1 -1 0.00 0.0578011 0.0529737 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.92 odin 167.25 MiB 2.63 171264 -1 -1 4 0.12 -1 -1 33088 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67040 11 30 262 292 2 99 61 7 7 49 clb auto 25.8 MiB 0.04 688 430 2821 451 2299 71 65.5 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000396362 0.000343176 0.0120084 0.0105776 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.18 0.073831 0.0622022 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0227802 0.0197882 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt index c15f8828261..cd20352a239 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.38 vpr 62.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 33172 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4078e-05 8.305e-06 7.897e-05 5.195e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00158662 0.00151514 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.40 vpr 62.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 32980 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1945e-05 6.486e-06 7.545e-05 4.8841e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00148797 0.00142035 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.44 vpr 62.59 MiB -1 -1 -1 -1 0 0.02 -1 -1 32992 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64096 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 2.0091e-05 1.2082e-05 0.000201085 0.000162772 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00181183 0.00172223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.43 vpr 62.71 MiB -1 -1 -1 -1 0 0.02 -1 -1 33076 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.7 MiB 0.00 0.00 nan 0 0 nan 0.00 1.9557e-05 1.1746e-05 0.00010411 6.6917e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.0019441 0.00185632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.39 vpr 62.59 MiB -1 -1 -1 -1 1 0.02 -1 -1 33300 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 2 1 3 4 0 3 4 3 3 9 -1 auto 24.3 MiB 0.00 9 9 5 0 4 62.6 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.6008e-05 1.0878e-05 0.0001005 7.3545e-05 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.00 0.00172772 0.00159734 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.62 vpr 62.37 MiB -1 -1 -1 -1 2 0.06 -1 -1 35272 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63864 5 1 7 8 0 7 7 3 3 9 -1 auto 24.0 MiB 0.00 20 18 12 0 6 62.4 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4824e-05 1.9123e-05 0.000151781 0.000121494 -1 -1 -1 -1 -1 8 6 3900 3900 7855.82 872.868 0.00 0.00207121 0.00193926 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.55 vpr 62.58 MiB -1 -1 -1 -1 2 0.06 -1 -1 35192 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64080 5 1 7 8 0 7 7 3 3 9 -1 auto 24.2 MiB 0.00 20 18 13 0 5 62.6 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4985e-05 1.9224e-05 0.000155624 0.000125459 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.002084 0.00190667 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.39 vpr 62.40 MiB -1 -1 -1 -1 1 0.02 -1 -1 33452 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63896 3 1 5 6 1 4 5 3 3 9 -1 auto 24.0 MiB 0.01 9 12 9 0 3 62.4 MiB 0.00 0.00 0.274843 -0.536407 -0.274843 0.274843 0.00 2.7938e-05 2.0741e-05 0.000161269 0.000123343 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.00690521 0.00673198 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.54 vpr 62.71 MiB -1 -1 -1 -1 1 0.06 -1 -1 35264 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 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release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62644 5 1 7 8 0 7 7 3 3 9 -1 auto 22.5 MiB 0.00 20 20 18 13 0 5 61.2 MiB 0.00 0.00 0.70303 0.70303 -0.70303 -0.70303 nan 0.00 1.2562e-05 9.128e-06 0.000100257 8.0833e-05 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.00112653 0.00101108 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.32 vpr 61.18 MiB -1 -1 -1 -1 1 0.02 -1 -1 29972 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62644 3 1 5 6 1 4 5 3 3 9 -1 auto 22.5 MiB 0.00 9 9 12 9 0 3 61.2 MiB 0.00 0.00 0.274843 0.274843 -0.536407 -0.274843 0.274843 0.00 1.6058e-05 1.2667e-05 8.7915e-05 6.761e-05 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.00110022 0.000978035 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.41 vpr 61.18 MiB -1 -1 -1 -1 1 0.03 -1 -1 31808 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62648 4 1 4 6 0 4 6 3 3 9 -1 auto 22.6 MiB 0.00 12 12 15 11 0 4 61.2 MiB 0.00 0.00 0.443777 0.443777 -0.443777 -0.443777 nan 0.00 1.0319e-05 6.951e-06 7.5732e-05 5.7277e-05 -1 -1 -1 -1 -1 7 16 3900 3900 7855.82 872.868 0.00 0.00115846 0.00103589 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.40 vpr 61.18 MiB -1 -1 -1 -1 1 0.03 -1 -1 31872 -1 -1 1 4 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62644 4 4 8 12 0 8 9 3 3 9 -1 auto 22.9 MiB 0.00 25 25 27 23 0 4 61.2 MiB 0.00 0.00 0.443777 0.443777 -1.77511 -0.443777 nan 0.00 1.7573e-05 1.3738e-05 0.000134702 0.000112478 -1 -1 -1 -1 -1 30 13 3900 3900 7855.82 872.868 0.00 0.00139893 0.00124994 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.41 vpr 61.21 MiB -1 -1 -1 -1 3 0.04 -1 -1 32352 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62680 6 6 28 34 0 28 15 5 5 25 clb auto 22.5 MiB 0.00 113 107 51 16 35 0 61.2 MiB 0.00 0.00 1.19848 1.19848 -5.43061 -1.19848 nan 0.00 4.9548e-05 4.359e-05 0.000386615 0.000355713 -1 -1 -1 -1 -1 190 16 23400 11700 33739.5 1349.58 0.01 0.00300051 0.00265436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.45 vpr 61.29 MiB -1 -1 -1 -1 4 0.04 -1 -1 32088 -1 -1 5 7 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62760 7 8 39 47 0 39 20 5 5 25 clb auto 22.9 MiB 0.01 182 166 236 59 163 14 61.3 MiB 0.00 0.00 1.48602 1.46514 -7.47508 -1.46514 nan 0.00 6.7215e-05 5.9185e-05 0.00094307 0.000857338 -1 -1 -1 -1 -1 326 19 23400 19500 33739.5 1349.58 0.02 0.00469121 0.0041336 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.46 vpr 61.34 MiB -1 -1 -1 -1 8 0.05 -1 -1 32088 -1 -1 6 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62808 8 8 51 59 0 51 22 5 5 25 clb auto 22.7 MiB 0.01 241 211 352 90 254 8 61.3 MiB 0.00 0.00 2.56944 2.55689 -12.2592 -2.55689 nan 0.00 8.608e-05 7.7986e-05 0.0014657 0.0013411 -1 -1 -1 -1 -1 432 21 23400 23400 33739.5 1349.58 0.02 0.00627483 0.00552861 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.54 vpr 61.46 MiB -1 -1 -1 -1 7 0.06 -1 -1 32828 -1 -1 11 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62936 10 10 95 105 0 95 31 6 6 36 clb auto 22.3 MiB 0.01 521 440 511 77 404 30 61.5 MiB 0.01 0.00 2.69967 2.57044 -18.1695 -2.57044 nan 0.00 0.000151539 0.000138116 0.00236646 0.00218357 -1 -1 -1 -1 -1 938 24 165600 42900 61410.5 1705.85 0.05 0.0108678 0.00957908 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.55 vpr 61.65 MiB -1 -1 -1 -1 8 0.07 -1 -1 32920 -1 -1 11 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63132 11 11 94 105 0 94 33 6 6 36 clb auto 22.9 MiB 0.01 523 447 709 77 581 51 61.7 MiB 0.01 0.00 2.83651 2.78731 -20.9698 -2.78731 nan 0.00 0.000146348 0.000133771 0.00278277 0.00255985 -1 -1 -1 -1 -1 978 22 165600 42900 61410.5 1705.85 0.05 0.010858 0.00961707 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.38 vpr 60.83 MiB -1 -1 -1 -1 1 0.03 -1 -1 30680 -1 -1 1 3 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62288 3 2 5 7 0 5 6 3 3 9 -1 auto 22.2 MiB 0.00 15 15 15 11 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.887553 -0.443777 nan 0.00 1.209e-05 8.732e-06 9.1869e-05 7.2945e-05 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.00124012 0.00110096 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.38 vpr 61.18 MiB -1 -1 -1 -1 2 0.03 -1 -1 31868 -1 -1 1 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62648 5 3 9 12 0 9 9 3 3 9 -1 auto 22.5 MiB 0.00 26 26 27 24 0 3 61.2 MiB 0.00 0.00 0.70303 0.70303 -1.84984 -0.70303 nan 0.00 1.7006e-05 1.3134e-05 0.000130625 0.000109922 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.00148586 0.00131377 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.40 vpr 61.18 MiB -1 -1 -1 -1 3 0.03 -1 -1 31864 -1 -1 1 7 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62648 7 4 13 17 0 13 12 3 3 9 -1 auto 22.5 MiB 0.00 37 37 38 34 0 4 61.2 MiB 0.00 0.00 0.962283 0.962283 -3.07137 -0.962283 nan 0.00 2.1905e-05 1.7808e-05 0.000171216 0.000147331 -1 -1 -1 -1 -1 39 18 3900 3900 7855.82 872.868 0.00 0.00170731 0.00150491 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.41 vpr 61.19 MiB -1 -1 -1 -1 4 0.03 -1 -1 31864 -1 -1 1 9 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62656 9 5 17 22 0 17 15 3 3 9 -1 auto 22.9 MiB 0.00 48 48 51 43 0 8 61.2 MiB 0.00 0.00 1.22154 1.22154 -4.55216 -1.22154 nan 0.00 2.6838e-05 2.2089e-05 0.000214843 0.000189834 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.00 0.00202953 0.00177973 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.41 vpr 61.20 MiB -1 -1 -1 -1 4 0.03 -1 -1 31868 -1 -1 2 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62664 11 6 24 30 0 24 19 4 4 16 clb auto 22.5 MiB 0.00 96 81 219 61 139 19 61.2 MiB 0.00 0.00 1.37337 1.3375 -6.59285 -1.3375 nan 0.00 3.5886e-05 3.0342e-05 0.000510299 0.000442952 -1 -1 -1 -1 -1 131 14 7800 7800 17482.0 1092.63 0.01 0.00251022 0.00221932 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 1f6be016ab1..4ad63c55fd1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.79 vpr 67.81 MiB 0.06 9856 -1 -1 3 0.37 -1 -1 39772 -1 54808 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.13 821 70943 24958 34400 11585 67.8 MiB 0.24 0.00 2.51136 -219.195 -2.51136 2.51136 0.28 0.000896235 0.000803075 0.0731146 0.0664864 -1 -1 -1 -1 40 1499 25 5.66058e+06 4.21279e+06 333335. 2314.82 1.63 0.35542 0.319058 12666 64609 -1 1442 10 553 749 42115 14455 2.64494 2.64494 -235.699 -2.64494 0 0 419432. 2912.72 0.02 0.06 0.11 -1 -1 0.02 0.0374155 0.0350957 0.008441 0.2001 0.06777 0.7321 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 16.21 vpr 71.75 MiB 0.06 9856 -1 -1 15 0.50 -1 -1 38288 -1 56228 38 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73476 162 96 999 932 1 689 301 16 16 256 mult_36 auto 32.3 MiB 0.49 5426 96061 33445 54809 7807 71.8 MiB 1.03 0.02 21.3991 -1811.48 -21.3991 21.3991 0.51 0.00504368 0.00468153 0.493175 0.461597 -1 -1 -1 -1 56 11482 33 1.21132e+07 4.02797e+06 870502. 3400.40 8.42 2.47741 2.31569 26504 172068 -1 9223 22 3083 6041 811453 269172 22.8885 22.8885 -1951.66 -22.8885 0 0 1.11200e+06 4343.75 0.07 0.47 0.29 -1 -1 0.07 0.221232 0.208061 0.007874 0.3571 0.01689 0.626 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.21 odin 100.12 MiB 2.22 102528 -1 -1 3 0.20 -1 -1 34100 -1 52224 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68248 99 130 363 493 1 251 298 12 12 144 clb auto 27.9 MiB 0.07 2086 873 75918 23929 39390 12599 66.6 MiB 0.13 0.00 2.81842 2.17528 -220.25 -2.17528 2.17528 0.09 0.00057296 0.000536541 0.045254 0.042348 -1 -1 -1 -1 32 1783 21 5.66058e+06 4.21279e+06 281316. 1953.58 0.21 0.115911 0.106856 11950 52952 -1 1569 8 475 592 37949 12971 2.62567 2.62567 -236.989 -2.62567 0 0 345702. 2400.71 0.01 0.02 0.03 -1 -1 0.01 0.0148651 0.0139996 0.008359 0.1947 0.06177 0.7435 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.33 odin 87.38 MiB 2.02 89472 -1 -1 15 0.28 -1 -1 34648 -1 54320 39 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72896 162 96 999 932 1 692 302 16 16 256 mult_36 auto 31.6 MiB 0.22 9298 5609 93406 28941 57235 7230 71.2 MiB 0.37 0.01 25.0935 21.2697 -1792.21 -21.2697 21.2697 0.17 0.00167786 0.00157594 0.166256 0.156124 -1 -1 -1 -1 42 13435 49 1.21132e+07 4.08187e+06 666210. 2602.38 1.63 0.455209 0.425126 24208 131534 -1 10212 18 3382 6827 1034510 307036 22.5724 22.5724 -1934.15 -22.5724 0 0 835850. 3265.04 0.02 0.20 0.07 -1 -1 0.02 0.0801778 0.0759457 0.00765 0.3347 0.01582 0.6495 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt index d6f9144a21f..91c650b7642 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 66.34 MiB 0.08 10496 -1 -1 4 0.22 -1 -1 36740 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.07 425 2283 406 1804 73 66.3 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000792071 0.00065667 0.0233552 0.0207856 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.3 MiB 0.07 0.0694098 0.0624777 66.3 MiB -1 0.01 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.84 vpr 69.28 MiB 0.07 10496 -1 -1 5 0.19 -1 -1 36360 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70940 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.48 448 1927 352 1502 73 69.3 MiB 0.05 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.00080657 0.000690329 0.0283624 0.0258806 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.06 -1 -1 69.3 MiB 0.04 0.0633117 0.0585851 69.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.89 odin 167.25 MiB 2.94 171264 -1 -1 4 0.12 -1 -1 33084 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.00039432 0.000341138 0.0102726 0.00907409 -1 -1 -1 -1 434 4.56842 177 1.86316 730 1655 64750 15779 1.07788e+06 1.07788e+06 207176. 4228.08 23 4440 29880 -1 2.44651 2.32748 -175.142 -2.44651 0 0 0.02 -1 -1 65.7 MiB 0.03 0.0322281 0.0281216 65.7 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.73 odin 156.75 MiB 2.62 160512 -1 -1 5 0.11 -1 -1 33288 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69568 11 30 313 321 2 114 55 7 7 49 clb auto 28.6 MiB 0.19 671 455 1719 301 1356 62 67.9 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000431787 0.000378246 0.0113226 0.0102357 -1 -1 -1 -1 571 5.28704 218 2.01852 192 380 9910 2908 1.07788e+06 754516 219490. 4479.39 12 5100 32136 -1 2.66069 2.29553 -166.559 -2.66069 0 0 0.02 -1 -1 67.9 MiB 0.02 0.031952 0.0291815 67.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt index 9c4fd28b84b..ced6ee7cc83 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 29.83 vpr 86.25 MiB 0.45 29568 -1 -1 4 2.98 -1 -1 43168 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88324 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.0 MiB 2.27 10985 240245 81936 130873 27436 86.3 MiB 2.86 0.03 4.42447 -2617.73 -4.42447 4.42447 0.89 0.00871072 0.007701 1.03653 0.893245 -1 -1 -1 -1 78 21148 33 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 13.92 4.09327 3.61448 52874 439520 -1 19015 17 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.98 0.77 -1 -1 0.19 0.584807 0.525478 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 21.80 odin 1.01 GiB 10.99 1063152 -1 -1 4 1.51 -1 -1 40168 -1 -1 165 193 5 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87924 193 205 2863 2789 1 1378 568 20 20 400 memory auto 45.9 MiB 1.01 22943 10817 247423 86121 133897 27405 85.9 MiB 1.12 0.01 6.47551 5.02579 -2678.97 -5.02579 5.02579 0.32 0.00374808 0.00338021 0.423272 0.380582 -1 -1 -1 -1 76 21112 34 2.07112e+07 1.16325e+07 2.02110e+06 5052.76 3.91 1.38132 1.25049 52074 423490 -1 19105 17 5044 13854 1088699 242536 5.48145 5.48145 -2895.27 -5.48145 -14.3689 -0.360359 2.51807e+06 6295.18 0.07 0.33 0.24 -1 -1 0.07 0.214376 0.201156 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt index 812f4d3bdb5..63f396f9727 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.96 vpr 71.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73224 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.52 4992 14048 2664 10357 1027 71.5 MiB 0.35 0.02 4.19211 -186.67 -4.19211 nan 0.00 0.00713555 0.00269028 0.139755 0.114328 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.22 -1 -1 71.5 MiB 0.32 0.294582 0.254721 71.5 MiB -1 0.05 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.24 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73336 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.64 4992 14048 2664 10357 1027 71.6 MiB 0.33 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00345084 0.002875 0.154792 0.13937 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.26 -1 -1 71.6 MiB 0.37 0.334856 0.303047 71.6 MiB -1 0.08 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 0.96 vpr 70.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71996 8 63 748 811 0 451 161 14 14 196 clb auto 31.2 MiB 0.24 7035 5048 13708 2494 10216 998 70.3 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.0012361 0.00107738 0.0505529 0.0454928 -1 -1 -1 -1 6826 15.1353 1836 4.07095 3768 15421 585680 92261 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17836 nan -185.935 -4.17836 0 0 0.08 -1 -1 70.3 MiB 0.19 0.141694 0.128755 70.3 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 0.91 vpr 69.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71608 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7035 5048 13708 2494 10216 998 69.9 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.00117606 0.00102769 0.0494933 0.0444045 -1 -1 -1 -1 6906 15.3126 1853 4.10865 3897 16323 609528 97595 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17947 nan -185.454 -4.17947 0 0 0.08 -1 -1 69.9 MiB 0.16 0.127311 0.115445 69.9 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt index ca94c478175..a43902b89ef 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.33 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.53 4993 17086 3593 12286 1207 71.5 MiB 0.39 0.01 3.65588 -160.421 -3.65588 nan 0.05 0.00324947 0.00265148 0.171741 0.145172 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.19 -1 -1 71.5 MiB 0.65 0.403427 0.354208 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.06 vpr 71.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72900 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.61 4933 15350 2970 11325 1055 71.2 MiB 0.33 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00354772 0.00306723 0.134491 0.114487 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.2 MiB 0.37 0.342443 0.304101 71.2 MiB -1 0.04 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 4.12 vpr 71.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73084 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.46 5048 17520 3917 12196 1407 71.4 MiB 0.41 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.0055915 0.00450451 0.174816 0.150375 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.22 -1 -1 71.4 MiB 0.70 0.438594 0.389856 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.79 vpr 71.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73092 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.34 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00371073 0.00310746 0.151921 0.128885 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.16 -1 -1 71.4 MiB 0.65 0.390878 0.342895 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.01 vpr 70.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72112 8 63 748 811 0 451 161 14 14 196 clb auto 31.2 MiB 0.23 7019 5149 19389 4557 13188 1644 70.4 MiB 0.16 0.00 5.27085 3.74489 -168.03 -3.74489 nan 0.02 0.00126033 0.00109349 0.0665406 0.0595916 -1 -1 -1 -1 7151 15.8559 1918 4.25277 4270 17535 1282134 224677 9.20055e+06 4.85046e+06 701736. 3580.29 23 16332 105598 -1 4.37015 nan -196.64 -4.37015 0 0 0.06 -1 -1 70.4 MiB 0.22 0.146899 0.133127 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 0.92 vpr 69.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71600 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7019 5029 15019 2779 11014 1226 69.9 MiB 0.13 0.00 5.64572 4.2713 -188.25 -4.2713 nan 0.00 0.00124937 0.00108276 0.0545594 0.0488954 -1 -1 -1 -1 7035 15.5987 1894 4.19956 3783 16134 598321 102284 9.20055e+06 4.85046e+06 701736. 3580.29 20 16332 105598 -1 4.48059 nan -193.333 -4.48059 0 0 0.06 -1 -1 69.9 MiB 0.19 0.141965 0.128041 69.9 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 1.71 vpr 70.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71984 8 63 748 811 0 451 161 14 14 196 clb auto 31.2 MiB 0.24 7019 5066 19826 4740 13454 1632 70.3 MiB 0.16 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00121598 0.00106627 0.0675193 0.0602983 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 70.3 MiB 0.22 0.145124 0.131162 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.68 vpr 70.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71980 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7019 5066 19826 4740 13454 1632 70.3 MiB 0.16 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00119569 0.00104348 0.0665483 0.0593856 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 70.3 MiB 0.22 0.143597 0.129548 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt index 73afad51c48..fecff9d091a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 2.09 vpr 71.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73036 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.3 MiB 0.32 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00299665 0.00251735 0.139481 0.119628 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.42 0.337391 0.298836 71.3 MiB -1 0.06 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.37 vpr 71.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73112 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.4 MiB 0.36 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00287338 0.00244407 0.145055 0.130505 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.23 -1 -1 71.4 MiB 0.57 0.403361 0.368877 71.4 MiB -1 0.07 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 0.93 vpr 69.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71600 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.24 7035 5098 13271 2309 10001 961 69.9 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00119598 0.00104626 0.0485432 0.0437081 -1 -1 -1 -1 7155 15.8647 1916 4.24834 4312 18456 674497 110334 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.9 MiB 0.18 0.128344 0.116744 69.9 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 0.91 vpr 70.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71984 8 63 748 811 0 451 161 14 14 196 clb auto 31.2 MiB 0.23 7035 5098 13271 2309 10001 961 70.3 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00124712 0.00108956 0.049401 0.0444125 -1 -1 -1 -1 7141 15.8337 1913 4.24168 4366 18775 685171 111801 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 70.3 MiB 0.17 0.12868 0.116884 70.3 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt index d51a6534507..d1a8675565f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 1.14 vpr 59.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61108 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 20.9 MiB 0.25 70 15 4 10 1 59.7 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000126011 0.000111009 0.000872338 0.000798258 -1 -1 -1 -1 25 262 18 133321 74067 -1 -1 0.48 0.0703731 0.0607281 1252 5405 -1 274 13 122 122 23159 13821 1.78919 1.78919 -18.223 -1.78919 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.00593831 0.00529293 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +slicem.xml carry_chain.blif common 0.55 vpr 58.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60200 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 19.9 MiB 0.14 70 70 15 4 10 1 58.8 MiB 0.00 0.00 0.552322 0.523836 -5.19346 -0.523836 0.523836 0.00 6.816e-05 6.1015e-05 0.000550461 0.000511682 -1 -1 -1 -1 27 337 26 133321 74067 -1 -1 0.09 0.0140307 0.0116797 1284 5874 -1 249 10 84 84 16544 9291 1.47622 1.47622 -16.7882 -1.47622 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00286435 0.00259865 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt index 2974b610be2..5dba66ce28c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.30 vpr 59.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60508 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.6 MiB 0.00 31 59 13 43 3 59.1 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.5462e-05 2.8363e-05 0.000299521 0.0002448 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00397217 0.00338578 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00197845 0.00188555 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml ndff.blif common 0.28 vpr 57.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58932 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.8 MiB 0.00 36 31 59 13 43 3 57.6 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8904e-05 1.4655e-05 0.00017596 0.000143236 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00219197 0.00184136 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00106544 0.00100507 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt index 936401071c3..b163155ac32 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.54 vpr 68.95 MiB 0.06 10496 -1 -1 5 0.18 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70604 11 30 313 321 2 114 55 7 7 49 clb auto 29.5 MiB 0.39 459 2031 574 1374 83 68.9 MiB 0.04 0.00 4.6413 0 0 4.31525 0.00 0.000717512 0.000626394 0.019463 0.0174272 -1 -1 -1 -1 569 5.26852 227 2.10185 207 393 9602 2945 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 68.9 MiB 0.06 0.0634405 0.0562085 68.9 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.58 odin 157.12 MiB 2.51 160896 -1 -1 5 0.11 -1 -1 33284 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69888 11 30 313 321 2 115 55 7 7 49 clb auto 28.4 MiB 0.17 671 430 3071 674 1846 551 68.2 MiB 0.03 0.00 4.73611 4.6413 0 0 4.32062 0.00 0.000379979 0.000346033 0.014831 0.0136619 -1 -1 -1 -1 573 5.25688 232 2.12844 279 564 13433 4035 1.07788e+06 754516 219490. 4479.39 9 5100 32136 -1 4.69675 4.35776 0 0 -164.736 -1.707 0.02 -1 -1 68.2 MiB 0.02 0.0309486 0.0287174 68.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index f1ae2610488..e9412340705 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.44 vpr 65.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66884 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.01 21 30 5 21 4 65.3 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.01 3.9163e-05 3.0734e-05 0.00023521 0.000191167 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00213897 0.00197887 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00188153 0.00176769 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.42 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66820 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.3 MiB 0.00 0.00 0.571 0 0 0.571 0.01 6.1332e-05 3.1443e-05 0.00028123 0.000216755 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00219985 0.00199813 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0028018 0.00269609 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.40 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66764 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 21 30 5 22 3 65.2 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.8778e-05 3.099e-05 0.000214053 0.000176854 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00219902 0.00204346 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00216696 0.00200612 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.40 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.3 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.3301e-05 3.3225e-05 0.000258104 0.000204952 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00214578 0.0019473 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00224405 0.00207678 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.38 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.4 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 5.0024e-05 3.2956e-05 0.000205951 0.000157313 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00254156 0.00219599 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0022282 0.00180897 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.40 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.00 21 30 5 23 2 65.4 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 5.2455e-05 4.3444e-05 0.00030806 0.000256078 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.01 0.00225516 0.00206503 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00187829 0.00175106 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.31 vpr 63.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 21 4 63.9 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 1.9532e-05 1.4985e-05 0.000133208 0.000107724 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.00115214 0.00105112 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00103168 0.000957693 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.33 vpr 63.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 5 3 11 14 2 9 10 4 4 16 clb auto 25.3 MiB 0.00 22 22 30 6 14 10 63.9 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.00 1.7929e-05 1.4042e-05 0.000128716 0.000105881 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00119508 0.00109064 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00110004 0.00102934 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.31 vpr 64.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 22 3 64.2 MiB 0.00 0.00 0.646297 0.646297 -2.19033 -0.646297 0.571 0.00 2.1502e-05 1.6408e-05 0.000150491 0.000121289 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00123245 0.00111483 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00112413 0.00104219 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.33 vpr 63.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65340 5 3 11 14 2 9 10 4 4 16 clb auto 25.2 MiB 0.00 22 21 30 7 16 7 63.8 MiB 0.00 0.00 1.64604 1.6463 -5.31965 -1.6463 0.571 0.00 2.3243e-05 1.7592e-05 0.000161496 0.000129112 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.00125222 0.00112683 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00115066 0.00105296 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.30 vpr 64.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 22 30 8 15 7 64.2 MiB 0.00 0.00 1.44967 1.44967 -2.9103 -1.44967 0.571 0.00 2.7152e-05 1.8078e-05 0.000163344 0.000129482 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.0014976 0.00130776 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00117943 0.00108545 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.33 vpr 63.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 23 2 63.9 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.1693e-05 1.7097e-05 0.000167017 0.000140121 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00122871 0.00112733 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00114705 0.00106508 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt index 5a4eb2784da..99931973f06 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.55 vpr 66.09 MiB 0.01 7168 -1 -1 1 0.03 -1 -1 33640 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67672 9 8 75 70 1 36 20 5 5 25 clb auto 27.1 MiB 0.69 94 695 228 460 7 66.1 MiB 0.01 0.00 2.48207 -26.1618 -2.48207 2.48207 0.03 0.000181733 0.000161557 0.00585234 0.0052913 -1 -1 -1 -1 52 134 15 151211 75605.7 63348.9 2533.96 0.11 0.0432562 0.0374575 2316 10503 -1 114 8 106 124 3566 1793 2.40307 2.40307 -27.5996 -2.40307 0 0 82390.3 3295.61 0.00 0.01 0.02 -1 -1 0.00 0.0069119 0.0064541 13 18 19 7 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.05 vpr 66.50 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33588 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68092 11 10 108 97 1 47 23 4 4 16 clb auto 27.2 MiB 3.14 125 439 123 270 46 66.5 MiB 0.01 0.00 3.45122 -41.5692 -3.45122 3.45122 0.01 0.000220655 0.000197533 0.0046684 0.00428671 -1 -1 -1 -1 30 238 26 50403.8 50403.8 19887.8 1242.99 0.18 0.0734016 0.0633094 992 2748 -1 177 19 176 222 5882 3651 3.90204 3.90204 -49.9067 -3.90204 0 0 24232.7 1514.54 0.00 0.02 0.00 -1 -1 0.00 0.013296 0.0120352 15 27 29 8 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 5.44 vpr 66.68 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33700 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68284 13 12 149 129 1 69 32 6 6 36 clb auto 27.4 MiB 4.03 199 682 229 444 9 66.7 MiB 0.02 0.00 3.51316 -53.1567 -3.51316 3.51316 0.06 0.000399911 0.000364812 0.00775114 0.00715794 -1 -1 -1 -1 40 438 24 403230 176413 88484.8 2457.91 0.50 0.147128 0.127344 3734 16003 -1 329 29 379 534 18280 7787 3.72931 3.72931 -57.4119 -3.72931 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0175574 0.0158074 25 38 42 9 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.95 vpr 66.76 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33776 -1 -1 6 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 15 14 196 165 1 93 35 5 5 25 clb auto 27.2 MiB 2.85 306 947 216 708 23 66.8 MiB 0.02 0.00 3.70693 -62.6491 -3.70693 3.70693 0.02 0.000376121 0.000333163 0.00931262 0.00852228 -1 -1 -1 -1 44 480 22 151211 151211 54748.7 2189.95 0.20 0.0954411 0.083284 2196 9177 -1 392 18 349 466 14859 7098 4.20858 4.20858 -72.9456 -4.20858 0 0 71025.7 2841.03 0.00 0.03 0.01 -1 -1 0.00 0.0211201 0.0192846 36 51 57 11 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.23 vpr 67.12 MiB 0.01 7040 -1 -1 1 0.06 -1 -1 33688 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68736 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 7.05 397 2054 481 1553 20 67.1 MiB 0.04 0.00 3.86806 -74.2346 -3.86806 3.86806 0.03 0.00048716 0.000431817 0.0193024 0.0173986 -1 -1 -1 -1 50 602 24 151211 126010 61632.8 2465.31 0.24 0.130358 0.114428 2268 9834 -1 534 19 619 1012 32161 14755 4.95834 4.95834 -93.7979 -4.95834 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0271021 0.0248239 44 66 75 13 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.18 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33916 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 19 18 308 249 1 137 45 6 6 36 clb auto 27.7 MiB 5.92 455 2365 460 1885 20 67.2 MiB 0.03 0.00 4.8546 -99.6039 -4.8546 4.8546 0.03 0.000494067 0.000457319 0.0145592 0.0132203 -1 -1 -1 -1 62 737 27 403230 201615 131137. 3642.71 0.40 0.139917 0.121866 4226 23319 -1 634 19 613 910 31131 12187 5.08188 5.08188 -101.573 -5.08188 0 0 160622. 4461.73 0.00 0.04 0.02 -1 -1 0.00 0.0328006 0.0301511 55 83 93 14 0 0 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 2.20 vpr 64.73 MiB 1.09 63360 -1 -1 1 0.02 -1 -1 30140 -1 -1 3 9 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 9 8 75 70 1 34 20 5 5 25 clb auto 25.9 MiB 0.35 123 90 614 218 387 9 64.7 MiB 0.01 0.00 2.48207 2.48207 -27.847 -2.48207 2.48207 0.01 9.1142e-05 8.2526e-05 0.00284948 0.00263576 -1 -1 -1 -1 44 151 38 151211 75605.7 54748.7 2189.95 0.07 0.0244535 0.0205798 2196 9177 -1 119 9 90 109 2746 1383 2.64007 2.64007 -30.0799 -2.64007 0 0 71025.7 2841.03 0.00 0.01 0.01 -1 -1 0.00 0.00398542 0.00370067 13 18 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 3.56 vpr 64.87 MiB 1.21 64512 -1 -1 1 0.02 -1 -1 30152 -1 -1 2 11 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66424 11 10 108 97 1 49 23 4 4 16 clb auto 25.6 MiB 1.61 144 130 311 98 183 30 64.9 MiB 0.01 0.00 3.45122 3.45122 -42.5068 -3.45122 3.45122 0.01 0.000122211 0.00011105 0.00236027 0.00222968 -1 -1 -1 -1 38 205 31 50403.8 50403.8 23356.0 1459.75 0.07 0.0310065 0.0263469 1064 3436 -1 155 11 118 137 3972 2416 3.45122 3.45122 -47.4838 -3.45122 0 0 29887.0 1867.94 0.00 0.01 0.00 -1 -1 0.00 0.0060327 0.00557363 15 27 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 4.85 vpr 65.21 MiB 1.19 64896 -1 -1 1 0.02 -1 -1 29976 -1 -1 7 13 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66780 13 12 149 129 1 68 32 6 6 36 clb auto 25.9 MiB 2.80 259 213 732 224 501 7 65.2 MiB 0.01 0.00 3.50789 3.50789 -53.116 -3.50789 3.50789 0.02 0.000156429 0.000142731 0.00389953 0.0036633 -1 -1 -1 -1 56 371 18 403230 176413 117789. 3271.93 0.11 0.0381154 0.0327749 4086 21443 -1 348 11 215 316 13445 5456 3.49231 3.49231 -56.5872 -3.49231 0 0 149557. 4154.36 0.00 0.01 0.01 -1 -1 0.00 0.00764244 0.0070994 25 38 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.35 vpr 65.61 MiB 1.06 64896 -1 -1 1 0.02 -1 -1 30188 -1 -1 7 15 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67184 15 14 196 165 1 92 36 6 6 36 clb auto 26.3 MiB 1.37 403 300 744 201 529 14 65.6 MiB 0.01 0.00 3.89713 3.62628 -64.1883 -3.62628 3.62628 0.02 0.000203778 0.000186501 0.00460964 0.00434602 -1 -1 -1 -1 36 756 35 403230 176413 82124.2 2281.23 0.15 0.0535333 0.0461786 3630 14583 -1 550 23 686 1034 36633 15919 4.66971 4.66971 -82.2718 -4.66971 0 0 100559. 2793.30 0.00 0.02 0.01 -1 -1 0.00 0.0134913 0.0122142 37 51 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 5.28 vpr 65.84 MiB 1.14 65664 -1 -1 1 0.03 -1 -1 30264 -1 -1 5 17 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67420 17 16 251 206 1 120 38 5 5 25 clb auto 25.9 MiB 3.23 489 407 2495 683 1791 21 65.8 MiB 0.02 0.00 3.91442 3.88071 -74.5105 -3.88071 3.88071 0.01 0.000246257 0.000225884 0.0123032 0.011433 -1 -1 -1 -1 50 657 26 151211 126010 61632.8 2465.31 0.13 0.0697365 0.0608136 2268 9834 -1 542 20 727 1123 36489 16871 4.71841 4.71841 -93.0154 -4.71841 0 0 77226.2 3089.05 0.00 0.02 0.01 -1 -1 0.00 0.0149146 0.0135832 45 66 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 5.52 vpr 65.22 MiB 1.10 66432 -1 -1 1 0.03 -1 -1 30340 -1 -1 7 19 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 19 18 308 249 1 134 44 6 6 36 clb auto 25.6 MiB 3.44 593 481 1815 377 1429 9 65.2 MiB 0.02 0.00 4.92231 4.8546 -99.9033 -4.8546 4.8546 0.02 0.000291676 0.00026758 0.00958251 0.00895714 -1 -1 -1 -1 68 826 27 403230 176413 143382. 3982.83 0.18 0.0751968 0.0658061 4366 25715 -1 720 17 520 914 34542 12871 4.61234 4.61234 -99.3851 -4.61234 0 0 176130. 4892.50 0.00 0.02 0.02 -1 -1 0.00 0.0164293 0.0151379 53 83 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt index 8a6305788b3..3046d61aebd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 17.34 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.93 4.894e-05 4.1022e-05 0.00272802 0.000370563 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00475066 0.00224296 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00235645 0.00226006 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common 4.55 vpr 57.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58916 6 7 19 26 0 19 26 3 3 9 -1 auto 19.4 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.82 2.1746e-05 1.7637e-05 0.000209106 0.000168705 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00145582 0.00132483 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00105587 0.000992599 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt index 518626ca870..792e122ceda 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.35 vpr 58.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60280 2 2 4 5 0 4 5 3 3 9 -1 auto 20.6 MiB 0.00 8 12 0 0 12 58.9 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7797e-05 1.2853e-05 0.000104532 7.7041e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.00210372 0.00170648 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.0014857 0.00144705 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +heterogeneous_tile.xml sub_tile_directs.blif common 0.28 vpr 56.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58116 2 2 4 5 0 4 5 3 3 9 -1 auto 18.4 MiB 0.00 8 8 12 0 0 12 56.8 MiB 0.00 0.00 1.899 1.899 -3.798 -1.899 nan 0.01 9.975e-06 6.727e-06 7.0576e-05 5.1334e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.00 0.00125353 0.00115577 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000874998 0.000839109 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt index 2adfcb2953c..06a46bcee1a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.13 vpr 66.94 MiB 0.07 9984 -1 -1 3 0.37 -1 -1 39768 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68544 99 74 307 381 1 199 193 8 8 64 io memory auto 27.3 MiB 0.07 869 22473 4565 15889 2019 66.9 MiB 0.09 0.00 2.15432 -215.614 -2.15432 2.15432 0.09 0.000919068 0.000833008 0.0321902 0.029066 -1 -1 -1 -1 32 1554 36 2.23746e+06 1.57199e+06 106908. 1670.44 0.41 0.172041 0.155343 4378 18911 -1 1152 12 699 1089 60199 20903 2.21433 2.21433 -220.084 -2.21433 0 0 130676. 2041.82 0.01 0.06 0.03 -1 -1 0.01 0.0316397 0.0293511 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.49 odin 99.75 MiB 2.08 102144 -1 -1 3 0.21 -1 -1 34100 -1 -1 19 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67276 99 74 307 381 1 197 193 8 8 64 io memory auto 25.6 MiB 0.03 1382 812 18574 3262 13483 1829 65.7 MiB 0.04 0.00 2.24422 2.11879 -214.824 -2.11879 2.11879 0.04 0.00043653 0.000403884 0.0169436 0.0157473 -1 -1 -1 -1 34 1407 30 2.23746e+06 1.57199e+06 111309. 1739.21 0.29 0.114174 0.102974 4442 19988 -1 1106 23 739 1099 89273 34816 2.38477 2.38477 -220.891 -2.38477 0 0 136889. 2138.88 0.00 0.04 0.01 -1 -1 0.00 0.0218706 0.0199682 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt index b4f05d4d127..67c1e31e1bc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 1.31 vpr 68.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70324 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.20 399 703 140 536 27 68.7 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000310541 0.000262563 0.00936798 0.00854482 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.46 0.175458 0.152388 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0280432 0.0256776 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.18 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70172 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.5 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000328824 0.000280405 0.00830952 0.00754823 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.31 0.10752 0.0932813 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0371511 0.0342602 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 4.10 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70728 10 10 168 178 1 162 111 14 14 196 clb auto 29.4 MiB 0.90 1467 5165 686 4267 212 69.1 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.39 0.000594399 0.00050939 0.0158932 0.0140866 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.204118 0.178235 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.04 0.10 0.10 -1 -1 0.04 0.0402804 0.0376719 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.27 vpr 68.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70312 10 10 168 178 1 75 33 7 7 49 clb auto 29.2 MiB 0.22 414 605 98 486 21 68.7 MiB 0.02 0.00 2.40687 -27.3475 -2.40687 2.40687 0.06 0.000598343 0.000517434 0.011833 0.0108149 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.28 0.112886 0.100348 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.05 0.02 -1 -1 0.00 0.0342617 0.0315172 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.32 vpr 68.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70636 10 10 168 178 1 163 124 14 14 196 clb auto 29.3 MiB 0.71 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.24 0.000341831 0.000287957 0.0139093 0.0123738 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.36 0.0484505 0.0438885 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.07 -1 -1 0.03 0.0262959 0.0240352 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.51 vpr 68.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70184 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000592996 0.000513744 0.0148871 0.0136124 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.60 0.233947 0.201424 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0337396 0.0309919 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.26 vpr 68.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69936 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.14 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000607215 0.000528624 0.0138198 0.0125584 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.45 0.178959 0.157093 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0299846 0.0274172 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 4.05 vpr 68.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70468 10 10 168 178 1 162 111 14 14 196 clb auto 29.3 MiB 0.89 1467 5165 686 4267 212 68.8 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.31 0.000662054 0.000579378 0.0167691 0.0149922 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.58 0.235946 0.204687 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.12 -1 -1 0.03 0.0296338 0.0273566 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.49 vpr 68.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69976 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.21 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000326035 0.000277526 0.0147842 0.0134826 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.61 0.214908 0.181228 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.02 -1 -1 0.00 0.0279877 0.0256826 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30628 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.7 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.11 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.11 vpr 30.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31020 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.11 vpr 30.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30716 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml styr.blif common_--target_ext_pin_util_1 0.71 vpr 67.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68820 10 10 168 178 1 75 32 6 6 36 clb auto 27.9 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.01 0.000307944 0.000276032 0.00676594 0.00627534 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0533675 0.0468966 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0175152 0.0161192 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.75 vpr 67.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68820 10 10 168 178 1 75 32 6 6 36 clb auto 27.5 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.00031604 0.000283289 0.00712143 0.00664783 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0548186 0.0483415 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.020456 0.018652 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.53 vpr 67.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69336 10 10 168 178 1 162 110 14 14 196 clb auto 28.0 MiB 0.43 2218 1472 5633 779 4632 222 67.7 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.15 0.000304349 0.000273692 0.0088502 0.00811274 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.27 0.0479021 0.0422392 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.02 0.03 0.04 -1 -1 0.02 0.013483 0.0124375 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.77 vpr 67.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68892 10 10 168 178 1 73 34 7 7 49 clb auto 27.5 MiB 0.13 556 403 749 133 594 22 67.3 MiB 0.01 0.00 2.47538 2.3678 -27.2356 -2.3678 2.3678 0.02 0.0003094 0.000282354 0.00717457 0.00670075 -1 -1 -1 -1 28 1121 29 1.07788e+06 754516 79600.7 1624.51 0.14 0.0552858 0.0488082 3864 14328 -1 1032 22 640 2278 94416 33063 2.98849 2.98849 -34.8096 -2.98849 0 0 95067.4 1940.15 0.00 0.04 0.01 -1 -1 0.00 0.0204833 0.0186535 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.53 vpr 67.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69248 10 10 168 178 1 163 124 14 14 196 clb auto 28.3 MiB 0.47 2325 1534 6922 992 5667 263 67.6 MiB 0.03 0.00 4.16044 3.06133 -37.5377 -3.06133 3.06133 0.16 0.000326442 0.000288594 0.0112173 0.010305 -1 -1 -1 -1 20 3156 16 9.20055e+06 5.60498e+06 295730. 1508.82 0.17 0.0294748 0.0269576 18004 60473 -1 3023 14 646 2892 171027 37325 3.649 3.649 -45.9039 -3.649 0 0 387483. 1976.95 0.01 0.04 0.03 -1 -1 0.01 0.0139433 0.0127176 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 0.71 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68816 10 10 168 178 1 75 32 6 6 36 clb auto 27.9 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000314617 0.000282107 0.00692448 0.00646733 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0534945 0.0471471 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0176284 0.0162169 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 0.69 vpr 66.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68176 10 10 168 178 1 75 32 6 6 36 clb auto 26.9 MiB 0.11 467 424 582 89 470 23 66.6 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.01 0.000305919 0.000274687 0.00679179 0.00634009 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0535061 0.0471986 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0175573 0.0161405 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 1.49 vpr 67.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69192 10 10 168 178 1 162 110 14 14 196 clb auto 28.3 MiB 0.41 2218 1472 5633 779 4632 222 67.6 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.15 0.000318412 0.000287457 0.00903161 0.00829414 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.26 0.0468353 0.0413059 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.01 0.03 0.04 -1 -1 0.01 0.0128862 0.0118738 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 0.71 vpr 67.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68824 10 10 168 178 1 75 32 6 6 36 clb auto 27.9 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.01 0.000318255 0.000286123 0.00690877 0.00645849 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0541523 0.0478013 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0177266 0.0163392 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 vpr 28.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28936 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.8 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 vpr 29.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 29704 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 28.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28964 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 28.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 29320 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.1 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt index 95f2081009b..97bcad685cb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 9.08 vpr 75.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77084 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.8 MiB 4.29 8858 177806 51921 111135 14750 75.3 MiB 1.45 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00692729 0.00619106 0.572476 0.497763 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.34 0.862195 0.757255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 4.10 vpr 74.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 118 229 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76392 229 197 2152 2349 1 1012 544 16 16 256 io auto 34.6 MiB 2.04 13816 8635 175845 51740 110676 13429 74.6 MiB 0.62 0.01 3.6187 2.93018 -676.548 -2.93018 2.93018 0.00 0.00285906 0.00253098 0.244304 0.219997 -1 -1 -1 -1 -1 11066 15 1.05632e+07 6.35949e+06 4.24953e+06 16599.7 0.18 0.389441 0.356177 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt index a285dc5eca4..86b1be0aab8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.34 vpr 67.74 MiB 0.06 9856 -1 -1 3 0.39 -1 -1 39776 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69364 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.29 0.00 2.23767 -220.613 -2.23767 2.23767 0.27 0.00107588 0.000959454 0.0879605 0.0803385 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 0.81 0.341856 0.310926 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.05 0.14 -1 -1 0.03 0.0261531 0.0245164 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.91 odin 100.12 MiB 2.20 102528 -1 -1 3 0.20 -1 -1 34288 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68344 99 130 363 493 1 252 298 12 12 144 clb auto 27.5 MiB 0.07 2018 885 69948 23010 34855 12083 66.7 MiB 0.12 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.09 0.000560638 0.000524271 0.0428473 0.0401199 -1 -1 -1 -1 40 1646 17 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.159079 0.1459 12666 64609 -1 1625 10 525 650 46110 15051 2.57635 2.57635 -244.199 -2.57635 0 0 419432. 2912.72 0.01 0.02 0.04 -1 -1 0.01 0.0167278 0.0157148 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt index ddf76e6dee9..61db489ac85 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.16 vpr 67.80 MiB 0.06 9984 -1 -1 3 0.37 -1 -1 39748 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.14 877 59998 22493 27317 10188 67.8 MiB 0.17 0.00 2.17528 -133.517 -2.17528 2.17528 0.25 0.000598743 0.00053199 0.0416228 0.0366674 -1 -1 -1 -1 40 1685 15 5.66058e+06 4.21279e+06 333335. 2314.82 1.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.61 odin 100.12 MiB 2.11 102528 -1 -1 3 0.19 -1 -1 34096 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67704 99 130 363 493 1 252 298 12 12 144 clb auto 27.3 MiB 0.06 2007 832 63978 23229 30524 10225 66.1 MiB 0.09 0.00 2.23767 2.17638 -131.403 -2.17638 2.17638 0.09 0.000333564 0.000306163 0.0239387 0.0220541 -1 -1 -1 -1 40 1539 8 5.66058e+06 4.21279e+06 333335. 2314.82 0.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt index 4503f0925f9..af9a878e7be 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.64 vpr 67.62 MiB 0.06 9856 -1 -1 3 0.30 -1 -1 39896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69248 99 130 363 493 1 252 298 12 12 144 clb auto 28.5 MiB 0.14 956 73928 27133 34341 12454 67.6 MiB 0.26 0.00 2.30557 0 0 2.30557 0.25 0.000962793 0.000867177 0.0597068 0.0524058 -1 -1 -1 -1 38 1840 8 5.66058e+06 4.21279e+06 319130. 2216.18 1.37 0.282428 0.244945 12522 62564 -1 1734 8 415 510 29213 8865 2.61298 2.61298 0 0 0 0 406292. 2821.48 0.02 0.03 0.09 -1 -1 0.02 0.0187719 0.0170722 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 2.01 odin 99.38 MiB 0.18 101760 -1 -1 3 0.20 -1 -1 33348 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67932 99 130 363 493 1 253 298 12 12 144 clb auto 27.5 MiB 0.07 1922 792 82883 30333 38996 13554 66.3 MiB 0.12 0.00 2.3756 2.31285 0 0 2.31285 0.09 0.000342166 0.000313838 0.0308764 0.0284297 -1 -1 -1 -1 38 1683 10 5.66058e+06 4.21279e+06 319130. 2216.18 0.44 0.205871 0.176164 12522 62564 -1 1509 8 399 488 29742 9782 3.03498 3.03498 0 0 0 0 406292. 2821.48 0.01 0.02 0.04 -1 -1 0.01 0.00956584 0.00877781 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt index 0a5e59f0296..60debff32f8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.62 vpr 67.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68616 5 3 11 14 2 9 10 4 4 16 clb auto 28.6 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8501e-05 3.4711e-05 0.00027851 0.000219913 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00215999 0.00198392 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181366 0.00173531 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.62 vpr 67.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68636 5 3 11 14 2 9 10 4 4 16 clb auto 28.5 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.1152e-05 3.666e-05 0.000287379 0.000227035 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.03 0.0023614 0.00216487 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.0022135 0.00167838 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.55 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68936 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.7208e-05 4.2383e-05 0.000322556 0.000257546 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.02 0.00215648 0.00197387 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181267 0.00173458 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.37 vpr 65.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67352 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.00 24 21 30 9 19 2 65.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3433e-05 1.6316e-05 0.000167701 0.000131993 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00124098 0.00112929 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00103978 0.000979331 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.38 vpr 66.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67744 5 3 11 14 2 9 10 4 4 16 clb auto 27.5 MiB 0.00 24 21 30 9 19 2 66.2 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.4371e-05 1.7073e-05 0.000167678 0.000133091 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00122278 0.00111533 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00104402 0.000992025 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.41 vpr 65.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67356 5 3 11 14 2 9 10 4 4 16 clb auto 27.5 MiB 0.00 24 21 30 9 19 2 65.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3581e-05 1.6396e-05 0.000163408 0.000128983 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00126469 0.0011518 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00112382 0.00106571 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt index 9d457582f18..1814e2bfbd5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.68 vpr 69.25 MiB 0.08 10496 -1 -1 5 0.17 -1 -1 36364 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70908 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.39 448 1927 352 1502 73 69.2 MiB 0.04 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000798161 0.000674358 0.0213182 0.0191108 -1 -1 -1 -1 -1 595 8 1.07788e+06 754516 219490. 4479.39 0.04 0.060298 0.0550487 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 4.79 odin 156.75 MiB 3.12 160512 -1 -1 5 0.11 -1 -1 33284 -1 -1 14 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69568 11 30 313 321 2 114 55 7 7 49 clb auto 28.3 MiB 0.18 671 455 1719 301 1356 62 67.9 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000433259 0.000381809 0.011092 0.0100284 -1 -1 -1 -1 -1 571 12 1.07788e+06 754516 219490. 4479.39 0.02 0.0308004 0.0280931 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt index 070113b9371..f78c9ca7563 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.31 vpr 66.76 MiB 0.06 10368 -1 -1 4 0.22 -1 -1 36924 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 425 2283 406 1804 73 66.8 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000550429 0.00044745 0.0205892 0.0175295 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0715823 0.0554655 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.35 vpr 67.11 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36664 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68720 11 30 262 292 2 99 60 7 7 49 clb auto 27.5 MiB 0.09 425 2283 406 1804 73 67.1 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000592669 0.000483133 0.0176652 0.0153201 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.08 0.0695138 0.0618702 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.40 vpr 66.21 MiB 0.07 10368 -1 -1 4 0.18 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67804 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000259913 0.000168736 0.00804711 0.00632437 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0326926 0.0257255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.40 vpr 66.24 MiB 0.07 10368 -1 -1 4 0.22 -1 -1 36412 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67828 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000820125 0.000270462 0.0105947 0.00836537 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0358221 0.028376 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 3.52 odin 166.88 MiB 2.58 170880 -1 -1 4 0.12 -1 -1 33100 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000407927 0.000352794 0.0103629 0.00913612 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.03 0.0329737 0.0288413 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 3.51 odin 167.25 MiB 2.59 171264 -1 -1 4 0.12 -1 -1 33100 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000396579 0.000343532 0.0101806 0.00898166 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.03 0.0321781 0.0281256 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 3.92 odin 167.25 MiB 2.91 171264 -1 -1 4 0.12 -1 -1 33076 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67276 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.03 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 7.0829e-05 2.2318e-05 0.00621115 0.00447324 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.03 0.0212245 0.0160265 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 3.38 odin 167.25 MiB 2.47 171264 -1 -1 4 0.12 -1 -1 33108 -1 -1 20 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.01 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000417801 7.7923e-05 0.00452636 0.00335783 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.02 0.016299 0.0118717 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt index ec4372e5ea5..5ebdbecff03 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 76.86 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215732 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.5 MiB 14.49 75097 245792 47628 188491 9673 1158.4 MiB 19.32 0.31 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0645942 0.0566793 4.57717 3.66743 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 8.99 -1 -1 1158.4 MiB 6.77 7.11559 5.86421 1158.4 MiB -1 3.90 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 32.94 vpr 1.16 GiB 42 749 0 0 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1215300 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 1077.6 MiB 7.56 231619 75107 234775 43541 180854 10380 1154.8 MiB 5.78 0.08 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.00 0.022899 0.0201602 1.65582 1.36851 87307 6.90501 21230 1.67906 25811 34329 9106433 1637889 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.36451 2.98815 -5707.14 -4.36451 0 0 3.12 -1 -1 1154.8 MiB 2.51 2.68373 2.2771 1154.8 MiB -1 1.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt index 9097fbde85d..ea5a62166c3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 18.00 vpr 70.38 MiB 0.05 10112 -1 -1 6 0.25 -1 -1 38052 -1 -1 15 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72072 66 96 1000 687 1 578 192 18 18 324 mult_27 auto 31.1 MiB 2.15 5241 46091 14804 26339 4948 70.4 MiB 0.71 0.01 16.7702 -967.772 -16.7702 16.7702 0.75 0.00350611 0.00326694 0.374139 0.351063 -1 -1 -1 -1 54 12671 42 6.4517e+06 1.13409e+06 1.49609e+06 4617.55 10.37 1.47511 1.37701 50360 316156 -1 11227 19 3612 7762 1892477 579383 16.9221 16.9221 -1089.8 -16.9221 0 0 1.91711e+06 5917.01 0.13 0.79 0.45 -1 -1 0.13 0.185679 0.177041 133 202 146 33 66 33 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 8.84 odin 81.00 MiB 1.62 82944 -1 -1 6 0.10 -1 -1 34308 -1 -1 16 66 0 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70700 66 96 1000 687 1 578 193 18 18 324 mult_27 auto 29.7 MiB 0.88 8817 5194 44753 13259 26140 5354 69.0 MiB 0.26 0.00 17.614 16.4128 -968.178 -16.4128 16.4128 0.28 0.00142532 0.00134186 0.124539 0.117372 -1 -1 -1 -1 56 13393 29 6.4517e+06 1.15929e+06 1.55150e+06 4788.57 3.94 0.460824 0.429459 50684 323660 -1 11784 18 3706 7635 1966406 594465 16.8068 16.8068 -1080.85 -16.8068 0 0 1.95585e+06 6036.58 0.05 0.30 0.16 -1 -1 0.05 0.0694977 0.0659629 133 202 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt index 9b26c986ccf..ec7b2e0c03c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.53 vpr 65.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66664 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.03 88 59 31 28 0 65.1 MiB 0.01 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.00022667 0.0001997 0.00145978 0.00134015 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.01 -1 -1 65.1 MiB 0.01 0.0151269 0.0141345 65.1 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.49 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000166651 0.000146123 0.00118945 0.00110009 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.0110046 0.0100571 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.25 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66768 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000189994 0.000167385 0.00110293 0.00101544 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.2 MiB 0.03 -1 -1 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.27 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000187343 0.000161123 0.00133988 0.00123837 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.2 MiB 0.04 -1 -1 65.2 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.18 vpr 63.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65184 6 8 39 47 1 20 17 5 5 25 clb auto 25.3 MiB 0.01 107 88 59 31 28 0 63.7 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 7.9799e-05 7.1099e-05 0.000712939 0.000670565 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.7 MiB 0.01 0.00498597 0.004445 63.7 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.18 vpr 63.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 6 8 39 47 1 20 17 5 5 25 clb auto 25.2 MiB 0.01 107 88 59 31 28 0 63.9 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 8.1571e-05 7.2642e-05 0.000740217 0.000697213 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.9 MiB 0.01 0.00512095 0.00457576 63.9 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.19 vpr 63.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64752 6 8 39 47 1 20 17 5 5 25 clb auto 24.9 MiB 0.01 107 88 59 31 28 0 63.2 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.191e-05 7.295e-05 0.000726941 0.000683562 -1 -1 -1 -1 -1 -1 -1 -1 656 1029 31338 15241 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.2 MiB 0.02 -1 -1 63.2 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.19 vpr 63.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65292 6 8 39 47 1 20 17 5 5 25 clb auto 25.1 MiB 0.01 107 88 59 31 28 0 63.8 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.0823e-05 7.2013e-05 0.00072635 0.000683135 -1 -1 -1 -1 141 7.42105 65 3.42105 656 1029 31338 15241 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9119 -1.84852 0 0 0.00 -1 -1 63.8 MiB 0.02 -1 -1 63.8 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt index a8c8aed1d54..f6f2c1145a0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.42 vpr 61.41 MiB 0.07 9984 -1 -1 6 0.21 -1 -1 36540 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62880 11 30 336 366 2 175 110 11 11 121 clb auto 21.7 MiB 0.07 1099 5370 731 4291 348 61.4 MiB 0.07 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.000895008 0.000764708 0.0287001 0.0253164 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.19 -1 -1 61.4 MiB 0.11 0.0797492 0.0714232 61.4 MiB -1 0.02 - k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 62.21 MiB 0.06 9984 -1 -1 4 0.20 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63704 11 30 262 292 2 110 54 6 6 36 clb auto 22.6 MiB 0.15 403 1584 300 1231 53 62.2 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000808513 0.00071129 0.0212101 0.0190689 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.05 -1 -1 62.2 MiB 0.04 0.0510796 0.0464992 62.2 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 2.87 odin 150.38 MiB 1.42 153984 -1 -1 6 0.13 -1 -1 33084 -1 -1 65 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61456 11 30 336 366 2 170 106 11 11 121 clb auto 20.6 MiB 0.03 1794 1031 5856 842 4573 441 60.0 MiB 0.03 0.00 6.01276 3.5056 -244.76 -3.5056 3.41098 0.00 0.000481658 0.0004129 0.0143059 0.0124525 -1 -1 -1 -1 976 5.87952 976 5.87952 913 2746 123850 27697 180575 144906 597941. 4941.66 13 20106 83797 -1 3.39028 3.23041 -241.825 -3.39028 -0.29331 -0.0734 0.06 -1 -1 60.0 MiB 0.04 0.0324494 0.0284835 60.0 MiB -1 0.01 +k6_frac_N10_40nm.xml stereovision3.v common 2.96 odin 151.50 MiB 1.71 155136 -1 -1 4 0.12 -1 -1 33092 -1 -1 13 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61812 11 30 262 292 2 107 54 6 6 36 clb auto 21.0 MiB 0.07 561 400 1890 329 1495 66 60.4 MiB 0.02 0.00 2.44705 2.33435 -170.194 -2.33435 2.21316 0.00 0.000401082 0.000350284 0.0105728 0.00946584 -1 -1 -1 -1 486 4.71845 224 2.17476 223 387 11633 4030 862304 700622 161034. 4473.17 11 3844 24048 -1 2.35133 2.20841 -178.735 -2.35133 0 0 0.01 -1 -1 60.4 MiB 0.02 0.0271978 0.024617 60.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt index c745d2940f2..c5a98194fb1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.36 vpr 61.16 MiB 0.06 9984 -1 -1 6 0.24 -1 -1 36564 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62624 11 30 336 366 2 175 110 11 11 121 clb auto 21.6 MiB 0.08 1099 5370 731 4291 348 61.2 MiB 0.08 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.00109238 0.000939106 0.0296397 0.0256861 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.18 -1 -1 61.2 MiB 0.09 0.0740596 0.0653877 61.2 MiB -1 0.03 - k6_frac_N10_40nm.xml stereovision3.v common 1.71 vpr 62.40 MiB 0.03 10112 -1 -1 4 0.22 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63900 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 403 1584 300 1231 53 62.4 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000733682 0.000641677 0.0178767 0.0155436 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.04 -1 -1 62.4 MiB 0.04 0.0527381 0.04796 62.4 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 2.68 odin 150.38 MiB 1.39 153984 -1 -1 6 0.12 -1 -1 33080 -1 -1 65 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61460 11 30 336 366 2 170 106 11 11 121 clb auto 20.2 MiB 0.03 1794 1031 5856 842 4573 441 60.0 MiB 0.03 0.00 6.01276 3.5056 -244.76 -3.5056 3.41098 0.00 0.000486395 0.00042381 0.0138701 0.0120728 -1 -1 -1 -1 976 5.87952 976 5.87952 913 2746 123850 27697 180575 144906 597941. 4941.66 13 20106 83797 -1 3.39028 3.23041 -241.825 -3.39028 -0.29331 -0.0734 0.06 -1 -1 60.0 MiB 0.03 0.0307292 0.0268906 60.0 MiB -1 0.01 +k6_frac_N10_40nm.xml stereovision3.v common 2.71 odin 151.50 MiB 1.49 155136 -1 -1 4 0.12 -1 -1 33104 -1 -1 13 11 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61808 11 30 262 292 2 107 54 6 6 36 clb auto 21.0 MiB 0.06 561 400 1890 329 1495 66 60.4 MiB 0.02 0.00 2.44705 2.33435 -170.194 -2.33435 2.21316 0.00 0.000398384 0.000344047 0.010359 0.0092135 -1 -1 -1 -1 486 4.71845 224 2.17476 223 387 11633 4030 862304 700622 161034. 4473.17 11 3844 24048 -1 2.35133 2.20841 -178.735 -2.35133 0 0 0.01 -1 -1 60.4 MiB 0.02 0.026643 0.0240418 60.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt index 8249d51c4a6..7e66c359122 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 34.23 vpr 978.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001816 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.58 371 490 69 397 24 978.3 MiB 0.06 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000593468 0.00051514 0.0111956 0.0102241 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.3 MiB 0.07 0.0418866 0.0386921 978.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml styr.blif common 21.32 vpr 979.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003348 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.33 530 402 720 97 571 52 979.8 MiB 0.06 0.00 6.8225 6.61671 -72.4654 -6.61671 6.61671 0.00 0.000286578 0.00025614 0.00775293 0.0072086 -1 -1 -1 -1 669 10.4531 198 3.09375 255 965 67200 31259 0 0 194014. 2204.70 14 11730 32605 -1 6.73871 6.73871 -74.3689 -6.73871 0 0 0.03 -1 -1 979.8 MiB 0.05 0.0239292 0.0222252 979.8 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt index 37eedf040f0..4df0977db16 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt @@ -1,6 +1,5 @@ regression_tests/vtr_reg_strong_odin/strong_absorb_buffers regression_tests/vtr_reg_strong_odin/strong_analysis_only -regression_tests/vtr_reg_strong_odin/strong_analytic_placer regression_tests/vtr_reg_strong_odin/strong_bidir regression_tests/vtr_reg_strong_odin/strong_binary regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs From e71ef454615d6cca0b1b6c80c796c4aaba374dc1 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Wed, 21 May 2025 12:28:59 -0400 Subject: [PATCH 452/453] OpenFPGA Update (#3066) * [Router] Added ConnectionRouter Abstraction and Reduced Code Duplication Added a partial abstract class for ConnectionRouter, derived from the pure abstract ConnectionRouterInterface. The SerialConnectionRouter and ParallelConnectionRouter classes are now derived from the ConnectionRouter class, utilizing the common class members and helper functions to reduce code duplication. * [Router] Added Code Comments and Documentation for Connection Routers Added Doxygen-style code comments and documentation for connection routers, including the ConnectionRouter abstract class, the Parallel- ConnectionRouter concrete class, and the SerialConnectionRouter concrete class. Updated the helper messages for command-line options added for parallel connection router. * [Router] Fixed Interface Issues in NestedNetlistRouter and Code Formats Fixed the interface issues of ConnectionRouter in NestedNetlistRouter. Fixed code formats. Fixed typo in read_options.cpp. * [Router] Updated Command-Line Usage for Parallel Connection Router Updated the command-line usage for parallel connection router in both Read the Docs and read_options.cpp. * [Router] Added Regression Tests for Parallel Connection Router Added regression tests for parallel connection router by appending extra sets of configurations to those VTR flow regression tests previously selected by Fahri for testing coarse-grained parallel router. Removed VPR connection router test (vpr/test/test_connection_router.cpp), since it has been out-dated for a very long time and has caused lots of trouble for running VPR C++ tests locally. * Fixed Code Formatting Issue Fixed a weird code formatting issue in libs/librtlnumber/src/include/ internal_bits.hpp. GitHub CI said the file failed dev/check-format.sh, however, the same script runs perfectly in my local environment. Double checked the version of clang-format, which seemed to be the same as CI. Directly copied the file from the GitHub repo to resolve this issue. * [Router] Fixed `No source in route tree` in ParallelConnectionRouter The `No source in route tree` bug in ParallelConnectionRouter (since commit 875b98e) has been fixed. It turns out that putting another member variable `MultiQueueDAryHeap heap_` in the derived class ParallelConnectionRouter together with the existing `HeapImplementation heap_` in the base class ConnectionRouter causes the issue. The solution is to keep `heap_` only in the base class and use `ConnectionRouter>` rather than `ConnectionRouter` for deriving the parallel connection router. Please note that ParallelConnectionRouter still has some bugs (i.e., getting stuck in the MultiQueue pop). This commit is not fully working. Please do not use it for any experiments. Updated the previously incorrect command-line options for the parallel connection router in the regression tests. * [AP][MassLegalizer] Revistited Mass Legalizer Found that the mass legalizer was not spreading out the blocks well enough according to the mass. Revistied the spatial partitioning in the mass legalizer. Before, we just cut the window in half in the larger dimension. This was fine, however it may create an inbalanced cut which can cause things to not spread well. Instead, we now search for the best partition by trying different partition lines and computing how balanced the partition is. Although this is more expensive than before, by creating more balanced partitions, it should allow the mass legalizer to converge faster. Time in the mass legalizer is also dominated by partitioning the blocks, so increasing the time to choose the partition line should not have that large of an effect anyways. Found an oversight with how blocks were partitioned when one of the partitions become overfilled. Fixed this issue. * Inverse use of macro_can_be_placed argument check_all_legality to align with meaning * [vpr][pack] fix merge issues w/ flat sync list * make format * [packages] add clang-format * make format 2 * Invalid C++ fix * [docker] set ubuntu version to 24.04 * [dockerfile] enable system-wide python package installation for pip * [dockerfile] add comment * [package] check whehter clang-format-18 package exist * [package] remove deprecated names-only option * [package] remove if condition * [doc] update quick start on installing packages * make format enum class e_rr_type a few remaining t_rr_type vals CHANY ---> t_rr_type::CHANY CHANX ---> t_rr_type::CHANX OPIN ---> t_rr_type::OPIN IPIN ---> t_rr_type::IPIN SINK ---> t_rr_type::SINK SOURCE ---> t_rr_type::SOURCE * [Router] Finally fixed the weird bug in parallel connection router Fixed the weird bug in parallel connection router as mentioned in commit f73212c. The bug occurred because two function parameters 'num_threads' and 'num_queues' have been misplaced when instantiating the MQ_IO. This took two weeks to figure out exactly. The VTR benchmark (`vtr_reg_qor_chain` task) has been tested/passed for different cases (1) 'serial mode' 1T+2Q (1 thread, 2 queues), (2) 2T+4Q, and (3) 4T+2Q. The determinism has also been verified for the VTR benchmark. * [Router] Fixed Code Review Comments and Cleanup Codebase Added more explanation to the command-line options messages and code comments. Cleaned up ParallelConnectionRouter-related codebase. * [doc] clarify that clang-format is not required to build VPR * remove typedef t_rr_type * doxygen comment for Direction * add vtr::array class * make rr_node_typename of type vtr::array to index it only with e_rr_type * add default constructor to vtr::array * access rr_node_indices_ with e_rr_type instead of casting to size_t * add single argument constructor to vtr::array * [Router] Updated Golden Results for Parallel Connection Router CI Tests Updated the golden results for CI tests for parallel connection router: - `vtr_reg_strong/koios_test` - `vtr_reg_strong/strong_flat_router` - `vtr_reg_strong/strong_multiclock` - `vtr_reg_strong/strong_timing` * use vtr::array to index some arrays using e_rr_type * make format * avoid using e_rr_type and casting it in place_macro * [vpr][base] fix assigned pb_graph_pin when graph node is not primitive * [vpr][pack] pass logical type to alloc_and_laod_pb_route * [vpr][pack] update alloc_and_load_pb_route header file * [vpr][pack] fix pb_graph_pin assignment in load_trace_to_pb_route * [test] keep 3d sb and cb tests * [vpr][pack] add intra_lb_pb_pin_lookup_ to cluster legalizer * [vpr][pack] initializer intra_lb_pb_pin_lookup and pass it to alloc_and_load_pb_route * [vpr][pack] use intra_lb_pb_pin_lookup to get pb_pin from pin number * make format * add vtr::array to docs * [vpr][pack] remove casting net id * [vpr][pack] add doxygen comment for alloc_and_load_pb_route * [vpr][pack] remove redundant parameters * [vpr][pack] polish load_trace_to_pb_route * make format * [vpr][pack] fix parameter shadowing * [AP][HotFix] Fixed Bug With Solver Putting Blocks Off-Device After moving fixed blocks to the center of tiles, there is a very small chance that blocks go off the device due to rounding. This is such a small effect that it does not show up locally on my machine, but it shows up on CI. Clamping the positions of blocks after solving to be just within the device region. * Increase the daily stale issue action API call limit * [vpr][pack] add a method to get root_ipin * [vpr][pack] remove unused var * [Router] Added Assert for MQ_IO numQueues and Updated Golden Results Added assert for MultiQueueIO numQueues to ensure it must be greater than two. Updated CI test tasks to ensure the parallel connection router runs in Dijkstra mode to ensure determinism and avoid hanging in CI runs. * [AP][HotFix] Placed Fixed Blocks First During IP The cost terms in the AP initial placer were not placing fixed blocks early enough, causing other blocks to take their place and causing the initial placer to not return a solution. Blocks which have region constraints are now placed first based on how constrained they are. More constrained blocks (can only be placed in a smaller region) will be placed first. Also found that macros that contained fixed blocks were not observing these constraints when calculating the centroid position of the macro. For constrained macros, projected the centroid position onto the partition region to get the closest point in the partition region to the calculated centroid. This new centroid is used to then perform the placement. * [STA] Added Option to Remove Parameters from Post-Implementation Netlist When performing post-implementation timing analysis using OpenSTA, the generated netlist cannot use parameters since each module needs to correspond with a cell in a liberty file. Added a command-line option which tells the netlist writer to not use parameters when generating the netlist. If a primitive cannot be generated without using parameters, it will error out. * [Tatum][Parse] Fixed Extraneous Warning With get_clocks The get_clocks command is used in an SDC file to reference a set of clocks by name using a regex string. The code to do this tries to produce a warning if get_clocks is used on a regex string and no clocks could be found. The issue is that the code to do this was mistakenly producing this warning for each clock in the circuit. For example, if we had {clk1, clk2, clk3} and we wanted to do "get_clocks {clk3}", we will get two warnings since clk1 and clk2 did not match. Fixed this by moving the warning out of one loop nest. * Remove PR staling This commit sets the number of days before marking issues or PRs as stale to 100 years. This number is overriden for issues to be 1 years but stays 100 years for PRs. This means that PR effectively do not get marked as stale. * [LibArchFPGA] Updating Model Data Structures The logical models (the technology-mapped logical blocks) for an architecture were stored using two independent linked lists. One for the library models (the models that all architectures have, such as luts and ffs) and one of the user models. This linked lists were hard to traverse and were injecting pointers all across VPR. Created a new class to store and manage the logical models. This class maintains a unique ID for each logical model (similar to the netlist data structures in VPR). It also contains helper methods to make working with the logical models easier. * fix comments from alex * revert prepacker changes * [vpr][pack] add get_pattern_blocks * [vpr][pack] add blocks in get_all_connected_primitive_pins if they are a part of the pattern * make format * Bump libs/EXTERNAL/libcatch2 from `76f70b1` to `5abfc0a` Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `76f70b1` to `5abfc0a`. - [Release notes](https://github.com/catchorg/Catch2/releases) - [Commits](https://github.com/catchorg/Catch2/compare/76f70b1403dbc0781216f49e20e45b71f7eccdd8...5abfc0aa9c1ef4cb40c9f387495134dab02e1af2) --- updated-dependencies: - dependency-name: libs/EXTERNAL/libcatch2 dependency-version: 5abfc0aa9c1ef4cb40c9f387495134dab02e1af2 dependency-type: direct:production ... Signed-off-by: dependabot[bot] * [vpr][pack] add more comments * Add helper functions to t_pb_type * Change t_pb_type users to use helper functions * Add documentation for t_pb_type::is_root and is_primitive * Fix formatting in libarchfpga/physical_types.h * [vpr][pack] change count method to find * [Router] Updated the Regression Tests and Corresponding Golden Results Changed `multi_queue_num_threads` and `multi_queue_num_queues` settings in the CI strong regression tests to avoid QoR failure in the CI runs. The coverage of the regression tests for parallel connection router after this change is still fair. * [vpr][CLI] add generate_net_timing_report * [vpr][route] remove debugging msg * [vpr][analysis] add generate_net_timing_report * [vpr][pack] apply formatting comments * make format * [vpr][analysis] add comments * make format * [vpr][CLI] remove generate net timing from CLI parameters and generate the report by default * Unused Packer Options Cleanup (#2976) * Standardized and renamed packer alpha and beta variable. They are now referred to as timing_gain_weight and connection_gain_weight, used as a weight parameter during timing and connection driven clustering respectively. Removed global_clocks, use_attraction_groups, pack_num_moves, pack_move_type from packer. * [APPack] Updated Max Candidate Distance Interface The max candidate distance is used by APPack to decide which molecules to ignore when packing, based on their distance from the cluster being formed. Cleaned up the interface of this by pre-computing the max candidate distance of all logical blocks ahead of time and reading from these pre-computed values during packing. Added a command-line option to allow the user to override some or all of these max distance thresholds. By default, VPR will select values based on the type of logical block and the primitives it contains. Fixed issue with APPack creating too many IO blocks for some circuits due to the max candidate distance thresholds for IO blocks being too low. More tuning should be done on these values once the mass legalizer has been cleaned up a bit more. * [vtr][parse] fix pattern for init place wl * [vpr][analysis] add header for net timing report * [vpr][analysis] add timing format to comments * formatting fix * Revert "[vpr][CLI] remove generate net timing from CLI parameters and generate the report by default" This reverts commit b8289db3ed811a9b831dbb036b91929e6b2737fc. * make format * [STA] Generating SDC Commands Post-Implementation Added an option to have VPR generate an SDC file containing the timing commands required for an external timing analysis of the post- implementation netlist to match VPR's timing analysis. * [STA] Added Tutorial for Post-Implementation Timing Analysis Created a tutorial demonstrating how OpenSTA can be used after VPR to perform static timing analysis. * Add artifact upload to nightly test workflow * t_det_routing_arch* --> const t_det_routing_arch& * t_chan_width_dist ---> const t_chan_width_dist& * make format * fix compilation error in route_diag by passing det_routing_arch argument by reference instead of pointer * [task] add generate_net_timing_report to timing report strong test * [doc] add doc for generating _net_timing_report command line option * [vpr][timing] update generate_net_timing_report comment * [vpr][timing] add get_net_bounding_box * [vpr][timing] add net bounding box to the report * [test] add test for net timing report * [doc] update doc with new format to net timing report * [vpr][analysis] fix net timing report bugs + including layer min/max of bb * make format * [vpr][analysis] capture vars by reference in lambda * [packer] Changing the vector of candidate molecules into LazyPopUniquePriorityQueue. The class LazyPopUniquePriorityQueue is a priority queue that allows for lazy deletion of elements. It is implemented using a vector and 2 sets, one set keeps track of the elements in the queue, and the other set keeps track of the elements that are pending deletion. The queue is sorted by the sort-value(SV) of the elements, and the elements are stored in a vector. The set is used to keep track of the elements that are pending deletion, so that they can be removed from the queue when they are popped. The class definiation can be found in vpr/src/util/lazy_pop_unique_priority_queue.h Currently, the class supports the following functions: LazyPopUniquePriorityQueue::push(): Pushes a key-sort-value (K-SV) pair into the priority queue and adds the key to the tracking set. LazyPopUniquePriorityQueue::pop(): Returns the K-SV pair with the highest SV whose key is not pending deletion. LazyPopUniquePriorityQueue::remove(): Removes an element from the priority queue immediately. LazyPopUniquePriorityQueue::remove_at_pop_time(): Removes an element from the priority queue when it is popped. LazyPopUniquePriorityQueue::empty(): Returns whether the queue is empty. LazyPopUniquePriorityQueue::clear(): Clears the priority queue vector and the tracking sets. LazyPopUniquePriorityQueue::size(): Returns the number of elements in the queue. LazyPopUniquePriorityQueue::contains(): Returns true if the key is in the queue, false otherwise. * [packer] recollected golden results for regression basic, basic_odin, strong, strong_odin * [packer] recollected golden results for Nightly * add pointer to VTR9 paper in the readme * Add documentation to explain which parts of VPR are parellel * pass t_chan_width by reference * doxygen comment for alloc_and_load_rr_node_indices * add doxygen comments for load_block_rr_indices() * [AP][Solver] Enabled Parallel Eigen The Eigen solver has the ability to use OpenMP to run the solver computations in parallel. Made the AP flow use the num_workers option to set the number of threads that Eigen can use. VPR did not have the ability to build with OpenMP in its CMAKE. Added an option to the CMAKE to allow the user to enable OpenMP. * remove unused is_flat argument from alloc_and_load_rr_node_indices() and load_block_rr_indices() * use (x, y) convention for CHANX instead of (y, x) * make format * cast x/y to size_t * get rid of warnings in RRSpatialLookup::find_nodes() * Add references to the main VTR papers in the documentation. * Add link to the VTR 9 paper in the documentation * Add link to the VTR 9 paper in the README * add a closing ) to the text printed by node_coordinate_to_string() * fix the x/y mismatch for CHANX nodes in rr_nodes and rr_node_indices * reserve nodes using x/y instead of chan/seg * fix a typo * add rr_graph_genearion directory * resize node lookup for CHANX nodes in RR graph serializer * add rr_node_indices.cpp/.h * add doxygen comment for load_chan_rr_indices() * [Infra] Updated Install Packages Script For Backwards Compatibility The install_apt_packages.sh script is no longer backward compatible with older versions of Ubuntu due to the dependency on clang-format-18. Added an if statement to check if the distribution can support clang-format-18 and only installing it if it can. Added this script to the CI build process so it can always be tested within the CI to prevent future regression. * [RegTest] Disabled `strong_multiclock` test for parallel connection router Temporarily disabled the `strong_multiclock` test in `vtr_reg_strong` CI regression tests for the parallel connection router, due to some random failures as mentioned in Issue #3029. After fixing the problem with the `strong_multiclock` test, this will be reactivated. * [doc] update the doc with new report format * [RegTest] Updated golden results for `strong_multiclock` regression test Removed the golden results of parallel connection router test cases for `strong_multiclock` regression test. * [vpr][analysis] use std::min/max instead of if condition * Add documentation for include sanitization * [vpr][analysis] change report_net_timing format to csv * [vpr][analysis] update comments * [vpr][analysis] print constant nets in the net timing report * [vpr][analysis] apply comments * [vpr][analysis] fix function name * [doc] add net timing report use case * fix a typo * [Infra] Cleaned Up Include Files in VPR Base Directory Many include files in the base directory contained includes to other headers which they do not use. This causes many CPP files to include way more header files than they need, increasing the incremental build time. This process needs to be done on the entire VTR repo, but I found that the base directory was one of the biggest culprits of this and the hardest to untangle. * [Infra] Cleaned Up Header Files in Pack Folder Went through the header files in the pack folder and resolved any unused header files. * [AP] Removed Old Cluster-Level AP Flow Prior to the flat AP flow, a cluster-level AP flow existed in VPR which performed a SimPL-style algorithm on the clusters created during packing before performing a placement quench. Although well-written, this flow was not shown to outperform the SA placer in VPR. It has also been becoming confusing to keep in VPR since the new flat AP flow supercedes it. It is unclear if a cluster-level AP flow will work well with the flat AP flow; however in that case the cluster-level AP flow would be made using the new AP APIs written. Removed the old cluster-level AP flow to reduce confusion. * [Infra] Cleaned Up Header Files in Place Folder * [lib][rr_graph] replace t_rr_type with e_rr_type * [vpr][tileable] remove t_rr_type usage * make is_io_type() a member function of t_physical_tile_type * replace calls to is_io_type() with t_physical_tile_type::is_io() * make format * fix compiler bugs * make format * [lib][libutil] fix size_t issue * inline t_physical_tile_type::is_io() * add doxygen comments for alloc_and_load_tile_rr_node_indices() * [libs][vtrutil] use generate instead of fill to avoid getting potential null pointer dereference * document alloc_and_load_rr_node_indices() arguments * made a few function operating on t_pb_type its member functions * add router_lookahead directory * [STA] Added Multiclock Incremental STA Consistency Check The incremental STA consistency coverage was very good, but was just missing a multiclock circuit with an SDC file. Added a quick test. * [libs][rr_graph] don't reverse xy when calling node lookup * [vpr][util] consider medium node type as inter cluster node * [Infra] Cleaned Up Header Files in Route Folder Continued the header file cleanup effort in the route folder. Some of these files may need to be revisited in more detail, but got some of the major header include issues. Found that some definitions were in the wrong place, so moved them to the correct implementation file. * [Infra] Updated Header Files Based on Comments Moved to pragma once symantics and cleaned up some less than ideal code. * [vpr][tileable] use is_io in t_physcial_tile * [vpr][route] update rr node indices to include medium type --------- Signed-off-by: dependabot[bot] Co-authored-by: Hang Yan Co-authored-by: AlexandreSinger Co-authored-by: Fred Tombs Co-authored-by: soheilshahrouz Co-authored-by: AlexandreSinger <49374526+AlexandreSinger@users.noreply.github.com> Co-authored-by: Soheil Shahrouz <80951211+soheilshahrouz@users.noreply.github.com> Co-authored-by: Amir Poolad <54797949+AmirhosseinPoolad@users.noreply.github.com> Co-authored-by: Amir Poolad Co-authored-by: vaughnbetz Co-authored-by: Fred Tombs Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Co-authored-by: James Yen <90464912+yenjames@users.noreply.github.com> Co-authored-by: Rongbo Zhang Co-authored-by: Rongbo Zhang Co-authored-by: Mohamed Elgammal --- vpr/src/route/NestedNetlistRouter.h | 1 + vpr/src/route/SerialNetlistRouter.tpp | 2 + vpr/src/route/annotate_routing.cpp | 3 +- vpr/src/route/annotate_routing.h | 8 +- vpr/src/route/check_route.h | 4 +- vpr/src/route/connection_based_routing.h | 4 +- vpr/src/route/connection_router.h | 4 +- vpr/src/route/connection_router.tpp | 1 + vpr/src/route/connection_router_interface.h | 3 - vpr/src/route/edge_groups.cpp | 1 + vpr/src/route/edge_groups.h | 3 +- vpr/src/route/heap_type.h | 3 - vpr/src/route/multi_queue_d_ary_heap.h | 5 +- vpr/src/route/netlist_routers.h | 4 +- vpr/src/route/overuse_report.cpp | 1 + vpr/src/route/overuse_report.h | 3 +- vpr/src/route/parallel_connection_router.cpp | 1 + vpr/src/route/parallel_connection_router.h | 1 - vpr/src/route/partition_tree.cpp | 2 + vpr/src/route/partition_tree.h | 7 +- vpr/src/route/route_budgets.cpp | 22 --- vpr/src/route/route_budgets.h | 2 +- vpr/src/route/route_common.cpp | 1 + vpr/src/route/route_common.h | 2 - vpr/src/route/route_export.h | 14 +- vpr/src/route/route_net.cpp | 130 +---------------- vpr/src/route/route_net.h | 10 -- vpr/src/route/route_net.tpp | 2 + vpr/src/route/route_path_manager.cpp | 2 +- vpr/src/route/route_path_manager.h | 9 +- vpr/src/route/route_tree.h | 3 - vpr/src/route/route_utilization.cpp | 2 + vpr/src/route/route_utilization.h | 11 +- vpr/src/route/route_utils.cpp | 134 ++++++++++++++++++ vpr/src/route/route_utils.h | 1 - vpr/src/route/router_delay_profiling.cpp | 1 - vpr/src/route/router_delay_profiling.h | 10 +- vpr/src/route/routing_predictor.cpp | 1 - .../rr_graph_generation/rr_node_indices.cpp | 3 +- vpr/src/route/segment_stats.cpp | 2 - vpr/src/route/segment_stats.h | 5 + vpr/src/route/serial_connection_router.cpp | 2 +- vpr/src/route/serial_connection_router.h | 2 - vpr/src/route/sink_sampling.h | 1 - vpr/src/route/spatial_route_tree_lookup.h | 7 +- .../tileable_rr_graph_node_builder.cpp | 4 +- vpr/src/util/vpr_utils.h | 1 + 47 files changed, 203 insertions(+), 242 deletions(-) diff --git a/vpr/src/route/NestedNetlistRouter.h b/vpr/src/route/NestedNetlistRouter.h index e776d0a42da..87a3fdd880c 100644 --- a/vpr/src/route/NestedNetlistRouter.h +++ b/vpr/src/route/NestedNetlistRouter.h @@ -2,6 +2,7 @@ /** @file Nested parallel case for NetlistRouter */ #include "netlist_routers.h" +#include "partition_tree.h" #include "vtr_optional.h" #include "vtr_thread_pool.h" #include "serial_connection_router.h" diff --git a/vpr/src/route/SerialNetlistRouter.tpp b/vpr/src/route/SerialNetlistRouter.tpp index b84acfbd58f..ae7c8117db7 100644 --- a/vpr/src/route/SerialNetlistRouter.tpp +++ b/vpr/src/route/SerialNetlistRouter.tpp @@ -3,7 +3,9 @@ /** @file Templated implementations for SerialNetlistRouter */ #include "SerialNetlistRouter.h" +#include "partition_tree.h" #include "route_net.h" +#include "route_utils.h" #include "vtr_time.h" template diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 71c78a2498c..4f3fdc4c52d 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -3,13 +3,12 @@ * from VPR to OpenFPGA. (i.e. create a mapping from RRNodeIds to ClusterNetIds) *******************************************************************/ +#include "describe_rr_node.h" #include "vpr_error.h" -#include "vtr_assert.h" #include "vtr_time.h" #include "vtr_log.h" #include "route_utils.h" -#include "rr_graph.h" #include "annotate_routing.h" diff --git a/vpr/src/route/annotate_routing.h b/vpr/src/route/annotate_routing.h index e00be549259..b4026562175 100644 --- a/vpr/src/route/annotate_routing.h +++ b/vpr/src/route/annotate_routing.h @@ -1,7 +1,13 @@ #ifndef ANNOTATE_ROUTING_H #define ANNOTATE_ROUTING_H -#include "vpr_context.h" +#include "clustered_netlist_fwd.h" +#include "rr_graph_fwd.h" +#include "vtr_vector.h" + +struct AtomContext; +struct ClusteringContext; +struct DeviceContext; /******************************************************************** * Create a mapping between each rr_node and its mapped nets diff --git a/vpr/src/route/check_route.h b/vpr/src/route/check_route.h index feff233156e..609a2fcb8d4 100644 --- a/vpr/src/route/check_route.h +++ b/vpr/src/route/check_route.h @@ -1,8 +1,8 @@ #ifndef VPR_CHECK_ROUTE_H #define VPR_CHECK_ROUTE_H -#include "physical_types.h" + +#include "netlist.h" #include "vpr_types.h" -#include "route_common.h" void check_route(const Netlist<>& net_list, enum e_route_type route_type, diff --git a/vpr/src/route/connection_based_routing.h b/vpr/src/route/connection_based_routing.h index 0f0faaaace5..2b7915bf6d5 100644 --- a/vpr/src/route/connection_based_routing.h +++ b/vpr/src/route/connection_based_routing.h @@ -1,10 +1,10 @@ #pragma once + #include #include -#include "route_tree_fwd.h" -#include "vpr_types.h" #include "timing_info.h" #include "vpr_net_pins_matrix.h" +#include "connection_based_routing_fwd.h" /***************** Connection based rerouting **********************/ // encompasses both incremental rerouting through route tree pruning diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h index f5bb7c57aa9..ad888834896 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/connection_router.h @@ -22,12 +22,12 @@ */ #include "connection_router_interface.h" +#include "globals.h" #include "rr_graph_storage.h" -#include "route_common.h" #include "router_lookahead.h" #include "route_tree.h" -#include "rr_rc_data.h" #include "router_stats.h" +#include "rr_graph_view.h" #include "spatial_route_tree_lookup.h" /** diff --git a/vpr/src/route/connection_router.tpp b/vpr/src/route/connection_router.tpp index f74b213235f..34774ccf9d5 100644 --- a/vpr/src/route/connection_router.tpp +++ b/vpr/src/route/connection_router.tpp @@ -4,6 +4,7 @@ #include #include "describe_rr_node.h" +#include "route_common.h" #include "rr_graph_fwd.h" #include "vpr_utils.h" diff --git a/vpr/src/route/connection_router_interface.h b/vpr/src/route/connection_router_interface.h index 178768bf5d5..c5b63e57fbf 100644 --- a/vpr/src/route/connection_router_interface.h +++ b/vpr/src/route/connection_router_interface.h @@ -1,9 +1,6 @@ #ifndef _CONNECTION_ROUTER_INTERFACE_H #define _CONNECTION_ROUTER_INTERFACE_H -#include - -#include "heap_type.h" #include "route_tree_fwd.h" #include "rr_graph_fwd.h" #include "vpr_types.h" diff --git a/vpr/src/route/edge_groups.cpp b/vpr/src/route/edge_groups.cpp index 6ca1e36692a..d23d4d248ee 100644 --- a/vpr/src/route/edge_groups.cpp +++ b/vpr/src/route/edge_groups.cpp @@ -2,6 +2,7 @@ #include #include "rr_graph_fwd.h" +#include "vpr_context.h" // Adds non-configurable (undirected) edge to be grouped. // diff --git a/vpr/src/route/edge_groups.h b/vpr/src/route/edge_groups.h index 90236ce3d65..a5521b6d2ec 100644 --- a/vpr/src/route/edge_groups.h +++ b/vpr/src/route/edge_groups.h @@ -7,7 +7,8 @@ #include #include "vpr_types.h" -#include "vpr_context.h" + +struct DeviceContext; // Class for identifying the components of a graph as sets of nodes. // Each node is reachable from any other node in the same set, and diff --git a/vpr/src/route/heap_type.h b/vpr/src/route/heap_type.h index dd722928bcc..6330fc4c0d9 100644 --- a/vpr/src/route/heap_type.h +++ b/vpr/src/route/heap_type.h @@ -2,10 +2,7 @@ #define _HEAP_TYPE_H #include -#include "physical_types.h" #include "device_grid.h" -#include "vtr_memory.h" -#include "vtr_array_view.h" #include "rr_graph_fwd.h" #include "route_path_manager.h" diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index 5a49dadae50..c5f43e5aa3c 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -17,8 +17,7 @@ * Modified: February 2025 ********************************************************************/ -#ifndef _MULTI_QUEUE_D_ARY_HEAP_H -#define _MULTI_QUEUE_D_ARY_HEAP_H +#pragma once #include "device_grid.h" #include "heap_type.h" @@ -129,5 +128,3 @@ class MultiQueueDAryHeap { private: std::unique_ptr pq_; }; - -#endif diff --git a/vpr/src/route/netlist_routers.h b/vpr/src/route/netlist_routers.h index eb8a220f51f..d4cb0a32840 100644 --- a/vpr/src/route/netlist_routers.h +++ b/vpr/src/route/netlist_routers.h @@ -19,13 +19,11 @@ #include "NetPinTimingInvalidator.h" #include "clustered_netlist_utils.h" #include "connection_based_routing_fwd.h" -#include "globals.h" +#include "d_ary_heap.h" #include "heap_type.h" #include "netlist_fwd.h" -#include "partition_tree.h" #include "routing_predictor.h" #include "route_budgets.h" -#include "route_utils.h" #include "router_stats.h" #include "timing_info.h" #include "vpr_net_pins_matrix.h" diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 24913fad6d5..a9300b888cd 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -1,6 +1,7 @@ #include "overuse_report.h" #include +#include "globals.h" #include "physical_types_util.h" #include "vpr_utils.h" #include "vtr_log.h" diff --git a/vpr/src/route/overuse_report.h b/vpr/src/route/overuse_report.h index bae9da1d135..04b52f5846a 100644 --- a/vpr/src/route/overuse_report.h +++ b/vpr/src/route/overuse_report.h @@ -1,8 +1,7 @@ #pragma once -#include "rr_graph_storage.h" +#include "netlist.h" #include "rr_graph_view.h" -#include "globals.h" #include #include diff --git a/vpr/src/route/parallel_connection_router.cpp b/vpr/src/route/parallel_connection_router.cpp index f3111f156f0..b8d97ceedf7 100644 --- a/vpr/src/route/parallel_connection_router.cpp +++ b/vpr/src/route/parallel_connection_router.cpp @@ -1,6 +1,7 @@ #include "parallel_connection_router.h" #include +#include "d_ary_heap.h" #include "route_tree.h" #include "rr_graph_fwd.h" diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index 18d873e0c6e..b6db78a0d0f 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -3,7 +3,6 @@ #include "connection_router.h" -#include "d_ary_heap.h" #include "multi_queue_d_ary_heap.h" #include diff --git a/vpr/src/route/partition_tree.cpp b/vpr/src/route/partition_tree.cpp index 497f887cf74..7073db231be 100644 --- a/vpr/src/route/partition_tree.cpp +++ b/vpr/src/route/partition_tree.cpp @@ -1,7 +1,9 @@ #include "partition_tree.h" #include #include +#include #include +#include "globals.h" /** Minimum number of nets inside a partition to continue further partitioning. * Mostly an arbitrary limit. At a certain point, the quality lost due to disturbed net ordering diff --git a/vpr/src/route/partition_tree.h b/vpr/src/route/partition_tree.h index d30d5121492..229ba522152 100644 --- a/vpr/src/route/partition_tree.h +++ b/vpr/src/route/partition_tree.h @@ -1,13 +1,10 @@ #pragma once -#include "serial_connection_router.h" -#include "netlist_fwd.h" -#include "router_stats.h" +#include "netlist.h" +#include "vpr_types.h" #include -#include #include -#include #ifdef VPR_USE_TBB #include diff --git a/vpr/src/route/route_budgets.cpp b/vpr/src/route/route_budgets.cpp index 677450ee034..a223c5629c8 100644 --- a/vpr/src/route/route_budgets.cpp +++ b/vpr/src/route/route_budgets.cpp @@ -22,33 +22,11 @@ #include #include "vpr_error.h" #include "globals.h" -#include "tatum/util/tatum_assert.hpp" - -#include "tatum/timing_analyzers.hpp" -#include "tatum/graph_walkers.hpp" -#include "tatum/analyzer_factory.hpp" - -#include "tatum/TimingGraph.hpp" -#include "tatum/TimingConstraints.hpp" -#include "tatum/TimingReporter.hpp" -#include "tatum/timing_paths.hpp" - -#include "tatum/delay_calc/FixedDelayCalculator.hpp" - -#include "tatum/report/graphviz_dot_writer.hpp" -#include "tatum/base/sta_util.hpp" -#include "tatum/echo_writer.hpp" #include "tatum/TimingGraphFwd.hpp" -#include "slack_evaluation.h" #include "tatum/TimingGraphFwd.hpp" #include "vtr_assert.h" -#include "vtr_log.h" -#include "tatum/report/TimingPathFwd.hpp" -#include "tatum/base/TimingType.hpp" #include "concrete_timing_info.h" -#include "tatum/echo_writer.hpp" -#include "net_delay.h" #include "route_budgets.h" #include "vtr_time.h" diff --git a/vpr/src/route/route_budgets.h b/vpr/src/route/route_budgets.h index 7518027b85f..4d3e1fc03c4 100644 --- a/vpr/src/route/route_budgets.h +++ b/vpr/src/route/route_budgets.h @@ -4,10 +4,10 @@ #ifndef ROUTE_BUDGETS_H #define ROUTE_BUDGETS_H -#include #include #include #include "RoutingDelayCalculator.h" +#include "timing_info.h" enum analysis_type { SETUP, diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 3f6d574b601..7ead8f73cd5 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -7,6 +7,7 @@ #include "logic_types.h" #include "physical_types_util.h" #include "route_export.h" +#include "vpr_utils.h" #if defined(VPR_USE_TBB) #include diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h index 1d6bfb58082..49ac82a690e 100644 --- a/vpr/src/route/route_common.h +++ b/vpr/src/route/route_common.h @@ -4,8 +4,6 @@ * router files and some used globally. */ #include -#include "clustered_netlist.h" -#include "rr_node_fwd.h" #include "router_stats.h" #include "globals.h" diff --git a/vpr/src/route/route_export.h b/vpr/src/route/route_export.h index 971aeba966b..b9c6a28620e 100644 --- a/vpr/src/route/route_export.h +++ b/vpr/src/route/route_export.h @@ -3,13 +3,13 @@ /** @file Function prototypes for functions in route_common.cpp that * are used outside the router modules. */ -#include - -#include "route_common.h" -#include "timing_info_fwd.h" -#include "vpr_types.h" - -#include "RoutingDelayCalculator.h" +#include +#include "clustered_netlist_fwd.h" +#include "netlist.h" +#include "route_tree.h" +#include "rr_graph_fwd.h" +#include "vtr_optional.h" +#include "vtr_vector.h" std::vector collect_congested_rr_nodes(); diff --git a/vpr/src/route/route_net.cpp b/vpr/src/route/route_net.cpp index 4d89ae04cfe..c2718fbf494 100644 --- a/vpr/src/route/route_net.cpp +++ b/vpr/src/route/route_net.cpp @@ -1,7 +1,7 @@ /** @file Impls for non-templated net routing fns & utils */ #include "route_net.h" -#include "stats.h" +#include "connection_based_routing.h" bool check_hold(const t_router_opts& router_opts, float worst_neg_slack) { if (router_opts.routing_budgets_algorithm != YOYO) { @@ -174,16 +174,6 @@ bool should_route_net(const Netlist<>& net_list, return true; } -bool early_exit_heuristic(const t_router_opts& router_opts, const WirelengthInfo& wirelength_info) { - if (wirelength_info.used_wirelength_ratio() > router_opts.init_wirelength_abort_threshold) { - VTR_LOG("Wire length usage ratio %g exceeds limit of %g, fail routing.\n", - wirelength_info.used_wirelength_ratio(), - router_opts.init_wirelength_abort_threshold); - return true; - } - return false; -} - float get_net_pin_criticality(const SetupHoldTimingInfo* timing_info, const ClusteredPinAtomPinsLookup& netlist_pin_lookup, float max_criticality, @@ -221,124 +211,6 @@ float get_net_pin_criticality(const SetupHoldTimingInfo* timing_info, return pin_criticality; } -size_t calculate_wirelength_available() { - auto& device_ctx = g_vpr_ctx.device(); - const auto& rr_graph = device_ctx.rr_graph; - - size_t available_wirelength = 0; - // But really what's happening is that this for loop iterates over every node and determines the available wirelength - for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { - const e_rr_type channel_type = rr_graph.node_type(rr_id); - if (channel_type == e_rr_type::CHANX || channel_type == e_rr_type::CHANY) { - available_wirelength += rr_graph.node_capacity(rr_id) * rr_graph.node_length(rr_id); - } - } - return available_wirelength; -} - -WirelengthInfo calculate_wirelength_info(const Netlist<>& net_list, size_t available_wirelength) { - size_t used_wirelength = 0; - VTR_ASSERT(available_wirelength > 0); - - auto& route_ctx = g_vpr_ctx.routing(); - -#ifdef VPR_USE_TBB - tbb::combinable thread_used_wirelength(0); - - tbb::parallel_for_each(net_list.nets().begin(), net_list.nets().end(), [&](ParentNetId net_id) { - if (!net_list.net_is_ignored(net_id) - && net_list.net_sinks(net_id).size() != 0 /* Globals don't count. */ - && route_ctx.route_trees[net_id]) { - int bends, wirelength, segments; - bool is_absorbed; - get_num_bends_and_length(net_id, &bends, &wirelength, &segments, &is_absorbed); - - thread_used_wirelength.local() += wirelength; - } - }); - - used_wirelength = thread_used_wirelength.combine(std::plus()); -#else - for (auto net_id : net_list.nets()) { - if (!net_list.net_is_ignored(net_id) - && net_list.net_sinks(net_id).size() != 0 /* Globals don't count. */ - && route_ctx.route_trees[net_id]) { - int bends = 0, wirelength = 0, segments = 0; - bool is_absorbed; - get_num_bends_and_length(net_id, &bends, &wirelength, &segments, &is_absorbed); - - used_wirelength += wirelength; - } - } -#endif - - return WirelengthInfo(available_wirelength, used_wirelength); -} - -t_bb calc_current_bb(const RouteTree& tree) { - auto& device_ctx = g_vpr_ctx.device(); - const auto& rr_graph = device_ctx.rr_graph; - auto& grid = device_ctx.grid; - - t_bb bb; - bb.xmin = grid.width() - 1; - bb.ymin = grid.height() - 1; - bb.layer_min = grid.get_num_layers() - 1; - bb.xmax = 0; - bb.ymax = 0; - bb.layer_max = 0; - - for (auto& rt_node : tree.all_nodes()) { - //The router interprets RR nodes which cross the boundary as being - //'within' of the BB. Only those which are *strictly* out side the - //box are excluded, hence we use the nodes xhigh/yhigh for xmin/xmax, - //and xlow/ylow for xmax/ymax calculations - bb.xmin = std::min(bb.xmin, rr_graph.node_xhigh(rt_node.inode)); - bb.ymin = std::min(bb.ymin, rr_graph.node_yhigh(rt_node.inode)); - bb.layer_min = std::min(bb.layer_min, rr_graph.node_layer(rt_node.inode)); - bb.xmax = std::max(bb.xmax, rr_graph.node_xlow(rt_node.inode)); - bb.ymax = std::max(bb.ymax, rr_graph.node_ylow(rt_node.inode)); - bb.layer_max = std::max(bb.layer_max, rr_graph.node_layer(rt_node.inode)); - } - - VTR_ASSERT(bb.xmin <= bb.xmax); - VTR_ASSERT(bb.ymin <= bb.ymax); - - return bb; -} - -// Initializes net_delay based on best-case delay estimates from the router lookahead -void init_net_delay_from_lookahead(const RouterLookahead& router_lookahead, - const Netlist<>& net_list, - const vtr::vector>& net_rr_terminals, - NetPinsMatrix& net_delay, - const RRGraphView& rr_graph, - bool is_flat) { - t_conn_cost_params cost_params; - cost_params.criticality = 1.; // Ensures lookahead returns delay value - - for (auto net_id : net_list.nets()) { - if (net_list.net_is_ignored(net_id)) continue; - - RRNodeId source_rr = net_rr_terminals[net_id][0]; - - for (size_t ipin = 1; ipin < net_list.net_pins(net_id).size(); ++ipin) { - RRNodeId sink_rr = net_rr_terminals[net_id][ipin]; - - float est_delay = get_cost_from_lookahead(router_lookahead, - rr_graph, - source_rr, - sink_rr, - 0., - cost_params, - is_flat); - VTR_ASSERT(std::isfinite(est_delay) && est_delay < std::numeric_limits::max()); - - net_delay[net_id][ipin] = est_delay; - } - } -} - void update_net_delays_from_route_tree(float* net_delay, const Netlist<>& net_list, ParentNetId inet, diff --git a/vpr/src/route/route_net.h b/vpr/src/route/route_net.h index f996be8b64c..e03b010c5ec 100644 --- a/vpr/src/route/route_net.h +++ b/vpr/src/route/route_net.h @@ -2,20 +2,10 @@ /** @file Net and sink routing functions, and other utils used by them. */ -#include #include -#include "connection_based_routing.h" -#include "connection_router_interface.h" -#include "heap_type.h" #include "netlist.h" #include "route_budgets.h" -#include "route_utils.h" -#include "router_stats.h" -#include "router_lookahead.h" -#include "routing_predictor.h" -#include "rr_graph_type.h" -#include "spatial_route_tree_lookup.h" #include "timing_info_fwd.h" #include "vpr_types.h" #include "vpr_utils.h" diff --git a/vpr/src/route/route_net.tpp b/vpr/src/route/route_net.tpp index 1a5715b7341..dc1cc75dab4 100644 --- a/vpr/src/route/route_net.tpp +++ b/vpr/src/route/route_net.tpp @@ -6,12 +6,14 @@ #include +#include "connection_based_routing.h" #include "connection_router_interface.h" #include "describe_rr_node.h" #include "draw.h" #include "route_common.h" #include "route_debug.h" #include "route_profiling.h" +#include "routing_predictor.h" #include "rr_graph_fwd.h" #include "vtr_dynamic_bitset.h" diff --git a/vpr/src/route/route_path_manager.cpp b/vpr/src/route/route_path_manager.cpp index 03dec823993..58aa565aee5 100644 --- a/vpr/src/route/route_path_manager.cpp +++ b/vpr/src/route/route_path_manager.cpp @@ -1,5 +1,5 @@ #include "route_path_manager.h" -#include "globals.h" +#include "vpr_context.h" PathManager::PathManager() { // Only init data structure if required by RCV diff --git a/vpr/src/route/route_path_manager.h b/vpr/src/route/route_path_manager.h index f1673772193..30377805f03 100644 --- a/vpr/src/route/route_path_manager.h +++ b/vpr/src/route/route_path_manager.h @@ -1,13 +1,10 @@ +#pragma once + #include "rr_graph_fwd.h" -#include "vtr_assert.h" #include -#include #include -#ifndef _PATH_MANAGER_H -#define _PATH_MANAGER_H - /* Extra path data needed by RCV, separated from RTExploredNode struct for performance reasons * Can be accessed by a pointer, won't be initialized unless by RCV * Use PathManager class to handle this structure's allocation and deallocation @@ -115,5 +112,3 @@ class PathManager { // Required by RCV so the router doesn't expand already visited nodes std::set route_tree_nodes_; }; - -#endif diff --git a/vpr/src/route/route_tree.h b/vpr/src/route/route_tree.h index 37e89db16ae..36b5dcabfac 100644 --- a/vpr/src/route/route_tree.h +++ b/vpr/src/route/route_tree.h @@ -81,19 +81,16 @@ */ #include -#include #include #include #include #include "connection_based_routing_fwd.h" #include "route_tree_fwd.h" -#include "vtr_assert.h" #include "spatial_route_tree_lookup.h" #include "vtr_dynamic_bitset.h" #include "vtr_optional.h" #include "vtr_range.h" -#include "vtr_vec_id_set.h" /** * @brief A single route tree node diff --git a/vpr/src/route/route_utilization.cpp b/vpr/src/route/route_utilization.cpp index bb9c5e736e3..e4bb2df36af 100644 --- a/vpr/src/route/route_utilization.cpp +++ b/vpr/src/route/route_utilization.cpp @@ -1,4 +1,6 @@ #include "route_utilization.h" +#include "draw_global.h" +#include "draw_types.h" #include "globals.h" #include "vpr_utils.h" diff --git a/vpr/src/route/route_utilization.h b/vpr/src/route/route_utilization.h index 194df6deb14..228ac842c85 100644 --- a/vpr/src/route/route_utilization.h +++ b/vpr/src/route/route_utilization.h @@ -1,8 +1,7 @@ -#ifndef VPR_ROUTE_UTIL_H -#define VPR_ROUTE_UTIL_H -#include "vpr_types.h" -#include "draw_types.h" -#include "draw_global.h" +#pragma once + +#include "rr_node_types.h" +#include "vtr_ndmatrix.h" vtr::Matrix calculate_routing_avail(e_rr_type rr_type); @@ -17,5 +16,3 @@ vtr::Matrix calculate_routing_avail(e_rr_type rr_type); */ vtr::Matrix calculate_routing_usage(e_rr_type rr_type, bool is_flat, bool is_print); float routing_util(float used, float avail); - -#endif diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index 198d64197e7..d61b6bb56c9 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -12,12 +12,18 @@ #include "overuse_report.h" #include "physical_types_util.h" #include "place_and_route.h" +#include "route_common.h" #include "route_debug.h" #include "VprTimingGraphResolver.h" +#include "route_tree.h" #include "rr_graph.h" #include "tatum/TimingReporter.hpp" +#ifdef VPR_USE_TBB +#include "stats.h" +#endif // VPR_USE_TBB + bool check_net_delays(const Netlist<>& net_list, NetPinsMatrix& net_delay) { constexpr float ERROR_TOL = 0.0001; @@ -504,6 +510,134 @@ void try_graph(int width_fac, is_flat); } +bool early_exit_heuristic(const t_router_opts& router_opts, const WirelengthInfo& wirelength_info) { + if (wirelength_info.used_wirelength_ratio() > router_opts.init_wirelength_abort_threshold) { + VTR_LOG("Wire length usage ratio %g exceeds limit of %g, fail routing.\n", + wirelength_info.used_wirelength_ratio(), + router_opts.init_wirelength_abort_threshold); + return true; + } + return false; +} + +size_t calculate_wirelength_available() { + auto& device_ctx = g_vpr_ctx.device(); + const auto& rr_graph = device_ctx.rr_graph; + + size_t available_wirelength = 0; + // But really what's happening is that this for loop iterates over every node and determines the available wirelength + for (RRNodeId rr_id : device_ctx.rr_graph.nodes()) { + const e_rr_type channel_type = rr_graph.node_type(rr_id); + if (channel_type == e_rr_type::CHANX || channel_type == e_rr_type::CHANY) { + available_wirelength += rr_graph.node_capacity(rr_id) * rr_graph.node_length(rr_id); + } + } + return available_wirelength; +} + +WirelengthInfo calculate_wirelength_info(const Netlist<>& net_list, size_t available_wirelength) { + size_t used_wirelength = 0; + VTR_ASSERT(available_wirelength > 0); + + auto& route_ctx = g_vpr_ctx.routing(); + +#ifdef VPR_USE_TBB + tbb::combinable thread_used_wirelength(0); + + tbb::parallel_for_each(net_list.nets().begin(), net_list.nets().end(), [&](ParentNetId net_id) { + if (!net_list.net_is_ignored(net_id) + && net_list.net_sinks(net_id).size() != 0 /* Globals don't count. */ + && route_ctx.route_trees[net_id]) { + int bends, wirelength, segments; + bool is_absorbed; + get_num_bends_and_length(net_id, &bends, &wirelength, &segments, &is_absorbed); + + thread_used_wirelength.local() += wirelength; + } + }); + + used_wirelength = thread_used_wirelength.combine(std::plus()); +#else + for (auto net_id : net_list.nets()) { + if (!net_list.net_is_ignored(net_id) + && net_list.net_sinks(net_id).size() != 0 /* Globals don't count. */ + && route_ctx.route_trees[net_id]) { + int bends = 0, wirelength = 0, segments = 0; + bool is_absorbed; + get_num_bends_and_length(net_id, &bends, &wirelength, &segments, &is_absorbed); + + used_wirelength += wirelength; + } + } +#endif + + return WirelengthInfo(available_wirelength, used_wirelength); +} + +t_bb calc_current_bb(const RouteTree& tree) { + auto& device_ctx = g_vpr_ctx.device(); + const auto& rr_graph = device_ctx.rr_graph; + auto& grid = device_ctx.grid; + + t_bb bb; + bb.xmin = grid.width() - 1; + bb.ymin = grid.height() - 1; + bb.layer_min = grid.get_num_layers() - 1; + bb.xmax = 0; + bb.ymax = 0; + bb.layer_max = 0; + + for (const RouteTreeNode& rt_node : tree.all_nodes()) { + //The router interprets RR nodes which cross the boundary as being + //'within' of the BB. Only those which are *strictly* out side the + //box are excluded, hence we use the nodes xhigh/yhigh for xmin/xmax, + //and xlow/ylow for xmax/ymax calculations + bb.xmin = std::min(bb.xmin, rr_graph.node_xhigh(rt_node.inode)); + bb.ymin = std::min(bb.ymin, rr_graph.node_yhigh(rt_node.inode)); + bb.layer_min = std::min(bb.layer_min, rr_graph.node_layer(rt_node.inode)); + bb.xmax = std::max(bb.xmax, rr_graph.node_xlow(rt_node.inode)); + bb.ymax = std::max(bb.ymax, rr_graph.node_ylow(rt_node.inode)); + bb.layer_max = std::max(bb.layer_max, rr_graph.node_layer(rt_node.inode)); + } + + VTR_ASSERT(bb.xmin <= bb.xmax); + VTR_ASSERT(bb.ymin <= bb.ymax); + + return bb; +} + +// Initializes net_delay based on best-case delay estimates from the router lookahead +void init_net_delay_from_lookahead(const RouterLookahead& router_lookahead, + const Netlist<>& net_list, + const vtr::vector>& net_rr_terminals, + NetPinsMatrix& net_delay, + const RRGraphView& rr_graph, + bool is_flat) { + t_conn_cost_params cost_params; + cost_params.criticality = 1.; // Ensures lookahead returns delay value + + for (ParentNetId net_id : net_list.nets()) { + if (net_list.net_is_ignored(net_id)) continue; + + RRNodeId source_rr = net_rr_terminals[net_id][0]; + + for (size_t ipin = 1; ipin < net_list.net_pins(net_id).size(); ++ipin) { + RRNodeId sink_rr = net_rr_terminals[net_id][ipin]; + + float est_delay = get_cost_from_lookahead(router_lookahead, + rr_graph, + source_rr, + sink_rr, + 0.0f /* R_upstream */, + cost_params, + is_flat); + VTR_ASSERT(std::isfinite(est_delay) && est_delay < std::numeric_limits::max()); + + net_delay[net_id][ipin] = est_delay; + } + } +} + #ifndef NO_GRAPHICS void update_draw_pres_fac(const float new_pres_fac) { #else diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index 5cac4fbb045..71e3dc895dd 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -6,7 +6,6 @@ #include "router_stats.h" #include "timing_info.h" #include "vpr_net_pins_matrix.h" -#include "vpr_types.h" #include "RoutingDelayCalculator.h" diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index 30180eb7e14..ff9e6e76cb4 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -5,7 +5,6 @@ #include "route_export.h" #include "route_tree.h" #include "rr_graph.h" -#include "vtr_time.h" RouterDelayProfiler::RouterDelayProfiler(const Netlist<>& net_list, const RouterLookahead* lookahead, diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h index 082349a9a07..e03d62abbd9 100644 --- a/vpr/src/route/router_delay_profiling.h +++ b/vpr/src/route/router_delay_profiling.h @@ -1,7 +1,9 @@ -#ifndef ROUTER_DELAY_PROFILING_H_ -#define ROUTER_DELAY_PROFILING_H_ +#pragma once -#include "vpr_types.h" +#include "d_ary_heap.h" +#include "netlist.h" +#include "router_lookahead.h" +#include "router_stats.h" #include "serial_connection_router.h" #include @@ -60,5 +62,3 @@ void alloc_routing_structs(const t_chan_width& chan_width, bool is_flat); void free_routing_structs(); - -#endif /* ROUTER_DELAY_PROFILING_H_ */ diff --git a/vpr/src/route/routing_predictor.cpp b/vpr/src/route/routing_predictor.cpp index 4f0f69a28a0..4b8e156d52c 100644 --- a/vpr/src/route/routing_predictor.cpp +++ b/vpr/src/route/routing_predictor.cpp @@ -1,7 +1,6 @@ #include #include #include -#include #include "vtr_assert.h" diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp index 99c1a729e6c..5fed7376669 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -517,8 +517,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, y, describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } - } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) { - // Sources have co-ordinates covering the entire block they are in, but not sinks + } else if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK || rr_graph.node_type(inode) == e_rr_type::MEDIUM) { if (!rr_graph.x_in_node_range(x, inode)) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", rr_graph.node_xlow(inode), diff --git a/vpr/src/route/segment_stats.cpp b/vpr/src/route/segment_stats.cpp index 3d7de733ce3..968a12d0c6d 100644 --- a/vpr/src/route/segment_stats.cpp +++ b/vpr/src/route/segment_stats.cpp @@ -1,8 +1,6 @@ #include "vtr_log.h" -#include "vtr_memory.h" -#include "vpr_types.h" #include "globals.h" #include "segment_stats.h" diff --git a/vpr/src/route/segment_stats.h b/vpr/src/route/segment_stats.h index 346355c168a..a040ab08b0d 100644 --- a/vpr/src/route/segment_stats.h +++ b/vpr/src/route/segment_stats.h @@ -1 +1,6 @@ +#pragma once + +#include +#include "physical_types.h" + void get_segment_usage_stats(std::vector& segment_inf); diff --git a/vpr/src/route/serial_connection_router.cpp b/vpr/src/route/serial_connection_router.cpp index 3bb2d2b64a2..4a5c074970c 100644 --- a/vpr/src/route/serial_connection_router.cpp +++ b/vpr/src/route/serial_connection_router.cpp @@ -1,7 +1,7 @@ #include "serial_connection_router.h" #include -#include "rr_graph.h" +#include "d_ary_heap.h" #include "rr_graph_fwd.h" /** Used to update router statistics for serial connection router */ diff --git a/vpr/src/route/serial_connection_router.h b/vpr/src/route/serial_connection_router.h index 2cd23f1460e..990c93c29fb 100644 --- a/vpr/src/route/serial_connection_router.h +++ b/vpr/src/route/serial_connection_router.h @@ -3,8 +3,6 @@ #include "connection_router.h" -#include "d_ary_heap.h" - /** * @class SerialConnectionRouter implements the AIR's serial timing-driven connection router * @details This class routes from some initial set of sources (via the input rt tree) to a diff --git a/vpr/src/route/sink_sampling.h b/vpr/src/route/sink_sampling.h index 341a292db7f..6277d554075 100644 --- a/vpr/src/route/sink_sampling.h +++ b/vpr/src/route/sink_sampling.h @@ -14,7 +14,6 @@ #include "globals.h" #include "partition_tree.h" #include "route_common.h" -#include "router_lookahead_sampling.h" /** Sink container for geometry operations */ struct SinkPoint { diff --git a/vpr/src/route/spatial_route_tree_lookup.h b/vpr/src/route/spatial_route_tree_lookup.h index 9ac1ac3c23f..1766f972c58 100644 --- a/vpr/src/route/spatial_route_tree_lookup.h +++ b/vpr/src/route/spatial_route_tree_lookup.h @@ -1,5 +1,5 @@ -#ifndef VPR_SPATIAL_ROUTE_TREE_LOOKUP_H -#define VPR_SPATIAL_ROUTE_TREE_LOOKUP_H +#pragma once + #include #include "vpr_types.h" @@ -7,6 +7,7 @@ #include "netlist.h" #include "route_tree_fwd.h" +#include "vtr_vector.h" typedef vtr::Matrix>> SpatialRouteTreeLookup; @@ -21,5 +22,3 @@ size_t grid_to_bin_x(size_t grid_x, const SpatialRouteTreeLookup& spatial_lookup size_t grid_to_bin_y(size_t grid_y, const SpatialRouteTreeLookup& spatial_lookup); bool validate_route_tree_spatial_lookup(const RouteTreeNode& rt_node, const SpatialRouteTreeLookup& spatial_lookup); - -#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 887b876defd..68bee2bbebf 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -48,7 +48,7 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, std::vector io_side = {TOP, RIGHT, BOTTOM, LEFT}; /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids.get_physical_type(tile_loc))) { + if (grids.get_physical_type(tile_loc)->is_io()) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); vtr::Point grid_coordinate(ix, iy); io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb); @@ -745,7 +745,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, std::vector wanted_sides{TOP, RIGHT, BOTTOM, LEFT}; /* If this is the block on borders, we consider IO side */ - if (true == is_io_type(grids.get_physical_type(tile_loc))) { + if (grids.get_physical_type(tile_loc)->is_io()) { vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); wanted_sides = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb); } diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index c81b00db08e..525e4bd9626 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -7,6 +7,7 @@ #include "vpr_types.h" #include "vtr_vector.h" #include "atom_pb_bimap.h" +#include #include #include From cc0302d6dce92bcaebe73e7ba208af810661a4c7 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Tue, 10 Jun 2025 20:44:01 -0400 Subject: [PATCH 453/453] Update OpenFPGA (#3126) * pass t_chan_width by reference * doxygen comment for alloc_and_load_rr_node_indices * add doxygen comments for load_block_rr_indices() * [AP][Solver] Enabled Parallel Eigen The Eigen solver has the ability to use OpenMP to run the solver computations in parallel. Made the AP flow use the num_workers option to set the number of threads that Eigen can use. VPR did not have the ability to build with OpenMP in its CMAKE. Added an option to the CMAKE to allow the user to enable OpenMP. * undid a couple changes to fix odin memory leak * [vpr][place] expand search range if block is io * Revert "[vpr][place] expand search range if block is io" This reverts commit af29e9dc29442621caef06df662bba4e5d161308. * Revert "make format" This reverts commit caaf456bfd45a947cae7a90f2766ddd754b682be. * Revert "[vpr][place] move MIN_BLK_PER_COLUMN_EXPAND into the routine" This reverts commit 4a6e3333fde71c2edda9ea42366d72cdad376586. * Revert "make format" This reverts commit 96e9cc5c43a4940ec7e7482a63d6b031f744abdd. * Revert "[vpr][place] pass block_constraint parameter to relevant functions in initial placement to prevent search range to be adjusted" This reverts commit ade994b4c7e69b154639f086837ed27481d925a5. * Revert "[vpr][place] use a constexpr to compare the number of blocks in column" This reverts commit dae25cc77545a21498d9fcb738c386382236886f. * Revert "[vpr][place] remove adjust search range and adjust it inside find_compatible_compressed_loc_in_range" This reverts commit f9e85172388b2cb4ed45da36c95ea9132a4ec84e. * [vpr][place] move adjust_search_range to move_utils.h so it can be accessed by initial placement * [vpr][place] add adjust search range to find centriod neighbour * remove unused is_flat argument from alloc_and_load_rr_node_indices() and load_block_rr_indices() * use (x, y) convention for CHANX instead of (y, x) * make format * cast x/y to size_t * get rid of warnings in RRSpatialLookup::find_nodes() * Add references to the main VTR papers in the documentation. * Add link to the VTR 9 paper in the documentation * Add link to the VTR 9 paper in the README * [vpr][place] remove a special case in find_compatible_compressed_loc_in_range * add a closing ) to the text printed by node_coordinate_to_string() * fix the x/y mismatch for CHANX nodes in rr_nodes and rr_node_indices * reserve nodes using x/y instead of chan/seg * fix a typo * add rr_graph_genearion directory * resize node lookup for CHANX nodes in RR graph serializer * add rr_node_indices.cpp/.h * add doxygen comment for load_chan_rr_indices() * [Infra] Updated Install Packages Script For Backwards Compatibility The install_apt_packages.sh script is no longer backward compatible with older versions of Ubuntu due to the dependency on clang-format-18. Added an if statement to check if the distribution can support clang-format-18 and only installing it if it can. Added this script to the CI build process so it can always be tested within the CI to prevent future regression. * [RegTest] Disabled `strong_multiclock` test for parallel connection router Temporarily disabled the `strong_multiclock` test in `vtr_reg_strong` CI regression tests for the parallel connection router, due to some random failures as mentioned in Issue #3029. After fixing the problem with the `strong_multiclock` test, this will be reactivated. * [doc] update the doc with new report format * [RegTest] Updated golden results for `strong_multiclock` regression test Removed the golden results of parallel connection router test cases for `strong_multiclock` regression test. * [vpr][analysis] use std::min/max instead of if condition * Add documentation for include sanitization * [vpr][analysis] change report_net_timing format to csv * [vpr][analysis] update comments * [vpr][analysis] print constant nets in the net timing report * [vpr][analysis] apply comments * [vpr][analysis] fix function name * [doc] add net timing report use case * fix a typo * [Infra] Cleaned Up Include Files in VPR Base Directory Many include files in the base directory contained includes to other headers which they do not use. This causes many CPP files to include way more header files than they need, increasing the incremental build time. This process needs to be done on the entire VTR repo, but I found that the base directory was one of the biggest culprits of this and the hardest to untangle. * [FGParallelRouter] Updated Barrier to C++20 Std Barrier The fine-grained parallel router was originally built before VTR upgraded to C++20, so we had to roll our own barrier. We originally had two barriers: spin barriers (thread spin on a lock while waiting) and a "mutex" barrer (where threads wait on a condition variable and potentially went to sleep). Through experimentation, found that the choice of barrier implementation did not matter; however, the standard barrier provides slight performance improvements for very long routes and has a much cleaner interface. Moved the FG parallel router to the standard barrier. The old implementations are left in as classes in case c++20 is not preferred for some users. Also added a QoR script to make parsing FG parallel router runs easier. * [Infra] Cleaned Up Header Files in Pack Folder Went through the header files in the pack folder and resolved any unused header files. * [AP] Removed Old Cluster-Level AP Flow Prior to the flat AP flow, a cluster-level AP flow existed in VPR which performed a SimPL-style algorithm on the clusters created during packing before performing a placement quench. Although well-written, this flow was not shown to outperform the SA placer in VPR. It has also been becoming confusing to keep in VPR since the new flat AP flow supercedes it. It is unclear if a cluster-level AP flow will work well with the flat AP flow; however in that case the cluster-level AP flow would be made using the new AP APIs written. Removed the old cluster-level AP flow to reduce confusion. * [Infra] Cleaned Up Header Files in Place Folder * make is_io_type() a member function of t_physical_tile_type * replace calls to is_io_type() with t_physical_tile_type::is_io() * make format * inline t_physical_tile_type::is_io() * add doxygen comments for alloc_and_load_tile_rr_node_indices() * document alloc_and_load_rr_node_indices() arguments * made a few function operating on t_pb_type its member functions * add router_lookahead directory * [STA] Added Multiclock Incremental STA Consistency Check The incremental STA consistency coverage was very good, but was just missing a multiclock circuit with an SDC file. Added a quick test. * add show-resource-usage mode * add --show_resource_usage to command_line_usage.rst * run 'make format' * fix drawing contour style in draw_crit_path_elements * make format * fixes in VPR Viewer for flat_routing=on * fix build errors after cherry-pick * remove inner //hotfix-vpr-flat-routing-viewer mark toseparate one hotfix from another * [Infra] Cleaned Up Header Files in Route Folder Continued the header file cleanup effort in the route folder. Some of these files may need to be revisited in more detail, but got some of the major header include issues. Found that some definitions were in the wrong place, so moved them to the correct implementation file. * [Infra] Updated Header Files Based on Comments Moved to pragma once symantics and cleaned up some less than ideal code. * make format * [Infra] Cleaned Up Includes in Analysis, Power, and Util Dirs Continued the cleanup into the analysis, power, and util directories. Nothing majorly changed. * [FASM] Fixed Bug With Wire Creation Found a bug within FASM's wire generation where it uses the index of the output pin to create the wire instead of the index of the input pin. This stemmed from some confusing code which both verified that the wire was being used and returning the first valid pin. It just so happens that it checked the outputs first and returned the output pin instead. Cleaned up the code and added more error checking to prevent issues like this in the future. * [FASM] Updated Documentation Based on PR Review * replace keyword `auto` with specific type * Change GreedySeedSelector to work with molecules instead of atoms * [Infra] Cleaned Up Includes in Draw Dir Cleaned up the includes in the draw files. These ones were much messier than I originally thought. Many of the header files in the draw directory included way more than they needed which was causing false dependencies anywhere in VPR which included any draw files. * replaced t_clock_arch with std::shared_ptr> * rename vpr_show_resource_usage to vpr_print_arch_resources, to not confuse with existed print_resource_usage(). the new name more clear explain function flow. * remove unnecessary shortcut std::string device_layout_variant = l.name in vpr_print_arch_resources() * remove "auto num_instances = 0;" in vpr_print_arch_resources * replace auto with specific type in expression "for (const auto equivalent_tile : type.equivalent_tiles" * get red of keyword auto in vpr_print_arch_resources method * Added EZGL docs under API * fix 'possibly dangling reference to a temporary' * refactor server/gateio module. idea is to include any sockpp header directly in gateio.cpp transaction unit. this helps avoid win32 enum names collision with enums defined in VTR if gateio.h is included. * make format * [CI] Added Serial Execution Engine Test Since the CI always installs oneTBB and the execution engine is set to auto, I found that the CI always tested with the tbb execution engine. Some users may not have oneTBB installed for one reason or another and we need to ensure that VTR always builds. Added a CI test which sets the parallel execution engine to serial for Tatum and VPR. * [CI] Removed Redundant Warning Test Prior to the updates to the CI to make all regression tests warning clean, there was another warning test which was not as comprehensive as the tests we have now. Since this test was superceded, removed it from the CI. The CMAKE param that enabled it was also used and replaced with a more comprehensive CMAKE option. * Have readthedocs install base requirements.txt packages * Repaced prop and value in t_pin_to_pin_annotation with std::pair * replaced char[level+1] with std::string * [Infra] The Big VPR Pragma Commit VPR is moving to a style that uses "#pragma once" instead of header gaurds. These are less error prone and may be slightly more performant. Converted all of the header gaurds in VPR into pragma once's. Also moved all pragma onces to the top of all header files to maintain a consistent style. It is a good idea to have them as the very first line in all header files. While going through all header files, cleaned up any extra header includes which were including things they did not need. * Added basic information on building with debug information and turning on verbosity to the developer guide. * [HotFix] Fix Failing Python Formatting Check A failing python formatting check got into Master. Fixing it. * [libs][utils] remove redundant helper functions * remove is_net_unrouted, replace it with more appropriate logic * [libs][physical_types] add is_io to logical block * [vpr][place] use logic block is_io * move is_net_fully_absorbed to route_utils.h * changed calloc to new * fixed memory leak * [vpr][place] update initial placement to limit set search range based on placement constraints * [vpr][place] adjust search range if number of blocks in the column is less that a certain number * [vpr][place] pass search_range by value * make format * Clean up the usage tracking in grid blocks. * [CI] Consolidated Build Variation Tests Different build variations of VTR were being run on different CI runners which was wasteful. Consolidated these build variations into a single job which will run on a single runner. * revert bool is_net_routed(ParentNetId net_id); as using net_stats is not robust for stage except the route. add doxygen doc for is_net_routed and is_net_fully_absorbed * make format * added default constructors * Documenting get_usage method in grid blocks * fixed build issues and improved pair for loops * Upload vpr.out in nightly_test_manual artifacts * [vpr][place] replace auto key word with variable type * Clean up auto types from grid blocks * [Infra] Cleaned Up Includes in Non-External Libs Updated the header files in the non-external libraries of VTR such that they use pragma once instead of ifdefs and removed false include files. * [Router] Fixed the Segfault Bug in Parallel Connection Router Fixed https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/3029. Switched from detaching helper threads to joining threads in parallel connection router to ensure that helper threads terminate before main thread destroys the parallel connection router object. * [AP][Legalizer] Added Ability to Generate a Mass Report While working on the mass abstraction in the partial legalizer of the globlal placer, found that I needed a lot more information on the device to be able to debug the mass calculations. Added a command-line option which will generate a mass report if requested. This mass report contains useful information on the device, the netlist, and the mass / capacities computed in the mass calculator. * [AP][Legalizer] Updated Mass Report Based on PR Comments * renamed pairs and replaced .first and .second with ={} notation * removed unecessary if statements to check for nullptr * moved loop variable definitions to loop * make format * [AP][Timing] Used Flat Placement Info to Compute Setup Criticalities When timing analysis was turned on for AP, we originally only used the pre-cluster timing analyzer which was very high-level and innacurate. It practically just counted the number of hops between launch and capture registers to approximate criticality. Improved this by using flat placement information provided by AP. During global placement, the criticality of all edges are recomputed using the upper bound solution from the prior iteration of GP. The place delay model from the placement flow was used to get an mostly-accurate delay estimation for distances between tiles. The slacks computed each GP iteration are used to update the net weights between iterations to better optimize CPD and sTNS. This improved estimation of setup slacks is then passed into the full legalizer, which it is then used by the packer to better pack critical atoms together. This change required some changes to the APNetlist. Notably, we need all atom nets to be located somewhere in the AP netlist such that their delays can be calculated properly. Instead of removing nets we do not care about for AP, marked them as ignored. * [AP][Timing] Updated Comments for Timing * [AP][Timing] More Updates to Comments * [Infra] Fixed False Forward Declarations The Clang builds were warning that there were several forward declarations of structs which were supposed to be classes and vice-versa. This is not necessarily a problem since in C++ classes and structs end up being basically the same from the compiler's perspective, but its still incorrect. Fixed the cases I could see in the Clang builds. * [test] update golden results * update golden results * Bump libs/EXTERNAL/libcatch2 from `5abfc0a` to `74fcff6` Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `5abfc0a` to `74fcff6`. - [Release notes](https://github.com/catchorg/Catch2/releases) - [Commits](https://github.com/catchorg/Catch2/compare/5abfc0aa9c1ef4cb40c9f387495134dab02e1af2...74fcff6e5b190fb833a231b7f7c1829e3c3ac54d) --- updated-dependencies: - dependency-name: libs/EXTERNAL/libcatch2 dependency-version: 74fcff6e5b190fb833a231b7f7c1829e3c3ac54d dependency-type: direct:production ... Signed-off-by: dependabot[bot] * [test] update golden result * [test][nightly_test_3] change seed from 5 to 3 * [Infra] Converted Pin to Pin Annotations into Vector Pin to Pin annotations were stored as C-style arrays which creates confusing pointers around VTR. Converted to a standard vector. * Improve makefile build types documentation * [STA] Fixed Visual Bug in Post-Implementation SDC While presenting my tutorial on post-implementation timing analysis, I found that the SDC file generated did not look quite right. It was functionally correct, but some of the new-line characters were missing. Added the missing new line characters. * [STA] Added Tutorial Video to Timing Analysis Tutorial * [CI] Added Quick Titanium S10 Tests The titanium benchmarks were not being tested by the CI. Added the Titanium benchmarks which could be run in under around 2 hours to NightlyTest7. 5 circuits in this benchmark set currently fail through VTR. The failures are mainly in the initial placer, which is struggling to create an initial placement when logical blocks can be placed into different physical block types which are constrained resources. * [libs][libarch] add reverse map for pin_physical_num to pb_pin * [vpr][util] add get_atom_pin_rr_node_id * [vpr][utils] add comment for get_atom_pin_rr_node_id * make format * [libs][archfpga] use pb_pin_to_pin_num to return pb_pin physical_num * Revert "[libs][archfpga] use pb_pin_to_pin_num to return pb_pin physical_num" This reverts commit ffe3c7cbcfc0528d28fcf03a4d4d26a2d38d45ea. * Update golden results * apply review comments * fixed duplicate items * [AP] Optimized Primitive Vector Class The primitive vector class was assumed to be quite sparse, and as such used an unordered map as its internal data structure. Found through experimentation that most of the time in the partial legalizer was being spent in the operations of the primitive vector class. Also, while improving the mass abstraction, I found a need to separate logical models from the dimensions of the primitive vector to allow multiple models to point to the same dimension in the primitive vector. This PR kills two birds with one stone by turning the unordered map into a VTR vector map and creating a new PrimitiveVectorDim which can allow the models to be separate from the dimensions. Future PRs will make use of this feature to improve the mass abstraction. * Added --read_initial_place_file and clarified options that took clustered placement file formats. * Clarified that --write_initial_place_file is for a clustered placement. * deleted comment * Update ezgl to use submodules * documentation fix * [lib][libarch] add sstream lib * fix compile errors * [CI] Added Test Suite Verification to CI Found that we were regressing on many features in VTR due to tasks being added to the appropriate test suite directory, but not being included in the necessary task list. As such, it appeared as though the tests were being run, but in reality they were not. Added a script which will be run by the CI which will verify that all of the test suites that we care about have all their tasks in the appropriate task list. From this tool, found many tasks which were not in the task lists. Marked these tasks as "ignored" for now. These should be handled in a separate PR. * update libcatch2 * [test][ap] fix config file * remove redundant declerations * [libs][rr_graph] add rr_graph def to fwd * [libs][capnp] fix a typo in cmake file * [libs][arch] remove redundant code * [vtr_flow][task] fix config file * [test][strong] fix tileable test --------- Signed-off-by: dependabot[bot] Co-authored-by: soheilshahrouz Co-authored-by: AlexandreSinger <49374526+AlexandreSinger@users.noreply.github.com> Co-authored-by: AlexandreSinger Co-authored-by: SamuelHo10 Co-authored-by: mohamedElgammal Co-authored-by: vaughnbetz Co-authored-by: Hang Yan Co-authored-by: Amir Poolad Co-authored-by: Soheil Shahrouz <80951211+soheilshahrouz@users.noreply.github.com> Co-authored-by: Oleksandr Co-authored-by: Amir Poolad <54797949+AmirhosseinPoolad@users.noreply.github.com> Co-authored-by: w0lek <141943514+w0lek@users.noreply.github.com> Co-authored-by: Samuel <60633644+SamuelHo10@users.noreply.github.com> Co-authored-by: Jeff Goeders Co-authored-by: Vaughn Betz Co-authored-by: haydar-c Co-authored-by: haydar-c <82066544+haydar-c@users.noreply.github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> --- .github/workflows/nightly_test_manual.yml | 1 + .github/workflows/test.yml | 124 +- .gitmodules | 4 + .readthedocs.yaml | 4 + CMakeLists.txt | 1 - Makefile | 18 +- README.developers.md | 10 +- dev/subtree_config.xml | 5 - .../test_suites_info.json | 85 + .../verify_test_suites.py | 240 ++ doc/_doxygen/ezgl.dox | 13 + doc/src/api/ezgl/application.rst | 6 + doc/src/api/ezgl/callback.rst | 56 + doc/src/api/ezgl/camera.rst | 5 + doc/src/api/ezgl/canvas.rst | 5 + doc/src/api/ezgl/color.rst | 5 + doc/src/api/ezgl/control.rst | 41 + doc/src/api/ezgl/graphics.rst | 5 + doc/src/api/ezgl/index.rst | 20 + doc/src/api/ezgl/point.rst | 6 + doc/src/api/ezgl/rectangle.rst | 5 + doc/src/conf.py | 1 + doc/src/index.rst | 1 + doc/src/tutorials/timing_analysis/index.rst | 2 + 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+++++++-------- .../config/config.txt | 2 +- .../config/golden_results.txt | 40 +- .../titan_s10_qor/config/golden_results.txt | 30 +- .../config/golden_results.txt | 8 +- .../vtr_reg_nightly_test7/task_list.txt | 1 + .../titanium_s10_quick_qor/config/config.txt | 58 + .../config/golden_results.txt | 17 + .../gen_mass_report/config/config.txt | 28 + .../gen_mass_report/config/golden_results.txt | 2 + .../no_fixed_blocks/config/golden_results.txt | 12 +- .../vtr_chain/config/golden_results.txt | 10 +- .../config/golden_results.txt | 2 +- .../strong_multiclock/config/config.txt | 6 +- .../config/golden_results.txt | 3 + .../config/golden_results.txt | 2 +- .../config/config.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../strong_power/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- 584 files changed, 5648 insertions(+), 13960 deletions(-) create mode 100644 dev/vtr_test_suite_verifier/test_suites_info.json create mode 100755 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mode 100644 libs/EXTERNAL/libezgl/examples/CMakeLists.txt delete mode 100644 libs/EXTERNAL/libezgl/examples/basic-application/.gresource.xml delete mode 100644 libs/EXTERNAL/libezgl/examples/basic-application/CMakeLists.txt delete mode 100644 libs/EXTERNAL/libezgl/examples/basic-application/Makefile delete mode 100644 libs/EXTERNAL/libezgl/examples/basic-application/basic_application.cpp delete mode 100644 libs/EXTERNAL/libezgl/examples/basic-application/main.ui delete mode 100644 libs/EXTERNAL/libezgl/examples/basic-application/small_image.png delete mode 100644 libs/EXTERNAL/libezgl/examples/raw-gtk/CMakeLists.txt delete mode 100644 libs/EXTERNAL/libezgl/examples/raw-gtk/main.ui delete mode 100644 libs/EXTERNAL/libezgl/examples/raw-gtk/raw-gtk.cpp delete mode 100644 libs/EXTERNAL/libezgl/gcr-cmake/LICENSE delete mode 100644 libs/EXTERNAL/libezgl/gcr-cmake/README.md delete mode 100644 libs/EXTERNAL/libezgl/gcr-cmake/macros/BuildTargetScript.cmake delete mode 100644 libs/EXTERNAL/libezgl/gcr-cmake/macros/CompileGResources.cmake delete mode 100644 libs/EXTERNAL/libezgl/gcr-cmake/macros/GenerateGXML.cmake delete mode 100644 libs/EXTERNAL/libezgl/gcr-cmake/macros/GlibCompileResourcesSupport.cmake delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/application.hpp delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/callback.hpp delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/camera.hpp delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/canvas.hpp delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/color.hpp delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/control.hpp delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/graphics.hpp delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/point.hpp delete mode 100644 libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp delete mode 100644 libs/EXTERNAL/libezgl/options.cmake delete mode 100644 libs/EXTERNAL/libezgl/src/application.cpp delete mode 100644 libs/EXTERNAL/libezgl/src/callback.cpp delete mode 100644 libs/EXTERNAL/libezgl/src/camera.cpp delete mode 100644 libs/EXTERNAL/libezgl/src/canvas.cpp delete mode 100644 libs/EXTERNAL/libezgl/src/control.cpp delete mode 100644 libs/EXTERNAL/libezgl/src/graphics.cpp create mode 100644 vpr/src/analytical_place/ap_mass_report.cpp create mode 100644 vpr/src/analytical_place/ap_mass_report.h create mode 100644 vpr/src/analytical_place/primitive_dim_manager.h create mode 100644 vpr/src/analytical_place/primitive_vector_fwd.h create mode 100644 vtr_flow/parse/qor_config/qor_fg_parallel_router_fixed_chan_width.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/golden_results.txt create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/golden_results.txt diff --git a/.github/workflows/nightly_test_manual.yml b/.github/workflows/nightly_test_manual.yml index 5bf32327050..0ad4ce31e52 100644 --- a/.github/workflows/nightly_test_manual.yml +++ b/.github/workflows/nightly_test_manual.yml @@ -112,4 +112,5 @@ jobs: name: nightly_test_results path: | vtr_flow/**/*.log + vtr_flow/**/vpr.out vtr_flow/**/parse_results*.txt diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 5977e1221ba..fc80c9d523e 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -99,7 +99,26 @@ jobs: run: ./dev/${{ matrix.script }} - UniTests: + VerifyTestSuites: + runs-on: ubuntu-24.04 + name: 'Verify Test Suites' + steps: + + - uses: actions/setup-python@v5 + with: + python-version: 3.12.3 + + - uses: actions/checkout@v4 + # NOTE: We do not need sub-modules. This only verifies the tests, does not run them. + + - name: 'Run test suite verification' + run: | + ./dev/vtr_test_suite_verifier/verify_test_suites.py \ + -vtr_regression_tests_dir vtr_flow/tasks/regression_tests \ + -test_suite_info dev/vtr_test_suite_verifier/test_suites_info.json + + + UnitTests: name: 'U: C++ Unit Tests' runs-on: ubuntu-24.04 steps: @@ -125,36 +144,90 @@ jobs: run: ./.github/scripts/unittest.sh - Warnings: - name: 'W: Check Compilation Warnings' + # This test builds different variations of VTR (with different CMake Params) + # and ensures that they can run the basic regression tests. This also ensures + # that these build variations are warning clean. + BuildVariations: runs-on: ubuntu-24.04 + name: 'B: Build Variations' + env: + # For the CI, we want all build variations to be warning clean. + # NOTE: Need to turn IPO off due to false warnings being produced. + COMMON_CMAKE_PARAMS: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off' steps: - uses: actions/setup-python@v5 with: python-version: 3.12.3 + - uses: actions/checkout@v4 with: submodules: 'true' - - name: Get number of CPU cores + - name: 'Get number of CPU cores' uses: SimenB/github-actions-cpu-cores@v2 id: cpu-cores - - name: Install dependencies + - name: 'Install dependencies' run: ./.github/scripts/install_dependencies.sh - - uses: hendrikmuhs/ccache-action@v1.2 + - name: 'ccache' + uses: hendrikmuhs/ccache-action@v1.2 - - name: Test + - name: 'Test with VTR_ASSERT_LEVEL 4' + if: success() || failure() env: - #In order to get compilation warnings produced per source file, we must do a non-IPO build - #We also turn warnings into errors for this target by doing a strict compile - CMAKE_PARAMS: "-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_STRICT_COMPILE=on -DVTR_IPO_BUILD=off" + CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ASSERT_LEVEL=4" NUM_PROC: ${{ steps.cpu-cores.outputs.count }} run: | + rm -f build/CMakeCache.txt export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - ./.github/scripts/build.sh + make -j${{ steps.cpu-cores.outputs.count}} + ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}} + + - name: 'Test with NO_GRAPHICS' + if: success() || failure() + env: + CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_EZGL=off" + NUM_PROC: ${{ steps.cpu-cores.outputs.count }} + run: | + rm -f build/CMakeCache.txt + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + make -j${{ steps.cpu-cores.outputs.count}} + ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}} + + - name: 'Test with NO_SERVER' + if: success() || failure() + env: + CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_SERVER=off" + NUM_PROC: ${{ steps.cpu-cores.outputs.count }} + run: | + rm -f build/CMakeCache.txt + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + make -j${{ steps.cpu-cores.outputs.count}} + ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}} + + - name: 'Test with CAPNPROTO disabled' + if: success() || failure() + env: + CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ENABLE_CAPNPROTO=off" + NUM_PROC: ${{ steps.cpu-cores.outputs.count }} + run: | + rm -f build/CMakeCache.txt + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + make -j${{ steps.cpu-cores.outputs.count}} + ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}} + + - name: 'Test with serial VPR_EXECUTION_ENGINE' + if: success() || failure() + env: + CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_EXECUTION_ENGINE=serial -DTATUM_EXECUTION_ENGINE=serial" + NUM_PROC: ${{ steps.cpu-cores.outputs.count }} + run: | + rm -f build/CMakeCache.txt + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + make -j${{ steps.cpu-cores.outputs.count}} + ./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}} Regression: @@ -169,36 +242,12 @@ jobs: suite: 'vtr_reg_basic', extra_pkgs: "" }, - { - name: 'Basic with highest assertion level', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=4 -DWITH_BLIFEXPLORER=on', - suite: 'vtr_reg_basic', - extra_pkgs: "" - }, { name: 'Basic_odin', params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on', suite: 'vtr_reg_basic_odin', extra_pkgs: "" }, - { - name: 'Basic with NO_GRAPHICS', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off', - suite: 'vtr_reg_basic', - extra_pkgs: "" - }, - { - name: 'Basic with NO_SERVER', - params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=on -DVPR_USE_SERVER=off', - suite: 'vtr_reg_basic', - extra_pkgs: "" - }, - { - name: 'Basic with CAPNPROTO disabled', - params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_CAPNPROTO=off', - suite: 'vtr_reg_basic', - extra_pkgs: "" - }, { name: 'Basic with VTR_ENABLE_DEBUG_LOGGING', params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on', @@ -510,8 +559,9 @@ jobs: needs: - Build - Format - - UniTests - - Warnings + - VerifyTestSuites + - UnitTests + - BuildVariations - Regression - Sanitized - Parmys diff --git a/.gitmodules b/.gitmodules index 8a35f2bff8c..90a89248c2a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -6,3 +6,7 @@ [submodule "libs/EXTERNAL/sockpp"] path = libs/EXTERNAL/sockpp url = https://github.com/w0lek/sockpp.git + +[submodule "libs/EXTERNAL/libezgl"] + path = libs/EXTERNAL/libezgl + url = https://github.com/verilog-to-routing/ezgl.git diff --git a/.readthedocs.yaml b/.readthedocs.yaml index 884a834f088..a0652f749e0 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -19,6 +19,10 @@ build: tools: python: "3.11" +submodules: + include: all + python: install: - requirements: doc/requirements.txt + - requirements: requirements.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index 99a3ffa33ef..34504cd898f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -26,7 +26,6 @@ set_property(CACHE VTR_IPO_BUILD PROPERTY STRINGS auto on off) set(VTR_ASSERT_LEVEL "2" CACHE STRING "VTR assertion checking level. 0: no assertions, 1: fast assertions, 2: regular assertions, 3: additional assertions with noticeable run-time overhead, 4: all assertions (including those with significant run-time cost)") set_property(CACHE VTR_ASSERT_LEVEL PROPERTY STRINGS 0 1 2 3 4) -option(VTR_ENABLE_STRICT_COMPILE "Specifies whether compiler warnings should be treated as errors (e.g. -Werror)" OFF) option(VTR_ENABLE_SANITIZE "Enable address/leak/undefined-behaviour sanitizers (i.e. run-time error checking)" OFF) option(VTR_ENABLE_PROFILING "Enable performance profiler (gprof)" OFF) option(VTR_ENABLE_COVERAGE "Enable code coverage tracking (gcov)" OFF) diff --git a/Makefile b/Makefile index 109288f0344..78b5257dc0f 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -#This is a simple wrapper which hides cmake (for convenience, and from non-expert end users). +# This is a simple wrapper which hides cmake (for convenience, and from non-expert end users). # # It supports the targets: # 'make' - builds everything (all libaries/executables) @@ -15,12 +15,14 @@ # # 'make BUILD_TYPE=debug VERBOSE=1' -#Default build type -# Possible values: -# release_pgo #Perform a 2-stage build with profile-guided compiler optimization -# release #Build with compiler optimization -# debug #Build with debug info and no compiler optimization -# strict #Build VPR with warnings treated as errors +# Build type +# Possible values (not case sensitive): +# release #Build with compiler optimization (Default) +# RelWithDebInfo #Build with debug info and compiler optimizations +# debug #Build with debug info and no compiler optimization +# Possible suffixes: +# _pgo #Perform a 2-stage build with profile-guided compiler optimization +# _strict #Build VPR with warnings treated as errors BUILD_TYPE ?= release #Debugging verbosity enable @@ -40,7 +42,7 @@ override CMAKE_PARAMS := -DCMAKE_BUILD_TYPE=$(CMAKE_BUILD_TYPE) -G 'Unix Makefil #Are we doing a strict (i.e. warnings as errors) build? ifneq (,$(findstring strict,$(BUILD_TYPE))) #Configure for strict build with VPR warning treated as errors -override CMAKE_PARAMS := -DVTR_ENABLE_STRICT_COMPILE=on ${CMAKE_PARAMS} +override CMAKE_PARAMS := -DCMAKE_COMPILE_WARNING_AS_ERROR=on ${CMAKE_PARAMS} endif #Strict build type #Enable verbosity diff --git a/README.developers.md b/README.developers.md index 4c05edfedca..d2d0d37af39 100644 --- a/README.developers.md +++ b/README.developers.md @@ -1131,11 +1131,17 @@ All tests passed (1 assertion in 1 test case) VTR has support for several additional tools/features to aid debugging. ## Basic -To build vpr with make in debug mode, simply add `BUILD_TYPE=debug` at the end of your make command. +To build a tool with make in debug mode, simply add `BUILD_TYPE=debug` at the end of your make command. For example, to build all tools in debug mode use: ```shell -$ make vpr BUILD_TYPE=debug +$ make BUILD_TYPE=debug ``` +You can also enable additional (verbose) output from some tools. To build vpr with both debug information and additional output, use: +```shell +$ make vpr BUILD_TYPE=debug VERBOSE=1 +``` + + ## Sanitizers VTR can be compiled using *sanitizers* which will detect invalid memory accesses, memory leaks and undefined behaviour (supported by both GCC and LLVM): ```shell diff --git a/dev/subtree_config.xml b/dev/subtree_config.xml index d2e97bcbd9e..07357619081 100644 --- a/dev/subtree_config.xml +++ b/dev/subtree_config.xml @@ -24,11 +24,6 @@ internal_path="libs/EXTERNAL/libtatum" external_url="https://github.com/verilog-to-routing/tatum.git" default_external_ref="master"/> - List[TestSuite]: + """ + Parses the given test_suite_info file. The test suite info file is expected + to be a JSON file which contains information on which test suites in the + regression tests to verify and if any of the tasks should be ignored. + + The JSON should have the following form: + {"test_suites": [ + { + "name": "", + "ignored_tasks": [ + "", + ... + ] + }, + { + ... + } + ]} + """ + with open(test_suite_info_file, "r") as file: + data = json.load(file) + + assert isinstance(data, dict), "Test suite info should be a dictionary" + assert "test_suites" in data, "A list of test suites must be provided" + + test_suites = [] + for test_suite in data["test_suites"]: + assert isinstance(test_suite, dict), "Test suite should be a dictionary" + assert "name" in test_suite, "All test suites must have names" + assert "ignored_tasks" in test_suite, "All test suite must have an ignored task list" + + test_suites.append( + TestSuite( + name=test_suite["name"], + ignored_tasks=test_suite["ignored_tasks"], + ) + ) + + return test_suites + + +def parse_task_list(task_list_file: str) -> Set[str]: + """ + Parses the given task_list file and returns a list of the tasks within + the task list. + """ + tasks = set() + with open(task_list_file, "r") as file: + for line in file: + # Strip the whitespace from the line. + line.strip() + # If this is a comment line, skip it. + if line[0] == "#": + continue + # Split the line. This is used in case there is a comment on the line. + split_line = line.split() + if split_line: + # If the line can be split (i.e. the line is not empty), add + # the first part of the line to the tasks list, stripping any + # trailing "/" characters. + tasks.add(split_line[0].rstrip("/")) + + return tasks + + +def get_expected_task_list(test_suite_dir: str, reg_tests_parent_dir: str) -> Set[str]: + """ + Get the expected task list by parsing the test suite directory and finding + all files that look like config files. + """ + # Get all config files in the test suite. These will indicated where all + # the tasks are in the suite. + base_path = Path(test_suite_dir) + assert base_path.is_dir() + config_files = list(base_path.rglob("config.txt")) + + # Get a list of all the expected tasks in the task list + expected_task_list = set() + for config_file in config_files: + config_dir = os.path.dirname(config_file) + task_dir = os.path.dirname(config_dir) + # All tasks in the task list are relative to the parent of the regression + # tests directory. + expected_task_list.add(os.path.relpath(task_dir, reg_tests_parent_dir)) + + return expected_task_list + + +def verify_test_suite(test_suite: TestSuite, regression_tests_dir: str): + """ + Verifies the given test suite by looking into the regression tests directory + for the suite and ensures that all expected tasks are present in the suite's + task list. + + Returns the number of failures found in the test suite. + """ + # Check that the test suite exists in the regression tests directory + test_suite_dir = os.path.join(regression_tests_dir, test_suite.name) + if not os.path.exists(test_suite_dir): + print("\tError: Test suite not found in regression tests directory") + return 1 + + # Get the expected tasks list from the test suite directory. + reg_tests_parent_dir = os.path.dirname(regression_tests_dir.rstrip("/")) + expected_task_list = get_expected_task_list(test_suite_dir, reg_tests_parent_dir) + + # Get the task list file from the test suite and parse it to get the actual + # task list. + task_list_file = os.path.join(test_suite_dir, "task_list.txt") + if not os.path.exists(task_list_file): + print("\tError: Test suite does not have a root-level task list") + return 1 + actual_task_list = parse_task_list(task_list_file) + + # Keep track of the number of failures + num_failures = 0 + + # Process the ignored tests + ignored_tasks = set() + for ignored_task in test_suite.ignored_tasks: + # Ignored tasks are relative to the test directory, get their full path. + ignored_task_path = os.path.join(test_suite_dir, ignored_task) + # Check that the task exists. + if not os.path.exists(ignored_task_path): + print(f"\tError: Ignored task '{ignored_task}' not found in test suite") + num_failures += 1 + continue + # If the task exists, add it to the ignored tasks list relative to the + # reg test's parent directory so it can be compared properly. + ignored_tasks.add(os.path.relpath(ignored_task_path, reg_tests_parent_dir)) + + if len(ignored_tasks) > 0: + print(f"\tWarning: {len(ignored_tasks)} tasks were ignored") + + # Check for any missing tasks in the task list + for task in expected_task_list: + # If this task is ignored, it is expected to be missing. + if task in ignored_tasks: + continue + # If the task is not in the actual task list, this is an error. + if task not in actual_task_list: + print(f"\tError: Failed to find task '{task}' in task list!") + num_failures += 1 + + # Check for any tasks in the task list which should not be there + for task in actual_task_list: + # If a task is in the task list, but is not in the test directory, this + # is a failure. + if task not in expected_task_list: + print(f"\tError: Task '{task}' found in task list but not in test directory") + num_failures += 1 + # If a task is in the task list, but is marked as ignored, this must be + # a mistake. + if task in ignored_tasks: + print(f"\tError: Task '{task}' found in task list but was marked as ignored") + + return num_failures + + +def verify_test_suites(): + """ + Verify the VTR test suites. + + Test suites are verified by checking the tasks within their test directory + and the tasks within the task list at the root of that directory and ensuring + that they match. If there are any tasks which appear in one but not the other, + an error is produced and this script will return an error code. + """ + # Set up the argument parser object. + parser = argparse.ArgumentParser(description="Verifies the test suites used in VTR.") + parser.add_argument( + "-vtr_regression_tests_dir", + type=str, + required=True, + help="The path to the vtr_flow/tasks/regression_tests directory in VTR.", + ) + parser.add_argument( + "-test_suite_info", + type=str, + required=True, + help="Information on the test suite (must be a JSON file).", + ) + + # Parse the arguments from the command line. + args = parser.parse_args() + + # Verify each of the test suites. + num_failures = 0 + test_suites = parse_test_suite_info(args.test_suite_info) + for test_suite in test_suites: + print(f"Verifying test suite: {test_suite.name}") + test_suite_failures = verify_test_suite(test_suite, args.vtr_regression_tests_dir) + print(f"\tTest suite had {test_suite_failures} failures\n") + num_failures += test_suite_failures + + # If any failures were found in any suite, return exit code 1. + if num_failures != 0: + print(f"Failure: Test suite verifcation failed with {num_failures} failures") + print(f"Please fix the failing test suites found in {args.vtr_regression_tests_dir}") + print(f"If necessary, update the test suites info found here: {args.test_suite_info}") + sys.exit(1) + + print(f"Success: All test suites in {args.test_suite_info} passed") + + +if __name__ == "__main__": + verify_test_suites() diff --git a/doc/_doxygen/ezgl.dox b/doc/_doxygen/ezgl.dox new file mode 100644 index 00000000000..b0d39c4bce9 --- /dev/null +++ b/doc/_doxygen/ezgl.dox @@ -0,0 +1,13 @@ +PROJECT_NAME = "Verilog to Routing - EZGL" +OUTPUT_DIRECTORY = ../_build/doxygen/ezgl +FULL_PATH_NAMES = NO +OPTIMIZE_OUTPUT_FOR_C = YES +EXTRACT_ALL = YES +EXTRACT_PRIVATE = YES +EXTRACT_STATIC = YES +WARN_IF_UNDOCUMENTED = NO +INPUT = ../../libs/EXTERNAL/libezgl +RECURSIVE = YES +GENERATE_HTML = NO +GENERATE_LATEX = NO +GENERATE_XML = YES diff --git a/doc/src/api/ezgl/application.rst b/doc/src/api/ezgl/application.rst new file mode 100644 index 00000000000..cd1ef7a223a --- /dev/null +++ b/doc/src/api/ezgl/application.rst @@ -0,0 +1,6 @@ +=========== +Application +=========== + +.. doxygenfile:: application.hpp + :project: ezgl diff --git a/doc/src/api/ezgl/callback.rst b/doc/src/api/ezgl/callback.rst new file mode 100644 index 00000000000..73b9b53692d --- /dev/null +++ b/doc/src/api/ezgl/callback.rst @@ -0,0 +1,56 @@ +========= +Callbacks +========= + +This module provides callback functions for handling keyboard and mouse input, as well as predefined button actions in EZGL applications. + +Input Event Callbacks +-------------------- + +.. doxygenfunction:: press_key + :project: ezgl + +.. doxygenfunction:: press_mouse + :project: ezgl + +.. doxygenfunction:: release_mouse + :project: ezgl + +.. doxygenfunction:: move_mouse + :project: ezgl + +.. doxygenfunction:: scroll_mouse + :project: ezgl + +Button Action Callbacks +---------------------- + +.. doxygenfunction:: press_zoom_fit + :project: ezgl + +.. doxygenfunction:: press_zoom_in + :project: ezgl + +.. doxygenfunction:: press_zoom_out + :project: ezgl + +Navigation Callbacks +------------------ + +.. doxygenfunction:: press_up + :project: ezgl + +.. doxygenfunction:: press_down + :project: ezgl + +.. doxygenfunction:: press_left + :project: ezgl + +.. doxygenfunction:: press_right + :project: ezgl + +Other Callbacks +------------- + +.. doxygenfunction:: press_proceed + :project: ezgl \ No newline at end of file diff --git a/doc/src/api/ezgl/camera.rst b/doc/src/api/ezgl/camera.rst new file mode 100644 index 00000000000..9a7b7b9108f --- /dev/null +++ b/doc/src/api/ezgl/camera.rst @@ -0,0 +1,5 @@ +====== +Camera +====== +.. doxygenfile:: camera.hpp + :project: ezgl diff --git a/doc/src/api/ezgl/canvas.rst b/doc/src/api/ezgl/canvas.rst new file mode 100644 index 00000000000..a19065e7497 --- /dev/null +++ b/doc/src/api/ezgl/canvas.rst @@ -0,0 +1,5 @@ +====== +Canvas +====== +.. doxygenfile:: canvas.hpp + :project: ezgl diff --git a/doc/src/api/ezgl/color.rst b/doc/src/api/ezgl/color.rst new file mode 100644 index 00000000000..ebb245e8639 --- /dev/null +++ b/doc/src/api/ezgl/color.rst @@ -0,0 +1,5 @@ +===== +Color +===== +.. doxygenfile:: color.hpp + :project: ezgl diff --git a/doc/src/api/ezgl/control.rst b/doc/src/api/ezgl/control.rst new file mode 100644 index 00000000000..5c8d6cce10e --- /dev/null +++ b/doc/src/api/ezgl/control.rst @@ -0,0 +1,41 @@ +======= +Control +======= + +Functions to manipulate what is visible on the EZGL canvas. These functions are used by EZGL's predefined buttons, but application code can also call them directly when needed. + +Zoom Functions +------------- + +.. doxygenfunction:: ezgl::zoom_in(canvas*, double) + :project: ezgl + +.. doxygenfunction:: ezgl::zoom_out(canvas*, double) + :project: ezgl + +.. doxygenfunction:: ezgl::zoom_in(canvas*, point2d, double) + :project: ezgl + +.. doxygenfunction:: ezgl::zoom_out(canvas*, point2d, double) + :project: ezgl + +.. doxygenfunction:: ezgl::zoom_fit + :project: ezgl + +Translation Functions +-------------------- + +.. doxygenfunction:: ezgl::translate + :project: ezgl + +.. doxygenfunction:: ezgl::translate_up + :project: ezgl + +.. doxygenfunction:: ezgl::translate_down + :project: ezgl + +.. doxygenfunction:: ezgl::translate_left + :project: ezgl + +.. doxygenfunction:: ezgl::translate_right + :project: ezgl \ No newline at end of file diff --git a/doc/src/api/ezgl/graphics.rst b/doc/src/api/ezgl/graphics.rst new file mode 100644 index 00000000000..d6425154c40 --- /dev/null +++ b/doc/src/api/ezgl/graphics.rst @@ -0,0 +1,5 @@ +======== +Graphics +======== +.. doxygenfile:: graphics.hpp + :project: ezgl diff --git a/doc/src/api/ezgl/index.rst b/doc/src/api/ezgl/index.rst new file mode 100644 index 00000000000..0429b42af1d --- /dev/null +++ b/doc/src/api/ezgl/index.rst @@ -0,0 +1,20 @@ +.. _ezgl: + +==== +EZGL +==== + +EZGL is a graphics layer on top of version 3.x of the GTK graphics library. It allows drawing in an arbitrary 2D world coordinate space (instead of in pixel coordinates), handles panning and zooming automatically, and provides easy-to-use functions for common tasks like setting up a window, setting graphics attributes (like colour and line style) and drawing primitives (like lines and polygons). Most of VPR's drawing is performed in ezgl, and GTK functionality not exposed by ezgl can still be accessed by directly calling the relevant gtk functions. + +.. toctree:: + :maxdepth: 1 + + application + callback + camera + canvas + color + control + graphics + point + rectangle \ No newline at end of file diff --git a/doc/src/api/ezgl/point.rst b/doc/src/api/ezgl/point.rst new file mode 100644 index 00000000000..d335dc3873b --- /dev/null +++ b/doc/src/api/ezgl/point.rst @@ -0,0 +1,6 @@ +===== +Point +===== +.. doxygenfile:: point.hpp + :project: ezgl + diff --git a/doc/src/api/ezgl/rectangle.rst b/doc/src/api/ezgl/rectangle.rst new file mode 100644 index 00000000000..0a62cdb542e --- /dev/null +++ b/doc/src/api/ezgl/rectangle.rst @@ -0,0 +1,5 @@ +========= +Rectangle +========= +.. doxygenfile:: rectangle.hpp + :project: ezgl diff --git a/doc/src/conf.py b/doc/src/conf.py index fe2fc79f5b1..7e3a421f7f7 100644 --- a/doc/src/conf.py +++ b/doc/src/conf.py @@ -155,6 +155,7 @@ "odin_ii": "../_build/doxygen/odin_ii/xml", "blifexplorer": "../_build/doxygen/blifexplorer/xml", "librrgraph": "../_build/doxygen/librrgraph/xml", + "ezgl": "../_build/doxygen/ezgl/xml", } breathe_default_project = "vpr" diff --git a/doc/src/index.rst b/doc/src/index.rst index a7881f79a8d..378e46af087 100644 --- a/doc/src/index.rst +++ b/doc/src/index.rst @@ -62,6 +62,7 @@ For more specific documentation about VPR see :ref:`vpr`. api/vpr/index api/vtrutil/index + api/ezgl/index api/vprinternals/index Indices and tables diff --git a/doc/src/tutorials/timing_analysis/index.rst b/doc/src/tutorials/timing_analysis/index.rst index 6f93faa4c0e..20c6e2aef67 100644 --- a/doc/src/tutorials/timing_analysis/index.rst +++ b/doc/src/tutorials/timing_analysis/index.rst @@ -6,6 +6,8 @@ Post-Implementation Timing Analysis This tutorial describes how to perform static timing analysis (STA) on a circuit which has been implemented by :ref:`VPR` using OpenSTA, an external timing analysis tool. +A video of this tutorial can be found here: https://youtu.be/yihFJc7WOfE + External timing analysis can be useful since VPR's timing analyzer (Tatum) does not support all timing constraints and does not provide a TCL interface to allow you to directly interrogate the timing graph. VPR also has limited support for diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index c420ef40f80..916a7986cd2 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -416,9 +416,14 @@ Use the options below to override this default naming behaviour. .. option:: --write_placement_delay_lookup Writes the placement delay lookup to the specified file. Expects a file extension of either ``.capnp`` or ``.bin``. + +.. option:: --read_initial_place_file + + Reads in the initial cluster-level placement (in :ref:`.place file format `) from the specified file and uses it as the starting point for annealing improvement, instead of generating an initial placement internally. + .. option:: --write_initial_place_file - Writes out the the placement chosen by the initial placement algorithm to the specified file. + Writes out the clustered netlist placement chosen by the initial placement algorithm to the specified file, in :ref:`.place file format `. .. option:: --outfile_prefix @@ -838,9 +843,9 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe Controls how the placer handles blocks (of any type) during placement. - * ````: A path to a file listing the desired location of blocks in the netlist. + * ````: A path to a file listing the desired location of clustered blocks in the netlist. - This place location file is in the same format as a :ref:`normal placement file `, but does not require the first two lines which are normally at the top of a placement file that specify the netlist file, netlist ID, and array size. + This place location file is in the same format as a :ref:`.place file `, but does not require the first two lines which are normally at the top of a placement file that specify the netlist file, netlist ID, and array size. **Default:** ````. @@ -1336,6 +1341,15 @@ Analytical Placement is generally split into three stages: **Default:** ``1`` +.. option:: --ap_generate_mass_report {on | off} + + Controls whether to generate a report on how the partial legalizer + within the AP flow calculates the mass of primitives and the + capacity of tiles on the device. This report is useful when + debugging the partial legalizer. + + **Default:** ``off`` + .. _router_options: @@ -2222,6 +2236,16 @@ The following options are used to enable server mode in VPR. .. seealso:: :ref:`interactive_path_analysis_client` + +Show Architecture Resources +^^^^^^^^^^^^^^^^^^^^^^^^ +.. option:: --show_arch_resources + + Print the architecture resource report for each device layout and exit normally. + + **Default:** ``off`` + + Command-line Auto Completion ---------------------------- diff --git a/libs/EXTERNAL/libcatch2 b/libs/EXTERNAL/libcatch2 index 76f70b1403d..74fcff6e5b1 160000 --- a/libs/EXTERNAL/libcatch2 +++ b/libs/EXTERNAL/libcatch2 @@ -1 +1 @@ -Subproject commit 76f70b1403dbc0781216f49e20e45b71f7eccdd8 +Subproject commit 74fcff6e5b190fb833a231b7f7c1829e3c3ac54d diff --git a/libs/EXTERNAL/libezgl b/libs/EXTERNAL/libezgl new file mode 160000 index 00000000000..b6beef98a3e --- /dev/null +++ b/libs/EXTERNAL/libezgl @@ -0,0 +1 @@ +Subproject commit b6beef98a3e51907c66fa6c7cc74933fb91faa6c diff --git a/libs/EXTERNAL/libezgl/.clang-format b/libs/EXTERNAL/libezgl/.clang-format deleted file mode 100644 index 86a33c1358e..00000000000 --- a/libs/EXTERNAL/libezgl/.clang-format +++ /dev/null @@ -1,38 +0,0 @@ ---- -AccessModifierOffset: '-2' -AlignAfterOpenBracket: DontAlign -AlignConsecutiveAssignments: 'false' -AlignConsecutiveDeclarations: 'false' -AlignEscapedNewlinesLeft: 'true' -AlignOperands: 'true' -AlignTrailingComments: 'true' -AllowAllParametersOfDeclarationOnNextLine: 'false' -AllowShortBlocksOnASingleLine: 'false' -AllowShortFunctionsOnASingleLine: None -AllowShortIfStatementsOnASingleLine: 'false' -AllowShortLoopsOnASingleLine: 'false' -AlwaysBreakAfterReturnType: None -AlwaysBreakTemplateDeclarations: 'true' -BinPackArguments: 'true' -BinPackParameters: 'false' -BreakBeforeBraces: WebKit -BreakConstructorInitializersBeforeComma: 'true' -ColumnLimit: '100' -ConstructorInitializerAllOnOneLineOrOnePerLine: 'true' -Cpp11BracedListStyle: 'true' -ExperimentalAutoDetectBinPacking: 'false' -IndentWidth: '2' -Language: Cpp -NamespaceIndentation: None -ReflowComments: 'false' -SortIncludes: 'false' -SpaceBeforeParens: Never -SpaceInEmptyParentheses: 'false' -SpacesBeforeTrailingComments: '1' -SpacesInAngles: 'false' -SpacesInSquareBrackets: 'false' -Standard: Cpp11 -TabWidth: '2' -UseTab: Never - -... diff --git a/libs/EXTERNAL/libezgl/.gitignore b/libs/EXTERNAL/libezgl/.gitignore deleted file mode 100644 index f3c566480eb..00000000000 --- a/libs/EXTERNAL/libezgl/.gitignore +++ /dev/null @@ -1,41 +0,0 @@ -# Prerequisites -*.d - -# Compiled Object files -*.slo -*.lo -*.o -*.obj - -# Precompiled Headers -*.gch -*.pch - -# Compiled Dynamic libraries -*.so -*.dylib -*.dll - -# Fortran module files -*.mod -*.smod - -# Compiled Static libraries -*.lai -*.la -*.a -*.lib - -# Executables -*.exe -*.out -*.app - -# Build Directories -cmake-build* - -# Vim -.swp - -# IDE Files and Folders -.idea diff --git a/libs/EXTERNAL/libezgl/CMakeLists.txt b/libs/EXTERNAL/libezgl/CMakeLists.txt deleted file mode 100644 index d63d2cca64c..00000000000 --- a/libs/EXTERNAL/libezgl/CMakeLists.txt +++ /dev/null @@ -1,82 +0,0 @@ -cmake_minimum_required(VERSION 3.10 FATAL_ERROR) - -# create the project -project( - ezgl - VERSION 1.0.1 - LANGUAGES CXX -) - -# we rely on GTK3 for the GUI, so make sure the system has it -find_package(PkgConfig REQUIRED) -pkg_check_modules(GTK3 QUIET gtk+-3.0) -pkg_check_modules(X11 QUIET x11) - -if(NOT GTK3_FOUND) - message(WARNING "EZGL: Failed to find required GTK3 library (on debian/ubuntu try 'sudo apt-get install libgtk-3-dev' to install)") -endif() - -# we also rely on glib to compile the GTK resource files -# a set of macros has been developed by Makman2 on GitHub to help with this -list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/gcr-cmake/macros) - -#Is ezgl the root cmake project? -set(IS_ROOT_PROJECT TRUE) -if (${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_CURRENT_SOURCE_DIR}) - set(IS_ROOT_PROJECT FALSE) -endif() - -# include the configuration/compile time options for this library -include(options.cmake) - -# create a library that can be linked by executables -add_library( - ${PROJECT_NAME} - include/ezgl/application.hpp - include/ezgl/camera.hpp - include/ezgl/canvas.hpp - include/ezgl/color.hpp - include/ezgl/control.hpp - include/ezgl/callback.hpp - include/ezgl/graphics.hpp - include/ezgl/point.hpp - include/ezgl/rectangle.hpp - src/application.cpp - src/camera.cpp - src/canvas.cpp - src/control.cpp - src/callback.cpp - src/graphics.cpp -) - -target_include_directories( - ${PROJECT_NAME} - PUBLIC include -) - -#Treat GTK/X11 headers as system headers so they -#do not generate compilation warnings -target_include_directories( - ${PROJECT_NAME} - SYSTEM - PUBLIC ${GTK3_INCLUDE_DIRS} - PUBLIC ${X11_INCLUDE_DIRS} -) - -target_link_libraries( - ${PROJECT_NAME} - PUBLIC ${GTK3_LIBRARIES} - PUBLIC ${X11_LIBRARIES} -) - -# add_compile_options does not seem to be working on the UG machines, -# and we cannot set target properties in version 3.0.2 -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++14") - -if(EZGL_BUILD_EXAMPLES) - add_subdirectory(examples) -endif() - -if(EZGL_BUILD_DOCS) - add_subdirectory(doc) -endif() diff --git a/libs/EXTERNAL/libezgl/LICENSE b/libs/EXTERNAL/libezgl/LICENSE deleted file mode 100644 index 8dada3edaf5..00000000000 --- a/libs/EXTERNAL/libezgl/LICENSE +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright {yyyy} {name of copyright owner} - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. diff --git a/libs/EXTERNAL/libezgl/README.adoc b/libs/EXTERNAL/libezgl/README.adoc deleted file mode 100644 index 836033efe83..00000000000 --- a/libs/EXTERNAL/libezgl/README.adoc +++ /dev/null @@ -1,38 +0,0 @@ -= EZGL - An Easy Graphics Library - -image:https://codedocs.xyz/mariobadr/ezgl.svg[link="https://codedocs.xyz/mariobadr/ezgl"] - -EZGL is a library for use in ece297 as a simple way to create a GUI application. -The library provides a thin wrapper around GTK and drawing functionality. - -== Dependencies - -The library currently depends on GTK 3 and cairo. - -== Compilation - -This project uses CMake for compiling and works with CMake version 3.0.2 (the version available on the UG machines). -CMake can configure the project for different build systems and IDEs (type `cmake --help` for a list of generators available for your platform). -We recommend you create a build directory before invoking CMake to configure the project (`cmake -B`). -For example, we can perform the configuration step from the project root directory: - - cmake -H. -Bcmake-build-release -DCMAKE_BUILD_TYPE=Release - cmake -H. -Bcmake-build-debug -DCMAKE_BUILD_TYPE=Debug - -After the configuration step, you can ask CMake to build the project. - - cmake --build cmake-build-release/ --target all - cmake --build cmake-build-debug/ --target all - -=== Build Options - -Build options can be found in `options.cmake`. -Simply specify the build option during the configuration step in CMake. -Using the already generated `cmake-build-release` directory from the previous section, we can: - - cmake -H. -Bcmake-build-release -DEZGL_BUILD_EXAMPLES=ON - -Your IDE or Makefile should now include additional targets when you turn these options on. -For example, enabling `EZGL_BUILD_EXAMPLES` should provide access to the `basic-application` target, which you can build: - - cmake --build cmake-build-release/ --target basic-application diff --git a/libs/EXTERNAL/libezgl/doc/CMakeLists.txt b/libs/EXTERNAL/libezgl/doc/CMakeLists.txt deleted file mode 100644 index d56545e6c90..00000000000 --- a/libs/EXTERNAL/libezgl/doc/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -find_package(Doxygen) - -if(NOT DOXYGEN_FOUND) - message(FATAL_ERROR "Doxygen is needed to build the documentation.") -endif() - -set(DOXYFILE_IN Doxyfile.in) -set(DOXYFILE ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile) - -configure_file(${DOXYFILE_IN} ${DOXYFILE} @ONLY) - -# add a target to generate API documentation with Doxygen -add_custom_target( - doc - COMMAND ${DOXYGEN_EXECUTABLE} ${DOXYFILE} - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Generating API documentation with Doxygen" - VERBATIM -) diff --git a/libs/EXTERNAL/libezgl/doc/Doxyfile.in b/libs/EXTERNAL/libezgl/doc/Doxyfile.in deleted file mode 100644 index 8365d2ba95a..00000000000 --- a/libs/EXTERNAL/libezgl/doc/Doxyfile.in +++ /dev/null @@ -1,2291 +0,0 @@ -# Doxyfile 1.8.6 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project. -# -# All text after a double hash (##) is considered a comment and is placed in -# front of the TAG it is preceding. -# -# All text after a single hash (#) is considered a comment and will be ignored. -# The format is: -# TAG = value [value, ...] -# For lists, items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (\" \"). - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all text -# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv -# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv -# for the list of possible encodings. -# The default value is: UTF-8. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by -# double-quotes, unless you are using Doxywizard) that should identify the -# project for which the documentation is generated. This name is used in the -# title of most generated pages and in a few other places. -# The default value is: My Project. - -PROJECT_NAME = "@PROJECT_NAME@" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. This -# could be handy for archiving the generated documentation or if some version -# control system is used. - -PROJECT_NUMBER = "@ezgl_VERSION@" - -# Using the PROJECT_BRIEF tag one can provide an optional one line description -# for a project that appears at the top of each page and should give viewer a -# quick idea about the purpose of the project. Keep the description short. - -PROJECT_BRIEF = "An Easy Graphics & GUI Library" - -# With the PROJECT_LOGO tag one can specify an logo or icon that is included in -# the documentation. The maximum height of the logo should not exceed 55 pixels -# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo -# to the output directory. - -PROJECT_LOGO = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path -# into which the generated documentation will be written. If a relative path is -# entered, it will be relative to the location where doxygen was started. If -# left blank the current directory will be used. - -OUTPUT_DIRECTORY = - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub- -# directories (in 2 levels) under the output directory of each output format and -# will distribute the generated files over these directories. Enabling this -# option can be useful when feeding doxygen a huge amount of source files, where -# putting all generated files in the same directory would otherwise causes -# performance problems for the file system. -# The default value is: NO. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese, -# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States), -# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian, -# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages), -# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian, -# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian, -# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish, -# Ukrainian and Vietnamese. -# The default value is: English. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member -# descriptions after the members that are listed in the file and class -# documentation (similar to Javadoc). Set to NO to disable this. -# The default value is: YES. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief -# description of a member or function before the detailed description -# -# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. -# The default value is: YES. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator that is -# used to form the text in various listings. Each string in this list, if found -# as the leading text of the brief description, will be stripped from the text -# and the result, after processing the whole list, is used as the annotated -# text. Otherwise, the brief description is used as-is. If left blank, the -# following values are used ($name is automatically replaced with the name of -# the entity):The $name class, The $name widget, The $name file, is, provides, -# specifies, contains, represents, a, an and the. - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# doxygen will generate a detailed section even if there is only a brief -# description. -# The default value is: NO. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. -# The default value is: NO. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path -# before files name in the file list and in the header files. If set to NO the -# shortest path that makes the file name unique will be used -# The default value is: YES. - -FULL_PATH_NAMES = YES - -# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path. -# Stripping is only done if one of the specified strings matches the left-hand -# part of the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the path to -# strip. -# -# Note that you can specify absolute paths here, but also relative paths, which -# will be relative from the directory where doxygen is started. -# This tag requires that the tag FULL_PATH_NAMES is set to YES. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the -# path mentioned in the documentation of a class, which tells the reader which -# header file to include in order to use a class. If left blank only the name of -# the header file containing the class definition is used. Otherwise one should -# specify the list of include paths that are normally passed to the compiler -# using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but -# less readable) file names. This can be useful is your file systems doesn't -# support long names like on DOS, Mac, or CD-ROM. -# The default value is: NO. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the -# first line (until the first dot) of a Javadoc-style comment as the brief -# description. If set to NO, the Javadoc-style will behave just like regular Qt- -# style comments (thus requiring an explicit @brief command for a brief -# description.) -# The default value is: NO. - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first -# line (until the first dot) of a Qt-style comment as the brief description. If -# set to NO, the Qt-style will behave just like regular Qt-style comments (thus -# requiring an explicit \brief command for a brief description.) -# The default value is: NO. - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a -# multi-line C++ special comment block (i.e. a block of //! or /// comments) as -# a brief description. This used to be the default behavior. The new default is -# to treat a multi-line C++ comment block as a detailed description. Set this -# tag to YES if you prefer the old behavior instead. -# -# Note that setting this tag to YES also means that rational rose comments are -# not recognized any more. -# The default value is: NO. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the -# documentation from any documented member that it re-implements. -# The default value is: YES. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a -# new page for each member. If set to NO, the documentation of a member will be -# part of the file/class/namespace that contains it. -# The default value is: NO. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen -# uses this value to replace tabs by spaces in code fragments. -# Minimum value: 1, maximum value: 16, default value: 4. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that act as commands in -# the documentation. An alias has the form: -# name=value -# For example adding -# "sideeffect=@par Side Effects:\n" -# will allow you to put the command \sideeffect (or @sideeffect) in the -# documentation, which will result in a user-defined paragraph with heading -# "Side Effects:". You can put \n's in the value part of an alias to insert -# newlines. - -ALIASES = - -# This tag can be used to specify a number of word-keyword mappings (TCL only). -# A mapping has the form "name=value". For example adding "class=itcl::class" -# will allow you to use the command class in the itcl::class meaning. - -TCL_SUBST = - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources -# only. Doxygen will then generate output that is more tailored for C. For -# instance, some of the names that are used will be different. The list of all -# members will be omitted, etc. -# The default value is: NO. - -OPTIMIZE_OUTPUT_FOR_C = NO - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or -# Python sources only. Doxygen will then generate output that is more tailored -# for that language. For instance, namespaces will be presented as packages, -# qualified scopes will look different, etc. -# The default value is: NO. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources. Doxygen will then generate output that is tailored for Fortran. -# The default value is: NO. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for VHDL. -# The default value is: NO. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given -# extension. Doxygen has a built-in mapping, but you can override or extend it -# using this tag. The format is ext=language, where ext is a file extension, and -# language is one of the parsers supported by doxygen: IDL, Java, Javascript, -# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. -# -# Note For files without extension you can use no_extension as a placeholder. -# -# Note that for custom extensions you also need to set FILE_PATTERNS otherwise -# the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments -# according to the Markdown format, which allows for more readable -# documentation. See http://daringfireball.net/projects/markdown/ for details. -# The output of markdown processing is further processed by doxygen, so you can -# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in -# case of backward compatibilities issues. -# The default value is: YES. - -MARKDOWN_SUPPORT = YES - -# When enabled doxygen tries to link words that correspond to documented -# classes, or namespaces to their corresponding documentation. Such a link can -# be prevented in individual cases by by putting a % sign in front of the word -# or globally by setting AUTOLINK_SUPPORT to NO. -# The default value is: YES. - -AUTOLINK_SUPPORT = YES - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should set this -# tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); -# versus func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. -# The default value is: NO. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. -# The default value is: NO. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip (see: -# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen -# will parse them like normal C++ but will assume all classes use public instead -# of private inheritance when no explicit protection keyword is present. -# The default value is: NO. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate -# getter and setter methods for a property. Setting this option to YES will make -# doxygen to replace the get and set methods by a property in the documentation. -# This will only work if the methods are indeed getting or setting a simple -# type. If this is not the case, or you want to show the methods anyway, you -# should set this option to NO. -# The default value is: YES. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. -# The default value is: NO. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES to allow class member groups of the same type -# (for instance a group of public functions) to be put as a subgroup of that -# type (e.g. under the Public Functions section). Set it to NO to prevent -# subgrouping. Alternatively, this can be done per class using the -# \nosubgrouping command. -# The default value is: YES. - -SUBGROUPING = YES - -# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions -# are shown inside the group in which they are included (e.g. using \ingroup) -# instead of on a separate page (for HTML and Man pages) or section (for LaTeX -# and RTF). -# -# Note that this feature does not work in combination with -# SEPARATE_MEMBER_PAGES. -# The default value is: NO. - -INLINE_GROUPED_CLASSES = NO - -# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions -# with only public data fields or simple typedef fields will be shown inline in -# the documentation of the scope in which they are defined (i.e. file, -# namespace, or group documentation), provided this scope is documented. If set -# to NO, structs, classes, and unions are shown on a separate page (for HTML and -# Man pages) or section (for LaTeX and RTF). -# The default value is: NO. - -INLINE_SIMPLE_STRUCTS = NO - -# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or -# enum is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically be -# useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. -# The default value is: NO. - -TYPEDEF_HIDES_STRUCT = NO - -# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This -# cache is used to resolve symbols given their name and scope. Since this can be -# an expensive process and often the same symbol appears multiple times in the -# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small -# doxygen will become slower. If the cache is too large, memory is wasted. The -# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range -# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 -# symbols. At the end of a run doxygen will report the cache usage and suggest -# the optimal cache size from a speed point of view. -# Minimum value: 0, maximum value: 9, default value: 0. - -LOOKUP_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. Private -# class members and static file members will be hidden unless the -# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. -# Note: This will also disable the warnings about undocumented members that are -# normally produced when WARNINGS is set to YES. -# The default value is: NO. - -EXTRACT_ALL = NO - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will -# be included in the documentation. -# The default value is: NO. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal -# scope will be included in the documentation. -# The default value is: NO. - -EXTRACT_PACKAGE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file will be -# included in the documentation. -# The default value is: NO. - -EXTRACT_STATIC = NO - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined -# locally in source files will be included in the documentation. If set to NO -# only classes defined in header files are included. Does not have any effect -# for Java sources. -# The default value is: YES. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local methods, -# which are defined in the implementation section but not in the interface are -# included in the documentation. If set to NO only methods in the interface are -# included. -# The default value is: NO. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base name of -# the file that contains the anonymous namespace. By default anonymous namespace -# are hidden. -# The default value is: NO. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all -# undocumented members inside documented classes or files. If set to NO these -# members will be included in the various overviews, but no documentation -# section is generated. This option has no effect if EXTRACT_ALL is enabled. -# The default value is: NO. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. If set -# to NO these classes will be included in the various overviews. This option has -# no effect if EXTRACT_ALL is enabled. -# The default value is: NO. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend -# (class|struct|union) declarations. If set to NO these declarations will be -# included in the documentation. -# The default value is: NO. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any -# documentation blocks found inside the body of a function. If set to NO these -# blocks will be appended to the function's detailed documentation block. -# The default value is: NO. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation that is typed after a -# \internal command is included. If the tag is set to NO then the documentation -# will be excluded. Set it to YES to include the internal documentation. -# The default value is: NO. - -INTERNAL_DOCS = NO - -# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file -# names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. -# The default value is: system dependent. - -CASE_SENSE_NAMES = YES - -# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with -# their full class and namespace scopes in the documentation. If set to YES the -# scope will be hidden. -# The default value is: NO. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of -# the files that are included by a file in the documentation of that file. -# The default value is: YES. - -SHOW_INCLUDE_FILES = YES - -# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each -# grouped member an include statement to the documentation, telling the reader -# which file to include in order to use the member. -# The default value is: NO. - -SHOW_GROUPED_MEMB_INC = NO - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include -# files with double quotes in the documentation rather than with sharp brackets. -# The default value is: NO. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the -# documentation for inline members. -# The default value is: YES. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the -# (detailed) documentation of file and class members alphabetically by member -# name. If set to NO the members will appear in declaration order. -# The default value is: YES. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief -# descriptions of file, namespace and class members alphabetically by member -# name. If set to NO the members will appear in declaration order. Note that -# this will also influence the order of the classes in the class list. -# The default value is: NO. - -SORT_BRIEF_DOCS = NO - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the -# (brief and detailed) documentation of class members so that constructors and -# destructors are listed first. If set to NO the constructors will appear in the -# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. -# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief -# member documentation. -# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting -# detailed member documentation. -# The default value is: NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy -# of group names into alphabetical order. If set to NO the group names will -# appear in their defined order. -# The default value is: NO. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by -# fully-qualified names, including namespaces. If set to NO, the class list will -# be sorted only by class name, not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the alphabetical -# list. -# The default value is: NO. - -SORT_BY_SCOPE_NAME = NO - -# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper -# type resolution of all parameters of a function it will reject a match between -# the prototype and the implementation of a member function even if there is -# only one candidate or it is obvious which candidate to choose by doing a -# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still -# accept a match between prototype and implementation in such cases. -# The default value is: NO. - -STRICT_PROTO_MATCHING = NO - -# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the -# todo list. This list is created by putting \todo commands in the -# documentation. -# The default value is: YES. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the -# test list. This list is created by putting \test commands in the -# documentation. -# The default value is: YES. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug -# list. This list is created by putting \bug commands in the documentation. -# The default value is: YES. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO) -# the deprecated list. This list is created by putting \deprecated commands in -# the documentation. -# The default value is: YES. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional documentation -# sections, marked by \if ... \endif and \cond -# ... \endcond blocks. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the -# initial value of a variable or macro / define can have for it to appear in the -# documentation. If the initializer consists of more lines than specified here -# it will be hidden. Use a value of 0 to hide initializers completely. The -# appearance of the value of individual variables and macros / defines can be -# controlled using \showinitializer or \hideinitializer command in the -# documentation regardless of this setting. -# Minimum value: 0, maximum value: 10000, default value: 30. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at -# the bottom of the documentation of classes and structs. If set to YES the list -# will mention the files that were used to generate the documentation. -# The default value is: YES. - -SHOW_USED_FILES = YES - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This -# will remove the Files entry from the Quick Index and from the Folder Tree View -# (if specified). -# The default value is: YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces -# page. This will remove the Namespaces entry from the Quick Index and from the -# Folder Tree View (if specified). -# The default value is: YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command command input-file, where command is the value of the -# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided -# by doxygen. Whatever the program writes to standard output is used as the file -# version. For an example see the documentation. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. To create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. You can -# optionally specify a file name after the option, if omitted DoxygenLayout.xml -# will be used as the name of the layout file. -# -# Note that if you run doxygen from a directory containing a file called -# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE -# tag is left empty. - -LAYOUT_FILE = - -# The CITE_BIB_FILES tag can be used to specify one or more bib files containing -# the reference definitions. This must be a list of .bib files. The .bib -# extension is automatically appended if omitted. This requires the bibtex tool -# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. -# For LaTeX the style of the bibliography can be controlled using -# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the -# search path. Do not use file names with spaces, bibtex cannot handle them. See -# also \cite for info how to create references. - -CITE_BIB_FILES = - -#--------------------------------------------------------------------------- -# Configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated to -# standard output by doxygen. If QUIET is set to YES this implies that the -# messages are off. -# The default value is: NO. - -QUIET = NO - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES -# this implies that the warnings are on. -# -# Tip: Turn warnings on while writing the documentation. -# The default value is: YES. - -WARNINGS = YES - -# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate -# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag -# will automatically be disabled. -# The default value is: YES. - -WARN_IF_UNDOCUMENTED = YES - -# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some parameters -# in a documented function, or documenting parameters that don't exist or using -# markup commands wrongly. -# The default value is: YES. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that -# are documented, but have no documentation for their parameters or return -# value. If set to NO doxygen will only warn about wrong or incomplete parameter -# documentation, but not about the absence of documentation. -# The default value is: NO. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that doxygen -# can produce. The string should contain the $file, $line, and $text tags, which -# will be replaced by the file and line number from which the warning originated -# and the warning text. Optionally the format may contain $version, which will -# be replaced by the version of the file (if it could be obtained via -# FILE_VERSION_FILTER) -# The default value is: $file:$line: $text. - -WARN_FORMAT = "$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning and error -# messages should be written. If left blank the output is written to standard -# error (stderr). - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# Configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag is used to specify the files and/or directories that contain -# documented source files. You may enter file names like myfile.cpp or -# directories like /usr/src/myproject. Separate the files or directories with -# spaces. -# Note: If this tag is empty the current directory is searched. - -INPUT = "@PROJECT_SOURCE_DIR@/include" "@PROJECT_SOURCE_DIR@/examples" - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses -# libiconv (or the iconv built into libc) for the transcoding. See the libiconv -# documentation (see: http://www.gnu.org/software/libiconv) for the list of -# possible encodings. -# The default value is: UTF-8. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and -# *.h) to filter out the source-files in the directories. If left blank the -# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii, -# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp, -# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown, -# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf, -# *.qsf, *.as and *.js. - -FILE_PATTERNS = - -# The RECURSIVE tag can be used to specify whether or not subdirectories should -# be searched for input files as well. -# The default value is: NO. - -RECURSIVE = YES - -# The EXCLUDE tag can be used to specify files and/or directories that should be -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. -# -# Note that relative paths are relative to the directory from which doxygen is -# run. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or -# directories that are symbolic links (a Unix file system feature) are excluded -# from the input. -# The default value is: NO. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. -# -# Note that the wildcards are matched against the file with absolute path, so to -# exclude all test directories for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test -# -# Note that the wildcards are matched against the file with absolute path, so to -# exclude all test directories use the pattern */test/* - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or directories -# that contain example code fragments that are included (see the \include -# command). - -EXAMPLE_PATH = - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and -# *.h) to filter out the source-files in the directories. If left blank all -# files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude commands -# irrespective of the value of the RECURSIVE tag. -# The default value is: NO. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or directories -# that contain images that are to be included in the documentation (see the -# \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command: -# -# -# -# where is the value of the INPUT_FILTER tag, and is the -# name of an input file. Doxygen will then use the output that the filter -# program writes to standard output. If FILTER_PATTERNS is specified, this tag -# will be ignored. -# -# Note that the filter must not add or remove lines; it is applied before the -# code is scanned, but not when the output code is generated. If lines are added -# or removed, the anchors will not be placed correctly. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. The filters are a list of the form: pattern=filter -# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how -# filters are used. If the FILTER_PATTERNS tag is empty or if none of the -# patterns match the file name, INPUT_FILTER is applied. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER ) will also be used to filter the input files that are used for -# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). -# The default value is: NO. - -FILTER_SOURCE_FILES = NO - -# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file -# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and -# it is also possible to disable source filtering for a specific pattern using -# *.ext= (so without naming a filter). -# This tag requires that the tag FILTER_SOURCE_FILES is set to YES. - -FILTER_SOURCE_PATTERNS = - -# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that -# is part of the input, its contents will be placed on the main page -# (index.html). This can be useful if you have a project on for instance GitHub -# and want to reuse the introduction page also for the doxygen output. - -USE_MDFILE_AS_MAINPAGE = - -#--------------------------------------------------------------------------- -# Configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will be -# generated. Documented entities will be cross-referenced with these sources. -# -# Note: To get rid of all source code in the generated output, make sure that -# also VERBATIM_HEADERS is set to NO. -# The default value is: NO. - -SOURCE_BROWSER = NO - -# Setting the INLINE_SOURCES tag to YES will include the body of functions, -# classes and enums directly into the documentation. -# The default value is: NO. - -INLINE_SOURCES = NO - -# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any -# special comment blocks from generated source code fragments. Normal C, C++ and -# Fortran comments will always remain visible. -# The default value is: YES. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES then for each documented -# function all documented functions referencing it will be listed. -# The default value is: NO. - -REFERENCED_BY_RELATION = NO - -# If the REFERENCES_RELATION tag is set to YES then for each documented function -# all documented entities called/used by that function will be listed. -# The default value is: NO. - -REFERENCES_RELATION = NO - -# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set -# to YES, then the hyperlinks from functions in REFERENCES_RELATION and -# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will -# link to the documentation. -# The default value is: YES. - -REFERENCES_LINK_SOURCE = YES - -# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the -# source code will show a tooltip with additional information such as prototype, -# brief description and links to the definition and documentation. Since this -# will make the HTML file larger and loading of large files a bit slower, you -# can opt to disable this feature. -# The default value is: YES. -# This tag requires that the tag SOURCE_BROWSER is set to YES. - -SOURCE_TOOLTIPS = YES - -# If the USE_HTAGS tag is set to YES then the references to source code will -# point to the HTML generated by the htags(1) tool instead of doxygen built-in -# source browser. The htags tool is part of GNU's global source tagging system -# (see http://www.gnu.org/software/global/global.html). You will need version -# 4.8.6 or higher. -# -# To use it do the following: -# - Install the latest version of global -# - Enable SOURCE_BROWSER and USE_HTAGS in the config file -# - Make sure the INPUT points to the root of the source tree -# - Run doxygen as normal -# -# Doxygen will invoke htags (and that will in turn invoke gtags), so these -# tools must be available from the command line (i.e. in the search path). -# -# The result: instead of the source browser generated by doxygen, the links to -# source code will now point to the output of htags. -# The default value is: NO. -# This tag requires that the tag SOURCE_BROWSER is set to YES. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a -# verbatim copy of the header file for each class for which an include is -# specified. Set to NO to disable this. -# See also: Section \class. -# The default value is: YES. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# Configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all -# compounds will be generated. Enable this if the project contains a lot of -# classes, structs, unions or interfaces. -# The default value is: YES. - -ALPHABETICAL_INDEX = YES - -# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in -# which the alphabetical index list will be split. -# Minimum value: 1, maximum value: 20, default value: 5. -# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all classes will -# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag -# can be used to specify a prefix (or a list of prefixes) that should be ignored -# while generating the index headers. -# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output -# The default value is: YES. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a -# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of -# it. -# The default directory is: html. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each -# generated HTML page (for example: .htm, .php, .asp). -# The default value is: .html. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a user-defined HTML header file for -# each generated HTML page. If the tag is left blank doxygen will generate a -# standard header. -# -# To get valid HTML the header file that includes any scripts and style sheets -# that doxygen needs, which is dependent on the configuration options used (e.g. -# the setting GENERATE_TREEVIEW). It is highly recommended to start with a -# default header using -# doxygen -w html new_header.html new_footer.html new_stylesheet.css -# YourConfigFile -# and then modify the file new_header.html. See also section "Doxygen usage" -# for information on how to generate the default header that doxygen normally -# uses. -# Note: The header is subject to change so you typically have to regenerate the -# default header when upgrading to a newer version of doxygen. For a description -# of the possible markers and block names see the documentation. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each -# generated HTML page. If the tag is left blank doxygen will generate a standard -# footer. See HTML_HEADER for more information on how to generate a default -# footer and what special commands can be used inside the footer. See also -# section "Doxygen usage" for information on how to generate the default footer -# that doxygen normally uses. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style -# sheet that is used by each HTML page. It can be used to fine-tune the look of -# the HTML output. If left blank doxygen will generate a default style sheet. -# See also section "Doxygen usage" for information on how to generate the style -# sheet that doxygen normally uses. -# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as -# it is more robust and this tag (HTML_STYLESHEET) will in the future become -# obsolete. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_STYLESHEET = - -# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user- -# defined cascading style sheet that is included after the standard style sheets -# created by doxygen. Using this option one can overrule certain style aspects. -# This is preferred over using HTML_STYLESHEET since it does not replace the -# standard style sheet and is therefor more robust against future updates. -# Doxygen will copy the style sheet file to the output directory. For an example -# see the documentation. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_EXTRA_STYLESHEET = - -# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or -# other source files which should be copied to the HTML output directory. Note -# that these files will be copied to the base HTML output directory. Use the -# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these -# files. In the HTML_STYLESHEET file, use the file name only. Also note that the -# files will be copied as-is; there are no commands or markers available. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_EXTRA_FILES = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen -# will adjust the colors in the stylesheet and background images according to -# this color. Hue is specified as an angle on a colorwheel, see -# http://en.wikipedia.org/wiki/Hue for more information. For instance the value -# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 -# purple, and 360 is red again. -# Minimum value: 0, maximum value: 359, default value: 220. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors -# in the HTML output. For a value of 0 the output will use grayscales only. A -# value of 255 will produce the most vivid colors. -# Minimum value: 0, maximum value: 255, default value: 100. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the -# luminance component of the colors in the HTML output. Values below 100 -# gradually make the output lighter, whereas values above 100 make the output -# darker. The value divided by 100 is the actual gamma applied, so 80 represents -# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not -# change the gamma. -# Minimum value: 40, maximum value: 240, default value: 80. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting this -# to NO can help when comparing the output of multiple runs. -# The default value is: YES. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_TIMESTAMP = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_DYNAMIC_SECTIONS = NO - -# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries -# shown in the various tree structured indices initially; the user can expand -# and collapse entries dynamically later on. Doxygen will expand the tree to -# such a level that at most the specified number of entries are visible (unless -# a fully collapsed tree already exceeds this amount). So setting the number of -# entries 1 will produce a full collapsed tree by default. 0 is a special value -# representing an infinite number of entries and will result in a full expanded -# tree by default. -# Minimum value: 0, maximum value: 9999, default value: 100. -# This tag requires that the tag GENERATE_HTML is set to YES. - -HTML_INDEX_NUM_ENTRIES = 100 - -# If the GENERATE_DOCSET tag is set to YES, additional index files will be -# generated that can be used as input for Apple's Xcode 3 integrated development -# environment (see: http://developer.apple.com/tools/xcode/), introduced with -# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a -# Makefile in the HTML output directory. Running make will produce the docset in -# that directory and running make install will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at -# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -GENERATE_DOCSET = NO - -# This tag determines the name of the docset feed. A documentation feed provides -# an umbrella under which multiple documentation sets from a single provider -# (such as a company or product suite) can be grouped. -# The default value is: Doxygen generated docs. -# This tag requires that the tag GENERATE_DOCSET is set to YES. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# This tag specifies a string that should uniquely identify the documentation -# set bundle. This should be a reverse domain-name style string, e.g. -# com.mycompany.MyDocSet. Doxygen will append .docset to the name. -# The default value is: org.doxygen.Project. -# This tag requires that the tag GENERATE_DOCSET is set to YES. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. -# The default value is: org.doxygen.Publisher. -# This tag requires that the tag GENERATE_DOCSET is set to YES. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. -# The default value is: Publisher. -# This tag requires that the tag GENERATE_DOCSET is set to YES. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three -# additional HTML index files: index.hhp, index.hhc, and index.hhk. The -# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop -# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on -# Windows. -# -# The HTML Help Workshop contains a compiler that can convert all HTML output -# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML -# files are now used as the Windows 98 help format, and will replace the old -# Windows help format (.hlp) on all Windows platforms in the future. Compressed -# HTML files also contain an index, a table of contents, and you can search for -# words in the documentation. The HTML workshop also contains a viewer for -# compressed HTML files. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -GENERATE_HTMLHELP = NO - -# The CHM_FILE tag can be used to specify the file name of the resulting .chm -# file. You can add a path in front of the file if the result should not be -# written to the html output directory. -# This tag requires that the tag GENERATE_HTMLHELP is set to YES. - -CHM_FILE = - -# The HHC_LOCATION tag can be used to specify the location (absolute path -# including file name) of the HTML help compiler ( hhc.exe). If non-empty -# doxygen will try to run the HTML help compiler on the generated index.hhp. -# The file has to be specified with full path. -# This tag requires that the tag GENERATE_HTMLHELP is set to YES. - -HHC_LOCATION = - -# The GENERATE_CHI flag controls if a separate .chi index file is generated ( -# YES) or that it should be included in the master .chm file ( NO). -# The default value is: NO. -# This tag requires that the tag GENERATE_HTMLHELP is set to YES. - -GENERATE_CHI = NO - -# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc) -# and project file content. -# This tag requires that the tag GENERATE_HTMLHELP is set to YES. - -CHM_INDEX_ENCODING = - -# The BINARY_TOC flag controls whether a binary table of contents is generated ( -# YES) or a normal table of contents ( NO) in the .chm file. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTMLHELP is set to YES. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members to -# the table of contents of the HTML help documentation and to the tree view. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTMLHELP is set to YES. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that -# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help -# (.qch) of the generated HTML documentation. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify -# the file name of the resulting .qch file. The path specified is relative to -# the HTML output folder. -# This tag requires that the tag GENERATE_QHP is set to YES. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help -# Project output. For more information please see Qt Help Project / Namespace -# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). -# The default value is: org.doxygen.Project. -# This tag requires that the tag GENERATE_QHP is set to YES. - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt -# Help Project output. For more information please see Qt Help Project / Virtual -# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- -# folders). -# The default value is: doc. -# This tag requires that the tag GENERATE_QHP is set to YES. - -QHP_VIRTUAL_FOLDER = doc - -# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom -# filter to add. For more information please see Qt Help Project / Custom -# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- -# filters). -# This tag requires that the tag GENERATE_QHP is set to YES. - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see Qt Help Project / Custom -# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- -# filters). -# This tag requires that the tag GENERATE_QHP is set to YES. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's filter section matches. Qt Help Project / Filter Attributes (see: -# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). -# This tag requires that the tag GENERATE_QHP is set to YES. - -QHP_SECT_FILTER_ATTRS = - -# The QHG_LOCATION tag can be used to specify the location of Qt's -# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the -# generated .qhp file. -# This tag requires that the tag GENERATE_QHP is set to YES. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be -# generated, together with the HTML files, they form an Eclipse help plugin. To -# install this plugin and make it available under the help contents menu in -# Eclipse, the contents of the directory containing the HTML and XML files needs -# to be copied into the plugins directory of eclipse. The name of the directory -# within the plugins directory should be the same as the ECLIPSE_DOC_ID value. -# After copying Eclipse needs to be restarted before the help appears. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the Eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have this -# name. Each documentation set should have its own identifier. -# The default value is: org.doxygen.Project. -# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# If you want full control over the layout of the generated HTML pages it might -# be necessary to disable the index and replace it with your own. The -# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top -# of each HTML page. A value of NO enables the index and the value YES disables -# it. Since the tabs in the index contain the same information as the navigation -# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -DISABLE_INDEX = NO - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. If the tag -# value is set to YES, a side panel will be generated containing a tree-like -# index structure (just like the one that is generated for HTML Help). For this -# to work a browser that supports JavaScript, DHTML, CSS and frames is required -# (i.e. any modern browser). Windows users are probably better off using the -# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can -# further fine-tune the look of the index. As an example, the default style -# sheet generated by doxygen has an example that shows how to put an image at -# the root of the tree instead of the PROJECT_NAME. Since the tree basically has -# the same information as the tab index, you could consider setting -# DISABLE_INDEX to YES when enabling this option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -GENERATE_TREEVIEW = NO - -# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that -# doxygen will group on one line in the generated HTML documentation. -# -# Note that a value of 0 will completely suppress the enum values from appearing -# in the overview section. -# Minimum value: 0, maximum value: 20, default value: 4. -# This tag requires that the tag GENERATE_HTML is set to YES. - -ENUM_VALUES_PER_LINE = 4 - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used -# to set the initial width (in pixels) of the frame in which the tree is shown. -# Minimum value: 0, maximum value: 1500, default value: 250. -# This tag requires that the tag GENERATE_HTML is set to YES. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to -# external symbols imported via tag files in a separate window. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of LaTeX formulas included as images in -# the HTML documentation. When you change the font size after a successful -# doxygen run you need to manually remove any form_*.png images from the HTML -# output directory to force them to be regenerated. -# Minimum value: 8, maximum value: 50, default value: 10. -# This tag requires that the tag GENERATE_HTML is set to YES. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are not -# supported properly for IE 6.0, but are supported on all modern browsers. -# -# Note that when changing this option you need to delete any form_*.png files in -# the HTML output directory before the changes have effect. -# The default value is: YES. -# This tag requires that the tag GENERATE_HTML is set to YES. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When MathJax is enabled you can set the default output format to be used for -# the MathJax output. See the MathJax site (see: -# http://docs.mathjax.org/en/latest/output.html) for more details. -# Possible values are: HTML-CSS (which is slower, but has the best -# compatibility), NativeMML (i.e. MathML) and SVG. -# The default value is: HTML-CSS. -# This tag requires that the tag USE_MATHJAX is set to YES. - -MATHJAX_FORMAT = HTML-CSS - -# When MathJax is enabled you need to specify the location relative to the HTML -# output directory using the MATHJAX_RELPATH option. The destination directory -# should contain the MathJax.js script. For instance, if the mathjax directory -# is located at the same level as the HTML output directory, then -# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax -# Content Delivery Network so you can quickly see the result without installing -# MathJax. However, it is strongly recommended to install a local copy of -# MathJax from http://www.mathjax.org before deployment. -# The default value is: http://cdn.mathjax.org/mathjax/latest. -# This tag requires that the tag USE_MATHJAX is set to YES. - -MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest - -# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax -# extension names that should be enabled during MathJax rendering. For example -# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols -# This tag requires that the tag USE_MATHJAX is set to YES. - -MATHJAX_EXTENSIONS = - -# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces -# of code that will be used on startup of the MathJax code. See the MathJax site -# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an -# example see the documentation. -# This tag requires that the tag USE_MATHJAX is set to YES. - -MATHJAX_CODEFILE = - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box for -# the HTML output. The underlying search engine uses javascript and DHTML and -# should work on any modern browser. Note that when using HTML help -# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) -# there is already a search function so this one should typically be disabled. -# For large projects the javascript based search engine can be slow, then -# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to -# search using the keyboard; to jump to the search box use + S -# (what the is depends on the OS and browser, but it is typically -# , /here. - * - * If not provided, application::register_default_buttons_callbacks function will be used, which assumes that the - * UI has GtkButton widgets named "ZoomFitButton", "ZoomInButton", "ZoomOutButton", "UpButton", "DownButton", - * "LeftButton", "RightButton", "ProceedButton" - */ - connect_g_objects_fn setup_callbacks; - - /** - * Create the settings structure with default values - */ - settings() - : main_ui_resource(build_ui_from_file ? "main_ui" : "/ezgl/main.ui"), window_identifier("MainWindow"), canvas_identifier("MainCanvas"), application_identifier("ezgl.app"), - setup_callbacks(nullptr) - { - // Uniquify the application_identifier by appending a time stamp, - // so that each instance of the same program has a different application ID. - // This allows multiple instance of the program to run independelty. - application_identifier += ".t" + std::to_string(std::time(nullptr)); - } - - /** - * Create the settings structure with user-defined values - */ - settings(std::string m_resource, std::string w_identifier, std::string c_identifier, std::string a_identifier = "ezgl.app", - connect_g_objects_fn s_callbacks = nullptr) - : main_ui_resource(m_resource), window_identifier(w_identifier), canvas_identifier(c_identifier), application_identifier(a_identifier), - setup_callbacks(s_callbacks) - { - // Uniquify the application_identifier by appending a time stamp, - // so that each instance of the same program has a different application ID. - // This allows multiple instance of the program to run independelty. - application_identifier += ".t" + std::to_string(std::time(nullptr)); - } - }; - -public: - /** - * Create an application. - * - * @param s The preconfigured settings. - */ - explicit application(application::settings s); - - /** - * Add a canvas to the application. - * - * If the canvas has already been added, it will not be overwritten and a warning will be displayed. - * - * @param canvas_id The id of the GtkDrawingArea in the XML file. - * @param draw_callback The function to call that draws to this canvas. - * @param coordinate_system The initial coordinate system of this canvas. - * @param background_color (OPTIONAL) The color of the canvas background. Default is WHITE. - * - * @return A pointer to the newly created canvas. - */ - canvas *add_canvas(std::string const &canvas_id, - draw_canvas_fn draw_callback, - rectangle coordinate_system, - color background_color = WHITE); - - /** - * Add a button - * - * @param button_text the new button text - * @param left the column number to attach the left side of the new button to - * @param top the row number to attach the top side of the new button to - * @param width the number of columns that the button will span - * @param height the number of rows that the button will span - * @param button_func callback function for the button - * - * The function assumes that the UI has a GtkGrid named "InnerGrid" - */ - void create_button(const char *button_text, - int left, - int top, - int width, - int height, - button_callback_fn button_func); - - /** - * Add a button convenience - * Adds a button at a given row index (assuming buttons in the right bar use 1 row each) - * by inserting a row in the grid and adding the button. Uses the default width of 3 and height of 1 - * - * @param button_text the new button text - * @param insert_row the row in the right bar to insert the button - * @param button_func callback function for the button - * - * The function assumes that the UI has a GtkGrid named "InnerGrid" - */ - void create_button(const char *button_text, int insert_row, button_callback_fn button_func); - - /** - * Deletes a button by its label (displayed text) - * - * @param the text of the button to delete - * @return whether the button was found and deleted - * - * The function assumes that the UI has a GtkGrid named "InnerGrid" - */ - bool destroy_button(const char *button_text_to_destroy); - - /** - * Change the label of the button (displayed text) - * - * @param button_text the old text of the button - * @param new_button_text the new button text - * - * The function assumes that the UI has a GtkGrid named "InnerGrid" - */ - void change_button_text(const char *button_text, const char *new_button_text); - - /** - * Update the message in the status bar - * - * @param message The message that will be displayed on the status bar - * - * The function assumes that the UI has a GtkStatusbar named "StatusBar" - */ - void update_message(std::string const &message); - - /** - * Change the coordinate system of a created canvas - * - * @param canvas_id The id of the GtkDrawingArea in the XML file. - * @param coordinate_system The new coordinate system of this canvas. - */ - void change_canvas_world_coordinates(std::string const &canvas_id, rectangle coordinate_system); - - /** - * redraw the main canvas - */ - void refresh_drawing(); - - /** - * Get a renderer that can be used to draw on top of the main canvas - */ - renderer *get_renderer(); - - /** - * Flush the drawings done by the renderer, returned from get_renderer(), to the on-screen buffer - * - * The flushing is done immediately - */ - void flush_drawing(); - - /** - * Run the application. - * - * Once this is called, the application will be initialized first. Initialization will build the GUI based on the XML - * resource given in the constructor. Once the GUI has been created, the function initial_setup_user_callback will be - * called. - * - * After initialization, control of the program will be given to GTK. You will only regain control for the signals - * that you have registered callbacks for. - * - * @param initial_setup_user_callback A user-defined function that is called before application activation - * @param mouse_press_user_callback The user-defined callback function for mouse press - * @param mouse_move_user_callback The user-defined callback function for mouse move - * @param key_press_user_callback The user-defined callback function for keyboard press - * - * @return The exit status. - */ - int run(setup_callback_fn initial_setup_user_callback, - mouse_callback_fn mouse_press_user_callback, - mouse_callback_fn mouse_move_user_callback, - key_callback_fn key_press_user_callback); - - /** - * Destructor. - */ - ~application(); - - /** - * Copies are disabled. - */ - application(application const &) = delete; - - /** - * Copies are disabled. - */ - application &operator=(application const &) = delete; - - /** - * Ownership of an application is transferrable. - */ - application(application &&) = default; - - /** - * Ownership of an application is transferrable. - */ - application &operator=(application &&) = default; - - /** - * Retrieve a pointer to a canvas that was previously added to the application. - * - * Calling this function before application::run results in undefined behaviour. - * - * @param canvas_id The key used when the canvas was added. - * - * @return A non-owning pointer, or nullptr if not found. - * - * @see application::get_object - */ - canvas *get_canvas(std::string const &canvas_id) const; - - /** - * Retrieve a GLib Object (i.e., a GObject). - * - * This is useful for retrieving GUI elements specified in your XML file(s). You should only call this function after - * the application has been run, otherwise the GUI elements will have not been created yet. - * - * @param name The ID of the object. - * @return The object with the ID, or NULL if it could not be found. - * - * @see application::run - */ - GObject *get_object(gchar const *name) const; - - /** - * Get the ID of the main window - */ - std::string get_main_window_id() const - { - return m_window_id; - } - - /** - * Get the ID of the main canvas - */ - std::string get_main_canvas_id() const - { - return m_canvas_id; - } - - /** - * Quit the application - */ - void quit(); - -private: - // The package path to the XML file that describes the UI. - std::string m_main_ui; - - // The ID of the main window to add to our GTK application. - std::string m_window_id; - - // The ID of the main canvas - std::string m_canvas_id; - - // The ID of the GTK application - std::string m_application_id; - - // The GTK application. - GtkApplication *m_application; - - // The GUI builder that parses an XML user interface. - GtkBuilder *m_builder; - - // The function to call when the application is starting up. - connect_g_objects_fn m_register_callbacks; - - // The collection of canvases added to the application. - std::map> m_canvases; - - // A flag that indicates if the run() was called before or not to allow multiple reruns - bool first_run; - - // A flag that indicates if we are resuming an older run to allow proper quitting - bool resume_run; - -private: - // Called when our GtkApplication is initialized for the first time. - static void startup(GtkApplication *gtk_app, gpointer user_data); - - // Called when GTK activates our application for the first time. - static void activate(GtkApplication *gtk_app, gpointer user_data); - - // Called during application activation to setup the default callbacks for the prebuilt buttons - static void register_default_buttons_callbacks(application *application); - - // Called during application activation to setup the default callbacks for the mouse and key events - static void register_default_events_callbacks(application *application); - -public: - // The user-defined initial setup callback function - setup_callback_fn initial_setup_callback; - - // The user-defined callback function for handling mouse press - mouse_callback_fn mouse_press_callback; - - // The user-defined callback function for handling mouse move - mouse_callback_fn mouse_move_callback; - - // The user-defined callback function for handling keyboard press - key_callback_fn key_press_callback; -}; - -/** - * Set the disable_event_loop flag to new_setting - * Call with new_setting == true to make the event_loop immediately return. - * - * @param new_setting The new state of disable_event_loop flag - */ -void set_disable_event_loop(bool new_setting); -} - -#endif //EZGL_APPLICATION_HPP diff --git a/libs/EXTERNAL/libezgl/include/ezgl/callback.hpp b/libs/EXTERNAL/libezgl/include/ezgl/callback.hpp deleted file mode 100644 index 10414880e1b..00000000000 --- a/libs/EXTERNAL/libezgl/include/ezgl/callback.hpp +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#ifndef EZGL_CALLBACK_HPP -#define EZGL_CALLBACK_HPP - -#include "ezgl/application.hpp" -#include "ezgl/camera.hpp" -#include "ezgl/canvas.hpp" -#include "ezgl/control.hpp" -#include "ezgl/graphics.hpp" - -#include - -// Mouse button used for panning (left button (1) - middle button (2) - right button (3)) -#define PANNING_MOUSE_BUTTON 1 - -namespace ezgl { - -/**** Callback functions for keyboard and mouse input, and for all the ezgl predefined buttons. *****/ - -/** - * React to a keyboard - * press event. - * - * @param widget The GUI widget where this event came from. - * @param event The keyboard event. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_key(GtkWidget *widget, GdkEventKey *event, gpointer data); - -/** - * React to mouse click - * event - * - * @param widget The GUI widget where this event came from. - * @param event The click event. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_mouse(GtkWidget *widget, GdkEventButton *event, gpointer data); - -/** - * React to mouse release - * event - * - * @param widget The GUI widget where this event came from. - * @param event The click event. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean release_mouse(GtkWidget *widget, GdkEventButton *event, gpointer data); - -/** - * React to mouse release - * event - * - * @param widget The GUI widget where this event came from. - * @param event The click event. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean move_mouse(GtkWidget *widget, GdkEventButton *event, gpointer data); - -/** - * React to scroll_event - * event - * - * @param widget The GUI widget where this event came from. - * @param event The click event. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean scroll_mouse(GtkWidget *widget, GdkEvent *event, gpointer data); - -/** - * React to the clicked zoom_fit button - * - * @param widget The GUI widget where this event came from. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_zoom_fit(GtkWidget *widget, gpointer data); - -/** - * React to the clicked zoom_in button - * - * @param widget The GUI widget where this event came from. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_zoom_in(GtkWidget *widget, gpointer data); - -/** - * React to the clicked zoom_out button - * - * @param widget The GUI widget where this event came from. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_zoom_out(GtkWidget *widget, gpointer data); - -/** - * React to the clicked up button - * - * @param widget The GUI widget where this event came from. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_up(GtkWidget *widget, gpointer data); - -/** - * React to the clicked up button - * - * @param widget The GUI widget where this event came from. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_down(GtkWidget *widget, gpointer data); - -/** - * React to the clicked up button - * - * @param widget The GUI widget where this event came from. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_left(GtkWidget *widget, gpointer data); - -/** - * React to the clicked up button - * - * @param widget The GUI widget where this event came from. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_right(GtkWidget *widget, gpointer data); - -/** - * React to the clicked proceed button - * - * @param widget The GUI widget where this event came from. - * @param data A pointer to any user-specified data you passed in. - * - * @return FALSE to allow other handlers to see this event, too. TRUE otherwise. - */ -gboolean press_proceed(GtkWidget *widget, gpointer data); -} - -#endif //EZGL_CALLBACK_HPP diff --git a/libs/EXTERNAL/libezgl/include/ezgl/camera.hpp b/libs/EXTERNAL/libezgl/include/ezgl/camera.hpp deleted file mode 100644 index fb3e4d1a7e6..00000000000 --- a/libs/EXTERNAL/libezgl/include/ezgl/camera.hpp +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#ifndef EZGL_CAMERA_HPP -#define EZGL_CAMERA_HPP - -#include "ezgl/point.hpp" -#include "ezgl/rectangle.hpp" - -namespace ezgl { - -/** - * Manages the transformations between coordinate systems. - * Application code doesn't (and can't) call these functions; they are for ezgl internal use. - * - * The camera class manages transformations between a GTK widget, world, and "screen" coordinate system. A GTK widget - * has dimensions that change based on the user, and its aspect ratio may not match the world coordinate system. The - * camera maintains a "screen" within the widget that keeps the same aspect ratio as the world coordinate system, - * regardless of the dimensions of the widget. - * - * A camera object can only be created by an ezgl::canvas object, who has the responsibility of updating the camera with - * changes to the widget's dimensions. The only state that can be mutated outside the library is the camera's world - * coordinate system. - */ -class camera { -public: - /** - * Convert a point in world coordinates to screen coordinates. - */ - point2d world_to_screen(point2d world_coordinates) const; - - /** - * Convert a point in widget coordinates to screen coordinates. - */ - point2d widget_to_screen(point2d widget_coordinates) const; - - /** - * Convert a point in widget coordinates to world coordinates. - */ - point2d widget_to_world(point2d widget_coordinates) const; - - /** - * Get the currently visible bounds of the world. - */ - rectangle get_world() const - { - return m_world; - } - - /** - * Get the dimensions of the screen. - */ - rectangle get_screen() const - { - return m_screen; - } - - /** - * Get the dimensions of the widget. - */ - rectangle get_widget() const - { - return m_widget; - } - - /** - * Get the initial bounds of the world. Needed for zoom_fit - */ - rectangle get_initial_world() const - { - return m_initial_world; - } - - /** - * Update the visible bounds of the world. - * - * Used in panning and zooming. - */ - void set_world(rectangle new_world); - - /** - * Reset the world coordinates - * - * Used by change_canvas_world_coordinates(). - */ - void reset_world(rectangle new_world); - - /** - * Get the screen to world scaling factor. - */ - point2d get_world_scale_factor() const - { - return m_screen_to_world; - } - -protected: - // Only an ezgl::canvas can create a camera. - friend class canvas; - - /** - * Create a camera. - * - * @param bounds The initial bounds of the coordinate system. - */ - explicit camera(rectangle bounds); - - /** - * Update the dimensions of the widget. - * - * This will change the screen where the world is projected. The screen will maintain the aspect ratio of the world's - * coordinate system while being centered within the screen. - * - * @see canvas::configure_event - */ - void update_widget(int width, int height); - - /** - * Update the scaling factors. - */ - void update_scale_factors(); - -private: - // The dimensions of the parent widget. - rectangle m_widget = {{0, 0}, 1.0, 1.0}; - - // The dimensions of the world (user-defined bounding box). - rectangle m_world; - - // The dimensions of the screen, which may not match the widget. - rectangle m_screen; - - // The dimensions of the initial world (user-defined bounding box). Needed for zoom_fit - rectangle m_initial_world; - - // The x and y scaling factors. - point2d m_world_to_widget = {1.0, 1.0}; - point2d m_widget_to_screen = {1.0, 1.0}; - point2d m_screen_to_world = {1.0, 1.0}; -}; -} - -#endif //EZGL_CAMERA_HPP diff --git a/libs/EXTERNAL/libezgl/include/ezgl/canvas.hpp b/libs/EXTERNAL/libezgl/include/ezgl/canvas.hpp deleted file mode 100644 index b6aa475009e..00000000000 --- a/libs/EXTERNAL/libezgl/include/ezgl/canvas.hpp +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#ifndef EZGL_CANVAS_HPP -#define EZGL_CANVAS_HPP - -#include "ezgl/camera.hpp" -#include "ezgl/rectangle.hpp" -#include "ezgl/graphics.hpp" -#include "ezgl/color.hpp" - -#include -#include -#include -#include - -#include - -namespace ezgl { - -/**** Functions in this class are for ezgl internal use; application code doesn't need to call them ****/ - -class renderer; - -/** - * The signature of a function that draws to an ezgl::canvas. - */ -using draw_canvas_fn = void (*)(renderer*); - -/** - * Responsible for creating, destroying, and maintaining the rendering context of a GtkWidget. - * - * Underneath, the class relies on a GtkDrawingArea as its GUI widget along with cairo to provide the rendering context. - * The class connects to the relevant GTK signals, namely configure and draw events, to remain responsive. - * - * Each canvas is double-buffered. A draw callback (see: ezgl::draw_canvas_fn) is invoked each time the canvas needs to - * be redrawn. This may be caused by the user (e.g., resizing the screen), but can also be forced by the programmer. - */ -class canvas { -public: - /** - * Destructor. - */ - ~canvas(); - - /** - * Get the name (identifier) of the canvas. - */ - char const *id() const - { - return m_canvas_id.c_str(); - } - - /** - * Get the width of the canvas in pixels. - */ - int width() const; - - /** - * Get the height of the canvas in pixels. - */ - int height() const; - - /** - * Force the canvas to redraw itself. - * - * This will invoke the ezgl::draw_canvas_fn callback and queue a redraw of the GtkWidget. - */ - void redraw(); - - /** - * Get an immutable reference to this canvas' camera. - */ - camera const &get_camera() const - { - return m_camera; - } - - /** - * Get a mutable reference to this canvas' camera. - */ - camera &get_camera() - { - return m_camera; - } - - /** - * Create an animation renderer that can be used to draw on top of the current canvas - */ - renderer *create_animation_renderer(); - - /** - * print_pdf, print_svg, and print_png generate a PDF, SVG, or PNG output file showing - * all the graphical content of the current canvas. - * - * @param file_name name of the output file - * @return returns true if the function has successfully generated the output file, otherwise - * failed due to errors such as out of memory occurs. - */ - bool print_pdf(const char *file_name, int width = 0, int height = 0); - bool print_svg(const char *file_name, int width = 0, int height = 0); - bool print_png(const char *file_name, int width = 0, int height = 0); - - -protected: - // Only the ezgl::application can create and initialize a canvas object. - friend class application; - - /** - * Create a canvas that can be drawn to. - */ - canvas(std::string canvas_id, draw_canvas_fn draw_callback, rectangle coordinate_system, color background_color); - - /** - * Lazy initialization of the canvas class. - * - * This function is required because GTK will not send activate/startup signals to an ezgl::application until control - * of the program has been reliquished. The GUI is not built until ezgl::application receives an activate signal. - */ - void initialize(GtkWidget *drawing_area); - -private: - // Name of the canvas in XML. - std::string m_canvas_id; - - // The function to call when the widget needs to be redrawn. - draw_canvas_fn m_draw_callback; - - // The transformations between the GUI and the world. - camera m_camera; - - // The background color of the drawing area - color m_background_color; - - // A non-owning pointer to the drawing area inside a GTK window. - GtkWidget *m_drawing_area = nullptr; - - // The off-screen surface that can be drawn to. - cairo_surface_t *m_surface = nullptr; - - // The off-screen cairo context that can be drawn to - cairo_t *m_context = nullptr; - - // The animation renderer - renderer *m_animation_renderer = nullptr; - -private: - // Called each time our drawing area widget has changed (e.g., in size). - static gboolean configure_event(GtkWidget *widget, GdkEventConfigure *event, gpointer data); - - // Called each time we need to draw to our drawing area widget. - static gboolean draw_surface(GtkWidget *widget, cairo_t *context, gpointer data); -}; -} - -#endif //EZGL_CANVAS_HPP diff --git a/libs/EXTERNAL/libezgl/include/ezgl/color.hpp b/libs/EXTERNAL/libezgl/include/ezgl/color.hpp deleted file mode 100644 index d963372ff81..00000000000 --- a/libs/EXTERNAL/libezgl/include/ezgl/color.hpp +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#ifndef EZGL_COLOR_HPP -#define EZGL_COLOR_HPP - -#include - -namespace ezgl { - -/** - * Represents a color as a mixture or red, green, and blue as well as the transparency level. - * - * Each color channel and transparency level is an 8-bit value, ranging from 0-255. - */ -struct color { - /** - * Default constructor: Create a black color. - */ - constexpr color() noexcept - : red(0), green(0), blue(0), alpha(255) - { - } - - /** - * Create a color. - * - * @param r The amount of red. - * @param g The amount of green. - * @param b The amount of blue. - * @param a The level of transparency. - */ - constexpr color(std::uint_fast8_t r, - std::uint_fast8_t g, - std::uint_fast8_t b, - std::uint_fast8_t a = 255) noexcept - : red(r), green(g), blue(b), alpha(a) - { - } - - /** - * A red component of the color, between 0 and 255. - */ - std::uint_fast8_t red; - - /** - * The green component of the color, between 0 and 255. - */ - std::uint_fast8_t green; - - /** - * The blue component of the color, between 0 and 255. - */ - std::uint_fast8_t blue; - - /** - * The amount of transparency, between 0 and 255. - */ - std::uint_fast8_t alpha; - - /** - * Test for equality. - */ - bool operator==(const color &rhs) const - { - return red == rhs.red && green == rhs.green && blue == rhs.blue && alpha == rhs.alpha; - } - - /** - * Test for inequality. - */ - bool operator!=(const color &rhs) const - { - return !(rhs == *this); - } -}; - -static constexpr color WHITE(0xFF, 0xFF, 0xFF); -static constexpr color BLACK(0x00, 0x00, 0x00); -static constexpr color GREY_55(0x8C, 0x8C, 0x8C); -static constexpr color GREY_75(0xBF, 0xBF, 0xBF); -static constexpr color RED(0xFF, 0x00, 0x00); -static constexpr color ORANGE(0xFF, 0xA5, 0x00); -static constexpr color YELLOW(0xFF, 0xFF, 0x00); -static constexpr color GREEN(0x00, 0xFF, 0x00); -static constexpr color CYAN(0x00, 0xFF, 0xFF); -static constexpr color BLUE(0x00, 0x00, 0xFF); -static constexpr color PURPLE(0xA0, 0x20, 0xF0); -static constexpr color PINK(0xFF, 0xC0, 0xCB); -static constexpr color LIGHT_PINK(0xFF, 0xB6, 0xC1); -static constexpr color DARK_GREEN(0x00, 0x64, 0x00); -static constexpr color MAGENTA(0xFF, 0x00, 0xFF); -static constexpr color BISQUE(0xFF, 0xE4, 0xC4); -static constexpr color LIGHT_SKY_BLUE(0x87, 0xCE, 0xFA); -static constexpr color THISTLE(0xD8, 0xBF, 0xD8); -static constexpr color PLUM(0xDD, 0xA0, 0xDD); -static constexpr color KHAKI(0xF0, 0xE6, 0x8C); -static constexpr color CORAL(0xFF, 0x7F, 0x50); -static constexpr color TURQUOISE(0x40, 0xE0, 0xD0); -static constexpr color MEDIUM_PURPLE(0x93, 0x70, 0xDB); -static constexpr color DARK_SLATE_BLUE(0x48, 0x3D, 0x8B); -static constexpr color DARK_KHAKI(0xBD, 0xB7, 0x6B); -static constexpr color LIGHT_MEDIUM_BLUE(0x44, 0x44, 0xFF); -static constexpr color SADDLE_BROWN(0x8B, 0x45, 0x13); -static constexpr color FIRE_BRICK(0xB2, 0x22, 0x22); -static constexpr color LIME_GREEN(0x32, 0xCD, 0x32); -} - -#endif //EZGL_COLOR_HPP diff --git a/libs/EXTERNAL/libezgl/include/ezgl/control.hpp b/libs/EXTERNAL/libezgl/include/ezgl/control.hpp deleted file mode 100644 index 82898e8ff36..00000000000 --- a/libs/EXTERNAL/libezgl/include/ezgl/control.hpp +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#ifndef EZGL_CONTROL_HPP -#define EZGL_CONTROL_HPP - -#include "ezgl/point.hpp" -#include "ezgl/rectangle.hpp" - -namespace ezgl { - -/**** Functions to manipulate what is visible on the screen; used by ezgl's predefined buttons. ****/ -/**** Application code does not have to ever call these functions. ****/ - -class canvas; - -/** - * Zoom in on the center of the currently visible world. - */ -void zoom_in(canvas *cnv, double zoom_factor); - -/** - * Zoom out from the center of the currently visible world. - */ -void zoom_out(canvas *cnv, double zoom_factor); - -/** - * Zoom in on a specific point in the GTK widget. - */ -void zoom_in(canvas *cnv, point2d zoom_point, double zoom_factor); - -/** - * Zoom out from a specific point in GTK widget. - */ -void zoom_out(canvas *cnv, point2d zoom_point, double zoom_factor); - -/** - * Zoom in or out to fit an exact region of the world. - */ -void zoom_fit(canvas *cnv, rectangle region); - -/** - * Translate by delta x and delta y (dx, dy) - */ -void translate(canvas *cnv, double dx, double dy); - -/** - * Translate up - */ -void translate_up(canvas *cnv, double translate_factor); - -/** - * Translate down - */ -void translate_down(canvas *cnv, double translate_factor); - -/** - * Translate left - */ -void translate_left(canvas *cnv, double translate_factor); - -/** - * Translate right - */ -void translate_right(canvas *cnv, double translate_factor); -} - -#endif //EZGL_CONTROL_HPP diff --git a/libs/EXTERNAL/libezgl/include/ezgl/graphics.hpp b/libs/EXTERNAL/libezgl/include/ezgl/graphics.hpp deleted file mode 100644 index 7b7250baa5c..00000000000 --- a/libs/EXTERNAL/libezgl/include/ezgl/graphics.hpp +++ /dev/null @@ -1,540 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#ifndef EZGL_GRAPHICS_HPP -#define EZGL_GRAPHICS_HPP - -#include "ezgl/color.hpp" -#include "ezgl/point.hpp" -#include "ezgl/rectangle.hpp" -#include "ezgl/camera.hpp" - -#include -#include - -#ifdef CAIRO_HAS_XLIB_SURFACE -#ifdef GDK_WINDOWING_X11 -#include - -// Speed up draw calls by using X11 instead of cairo wherever possible. -#define EZGL_USE_X11 -#endif -#endif - -#include -#include -#include -#include -#include -#include - -namespace ezgl { - -/** - * define ezgl::surface type used for drawing pngs - */ -typedef cairo_surface_t surface; - -/** - * Available coordinate systems - */ -enum t_coordinate_system { - /** - * Default coordinate system - */ - WORLD, - /** - * Screen coordinate system. Screen Coordinates are not transformed so the drawn objects do not pan or zoom. - */ - SCREEN -}; - -/** - * Justification options (used for text and surfaces) - */ -enum class justification { - /** - * Center Justification: used for both vertical and horizontal justification - */ - center, - /** - * Left justification: used for horizontal justification - */ - left, - /** - * Right justification: used for horizontal justification - */ - right, - /** - * Top justification: used for vertical justification - */ - top, - /** - * Bottom justification: used for vertical justification - */ - bottom -}; - -/** - * The slant of the font. - * - * This enum is setup to match with the cairo graphics library and should not be changed. - */ -enum class font_slant : int { - /** - * No slant. - */ - normal = CAIRO_FONT_SLANT_NORMAL, - - /** - * Slant is more calligraphic. Make sure the font you're using has an italic design, otherwise it may look ugly. - */ - italic = CAIRO_FONT_SLANT_ITALIC, - - /** - * Slanted to the right. - */ - oblique = CAIRO_FONT_SLANT_OBLIQUE -}; - -/** - * The weight of the font. - */ -enum class font_weight : int { - /** - * No additional weight. - */ - normal = CAIRO_FONT_WEIGHT_NORMAL, - - /** - * Bold font weight. - */ - bold = CAIRO_FONT_WEIGHT_BOLD -}; - -/** - * The shape of a line's start and end point. - */ -enum class line_cap : int { - /** - * Start and stop the line exactly where it begins/ends. - */ - butt = CAIRO_LINE_CAP_BUTT, - - /** - * Each end of the line has circles. - */ - round = CAIRO_LINE_CAP_ROUND -}; - -/** - * The dash style of a line. - */ -enum class line_dash : int { - /** - * No dashes in the line (i.e., solid). - */ - none, - - /** - * Dash to whitespace ratio is 5:3. - */ - asymmetric_5_3 -}; - -/** - * Provides functions to draw primitives (e.g., lines, shapes) to a rendering context. - * - * The renderer modifies a cairo_t context based on draw calls. The renderer uses an ezgl::camera object to convert - * world coordinates into cairo's expected coordinate system. - */ -class renderer { -public: - /** - * Change the current coordinate system - * - * @param new_coordinate_system The drawing coordinate system SCREEN or WORLD - */ - void set_coordinate_system(t_coordinate_system new_coordinate_system); - - /** - * Set the visible bounds of the world - * - * The function preserves the aspect ratio of the initial world - * - * @param new_world The new visible bounds of the world - */ - void set_visible_world(rectangle new_world); - - /** - * Get the current visible bounds of the world - */ - rectangle get_visible_world(); - - /** - * Get the current visible bounds of the screen - */ - rectangle get_visible_screen(); - - /** - * Get the screen coordinates (i.e. pixel locations) of the world coordinate rectangle box - * - * @param box: a rectangle in world coordinates - */ - rectangle world_to_screen(const rectangle& box); - - /**** Functions to set graphics attributes (for all subsequent drawing calls). ****/ - - /** - * Change the color for subsequent draw calls. - * - * @param new_color The new color to use. - */ - void set_color(color new_color); - - /** - * Change the color for subsequent draw calls. - * - * @param new_color The new color to use. - * @param alpha Overwrite the alpha channel in the chosen color. - */ - void set_color(color new_color, uint_fast8_t alpha); - - /** - * Change the color for subsequent draw calls. - * - * @param red The amount of red to use, between 0 and 255. - * @param green The amount of green to use, between 0 and 255. - * @param blue The amount of blue to use, between 0 and 255. - * @param alpha The transparency level (0 is fully transparent, 255 is opaque). - */ - void set_color(uint_fast8_t red, uint_fast8_t green, uint_fast8_t blue, uint_fast8_t alpha = 255); - - /** - * Change how line endpoints will be rendered in subsequent draw calls. - */ - void set_line_cap(line_cap cap); - - /** - * Change the dash style of the line. - */ - void set_line_dash(line_dash dash); - - /** - * Set the line width. - * - * @param width The width in pixels. - * A value of 0 is still one pixel wide but about 100x faster - * to draw than other line widths. - */ - void set_line_width(int width); - - /** - * Change the font size. - * - * @param new_size The new size text should be drawn at. - */ - void set_font_size(double new_size); - - /** - * Change the font. - * - * @param family The font family to use (e.g., serif) - * @param slant The slant to use (e.g., italic) - * @param weight The weight of the font (e.g., bold) - */ - void format_font(std::string const &family, font_slant slant, font_weight weight); - - /** - * Change the font. - * - * @param family The font family to use (e.g., serif) - * @param slant The slant to use (e.g., italic) - * @param weight The weight of the font (e.g., bold) - * @param new_size The new size text should be drawn at. - */ - void - format_font(std::string const &family, font_slant slant, font_weight weight, double new_size); - - /** - * set the rotation_angle variable that is used in rotating text. - * - * @param degrees The angle by which the text should rotate, in degrees. - */ - void set_text_rotation(double degrees); - - /** - * set horizontal justification (used for text and surfaces). - * - * @param horiz_just Options: center, left and right justification. - */ - void set_horiz_justification(justification horiz_just); - - /** - * set vertical justification (used for text and surfaces). - * - * @param vert_just Options: center, top and bottom justification. - */ - void set_vert_justification(justification vert_just); - - /**** Functions to draw various graphics primitives ****/ - - /** - * Draw a line. - * - * @param start The start point of the line, in pixels. - * @param end The end point of the line, in pixels. - */ - void draw_line(point2d start, point2d end); - - /** - * Draw the outline a rectangle. - * - * @param start The start point of the rectangle, in pixels. - * @param end The end point of the rectangle, in pixels. - */ - void draw_rectangle(point2d start, point2d end); - - /** - * Draw the outline of a rectangle. - * - * @param start The start point of the rectangle, in pixels. - * @param width How wide the rectangle is, in pixels. - * @param height How high the rectangle is, in pixels. - */ - void draw_rectangle(point2d start, double width, double height); - - /** - * Draw the outline of a rectangle. - */ - void draw_rectangle(rectangle r); - - /** - * Draw a filled in rectangle. - * - * @param start The start point of the rectangle, in pixels. - * @param end The end point of the rectangle, in pixels. - */ - void fill_rectangle(point2d start, point2d end); - - /** - * Draw a filled in rectangle. - * - * @param start The start point of the rectangle, in pixels. - * @param width How wide the rectangle is, in pixels. - * @param height How high the rectangle is, in pixels. - */ - void fill_rectangle(point2d start, double width, double height); - - /** - * Draw a filled in rectangle. - */ - void fill_rectangle(rectangle r); - - /** - * Draw a filled polygon. - * - * @param points The points to draw. The first and last points are connected to close the polygon. - */ - void fill_poly(std::vector const &points); - - /** - * Draw the outline of an elliptic arc. - * - * @param center The center of the arc, in pixels. - * @param radius_x The x radius of the elliptic arc, in pixels. - * @param radius_y The y radius of the elliptic arc, in pixels. - * @param start_angle The starting angle of the arc, in degrees. - * @param extent_angle The extent angle of the arc, in degrees. - */ - void draw_elliptic_arc(point2d center, - double radius_x, - double radius_y, - double start_angle, - double extent_angle); - - /** - * Draw the outline of an arc. - * - * @param center The center of the arc, in pixels. - * @param radius The radius of the arc, in pixels. - * @param start_angle The starting angle of the arc, in degrees. - * @param extent_angle The extent angle of the arc, in degrees. - */ - void draw_arc(point2d center, double radius, double start_angle, double extent_angle); - - /** - * Draw a filled in elliptic arc. - * - * @param center The center of the arc, in pixels. - * @param radius_x The x radius of the elliptic arc, in pixels. - * @param radius_y The y radius of the elliptic arc, in pixels. - * @param start_angle The starting angle of the arc, in degrees. - * @param extent_angle The extent angle of the arc, in degrees. - */ - void fill_elliptic_arc(point2d center, - double radius_x, - double radius_y, - double start_angle, - double extent_angle); - - /** - * Draw a filled in arc. - * - * @param center The center of the arc, in pixels. - * @param radius The radius of the arc, in pixels. - * @param start_angle The starting angle of the arc, in degrees. - * @param extent_angle The extent angle of the arc, in degrees. - */ - void fill_arc(point2d center, double radius, double start_angle, double extent_angle); - - /** - * Draw text. - * - * @param point The point where the text is drawn, in pixels. - * @param text The text to draw. - */ - void draw_text(point2d point, std::string const &text); - - /** - * Draw text with bounds. - * - * @param point The point where the text is drawn, in pixels. - * @param text The text to draw. - * @param bound_x The maximum allowed width of the text - * @param bound_y The maximum allowed height of the text - */ - void draw_text(point2d point, std::string const &text, double bound_x, double bound_y); - - /** - * Draw a surface - * - * @param surface The surface to draw - * @param anchor_point The anchor_point point of the drawn surface. - * @param scale_factor The scaling factor of the drawn surface (optional) - */ - void draw_surface(surface *p_surface, point2d anchor_point, double scale_factor = 1); - - /** - * load a png image - * - * @param file_path The path to the png image. - * - * @return a pointer to the created surface. Should be freed using free_surface() - */ - static surface *load_png(const char *file_path); - - /** - * Free a surface - * - * @param surface The surface to destroy - */ - static void free_surface(surface *surface); - - /** - * Destructor. - */ - ~renderer(); - -protected: - // Only the canvas class can create a renderer. - friend class canvas; - - /** - * A callback for transforming points from one coordinate system to another. - */ - using transform_fn = std::function; - - /** - * Constructor. - * - * @param cairo The cairo graphics state. - * @param transform The function to use to transform points to cairo's coordinate system. - */ - renderer(cairo_t *cairo, transform_fn transform, camera *m_camera, cairo_surface_t *m_surface); - - /** - * Update the renderer when the cairo surface/context changes - * - * @param cairo The new cairo graphics state - * @param m_surface The new cairo surface - */ - void update_renderer(cairo_t *cairo, cairo_surface_t *m_surface); - -private: - void draw_rectangle_path(point2d start, point2d end, bool fill_flag); - - void draw_arc_path(point2d center, - double radius, - double start_angle, - double extent_angle, - double stretch_factor, - bool fill_flag); - - // Pre-clipping function - bool rectangle_off_screen(rectangle rect); - - // Current coordinate system (World is the default) - t_coordinate_system current_coordinate_system = WORLD; - - // A non-owning pointer to a cairo graphics context. - cairo_t *m_cairo; - -#ifdef EZGL_USE_X11 - // The x11 drawable - Drawable x11_drawable; - - // The x11 display - Display *x11_display = nullptr; - - // The x11 context - GC x11_context; - - // Transparency flag, if set, cairo will be used - bool transparency_flag = false; -#endif - - transform_fn m_transform; - - //A non-owning pointer to camera object - camera *m_camera; - - // the rotation angle variable used in rotating text - double rotation_angle; - - // Current horizontal justification (used for text and surfaces) - justification horiz_justification = justification::center; - - // Current vertical justification (used for text and surfaces) - justification vert_justification = justification::center; - - // Current line width - int current_line_width = 1; - - // Current line cap - line_cap current_line_cap = line_cap::butt; - - // Current line dash - line_dash current_line_dash = line_dash::none; - - // Current color - color current_color = {0, 0, 0, 255}; -}; -} - -#endif //EZGL_GRAPHICS_HPP diff --git a/libs/EXTERNAL/libezgl/include/ezgl/point.hpp b/libs/EXTERNAL/libezgl/include/ezgl/point.hpp deleted file mode 100644 index a0d39279f19..00000000000 --- a/libs/EXTERNAL/libezgl/include/ezgl/point.hpp +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#ifndef EZGL_POINT_HPP -#define EZGL_POINT_HPP - -namespace ezgl { - -/** - * Represents a two-dimensional point. - */ -class point2d { -public: - /** - * Default constructor: Create a point at (0, 0). - */ - point2d() : x(0.0), y(0.0) - { - } - - /** - * Create a point at the given x and y position. - */ - point2d(double x_coord, double y_coord) noexcept : x(x_coord), y(y_coord) - { - } - - /** - * Location of the x-coordinate. - */ - double x = 0.0; - - /** - * Location of the y-coordinate. - */ - double y = 0.0; - - /** - * Test for equality. - */ - friend bool operator==(point2d const &lhs, point2d const &rhs) - { - return (lhs.x == rhs.x) && (lhs.y == rhs.y); - } - - /** - * Test for inequality. - */ - friend bool operator!=(point2d const &lhs, point2d const &rhs) - { - return !(lhs == rhs); - } - - /** - * Create a new point that is the sum of two points. - */ - friend point2d operator+(point2d const &lhs, point2d const &rhs) - { - return {lhs.x + rhs.x, lhs.y + rhs.y}; - } - - /** - * Add one point to another point. - */ - friend point2d &operator+=(point2d &lhs, point2d const &rhs) - { - lhs.x += rhs.x; - lhs.y += rhs.y; - - return lhs; - } - - /** - * Create a new point that is the difference of two points. - */ - friend point2d operator-(point2d const &lhs, point2d const &rhs) - { - return {lhs.x - rhs.x, lhs.y - rhs.y}; - } - - /** - * Subtract one point from another point. - */ - friend point2d &operator-=(point2d &lhs, point2d const &rhs) - { - lhs.x -= rhs.x; - lhs.y -= rhs.y; - - return lhs; - } - - /** - * Create a new point that is the product of two points. - */ - friend point2d operator*(point2d const &lhs, point2d const &rhs) - { - return {lhs.x * rhs.x, lhs.y * rhs.y}; - } - - /** - * Multiply one point with another point. - */ - friend point2d &operator*=(point2d &lhs, point2d const &rhs) - { - lhs.x *= rhs.x; - lhs.y *= rhs.y; - - return lhs; - } -}; -} - -#endif //EZGL_POINT_HPP diff --git a/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp b/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp deleted file mode 100644 index a454e7f107c..00000000000 --- a/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#ifndef EZGL_RECTANGLE_HPP -#define EZGL_RECTANGLE_HPP - -#include "ezgl/point.hpp" - -#include - -namespace ezgl { - -/** - * Represents a rectangle as two diagonally opposite points. - */ -class rectangle { -public: - /** - * Default constructor: Create a zero-sized rectangle at {0,0}. - */ - rectangle() noexcept : m_first({0, 0}), m_second({0, 0}) - { - } - - /** - * Create a rectangle from two diagonally opposite points. - */ - rectangle(point2d origin_pt, point2d top_right_pt) : m_first(origin_pt), m_second(top_right_pt) - { - } - - /** - * Create a rectangle with a given width and height. - */ - rectangle(point2d origin_pt, double rec_width, double rec_height) : m_first(origin_pt), m_second(origin_pt) - { - m_second.x += rec_width; - m_second.y += rec_height; - } - - /** - * The minimum x-coordinate. - */ - double left() const - { - return std::min(m_first.x, m_second.x); - } - - /** - * The maximum x-coordinate. - */ - double right() const - { - return std::max(m_first.x, m_second.x); - } - - /** - * The minimum y-coordinate. - */ - double bottom() const - { - return std::min(m_first.y, m_second.y); - } - - /** - * The maximum y-coordinate. - */ - double top() const - { - return std::max(m_first.y, m_second.y); - } - - /** - * The minimum x-coordinate and the minimum y-coordinate. - */ - point2d bottom_left() const - { - return {left(), bottom()}; - } - - /** - * The minimum x-coordinate and the maximum y-coordinate. - */ - point2d top_left() const - { - return {left(), top()}; - } - - /** - * The maximum x-coordinate and the minimum y-coordinate. - */ - point2d bottom_right() const - { - return {right(), bottom()}; - } - - /** - * The maximum x-coordinate and the maximum y-coordinate. - */ - point2d top_right() const - { - return {right(), top()}; - } - - /** - * Test if the x and y values are within the rectangle. - */ - bool contains(double x, double y) const - { - if(x < left() || right() < x || y < bottom() || top() < y) { - return false; - } - - return true; - } - - /** - * Test if the x and y values are within the rectangle. - */ - bool contains(point2d point) const - { - return contains(point.x, point.y); - } - - /** - * The width of the rectangle. - */ - double width() const - { - return right() - left(); - } - - /** - * The height of the rectangle. - */ - double height() const - { - return top() - bottom(); - } - - /** - * - * The area of the rectangle. - */ - double area() const - { - return width() * height(); - } - - /** - * The center of the rectangle in the x plane. - */ - double center_x() const - { - return (right() + left()) * 0.5; - } - - /** - * The center of the rectangle in the y plane. - */ - double center_y() const - { - return (top() + bottom()) * 0.5; - } - - /** - * The center of the recangle. - */ - point2d center() const - { - return {center_x(), center_y()}; - } - - /** - * Test for equality. - */ - bool operator==(const rectangle &rhs) const - { - return m_first == rhs.m_first && m_second == rhs.m_second; - } - - /** - * Test for inequality. - */ - bool operator!=(const rectangle &rhs) const - { - return !(rhs == *this); - } - - /** - * translate the rectangle by positive offsets. - */ - friend rectangle &operator+=(rectangle &lhs, point2d const &rhs) - { - lhs.m_first += rhs; - lhs.m_second += rhs; - - return lhs; - } - - /** - * translate the rectangle by negative offsets. - */ - friend rectangle &operator-=(rectangle &lhs, point2d const &rhs) - { - lhs.m_first -= rhs; - lhs.m_second -= rhs; - - return lhs; - } - - /** - * Create a new rectangle that is translated (negative offsets). - */ - friend rectangle operator-(rectangle &lhs, point2d const &rhs) - { - return rectangle(lhs.m_first - rhs, lhs.m_second - rhs); - } - - /** - * Create a new rectangle that is translated (positive offsets). - */ - friend rectangle operator+(rectangle &lhs, point2d const &rhs) - { - return rectangle(lhs.m_first + rhs, lhs.m_second + rhs); - } - - /** The first point of the rectangle */ - point2d m_first; - - /** The second point of the rectangle */ - point2d m_second; -}; -} - -#endif //EZGL_RECTANGLE_HPP diff --git a/libs/EXTERNAL/libezgl/options.cmake b/libs/EXTERNAL/libezgl/options.cmake deleted file mode 100644 index 59f85dbb102..00000000000 --- a/libs/EXTERNAL/libezgl/options.cmake +++ /dev/null @@ -1,11 +0,0 @@ -option( - EZGL_BUILD_EXAMPLES - "Build the EZGL example executables." - ${IS_ROOT_PROJECT} #Only build examples by default if EZGL is the root cmake project -) - -option( - EZGL_BUILD_DOCS - "Create HTML/PDF documentation (requires Doygen)." - OFF -) diff --git a/libs/EXTERNAL/libezgl/src/application.cpp b/libs/EXTERNAL/libezgl/src/application.cpp deleted file mode 100644 index 27f8e04d1ad..00000000000 --- a/libs/EXTERNAL/libezgl/src/application.cpp +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#include "ezgl/application.hpp" - -// GLib deprecated G_APPLICATION_FLAGS_NONE and replaced it with G_APPLICATION_DEFAULT_FLAGS, -// however, this enum was not introduced until GLib 2.74. These lines of code allow EZGL -// to be backwards compatible with older versions of GLib, while not using the deprecated -// enum. -#if GLIB_CHECK_VERSION(2, 74, 0) -static constexpr GApplicationFlags EZGL_APPLICATION_DEFAULT_FLAGS = G_APPLICATION_DEFAULT_FLAGS; -#else -static constexpr GApplicationFlags EZGL_APPLICATION_DEFAULT_FLAGS = G_APPLICATION_FLAGS_NONE; -#endif - -namespace ezgl { - -// A flag to disable event loop (default is false) -// This allows basic scripted testing even if the GUI is on (return immediately when the event loop is called) -bool disable_event_loop = false; - -void application::startup(GtkApplication *, gpointer user_data) -{ - auto ezgl_app = static_cast(user_data); - g_return_if_fail(ezgl_app != nullptr); - - char const *main_ui_resource = ezgl_app->m_main_ui.c_str(); - - if (!build_ui_from_file) { - // Build the main user interface from the XML resource. - // The XML resource is built from an XML file using the glib-compile-resources tool. - // This adds an extra compilation step, but it embeds the UI description in the executable. - GError *error = nullptr; - if(gtk_builder_add_from_resource(ezgl_app->m_builder, main_ui_resource, &error) == 0) { - g_error("%s.", error->message); - } - } - else { - // Build the main user interface from the XML file. - GError *error = nullptr; - if(gtk_builder_add_from_file(ezgl_app->m_builder, main_ui_resource, &error) == 0) { - g_error("%s.", error->message); - } - } - - for(auto &c_pair : ezgl_app->m_canvases) { - GObject *drawing_area = ezgl_app->get_object(c_pair.second->id()); - c_pair.second->initialize(GTK_WIDGET(drawing_area)); - } - - g_info("application::startup successful."); -} - -void application::activate(GtkApplication *, gpointer user_data) -{ - auto ezgl_app = static_cast(user_data); - g_return_if_fail(ezgl_app != nullptr); - - // The main parent window needs to be explicitly added to our GTK application. - GObject *window = ezgl_app->get_object(ezgl_app->m_window_id.c_str()); - gtk_application_add_window(ezgl_app->m_application, GTK_WINDOW(window)); - - // Setup the default callbacks for the mouse and key events - register_default_events_callbacks(ezgl_app); - - if(ezgl_app->m_register_callbacks != nullptr) { - ezgl_app->m_register_callbacks(ezgl_app); - } else { - // Setup the default callbacks for the prebuilt buttons - register_default_buttons_callbacks(ezgl_app); - } - - if(ezgl_app->initial_setup_callback != nullptr) - ezgl_app->initial_setup_callback(ezgl_app, true); - - g_info("application::activate successful."); -} - -application::application(application::settings s) - : m_main_ui(s.main_ui_resource) - , m_window_id(s.window_identifier) - , m_canvas_id(s.canvas_identifier) - , m_application_id(s.application_identifier) - , m_application(gtk_application_new(s.application_identifier.c_str(), EZGL_APPLICATION_DEFAULT_FLAGS)) - , m_builder(gtk_builder_new()) - , m_register_callbacks(s.setup_callbacks) -{ -#ifdef EZGL_USE_X11 - // Prefer x11 first, then other backends. - gdk_set_allowed_backends("x11,*"); -#endif - - // Connect our static functions application::{startup, activate} to their callbacks. We pass 'this' as the userdata - // so that we can use it in our static functions. - g_signal_connect(m_application, "startup", G_CALLBACK(startup), this); - g_signal_connect(m_application, "activate", G_CALLBACK(activate), this); - - first_run = true; - resume_run = false; -} - -application::~application() -{ - // GTK uses reference counting to track object lifetime. Since we called *_new() for our application and builder, we - // need to unreference them. This should set their reference count to 0, letting GTK know that they should be cleaned - // up in memory. - g_object_unref(m_builder); - g_object_unref(m_application); -} - -canvas *application::get_canvas(const std::string &canvas_id) const -{ - auto it = m_canvases.find(canvas_id); - if(it != m_canvases.end()) { - return it->second.get(); - } - - g_warning("Could not find canvas with name %s.", canvas_id.c_str()); - return nullptr; -} - -canvas *application::add_canvas(std::string const &canvas_id, - draw_canvas_fn draw_callback, - rectangle coordinate_system, - color background_color) -{ - if(draw_callback == nullptr) { - // A NULL draw callback means the canvas will never render anything to the screen. - g_warning("Canvas %s's draw callback is NULL.", canvas_id.c_str()); - } - - // Can't use make_unique with protected constructor without fancy code that will confuse students, so we use new - // instead. - std::unique_ptr canvas_ptr(new canvas(canvas_id, draw_callback, coordinate_system, background_color)); - auto it = m_canvases.emplace(canvas_id, std::move(canvas_ptr)); - - if(!it.second) { - // std::map's emplace does not insert the value when the key is already present. - g_warning("Duplicate key (%s) ignored in application::add_canvas.", canvas_id.c_str()); - } else { - g_info("The %s canvas has been added to the application.", canvas_id.c_str()); - } - - return it.first->second.get(); -} - -GObject *application::get_object(gchar const *name) const -{ - // Getting an object from the GTK builder does not increase its reference count. - GObject *object = gtk_builder_get_object(m_builder, name); - g_return_val_if_fail(object != nullptr, nullptr); - - return object; -} - -int application::run(setup_callback_fn initial_setup_user_callback, - mouse_callback_fn mouse_press_user_callback, - mouse_callback_fn mouse_move_user_callback, - key_callback_fn key_press_user_callback) -{ - if(disable_event_loop) - return 0; - - initial_setup_callback = initial_setup_user_callback; - mouse_press_callback = mouse_press_user_callback; - mouse_move_callback = mouse_move_user_callback; - key_press_callback = key_press_user_callback; - - if(first_run) { - // set the first_run flag to false - first_run = false; - - g_info("The event loop is now starting."); - - // see: https://developer.gnome.org/gio/stable/GApplication.html#g-application-run - return g_application_run(G_APPLICATION(m_application), 0, 0); - } - // The result of calling g_application_run() again after it returns is unspecified. - // So in the subsequent runs instead of calling g_application_run(), we will go back to the event loop using gtk_main() - else if(!first_run && gtk_application_get_active_window(m_application) != nullptr) { - - // Call user's initial setup call - if(initial_setup_callback != nullptr) - initial_setup_callback(this, false); - - // set the resume_run flag to true - resume_run = true; - - g_info("The event loop is now resuming."); - - // see: https://developer.gnome.org/gtk3/stable/gtk3-General.html#gtk-main - gtk_main(); - - return 0; - } - // But if the GTK window is closed, we will have to destruct and reconstruct the GTKApplication - else { - // Destroy the GTK application - g_object_unref(m_application); - g_object_unref(m_builder); - - // Reconstruct the GTK application - m_application = (gtk_application_new(m_application_id.c_str(), EZGL_APPLICATION_DEFAULT_FLAGS)); - m_builder = (gtk_builder_new()); - g_signal_connect(m_application, "startup", G_CALLBACK(startup), this); - g_signal_connect(m_application, "activate", G_CALLBACK(activate), this); - - // set the resume_run flag to false - resume_run = false; - - g_info("The event loop is now restarting."); - - // see: https://developer.gnome.org/gio/stable/GApplication.html#g-application-run - return g_application_run(G_APPLICATION(m_application), 0, 0); - } -} - -void application::quit() -{ - if(resume_run) { - // Quit the event loop (exit gtk_main()) - gtk_main_quit(); - } else { - // Quit the GTK application (exit g_application_run()) - g_application_quit(G_APPLICATION(m_application)); - } -} - -void application::register_default_events_callbacks(ezgl::application *application) -{ - // Get a pointer to the main window GUI object by using its name. - std::string main_window_id = application->get_main_window_id(); - GObject *window = application->get_object(main_window_id.c_str()); - - // Get a pointer to the main canvas GUI object by using its name. - std::string main_canvas_id = application->get_main_canvas_id(); - GObject *main_canvas = application->get_object(main_canvas_id.c_str()); - - // Connect press_key function to keyboard presses in the MainWindow. - g_signal_connect(window, "key_press_event", G_CALLBACK(press_key), application); - - // Connect press_mouse function to mouse presses and releases in the MainWindow. - g_signal_connect(main_canvas, "button_press_event", G_CALLBACK(press_mouse), application); - - // Connect release_mouse function to mouse presses and releases in the MainWindow. - g_signal_connect(main_canvas, "button_release_event", G_CALLBACK(release_mouse), application); - - // Connect release_mouse function to mouse presses and releases in the MainWindow. - g_signal_connect(main_canvas, "motion_notify_event", G_CALLBACK(move_mouse), application); - - // Connect scroll_mouse function to the mouse scroll event (up, down, left and right) - g_signal_connect(main_canvas, "scroll_event", G_CALLBACK(scroll_mouse), application); - - // Connect press_proceed function to the close button of the MainWindow - g_signal_connect(window, "destroy", G_CALLBACK(press_proceed), application); -} - -void application::register_default_buttons_callbacks(ezgl::application *application) -{ - // Connect press_zoom_fit function to the Zoom-fit button - GObject *zoom_fit_button = application->get_object("ZoomFitButton"); - g_signal_connect(zoom_fit_button, "clicked", G_CALLBACK(press_zoom_fit), application); - - // Connect press_zoom_in function to the Zoom-in button - GObject *zoom_in_button = application->get_object("ZoomInButton"); - g_signal_connect(zoom_in_button, "clicked", G_CALLBACK(press_zoom_in), application); - - // Connect press_zoom_out function to the Zoom-out button - GObject *zoom_out_button = application->get_object("ZoomOutButton"); - g_signal_connect(zoom_out_button, "clicked", G_CALLBACK(press_zoom_out), application); - - // Connect press_up function to the Up button - GObject *shift_up_button = application->get_object("UpButton"); - g_signal_connect(shift_up_button, "clicked", G_CALLBACK(press_up), application); - - // Connect press_down function to the Down button - GObject *shift_down_button = application->get_object("DownButton"); - g_signal_connect(shift_down_button, "clicked", G_CALLBACK(press_down), application); - - // Connect press_left function to the Left button - GObject *shift_left_button = application->get_object("LeftButton"); - g_signal_connect(shift_left_button, "clicked", G_CALLBACK(press_left), application); - - // Connect press_right function to the Right button - GObject *shift_right_button = application->get_object("RightButton"); - g_signal_connect(shift_right_button, "clicked", G_CALLBACK(press_right), application); - - // Connect press_proceed function to the Proceed button - GObject *proceed_button = application->get_object("ProceedButton"); - g_signal_connect(proceed_button, "clicked", G_CALLBACK(press_proceed), application); -} - -void application::update_message(std::string const &message) -{ - // Get the StatusBar Object - GtkStatusbar *status_bar = (GtkStatusbar *)get_object("StatusBar"); - - // Remove all previous messages from the message stack - gtk_statusbar_remove_all(status_bar, 0); - - // Push user message to the message stack - gtk_statusbar_push(status_bar, 0, message.c_str()); -} - -void application::create_button(const char *button_text, - int left, - int top, - int width, - int height, - button_callback_fn button_func) -{ - // get the internal Gtk grid - GtkGrid *in_grid = (GtkGrid *)get_object("InnerGrid"); - - // create the new button with the given label - GtkWidget *new_button = gtk_button_new_with_label(button_text); - - // set can_focus property to false -#if GTK_CHECK_VERSION (3, 20, 0) - gtk_widget_set_focus_on_click(new_button, false); -#endif - - // connect the buttons clicked event to the callback - if(button_func != NULL) { - g_signal_connect(G_OBJECT(new_button), "clicked", G_CALLBACK(button_func), this); - } - - // add the new button - gtk_grid_attach(in_grid, new_button, left, top, width, height); - - // show the button - gtk_widget_show(new_button); -} - -void application::create_button(const char *button_text, - int insert_row, - button_callback_fn button_func) -{ - // get the internal Gtk grid - GtkGrid *in_grid = (GtkGrid *)get_object("InnerGrid"); - - // add a row where we want to insert - gtk_grid_insert_row(in_grid, insert_row); - - // create the button - create_button(button_text, 0, insert_row, 3, 1, button_func); -} - -bool application::destroy_button(const char *button_text_to_destroy) -{ - // get the inner grid - GtkGrid *in_grid = (GtkGrid *)get_object("InnerGrid"); - - // the text to delete, in c++ string form - std::string text_to_del = std::string(button_text_to_destroy); - - // iterate over all of the children in the grid and find the button by it's text - GList *children, *iter; - children = gtk_container_get_children(GTK_CONTAINER(in_grid)); - for(iter = children; iter != NULL; iter = g_list_next(iter)) { - // iterator to widget - GtkWidget *widget = GTK_WIDGET(iter->data); - - // check if widget is a button - if(GTK_IS_BUTTON(widget)) { - // convert to button - GtkButton *button = GTK_BUTTON(widget); - - // get the button label - const char *button_label = gtk_button_get_label(button); - if(button_label != nullptr) { - std::string button_text = std::string(button_label); - - // does the label of the button match the one we want to delete? - if(button_text == text_to_del) { - // destroy the button (widget) and return true - gtk_widget_destroy(widget); - // free the children list - g_list_free (children); - return true; - } - } - } - } - - // free the children list - g_list_free (children); - // couldn't find the button with the label 'button_text_to_destroy' - return false; -} - -void application::change_button_text(const char *button_text, const char *new_button_text) -{ - // get the inner grid - GtkGrid *in_grid = (GtkGrid *)get_object("InnerGrid"); - - // the text to change, in c++ string form - std::string text_to_change = std::string(button_text); - - // iterate over all of the children in the grid and find the button by it's text - GList *children, *iter; - children = gtk_container_get_children(GTK_CONTAINER(in_grid)); - for(iter = children; iter != NULL; iter = g_list_next(iter)) { - // iterator to widget - GtkWidget *widget = GTK_WIDGET(iter->data); - - // check if widget is a button - if(GTK_IS_BUTTON(widget)) { - // convert to button - GtkButton *button = GTK_BUTTON(widget); - - // get the button label - const char *button_label = gtk_button_get_label(button); - if(button_label != nullptr) { - std::string button_text_str = std::string(button_label); - - // does the label of the button match the one we want to change? - if(button_text_str == text_to_change) { - // change button label - gtk_button_set_label(button, new_button_text); - } - } - } - } - - // free the children list - g_list_free (children); -} - -void application::change_canvas_world_coordinates(std::string const &canvas_id, - rectangle coordinate_system) -{ - // get the canvas - canvas *cnv = get_canvas(canvas_id); - - // reset the camera system with the new coordinates - if (cnv != nullptr) { - cnv->get_camera().reset_world(coordinate_system); - } -} - -void application::refresh_drawing() -{ - // get the main canvas - canvas *cnv = get_canvas(m_canvas_id); - - // force redrawing - cnv->redraw(); -} - -void application::flush_drawing() -{ - // get the main drawing area widget - GtkWidget *drawing_area = (GtkWidget *)get_object(m_canvas_id.c_str()); - - // queue a redraw of the GtkWidget - gtk_widget_queue_draw(drawing_area); - - // run the main loop on pending events - while(gtk_events_pending()) - gtk_main_iteration(); -} - -renderer *application::get_renderer() -{ - // get the main canvas - canvas *cnv = get_canvas(m_canvas_id); - - return cnv->create_animation_renderer(); -} - -void set_disable_event_loop(bool new_setting) -{ - disable_event_loop = new_setting; -} -} diff --git a/libs/EXTERNAL/libezgl/src/callback.cpp b/libs/EXTERNAL/libezgl/src/callback.cpp deleted file mode 100644 index 33e2ff1d7d9..00000000000 --- a/libs/EXTERNAL/libezgl/src/callback.cpp +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright 2019-2022 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia, Tanner Young-Schultz and Vaughn Betz - */ - -#include "ezgl/callback.hpp" - -namespace ezgl { - -/** - * Provides file wide variables to support mouse panning. We store some - * state about mouse panning so we can determine when click & drag mouse - * panning (handled by ezgl) is happening vs. simple mouse clicks (sent to - * user mouse click callback). - */ -struct mouse_pan { - /** - * Tracks whether the mouse button used for panning is currently pressed - */ - bool panning_mouse_button_pressed = false; - /** - * Holds the timestamp of the last panning event - */ - int last_panning_event_time = 0; - /** - * The old x and y positions of the mouse pointer, in the previous pan - * event. - */ - double prev_x = 0; - double prev_y = 0; - - /* Has any panning happened since the mouse button was held down? - */ - bool has_panned = false; -} g_mouse_pan; - -gboolean press_key(GtkWidget *, GdkEventKey *event, gpointer data) -{ - auto application = static_cast(data); - - // Call the user-defined key press callback if defined - if(application->key_press_callback != nullptr) { - // see: https://developer.gnome.org/gdk3/stable/gdk3-Keyboard-Handling.html - application->key_press_callback(application, event, gdk_keyval_name(event->keyval)); - } - - // Returning FALSE to indicate this event should be propagated on to other - // gtk widgets. This is important since we're grabbing keyboard events - // for the whole main window. It can have unexpected effects though, such - // as Enter/Space being treated as press any highlighted button. - // return TRUE (event consumed) if you want to avoid that, and don't have - // any widgets that need keyboard events. - return FALSE; -} - -gboolean press_mouse(GtkWidget *, GdkEventButton *event, gpointer data) -{ - auto application = static_cast(data); - - if(event->type == GDK_BUTTON_PRESS) { - - // Check for mouse press to support dragging. - if(event->button == PANNING_MOUSE_BUTTON) { - g_mouse_pan.panning_mouse_button_pressed = true; - g_mouse_pan.prev_x = event->x; - g_mouse_pan.prev_y = event->y; - g_mouse_pan.has_panned = false; /* Haven't shifted the view yet */ - } - // Call the user-defined mouse press callback if defined - // The user-defined callback is called for mouse buttons other than - // the PANNING_MOUSE_BUTTON button. If the user pressed the PANNING_MOUSE_BUTTON button, - // the callback will be called at mouse release only if no panning occurs - else if(application->mouse_press_callback != nullptr) { - ezgl::point2d const widget_coordinates(event->x, event->y); - - std::string main_canvas_id = application->get_main_canvas_id(); - ezgl::canvas *canvas = application->get_canvas(main_canvas_id); - - ezgl::point2d const world = canvas->get_camera().widget_to_world(widget_coordinates); - application->mouse_press_callback(application, event, world.x, world.y); - } - } - - return TRUE; // consume the event -} - -gboolean release_mouse(GtkWidget *, GdkEventButton *event, gpointer data) -{ - auto application = static_cast(data); - - if(event->type == GDK_BUTTON_RELEASE) { - // Check for mouse release to support dragging - if(event->button == PANNING_MOUSE_BUTTON) { - g_mouse_pan.panning_mouse_button_pressed = false; - - // Call the user-defined mouse press callback for the PANNING_MOUSE_BUTTON button only if no panning occurs. - // This lets the user use one mouse button for both click-and-drag - // panning and simple clicking. - if (!g_mouse_pan.has_panned && application->mouse_press_callback != nullptr) { - ezgl::point2d const widget_coordinates(event->x, event->y); - - std::string main_canvas_id = application->get_main_canvas_id(); - ezgl::canvas *canvas = application->get_canvas(main_canvas_id); - - ezgl::point2d const world = canvas->get_camera().widget_to_world(widget_coordinates); - application->mouse_press_callback(application, event, world.x, world.y); - } - g_mouse_pan.has_panned = false; /* Done pan; reset for next time */ - } - } - - return TRUE; // consume the event -} - -gboolean move_mouse(GtkWidget *, GdkEventButton *event, gpointer data) -{ - auto application = static_cast(data); - - if(event->type == GDK_MOTION_NOTIFY) { - - // Check if the mouse button is pressed to support dragging - if(g_mouse_pan.panning_mouse_button_pressed) { - // Code below drops a panning event if we served anothe one - // less than 100 ms. I believe it was intended to avoid having panning - // fall behind and queue up many events if redraws were slow. However, - // it is not necessary on the UG machines (debian) in person, or over - // VNC or on a VM and it has the bad effect of limiting refresh to 10 Hz. - // Commenting it out for now and will delete if there - // are no reported issues. - VB - // if(gtk_get_current_event_time() - g_mouse_pan.last_panning_event_time < 100) - // return true; - - g_mouse_pan.last_panning_event_time = gtk_get_current_event_time(); - - GdkEventMotion *motion_event = (GdkEventMotion *)event; - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - point2d curr_trans = canvas->get_camera().widget_to_world({motion_event->x, motion_event->y}); - point2d prev_trans = canvas->get_camera().widget_to_world({g_mouse_pan.prev_x, g_mouse_pan.prev_y}); - - double dx = curr_trans.x - prev_trans.x; - double dy = curr_trans.y - prev_trans.y; - - g_mouse_pan.prev_x = motion_event->x; - g_mouse_pan.prev_y = motion_event->y; - - // Flip the delta x to avoid inverted dragging - translate(canvas, -dx, -dy); - g_mouse_pan.has_panned = true; - } - // Else call the user-defined mouse move callback if defined - else if(application->mouse_move_callback != nullptr) { - ezgl::point2d const widget_coordinates(event->x, event->y); - - std::string main_canvas_id = application->get_main_canvas_id(); - ezgl::canvas *canvas = application->get_canvas(main_canvas_id); - - ezgl::point2d const world = canvas->get_camera().widget_to_world(widget_coordinates); - application->mouse_move_callback(application, event, world.x, world.y); - } - } - - return TRUE; // consume the event -} - -gboolean scroll_mouse(GtkWidget *, GdkEvent *event, gpointer data) -{ - - if(event->type == GDK_SCROLL) { - auto application = static_cast(data); - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - GdkEventScroll *scroll_event = (GdkEventScroll *)event; - - ezgl::point2d scroll_point(scroll_event->x, scroll_event->y); - - if(scroll_event->direction == GDK_SCROLL_UP) { - // Zoom in at the scroll point - ezgl::zoom_in(canvas, scroll_point, 5.0 / 3.0); - } else if(scroll_event->direction == GDK_SCROLL_DOWN) { - // Zoom out at the scroll point - ezgl::zoom_out(canvas, scroll_point, 5.0 / 3.0); - } else if(scroll_event->direction == GDK_SCROLL_SMOOTH) { - // Doesn't seem to be happening - } // NOTE: We ignore scroll GDK_SCROLL_LEFT and GDK_SCROLL_RIGHT - } - return TRUE; -} - -gboolean press_zoom_fit(GtkWidget *, gpointer data) -{ - - auto application = static_cast(data); - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - ezgl::zoom_fit(canvas, canvas->get_camera().get_initial_world()); - - return TRUE; -} - -gboolean press_zoom_in(GtkWidget *, gpointer data) -{ - - auto application = static_cast(data); - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - ezgl::zoom_in(canvas, 5.0 / 3.0); - - return TRUE; -} - -gboolean press_zoom_out(GtkWidget *, gpointer data) -{ - - auto application = static_cast(data); - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - ezgl::zoom_out(canvas, 5.0 / 3.0); - - return TRUE; -} - -gboolean press_up(GtkWidget *, gpointer data) -{ - - auto application = static_cast(data); - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - ezgl::translate_up(canvas, 5.0); - - return TRUE; -} - -gboolean press_down(GtkWidget *, gpointer data) -{ - - auto application = static_cast(data); - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - ezgl::translate_down(canvas, 5.0); - - return TRUE; -} - -gboolean press_left(GtkWidget *, gpointer data) -{ - - auto application = static_cast(data); - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - ezgl::translate_left(canvas, 5.0); - - return TRUE; -} - -gboolean press_right(GtkWidget *, gpointer data) -{ - - auto application = static_cast(data); - - std::string main_canvas_id = application->get_main_canvas_id(); - auto canvas = application->get_canvas(main_canvas_id); - - ezgl::translate_right(canvas, 5.0); - - return TRUE; -} - -gboolean press_proceed(GtkWidget *, gpointer data) -{ - auto ezgl_app = static_cast(data); - ezgl_app->quit(); - - return TRUE; -} -} \ No newline at end of file diff --git a/libs/EXTERNAL/libezgl/src/camera.cpp b/libs/EXTERNAL/libezgl/src/camera.cpp deleted file mode 100644 index 17afc4ea61e..00000000000 --- a/libs/EXTERNAL/libezgl/src/camera.cpp +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#include "ezgl/camera.hpp" - -#include -#include - -namespace ezgl { - -static rectangle maintain_aspect_ratio(rectangle const &view, double widget_width, double widget_height) -{ - double const x_scale = widget_width / view.width(); - double const y_scale = widget_height / view.height(); - - double x_start = 0.0; - double y_start = 0.0; - double new_width; - double new_height; - - if(x_scale * view.height() > widget_height) { - // Using x_scale causes the view to be larger than the widget's height. - - // Keep the same height as the widget. - new_height = widget_height; - // Scale the width to maintain the aspect ratio. - new_width = view.width() * y_scale; - // Keep the view in the center of the widget. - x_start = 0.5 * std::fabs(widget_width - new_width); - } else { - // Using x_scale keeps the view within the widget's height. - - // Keep the width the same as the widget. - new_width = widget_width; - // Scale the height to maintain the aspect ratio. - new_height = view.height() * x_scale; - // Keep the view in the center of the widget. - y_start = 0.5 * std::fabs(widget_height - new_height); - } - - return {{x_start, y_start}, new_width, new_height}; -} - -camera::camera(rectangle bounds) : m_world(bounds), m_screen(bounds), m_initial_world(bounds) -{ -} - -point2d camera::widget_to_screen(point2d widget_coordinates) const -{ - point2d const screen_origin = {m_screen.left(), m_screen.bottom()}; - point2d screen_coordinates = widget_coordinates - screen_origin; - - return screen_coordinates; -} - -point2d camera::widget_to_world(point2d widget_coordinates) const -{ - point2d const screen_coordinates = widget_to_screen(widget_coordinates); - - point2d world_coordinates = screen_coordinates * m_screen_to_world; - - world_coordinates.x += m_world.left(); - - // GTK and cairo use a flipped y-axis. - world_coordinates.y = (world_coordinates.y - m_world.top()) * -1.0; - - return world_coordinates; -} - -/** - * Some X11 implementations overflow with sufficiently large pixel - * coordinates and start drawing strangely. We will clip all pixels - * to lie in the range below. - * TODO: We can also switch to cairo for large pixel coordinates - */ -#define MAXPIXEL 10000.0 -#define MINPIXEL -10000.0 - -point2d camera::world_to_screen(point2d world_coordinates) const -{ - point2d const world_origin{m_world.left(), m_world.bottom()}; - point2d widget_coordinates = (world_coordinates - world_origin) * m_world_to_widget; - - // GTK and cairo use a flipped y-axis. - widget_coordinates.y = (widget_coordinates.y - m_widget.top()) * -1.0; - - point2d screen_coordinates = widget_coordinates * m_widget_to_screen; - - point2d const screen_origin = {m_screen.left(), m_screen.bottom()}; - screen_coordinates = screen_coordinates + screen_origin; - - screen_coordinates.x = std::max(screen_coordinates.x, MINPIXEL); - screen_coordinates.y = std::max(screen_coordinates.y, MINPIXEL); - screen_coordinates.x = std::min(screen_coordinates.x, MAXPIXEL); - screen_coordinates.y = std::min(screen_coordinates.y, MAXPIXEL); - - return screen_coordinates; -} - -void camera::set_world(rectangle new_world) -{ - m_world = new_world; - - update_scale_factors(); -} - -void camera::reset_world(rectangle new_world) -{ - // Change the coordinates to the new bounds - m_world = new_world; - m_screen = new_world; - m_initial_world = new_world; - - m_screen = maintain_aspect_ratio(m_screen, m_widget.width(), m_widget.height()); - update_scale_factors(); -} - -void camera::update_widget(int width, int height) -{ - m_widget = rectangle{{0, 0}, static_cast(width), static_cast(height)}; - - m_screen = maintain_aspect_ratio(m_screen, m_widget.width(), m_widget.height()); - update_scale_factors(); -} - -void camera::update_scale_factors() -{ - m_widget_to_screen.x = m_screen.width() / m_widget.width(); - m_widget_to_screen.y = m_screen.height() / m_widget.height(); - - m_world_to_widget.x = m_widget.width() / m_world.width(); - m_world_to_widget.y = m_widget.height() / m_world.height(); - - m_screen_to_world.x = m_world.width() / m_screen.width(); - m_screen_to_world.y = m_world.height() / m_screen.height(); -} -} diff --git a/libs/EXTERNAL/libezgl/src/canvas.cpp b/libs/EXTERNAL/libezgl/src/canvas.cpp deleted file mode 100644 index 75452a3225f..00000000000 --- a/libs/EXTERNAL/libezgl/src/canvas.cpp +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#include "ezgl/canvas.hpp" - -#include "ezgl/graphics.hpp" - -#include - -#include -#include -#include - -namespace ezgl { - -static cairo_surface_t *create_surface(GtkWidget *widget) -{ - GdkWindow *parent_window = gtk_widget_get_window(widget); - int const width = gtk_widget_get_allocated_width(widget); - int const height = gtk_widget_get_allocated_height(widget); - - // Cairo image surfaces are more efficient than normal Cairo surfaces - // However, you cannot use X11 functions to draw on image surfaces -#ifdef EZGL_USE_X11 - cairo_surface_t *p_surface = gdk_window_create_similar_surface( - parent_window, CAIRO_CONTENT_COLOR_ALPHA, width, height); -#else - cairo_surface_t *p_surface = gdk_window_create_similar_image_surface( - parent_window, CAIRO_FORMAT_ARGB32, width, height, 0); -#endif - - // On HiDPI displays, Cairos surfaces are scaled to 2x or more - // However, EZGL doesn't support scaling yet - // Force the scaling factor to 1 for both x and y - cairo_surface_set_device_scale(p_surface, 1, 1); - - return p_surface; -} - -static cairo_t *create_context(cairo_surface_t *p_surface) -{ - cairo_t *context = cairo_create(p_surface); - - // Set the antialiasing mode of the rasterizer used for drawing shapes - // Set to CAIRO_ANTIALIAS_NONE for maximum speed - // See https://www.cairographics.org/manual/cairo-cairo-t.html#cairo-antialias-t - cairo_set_antialias(context, CAIRO_ANTIALIAS_NONE); - - return context; -} - -bool canvas::print_pdf(const char *file_name, int output_width, int output_height) -{ - cairo_surface_t *pdf_surface; - cairo_t *context; - int surface_width = 0; - int surface_height = 0; - - // create pdf surface based on canvas size - if(output_width == 0 && output_height == 0){ - surface_width = gtk_widget_get_allocated_width(m_drawing_area); - surface_height = gtk_widget_get_allocated_height(m_drawing_area); - }else{ - surface_width = output_width; - surface_height = output_height; - } - pdf_surface = cairo_pdf_surface_create(file_name, surface_width, surface_height); - - if(pdf_surface == NULL) - return false; // failed to create due to errors such as out of memory - context = create_context(pdf_surface); - - // draw on the newly created pdf surface & context - cairo_set_source_rgb(context, m_background_color.red / 255.0, m_background_color.green / 255.0, - m_background_color.blue / 255.0); - cairo_paint(context); - - using namespace std::placeholders; - camera pdf_cam = m_camera; - pdf_cam.update_widget(surface_width, surface_height); - renderer g(context, std::bind(&camera::world_to_screen, pdf_cam, _1), &pdf_cam, pdf_surface); - m_draw_callback(&g); - - // free surface & context - cairo_surface_destroy(pdf_surface); - cairo_destroy(context); - - return true; -} - -bool canvas::print_svg(const char *file_name, int output_width, int output_height) -{ - cairo_surface_t *svg_surface; - cairo_t *context; - int surface_width = 0; - int surface_height = 0; - - // create pdf surface based on canvas size - if(output_width == 0 && output_height == 0){ - surface_width = gtk_widget_get_allocated_width(m_drawing_area); - surface_height = gtk_widget_get_allocated_height(m_drawing_area); - }else{ - surface_width = output_width; - surface_height = output_height; - } - svg_surface = cairo_svg_surface_create(file_name, surface_width, surface_height); - - if(svg_surface == NULL) - return false; // failed to create due to errors such as out of memory - context = create_context(svg_surface); - - // draw on the newly created svg surface & context - cairo_set_source_rgb(context, m_background_color.red / 255.0, m_background_color.green / 255.0, - m_background_color.blue / 255.0); - cairo_paint(context); - - using namespace std::placeholders; - camera svg_cam = m_camera; - svg_cam.update_widget(surface_width, surface_height); - renderer g(context, std::bind(&camera::world_to_screen, svg_cam, _1), &svg_cam, svg_surface); - m_draw_callback(&g); - - // free surface & context - cairo_surface_destroy(svg_surface); - cairo_destroy(context); - - return true; -} - -bool canvas::print_png(const char *file_name, int output_width, int output_height) -{ - cairo_surface_t *png_surface; - cairo_t *context; - int surface_width = 0; - int surface_height = 0; - - // create pdf surface based on canvas size - if(output_width == 0 && output_height == 0){ - surface_width = gtk_widget_get_allocated_width(m_drawing_area); - surface_height = gtk_widget_get_allocated_height(m_drawing_area); - }else{ - surface_width = output_width; - surface_height = output_height; - } - png_surface = cairo_image_surface_create(CAIRO_FORMAT_ARGB32, surface_width, surface_height); - - if(png_surface == NULL) - return false; // failed to create due to errors such as out of memory - context = create_context(png_surface); - - // draw on the newly created png surface & context - cairo_set_source_rgb(context, m_background_color.red / 255.0, m_background_color.green / 255.0, - m_background_color.blue / 255.0); - cairo_paint(context); - - using namespace std::placeholders; - camera png_cam = m_camera; - png_cam.update_widget(surface_width, surface_height); - renderer g(context, std::bind(&camera::world_to_screen, png_cam, _1), &png_cam, png_surface); - m_draw_callback(&g); - - // create png output file - cairo_surface_write_to_png(png_surface, file_name); - - // free surface & context - cairo_surface_destroy(png_surface); - cairo_destroy(context); - - return true; -} - -gboolean canvas::configure_event(GtkWidget *widget, GdkEventConfigure *, gpointer data) -{ - // User data should have been set during the signal connection. - g_return_val_if_fail(data != nullptr, FALSE); - - auto ezgl_canvas = static_cast(data); - auto &p_surface = ezgl_canvas->m_surface; - auto &p_context = ezgl_canvas->m_context; - - if(p_surface != nullptr) { - cairo_surface_destroy(p_surface); - } - - if(p_context != nullptr) { - cairo_destroy(p_context); - } - - // Something has changed, recreate the surface. - p_surface = create_surface(widget); - - // Recreate the context - p_context = create_context(p_surface); - - // The camera needs to be updated before we start drawing again. - ezgl_canvas->m_camera.update_widget(ezgl_canvas->width(), ezgl_canvas->height()); - - // Draw to the newly created surface. - ezgl_canvas->redraw(); - - // Update the animation renderer - if(ezgl_canvas->m_animation_renderer != nullptr) - ezgl_canvas->m_animation_renderer->update_renderer(p_context, p_surface); - - g_info("canvas::configure_event has been handled."); - return TRUE; // the configure event was handled -} - -gboolean canvas::draw_surface(GtkWidget *, cairo_t *context, gpointer data) -{ - // Assume context and data are non-null. - auto &p_surface = static_cast(data)->m_surface; - - // Assume surface is non-null. - cairo_set_source_surface(context, p_surface, 0, 0); - cairo_paint(context); - - return FALSE; -} - -canvas::canvas(std::string canvas_id, - draw_canvas_fn draw_callback, - rectangle coordinate_system, - color background_color) - : m_canvas_id(std::move(canvas_id)) - , m_draw_callback(draw_callback) - , m_camera(coordinate_system) - , m_background_color(background_color) -{ -} - -canvas::~canvas() -{ - if(m_surface != nullptr) { - cairo_surface_destroy(m_surface); - } - - if(m_context != nullptr) { - cairo_destroy(m_context); - } - - if(m_animation_renderer != nullptr) { - delete m_animation_renderer; - } -} - -int canvas::width() const -{ - return gtk_widget_get_allocated_width(m_drawing_area); -} - -int canvas::height() const -{ - return gtk_widget_get_allocated_height(m_drawing_area); -} - -void canvas::initialize(GtkWidget *drawing_area) -{ - g_return_if_fail(drawing_area != nullptr); - - m_drawing_area = drawing_area; - m_surface = create_surface(m_drawing_area); - m_context = create_context(m_surface); - m_camera.update_widget(width(), height()); - - // Draw to the newly created surface for the first time. - redraw(); - - // Connect to configure events in case our widget changes shape. - g_signal_connect(m_drawing_area, "configure-event", G_CALLBACK(configure_event), this); - // Connect to draw events so that we draw our surface to the drawing area. - g_signal_connect(m_drawing_area, "draw", G_CALLBACK(draw_surface), this); - - // GtkDrawingArea objects need specific events enabled explicitly. - gtk_widget_add_events(GTK_WIDGET(m_drawing_area), GDK_BUTTON_PRESS_MASK); - gtk_widget_add_events(GTK_WIDGET(m_drawing_area), GDK_BUTTON_RELEASE_MASK); - gtk_widget_add_events(GTK_WIDGET(m_drawing_area), GDK_POINTER_MOTION_MASK); - gtk_widget_add_events(GTK_WIDGET(m_drawing_area), GDK_SCROLL_MASK); - - g_info("canvas::initialize successful."); -} - -void canvas::redraw() -{ - // Clear the screen and set the background color - cairo_set_source_rgb(m_context, m_background_color.red / 255.0, m_background_color.green / 255.0, - m_background_color.blue / 255.0); - cairo_paint(m_context); - - using namespace std::placeholders; - renderer g(m_context, std::bind(&camera::world_to_screen, &m_camera, _1), &m_camera, m_surface); - m_draw_callback(&g); - - gtk_widget_queue_draw(m_drawing_area); - - g_info("The canvas will be redrawn."); -} - -renderer *canvas::create_animation_renderer() -{ - if(m_animation_renderer == nullptr) { - using namespace std::placeholders; - m_animation_renderer = new renderer(m_context, std::bind(&camera::world_to_screen, &m_camera, _1), &m_camera, m_surface); - } - - return m_animation_renderer; -} -} // namespace ezgl diff --git a/libs/EXTERNAL/libezgl/src/control.cpp b/libs/EXTERNAL/libezgl/src/control.cpp deleted file mode 100644 index 43ef651e968..00000000000 --- a/libs/EXTERNAL/libezgl/src/control.cpp +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#include "ezgl/control.hpp" - -#include "ezgl/camera.hpp" -#include "ezgl/canvas.hpp" - -namespace ezgl { - -static rectangle zoom_in_world(point2d zoom_point, rectangle world, double zoom_factor) -{ - double const left = zoom_point.x - (zoom_point.x - world.left()) / zoom_factor; - double const bottom = zoom_point.y + (world.bottom() - zoom_point.y) / zoom_factor; - - double const right = zoom_point.x + (world.right() - zoom_point.x) / zoom_factor; - double const top = zoom_point.y - (zoom_point.y - world.top()) / zoom_factor; - - return {{left, bottom}, {right, top}}; -} - -static rectangle zoom_out_world(point2d zoom_point, rectangle world, double zoom_factor) -{ - double const left = zoom_point.x - (zoom_point.x - world.left()) * zoom_factor; - double const bottom = zoom_point.y + (world.bottom() - zoom_point.y) * zoom_factor; - - double const right = zoom_point.x + (world.right() - zoom_point.x) * zoom_factor; - double const top = zoom_point.y - (zoom_point.y - world.top()) * zoom_factor; - - return {{left, bottom}, {right, top}}; -} - -void zoom_in(canvas *cnv, double zoom_factor) -{ - point2d const zoom_point = cnv->get_camera().get_world().center(); - rectangle const world = cnv->get_camera().get_world(); - - cnv->get_camera().set_world(zoom_in_world(zoom_point, world, zoom_factor)); - cnv->redraw(); -} - -void zoom_in(canvas *cnv, point2d zoom_point, double zoom_factor) -{ - zoom_point = cnv->get_camera().widget_to_world(zoom_point); - rectangle const world = cnv->get_camera().get_world(); - - cnv->get_camera().set_world(zoom_in_world(zoom_point, world, zoom_factor)); - cnv->redraw(); -} - -void zoom_out(canvas *cnv, double zoom_factor) -{ - point2d const zoom_point = cnv->get_camera().get_world().center(); - rectangle const world = cnv->get_camera().get_world(); - - cnv->get_camera().set_world(zoom_out_world(zoom_point, world, zoom_factor)); - cnv->redraw(); -} - -void zoom_out(canvas *cnv, point2d zoom_point, double zoom_factor) -{ - zoom_point = cnv->get_camera().widget_to_world(zoom_point); - rectangle const world = cnv->get_camera().get_world(); - - cnv->get_camera().set_world(zoom_out_world(zoom_point, world, zoom_factor)); - cnv->redraw(); -} - -void zoom_fit(canvas *cnv, rectangle region) -{ - cnv->get_camera().set_world(region); - cnv->redraw(); -} - -void translate(canvas *cnv, double dx, double dy) -{ - rectangle new_world = cnv->get_camera().get_world(); - new_world += ezgl::point2d(dx, dy); - - cnv->get_camera().set_world(new_world); - cnv->redraw(); -} - -void translate_up(canvas *cnv, double translate_factor) -{ - rectangle new_world = cnv->get_camera().get_world(); - double dy = new_world.height() / translate_factor; - - translate(cnv, 0.0, dy); -} - -void translate_down(canvas *cnv, double translate_factor) -{ - rectangle new_world = cnv->get_camera().get_world(); - double dy = new_world.height() / translate_factor; - - translate(cnv, 0.0, -dy); -} - -void translate_left(canvas *cnv, double translate_factor) -{ - rectangle new_world = cnv->get_camera().get_world(); - double dx = new_world.width() / translate_factor; - - translate(cnv, -dx, 0.0); -} - -void translate_right(canvas *cnv, double translate_factor) -{ - rectangle new_world = cnv->get_camera().get_world(); - double dx = new_world.width() / translate_factor; - - translate(cnv, dx, 0.0); -} -} diff --git a/libs/EXTERNAL/libezgl/src/graphics.cpp b/libs/EXTERNAL/libezgl/src/graphics.cpp deleted file mode 100644 index 344658de323..00000000000 --- a/libs/EXTERNAL/libezgl/src/graphics.cpp +++ /dev/null @@ -1,801 +0,0 @@ -/* - * Copyright 2019 University of Toronto - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Authors: Mario Badr, Sameh Attia and Tanner Young-Schultz - */ - -#include "ezgl/graphics.hpp" - -#include -#include - -namespace ezgl { - -renderer::renderer(cairo_t *cairo, - transform_fn transform, - camera *p_camera, - cairo_surface_t *m_surface) - : m_cairo(cairo), m_transform(std::move(transform)), m_camera(p_camera), rotation_angle(0) -{ -#ifdef EZGL_USE_X11 - // Check if the created cairo surface is an XLIB surface - if (cairo_surface_get_type(m_surface) == CAIRO_SURFACE_TYPE_XLIB) { - // get the underlying x11 drawable used by cairo surface - x11_drawable = cairo_xlib_surface_get_drawable(m_surface); - - // get the x11 display - x11_display = cairo_xlib_surface_get_display(m_surface); - - // create the x11 context from the drawable of the cairo surface - if (x11_display != nullptr) { - x11_context = XCreateGC(x11_display, x11_drawable, 0, 0); - } - } -#endif -} - -renderer::~renderer() -{ -#ifdef EZGL_USE_X11 - // free the x11 context - if (x11_display != nullptr) { - XFreeGC(x11_display, x11_context); - } -#endif -} - -void renderer::update_renderer(cairo_t *cairo, cairo_surface_t *m_surface) -{ - // Update Cairo Context - m_cairo = cairo; - - // Update X11 Context -#ifdef EZGL_USE_X11 - // Check if the created cairo surface is an XLIB surface - if (cairo_surface_get_type(m_surface) == CAIRO_SURFACE_TYPE_XLIB) { - // get the underlying x11 drawable used by cairo surface - x11_drawable = cairo_xlib_surface_get_drawable(m_surface); - - // get the x11 display - x11_display = cairo_xlib_surface_get_display(m_surface); - - // create the x11 context from the drawable of the cairo surface - if (x11_display != nullptr) { - XFreeGC(x11_display, x11_context); - x11_context = XCreateGC(x11_display, x11_drawable, 0, 0); - } - } -#endif - - // Restore graphics attributes - set_color(current_color); - set_line_width(current_line_width); - set_line_cap(current_line_cap); - set_line_dash(current_line_dash); -} - -void renderer::set_coordinate_system(t_coordinate_system new_coordinate_system) -{ - current_coordinate_system = new_coordinate_system; -} - -void renderer::set_visible_world(rectangle new_world) -{ - // Change the aspect ratio of the new_world to align with the aspect ratio of the initial world - // Get the width and height of the new_world - point2d n_center = new_world.center(); - double n_width = new_world.width(); - double n_height = new_world.height(); - - // Get the aspect ratio of the initial world - double i_width = m_camera->get_initial_world().width(); - double i_height = m_camera->get_initial_world().height(); - double i_aspect_ratio = i_width / i_height; - - // Make sure the required area is entirely visible - if (n_width/i_aspect_ratio >= n_height) { - // Change the height - double new_height = n_width/i_aspect_ratio; - new_world ={{n_center.x-n_width/2, n_center.y-new_height/2}, n_width, new_height}; - } - else { - // Change the width - double new_width = n_height*i_aspect_ratio; - new_world ={{n_center.x-new_width/2, n_center.y-n_height/2}, new_width, n_height}; - } - - // set the visible bounds of the world - m_camera->set_world(new_world); -} - -rectangle renderer::get_visible_world() -{ - // m_camera->get_world() is not good representative of the visible world since it doesn't - // account for the drawable margins. - // TODO: precalculate the visible world in camera class to speedup the clipping - - // Get the world and screen dimensions - rectangle world = m_camera->get_world(); - rectangle screen = m_camera->get_screen(); - - // Calculate the margins by converting the screen origin to world coordinates - point2d margin = screen.bottom_left() * m_camera->get_world_scale_factor(); - - // The actual visible world - return {(world.bottom_left() - margin), (world.top_right() + margin)}; -} - -rectangle renderer::get_visible_screen() -{ - // Get the widget dimensions - return m_camera->get_widget(); -} - -rectangle renderer::world_to_screen(const rectangle& box) -{ - point2d origin = m_transform(box.bottom_left()); - point2d top_right = m_transform(box.top_right()); - - return rectangle(origin, top_right); -} - -bool renderer::rectangle_off_screen(rectangle rect) -{ - if(current_coordinate_system == SCREEN) - return false; - - rectangle visible = get_visible_world(); - - if(rect.right() < visible.left()) - return true; - - if(rect.left() > visible.right()) - return true; - - if(rect.top() < visible.bottom()) - return true; - - if(rect.bottom() > visible.top()) - return true; - - return false; -} - -void renderer::set_color(color c) -{ - set_color(c.red, c.green, c.blue, c.alpha); -} - -void renderer::set_color(color c, uint_fast8_t alpha) -{ - set_color(c.red, c.green, c.blue, alpha); -} - -void renderer::set_color(uint_fast8_t red, - uint_fast8_t green, - uint_fast8_t blue, - uint_fast8_t alpha) -{ - // set color for cairo - cairo_set_source_rgba(m_cairo, red / 255.0, green / 255.0, blue / 255.0, alpha / 255.0); - - // set current_color - current_color = {red, green, blue, alpha}; - -#ifdef EZGL_USE_X11 - // check transparency - if(alpha != 255) - transparency_flag = true; - else - transparency_flag = false; - - // set color for x11 (no transparency) - if (x11_display != nullptr) { - unsigned long xcolor = 0; - xcolor |= (red << 2 * 8 | red << 8 | red) & 0xFF0000; - xcolor |= (green << 2 * 8 | green << 8 | green) & 0xFF00; - xcolor |= (blue << 2 * 8 | blue << 8 | blue) & 0xFF; - xcolor |= 0xFF000000; - XSetForeground(x11_display, x11_context, xcolor); - } -#endif -} - -void renderer::set_line_cap(line_cap cap) -{ - auto cairo_cap = static_cast(cap); - cairo_set_line_cap(m_cairo, cairo_cap); - - current_line_cap = cap; - -#ifdef EZGL_USE_X11 - if (x11_display != nullptr) { - XSetLineAttributes(x11_display, x11_context, current_line_width, - current_line_dash == line_dash::none ? LineSolid : LineOnOffDash, - current_line_cap == line_cap::butt ? CapButt : CapRound, JoinMiter); - } -#endif -} - -void renderer::set_line_dash(line_dash dash) -{ - if(dash == line_dash::none) { - int num_dashes = 0; // disables dashing - - cairo_set_dash(m_cairo, nullptr, num_dashes, 0); - } else if(dash == line_dash::asymmetric_5_3) { - static double dashes[] = {5.0, 3.0}; - int num_dashes = 2; // asymmetric dashing - - cairo_set_dash(m_cairo, dashes, num_dashes, 0); - } - - current_line_dash = dash; - -#ifdef EZGL_USE_X11 - if (x11_display != nullptr) { - XSetLineAttributes(x11_display, x11_context, current_line_width, - current_line_dash == line_dash::none ? LineSolid : LineOnOffDash, - current_line_cap == line_cap::butt ? CapButt : CapRound, JoinMiter); - } -#endif -} - -void renderer::set_line_width(int width) -{ - cairo_set_line_width(m_cairo, width == 0 ? 1 : width); - - current_line_width = width; - -#ifdef EZGL_USE_X11 - if (x11_display != nullptr) { - XSetLineAttributes(x11_display, x11_context, current_line_width, - current_line_dash == line_dash::none ? LineSolid : LineOnOffDash, - current_line_cap == line_cap::butt ? CapButt : CapRound, JoinMiter); - } -#endif -} - -void renderer::set_font_size(double new_size) -{ - cairo_set_font_size(m_cairo, new_size); -} - -void renderer::format_font(std::string const &family, font_slant slant, font_weight weight) -{ - cairo_select_font_face(m_cairo, family.c_str(), static_cast(slant), - static_cast(weight)); -} - -void renderer::format_font(std::string const &family, - font_slant slant, - font_weight weight, - double new_size) -{ - set_font_size(new_size); - format_font(family, slant, weight); -} - -void renderer::set_text_rotation(double degrees) -{ - // Bad rotation values (inf, NaN) can cause permanent problems in the - // graphics, as the cairo_restore to undo the rotation doesn't work. - // Check for them before changing the angle. - if (degrees >= -360. && degrees <= 360.) { - // convert the given angle to rad - rotation_angle = -degrees * M_PI / 180; - } - else { - g_warning("set_text_rotation: bad rotation angle of %f. Ignored!", degrees); - } -} - -void renderer::set_horiz_justification(justification horiz_just) -{ - // Ignore illegal values for horizontal justification - if (horiz_just != justification::top && horiz_just != justification::bottom) - horiz_justification = horiz_just; -} - -void renderer::set_vert_justification(justification vert_just) -{ - // Ignore illegal values for vertical justification - if (vert_just != justification::right && vert_just != justification::left) - vert_justification = vert_just; -} - -void renderer::draw_line(point2d start, point2d end) -{ - if(rectangle_off_screen({start, end})) - return; - - if(current_coordinate_system == WORLD) { - start = m_transform(start); - end = m_transform(end); - } - -#ifdef EZGL_USE_X11 - if(!transparency_flag && x11_display != nullptr) { - XDrawLine(x11_display, x11_drawable, x11_context, start.x, start.y, end.x, end.y); - return; - } -#endif - - cairo_move_to(m_cairo, start.x, start.y); - cairo_line_to(m_cairo, end.x, end.y); - - cairo_stroke(m_cairo); -} - -void renderer::draw_rectangle(point2d start, point2d end) -{ - if(rectangle_off_screen({start, end})) - return; - - draw_rectangle_path(start, end, false); -} - -void renderer::draw_rectangle(point2d start, double width, double height) -{ - if(rectangle_off_screen({start, {start.x + width, start.y + height}})) - return; - - draw_rectangle_path(start, {start.x + width, start.y + height}, false); -} - -void renderer::draw_rectangle(rectangle r) -{ - if(rectangle_off_screen({{r.left(), r.bottom()}, {r.right(), r.top()}})) - return; - - draw_rectangle_path({r.left(), r.bottom()}, {r.right(), r.top()}, false); -} - -void renderer::fill_rectangle(point2d start, point2d end) -{ - if(rectangle_off_screen({start, end})) - return; - - draw_rectangle_path(start, end, true); -} - -void renderer::fill_rectangle(point2d start, double width, double height) -{ - if(rectangle_off_screen({start, {start.x + width, start.y + height}})) - return; - - draw_rectangle_path(start, {start.x + width, start.y + height}, true); -} - -void renderer::fill_rectangle(rectangle r) -{ - if(rectangle_off_screen({{r.left(), r.bottom()}, {r.right(), r.top()}})) - return; - - draw_rectangle_path({r.left(), r.bottom()}, {r.right(), r.top()}, true); -} - -// For speed, use a fixed size polygon point buffer when possible -// Dynamically allocate an arbitrary size buffer only when necessary. -#define X11_MAX_FIXED_POLY_PTS 100 - -void renderer::fill_poly(std::vector const &points) -{ - assert(points.size() > 1); - - // Conservative but fast clip test -- check containing rectangle of polygon - double x_min = points[0].x; - double x_max = points[0].x; - double y_min = points[0].y; - double y_max = points[0].y; - - for(std::size_t i = 1; i < points.size(); ++i) { - x_min = std::min(x_min, points[i].x); - x_max = std::max(x_max, points[i].x); - y_min = std::min(y_min, points[i].y); - y_max = std::max(y_max, points[i].y); - } - - if(rectangle_off_screen({{x_min, y_min}, {x_max, y_max}})) - return; - - point2d next_point = points[0]; - -#ifdef EZGL_USE_X11 - if(!transparency_flag && x11_display != nullptr) { - XPoint fixed_trans_points[X11_MAX_FIXED_POLY_PTS]; - XPoint *trans_points = fixed_trans_points; - - if(points.size() > X11_MAX_FIXED_POLY_PTS) { - trans_points = new XPoint[points.size()]; - } - - for(size_t i = 0; i < points.size(); i++) { - if(current_coordinate_system == WORLD) - next_point = m_transform(points[i]); - else - next_point = points[i]; - trans_points[i].x = static_cast(next_point.x); - trans_points[i].y = static_cast(next_point.y); - } - - XFillPolygon(x11_display, x11_drawable, x11_context, trans_points, points.size(), Complex, - CoordModeOrigin); - - if(points.size() > X11_MAX_FIXED_POLY_PTS) - delete[] trans_points; - return; - } -#endif - - if(current_coordinate_system == WORLD) - next_point = m_transform(points[0]); - - cairo_move_to(m_cairo, next_point.x, next_point.y); - - for(std::size_t i = 1; i < points.size(); ++i) { - if(current_coordinate_system == WORLD) - next_point = m_transform(points[i]); - else - next_point = points[i]; - cairo_line_to(m_cairo, next_point.x, next_point.y); - } - - cairo_close_path(m_cairo); - cairo_fill(m_cairo); -} - -void renderer::draw_elliptic_arc(point2d center, - double radius_x, - double radius_y, - double start_angle, - double extent_angle) -{ - if(rectangle_off_screen( - {{center.x - radius_x, center.y - radius_y}, {center.x + radius_x, center.y + radius_y}})) - return; - - // define the stretch factor (i.e. An ellipse is a stretched circle) - double stretch_factor = radius_y / radius_x; - - draw_arc_path(center, radius_x, start_angle, extent_angle, stretch_factor, false); -} - -void renderer::draw_arc(point2d center, double radius, double start_angle, double extent_angle) -{ - if(rectangle_off_screen( - {{center.x - radius, center.y - radius}, {center.x + radius, center.y + radius}})) - return; - - draw_arc_path(center, radius, start_angle, extent_angle, 1, false); -} - -void renderer::fill_elliptic_arc(point2d center, - double radius_x, - double radius_y, - double start_angle, - double extent_angle) -{ - if(rectangle_off_screen( - {{center.x - radius_x, center.y - radius_y}, {center.x + radius_x, center.y + radius_y}})) - return; - - // define the stretch factor (i.e. An ellipse is a stretched circle) - double stretch_factor = radius_y / radius_x; - - draw_arc_path(center, radius_x, start_angle, extent_angle, stretch_factor, true); -} - -void renderer::fill_arc(point2d center, double radius, double start_angle, double extent_angle) -{ - if(rectangle_off_screen( - {{center.x - radius, center.y - radius}, {center.x + radius, center.y + radius}})) - return; - - draw_arc_path(center, radius, start_angle, extent_angle, 1, true); -} - -void renderer::draw_text(point2d point, std::string const &text) -{ - // call the draw_text function with no bounds - draw_text(point, text, DBL_MAX, DBL_MAX); -} - -void renderer::draw_text(point2d point, std::string const &text, double bound_x, double bound_y) -{ - // the center point of the text - point2d center = point; - - // roughly calculate the center point for pre-clipping - if (horiz_justification == justification::left) - center.x += bound_x/2; - else if (horiz_justification == justification::right) - center.x -= bound_x/2; - if (vert_justification == justification::top) - center.y -= bound_y/2; - else if (vert_justification == justification::bottom) - center.y += bound_y/2; - - if(rectangle_off_screen({{center.x - bound_x / 2, center.y - bound_y / 2}, bound_x, bound_y})) - return; - - // get the width and height of the drawn text - cairo_text_extents_t text_extents{0,0,0,0,0,0}; - cairo_text_extents(m_cairo, text.c_str(), &text_extents); - - // get more information about the font used - cairo_font_extents_t font_extents{0,0,0,0,0}; - cairo_font_extents(m_cairo, &font_extents); - - // get text width and height in world coordinates (text width and height are constant in widget coordinates) - double scaled_width = text_extents.width * m_camera->get_world_scale_factor().x; - double scaled_height = text_extents.height * m_camera->get_world_scale_factor().y; - - // if text width or height is greater than the given bounds, don't draw the text. - // NOTE: text rotation is NOT taken into account in bounding check (i.e. text width is compared to bound_x) - if(scaled_width > bound_x || scaled_height > bound_y) { - return; - } - - // save the current state to undo the rotation needed for drawing rotated text - cairo_save(m_cairo); - - // transform the given point - if(current_coordinate_system == WORLD) - center = m_transform(point); - else - center = point; - - // calculating the reference point to center the text around "center" taking into account the rotation_angle - // for more info about reference point location: see https://www.cairographics.org/tutorial/#L1understandingtext - point2d ref_point = {0, 0}; - - ref_point.x = center.x - - (text_extents.x_bearing + (text_extents.width / 2)) * cos(rotation_angle) - - (-font_extents.descent + (text_extents.height / 2)) * sin(rotation_angle); - - ref_point.y = center.y - - (text_extents.y_bearing + (text_extents.height / 2)) * cos(rotation_angle) - - (text_extents.x_bearing + (text_extents.width / 2)) * sin(rotation_angle); - - // adjust the reference point according to the required justification - if (horiz_justification == justification::left) { - ref_point.x += (text_extents.width / 2) * cos(rotation_angle); - ref_point.y += (text_extents.width / 2) * sin(rotation_angle); - } - else if (horiz_justification == justification::right) { - ref_point.x -= (text_extents.width / 2) * cos(rotation_angle); - ref_point.y -= (text_extents.width / 2) * sin(rotation_angle); - } - if (vert_justification == justification::top) { - ref_point.x -= (text_extents.height / 2) * sin(rotation_angle); - ref_point.y += (text_extents.height / 2) * cos(rotation_angle); - } - else if (vert_justification == justification::bottom) { - ref_point.x += (text_extents.height / 2) * sin(rotation_angle); - ref_point.y -= (text_extents.height / 2) * cos(rotation_angle); - } - - // move to the reference point, perform the rotation, and draw the text - cairo_move_to(m_cairo, ref_point.x, ref_point.y); - cairo_rotate(m_cairo, rotation_angle); - cairo_show_text(m_cairo, text.c_str()); - - // restore the old state to undo the performed rotation - cairo_restore(m_cairo); -} - -void renderer::draw_rectangle_path(point2d start, point2d end, bool fill_flag) -{ - if(current_coordinate_system == WORLD) { - start = m_transform(start); - end = m_transform(end); - } - -#ifdef EZGL_USE_X11 - if(!transparency_flag && x11_display != nullptr) { - // Add 0.5 for extra half-pixel accuracy - int start_x = static_cast(start.x + 0.5); - int start_y = static_cast(start.y + 0.5); - int end_x = static_cast(end.x + 0.5); - int end_y = static_cast(end.y + 0.5); - - if(fill_flag) - XFillRectangle(x11_display, x11_drawable, x11_context, std::min(start_x, end_x), - std::min(start_y, end_y), std::abs(end_x - start_x), std::abs(end_y - start_y)); - else - XDrawRectangle(x11_display, x11_drawable, x11_context, std::min(start_x, end_x), - std::min(start_y, end_y), std::abs(end_x - start_x), std::abs(end_y - start_y)); - return; - } -#endif - - cairo_move_to(m_cairo, start.x, start.y); - cairo_line_to(m_cairo, start.x, end.y); - cairo_line_to(m_cairo, end.x, end.y); - cairo_line_to(m_cairo, end.x, start.y); - - cairo_close_path(m_cairo); - - // actual drawing - if(fill_flag) - cairo_fill(m_cairo); - else - cairo_stroke(m_cairo); -} - -void renderer::draw_arc_path(point2d center, - double radius, - double start_angle, - double extent_angle, - double stretch_factor, - bool fill_flag) -{ - // point_x is a point on the arc outline - point2d point_x = {center.x + radius, center.y}; - - // transform the center point of the arc, and the other point - if(current_coordinate_system == WORLD) { - center = m_transform(center); - point_x = m_transform(point_x); - } - - // calculate the new radius after transforming to the new coordinates - radius = point_x.x - center.x; - -#ifdef EZGL_USE_X11 - if(!transparency_flag && x11_display != nullptr) { - if(fill_flag) - XFillArc(x11_display, x11_drawable, x11_context, center.x - radius, - center.y - radius * stretch_factor, 2 * radius, 2 * radius * stretch_factor, - start_angle * 64, extent_angle * 64); - else - XDrawArc(x11_display, x11_drawable, x11_context, center.x - radius, - center.y - radius * stretch_factor, 2 * radius, 2 * radius * stretch_factor, - start_angle * 64, extent_angle * 64); - return; - } -#endif - - // save the current state to undo the scaling needed for drawing ellipse - cairo_save(m_cairo); - - // scale the drawing by the stretch factor to draw elliptic circles - cairo_scale(m_cairo, 1 / stretch_factor, 1); - center.x = center.x * stretch_factor; - radius = radius * stretch_factor; - - // start a new path (forget the current point). Alternative for cairo_move_to() for drawing non-filled arc - cairo_new_path(m_cairo); - - // if the arc will be filled in, start drawing from the center of the arc - if(fill_flag) - cairo_move_to(m_cairo, center.x, center.y); - - // calculating the ending angle - double end_angle = start_angle + extent_angle; - - // draw the arc in counter clock-wise direction if the extent angle is positive - if(extent_angle >= 0) { - cairo_arc_negative( - m_cairo, center.x, center.y, radius, -start_angle * M_PI / 180, -end_angle * M_PI / 180); - } - // draw the arc in clock-wise direction if the extent angle is negative - else { - cairo_arc( - m_cairo, center.x, center.y, radius, -start_angle * M_PI / 180, -end_angle * M_PI / 180); - } - - // if the arc will be filled in, return back to the center of the arc - if(fill_flag) - cairo_close_path(m_cairo); - - // restore the old state to undo the scaling needed for drawing ellipse - cairo_restore(m_cairo); - - // actual drawing - if(fill_flag) - cairo_fill(m_cairo); - else - cairo_stroke(m_cairo); -} - -void renderer::draw_surface(surface *p_surface, point2d point, double scale_factor) -{ - // Check if the surface is properly created - if(cairo_surface_status(p_surface) != CAIRO_STATUS_SUCCESS) { - g_warning("renderer::draw_surface: Error drawing surface at address %p; surface is not valid.", p_surface); - return; - } - - // calculate surface width and height in screen coordinates - double s_width = (double)cairo_image_surface_get_width(p_surface) * scale_factor; - double s_height = (double)cairo_image_surface_get_height(p_surface) * scale_factor; - - // calculate surface width and height in world coordinates - if (current_coordinate_system == WORLD) { - s_width *= m_camera->get_world_scale_factor().x; - s_height *= m_camera->get_world_scale_factor().y; - } - - // Calculate the top left point - point2d top_left = point; - if (horiz_justification == justification::center) - top_left.x -= s_width/2; - else if (horiz_justification == justification::right) - top_left.x -= s_width; - // Vertical justifaction is calculated differently based on the current coordinate system - // Since the origin point of screen coordinates is at the top left, - // while the origin point of world coordinates is at the bottom left - if (vert_justification == justification::center) - top_left.y += (current_coordinate_system == WORLD) ? s_height/2 : -s_height/2; - else if (vert_justification == justification::bottom) - top_left.y += (current_coordinate_system == WORLD) ? s_height : -s_height; - - if (rectangle_off_screen({{top_left.x, top_left.y - s_height}, s_width, s_height})) - return; - - // transform the given point - if(current_coordinate_system == WORLD) - top_left = m_transform(top_left); - - if (scale_factor != 1) { - // save the current state to undo the scaling - cairo_save(m_cairo); - - // scale the cairo context with the given scale factor - cairo_scale(m_cairo, scale_factor, scale_factor); - - // adjust the corner point based on the context scaling - top_left.x /= scale_factor; - top_left.y /= scale_factor; - } - - // Create a source for painting from the surface - cairo_set_source_surface(m_cairo, p_surface, top_left.x, top_left.y); - - // Actual drawing - cairo_paint(m_cairo); - - if (scale_factor != 1) { - // restore the old state to undo the performed scaling - cairo_restore(m_cairo); - } -} - -surface *renderer::load_png(const char *file_path) -{ - // Create an image surface from a PNG image - cairo_surface_t *png_surface = cairo_image_surface_create_from_png(file_path); - - cairo_status_t status = cairo_surface_status(png_surface); - - if (status == CAIRO_STATUS_FILE_NOT_FOUND) { - g_warning("renderer::load_png: File %s not found.", file_path); - } - else if (status != CAIRO_STATUS_SUCCESS) { - g_warning("renderer::load_png: Error loading file %s.", file_path); - } - - return png_surface; -} - -void renderer::free_surface(surface *p_surface) -{ - // Check if the surface is properly created - if (cairo_surface_status(p_surface) == CAIRO_STATUS_SUCCESS) - cairo_surface_destroy(p_surface); -} -} diff --git a/libs/libarchfpga/src/arch_check.cpp b/libs/libarchfpga/src/arch_check.cpp index 75c96aa3cfb..a008dc80cf3 100644 --- a/libs/libarchfpga/src/arch_check.cpp +++ b/libs/libarchfpga/src/arch_check.cpp @@ -1,5 +1,7 @@ #include +#include +#include "arch_util.h" #include "logic_types.h" #include "vtr_log.h" #include "arch_error.h" @@ -157,20 +159,18 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Check from the pb_type's delay annotations match the model // // This ensures that the pb_types' delay annotations are consistent with the model - for (int i = 0; i < pb_type->num_annotations; ++i) { - const t_pin_to_pin_annotation* annot = &pb_type->annotations[i]; - - if (annot->type == E_ANNOT_PIN_TO_PIN_DELAY) { + for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) { + if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) { //Check that any combinational delays specified match the 'combinational_sinks_ports' in the model - if (annot->clock) { + if (annotation.clock) { //Sequential annotation, check that the clock on the specified port matches the model //Annotations always put the pin in the input_pins field - VTR_ASSERT(annot->input_pins); - for (const std::string& input_pin : vtr::split(annot->input_pins)) { + VTR_ASSERT(annotation.input_pins); + for (const std::string& input_pin : vtr::split(annotation.input_pins)) { InstPort annot_port(input_pin); - for (const std::string& clock : vtr::split(annot->clock)) { + for (const std::string& clock : vtr::split(annotation.clock)) { InstPort annot_clock(clock); //Find the model port @@ -185,7 +185,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar if (model_port != nullptr) break; } if (model_port == nullptr) { - archfpga_throw(get_arch_file_name(), annot->line_num, + archfpga_throw(get_arch_file_name(), annotation.line_num, "Failed to find port '%s' on '%s' for sequential delay annotation", annot_port.port_name().c_str(), annot_port.instance_name().c_str()); } @@ -193,13 +193,13 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Check that the clock matches the model definition std::string model_clock = model_port->clock; if (model_clock.empty()) { - archfpga_throw(get_arch_file_name(), annot->line_num, + archfpga_throw(get_arch_file_name(), annotation.line_num, " timing-annotation/ mismatch on port '%s' of model '%s', model specifies" " no clock but timing annotation specifies '%s'", annot_port.port_name().c_str(), model.name, annot_clock.port_name().c_str()); } if (model_port->clock != annot_clock.port_name()) { - archfpga_throw(get_arch_file_name(), annot->line_num, + archfpga_throw(get_arch_file_name(), annotation.line_num, " timing-annotation/ mismatch on port '%s' of model '%s', model specifies" " clock as '%s' but timing annotation specifies '%s'", annot_port.port_name().c_str(), model.name, model_clock.c_str(), annot_clock.port_name().c_str()); @@ -207,12 +207,12 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar } } - } else if (annot->input_pins && annot->output_pins) { + } else if (annotation.input_pins && annotation.output_pins) { //Combinational annotation - VTR_ASSERT_MSG(!annot->clock, "Combinational annotations should have no clock"); - for (const std::string& input_pin : vtr::split(annot->input_pins)) { + VTR_ASSERT_MSG(!annotation.clock, "Combinational annotations should have no clock"); + for (const std::string& input_pin : vtr::split(annotation.input_pins)) { InstPort annot_in(input_pin); - for (const std::string& output_pin : vtr::split(annot->output_pins)) { + for (const std::string& output_pin : vtr::split(annotation.output_pins)) { InstPort annot_out(output_pin); //Find the input model port @@ -225,7 +225,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar } if (model_port == nullptr) { - archfpga_throw(get_arch_file_name(), annot->line_num, + archfpga_throw(get_arch_file_name(), annotation.line_num, "Failed to find port '%s' on '%s' for combinational delay annotation", annot_in.port_name().c_str(), annot_in.instance_name().c_str()); } @@ -235,7 +235,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar auto e = model_port->combinational_sink_ports.end(); auto iter = std::find(b, e, annot_out.port_name()); if (iter == e) { - archfpga_throw(get_arch_file_name(), annot->line_num, + archfpga_throw(get_arch_file_name(), annotation.line_num, " timing-annotation/ mismatch on port '%s' of model '%s', timing annotation" " specifies combinational connection to port '%s' but the connection does not exist in the model", model_port->name, model.name, annot_out.port_name().c_str()); @@ -274,8 +274,8 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar if (model_port->dir == IN_PORT) { //Sequential inputs must have a T_setup or T_hold - if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) == nullptr - && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) { + if (!has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) + && !has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD)) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; msg << " port '" << model_port->name << "' of model '" << model.name << "',"; @@ -291,8 +291,8 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar if (!model_port->combinational_sink_ports.empty()) { //Sequential input with internal combinational connectsion it must also have T_clock_to_Q - if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) == nullptr - && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) { + if (!has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) + && !has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN)) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; msg << " port '" << model_port->name << "' of model '" << model.name << "',"; @@ -311,8 +311,8 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar } else { VTR_ASSERT(model_port->dir == OUT_PORT); //Sequential outputs must have T_clock_to_Q - if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) == nullptr - && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) { + if (!has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) + && !has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN)) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; msg << " port '" << model_port->name << "' of model '" << model.name << "',"; @@ -328,8 +328,8 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar if (comb_connected_outputs.count(model_port->name)) { //Sequential output with internal combinational connectison must have T_setup/T_hold - if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) == nullptr - && find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) { + if (!has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) + && !has_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD)) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; msg << " port '" << model_port->name << "' of model '" << model.name << "',"; @@ -350,7 +350,7 @@ bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_ar //Check that combinationally connected inputs/outputs have combinational delays between them if (model_port->dir == IN_PORT) { for (const auto& sink_port : model_port->combinational_sink_ports) { - if (find_combinational_annotation(pb_type, model_port->name, sink_port) == nullptr) { + if (!has_combinational_annotation(pb_type, model_port->name, sink_port)) { std::stringstream msg; msg << " '" << pb_type->name << "' timing-annotation/ mismatch on"; msg << " port '" << model_port->name << "' of model '" << model.name << "',"; diff --git a/libs/libarchfpga/src/arch_check.h b/libs/libarchfpga/src/arch_check.h index b057cbde347..cd154d022ee 100644 --- a/libs/libarchfpga/src/arch_check.h +++ b/libs/libarchfpga/src/arch_check.h @@ -1,5 +1,4 @@ -#ifndef ARCH_CHECK_H -#define ARCH_CHECK_H +#pragma once /** * This file includes all the definitions of functions which purpose is to @@ -8,12 +7,9 @@ * All new functions corresponding to the architecture checking should end up here. */ -#include "arch_types.h" -#include "arch_util.h" - -#include "physical_types_util.h" - -#include "vtr_util.h" +#include +#include "logic_types.h" +#include "physical_types.h" #ifdef __cplusplus extern "C" { @@ -76,5 +72,3 @@ void check_models(t_arch* arch); #ifdef __cplusplus } #endif - -#endif diff --git a/libs/libarchfpga/src/arch_error.h b/libs/libarchfpga/src/arch_error.h index 0dae1d8592e..b6f3cc3f9e0 100644 --- a/libs/libarchfpga/src/arch_error.h +++ b/libs/libarchfpga/src/arch_error.h @@ -1,5 +1,4 @@ -#ifndef ARCH_ERROR_H -#define ARCH_ERROR_H +#pragma once #include "vtr_error.h" #include @@ -14,5 +13,3 @@ class ArchFpgaError : public vtr::VtrError { ArchFpgaError(std::string msg = "", std::string new_filename = "", size_t new_linenumber = -1) : vtr::VtrError(msg, new_filename, new_linenumber) {} }; - -#endif diff --git a/libs/libarchfpga/src/arch_types.h b/libs/libarchfpga/src/arch_types.h index bc2e65a4ca2..6b4f4338a60 100644 --- a/libs/libarchfpga/src/arch_types.h +++ b/libs/libarchfpga/src/arch_types.h @@ -1,3 +1,4 @@ +#pragma once /* * Data types describing the FPGA architecture. * @@ -5,13 +6,6 @@ * Authors: Jason Luu and Kenneth Kent */ -#ifndef ARCH_TYPES_H -#define ARCH_TYPES_H - -#include "logic_types.h" -#include "physical_types.h" -#include "cad_types.h" - /* Input file parsing. */ #define TOKENS " \t\n" @@ -25,5 +19,3 @@ enum class e_arch_format { VTR, /// #include #include +#include #include "logic_types.h" #include "vtr_assert.h" @@ -162,10 +163,6 @@ void free_arch(t_arch* arch) { vtr::free(arch->architecture_id); - if (arch->clocks) { - vtr::free(arch->clocks->clock_inf); - } - delete (arch->noc); } @@ -309,8 +306,7 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) { static void free_pb_type(t_pb_type* pb_type) { vtr::free(pb_type->name); - if (pb_type->blif_model) - vtr::free(pb_type->blif_model); + vtr::free(pb_type->blif_model); for (int i = 0; i < pb_type->num_modes; ++i) { for (int j = 0; j < pb_type->modes[i].num_pb_type_children; ++j) { @@ -323,67 +319,35 @@ static void free_pb_type(t_pb_type* pb_type) { vtr::free(pb_type->modes[i].interconnect[j].output_string); vtr::free(pb_type->modes[i].interconnect[j].name); - for (int k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; ++k) { - if (pb_type->modes[i].interconnect[j].annotations[k].clock) - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].clock); - if (pb_type->modes[i].interconnect[j].annotations[k].input_pins) { - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].input_pins); - } - if (pb_type->modes[i].interconnect[j].annotations[k].output_pins) { - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].output_pins); - } - for (int m = 0; m < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; ++m) { - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]); - } - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].prop); - vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value); + for (t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) { + vtr::free(annotation.clock); + vtr::free(annotation.input_pins); + vtr::free(annotation.output_pins); } - vtr::free(pb_type->modes[i].interconnect[j].annotations); - if (pb_type->modes[i].interconnect[j].interconnect_power) - vtr::free(pb_type->modes[i].interconnect[j].interconnect_power); + pb_type->modes[i].interconnect[j].annotations.clear(); + delete pb_type->modes[i].interconnect[j].interconnect_power; } - if (pb_type->modes[i].interconnect) - delete[] pb_type->modes[i].interconnect; - if (pb_type->modes[i].mode_power) - vtr::free(pb_type->modes[i].mode_power); + delete[] pb_type->modes[i].interconnect; + delete (pb_type->modes[i].mode_power); } - if (pb_type->modes) - delete[] pb_type->modes; - for (int i = 0; i < pb_type->num_annotations; ++i) { - for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) { - vtr::free(pb_type->annotations[i].value[j]); - } - vtr::free(pb_type->annotations[i].value); - vtr::free(pb_type->annotations[i].prop); - if (pb_type->annotations[i].input_pins) { - vtr::free(pb_type->annotations[i].input_pins); - } - if (pb_type->annotations[i].output_pins) { - vtr::free(pb_type->annotations[i].output_pins); - } - if (pb_type->annotations[i].clock) { - vtr::free(pb_type->annotations[i].clock); - } - } - if (pb_type->num_annotations > 0) { - vtr::free(pb_type->annotations); - } + delete[] pb_type->modes; - if (pb_type->pb_type_power) { - vtr::free(pb_type->pb_type_power); + for (t_pin_to_pin_annotation& annotation : pb_type->annotations) { + vtr::free(annotation.input_pins); + vtr::free(annotation.output_pins); + vtr::free(annotation.clock); } + pb_type->annotations.clear(); + + delete pb_type->pb_type_power; for (int i = 0; i < pb_type->num_ports; ++i) { vtr::free(pb_type->ports[i].name); - if (pb_type->ports[i].port_class) { - vtr::free(pb_type->ports[i].port_class); - } - if (pb_type->ports[i].port_power) { - vtr::free(pb_type->ports[i].port_power); - } + vtr::free(pb_type->ports[i].port_class); + delete pb_type->ports[i].port_power; } - vtr::free(pb_type->ports); + delete[] pb_type->ports; } t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) { @@ -476,7 +440,6 @@ std::unordered_set get_equivalent_sites_set(t_physical void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, char* new_name, t_pb_type* copy) { - int i, j; char* dot; VTR_ASSERT(pb_type->blif_model != nullptr); @@ -495,14 +458,13 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->num_pb = 1; /* Power */ - copy->pb_type_power = (t_pb_type_power*)vtr::calloc(1, - sizeof(t_pb_type_power)); + copy->pb_type_power = new t_pb_type_power(); copy->pb_type_power->estimation_method = power_method_inherited(pb_type->pb_type_power->estimation_method); /* Ports */ copy->num_ports = pb_type->num_ports; - copy->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port)); - for (i = 0; i < pb_type->num_ports; i++) { + copy->ports = new t_port[pb_type->num_ports](); + for (int i = 0; i < pb_type->num_ports; i++) { copy->ports[i].is_clock = pb_type->ports[i].is_clock; copy->ports[i].model_port = pb_type->ports[i].model_port; copy->ports[i].type = pb_type->ports[i].type; @@ -514,8 +476,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->ports[i].index = pb_type->ports[i].index; copy->ports[i].absolute_first_pin_index = pb_type->ports[i].absolute_first_pin_index; - copy->ports[i].port_power = (t_port_power*)vtr::calloc(1, - sizeof(t_port_power)); + copy->ports[i].port_power = new t_port_power(); //Defaults if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) { copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO; @@ -527,9 +488,9 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, } } - copy->annotations = (t_pin_to_pin_annotation*)vtr::calloc(pb_type->num_annotations, sizeof(t_pin_to_pin_annotation)); - copy->num_annotations = pb_type->num_annotations; - for (i = 0; i < copy->num_annotations; i++) { + size_t num_annotations = pb_type->annotations.size(); + copy->annotations.resize(num_annotations); + for (size_t i = 0; i < num_annotations; i++) { copy->annotations[i].clock = vtr::strdup(pb_type->annotations[i].clock); dot = strstr(pb_type->annotations[i].input_pins, "."); copy->annotations[i].input_pins = (char*)vtr::malloc(sizeof(char) * (strlen(new_name) + strlen(dot) + 1)); @@ -548,13 +509,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, copy->annotations[i].line_num = pb_type->annotations[i].line_num; copy->annotations[i].format = pb_type->annotations[i].format; copy->annotations[i].type = pb_type->annotations[i].type; - copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs; - copy->annotations[i].prop = (int*)vtr::malloc(sizeof(int) * pb_type->annotations[i].num_value_prop_pairs); - copy->annotations[i].value = (char**)vtr::malloc(sizeof(char*) * pb_type->annotations[i].num_value_prop_pairs); - for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) { - copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j]; - copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]); - } + copy->annotations[i].annotation_entries = pb_type->annotations[i].annotation_entries; } } @@ -563,7 +518,6 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { char* default_name; t_port* in_port; t_port* out_port; - int i, j; if (strcmp(lut_pb_type->name, "lut") != 0) { default_name = vtr::strdup("lut"); @@ -580,8 +534,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].parent_pb_type = lut_pb_type; lut_pb_type->modes[0].index = 0; lut_pb_type->modes[0].num_pb_type_children = 0; - lut_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + lut_pb_type->modes[0].mode_power = new t_mode_power(); /* Process interconnect */ /* TODO: add timing annotations to route-through */ @@ -613,28 +566,19 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0; lut_pb_type->modes[0].interconnect[0].parent_mode = &lut_pb_type->modes[0]; - lut_pb_type->modes[0].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[0].interconnect[0].interconnect_power = new t_interconnect_power(); - lut_pb_type->modes[0].interconnect[0].annotations = (t_pin_to_pin_annotation*)vtr::calloc(lut_pb_type->num_annotations, - sizeof(t_pin_to_pin_annotation)); - lut_pb_type->modes[0].interconnect[0].num_annotations = lut_pb_type->num_annotations; - for (i = 0; i < lut_pb_type->modes[0].interconnect[0].num_annotations; - i++) { + size_t num_annotations = lut_pb_type->annotations.size(); + lut_pb_type->modes[0].interconnect[0].annotations.resize(num_annotations); + for (size_t i = 0; i < num_annotations; i++) { lut_pb_type->modes[0].interconnect[0].annotations[i].clock = vtr::strdup(lut_pb_type->annotations[i].clock); lut_pb_type->modes[0].interconnect[0].annotations[i].input_pins = vtr::strdup(lut_pb_type->annotations[i].input_pins); lut_pb_type->modes[0].interconnect[0].annotations[i].output_pins = vtr::strdup(lut_pb_type->annotations[i].output_pins); lut_pb_type->modes[0].interconnect[0].annotations[i].line_num = lut_pb_type->annotations[i].line_num; lut_pb_type->modes[0].interconnect[0].annotations[i].format = lut_pb_type->annotations[i].format; lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type; - lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs; - lut_pb_type->modes[0].interconnect[0].annotations[i].prop = (int*)vtr::malloc(sizeof(int) - * lut_pb_type->annotations[i].num_value_prop_pairs); - lut_pb_type->modes[0].interconnect[0].annotations[i].value = (char**)vtr::malloc(sizeof(char*) - * lut_pb_type->annotations[i].num_value_prop_pairs); - for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { - lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j]; - lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]); - } + + lut_pb_type->modes[0].interconnect[0].annotations[i].annotation_entries = lut_pb_type->annotations[i].annotation_entries; } /* Second mode, LUT */ @@ -643,34 +587,20 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].parent_pb_type = lut_pb_type; lut_pb_type->modes[1].index = 1; lut_pb_type->modes[1].num_pb_type_children = 1; - lut_pb_type->modes[1].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + lut_pb_type->modes[1].mode_power = new t_mode_power(); lut_pb_type->modes[1].pb_type_children = new t_pb_type[1]; alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name, lut_pb_type->modes[1].pb_type_children); /* moved annotations to child so delete old annotations */ - for (i = 0; i < lut_pb_type->num_annotations; i++) { - for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) { - free(lut_pb_type->annotations[i].value[j]); - } - free(lut_pb_type->annotations[i].value); - free(lut_pb_type->annotations[i].prop); - if (lut_pb_type->annotations[i].input_pins) { - free(lut_pb_type->annotations[i].input_pins); - } - if (lut_pb_type->annotations[i].output_pins) { - free(lut_pb_type->annotations[i].output_pins); - } - if (lut_pb_type->annotations[i].clock) { - free(lut_pb_type->annotations[i].clock); - } + for (size_t i = 0; i < num_annotations; i++) { + vtr::free(lut_pb_type->annotations[i].input_pins); + vtr::free(lut_pb_type->annotations[i].output_pins); + vtr::free(lut_pb_type->annotations[i].clock); } - lut_pb_type->num_annotations = 0; - free(lut_pb_type->annotations); - lut_pb_type->annotations = nullptr; + lut_pb_type->annotations.clear(); lut_pb_type->modes[1].pb_type_children[0].depth = lut_pb_type->depth + 1; lut_pb_type->modes[1].pb_type_children[0].parent_mode = &lut_pb_type->modes[1]; - for (i = 0; i < lut_pb_type->modes[1].pb_type_children[0].num_ports; i++) { + for (int i = 0; i < lut_pb_type->modes[1].pb_type_children[0].num_ports; i++) { if (lut_pb_type->modes[1].pb_type_children[0].ports[i].type == IN_PORT) { lut_pb_type->modes[1].pb_type_children[0].ports[i].equivalent = PortEquivalence::FULL; } @@ -694,7 +624,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].interconnect[0].parent_mode_index = 1; lut_pb_type->modes[1].interconnect[0].parent_mode = &lut_pb_type->modes[1]; - lut_pb_type->modes[1].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[1].interconnect[0].interconnect_power = new t_interconnect_power(); lut_pb_type->modes[1].interconnect[1].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 11, sizeof(char)); sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s", @@ -713,7 +643,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) { lut_pb_type->modes[1].interconnect[1].parent_mode_index = 1; lut_pb_type->modes[1].interconnect[1].parent_mode = &lut_pb_type->modes[1]; - lut_pb_type->modes[1].interconnect[1].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power)); + lut_pb_type->modes[1].interconnect[1].interconnect_power = new t_interconnect_power(); free(default_name); @@ -738,8 +668,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->modes[0].name = vtr::strdup(default_name); mem_pb_type->modes[0].parent_pb_type = mem_pb_type; mem_pb_type->modes[0].index = 0; - mem_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1, - sizeof(t_mode_power)); + mem_pb_type->modes[0].mode_power = new t_mode_power(); num_pb = OPEN; for (i = 0; i < mem_pb_type->num_ports; i++) { if (mem_pb_type->ports[i].port_class != nullptr @@ -836,8 +765,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { } /* Allocate interconnect power structures */ - mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power(); i_inter++; } else { for (j = 0; j < num_pb; j++) { @@ -877,8 +805,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { } /* Allocate interconnect power structures */ - mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power(); i_inter++; } } @@ -945,7 +872,7 @@ void SyncModelsPbTypes_rec(t_arch* arch, pb_type->model_id = model_match_prim_id; vtr::t_linked_vptr* old = model_match_prim.pb_types; - model_match_prim.pb_types = (vtr::t_linked_vptr*)vtr::malloc(sizeof(vtr::t_linked_vptr)); + model_match_prim.pb_types = new vtr::t_linked_vptr; model_match_prim.pb_types->next = old; model_match_prim.pb_types->data_vptr = pb_type; @@ -1100,39 +1027,37 @@ bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::string& bl return false; } -const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* port, enum e_pin_to_pin_delay_annotations annot_type) { +bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* port, enum e_pin_to_pin_delay_annotations annot_type) { VTR_ASSERT(annot_type == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP || annot_type == E_ANNOT_PIN_TO_PIN_DELAY_THOLD || annot_type == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX || annot_type == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN); - for (int iannot = 0; iannot < pb_type->num_annotations; ++iannot) { - const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot]; - InstPort annot_in(annot->input_pins); + for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) { + InstPort annot_in(annotation.input_pins); if (annot_in.port_name() == port->name) { - for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) { - if (annot->prop[iprop] == annot_type) { - return annot; + for (const auto& [key, val] : annotation.annotation_entries) { + if (key == annot_type) { + return true; } } } } - return nullptr; + return false; } -const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port) { - for (int iannot = 0; iannot < pb_type->num_annotations; ++iannot) { - const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot]; - for (const auto& annot_in_str : vtr::split(annot->input_pins)) { +bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port) { + for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) { + for (const auto& annot_in_str : vtr::split(annotation.input_pins)) { InstPort in_pins(annot_in_str); - for (const auto& annot_out_str : vtr::split(annot->output_pins)) { + for (const auto& annot_out_str : vtr::split(annotation.output_pins)) { InstPort out_pins(annot_out_str); if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) { - for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) { - if (annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MIN) { - return annot; + for (const auto& [key, val] : annotation.annotation_entries) { + if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) { + return true; } } } @@ -1140,7 +1065,7 @@ const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb } } - return nullptr; + return false; } void link_physical_logical_types(std::vector& PhysicalTileTypes, diff --git a/libs/libarchfpga/src/arch_util.h b/libs/libarchfpga/src/arch_util.h index fb87262878c..52660e7da82 100644 --- a/libs/libarchfpga/src/arch_util.h +++ b/libs/libarchfpga/src/arch_util.h @@ -1,7 +1,5 @@ -#ifndef ARCH_UTIL_H -#define ARCH_UTIL_H +#pragma once -#include #include #include "physical_types.h" @@ -98,8 +96,8 @@ bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::st //Returns true of a pb_type (or it's children) contain the specified blif model name bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::string& blif_model_name); -const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* port, enum e_pin_to_pin_delay_annotations annot_type); -const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port); +bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* port, enum e_pin_to_pin_delay_annotations annot_type); +bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port); /** * @brief Updates the physical and logical types based on the equivalence between one and the other. @@ -114,4 +112,3 @@ void link_physical_logical_types(std::vector& PhysicalTile std::vector& LogicalBlockTypes); void setup_pin_classes(t_physical_tile_type* type); -#endif diff --git a/libs/libarchfpga/src/cad_types.h b/libs/libarchfpga/src/cad_types.h index af0aac9a994..9b4610f029b 100644 --- a/libs/libarchfpga/src/cad_types.h +++ b/libs/libarchfpga/src/cad_types.h @@ -1,10 +1,8 @@ +#pragma once /* * Data types used to give architectural hints for the CAD algorithm */ -#ifndef CAD_TYPES_H -#define CAD_TYPES_H -#include "logic_types.h" #include "physical_types.h" struct t_pack_pattern_connections; @@ -128,5 +126,3 @@ struct t_cluster_placement_primitive { float base_cost; /* cost independent of current status of packing */ float incremental_cost; /* cost dependent on current status of packing */ }; - -#endif diff --git a/libs/libarchfpga/src/clock_types.h b/libs/libarchfpga/src/clock_types.h index ac622d29a95..bde96f56436 100644 --- a/libs/libarchfpga/src/clock_types.h +++ b/libs/libarchfpga/src/clock_types.h @@ -1,8 +1,6 @@ -#ifndef CLOCK_TYPES_H -#define CLOCK_TYPES_H +#pragma once #include -#include enum class e_clock_type { SPINE, @@ -59,5 +57,3 @@ struct t_clock_connection_arch { std::string locationy; float fc; }; - -#endif diff --git a/libs/libarchfpga/src/device_grid.h b/libs/libarchfpga/src/device_grid.h index c04e3f8dc4e..1c89164d8d9 100644 --- a/libs/libarchfpga/src/device_grid.h +++ b/libs/libarchfpga/src/device_grid.h @@ -1,5 +1,4 @@ -#ifndef DEVICE_GRID -#define DEVICE_GRID +#pragma once #include #include @@ -149,5 +148,3 @@ class DeviceGrid { std::vector limiting_resources_; }; - -#endif diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 2e08c196946..b7985e471f1 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -5,6 +5,7 @@ #include "echo_arch.h" #include "arch_util.h" #include "logic_types.h" +#include "physical_types.h" #include "vtr_list.h" #include "vtr_util.h" #include "vtr_memory.h" @@ -335,19 +336,19 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { fprintf(Echo, "*************************************************\n"); fprintf(Echo, "Clock:\n"); if (arch->clocks) { - for (int i = 0; i < arch->clocks->num_global_clocks; i++) { - if (arch->clocks->clock_inf[i].autosize_buffer) { - fprintf(Echo, "\tClock[%d]: buffer_size auto C_wire %e", i + 1, - arch->clocks->clock_inf->C_wire); + for (size_t i = 0; i < arch->clocks->size(); i++) { + if ((*arch->clocks)[i].autosize_buffer) { + fprintf(Echo, "\tClock[%zu]: buffer_size auto C_wire %e", i + 1, + (*arch->clocks)[i].C_wire); } else { - fprintf(Echo, "\tClock[%d]: buffer_size %e C_wire %e", i + 1, - arch->clocks->clock_inf[i].buffer_size, - arch->clocks->clock_inf[i].C_wire); + fprintf(Echo, "\tClock[%zu]: buffer_size %e C_wire %e", i + 1, + (*arch->clocks)[i].buffer_size, + (*arch->clocks)[i].C_wire); } fprintf(Echo, "\t\t\t\tstat_prob %f switch_density %f period %e", - arch->clocks->clock_inf[i].prob, - arch->clocks->clock_inf[i].dens, - arch->clocks->clock_inf[i].period); + (*arch->clocks)[i].prob, + (*arch->clocks)[i].dens, + (*arch->clocks)[i].period); } } @@ -381,51 +382,43 @@ static void print_model(FILE* echo, const t_model& model) { } static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models) { - char* tabs; + std::string tabs = std::string(level, '\t'); - tabs = (char*)vtr::malloc((level + 1) * sizeof(char)); - for (int i = 0; i < level; i++) { - tabs[i] = '\t'; - } - tabs[level] = '\0'; - - fprintf(Echo, "%spb_type name: %s\n", tabs, pb_type->name); - fprintf(Echo, "%s\tblif_model: %s\n", tabs, pb_type->blif_model); - fprintf(Echo, "%s\tclass_type: %d\n", tabs, pb_type->class_type); - fprintf(Echo, "%s\tnum_modes: %d\n", tabs, pb_type->num_modes); - fprintf(Echo, "%s\tnum_ports: %d\n", tabs, pb_type->num_ports); + fprintf(Echo, "%spb_type name: %s\n", tabs.c_str(), pb_type->name); + fprintf(Echo, "%s\tblif_model: %s\n", tabs.c_str(), pb_type->blif_model); + fprintf(Echo, "%s\tclass_type: %d\n", tabs.c_str(), pb_type->class_type); + fprintf(Echo, "%s\tnum_modes: %d\n", tabs.c_str(), pb_type->num_modes); + fprintf(Echo, "%s\tnum_ports: %d\n", tabs.c_str(), pb_type->num_ports); for (int i = 0; i < pb_type->num_ports; i++) { - fprintf(Echo, "%s\tport %s type %d num_pins %d\n", tabs, + fprintf(Echo, "%s\tport %s type %d num_pins %d\n", tabs.c_str(), pb_type->ports[i].name, pb_type->ports[i].type, pb_type->ports[i].num_pins); } if (pb_type->num_modes > 0) { /*one or more modes*/ for (int i = 0; i < pb_type->num_modes; i++) { - fprintf(Echo, "%s\tmode %s:\n", tabs, pb_type->modes[i].name); + fprintf(Echo, "%s\tmode %s:\n", tabs.c_str(), pb_type->modes[i].name); for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { PrintPb_types_rec(Echo, &pb_type->modes[i].pb_type_children[j], level + 2, models); } for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) { - fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs, + fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs.c_str(), pb_type->modes[i].interconnect[j].type, pb_type->modes[i].interconnect[j].input_string, pb_type->modes[i].interconnect[j].output_string); - for (int k = 0; - k < pb_type->modes[i].interconnect[j].num_annotations; - k++) { - fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs, - pb_type->modes[i].interconnect[j].annotations[k].input_pins, - pb_type->modes[i].interconnect[j].annotations[k].output_pins, - pb_type->modes[i].interconnect[j].annotations[k].format, - pb_type->modes[i].interconnect[j].annotations[k].value[0]); + for (const t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) { + fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs.c_str(), + annotation.input_pins, + annotation.output_pins, + annotation.format, + annotation.annotation_entries[0].second.c_str()); } //Print power info for interconnects if (pb_type->modes[i].interconnect[j].interconnect_power) { if (pb_type->modes[i].interconnect[j].interconnect_power->power_usage.dynamic || pb_type->modes[i].interconnect[j].interconnect_power->power_usage.leakage) { - fprintf(Echo, "%s\t\t\tpower %e %e\n", tabs, + fprintf(Echo, "%s\t\t\tpower %e %e\n", tabs.c_str(), pb_type->modes[i].interconnect[j].interconnect_power->power_usage.dynamic, pb_type->modes[i].interconnect[j].interconnect_power->power_usage.leakage); } @@ -441,21 +434,20 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, c if (pb_type_model_name != LogicalModels::MODEL_NAMES && pb_type_model_name != LogicalModels::MODEL_INPUT && pb_type_model_name != LogicalModels::MODEL_OUTPUT) { - for (int k = 0; k < pb_type->num_annotations; k++) { - fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs, - pb_type->annotations[k].clock, - pb_type->annotations[k].input_pins, - pb_type->annotations[k].output_pins, - pb_type->annotations[k].format, - pb_type->annotations[k].value[0]); + for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) { + fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs.c_str(), + annotation.clock, + annotation.input_pins, + annotation.output_pins, + annotation.format, + annotation.annotation_entries[0].second.c_str()); } } } if (pb_type->pb_type_power) { - PrintPb_types_recPower(Echo, pb_type, tabs); + PrintPb_types_recPower(Echo, pb_type, tabs.c_str()); } - free(tabs); } //Added May 2013 Daniel Chen, help dump arch info after loading from XML diff --git a/libs/libarchfpga/src/echo_arch.h b/libs/libarchfpga/src/echo_arch.h index 4e9d2300167..38a8c4f8146 100644 --- a/libs/libarchfpga/src/echo_arch.h +++ b/libs/libarchfpga/src/echo_arch.h @@ -1,11 +1,9 @@ -#ifndef ECHO_ARCH_H -#define ECHO_ARCH_H +#pragma once -#include "arch_types.h" +#include +#include "physical_types.h" void EchoArch(const char* EchoFile, const std::vector& PhysicalTileTypes, const std::vector& LogicalBlockTypes, const t_arch* arch); - -#endif diff --git a/libs/libarchfpga/src/histogram.cpp b/libs/libarchfpga/src/histogram.cpp index aa00ec2ae6b..4d6cf9eaca9 100644 --- a/libs/libarchfpga/src/histogram.cpp +++ b/libs/libarchfpga/src/histogram.cpp @@ -1,6 +1,5 @@ #include #include -#include #include #include "vtr_log.h" diff --git a/libs/libarchfpga/src/histogram.h b/libs/libarchfpga/src/histogram.h index 29a0ae47040..2d46e24b6be 100644 --- a/libs/libarchfpga/src/histogram.h +++ b/libs/libarchfpga/src/histogram.h @@ -1,7 +1,7 @@ -#ifndef VPR_HISTOGRAM_H -#define VPR_HISTOGRAM_H +#pragma once #include +#include #include struct HistogramBucket { @@ -22,5 +22,3 @@ void print_histogram(std::vector histogram); float get_histogram_mode(std::vector histogram); std::vector format_histogram(std::vector histogram, size_t width = 80); - -#endif diff --git a/libs/libarchfpga/src/logic_types.cpp b/libs/libarchfpga/src/logic_types.cpp index dc4801d3347..b878c1f202b 100644 --- a/libs/libarchfpga/src/logic_types.cpp +++ b/libs/libarchfpga/src/logic_types.cpp @@ -28,6 +28,7 @@ LogicalModels::LogicalModels() { //INPAD { LogicalModelId inpad_model_id = create_logical_model(MODEL_INPUT); + VTR_ASSERT_OPT(inpad_model_id == MODEL_INPUT_ID); t_model& inpad_model = get_model(inpad_model_id); inpad_model.inputs = nullptr; @@ -47,6 +48,7 @@ LogicalModels::LogicalModels() { //OUTPAD { LogicalModelId outpad_model_id = create_logical_model(MODEL_OUTPUT); + VTR_ASSERT_OPT(outpad_model_id == MODEL_OUTPUT_ID); t_model& outpad_model = get_model(outpad_model_id); outpad_model.inputs = new t_model_ports; @@ -66,6 +68,7 @@ LogicalModels::LogicalModels() { //LATCH { LogicalModelId latch_model_id = create_logical_model(MODEL_LATCH); + VTR_ASSERT_OPT(latch_model_id == MODEL_LATCH_ID); t_model& latch_model = get_model(latch_model_id); t_model_ports* latch_model_input_port_1 = new t_model_ports; t_model_ports* latch_model_input_port_2 = new t_model_ports; @@ -104,6 +107,7 @@ LogicalModels::LogicalModels() { //NAMES { LogicalModelId names_model_id = create_logical_model(MODEL_NAMES); + VTR_ASSERT_OPT(names_model_id == MODEL_NAMES_ID); t_model& names_model = get_model(names_model_id); names_model.inputs = new t_model_ports; @@ -144,7 +148,7 @@ void LogicalModels::free_model_data(t_model& model) { while (vptr) { vtr::t_linked_vptr* vptr_prev = vptr; vptr = vptr->next; - vtr::free(vptr_prev); + delete vptr_prev; } if (model.instances) diff --git a/libs/libarchfpga/src/logic_types.h b/libs/libarchfpga/src/logic_types.h index 0a23b23d8e9..602ec5c2f12 100644 --- a/libs/libarchfpga/src/logic_types.h +++ b/libs/libarchfpga/src/logic_types.h @@ -1,3 +1,4 @@ +#pragma once /* * Data types describing the logic (technology-mapped) models that the architecture can implement. * Logic models include LUT (.names), flipflop (.latch), inpad, outpad, memory slice, etc. @@ -10,9 +11,6 @@ * Date: April, 2025 */ -#ifndef LOGIC_TYPES_H -#define LOGIC_TYPES_H - #include "vtr_assert.h" #include "vtr_list.h" #include "vtr_memory.h" @@ -97,6 +95,13 @@ class LogicalModels { static constexpr const char* MODEL_INPUT = ".input"; static constexpr const char* MODEL_OUTPUT = ".output"; + // The IDs of each of the library models. These are known ahead of time, + // and making these constexpr can save having to look them up in this class. + static constexpr LogicalModelId MODEL_INPUT_ID = LogicalModelId(0); + static constexpr LogicalModelId MODEL_OUTPUT_ID = LogicalModelId(1); + static constexpr LogicalModelId MODEL_LATCH_ID = LogicalModelId(2); + static constexpr LogicalModelId MODEL_NAMES_ID = LogicalModelId(3); + // Iterator for the logical model IDs array. typedef typename vtr::vector_map::const_iterator model_iterator; @@ -268,5 +273,3 @@ class LogicalModels { /// @brief A lookup between the name of a logical model and its ID. std::unordered_map model_name_to_logical_model_id_; }; - -#endif diff --git a/libs/libarchfpga/src/parse_switchblocks.h b/libs/libarchfpga/src/parse_switchblocks.h index 93777f965b6..fd5664818b9 100644 --- a/libs/libarchfpga/src/parse_switchblocks.h +++ b/libs/libarchfpga/src/parse_switchblocks.h @@ -1,9 +1,8 @@ -#ifndef PARSE_SWITCHBLOCKS_H -#define PARSE_SWITCHBLOCKS_H +#pragma once -#include +#include "physical_types.h" #include "pugixml.hpp" -#include "pugixml_util.hpp" +#include "pugixml_loc.hpp" #include "vtr_expr_eval.h" /**** Function Declarations ****/ @@ -18,5 +17,3 @@ void check_switchblock(const t_switchblock_inf* sb, const t_arch* arch); /* returns integer result according to the specified formula and data */ int get_sb_formula_raw_result(vtr::FormulaParser& formula_parser, const char* formula, const vtr::t_formula_data& mydata); - -#endif /* PARSE_SWITCHBLOCKS_H */ diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 6032bcb6d26..162ff81f4e9 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -230,9 +230,20 @@ bool t_logical_block_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } +bool t_logical_block_type::is_io() const { + // Iterate over all equivalent tiles and return true if any + // of them are IO tiles + for (t_physical_tile_type_ptr tile : equivalent_tiles) { + if (tile->is_io()) { + return true; + } + } + return false; +} + const t_port* t_logical_block_type::get_port(std::string_view port_name) const { for (int i = 0; i < pb_type->num_ports; i++) { - auto port = pb_type->ports[i]; + const t_port& port = pb_type->ports[i]; if (port_name == port.name) { return &pb_type->ports[port.index]; } diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index f5ffa481395..cafe99ec0db 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1,3 +1,4 @@ +#pragma once /* * Data types describing the physical components on the FPGA architecture. * @@ -24,8 +25,6 @@ * Authors: Jason Luu and Kenneth Kent */ -#pragma once - #include #include #include @@ -34,12 +33,9 @@ #include #include #include -#include -#include #include #include "vtr_ndmatrix.h" -#include "vtr_hash.h" #include "vtr_bimap.h" #include "vtr_string_interning.h" @@ -49,7 +45,6 @@ #include "vib_inf.h" //Forward declarations -struct t_clock_arch; struct t_clock_network; struct t_power_arch; struct t_interconnect_pins; @@ -168,11 +163,8 @@ enum e_pin_type { enum e_interconnect { COMPLETE_INTERC = 1, DIRECT_INTERC = 2, - MUX_INTERC = 3, - NUM_INTERC_TYPES /* Invalid type */ + MUX_INTERC = 3 }; -/* String version of interconnect types. Use for debugging messages */ -constexpr std::array INTERCONNECT_TYPE_STRING = {{"unknown", "complete", "direct", "mux"}}; /* Orientations. */ enum e_side : unsigned char { @@ -416,12 +408,6 @@ struct t_grid_def { /************************* POWER ***********************************/ -/* Global clock architecture */ -struct t_clock_arch { - int num_global_clocks; - t_clock_network* clock_inf; /* Details about each clock */ -}; - /* Architecture information for a single clock */ struct t_clock_network { bool autosize_buffer; /* autosize clock buffers */ @@ -431,6 +417,15 @@ struct t_clock_network { float prob; /* Static probability of net assigned to this clock */ float dens; /* Switching density of net assigned to this clock */ float period; /* Period of clock */ + + t_clock_network() { + autosize_buffer = false; + buffer_size = 0.0f; + C_wire = 0.0f; + prob = 0.0f; + dens = 0.0f; + period = 0.0f; + } }; /* Power-related architecture information */ @@ -443,12 +438,26 @@ struct t_power_arch { float mux_transistor_size; float FF_size; float LUT_transistor_size; + + t_power_arch() { + C_wire_local = 0.0f; + logical_effort_factor = 0.0f; + local_interc_factor = 0.0f; + transistors_per_SRAM_bit = 0.0f; + mux_transistor_size = 0.0f; + FF_size = 0.0f; + LUT_transistor_size = 0.0f; + } }; /* Power usage for an entity */ struct t_power_usage { float dynamic; float leakage; + t_power_usage() { + dynamic = 0.0f; + leakage = 0.0f; + } }; /*************************************************************************************************/ @@ -543,6 +552,18 @@ struct t_port_power { t_port* scaled_by_port; int scaled_by_port_pin_idx; bool reverse_scaled; /* Scale by (1-prob) */ + + t_port_power() { + wire_type = (e_power_wire_type)0; + wire = {0.0f}; // Default to C = 0.0f + buffer_type = (e_power_buffer_type)0; + buffer_size = 0.0f; + pin_toggle_initialized = false; + energy_per_toggle = 0.0f; + scaled_by_port = nullptr; + scaled_by_port_pin_idx = 0; + reverse_scaled = false; + } }; /** @@ -690,6 +711,7 @@ struct t_physical_tile_type { std::unordered_map> on_tile_pin_num_to_pb_pin; // [root_pin_physical_num][logical_block] -> t_pb_graph_pin* std::unordered_map pin_num_to_pb_pin; // [intra_tile_pin_physical_num] -> t_pb_graph_pin + std::unordered_map pb_pin_to_pin_num; // [t_pb_graph_pin*] -> intra_tile_pin_physical_num std::vector fc_specs; @@ -983,6 +1005,9 @@ struct t_logical_block_type { // Is this t_logical_block_type empty? bool is_empty() const; + // Returns true if this logical block type is an IO block + bool is_io() const; + public: /** * @brief Returns the logical block port given the port name and the corresponding logical block type @@ -1069,8 +1094,7 @@ struct t_pb_type { t_mode* parent_mode = nullptr; int depth = 0; /* depth of pb_type */ - t_pin_to_pin_annotation* annotations = nullptr; /* [0..num_annotations-1] */ - int num_annotations = 0; + std::vector annotations; int index_in_logical_block = 0; /* assign a unique id to each pb_type in a logical block */ @@ -1141,6 +1165,43 @@ struct t_mode { t_metadata_dict meta; }; +/** Info placed between pins in the architecture file (e.g. delay annotations), + * + * This is later for additional information. + * + * Data Members: + * annotation_entries: pairs of annotation subtypes and the annotation values + * type: type of annotation + * format: formatting of data + * input_pins: input pins as string affected by annotation + * output_pins: output pins as string affected by annotation + * clock_pin: clock as string affected by annotation + */ +struct t_pin_to_pin_annotation { + + std::vector> annotation_entries; + + enum e_pin_to_pin_annotation_type type; + enum e_pin_to_pin_annotation_format format; + + char* input_pins; + char* output_pins; + char* clock; + + int line_num; /* used to report what line number this annotation is found in architecture file */ + + t_pin_to_pin_annotation() noexcept { + annotation_entries = std::vector>(); + input_pins = nullptr; + output_pins = nullptr; + clock = nullptr; + + line_num = 0; + type = (e_pin_to_pin_annotation_type)0; + format = (e_pin_to_pin_annotation_format)0; + } +}; + /** Describes an interconnect edge inside a cluster * * This forms part of the t_pb_type hierarchical description of a clustered logic block. @@ -1152,31 +1213,42 @@ struct t_mode { * input_string: input string verbatim to parse later * output_string: input string output to parse later * annotations: Annotations for delay, power, etc - * num_annotations: Total number of annotations * infer_annotations: This interconnect is autogenerated, if true, infer pack_patterns * such as carry-chains and forced packs based on interconnect linked to it * parent_mode_index: Mode of parent as int */ struct t_interconnect { enum e_interconnect type; - char* name = nullptr; + char* name; - char* input_string = nullptr; - char* output_string = nullptr; + char* input_string; + char* output_string; - t_pin_to_pin_annotation* annotations = nullptr; /* [0..num_annotations-1] */ - int num_annotations = 0; - bool infer_annotations = false; + std::vector annotations; + bool infer_annotations; - int line_num = 0; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */ + int line_num; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */ - int parent_mode_index = 0; + int parent_mode_index; /* Power related members */ - t_mode* parent_mode = nullptr; + t_mode* parent_mode; - t_interconnect_power* interconnect_power = nullptr; + t_interconnect_power* interconnect_power; t_metadata_dict meta; + + t_interconnect() { + type = (e_interconnect)0; + name = nullptr; + input_string = nullptr; + output_string = nullptr; + infer_annotations = false; + line_num = 0; + parent_mode_index = 0; + parent_mode = nullptr; + interconnect_power = nullptr; + meta = t_metadata_dict(); + } }; /** Describes I/O and clock ports @@ -1214,6 +1286,22 @@ struct t_port { int absolute_first_pin_index; t_port_power* port_power; + + t_port() { + name = nullptr; + model_port = nullptr; + type = (PORTS)0; + is_clock = false; + is_non_clock_global = false; + num_pins = 0; + equivalent = (PortEquivalence)0; + parent_pb_type = nullptr; + port_class = nullptr; + index = 0; + port_index_by_type = 0; + absolute_first_pin_index = 0; + port_power = nullptr; + } }; struct t_pb_type_power { @@ -1240,6 +1328,15 @@ struct t_interconnect_power { int num_output_ports; int num_pins_per_port; float transistor_cnt; + + t_interconnect_power() { + power_usage = t_power_usage(); + port_info_initialized = false; + num_input_ports = 0; + num_output_ports = 0; + num_pins_per_port = 0; + transistor_cnt = 0.0f; + } }; struct t_interconnect_pins { @@ -1253,34 +1350,6 @@ struct t_mode_power { t_power_usage power_usage; /* Power usage of this mode */ }; -/** Info placed between pins in the architecture file (e.g. delay annotations), - * - * This is later for additional information. - * - * Data Members: - * value: value/property pair - * prop: value/property pair - * type: type of annotation - * format: formatting of data - * input_pins: input pins as string affected by annotation - * output_pins: output pins as string affected by annotation - * clock_pin: clock as string affected by annotation - */ -struct t_pin_to_pin_annotation { - char** value; /* [0..num_value_prop_pairs - 1] */ - int* prop; /* [0..num_value_prop_pairs - 1] */ - int num_value_prop_pairs; - - enum e_pin_to_pin_annotation_type type; - enum e_pin_to_pin_annotation_format format; - - char* input_pins; - char* output_pins; - char* clock; - - int line_num; /* used to report what line number this annotation is found in architecture file */ -}; - /************************************************************************************************* * PB Graph * ************************************************************************************************* @@ -2245,7 +2314,8 @@ struct t_arch { LogicalModels models; t_power_arch* power = nullptr; - t_clock_arch* clocks = nullptr; + + std::shared_ptr> clocks; //determine which layers in multi-die FPGAs require to build global routing resources std::vector layer_global_routing; diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 74ad3aa6f1e..c0535943391 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -1,10 +1,7 @@ -#include +#include #include "vtr_assert.h" -#include "vtr_memory.h" #include "vtr_util.h" -#include "arch_types.h" -#include "arch_util.h" #include "arch_error.h" #include "physical_types_util.h" diff --git a/libs/libarchfpga/src/physical_types_util.h b/libs/libarchfpga/src/physical_types_util.h index 84cad62a845..a89ff092b47 100644 --- a/libs/libarchfpga/src/physical_types_util.h +++ b/libs/libarchfpga/src/physical_types_util.h @@ -1,8 +1,4 @@ - #pragma once - -#include "physical_types.h" - /******************************************************************** * * * Physical types utility functions * @@ -114,6 +110,8 @@ * and CLK_2 (physical pin) from the BUFG (logical block) and CLOCK TILE (physical tile). */ +#include "physical_types.h" + ///@brief Returns true if the absolute physical pin index is an output of the given physical tile type bool is_opin(int ipin, t_physical_tile_type_ptr type); diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 265991c23f2..53760953a7a 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -1,10 +1,15 @@ - #include "read_fpga_interchange_arch.h" -#include "logic_types.h" #ifdef VTR_ENABLE_CAPNPROTO +#include +#include "LogicalNetlist.capnp.h" +#include "logic_types.h" +#include "DeviceResources.capnp.h" +#include "LogicalNetlist.capnp.h" +#include "capnp/serialize.h" + #include #include #include @@ -19,13 +24,21 @@ #include "vtr_assert.h" #include "vtr_digest.h" -#include "vtr_memory.h" #include "vtr_util.h" #include "arch_check.h" #include "arch_error.h" #include "arch_util.h" +#else // VTR_ENABLE_CAPNPROTO + +#include +#include "physical_types.h" +#include "vtr_error.h" + +#endif // VTR_ENABLE_CAPNPROTO + +#ifdef VTR_ENABLE_CAPNPROTO /* * FPGA Interchange Device frontend * @@ -219,7 +232,7 @@ static t_port get_generic_port(t_arch* arch, port.is_non_clock_global = false; port.model_port = nullptr; port.port_class = vtr::strdup(nullptr); - port.port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port.port_power = new t_port_power(); if (!model.empty()) port.model_port = get_model_port(arch, model, name); @@ -243,16 +256,12 @@ static bool block_port_exists(t_pb_type* pb_type, std::string port_name) { static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) { t_pin_to_pin_annotation pp; - pp.prop = (int*)vtr::calloc(1, sizeof(int)); - pp.value = (char**)vtr::calloc(1, sizeof(char*)); - pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT; - pp.prop[0] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME; - pp.value[0] = vtr::strdup(pp_name.c_str()); + pp.annotation_entries.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name}); pp.input_pins = vtr::strdup(input.c_str()); pp.output_pins = vtr::strdup(output.c_str()); - pp.num_value_prop_pairs = 1; + pp.clock = nullptr; return pp; @@ -1290,10 +1299,10 @@ struct ArchReader { lut->parent_mode = mode; lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES); - lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES); + lut->model_id = LogicalModels::MODEL_NAMES_ID; lut->num_ports = 2; - lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port)); + lut->ports = new t_port[lut->num_ports](); lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", LogicalModels::MODEL_NAMES, width); lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", LogicalModels::MODEL_NAMES); @@ -1377,7 +1386,7 @@ struct ArchReader { port->name = is_input ? vtr::strdup(ipin.c_str()) : vtr::strdup(opin.c_str()); port->model_port = nullptr; port->port_class = vtr::strdup(nullptr); - port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port->port_power = new t_port_power(); } // OPAD mode @@ -1395,9 +1404,9 @@ struct ArchReader { num_ports = 1; opad->num_ports = num_ports; - opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + opad->ports = new t_port[num_ports](); opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT); - opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT); + opad->model_id = LogicalModels::MODEL_OUTPUT_ID; opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", LogicalModels::MODEL_OUTPUT); omode->pb_type_children[0] = *opad; @@ -1417,9 +1426,9 @@ struct ArchReader { num_ports = 1; ipad->num_ports = num_ports; - ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + ipad->ports = new t_port[num_ports](); ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT); - ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT); + ipad->model_id = LogicalModels::MODEL_INPUT_ID; ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", LogicalModels::MODEL_INPUT); imode->pb_type_children[0] = *ipad; @@ -1544,7 +1553,7 @@ struct ArchReader { int num_ports = ic_count; leaf->num_ports = num_ports; - leaf->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + leaf->ports = new t_port[num_ports](); leaf->blif_model = vtr::strdup((std::string(".subckt ") + name).c_str()); leaf->model_id = get_model(arch_, name); @@ -1819,8 +1828,7 @@ struct ArchReader { t_interconnect* pp_ic = pair.first; auto num_pp = pair.second.size(); - pp_ic->num_annotations = num_pp; - pp_ic->annotations = new t_pin_to_pin_annotation[num_pp]; + pp_ic->annotations.resize(num_pp); int idx = 0; for (auto pp_name : pair.second) @@ -2082,7 +2090,7 @@ struct ArchReader { pb_type->modes = new t_mode[pb_type->num_modes]; pb_type->num_ports = 2; - pb_type->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port)); + pb_type->ports = new t_port[pb_type->num_ports](); pb_type->num_output_pins = 2; pb_type->num_input_pins = 0; @@ -2118,7 +2126,7 @@ struct ArchReader { int num_ports = 1; leaf_pb_type->num_ports = num_ports; - leaf_pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + leaf_pb_type->ports = new t_port[num_ports](); leaf_pb_type->blif_model = vtr::strdup(const_cell.first.c_str()); leaf_pb_type->model_id = get_model(arch_, const_cell.first); diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.h b/libs/libarchfpga/src/read_fpga_interchange_arch.h index 753b44d3010..cdae78fb516 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.h +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.h @@ -1,18 +1,7 @@ -#ifndef READ_FPGAINTERCHANGE_ARCH_FILE_H -#define READ_FPGAINTERCHANGE_ARCH_FILE_H +#pragma once -#include "arch_types.h" - -#ifdef VTR_ENABLE_CAPNPROTO - -#include "DeviceResources.capnp.h" -#include "LogicalNetlist.capnp.h" -#include "capnp/serialize.h" -#include "capnp/serialize-packed.h" -#include -#include - -#endif // VTR_ENABLE_CAPNPROTO +#include +#include "physical_types.h" #ifdef __cplusplus extern "C" { @@ -34,5 +23,3 @@ void FPGAInterchangeReadArch(const char* FPGAInterchangeDeviceFile, #ifdef __cplusplus } #endif - -#endif diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index a4c0200d053..0865f7311ce 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -50,7 +50,6 @@ #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_util.h" -#include "vtr_memory.h" #include "vtr_digest.h" #include "vtr_token.h" #include "vtr_bimap.h" @@ -378,7 +377,7 @@ static void ProcessPower(pugi::xml_node parent, t_power_arch* power_arch, const pugiutil::loc_data& loc_data); -static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data); +static void ProcessClocks(pugi::xml_node Parent, std::vector& clocks, const pugiutil::loc_data& loc_data); static void ProcessPb_TypePowerEstMethod(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data); static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const pugiutil::loc_data& loc_data); @@ -566,10 +565,9 @@ void XmlReadArch(const char* ArchFile, /* This information still needs to be read, even if it is just * thrown away. */ - t_power_arch* power_arch_fake = (t_power_arch*)vtr::calloc(1, - sizeof(t_power_arch)); + t_power_arch* power_arch_fake = new t_power_arch(); ProcessPower(Next, power_arch_fake, loc_data); - free(power_arch_fake); + delete power_arch_fake; } } @@ -577,16 +575,13 @@ void XmlReadArch(const char* ArchFile, Next = get_single_child(architecture, "clocks", loc_data, POWER_REQD); if (Next) { if (arch->clocks) { - ProcessClocks(Next, arch->clocks, loc_data); + ProcessClocks(Next, *arch->clocks, loc_data); } else { /* This information still needs to be read, even if it is just * thrown away. */ - t_clock_arch* clocks_fake = (t_clock_arch*)vtr::calloc(1, - sizeof(t_clock_arch)); + std::vector clocks_fake; ProcessClocks(Next, clocks_fake, loc_data); - free(clocks_fake->clock_inf); - free(clocks_fake); } } @@ -1047,9 +1042,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, i = 1; } - annotation->num_value_prop_pairs = i; - annotation->prop = (int*)vtr::calloc(i, sizeof(int)); - annotation->value = (char**)vtr::calloc(i, sizeof(char*)); + annotation->annotation_entries.resize(i); annotation->line_num = loc_data.line(Parent); /* Todo: This is slow, I should use a case lookup */ i = 0; @@ -1058,14 +1051,12 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MAX, Prop}; i++; } Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_MIN, Prop}; i++; } Prop = get_attribute(Parent, "in_port", loc_data).value(); @@ -1078,13 +1069,13 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX; Prop = get_attribute(Parent, "type", loc_data).value(); - annotation->value[i] = vtr::strdup(Parent.child_value()); + annotation->annotation_entries[i].second = Parent.child_value(); if (0 == strcmp(Prop, "max")) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX; + annotation->annotation_entries[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MAX; } else { VTR_ASSERT(0 == strcmp(Prop, "min")); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN; + annotation->annotation_entries[i].first = E_ANNOT_PIN_TO_PIN_DELAY_MIN; } i++; @@ -1098,8 +1089,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "C", loc_data).value(); - annotation->value[i] = vtr::strdup(Prop); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C; + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, Prop}; i++; Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); @@ -1112,8 +1102,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, } else if (0 == strcmp(Parent.name(), "C_matrix")) { annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE; annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX; - annotation->value[i] = vtr::strdup(Parent.child_value()); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C; + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_CAPACITANCE_C, Parent.child_value()}; i++; Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); @@ -1127,9 +1116,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "value", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_TSETUP; - annotation->value[i] = vtr::strdup(Prop); - + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_TSETUP, Prop}; i++; Prop = get_attribute(Parent, "port", loc_data).value(); annotation->input_pins = vtr::strdup(Prop); @@ -1146,15 +1133,13 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, bool found_min_max_attrib = false; if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX, Prop}; i++; found_min_max_attrib = true; } Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (Prop) { - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN, Prop}; i++; found_min_max_attrib = true; } @@ -1177,8 +1162,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_DELAY; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "value", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_THOLD; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_DELAY_THOLD, Prop}; i++; Prop = get_attribute(Parent, "port", loc_data).value(); @@ -1193,8 +1177,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, annotation->type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN; annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT; Prop = get_attribute(Parent, "name", loc_data).value(); - annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME; - annotation->value[i] = vtr::strdup(Prop); + annotation->annotation_entries[i] = {E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, Prop}; i++; Prop = get_attribute(Parent, "in_port", loc_data).value(); @@ -1208,7 +1191,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent, "Unknown port type %s in %s in %s", Parent.name(), Parent.parent().name(), Parent.parent().parent().name()); } - VTR_ASSERT(i == annotation->num_value_prop_pairs); + VTR_ASSERT(i == static_cast(annotation->annotation_entries.size())); } static void ProcessPb_TypePowerPinToggle(pugi::xml_node parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) { @@ -1446,7 +1429,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, const int num_out_ports = count_children(Parent, "output", loc_data, ReqOpt::OPTIONAL); const int num_clock_ports = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); const int num_ports = num_in_ports + num_out_ports + num_clock_ports; - pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port)); + pb_type->ports = new t_port[num_ports](); pb_type->num_ports = num_ports; /* Enforce VPR's definition of LUT/FF by checking number of ports */ @@ -1461,7 +1444,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, } /* Initialize Power Structure */ - pb_type->pb_type_power = (t_pb_type_power*)vtr::calloc(1, sizeof(t_pb_type_power)); + pb_type->pb_type_power = new t_pb_type_power(); ProcessPb_TypePowerEstMethod(Parent, pb_type, loc_data); /* process ports */ @@ -1528,8 +1511,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, archfpga_throw(e.filename().c_str(), e.line(), msg.c_str()); } - pb_type->annotations = nullptr; - pb_type->num_annotations = 0; + pb_type->annotations.clear(); /* Determine if this is a leaf or container pb_type */ if (pb_type->blif_model != nullptr) { /* Process delay and capacitance annotations */ @@ -1538,8 +1520,7 @@ static void ProcessPb_Type(pugi::xml_node Parent, num_annotations += count_children(Parent, child_name, loc_data, ReqOpt::OPTIONAL); } - pb_type->annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, sizeof(t_pin_to_pin_annotation)); - pb_type->num_annotations = num_annotations; + pb_type->annotations.resize(num_annotations); int annotation_idx = 0; for (auto child_name : {"delay_constant", "delay_matrix", "C_constant", "C_matrix", "T_setup", "T_clock_to_Q", "T_hold"}) { @@ -1622,7 +1603,7 @@ static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_powe const char* prop; bool wire_defined = false; - port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power)); + port->port_power = new t_port_power(); //Defaults if (power_method == POWER_METHOD_AUTO_SIZES) { @@ -1908,9 +1889,7 @@ static void ProcessInterconnect(vtr::string_internment& strings, num_annotations += count_children(Cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); } - mode->interconnect[interconnect_idx].annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, - sizeof(t_pin_to_pin_annotation)); - mode->interconnect[interconnect_idx].num_annotations = num_annotations; + mode->interconnect[interconnect_idx].annotations.resize(num_annotations); int annotation_idx = 0; for (auto annot_child_name : {"delay_constant", "delay_matrix", "C_constant", "C_matrix", "pack_pattern"}) { @@ -1928,8 +1907,7 @@ static void ProcessInterconnect(vtr::string_internment& strings, VTR_ASSERT(annotation_idx == num_annotations); /* Power */ - mode->interconnect[interconnect_idx].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + mode->interconnect[interconnect_idx].interconnect_power = new t_interconnect_power(); mode->interconnect[interconnect_idx].interconnect_power->port_info_initialized = false; /* get next iteration */ @@ -2009,7 +1987,7 @@ static void ProcessMode(pugi::xml_node Parent, } /* Allocate power structure */ - mode->mode_power = (t_mode_power*)vtr::calloc(1, sizeof(t_mode_power)); + mode->mode_power = new t_mode_power(); if (!implied_mode) { // Implied mode metadata is attached to the pb_type, rather than @@ -5008,32 +4986,26 @@ static void ProcessPower(pugi::xml_node parent, } /* Get the clock architecture */ -static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data) { +static void ProcessClocks(pugi::xml_node Parent, std::vector& clocks, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; const char* tmp; - clocks->num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); + int num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); - /* Alloc the clockdetails */ - clocks->clock_inf = nullptr; - if (clocks->num_global_clocks > 0) { - clocks->clock_inf = (t_clock_network*)vtr::malloc(clocks->num_global_clocks * sizeof(t_clock_network)); - memset(clocks->clock_inf, 0, - clocks->num_global_clocks * sizeof(t_clock_network)); - } + clocks.resize(num_global_clocks, t_clock_network()); /* Load the clock info. */ Node = get_first_child(Parent, "clock", loc_data); - for (int i = 0; i < clocks->num_global_clocks; ++i) { + for (int i = 0; i < num_global_clocks; ++i) { tmp = get_attribute(Node, "buffer_size", loc_data).value(); if (strcmp(tmp, "auto") == 0) { - clocks->clock_inf[i].autosize_buffer = true; + clocks[i].autosize_buffer = true; } else { - clocks->clock_inf[i].autosize_buffer = false; - clocks->clock_inf[i].buffer_size = (float)atof(tmp); + clocks[i].autosize_buffer = false; + clocks[i].buffer_size = (float)atof(tmp); } - clocks->clock_inf[i].C_wire = get_attribute(Node, "C_wire", loc_data).as_float(0); + clocks[i].C_wire = get_attribute(Node, "C_wire", loc_data).as_float(0); /* get the next clock item */ Node = Node.next_sibling(Node.name()); diff --git a/libs/libarchfpga/src/read_xml_arch_file.h b/libs/libarchfpga/src/read_xml_arch_file.h index b6763493a4c..11a327a66b5 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.h +++ b/libs/libarchfpga/src/read_xml_arch_file.h @@ -1,7 +1,7 @@ -#ifndef READ_XML_ARCH_FILE_H -#define READ_XML_ARCH_FILE_H +#pragma once -#include "arch_types.h" +#include +#include "physical_types.h" #ifdef __cplusplus extern "C" { @@ -21,5 +21,3 @@ void XmlReadArch(const char* ArchFile, #ifdef __cplusplus } #endif - -#endif diff --git a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h index ab5015ecc0e..aee99406926 100644 --- a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h +++ b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h @@ -1,6 +1,4 @@ - -#ifndef VTR_READ_XML_ARCH_FILE_NOC_TAG_H -#define VTR_READ_XML_ARCH_FILE_NOC_TAG_H +#pragma once #include "pugixml.hpp" #include "pugixml_loc.hpp" @@ -37,5 +35,3 @@ struct t_mesh_region { /// The number of NoC routers in each row or column. int mesh_size; }; - -#endif //VTR_READ_XML_ARCH_FILE_NOC_TAG_H diff --git a/libs/libarchfpga/src/read_xml_util.h b/libs/libarchfpga/src/read_xml_util.h index b5fa4fbf704..e9cf49d1e18 100644 --- a/libs/libarchfpga/src/read_xml_util.h +++ b/libs/libarchfpga/src/read_xml_util.h @@ -1,5 +1,4 @@ -#ifndef READ_XML_UTIL_H -#define READ_XML_UTIL_H +#pragma once #include "pugixml.hpp" #include "pugixml_loc.hpp" @@ -24,5 +23,3 @@ void bad_attribute_value(const pugi::xml_attribute attr, InstPort make_inst_port(std::string str, pugi::xml_node node, const pugiutil::loc_data& loc_data); InstPort make_inst_port(pugi::xml_attribute attr, pugi::xml_node node, const pugiutil::loc_data& loc_data); - -#endif diff --git a/libs/libarchfpga/src/write_models_bb.h b/libs/libarchfpga/src/write_models_bb.h index 251ebf51aad..1bd872e8bba 100644 --- a/libs/libarchfpga/src/write_models_bb.h +++ b/libs/libarchfpga/src/write_models_bb.h @@ -1,10 +1,7 @@ -#ifndef WRITE_MODELS_BB_H -#define WRITE_MODELS_BB_H +#pragma once -#include "arch_types.h" +#include "physical_types.h" void WriteModels_bb(const char* ArchFile, const char* VEchoFile, const t_arch* arch); - -#endif diff --git a/libs/liblog/src/log.h b/libs/liblog/src/log.h index a350a64c558..8670608f68a 100644 --- a/libs/liblog/src/log.h +++ b/libs/liblog/src/log.h @@ -1,3 +1,4 @@ +#pragma once /** * Lightweight logging tool. Automatically prepend messages with prefixes and store in log file. * @@ -7,9 +8,6 @@ * Date: Sept 5, 2014 */ -#ifndef LOG_H -#define LOG_H - void log_set_output_file(const char* filename); void log_print_direct(const char* message, ...); @@ -18,5 +16,3 @@ void log_print_warning(const char* filename, unsigned int line_num, const char* void log_print_error(const char* filename, unsigned int line_num, const char* message, ...); void log_close(); - -#endif diff --git a/libs/libpugiutil/src/pugixml_loc.hpp b/libs/libpugiutil/src/pugixml_loc.hpp index b8e11fded7d..36e6a1aa10a 100644 --- a/libs/libpugiutil/src/pugixml_loc.hpp +++ b/libs/libpugiutil/src/pugixml_loc.hpp @@ -1,5 +1,4 @@ -#ifndef PUGIXML_LOC_H -#define PUGIXML_LOC_H +#pragma once /* * This file contains utilities for the PUGI XML parser, * hanlding the retrieval of line numbers (useful for error messages) @@ -52,5 +51,3 @@ class loc_data { std::vector offsets_; }; } // namespace pugiutil - -#endif diff --git a/libs/libpugiutil/src/pugixml_util.hpp b/libs/libpugiutil/src/pugixml_util.hpp index 3bb60779fc0..54b27fa8ade 100644 --- a/libs/libpugiutil/src/pugixml_util.hpp +++ b/libs/libpugiutil/src/pugixml_util.hpp @@ -1,5 +1,4 @@ -#ifndef PUGIXML_UTIL_H -#define PUGIXML_UTIL_H +#pragma once /* * This file contains utilities for the PUGI XML parser. * @@ -195,5 +194,3 @@ bool check_node(const pugi::xml_node node, const ReqOpt req_opt = REQUIRED); } // namespace pugiutil - -#endif diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 06bb22e3566..45a1cdef1f8 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -1,5 +1,4 @@ #include "vtr_log.h" -#include "vtr_memory.h" #include "vtr_util.h" #include "vpr_error.h" @@ -9,7 +8,6 @@ #include "physical_types_util.h" #include "describe_rr_node.h" -#include "rr_graph_utils.h" /*********************** Subroutines local to this module *******************/ diff --git a/libs/librrgraph/src/base/check_rr_graph.h b/libs/librrgraph/src/base/check_rr_graph.h index fc0e37fe62a..0d601149d3f 100644 --- a/libs/librrgraph/src/base/check_rr_graph.h +++ b/libs/librrgraph/src/base/check_rr_graph.h @@ -1,5 +1,4 @@ -#ifndef CHECK_RR_GRAPH_H -#define CHECK_RR_GRAPH_H +#pragma once #include "device_grid.h" #include "rr_graph_view.h" @@ -22,5 +21,3 @@ void check_rr_node(const RRGraphView& rr_graph, const enum e_route_type route_type, const int inode, bool is_flat); - -#endif diff --git a/libs/librrgraph/src/base/check_rr_graph_obj.h b/libs/librrgraph/src/base/check_rr_graph_obj.h index 5b5041277b4..fe3bdc23ba1 100644 --- a/libs/librrgraph/src/base/check_rr_graph_obj.h +++ b/libs/librrgraph/src/base/check_rr_graph_obj.h @@ -1,11 +1,7 @@ -#ifndef CHECK_RR_GRAPH_OBJ_H -#define CHECK_RR_GRAPH_OBJ_H - +#pragma once /* Include header files which include data structures used by * the function declaration */ #include "rr_graph_obj.h" bool check_rr_graph(const RRGraph& rr_graph); - -#endif diff --git a/libs/librrgraph/src/base/get_parallel_segs.h b/libs/librrgraph/src/base/get_parallel_segs.h index f173b3aa15c..d6c7be02e64 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.h +++ b/libs/librrgraph/src/base/get_parallel_segs.h @@ -1,5 +1,4 @@ -#ifndef GET_PARALLEL_SEGS_H -#define GET_PARALLEL_SEGS_H +#pragma once #include "rr_graph_type.h" #include "physical_types.h" @@ -20,5 +19,3 @@ std::vector get_parallel_segs(const std::vector& s t_unified_to_parallel_seg_index& seg_index_map, enum e_parallel_axis parallel_axis, bool keep_original_index = false); - -#endif diff --git a/libs/librrgraph/src/base/metadata_storage.h b/libs/librrgraph/src/base/metadata_storage.h index c261ff28aa8..db703d2de4c 100644 --- a/libs/librrgraph/src/base/metadata_storage.h +++ b/libs/librrgraph/src/base/metadata_storage.h @@ -1,6 +1,7 @@ -#ifndef _METADATA_STORAGE_H_ -#define _METADATA_STORAGE_H_ +#pragma once +#include "physical_types.h" +#include "vtr_flat_map.h" #include "vtr_string_interning.h" /** @@ -111,5 +112,3 @@ class MetadataStorage { mutable std::vector> data_; mutable vtr::flat_map map_; }; - -#endif /* _METADATA_STORAGE_H_ */ diff --git a/libs/librrgraph/src/base/rr_edge.h b/libs/librrgraph/src/base/rr_edge.h index 0fb3ac244ff..0f95a96167f 100644 --- a/libs/librrgraph/src/base/rr_edge.h +++ b/libs/librrgraph/src/base/rr_edge.h @@ -1,6 +1,6 @@ -#ifndef RR_EDGE_H -#define RR_EDGE_H +#pragma once +#include "physical_types.h" #include "rr_graph_fwd.h" struct t_rr_edge_info { @@ -27,5 +27,3 @@ struct t_rr_edge_info { }; typedef std::vector t_rr_edge_info_set; - -#endif /* RR_EDGE */ diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 33ea035f0fe..925110a401c 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -5,9 +5,6 @@ #include "vtr_tokenizer.h" #include #include -//#include - -//#include "globals.h" RRGraphBuilder::RRGraphBuilder() { is_edge_dirty_ = true; diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index 576d28c2101..8f6c50ea96f 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -1,6 +1,4 @@ -#ifndef RR_GRAPH_BUILDER_H -#define RR_GRAPH_BUILDER_H - +#pragma once /** * @file * @brief This file defines the RRGraphBuilder data structure which allows data modification on a routing resource graph @@ -13,6 +11,7 @@ * - This is the only data structure allowed to modify a routing resource graph * */ + #include "rr_graph_storage.h" #include "rr_spatial_lookup.h" #include "metadata_storage.h" @@ -525,5 +524,3 @@ class RRGraphBuilder { bool is_edge_dirty_; bool is_incoming_edge_dirty_; }; - -#endif diff --git a/libs/librrgraph/src/base/rr_graph_cost.h b/libs/librrgraph/src/base/rr_graph_cost.h index 6ad8be9e1b8..80b06dcf534 100644 --- a/libs/librrgraph/src/base/rr_graph_cost.h +++ b/libs/librrgraph/src/base/rr_graph_cost.h @@ -1,5 +1,4 @@ -#ifndef RR_GRAPH_COST_H -#define RR_GRAPH_COST_H +#pragma once enum e_base_cost_type { DELAY_NORMALIZED, @@ -20,5 +19,3 @@ enum e_cost_indices { IPIN_COST_INDEX, CHANX_COST_INDEX_START }; - -#endif diff --git a/libs/librrgraph/src/base/rr_graph_fwd.h b/libs/librrgraph/src/base/rr_graph_fwd.h index 2f685e4c15a..1d3b15f7a02 100644 --- a/libs/librrgraph/src/base/rr_graph_fwd.h +++ b/libs/librrgraph/src/base/rr_graph_fwd.h @@ -1,7 +1,7 @@ -#ifndef RR_GRAPH_FWD_H -#define RR_GRAPH_FWD_H +#pragma once #include + #include "vtr_strong_id.h" /*************************************************************** @@ -13,6 +13,8 @@ //Forward declaration class t_rr_graph_storage; +class RRGraph; + struct rr_node_id_tag; struct rr_edge_id_tag; struct rr_indexed_data_id_tag; @@ -26,5 +28,3 @@ typedef vtr::StrongId RRIndexedDataId; typedef vtr::StrongId RRSwitchId; typedef vtr::StrongId RRSegmentId; typedef vtr::StrongId NodeRCIndex; - -#endif diff --git a/libs/librrgraph/src/base/rr_graph_obj.cpp b/libs/librrgraph/src/base/rr_graph_obj.cpp index 211c49990bf..59654aa0992 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.cpp +++ b/libs/librrgraph/src/base/rr_graph_obj.cpp @@ -4,12 +4,8 @@ ***********************************************************************/ #include #include -#include -#include -#include "vtr_vector_map.h" #include "vtr_log.h" -#include "vtr_util.h" #include "vtr_assert.h" #include "rr_graph_obj.h" #include "rr_graph_obj_utils.h" diff --git a/libs/librrgraph/src/base/rr_graph_obj.h b/libs/librrgraph/src/base/rr_graph_obj.h index f3a3f8c8477..59aa34edc1f 100644 --- a/libs/librrgraph/src/base/rr_graph_obj.h +++ b/libs/librrgraph/src/base/rr_graph_obj.h @@ -1,3 +1,4 @@ +#pragma once /************************************************************************ * This file introduces a class to model a Routing Resource Graph (RRGraph or RRG) * which is widely used by placers, routers, analyzers etc. @@ -186,8 +187,6 @@ * } * ***********************************************************************/ -#ifndef RR_GRAPH_OBJ_H -#define RR_GRAPH_OBJ_H /* * Notes in include header files in a head file @@ -196,14 +195,13 @@ */ /* Header files should be included in a sequence */ /* Standard header files required go first */ -#include #include /* EXTERNAL library header files go second*/ +#include "physical_types.h" #include "vtr_vector.h" #include "vtr_range.h" #include "vtr_geometry.h" -#include "arch_types.h" /* VPR header files go third */ #include "rr_node_types.h" @@ -833,5 +831,3 @@ class RRGraph { typedef std::vector>>>> NodeLookup; mutable NodeLookup node_lookup_; }; - -#endif diff --git a/libs/librrgraph/src/base/rr_graph_obj_utils.h b/libs/librrgraph/src/base/rr_graph_obj_utils.h index 910b0ce3acd..708f4f389ec 100644 --- a/libs/librrgraph/src/base/rr_graph_obj_utils.h +++ b/libs/librrgraph/src/base/rr_graph_obj_utils.h @@ -1,10 +1,8 @@ -#ifndef RR_GRAPH_OBJ_UTILS_H -#define RR_GRAPH_OBJ_UTILS_H - +#pragma once /* Include header files which include data structures used by * the function declaration */ -#include + #include "vtr_vector_map.h" /* @@ -161,5 +159,3 @@ ValueContainer update_valid_refs(const ValueContainer& values, const IdContainer } return updated; } - -#endif diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 8ff99e1513a..cf251f56fdd 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -1,7 +1,6 @@ #include #include "arch_types.h" #include "rr_graph_storage.h" -#include "vtr_expr_eval.h" #include "vtr_error.h" #include diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 255b9535e35..0b51747f830 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -1,7 +1,5 @@ -#ifndef RR_GRAPH_STORAGE -#define RR_GRAPH_STORAGE +#pragma once -#include #include #include "vtr_vector.h" @@ -15,7 +13,6 @@ #include "vtr_memory.h" #include "vtr_strong_id_range.h" #include "vtr_array_view.h" -#include #include #include @@ -1222,5 +1219,3 @@ class t_rr_graph_view { const std::unordered_map& virtual_clock_network_root_idx_; }; - -#endif /* _RR_GRAPH_STORAGE_ */ diff --git a/libs/librrgraph/src/base/rr_graph_storage_utils.h b/libs/librrgraph/src/base/rr_graph_storage_utils.h index a2c9dfdeb70..1d60707d66d 100644 --- a/libs/librrgraph/src/base/rr_graph_storage_utils.h +++ b/libs/librrgraph/src/base/rr_graph_storage_utils.h @@ -1,11 +1,12 @@ -#ifndef RR_GRAPH_STORAGE_UTILS_H -#define RR_GRAPH_STORAGE_UTILS_H +#pragma once + +#include +#include // Make room in a vector, with amortized O(1) time by using a pow2 growth pattern. // // This enables potentially random insertion into a vector with amortized O(1) // time. - template void make_room_in_vector(T* vec, size_t elem_position) { if (elem_position < vec->size()) { @@ -23,5 +24,3 @@ void make_room_in_vector(T* vec, size_t elem_position) { vec->resize(elem_position + 1); } - -#endif \ No newline at end of file diff --git a/libs/librrgraph/src/base/rr_graph_type.h b/libs/librrgraph/src/base/rr_graph_type.h index 05c0cad0818..cb4caff72d8 100644 --- a/libs/librrgraph/src/base/rr_graph_type.h +++ b/libs/librrgraph/src/base/rr_graph_type.h @@ -1,5 +1,4 @@ -#ifndef RR_GRAPH_TYPE_H -#define RR_GRAPH_TYPE_H +#pragma once #include #include "physical_types.h" @@ -46,5 +45,3 @@ enum class e_graph_type { * @see get_parallel_segs for more details. */ typedef std::unordered_multimap> t_unified_to_parallel_seg_index; - -#endif \ No newline at end of file diff --git a/libs/librrgraph/src/base/rr_graph_utils.cpp b/libs/librrgraph/src/base/rr_graph_utils.cpp index 6a76ac6bac2..a728ed04593 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.cpp +++ b/libs/librrgraph/src/base/rr_graph_utils.cpp @@ -1,7 +1,5 @@ -#include -#include - #include "rr_graph_utils.h" +#include #include "vpr_error.h" #include "rr_graph_obj.h" #include "rr_graph_builder.h" diff --git a/libs/librrgraph/src/base/rr_graph_utils.h b/libs/librrgraph/src/base/rr_graph_utils.h index 63288b09f3b..53b35fcc5be 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.h +++ b/libs/librrgraph/src/base/rr_graph_utils.h @@ -1,16 +1,16 @@ +#pragma once /** * @file rr_graph_utils.h * * @brief This file includes the most-utilized functions that manipulate the RRGraph object. */ -#ifndef RR_GRAPH_UTILS_H -#define RR_GRAPH_UTILS_H - /* Include header files which include data structures used by * the function declaration */ #include +#include "rr_graph_builder.h" +#include "rr_graph_fwd.h" #include "rr_node_types.h" #include "rr_graph_obj.h" #include "rr_graph_view.h" @@ -99,4 +99,3 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) * @return limited_to_opin */ bool inter_layer_connections_limited_to_opin(const RRGraphView& rr_graph); -#endif diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 2e18db1ce06..5dd66d75719 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -1,6 +1,4 @@ -#ifndef RR_GRAPH_VIEW_H -#define RR_GRAPH_VIEW_H - +#pragma once /** * @file * @brief The RRGraphView encapsulates a read-only routing resource graph as most @@ -60,9 +58,12 @@ * attributes, particularly geometry information (type, x, y, etc.). * \endinternal */ -#include "rr_graph_builder.h" + +#include "metadata_storage.h" #include "rr_node.h" #include "physical_types.h" +#include "rr_spatial_lookup.h" +#include "vtr_geometry.h" class RRGraphView { /* -- Constructors -- */ @@ -695,6 +696,7 @@ class RRGraphView { * The main (perhaps only) current use of this metadata is the fasm tool of symbiflow, * which needs extra metadata on which programming bits control which switch in order to produce a bitstream.*/ const MetadataStorage& rr_node_metadata_; + /** * @brief Attributes for each rr_edge * @@ -724,5 +726,3 @@ class RRGraphView { /** A list of extra ptc numbers for each routing resource node. See details in RRGraphBuilder class */ const vtr::vector>& node_ptc_nums_; }; - -#endif diff --git a/libs/librrgraph/src/base/rr_metadata.h b/libs/librrgraph/src/base/rr_metadata.h index 8bc1577cd08..dd2b9f5b935 100644 --- a/libs/librrgraph/src/base/rr_metadata.h +++ b/libs/librrgraph/src/base/rr_metadata.h @@ -1,5 +1,4 @@ -#ifndef RR_METADATA_H_ -#define RR_METADATA_H_ +#pragma once #include "physical_types.h" #include "rr_graph_builder.h" @@ -15,5 +14,3 @@ void add_rr_edge_metadata(MetadataStorage>& rr_edge_ void add_rr_edge_metadata(MetadataStorage>& rr_edge_metadata, int src_node, int sink_node, short switch_id, vtr::string_view key, vtr::string_view value, const t_arch* arch); } // namespace vpr - -#endif // RR_METADATA_H_ diff --git a/libs/librrgraph/src/base/rr_node.h b/libs/librrgraph/src/base/rr_node.h index f34bb31fa7e..a2cd0aa9b2c 100644 --- a/libs/librrgraph/src/base/rr_node.h +++ b/libs/librrgraph/src/base/rr_node.h @@ -1,5 +1,4 @@ -#ifndef RR_NODE_H -#define RR_NODE_H +#pragma once #include #include "physical_types.h" @@ -7,12 +6,6 @@ #include "rr_graph_fwd.h" #include "rr_node_types.h" -#include "vtr_range.h" - -#include -#include -#include - // t_rr_node is a proxy object for accessing data in t_rr_graph_storage. // // In general, new code should not use this object, but instead directly @@ -150,5 +143,3 @@ struct t_rr_indexed_data { }; #include "rr_node_impl.h" - -#endif diff --git a/libs/librrgraph/src/base/rr_node_fwd.h b/libs/librrgraph/src/base/rr_node_fwd.h index 82807fb01a1..a894594d6ca 100644 --- a/libs/librrgraph/src/base/rr_node_fwd.h +++ b/libs/librrgraph/src/base/rr_node_fwd.h @@ -1,12 +1,6 @@ -#ifndef RR_NODE_FWD_H -#define RR_NODE_FWD_H - -#include -#include "rr_node_types.h" +#pragma once //Forward declaration class t_rr_node; class t_rr_graph_storage; class node_idx_iterator; - -#endif diff --git a/libs/librrgraph/src/base/rr_node_impl.h b/libs/librrgraph/src/base/rr_node_impl.h index 83b93e43b46..4b5f41d62d8 100644 --- a/libs/librrgraph/src/base/rr_node_impl.h +++ b/libs/librrgraph/src/base/rr_node_impl.h @@ -1,5 +1,4 @@ -#ifndef RR_NODE_IMPL_H -#define RR_NODE_IMPL_H +#pragma once // This file provides the inline proxy implemenation for t_rr_node. // See the t_rr_node class comment for additional details. @@ -84,5 +83,3 @@ inline t_edge_size t_rr_node::num_edges() const { inline edge_idx_range t_rr_node::edges() const { return storage_->edges(id_); } - -#endif /* _RR_NODE_IMPL_H_ */ diff --git a/libs/librrgraph/src/base/rr_rc_data.h b/libs/librrgraph/src/base/rr_rc_data.h index 5c2009dc810..60a52a98f5d 100644 --- a/libs/librrgraph/src/base/rr_rc_data.h +++ b/libs/librrgraph/src/base/rr_rc_data.h @@ -1,5 +1,4 @@ -#ifndef _RR_RC_DATA_H_ -#define _RR_RC_DATA_H_ +#pragma once #include "rr_node_types.h" @@ -12,5 +11,3 @@ * The returned indicies index into DeviceContext.rr_rc_data. */ short find_create_rr_rc_data(const float R, const float C, std::vector& rr_rc_data); - -#endif /* _RR_RC_DATA_H_ */ diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index a27f9b6b088..7967454acd0 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -1,6 +1,8 @@ +#include "rr_graph_fwd.h" #include "vtr_assert.h" #include "vtr_log.h" #include "rr_spatial_lookup.h" +#include RRNodeId RRSpatialLookup::find_node(int layer, int x, diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.h b/libs/librrgraph/src/base/rr_spatial_lookup.h index c69f34b791a..733aa413b86 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.h +++ b/libs/librrgraph/src/base/rr_spatial_lookup.h @@ -1,5 +1,4 @@ #pragma once - /** * @file * @brief This RRSpatialLookup class encapsulates @@ -14,6 +13,7 @@ * - Update the look-up with new nodes * - Find the id of a node with given information, e.g., x, y, type etc. */ + #include "vtr_geometry.h" #include "vtr_vector.h" #include "physical_types.h" diff --git a/libs/librrgraph/src/io/rr_graph_reader.cpp b/libs/librrgraph/src/io/rr_graph_reader.cpp index 0bcd843ae34..875587695b8 100644 --- a/libs/librrgraph/src/io/rr_graph_reader.cpp +++ b/libs/librrgraph/src/io/rr_graph_reader.cpp @@ -19,7 +19,6 @@ #include "rr_graph_uxsdcxx.h" #include -#include #include #include "vtr_time.h" @@ -207,4 +206,4 @@ void load_rr_edge_delay_overrides(std::string_view filename, rr_graph_builder.override_edge_switch(edge_id, new_switch_id); } } -} \ No newline at end of file +} diff --git a/libs/librrgraph/src/io/rr_graph_reader.h b/libs/librrgraph/src/io/rr_graph_reader.h index 044345ee721..038addb22fc 100644 --- a/libs/librrgraph/src/io/rr_graph_reader.h +++ b/libs/librrgraph/src/io/rr_graph_reader.h @@ -1,8 +1,6 @@ +#pragma once /* Defines the function used to load an rr graph written in xml format into vpr*/ -#ifndef RR_GRAPH_READER_H -#define RR_GRAPH_READER_H - #include "rr_graph_type.h" #include "rr_graph_cost.h" #include "rr_graph_builder.h" @@ -54,5 +52,3 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, void load_rr_edge_delay_overrides(std::string_view filename, RRGraphBuilder& rr_graph_builder, const RRGraphView& rr_graph); - -#endif /* RR_GRAPH_READER_H */ diff --git a/libs/librrgraph/src/io/rr_graph_writer.cpp b/libs/librrgraph/src/io/rr_graph_writer.cpp index 291d9ffafa4..341bb67c410 100644 --- a/libs/librrgraph/src/io/rr_graph_writer.cpp +++ b/libs/librrgraph/src/io/rr_graph_writer.cpp @@ -13,8 +13,6 @@ #include "rr_graph_uxsdcxx_serializer.h" #include "rr_graph_uxsdcxx.h" #ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "ndmatrix_serdes.h" # include "serdes_utils.h" # include "rr_graph_uxsdcxx_capnp.h" #endif diff --git a/libs/librrgraph/src/io/rr_graph_writer.h b/libs/librrgraph/src/io/rr_graph_writer.h index b84fe3e9f6e..d4abbd1697b 100644 --- a/libs/librrgraph/src/io/rr_graph_writer.h +++ b/libs/librrgraph/src/io/rr_graph_writer.h @@ -1,11 +1,9 @@ +#pragma once /* * This function writes the RR_graph generated by VPR into a file in XML format * Information included in the file includes rr nodes, rr switches, the grid, block info, node indices */ -#ifndef RR_GRAPH_WRITER_H -#define RR_GRAPH_WRITER_H - #include "rr_node.h" #include "rr_graph_type.h" #include "rr_graph_builder.h" @@ -26,5 +24,3 @@ void write_rr_graph(RRGraphBuilder* rr_graph_builder, bool echo_enabled, const char* echo_file_name, bool is_flat); - -#endif diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index c7fb3a254b1..55107e9d223 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -1,23 +1,21 @@ #include /* Needed only for sqrt call (remove if sqrt removed) */ #include #include +#include #include -#include /* Needed for ortho_Cost_index calculation*/ #include "alloc_and_load_rr_indexed_data.h" +#include "arch_types.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_memory.h" #include "vtr_math.h" #include "vpr_error.h" #include "rr_graph_utils.h" -#include "read_xml_arch_file.h" #include "rr_graph_cost.h" -#include "rr_graph_type.h" #include "histogram.h" diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h index 1a96141163a..a70946dc565 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h @@ -1,5 +1,4 @@ -#ifndef ALLOC_AND_LOAD_RR_INDEXED_DATA_H -#define ALLOC_AND_LOAD_RR_INDEXED_DATA_H +#pragma once #include "rr_graph_view.h" #include "rr_node.h" @@ -21,5 +20,3 @@ std::vector find_ortho_cost_index(const RRGraphView& rr_graph, const std::vector segment_inf_x, const std::vector segment_inf_y, e_parallel_axis parallel_axis); - -#endif \ No newline at end of file diff --git a/libs/librrgraph/src/utils/describe_rr_node.h b/libs/librrgraph/src/utils/describe_rr_node.h index 6b3e9355620..3c44031bb1c 100644 --- a/libs/librrgraph/src/utils/describe_rr_node.h +++ b/libs/librrgraph/src/utils/describe_rr_node.h @@ -1,5 +1,4 @@ -#ifndef DESCRIBE_RR_NODE_H -#define DESCRIBE_RR_NODE_H +#pragma once #include #include "rr_graph_view.h" @@ -11,5 +10,3 @@ std::string describe_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, RRNodeId inode, bool is_flat); - -#endif \ No newline at end of file diff --git a/libs/libvtrcapnproto/CMakeLists.txt b/libs/libvtrcapnproto/CMakeLists.txt index 0f66a10856a..cd97b0ec4f1 100644 --- a/libs/libvtrcapnproto/CMakeLists.txt +++ b/libs/libvtrcapnproto/CMakeLists.txt @@ -32,7 +32,7 @@ capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS ) if (VPR_ENABLE_INTERCHANGE) - set(IC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../EXTERNAL/libinterchange/interchange) + set(IC_DIR ${CMAKE_SOURCE_DIR}/libs/EXTERNAL/libinterchange/interchange) set(CAPNPC_SRC_PREFIX ${IC_DIR}) find_program(WGET wget REQUIRED) diff --git a/libs/libvtrcapnproto/intra_cluster_serdes.h b/libs/libvtrcapnproto/intra_cluster_serdes.h index f5579fc8cde..6d99ff2bc88 100644 --- a/libs/libvtrcapnproto/intra_cluster_serdes.h +++ b/libs/libvtrcapnproto/intra_cluster_serdes.h @@ -1,16 +1,12 @@ +#pragma once // // Created by amin on 1/17/23. // -#ifndef VTR_INTRA_CLUSTER_SERDES_H -#define VTR_INTRA_CLUSTER_SERDES_H - #include #include #include -#include "vtr_ndmatrix.h" -#include "vpr_error.h" #include "matrix.capnp.h" #include "map_lookahead.capnp.h" #include "vpr_types.h" @@ -75,8 +71,3 @@ void FromUnorderedMap( flat_idx++; } } - - - - -#endif //VTR_INTRA_CLUSTER_SERDES_H diff --git a/libs/libvtrcapnproto/mmap_file.h b/libs/libvtrcapnproto/mmap_file.h index ee1a93e83c5..4a93144a80a 100644 --- a/libs/libvtrcapnproto/mmap_file.h +++ b/libs/libvtrcapnproto/mmap_file.h @@ -1,8 +1,7 @@ -#ifndef MMAP_FILE_H_ -#define MMAP_FILE_H_ +#pragma once +#include "capnp/common.h" #include -#include "capnp/message.h" #include "kj/array.h" // Platform independent mmap, useful for reading large capnp's. @@ -15,5 +14,3 @@ class MmapFile { size_t size_; kj::Array data_; }; - -#endif /* MMAP_FILE_H_ */ diff --git a/libs/libvtrcapnproto/ndmatrix_serdes.h b/libs/libvtrcapnproto/ndmatrix_serdes.h index 0282d4583b2..11bf3492d68 100644 --- a/libs/libvtrcapnproto/ndmatrix_serdes.h +++ b/libs/libvtrcapnproto/ndmatrix_serdes.h @@ -1,5 +1,4 @@ -#ifndef NDMATRIX_SERDES_H_ -#define NDMATRIX_SERDES_H_ +#pragma once // Provide generic functions for serializing vtr::NdMatrix to and from Cap'n // proto Matrix. // @@ -56,6 +55,7 @@ // vtr::NdMatrix mat_out; // ToNdMatrix<3, Test::Vec2, Vec2>(&mat_out, test.getVectors(), FromVec2); // } + #include #include "vtr_ndmatrix.h" #include "vpr_error.h" @@ -137,5 +137,3 @@ void FromNdMatrix( copy_fun(&elem, m_in.get(i)); } } - -#endif /* NDMATRIX_SERDES_H_ */ diff --git a/libs/libvtrcapnproto/serdes_utils.cpp b/libs/libvtrcapnproto/serdes_utils.cpp index 2201fa584ea..2190f3539ca 100644 --- a/libs/libvtrcapnproto/serdes_utils.cpp +++ b/libs/libvtrcapnproto/serdes_utils.cpp @@ -1,5 +1,6 @@ #include "serdes_utils.h" +#include "capnp/serialize.h" #include #include diff --git a/libs/libvtrcapnproto/serdes_utils.h b/libs/libvtrcapnproto/serdes_utils.h index 723a14772d8..17ba042faa4 100644 --- a/libs/libvtrcapnproto/serdes_utils.h +++ b/libs/libvtrcapnproto/serdes_utils.h @@ -1,9 +1,9 @@ -#ifndef SERDES_UTILS_H_ -#define SERDES_UTILS_H_ +#pragma once +#include "capnp/message.h" +#include #include #include -#include "capnp/serialize.h" // Platform indepedent way to file message to a file on disk. void writeMessageToFile(const std::string& file, @@ -16,5 +16,3 @@ inline ::capnp::ReaderOptions default_large_capnp_opts() { opts.traversalLimitInWords = std::numeric_limits::max(); return opts; } - -#endif /* SERDES_UTILS_H_ */ diff --git a/libs/libvtrutil/src/picosha2.h b/libs/libvtrutil/src/picosha2.h index 67794f92087..9ad8f82eba3 100644 --- a/libs/libvtrutil/src/picosha2.h +++ b/libs/libvtrutil/src/picosha2.h @@ -1,3 +1,4 @@ +#pragma once /* * The MIT License (MIT) * @@ -21,8 +22,6 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#ifndef PICOSHA2_H -#define PICOSHA2_H //picosha2:20140213 #include #include @@ -353,5 +352,3 @@ std::string hash256_hex_string(const RaContainer& src) { } } //namespace picosha2 - -#endif //PICOSHA2_H diff --git a/libs/libvtrutil/src/specrand.h b/libs/libvtrutil/src/specrand.h index 6216a3a341a..2536efcd55e 100644 --- a/libs/libvtrutil/src/specrand.h +++ b/libs/libvtrutil/src/specrand.h @@ -1,5 +1,4 @@ -#ifndef VPR_SPEC_RAND_H -#define VPR_SPEC_RAND_H +#pragma once /* * For inclusion in the SPEC cpu benchmarks * This file implements the random number generation necessary for the SPEC cpu benchmarks. The functions @@ -115,5 +114,3 @@ class SpecRandomNumberGenerator : public vtr::RandomNumberGeneratorInterface { /// the array for the state vector unsigned long mt[N]; }; - -#endif diff --git a/libs/libvtrutil/src/vpr_error.h b/libs/libvtrutil/src/vpr_error.h index 19813253625..8df3adcc4d9 100644 --- a/libs/libvtrutil/src/vpr_error.h +++ b/libs/libvtrutil/src/vpr_error.h @@ -1,9 +1,7 @@ -#ifndef VPR_ERROR_H -#define VPR_ERROR_H +#pragma once #include #include -#include #include "vtr_error.h" @@ -124,5 +122,3 @@ void vpr_throw_opt(enum e_vpr_error type, const char* psz_func_pretty_name, cons do { \ vpr_throw_opt(type, VPR_THROW_FUNCTION, __func__, __FILE__, __LINE__, __VA_ARGS__); \ } while (false) - -#endif diff --git a/libs/libvtrutil/src/vtr_assert.h b/libs/libvtrutil/src/vtr_assert.h index e17448a0c89..f159bc2969e 100644 --- a/libs/libvtrutil/src/vtr_assert.h +++ b/libs/libvtrutil/src/vtr_assert.h @@ -1,6 +1,4 @@ -#ifndef VTR_ASSERT_H -#define VTR_ASSERT_H - +#pragma once /** * @file * @brief The header vtr_assert.h defines useful assertion macros for VTR projects. @@ -147,5 +145,3 @@ namespace assert { [[noreturn]] void handle_assert(const char* expr, const char* file, unsigned int line, const char* function, const char* msg); } // namespace assert } // namespace vtr - -#endif //VTR_ASSERT_H diff --git a/libs/libvtrutil/src/vtr_bimap.h b/libs/libvtrutil/src/vtr_bimap.h index 28e11772d89..014aa0a3259 100644 --- a/libs/libvtrutil/src/vtr_bimap.h +++ b/libs/libvtrutil/src/vtr_bimap.h @@ -1,6 +1,4 @@ -#ifndef VTR_BIMAP -#define VTR_BIMAP - +#pragma once /** * @file * @brief The vtr_bimap.h header provides a bi-directonal mapping between key and value which means that it can be addressed by either the key or the value @@ -181,5 +179,3 @@ template using linear_bimap = bimap; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_cache.h b/libs/libvtrutil/src/vtr_cache.h index deea5311af8..202a4559b3c 100644 --- a/libs/libvtrutil/src/vtr_cache.h +++ b/libs/libvtrutil/src/vtr_cache.h @@ -1,5 +1,4 @@ -#ifndef VTR_CACHE_H_ -#define VTR_CACHE_H_ +#pragma once #include @@ -48,5 +47,3 @@ class Cache { }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_color_map.h b/libs/libvtrutil/src/vtr_color_map.h index f313999caf2..94317850e43 100644 --- a/libs/libvtrutil/src/vtr_color_map.h +++ b/libs/libvtrutil/src/vtr_color_map.h @@ -1,5 +1,5 @@ -#ifndef VTR_CMAP_H -#define VTR_CMAP_H +#pragma once + #include namespace vtr { @@ -55,4 +55,3 @@ class ViridisColorMap : public ColorMap { }; } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_digest.h b/libs/libvtrutil/src/vtr_digest.h index 4d67f8f6acd..75130bcb99e 100644 --- a/libs/libvtrutil/src/vtr_digest.h +++ b/libs/libvtrutil/src/vtr_digest.h @@ -1,5 +1,5 @@ -#ifndef VTR_DIGEST_H -#define VTR_DIGEST_H +#pragma once + #include #include @@ -12,5 +12,3 @@ std::string secure_digest_file(const std::string& filepath); std::string secure_digest_stream(std::istream& is); } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_dynamic_bitset.h b/libs/libvtrutil/src/vtr_dynamic_bitset.h index 87a038f40bc..e2f892d1a52 100644 --- a/libs/libvtrutil/src/vtr_dynamic_bitset.h +++ b/libs/libvtrutil/src/vtr_dynamic_bitset.h @@ -1,5 +1,4 @@ -#ifndef VTR_DYNAMIC_BITSET -#define VTR_DYNAMIC_BITSET +#pragma once #include #include @@ -106,5 +105,3 @@ class dynamic_bitset { }; } // namespace vtr - -#endif /* VTR_DYNAMIC_BITSET */ diff --git a/libs/libvtrutil/src/vtr_error.h b/libs/libvtrutil/src/vtr_error.h index f13d46bcdb7..9fd4015d3f7 100644 --- a/libs/libvtrutil/src/vtr_error.h +++ b/libs/libvtrutil/src/vtr_error.h @@ -1,5 +1,4 @@ -#ifndef VTR_ERROR_H -#define VTR_ERROR_H +#pragma once #include #include @@ -65,5 +64,3 @@ class VtrError : public std::runtime_error { }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_expr_eval.cpp b/libs/libvtrutil/src/vtr_expr_eval.cpp index 791319f4367..e3716865455 100644 --- a/libs/libvtrutil/src/vtr_expr_eval.cpp +++ b/libs/libvtrutil/src/vtr_expr_eval.cpp @@ -5,7 +5,6 @@ #include #include -#include /** global variables **/ diff --git a/libs/libvtrutil/src/vtr_expr_eval.h b/libs/libvtrutil/src/vtr_expr_eval.h index 3c528cccd37..326af017bd5 100644 --- a/libs/libvtrutil/src/vtr_expr_eval.h +++ b/libs/libvtrutil/src/vtr_expr_eval.h @@ -1,11 +1,9 @@ -#ifndef EXPR_EVAL_H -#define EXPR_EVAL_H -#include +#pragma once + #include #include #include #include -#include #include "vtr_util.h" #include "vtr_error.h" @@ -230,5 +228,3 @@ class FormulaParser { }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_flat_map.h b/libs/libvtrutil/src/vtr_flat_map.h index bc857159bdb..251171da7bb 100644 --- a/libs/libvtrutil/src/vtr_flat_map.h +++ b/libs/libvtrutil/src/vtr_flat_map.h @@ -1,5 +1,5 @@ -#ifndef VTR_FLAT_MAP -#define VTR_FLAT_MAP +#pragma once + #include #include #include @@ -480,4 +480,3 @@ class flat_map::value_compare { }; } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index d459653b0a1..4dda5f6b15c 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -1,13 +1,11 @@ -#ifndef VTR_GEOMETRY_H -#define VTR_GEOMETRY_H +#pragma once + #include "vtr_range.h" -#include "vtr_assert.h" #include // vtr_geometry.tpp uses printf() #include #include -#include #include /** @@ -339,4 +337,3 @@ class RectUnion { } // namespace vtr #include "vtr_geometry.tpp" -#endif diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 6cc932ae4a9..8c2aa01d7e8 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -1,3 +1,5 @@ +#include "vtr_assert.h" + namespace vtr { /* * Point diff --git a/libs/libvtrutil/src/vtr_hash.h b/libs/libvtrutil/src/vtr_hash.h index 7e8e6fa42d7..701edc6e22f 100644 --- a/libs/libvtrutil/src/vtr_hash.h +++ b/libs/libvtrutil/src/vtr_hash.h @@ -1,5 +1,5 @@ -#ifndef VTR_HASH_H -#define VTR_HASH_H +#pragma once + #include namespace vtr { @@ -26,5 +26,3 @@ struct hash_pair { }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_linear_map.h b/libs/libvtrutil/src/vtr_linear_map.h index c0ef38cfca2..ab0d533dc47 100644 --- a/libs/libvtrutil/src/vtr_linear_map.h +++ b/libs/libvtrutil/src/vtr_linear_map.h @@ -1,5 +1,5 @@ -#ifndef VTR_LINEAR_MAP_H -#define VTR_LINEAR_MAP_H +#pragma once + #include #include @@ -309,4 +309,3 @@ class linear_map { }; } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_list.h b/libs/libvtrutil/src/vtr_list.h index 8403742c70e..656cb8e5024 100644 --- a/libs/libvtrutil/src/vtr_list.h +++ b/libs/libvtrutil/src/vtr_list.h @@ -1,5 +1,4 @@ -#ifndef VTR_LIST_H -#define VTR_LIST_H +#pragma once /** * @file @@ -21,4 +20,3 @@ t_linked_vptr* insert_in_vptr_list(t_linked_vptr* head, ///@brief Delete a list t_linked_vptr* delete_in_vptr_list(t_linked_vptr* head); } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_log.h b/libs/libvtrutil/src/vtr_log.h index d9b340d1214..279f0940279 100644 --- a/libs/libvtrutil/src/vtr_log.h +++ b/libs/libvtrutil/src/vtr_log.h @@ -1,9 +1,4 @@ -#ifndef VTR_LOG_H -#define VTR_LOG_H -#include -#include -#include - +#pragma once /** * @file * @brief This header defines useful logging macros for VTR projects. @@ -57,6 +52,9 @@ * is defined (disabled by default). */ +#include +#include + // Unconditional logging macros #define VTR_LOG(...) VTR_LOGV(true, __VA_ARGS__) #define VTR_LOG_WARN(...) VTR_LOGV_WARN(true, __VA_ARGS__) @@ -165,5 +163,3 @@ void set_noisy_warn_log_file(std::string log_file_name); * noisy_warn_log_file, otherwise it is printed on stdout (or the regular log file) */ void print_or_suppress_warning(const char* pszFileName, unsigned int lineNum, const char* pszFuncName, const char* pszMessage, ...); - -#endif diff --git a/libs/libvtrutil/src/vtr_logic.h b/libs/libvtrutil/src/vtr_logic.h index 3ad2deb7f97..4839781dfcf 100644 --- a/libs/libvtrutil/src/vtr_logic.h +++ b/libs/libvtrutil/src/vtr_logic.h @@ -1,7 +1,6 @@ +#pragma once // Put this above guard so that TRUE/FALSE are undef'ed // even if this file was already included earlier. -#ifndef VTR_LOGIC_H -#define VTR_LOGIC_H #ifdef FALSE #undef FALSE @@ -34,5 +33,3 @@ enum class LogicValue { constexpr std::array LOGIC_VALUE_STRING = {{"false", "true", "don't care", "unknown"}}; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_map_util.h b/libs/libvtrutil/src/vtr_map_util.h index fd1cdd4f88e..eb1460b00c7 100644 --- a/libs/libvtrutil/src/vtr_map_util.h +++ b/libs/libvtrutil/src/vtr_map_util.h @@ -1,5 +1,4 @@ -#ifndef VTR_MAP_UTIL_H -#define VTR_MAP_UTIL_H +#pragma once #include "vtr_pair_util.h" #include "vtr_range.h" @@ -41,5 +40,3 @@ auto make_value_range(const Container& c) { } } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_math.h b/libs/libvtrutil/src/vtr_math.h index 74b4ccebf58..c5124ba2349 100644 --- a/libs/libvtrutil/src/vtr_math.h +++ b/libs/libvtrutil/src/vtr_math.h @@ -1,12 +1,9 @@ -#ifndef VTR_MATH_H -#define VTR_MATH_H +#pragma once #include #include #include -#include "vtr_assert.h" - /** * @file * @@ -164,5 +161,3 @@ bool isclose(T a, T b) { } } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_memory.cpp b/libs/libvtrutil/src/vtr_memory.cpp index 4bea9f1c652..436cc2c84bb 100644 --- a/libs/libvtrutil/src/vtr_memory.cpp +++ b/libs/libvtrutil/src/vtr_memory.cpp @@ -7,7 +7,6 @@ #include "vtr_memory.h" #include "vtr_error.h" #include "vtr_util.h" -#include "vtr_log.h" #ifndef __GLIBC__ #include diff --git a/libs/libvtrutil/src/vtr_memory.h b/libs/libvtrutil/src/vtr_memory.h index 4c9877ec2cc..a4a138617e2 100644 --- a/libs/libvtrutil/src/vtr_memory.h +++ b/libs/libvtrutil/src/vtr_memory.h @@ -1,5 +1,5 @@ -#ifndef VTR_MEMORY_H -#define VTR_MEMORY_H +#pragma once + #include #include #include @@ -147,5 +147,3 @@ bool operator==(const aligned_allocator&, const aligned_allocator&) { } } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_ndmatrix.h b/libs/libvtrutil/src/vtr_ndmatrix.h index 7c3eb5d7c49..9d19ecc90c7 100644 --- a/libs/libvtrutil/src/vtr_ndmatrix.h +++ b/libs/libvtrutil/src/vtr_ndmatrix.h @@ -1,5 +1,5 @@ -#ifndef VTR_ND_MATRIX_H -#define VTR_ND_MATRIX_H +#pragma once + #include #include #include @@ -437,4 +437,3 @@ template using Matrix = NdMatrix; } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h index 0e1001239bc..3272d1abe1d 100644 --- a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h +++ b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h @@ -1,5 +1,5 @@ -#ifndef VTR_ND_OFFSET_MATRIX_H -#define VTR_ND_OFFSET_MATRIX_H +#pragma once + #include #include #include @@ -458,4 +458,3 @@ template using OffsetMatrix = NdOffsetMatrix; } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_optional.h b/libs/libvtrutil/src/vtr_optional.h index 8aea3c0e2c2..aa832a932d7 100644 --- a/libs/libvtrutil/src/vtr_optional.h +++ b/libs/libvtrutil/src/vtr_optional.h @@ -1,5 +1,4 @@ #pragma once - /** * @file * @brief std::optional-like interface with optional references. diff --git a/libs/libvtrutil/src/vtr_ostream_guard.h b/libs/libvtrutil/src/vtr_ostream_guard.h index 199c5cb4cc5..d2ab07e81b4 100644 --- a/libs/libvtrutil/src/vtr_ostream_guard.h +++ b/libs/libvtrutil/src/vtr_ostream_guard.h @@ -1,5 +1,6 @@ -#ifndef VTR_OSTREAM_GUARD_H -#define VTR_OSTREAM_GUARD_H +#pragma once + +#include namespace vtr { @@ -36,5 +37,3 @@ class OsFormatGuard { }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_pair_util.h b/libs/libvtrutil/src/vtr_pair_util.h index cddb4162543..be5dd4b9282 100644 --- a/libs/libvtrutil/src/vtr_pair_util.h +++ b/libs/libvtrutil/src/vtr_pair_util.h @@ -1,7 +1,6 @@ -#ifndef VTR_PAIR_UTIL_H -#define VTR_PAIR_UTIL_H +#pragma once -#include "vtr_range.h" +#include namespace vtr { /** @@ -93,4 +92,3 @@ class pair_second_iter { }; } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_path.h b/libs/libvtrutil/src/vtr_path.h index a48d2bdb59c..eb1948903c8 100644 --- a/libs/libvtrutil/src/vtr_path.h +++ b/libs/libvtrutil/src/vtr_path.h @@ -1,5 +1,5 @@ -#ifndef VTR_PATH_H -#define VTR_PATH_H +#pragma once + #include #include @@ -30,4 +30,3 @@ std::string dirname(const std::string& path); std::string getcwd(); } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_prefix_sum.h b/libs/libvtrutil/src/vtr_prefix_sum.h index 31635904f1b..a5817f848fc 100644 --- a/libs/libvtrutil/src/vtr_prefix_sum.h +++ b/libs/libvtrutil/src/vtr_prefix_sum.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -6,8 +7,6 @@ * sums over regions of an unchanging grid of values. */ -#pragma once - #include #include #include "vtr_assert.h" diff --git a/libs/libvtrutil/src/vtr_ragged_matrix.h b/libs/libvtrutil/src/vtr_ragged_matrix.h index 862047e0b1e..de51eee9114 100644 --- a/libs/libvtrutil/src/vtr_ragged_matrix.h +++ b/libs/libvtrutil/src/vtr_ragged_matrix.h @@ -1,5 +1,5 @@ -#ifndef VTR_RAGGED_MATRIX_H -#define VTR_RAGGED_MATRIX_H +#pragma once + #include #include #include @@ -258,5 +258,3 @@ class FlatRaggedMatrix { }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_random.h b/libs/libvtrutil/src/vtr_random.h index 15614b7141e..ec82d1cf41f 100644 --- a/libs/libvtrutil/src/vtr_random.h +++ b/libs/libvtrutil/src/vtr_random.h @@ -1,5 +1,4 @@ -#ifndef VTR_RANDOM_H -#define VTR_RANDOM_H +#pragma once #include //For std::swap #include @@ -94,4 +93,3 @@ void shuffle(Iter first, Iter last, RngContainer& rng) { } } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_range.h b/libs/libvtrutil/src/vtr_range.h index 9674f5e45c0..2692a5715bc 100644 --- a/libs/libvtrutil/src/vtr_range.h +++ b/libs/libvtrutil/src/vtr_range.h @@ -1,5 +1,5 @@ -#ifndef VTR_RANGE_H -#define VTR_RANGE_H +#pragma once + #include namespace vtr { @@ -81,5 +81,3 @@ template inline auto make_range(const Container& c) { return make_range(std::begin(c), std::end(c)); } } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_rusage.h b/libs/libvtrutil/src/vtr_rusage.h index b69dc438a97..5b2c5f60be4 100644 --- a/libs/libvtrutil/src/vtr_rusage.h +++ b/libs/libvtrutil/src/vtr_rusage.h @@ -1,5 +1,5 @@ -#ifndef VTR_RUSAGE_H -#define VTR_RUSAGE_H +#pragma once + #include namespace vtr { @@ -7,5 +7,3 @@ namespace vtr { ///@brief Returns the maximum resident set size in bytes, or zero if unable to determine. size_t get_max_rss(); } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_sentinels.h b/libs/libvtrutil/src/vtr_sentinels.h index 036fd593b17..ff48f897100 100644 --- a/libs/libvtrutil/src/vtr_sentinels.h +++ b/libs/libvtrutil/src/vtr_sentinels.h @@ -1,5 +1,4 @@ -#ifndef VTR_SENTINELS_H -#define VTR_SENTINELS_H +#pragma once /** * @file @@ -46,4 +45,3 @@ template using MinusOneSentinel = CustomSentinel; } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_small_vector.h b/libs/libvtrutil/src/vtr_small_vector.h index 5fe75520129..5aa1c89f781 100644 --- a/libs/libvtrutil/src/vtr_small_vector.h +++ b/libs/libvtrutil/src/vtr_small_vector.h @@ -1,5 +1,5 @@ -#ifndef VTR_SMALL_VECTOR -#define VTR_SMALL_VECTOR +#pragma once + #include #include #include @@ -850,5 +850,3 @@ class small_vector { }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_string_interning.h b/libs/libvtrutil/src/vtr_string_interning.h index 65b611e6015..c845aded20c 100644 --- a/libs/libvtrutil/src/vtr_string_interning.h +++ b/libs/libvtrutil/src/vtr_string_interning.h @@ -1,5 +1,4 @@ -#ifndef VTR_STRING_INTERNING_H_ -#define VTR_STRING_INTERNING_H_ +#pragma once /** * @file @@ -44,7 +43,6 @@ */ #include #include -#include #include #include #include @@ -555,5 +553,3 @@ struct hash { } }; } // namespace std - -#endif /* VTR_STRING_INTERNING_H_ */ diff --git a/libs/libvtrutil/src/vtr_string_view.h b/libs/libvtrutil/src/vtr_string_view.h index 12a7a7a446c..cc76c40d851 100644 --- a/libs/libvtrutil/src/vtr_string_view.h +++ b/libs/libvtrutil/src/vtr_string_view.h @@ -1,9 +1,7 @@ -#ifndef VTR_STRING_VIEW_H_ -#define VTR_STRING_VIEW_H_ +#pragma once #include #include -#include #include #include "vtr_hash.h" @@ -188,5 +186,3 @@ struct hash { } }; } // namespace std - -#endif /* VTR_STRING_VIEW_H_ */ diff --git a/libs/libvtrutil/src/vtr_strong_id.h b/libs/libvtrutil/src/vtr_strong_id.h index 672dbae1e7e..48970bfaa10 100644 --- a/libs/libvtrutil/src/vtr_strong_id.h +++ b/libs/libvtrutil/src/vtr_strong_id.h @@ -1,5 +1,4 @@ -#ifndef VTR_STRONG_ID_H -#define VTR_STRONG_ID_H +#pragma once /** * @file * @brief This header provides the StrongId class. @@ -262,5 +261,3 @@ struct hash> { } }; } //namespace std - -#endif diff --git a/libs/libvtrutil/src/vtr_strong_id_range.h b/libs/libvtrutil/src/vtr_strong_id_range.h index 6728f13a174..c4cb036ddf4 100644 --- a/libs/libvtrutil/src/vtr_strong_id_range.h +++ b/libs/libvtrutil/src/vtr_strong_id_range.h @@ -1,7 +1,6 @@ -#ifndef _VTR_STRONG_ID_RANGE_H -#define _VTR_STRONG_ID_RANGE_H +#pragma once -#include +#include #include "vtr_assert.h" namespace vtr { @@ -187,5 +186,3 @@ class StrongIdRange { }; } //namespace vtr - -#endif /* _VTR_STRONG_ID_RANGE_H */ diff --git a/libs/libvtrutil/src/vtr_time.h b/libs/libvtrutil/src/vtr_time.h index 3f187e59288..9d837d8cdf4 100644 --- a/libs/libvtrutil/src/vtr_time.h +++ b/libs/libvtrutil/src/vtr_time.h @@ -1,5 +1,5 @@ -#ifndef VTR_TIME_H -#define VTR_TIME_H +#pragma once + #include #include @@ -95,5 +95,3 @@ class ScopedStartFinishTimer : public ScopedActionTimer { ~ScopedStartFinishTimer(); }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_token.cpp b/libs/libvtrutil/src/vtr_token.cpp index 1715e9f2381..9deb1c97af7 100644 --- a/libs/libvtrutil/src/vtr_token.cpp +++ b/libs/libvtrutil/src/vtr_token.cpp @@ -7,7 +7,6 @@ #include #include "vtr_assert.h" -#include "vtr_log.h" #include "vtr_util.h" #include "vtr_memory.h" #include "vtr_token.h" diff --git a/libs/libvtrutil/src/vtr_token.h b/libs/libvtrutil/src/vtr_token.h index 9556d6614ad..6084dff9621 100644 --- a/libs/libvtrutil/src/vtr_token.h +++ b/libs/libvtrutil/src/vtr_token.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Jason Luu @@ -5,9 +6,6 @@ * @brief Tokenizer */ -#ifndef TOKEN_H -#define TOKEN_H - ///@brief Token types enum e_token_type { TOKEN_NULL, @@ -36,5 +34,3 @@ bool checkTokenType(const t_token token, enum e_token_type token_type); void my_atof_2D(float** matrix, const int max_i, const int max_j, const char* instring); bool check_my_atof_2D(const int max_i, const int max_j, const char* instring, int* num_entries); - -#endif diff --git a/libs/libvtrutil/src/vtr_util.h b/libs/libvtrutil/src/vtr_util.h index 8463a3a6ea4..b9a08393c82 100644 --- a/libs/libvtrutil/src/vtr_util.h +++ b/libs/libvtrutil/src/vtr_util.h @@ -1,5 +1,4 @@ -#ifndef VTR_UTIL_H -#define VTR_UTIL_H +#pragma once #include #include @@ -150,5 +149,3 @@ bool exactly_k_conditions(int k, Conditions... conditions) { int get_pid(); } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_vec_id_set.h b/libs/libvtrutil/src/vtr_vec_id_set.h index 10dc10e0f0a..1b54172a86d 100644 --- a/libs/libvtrutil/src/vtr_vec_id_set.h +++ b/libs/libvtrutil/src/vtr_vec_id_set.h @@ -1,5 +1,4 @@ -#ifndef VTR_SET_H -#define VTR_SET_H +#pragma once #include #include @@ -103,5 +102,3 @@ class vec_id_set { }; } // namespace vtr - -#endif diff --git a/libs/libvtrutil/src/vtr_vector_map.h b/libs/libvtrutil/src/vtr_vector_map.h index 68200ad390e..337773ba12a 100644 --- a/libs/libvtrutil/src/vtr_vector_map.h +++ b/libs/libvtrutil/src/vtr_vector_map.h @@ -1,5 +1,5 @@ -#ifndef VTR_VECTOR_MAP -#define VTR_VECTOR_MAP +#pragma once + #include #include #include @@ -171,4 +171,3 @@ class vector_map { }; } // namespace vtr -#endif diff --git a/libs/libvtrutil/src/vtr_version.h b/libs/libvtrutil/src/vtr_version.h index f9bfaac14ea..c8a24bf33d6 100644 --- a/libs/libvtrutil/src/vtr_version.h +++ b/libs/libvtrutil/src/vtr_version.h @@ -1,5 +1,5 @@ -#ifndef VTR_VERSION_H -#define VTR_VERSION_H +#pragma once + #include namespace vtr { @@ -16,5 +16,3 @@ extern const char* COMPILER; extern const char* BUILD_TIMESTAMP; extern const char* BUILD_INFO; } // namespace vtr - -#endif diff --git a/odin_ii/CMakeLists.txt b/odin_ii/CMakeLists.txt index a5147fe0bba..22f3759728d 100644 --- a/odin_ii/CMakeLists.txt +++ b/odin_ii/CMakeLists.txt @@ -190,22 +190,5 @@ if (ODIN_USES_IPO) set_property(TARGET odin_ii APPEND PROPERTY LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS}) endif() -#add strict odin compiler flags, if set -if(VTR_ENABLE_STRICT_COMPILE) - message(STATUS "odin_ii: building with strict flags") - - set(ODIN_STRICT_COMPILE_FLAGS_TO_CHECK - #GCC-like - "-Werror" - ) - - foreach(flag ${ODIN_STRICT_COMPILE_FLAGS_TO_CHECK}) - message(STATUS "\tAdding CXX flag: ${flag}") - target_compile_options(libodin_ii PRIVATE ${flag}) - target_compile_options(odin_ii PRIVATE ${flag}) - target_link_libraries(odin_ii ${flag}) - endforeach() -endif() - install(TARGETS odin_ii libodin_ii DESTINATION bin) install(FILES ${LIB_HEADERS} DESTINATION include/libodin_ii) diff --git a/utils/fasm/src/fasm.cpp b/utils/fasm/src/fasm.cpp index 9a10808cdb1..3e70578ee6c 100644 --- a/utils/fasm/src/fasm.cpp +++ b/utils/fasm/src/fasm.cpp @@ -217,26 +217,73 @@ std::string FasmWriterVisitor::build_clb_prefix(const t_pb *pb, const t_pb_graph return clb_prefix; } -static const t_pb_graph_pin* is_node_used(const t_pb_routes &top_pb_route, const t_pb_graph_node* pb_graph_node) { - // Is the node used at all? - const t_pb_graph_pin* pin = nullptr; - for(int port_index = 0; port_index < pb_graph_node->num_output_ports; ++port_index) { - for(int pin_index = 0; pin_index < pb_graph_node->num_output_pins[port_index]; ++pin_index) { - pin = &pb_graph_node->output_pins[port_index][pin_index]; - if (top_pb_route.count(pin->pin_count_in_cluster) > 0 && top_pb_route[pin->pin_count_in_cluster].atom_net_id != AtomNetId::INVALID()) { - return pin; +/** + * @brief Returns true if the given pin is used (i.e. is not "open"). + */ +static bool is_pin_used(const t_pb_graph_pin* pin, const t_pb_routes &top_pb_route) { + // A pin is used if it has a pb_route that is connected to an atom net. + if (top_pb_route.count(pin->pin_count_in_cluster) == 0) + return false; + if (!top_pb_route[pin->pin_count_in_cluster].atom_net_id.is_valid()) + return false; + return true; +} + +/** + * @brief Returns the input pin for the given wire. + * + * Wires in VPR are a special primitive which is a LUT which acts like a wire + * pass-through. Only one input of this LUT should be used. + * + * @param top_pb_route + * The top pb route for the cluster that contains the wire. + * @param pb_graph_node + * The pb_graph_node of the wire primitive that we are getting the input + * pin for. + */ +static const t_pb_graph_pin* get_wire_input_pin(const t_pb_routes &top_pb_route, const t_pb_graph_node* pb_graph_node) { + const t_pb_graph_pin* wire_input_pin = nullptr; + for(int port_index = 0; port_index < pb_graph_node->num_input_ports; ++port_index) { + for(int pin_index = 0; pin_index < pb_graph_node->num_input_pins[port_index]; ++pin_index) { + const t_pb_graph_pin* pin = &pb_graph_node->input_pins[port_index][pin_index]; + if (is_pin_used(pin, top_pb_route)) { + VTR_ASSERT_MSG(wire_input_pin == nullptr, + "Wire found with more than 1 used input"); + wire_input_pin = pin; } } } - for(int port_index = 0; port_index < pb_graph_node->num_input_ports; ++port_index) { - for(int pin_index = 0; pin_index < pb_graph_node->num_input_pins[port_index]; ++pin_index) { - pin = &pb_graph_node->input_pins[port_index][pin_index]; - if (top_pb_route.count(pin->pin_count_in_cluster) > 0 && top_pb_route[pin->pin_count_in_cluster].atom_net_id != AtomNetId::INVALID()) { - return pin; + return wire_input_pin; +} + +/** + * @brief Returns true if the given wire is used. + * + * A wire is used if it has a used output pin. + * + * @param top_pb_route + * The top pb route for the cluster that contains the wire. + * @param pb_graph_node + * The pb_graph_node of the wire primitive that we are checking is used. + */ +static bool is_wire_used(const t_pb_routes &top_pb_route, const t_pb_graph_node* pb_graph_node) { + // A wire is used if it has a used output pin. + const t_pb_graph_pin* wire_output_pin = nullptr; + for(int port_index = 0; port_index < pb_graph_node->num_output_ports; ++port_index) { + for(int pin_index = 0; pin_index < pb_graph_node->num_output_pins[port_index]; ++pin_index) { + const t_pb_graph_pin* pin = &pb_graph_node->output_pins[port_index][pin_index]; + if (is_pin_used(pin, top_pb_route)) { + VTR_ASSERT_MSG(wire_output_pin == nullptr, + "Wire found with more than 1 used output"); + wire_output_pin = pin; } } } - return nullptr; + + if (wire_output_pin != nullptr) + return true; + + return false; } void FasmWriterVisitor::check_features(const t_metadata_dict *meta) const { @@ -278,14 +325,31 @@ void FasmWriterVisitor::visit_all_impl(const t_pb_routes &pb_routes, const t_pb* } if(mode != nullptr && std::string(mode->name) == "wire") { - auto io_pin = is_node_used(pb_routes, pb_graph_node); - if(io_pin != nullptr) { - const auto& route = pb_routes.at(io_pin->pin_count_in_cluster); + // Check if the wire is used. If the wire is unused (i.e. it does not connect + // to anything), it does not need to be created. + if (is_wire_used(pb_routes, pb_graph_node)) { + // Get the input pin of the LUT that feeds the wire. There should be one + // and only one. + const t_pb_graph_pin* wire_input_pin = get_wire_input_pin(pb_routes, pb_graph_node); + VTR_ASSERT_MSG(wire_input_pin != nullptr, + "Wire found with no used input pins"); + + // Get the route going into this pin. + const auto& route = pb_routes.at(wire_input_pin->pin_count_in_cluster); + + // Find the lut definition for the parent of this wire. const int num_inputs = *route.pb_graph_pin->parent_node->num_input_pins; const auto *lut_definition = find_lut(route.pb_graph_pin->parent_node); VTR_ASSERT(lut_definition->num_inputs == num_inputs); + // Create a wire implementation for the LUT. output_fasm_features(lut_definition->CreateWire(route.pb_graph_pin->pin_number)); + } else { + // If the wire is not used, ensure that the inputs to the wire are also + // unused. This is just a sanity check to ensure that all wires are + // either completely unused or have one input and one output. + VTR_ASSERT_MSG(get_wire_input_pin(pb_routes, pb_graph_node) == nullptr, + "Wire found with a used input pin, but no used output pin"); } } diff --git a/utils/fasm/src/parameters.cpp b/utils/fasm/src/parameters.cpp index 70fb3f6cab8..7877568c7d4 100644 --- a/utils/fasm/src/parameters.cpp +++ b/utils/fasm/src/parameters.cpp @@ -1,4 +1,5 @@ #include "parameters.h" +#include #include "vtr_assert.h" namespace fasm { diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt index 530928ac612..ffbec095445 100644 --- a/vpr/CMakeLists.txt +++ b/vpr/CMakeLists.txt @@ -227,24 +227,6 @@ else() message(ERROR "Unsupported VPR_PGO_CONFIG '${VPR_PGO_CONFIG}'") endif() -if (VTR_ENABLE_STRICT_COMPILE) - message(STATUS "VPR: building with strict flags") - - set(VPR_STRICT_COMPILE_FLAGS_TO_CHECK - #GCC-like - "-Werror" - # due to the pointer hackery in timing_driven_route_structs and BinaryHeap.heap_ - "-Wno-error=free-nonheap-object" - ) - - foreach(flag ${VPR_STRICT_COMPILE_FLAGS_TO_CHECK}) - message(STATUS "\tAdding CXX flag: ${flag}") - target_compile_options(libvpr PRIVATE ${flag}) - target_compile_options(vpr PRIVATE ${flag}) - target_link_libraries(vpr ${flag}) - endforeach() -endif() - # # Execution Engine Configuration # diff --git a/vpr/main.ui b/vpr/main.ui index babbccfc3e1..23d6b04928a 100644 --- a/vpr/main.ui +++ b/vpr/main.ui @@ -425,8 +425,6 @@ None Crit Path Flylines Crit Path Flylines Delays - Crit Path Routing - Crit Path Routing Delays diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index eeffe27e01a..0c7a408ab4a 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -1,14 +1,11 @@ #include "timing_reports.h" #include -#include #include "timing_reports.h" -#include "rr_graph.h" #include "tatum/TimingReporter.hpp" -#include "vtr_version.h" #include "vpr_types.h" #include "globals.h" diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index f8ae0c6fc67..ecb484d2e74 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -1,5 +1,4 @@ -#ifndef VPR_TIMING_REPORTS_H -#define VPR_TIMING_REPORTS_H +#pragma once #include "timing_info_fwd.h" #include "AnalysisDelayCalculator.h" @@ -45,5 +44,3 @@ void generate_hold_timing_stats(const std::string& prefix, void generate_net_timing_report(const std::string& prefix, const SetupHoldTimingInfo& timing_info, const AnalysisDelayCalculator& delay_calc); - -#endif diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index cd07b601198..ecb28d5f7e6 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -7,6 +7,7 @@ #include "analytical_placement_flow.h" #include +#include "PlacementDelayModelCreator.h" #include "PreClusterTimingManager.h" #include "analytical_solver.h" #include "ap_netlist.h" @@ -17,8 +18,11 @@ #include "gen_ap_netlist_from_atoms.h" #include "global_placer.h" #include "globals.h" +#include "netlist_fwd.h" #include "partial_legalizer.h" #include "partial_placement.h" +#include "physical_types.h" +#include "place_delay_model.h" #include "prepack.h" #include "user_place_constraints.h" #include "vpr_context.h" @@ -43,19 +47,23 @@ static void print_ap_netlist_stats(const APNetlist& netlist) { // Get the fanout information of nets size_t highest_fanout = 0; float average_fanout = 0.f; + unsigned net_count = 0; for (APNetId net_id : netlist.nets()) { + if (netlist.net_is_ignored(net_id)) + continue; size_t net_fanout = netlist.net_pins(net_id).size(); if (net_fanout > highest_fanout) highest_fanout = net_fanout; average_fanout += static_cast(net_fanout); + net_count++; } - average_fanout /= static_cast(netlist.nets().size()); + average_fanout /= static_cast(net_count); // Print the statistics VTR_LOG("Analytical Placement Netlist Statistics:\n"); VTR_LOG("\tBlocks: %zu\n", netlist.blocks().size()); VTR_LOG("\t\tMoveable Blocks: %zu\n", num_moveable_blocks); VTR_LOG("\t\tFixed Blocks: %zu\n", num_fixed_blocks); - VTR_LOG("\tNets: %zu\n", netlist.nets().size()); + VTR_LOG("\tNets: %zu\n", net_count); VTR_LOG("\t\tAverage Fanout: %.2f\n", average_fanout); VTR_LOG("\t\tHighest Fanout: %zu\n", highest_fanout); VTR_LOG("\tPins: %zu\n", netlist.pins().size()); @@ -122,7 +130,8 @@ static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, const AtomNetlist& atom_nlist, const APNetlist& ap_netlist, const Prepacker& prepacker, - const PreClusterTimingManager& pre_cluster_timing_manager, + PreClusterTimingManager& pre_cluster_timing_manager, + std::shared_ptr place_delay_model, const DeviceContext& device_ctx) { if (g_vpr_ctx.atom().flat_placement_info().valid) { VTR_LOG("Flat Placement is provided in the AP flow, skipping the Global Placement.\n"); @@ -142,8 +151,11 @@ static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, device_ctx.grid, device_ctx.logical_block_types, device_ctx.physical_tile_types, + device_ctx.arch->models, pre_cluster_timing_manager, + place_delay_model, ap_opts.ap_timing_tradeoff, + ap_opts.generate_mass_report, ap_opts.num_threads, ap_opts.log_verbosity); return global_placer->place(); @@ -181,6 +193,20 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { vpr_setup.PackerOpts.device_layout, vpr_setup.AnalysisOpts); + // Pre-compute the place delay model. This will be passed into the global + // placer to create a more accurate timing model. + std::shared_ptr place_delay_model; + if (pre_cluster_timing_manager.is_valid()) { + place_delay_model = PlacementDelayModelCreator::create_delay_model(vpr_setup.PlacerOpts, + vpr_setup.RouterOpts, + (const Netlist<>&)atom_nlist, + vpr_setup.RoutingArch, + vpr_setup.Segments, + device_ctx.arch->Chans, + device_ctx.arch->directs, + false /*is_flat*/); + } + // Run the Global Placer. const t_ap_opts& ap_opts = vpr_setup.APOpts; PartialPlacement p_placement = run_global_placer(ap_opts, @@ -188,6 +214,7 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { ap_netlist, prepacker, pre_cluster_timing_manager, + place_delay_model, device_ctx); // Verify that the partial placement is valid before running the full diff --git a/vpr/src/analytical_place/analytical_placement_flow.h b/vpr/src/analytical_place/analytical_placement_flow.h index 527fe241706..46cdd8e0f1d 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.h +++ b/vpr/src/analytical_place/analytical_placement_flow.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -5,8 +6,6 @@ * @brief Methods for running the Analytical Placement flow. */ -#pragma once - // Forward declarations struct t_vpr_setup; diff --git a/vpr/src/analytical_place/analytical_solver.cpp b/vpr/src/analytical_place/analytical_solver.cpp index 0c9467a3435..9bacadecdf2 100644 --- a/vpr/src/analytical_place/analytical_solver.cpp +++ b/vpr/src/analytical_place/analytical_solver.cpp @@ -114,9 +114,11 @@ AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist, float ap_timing_tradeoff, int log_verbosity) : netlist_(netlist) + , atom_netlist_(atom_netlist) , blk_id_to_row_id_(netlist.blocks().size(), APRowId::INVALID()) , row_id_to_blk_id_(netlist.blocks().size(), APBlockId::INVALID()) , net_weights_(netlist.nets().size(), 1.0f) + , ap_timing_tradeoff_(ap_timing_tradeoff) , log_verbosity_(log_verbosity) { // Get the number of moveable blocks in the netlist and create a unique // row ID from [0, num_moveable_blocks) for each moveable block in the @@ -136,19 +138,38 @@ AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist, num_moveable_blocks_++; } - if (pre_cluster_timing_manager.is_valid()) { - for (APNetId net_id : netlist.nets()) { - // Get the atom net associated with the given AP net. When - // constructing the AP netlist, we happen to set the name of each - // AP net to the same name as the atom net that generated them! - // TODO: Create a proper lookup structure to go from the AP Netlist - // back to the Atom Netlist. - AtomNetId atom_net_id = atom_netlist.find_net(netlist.net_name(net_id)); - VTR_ASSERT(atom_net_id.is_valid()); - float crit = pre_cluster_timing_manager.calc_net_setup_criticality(atom_net_id, atom_netlist); - - net_weights_[net_id] = ap_timing_tradeoff * crit + (1.0f - ap_timing_tradeoff); - } + update_net_weights(pre_cluster_timing_manager); +} + +void AnalyticalSolver::update_net_weights(const PreClusterTimingManager& pre_cluster_timing_manager) { + // If the pre-cluster timing manager has not been initialized (i.e. timing + // analysis is off), no need to update. + if (!pre_cluster_timing_manager.is_valid()) + return; + + // For each of the nets, update the net weights. + for (APNetId net_id : netlist_.nets()) { + // Note: To save time, we do not compute the weights of nets that we + // do not care about for AP. This leaves their weights at 1.0 just + // in case they are accidentally used. + if (netlist_.net_is_ignored(net_id)) + continue; + + AtomNetId atom_net_id = netlist_.net_atom_net(net_id); + VTR_ASSERT_SAFE(atom_net_id.is_valid()); + + float crit = pre_cluster_timing_manager.calc_net_setup_criticality(atom_net_id, atom_netlist_); + + // When optimizing for WL, the net weights are just set to 1 (meaning + // that we want to minimize the WL of nets). + // When optimizing for timing, the net weights are set to the timing + // criticality, which is based on the lowest slack of any edge belonging + // to this net. + // The intuition is that we care more about shrinking the wirelength of + // more critical connections than less critical ones. + // Use the AP timing trade-off term to linearly interpolate between these + // weighting terms. + net_weights_[net_id] = ap_timing_tradeoff_ * crit + (1.0f - ap_timing_tradeoff_); } } @@ -225,7 +246,11 @@ static inline void add_connection_to_system(size_t src_row_id, void QPHybridSolver::init_linear_system() { // Count the number of star nodes that the netlist will have. size_t num_star_nodes = 0; + unsigned num_nets = 0; for (APNetId net_id : netlist_.nets()) { + if (netlist_.net_is_ignored(net_id)) + continue; + num_nets++; if (netlist_.net_pins(net_id).size() > star_num_pins_threshold) num_star_nodes++; } @@ -248,13 +273,14 @@ void QPHybridSolver::init_linear_system() { // TODO: This can be made more space-efficient by getting the average fanout // of all nets in the APNetlist. Ideally this should be not enough // space, but be within a constant factor. - size_t num_nets = netlist_.nets().size(); tripletList.reserve(num_nets); // Create the connections using a hybrid connection model of the star and // clique connnection models. size_t star_node_offset = 0; for (APNetId net_id : netlist_.nets()) { + if (netlist_.net_is_ignored(net_id)) + continue; size_t num_pins = netlist_.net_pins(net_id).size(); VTR_ASSERT_DEBUG(num_pins > 1); @@ -772,6 +798,8 @@ void B2BSolver::init_linear_system(PartialPlacement& p_placement) { triplet_list_y.reserve(num_nets); for (APNetId net_id : netlist_.nets()) { + if (netlist_.net_is_ignored(net_id)) + continue; size_t num_pins = netlist_.net_pins(net_id).size(); VTR_ASSERT_SAFE_MSG(num_pins > 1, "net must have at least 2 pins"); diff --git a/vpr/src/analytical_place/analytical_solver.h b/vpr/src/analytical_place/analytical_solver.h index 2209349fdaf..f5c4fde1924 100644 --- a/vpr/src/analytical_place/analytical_solver.h +++ b/vpr/src/analytical_place/analytical_solver.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer and Robert Luo @@ -6,8 +7,6 @@ * to define the functionality of all solvers used in the AP flow. */ -#pragma once - #include #include "ap_flow_enums.h" #include "ap_netlist.h" @@ -29,7 +28,7 @@ #endif // EIGEN_INSTALLED // Forward declarations -class PartialPlacement; +struct PartialPlacement; class APNetlist; class AtomNetlist; class PreClusterTimingManager; @@ -96,11 +95,24 @@ class AnalyticalSolver { */ virtual void print_statistics() = 0; + /** + * @brief Update the net weights according to the criticality of the nets. + * + * @param pre_cluster_timing_manager + * The timing manager which manages the criticalities of the nets. + */ + void update_net_weights(const PreClusterTimingManager& pre_cluster_timing_manager); + protected: /// @brief The APNetlist the solver is optimizing over. It is implied that /// the netlist is not being modified during global placement. const APNetlist& netlist_; + /// @brief The Atom netlist the solver is optimizing over. It is implied + /// that the atom netlist is not being modified during global + /// placement. + const AtomNetlist& atom_netlist_; + /// @brief The number of moveable blocks in the netlist. This is helpful /// when allocating matrices. size_t num_moveable_blocks_ = 0; @@ -125,6 +137,10 @@ class AnalyticalSolver { /// between 0 and 1. vtr::vector net_weights_; + /// @brief The AP timing tradeoff term used during global placement. Decides + /// how much the solver cares about timing vs wirelength. + float ap_timing_tradeoff_; + /// @brief The verbosity of log messages in the Analytical Solver. int log_verbosity_; }; diff --git a/vpr/src/analytical_place/ap_flow_enums.h b/vpr/src/analytical_place/ap_flow_enums.h index 91c1407059d..da47927d5d1 100644 --- a/vpr/src/analytical_place/ap_flow_enums.h +++ b/vpr/src/analytical_place/ap_flow_enums.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -5,8 +6,6 @@ * @brief Enumerations used by the Analytical Placement Flow. */ -#pragma once - /** * @brief The type of an Analytical Solver. * diff --git a/vpr/src/analytical_place/ap_mass_report.cpp b/vpr/src/analytical_place/ap_mass_report.cpp new file mode 100644 index 00000000000..8202fca5509 --- /dev/null +++ b/vpr/src/analytical_place/ap_mass_report.cpp @@ -0,0 +1,550 @@ +/** + * @file + * @author Alex Singer + * @date May 2025 + * @brief Implementation of the AP mass report generator. + */ + +#include "ap_mass_report.h" +#include +#include +#include +#include +#include +#include +#include "ap_netlist.h" +#include "ap_netlist_fwd.h" +#include "globals.h" +#include "logic_types.h" +#include "physical_types.h" +#include "physical_types_util.h" +#include "primitive_dim_manager.h" +#include "primitive_vector.h" +#include "vpr_context.h" +#include "vpr_error.h" +#include "vtr_time.h" +#include "vtr_vector.h" + +namespace { + +/** + * @brief A node in a printing tree. + */ +struct PrintingTreeNode { + /// @brief The name of this node. This will be printed when the tree is printed. + std::string name; + /// @brief The children of this node in the tree. + std::vector children; +}; + +/** + * @brief A printing tree. This tree contains basic information which will be + * used to print data in a good-looking form. + */ +struct PrintingTree { + /// @brief The root node of the tree. + PrintingTreeNode root; +}; + +/** + * @brief Recursively print the given tree node. + * + * @param node + * The node to print. + * @param os + * The output file stream to print the node to. + * @param prefix + * The prefix that all children of this node will print before their names. + */ +void print_tree_node_recur(const PrintingTreeNode& node, + std::ofstream& os, + const std::string& prefix) { + // Print the name of the node here and start a new line. + os << node.name << "\n"; + + // Print the children of this node. + size_t num_children = node.children.size(); + for (size_t child_idx = 0; child_idx < num_children; child_idx++) { + if (child_idx != num_children - 1) { + // If this is not the last child, print a vertical line which will + // be connected by the next child. This will be printed just before + // the node name of this child. + os << prefix << "├── "; + // Print the child node and update the prefix for any of its children. + // This prefix will connect the lines in a good looking way. + print_tree_node_recur(node.children[child_idx], os, prefix + "│ "); + } else { + // If this is the last child, we print an L shape to signify that + // there are no further children. + os << prefix << "└── "; + // Print the child node, and set the prefix to basically just be + // an indent. + print_tree_node_recur(node.children[child_idx], os, prefix + " "); + } + } +} + +/** + * @brief Helper function to print an entire printing tree. + * + * This method begins the recursion of printing using the proper prefix. + * + * @param tree + * The tree to print. + * @param os + * The output file stream to print to. + */ +void print_tree(const PrintingTree& tree, std::ofstream& os) { + print_tree_node_recur(tree.root, os, ""); +} + +/** + * @brief Generate the printing tree node for the given pb type. + * + * @param pb_type + * The pb type to generate the tree node for. + * @param models + * The logical models in the architecture. + */ +PrintingTreeNode gen_pb_printing_tree_node(const t_pb_type* pb_type, const LogicalModels& models); + +/** + * @brief Generate the printing tree node for the given mode. + * + * @param mode + * The mode to generate the tree node for. + * @param models + * The logical models in the architecture. + */ +PrintingTreeNode gen_mode_printing_tree_node(const t_mode& mode, const LogicalModels& models) { + // Create the node with the mode name. + PrintingTreeNode mode_node; + mode_node.name = std::string(mode.name) + " (mode)"; + + // Create the children. There will be one child for each pb in this mode. + mode_node.children.reserve(mode.num_pb_type_children); + for (int pb_child_idx = 0; pb_child_idx < mode.num_pb_type_children; pb_child_idx++) { + // Generate the child pb's node. + const t_pb_type& pb_type = mode.pb_type_children[pb_child_idx]; + PrintingTreeNode pb_node = gen_pb_printing_tree_node(&pb_type, models); + // Insert the node into the list of children. + mode_node.children.emplace_back(std::move(pb_node)); + } + + return mode_node; +} + +PrintingTreeNode gen_pb_printing_tree_node(const t_pb_type* pb_type, const LogicalModels& models) { + // Create the node with the pb name and the number of pbs. + PrintingTreeNode pb_node; + pb_node.name = std::string(pb_type->name) + " [" + std::to_string(pb_type->num_pb) + "]"; + if (!pb_type->is_primitive()) { + pb_node.name += " (pb_type)"; + } else { + // If this pb type is a primitive, print the name of the model as well. + LogicalModelId model_id = pb_type->model_id; + std::string model_name = models.model_name(model_id); + pb_node.name += " (primitive pb_type | model: " + model_name + ")"; + } + + // Create the children. There will be one child for each mode of this pb. + pb_node.children.reserve(pb_type->num_modes); + for (int mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { + // Generate the child mode's node. + const t_mode& mode = pb_type->modes[mode_idx]; + PrintingTreeNode mode_node = gen_mode_printing_tree_node(mode, models); + // Insert the node into the list of children. + pb_node.children.emplace_back(std::move(mode_node)); + } + + return pb_node; +} + +/** + * @brief Print the logical block type graph. + * + * This graph is a forest, as such we can print the forest in a pretty way in + * a text file. + */ +void print_logical_block_graph(std::ofstream& os, + const std::vector& logical_block_types, + const LogicalModels& models) { + // Generate the internal complex block trees. + // This is a DFS traversal of each complex block root in the forest. + os << "=================================================================\n"; + os << "Logical (Complex) Block Graph:\n"; + os << "=================================================================\n"; + os << "\n"; + + for (const t_logical_block_type& block_type : logical_block_types) { + // Set the root of the complex block tree to be the name of this logical + // block type. + PrintingTree complex_block_tree; + complex_block_tree.root.name = block_type.name + " (root logical block)"; + + // If this block has a pb type, generate the pb printing node (including + // its children) and add to the list of children. + if (block_type.pb_type != nullptr) { + PrintingTreeNode root_pb_node = gen_pb_printing_tree_node(block_type.pb_type, models); + complex_block_tree.root.children.emplace_back(std::move(root_pb_node)); + } + + // Print the tree to the file. + print_tree(complex_block_tree, os); + os << "\n"; + } +} + +/** + * @brief Print information on the physical tiles and how they relate to the + * logical block types. + */ +void print_physical_tiles(std::ofstream& os, + const std::vector& physical_tile_types) { + // Generate the physical tile relationships with the complex blocks. + os << "=================================================================\n"; + os << "Physical Tile Graph:\n"; + os << "=================================================================\n"; + os << "\n"; + + for (const t_physical_tile_type& tile_type : physical_tile_types) { + // Create a printing tree with a root name of the tile. + PrintingTree tile_tree; + tile_tree.root.name = tile_type.name + " (tile)"; + + // Create a child for each sub tile. + tile_tree.root.children.reserve(tile_type.sub_tiles.size()); + for (const auto& sub_tile : tile_type.sub_tiles) { + // Create a sub tile node with the name of the sub tile and the capacity. + PrintingTreeNode sub_tile_node; + sub_tile_node.name = sub_tile.name + " [" + std::to_string(sub_tile.capacity.total()) + "] (sub-tile)"; + + // Create a child for each equivalent site. + sub_tile_node.children.reserve(sub_tile.equivalent_sites.size()); + for (const auto& block_type : sub_tile.equivalent_sites) { + PrintingTreeNode block_type_node; + block_type_node.name = block_type->name + " (equiv-site)"; + + // Add this equivalent site to the parent sub-tile. + sub_tile_node.children.push_back(std::move(block_type_node)); + } + + // Add this sub-tile to the tile node. + tile_tree.root.children.push_back(std::move(sub_tile_node)); + } + + // Print the tree for this tile. + print_tree(tile_tree, os); + os << "\n"; + } +} + +/** + * @brief Prints all of the non-zero dimensions of the given primitive vector. + * + * @param os + * The output file stream to print the primtive vector to. + * @param primitive_vec + * The primitive vector to print. + * @param dim_manager + * The manager class which handles all of the dims of this vector. + * @param prefix + * The prefix to print ahead of each entry in the primitive vector print. + */ +void print_primitive_vector(std::ofstream& os, + const PrimitiveVector& primitive_vec, + const PrimitiveDimManager& dim_manager, + const std::string& prefix) { + std::vector contained_dims = primitive_vec.get_non_zero_dims(); + + // Get the max name length of the contained dim name for pretty printing. + size_t max_model_name_len = 0; + for (PrimitiveVectorDim dim : contained_dims) { + std::string dim_name = dim_manager.get_dim_name(dim); + max_model_name_len = std::max(max_model_name_len, + dim_name.size()); + } + + // Print the capacity of each dim. + for (PrimitiveVectorDim dim : contained_dims) { + std::string dim_name = dim_manager.get_dim_name(dim); + os << prefix << std::setw(max_model_name_len) << dim_name; + os << ": " << primitive_vec.get_dim_val(dim); + os << "\n"; + } +} + +/** + * @brief Print information of the capacity of each logical block type. + */ +void print_logical_block_type_capacities(std::ofstream& os, + const std::vector& logical_block_types, + const std::vector& logical_block_type_capacities, + const PrimitiveDimManager& dim_manager) { + os << "=================================================================\n"; + os << "Logical Block Type Capacities:\n"; + os << "=================================================================\n"; + os << "\n"; + + // For each logical block type, print the capacity (in primitive-vector + // space). + for (const t_logical_block_type& block_type : logical_block_types) { + // Print the name of the block. + os << block_type.name << ":\n"; + + // Print the capacity of the logical block type. + const PrimitiveVector& cap = logical_block_type_capacities[block_type.index]; + print_primitive_vector(os, cap, dim_manager, "\t"); + os << "\n"; + } +} + +/** + * @brief Print information of the capacity of each physical tile on the device. + */ +void print_physical_tile_type_capacities(std::ofstream& os, + const std::vector& physical_tile_types, + const std::vector& physical_tile_type_capacities, + const PrimitiveDimManager& dim_manager) { + os << "=================================================================\n"; + os << "Physical Tile Type Capacities:\n"; + os << "=================================================================\n"; + os << "\n"; + + // For each physical tile type, print the capacity (in primitive-vector + // space). + for (const t_physical_tile_type& tile_type : physical_tile_types) { + // Print the name of the tile. + os << tile_type.name << ":\n"; + + // Print the capacity of the tile type. + const PrimitiveVector& cap = physical_tile_type_capacities[tile_type.index]; + print_primitive_vector(os, cap, dim_manager, "\t"); + os << "\n"; + } +} + +/** + * @brief Helper method for computing the total primitive vector mass of the + * given AP netlist. + */ +PrimitiveVector calc_total_netlist_mass(const APNetlist& ap_netlist, + const vtr::vector& block_mass) { + PrimitiveVector total_netlist_mass; + for (APBlockId ap_blk_id : ap_netlist.blocks()) { + total_netlist_mass += block_mass[ap_blk_id]; + } + + return total_netlist_mass; +} + +/** + * @brief Print information on how much mass the AP netlist uses relative to + * the overall device. + */ +void print_netlist_mass_utilization(std::ofstream& os, + const APNetlist& ap_netlist, + const vtr::vector& block_mass, + const std::vector& physical_tile_type_capacities, + const PrimitiveDimManager& dim_manager, + const DeviceGrid& device_grid, + const LogicalModels& models) { + os << "=================================================================\n"; + os << "Netlist Mass Utilization:\n"; + os << "=================================================================\n"; + os << "\n"; + + // Get the capacity of all the physical tiles in the grid. + PrimitiveVector total_grid_capacity; + size_t grid_width = device_grid.width(); + size_t grid_height = device_grid.height(); + size_t layer = 0; + for (size_t x = 0; x < grid_width; x++) { + for (size_t y = 0; y < grid_height; y++) { + t_physical_tile_loc tile_loc(x, y, layer); + if (device_grid.get_width_offset(tile_loc) != 0 || device_grid.get_height_offset(tile_loc) != 0) + continue; + + auto tile_type = device_grid.get_physical_type(tile_loc); + total_grid_capacity += physical_tile_type_capacities[tile_type->index]; + } + } + + // Get the mass of all blocks in the netlist. + PrimitiveVector total_netlist_mass = calc_total_netlist_mass(ap_netlist, block_mass); + + PrimitiveVector netlist_per_dim_counts; + for (APBlockId ap_blk_id : ap_netlist.blocks()) { + for (PrimitiveVectorDim dim : block_mass[ap_blk_id].get_non_zero_dims()) { + netlist_per_dim_counts.add_val_to_dim(1, dim); + } + } + + // Get the max string length of any model to make the printing prettier. + size_t max_dim_name_len = 0; + for (PrimitiveVectorDim dim : dim_manager.dims()) { + std::string dim_name = dim_manager.get_dim_name(dim); + max_dim_name_len = std::max(max_dim_name_len, dim_name.size()); + } + + // Print a breakdown of the mass utilization of the netlist. + os << std::setw(max_dim_name_len) << "Dim"; + os << ": Total Netlist Mass | Total Grid Mass | Mass Utilization\n"; + for (LogicalModelId model_id : models.all_models()) { + PrimitiveVectorDim dim = dim_manager.get_model_dim(model_id); + std::string dim_name = dim_manager.get_dim_name(dim); + float dim_netlist_mass = total_netlist_mass.get_dim_val(dim); + float dim_grid_capacity = total_grid_capacity.get_dim_val(dim); + os << std::setw(max_dim_name_len) << dim_name; + os << ": " << std::setw(18) << dim_netlist_mass; + os << " | " << std::setw(15) << dim_grid_capacity; + os << " | " << std::setw(16) << dim_netlist_mass / dim_grid_capacity; + os << "\n"; + } + os << "\n"; + + os << std::setw(max_dim_name_len) << "Dim"; + os << ": Total Netlist Mass | Number of Blocks | Average Mass per Block\n"; + for (LogicalModelId model_id : models.all_models()) { + PrimitiveVectorDim dim = dim_manager.get_model_dim(model_id); + std::string dim_name = dim_manager.get_dim_name(dim); + float dim_netlist_mass = total_netlist_mass.get_dim_val(dim); + float num_blocks = netlist_per_dim_counts.get_dim_val(dim); + float average_mass_per_block = 0.0f; + if (num_blocks > 0.0f) { + average_mass_per_block = dim_netlist_mass / num_blocks; + } + os << std::setw(max_dim_name_len) << dim_name; + os << ": " << std::setw(18) << dim_netlist_mass; + os << " | " << std::setw(16) << num_blocks; + os << " | " << std::setw(22) << average_mass_per_block; + os << "\n"; + } + os << "\n"; +} + +/** + * @brief Uses the mass of the netlist and the mass of the logical block types + * to predict the device utilization for the given device grid. + */ +void print_expected_device_utilization(std::ofstream& os, + const APNetlist& ap_netlist, + const vtr::vector& block_mass, + const std::vector& logical_block_types, + const std::vector& logical_block_type_capacities, + const DeviceGrid& device_grid) { + os << "=================================================================\n"; + os << "Expected Device Utilization:\n"; + os << "=================================================================\n"; + os << "\n"; + + // Get the total mass of the netlist. + PrimitiveVector total_netlist_mass = calc_total_netlist_mass(ap_netlist, block_mass); + + // Get the expected number of instances of each logical block type. + std::vector num_type_instances(logical_block_types.size(), 0); + for (const t_logical_block_type& block_type : logical_block_types) { + // For each logical block type, estimate the number of blocks of that type + // We can estimate this value as being the maximum required number of + // instances to support the most utilized model. + const PrimitiveVector block_type_cap = logical_block_type_capacities[block_type.index]; + unsigned num_blocks_of_this_type = 0; + for (PrimitiveVectorDim dim : block_type_cap.get_non_zero_dims()) { + float netlist_model_mass = total_netlist_mass.get_dim_val(dim); + float model_mass_per_block = block_type_cap.get_dim_val(dim); + unsigned num_blocks_needed_for_model = std::ceil(netlist_model_mass / model_mass_per_block); + num_blocks_of_this_type = std::max(num_blocks_of_this_type, num_blocks_needed_for_model); + } + + num_type_instances[block_type.index] = num_blocks_of_this_type; + } + + // Get the max logical block type name length for pretty printing. + size_t max_logical_block_name_len = 0; + for (const t_logical_block_type& block_type : logical_block_types) { + max_logical_block_name_len = std::max(max_logical_block_name_len, block_type.name.size()); + } + + // Print the expected number of logical blocks and the expected block utilization. + // Note: These may be innacurate if a model appears in multiple different + // logical blocks. + // TODO: Investigate resolving this issue. + os << "Expected number of logical blocks:\n"; + for (const t_logical_block_type& block_type : logical_block_types) { + if (block_type.is_empty()) + continue; + os << "\t" << std::setw(max_logical_block_name_len) << block_type.name; + os << ": " << num_type_instances[block_type.index]; + os << "\n"; + } + os << "\n"; + + os << "Expected block utilization:\n"; + for (const t_logical_block_type& block_type : logical_block_types) { + if (block_type.is_empty()) + continue; + // Get the number of instances of this logical block in this device. + size_t num_inst = device_grid.num_instances(pick_physical_type(&block_type), -1); + + // Estimate the utilization as being the expected number of instances + // divided by the number of instances possible on the device. + float util = 0.0f; + if (num_inst > 0) { + util = static_cast(num_type_instances[block_type.index]); + util /= static_cast(num_inst); + } + os << "\t" << std::setw(max_logical_block_name_len) << block_type.name; + os << ": " << util; + os << "\n"; + } + os << "\n"; +} + +} // namespace + +void generate_ap_mass_report(const std::vector& logical_block_type_capacities, + const std::vector& physical_tile_type_capacities, + const vtr::vector& block_mass, + const PrimitiveDimManager& dim_manager, + const APNetlist& ap_netlist) { + + vtr::ScopedStartFinishTimer timer("Generating AP Mass Report"); + + // Load device data which is used to calculate the data in the report. + const DeviceContext& device_ctx = g_vpr_ctx.device(); + const std::vector& physical_tile_types = device_ctx.physical_tile_types; + const std::vector& logical_block_types = device_ctx.logical_block_types; + const LogicalModels& models = device_ctx.arch->models; + const DeviceGrid& device_grid = device_ctx.grid; + + // Open the AP mass report file as an output file stream. + std::string mass_report_file_name = "ap_mass.rpt"; + std::ofstream os(mass_report_file_name); + if (!os.is_open()) { + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Unable to open AP mass report file"); + return; + } + + // Print the logical block graph. + print_logical_block_graph(os, logical_block_types, models); + + // Print information on the physical tiles. + print_physical_tiles(os, physical_tile_types); + + // TODO: Print a lookup between the model names and IDs and Primitive Dim + + // Print the computed capacities of each logical block type. + print_logical_block_type_capacities(os, logical_block_types, logical_block_type_capacities, dim_manager); + + // Print the computed capacities of each physical tile type. + print_physical_tile_type_capacities(os, physical_tile_types, physical_tile_type_capacities, dim_manager); + + // Print information on how much mass is utilized by the netlist relative + // to the device. + print_netlist_mass_utilization(os, ap_netlist, block_mass, physical_tile_type_capacities, dim_manager, device_grid, models); + + // Print the expected device utilization, given the mass of the netlist + // and the capacity of the device grid. + print_expected_device_utilization(os, ap_netlist, block_mass, logical_block_types, logical_block_type_capacities, device_grid); +} diff --git a/vpr/src/analytical_place/ap_mass_report.h b/vpr/src/analytical_place/ap_mass_report.h new file mode 100644 index 00000000000..bfc0948a44d --- /dev/null +++ b/vpr/src/analytical_place/ap_mass_report.h @@ -0,0 +1,35 @@ +#pragma once +/** + * @file + * @author Alex Singer + * @date May 2025 + * @brief Methods for generating mass reports. Mass reports contain information + * on the AP partial legalizer's internal representation of mass for + * primitives and tiles. + */ + +#include +#include "ap_netlist_fwd.h" +#include "primitive_vector_fwd.h" +#include "vtr_vector.h" + +// Forward declarations +class PrimitiveDimManager; + +/** + * @brief Generate a mass report for the given AP netlist with the given block + * masses and tile / logic block capacities. + * + * @param logical_block_type_capacities + * The primitive-vector capacity of each logical block on the device. + * @param physical_tile_type_capacities + * The primitive-vector capacity of each tile on the device. + * @param block_mass + * The mass of each AP block in the AP netlist. + * @param ap_netlist + */ +void generate_ap_mass_report(const std::vector& logical_block_type_capacities, + const std::vector& physical_tile_type_capacities, + const vtr::vector& block_mass, + const PrimitiveDimManager& dim_manager, + const APNetlist& ap_netlist); diff --git a/vpr/src/analytical_place/ap_netlist.cpp b/vpr/src/analytical_place/ap_netlist.cpp index 26c80119b9a..83435ead484 100644 --- a/vpr/src/analytical_place/ap_netlist.cpp +++ b/vpr/src/analytical_place/ap_netlist.cpp @@ -7,6 +7,7 @@ #include "ap_netlist.h" #include +#include "atom_netlist_fwd.h" #include "netlist_fwd.h" #include "netlist_utils.h" #include "prepack.h" @@ -34,6 +35,24 @@ const APFixedBlockLoc& APNetlist::block_loc(const APBlockId id) const { return block_locs_[id]; } +/* + * Pins + */ +AtomPinId APNetlist::pin_atom_pin(const APPinId id) const { + VTR_ASSERT_SAFE(valid_pin_id(id)); + + return pin_atom_pin_[id]; +} + +/* + * Nets + */ +AtomNetId APNetlist::net_atom_net(const APNetId id) const { + VTR_ASSERT_SAFE(valid_net_id(id)); + + return net_atom_net_[id]; +} + /* * Mutators */ @@ -93,9 +112,12 @@ APPortId APNetlist::create_port(const APBlockId blk_id, const std::string& name, return port_id; } -APPinId APNetlist::create_pin(const APPortId port_id, BitIndex port_bit, const APNetId net_id, const PinType pin_type_, bool is_const) { +APPinId APNetlist::create_pin(const APPortId port_id, BitIndex port_bit, const APNetId net_id, const PinType pin_type_, const AtomPinId atom_pin_id, bool is_const) { APPinId pin_id = Netlist::create_pin(port_id, port_bit, net_id, pin_type_, is_const); + // Initialize the pin data. + pin_atom_pin_.insert(pin_id, atom_pin_id); + // Check post-conditions: size VTR_ASSERT(validate_pin_sizes()); @@ -107,9 +129,12 @@ APPinId APNetlist::create_pin(const APPortId port_id, BitIndex port_bit, const A return pin_id; } -APNetId APNetlist::create_net(const std::string& name) { +APNetId APNetlist::create_net(const std::string& name, const AtomNetId atom_net_id) { APNetId net_id = Netlist::create_net(name); + // Initialize the net data. + net_atom_net_.insert(net_id, atom_net_id); + // Check post-conditions: size VTR_ASSERT(validate_net_sizes()); @@ -132,12 +157,12 @@ void APNetlist::clean_ports_impl(const vtr::vector_map& /*po // Unused } -void APNetlist::clean_pins_impl(const vtr::vector_map& /*pin_id_map*/) { - // Unused +void APNetlist::clean_pins_impl(const vtr::vector_map& pin_id_map) { + pin_atom_pin_ = clean_and_reorder_values(pin_atom_pin_, pin_id_map); } -void APNetlist::clean_nets_impl(const vtr::vector_map& /*net_id_map*/) { - // Unused +void APNetlist::clean_nets_impl(const vtr::vector_map& net_id_map) { + net_atom_net_ = clean_and_reorder_values(net_atom_net_, net_id_map); } void APNetlist::rebuild_block_refs_impl(const vtr::vector_map& /*pin_id_map*/, @@ -162,6 +187,12 @@ void APNetlist::shrink_to_fit_impl() { block_molecules_.shrink_to_fit(); block_mobilities_.shrink_to_fit(); block_locs_.shrink_to_fit(); + + // Pin data + pin_atom_pin_.shrink_to_fit(); + + // Net data + net_atom_net_.shrink_to_fit(); } void APNetlist::remove_block_impl(const APBlockId /*blk_id*/) { @@ -198,12 +229,14 @@ bool APNetlist::validate_port_sizes_impl(size_t /*num_ports*/) const { return true; } -bool APNetlist::validate_pin_sizes_impl(size_t /*num_pins*/) const { - // No AP-specific pin data to check +bool APNetlist::validate_pin_sizes_impl(size_t num_pins) const { + if (pin_atom_pin_.size() != num_pins) + return false; return true; } -bool APNetlist::validate_net_sizes_impl(size_t /*num_nets*/) const { - // No AP-specific net data to check +bool APNetlist::validate_net_sizes_impl(size_t num_nets) const { + if (net_atom_net_.size() != num_nets) + return false; return true; } diff --git a/vpr/src/analytical_place/ap_netlist.h b/vpr/src/analytical_place/ap_netlist.h index 1bfe8c5e49b..a5ead901864 100644 --- a/vpr/src/analytical_place/ap_netlist.h +++ b/vpr/src/analytical_place/ap_netlist.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -18,9 +19,8 @@ * unused by Analytical Placement are ignored. */ -#pragma once - #include +#include "atom_netlist_fwd.h" #include "netlist.h" #include "ap_netlist_fwd.h" #include "prepack.h" @@ -91,6 +91,20 @@ class APNetlist : public Netlist { /// This method should not be used if the block is moveable. const APFixedBlockLoc& block_loc(const APBlockId id) const; + /* + * Pins + */ + + /// @brief Returns the atom pin that corresponds with the given AP pin. + AtomPinId pin_atom_pin(const APPinId id) const; + + /* + * Nets + */ + + /// @brief Returns the atom net that corresponds with the given AP net. + AtomNetId net_atom_net(const APNetId id) const; + public: // Public Mutators /* * Note: all create_*() functions will silently return the appropriate ID @@ -130,17 +144,19 @@ class APNetlist : public Netlist { * @param port_bit The bit index of the pin in the port * @param net_id The net the pin drives/sinks * @param pin_type The type of the pin (driver/sink) + * @param atom_pin_id The atom pin that this pin is modeling. * @param is_const Indicates whether the pin holds a constant value (e.g. * vcc/gnd) */ - APPinId create_pin(const APPortId port_id, BitIndex port_bit, const APNetId net_id, const PinType pin_type, bool is_const = false); + APPinId create_pin(const APPortId port_id, BitIndex port_bit, const APNetId net_id, const PinType pin_type, const AtomPinId atom_pin_id, bool is_const = false); /** * @brief Create an empty, or return an existing net in the netlist * * @param name The unique name of the net + * @param atom_net_id The atom net that this net is modeling. */ - APNetId create_net(const std::string& name); + APNetId create_net(const std::string& name, const AtomNetId atom_net_id); private: // Private Members /* @@ -187,4 +203,8 @@ class APNetlist : public Netlist { /// @brief Location of each block (if fixed). /// NOTE: This vector will likely be quite sparse. vtr::vector_map block_locs_; + /// @brief Atom pin associated with each AP pin. + vtr::vector_map pin_atom_pin_; + /// @brief Atom net associated with each AP net. + vtr::vector_map net_atom_net_; }; diff --git a/vpr/src/analytical_place/ap_netlist_fwd.h b/vpr/src/analytical_place/ap_netlist_fwd.h index ede36cf6a07..1679f1f9d11 100644 --- a/vpr/src/analytical_place/ap_netlist_fwd.h +++ b/vpr/src/analytical_place/ap_netlist_fwd.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -7,8 +8,6 @@ * Forward declares the APNetlist class, and defines common types used by it. */ -#pragma once - #include "netlist_fwd.h" #include "vtr_strong_id.h" diff --git a/vpr/src/analytical_place/detailed_placer.h b/vpr/src/analytical_place/detailed_placer.h index 46f769a4d22..1fd11b75a9c 100644 --- a/vpr/src/analytical_place/detailed_placer.h +++ b/vpr/src/analytical_place/detailed_placer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -6,8 +7,6 @@ * and placement and optimizes them while remaining legal. */ -#pragma once - #include #include "ap_flow_enums.h" #include "clustered_netlist_utils.h" diff --git a/vpr/src/analytical_place/flat_placement_bins.h b/vpr/src/analytical_place/flat_placement_bins.h index e94ed958312..1aefdd2520b 100644 --- a/vpr/src/analytical_place/flat_placement_bins.h +++ b/vpr/src/analytical_place/flat_placement_bins.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -8,8 +9,6 @@ * FPGA. */ -#pragma once - #include #include "ap_netlist.h" #include "vtr_assert.h" diff --git a/vpr/src/analytical_place/flat_placement_density_manager.cpp b/vpr/src/analytical_place/flat_placement_density_manager.cpp index f4c37b191c8..2899981943e 100644 --- a/vpr/src/analytical_place/flat_placement_density_manager.cpp +++ b/vpr/src/analytical_place/flat_placement_density_manager.cpp @@ -12,9 +12,12 @@ #include "atom_netlist.h" #include "flat_placement_bins.h" #include "flat_placement_mass_calculator.h" +#include "logic_types.h" #include "partial_placement.h" #include "physical_types.h" #include "prepack.h" +#include "primitive_dim_manager.h" +#include "primitive_vector.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_vector.h" @@ -48,10 +51,11 @@ FlatPlacementDensityManager::FlatPlacementDensityManager(const APNetlist& ap_net const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, + const LogicalModels& models, int log_verbosity) : ap_netlist_(ap_netlist) , bins_(ap_netlist) - , mass_calculator_(ap_netlist, prepacker, atom_netlist, logical_block_types, physical_tile_types, log_verbosity) + , mass_calculator_(ap_netlist, prepacker, atom_netlist, logical_block_types, physical_tile_types, models, log_verbosity) , log_verbosity_(log_verbosity) { // Initialize the bin spatial lookup object. size_t num_layers, width, height; @@ -96,12 +100,24 @@ FlatPlacementDensityManager::FlatPlacementDensityManager(const APNetlist& ap_net } } + // Get the used primitive dims. This is used to ignore the unused dims during + // partial legalization. + const PrimitiveDimManager& dim_manager = mass_calculator_.get_dim_manager(); + for (AtomBlockId blk_id : atom_netlist.blocks()) { + LogicalModelId model_id = atom_netlist.block_model(blk_id); + PrimitiveVectorDim dim = dim_manager.get_model_dim(model_id); + used_dims_mask_.set_dim_val(dim, 1); + } + // Initialize the bin capacities to the mass capacity of the physical tile // this bin represents. bin_capacity_.resize(bins_.bins().size()); for (FlatPlacementBinId bin_id : bins_.bins()) { size_t physical_tile_type_index = bin_phy_tile_type_idx[bin_id]; bin_capacity_[bin_id] = mass_calculator_.get_physical_tile_type_capacity(physical_tile_type_index); + // Only allocate capacity to dims which are actually used. This prevents + // the capacity vectors from getting too large, saving run time. + bin_capacity_[bin_id].project(used_dims_mask_); } // Initialize the bin utilizations to be zero (there is nothing in the bin @@ -307,3 +323,7 @@ void FlatPlacementDensityManager::print_bin_grid() const { } VTR_LOG("\n"); } + +void FlatPlacementDensityManager::generate_mass_report() const { + mass_calculator_.generate_mass_report(ap_netlist_); +} diff --git a/vpr/src/analytical_place/flat_placement_density_manager.h b/vpr/src/analytical_place/flat_placement_density_manager.h index ad3977589c1..73f27b4efd3 100644 --- a/vpr/src/analytical_place/flat_placement_density_manager.h +++ b/vpr/src/analytical_place/flat_placement_density_manager.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -8,13 +9,12 @@ * defines a bin that is "overfilled". */ -#pragma once - #include #include #include #include "flat_placement_bins.h" #include "flat_placement_mass_calculator.h" +#include "primitive_vector.h" #include "vtr_assert.h" #include "vtr_ndmatrix.h" #include "vtr_vector.h" @@ -22,6 +22,7 @@ class APNetlist; class AtomNetlist; class DeviceGrid; +class LogicalModels; class Prepacker; struct PartialPlacement; struct t_logical_block_type; @@ -67,6 +68,7 @@ class FlatPlacementDensityManager { * @param device_grid * @param logical_block_types * @param physical_tile_types + * @param models * @param log_verbosity */ FlatPlacementDensityManager(const APNetlist& ap_netlist, @@ -75,6 +77,7 @@ class FlatPlacementDensityManager { const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, + const LogicalModels& models, int log_verbosity); /** @@ -218,6 +221,16 @@ class FlatPlacementDensityManager { const vtr::Rect& bin_region, const PartialPlacement& p_placement) const; + /** + * @brief Return a primitive vector where any dim which is used in the netlist + * is set to 1, and any unused dim is set to 0. + * + * This information can be used to ignore dims which are unused. + */ + const PrimitiveVector& get_used_dims_mask() const { + return used_dims_mask_; + } + /** * @brief Resets all bins by emptying them. */ @@ -236,6 +249,12 @@ class FlatPlacementDensityManager { */ void print_bin_grid() const; + /** + * @brief Generate a report on the mass calculations within the density + * manager class. + */ + void generate_mass_report() const; + private: /// @brief The AP netlist of blocks which are filling the bins. const APNetlist& ap_netlist_; @@ -268,6 +287,11 @@ class FlatPlacementDensityManager { /// @brief The set of overfilled bins. std::unordered_set overfilled_bins_; + /// @brief A vector mask representing the used primitive vector dimensions + /// in the netlist. If a dimension is used, its value will be set to + /// 1 in this vector, and 0 otherwise. + PrimitiveVector used_dims_mask_; + /// @brief The verbosity of log messages in this class. const int log_verbosity_; }; diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp index 3581c4ce868..523586f7ec6 100644 --- a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp @@ -7,14 +7,17 @@ #include "flat_placement_mass_calculator.h" #include +#include "ap_mass_report.h" #include "ap_netlist.h" #include "atom_netlist.h" -#include "globals.h" #include "logic_types.h" #include "physical_types.h" #include "prepack.h" +#include "primitive_dim_manager.h" #include "primitive_vector.h" +#include "primitive_vector_fwd.h" #include "vtr_log.h" +#include "vtr_vector.h" /** * @brief Get the scalar mass of the given model (primitive type). @@ -34,7 +37,8 @@ static float get_model_mass(LogicalModelId model_id) { // This method is being forward-declared due to the double recursion below. // Eventually this should be made into a non-recursive algorithm for performance, // however this is not in a performance critical part of the code. -static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type); +static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type, + const PrimitiveDimManager& dim_manager); /** * @brief Get the amount of primitives this mode can contain. @@ -42,12 +46,13 @@ static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type); * This is part of a double recursion, since a mode contains primitives which * themselves have modes. */ -static PrimitiveVector calc_mode_capacity(const t_mode& mode) { +static PrimitiveVector calc_mode_capacity(const t_mode& mode, + const PrimitiveDimManager& dim_manager) { // Accumulate the capacities of all the pbs in this mode. PrimitiveVector capacity; for (int pb_child_idx = 0; pb_child_idx < mode.num_pb_type_children; pb_child_idx++) { const t_pb_type& pb_type = mode.pb_type_children[pb_child_idx]; - PrimitiveVector pb_capacity = calc_pb_type_capacity(&pb_type); + PrimitiveVector pb_capacity = calc_pb_type_capacity(&pb_type, dim_manager); // A mode may contain multiple pbs of the same type, multiply the // capacity. pb_capacity *= pb_type.num_pb; @@ -62,7 +67,8 @@ static PrimitiveVector calc_mode_capacity(const t_mode& mode) { * This is the other part of the double recursion. A pb may have multiple modes. * Modes are made of pbs. */ -static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) { +static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type, + const PrimitiveDimManager& dim_manager) { // Since a pb cannot be multiple modes at the same time, we do not // accumulate the capacities of the mode. Instead we need to "mix" the two // capacities as if the pb could choose either one. @@ -71,14 +77,16 @@ static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) { if (pb_type->is_primitive()) { LogicalModelId model_id = pb_type->model_id; VTR_ASSERT(model_id.is_valid()); - capacity.add_val_to_dim(get_model_mass(model_id), (size_t)model_id); + PrimitiveVectorDim dim = dim_manager.get_model_dim(model_id); + VTR_ASSERT(dim.is_valid()); + capacity.add_val_to_dim(get_model_mass(model_id), dim); return capacity; } // For now, we simply mix the capacities of modes by taking the max of each // dimension of the capcities. This provides an upper-bound on the amount of // primitives this pb can contain. for (int mode = 0; mode < pb_type->num_modes; mode++) { - PrimitiveVector mode_capacity = calc_mode_capacity(pb_type->modes[mode]); + PrimitiveVector mode_capacity = calc_mode_capacity(pb_type->modes[mode], dim_manager); capacity = PrimitiveVector::max(capacity, mode_capacity); } return capacity; @@ -87,13 +95,14 @@ static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) { /** * @brief Calculate the cpacity of the given logical block type. */ -static PrimitiveVector calc_logical_block_type_capacity(const t_logical_block_type& logical_block_type) { +static PrimitiveVector calc_logical_block_type_capacity(const t_logical_block_type& logical_block_type, + const PrimitiveDimManager& dim_manager) { // If this logical block is empty, it cannot contain any primitives. if (logical_block_type.is_empty()) return PrimitiveVector(); // The primitive capacity of a logical block is the primitive capacity of // its root pb. - return calc_pb_type_capacity(logical_block_type.pb_type); + return calc_pb_type_capacity(logical_block_type.pb_type, dim_manager); } /** @@ -155,6 +164,7 @@ static PrimitiveVector calc_physical_tile_type_capacity(const t_physical_tile_ty * (primitive types) in the architecture. */ static PrimitiveVector calc_block_mass(APBlockId blk_id, + const PrimitiveDimManager& dim_manager, const APNetlist& netlist, const Prepacker& prepacker, const AtomNetlist& atom_netlist) { @@ -168,56 +178,42 @@ static PrimitiveVector calc_block_mass(APBlockId blk_id, continue; LogicalModelId model_id = atom_netlist.block_model(atom_blk_id); VTR_ASSERT(model_id.is_valid()); - mass.add_val_to_dim(get_model_mass(model_id), (size_t)model_id); + PrimitiveVectorDim dim = dim_manager.get_model_dim(model_id); + VTR_ASSERT(dim.is_valid()); + mass.add_val_to_dim(get_model_mass(model_id), dim); } return mass; } /** - * @brief Debug printing method to print the capacities of all logical blocks - * and physical tile types. + * @brief Initialize the dim manager such that every model in the architecture + * has a valid dimension in the primitive vector. */ -static void print_capacities(const std::vector& logical_block_type_capacities, - const std::vector& physical_tile_type_capacities, - const std::vector& logical_block_types, - const std::vector& physical_tile_types) { - // TODO: Pass these into this function. - const LogicalModels& models = g_vpr_ctx.device().arch->models; +static void initialize_dim_manager(PrimitiveDimManager& dim_manager, + const LogicalModels& models, + const AtomNetlist& atom_netlist) { + // Set the mapping between model IDs and Primitive Vector IDs - // Print the capacities. - VTR_LOG("Logical Block Type Capacities:\n"); - VTR_LOG("------------------------------\n"); - VTR_LOG("name\t"); - for (LogicalModelId model_id : models.all_models()) { - VTR_LOG("%s\t", models.get_model(model_id).name); + // Count the number of occurences of each model in the netlist. + vtr::vector num_model_occurence(models.all_models().size(), 0); + for (AtomBlockId blk_id : atom_netlist.blocks()) { + num_model_occurence[atom_netlist.block_model(blk_id)]++; } - VTR_LOG("\n"); - for (const t_logical_block_type& block_type : logical_block_types) { - const PrimitiveVector& capacity = logical_block_type_capacities[block_type.index]; - VTR_LOG("%s\t", block_type.name.c_str()); - for (LogicalModelId model_id : models.all_models()) { - VTR_LOG("%.2f\t", capacity.get_dim_val((size_t)model_id)); - } - VTR_LOG("\n"); - } - VTR_LOG("\n"); - VTR_LOG("Physical Tile Type Capacities:\n"); - VTR_LOG("------------------------------\n"); - VTR_LOG("name\t"); - for (LogicalModelId model_id : models.all_models()) { - VTR_LOG("%s\t", models.get_model(model_id).name); - } - VTR_LOG("\n"); - for (const t_physical_tile_type& tile_type : physical_tile_types) { - const PrimitiveVector& capacity = physical_tile_type_capacities[tile_type.index]; - VTR_LOG("%s\t", tile_type.name.c_str()); - for (LogicalModelId model_id : models.all_models()) { - VTR_LOG("%.2f\t", capacity.get_dim_val((size_t)model_id)); - } - VTR_LOG("\n"); + + // Create a list of models, sorted by their frequency in the netlist. + // By sorting by frequency, we make the early dimensions more common, + // which can reduce the overall size of the sparse vector. + // NOTE: We use stable sort here to keep the order of models the same + // as what the user provided in the arch file in the event of a tie. + std::vector logical_models(models.all_models().begin(), models.all_models().end()); + std::stable_sort(logical_models.begin(), logical_models.end(), [&](LogicalModelId a, LogicalModelId b) { + return num_model_occurence[a] > num_model_occurence[b]; + }); + + // Create a primitive vector dim for each model. + for (LogicalModelId model_id : logical_models) { + dim_manager.create_dim(model_id, models.model_name(model_id)); } - VTR_LOG("\n"); - // TODO: Print the masses of each model. } FlatPlacementMassCalculator::FlatPlacementMassCalculator(const APNetlist& ap_netlist, @@ -225,15 +221,21 @@ FlatPlacementMassCalculator::FlatPlacementMassCalculator(const APNetlist& ap_net const AtomNetlist& atom_netlist, const std::vector& logical_block_types, const std::vector& physical_tile_types, + const LogicalModels& models, int log_verbosity) : physical_tile_type_capacity_(physical_tile_types.size()) , logical_block_type_capacity_(logical_block_types.size()) , block_mass_(ap_netlist.blocks().size()) , log_verbosity_(log_verbosity) { + // Initialize the mapping between model IDs and Primitive Vector dims + initialize_dim_manager(primitive_dim_manager_, + models, + atom_netlist); + // Precompute the capacity of each logical block type. for (const t_logical_block_type& logical_block_type : logical_block_types) { - logical_block_type_capacity_[logical_block_type.index] = calc_logical_block_type_capacity(logical_block_type); + logical_block_type_capacity_[logical_block_type.index] = calc_logical_block_type_capacity(logical_block_type, primitive_dim_manager_); } // Precompute the capacity of each physical tile type. @@ -245,17 +247,18 @@ FlatPlacementMassCalculator::FlatPlacementMassCalculator(const APNetlist& ap_net VTR_LOGV(log_verbosity_ >= 10, "Pre-computing the block masses...\n"); for (APBlockId ap_block_id : ap_netlist.blocks()) { block_mass_[ap_block_id] = calc_block_mass(ap_block_id, + primitive_dim_manager_, ap_netlist, prepacker, atom_netlist); } VTR_LOGV(log_verbosity_ >= 10, "Finished pre-computing the block masses.\n"); +} - // Print the precomputed block capacities. This can be helpful for debugging. - if (log_verbosity_ > 1) { - print_capacities(logical_block_type_capacity_, - physical_tile_type_capacity_, - logical_block_types, - physical_tile_types); - } +void FlatPlacementMassCalculator::generate_mass_report(const APNetlist& ap_netlist) const { + generate_ap_mass_report(logical_block_type_capacity_, + physical_tile_type_capacity_, + block_mass_, + primitive_dim_manager_, + ap_netlist); } diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.h b/vpr/src/analytical_place/flat_placement_mass_calculator.h index 286b91dd743..dc12d635660 100644 --- a/vpr/src/analytical_place/flat_placement_mass_calculator.h +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.h @@ -1,14 +1,30 @@ +#pragma once /** * @file * @author Alex Singer * @date February 2024 * @brief Mass calculation for AP blocks and logical/physical block/tile types + * + * This class is used to abstract away the concept of mass in the partial legalizer. + * Mass is a multi-dimensional quantity where every AP block has mass and every + * tile has a mass capacity. For example, a molecule consisting of a LUT and FF + * may have a mass of <1, 1>, where the first dimension is LUTs and the second + * dimension is FFs. A CLB tile which contains 8 LUTs and 8 FFs may have a + * capacity of <8, 8>. + * + * Outside of this class, mass is viewed as a sparse, multi-dimensional vector + * called the PrimitiveVector. + * + * This class will decide what each dimension in that primitive vector means and + * how much of that dimension each atom will take up. A Dim Manager class is used + * to manage the lookup between atom models and the dimensions in the + * primitive vector. */ -#pragma once - #include #include "ap_netlist_fwd.h" +#include "logic_types.h" +#include "primitive_dim_manager.h" #include "primitive_vector.h" #include "vtr_assert.h" #include "vtr_vector.h" @@ -60,6 +76,9 @@ class FlatPlacementMassCalculator { * A list of all physical_tile_types that exist on the FGPA. The * capacity of each physical tile is precomputed in the constructor to * be loaded cheaply later. + * @param models + * All of the logical models in the architecture. Used to inform the + * dimensionality of the mass. * @param log_verbosity * The verbosity of log messages in the mass calculator. */ @@ -68,6 +87,7 @@ class FlatPlacementMassCalculator { const AtomNetlist& atom_netlist, const std::vector& logical_block_types, const std::vector& physical_tile_types, + const LogicalModels& models, int log_verbosity); /** @@ -97,6 +117,30 @@ class FlatPlacementMassCalculator { return block_mass_[blk_id]; } + /** + * @brief Get the primitive vector dim of the given model ID. + */ + inline PrimitiveVectorDim get_model_dim(LogicalModelId model_id) const { + VTR_ASSERT_SAFE(model_id.is_valid()); + return primitive_dim_manager_.get_model_dim(model_id); + } + + /** + * @brief Get a reference to the primitive dim manager. + * + * This object controls the lookup between logical model IDs and primitive + * vector dims. + */ + inline const PrimitiveDimManager& get_dim_manager() const { + return primitive_dim_manager_; + } + + /** + * @brief Generate a report on the mass and capacities calculated by this + * class. + */ + void generate_mass_report(const APNetlist& ap_netlist) const; + private: /// @brief The capacity of each physical tile type, indexed by the index /// of the physical_tile_type. @@ -109,6 +153,10 @@ class FlatPlacementMassCalculator { /// @brief The mass of each block in the AP netlist. vtr::vector block_mass_; + /// @brief The primitive dim manager. This class manages what the dimensions + /// within the primitive vectors this class produces represents. + PrimitiveDimManager primitive_dim_manager_; + /// @brief The verbosity of log messages in the mass calculator. const int log_verbosity_; }; diff --git a/vpr/src/analytical_place/full_legalizer.h b/vpr/src/analytical_place/full_legalizer.h index 57baef27fc9..34f1f1da442 100644 --- a/vpr/src/analytical_place/full_legalizer.h +++ b/vpr/src/analytical_place/full_legalizer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -7,8 +8,6 @@ * routed by VTR. */ -#pragma once - #include #include "ap_flow_enums.h" @@ -17,7 +16,7 @@ class APNetlist; class AtomNetlist; class ClusteredNetlist; class DeviceGrid; -class PartialPlacement; +struct PartialPlacement; class PlaceMacros; class PreClusterTimingManager; class Prepacker; diff --git a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp index 75c3361ec3d..e49d96e7c27 100644 --- a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp +++ b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp @@ -60,8 +60,8 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, bool pin_is_const = atom_netlist.pin_is_constant(atom_pin_id); AtomNetId pin_atom_net_id = atom_netlist.pin_net(atom_pin_id); const std::string& pin_atom_net_name = atom_netlist.net_name(pin_atom_net_id); - APNetId pin_ap_net_id = ap_netlist.create_net(pin_atom_net_name); - ap_netlist.create_pin(ap_port_id, port_bit, pin_ap_net_id, pin_type, pin_is_const); + APNetId pin_ap_net_id = ap_netlist.create_net(pin_atom_net_name, pin_atom_net_id); + ap_netlist.create_pin(ap_port_id, port_bit, pin_ap_net_id, pin_type, atom_pin_id, pin_is_const); } } } @@ -109,32 +109,26 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, } } - // Cleanup the netlist by removing undesirable nets. + // Cleanup the netlist by marking undesirable nets. // Currently undesirable nets are nets that are: // - ignored for placement // - a global net // - connected to 1 or fewer unique blocks // - connected to only fixed blocks - // TODO: Allow the user to pass a threshold so we can remove high-fanout nets. - auto remove_net = [&](APNetId net_id) { - // Remove all pins associated with this net - for (APPinId pin_id : ap_netlist.net_pins(net_id)) - ap_netlist.remove_pin(pin_id); - // Remove the net - ap_netlist.remove_net(net_id); - }; for (APNetId ap_net_id : ap_netlist.nets()) { - // Is the net ignored for placement, if so remove + // Is the net ignored for placement, if so mark as ignored for AP. const std::string& net_name = ap_netlist.net_name(ap_net_id); AtomNetId atom_net_id = atom_netlist.find_net(net_name); VTR_ASSERT(atom_net_id.is_valid()); if (atom_netlist.net_is_ignored(atom_net_id)) { - remove_net(ap_net_id); + ap_netlist.set_net_is_ignored(ap_net_id, true); continue; } - // Is the net global, if so remove + // Is the net global, if so mark as global for AP (also ignored) if (atom_netlist.net_is_global(atom_net_id)) { - remove_net(ap_net_id); + ap_netlist.set_net_is_global(ap_net_id, true); + // Global nets are also ignored by the AP flow. + ap_netlist.set_net_is_ignored(ap_net_id, true); continue; } // Get the unique blocks connectioned to this net @@ -142,12 +136,12 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, for (APPinId ap_pin_id : ap_netlist.net_pins(ap_net_id)) { net_blocks.insert(ap_netlist.pin_block(ap_pin_id)); } - // If connected to 1 or fewer unique blocks, remove + // If connected to 1 or fewer unique blocks, mark as ignored for AP. if (net_blocks.size() <= 1) { - remove_net(ap_net_id); + ap_netlist.set_net_is_ignored(ap_net_id, true); continue; } - // If all the connected blocks are fixed, remove + // If all the connected blocks are fixed, mark as ignored for AP. bool is_all_fixed = true; for (APBlockId ap_blk_id : net_blocks) { if (ap_netlist.block_mobility(ap_blk_id) == APBlockMobility::MOVEABLE) { @@ -156,11 +150,11 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, } } if (is_all_fixed) { - remove_net(ap_net_id); + ap_netlist.set_net_is_ignored(ap_net_id, true); continue; } } - ap_netlist.remove_and_compress(); + ap_netlist.compress(); // TODO: Should we cleanup the blocks? For example if there is no path // from a fixed block to a given moveable block, then that moveable diff --git a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h index ed5ae7bb0d1..f7236616d3d 100644 --- a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h +++ b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -6,8 +7,6 @@ * results of the prepacker to generate an APNetlist. */ -#pragma once - // Forward declarations class APNetlist; class AtomNetlist; diff --git a/vpr/src/analytical_place/global_placer.cpp b/vpr/src/analytical_place/global_placer.cpp index ebf506a3432..1f44eff6647 100644 --- a/vpr/src/analytical_place/global_placer.cpp +++ b/vpr/src/analytical_place/global_placer.cpp @@ -11,6 +11,7 @@ #include #include #include +#include "PreClusterTimingManager.h" #include "analytical_solver.h" #include "ap_flow_enums.h" #include "ap_netlist.h" @@ -20,10 +21,13 @@ #include "flat_placement_bins.h" #include "flat_placement_density_manager.h" #include "globals.h" +#include "logic_types.h" #include "partial_legalizer.h" #include "partial_placement.h" #include "physical_types.h" +#include "place_delay_model.h" #include "primitive_vector.h" +#include "timing_info.h" #include "vtr_log.h" #include "vtr_time.h" @@ -35,8 +39,11 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, - const PreClusterTimingManager& pre_cluster_timing_manager, + const LogicalModels& models, + PreClusterTimingManager& pre_cluster_timing_manager, + std::shared_ptr place_delay_model, float ap_timing_tradeoff, + bool generate_mass_report, unsigned num_threads, int log_verbosity) { return std::make_unique(analytical_solver_type, @@ -47,8 +54,11 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic device_grid, logical_block_types, physical_tile_types, + models, pre_cluster_timing_manager, + place_delay_model, ap_timing_tradeoff, + generate_mass_report, num_threads, log_verbosity); } @@ -61,11 +71,16 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, - const PreClusterTimingManager& pre_cluster_timing_manager, + const LogicalModels& models, + PreClusterTimingManager& pre_cluster_timing_manager, + std::shared_ptr place_delay_model, float ap_timing_tradeoff, + bool generate_mass_report, unsigned num_threads, int log_verbosity) - : GlobalPlacer(ap_netlist, log_verbosity) { + : GlobalPlacer(ap_netlist, log_verbosity) + , pre_cluster_timing_manager_(pre_cluster_timing_manager) + , place_delay_model_(place_delay_model) { // This can be a long method. Good to time this to see how long it takes to // construct the global placer. vtr::ScopedStartFinishTimer global_placer_building_timer("Constructing Global Placer"); @@ -76,7 +91,7 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty ap_netlist_, device_grid, atom_netlist, - pre_cluster_timing_manager, + pre_cluster_timing_manager_, ap_timing_tradeoff, num_threads, log_verbosity_); @@ -89,7 +104,10 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty device_grid, logical_block_types, physical_tile_types, + models, log_verbosity_); + if (generate_mass_report) + density_manager_->generate_mass_report(); // Build the partial legalizer VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the partial legalizer...\n"); @@ -97,6 +115,7 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty ap_netlist_, density_manager_, prepacker, + models, log_verbosity_); } @@ -169,10 +188,10 @@ static void print_placement_stats(const PartialPlacement& p_placement, * of the global placer. */ static void print_SimPL_status_header() { - VTR_LOG("---- ---------------- ---------------- ----------- -------------- ----------\n"); - VTR_LOG("Iter Lower Bound HPWL Upper Bound HPWL Solver Time Legalizer Time Total Time\n"); - VTR_LOG(" (sec) (sec) (sec)\n"); - VTR_LOG("---- ---------------- ---------------- ----------- -------------- ----------\n"); + VTR_LOG("---- ---------------- ---------------- ----------- ------------ ----------- -------------- ------------------ ----------\n"); + VTR_LOG("Iter Lower Bound HPWL Upper Bound HPWL UB CPD (ns) UB sTNS (ns) Solver Time Legalizer Time Timing Update Time Total Time\n"); + VTR_LOG(" (sec) (sec) (sec) (sec)\n"); + VTR_LOG("---- ---------------- ---------------- ----------- ------------ ----------- -------------- ------------------ ----------\n"); } /** @@ -181,8 +200,11 @@ static void print_SimPL_status_header() { static void print_SimPL_status(size_t iteration, double lb_hpwl, double ub_hpwl, + float cpd, + float stns, float solver_time, float legalizer_time, + float timing_update_time, float total_time) { // Iteration VTR_LOG("%4zu", iteration); @@ -193,12 +215,21 @@ static void print_SimPL_status(size_t iteration, // Upper Bound HPWL VTR_LOG(" %16.2f", ub_hpwl); + // Upper Bound CPD (ns) + VTR_LOG(" %11.3f", cpd); + + // Upper Bound sTNS (ns) + VTR_LOG(" %12g", stns); + // Solver runtime VTR_LOG(" %11.3f", solver_time); // Legalizer runtime VTR_LOG(" %14.3f", legalizer_time); + // Timing update runtime + VTR_LOG(" %18.3f", timing_update_time); + // Total runtime VTR_LOG(" %10.3f", total_time); @@ -207,6 +238,84 @@ static void print_SimPL_status(size_t iteration, fflush(stdout); } +/** + * @brief Helper method for updating the timing information in the pre-cluster + * timing manager using a flat placement as a hint for where the atoms + * will be placed. + * + * @param pre_cluster_timing_manager + * Manager object which computes the slacks of timing edges. + * @param place_delay_model + * A delay model which can approximate the delay of wires over some distance. + * @param p_placement + * The flat placement used to update the timing information. + * @param ap_netlist + * The AP netlist the p_placement uses. + */ +static void update_timing_info_with_gp_placement(PreClusterTimingManager& pre_cluster_timing_manager, + const PlaceDelayModel& place_delay_model, + const PartialPlacement& p_placement, + const APNetlist& ap_netlist) { + // If the timing manager is invalid (i.e. timing analysis is off), do not + // update. + if (!pre_cluster_timing_manager.is_valid()) + return; + + // For each AP pin, update the delay of the timing arc going through it. + // The timing manager operates on the Atom netlist; however, by construction + // of the AP netlist, every atom pin corresponds 1to1 to an AP pin. + for (APPinId ap_pin_id : ap_netlist.pins()) { + // Timing arcs are uniquely identified by the sink pin. Only update + // timing for sink pins. + if (ap_netlist.pin_type(ap_pin_id) != PinType::SINK) + continue; + + // Get the driver and sink blocks for this timing arc based on the net + // that terminates at this sink pin. + APNetId ap_net_id = ap_netlist.pin_net(ap_pin_id); + APBlockId ap_driver_block_id = ap_netlist.net_driver_block(ap_net_id); + APBlockId ap_sink_block_id = ap_netlist.pin_block(ap_pin_id); + + // Get the physical tile locations that each block is located in according + // to the flat placement. + t_physical_tile_loc driver_block_loc(p_placement.block_x_locs[ap_driver_block_id], + p_placement.block_y_locs[ap_driver_block_id], + p_placement.block_layer_nums[ap_driver_block_id]); + t_physical_tile_loc sink_block_loc(p_placement.block_x_locs[ap_sink_block_id], + p_placement.block_y_locs[ap_sink_block_id], + p_placement.block_layer_nums[ap_sink_block_id]); + + // Use the place delay model to get the expected delay of going from + // the driver block to the sink block tile. + // NOTE: We may not have enough information to know which pin the driver + // and sink block will use; however the delay models that we care + // about do not use this feature yet. + // We do not know this information since those pins are cluster- + // level pins, and the cluster-level blocks have not been created + // yet. + // TODO: Handle the from and to pins better. + float delay = place_delay_model.delay(driver_block_loc, + 0 /*from_pin*/, + sink_block_loc, + 0 /*to_pin*/); + + // Get the atom pin associated with this AP pin (i.e. the one the AP + // netlist is modeling). + AtomPinId atom_sink_pin_id = ap_netlist.pin_atom_pin(ap_pin_id); + // Set the timing arc delay for this atom sink pin. + pre_cluster_timing_manager.set_timing_arc_delay(atom_sink_pin_id, delay); + } + + // Update the timing info. This will run STA to recompute the slacks and + // the criticalities of all timing arcs. + pre_cluster_timing_manager.update_timing_info(); + + // Do not warn again about unconstrained nodes during placement. + // Without this line, every GP iteration would see the same warning. + // Ok to warn once after the first iteration. + pre_cluster_timing_manager.get_timing_info_ptr()->set_warn_unconstrained(false); +} + PartialPlacement SimPLGlobalPlacer::place() { // Create a timer to time the entire global placement time. vtr::ScopedStartFinishTimer global_placer_time("AP Global Placer"); @@ -220,6 +329,7 @@ PartialPlacement SimPLGlobalPlacer::place() { float total_time_spent_in_solver = 0.0f; float total_time_spent_in_legalizer = 0.0f; + float total_time_spent_updating_timing = 0.0f; // Create a partial placement object to store the best placement found during // global placement. It is possible for the global placement to hit a minimum @@ -243,19 +353,42 @@ PartialPlacement SimPLGlobalPlacer::place() { float legalizer_end_time = runtime_timer.elapsed_sec(); double ub_hpwl = p_placement.get_hpwl(ap_netlist_); + // Perform a timing update + float timing_update_start_time = runtime_timer.elapsed_sec(); + update_timing_info_with_gp_placement(pre_cluster_timing_manager_, + *place_delay_model_.get(), + p_placement, + ap_netlist_); + solver_->update_net_weights(pre_cluster_timing_manager_); + float timing_update_end_time = runtime_timer.elapsed_sec(); + total_time_spent_in_solver += solver_end_time - solver_start_time; total_time_spent_in_legalizer += legalizer_end_time - legalizer_start_time; + total_time_spent_updating_timing += timing_update_end_time - timing_update_start_time; // Print some stats if (log_verbosity_ >= 1) { + float cpd_ns = -1.0f; + float stns_ns = -1.0f; + if (pre_cluster_timing_manager_.is_valid()) { + cpd_ns = pre_cluster_timing_manager_.get_timing_info().least_slack_critical_path().delay() * 1e9; + stns_ns = pre_cluster_timing_manager_.get_timing_info().setup_total_negative_slack() * 1e9; + } + float iter_end_time = runtime_timer.elapsed_sec(); print_SimPL_status(i, lb_hpwl, ub_hpwl, + cpd_ns, + stns_ns, solver_end_time - solver_start_time, legalizer_end_time - legalizer_start_time, + timing_update_end_time - timing_update_start_time, iter_end_time - iter_start_time); } // If this placement is better than the best we have seen, save it. + // TODO: This is not correct for timing. We want to use a costing + // function that takes timing into account as well. We do not just + // want the lowest HPWL. if (ub_hpwl < best_ub_hpwl) { best_ub_hpwl = ub_hpwl; best_p_placement = p_placement; @@ -268,6 +401,14 @@ PartialPlacement SimPLGlobalPlacer::place() { break; } + // Update the setup slacks. This is performed down here (as well as being + // inside the GP loop) since the best_p_placement may not be the p_placement + // from the last iteration of GP. + update_timing_info_with_gp_placement(pre_cluster_timing_manager_, + *place_delay_model_.get(), + best_p_placement, + ap_netlist_); + // Print statistics on the solver used. solver_->print_statistics(); @@ -277,6 +418,7 @@ PartialPlacement SimPLGlobalPlacer::place() { VTR_LOG("Global Placer Statistics:\n"); VTR_LOG("\tTime spent in solver: %g seconds\n", total_time_spent_in_solver); VTR_LOG("\tTime spent in legalizer: %g seconds\n", total_time_spent_in_legalizer); + VTR_LOG("\tTime spent updating timing: %g seconds\n", total_time_spent_updating_timing); // Print some statistics on the final placement. VTR_LOG("Placement after Global Placement:\n"); @@ -285,7 +427,5 @@ PartialPlacement SimPLGlobalPlacer::place() { *density_manager_); // Return the placement from the final iteration. - // TODO: investigate saving the best solution found so far. It should be - // cheap to save a copy of the PartialPlacement object. return best_p_placement; } diff --git a/vpr/src/analytical_place/global_placer.h b/vpr/src/analytical_place/global_placer.h index 6b59484db65..033db223b11 100644 --- a/vpr/src/analytical_place/global_placer.h +++ b/vpr/src/analytical_place/global_placer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -12,8 +13,6 @@ * architecture. */ -#pragma once - #include #include "ap_flow_enums.h" #include "flat_placement_density_manager.h" @@ -22,9 +21,11 @@ // Forward declarations class APNetlist; class AnalyticalSolver; +class LogicalModels; class PartialLegalizer; -class Prepacker; +class PlaceDelayModel; class PreClusterTimingManager; +class Prepacker; struct PartialPlacement; /** @@ -81,8 +82,11 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, - const PreClusterTimingManager& pre_cluster_timing_manager, + const LogicalModels& models, + PreClusterTimingManager& pre_cluster_timing_manager, + std::shared_ptr place_delay_model, float ap_timing_tradeoff, + bool generate_mass_report, unsigned num_threads, int log_verbosity); @@ -133,6 +137,14 @@ class SimPLGlobalPlacer : public GlobalPlacer { /// @brief The legalizer which generates the upper-bound placement. std::unique_ptr partial_legalizer_; + /// @brief The pre-cluster timing manager which manages how the timing of + /// the netlist is computed. + PreClusterTimingManager& pre_cluster_timing_manager_; + + /// @brief A placement delay model which is used to help compute the delays + /// of connections in the AP netlist. + std::shared_ptr place_delay_model_; + public: /** * @brief Constructor for the SimPL Global Placer @@ -147,8 +159,11 @@ class SimPLGlobalPlacer : public GlobalPlacer { const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, - const PreClusterTimingManager& pre_cluster_timing_manager, + const LogicalModels& models, + PreClusterTimingManager& pre_cluster_timing_manager, + std::shared_ptr place_delay_model, float ap_timing_tradeoff, + bool generate_mass_report, unsigned num_threads, int log_verbosity); diff --git a/vpr/src/analytical_place/model_grouper.h b/vpr/src/analytical_place/model_grouper.h index 6e9e56ce03a..5cfe4583175 100644 --- a/vpr/src/analytical_place/model_grouper.h +++ b/vpr/src/analytical_place/model_grouper.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -6,8 +7,6 @@ * that must be legalized together in a flat placement. */ -#pragma once - #include #include "logic_types.h" #include "vtr_assert.h" @@ -61,10 +60,8 @@ class ModelGrouper { * @param prepacker * The prepacker used to create molecules in the flat placement. This * provides the pack patterns for forming the groups. - * @param user_models - * Linked list of user-provided models. - * @param library_models - * Linked list of library models. + * @param models + * The logical models found in the architecture. * @param log_verbosity * The verbosity of log messages in the grouper class. */ diff --git a/vpr/src/analytical_place/partial_legalizer.cpp b/vpr/src/analytical_place/partial_legalizer.cpp index 38e585ae1b1..f80ec368190 100644 --- a/vpr/src/analytical_place/partial_legalizer.cpp +++ b/vpr/src/analytical_place/partial_legalizer.cpp @@ -24,13 +24,11 @@ #include "flat_placement_bins.h" #include "flat_placement_density_manager.h" #include "flat_placement_mass_calculator.h" -#include "globals.h" #include "model_grouper.h" #include "partial_placement.h" -#include "physical_types.h" #include "prepack.h" +#include "primitive_dim_manager.h" #include "primitive_vector.h" -#include "vpr_context.h" #include "vpr_error.h" #include "vtr_assert.h" #include "vtr_geometry.h" @@ -46,17 +44,20 @@ std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer const APNetlist& netlist, std::shared_ptr density_manager, const Prepacker& prepacker, + const LogicalModels& models, int log_verbosity) { // Based on the partial legalizer type passed in, build the partial legalizer. switch (legalizer_type) { case e_ap_partial_legalizer::FlowBased: return std::make_unique(netlist, density_manager, + models, log_verbosity); case e_ap_partial_legalizer::BiPartitioning: return std::make_unique(netlist, density_manager, prepacker, + models, log_verbosity); default: VPR_FATAL_ERROR(VPR_ERROR_AP, @@ -175,7 +176,8 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, continue; // If this bin has this model in its capacity, we found a neighbor! const PrimitiveVector& target_bin_capacity = density_manager_->get_bin_capacity(target_bin_id); - if (target_bin_capacity.get_dim_val((size_t)model_id) > 0) { + PrimitiveVectorDim dim = density_manager_->mass_calculator().get_model_dim(model_id); + if (target_bin_capacity.get_dim_val(dim) > 0) { dir_found[model_id] = true; neighbors.insert(target_bin_id); } else { @@ -245,6 +247,7 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, FlowBasedLegalizer::FlowBasedLegalizer(const APNetlist& netlist, std::shared_ptr density_manager, + const LogicalModels& models, int log_verbosity) : PartialLegalizer(netlist, log_verbosity) , density_manager_(density_manager) @@ -252,8 +255,7 @@ FlowBasedLegalizer::FlowBasedLegalizer(const APNetlist& netlist, // Connect the bins. for (FlatPlacementBinId bin_id : density_manager_->flat_placement_bins().bins()) { - // TODO: Pass the models in. - compute_neighbors_of_bin(bin_id, g_vpr_ctx.device().arch->models); + compute_neighbors_of_bin(bin_id, models); } } @@ -682,65 +684,167 @@ void FlowBasedLegalizer::legalize(PartialPlacement& p_placement) { density_manager_->export_placement_from_bins(p_placement); } -PerModelPrefixSum2D::PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, - const LogicalModels& models, - std::function lookup) { +PerPrimitiveDimPrefixSum2D::PerPrimitiveDimPrefixSum2D(const FlatPlacementDensityManager& density_manager, + std::function lookup) { // Get the size that the prefix sums should be. size_t width, height, layers; std::tie(width, height, layers) = density_manager.get_overall_placeable_region_size(); // Create each of the prefix sums. - model_prefix_sum_.resize(models.all_models().size()); - for (LogicalModelId model_id : models.all_models()) { - model_prefix_sum_[model_id] = vtr::PrefixSum2D( + const PrimitiveDimManager& dim_manager = density_manager.mass_calculator().get_dim_manager(); + dim_prefix_sum_.resize(dim_manager.dims().size()); + for (PrimitiveVectorDim dim : density_manager.get_used_dims_mask().get_non_zero_dims()) { + dim_prefix_sum_[dim] = vtr::PrefixSum2D( width, height, [&](size_t x, size_t y) { - return lookup(model_id, x, y); + return lookup(dim, x, y); }); } } -float PerModelPrefixSum2D::get_model_sum(LogicalModelId model_index, - const vtr::Rect& region) const { - VTR_ASSERT_SAFE(model_index.is_valid()); +float PerPrimitiveDimPrefixSum2D::get_dim_sum(PrimitiveVectorDim dim, + const vtr::Rect& region) const { + VTR_ASSERT_SAFE(dim.is_valid()); // Get the sum over the given region. - return model_prefix_sum_[model_index].get_sum(region.xmin(), - region.ymin(), - region.xmax() - 1, - region.ymax() - 1); + return dim_prefix_sum_[dim].get_sum(region.xmin(), + region.ymin(), + region.xmax() - 1, + region.ymax() - 1); } -PrimitiveVector PerModelPrefixSum2D::get_sum(const std::vector& model_indices, - const vtr::Rect& region) const { +PrimitiveVector PerPrimitiveDimPrefixSum2D::get_sum(const std::vector& dims, + const vtr::Rect& region) const { PrimitiveVector res; - for (LogicalModelId model_index : model_indices) { - VTR_ASSERT_SAFE(res.get_dim_val((size_t)model_index) == 0.0f); - res.set_dim_val((size_t)model_index, get_model_sum(model_index, region)); + for (PrimitiveVectorDim dim : dims) { + VTR_ASSERT_SAFE(res.get_dim_val(dim) == 0.0f); + res.set_dim_val(dim, get_dim_sum(dim, region)); } return res; } +PrimitiveDimGrouper::PrimitiveDimGrouper(const Prepacker& prepacker, + const LogicalModels& models, + const FlatPlacementDensityManager& density_manager, + const PrimitiveDimManager& dim_manager, + int log_verbosity) + : model_grouper_(prepacker, models, log_verbosity) { + + // Models are grouped together by the model grouper based on the pack + // patterns provided by the architecture. Different models may be mapped to + // the same primitive dim. As such, we need to perform another grouping in + // a similar manner to group together the dims which must be spread together. + // + // We ignore unused dims to prevent them from being used in the spreading + // algorithm. Since they are unused, we do not put them into groups. + + // Create an adjacency list connecting dimensions together which share models + // that are grouped together. + size_t num_dims = dim_manager.dims().size(); + vtr::vector> adj_list(num_dims); + const PrimitiveVector& used_dims_mask = density_manager.get_used_dims_mask(); + for (ModelGroupId group_id : model_grouper_.groups()) { + // Collect all of the models in this group. + const auto& models_in_group = model_grouper_.get_models_in_group(group_id); + + // Collect all of the used dimensions of the models in this group. + std::unordered_set dims_in_group; + for (LogicalModelId model_id : models_in_group) { + PrimitiveVectorDim dim = dim_manager.get_model_dim(model_id); + // If this dim is unused, skip. + if (used_dims_mask.get_dim_val(dim) == 0) + continue; + + dims_in_group.insert(dim); + } + + // If this group is empty (i.e. all dims are unused), pass. + if (dims_in_group.empty()) + continue; + + // Create a bidirectional edge between the first dim and all other + // dims in the group. + PrimitiveVectorDim first_dim = *dims_in_group.begin(); + for (PrimitiveVectorDim dim : dims_in_group) { + adj_list[dim].insert(first_dim); + adj_list[first_dim].insert(dim); + } + } + + // Perform BFS to group the dims. This BFS will traverse all dims that are + // connected to each other and put them into groups. Dims which have no + // path between another dim will not be grouped together. + std::queue node_queue; + dim_group_id_.resize(num_dims, PrimitiveGroupId::INVALID()); + for (PrimitiveVectorDim dim : dim_manager.dims()) { + // If this dim is unused, skip it. + // TODO: Maybe put unused dims into a special group. + if (used_dims_mask.get_dim_val(dim) == 0) + continue; + + // If this dim is already in a group, skip it. + if (dim_group_id_[dim].is_valid()) { + continue; + } + + // Create a new group ID and put this dim in that group. + PrimitiveGroupId group_id = PrimitiveGroupId(group_ids_.size()); + dim_group_id_[dim] = group_id; + // Put this dim into the BFS queue to explore its neighbors. + node_queue.push(dim); + + while (!node_queue.empty()) { + // Pop the dim from the queue and explore its neighbors. + PrimitiveVectorDim node_dim = node_queue.front(); + node_queue.pop(); + for (PrimitiveVectorDim neighbor_dim : adj_list[node_dim]) { + // If this neighbor dim is already in the group, skip it. + if (dim_group_id_[neighbor_dim].is_valid()) { + VTR_ASSERT_SAFE(dim_group_id_[neighbor_dim] == group_id); + continue; + } + // Put the neighbor in this group and push it to the queue. + dim_group_id_[neighbor_dim] = group_id; + node_queue.push(neighbor_dim); + } + } + + // Add this group to the list of all groups. + group_ids_.push_back(group_id); + } + + // Create a lookup between each group and the dims it contains. + groups_.resize(groups().size()); + for (PrimitiveVectorDim dim : dim_manager.dims()) { + // If this dim is unused, skip it. + if (!dim_group_id_[dim].is_valid()) + continue; + groups_[dim_group_id_[dim]].push_back(dim); + } +} + BiPartitioningPartialLegalizer::BiPartitioningPartialLegalizer( const APNetlist& netlist, std::shared_ptr density_manager, const Prepacker& prepacker, + const LogicalModels& models, int log_verbosity) : PartialLegalizer(netlist, log_verbosity) , density_manager_(density_manager) - , model_grouper_(prepacker, - g_vpr_ctx.device().arch->models, - log_verbosity) { + , dim_grouper_(prepacker, + models, + *density_manager, + density_manager->mass_calculator().get_dim_manager(), + log_verbosity) { // Compute the capacity prefix sum. Capacity is assumed to not change // between iterations of the partial legalizer. - capacity_prefix_sum_ = PerModelPrefixSum2D( + capacity_prefix_sum_ = PerPrimitiveDimPrefixSum2D( *density_manager, - g_vpr_ctx.device().arch->models, - [&](LogicalModelId model_index, size_t x, size_t y) { + [&](PrimitiveVectorDim dim, size_t x, size_t y) { // Get the bin at this grid location. FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); - // Get the capacity of the bin for this model. - float cap = density_manager_->get_bin_capacity(bin_id).get_dim_val((size_t)model_index); + // Get the capacity of the bin for this dim. + float cap = density_manager_->get_bin_capacity(bin_id).get_dim_val(dim); VTR_ASSERT_SAFE(cap >= 0.0f); // Bins may be large, but the prefix sum assumes a 1x1 grid of // values. Normalize by the area of the bin to turn this into @@ -787,14 +891,14 @@ void BiPartitioningPartialLegalizer::legalize(PartialPlacement& p_placement) { } // 1) Identify the groups that need to be spread - std::unordered_set groups_to_spread; + std::unordered_set groups_to_spread; for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { - // Get the overfilled models in this bin. + // Get the overfilled dims in this bin. const PrimitiveVector& overfill = density_manager_->get_bin_overfill(overfilled_bin_id); - std::vector overfilled_models = overfill.get_non_zero_dims(); - // For each model, insert its group into the set. Set will handle dupes. - for (int model_index : overfilled_models) { - groups_to_spread.insert(model_grouper_.get_model_group_id((LogicalModelId)model_index)); + std::vector overfilled_dims = overfill.get_non_zero_dims(); + // For each dim, insert its group into the set. Set will handle dupes. + for (PrimitiveVectorDim dim : overfilled_dims) { + groups_to_spread.insert(dim_grouper_.get_dim_group_id(dim)); } } @@ -802,7 +906,7 @@ void BiPartitioningPartialLegalizer::legalize(PartialPlacement& p_placement) { vtr::Timer runtime_timer; float window_identification_time = 0.0f; float window_spreading_time = 0.0f; - for (ModelGroupId group_id : groups_to_spread) { + for (PrimitiveGroupId group_id : groups_to_spread) { VTR_LOGV(log_verbosity_ >= 10, "\tSpreading group %zu\n", group_id); // Identify non-overlapping spreading windows. float window_identification_start_time = runtime_timer.elapsed_sec(); @@ -836,7 +940,7 @@ void BiPartitioningPartialLegalizer::legalize(PartialPlacement& p_placement) { density_manager_->export_placement_from_bins(p_placement); } -std::vector BiPartitioningPartialLegalizer::identify_non_overlapping_windows(ModelGroupId group_id) { +std::vector BiPartitioningPartialLegalizer::identify_non_overlapping_windows(PrimitiveGroupId group_id) { // 1) Cluster the overfilled bins. This will make creating minimum spanning // windows more efficient. @@ -859,18 +963,18 @@ std::vector BiPartitioningPartialLegalizer::identify_non_overla /** * @brief Helper method to check if the given PrimitiveVector has any values - * in the model dimensions in the given group. + * in the dim dimensions in the given group. * * This method assumes the vector is non-negative. If the vector had any negative * dimensions, it does not make sense to ask if it is in the group or not. */ static bool is_vector_in_group(const PrimitiveVector& vec, - ModelGroupId group_id, - const ModelGrouper& model_grouper) { + PrimitiveGroupId group_id, + const PrimitiveDimGrouper& dim_grouper) { VTR_ASSERT_SAFE(vec.is_non_negative()); - const std::vector& models_in_group = model_grouper.get_models_in_group(group_id); - for (LogicalModelId model_index : models_in_group) { - float dim_val = vec.get_dim_val((size_t)model_index); + const std::vector& dims_in_group = dim_grouper.get_dims_in_group(group_id); + for (PrimitiveVectorDim dim : dims_in_group) { + float dim_val = vec.get_dim_val(dim); if (dim_val != 0.0f) return true; } @@ -878,46 +982,46 @@ static bool is_vector_in_group(const PrimitiveVector& vec, } /** - * @brief Checks if the overfilled models in the given overfilled bin is in the - * given model group. + * @brief Checks if the overfilled dims in the given overfilled bin is in the + * given dim group. * * This method does not check if the bin could be in the given group (for * example the capacity), this checks if the overfilled blocks are in the group. */ static bool is_overfilled_bin_in_group(FlatPlacementBinId overfilled_bin_id, - ModelGroupId group_id, + PrimitiveGroupId group_id, const FlatPlacementDensityManager& density_manager, - const ModelGrouper& model_grouper) { + const PrimitiveDimGrouper& dim_grouper) { const PrimitiveVector& bin_overfill = density_manager.get_bin_overfill(overfilled_bin_id); VTR_ASSERT_SAFE(bin_overfill.is_non_zero()); - return is_vector_in_group(bin_overfill, group_id, model_grouper); + return is_vector_in_group(bin_overfill, group_id, dim_grouper); } /** - * @brief Checks if the given AP block is in the given model group. + * @brief Checks if the given AP block is in the given dim group. * - * An AP block is in a model group if it contains any models in the model group. + * An AP block is in a dim group if it contains any dims in the dim group. */ static bool is_block_in_group(APBlockId blk_id, - ModelGroupId group_id, + PrimitiveGroupId group_id, const FlatPlacementDensityManager& density_manager, - const ModelGrouper& model_grouper) { + const PrimitiveDimGrouper& dim_grouper) { const PrimitiveVector& blk_mass = density_manager.mass_calculator().get_block_mass(blk_id); - return is_vector_in_group(blk_mass, group_id, model_grouper); + return is_vector_in_group(blk_mass, group_id, dim_grouper); } std::vector BiPartitioningPartialLegalizer::get_overfilled_bin_clusters( - ModelGroupId group_id) { + PrimitiveGroupId group_id) { // Use BFS over the overfilled bins to cluster them. std::vector overfilled_bin_clusters; // Maintain the distance from the last overfilled bin vtr::vector dist(density_manager_->flat_placement_bins().bins().size(), -1); for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { - // If this bin is not overfilled with the models in the group, skip. + // If this bin is not overfilled with the dims in the group, skip. if (!is_overfilled_bin_in_group(overfilled_bin_id, group_id, *density_manager_, - model_grouper_)) { + dim_grouper_)) { continue; } // If this bin is already in a cluster, skip. @@ -948,7 +1052,7 @@ std::vector BiPartitioningPartialLegalizer::get_overfil // If the neighbor is an overfilled bin that we care about, add // it to the list of nearby bins and set its distance to 0. if (density_manager_->bin_is_overfilled(neighbor) - && is_overfilled_bin_in_group(neighbor, group_id, *density_manager_, model_grouper_)) { + && is_overfilled_bin_in_group(neighbor, group_id, *density_manager_, dim_grouper_)) { nearby_bins.push_back(neighbor); dist[neighbor] = 0; } else { @@ -971,32 +1075,32 @@ std::vector BiPartitioningPartialLegalizer::get_overfil * than its capacity. */ static bool is_region_overfilled(const vtr::Rect& region, - const PerModelPrefixSum2D& capacity_prefix_sum, - const PerModelPrefixSum2D& utilization_prefix_sum, - const std::vector& model_indices) { - // Go through each model in the model group we are interested in. - for (LogicalModelId model_index : model_indices) { - // Get the capacity of this region for this model. - float region_model_capacity = capacity_prefix_sum.get_model_sum(model_index, - region); - // Get the utilization of this region for this model. - float region_model_utilization = utilization_prefix_sum.get_model_sum(model_index, - region); + const PerPrimitiveDimPrefixSum2D& capacity_prefix_sum, + const PerPrimitiveDimPrefixSum2D& utilization_prefix_sum, + const std::vector& dims) { + // Go through each dim in the dim group we are interested in. + for (PrimitiveVectorDim dim : dims) { + // Get the capacity of this region for this dim. + float region_dim_capacity = capacity_prefix_sum.get_dim_sum(dim, + region); + // Get the utilization of this region for this dim. + float region_dim_utilization = utilization_prefix_sum.get_dim_sum(dim, + region); // If the utilization is higher than the capacity, then this region is // overfilled. // TODO: Look into adding some head room to account for rounding. - if (region_model_utilization > region_model_capacity) + if (region_dim_utilization > region_dim_capacity) return true; } - // If the utilization is less than or equal to the capacity for each model + // If the utilization is less than or equal to the capacity for each dim // then this region is not overfilled. return false; } std::vector BiPartitioningPartialLegalizer::get_min_windows_around_clusters( const std::vector& overfilled_bin_clusters, - ModelGroupId group_id) { + PrimitiveGroupId group_id) { // TODO: Currently, we greedily grow the region by 1 in all directions until // the capacity is larger than the utilization. This may not produce // the minimum window. Should investigate "touching-up" the windows. @@ -1012,15 +1116,14 @@ std::vector BiPartitioningPartialLegalizer::get_min_windows_aro // Precompute a prefix sum for the current utilization of each 1x1 region // of the device. This needs to be recomputed every time the bins are // modified, so it is recomputed here. - PerModelPrefixSum2D utilization_prefix_sum( + PerPrimitiveDimPrefixSum2D utilization_prefix_sum( *density_manager_, - g_vpr_ctx.device().arch->models, - [&](LogicalModelId model_index, size_t x, size_t y) { + [&](PrimitiveVectorDim dim, size_t x, size_t y) { FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); // This is computed the same way as the capacity prefix sum above. const vtr::Rect& bin_region = density_manager_->flat_placement_bins().bin_region(bin_id); float bin_area = bin_region.width() * bin_region.height(); - float util = density_manager_->get_bin_utilization(bin_id).get_dim_val((size_t)model_index); + float util = density_manager_->get_bin_utilization(bin_id).get_dim_val(dim); VTR_ASSERT_SAFE(util >= 0.0f); return util / bin_area; }); @@ -1061,7 +1164,7 @@ std::vector BiPartitioningPartialLegalizer::get_min_windows_aro region.set_ymax(new_ymax); // If the region is no longer overfilled, stop growing. - if (!is_region_overfilled(region, capacity_prefix_sum_, utilization_prefix_sum, model_grouper_.get_models_in_group(group_id))) + if (!is_region_overfilled(region, capacity_prefix_sum_, utilization_prefix_sum, dim_grouper_.get_dims_in_group(group_id))) break; } // Insert this window into the list of windows. @@ -1128,7 +1231,7 @@ void BiPartitioningPartialLegalizer::merge_overlapping_windows( void BiPartitioningPartialLegalizer::move_blocks_into_windows( std::vector& non_overlapping_windows, - ModelGroupId group_id) { + PrimitiveGroupId group_id) { // Move the blocks from their bins into the windows that should contain them. // TODO: It may be good for debugging to check if the windows have nothing // to move. This may indicate a problem (overfilled bins of fixed @@ -1152,7 +1255,7 @@ void BiPartitioningPartialLegalizer::move_blocks_into_windows( if (netlist_.block_mobility(blk_id) != APBlockMobility::MOVEABLE) continue; // If this block is not in the group, do not move it. - if (!is_block_in_group(blk_id, group_id, *density_manager_, model_grouper_)) + if (!is_block_in_group(blk_id, group_id, *density_manager_, dim_grouper_)) continue; moveable_blks.push_back(blk_id); @@ -1170,7 +1273,7 @@ void BiPartitioningPartialLegalizer::move_blocks_into_windows( void BiPartitioningPartialLegalizer::spread_over_windows(std::vector& non_overlapping_windows, const PartialPlacement& p_placement, - ModelGroupId group_id) { + PrimitiveGroupId group_id) { if (log_verbosity_ >= 10) { VTR_LOG("\tIdentified %zu non-overlapping spreading windows.\n", non_overlapping_windows.size()); @@ -1180,7 +1283,7 @@ void BiPartitioningPartialLegalizer::spread_over_windows(std::vector& model_indices = model_grouper_.get_models_in_group(group_id); + const std::vector& dims = dim_grouper_.get_dims_in_group(group_id); // First, try all of the vertical partitions. double min_pivot_x = std::floor(window.region.xmin()) + 1.0; @@ -1308,13 +1411,13 @@ PartitionedWindow BiPartitioningPartialLegalizer::partition_window( vtr::Point(window.region.xmax(), window.region.ymax())); - // Compute the capacity of each partition for the models that we care + // Compute the capacity of each partition for the dims that we care // about. // TODO: This can be made better by looking at the mass of all blocks // within the window and scaling the capacity based on that. - float lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, lower_region).manhattan_norm(); + float lower_window_capacity = capacity_prefix_sum_.get_sum(dims, lower_region).manhattan_norm(); lower_window_capacity = std::max(lower_window_capacity, 0.0f); - float upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, upper_region).manhattan_norm(); + float upper_window_capacity = capacity_prefix_sum_.get_sum(dims, upper_region).manhattan_norm(); upper_window_capacity = std::max(upper_window_capacity, 0.0f); // Compute the score of this partition line. The score is simply just @@ -1349,13 +1452,13 @@ PartitionedWindow BiPartitioningPartialLegalizer::partition_window( vtr::Point(window.region.xmax(), window.region.ymax())); - // Compute the capacity of each partition for the models that we care + // Compute the capacity of each partition for the dims that we care // about. // TODO: This can be made better by looking at the mass of all blocks // within the window and scaling the capacity based on that. - float lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, lower_region).manhattan_norm(); + float lower_window_capacity = capacity_prefix_sum_.get_sum(dims, lower_region).manhattan_norm(); lower_window_capacity = std::max(lower_window_capacity, 0.0f); - float upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, upper_region).manhattan_norm(); + float upper_window_capacity = capacity_prefix_sum_.get_sum(dims, upper_region).manhattan_norm(); upper_window_capacity = std::max(upper_window_capacity, 0.0f); // Compute the score of this partition line. The score is simply just @@ -1384,17 +1487,17 @@ PartitionedWindow BiPartitioningPartialLegalizer::partition_window( void BiPartitioningPartialLegalizer::partition_blocks_in_window( SpreadingWindow& window, PartitionedWindow& partitioned_window, - ModelGroupId group_id, + PrimitiveGroupId group_id, const PartialPlacement& p_placement) { SpreadingWindow& lower_window = partitioned_window.lower_window; SpreadingWindow& upper_window = partitioned_window.upper_window; // Get the capacity of each window partition. - const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); - PrimitiveVector lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, + const std::vector& dims = dim_grouper_.get_dims_in_group(group_id); + PrimitiveVector lower_window_capacity = capacity_prefix_sum_.get_sum(dims, lower_window.region); - PrimitiveVector upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, + PrimitiveVector upper_window_capacity = capacity_prefix_sum_.get_sum(dims, upper_window.region); // Due to the division by the area, we may get numerical underflows / diff --git a/vpr/src/analytical_place/partial_legalizer.h b/vpr/src/analytical_place/partial_legalizer.h index 3920194eee0..593e786dbd7 100644 --- a/vpr/src/analytical_place/partial_legalizer.h +++ b/vpr/src/analytical_place/partial_legalizer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer and Robert Luo @@ -11,8 +12,6 @@ * constraints of the architecture). */ -#pragma once - #include #include #include @@ -22,7 +21,9 @@ #include "flat_placement_density_manager.h" #include "logic_types.h" #include "model_grouper.h" -#include "primitive_vector.h" +#include "primitive_dim_manager.h" +#include "primitive_vector_fwd.h" +#include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_prefix_sum.h" #include "vtr_vector.h" @@ -96,6 +97,7 @@ std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer const APNetlist& netlist, std::shared_ptr density_manager, const Prepacker& prepacker, + const LogicalModels& models, int log_verbosity); /** @@ -235,6 +237,7 @@ class FlowBasedLegalizer : public PartialLegalizer { */ FlowBasedLegalizer(const APNetlist& netlist, std::shared_ptr density_manager, + const LogicalModels& models, int log_verbosity); /** @@ -301,41 +304,128 @@ struct PartitionedWindow { /** * @brief Wrapper class around the prefix sum class which creates a prefix sum - * for each model type and has helper methods for getting the sums over + * for each dim type and has helper methods for getting the sums over * regions. */ -class PerModelPrefixSum2D { +class PerPrimitiveDimPrefixSum2D { public: - PerModelPrefixSum2D() = default; + PerPrimitiveDimPrefixSum2D() = default; /** - * @brief Construct prefix sums for each of the models in the architecture. + * @brief Construct prefix sums for each of the primitive vector dims. * * Uses the density manager to get the size of the placeable region. * * The lookup is a lambda used to populate the prefix sum. It provides * the model index, x, and y to be populated. */ - PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, - const LogicalModels& models, - std::function lookup); + PerPrimitiveDimPrefixSum2D(const FlatPlacementDensityManager& density_manager, + std::function lookup); /** - * @brief Get the sum for a given model over the given region. + * @brief Get the sum for a given dim over the given region. */ - float get_model_sum(LogicalModelId model_index, - const vtr::Rect& region) const; + float get_dim_sum(PrimitiveVectorDim dim, + const vtr::Rect& region) const; /** - * @brief Get the multi-dimensional sum over the given model indices over + * @brief Get the multi-dimensional sum over the given dims over * the given region. */ - PrimitiveVector get_sum(const std::vector& model_indices, + PrimitiveVector get_sum(const std::vector& dims, const vtr::Rect& region) const; private: - /// @brief Per-Model Prefix Sums - vtr::vector> model_prefix_sum_; + /// @brief Per-Dim Prefix Sums + vtr::vector> dim_prefix_sum_; +}; + +/// @brief Tag for the PrimitiveGroupId +struct primitive_group_id_tag; + +/// @brief A unique ID of a group of primitive dims created by the PrimitiveDimGrouper class. +typedef vtr::StrongId PrimitiveGroupId; + +/** + * @brief A manager class for grouping together dimensions of the primitive + * vector which must be legalized together in a flat placement due to + * how the models they represent being associated with one another. + */ +class PrimitiveDimGrouper { + public: + // Iterator for the primitive group IDs. + typedef typename vtr::vector_map::const_iterator prim_group_iterator; + + // Range for the primitive group IDs. + typedef typename vtr::Range prim_group_range; + + public: + PrimitiveDimGrouper() = delete; + + /** + * @brief Constructor for the primitive grouper class. Groups are formed here. + * + * @param prepacker + * The prepacker used to create molecules in the flat placement. + * @param models + * The logical models in the architecture. + * @param density_manager + * The density manager object used to manage mass in the legalizer. + * @param dim_manager + * The primitive vector dimension manager. + * @param log_verbosity + * The verbosity of log messages in the grouper class. + */ + PrimitiveDimGrouper(const Prepacker& prepacker, + const LogicalModels& models, + const FlatPlacementDensityManager& density_manager, + const PrimitiveDimManager& dim_manager, + int log_verbosity); + + /** + * @brief Returns a list of all valid primitive group IDs. + */ + inline prim_group_range groups() const { + return vtr::make_range(group_ids_.begin(), group_ids_.end()); + } + + /** + * @brief Gets the primitive group ID of the given primitive dim. + */ + inline PrimitiveGroupId get_dim_group_id(PrimitiveVectorDim dim) const { + VTR_ASSERT_SAFE_MSG(dim.is_valid(), + "Cannot get the group of an invalid dim"); + PrimitiveGroupId group_id = dim_group_id_[dim]; + VTR_ASSERT_SAFE_MSG(group_id.is_valid(), + "Dim is not in a group"); + return group_id; + } + + /** + * @brief Gets the primitive dims in the given primitive group. + */ + inline const std::vector& get_dims_in_group(PrimitiveGroupId group_id) const { + VTR_ASSERT_SAFE_MSG(group_id.is_valid(), + "Invalid group id"); + VTR_ASSERT_SAFE_MSG(groups_[group_id].size() != 0, + "Group is empty"); + return groups_[group_id]; + } + + private: + /// @brief Grouper object which handles grouping together models which must + /// be spread together. Models are grouped based on the pack patterns + /// that they can form with each other. + ModelGrouper model_grouper_; + + /// @brief List of all primitive group IDs. + vtr::vector_map group_ids_; + + /// @brief A lookup between primitive dims and the group ID that contains them. + vtr::vector dim_group_id_; + + /// @brief A lookup between each primitive group ID and the dims in that group. + vtr::vector> groups_; }; /** @@ -379,6 +469,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { BiPartitioningPartialLegalizer(const APNetlist& netlist, std::shared_ptr density_manager, const Prepacker& prepacker, + const LogicalModels& models, int log_verbosity); /** @@ -424,7 +515,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { * - This allows us to ignore block models which are already in legal * positions. */ - std::vector identify_non_overlapping_windows(ModelGroupId group_id); + std::vector identify_non_overlapping_windows(PrimitiveGroupId group_id); /** * @brief Identifies clusters of overfilled bins for the given model group. @@ -432,7 +523,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { * This locates clusters of overfilled bins which are within a given * distance from each other. */ - std::vector get_overfilled_bin_clusters(ModelGroupId group_id); + std::vector get_overfilled_bin_clusters(PrimitiveGroupId group_id); /** * @brief Creates and grows minimum spanning windows around the given @@ -444,7 +535,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { */ std::vector get_min_windows_around_clusters( const std::vector& overfilled_bin_clusters, - ModelGroupId group_id); + PrimitiveGroupId group_id); /** * @brief Merges overlapping windows in the given vector of windows. @@ -459,7 +550,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { * Only blocks in the given model group will be moved. */ void move_blocks_into_windows(std::vector& non_overlapping_windows, - ModelGroupId group_id); + PrimitiveGroupId group_id); // ======================================================================== // Spreading blocks over windows @@ -474,7 +565,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { */ void spread_over_windows(std::vector& non_overlapping_windows, const PartialPlacement& p_placement, - ModelGroupId group_id); + PrimitiveGroupId group_id); /** * @brief Partition the given window into two sub-windows. @@ -483,7 +574,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { * the direction of the partition (vertical / horizontal) and the position * of the cut. */ - PartitionedWindow partition_window(SpreadingWindow& window, ModelGroupId group_id); + PartitionedWindow partition_window(SpreadingWindow& window, PrimitiveGroupId group_id); /** * @brief Partition the blocks in the given window into the partitioned @@ -495,7 +586,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { */ void partition_blocks_in_window(SpreadingWindow& window, PartitionedWindow& partitioned_window, - ModelGroupId group_id, + PrimitiveGroupId group_id, const PartialPlacement& p_placement); /** @@ -509,10 +600,11 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { /// of regions of the device. std::shared_ptr density_manager_; - /// @brief Grouper object which handles grouping together models which must - /// be spread together. Models are grouped based on the pack patterns - /// that they can form with each other. - ModelGrouper model_grouper_; + /// @brief Grouper object which handles grouping together primitive dimensions + /// which must be spread together. Dims are grouped based on the model + /// pack patterns they represent and how those models are mapped into + /// primitive vector dimensions. + PrimitiveDimGrouper dim_grouper_; /// @brief The prefix sum for the capacity of the device, as given by the /// density manager. We will need to get the capacity of 2D regions @@ -520,7 +612,7 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { /// structure greatly improves the time complexity of this operation. /// /// This is populated in the constructor and not modified. - PerModelPrefixSum2D capacity_prefix_sum_; + PerPrimitiveDimPrefixSum2D capacity_prefix_sum_; /// @brief The number of times a window was partitioned in the legalizer. unsigned num_windows_partitioned_ = 0; diff --git a/vpr/src/analytical_place/partial_placement.cpp b/vpr/src/analytical_place/partial_placement.cpp index 4e52faecef0..415c998eb9b 100644 --- a/vpr/src/analytical_place/partial_placement.cpp +++ b/vpr/src/analytical_place/partial_placement.cpp @@ -14,6 +14,8 @@ double PartialPlacement::get_hpwl(const APNetlist& netlist) const { double hpwl = 0.0; for (APNetId net_id : netlist.nets()) { + if (netlist.net_is_ignored(net_id)) + continue; double min_x = std::numeric_limits::max(); double max_x = std::numeric_limits::lowest(); double min_y = std::numeric_limits::max(); diff --git a/vpr/src/analytical_place/partial_placement.h b/vpr/src/analytical_place/partial_placement.h index bb7406fcd34..5ef0e413553 100644 --- a/vpr/src/analytical_place/partial_placement.h +++ b/vpr/src/analytical_place/partial_placement.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -10,8 +11,6 @@ * will always be on the device and will respect fixed block locations. */ -#pragma once - #include #include "ap_netlist.h" #include "physical_types.h" diff --git a/vpr/src/analytical_place/primitive_dim_manager.h b/vpr/src/analytical_place/primitive_dim_manager.h new file mode 100644 index 00000000000..79c980081d9 --- /dev/null +++ b/vpr/src/analytical_place/primitive_dim_manager.h @@ -0,0 +1,93 @@ +#pragma once +/** + * @file + * @author Alex Singer + * @date June 2025 + * @brief Declaration of the primitive dim manager class. This class manages + * the mapping between logical models in the architecture and the dimension + * in the primitive vector they correspond to. + * + * This class is populated by another class, the Mass Calculator, which decides + * the meaning of each dimension. The Mass Calculator will pick dimensions that + * make the most sense for the mass abstraction it hopes to create, and uses this + * class to keep track of the dimensions which have been created. This class is + * also passed throughout the partial legalizer in order to query about the + * dimensions in the primitive vector. + */ + +#include +#include "logic_types.h" +#include "primitive_vector_fwd.h" +#include "vtr_assert.h" +#include "vtr_range.h" +#include "vtr_vector_map.h" + +/** + * @brief A manager class for keeping track of the mapping between logical models + * and the dimension in the primitive vector data structure they represent. + * + * This class allows the order of models to be changed within the primitive vector + * data structure and allows multiple models to map to the same dimension. This + * can help improve the efficiency and quality of partial legalization. + */ +class PrimitiveDimManager { + public: + // Iterator for the primitive vector dims. + typedef typename vtr::vector_map::const_iterator dim_iterator; + + // Range for the primitive vector dims. + typedef typename vtr::Range dim_range; + + public: + /** + * @brief Returns a list of all valid primitive vector dimensions. + */ + inline dim_range dims() const { + return vtr::make_range(dims_.begin(), dims_.end()); + } + + /** + * @brief Create a mapping between the given logical model and a new dimension. + * + * The name is used only for printing debug information on this dimension. + */ + inline void create_dim(LogicalModelId model_id, const std::string& name) { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Cannot create a dim for an invalid model"); + PrimitiveVectorDim new_dim = static_cast(dims_.size()); + dims_.push_back(new_dim); + dim_name_.push_back(name); + model_dim_.insert(model_id, new_dim); + } + + /** + * @brief Get the primitive vector dim for the given model. + */ + inline PrimitiveVectorDim get_model_dim(LogicalModelId model_id) const { + VTR_ASSERT_SAFE_MSG(model_id.is_valid(), + "Cannot create a dim for an invalid model"); + if (model_dim_.count(model_id) == 0) + return PrimitiveVectorDim(); + + return model_dim_[model_id]; + } + + /** + * @brief Get the name of the given primitive vector dim. + */ + inline const std::string& get_dim_name(PrimitiveVectorDim dim) const { + VTR_ASSERT_SAFE_MSG(dim.is_valid(), + "Cannot get the name of an invalid dim"); + return dim_name_[dim]; + } + + private: + /// @brief All of the valid primitive vector dims. + vtr::vector_map dims_; + + /// @brief A lookup between logical models and their primitive dim. + vtr::vector_map model_dim_; + + /// @brief A lookup between primitive dims and their names. + vtr::vector_map dim_name_; +}; diff --git a/vpr/src/analytical_place/primitive_vector.h b/vpr/src/analytical_place/primitive_vector.h index 52b0cb8a560..31e0c016fc7 100644 --- a/vpr/src/analytical_place/primitive_vector.h +++ b/vpr/src/analytical_place/primitive_vector.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -6,15 +7,23 @@ * * This object is designed to store a sparse M-dimensional vector which can be * efficiently operated upon. + * + * Each dimensions of this vector is indexed using a PrimitiveVectorDim. These + * dims are controlled outside of this class and are used to encode more complex + * meaning based on the mass of primitives (by the Mass Calculator class). + * + * To keep track of the meaning of each dimension, the mass calculator also + * has a primitive dim manager class. That class is what holds all of the + * available dims and lookups between the models and the dims. */ -#pragma once - #include #include -#include #include #include "vtr_log.h" +#include "vtr_vector.h" + +#include "primitive_vector_fwd.h" /** * @brief A sparse vector class to store an M-dimensional quantity of primitives @@ -36,13 +45,13 @@ class PrimitiveVector { private: /// @brief Storage container for the data of this primitive vector. /// - /// This is stored as a map since it is assumed that the vector will be - /// quite sparse. This is designed to be a vector which has a dimension - /// for each t_model::index. - /// - /// TODO: Is there a more efficient way to store this sparse info? - /// Perhaps we can just waste the space and use a vector. - std::unordered_map data_; + /// Although it is assumed that the primitive vector will be quite sparse, + /// found that using an unordered map was slower than just directly using + /// a vector and leaving them empty. Instead, using a vector; but outside + /// of this class, we are careful to try and keep the most used information + /// in the early dimensions of this array so the vector can remain small in + /// length and only grow if it needs to. + vtr::vector data_; public: /** @@ -50,44 +59,36 @@ class PrimitiveVector { * * This is a common enough feature to use its own setter. */ - inline void add_val_to_dim(float val, size_t dim) { - auto it = data_.find(dim); - if (it == data_.end()) - data_.insert({dim, val}); - else { - it->second += val; - } + inline void add_val_to_dim(float val, PrimitiveVectorDim dim) { + if ((size_t)dim >= data_.size()) + data_.resize((size_t)dim + 1, 0.0f); + data_[dim] += val; } /** * @brief Subtract the value to the given dimension. */ - inline void subtract_val_from_dim(float val, size_t dim) { - auto it = data_.find(dim); - if (it == data_.end()) - data_.insert({dim, -1.0f * val}); - else { - it->second -= val; - } + inline void subtract_val_from_dim(float val, PrimitiveVectorDim dim) { + if ((size_t)dim >= data_.size()) + data_.resize((size_t)dim + 1, 0.0f); + data_[dim] -= val; } /** * @brief Get the value at the given dimension. */ - inline float get_dim_val(size_t dim) const { - const auto it = data_.find(dim); - // If there is no data in the dim, return 0. By default the vector is - // empty. - if (it == data_.end()) - return 0.f; - // If there is data at this dimension, return it. - return it->second; + inline float get_dim_val(PrimitiveVectorDim dim) const { + if ((size_t)dim >= data_.size()) + return 0.0f; + return data_[dim]; } /** * @brief Set the value at the given dimension. */ - inline void set_dim_val(size_t dim, float val) { + inline void set_dim_val(PrimitiveVectorDim dim, float val) { + if ((size_t)dim >= data_.size()) + data_.resize((size_t)dim + 1, 0.0f); data_[dim] = val; } @@ -97,14 +98,11 @@ class PrimitiveVector { * Returns true if the dimensions of each vector are equal. */ inline bool operator==(const PrimitiveVector& rhs) const { + size_t num_elem_to_check = std::max(rhs.data_.size(), data_.size()); // Check if every dim in rhs matches this. - for (const auto& p : rhs.data_) { - if (get_dim_val(p.first) != p.second) - return false; - } - // If there is anything in this which is not in rhs, need to check. - for (const auto& p : data_) { - if (rhs.get_dim_val(p.first) != p.second) + for (size_t i = 0; i < num_elem_to_check; i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; + if (get_dim_val(dim) != rhs.get_dim_val(dim)) return false; } return true; @@ -121,8 +119,9 @@ class PrimitiveVector { * @brief Element-wise accumulation of rhs into this. */ inline PrimitiveVector& operator+=(const PrimitiveVector& rhs) { - for (const auto& p : rhs.data_) { - add_val_to_dim(p.second, p.first); + for (size_t i = 0; i < rhs.data_.size(); i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; + add_val_to_dim(rhs.get_dim_val(dim), dim); } return *this; } @@ -140,8 +139,9 @@ class PrimitiveVector { * @brief Element-wise de-accumulation of rhs into this. */ inline PrimitiveVector& operator-=(const PrimitiveVector& rhs) { - for (const auto& p : rhs.data_) { - subtract_val_from_dim(p.second, p.first); + for (size_t i = 0; i < rhs.data_.size(); i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; + subtract_val_from_dim(rhs.get_dim_val(dim), dim); } return *this; } @@ -160,7 +160,7 @@ class PrimitiveVector { */ inline PrimitiveVector& operator*=(float rhs) { for (auto& p : data_) { - p.second *= rhs; + p *= rhs; } return *this; } @@ -170,7 +170,7 @@ class PrimitiveVector { */ inline PrimitiveVector& operator/=(float rhs) { for (auto& p : data_) { - p.second /= rhs; + p /= rhs; } return *this; } @@ -190,16 +190,10 @@ class PrimitiveVector { */ inline bool operator<(const PrimitiveVector& rhs) const { // Check for any element of this < rhs - for (const auto& p : data_) { - if (p.second < rhs.get_dim_val(p.first)) - return true; - } - // Check for any element of rhs > this. - // NOTE: This is required since there may be elements in rhs which are - // not in this. - // TODO: This is inneficient. - for (const auto& p : rhs.data_) { - if (p.second > get_dim_val(p.first)) + size_t num_elem_to_check = std::max(rhs.data_.size(), data_.size()); + for (size_t i = 0; i < num_elem_to_check; i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; + if (get_dim_val(dim) < rhs.get_dim_val(dim)) return true; } return false; @@ -212,11 +206,10 @@ class PrimitiveVector { * is positive, it will not change. */ inline void relu() { - std::erase_if(data_, [](const std::pair& p) { - // Note: we erase the numbers from the map to improve the performance - // of future operations on this vector. - return p.second <= 0.0f; - }); + for (float& val : data_) { + if (val < 0.0f) + val = 0.0f; + } } /** @@ -225,8 +218,8 @@ class PrimitiveVector { inline bool is_zero() const { // NOTE: This can be made cheaper by storing this information at // creation and updating it if values are added or removed. - for (const auto& p : data_) { - if (p.second != 0.f) + for (float p : data_) { + if (p != 0.f) return false; } return true; @@ -243,8 +236,8 @@ class PrimitiveVector { * @brief Returns true if all dimensions of this vector are non-negative. */ inline bool is_non_negative() const { - for (const auto& p : data_) { - if (p.second < 0.f) + for (float p : data_) { + if (p < 0.f) return false; } return true; @@ -260,8 +253,8 @@ class PrimitiveVector { // of the class and updating it whenever something is added or // removed. float mag = 0.f; - for (const auto& p : data_) { - mag += std::abs(p.second); + for (float p : data_) { + mag += std::abs(p); } return mag; } @@ -274,8 +267,8 @@ class PrimitiveVector { */ inline float sum() const { float sum = 0.f; - for (const auto& p : data_) { - sum += p.second; + for (float p : data_) { + sum += p; } return sum; } @@ -291,19 +284,28 @@ class PrimitiveVector { inline void project(const PrimitiveVector& dir) { // For each dimension of this vector, if that dimension is zero in dir // set the dimension to zero. - std::erase_if(data_, [&](const std::pair& p) { - return dir.get_dim_val(p.first) == 0.0f; - }); + size_t last_non_zero_dim = 0; + for (size_t i = 0; i < data_.size(); i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; + if (dir.get_dim_val(dim) == 0.0f) + data_[dim] = 0.0f; + else + last_non_zero_dim = i; + } + // Resize the vector to the last non-zero dim. This can improve performance + // by keeping the size of vectors as small as possible. + data_.resize(last_non_zero_dim + 1); } /** * @brief Gets the non-zero dimensions of this vector. */ - inline std::vector get_non_zero_dims() const { - std::vector non_zero_dims; - for (auto& p : data_) { - if (p.second != 0.0f) - non_zero_dims.push_back(p.first); + inline std::vector get_non_zero_dims() const { + std::vector non_zero_dims; + for (size_t i = 0; i < data_.size(); i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; + if (data_[dim] != 0.0f) + non_zero_dims.push_back(dim); } return non_zero_dims; } @@ -312,10 +314,12 @@ class PrimitiveVector { * @brief Returns true if this and other do not share any non-zero dimensions. */ inline bool are_dims_disjoint(const PrimitiveVector& other) const { - for (const auto& p : other.data_) { + size_t dims_to_check = std::min(data_.size(), other.data_.size()); + for (size_t i = 0; i < dims_to_check; i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; // If this and other both have a shared dimension, then they are not // perpendicular. - if (p.second != 0.0f && get_dim_val(p.first) != 0.0f) { + if (other.get_dim_val(dim) != 0.0f && get_dim_val(dim) != 0.0f) { return false; } } @@ -337,15 +341,11 @@ class PrimitiveVector { static inline PrimitiveVector max(const PrimitiveVector& lhs, const PrimitiveVector& rhs) { PrimitiveVector res; - // For each key in rhs, get the max(lhs, rhs) - for (const auto& p : rhs.data_) { - res.set_dim_val(p.first, - std::max(lhs.get_dim_val(p.first), p.second)); - } - // For each key in lhs, get the max(lhs, rhs) - for (const auto& p : lhs.data_) { - res.set_dim_val(p.first, - std::max(p.second, rhs.get_dim_val(p.first))); + size_t num_dims = std::max(lhs.data_.size(), rhs.data_.size()); + res.data_.resize(num_dims, 0.0f); + for (size_t i = 0; i < num_dims; i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; + res.data_[dim] = std::max(lhs.get_dim_val(dim), rhs.get_dim_val(dim)); } return res; } @@ -354,8 +354,9 @@ class PrimitiveVector { * @brief Debug printing method. */ inline void print() const { - for (const auto& p : data_) { - VTR_LOG("(%zu, %f)\n", p.first, p.second); + for (size_t i = 0; i < data_.size(); i++) { + PrimitiveVectorDim dim = (PrimitiveVectorDim)i; + VTR_LOG("(%zu, %f)\n", i, get_dim_val(dim)); } } }; diff --git a/vpr/src/analytical_place/primitive_vector_fwd.h b/vpr/src/analytical_place/primitive_vector_fwd.h new file mode 100644 index 00000000000..afaff8c6a4e --- /dev/null +++ b/vpr/src/analytical_place/primitive_vector_fwd.h @@ -0,0 +1,19 @@ +#pragma once +/** + * @file + * @author Alex Singer + * @date June 2025 + * @brief Forward declarations for the primitive vector class. + */ + +#include +#include "vtr_strong_id.h" + +/// @brief Tag for the PrimitiveVectorDim +struct primitive_vector_dim_tag; + +/// @brief A unique dimension in the PrimtiveVector class. +typedef vtr::StrongId PrimitiveVectorDim; + +// Forward declaration of the Primitive Vector class. +class PrimitiveVector; diff --git a/vpr/src/base/CheckArch.h b/vpr/src/base/CheckArch.h index 5b47ded2acb..02a6170d4a9 100644 --- a/vpr/src/base/CheckArch.h +++ b/vpr/src/base/CheckArch.h @@ -1,8 +1,5 @@ -#ifndef CHECKARCH_H -#define CHECKARCH_H +#pragma once #include "physical_types.h" void CheckArch(const t_arch& Arch); - -#endif diff --git a/vpr/src/base/CheckSetup.h b/vpr/src/base/CheckSetup.h index 69ed92cacf1..ae60adda674 100644 --- a/vpr/src/base/CheckSetup.h +++ b/vpr/src/base/CheckSetup.h @@ -1,5 +1,4 @@ -#ifndef CHECKSETUP_H -#define CHECKSETUP_H +#pragma once #include "vpr_types.h" @@ -12,5 +11,3 @@ void CheckSetup(const t_packer_opts& packer_opts, const std::vector& segments, const t_timing_inf& timing, const t_chan_width_dist& chans); - -#endif diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 9686f1b7546..f3ab1afa91f 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -1,6 +1,4 @@ -#ifndef SETUPGRID_H -#define SETUPGRID_H - +#pragma once /** * @file * @author Jason Luu @@ -22,12 +20,13 @@ DeviceGrid create_device_grid(const std::string& layout_name, float target_device_utilization = 0.0); ///@brief Find the device close in size to the specified dimensions -DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); +DeviceGrid create_device_grid(const std::string& layout_name, + const std::vector& grid_layouts, + size_t min_width, + size_t min_height); /** * @brief Returns the effective size of the device * (size of the bounding box of non-empty grid tiles) */ size_t count_grid_tiles(const DeviceGrid& grid); - -#endif diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 6824d388864..aa4a18207f4 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -589,6 +589,7 @@ void SetupAPOpts(const t_options& options, apOpts.appack_max_dist_th = options.appack_max_dist_th.value(); apOpts.num_threads = options.num_workers.value(); apOpts.log_verbosity = options.ap_verbosity.value(); + apOpts.generate_mass_report = options.ap_generate_mass_report.value(); } /** @@ -760,14 +761,16 @@ static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t if (!Arch->power) Arch->power = new t_power_arch(); - if (!Arch->clocks) - Arch->clocks = new t_clock_arch(); + if (!Arch->clocks) { + Arch->clocks = std::make_shared>(); + } device_ctx.clock_arch = Arch->clocks; + } else { Arch->power = nullptr; - Arch->clocks = nullptr; - device_ctx.clock_arch = nullptr; + Arch->clocks.reset(); + device_ctx.clock_arch.reset(); } } @@ -925,9 +928,11 @@ static void add_logical_pin_to_physical_tile(int physical_pin_offset, t_logical_block_type_ptr logical_block_ptr, t_physical_tile_type* physical_type) { for (auto logical_pin_pair : logical_block_ptr->pin_logical_num_to_pb_pin_mapping) { - auto pin_logical_num = logical_pin_pair.first; - auto pb_pin = logical_pin_pair.second; - physical_type->pin_num_to_pb_pin.insert(std::make_pair(pin_logical_num + physical_pin_offset, pb_pin)); + int pin_logical_num = logical_pin_pair.first; + t_pb_graph_pin* pb_pin = logical_pin_pair.second; + int pin_physical_num = pin_logical_num + physical_pin_offset; + physical_type->pin_num_to_pb_pin.insert({pin_physical_num, pb_pin}); + physical_type->pb_pin_to_pin_num.insert({pb_pin, pin_physical_num}); } } diff --git a/vpr/src/base/SetupVPR.h b/vpr/src/base/SetupVPR.h index 7470a1fd0c8..f72bb231bd3 100644 --- a/vpr/src/base/SetupVPR.h +++ b/vpr/src/base/SetupVPR.h @@ -1,5 +1,5 @@ -#ifndef SETUPVPR_H -#define SETUPVPR_H +#pragma once + #include #include "read_options.h" #include "physical_types.h" @@ -28,4 +28,3 @@ void SetupVPR(const t_options* Options, std::string* GraphicsCommands, t_power_opts* PowerOpts, t_vpr_setup* vpr_setup); -#endif diff --git a/vpr/src/base/ShowSetup.h b/vpr/src/base/ShowSetup.h index 2991a1f42fe..dd5415793ad 100644 --- a/vpr/src/base/ShowSetup.h +++ b/vpr/src/base/ShowSetup.h @@ -1,12 +1,11 @@ -#ifndef SHOWSETUP_H -#define SHOWSETUP_H +#pragma once #include #include #include -class t_logical_block_type; -class t_vpr_setup; +struct t_logical_block_type; +struct t_vpr_setup; struct ClusteredNetlistStats { private: @@ -35,5 +34,3 @@ struct ClusteredNetlistStats { void ShowSetup(const t_vpr_setup& vpr_setup); void writeClusteredNetlistStats(const std::string& block_usage_filename); - -#endif diff --git a/vpr/src/base/atom_lookup.h b/vpr/src/base/atom_lookup.h index 0eedbc7dc41..8dca580da9a 100644 --- a/vpr/src/base/atom_lookup.h +++ b/vpr/src/base/atom_lookup.h @@ -1,5 +1,5 @@ -#ifndef ATOM_LOOKUP_H -#define ATOM_LOOKUP_H +#pragma once + #include "atom_lookup_fwd.h" #include "vtr_vector_map.h" @@ -149,5 +149,3 @@ class AtomLookup { vtr::linear_map atom_pin_tnode_internal_; vtr::linear_map tnode_atom_pin_; }; - -#endif diff --git a/vpr/src/base/atom_lookup_fwd.h b/vpr/src/base/atom_lookup_fwd.h index 1adb2e68bb0..b7885a738f3 100644 --- a/vpr/src/base/atom_lookup_fwd.h +++ b/vpr/src/base/atom_lookup_fwd.h @@ -1,5 +1,4 @@ -#ifndef VPR_ATOM_LOOKUP_FWD_H -#define VPR_ATOM_LOOKUP_FWD_H +#pragma once class AtomLookup; @@ -7,5 +6,3 @@ enum class BlockTnode { INTERNAL, ///(name, id) - , inpad_model_(LogicalModelId::INVALID()) - , outpad_model_(LogicalModelId::INVALID()) {} + : Netlist(name, id) {} /* * * Blocks * */ -void AtomNetlist::set_block_types(LogicalModelId inpad, LogicalModelId outpad) { - VTR_ASSERT(inpad.is_valid()); - VTR_ASSERT(outpad.is_valid()); - - inpad_model_ = inpad; - outpad_model_ = outpad; -} - AtomBlockType AtomNetlist::block_type(const AtomBlockId id) const { - VTR_ASSERT(inpad_model_.is_valid()); - VTR_ASSERT(outpad_model_.is_valid()); - LogicalModelId blk_model = block_model(id); AtomBlockType type = AtomBlockType::BLOCK; - if (blk_model == inpad_model_) { + if (blk_model == LogicalModels::MODEL_INPUT_ID) { type = AtomBlockType::INPAD; - } else if (blk_model == outpad_model_) { + } else if (blk_model == LogicalModels::MODEL_OUTPUT_ID) { type = AtomBlockType::OUTPAD; } else { type = AtomBlockType::BLOCK; diff --git a/vpr/src/base/atom_netlist.h b/vpr/src/base/atom_netlist.h index 639af85c428..8f296e14bf2 100644 --- a/vpr/src/base/atom_netlist.h +++ b/vpr/src/base/atom_netlist.h @@ -1,5 +1,4 @@ -#ifndef ATOM_NETLIST_H -#define ATOM_NETLIST_H +#pragma once /** * @file @@ -65,6 +64,7 @@ * Refer to netlist.h for more information. * */ + #include #include @@ -93,11 +93,6 @@ class AtomNetlist : public Netlist> TruthTable; public: //Public Accessors - /* - * Blocks - */ - void set_block_types(LogicalModelId inpad, LogicalModelId outpad); - ///@brief Returns the type of the specified block AtomBlockType block_type(const AtomBlockId id) const; @@ -264,14 +259,6 @@ class AtomNetlist : public Netlist block_models_; //Architecture model of each block vtr::vector_map block_truth_tables_; //Truth tables of each block - // Input IOs and output IOs always exist and have their own architecture - // models. While their models are already included in block_models_, we - // also store direct pointers to them to make checks of whether a block is - // an INPAD or OUTPAD fast, as such checks are common in some netlist - // operations (e.g. clean-up of an input netlist). - LogicalModelId inpad_model_; - LogicalModelId outpad_model_; - //Port data vtr::vector_map port_models_; //Architecture port models of each port @@ -280,5 +267,3 @@ class AtomNetlist : public Netlist { } }; } // namespace std - -#endif diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index a56ea9ceb44..a5f2b1f8825 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -34,7 +34,7 @@ std::vector find_combinationally_connected_input_ports(const AtomNet ///@brief Returns the set of clock ports which are combinationally connected to output_port std::vector find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port); -bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models); +bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk); bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr); bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr); bool is_removable_output(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); @@ -137,7 +137,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod } //Latch - LogicalModelId latch_model = models.get_model_by_name(LogicalModels::MODEL_LATCH); + LogicalModelId latch_model = LogicalModels::MODEL_LATCH_ID; for (auto blk_id : netlist.blocks()) { if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) { LogicalModelId blk_model = netlist.block_model(blk_id); @@ -225,7 +225,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod } //Names - LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES); + LogicalModelId names_model = LogicalModels::MODEL_NAMES_ID; for (auto blk_id : netlist.blocks()) { if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) { LogicalModelId blk_model = netlist.block_model(blk_id); @@ -292,8 +292,8 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod } //Subckt - LogicalModelId input_model = models.get_model_by_name(LogicalModels::MODEL_INPUT); - LogicalModelId output_model = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); + LogicalModelId input_model = LogicalModels::MODEL_INPUT_ID; + LogicalModelId output_model = LogicalModels::MODEL_OUTPUT_ID; std::set subckt_models; for (auto blk_id : netlist.blocks()) { LogicalModelId blk_model = netlist.block_model(blk_id); @@ -690,7 +690,7 @@ void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int v //Remove the buffer luts for (auto blk : netlist.blocks()) { - if (is_buffer_lut(netlist, blk, models)) { + if (is_buffer_lut(netlist, blk)) { if (remove_buffer_lut(netlist, blk, models, verbosity)) { ++removed_buffer_count; } @@ -701,9 +701,9 @@ void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int v //TODO: absorb inverter LUTs? } -bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models) { +bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk) { if (netlist.block_type(blk) == AtomBlockType::BLOCK) { - const LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES); + const LogicalModelId names_model = LogicalModels::MODEL_NAMES_ID; if (netlist.block_model(blk) != names_model) return false; auto input_ports = netlist.block_input_ports(blk); @@ -1412,7 +1412,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis //to find the true source size_t assumed_buffer_count = 0; std::set prev_clock_nets; - LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); + LogicalModelId names_model_id = LogicalModels::MODEL_NAMES_ID; while (prev_clock_nets != clock_nets) { //Still tracing back prev_clock_nets = clock_nets; clock_nets.clear(); diff --git a/vpr/src/base/atom_netlist_utils.h b/vpr/src/base/atom_netlist_utils.h index 5bf0791bfad..8fda736c696 100644 --- a/vpr/src/base/atom_netlist_utils.h +++ b/vpr/src/base/atom_netlist_utils.h @@ -1,5 +1,5 @@ -#ifndef ATOM_NETLIST_UTILS_H -#define ATOM_NETLIST_UTILS_H +#pragma once + #include #include #include "atom_netlist.h" @@ -122,4 +122,3 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis ///@brief Prints out information about netlist clocks void print_netlist_clock_info(const AtomNetlist& netlist, const LogicalModels& models); -#endif diff --git a/vpr/src/base/blk_loc_registry.cpp b/vpr/src/base/blk_loc_registry.cpp index 2e5b1f2c5bb..7b392cf6a9d 100644 --- a/vpr/src/base/blk_loc_registry.cpp +++ b/vpr/src/base/blk_loc_registry.cpp @@ -125,9 +125,8 @@ void BlkLocRegistry::set_block_location(ClusterBlockId blk_id, const t_pl_loc& l location.layer); } - // Mark the grid location and usage of the block + // Mark the grid location grid_blocks_.set_block_at_location(location, blk_id); - grid_blocks_.increment_usage({location.x, location.y, location.layer}); place_sync_external_block_connections(blk_id); } @@ -172,7 +171,6 @@ void BlkLocRegistry::clear_block_type_grid_locs(const std::unordered_set& u const t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({i, j, layer_num}); int itype = type->index; if (clear_all_block_types || unplaced_blk_types_index.count(itype)) { - grid_blocks_.set_usage({i, j, layer_num}, 0); for (int k = 0; k < device_ctx.physical_tile_types[itype].capacity; k++) { grid_blocks_.set_block_at_location({i, j, k, layer_num}, ClusterBlockId::INVALID()); } @@ -267,14 +265,9 @@ void BlkLocRegistry::commit_move_blocks(const t_pl_blocks_to_be_moved& blocks_af // Remove from old location only if it hasn't already been updated by a previous block update if (grid_blocks_.block_at_location(from) == blk) { grid_blocks_.set_block_at_location(from, ClusterBlockId::INVALID()); - grid_blocks_.decrement_usage({from.x, from.y, from.layer}); } // Add to new location - if (grid_blocks_.block_at_location(to) == ClusterBlockId::INVALID()) { - //Only need to increase usage if previously unused - grid_blocks_.increment_usage({to.x, to.y, to.layer}); - } grid_blocks_.set_block_at_location(to, blk); } // Finish updating clb for all blocks diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index d8ad7fab6f6..3cce0e1a573 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -128,7 +128,6 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi static int check_clb_conn(ClusterBlockId iblk, int num_conn) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& clb_nlist = cluster_ctx.clb_nlist; - const LogicalModels& models = g_vpr_ctx.device().arch->models; int error = 0; t_logical_block_type_ptr type = clb_nlist.block_type(iblk); @@ -137,7 +136,7 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) { for (auto pin_id : clb_nlist.block_pins(iblk)) { auto pin_type = clb_nlist.pin_type(pin_id); - if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk, models)) { + if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk)) { //Input only and not a Primary-Output block VTR_LOG_WARN( "Logic block #%d (%s) has only 1 input pin '%s'" @@ -145,7 +144,7 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) { iblk, clb_nlist.block_name(iblk).c_str(), clb_nlist.pin_name(pin_id).c_str()); } - if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk, models)) { + if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk)) { //Output only and not a Primary-Input block VTR_LOG_WARN( "Logic block #%d (%s) has only 1 output pin '%s'." diff --git a/vpr/src/base/check_netlist.h b/vpr/src/base/check_netlist.h index c21bef5be0c..9936cd81b4e 100644 --- a/vpr/src/base/check_netlist.h +++ b/vpr/src/base/check_netlist.h @@ -1,6 +1,3 @@ -#ifndef CHECK_NETLIST_H -#define CHECK_NETLIST_H +#pragma once void check_netlist(int verbosity); - -#endif diff --git a/vpr/src/base/clock_modeling.h b/vpr/src/base/clock_modeling.h index 9bf685ec86d..c6d2ef240a7 100644 --- a/vpr/src/base/clock_modeling.h +++ b/vpr/src/base/clock_modeling.h @@ -1,5 +1,4 @@ -#ifndef CLOCK_MODELING_H -#define CLOCK_MODELING_H +#pragma once enum e_clock_modeling { IDEAL_CLOCK, ///find_pb_for_model(input_model_id); return primary_input_pb != nullptr; } ///@brief Returns true if the specified block contains a primary output (e.g. BLIF .output primitive) -bool ClusteredNetlist::block_contains_primary_output(const ClusterBlockId blk, const LogicalModels& models) const { +bool ClusteredNetlist::block_contains_primary_output(const ClusterBlockId blk) const { const t_pb* pb = block_pb(blk); - LogicalModelId output_model_id = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); + LogicalModelId output_model_id = LogicalModels::MODEL_OUTPUT_ID; const t_pb* primary_output_pb = pb->find_pb_for_model(output_model_id); return primary_output_pb != nullptr; } diff --git a/vpr/src/base/clustered_netlist.h b/vpr/src/base/clustered_netlist.h index c711b13262a..ddde85aacc2 100644 --- a/vpr/src/base/clustered_netlist.h +++ b/vpr/src/base/clustered_netlist.h @@ -1,5 +1,4 @@ -#ifndef CLUSTERED_NETLIST_H -#define CLUSTERED_NETLIST_H +#pragma once /** * @file * @brief This file defines the ClusteredNetlist class in the ClusteredContext @@ -141,10 +140,10 @@ class ClusteredNetlist : public Netlist { } }; } // namespace std - -#endif diff --git a/vpr/src/base/clustered_netlist_utils.h b/vpr/src/base/clustered_netlist_utils.h index b5d1504ed91..3c81650f92b 100644 --- a/vpr/src/base/clustered_netlist_utils.h +++ b/vpr/src/base/clustered_netlist_utils.h @@ -1,5 +1,4 @@ -#ifndef CLUSTERED_NETLIST_UTILS_H -#define CLUSTERED_NETLIST_UTILS_H +#pragma once #include "vtr_vector.h" #include "vtr_range.h" @@ -46,4 +45,3 @@ class ClusterAtomsLookup { //Store the atom ids of the atoms inside each cluster vtr::vector> cluster_atoms; }; -#endif diff --git a/vpr/src/base/constant_nets.h b/vpr/src/base/constant_nets.h index 8bf943b8bc8..8847b325973 100644 --- a/vpr/src/base/constant_nets.h +++ b/vpr/src/base/constant_nets.h @@ -1,5 +1,4 @@ -#ifndef CONSTANT_NETS_H -#define CONSTANT_NETS_H +#pragma once #include "clustered_netlist_fwd.h" #include "atom_netlist_fwd.h" @@ -10,5 +9,3 @@ enum e_constant_net_method { }; void process_constant_nets(AtomNetlist& atom_nlist, const AtomLookup& atom_look_up, ClusteredNetlist& nlist, e_constant_net_method method, int verbosity); - -#endif diff --git a/vpr/src/base/constraints_load.h b/vpr/src/base/constraints_load.h index bf57b571aac..8a097697fe5 100644 --- a/vpr/src/base/constraints_load.h +++ b/vpr/src/base/constraints_load.h @@ -1,9 +1,6 @@ -#ifndef CONSTRAINTS_LOAD_H_ -#define CONSTRAINTS_LOAD_H_ +#pragma once #include "user_place_constraints.h" ///@brief Used to print vpr's floorplanning constraints to an echo file "vpr_constraints.echo" void echo_constraints(char* filename, const UserPlaceConstraints& constraints); - -#endif diff --git a/vpr/src/base/echo_files.h b/vpr/src/base/echo_files.h index 9828ef62ec8..ac38f2e55f9 100644 --- a/vpr/src/base/echo_files.h +++ b/vpr/src/base/echo_files.h @@ -1,5 +1,4 @@ -#ifndef ECHO_FILES_H -#define ECHO_FILES_H +#pragma once #include @@ -99,5 +98,3 @@ void setOutputFileName(enum e_output_files ename, const char* name, const char* char* getOutputFileName(enum e_output_files ename); void alloc_and_load_output_file_names(const std::string& default_name); void free_output_file_names(); - -#endif diff --git a/vpr/src/base/flat_placement_types.h b/vpr/src/base/flat_placement_types.h index 6ece9b2d318..b725751a05c 100644 --- a/vpr/src/base/flat_placement_types.h +++ b/vpr/src/base/flat_placement_types.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -5,8 +6,6 @@ * @brief Declaration of flat placement types used throughout VPR. */ -#pragma once - #include "atom_netlist.h" #include "vtr_assert.h" #include "vtr_vector.h" diff --git a/vpr/src/base/flat_placement_utils.h b/vpr/src/base/flat_placement_utils.h index eef37489585..16a4641a01f 100644 --- a/vpr/src/base/flat_placement_utils.h +++ b/vpr/src/base/flat_placement_utils.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -5,8 +6,6 @@ * @brief Utility methods for working with flat placements. */ -#pragma once - #include #include "flat_placement_types.h" diff --git a/vpr/src/base/globals.h b/vpr/src/base/globals.h index cbbbe3a75e3..1b813e33629 100644 --- a/vpr/src/base/globals.h +++ b/vpr/src/base/globals.h @@ -1,12 +1,9 @@ +#pragma once /* * Global variables * Key global variables that are used everywhere in VPR: */ -#ifndef GLOBALS_H -#define GLOBALS_H #include "vpr_context.h" extern VprContext g_vpr_ctx; - -#endif diff --git a/vpr/src/base/grid_block.cpp b/vpr/src/base/grid_block.cpp index 4a6e35b0aba..e89ba6555aa 100644 --- a/vpr/src/base/grid_block.cpp +++ b/vpr/src/base/grid_block.cpp @@ -17,7 +17,7 @@ void GridBlock::init_grid_blocks(const DeviceGrid& device_grid) { for (size_t x = 0; x < grid_width; x++) { for (size_t y = 0; y < grid_height; y++) { const t_physical_tile_loc tile_loc({(int)x, (int)y, (int)layer_num}); - auto type = device_grid.get_physical_type(tile_loc); + t_physical_tile_type_ptr type = device_grid.get_physical_type(tile_loc); initialized_grid_block_at_location(tile_loc, type->capacity); } } @@ -25,17 +25,16 @@ void GridBlock::init_grid_blocks(const DeviceGrid& device_grid) { } void GridBlock::zero_initialize() { - auto& device_ctx = g_vpr_ctx.device(); + const DeviceContext& device_ctx = g_vpr_ctx.device(); /* Initialize all occupancy to zero. */ for (int layer_num = 0; layer_num < (int)device_ctx.grid.get_num_layers(); layer_num++) { for (int i = 0; i < (int)device_ctx.grid.width(); i++) { for (int j = 0; j < (int)device_ctx.grid.height(); j++) { - set_usage({i, j, layer_num}, 0); - auto tile = device_ctx.grid.get_physical_type({i, j, layer_num}); + t_physical_tile_type_ptr tile = device_ctx.grid.get_physical_type({i, j, layer_num}); - for (const auto& sub_tile : tile->sub_tiles) { - auto capacity = sub_tile.capacity; + for (const t_sub_tile& sub_tile : tile->sub_tiles) { + t_capacity_range capacity = sub_tile.capacity; for (int k = 0; k < capacity.total(); k++) { set_block_at_location({i, j, k + capacity.low, layer_num}, ClusterBlockId::INVALID()); @@ -47,8 +46,8 @@ void GridBlock::zero_initialize() { } void GridBlock::load_from_block_locs(const vtr::vector_map& block_locs) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& device_ctx = g_vpr_ctx.device(); + const ClusteringContext& cluster_ctx = g_vpr_ctx.clustering(); + const DeviceContext& device_ctx = g_vpr_ctx.device(); zero_initialize(); @@ -59,20 +58,5 @@ void GridBlock::load_from_block_locs(const vtr::vector_map(sub_tile))) + usage++; + } + return usage; } inline bool is_sub_tile_empty(const t_physical_tile_loc loc, int sub_tile) const { @@ -89,12 +93,6 @@ class GridBlock { */ void load_from_block_locs(const vtr::vector_map& block_locs); - int increment_usage(const t_physical_tile_loc& loc); - - int decrement_usage(const t_physical_tile_loc& loc); - private: vtr::NdMatrix grid_blocks_; }; - -#endif //VTR_GRID_BLOCK_H diff --git a/vpr/src/base/load_flat_place.h b/vpr/src/base/load_flat_place.h index 3c25780fc57..7776d7f658f 100644 --- a/vpr/src/base/load_flat_place.h +++ b/vpr/src/base/load_flat_place.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -8,8 +9,6 @@ * flat placement information to different parts of the VPR flow. */ -#pragma once - #include #include #include "vtr_vector_map.h" diff --git a/vpr/src/base/logic_vec.h b/vpr/src/base/logic_vec.h index e921debdb49..8ecb94f0644 100644 --- a/vpr/src/base/logic_vec.h +++ b/vpr/src/base/logic_vec.h @@ -1,5 +1,4 @@ -#ifndef LOGIC_VEC_H -#define LOGIC_VEC_H +#pragma once #include #include @@ -45,5 +44,3 @@ class LogicVec { private: std::vector values_; /// @@ -176,5 +175,3 @@ Container update_valid_refs(const Container& values, } return updated; } - -#endif diff --git a/vpr/src/base/netlist_walker.h b/vpr/src/base/netlist_walker.h index 93c807a074a..c2dc6dd2411 100644 --- a/vpr/src/base/netlist_walker.h +++ b/vpr/src/base/netlist_walker.h @@ -1,5 +1,5 @@ -#ifndef NETLIST_WALKER_H -#define NETLIST_WALKER_H +#pragma once + #include "vpr_types.h" class NetlistVisitor; @@ -59,4 +59,3 @@ class NetlistVisitor { virtual void finish_impl(); }; -#endif diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index 8a02b9a7be1..c5e41113ee5 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -2689,22 +2689,8 @@ void add_original_sdc_to_post_implemented_sdc_file(std::ofstream& sdc_os, * * @param sdc_os * The file stream to add the propagated clock commands to. - * @param clock_modeling - * The type of clock modeling used by VPR during the CAD flow. */ -void add_propagated_clocks_to_sdc_file(std::ofstream& sdc_os, - e_clock_modeling clock_modeling) { - - // Ideal and routed clocks are handled by the code below. Other clock models - // like dedicated routing are not supported yet. - // TODO: Supporting dedicated routing should be simple; however it should - // be investigated. Tried quickly but found that the delays produced - // were off by 0.003 ns. Need to investigate why. - if (clock_modeling != e_clock_modeling::ROUTED_CLOCK && clock_modeling != e_clock_modeling::IDEAL_CLOCK) { - VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, - "Only ideal and routed clock modeling are currentlt " - "supported for post-implementation SDC file generation"); - } +void add_propagated_clocks_to_sdc_file(std::ofstream& sdc_os) { // The timing constraints contain information on all the clocks in the circuit // (provided by the user-provided SDC file). @@ -2730,8 +2716,8 @@ void add_propagated_clocks_to_sdc_file(std::ofstream& sdc_os, sdc_os << "#******************************************************************************#\n"; sdc_os << "# The following are clock domains in VPR which have delays on their edges.\n"; sdc_os << "#\n"; - sdc_os << "# Any non-virtual clock has its delay determined and written out as part of a"; - sdc_os << "# propagated clock command. If VPR was instructed not to route the clock, this"; + sdc_os << "# Any non-virtual clock has its delay determined and written out as part of a\n"; + sdc_os << "# propagated clock command. If VPR was instructed not to route the clock, this\n"; sdc_os << "# delay will be an underestimate.\n"; sdc_os << "#\n"; sdc_os << "# Note: Virtual clocks do not get routed and are treated as ideal.\n"; @@ -2751,18 +2737,15 @@ void add_propagated_clocks_to_sdc_file(std::ofstream& sdc_os, /** * @brief Generates a post-implementation SDC file with the given file name - * based on the timing info and clock modeling set for VPR. + * based on the timing info used for VPR. * * @param sdc_filename * The file name of the SDC file to generate. * @param timing_info * Information on the timing used in the VPR flow. - * @param clock_modeling - * The type of clock modeling used by VPR during its flow. */ void generate_post_implementation_sdc(const std::string& sdc_filename, - const t_timing_inf& timing_info, - e_clock_modeling clock_modeling) { + const t_timing_inf& timing_info) { if (!timing_info.timing_analysis_enabled) { VTR_LOG_WARN("Timing analysis is disabled. Post-implementation SDC file " "will not be generated.\n"); @@ -2783,7 +2766,7 @@ void generate_post_implementation_sdc(const std::string& sdc_filename, add_original_sdc_to_post_implemented_sdc_file(sdc_os, timing_info); // Add propagated clocks to SDC file if needed. - add_propagated_clocks_to_sdc_file(sdc_os, clock_modeling); + add_propagated_clocks_to_sdc_file(sdc_os); } } // namespace @@ -2797,7 +2780,6 @@ void netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, const t_timing_inf& timing_info, - e_clock_modeling clock_modeling, t_analysis_opts opts) { std::string verilog_filename = basename + "_post_synthesis.v"; std::string blif_filename = basename + "_post_synthesis.blif"; @@ -2822,8 +2804,7 @@ void netlist_writer(const std::string basename, VTR_LOG("Writing Implementation SDC : %s\n", sdc_filename.c_str()); generate_post_implementation_sdc(sdc_filename, - timing_info, - clock_modeling); + timing_info); } } diff --git a/vpr/src/base/netlist_writer.h b/vpr/src/base/netlist_writer.h index 64ce79e6687..67ada9d54ec 100644 --- a/vpr/src/base/netlist_writer.h +++ b/vpr/src/base/netlist_writer.h @@ -24,8 +24,6 @@ class LogicalModels; * The logical models in the architecture. * @param timing_info * Information on the timing used in the VPR flow. - * @param clock_modeling - * The type of clock modeling used in the VPR flow. * @param opts * The analysis options. */ @@ -33,7 +31,6 @@ void netlist_writer(const std::string basename, std::shared_ptr delay_calc, const LogicalModels& models, const t_timing_inf& timing_info, - e_clock_modeling clock_modeling, t_analysis_opts opts); /** diff --git a/vpr/src/base/partition.h b/vpr/src/base/partition.h index 1772d47a0fc..a86b3150272 100644 --- a/vpr/src/base/partition.h +++ b/vpr/src/base/partition.h @@ -1,5 +1,4 @@ -#ifndef PARTITION_H -#define PARTITION_H +#pragma once #include @@ -59,5 +58,3 @@ class Partition { ///@brief used to print data from a Partition void print_partition(FILE* fp, const Partition& part); - -#endif /* PARTITION_H */ diff --git a/vpr/src/base/partition_region.h b/vpr/src/base/partition_region.h index 80f3a2f36a7..95e29280b1d 100644 --- a/vpr/src/base/partition_region.h +++ b/vpr/src/base/partition_region.h @@ -1,5 +1,4 @@ -#ifndef PARTITION_REGIONS_H -#define PARTITION_REGIONS_H +#pragma once #include "region.h" #include "vpr_types.h" @@ -106,5 +105,3 @@ struct hash { } }; } // namespace std - -#endif /* PARTITION_REGIONS_H */ diff --git a/vpr/src/base/place_and_route.h b/vpr/src/base/place_and_route.h index 935f678841e..a67712d694d 100644 --- a/vpr/src/base/place_and_route.h +++ b/vpr/src/base/place_and_route.h @@ -1,5 +1,4 @@ -#ifndef VPR_PLACE_AND_ROUTE_H -#define VPR_PLACE_AND_ROUTE_H +#pragma once #define INFINITE -1 @@ -43,5 +42,3 @@ t_chan_width init_chan(int cfactor, e_graph_type graph_directionality); void post_place_sync(); - -#endif diff --git a/vpr/src/base/read_activity.h b/vpr/src/base/read_activity.h index 51be12a201c..43830ea723c 100644 --- a/vpr/src/base/read_activity.h +++ b/vpr/src/base/read_activity.h @@ -1,10 +1,8 @@ -#ifndef READ_ACTIVITY_H -#define READ_ACTIVITY_H +#pragma once + #include #include "atom_netlist_fwd.h" #include "vpr_types.h" std::unordered_map read_activity(const AtomNetlist& netlist, const char* activity_file); - -#endif diff --git a/vpr/src/base/read_blif.cpp b/vpr/src/base/read_blif.cpp index 9e0668e39d1..0d5e25a02c0 100644 --- a/vpr/src/base/read_blif.cpp +++ b/vpr/src/base/read_blif.cpp @@ -46,10 +46,6 @@ struct BlifAllocCallback : public blifparse::Callback { , blif_format_(blif_format) { VTR_ASSERT(blif_format_ == e_circuit_format::BLIF || blif_format_ == e_circuit_format::EBLIF); - inpad_model_ = models.get_model_by_name(LogicalModels::MODEL_INPUT); - outpad_model_ = models.get_model_by_name(LogicalModels::MODEL_OUTPUT); - - main_netlist_.set_block_types(inpad_model_, outpad_model_); } static constexpr const char* OUTPAD_NAME_PREFIX = "out:"; @@ -69,14 +65,13 @@ struct BlifAllocCallback : public blifparse::Callback { //Create a new model, and set it's name blif_models_.emplace_back(model_name, netlist_id_); - blif_models_.back().set_block_types(inpad_model_, outpad_model_); blif_models_black_box_.emplace_back(false); ended_ = false; set_curr_block(AtomBlockId::INVALID()); //This statement doesn't define a block, so mark invalid } void inputs(std::vector input_names) override { - LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_INPUT); + LogicalModelId blk_model_id = LogicalModels::MODEL_INPUT_ID; const t_model& blk_model = models_.get_model(blk_model_id); VTR_ASSERT_MSG(!blk_model.inputs, "Inpad model has an input port"); @@ -95,7 +90,7 @@ struct BlifAllocCallback : public blifparse::Callback { } void outputs(std::vector output_names) override { - LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_OUTPUT); + LogicalModelId blk_model_id = LogicalModels::MODEL_OUTPUT_ID; const t_model& blk_model = models_.get_model(blk_model_id); VTR_ASSERT_MSG(!blk_model.outputs, "Outpad model has an output port"); @@ -116,7 +111,7 @@ struct BlifAllocCallback : public blifparse::Callback { } void names(std::vector nets, std::vector> so_cover) override { - LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_NAMES); + LogicalModelId blk_model_id = LogicalModels::MODEL_NAMES_ID; const t_model& blk_model = models_.get_model(blk_model_id); VTR_ASSERT_MSG(nets.size() > 0, "BLIF .names has no connections"); @@ -200,7 +195,7 @@ struct BlifAllocCallback : public blifparse::Callback { vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "Latch must have a clock\n"); } - LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_LATCH); + LogicalModelId blk_model_id = LogicalModels::MODEL_LATCH_ID; const t_model& blk_model = models_.get_model(blk_model_id); VTR_ASSERT_MSG(blk_model.inputs, "Has one input port"); @@ -618,8 +613,6 @@ struct BlifAllocCallback : public blifparse::Callback { AtomNetlist& main_netlist_; /// #include "atom_netlist_fwd.h" @@ -14,5 +13,3 @@ bool is_real_param(const std::string& param); AtomNetlist read_blif(e_circuit_format circuit_format, const char* blif_file, const LogicalModels& models); - -#endif /*READ_BLIF_H*/ diff --git a/vpr/src/base/read_circuit.cpp b/vpr/src/base/read_circuit.cpp index f1112d92016..152a627d77d 100644 --- a/vpr/src/base/read_circuit.cpp +++ b/vpr/src/base/read_circuit.cpp @@ -149,7 +149,7 @@ static void show_circuit_stats(const AtomNetlist& netlist, const LogicalModels& // Count the block statistics std::map block_type_counts; std::map lut_size_counts; - LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); + LogicalModelId names_model_id = LogicalModels::MODEL_NAMES_ID; for (auto blk_id : netlist.blocks()) { // For each model, count the number of occurrences in the netlist. LogicalModelId blk_model_id = netlist.block_model(blk_id); diff --git a/vpr/src/base/read_circuit.h b/vpr/src/base/read_circuit.h index 89f42f7ec61..e2472ff9179 100644 --- a/vpr/src/base/read_circuit.h +++ b/vpr/src/base/read_circuit.h @@ -1,5 +1,4 @@ -#ifndef VPR_READ_CIRCUIT_H -#define VPR_READ_CIRCUIT_H +#pragma once #include "atom_netlist_fwd.h" @@ -14,4 +13,3 @@ enum class e_circuit_format { }; AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch); -#endif diff --git a/vpr/src/base/read_interchange_netlist.cpp b/vpr/src/base/read_interchange_netlist.cpp index d327d351a73..710e484af1d 100644 --- a/vpr/src/base/read_interchange_netlist.cpp +++ b/vpr/src/base/read_interchange_netlist.cpp @@ -54,10 +54,6 @@ struct NetlistReader { auto str_list = nr_.getStrList(); main_netlist_ = AtomNetlist(str_list[top_cell_instance_.getName()], netlist_id); - inpad_model_ = models_.get_model_by_name(LogicalModels::MODEL_INPUT); - outpad_model_ = models_.get_model_by_name(LogicalModels::MODEL_OUTPUT); - main_netlist_.set_block_types(inpad_model_, outpad_model_); - prepare_port_net_maps(); VTR_LOG("Reading IOs...\n"); @@ -75,8 +71,6 @@ struct NetlistReader { const char* netlist_file_; - LogicalModelId inpad_model_; - LogicalModelId outpad_model_; const LogicalModels& models_; const t_arch& arch_; @@ -137,9 +131,9 @@ struct NetlistReader { } void read_ios() { - LogicalModelId input_model_id = models_.get_model_by_name(LogicalModels::MODEL_INPUT); + LogicalModelId input_model_id = LogicalModels::MODEL_INPUT_ID; const t_model& input_model = models_.get_model(input_model_id); - LogicalModelId output_model_id = models_.get_model_by_name(LogicalModels::MODEL_OUTPUT); + LogicalModelId output_model_id = LogicalModels::MODEL_OUTPUT_ID; const t_model& output_model = models_.get_model(output_model_id); auto str_list = nr_.getStrList(); @@ -187,7 +181,7 @@ struct NetlistReader { } void read_names() { - LogicalModelId blk_model_id = models_.get_model_by_name(LogicalModels::MODEL_NAMES); + LogicalModelId blk_model_id = LogicalModels::MODEL_NAMES_ID; const t_model& blk_model = models_.get_model(blk_model_id); // Set the max size of the LUT diff --git a/vpr/src/base/read_interchange_netlist.h b/vpr/src/base/read_interchange_netlist.h index 02a7546c660..b8c2a2cc05f 100644 --- a/vpr/src/base/read_interchange_netlist.h +++ b/vpr/src/base/read_interchange_netlist.h @@ -1,5 +1,4 @@ -#ifndef READ_INTERCHANGE_NETLIST_H -#define READ_INTERCHANGE_NETLIST_H +#pragma once #include "atom_netlist_fwd.h" @@ -7,5 +6,3 @@ struct t_arch; AtomNetlist read_interchange_netlist(const char* ic_netlist_file, t_arch& arch); - -#endif /*READ_INTERCHANGE_NETLIST_H*/ diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index eb2638ee4c0..50d0b75d87c 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -755,6 +755,7 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route, pb_route.insert(std::make_pair(rr_node_index, t_pb_route())); pb_route[rr_node_index].driver_pb_pin_id = pin_node[0][0]->pin_count_in_cluster; pb_route[rr_node_index].pb_graph_pin = pb_gpin; + VTR_ASSERT(pb_route[rr_node_index].pb_graph_pin->pin_number == i); found = false; for (j = 0; j < pin_node[0][0]->num_output_edges; j++) { diff --git a/vpr/src/base/read_netlist.h b/vpr/src/base/read_netlist.h index 090ded87a08..7d21f772542 100644 --- a/vpr/src/base/read_netlist.h +++ b/vpr/src/base/read_netlist.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Jason Luu @@ -7,9 +8,6 @@ * the netlist data structures for VPR */ -#ifndef READ_NETLIST_H -#define READ_NETLIST_H - #include "atom_netlist_fwd.h" #include "clustered_netlist_fwd.h" #include "physical_types.h" @@ -23,5 +21,3 @@ void set_atom_pin_mapping(const ClusteredNetlist& clb_nlist, const AtomBlockId atom_blk, const AtomPortId atom_port, const t_pb_graph_pin* gpin); - -#endif diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 75bf7385b61..674327b1c4e 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1584,6 +1584,11 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .help("Show version information then exit") .action(argparse::Action::VERSION); + gen_grp.add_argument(args.show_arch_resources, "--show_arch_resources") + .help("Show architecture resources then exit") + .action(argparse::Action::STORE_TRUE) + .default_value("off"); + gen_grp.add_argument(args.device_layout, "--device") .help( "Controls which device layout/floorplan is used from the architecture file." @@ -1978,6 +1983,15 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("1") .show_in(argparse::ShowIn::HELP_ONLY); + ap_grp.add_argument(args.ap_generate_mass_report, "--ap_generate_mass_report") + .help( + "Controls whether to generate a report on how the partial legalizer " + "within the AP flow calculates the mass of primitives and the " + "capacity of tiles on the device. This report is useful when " + "debugging the partial legalizer.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + auto& pack_grp = parser.add_argument_group("packing options"); pack_grp.add_argument(args.connection_driven_clustering, "--connection_driven_clustering") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 03153ac1446..72d753d108f 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -1,5 +1,4 @@ -#ifndef READ_OPTIONS_H -#define READ_OPTIONS_H +#pragma once #include "arch_types.h" #include "read_circuit.h" @@ -68,6 +67,7 @@ struct t_options { /* General options */ argparse::ArgValue show_help; argparse::ArgValue show_version; + argparse::ArgValue show_arch_resources; argparse::ArgValue num_workers; argparse::ArgValue timing_analysis; argparse::ArgValue timing_update_type; @@ -106,6 +106,7 @@ struct t_options { argparse::ArgValue> appack_max_dist_th; argparse::ArgValue ap_verbosity; argparse::ArgValue ap_timing_tradeoff; + argparse::ArgValue ap_generate_mass_report; /* Clustering options */ argparse::ArgValue connection_driven_clustering; @@ -280,5 +281,3 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio t_options read_options(int argc, const char** argv); void set_conditional_defaults(t_options& args); bool verify_args(const t_options& args); - -#endif diff --git a/vpr/src/base/read_place.h b/vpr/src/base/read_place.h index dbce07b77ef..955a0ac3153 100644 --- a/vpr/src/base/read_place.h +++ b/vpr/src/base/read_place.h @@ -1,5 +1,4 @@ -#ifndef READ_PLACE_H -#define READ_PLACE_H +#pragma once #include "vtr_vector_map.h" @@ -43,5 +42,3 @@ std::string print_place(const char* net_file, const char* place_file, const vtr::vector_map& block_locs, bool is_place_file = true); - -#endif diff --git a/vpr/src/base/read_route.h b/vpr/src/base/read_route.h index 4758b0cf646..95f9c516498 100644 --- a/vpr/src/base/read_route.h +++ b/vpr/src/base/read_route.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @brief Functions to read/write a .route file, which contains a serialized routing state. @@ -5,8 +6,6 @@ * This is used to perform --analysis only */ -#pragma once - #include "netlist.h" #include "vpr_types.h" diff --git a/vpr/src/base/region.h b/vpr/src/base/region.h index 08959f1bdc6..d8d86cbf303 100644 --- a/vpr/src/base/region.h +++ b/vpr/src/base/region.h @@ -1,5 +1,4 @@ -#ifndef REGION_H -#define REGION_H +#pragma once #include "vtr_geometry.h" #include "vpr_types.h" @@ -130,5 +129,3 @@ struct hash { } }; } // namespace std - -#endif /* REGION_H */ diff --git a/vpr/src/base/setup_clocks.h b/vpr/src/base/setup_clocks.h index 0687cc68589..749a4ff01c8 100644 --- a/vpr/src/base/setup_clocks.h +++ b/vpr/src/base/setup_clocks.h @@ -1,10 +1,7 @@ -#ifndef SETUP_CLOCKS_H -#define SETUP_CLOCKS_H +#pragma once #include #include "physical_types.h" void setup_clock_networks(const t_arch& Arch, std::vector& segment_inf); - -#endif diff --git a/vpr/src/base/setup_noc.h b/vpr/src/base/setup_noc.h index 4b11f59259a..81bfcd4a5b6 100644 --- a/vpr/src/base/setup_noc.h +++ b/vpr/src/base/setup_noc.h @@ -1,6 +1,4 @@ -#ifndef SETUP_NOC -#define SETUP_NOC - +#pragma once /** * @file * @brief This is the setup_noc header file. The main purpose of @@ -129,5 +127,3 @@ void create_noc_routers(const t_noc_inf& noc_info, * routers and links that connect the routers together. */ void create_noc_links(const t_noc_inf& noc_info, NocStorage* noc_model); - -#endif diff --git a/vpr/src/base/user_place_constraints.h b/vpr/src/base/user_place_constraints.h index 65043f5d4ad..2662f84360f 100644 --- a/vpr/src/base/user_place_constraints.h +++ b/vpr/src/base/user_place_constraints.h @@ -1,5 +1,4 @@ -#ifndef USER_PLACE_CONSTRAINTS_H -#define USER_PLACE_CONSTRAINTS_H +#pragma once #include "vtr_vector.h" #include "partition.h" @@ -113,5 +112,3 @@ class UserPlaceConstraints { ///@brief used to print floorplanning constraints data from a VprConstraints object void print_placement_constraints(FILE* fp, const UserPlaceConstraints& constraints); - -#endif /* USER_PLACE_CONSTRAINTS_H */ diff --git a/vpr/src/base/user_route_constraints.h b/vpr/src/base/user_route_constraints.h index 0510072a36a..2df0206adf9 100644 --- a/vpr/src/base/user_route_constraints.h +++ b/vpr/src/base/user_route_constraints.h @@ -1,5 +1,4 @@ -#ifndef USER_ROUTE_CONSTRAINTS_H -#define USER_ROUTE_CONSTRAINTS_H +#pragma once #include "clock_modeling.h" #include @@ -152,4 +151,3 @@ class UserRouteConstraints { */ std::unordered_map route_constraints_; }; -#endif /* USER_ROUTE_CONSTRAINTS_H */ diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 7eda86f8dd6..fc0c3e32b46 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -106,6 +106,10 @@ #include "serverupdate.h" #endif /* NO_SERVER */ +#ifndef NO_GRAPHICS +#include "draw_global.h" +#endif // NO_GRAPHICS + /* Local subroutines */ static void free_complex_block_types(); @@ -389,6 +393,48 @@ static void unset_port_equivalences(DeviceContext& device_ctx) { } } +void vpr_print_arch_resources(const t_vpr_setup& vpr_setup, const t_arch& Arch) { + vtr::ScopedStartFinishTimer timer("Build Device Grid"); + /* Read in netlist file for placement and routing */ + auto& device_ctx = g_vpr_ctx.mutable_device(); + + device_ctx.arch = &Arch; + + /* + *Load the device grid + */ + + //Record the resource requirement + std::map num_type_instances; + + //Build the device + for (const t_grid_def& l : Arch.grid_layouts) { + float target_device_utilization = vpr_setup.PackerOpts.target_device_utilization; + device_ctx.grid = create_device_grid(l.name, Arch.grid_layouts, num_type_instances, target_device_utilization); + + /* + *Report on the device + */ + size_t num_grid_tiles = count_grid_tiles(device_ctx.grid); + VTR_LOG("FPGA sized to %zu x %zu: %zu grid tiles (%s)\n", device_ctx.grid.width(), device_ctx.grid.height(), num_grid_tiles, device_ctx.grid.name().c_str()); + + std::string title("\nResource usage for device layout " + l.name + "...\n"); + VTR_LOG(title.c_str()); + for (const t_logical_block_type& type : device_ctx.logical_block_types) { + if (is_empty_type(&type)) continue; + + VTR_LOG("\tArchitecture\n"); + for (const t_physical_tile_type_ptr equivalent_tile : type.equivalent_tiles) { + //get the number of equivalent tile across all layers + int num_instances = (int)device_ctx.grid.num_instances(equivalent_tile, -1); + + VTR_LOG("\t\t%d\tblocks of type: %s\n", + num_instances, equivalent_tile->name.c_str()); + } + } + } +} + bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { if (vpr_setup.exit_before_pack) { VTR_LOG_WARN("Exiting before packing as requested.\n"); @@ -421,7 +467,8 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { } // TODO: Placer still assumes that cluster net list is used - graphics can not work with flat routing yet - vpr_init_graphics(vpr_setup, arch, false); + bool is_flat = vpr_setup.RouterOpts.flat_routing; + vpr_init_graphics(vpr_setup, arch, is_flat); vpr_init_server(vpr_setup); @@ -465,7 +512,6 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { block_locs); } - bool is_flat = vpr_setup.RouterOpts.flat_routing; const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; if (is_flat) { VTR_LOG_WARN("Disabling port equivalence in the architecture since flat routing is enabled.\n"); @@ -1478,8 +1524,11 @@ void vpr_analysis(const Netlist<>& net_list, //Write the post-synthesis netlist if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) { - netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, - Arch.models, vpr_setup.Timing, vpr_setup.clock_modeling, vpr_setup.AnalysisOpts); + netlist_writer(atom_ctx.netlist().netlist_name(), + analysis_delay_calc, + Arch.models, + vpr_setup.Timing, + vpr_setup.AnalysisOpts); } //Write the post-implementation merged netlist diff --git a/vpr/src/base/vpr_api.h b/vpr/src/base/vpr_api.h index 02fb56a46b4..7147691ba73 100644 --- a/vpr/src/base/vpr_api.h +++ b/vpr/src/base/vpr_api.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Jason Luu @@ -24,9 +25,6 @@ * 3. globals.h - Defines the global variables used by VPR. */ -#ifndef VPR_API_H -#define VPR_API_H - #include #include "physical_types.h" #include "vpr_types.h" @@ -136,6 +134,9 @@ void vpr_analysis(const Netlist<>& net_list, ///@brief Create the device (grid + rr graph) void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& Arch); +/// @brief Print architecture resources +void vpr_print_arch_resources(const t_vpr_setup& vpr_setup, const t_arch& Arch); + ///@brief Create the device grid void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch); @@ -221,5 +222,3 @@ char* vpr_get_output_file_name(enum e_output_files ename); ///@brief Prints user file or internal errors for VPR void vpr_print_error(const VprError& vpr_error); - -#endif diff --git a/vpr/src/base/vpr_constraints.h b/vpr/src/base/vpr_constraints.h index 797032f6b7e..4af0a9b9d51 100644 --- a/vpr/src/base/vpr_constraints.h +++ b/vpr/src/base/vpr_constraints.h @@ -1,5 +1,4 @@ -#ifndef VPR_CONSTRAINTS_H -#define VPR_CONSTRAINTS_H +#pragma once #include "user_place_constraints.h" #include "user_route_constraints.h" @@ -77,5 +76,3 @@ class VprConstraints { UserRouteConstraints route_constraints_; UserPlaceConstraints placement_constraints_; }; - -#endif /* VPR_CONSTRAINTS_H */ diff --git a/vpr/src/base/vpr_constraints_reader.h b/vpr/src/base/vpr_constraints_reader.h index 9740825836d..60187c1cc8e 100644 --- a/vpr/src/base/vpr_constraints_reader.h +++ b/vpr/src/base/vpr_constraints_reader.h @@ -1,10 +1,6 @@ +#pragma once /* Defines the function used to load a vpr constraints file written in XML format into vpr * The functions loads up the data structures related to placement and routing constraints * according to the data provided in the XML file*/ -#ifndef VPR_CONSTRAINTS_READER_H_ -#define VPR_CONSTRAINTS_READER_H_ - void load_vpr_constraints_file(const char* read_vpr_constraints_name); - -#endif /* VPR_CONSTRAINTS_READER_H_ */ diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index 08d6bee73cb..6216bba6e23 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -1,17 +1,4 @@ -#ifndef VPR_CONSTRAINTS_SERIALIZER_H_ -#define VPR_CONSTRAINTS_SERIALIZER_H_ - -#include -#include "region.h" -#include "vpr_constraints.h" -#include "partition.h" -#include "partition_region.h" -#include "vtr_log.h" -#include "globals.h" //for the g_vpr_ctx -#include "clock_modeling.h" - -#include "vpr_constraints_uxsdcxx_interface.h" - +#pragma once /** * @file * @brief The reading of vpr constraints is now done via uxsdcxx and the 'vpr_constraints.xsd' file. @@ -50,6 +37,17 @@ * For more detail on how the load and write interfaces work with uxsdcxx, refer to 'vpr/src/route/SCHEMA_GENERATOR.md' */ +#include +#include "region.h" +#include "vpr_constraints.h" +#include "partition.h" +#include "partition_region.h" +#include "vtr_log.h" +#include "globals.h" //for the g_vpr_ctx +#include "clock_modeling.h" + +#include "vpr_constraints_uxsdcxx_interface.h" + /* * Used for the PartitionReadContext, which is used when writing out a constraints XML file. * Groups together the information needed when printing a partition. @@ -526,5 +524,3 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase atoms_; }; - -#endif /* VPR_CONSTRAINTS_SERIALIZER_H_ */ diff --git a/vpr/src/base/vpr_constraints_writer.h b/vpr/src/base/vpr_constraints_writer.h index acff1198a7b..82841fe14a0 100644 --- a/vpr/src/base/vpr_constraints_writer.h +++ b/vpr/src/base/vpr_constraints_writer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @brief This file contains functions related to writing out a vpr constraints XML file. @@ -22,9 +23,6 @@ * four partitions - two partitions in the horizontal dimension, and two partitions in the vertical dimension. */ -#ifndef VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ -#define VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ - class VprConstraints; /** @@ -81,5 +79,3 @@ void setup_vpr_floorplan_constraints_one_loc(VprConstraints& constraints, void setup_vpr_floorplan_constraints_cutpoints(VprConstraints& constraints, int horizontal_cutpoints, int vertical_cutpoints); - -#endif /* VPR_SRC_BASE_VPR_CONSTRAINTS_WRITER_H_ */ diff --git a/vpr/src/base/vpr_context.cpp b/vpr/src/base/vpr_context.cpp index 2b7744a5107..78f678b97c3 100644 --- a/vpr/src/base/vpr_context.cpp +++ b/vpr/src/base/vpr_context.cpp @@ -13,6 +13,7 @@ #include "physical_types.h" #include "place_constraints.h" #include "place_macro.h" +#include "rr_graph_utils.h" #include "vpr_types.h" #include "vtr_memory.h" diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 47dd84843d4..83bcbdaab4f 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -1,5 +1,5 @@ -#ifndef VPR_CONTEXT_H -#define VPR_CONTEXT_H +#pragma once + #include #include #include @@ -277,7 +277,7 @@ struct DeviceContext : public Context { /******************************************************************* * Clock Network ********************************************************************/ - t_clock_arch* clock_arch; + std::shared_ptr> clock_arch; /// @brief Name of rrgraph file read (if any). /// Used to determine if the specified rr-graph file is already loaded, @@ -856,5 +856,3 @@ class VprContext : public Context { PackingMultithreadingContext packing_multithreading_; }; - -#endif diff --git a/vpr/src/base/vpr_exit_codes.h b/vpr/src/base/vpr_exit_codes.h index 6e92b527b41..197815832db 100644 --- a/vpr/src/base/vpr_exit_codes.h +++ b/vpr/src/base/vpr_exit_codes.h @@ -1,5 +1,4 @@ -#ifndef VPR_EXIT_CODES_H -#define VPR_EXIT_CODES_H +#pragma once /** * @file @@ -9,5 +8,3 @@ constexpr int SUCCESS_EXIT_CODE = 0; /// #include "tatum/error.hpp" std::string format_tatum_error(const tatum::Error& error); - -#endif diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index f96a9a8346b..b12b6001cd3 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @brief This is a core file that defines the major data types used by VPR @@ -21,8 +22,6 @@ * The t_pb hierarchy follows what is described by t_pb_graph_node */ -#pragma once - #include #include #include @@ -412,6 +411,13 @@ struct t_net_power { /** * @brief Stores a 3D bounding box in terms of the minimum and * maximum coordinates: x, y, layer + * + * @var xmin: The minimum x-coordinate of the bounding box + * @var xmax: The maximum x-coordinate of the bounding box + * @var ymin: The minimum y-coordinate of the bounding box + * @var ymax: The maximum y-coordinate of the bounding box + * @var layer_min: The minimum layer of the bounding box + * @var layer_max: The maximum layer of the bounding box */ struct t_bb { t_bb() = default; @@ -1104,6 +1110,8 @@ struct t_placer_opts { * @param log_verbosity * The verbosity level of log messages in the AP flow, with higher * values leading to more verbose messages. + * @param generate_mass_report + * Whether to generate a mass report during global placement or not. */ struct t_ap_opts { e_stage_action doAP; @@ -1123,6 +1131,8 @@ struct t_ap_opts { unsigned num_threads; int log_verbosity; + + bool generate_mass_report; }; /****************************************************************** diff --git a/vpr/src/draw/breakpoint.cpp b/vpr/src/draw/breakpoint.cpp index 9f0c9fe7ce6..93bcd3da101 100644 --- a/vpr/src/draw/breakpoint.cpp +++ b/vpr/src/draw/breakpoint.cpp @@ -1,9 +1,12 @@ + +#ifndef NO_GRAPHICS + #include "breakpoint.h" #include "draw_global.h" +#include "vtr_expr_eval.h" #include -#ifndef NO_GRAPHICS //if the user adds a "proceed move" breakpoint using the entry field in the UI, this function converts it to the equivalent expression and calls the expression evaluator. Returns true if a breakpoint is encountered //the way the proceed moves breakpoint works is that it proceeds the indicated number of moves from where the placer currently is i.e if at move 3 and proceed 4 ends up at move 7 bool check_for_moves_breakpoints(int moves_to_proceed) { diff --git a/vpr/src/draw/breakpoint.h b/vpr/src/draw/breakpoint.h index 612d85eb8a6..0b0091826d0 100644 --- a/vpr/src/draw/breakpoint.h +++ b/vpr/src/draw/breakpoint.h @@ -1,3 +1,4 @@ +#pragma once /** * @file breakpoint.h * @@ -16,14 +17,8 @@ * breakpoints have the same type, and the same value corresponding to the type. */ -#ifndef BREAKPOINT_H -#define BREAKPOINT_H - -#include #include - -#include "move_transactions.h" -#include "vtr_expr_eval.h" +#include "breakpoint_state_globals.h" typedef enum breakpoint_types { BT_MOVE_NUM, @@ -133,5 +128,3 @@ BreakpointState get_current_info_b(); //prints current BreakpointState information to terminal when breakpoint is reached void print_current_info(bool in_placer); - -#endif /* BREAKPOINT_H */ diff --git a/vpr/src/draw/breakpoint_state_globals.h b/vpr/src/draw/breakpoint_state_globals.h index d1bb22383d5..7ca1a0c433e 100644 --- a/vpr/src/draw/breakpoint_state_globals.h +++ b/vpr/src/draw/breakpoint_state_globals.h @@ -1,5 +1,4 @@ -#ifndef BREAKPOINT_STATE_GLOBALS -#define BREAKPOINT_STATE_GLOBALS +#pragma once #include #include @@ -29,5 +28,3 @@ class BreakpointStateGlobals { return &glob_breakpoint_state; } }; - -#endif diff --git a/vpr/src/draw/buttons.cpp b/vpr/src/draw/buttons.cpp index db64d45c5de..f8429b44299 100644 --- a/vpr/src/draw/buttons.cpp +++ b/vpr/src/draw/buttons.cpp @@ -10,16 +10,10 @@ * Last updated: Aug 2019 */ -#include "draw_global.h" #include "draw.h" -#include "draw_toggle_functions.h" #include "buttons.h" -#include "intra_logic_block.h" -#include "clustered_netlist.h" -#include "ezgl/point.hpp" #include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" //location of spin buttons, combo boxes, and labels on grid gint box_width = 1; diff --git a/vpr/src/draw/buttons.h b/vpr/src/draw/buttons.h index ce7d2910130..e1c706b39cb 100644 --- a/vpr/src/draw/buttons.h +++ b/vpr/src/draw/buttons.h @@ -1,16 +1,10 @@ -#ifndef BUTTONS_H -#define BUTTONS_H +#pragma once #ifndef NO_GRAPHICS -#include "draw_global.h" - -#include "ezgl/point.hpp" -#include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" +#include void delete_button(const char* button_name); GtkWidget* find_button(const char* button_name); -#endif /* NO_GRAPHICS */ -#endif /* BUTTONS_H */ +#endif /* NO_GRAPHICS */ diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 0f3ec5902fe..42d61233700 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -15,13 +15,21 @@ #include #include #include +#include "draw.h" +#include "timing_info.h" +#include "physical_types.h" + +#include "move_utils.h" + +#ifndef NO_GRAPHICS + #include #include #include +#include "draw_debug.h" #include "vtr_assert.h" #include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" #include "vtr_log.h" #include "vtr_color_map.h" #include "vtr_path.h" @@ -30,39 +38,27 @@ #include "globals.h" #include "draw_color.h" -#include "draw.h" #include "draw_basic.h" #include "draw_rr.h" -#include "draw_toggle_functions.h" #include "draw_searchbar.h" #include "draw_global.h" #include "intra_logic_block.h" -#include "tatum/report/TimingPathCollector.hpp" #include "hsl.h" -#include "route_export.h" #include "search_bar.h" #include "save_graphics.h" -#include "timing_info.h" -#include "physical_types.h" #include "manual_moves.h" #include "draw_noc.h" #include "draw_floorplanning.h" -#include "move_utils.h" #include "ui_setup.h" -#ifndef NO_GRAPHICS - //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW #if defined(X11) && !defined(__MINGW32__) #include #endif -#include "rr_graph.h" -#include "route_utilization.h" #include "place_macro.h" -#include "buttons.h" #include "draw_rr.h" /****************************** Define Macros *******************************/ @@ -493,6 +489,7 @@ void alloc_draw_structs(const t_arch* arch) { t_draw_state* draw_state = get_draw_state_vars(); auto& device_ctx = g_vpr_ctx.device(); auto& cluster_ctx = g_vpr_ctx.clustering(); + const AtomContext& atom_ctx = g_vpr_ctx.atom(); /* Allocate the structures needed to draw the placement and routing-> Set * * up the default colors for blocks and nets. */ @@ -502,7 +499,12 @@ void alloc_draw_structs(const t_arch* arch) { /* For sub-block drawings inside clbs */ draw_internal_alloc_blk(); - draw_state->net_color.resize(cluster_ctx.clb_nlist.nets().size()); + if (draw_state->is_flat) { + draw_state->net_color.resize(atom_ctx.netlist().nets().size()); + } else { + draw_state->net_color.resize(cluster_ctx.clb_nlist.nets().size()); + } + draw_state->block_color_.resize(cluster_ctx.clb_nlist.blocks().size()); draw_state->use_default_block_color_.resize( cluster_ctx.clb_nlist.blocks().size()); diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h index adfb6fd47be..6224bf49b9a 100644 --- a/vpr/src/draw/draw.h +++ b/vpr/src/draw/draw.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw.h * @@ -17,24 +18,21 @@ * Last updated: August 2022 */ -#ifndef DRAW_H -#define DRAW_H - -#include "rr_graph_fwd.h" -#include "timing_info.h" +#include "blk_loc_registry.h" #include "physical_types.h" +#include "rr_graph_type.h" +#include "timing_info.h" +#include "vpr_types.h" +#include #ifndef NO_GRAPHICS -#include "draw_global.h" - -#include "ezgl/point.hpp" +#include "draw_types.h" #include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" -#include "draw_color.h" -#include "search_bar.h" -#include "draw_debug.h" -#include "manual_moves.h" +#include "ezgl/point.hpp" +#include "physical_types.h" +#include "rr_graph_fwd.h" +#include "vtr_color_map.h" #include "vtr_ndoffsetmatrix.h" extern ezgl::application::settings settings; @@ -173,5 +171,3 @@ t_draw_layer_display get_element_visibility_and_transparency(int src_layer, int ClusterBlockId get_cluster_block_id_from_xy_loc(double x, double y); #endif /* NO_GRAPHICS */ - -#endif /* DRAW_H */ diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 82e0fa134ca..c6c6c6d7fd7 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -1,6 +1,8 @@ /* draw_basic.cpp contains all functions that draw in the main graphics area * that aren't RR nodes or muxes (they have their own file). * All functions in this file contain the prefix draw_. */ +#ifndef NO_GRAPHICS + #include #include #include @@ -27,18 +29,14 @@ #include "route_export.h" #include "tatum/report/TimingPathCollector.hpp" -#ifndef NO_GRAPHICS - //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW #if defined(X11) && !defined(__MINGW32__) #include #endif -#include "rr_graph.h" #include "route_utilization.h" #include "place_macro.h" -#include "buttons.h" /****************************** Define Macros *******************************/ #define DEFAULT_RR_NODE_COLOR ezgl::BLACK @@ -539,6 +537,7 @@ void drawroute(enum e_draw_net_type draw_net_type, ezgl::renderer* g) { /* Next free track in each channel segment if routing is GLOBAL */ auto& cluster_ctx = g_vpr_ctx.clustering(); + const AtomContext& atom_ctx = g_vpr_ctx.atom(); t_draw_state* draw_state = get_draw_state_vars(); @@ -548,14 +547,23 @@ void drawroute(enum e_draw_net_type draw_net_type, ezgl::renderer* g) { g->set_color(ezgl::BLACK, ezgl::BLACK.alpha * NET_ALPHA); /* Now draw each net, one by one. */ + if (draw_state->is_flat) { + for (AtomNetId net_id : atom_ctx.netlist().nets()) { + if (draw_net_type == HIGHLIGHTED + && draw_state->net_color[net_id] == ezgl::BLACK) + continue; + + draw_routed_net((ParentNetId&)net_id, g); + } /* End for (each net) */ + } else { + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { + if (draw_net_type == HIGHLIGHTED + && draw_state->net_color[net_id] == ezgl::BLACK) + continue; - for (auto net_id : cluster_ctx.clb_nlist.nets()) { - if (draw_net_type == HIGHLIGHTED - && draw_state->net_color[net_id] == ezgl::BLACK) - continue; - - draw_routed_net((ParentNetId&)net_id, g); - } /* End for (each net) */ + draw_routed_net((ParentNetId&)net_id, g); + } /* End for (each net) */ + } } void draw_routed_net(ParentNetId net_id, ezgl::renderer* g) { @@ -1094,6 +1102,8 @@ void draw_crit_path(ezgl::renderer* g) { void draw_crit_path_elements(const std::vector& paths, const std::map>& indexes, bool draw_crit_path_contour, ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); const ezgl::color contour_color{0, 0, 0, 40}; + const ezgl::line_dash contour_line_style{ezgl::line_dash::none}; + const int contour_line_width{1}; auto draw_flyline_timing_edge_helper_fn = [](ezgl::renderer* renderer, const ezgl::color& color, ezgl::line_dash line_style, int line_width, float delay, const tatum::NodeId& prev_node, const tatum::NodeId& node, bool skip_draw_delays = false) { @@ -1134,7 +1144,7 @@ void draw_crit_path_elements(const std::vector& paths, const if (draw_current_element) { draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::none, /*line_width*/ 4, delay, prev_node, node); } else if (draw_crit_path_contour) { - draw_flyline_timing_edge_helper_fn(g, contour_color, ezgl::line_dash::none, /*line_width*/ 1, delay, prev_node, node, /*skip_draw_delays*/ true); + draw_flyline_timing_edge_helper_fn(g, contour_color, contour_line_style, contour_line_width, delay, prev_node, node, /*skip_draw_delays*/ true); } } else { VTR_ASSERT(draw_state->show_crit_path != DRAW_NO_CRIT_PATH); @@ -1145,7 +1155,7 @@ void draw_crit_path_elements(const std::vector& paths, const draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/ 3, delay, prev_node, node); } else if (draw_crit_path_contour) { - draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/ 3, delay, prev_node, node, /*skip_draw_delays*/ true); + draw_flyline_timing_edge_helper_fn(g, contour_color, contour_line_style, contour_line_width, delay, prev_node, node, /*skip_draw_delays*/ true); } } } diff --git a/vpr/src/draw/draw_basic.h b/vpr/src/draw/draw_basic.h index 65d42836948..3af8165b9a8 100644 --- a/vpr/src/draw/draw_basic.h +++ b/vpr/src/draw/draw_basic.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw_basic.h * @@ -6,38 +7,21 @@ * All functions in this file contain the prefix draw_. */ -#ifndef DRAW_BASIC_H -#define DRAW_BASIC_H +#ifndef NO_GRAPHICS #include #include #include #include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" -#include "vtr_log.h" -#include "vtr_color_map.h" -#include "vtr_path.h" - -#include "vpr_utils.h" -#include "vpr_error.h" - -#include "globals.h" -#include "move_utils.h" +#include "draw_types.h" +#include "netlist_fwd.h" +#include "rr_graph_fwd.h" +#include "tatum/TimingGraphFwd.hpp" -#ifndef NO_GRAPHICS - -#include "draw_global.h" +#include "vtr_color_map.h" #include "ezgl/point.hpp" -#include "ezgl/application.hpp" #include "ezgl/graphics.hpp" /* Draws the blocks placed on the proper clbs. Occupied blocks are darker colours * @@ -158,4 +142,3 @@ void draw_reset_blk_colors(); void draw_reset_blk_color(ClusterBlockId blk_id); #endif /* NO_GRAPHICS */ -#endif /* DRAW_BASIC_H */ diff --git a/vpr/src/draw/draw_color.h b/vpr/src/draw/draw_color.h index 4dcc5e5dbe8..a73bacfc5e1 100644 --- a/vpr/src/draw/draw_color.h +++ b/vpr/src/draw/draw_color.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw_color.h * @@ -5,14 +6,11 @@ * as well as a global vector of colors shuffled to prevent similar * colors from being close together */ -#ifndef DRAW_COLOR_H -#define DRAW_COLOR_H #ifndef NO_GRAPHICS -#include "ezgl/point.hpp" -#include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" +#include +#include "ezgl/color.hpp" static constexpr ezgl::color blk_BISQUE(0xFF, 0xE4, 0xC4); static constexpr ezgl::color blk_LIGHTGREY(0xD3, 0xD3, 0xD3); @@ -326,5 +324,3 @@ const std::vector block_colors{ }; #endif /* NO_GRAPHICS */ - -#endif /* DRAW_COLOR_H */ diff --git a/vpr/src/draw/draw_debug.cpp b/vpr/src/draw/draw_debug.cpp index 89566863c5e..be7f9acdc46 100644 --- a/vpr/src/draw/draw_debug.cpp +++ b/vpr/src/draw/draw_debug.cpp @@ -1,7 +1,9 @@ -#include "draw_debug.h" - #ifndef NO_GRAPHICS +#include "draw_debug.h" +#include "draw_global.h" +#include "vtr_expr_eval.h" + //keeps track of open windows to avoid reopenning windows that are alerady open struct open_windows { bool debug_window = false; diff --git a/vpr/src/draw/draw_debug.h b/vpr/src/draw/draw_debug.h index f79d7740d7b..f5e0a547e05 100644 --- a/vpr/src/draw/draw_debug.h +++ b/vpr/src/draw/draw_debug.h @@ -1,27 +1,20 @@ +#pragma once /** * @file draw_debug.h * * This file contains all functions regarding the graphics related to the setting of place and route breakpoints. * Manages creation of new Gtk Windows with debug options on use of the "Debug" button. */ -#ifndef DRAW_DEBUG_H -#define DRAW_DEBUG_H #ifndef NO_GRAPHICS -#include "breakpoint.h" -#include "draw_global.h" -#include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" - -#include #include -#include #include -#include -#include -#include -#include +#include +#include +#include +#include +#include "breakpoint_state_globals.h" /** debugger functions **/ void draw_debug_window(); @@ -44,5 +37,3 @@ bool valid_expression(std::string exp); void breakpoint_info_window(std::string bpDescription, BreakpointState draw_breakpoint_state, bool in_placer); #endif /*NO_GRAPHICS*/ - -#endif /*DRAW_DEBUG_H*/ diff --git a/vpr/src/draw/draw_floorplanning.cpp b/vpr/src/draw/draw_floorplanning.cpp index e22c6446f7a..7b184baf965 100644 --- a/vpr/src/draw/draw_floorplanning.cpp +++ b/vpr/src/draw/draw_floorplanning.cpp @@ -1,20 +1,13 @@ -#include +#ifndef NO_GRAPHICS -#include "vpr_error.h" +#include #include "globals.h" #include "draw_floorplanning.h" #include "user_place_constraints.h" -#include "draw_color.h" #include "draw.h" -#include "read_xml_arch_file.h" #include "draw_global.h" -#include "intra_logic_block.h" -#include "route_export.h" -#include "tatum/report/TimingPathCollector.hpp" - -#ifndef NO_GRAPHICS //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW diff --git a/vpr/src/draw/draw_floorplanning.h b/vpr/src/draw/draw_floorplanning.h index feae6ec127c..601f05497ae 100644 --- a/vpr/src/draw/draw_floorplanning.h +++ b/vpr/src/draw/draw_floorplanning.h @@ -1,15 +1,9 @@ +#pragma once /** This file contains all functions regarding the graphics related to drawing floorplanning constraints. **/ -#ifndef DRAW_FLOORPLANNING_H -#define DRAW_FLOORPLANNING_H - -#include "globals.h" #ifndef NO_GRAPHICS -#include "draw_global.h" - -#include "ezgl/point.hpp" -#include "ezgl/application.hpp" +#include #include "ezgl/graphics.hpp" ///@brief Iterates through all partitions described in the constraints file and highlights their respective partitions @@ -25,5 +19,3 @@ GtkWidget* setup_floorplanning_legend(GtkWidget* content_tree); void highlight_selected_partition(GtkWidget* widget); #endif /*NO_GRAPHICS*/ - -#endif /*DRAW_FLOORPLANNING_H*/ diff --git a/vpr/src/draw/draw_global.h b/vpr/src/draw/draw_global.h index e53b628cc73..5179613b83c 100644 --- a/vpr/src/draw/draw_global.h +++ b/vpr/src/draw/draw_global.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw_global.h * This file contains declaration of accessor functions that can be used to @@ -10,9 +11,6 @@ * Date: August 21, 2013 */ -#ifndef DRAW_GLOBAL_H -#define DRAW_GLOBAL_H - #ifndef NO_GRAPHICS #include "draw_types.h" @@ -28,5 +26,3 @@ t_draw_coords* get_draw_coords_vars(); t_draw_state* get_draw_state_vars(); #endif // NO_GRAPHICS - -#endif diff --git a/vpr/src/draw/draw_mux.cpp b/vpr/src/draw/draw_mux.cpp index 7d03e2f468b..806391f42bf 100644 --- a/vpr/src/draw/draw_mux.cpp +++ b/vpr/src/draw/draw_mux.cpp @@ -1,16 +1,12 @@ /*draw_mux.cpp contains all functions that draw muxes.*/ +#ifndef NO_GRAPHICS + #include -#include #include "vtr_assert.h" -#include "vtr_color_map.h" -#include "draw_color.h" #include "draw_mux.h" -#include "read_xml_arch_file.h" - -#ifndef NO_GRAPHICS //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW diff --git a/vpr/src/draw/draw_mux.h b/vpr/src/draw/draw_mux.h index cb62427f339..9775db37db4 100644 --- a/vpr/src/draw/draw_mux.h +++ b/vpr/src/draw/draw_mux.h @@ -1,41 +1,20 @@ +#pragma once /** * @file draw_mux.h * * This file contains all functions related to drawing muxes */ -#ifndef DRAW_MUX_H -#define DRAW_MUX_H + +#ifndef NO_GRAPHICS #include #include #include #include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" -#include "vtr_log.h" -#include "vtr_color_map.h" -#include "vtr_path.h" - -#include "vpr_utils.h" -#include "vpr_error.h" - -#include "globals.h" - -#include "move_utils.h" - -#ifndef NO_GRAPHICS - -#include "draw_global.h" #include "ezgl/point.hpp" -#include "ezgl/application.hpp" #include "ezgl/graphics.hpp" +#include "physical_types.h" /** * @brief Draws a mux with width = height * 0.4 and scale (slope of the muxes sides) = 0.6, labelled with its size. @@ -54,4 +33,3 @@ ezgl::rectangle draw_mux(ezgl::point2d origin, e_side orientation, float height, ezgl::rectangle draw_mux(ezgl::point2d origin, e_side orientation, float height, float width, float height_scale, ezgl::renderer* g); #endif /* NO_GRAPHICS */ -#endif /* DRAW_MUX_H */ diff --git a/vpr/src/draw/draw_noc.cpp b/vpr/src/draw/draw_noc.cpp index a988d7b4d65..1ff55a1f43d 100644 --- a/vpr/src/draw/draw_noc.cpp +++ b/vpr/src/draw/draw_noc.cpp @@ -1,7 +1,9 @@ #ifndef NO_GRAPHICS +#include "draw.h" #include "draw_basic.h" +#include "draw_global.h" #include "draw_noc.h" #include "globals.h" #include "noc_storage.h" diff --git a/vpr/src/draw/draw_noc.h b/vpr/src/draw/draw_noc.h index e24ae6b1db2..dd1141b40a2 100644 --- a/vpr/src/draw/draw_noc.h +++ b/vpr/src/draw/draw_noc.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw_noc.h * @brief This is the draw_noc header file. This file provides utilities @@ -21,15 +22,14 @@ * Author: Srivatsan Srinivasan */ -#ifndef DRAW_NOC_H -#define DRAW_NOC_H - -#include -#include - #ifndef NO_GRAPHICS -#include "draw.h" +#include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "noc_data_types.h" +#include "noc_router.h" +#include "physical_types.h" +#include "vtr_vector.h" // defines the area of the marker that represents connection points between links // area is equivalent to the %x of the area of the router @@ -242,5 +242,3 @@ NocLinkType determine_noc_link_type(ezgl::point2d link_start_point, ezgl::point2 void shift_noc_link(noc_link_draw_coords& link_coords, NocLinkShift link_shift_direction, NocLinkType link_type, double noc_connection_marker_quarter_width, double noc_connection_marker_quarter_height); #endif - -#endif diff --git a/vpr/src/draw/draw_rr.cpp b/vpr/src/draw/draw_rr.cpp index d9c6c71c5f3..156147c17e0 100644 --- a/vpr/src/draw/draw_rr.cpp +++ b/vpr/src/draw/draw_rr.cpp @@ -1,12 +1,12 @@ /*draw_rr.cpp contains all functions that relate to drawing routing resources.*/ +#ifndef NO_GRAPHICS + #include #include #include -#include #include "rr_graph_fwd.h" #include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" #include "vtr_color_map.h" #include "vpr_utils.h" @@ -21,10 +21,8 @@ #include "draw_triangle.h" #include "draw_searchbar.h" #include "draw_mux.h" -#include "read_xml_arch_file.h" #include "draw_global.h" - -#ifndef NO_GRAPHICS +#include "search_bar.h" //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW diff --git a/vpr/src/draw/draw_rr.h b/vpr/src/draw/draw_rr.h index 9c19f6bc951..dd7a305ffcd 100644 --- a/vpr/src/draw/draw_rr.h +++ b/vpr/src/draw/draw_rr.h @@ -1,51 +1,21 @@ +#pragma once /** * @file draw_rr.h * * draw_rr.cpp contains all functions that relate to drawing routing resources. */ -#ifndef DRAW_RR_H -#define DRAW_RR_H +#ifndef NO_GRAPHICS #include #include #include #include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" -#include "vtr_log.h" -#include "vtr_color_map.h" -#include "vtr_path.h" - -#include "vpr_utils.h" -#include "vpr_error.h" - -#include "globals.h" -#include "move_utils.h" +#include "rr_graph_fwd.h" +#include "rr_node.h" -#ifndef NO_GRAPHICS - -#include "draw_global.h" - -#include "ezgl/point.hpp" -#include "ezgl/application.hpp" #include "ezgl/graphics.hpp" -#include "draw_color.h" -#include "search_bar.h" -#include "draw_debug.h" -#include "manual_moves.h" - -#include "rr_graph.h" -#include "route_utilization.h" -#include "place_macro.h" -#include "buttons.h" /* Draws the routing resources that exist in the FPGA, if the user wants * * them drawn. */ @@ -104,4 +74,3 @@ void draw_get_rr_pin_coords(const t_rr_node& node, float* xcen, float* ycen, con */ int get_rr_node_transparency(RRNodeId rr_node); #endif /* NO_GRAPHICS */ -#endif /* DRAW_RR_H */ diff --git a/vpr/src/draw/draw_rr_edges.cpp b/vpr/src/draw/draw_rr_edges.cpp index 2aff5c3d35c..85deffe7652 100644 --- a/vpr/src/draw/draw_rr_edges.cpp +++ b/vpr/src/draw/draw_rr_edges.cpp @@ -1,4 +1,6 @@ /*draw_rr_edges.cpp contains all functions that draw lines between RR nodes.*/ +#ifndef NO_GRAPHICS + #include #include "physical_types_util.h" @@ -15,8 +17,6 @@ #include "draw_global.h" #include "draw_basic.h" -#ifndef NO_GRAPHICS - //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW #if defined(X11) && !defined(__MINGW32__) diff --git a/vpr/src/draw/draw_rr_edges.h b/vpr/src/draw/draw_rr_edges.h index 8ea7a383dcb..3b51bd0ab65 100644 --- a/vpr/src/draw/draw_rr_edges.h +++ b/vpr/src/draw/draw_rr_edges.h @@ -1,51 +1,21 @@ +#pragma once /** * @file draw_rr_edges.h * * draw_rr_edges.cpp contains all functions that draw lines between RR nodes. */ -#ifndef DRAW_X_TO_Y_H -#define DRAW_X_TO_Y_H +#ifndef NO_GRAPHICS #include #include #include #include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" -#include "vtr_log.h" -#include "vtr_color_map.h" -#include "vtr_path.h" - -#include "vpr_utils.h" -#include "vpr_error.h" - -#include "globals.h" -#include "move_utils.h" +#include "draw_types.h" +#include "rr_graph_fwd.h" -#ifndef NO_GRAPHICS - -#include "draw_global.h" - -#include "ezgl/point.hpp" -#include "ezgl/application.hpp" #include "ezgl/graphics.hpp" -#include "draw_color.h" -#include "search_bar.h" -#include "draw_debug.h" -#include "manual_moves.h" - -#include "rr_graph.h" -#include "route_utilization.h" -#include "place_macro.h" -#include "buttons.h" void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g); void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g); @@ -56,4 +26,3 @@ void draw_source_to_pin(RRNodeId source_node, RRNodeId opin_node, ezgl::renderer void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer* g); #endif /* NO_GRAPHICS */ -#endif /* DRAW_X_TO_Y_H */ diff --git a/vpr/src/draw/draw_searchbar.cpp b/vpr/src/draw/draw_searchbar.cpp index 28f174a50dd..e80f450af3a 100644 --- a/vpr/src/draw/draw_searchbar.cpp +++ b/vpr/src/draw/draw_searchbar.cpp @@ -1,4 +1,6 @@ /*draw_searchbar.cpp contains all functions related to searchbar actions.*/ +#ifndef NO_GRAPHICS + #include #include "netlist_fwd.h" @@ -14,8 +16,6 @@ #include "draw_global.h" #include "intra_logic_block.h" -#ifndef NO_GRAPHICS - //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW #if defined(X11) && !defined(__MINGW32__) @@ -231,6 +231,7 @@ void deselect_all() { t_draw_state* draw_state = get_draw_state_vars(); const auto& cluster_ctx = g_vpr_ctx.clustering(); + const AtomContext& atom_ctx = g_vpr_ctx.atom(); const auto& device_ctx = g_vpr_ctx.device(); /* Create some colour highlighting */ @@ -239,8 +240,13 @@ void deselect_all() { draw_reset_blk_color(blk_id); } - for (auto net_id : cluster_ctx.clb_nlist.nets()) - draw_state->net_color[net_id] = ezgl::BLACK; + if (draw_state->is_flat) { + for (auto net_id : atom_ctx.netlist().nets()) + draw_state->net_color[net_id] = ezgl::BLACK; + } else { + for (auto net_id : cluster_ctx.clb_nlist.nets()) + draw_state->net_color[net_id] = ezgl::BLACK; + } for (RRNodeId inode : device_ctx.rr_graph.nodes()) { draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR; diff --git a/vpr/src/draw/draw_searchbar.h b/vpr/src/draw/draw_searchbar.h index 25a135be153..7d195dde988 100644 --- a/vpr/src/draw/draw_searchbar.h +++ b/vpr/src/draw/draw_searchbar.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw_searchbar.h * @@ -5,48 +6,17 @@ * and manages the selection/highlighting of currently selected options. */ -#ifndef DRAW_SEARCHBAR_H -#define DRAW_SEARCHBAR_H +#ifndef NO_GRAPHICS #include #include #include #include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" -#include "vtr_log.h" -#include "vtr_color_map.h" -#include "vtr_path.h" - -#include "vpr_utils.h" -#include "vpr_error.h" - -#include "globals.h" - -#include "move_utils.h" - -#ifndef NO_GRAPHICS - -#include "draw_global.h" - -#include "ezgl/point.hpp" -#include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" -#include "draw_color.h" -#include "search_bar.h" -#include "draw_debug.h" -#include "manual_moves.h" -#include "rr_graph.h" -#include "route_utilization.h" -#include "place_macro.h" -#include "buttons.h" +#include "clustered_netlist_fwd.h" +#include "ezgl/rectangle.hpp" +#include "physical_types.h" +#include "rr_graph_fwd.h" /* This function computes and returns the boundary coordinates of a channel * wire segment. This can be used for drawing a wire or determining if a @@ -75,4 +45,3 @@ std::set draw_expand_non_configurable_rr_nodes(RRNodeId hit_node); void deselect_all(); #endif /* NO_GRAPHICS */ -#endif /* DRAW_SEARCHBAR_H */ diff --git a/vpr/src/draw/draw_toggle_functions.cpp b/vpr/src/draw/draw_toggle_functions.cpp index ddd518cf4a5..6858c54fea2 100644 --- a/vpr/src/draw/draw_toggle_functions.cpp +++ b/vpr/src/draw/draw_toggle_functions.cpp @@ -1,21 +1,17 @@ +#ifndef NO_GRAPHICS + #include -#include -#include -#include "vpr_utils.h" #include "vpr_error.h" #include "globals.h" -#include "draw_color.h" #include "draw.h" #include "draw_toggle_functions.h" #include "draw_global.h" #include "draw_basic.h" -#ifndef NO_GRAPHICS - //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW #if defined(X11) && !defined(__MINGW32__) diff --git a/vpr/src/draw/draw_toggle_functions.h b/vpr/src/draw/draw_toggle_functions.h index e6c9114900e..04afac1399c 100644 --- a/vpr/src/draw/draw_toggle_functions.h +++ b/vpr/src/draw/draw_toggle_functions.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw_toggle_functions.h * @@ -10,48 +11,14 @@ * Author: Sebastian Lievano */ -#ifndef DRAW_TOGGLE_FUNCTIONS_H -#define DRAW_TOGGLE_FUNCTIONS_H +#ifndef NO_GRAPHICS #include #include #include #include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" -#include "vtr_log.h" -#include "vtr_color_map.h" -#include "vtr_path.h" - -#include "vpr_utils.h" -#include "vpr_error.h" - -#include "globals.h" - -#include "move_utils.h" -#ifndef NO_GRAPHICS - -#include "draw_global.h" - -#include "ezgl/point.hpp" #include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" -#include "draw_color.h" -#include "search_bar.h" -#include "draw_debug.h" -#include "manual_moves.h" - -#include "rr_graph.h" -#include "route_utilization.h" -#include "place_macro.h" -#include "buttons.h" /* Callback function for main.ui created toggle_nets button in ui_setup.cpp. Controls whether or not nets are visualized. * Toggles value of draw_state->show_nets.*/ @@ -160,4 +127,3 @@ void cross_layer_checkbox_cbk(GtkWidget* widget, gint /*response_id*/, gpointer */ void cross_layer_transparency_cbk(GtkWidget* widget, gint /*response_id*/, gpointer /*data*/); #endif /* NO_GRAPHICS */ -#endif /* DRAW_TOGGLE_FUNCTIONS_H */ diff --git a/vpr/src/draw/draw_triangle.cpp b/vpr/src/draw/draw_triangle.cpp index 83ccd1af7f1..a102ca289de 100644 --- a/vpr/src/draw/draw_triangle.cpp +++ b/vpr/src/draw/draw_triangle.cpp @@ -1,13 +1,12 @@ +#ifndef NO_GRAPHICS + #include #include "vtr_assert.h" -#include "vtr_color_map.h" -#include "draw_color.h" #include "draw_triangle.h" -#include "draw_global.h" -#ifndef NO_GRAPHICS +#include "ezgl/graphics.hpp" //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW diff --git a/vpr/src/draw/draw_triangle.h b/vpr/src/draw/draw_triangle.h index 9c0116f0c5a..cadb9c1d6a4 100644 --- a/vpr/src/draw/draw_triangle.h +++ b/vpr/src/draw/draw_triangle.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw_triangle.h * @@ -5,48 +6,17 @@ * direction of signals, flylines */ -#ifndef DRAW_TRIANGLE_H -#define DRAW_TRIANGLE_H +#ifndef NO_GRAPHICS #include #include #include #include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" -#include "vtr_log.h" -#include "vtr_color_map.h" -#include "vtr_path.h" - -#include "vpr_utils.h" -#include "vpr_error.h" - -#include "globals.h" - -#include "move_utils.h" - -#ifndef NO_GRAPHICS #include "draw_global.h" #include "ezgl/point.hpp" -#include "ezgl/application.hpp" #include "ezgl/graphics.hpp" -#include "draw_color.h" -#include "search_bar.h" -#include "draw_debug.h" -#include "manual_moves.h" - -#include "rr_graph.h" -#include "route_utilization.h" -#include "place_macro.h" -#include "buttons.h" /** * Retrieves the current zoom level based on the visible world and screen dimensions. @@ -83,4 +53,3 @@ void draw_triangle_along_line(ezgl::renderer* g, ezgl::point2d loc, ezgl::point2 void draw_triangle_along_line(ezgl::renderer* g, float xend, float yend, float x1, float x2, float y1, float y2, float arrow_size = DEFAULT_ARROW_SIZE); #endif /* NO_GRAPHICS */ -#endif /* DRAW_TRIANGLE_H */ diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index 8d96ceaf732..92cdae46017 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -1,3 +1,4 @@ +#pragma once /** * @file draw_types.h * @@ -15,14 +16,10 @@ * Author: Long Yu (Mike) Wang, Sebastian Lievano */ -#ifndef DRAW_TYPES_H -#define DRAW_TYPES_H - #ifndef NO_GRAPHICS #include #include -#include "clustered_netlist.h" #include "timing_info_fwd.h" #include "vtr_util.h" #include "vpr_types.h" @@ -31,7 +28,6 @@ #include "breakpoint.h" #include "manual_moves.h" -#include "ezgl/point.hpp" #include "ezgl/rectangle.hpp" #include "ezgl/color.hpp" @@ -238,7 +234,7 @@ struct t_draw_state { char default_message[vtr::bufsize]; ///@brief color in which each net should be drawn. [0..cluster_ctx.clb_nlist.nets().size()-1] - vtr::vector net_color; + vtr::vector net_color; /** * @brief stores the state information of each routing resource. @@ -457,5 +453,3 @@ struct t_draw_coords { }; #endif // NO_GRAPHICS - -#endif diff --git a/vpr/src/draw/gtkcomboboxhelper.h b/vpr/src/draw/gtkcomboboxhelper.h index f7b2c2aa637..d950ca91766 100644 --- a/vpr/src/draw/gtkcomboboxhelper.h +++ b/vpr/src/draw/gtkcomboboxhelper.h @@ -1,5 +1,4 @@ -#ifndef GTKCOMBOBOXHELPER_H -#define GTKCOMBOBOXHELPER_H +#pragma once #ifndef NO_GRAPHICS @@ -18,5 +17,3 @@ gint get_item_index_by_text(gpointer combo_box, const gchar* target_item); #endif // NO_GRAPHICS - -#endif // GTKCOMBOBOXHELPER_H diff --git a/vpr/src/draw/hsl.h b/vpr/src/draw/hsl.h index 589266bc6e4..fe7abeefb0c 100644 --- a/vpr/src/draw/hsl.h +++ b/vpr/src/draw/hsl.h @@ -1,12 +1,10 @@ +#pragma once /** * @file hsl.h * * This file manages conversions between color (red, green, and blue) and hsl (hue, saturation, and luminesence) */ -#ifndef HSL_H -#define HSL_H - #ifndef NO_GRAPHICS #include "ezgl/color.hpp" @@ -22,5 +20,3 @@ hsl color2hsl(ezgl::color in); ezgl::color hsl2color(hsl in); #endif /* NO_GRAPHICS */ - -#endif diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index 48993eaf8a7..d30bded969b 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -25,7 +25,6 @@ #include #include "vtr_assert.h" -#include "vtr_memory.h" #include "intra_logic_block.h" #include "globals.h" @@ -34,7 +33,6 @@ #include "draw_global.h" #include "draw.h" #include "draw_triangle.h" -#include "draw_color.h" /************************* Subroutines local to this file. *******************************/ diff --git a/vpr/src/draw/intra_logic_block.h b/vpr/src/draw/intra_logic_block.h index 7ad0bf9bba5..35b6f0ee3e5 100644 --- a/vpr/src/draw/intra_logic_block.h +++ b/vpr/src/draw/intra_logic_block.h @@ -1,3 +1,4 @@ +#pragma once /** * @file intra_logic_block.h * @@ -15,22 +16,14 @@ * Date: May,June 2014 */ -#ifndef INTRA_LOGIC_BLOCK_H -#define INTRA_LOGIC_BLOCK_H - #ifndef NO_GRAPHICS #include "vpr_types.h" -#include "draw_types.h" #include "atom_netlist_fwd.h" #include #include "ezgl/point.hpp" - -#ifndef NO_GRAPHICS #include "ezgl/graphics.hpp" -#include "ezgl/application.hpp" -#endif /* NO_GRAPHICS */ struct t_selected_sub_block_info { struct clb_pin_tuple { @@ -112,9 +105,7 @@ void draw_internal_init_blk(); /* Top-level drawing routine for internal sub-blocks. The function traverses through all * grid tiles and calls helper function to draw inside each block. */ -#ifndef NO_GRAPHICS void draw_internal_draw_subblk(ezgl::renderer* g); -#endif /* NO_GRAPHICS */ /* Determines which part of a block to highlight, and stores it, * so that the other subblock drawing functions will obey it. @@ -141,5 +132,3 @@ void find_pin_index_at_model_scope(const AtomPinId the_pin, const AtomBlockId lb t_pb* find_atom_block_in_pb(const std::string& name, t_pb* pb); #endif /* NO_GRAPHICS */ - -#endif /* INTRA_LOGIC_BLOCK_H */ diff --git a/vpr/src/draw/manual_moves.cpp b/vpr/src/draw/manual_moves.cpp index 972b2a36bd7..2377feca006 100644 --- a/vpr/src/draw/manual_moves.cpp +++ b/vpr/src/draw/manual_moves.cpp @@ -12,15 +12,17 @@ * if the manual move toggle button in the UI is active or not, and calls the function needed. */ +#ifndef NO_GRAPHICS + #include "manual_moves.h" +#include "draw_debug.h" #include "globals.h" #include "draw.h" +#include "draw_global.h" #include "draw_searchbar.h" #include "buttons.h" #include "physical_types_util.h" -#ifndef NO_GRAPHICS - void draw_manual_moves_window(const std::string& block_id) { t_draw_state* draw_state = get_draw_state_vars(); diff --git a/vpr/src/draw/manual_moves.h b/vpr/src/draw/manual_moves.h index e5c152275d4..43ab9f3ad6a 100644 --- a/vpr/src/draw/manual_moves.h +++ b/vpr/src/draw/manual_moves.h @@ -1,3 +1,4 @@ +#pragma once /** * @file manual_moves.h * @@ -7,14 +8,9 @@ * Author: Paula Perdomo */ -#ifndef MANUAL_MOVES_H -#define MANUAL_MOVES_H - /** This file contains all functions for manual moves **/ #ifndef NO_GRAPHICS -#include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" #include "manual_move_generator.h" #include "move_utils.h" @@ -22,8 +18,7 @@ #include #include #include -#include -#include +#include /** * @brief ManualMovesInfo struct @@ -70,7 +65,6 @@ struct ManualMovesInfo { * user_highlighted_block: Stores whether user highlighted block in UI instead of entering the block ID manually. * manual_move_window: GtkWindow for the manual move. In this window the user inputs the block ID and to position of the block to move. */ - struct ManualMovesState { ManualMovesInfo manual_move_info; bool manual_move_window_is_open = false; @@ -164,5 +158,3 @@ e_create_move manual_move_display_and_propose(ManualMoveGenerator& manual_move_g const PlacerCriticalities* criticalities); #endif /*NO_GRAPHICS*/ - -#endif /* MANUAL_MOVES_H */ diff --git a/vpr/src/draw/save_graphics.h b/vpr/src/draw/save_graphics.h index f9a6ec2fbb1..488fafd560f 100644 --- a/vpr/src/draw/save_graphics.h +++ b/vpr/src/draw/save_graphics.h @@ -1,24 +1,17 @@ +#pragma once /** * @file save_graphics.h * * Manages saving of graphics in different file formats */ -#ifndef SAVE_GRAPHICS_H -#define SAVE_GRAPHICS_H - #ifndef NO_GRAPHICS -#include "draw_global.h" - -#include "ezgl/point.hpp" #include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" +#include void save_graphics(std::string extension, std::string file_name); void save_graphics_dialog_box(GtkWidget* /*widget*/, ezgl::application* /*app*/); void save_graphics_from_button(GtkWidget* /*widget*/, gint response_id, gpointer data); #endif /* NO_GRAPHICS */ - -#endif /* SAVE_GRAPHICS_H */ diff --git a/vpr/src/draw/search_bar.cpp b/vpr/src/draw/search_bar.cpp index 46261da44d5..17de84c587e 100644 --- a/vpr/src/draw/search_bar.cpp +++ b/vpr/src/draw/search_bar.cpp @@ -13,34 +13,27 @@ * */ -#include "physical_types.h" #ifndef NO_GRAPHICS #include #include #include "vtr_assert.h" -#include "vtr_ndoffsetmatrix.h" -#include "vtr_memory.h" #include "vtr_log.h" -#include "vtr_color_map.h" #include "vpr_utils.h" -#include "vpr_error.h" +#include "route_utils.h" #include "globals.h" -#include "draw_color.h" #include "draw.h" -#include "draw_basic.h" #include "draw_rr.h" #include "draw_searchbar.h" -#include "read_xml_arch_file.h" #include "draw_global.h" #include "intra_logic_block.h" #include "atom_netlist.h" -#include "tatum/report/TimingPathCollector.hpp" -#include "hsl.h" -#include "route_export.h" #include "search_bar.h" +#include "old_traceback.h" +#include "physical_types.h" +#include "place_macro.h" //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW @@ -48,10 +41,6 @@ #include #endif -#include "rr_graph.h" -#include "route_utilization.h" -#include "place_macro.h" - extern std::string rr_highlight_message; void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { @@ -72,6 +61,8 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { // reset deselect_all(); + t_draw_state* draw_state = get_draw_state_vars(); + if (search_type == "RR Node ID") { int rr_node_id = -1; ss >> rr_node_id; @@ -135,15 +126,33 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { else if (search_type == "Net ID") { int net_id = -1; ss >> net_id; - - // valid net id check - if (!cluster_ctx.clb_nlist.valid_net_id(ClusterNetId(net_id))) { - warning_dialog_box("Invalid Net ID"); - app->refresh_drawing(); - return; + if (draw_state->is_flat) { + AtomNetId atom_net_id = AtomNetId(net_id); + if (!atom_ctx.netlist().valid_net_id(atom_net_id)) { + warning_dialog_box("Invalid Net ID"); + app->refresh_drawing(); + return; + } + if (!is_net_routed(atom_net_id)) { + warning_dialog_box("Net is unrouted"); + app->refresh_drawing(); + return; + } + if (is_net_fully_absorbed(atom_net_id)) { + warning_dialog_box("Net is fully absorbed"); + app->refresh_drawing(); + return; + } + highlight_nets((ClusterNetId)net_id); + } else { + // valid net id check + if (!cluster_ctx.clb_nlist.valid_net_id(ClusterNetId(net_id))) { + warning_dialog_box("Invalid Net ID"); + app->refresh_drawing(); + return; + } + highlight_nets((ClusterNetId)net_id); } - - highlight_nets((ClusterNetId)net_id); } else if (search_type == "Net Name") { @@ -151,16 +160,39 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { //So we only need to search this one std::string net_name; ss >> net_name; - AtomNetId atom_net_id = atom_ctx.netlist().find_net(net_name); - - if (atom_net_id == AtomNetId::INVALID()) { - warning_dialog_box("Invalid Net Name"); - return; //name not exist - } - const auto clb_nets = atom_ctx.lookup().clb_nets(atom_net_id); - for (auto clb_net_id : clb_nets.value()) { - highlight_nets(clb_net_id); + if (draw_state->is_flat) { + AtomNetId atom_net_id = atom_ctx.netlist().find_net(net_name); + if (atom_net_id == AtomNetId::INVALID()) { + warning_dialog_box("Invalid Net Name"); + app->refresh_drawing(); + return; + } + if (!is_net_routed(atom_net_id)) { + warning_dialog_box("Net is unrouted"); + app->refresh_drawing(); + return; + } + if (is_net_fully_absorbed(atom_net_id)) { + warning_dialog_box("Net is fully absorbed"); + app->refresh_drawing(); + return; + } + highlight_nets(convert_to_cluster_net_id(atom_net_id)); + } else { + AtomNetId atom_net_id = atom_ctx.netlist().find_net(net_name); + + if (atom_net_id == AtomNetId::INVALID()) { + warning_dialog_box("Invalid Net Name"); + app->refresh_drawing(); + return; + } + auto clb_net_ids_opt = atom_ctx.lookup().clb_nets(atom_net_id); + if (clb_net_ids_opt.has_value()) { + for (auto clb_net_id : clb_net_ids_opt.value()) { + highlight_nets(clb_net_id); + } + } } } diff --git a/vpr/src/draw/search_bar.h b/vpr/src/draw/search_bar.h index 5aafd49435d..bf155298e1a 100644 --- a/vpr/src/draw/search_bar.h +++ b/vpr/src/draw/search_bar.h @@ -1,3 +1,4 @@ +#pragma once /** * @file search_bar.h * @@ -7,17 +8,13 @@ * Author: Sebastian Lievano */ -#ifndef SEARCH_BAR_H -#define SEARCH_BAR_H - #ifndef NO_GRAPHICS -#include "draw_global.h" +#include "atom_netlist_fwd.h" +#include "clustered_netlist_fwd.h" +#include "rr_graph_fwd.h" -#include "ezgl/point.hpp" #include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" -#include "draw_color.h" void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app); bool highlight_rr_nodes(RRNodeId hit_node); @@ -51,6 +48,5 @@ GdkEvent simulate_keypress(char key, GdkWindow* window); //Returns current search type std::string get_search_type(ezgl::application* app); -#endif /* NO_GRAPHICS */ -#endif /* SEARCH_BAR_H */ +#endif /* NO_GRAPHICS */ diff --git a/vpr/src/draw/ui_setup.cpp b/vpr/src/draw/ui_setup.cpp index d62d8210e63..d03bb717279 100644 --- a/vpr/src/draw/ui_setup.cpp +++ b/vpr/src/draw/ui_setup.cpp @@ -1,4 +1,3 @@ -#ifndef NO_GRAPHICS /** * @file UI_SETUP.CPP * @author Sebastian Lievano @@ -10,18 +9,18 @@ * Each function here initializes a different set of ui buttons, connecting their callback functions */ -#include "draw_global.h" +#ifndef NO_GRAPHICS + +#include "clustered_netlist.h" #include "draw.h" +#include "draw_global.h" #include "draw_toggle_functions.h" -#include "buttons.h" -#include "intra_logic_block.h" -#include "clustered_netlist.h" -#include "ui_setup.h" #include "save_graphics.h" +#include "search_bar.h" +#include "ui_setup.h" -#include "ezgl/point.hpp" #include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" + void basic_button_setup(ezgl::application* app) { //button to enter window_mode, created in main.ui GtkButton* window = (GtkButton*)app->get_object("Window"); diff --git a/vpr/src/draw/ui_setup.h b/vpr/src/draw/ui_setup.h index 3b543adb493..9ab81448091 100644 --- a/vpr/src/draw/ui_setup.h +++ b/vpr/src/draw/ui_setup.h @@ -1,3 +1,4 @@ +#pragma once /** * @file ui_setup.h * @brief declares ui setup functions @@ -9,16 +10,11 @@ * Author: Sebastian Lievano */ -#ifndef UISETUP_H -#define UISETUP_H - #ifndef NO_GRAPHICS -#include "draw_global.h" - -#include "ezgl/point.hpp" #include "ezgl/application.hpp" -#include "ezgl/graphics.hpp" + +#include /** * @brief configures basic buttons @@ -100,5 +96,3 @@ void hide_widget(std::string widgetName, ezgl::application* app); void show_widget(std::string widgetName, ezgl::application* app); #endif /* NO_GRAPHICS */ - -#endif /* UISETUP_H */ diff --git a/vpr/src/main.cpp b/vpr/src/main.cpp index 6643de94840..3d4607473a2 100644 --- a/vpr/src/main.cpp +++ b/vpr/src/main.cpp @@ -58,6 +58,12 @@ int main(int argc, const char** argv) { return SUCCESS_EXIT_CODE; } + if (Options.show_arch_resources) { + vpr_print_arch_resources(vpr_setup, Arch); + vpr_free_all(Arch, vpr_setup); + return SUCCESS_EXIT_CODE; + } + bool flow_succeeded = vpr_flow(vpr_setup, Arch); if (!flow_succeeded) { VTR_LOG("VPR failed to implement circuit\n"); diff --git a/vpr/src/noc/bfs_routing.cpp b/vpr/src/noc/bfs_routing.cpp index ef7d5c00d0e..f334de57d0f 100644 --- a/vpr/src/noc/bfs_routing.cpp +++ b/vpr/src/noc/bfs_routing.cpp @@ -1,5 +1,6 @@ #include +#include "vpr_error.h" #include "bfs_routing.h" diff --git a/vpr/src/noc/bfs_routing.h b/vpr/src/noc/bfs_routing.h index 7d881bed8b1..64f3bdaaff8 100644 --- a/vpr/src/noc/bfs_routing.h +++ b/vpr/src/noc/bfs_routing.h @@ -1,6 +1,4 @@ -#ifndef BFS_ROUTING -#define BFS_ROUTING - +#pragma once /** * @file * @brief This file defines the BFSRouting class. @@ -86,5 +84,3 @@ class BFSRouting : public NocRouting { const NocStorage& noc_model, const std::unordered_map& router_parent_link); }; - -#endif diff --git a/vpr/src/noc/channel_dependency_graph.h b/vpr/src/noc/channel_dependency_graph.h index 54bcb26ab3a..574e04bec7d 100644 --- a/vpr/src/noc/channel_dependency_graph.h +++ b/vpr/src/noc/channel_dependency_graph.h @@ -1,6 +1,4 @@ -#ifndef VTR_CHANNEL_DEPENDENCY_GRAPH_H -#define VTR_CHANNEL_DEPENDENCY_GRAPH_H - +#pragma once /** * @file * @brief This file declares the ChannelDependencyGraph class. @@ -56,5 +54,3 @@ class ChannelDependencyGraph { /** An adjacency list used to represent channel dependency graph.*/ vtr::vector> adjacency_list_; }; - -#endif //VTR_CHANNEL_DEPENDENCY_GRAPH_H diff --git a/vpr/src/noc/negative_first_routing.h b/vpr/src/noc/negative_first_routing.h index 74bd38e2ba9..468c71fc9da 100644 --- a/vpr/src/noc/negative_first_routing.h +++ b/vpr/src/noc/negative_first_routing.h @@ -1,6 +1,4 @@ -#ifndef VTR_NEGATIVE_FIRST_ROUTING_H -#define VTR_NEGATIVE_FIRST_ROUTING_H - +#pragma once /** * @file * @brief This file declares the NegativeFirstRouting class, which implements @@ -44,5 +42,3 @@ class NegativeFirstRouting : public TurnModelRouting { bool is_turn_legal(const std::array, 3>& noc_routers, const NocStorage& noc_model) const override; }; - -#endif //VTR_NEGATIVE_FIRST_ROUTING_H diff --git a/vpr/src/noc/noc_data_types.h b/vpr/src/noc/noc_data_types.h index 85752445245..97f2e931dc0 100644 --- a/vpr/src/noc/noc_data_types.h +++ b/vpr/src/noc/noc_data_types.h @@ -1,6 +1,4 @@ -#ifndef NOC_DATA_TYPES_H -#define NOC_DATA_TYPES_H - +#pragma once /** * @file * @brief This file contains datatype definitions which are used by the NoC data structures. @@ -27,5 +25,3 @@ typedef vtr::StrongId NocTrafficFlowId; /** Data type to index NoC groups. */ struct noc_group_id_tag; typedef vtr::StrongId NocGroupId; - -#endif diff --git a/vpr/src/noc/noc_link.h b/vpr/src/noc/noc_link.h index ba7ba01fbba..525dcf3f2fe 100644 --- a/vpr/src/noc/noc_link.h +++ b/vpr/src/noc/noc_link.h @@ -1,6 +1,4 @@ -#ifndef NOC_LINK_H -#define NOC_LINK_H - +#pragma once /** * @file * @brief This file defines the NocLink class. @@ -37,8 +35,6 @@ * */ -#include -#include "noc_router.h" #include "noc_data_types.h" class NocLink { @@ -120,5 +116,3 @@ class NocLink { */ operator NocLinkId() const; }; - -#endif diff --git a/vpr/src/noc/noc_router.h b/vpr/src/noc/noc_router.h index e7a2b04ab0e..cbdc26a03f5 100644 --- a/vpr/src/noc/noc_router.h +++ b/vpr/src/noc/noc_router.h @@ -1,6 +1,4 @@ -#ifndef NOC_ROUTER_H -#define NOC_ROUTER_H - +#pragma once /** * @file * @brief This file defines the NocRouter class. @@ -31,10 +29,8 @@ * between them. */ -#include -#include - -#include "clustered_netlist.h" +#include "clustered_netlist_fwd.h" +#include "physical_types.h" class NocRouter { private: @@ -118,5 +114,3 @@ class NocRouter { */ void set_router_block_ref(ClusterBlockId router_block_ref_id); }; - -#endif diff --git a/vpr/src/noc/noc_routing.h b/vpr/src/noc/noc_routing.h index 4804af6fa8c..5c27ad28bf0 100644 --- a/vpr/src/noc/noc_routing.h +++ b/vpr/src/noc/noc_routing.h @@ -1,6 +1,4 @@ -#ifndef VTR_NOCROUTING_H -#define VTR_NOCROUTING_H - +#pragma once /** * @file * @brief This file defines the NocRouting class, which handles the @@ -62,5 +60,3 @@ class NocRouting { std::vector& flow_route, const NocStorage& noc_model) = 0; }; - -#endif diff --git a/vpr/src/noc/noc_routing_algorithm_creator.h b/vpr/src/noc/noc_routing_algorithm_creator.h index 4c33d13f590..0d9a5ef6c68 100644 --- a/vpr/src/noc/noc_routing_algorithm_creator.h +++ b/vpr/src/noc/noc_routing_algorithm_creator.h @@ -1,6 +1,4 @@ -#ifndef NOC_ROUTING_ALGORITHM_CREATOR -#define NOC_ROUTING_ALGORITHM_CREATOR - +#pragma once /** * @file * @brief This file defines the NocRoutingAlgorithmCreator class, which creates @@ -20,8 +18,8 @@ #include #include - #include "noc_routing.h" +#include "noc_storage.h" class NocRoutingAlgorithmCreator { public: @@ -42,5 +40,3 @@ class NocRoutingAlgorithmCreator { static std::unique_ptr create_routing_algorithm(const std::string& routing_algorithm_name, const NocStorage& noc_model); }; - -#endif diff --git a/vpr/src/noc/noc_storage.cpp b/vpr/src/noc/noc_storage.cpp index 4cf62e8b173..e1aafa478a5 100644 --- a/vpr/src/noc/noc_storage.cpp +++ b/vpr/src/noc/noc_storage.cpp @@ -1,6 +1,7 @@ #include "noc_storage.h" #include "vtr_assert.h" +#include "vtr_log.h" #include "vpr_error.h" #include diff --git a/vpr/src/noc/noc_storage.h b/vpr/src/noc/noc_storage.h index deabfd27853..0ceaf3788d8 100644 --- a/vpr/src/noc/noc_storage.h +++ b/vpr/src/noc/noc_storage.h @@ -1,6 +1,4 @@ -#ifndef NOC_STORAGE_H -#define NOC_STORAGE_H - +#pragma once /** * @file * @brief This file defines the NocStorage class. @@ -36,9 +34,9 @@ */ #include -#include #include #include "noc_data_types.h" +#include "vpr_types.h" #include "vtr_vector.h" #include "noc_router.h" #include "noc_link.h" @@ -572,5 +570,3 @@ const std::vector>& NocStorage::get_noc_li return returnable_noc_link_const_refs_; } - -#endif diff --git a/vpr/src/noc/noc_traffic_flows.cpp b/vpr/src/noc/noc_traffic_flows.cpp index b0d7cfe1b46..088803a6350 100644 --- a/vpr/src/noc/noc_traffic_flows.cpp +++ b/vpr/src/noc/noc_traffic_flows.cpp @@ -1,6 +1,7 @@ #include "noc_traffic_flows.h" -#include "vpr_error.h" +#include "vtr_assert.h" +#include "vtr_util.h" // constructor indicates that the class has not been properly initialized yet as the user supplied traffic flows have not been added. NocTrafficFlows::NocTrafficFlows() { diff --git a/vpr/src/noc/noc_traffic_flows.h b/vpr/src/noc/noc_traffic_flows.h index a05a2e37696..f9a59ca4d28 100644 --- a/vpr/src/noc/noc_traffic_flows.h +++ b/vpr/src/noc/noc_traffic_flows.h @@ -1,6 +1,4 @@ -#ifndef NOC_TRAFFIC_FLOWS_H -#define NOC_TRAFFIC_FLOWS_H - +#pragma once /** * @file * @brief This file defines the NocTrafficFlows class, which contains all @@ -29,17 +27,13 @@ * around to different tiles on the FPGA device. * */ -#include + #include -#include #include #include #include "clustered_netlist_fwd.h" #include "noc_data_types.h" #include "vtr_vector.h" -#include "echo_files.h" -#include "vtr_util.h" -#include "vtr_assert.h" /** * @brief Describes a traffic flow within the NoC, which is the communication @@ -314,5 +308,3 @@ class NocTrafficFlows { */ static constexpr double DEFAULT_MAX_TRAFFIC_FLOW_LATENCY = 1.; }; - -#endif diff --git a/vpr/src/noc/north_last_routing.h b/vpr/src/noc/north_last_routing.h index 3d755d67624..dbfe8381303 100644 --- a/vpr/src/noc/north_last_routing.h +++ b/vpr/src/noc/north_last_routing.h @@ -1,6 +1,4 @@ -#ifndef VTR_NORTH_LAST_ROUTING_H -#define VTR_NORTH_LAST_ROUTING_H - +#pragma once /** * @file * @brief This file declares the NorthLastRouting class, which implements @@ -45,5 +43,3 @@ class NorthLastRouting : public TurnModelRouting { bool is_turn_legal(const std::array, 3>& noc_routers, const NocStorage& noc_model) const override; }; - -#endif //VTR_NORTH_LAST_ROUTING_H diff --git a/vpr/src/noc/odd_even_routing.h b/vpr/src/noc/odd_even_routing.h index da61c5f3e9b..f6a0cf8074e 100644 --- a/vpr/src/noc/odd_even_routing.h +++ b/vpr/src/noc/odd_even_routing.h @@ -1,5 +1,4 @@ -#ifndef VTR_ODD_EVEN_ROUTING_H -#define VTR_ODD_EVEN_ROUTING_H +#pragma once #include "turn_model_routing.h" @@ -90,5 +89,3 @@ class OddEvenRouting : public TurnModelRouting { */ vtr::vector compressed_noc_locs_; }; - -#endif //VTR_ODD_EVEN_ROUTING_H diff --git a/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp b/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp index 6b3df6c7ad9..2be62047455 100644 --- a/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp +++ b/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp @@ -1,6 +1,11 @@ #include "read_xml_noc_traffic_flows_file.h" +#include +#include "ShowSetup.h" +#include "echo_files.h" +#include "globals.h" #include "physical_types_util.h" +#include "pugixml_util.hpp" void read_xml_noc_traffic_flows_file(const char* noc_flows_file) { // start by checking that the provided file is a ".flows" file diff --git a/vpr/src/noc/read_xml_noc_traffic_flows_file.h b/vpr/src/noc/read_xml_noc_traffic_flows_file.h index b53a0e432be..336e5458710 100644 --- a/vpr/src/noc/read_xml_noc_traffic_flows_file.h +++ b/vpr/src/noc/read_xml_noc_traffic_flows_file.h @@ -1,6 +1,4 @@ -#ifndef READ_XML_NOC_TRAFFIC_FLOWS_FILE_H -#define READ_XML_NOC_TRAFFIC_FLOWS_FILE_H - +#pragma once /** * @brief The purpose of this file is to read and parse an xml file that has * a '.flows' extension. This file contains the description of @@ -17,25 +15,19 @@ * */ +#include "clustered_netlist_fwd.h" +#include "physical_types.h" #include "pugixml.hpp" -#include "pugixml_util.hpp" -#include "read_xml_util.h" -#include "globals.h" - -#include "vtr_assert.h" -#include "vtr_util.h" -#include "ShowSetup.h" -#include "vpr_error.h" -#include "echo_files.h" - -#include "noc_data_types.h" -#include "noc_traffic_flows.h" +#include "pugixml_loc.hpp" -#include #include #include #include +struct DeviceContext; +struct ClusteringContext; +struct NocContext; + // identifier when an integer conversion failed while reading an attribute value in an xml file constexpr int NUMERICAL_ATTRIBUTE_CONVERSION_FAILURE = -1; @@ -256,5 +248,3 @@ bool check_that_all_router_blocks_have_an_associated_traffic_flow(NocContext& no * are compatible with a NoC router tile. */ std::vector get_cluster_blocks_compatible_with_noc_router_tiles(const ClusteringContext& cluster_ctx, t_physical_tile_type_ptr noc_router_tile_type); - -#endif diff --git a/vpr/src/noc/sat_routing.h b/vpr/src/noc/sat_routing.h index 60f9a900fb0..6eb560e20bc 100644 --- a/vpr/src/noc/sat_routing.h +++ b/vpr/src/noc/sat_routing.h @@ -1,6 +1,4 @@ -#ifndef VTR_SATROUTING_H -#define VTR_SATROUTING_H - +#pragma once /** * @file * @brief SAT formulation of NoC traffic flow routing. @@ -67,4 +65,3 @@ struct hash> { } // namespace std #endif -#endif diff --git a/vpr/src/noc/turn_model_routing.cpp b/vpr/src/noc/turn_model_routing.cpp index 398af104844..2cb61286b56 100644 --- a/vpr/src/noc/turn_model_routing.cpp +++ b/vpr/src/noc/turn_model_routing.cpp @@ -1,5 +1,6 @@ #include "turn_model_routing.h" +#include "vpr_error.h" TurnModelRouting::~TurnModelRouting() = default; diff --git a/vpr/src/noc/turn_model_routing.h b/vpr/src/noc/turn_model_routing.h index 7263c3d813d..9db6db7932e 100644 --- a/vpr/src/noc/turn_model_routing.h +++ b/vpr/src/noc/turn_model_routing.h @@ -1,6 +1,4 @@ -#ifndef VTR_TURN_MODEL_ROUTING_H -#define VTR_TURN_MODEL_ROUTING_H - +#pragma once /** * @file * @brief This file declares the TurnModelRouting class, which abstract all @@ -274,5 +272,3 @@ class TurnModelRouting : public NocRouting { private: std::vector inputs_to_murmur3_hasher{4}; }; - -#endif //VTR_TURN_MODEL_ROUTING_H diff --git a/vpr/src/noc/west_first_routing.h b/vpr/src/noc/west_first_routing.h index e9acb7588c0..4e0912af4bb 100644 --- a/vpr/src/noc/west_first_routing.h +++ b/vpr/src/noc/west_first_routing.h @@ -1,6 +1,4 @@ -#ifndef VTR_WEST_FIRST_ROUTING_H -#define VTR_WEST_FIRST_ROUTING_H - +#pragma once /** * @file * @brief This file declares the WestFirstRouting class, which implements @@ -44,5 +42,3 @@ class WestFirstRouting : public TurnModelRouting { bool is_turn_legal(const std::array, 3>& noc_routers, const NocStorage& noc_model) const override; }; - -#endif //VTR_WEST_FIRST_ROUTING_H diff --git a/vpr/src/noc/xy_routing.h b/vpr/src/noc/xy_routing.h index f676cb45f71..2deb8ef1728 100644 --- a/vpr/src/noc/xy_routing.h +++ b/vpr/src/noc/xy_routing.h @@ -1,6 +1,4 @@ -#ifndef VTR_XYROUTING_H -#define VTR_XYROUTING_H - +#pragma once /** * @file * @brief This file defines the XYRouting class, which represents a direction @@ -117,5 +115,3 @@ class XYRouting : public TurnModelRouting { const std::vector down_direction{TurnModelRouting::Direction::DOWN}; const std::vector no_direction{}; }; - -#endif diff --git a/vpr/src/pack/appack_context.h b/vpr/src/pack/appack_context.h index 4235fb1fd95..4cc7e84fd89 100644 --- a/vpr/src/pack/appack_context.h +++ b/vpr/src/pack/appack_context.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Siner @@ -6,8 +7,6 @@ * information used to configure APPack in the packer. */ -#pragma once - #include "appack_max_dist_th_manager.h" #include "device_grid.h" #include "flat_placement_types.h" diff --git a/vpr/src/pack/appack_max_dist_th_manager.h b/vpr/src/pack/appack_max_dist_th_manager.h index 558b224c56b..5dc461b2a67 100644 --- a/vpr/src/pack/appack_max_dist_th_manager.h +++ b/vpr/src/pack/appack_max_dist_th_manager.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -6,8 +7,6 @@ * thresholding optimization used within APPack. */ -#pragma once - #include #include #include "physical_types.h" diff --git a/vpr/src/pack/atom_pb_bimap.h b/vpr/src/pack/atom_pb_bimap.h index d8623543910..88f58cbab3c 100644 --- a/vpr/src/pack/atom_pb_bimap.h +++ b/vpr/src/pack/atom_pb_bimap.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Amir Poolad @@ -8,8 +9,6 @@ * contains a two way mapping between AtomBlockIds and pb types. */ -#pragma once - #include "vpr_types.h" // Forward declaration diff --git a/vpr/src/pack/attraction_groups.h b/vpr/src/pack/attraction_groups.h index d0d79c721b6..7790a743acb 100644 --- a/vpr/src/pack/attraction_groups.h +++ b/vpr/src/pack/attraction_groups.h @@ -1,3 +1,4 @@ +#pragma once /* * attraction_groups.h * @@ -5,9 +6,6 @@ * Author: khalid88 */ -#ifndef VPR_SRC_PACK_ATTRACTION_GROUPS_H_ -#define VPR_SRC_PACK_ATTRACTION_GROUPS_H_ - #include "vtr_strong_id.h" #include "vtr_vector.h" #include "atom_netlist_fwd.h" @@ -135,5 +133,3 @@ inline void AttractionInfo::set_attraction_group_gain(const AttractGroupId group inline AttractionGroup& AttractionInfo::get_attraction_group_info(const AttractGroupId group_id) { return attraction_groups[group_id]; } - -#endif /* VPR_SRC_PACK_ATTRACTION_GROUPS_H_ */ diff --git a/vpr/src/pack/cluster_feasibility_filter.h b/vpr/src/pack/cluster_feasibility_filter.h index e56f3a67a90..53e452bc908 100644 --- a/vpr/src/pack/cluster_feasibility_filter.h +++ b/vpr/src/pack/cluster_feasibility_filter.h @@ -1,3 +1,4 @@ +#pragma once /* * Feasibility filter used during packing that determines if various necessary conditions for legality are met * @@ -19,11 +20,6 @@ * */ -#ifndef CLUSTER_FEASIBILITY_CHECK_H -#define CLUSTER_FEASIBILITY_CHECK_H - class t_pb_graph_node; void load_pin_classes_in_pb_graph_head(t_pb_graph_node* pb_graph_node); - -#endif diff --git a/vpr/src/pack/cluster_legalizer.h b/vpr/src/pack/cluster_legalizer.h index 8cdd42df298..f9c5493dce8 100644 --- a/vpr/src/pack/cluster_legalizer.h +++ b/vpr/src/pack/cluster_legalizer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -10,8 +11,6 @@ * externally to the Packer in VPR. */ -#pragma once - #include #include "atom_netlist_fwd.h" #include "noc_data_types.h" diff --git a/vpr/src/pack/cluster_placement.h b/vpr/src/pack/cluster_placement.h index 2f3e438b0fd..facb8b3c68e 100644 --- a/vpr/src/pack/cluster_placement.h +++ b/vpr/src/pack/cluster_placement.h @@ -1,11 +1,9 @@ +#pragma once /* * Find placement for group of atom blocks in complex block * Author: Jason Luu */ -#ifndef CLUSTER_PLACEMENT_H -#define CLUSTER_PLACEMENT_H - #include #include #include "physical_types.h" @@ -186,5 +184,3 @@ bool exists_free_primitive_for_atom_block( void reset_tried_but_unused_cluster_placements( t_intra_cluster_placement_stats* cluster_placement_stats); - -#endif diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index 40d689b514d..35b0892ec42 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -1,11 +1,10 @@ +#pragma once /* * Intra-logic block router determines if a candidate packing solution (or intermediate solution) can route. * * Author: Jason Luu * Date: July 22, 2013 */ -#ifndef CLUSTER_ROUTER_H -#define CLUSTER_ROUTER_H #include #include "atom_netlist_fwd.h" @@ -40,5 +39,3 @@ t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_ t_logical_block_type_ptr logic_block_type, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup); void free_pb_route(t_pb_route* free_pb_route); - -#endif diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index 60c67f3c7d1..1fe7ff1ae68 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -6,6 +6,7 @@ #include "attraction_groups.h" #include "cluster_legalizer.h" #include "clustered_netlist.h" +#include "echo_files.h" #include "globals.h" #include "logic_types.h" #include "output_clustering.h" @@ -272,11 +273,8 @@ void print_pb_type_count(const ClusteredNetlist& clb_nlist) { VTR_LOG("\n"); } -t_logical_block_type_ptr identify_logic_block_type(const vtr::vector>& primitive_candidate_block_types, - const LogicalModels& models) { - LogicalModelId lut_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES); - - VTR_ASSERT(lut_model_id.is_valid()); +t_logical_block_type_ptr identify_logic_block_type(const vtr::vector>& primitive_candidate_block_types) { + LogicalModelId lut_model_id = LogicalModels::MODEL_NAMES_ID; if (primitive_candidate_block_types[lut_model_id].size() == 0) return nullptr; diff --git a/vpr/src/pack/cluster_util.h b/vpr/src/pack/cluster_util.h index 82fcf805047..084ff454cdf 100644 --- a/vpr/src/pack/cluster_util.h +++ b/vpr/src/pack/cluster_util.h @@ -1,5 +1,4 @@ -#ifndef CLUSTER_UTIL_H -#define CLUSTER_UTIL_H +#pragma once #include #include @@ -91,8 +90,7 @@ void print_pb_type_count(const ClusteredNetlist& clb_nlist); * @brief This function identifies the logic block type which is defined by the * block type which has a lut primitive. */ -t_logical_block_type_ptr identify_logic_block_type(const vtr::vector>& primitive_candidate_block_types, - const LogicalModels& models); +t_logical_block_type_ptr identify_logic_block_type(const vtr::vector>& primitive_candidate_block_types); /* * @brief This function returns the pb_type that is similar to Logic Element (LE) @@ -124,4 +122,3 @@ void print_le_count(int num_logic_le, void init_clb_atoms_lookup(vtr::vector>& atoms_lookup, const AtomContext& atom_ctx, const ClusteredNetlist& clb_nlist); -#endif diff --git a/vpr/src/pack/constraints_report.h b/vpr/src/pack/constraints_report.h index 779f629ba69..0a74ba17c83 100644 --- a/vpr/src/pack/constraints_report.h +++ b/vpr/src/pack/constraints_report.h @@ -1,9 +1,8 @@ +#pragma once /* Perform a check at the end of each packing iteration to see whether any * floorplan regions have been packed with too many clusters. */ -#pragma once - #include class ClusterLegalizer; diff --git a/vpr/src/pack/greedy_candidate_selector.h b/vpr/src/pack/greedy_candidate_selector.h index b39ad469b45..9888cca5697 100644 --- a/vpr/src/pack/greedy_candidate_selector.h +++ b/vpr/src/pack/greedy_candidate_selector.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -7,8 +8,6 @@ * maintains the gains of packing molecules into clusters. */ -#pragma once - #include #include #include @@ -22,7 +21,6 @@ #include "vtr_ndmatrix.h" #include "vtr_vector.h" #include "vtr_random.h" -#include "vtr_vector_map.h" #include "lazy_pop_unique_priority_queue.h" // Forward declarations diff --git a/vpr/src/pack/greedy_clusterer.cpp b/vpr/src/pack/greedy_clusterer.cpp index b7845c4f564..91cfd532a93 100644 --- a/vpr/src/pack/greedy_clusterer.cpp +++ b/vpr/src/pack/greedy_clusterer.cpp @@ -144,8 +144,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, pre_cluster_timing_manager_); // Pick the first seed molecule. - PackMoleculeId seed_mol_id = seed_selector.get_next_seed(prepacker, - cluster_legalizer); + PackMoleculeId seed_mol_id = seed_selector.get_next_seed(cluster_legalizer); /**************************************************************** * Clustering @@ -213,8 +212,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, cluster_legalizer); // Pick new seed. - seed_mol_id = seed_selector.get_next_seed(prepacker, - cluster_legalizer); + seed_mol_id = seed_selector.get_next_seed(cluster_legalizer); } // If this architecture has LE physical block, report its usage. @@ -526,7 +524,7 @@ bool GreedyClusterer::try_add_candidate_mol_to_cluster(PackMoleculeId candidate_ void GreedyClusterer::report_le_physical_block_usage(const ClusterLegalizer& cluster_legalizer) { // find the cluster type that has lut primitives - auto logic_block_type = identify_logic_block_type(primitive_candidate_block_types_, arch_.models); + auto logic_block_type = identify_logic_block_type(primitive_candidate_block_types_); // find a LE pb_type within the found logic_block_type auto le_pb_type = identify_le_block_type(logic_block_type); diff --git a/vpr/src/pack/greedy_clusterer.h b/vpr/src/pack/greedy_clusterer.h index cb92a0dbccf..ae22949f568 100644 --- a/vpr/src/pack/greedy_clusterer.h +++ b/vpr/src/pack/greedy_clusterer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -6,8 +7,6 @@ * encapsulate the process of greedy clustering. */ -#pragma once - #include #include #include @@ -18,11 +17,11 @@ #include "vtr_vector.h" // Forward declarations -class APPackContext; +struct APPackContext; class AtomNetId; class AtomNetlist; class AttractionInfo; -class DeviceContext; +struct DeviceContext; class GreedyCandidateSelector; class PreClusterTimingManager; class t_pack_high_fanout_thresholds; diff --git a/vpr/src/pack/greedy_seed_selector.cpp b/vpr/src/pack/greedy_seed_selector.cpp index 9850500400a..9ce473cba1e 100644 --- a/vpr/src/pack/greedy_seed_selector.cpp +++ b/vpr/src/pack/greedy_seed_selector.cpp @@ -9,6 +9,8 @@ #include #include +#include +#include #include "PreClusterTimingManager.h" #include "atom_netlist.h" #include "cluster_legalizer.h" @@ -129,11 +131,12 @@ static inline float get_seed_gain(AtomBlockId blk_id, * criticalities. */ static inline void print_seed_gains(const char* fname, - const std::vector& seed_atoms, - const vtr::vector& atom_gain, + const std::vector& seed_mols, + const vtr::vector& molecule_gain, const vtr::vector& atom_criticality, const AtomNetlist& atom_netlist, - const LogicalModels& models) { + const LogicalModels& models, + const Prepacker& prepacker) { FILE* fp = vtr::fopen(fname, "w"); // For pretty formatting determine the maximum name length @@ -148,16 +151,18 @@ static inline void print_seed_gains(const char* fname, fprintf(fp, "%-*s %-*s %8s %8s\n", max_name_len, "atom_block_name", max_type_len, "atom_block_type", "gain", "criticality"); fprintf(fp, "\n"); - for (auto blk_id : seed_atoms) { - std::string name = atom_netlist.block_name(blk_id); - fprintf(fp, "%-*s ", max_name_len, name.c_str()); + for (auto mol_id : seed_mols) { + for (AtomBlockId blk_id : prepacker.get_molecule(mol_id).atom_block_ids) { + std::string name = atom_netlist.block_name(blk_id); + fprintf(fp, "%-*s ", max_name_len, name.c_str()); - std::string model_name = models.model_name(atom_netlist.block_model(blk_id)); - fprintf(fp, "%-*s ", max_type_len, model_name.c_str()); + std::string model_name = models.model_name(atom_netlist.block_model(blk_id)); + fprintf(fp, "%-*s ", max_type_len, model_name.c_str()); - fprintf(fp, "%*f ", std::max((int)strlen("gain"), 8), atom_gain[blk_id]); - fprintf(fp, "%*f ", std::max((int)strlen("criticality"), 8), atom_criticality[blk_id]); - fprintf(fp, "\n"); + fprintf(fp, "%*f ", std::max((int)strlen("gain"), 8), molecule_gain[mol_id]); + fprintf(fp, "%*f ", std::max((int)strlen("criticality"), 8), atom_criticality[blk_id]); + fprintf(fp, "\n"); + } } fclose(fp); @@ -169,8 +174,8 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, const t_molecule_stats& max_molecule_stats, const LogicalModels& models, const PreClusterTimingManager& pre_cluster_timing_manager) - : seed_atoms_(atom_netlist.blocks().begin(), atom_netlist.blocks().end()) { - // Seed atoms list is initialized with all atoms in the atom netlist. + : seed_mols_(prepacker.molecules().begin(), prepacker.molecules().end()) { + // Seed molecule list is initialized with all molecule in the netlist. // Pre-compute the criticality of each atom // Default criticalities set to zero (e.g. if not timing driven) @@ -183,20 +188,31 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, } } - // Maintain a lookup table of the seed gain for each atom. This will be - // used to sort the seed atoms. + // Maintain a lookup table of the seed gain for each molecule. This will be + // used to sort the seed molecules. // Initially all gains are zero. - vtr::vector atom_gains(atom_netlist.blocks().size(), 0.f); - - // Get the seed gain of each atom. - for (AtomBlockId blk_id : atom_netlist.blocks()) { - atom_gains[blk_id] = get_seed_gain(blk_id, - atom_netlist, - prepacker, - models, - seed_type, - max_molecule_stats, - atom_criticality); + vtr::vector molecule_gains(seed_mols_.size(), 0.f); + + // Get the seed gain of each molecule. + for (PackMoleculeId mol_id : seed_mols_) { + // Gain of each molecule is the maximum gain of its atoms + float mol_gain = std::numeric_limits::lowest(); + const std::vector& molecule_atoms = prepacker.get_molecule(mol_id).atom_block_ids; + for (AtomBlockId blk_id : molecule_atoms) { + // If the molecule does not fit the entire pack pattern, it's possible to have invalid block ids in the molecule_atoms vector + if (blk_id == AtomBlockId::INVALID()) { + continue; + } + float atom_gain = get_seed_gain(blk_id, + atom_netlist, + prepacker, + models, + seed_type, + max_molecule_stats, + atom_criticality); + mol_gain = std::max(mol_gain, atom_gain); + } + molecule_gains[mol_id] = mol_gain; } // Sort seeds in descending order of seed gain (i.e. highest seed gain first) @@ -207,47 +223,42 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, // std::sort which does not specify how equal values are handled). Using a stable // sort ensures that regardless of the underlying sorting algorithm the same seed // order is produced regardless of compiler. - auto by_descending_gain = [&](const AtomBlockId lhs, const AtomBlockId rhs) { - return atom_gains[lhs] > atom_gains[rhs]; + auto by_descending_gain = [&](const PackMoleculeId lhs, const PackMoleculeId rhs) { + return molecule_gains[lhs] > molecule_gains[rhs]; }; - std::stable_sort(seed_atoms_.begin(), seed_atoms_.end(), by_descending_gain); + std::stable_sort(seed_mols_.begin(), seed_mols_.end(), by_descending_gain); // Print the seed gains if requested. if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES)) { print_seed_gains(getEchoFileName(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES), - seed_atoms_, atom_gains, atom_criticality, atom_netlist, models); + seed_mols_, molecule_gains, atom_criticality, atom_netlist, models, prepacker); } // Set the starting seed index (the index of the first molecule to propose). // The index of the first seed to propose is the first molecule in the - // seed atoms vector (i.e. the one with the highest seed gain). + // seed molecules vector (i.e. the one with the highest seed gain). seed_index_ = 0; } -PackMoleculeId GreedySeedSelector::get_next_seed(const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer) { - while (seed_index_ < seed_atoms_.size()) { - // Get the current seed atom at the seed index and increment the +PackMoleculeId GreedySeedSelector::get_next_seed(const ClusterLegalizer& cluster_legalizer) { + while (seed_index_ < seed_mols_.size()) { + // Get the current seed molecule at the seed index and increment the // seed index. // All previous seed indices have been either proposed already or // are already clustered. This process assumes that once an atom // is clustered it will never become unclustered. - AtomBlockId seed_blk_id = seed_atoms_[seed_index_++]; + PackMoleculeId seed_molecule_id = seed_mols_[seed_index_++]; - // If this atom has been clustered, it cannot be proposed as a seed. + // If this molecule has been clustered, it cannot be proposed as a seed. // Skip to the next seed. - if (cluster_legalizer.is_atom_clustered(seed_blk_id)) + if (cluster_legalizer.is_mol_clustered(seed_molecule_id)) { continue; - - // Get the molecule that contains this atom and return it as the - // next seed. - PackMoleculeId seed_molecule_id = prepacker.get_atom_molecule(seed_blk_id); - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_molecule_id)); + } return seed_molecule_id; } // If the previous loop does not return a molecule, it implies that all - // atoms have been clustered or have already been proposed as a seed. + // molecule have been clustered or have already been proposed as a seed. // Return nullptr to signify that there are no further seeds. return PackMoleculeId::INVALID(); } diff --git a/vpr/src/pack/greedy_seed_selector.h b/vpr/src/pack/greedy_seed_selector.h index 0207949bef1..61f618cdd2c 100644 --- a/vpr/src/pack/greedy_seed_selector.h +++ b/vpr/src/pack/greedy_seed_selector.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -6,8 +7,6 @@ * seed molecules for starting new clusters in the greedy clusterer. */ -#pragma once - #include "prepack.h" #include "vpr_types.h" @@ -68,32 +67,24 @@ class GreedySeedSelector { * This method assumes that once a molecule is clustered, it will never be * unclustered. * - * @param prepacker - * The prepacker object that stores the molecules. * @param cluster_legalizer * The cluster legalizer object that is used to create the * clusters. This is used to check if a molecule has already * been clustered or not. */ - PackMoleculeId get_next_seed(const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer); + PackMoleculeId get_next_seed(const ClusterLegalizer& cluster_legalizer); - // TODO: Maybe create an update_seed_gains method to update the seed atoms + // TODO: Maybe create an update_seed_gains method to update the seed molecules // list using current clustering information. private: - /// @brief The index of the next seed to propose in the seed_atoms vector. + /// @brief The index of the next seed to propose in the seed_mols_ vector. /// This is set to 0 in the constructor and incremented as more seeds /// are proposed. size_t seed_index_; - /// @brief A list of seed atoms, sorted in decreasing order of gain. This + /// @brief A list of seed molecules, sorted in decreasing order of gain. This /// is computed in the constructor and is traversed when a new seed /// is being proposed. - // FIXME: This should really be seed molecules. It looks like the only - // reason it isn't is because of the atom criticality. May want to - // create the concept of molecule criticality. Currently, the max - // criticality of any block in the molecule is technically being - // used. - std::vector seed_atoms_; + std::vector seed_mols_; }; diff --git a/vpr/src/pack/lb_type_rr_graph.h b/vpr/src/pack/lb_type_rr_graph.h index 188254a3b39..16c353c9442 100644 --- a/vpr/src/pack/lb_type_rr_graph.h +++ b/vpr/src/pack/lb_type_rr_graph.h @@ -1,3 +1,4 @@ +#pragma once /* * Functions to creates, manipulate, and free the lb_type_rr_node graph that represents interconnect within a logic block type. * @@ -5,9 +6,6 @@ * Date: July 22, 2013 */ -#ifndef LB_TYPE_RR_GRAPH_H -#define LB_TYPE_RR_GRAPH_H - #include "pack_types.h" /* Constructors/Destructors */ @@ -21,5 +19,3 @@ int get_lb_type_rr_graph_edge_mode(std::vector& lb_type_rr_gr /* Debug functions */ void echo_lb_type_rr_graphs(char* filename, std::vector* lb_type_rr_graphs); - -#endif diff --git a/vpr/src/pack/noc_aware_cluster_util.h b/vpr/src/pack/noc_aware_cluster_util.h index dbdb79d5785..5c3f6a3246b 100644 --- a/vpr/src/pack/noc_aware_cluster_util.h +++ b/vpr/src/pack/noc_aware_cluster_util.h @@ -1,6 +1,4 @@ -#ifndef VTR_NOC_AWARE_CLUSTER_UTIL_H -#define VTR_NOC_AWARE_CLUSTER_UTIL_H - +#pragma once /** * @file This file includes helper functions used to find NoC groups * in the atom netlist and assign NoC group IDs to atom blocks. @@ -45,5 +43,3 @@ void update_noc_reachability_partitions(const std::vector& noc_atom const AtomNetlist& atom_netlist, const t_pack_high_fanout_thresholds& high_fanout_threshold, vtr::vector& atom_noc_grp_id); - -#endif diff --git a/vpr/src/pack/output_clustering.h b/vpr/src/pack/output_clustering.h index c7537ee8c39..e40af137eee 100644 --- a/vpr/src/pack/output_clustering.h +++ b/vpr/src/pack/output_clustering.h @@ -1,5 +1,4 @@ -#ifndef OUTPUT_CLUSTERING_H -#define OUTPUT_CLUSTERING_H +#pragma once #include #include @@ -25,5 +24,3 @@ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, void write_packing_results_to_xml(const std::string& architecture_id, const char* out_fname); - -#endif diff --git a/vpr/src/pack/pack.h b/vpr/src/pack/pack.h index f484146ac66..26b23182cb0 100644 --- a/vpr/src/pack/pack.h +++ b/vpr/src/pack/pack.h @@ -1,5 +1,4 @@ -#ifndef PACK_H -#define PACK_H +#pragma once #include #include @@ -46,5 +45,3 @@ bool try_pack(const t_packer_opts& packer_opts, const FlatPlacementInfo& flat_placement_info); std::unordered_set alloc_and_load_is_clock(); - -#endif diff --git a/vpr/src/pack/pack_report.h b/vpr/src/pack/pack_report.h index 75fd0d36058..1f4b20e3df6 100644 --- a/vpr/src/pack/pack_report.h +++ b/vpr/src/pack/pack_report.h @@ -1,9 +1,6 @@ -#ifndef VPR_PACK_REPORT_H -#define VPR_PACK_REPORT_H +#pragma once #include #include "vpr_context.h" void report_packing_pin_usage(std::ostream& os, const VprContext& ctx); - -#endif diff --git a/vpr/src/pack/pack_types.h b/vpr/src/pack/pack_types.h index 994dbd73f1f..1d3c336072c 100644 --- a/vpr/src/pack/pack_types.h +++ b/vpr/src/pack/pack_types.h @@ -1,5 +1,4 @@ -#ifndef PACK_TYPES_H -#define PACK_TYPES_H +#pragma once /** * Jason Luu * July 22, 2013 @@ -13,7 +12,7 @@ #include "atom_netlist_fwd.h" #include "physical_types.h" -struct t_pack_molecule; +class t_pack_molecule; /************************************************************************** * Packing Algorithm Enumerations @@ -244,5 +243,3 @@ struct t_mode_selection_status { return is_mode_conflict || try_expand_all_modes; } }; - -#endif diff --git a/vpr/src/pack/pb_type_graph.h b/vpr/src/pack/pb_type_graph.h index cda5bdf1696..00e7af6777d 100644 --- a/vpr/src/pack/pb_type_graph.h +++ b/vpr/src/pack/pb_type_graph.h @@ -1,5 +1,4 @@ -#ifndef PB_TYPE_GRAPH_H -#define PB_TYPE_GRAPH_H +#pragma once #include "physical_types.h" @@ -29,4 +28,3 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num, int* num_sets, const bool is_input_to_interc, const bool interconnect_error_check); -#endif diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index e0988af7143..2b78a2a6d97 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -6,6 +6,7 @@ #include #include #include +#include #include "arch_util.h" #include "vtr_assert.h" @@ -17,7 +18,7 @@ #include "pb_type_graph.h" #include "pb_type_graph_annotations.h" -static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const char* value); +static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value); static void load_delay_annotations(const int line_num, t_pb_graph_node* pb_graph_node, @@ -36,30 +37,25 @@ static void inferr_unspecified_pb_graph_edge_delays(t_pb_graph_edge* pb_graph_pi static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, const char* clock, int line_num); void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { - int i, j, k, m; - const t_pb_type* pb_type; - t_pin_to_pin_annotation* annotations; - - pb_type = pb_graph_node->pb_type; + const t_pb_type* pb_type = pb_graph_node->pb_type; /* Load primitive critical path delays */ if (pb_type->is_primitive()) { - annotations = pb_type->annotations; - for (i = 0; i < pb_type->num_annotations; i++) { - if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) { - for (j = 0; j < annotations[i].num_value_prop_pairs; j++) { - if (annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MIN - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP - || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { - load_delay_annotations(annotations[i].line_num, pb_graph_node, OPEN, - annotations[i].format, (enum e_pin_to_pin_delay_annotations)annotations[i].prop[j], - annotations[i].input_pins, - annotations[i].output_pins, - annotations[i].clock, - annotations[i].value[j]); + for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) { + if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) { + for (const auto& [key, val] : annotation.annotation_entries) { + if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN + || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN + || key == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP + || key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { + load_delay_annotations(annotation.line_num, pb_graph_node, OPEN, + annotation.format, (enum e_pin_to_pin_delay_annotations)key, + annotation.input_pins, + annotation.output_pins, + annotation.clock, + val.c_str()); } else { VTR_ASSERT(false); } @@ -68,35 +64,34 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { } } else { /* Load interconnect delays */ - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_interconnect; j++) { - annotations = pb_type->modes[i].interconnect[j].annotations; - for (k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; k++) { - if (annotations[k].type == E_ANNOT_PIN_TO_PIN_DELAY) { - for (m = 0; m < annotations[k].num_value_prop_pairs; m++) { - if (annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_MIN - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP - || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { - load_delay_annotations(annotations[k].line_num, pb_graph_node, i, - annotations[k].format, - (enum e_pin_to_pin_delay_annotations)annotations[k].prop[m], - annotations[k].input_pins, - annotations[k].output_pins, - annotations[k].clock, - annotations[k].value[m]); + for (int i = 0; i < pb_type->num_modes; i++) { + for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) { + for (const t_pin_to_pin_annotation& annotation : pb_type->modes[i].interconnect[j].annotations) { + if (annotation.type == E_ANNOT_PIN_TO_PIN_DELAY) { + for (const auto& [key, val] : annotation.annotation_entries) { + if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN + || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX + || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN + || key == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP + || key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { + load_delay_annotations(annotation.line_num, pb_graph_node, i, + annotation.format, + (enum e_pin_to_pin_delay_annotations)key, + annotation.input_pins, + annotation.output_pins, + annotation.clock, + val.c_str()); } else { VTR_ASSERT(false); } } - } else if (annotations[k].type == E_ANNOT_PIN_TO_PIN_PACK_PATTERN) { - VTR_ASSERT(annotations[k].num_value_prop_pairs == 1); - load_pack_pattern_annotations(annotations[k].line_num, pb_graph_node, i, - annotations[k].input_pins, - annotations[k].output_pins, - annotations[k].value[0]); + } else if (annotation.type == E_ANNOT_PIN_TO_PIN_PACK_PATTERN) { + VTR_ASSERT(annotation.annotation_entries.size() == 1); + load_pack_pattern_annotations(annotation.line_num, pb_graph_node, i, + annotation.input_pins, + annotation.output_pins, + annotation.annotation_entries[0].second); } else { /* Todo: * load_power_annotations(pb_graph_node); @@ -110,9 +105,9 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { inferr_unspecified_pb_graph_node_delays(pb_graph_node); //Recursively annotate child pb's - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { + for (int i = 0; i < pb_type->num_modes; i++) { + for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + for (int k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { load_pb_graph_pin_to_pin_annotations(&pb_graph_node->child_pb_graph_nodes[i][j][k]); } } @@ -122,7 +117,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { /* * Add the pattern name to the pack_pattern field for each pb_graph_edge that is used in a pack pattern */ -static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const char* value) { +static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* pb_graph_node, const int mode, const char* annot_in_pins, const char* annot_out_pins, const std::string& value) { int i, j, k, m, n, p, iedge; t_pb_graph_pin ***in_port, ***out_port; int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; @@ -151,7 +146,7 @@ static void load_pack_pattern_annotations(const int line_num, t_pb_graph_node* p if (iedge != in_port[i][j]->num_output_edges) { in_port[i][j]->output_edges[iedge]->num_pack_patterns++; in_port[i][j]->output_edges[iedge]->pack_pattern_names.resize(in_port[i][j]->output_edges[iedge]->num_pack_patterns); - in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value; + in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - 1] = value.c_str(); // TODO: convert to std::string } p++; } diff --git a/vpr/src/pack/pb_type_graph_annotations.h b/vpr/src/pack/pb_type_graph_annotations.h index 317f63b394c..3a55e2c0edd 100644 --- a/vpr/src/pack/pb_type_graph_annotations.h +++ b/vpr/src/pack/pb_type_graph_annotations.h @@ -1,14 +1,10 @@ +#pragma once /** * Jason Luu * April 15, 2011 * pb_type_graph_annotations loads statistical information onto the different nodes/edges of a pb_type_graph. These statistical informations include delays, capacitance, etc. */ -#ifndef PB_TYPE_GRAPH_ANNOTATIONS_H -#define PB_TYPE_GRAPH_ANNOTATIONS_H - class t_pb_graph_node; void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node); - -#endif diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.h b/vpr/src/pack/post_routing_pb_pin_fixup.h index 2459da04487..aa0896a0f77 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.h +++ b/vpr/src/pack/post_routing_pb_pin_fixup.h @@ -1,5 +1,4 @@ -#ifndef POST_ROUTING_PB_PIN_FIXUP_H -#define POST_ROUTING_PB_PIN_FIXUP_H +#pragma once /******************************************************************** * Include header files that are required by function declaration @@ -32,5 +31,3 @@ void sync_netlists_to_routing(const Netlist<>& net_list, ClusteringContext& clustering_ctx, const PlacementContext& placement_ctx, const bool& verbose); - -#endif diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 1f9f1a717bc..502b595ed82 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -71,8 +71,7 @@ static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_ static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, const std::multimap& atom_molecules, - const AtomNetlist& atom_nlist, - const LogicalModels& models); + const AtomNetlist& atom_nlist); static void print_pack_molecules(const char* fname, const std::vector& list_of_pack_patterns, @@ -120,8 +119,7 @@ static void init_molecule_chain_info(const AtomBlockId blk_id, static AtomBlockId get_sink_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, - const AtomNetlist& atom_nlist, - const LogicalModels& models); + const AtomNetlist& atom_nlist); static AtomBlockId get_driving_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, @@ -833,8 +831,7 @@ void Prepacker::alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, - const AtomNetlist& atom_nlist, - const LogicalModels& models) { + const AtomNetlist& atom_nlist) { auto pack_pattern = &list_of_pack_patterns[pack_pattern_index]; // Check pack pattern validity @@ -968,7 +964,7 @@ PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, molecule.root = pack_pattern->root_block->block_id; molecule.chain_id = MoleculeChainId::INVALID(); - if (!try_expand_molecule(molecule, blk_id, atom_molecules_multimap, atom_nlist, models)) { + if (!try_expand_molecule(molecule, blk_id, atom_molecules_multimap, atom_nlist)) { // Failed to create molecule return PackMoleculeId::INVALID(); } @@ -1012,8 +1008,7 @@ PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, const std::multimap& atom_molecules, - const AtomNetlist& atom_nlist, - const LogicalModels& models) { + const AtomNetlist& atom_nlist) { // root block of the pack pattern, which is the starting point of this pattern const auto pattern_root_block = molecule.pack_pattern->root_block; // bool array indicating whether a position in a pack pattern is optional or should @@ -1070,7 +1065,7 @@ static bool try_expand_molecule(t_pack_molecule& molecule, // this block is the driver of this connection if (block_connection->from_block == pattern_block) { // find the block this connection is driving and add it to the queue - auto sink_blk_id = get_sink_block(block_id, *block_connection, atom_nlist, models); + auto sink_blk_id = get_sink_block(block_id, *block_connection, atom_nlist); // add this sink block id with its corresponding pattern block to the queue pattern_block_queue.push(std::make_pair(block_connection->to_block, sink_blk_id)); // this block is being driven by this connection @@ -1102,8 +1097,7 @@ static bool try_expand_molecule(t_pack_molecule& molecule, */ static AtomBlockId get_sink_block(const AtomBlockId block_id, const t_pack_pattern_connections& connections, - const AtomNetlist& atom_nlist, - const LogicalModels& models) { + const AtomNetlist& atom_nlist) { const t_model_ports* from_port_model = connections.from_pin->port->model_port; const int from_pin_number = connections.from_pin->pin_number; auto from_port_id = atom_nlist.find_atom_port(block_id, from_port_model); @@ -1125,7 +1119,7 @@ static AtomBlockId get_sink_block(const AtomBlockId block_id, // Iterate through all sink blocks and check whether any of them // is compatible with the block specified in the pack pattern. bool connected_to_latch = false; - LogicalModelId latch_model_id = models.get_model_by_name(LogicalModels::MODEL_LATCH); + LogicalModelId latch_model_id = LogicalModels::MODEL_LATCH_ID; AtomBlockId pattern_sink_block_id = AtomBlockId::INVALID(); for (const auto& sink_pin_id : net_sinks) { auto sink_block_id = atom_nlist.pin_block(sink_pin_id); diff --git a/vpr/src/pack/prepack.h b/vpr/src/pack/prepack.h index 08c960f3105..f75ca8ac8b8 100644 --- a/vpr/src/pack/prepack.h +++ b/vpr/src/pack/prepack.h @@ -1,3 +1,4 @@ +#pragma once /* * Prepacking: Group together technology-mapped netlist blocks before packing. * This gives hints to the packer on what groups of blocks to keep together @@ -7,8 +8,6 @@ * 2) Carry-chains */ -#pragma once - #include #include "atom_netlist_fwd.h" #include "cad_types.h" @@ -327,8 +326,7 @@ class Prepacker { PackMoleculeId try_create_molecule(const int pack_pattern_index, AtomBlockId blk_id, std::multimap& atom_molecules_multimap, - const AtomNetlist& atom_nlist, - const LogicalModels& models); + const AtomNetlist& atom_nlist); private: /** diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 1e1a6830492..e1da710d40b 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -16,6 +16,7 @@ #include "vpr_utils.h" #include "sync_netlists_to_routing_flat.h" +#include /* Static function decls (file-scope) */ diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.h b/vpr/src/pack/sync_netlists_to_routing_flat.h index ef6b743fe30..cfe05967232 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.h +++ b/vpr/src/pack/sync_netlists_to_routing_flat.h @@ -1,3 +1,4 @@ +#pragma once /******************************************************************** * Top-level function to synchronize packing results to routing results. * Flat routing invalidates the ClusteredNetlist since nets may be routed diff --git a/vpr/src/pack/verify_clustering.h b/vpr/src/pack/verify_clustering.h index f13de9a6d48..34ea01cf808 100644 --- a/vpr/src/pack/verify_clustering.h +++ b/vpr/src/pack/verify_clustering.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -7,8 +8,6 @@ * the rest of the VPR flow. */ -#pragma once - #include #include "vtr_vector.h" diff --git a/vpr/src/pack/verify_flat_placement.h b/vpr/src/pack/verify_flat_placement.h index 44bfb47f3fd..97668a28e23 100644 --- a/vpr/src/pack/verify_flat_placement.h +++ b/vpr/src/pack/verify_flat_placement.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -7,8 +8,6 @@ * invalid data so this does not have to be checked during packing. */ -#pragma once - // Forward declarations class FlatPlacementInfo; class AtomNetlist; diff --git a/vpr/src/place/RL_agent_util.h b/vpr/src/place/RL_agent_util.h index 511cd73d0d6..2b7995f5490 100644 --- a/vpr/src/place/RL_agent_util.h +++ b/vpr/src/place/RL_agent_util.h @@ -1,5 +1,4 @@ -#ifndef RL_AGENT_UTIL_H -#define RL_AGENT_UTIL_H +#pragma once #include "move_generator.h" @@ -45,5 +44,3 @@ MoveGenerator& select_move_generator(std::unique_ptr& move_genera e_agent_state agent_state, const t_placer_opts& placer_opts, bool in_quench); - -#endif diff --git a/vpr/src/place/annealer.cpp b/vpr/src/place/annealer.cpp index 949dfe5b4c1..6183fceec61 100644 --- a/vpr/src/place/annealer.cpp +++ b/vpr/src/place/annealer.cpp @@ -5,7 +5,6 @@ #include #include "globals.h" -#include "draw_global.h" #include "place_macro.h" #include "vpr_types.h" #include "place_util.h" @@ -19,6 +18,11 @@ #include "RL_agent_util.h" #include "PlacerSetupSlacks.h" #include "PlacerCriticalities.h" +#include "vtr_expr_eval.h" + +#ifndef NO_GRAPHICS +#include "draw_global.h" +#endif // NO_GRAPHICS /**************************************************************************/ /*************** Static Function Declarations *****************************/ diff --git a/vpr/src/place/annealer.h b/vpr/src/place/annealer.h index 66abceea1e3..368b8c5607b 100644 --- a/vpr/src/place/annealer.h +++ b/vpr/src/place/annealer.h @@ -1,4 +1,3 @@ - #pragma once #include "vpr_types.h" @@ -6,6 +5,7 @@ #include "move_generator.h" // movestats #include "net_cost_handler.h" #include "manual_move_generator.h" +#include "vtr_random.h" #include #include diff --git a/vpr/src/place/compressed_grid.h b/vpr/src/place/compressed_grid.h index 8d6ecd9097b..37be37828e4 100644 --- a/vpr/src/place/compressed_grid.h +++ b/vpr/src/place/compressed_grid.h @@ -1,5 +1,4 @@ -#ifndef VPR_COMPRESSED_GRID_H -#define VPR_COMPRESSED_GRID_H +#pragma once #include #include "physical_types.h" @@ -186,5 +185,3 @@ std::vector create_compressed_block_grids(); * */ void echo_compressed_grids(const char* filename, const std::vector& comp_grids); - -#endif diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.h b/vpr/src/place/delay_model/PlacementDelayModelCreator.h index c003d85e034..2cfd4e5b12e 100644 --- a/vpr/src/place/delay_model/PlacementDelayModelCreator.h +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.h @@ -1,4 +1,3 @@ - #pragma once #include diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.h b/vpr/src/place/delay_model/compute_delta_delays_utils.h index d51c41cf18f..f79b54140aa 100644 --- a/vpr/src/place/delay_model/compute_delta_delays_utils.h +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.h @@ -1,4 +1,3 @@ - #pragma once #include "vtr_ndmatrix.h" diff --git a/vpr/src/place/delay_model/delta_delay_model.h b/vpr/src/place/delay_model/delta_delay_model.h index a4c548210ae..cbea2f18639 100644 --- a/vpr/src/place/delay_model/delta_delay_model.h +++ b/vpr/src/place/delay_model/delta_delay_model.h @@ -1,4 +1,3 @@ - #pragma once #include "place_delay_model.h" diff --git a/vpr/src/place/delay_model/override_delay_model.h b/vpr/src/place/delay_model/override_delay_model.h index e7d71c72318..9d46afa127b 100644 --- a/vpr/src/place/delay_model/override_delay_model.h +++ b/vpr/src/place/delay_model/override_delay_model.h @@ -1,4 +1,3 @@ - #pragma once #include "place_delay_model.h" diff --git a/vpr/src/place/delay_model/place_delay_model.h b/vpr/src/place/delay_model/place_delay_model.h index ba22125d712..04e7b0fac64 100644 --- a/vpr/src/place/delay_model/place_delay_model.h +++ b/vpr/src/place/delay_model/place_delay_model.h @@ -1,13 +1,10 @@ +#pragma once /** * @file place_delay_model.h * @brief This file contains all the class and function declarations related to * the placer delay model. For implementations, see place_delay_model.cpp. */ -#pragma once - -#include "vtr_ndmatrix.h" -#include "vtr_flat_map.h" #include "vpr_types.h" #include "router_delay_profiling.h" diff --git a/vpr/src/place/delay_model/simple_delay_model.h b/vpr/src/place/delay_model/simple_delay_model.h index 0a7ace6aece..220b5ff9eb1 100644 --- a/vpr/src/place/delay_model/simple_delay_model.h +++ b/vpr/src/place/delay_model/simple_delay_model.h @@ -1,4 +1,3 @@ - #pragma once #include "place_delay_model.h" diff --git a/vpr/src/place/grid_tile_lookup.h b/vpr/src/place/grid_tile_lookup.h index 74b858d6238..ccecfc00b3f 100644 --- a/vpr/src/place/grid_tile_lookup.h +++ b/vpr/src/place/grid_tile_lookup.h @@ -1,5 +1,4 @@ -#ifndef VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ -#define VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ +#pragma once #include #include "physical_types.h" @@ -89,5 +88,3 @@ class GridTileLookup { */ std::vector max_placement_locations; }; - -#endif /* VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ */ diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index 40376e3a187..86125ee46a9 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -8,6 +8,7 @@ #include "noc_place_checkpoint.h" #include "place_constraints.h" +#include "vtr_random.h" #include "vtr_time.h" /** diff --git a/vpr/src/place/initial_noc_placment.h b/vpr/src/place/initial_noc_placment.h index 1e62164b549..f130eaac0cf 100644 --- a/vpr/src/place/initial_noc_placment.h +++ b/vpr/src/place/initial_noc_placment.h @@ -1,6 +1,4 @@ - -#ifndef VTR_INITIAL_NOC_PLACEMENT_H -#define VTR_INITIAL_NOC_PLACEMENT_H +#pragma once struct t_noc_opts; struct t_placer_opts; @@ -26,5 +24,3 @@ void initial_noc_placement(const t_noc_opts& noc_opts, const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng); - -#endif //VTR_INITIAL_NOC_PLACEMENT_H diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index bcf6e3b7094..52a400c4b80 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -203,7 +203,8 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, * * @return true if the function can find any location near the centroid one, false otherwise. */ -static bool find_centroid_neighbor(t_pl_loc& centroid_loc, +static bool find_centroid_neighbor(ClusterBlockId block_id, + t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, int r_lim, @@ -212,7 +213,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, /** * @brief tries to place a macro at a centroid location of its placed connections. - * + * + * @param block_id The block to be placed. * @param pl_macro The macro to be placed. * @param pr The PartitionRegion of the macro - represents its floorplanning constraints, is the size of the whole chip if the macro is not * constrained. @@ -225,7 +227,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, * * @return true if the macro gets placed, false if not. */ -static bool try_centroid_placement(const t_pl_macro& pl_macro, +static bool try_centroid_placement(ClusterBlockId block_id, + const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, @@ -400,7 +403,8 @@ bool find_subtile_in_location(t_pl_loc& centroid, return false; } -static bool find_centroid_neighbor(t_pl_loc& centroid_loc, +static bool find_centroid_neighbor(ClusterBlockId block_id, + t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, int rlim, @@ -425,6 +429,18 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, int delta_cx = search_range.xmax - search_range.xmin; + bool block_constrained = is_cluster_constrained(block_id); + + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(block_id, + search_range, + delta_cx, + centroid_loc_layer_num); + if (!intersect) { + return false; + } + } + //Block has not been placed yet, so the "from" coords will be (-1, -1) int cx_from = OPEN; int cy_from = OPEN; @@ -441,7 +457,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, centroid_loc_layer_num, search_for_empty, blk_loc_registry, - rng); + rng, + block_constrained); if (!legal) { return false; @@ -832,7 +849,8 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat return best_loc; } -static bool try_centroid_placement(const t_pl_macro& pl_macro, +static bool try_centroid_placement(ClusterBlockId block_id, + const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, @@ -889,7 +907,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, //centroid suggestion was either occupied or does not match block type //try to find a near location that meet these requirements if (!found_legal_subtile) { - bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, rlim, blk_loc_registry, rng); + bool neighbor_legal_loc = find_centroid_neighbor(block_id, centroid_loc, block_type, false, rlim, blk_loc_registry, rng); if (!neighbor_legal_loc) { //no neighbor candidate found return false; } @@ -1065,6 +1083,9 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, bool legal; + // is_fixed_range is true since even if the block is not constrained, + // the search range covers the entire region, so there is no need for + // the search range to be adjusted legal = find_compatible_compressed_loc_in_range(block_type, delta_cx, {cx_from, cy_from, selected_layer}, @@ -1076,7 +1097,8 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, selected_layer, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + /*is_range_fixed=*/true); if (!legal) { //No valid position found @@ -1300,7 +1322,7 @@ static bool place_macro(int macros_max_num_tries, if (!macro_placed) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry centroid placement\n"); - macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); + macro_placed = try_centroid_placement(blk_id, pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); } VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tMacro is placed: %d\n", macro_placed); // If macro is not placed yet, try to place the macro randomly for the max number of random tries diff --git a/vpr/src/place/initial_placement.h b/vpr/src/place/initial_placement.h index b668ce92075..0a66f0694d8 100644 --- a/vpr/src/place/initial_placement.h +++ b/vpr/src/place/initial_placement.h @@ -1,5 +1,4 @@ -#ifndef VPR_INITIAL_PLACEMENT_H -#define VPR_INITIAL_PLACEMENT_H +#pragma once class NocCostHandler; @@ -173,5 +172,3 @@ bool place_one_block(const ClusterBlockId blk_id, const PlaceMacros& place_macros, const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); - -#endif diff --git a/vpr/src/place/move_generators/manual_move_generator.cpp b/vpr/src/place/move_generators/manual_move_generator.cpp index cebbe8e8dd6..a4e67644774 100644 --- a/vpr/src/place/move_generators/manual_move_generator.cpp +++ b/vpr/src/place/move_generators/manual_move_generator.cpp @@ -17,7 +17,7 @@ #include "placer_state.h" #ifndef NO_GRAPHICS -#include "draw.h" +#include "draw_global.h" #endif //NO_GRAPHICS ManualMoveGenerator::ManualMoveGenerator(PlacerState& placer_state, diff --git a/vpr/src/place/move_generators/manual_move_generator.h b/vpr/src/place/move_generators/manual_move_generator.h index 417ecb9d514..1c2e412e3b3 100644 --- a/vpr/src/place/move_generators/manual_move_generator.h +++ b/vpr/src/place/move_generators/manual_move_generator.h @@ -1,3 +1,4 @@ +#pragma once /* * @file manual_move_generator.h * @author Paula Perdomo @@ -5,8 +6,6 @@ * @brief Contains the ManualMoveGenerator class. */ -#pragma once - #include "move_generator.h" class PlaceMacros; diff --git a/vpr/src/place/move_transactions.h b/vpr/src/place/move_transactions.h index 78cde262e54..831461a9c54 100644 --- a/vpr/src/place/move_transactions.h +++ b/vpr/src/place/move_transactions.h @@ -1,5 +1,4 @@ -#ifndef VPR_MOVE_TRANSACTIONS_H -#define VPR_MOVE_TRANSACTIONS_H +#pragma once #include "vpr_types.h" @@ -94,5 +93,3 @@ struct t_pl_blocks_to_be_moved { MoveAbortionLogger move_abortion_logger; }; - -#endif diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 88dd5505777..424642463f8 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -16,6 +16,24 @@ //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING bool f_placer_breakpoint_reached = false; +/** + * @brief Adjust the search range based on how many blocks are in the column. + * If the number of blocks in the column is less than MIN_NUM_BLOCKS_IN_COLUMN, + * expand the search range to cover the entire column. + * + * @param block_type The type of the block to move + * @param compressed_column_num The compressed column to move the block to + * @param to_layer_num The layer that the block is moving to + * @param is_range_fixed Whether the search range is fixed (e.g., in case of placement constraints) + * @param search_range The search range to adjust + * + */ +static void adjust_search_range(t_logical_block_type_ptr block_type, + const int compressed_column_num, + const int to_layer_num, + const bool is_range_fixed, + t_bb& search_range); + //Accessor for f_placer_breakpoint_reached bool placer_breakpoint_reached() { return f_placer_breakpoint_reached; @@ -666,10 +684,9 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, rlim); int delta_cx = search_range.xmax - search_range.xmin; - t_physical_tile_loc to_compressed_loc; - bool legal = false; + bool block_constrained = is_cluster_constrained(b_from); - if (is_cluster_constrained(b_from)) { + if (block_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -678,6 +695,9 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, return false; } } + + t_physical_tile_loc to_compressed_loc; + bool legal = false; //TODO: For now, we only move the blocks on the same tile legal = find_compatible_compressed_loc_in_range(type, delta_cx, @@ -688,7 +708,8 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + block_constrained); if (!legal) { //No valid position found @@ -758,10 +779,9 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, to_layer_num); - t_physical_tile_loc to_compressed_loc; - bool legal = false; + bool block_constrained = is_cluster_constrained(b_from); - if (is_cluster_constrained(b_from)) { + if (block_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -771,6 +791,8 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, } } + t_physical_tile_loc to_compressed_loc; + bool legal = false; legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, from_compressed_locs[to_layer_num], @@ -780,7 +802,8 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + block_constrained); if (!legal) { //No valid position found @@ -847,10 +870,9 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } delta_cx = search_range.xmax - search_range.xmin; - t_physical_tile_loc to_compressed_loc; - bool legal = false; + bool block_constrained = is_cluster_constrained(b_from); - if (is_cluster_constrained(b_from)) { + if (block_constrained) { bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, search_range, delta_cx, @@ -860,7 +882,10 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } } - //TODO: For now, we only move the blocks on the same tile + t_physical_tile_loc to_compressed_loc; + bool legal = false; + + //TODO: For now, we only move the blocks on the same layer legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, from_compressed_loc[to_layer_num], @@ -870,7 +895,8 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, to_layer_num, /*search_for_empty=*/false, blk_loc_registry, - rng); + rng, + block_constrained); if (!legal) { //No valid position found @@ -964,7 +990,8 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int to_layer_num, bool search_for_empty, const BlkLocRegistry& blk_loc_registry, - vtr::RngContainer& rng) { + vtr::RngContainer& rng, + const bool is_range_fixed) { //TODO For the time being, the blocks only moved in the same layer. This assertion should be removed after VPR is updated to move blocks between layers VTR_ASSERT(to_layer_num == from_loc.layer_num); const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[type->index]; @@ -999,28 +1026,17 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, //The candidates are stored in a flat_map so we can efficiently find the set of valid //candidates with upper/lower bound. const auto& block_rows = compressed_block_grid.get_column_block_map(to_loc.x, to_layer_num); + adjust_search_range(type, + to_loc.x, + to_layer_num, + is_range_fixed, + search_range); auto y_lower_iter = block_rows.lower_bound(search_range.ymin); if (y_lower_iter == block_rows.end()) { continue; } - auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (y_lower_iter->first > search_range.ymin) { - //No valid blocks at this x location which are within rlim_y - // - if (type->index != 1) - continue; - else { - //Fall back to allow the whole y range - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); - - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; - } - } - int y_range = std::distance(y_lower_iter, y_upper_iter); VTR_ASSERT(y_range >= 0); @@ -1199,6 +1215,25 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, return true; } +static void adjust_search_range(t_logical_block_type_ptr block_type, + const int compressed_column_num, + const int to_layer_num, + const bool is_range_fixed, + t_bb& search_range) { + // The value is chosen empirically to expand the search range for sparse blocks, + // or blocks located on the perimeter of the FPGA (e.g., IO blocks) + constexpr int MIN_NUM_BLOCKS_IN_COLUMN = 3; + + const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; + + size_t num_blocks_in_column = compressed_block_grid.get_column_block_map(compressed_column_num, to_layer_num).size(); + + if (num_blocks_in_column < MIN_NUM_BLOCKS_IN_COLUMN && !is_range_fixed) { + search_range.ymin = 0; + search_range.ymax = compressed_block_grid.get_num_rows(to_layer_num) - 1; + } +} + std::string e_move_result_to_string(e_move_result move_outcome) { switch (move_outcome) { case e_move_result::REJECTED: diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index 5552c36e8e9..77abcef74c6 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -1,4 +1,3 @@ - #pragma once #include "vpr_types.h" @@ -328,6 +327,7 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, * is_median: true if this is called from find_to_loc_median * to_layer_num: the layer number of the new location (set by the caller) * search_for_empty: indicates that the returned location must be empty + * is_range_fixed: indicates that the search range is fixed and should not be adjusted */ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int delta_cx, @@ -338,7 +338,8 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int to_layer_num, bool search_for_empty, const BlkLocRegistry& blk_loc_registry, - vtr::RngContainer& rng); + vtr::RngContainer& rng, + const bool is_range_fixed); /** * @brief Get the the compressed loc from the uncompressed loc (grid_loc) diff --git a/vpr/src/place/net_cost_handler.h b/vpr/src/place/net_cost_handler.h index ee60d5ed348..7681b93f6ad 100644 --- a/vpr/src/place/net_cost_handler.h +++ b/vpr/src/place/net_cost_handler.h @@ -1,11 +1,10 @@ +#pragma once /** * @file net_cost_handler.h * @brief This file contains the declaration of NetCostHandler class used to update placement cost when a new move is proposed/committed. * For more details on the overall algorithm, refer to the comment at the top of the net_cost_handler.cpp */ -#pragma once - #include "place_delay_model.h" #include "move_transactions.h" #include "place_util.h" diff --git a/vpr/src/place/noc_place_checkpoint.cpp b/vpr/src/place/noc_place_checkpoint.cpp index 0cb0f0134c1..f479d46c486 100644 --- a/vpr/src/place/noc_place_checkpoint.cpp +++ b/vpr/src/place/noc_place_checkpoint.cpp @@ -45,7 +45,6 @@ void NoCPlacementCheckpoint::restore_checkpoint(t_placer_costs& costs, for (const NocRouter& phy_router : noc_phy_routers) { t_physical_tile_loc phy_loc = phy_router.get_router_physical_location(); - grid_blocks.set_usage(phy_loc, 0); auto tile = device_ctx.grid.get_physical_type(phy_loc); for (const auto& sub_tile : tile->sub_tiles) { diff --git a/vpr/src/place/noc_place_checkpoint.h b/vpr/src/place/noc_place_checkpoint.h index 963acee281c..59db6a70e20 100644 --- a/vpr/src/place/noc_place_checkpoint.h +++ b/vpr/src/place/noc_place_checkpoint.h @@ -1,5 +1,4 @@ -#ifndef VTR_ROUTERPLACEMENTCHECKPOINT_H -#define VTR_ROUTERPLACEMENTCHECKPOINT_H +#pragma once /** * @brief NoC router placement checkpoint @@ -73,5 +72,3 @@ class NoCPlacementCheckpoint { bool valid_ = false; double cost_; }; - -#endif //VTR_ROUTERPLACEMENTCHECKPOINT_H diff --git a/vpr/src/place/noc_place_utils.h b/vpr/src/place/noc_place_utils.h index a71963b8f10..db5e26f9cfe 100644 --- a/vpr/src/place/noc_place_utils.h +++ b/vpr/src/place/noc_place_utils.h @@ -1,5 +1,4 @@ -#ifndef NOC_PLACE_UTILS_H -#define NOC_PLACE_UTILS_H +#pragma once #include #include "move_utils.h" @@ -704,5 +703,3 @@ bool noc_routing_has_cycle(const vtr::vector& pin_timing_invalidator, PlaceCritParams crit_params, std::optional& noc_cost_handler); -#endif diff --git a/vpr/src/place/place_constraints.h b/vpr/src/place/place_constraints.h index b1d2b5a556f..e8ba399ce05 100644 --- a/vpr/src/place/place_constraints.h +++ b/vpr/src/place/place_constraints.h @@ -1,5 +1,4 @@ -#ifndef VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ -#define VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ +#pragma once /* * place_constraints.h @@ -201,5 +200,3 @@ double get_floorplan_score(ClusterBlockId blk_id, const PartitionRegion& pr, t_logical_block_type_ptr block_type, const GridTileLookup& grid_tiles); - -#endif /* VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ */ diff --git a/vpr/src/place/place_macro.h b/vpr/src/place/place_macro.h index 188fbbdab46..d3eacc2e6f0 100644 --- a/vpr/src/place/place_macro.h +++ b/vpr/src/place/place_macro.h @@ -1,3 +1,4 @@ +#pragma once /**************************************************************************************** * Y.G.THIEN * 29 AUG 2012 @@ -116,9 +117,6 @@ * ****************************************************************************************/ -#ifndef PLACE_MACRO_H -#define PLACE_MACRO_H - #include #include "clustered_netlist_fwd.h" @@ -263,5 +261,3 @@ class PlaceMacros { void alloc_and_load_idirect_from_blk_pin_(const std::vector& directs, const std::vector& physical_tile_types); }; - -#endif diff --git a/vpr/src/place/place_util.h b/vpr/src/place/place_util.h index f21761b9e31..f9925cbcc76 100644 --- a/vpr/src/place/place_util.h +++ b/vpr/src/place/place_util.h @@ -1,12 +1,10 @@ +#pragma once /** * @file place_util.h * @brief Utility structures representing various states of the * placement and utility functions used by the placer. */ -#ifndef PLACE_UTIL_H -#define PLACE_UTIL_H - #include "vpr_types.h" #include "globals.h" @@ -265,4 +263,3 @@ bool macro_can_be_placed(const t_pl_macro& pl_macro, const t_pl_loc& head_pos, bool check_all_legality, const BlkLocRegistry& blk_loc_registry); -#endif diff --git a/vpr/src/place/placement_log_printer.cpp b/vpr/src/place/placement_log_printer.cpp index f4fccecbcc1..6bf49f63f48 100644 --- a/vpr/src/place/placement_log_printer.cpp +++ b/vpr/src/place/placement_log_printer.cpp @@ -1,7 +1,9 @@ #include "placement_log_printer.h" +#include "echo_files.h" #include "place_macro.h" +#include "timing_util.h" #include "vtr_log.h" #include "annealer.h" #include "place_util.h" diff --git a/vpr/src/place/placement_log_printer.h b/vpr/src/place/placement_log_printer.h index 56d18835078..4b7d201fc77 100644 --- a/vpr/src/place/placement_log_printer.h +++ b/vpr/src/place/placement_log_printer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file placement_log_printer.h * @brief Declares the PlacementLogPrinter class and associated utilities for logging @@ -8,8 +9,6 @@ * the placement process for debugging, optimization, and analysis purposes. */ -#pragma once - #include #include "timing_info_fwd.h" diff --git a/vpr/src/place/placer.cpp b/vpr/src/place/placer.cpp index b2ea7078e95..43018b7c904 100644 --- a/vpr/src/place/placer.cpp +++ b/vpr/src/place/placer.cpp @@ -5,6 +5,7 @@ #include #include +#include "echo_files.h" #include "flat_placement_types.h" #include "blk_loc_registry.h" #include "place_macro.h" @@ -21,6 +22,10 @@ #include "place_checkpoint.h" #include "tatum/echo_writer.hpp" +#ifndef NO_GRAPHICS +#include "draw_global.h" +#endif // NO_GRAPHICS + Placer::Placer(const Netlist<>& net_list, std::optional> init_place, const t_placer_opts& placer_opts, diff --git a/vpr/src/place/placer.h b/vpr/src/place/placer.h index 61a8301818c..02ffd5478a6 100644 --- a/vpr/src/place/placer.h +++ b/vpr/src/place/placer.h @@ -1,3 +1,4 @@ +#pragma once /** * @file placer.h * @brief Declares the Placer class, which encapsulates the functionality, data structures, @@ -15,8 +16,6 @@ * - Includes debugging and validation utilities to verify the correctness of placement. */ -#pragma once - #include #include #include @@ -31,6 +30,7 @@ #include "PlacerSetupSlacks.h" #include "PlacerCriticalities.h" #include "NetPinTimingInvalidator.h" +#include "vtr_random.h" class BlkLocRegistry; class FlatPlacementInfo; diff --git a/vpr/src/place/placer_breakpoint.h b/vpr/src/place/placer_breakpoint.h index d23e927ae7f..100440f1183 100644 --- a/vpr/src/place/placer_breakpoint.h +++ b/vpr/src/place/placer_breakpoint.h @@ -1,4 +1,3 @@ - #pragma once #include "move_utils.h" diff --git a/vpr/src/place/placer_state.h b/vpr/src/place/placer_state.h index 10592ebcfca..b633d4c17e3 100644 --- a/vpr/src/place/placer_state.h +++ b/vpr/src/place/placer_state.h @@ -1,3 +1,4 @@ +#pragma once /** * @file placer_state.h * @brief Contains placer state/data structures referenced by various source files in vpr/src/place. @@ -8,7 +9,6 @@ * the end of the placement stage. */ -#pragma once #include "vpr_context.h" #include "vpr_net_pins_matrix.h" #include "vpr_types.h" diff --git a/vpr/src/place/timing/PlacerCriticalities.h b/vpr/src/place/timing/PlacerCriticalities.h index 5ad0ef80735..80c68a01d3e 100644 --- a/vpr/src/place/timing/PlacerCriticalities.h +++ b/vpr/src/place/timing/PlacerCriticalities.h @@ -1,4 +1,3 @@ - #pragma once #include "vtr_vec_id_set.h" diff --git a/vpr/src/place/timing/PlacerSetupSlacks.h b/vpr/src/place/timing/PlacerSetupSlacks.h index 521d83809ca..800091e9bd1 100644 --- a/vpr/src/place/timing/PlacerSetupSlacks.h +++ b/vpr/src/place/timing/PlacerSetupSlacks.h @@ -1,10 +1,8 @@ - #pragma once #include "vtr_vec_id_set.h" #include "timing_info_fwd.h" #include "clustered_netlist_utils.h" -#include "place_delay_model.h" #include "vpr_net_pins_matrix.h" /** diff --git a/vpr/src/place/timing/PlacerTimingCosts.h b/vpr/src/place/timing/PlacerTimingCosts.h index 5e1415581c3..ccdf10f848c 100644 --- a/vpr/src/place/timing/PlacerTimingCosts.h +++ b/vpr/src/place/timing/PlacerTimingCosts.h @@ -1,11 +1,4 @@ - #pragma once -#include "vtr_vec_id_set.h" -#include "timing_info_fwd.h" -#include "clustered_netlist_utils.h" -#include "place_delay_model.h" -#include "vpr_net_pins_matrix.h" - /** * @brief PlacerTimingCosts mimics a 2D array of connection timing costs running from: * [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1]. @@ -73,6 +66,9 @@ * PlacerTimingCosts's invalidate() method marks the cost element's ancestors as invalid (NaN) * so they will be re-calculated by PlacerTimingCosts' total_cost() method. */ + +#include "clustered_netlist.h" + class PlacerTimingCosts { public: PlacerTimingCosts() = default; diff --git a/vpr/src/place/timing/place_timing_update.h b/vpr/src/place/timing/place_timing_update.h index 8e7a0dc1f46..3f9084cf846 100644 --- a/vpr/src/place/timing/place_timing_update.h +++ b/vpr/src/place/timing/place_timing_update.h @@ -1,18 +1,17 @@ +#pragma once /** * @file place_timing_update.h * @brief Timing update routines used by the VPR placer. */ -#pragma once - class PlacerState; -class PlaceCritParams; +struct PlaceCritParams; class PlacerCriticalities; class PlacerSetupSlacks; class NetPinTimingInvalidator; class PlaceDelayModel; class SetupTimingInfo; -struct t_placer_costs; +class t_placer_costs; ///@brief Initialize the timing information and structures in the placer. void initialize_timing_info(const PlaceCritParams& crit_params, diff --git a/vpr/src/place/verify_placement.h b/vpr/src/place/verify_placement.h index 2a3236d3b4c..75b2c3f3af6 100644 --- a/vpr/src/place/verify_placement.h +++ b/vpr/src/place/verify_placement.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -12,8 +13,6 @@ * makes sense that they are in their own file. */ -#pragma once - #include "vtr_vector.h" // Forward declarations diff --git a/vpr/src/power/PowerSpicedComponent.h b/vpr/src/power/PowerSpicedComponent.h index 57b43c309a1..2100ee6896d 100644 --- a/vpr/src/power/PowerSpicedComponent.h +++ b/vpr/src/power/PowerSpicedComponent.h @@ -1,3 +1,4 @@ +#pragma once /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -15,9 +16,6 @@ * ********************************************************************/ -#ifndef __POWER_POWERSPICEDCOMPONENT_NMOS_H__ -#define __POWER_POWERSPICEDCOMPONENT_NMOS_H__ - #include #include @@ -85,5 +83,3 @@ class PowerSpicedComponent { bool is_done_callibration(); void print(FILE* fp); }; - -#endif diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 92e24020675..e210e4dea04 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -81,7 +81,7 @@ static void power_usage_local_buffers_and_wires(t_power_usage* power_usage, /* Clock */ static void power_usage_clock(t_power_usage* power_usage, - t_clock_arch* clock_arch); + std::vector& clock_arch); static void power_usage_clock_single(t_power_usage* power_usage, t_clock_network* clock_inf); @@ -192,8 +192,8 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra Q_dens = pin_dens(pb, Q_pin, iblk); Q_prob = pin_prob(pb, Q_pin, iblk); - clk_prob = device_ctx.clock_arch->clock_inf[0].prob; - clk_dens = device_ctx.clock_arch->clock_inf[0].dens; + clk_prob = (*device_ctx.clock_arch)[0].prob; + clk_dens = (*device_ctx.clock_arch)[0].dens; power_usage_ff(&sub_power_usage, power_ctx.arch->FF_size, D_prob, D_dens, Q_prob, Q_dens, clk_prob, clk_dens, power_ctx.solution_inf.T_crit); @@ -645,8 +645,7 @@ static void power_usage_blocks(t_power_usage* power_usage) { * Calculates the total power usage from the clock network */ static void power_usage_clock(t_power_usage* power_usage, - t_clock_arch* clock_arch) { - int clock_idx; + std::vector& clock_arch) { auto& power_ctx = g_vpr_ctx.power(); /* Initialization */ @@ -654,27 +653,25 @@ static void power_usage_clock(t_power_usage* power_usage, power_usage->leakage = 0.; /* if no global clock, then return */ - if (clock_arch->num_global_clocks == 0) { + if (clock_arch.empty()) { return; } - for (clock_idx = 0; clock_idx < clock_arch->num_global_clocks; - clock_idx++) { + for (auto& clock : clock_arch) { t_power_usage clock_power; /* Assume the global clock is active even for combinational circuits */ - if (clock_arch->num_global_clocks == 1) { - if (clock_arch->clock_inf[clock_idx].dens == 0) { - clock_arch->clock_inf[clock_idx].dens = 2; - clock_arch->clock_inf[clock_idx].prob = 0.5; + if (clock_arch.size() == 1) { + if (clock.dens == 0) { + clock.dens = 2; + clock.prob = 0.5; // This will need to change for multi-clock - clock_arch->clock_inf[clock_idx].period = power_ctx.solution_inf.T_crit; + clock.period = power_ctx.solution_inf.T_crit; } } /* find the power dissipated by each clock network */ - power_usage_clock_single(&clock_power, - &clock_arch->clock_inf[clock_idx]); + power_usage_clock_single(&clock_power, &clock); power_add_usage(power_usage, &clock_power); } @@ -1737,7 +1734,7 @@ e_power_ret_code power_total(float* run_time_s, const t_vpr_setup& vpr_setup, co power_component_add_usage(&sub_power_usage, POWER_COMPONENT_ROUTING); /* Clock */ - power_usage_clock(&sub_power_usage, arch->clocks); + power_usage_clock(&sub_power_usage, *arch->clocks); power_add_usage(&total_power, &sub_power_usage); power_component_add_usage(&sub_power_usage, POWER_COMPONENT_CLOCK); diff --git a/vpr/src/power/power.h b/vpr/src/power/power.h index 36630921b03..9183bcb0b2b 100644 --- a/vpr/src/power/power.h +++ b/vpr/src/power/power.h @@ -1,5 +1,4 @@ #pragma once - /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -22,8 +21,6 @@ */ /************************* INCLUDES *********************************/ -#include - #include "vpr_types.h" #include "PowerSpicedComponent.h" diff --git a/vpr/src/power/power_callibrate.cpp b/vpr/src/power/power_callibrate.cpp index d4576dd04d2..2d14f467d03 100644 --- a/vpr/src/power/power_callibrate.cpp +++ b/vpr/src/power/power_callibrate.cpp @@ -20,16 +20,11 @@ */ /************************* INCLUDES *********************************/ -#include - #include "vtr_assert.h" -#include "vtr_memory.h" #include "power_callibrate.h" #include "power_components.h" -#include "power_lowlevel.h" #include "power_util.h" -#include "power_cmos_tech.h" #include "globals.h" /************************* FUNCTION DECLARATIONS ********************/ diff --git a/vpr/src/power/power_callibrate.h b/vpr/src/power/power_callibrate.h index 48852da4ea9..2aee2b717d3 100644 --- a/vpr/src/power/power_callibrate.h +++ b/vpr/src/power/power_callibrate.h @@ -1,3 +1,4 @@ +#pragma once /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -19,11 +20,6 @@ * againt SPICE. */ -#pragma once - -/************************* INCLUDES *********************************/ -#include "power.h" - /************************* DEFINES **********************************/ const float power_callib_period = 5e-9; diff --git a/vpr/src/power/power_cmos_tech.cpp b/vpr/src/power/power_cmos_tech.cpp index 6d8b38ac32e..e8cbb8ec0f9 100644 --- a/vpr/src/power/power_cmos_tech.cpp +++ b/vpr/src/power/power_cmos_tech.cpp @@ -29,17 +29,12 @@ #include "pugixml.hpp" #include "pugixml_util.hpp" -#include "vtr_util.h" -#include "vtr_memory.h" -#include "vtr_math.h" - #include "vpr_error.h" #include "globals.h" #include "power_cmos_tech.h" #include "power.h" #include "power_util.h" -#include "read_xml_util.h" #include "PowerSpicedComponent.h" #include "power_callibrate.h" diff --git a/vpr/src/power/power_cmos_tech.h b/vpr/src/power/power_cmos_tech.h index 799a798c9b3..7edca2b98be 100644 --- a/vpr/src/power/power_cmos_tech.h +++ b/vpr/src/power/power_cmos_tech.h @@ -1,3 +1,4 @@ +#pragma once /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -22,9 +23,6 @@ * these data structures. */ -#ifndef __POWER_CMOS_TECH_H__ -#define __POWER_CMOS_TECH_H__ - /************************* INCLUDES *********************************/ #include "power.h" @@ -50,4 +48,3 @@ void power_find_buffer_sc_levr(t_power_buffer_sc_levr_inf** lower, t_power_buffer_sc_levr_inf** upper, t_power_buffer_strength_inf* buffer_sc, int input_mux_size); -#endif diff --git a/vpr/src/power/power_components.cpp b/vpr/src/power/power_components.cpp index 0a6b22e0786..38e99fae6f7 100644 --- a/vpr/src/power/power_components.cpp +++ b/vpr/src/power/power_components.cpp @@ -27,7 +27,6 @@ #include "vtr_math.h" #include "vtr_assert.h" -#include "vtr_memory.h" #include "power_components.h" #include "power_lowlevel.h" diff --git a/vpr/src/power/power_components.h b/vpr/src/power/power_components.h index 3faa7b7b641..9e467f88c28 100644 --- a/vpr/src/power/power_components.h +++ b/vpr/src/power/power_components.h @@ -1,3 +1,4 @@ +#pragma once /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -20,13 +21,9 @@ * within the FPGA (flip-flops, LUTs, interconnect structures, etc). */ -#ifndef __POWER_COMPONENTS_H__ -#define __POWER_COMPONENTS_H__ - /************************* INCLUDES *********************************/ #include #include "power.h" -#include "clustered_netlist.h" /************************* Defines **********************************/ @@ -93,5 +90,3 @@ void power_usage_mux_multilevel(t_power_usage* power_usage, bool output_level_restored, float period); void power_usage_buffer(t_power_usage* power_usage, float size, float in_prob, float in_dens, bool level_restored, float period); - -#endif diff --git a/vpr/src/power/power_lowlevel.h b/vpr/src/power/power_lowlevel.h index 6a128b45453..5a165cfd448 100644 --- a/vpr/src/power/power_lowlevel.h +++ b/vpr/src/power/power_lowlevel.h @@ -1,3 +1,4 @@ +#pragma once /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -20,11 +21,9 @@ * components (inverters, simple multiplexers, etc) */ -#ifndef __POWER_LOW_LEVEL_H__ -#define __POWER_LOW_LEVEL_H__ - /************************* INCLUDES *********************************/ -#include "power.h" +#include "physical_types.h" +#include "vpr_types.h" /************************* GLOBALS **********************************/ @@ -89,5 +88,3 @@ float power_calc_mux_v_out(int num_inputs, float transistor_size, float v_in, fl float power_calc_node_switching(float capacitance, float density, float period); float power_calc_buffer_size_from_Cout(float C_out); - -#endif diff --git a/vpr/src/power/power_sizing.cpp b/vpr/src/power/power_sizing.cpp index 37f06028dc3..b00a9bc419e 100644 --- a/vpr/src/power/power_sizing.cpp +++ b/vpr/src/power/power_sizing.cpp @@ -28,13 +28,13 @@ #include "logic_types.h" #include "vtr_util.h" #include "vtr_assert.h" -#include "vtr_memory.h" #include "power_sizing.h" #include "power.h" #include "globals.h" #include "power_util.h" #include "vpr_utils.h" + /************************ FILE SCOPE *********************************/ static double f_MTA_area; diff --git a/vpr/src/power/power_sizing.h b/vpr/src/power/power_sizing.h index c6ad3ee4f10..e914e99345b 100644 --- a/vpr/src/power/power_sizing.h +++ b/vpr/src/power/power_sizing.h @@ -1,3 +1,4 @@ +#pragma once /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -20,12 +21,6 @@ * FPGA, for physical size estimations */ -#ifndef __POWER_TRANSISTOR_CNT_H__ -#define __POWER_TRANSISTOR_CNT_H__ - -/************************* INCLUDES *********************************/ -#include "physical_types.h" - /************************* DEFINES **********************************/ /* Design rules, values in LAMBDA, where tech size = 2 LAMBDA */ @@ -42,4 +37,3 @@ void power_sizing_init(); double power_count_transistors_buffer(float buffer_size); double power_transistor_area(double num_transistors); -#endif diff --git a/vpr/src/power/power_util.cpp b/vpr/src/power/power_util.cpp index 52556dac0aa..24c35f580f8 100644 --- a/vpr/src/power/power_util.cpp +++ b/vpr/src/power/power_util.cpp @@ -26,7 +26,6 @@ #include #include "vtr_assert.h" -#include "vtr_memory.h" #include "power_util.h" #include "globals.h" diff --git a/vpr/src/power/power_util.h b/vpr/src/power/power_util.h index 7589af621ad..c936f322065 100644 --- a/vpr/src/power/power_util.h +++ b/vpr/src/power/power_util.h @@ -1,3 +1,4 @@ +#pragma once /********************************************************************* * The following code is part of the power modelling feature of VTR. * @@ -19,15 +20,10 @@ * This file provides utility functions used by power estimation. */ -#ifndef __POWER_UTIL_H__ -#define __POWER_UTIL_H__ - /************************* INCLUDES *********************************/ #include #include "power.h" -#include "power_components.h" #include "atom_netlist.h" -#include "clustered_netlist.h" /************************* FUNCTION DECLARATIONS ********************/ @@ -75,5 +71,3 @@ void output_log(t_log* log_ptr, FILE* fp); void output_logs(FILE* fp, t_log* logs, int num_logs); void power_print_title(FILE* fp, const char* title); - -#endif diff --git a/vpr/src/route/ParallelNetlistRouter.h b/vpr/src/route/ParallelNetlistRouter.h index 68b240321b2..5e0be62fc57 100644 --- a/vpr/src/route/ParallelNetlistRouter.h +++ b/vpr/src/route/ParallelNetlistRouter.h @@ -1,5 +1,4 @@ #pragma once - /** @file Parallel case for NetlistRouter. Builds a \ref PartitionTree from the * netlist according to net bounding boxes. Tree nodes are then routed in parallel * using tbb::task_group. Each task routes the nets inside a node serially and then adds @@ -9,6 +8,7 @@ * Note that the parallel router does not support graphical router breakpoints. * * [0]: "Parallel FPGA Routing with On-the-Fly Net Decomposition", FPT'24 */ + #include "netlist_routers.h" #include "vtr_optional.h" diff --git a/vpr/src/route/annotate_routing.h b/vpr/src/route/annotate_routing.h index b4026562175..78d1aad0c6f 100644 --- a/vpr/src/route/annotate_routing.h +++ b/vpr/src/route/annotate_routing.h @@ -1,5 +1,4 @@ -#ifndef ANNOTATE_ROUTING_H -#define ANNOTATE_ROUTING_H +#pragma once #include "clustered_netlist_fwd.h" #include "rr_graph_fwd.h" @@ -20,5 +19,3 @@ vtr::vector annotate_rr_node_nets(const ClusteringContex const DeviceContext& device_ctx, const AtomContext& atom_ctx, const bool& verbose); - -#endif diff --git a/vpr/src/route/channel_stats.h b/vpr/src/route/channel_stats.h index a087fba31f0..7b17a0c0fa3 100644 --- a/vpr/src/route/channel_stats.h +++ b/vpr/src/route/channel_stats.h @@ -1,6 +1,3 @@ -#ifndef VPR_CHANNEL_STATS_H -#define VPR_CHANNEL_STATS_H +#pragma once void print_channel_stats(bool is_flat); - -#endif diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index ac553aae092..8527f290196 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -1,6 +1,7 @@ #include "check_route.h" +#include "describe_rr_node.h" #include "physical_types_util.h" #include "route_common.h" #include "vpr_utils.h" diff --git a/vpr/src/route/check_route.h b/vpr/src/route/check_route.h index 609a2fcb8d4..0baff0394b5 100644 --- a/vpr/src/route/check_route.h +++ b/vpr/src/route/check_route.h @@ -1,5 +1,4 @@ -#ifndef VPR_CHECK_ROUTE_H -#define VPR_CHECK_ROUTE_H +#pragma once #include "netlist.h" #include "vpr_types.h" @@ -10,5 +9,3 @@ void check_route(const Netlist<>& net_list, bool is_flat); void recompute_occupancy_from_scratch(const Netlist<>& net_list, bool is_flat); - -#endif diff --git a/vpr/src/route/connection_based_routing.cpp b/vpr/src/route/connection_based_routing.cpp index a8f3d1b0a86..06f55a4fef1 100644 --- a/vpr/src/route/connection_based_routing.cpp +++ b/vpr/src/route/connection_based_routing.cpp @@ -1,6 +1,7 @@ #include "connection_based_routing.h" #include "route_profiling.h" +#include "timing_util.h" // incremental rerouting resources class definitions Connection_based_routing_resources::Connection_based_routing_resources(const Netlist<>& net_list, diff --git a/vpr/src/route/connection_based_routing.h b/vpr/src/route/connection_based_routing.h index 2b7915bf6d5..ac8068113b3 100644 --- a/vpr/src/route/connection_based_routing.h +++ b/vpr/src/route/connection_based_routing.h @@ -2,6 +2,7 @@ #include #include +#include "clustered_netlist_utils.h" #include "timing_info.h" #include "vpr_net_pins_matrix.h" #include "connection_based_routing_fwd.h" diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h index ad888834896..66928d343ed 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/connection_router.h @@ -1,5 +1,23 @@ -#ifndef _CONNECTION_ROUTER_H -#define _CONNECTION_ROUTER_H +#pragma once +/** + * @file + * @brief This file defines the ConnectionRouter class. + * + * Overview + * ======== + * The ConnectionRouter represents the timing-driven connection routers, which + * route from some initial set of sources (via the input rt tree) to a particular + * sink. VPR supports two timing-driven connection routers, including the serial + * connection router and the MultiQueue-based parallel connection router. This + * class defines the interface for the two connection routers and encapsulates + * the common member variables and helper functions for them. + * + * @note + * When the ConnectionRouter is used, it mutates the provided rr_node_route_inf. + * The routed path can be found by tracing from the sink node (which is returned) + * through the rr_node_route_inf. See update_traceback as an example of this tracing. + * + */ /** * @file @@ -23,6 +41,7 @@ #include "connection_router_interface.h" #include "globals.h" +#include "route_path_manager.h" #include "rr_graph_storage.h" #include "router_lookahead.h" #include "route_tree.h" @@ -356,5 +375,3 @@ class ConnectionRouter : public ConnectionRouterInterface { }; #include "connection_router.tpp" - -#endif /* _CONNECTION_ROUTER_H */ diff --git a/vpr/src/route/connection_router_interface.h b/vpr/src/route/connection_router_interface.h index c5b63e57fbf..83c11479216 100644 --- a/vpr/src/route/connection_router_interface.h +++ b/vpr/src/route/connection_router_interface.h @@ -1,5 +1,4 @@ -#ifndef _CONNECTION_ROUTER_INTERFACE_H -#define _CONNECTION_ROUTER_INTERFACE_H +#pragma once #include "route_tree_fwd.h" #include "rr_graph_fwd.h" @@ -112,5 +111,3 @@ class ConnectionRouterInterface { // Ensure route budgets have been calculated before enabling this virtual void set_rcv_enabled(bool enable) = 0; }; - -#endif /* _CONNECTION_ROUTER_INTERFACE_H */ diff --git a/vpr/src/route/d_ary_heap.h b/vpr/src/route/d_ary_heap.h index ed10b0157bd..4d44a469f44 100644 --- a/vpr/src/route/d_ary_heap.h +++ b/vpr/src/route/d_ary_heap.h @@ -1,5 +1,4 @@ -#ifndef _VTR_D_ARY_HEAP_H -#define _VTR_D_ARY_HEAP_H +#pragma once #include @@ -72,5 +71,3 @@ class DAryHeap : public HeapInterface { using BinaryHeap = DAryHeap<2>; using FourAryHeap = DAryHeap<4>; - -#endif /* _VTR_D_ARY_HEAP_H */ diff --git a/vpr/src/route/edge_groups.h b/vpr/src/route/edge_groups.h index a5521b6d2ec..766758ecb67 100644 --- a/vpr/src/route/edge_groups.h +++ b/vpr/src/route/edge_groups.h @@ -1,5 +1,4 @@ -#ifndef EDGE_GROUPS_H -#define EDGE_GROUPS_H +#pragma once #include #include @@ -57,5 +56,3 @@ class EdgeGroups { // Order is arbitrary. std::vector> rr_non_config_node_sets_; }; - -#endif diff --git a/vpr/src/route/heap_type.h b/vpr/src/route/heap_type.h index 6330fc4c0d9..353b3b478eb 100644 --- a/vpr/src/route/heap_type.h +++ b/vpr/src/route/heap_type.h @@ -1,10 +1,8 @@ -#ifndef _HEAP_TYPE_H -#define _HEAP_TYPE_H +#pragma once #include #include "device_grid.h" #include "rr_graph_fwd.h" -#include "route_path_manager.h" using HeapNodePriority = float; using HeapNodeId = RRNodeId; @@ -117,5 +115,3 @@ enum class e_heap_type { * @brief Heap factory. */ std::unique_ptr make_heap(e_heap_type); - -#endif /* _HEAP_TYPE_H */ diff --git a/vpr/src/route/multi_queue_d_ary_heap.h b/vpr/src/route/multi_queue_d_ary_heap.h index c5f43e5aa3c..9882589b63a 100644 --- a/vpr/src/route/multi_queue_d_ary_heap.h +++ b/vpr/src/route/multi_queue_d_ary_heap.h @@ -1,3 +1,4 @@ +#pragma once /******************************************************************** * MultiQueue Implementation * @@ -17,8 +18,6 @@ * Modified: February 2025 ********************************************************************/ -#pragma once - #include "device_grid.h" #include "heap_type.h" #include "multi_queue_d_ary_heap.tpp" diff --git a/vpr/src/route/netlist_routers.h b/vpr/src/route/netlist_routers.h index d4cb0a32840..ed8f216d346 100644 --- a/vpr/src/route/netlist_routers.h +++ b/vpr/src/route/netlist_routers.h @@ -1,5 +1,4 @@ #pragma once - /** @file Interface for a netlist router. * * A NetlistRouter manages the required bits of state to complete the netlist routing process, diff --git a/vpr/src/route/parallel_connection_router.h b/vpr/src/route/parallel_connection_router.h index b6db78a0d0f..8f7db3a5b49 100644 --- a/vpr/src/route/parallel_connection_router.h +++ b/vpr/src/route/parallel_connection_router.h @@ -1,11 +1,11 @@ -#ifndef _PARALLEL_CONNECTION_ROUTER_H -#define _PARALLEL_CONNECTION_ROUTER_H +#pragma once #include "connection_router.h" #include "multi_queue_d_ary_heap.h" #include +#include #include #include #include @@ -47,7 +47,6 @@ class spin_lock_t { * condition variable to coordinate thread synchronization. */ class barrier_mutex_t { - // FIXME: Try std::barrier (since C++20) to replace this mutex barrier std::mutex mutex_; std::condition_variable cv_; size_t count_; @@ -60,17 +59,22 @@ class barrier_mutex_t { * @param num_threads Number of threads that must call wait() before * any thread is allowed to proceed */ - explicit barrier_mutex_t(size_t num_threads) + explicit inline barrier_mutex_t(size_t num_threads) : count_(num_threads) , max_count_(num_threads) {} + /** + * Initialization method goes unused by this barrier implementation. + */ + inline void init() {} + /** * @brief Blocks the calling thread until all threads have called wait() * * When the specified number of threads have called this method, all * threads are unblocked and the barrier is reset for the next use. */ - void wait() { + inline void wait() { std::unique_lock lock{mutex_}; size_t gen = generation_; if (--count_ == 0) { @@ -110,13 +114,13 @@ class barrier_spin_t { * @param num_threads Number of threads that must call wait() before * any thread is allowed to proceed */ - explicit barrier_spin_t(size_t num_threads) { num_threads_ = num_threads; } + explicit inline barrier_spin_t(size_t num_threads) { num_threads_ = num_threads; } /** * @brief Initializes the thread-local sense flag * @note Should be called by each thread before first using the barrier. */ - void init() { + inline void init() { local_sense_ = false; } @@ -127,7 +131,7 @@ class barrier_spin_t { * to arrive unblocks all waiting threads. This method avoids using locks or * condition variables, making it potentially more efficient for short waits. */ - void wait() { + inline void wait() { bool s = !local_sense_; local_sense_ = s; size_t num_arrivals = count_.fetch_add(1) + 1; @@ -141,7 +145,41 @@ class barrier_spin_t { } }; -using barrier_t = barrier_spin_t; // Using the spin-based thread barrier +/** + * @brief Thread barrier implementation using std::barrier + * + * It ensures all participating threads reach a synchronization point + * before any are allowed to proceed further. + */ +class standard_barrier_t { + /// @brief Internal barrier implementation. + std::barrier<> barrier_; + + public: + /** + * @brief Constructs a barrier for a specific number of threads + * + * @param num_threads + * Number of threads that must call wait() before any thread is allowed + * to proceed. + */ + explicit inline standard_barrier_t(size_t num_threads) + : barrier_(num_threads) {} + + /** + * Initialization method goes unused by this barrier implementation. + */ + inline void init() {} + + /** + * @brief Blocks the calling thread until all threads have called wait() + */ + inline void wait() { + barrier_.arrive_and_wait(); + } +}; + +using barrier_t = standard_barrier_t; // Using the standard thread barrier /** * @class ParallelConnectionRouter implements the MultiQueue-based parallel connection @@ -180,13 +218,29 @@ class ParallelConnectionRouter : public ConnectionRoutersub_threads_.resize(multi_queue_num_threads - 1); for (int i = 0; i < multi_queue_num_threads - 1; ++i) { this->sub_threads_[i] = std::thread(&ParallelConnectionRouter::timing_driven_find_single_shortest_path_from_heap_sub_thread_wrapper, this, i + 1 /*0: main thread*/); - this->sub_threads_[i].detach(); } } ~ParallelConnectionRouter() { this->is_router_destroying_ = true; // signal the helper threads to exit this->thread_barrier_.wait(); // wait until all threads reach the barrier + for (auto& sub_thread : this->sub_threads_) { + VTR_ASSERT(sub_thread.joinable()); + // Wait for all helper threads to terminate + // + // IMPORTANT: This must be done before the main thread destructs this object, + // otherwise, helper threads might have access to polluted data members, leading + // to undefined behavior. In some cases, due to timing issues between threads, + // for example, after both main and helper threads hit the barrier, the main + // thread completes object destruction/cleanup before helper threads can check + // `this->is_router_destroying_ == true` in `..._sub_thread_wrapper` function, + // helper threads may still see `this->is_router_destroying_` as false and fail + // to exit their thread functions. This results in helper threads remaining alive + // and accessing invalid memory addresses, leading to segfaults (please refer to + // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/3029 for + // details). + sub_thread.join(); + } VTR_LOG("Parallel Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", std::chrono::duration(this->path_search_cumulative_time).count()); @@ -438,5 +492,3 @@ std::unique_ptr make_parallel_connection_router( int multi_queue_num_threads, int multi_queue_num_queues, bool multi_queue_direct_draining); - -#endif /* _PARALLEL_CONNECTION_ROUTER_H */ diff --git a/vpr/src/route/route_budgets.h b/vpr/src/route/route_budgets.h index 4d3e1fc03c4..c119ca82162 100644 --- a/vpr/src/route/route_budgets.h +++ b/vpr/src/route/route_budgets.h @@ -1,12 +1,12 @@ +#pragma once /*Defines the route_budgets class that contains the minimum, maximum, * target, upper bound, and lower bound budgets. These information are * used by the router to optimize for hold time. */ -#ifndef ROUTE_BUDGETS_H -#define ROUTE_BUDGETS_H #include #include #include "RoutingDelayCalculator.h" +#include "clustered_netlist_utils.h" #include "timing_info.h" enum analysis_type { @@ -139,5 +139,3 @@ class route_budgets { std::map should_reroute_for_hold; std::map hold_fac; }; - -#endif /* ROUTE_BUDGETS_H */ diff --git a/vpr/src/route/route_net.cpp b/vpr/src/route/route_net.cpp index c2718fbf494..e756ee93207 100644 --- a/vpr/src/route/route_net.cpp +++ b/vpr/src/route/route_net.cpp @@ -2,6 +2,7 @@ #include "route_net.h" #include "connection_based_routing.h" +#include "timing_util.h" bool check_hold(const t_router_opts& router_opts, float worst_neg_slack) { if (router_opts.routing_budgets_algorithm != YOYO) { diff --git a/vpr/src/route/route_tree.h b/vpr/src/route/route_tree.h index 36b5dcabfac..35707022118 100644 --- a/vpr/src/route/route_tree.h +++ b/vpr/src/route/route_tree.h @@ -1,5 +1,4 @@ #pragma once - /** * @file * @brief This file defines the RouteTree and RouteTreeNode, used to keep partial or full routing @@ -86,6 +85,7 @@ #include #include "connection_based_routing_fwd.h" +#include "route_path_manager.h" #include "route_tree_fwd.h" #include "spatial_route_tree_lookup.h" #include "vtr_dynamic_bitset.h" diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index d61b6bb56c9..1c206f778bf 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -3,10 +3,6 @@ #include "route_utils.h" #include "connection_based_routing.h" -#include "draw.h" -#include "draw_debug.h" -#include "draw_global.h" -#include "draw_types.h" #include "net_delay.h" #include "netlist_fwd.h" #include "overuse_report.h" @@ -19,6 +15,21 @@ #include "route_tree.h" #include "rr_graph.h" #include "tatum/TimingReporter.hpp" +#include "stats.h" +#include "timing_util.h" + +#ifdef VPR_USE_TBB +#include +#include +#endif // VPR_USE_TBB + +#ifndef NO_GRAPHICS +#include "draw.h" +#include "draw_debug.h" +#include "draw_global.h" +#include "draw_types.h" +#include "vtr_expr_eval.h" +#endif // NO_GRAPHICS #ifdef VPR_USE_TBB #include "stats.h" @@ -666,3 +677,29 @@ void update_router_info_and_check_bp(bp_router_type type, int net_id) { } } #endif + +bool is_net_routed(ParentNetId net_id) { + const auto& route_ctx = g_vpr_ctx.routing(); + //Note: we can't use route_ctx.net_status.is_routed(atom_net_id), because net_status is filled only when route stage took place + return route_ctx.route_trees[net_id].has_value(); +} + +bool is_net_fully_absorbed(ParentNetId net_id) { + const RRGraphView& rr_graph = g_vpr_ctx.device().rr_graph; + const RoutingContext& route_ctx = g_vpr_ctx.routing(); + + bool is_absorbed = true; + + for (auto& rt_node : route_ctx.route_trees[net_id].value().all_nodes()) { + RRNodeId inode = rt_node.inode; + + e_rr_type rr_type = rr_graph.node_type(inode); + + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { + is_absorbed = false; + break; + } + } + + return is_absorbed; +} diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index 71e3dc895dd..392f764704d 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -2,6 +2,7 @@ /** @file Utility functions used in the top-level router (route.cpp). */ +#include "clustered_netlist_utils.h" #include "netlist_fwd.h" #include "router_stats.h" #include "timing_info.h" @@ -156,3 +157,29 @@ void update_draw_pres_fac(const float new_pres_fac); * Stops after the specified router iteration or net id is encountered */ void update_router_info_and_check_bp(bp_router_type type, int net_id); #endif + +/** + * @brief Checks whether a given net has been routed. + * + * This function determines if the specified net (identified by `net_id`) + * has routing information associated with it in the current routing context. + * + * @param net_id The identifier of the net to check. + * @return true if the net is routed; false otherwise. + */ +bool is_net_routed(ParentNetId net_id); + +/** + * @brief Checks whether a given net is fully absorbed within sink nodes. + * + * This function inspects the route tree of the specified net and determines + * whether it is fully absorbed into non-routing resources (i.e., it does not + * occupy any routing channels such as CHANX or CHANY). + * + * A net is considered fully absorbed if all its route tree nodes are of types + * other than CHANX or CHANY (e.g., IPIN, SINK, OPIN). + * + * @param net_id The identifier of the net to be checked. + * @return true if the net is fully absorbed (uses no routing channels); false otherwise. + */ +bool is_net_fully_absorbed(ParentNetId net_id); diff --git a/vpr/src/route/router_lookahead/router_lookahead.h b/vpr/src/route/router_lookahead/router_lookahead.h index 2a13dd55aa1..ff50ff9e9d5 100644 --- a/vpr/src/route/router_lookahead/router_lookahead.h +++ b/vpr/src/route/router_lookahead/router_lookahead.h @@ -1,5 +1,5 @@ -#ifndef VPR_ROUTER_LOOKAHEAD_H -#define VPR_ROUTER_LOOKAHEAD_H +#pragma once + #include #include "vpr_types.h" #include "vpr_error.h" @@ -188,5 +188,3 @@ class NoOpLookahead : public RouterLookahead { return -1.; } }; - -#endif diff --git a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp index e45593f68e8..337fc171618 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp @@ -4,24 +4,18 @@ #include #include -#include #include #include "router_lookahead_compressed_map.h" #include "connection_router_interface.h" +#include "describe_rr_node.h" #include "vpr_types.h" #include "vpr_error.h" #include "vpr_utils.h" #include "globals.h" #include "vtr_math.h" -#include "vtr_log.h" #include "vtr_assert.h" #include "vtr_time.h" -#include "vtr_geometry.h" -#include "router_lookahead_map.h" #include "router_lookahead_map_utils.h" -#include "rr_graph2.h" -#include "rr_graph.h" -#include "route_common.h" vtr::Matrix compressed_loc_index_map; std::unordered_map> sample_locations; diff --git a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h index a111089c826..4e3e4e4ad83 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h +++ b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.h @@ -1,12 +1,9 @@ +#pragma once // // Created by amin on 11/27/23. // -#ifndef VTR_ROUTER_LOOKAHEAD_COMPRESSED_MAP_H -#define VTR_ROUTER_LOOKAHEAD_COMPRESSED_MAP_H - #include -#include #include "vtr_ndmatrix.h" #include "router_lookahead.h" #include "router_lookahead_map_utils.h" @@ -71,5 +68,3 @@ typedef vtr::NdMatrix t_compressed_wire_cost_map; //[0..num //[0..1] entry distinguish between CHANX/CHANY start nodes respectively // The first index is the layer number that the node under consideration is on, and the forth index // is the layer number that the target node is on. - -#endif //VTR_ROUTER_LOOKAHEAD_COMPRESSED_MAP_H diff --git a/vpr/src/route/router_lookahead/router_lookahead_cost_map.h b/vpr/src/route/router_lookahead/router_lookahead_cost_map.h index 39b0fd21751..03b71eefb93 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_cost_map.h +++ b/vpr/src/route/router_lookahead/router_lookahead_cost_map.h @@ -1,5 +1,4 @@ -#ifndef ROUTER_LOOKAHEAD_COST_MAP_H_ -#define ROUTER_LOOKAHEAD_COST_MAP_H_ +#pragma once #include #include "router_lookahead_map_utils.h" @@ -119,5 +118,3 @@ class CostMap { */ void fill_holes(vtr::NdMatrix& matrix, int seg_index, int bounding_box_width, int bounding_box_height, float delay_penalty); }; - -#endif diff --git a/vpr/src/route/router_lookahead/router_lookahead_extended_map.h b/vpr/src/route/router_lookahead/router_lookahead_extended_map.h index 589ea06e6a4..6bb63e71256 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_extended_map.h +++ b/vpr/src/route/router_lookahead/router_lookahead_extended_map.h @@ -1,12 +1,10 @@ -#ifndef EXTENDED_MAP_LOOKAHEAD_H_ -#define EXTENDED_MAP_LOOKAHEAD_H_ +#pragma once #include #include "physical_types.h" #include "router_lookahead.h" #include "router_lookahead_map_utils.h" #include "router_lookahead_cost_map.h" -#include "vtr_geometry.h" // Implementation of RouterLookahead based on source segment and destination connection box types class ExtendedMapLookahead : public RouterLookahead { @@ -108,5 +106,3 @@ class ExtendedMapLookahead : public RouterLookahead { return -1.; } }; - -#endif diff --git a/vpr/src/route/router_lookahead/router_lookahead_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_map.cpp index 5d8671aa468..ce60b6641db 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_map.cpp @@ -24,6 +24,7 @@ #include #include #include "connection_router_interface.h" +#include "describe_rr_node.h" #include "physical_types_util.h" #include "vpr_types.h" #include "vpr_utils.h" @@ -200,7 +201,6 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI t_physical_tile_type_ptr from_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node), rr_graph.node_layer(current_node)}); - int from_node_ptc_num = rr_graph.node_ptc_num(current_node); t_physical_tile_type_ptr to_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(target_node), rr_graph.node_ylow(target_node), @@ -318,6 +318,7 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ //cost to reach them) in src_opin_delays. Once we know what wire types are //reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final //delay to reach the sink. + t_physical_tile_type_ptr from_tile_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(from_node), rr_graph.node_ylow(from_node), from_layer_num}); diff --git a/vpr/src/route/router_lookahead/router_lookahead_map.h b/vpr/src/route/router_lookahead/router_lookahead_map.h index 29293020078..2eb4621666b 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_map.h +++ b/vpr/src/route/router_lookahead/router_lookahead_map.h @@ -1,7 +1,6 @@ #pragma once #include -#include #include "vtr_ndmatrix.h" #include "router_lookahead.h" #include "router_lookahead_map_utils.h" diff --git a/vpr/src/route/router_lookahead/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead/router_lookahead_map_utils.h index 6222a71967f..01ea3e9be35 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead/router_lookahead_map_utils.h @@ -1,5 +1,4 @@ -#ifndef ROUTER_LOOKAHEAD_MAP_UTILS_H_ -#define ROUTER_LOOKAHEAD_MAP_UTILS_H_ +#pragma once /* * The router lookahead provides an estimate of the cost from an intermediate node to the target node * during directed (A*-like) routing. @@ -20,9 +19,7 @@ #include #include #include -#include "vpr_types.h" #include "vtr_geometry.h" -#include "rr_node.h" #include "rr_graph_view.h" namespace util { @@ -362,5 +359,3 @@ std::pair get_cost_from_src_opin(const std::map& dim_sizes, WireCostCallBackFunction wire_cost_func); } // namespace util - -#endif diff --git a/vpr/src/route/router_lookahead/router_lookahead_sampling.h b/vpr/src/route/router_lookahead/router_lookahead_sampling.h index ab08ae9404d..86f4ebf9364 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_sampling.h +++ b/vpr/src/route/router_lookahead/router_lookahead_sampling.h @@ -1,9 +1,8 @@ -#ifndef ROUTER_LOOKAHEAD_SAMPLING_H -#define ROUTER_LOOKAHEAD_SAMPLING_H +#pragma once #include +#include "rr_graph_fwd.h" #include "vtr_geometry.h" -#include "globals.h" // a sample point for a segment type, contains all segments at the VPR location struct SamplePoint { @@ -31,5 +30,3 @@ struct SampleRegion { }; std::vector find_sample_regions(int num_segments); - -#endif diff --git a/vpr/src/route/routing_predictor.h b/vpr/src/route/routing_predictor.h index 13ca32be920..6da6bc6e7a6 100644 --- a/vpr/src/route/routing_predictor.h +++ b/vpr/src/route/routing_predictor.h @@ -1,5 +1,5 @@ -#ifndef VPR_ROUTING_PREDICTOR_H -#define VPR_ROUTING_PREDICTOR_H +#pragma once + #include #include @@ -35,5 +35,3 @@ class RoutingPredictor { std::vector iteration_overused_rr_node_counts_; float slope_; }; - -#endif diff --git a/vpr/src/route/rr_graph_generation/build_switchblocks.cpp b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp index b9bf8b819cc..92089dbe1dc 100644 --- a/vpr/src/route/rr_graph_generation/build_switchblocks.cpp +++ b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp @@ -127,8 +127,6 @@ #include #include -#include -#include #include "vtr_assert.h" #include "vtr_memory.h" @@ -136,6 +134,7 @@ #include "vtr_string_view.h" #include "vpr_error.h" +#include "vpr_types.h" #include "build_switchblocks.h" #include "physical_types.h" diff --git a/vpr/src/route/rr_graph_generation/build_switchblocks.h b/vpr/src/route/rr_graph_generation/build_switchblocks.h index 917bd16620b..7c75e55358d 100644 --- a/vpr/src/route/rr_graph_generation/build_switchblocks.h +++ b/vpr/src/route/rr_graph_generation/build_switchblocks.h @@ -1,12 +1,10 @@ -#ifndef BUILD_SWITCHBLOCKS_H -#define BUILD_SWITCHBLOCKS_H +#pragma once #include #include -#include #include "physical_types.h" -#include "vpr_types.h" #include "device_grid.h" +#include "rr_graph_type.h" #include "vtr_random.h" #include "rr_types.h" @@ -131,5 +129,3 @@ t_sb_connection_map* alloc_and_load_switchblock_permutations(const t_chan_detail * @param sb_conns switch block permutation map */ void free_switchblock_permutations(t_sb_connection_map* sb_conns); - -#endif diff --git a/vpr/src/route/rr_graph_generation/cb_metrics.h b/vpr/src/route/rr_graph_generation/cb_metrics.h index 4d19f84c772..de34e194050 100644 --- a/vpr/src/route/rr_graph_generation/cb_metrics.h +++ b/vpr/src/route/rr_graph_generation/cb_metrics.h @@ -1,8 +1,9 @@ -#ifndef CB_METRICS_H -#define CB_METRICS_H +#pragma once #include #include +#include "physical_types.h" +#include "rr_graph_type.h" #define MAX_OUTER_ITERATIONS 100000 #define MAX_INNER_ITERATIONS 10 @@ -99,5 +100,3 @@ void analyze_conn_blocks(const int***** opin_cb, const int***** ipin_cb, const t void make_poor_cb_pattern(const e_pin_type pin_type, const t_physical_tile_type_ptr block_type, const int* Fc_array, const t_chan_width* chan_width_inf, int***** cb); /**** END EXPERIMENTAL ****/ - -#endif /*CB_METRICS_H*/ diff --git a/vpr/src/route/rr_graph_generation/clock_connection_builders.h b/vpr/src/route/rr_graph_generation/clock_connection_builders.h index 7ab1c7c5be7..87aefe8d989 100644 --- a/vpr/src/route/rr_graph_generation/clock_connection_builders.h +++ b/vpr/src/route/rr_graph_generation/clock_connection_builders.h @@ -1,11 +1,9 @@ -#ifndef CLOCK_CONNECTION_BUILDERS_H -#define CLOCK_CONNECTION_BUILDERS_H +#pragma once #include #include "clock_fwd.h" -#include "rr_graph2.h" #include "rr_graph_clock.h" class ClockRRGraphBuilder; @@ -113,5 +111,3 @@ class ClockToPinsConnection : public ClockConnection { void create_switches(const ClockRRGraphBuilder& clock_graph, t_rr_edge_info_set* rr_edges_to_create) override; size_t estimate_additional_nodes() override; }; - -#endif diff --git a/vpr/src/route/rr_graph_generation/clock_fwd.h b/vpr/src/route/rr_graph_generation/clock_fwd.h index abf76b3b7bd..540b2aa9b3a 100644 --- a/vpr/src/route/rr_graph_generation/clock_fwd.h +++ b/vpr/src/route/rr_graph_generation/clock_fwd.h @@ -1,10 +1,7 @@ -#ifndef CLOCK_FWD -#define CLOCK_FWD +#pragma once struct Coordinates { int x = -1; int y = -1; int layer = -1; }; - -#endif diff --git a/vpr/src/route/rr_graph_generation/clock_network_builders.h b/vpr/src/route/rr_graph_generation/clock_network_builders.h index 2e73fe211c0..584ab78e579 100644 --- a/vpr/src/route/rr_graph_generation/clock_network_builders.h +++ b/vpr/src/route/rr_graph_generation/clock_network_builders.h @@ -1,16 +1,14 @@ -#ifndef CLOCK_NETWORK_BUILDERS_H -#define CLOCK_NETWORK_BUILDERS_H +#pragma once #include #include #include "clock_fwd.h" -#include "vpr_types.h" - +#include "device_grid.h" #include "rr_graph_builder.h" -#include "rr_graph2.h" #include "rr_graph_clock.h" +#include "rr_graph_type.h" class t_rr_graph_storage; class ClockRRGraphBuilder; @@ -281,5 +279,3 @@ class ClockHTree : private ClockNetwork { int num_segments_x) override; size_t estimate_additional_nodes(const DeviceGrid& grid) override; }; - -#endif diff --git a/vpr/src/route/rr_graph_generation/rr_graph.cpp b/vpr/src/route/rr_graph_generation/rr_graph.cpp index 221183161f3..8f514d182d8 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph.cpp @@ -4,6 +4,7 @@ #include #include #include "alloc_and_load_rr_indexed_data.h" +#include "get_parallel_segs.h" #include "physical_types_util.h" #include "rr_rc_data.h" #include "vtr_assert.h" diff --git a/vpr/src/route/rr_graph_generation/rr_graph.h b/vpr/src/route/rr_graph_generation/rr_graph.h index d57077c1da9..fd62da1fdfb 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph.h +++ b/vpr/src/route/rr_graph_generation/rr_graph.h @@ -1,5 +1,4 @@ -#ifndef RR_GRAPH_H -#define RR_GRAPH_H +#pragma once /* Include track buffers or not. Track buffers isolate the tracks from the * input connection block. However, they are difficult to lay out in practice, @@ -8,8 +7,8 @@ #include "device_grid.h" #include "vpr_types.h" +#include "rr_graph_builder.h" #include "rr_graph_type.h" -#include "describe_rr_node.h" #include "clb2clb_directs.h" /* Warnings about the routing graph that can be returned. @@ -90,5 +89,3 @@ bool pins_connected(t_block_loc cluster_loc, t_logical_block_type_ptr logical_block, int from_pin_logical_num, int to_pin_logical_num); - -#endif diff --git a/vpr/src/route/rr_graph_generation/rr_graph2.cpp b/vpr/src/route/rr_graph_generation/rr_graph2.cpp index 0295a8cca3d..d65482ac364 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph2.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph2.cpp @@ -9,7 +9,6 @@ #include "vpr_error.h" #include "globals.h" -#include "rr_graph_utils.h" #include "rr_graph2.h" #include "rr_graph_sbox.h" #include "rr_types.h" diff --git a/vpr/src/route/rr_graph_generation/rr_graph2.h b/vpr/src/route/rr_graph_generation/rr_graph2.h index c4b24569993..b362c120b5b 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph2.h +++ b/vpr/src/route/rr_graph_generation/rr_graph2.h @@ -5,12 +5,9 @@ #include "build_switchblocks.h" #include "rr_graph_type.h" #include "rr_graph_fwd.h" -#include "rr_graph_utils.h" -#include "rr_graph_view.h" #include "rr_graph_builder.h" #include "rr_types.h" #include "device_grid.h" -#include "get_parallel_segs.h" /******************* Subroutines exported by rr_graph2.c *********************/ diff --git a/vpr/src/route/rr_graph_generation/rr_graph_area.cpp b/vpr/src/route/rr_graph_generation/rr_graph_area.cpp index 3443038c82b..f724b6662f3 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_area.cpp @@ -1,11 +1,10 @@ #include +#include "describe_rr_node.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_math.h" -#include "vtr_memory.h" -#include "vpr_types.h" #include "vpr_error.h" #include "globals.h" diff --git a/vpr/src/route/rr_graph_generation/rr_graph_area.h b/vpr/src/route/rr_graph_generation/rr_graph_area.h index 3edf6e5c4f9..cac5c81794e 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_area.h +++ b/vpr/src/route/rr_graph_generation/rr_graph_area.h @@ -1,5 +1,7 @@ -#ifndef RR_GRAPH_AREA_H -#define RR_GRAPH_AREA_H +#pragma once + +#include +#include "physical_types.h" void count_routing_transistors(enum e_directionality directionality, int num_switch, @@ -10,5 +12,3 @@ void count_routing_transistors(enum e_directionality directionality, bool is_flat); float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos); - -#endif diff --git a/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp b/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp index 84872485f15..d06f5909449 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_clock.cpp @@ -1,16 +1,9 @@ #include "rr_graph_clock.h" #include "globals.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "rr_graph_area.h" -#include "rr_graph_utils.h" -#include "rr_graph_indexed_data.h" #include "vtr_assert.h" -#include "vtr_log.h" #include "vtr_time.h" -#include "vpr_error.h" void ClockRRGraphBuilder::create_and_append_clock_rr_graph(int num_seg_types_x, t_rr_edge_info_set* rr_edges_to_create) { diff --git a/vpr/src/route/rr_graph_generation/rr_graph_clock.h b/vpr/src/route/rr_graph_generation/rr_graph_clock.h index 6ce575b7423..9acd06a4368 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_clock.h +++ b/vpr/src/route/rr_graph_generation/rr_graph_clock.h @@ -1,5 +1,4 @@ -#ifndef RR_GRAPH_CLOCK_H -#define RR_GRAPH_CLOCK_H +#pragma once #include #include @@ -9,10 +8,10 @@ #include #include "rr_graph_builder.h" -#include "clock_fwd.h" #include "clock_network_builders.h" #include "clock_connection_builders.h" +#include "rr_graph_type.h" class ClockNetwork; class ClockConnection; @@ -156,5 +155,3 @@ class ClockRRGraphBuilder { int chanx_ptc_idx_; int chany_ptc_idx_; }; - -#endif diff --git a/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.h b/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.h index 64e6f8cc4b2..23a3f4d4b68 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.h +++ b/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.h @@ -1,8 +1,3 @@ -#ifndef RR_GRAPH_INDEXED_DATA_H -#define RR_GRAPH_INDEXED_DATA_H -#include "physical_types.h" -#include "alloc_and_load_rr_indexed_data.h" +#pragma once void load_rr_index_segments(const int num_segment); - -#endif diff --git a/vpr/src/route/rr_graph_generation/rr_graph_sbox.cpp b/vpr/src/route/rr_graph_generation/rr_graph_sbox.cpp index 0e57727f056..023b93b15e3 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_sbox.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_sbox.cpp @@ -1,12 +1,8 @@ #include "vtr_assert.h" #include "vtr_util.h" -#include "vtr_memory.h" -#include "vpr_types.h" #include "rr_graph_sbox.h" -#include "rr_graph_utils.h" -#include "rr_graph2.h" #include "echo_files.h" /* Switch box: * diff --git a/vpr/src/route/rr_graph_generation/rr_graph_sbox.h b/vpr/src/route/rr_graph_generation/rr_graph_sbox.h index d50d9a50edb..f4666f53964 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_sbox.h +++ b/vpr/src/route/rr_graph_generation/rr_graph_sbox.h @@ -1,7 +1,9 @@ -#ifndef RR_GRAPH_SBOX_H -#define RR_GRAPH_SBOX_H +#pragma once #include +#include "rr_graph_type.h" +#include "rr_node_types.h" +#include "vtr_ndmatrix.h" std::vector get_switch_box_tracks(const int from_i, const int from_j, @@ -17,5 +19,3 @@ vtr::NdMatrix, 3> alloc_and_load_switch_block_conn(t_chan_width int Fs); int get_simple_switch_block_track(enum e_side from_side, enum e_side to_side, int from_track, enum e_switch_block_type switch_block_type, const int from_chan_width, const int to_chan_width); - -#endif diff --git a/vpr/src/route/rr_graph_generation/rr_graph_timing_params.h b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.h index c250efdba3a..e919edf9a2a 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_timing_params.h +++ b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.h @@ -1 +1,3 @@ +#pragma once + void add_rr_graph_C_from_switches(float C_ipin_cblock); diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp index 5fed7376669..4097e42fc87 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -4,6 +4,7 @@ #include "describe_rr_node.h" #include "globals.h" #include "physical_types_util.h" +#include "rr_graph2.h" #include "vpr_utils.h" /** diff --git a/vpr/src/route/rr_graph_generation/rr_types.h b/vpr/src/route/rr_graph_generation/rr_types.h index 620427a2d11..12854d26e1a 100644 --- a/vpr/src/route/rr_graph_generation/rr_types.h +++ b/vpr/src/route/rr_graph_generation/rr_types.h @@ -1,8 +1,9 @@ -#ifndef RR_TYPES_H -#define RR_TYPES_H +#pragma once #include +#include "rr_node_types.h" #include "vtr_ndmatrix.h" +#include "vtr_string_view.h" /* AA: This structure stores the track connections for each physical pin. Note that num_pins refers to the # of logical pins for a tile and * we use the relative x and y location (0...width and 0...height of the tile) and the side of that unit tile to locate the physical pin. @@ -75,7 +76,7 @@ struct t_seg_details { bool twisted = false; /** @brief Direction of the segment. */ - enum Direction direction = Direction::NONE; + Direction direction = Direction::NONE; /** @brief Index of the first logic block in the group. */ int group_start = 0; @@ -182,5 +183,3 @@ typedef vtr::NdMatrix t_chan_details; * [0..3 (To side)][0...max_chan_width][0..3 (to_mux,to_trac,alt_mux,alt_track)] * originally initialized to UN_SET until alloc_and_load_sb is called */ typedef vtr::NdMatrix t_sblock_pattern; - -#endif diff --git a/vpr/src/route/serial_connection_router.h b/vpr/src/route/serial_connection_router.h index 990c93c29fb..d083504a3aa 100644 --- a/vpr/src/route/serial_connection_router.h +++ b/vpr/src/route/serial_connection_router.h @@ -1,5 +1,4 @@ -#ifndef _SERIAL_CONNECTION_ROUTER_H -#define _SERIAL_CONNECTION_ROUTER_H +#pragma once #include "connection_router.h" @@ -249,5 +248,3 @@ std::unique_ptr make_serial_connection_router( const vtr::vector& rr_switch_inf, vtr::vector& rr_node_route_inf, bool is_flat); - -#endif /* _SERIAL_CONNECTION_ROUTER_H */ diff --git a/vpr/src/server/bytearray.h b/vpr/src/server/bytearray.h index 566cc83f02d..66acbf51a87 100644 --- a/vpr/src/server/bytearray.h +++ b/vpr/src/server/bytearray.h @@ -1,12 +1,11 @@ -#ifndef BYTEARRAY_H -#define BYTEARRAY_H +#pragma once #ifndef NO_SERVER -#include -#include -#include #include +#include +#include +#include namespace comm { @@ -170,5 +169,3 @@ class ByteArray : public std::vector { } // namespace comm #endif /* NO_SERVER */ - -#endif /* BYTEARRAY_H */ diff --git a/vpr/src/server/commcmd.h b/vpr/src/server/commcmd.h index 54301bad63e..b90428f2762 100644 --- a/vpr/src/server/commcmd.h +++ b/vpr/src/server/commcmd.h @@ -1,5 +1,4 @@ -#ifndef COMMCMD_H -#define COMMCMD_H +#pragma once #ifndef NO_SERVER @@ -14,5 +13,3 @@ enum class CMD : int { } // namespace comm #endif /* NO_SERVER */ - -#endif /* COMMCMD_H */ diff --git a/vpr/src/server/commconstants.h b/vpr/src/server/commconstants.h index 2eaeed60386..b5a638735fa 100644 --- a/vpr/src/server/commconstants.h +++ b/vpr/src/server/commconstants.h @@ -1,5 +1,4 @@ -#ifndef COMMCONSTS_H -#define COMMCONSTS_H +#pragma once #ifndef NO_SERVER @@ -31,5 +30,3 @@ inline const std::string KEY_HOLD_PATH_LIST{"hold"}; } // namespace comm #endif /* NO_SERVER */ - -#endif /* COMMCONSTS_H */ diff --git a/vpr/src/server/convertutils.h b/vpr/src/server/convertutils.h index 73658145395..3bab3424283 100644 --- a/vpr/src/server/convertutils.h +++ b/vpr/src/server/convertutils.h @@ -1,5 +1,4 @@ -#ifndef CONVERTUTILS_H -#define CONVERTUTILS_H +#pragma once #ifndef NO_SERVER @@ -15,5 +14,3 @@ std::string get_pretty_size_str_from_bytes_num(int64_t bytesNum); std::string get_truncated_middle_str(const std::string& src, std::size_t num = DEFAULT_PRINT_STRING_MAX_NUM); #endif /* NO_SERVER */ - -#endif /* CONVERTUTILS_H */ diff --git a/vpr/src/server/gateio.cpp b/vpr/src/server/gateio.cpp index 4094fd3e061..346c0843310 100644 --- a/vpr/src/server/gateio.cpp +++ b/vpr/src/server/gateio.cpp @@ -6,59 +6,17 @@ #include "commconstants.h" #include "convertutils.h" -namespace server { - -GateIO::GateIO() { - m_is_running.store(false); -} - -GateIO::~GateIO() { - stop(); -} +#include "sockpp/tcp6_acceptor.h" -void GateIO::start(int port_num) { - if (!m_is_running.load()) { - m_port_num = port_num; - VTR_LOG("starting server"); - m_is_running.store(true); - m_thread = std::thread(&GateIO::start_listening, this); - } -} - -void GateIO::stop() { - if (m_is_running.load()) { - m_is_running.store(false); - if (m_thread.joinable()) { - m_thread.join(); - } - } -} - -void GateIO::take_received_tasks(std::vector& tasks) { - std::unique_lock lock(m_tasks_mutex); - for (TaskPtr& task : m_received_tasks) { - m_logger.queue(LogLevel::Debug, "move task id=", task->job_id(), "for processing"); - tasks.push_back(std::move(task)); - } - m_received_tasks.clear(); -} - -void GateIO::move_tasks_to_send_queue(std::vector& tasks) { - std::unique_lock lock(m_tasks_mutex); - for (TaskPtr& task : tasks) { - m_logger.queue(LogLevel::Debug, "move task id=", task->job_id(), "finished", (task->has_error() ? "with error" : "successfully"), task->error(), "to send queue"); - m_send_tasks.push_back(std::move(task)); - } - tasks.clear(); -} +namespace server { -GateIO::ActivityStatus GateIO::check_client_connection(sockpp::tcp6_acceptor& tcp_server, std::optional& client_opt) { +static ActivityStatus check_client_connection(sockpp::tcp6_acceptor& tcp_server, std::optional& client_opt, TLogger& logger) { ActivityStatus status = ActivityStatus::WAITING_ACTIVITY; sockpp::inet6_address peer; sockpp::tcp6_socket client = tcp_server.accept(&peer); if (client) { - m_logger.queue(LogLevel::Info, "client", client.address().to_string(), "connection accepted"); + logger.queue(LogLevel::Info, "client", client.address().to_string(), "connection accepted"); client.set_non_blocking(true); client_opt = std::move(client); @@ -68,59 +26,59 @@ GateIO::ActivityStatus GateIO::check_client_connection(sockpp::tcp6_acceptor& tc return status; } -GateIO::ActivityStatus GateIO::handle_sending_data(sockpp::tcp6_socket& client) { +static ActivityStatus handle_sending_data(sockpp::tcp6_socket& client, std::mutex& tasks_mutex, std::vector& send_tasks, TLogger& logger) { ActivityStatus status = ActivityStatus::WAITING_ACTIVITY; - std::unique_lock lock(m_tasks_mutex); + std::unique_lock lock(tasks_mutex); - if (!m_send_tasks.empty()) { - const TaskPtr& task = m_send_tasks.at(0); + if (!send_tasks.empty()) { + const TaskPtr& task = send_tasks.at(0); try { std::size_t bytes_to_send = std::min(CHUNK_MAX_BYTES_NUM, task->response_buffer().size()); std::size_t bytes_sent = client.write_n(task->response_buffer().data(), bytes_to_send); if (bytes_sent <= task->orig_reponse_bytes_num()) { task->chop_num_sent_bytes_from_response_buffer(bytes_sent); - m_logger.queue(LogLevel::Detail, - "sent chunk:", get_pretty_size_str_from_bytes_num(bytes_sent), - "from", get_pretty_size_str_from_bytes_num(task->orig_reponse_bytes_num()), - "left:", get_pretty_size_str_from_bytes_num(task->response_buffer().size())); + logger.queue(LogLevel::Detail, + "sent chunk:", get_pretty_size_str_from_bytes_num(bytes_sent), + "from", get_pretty_size_str_from_bytes_num(task->orig_reponse_bytes_num()), + "left:", get_pretty_size_str_from_bytes_num(task->response_buffer().size())); status = ActivityStatus::CLIENT_ACTIVITY; } } catch (...) { - m_logger.queue(LogLevel::Detail, "error while writing chunk"); + logger.queue(LogLevel::Detail, "error while writing chunk"); status = ActivityStatus::COMMUNICATION_PROBLEM; } if (task->is_response_fully_sent()) { - m_logger.queue(LogLevel::Info, "sent:", task->telegram_header().info(), task->info()); + logger.queue(LogLevel::Info, "sent:", task->telegram_header().info(), task->info()); } } // remove reported tasks - std::size_t tasks_num_before_removing = m_send_tasks.size(); + std::size_t tasks_num_before_removing = send_tasks.size(); - auto partition_iter = std::partition(m_send_tasks.begin(), m_send_tasks.end(), + auto partition_iter = std::partition(send_tasks.begin(), send_tasks.end(), [](const TaskPtr& task) { return !task->is_response_fully_sent(); }); - m_send_tasks.erase(partition_iter, m_send_tasks.end()); - bool is_removing_took_place = tasks_num_before_removing != m_send_tasks.size(); - if (!m_send_tasks.empty() && is_removing_took_place) { - m_logger.queue(LogLevel::Detail, "left tasks num to send ", m_send_tasks.size()); + send_tasks.erase(partition_iter, send_tasks.end()); + bool is_removing_took_place = tasks_num_before_removing != send_tasks.size(); + if (!send_tasks.empty() && is_removing_took_place) { + logger.queue(LogLevel::Detail, "left tasks num to send ", send_tasks.size()); } return status; } -GateIO::ActivityStatus GateIO::handle_receiving_data(sockpp::tcp6_socket& client, comm::TelegramBuffer& telegram_buff, std::string& received_message) { +static ActivityStatus handle_receiving_data(sockpp::tcp6_socket& client, comm::TelegramBuffer& telegram_buff, std::string& received_message, TLogger& logger) { ActivityStatus status = ActivityStatus::WAITING_ACTIVITY; std::size_t bytes_actually_received{0}; try { bytes_actually_received = client.read_n(&received_message[0], CHUNK_MAX_BYTES_NUM); } catch (...) { - m_logger.queue(LogLevel::Error, "fail to receiving"); + logger.queue(LogLevel::Error, "fail to receiving"); status = ActivityStatus::COMMUNICATION_PROBLEM; } if ((bytes_actually_received > 0) && (bytes_actually_received <= CHUNK_MAX_BYTES_NUM)) { - m_logger.queue(LogLevel::Detail, "received chunk:", get_pretty_size_str_from_bytes_num(bytes_actually_received)); + logger.queue(LogLevel::Detail, "received chunk:", get_pretty_size_str_from_bytes_num(bytes_actually_received)); telegram_buff.append(comm::ByteArray{received_message.c_str(), bytes_actually_received}); status = ActivityStatus::CLIENT_ACTIVITY; } @@ -128,7 +86,7 @@ GateIO::ActivityStatus GateIO::handle_receiving_data(sockpp::tcp6_socket& client return status; } -GateIO::ActivityStatus GateIO::handle_telegrams(std::vector& telegram_frames, comm::TelegramBuffer& telegram_buff) { +static ActivityStatus handle_telegrams(std::vector& telegram_frames, comm::TelegramBuffer& telegram_buff, std::mutex& tasks_mutex, std::vector& received_tasks, TLogger& logger) { ActivityStatus status = ActivityStatus::WAITING_ACTIVITY; telegram_frames.clear(); telegram_buff.take_telegram_frames(telegram_frames); @@ -137,24 +95,24 @@ GateIO::ActivityStatus GateIO::handle_telegrams(std::vectorbody}; bool is_echo_telegram = false; if ((message.size() == comm::ECHO_TELEGRAM_BODY.size()) && (message == comm::ECHO_TELEGRAM_BODY)) { - m_logger.queue(LogLevel::Detail, "received", comm::ECHO_TELEGRAM_BODY); + logger.queue(LogLevel::Detail, "received", comm::ECHO_TELEGRAM_BODY); is_echo_telegram = true; status = ActivityStatus::CLIENT_ACTIVITY; } if (!is_echo_telegram) { - m_logger.queue(LogLevel::Detail, "received composed", get_pretty_size_str_from_bytes_num(message.size()), ":", get_truncated_middle_str(message)); + logger.queue(LogLevel::Detail, "received composed", get_pretty_size_str_from_bytes_num(message.size()), ":", get_truncated_middle_str(message)); std::optional job_id_opt = comm::TelegramParser::try_extract_field_job_id(message); std::optional cmd_opt = comm::TelegramParser::try_extract_field_cmd(message); std::optional options_opt = comm::TelegramParser::try_extract_field_options(message); if (job_id_opt && cmd_opt && options_opt) { TaskPtr task = std::make_unique(job_id_opt.value(), static_cast(cmd_opt.value()), options_opt.value()); const comm::TelegramHeader& header = telegram_frame->header; - m_logger.queue(LogLevel::Info, "received:", header.info(), task->info(/*skipDuration*/ true)); - std::unique_lock lock(m_tasks_mutex); - m_received_tasks.push_back(std::move(task)); + logger.queue(LogLevel::Info, "received:", header.info(), task->info(/*skipDuration*/ true)); + std::unique_lock lock(tasks_mutex); + received_tasks.push_back(std::move(task)); } else { - m_logger.queue(LogLevel::Error, "broken telegram detected, fail extract options from", message); + logger.queue(LogLevel::Error, "broken telegram detected, fail extract options from", message); } } } @@ -162,7 +120,7 @@ GateIO::ActivityStatus GateIO::handle_telegrams(std::vector& client_alive_tracker_ptr) { +static ActivityStatus handle_client_alive_tracker(sockpp::tcp6_socket& client, std::unique_ptr& client_alive_tracker_ptr, TLogger& logger) { ActivityStatus status = ActivityStatus::WAITING_ACTIVITY; if (client_alive_tracker_ptr) { /// handle sending echo to client @@ -173,18 +131,18 @@ GateIO::ActivityStatus GateIO::handle_client_alive_tracker(sockpp::tcp6_socket& try { std::size_t bytes_sent = client.write(message); if (bytes_sent == message.size()) { - m_logger.queue(LogLevel::Detail, "sent", comm::ECHO_TELEGRAM_BODY); + logger.queue(LogLevel::Detail, "sent", comm::ECHO_TELEGRAM_BODY); client_alive_tracker_ptr->on_echo_sent(); } } catch (...) { - m_logger.queue(LogLevel::Debug, "fail to sent", comm::ECHO_TELEGRAM_BODY); + logger.queue(LogLevel::Debug, "fail to sent", comm::ECHO_TELEGRAM_BODY); status = ActivityStatus::COMMUNICATION_PROBLEM; } } /// handle client timeout if (client_alive_tracker_ptr->is_client_timeout()) { - m_logger.queue(LogLevel::Error, "client didn't respond too long"); + logger.queue(LogLevel::Error, "client didn't respond too long"); status = ActivityStatus::COMMUNICATION_PROBLEM; } } @@ -192,7 +150,7 @@ GateIO::ActivityStatus GateIO::handle_client_alive_tracker(sockpp::tcp6_socket& return status; } -void GateIO::handle_activity_status(ActivityStatus status, std::unique_ptr& client_alive_tracker_ptr, bool& is_communication_problem_detected) { +static void handle_activity_status(ActivityStatus status, std::unique_ptr& client_alive_tracker_ptr, bool& is_communication_problem_detected) { if (status == ActivityStatus::CLIENT_ACTIVITY) { if (client_alive_tracker_ptr) { client_alive_tracker_ptr->on_client_activity(); @@ -202,9 +160,54 @@ void GateIO::handle_activity_status(ActivityStatus status, std::unique_ptr& tasks) { + std::unique_lock lock(m_tasks_mutex); + for (TaskPtr& task : m_received_tasks) { + m_logger.queue(LogLevel::Debug, "move task id=", task->job_id(), "for processing"); + tasks.push_back(std::move(task)); + } + m_received_tasks.clear(); +} + +void GateIO::move_tasks_to_send_queue(std::vector& tasks) { + std::unique_lock lock(m_tasks_mutex); + for (TaskPtr& task : tasks) { + m_logger.queue(LogLevel::Debug, "move task id=", task->job_id(), "finished", (task->has_error() ? "with error" : "successfully"), task->error(), "to send queue"); + m_send_tasks.push_back(std::move(task)); + } + tasks.clear(); +} + void GateIO::start_listening() { #ifdef ENABLE_CLIENT_ALIVE_TRACKER - std::unique_ptr client_alive_tracker_ptr = std::make_unique(std::chrono::milliseconds{5000}, std::chrono::milliseconds{20000}); + std::unique_ptr client_alive_tracker_ptr = + std::make_unique(std::chrono::milliseconds{5000}, std::chrono::milliseconds{20000}); #else std::unique_ptr client_alive_tracker_ptr; #endif @@ -232,7 +235,7 @@ void GateIO::start_listening() { bool is_communication_problem_detected = false; if (!client_opt) { - ActivityStatus status = check_client_connection(tcp_server, client_opt); + ActivityStatus status = check_client_connection(tcp_server, client_opt, m_logger); if (status == ActivityStatus::CLIENT_ACTIVITY) { if (client_alive_tracker_ptr) { client_alive_tracker_ptr->reset(); @@ -244,15 +247,15 @@ void GateIO::start_listening() { sockpp::tcp6_socket& client = client_opt.value(); // shortcut /// handle sending - ActivityStatus status = handle_sending_data(client); + ActivityStatus status = handle_sending_data(client, m_tasks_mutex, m_send_tasks, m_logger); handle_activity_status(status, client_alive_tracker_ptr, is_communication_problem_detected); /// handle receiving - status = handle_receiving_data(client, telegram_buff, received_message); + status = handle_receiving_data(client, telegram_buff, received_message, m_logger); handle_activity_status(status, client_alive_tracker_ptr, is_communication_problem_detected); /// handle telegrams - status = handle_telegrams(telegram_frames, telegram_buff); + status = handle_telegrams(telegram_frames, telegram_buff, m_tasks_mutex, m_received_tasks, m_logger); handle_activity_status(status, client_alive_tracker_ptr, is_communication_problem_detected); // forward telegramBuffer errors @@ -263,7 +266,7 @@ void GateIO::start_listening() { } /// handle client alive tracker - status = handle_client_alive_tracker(client, client_alive_tracker_ptr); + status = handle_client_alive_tracker(client, client_alive_tracker_ptr, m_logger); handle_activity_status(status, client_alive_tracker_ptr, is_communication_problem_detected); /// handle communication problem diff --git a/vpr/src/server/gateio.h b/vpr/src/server/gateio.h index ee72d155cb7..6646882b0f7 100644 --- a/vpr/src/server/gateio.h +++ b/vpr/src/server/gateio.h @@ -1,5 +1,4 @@ -#ifndef GATEIO_H -#define GATEIO_H +#pragma once #ifndef NO_SERVER @@ -17,10 +16,107 @@ #include #include -#include "sockpp/tcp6_acceptor.h" - namespace server { +enum class ActivityStatus : int { + WAITING_ACTIVITY, + CLIENT_ACTIVITY, + COMMUNICATION_PROBLEM +}; + +enum class LogLevel : int { + Error, + Info, + Detail, + Debug +}; + +const std::size_t CHUNK_MAX_BYTES_NUM = 2 * 1024 * 1024; // 2Mb + +/** + * @brief Helper class aimed to help detecting a client offline. + * + * The ClientAliveTracker is pinged each time there is some activity from the client side. + * When the client doesn't show activity for a certain amount of time, the ClientAliveTracker generates + * an event for sending an ECHO telegram to the client. + * If, after sending the ECHO telegram, the client does not respond with an ECHO, it means the client is absent, + * and it's time to start accepting new client connections in GateIO. + */ +class ClientAliveTracker { + public: + ClientAliveTracker(const std::chrono::milliseconds& echoIntervalMs, const std::chrono::milliseconds& clientTimeoutMs) + : m_echo_interval_ms(echoIntervalMs) + , m_client_timeout_ms(clientTimeoutMs) { + reset(); + } + ClientAliveTracker() = default; + + void on_client_activity() { + m_last_client_activity_time = std::chrono::high_resolution_clock::now(); + } + + void on_echo_sent() { + m_last_echo_sent_time = std::chrono::high_resolution_clock::now(); + } + + bool is_time_to_sent_echo() const { + return (duration_since_last_client_activity_ms() > m_echo_interval_ms) && (durationSinceLastEchoSentMs() > m_echo_interval_ms); + } + bool is_client_timeout() const { return duration_since_last_client_activity_ms() > m_client_timeout_ms; } + + void reset() { + on_client_activity(); + } + + private: + std::chrono::high_resolution_clock::time_point m_last_client_activity_time; + std::chrono::high_resolution_clock::time_point m_last_echo_sent_time; + std::chrono::milliseconds m_echo_interval_ms; + std::chrono::milliseconds m_client_timeout_ms; + + std::chrono::milliseconds duration_since_last_client_activity_ms() const { + auto now = std::chrono::high_resolution_clock::now(); + return std::chrono::duration_cast(now - m_last_client_activity_time); + } + std::chrono::milliseconds durationSinceLastEchoSentMs() const { + auto now = std::chrono::high_resolution_clock::now(); + return std::chrono::duration_cast(now - m_last_echo_sent_time); + } +}; + +class TLogger { + public: + TLogger() { + m_log_level = static_cast(LogLevel::Info); + } + ~TLogger() {} + + template + void queue(LogLevel logLevel, Args&&... args) { + if (static_cast(logLevel) <= m_log_level) { + std::unique_lock lock(m_log_stream_mutex); + if (logLevel == LogLevel::Error) { + m_log_stream << "ERROR:"; + } + ((m_log_stream << ' ' << std::forward(args)), ...); + m_log_stream << "\n"; + } + } + + void flush() { + std::unique_lock lock(m_log_stream_mutex); + if (!m_log_stream.str().empty()) { + VTR_LOG(m_log_stream.str().c_str()); + m_log_stream.str(""); + } + } + + private: + std::stringstream m_log_stream; + std::mutex m_log_stream_mutex; + std::atomic m_log_level; +}; + /** * @brief Implements the socket communication layer with the outside world. * @@ -39,105 +135,6 @@ namespace server { * - The socket is initialized in a non-blocking mode to function properly in a multithreaded environment. */ class GateIO { - enum class ActivityStatus : int { - WAITING_ACTIVITY, - CLIENT_ACTIVITY, - COMMUNICATION_PROBLEM - }; - - const std::size_t CHUNK_MAX_BYTES_NUM = 2 * 1024 * 1024; // 2Mb - - /** - * @brief Helper class aimed to help detecting a client offline. - * - * The ClientAliveTracker is pinged each time there is some activity from the client side. - * When the client doesn't show activity for a certain amount of time, the ClientAliveTracker generates - * an event for sending an ECHO telegram to the client. - * If, after sending the ECHO telegram, the client does not respond with an ECHO, it means the client is absent, - * and it's time to start accepting new client connections in GateIO. - */ - class ClientAliveTracker { - public: - ClientAliveTracker(const std::chrono::milliseconds& echoIntervalMs, const std::chrono::milliseconds& clientTimeoutMs) - : m_echo_interval_ms(echoIntervalMs) - , m_client_timeout_ms(clientTimeoutMs) { - reset(); - } - ClientAliveTracker() = default; - - void on_client_activity() { - m_last_client_activity_time = std::chrono::high_resolution_clock::now(); - } - - void on_echo_sent() { - m_last_echo_sent_time = std::chrono::high_resolution_clock::now(); - } - - bool is_time_to_sent_echo() const { - return (duration_since_last_client_activity_ms() > m_echo_interval_ms) && (durationSinceLastEchoSentMs() > m_echo_interval_ms); - } - bool is_client_timeout() const { return duration_since_last_client_activity_ms() > m_client_timeout_ms; } - - void reset() { - on_client_activity(); - } - - private: - std::chrono::high_resolution_clock::time_point m_last_client_activity_time; - std::chrono::high_resolution_clock::time_point m_last_echo_sent_time; - std::chrono::milliseconds m_echo_interval_ms; - std::chrono::milliseconds m_client_timeout_ms; - - std::chrono::milliseconds duration_since_last_client_activity_ms() const { - auto now = std::chrono::high_resolution_clock::now(); - return std::chrono::duration_cast(now - m_last_client_activity_time); - } - std::chrono::milliseconds durationSinceLastEchoSentMs() const { - auto now = std::chrono::high_resolution_clock::now(); - return std::chrono::duration_cast(now - m_last_echo_sent_time); - } - }; - - enum class LogLevel : int { - Error, - Info, - Detail, - Debug - }; - - class TLogger { - public: - TLogger() { - m_log_level = static_cast(LogLevel::Info); - } - ~TLogger() {} - - template - void queue(LogLevel logLevel, Args&&... args) { - if (static_cast(logLevel) <= m_log_level) { - std::unique_lock lock(m_log_stream_mutex); - if (logLevel == LogLevel::Error) { - m_log_stream << "ERROR:"; - } - ((m_log_stream << ' ' << std::forward(args)), ...); - m_log_stream << "\n"; - } - } - - void flush() { - std::unique_lock lock(m_log_stream_mutex); - if (!m_log_stream.str().empty()) { - VTR_LOG(m_log_stream.str().c_str()); - m_log_stream.str(""); - } - } - - private: - std::stringstream m_log_stream; - std::mutex m_log_stream_mutex; - std::atomic m_log_level; - }; - const int LOOP_INTERVAL_MS = 100; public: @@ -224,19 +221,8 @@ class GateIO { TLogger m_logger; void start_listening(); // thread worker function - - /// helper functions to be executed inside startListening - ActivityStatus check_client_connection(sockpp::tcp6_acceptor& tcp_server, std::optional& client_opt); - ActivityStatus handle_sending_data(sockpp::tcp6_socket& client); - ActivityStatus handle_receiving_data(sockpp::tcp6_socket& client, comm::TelegramBuffer& telegram_buff, std::string& received_message); - ActivityStatus handle_telegrams(std::vector& telegram_frames, comm::TelegramBuffer& telegram_buff); - ActivityStatus handle_client_alive_tracker(sockpp::tcp6_socket& client, std::unique_ptr& client_alive_tracker_ptr); - void handle_activity_status(ActivityStatus status, std::unique_ptr& client_alive_tracker_ptr, bool& is_communication_problem_detected); - /// }; } // namespace server #endif /* NO_SERVER */ - -#endif /* GATEIO_H */ diff --git a/vpr/src/server/pathhelper.h b/vpr/src/server/pathhelper.h index 3de4ba9f4f4..09337cf9ca1 100644 --- a/vpr/src/server/pathhelper.h +++ b/vpr/src/server/pathhelper.h @@ -1,5 +1,4 @@ -#ifndef PATHHELPER_H -#define PATHHELPER_H +#pragma once #ifndef NO_SERVER @@ -51,5 +50,3 @@ CritPathsResultPtr calc_critical_path(const std::string& type, int crit_path_num } // namespace server #endif /* NO_SERVER */ - -#endif /* PATHHELPER_H */ diff --git a/vpr/src/server/serverupdate.h b/vpr/src/server/serverupdate.h index 2235c6910a3..cc935808829 100644 --- a/vpr/src/server/serverupdate.h +++ b/vpr/src/server/serverupdate.h @@ -1,5 +1,4 @@ -#ifndef SERVERUPDATE_H -#define SERVERUPDATE_H +#pragma once #ifndef NO_SERVER @@ -19,5 +18,3 @@ gboolean update(gpointer); } // namespace server #endif /* NO_SERVER */ - -#endif /* SERVERUPDATE_H */ diff --git a/vpr/src/server/task.h b/vpr/src/server/task.h index 696e2fb012d..3c9430397a4 100644 --- a/vpr/src/server/task.h +++ b/vpr/src/server/task.h @@ -1,5 +1,4 @@ -#ifndef TASK_H -#define TASK_H +#pragma once #ifndef NO_SERVER @@ -201,5 +200,3 @@ using TaskPtr = std::unique_ptr; } // namespace server #endif /* NO_SERVER */ - -#endif /* TASK_H */ diff --git a/vpr/src/server/taskresolver.h b/vpr/src/server/taskresolver.h index ce38348a6b5..86e5d4134f3 100644 --- a/vpr/src/server/taskresolver.h +++ b/vpr/src/server/taskresolver.h @@ -1,5 +1,4 @@ -#ifndef TASKRESOLVER_H -#define TASKRESOLVER_H +#pragma once #ifndef NO_SERVER @@ -75,5 +74,3 @@ class TaskResolver { } // namespace server #endif /* NO_SERVER */ - -#endif /* TASKRESOLVER_H */ diff --git a/vpr/src/server/telegrambuffer.h b/vpr/src/server/telegrambuffer.h index f7e2abba229..ed5e053dca6 100644 --- a/vpr/src/server/telegrambuffer.h +++ b/vpr/src/server/telegrambuffer.h @@ -1,5 +1,4 @@ -#ifndef TELEGRAMBUFFER_H -#define TELEGRAMBUFFER_H +#pragma once #ifndef NO_SERVER @@ -97,5 +96,3 @@ class TelegramBuffer { } // namespace comm #endif /* NO_SERVER */ - -#endif /* TELEGRAMBUFFER_H */ diff --git a/vpr/src/server/telegramframe.h b/vpr/src/server/telegramframe.h index 2fc0c312a73..158613bc357 100644 --- a/vpr/src/server/telegramframe.h +++ b/vpr/src/server/telegramframe.h @@ -1,5 +1,4 @@ -#ifndef TELEGRAMFRAME_H -#define TELEGRAMFRAME_H +#pragma once #ifndef NO_SERVER @@ -31,5 +30,3 @@ using TelegramFramePtr = std::shared_ptr; } // namespace comm #endif /* NO_SERVER */ - -#endif /* TELEGRAMFRAME_H */ diff --git a/vpr/src/server/telegramheader.h b/vpr/src/server/telegramheader.h index 84f1adcac1d..a2acdd9c1de 100644 --- a/vpr/src/server/telegramheader.h +++ b/vpr/src/server/telegramheader.h @@ -1,5 +1,4 @@ -#ifndef TELEGRAMHEADER_H -#define TELEGRAMHEADER_H +#pragma once #ifndef NO_SERVER @@ -141,5 +140,3 @@ class TelegramHeader { } // namespace comm #endif /* NO_SERVER */ - -#endif /* TELEGRAMHEADER_H */ diff --git a/vpr/src/server/telegramoptions.h b/vpr/src/server/telegramoptions.h index 576973c441f..f789205af9b 100644 --- a/vpr/src/server/telegramoptions.h +++ b/vpr/src/server/telegramoptions.h @@ -1,5 +1,4 @@ -#ifndef TELEGRAMOPTIONS_H -#define TELEGRAMOPTIONS_H +#pragma once #ifndef NO_SERVER @@ -126,5 +125,3 @@ class TelegramOptions { } // namespace server #endif /* NO_SERVER */ - -#endif /* TELEGRAMOPTIONS_H */ diff --git a/vpr/src/server/telegramparser.h b/vpr/src/server/telegramparser.h index 633c83484ce..2da3dfe35a4 100644 --- a/vpr/src/server/telegramparser.h +++ b/vpr/src/server/telegramparser.h @@ -1,5 +1,4 @@ -#ifndef TELEGRAMPARSER_H -#define TELEGRAMPARSER_H +#pragma once #ifndef NO_SERVER @@ -83,5 +82,3 @@ class TelegramParser { } // namespace comm #endif /* NO_SERVER */ - -#endif /* TELEGRAMPARSER_H */ diff --git a/vpr/src/server/zlibutils.h b/vpr/src/server/zlibutils.h index c9ca7cded52..d925ab36533 100644 --- a/vpr/src/server/zlibutils.h +++ b/vpr/src/server/zlibutils.h @@ -1,5 +1,4 @@ -#ifndef ZLIBUTILS_H -#define ZLIBUTILS_H +#pragma once #ifndef NO_SERVER @@ -37,5 +36,3 @@ std::optional try_compress(const std::string& decompressed); std::optional try_decompress(const std::string& compressed); #endif /* NO_SERVER */ - -#endif /* ZLIBUTILS_H */ diff --git a/vpr/src/timing/AnalysisDelayCalculator.h b/vpr/src/timing/AnalysisDelayCalculator.h index c12dbab6919..97098827754 100644 --- a/vpr/src/timing/AnalysisDelayCalculator.h +++ b/vpr/src/timing/AnalysisDelayCalculator.h @@ -1,8 +1,5 @@ -#ifndef ANALYSIS_DELAY_CALCULATOR_H -#define ANALYSIS_DELAY_CALCULATOR_H +#pragma once #include "PostClusterDelayCalculator.h" using AnalysisDelayCalculator = PostClusterDelayCalculator; - -#endif diff --git a/vpr/src/timing/DelayType.h b/vpr/src/timing/DelayType.h index 77d3144708b..872ee212e45 100644 --- a/vpr/src/timing/DelayType.h +++ b/vpr/src/timing/DelayType.h @@ -1,10 +1,7 @@ -#ifndef VPR_DELAY_TYPE -#define VPR_DELAY_TYPE +#pragma once enum class DelayType { MAX = 0, MIN, NUM_DELAY_TYPES }; - -#endif diff --git a/vpr/src/timing/DomainPair.h b/vpr/src/timing/DomainPair.h index 892ab6a5605..fe73d07a783 100644 --- a/vpr/src/timing/DomainPair.h +++ b/vpr/src/timing/DomainPair.h @@ -1,5 +1,4 @@ -#ifndef VRP_DOMAIN_PAIR_H -#define VRP_DOMAIN_PAIR_H +#pragma once #include "tatum/TimingGraphFwd.hpp" @@ -20,5 +19,3 @@ struct DomainPair { return std::tie(lhs.launch, lhs.capture) == std::tie(rhs.launch, rhs.capture); } }; - -#endif diff --git a/vpr/src/timing/NetPinTimingInvalidator.h b/vpr/src/timing/NetPinTimingInvalidator.h index 09badeecc53..b90c4c83b66 100644 --- a/vpr/src/timing/NetPinTimingInvalidator.h +++ b/vpr/src/timing/NetPinTimingInvalidator.h @@ -1,15 +1,17 @@ #pragma once -#include "netlist_fwd.h" +#include "clustered_netlist_utils.h" +#include "netlist.h" +#include "tatum/TimingGraph.hpp" #include "tatum/TimingGraphFwd.hpp" #include "timing_info.h" #include "vtr_range.h" #include "move_transactions.h" -#include "vtr_vec_id_set.h" - #ifdef VPR_USE_TBB #include +#else +#include "vtr_vec_id_set.h" #endif /** Make NetPinTimingInvalidator a virtual class since it does nothing for the general case of non-incremental diff --git a/vpr/src/timing/PlacementDelayCalculator.h b/vpr/src/timing/PlacementDelayCalculator.h index fc7c66d8efb..713481c2ff7 100644 --- a/vpr/src/timing/PlacementDelayCalculator.h +++ b/vpr/src/timing/PlacementDelayCalculator.h @@ -1,8 +1,5 @@ -#ifndef PLACEMENT_DELAY_CALCULATOR_H -#define PLACEMENT_DELAY_CALCULATOR_H +#pragma once #include "PostClusterDelayCalculator.h" using PlacementDelayCalculator = PostClusterDelayCalculator; - -#endif diff --git a/vpr/src/timing/PostClusterDelayCalculator.h b/vpr/src/timing/PostClusterDelayCalculator.h index fc89373b955..283e48f2298 100644 --- a/vpr/src/timing/PostClusterDelayCalculator.h +++ b/vpr/src/timing/PostClusterDelayCalculator.h @@ -1,14 +1,10 @@ -#ifndef POST_CLUSTER_DELAY_CALCULATOR_H -#define POST_CLUSTER_DELAY_CALCULATOR_H -#include "vtr_linear_map.h" +#pragma once #include "tatum/Time.hpp" #include "tatum/TimingGraph.hpp" #include "tatum/delay_calc/DelayCalculator.hpp" #include "atom_netlist.h" -#include "clustered_netlist.h" -#include "vpr_utils.h" #include "vpr_net_pins_matrix.h" #include "atom_delay_calc.h" @@ -90,4 +86,3 @@ class PostClusterDelayCalculator : public tatum::DelayCalculator { }; #include "PostClusterDelayCalculator.tpp" -#endif diff --git a/vpr/src/timing/PreClusterDelayCalculator.h b/vpr/src/timing/PreClusterDelayCalculator.h index 7b7ee903bbb..ccf4c290bee 100644 --- a/vpr/src/timing/PreClusterDelayCalculator.h +++ b/vpr/src/timing/PreClusterDelayCalculator.h @@ -1,5 +1,6 @@ -#ifndef PRE_CLUSTER_DELAY_CALCULATOR_H -#define PRE_CLUSTER_DELAY_CALCULATOR_H +#pragma once + +#include "netlist_fwd.h" #include "vtr_assert.h" #include "tatum/Time.hpp" @@ -14,6 +15,7 @@ #include "logic_types.h" #include "physical_types.h" #include "prepack.h" +#include "vtr_vector.h" class LogicalModels; @@ -22,14 +24,17 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { PreClusterDelayCalculator(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, const LogicalModels& models, - float intercluster_net_delay, + const vtr::vector& timing_arc_delays, const Prepacker& prepacker) noexcept : netlist_(netlist) , netlist_lookup_(netlist_lookup) , models_(models) - , inter_cluster_net_delay_(intercluster_net_delay) + , timing_arc_delays_(timing_arc_delays) , prepacker_(prepacker) { - //nop + + // Timing arcs are uniquely identified by sink pins, ensure that every + // timing arc delay has an entry for each pin in the atom netlist. + VTR_ASSERT(timing_arc_delays.size() == netlist_.pins().size()); } tatum::Time max_edge_delay(const tatum::TimingGraph& tg, tatum::EdgeId edge_id) const override { @@ -45,8 +50,14 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { } else { VTR_ASSERT(edge_type == tatum::EdgeType::INTERCONNECT); - //External net delay - return tatum::Time(inter_cluster_net_delay_); + // Get the sink pin for this timing edge. This is used to get the + // delay for the timing arc that goes through this sink pin. + AtomPinId atom_sink_pin = netlist_lookup_.tnode_atom_pin(sink_node); + VTR_ASSERT_SAFE(atom_sink_pin.is_valid()); + VTR_ASSERT_SAFE(netlist_.pin_type(atom_sink_pin) == PinType::SINK); + + // External net delay + return tatum::Time(timing_arc_delays_[atom_sink_pin]); } } @@ -168,8 +179,6 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { const AtomNetlist& netlist_; const AtomLookup& netlist_lookup_; const LogicalModels& models_; - const float inter_cluster_net_delay_; + const vtr::vector& timing_arc_delays_; const Prepacker& prepacker_; }; - -#endif diff --git a/vpr/src/timing/PreClusterTimingGraphResolver.cpp b/vpr/src/timing/PreClusterTimingGraphResolver.cpp index 665da067646..d5afe3a5ded 100644 --- a/vpr/src/timing/PreClusterTimingGraphResolver.cpp +++ b/vpr/src/timing/PreClusterTimingGraphResolver.cpp @@ -1,6 +1,8 @@ #include "PreClusterTimingGraphResolver.h" +#include "DelayType.h" #include "atom_netlist.h" #include "atom_lookup.h" +#include "globals.h" PreClusterTimingGraphResolver::PreClusterTimingGraphResolver( const AtomNetlist& netlist, diff --git a/vpr/src/timing/PreClusterTimingGraphResolver.h b/vpr/src/timing/PreClusterTimingGraphResolver.h index 6469c4f8b66..7f048e0166c 100644 --- a/vpr/src/timing/PreClusterTimingGraphResolver.h +++ b/vpr/src/timing/PreClusterTimingGraphResolver.h @@ -1,10 +1,9 @@ -#ifndef VPR_PRE_CLUSTER_TIMING_GRAPH_RESOLVER_H_ -#define VPR_PRE_CLUSTER_TIMING_GRAPH_RESOLVER_H_ +#pragma once -#include "tatum/TimingGraphNameResolver.hpp" -#include "atom_netlist_fwd.h" #include "atom_lookup.h" -#include "AnalysisDelayCalculator.h" +#include "atom_netlist_fwd.h" +#include "tatum/TimingGraphNameResolver.hpp" +#include "tatum/delay_calc/DelayCalculator.hpp" class LogicalModels; @@ -34,5 +33,3 @@ class PreClusterTimingGraphResolver : public tatum::TimingGraphNameResolver { const tatum::DelayCalculator& delay_calc_; e_timing_report_detail detail_level_ = e_timing_report_detail::NETLIST; }; - -#endif /* VPR_PRE_CLUSTER_TIMING_GRAPH_RESOLVER_H_ */ diff --git a/vpr/src/timing/PreClusterTimingManager.cpp b/vpr/src/timing/PreClusterTimingManager.cpp index 7e9d7a6a0d1..f7215dc0592 100644 --- a/vpr/src/timing/PreClusterTimingManager.cpp +++ b/vpr/src/timing/PreClusterTimingManager.cpp @@ -15,6 +15,7 @@ #include "atom_netlist.h" #include "atom_netlist_fwd.h" #include "concrete_timing_info.h" +#include "echo_files.h" #include "physical_types_util.h" #include "prepack.h" #include "tatum/TimingReporter.hpp" @@ -22,6 +23,7 @@ #include "vpr_types.h" #include "vtr_assert.h" #include "vtr_time.h" +#include "vtr_vector.h" /** * Since the parameters of a switch may change as a function of its fanin, @@ -69,17 +71,21 @@ PreClusterTimingManager::PreClusterTimingManager(bool timing_driven, // Start an overall timer for building the pre-cluster timing info. vtr::ScopedStartFinishTimer timer("Initializing Pre-Cluster Timing"); - // Approximate the inter-cluster delay - // FIXME: This can probably be simplified. It can also be improved using - // AP information. + // Approximate the inter-cluster delay. Here, we assign each timing arc + // (which is uniquely identified by the sink pin that it passes through) to + // be an approximation of the inter-cluster delay. + // FIXME: This can probably be simplified. This approximation does not need + // to be that accurate. + // TODO: This can be improved using molecule information. float inter_cluster_net_delay = approximate_inter_cluster_delay(arch, routing_arch, device_layout); VTR_LOG("Using inter-cluster delay: %g\n", inter_cluster_net_delay); + timing_arc_delays_.resize(atom_netlist.pins().size(), inter_cluster_net_delay); // Initialize the timing analyzer clustering_delay_calc_ = std::make_shared(atom_netlist, atom_lookup, arch.models, - inter_cluster_net_delay, + timing_arc_delays_, prepacker); timing_info_ = make_setup_timing_info(clustering_delay_calc_, timing_update_type); @@ -296,3 +302,7 @@ float PreClusterTimingManager::calc_net_setup_criticality(AtomNetId net_id, "Net has no driver"); return timing_info_->setup_pin_criticality(net_driver_pin_id); } + +void PreClusterTimingManager::update_timing_info() { + timing_info_->update(); +} diff --git a/vpr/src/timing/PreClusterTimingManager.h b/vpr/src/timing/PreClusterTimingManager.h index 0aaed6edea1..1560b301c4a 100644 --- a/vpr/src/timing/PreClusterTimingManager.h +++ b/vpr/src/timing/PreClusterTimingManager.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Alex Singer @@ -5,16 +6,17 @@ * @brief Manager class for pre-cluster (primitive-level) timing analysis. */ -#pragma once - #include #include #include "vpr_types.h" #include "vtr_assert.h" +#include "vtr_vector.h" // Forward declarations. class AtomLookup; class AtomNetlist; +class PartialPlacement; +class PlaceDelayModel; class PreClusterDelayCalculator; class Prepacker; class SetupTimingInfo; @@ -86,6 +88,29 @@ class PreClusterTimingManager { float calc_net_setup_criticality(AtomNetId net_id, const AtomNetlist& atom_netlist) const; + /** + * @brief Set the delay of a timing arc, identified by the sink pin that + * it terminates at. + * + * This method only updates an internal variable to this class and does not + * perform STA. Call update_timing_info after updating the delays of all + * arcs to save time. + */ + void set_timing_arc_delay(AtomPinId sink_pin_id, float delay) { + VTR_ASSERT_SAFE_MSG(sink_pin_id.is_valid(), + "Cannot set arc delay of invalid pin"); + + timing_arc_delays_[sink_pin_id] = delay; + } + + /** + * @brief Perform STA to updating the timing information. + * + * This should be called after set_timing_arc_delay has been called on the + * timing arcs that have changed. + */ + void update_timing_info(); + /** * @brief Returns whether or not the pre-cluster timing manager was * initialized (i.e. timing information can be computed). @@ -103,6 +128,16 @@ class PreClusterTimingManager { return *timing_info_; } + /** + * @brief Get a pointer to the setup timing info. This may be needed when + * a base class method is used by the timing info class. + */ + std::shared_ptr get_timing_info_ptr() { + VTR_ASSERT_SAFE_MSG(is_valid_, + "Timing manager has not been initialized"); + return timing_info_; + } + private: /// @brief A valid flag used to signify if the pre-cluster timing manager /// class has been initialized or not. For example, if the flow is @@ -116,4 +151,10 @@ class PreClusterTimingManager { /// @brief The setup timing info used for getting the timing of edges /// in the timing graph. std::shared_ptr timing_info_; + + /// @brief Delays of all timing arcs in the atom netlist. This is used to + /// hold the estimated delays of all atom connections so that the + /// delay calculator can query them when Tatum performs a timing analysis. + /// Here, we use sink pins as unique identifiers for the the timing arc. + vtr::vector timing_arc_delays_; }; diff --git a/vpr/src/timing/RoutingDelayCalculator.h b/vpr/src/timing/RoutingDelayCalculator.h index 2de0f3af1a0..dec729c9bb2 100644 --- a/vpr/src/timing/RoutingDelayCalculator.h +++ b/vpr/src/timing/RoutingDelayCalculator.h @@ -1,8 +1,5 @@ -#ifndef ROUTING_DELAY_CALCULATOR_H -#define ROUTING_DELAY_CALCULATOR_H +#pragma once #include "PostClusterDelayCalculator.h" using RoutingDelayCalculator = PostClusterDelayCalculator; - -#endif diff --git a/vpr/src/timing/VprTimingGraphResolver.h b/vpr/src/timing/VprTimingGraphResolver.h index 0f63c3d9370..3a1d74054c1 100644 --- a/vpr/src/timing/VprTimingGraphResolver.h +++ b/vpr/src/timing/VprTimingGraphResolver.h @@ -1,5 +1,4 @@ -#ifndef VRP_TIMING_GRAPH_NAME_RESOLVER_H -#define VRP_TIMING_GRAPH_NAME_RESOLVER_H +#pragma once #include "tatum/TimingGraphNameResolver.hpp" #include "atom_netlist_fwd.h" @@ -43,5 +42,3 @@ class VprTimingGraphResolver : public tatum::TimingGraphNameResolver { ///@brief contains information about the placement of clustered blocks. const BlkLocRegistry& blk_loc_registry_; }; - -#endif diff --git a/vpr/src/timing/atom_delay_calc.h b/vpr/src/timing/atom_delay_calc.h index 28d303815d9..e1e3c96dbef 100644 --- a/vpr/src/timing/atom_delay_calc.h +++ b/vpr/src/timing/atom_delay_calc.h @@ -1,9 +1,7 @@ -#ifndef VPR_ATOM_DELAY_CALC_H -#define VPR_ATOM_DELAY_CALC_H +#pragma once #include "atom_netlist.h" #include "atom_lookup.h" -#include "vtr_hash.h" #include "DelayType.h" //Delay Calculator for timing edges which are internal to atoms @@ -24,5 +22,3 @@ class AtomDelayCalc { }; #include "atom_delay_calc.inl" - -#endif diff --git a/vpr/src/timing/clb_delay_calc.h b/vpr/src/timing/clb_delay_calc.h index c84a2d736de..44679fd47e9 100644 --- a/vpr/src/timing/clb_delay_calc.h +++ b/vpr/src/timing/clb_delay_calc.h @@ -1,6 +1,9 @@ -#ifndef VPR_CLB_DELAY_CALC_H -#define VPR_CLB_DELAY_CALC_H +#pragma once + +#include "clustered_netlist_fwd.h" #include "DelayType.h" +#include "physical_types.h" +#include "vpr_utils.h" //Delay Calculator for routing internal to a clustered logic block class ClbDelayCalc { @@ -28,5 +31,3 @@ class ClbDelayCalc { }; #include "clb_delay_calc.inl" - -#endif diff --git a/vpr/src/timing/concrete_timing_info.cpp b/vpr/src/timing/concrete_timing_info.cpp index 02f141ca973..fd83cdddc33 100644 --- a/vpr/src/timing/concrete_timing_info.cpp +++ b/vpr/src/timing/concrete_timing_info.cpp @@ -1,6 +1,5 @@ #include "vtr_log.h" -#include "timing_info.h" #include "concrete_timing_info.h" void warn_unconstrained(std::shared_ptr analyzer) { diff --git a/vpr/src/timing/concrete_timing_info.h b/vpr/src/timing/concrete_timing_info.h index d534e597c70..7e4d0a5dd58 100644 --- a/vpr/src/timing/concrete_timing_info.h +++ b/vpr/src/timing/concrete_timing_info.h @@ -1,15 +1,13 @@ -#ifndef VPR_CONCRETE_TIMING_INFO_H -#define VPR_CONCRETE_TIMING_INFO_H +#pragma once -#include "vtr_log.h" +#include "tatum/analyzer_factory.hpp" +#include "tatum/analyzers/SetupTimingAnalyzer.hpp" +#include "tatum/timing_paths.hpp" #include "timing_info.h" #include "timing_util.h" -#include "vpr_error.h" #include "slack_evaluation.h" #include "globals.h" -#include "tatum/report/graphviz_dot_writer.hpp" - void warn_unconstrained(std::shared_ptr analyzer); //NOTE: These classes should not be used directly but created with the @@ -506,5 +504,3 @@ std::unique_ptr make_setup_hold_timing_info(std::shared_ptr inline std::unique_ptr make_constant_timing_info(const float criticality) { return std::make_unique(criticality); } - -#endif diff --git a/vpr/src/timing/net_delay.cpp b/vpr/src/timing/net_delay.cpp index 5420c197769..1f2b9bd509a 100644 --- a/vpr/src/timing/net_delay.cpp +++ b/vpr/src/timing/net_delay.cpp @@ -1,9 +1,5 @@ #include -#include "vtr_memory.h" -#include "vtr_log.h" - -#include "vpr_types.h" #include "vpr_error.h" #include "globals.h" diff --git a/vpr/src/timing/net_delay.h b/vpr/src/timing/net_delay.h index f5a1727cd5c..12990617f66 100644 --- a/vpr/src/timing/net_delay.h +++ b/vpr/src/timing/net_delay.h @@ -1,10 +1,6 @@ -#ifndef NET_DELAY_H -#define NET_DELAY_H +#pragma once -#include "vtr_memory.h" -#include "vtr_vector.h" +#include "netlist.h" #include "vpr_net_pins_matrix.h" void load_net_delay_from_routing(const Netlist<>& net_list, NetPinsMatrix& net_delay); - -#endif diff --git a/vpr/src/timing/read_sdc.h b/vpr/src/timing/read_sdc.h index bae43206952..7241a29474b 100644 --- a/vpr/src/timing/read_sdc.h +++ b/vpr/src/timing/read_sdc.h @@ -1,5 +1,5 @@ -#ifndef VPR_READ_SDC_H -#define VPR_READ_SDC_H +#pragma once + #include #include "tatum/TimingConstraintsFwd.hpp" @@ -16,5 +16,3 @@ std::unique_ptr read_sdc(const t_timing_inf& timing_in const AtomLookup& lookup, const LogicalModels& models, tatum::TimingGraph& timing_graph); - -#endif diff --git a/vpr/src/timing/slack_evaluation.h b/vpr/src/timing/slack_evaluation.h index 3cd75b6ce8b..e6539082b0d 100644 --- a/vpr/src/timing/slack_evaluation.h +++ b/vpr/src/timing/slack_evaluation.h @@ -1,11 +1,11 @@ #pragma once #include -#include #include "atom_netlist_fwd.h" #include "DomainPair.h" -#include "tatum/timing_analyzers.hpp" +#include "tatum/analyzers/HoldTimingAnalyzer.hpp" +#include "tatum/analyzers/SetupTimingAnalyzer.hpp" #include "vtr_vector.h" /* diff --git a/vpr/src/timing/timing_fail_error.cpp b/vpr/src/timing/timing_fail_error.cpp index 3543f0a47ba..23b0a6d79b2 100644 --- a/vpr/src/timing/timing_fail_error.cpp +++ b/vpr/src/timing/timing_fail_error.cpp @@ -1,12 +1,4 @@ -#include -#include - -#include "vtr_log.h" -#include "vtr_assert.h" -#include "vtr_math.h" - #include "globals.h" -#include "timing_util.h" #include "timing_fail_error.h" /* Sets terminate_if_timing_fails in the timing context if the user has indicated diff --git a/vpr/src/timing/timing_fail_error.h b/vpr/src/timing/timing_fail_error.h index 22992312c76..b86452f97e1 100644 --- a/vpr/src/timing/timing_fail_error.h +++ b/vpr/src/timing/timing_fail_error.h @@ -1,13 +1,4 @@ -#ifndef VPR_FAIL_ERROR_H -#define VPR_FAIL_ERROR_H -#include - -#include "timing_info_fwd.h" -#include "tatum/analyzer_factory.hpp" -#include "tatum/timing_paths.hpp" -#include "timing_util.h" +#pragma once /* Represents whether or not VPR should fail if timing constraints aren't met. */ void set_terminate_if_timing_fails(bool cmd_opt_terminate_if_timing_fails); - -#endif diff --git a/vpr/src/timing/timing_graph_builder.h b/vpr/src/timing/timing_graph_builder.h index 40b571a8bb1..0e3f1c470e8 100644 --- a/vpr/src/timing/timing_graph_builder.h +++ b/vpr/src/timing/timing_graph_builder.h @@ -1,3 +1,5 @@ +#pragma once + #include #include "tatum/TimingGraphFwd.hpp" diff --git a/vpr/src/timing/timing_info.h b/vpr/src/timing/timing_info.h index fbd21cbf1bc..21bfb8145dc 100644 --- a/vpr/src/timing/timing_info.h +++ b/vpr/src/timing/timing_info.h @@ -1,11 +1,17 @@ -#ifndef VPR_TIMING_INFO_H -#define VPR_TIMING_INFO_H +#pragma once + #include +#include "atom_netlist_fwd.h" +#include "tatum/TimingConstraints.hpp" +#include "tatum/analyzers/HoldTimingAnalyzer.hpp" +#include "tatum/analyzers/SetupHoldTimingAnalyzer.hpp" +#include "tatum/analyzers/SetupTimingAnalyzer.hpp" +#include "tatum/analyzers/TimingAnalyzer.hpp" +#include "tatum/delay_calc/DelayCalculator.hpp" +#include "tatum/report/TimingPath.hpp" #include "timing_info_fwd.h" -#include "tatum/analyzer_factory.hpp" -#include "tatum/timing_paths.hpp" -#include "timing_util.h" +#include "vtr_range.h" //Generic interface which provides functionality to update (but not //access) timing information. @@ -138,5 +144,3 @@ class SetupHoldTimingInfo : public SetupTimingInfo, public HoldTimingInfo { public: virtual std::shared_ptr setup_hold_analyzer() const = 0; }; - -#endif diff --git a/vpr/src/timing/timing_info_fwd.h b/vpr/src/timing/timing_info_fwd.h index 5a8a07ddb33..4a72707cb0d 100644 --- a/vpr/src/timing/timing_info_fwd.h +++ b/vpr/src/timing/timing_info_fwd.h @@ -1,9 +1,6 @@ -#ifndef VPR_TIMING_INFO_FWD_H -#define VPR_TIMING_INFO_FWD_H +#pragma once class TimingInfo; class SetupTimingInfo; class HoldTimingInfo; class SetupHoldTimingInfo; - -#endif diff --git a/vpr/src/timing/timing_util.cpp b/vpr/src/timing/timing_util.cpp index 94191667499..77fa7d151cd 100644 --- a/vpr/src/timing/timing_util.cpp +++ b/vpr/src/timing/timing_util.cpp @@ -2,12 +2,12 @@ #include #include +#include "tatum/timing_paths.hpp" #include "vtr_log.h" #include "vtr_assert.h" #include "vtr_math.h" #include "globals.h" -#include "timing_fail_error.h" #include "timing_info.h" #include "timing_util.h" diff --git a/vpr/src/timing/timing_util.h b/vpr/src/timing/timing_util.h index e0d011214ba..86c32035fc8 100644 --- a/vpr/src/timing/timing_util.h +++ b/vpr/src/timing/timing_util.h @@ -1,19 +1,18 @@ -#ifndef VPR_TIMING_UTIL_H -#define VPR_TIMING_UTIL_H +#pragma once + #include #include #include "netlist_fwd.h" -#include "tatum/timing_analyzers.hpp" #include "tatum/TimingConstraints.hpp" -#include "tatum/timing_paths.hpp" #include "histogram.h" +#include "tatum/analyzers/HoldTimingAnalyzer.hpp" +#include "tatum/analyzers/SetupTimingAnalyzer.hpp" +#include "tatum/report/TimingPath.hpp" #include "timing_info_fwd.h" #include "DomainPair.h" -#include "globals.h" -#include "vpr_utils.h" #include "clustered_netlist_utils.h" double sec_to_nanosec(double seconds); @@ -154,5 +153,3 @@ struct TimingStats { //Write a useful summary of timing information to JSON file void write_setup_timing_summary(std::string_view timing_summary_filename, const TimingStats& stats); - -#endif diff --git a/vpr/src/util/hash.cpp b/vpr/src/util/hash.cpp index 96271bfe996..408f7fde8bb 100644 --- a/vpr/src/util/hash.cpp +++ b/vpr/src/util/hash.cpp @@ -1,7 +1,6 @@ #include #include -#include "vtr_memory.h" #include "vtr_log.h" #include "hash.h" diff --git a/vpr/src/util/hash.h b/vpr/src/util/hash.h index d37cbf51733..bb328ffc001 100644 --- a/vpr/src/util/hash.h +++ b/vpr/src/util/hash.h @@ -1,5 +1,7 @@ +#pragma once + #define HASHSIZE 5000001 -#include + #include struct t_hash { diff --git a/vpr/src/util/lazy_pop_unique_priority_queue.h b/vpr/src/util/lazy_pop_unique_priority_queue.h index d375daf19cd..5bf88f2cef2 100644 --- a/vpr/src/util/lazy_pop_unique_priority_queue.h +++ b/vpr/src/util/lazy_pop_unique_priority_queue.h @@ -1,3 +1,4 @@ +#pragma once /** * @file * @author Rongbo Zhang @@ -20,8 +21,6 @@ * LazyPopUniquePriorityQueue::contains(): Returns true if the key is in the queue, false otherwise. */ -#pragma once - #include #include #include diff --git a/vpr/src/util/vpr_net_pins_matrix.h b/vpr/src/util/vpr_net_pins_matrix.h index 585e7f3873a..db846da42c4 100644 --- a/vpr/src/util/vpr_net_pins_matrix.h +++ b/vpr/src/util/vpr_net_pins_matrix.h @@ -1,7 +1,6 @@ -#ifndef VPR_NET_PINS_MATRIX_H -#define VPR_NET_PINS_MATRIX_H +#pragma once -#include "atom_netlist_fwd.h" +#include "atom_netlist.h" #include "clustered_netlist.h" #include "clustered_netlist_fwd.h" #include "netlist_fwd.h" @@ -45,5 +44,3 @@ NetPinsMatrix make_net_pins_matrix(const Netlist<>& nlist, T default_value = return NetPinsMatrix(nlist.nets().size(), pins_in_net, default_value); } - -#endif diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index bbb57f7c9f1..319262f9a7b 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -40,6 +40,8 @@ static AtomPinId find_atom_pin_for_pb_route_id(ClusterBlockId clb, int pb_route_ static bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::regex& blif_model_regex); static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::regex& blif_model_regex); +static t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type); +static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type); /******************** Subroutine definitions *********************************/ @@ -1031,7 +1033,7 @@ static void load_pb_graph_pin_lookup_from_index_rec(t_pb_graph_pin** pb_graph_pi } /* Create a lookup that returns a pb_graph_pin pointer given the pb_graph_pin index */ -t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type) { +static t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type) { t_pb_graph_pin** pb_graph_pin_lookup_from_type = nullptr; t_pb_graph_node* pb_graph_head = type->pb_graph_head; @@ -1059,7 +1061,7 @@ t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_t } /* Free pb_graph_pin lookup array */ -void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type) { +static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type) { if (pb_graph_pin_lookup_from_type == nullptr) { return; } @@ -1739,6 +1741,41 @@ RRNodeId get_class_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, return rr_spatial_lookup.find_node(layer, i, j, node_type, class_physical_num); } +RRNodeId get_atom_pin_rr_node_id(AtomPinId atom_pin_id) { + auto& atom_nlist = g_vpr_ctx.atom().netlist(); + auto& atom_lookup = g_vpr_ctx.atom().lookup(); + auto& place_ctx = g_vpr_ctx.placement(); + auto& device_ctx = g_vpr_ctx.device(); + + /* + * To get the RRNodeId for an atom pin, we need to: + * 1. Find the atom block that the pin belongs to + * 2. Find the cluster block that the atom block is a part of + * 3. Find the physical tile that the cluster block is located on + * 4. Find the physical pin number of the atom pin (corresponds to ptc number of the RR node) + * 5. Call get_pin_rr_node_id to get the RRNodeId for the pin + */ + + AtomBlockId atom_blk_id = atom_nlist.pin_block(atom_pin_id); + ClusterBlockId clb_blk_id = atom_lookup.atom_clb(atom_blk_id); + + t_pl_loc clb_blk_loc = place_ctx.block_locs()[clb_blk_id].loc; + + t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({clb_blk_loc.x, clb_blk_loc.y, clb_blk_loc.layer}); + + const t_pb_graph_pin* atom_pb_pin = atom_lookup.atom_pin_pb_graph_pin(atom_pin_id); + int pin_physical_num = physical_tile->pb_pin_to_pin_num.at(atom_pb_pin); + + RRNodeId rr_node_id = get_pin_rr_node_id(device_ctx.rr_graph.node_lookup(), + physical_tile, + clb_blk_loc.layer, + clb_blk_loc.x, + clb_blk_loc.y, + pin_physical_num); + + return rr_node_id; +} + bool node_in_same_physical_tile(RRNodeId node_first, RRNodeId node_second) { const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 525e4bd9626..8881dc40bde 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -187,9 +187,7 @@ t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* m /// pb_graph_node. t_pb_graph_pin* get_pb_graph_node_pin_from_pb_graph_node(t_pb_graph_node* pb_graph_node, int ipin); t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(ClusterBlockId iblock, int ipin); -t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type); vtr::vector alloc_and_load_pin_id_to_pb_mapping(); -void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type); void free_pin_id_to_pb_mapping(vtr::vector& pin_id_to_pb_mapping); std::tuple get_cluster_blk_physical_spec(ClusterBlockId cluster_blk_id); @@ -255,6 +253,14 @@ RRNodeId get_pin_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, const int root_j, int pin_physical_num); +/** + * @brief Returns the RR node ID for the given atom pin ID. + * **Warning**: This function should be called only if flat-router is enabled, + * since, otherwise, the routing resources inside clusters are not added to the RR graph. + * @param atom_pin_id The atom pin ID. + */ +RRNodeId get_atom_pin_rr_node_id(AtomPinId atom_pin_id); + RRNodeId get_class_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, t_physical_tile_type_ptr physical_tile, const int layer, diff --git a/vpr/test/test_ap_primitive_vector.cpp b/vpr/test/test_ap_primitive_vector.cpp index d3455d7cfe7..074ba627b8d 100644 --- a/vpr/test/test_ap_primitive_vector.cpp +++ b/vpr/test/test_ap_primitive_vector.cpp @@ -15,29 +15,36 @@ namespace { TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { + PrimitiveVectorDim dim_0 = static_cast(0); + PrimitiveVectorDim dim_1 = static_cast(1); + PrimitiveVectorDim dim_2 = static_cast(2); + PrimitiveVectorDim dim_3 = static_cast(3); + PrimitiveVectorDim dim_4 = static_cast(4); + PrimitiveVectorDim dim_10 = static_cast(10); + PrimitiveVectorDim dim_42 = static_cast(42); SECTION("Test getters and setters") { PrimitiveVector vec; // Default value in the vector should be zero. - REQUIRE(vec.get_dim_val(42) == 0.f); + REQUIRE(vec.get_dim_val(dim_42) == 0.f); // Able to set a random dim to a value. - vec.set_dim_val(42, 2.f); - REQUIRE(vec.get_dim_val(42) == 2.f); + vec.set_dim_val(dim_42, 2.f); + REQUIRE(vec.get_dim_val(dim_42) == 2.f); // Able to add a value to a dim. - vec.add_val_to_dim(10.f, 42); - REQUIRE(vec.get_dim_val(42) == 12.f); + vec.add_val_to_dim(10.f, dim_42); + REQUIRE(vec.get_dim_val(dim_42) == 12.f); // Try a negative number. - vec.set_dim_val(0, -2.f); - REQUIRE(vec.get_dim_val(0) == -2.f); - vec.add_val_to_dim(-4.f, 42); - REQUIRE(vec.get_dim_val(42) == 8.f); + vec.set_dim_val(dim_0, -2.f); + REQUIRE(vec.get_dim_val(dim_0) == -2.f); + vec.add_val_to_dim(-4.f, dim_42); + REQUIRE(vec.get_dim_val(dim_42) == 8.f); // Try setting to zero. - vec.set_dim_val(42, 0.f); - REQUIRE(vec.get_dim_val(42) == 0.f); + vec.set_dim_val(dim_42, 0.f); + REQUIRE(vec.get_dim_val(dim_42) == 0.f); // Test clear method. vec.clear(); - REQUIRE(vec.get_dim_val(42) == 0.f); - REQUIRE(vec.get_dim_val(0) == 0.f); + REQUIRE(vec.get_dim_val(dim_42) == 0.f); + REQUIRE(vec.get_dim_val(dim_0) == 0.f); } SECTION("Test operators") { PrimitiveVector vec1, vec2; @@ -45,15 +52,15 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { // Equality: // Two empty vectors should be equal. REQUIRE(vec1 == vec2); - vec1.set_dim_val(0, 0.f); - vec1.set_dim_val(1, 1.f); - vec1.set_dim_val(2, 2.f); + vec1.set_dim_val(dim_0, 0.f); + vec1.set_dim_val(dim_1, 1.f); + vec1.set_dim_val(dim_2, 2.f); // Compare with self. REQUIRE(vec1 == vec1); // Set vec2 indirectly to vec 1 - vec2.set_dim_val(0, 0.f); - vec2.set_dim_val(1, 1.f); - vec2.set_dim_val(2, 2.f); + vec2.set_dim_val(dim_0, 0.f); + vec2.set_dim_val(dim_1, 1.f); + vec2.set_dim_val(dim_2, 2.f); REQUIRE(vec1 == vec2); // Check commutivity REQUIRE(vec2 == vec1); @@ -62,97 +69,97 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { REQUIRE(vec1 == vec3); // Check strange corner-case where 1 vec has more dims set than another. PrimitiveVector vec4 = vec1; - vec4.set_dim_val(10, 100.f); + vec4.set_dim_val(dim_10, 100.f); REQUIRE(!(vec4 == vec1)); REQUIRE(!(vec1 == vec4)); // Inequality: // Set vec2 to not be equal - vec2.set_dim_val(0, 3.f); + vec2.set_dim_val(dim_0, 3.f); REQUIRE(!(vec1 == vec2)); REQUIRE(vec1 != vec2); REQUIRE(vec2 != vec1); - vec2.set_dim_val(0, 0.f); - vec2.set_dim_val(3, 3.f); + vec2.set_dim_val(dim_0, 0.f); + vec2.set_dim_val(dim_3, 3.f); REQUIRE(!(vec1 == vec2)); REQUIRE(vec1 != vec2); // Set a random dim to 0. By default all dims are 0. vec2 = vec1; - vec2.set_dim_val(10, 0.f); + vec2.set_dim_val(dim_10, 0.f); REQUIRE(vec1 == vec2); // Accumulation: vec1.clear(); REQUIRE(vec1 == PrimitiveVector()); - vec1.set_dim_val(0, 0.f); - vec1.set_dim_val(1, 1.f); - vec1.set_dim_val(2, 2.f); + vec1.set_dim_val(dim_0, 0.f); + vec1.set_dim_val(dim_1, 1.f); + vec1.set_dim_val(dim_2, 2.f); vec2.clear(); - vec2.set_dim_val(0, 3.f); - vec2.set_dim_val(1, 4.f); - vec2.set_dim_val(2, 5.f); + vec2.set_dim_val(dim_0, 3.f); + vec2.set_dim_val(dim_1, 4.f); + vec2.set_dim_val(dim_2, 5.f); vec1 += vec2; PrimitiveVector res; - res.set_dim_val(0, 3.f); - res.set_dim_val(1, 5.f); - res.set_dim_val(2, 7.f); + res.set_dim_val(dim_0, 3.f); + res.set_dim_val(dim_1, 5.f); + res.set_dim_val(dim_2, 7.f); REQUIRE(vec1 == res); // accumulate different dims vec1.clear(); - vec1.set_dim_val(0, 10.f); + vec1.set_dim_val(dim_0, 10.f); vec2.clear(); - vec2.set_dim_val(1, 20.f); + vec2.set_dim_val(dim_1, 20.f); vec1 += vec2; - REQUIRE(vec1.get_dim_val(0) == 10.f); - REQUIRE(vec1.get_dim_val(1) == 20.f); + REQUIRE(vec1.get_dim_val(dim_0) == 10.f); + REQUIRE(vec1.get_dim_val(dim_1) == 20.f); // Subtraction: vec1 -= vec2; - REQUIRE(vec1.get_dim_val(0) == 10.f); - REQUIRE(vec1.get_dim_val(1) == 0.f); + REQUIRE(vec1.get_dim_val(dim_0) == 10.f); + REQUIRE(vec1.get_dim_val(dim_1) == 0.f); res = vec1; res -= vec2; REQUIRE(vec1 - vec2 == res); // Element-wise multiplication: vec1.clear(); - vec1.set_dim_val(0, 0.f); - vec1.set_dim_val(1, 1.f); - vec1.set_dim_val(2, 2.f); + vec1.set_dim_val(dim_0, 0.f); + vec1.set_dim_val(dim_1, 1.f); + vec1.set_dim_val(dim_2, 2.f); vec1 *= 2.f; - REQUIRE(vec1.get_dim_val(0) == 0.f); - REQUIRE(vec1.get_dim_val(1) == 2.f); - REQUIRE(vec1.get_dim_val(2) == 4.f); + REQUIRE(vec1.get_dim_val(dim_0) == 0.f); + REQUIRE(vec1.get_dim_val(dim_1) == 2.f); + REQUIRE(vec1.get_dim_val(dim_2) == 4.f); } SECTION("Test comparitors") { PrimitiveVector vec1, vec2; // empty vector. - vec2.set_dim_val(0, 10.f); - vec2.set_dim_val(1, 20.f); + vec2.set_dim_val(dim_0, 10.f); + vec2.set_dim_val(dim_1, 20.f); REQUIRE(vec1 < vec2); // 1D case. vec1.clear(); vec2.clear(); - vec1.set_dim_val(0, 1.f); - vec2.set_dim_val(0, 2.f); + vec1.set_dim_val(dim_0, 1.f); + vec2.set_dim_val(dim_0, 2.f); REQUIRE(vec1 < vec2); - vec1.set_dim_val(0, 2.f); + vec1.set_dim_val(dim_0, 2.f); REQUIRE(!(vec1 < vec2)); - vec1.set_dim_val(0, 3.f); + vec1.set_dim_val(dim_0, 3.f); REQUIRE(!(vec1 < vec2)); // 2D case. vec1.clear(); vec2.clear(); - vec1.set_dim_val(0, 1.f); - vec1.set_dim_val(1, 1.f); - vec2.set_dim_val(0, 2.f); - vec2.set_dim_val(1, 2.f); + vec1.set_dim_val(dim_0, 1.f); + vec1.set_dim_val(dim_1, 1.f); + vec2.set_dim_val(dim_0, 2.f); + vec2.set_dim_val(dim_1, 2.f); REQUIRE(vec1 < vec2); // NOTE: This is somewhat special. Since 1 dimension is less for vec1 // it should still be less. - vec1.set_dim_val(0, 3.f); + vec1.set_dim_val(dim_0, 3.f); REQUIRE(vec1 < vec2); - vec1.set_dim_val(1, 3.f); + vec1.set_dim_val(dim_1, 3.f); REQUIRE(!(vec1 < vec2)); } SECTION("Test methods") { @@ -161,14 +168,14 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { // The default vector is zero. REQUIRE(vec1.is_zero()); // Setting an element of the zero-vector to 0 is still a zero vector. - vec1.set_dim_val(0, 0.f); + vec1.set_dim_val(dim_0, 0.f); REQUIRE(vec1.is_zero()); - vec1.set_dim_val(42, 0.f); + vec1.set_dim_val(dim_42, 0.f); REQUIRE(vec1.is_zero()); - vec1.set_dim_val(42, 1.f); + vec1.set_dim_val(dim_42, 1.f); REQUIRE(!vec1.is_zero()); REQUIRE(vec1.is_non_zero()); - vec1.set_dim_val(42, 0.f); + vec1.set_dim_val(dim_42, 0.f); REQUIRE(vec1.is_zero()); REQUIRE(!vec1.is_non_zero()); @@ -178,49 +185,49 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { vec1.relu(); REQUIRE(vec1.is_zero()); // Relu of a negative vector is the zero vector. - vec1.set_dim_val(0, -1.f); - vec1.set_dim_val(1, -2.f); + vec1.set_dim_val(dim_0, -1.f); + vec1.set_dim_val(dim_1, -2.f); vec1.relu(); REQUIRE(vec1.is_zero()); // Relu of a positive vector is the same vector. - vec1.set_dim_val(0, 1.f); - vec1.set_dim_val(1, 2.f); + vec1.set_dim_val(dim_0, 1.f); + vec1.set_dim_val(dim_1, 2.f); PrimitiveVector vec2 = vec1; vec1.relu(); REQUIRE(vec1 == vec2); // Standard Relu test. - vec1.set_dim_val(0, 1.f); - vec1.set_dim_val(1, 0.f); - vec1.set_dim_val(2, -4.f); - vec1.set_dim_val(3, 2.f); - vec1.set_dim_val(4, -5.f); + vec1.set_dim_val(dim_0, 1.f); + vec1.set_dim_val(dim_1, 0.f); + vec1.set_dim_val(dim_2, -4.f); + vec1.set_dim_val(dim_3, 2.f); + vec1.set_dim_val(dim_4, -5.f); vec2 = vec1; vec1.relu(); - vec2.set_dim_val(2, 0.f); - vec2.set_dim_val(4, 0.f); + vec2.set_dim_val(dim_2, 0.f); + vec2.set_dim_val(dim_4, 0.f); REQUIRE(vec1 == vec2); // is_non_negative: vec1.clear(); // The zero vector is non-negative. REQUIRE(vec1.is_non_negative()); - vec1.set_dim_val(0, 0.f); + vec1.set_dim_val(dim_0, 0.f); REQUIRE(vec1.is_non_negative()); // Postive vector is non-negative - vec1.set_dim_val(0, 1.f); + vec1.set_dim_val(dim_0, 1.f); REQUIRE(vec1.is_non_negative()); - vec1.set_dim_val(1, 2.f); + vec1.set_dim_val(dim_1, 2.f); REQUIRE(vec1.is_non_negative()); // Negative vector is negative. vec2.clear(); - vec2.set_dim_val(0, -1.f); + vec2.set_dim_val(dim_0, -1.f); REQUIRE(!vec2.is_non_negative()); - vec2.set_dim_val(1, -2.f); + vec2.set_dim_val(dim_1, -2.f); REQUIRE(!vec2.is_non_negative()); // Mixed positive and negative vector is not non-negative. - vec2.set_dim_val(1, 2.f); + vec2.set_dim_val(dim_1, 2.f); REQUIRE(!vec2.is_non_negative()); - vec2.set_dim_val(0, 1.f); + vec2.set_dim_val(dim_0, 1.f); REQUIRE(vec1.is_non_negative()); // manhattan_norm: @@ -228,12 +235,12 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { // Manhatten norm of the zero vector is zero. REQUIRE(vec1.manhattan_norm() == 0.f); // Manhatten norm of a non-negative vector is the sum of its dims. - vec1.set_dim_val(0, 1.f); + vec1.set_dim_val(dim_0, 1.f); REQUIRE(vec1.manhattan_norm() == 1.f); - vec1.set_dim_val(1, 2.f); - vec1.set_dim_val(2, 3.f); - vec1.set_dim_val(3, 4.f); - vec1.set_dim_val(4, 5.f); + vec1.set_dim_val(dim_1, 2.f); + vec1.set_dim_val(dim_2, 3.f); + vec1.set_dim_val(dim_3, 4.f); + vec1.set_dim_val(dim_4, 5.f); REQUIRE(vec1.manhattan_norm() == 15.f); // Manhatten norm of a negative vector is the sum of the absolute value // of its dims. @@ -246,12 +253,12 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { // Sum of the zero vector is zero. REQUIRE(vec1.sum() == 0.f); // Sum of a non-negative vector is the sum of its dims. - vec1.set_dim_val(0, 1.f); + vec1.set_dim_val(dim_0, 1.f); REQUIRE(vec1.sum() == 1.f); - vec1.set_dim_val(1, 2.f); - vec1.set_dim_val(2, 3.f); - vec1.set_dim_val(3, 4.f); - vec1.set_dim_val(4, 5.f); + vec1.set_dim_val(dim_1, 2.f); + vec1.set_dim_val(dim_2, 3.f); + vec1.set_dim_val(dim_3, 4.f); + vec1.set_dim_val(dim_4, 5.f); REQUIRE(vec1.sum() == 15.f); // Sum of a negative vector is the opposite of the sum of the absolute // value of its dims. @@ -262,33 +269,33 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { // Projection: // Basic example: vec1.clear(); - vec1.set_dim_val(0, 12.f); - vec1.set_dim_val(1, 32.f); - vec1.set_dim_val(2, 8.f); - vec1.set_dim_val(3, 2.f); + vec1.set_dim_val(dim_0, 12.f); + vec1.set_dim_val(dim_1, 32.f); + vec1.set_dim_val(dim_2, 8.f); + vec1.set_dim_val(dim_3, 2.f); vec2.clear(); - vec2.set_dim_val(0, 2.f); - vec2.set_dim_val(2, 2.f); + vec2.set_dim_val(dim_0, 2.f); + vec2.set_dim_val(dim_2, 2.f); vec1.project(vec2); PrimitiveVector res; - res.set_dim_val(0, 12.f); - res.set_dim_val(2, 8.f); + res.set_dim_val(dim_0, 12.f); + res.set_dim_val(dim_2, 8.f); REQUIRE(vec1 == res); // Projecting onto the same vector again should give the same answer. vec1.project(vec2); REQUIRE(vec1 == res); // Projecting onto the same dimensions should not change the vector. vec1.clear(); - vec1.set_dim_val(0, 1.f); - vec1.set_dim_val(1, 2.f); + vec1.set_dim_val(dim_0, 1.f); + vec1.set_dim_val(dim_1, 2.f); vec2.clear(); - vec2.set_dim_val(0, 3.f); - vec2.set_dim_val(1, 4.f); + vec2.set_dim_val(dim_0, 3.f); + vec2.set_dim_val(dim_1, 4.f); res = vec1; vec1.project(vec2); REQUIRE(vec1 == res); // Projecting onto higher dimensions should not change the vector. - vec2.set_dim_val(2, 5.f); + vec2.set_dim_val(dim_2, 5.f); res = vec1; vec1.project(vec2); REQUIRE(vec1 == res); @@ -301,29 +308,29 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { REQUIRE(res.is_zero()); // The max of a non-negative vector with the zero vector is the non- // negative vector. - vec1.set_dim_val(0, 1.f); + vec1.set_dim_val(dim_0, 1.f); res = PrimitiveVector::max(vec1, vec2); REQUIRE(res == vec1); res = PrimitiveVector::max(vec2, vec1); REQUIRE(res == vec1); // The max of a negative vector with the zero vector is the zero vector. - vec1.set_dim_val(0, -1.f); + vec1.set_dim_val(dim_0, -1.f); res = PrimitiveVector::max(vec1, vec2); REQUIRE(res.is_zero()); // Basic test: // max(<5, 9, 0>, <3, 10, -2>) = <5, 10, 0> vec1.clear(); - vec1.set_dim_val(0, 5.f); - vec1.set_dim_val(1, 9.f); - vec1.set_dim_val(2, 0.f); + vec1.set_dim_val(dim_0, 5.f); + vec1.set_dim_val(dim_1, 9.f); + vec1.set_dim_val(dim_2, 0.f); vec2.clear(); - vec2.set_dim_val(0, 3.f); - vec2.set_dim_val(1, 10.f); - vec2.set_dim_val(2, -2.f); + vec2.set_dim_val(dim_0, 3.f); + vec2.set_dim_val(dim_1, 10.f); + vec2.set_dim_val(dim_2, -2.f); PrimitiveVector golden; - golden.set_dim_val(0, 5.f); - golden.set_dim_val(1, 10.f); - golden.set_dim_val(2, 0.f); + golden.set_dim_val(dim_0, 5.f); + golden.set_dim_val(dim_1, 10.f); + golden.set_dim_val(dim_2, 0.f); res = PrimitiveVector::max(vec1, vec2); REQUIRE(res == golden); res = PrimitiveVector::max(vec2, vec1); @@ -334,53 +341,53 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { PrimitiveVector vec1, vec2; // Subtract value from dimension - vec1.set_dim_val(0, 5.f); - vec1.subtract_val_from_dim(3.f, 0); - REQUIRE(vec1.get_dim_val(0) == 2.f); + vec1.set_dim_val(dim_0, 5.f); + vec1.subtract_val_from_dim(3.f, dim_0); + REQUIRE(vec1.get_dim_val(dim_0) == 2.f); // Element-wise addition operator vec1.clear(); - vec1.set_dim_val(0, 1.f); - vec1.set_dim_val(1, 2.f); + vec1.set_dim_val(dim_0, 1.f); + vec1.set_dim_val(dim_1, 2.f); vec2.clear(); - vec2.set_dim_val(0, 3.f); - vec2.set_dim_val(1, 4.f); + vec2.set_dim_val(dim_0, 3.f); + vec2.set_dim_val(dim_1, 4.f); PrimitiveVector vec_sum = vec1 + vec2; - REQUIRE(vec_sum.get_dim_val(0) == 4.f); - REQUIRE(vec_sum.get_dim_val(1) == 6.f); + REQUIRE(vec_sum.get_dim_val(dim_0) == 4.f); + REQUIRE(vec_sum.get_dim_val(dim_1) == 6.f); // Element-wise division operator vec1.clear(); - vec1.set_dim_val(0, 10.f); - vec1.set_dim_val(1, 20.f); + vec1.set_dim_val(dim_0, 10.f); + vec1.set_dim_val(dim_1, 20.f); vec1 /= 2.f; - REQUIRE(vec1.get_dim_val(0) == 5.f); - REQUIRE(vec1.get_dim_val(1) == 10.f); + REQUIRE(vec1.get_dim_val(dim_0) == 5.f); + REQUIRE(vec1.get_dim_val(dim_1) == 10.f); // Element-wise division operator (const) vec1.clear(); - vec1.set_dim_val(0, 10.f); - vec1.set_dim_val(1, 20.f); + vec1.set_dim_val(dim_0, 10.f); + vec1.set_dim_val(dim_1, 20.f); PrimitiveVector vec_div = vec1 / 2.f; - REQUIRE(vec_div.get_dim_val(0) == 5.f); - REQUIRE(vec_div.get_dim_val(1) == 10.f); + REQUIRE(vec_div.get_dim_val(dim_0) == 5.f); + REQUIRE(vec_div.get_dim_val(dim_1) == 10.f); // Get non-zero dimensions vec1.clear(); - vec1.set_dim_val(0, 1.f); - vec1.set_dim_val(2, 3.f); - std::vector non_zero_dims = vec1.get_non_zero_dims(); - REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 0) != non_zero_dims.end()); - REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 2) != non_zero_dims.end()); - REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 1) == non_zero_dims.end()); + vec1.set_dim_val(dim_0, 1.f); + vec1.set_dim_val(dim_2, 3.f); + std::vector non_zero_dims = vec1.get_non_zero_dims(); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), dim_0) != non_zero_dims.end()); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), dim_2) != non_zero_dims.end()); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), dim_1) == non_zero_dims.end()); // Test orthogonal vectors vec1.clear(); vec2.clear(); - vec1.set_dim_val(0, 1.f); - vec2.set_dim_val(1, 2.f); + vec1.set_dim_val(dim_0, 1.f); + vec2.set_dim_val(dim_1, 2.f); REQUIRE(vec1.are_dims_disjoint(vec2)); - vec2.set_dim_val(0, 3.f); + vec2.set_dim_val(dim_0, 3.f); REQUIRE(!vec1.are_dims_disjoint(vec2)); } } diff --git a/vpr/test/test_bfs_routing.cpp b/vpr/test/test_bfs_routing.cpp index 61d98a3c200..0290bcfc173 100644 --- a/vpr/test/test_bfs_routing.cpp +++ b/vpr/test/test_bfs_routing.cpp @@ -1,5 +1,5 @@ +#include "catch2/matchers/catch_matchers.hpp" #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "bfs_routing.h" diff --git a/vpr/test/test_clustered_netlist.cpp b/vpr/test/test_clustered_netlist.cpp index bcd42988068..c7d5e54214b 100644 --- a/vpr/test/test_clustered_netlist.cpp +++ b/vpr/test/test_clustered_netlist.cpp @@ -1,5 +1,4 @@ #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "clustered_netlist.h" diff --git a/vpr/test/test_edge_groups.cpp b/vpr/test/test_edge_groups.cpp index e8b83741afa..2b6347f34ab 100644 --- a/vpr/test/test_edge_groups.cpp +++ b/vpr/test/test_edge_groups.cpp @@ -1,6 +1,5 @@ #include #include -#include #include #include #include diff --git a/vpr/test/test_flat_placement_types.cpp b/vpr/test/test_flat_placement_types.cpp index b8daaaf61ea..cba4a297780 100644 --- a/vpr/test/test_flat_placement_types.cpp +++ b/vpr/test/test_flat_placement_types.cpp @@ -5,7 +5,7 @@ * @brief Unit tests for flat placement types */ -#include +#include "catch2/catch_approx.hpp" #include "catch2/catch_test_macros.hpp" #include "flat_placement_types.h" diff --git a/vpr/test/test_noc_place_utils.cpp b/vpr/test/test_noc_place_utils.cpp index 515608c1a19..218299cada9 100644 --- a/vpr/test/test_noc_place_utils.cpp +++ b/vpr/test/test_noc_place_utils.cpp @@ -1,10 +1,8 @@ +#include #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "noc_place_utils.h" -#include "noc_routing.h" #include "xy_routing.h" -#include "bfs_routing.h" #include "vtr_math.h" // test parameters diff --git a/vpr/test/test_noc_traffic_flows.cpp b/vpr/test/test_noc_traffic_flows.cpp index ea5806d3261..7d66439ce1d 100644 --- a/vpr/test/test_noc_traffic_flows.cpp +++ b/vpr/test/test_noc_traffic_flows.cpp @@ -2,8 +2,6 @@ #include "noc_traffic_flows.h" -#include - #define NUM_OF_ROUTERS 10 namespace { diff --git a/vpr/test/test_odd_even_routing.cpp b/vpr/test/test_odd_even_routing.cpp index 4f00b7d2663..0770d11bc36 100644 --- a/vpr/test/test_odd_even_routing.cpp +++ b/vpr/test/test_odd_even_routing.cpp @@ -1,11 +1,9 @@ #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "odd_even_routing.h" #include "channel_dependency_graph.h" #include -#include namespace { diff --git a/vpr/test/test_read_xml_noc_traffic_flows_file.cpp b/vpr/test/test_read_xml_noc_traffic_flows_file.cpp index 17aedd6bad1..43986cd9144 100644 --- a/vpr/test/test_read_xml_noc_traffic_flows_file.cpp +++ b/vpr/test/test_read_xml_noc_traffic_flows_file.cpp @@ -1,10 +1,9 @@ +#include "catch2/matchers/catch_matchers.hpp" #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" +#include "globals.h" #include "read_xml_noc_traffic_flows_file.h" -#include - namespace { /* diff --git a/vpr/test/test_server_convertutils.cpp b/vpr/test/test_server_convertutils.cpp index 2006170de46..94a128551d8 100644 --- a/vpr/test/test_server_convertutils.cpp +++ b/vpr/test/test_server_convertutils.cpp @@ -1,7 +1,6 @@ #ifndef NO_SERVER #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "convertutils.h" diff --git a/vpr/test/test_server_taskresolver.cpp b/vpr/test/test_server_taskresolver.cpp index 20c6a865183..87faae2d3b4 100644 --- a/vpr/test/test_server_taskresolver.cpp +++ b/vpr/test/test_server_taskresolver.cpp @@ -1,7 +1,6 @@ #ifndef NO_SERVER #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "taskresolver.h" #include diff --git a/vpr/test/test_server_telegrambuffer.cpp b/vpr/test/test_server_telegrambuffer.cpp index 1b20a3c312f..0ec5d0c4368 100644 --- a/vpr/test/test_server_telegrambuffer.cpp +++ b/vpr/test/test_server_telegrambuffer.cpp @@ -1,7 +1,6 @@ #ifndef NO_SERVER #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "telegrambuffer.h" diff --git a/vpr/test/test_server_telegramoptions.cpp b/vpr/test/test_server_telegramoptions.cpp index e49b684bc72..3b6d16d316b 100644 --- a/vpr/test/test_server_telegramoptions.cpp +++ b/vpr/test/test_server_telegramoptions.cpp @@ -1,7 +1,6 @@ #ifndef NO_SERVER #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "telegramoptions.h" diff --git a/vpr/test/test_server_telegramparser.cpp b/vpr/test/test_server_telegramparser.cpp index a3ac0defa4e..b57cbc72217 100644 --- a/vpr/test/test_server_telegramparser.cpp +++ b/vpr/test/test_server_telegramparser.cpp @@ -3,7 +3,6 @@ #include "telegramparser.h" #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" TEST_CASE("test_server_telegram_parser_base", "[vpr]") { const std::string tdata{R"({"JOB_ID":"7","CMD":"2","OPTIONS":"type1:name1:value1;type2:name2:v a l u e 2;t3:n3:v3","DATA":"some_data...","STATUS":"1"})"}; diff --git a/vpr/test/test_server_zlibutils.cpp b/vpr/test/test_server_zlibutils.cpp index 4b5ecf76c30..87a34553a3c 100644 --- a/vpr/test/test_server_zlibutils.cpp +++ b/vpr/test/test_server_zlibutils.cpp @@ -3,7 +3,6 @@ #include "zlibutils.h" #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" TEST_CASE("test_server_zlib_utils", "[vpr]") { const std::string orig{"This string is going to be compressed now"}; diff --git a/vpr/test/test_setup_noc.cpp b/vpr/test/test_setup_noc.cpp index 31dacd0b5d8..283ef07e3e7 100644 --- a/vpr/test/test_setup_noc.cpp +++ b/vpr/test/test_setup_noc.cpp @@ -1,5 +1,6 @@ #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" +#include "catch2/matchers/catch_matchers.hpp" +#include #include "setup_noc.h" #include "globals.h" diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index 2a4f7a7fc4a..566aec3eb81 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -8,6 +8,7 @@ #include "vpr_api.h" #include "echo_files.h" #include +#include #include namespace { diff --git a/vpr/test/test_vpr_constraints.cpp b/vpr/test/test_vpr_constraints.cpp index 9069cc2ba2f..7a1ffdb96f9 100644 --- a/vpr/test/test_vpr_constraints.cpp +++ b/vpr/test/test_vpr_constraints.cpp @@ -2,8 +2,6 @@ #include "catch2/catch_test_macros.hpp" -#include "vpr_api.h" -#include "globals.h" #include "user_place_constraints.h" #include "partition.h" #include "region.h" diff --git a/vpr/test/test_xy_routing.cpp b/vpr/test/test_xy_routing.cpp index b96331cc83a..ce946b74479 100644 --- a/vpr/test/test_xy_routing.cpp +++ b/vpr/test/test_xy_routing.cpp @@ -1,5 +1,5 @@ +#include "catch2/matchers/catch_matchers.hpp" #include "catch2/catch_test_macros.hpp" -#include "catch2/matchers/catch_matchers_all.hpp" #include "xy_routing.h" diff --git a/vtr_flow/parse/qor_config/qor_fg_parallel_router_fixed_chan_width.txt b/vtr_flow/parse/qor_config/qor_fg_parallel_router_fixed_chan_width.txt new file mode 100644 index 00000000000..7b126fb629e --- /dev/null +++ b/vtr_flow/parse/qor_config/qor_fg_parallel_router_fixed_chan_width.txt @@ -0,0 +1,10 @@ +# This collects QoR data that is interesting for the Fine-Grained Parallel +# Router running on a fixed channel width. + +vpr_status;output.txt;vpr_status=(.*) +crit_path_delay;vpr.out;Critical path: (.*) ns +post_route_wirelength;vpr.out;\s*Total wirelength: (\d+) +total_connection_pathsearch_time;vpr.out;.*Time spent on path search: (.*) seconds. +route_runtime;vpr.out;Routing took (.*) seconds +total_runtime;vpr.out;The entire flow of VPR took (.*) seconds +magic_cookie;vpr.out;Serial number \(magic cookie\) for the routing is: (.*) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt index 594c4215910..8ad73fd83e5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.77 MiB -1 -1 0.12 16500 1 0.10 -1 -1 31836 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63252 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.8 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.6498e-05 2.6643e-05 0.000260655 0.000218319 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00250948 0.00220504 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00176399 0.00169239 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.09 vpr 61.68 MiB -1 -1 0.15 16776 1 0.07 -1 -1 31648 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63160 3 -1 23 23 2 3 5 4 4 16 clb auto 23.2 MiB 0.01 3 12 2 3 7 61.7 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.5504e-05 5.6164e-05 0.000543565 0.00049453 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00311117 0.00290556 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.01 0.00 -1 -1 0.00 0.00221081 0.00210995 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 10 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 22 1 3 3 79 69 1.8363 1.8363 -2.38182 -1.8363 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 5 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 20 1 3 3 79 69 1.6 1.6 -1.8 -1.6 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt index 21dd6c7c148..41ea071cdf6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.3 vpr 255.23 MiB 0.1 37032 -1 -1 1 0.05 -1 -1 34904 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261360 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000265884 0.000243239 0.00748601 0.00452291 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136031 0.00885329 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00736034 0.00605214 +k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.3 vpr 255.23 MiB 0.1 37032 -1 -1 1 0.05 -1 -1 34904 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261360 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000265884 0.000243239 0.00748601 0.00452291 20 30 7 107788 107788 10441.3 652.579 0.66 0.0136031 0.00885329 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00736034 0.00605214 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.17 vpr 257.73 MiB 0.11 45924 -1 -1 1 0.05 -1 -1 34916 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 263920 3 1 23 24 2 8 6 4 4 16 clb auto 102.9 MiB 0.41 17 246.4 MiB 0.03 0 0.571 -8.10303 -0.571 0.557849 0.47 0.000537036 0.000469297 0.00334227 0.00240417 20 19 1 107788 107788 10441.3 652.579 0.66 0.0107944 0.00802791 742 1670 -1 27 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.27775 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471694 0.00381784 k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.06 vpr 254.61 MiB 0.11 36040 -1 -1 1 0.01 -1 -1 32628 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260720 6 2 10 12 2 8 10 4 4 16 clb auto 100.6 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000492001 0.000225939 0.00246091 0.00127477 20 20 1 107788 107788 10441.3 652.579 0.64 0.00559049 0.00306652 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00247934 0.00153705 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt index 68bca7c32e2..ccde9fdd5d3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -1,1025 +1,1025 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 4.14 vpr 64.34 MiB -1 -1 0.19 18372 14 0.23 -1 -1 32420 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 277 309 1 203 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3169 1468 11328 2379 7541 1408 64.3 MiB 0.07 0.00 10.3228 8.34809 -172.958 -8.34809 8.34809 0.24 0.000458019 0.000420977 0.0267514 0.024586 -1 -1 -1 -1 26 4102 40 6.55708e+06 482200 477104. 1650.88 2.34 0.198273 0.175014 21022 109990 -1 3183 21 1415 4612 232092 56261 7.86483 7.86483 -171.918 -7.86483 0 0 585099. 2024.56 0.05 0.08 0.06 -1 -1 0.05 0.0346821 0.0278328 194 183 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 2.82 vpr 64.72 MiB -1 -1 0.19 18608 14 0.26 -1 -1 32020 -1 -1 39 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66272 30 32 272 304 1 192 101 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2855 1327 6211 1127 4807 277 64.7 MiB 0.04 0.00 10.4229 7.81577 -157.932 -7.81577 7.81577 0.25 0.00044353 0.000407199 0.0145115 0.013339 -1 -1 -1 -1 26 3276 21 6.55708e+06 470145 477104. 1650.88 1.03 0.138339 0.121807 21022 109990 -1 2977 18 1223 3838 191983 48311 7.09678 7.09678 -155.225 -7.09678 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0222913 0.0201627 191 184 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 2.79 vpr 64.70 MiB -1 -1 0.14 17972 11 0.20 -1 -1 32500 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 280 312 1 187 103 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2827 1361 6128 1131 4405 592 64.7 MiB 0.04 0.00 8.30478 6.65392 -136.28 -6.65392 6.65392 0.23 0.000444217 0.000407628 0.0153173 0.0140577 -1 -1 -1 -1 28 3532 22 6.55708e+06 470145 500653. 1732.36 1.13 0.141601 0.124216 21310 115450 -1 2893 19 1295 4984 238971 59050 5.81978 5.81978 -132.978 -5.81978 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.022413 0.0200969 193 186 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 2.40 vpr 64.21 MiB -1 -1 0.16 18368 12 0.29 -1 -1 32700 -1 -1 40 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 29 32 275 307 1 194 101 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2959 1244 8326 1689 5934 703 64.2 MiB 0.05 0.00 9.98698 7.42963 -136.806 -7.42963 7.42963 0.33 0.000442208 0.000402322 0.0186625 0.0171344 -1 -1 -1 -1 22 3463 27 6.55708e+06 482200 420624. 1455.45 0.62 0.111711 0.100638 20158 92377 -1 3149 20 1718 5783 304181 76974 6.67344 6.67344 -140.022 -6.67344 0 0 500653. 1732.36 0.02 0.08 0.05 -1 -1 0.02 0.0253416 0.0228426 200 190 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 2.59 vpr 64.82 MiB -1 -1 0.18 18364 13 0.24 -1 -1 31812 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 302 334 1 214 106 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3277 1472 9856 1982 7031 843 64.8 MiB 0.05 0.00 10.9395 7.98333 -168.064 -7.98333 7.98333 0.23 0.000470534 0.000431442 0.0218695 0.0200206 -1 -1 -1 -1 26 3770 18 6.55708e+06 506310 477104. 1650.88 0.93 0.134458 0.118969 21022 109990 -1 3230 16 1274 3900 187211 47077 7.22463 7.22463 -162.98 -7.22463 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.021449 0.0195803 217 208 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 2.56 vpr 64.45 MiB -1 -1 0.25 18364 13 0.23 -1 -1 32448 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 292 324 1 212 106 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2866 1500 7356 1329 5608 419 64.4 MiB 0.06 0.00 9.67796 7.98192 -159.937 -7.98192 7.98192 0.24 0.0011069 0.0010281 0.0237148 0.0219451 -1 -1 -1 -1 30 3231 22 6.55708e+06 506310 526063. 1820.29 0.67 0.135582 0.121368 21886 126133 -1 2914 15 1161 4203 188301 46205 6.76976 6.76976 -150.378 -6.76976 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0231856 0.0211083 204 198 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 2.26 vpr 64.33 MiB -1 -1 0.17 17984 12 0.18 -1 -1 32260 -1 -1 38 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 27 32 229 261 1 167 97 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2337 1007 8533 2013 5783 737 64.3 MiB 0.04 0.00 9.40566 7.49882 -132.896 -7.49882 7.49882 0.23 0.000357417 0.000327606 0.0166803 0.0152855 -1 -1 -1 -1 22 2846 33 6.55708e+06 458090 420624. 1455.45 0.73 0.0961015 0.0844727 20158 92377 -1 2495 21 936 2825 151732 38675 7.10844 7.10844 -133.129 -7.10844 0 0 500653. 1732.36 0.02 0.05 0.05 -1 -1 0.02 0.0221263 0.0200669 162 150 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 2.26 vpr 63.80 MiB -1 -1 0.15 17980 12 0.16 -1 -1 32388 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65328 31 32 229 261 1 172 99 17 17 289 -1 unnamed_device 24.0 MiB 0.09 2493 1182 11499 2779 7797 923 63.8 MiB 0.05 0.00 7.48917 6.1978 -123.822 -6.1978 6.1978 0.23 0.000357937 0.00032045 0.0200933 0.0182708 -1 -1 -1 -1 26 3022 23 6.55708e+06 433980 477104. 1650.88 0.68 0.0929068 0.0826701 21022 109990 -1 2558 15 983 3146 160300 39339 5.61152 5.61152 -124 -5.61152 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152523 0.0138522 153 138 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 2.12 vpr 64.02 MiB -1 -1 0.18 18368 12 0.15 -1 -1 32260 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 31 32 235 267 1 170 98 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2607 1194 6398 1155 4738 505 64.0 MiB 0.03 0.00 8.76355 7.13011 -140.761 -7.13011 7.13011 0.24 0.000359813 0.000329497 0.0130808 0.0120095 -1 -1 -1 -1 26 2823 45 6.55708e+06 421925 477104. 1650.88 0.53 0.0813171 0.0719305 21022 109990 -1 2481 18 878 2720 142628 35086 6.35464 6.35464 -138.252 -6.35464 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.026961 0.024312 155 144 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_010.v common 2.73 vpr 64.53 MiB -1 -1 0.17 17972 13 0.23 -1 -1 32340 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 250 282 1 190 99 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2595 1285 6255 1073 4701 481 64.5 MiB 0.04 0.00 9.61062 7.56812 -165.213 -7.56812 7.56812 0.26 0.000386406 0.000353879 0.0145749 0.0134141 -1 -1 -1 -1 26 3258 24 6.55708e+06 421925 477104. 1650.88 1.03 0.151248 0.131586 21022 109990 -1 2743 21 1276 3790 183407 45756 6.89358 6.89358 -162.183 -6.89358 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0293242 0.0262182 166 156 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 2.49 vpr 64.09 MiB -1 -1 0.15 17980 12 0.16 -1 -1 32496 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 30 32 216 248 1 160 95 17 17 289 -1 unnamed_device 24.2 MiB 0.07 2363 1089 9383 1996 6576 811 64.1 MiB 0.04 0.00 8.78898 6.99514 -141.661 -6.99514 6.99514 0.25 0.00034128 0.000311808 0.0166983 0.0152604 -1 -1 -1 -1 28 2591 19 6.55708e+06 397815 500653. 1732.36 0.90 0.101924 0.0897543 21310 115450 -1 2231 16 835 2644 129323 32207 6.02864 6.02864 -134.773 -6.02864 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0171828 0.0155916 140 128 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 2.27 vpr 63.82 MiB -1 -1 0.14 17980 12 0.13 -1 -1 32248 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65348 32 32 236 268 1 171 97 17 17 289 -1 unnamed_device 24.0 MiB 0.07 2486 1250 7201 1363 5333 505 63.8 MiB 0.04 0.00 7.92826 6.93051 -150.969 -6.93051 6.93051 0.24 0.000362163 0.000323716 0.0139954 0.0127661 -1 -1 -1 -1 22 3133 21 6.55708e+06 397815 420624. 1455.45 0.80 0.105874 0.0929435 20158 92377 -1 2873 18 1055 3139 174475 42904 6.04852 6.04852 -151.719 -6.04852 0 0 500653. 1732.36 0.02 0.05 0.05 -1 -1 0.02 0.0177045 0.0160033 148 142 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_013.v common 2.11 vpr 64.77 MiB -1 -1 0.17 17904 13 0.22 -1 -1 32380 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 283 315 1 206 102 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2918 1396 8432 1576 6264 592 64.8 MiB 0.05 0.00 10.5047 7.90793 -163.623 -7.90793 7.90793 0.24 0.000463543 0.000426506 0.0209377 0.0192839 -1 -1 -1 -1 26 3470 21 6.55708e+06 458090 477104. 1650.88 0.49 0.0961944 0.0860277 21022 109990 -1 2987 16 1182 3603 185734 44882 6.92916 6.92916 -156.223 -6.92916 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0219292 0.0199363 197 189 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_014.v common 2.97 vpr 64.87 MiB -1 -1 0.17 18364 14 0.28 -1 -1 32428 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 303 335 1 216 103 17 17 289 -1 unnamed_device 25.2 MiB 0.11 3288 1474 6128 1054 4658 416 64.9 MiB 0.04 0.00 12.0727 8.81606 -181.273 -8.81606 8.81606 0.24 0.000504434 0.000449507 0.0154959 0.0142237 -1 -1 -1 -1 28 3839 27 6.55708e+06 470145 500653. 1732.36 1.22 0.163212 0.143995 21310 115450 -1 3197 18 1484 4767 234549 57799 7.60916 7.60916 -170.785 -7.60916 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0274708 0.0249197 214 209 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_015.v common 2.39 vpr 64.35 MiB -1 -1 0.14 17980 11 0.15 -1 -1 32280 -1 -1 39 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 29 32 225 257 1 164 100 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2302 1071 8684 1857 6075 752 64.3 MiB 0.04 0.00 8.12271 6.84055 -135.697 -6.84055 6.84055 0.23 0.000349214 0.000319509 0.0150334 0.013758 -1 -1 -1 -1 30 2348 30 6.55708e+06 470145 526063. 1820.29 0.91 0.137917 0.121515 21886 126133 -1 2011 13 693 2200 90643 23004 5.99144 5.99144 -125.931 -5.99144 0 0 666494. 2306.21 0.02 0.03 0.07 -1 -1 0.02 0.013831 0.012644 154 140 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_016.v common 3.46 vpr 64.83 MiB -1 -1 0.25 18748 12 0.25 -1 -1 32680 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 32 32 301 333 1 214 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3731 1580 10108 2123 7160 825 64.8 MiB 0.06 0.00 10.4215 7.69506 -165.69 -7.69506 7.69506 0.23 0.00048124 0.000442319 0.023123 0.0211923 -1 -1 -1 -1 28 4238 23 6.55708e+06 482200 500653. 1732.36 1.51 0.193497 0.172492 21310 115450 -1 3402 20 1337 4577 232126 56137 6.59044 6.59044 -157.099 -6.59044 0 0 612192. 2118.31 0.04 0.11 0.11 -1 -1 0.04 0.0451348 0.0409865 211 207 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_017.v common 2.31 vpr 64.70 MiB -1 -1 0.17 18368 14 0.22 -1 -1 32384 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 277 309 1 206 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3035 1443 6528 1220 4877 431 64.7 MiB 0.04 0.00 10.0543 7.86974 -166.415 -7.86974 7.86974 0.24 0.000429846 0.000392749 0.0174185 0.0160311 -1 -1 -1 -1 30 3432 26 6.55708e+06 458090 526063. 1820.29 0.64 0.10171 0.0899918 21886 126133 -1 2807 16 1180 4013 184856 44602 6.94704 6.94704 -156.04 -6.94704 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0206573 0.018835 193 183 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_018.v common 2.73 vpr 64.29 MiB -1 -1 0.20 18360 12 0.14 -1 -1 32224 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 227 259 1 155 96 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2590 1167 9951 2256 6821 874 64.3 MiB 0.07 0.00 9.34738 6.87555 -150.994 -6.87555 6.87555 0.24 0.000849311 0.000790944 0.0342931 0.0321893 -1 -1 -1 -1 26 2790 20 6.55708e+06 385760 477104. 1650.88 1.03 0.160074 0.142578 21022 109990 -1 2381 19 920 3114 159590 38534 6.18098 6.18098 -145.131 -6.18098 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0283522 0.025653 145 133 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_019.v common 1.73 vpr 63.68 MiB -1 -1 0.13 17984 10 0.08 -1 -1 31720 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65204 30 32 175 207 1 133 87 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1817 875 6615 1509 4517 589 63.7 MiB 0.03 0.00 6.36477 5.54003 -124.848 -5.54003 5.54003 0.24 0.000273145 0.000250213 0.0117929 0.0108481 -1 -1 -1 -1 26 1892 14 6.55708e+06 301375 477104. 1650.88 0.37 0.0455235 0.0402896 21022 109990 -1 1707 15 580 1538 75173 19570 4.68146 4.68146 -118.937 -4.68146 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.011085 0.00998996 100 87 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_020.v common 2.61 vpr 64.34 MiB -1 -1 0.26 18368 13 0.16 -1 -1 32248 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 31 32 231 263 1 172 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2551 1219 5133 882 3910 341 64.3 MiB 0.03 0.00 9.56848 7.51354 -158.515 -7.51354 7.51354 0.25 0.00037534 0.000342742 0.011147 0.0102689 -1 -1 -1 -1 26 2914 16 6.55708e+06 397815 477104. 1650.88 0.93 0.10781 0.0949072 21022 109990 -1 2616 16 912 2770 141635 35169 6.50744 6.50744 -149.665 -6.50744 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0166308 0.0151505 151 140 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_021.v common 3.59 vpr 64.70 MiB -1 -1 0.25 18364 13 0.24 -1 -1 33084 -1 -1 45 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 32 32 304 336 1 215 109 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3300 1520 9729 2088 6855 786 64.7 MiB 0.05 0.00 11.3205 8.3687 -170.208 -8.3687 8.3687 0.36 0.000468055 0.00042951 0.021122 0.0193255 -1 -1 -1 -1 26 4144 38 6.55708e+06 542475 477104. 1650.88 1.62 0.168739 0.149499 21022 109990 -1 3324 16 1386 4558 227561 55685 7.37076 7.37076 -163.235 -7.37076 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0248103 0.0223431 222 210 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_022.v common 3.26 vpr 65.14 MiB -1 -1 0.17 18364 13 0.32 -1 -1 32320 -1 -1 46 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66700 32 32 288 320 1 212 110 17 17 289 -1 unnamed_device 25.2 MiB 0.08 3011 1549 9841 1986 7037 818 65.1 MiB 0.06 0.00 9.94628 8.09001 -170.835 -8.09001 8.09001 0.25 0.000783059 0.000709901 0.0240612 0.0222191 -1 -1 -1 -1 34 3785 46 6.55708e+06 554530 585099. 2024.56 1.41 0.194299 0.171381 22462 138074 -1 3315 18 1268 4764 252706 59815 6.97197 6.97197 -158.757 -6.97197 0 0 742403. 2568.87 0.03 0.07 0.08 -1 -1 0.03 0.0266895 0.0242846 209 194 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_023.v common 1.70 vpr 63.59 MiB -1 -1 0.12 17600 9 0.08 -1 -1 32016 -1 -1 30 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65120 26 32 152 184 1 110 88 17 17 289 -1 unnamed_device 24.0 MiB 0.03 1535 711 7888 1985 4791 1112 63.6 MiB 0.03 0.00 5.98374 4.84 -87.8657 -4.84 4.84 0.23 0.000243053 0.000222729 0.0112522 0.0102964 -1 -1 -1 -1 26 1557 15 6.55708e+06 361650 477104. 1650.88 0.33 0.0419996 0.0368842 21022 109990 -1 1389 17 478 1412 69242 17472 4.2322 4.2322 -86.9531 -4.2322 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0156673 0.0139829 95 76 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_024.v common 2.28 vpr 64.75 MiB -1 -1 0.16 18220 13 0.25 -1 -1 32356 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 287 319 1 209 106 17 17 289 -1 unnamed_device 25.0 MiB 0.07 3188 1475 7356 1240 5841 275 64.8 MiB 0.04 0.00 10.9129 8.3667 -168.117 -8.3667 8.3667 0.24 0.000456208 0.00041319 0.0164859 0.015092 -1 -1 -1 -1 26 3835 20 6.55708e+06 506310 477104. 1650.88 0.65 0.0893791 0.0794058 21022 109990 -1 3121 17 1250 3890 189718 46969 7.40996 7.40996 -160.049 -7.40996 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0207467 0.0188691 204 193 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_025.v common 1.68 vpr 63.57 MiB -1 -1 0.13 17600 8 0.07 -1 -1 32016 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65092 32 32 154 186 1 117 91 17 17 289 -1 unnamed_device 24.0 MiB 0.04 1504 839 6823 1506 4714 603 63.6 MiB 0.03 0.00 4.86674 4.14794 -97.1492 -4.14794 4.14794 0.23 0.000245642 0.000219086 0.00957985 0.00875471 -1 -1 -1 -1 26 1708 16 6.55708e+06 325485 477104. 1650.88 0.35 0.040037 0.0351673 21022 109990 -1 1465 13 445 1124 51583 13618 3.90514 3.90514 -96.8068 -3.90514 0 0 585099. 2024.56 0.02 0.02 0.08 -1 -1 0.02 0.00901111 0.00814501 83 60 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_026.v common 2.70 vpr 64.62 MiB -1 -1 0.19 17980 15 0.21 -1 -1 32384 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 32 32 254 286 1 184 108 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2794 1289 8846 1673 6391 782 64.6 MiB 0.04 0.00 11.4269 8.91249 -179.898 -8.91249 8.91249 0.24 0.000411792 0.000376479 0.0166773 0.0152536 -1 -1 -1 -1 28 3141 22 6.55708e+06 530420 500653. 1732.36 1.05 0.133835 0.117718 21310 115450 -1 2703 19 1085 3420 169095 41588 7.75229 7.75229 -168.555 -7.75229 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0202997 0.0183246 178 160 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_027.v common 3.32 vpr 64.26 MiB -1 -1 0.28 18368 13 0.20 -1 -1 32396 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 32 32 260 292 1 185 101 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2553 1218 6446 1181 4503 762 64.3 MiB 0.04 0.00 8.41804 7.47895 -148.299 -7.47895 7.47895 0.35 0.000420455 0.000384763 0.0146573 0.0134158 -1 -1 -1 -1 28 3650 32 6.55708e+06 446035 500653. 1732.36 1.30 0.141603 0.124407 21310 115450 -1 2721 15 1115 3669 183849 47689 6.42904 6.42904 -144.643 -6.42904 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0184911 0.0168997 177 166 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_028.v common 2.89 vpr 64.74 MiB -1 -1 0.17 18368 13 0.24 -1 -1 32460 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 279 311 1 203 102 17 17 289 -1 unnamed_device 24.8 MiB 0.11 2785 1427 7242 1418 5129 695 64.7 MiB 0.07 0.00 9.58507 7.90558 -164.249 -7.90558 7.90558 0.44 0.000817344 0.000732132 0.0296013 0.0270257 -1 -1 -1 -1 28 3858 46 6.55708e+06 458090 500653. 1732.36 0.87 0.129441 0.116272 21310 115450 -1 3094 16 1193 4031 204357 49925 6.90524 6.90524 -156.112 -6.90524 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0215907 0.0197086 194 185 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_029.v common 2.58 vpr 63.68 MiB -1 -1 0.14 17984 12 0.15 -1 -1 32200 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65212 32 32 238 270 1 175 98 17 17 289 -1 unnamed_device 24.1 MiB 0.07 2532 1229 6623 1196 5108 319 63.7 MiB 0.05 0.00 8.83794 6.95354 -149.945 -6.95354 6.95354 0.34 0.000362825 0.000331699 0.0207453 0.0191131 -1 -1 -1 -1 26 3231 30 6.55708e+06 409870 477104. 1650.88 0.76 0.0914983 0.0816512 21022 109990 -1 2625 20 1044 3327 165434 41832 6.25938 6.25938 -147.249 -6.25938 0 0 585099. 2024.56 0.03 0.08 0.10 -1 -1 0.03 0.0311287 0.0280935 151 144 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_030.v common 2.42 vpr 64.23 MiB -1 -1 0.14 17980 11 0.18 -1 -1 32228 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 30 32 213 245 1 156 94 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2070 1033 7549 1505 5428 616 64.2 MiB 0.04 0.00 8.27041 6.08486 -132.558 -6.08486 6.08486 0.24 0.00033254 0.000298034 0.0137224 0.0125369 -1 -1 -1 -1 26 2273 36 6.55708e+06 385760 477104. 1650.88 0.75 0.10972 0.0956295 21022 109990 -1 2055 14 763 2181 98833 26461 5.43986 5.43986 -127.04 -5.43986 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0168096 0.0153762 136 125 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_031.v common 2.06 vpr 64.36 MiB -1 -1 0.18 17820 11 0.15 -1 -1 32252 -1 -1 38 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 28 32 227 259 1 163 98 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2167 1077 9098 1974 6271 853 64.4 MiB 0.05 0.00 7.98015 6.78919 -130.953 -6.78919 6.78919 0.25 0.000476822 0.000447209 0.0226207 0.0209058 -1 -1 -1 -1 26 2605 24 6.55708e+06 458090 477104. 1650.88 0.46 0.0935539 0.083392 21022 109990 -1 2357 15 882 2746 133141 33518 6.11266 6.11266 -125.603 -6.11266 0 0 585099. 2024.56 0.03 0.05 0.06 -1 -1 0.03 0.0199283 0.0181338 155 145 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_032.v common 2.69 vpr 64.65 MiB -1 -1 0.19 17980 12 0.19 -1 -1 32280 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 32 32 274 306 1 199 103 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3018 1411 6128 1033 4730 365 64.7 MiB 0.04 0.00 9.91223 7.35615 -165.077 -7.35615 7.35615 0.24 0.000661124 0.000624461 0.0141509 0.0130367 -1 -1 -1 -1 28 3428 19 6.55708e+06 470145 500653. 1732.36 1.00 0.123875 0.108623 21310 115450 -1 2862 17 1149 3414 164768 41668 6.35004 6.35004 -156.285 -6.35004 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0208 0.0188528 188 180 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_033.v common 1.97 vpr 64.18 MiB -1 -1 0.14 17976 12 0.14 -1 -1 32240 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 31 32 237 269 1 165 98 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2339 1152 7973 1666 5519 788 64.2 MiB 0.04 0.00 8.83795 7.15214 -144.041 -7.15214 7.15214 0.24 0.000360413 0.000326731 0.0152974 0.0139203 -1 -1 -1 -1 26 2785 21 6.55708e+06 421925 477104. 1650.88 0.42 0.0710706 0.0628035 21022 109990 -1 2478 19 1052 3111 153968 38476 6.22984 6.22984 -139.914 -6.22984 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0257539 0.0230039 161 146 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_034.v common 1.80 vpr 64.32 MiB -1 -1 0.18 17984 10 0.12 -1 -1 32220 -1 -1 33 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 220 252 1 154 94 17 17 289 -1 unnamed_device 24.8 MiB 0.05 2111 1030 5206 950 3856 400 64.3 MiB 0.03 0.00 7.90072 6.31249 -127.587 -6.31249 6.31249 0.23 0.000341905 0.000312898 0.0105515 0.00968785 -1 -1 -1 -1 26 2457 16 6.55708e+06 397815 477104. 1650.88 0.30 0.0550495 0.0487275 21022 109990 -1 2196 16 763 2669 127482 31451 5.50298 5.50298 -123.617 -5.50298 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.015236 0.0138402 146 135 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_035.v common 2.56 vpr 64.93 MiB -1 -1 0.18 18748 13 0.35 -1 -1 32504 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 32 32 315 347 1 220 104 17 17 289 -1 unnamed_device 25.5 MiB 0.09 3359 1629 9132 2182 5924 1026 64.9 MiB 0.05 0.00 10.2396 8.33236 -170.529 -8.33236 8.33236 0.23 0.000496726 0.000454774 0.0221698 0.0202728 -1 -1 -1 -1 26 4005 19 6.55708e+06 482200 477104. 1650.88 0.70 0.0969603 0.0867237 21022 109990 -1 3407 16 1525 5269 261204 63091 6.78964 6.78964 -154.084 -6.78964 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0222822 0.0202409 231 221 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_036.v common 2.68 vpr 64.77 MiB -1 -1 0.17 18752 14 0.34 -1 -1 32288 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 282 314 1 219 107 17 17 289 -1 unnamed_device 24.8 MiB 0.13 3309 1501 7444 1465 5350 629 64.8 MiB 0.04 0.00 9.01512 7.882 -167.76 -7.882 7.882 0.23 0.000457104 0.000413096 0.0160806 0.0147011 -1 -1 -1 -1 30 3451 21 6.55708e+06 518365 526063. 1820.29 0.63 0.114441 0.102052 21886 126133 -1 3012 19 1353 4471 189705 48631 6.82684 6.82684 -156.723 -6.82684 0 0 666494. 2306.21 0.03 0.07 0.08 -1 -1 0.03 0.0272279 0.0246689 199 188 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_037.v common 2.55 vpr 64.40 MiB -1 -1 0.15 17984 12 0.13 -1 -1 32280 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 31 32 241 273 1 176 97 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2615 1203 10087 2397 6601 1089 64.4 MiB 0.07 0.00 10.1954 7.8818 -157.766 -7.8818 7.8818 0.25 0.000373792 0.000342257 0.0315957 0.0290482 -1 -1 -1 -1 26 2814 23 6.55708e+06 409870 477104. 1650.88 0.99 0.145263 0.128418 21022 109990 -1 2492 19 1059 3340 167020 41325 6.94904 6.94904 -150.445 -6.94904 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0178526 0.0160758 161 150 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_038.v common 3.38 vpr 64.19 MiB -1 -1 0.18 18604 12 0.24 -1 -1 32444 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65732 31 32 307 339 1 218 105 17 17 289 -1 unnamed_device 25.2 MiB 0.12 3531 1406 11961 2747 8126 1088 64.2 MiB 0.07 0.00 9.67644 7.34358 -149.686 -7.34358 7.34358 0.23 0.000477874 0.000430677 0.0279143 0.0255112 -1 -1 -1 -1 26 4060 37 6.55708e+06 506310 477104. 1650.88 1.57 0.230868 0.204995 21022 109990 -1 3110 21 1514 5290 250090 63272 6.71064 6.71064 -148.302 -6.71064 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.031789 0.0285672 222 216 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_039.v common 3.01 vpr 64.46 MiB -1 -1 0.19 18748 14 0.30 -1 -1 33004 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 293 325 1 209 103 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3249 1483 8056 1615 5882 559 64.5 MiB 0.10 0.00 11.3501 8.401 -168.472 -8.401 8.401 0.32 0.00120517 0.0011155 0.0430016 0.0397087 -1 -1 -1 -1 24 4160 43 6.55708e+06 482200 448715. 1552.65 1.10 0.163162 0.145601 20734 103517 -1 3341 29 1546 4981 334492 116243 7.72936 7.72936 -165.676 -7.72936 0 0 554710. 1919.41 0.02 0.12 0.06 -1 -1 0.02 0.0390517 0.0352076 211 202 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_040.v common 2.75 vpr 64.60 MiB -1 -1 0.19 18752 13 0.23 -1 -1 32248 -1 -1 49 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 31 32 276 308 1 210 112 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3496 1506 9527 2110 6648 769 64.6 MiB 0.05 0.00 10.2681 8.49401 -167.474 -8.49401 8.49401 0.24 0.000435905 0.000399578 0.0187398 0.0171331 -1 -1 -1 -1 26 4222 41 6.55708e+06 590695 477104. 1650.88 1.06 0.116426 0.103875 21022 109990 -1 3390 31 1362 4459 292331 95208 7.1573 7.1573 -156.188 -7.1573 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.0302454 0.0269603 204 185 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_041.v common 4.13 vpr 64.66 MiB -1 -1 0.18 18368 13 0.33 -1 -1 32428 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 31 32 269 301 1 187 99 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2993 1382 7623 1737 5150 736 64.7 MiB 0.05 0.00 9.77611 7.29977 -148.117 -7.29977 7.29977 0.23 0.000649272 0.000586185 0.0179255 0.0164024 -1 -1 -1 -1 26 3776 30 6.55708e+06 433980 477104. 1650.88 2.36 0.170021 0.150298 21022 109990 -1 2992 18 1097 3889 201560 47848 6.31084 6.31084 -138.606 -6.31084 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0209992 0.0190088 186 178 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_042.v common 2.52 vpr 64.57 MiB -1 -1 0.16 17980 12 0.16 -1 -1 32392 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 264 296 1 182 100 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2787 1178 16572 4143 9707 2722 64.6 MiB 0.08 0.00 8.67103 7.20861 -147.87 -7.20861 7.20861 0.24 0.000396717 0.000362317 0.031655 0.0287685 -1 -1 -1 -1 28 2903 30 6.55708e+06 433980 500653. 1732.36 0.92 0.146414 0.129198 21310 115450 -1 2418 14 944 2858 141962 35987 6.33838 6.33838 -138.315 -6.33838 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0198651 0.0180623 180 170 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_043.v common 3.48 vpr 65.00 MiB -1 -1 0.30 19516 14 0.36 -1 -1 32460 -1 -1 46 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 32 32 324 356 1 237 110 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3588 1767 7474 1429 5523 522 65.0 MiB 0.05 0.00 10.0303 8.51709 -182.069 -8.51709 8.51709 0.23 0.000502932 0.000460485 0.017751 0.0163008 -1 -1 -1 -1 32 4223 21 6.55708e+06 554530 554710. 1919.41 1.49 0.228883 0.201565 22174 131602 -1 3712 19 1425 5225 247788 61833 7.3565 7.3565 -172.567 -7.3565 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0292167 0.0264599 241 230 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_044.v common 1.96 vpr 63.96 MiB -1 -1 0.14 17984 11 0.17 -1 -1 31924 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65500 31 32 249 281 1 175 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2703 1245 9951 2354 6419 1178 64.0 MiB 0.05 0.00 8.92495 6.69552 -142.327 -6.69552 6.69552 0.23 0.000400985 0.000367433 0.020751 0.0189973 -1 -1 -1 -1 26 3314 26 6.55708e+06 397815 477104. 1650.88 0.45 0.0794923 0.0704457 21022 109990 -1 2774 20 1213 4204 218942 54057 5.89112 5.89112 -137.993 -5.89112 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0204148 0.0184373 169 158 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_045.v common 2.79 vpr 64.76 MiB -1 -1 0.17 18368 13 0.24 -1 -1 32256 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 284 316 1 195 106 17 17 289 -1 unnamed_device 24.8 MiB 0.09 2880 1407 6106 991 4788 327 64.8 MiB 0.04 0.00 10.1669 8.04395 -157.61 -8.04395 8.04395 0.23 0.000456389 0.000417669 0.0140646 0.0128906 -1 -1 -1 -1 26 3416 21 6.55708e+06 518365 477104. 1650.88 1.13 0.14093 0.124106 21022 109990 -1 2935 19 1052 3846 213355 60751 7.1573 7.1573 -151.712 -7.1573 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0259928 0.0232535 202 193 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_046.v common 4.22 vpr 64.81 MiB -1 -1 0.16 18364 12 0.23 -1 -1 32416 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 32 32 303 335 1 213 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3637 1510 9620 2142 6549 929 64.8 MiB 0.06 0.00 9.78237 6.97332 -152.142 -6.97332 6.97332 0.23 0.000502106 0.00042931 0.0261794 0.0239064 -1 -1 -1 -1 26 4325 34 6.55708e+06 482200 477104. 1650.88 2.53 0.197744 0.174299 21022 109990 -1 3559 22 2010 7594 396246 94358 6.30318 6.30318 -151.607 -6.30318 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.029183 0.0262317 216 209 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_047.v common 2.16 vpr 64.32 MiB -1 -1 0.15 18364 13 0.24 -1 -1 32524 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 272 304 1 187 98 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2741 1323 5723 957 4337 429 64.3 MiB 0.04 0.00 10.5096 7.47895 -154.869 -7.47895 7.47895 0.24 0.000437137 0.000400272 0.0143062 0.0131723 -1 -1 -1 -1 26 3535 21 6.55708e+06 409870 477104. 1650.88 0.54 0.0847412 0.0755315 21022 109990 -1 2816 18 1335 4235 204307 50601 6.70864 6.70864 -152.349 -6.70864 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.0206862 0.0187005 188 178 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_048.v common 2.55 vpr 64.30 MiB -1 -1 0.16 18368 13 0.19 -1 -1 32404 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 32 32 271 303 1 198 105 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2854 1297 7762 1580 5576 606 64.3 MiB 0.05 0.00 9.09457 7.36601 -155.837 -7.36601 7.36601 0.23 0.000415008 0.000379214 0.0185983 0.0171236 -1 -1 -1 -1 26 3146 23 6.55708e+06 494255 477104. 1650.88 1.01 0.139015 0.12237 21022 109990 -1 2730 15 1086 3278 165110 40936 6.44432 6.44432 -147.717 -6.44432 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184486 0.0168059 189 177 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_049.v common 3.65 vpr 64.80 MiB -1 -1 0.25 18368 12 0.22 -1 -1 32044 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66352 32 32 288 320 1 205 102 17 17 289 -1 unnamed_device 25.0 MiB 0.09 3079 1440 8670 1767 6237 666 64.8 MiB 0.05 0.00 8.89602 7.32135 -155.214 -7.32135 7.32135 0.23 0.000445433 0.000406962 0.0195291 0.0179138 -1 -1 -1 -1 26 3667 27 6.55708e+06 458090 477104. 1650.88 1.92 0.217527 0.191661 21022 109990 -1 3235 22 1404 5425 270682 64761 6.53898 6.53898 -150.672 -6.53898 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.024792 0.0223819 201 194 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_050.v common 3.79 vpr 64.84 MiB -1 -1 0.25 18752 13 0.26 -1 -1 33056 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66400 32 32 306 338 1 222 108 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3151 1541 9617 2019 6835 763 64.8 MiB 0.06 0.00 10.5209 8.10463 -168.591 -8.10463 8.10463 0.23 0.000483588 0.000442669 0.0214407 0.0196021 -1 -1 -1 -1 26 4372 38 6.55708e+06 530420 477104. 1650.88 1.97 0.193338 0.171644 21022 109990 -1 3411 15 1394 4439 211034 53368 7.2801 7.2801 -161.773 -7.2801 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0212496 0.019415 223 212 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_051.v common 2.37 vpr 64.64 MiB -1 -1 0.15 18368 14 0.24 -1 -1 32696 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 262 294 1 188 100 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2763 1363 11700 2683 7233 1784 64.6 MiB 0.06 0.00 11.1513 8.70517 -163.209 -8.70517 8.70517 0.24 0.000445018 0.000409166 0.0237738 0.0217999 -1 -1 -1 -1 26 3751 36 6.55708e+06 433980 477104. 1650.88 0.74 0.097964 0.0871314 21022 109990 -1 2963 18 1219 3929 208524 50182 7.98142 7.98142 -159.654 -7.98142 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0219043 0.0197382 181 168 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_052.v common 3.29 vpr 64.70 MiB -1 -1 0.18 18364 13 0.23 -1 -1 32404 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 32 32 291 323 1 211 107 17 17 289 -1 unnamed_device 24.8 MiB 0.10 3299 1433 10480 2285 7646 549 64.7 MiB 0.08 0.00 11.3728 8.2812 -162.484 -8.2812 8.2812 0.23 0.000456943 0.000419163 0.0319448 0.0295537 -1 -1 -1 -1 26 4249 38 6.55708e+06 518365 477104. 1650.88 1.59 0.201052 0.17736 21022 109990 -1 3257 22 1390 4748 258559 69429 7.1579 7.1579 -156.58 -7.1579 0 0 585099. 2024.56 0.02 0.07 0.06 -1 -1 0.02 0.0241806 0.0217837 211 197 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_053.v common 3.45 vpr 64.82 MiB -1 -1 0.25 18752 13 0.24 -1 -1 32152 -1 -1 44 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 302 334 1 217 107 17 17 289 -1 unnamed_device 24.8 MiB 0.06 3175 1433 9974 2144 6983 847 64.8 MiB 0.06 0.00 10.7693 8.14207 -165.881 -8.14207 8.14207 0.23 0.000463083 0.000424081 0.0213645 0.019549 -1 -1 -1 -1 26 3885 44 6.55708e+06 530420 477104. 1650.88 1.62 0.186609 0.164822 21022 109990 -1 3210 16 1307 4049 198045 49445 7.04936 7.04936 -156.762 -7.04936 0 0 585099. 2024.56 0.02 0.06 0.10 -1 -1 0.02 0.0220925 0.0201608 219 211 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_054.v common 3.00 vpr 64.88 MiB -1 -1 0.25 18748 12 0.28 -1 -1 32588 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66432 32 32 308 340 1 227 107 17 17 289 -1 unnamed_device 25.2 MiB 0.10 3553 1588 8456 1657 6340 459 64.9 MiB 0.05 0.00 10.5054 7.81338 -162.105 -7.81338 7.81338 0.23 0.000467261 0.0004282 0.0190897 0.0174553 -1 -1 -1 -1 30 3533 18 6.55708e+06 518365 526063. 1820.29 1.20 0.175664 0.154749 21886 126133 -1 2975 18 1181 4009 172026 42611 6.9633 6.9633 -152.154 -6.9633 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0281559 0.0255785 222 214 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_055.v common 2.30 vpr 63.96 MiB -1 -1 0.14 17984 11 0.11 -1 -1 32256 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65492 32 32 216 248 1 150 93 17 17 289 -1 unnamed_device 24.0 MiB 0.05 2172 1114 6813 1476 4649 688 64.0 MiB 0.03 0.00 7.67149 6.45472 -142.708 -6.45472 6.45472 0.23 0.000329671 0.000300919 0.0124913 0.0114155 -1 -1 -1 -1 26 2542 22 6.55708e+06 349595 477104. 1650.88 0.90 0.111032 0.0966003 21022 109990 -1 2319 13 784 2335 118482 29614 5.83766 5.83766 -144.011 -5.83766 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0132596 0.0121081 134 122 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_056.v common 2.35 vpr 64.57 MiB -1 -1 0.16 18224 13 0.19 -1 -1 31976 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 254 286 1 184 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2723 1225 8432 1783 5976 673 64.6 MiB 0.04 0.00 9.64721 7.76601 -160.89 -7.76601 7.76601 0.23 0.000398125 0.000364366 0.0168136 0.0153621 -1 -1 -1 -1 26 3260 44 6.55708e+06 458090 477104. 1650.88 0.72 0.0960043 0.0851036 21022 109990 -1 2668 30 1325 4578 317119 107312 7.1573 7.1573 -159.968 -7.1573 0 0 585099. 2024.56 0.02 0.10 0.06 -1 -1 0.02 0.0292682 0.0261828 175 160 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_057.v common 3.52 vpr 65.05 MiB -1 -1 0.19 19136 14 0.39 -1 -1 32632 -1 -1 47 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 338 370 1 243 111 17 17 289 -1 unnamed_device 25.8 MiB 0.09 3926 1767 7559 1351 5612 596 65.1 MiB 0.05 0.00 11.6381 8.88614 -176.77 -8.88614 8.88614 0.23 0.000538484 0.000482436 0.0186713 0.0170975 -1 -1 -1 -1 28 4757 39 6.55708e+06 566585 500653. 1732.36 1.59 0.216624 0.192218 21310 115450 -1 3846 18 1679 5489 285754 69543 7.90101 7.90101 -169.258 -7.90101 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0266501 0.0243171 256 244 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_058.v common 3.29 vpr 64.53 MiB -1 -1 0.19 18220 13 0.25 -1 -1 32408 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 271 303 1 202 100 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2981 1449 7060 1377 5094 589 64.5 MiB 0.04 0.00 9.8853 7.81987 -168.799 -7.81987 7.81987 0.23 0.000432617 0.000395853 0.0160406 0.0146835 -1 -1 -1 -1 26 3590 23 6.55708e+06 433980 477104. 1650.88 1.51 0.144757 0.127716 21022 109990 -1 3059 15 1235 3945 193279 47785 6.8803 6.8803 -158.318 -6.8803 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0195175 0.0177688 186 177 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_059.v common 2.17 vpr 64.32 MiB -1 -1 0.17 17980 11 0.15 -1 -1 32468 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 30 32 224 256 1 152 94 17 17 289 -1 unnamed_device 24.8 MiB 0.09 1968 1020 7762 1726 5530 506 64.3 MiB 0.05 0.00 8.50338 6.74949 -138.67 -6.74949 6.74949 0.26 0.000356161 0.00032542 0.0222888 0.0205686 -1 -1 -1 -1 24 2406 20 6.55708e+06 385760 448715. 1552.65 0.55 0.0898862 0.0798319 20734 103517 -1 2133 14 787 2459 127346 32295 5.93998 5.93998 -132.575 -5.93998 0 0 554710. 1919.41 0.02 0.04 0.06 -1 -1 0.02 0.0148732 0.0136023 150 136 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_060.v common 5.66 vpr 65.20 MiB -1 -1 0.19 19508 15 0.47 -1 -1 32024 -1 -1 49 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66760 32 32 351 383 1 261 113 17 17 289 -1 unnamed_device 25.6 MiB 0.09 3995 2010 11852 2629 8141 1082 65.2 MiB 0.07 0.00 12.8102 9.45181 -192.305 -9.45181 9.45181 0.23 0.000559457 0.000504907 0.027816 0.0253997 -1 -1 -1 -1 28 5547 42 6.55708e+06 590695 500653. 1732.36 3.63 0.240926 0.214838 21310 115450 -1 4448 19 2153 7534 412419 96794 8.64975 8.64975 -185.929 -8.64975 0 0 612192. 2118.31 0.02 0.09 0.06 -1 -1 0.02 0.0302484 0.0276287 261 257 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_061.v common 3.60 vpr 64.78 MiB -1 -1 0.29 18368 13 0.28 -1 -1 32244 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 297 329 1 206 104 17 17 289 -1 unnamed_device 25.2 MiB 0.08 3275 1492 10352 2588 6648 1116 64.8 MiB 0.06 0.00 10.6893 8.11669 -167.863 -8.11669 8.11669 0.24 0.000535712 0.000495888 0.0247164 0.0227451 -1 -1 -1 -1 28 4178 42 6.55708e+06 482200 500653. 1732.36 1.62 0.210555 0.186384 21310 115450 -1 3202 18 1377 4381 237630 56889 6.81096 6.81096 -157.796 -6.81096 0 0 612192. 2118.31 0.04 0.13 0.08 -1 -1 0.04 0.0513009 0.0464052 211 203 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_062.v common 1.74 vpr 64.33 MiB -1 -1 0.13 17980 11 0.11 -1 -1 32248 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 231 263 1 168 96 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2404 1200 5352 1082 3950 320 64.3 MiB 0.03 0.00 7.81172 6.30809 -138.848 -6.30809 6.30809 0.23 0.000345025 0.000315149 0.010973 0.0100535 -1 -1 -1 -1 26 2781 16 6.55708e+06 385760 477104. 1650.88 0.35 0.0549483 0.0486739 21022 109990 -1 2413 18 931 2920 146323 36299 5.79586 5.79586 -136.986 -5.79586 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0199369 0.0179319 149 137 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_063.v common 3.06 vpr 64.87 MiB -1 -1 0.18 18756 12 0.26 -1 -1 32492 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 305 337 1 209 106 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3192 1509 8106 1613 5842 651 64.9 MiB 0.06 0.00 10.8824 7.43184 -153.804 -7.43184 7.43184 0.23 0.000627827 0.000546897 0.025293 0.0233741 -1 -1 -1 -1 30 3226 28 6.55708e+06 506310 526063. 1820.29 1.36 0.221708 0.195832 21886 126133 -1 2895 17 1214 4355 186157 46002 6.47224 6.47224 -143.336 -6.47224 0 0 666494. 2306.21 0.02 0.05 0.07 -1 -1 0.02 0.0218846 0.0199037 224 211 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_064.v common 2.63 vpr 64.36 MiB -1 -1 0.16 17984 12 0.17 -1 -1 32132 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 243 275 1 185 101 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2741 1320 8326 1851 5875 600 64.4 MiB 0.04 0.00 8.98498 7.57401 -157.5 -7.57401 7.57401 0.23 0.000391939 0.000359402 0.0160215 0.0146932 -1 -1 -1 -1 28 3291 20 6.55708e+06 446035 500653. 1732.36 0.96 0.120985 0.106511 21310 115450 -1 2704 18 1002 3193 154404 38429 6.70098 6.70098 -151.983 -6.70098 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0183839 0.0166494 160 149 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_065.v common 2.00 vpr 64.36 MiB -1 -1 0.15 17976 12 0.16 -1 -1 32424 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 30 32 228 260 1 158 96 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2463 1057 6009 1165 4395 449 64.4 MiB 0.03 0.00 9.70233 7.10808 -144.903 -7.10808 7.10808 0.23 0.000361721 0.000331358 0.0122651 0.0112354 -1 -1 -1 -1 20 2487 24 6.55708e+06 409870 394039. 1363.46 0.49 0.061774 0.0548534 19870 87366 -1 2323 17 852 2864 148607 36739 6.46058 6.46058 -142.134 -6.46058 0 0 477104. 1650.88 0.02 0.04 0.05 -1 -1 0.02 0.0165964 0.0150485 151 140 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_066.v common 2.62 vpr 64.75 MiB -1 -1 0.18 18364 12 0.25 -1 -1 32836 -1 -1 41 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 29 32 275 307 1 195 102 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2776 1290 7956 1517 5875 564 64.8 MiB 0.04 0.00 9.75944 6.89912 -129.506 -6.89912 6.89912 0.23 0.000439187 0.000401806 0.0176508 0.016155 -1 -1 -1 -1 26 3296 19 6.55708e+06 494255 477104. 1650.88 0.94 0.140672 0.123405 21022 109990 -1 2817 17 1189 4151 205219 50431 6.27364 6.27364 -125.715 -6.27364 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0217945 0.0198656 198 190 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_067.v common 4.15 vpr 64.46 MiB -1 -1 0.20 18364 13 0.35 -1 -1 32304 -1 -1 50 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 330 362 1 232 114 17 17 289 -1 unnamed_device 25.2 MiB 0.13 3249 1646 11706 2331 8577 798 64.5 MiB 0.07 0.00 10.166 8.087 -174.968 -8.087 8.087 0.23 0.000504128 0.00046231 0.0252032 0.0230892 -1 -1 -1 -1 26 4440 49 6.55708e+06 602750 477104. 1650.88 2.09 0.265695 0.235973 21022 109990 -1 3658 31 2107 6976 387104 114321 7.6773 7.6773 -175.999 -7.6773 0 0 585099. 2024.56 0.02 0.16 0.06 -1 -1 0.02 0.0585253 0.0524828 247 236 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_068.v common 3.05 vpr 64.17 MiB -1 -1 0.20 18364 12 0.21 -1 -1 32352 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 290 322 1 203 104 17 17 289 -1 unnamed_device 24.4 MiB 0.10 3300 1279 10352 2652 6577 1123 64.2 MiB 0.07 0.00 10.7679 7.73832 -150.742 -7.73832 7.73832 0.25 0.000467737 0.000428655 0.0302749 0.0280738 -1 -1 -1 -1 28 3491 20 6.55708e+06 482200 500653. 1732.36 1.23 0.162438 0.144317 21310 115450 -1 2895 16 1315 4243 219437 55418 6.8405 6.8405 -146.978 -6.8405 0 0 612192. 2118.31 0.04 0.09 0.07 -1 -1 0.04 0.035537 0.0323181 206 196 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_069.v common 2.48 vpr 64.25 MiB -1 -1 0.14 17984 12 0.13 -1 -1 32928 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 214 246 1 156 95 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2480 1130 5927 1103 4408 416 64.2 MiB 0.03 0.00 9.31584 7.04661 -144.877 -7.04661 7.04661 0.24 0.000339655 0.000310041 0.0115631 0.010563 -1 -1 -1 -1 26 2534 18 6.55708e+06 373705 477104. 1650.88 1.07 0.122005 0.106406 21022 109990 -1 2279 18 854 2634 133675 33889 5.97718 5.97718 -136.774 -5.97718 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0161625 0.0146372 135 120 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_070.v common 2.62 vpr 64.46 MiB -1 -1 0.16 18368 12 0.19 -1 -1 31944 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 244 276 1 170 98 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2617 1274 6398 1159 4710 529 64.5 MiB 0.03 0.00 9.56447 7.57061 -150.375 -7.57061 7.57061 0.24 0.00038161 0.000349434 0.0132809 0.0121488 -1 -1 -1 -1 28 3024 18 6.55708e+06 421925 500653. 1732.36 1.06 0.135071 0.118552 21310 115450 -1 2560 16 918 3190 159899 38980 6.2813 6.2813 -142.114 -6.2813 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0199613 0.0181369 161 153 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_071.v common 3.01 vpr 64.17 MiB -1 -1 0.26 18368 11 0.17 -1 -1 32488 -1 -1 40 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 30 32 276 308 1 199 102 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2727 1365 7242 1318 5567 357 64.2 MiB 0.05 0.00 8.59664 6.98252 -137.845 -6.98252 6.98252 0.24 0.000452447 0.000411507 0.0193183 0.0178012 -1 -1 -1 -1 26 3630 40 6.55708e+06 482200 477104. 1650.88 1.29 0.156421 0.137889 21022 109990 -1 3067 18 1183 4172 215666 51876 6.07244 6.07244 -134.218 -6.07244 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0227691 0.0204083 194 188 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_072.v common 2.85 vpr 64.55 MiB -1 -1 0.17 17980 11 0.18 -1 -1 32268 -1 -1 36 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 28 32 253 285 1 177 96 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2506 1211 8199 1748 5508 943 64.6 MiB 0.05 0.00 8.69997 6.71295 -129.325 -6.71295 6.71295 0.23 0.00042684 0.000393932 0.0228206 0.0211229 -1 -1 -1 -1 30 2524 16 6.55708e+06 433980 526063. 1820.29 1.18 0.162297 0.142794 21886 126133 -1 2281 16 880 3154 140107 34317 5.85898 5.85898 -123.314 -5.85898 0 0 666494. 2306.21 0.04 0.08 0.08 -1 -1 0.04 0.0371708 0.0335976 176 171 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_073.v common 2.11 vpr 64.43 MiB -1 -1 0.16 18364 13 0.18 -1 -1 31916 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 30 32 235 267 1 166 98 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2275 1124 7748 1646 5543 559 64.4 MiB 0.06 0.00 10.228 7.79233 -143.293 -7.79233 7.79233 0.24 0.000882547 0.000817551 0.0271881 0.0254 -1 -1 -1 -1 26 2682 22 6.55708e+06 433980 477104. 1650.88 0.39 0.0872149 0.0781979 21022 109990 -1 2310 16 922 3336 150513 38472 6.8039 6.8039 -136.548 -6.8039 0 0 585099. 2024.56 0.04 0.06 0.09 -1 -1 0.04 0.0265682 0.0241882 157 147 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_074.v common 2.88 vpr 64.63 MiB -1 -1 0.18 18364 12 0.25 -1 -1 32276 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66180 32 32 264 296 1 187 100 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2846 1273 10540 2582 6897 1061 64.6 MiB 0.05 0.00 9.32034 7.41947 -161.03 -7.41947 7.41947 0.24 0.000416783 0.000381574 0.0215499 0.0196879 -1 -1 -1 -1 28 3178 43 6.55708e+06 433980 500653. 1732.36 1.13 0.150714 0.132237 21310 115450 -1 2752 18 1030 3249 171987 42405 6.2003 6.2003 -148.62 -6.2003 0 0 612192. 2118.31 0.02 0.05 0.08 -1 -1 0.02 0.019547 0.0176734 180 170 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_075.v common 2.19 vpr 64.74 MiB -1 -1 0.16 18000 13 0.26 -1 -1 32444 -1 -1 41 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 278 310 1 197 104 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2948 1285 6204 1121 4455 628 64.7 MiB 0.04 0.00 10.4607 8.33266 -159.321 -8.33266 8.33266 0.23 0.000450174 0.000413364 0.0161966 0.0149247 -1 -1 -1 -1 26 3400 25 6.55708e+06 494255 477104. 1650.88 0.51 0.0828088 0.0735628 21022 109990 -1 2719 17 1068 3376 157383 40304 7.28976 7.28976 -154.47 -7.28976 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0220486 0.0201017 196 187 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_076.v common 2.83 vpr 64.76 MiB -1 -1 0.18 18368 14 0.23 -1 -1 32384 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 290 322 1 201 102 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2948 1449 9860 2172 6855 833 64.8 MiB 0.05 0.00 10.9465 8.71544 -176.837 -8.71544 8.71544 0.34 0.000453693 0.000415773 0.0221562 0.02036 -1 -1 -1 -1 26 3548 21 6.55708e+06 458090 477104. 1650.88 1.07 0.149225 0.13138 21022 109990 -1 2951 16 1100 3513 167818 41879 7.92796 7.92796 -172.589 -7.92796 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0203231 0.0184758 203 196 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_077.v common 2.31 vpr 64.68 MiB -1 -1 0.18 18748 14 0.23 -1 -1 32424 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 269 301 1 187 100 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2291 1303 7756 1442 5636 678 64.7 MiB 0.04 0.00 10.3699 8.36955 -159.159 -8.36955 8.36955 0.23 0.000433687 0.000393612 0.0182587 0.0167452 -1 -1 -1 -1 26 3430 22 6.55708e+06 433980 477104. 1650.88 0.64 0.0842795 0.0747516 21022 109990 -1 2830 19 1184 4577 262704 74075 7.20936 7.20936 -150.018 -7.20936 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0285986 0.0255366 179 175 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_078.v common 3.05 vpr 64.75 MiB -1 -1 0.20 18752 13 0.30 -1 -1 32616 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 296 328 1 216 108 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3246 1544 7561 1452 5398 711 64.7 MiB 0.05 0.00 10.7252 8.52515 -170.673 -8.52515 8.52515 0.24 0.000599389 0.000558386 0.0190979 0.0176173 -1 -1 -1 -1 30 3404 28 6.55708e+06 530420 526063. 1820.29 1.22 0.159177 0.140846 21886 126133 -1 3028 17 1199 4291 182956 46284 7.56735 7.56735 -161.205 -7.56735 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0223292 0.0203908 212 202 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_079.v common 2.70 vpr 64.03 MiB -1 -1 0.16 17984 13 0.16 -1 -1 32448 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65568 30 32 234 266 1 169 96 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2265 1134 4695 742 3633 320 64.0 MiB 0.03 0.00 10.2529 7.95464 -161.944 -7.95464 7.95464 0.24 0.000503181 0.00047225 0.0126481 0.0117035 -1 -1 -1 -1 28 2792 17 6.55708e+06 409870 500653. 1732.36 1.03 0.115548 0.101979 21310 115450 -1 2338 16 791 2338 113501 28721 6.77538 6.77538 -150.108 -6.77538 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0215635 0.0196967 155 146 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_080.v common 3.66 vpr 64.75 MiB -1 -1 0.30 18748 13 0.40 -1 -1 32412 -1 -1 42 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66308 30 32 291 323 1 211 104 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2984 1412 9376 2164 6142 1070 64.8 MiB 0.05 0.00 10.8675 8.7665 -166.076 -8.7665 8.7665 0.25 0.00048301 0.000435282 0.0216956 0.0198322 -1 -1 -1 -1 28 4440 36 6.55708e+06 506310 500653. 1732.36 1.52 0.195156 0.172406 21310 115450 -1 3306 22 1808 6039 308441 75318 8.13116 8.13116 -164.886 -8.13116 0 0 612192. 2118.31 0.02 0.12 0.06 -1 -1 0.02 0.0480109 0.0432038 211 203 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_081.v common 3.33 vpr 64.71 MiB -1 -1 0.17 18364 14 0.36 -1 -1 32276 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 274 306 1 188 100 17 17 289 -1 unnamed_device 24.8 MiB 0.11 2874 1381 6828 1358 4978 492 64.7 MiB 0.04 0.00 10.16 8.0528 -168.058 -8.0528 8.0528 0.26 0.000433477 0.000396437 0.0159878 0.0146877 -1 -1 -1 -1 26 3440 29 6.55708e+06 433980 477104. 1650.88 1.31 0.163675 0.144893 21022 109990 -1 2924 17 1120 4094 202887 49196 7.29236 7.29236 -160.792 -7.29236 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.021869 0.0198747 188 180 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_082.v common 2.44 vpr 64.65 MiB -1 -1 0.17 18368 13 0.20 -1 -1 32416 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 31 32 266 298 1 188 103 17 17 289 -1 unnamed_device 25.2 MiB 0.05 2648 1278 6851 1303 5218 330 64.7 MiB 0.06 0.00 9.79664 7.73626 -147.024 -7.73626 7.73626 0.26 0.000753216 0.000687884 0.0256158 0.0234295 -1 -1 -1 -1 26 3475 22 6.55708e+06 482200 477104. 1650.88 0.78 0.106799 0.0961352 21022 109990 -1 2882 21 1188 3871 201792 49498 6.6419 6.6419 -139.849 -6.6419 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0230652 0.0209088 189 175 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_083.v common 2.84 vpr 64.66 MiB -1 -1 0.17 18368 13 0.19 -1 -1 32276 -1 -1 42 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 30 32 266 298 1 198 104 17 17 289 -1 unnamed_device 25.3 MiB 0.08 3212 1451 7180 1397 5391 392 64.7 MiB 0.04 0.00 9.98558 8.08209 -153.888 -8.08209 8.08209 0.24 0.00041428 0.000379794 0.0146925 0.0134878 -1 -1 -1 -1 30 3135 19 6.55708e+06 506310 526063. 1820.29 1.15 0.133595 0.117686 21886 126133 -1 2656 16 1001 3565 158345 38941 6.8803 6.8803 -143.947 -6.8803 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0190113 0.0173463 188 178 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_084.v common 3.35 vpr 64.14 MiB -1 -1 0.17 18748 14 0.32 -1 -1 32436 -1 -1 45 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 310 342 1 226 109 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3591 1582 8689 1758 6168 763 64.1 MiB 0.06 0.00 10.8164 8.74282 -175.793 -8.74282 8.74282 0.24 0.000619421 0.000577581 0.0244264 0.0226096 -1 -1 -1 -1 28 3859 21 6.55708e+06 542475 500653. 1732.36 1.59 0.224812 0.199302 21310 115450 -1 3320 22 1569 5205 250249 62085 7.80069 7.80069 -168.216 -7.80069 0 0 612192. 2118.31 0.02 0.07 0.06 -1 -1 0.02 0.0269125 0.0242969 225 216 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_085.v common 2.20 vpr 64.32 MiB -1 -1 0.18 18368 11 0.24 -1 -1 32232 -1 -1 44 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 262 294 1 199 105 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3052 1320 8997 1938 5901 1158 64.3 MiB 0.05 0.00 10.039 7.47594 -139.521 -7.47594 7.47594 0.25 0.000443441 0.000400928 0.0210946 0.019397 -1 -1 -1 -1 28 3433 19 6.55708e+06 530420 500653. 1732.36 0.49 0.0838839 0.0748833 21310 115450 -1 2860 19 1167 3779 180535 45529 6.59044 6.59044 -133.662 -6.59044 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0217172 0.0197123 187 177 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_086.v common 1.76 vpr 64.29 MiB -1 -1 0.15 17452 13 0.14 -1 -1 32192 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 222 254 1 166 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2365 1134 8198 1752 5856 590 64.3 MiB 0.04 0.00 9.5772 7.60931 -162.659 -7.60931 7.60931 0.23 0.000354996 0.000325193 0.0199103 0.018532 -1 -1 -1 -1 26 2640 18 6.55708e+06 409870 477104. 1650.88 0.33 0.0653865 0.0584309 21022 109990 -1 2286 15 824 2298 113671 28726 6.82684 6.82684 -156.225 -6.82684 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0146309 0.01333 138 128 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_087.v common 2.89 vpr 64.68 MiB -1 -1 0.16 18752 14 0.32 -1 -1 32396 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 267 299 1 189 101 17 17 289 -1 unnamed_device 24.8 MiB 0.10 2654 1253 5741 1095 4066 580 64.7 MiB 0.03 0.00 10.1014 8.22497 -162.245 -8.22497 8.22497 0.23 0.000420987 0.000385592 0.0129977 0.0119483 -1 -1 -1 -1 28 3525 29 6.55708e+06 446035 500653. 1732.36 1.12 0.138603 0.121855 21310 115450 -1 2791 16 995 3352 161293 40081 7.37336 7.37336 -157.789 -7.37336 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0199676 0.0181409 183 173 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_088.v common 4.09 vpr 65.06 MiB -1 -1 0.18 18740 15 0.41 -1 -1 32468 -1 -1 50 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66624 32 32 334 366 1 242 114 17 17 289 -1 unnamed_device 25.6 MiB 0.10 3845 1754 10878 2260 7829 789 65.1 MiB 0.07 0.00 12.4201 9.30007 -197.166 -9.30007 9.30007 0.25 0.00073948 0.000685983 0.0295529 0.0270958 -1 -1 -1 -1 26 4755 36 6.55708e+06 602750 477104. 1650.88 2.09 0.22201 0.19724 21022 109990 -1 3923 19 1866 5993 314116 76247 8.60335 8.60335 -194.026 -8.60335 0 0 585099. 2024.56 0.02 0.10 0.06 -1 -1 0.02 0.0383912 0.0348739 250 240 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_089.v common 2.17 vpr 64.28 MiB -1 -1 0.18 17984 11 0.14 -1 -1 32264 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 32 32 220 252 1 154 97 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2168 1074 8977 1935 6287 755 64.3 MiB 0.04 0.00 8.59479 6.66858 -139.589 -6.66858 6.66858 0.23 0.000338532 0.000309224 0.0167458 0.015295 -1 -1 -1 -1 26 2415 19 6.55708e+06 397815 477104. 1650.88 0.66 0.0991471 0.0868577 21022 109990 -1 2246 16 755 2442 124269 30281 5.94258 5.94258 -136.678 -5.94258 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0148758 0.0135052 142 126 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_090.v common 2.99 vpr 64.48 MiB -1 -1 0.15 17984 12 0.16 -1 -1 32296 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 31 32 244 276 1 183 99 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2718 1278 7623 1628 5411 584 64.5 MiB 0.04 0.00 9.30618 7.4792 -158.92 -7.4792 7.4792 0.23 0.000382061 0.000343151 0.0153388 0.0139891 -1 -1 -1 -1 26 3486 19 6.55708e+06 433980 477104. 1650.88 1.45 0.150081 0.132485 21022 109990 -1 2982 15 1147 3679 189997 47278 6.26704 6.26704 -150.559 -6.26704 0 0 585099. 2024.56 0.03 0.05 0.07 -1 -1 0.03 0.0191888 0.0175386 165 153 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_091.v common 3.49 vpr 64.71 MiB -1 -1 0.18 18368 12 0.26 -1 -1 32432 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 300 332 1 217 108 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3275 1622 10645 2328 7422 895 64.7 MiB 0.08 0.00 10.2612 7.59364 -164.56 -7.59364 7.59364 0.24 0.000486686 0.000442889 0.0386317 0.0358231 -1 -1 -1 -1 34 3724 22 6.55708e+06 530420 585099. 2024.56 1.66 0.233929 0.207628 22462 138074 -1 3411 16 1421 4778 241051 58262 6.6811 6.6811 -156.408 -6.6811 0 0 742403. 2568.87 0.04 0.10 0.08 -1 -1 0.04 0.03612 0.0328032 217 206 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_092.v common 3.37 vpr 64.69 MiB -1 -1 0.18 18604 12 0.21 -1 -1 32768 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 271 303 1 200 105 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3003 1380 8750 1810 6138 802 64.7 MiB 0.05 0.00 9.79464 7.36891 -159.112 -7.36891 7.36891 0.23 0.000426637 0.000390945 0.017895 0.0164169 -1 -1 -1 -1 24 4116 29 6.55708e+06 494255 448715. 1552.65 1.71 0.160092 0.141723 20734 103517 -1 3365 25 1982 7225 408926 104160 6.75244 6.75244 -158.639 -6.75244 0 0 554710. 1919.41 0.02 0.09 0.06 -1 -1 0.02 0.025969 0.0232829 190 177 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_093.v common 4.60 vpr 64.64 MiB -1 -1 0.18 19136 14 0.42 -1 -1 32440 -1 -1 44 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 327 359 1 229 108 17 17 289 -1 unnamed_device 25.3 MiB 0.09 3556 1590 6276 1065 4786 425 64.6 MiB 0.05 0.00 11.4017 8.85831 -179.658 -8.85831 8.85831 0.23 0.00100888 0.000964631 0.0195122 0.0181514 -1 -1 -1 -1 26 4696 36 6.55708e+06 530420 477104. 1650.88 2.70 0.216563 0.19256 21022 109990 -1 3722 21 1876 6496 326439 79639 7.96009 7.96009 -172.069 -7.96009 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0285679 0.0258669 239 233 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_094.v common 2.94 vpr 64.52 MiB -1 -1 0.16 18364 12 0.18 -1 -1 32224 -1 -1 35 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 30 32 246 278 1 176 97 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2728 1268 8755 2050 5708 997 64.5 MiB 0.05 0.00 10.0467 7.41486 -143.807 -7.41486 7.41486 0.24 0.00040521 0.000366057 0.0205555 0.0189281 -1 -1 -1 -1 28 3102 24 6.55708e+06 421925 500653. 1732.36 1.32 0.176868 0.155997 21310 115450 -1 2547 27 942 3467 228891 85010 6.50684 6.50684 -134.136 -6.50684 0 0 612192. 2118.31 0.02 0.08 0.06 -1 -1 0.02 0.0271277 0.0243958 166 158 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_095.v common 2.40 vpr 64.17 MiB -1 -1 0.15 17980 11 0.16 -1 -1 31856 -1 -1 31 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 27 32 219 251 1 153 90 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2075 890 11346 2674 7241 1431 64.2 MiB 0.05 0.00 8.56235 6.47229 -119.898 -6.47229 6.47229 0.23 0.000341003 0.000311104 0.0216579 0.0197916 -1 -1 -1 -1 28 2291 17 6.55708e+06 373705 500653. 1732.36 0.84 0.110181 0.0967621 21310 115450 -1 1920 17 832 2771 122094 32173 5.80812 5.80812 -117.51 -5.80812 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0160773 0.0145507 146 140 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_096.v common 3.17 vpr 65.43 MiB -1 -1 0.30 19132 13 0.39 -1 -1 32616 -1 -1 54 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67004 32 32 380 412 1 274 118 17 17 289 -1 unnamed_device 25.5 MiB 0.10 4655 2221 11100 2341 7945 814 65.4 MiB 0.09 0.00 10.8384 8.21927 -169.077 -8.21927 8.21927 0.23 0.000611341 0.000552744 0.0377977 0.0348813 -1 -1 -1 -1 30 5210 32 6.55708e+06 650970 526063. 1820.29 1.10 0.160347 0.144658 21886 126133 -1 4272 20 1942 7051 322540 77378 7.23124 7.23124 -159.615 -7.23124 0 0 666494. 2306.21 0.02 0.08 0.07 -1 -1 0.02 0.031786 0.028998 289 286 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_097.v common 2.30 vpr 64.73 MiB -1 -1 0.17 18368 14 0.22 -1 -1 32316 -1 -1 41 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 31 32 277 309 1 197 104 17 17 289 -1 unnamed_device 25.2 MiB 0.06 3097 1274 12304 3037 7768 1499 64.7 MiB 0.06 0.00 12.2136 8.62006 -170.085 -8.62006 8.62006 0.24 0.000432138 0.000396089 0.0252147 0.0231002 -1 -1 -1 -1 26 3603 32 6.55708e+06 494255 477104. 1650.88 0.68 0.106179 0.0939771 21022 109990 -1 2789 17 1209 3625 176693 45658 7.45942 7.45942 -162.283 -7.45942 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0202702 0.0183759 202 186 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_098.v common 1.86 vpr 64.37 MiB -1 -1 0.16 18360 12 0.15 -1 -1 32220 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 229 261 1 169 98 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2364 1167 6398 1184 4756 458 64.4 MiB 0.04 0.00 10.1826 7.64801 -160.064 -7.64801 7.64801 0.23 0.00048408 0.000452387 0.0138589 0.0127355 -1 -1 -1 -1 26 2856 21 6.55708e+06 409870 477104. 1650.88 0.37 0.0640324 0.0568082 21022 109990 -1 2410 15 851 2669 125206 31603 6.5589 6.5589 -149.274 -6.5589 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0155306 0.0141676 149 135 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_099.v common 3.16 vpr 64.67 MiB -1 -1 0.18 18364 13 0.25 -1 -1 31888 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 32 32 263 295 1 192 101 17 17 289 -1 unnamed_device 24.8 MiB 0.06 2878 1329 9971 1977 6864 1130 64.7 MiB 0.05 0.00 10.3391 7.91544 -159.644 -7.91544 7.91544 0.23 0.000426804 0.0003908 0.0210623 0.0192623 -1 -1 -1 -1 28 3543 34 6.55708e+06 446035 500653. 1732.36 1.25 0.163021 0.144227 21310 115450 -1 2890 17 1266 4303 210367 52177 6.7993 6.7993 -152.562 -6.7993 0 0 612192. 2118.31 0.02 0.06 0.08 -1 -1 0.02 0.0235242 0.0211813 177 169 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_100.v common 3.61 vpr 64.95 MiB -1 -1 0.17 18748 13 0.29 -1 -1 32496 -1 -1 48 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 31 32 321 353 1 234 111 17 17 289 -1 unnamed_device 25.6 MiB 0.08 3400 1604 9953 2030 7063 860 64.9 MiB 0.06 0.00 9.6468 7.26834 -148.565 -7.26834 7.26834 0.23 0.000503324 0.000461623 0.0225716 0.0206576 -1 -1 -1 -1 26 4462 29 6.55708e+06 578640 477104. 1650.88 1.84 0.204323 0.180668 21022 109990 -1 3651 20 2029 6761 360098 85834 6.67706 6.67706 -150.677 -6.67706 0 0 585099. 2024.56 0.02 0.08 0.06 -1 -1 0.02 0.0263633 0.0238787 242 230 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_101.v common 2.43 vpr 64.31 MiB -1 -1 0.21 17984 11 0.22 -1 -1 32456 -1 -1 43 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 30 32 287 319 1 198 105 17 17 289 -1 unnamed_device 24.8 MiB 0.07 3001 1293 11220 2634 7278 1308 64.3 MiB 0.14 0.00 9.47524 7.25311 -136.619 -7.25311 7.25311 0.25 0.00121921 0.00112523 0.0612861 0.0568716 -1 -1 -1 -1 30 2864 16 6.55708e+06 518365 526063. 1820.29 0.60 0.154135 0.140337 21886 126133 -1 2537 18 972 3930 165233 40913 6.35004 6.35004 -128.389 -6.35004 0 0 666494. 2306.21 0.03 0.06 0.07 -1 -1 0.03 0.0273439 0.0245502 207 199 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_102.v common 2.56 vpr 64.80 MiB -1 -1 0.18 18752 15 0.33 -1 -1 32512 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 296 328 1 208 101 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3400 1425 8326 1756 5851 719 64.8 MiB 0.05 0.00 12.6428 9.11323 -184.154 -9.11323 9.11323 0.23 0.00050701 0.000465418 0.0201741 0.0184292 -1 -1 -1 -1 26 3950 24 6.55708e+06 446035 477104. 1650.88 0.61 0.0902455 0.0803698 21022 109990 -1 3244 16 1338 4712 234668 58393 7.97942 7.97942 -176.46 -7.97942 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0212655 0.0193666 207 202 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_103.v common 3.78 vpr 64.78 MiB -1 -1 0.18 18752 13 0.31 -1 -1 32440 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 285 317 1 204 102 17 17 289 -1 unnamed_device 25.2 MiB 0.12 3131 1495 5338 899 4142 297 64.8 MiB 0.03 0.00 10.6725 8.26703 -174.041 -8.26703 8.26703 0.24 0.000462099 0.000423406 0.0133165 0.0122552 -1 -1 -1 -1 28 4046 41 6.55708e+06 458090 500653. 1732.36 1.93 0.213209 0.188425 21310 115450 -1 3146 16 1246 4278 217929 53207 7.2409 7.2409 -163.588 -7.2409 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0212515 0.0193558 202 191 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_104.v common 2.00 vpr 64.46 MiB -1 -1 0.18 17984 12 0.18 -1 -1 32132 -1 -1 41 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 29 32 239 271 1 178 102 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2844 1190 7956 1682 5619 655 64.5 MiB 0.04 0.00 10.6983 7.98398 -159.232 -7.98398 7.98398 0.24 0.000371108 0.000339729 0.0153222 0.014034 -1 -1 -1 -1 26 3200 29 6.55708e+06 494255 477104. 1650.88 0.45 0.0732874 0.0649933 21022 109990 -1 2709 20 1104 3239 159893 40584 7.1573 7.1573 -156.73 -7.1573 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0188511 0.0170473 168 154 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_105.v common 2.75 vpr 63.94 MiB -1 -1 0.16 18368 11 0.13 -1 -1 32292 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 32 32 235 267 1 176 98 17 17 289 -1 unnamed_device 24.1 MiB 0.05 2767 1260 7298 1447 5288 563 63.9 MiB 0.05 0.00 9.23769 6.98988 -143.739 -6.98988 6.98988 0.34 0.000348314 0.000318582 0.018582 0.0170113 -1 -1 -1 -1 26 3168 19 6.55708e+06 409870 477104. 1650.88 1.13 0.150939 0.133035 21022 109990 -1 2729 16 1008 3088 154235 38775 6.31284 6.31284 -144.7 -6.31284 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0156476 0.0142051 155 141 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_106.v common 2.74 vpr 64.85 MiB -1 -1 0.17 18368 13 0.29 -1 -1 32432 -1 -1 44 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66404 31 32 294 326 1 211 107 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3439 1453 7444 1510 5262 672 64.8 MiB 0.06 0.00 10.2189 7.97431 -160.47 -7.97431 7.97431 0.36 0.000708924 0.000639099 0.0251625 0.0230048 -1 -1 -1 -1 28 3874 29 6.55708e+06 530420 500653. 1732.36 0.63 0.105132 0.0937956 21310 115450 -1 3104 16 1212 4206 205123 50684 7.4003 7.4003 -160.122 -7.4003 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0211131 0.0192249 211 203 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_107.v common 2.44 vpr 64.32 MiB -1 -1 0.20 17972 10 0.18 -1 -1 32220 -1 -1 35 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 219 251 1 150 96 17 17 289 -1 unnamed_device 24.8 MiB 0.06 1946 1061 5790 1112 4104 574 64.3 MiB 0.04 0.00 7.37011 6.00295 -119.764 -6.00295 6.00295 0.25 0.00035911 0.000329803 0.0191472 0.0177945 -1 -1 -1 -1 26 2502 24 6.55708e+06 421925 477104. 1650.88 0.86 0.117586 0.103676 21022 109990 -1 2062 17 806 2797 128453 31706 5.21312 5.21312 -114.473 -5.21312 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0158314 0.0142786 147 134 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_108.v common 2.22 vpr 64.45 MiB -1 -1 0.18 17980 14 0.17 -1 -1 32276 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 239 271 1 173 98 17 17 289 -1 unnamed_device 24.4 MiB 0.06 2734 1213 7073 1458 5059 556 64.5 MiB 0.05 0.00 11.0242 8.4809 -168.731 -8.4809 8.4809 0.33 0.000366617 0.000335327 0.0184044 0.0169477 -1 -1 -1 -1 26 3090 29 6.55708e+06 409870 477104. 1650.88 0.58 0.101652 0.0904075 21022 109990 -1 2658 16 969 3018 149359 37853 7.24455 7.24455 -157.889 -7.24455 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0163044 0.0148298 156 145 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_109.v common 2.81 vpr 64.29 MiB -1 -1 0.18 18752 13 0.24 -1 -1 32408 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 31 32 266 298 1 193 103 17 17 289 -1 unnamed_device 24.8 MiB 0.09 3161 1363 8538 1729 6172 637 64.3 MiB 0.05 0.00 10.4036 7.97301 -166.024 -7.97301 7.97301 0.24 0.000424703 0.000382451 0.024452 0.0226427 -1 -1 -1 -1 26 3263 23 6.55708e+06 482200 477104. 1650.88 1.15 0.195819 0.172559 21022 109990 -1 2818 15 1049 3322 160900 40390 6.8803 6.8803 -152.18 -6.8803 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0178379 0.0162423 188 175 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_110.v common 2.58 vpr 64.30 MiB -1 -1 0.21 17984 12 0.13 -1 -1 32200 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 31 32 225 257 1 161 97 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2415 1133 6757 1438 4598 721 64.3 MiB 0.03 0.00 9.26878 7.00946 -143.372 -7.00946 7.00946 0.23 0.000349322 0.000319975 0.0126652 0.0116002 -1 -1 -1 -1 26 2691 23 6.55708e+06 409870 477104. 1650.88 0.96 0.107657 0.0948875 21022 109990 -1 2292 17 845 2615 133353 32686 6.23184 6.23184 -137.649 -6.23184 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0283693 0.0256193 145 134 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_111.v common 2.97 vpr 64.77 MiB -1 -1 0.22 17980 12 0.18 -1 -1 33052 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 288 320 1 205 105 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3231 1460 9244 1928 6414 902 64.8 MiB 0.07 0.00 9.79864 7.07814 -148.913 -7.07814 7.07814 0.27 0.000569668 0.000527241 0.0282744 0.0260291 -1 -1 -1 -1 28 3623 19 6.55708e+06 494255 500653. 1732.36 1.21 0.175311 0.154218 21310 115450 -1 3038 18 1249 4669 234810 56737 6.41878 6.41878 -147.502 -6.41878 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0237192 0.021482 206 194 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_112.v common 3.31 vpr 64.61 MiB -1 -1 0.19 18740 13 0.29 -1 -1 32356 -1 -1 38 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 31 32 282 314 1 202 101 17 17 289 -1 unnamed_device 24.8 MiB 0.10 3277 1590 6681 1310 4868 503 64.6 MiB 0.04 0.00 10.7471 8.73972 -167.897 -8.73972 8.73972 0.23 0.000460535 0.000422889 0.0162374 0.0149525 -1 -1 -1 -1 28 3932 24 6.55708e+06 458090 500653. 1732.36 1.51 0.16573 0.146424 21310 115450 -1 3256 15 1195 4023 206433 49925 7.28716 7.28716 -157.96 -7.28716 0 0 612192. 2118.31 0.02 0.06 0.07 -1 -1 0.02 0.0254841 0.02301 201 191 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_113.v common 1.99 vpr 64.38 MiB -1 -1 0.19 17984 11 0.16 -1 -1 32248 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 233 265 1 176 99 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2465 1216 7395 1434 5485 476 64.4 MiB 0.04 0.00 8.01481 6.6836 -143.167 -6.6836 6.6836 0.23 0.000354533 0.00032415 0.0139007 0.0127385 -1 -1 -1 -1 26 2889 24 6.55708e+06 421925 477104. 1650.88 0.40 0.0652603 0.0578256 21022 109990 -1 2427 20 1207 3730 171289 43329 5.71184 5.71184 -135.745 -5.71184 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0233234 0.0209333 152 139 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_114.v common 2.17 vpr 64.54 MiB -1 -1 0.22 17980 13 0.22 -1 -1 32172 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 32 32 254 286 1 183 102 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2879 1214 6528 1147 5041 340 64.5 MiB 0.04 0.00 10.6786 7.73627 -160.675 -7.73627 7.73627 0.25 0.000409177 0.000375614 0.0135402 0.0124612 -1 -1 -1 -1 26 2886 16 6.55708e+06 458090 477104. 1650.88 0.39 0.0686872 0.0611683 21022 109990 -1 2556 28 1471 5017 296309 110070 6.74524 6.74524 -153.355 -6.74524 0 0 585099. 2024.56 0.02 0.09 0.06 -1 -1 0.02 0.0258403 0.0231684 170 160 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_115.v common 3.18 vpr 64.73 MiB -1 -1 0.25 18368 13 0.32 -1 -1 32408 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 32 32 285 317 1 211 105 17 17 289 -1 unnamed_device 25.3 MiB 0.10 3339 1491 8503 1758 5902 843 64.7 MiB 0.05 0.00 10.8748 7.88135 -168.607 -7.88135 7.88135 0.37 0.000513341 0.000475271 0.0182779 0.0167377 -1 -1 -1 -1 28 3856 19 6.55708e+06 494255 500653. 1732.36 1.11 0.135527 0.119597 21310 115450 -1 3156 16 1241 3837 184163 45729 6.9979 6.9979 -160.864 -6.9979 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0198868 0.0181274 203 191 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_116.v common 2.49 vpr 64.50 MiB -1 -1 0.18 18368 11 0.26 -1 -1 32416 -1 -1 36 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 29 32 243 275 1 174 97 17 17 289 -1 unnamed_device 24.4 MiB 0.07 2558 1138 10309 2535 6640 1134 64.5 MiB 0.06 0.00 9.92175 6.74749 -129.645 -6.74749 6.74749 0.30 0.000772465 0.000712951 0.0260806 0.0238587 -1 -1 -1 -1 26 3126 32 6.55708e+06 433980 477104. 1650.88 0.67 0.0939845 0.0839562 21022 109990 -1 2578 17 931 3325 169042 40480 6.05818 6.05818 -124.542 -6.05818 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184457 0.0167471 161 158 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_117.v common 4.27 vpr 64.39 MiB -1 -1 0.29 19136 14 0.31 -1 -1 33084 -1 -1 49 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 318 350 1 238 113 17 17 289 -1 unnamed_device 25.0 MiB 0.10 3835 1720 13490 3177 9101 1212 64.4 MiB 0.09 0.00 11.3374 8.61726 -184.782 -8.61726 8.61726 0.38 0.000531117 0.000488117 0.0381217 0.0350571 -1 -1 -1 -1 26 4747 29 6.55708e+06 590695 477104. 1650.88 1.96 0.210063 0.187395 21022 109990 -1 3847 17 1619 5028 258599 64735 7.6387 7.6387 -177.864 -7.6387 0 0 585099. 2024.56 0.03 0.07 0.10 -1 -1 0.03 0.0264884 0.0241963 237 224 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_118.v common 3.07 vpr 64.34 MiB -1 -1 0.14 17596 12 0.16 -1 -1 32212 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 31 32 222 254 1 168 102 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2680 1201 9146 2230 5919 997 64.3 MiB 0.07 0.00 9.64207 6.86528 -149.041 -6.86528 6.86528 0.27 0.000812538 0.000756576 0.0281269 0.0260777 -1 -1 -1 -1 28 2882 21 6.55708e+06 470145 500653. 1732.36 1.53 0.151684 0.134655 21310 115450 -1 2472 16 858 2767 136347 34084 6.01898 6.01898 -141.29 -6.01898 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0163473 0.014792 148 131 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_119.v common 3.95 vpr 64.73 MiB -1 -1 0.18 18748 13 0.38 -1 -1 33024 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 282 314 1 207 106 17 17 289 -1 unnamed_device 24.8 MiB 0.11 3147 1501 6856 1348 5065 443 64.7 MiB 0.04 0.00 11.0904 8.08861 -162.494 -8.08861 8.08861 0.24 0.000487836 0.00044248 0.0151914 0.0139396 -1 -1 -1 -1 30 3270 24 6.55708e+06 506310 526063. 1820.29 1.81 0.202497 0.178708 21886 126133 -1 2801 17 1152 3849 170213 42169 6.9959 6.9959 -151.51 -6.9959 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0214516 0.0195268 197 188 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_120.v common 2.26 vpr 64.41 MiB -1 -1 0.16 18356 13 0.16 -1 -1 31960 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 238 270 1 177 100 17 17 289 -1 unnamed_device 24.4 MiB 0.05 2839 1155 9612 2317 6234 1061 64.4 MiB 0.06 0.00 10.0742 7.73627 -166.258 -7.73627 7.73627 0.26 0.000577123 0.000544952 0.0229617 0.0211759 -1 -1 -1 -1 26 3028 23 6.55708e+06 433980 477104. 1650.88 0.64 0.0971387 0.0867266 21022 109990 -1 2456 17 990 2796 128129 34060 6.7183 6.7183 -154.301 -6.7183 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0259404 0.0234647 163 144 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_121.v common 2.36 vpr 64.06 MiB -1 -1 0.19 18364 12 0.19 -1 -1 32400 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65600 32 32 269 301 1 185 98 17 17 289 -1 unnamed_device 24.0 MiB 0.07 2537 1263 4823 745 3784 294 64.1 MiB 0.04 0.00 8.39043 7.2824 -152.393 -7.2824 7.2824 0.28 0.000905441 0.000848363 0.0153777 0.0142054 -1 -1 -1 -1 26 3179 19 6.55708e+06 409870 477104. 1650.88 0.52 0.0875654 0.0779802 21022 109990 -1 2833 16 1121 3843 195292 47160 6.33578 6.33578 -144.328 -6.33578 0 0 585099. 2024.56 0.04 0.12 0.08 -1 -1 0.04 0.0502091 0.0457004 181 175 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_122.v common 4.30 vpr 64.66 MiB -1 -1 0.21 19136 15 0.52 -1 -1 32728 -1 -1 53 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 350 382 1 251 117 17 17 289 -1 unnamed_device 25.5 MiB 0.10 4081 1828 11271 2288 8079 904 64.7 MiB 0.08 0.00 12.2654 9.04209 -187.694 -9.04209 9.04209 0.24 0.000564516 0.000516461 0.0316535 0.0292536 -1 -1 -1 -1 34 4381 20 6.55708e+06 638915 585099. 2024.56 1.93 0.266028 0.237356 22462 138074 -1 3819 17 1628 5914 283565 69847 7.93821 7.93821 -172.8 -7.93821 0 0 742403. 2568.87 0.04 0.11 0.13 -1 -1 0.04 0.0448869 0.0406004 267 256 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_123.v common 2.15 vpr 63.67 MiB -1 -1 0.17 17984 10 0.08 -1 -1 31896 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65200 30 32 174 206 1 130 87 17 17 289 -1 unnamed_device 24.1 MiB 0.06 1854 885 5271 1136 3651 484 63.7 MiB 0.03 0.00 6.3165 5.04697 -113.367 -5.04697 5.04697 0.27 0.000281181 0.000256712 0.0096779 0.00890741 -1 -1 -1 -1 22 2009 18 6.55708e+06 301375 420624. 1455.45 0.72 0.0769089 0.067373 20158 92377 -1 1822 15 647 1672 87673 22492 4.69874 4.69874 -113.69 -4.69874 0 0 500653. 1732.36 0.02 0.03 0.05 -1 -1 0.02 0.0113927 0.0102766 101 86 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_124.v common 2.17 vpr 64.31 MiB -1 -1 0.16 17984 13 0.16 -1 -1 32224 -1 -1 35 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65856 30 32 228 260 1 166 97 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2503 1064 8533 2145 5652 736 64.3 MiB 0.05 0.00 9.22658 7.43294 -146.134 -7.43294 7.43294 0.25 0.000684186 0.00061813 0.0193226 0.0176829 -1 -1 -1 -1 26 2779 19 6.55708e+06 421925 477104. 1650.88 0.59 0.0941429 0.083978 21022 109990 -1 2338 20 900 2793 146444 39162 6.62764 6.62764 -141.958 -6.62764 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0212905 0.0192897 158 140 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_125.v common 2.93 vpr 64.61 MiB -1 -1 0.16 17984 12 0.22 -1 -1 32456 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66164 32 32 264 296 1 190 103 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2629 1279 6851 1204 5209 438 64.6 MiB 0.06 0.00 9.58679 7.67078 -160.044 -7.67078 7.67078 0.26 0.00074458 0.000678895 0.0262383 0.0240079 -1 -1 -1 -1 26 3107 22 6.55708e+06 470145 477104. 1650.88 1.18 0.160881 0.142423 21022 109990 -1 2653 17 1110 3493 165297 42443 6.9215 6.9215 -157.739 -6.9215 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.0191677 0.017369 182 170 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_126.v common 1.94 vpr 63.14 MiB -1 -1 0.16 17984 9 0.14 -1 -1 32072 -1 -1 32 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64652 25 32 183 215 1 133 89 17 17 289 -1 unnamed_device 23.7 MiB 0.04 1645 871 9395 2229 5617 1549 63.1 MiB 0.04 0.00 7.61712 5.81412 -100.01 -5.81412 5.81412 0.24 0.000292282 0.000267119 0.0173114 0.0159233 -1 -1 -1 -1 20 2082 17 6.55708e+06 385760 394039. 1363.46 0.46 0.0530832 0.0471797 19870 87366 -1 1921 20 716 2165 117867 32355 5.29412 5.29412 -99.9076 -5.29412 0 0 477104. 1650.88 0.02 0.04 0.05 -1 -1 0.02 0.0149858 0.0134956 117 110 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_127.v common 2.38 vpr 64.78 MiB -1 -1 0.19 18368 12 0.24 -1 -1 32288 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66336 32 32 300 332 1 216 107 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3565 1492 7444 1324 5746 374 64.8 MiB 0.05 0.00 10.0075 7.59118 -168.041 -7.59118 7.59118 0.24 0.000891795 0.000812487 0.0203308 0.0187674 -1 -1 -1 -1 26 3908 24 6.55708e+06 518365 477104. 1650.88 0.63 0.101343 0.0903997 21022 109990 -1 3205 18 1335 4400 213388 52780 6.7621 6.7621 -161.57 -6.7621 0 0 585099. 2024.56 0.03 0.09 0.07 -1 -1 0.03 0.038608 0.0346733 214 206 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_128.v common 3.03 vpr 64.82 MiB -1 -1 0.34 18748 13 0.34 -1 -1 32352 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 290 322 1 209 103 17 17 289 -1 unnamed_device 24.8 MiB 0.08 3076 1400 9020 1816 6496 708 64.8 MiB 0.06 0.00 10.9492 8.22447 -168.698 -8.22447 8.22447 0.24 0.000468237 0.000425889 0.0269885 0.0247947 -1 -1 -1 -1 26 4161 44 6.55708e+06 482200 477104. 1650.88 0.88 0.150718 0.134439 21022 109990 -1 3404 19 1491 5035 261566 64544 7.49096 7.49096 -169.674 -7.49096 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0380429 0.0345811 210 199 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 2.05 vpr 64.81 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30188 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 32 32 354 285 1 202 100 17 17 289 -1 unnamed_device 24.9 MiB 0.17 2678 1168 17500 5183 9317 3000 64.8 MiB 0.09 0.00 6.89032 5.76129 -168.782 -5.76129 5.76129 0.25 0.000333333 0.000305308 0.0299479 0.0274962 -1 -1 -1 -1 32 2438 20 6.64007e+06 452088 554710. 1919.41 0.45 0.0846256 0.0753861 22834 132086 -1 2056 19 1088 1723 102004 24911 4.49028 4.49028 -149.555 -4.49028 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0160781 0.0144875 152 50 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.00 vpr 64.81 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29772 -1 -1 30 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2387 1153 13961 4091 8036 1834 64.8 MiB 0.11 0.00 6.11521 5.05541 -146.114 -5.05541 5.05541 0.25 0.000500957 0.000466786 0.0364324 0.0336624 -1 -1 -1 -1 32 2330 19 6.64007e+06 376740 554710. 1919.41 0.43 0.0998543 0.0896451 22834 132086 -1 2183 20 1448 2220 169416 37520 3.76628 3.76628 -132.238 -3.76628 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0177524 0.0158766 147 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.62 vpr 64.13 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 32 32 299 247 1 188 94 17 17 289 -1 unnamed_device 24.5 MiB 0.16 2525 988 13087 3736 7613 1738 64.1 MiB 0.07 0.00 5.74935 4.679 -119.362 -4.679 4.679 0.23 0.000294184 0.000268866 0.0198637 0.018188 -1 -1 -1 -1 28 2482 34 6.64007e+06 376740 500653. 1732.36 1.10 0.1219 0.106318 21970 115934 -1 1920 19 1114 1579 102339 24279 3.91102 3.91102 -116.938 -3.91102 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0155755 0.0139714 129 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.18 vpr 64.59 MiB -1 -1 0.19 17668 1 0.03 -1 -1 29756 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2219 999 11684 2867 7870 947 64.6 MiB 0.06 0.00 5.50467 4.50524 -120.656 -4.50524 4.50524 0.23 0.000301757 0.000276843 0.0194556 0.0177984 -1 -1 -1 -1 26 2353 21 6.64007e+06 389298 477104. 1650.88 0.78 0.102845 0.0897238 21682 110474 -1 1996 22 1376 2539 149716 35231 3.78483 3.78483 -117.773 -3.78483 0 0 585099. 2024.56 0.02 0.06 0.07 -1 -1 0.02 0.0206924 0.0183868 132 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 1.93 vpr 64.67 MiB -1 -1 0.11 18052 1 0.03 -1 -1 30212 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 25.2 MiB 0.05 2401 1044 13340 3641 8511 1188 64.7 MiB 0.10 0.00 5.52176 4.47681 -129.939 -4.47681 4.47681 0.27 0.000326175 0.000298389 0.0335294 0.031105 -1 -1 -1 -1 26 2714 23 6.64007e+06 351624 477104. 1650.88 0.52 0.0841857 0.0755446 21682 110474 -1 2319 20 1464 2737 194545 44782 3.91083 3.91083 -130.973 -3.91083 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0173489 0.015589 134 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.19 vpr 64.17 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29756 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 24.6 MiB 0.07 2589 1146 13840 3734 8768 1338 64.2 MiB 0.07 0.00 4.20679 3.37156 -118.042 -3.37156 3.37156 0.24 0.000343562 0.000314786 0.0216965 0.0198462 -1 -1 -1 -1 28 2430 24 6.64007e+06 489762 500653. 1732.36 0.79 0.125458 0.109537 21970 115934 -1 2113 20 1219 1980 106732 27236 3.00917 3.00917 -117.621 -3.00917 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0217329 0.0195006 145 58 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.30 vpr 63.78 MiB -1 -1 0.20 17288 1 0.02 -1 -1 30552 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65312 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1585 646 13324 5650 6908 766 63.8 MiB 0.06 0.00 4.47141 3.76738 -100.249 -3.76738 3.76738 0.24 0.000261076 0.000238807 0.0222262 0.0203919 -1 -1 -1 -1 30 1362 22 6.64007e+06 263718 526063. 1820.29 0.89 0.104457 0.0913085 22546 126617 -1 1268 22 886 1557 92007 22640 2.87397 2.87397 -91.7688 -2.87397 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0171266 0.015248 97 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.27 vpr 64.12 MiB -1 -1 0.11 17912 1 0.03 -1 -1 29800 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65656 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2037 1027 15848 4746 8906 2196 64.1 MiB 0.08 0.00 4.0843 3.4441 -101.869 -3.4441 3.4441 0.23 0.000279498 0.000255601 0.0233277 0.0213053 -1 -1 -1 -1 26 2300 22 6.64007e+06 439530 477104. 1650.88 0.94 0.108532 0.0952919 21682 110474 -1 2007 20 1077 1995 121729 28059 2.93817 2.93817 -99.1235 -2.93817 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0142379 0.0126856 123 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.53 vpr 64.61 MiB -1 -1 0.13 17908 1 0.03 -1 -1 30172 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 317 271 1 168 88 17 17 289 -1 unnamed_device 24.9 MiB 0.11 2086 995 13543 3931 7670 1942 64.6 MiB 0.06 0.00 3.99239 3.60222 -119.143 -3.60222 3.60222 0.23 0.000300054 0.000274015 0.0225345 0.0206345 -1 -1 -1 -1 32 1822 20 6.64007e+06 313950 554710. 1919.41 0.92 0.11928 0.104086 22834 132086 -1 1636 20 877 1310 79180 19116 2.89043 2.89043 -109.637 -2.89043 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0150146 0.013392 117 64 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.63 vpr 64.51 MiB -1 -1 0.13 17664 1 0.03 -1 -1 30140 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 24.9 MiB 0.12 1795 817 8003 1790 5827 386 64.5 MiB 0.05 0.00 4.55761 3.87558 -124.983 -3.87558 3.87558 0.24 0.000293751 0.000267622 0.014943 0.0137302 -1 -1 -1 -1 28 1916 23 6.64007e+06 238602 500653. 1732.36 0.99 0.107138 0.0936028 21970 115934 -1 1743 21 1210 1968 117336 30369 2.80477 2.80477 -113.751 -2.80477 0 0 612192. 2118.31 0.02 0.04 0.08 -1 -1 0.02 0.0158551 0.0140681 115 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.40 vpr 64.53 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29796 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 24.5 MiB 0.07 1688 651 12156 4701 5752 1703 64.5 MiB 0.06 0.00 4.55761 3.85358 -107.527 -3.85358 3.85358 0.25 0.000290653 0.000265701 0.0218367 0.0200019 -1 -1 -1 -1 30 1469 20 6.64007e+06 238602 526063. 1820.29 0.83 0.0990725 0.0867591 22546 126617 -1 1254 17 604 926 54157 13941 2.77497 2.77497 -95.1733 -2.77497 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0130171 0.0117058 101 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.31 vpr 64.49 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29716 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2346 951 8919 2111 6427 381 64.5 MiB 0.05 0.00 4.97492 3.76035 -118.411 -3.76035 3.76035 0.23 0.000287454 0.000258142 0.0148458 0.0135347 -1 -1 -1 -1 26 2233 26 6.64007e+06 288834 477104. 1650.88 0.90 0.106722 0.0926572 21682 110474 -1 1861 21 1041 1454 89116 22517 3.10837 3.10837 -114.215 -3.10837 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0137714 0.0122685 110 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 1.86 vpr 64.40 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29768 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2572 1221 14583 4808 7640 2135 64.4 MiB 0.09 0.00 4.99767 4.51687 -145.067 -4.51687 4.51687 0.24 0.000323777 0.000296108 0.0247005 0.0224532 -1 -1 -1 -1 30 2687 23 6.64007e+06 364182 526063. 1820.29 0.39 0.0704651 0.0623808 22546 126617 -1 2135 17 1045 1588 103097 22969 3.25883 3.25883 -126.603 -3.25883 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0154776 0.0138331 148 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.07 vpr 64.78 MiB -1 -1 0.14 17696 1 0.03 -1 -1 29780 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2535 922 19223 5837 10520 2866 64.8 MiB 0.11 0.00 5.92827 4.77444 -136.955 -4.77444 4.77444 0.25 0.000376709 0.000347561 0.0371074 0.034053 -1 -1 -1 -1 28 2714 33 6.64007e+06 426972 500653. 1732.36 0.57 0.0952296 0.0848217 21970 115934 -1 2193 22 1709 2838 188317 48152 4.01303 4.01303 -131.661 -4.01303 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0173466 0.0155029 139 61 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.26 vpr 64.13 MiB -1 -1 0.12 17672 1 0.02 -1 -1 30240 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 24.9 MiB 0.05 1651 648 11064 3436 5196 2432 64.1 MiB 0.06 0.00 3.81299 3.12479 -88.8266 -3.12479 3.12479 0.26 0.00026897 0.00023978 0.0232876 0.0215518 -1 -1 -1 -1 32 1369 19 6.64007e+06 288834 554710. 1919.41 0.89 0.105223 0.0919344 22834 132086 -1 1104 15 627 1014 49151 13344 2.77777 2.77777 -84.3561 -2.77777 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.0103697 0.00930164 103 27 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 1.84 vpr 64.30 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 24.8 MiB 0.08 2380 942 16819 5830 8106 2883 64.3 MiB 0.09 0.00 4.6791 4.09527 -122.173 -4.09527 4.09527 0.23 0.000346698 0.000316608 0.0307314 0.0280788 -1 -1 -1 -1 32 2367 28 6.64007e+06 339066 554710. 1919.41 0.39 0.0804661 0.0715237 22834 132086 -1 1983 22 1455 2736 169045 42069 3.21356 3.21356 -117.004 -3.21356 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0201019 0.0179187 138 58 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 1.78 vpr 64.36 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29828 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2606 1192 12305 3184 7882 1239 64.4 MiB 0.07 0.00 5.47847 4.60407 -146.257 -4.60407 4.60407 0.23 0.000330363 0.000302451 0.0218624 0.0200378 -1 -1 -1 -1 32 2209 18 6.64007e+06 351624 554710. 1919.41 0.34 0.0628724 0.0559061 22834 132086 -1 2050 16 1144 1644 92509 23959 3.27883 3.27883 -126.125 -3.27883 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0139599 0.012587 144 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.37 vpr 64.11 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29644 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65648 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2093 899 12248 2945 8519 784 64.1 MiB 0.06 0.00 3.59784 2.85064 -103.682 -2.85064 2.85064 0.23 0.00031002 0.000284204 0.0183735 0.0167743 -1 -1 -1 -1 26 2006 25 6.64007e+06 426972 477104. 1650.88 0.82 0.101691 0.0889344 21682 110474 -1 1742 21 1124 1885 120447 29317 2.14431 2.14431 -98.4532 -2.14431 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152302 0.0135505 115 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.13 vpr 64.00 MiB -1 -1 0.11 17528 1 0.02 -1 -1 29752 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65532 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1535 603 7853 2116 5212 525 64.0 MiB 0.04 0.00 2.99233 2.39133 -77.851 -2.39133 2.39133 0.24 0.000231626 0.000212413 0.0147234 0.0135737 -1 -1 -1 -1 32 1129 17 6.64007e+06 213486 554710. 1919.41 0.86 0.0935232 0.0812611 22834 132086 -1 990 20 553 827 48112 12467 1.79471 1.79471 -72.575 -1.79471 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.0110231 0.00979166 85 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 1.76 vpr 64.60 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29800 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 31 32 291 243 1 171 87 17 17 289 -1 unnamed_device 24.5 MiB 0.15 2125 1026 10455 2663 6617 1175 64.6 MiB 0.06 0.00 6.02746 5.0168 -149.308 -5.0168 5.0168 0.23 0.000293444 0.000269173 0.0187775 0.0172066 -1 -1 -1 -1 30 2023 21 6.64007e+06 301392 526063. 1820.29 0.32 0.0582338 0.0515822 22546 126617 -1 1733 20 829 1237 65753 16555 3.62043 3.62043 -133.716 -3.62043 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0181583 0.0162736 127 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.76 vpr 64.73 MiB -1 -1 0.16 18436 1 0.03 -1 -1 29980 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 25.2 MiB 0.04 2331 1141 17961 5691 10386 1884 64.7 MiB 0.11 0.00 5.44296 4.13552 -132.934 -4.13552 4.13552 0.24 0.000351539 0.00032317 0.0368032 0.0340409 -1 -1 -1 -1 26 2527 22 6.64007e+06 464646 477104. 1650.88 1.27 0.152604 0.135082 21682 110474 -1 2212 22 1474 2442 179110 40191 3.73683 3.73683 -133.451 -3.73683 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0173672 0.0155182 140 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 2.89 vpr 64.85 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29712 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66404 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 24.9 MiB 0.25 2693 1197 9383 1945 6894 544 64.8 MiB 0.06 0.00 5.6841 4.62416 -139.043 -4.62416 4.62416 0.24 0.000343386 0.000314627 0.0172008 0.0157806 -1 -1 -1 -1 30 2804 24 6.64007e+06 389298 526063. 1820.29 1.14 0.12124 0.106579 22546 126617 -1 2221 19 1154 1858 115618 26985 3.82228 3.82228 -129.932 -3.82228 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0172664 0.0155995 151 62 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 1.96 vpr 63.86 MiB -1 -1 0.12 18056 1 0.02 -1 -1 30160 -1 -1 20 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65396 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1349 633 10868 3050 6437 1381 63.9 MiB 0.04 0.00 2.81093 2.39133 -70.7944 -2.39133 2.39133 0.23 0.000198641 0.000181079 0.0142663 0.0130218 -1 -1 -1 -1 26 1233 20 6.64007e+06 251160 477104. 1650.88 0.68 0.070323 0.0614049 21682 110474 -1 1121 19 523 781 49077 12394 1.95411 1.95411 -71.0211 -1.95411 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.0107949 0.00959479 81 30 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 1.78 vpr 64.57 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29764 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2052 991 13751 4633 6453 2665 64.6 MiB 0.07 0.00 4.97861 4.55404 -124.907 -4.55404 4.55404 0.25 0.000298608 0.000273835 0.0228545 0.0209681 -1 -1 -1 -1 32 2035 19 6.64007e+06 313950 554710. 1919.41 0.36 0.0657503 0.0584607 22834 132086 -1 1878 20 1138 2086 138403 31685 3.44803 3.44803 -114.756 -3.44803 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0144217 0.0128571 125 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.04 vpr 63.86 MiB -1 -1 0.11 17664 1 0.02 -1 -1 30076 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65388 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 24.7 MiB 0.03 1447 554 12331 4885 6406 1040 63.9 MiB 0.05 0.00 2.77793 2.35833 -70.3669 -2.35833 2.35833 0.24 0.000401366 0.000368701 0.0176975 0.0162144 -1 -1 -1 -1 28 1254 19 6.64007e+06 213486 500653. 1732.36 0.82 0.074078 0.0649612 21970 115934 -1 991 16 450 533 42691 11758 1.86191 1.86191 -70.1632 -1.86191 0 0 612192. 2118.31 0.02 0.02 0.06 -1 -1 0.02 0.00837099 0.00747193 82 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.55 vpr 64.57 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29764 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2081 918 9383 2172 5914 1297 64.6 MiB 0.05 0.00 5.31627 4.63183 -123.978 -4.63183 4.63183 0.24 0.000306745 0.000280355 0.0150318 0.0138059 -1 -1 -1 -1 30 2001 23 6.64007e+06 389298 526063. 1820.29 1.00 0.115117 0.10028 22546 126617 -1 1617 20 798 1425 79320 19609 3.37283 3.37283 -108.474 -3.37283 0 0 666494. 2306.21 0.04 0.05 0.12 -1 -1 0.04 0.0244901 0.0219357 126 24 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.28 vpr 64.39 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29948 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 24.6 MiB 0.03 2388 1070 19624 5823 11095 2706 64.4 MiB 0.10 0.00 4.70631 3.69341 -108.189 -3.69341 3.69341 0.23 0.000320509 0.00029285 0.0301434 0.0276299 -1 -1 -1 -1 28 2304 20 6.64007e+06 489762 500653. 1732.36 0.89 0.12607 0.111455 21970 115934 -1 2043 19 1110 2038 137544 38662 3.00917 3.00917 -107.4 -3.00917 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0143121 0.0128153 136 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.84 vpr 64.70 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30168 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 338 277 1 179 98 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2303 1088 17423 5246 9519 2658 64.7 MiB 0.09 0.00 5.78707 4.89043 -136.673 -4.89043 4.89043 0.24 0.000327236 0.000299569 0.0274047 0.0250913 -1 -1 -1 -1 26 2626 24 6.64007e+06 426972 477104. 1650.88 1.39 0.158323 0.139377 21682 110474 -1 2086 20 1058 1856 117209 27300 3.85983 3.85983 -129.261 -3.85983 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0157392 0.0140998 132 50 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.00 vpr 64.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29628 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 24.9 MiB 0.05 1848 932 9571 2445 6468 658 64.4 MiB 0.05 0.00 3.79099 3.02179 -103.859 -3.02179 3.02179 0.23 0.000290894 0.000267194 0.0165695 0.0152169 -1 -1 -1 -1 30 1784 18 6.64007e+06 263718 526063. 1820.29 0.65 0.0906451 0.0790376 22546 126617 -1 1601 19 736 1233 74070 17622 2.70797 2.70797 -101.892 -2.70797 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0137793 0.0123494 107 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.26 vpr 64.42 MiB -1 -1 0.12 17668 1 0.02 -1 -1 29852 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65964 30 32 262 227 1 135 86 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1630 675 10103 2270 6949 884 64.4 MiB 0.05 0.00 3.60179 3.24119 -95.5452 -3.24119 3.24119 0.23 0.00034986 0.000321242 0.0196118 0.0180662 -1 -1 -1 -1 30 1518 17 6.64007e+06 301392 526063. 1820.29 0.88 0.10414 0.0913886 22546 126617 -1 1212 20 661 1089 52330 13795 2.56257 2.56257 -89.8228 -2.56257 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0132004 0.0116361 100 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 1.76 vpr 64.43 MiB -1 -1 0.15 17668 1 0.03 -1 -1 29816 -1 -1 24 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 24.3 MiB 0.04 1853 868 11247 3492 5966 1789 64.4 MiB 0.07 0.00 4.1543 3.41886 -98.6687 -3.41886 3.41886 0.25 0.000328088 0.000304966 0.0270155 0.0250108 -1 -1 -1 -1 32 1674 22 6.64007e+06 301392 554710. 1919.41 0.34 0.0669298 0.0597058 22834 132086 -1 1544 22 868 1612 92339 21804 2.72157 2.72157 -97.0146 -2.72157 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0150226 0.0132339 104 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 2.35 vpr 64.43 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29816 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2077 943 13663 4291 7577 1795 64.4 MiB 0.06 0.00 4.55061 3.72021 -112.43 -3.72021 3.72021 0.24 0.00027512 0.000252672 0.0213097 0.0195023 -1 -1 -1 -1 26 2096 19 6.64007e+06 263718 477104. 1650.88 0.79 0.0898311 0.0787572 21682 110474 -1 1871 22 1227 1984 139135 31601 2.85597 2.85597 -110.575 -2.85597 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0139917 0.0124162 116 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.20 vpr 64.48 MiB -1 -1 0.13 17544 1 0.02 -1 -1 30152 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1915 918 11703 2893 8058 752 64.5 MiB 0.06 0.00 3.9659 3.50227 -105.619 -3.50227 3.50227 0.24 0.000276998 0.000253415 0.0163437 0.014946 -1 -1 -1 -1 32 1765 22 6.64007e+06 414414 554710. 1919.41 0.90 0.108379 0.0945088 22834 132086 -1 1550 19 732 1226 65350 16682 2.72157 2.72157 -100.584 -2.72157 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0126351 0.0112682 111 30 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.30 vpr 64.14 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29800 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65676 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2169 773 17273 5937 9206 2130 64.1 MiB 0.18 0.00 3.9379 3.3369 -101.534 -3.3369 3.3369 0.24 0.000761204 0.000704797 0.0671225 0.0623348 -1 -1 -1 -1 26 1968 20 6.64007e+06 389298 477104. 1650.88 0.86 0.144333 0.129123 21682 110474 -1 1572 20 922 1465 89723 22843 2.34097 2.34097 -89.7372 -2.34097 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0136178 0.012134 112 54 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 3.16 vpr 64.87 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29616 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66428 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2308 1232 18356 5288 9596 3472 64.9 MiB 0.09 0.00 4.83776 4.37413 -122.59 -4.37413 4.37413 0.25 0.000352344 0.000322425 0.0280539 0.025636 -1 -1 -1 -1 28 2975 26 6.64007e+06 527436 500653. 1732.36 1.76 0.14119 0.125231 21970 115934 -1 2412 18 1248 2439 162377 37472 3.48123 3.48123 -118.393 -3.48123 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.016007 0.0144134 158 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.55 vpr 64.89 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29744 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66448 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 25.5 MiB 0.07 2421 1023 18877 5825 10430 2622 64.9 MiB 0.11 0.00 4.51361 3.87558 -128.529 -3.87558 3.87558 0.23 0.000369261 0.000339114 0.0340034 0.0311586 -1 -1 -1 -1 32 2017 21 6.64007e+06 514878 554710. 1919.41 1.15 0.184919 0.162569 22834 132086 -1 1849 21 1444 2355 125874 31664 2.77177 2.77177 -110.96 -2.77177 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0176566 0.0158237 150 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.42 vpr 64.50 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29780 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 24.5 MiB 0.14 2417 918 9536 2320 6465 751 64.5 MiB 0.06 0.00 5.18307 4.35884 -128.706 -4.35884 4.35884 0.24 0.000284721 0.000261675 0.0198292 0.0182771 -1 -1 -1 -1 32 1849 20 6.64007e+06 288834 554710. 1919.41 0.90 0.111762 0.0974411 22834 132086 -1 1689 20 806 1172 74453 17829 3.22283 3.22283 -115.365 -3.22283 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0134962 0.0120415 114 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 1.89 vpr 64.34 MiB -1 -1 0.13 18052 1 0.04 -1 -1 29788 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65884 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2217 1122 16238 4882 9322 2034 64.3 MiB 0.09 0.00 4.8385 3.9971 -121.388 -3.9971 3.9971 0.23 0.000336917 0.000307579 0.0286334 0.0261744 -1 -1 -1 -1 32 2344 20 6.64007e+06 364182 554710. 1919.41 0.36 0.0728185 0.0646739 22834 132086 -1 2088 23 1449 2642 147498 35841 3.12137 3.12137 -116.821 -3.12137 0 0 701300. 2426.64 0.03 0.05 0.10 -1 -1 0.03 0.0194932 0.0173853 145 61 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.22 vpr 64.95 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29756 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 31 32 377 302 1 233 99 17 17 289 -1 unnamed_device 25.2 MiB 0.24 2995 1421 19707 5440 12139 2128 64.9 MiB 0.11 0.00 7.81519 5.67793 -171.305 -5.67793 5.67793 0.23 0.000346066 0.000316676 0.0325169 0.0297691 -1 -1 -1 -1 28 3277 23 6.64007e+06 452088 500653. 1732.36 0.61 0.104355 0.0932129 21970 115934 -1 2581 21 1555 2326 136329 33259 4.52274 4.52274 -159.537 -4.52274 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.018193 0.0163931 178 64 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.73 vpr 64.90 MiB -1 -1 0.24 18056 1 0.03 -1 -1 29784 -1 -1 32 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66456 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 25.2 MiB 0.20 2681 1319 14999 4569 8381 2049 64.9 MiB 0.09 0.00 6.40882 5.22399 -160.729 -5.22399 5.22399 0.25 0.000373524 0.000343579 0.0331096 0.0307403 -1 -1 -1 -1 32 2679 17 6.64007e+06 401856 554710. 1919.41 0.96 0.122984 0.109251 22834 132086 -1 2354 19 1056 1619 130226 28911 4.31108 4.31108 -149.075 -4.31108 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0237688 0.0214486 167 64 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.39 vpr 64.77 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30124 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2150 1128 15412 3921 9377 2114 64.8 MiB 0.08 0.00 5.33427 4.63507 -135.372 -4.63507 4.63507 0.23 0.000329383 0.000301672 0.0241206 0.0220879 -1 -1 -1 -1 30 2296 22 6.64007e+06 464646 526063. 1820.29 0.94 0.132554 0.115834 22546 126617 -1 2016 22 1100 1926 104277 24750 3.19762 3.19762 -115.815 -3.19762 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0177833 0.0158452 140 55 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.60 vpr 64.61 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30148 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 291 242 1 179 91 17 17 289 -1 unnamed_device 24.5 MiB 0.19 2447 1083 8863 2197 6096 570 64.6 MiB 0.05 0.00 5.56996 4.45012 -118.426 -4.45012 4.45012 0.25 0.000299359 0.000274949 0.0144886 0.0132926 -1 -1 -1 -1 32 2169 21 6.64007e+06 339066 554710. 1919.41 0.92 0.11342 0.0992661 22834 132086 -1 1944 22 951 1417 84928 20855 3.51243 3.51243 -111.872 -3.51243 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0149971 0.0133682 124 27 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 2.52 vpr 65.09 MiB -1 -1 0.13 17668 1 0.03 -1 -1 29868 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 25.2 MiB 0.10 3200 1325 22371 6342 13589 2440 65.1 MiB 0.14 0.00 6.26139 5.1195 -164.675 -5.1195 5.1195 0.23 0.0004489 0.000412219 0.0433974 0.0398984 -1 -1 -1 -1 28 3170 21 6.64007e+06 539994 500653. 1732.36 1.01 0.166744 0.147094 21970 115934 -1 2626 19 1703 2722 167391 39031 4.00549 4.00549 -146.496 -4.00549 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0228447 0.0204446 176 87 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 1.70 vpr 64.06 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29676 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65596 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2009 855 10481 2942 6568 971 64.1 MiB 0.06 0.00 4.5869 3.77367 -103.344 -3.77367 3.77367 0.24 0.000271845 0.000248737 0.0209896 0.0193119 -1 -1 -1 -1 32 1689 18 6.64007e+06 288834 554710. 1919.41 0.32 0.0563517 0.0499083 22834 132086 -1 1523 18 785 1365 80306 19202 2.76057 2.76057 -98.8257 -2.76057 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0123234 0.0110592 104 28 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 1.88 vpr 64.25 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30236 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 24.7 MiB 0.15 2890 1252 16081 4637 9397 2047 64.2 MiB 0.10 0.00 6.34307 5.14733 -154.615 -5.14733 5.14733 0.24 0.000368948 0.00034104 0.0275732 0.0253414 -1 -1 -1 -1 30 2475 23 6.64007e+06 426972 526063. 1820.29 0.39 0.0714749 0.0637398 22546 126617 -1 2096 16 1084 1657 88851 21305 3.68189 3.68189 -130.335 -3.68189 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0145065 0.0130876 149 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.98 vpr 64.76 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29612 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 349 284 1 182 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2675 1103 12240 2946 8556 738 64.8 MiB 0.07 0.00 4.99666 3.95307 -115.476 -3.95307 3.95307 0.24 0.000333577 0.000303121 0.0217054 0.0198476 -1 -1 -1 -1 26 2701 22 6.64007e+06 477204 477104. 1650.88 1.63 0.165153 0.14533 21682 110474 -1 2200 19 1260 2288 139167 34153 3.10737 3.10737 -113.433 -3.10737 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0155087 0.0138955 136 53 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 1.77 vpr 64.59 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29776 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1813 1148 12127 3848 6621 1658 64.6 MiB 0.07 0.00 4.79356 4.19256 -126.138 -4.19256 4.19256 0.24 0.000295337 0.000269636 0.0215588 0.0198294 -1 -1 -1 -1 32 2151 21 6.64007e+06 339066 554710. 1919.41 0.43 0.0824346 0.0732441 22834 132086 -1 1914 22 904 1746 107845 24237 3.45223 3.45223 -118.392 -3.45223 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.015861 0.0141677 127 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.07 vpr 64.82 MiB -1 -1 0.14 18052 1 0.03 -1 -1 30168 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 353 287 1 198 95 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2414 1205 15647 4038 9814 1795 64.8 MiB 0.11 0.00 5.52647 4.90352 -143.647 -4.90352 4.90352 0.25 0.0008019 0.000745825 0.0364362 0.033814 -1 -1 -1 -1 28 2686 18 6.64007e+06 389298 500653. 1732.36 0.39 0.0847936 0.0764764 21970 115934 -1 2410 18 1295 1758 111267 27132 3.30283 3.30283 -125.331 -3.30283 0 0 612192. 2118.31 0.02 0.07 0.10 -1 -1 0.02 0.02999 0.026759 142 55 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 2.65 vpr 64.80 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29828 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2461 1024 18178 5514 9376 3288 64.8 MiB 0.09 0.00 4.3595 3.73184 -117.882 -3.73184 3.73184 0.23 0.000342503 0.000313459 0.0274297 0.0250706 -1 -1 -1 -1 28 2934 24 6.64007e+06 489762 500653. 1732.36 1.24 0.134412 0.118217 21970 115934 -1 2157 20 1301 2160 149192 38424 3.16237 3.16237 -119.152 -3.16237 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0170942 0.0152499 139 55 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.02 vpr 64.38 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30240 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 24.9 MiB 0.10 2721 1115 21088 6199 11891 2998 64.4 MiB 0.14 0.00 5.01327 4.29207 -130.428 -4.29207 4.29207 0.25 0.000354017 0.000323912 0.0461859 0.0427932 -1 -1 -1 -1 28 2739 18 6.64007e+06 502320 500653. 1732.36 0.52 0.101778 0.0916839 21970 115934 -1 2203 21 1389 2324 157732 36229 3.12137 3.12137 -119.153 -3.12137 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176308 0.0157409 149 62 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 3.47 vpr 64.60 MiB -1 -1 0.18 17672 1 0.03 -1 -1 30132 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 25.2 MiB 0.06 1947 873 16108 4476 7806 3826 64.6 MiB 0.07 0.00 4.78256 4.34576 -121.313 -4.34576 4.34576 0.23 0.000306518 0.000280534 0.0227357 0.0207675 -1 -1 -1 -1 30 2090 25 6.64007e+06 452088 526063. 1820.29 1.86 0.113549 0.0993707 22546 126617 -1 1553 21 1051 1873 98927 27703 4.05503 4.05503 -119.589 -4.05503 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0151484 0.0135515 127 24 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 1.86 vpr 64.32 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29572 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 319 257 1 198 92 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2350 1149 11684 3237 7258 1189 64.3 MiB 0.07 0.00 6.11266 5.05904 -138.884 -5.05904 5.05904 0.23 0.000310168 0.000284344 0.0194827 0.0178456 -1 -1 -1 -1 32 2297 18 6.64007e+06 351624 554710. 1919.41 0.33 0.0597045 0.0529702 22834 132086 -1 2103 18 1068 1607 98345 23408 3.70662 3.70662 -126.282 -3.70662 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0145917 0.0131743 137 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 1.83 vpr 64.86 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30156 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2921 1233 9543 2186 6591 766 64.9 MiB 0.07 0.00 6.45652 5.2717 -153.789 -5.2717 5.2717 0.23 0.000341115 0.000312552 0.0185871 0.0170812 -1 -1 -1 -1 28 2872 24 6.64007e+06 376740 500653. 1732.36 0.39 0.0660029 0.0583999 21970 115934 -1 2431 24 1612 2594 167132 39590 4.02948 4.02948 -138.297 -4.02948 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0191265 0.0170798 151 62 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.47 vpr 64.84 MiB -1 -1 0.13 18048 1 0.03 -1 -1 30132 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2687 1076 16523 6080 8261 2182 64.8 MiB 0.10 0.00 5.30485 4.45447 -137.456 -4.45447 4.45447 0.23 0.000353272 0.000322898 0.0342221 0.0314022 -1 -1 -1 -1 32 2442 17 6.64007e+06 313950 554710. 1919.41 0.97 0.128817 0.11348 22834 132086 -1 2010 18 1272 2259 134813 32070 3.47843 3.47843 -125.006 -3.47843 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0187106 0.0168733 141 77 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 1.60 vpr 64.16 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29792 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65696 32 32 251 219 1 140 91 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1818 889 8659 1974 6034 651 64.2 MiB 0.05 0.00 3.7947 3.57147 -104.095 -3.57147 3.57147 0.23 0.000261867 0.000239075 0.0134388 0.0123337 -1 -1 -1 -1 28 1905 21 6.64007e+06 339066 500653. 1732.36 0.33 0.0523148 0.0459728 21970 115934 -1 1631 21 853 1375 86391 21527 2.77477 2.77477 -97.2385 -2.77477 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0138134 0.0123514 101 23 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.59 vpr 64.23 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29420 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 24.9 MiB 0.18 2440 999 7231 1434 5468 329 64.2 MiB 0.06 0.00 5.00545 4.0787 -137.534 -4.0787 4.0787 0.25 0.000462463 0.000411606 0.0167471 0.0154013 -1 -1 -1 -1 26 2717 42 6.64007e+06 339066 477104. 1650.88 1.09 0.111643 0.0977058 21682 110474 -1 2232 21 1443 2087 144175 36536 3.38903 3.38903 -135.561 -3.38903 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0161341 0.0143439 133 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 1.94 vpr 64.99 MiB -1 -1 0.12 18676 1 0.03 -1 -1 30196 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66548 32 32 387 293 1 234 98 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2841 1439 17873 5142 10318 2413 65.0 MiB 0.11 0.00 6.57692 5.56526 -164.086 -5.56526 5.56526 0.24 0.000362134 0.000331955 0.0320601 0.0294007 -1 -1 -1 -1 32 2821 20 6.64007e+06 426972 554710. 1919.41 0.38 0.0829831 0.0739859 22834 132086 -1 2555 20 1454 2329 127947 31765 4.32308 4.32308 -149.736 -4.32308 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0193231 0.0173864 174 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.28 vpr 64.72 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29928 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66276 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2567 1021 10336 2399 7366 571 64.7 MiB 0.06 0.00 5.11912 4.26806 -134.06 -4.26806 4.26806 0.23 0.000334349 0.000304198 0.0160871 0.0147197 -1 -1 -1 -1 30 2164 19 6.64007e+06 477204 526063. 1820.29 0.92 0.113507 0.0996864 22546 126617 -1 1765 18 985 1626 87746 21380 2.84497 2.84497 -113.29 -2.84497 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0148181 0.0133477 141 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 1.72 vpr 64.52 MiB -1 -1 0.18 17672 1 0.02 -1 -1 30240 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2182 743 10679 2942 6832 905 64.5 MiB 0.05 0.00 4.2965 3.52427 -104.21 -3.52427 3.52427 0.25 0.000284469 0.000260517 0.0152668 0.0139714 -1 -1 -1 -1 32 1599 16 6.64007e+06 414414 554710. 1919.41 0.31 0.0492061 0.0433694 22834 132086 -1 1397 17 644 1197 65700 16378 2.71257 2.71257 -96.443 -2.71257 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0125154 0.0112655 111 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.00 vpr 65.11 MiB -1 -1 0.18 18440 1 0.03 -1 -1 29996 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 431 332 1 235 95 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2995 1451 16943 5312 9314 2317 65.1 MiB 0.14 0.00 7.55549 6.37067 -184.872 -6.37067 6.37067 0.25 0.000439913 0.000406748 0.0454496 0.0419737 -1 -1 -1 -1 32 3012 21 6.64007e+06 389298 554710. 1919.41 1.27 0.189098 0.167098 22834 132086 -1 2523 19 1586 2324 142907 33660 5.14455 5.14455 -172.168 -5.14455 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0191733 0.0172741 177 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.58 vpr 64.71 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30356 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1956 1035 13668 3578 8233 1857 64.7 MiB 0.08 0.00 5.19907 4.58683 -138.182 -4.58683 4.58683 0.24 0.000338718 0.000311084 0.0250615 0.0230519 -1 -1 -1 -1 28 2405 23 6.64007e+06 477204 500653. 1732.36 1.17 0.125233 0.110063 21970 115934 -1 2035 19 1349 2237 141237 33242 3.66243 3.66243 -129.496 -3.66243 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0159444 0.0143778 136 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.01 vpr 64.10 MiB -1 -1 0.10 17672 1 0.02 -1 -1 29932 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65640 32 32 231 199 1 140 91 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1906 764 9067 2085 6178 804 64.1 MiB 0.05 0.00 4.2445 3.5653 -97.5026 -3.5653 3.5653 0.23 0.000250471 0.000229596 0.0128699 0.011824 -1 -1 -1 -1 26 1747 20 6.64007e+06 339066 477104. 1650.88 0.78 0.0916771 0.079558 21682 110474 -1 1553 18 736 1243 69356 18200 3.03517 3.03517 -99.0581 -3.03517 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0114051 0.0102012 103 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.25 vpr 64.42 MiB -1 -1 0.11 17912 1 0.03 -1 -1 29820 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2540 1175 11816 2954 8205 657 64.4 MiB 0.07 0.00 6.69892 5.65147 -139.258 -5.65147 5.65147 0.23 0.000343487 0.000315207 0.018729 0.0171086 -1 -1 -1 -1 28 2581 21 6.64007e+06 502320 500653. 1732.36 0.91 0.119022 0.104048 21970 115934 -1 2231 19 1018 2155 132770 30621 4.27588 4.27588 -130.562 -4.27588 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0157386 0.0141662 147 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.20 vpr 64.39 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29800 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 24.5 MiB 0.03 2164 893 10263 2683 6663 917 64.4 MiB 0.06 0.00 4.3277 3.5273 -108.396 -3.5273 3.5273 0.24 0.000311698 0.000287949 0.0177608 0.0162611 -1 -1 -1 -1 32 1749 18 6.64007e+06 288834 554710. 1919.41 0.91 0.101392 0.0881871 22834 132086 -1 1533 20 784 1238 71387 17120 2.77177 2.77177 -103.397 -2.77177 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0129162 0.0115158 107 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 1.81 vpr 64.39 MiB -1 -1 0.13 17908 1 0.03 -1 -1 29836 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2117 911 17732 5400 9784 2548 64.4 MiB 0.08 0.00 5.13641 4.09995 -112.419 -4.09995 4.09995 0.28 0.000286035 0.000255044 0.0231712 0.0210843 -1 -1 -1 -1 28 1992 21 6.64007e+06 477204 500653. 1732.36 0.38 0.0635272 0.0563098 21970 115934 -1 1710 18 975 1883 102536 25450 2.74837 2.74837 -101.654 -2.74837 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0128309 0.0114514 110 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 2.43 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 30 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 29 32 355 287 1 198 91 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2698 1076 9679 2548 6094 1037 64.8 MiB 0.06 0.00 5.53367 4.61203 -130.625 -4.61203 4.61203 0.23 0.000338658 0.000311571 0.0192196 0.0176251 -1 -1 -1 -1 32 2459 22 6.64007e+06 376740 554710. 1919.41 0.99 0.129037 0.112919 22834 132086 -1 2073 18 1299 1977 111378 28075 3.37503 3.37503 -116.489 -3.37503 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0154722 0.0139398 146 62 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 1.96 vpr 64.73 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29784 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1949 947 7639 1677 5525 437 64.7 MiB 0.05 0.00 5.24456 4.53352 -139.004 -4.53352 4.53352 0.25 0.000332698 0.00030496 0.0143265 0.0131711 -1 -1 -1 -1 32 2009 19 6.64007e+06 339066 554710. 1919.41 0.49 0.0942014 0.0834076 22834 132086 -1 1774 21 1241 1905 118138 28466 3.74782 3.74782 -129.815 -3.74782 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0215813 0.0193967 135 54 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 1.84 vpr 64.76 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29752 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 25.2 MiB 0.13 2440 1011 14498 3923 8676 1899 64.8 MiB 0.08 0.00 5.77607 4.82681 -139.307 -4.82681 4.82681 0.23 0.000370343 0.000327299 0.0234924 0.0214514 -1 -1 -1 -1 32 2255 19 6.64007e+06 426972 554710. 1919.41 0.34 0.0668056 0.0594183 22834 132086 -1 1902 18 994 1738 88852 22474 4.06723 4.06723 -132.101 -4.06723 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0149293 0.013428 136 51 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.78 vpr 64.15 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29784 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 24.5 MiB 0.22 1928 770 5189 970 3673 546 64.2 MiB 0.03 0.00 5.21395 4.75032 -127.226 -4.75032 4.75032 0.24 0.000282943 0.000258953 0.0093242 0.0085679 -1 -1 -1 -1 28 2312 21 6.64007e+06 276276 500653. 1732.36 1.22 0.102145 0.0888686 21970 115934 -1 1617 18 803 1095 74187 19482 3.17683 3.17683 -111.986 -3.17683 0 0 612192. 2118.31 0.02 0.03 0.07 -1 -1 0.02 0.0160528 0.0144005 107 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.48 vpr 64.59 MiB -1 -1 0.12 18292 1 0.03 -1 -1 30320 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 31 32 319 272 1 169 86 17 17 289 -1 unnamed_device 25.1 MiB 0.12 2149 981 13694 3750 8080 1864 64.6 MiB 0.07 0.00 4.95096 4.00653 -127.945 -4.00653 4.00653 0.23 0.000296843 0.000271587 0.0257813 0.023674 -1 -1 -1 -1 32 1939 22 6.64007e+06 288834 554710. 1919.41 0.92 0.12807 0.111978 22834 132086 -1 1753 19 1043 1582 90723 22601 3.22583 3.22583 -119.839 -3.22583 0 0 701300. 2426.64 0.03 0.03 0.13 -1 -1 0.03 0.0144012 0.0128713 116 64 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.22 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30116 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2322 929 9548 2022 6797 729 64.6 MiB 0.05 0.00 4.3867 3.5433 -97.7345 -3.5433 3.5433 0.23 0.000315462 0.000287317 0.0152887 0.0139914 -1 -1 -1 -1 32 1970 20 6.64007e+06 452088 554710. 1919.41 0.89 0.111736 0.0971106 22834 132086 -1 1630 17 815 1410 71619 17962 2.64857 2.64857 -94.6457 -2.64857 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0141874 0.0127433 128 57 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.61 vpr 64.55 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29804 -1 -1 39 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1932 905 16515 4803 9135 2577 64.5 MiB 0.12 0.00 5.16736 4.19576 -104.869 -4.19576 4.19576 0.25 0.000632614 0.000587453 0.0403436 0.0370875 -1 -1 -1 -1 26 2022 22 6.64007e+06 489762 477104. 1650.88 1.09 0.130341 0.115208 21682 110474 -1 1822 20 1097 2083 117673 28230 3.55243 3.55243 -105.89 -3.55243 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0187176 0.0166672 122 27 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 1.68 vpr 64.55 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29788 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 30 32 317 269 1 152 83 17 17 289 -1 unnamed_device 24.5 MiB 0.07 1992 820 8003 2033 5428 542 64.5 MiB 0.05 0.00 4.60481 3.90078 -115.378 -3.90078 3.90078 0.23 0.000302657 0.000277024 0.0153228 0.0140736 -1 -1 -1 -1 32 1752 22 6.64007e+06 263718 554710. 1919.41 0.34 0.0557821 0.0493271 22834 132086 -1 1562 19 1039 1837 109271 27109 2.78277 2.78277 -104.529 -2.78277 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0140966 0.0125822 115 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 2.41 vpr 64.68 MiB -1 -1 0.17 18052 1 0.03 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2267 1041 7728 1594 5511 623 64.7 MiB 0.05 0.00 4.51839 3.97836 -130.923 -3.97836 3.97836 0.23 0.000320385 0.000287586 0.0151298 0.0139414 -1 -1 -1 -1 28 2450 20 6.64007e+06 326508 500653. 1732.36 0.96 0.121822 0.106713 21970 115934 -1 2048 20 1250 1844 127691 29643 3.29503 3.29503 -126.978 -3.29503 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0153238 0.0137008 127 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.43 vpr 64.59 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29920 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2060 1087 14716 3609 8495 2612 64.6 MiB 0.08 0.00 5.23607 4.60801 -131.451 -4.60801 4.60801 0.24 0.000305422 0.000279931 0.0231359 0.0211931 -1 -1 -1 -1 30 2215 19 6.64007e+06 464646 526063. 1820.29 1.06 0.136734 0.120549 22546 126617 -1 1958 23 1056 1969 119309 26451 3.47322 3.47322 -117.132 -3.47322 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0158791 0.0141618 134 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 1.92 vpr 64.80 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29936 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 350 275 1 209 93 17 17 289 -1 unnamed_device 25.0 MiB 0.15 2681 1037 9753 2581 5955 1217 64.8 MiB 0.07 0.00 6.01073 5.18024 -156.404 -5.18024 5.18024 0.24 0.000336837 0.000308978 0.0215031 0.0199073 -1 -1 -1 -1 32 2480 23 6.64007e+06 364182 554710. 1919.41 0.42 0.0729427 0.0649708 22834 132086 -1 2043 17 1212 1843 105388 26002 4.27189 4.27189 -143.17 -4.27189 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0155817 0.0140506 151 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 2.78 vpr 64.84 MiB -1 -1 0.16 18052 1 0.03 -1 -1 29820 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2633 929 18196 5476 8417 4303 64.8 MiB 0.08 0.00 5.68167 4.5876 -139.046 -4.5876 4.5876 0.23 0.000362423 0.000326394 0.0296245 0.0269269 -1 -1 -1 -1 34 2649 32 6.64007e+06 464646 585099. 2024.56 1.32 0.155351 0.136509 23122 138558 -1 1938 22 1357 2352 167798 52522 3.76663 3.76663 -127.254 -3.76663 0 0 742403. 2568.87 0.03 0.05 0.08 -1 -1 0.03 0.0180392 0.0161401 143 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 2.96 vpr 64.88 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30224 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66436 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2914 1203 17817 4991 10319 2507 64.9 MiB 0.09 0.00 5.86707 4.47484 -142.898 -4.47484 4.47484 0.23 0.000359612 0.000326009 0.0272184 0.0247497 -1 -1 -1 -1 26 2975 23 6.64007e+06 539994 477104. 1650.88 1.56 0.12861 0.113349 21682 110474 -1 2473 21 1636 3093 192512 45419 3.88183 3.88183 -138.131 -3.88183 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.017884 0.0159925 147 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 1.71 vpr 64.47 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29852 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66020 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 24.3 MiB 0.07 1992 827 11963 3673 6023 2267 64.5 MiB 0.06 0.00 4.80601 3.86158 -112.965 -3.86158 3.86158 0.23 0.000449703 0.000425374 0.0237691 0.022019 -1 -1 -1 -1 32 1758 20 6.64007e+06 263718 554710. 1919.41 0.33 0.060739 0.0541405 22834 132086 -1 1584 20 900 1546 91449 21952 2.74357 2.74357 -100.335 -2.74357 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.015396 0.0137804 109 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 2.41 vpr 64.81 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30148 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 24.9 MiB 0.11 2027 1031 14741 4291 8504 1946 64.8 MiB 0.09 0.00 5.46127 4.75724 -139.41 -4.75724 4.75724 0.25 0.00034081 0.000312004 0.0309057 0.0283983 -1 -1 -1 -1 28 2442 23 6.64007e+06 339066 500653. 1732.36 0.80 0.136583 0.120041 21970 115934 -1 2156 21 1668 2701 170774 41593 4.08103 4.08103 -135.525 -4.08103 0 0 612192. 2118.31 0.04 0.08 0.11 -1 -1 0.04 0.0328061 0.0292899 147 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 2.69 vpr 64.76 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30236 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 24.9 MiB 0.15 2563 1179 8401 1845 5726 830 64.8 MiB 0.05 0.00 6.4762 5.43878 -158.127 -5.43878 5.43878 0.24 0.000339119 0.000311131 0.0150216 0.0138245 -1 -1 -1 -1 28 2965 25 6.64007e+06 376740 500653. 1732.36 1.19 0.120148 0.105622 21970 115934 -1 2377 19 1306 2106 150947 36744 4.09669 4.09669 -142.216 -4.09669 0 0 612192. 2118.31 0.04 0.07 0.09 -1 -1 0.04 0.0253964 0.0228129 145 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 2.49 vpr 64.77 MiB -1 -1 0.15 17852 1 0.03 -1 -1 30196 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 24.9 MiB 0.17 2657 1228 12698 3369 8227 1102 64.8 MiB 0.07 0.00 6.49901 5.45438 -153.019 -5.45438 5.45438 0.24 0.000328689 0.000301312 0.0205704 0.0188312 -1 -1 -1 -1 28 2672 21 6.64007e+06 439530 500653. 1732.36 0.93 0.119834 0.105177 21970 115934 -1 2273 20 1393 2173 133451 33025 4.68168 4.68168 -150.535 -4.68168 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.018244 0.0164405 152 47 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.04 vpr 64.82 MiB -1 -1 0.19 17908 1 0.03 -1 -1 30140 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2368 1088 19124 5773 11033 2318 64.8 MiB 0.10 0.00 5.27727 4.45304 -133.741 -4.45304 4.45304 0.33 0.000340028 0.000311762 0.0308833 0.0282403 -1 -1 -1 -1 32 2027 17 6.64007e+06 477204 554710. 1919.41 0.34 0.0763852 0.0678982 22834 132086 -1 1840 18 828 1458 87897 20192 2.99843 2.99843 -114.489 -2.99843 0 0 701300. 2426.64 0.03 0.03 0.09 -1 -1 0.03 0.0156678 0.0141019 144 83 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 2.56 vpr 64.62 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29764 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 25.2 MiB 0.12 2717 1084 11771 2992 7832 947 64.6 MiB 0.08 0.00 6.07747 5.03001 -142.129 -5.03001 5.03001 0.24 0.000341787 0.000313273 0.0256136 0.0235617 -1 -1 -1 -1 32 2400 18 6.64007e+06 313950 554710. 1919.41 1.03 0.132022 0.115711 22834 132086 -1 2204 17 1217 2211 124731 29809 3.86283 3.86283 -134.875 -3.86283 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152233 0.0137184 141 57 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 1.75 vpr 64.43 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29736 -1 -1 38 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 29 32 378 310 1 177 99 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2434 959 18567 5802 9719 3046 64.4 MiB 0.10 0.00 5.08141 4.25424 -118.37 -4.25424 4.25424 0.24 0.000348555 0.000319788 0.0336972 0.0310577 -1 -1 -1 -1 32 1868 18 6.64007e+06 477204 554710. 1919.41 0.35 0.0778854 0.0696741 22834 132086 -1 1742 19 1067 1824 102169 25222 2.96197 2.96197 -106.132 -2.96197 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0166391 0.0149238 137 85 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 1.62 vpr 64.12 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29928 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65656 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1776 737 8003 1763 5996 244 64.1 MiB 0.04 0.00 4.47141 3.88758 -112.726 -3.88758 3.88758 0.24 0.000260941 0.000238488 0.0130657 0.0119905 -1 -1 -1 -1 28 1687 18 6.64007e+06 238602 500653. 1732.36 0.33 0.0470139 0.0415744 21970 115934 -1 1415 17 749 1150 66721 17748 2.93797 2.93797 -105.31 -2.93797 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0114493 0.0102428 99 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 1.96 vpr 64.79 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29772 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 25.3 MiB 0.11 2455 1051 10131 2558 6985 588 64.8 MiB 0.06 0.00 5.67067 4.66023 -138.505 -4.66023 4.66023 0.23 0.000342724 0.000314219 0.0174902 0.0160199 -1 -1 -1 -1 32 2099 20 6.64007e+06 439530 554710. 1919.41 0.36 0.0663895 0.058967 22834 132086 -1 1859 21 1036 1822 107535 26414 3.73983 3.73983 -129.269 -3.73983 0 0 701300. 2426.64 0.04 0.07 0.12 -1 -1 0.04 0.0301792 0.0272055 135 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 1.84 vpr 64.88 MiB -1 -1 0.13 17444 1 0.03 -1 -1 30116 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66432 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2786 978 14939 5098 7315 2526 64.9 MiB 0.09 0.00 5.96407 4.77924 -147.588 -4.77924 4.77924 0.23 0.000358013 0.000327645 0.0296295 0.0271703 -1 -1 -1 -1 32 2301 21 6.64007e+06 313950 554710. 1919.41 0.36 0.0769698 0.0685732 22834 132086 -1 1890 22 1749 2967 165614 41703 3.75843 3.75843 -135.029 -3.75843 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0205468 0.0184283 155 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 1.73 vpr 64.52 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66068 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 24.5 MiB 0.14 2060 1019 8999 2097 6268 634 64.5 MiB 0.05 0.00 5.08536 4.17772 -116.047 -4.17772 4.17772 0.23 0.000432787 0.000408561 0.0145659 0.0133905 -1 -1 -1 -1 26 2304 22 6.64007e+06 313950 477104. 1650.88 0.31 0.0518409 0.0456961 21682 110474 -1 1979 15 909 1262 86214 21433 3.35623 3.35623 -114.421 -3.35623 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0116363 0.0104526 117 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 2.18 vpr 63.69 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30320 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65216 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 23.9 MiB 0.04 2077 870 15017 4767 7797 2453 63.7 MiB 0.07 0.00 4.82101 3.80732 -109.576 -3.80732 3.80732 0.25 0.000256941 0.000235154 0.022651 0.0207191 -1 -1 -1 -1 30 1774 18 6.64007e+06 288834 526063. 1820.29 0.87 0.101667 0.0884464 22546 126617 -1 1499 20 971 1627 84799 20654 2.75457 2.75457 -100.629 -2.75457 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0128585 0.011425 110 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 3.07 vpr 64.81 MiB -1 -1 0.13 17908 1 0.03 -1 -1 30380 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 348 274 1 211 94 17 17 289 -1 unnamed_device 24.9 MiB 0.14 2693 1116 13726 3780 8585 1361 64.8 MiB 0.09 0.00 6.31933 5.03147 -151.742 -5.03147 5.03147 0.26 0.000340195 0.000312031 0.0263611 0.0242555 -1 -1 -1 -1 26 3082 38 6.64007e+06 376740 477104. 1650.88 1.57 0.135113 0.119158 21682 110474 -1 2413 18 1436 1908 121395 30312 4.28008 4.28008 -150.977 -4.28008 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0157398 0.0141925 151 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 3.12 vpr 64.84 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29864 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66400 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 24.9 MiB 0.23 2455 1138 17726 5560 9419 2747 64.8 MiB 0.09 0.00 6.43337 5.25633 -153.723 -5.25633 5.25633 0.24 0.00033534 0.000306284 0.0271419 0.0248337 -1 -1 -1 -1 28 2970 26 6.64007e+06 464646 500653. 1732.36 1.21 0.137274 0.12092 21970 115934 -1 2282 20 1151 1899 136719 33457 4.29708 4.29708 -142.574 -4.29708 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176497 0.0158217 157 56 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.77 vpr 64.82 MiB -1 -1 0.12 17908 1 0.03 -1 -1 30172 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2789 1287 17058 4718 10081 2259 64.8 MiB 0.11 0.00 6.50947 5.53806 -146.188 -5.53806 5.53806 0.34 0.000845223 0.000792687 0.0343809 0.0317838 -1 -1 -1 -1 30 2736 22 6.64007e+06 539994 526063. 1820.29 1.15 0.160837 0.141766 22546 126617 -1 2231 22 1148 2273 135275 29822 4.48228 4.48228 -138.994 -4.48228 0 0 666494. 2306.21 0.04 0.10 0.10 -1 -1 0.04 0.0419782 0.0376554 162 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 1.72 vpr 64.60 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30204 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 30 32 316 264 1 162 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2263 842 16298 4881 8912 2505 64.6 MiB 0.08 0.00 4.4797 3.59647 -102.523 -3.59647 3.59647 0.23 0.000307307 0.000280621 0.0251614 0.0229662 -1 -1 -1 -1 32 1785 20 6.64007e+06 452088 554710. 1919.41 0.34 0.0656727 0.0582729 22834 132086 -1 1466 19 1042 1950 89350 23678 2.76377 2.76377 -94.1745 -2.76377 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0187442 0.0167254 124 52 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.16 vpr 63.77 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30148 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 27 32 255 219 1 132 82 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1707 787 11296 3601 6010 1685 63.8 MiB 0.05 0.00 4.4859 3.4653 -97.6029 -3.4653 3.4653 0.23 0.000259889 0.000238275 0.0182365 0.0167452 -1 -1 -1 -1 32 1511 19 6.64007e+06 288834 554710. 1919.41 0.87 0.102496 0.0888358 22834 132086 -1 1326 21 866 1379 78231 19198 2.71397 2.71397 -92.9443 -2.71397 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0130114 0.0115292 100 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 2.68 vpr 65.09 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30116 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66648 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 25.2 MiB 0.14 3118 1444 14498 4090 9211 1197 65.1 MiB 0.10 0.00 5.55196 4.5101 -140.741 -4.5101 4.5101 0.23 0.000398638 0.000366161 0.0272928 0.0249945 -1 -1 -1 -1 30 3465 22 6.64007e+06 426972 526063. 1820.29 1.05 0.136378 0.119849 22546 126617 -1 2722 21 1607 2624 142172 32764 3.65863 3.65863 -130.646 -3.65863 0 0 666494. 2306.21 0.04 0.06 0.12 -1 -1 0.04 0.0258273 0.0233244 176 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 2.80 vpr 64.80 MiB -1 -1 0.13 18044 1 0.03 -1 -1 29768 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 25.2 MiB 0.23 2629 1132 9336 2424 6148 764 64.8 MiB 0.06 0.00 6.80513 5.51727 -161.811 -5.51727 5.51727 0.24 0.000362914 0.000323191 0.0180721 0.016584 -1 -1 -1 -1 28 2466 20 6.64007e+06 339066 500653. 1732.36 1.25 0.174434 0.153503 21970 115934 -1 2101 19 1237 2000 130018 29929 4.16568 4.16568 -143.37 -4.16568 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0161927 0.0145835 151 64 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 1.88 vpr 64.64 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30324 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 331 280 1 174 87 17 17 289 -1 unnamed_device 24.9 MiB 0.20 2094 1015 14679 4364 8389 1926 64.6 MiB 0.08 0.00 5.09416 4.33009 -141.29 -4.33009 4.33009 0.24 0.000312539 0.000284692 0.0257348 0.0234754 -1 -1 -1 -1 32 1899 18 6.64007e+06 288834 554710. 1919.41 0.32 0.066431 0.0591023 22834 132086 -1 1719 19 831 1221 79113 18762 3.36323 3.36323 -128.856 -3.36323 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0147407 0.0132364 128 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.01 vpr 64.66 MiB -1 -1 0.12 18056 1 0.04 -1 -1 29908 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 24.7 MiB 0.07 2458 1067 12164 3189 8279 696 64.7 MiB 0.07 0.00 6.37057 5.24988 -134.918 -5.24988 5.24988 0.23 0.000320631 0.000287726 0.018401 0.0167501 -1 -1 -1 -1 26 2581 23 6.64007e+06 452088 477104. 1650.88 0.42 0.0642136 0.0567882 21682 110474 -1 2228 21 1099 1899 121927 29754 3.83082 3.83082 -126.562 -3.83082 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.02192 0.0194781 133 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 2.30 vpr 64.30 MiB -1 -1 0.14 17892 1 0.03 -1 -1 29868 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 373 294 1 196 102 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2316 1109 11050 2358 7802 890 64.3 MiB 0.06 0.00 5.64915 5.02635 -128.904 -5.02635 5.02635 0.24 0.00034588 0.00031657 0.0180672 0.0165722 -1 -1 -1 -1 30 2070 21 6.64007e+06 489762 526063. 1820.29 0.90 0.13078 0.114565 22546 126617 -1 1846 16 918 1501 68384 17532 4.07422 4.07422 -121.604 -4.07422 0 0 666494. 2306.21 0.03 0.03 0.08 -1 -1 0.03 0.0168693 0.0152914 151 50 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.26 vpr 64.05 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29844 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65584 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 24.6 MiB 0.07 2399 1037 15848 4616 8805 2427 64.0 MiB 0.08 0.00 4.4759 3.71089 -106.291 -3.71089 3.71089 0.24 0.000314293 0.000287759 0.0254439 0.0233391 -1 -1 -1 -1 32 2018 20 6.64007e+06 452088 554710. 1919.41 0.89 0.106875 0.0936934 22834 132086 -1 1894 20 997 1743 113167 25894 2.73777 2.73777 -99.0335 -2.73777 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0155864 0.013987 130 51 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 2.58 vpr 64.82 MiB -1 -1 0.16 18048 1 0.03 -1 -1 29816 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2711 1355 17159 4707 10238 2214 64.8 MiB 0.11 0.00 6.39133 5.42973 -168.16 -5.42973 5.42973 0.24 0.000333297 0.000305473 0.0305336 0.027931 -1 -1 -1 -1 32 2899 17 6.64007e+06 389298 554710. 1919.41 0.97 0.119619 0.104995 22834 132086 -1 2528 21 1636 2593 168950 38601 4.20469 4.20469 -151.273 -4.20469 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.017333 0.015535 155 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 3.02 vpr 64.88 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29784 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2637 1151 20606 6244 9655 4707 64.9 MiB 0.09 0.00 5.13347 4.30924 -132.442 -4.30924 4.30924 0.26 0.000366994 0.000335366 0.0367992 0.0340036 -1 -1 -1 -1 32 2462 42 6.64007e+06 527436 554710. 1919.41 1.55 0.189485 0.167465 22834 132086 -1 1986 17 1183 1864 116056 30310 3.22157 3.22157 -117.993 -3.22157 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0155732 0.014057 151 62 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.21 vpr 64.13 MiB -1 -1 0.12 18056 1 0.02 -1 -1 29828 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1582 689 11948 3112 7844 992 64.1 MiB 0.06 0.00 4.48041 4.01678 -109.438 -4.01678 4.01678 0.24 0.000455205 0.000431544 0.0247681 0.0228668 -1 -1 -1 -1 32 1385 20 6.64007e+06 238602 554710. 1919.41 0.86 0.10574 0.0924354 22834 132086 -1 1290 19 791 1195 77092 18865 2.88077 2.88077 -97.6008 -2.88077 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0128196 0.0114748 93 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.41 vpr 64.59 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29936 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 310 266 1 175 90 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2235 1059 15969 4938 9075 1956 64.6 MiB 0.07 0.00 5.20036 4.23876 -128.495 -4.23876 4.23876 0.24 0.000299718 0.000274504 0.0251125 0.0229545 -1 -1 -1 -1 32 2001 23 6.64007e+06 326508 554710. 1919.41 1.01 0.131817 0.114808 22834 132086 -1 1797 18 929 1290 89628 20456 3.08203 3.08203 -115.313 -3.08203 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0136287 0.0122168 123 58 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.97 vpr 64.70 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29924 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 31 32 326 261 1 177 106 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2343 905 18606 5361 10083 3162 64.7 MiB 0.09 0.00 5.80407 4.54858 -124.201 -4.54858 4.54858 0.24 0.000312841 0.000285299 0.0289889 0.0265187 -1 -1 -1 -1 28 2713 40 6.64007e+06 539994 500653. 1732.36 1.50 0.168338 0.147939 21970 115934 -1 2157 23 1491 2776 199878 49701 3.88503 3.88503 -124.264 -3.88503 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0168966 0.0150698 138 33 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 1.83 vpr 64.50 MiB -1 -1 0.16 17672 1 0.03 -1 -1 29820 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66044 29 32 262 224 1 168 87 17 17 289 -1 unnamed_device 24.5 MiB 0.14 1937 1016 11799 3172 7074 1553 64.5 MiB 0.06 0.00 4.85327 4.04852 -112.319 -4.04852 4.04852 0.23 0.000270092 0.000247629 0.0179409 0.0164448 -1 -1 -1 -1 26 2153 18 6.64007e+06 326508 477104. 1650.88 0.29 0.0517776 0.0458058 21682 110474 -1 1918 18 889 1186 72681 17751 3.29122 3.29122 -107.623 -3.29122 0 0 585099. 2024.56 0.04 0.06 0.09 -1 -1 0.04 0.0283681 0.0254054 116 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.23 vpr 64.48 MiB -1 -1 0.10 18052 1 0.02 -1 -1 29788 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1781 947 10883 2848 6498 1537 64.5 MiB 0.05 0.00 4.52641 4.02095 -125.546 -4.02095 4.02095 0.23 0.00027826 0.000254627 0.0185587 0.0170438 -1 -1 -1 -1 30 1980 22 6.64007e+06 238602 526063. 1820.29 0.93 0.111158 0.096955 22546 126617 -1 1771 19 1115 1979 106566 25643 2.79377 2.79377 -111.145 -2.79377 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0130158 0.0116049 111 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.54 vpr 64.81 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29768 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66368 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2560 1034 12876 3096 8656 1124 64.8 MiB 0.07 0.00 4.91801 4.20195 -124.421 -4.20195 4.20195 0.24 0.000360523 0.000329806 0.0257987 0.023957 -1 -1 -1 -1 32 2018 22 6.64007e+06 502320 554710. 1919.41 1.02 0.149989 0.131986 22834 132086 -1 1831 17 1180 1846 100223 25917 2.96877 2.96877 -113.134 -2.96877 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152364 0.0137279 141 64 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.41 vpr 64.49 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29848 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1957 849 12568 3841 6272 2455 64.5 MiB 0.08 0.00 4.49165 3.90436 -116.108 -3.90436 3.90436 0.25 0.000270822 0.000247709 0.0271462 0.0251465 -1 -1 -1 -1 32 1843 22 6.64007e+06 313950 554710. 1919.41 0.99 0.126567 0.110341 22834 132086 -1 1628 20 997 1467 92295 22084 2.90603 2.90603 -105.107 -2.90603 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0130624 0.0116593 113 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.19 vpr 64.75 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2312 1072 14671 3700 9355 1616 64.8 MiB 0.07 0.00 4.37944 3.68167 -112.793 -3.68167 3.68167 0.23 0.000328231 0.000299444 0.0224555 0.0205477 -1 -1 -1 -1 26 2288 20 6.64007e+06 464646 477104. 1650.88 0.82 0.108143 0.0950909 21682 110474 -1 1944 21 1079 1949 120319 27849 2.90097 2.90097 -107.811 -2.90097 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0169673 0.0152162 131 57 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 1.81 vpr 64.74 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30212 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 24.7 MiB 0.13 2484 1002 10815 2483 7746 586 64.7 MiB 0.06 0.00 4.7433 4.0221 -125.424 -4.0221 4.0221 0.24 0.000397566 0.000334154 0.0194519 0.0177821 -1 -1 -1 -1 30 2069 23 6.64007e+06 452088 526063. 1820.29 0.35 0.0685942 0.0607519 22546 126617 -1 1876 21 1394 2192 129190 30545 3.12957 3.12957 -117.777 -3.12957 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0174038 0.015566 145 91 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 1.76 vpr 64.49 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29744 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1814 857 7770 1801 5584 385 64.5 MiB 0.10 0.00 3.8549 3.3869 -105.248 -3.3869 3.3869 0.26 0.000808908 0.000752472 0.036892 0.0342639 -1 -1 -1 -1 30 1717 23 6.64007e+06 251160 526063. 1820.29 0.36 0.0758761 0.0680954 22546 126617 -1 1505 18 707 1177 69640 16846 2.62037 2.62037 -101.98 -2.62037 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0131102 0.0117754 111 57 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 1.88 vpr 64.57 MiB -1 -1 0.11 18436 1 0.02 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 290 244 1 177 89 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2414 1035 16127 4715 9194 2218 64.6 MiB 0.08 0.00 5.19407 4.38701 -135.203 -4.38701 4.38701 0.30 0.000285817 0.00026167 0.0250029 0.0228938 -1 -1 -1 -1 28 2331 19 6.64007e+06 313950 500653. 1732.36 0.35 0.061641 0.0547906 21970 115934 -1 1998 18 1184 1766 112327 26702 3.18183 3.18183 -121.919 -3.18183 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0156723 0.0140089 123 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.90 vpr 64.68 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29532 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2494 951 15617 4720 8033 2864 64.7 MiB 0.08 0.00 5.8041 4.77338 -128.314 -4.77338 4.77338 0.24 0.000322955 0.000295402 0.0258152 0.0235919 -1 -1 -1 -1 30 2411 22 6.64007e+06 351624 526063. 1820.29 1.43 0.116548 0.102484 22546 126617 -1 1780 20 1025 1564 87363 22048 3.81583 3.81583 -122.51 -3.81583 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0154909 0.0139488 138 30 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.09 vpr 64.66 MiB -1 -1 0.14 18044 1 0.03 -1 -1 29808 -1 -1 36 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2020 1028 6757 1470 4618 669 64.7 MiB 0.04 0.00 4.83347 4.36984 -119.357 -4.36984 4.36984 0.24 0.000308469 0.000282152 0.0111219 0.0102283 -1 -1 -1 -1 26 2136 15 6.64007e+06 452088 477104. 1650.88 0.68 0.0886405 0.0772855 21682 110474 -1 1886 18 837 1482 89240 21546 3.02743 3.02743 -103.989 -3.02743 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0143245 0.0128477 129 55 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.68 vpr 64.55 MiB -1 -1 0.22 18440 1 0.03 -1 -1 30148 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66104 32 32 393 312 1 213 93 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2426 1118 15843 4746 8389 2708 64.6 MiB 0.09 0.00 6.27101 5.72815 -176.849 -5.72815 5.72815 0.24 0.000376256 0.00034593 0.0315166 0.028967 -1 -1 -1 -1 32 2546 19 6.64007e+06 364182 554710. 1919.41 1.03 0.159075 0.140221 22834 132086 -1 2255 20 1391 2068 146331 34168 4.58628 4.58628 -155.397 -4.58628 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0179246 0.0161235 158 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.12 vpr 64.08 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29692 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 24.3 MiB 0.03 1660 747 7221 1683 5260 278 64.1 MiB 0.04 0.00 3.9861 3.49806 -100.112 -3.49806 3.49806 0.24 0.000247913 0.000227211 0.0112366 0.0103119 -1 -1 -1 -1 30 1664 18 6.64007e+06 263718 526063. 1820.29 0.90 0.0946062 0.0821045 22546 126617 -1 1301 16 550 893 50864 12892 2.64857 2.64857 -91.973 -2.64857 0 0 666494. 2306.21 0.03 0.02 0.07 -1 -1 0.03 0.0106208 0.00956507 100 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 1.94 vpr 64.96 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29708 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66516 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2451 1087 18431 5518 10395 2518 65.0 MiB 0.11 0.00 5.50696 4.44233 -144.688 -4.44233 4.44233 0.23 0.00038496 0.000353611 0.0389541 0.0358696 -1 -1 -1 -1 32 2221 20 6.64007e+06 464646 554710. 1919.41 0.39 0.0947235 0.0847517 22834 132086 -1 1905 18 1214 1798 108778 25534 3.75862 3.75862 -135.309 -3.75862 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0201159 0.0182483 146 90 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 1.77 vpr 64.17 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29824 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 376 318 1 155 82 17 17 289 -1 unnamed_device 24.4 MiB 0.12 1766 955 11830 3130 7536 1164 64.2 MiB 0.06 0.00 4.1133 3.5251 -125.052 -3.5251 3.5251 0.24 0.000330759 0.000302081 0.0243994 0.022357 -1 -1 -1 -1 32 1865 20 6.64007e+06 226044 554710. 1919.41 0.36 0.0677556 0.0602023 22834 132086 -1 1684 21 1128 1645 110610 25795 2.66437 2.66437 -115.654 -2.66437 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0168254 0.0150063 116 96 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.72 vpr 64.39 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29776 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2247 944 17427 4836 9376 3215 64.4 MiB 0.13 0.00 4.122 4.04884 -119.999 -4.04884 4.04884 0.23 0.000618313 0.000568585 0.0416241 0.038231 -1 -1 -1 -1 28 2356 26 6.64007e+06 439530 500653. 1732.36 1.26 0.157839 0.139557 21970 115934 -1 1861 17 982 1579 105965 27943 3.13537 3.13537 -108.58 -3.13537 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.015124 0.0136237 134 60 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 2.66 vpr 64.63 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29808 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66180 32 32 396 299 1 236 97 17 17 289 -1 unnamed_device 25.2 MiB 0.18 3069 1434 11863 3029 7657 1177 64.6 MiB 0.10 0.00 7.74409 6.65703 -196.862 -6.65703 6.65703 0.23 0.000392613 0.000361026 0.02616 0.0242474 -1 -1 -1 -1 30 2977 29 6.64007e+06 414414 526063. 1820.29 1.12 0.168442 0.148951 22546 126617 -1 2525 20 1541 2230 119707 29396 5.29994 5.29994 -175.636 -5.29994 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.019447 0.0175604 178 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 1.65 vpr 64.08 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30200 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 30 32 224 207 1 138 85 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1779 825 13663 4108 8029 1526 64.1 MiB 0.05 0.00 3.77619 3.29107 -101.735 -3.29107 3.29107 0.23 0.000232903 0.000213388 0.0185332 0.0169707 -1 -1 -1 -1 26 1653 18 6.64007e+06 288834 477104. 1650.88 0.27 0.0489107 0.0432584 21682 110474 -1 1457 16 625 800 52338 13195 2.38617 2.38617 -94.87 -2.38617 0 0 585099. 2024.56 0.02 0.02 0.06 -1 -1 0.02 0.00980788 0.00878496 93 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.23 vpr 64.48 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30180 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1551 715 8831 2097 6321 413 64.5 MiB 0.04 0.00 4.64461 4.13192 -117.713 -4.13192 4.13192 0.23 0.000283608 0.000257957 0.0163788 0.0150423 -1 -1 -1 -1 32 1455 18 6.64007e+06 238602 554710. 1919.41 0.87 0.0917998 0.0799261 22834 132086 -1 1299 17 693 1155 74739 18315 2.98597 2.98597 -106.773 -2.98597 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0161838 0.0144625 95 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 1.80 vpr 64.14 MiB -1 -1 0.21 17672 1 0.03 -1 -1 29604 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65676 32 32 296 247 1 157 87 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2105 944 14103 4753 7503 1847 64.1 MiB 0.07 0.00 4.1763 3.40707 -111.974 -3.40707 3.40707 0.23 0.000441972 0.000415373 0.023287 0.0213172 -1 -1 -1 -1 32 1961 19 6.64007e+06 288834 554710. 1919.41 0.34 0.0611781 0.0542074 22834 132086 -1 1733 21 1059 1936 116096 28016 2.87177 2.87177 -111.073 -2.87177 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0147393 0.0131377 119 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.33 vpr 64.04 MiB -1 -1 0.10 18056 1 0.02 -1 -1 29888 -1 -1 31 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65572 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 24.9 MiB 0.03 1494 591 13153 4635 5984 2534 64.0 MiB 0.05 0.00 4.0913 3.45027 -80.5708 -3.45027 3.45027 0.25 0.000229 0.00020925 0.0176622 0.0161781 -1 -1 -1 -1 28 1498 20 6.64007e+06 389298 500653. 1732.36 1.02 0.117375 0.102145 21970 115934 -1 1204 20 767 1265 67303 18216 2.69777 2.69777 -76.5165 -2.69777 0 0 612192. 2118.31 0.03 0.03 0.08 -1 -1 0.03 0.0133537 0.0119732 93 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 2.42 vpr 64.81 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29772 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2264 1161 14323 4312 8018 1993 64.8 MiB 0.10 0.00 5.34776 4.34527 -135.212 -4.34527 4.34527 0.25 0.000775451 0.00072278 0.0348073 0.0320495 -1 -1 -1 -1 26 2998 22 6.64007e+06 301392 477104. 1650.88 0.83 0.118776 0.10489 21682 110474 -1 2499 16 1260 2258 137367 32949 3.70982 3.70982 -129.996 -3.70982 0 0 585099. 2024.56 0.04 0.07 0.07 -1 -1 0.04 0.0305887 0.02766 137 72 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 3.06 vpr 64.97 MiB -1 -1 0.14 18056 1 0.04 -1 -1 30020 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66532 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 25.6 MiB 0.11 2647 843 12949 3259 8450 1240 65.0 MiB 0.09 0.00 4.62461 4.03784 -124.693 -4.03784 4.03784 0.24 0.000379639 0.000344151 0.0272347 0.0251462 -1 -1 -1 -1 28 2404 29 6.64007e+06 527436 500653. 1732.36 1.36 0.169941 0.15025 21970 115934 -1 1842 19 1533 2462 139710 38054 3.40377 3.40377 -121.42 -3.40377 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0196062 0.0175902 148 90 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 3.08 vpr 64.26 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29560 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 32 32 354 285 1 202 100 17 17 289 -1 unnamed_device 24.5 MiB 0.11 2680 1148 17500 5750 8438 3312 64.3 MiB 0.09 0.00 6.6478 5.42989 -160.249 -5.42989 5.42989 0.24 0.000335393 0.000306568 0.0277456 0.0253704 -1 -1 -1 -1 30 2512 22 6.65987e+06 456408 526063. 1820.29 1.56 0.126519 0.111713 22546 126617 -1 2013 18 1144 1889 100010 26167 4.13851 4.13851 -142.958 -4.13851 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0214642 0.0194976 152 50 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.48 vpr 64.32 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29772 -1 -1 30 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2387 1221 13961 4223 7808 1930 64.3 MiB 0.10 0.00 5.99396 4.81396 -139.964 -4.81396 4.81396 0.25 0.000338399 0.000310271 0.0346576 0.0320334 -1 -1 -1 -1 28 2736 20 6.65987e+06 380340 500653. 1732.36 1.05 0.148244 0.130948 21970 115934 -1 2265 22 1517 2342 156634 37698 4.01363 4.01363 -138.509 -4.01363 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0176982 0.015846 147 63 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 1.88 vpr 64.51 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30216 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 32 32 299 247 1 188 94 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2525 994 9892 2479 6892 521 64.5 MiB 0.06 0.00 5.48484 4.34823 -112.31 -4.34823 4.34823 0.24 0.000492363 0.000456063 0.0191802 0.0176607 -1 -1 -1 -1 26 2792 43 6.65987e+06 380340 477104. 1650.88 0.57 0.0721775 0.0637459 21682 110474 -1 2032 20 1364 1969 121340 31274 3.49631 3.49631 -112.125 -3.49631 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0150753 0.0135285 129 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.22 vpr 64.45 MiB -1 -1 0.15 18056 1 0.03 -1 -1 30124 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2219 1039 14996 4248 8800 1948 64.4 MiB 0.08 0.00 5.26215 4.26714 -116.661 -4.26714 4.26714 0.24 0.000302092 0.000276833 0.0237687 0.02172 -1 -1 -1 -1 26 2187 23 6.65987e+06 393018 477104. 1650.88 0.82 0.105402 0.0923726 21682 110474 -1 1980 24 1460 2740 181180 44106 3.71485 3.71485 -115.237 -3.71485 0 0 585099. 2024.56 0.02 0.06 0.06 -1 -1 0.02 0.0193045 0.0170988 132 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.42 vpr 64.53 MiB -1 -1 0.11 18292 1 0.03 -1 -1 30208 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2401 1053 15203 4130 9477 1596 64.5 MiB 0.08 0.00 5.31844 4.32872 -126.669 -4.32872 4.32872 0.23 0.000320268 0.000292697 0.025632 0.0234395 -1 -1 -1 -1 32 2377 17 6.65987e+06 354984 554710. 1919.41 1.04 0.128557 0.112316 22834 132086 -1 2184 20 1318 2611 177400 41362 3.28085 3.28085 -117.499 -3.28085 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0162517 0.0145872 134 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.21 vpr 64.70 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29604 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 25.2 MiB 0.04 2589 1122 12876 3256 8561 1059 64.7 MiB 0.07 0.00 4.08553 3.2871 -114.846 -3.2871 3.2871 0.24 0.000367425 0.000337979 0.0203682 0.018632 -1 -1 -1 -1 26 2486 22 6.65987e+06 494442 477104. 1650.88 0.84 0.116554 0.102469 21682 110474 -1 2096 17 1159 1903 117864 29212 3.03931 3.03931 -115.398 -3.03931 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.016059 0.0145175 145 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.22 vpr 64.25 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30136 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1585 699 13324 5476 6895 953 64.2 MiB 0.06 0.00 4.35015 3.70388 -99.5965 -3.70388 3.70388 0.24 0.000265705 0.000243102 0.0220906 0.0202858 -1 -1 -1 -1 32 1384 19 6.65987e+06 266238 554710. 1919.41 0.86 0.104037 0.0904849 22834 132086 -1 1269 20 872 1519 90801 22733 2.68351 2.68351 -90.0723 -2.68351 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0133136 0.0118923 97 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.19 vpr 64.39 MiB -1 -1 0.12 17284 1 0.02 -1 -1 29624 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2037 1041 15848 4643 9032 2173 64.4 MiB 0.08 0.00 3.96304 3.28184 -98.7666 -3.28184 3.28184 0.23 0.000338791 0.000314774 0.0269531 0.0249084 -1 -1 -1 -1 26 2326 21 6.65987e+06 443730 477104. 1650.88 0.83 0.10049 0.0888051 21682 110474 -1 2048 20 1142 2144 140940 33098 2.61165 2.61165 -95.2482 -2.61165 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0141719 0.012715 123 4 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.35 vpr 64.45 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29784 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 31 32 317 271 1 168 88 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2086 993 10423 2723 6384 1316 64.5 MiB 0.07 0.00 3.77724 3.3699 -115.032 -3.3699 3.3699 0.25 0.000671767 0.000645824 0.0231996 0.0214673 -1 -1 -1 -1 32 1809 20 6.65987e+06 316950 554710. 1919.41 0.92 0.127375 0.111058 22834 132086 -1 1615 20 794 1199 70607 17725 2.71311 2.71311 -106.08 -2.71311 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0328717 0.0293078 117 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.60 vpr 64.36 MiB -1 -1 0.19 17660 1 0.03 -1 -1 29748 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1795 844 9983 2313 7049 621 64.4 MiB 0.06 0.00 4.44435 3.77949 -122.028 -3.77949 3.77949 0.23 0.000293552 0.000268791 0.0198136 0.0182461 -1 -1 -1 -1 32 1846 16 6.65987e+06 240882 554710. 1919.41 0.94 0.121669 0.106343 22834 132086 -1 1731 18 979 1642 97359 24956 2.64251 2.64251 -108.37 -2.64251 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0139297 0.0125035 115 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 1.67 vpr 63.78 MiB -1 -1 0.12 18436 1 0.02 -1 -1 29804 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65308 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.9 MiB 0.06 1674 802 13206 4528 6671 2007 63.8 MiB 0.06 0.00 4.47555 3.77152 -109.712 -3.77152 3.77152 0.24 0.000293529 0.000268875 0.0245645 0.0225758 -1 -1 -1 -1 32 1549 21 6.65987e+06 240882 554710. 1919.41 0.31 0.0629295 0.0559363 22834 132086 -1 1379 21 624 931 58999 14595 2.67371 2.67371 -95.9888 -2.67371 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0197524 0.0176291 101 63 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.16 vpr 64.39 MiB -1 -1 0.12 17912 1 0.02 -1 -1 29688 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 24.8 MiB 0.05 2346 870 8343 1986 6056 301 64.4 MiB 0.05 0.00 4.65034 3.60712 -112.822 -3.60712 3.60712 0.23 0.00027589 0.000251814 0.013582 0.0124272 -1 -1 -1 -1 30 2025 25 6.65987e+06 291594 526063. 1820.29 0.87 0.0938097 0.0815367 22546 126617 -1 1544 16 760 1070 57907 15189 2.73385 2.73385 -101.25 -2.73385 0 0 666494. 2306.21 0.02 0.03 0.07 -1 -1 0.02 0.0118484 0.0106631 110 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 3.22 vpr 64.61 MiB -1 -1 0.13 17912 1 0.03 -1 -1 30064 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2572 1235 14583 4936 7551 2096 64.6 MiB 0.09 0.00 4.91561 4.33178 -140.279 -4.33178 4.33178 0.23 0.000334058 0.000305194 0.0254602 0.0232105 -1 -1 -1 -1 28 3236 28 6.65987e+06 367662 500653. 1732.36 1.72 0.149472 0.131385 21970 115934 -1 2425 22 1423 2166 166024 37915 3.20871 3.20871 -128.98 -3.20871 0 0 612192. 2118.31 0.02 0.05 0.11 -1 -1 0.02 0.0176084 0.015759 148 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 3.16 vpr 64.28 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29772 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2535 916 19223 6040 10330 2853 64.3 MiB 0.10 0.00 5.72495 4.44986 -128.732 -4.44986 4.44986 0.31 0.000335278 0.000306305 0.0326129 0.0298459 -1 -1 -1 -1 28 2781 28 6.65987e+06 431052 500653. 1732.36 1.60 0.164036 0.144127 21970 115934 -1 2095 22 1720 2855 211888 56822 3.64231 3.64231 -126.124 -3.64231 0 0 612192. 2118.31 0.02 0.07 0.07 -1 -1 0.02 0.0230006 0.0205473 139 61 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.35 vpr 63.86 MiB -1 -1 0.19 17672 1 0.03 -1 -1 29892 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65388 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 24.3 MiB 0.06 1651 644 11064 3432 5040 2592 63.9 MiB 0.05 0.00 3.69173 2.97053 -85.1657 -2.97053 2.97053 0.23 0.000259807 0.000238065 0.0167708 0.015379 -1 -1 -1 -1 32 1255 21 6.65987e+06 291594 554710. 1919.41 0.93 0.10113 0.0875946 22834 132086 -1 1067 19 701 1169 54274 15412 2.52431 2.52431 -81.3486 -2.52431 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0133753 0.0119419 103 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 1.85 vpr 64.63 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29772 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66184 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2380 968 16819 5706 8070 3043 64.6 MiB 0.11 0.00 4.6711 4.04346 -120.969 -4.04346 4.04346 0.24 0.000352021 0.000322419 0.0406105 0.0374978 -1 -1 -1 -1 32 2265 23 6.65987e+06 342306 554710. 1919.41 0.38 0.0901688 0.0809194 22834 132086 -1 1906 20 1277 2430 141211 36257 3.18037 3.18037 -113.866 -3.18037 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0169663 0.0152628 138 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 2.08 vpr 64.57 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29812 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2606 1180 9821 2681 6536 604 64.6 MiB 0.08 0.00 5.38841 4.32378 -139.417 -4.32378 4.32378 0.25 0.000791528 0.000740611 0.0268259 0.0249583 -1 -1 -1 -1 32 2326 24 6.65987e+06 354984 554710. 1919.41 0.36 0.0762524 0.0683985 22834 132086 -1 2119 19 1135 1613 108552 25602 2.99237 2.99237 -119.109 -2.99237 0 0 701300. 2426.64 0.04 0.06 0.13 -1 -1 0.04 0.0273834 0.0246954 144 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.62 vpr 64.43 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29744 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2090 920 16748 5345 9445 1958 64.4 MiB 0.08 0.00 3.59784 2.86781 -104.206 -2.86781 2.86781 0.24 0.000333852 0.000306347 0.0276424 0.0253042 -1 -1 -1 -1 26 2004 20 6.65987e+06 431052 477104. 1650.88 1.02 0.118539 0.104012 21682 110474 -1 1752 18 988 1648 111876 27246 2.22331 2.22331 -97.4468 -2.22331 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0138236 0.0124016 115 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.42 vpr 63.84 MiB -1 -1 0.19 17668 1 0.03 -1 -1 29836 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65372 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 24.6 MiB 0.04 1535 577 8022 1971 5649 402 63.8 MiB 0.04 0.00 2.83187 2.23087 -73.1637 -2.23087 2.23087 0.26 0.000238925 0.000219996 0.016597 0.0153503 -1 -1 -1 -1 32 1160 20 6.65987e+06 215526 554710. 1919.41 0.89 0.0914579 0.0795766 22834 132086 -1 1031 16 512 757 46741 12549 1.68145 1.68145 -71.9785 -1.68145 0 0 701300. 2426.64 0.03 0.02 0.07 -1 -1 0.03 0.00974086 0.00870837 85 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 1.84 vpr 64.21 MiB -1 -1 0.14 17912 1 0.03 -1 -1 29612 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 31 32 291 243 1 171 87 17 17 289 -1 unnamed_device 24.5 MiB 0.13 2125 1025 13911 4279 7725 1907 64.2 MiB 0.09 0.00 5.78495 4.84052 -144.776 -4.84052 4.84052 0.24 0.000318651 0.000293292 0.0318166 0.0293921 -1 -1 -1 -1 32 1975 23 6.65987e+06 304272 554710. 1919.41 0.37 0.0796161 0.0710669 22834 132086 -1 1717 18 884 1286 76003 18888 3.38591 3.38591 -126.147 -3.38591 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0139715 0.012598 127 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.67 vpr 64.59 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29900 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2331 1127 17961 5306 10774 1881 64.6 MiB 0.09 0.00 5.44296 4.25196 -133.571 -4.25196 4.25196 0.24 0.000328108 0.000300221 0.0278798 0.0255437 -1 -1 -1 -1 32 2239 20 6.65987e+06 469086 554710. 1919.41 1.28 0.164041 0.144183 22834 132086 -1 2044 20 1134 1882 137464 30497 3.52443 3.52443 -125.531 -3.52443 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0164691 0.0147989 140 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 1.94 vpr 64.74 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29936 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2693 1105 8735 1790 6509 436 64.7 MiB 0.07 0.00 5.32033 4.24321 -129.182 -4.24321 4.24321 0.24 0.000355888 0.000326787 0.021586 0.0199751 -1 -1 -1 -1 32 2756 25 6.65987e+06 393018 554710. 1919.41 0.41 0.0732554 0.0652145 22834 132086 -1 2171 17 1204 1933 126107 29946 3.40551 3.40551 -121.526 -3.40551 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0163433 0.014756 151 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 1.60 vpr 63.71 MiB -1 -1 0.10 17672 1 0.02 -1 -1 29788 -1 -1 20 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65236 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1349 468 11200 4643 5749 808 63.7 MiB 0.04 0.00 2.72887 2.30927 -65.1311 -2.30927 2.30927 0.23 0.000202817 0.000184723 0.0152371 0.0139236 -1 -1 -1 -1 28 1180 20 6.65987e+06 253560 500653. 1732.36 0.32 0.0421095 0.0370717 21970 115934 -1 973 22 671 1041 63401 16945 1.84505 1.84505 -64.3919 -1.84505 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0104773 0.00928288 81 30 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.48 vpr 64.38 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29792 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2052 1025 13751 4494 6800 2457 64.4 MiB 0.09 0.00 4.848 4.36895 -121.042 -4.36895 4.36895 0.24 0.000289177 0.000264542 0.0307812 0.0282922 -1 -1 -1 -1 30 2062 23 6.65987e+06 316950 526063. 1820.29 1.05 0.119757 0.105578 22546 126617 -1 1919 21 1129 2131 143866 32712 3.23591 3.23591 -111.109 -3.23591 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0153198 0.013733 125 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.21 vpr 63.69 MiB -1 -1 0.09 17676 1 0.03 -1 -1 29708 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65220 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 24.1 MiB 0.05 1447 545 12331 4341 5596 2394 63.7 MiB 0.04 0.00 2.73393 2.35833 -70.1665 -2.35833 2.35833 0.24 0.000200135 0.000182493 0.0152465 0.0138979 -1 -1 -1 -1 28 1272 22 6.65987e+06 215526 500653. 1732.36 0.84 0.0753932 0.0656314 21970 115934 -1 1023 19 461 533 38297 10550 1.69971 1.69971 -68.1319 -1.69971 0 0 612192. 2118.31 0.02 0.02 0.09 -1 -1 0.02 0.00930423 0.00823659 82 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.70 vpr 64.46 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30148 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2081 896 13487 3921 6875 2691 64.5 MiB 0.07 0.00 5.05175 4.41269 -119.651 -4.41269 4.41269 0.24 0.000297513 0.000271843 0.0207646 0.019033 -1 -1 -1 -1 30 2108 21 6.65987e+06 393018 526063. 1820.29 1.30 0.141092 0.123292 22546 126617 -1 1652 20 867 1525 86666 21900 3.26785 3.26785 -105.916 -3.26785 0 0 666494. 2306.21 0.03 0.04 0.08 -1 -1 0.03 0.0170098 0.0152863 126 24 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.92 vpr 63.70 MiB -1 -1 0.11 17664 1 0.03 -1 -1 29928 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65232 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 24.1 MiB 0.03 2388 1023 19624 6470 10444 2710 63.7 MiB 0.16 0.00 4.58506 3.64141 -104.769 -3.64141 3.64141 0.25 0.000560476 0.000510967 0.0484126 0.0441709 -1 -1 -1 -1 26 2542 46 6.65987e+06 494442 477104. 1650.88 1.29 0.168586 0.149805 21682 110474 -1 2045 18 1075 2003 124306 31296 3.00917 3.00917 -106.461 -3.00917 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0140512 0.0126467 136 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.79 vpr 64.55 MiB -1 -1 0.21 18044 1 0.04 -1 -1 30164 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 338 277 1 179 98 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2305 1091 18323 5790 9817 2716 64.6 MiB 0.09 0.00 5.46249 4.55003 -127.972 -4.55003 4.55003 0.24 0.000318033 0.000290194 0.0282284 0.0257753 -1 -1 -1 -1 30 2249 26 6.65987e+06 431052 526063. 1820.29 1.08 0.140788 0.122545 22546 126617 -1 1876 22 1106 1999 115126 27433 3.41605 3.41605 -116.12 -3.41605 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0170675 0.0152663 132 50 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.16 vpr 64.35 MiB -1 -1 0.11 18056 1 0.04 -1 -1 29776 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1848 913 13291 3770 7974 1547 64.3 MiB 0.06 0.00 3.57584 2.90053 -103.342 -2.90053 2.90053 0.24 0.000281589 0.000257719 0.0224208 0.0205218 -1 -1 -1 -1 28 1955 21 6.65987e+06 266238 500653. 1732.36 0.80 0.109728 0.0958161 21970 115934 -1 1804 21 1025 1722 112193 27509 2.68265 2.68265 -105.703 -2.68265 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0146769 0.0131164 107 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.40 vpr 64.27 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29776 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65808 30 32 262 227 1 135 86 17 17 289 -1 unnamed_device 24.3 MiB 0.04 1630 651 8969 1996 5970 1003 64.3 MiB 0.06 0.00 3.39847 3.05504 -90.9474 -3.05504 3.05504 0.25 0.000642942 0.000600414 0.0237623 0.0220744 -1 -1 -1 -1 28 1977 31 6.65987e+06 304272 500653. 1732.36 1.09 0.126607 0.110752 21970 115934 -1 1470 22 937 1443 90491 25132 2.67851 2.67851 -92.6094 -2.67851 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.01419 0.0126255 100 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.45 vpr 64.29 MiB -1 -1 0.12 18056 1 0.02 -1 -1 29432 -1 -1 24 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 24.9 MiB 0.03 1903 614 8319 1869 5547 903 64.3 MiB 0.04 0.00 4.15324 3.37407 -91.8212 -3.37407 3.37407 0.24 0.000265987 0.000243464 0.0137025 0.012562 -1 -1 -1 -1 28 1780 25 6.65987e+06 304272 500653. 1732.36 1.08 0.111413 0.0967491 21970 115934 -1 1400 26 1051 1933 126779 34231 2.79571 2.79571 -93.3762 -2.79571 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0181639 0.0161746 104 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 2.08 vpr 64.27 MiB -1 -1 0.10 17672 1 0.03 -1 -1 29812 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2077 937 13663 4386 7373 1904 64.3 MiB 0.07 0.00 4.42935 3.71432 -111.148 -3.71432 3.71432 0.24 0.000318555 0.000292319 0.0221483 0.0202869 -1 -1 -1 -1 30 1919 20 6.65987e+06 266238 526063. 1820.29 0.76 0.0917732 0.0801906 22546 126617 -1 1728 21 1075 1786 109331 25720 2.65051 2.65051 -104.501 -2.65051 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0142262 0.0127329 116 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 1.97 vpr 64.33 MiB -1 -1 0.12 17668 1 0.03 -1 -1 29800 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1915 835 10827 2687 7563 577 64.3 MiB 0.09 0.00 3.84464 3.33721 -100.19 -3.33721 3.33721 0.35 0.000522039 0.00047658 0.0275881 0.0251882 -1 -1 -1 -1 26 1992 24 6.65987e+06 418374 477104. 1650.88 0.54 0.0791696 0.0702585 21682 110474 -1 1818 16 954 1675 105836 27778 2.82585 2.82585 -102.328 -2.82585 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0117904 0.0105846 111 30 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 1.74 vpr 64.40 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30200 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2169 872 17273 5743 9135 2395 64.4 MiB 0.07 0.00 3.81664 3.21564 -100.08 -3.21564 3.21564 0.24 0.000287972 0.000263067 0.0258344 0.0235912 -1 -1 -1 -1 32 1641 19 6.65987e+06 393018 554710. 1919.41 0.35 0.0669967 0.0594516 22834 132086 -1 1488 14 765 1169 65775 17191 2.31791 2.31791 -88.1097 -2.31791 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0124866 0.0111334 112 54 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 2.12 vpr 64.70 MiB -1 -1 0.16 18436 1 0.03 -1 -1 29616 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2308 1244 18356 5163 9963 3230 64.7 MiB 0.10 0.00 4.39192 3.92829 -113.996 -3.92829 3.92829 0.25 0.000749949 0.000718237 0.0389664 0.0359702 -1 -1 -1 -1 32 2640 24 6.65987e+06 532476 554710. 1919.41 0.44 0.095081 0.0852499 22834 132086 -1 2262 21 1317 2612 179532 41270 3.25579 3.25579 -109.354 -3.25579 0 0 701300. 2426.64 0.03 0.08 0.13 -1 -1 0.03 0.0355269 0.0316882 158 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 1.87 vpr 64.75 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29764 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2421 1098 16654 4458 10225 1971 64.7 MiB 0.10 0.00 4.43155 3.83032 -129.396 -3.83032 3.83032 0.24 0.000365598 0.000334178 0.0332215 0.0304978 -1 -1 -1 -1 28 2395 21 6.65987e+06 519798 500653. 1732.36 0.37 0.0820495 0.0733414 21970 115934 -1 2087 22 1631 2798 163826 40220 2.88617 2.88617 -117.628 -2.88617 0 0 612192. 2118.31 0.03 0.05 0.06 -1 -1 0.03 0.0206196 0.0184833 150 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 1.74 vpr 64.39 MiB -1 -1 0.13 17912 1 0.03 -1 -1 29804 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 24.3 MiB 0.05 2417 954 13883 3379 9484 1020 64.4 MiB 0.07 0.00 4.94055 4.24332 -124.031 -4.24332 4.24332 0.24 0.000288508 0.000262756 0.0228909 0.0208676 -1 -1 -1 -1 32 1963 21 6.65987e+06 291594 554710. 1919.41 0.33 0.0612728 0.0542438 22834 132086 -1 1756 20 823 1155 77844 19870 2.98031 2.98031 -108.773 -2.98031 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0143922 0.0129215 114 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.26 vpr 64.67 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30520 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66224 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2217 1128 16238 4900 9111 2227 64.7 MiB 0.09 0.00 4.7803 3.9389 -118.342 -3.9389 3.9389 0.24 0.000337036 0.000307837 0.0287174 0.0262948 -1 -1 -1 -1 30 2357 17 6.65987e+06 367662 526063. 1820.29 0.85 0.125417 0.110734 22546 126617 -1 2060 20 1126 2079 105239 26274 2.83077 2.83077 -109.668 -2.83077 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0172833 0.0155108 145 61 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.99 vpr 64.78 MiB -1 -1 0.17 18440 1 0.03 -1 -1 29768 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 377 302 1 233 99 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2995 1450 19023 5551 11450 2022 64.8 MiB 0.12 0.00 7.69393 5.6677 -167.985 -5.6677 5.6677 0.32 0.000381638 0.000350701 0.0372226 0.0341246 -1 -1 -1 -1 28 3350 21 6.65987e+06 456408 500653. 1732.36 1.33 0.159215 0.140889 21970 115934 -1 2772 21 1856 2735 170569 41048 4.77703 4.77703 -165.781 -4.77703 0 0 612192. 2118.31 0.03 0.06 0.07 -1 -1 0.03 0.0228982 0.0206184 178 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.97 vpr 64.36 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30132 -1 -1 32 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 24.9 MiB 0.59 2681 1309 14999 4622 8322 2055 64.4 MiB 0.09 0.00 6.28756 5.10273 -157.72 -5.10273 5.10273 0.23 0.00068262 0.00062368 0.0291839 0.0267265 -1 -1 -1 -1 32 2682 21 6.65987e+06 405696 554710. 1919.41 1.01 0.131813 0.116038 22834 132086 -1 2351 17 1068 1598 128922 28801 3.94943 3.94943 -145.575 -3.94943 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0160375 0.0145622 167 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 1.94 vpr 64.62 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29740 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2150 1138 13788 3708 8180 1900 64.6 MiB 0.08 0.00 5.13095 4.43175 -130.78 -4.43175 4.43175 0.23 0.000330854 0.000303241 0.0226578 0.0208034 -1 -1 -1 -1 26 2684 23 6.65987e+06 469086 477104. 1650.88 0.48 0.0706622 0.0628663 21682 110474 -1 2241 22 1376 2290 147550 36455 3.10551 3.10551 -115.897 -3.10551 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0181755 0.0161496 140 55 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 1.78 vpr 64.46 MiB -1 -1 0.13 18052 1 0.03 -1 -1 29580 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66008 32 32 291 242 1 179 91 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2447 1059 9883 2265 7085 533 64.5 MiB 0.06 0.00 5.12624 4.09841 -110.895 -4.09841 4.09841 0.25 0.000296132 0.000272346 0.0176985 0.0162418 -1 -1 -1 -1 26 2556 27 6.65987e+06 342306 477104. 1650.88 0.46 0.0606008 0.0535975 21682 110474 -1 2017 21 1095 1676 106066 26073 3.51731 3.51731 -113.349 -3.51731 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0152707 0.0135971 124 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 2.51 vpr 64.29 MiB -1 -1 0.12 18436 1 0.03 -1 -1 29856 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 25.2 MiB 0.07 3074 1204 12757 3068 8413 1276 64.3 MiB 0.08 0.00 6.1774 4.89901 -154.002 -4.89901 4.89901 0.23 0.000414085 0.000380006 0.0237217 0.0217485 -1 -1 -1 -1 28 3067 37 6.65987e+06 545154 500653. 1732.36 1.06 0.158471 0.138717 21970 115934 -1 2549 21 1787 2650 155948 39478 4.09557 4.09557 -145.446 -4.09557 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.023765 0.0213011 176 87 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.10 vpr 64.28 MiB -1 -1 0.12 17668 1 0.02 -1 -1 29856 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 24.9 MiB 0.04 2009 887 11048 2987 7063 998 64.3 MiB 0.06 0.00 4.26232 3.39378 -98.4132 -3.39378 3.39378 0.24 0.000267305 0.000244906 0.020054 0.018467 -1 -1 -1 -1 26 1891 30 6.65987e+06 291594 477104. 1650.88 0.77 0.105782 0.092071 21682 110474 -1 1662 20 1011 1739 107514 26503 2.82891 2.82891 -101.876 -2.82891 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0133012 0.0118709 104 28 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 2.54 vpr 64.61 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30240 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2890 1251 18301 5355 10266 2680 64.6 MiB 0.10 0.00 6.05769 4.76375 -144.29 -4.76375 4.76375 0.25 0.000325031 0.000298013 0.0320046 0.0294245 -1 -1 -1 -1 26 3189 24 6.65987e+06 431052 477104. 1650.88 1.13 0.140561 0.123821 21682 110474 -1 2546 22 1555 2328 159437 38754 4.09251 4.09251 -137.605 -4.09251 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0175959 0.015789 149 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.00 vpr 64.21 MiB -1 -1 0.12 18048 1 0.03 -1 -1 29732 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 32 32 349 284 1 182 102 17 17 289 -1 unnamed_device 24.2 MiB 0.05 2675 1157 12240 3182 8323 735 64.2 MiB 0.08 0.00 4.8754 3.93484 -114.185 -3.93484 3.93484 0.24 0.000330143 0.000300671 0.0222818 0.0204813 -1 -1 -1 -1 26 2757 32 6.65987e+06 481764 477104. 1650.88 0.60 0.0776811 0.0690096 21682 110474 -1 2363 19 1261 2360 164757 38552 3.36871 3.36871 -117.29 -3.36871 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.019165 0.0171186 136 53 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 1.88 vpr 64.40 MiB -1 -1 0.16 17528 1 0.03 -1 -1 30164 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 24.5 MiB 0.04 1813 1098 12127 4092 6786 1249 64.4 MiB 0.09 0.00 4.58224 3.99224 -122.075 -3.99224 3.99224 0.25 0.000381717 0.000350442 0.0280412 0.0258922 -1 -1 -1 -1 32 2237 19 6.65987e+06 342306 554710. 1919.41 0.40 0.0682722 0.0610453 22834 132086 -1 2105 20 1119 2098 156985 35010 3.48525 3.48525 -121.639 -3.48525 0 0 701300. 2426.64 0.03 0.07 0.07 -1 -1 0.03 0.0257139 0.0230642 127 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.25 vpr 64.68 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30152 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66232 32 32 353 287 1 198 95 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2414 1201 14783 3737 9111 1935 64.7 MiB 0.09 0.00 5.28395 4.64383 -136.782 -4.64383 4.64383 0.23 0.000330395 0.000300954 0.0254379 0.0232664 -1 -1 -1 -1 28 2543 26 6.65987e+06 393018 500653. 1732.36 0.80 0.120905 0.105969 21970 115934 -1 2251 21 1408 1875 123007 30781 3.10031 3.10031 -118.173 -3.10031 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0168622 0.0151259 142 55 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 4.51 vpr 64.64 MiB -1 -1 0.13 18436 1 0.03 -1 -1 29688 -1 -1 39 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2461 953 17937 5130 8807 4000 64.6 MiB 0.08 0.00 4.2905 3.7987 -116.61 -3.7987 3.7987 0.24 0.000333522 0.000304868 0.0275557 0.0252356 -1 -1 -1 -1 34 2395 37 6.65987e+06 494442 585099. 2024.56 3.08 0.18849 0.165399 23122 138558 -1 1886 17 1036 1828 125524 37518 2.91397 2.91397 -111.895 -2.91397 0 0 742403. 2568.87 0.03 0.05 0.08 -1 -1 0.03 0.0175925 0.0160764 139 55 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.11 vpr 64.62 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30212 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 24.8 MiB 0.07 2721 1179 19868 6240 11195 2433 64.6 MiB 0.21 0.00 4.80995 4.10592 -126.681 -4.10592 4.10592 0.23 0.000537632 0.000496731 0.0705905 0.0653766 -1 -1 -1 -1 26 2816 24 6.65987e+06 507120 477104. 1650.88 0.60 0.128236 0.11589 21682 110474 -1 2357 21 1447 2439 171323 40624 2.93371 2.93371 -116.894 -2.93371 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0178623 0.0160256 149 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 3.71 vpr 64.45 MiB -1 -1 0.11 17904 1 0.03 -1 -1 29800 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 25.0 MiB 0.05 1946 873 16108 4349 7937 3822 64.5 MiB 0.07 0.00 4.57124 3.93324 -112.121 -3.93324 3.93324 0.23 0.000306658 0.000280335 0.0248876 0.0228463 -1 -1 -1 -1 30 2274 29 6.65987e+06 456408 526063. 1820.29 2.35 0.120616 0.105943 22546 126617 -1 1515 22 1093 1983 103839 27229 3.38699 3.38699 -106.02 -3.38699 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0177718 0.0157363 127 24 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.23 vpr 63.87 MiB -1 -1 0.14 18052 1 0.03 -1 -1 29584 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 32 32 319 257 1 198 92 17 17 289 -1 unnamed_device 24.5 MiB 0.09 2350 1139 12719 3270 8148 1301 63.9 MiB 0.07 0.00 5.74889 4.74243 -133.951 -4.74243 4.74243 0.24 0.000312147 0.000284437 0.0214525 0.0196459 -1 -1 -1 -1 30 2287 21 6.65987e+06 354984 526063. 1820.29 0.68 0.102014 0.0894369 22546 126617 -1 1970 18 1171 1696 92785 22648 3.49131 3.49131 -121.376 -3.49131 0 0 666494. 2306.21 0.04 0.05 0.12 -1 -1 0.04 0.0187291 0.0169296 137 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 2.62 vpr 64.74 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29800 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2919 1229 8073 1790 5652 631 64.7 MiB 0.06 0.00 6.09275 4.90792 -144.963 -4.90792 4.90792 0.24 0.000354844 0.000325213 0.0163957 0.0150592 -1 -1 -1 -1 26 3109 38 6.65987e+06 380340 477104. 1650.88 1.20 0.150978 0.132741 21682 110474 -1 2584 23 1839 2855 189670 45582 4.00631 4.00631 -139.798 -4.00631 0 0 585099. 2024.56 0.02 0.05 0.07 -1 -1 0.02 0.019152 0.0170771 151 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.92 vpr 64.23 MiB -1 -1 0.17 18056 1 0.03 -1 -1 30108 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2687 1072 16523 5659 7829 3035 64.2 MiB 0.11 0.00 4.94107 4.09069 -129.92 -4.09069 4.09069 0.24 0.000857988 0.000801055 0.0416845 0.0386047 -1 -1 -1 -1 30 2468 19 6.65987e+06 316950 526063. 1820.29 1.40 0.171759 0.152727 22546 126617 -1 1929 19 1275 2194 126979 30184 3.36805 3.36805 -121.211 -3.36805 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0232353 0.0208535 141 77 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.15 vpr 64.25 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29820 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 251 219 1 140 91 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1818 851 9271 2119 6628 524 64.2 MiB 0.04 0.00 3.59669 3.36815 -99.3617 -3.36815 3.36815 0.24 0.000266366 0.000244407 0.0136646 0.0125264 -1 -1 -1 -1 28 1906 24 6.65987e+06 342306 500653. 1732.36 0.84 0.108303 0.0937673 21970 115934 -1 1646 22 837 1395 90639 21909 2.60345 2.60345 -92.8412 -2.60345 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0136441 0.012154 101 23 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 1.94 vpr 64.57 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29848 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66120 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2440 992 6007 1156 4597 254 64.6 MiB 0.04 0.00 4.88419 3.97947 -135.407 -3.97947 3.97947 0.29 0.000328686 0.000301478 0.0111881 0.0102596 -1 -1 -1 -1 28 2655 20 6.65987e+06 342306 500653. 1732.36 0.40 0.0545205 0.04797 21970 115934 -1 2093 23 1541 2202 159522 39777 3.38797 3.38797 -131.381 -3.38797 0 0 612192. 2118.31 0.03 0.05 0.06 -1 -1 0.03 0.0182671 0.0163156 133 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 1.88 vpr 64.34 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29828 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 32 32 387 293 1 234 98 17 17 289 -1 unnamed_device 25.1 MiB 0.06 2841 1434 16523 4655 9834 2034 64.3 MiB 0.11 0.00 6.09189 5.18108 -152.063 -5.18108 5.18108 0.24 0.000363101 0.000332817 0.0361583 0.0334442 -1 -1 -1 -1 32 3145 19 6.65987e+06 431052 554710. 1919.41 0.38 0.0838214 0.0752932 22834 132086 -1 2602 22 1587 2577 157408 37857 4.25491 4.25491 -142.991 -4.25491 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0194226 0.0174853 174 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 3.65 vpr 64.57 MiB -1 -1 0.13 18020 1 0.03 -1 -1 29944 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2565 908 17952 4964 9148 3840 64.6 MiB 0.09 0.00 5.03706 4.14283 -126.342 -4.14283 4.14283 0.23 0.000329597 0.000301333 0.0285814 0.0262011 -1 -1 -1 -1 30 2351 28 6.65987e+06 481764 526063. 1820.29 2.07 0.16465 0.145021 22546 126617 -1 1739 20 1039 1780 111645 29043 2.61551 2.61551 -104.065 -2.61551 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0164232 0.0147637 141 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.35 vpr 64.36 MiB -1 -1 0.12 17668 1 0.03 -1 -1 30328 -1 -1 33 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 24.9 MiB 0.03 2182 907 13703 3856 8397 1450 64.4 MiB 0.07 0.00 4.13824 3.55007 -108.481 -3.55007 3.55007 0.25 0.000293269 0.000263617 0.024289 0.0224368 -1 -1 -1 -1 32 1765 21 6.65987e+06 418374 554710. 1919.41 0.98 0.118204 0.103343 22834 132086 -1 1534 19 670 1228 76480 18288 2.48817 2.48817 -96.8001 -2.48817 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.013599 0.0121795 111 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 2.80 vpr 64.20 MiB -1 -1 0.15 18824 1 0.03 -1 -1 30124 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65744 32 32 431 332 1 235 95 17 17 289 -1 unnamed_device 24.9 MiB 0.16 2995 1435 16943 5441 8966 2536 64.2 MiB 0.11 0.00 7.19172 6.12709 -179.158 -6.12709 6.12709 0.24 0.000402579 0.000368127 0.0338431 0.0310673 -1 -1 -1 -1 32 2968 21 6.65987e+06 393018 554710. 1919.41 1.11 0.166916 0.146566 22834 132086 -1 2576 21 1778 2583 161656 39107 4.64457 4.64457 -161.765 -4.64457 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0204855 0.0183688 177 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 1.88 vpr 64.54 MiB -1 -1 0.17 17672 1 0.03 -1 -1 29952 -1 -1 38 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1956 1087 13668 3395 8471 1802 64.5 MiB 0.07 0.00 5.02695 4.36075 -134.246 -4.36075 4.36075 0.23 0.000320393 0.000293161 0.0207929 0.0190365 -1 -1 -1 -1 32 2118 20 6.65987e+06 481764 554710. 1919.41 0.38 0.0685113 0.0607201 22834 132086 -1 1937 19 1075 1822 123899 28240 3.11425 3.11425 -116.807 -3.11425 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0159821 0.0143821 136 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.20 vpr 64.20 MiB -1 -1 0.11 17668 1 0.02 -1 -1 29924 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 231 199 1 140 91 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1906 763 10291 2431 6883 977 64.2 MiB 0.05 0.00 4.00198 3.24072 -93.0898 -3.24072 3.24072 0.24 0.000252957 0.00023204 0.014133 0.0129556 -1 -1 -1 -1 26 1813 19 6.65987e+06 342306 477104. 1650.88 0.90 0.100565 0.0873611 21682 110474 -1 1587 17 924 1601 94219 24609 2.67551 2.67551 -95.133 -2.67551 0 0 585099. 2024.56 0.02 0.03 0.07 -1 -1 0.02 0.0144873 0.0129215 103 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.94 vpr 64.62 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30252 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2540 1184 12792 3130 8784 878 64.6 MiB 0.08 0.00 6.17103 5.12357 -128.342 -5.12357 5.12357 0.24 0.000405648 0.00035247 0.0251103 0.0232583 -1 -1 -1 -1 26 2736 22 6.65987e+06 507120 477104. 1650.88 1.38 0.129295 0.114292 21682 110474 -1 2329 19 1224 2599 181219 41024 3.77199 3.77199 -121.701 -3.77199 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0175625 0.0157507 147 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.20 vpr 64.25 MiB -1 -1 0.23 17912 1 0.02 -1 -1 29776 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 24.1 MiB 0.04 2164 862 9111 2261 6252 598 64.2 MiB 0.05 0.00 4.2295 3.4211 -103.943 -3.4211 3.4211 0.25 0.000272144 0.000249418 0.0165738 0.015236 -1 -1 -1 -1 26 1976 21 6.65987e+06 291594 477104. 1650.88 0.72 0.0817198 0.0712883 21682 110474 -1 1647 22 1171 2052 118500 29809 2.99817 2.99817 -107.951 -2.99817 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0148357 0.0132715 107 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.37 vpr 64.37 MiB -1 -1 0.15 17912 1 0.04 -1 -1 29824 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2117 919 17732 5394 9708 2630 64.4 MiB 0.09 0.00 5.05435 4.00072 -108.105 -4.00072 4.00072 0.25 0.000319002 0.000294923 0.0275487 0.0252902 -1 -1 -1 -1 28 1932 24 6.65987e+06 481764 500653. 1732.36 0.86 0.115273 0.101221 21970 115934 -1 1752 19 902 1787 109885 27332 2.74851 2.74851 -98.5026 -2.74851 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0132408 0.0118756 110 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 2.40 vpr 64.51 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29996 -1 -1 30 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 29 32 355 287 1 198 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2795 1157 13759 4262 7817 1680 64.5 MiB 0.08 0.00 5.46461 4.50718 -131.152 -4.50718 4.50718 0.31 0.000330091 0.000302586 0.0257511 0.0236546 -1 -1 -1 -1 26 2957 22 6.65987e+06 380340 477104. 1650.88 0.51 0.0783395 0.0700172 21682 110474 -1 2345 21 1460 2184 143176 34536 3.37397 3.37397 -119.24 -3.37397 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0287388 0.0256969 146 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 2.14 vpr 64.57 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29768 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 0.05 1949 952 8251 1965 5842 444 64.6 MiB 0.05 0.00 5.1233 4.33587 -133.747 -4.33587 4.33587 0.25 0.00033683 0.00030808 0.0176046 0.0162384 -1 -1 -1 -1 32 1981 22 6.65987e+06 342306 554710. 1919.41 0.57 0.102101 0.0906133 22834 132086 -1 1751 21 1307 2030 131428 31363 3.43337 3.43337 -125.859 -3.43337 0 0 701300. 2426.64 0.04 0.05 0.14 -1 -1 0.04 0.0190603 0.0171537 135 54 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 1.82 vpr 64.58 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29644 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66128 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2440 995 11573 3131 7196 1246 64.6 MiB 0.07 0.00 5.53355 4.52906 -132.157 -4.52906 4.52906 0.25 0.000337555 0.000309443 0.0200569 0.0183746 -1 -1 -1 -1 32 2149 21 6.65987e+06 431052 554710. 1919.41 0.34 0.0639729 0.0567577 22834 132086 -1 1930 21 1161 1924 112326 28305 3.56431 3.56431 -123.17 -3.56431 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0192602 0.017328 136 51 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.28 vpr 64.37 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29596 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1928 842 5756 1110 4290 356 64.4 MiB 0.04 0.00 5.01063 4.547 -125.133 -4.547 4.547 0.24 0.000281039 0.000257092 0.0108104 0.00993427 -1 -1 -1 -1 26 2746 42 6.65987e+06 278916 477104. 1650.88 0.81 0.0695017 0.0610828 21682 110474 -1 2009 23 1128 1545 124492 32025 3.20671 3.20671 -119.094 -3.20671 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0149363 0.0132929 107 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.31 vpr 64.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29780 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 31 32 319 272 1 169 86 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2087 999 8402 2135 5628 639 64.4 MiB 0.05 0.00 4.70844 3.76401 -122.041 -3.76401 3.76401 0.24 0.000297899 0.000272927 0.0150693 0.0138092 -1 -1 -1 -1 30 2009 19 6.65987e+06 291594 526063. 1820.29 0.77 0.139907 0.122491 22546 126617 -1 1802 22 1049 1597 92062 22220 3.08351 3.08351 -115.52 -3.08351 0 0 666494. 2306.21 0.05 0.05 0.11 -1 -1 0.05 0.023418 0.0209173 116 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.79 vpr 64.51 MiB -1 -1 0.14 18440 1 0.03 -1 -1 30120 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2322 911 10223 2206 7289 728 64.5 MiB 0.06 0.00 4.14418 3.34001 -95.1163 -3.34001 3.34001 0.24 0.000313524 0.000285877 0.0164285 0.0150486 -1 -1 -1 -1 26 2414 22 6.65987e+06 456408 477104. 1650.88 1.37 0.107607 0.0946655 21682 110474 -1 1927 22 1181 2235 140233 36386 2.57639 2.57639 -96.5212 -2.57639 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0200354 0.0178693 128 57 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.64 vpr 64.39 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30184 -1 -1 39 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1932 968 16515 5028 9029 2458 64.4 MiB 0.10 0.00 4.80358 3.82106 -98.9222 -3.82106 3.82106 0.27 0.000295246 0.000271701 0.0370857 0.0343414 -1 -1 -1 -1 30 1920 22 6.65987e+06 494442 526063. 1820.29 1.00 0.146017 0.128722 22546 126617 -1 1687 18 746 1556 78646 19064 3.06345 3.06345 -92.4917 -3.06345 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0156517 0.0140541 122 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 1.82 vpr 64.39 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29780 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 30 32 317 269 1 152 83 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1992 840 8543 2231 5712 600 64.4 MiB 0.07 0.00 4.52275 3.81872 -113.653 -3.81872 3.81872 0.28 0.000471169 0.0004455 0.0265634 0.0247268 -1 -1 -1 -1 32 1758 21 6.65987e+06 266238 554710. 1919.41 0.37 0.0718623 0.0643443 22834 132086 -1 1633 20 966 1723 107995 26820 2.70651 2.70651 -105.636 -2.70651 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152378 0.0135695 115 63 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 2.08 vpr 64.07 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29868 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65604 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 24.5 MiB 0.07 2267 1081 11748 2737 7741 1270 64.1 MiB 0.12 0.00 4.27587 3.75301 -127.23 -3.75301 3.75301 0.24 0.000922484 0.000857673 0.046778 0.043576 -1 -1 -1 -1 32 2169 20 6.65987e+06 329628 554710. 1919.41 0.53 0.113914 0.10228 22834 132086 -1 1912 17 1021 1536 95655 22988 3.18891 3.18891 -117.522 -3.18891 0 0 701300. 2426.64 0.04 0.06 0.11 -1 -1 0.04 0.0257491 0.022733 127 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.59 vpr 64.44 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29548 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 25.0 MiB 0.04 2060 1066 14716 3823 8466 2427 64.4 MiB 0.07 0.00 4.86349 4.26143 -121.889 -4.26143 4.26143 0.27 0.000296603 0.000269714 0.0210521 0.0191673 -1 -1 -1 -1 32 2163 21 6.65987e+06 469086 554710. 1919.41 1.11 0.142451 0.124381 22834 132086 -1 1952 18 1051 1980 108284 26406 3.51125 3.51125 -111.09 -3.51125 0 0 701300. 2426.64 0.03 0.04 0.10 -1 -1 0.03 0.0165159 0.0149261 134 4 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 1.98 vpr 64.64 MiB -1 -1 0.12 18048 1 0.03 -1 -1 30360 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 350 275 1 209 93 17 17 289 -1 unnamed_device 25.2 MiB 0.07 2681 1168 10383 2802 6577 1004 64.6 MiB 0.07 0.00 5.68615 4.86192 -151.547 -4.86192 4.86192 0.24 0.000334875 0.000306795 0.0187135 0.0171881 -1 -1 -1 -1 32 2556 25 6.65987e+06 367662 554710. 1919.41 0.49 0.0877671 0.0777807 22834 132086 -1 2143 20 1336 2094 119998 29832 3.72991 3.72991 -134.478 -3.72991 0 0 701300. 2426.64 0.04 0.06 0.08 -1 -1 0.04 0.0242861 0.021965 151 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 4.53 vpr 64.66 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29792 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2633 927 18196 5275 8727 4194 64.7 MiB 0.08 0.00 5.51755 4.47917 -136.038 -4.47917 4.47917 0.23 0.00035799 0.000327422 0.0311637 0.0285323 -1 -1 -1 -1 36 2460 39 6.65987e+06 469086 612192. 2118.31 3.09 0.183338 0.161522 23410 145293 -1 1908 19 1434 2459 149777 39483 3.72051 3.72051 -129.983 -3.72051 0 0 782063. 2706.10 0.03 0.04 0.09 -1 -1 0.03 0.0173432 0.0156109 143 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.52 vpr 64.05 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30240 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2914 1226 13516 3426 8918 1172 64.1 MiB 0.11 0.00 5.66375 4.30832 -138.449 -4.30832 4.30832 0.31 0.000364026 0.000327868 0.0352371 0.0324508 -1 -1 -1 -1 26 3133 37 6.65987e+06 545154 477104. 1650.88 2.01 0.204454 0.180913 21682 110474 -1 2585 21 1659 3001 194586 46671 3.27771 3.27771 -128.625 -3.27771 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0184663 0.0164533 147 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 1.84 vpr 64.31 MiB -1 -1 0.22 17672 1 0.03 -1 -1 30260 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65856 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1945 699 9443 2134 6868 441 64.3 MiB 0.06 0.00 4.63389 3.7606 -108.702 -3.7606 3.7606 0.25 0.000274486 0.000250373 0.0202243 0.0186816 -1 -1 -1 -1 32 1712 22 6.65987e+06 266238 554710. 1919.41 0.36 0.0608618 0.0541478 22834 132086 -1 1351 17 754 1264 75034 19152 2.55625 2.55625 -94.2402 -2.55625 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0127318 0.0114779 109 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 1.87 vpr 64.62 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30156 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 24.9 MiB 0.07 2028 1003 9395 2078 6561 756 64.6 MiB 0.06 0.00 5.34001 4.72954 -137.554 -4.72954 4.72954 0.23 0.000351356 0.000321724 0.0184561 0.0169463 -1 -1 -1 -1 28 2499 27 6.65987e+06 342306 500653. 1732.36 0.47 0.0711341 0.0630113 21970 115934 -1 2043 19 1375 2121 129278 33516 3.72637 3.72637 -132.273 -3.72637 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0175255 0.0158171 147 63 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 3.56 vpr 64.59 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29852 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 24.9 MiB 0.09 2562 1172 8614 1885 5948 781 64.6 MiB 0.06 0.00 6.11242 5.075 -148.312 -5.075 5.075 0.24 0.000324053 0.000296578 0.0159447 0.0146839 -1 -1 -1 -1 28 3045 34 6.65987e+06 380340 500653. 1732.36 2.06 0.139928 0.123519 21970 115934 -1 2409 21 1636 2519 180150 43978 3.77211 3.77211 -133.398 -3.77211 0 0 612192. 2118.31 0.03 0.07 0.07 -1 -1 0.03 0.0233923 0.0209471 145 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 2.64 vpr 64.71 MiB -1 -1 0.16 17524 1 0.04 -1 -1 29784 -1 -1 35 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 340 275 1 195 98 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2655 1234 13373 3486 8666 1221 64.7 MiB 0.08 0.00 6.2565 5.20087 -146.632 -5.20087 5.20087 0.24 0.000337977 0.000309774 0.0232074 0.0213238 -1 -1 -1 -1 28 2603 23 6.65987e+06 443730 500653. 1732.36 0.95 0.148618 0.130153 21970 115934 -1 2276 21 1462 2381 143787 35641 4.28397 4.28397 -142.339 -4.28397 0 0 612192. 2118.31 0.04 0.07 0.11 -1 -1 0.04 0.0301272 0.0271323 152 47 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.11 vpr 64.64 MiB -1 -1 0.12 18052 1 0.03 -1 -1 30124 -1 -1 38 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 24.9 MiB 0.37 2368 1078 19356 5734 11269 2353 64.6 MiB 0.11 0.00 5.15601 4.43481 -132.977 -4.43481 4.43481 0.24 0.000356646 0.000327786 0.0400155 0.0371255 -1 -1 -1 -1 32 2034 21 6.65987e+06 481764 554710. 1919.41 0.34 0.0872187 0.0784088 22834 132086 -1 1867 19 1042 1815 109969 26079 3.09757 3.09757 -117.861 -3.09757 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0270637 0.0241799 144 83 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 1.79 vpr 64.22 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29780 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65760 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2717 1028 9989 2368 7036 585 64.2 MiB 0.08 0.00 5.82395 4.80846 -135.83 -4.80846 4.80846 0.25 0.000785676 0.000756889 0.0268928 0.0250003 -1 -1 -1 -1 32 2279 22 6.65987e+06 316950 554710. 1919.41 0.40 0.0816934 0.072869 22834 132086 -1 1969 18 1045 1838 103539 25809 3.51511 3.51511 -124.567 -3.51511 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0162994 0.0147361 141 57 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 1.73 vpr 64.64 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29804 -1 -1 38 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 29 32 378 310 1 177 99 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2479 1013 19251 5705 10712 2834 64.6 MiB 0.10 0.00 4.83889 4.07094 -114.526 -4.07094 4.07094 0.24 0.000337925 0.000308777 0.0326149 0.0298842 -1 -1 -1 -1 30 1955 24 6.65987e+06 481764 526063. 1820.29 0.34 0.0803182 0.0715981 22546 126617 -1 1736 16 966 1673 79843 20483 2.65731 2.65731 -99.9201 -2.65731 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0153559 0.0139599 137 85 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 2.25 vpr 64.21 MiB -1 -1 0.10 17668 1 0.02 -1 -1 29944 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65756 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 24.1 MiB 0.05 1776 913 13583 3827 8166 1590 64.2 MiB 0.06 0.00 4.36335 3.77952 -113.791 -3.77952 3.77952 0.23 0.000258733 0.000237246 0.0221535 0.0203246 -1 -1 -1 -1 32 1628 18 6.65987e+06 240882 554710. 1919.41 0.86 0.108382 0.0947406 22834 132086 -1 1492 15 568 862 53023 12847 2.73465 2.73465 -99.7426 -2.73465 0 0 701300. 2426.64 0.03 0.02 0.12 -1 -1 0.03 0.0110657 0.0100029 99 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.64 vpr 64.61 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29768 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 25.2 MiB 0.08 2442 1018 18339 5915 9603 2821 64.6 MiB 0.09 0.00 5.53955 4.46392 -134.604 -4.46392 4.46392 0.24 0.000350581 0.000320376 0.030238 0.0276861 -1 -1 -1 -1 28 2559 33 6.65987e+06 443730 500653. 1732.36 1.23 0.157921 0.139255 21970 115934 -1 2034 22 1390 2379 155320 38127 3.72251 3.72251 -131.726 -3.72251 0 0 612192. 2118.31 0.03 0.06 0.06 -1 -1 0.03 0.0224972 0.0200975 135 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 1.88 vpr 64.36 MiB -1 -1 0.13 18044 1 0.03 -1 -1 29776 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65900 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 24.9 MiB 0.08 2649 1042 7415 1478 5399 538 64.4 MiB 0.05 0.00 5.84281 4.69477 -144.735 -4.69477 4.69477 0.25 0.000363804 0.000333298 0.0164987 0.0151272 -1 -1 -1 -1 32 2467 22 6.65987e+06 316950 554710. 1919.41 0.43 0.0723381 0.0642314 22834 132086 -1 2120 20 1640 2746 168107 41989 3.74157 3.74157 -135.95 -3.74157 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0231033 0.0206951 155 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.15 vpr 64.37 MiB -1 -1 0.14 17660 1 0.03 -1 -1 29800 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2060 1041 9791 2284 6736 771 64.4 MiB 0.05 0.00 4.9641 4.13987 -114.14 -4.13987 4.13987 0.23 0.000285581 0.000261993 0.0167929 0.0154416 -1 -1 -1 -1 22 2510 30 6.65987e+06 316950 420624. 1455.45 0.84 0.0995754 0.0866549 20818 92861 -1 2270 19 1086 1462 115592 27496 3.61557 3.61557 -116.563 -3.61557 0 0 500653. 1732.36 0.02 0.04 0.05 -1 -1 0.02 0.0135916 0.0121488 117 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 1.77 vpr 64.24 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29940 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2068 883 14639 5191 7304 2144 64.2 MiB 0.07 0.00 4.81301 3.84841 -109.743 -3.84841 3.84841 0.25 0.000261358 0.000239166 0.0228225 0.0209759 -1 -1 -1 -1 32 1873 20 6.65987e+06 291594 554710. 1919.41 0.33 0.0586236 0.0521393 22834 132086 -1 1716 18 1042 1695 113744 27403 2.66951 2.66951 -100.595 -2.66951 0 0 701300. 2426.64 0.03 0.04 0.09 -1 -1 0.03 0.0131841 0.0117093 110 4 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 2.88 vpr 64.64 MiB -1 -1 0.11 18052 1 0.03 -1 -1 30384 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 32 32 348 274 1 211 94 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2693 1126 12235 3289 8013 933 64.6 MiB 0.08 0.00 6.19807 4.92983 -147.924 -4.92983 4.92983 0.24 0.000328778 0.000300919 0.0228505 0.0209311 -1 -1 -1 -1 26 2899 25 6.65987e+06 380340 477104. 1650.88 1.47 0.125491 0.110588 21682 110474 -1 2453 19 1611 2205 158180 38601 3.91843 3.91843 -143.277 -3.91843 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.016446 0.01476 151 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 2.73 vpr 64.70 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29820 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 24.9 MiB 0.10 2455 1202 17726 5863 9448 2415 64.7 MiB 0.10 0.00 6.19085 4.98326 -147.838 -4.98326 4.98326 0.23 0.000337012 0.00030237 0.0286512 0.0261769 -1 -1 -1 -1 28 2992 31 6.65987e+06 469086 500653. 1732.36 1.28 0.150303 0.13201 21970 115934 -1 2209 22 1417 2227 163353 43256 4.07751 4.07751 -138.323 -4.07751 0 0 612192. 2118.31 0.02 0.05 0.06 -1 -1 0.02 0.0211012 0.0188692 157 56 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.12 vpr 64.40 MiB -1 -1 0.21 18056 1 0.04 -1 -1 29828 -1 -1 43 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 24.7 MiB 0.04 2789 1282 17058 4558 10111 2389 64.4 MiB 0.10 0.00 6.22775 5.25635 -138.9 -5.25635 5.25635 0.24 0.000847755 0.000792737 0.0270822 0.0248474 -1 -1 -1 -1 30 2744 22 6.65987e+06 545154 526063. 1820.29 0.51 0.0787829 0.0704927 22546 126617 -1 2279 19 1165 2296 144567 32446 4.20857 4.20857 -132.092 -4.20857 0 0 666494. 2306.21 0.04 0.09 0.08 -1 -1 0.04 0.0377591 0.0340845 162 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.48 vpr 64.46 MiB -1 -1 0.12 17908 1 0.03 -1 -1 29804 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 30 32 316 264 1 162 98 17 17 289 -1 unnamed_device 24.5 MiB 0.08 2263 907 15623 4094 8873 2656 64.5 MiB 0.07 0.00 4.35844 3.46421 -101.49 -3.46421 3.46421 0.23 0.000302285 0.000277318 0.0237892 0.0218542 -1 -1 -1 -1 30 1887 20 6.65987e+06 456408 526063. 1820.29 0.93 0.125269 0.109434 22546 126617 -1 1617 20 923 1599 76990 19613 2.69151 2.69151 -96.3226 -2.69151 0 0 666494. 2306.21 0.04 0.07 0.08 -1 -1 0.04 0.035453 0.0317282 124 52 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.19 vpr 64.24 MiB -1 -1 0.14 17672 1 0.02 -1 -1 30144 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 27 32 255 219 1 132 82 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1707 762 11296 3316 6423 1557 64.2 MiB 0.05 0.00 4.35664 3.48247 -97.7908 -3.48247 3.48247 0.23 0.000254069 0.00023285 0.0176088 0.0161447 -1 -1 -1 -1 32 1498 19 6.65987e+06 291594 554710. 1919.41 0.88 0.0982668 0.0852425 22834 132086 -1 1390 21 750 1239 79737 19491 2.74977 2.74977 -93.2365 -2.74977 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0131444 0.0117322 100 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 3.10 vpr 64.94 MiB -1 -1 0.16 17672 1 0.03 -1 -1 30148 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 25.6 MiB 0.06 3118 1504 18998 5785 11135 2078 64.9 MiB 0.16 0.00 5.30144 4.15341 -134.659 -4.15341 4.15341 0.24 0.000723216 0.00066104 0.048028 0.0441656 -1 -1 -1 -1 32 3347 20 6.65987e+06 431052 554710. 1919.41 1.49 0.187082 0.165648 22834 132086 -1 2852 23 1753 2861 212134 47689 3.41911 3.41911 -128.837 -3.41911 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0239451 0.0214081 176 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 2.76 vpr 64.15 MiB -1 -1 0.14 18044 1 0.03 -1 -1 30148 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 24.9 MiB 0.36 2626 1131 10743 2617 7196 930 64.2 MiB 0.07 0.00 6.52641 5.34958 -160.242 -5.34958 5.34958 0.23 0.000344068 0.000315901 0.0230363 0.0213167 -1 -1 -1 -1 32 2256 22 6.65987e+06 342306 554710. 1919.41 1.04 0.141545 0.124772 22834 132086 -1 2058 19 1267 1995 127981 30724 4.12737 4.12737 -144.115 -4.12737 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0163519 0.0147443 151 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 2.49 vpr 64.12 MiB -1 -1 0.12 18052 1 0.02 -1 -1 29692 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65660 32 32 331 280 1 175 87 17 17 289 -1 unnamed_device 24.5 MiB 0.34 2093 1056 11223 2777 6565 1881 64.1 MiB 0.07 0.00 5.5891 4.44586 -136.991 -4.44586 4.44586 0.23 0.000310743 0.00028465 0.0245441 0.0226654 -1 -1 -1 -1 30 2098 21 6.65987e+06 291594 526063. 1820.29 0.83 0.115069 0.101493 22546 126617 -1 1713 17 744 1061 64700 15352 3.42717 3.42717 -125.557 -3.42717 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0188638 0.0169499 129 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 1.99 vpr 64.05 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30332 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2458 1023 12396 3002 8710 684 64.1 MiB 0.06 0.00 5.92474 4.91628 -125.981 -4.91628 4.91628 0.31 0.00031312 0.000285308 0.0186718 0.0170098 -1 -1 -1 -1 26 2519 25 6.65987e+06 456408 477104. 1650.88 0.49 0.0681747 0.0605424 21682 110474 -1 2143 19 1162 2005 137788 34909 3.45605 3.45605 -115.538 -3.45605 0 0 585099. 2024.56 0.04 0.04 0.08 -1 -1 0.04 0.0156747 0.0141323 133 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 2.49 vpr 64.38 MiB -1 -1 0.18 18052 1 0.03 -1 -1 29868 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 31 32 373 294 1 196 102 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2316 1116 9622 2124 6827 671 64.4 MiB 0.07 0.00 5.28538 4.66257 -122.009 -4.66257 4.66257 0.24 0.000500582 0.000470974 0.022367 0.0207019 -1 -1 -1 -1 32 2164 22 6.65987e+06 494442 554710. 1919.41 0.96 0.150679 0.132762 22834 132086 -1 1941 21 1024 1664 98113 24600 3.71045 3.71045 -118.186 -3.71045 0 0 701300. 2426.64 0.03 0.04 0.08 -1 -1 0.03 0.0217 0.0195245 151 50 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.43 vpr 64.50 MiB -1 -1 0.19 18056 1 0.03 -1 -1 30260 -1 -1 36 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2399 1001 15848 4524 8647 2677 64.5 MiB 0.10 0.00 4.35464 3.6178 -102.686 -3.6178 3.6178 0.25 0.000340058 0.000313523 0.032293 0.0300242 -1 -1 -1 -1 32 2093 22 6.65987e+06 456408 554710. 1919.41 0.91 0.115634 0.10181 22834 132086 -1 1735 20 927 1616 95276 23308 2.75671 2.75671 -93.3009 -2.75671 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0152838 0.0137139 130 51 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 2.63 vpr 64.65 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30252 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 32 32 350 275 1 215 95 17 17 289 -1 unnamed_device 25.3 MiB 0.13 2711 1336 11327 3094 7340 893 64.7 MiB 0.08 0.00 6.10595 5.14435 -160.142 -5.14435 5.14435 0.23 0.00035727 0.000327964 0.0199369 0.0183003 -1 -1 -1 -1 32 2855 24 6.65987e+06 393018 554710. 1919.41 1.00 0.118695 0.104006 22834 132086 -1 2484 19 1479 2310 144508 33634 3.96111 3.96111 -144.603 -3.96111 0 0 701300. 2426.64 0.03 0.05 0.07 -1 -1 0.03 0.0177237 0.0159978 155 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 3.00 vpr 64.70 MiB -1 -1 0.13 18052 1 0.03 -1 -1 30148 -1 -1 42 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 25.2 MiB 0.11 2637 1017 18856 5646 10377 2833 64.7 MiB 0.10 0.00 5.01221 4.18798 -126.815 -4.18798 4.18798 0.23 0.000362844 0.000331712 0.0291056 0.0266064 -1 -1 -1 -1 30 2352 24 6.65987e+06 532476 526063. 1820.29 1.29 0.129417 0.113746 22546 126617 -1 1931 21 1304 2159 137888 33646 2.87277 2.87277 -109.84 -2.87277 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0238673 0.0214352 151 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.36 vpr 64.15 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29820 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65688 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 24.5 MiB 0.03 1576 639 12464 3221 8431 812 64.1 MiB 0.09 0.00 4.48041 4.01678 -108.148 -4.01678 4.01678 0.28 0.000480442 0.000438543 0.0373201 0.0341971 -1 -1 -1 -1 30 1486 20 6.65987e+06 240882 526063. 1820.29 0.93 0.126396 0.111447 22546 126617 -1 1234 20 690 1018 70885 16894 2.71377 2.71377 -93.534 -2.71377 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0135202 0.0121234 93 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.28 vpr 63.98 MiB -1 -1 0.13 17908 1 0.03 -1 -1 29936 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65520 32 32 310 266 1 175 90 17 17 289 -1 unnamed_device 24.1 MiB 0.04 2095 940 8331 1938 5650 743 64.0 MiB 0.05 0.00 4.98039 4.1175 -122.325 -4.1175 4.1175 0.25 0.000294899 0.000270139 0.0142154 0.0130403 -1 -1 -1 -1 26 2117 18 6.65987e+06 329628 477104. 1650.88 0.95 0.114865 0.100577 21682 110474 -1 1793 22 1060 1496 105030 24470 3.22317 3.22317 -116.181 -3.22317 0 0 585099. 2024.56 0.02 0.04 0.06 -1 -1 0.02 0.0159831 0.014244 123 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.83 vpr 64.54 MiB -1 -1 0.14 18440 1 0.03 -1 -1 29876 -1 -1 43 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66088 31 32 326 261 1 177 106 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2343 916 18356 4978 9795 3583 64.5 MiB 0.09 0.00 5.52155 4.37352 -119.432 -4.37352 4.37352 0.25 0.000354148 0.000290662 0.0273844 0.0250176 -1 -1 -1 -1 30 2290 33 6.65987e+06 545154 526063. 1820.29 1.40 0.157058 0.137275 22546 126617 -1 1831 24 1339 2530 162695 40201 3.55325 3.55325 -112.175 -3.55325 0 0 666494. 2306.21 0.03 0.05 0.07 -1 -1 0.03 0.0183438 0.0163401 138 33 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 1.69 vpr 64.36 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29796 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 29 32 262 224 1 168 87 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1937 962 8151 2045 5043 1063 64.4 MiB 0.05 0.00 4.73201 3.89047 -108.453 -3.89047 3.89047 0.24 0.000334714 0.000292814 0.0167961 0.0155764 -1 -1 -1 -1 26 2222 19 6.65987e+06 329628 477104. 1650.88 0.37 0.0576277 0.0510664 21682 110474 -1 1935 15 790 1052 70400 17366 3.46957 3.46957 -109.369 -3.46957 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0117647 0.0106224 116 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.30 vpr 64.32 MiB -1 -1 0.12 17668 1 0.02 -1 -1 30196 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 24.5 MiB 0.06 1781 952 11063 2996 6474 1593 64.3 MiB 0.06 0.00 4.35429 3.84883 -121.23 -3.84883 3.84883 0.23 0.000287209 0.000263087 0.0212423 0.0195714 -1 -1 -1 -1 32 2005 20 6.65987e+06 240882 554710. 1919.41 0.95 0.109571 0.0957045 22834 132086 -1 1812 17 1077 1863 113788 27875 2.76365 2.76365 -109.874 -2.76365 0 0 701300. 2426.64 0.03 0.03 0.07 -1 -1 0.03 0.0124444 0.0111877 111 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.11 vpr 64.69 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30172 -1 -1 40 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66244 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 25.2 MiB 0.10 2567 987 19865 6213 10843 2809 64.7 MiB 0.10 0.00 4.83595 3.99455 -119.479 -3.99455 3.99455 0.24 0.000342915 0.000313639 0.0314504 0.0287291 -1 -1 -1 -1 30 2020 22 6.65987e+06 507120 526063. 1820.29 0.38 0.0796706 0.0710934 22546 126617 -1 1680 17 1092 1822 104124 25102 2.69057 2.69057 -105.166 -2.69057 0 0 666494. 2306.21 0.04 0.06 0.13 -1 -1 0.04 0.0275626 0.0248684 141 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 1.86 vpr 64.24 MiB -1 -1 0.22 17912 1 0.02 -1 -1 30232 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 24.2 MiB 0.05 1957 962 7888 1862 5402 624 64.2 MiB 0.04 0.00 4.37039 3.7831 -115.738 -3.7831 3.7831 0.24 0.000271273 0.000248449 0.0127145 0.0116877 -1 -1 -1 -1 32 1927 16 6.65987e+06 316950 554710. 1919.41 0.31 0.0483232 0.0426507 22834 132086 -1 1730 18 773 1167 76810 18412 2.99882 2.99882 -104.533 -2.99882 0 0 701300. 2426.64 0.03 0.03 0.12 -1 -1 0.03 0.0145656 0.0130899 113 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.22 vpr 64.57 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29800 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2312 1008 10206 2347 7231 628 64.6 MiB 0.06 0.00 4.25818 3.54324 -107.169 -3.54324 3.54324 0.23 0.000332085 0.000303616 0.0162243 0.0148741 -1 -1 -1 -1 26 2349 20 6.65987e+06 469086 477104. 1650.88 0.85 0.0996743 0.0869767 21682 110474 -1 2018 17 1073 1917 117571 28694 3.00811 3.00811 -108.65 -3.00811 0 0 585099. 2024.56 0.03 0.04 0.06 -1 -1 0.03 0.0161924 0.0146389 131 57 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.55 vpr 64.71 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30128 -1 -1 36 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 25.2 MiB 0.31 2511 865 8763 1886 5820 1057 64.7 MiB 0.04 0.00 4.68116 3.95996 -121.43 -3.95996 3.95996 0.23 0.000354374 0.00032327 0.0160355 0.0147464 -1 -1 -1 -1 30 2002 20 6.65987e+06 456408 526063. 1820.29 0.94 0.117387 0.102667 22546 126617 -1 1550 23 1220 1942 99122 25765 3.04517 3.04517 -111.679 -3.04517 0 0 666494. 2306.21 0.03 0.05 0.08 -1 -1 0.03 0.0217423 0.0193783 145 91 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.16 vpr 64.38 MiB -1 -1 0.13 17528 1 0.03 -1 -1 30128 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 24.5 MiB 0.05 1814 855 8685 1965 6279 441 64.4 MiB 0.05 0.00 3.73364 3.26564 -102.346 -3.26564 3.26564 0.24 0.000288455 0.000264091 0.0153522 0.0140632 -1 -1 -1 -1 30 1748 23 6.65987e+06 253560 526063. 1820.29 0.85 0.110401 0.0963068 22546 126617 -1 1498 21 732 1205 70856 17065 2.63031 2.63031 -100.894 -2.63031 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.017499 0.0156765 111 57 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.55 vpr 64.08 MiB -1 -1 0.11 18052 1 0.03 -1 -1 29772 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 290 244 1 177 89 17 17 289 -1 unnamed_device 24.5 MiB 0.05 2414 1034 14345 4099 8382 1864 64.1 MiB 0.08 0.00 4.99075 4.16652 -128.649 -4.16652 4.16652 0.23 0.000836935 0.000781281 0.0238684 0.0218989 -1 -1 -1 -1 26 2468 26 6.65987e+06 316950 477104. 1650.88 1.23 0.120498 0.105531 21682 110474 -1 2134 24 1416 2156 157699 36703 3.04751 3.04751 -115.392 -3.04751 0 0 585099. 2024.56 0.02 0.05 0.06 -1 -1 0.02 0.0174596 0.0154964 123 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.52 vpr 64.16 MiB -1 -1 0.12 18056 1 0.04 -1 -1 29776 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65700 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2494 994 15617 4673 8037 2907 64.2 MiB 0.09 0.00 5.51987 4.47824 -122.048 -4.47824 4.47824 0.25 0.000735291 0.000686061 0.0334077 0.0308887 -1 -1 -1 -1 32 2294 23 6.65987e+06 354984 554710. 1919.41 1.08 0.143869 0.126522 22834 132086 -1 1774 21 1187 1626 103869 25571 3.45205 3.45205 -115.407 -3.45205 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0163066 0.0146294 138 30 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.17 vpr 64.41 MiB -1 -1 0.15 17900 1 0.03 -1 -1 29816 -1 -1 36 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 24.5 MiB 0.06 2020 1018 6757 1480 4594 683 64.4 MiB 0.04 0.00 4.63015 4.16652 -114.233 -4.16652 4.16652 0.24 0.000324166 0.00029741 0.0121531 0.0112268 -1 -1 -1 -1 26 2263 17 6.65987e+06 456408 477104. 1650.88 0.81 0.10672 0.0933432 21682 110474 -1 1930 17 916 1609 100571 24369 2.92431 2.92431 -101.278 -2.92431 0 0 585099. 2024.56 0.02 0.04 0.07 -1 -1 0.02 0.0152708 0.0135685 129 55 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 1.83 vpr 64.79 MiB -1 -1 0.17 18044 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 32 32 393 312 1 213 93 17 17 289 -1 unnamed_device 25.2 MiB 0.06 2445 1182 15843 4177 9740 1926 64.8 MiB 0.10 0.00 6.02849 5.60583 -175.338 -5.60583 5.60583 0.24 0.000364198 0.000333706 0.0327777 0.0301651 -1 -1 -1 -1 32 2463 22 6.65987e+06 367662 554710. 1919.41 0.36 0.0842253 0.075097 22834 132086 -1 2221 17 1304 1896 104576 26642 4.22277 4.22277 -152.701 -4.22277 0 0 701300. 2426.64 0.03 0.04 0.07 -1 -1 0.03 0.0167933 0.015254 158 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.23 vpr 63.93 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29940 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65468 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 24.1 MiB 0.04 1660 797 8502 1949 6085 468 63.9 MiB 0.04 0.00 3.86484 3.31781 -96.9676 -3.31781 3.31781 0.24 0.000251262 0.000230584 0.0130921 0.0120166 -1 -1 -1 -1 32 1566 18 6.65987e+06 266238 554710. 1919.41 0.87 0.0866868 0.0751474 22834 132086 -1 1391 19 657 1075 65111 16588 2.50751 2.50751 -91.4965 -2.50751 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0126917 0.0113845 100 4 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 1.89 vpr 64.77 MiB -1 -1 0.18 18052 1 0.03 -1 -1 29736 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 24.9 MiB 0.05 2451 1117 18431 5270 10930 2231 64.8 MiB 0.10 0.00 5.26444 4.25378 -140.231 -4.25378 4.25378 0.23 0.000373417 0.000339939 0.0316981 0.0289474 -1 -1 -1 -1 32 2341 20 6.65987e+06 469086 554710. 1919.41 0.35 0.080619 0.0716735 22834 132086 -1 2008 21 1252 1842 124809 28919 3.67551 3.67551 -132.399 -3.67551 0 0 701300. 2426.64 0.05 0.10 0.07 -1 -1 0.05 0.0452931 0.0406668 146 90 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.82 vpr 64.54 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29804 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66092 32 32 376 318 1 156 82 17 17 289 -1 unnamed_device 24.5 MiB 0.09 1828 704 11118 4283 5586 1249 64.5 MiB 0.06 0.00 4.2335 3.6453 -123.384 -3.6453 3.6453 0.24 0.000342878 0.000313621 0.023058 0.0211148 -1 -1 -1 -1 28 2422 44 6.65987e+06 228204 500653. 1732.36 1.43 0.142219 0.124509 21970 115934 -1 1780 19 1300 1811 145425 37952 3.84337 3.84337 -134.566 -3.84337 0 0 612192. 2118.31 0.02 0.04 0.06 -1 -1 0.02 0.0162809 0.0146439 117 96 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 3.28 vpr 64.64 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29800 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2247 913 17427 4947 8338 4142 64.6 MiB 0.08 0.00 3.91868 3.84552 -113.949 -3.84552 3.84552 0.24 0.000355925 0.00032683 0.0299331 0.027482 -1 -1 -1 -1 30 2270 33 6.65987e+06 443730 526063. 1820.29 1.87 0.141496 0.124872 22546 126617 -1 1646 21 1045 1639 90768 24593 2.74351 2.74351 -97.3413 -2.74351 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0173314 0.0155781 134 60 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.41 vpr 64.84 MiB -1 -1 0.13 18436 1 0.03 -1 -1 30408 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 396 299 1 236 97 17 17 289 -1 unnamed_device 25.2 MiB 0.09 3069 1481 14971 3777 9344 1850 64.8 MiB 0.10 0.00 7.38831 6.08328 -185.229 -6.08328 6.08328 0.24 0.000411097 0.000378951 0.029417 0.0270377 -1 -1 -1 -1 28 3362 36 6.65987e+06 418374 500653. 1732.36 1.91 0.197809 0.176182 21970 115934 -1 2828 20 1964 2892 207521 47864 4.90737 4.90737 -169.574 -4.90737 0 0 612192. 2118.31 0.02 0.06 0.06 -1 -1 0.02 0.0197778 0.0179217 178 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.17 vpr 64.17 MiB -1 -1 0.14 17660 1 0.02 -1 -1 29808 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65708 30 32 224 207 1 138 85 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1779 770 11245 2856 7531 858 64.2 MiB 0.05 0.00 3.68981 3.20901 -98.3536 -3.20901 3.20901 0.25 0.000246513 0.000216211 0.0159507 0.0145994 -1 -1 -1 -1 28 1564 19 6.65987e+06 291594 500653. 1732.36 0.87 0.100704 0.088167 21970 115934 -1 1350 17 651 829 50023 12838 2.20351 2.20351 -87.8269 -2.20351 0 0 612192. 2118.31 0.02 0.03 0.06 -1 -1 0.02 0.0142654 0.0125989 93 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.33 vpr 64.30 MiB -1 -1 0.11 17668 1 0.02 -1 -1 30056 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 24.9 MiB 0.07 1551 682 8831 2129 6271 431 64.3 MiB 0.04 0.00 4.40209 3.8416 -111.334 -3.8416 3.8416 0.23 0.000277254 0.000253555 0.0158328 0.0145297 -1 -1 -1 -1 30 1565 17 6.65987e+06 240882 526063. 1820.29 1.00 0.125437 0.109434 22546 126617 -1 1321 19 741 1248 76607 18509 2.86471 2.86471 -106.925 -2.86471 0 0 666494. 2306.21 0.03 0.03 0.07 -1 -1 0.03 0.0139883 0.0125804 95 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 1.67 vpr 64.40 MiB -1 -1 0.11 17672 1 0.04 -1 -1 29780 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 296 247 1 157 87 17 17 289 -1 unnamed_device 24.5 MiB 0.04 2143 845 9303 1922 7070 311 64.4 MiB 0.05 0.00 4.04404 3.39881 -108.793 -3.39881 3.39881 0.23 0.000291844 0.000265742 0.0156435 0.0143167 -1 -1 -1 -1 30 2055 22 6.65987e+06 291594 526063. 1820.29 0.36 0.0577119 0.0509962 22546 126617 -1 1649 20 1059 1884 106086 26424 2.57731 2.57731 -102.381 -2.57731 0 0 666494. 2306.21 0.03 0.04 0.07 -1 -1 0.03 0.0142499 0.0127288 119 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 1.66 vpr 63.88 MiB -1 -1 0.11 17668 1 0.03 -1 -1 29940 -1 -1 31 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 24.1 MiB 0.03 1494 614 13153 4634 5792 2727 63.9 MiB 0.05 0.00 3.79264 3.36581 -78.5128 -3.36581 3.36581 0.24 0.000221928 0.000202489 0.0164571 0.0150544 -1 -1 -1 -1 32 1365 25 6.65987e+06 393018 554710. 1919.41 0.32 0.0489517 0.0432483 22834 132086 -1 1113 18 614 985 48919 13492 2.53525 2.53525 -71.42 -2.53525 0 0 701300. 2426.64 0.03 0.03 0.08 -1 -1 0.03 0.0126873 0.0114295 93 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 1.91 vpr 64.62 MiB -1 -1 0.14 18056 1 0.04 -1 -1 29764 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 32 32 376 307 1 185 88 17 17 289 -1 unnamed_device 24.7 MiB 0.06 2264 1147 14323 4224 8035 2064 64.6 MiB 0.10 0.00 5.10524 4.17275 -131.194 -4.17275 4.17275 0.25 0.000342368 0.000312581 0.0307727 0.0283674 -1 -1 -1 -1 32 2473 25 6.65987e+06 304272 554710. 1919.41 0.42 0.0914247 0.0815378 22834 132086 -1 2202 25 1395 2545 160708 39277 3.38805 3.38805 -119.812 -3.38805 0 0 701300. 2426.64 0.03 0.06 0.07 -1 -1 0.03 0.0241588 0.0215803 137 72 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 1.77 vpr 64.71 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29792 -1 -1 42 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 24.9 MiB 0.06 2647 860 12702 3275 8213 1214 64.7 MiB 0.08 0.00 4.50335 3.91658 -121.607 -3.91658 3.91658 0.23 0.000366347 0.000329594 0.0216129 0.0197719 -1 -1 -1 -1 32 2045 24 6.65987e+06 532476 554710. 1919.41 0.38 0.0799359 0.0709708 22834 132086 -1 1761 21 1382 2184 119657 31714 2.82571 2.82571 -107.817 -2.82571 0 0 701300. 2426.64 0.03 0.05 0.08 -1 -1 0.03 0.0226136 0.02042 148 90 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_001.v common 4.08 vpr 65.26 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30128 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66828 32 32 354 285 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 0.85 2453 972 10228 4188 5749 291 65.3 MiB 0.06 0.00 6.53897 5.5107 -161.059 -5.5107 5.5107 0.25 0.000360483 0.000330651 0.0301468 0.0280027 -1 -1 -1 -1 48 2385 23 6.95648e+06 231611 865456. 2994.66 1.81 0.152519 0.134344 28354 207349 -1 1961 26 1704 2847 242432 77762 4.53791 4.53791 -149.014 -4.53791 0 0 1.05005e+06 3633.38 0.04 0.08 0.11 -1 -1 0.04 0.0207781 0.0185925 81 50 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 6.05 vpr 64.70 MiB -1 -1 0.13 18444 1 0.03 -1 -1 30380 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 30 32 363 293 1 187 80 17 17 289 -1 unnamed_device 25.5 MiB 1.26 2699 985 12980 3943 7957 1080 64.7 MiB 0.06 0.00 5.32638 4.21658 -134.56 -4.21658 4.21658 0.24 0.000338369 0.000310011 0.0273553 0.0251228 -1 -1 -1 -1 36 2667 32 6.95648e+06 260562 648988. 2245.63 3.39 0.180648 0.159451 26050 158493 -1 2213 23 2112 3019 267785 55858 4.35602 4.35602 -151.278 -4.35602 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0188925 0.0169542 79 63 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_003.v common 3.46 vpr 64.77 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29740 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 25.2 MiB 0.60 2358 1032 12186 3430 7248 1508 64.8 MiB 0.06 0.00 4.71675 3.78245 -119.015 -3.78245 3.78245 0.24 0.000295122 0.000269011 0.022121 0.0202745 -1 -1 -1 -1 40 2414 23 6.95648e+06 260562 706193. 2443.58 1.50 0.121574 0.106131 26914 176310 -1 2051 18 1192 1596 127749 28397 3.76412 3.76412 -125.019 -3.76412 0 0 926341. 3205.33 0.03 0.04 0.09 -1 -1 0.03 0.0170379 0.0152769 74 29 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_004.v common 3.41 vpr 64.20 MiB -1 -1 0.12 18048 1 0.04 -1 -1 29756 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 29 32 308 248 1 162 84 17 17 289 -1 unnamed_device 25.2 MiB 0.18 2112 720 13077 5176 5901 2000 64.2 MiB 0.06 0.00 4.84222 3.96328 -113.617 -3.96328 3.96328 0.25 0.000302052 0.000274458 0.0235956 0.0215408 -1 -1 -1 -1 40 2085 22 6.95648e+06 332941 706193. 2443.58 1.80 0.148459 0.129635 26914 176310 -1 1621 23 1506 2612 185027 44223 3.91416 3.91416 -121.795 -3.91416 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0165964 0.014824 73 31 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 2.47 vpr 64.86 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29800 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 32 32 336 268 1 167 85 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1783 1032 10315 2877 5917 1521 64.9 MiB 0.05 0.00 4.51952 3.92812 -130.309 -3.92812 3.92812 0.25 0.000322632 0.000292025 0.0200178 0.0182508 -1 -1 -1 -1 38 2695 38 6.95648e+06 303989 678818. 2348.85 0.88 0.0962041 0.0849132 26626 170182 -1 2290 20 1586 2944 220343 47674 3.95326 3.95326 -137.892 -3.95326 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0177714 0.0159486 76 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 2.99 vpr 65.46 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29784 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67028 32 32 366 295 1 182 89 17 17 289 -1 unnamed_device 25.6 MiB 0.25 1940 1017 15137 4323 9926 888 65.5 MiB 0.08 0.00 3.4886 3.1127 -116.972 -3.1127 3.1127 0.25 0.0003474 0.00031008 0.0306325 0.0281225 -1 -1 -1 -1 36 2556 21 6.95648e+06 361892 648988. 2245.63 1.35 0.148265 0.129937 26050 158493 -1 2163 22 1481 2233 179619 40338 3.25947 3.25947 -126.143 -3.25947 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0190004 0.0170065 81 58 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 5.15 vpr 64.68 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30108 -1 -1 14 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 27 32 259 221 1 124 73 17 17 289 -1 unnamed_device 25.2 MiB 2.03 1479 544 11169 5105 5436 628 64.7 MiB 0.04 0.00 3.66833 3.46173 -93.1309 -3.46173 3.46173 0.25 0.000261857 0.000239568 0.0209747 0.0192546 -1 -1 -1 -1 38 1555 46 6.95648e+06 202660 678818. 2348.85 1.71 0.145141 0.126544 26626 170182 -1 1272 22 1128 1830 194540 63071 2.72212 2.72212 -92.3383 -2.72212 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0173633 0.0154463 52 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_008.v common 2.44 vpr 65.14 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30192 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 25.2 MiB 0.13 1731 837 13758 3354 9842 562 65.1 MiB 0.06 0.00 3.236 3.0033 -96.4877 -3.0033 3.0033 0.25 0.000283257 0.000257476 0.0224466 0.0205166 -1 -1 -1 -1 38 2185 35 6.95648e+06 390843 678818. 2348.85 0.94 0.0935904 0.0819904 26626 170182 -1 1935 17 1016 1691 155726 37439 2.85232 2.85232 -101.969 -2.85232 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0128395 0.0115411 69 4 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_009.v common 6.46 vpr 65.11 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30160 -1 -1 13 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 31 32 317 271 1 163 76 17 17 289 -1 unnamed_device 25.4 MiB 1.02 2045 984 6476 1579 4344 553 65.1 MiB 0.04 0.00 4.38541 3.20949 -116.851 -3.20949 3.20949 0.25 0.000304035 0.000278359 0.0141149 0.0129919 -1 -1 -1 -1 38 2225 23 6.95648e+06 188184 678818. 2348.85 4.11 0.175878 0.153736 26626 170182 -1 1916 23 1238 1764 156025 32304 3.10437 3.10437 -120.049 -3.10437 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0167635 0.0150094 63 64 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_010.v common 2.47 vpr 64.80 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29756 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 298 248 1 150 75 17 17 289 -1 unnamed_device 25.2 MiB 0.52 1624 626 11135 4403 5579 1153 64.8 MiB 0.05 0.00 3.54488 3.30308 -115.111 -3.30308 3.30308 0.25 0.000294589 0.000269238 0.0240851 0.0221711 -1 -1 -1 -1 40 1722 35 6.95648e+06 159232 706193. 2443.58 0.62 0.0818033 0.0720409 26914 176310 -1 1420 24 1290 1850 123276 30882 3.09812 3.09812 -112.612 -3.09812 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.0168038 0.0149627 60 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_011.v common 4.11 vpr 64.83 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29584 -1 -1 12 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 30 32 303 262 1 135 74 17 17 289 -1 unnamed_device 25.2 MiB 0.66 1495 729 9064 2569 5999 496 64.8 MiB 0.04 0.00 3.68438 3.28838 -103.976 -3.28838 3.28838 0.24 0.000292096 0.000267169 0.0187869 0.0172538 -1 -1 -1 -1 34 1814 26 6.95648e+06 173708 618332. 2139.56 2.16 0.138849 0.120791 25762 151098 -1 1490 24 1184 1664 130152 30363 3.42052 3.42052 -114.288 -3.42052 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0178223 0.0157866 54 63 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 6.43 vpr 65.00 MiB -1 -1 0.13 17672 1 0.03 -1 -1 30076 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 32 32 276 237 1 161 77 17 17 289 -1 unnamed_device 25.2 MiB 0.89 1858 901 11324 2936 7996 392 65.0 MiB 0.05 0.00 4.14163 3.40773 -113.867 -3.40773 3.40773 0.25 0.000320972 0.000297119 0.0219671 0.0201439 -1 -1 -1 -1 38 2225 33 6.95648e+06 188184 678818. 2348.85 4.06 0.177221 0.15457 26626 170182 -1 1830 23 1206 1558 121613 27198 3.12917 3.12917 -117.675 -3.12917 0 0 902133. 3121.57 0.03 0.04 0.10 -1 -1 0.03 0.0181981 0.0163783 61 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_013.v common 7.28 vpr 64.84 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29752 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 344 272 1 194 81 17 17 289 -1 unnamed_device 25.2 MiB 1.00 2661 1052 13556 4454 6679 2423 64.8 MiB 0.07 0.00 4.95968 4.03143 -135.537 -4.03143 4.03143 0.24 0.000326325 0.000299541 0.0282066 0.0259143 -1 -1 -1 -1 38 2740 31 6.95648e+06 246087 678818. 2348.85 4.74 0.196684 0.172533 26626 170182 -1 2270 20 1490 2238 167680 36771 3.49922 3.49922 -132.659 -3.49922 0 0 902133. 3121.57 0.04 0.07 0.13 -1 -1 0.04 0.0232164 0.0208544 80 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_014.v common 3.32 vpr 65.40 MiB -1 -1 0.19 18056 1 0.04 -1 -1 30120 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66968 32 32 363 295 1 174 89 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2639 1006 16721 5083 10286 1352 65.4 MiB 0.07 0.00 5.50502 4.26608 -134.261 -4.26608 4.26608 0.24 0.000347966 0.00031851 0.0304499 0.0278639 -1 -1 -1 -1 44 2225 22 6.95648e+06 361892 787024. 2723.27 1.60 0.154803 0.135854 27778 195446 -1 2034 24 1656 2393 186636 39712 3.87492 3.87492 -138.683 -3.87492 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0186054 0.0166199 78 61 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_015.v common 3.30 vpr 64.66 MiB -1 -1 0.19 18060 1 0.03 -1 -1 29916 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 29 32 248 215 1 132 79 17 17 289 -1 unnamed_device 25.6 MiB 0.37 1589 651 12078 4589 5218 2271 64.7 MiB 0.05 0.00 3.39735 2.90715 -89.179 -2.90715 2.90715 0.25 0.000252159 0.00023083 0.0201331 0.0184469 -1 -1 -1 -1 32 1836 31 6.95648e+06 260562 586450. 2029.24 1.34 0.118347 0.102735 25474 144626 -1 1503 20 997 1583 125466 28770 3.05702 3.05702 -99.4476 -3.05702 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0205365 0.0182302 55 27 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 2.73 vpr 64.73 MiB -1 -1 0.12 18060 1 0.04 -1 -1 29784 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 370 297 1 178 81 17 17 289 -1 unnamed_device 25.6 MiB 0.39 2049 1029 11981 3954 6378 1649 64.7 MiB 0.06 0.00 3.37235 3.1427 -120.775 -3.1427 3.1427 0.25 0.00035851 0.000328148 0.0268688 0.0246765 -1 -1 -1 -1 36 2643 31 6.95648e+06 246087 648988. 2245.63 0.88 0.10544 0.0937733 26050 158493 -1 2255 24 1811 2949 246149 54989 3.28927 3.28927 -130.375 -3.28927 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0197367 0.0176201 77 58 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 4.33 vpr 65.27 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29808 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66840 32 32 338 269 1 190 81 17 17 289 -1 unnamed_device 26.0 MiB 1.14 2597 1132 10756 3252 6270 1234 65.3 MiB 0.09 0.00 4.76516 3.87916 -128.033 -3.87916 3.87916 0.27 0.000563673 0.000514764 0.0381079 0.0349105 -1 -1 -1 -1 42 2528 39 6.95648e+06 246087 744469. 2576.02 1.76 0.175647 0.154706 27202 183097 -1 2217 22 1720 2455 228601 47027 3.26597 3.26597 -129.76 -3.26597 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0178021 0.0160045 78 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_018.v common 2.86 vpr 64.37 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30132 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 32 32 323 276 1 148 80 17 17 289 -1 unnamed_device 25.1 MiB 0.47 1940 709 13324 5680 7328 316 64.4 MiB 0.06 0.00 2.8806 2.25046 -92.451 -2.25046 2.25046 0.24 0.000321601 0.000294567 0.0263952 0.0242186 -1 -1 -1 -1 38 2063 49 6.95648e+06 231611 678818. 2348.85 1.00 0.109513 0.096137 26626 170182 -1 1469 19 1138 1719 118571 27421 2.31168 2.31168 -99.7954 -2.31168 0 0 902133. 3121.57 0.04 0.04 0.11 -1 -1 0.04 0.0146975 0.0132061 61 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_019.v common 2.39 vpr 64.57 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29840 -1 -1 11 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 30 32 222 206 1 114 73 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1511 777 10865 4570 5988 307 64.6 MiB 0.04 0.00 2.51091 2.19546 -86.0348 -2.19546 2.19546 0.24 0.000228699 0.000208066 0.0176833 0.0161505 -1 -1 -1 -1 30 1680 41 6.95648e+06 159232 556674. 1926.21 1.04 0.0942002 0.0812793 25186 138497 -1 1470 25 872 1208 156123 52175 2.24868 2.24868 -93.6233 -2.24868 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0130512 0.0115238 44 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_020.v common 4.25 vpr 65.08 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29832 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66644 31 32 291 243 1 167 77 17 17 289 -1 unnamed_device 25.2 MiB 1.28 1942 915 11161 3690 6402 1069 65.1 MiB 0.05 0.00 5.06493 4.53133 -147.051 -4.53133 4.53133 0.25 0.000298558 0.000268472 0.0217239 0.0198683 -1 -1 -1 -1 36 2497 27 6.95648e+06 202660 648988. 2245.63 1.65 0.13307 0.116025 26050 158493 -1 2085 22 1516 2176 182935 41144 4.25897 4.25897 -152.532 -4.25897 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0156028 0.0139499 68 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 4.09 vpr 65.23 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30352 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66792 32 32 342 271 1 172 91 17 17 289 -1 unnamed_device 26.0 MiB 0.15 2240 900 16819 7148 9182 489 65.2 MiB 0.09 0.00 4.59829 3.69419 -127.892 -3.69419 3.69419 0.25 0.000327843 0.000299751 0.0411088 0.0379383 -1 -1 -1 -1 36 2377 35 6.95648e+06 390843 648988. 2245.63 2.54 0.186161 0.164863 26050 158493 -1 1845 26 1702 2575 179217 41202 3.87196 3.87196 -134.248 -3.87196 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0217552 0.0194069 79 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_022.v common 7.73 vpr 65.38 MiB -1 -1 0.18 17676 1 0.03 -1 -1 30120 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66948 32 32 372 300 1 200 80 17 17 289 -1 unnamed_device 25.6 MiB 0.78 2415 1121 6444 1474 4751 219 65.4 MiB 0.04 0.00 5.37301 4.45576 -133.655 -4.45576 4.45576 0.26 0.00035798 0.00032954 0.0151061 0.0139068 -1 -1 -1 -1 38 2880 26 6.95648e+06 231611 678818. 2348.85 5.52 0.175453 0.15353 26626 170182 -1 2526 22 1727 2641 222774 46845 4.34031 4.34031 -139.36 -4.34031 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0185616 0.0166569 82 62 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_023.v common 2.66 vpr 64.47 MiB -1 -1 0.10 18060 1 0.02 -1 -1 30160 -1 -1 15 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66020 26 32 190 182 1 104 73 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1222 421 8281 3372 4348 561 64.5 MiB 0.03 0.00 2.67211 2.19726 -65.4152 -2.19726 2.19726 0.26 0.000228356 0.00020948 0.0126875 0.0116165 -1 -1 -1 -1 34 1125 29 6.95648e+06 217135 618332. 2139.56 1.06 0.0810129 0.0700315 25762 151098 -1 896 17 520 688 56109 14316 2.11048 2.11048 -70.2765 -2.11048 0 0 787024. 2723.27 0.04 0.03 0.12 -1 -1 0.04 0.0133129 0.0119175 44 30 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_024.v common 6.89 vpr 64.69 MiB -1 -1 0.10 17676 1 0.03 -1 -1 29772 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 285 227 1 159 81 17 17 289 -1 unnamed_device 25.2 MiB 0.35 1875 1004 10231 3152 5666 1413 64.7 MiB 0.06 0.00 5.1927 4.35141 -124.49 -4.35141 4.35141 0.25 0.000474772 0.000449994 0.0235867 0.0218554 -1 -1 -1 -1 36 2522 34 6.95648e+06 246087 648988. 2245.63 5.19 0.179034 0.157958 26050 158493 -1 2149 24 1520 2509 215703 44929 4.03036 4.03036 -133.912 -4.03036 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0165415 0.0147724 66 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 2.43 vpr 64.38 MiB -1 -1 0.09 17676 1 0.02 -1 -1 30096 -1 -1 10 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 25.1 MiB 0.07 1407 728 7049 2858 4069 122 64.4 MiB 0.02 0.00 2.65931 2.13126 -73.9387 -2.13126 2.13126 0.35 0.000195657 0.000177916 0.0099747 0.00911854 -1 -1 -1 -1 32 1341 22 6.95648e+06 144757 586450. 2029.24 1.01 0.0883843 0.0759555 25474 144626 -1 1180 22 633 749 76305 16284 2.09038 2.09038 -81.6951 -2.09038 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0107041 0.00951017 43 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_026.v common 5.27 vpr 65.07 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29532 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 300 245 1 159 83 17 17 289 -1 unnamed_device 25.2 MiB 0.32 1864 913 6383 1452 4629 302 65.1 MiB 0.04 0.00 5.25865 4.40051 -125.247 -4.40051 4.40051 0.26 0.000324656 0.000298873 0.0125488 0.0115213 -1 -1 -1 -1 34 2450 32 6.95648e+06 275038 618332. 2139.56 3.53 0.144068 0.12555 25762 151098 -1 1968 22 1275 2064 154484 34551 3.92096 3.92096 -128.528 -3.92096 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0158121 0.0141592 67 24 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_027.v common 3.01 vpr 64.59 MiB -1 -1 0.15 17912 1 0.04 -1 -1 29932 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66136 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 25.6 MiB 0.11 1827 924 6823 1513 4978 332 64.6 MiB 0.04 0.00 3.55265 2.9965 -104.682 -2.9965 2.9965 0.25 0.000516058 0.000468551 0.0159334 0.0147054 -1 -1 -1 -1 36 2414 49 6.95648e+06 390843 648988. 2245.63 1.42 0.124523 0.109913 26050 158493 -1 2132 24 1474 2395 199348 43414 3.61137 3.61137 -119.408 -3.61137 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0172033 0.015398 77 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_028.v common 8.45 vpr 64.66 MiB -1 -1 0.12 18036 1 0.04 -1 -1 30072 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 338 277 1 172 87 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2669 874 15063 4561 8642 1860 64.7 MiB 0.07 0.00 5.40282 4.22168 -126.749 -4.22168 4.22168 0.24 0.000319671 0.000291658 0.02712 0.0248042 -1 -1 -1 -1 36 2848 47 6.95648e+06 332941 648988. 2245.63 6.44 0.185299 0.162867 26050 158493 -1 2116 21 1518 2498 224468 49562 4.10051 4.10051 -134.747 -4.10051 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0182949 0.0163777 74 50 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_029.v common 3.03 vpr 64.75 MiB -1 -1 0.19 17676 1 0.02 -1 -1 29812 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 284 241 1 139 79 17 17 289 -1 unnamed_device 25.6 MiB 0.33 1680 676 6670 1523 4966 181 64.7 MiB 0.04 0.00 3.27205 2.9051 -100.648 -2.9051 2.9051 0.24 0.000284299 0.000260273 0.0131353 0.012032 -1 -1 -1 -1 42 1765 28 6.95648e+06 217135 744469. 2576.02 1.26 0.115797 0.100284 27202 183097 -1 1497 22 1119 1800 140720 33242 2.86952 2.86952 -107.095 -2.86952 0 0 949917. 3286.91 0.03 0.04 0.10 -1 -1 0.03 0.0149791 0.0133634 57 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_030.v common 2.72 vpr 64.80 MiB -1 -1 0.14 18060 1 0.02 -1 -1 29852 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 30 32 262 227 1 134 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1538 820 8831 2040 6273 518 64.8 MiB 0.05 0.00 3.47888 3.21595 -101.099 -3.21595 3.21595 0.36 0.000386212 0.000355056 0.0224496 0.020607 -1 -1 -1 -1 32 1847 36 6.95648e+06 275038 586450. 2029.24 1.08 0.108432 0.0945639 25474 144626 -1 1689 22 1091 1749 148756 32107 3.02582 3.02582 -108.609 -3.02582 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0174901 0.0155263 59 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_031.v common 4.82 vpr 64.29 MiB -1 -1 0.14 16988 1 0.03 -1 -1 29608 -1 -1 21 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 28 32 260 223 1 135 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1490 680 8131 2137 5414 580 64.3 MiB 0.04 0.00 3.44925 2.9041 -94.451 -2.9041 2.9041 0.25 0.000306648 0.000271689 0.0168356 0.0155005 -1 -1 -1 -1 36 1823 27 6.95648e+06 303989 648988. 2245.63 3.31 0.15174 0.132313 26050 158493 -1 1652 18 950 1569 148138 33466 3.16212 3.16212 -107.018 -3.16212 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0121723 0.0109062 60 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_032.v common 3.39 vpr 64.12 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29812 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65664 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 24.9 MiB 0.12 1566 824 4152 861 3106 185 64.1 MiB 0.03 0.00 3.63718 3.35753 -114.051 -3.35753 3.35753 0.26 0.000266189 0.000243736 0.0126143 0.0117093 -1 -1 -1 -1 38 1997 21 6.95648e+06 188184 678818. 2348.85 1.83 0.153 0.132863 26626 170182 -1 1719 21 1284 1950 159352 33411 2.89152 2.89152 -114.478 -2.89152 0 0 902133. 3121.57 0.03 0.04 0.12 -1 -1 0.03 0.0157463 0.0139925 59 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_033.v common 3.90 vpr 64.73 MiB -1 -1 0.20 17676 1 0.02 -1 -1 29760 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 31 32 271 231 1 143 80 17 17 289 -1 unnamed_device 25.2 MiB 0.11 1688 869 8680 2729 4472 1479 64.7 MiB 0.04 0.00 3.72648 3.16398 -108.388 -3.16398 3.16398 0.25 0.00027281 0.000249896 0.0156627 0.0143815 -1 -1 -1 -1 34 2179 22 6.95648e+06 246087 618332. 2139.56 2.41 0.131565 0.114533 25762 151098 -1 2014 21 1110 1930 166652 35472 3.09012 3.09012 -116.571 -3.09012 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0141418 0.0126396 60 30 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_034.v common 4.04 vpr 65.15 MiB -1 -1 0.16 18056 1 0.02 -1 -1 29796 -1 -1 20 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 29 32 291 250 1 148 81 17 17 289 -1 unnamed_device 25.2 MiB 0.55 1854 689 13206 5558 7105 543 65.1 MiB 0.06 0.00 2.91366 2.41246 -87.9827 -2.41246 2.41246 0.25 0.000281282 0.000256616 0.0241148 0.0221193 -1 -1 -1 -1 36 2057 43 6.95648e+06 289514 648988. 2245.63 1.88 0.158976 0.138171 26050 158493 -1 1583 29 1369 1971 208107 67819 2.98053 2.98053 -102.288 -2.98053 0 0 828058. 2865.25 0.03 0.07 0.09 -1 -1 0.03 0.0181052 0.0160143 63 54 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_035.v common 7.24 vpr 64.71 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29616 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 367 282 1 193 97 17 17 289 -1 unnamed_device 25.6 MiB 0.21 2526 1025 17413 5779 8975 2659 64.7 MiB 0.08 0.00 5.03788 4.17868 -123.252 -4.17868 4.17868 0.25 0.000357228 0.000325244 0.030235 0.0275701 -1 -1 -1 -1 42 2595 19 6.95648e+06 477698 744469. 2576.02 5.55 0.206893 0.181707 27202 183097 -1 2211 31 1710 2988 296315 99088 3.69472 3.69472 -122.109 -3.69472 0 0 949917. 3286.91 0.03 0.09 0.11 -1 -1 0.03 0.0247971 0.0221375 91 29 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_036.v common 3.70 vpr 65.41 MiB -1 -1 0.12 18300 1 0.03 -1 -1 29748 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 391 311 1 184 96 17 17 289 -1 unnamed_device 25.6 MiB 0.38 2256 862 16740 6194 8330 2216 65.4 MiB 0.08 0.00 3.74582 3.41048 -122.287 -3.41048 3.41048 0.34 0.000358304 0.000326722 0.0296809 0.0270057 -1 -1 -1 -1 44 2238 38 6.95648e+06 463222 787024. 2723.27 1.75 0.167056 0.145504 27778 195446 -1 1850 25 2011 3068 224363 51977 3.35632 3.35632 -126.689 -3.35632 0 0 997811. 3452.63 0.04 0.06 0.12 -1 -1 0.04 0.0204384 0.0182152 88 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_037.v common 3.57 vpr 64.55 MiB -1 -1 0.12 18052 1 0.02 -1 -1 30172 -1 -1 13 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 31 32 279 237 1 159 76 17 17 289 -1 unnamed_device 25.5 MiB 0.74 1859 944 11436 4031 5937 1468 64.6 MiB 0.05 0.00 4.42062 3.66882 -116.881 -3.66882 3.66882 0.25 0.000536804 0.000511655 0.0225096 0.020716 -1 -1 -1 -1 40 2026 25 6.95648e+06 188184 706193. 2443.58 1.40 0.115557 0.10067 26914 176310 -1 1930 22 1362 1958 174593 39631 3.25737 3.25737 -121.471 -3.25737 0 0 926341. 3205.33 0.03 0.05 0.13 -1 -1 0.03 0.0175896 0.015843 65 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_038.v common 3.50 vpr 64.73 MiB -1 -1 0.13 18060 1 0.04 -1 -1 30156 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 31 32 370 297 1 179 82 17 17 289 -1 unnamed_device 26.0 MiB 0.37 2058 981 11474 4741 6449 284 64.7 MiB 0.06 0.00 4.15263 3.41873 -120.517 -3.41873 3.41873 0.25 0.000343553 0.000314072 0.0242446 0.0222411 -1 -1 -1 -1 36 2791 28 6.95648e+06 275038 648988. 2245.63 1.51 0.113157 0.100064 26050 158493 -1 2313 25 1860 2917 241256 52575 3.29867 3.29867 -128.902 -3.29867 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0199085 0.017774 78 61 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_039.v common 4.99 vpr 65.45 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29748 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67020 31 32 377 302 1 231 84 17 17 289 -1 unnamed_device 26.0 MiB 1.01 2986 1206 16188 5856 7795 2537 65.4 MiB 0.09 0.00 6.98421 5.23991 -167.77 -5.23991 5.23991 0.24 0.000345786 0.000316332 0.0397705 0.0366514 -1 -1 -1 -1 44 3341 26 6.95648e+06 303989 787024. 2723.27 2.49 0.212114 0.187739 27778 195446 -1 2677 24 2355 3504 330191 67709 4.75275 4.75275 -167.178 -4.75275 0 0 997811. 3452.63 0.04 0.07 0.11 -1 -1 0.04 0.0199259 0.0178701 99 64 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_040.v common 3.87 vpr 65.04 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30152 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 31 32 383 305 1 201 80 17 17 289 -1 unnamed_device 25.6 MiB 1.19 2460 938 14012 6050 7484 478 65.0 MiB 0.07 0.00 5.07595 4.39319 -147.97 -4.39319 4.39319 0.30 0.000353719 0.000323381 0.0319885 0.0293714 -1 -1 -1 -1 46 2574 33 6.95648e+06 246087 828058. 2865.25 1.19 0.122738 0.108773 28066 200906 -1 2087 21 1723 2601 166326 39721 4.33271 4.33271 -148.753 -4.33271 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0184975 0.0166052 88 64 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_041.v common 6.56 vpr 63.99 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65524 31 32 352 285 1 177 86 17 17 289 -1 unnamed_device 25.3 MiB 0.61 1905 1063 13505 4619 6904 1982 64.0 MiB 0.07 0.00 3.86153 3.50353 -122.837 -3.50353 3.50353 0.25 0.000334119 0.000306413 0.0260397 0.023895 -1 -1 -1 -1 38 2691 24 6.95648e+06 332941 678818. 2348.85 4.55 0.175979 0.154524 26626 170182 -1 2207 20 1543 2431 175549 38503 3.17607 3.17607 -124.233 -3.17607 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0179781 0.0161697 79 55 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_042.v common 2.72 vpr 65.22 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66788 32 32 291 242 1 173 82 17 17 289 -1 unnamed_device 25.4 MiB 0.58 2234 1084 10050 2925 5856 1269 65.2 MiB 0.05 0.00 5.02688 4.05268 -121.011 -4.05268 4.05268 0.24 0.000289648 0.000264781 0.018507 0.0170161 -1 -1 -1 -1 36 2592 25 6.95648e+06 260562 648988. 2245.63 0.78 0.0776036 0.068171 26050 158493 -1 2252 21 1397 2007 181674 36928 3.91432 3.91432 -125.021 -3.91432 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0149357 0.0133601 70 27 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_043.v common 8.70 vpr 65.39 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30288 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 32 32 457 356 1 214 92 17 17 289 -1 unnamed_device 26.0 MiB 0.61 3011 1199 9614 2248 6243 1123 65.4 MiB 0.06 0.00 5.60998 4.24958 -145.469 -4.24958 4.24958 0.25 0.000422765 0.000388597 0.0221656 0.0203896 -1 -1 -1 -1 36 3239 50 6.95648e+06 405319 648988. 2245.63 6.67 0.281134 0.247038 26050 158493 -1 2666 23 2075 3298 272107 58339 4.23492 4.23492 -151.925 -4.23492 0 0 828058. 2865.25 0.03 0.07 0.09 -1 -1 0.03 0.0229493 0.0205874 97 87 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_044.v common 1.98 vpr 64.71 MiB -1 -1 0.11 17912 1 0.02 -1 -1 30264 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 31 32 261 225 1 138 80 17 17 289 -1 unnamed_device 25.6 MiB 0.21 1501 818 9024 2908 5023 1093 64.7 MiB 0.04 0.00 3.4146 3.0387 -101.681 -3.0387 3.0387 0.25 0.000266387 0.000243369 0.0156035 0.0143094 -1 -1 -1 -1 32 2004 40 6.95648e+06 246087 586450. 2029.24 0.49 0.0599967 0.0526947 25474 144626 -1 1709 22 1202 1786 156398 34480 3.27367 3.27367 -111.108 -3.27367 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0143091 0.0127558 58 28 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_045.v common 4.00 vpr 64.32 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29872 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 31 32 337 267 1 199 81 17 17 289 -1 unnamed_device 25.6 MiB 0.71 2145 1112 10931 4151 5627 1153 64.3 MiB 0.06 0.00 4.85719 4.35599 -139.539 -4.35599 4.35599 0.25 0.000344925 0.000316949 0.0228979 0.021019 -1 -1 -1 -1 46 2578 27 6.95648e+06 260562 828058. 2865.25 1.80 0.152247 0.133516 28066 200906 -1 2222 20 1385 2128 175307 36107 4.35122 4.35122 -143.095 -4.35122 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0206612 0.0185831 82 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 5.18 vpr 65.28 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29724 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 349 284 1 175 90 17 17 289 -1 unnamed_device 25.6 MiB 0.32 2157 965 10542 2851 6614 1077 65.3 MiB 0.06 0.00 3.52265 3.1127 -108.745 -3.1127 3.1127 0.24 0.000330891 0.000302135 0.0192964 0.0176786 -1 -1 -1 -1 36 2961 34 6.95648e+06 376368 648988. 2245.63 3.51 0.168227 0.14795 26050 158493 -1 2355 20 1415 2400 212790 47241 3.46317 3.46317 -122.988 -3.46317 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0163403 0.0146583 78 53 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_047.v common 4.70 vpr 65.20 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29816 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 32 32 291 230 1 161 83 17 17 289 -1 unnamed_device 25.6 MiB 0.22 1764 988 11603 4009 6122 1472 65.2 MiB 0.05 0.00 4.66672 3.99627 -123.227 -3.99627 3.99627 0.25 0.000450265 0.000422578 0.0219192 0.0201582 -1 -1 -1 -1 36 2563 29 6.95648e+06 275038 648988. 2245.63 2.93 0.158681 0.13936 26050 158493 -1 2183 22 1428 2520 202696 44123 3.83276 3.83276 -133.9 -3.83276 0 0 828058. 2865.25 0.04 0.08 0.14 -1 -1 0.04 0.0269728 0.0241938 70 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_048.v common 3.77 vpr 65.38 MiB -1 -1 0.17 18056 1 0.04 -1 -1 30056 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 353 287 1 190 80 17 17 289 -1 unnamed_device 25.6 MiB 1.14 2163 1097 11948 3658 6620 1670 65.4 MiB 0.06 0.00 4.63715 4.346 -136.985 -4.346 4.346 0.27 0.000328162 0.000300805 0.0253231 0.0232672 -1 -1 -1 -1 34 2975 47 6.95648e+06 231611 618332. 2139.56 0.96 0.10334 0.0912855 25762 151098 -1 2354 20 1518 2047 175086 38630 3.82676 3.82676 -139.13 -3.82676 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0164645 0.014809 76 55 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_049.v common 2.80 vpr 65.41 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66976 32 32 361 291 1 178 93 17 17 289 -1 unnamed_device 25.6 MiB 0.36 2190 1077 15423 4714 8722 1987 65.4 MiB 0.07 0.00 3.80407 3.1427 -117.276 -3.1427 3.1427 0.24 0.000335494 0.00030613 0.0268972 0.0246316 -1 -1 -1 -1 36 2642 22 6.95648e+06 419795 648988. 2245.63 1.07 0.115534 0.102164 26050 158493 -1 2227 23 1499 2470 188526 40710 3.00577 3.00577 -119.751 -3.00577 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0206086 0.0184721 81 55 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_050.v common 3.78 vpr 65.39 MiB -1 -1 0.21 18056 1 0.04 -1 -1 29324 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66960 32 32 382 305 1 184 92 17 17 289 -1 unnamed_device 26.0 MiB 0.26 1992 927 11891 3545 6012 2334 65.4 MiB 0.06 0.00 4.22719 3.72599 -122.298 -3.72599 3.72599 0.25 0.000354423 0.000324206 0.022889 0.0209982 -1 -1 -1 -1 38 2841 35 6.95648e+06 405319 678818. 2348.85 1.97 0.123296 0.108865 26626 170182 -1 2185 23 1596 2460 203199 45565 3.39842 3.39842 -128.958 -3.39842 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0194308 0.0173982 86 62 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_051.v common 3.43 vpr 64.74 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29772 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66292 32 32 306 248 1 160 86 17 17 289 -1 unnamed_device 25.2 MiB 0.41 1773 991 12182 3165 8076 941 64.7 MiB 0.06 0.00 4.66977 4.24147 -124.389 -4.24147 4.24147 0.25 0.000303542 0.000277176 0.0212523 0.0194711 -1 -1 -1 -1 44 2187 23 6.95648e+06 318465 787024. 2723.27 1.56 0.130789 0.114575 27778 195446 -1 1919 20 1150 1977 158945 33393 3.70736 3.70736 -126.727 -3.70736 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0150716 0.01354 70 24 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_052.v common 3.63 vpr 64.13 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29560 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 32 32 319 257 1 191 81 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2389 1129 13556 4515 7064 1977 64.1 MiB 0.07 0.00 5.21638 4.27023 -132.909 -4.27023 4.27023 0.25 0.00032728 0.00029993 0.0285934 0.0263253 -1 -1 -1 -1 46 2261 24 6.95648e+06 246087 828058. 2865.25 1.56 0.139003 0.122239 28066 200906 -1 2053 19 1489 2067 148493 32149 3.91922 3.91922 -135.811 -3.91922 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0243854 0.0220312 78 29 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_053.v common 4.48 vpr 64.78 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29732 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 373 299 1 197 80 17 17 289 -1 unnamed_device 26.0 MiB 0.83 2531 897 9540 3871 5214 455 64.8 MiB 0.05 0.00 5.05188 4.17558 -131.538 -4.17558 4.17558 0.25 0.00034728 0.000317831 0.022077 0.0202609 -1 -1 -1 -1 52 2602 45 6.95648e+06 246087 926341. 3205.33 2.17 0.168751 0.148119 29218 227130 -1 1929 23 1708 2759 217252 49174 3.83221 3.83221 -127.134 -3.83221 0 0 1.14541e+06 3963.36 0.04 0.05 0.12 -1 -1 0.04 0.0187353 0.0168008 84 62 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_054.v common 8.14 vpr 65.36 MiB -1 -1 0.18 18296 1 0.03 -1 -1 30104 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66928 32 32 387 315 1 182 79 17 17 289 -1 unnamed_device 25.6 MiB 0.44 1967 1073 7177 2229 3943 1005 65.4 MiB 0.04 0.00 4.52855 3.87614 -130.615 -3.87614 3.87614 0.31 0.000389174 0.000358475 0.0179409 0.0165194 -1 -1 -1 -1 36 3074 47 6.95648e+06 217135 648988. 2245.63 6.15 0.265094 0.23242 26050 158493 -1 2610 24 1796 3077 296639 62485 4.18392 4.18392 -145.171 -4.18392 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.020107 0.0180066 76 77 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_055.v common 2.83 vpr 64.64 MiB -1 -1 0.10 17912 1 0.02 -1 -1 29788 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66192 32 32 251 219 1 136 80 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1592 878 8852 2868 4758 1226 64.6 MiB 0.04 0.00 3.87998 3.17038 -103.769 -3.17038 3.17038 0.25 0.000264988 0.00024193 0.0149789 0.0137099 -1 -1 -1 -1 36 2026 24 6.95648e+06 231611 648988. 2245.63 1.46 0.117846 0.102121 26050 158493 -1 1799 19 1076 1732 149430 31991 3.22042 3.22042 -107.606 -3.22042 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0127789 0.0114464 56 23 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_056.v common 3.40 vpr 65.29 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29828 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66860 32 32 341 285 1 183 78 17 17 289 -1 unnamed_device 25.2 MiB 0.73 1846 1064 9706 3019 5412 1275 65.3 MiB 0.05 0.00 3.60009 3.47479 -130.861 -3.47479 3.47479 0.25 0.000773114 0.000715199 0.0212245 0.0194564 -1 -1 -1 -1 40 2587 46 6.95648e+06 202660 706193. 2443.58 1.27 0.118264 0.104074 26914 176310 -1 2232 22 1763 2514 248265 50335 3.32827 3.32827 -135.378 -3.32827 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0173627 0.0155392 72 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_057.v common 4.17 vpr 65.05 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30200 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 32 32 387 293 1 226 82 17 17 289 -1 unnamed_device 25.5 MiB 0.60 2660 1172 13076 5502 7259 315 65.0 MiB 0.07 0.00 5.95448 4.84692 -154.661 -4.84692 4.84692 0.25 0.000367204 0.000336088 0.0295512 0.0270804 -1 -1 -1 -1 46 3443 25 6.95648e+06 260562 828058. 2865.25 2.08 0.175334 0.154048 28066 200906 -1 2694 32 2085 3257 431955 154928 5.30886 5.30886 -163.334 -5.30886 0 0 1.01997e+06 3529.29 0.04 0.12 0.11 -1 -1 0.04 0.0268485 0.0240574 95 31 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_058.v common 3.02 vpr 65.37 MiB -1 -1 0.13 17916 1 0.03 -1 -1 30352 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66936 32 32 340 270 1 174 84 17 17 289 -1 unnamed_device 25.6 MiB 0.40 1785 1004 12162 4142 6583 1437 65.4 MiB 0.06 0.00 3.74951 3.62421 -127.524 -3.62421 3.62421 0.25 0.000328207 0.000300371 0.0237712 0.0218108 -1 -1 -1 -1 34 2614 24 6.95648e+06 289514 618332. 2139.56 1.06 0.099806 0.0878389 25762 151098 -1 2197 22 1673 2441 224418 54031 3.16082 3.16082 -132.565 -3.16082 0 0 787024. 2723.27 0.05 0.10 0.14 -1 -1 0.05 0.0315226 0.0283479 75 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_059.v common 3.39 vpr 64.27 MiB -1 -1 0.12 17532 1 0.02 -1 -1 29796 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 30 32 278 235 1 143 81 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1631 823 9181 2114 6505 562 64.3 MiB 0.05 0.00 3.34415 2.9573 -102.523 -2.9573 2.9573 0.26 0.00028315 0.000259772 0.0223587 0.0207038 -1 -1 -1 -1 36 1928 25 6.95648e+06 275038 648988. 2245.63 1.83 0.127391 0.111338 26050 158493 -1 1722 21 1126 1816 175406 51035 3.20612 3.20612 -118.395 -3.20612 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0163952 0.0145539 61 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_060.v common 9.47 vpr 65.29 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29820 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66856 32 32 431 332 1 227 82 17 17 289 -1 unnamed_device 25.6 MiB 0.98 2894 1372 10584 3239 6480 865 65.3 MiB 0.07 0.00 6.27232 5.48274 -168.026 -5.48274 5.48274 0.24 0.000400481 0.000366473 0.0260854 0.0239812 -1 -1 -1 -1 40 3261 24 6.95648e+06 260562 706193. 2443.58 7.07 0.217311 0.190731 26914 176310 -1 2808 20 2067 3042 240600 51699 5.01116 5.01116 -171.359 -5.01116 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0201692 0.0181833 94 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 3.66 vpr 64.59 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30340 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 32 32 336 268 1 169 89 17 17 289 -1 unnamed_device 25.2 MiB 0.69 1948 1025 14147 4356 8052 1739 64.6 MiB 0.06 0.00 5.21955 4.32235 -136.289 -4.32235 4.32235 0.26 0.000325361 0.00029643 0.025429 0.0232205 -1 -1 -1 -1 38 2361 27 6.95648e+06 361892 678818. 2348.85 1.59 0.152009 0.133043 26626 170182 -1 2059 21 1422 2085 156669 34906 4.01806 4.01806 -140.938 -4.01806 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0168919 0.0151418 75 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_062.v common 2.95 vpr 64.64 MiB -1 -1 0.10 17680 1 0.02 -1 -1 30328 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 231 199 1 136 80 17 17 289 -1 unnamed_device 25.6 MiB 0.15 1662 643 9368 2123 6903 342 64.6 MiB 0.05 0.00 3.47745 2.966 -95.4204 -2.966 2.966 0.26 0.000417153 0.00039395 0.0187903 0.0172787 -1 -1 -1 -1 36 2034 42 6.95648e+06 231611 648988. 2245.63 1.48 0.11454 0.0994636 26050 158493 -1 1518 21 1006 1688 188499 70294 3.07297 3.07297 -103.979 -3.07297 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0133088 0.0118814 54 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_063.v common 3.62 vpr 64.90 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29928 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66456 32 32 349 273 1 184 95 17 17 289 -1 unnamed_device 25.2 MiB 0.19 2110 1084 13919 4620 7096 2203 64.9 MiB 0.07 0.00 5.666 4.87452 -132.402 -4.87452 4.87452 0.27 0.000367143 0.000334943 0.0266391 0.0244722 -1 -1 -1 -1 36 3030 29 6.95648e+06 448746 648988. 2245.63 2.00 0.123915 0.110447 26050 158493 -1 2425 21 1662 3047 282448 59742 4.65731 4.65731 -144.362 -4.65731 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0173935 0.0156353 85 29 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_064.v common 2.65 vpr 64.11 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29776 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65652 32 32 247 207 1 142 80 17 17 289 -1 unnamed_device 25.2 MiB 0.16 1515 868 8852 2747 5050 1055 64.1 MiB 0.04 0.00 3.51345 2.9793 -108.005 -2.9793 2.9793 0.24 0.000259585 0.000237221 0.0150162 0.0137528 -1 -1 -1 -1 34 1886 24 6.95648e+06 231611 618332. 2139.56 1.18 0.0966165 0.0838043 25762 151098 -1 1797 19 1169 1788 142635 30918 3.15892 3.15892 -117.991 -3.15892 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0128545 0.0115147 58 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_065.v common 3.50 vpr 64.79 MiB -1 -1 0.16 18060 1 0.02 -1 -1 29840 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66340 30 32 278 235 1 141 87 17 17 289 -1 unnamed_device 25.6 MiB 0.33 1720 753 11223 4264 5738 1221 64.8 MiB 0.05 0.00 3.72028 3.23198 -104.978 -3.23198 3.23198 0.35 0.000279277 0.000254685 0.0198131 0.0182093 -1 -1 -1 -1 38 1855 21 6.95648e+06 361892 678818. 2348.85 1.56 0.133737 0.11684 26626 170182 -1 1614 22 1198 1946 139206 32254 3.38942 3.38942 -117.246 -3.38942 0 0 902133. 3121.57 0.05 0.06 0.14 -1 -1 0.05 0.0223008 0.0199494 64 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 3.75 vpr 65.32 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29760 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66884 29 32 355 287 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 0.71 2234 978 11948 4957 6509 482 65.3 MiB 0.06 0.00 4.18549 3.52127 -111.57 -3.52127 3.52127 0.25 0.000328695 0.000300758 0.0250101 0.0229279 -1 -1 -1 -1 44 2569 26 6.95648e+06 275038 787024. 2723.27 1.60 0.138089 0.120443 27778 195446 -1 2149 23 1910 2895 251904 52894 3.24537 3.24537 -116.207 -3.24537 0 0 997811. 3452.63 0.04 0.08 0.11 -1 -1 0.04 0.0236407 0.0211535 81 62 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_067.v common 2.87 vpr 65.26 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29760 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66824 32 32 358 289 1 171 83 17 17 289 -1 unnamed_device 26.0 MiB 0.49 2085 843 13943 6117 7487 339 65.3 MiB 0.06 0.00 5.02682 4.14368 -134.376 -4.14368 4.14368 0.24 0.000339146 0.000310561 0.0280627 0.025702 -1 -1 -1 -1 36 2481 34 6.95648e+06 275038 648988. 2245.63 1.03 0.111834 0.0985597 26050 158493 -1 1947 23 1701 2459 192548 45377 4.30012 4.30012 -147.879 -4.30012 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0185936 0.0166696 74 54 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_068.v common 8.00 vpr 65.21 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29752 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66780 32 32 353 285 1 175 84 17 17 289 -1 unnamed_device 25.9 MiB 0.37 1817 988 13443 4741 6786 1916 65.2 MiB 0.06 0.00 4.64078 4.17648 -135.842 -4.17648 4.17648 0.24 0.000324448 0.000296469 0.0260462 0.0238591 -1 -1 -1 -1 36 3048 49 6.95648e+06 289514 648988. 2245.63 6.23 0.203406 0.178319 26050 158493 -1 2385 23 1677 2692 269744 58364 4.16382 4.16382 -145.367 -4.16382 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0195483 0.0175155 77 51 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_069.v common 6.19 vpr 65.02 MiB -1 -1 0.11 17916 1 0.03 -1 -1 29808 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 276 237 1 153 76 17 17 289 -1 unnamed_device 25.6 MiB 1.10 1886 837 9356 2240 6749 367 65.0 MiB 0.05 0.00 4.63212 3.81128 -119.489 -3.81128 3.81128 0.25 0.000277956 0.000254334 0.0212686 0.0195754 -1 -1 -1 -1 38 2203 37 6.95648e+06 173708 678818. 2348.85 3.64 0.151591 0.13123 26626 170182 -1 1790 20 1149 1580 134760 29661 3.38327 3.38327 -119.839 -3.38327 0 0 902133. 3121.57 0.05 0.08 0.10 -1 -1 0.05 0.0324819 0.0289059 59 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_070.v common 3.92 vpr 64.91 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29796 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 31 32 319 272 1 165 77 17 17 289 -1 unnamed_device 25.4 MiB 1.03 1833 985 10672 3667 5493 1512 64.9 MiB 0.05 0.00 4.19022 3.70692 -123.76 -3.70692 3.70692 0.24 0.000301967 0.00027545 0.0222779 0.020474 -1 -1 -1 -1 42 2256 26 6.95648e+06 202660 744469. 2576.02 1.53 0.125605 0.109064 27202 183097 -1 2010 22 1417 2054 188245 38923 3.30947 3.30947 -128.605 -3.30947 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0163974 0.0146881 65 64 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_071.v common 3.47 vpr 65.02 MiB -1 -1 0.14 17672 1 0.03 -1 -1 30516 -1 -1 29 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66576 30 32 329 273 1 160 91 17 17 289 -1 unnamed_device 25.2 MiB 0.19 1945 745 13351 4198 6604 2549 65.0 MiB 0.08 0.00 3.7091 3.01356 -93.2618 -3.01356 3.01356 0.25 0.000760732 0.000708834 0.035933 0.033495 -1 -1 -1 -1 38 2032 20 6.95648e+06 419795 678818. 2348.85 1.76 0.146264 0.12921 26626 170182 -1 1601 22 1121 1935 125895 29552 3.02112 3.02112 -95.7193 -3.02112 0 0 902133. 3121.57 0.03 0.04 0.18 -1 -1 0.03 0.0161828 0.0144409 75 57 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_072.v common 5.36 vpr 64.51 MiB -1 -1 0.16 17676 1 0.03 -1 -1 30208 -1 -1 30 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 28 32 277 229 1 150 90 17 17 289 -1 unnamed_device 25.2 MiB 0.16 2011 872 12552 3452 7683 1417 64.5 MiB 0.06 0.00 4.66475 3.68024 -105.78 -3.68024 3.68024 0.24 0.000503075 0.000476972 0.0239511 0.0222033 -1 -1 -1 -1 32 2459 50 6.95648e+06 434271 586450. 2029.24 3.79 0.154412 0.135403 25474 144626 -1 2023 22 1254 2170 186743 41740 3.87011 3.87011 -115.393 -3.87011 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0154132 0.0137491 69 27 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_073.v common 2.40 vpr 65.05 MiB -1 -1 0.18 18060 1 0.04 -1 -1 30168 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 30 32 317 269 1 146 75 17 17 289 -1 unnamed_device 25.2 MiB 0.43 1690 920 7501 2498 3863 1140 65.1 MiB 0.04 0.00 3.88478 3.28908 -114.727 -3.28908 3.28908 0.24 0.000297594 0.000272455 0.0159031 0.0146019 -1 -1 -1 -1 32 2138 42 6.95648e+06 188184 586450. 2029.24 0.51 0.0667491 0.0588076 25474 144626 -1 1947 21 1371 2041 175235 41141 3.06372 3.06372 -123.129 -3.06372 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0152027 0.0135917 60 63 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_074.v common 10.45 vpr 64.18 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30184 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65724 32 32 335 282 1 178 78 17 17 289 -1 unnamed_device 25.2 MiB 0.98 1907 1068 11864 3789 6604 1471 64.2 MiB 0.06 0.00 3.98976 3.26039 -121.807 -3.26039 3.26039 0.25 0.000332258 0.000298989 0.0244042 0.0223413 -1 -1 -1 -1 40 2633 27 6.95648e+06 202660 706193. 2443.58 8.03 0.197614 0.173512 26914 176310 -1 2317 24 1532 2182 220982 44609 3.39857 3.39857 -132.889 -3.39857 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0197269 0.0177008 69 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_075.v common 6.33 vpr 65.14 MiB -1 -1 0.19 17676 1 0.03 -1 -1 29524 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 293 230 1 168 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1954 1022 8863 2079 6129 655 65.1 MiB 0.04 0.00 4.72172 4.01902 -124.512 -4.01902 4.01902 0.24 0.0003344 0.000307698 0.0152924 0.0139831 -1 -1 -1 -1 40 2382 38 6.95648e+06 405319 706193. 2443.58 4.77 0.171303 0.149447 26914 176310 -1 2176 25 1492 2546 211497 46101 3.93111 3.93111 -128.021 -3.93111 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0182985 0.016269 77 4 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_076.v common 8.52 vpr 65.37 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29952 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66940 32 32 350 275 1 201 81 17 17 289 -1 unnamed_device 25.8 MiB 0.86 2386 1198 10231 3183 5327 1721 65.4 MiB 0.06 0.00 5.01638 4.27059 -145.615 -4.27059 4.27059 0.25 0.000347323 0.000318969 0.0270089 0.0251911 -1 -1 -1 -1 38 3178 30 6.95648e+06 246087 678818. 2348.85 6.30 0.188955 0.166547 26626 170182 -1 2598 21 1833 2710 208293 44175 4.12906 4.12906 -152.157 -4.12906 0 0 902133. 3121.57 0.04 0.05 0.09 -1 -1 0.04 0.0179993 0.0161953 83 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_077.v common 4.33 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29768 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 385 308 1 176 91 17 17 289 -1 unnamed_device 25.6 MiB 0.76 2067 860 9067 2994 4608 1465 64.7 MiB 0.05 0.00 5.02252 4.13222 -135.728 -4.13222 4.13222 0.25 0.000357951 0.000322619 0.0220214 0.0203008 -1 -1 -1 -1 52 2139 29 6.95648e+06 390843 926341. 3205.33 2.07 0.163955 0.142438 29218 227130 -1 1758 23 1486 2566 195701 45640 3.61706 3.61706 -133.911 -3.61706 0 0 1.14541e+06 3963.36 0.04 0.05 0.14 -1 -1 0.04 0.0192195 0.0172358 81 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_078.v common 3.00 vpr 65.49 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29848 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67064 32 32 387 309 1 182 98 17 17 289 -1 unnamed_device 26.0 MiB 0.37 2383 1001 14723 3257 11066 400 65.5 MiB 0.07 0.00 4.65582 4.051 -135.3 -4.051 4.051 0.26 0.000364327 0.000329589 0.0259811 0.0236825 -1 -1 -1 -1 46 2674 49 6.95648e+06 492173 828058. 2865.25 1.18 0.131299 0.115986 28066 200906 -1 2258 24 1693 2916 231831 48343 3.79886 3.79886 -135.102 -3.79886 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0221089 0.0198942 88 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_079.v common 2.49 vpr 64.73 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29664 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 30 32 272 232 1 142 75 17 17 289 -1 unnamed_device 25.2 MiB 0.34 1640 871 10503 3905 4899 1699 64.7 MiB 0.05 0.00 4.04631 3.58091 -110.597 -3.58091 3.58091 0.25 0.000271226 0.000247969 0.0204865 0.0188574 -1 -1 -1 -1 40 1905 22 6.95648e+06 188184 706193. 2443.58 0.82 0.0881242 0.0774387 26914 176310 -1 1801 18 1073 1821 136370 29998 2.95232 2.95232 -113.094 -2.95232 0 0 926341. 3205.33 0.03 0.04 0.09 -1 -1 0.03 0.0127374 0.0114172 58 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_080.v common 3.12 vpr 64.73 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29792 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66280 30 32 375 299 1 179 78 17 17 289 -1 unnamed_device 25.6 MiB 0.20 2263 979 14022 6059 7515 448 64.7 MiB 0.07 0.00 4.96142 3.95902 -134.036 -3.95902 3.95902 0.24 0.000345961 0.000317658 0.0343629 0.0315794 -1 -1 -1 -1 40 2208 27 6.95648e+06 231611 706193. 2443.58 1.48 0.146559 0.128454 26914 176310 -1 1994 23 2050 2994 247756 52238 3.84676 3.84676 -136.997 -3.84676 0 0 926341. 3205.33 0.03 0.08 0.11 -1 -1 0.03 0.0293045 0.0261939 78 63 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_081.v common 4.32 vpr 65.41 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29852 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 340 270 1 193 82 17 17 289 -1 unnamed_device 25.3 MiB 0.83 2252 1135 5422 1105 3974 343 65.4 MiB 0.03 0.00 5.21041 4.51361 -142.408 -4.51361 4.51361 0.25 0.000326717 0.000299349 0.0118588 0.010928 -1 -1 -1 -1 48 2777 21 6.95648e+06 260562 865456. 2994.66 2.04 0.1506 0.131797 28354 207349 -1 2286 24 1653 2579 248336 48799 4.23062 4.23062 -147.459 -4.23062 0 0 1.05005e+06 3633.38 0.04 0.06 0.11 -1 -1 0.04 0.0184952 0.0165578 80 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_082.v common 7.39 vpr 65.29 MiB -1 -1 0.12 18444 1 0.04 -1 -1 29792 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66852 31 32 340 275 1 188 79 17 17 289 -1 unnamed_device 25.4 MiB 0.83 2310 992 9543 2486 6548 509 65.3 MiB 0.06 0.00 6.40554 5.4777 -155.957 -5.4777 5.4777 0.25 0.000327639 0.000300051 0.020285 0.0186377 -1 -1 -1 -1 38 2728 50 6.95648e+06 231611 678818. 2348.85 5.14 0.179636 0.157579 26626 170182 -1 2193 21 1591 2407 184090 43251 4.33266 4.33266 -145.385 -4.33266 0 0 902133. 3121.57 0.04 0.05 0.09 -1 -1 0.04 0.0169823 0.0152252 80 47 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_083.v common 3.68 vpr 64.68 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30372 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 30 32 377 310 1 169 87 17 17 289 -1 unnamed_device 25.6 MiB 1.28 1889 756 14871 5671 7163 2037 64.7 MiB 0.06 0.00 4.34198 4.07348 -128.883 -4.07348 4.07348 0.24 0.000338279 0.000309011 0.0286867 0.0262429 -1 -1 -1 -1 40 2318 30 6.95648e+06 361892 706193. 2443.58 1.01 0.100877 0.0892676 26914 176310 -1 1820 22 1439 2322 207641 51502 3.33982 3.33982 -122.459 -3.33982 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.018083 0.0162233 76 83 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_084.v common 3.78 vpr 65.30 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30156 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66864 32 32 365 294 1 177 79 17 17 289 -1 unnamed_device 26.0 MiB 0.31 1978 1030 12247 4070 6334 1843 65.3 MiB 0.06 0.00 4.70608 4.25858 -140.542 -4.25858 4.25858 0.25 0.000351506 0.000322633 0.0273447 0.0251296 -1 -1 -1 -1 46 2664 29 6.95648e+06 217135 828058. 2865.25 2.04 0.190442 0.16687 28066 200906 -1 2305 22 1743 3062 250592 49506 3.92702 3.92702 -139.174 -3.92702 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0181199 0.016217 74 57 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_085.v common 2.99 vpr 64.88 MiB -1 -1 0.13 18444 1 0.03 -1 -1 30004 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 29 32 378 310 1 170 86 17 17 289 -1 unnamed_device 25.5 MiB 0.38 1806 1002 10670 2920 6625 1125 64.9 MiB 0.05 0.00 3.96908 3.44163 -116.475 -3.44163 3.44163 0.25 0.000347162 0.000317562 0.0214865 0.0197233 -1 -1 -1 -1 36 2578 39 6.95648e+06 361892 648988. 2245.63 1.22 0.118359 0.104523 26050 158493 -1 2261 28 1817 2808 264581 56589 3.83567 3.83567 -128.927 -3.83567 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0211173 0.0187645 78 85 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_086.v common 2.57 vpr 64.28 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30124 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 243 205 1 140 76 17 17 289 -1 unnamed_device 25.2 MiB 0.62 1666 819 5676 1328 4145 203 64.3 MiB 0.04 0.00 3.96613 3.48283 -113.364 -3.48283 3.48283 0.25 0.000466901 0.000444113 0.0149633 0.0138973 -1 -1 -1 -1 34 1869 21 6.95648e+06 173708 618332. 2139.56 0.57 0.0703562 0.0621034 25762 151098 -1 1695 23 1032 1521 123987 26549 3.10097 3.10097 -115.483 -3.10097 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0146156 0.0130885 55 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_087.v common 5.53 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66416 32 32 373 302 1 170 91 17 17 289 -1 unnamed_device 25.0 MiB 2.25 2487 909 14983 5086 7268 2629 64.9 MiB 0.07 0.00 5.45342 4.07722 -130.088 -4.07722 4.07722 0.25 0.000344536 0.000314315 0.0289953 0.0265024 -1 -1 -1 -1 48 2299 22 6.95648e+06 390843 865456. 2994.66 1.80 0.164245 0.143738 28354 207349 -1 1991 19 1367 2167 187733 39323 4.06326 4.06326 -132.586 -4.06326 0 0 1.05005e+06 3633.38 0.04 0.05 0.11 -1 -1 0.04 0.0163677 0.0147465 77 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_088.v common 2.57 vpr 64.77 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 32 32 397 314 1 188 78 17 17 289 -1 unnamed_device 25.5 MiB 0.26 2454 1052 12860 4424 7590 846 64.8 MiB 0.07 0.00 4.96142 3.97692 -145.635 -3.97692 3.97692 0.24 0.000362887 0.000332149 0.0302037 0.0277082 -1 -1 -1 -1 40 2507 27 6.95648e+06 202660 706193. 2443.58 0.88 0.104123 0.0923463 26914 176310 -1 2263 21 2040 3064 258642 54364 3.94116 3.94116 -154.866 -3.94116 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0185875 0.0166838 80 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_089.v common 3.21 vpr 63.55 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30216 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65076 32 32 269 231 1 163 77 17 17 289 -1 unnamed_device 25.0 MiB 0.84 1853 775 10346 4263 5879 204 63.6 MiB 0.05 0.00 3.82363 3.41043 -106.561 -3.41043 3.41043 0.25 0.000274716 0.000250626 0.0190657 0.017461 -1 -1 -1 -1 40 2161 23 6.95648e+06 188184 706193. 2443.58 0.92 0.0905387 0.0795776 26914 176310 -1 1801 21 1327 1750 165546 38654 3.26227 3.26227 -113.791 -3.26227 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0146235 0.0130764 64 29 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_090.v common 2.68 vpr 64.38 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29944 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 25.2 MiB 0.15 1533 780 8529 3413 4923 193 64.4 MiB 0.04 0.00 3.74228 3.28943 -106.539 -3.28943 3.28943 0.26 0.000258839 0.000236409 0.0154785 0.0142302 -1 -1 -1 -1 34 1921 28 6.95648e+06 231611 618332. 2139.56 1.20 0.108495 0.0938914 25762 151098 -1 1669 23 1353 2052 154963 33971 3.10392 3.10392 -112.189 -3.10392 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143899 0.0127996 59 4 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_091.v common 4.12 vpr 65.40 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66972 32 32 348 274 1 203 82 17 17 289 -1 unnamed_device 25.6 MiB 0.76 2467 1004 13432 4674 7054 1704 65.4 MiB 0.07 0.00 5.20718 4.12648 -139.222 -4.12648 4.12648 0.25 0.000332018 0.000303875 0.0273176 0.0250357 -1 -1 -1 -1 44 2510 23 6.95648e+06 260562 787024. 2723.27 1.70 0.141425 0.12424 27778 195446 -1 2086 22 1919 2600 212528 45424 4.00852 4.00852 -143.085 -4.00852 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0181433 0.0162844 82 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_092.v common 3.92 vpr 65.39 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29836 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 32 32 356 289 1 193 83 17 17 289 -1 unnamed_device 25.3 MiB 0.70 2587 1001 13943 3775 9769 399 65.4 MiB 0.07 0.00 5.38354 4.77262 -147.362 -4.77262 4.77262 0.25 0.00034617 0.000316777 0.0291289 0.0266296 -1 -1 -1 -1 46 2365 25 6.95648e+06 275038 828058. 2865.25 1.74 0.164581 0.144566 28066 200906 -1 2008 23 1426 2177 149929 33848 4.62936 4.62936 -148.354 -4.62936 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0184672 0.0165355 82 56 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_093.v common 2.94 vpr 65.11 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 25.6 MiB 0.14 2197 1019 15213 5463 7727 2023 65.1 MiB 0.09 0.00 5.73982 4.68117 -141.736 -4.68117 4.68117 0.34 0.000368249 0.000317849 0.0353615 0.0325265 -1 -1 -1 -1 44 2766 38 6.95648e+06 419795 787024. 2723.27 1.13 0.119924 0.107142 27778 195446 -1 2279 21 1815 3185 288567 62270 4.55991 4.55991 -145.102 -4.55991 0 0 997811. 3452.63 0.04 0.07 0.11 -1 -1 0.04 0.0206305 0.0183858 90 3 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_094.v common 2.73 vpr 64.57 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29912 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 30 32 316 264 1 156 89 17 17 289 -1 unnamed_device 25.6 MiB 0.22 1994 761 12563 2870 9117 576 64.6 MiB 0.06 0.00 3.94408 3.31423 -98.4865 -3.31423 3.31423 0.39 0.000306285 0.000278227 0.0224075 0.0205549 -1 -1 -1 -1 36 2264 42 6.95648e+06 390843 648988. 2245.63 0.99 0.131193 0.116194 26050 158493 -1 1901 21 1431 2403 188292 43569 3.19992 3.19992 -108.587 -3.19992 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0162737 0.0145473 71 52 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_095.v common 2.55 vpr 64.66 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30556 -1 -1 19 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 27 32 255 219 1 128 78 17 17 289 -1 unnamed_device 25.4 MiB 0.16 1405 640 9872 2965 6271 636 64.7 MiB 0.04 0.00 3.54465 2.9243 -92.5518 -2.9243 2.9243 0.25 0.000264446 0.000241443 0.0170022 0.0155638 -1 -1 -1 -1 32 1668 25 6.95648e+06 275038 586450. 2029.24 1.07 0.0945713 0.0820646 25474 144626 -1 1378 22 1095 1565 118686 26784 2.92552 2.92552 -98.9985 -2.92552 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0136876 0.0121712 59 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_096.v common 3.68 vpr 65.58 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29744 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67152 32 32 421 327 1 224 82 17 17 289 -1 unnamed_device 26.0 MiB 0.61 2597 1273 12720 3612 7834 1274 65.6 MiB 0.08 0.00 4.73785 3.78655 -136.554 -3.78655 3.78655 0.24 0.000384672 0.000352581 0.0300313 0.0275734 -1 -1 -1 -1 42 3519 29 6.95648e+06 260562 744469. 2576.02 1.63 0.132697 0.117622 27202 183097 -1 3005 22 2080 3405 314185 64432 3.95532 3.95532 -149.527 -3.95532 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.021025 0.0188977 93 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_097.v common 5.44 vpr 64.93 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29760 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 31 32 365 296 1 191 80 17 17 289 -1 unnamed_device 25.6 MiB 2.64 2283 1122 12292 4005 7130 1157 64.9 MiB 0.07 0.00 5.96575 5.12445 -155.529 -5.12445 5.12445 0.25 0.000337024 0.000308455 0.0295189 0.0270785 -1 -1 -1 -1 38 2762 45 6.95648e+06 246087 678818. 2348.85 1.37 0.131579 0.116282 26626 170182 -1 2224 21 1531 2248 178571 38503 4.67096 4.67096 -158.865 -4.67096 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0195671 0.0176194 81 64 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_098.v common 5.12 vpr 64.20 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30128 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65736 32 32 331 280 1 171 77 17 17 289 -1 unnamed_device 25.2 MiB 2.35 2263 831 10346 4372 5809 165 64.2 MiB 0.05 0.00 4.65874 3.66435 -131.027 -3.66435 3.66435 0.24 0.000310938 0.000283553 0.0216721 0.0198615 -1 -1 -1 -1 40 2127 20 6.95648e+06 188184 706193. 2443.58 1.44 0.137458 0.120294 26914 176310 -1 1839 21 1307 1913 170049 36740 3.63446 3.63446 -138.29 -3.63446 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0166748 0.0149375 69 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_099.v common 3.11 vpr 65.18 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30312 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66744 32 32 326 263 1 169 91 17 17 289 -1 unnamed_device 25.6 MiB 0.10 1919 1016 13147 4843 6404 1900 65.2 MiB 0.06 0.00 4.64482 4.16998 -130.262 -4.16998 4.16998 0.24 0.000346533 0.000316496 0.0224885 0.020484 -1 -1 -1 -1 40 2384 25 6.95648e+06 390843 706193. 2443.58 1.56 0.137469 0.119796 26914 176310 -1 2171 22 1287 2054 170952 36008 3.73576 3.73576 -130.81 -3.73576 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0168862 0.0151431 78 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_100.v common 5.22 vpr 64.75 MiB -1 -1 0.22 18060 1 0.03 -1 -1 29868 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66308 31 32 373 294 1 188 89 17 17 289 -1 unnamed_device 25.2 MiB 0.30 1978 1064 14147 4993 7358 1796 64.8 MiB 0.07 0.00 4.83868 4.13778 -125.088 -4.13778 4.13778 0.24 0.000347007 0.000317888 0.0269397 0.0247308 -1 -1 -1 -1 32 2893 42 6.95648e+06 376368 586450. 2029.24 3.43 0.174284 0.153096 25474 144626 -1 2450 24 1685 2597 193336 42653 3.90842 3.90842 -134.368 -3.90842 0 0 744469. 2576.02 0.03 0.06 0.09 -1 -1 0.03 0.0209366 0.0188136 86 50 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_101.v common 2.29 vpr 64.83 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29816 -1 -1 26 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66384 30 32 325 268 1 165 88 17 17 289 -1 unnamed_device 25.2 MiB 0.30 2005 1028 11788 3531 6603 1654 64.8 MiB 0.05 0.00 3.5368 3.13114 -104.094 -3.13114 3.13114 0.25 0.00031141 0.000284959 0.0207535 0.0190534 -1 -1 -1 -1 38 2346 24 6.95648e+06 376368 678818. 2348.85 0.66 0.0754822 0.0665845 26626 170182 -1 2032 19 1160 1908 135098 29773 3.16517 3.16517 -107.895 -3.16517 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0149197 0.013408 73 51 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_102.v common 7.44 vpr 64.93 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29764 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 350 275 1 208 82 17 17 289 -1 unnamed_device 25.6 MiB 0.70 2473 1225 12364 3185 8008 1171 64.9 MiB 0.08 0.00 4.77678 4.16128 -145.153 -4.16128 4.16128 0.26 0.000404071 0.000374789 0.0313753 0.0288088 -1 -1 -1 -1 44 3002 25 6.95648e+06 260562 787024. 2723.27 5.26 0.181151 0.159774 27778 195446 -1 2501 21 1929 2888 254181 52739 4.05232 4.05232 -152.306 -4.05232 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0178059 0.0160364 86 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 3.78 vpr 65.50 MiB -1 -1 0.14 18444 1 0.03 -1 -1 29880 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67076 32 32 386 307 1 187 93 17 17 289 -1 unnamed_device 25.7 MiB 0.43 2024 1035 11643 3723 6128 1792 65.5 MiB 0.06 0.00 3.74723 3.51453 -126.992 -3.51453 3.51453 0.26 0.000359398 0.000328095 0.0219604 0.0201218 -1 -1 -1 -1 38 2497 41 6.95648e+06 419795 678818. 2348.85 1.61 0.171102 0.149711 26626 170182 -1 2126 21 1643 2340 175495 37297 3.06657 3.06657 -126.206 -3.06657 0 0 902133. 3121.57 0.04 0.07 0.13 -1 -1 0.04 0.0262995 0.0235558 89 62 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_104.v common 3.91 vpr 64.29 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29856 -1 -1 13 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 29 32 269 229 1 131 74 17 17 289 -1 unnamed_device 25.2 MiB 1.98 1409 525 11234 4704 6022 508 64.3 MiB 0.06 0.00 4.32326 3.73256 -100.612 -3.73256 3.73256 0.25 0.000454335 0.00043038 0.027869 0.0258546 -1 -1 -1 -1 36 1494 27 6.95648e+06 188184 648988. 2245.63 0.58 0.0907463 0.0799895 26050 158493 -1 1158 19 812 1114 77704 18636 2.78907 2.78907 -96.8024 -2.78907 0 0 828058. 2865.25 0.03 0.03 0.08 -1 -1 0.03 0.0132226 0.0118612 54 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_105.v common 3.50 vpr 65.11 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29916 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 32 32 310 266 1 169 78 17 17 289 -1 unnamed_device 25.2 MiB 0.56 1977 706 10038 3625 5105 1308 65.1 MiB 0.05 0.00 3.7422 3.1157 -108.673 -3.1157 3.1157 0.33 0.000294774 0.000269053 0.0197681 0.0181074 -1 -1 -1 -1 40 1746 31 6.95648e+06 202660 706193. 2443.58 1.49 0.12737 0.110608 26914 176310 -1 1498 22 1422 1863 141586 36360 3.37177 3.37177 -118.821 -3.37177 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.015732 0.0140493 66 58 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_106.v common 3.58 vpr 65.12 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29912 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 31 32 326 261 1 170 94 17 17 289 -1 unnamed_device 25.2 MiB 0.17 2332 811 13087 3914 6088 3085 65.1 MiB 0.05 0.00 4.97742 3.97428 -119.674 -3.97428 3.97428 0.24 0.000315998 0.000287636 0.0230737 0.0211763 -1 -1 -1 -1 40 2279 46 6.95648e+06 448746 706193. 2443.58 2.01 0.173492 0.152007 26914 176310 -1 1762 28 1677 2723 255514 76442 3.96126 3.96126 -125.346 -3.96126 0 0 926341. 3205.33 0.04 0.08 0.10 -1 -1 0.04 0.0227733 0.0202212 80 33 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_107.v common 2.68 vpr 65.11 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29856 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66668 29 32 262 224 1 162 78 17 17 289 -1 unnamed_device 25.2 MiB 0.53 1704 832 10204 3476 5170 1558 65.1 MiB 0.04 0.00 4.25002 3.76672 -110.108 -3.76672 3.76672 0.24 0.000262567 0.000240474 0.0178239 0.0163649 -1 -1 -1 -1 34 2241 29 6.95648e+06 246087 618332. 2139.56 0.83 0.0787243 0.0694314 25762 151098 -1 1822 23 1401 1800 155915 34217 3.33297 3.33297 -112.31 -3.33297 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.01507 0.0132915 66 31 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_108.v common 4.86 vpr 64.69 MiB -1 -1 0.14 17676 1 0.02 -1 -1 30212 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66244 32 32 278 238 1 144 75 17 17 289 -1 unnamed_device 25.6 MiB 0.71 1586 629 9871 3760 4775 1336 64.7 MiB 0.05 0.00 4.25682 3.85356 -110.478 -3.85356 3.85356 0.25 0.000276118 0.000252385 0.0198227 0.0181798 -1 -1 -1 -1 36 2060 29 6.95648e+06 159232 648988. 2245.63 2.80 0.142247 0.123915 26050 158493 -1 1562 24 1364 2227 179795 40766 3.45952 3.45952 -119.804 -3.45952 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.015841 0.0140933 56 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_109.v common 3.44 vpr 64.82 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29784 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66376 31 32 373 300 1 174 94 17 17 289 -1 unnamed_device 25.5 MiB 0.39 1975 777 12235 3547 6422 2266 64.8 MiB 0.06 0.00 3.92078 3.36072 -113.014 -3.36072 3.36072 0.24 0.000343711 0.000312696 0.0218847 0.0199664 -1 -1 -1 -1 36 2383 29 6.95648e+06 448746 648988. 2245.63 1.69 0.174196 0.152739 26050 158493 -1 1890 23 1823 2630 192141 46427 3.32232 3.32232 -125.254 -3.32232 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0193631 0.0172866 83 64 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_110.v common 4.31 vpr 64.29 MiB -1 -1 0.12 17920 1 0.02 -1 -1 30204 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 31 32 265 230 1 159 77 17 17 289 -1 unnamed_device 24.6 MiB 1.08 1790 729 11813 4928 6553 332 64.3 MiB 0.05 0.00 3.77783 3.40453 -105.323 -3.40453 3.40453 0.25 0.000308872 0.000277629 0.0214596 0.0196707 -1 -1 -1 -1 40 2146 36 6.95648e+06 202660 706193. 2443.58 1.84 0.134082 0.117173 26914 176310 -1 1739 22 1464 2120 189319 43391 3.29247 3.29247 -120.401 -3.29247 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0143602 0.0128295 61 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_111.v common 3.26 vpr 64.05 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29460 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 349 286 1 165 90 17 17 289 -1 unnamed_device 25.4 MiB 0.60 2297 786 16371 5346 8562 2463 64.1 MiB 0.07 0.00 3.67454 3.219 -105.866 -3.219 3.219 0.25 0.000337391 0.000309016 0.0296005 0.0271143 -1 -1 -1 -1 36 2478 41 6.95648e+06 376368 648988. 2245.63 1.24 0.10822 0.0954031 26050 158493 -1 1746 19 1244 2022 141843 33916 3.28147 3.28147 -107.564 -3.28147 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0160826 0.0144954 73 57 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_112.v common 3.73 vpr 64.76 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29768 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 396 325 1 176 83 17 17 289 -1 unnamed_device 25.6 MiB 0.93 2367 760 13403 5641 7157 605 64.8 MiB 0.07 0.00 4.16215 3.42825 -117.829 -3.42825 3.42825 0.24 0.000472934 0.000415205 0.0310469 0.0284745 -1 -1 -1 -1 40 2441 42 6.95648e+06 289514 706193. 2443.58 1.28 0.128029 0.113433 26914 176310 -1 1940 25 1789 2570 188127 47601 3.62427 3.62427 -132.869 -3.62427 0 0 926341. 3205.33 0.03 0.06 0.12 -1 -1 0.03 0.0248133 0.0219353 79 91 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_113.v common 2.56 vpr 64.76 MiB -1 -1 0.12 18056 1 0.04 -1 -1 30116 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 303 262 1 145 75 17 17 289 -1 unnamed_device 25.6 MiB 0.21 1778 712 10977 4578 6228 171 64.8 MiB 0.05 0.00 3.29253 2.84005 -99.7836 -2.84005 2.84005 0.25 0.00042795 0.000388641 0.0239453 0.021948 -1 -1 -1 -1 36 2050 34 6.95648e+06 159232 648988. 2245.63 0.79 0.0853346 0.0750854 26050 158493 -1 1762 20 1194 1822 154899 35238 3.11192 3.11192 -113.612 -3.11192 0 0 828058. 2865.25 0.05 0.07 0.15 -1 -1 0.05 0.0238669 0.0213025 58 57 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_114.v common 3.40 vpr 64.19 MiB -1 -1 0.13 18296 1 0.03 -1 -1 29756 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 32 32 290 244 1 172 78 17 17 289 -1 unnamed_device 25.2 MiB 0.73 1995 861 8378 1972 6153 253 64.2 MiB 0.04 0.00 3.97583 3.49463 -115.332 -3.49463 3.49463 0.26 0.000286549 0.000262684 0.0160968 0.0147723 -1 -1 -1 -1 40 2267 25 6.95648e+06 202660 706193. 2443.58 1.28 0.0945591 0.0830124 26914 176310 -1 1967 21 1553 2292 189903 41785 3.35347 3.35347 -120.801 -3.35347 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0147377 0.0131938 68 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_115.v common 4.63 vpr 64.66 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29772 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 32 32 318 257 1 190 81 17 17 289 -1 unnamed_device 25.6 MiB 0.63 1985 868 6206 1328 4710 168 64.7 MiB 0.03 0.00 4.72618 4.25388 -127.376 -4.25388 4.25388 0.24 0.000319888 0.000293074 0.0132111 0.0121845 -1 -1 -1 -1 36 2808 32 6.95648e+06 246087 648988. 2245.63 2.57 0.158635 0.139331 26050 158493 -1 2074 22 1723 2285 180456 42709 4.25992 4.25992 -139.303 -4.25992 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0165456 0.0148185 76 30 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_116.v common 4.11 vpr 64.66 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29780 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 29 32 324 268 1 162 86 17 17 289 -1 unnamed_device 25.0 MiB 0.51 1715 960 12371 3218 7643 1510 64.7 MiB 0.06 0.00 4.12939 3.75349 -109.494 -3.75349 3.75349 0.25 0.000312325 0.000285891 0.0222995 0.0204763 -1 -1 -1 -1 36 2399 29 6.95648e+06 361892 648988. 2245.63 2.08 0.162881 0.143154 26050 158493 -1 2124 24 1309 2223 188987 40183 3.40282 3.40282 -112.56 -3.40282 0 0 828058. 2865.25 0.03 0.05 0.10 -1 -1 0.03 0.0178762 0.0159922 73 55 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_117.v common 10.74 vpr 64.86 MiB -1 -1 0.12 18296 1 0.03 -1 -1 29960 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 32 32 393 312 1 205 80 17 17 289 -1 unnamed_device 25.6 MiB 0.82 2498 877 13324 5609 7307 408 64.9 MiB 0.07 0.00 5.49221 4.58061 -145.903 -4.58061 4.58061 0.25 0.000374154 0.000342411 0.0337134 0.0310037 -1 -1 -1 -1 42 3205 39 6.95648e+06 231611 744469. 2576.02 8.24 0.240569 0.211499 27202 183097 -1 2393 26 2399 3408 288616 65006 4.30292 4.30292 -159.239 -4.30292 0 0 949917. 3286.91 0.05 0.10 0.14 -1 -1 0.05 0.0309125 0.0275603 86 65 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_118.v common 2.34 vpr 64.54 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29936 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 31 32 229 197 1 137 77 17 17 289 -1 unnamed_device 24.9 MiB 0.37 1573 789 7738 2349 3877 1512 64.5 MiB 0.03 0.00 3.62318 3.27643 -101.711 -3.27643 3.27643 0.24 0.000248976 0.000227423 0.0132757 0.0121928 -1 -1 -1 -1 34 1944 27 6.95648e+06 202660 618332. 2139.56 0.69 0.0826342 0.0725114 25762 151098 -1 1657 22 990 1577 151209 32013 3.17312 3.17312 -112.749 -3.17312 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0133466 0.0118792 54 4 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_119.v common 6.20 vpr 65.46 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29756 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67036 32 32 412 334 1 182 92 17 17 289 -1 unnamed_device 25.5 MiB 0.34 2584 779 15410 4873 7828 2709 65.5 MiB 0.07 0.00 4.99926 3.90964 -132.617 -3.90964 3.90964 0.35 0.000367291 0.000335681 0.0295207 0.0270144 -1 -1 -1 -1 54 2048 24 6.95648e+06 405319 949917. 3286.91 4.30 0.220353 0.193683 29506 232905 -1 1646 23 1577 2111 155055 38389 4.14962 4.14962 -142.145 -4.14962 0 0 1.17392e+06 4061.99 0.04 0.06 0.14 -1 -1 0.04 0.0246995 0.0221709 84 90 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_120.v common 4.94 vpr 64.66 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30212 -1 -1 11 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66208 32 32 376 318 1 154 75 17 17 289 -1 unnamed_device 25.6 MiB 1.68 1894 675 12083 5157 6591 335 64.7 MiB 0.06 0.00 3.54619 2.94085 -113.533 -2.94085 2.94085 0.25 0.000336191 0.000306852 0.0277439 0.0254059 -1 -1 -1 -1 48 1588 22 6.95648e+06 159232 865456. 2994.66 1.84 0.165957 0.145157 28354 207349 -1 1301 20 1327 1806 124593 28920 3.01532 3.01532 -115.899 -3.01532 0 0 1.05005e+06 3633.38 0.04 0.04 0.11 -1 -1 0.04 0.0165622 0.0148394 62 96 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_121.v common 3.44 vpr 64.68 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30156 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 360 293 1 172 90 17 17 289 -1 unnamed_device 25.3 MiB 0.48 1853 1069 14562 4604 8437 1521 64.7 MiB 0.07 0.00 3.91173 3.53583 -120.704 -3.53583 3.53583 0.25 0.000335501 0.000306033 0.0322582 0.0297118 -1 -1 -1 -1 40 2375 24 6.95648e+06 376368 706193. 2443.58 1.49 0.158921 0.139899 26914 176310 -1 2117 23 1326 2047 179309 38171 3.29717 3.29717 -119.13 -3.29717 0 0 926341. 3205.33 0.05 0.08 0.11 -1 -1 0.05 0.0312325 0.0278867 78 60 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_122.v common 3.18 vpr 65.48 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30192 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67056 32 32 396 299 1 227 83 17 17 289 -1 unnamed_device 25.6 MiB 0.86 2452 1278 10883 3044 6597 1242 65.5 MiB 0.07 0.00 6.40588 5.67799 -169.514 -5.67799 5.67799 0.26 0.000375871 0.000344229 0.0265442 0.0244031 -1 -1 -1 -1 42 3157 23 6.95648e+06 275038 744469. 2576.02 0.83 0.0987754 0.0878873 27202 183097 -1 2714 35 2694 3788 394527 125732 4.9392 4.9392 -169.567 -4.9392 0 0 949917. 3286.91 0.03 0.11 0.10 -1 -1 0.03 0.028617 0.0255556 95 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_123.v common 4.02 vpr 64.68 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29564 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 30 32 224 207 1 132 75 17 17 289 -1 unnamed_device 25.6 MiB 0.54 1627 598 12241 5372 6458 411 64.7 MiB 0.05 0.00 2.90706 2.40586 -87.9482 -2.40586 2.40586 0.25 0.000233649 0.000212956 0.0201236 0.0184129 -1 -1 -1 -1 40 1508 30 6.95648e+06 188184 706193. 2443.58 2.06 0.157661 0.137737 26914 176310 -1 1331 20 901 1144 111930 30811 2.88623 2.88623 -98.6954 -2.88623 0 0 926341. 3205.33 0.03 0.04 0.11 -1 -1 0.03 0.0123386 0.0110566 51 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_124.v common 4.72 vpr 64.19 MiB -1 -1 0.19 17676 1 0.03 -1 -1 30184 -1 -1 12 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 30 32 286 239 1 137 74 17 17 289 -1 unnamed_device 25.1 MiB 0.91 1634 584 10304 2805 7001 498 64.2 MiB 0.04 0.00 3.45258 3.27614 -105.411 -3.27614 3.27614 0.25 0.000284959 0.000261096 0.0205025 0.0187956 -1 -1 -1 -1 34 1944 38 6.95648e+06 173708 618332. 2139.56 2.32 0.143174 0.124606 25762 151098 -1 1413 22 1179 1705 141397 34783 3.09482 3.09482 -117.715 -3.09482 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0150785 0.0134656 56 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 3.29 vpr 65.05 MiB -1 -1 0.11 18064 1 0.02 -1 -1 29768 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 296 247 1 152 83 17 17 289 -1 unnamed_device 25.2 MiB 0.11 1728 922 8723 2565 5365 793 65.1 MiB 0.04 0.00 3.55445 2.9873 -113.256 -2.9873 2.9873 0.25 0.000301223 0.00027349 0.0160763 0.0147241 -1 -1 -1 -1 40 2197 27 6.95648e+06 275038 706193. 2443.58 1.75 0.156743 0.136892 26914 176310 -1 2042 23 1349 2303 218886 48209 3.19827 3.19827 -121.7 -3.19827 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0160692 0.0143372 65 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_126.v common 2.84 vpr 64.26 MiB -1 -1 0.12 18060 1 0.02 -1 -1 29828 -1 -1 18 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 25 32 216 194 1 119 75 17 17 289 -1 unnamed_device 25.2 MiB 0.09 1353 690 8449 3120 3872 1457 64.3 MiB 0.03 0.00 3.58218 3.24133 -80.823 -3.24133 3.24133 0.25 0.000224742 0.000205297 0.0131913 0.0120881 -1 -1 -1 -1 32 1648 24 6.95648e+06 260562 586450. 2029.24 1.34 0.123269 0.106366 25474 144626 -1 1400 20 849 1332 99865 22135 2.72602 2.72602 -85.395 -2.72602 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0111245 0.00989695 51 29 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_127.v common 6.84 vpr 64.71 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29796 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66268 32 32 376 307 1 179 78 17 17 289 -1 unnamed_device 26.0 MiB 0.46 1982 1168 8876 2502 5267 1107 64.7 MiB 0.05 0.00 4.59945 3.81054 -129.805 -3.81054 3.81054 0.25 0.000344787 0.000315324 0.0205257 0.0187772 -1 -1 -1 -1 40 2820 23 6.95648e+06 202660 706193. 2443.58 4.95 0.191278 0.167763 26914 176310 -1 2463 25 1559 2688 247418 60274 4.07062 4.07062 -139.096 -4.07062 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0204429 0.0182595 75 72 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_128.v common 3.87 vpr 65.58 MiB -1 -1 0.20 18440 1 0.03 -1 -1 29772 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67156 31 32 409 331 1 183 92 17 17 289 -1 unnamed_device 25.6 MiB 0.39 1880 934 14582 5336 7343 1903 65.6 MiB 0.07 0.00 3.75413 3.54189 -123.861 -3.54189 3.54189 0.25 0.000370518 0.000338041 0.0281666 0.0258067 -1 -1 -1 -1 40 2135 23 6.95648e+06 419795 706193. 2443.58 1.67 0.181804 0.159938 26914 176310 -1 1941 23 1958 2686 194478 42954 3.22012 3.22012 -126.025 -3.22012 0 0 926341. 3205.33 0.05 0.09 0.17 -1 -1 0.05 0.0361223 0.0324491 88 90 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_001.v common 3.61 vpr 65.28 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30180 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66844 32 32 354 285 1 206 82 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2477 1104 5956 1234 4454 268 65.3 MiB 0.04 0.00 5.9831 5.0213 -150.404 -5.0213 5.0213 0.25 0.000339429 0.000311214 0.0135732 0.0124946 -1 -1 -1 -1 40 2746 30 6.99608e+06 264882 706193. 2443.58 1.64 0.140449 0.122546 26914 176310 -1 2503 21 1812 2826 219665 47612 4.45375 4.45375 -154.395 -4.45375 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0178176 0.0160479 89 50 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_002.v common 7.00 vpr 64.60 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29756 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 30 32 363 293 1 224 85 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2539 1213 13663 4903 6549 2211 64.6 MiB 0.08 0.00 5.97457 4.74455 -148.167 -4.74455 4.74455 0.25 0.000819983 0.00075946 0.0339081 0.0313222 -1 -1 -1 -1 38 2904 29 6.99608e+06 338461 678818. 2348.85 5.25 0.188274 0.165386 26626 170182 -1 2475 23 2204 3166 262316 53855 4.3292 4.3292 -149.244 -4.3292 0 0 902133. 3121.57 0.03 0.07 0.10 -1 -1 0.03 0.0216333 0.0194628 99 63 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_003.v common 6.20 vpr 64.43 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29800 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 299 247 1 182 82 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2357 1078 12186 3608 6974 1604 64.4 MiB 0.07 0.00 4.53839 3.58799 -116.676 -3.58799 3.58799 0.25 0.000295115 0.00027033 0.0302567 0.0279761 -1 -1 -1 -1 36 2482 30 6.99608e+06 264882 648988. 2245.63 4.46 0.190584 0.167465 26050 158493 -1 2238 23 1374 1912 157043 33421 4.08876 4.08876 -130.004 -4.08876 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0161449 0.0144234 75 29 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_004.v common 2.49 vpr 63.83 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29748 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65364 29 32 308 248 1 182 80 17 17 289 -1 unnamed_device 24.9 MiB 0.33 2573 764 13496 3536 9305 655 63.8 MiB 0.09 0.00 5.42531 4.05748 -115.939 -4.05748 4.05748 0.24 0.000828626 0.000781172 0.0376447 0.0347493 -1 -1 -1 -1 36 2604 27 6.99608e+06 279598 648988. 2245.63 0.77 0.0932788 0.0829728 26050 158493 -1 1796 20 1431 2220 152925 38511 3.99626 3.99626 -126.688 -3.99626 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.015111 0.0135488 79 31 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_005.v common 3.59 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29848 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66296 32 32 336 268 1 193 80 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2057 952 12464 3721 7118 1625 64.7 MiB 0.06 0.00 5.56057 4.88167 -146.243 -4.88167 4.88167 0.25 0.000331052 0.00030369 0.0256676 0.0235046 -1 -1 -1 -1 44 2790 26 6.99608e+06 235451 787024. 2723.27 1.89 0.151492 0.133144 27778 195446 -1 2240 23 1634 2747 222001 48807 4.40571 4.40571 -143.589 -4.40571 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0197017 0.0177011 86 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_006.v common 2.89 vpr 65.35 MiB -1 -1 0.12 18440 1 0.03 -1 -1 29780 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66916 32 32 366 295 1 222 88 17 17 289 -1 unnamed_device 25.6 MiB 0.24 2506 1118 13933 5613 7680 640 65.3 MiB 0.07 0.00 4.26916 3.42564 -123.507 -3.42564 3.42564 0.25 0.000345196 0.00031104 0.0287072 0.0263298 -1 -1 -1 -1 38 3421 45 6.99608e+06 353176 678818. 2348.85 1.26 0.112321 0.0993323 26626 170182 -1 2462 24 1784 3007 215704 50106 3.76796 3.76796 -132.934 -3.76796 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0195075 0.0174687 99 58 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_007.v common 2.41 vpr 64.68 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30136 -1 -1 18 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 27 32 259 221 1 152 77 17 17 289 -1 unnamed_device 25.2 MiB 0.25 1709 563 9857 3638 4045 2174 64.7 MiB 0.05 0.00 4.67622 3.83492 -100.928 -3.83492 3.83492 0.26 0.000310689 0.000287664 0.022248 0.0206329 -1 -1 -1 -1 38 1948 27 6.99608e+06 264882 678818. 2348.85 0.78 0.0780478 0.0687188 26626 170182 -1 1392 30 1579 2262 176346 42562 3.41652 3.41652 -110.525 -3.41652 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0218746 0.0192852 65 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_008.v common 2.40 vpr 64.66 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29804 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66216 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 24.9 MiB 0.11 1776 919 11547 2651 7976 920 64.7 MiB 0.05 0.00 3.1255 2.7565 -95.0074 -2.7565 2.7565 0.26 0.000293209 0.000264748 0.0180705 0.0165422 -1 -1 -1 -1 36 2309 50 6.99608e+06 397324 648988. 2245.63 0.94 0.103789 0.0914604 26050 158493 -1 1978 22 1218 2212 171223 38751 2.65381 2.65381 -102.167 -2.65381 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0148703 0.0132452 69 4 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_009.v common 3.28 vpr 65.09 MiB -1 -1 0.15 18064 1 0.03 -1 -1 29792 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66652 31 32 317 271 1 204 81 17 17 289 -1 unnamed_device 25.3 MiB 0.23 2338 1082 14256 5263 7162 1831 65.1 MiB 0.07 0.00 4.24759 3.13884 -116.913 -3.13884 3.13884 0.29 0.000304151 0.000278446 0.0274291 0.0251884 -1 -1 -1 -1 40 2502 31 6.99608e+06 264882 706193. 2443.58 1.59 0.13523 0.118366 26914 176310 -1 2233 22 1689 2280 192202 40085 3.05882 3.05882 -122.616 -3.05882 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0162855 0.014578 83 64 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_010.v common 4.75 vpr 64.41 MiB -1 -1 0.14 17676 1 0.03 -1 -1 29648 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 32 32 298 248 1 181 79 17 17 289 -1 unnamed_device 25.3 MiB 0.24 1862 1015 12247 3678 6923 1646 64.4 MiB 0.07 0.00 3.99837 3.64037 -128.737 -3.64037 3.64037 0.25 0.000447112 0.000420921 0.0321216 0.0299558 -1 -1 -1 -1 34 2533 32 6.99608e+06 220735 618332. 2139.56 3.11 0.172253 0.152194 25762 151098 -1 2146 19 1516 1997 164767 35720 3.09382 3.09382 -128.206 -3.09382 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0141017 0.0126303 72 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_011.v common 3.34 vpr 64.45 MiB -1 -1 0.16 18060 1 0.03 -1 -1 29772 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 30 32 303 262 1 186 79 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2266 960 13599 4745 6819 2035 64.4 MiB 0.09 0.00 4.98263 3.86818 -125.247 -3.86818 3.86818 0.28 0.000424381 0.00038739 0.0373622 0.0341447 -1 -1 -1 -1 36 2348 40 6.99608e+06 250167 648988. 2245.63 1.51 0.148585 0.130262 26050 158493 -1 2064 21 1422 1950 168607 36652 3.59731 3.59731 -129.651 -3.59731 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0172651 0.0154663 79 63 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_012.v common 2.79 vpr 64.71 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29692 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 32 32 276 237 1 165 78 17 17 289 -1 unnamed_device 24.9 MiB 0.24 1950 725 8212 1860 5677 675 64.7 MiB 0.05 0.00 4.10243 3.37048 -107.801 -3.37048 3.37048 0.25 0.000669283 0.000624933 0.0224593 0.0208535 -1 -1 -1 -1 38 2443 48 6.99608e+06 206020 678818. 2348.85 1.17 0.109588 0.0965962 26626 170182 -1 1781 21 1241 1639 121264 31618 3.06712 3.06712 -115.463 -3.06712 0 0 902133. 3121.57 0.03 0.04 0.10 -1 -1 0.03 0.0151789 0.0135417 65 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 3.29 vpr 64.48 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29624 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 344 272 1 201 82 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2682 954 13076 5089 6303 1684 64.5 MiB 0.07 0.00 4.83632 3.86972 -128.357 -3.86972 3.86972 0.25 0.000326098 0.000297786 0.0290014 0.0266927 -1 -1 -1 -1 42 2795 25 6.99608e+06 264882 744469. 2576.02 1.57 0.143204 0.125742 27202 183097 -1 2199 24 1772 2664 231395 52184 3.34801 3.34801 -126.15 -3.34801 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0187747 0.0168077 85 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_014.v common 3.13 vpr 65.34 MiB -1 -1 0.20 18060 1 0.03 -1 -1 29688 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66908 32 32 363 295 1 228 85 17 17 289 -1 unnamed_device 25.2 MiB 0.32 2692 1244 14407 4661 7812 1934 65.3 MiB 0.08 0.00 5.90964 4.79277 -149.984 -4.79277 4.79277 0.27 0.000337196 0.000308944 0.0320247 0.0294721 -1 -1 -1 -1 40 2811 20 6.99608e+06 309029 706193. 2443.58 1.17 0.123832 0.110017 26914 176310 -1 2538 20 1946 2619 212273 44432 4.38451 4.38451 -153.65 -4.38451 0 0 926341. 3205.33 0.04 0.05 0.14 -1 -1 0.04 0.017113 0.0153806 96 61 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_015.v common 2.96 vpr 64.60 MiB -1 -1 0.11 18296 1 0.03 -1 -1 30276 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 29 32 248 215 1 150 78 17 17 289 -1 unnamed_device 24.9 MiB 0.31 1740 893 9706 2711 5534 1461 64.6 MiB 0.05 0.00 3.47743 2.91415 -94.4077 -2.91415 2.91415 0.25 0.000254157 0.000232628 0.020588 0.018958 -1 -1 -1 -1 32 2036 22 6.99608e+06 250167 586450. 2029.24 1.29 0.106588 0.0929905 25474 144626 -1 1646 20 1019 1427 101641 22220 2.71507 2.71507 -98.7671 -2.71507 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0128596 0.0114275 62 27 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_016.v common 2.63 vpr 65.34 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66912 32 32 370 297 1 219 83 17 17 289 -1 unnamed_device 25.7 MiB 0.35 2362 1073 15563 6532 7835 1196 65.3 MiB 0.08 0.00 4.16944 3.57294 -125.244 -3.57294 3.57294 0.24 0.000347667 0.000317742 0.0318598 0.0291397 -1 -1 -1 -1 38 2963 48 6.99608e+06 279598 678818. 2348.85 0.89 0.110101 0.0973561 26626 170182 -1 2204 21 1887 2913 199419 44516 3.57851 3.57851 -131.037 -3.57851 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0176817 0.0158624 98 58 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_017.v common 3.04 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29840 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 338 269 1 198 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2635 1084 14431 4177 8907 1347 64.5 MiB 0.08 0.00 4.64181 3.75386 -123.111 -3.75386 3.75386 0.25 0.000409682 0.000377196 0.036391 0.033598 -1 -1 -1 -1 36 2769 26 6.99608e+06 250167 648988. 2245.63 1.27 0.155204 0.138893 26050 158493 -1 2414 20 1701 2429 219821 56511 3.11862 3.11862 -126.555 -3.11862 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0208099 0.0188496 83 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_018.v common 3.89 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29584 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66612 32 32 323 276 1 210 81 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2734 1198 13031 4384 6941 1706 65.1 MiB 0.06 0.00 4.46501 3.1116 -120.136 -3.1116 3.1116 0.27 0.000301401 0.000276115 0.0248043 0.0226518 -1 -1 -1 -1 34 2850 47 6.99608e+06 250167 618332. 2139.56 2.24 0.158245 0.138253 25762 151098 -1 2471 21 1733 2316 195072 42876 3.22062 3.22062 -126.364 -3.22062 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0162061 0.0145209 84 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_019.v common 2.76 vpr 64.13 MiB -1 -1 0.13 18060 1 0.02 -1 -1 29784 -1 -1 14 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 30 32 222 206 1 135 76 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1543 727 10476 3465 5449 1562 64.1 MiB 0.04 0.00 2.68936 2.31346 -87.3083 -2.31346 2.31346 0.25 0.000244077 0.000223557 0.0172966 0.0158483 -1 -1 -1 -1 32 1548 26 6.99608e+06 206020 586450. 2029.24 1.21 0.103854 0.089959 25474 144626 -1 1415 22 733 828 76674 17191 2.18948 2.18948 -92.4069 -2.18948 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0121979 0.0108198 52 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_020.v common 3.85 vpr 63.91 MiB -1 -1 0.12 17712 1 0.03 -1 -1 29792 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65448 31 32 291 243 1 172 78 17 17 289 -1 unnamed_device 24.5 MiB 0.72 2133 838 8046 1881 5711 454 63.9 MiB 0.04 0.00 5.43629 4.06642 -132.88 -4.06642 4.06642 0.35 0.000286595 0.000262175 0.0155859 0.0143043 -1 -1 -1 -1 34 2585 50 6.99608e+06 220735 618332. 2139.56 1.53 0.13142 0.114418 25762 151098 -1 1987 22 1400 2056 153586 36992 3.64846 3.64846 -134.265 -3.64846 0 0 787024. 2723.27 0.04 0.07 0.13 -1 -1 0.04 0.0259421 0.0231603 70 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_021.v common 3.79 vpr 64.61 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30348 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 342 271 1 200 92 17 17 289 -1 unnamed_device 25.2 MiB 0.31 2545 898 17687 6355 8833 2499 64.6 MiB 0.08 0.00 5.23013 4.09659 -137.139 -4.09659 4.09659 0.24 0.000327188 0.000299437 0.0312595 0.0286912 -1 -1 -1 -1 38 2615 31 6.99608e+06 412039 678818. 2348.85 2.03 0.169548 0.152529 26626 170182 -1 1982 23 1854 2804 201893 47345 4.6472 4.6472 -149.149 -4.6472 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0179156 0.0160457 92 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_022.v common 3.69 vpr 64.76 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30104 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 372 300 1 225 84 17 17 289 -1 unnamed_device 25.2 MiB 0.37 2481 1280 13260 3957 7480 1823 64.8 MiB 0.08 0.00 5.12435 4.27615 -135.126 -4.27615 4.27615 0.26 0.000351019 0.000321597 0.0324092 0.0299401 -1 -1 -1 -1 44 3006 22 6.99608e+06 294314 787024. 2723.27 1.86 0.161059 0.14195 27778 195446 -1 2489 20 1768 2665 213136 44814 4.30622 4.30622 -143.652 -4.30622 0 0 997811. 3452.63 0.04 0.05 0.10 -1 -1 0.04 0.0175618 0.0158387 97 62 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_023.v common 2.37 vpr 64.02 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30140 -1 -1 17 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65556 26 32 190 182 1 123 75 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1496 591 9871 3440 4773 1658 64.0 MiB 0.03 0.00 3.5328 2.5304 -72.9745 -2.5304 2.5304 0.27 0.000201051 0.000183539 0.0137083 0.0125318 -1 -1 -1 -1 30 1434 20 6.99608e+06 250167 556674. 1926.21 0.88 0.0661549 0.0573686 25186 138497 -1 1178 19 742 883 70756 15921 2.30998 2.30998 -75.3621 -2.30998 0 0 706193. 2443.58 0.03 0.03 0.08 -1 -1 0.03 0.0122099 0.0107687 51 30 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_024.v common 6.67 vpr 64.61 MiB -1 -1 0.21 17672 1 0.03 -1 -1 30252 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66156 32 32 285 227 1 160 81 17 17 289 -1 unnamed_device 25.2 MiB 0.35 1881 1025 10231 3161 5849 1221 64.6 MiB 0.07 0.00 5.10855 4.37465 -123.584 -4.37465 4.37465 0.46 0.000291795 0.000266598 0.0320495 0.0296815 -1 -1 -1 -1 34 2652 24 6.99608e+06 250167 618332. 2139.56 4.51 0.160997 0.141917 25762 151098 -1 2217 22 1494 2515 241172 49180 3.78976 3.78976 -130.242 -3.78976 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0154296 0.0137911 66 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_025.v common 1.95 vpr 64.21 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29736 -1 -1 10 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65752 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 24.9 MiB 0.06 1439 560 9374 3843 5323 208 64.2 MiB 0.07 0.00 2.54695 2.03911 -69.5392 -2.03911 2.03911 0.28 0.000517782 0.00047721 0.0311304 0.0286357 -1 -1 -1 -1 32 1253 27 6.99608e+06 147157 586450. 2029.24 0.57 0.0745683 0.0659302 25474 144626 -1 1084 17 554 676 57342 13979 1.94502 1.94502 -76.2104 -1.94502 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00875001 0.00782223 43 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_026.v common 3.04 vpr 64.42 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30180 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 32 32 300 245 1 176 79 17 17 289 -1 unnamed_device 24.9 MiB 0.75 2120 991 10050 3166 5397 1487 64.4 MiB 0.05 0.00 5.61451 4.50471 -128.436 -4.50471 4.50471 0.24 0.000301009 0.000274742 0.0212028 0.0195085 -1 -1 -1 -1 34 2653 41 6.99608e+06 220735 618332. 2139.56 0.94 0.100568 0.0883959 25762 151098 -1 2097 19 1258 1913 140387 31529 3.94702 3.94702 -130.561 -3.94702 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143834 0.0129277 73 24 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_027.v common 3.06 vpr 64.92 MiB -1 -1 0.10 17672 1 0.03 -1 -1 29956 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 25.2 MiB 0.10 1823 770 8047 1794 5817 436 64.9 MiB 0.04 0.00 3.17834 2.84195 -96.8757 -2.84195 2.84195 0.25 0.000307522 0.000280239 0.0139893 0.0127846 -1 -1 -1 -1 38 2286 24 6.99608e+06 397324 678818. 2348.85 1.45 0.120098 0.104798 26626 170182 -1 1846 20 1304 2290 140400 35421 2.96851 2.96851 -105.541 -2.96851 0 0 902133. 3121.57 0.05 0.07 0.16 -1 -1 0.05 0.0249902 0.0224145 77 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_028.v common 7.89 vpr 65.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29768 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 338 277 1 204 84 17 17 289 -1 unnamed_device 25.2 MiB 0.46 2724 1022 8136 1841 6065 230 65.1 MiB 0.05 0.00 5.37647 4.14137 -127.473 -4.14137 4.14137 0.36 0.000375091 0.000347255 0.0168054 0.0153915 -1 -1 -1 -1 38 3057 31 6.99608e+06 294314 678818. 2348.85 5.89 0.19333 0.169565 26626 170182 -1 2256 20 1754 2596 181852 41367 3.87782 3.87782 -133.503 -3.87782 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0166011 0.0149371 88 50 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_029.v common 2.51 vpr 64.73 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29804 -1 -1 14 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 32 32 284 241 1 168 78 17 17 289 -1 unnamed_device 24.9 MiB 0.51 1906 924 9872 3709 5164 999 64.7 MiB 0.05 0.00 3.74453 3.11176 -114.352 -3.11176 3.11176 0.25 0.000287639 0.000263831 0.0210304 0.0193592 -1 -1 -1 -1 34 2359 22 6.99608e+06 206020 618332. 2139.56 0.67 0.0852771 0.0749924 25762 151098 -1 2040 23 1396 2031 159719 34924 3.14212 3.14212 -122.708 -3.14212 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0155618 0.0138549 68 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_030.v common 3.33 vpr 63.88 MiB -1 -1 0.18 17676 1 0.02 -1 -1 29840 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65416 30 32 262 227 1 160 78 17 17 289 -1 unnamed_device 24.9 MiB 0.18 1816 788 8212 1940 5916 356 63.9 MiB 0.04 0.00 4.36766 3.76823 -111.393 -3.76823 3.76823 0.24 0.000268796 0.000246457 0.014825 0.0136157 -1 -1 -1 -1 36 2251 27 6.99608e+06 235451 648988. 2245.63 1.49 0.114612 0.0991656 26050 158493 -1 1776 64 1632 2908 490429 252067 3.39226 3.39226 -111.31 -3.39226 0 0 828058. 2865.25 0.03 0.20 0.15 -1 -1 0.03 0.0388827 0.0341788 65 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_031.v common 2.37 vpr 64.65 MiB -1 -1 0.12 17472 1 0.02 -1 -1 29824 -1 -1 17 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 28 32 260 223 1 152 77 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1683 804 11650 4924 6170 556 64.7 MiB 0.05 0.00 4.26016 3.78259 -116.363 -3.78259 3.78259 0.25 0.000265538 0.000243257 0.0203419 0.0186211 -1 -1 -1 -1 40 1766 19 6.99608e+06 250167 706193. 2443.58 0.64 0.0678464 0.0597412 26914 176310 -1 1619 17 889 1497 109998 24855 3.37506 3.37506 -112.039 -3.37506 0 0 926341. 3205.33 0.05 0.05 0.17 -1 -1 0.05 0.0182635 0.0163129 69 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_032.v common 2.30 vpr 64.55 MiB -1 -1 0.13 17680 1 0.03 -1 -1 29808 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 24.9 MiB 0.10 1562 788 6108 1413 4387 308 64.5 MiB 0.03 0.00 3.55103 3.30043 -111.23 -3.30043 3.30043 0.25 0.00031688 0.00027615 0.0131315 0.0120434 -1 -1 -1 -1 36 2159 28 6.99608e+06 191304 648988. 2245.63 0.80 0.0795214 0.0697774 26050 158493 -1 1866 20 1176 1858 150356 33149 3.08997 3.08997 -117.255 -3.08997 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0133256 0.0119122 59 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_033.v common 2.91 vpr 64.66 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30288 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 31 32 271 231 1 164 78 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1729 914 6552 1539 4793 220 64.7 MiB 0.03 0.00 3.64733 3.26948 -110.36 -3.26948 3.26948 0.24 0.000274842 0.000251498 0.0124484 0.0114395 -1 -1 -1 -1 38 2086 22 6.99608e+06 220735 678818. 2348.85 1.41 0.113843 0.0989225 26626 170182 -1 1766 19 1123 1539 113480 24974 2.95762 2.95762 -107.253 -2.95762 0 0 902133. 3121.57 0.03 0.03 0.09 -1 -1 0.03 0.0130744 0.0117173 65 30 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_034.v common 3.02 vpr 65.02 MiB -1 -1 0.23 18060 1 0.03 -1 -1 30260 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 29 32 291 250 1 177 79 17 17 289 -1 unnamed_device 25.1 MiB 0.30 1970 870 12923 5432 7041 450 65.0 MiB 0.06 0.00 3.19185 3.0305 -101.634 -3.0305 3.0305 0.25 0.0002811 0.000256228 0.026476 0.024338 -1 -1 -1 -1 34 2394 43 6.99608e+06 264882 618332. 2139.56 1.28 0.123062 0.107742 25762 151098 -1 1866 20 1335 1783 151180 34619 2.90282 2.90282 -102.948 -2.90282 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0142251 0.0127067 75 54 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_035.v common 5.13 vpr 65.27 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30252 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66840 32 32 367 282 1 214 85 17 17 289 -1 unnamed_device 25.2 MiB 0.22 2522 1172 14035 4232 7971 1832 65.3 MiB 0.17 0.00 4.99868 4.08568 -124.995 -4.08568 4.08568 0.27 0.000960124 0.000884277 0.076292 0.0708771 -1 -1 -1 -1 36 3145 22 6.99608e+06 309029 648988. 2245.63 3.32 0.224409 0.200545 26050 158493 -1 2479 23 1718 2753 202121 45212 3.89121 3.89121 -131.794 -3.89121 0 0 828058. 2865.25 0.03 0.06 0.14 -1 -1 0.03 0.020053 0.0180574 91 29 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_036.v common 2.64 vpr 65.45 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30308 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67016 32 32 391 311 1 244 85 17 17 289 -1 unnamed_device 25.6 MiB 0.27 3114 1259 14779 4738 7682 2359 65.4 MiB 0.18 0.00 5.22142 3.95648 -143.346 -3.95648 3.95648 0.25 0.000988432 0.000921433 0.0827453 0.0770468 -1 -1 -1 -1 38 3454 34 6.99608e+06 309029 678818. 2348.85 0.82 0.15522 0.140296 26626 170182 -1 2633 24 2431 3409 267181 56072 3.57966 3.57966 -146.352 -3.57966 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0199938 0.017896 103 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_037.v common 3.43 vpr 64.29 MiB -1 -1 0.12 18444 1 0.02 -1 -1 29780 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 31 32 279 237 1 161 77 17 17 289 -1 unnamed_device 24.9 MiB 0.30 1951 789 11976 3042 8492 442 64.3 MiB 0.06 0.00 4.50867 3.52417 -108.752 -3.52417 3.52417 0.26 0.000669405 0.0006251 0.0285923 0.0264143 -1 -1 -1 -1 36 2241 46 6.99608e+06 206020 648988. 2245.63 1.65 0.131689 0.116324 26050 158493 -1 1842 19 1371 2033 165078 39629 3.27322 3.27322 -114.522 -3.27322 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0134904 0.0120612 67 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_038.v common 2.81 vpr 65.36 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29968 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66932 31 32 370 297 1 227 85 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2471 1139 11059 3848 5463 1748 65.4 MiB 0.06 0.00 3.93715 3.60485 -125.992 -3.60485 3.60485 0.24 0.000340222 0.000310302 0.0228227 0.0209047 -1 -1 -1 -1 38 3226 39 6.99608e+06 323745 678818. 2348.85 1.11 0.101109 0.0890899 26626 170182 -1 2488 20 1747 2530 216446 46223 3.50736 3.50736 -133.253 -3.50736 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0172056 0.0154889 98 61 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_039.v common 7.93 vpr 65.27 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30176 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66836 31 32 377 302 1 235 85 17 17 289 -1 unnamed_device 25.6 MiB 0.26 3086 1318 10687 2982 7130 575 65.3 MiB 0.06 0.00 6.44118 5.00244 -160.349 -5.00244 5.00244 0.25 0.000364276 0.000335521 0.022151 0.0203222 -1 -1 -1 -1 38 3194 28 6.99608e+06 323745 678818. 2348.85 6.29 0.176922 0.15499 26626 170182 -1 2740 19 2162 3082 228411 49616 4.82274 4.82274 -169.003 -4.82274 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0170405 0.0153752 101 64 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_040.v common 3.46 vpr 65.41 MiB -1 -1 0.13 18048 1 0.03 -1 -1 29768 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66980 31 32 383 305 1 232 84 17 17 289 -1 unnamed_device 25.6 MiB 0.68 2998 1211 13809 5832 7618 359 65.4 MiB 0.09 0.00 6.73307 4.94768 -163.914 -4.94768 4.94768 0.26 0.000351527 0.000321331 0.040439 0.0373557 -1 -1 -1 -1 38 3344 24 6.99608e+06 309029 678818. 2348.85 1.31 0.133483 0.119387 26626 170182 -1 2611 24 2258 3370 271018 68504 4.84 4.84 -173.04 -4.84 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.0207315 0.0186332 101 64 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_041.v common 2.96 vpr 64.58 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29740 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66132 31 32 352 285 1 214 82 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2321 1209 11118 3541 5840 1737 64.6 MiB 0.06 0.00 4.10443 3.47793 -120.035 -3.47793 3.47793 0.25 0.000339383 0.000311035 0.0228619 0.0209898 -1 -1 -1 -1 38 3104 43 6.99608e+06 279598 678818. 2348.85 1.16 0.105384 0.0934951 26626 170182 -1 2395 22 1987 2942 229567 48017 3.36022 3.36022 -127.979 -3.36022 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0181155 0.0162911 90 55 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_042.v common 2.91 vpr 64.39 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29748 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 291 242 1 173 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2257 1074 10584 2543 6589 1452 64.4 MiB 0.05 0.00 4.8427 4.02108 -120.371 -4.02108 4.02108 0.24 0.000295137 0.000271181 0.0192343 0.0176373 -1 -1 -1 -1 34 2686 27 6.99608e+06 264882 618332. 2139.56 1.31 0.0984721 0.0865377 25762 151098 -1 2408 21 1352 2027 180812 38694 3.83326 3.83326 -129.933 -3.83326 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0148508 0.0132692 73 27 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_043.v common 8.73 vpr 65.75 MiB -1 -1 0.13 18060 1 0.04 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67328 32 32 457 356 1 282 90 17 17 289 -1 unnamed_device 26.4 MiB 0.34 3052 1509 12753 3455 8062 1236 65.8 MiB 0.08 0.00 6.26717 5.14656 -172.851 -5.14656 5.14656 0.24 0.000438438 0.000399665 0.0312348 0.0287359 -1 -1 -1 -1 40 3984 25 6.99608e+06 382608 706193. 2443.58 6.88 0.245438 0.215822 26914 176310 -1 3415 22 2474 3639 272449 59278 5.07634 5.07634 -175.218 -5.07634 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0225554 0.0203049 127 87 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_044.v common 2.27 vpr 64.58 MiB -1 -1 0.14 17672 1 0.03 -1 -1 29648 -1 -1 14 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66132 31 32 261 225 1 158 77 17 17 289 -1 unnamed_device 24.8 MiB 0.30 1593 899 7412 1777 4948 687 64.6 MiB 0.04 0.00 3.6621 3.0623 -104.163 -3.0623 3.0623 0.25 0.000597636 0.000555705 0.0176173 0.0163332 -1 -1 -1 -1 32 2111 32 6.99608e+06 206020 586450. 2029.24 0.60 0.0699195 0.0614205 25474 144626 -1 1852 20 1077 1450 120781 26826 3.31142 3.31142 -117.221 -3.31142 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0140206 0.0125371 65 28 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_045.v common 2.66 vpr 65.18 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30228 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66748 31 32 337 267 1 199 81 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2145 1115 11106 4094 5276 1736 65.2 MiB 0.06 0.00 4.77304 4.27184 -135.826 -4.27184 4.27184 0.25 0.000324833 0.000296411 0.0225737 0.0206979 -1 -1 -1 -1 44 2697 25 6.99608e+06 264882 787024. 2723.27 1.00 0.101064 0.0892623 27778 195446 -1 2120 21 1262 1981 149067 31664 4.02291 4.02291 -134.519 -4.02291 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0168417 0.0151147 82 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_046.v common 3.33 vpr 65.23 MiB -1 -1 0.12 18440 1 0.04 -1 -1 30020 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66800 32 32 349 284 1 213 84 17 17 289 -1 unnamed_device 25.2 MiB 0.34 2736 1076 15273 5235 7717 2321 65.2 MiB 0.08 0.00 4.55139 3.66953 -119.489 -3.66953 3.66953 0.24 0.000334283 0.000306338 0.0300208 0.0275113 -1 -1 -1 -1 42 2891 20 6.99608e+06 294314 744469. 2576.02 1.52 0.137871 0.120656 27202 183097 -1 2348 19 1511 2377 177851 40110 3.63266 3.63266 -126.058 -3.63266 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0163287 0.0147117 90 53 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_047.v common 7.22 vpr 64.62 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30168 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66176 32 32 291 230 1 160 83 17 17 289 -1 unnamed_device 24.9 MiB 0.20 1772 1011 10343 3054 6149 1140 64.6 MiB 0.09 0.00 4.52137 4.01417 -123.961 -4.01417 4.01417 0.29 0.000533086 0.000484878 0.0332193 0.0304525 -1 -1 -1 -1 36 2627 27 6.99608e+06 279598 648988. 2245.63 5.58 0.170154 0.149886 26050 158493 -1 2246 27 1497 2733 298227 86162 3.91606 3.91606 -131.254 -3.91606 0 0 828058. 2865.25 0.03 0.08 0.08 -1 -1 0.03 0.0183437 0.0162826 70 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_048.v common 3.80 vpr 65.15 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29736 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66716 32 32 353 287 1 210 83 17 17 289 -1 unnamed_device 25.8 MiB 0.48 2562 1041 14123 5669 6794 1660 65.2 MiB 0.09 0.00 4.62756 3.95722 -121.021 -3.95722 3.95722 0.25 0.000523358 0.000494676 0.0370832 0.0342115 -1 -1 -1 -1 38 3059 28 6.99608e+06 279598 678818. 2348.85 1.73 0.173229 0.152378 26626 170182 -1 2276 22 1550 2190 162466 35607 3.46336 3.46336 -123.742 -3.46336 0 0 902133. 3121.57 0.05 0.05 0.14 -1 -1 0.05 0.0177621 0.0159143 91 55 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_049.v common 4.27 vpr 65.19 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30164 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66756 32 32 361 291 1 214 85 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2404 1228 14407 4938 7065 2404 65.2 MiB 0.08 0.00 4.47599 3.61653 -127.814 -3.61653 3.61653 0.26 0.000342994 0.000313604 0.0323871 0.0296708 -1 -1 -1 -1 34 3482 45 6.99608e+06 309029 618332. 2139.56 2.58 0.169262 0.149247 25762 151098 -1 2670 20 1670 2442 197737 43022 3.59376 3.59376 -134.576 -3.59376 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0174682 0.0157616 94 55 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_050.v common 2.79 vpr 65.41 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29852 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66984 32 32 382 305 1 237 86 17 17 289 -1 unnamed_device 26.0 MiB 0.28 2390 1306 9725 3245 4874 1606 65.4 MiB 0.06 0.00 4.47137 3.65053 -130.846 -3.65053 3.65053 0.25 0.000352114 0.00032115 0.0220394 0.0202648 -1 -1 -1 -1 40 3093 27 6.99608e+06 323745 706193. 2443.58 1.04 0.110123 0.09724 26914 176310 -1 2643 22 2052 2804 233702 50043 3.29947 3.29947 -131.275 -3.29947 0 0 926341. 3205.33 0.03 0.07 0.11 -1 -1 0.03 0.0235983 0.0212753 101 62 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_051.v common 6.58 vpr 64.65 MiB -1 -1 0.12 17748 1 0.03 -1 -1 29776 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66200 32 32 306 248 1 175 80 17 17 289 -1 unnamed_device 25.2 MiB 0.41 2053 1074 11776 3968 6127 1681 64.6 MiB 0.07 0.00 5.26523 4.40603 -128.032 -4.40603 4.40603 0.26 0.000728279 0.000680288 0.0316996 0.0293502 -1 -1 -1 -1 34 2691 25 6.99608e+06 235451 618332. 2139.56 4.79 0.197275 0.172981 25762 151098 -1 2202 23 1453 2321 173808 37601 4.15667 4.15667 -136.845 -4.15667 0 0 787024. 2723.27 0.03 0.05 0.09 -1 -1 0.03 0.0195148 0.0174502 74 24 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_052.v common 3.39 vpr 64.48 MiB -1 -1 0.17 17676 1 0.03 -1 -1 29596 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 319 257 1 191 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2287 910 14606 5914 7002 1690 64.5 MiB 0.07 0.00 4.83128 4.09737 -124.66 -4.09737 4.09737 0.24 0.000310375 0.000283813 0.0282189 0.0258265 -1 -1 -1 -1 40 2417 38 6.99608e+06 250167 706193. 2443.58 1.69 0.153958 0.134164 26914 176310 -1 2039 22 1754 2409 172828 40103 4.13556 4.13556 -134.855 -4.13556 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0170663 0.0152923 79 29 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_053.v common 4.20 vpr 65.36 MiB -1 -1 0.22 18680 1 0.03 -1 -1 29812 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66928 31 32 373 299 1 222 83 17 17 289 -1 unnamed_device 25.3 MiB 0.29 3060 1061 14663 6195 7837 631 65.4 MiB 0.07 0.00 5.29948 4.04648 -128.43 -4.04648 4.04648 0.25 0.000346543 0.000316492 0.0300002 0.0274375 -1 -1 -1 -1 44 3255 35 6.99608e+06 294314 787024. 2723.27 2.28 0.202541 0.177628 27778 195446 -1 2207 24 1922 2925 205658 47391 4.38296 4.38296 -146.891 -4.38296 0 0 997811. 3452.63 0.04 0.05 0.12 -1 -1 0.04 0.0192397 0.0172114 96 62 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_054.v common 3.78 vpr 65.43 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 387 315 1 239 84 17 17 289 -1 unnamed_device 25.6 MiB 0.36 2489 1239 10515 4270 6030 215 65.4 MiB 0.08 0.00 4.49482 3.93712 -132.475 -3.93712 3.93712 0.26 0.00042534 0.0003946 0.0319843 0.0296844 -1 -1 -1 -1 42 3657 38 6.99608e+06 294314 744469. 2576.02 1.97 0.19167 0.168728 27202 183097 -1 2768 23 2154 3218 251393 54624 3.81701 3.81701 -136.091 -3.81701 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0194698 0.0174518 102 77 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_055.v common 2.78 vpr 64.02 MiB -1 -1 0.16 17916 1 0.03 -1 -1 29788 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65560 32 32 251 219 1 151 77 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1737 727 8879 3608 5056 215 64.0 MiB 0.04 0.00 3.88198 3.25548 -102.196 -3.25548 3.25548 0.28 0.00026341 0.0002409 0.0158008 0.0144687 -1 -1 -1 -1 38 1830 24 6.99608e+06 191304 678818. 2348.85 1.16 0.0983347 0.0862121 26626 170182 -1 1501 21 989 1400 93207 22725 2.96192 2.96192 -100.295 -2.96192 0 0 902133. 3121.57 0.03 0.03 0.09 -1 -1 0.03 0.013285 0.0118673 59 23 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_056.v common 7.37 vpr 65.13 MiB -1 -1 0.18 18056 1 0.03 -1 -1 30212 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66696 32 32 341 285 1 216 81 17 17 289 -1 unnamed_device 25.2 MiB 0.30 2337 1049 10756 3701 4965 2090 65.1 MiB 0.06 0.00 4.38205 3.60289 -133.031 -3.60289 3.60289 0.25 0.000415296 0.000387779 0.0239569 0.0220371 -1 -1 -1 -1 40 2703 23 6.99608e+06 250167 706193. 2443.58 5.55 0.167443 0.147046 26914 176310 -1 2352 23 2080 2820 262366 57085 3.88501 3.88501 -148.748 -3.88501 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0176703 0.015799 89 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_057.v common 4.03 vpr 64.22 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29984 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65764 32 32 387 293 1 225 82 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2656 1174 14144 6001 7737 406 64.2 MiB 0.08 0.00 5.84018 4.78152 -149.199 -4.78152 4.78152 0.32 0.00038237 0.00035059 0.0376424 0.0348163 -1 -1 -1 -1 50 2834 24 6.99608e+06 264882 902133. 3121.57 2.10 0.205741 0.181907 28642 213929 -1 2303 22 2041 3172 224362 48220 4.42076 4.42076 -146.875 -4.42076 0 0 1.08113e+06 3740.92 0.04 0.05 0.12 -1 -1 0.04 0.0197493 0.0177838 96 31 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_058.v common 2.62 vpr 65.04 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30412 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 32 32 340 270 1 205 82 17 17 289 -1 unnamed_device 25.3 MiB 0.24 2003 1157 10406 3036 5903 1467 65.0 MiB 0.05 0.00 4.01546 3.80886 -131.153 -3.80886 3.80886 0.25 0.000332988 0.00030492 0.0213291 0.0195744 -1 -1 -1 -1 36 2842 26 6.99608e+06 264882 648988. 2245.63 0.83 0.0904082 0.079963 26050 158493 -1 2400 20 1865 2578 211228 44537 3.22692 3.22692 -130.367 -3.22692 0 0 828058. 2865.25 0.05 0.08 0.15 -1 -1 0.05 0.0276081 0.0248415 83 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_059.v common 2.73 vpr 64.88 MiB -1 -1 0.19 17676 1 0.03 -1 -1 29812 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 30 32 278 235 1 166 86 17 17 289 -1 unnamed_device 25.6 MiB 0.17 1819 953 11237 3335 6152 1750 64.9 MiB 0.05 0.00 4.46953 3.72455 -123.086 -3.72455 3.72455 0.34 0.000295449 0.000271121 0.0207062 0.0190016 -1 -1 -1 -1 32 2493 41 6.99608e+06 353176 586450. 2029.24 0.99 0.0810683 0.0713788 25474 144626 -1 1945 20 1129 1868 155903 34266 3.66766 3.66766 -130.635 -3.66766 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169198 0.0148726 75 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_060.v common 13.97 vpr 65.62 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29780 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67192 32 32 431 332 1 263 86 17 17 289 -1 unnamed_device 25.6 MiB 0.36 3530 1523 10859 3269 7015 575 65.6 MiB 0.07 0.00 8.11443 6.30909 -191.484 -6.30909 6.30909 0.25 0.000409098 0.000372795 0.0269271 0.024715 -1 -1 -1 -1 40 3812 24 6.99608e+06 323745 706193. 2443.58 12.07 0.275135 0.243556 26914 176310 -1 3230 22 2400 3619 307902 64475 5.46454 5.46454 -183.101 -5.46454 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0224372 0.0202166 113 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_061.v common 2.82 vpr 64.55 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30360 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66096 32 32 336 268 1 199 81 17 17 289 -1 unnamed_device 25.6 MiB 0.33 2220 1042 7256 1709 5288 259 64.5 MiB 0.10 0.00 5.22335 4.47706 -136.26 -4.47706 4.47706 0.26 0.000897643 0.000833199 0.040152 0.0374168 -1 -1 -1 -1 36 2668 31 6.99608e+06 250167 648988. 2245.63 1.01 0.123457 0.110111 26050 158493 -1 2169 22 1855 2587 213043 45510 4.09836 4.09836 -141.679 -4.09836 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0173523 0.015543 82 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_062.v common 3.31 vpr 64.49 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30328 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 231 199 1 136 80 17 17 289 -1 unnamed_device 25.0 MiB 0.14 1667 644 6788 1443 5150 195 64.5 MiB 0.04 0.00 3.3651 2.966 -94.919 -2.966 2.966 0.25 0.000257042 0.000236046 0.0117376 0.0108063 -1 -1 -1 -1 36 1886 27 6.99608e+06 235451 648988. 2245.63 1.77 0.127294 0.111299 26050 158493 -1 1559 19 950 1545 119567 29462 2.94467 2.94467 -105.198 -2.94467 0 0 828058. 2865.25 0.05 0.07 0.09 -1 -1 0.05 0.0278513 0.024845 54 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_063.v common 4.46 vpr 65.26 MiB -1 -1 0.14 18056 1 0.03 -1 -1 30232 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66828 32 32 349 273 1 205 84 17 17 289 -1 unnamed_device 25.6 MiB 0.23 2149 1082 11430 4676 6413 341 65.3 MiB 0.06 0.00 5.75835 4.90682 -134.383 -4.90682 4.90682 0.25 0.000333152 0.000304183 0.0230581 0.0211123 -1 -1 -1 -1 50 2420 28 6.99608e+06 294314 902133. 3121.57 2.75 0.210124 0.185284 28642 213929 -1 2106 23 1498 2570 197970 44240 4.41151 4.41151 -133.222 -4.41151 0 0 1.08113e+06 3740.92 0.04 0.06 0.12 -1 -1 0.04 0.0201727 0.0180905 86 29 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_064.v common 2.35 vpr 64.20 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29800 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 247 207 1 142 80 17 17 289 -1 unnamed_device 24.9 MiB 0.14 1516 866 8852 2265 5550 1037 64.2 MiB 0.07 0.00 3.3589 2.9481 -106.495 -2.9481 2.9481 0.29 0.000477265 0.000433152 0.0294708 0.0271445 -1 -1 -1 -1 32 1986 23 6.99608e+06 235451 586450. 2029.24 0.76 0.0926109 0.0816633 25474 144626 -1 1818 21 1207 1848 144119 31724 2.97567 2.97567 -114.332 -2.97567 0 0 744469. 2576.02 0.04 0.04 0.14 -1 -1 0.04 0.0132219 0.0117761 58 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_065.v common 4.51 vpr 64.35 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29852 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 30 32 278 235 1 168 79 17 17 289 -1 unnamed_device 24.9 MiB 0.27 1881 846 11740 4899 6478 363 64.3 MiB 0.06 0.00 3.88477 3.61627 -115.385 -3.61627 3.61627 0.38 0.000277943 0.000253538 0.0253803 0.0232971 -1 -1 -1 -1 34 2626 42 6.99608e+06 250167 618332. 2139.56 2.59 0.149488 0.131234 25762 151098 -1 1930 22 1548 2150 173949 38779 3.36322 3.36322 -120.284 -3.36322 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0148292 0.0132602 69 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_066.v common 8.09 vpr 65.30 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29796 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66872 29 32 355 287 1 212 82 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2487 1076 7024 1631 5053 340 65.3 MiB 0.04 0.00 4.65503 4.06423 -126.233 -4.06423 4.06423 0.24 0.0003279 0.00030095 0.0150345 0.0137987 -1 -1 -1 -1 40 2852 44 6.99608e+06 309029 706193. 2443.58 6.39 0.19367 0.169529 26914 176310 -1 2416 21 1657 2448 196716 42818 3.649 3.649 -124.232 -3.649 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.0171414 0.0153764 94 62 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_067.v common 5.18 vpr 65.18 MiB -1 -1 0.12 18440 1 0.03 -1 -1 29760 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66744 32 32 358 289 1 214 83 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2512 1102 12323 3030 8331 962 65.2 MiB 0.06 0.00 5.76244 4.57197 -150.669 -4.57197 4.57197 0.25 0.000340918 0.00031236 0.0265798 0.0243785 -1 -1 -1 -1 40 2617 23 6.99608e+06 279598 706193. 2443.58 3.43 0.182268 0.159744 26914 176310 -1 2263 20 1664 2404 159920 36281 4.4118 4.4118 -149.852 -4.4118 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0170972 0.0153704 93 54 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_068.v common 6.18 vpr 65.29 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30264 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66856 32 32 353 285 1 210 82 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2477 1259 12542 3693 7235 1614 65.3 MiB 0.07 0.00 5.61514 4.67867 -148.606 -4.67867 4.67867 0.26 0.000330558 0.000302788 0.0284666 0.0261654 -1 -1 -1 -1 36 3280 30 6.99608e+06 264882 648988. 2245.63 4.40 0.190601 0.1677 26050 158493 -1 2804 20 1753 2535 251826 52553 4.52301 4.52301 -153.738 -4.52301 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0175652 0.0158305 90 51 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_069.v common 2.87 vpr 64.66 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29796 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 276 237 1 160 77 17 17 289 -1 unnamed_device 25.2 MiB 0.39 2019 874 7412 2163 4944 305 64.7 MiB 0.04 0.00 4.43837 3.56127 -113.067 -3.56127 3.56127 0.25 0.000283865 0.000260375 0.0142326 0.0130747 -1 -1 -1 -1 38 2164 36 6.99608e+06 191304 678818. 2348.85 1.10 0.109947 0.0967195 26626 170182 -1 1847 21 1125 1512 114209 25335 3.29786 3.29786 -114.972 -3.29786 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.016037 0.0142694 65 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_070.v common 2.83 vpr 64.50 MiB -1 -1 0.15 17676 1 0.03 -1 -1 29640 -1 -1 17 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 31 32 319 272 1 200 80 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2059 1143 8680 2684 4726 1270 64.5 MiB 0.06 0.00 3.74443 3.36163 -119.008 -3.36163 3.36163 0.28 0.000348439 0.000322031 0.0245664 0.02271 -1 -1 -1 -1 36 2725 29 6.99608e+06 250167 648988. 2245.63 1.02 0.131981 0.116646 26050 158493 -1 2415 23 1788 2474 198378 43599 3.45072 3.45072 -132.987 -3.45072 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0175891 0.0157376 83 64 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_071.v common 3.31 vpr 64.93 MiB -1 -1 0.18 18060 1 0.04 -1 -1 30516 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 30 32 329 273 1 202 84 17 17 289 -1 unnamed_device 25.2 MiB 0.37 2292 985 10698 3333 5234 2131 64.9 MiB 0.05 0.00 3.96185 3.1635 -104.256 -3.1635 3.1635 0.25 0.000310397 0.000283766 0.0202326 0.0185443 -1 -1 -1 -1 38 2681 23 6.99608e+06 323745 678818. 2348.85 1.43 0.133462 0.116748 26626 170182 -1 2079 21 1525 2176 145997 33843 3.15117 3.15117 -108.403 -3.15117 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0163276 0.0146456 88 57 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_072.v common 2.62 vpr 64.30 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29820 -1 -1 20 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65848 28 32 277 229 1 167 80 17 17 289 -1 unnamed_device 24.6 MiB 0.18 2171 750 13324 5641 6785 898 64.3 MiB 0.06 0.00 4.60235 3.68935 -102.007 -3.68935 3.68935 0.26 0.000280311 0.000256331 0.0262871 0.0241405 -1 -1 -1 -1 38 2095 46 6.99608e+06 294314 678818. 2348.85 1.06 0.0999501 0.0881336 26626 170182 -1 1637 20 1275 2053 133456 31957 3.86712 3.86712 -107.152 -3.86712 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0139935 0.0125284 70 27 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_073.v common 4.06 vpr 64.07 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29780 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65612 30 32 317 269 1 200 80 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2064 1130 10400 3752 5071 1577 64.1 MiB 0.08 0.00 4.54182 3.92332 -130.777 -3.92332 3.92332 0.44 0.000299101 0.00027329 0.0360045 0.0331235 -1 -1 -1 -1 44 2351 40 6.99608e+06 264882 787024. 2723.27 1.79 0.167755 0.146837 27778 195446 -1 2079 50 2714 3757 509029 223795 3.54531 3.54531 -130.146 -3.54531 0 0 997811. 3452.63 0.04 0.17 0.11 -1 -1 0.04 0.0301622 0.0264103 84 63 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 3.55 vpr 64.54 MiB -1 -1 0.20 17672 1 0.03 -1 -1 30204 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66088 32 32 335 282 1 216 82 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2365 1114 12542 4673 5784 2085 64.5 MiB 0.08 0.00 3.99224 3.50894 -127.534 -3.50894 3.50894 0.25 0.000315106 0.000287859 0.034242 0.0315552 -1 -1 -1 -1 42 2677 24 6.99608e+06 264882 744469. 2576.02 1.61 0.152336 0.134508 27202 183097 -1 2084 22 1659 2257 159018 34861 3.14317 3.14317 -124.044 -3.14317 0 0 949917. 3286.91 0.03 0.05 0.10 -1 -1 0.03 0.0187501 0.0166729 87 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_075.v common 8.45 vpr 65.02 MiB -1 -1 0.13 17672 1 0.03 -1 -1 29552 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 31 32 293 230 1 168 91 17 17 289 -1 unnamed_device 25.2 MiB 0.09 2000 982 10903 2684 7356 863 65.0 MiB 0.05 0.00 4.71072 4.12848 -125.314 -4.12848 4.12848 0.24 0.000299526 0.000273857 0.0177575 0.0162742 -1 -1 -1 -1 40 2473 20 6.99608e+06 412039 706193. 2443.58 6.98 0.188456 0.165444 26914 176310 -1 2209 24 1486 2666 236458 56195 4.03642 4.03642 -129.321 -4.03642 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0170776 0.0152593 77 4 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_076.v common 3.08 vpr 64.80 MiB -1 -1 0.15 17916 1 0.03 -1 -1 29968 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 350 275 1 206 83 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2490 1189 13403 4211 7234 1958 64.8 MiB 0.08 0.00 4.89302 4.14724 -142.136 -4.14724 4.14724 0.26 0.00033104 0.000302573 0.034491 0.0318021 -1 -1 -1 -1 36 3453 42 6.99608e+06 279598 648988. 2245.63 1.35 0.125825 0.111916 26050 158493 -1 2897 21 1884 2802 281160 57735 4.19956 4.19956 -157.838 -4.19956 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0184156 0.0165322 87 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_077.v common 4.17 vpr 64.71 MiB -1 -1 0.21 18060 1 0.04 -1 -1 29772 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 32 32 385 308 1 237 85 17 17 289 -1 unnamed_device 25.8 MiB 0.44 2652 1256 15151 5422 7831 1898 64.7 MiB 0.08 0.00 5.94478 5.006 -165.631 -5.006 5.006 0.25 0.000358141 0.000328231 0.0313961 0.0287286 -1 -1 -1 -1 40 3284 27 6.99608e+06 309029 706193. 2443.58 1.99 0.176264 0.156042 26914 176310 -1 2763 21 2194 3069 284504 58389 4.65534 4.65534 -165.239 -4.65534 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.020252 0.0182285 103 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_078.v common 3.00 vpr 65.43 MiB -1 -1 0.14 18296 1 0.03 -1 -1 29856 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 387 309 1 244 86 17 17 289 -1 unnamed_device 25.6 MiB 0.38 3090 1280 16529 5531 8719 2279 65.4 MiB 0.09 0.00 4.97976 4.22796 -143.885 -4.22796 4.22796 0.26 0.000359741 0.000330081 0.0345095 0.0317078 -1 -1 -1 -1 38 3429 46 6.99608e+06 323745 678818. 2348.85 1.11 0.118587 0.105226 26626 170182 -1 2650 21 2083 3065 220833 47744 4.0125 4.0125 -147.917 -4.0125 0 0 902133. 3121.57 0.03 0.06 0.10 -1 -1 0.03 0.0220048 0.0195822 102 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_079.v common 4.55 vpr 64.08 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29876 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65620 30 32 272 232 1 169 79 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1873 976 10388 2655 6704 1029 64.1 MiB 0.05 0.00 4.35146 3.77996 -115.544 -3.77996 3.77996 0.25 0.000298857 0.000275244 0.019425 0.0178398 -1 -1 -1 -1 32 2668 46 6.99608e+06 250167 586450. 2029.24 2.81 0.171253 0.150186 25474 144626 -1 2156 23 1627 2295 190396 40496 3.16982 3.16982 -119.919 -3.16982 0 0 744469. 2576.02 0.04 0.08 0.14 -1 -1 0.04 0.0250296 0.0223372 68 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_080.v common 7.57 vpr 65.39 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29808 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66964 30 32 375 299 1 231 83 17 17 289 -1 unnamed_device 25.6 MiB 0.35 2543 1226 12863 4164 7357 1342 65.4 MiB 0.07 0.00 6.19097 4.8136 -157.664 -4.8136 4.8136 0.25 0.000343255 0.000314156 0.0271782 0.0248716 -1 -1 -1 -1 38 3234 41 6.99608e+06 309029 678818. 2348.85 5.75 0.208307 0.182755 26626 170182 -1 2608 23 2337 3366 264876 55857 4.57834 4.57834 -160.67 -4.57834 0 0 902133. 3121.57 0.03 0.06 0.11 -1 -1 0.03 0.0198221 0.0178488 101 63 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_081.v common 10.75 vpr 65.09 MiB -1 -1 0.21 18060 1 0.03 -1 -1 29580 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 340 270 1 197 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2353 1072 9338 2392 6620 326 65.1 MiB 0.05 0.00 5.08705 4.46071 -137.725 -4.46071 4.46071 0.25 0.000326806 0.000298657 0.0201311 0.018525 -1 -1 -1 -1 36 3037 36 6.99608e+06 264882 648988. 2245.63 8.96 0.198441 0.174241 26050 158493 -1 2579 20 1968 3193 317298 64436 4.05906 4.05906 -142.951 -4.05906 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0165587 0.014862 83 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_082.v common 5.09 vpr 65.23 MiB -1 -1 0.14 18444 1 0.03 -1 -1 29780 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66800 31 32 340 275 1 195 82 17 17 289 -1 unnamed_device 25.2 MiB 0.52 2485 1077 6846 1660 4720 466 65.2 MiB 0.04 0.00 5.99233 5.0824 -146.792 -5.0824 5.0824 0.25 0.000332049 0.000305039 0.0153348 0.0141025 -1 -1 -1 -1 36 2949 36 6.99608e+06 279598 648988. 2245.63 2.99 0.163543 0.14333 26050 158493 -1 2436 25 1611 2368 219315 58630 4.22141 4.22141 -143.659 -4.22141 0 0 828058. 2865.25 0.05 0.10 0.14 -1 -1 0.05 0.0345574 0.0311452 87 47 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_083.v common 4.20 vpr 64.68 MiB -1 -1 0.14 18296 1 0.03 -1 -1 30180 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 30 32 377 310 1 234 85 17 17 289 -1 unnamed_device 25.2 MiB 0.40 2527 1287 11803 3693 6222 1888 64.7 MiB 0.07 0.00 4.79242 3.97958 -130.547 -3.97958 3.97958 0.28 0.000341223 0.000312216 0.0298593 0.0275985 -1 -1 -1 -1 46 2907 27 6.99608e+06 338461 828058. 2865.25 2.30 0.188811 0.166861 28066 200906 -1 2352 20 1694 2546 209301 42710 3.4157 3.4157 -127.942 -3.4157 0 0 1.01997e+06 3529.29 0.04 0.05 0.11 -1 -1 0.04 0.0172781 0.0155465 105 83 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_084.v common 4.16 vpr 65.34 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29776 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66908 32 32 365 294 1 223 83 17 17 289 -1 unnamed_device 25.2 MiB 0.32 2642 1080 13043 4299 6062 2682 65.3 MiB 0.10 0.00 5.91884 4.65647 -145.605 -4.65647 4.65647 0.28 0.000616403 0.000561375 0.039827 0.0366499 -1 -1 -1 -1 58 2339 29 6.99608e+06 279598 997811. 3452.63 2.26 0.197471 0.173865 30370 251734 -1 1947 23 1549 2349 189783 40720 4.15385 4.15385 -138.843 -4.15385 0 0 1.25153e+06 4330.55 0.04 0.05 0.14 -1 -1 0.04 0.0191202 0.0171213 94 57 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_085.v common 3.96 vpr 65.42 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29244 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66988 29 32 378 310 1 232 84 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2249 1133 10332 4059 5536 737 65.4 MiB 0.06 0.00 4.37595 3.76735 -122.856 -3.76735 3.76735 0.25 0.000806941 0.000751406 0.0263063 0.0242243 -1 -1 -1 -1 40 2918 21 6.99608e+06 338461 706193. 2443.58 2.22 0.200676 0.177945 26914 176310 -1 2367 22 1494 2036 156146 35777 4.04156 4.04156 -134.374 -4.04156 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0229383 0.0205342 106 85 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_086.v common 3.20 vpr 64.49 MiB -1 -1 0.16 17676 1 0.03 -1 -1 30300 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 243 205 1 140 77 17 17 289 -1 unnamed_device 24.9 MiB 0.54 1620 885 6108 1414 4233 461 64.5 MiB 0.04 0.00 3.92693 3.42573 -113.797 -3.42573 3.42573 0.27 0.000262716 0.000240101 0.0155632 0.014418 -1 -1 -1 -1 32 2105 20 6.99608e+06 191304 586450. 2029.24 1.23 0.121706 0.106417 25474 144626 -1 1872 20 1044 1623 134418 28714 3.15892 3.15892 -116.975 -3.15892 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145525 0.0129752 56 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_087.v common 3.10 vpr 65.38 MiB -1 -1 0.13 17916 1 0.04 -1 -1 30272 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 373 302 1 234 85 17 17 289 -1 unnamed_device 25.3 MiB 0.25 2757 1184 15523 6072 7602 1849 65.4 MiB 0.08 0.00 6.55248 4.951 -158.167 -4.951 4.951 0.25 0.000359023 0.000329679 0.0314315 0.0288277 -1 -1 -1 -1 38 3214 39 6.99608e+06 309029 678818. 2348.85 1.29 0.120257 0.106819 26626 170182 -1 2557 23 2159 3151 273144 56610 4.50624 4.50624 -154.678 -4.50624 0 0 902133. 3121.57 0.05 0.10 0.11 -1 -1 0.05 0.0328808 0.0296767 98 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_088.v common 4.56 vpr 64.09 MiB -1 -1 0.15 18056 1 0.03 -1 -1 29748 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 32 32 397 314 1 249 85 17 17 289 -1 unnamed_device 24.5 MiB 0.37 2726 1321 14965 5056 8532 1377 64.1 MiB 0.08 0.00 5.25319 4.65797 -164.783 -4.65797 4.65797 0.25 0.000368298 0.000331202 0.0316858 0.0290061 -1 -1 -1 -1 40 3636 25 6.99608e+06 309029 706193. 2443.58 2.70 0.227798 0.201867 26914 176310 -1 2903 21 2508 3573 301907 62282 4.82971 4.82971 -176.472 -4.82971 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0188725 0.0170092 105 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_089.v common 2.76 vpr 64.69 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29784 -1 -1 13 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 32 32 269 231 1 163 77 17 17 289 -1 unnamed_device 25.5 MiB 0.26 1853 737 10346 4283 5770 293 64.7 MiB 0.05 0.00 3.61613 3.25618 -100.635 -3.25618 3.25618 0.26 0.000294064 0.00026383 0.0250246 0.0231762 -1 -1 -1 -1 40 1864 45 6.99608e+06 191304 706193. 2443.58 1.05 0.104956 0.0924776 26914 176310 -1 1561 25 1244 1653 120205 30029 3.41867 3.41867 -112.985 -3.41867 0 0 926341. 3205.33 0.05 0.04 0.17 -1 -1 0.05 0.0158374 0.0140831 66 29 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_090.v common 2.08 vpr 64.09 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30324 -1 -1 16 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 24.9 MiB 0.11 1536 858 8360 2256 5168 936 64.1 MiB 0.04 0.00 3.61893 3.28943 -106.361 -3.28943 3.28943 0.35 0.000256667 0.000234795 0.014228 0.0130658 -1 -1 -1 -1 32 2072 26 6.99608e+06 235451 586450. 2029.24 0.56 0.0580191 0.0509893 25474 144626 -1 1856 19 1171 1959 154991 34293 3.14792 3.14792 -114.535 -3.14792 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0130327 0.0116131 59 4 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_091.v common 3.42 vpr 65.25 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29996 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66820 32 32 348 274 1 209 82 17 17 289 -1 unnamed_device 25.2 MiB 0.26 2619 1051 8270 2110 5627 533 65.3 MiB 0.05 0.00 4.98867 4.02312 -135.346 -4.02312 4.02312 0.24 0.000356126 0.000327305 0.0175964 0.0161306 -1 -1 -1 -1 40 2752 48 6.99608e+06 264882 706193. 2443.58 1.62 0.131444 0.115935 26914 176310 -1 2412 21 1981 2778 221710 49503 4.01046 4.01046 -144.849 -4.01046 0 0 926341. 3205.33 0.05 0.09 0.16 -1 -1 0.05 0.0312576 0.0282401 85 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_092.v common 3.75 vpr 65.31 MiB -1 -1 0.12 17696 1 0.03 -1 -1 30196 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66876 32 32 356 289 1 215 85 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2661 1142 10687 2890 6795 1002 65.3 MiB 0.06 0.00 5.42227 4.69222 -141.619 -4.69222 4.69222 0.24 0.000331438 0.000303919 0.0213103 0.0195584 -1 -1 -1 -1 36 3081 25 6.99608e+06 309029 648988. 2245.63 1.92 0.196571 0.172762 26050 158493 -1 2497 20 1667 2322 178458 40445 4.59211 4.59211 -151.626 -4.59211 0 0 828058. 2865.25 0.03 0.09 0.12 -1 -1 0.03 0.032519 0.0294266 93 56 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_093.v common 4.75 vpr 64.54 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29808 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66092 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 25.3 MiB 0.13 2109 1015 8913 2758 4385 1770 64.5 MiB 0.04 0.00 5.39397 4.48151 -135.956 -4.48151 4.48151 0.25 0.000344854 0.000313183 0.0166858 0.0152261 -1 -1 -1 -1 46 2960 42 6.99608e+06 426755 828058. 2865.25 3.17 0.188439 0.16599 28066 200906 -1 2212 21 1697 3063 248423 56450 4.31935 4.31935 -140.411 -4.31935 0 0 1.01997e+06 3529.29 0.04 0.06 0.11 -1 -1 0.04 0.0181888 0.0163971 90 3 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_094.v common 2.90 vpr 65.11 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29988 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 30 32 316 264 1 191 83 17 17 289 -1 unnamed_device 25.6 MiB 0.38 2606 1009 7823 1822 5457 544 65.1 MiB 0.04 0.00 4.76312 3.58427 -106.995 -3.58427 3.58427 0.25 0.000308712 0.000283316 0.015233 0.0140358 -1 -1 -1 -1 36 2586 30 6.99608e+06 309029 648988. 2245.63 1.08 0.106457 0.0937082 26050 158493 -1 2283 24 1925 2911 230611 48960 3.34252 3.34252 -113.894 -3.34252 0 0 828058. 2865.25 0.03 0.06 0.11 -1 -1 0.03 0.0217187 0.0192677 86 52 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_095.v common 3.04 vpr 64.51 MiB -1 -1 0.11 17916 1 0.03 -1 -1 30168 -1 -1 17 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 27 32 255 219 1 145 76 17 17 289 -1 unnamed_device 24.9 MiB 0.21 1732 742 10956 3486 6732 738 64.5 MiB 0.04 0.00 4.92129 3.75245 -110.833 -3.75245 3.75245 0.24 0.000254695 0.00023279 0.0189859 0.0174081 -1 -1 -1 -1 30 1917 29 6.99608e+06 250167 556674. 1926.21 1.56 0.0982599 0.0857575 25186 138497 -1 1600 18 968 1431 102703 23011 3.61546 3.61546 -115.129 -3.61546 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0121467 0.0108756 67 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_096.v common 10.72 vpr 65.53 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29736 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67100 32 32 421 327 1 263 87 17 17 289 -1 unnamed_device 25.6 MiB 0.32 3139 1454 14487 3900 9094 1493 65.5 MiB 0.13 0.00 5.82494 4.22974 -144.161 -4.22974 4.22974 0.30 0.00039563 0.000362842 0.0564457 0.052421 -1 -1 -1 -1 42 3877 49 6.99608e+06 338461 744469. 2576.02 8.82 0.261665 0.23186 27202 183097 -1 3220 21 2143 3398 291996 60989 4.20031 4.20031 -152.043 -4.20031 0 0 949917. 3286.91 0.04 0.06 0.10 -1 -1 0.04 0.0201234 0.0181126 110 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_097.v common 3.24 vpr 64.75 MiB -1 -1 0.15 18060 1 0.03 -1 -1 29756 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 31 32 365 296 1 229 84 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2811 1262 12894 3886 6900 2108 64.7 MiB 0.07 0.00 6.59169 5.46783 -160.186 -5.46783 5.46783 0.25 0.000339653 0.000311033 0.0258576 0.0236764 -1 -1 -1 -1 40 2874 28 6.99608e+06 309029 706193. 2443.58 1.49 0.140763 0.124371 26914 176310 -1 2401 22 2013 2891 213884 45949 4.54281 4.54281 -157.549 -4.54281 0 0 926341. 3205.33 0.03 0.05 0.09 -1 -1 0.03 0.018057 0.0162127 97 64 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_098.v common 3.44 vpr 65.15 MiB -1 -1 0.15 18444 1 0.02 -1 -1 29880 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 32 32 331 280 1 215 82 17 17 289 -1 unnamed_device 25.2 MiB 0.29 2580 1220 8448 2298 5647 503 65.1 MiB 0.05 0.00 4.4353 3.55199 -133.806 -3.55199 3.55199 0.26 0.000319361 0.000292362 0.0213717 0.0197884 -1 -1 -1 -1 36 2753 24 6.99608e+06 264882 648988. 2245.63 1.68 0.158365 0.138772 26050 158493 -1 2346 21 1724 2226 174140 38058 3.49956 3.49956 -137.622 -3.49956 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0165778 0.0149044 86 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_099.v common 3.91 vpr 64.49 MiB -1 -1 0.12 17916 1 0.03 -1 -1 30300 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 326 263 1 198 81 17 17 289 -1 unnamed_device 25.2 MiB 0.24 2007 915 11806 4558 6015 1233 64.5 MiB 0.06 0.00 4.69498 4.19833 -126.153 -4.19833 4.19833 0.35 0.000331511 0.000303973 0.027978 0.0258442 -1 -1 -1 -1 44 2540 49 6.99608e+06 250167 787024. 2723.27 2.16 0.194089 0.170363 27778 195446 -1 1804 19 1192 1636 115903 27473 3.77352 3.77352 -123.719 -3.77352 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0177594 0.0161027 80 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_100.v common 2.91 vpr 65.25 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29868 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66816 31 32 373 294 1 216 84 17 17 289 -1 unnamed_device 25.8 MiB 0.36 2762 1151 14907 5290 7728 1889 65.2 MiB 0.09 0.00 5.40098 4.12378 -127.257 -4.12378 4.12378 0.24 0.000371977 0.000340791 0.0370602 0.0340631 -1 -1 -1 -1 40 2607 25 6.99608e+06 309029 706193. 2443.58 1.10 0.12845 0.114036 26914 176310 -1 2325 22 1845 2733 198743 43453 3.81082 3.81082 -130.703 -3.81082 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.019102 0.0171685 97 50 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_101.v common 3.97 vpr 65.03 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29816 -1 -1 20 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 30 32 325 268 1 197 82 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2275 931 9694 3916 5291 487 65.0 MiB 0.05 0.00 4.37729 3.52894 -109.796 -3.52894 3.52894 0.24 0.000319843 0.00028404 0.0189408 0.017331 -1 -1 -1 -1 46 2439 26 6.99608e+06 294314 828058. 2865.25 2.25 0.144389 0.126734 28066 200906 -1 1870 19 1331 2123 160757 36535 3.48697 3.48697 -114.338 -3.48697 0 0 1.01997e+06 3529.29 0.04 0.04 0.11 -1 -1 0.04 0.0153406 0.0138183 85 51 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_102.v common 3.77 vpr 65.11 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29792 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66672 32 32 350 275 1 209 82 17 17 289 -1 unnamed_device 25.6 MiB 0.29 2452 1191 11118 2720 7663 735 65.1 MiB 0.06 0.00 4.76098 4.21963 -145.335 -4.21963 4.21963 0.25 0.000357095 0.000307568 0.0240345 0.0221081 -1 -1 -1 -1 42 3059 30 6.99608e+06 264882 744469. 2576.02 1.99 0.183276 0.160905 27202 183097 -1 2646 22 2111 3171 339117 78140 4.30592 4.30592 -150.736 -4.30592 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.0180706 0.0162177 87 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_103.v common 3.22 vpr 65.43 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67000 32 32 386 307 1 240 85 17 17 289 -1 unnamed_device 25.5 MiB 0.28 2544 1330 10687 2581 6972 1134 65.4 MiB 0.06 0.00 4.10857 3.66363 -131.207 -3.66363 3.66363 0.24 0.000358631 0.000328675 0.0233891 0.0214854 -1 -1 -1 -1 40 2913 20 6.99608e+06 309029 706193. 2443.58 1.54 0.146169 0.128078 26914 176310 -1 2609 26 2198 3089 256591 54227 3.46877 3.46877 -133.609 -3.46877 0 0 926341. 3205.33 0.03 0.07 0.09 -1 -1 0.03 0.0247133 0.0222095 102 62 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.89 vpr 64.69 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29992 -1 -1 18 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66240 29 32 269 229 1 166 79 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1756 750 8867 3422 4589 856 64.7 MiB 0.04 0.00 4.44376 3.81986 -111.589 -3.81986 3.81986 0.25 0.000268678 0.000245483 0.0157691 0.0144682 -1 -1 -1 -1 32 2228 31 6.99608e+06 264882 586450. 2029.24 2.28 0.125635 0.109629 25474 144626 -1 1667 22 1606 2144 164445 35623 3.43772 3.43772 -115.848 -3.43772 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0143813 0.012807 68 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 4.92 vpr 65.08 MiB -1 -1 0.12 17916 1 0.02 -1 -1 29928 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66640 32 32 310 266 1 186 79 17 17 289 -1 unnamed_device 25.6 MiB 0.25 2114 1072 10388 2745 6664 979 65.1 MiB 0.05 0.00 4.23779 3.56989 -126.273 -3.56989 3.56989 0.25 0.000302879 0.000276572 0.0200515 0.018352 -1 -1 -1 -1 40 2251 27 6.99608e+06 220735 706193. 2443.58 3.29 0.150356 0.131318 26914 176310 -1 2129 19 1386 1859 153495 33604 3.78796 3.78796 -134.796 -3.78796 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0256499 0.0230263 78 58 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_106.v common 3.40 vpr 64.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30268 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65664 31 32 326 261 1 197 83 17 17 289 -1 unnamed_device 25.2 MiB 0.22 2462 1162 13763 5234 6995 1534 64.1 MiB 0.07 0.00 5.08188 4.09932 -130.497 -4.09932 4.09932 0.24 0.000314789 0.000287897 0.02625 0.0240865 -1 -1 -1 -1 46 2358 22 6.99608e+06 294314 828058. 2865.25 1.74 0.147828 0.129695 28066 200906 -1 2124 17 1370 2011 124268 27371 3.74866 3.74866 -129.695 -3.74866 0 0 1.01997e+06 3529.29 0.04 0.04 0.11 -1 -1 0.04 0.0146133 0.0132243 82 33 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_107.v common 4.76 vpr 64.61 MiB -1 -1 0.12 17676 1 0.02 -1 -1 30212 -1 -1 17 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 29 32 262 224 1 162 78 17 17 289 -1 unnamed_device 24.9 MiB 0.25 1704 837 10204 3081 5451 1672 64.6 MiB 0.05 0.00 4.00332 3.52002 -104.505 -3.52002 3.52002 0.24 0.000266925 0.000244771 0.0181439 0.016651 -1 -1 -1 -1 34 2235 27 6.99608e+06 250167 618332. 2139.56 3.12 0.149414 0.130029 25762 151098 -1 1839 33 1724 2185 236919 81430 3.10977 3.10977 -108.554 -3.10977 0 0 787024. 2723.27 0.03 0.10 0.08 -1 -1 0.03 0.029701 0.0266071 67 31 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 5.46 vpr 63.99 MiB -1 -1 0.13 17676 1 0.02 -1 -1 30164 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 278 238 1 178 79 17 17 289 -1 unnamed_device 24.9 MiB 0.27 2344 802 11233 4665 6317 251 64.0 MiB 0.05 0.00 4.87466 3.81986 -117.727 -3.81986 3.81986 0.25 0.000293201 0.000268469 0.0227949 0.020989 -1 -1 -1 -1 36 2662 38 6.99608e+06 220735 648988. 2245.63 3.82 0.16388 0.143411 26050 158493 -1 1945 22 1737 2335 205163 46980 3.35647 3.35647 -125.635 -3.35647 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0146639 0.0130972 70 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 3.50 vpr 64.76 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 373 300 1 230 85 17 17 289 -1 unnamed_device 25.2 MiB 0.35 2524 1290 13291 4296 7426 1569 64.8 MiB 0.07 0.00 5.14528 3.96644 -137.42 -3.96644 3.96644 0.25 0.000387044 0.000354926 0.0287595 0.0262542 -1 -1 -1 -1 44 2878 34 6.99608e+06 323745 787024. 2723.27 1.73 0.151986 0.133028 27778 195446 -1 2429 20 1825 2644 204826 43184 3.64925 3.64925 -135.828 -3.64925 0 0 997811. 3452.63 0.04 0.05 0.11 -1 -1 0.04 0.0179987 0.0161854 100 64 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_110.v common 2.92 vpr 64.68 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29828 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 31 32 265 230 1 170 78 17 17 289 -1 unnamed_device 25.2 MiB 0.22 1901 926 8378 2454 4499 1425 64.7 MiB 0.05 0.00 3.62338 3.26538 -103.352 -3.26538 3.26538 0.26 0.000272319 0.000249627 0.0194942 0.0180456 -1 -1 -1 -1 38 2049 20 6.99608e+06 220735 678818. 2348.85 1.28 0.102417 0.0892263 26626 170182 -1 1809 21 1209 1714 135631 28455 2.80117 2.80117 -107.376 -2.80117 0 0 902133. 3121.57 0.03 0.04 0.17 -1 -1 0.03 0.0141216 0.0125816 67 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_111.v common 2.51 vpr 65.15 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29804 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66712 32 32 349 286 1 207 82 17 17 289 -1 unnamed_device 25.6 MiB 0.27 2683 1135 10584 3164 6747 673 65.1 MiB 0.06 0.00 4.36937 3.54449 -120.669 -3.54449 3.54449 0.25 0.000338843 0.000311513 0.0217633 0.0199616 -1 -1 -1 -1 38 2762 21 6.99608e+06 264882 678818. 2348.85 0.89 0.0998171 0.0884553 26626 170182 -1 2311 19 1299 1882 133571 29409 3.16766 3.16766 -121.59 -3.16766 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0163812 0.0147286 89 57 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_112.v common 3.05 vpr 65.50 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29576 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67072 31 32 396 325 1 257 88 17 17 289 -1 unnamed_device 26.0 MiB 0.29 2720 1315 14128 4475 8272 1381 65.5 MiB 0.08 0.00 6.02652 4.44482 -155.897 -4.44482 4.44482 0.26 0.000742385 0.000711038 0.0330194 0.0304111 -1 -1 -1 -1 36 3582 39 6.99608e+06 367892 648988. 2245.63 1.27 0.133571 0.118438 26050 158493 -1 2929 30 2912 4166 446962 115122 4.4407 4.4407 -163.878 -4.4407 0 0 828058. 2865.25 0.03 0.10 0.08 -1 -1 0.03 0.0236603 0.0210998 111 91 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_113.v common 2.45 vpr 65.07 MiB -1 -1 0.11 18052 1 0.02 -1 -1 29604 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 303 262 1 189 80 17 17 289 -1 unnamed_device 25.0 MiB 0.32 1997 1013 12808 5361 7263 184 65.1 MiB 0.06 0.00 4.02834 3.18879 -114.113 -3.18879 3.18879 0.24 0.00029145 0.000266248 0.0237704 0.0217697 -1 -1 -1 -1 40 2271 23 6.99608e+06 235451 706193. 2443.58 0.77 0.0897322 0.0787789 26914 176310 -1 1978 19 1566 2160 160897 35900 2.92196 2.92196 -113.469 -2.92196 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0177855 0.0158654 80 57 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_114.v common 2.89 vpr 64.03 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29764 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65568 32 32 290 244 1 174 79 17 17 289 -1 unnamed_device 25.2 MiB 0.25 2070 991 12078 3761 7335 982 64.0 MiB 0.07 0.00 3.92883 3.42763 -115.198 -3.42763 3.42763 0.25 0.000352015 0.00032687 0.0293293 0.0270993 -1 -1 -1 -1 44 2260 49 6.99608e+06 220735 787024. 2723.27 1.27 0.11646 0.102895 27778 195446 -1 1939 20 1462 2114 176026 37248 3.13262 3.13262 -118.27 -3.13262 0 0 997811. 3452.63 0.04 0.04 0.11 -1 -1 0.04 0.0141357 0.0126608 70 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_115.v common 3.03 vpr 64.48 MiB -1 -1 0.14 17976 1 0.03 -1 -1 29776 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 318 257 1 190 81 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2008 1061 12156 3939 6984 1233 64.5 MiB 0.06 0.00 4.55868 4.12158 -127.831 -4.12158 4.12158 0.34 0.000319482 0.00029223 0.0286941 0.0265897 -1 -1 -1 -1 36 2636 26 6.99608e+06 250167 648988. 2245.63 1.09 0.120052 0.106785 26050 158493 -1 2264 21 1654 2305 182456 39548 3.99926 3.99926 -138.156 -3.99926 0 0 828058. 2865.25 0.05 0.08 0.14 -1 -1 0.05 0.0252004 0.0226623 79 30 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_116.v common 3.84 vpr 64.70 MiB -1 -1 0.21 18060 1 0.04 -1 -1 30232 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 29 32 324 268 1 193 80 17 17 289 -1 unnamed_device 25.2 MiB 0.28 2038 850 7992 3080 4019 893 64.7 MiB 0.04 0.00 4.14059 3.42459 -102.439 -3.42459 3.42459 0.24 0.000309691 0.000283343 0.0167648 0.0154227 -1 -1 -1 -1 38 2478 27 6.99608e+06 279598 678818. 2348.85 1.97 0.15036 0.131366 26626 170182 -1 1937 19 1363 2005 132397 30881 3.27106 3.27106 -107.497 -3.27106 0 0 902133. 3121.57 0.03 0.04 0.15 -1 -1 0.03 0.0152913 0.0137551 85 55 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_117.v common 4.11 vpr 65.06 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29792 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66624 32 32 393 312 1 234 83 17 17 289 -1 unnamed_device 25.6 MiB 0.31 2763 1341 14303 4864 7770 1669 65.1 MiB 0.08 0.00 6.04713 5.29533 -174.708 -5.29533 5.29533 0.25 0.000363933 0.000332944 0.0312788 0.0287185 -1 -1 -1 -1 48 3515 28 6.99608e+06 279598 865456. 2994.66 2.34 0.196802 0.172935 28354 207349 -1 2907 22 1926 2921 248278 49536 4.46704 4.46704 -168.361 -4.46704 0 0 1.05005e+06 3633.38 0.04 0.07 0.11 -1 -1 0.04 0.0224785 0.02012 102 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_118.v common 3.22 vpr 64.43 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29936 -1 -1 15 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 31 32 229 197 1 138 78 17 17 289 -1 unnamed_device 24.9 MiB 0.38 1665 866 10038 3879 5332 827 64.4 MiB 0.04 0.00 3.45398 3.07808 -95.6005 -3.07808 3.07808 0.25 0.00025341 0.000231039 0.0176736 0.0161604 -1 -1 -1 -1 34 1957 19 6.99608e+06 220735 618332. 2139.56 1.45 0.11107 0.0962653 25762 151098 -1 1727 19 948 1543 115724 25796 2.76232 2.76232 -99.9411 -2.76232 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0119476 0.0106754 55 4 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_119.v common 3.17 vpr 65.16 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30156 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66724 32 32 412 334 1 258 87 17 17 289 -1 unnamed_device 25.6 MiB 0.30 3136 1376 11799 3682 6020 2097 65.2 MiB 0.06 0.00 6.25193 4.95808 -168.612 -4.95808 4.95808 0.35 0.000374179 0.000341467 0.0250565 0.0229553 -1 -1 -1 -1 36 3619 37 6.99608e+06 338461 648988. 2245.63 1.34 0.128163 0.113155 26050 158493 -1 2910 20 2239 2839 225407 51024 5.3834 5.3834 -185.015 -5.3834 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0193173 0.017444 114 90 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_120.v common 8.25 vpr 65.29 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30212 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66852 32 32 376 318 1 253 85 17 17 289 -1 unnamed_device 25.6 MiB 0.30 2503 1284 12919 4933 5948 2038 65.3 MiB 0.07 0.00 5.63182 4.45298 -163.199 -4.45298 4.45298 0.25 0.000344204 0.000305634 0.0255725 0.0233133 -1 -1 -1 -1 36 3534 41 6.99608e+06 309029 648988. 2245.63 6.45 0.227881 0.19988 26050 158493 -1 2786 22 2693 3443 310767 66326 4.37485 4.37485 -164.891 -4.37485 0 0 828058. 2865.25 0.03 0.07 0.17 -1 -1 0.03 0.0187806 0.0168388 105 96 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_121.v common 3.52 vpr 65.28 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 360 293 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.25 2367 1051 11247 3952 5722 1573 65.3 MiB 0.05 0.00 4.26889 3.47593 -117.199 -3.47593 3.47593 0.26 0.000336143 0.000306239 0.022991 0.021056 -1 -1 -1 -1 44 2721 42 6.99608e+06 294314 787024. 2723.27 1.71 0.152173 0.133648 27778 195446 -1 1977 21 1581 2145 160989 36030 3.25147 3.25147 -116.771 -3.25147 0 0 997811. 3452.63 0.05 0.07 0.16 -1 -1 0.05 0.0257259 0.0230873 93 60 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_122.v common 9.91 vpr 65.45 MiB -1 -1 0.13 17840 1 0.03 -1 -1 29812 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67020 32 32 396 299 1 231 85 17 17 289 -1 unnamed_device 26.0 MiB 0.30 2469 1280 14965 4476 8929 1560 65.4 MiB 0.08 0.00 6.28253 5.57594 -163.801 -5.57594 5.57594 0.25 0.000370225 0.000338122 0.0321979 0.0295165 -1 -1 -1 -1 38 3513 25 6.99608e+06 309029 678818. 2348.85 8.19 0.201075 0.176852 26626 170182 -1 2951 22 2194 3313 270278 56814 5.12565 5.12565 -169.601 -5.12565 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0204029 0.0183752 99 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_123.v common 2.18 vpr 64.52 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29792 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 30 32 224 207 1 134 75 17 17 289 -1 unnamed_device 24.9 MiB 0.24 1623 599 8449 2065 6066 318 64.5 MiB 0.04 0.00 2.83666 2.33546 -84.6639 -2.33546 2.33546 0.25 0.000555342 0.00051864 0.0194883 0.0180519 -1 -1 -1 -1 34 1695 48 6.99608e+06 191304 618332. 2139.56 0.65 0.0682305 0.0598421 25762 151098 -1 1398 20 868 1102 100646 25554 2.33678 2.33678 -94.189 -2.33678 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0115737 0.0102789 52 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_124.v common 2.81 vpr 64.67 MiB -1 -1 0.13 17676 1 0.02 -1 -1 29812 -1 -1 15 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 30 32 286 239 1 159 77 17 17 289 -1 unnamed_device 24.9 MiB 0.91 1725 902 8879 3004 4356 1519 64.7 MiB 0.04 0.00 4.10447 3.92803 -130.612 -3.92803 3.92803 0.24 0.000281139 0.000257365 0.0174054 0.0159733 -1 -1 -1 -1 34 2176 27 6.99608e+06 220735 618332. 2139.56 0.56 0.068423 0.0600819 25762 151098 -1 1899 22 1246 1955 169232 36091 3.59731 3.59731 -136.68 -3.59731 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0152632 0.0136748 70 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_125.v common 3.35 vpr 64.34 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29168 -1 -1 15 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 296 247 1 182 79 17 17 289 -1 unnamed_device 25.2 MiB 0.20 1971 882 13261 5570 7431 260 64.3 MiB 0.09 0.00 4.19149 3.78235 -133.321 -3.78235 3.78235 0.29 0.000445199 0.000403688 0.0373451 0.0341953 -1 -1 -1 -1 38 2651 49 6.99608e+06 220735 678818. 2348.85 1.75 0.126489 0.111927 26626 170182 -1 2020 20 1450 2457 219315 48983 3.62081 3.62081 -134.809 -3.62081 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0146507 0.0131502 74 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_126.v common 2.16 vpr 64.50 MiB -1 -1 0.14 18056 1 0.02 -1 -1 29884 -1 -1 19 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 25 32 216 194 1 134 76 17 17 289 -1 unnamed_device 25.0 MiB 0.25 1590 696 11596 3751 6795 1050 64.5 MiB 0.04 0.00 4.10053 3.35753 -84.3952 -3.35753 3.35753 0.25 0.000220573 0.000201876 0.0175116 0.016058 -1 -1 -1 -1 36 1574 20 6.99608e+06 279598 648988. 2245.63 0.51 0.054351 0.0477519 26050 158493 -1 1398 21 929 1335 101544 22940 3.09097 3.09097 -90.8946 -3.09097 0 0 828058. 2865.25 0.04 0.04 0.08 -1 -1 0.04 0.0146461 0.0129751 57 29 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_127.v common 2.88 vpr 65.38 MiB -1 -1 0.13 17528 1 0.04 -1 -1 30176 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66952 32 32 376 307 1 230 83 17 17 289 -1 unnamed_device 25.6 MiB 0.45 2657 1316 7463 1720 5150 593 65.4 MiB 0.05 0.00 4.40039 3.97548 -133.176 -3.97548 3.97548 0.25 0.000350248 0.000315913 0.016928 0.0155579 -1 -1 -1 -1 38 3462 44 6.99608e+06 279598 678818. 2348.85 1.00 0.108019 0.0954574 26626 170182 -1 2797 24 2179 3377 250295 53465 4.20392 4.20392 -145.444 -4.20392 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0211822 0.0189813 99 72 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_128.v common 4.42 vpr 65.54 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29820 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67112 31 32 409 331 1 257 86 17 17 289 -1 unnamed_device 25.6 MiB 0.29 3057 1328 14639 4861 7943 1835 65.5 MiB 0.08 0.00 5.90204 4.55497 -151.39 -4.55497 4.55497 0.25 0.00036635 0.000334698 0.0308268 0.0282486 -1 -1 -1 -1 42 3264 47 6.99608e+06 338461 744469. 2576.02 2.69 0.236746 0.209256 27202 183097 -1 2636 21 2145 2960 233871 50459 3.92175 3.92175 -144.746 -3.92175 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0203923 0.0184184 114 90 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_001.v common 4.41 vpr 64.49 MiB -1 -1 0.19 18436 14 0.23 -1 -1 32268 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 277 309 1 196 84 17 17 289 -1 unnamed_device 24.9 MiB 0.78 3031 1205 13626 4599 7190 1837 64.5 MiB 0.16 0.00 11.4241 8.56631 -174.636 -8.56631 8.56631 0.24 0.00119097 0.00110789 0.0820653 0.0761529 -1 -1 -1 -1 40 2941 23 6.79088e+06 269440 706193. 2443.58 1.87 0.27365 0.243248 26254 175826 -1 2711 18 1428 4274 219784 51179 7.12477 7.12477 -158.977 -7.12477 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0219342 0.0199651 135 183 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_002.v common 3.93 vpr 64.29 MiB -1 -1 0.18 18440 14 0.33 -1 -1 32040 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65832 30 32 272 304 1 199 83 17 17 289 -1 unnamed_device 25.1 MiB 0.45 2323 1121 7283 1658 4725 900 64.3 MiB 0.06 0.00 9.21432 7.55348 -154.172 -7.55348 7.55348 0.25 0.000649361 0.00061241 0.0264904 0.0245894 -1 -1 -1 -1 38 2991 20 6.79088e+06 282912 678818. 2348.85 1.69 0.220787 0.195563 25966 169698 -1 2398 20 1400 3922 178800 44179 6.62003 6.62003 -146.847 -6.62003 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0235963 0.0214056 130 184 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_003.v common 3.30 vpr 64.28 MiB -1 -1 0.15 18052 11 0.20 -1 -1 32452 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65824 32 32 280 312 1 194 83 17 17 289 -1 unnamed_device 24.9 MiB 0.67 2611 1308 5483 1021 4219 243 64.3 MiB 0.05 0.00 9.0712 6.64585 -143.643 -6.64585 6.64585 0.27 0.000440044 0.000403629 0.0264756 0.0247267 -1 -1 -1 -1 32 4014 47 6.79088e+06 255968 586450. 2029.24 0.98 0.126559 0.113318 24814 144142 -1 2998 23 1611 5320 356143 96112 6.11518 6.11518 -146.285 -6.11518 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0310327 0.0279645 132 186 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_004.v common 5.13 vpr 64.30 MiB -1 -1 0.16 18284 12 0.37 -1 -1 32692 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 29 32 275 307 1 194 86 17 17 289 -1 unnamed_device 25.2 MiB 0.49 2342 1180 5189 1017 3857 315 64.3 MiB 0.04 0.00 9.35225 7.37182 -142.972 -7.37182 7.37182 0.26 0.00044831 0.00041197 0.0190445 0.0176998 -1 -1 -1 -1 32 3270 50 6.79088e+06 336800 586450. 2029.24 2.83 0.273476 0.241544 24814 144142 -1 2476 22 1379 3781 200348 47482 6.53383 6.53383 -138.939 -6.53383 0 0 744469. 2576.02 0.03 0.07 0.09 -1 -1 0.03 0.0330859 0.0298846 141 190 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_005.v common 6.99 vpr 63.98 MiB -1 -1 0.18 18436 13 0.24 -1 -1 32424 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65512 32 32 302 334 1 227 87 17 17 289 -1 unnamed_device 25.2 MiB 0.34 2826 1422 5847 1175 4382 290 64.0 MiB 0.05 0.00 10.4933 7.73127 -164.781 -7.73127 7.73127 0.24 0.000482411 0.000442208 0.0217472 0.0201042 -1 -1 -1 -1 36 3783 23 6.79088e+06 309856 648988. 2245.63 5.01 0.257872 0.227573 25390 158009 -1 3208 19 1670 4461 243005 57993 6.89412 6.89412 -162.383 -6.89412 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0245951 0.0223687 155 208 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_006.v common 3.67 vpr 64.34 MiB -1 -1 0.19 18436 13 0.23 -1 -1 32428 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 292 324 1 217 86 17 17 289 -1 unnamed_device 25.2 MiB 0.66 3136 1331 12560 3423 7370 1767 64.3 MiB 0.07 0.00 9.76013 7.28237 -154.711 -7.28237 7.28237 0.24 0.00046408 0.000424198 0.0337388 0.0309128 -1 -1 -1 -1 32 4210 42 6.79088e+06 296384 586450. 2029.24 1.27 0.132124 0.118043 24814 144142 -1 3323 21 1903 5560 319427 73380 6.75647 6.75647 -158.319 -6.75647 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0269225 0.024456 141 198 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_007.v common 2.75 vpr 64.39 MiB -1 -1 0.15 18052 12 0.17 -1 -1 32268 -1 -1 25 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 27 32 229 261 1 165 84 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1861 902 5757 1286 4119 352 64.4 MiB 0.03 0.00 8.53024 6.95672 -126.14 -6.95672 6.95672 0.25 0.000354372 0.000324783 0.013746 0.0126635 -1 -1 -1 -1 28 2519 27 6.79088e+06 336800 531479. 1839.03 1.09 0.120253 0.106175 23950 126010 -1 2066 18 1046 2497 128398 31899 5.82898 5.82898 -118.677 -5.82898 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0178246 0.0161843 109 150 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_008.v common 6.07 vpr 63.68 MiB -1 -1 0.16 17908 12 0.17 -1 -1 32412 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65212 31 32 229 261 1 181 82 17 17 289 -1 unnamed_device 24.1 MiB 0.28 2040 1181 5956 1284 4146 526 63.7 MiB 0.04 0.00 6.73834 6.21924 -138.39 -6.21924 6.21924 0.24 0.000362618 0.00032571 0.0141613 0.0129176 -1 -1 -1 -1 30 3719 48 6.79088e+06 255968 556674. 1926.21 4.29 0.201748 0.178617 24526 138013 -1 2630 18 1198 3419 188591 45425 5.43491 5.43491 -136.039 -5.43491 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0184844 0.0167371 110 138 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_009.v common 3.21 vpr 64.70 MiB -1 -1 0.15 17668 12 0.19 -1 -1 32372 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 31 32 235 267 1 189 83 17 17 289 -1 unnamed_device 24.9 MiB 0.25 2543 1227 8543 2270 5212 1061 64.7 MiB 0.05 0.00 8.6557 7.27148 -152.778 -7.27148 7.27148 0.24 0.000361802 0.000331237 0.0195722 0.0179241 -1 -1 -1 -1 40 2618 15 6.79088e+06 269440 706193. 2443.58 1.38 0.119766 0.105239 26254 175826 -1 2483 16 1033 2770 145853 34562 6.49468 6.49468 -148.795 -6.49468 0 0 926341. 3205.33 0.03 0.04 0.10 -1 -1 0.03 0.0170104 0.0154989 110 144 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_010.v common 2.55 vpr 64.77 MiB -1 -1 0.15 17668 13 0.17 -1 -1 32296 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 250 282 1 179 81 17 17 289 -1 unnamed_device 24.9 MiB 0.40 2565 1165 6206 1220 4462 524 64.8 MiB 0.04 0.00 10.5547 7.36881 -166.317 -7.36881 7.36881 0.24 0.000391536 0.000359231 0.016511 0.0152106 -1 -1 -1 -1 28 3160 27 6.79088e+06 229024 531479. 1839.03 0.64 0.0799198 0.0709347 23950 126010 -1 2659 17 1153 2882 165722 40410 6.36594 6.36594 -163.044 -6.36594 0 0 648988. 2245.63 0.03 0.06 0.07 -1 -1 0.03 0.0254959 0.022977 110 156 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_011.v common 3.94 vpr 64.14 MiB -1 -1 0.15 18060 12 0.16 -1 -1 32264 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 216 248 1 163 81 17 17 289 -1 unnamed_device 24.5 MiB 0.58 2068 857 10756 4429 6016 311 64.1 MiB 0.05 0.00 8.56921 6.97458 -139.004 -6.97458 6.97458 0.24 0.000343467 0.000307099 0.0234334 0.0214136 -1 -1 -1 -1 38 2181 21 6.79088e+06 255968 678818. 2348.85 1.84 0.135883 0.119614 25966 169698 -1 1757 15 890 2413 117726 29155 5.82898 5.82898 -125.97 -5.82898 0 0 902133. 3121.57 0.03 0.04 0.09 -1 -1 0.03 0.0154421 0.0141457 101 128 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_012.v common 3.54 vpr 64.31 MiB -1 -1 0.26 18056 12 0.13 -1 -1 32112 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 236 268 1 168 82 17 17 289 -1 unnamed_device 24.5 MiB 0.35 2572 1214 8982 2331 5744 907 64.3 MiB 0.05 0.00 8.22306 6.49083 -156.629 -6.49083 6.49083 0.24 0.000363246 0.000331103 0.0206227 0.0189085 -1 -1 -1 -1 36 2644 29 6.79088e+06 242496 648988. 2245.63 1.41 0.132842 0.116763 25390 158009 -1 2417 16 966 2757 155170 36040 6.09296 6.09296 -155.583 -6.09296 0 0 828058. 2865.25 0.05 0.07 0.15 -1 -1 0.05 0.0296218 0.0271121 104 142 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_013.v common 4.32 vpr 64.31 MiB -1 -1 0.17 18440 13 0.25 -1 -1 32384 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 283 315 1 215 84 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2835 1334 6489 1499 4360 630 64.3 MiB 0.04 0.00 11.6534 8.17439 -174.342 -8.17439 8.17439 0.25 0.000438675 0.000401184 0.0187568 0.0172093 -1 -1 -1 -1 32 3619 35 6.79088e+06 269440 586450. 2029.24 2.19 0.200192 0.177548 24814 144142 -1 3033 18 1340 3636 199882 46955 7.21431 7.21431 -168.629 -7.21431 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0230824 0.0210502 133 189 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_014.v common 5.12 vpr 65.04 MiB -1 -1 0.18 18440 14 0.28 -1 -1 32424 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 32 32 303 335 1 227 86 17 17 289 -1 unnamed_device 25.2 MiB 0.69 3489 1455 10292 2847 6856 589 65.0 MiB 0.07 0.00 11.4534 8.74059 -185.972 -8.74059 8.74059 0.25 0.000488456 0.000447227 0.0303164 0.0277935 -1 -1 -1 -1 40 3374 27 6.79088e+06 296384 706193. 2443.58 2.50 0.277905 0.246685 26254 175826 -1 3075 32 1530 4441 421130 190943 7.41807 7.41807 -171.541 -7.41807 0 0 926341. 3205.33 0.03 0.17 0.10 -1 -1 0.03 0.0436618 0.0390518 156 209 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_015.v common 3.18 vpr 64.39 MiB -1 -1 0.25 18056 11 0.15 -1 -1 32288 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 29 32 225 257 1 169 84 17 17 289 -1 unnamed_device 24.7 MiB 0.34 2298 1064 6855 1570 4646 639 64.4 MiB 0.04 0.00 8.40469 6.70263 -132.295 -6.70263 6.70263 0.25 0.000348348 0.000318449 0.0154087 0.0141195 -1 -1 -1 -1 30 2425 21 6.79088e+06 309856 556674. 1926.21 1.15 0.119115 0.105149 24526 138013 -1 2231 17 985 2602 130423 31578 5.86469 5.86469 -127.664 -5.86469 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0175344 0.0160361 108 140 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_016.v common 5.96 vpr 65.10 MiB -1 -1 0.19 18436 12 0.24 -1 -1 32692 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 32 32 301 333 1 219 91 17 17 289 -1 unnamed_device 25.2 MiB 0.74 2958 1459 10087 2738 6560 789 65.1 MiB 0.06 0.00 9.40585 7.27585 -159.598 -7.27585 7.27585 0.24 0.000475027 0.000434934 0.0268074 0.0244932 -1 -1 -1 -1 32 4260 32 6.79088e+06 363744 586450. 2029.24 3.49 0.246475 0.218856 24814 144142 -1 3465 23 1720 5638 455130 145122 6.73753 6.73753 -163.315 -6.73753 0 0 744469. 2576.02 0.03 0.12 0.08 -1 -1 0.03 0.0287396 0.026003 152 207 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_017.v common 3.79 vpr 64.29 MiB -1 -1 0.17 18440 14 0.22 -1 -1 32384 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 277 309 1 212 86 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2850 1312 6890 1429 5359 102 64.3 MiB 0.05 0.00 10.5304 7.97872 -168.371 -7.97872 7.97872 0.25 0.000606839 0.000536353 0.0197275 0.018177 -1 -1 -1 -1 36 3500 42 6.79088e+06 296384 648988. 2245.63 1.53 0.148978 0.131812 25390 158009 -1 2790 18 1406 4143 221995 51462 7.21088 7.21088 -159.551 -7.21088 0 0 828058. 2865.25 0.03 0.06 0.09 -1 -1 0.03 0.0218356 0.0197917 131 183 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_018.v common 3.27 vpr 64.32 MiB -1 -1 0.15 18052 12 0.14 -1 -1 31972 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 32 32 227 259 1 171 82 17 17 289 -1 unnamed_device 24.5 MiB 0.54 2494 1086 7736 1808 5543 385 64.3 MiB 0.04 0.00 8.77612 6.78318 -155.712 -6.78318 6.78318 0.25 0.000354223 0.000323322 0.018174 0.0166131 -1 -1 -1 -1 30 2715 18 6.79088e+06 242496 556674. 1926.21 1.25 0.12632 0.111156 24526 138013 -1 2226 14 889 2523 130718 31522 5.88818 5.88818 -146.658 -5.88818 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0162673 0.0148851 108 133 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_019.v common 2.55 vpr 64.02 MiB -1 -1 0.14 17908 10 0.10 -1 -1 32064 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65556 30 32 175 207 1 131 75 17 17 289 -1 unnamed_device 24.9 MiB 0.22 1668 806 10503 2849 6815 839 64.0 MiB 0.05 0.00 6.26916 4.98721 -124.709 -4.98721 4.98721 0.26 0.000478461 0.000454715 0.023872 0.02204 -1 -1 -1 -1 32 1826 25 6.79088e+06 175136 586450. 2029.24 0.94 0.0901868 0.0792017 24814 144142 -1 1616 13 591 1361 77271 18739 4.34281 4.34281 -119.196 -4.34281 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0113524 0.0103305 65 87 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_020.v common 3.03 vpr 63.89 MiB -1 -1 0.16 18052 13 0.16 -1 -1 32244 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65428 31 32 231 263 1 178 83 17 17 289 -1 unnamed_device 24.5 MiB 0.50 2365 1084 11783 3551 6465 1767 63.9 MiB 0.06 0.00 8.87866 7.49722 -158.804 -7.49722 7.49722 0.25 0.000362742 0.000331666 0.0270047 0.0247456 -1 -1 -1 -1 28 3316 28 6.79088e+06 269440 531479. 1839.03 0.98 0.0892173 0.0800554 23950 126010 -1 2618 16 1153 2704 167677 39802 6.33372 6.33372 -153.752 -6.33372 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0199065 0.0183664 109 140 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_021.v common 3.60 vpr 64.00 MiB -1 -1 0.21 18440 13 0.32 -1 -1 33084 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65536 32 32 304 336 1 215 87 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2586 1376 10839 2728 7031 1080 64.0 MiB 0.09 0.00 8.96492 7.91997 -166.691 -7.91997 7.91997 0.25 0.000464279 0.000424653 0.0425461 0.0392674 -1 -1 -1 -1 34 3753 44 6.79088e+06 309856 618332. 2139.56 1.41 0.199259 0.177438 25102 150614 -1 3173 21 1808 5062 277517 63992 7.25767 7.25767 -167.443 -7.25767 0 0 787024. 2723.27 0.03 0.08 0.08 -1 -1 0.03 0.029666 0.0271387 145 210 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_022.v common 5.06 vpr 64.92 MiB -1 -1 0.24 18440 13 0.26 -1 -1 32316 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 32 32 288 320 1 216 86 17 17 289 -1 unnamed_device 25.0 MiB 0.54 3098 1371 8969 2158 5992 819 64.9 MiB 0.06 0.00 10.2409 8.00961 -172.114 -8.00961 8.00961 0.25 0.000455242 0.000416838 0.0273004 0.025115 -1 -1 -1 -1 48 3044 22 6.79088e+06 296384 865456. 2994.66 2.49 0.280748 0.25145 27694 206865 -1 2693 35 1210 3789 333870 151059 6.84611 6.84611 -157.334 -6.84611 0 0 1.05005e+06 3633.38 0.05 0.14 0.20 -1 -1 0.05 0.0416726 0.0377162 144 194 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_023.v common 2.67 vpr 63.91 MiB -1 -1 0.15 17672 9 0.07 -1 -1 32016 -1 -1 19 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65448 26 32 152 184 1 121 77 17 17 289 -1 unnamed_device 24.5 MiB 0.19 1488 617 5782 1436 3916 430 63.9 MiB 0.03 0.00 6.09263 4.97145 -92.9358 -4.97145 4.97145 0.24 0.000244262 0.000223535 0.0101216 0.00930478 -1 -1 -1 -1 26 1806 27 6.79088e+06 255968 503264. 1741.40 1.15 0.100936 0.0879412 23662 119890 -1 1410 16 621 1418 72154 18823 4.40201 4.40201 -92.9496 -4.40201 0 0 618332. 2139.56 0.02 0.03 0.06 -1 -1 0.02 0.01089 0.00983063 70 76 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_024.v common 10.31 vpr 64.41 MiB -1 -1 0.16 18052 13 0.31 -1 -1 32380 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 287 319 1 211 88 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2866 1367 5353 1032 4119 202 64.4 MiB 0.04 0.00 10.0962 7.88173 -161.78 -7.88173 7.88173 0.25 0.000449381 0.000411785 0.015309 0.0141099 -1 -1 -1 -1 38 3405 34 6.79088e+06 323328 678818. 2348.85 8.08 0.267815 0.236873 25966 169698 -1 2807 21 1639 4697 237671 55346 7.00707 7.00707 -156.558 -7.00707 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0252728 0.0228831 137 193 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_025.v common 3.06 vpr 63.40 MiB -1 -1 0.11 17668 8 0.07 -1 -1 32008 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64924 32 32 154 186 1 122 81 17 17 289 -1 unnamed_device 24.1 MiB 0.21 1801 751 10056 3801 5079 1176 63.4 MiB 0.04 0.00 5.37538 4.0417 -97.2106 -4.0417 4.0417 0.25 0.000246317 0.000224443 0.0162963 0.0149155 -1 -1 -1 -1 28 2037 20 6.79088e+06 229024 531479. 1839.03 1.53 0.0849702 0.074266 23950 126010 -1 1607 16 643 1316 83382 21230 3.71266 3.71266 -99.3645 -3.71266 0 0 648988. 2245.63 0.02 0.03 0.07 -1 -1 0.02 0.0106624 0.00961875 64 60 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_026.v common 5.45 vpr 64.21 MiB -1 -1 0.30 18056 15 0.21 -1 -1 32388 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65752 32 32 254 286 1 199 85 17 17 289 -1 unnamed_device 24.9 MiB 0.57 2483 1240 9943 2138 6866 939 64.2 MiB 0.06 0.00 9.80857 8.30542 -172.111 -8.30542 8.30542 0.24 0.000413589 0.000379237 0.0245435 0.0225401 -1 -1 -1 -1 30 3906 37 6.79088e+06 282912 556674. 1926.21 3.13 0.211236 0.18686 24526 138013 -1 2898 17 1285 3527 205171 47925 7.42577 7.42577 -170.534 -7.42577 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0194069 0.0176652 125 160 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_027.v common 5.76 vpr 64.77 MiB -1 -1 0.24 18436 13 0.26 -1 -1 32408 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 32 32 260 292 1 195 85 17 17 289 -1 unnamed_device 24.9 MiB 0.59 2809 1235 6223 1362 4311 550 64.8 MiB 0.04 0.00 9.72987 7.14037 -153.834 -7.14037 7.14037 0.25 0.000409309 0.00037536 0.0166027 0.015261 -1 -1 -1 -1 28 3847 37 6.79088e+06 282912 531479. 1839.03 3.35 0.189471 0.167684 23950 126010 -1 3140 18 1510 4391 259846 62056 6.54163 6.54163 -159.303 -6.54163 0 0 648988. 2245.63 0.02 0.07 0.10 -1 -1 0.02 0.0221816 0.0201556 121 166 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_028.v common 3.24 vpr 64.31 MiB -1 -1 0.16 18440 13 0.24 -1 -1 32460 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 279 311 1 197 86 17 17 289 -1 unnamed_device 25.3 MiB 0.42 3092 1312 10670 2502 6881 1287 64.3 MiB 0.06 0.00 10.7137 7.55772 -167.165 -7.55772 7.55772 0.25 0.000496424 0.000437606 0.0278823 0.0255608 -1 -1 -1 -1 34 3511 26 6.79088e+06 296384 618332. 2139.56 1.12 0.149524 0.132934 25102 150614 -1 3012 26 1394 4168 319805 117147 6.53742 6.53742 -161.936 -6.53742 0 0 787024. 2723.27 0.03 0.11 0.08 -1 -1 0.03 0.0306397 0.0275996 137 185 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_029.v common 4.78 vpr 64.34 MiB -1 -1 0.21 18048 12 0.14 -1 -1 32216 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65884 32 32 238 270 1 179 83 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2215 1077 7463 1926 5127 410 64.3 MiB 0.04 0.00 8.90447 7.16817 -157.085 -7.16817 7.16817 0.24 0.000360981 0.000329659 0.0183015 0.016781 -1 -1 -1 -1 30 2953 38 6.79088e+06 255968 556674. 1926.21 2.72 0.213179 0.189075 24526 138013 -1 2363 15 977 2427 125582 30236 6.04043 6.04043 -146.514 -6.04043 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0233315 0.0211966 106 144 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_030.v common 2.66 vpr 63.57 MiB -1 -1 0.15 18056 11 0.13 -1 -1 32052 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65092 30 32 213 245 1 164 83 17 17 289 -1 unnamed_device 24.2 MiB 0.54 2157 906 8903 2145 5507 1251 63.6 MiB 0.05 0.00 8.36704 6.05468 -133.402 -6.05468 6.05468 0.26 0.000335989 0.00030755 0.0246192 0.02286 -1 -1 -1 -1 30 2680 33 6.79088e+06 282912 556674. 1926.21 0.66 0.0826156 0.0734008 24526 138013 -1 2099 20 1066 2662 146556 35824 5.18426 5.18426 -128.437 -5.18426 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0169118 0.0152834 98 125 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_031.v common 2.87 vpr 64.38 MiB -1 -1 0.15 18056 11 0.15 -1 -1 32252 -1 -1 22 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 28 32 227 259 1 169 82 17 17 289 -1 unnamed_device 24.9 MiB 0.19 2381 1026 10050 2724 5924 1402 64.4 MiB 0.05 0.00 8.60731 6.75879 -129.565 -6.75879 6.75879 0.24 0.000355493 0.000325819 0.0222164 0.0203714 -1 -1 -1 -1 32 2423 27 6.79088e+06 296384 586450. 2029.24 1.21 0.137782 0.121045 24814 144142 -1 2131 17 976 2549 133309 32630 5.82893 5.82893 -125.134 -5.82893 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0170262 0.0153374 110 145 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_032.v common 3.22 vpr 64.91 MiB -1 -1 0.14 18052 12 0.23 -1 -1 32352 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 274 306 1 205 88 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2875 1212 13153 3436 7680 2037 64.9 MiB 0.07 0.00 9.54873 6.775 -163.89 -6.775 6.775 0.25 0.000426219 0.000390708 0.0317792 0.0291933 -1 -1 -1 -1 38 3105 28 6.79088e+06 323328 678818. 2348.85 1.00 0.14567 0.129269 25966 169698 -1 2513 19 1288 3419 170230 41113 6.11529 6.11529 -157.306 -6.11529 0 0 902133. 3121.57 0.03 0.05 0.13 -1 -1 0.03 0.0220122 0.0199881 127 180 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_033.v common 2.77 vpr 64.30 MiB -1 -1 0.17 18056 12 0.14 -1 -1 32240 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 31 32 237 269 1 170 84 17 17 289 -1 unnamed_device 24.9 MiB 0.57 2060 1002 6672 1433 5012 227 64.3 MiB 0.04 0.00 7.92332 6.92092 -140.498 -6.92092 6.92092 0.24 0.000365858 0.000335237 0.0155583 0.0142796 -1 -1 -1 -1 34 2714 22 6.79088e+06 282912 618332. 2139.56 0.66 0.0804347 0.070896 25102 150614 -1 2212 17 1038 2779 151082 36854 5.83236 5.83236 -136.839 -5.83236 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0169749 0.0153974 103 146 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_034.v common 4.42 vpr 64.34 MiB -1 -1 0.15 18056 10 0.18 -1 -1 32228 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 29 32 220 252 1 166 80 17 17 289 -1 unnamed_device 24.5 MiB 0.38 2498 1114 12464 4239 6338 1887 64.3 MiB 0.08 0.00 8.45663 5.89864 -127.83 -5.89864 5.89864 0.27 0.000350178 0.000319832 0.0386761 0.0358483 -1 -1 -1 -1 30 2868 39 6.79088e+06 255968 556674. 1926.21 2.44 0.157288 0.139573 24526 138013 -1 2191 15 1009 2745 133799 31948 5.07353 5.07353 -121.877 -5.07353 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0187168 0.0170958 106 135 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_035.v common 4.31 vpr 65.09 MiB -1 -1 0.17 18824 13 0.37 -1 -1 32496 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 32 32 315 347 1 231 87 17 17 289 -1 unnamed_device 25.6 MiB 0.82 3406 1501 8151 1916 5443 792 65.1 MiB 0.06 0.00 10.5847 8.3634 -174.549 -8.3634 8.3634 0.25 0.000512226 0.000469738 0.0256547 0.0235679 -1 -1 -1 -1 34 4177 45 6.79088e+06 309856 618332. 2139.56 1.60 0.155047 0.138288 25102 150614 -1 3221 19 1668 4722 270668 63068 7.30036 7.30036 -169.537 -7.30036 0 0 787024. 2723.27 0.03 0.07 0.09 -1 -1 0.03 0.0268631 0.0244829 155 221 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_036.v common 6.21 vpr 64.89 MiB -1 -1 0.17 18680 14 0.29 -1 -1 32488 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66444 32 32 282 314 1 220 85 17 17 289 -1 unnamed_device 25.2 MiB 0.69 2943 1394 7711 1611 5817 283 64.9 MiB 0.05 0.00 10.4967 7.87598 -171.941 -7.87598 7.87598 0.26 0.000454747 0.000412271 0.021847 0.0200618 -1 -1 -1 -1 32 4122 48 6.79088e+06 282912 586450. 2029.24 3.80 0.264087 0.233687 24814 144142 -1 3384 26 1590 4354 315532 91570 6.90989 6.90989 -166.802 -6.90989 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0278672 0.0250781 141 188 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_037.v common 3.47 vpr 64.29 MiB -1 -1 0.27 18048 12 0.18 -1 -1 31904 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 31 32 241 273 1 167 85 17 17 289 -1 unnamed_device 24.9 MiB 0.81 2245 1124 11617 2830 7151 1636 64.3 MiB 0.06 0.00 9.13651 7.16673 -154.158 -7.16673 7.16673 0.24 0.000402222 0.000371053 0.0298095 0.027394 -1 -1 -1 -1 32 2540 25 6.79088e+06 296384 586450. 2029.24 0.75 0.104561 0.0929539 24814 144142 -1 2194 38 912 2526 247643 119222 6.40858 6.40858 -147.26 -6.40858 0 0 744469. 2576.02 0.03 0.11 0.08 -1 -1 0.03 0.0307068 0.027383 109 150 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_038.v common 4.79 vpr 64.44 MiB -1 -1 0.21 18440 12 0.24 -1 -1 32412 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 31 32 307 339 1 224 88 17 17 289 -1 unnamed_device 25.2 MiB 1.02 2945 1333 7108 1597 4418 1093 64.4 MiB 0.06 0.00 9.92626 7.46598 -153.742 -7.46598 7.46598 0.26 0.000482238 0.000434978 0.0278272 0.0257809 -1 -1 -1 -1 44 3306 50 6.79088e+06 336800 787024. 2723.27 2.00 0.23826 0.210092 27118 194962 -1 2867 17 1292 4003 228351 52035 6.84601 6.84601 -149.478 -6.84601 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0229471 0.0209391 149 216 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_039.v common 3.38 vpr 65.07 MiB -1 -1 0.21 18820 14 0.30 -1 -1 33008 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66632 31 32 293 325 1 210 87 17 17 289 -1 unnamed_device 25.2 MiB 0.62 2863 1260 7191 1526 5185 480 65.1 MiB 0.05 0.00 10.7622 8.34339 -164.83 -8.34339 8.34339 0.25 0.000461007 0.000422205 0.0206457 0.0189982 -1 -1 -1 -1 32 4175 47 6.79088e+06 323328 586450. 2029.24 0.99 0.128067 0.114334 24814 144142 -1 2958 17 1420 4068 211841 50823 7.27357 7.27357 -157.701 -7.27357 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0330715 0.026157 145 202 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_040.v common 3.88 vpr 64.86 MiB -1 -1 0.18 18824 13 0.23 -1 -1 32404 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 31 32 276 308 1 215 92 17 17 289 -1 unnamed_device 25.2 MiB 0.64 2522 1348 10856 2834 7113 909 64.9 MiB 0.06 0.00 9.47173 8.62453 -173.004 -8.62453 8.62453 0.29 0.000440966 0.000404379 0.0276626 0.025418 -1 -1 -1 -1 40 2987 28 6.79088e+06 390688 706193. 2443.58 1.54 0.191963 0.16863 26254 175826 -1 2731 15 1325 3511 178012 43029 7.1786 7.1786 -159.768 -7.1786 0 0 926341. 3205.33 0.03 0.05 0.11 -1 -1 0.03 0.0194924 0.0177471 141 185 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_041.v common 8.44 vpr 64.92 MiB -1 -1 0.18 18440 13 0.23 -1 -1 32424 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 31 32 269 301 1 202 87 17 17 289 -1 unnamed_device 25.2 MiB 0.42 2556 1153 5463 969 4379 115 64.9 MiB 0.04 0.00 9.98527 7.53333 -150.109 -7.53333 7.53333 0.24 0.000423469 0.000387405 0.0151339 0.0139092 -1 -1 -1 -1 38 3092 22 6.79088e+06 323328 678818. 2348.85 6.41 0.234781 0.206989 25966 169698 -1 2670 17 1343 3980 206829 49786 6.58427 6.58427 -142.162 -6.58427 0 0 902133. 3121.57 0.03 0.05 0.09 -1 -1 0.03 0.0206137 0.0188038 132 178 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_042.v common 3.53 vpr 64.59 MiB -1 -1 0.15 18056 12 0.16 -1 -1 32384 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 264 296 1 184 83 17 17 289 -1 unnamed_device 24.6 MiB 0.54 2002 1172 9083 2391 5419 1273 64.6 MiB 0.05 0.00 8.49442 7.30279 -160.079 -7.30279 7.30279 0.25 0.000425324 0.000390776 0.0256692 0.0237463 -1 -1 -1 -1 32 3059 44 6.79088e+06 255968 586450. 2029.24 1.35 0.163263 0.143696 24814 144142 -1 2506 18 1001 2650 149679 35783 6.24413 6.24413 -151.681 -6.24413 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0197901 0.0179497 117 170 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_043.v common 4.74 vpr 64.55 MiB -1 -1 0.35 19212 14 0.36 -1 -1 32704 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 324 356 1 233 89 17 17 289 -1 unnamed_device 25.2 MiB 0.53 2721 1387 9593 2160 6158 1275 64.6 MiB 0.06 0.00 10.2498 8.60377 -176.638 -8.60377 8.60377 0.36 0.000519234 0.000475246 0.0287265 0.0263298 -1 -1 -1 -1 42 3697 28 6.79088e+06 336800 744469. 2576.02 2.10 0.220451 0.19538 26542 182613 -1 3213 16 1508 4554 251372 60167 7.8443 7.8443 -173.087 -7.8443 0 0 949917. 3286.91 0.03 0.06 0.10 -1 -1 0.03 0.0253925 0.0232663 166 230 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_044.v common 3.17 vpr 64.68 MiB -1 -1 0.16 18052 11 0.17 -1 -1 32184 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66236 31 32 249 281 1 182 81 17 17 289 -1 unnamed_device 24.9 MiB 0.36 2383 1234 8831 2136 5283 1412 64.7 MiB 0.06 0.00 9.03977 6.55167 -143.832 -6.55167 6.55167 0.26 0.000390614 0.000357326 0.0306504 0.0284119 -1 -1 -1 -1 34 3424 26 6.79088e+06 242496 618332. 2139.56 1.28 0.149155 0.132617 25102 150614 -1 2799 17 1286 3775 224926 52311 5.53137 5.53137 -138.061 -5.53137 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0185385 0.0168386 116 158 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_045.v common 4.04 vpr 64.32 MiB -1 -1 0.18 18436 13 0.24 -1 -1 32404 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 31 32 284 316 1 189 83 17 17 289 -1 unnamed_device 25.2 MiB 0.59 2583 1227 7823 1987 5336 500 64.3 MiB 0.06 0.00 10.3304 8.2347 -167.362 -8.2347 8.2347 0.25 0.00107463 0.00100212 0.0242496 0.0222372 -1 -1 -1 -1 38 3089 31 6.79088e+06 269440 678818. 2348.85 1.79 0.182563 0.160756 25966 169698 -1 2457 17 1102 3538 183777 43994 6.928 6.928 -151.92 -6.928 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0229341 0.020939 137 193 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_046.v common 5.85 vpr 64.33 MiB -1 -1 0.20 18440 12 0.23 -1 -1 32476 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 303 335 1 211 88 17 17 289 -1 unnamed_device 25.2 MiB 0.72 3276 1368 7303 1652 5036 615 64.3 MiB 0.05 0.00 9.50649 7.04019 -156.99 -7.04019 7.04019 0.28 0.000485597 0.000444829 0.0239096 0.0220685 -1 -1 -1 -1 32 4045 46 6.79088e+06 323328 586450. 2029.24 3.39 0.250211 0.22096 24814 144142 -1 3137 20 1473 4574 259310 60569 6.07958 6.07958 -153.718 -6.07958 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0247197 0.0224238 149 209 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_047.v common 4.57 vpr 64.27 MiB -1 -1 0.19 18432 13 0.33 -1 -1 32428 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 32 32 272 304 1 193 84 17 17 289 -1 unnamed_device 25.2 MiB 1.10 2365 1209 7587 1894 5178 515 64.3 MiB 0.05 0.00 9.74801 7.69207 -163.114 -7.69207 7.69207 0.26 0.000440032 0.000395698 0.0215181 0.0197213 -1 -1 -1 -1 30 3206 26 6.79088e+06 269440 556674. 1926.21 1.49 0.177988 0.157193 24526 138013 -1 2685 19 1329 3576 180486 43057 6.58083 6.58083 -156.048 -6.58083 0 0 706193. 2443.58 0.03 0.06 0.07 -1 -1 0.03 0.0268247 0.0243982 129 178 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_048.v common 4.15 vpr 64.91 MiB -1 -1 0.17 18436 13 0.29 -1 -1 32272 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 271 303 1 208 84 17 17 289 -1 unnamed_device 24.9 MiB 0.36 3179 1230 9417 2549 6214 654 64.9 MiB 0.06 0.00 12.3503 7.56546 -162.927 -7.56546 7.56546 0.24 0.000419777 0.000383264 0.0245488 0.0224769 -1 -1 -1 -1 34 3342 25 6.79088e+06 269440 618332. 2139.56 1.96 0.222507 0.197685 25102 150614 -1 2749 20 1287 3531 194100 46258 6.63461 6.63461 -153.875 -6.63461 0 0 787024. 2723.27 0.03 0.06 0.09 -1 -1 0.03 0.0229001 0.0207611 126 177 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_049.v common 4.41 vpr 64.33 MiB -1 -1 0.29 18440 12 0.22 -1 -1 32072 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 288 320 1 213 85 17 17 289 -1 unnamed_device 25.2 MiB 0.73 3237 1350 6781 1616 4569 596 64.3 MiB 0.05 0.00 9.79309 7.26885 -157.003 -7.26885 7.26885 0.29 0.000453889 0.000415087 0.0228808 0.0209913 -1 -1 -1 -1 36 3641 25 6.79088e+06 282912 648988. 2245.63 1.83 0.204078 0.18037 25390 158009 -1 3026 21 1415 4844 275624 62278 6.33013 6.33013 -152.464 -6.33013 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.0264261 0.0237997 143 194 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_050.v common 3.94 vpr 65.12 MiB -1 -1 0.18 18824 13 0.26 -1 -1 33052 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 306 338 1 225 90 17 17 289 -1 unnamed_device 25.2 MiB 0.43 2993 1412 5718 1172 4154 392 65.1 MiB 0.05 0.00 9.84216 7.93745 -169.253 -7.93745 7.93745 0.26 0.000506572 0.000441632 0.0199996 0.0184984 -1 -1 -1 -1 34 3731 24 6.79088e+06 350272 618332. 2139.56 1.65 0.183595 0.164168 25102 150614 -1 3234 20 1610 4700 250750 58995 6.64794 6.64794 -157.372 -6.64794 0 0 787024. 2723.27 0.03 0.07 0.09 -1 -1 0.03 0.0260849 0.023678 154 212 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_051.v common 4.60 vpr 64.25 MiB -1 -1 0.15 18296 14 0.25 -1 -1 32688 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 262 294 1 194 83 17 17 289 -1 unnamed_device 24.9 MiB 0.48 2657 1180 4583 839 3547 197 64.2 MiB 0.03 0.00 10.6221 8.57741 -169.869 -8.57741 8.57741 0.25 0.000429716 0.000393141 0.0139303 0.012808 -1 -1 -1 -1 28 3338 31 6.79088e+06 255968 531479. 1839.03 2.48 0.181889 0.160377 23950 126010 -1 2914 20 1463 4240 240521 57665 7.62947 7.62947 -166.279 -7.62947 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.022302 0.0202324 126 168 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_052.v common 3.72 vpr 65.03 MiB -1 -1 0.28 18440 13 0.29 -1 -1 32388 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 32 32 291 323 1 211 86 17 17 289 -1 unnamed_device 25.6 MiB 0.57 2869 1258 10481 2943 5987 1551 65.0 MiB 0.07 0.00 10.9668 8.37706 -166.957 -8.37706 8.37706 0.26 0.000452579 0.00041402 0.0351629 0.0326495 -1 -1 -1 -1 32 3983 34 6.79088e+06 296384 586450. 2029.24 1.24 0.15596 0.139386 24814 144142 -1 3104 18 1493 4014 248833 58652 7.1394 7.1394 -164.599 -7.1394 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0277841 0.0252849 141 197 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_053.v common 5.22 vpr 63.88 MiB -1 -1 0.22 18436 13 0.32 -1 -1 32356 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65408 31 32 302 334 1 219 90 17 17 289 -1 unnamed_device 25.2 MiB 0.71 2984 1375 7929 1755 5579 595 63.9 MiB 0.05 0.00 10.6879 7.80965 -168.49 -7.80965 7.80965 0.26 0.000508235 0.000468038 0.0234246 0.0216387 -1 -1 -1 -1 44 3117 28 6.79088e+06 363744 787024. 2723.27 2.60 0.247217 0.219943 27118 194962 -1 2818 25 1372 3980 318440 129638 6.99593 6.99593 -160.634 -6.99593 0 0 997811. 3452.63 0.04 0.11 0.10 -1 -1 0.04 0.0310593 0.0280909 152 211 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_054.v common 4.83 vpr 65.00 MiB -1 -1 0.31 18824 12 0.27 -1 -1 32268 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 32 32 308 340 1 222 92 17 17 289 -1 unnamed_device 25.6 MiB 0.41 3144 1337 10649 2743 7103 803 65.0 MiB 0.07 0.00 10.1967 7.58252 -163.027 -7.58252 7.58252 0.25 0.000490837 0.000443114 0.0319269 0.0295168 -1 -1 -1 -1 40 3178 19 6.79088e+06 377216 706193. 2443.58 2.41 0.251239 0.223458 26254 175826 -1 3008 22 1701 4827 258713 61668 6.50587 6.50587 -155.351 -6.50587 0 0 926341. 3205.33 0.05 0.11 0.09 -1 -1 0.05 0.0451514 0.0407572 156 214 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_055.v common 2.48 vpr 63.77 MiB -1 -1 0.22 18052 11 0.11 -1 -1 32232 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 32 32 216 248 1 163 81 17 17 289 -1 unnamed_device 24.5 MiB 0.16 2444 1016 13381 3505 8370 1506 63.8 MiB 0.06 0.00 8.71077 6.38377 -127.37 -6.38377 6.38377 0.25 0.000324322 0.000295525 0.0272651 0.0249364 -1 -1 -1 -1 30 2471 48 6.79088e+06 229024 556674. 1926.21 0.77 0.111758 0.0991533 24526 138013 -1 2018 16 855 2033 108403 26277 5.53907 5.53907 -126.438 -5.53907 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0151176 0.0137736 96 122 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_056.v common 3.03 vpr 64.83 MiB -1 -1 0.17 18440 13 0.19 -1 -1 31976 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66384 32 32 254 286 1 192 84 17 17 289 -1 unnamed_device 25.0 MiB 0.79 2200 1130 7953 1961 5244 748 64.8 MiB 0.06 0.00 9.12952 7.64382 -162.069 -7.64382 7.64382 0.26 0.000404932 0.00037113 0.0266925 0.0246854 -1 -1 -1 -1 32 3343 36 6.79088e+06 269440 586450. 2029.24 0.62 0.103698 0.0924632 24814 144142 -1 2509 20 1303 3343 181626 44818 6.83492 6.83492 -156.203 -6.83492 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0210802 0.0190009 117 160 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_057.v common 4.16 vpr 64.23 MiB -1 -1 0.19 19208 14 0.50 -1 -1 32596 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 338 370 1 249 88 17 17 289 -1 unnamed_device 25.6 MiB 0.55 3289 1631 6133 1207 4481 445 64.2 MiB 0.05 0.00 12.1157 8.85191 -183.37 -8.85191 8.85191 0.25 0.00052977 0.00048526 0.0246398 0.0227741 -1 -1 -1 -1 36 4433 25 6.79088e+06 323328 648988. 2245.63 1.60 0.198607 0.176942 25390 158009 -1 3727 23 2320 7287 414178 93236 7.92691 7.92691 -180.612 -7.92691 0 0 828058. 2865.25 0.03 0.09 0.08 -1 -1 0.03 0.0315216 0.0285437 178 244 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_058.v common 4.45 vpr 64.82 MiB -1 -1 0.16 18436 13 0.25 -1 -1 32520 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 271 303 1 213 87 17 17 289 -1 unnamed_device 25.2 MiB 0.41 2695 1357 7767 1632 5687 448 64.8 MiB 0.05 0.00 9.55819 7.43065 -172.005 -7.43065 7.43065 0.26 0.000453633 0.000416022 0.0206436 0.0188543 -1 -1 -1 -1 44 3224 37 6.79088e+06 309856 787024. 2723.27 2.25 0.249436 0.219598 27118 194962 -1 2850 17 1234 3473 205079 46010 6.76533 6.76533 -164.687 -6.76533 0 0 997811. 3452.63 0.06 0.09 0.14 -1 -1 0.06 0.0356138 0.032349 139 177 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_059.v common 5.16 vpr 63.62 MiB -1 -1 0.15 18056 11 0.15 -1 -1 32220 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65144 30 32 224 256 1 165 81 17 17 289 -1 unnamed_device 24.5 MiB 0.28 2111 998 6031 1372 4208 451 63.6 MiB 0.04 0.00 8.95732 6.57733 -140.708 -6.57733 6.57733 0.25 0.000361391 0.000331213 0.0187657 0.0173949 -1 -1 -1 -1 30 2897 39 6.79088e+06 255968 556674. 1926.21 3.36 0.147671 0.130734 24526 138013 -1 2204 19 1182 3397 176175 42450 5.70014 5.70014 -134.673 -5.70014 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0198801 0.0179249 103 136 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_060.v common 5.46 vpr 64.95 MiB -1 -1 0.22 19208 15 0.48 -1 -1 32792 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66504 32 32 351 383 1 253 89 17 17 289 -1 unnamed_device 25.2 MiB 0.71 3433 1562 7613 1907 5097 609 64.9 MiB 0.10 0.00 11.6801 9.39421 -191.348 -9.39421 9.39421 0.36 0.00106071 0.000968475 0.046627 0.0426776 -1 -1 -1 -1 42 3751 25 6.79088e+06 336800 744469. 2576.02 2.52 0.366544 0.326961 26542 182613 -1 3337 18 1749 5222 274844 63949 8.01666 8.01666 -177.783 -8.01666 0 0 949917. 3286.91 0.04 0.07 0.10 -1 -1 0.04 0.0297378 0.0272194 185 257 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_061.v common 4.20 vpr 64.39 MiB -1 -1 0.17 18440 13 0.28 -1 -1 32436 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 297 329 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.33 2331 1313 3744 580 3016 148 64.4 MiB 0.03 0.00 9.31665 8.10068 -171.378 -8.10068 8.10068 0.25 0.00048237 0.000443634 0.0128747 0.0119037 -1 -1 -1 -1 30 3374 30 6.79088e+06 269440 556674. 1926.21 1.97 0.161087 0.142735 24526 138013 -1 2738 19 1436 3802 177108 45178 7.26121 7.26121 -166.861 -7.26121 0 0 706193. 2443.58 0.03 0.05 0.13 -1 -1 0.03 0.0260456 0.0238074 143 203 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_062.v common 4.84 vpr 64.27 MiB -1 -1 0.14 18056 11 0.17 -1 -1 32236 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 231 263 1 167 82 17 17 289 -1 unnamed_device 24.9 MiB 0.44 2270 1023 7736 2019 5297 420 64.3 MiB 0.04 0.00 8.47541 6.67703 -137.267 -6.67703 6.67703 0.25 0.000362463 0.000328679 0.018534 0.0169718 -1 -1 -1 -1 32 2657 23 6.79088e+06 242496 586450. 2029.24 2.81 0.168016 0.148222 24814 144142 -1 2290 22 939 2390 174462 52299 5.65673 5.65673 -133.532 -5.65673 0 0 744469. 2576.02 0.03 0.05 0.09 -1 -1 0.03 0.0191776 0.0172547 102 137 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_063.v common 4.62 vpr 65.11 MiB -1 -1 0.29 18444 12 0.27 -1 -1 32348 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 305 337 1 213 84 17 17 289 -1 unnamed_device 25.6 MiB 0.45 2891 1443 5757 1168 4018 571 65.1 MiB 0.04 0.00 9.11861 7.63944 -167.73 -7.63944 7.63944 0.25 0.000465144 0.000424934 0.0193417 0.0177798 -1 -1 -1 -1 34 3932 44 6.79088e+06 269440 618332. 2139.56 2.35 0.227299 0.200836 25102 150614 -1 3251 21 1580 4929 276598 63194 6.67032 6.67032 -159.862 -6.67032 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0265715 0.0240576 150 211 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_064.v common 3.39 vpr 64.76 MiB -1 -1 0.14 18052 12 0.17 -1 -1 32236 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66312 32 32 243 275 1 185 85 17 17 289 -1 unnamed_device 24.9 MiB 0.31 2761 1193 9013 2310 6187 516 64.8 MiB 0.06 0.00 9.53525 7.06923 -152.736 -7.06923 7.06923 0.25 0.000831744 0.000771026 0.0259706 0.0239944 -1 -1 -1 -1 32 3476 32 6.79088e+06 282912 586450. 2029.24 1.53 0.163362 0.144355 24814 144142 -1 2663 17 1226 3225 178849 42340 6.24403 6.24403 -150.803 -6.24403 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0181705 0.0165401 116 149 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_065.v common 2.59 vpr 64.29 MiB -1 -1 0.15 18056 12 0.16 -1 -1 32240 -1 -1 19 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 30 32 228 260 1 164 81 17 17 289 -1 unnamed_device 24.5 MiB 0.38 2420 1052 9006 2359 5756 891 64.3 MiB 0.06 0.00 9.79978 7.51114 -149.061 -7.51114 7.51114 0.26 0.000582199 0.00055125 0.0274052 0.0252224 -1 -1 -1 -1 28 2581 46 6.79088e+06 255968 531479. 1839.03 0.62 0.10047 0.0893174 23950 126010 -1 2268 17 883 2304 127041 31144 6.50931 6.50931 -142.821 -6.50931 0 0 648988. 2245.63 0.02 0.04 0.14 -1 -1 0.02 0.0175122 0.0159131 106 140 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_066.v common 4.27 vpr 65.00 MiB -1 -1 0.18 18440 12 0.24 -1 -1 33000 -1 -1 27 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 29 32 275 307 1 201 88 17 17 289 -1 unnamed_device 25.2 MiB 0.86 2477 1194 11983 2982 7056 1945 65.0 MiB 0.07 0.00 9.28703 7.29287 -140.54 -7.29287 7.29287 0.25 0.000596237 0.000555455 0.0308238 0.0281961 -1 -1 -1 -1 34 3229 49 6.79088e+06 363744 618332. 2139.56 1.61 0.208 0.183725 25102 150614 -1 2663 18 1246 3691 195920 47061 6.49468 6.49468 -135.021 -6.49468 0 0 787024. 2723.27 0.04 0.08 0.12 -1 -1 0.04 0.031244 0.0281388 141 190 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_067.v common 3.17 vpr 64.52 MiB -1 -1 0.19 18436 13 0.30 -1 -1 32424 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 330 362 1 243 89 17 17 289 -1 unnamed_device 25.2 MiB 0.27 2791 1433 6425 1352 4743 330 64.5 MiB 0.05 0.00 10.3234 8.72856 -182.327 -8.72856 8.72856 0.24 0.000795659 0.000728071 0.0232994 0.0214039 -1 -1 -1 -1 38 3464 26 6.79088e+06 336800 678818. 2348.85 1.14 0.157746 0.140616 25966 169698 -1 2843 20 1580 4086 185601 47097 7.50416 7.50416 -166.392 -7.50416 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.0309614 0.0279604 164 236 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_068.v common 4.63 vpr 63.84 MiB -1 -1 0.30 18440 12 0.30 -1 -1 32376 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65376 32 32 290 322 1 218 87 17 17 289 -1 unnamed_device 24.9 MiB 0.35 2738 1381 6039 1246 4273 520 63.8 MiB 0.04 0.00 10.6331 7.88426 -165.865 -7.88426 7.88426 0.25 0.000465683 0.000427551 0.0179957 0.016611 -1 -1 -1 -1 44 3100 19 6.79088e+06 309856 787024. 2723.27 2.38 0.252406 0.224359 27118 194962 -1 2732 20 1293 3687 194765 45364 7.04976 7.04976 -158.257 -7.04976 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0242765 0.022065 145 196 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_069.v common 3.11 vpr 64.28 MiB -1 -1 0.19 18056 12 0.13 -1 -1 32964 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 214 246 1 158 81 17 17 289 -1 unnamed_device 24.5 MiB 0.65 2402 966 11631 3699 5844 2088 64.3 MiB 0.06 0.00 10.2046 7.4716 -147.486 -7.4716 7.4716 0.31 0.000337689 0.000308377 0.0259086 0.0237764 -1 -1 -1 -1 30 2786 28 6.79088e+06 229024 556674. 1926.21 0.63 0.0863746 0.076974 24526 138013 -1 2052 27 873 2476 167777 62750 6.58427 6.58427 -143.078 -6.58427 0 0 706193. 2443.58 0.03 0.07 0.08 -1 -1 0.03 0.027424 0.0243636 94 120 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_070.v common 3.07 vpr 64.72 MiB -1 -1 0.17 18052 12 0.19 -1 -1 32040 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66276 31 32 244 276 1 178 85 17 17 289 -1 unnamed_device 25.2 MiB 0.54 2184 1042 4921 903 3842 176 64.7 MiB 0.05 0.00 8.68884 7.00394 -143.566 -7.00394 7.00394 0.35 0.000580339 0.000532143 0.0195529 0.0179552 -1 -1 -1 -1 30 3034 24 6.79088e+06 296384 556674. 1926.21 0.78 0.0893686 0.0802788 24526 138013 -1 2491 21 1275 3564 186778 44710 6.22488 6.22488 -141.943 -6.22488 0 0 706193. 2443.58 0.03 0.05 0.12 -1 -1 0.03 0.0205045 0.0184847 113 153 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_071.v common 3.99 vpr 64.89 MiB -1 -1 0.26 18436 11 0.17 -1 -1 32464 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66448 30 32 276 308 1 187 83 17 17 289 -1 unnamed_device 24.9 MiB 0.88 2327 1150 11783 3905 5750 2128 64.9 MiB 0.07 0.00 8.87527 6.95498 -139.11 -6.95498 6.95498 0.25 0.000420157 0.000383828 0.0308821 0.0282508 -1 -1 -1 -1 36 2957 25 6.79088e+06 282912 648988. 2245.63 1.42 0.17502 0.154264 25390 158009 -1 2591 18 1136 3349 191755 44399 5.75396 5.75396 -131.866 -5.75396 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0209723 0.0190357 129 188 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_072.v common 2.83 vpr 64.16 MiB -1 -1 0.15 18292 11 0.18 -1 -1 32256 -1 -1 22 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65704 28 32 253 285 1 172 82 17 17 289 -1 unnamed_device 24.9 MiB 0.41 2569 974 5778 1226 4251 301 64.2 MiB 0.05 0.00 9.47421 6.55419 -124.806 -6.55419 6.55419 0.25 0.000396379 0.000362887 0.0227797 0.0211258 -1 -1 -1 -1 30 2829 21 6.79088e+06 296384 556674. 1926.21 0.90 0.0960849 0.0857142 24526 138013 -1 2180 16 1052 3156 159340 38063 5.81774 5.81774 -121.9 -5.81774 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0180222 0.0164005 120 171 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_073.v common 4.56 vpr 64.36 MiB -1 -1 0.15 18052 13 0.24 -1 -1 32168 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 30 32 235 267 1 170 80 17 17 289 -1 unnamed_device 25.2 MiB 0.73 2387 982 10056 3040 5967 1049 64.4 MiB 0.08 0.00 9.81312 7.63272 -149.917 -7.63272 7.63272 0.26 0.000365681 0.000334243 0.0425039 0.0393652 -1 -1 -1 -1 28 3041 35 6.79088e+06 242496 531479. 1839.03 2.19 0.170005 0.151582 23950 126010 -1 2375 17 1061 2784 162889 39902 6.66693 6.66693 -147.788 -6.66693 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0189454 0.0172721 108 147 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_074.v common 3.17 vpr 64.23 MiB -1 -1 0.22 18436 12 0.17 -1 -1 31628 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 264 296 1 197 84 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2415 1100 7770 2015 4653 1102 64.2 MiB 0.05 0.00 8.61815 6.91588 -153.666 -6.91588 6.91588 0.25 0.000579984 0.000543002 0.0212815 0.0195477 -1 -1 -1 -1 34 3490 32 6.79088e+06 269440 618332. 2139.56 1.09 0.135237 0.119678 25102 150614 -1 2558 21 1284 3364 172397 44534 5.95079 5.95079 -148.444 -5.95079 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0229694 0.020794 123 170 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_075.v common 4.84 vpr 64.97 MiB -1 -1 0.23 18440 13 0.26 -1 -1 32440 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66528 31 32 278 310 1 200 88 17 17 289 -1 unnamed_device 24.9 MiB 0.60 2897 1114 11788 3097 6456 2235 65.0 MiB 0.07 0.00 11.7353 8.38278 -163.21 -8.38278 8.38278 0.25 0.000448414 0.000410921 0.031208 0.0287226 -1 -1 -1 -1 32 3812 34 6.79088e+06 336800 586450. 2029.24 2.47 0.211753 0.186949 24814 144142 -1 2673 22 1312 3766 200576 50238 7.37881 7.37881 -158.541 -7.37881 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0245143 0.0221544 139 187 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_076.v common 4.12 vpr 65.02 MiB -1 -1 0.17 18056 14 0.23 -1 -1 32256 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 290 322 1 211 86 17 17 289 -1 unnamed_device 25.6 MiB 0.40 2838 1263 6323 1281 4818 224 65.0 MiB 0.05 0.00 9.79877 8.51252 -171.88 -8.51252 8.51252 0.30 0.000558009 0.000518729 0.0243299 0.022691 -1 -1 -1 -1 36 3441 45 6.79088e+06 296384 648988. 2245.63 1.72 0.189446 0.168875 25390 158009 -1 2883 25 1619 4804 303117 88801 7.57564 7.57564 -165.101 -7.57564 0 0 828058. 2865.25 0.03 0.09 0.08 -1 -1 0.03 0.0285655 0.0257961 142 196 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_077.v common 5.32 vpr 64.20 MiB -1 -1 0.18 18824 14 0.21 -1 -1 31756 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 269 301 1 198 83 17 17 289 -1 unnamed_device 24.9 MiB 0.76 2866 1248 7823 1994 5588 241 64.2 MiB 0.08 0.00 10.6835 8.05628 -162.217 -8.05628 8.05628 0.44 0.000778824 0.000710335 0.0372945 0.0341344 -1 -1 -1 -1 36 3198 50 6.79088e+06 255968 648988. 2245.63 2.26 0.244666 0.217046 25390 158009 -1 2775 21 1430 4356 266832 59760 7.46142 7.46142 -158.825 -7.46142 0 0 828058. 2865.25 0.05 0.11 0.14 -1 -1 0.05 0.0415661 0.0375795 124 175 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_078.v common 4.92 vpr 64.81 MiB -1 -1 0.17 18820 13 0.29 -1 -1 32464 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66364 32 32 296 328 1 220 88 17 17 289 -1 unnamed_device 24.9 MiB 0.79 3301 1354 9838 2791 5943 1104 64.8 MiB 0.11 0.00 11.6561 8.50014 -174.144 -8.50014 8.50014 0.44 0.000953862 0.000846986 0.050354 0.0460695 -1 -1 -1 -1 40 3071 19 6.79088e+06 323328 706193. 2443.58 1.90 0.242904 0.215911 26254 175826 -1 2921 18 1386 4092 217498 50671 7.4292 7.4292 -164.596 -7.4292 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.0236931 0.0216261 148 202 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_079.v common 3.73 vpr 64.04 MiB -1 -1 0.15 18056 13 0.16 -1 -1 32240 -1 -1 20 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65572 30 32 234 266 1 174 82 17 17 289 -1 unnamed_device 24.9 MiB 0.71 2093 1110 11118 3343 5904 1871 64.0 MiB 0.07 0.00 8.34292 7.03168 -146.297 -7.03168 7.03168 0.37 0.000407522 0.000370634 0.0354939 0.0326379 -1 -1 -1 -1 32 3046 36 6.79088e+06 269440 586450. 2029.24 1.25 0.163242 0.144621 24814 144142 -1 2365 20 1188 3012 173307 40703 6.14335 6.14335 -141.075 -6.14335 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0190443 0.0172279 105 146 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_080.v common 4.29 vpr 64.45 MiB -1 -1 0.21 18824 13 0.40 -1 -1 32420 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 30 32 291 323 1 221 84 17 17 289 -1 unnamed_device 24.9 MiB 0.49 2701 1328 5940 1337 4353 250 64.5 MiB 0.08 0.00 9.92372 8.27725 -167.59 -8.27725 8.27725 0.32 0.000471761 0.000432104 0.0419352 0.0390168 -1 -1 -1 -1 40 2990 21 6.79088e+06 296384 706193. 2443.58 1.77 0.216138 0.191906 26254 175826 -1 2793 21 1499 3987 204361 48668 7.05325 7.05325 -158.984 -7.05325 0 0 926341. 3205.33 0.03 0.06 0.10 -1 -1 0.03 0.0270017 0.0245199 148 203 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_081.v common 4.21 vpr 64.30 MiB -1 -1 0.17 18444 14 0.37 -1 -1 32456 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 32 32 274 306 1 198 83 17 17 289 -1 unnamed_device 24.9 MiB 0.42 2766 1310 6203 1436 4242 525 64.3 MiB 0.06 0.00 10.68 7.90813 -170.809 -7.90813 7.90813 0.26 0.000437767 0.000400069 0.0261332 0.0241232 -1 -1 -1 -1 38 3375 23 6.79088e+06 255968 678818. 2348.85 1.97 0.190854 0.168878 25966 169698 -1 2731 20 1307 4212 215589 49236 6.96028 6.96028 -163.001 -6.96028 0 0 902133. 3121.57 0.03 0.06 0.10 -1 -1 0.03 0.0239148 0.021685 132 180 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_082.v common 6.03 vpr 63.70 MiB -1 -1 0.17 18420 13 0.21 -1 -1 32388 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65224 31 32 266 298 1 197 82 17 17 289 -1 unnamed_device 24.9 MiB 0.50 2670 1263 9516 2495 6168 853 63.7 MiB 0.08 0.00 9.28969 7.78026 -159.259 -7.78026 7.78026 0.24 0.000427306 0.000391277 0.0374739 0.0347377 -1 -1 -1 -1 40 3248 40 6.79088e+06 255968 706193. 2443.58 3.11 0.247052 0.219892 26254 175826 -1 2973 78 1765 5797 1115118 678019 6.70192 6.70192 -151.991 -6.70192 0 0 926341. 3205.33 0.05 0.62 0.18 -1 -1 0.05 0.0991482 0.088454 126 175 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_083.v common 6.00 vpr 64.51 MiB -1 -1 0.25 18048 13 0.19 -1 -1 32400 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 30 32 266 298 1 199 87 17 17 289 -1 unnamed_device 24.9 MiB 0.58 3172 1233 7767 1881 5232 654 64.5 MiB 0.05 0.00 10.3598 7.59138 -150.075 -7.59138 7.59138 0.25 0.000417312 0.000382562 0.0197533 0.0181414 -1 -1 -1 -1 30 3483 48 6.79088e+06 336800 556674. 1926.21 3.75 0.181702 0.160413 24526 138013 -1 2860 17 1326 3637 193421 45729 6.80459 6.80459 -149.735 -6.80459 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0204113 0.0184966 131 178 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_084.v common 10.01 vpr 64.36 MiB -1 -1 0.19 18680 14 0.32 -1 -1 32292 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 310 342 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 0.53 2887 1381 9336 2138 6356 842 64.4 MiB 0.06 0.00 11.5139 8.70357 -178.124 -8.70357 8.70357 0.25 0.00049894 0.000457278 0.02631 0.0241948 -1 -1 -1 -1 32 4103 38 6.79088e+06 350272 586450. 2029.24 7.66 0.268987 0.239194 24814 144142 -1 3266 21 1495 4302 258673 61020 8.00547 8.00547 -175.323 -8.00547 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.026999 0.0245295 158 216 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_085.v common 4.72 vpr 64.77 MiB -1 -1 0.19 18440 11 0.25 -1 -1 32332 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 29 32 262 294 1 200 84 17 17 289 -1 unnamed_device 25.2 MiB 0.67 2793 1203 9966 2546 6206 1214 64.8 MiB 0.06 0.00 9.38772 7.1445 -141.662 -7.1445 7.1445 0.24 0.000419357 0.000383247 0.0259456 0.0238008 -1 -1 -1 -1 28 3470 28 6.79088e+06 309856 531479. 1839.03 2.12 0.187136 0.166118 23950 126010 -1 2930 22 1722 4992 281067 65184 6.54502 6.54502 -143.562 -6.54502 0 0 648988. 2245.63 0.04 0.12 0.12 -1 -1 0.04 0.0430561 0.0387822 138 177 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_086.v common 3.15 vpr 64.34 MiB -1 -1 0.15 18052 13 0.21 -1 -1 31724 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 32 32 222 254 1 179 83 17 17 289 -1 unnamed_device 24.9 MiB 0.55 2069 1200 7283 1764 4531 988 64.3 MiB 0.04 0.00 8.60203 7.14167 -162.348 -7.14167 7.14167 0.25 0.000344035 0.000314977 0.0190755 0.0175703 -1 -1 -1 -1 30 2976 21 6.79088e+06 255968 556674. 1926.21 0.84 0.0752712 0.0674518 24526 138013 -1 2322 18 1104 2731 132385 32111 6.15798 6.15798 -152.89 -6.15798 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0171264 0.0155641 100 128 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_087.v common 4.03 vpr 63.72 MiB -1 -1 0.19 18440 14 0.30 -1 -1 32404 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65252 32 32 267 299 1 192 83 17 17 289 -1 unnamed_device 24.9 MiB 0.66 2378 1170 9443 2925 4513 2005 63.7 MiB 0.06 0.00 10.4435 8.52224 -173.995 -8.52224 8.52224 0.25 0.000566754 0.000498933 0.0287922 0.0265342 -1 -1 -1 -1 34 3483 37 6.79088e+06 255968 618332. 2139.56 1.62 0.18205 0.160753 25102 150614 -1 2712 18 1256 3540 198662 47419 7.38302 7.38302 -165.88 -7.38302 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0210165 0.0191077 127 173 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_088.v common 3.79 vpr 63.94 MiB -1 -1 0.18 18824 15 0.39 -1 -1 32460 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 32 32 334 366 1 249 94 17 17 289 -1 unnamed_device 25.1 MiB 0.67 2997 1457 6271 1114 4893 264 63.9 MiB 0.05 0.00 11.8769 9.02668 -192.137 -9.02668 9.02668 0.24 0.000537557 0.000493455 0.0195073 0.0180239 -1 -1 -1 -1 36 4225 32 6.79088e+06 404160 648988. 2245.63 1.21 0.163429 0.145622 25390 158009 -1 3413 20 1762 4569 244133 58653 8.26721 8.26721 -187.065 -8.26721 0 0 828058. 2865.25 0.03 0.08 0.09 -1 -1 0.03 0.0324314 0.0294256 173 240 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_089.v common 4.34 vpr 64.31 MiB -1 -1 0.14 18052 11 0.14 -1 -1 32388 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 220 252 1 162 82 17 17 289 -1 unnamed_device 24.5 MiB 0.43 1851 1048 4710 962 3444 304 64.3 MiB 0.03 0.00 7.41857 6.65913 -141.007 -6.65913 6.65913 0.25 0.000338577 0.000308878 0.011031 0.0101382 -1 -1 -1 -1 30 2490 34 6.79088e+06 242496 556674. 1926.21 2.37 0.132925 0.116936 24526 138013 -1 2104 20 918 2474 125119 29697 5.77089 5.77089 -135.604 -5.77089 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0227745 0.020516 99 126 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_090.v common 3.59 vpr 64.79 MiB -1 -1 0.14 18056 12 0.16 -1 -1 31716 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 31 32 244 276 1 190 91 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2514 1243 8251 2100 5415 736 64.8 MiB 0.07 0.00 8.41327 6.64151 -151.522 -6.64151 6.64151 0.36 0.000384324 0.000351749 0.030995 0.0286946 -1 -1 -1 -1 36 3288 38 6.79088e+06 377216 648988. 2245.63 1.31 0.171017 0.151396 25390 158009 -1 2786 19 1310 3450 219229 55840 5.77084 5.77084 -147.31 -5.77084 0 0 828058. 2865.25 0.04 0.09 0.15 -1 -1 0.04 0.0326963 0.0295814 120 153 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_091.v common 4.25 vpr 64.96 MiB -1 -1 0.17 18440 12 0.26 -1 -1 32432 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 32 32 300 332 1 219 84 17 17 289 -1 unnamed_device 25.2 MiB 0.58 3008 1362 5208 1021 3853 334 65.0 MiB 0.04 0.00 9.33179 7.30279 -161.797 -7.30279 7.30279 0.24 0.000490485 0.000449616 0.0170101 0.0156458 -1 -1 -1 -1 32 4017 47 6.79088e+06 269440 586450. 2029.24 1.72 0.181491 0.159594 24814 144142 -1 3222 25 1827 5666 393170 111302 6.49473 6.49473 -154.751 -6.49473 0 0 744469. 2576.02 0.05 0.17 0.14 -1 -1 0.05 0.0525904 0.0474923 147 206 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_092.v common 4.94 vpr 64.30 MiB -1 -1 0.17 18440 12 0.21 -1 -1 32704 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 32 32 271 303 1 207 87 17 17 289 -1 unnamed_device 24.9 MiB 0.35 2518 1359 4887 914 3740 233 64.3 MiB 0.04 0.00 9.30843 7.32413 -157.509 -7.32413 7.32413 0.24 0.000422354 0.000385538 0.0141421 0.0129613 -1 -1 -1 -1 42 3546 34 6.79088e+06 309856 744469. 2576.02 2.98 0.184685 0.162721 26542 182613 -1 3075 20 1631 5150 317078 68780 6.32248 6.32248 -151.947 -6.32248 0 0 949917. 3286.91 0.03 0.07 0.10 -1 -1 0.03 0.0225575 0.0203783 135 177 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_093.v common 4.66 vpr 65.20 MiB -1 -1 0.18 18820 14 0.41 -1 -1 32516 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66760 32 32 327 359 1 232 89 17 17 289 -1 unnamed_device 25.2 MiB 0.91 2902 1486 9197 2044 6238 915 65.2 MiB 0.07 0.00 11.0044 9.05824 -184.444 -9.05824 9.05824 0.24 0.000531234 0.000486752 0.0317284 0.0292755 -1 -1 -1 -1 36 4352 44 6.79088e+06 336800 648988. 2245.63 1.82 0.192183 0.171116 25390 158009 -1 3470 21 2095 6448 340912 77405 7.89475 7.89475 -180.096 -7.89475 0 0 828058. 2865.25 0.03 0.09 0.09 -1 -1 0.03 0.0368876 0.0334178 170 233 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_094.v common 5.07 vpr 64.79 MiB -1 -1 0.16 18052 12 0.18 -1 -1 32312 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66344 30 32 246 278 1 190 83 17 17 289 -1 unnamed_device 25.2 MiB 0.38 2872 1225 9443 2668 5974 801 64.8 MiB 0.07 0.00 11.0773 8.04235 -151.9 -8.04235 8.04235 0.26 0.000906454 0.000843157 0.0312125 0.0289054 -1 -1 -1 -1 30 3247 21 6.79088e+06 282912 556674. 1926.21 3.09 0.153647 0.13626 24526 138013 -1 2617 19 1174 3385 171181 40726 7.03513 7.03513 -147.434 -7.03513 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0208927 0.0189654 123 158 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_095.v common 3.30 vpr 64.29 MiB -1 -1 0.14 17924 11 0.16 -1 -1 32200 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65828 27 32 219 251 1 158 80 17 17 289 -1 unnamed_device 24.5 MiB 0.66 2254 914 10228 3057 5550 1621 64.3 MiB 0.06 0.00 9.28609 7.11012 -129.104 -7.11012 7.11012 0.26 0.000834625 0.000778535 0.0290409 0.0268197 -1 -1 -1 -1 32 2363 20 6.79088e+06 282912 586450. 2029.24 1.10 0.132738 0.117693 24814 144142 -1 2014 16 860 2297 118764 28995 6.41202 6.41202 -124.201 -6.41202 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.018655 0.0167893 106 140 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_096.v common 12.15 vpr 64.09 MiB -1 -1 0.34 19208 13 0.38 -1 -1 32612 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65628 32 32 380 412 1 267 93 17 17 289 -1 unnamed_device 25.2 MiB 0.96 3799 1688 9333 2238 6298 797 64.1 MiB 0.07 0.00 9.85648 8.03891 -164.154 -8.03891 8.03891 0.24 0.000570832 0.000522627 0.0301749 0.0276234 -1 -1 -1 -1 36 4720 50 6.79088e+06 390688 648988. 2245.63 9.12 0.333255 0.295789 25390 158009 -1 4022 18 1939 5882 349528 81642 7.24643 7.24643 -163.259 -7.24643 0 0 828058. 2865.25 0.03 0.09 0.09 -1 -1 0.03 0.0332537 0.0305258 194 286 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_097.v common 5.05 vpr 64.26 MiB -1 -1 0.18 18440 14 0.23 -1 -1 32352 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65800 31 32 277 309 1 194 84 17 17 289 -1 unnamed_device 25.2 MiB 0.43 2825 1259 8502 2170 5586 746 64.3 MiB 0.05 0.00 10.5434 8.40299 -170.106 -8.40299 8.40299 0.26 0.000438649 0.000401614 0.0240127 0.0220456 -1 -1 -1 -1 28 3607 48 6.79088e+06 282912 531479. 1839.03 2.70 0.212266 0.187267 23950 126010 -1 2799 19 1355 3498 182428 44663 7.5622 7.5622 -166.161 -7.5622 0 0 648988. 2245.63 0.03 0.08 0.07 -1 -1 0.03 0.0331487 0.0300722 135 186 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_098.v common 4.33 vpr 64.66 MiB -1 -1 0.27 18044 12 0.14 -1 -1 32196 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66212 32 32 229 261 1 173 88 17 17 289 -1 unnamed_device 24.9 MiB 0.47 2146 1148 7498 1703 4699 1096 64.7 MiB 0.04 0.00 9.61147 7.37908 -161.709 -7.37908 7.37908 0.25 0.000363041 0.000331373 0.0171253 0.015721 -1 -1 -1 -1 30 2639 20 6.79088e+06 323328 556674. 1926.21 2.24 0.140925 0.124252 24526 138013 -1 2241 16 933 2468 118642 29008 6.35367 6.35367 -152.496 -6.35367 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0215127 0.019597 114 135 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_099.v common 4.34 vpr 64.91 MiB -1 -1 0.18 18056 13 0.26 -1 -1 32468 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 263 295 1 189 86 17 17 289 -1 unnamed_device 24.9 MiB 0.87 2477 1198 6323 1455 4634 234 64.9 MiB 0.04 0.00 9.94771 7.95285 -163.297 -7.95285 7.95285 0.25 0.000419039 0.000383418 0.0192272 0.0177068 -1 -1 -1 -1 30 3038 31 6.79088e+06 296384 556674. 1926.21 1.80 0.189632 0.166804 24526 138013 -1 2547 17 1163 3392 164677 39638 6.92451 6.92451 -155.538 -6.92451 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0206129 0.0187785 132 169 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_100.v common 5.11 vpr 64.46 MiB -1 -1 0.18 18824 13 0.30 -1 -1 32440 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 321 353 1 243 89 17 17 289 -1 unnamed_device 25.5 MiB 0.47 2996 1555 6425 1253 4749 423 64.5 MiB 0.08 0.00 9.44492 8.03594 -170.227 -8.03594 8.03594 0.46 0.00109351 0.000985855 0.037958 0.0348172 -1 -1 -1 -1 36 4372 49 6.79088e+06 350272 648988. 2245.63 2.33 0.288027 0.256154 25390 158009 -1 3542 17 1701 4822 272035 63597 6.79572 6.79572 -158.919 -6.79572 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0243842 0.0223031 162 230 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_101.v common 4.27 vpr 64.99 MiB -1 -1 0.16 18440 11 0.22 -1 -1 32436 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 30 32 287 319 1 199 87 17 17 289 -1 unnamed_device 25.2 MiB 0.86 2711 1222 7191 1645 4976 570 65.0 MiB 0.05 0.00 9.60741 7.06412 -137.725 -7.06412 7.06412 0.24 0.000443175 0.000405281 0.0197344 0.0181089 -1 -1 -1 -1 40 2876 29 6.79088e+06 336800 706193. 2443.58 1.75 0.202725 0.178825 26254 175826 -1 2606 19 1353 4351 224230 52925 5.91852 5.91852 -128.55 -5.91852 0 0 926341. 3205.33 0.03 0.06 0.09 -1 -1 0.03 0.022852 0.0207243 143 199 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_102.v common 4.55 vpr 64.41 MiB -1 -1 0.27 18440 15 0.33 -1 -1 32440 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65952 32 32 296 328 1 214 86 17 17 289 -1 unnamed_device 25.2 MiB 0.59 3096 1319 6134 1277 4632 225 64.4 MiB 0.04 0.00 11.1915 8.22013 -174.204 -8.22013 8.22013 0.24 0.000481606 0.000431524 0.0187261 0.0171522 -1 -1 -1 -1 34 4119 45 6.79088e+06 296384 618332. 2139.56 2.03 0.178009 0.157929 25102 150614 -1 3072 18 1428 4203 233689 55761 7.32848 7.32848 -170.707 -7.32848 0 0 787024. 2723.27 0.05 0.08 0.14 -1 -1 0.05 0.0306779 0.0281631 148 202 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_103.v common 4.64 vpr 64.37 MiB -1 -1 0.25 18820 13 0.37 -1 -1 32476 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 285 317 1 219 85 17 17 289 -1 unnamed_device 25.2 MiB 0.46 2930 1425 7525 1768 5171 586 64.4 MiB 0.05 0.00 10.4559 8.30966 -180.808 -8.30966 8.30966 0.25 0.000502423 0.000463715 0.0224499 0.0206809 -1 -1 -1 -1 36 3708 27 6.79088e+06 282912 648988. 2245.63 2.23 0.211147 0.187347 25390 158009 -1 3210 17 1367 3795 216510 50749 7.33966 7.33966 -172.69 -7.33966 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0240039 0.0219196 145 191 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_104.v common 3.64 vpr 64.62 MiB -1 -1 0.14 18052 12 0.17 -1 -1 32272 -1 -1 24 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66168 29 32 239 271 1 185 85 17 17 289 -1 unnamed_device 25.2 MiB 0.48 2084 1062 6595 1474 4636 485 64.6 MiB 0.04 0.00 10.0683 7.87572 -156.471 -7.87572 7.87572 0.40 0.000377318 0.000346308 0.0159074 0.0146289 -1 -1 -1 -1 30 2731 21 6.79088e+06 323328 556674. 1926.21 1.31 0.146981 0.129805 24526 138013 -1 2294 18 1137 2909 136931 33931 6.58776 6.58776 -145.673 -6.58776 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0182257 0.0165595 115 154 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_105.v common 2.40 vpr 64.36 MiB -1 -1 0.14 18056 11 0.13 -1 -1 32284 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 235 267 1 172 82 17 17 289 -1 unnamed_device 24.5 MiB 0.32 2050 1060 6668 1430 4144 1094 64.4 MiB 0.04 0.00 7.79354 6.47149 -144.071 -6.47149 6.47149 0.24 0.000355213 0.000324341 0.0157647 0.0144757 -1 -1 -1 -1 30 2916 41 6.79088e+06 242496 556674. 1926.21 0.65 0.0815988 0.0723604 24526 138013 -1 2303 20 1233 3012 153485 37395 5.85694 5.85694 -146.237 -5.85694 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.018489 0.0167165 105 141 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_106.v common 5.00 vpr 64.54 MiB -1 -1 0.23 18440 13 0.37 -1 -1 32424 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 31 32 294 326 1 211 85 17 17 289 -1 unnamed_device 24.9 MiB 0.70 2712 1384 8455 2000 5617 838 64.5 MiB 0.06 0.00 10.7696 8.27424 -162.337 -8.27424 8.27424 0.24 0.000474087 0.00042731 0.0248337 0.0227038 -1 -1 -1 -1 44 3185 20 6.79088e+06 296384 787024. 2723.27 2.15 0.239145 0.211054 27118 194962 -1 2809 17 1208 3870 211069 47834 7.26465 7.26465 -155.018 -7.26465 0 0 997811. 3452.63 0.04 0.06 0.11 -1 -1 0.04 0.0260052 0.0238743 146 203 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_107.v common 4.01 vpr 64.32 MiB -1 -1 0.15 18056 10 0.23 -1 -1 32416 -1 -1 20 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65860 29 32 219 251 1 164 81 17 17 289 -1 unnamed_device 24.9 MiB 0.41 2040 1050 9181 2635 5082 1464 64.3 MiB 0.05 0.00 8.60248 6.23968 -127.611 -6.23968 6.23968 0.25 0.000341543 0.000311725 0.020299 0.0185793 -1 -1 -1 -1 30 2491 49 6.79088e+06 269440 556674. 1926.21 1.98 0.183649 0.161612 24526 138013 -1 2107 16 952 2430 121433 29267 5.32762 5.32762 -123.296 -5.32762 0 0 706193. 2443.58 0.03 0.04 0.10 -1 -1 0.03 0.0157135 0.0142992 102 134 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_108.v common 3.06 vpr 64.46 MiB -1 -1 0.27 18052 14 0.21 -1 -1 32268 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66008 32 32 239 271 1 181 84 17 17 289 -1 unnamed_device 24.9 MiB 0.73 2315 1098 11430 3365 6228 1837 64.5 MiB 0.06 0.00 10.7127 7.63704 -166.154 -7.63704 7.63704 0.24 0.000386695 0.000354045 0.0270002 0.0247053 -1 -1 -1 -1 30 3052 25 6.79088e+06 269440 556674. 1926.21 0.65 0.0895294 0.0802576 24526 138013 -1 2455 17 1129 3039 153350 36717 6.70624 6.70624 -158.346 -6.70624 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0180472 0.0163852 109 145 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_109.v common 3.80 vpr 64.23 MiB -1 -1 0.19 18440 13 0.30 -1 -1 31856 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 31 32 266 298 1 201 86 17 17 289 -1 unnamed_device 24.9 MiB 0.22 2581 1245 12938 3565 7972 1401 64.2 MiB 0.07 0.00 9.50492 7.70092 -164.904 -7.70092 7.70092 0.25 0.000426903 0.000390675 0.0317082 0.0290071 -1 -1 -1 -1 40 2648 20 6.79088e+06 309856 706193. 2443.58 1.70 0.179053 0.1576 26254 175826 -1 2643 32 1411 4011 312466 112192 6.87412 6.87412 -157.009 -6.87412 0 0 926341. 3205.33 0.03 0.10 0.09 -1 -1 0.03 0.0302607 0.0270951 131 175 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_110.v common 4.15 vpr 64.27 MiB -1 -1 0.15 18056 12 0.13 -1 -1 32216 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65816 31 32 225 257 1 170 83 17 17 289 -1 unnamed_device 24.9 MiB 0.49 2115 1069 8363 2595 4472 1296 64.3 MiB 0.04 0.00 7.74408 6.38969 -140.212 -6.38969 6.38969 0.35 0.000345596 0.000315547 0.018183 0.0166542 -1 -1 -1 -1 34 2730 27 6.79088e+06 269440 618332. 2139.56 1.95 0.172862 0.151998 25102 150614 -1 2386 18 1076 2987 160528 38621 5.77854 5.77854 -138.465 -5.77854 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0168124 0.0152225 103 134 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_111.v common 7.51 vpr 64.32 MiB -1 -1 0.17 18296 12 0.18 -1 -1 33036 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 32 32 288 320 1 203 88 17 17 289 -1 unnamed_device 25.5 MiB 0.51 3004 1280 11788 3296 6900 1592 64.3 MiB 0.07 0.00 10.2613 7.00869 -152.842 -7.00869 7.00869 0.27 0.000438351 0.000399908 0.031924 0.029294 -1 -1 -1 -1 28 3899 44 6.79088e+06 323328 531479. 1839.03 5.38 0.219573 0.193871 23950 126010 -1 2955 20 1664 4630 280626 64993 6.12648 6.12648 -151.532 -6.12648 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0235006 0.0210914 135 194 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_112.v common 6.17 vpr 64.38 MiB -1 -1 0.19 18828 13 0.26 -1 -1 32432 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65924 31 32 282 314 1 210 85 17 17 289 -1 unnamed_device 25.2 MiB 0.59 2791 1262 11989 3047 7402 1540 64.4 MiB 0.09 0.00 9.30843 7.42893 -161.431 -7.42893 7.42893 0.28 0.000974651 0.000901685 0.043486 0.040061 -1 -1 -1 -1 30 3449 32 6.79088e+06 296384 556674. 1926.21 3.72 0.235374 0.209057 24526 138013 -1 2705 19 1433 4023 185362 45909 6.48354 6.48354 -153.414 -6.48354 0 0 706193. 2443.58 0.04 0.09 0.09 -1 -1 0.04 0.0421007 0.0381483 146 191 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_113.v common 3.75 vpr 64.15 MiB -1 -1 0.16 18048 11 0.15 -1 -1 32388 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65692 32 32 233 265 1 180 86 17 17 289 -1 unnamed_device 24.5 MiB 0.41 2072 1111 7835 1720 5449 666 64.2 MiB 0.05 0.00 7.45434 6.20134 -144.716 -6.20134 6.20134 0.32 0.000830303 0.000790451 0.0195382 0.0179662 -1 -1 -1 -1 36 2970 27 6.79088e+06 296384 648988. 2245.63 1.69 0.172648 0.151291 25390 158009 -1 2502 29 1264 3459 234056 74739 5.52096 5.52096 -139.628 -5.52096 0 0 828058. 2865.25 0.03 0.07 0.08 -1 -1 0.03 0.0240282 0.0214863 110 139 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_114.v common 5.62 vpr 64.79 MiB -1 -1 0.17 18056 13 0.24 -1 -1 32176 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66348 32 32 254 286 1 184 81 17 17 289 -1 unnamed_device 24.9 MiB 1.26 2540 1123 6906 1729 4876 301 64.8 MiB 0.04 0.00 10.5313 7.62596 -162.162 -7.62596 7.62596 0.40 0.000407825 0.000374245 0.018867 0.0173648 -1 -1 -1 -1 38 2722 40 6.79088e+06 229024 678818. 2348.85 2.19 0.276797 0.244307 25966 169698 -1 2249 15 995 2896 146488 34789 6.54512 6.54512 -154.218 -6.54512 0 0 902133. 3121.57 0.05 0.07 0.16 -1 -1 0.05 0.0297021 0.0269232 116 160 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_115.v common 3.89 vpr 63.58 MiB -1 -1 0.16 18436 13 0.24 -1 -1 32396 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65108 32 32 285 317 1 212 85 17 17 289 -1 unnamed_device 24.9 MiB 0.63 2626 1379 8083 1955 5557 571 63.6 MiB 0.07 0.00 9.80963 7.47873 -167.813 -7.47873 7.47873 0.25 0.000461112 0.000414019 0.0308002 0.0282531 -1 -1 -1 -1 34 3779 35 6.79088e+06 282912 618332. 2139.56 1.52 0.160694 0.142529 25102 150614 -1 3127 35 2346 6906 463431 130783 6.64799 6.64799 -160.553 -6.64799 0 0 787024. 2723.27 0.03 0.13 0.08 -1 -1 0.03 0.0366382 0.0328335 141 191 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_116.v common 3.53 vpr 64.07 MiB -1 -1 0.16 18436 11 0.17 -1 -1 32420 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65612 29 32 243 275 1 183 84 17 17 289 -1 unnamed_device 25.0 MiB 0.49 2499 1173 5208 1126 3631 451 64.1 MiB 0.03 0.00 8.34934 6.48043 -132.63 -6.48043 6.48043 0.25 0.000388058 0.000355693 0.0135592 0.0124786 -1 -1 -1 -1 36 2852 31 6.79088e+06 309856 648988. 2245.63 1.48 0.140205 0.122902 25390 158009 -1 2465 15 967 2919 169443 38934 5.75934 5.75934 -130.721 -5.75934 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0215183 0.0194205 118 158 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_117.v common 7.21 vpr 64.50 MiB -1 -1 0.24 18824 14 0.29 -1 -1 33064 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 318 350 1 238 89 17 17 289 -1 unnamed_device 25.6 MiB 0.50 3185 1427 9989 2338 6256 1395 64.5 MiB 0.07 0.00 11.6109 8.7465 -186.455 -8.7465 8.7465 0.33 0.000521333 0.000476424 0.0308609 0.0283334 -1 -1 -1 -1 30 4195 34 6.79088e+06 336800 556674. 1926.21 4.77 0.280847 0.2493 24526 138013 -1 3114 19 1654 4325 208709 51804 7.58672 7.58672 -175.163 -7.58672 0 0 706193. 2443.58 0.03 0.06 0.08 -1 -1 0.03 0.0266528 0.0243323 164 224 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_118.v common 3.55 vpr 64.24 MiB -1 -1 0.14 18052 12 0.13 -1 -1 32232 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 222 254 1 182 84 17 17 289 -1 unnamed_device 24.9 MiB 0.32 2515 1195 7953 1918 5225 810 64.2 MiB 0.10 0.00 9.02976 6.57733 -149.186 -6.57733 6.57733 0.27 0.00096 0.00088875 0.0449597 0.0417068 -1 -1 -1 -1 40 2450 19 6.79088e+06 282912 706193. 2443.58 1.51 0.16322 0.144706 26254 175826 -1 2277 19 1016 2613 138232 32332 5.70014 5.70014 -139.839 -5.70014 0 0 926341. 3205.33 0.03 0.04 0.15 -1 -1 0.03 0.0177558 0.0160847 105 131 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_119.v common 4.23 vpr 64.32 MiB -1 -1 0.31 18824 13 0.26 -1 -1 33012 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 282 314 1 202 87 17 17 289 -1 unnamed_device 25.2 MiB 0.57 2586 1294 11223 2709 7284 1230 64.3 MiB 0.07 0.00 9.80636 7.81522 -163.002 -7.81522 7.81522 0.24 0.000459996 0.000421553 0.0298052 0.027397 -1 -1 -1 -1 32 3772 44 6.79088e+06 309856 586450. 2029.24 1.80 0.216101 0.190564 24814 144142 -1 3139 27 1415 4088 291600 96304 6.80686 6.80686 -159.585 -6.80686 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0326913 0.0294747 141 188 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_120.v common 3.43 vpr 64.70 MiB -1 -1 0.16 18428 13 0.16 -1 -1 32224 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 238 270 1 179 87 17 17 289 -1 unnamed_device 24.9 MiB 0.33 2213 1145 7959 1748 5469 742 64.7 MiB 0.06 0.00 9.57282 7.74786 -170.737 -7.74786 7.74786 0.30 0.000551588 0.000502718 0.0268101 0.0244864 -1 -1 -1 -1 32 2899 40 6.79088e+06 309856 586450. 2029.24 1.46 0.179622 0.159166 24814 144142 -1 2346 15 990 2455 133104 32316 6.67386 6.67386 -160.516 -6.67386 0 0 744469. 2576.02 0.04 0.05 0.10 -1 -1 0.04 0.0230009 0.0211562 112 144 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_121.v common 3.57 vpr 64.93 MiB -1 -1 0.17 18052 12 0.23 -1 -1 32288 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66488 32 32 269 301 1 193 85 17 17 289 -1 unnamed_device 24.9 MiB 0.83 2838 1258 5665 1169 4247 249 64.9 MiB 0.04 0.00 10.2294 7.48857 -162.185 -7.48857 7.48857 0.27 0.000426859 0.00038986 0.0193522 0.0178721 -1 -1 -1 -1 32 3332 43 6.79088e+06 282912 586450. 2029.24 0.72 0.118284 0.105925 24814 144142 -1 2752 17 1274 3805 210568 50438 6.37282 6.37282 -153.729 -6.37282 0 0 744469. 2576.02 0.04 0.12 0.08 -1 -1 0.04 0.0501828 0.0454932 132 175 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_122.v common 6.84 vpr 64.75 MiB -1 -1 0.20 19208 15 0.56 -1 -1 32720 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 350 382 1 251 89 17 17 289 -1 unnamed_device 25.6 MiB 1.00 3569 1573 10583 2766 6384 1433 64.7 MiB 0.09 0.00 11.6887 9.43481 -197.257 -9.43481 9.43481 0.24 0.000575225 0.00052701 0.0405772 0.0372963 -1 -1 -1 -1 48 3820 22 6.79088e+06 336800 865456. 2994.66 3.48 0.393652 0.351941 27694 206865 -1 3410 19 1843 6055 331838 74371 8.18111 8.18111 -182.275 -8.18111 0 0 1.05005e+06 3633.38 0.04 0.08 0.11 -1 -1 0.04 0.0308149 0.0280731 184 256 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_123.v common 2.87 vpr 64.00 MiB -1 -1 0.15 17668 10 0.10 -1 -1 32064 -1 -1 13 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65540 30 32 174 206 1 132 75 17 17 289 -1 unnamed_device 24.3 MiB 0.27 1704 689 6079 1358 4541 180 64.0 MiB 0.03 0.00 5.85167 5.06685 -115.513 -5.06685 5.06685 0.25 0.000272135 0.000249038 0.0120598 0.0110675 -1 -1 -1 -1 34 1844 23 6.79088e+06 175136 618332. 2139.56 1.13 0.0922076 0.0806298 25102 150614 -1 1531 16 723 1671 81394 21367 4.46811 4.46811 -112.797 -4.46811 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0119656 0.0108259 66 86 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_124.v common 4.10 vpr 64.34 MiB -1 -1 0.15 18056 13 0.16 -1 -1 32248 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65880 30 32 228 260 1 170 83 17 17 289 -1 unnamed_device 24.6 MiB 0.72 2214 1013 9083 2607 5166 1310 64.3 MiB 0.05 0.00 9.66643 7.93028 -158.567 -7.93028 7.93028 0.35 0.000357607 0.000326665 0.0206406 0.0189224 -1 -1 -1 -1 34 2709 33 6.79088e+06 282912 618332. 2139.56 1.47 0.155242 0.1373 25102 150614 -1 2341 27 1048 2773 214239 76852 6.87418 6.87418 -150.154 -6.87418 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0227765 0.0204907 108 140 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_125.v common 4.29 vpr 64.83 MiB -1 -1 0.17 18292 12 0.18 -1 -1 32276 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 32 32 264 296 1 193 87 17 17 289 -1 unnamed_device 25.2 MiB 0.53 2664 1204 6039 1295 4393 351 64.8 MiB 0.06 0.00 9.33663 7.42897 -167.088 -7.42897 7.42897 0.45 0.000748074 0.000682446 0.0272169 0.0249518 -1 -1 -1 -1 32 3186 39 6.79088e+06 309856 586450. 2029.24 1.61 0.19246 0.169113 24814 144142 -1 2600 14 1082 2781 153438 36660 6.37287 6.37287 -156.925 -6.37287 0 0 744469. 2576.02 0.05 0.07 0.14 -1 -1 0.05 0.032197 0.0295269 122 170 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_126.v common 2.53 vpr 64.12 MiB -1 -1 0.15 17672 9 0.11 -1 -1 31992 -1 -1 21 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65660 25 32 183 215 1 134 78 17 17 289 -1 unnamed_device 24.5 MiB 0.35 1513 648 7216 2007 4704 505 64.1 MiB 0.05 0.00 5.889 5.1159 -95.0834 -5.1159 5.1159 0.26 0.000290205 0.000265211 0.026009 0.0242288 -1 -1 -1 -1 30 1972 23 6.79088e+06 282912 556674. 1926.21 0.76 0.077457 0.0696231 24526 138013 -1 1532 18 764 2122 115511 30012 4.5968 4.5968 -95.8798 -4.5968 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0140883 0.0127257 88 110 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_127.v common 4.22 vpr 63.79 MiB -1 -1 0.18 18436 12 0.24 -1 -1 32436 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65324 32 32 300 332 1 224 87 17 17 289 -1 unnamed_device 24.8 MiB 0.34 3045 1374 8343 1969 5805 569 63.8 MiB 0.06 0.00 9.97086 7.70352 -168.911 -7.70352 7.70352 0.25 0.000460963 0.000421707 0.0249877 0.0229274 -1 -1 -1 -1 38 3802 30 6.79088e+06 309856 678818. 2348.85 2.16 0.213639 0.188965 25966 169698 -1 3001 21 1702 4852 241275 56642 6.49817 6.49817 -159.124 -6.49817 0 0 902133. 3121.57 0.03 0.07 0.09 -1 -1 0.03 0.029603 0.0270055 149 206 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml mult_128.v common 8.43 vpr 64.56 MiB -1 -1 0.18 18676 13 0.28 -1 -1 31596 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66108 31 32 290 322 1 214 89 17 17 289 -1 unnamed_device 24.9 MiB 0.67 2884 1321 10979 2886 6026 2067 64.6 MiB 0.06 0.00 10.7249 8.28064 -170.23 -8.28064 8.28064 0.24 0.000458984 0.000419435 0.0290037 0.0265888 -1 -1 -1 -1 30 4442 39 6.79088e+06 350272 556674. 1926.21 5.83 0.209846 0.18645 24526 138013 -1 3137 25 1751 5411 317221 91806 6.76345 6.76345 -158.739 -6.76345 0 0 706193. 2443.58 0.04 0.14 0.11 -1 -1 0.04 0.0497607 0.0449491 152 199 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_001.v common 5.80 vpr 65.13 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29804 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66692 32 32 354 285 1 207 93 17 17 289 -1 unnamed_device 25.6 MiB 2.12 2779 1278 16893 5344 9435 2114 65.1 MiB 0.10 0.00 6.98757 5.68891 -164.239 -5.68891 5.68891 0.25 0.000338691 0.000310099 0.0300408 0.0274606 -1 -1 -1 -1 28 3219 28 6.87369e+06 405241 531479. 1839.03 2.22 0.157807 0.138497 24610 126494 -1 2606 22 1750 2807 239588 55064 4.64695 4.64695 -157.22 -4.64695 0 0 648988. 2245.63 0.04 0.10 0.07 -1 -1 0.04 0.0310265 0.0277948 140 50 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_002.v common 4.10 vpr 65.14 MiB -1 -1 0.15 18060 1 0.04 -1 -1 29588 -1 -1 26 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66700 30 32 363 293 1 200 88 17 17 289 -1 unnamed_device 25.2 MiB 2.26 2339 1135 13153 3755 7866 1532 65.1 MiB 0.07 0.00 5.6483 4.6679 -138.364 -4.6679 4.6679 0.25 0.000376387 0.000339735 0.0260552 0.0238597 -1 -1 -1 -1 32 2500 24 6.87369e+06 363320 586450. 2029.24 0.40 0.0720625 0.0638607 25474 144626 -1 2037 21 1653 2504 161353 39229 3.72316 3.72316 -133.558 -3.72316 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.018555 0.0164825 138 63 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_003.v common 4.52 vpr 64.16 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29804 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65700 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 24.8 MiB 1.92 2478 1094 14965 5159 7778 2028 64.2 MiB 0.08 0.00 5.41115 4.32745 -123.858 -4.32745 4.32745 0.26 0.00029771 0.000272503 0.0284356 0.0260371 -1 -1 -1 -1 32 2462 24 6.87369e+06 293451 586450. 2029.24 1.20 0.158071 0.138595 25474 144626 -1 1923 20 1108 1542 96591 24435 3.88596 3.88596 -121.789 -3.88596 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0144447 0.012843 118 29 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_004.v common 3.08 vpr 64.42 MiB -1 -1 0.12 18064 1 0.04 -1 -1 29732 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 29 32 308 248 1 172 90 17 17 289 -1 unnamed_device 24.9 MiB 0.98 2239 851 8532 2063 5786 683 64.4 MiB 0.06 0.00 5.55862 4.64138 -122.547 -4.64138 4.64138 0.26 0.000307462 0.000282124 0.0164768 0.0151923 -1 -1 -1 -1 32 2081 20 6.87369e+06 405241 586450. 2029.24 0.62 0.0640387 0.056848 25474 144626 -1 1662 22 1299 2371 141246 35332 3.7854 3.7854 -114.536 -3.7854 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0152355 0.0135343 124 31 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_005.v common 3.79 vpr 65.01 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29848 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66568 32 32 336 268 1 181 91 17 17 289 -1 unnamed_device 25.2 MiB 1.26 2579 1028 12331 3533 8153 645 65.0 MiB 0.07 0.00 5.58731 4.58138 -133.975 -4.58138 4.58138 0.25 0.00032842 0.00029842 0.0222301 0.0202265 -1 -1 -1 -1 34 2450 23 6.87369e+06 377294 618332. 2139.56 1.15 0.13371 0.116761 25762 151098 -1 2095 20 1351 2747 172345 43095 3.7624 3.7624 -131.476 -3.7624 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.015162 0.0134923 132 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_006.v common 4.58 vpr 65.02 MiB -1 -1 0.14 18448 1 0.03 -1 -1 29780 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 366 295 1 189 96 17 17 289 -1 unnamed_device 25.6 MiB 1.47 2521 1045 10389 2533 6980 876 65.0 MiB 0.11 0.00 4.09707 3.40153 -116.732 -3.40153 3.40153 0.44 0.000632207 0.000578463 0.0332248 0.0304864 -1 -1 -1 -1 30 2392 22 6.87369e+06 447163 556674. 1926.21 1.17 0.156714 0.137506 25186 138497 -1 1903 19 1087 1810 94547 23615 2.90721 2.90721 -116.443 -2.90721 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0210304 0.0187682 138 58 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_007.v common 4.53 vpr 64.02 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30528 -1 -1 21 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 27 32 259 221 1 141 80 17 17 289 -1 unnamed_device 24.9 MiB 2.14 1624 653 12120 3521 6665 1934 64.0 MiB 0.09 0.00 4.57488 3.84098 -103.196 -3.84098 3.84098 0.44 0.000480389 0.000439216 0.0357836 0.0328233 -1 -1 -1 -1 30 1522 20 6.87369e+06 293451 556674. 1926.21 0.59 0.0942957 0.0835691 25186 138497 -1 1227 20 894 1556 82299 20516 2.81866 2.81866 -96.2951 -2.81866 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0122356 0.0108607 97 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_008.v common 2.67 vpr 64.45 MiB -1 -1 0.19 17672 1 0.02 -1 -1 29744 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 31 32 271 219 1 164 96 17 17 289 -1 unnamed_device 24.9 MiB 0.68 2063 1017 12798 3323 7724 1751 64.4 MiB 0.06 0.00 4.11555 3.57969 -107.766 -3.57969 3.57969 0.31 0.000280987 0.000257318 0.0179421 0.0164247 -1 -1 -1 -1 32 2056 21 6.87369e+06 461137 586450. 2029.24 0.37 0.0598981 0.0528727 25474 144626 -1 1863 18 869 1628 98904 24067 2.70166 2.70166 -100.41 -2.70166 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0134961 0.0120734 119 4 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_009.v common 3.65 vpr 64.42 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29768 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65968 31 32 317 271 1 175 83 17 17 289 -1 unnamed_device 24.9 MiB 1.75 2074 1069 13943 3853 8284 1806 64.4 MiB 0.08 0.00 4.71896 3.59126 -121.314 -3.59126 3.59126 0.26 0.000300172 0.000275204 0.0327664 0.030306 -1 -1 -1 -1 32 2340 23 6.87369e+06 279477 586450. 2029.24 0.41 0.0792721 0.0707055 25474 144626 -1 1994 22 1117 1624 122047 28163 2.96331 2.96331 -117.189 -2.96331 0 0 744469. 2576.02 0.05 0.07 0.11 -1 -1 0.05 0.0269692 0.0240161 110 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_010.v common 5.50 vpr 64.53 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29756 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 298 248 1 162 81 17 17 289 -1 unnamed_device 25.1 MiB 2.97 1876 975 12681 3745 6747 2189 64.5 MiB 0.07 0.00 4.66108 3.90928 -131.51 -3.90928 3.90928 0.25 0.00030816 0.000282988 0.0298978 0.0278187 -1 -1 -1 -1 32 2119 22 6.87369e+06 237555 586450. 2029.24 1.04 0.113415 0.0997871 25474 144626 -1 1840 18 1127 1808 118643 28174 3.01796 3.01796 -123.051 -3.01796 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0243406 0.0217732 107 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_011.v common 4.92 vpr 64.09 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29796 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65624 30 32 303 262 1 148 80 17 17 289 -1 unnamed_device 24.9 MiB 2.42 1634 783 11948 4947 6106 895 64.1 MiB 0.05 0.00 4.23198 3.85608 -112.834 -3.85608 3.85608 0.25 0.000296286 0.000271011 0.0217417 0.0199276 -1 -1 -1 -1 28 2153 36 6.87369e+06 251529 531479. 1839.03 1.18 0.116888 0.101806 24610 126494 -1 1655 22 1103 1769 168234 43143 3.01626 3.01626 -112.104 -3.01626 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0149998 0.0130769 99 63 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_012.v common 4.20 vpr 64.57 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29732 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 24.8 MiB 1.84 2449 1027 12898 3673 7248 1977 64.6 MiB 0.07 0.00 4.7813 3.6715 -118.222 -3.6715 3.6715 0.25 0.000276217 0.00025305 0.0233421 0.0213867 -1 -1 -1 -1 32 2217 20 6.87369e+06 251529 586450. 2029.24 0.99 0.121125 0.105513 25474 144626 -1 1865 18 1024 1435 104148 24249 2.77201 2.77201 -111.424 -2.77201 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0124142 0.0110837 102 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_013.v common 6.02 vpr 64.56 MiB -1 -1 0.21 18060 1 0.04 -1 -1 29956 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66108 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 24.9 MiB 2.77 2479 1044 14147 4566 6974 2607 64.6 MiB 0.08 0.00 4.50463 4.21693 -134.575 -4.21693 4.21693 0.30 0.000329492 0.000301485 0.0259677 0.0238215 -1 -1 -1 -1 30 2730 27 6.87369e+06 349346 556674. 1926.21 1.60 0.132473 0.116447 25186 138497 -1 1999 23 1665 2538 150407 37762 3.15591 3.15591 -119.224 -3.15591 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0170917 0.0151913 139 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_014.v common 4.56 vpr 64.74 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29804 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66292 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 25.4 MiB 2.01 2505 986 14999 4213 8032 2754 64.7 MiB 0.08 0.00 5.95652 4.79778 -139.915 -4.79778 4.79778 0.25 0.000334016 0.000305104 0.0255084 0.0233651 -1 -1 -1 -1 32 2454 25 6.87369e+06 433189 586450. 2029.24 1.07 0.12617 0.110398 25474 144626 -1 1945 22 1516 2402 150206 37108 3.67906 3.67906 -131.28 -3.67906 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0168173 0.0149209 133 61 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_015.v common 3.07 vpr 64.52 MiB -1 -1 0.15 17676 1 0.02 -1 -1 29868 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66068 29 32 248 215 1 142 82 17 17 289 -1 unnamed_device 24.9 MiB 1.40 1696 858 12008 3401 6739 1868 64.5 MiB 0.05 0.00 3.78522 3.15872 -98.3476 -3.15872 3.15872 0.24 0.00026521 0.000242593 0.018962 0.017341 -1 -1 -1 -1 30 1702 24 6.87369e+06 293451 556674. 1926.21 0.33 0.0533522 0.046956 25186 138497 -1 1492 19 693 1109 62576 15355 2.83796 2.83796 -99.8638 -2.83796 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0116954 0.0103542 94 27 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 4.40 vpr 64.64 MiB -1 -1 0.19 18440 1 0.03 -1 -1 30168 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2351 1142 14908 4316 8497 2095 64.6 MiB 0.09 0.00 4.2467 3.7455 -126.819 -3.7455 3.7455 0.30 0.000339557 0.000310568 0.0292364 0.026805 -1 -1 -1 -1 32 2773 22 6.87369e+06 335372 586450. 2029.24 1.07 0.140584 0.122861 25474 144626 -1 2188 19 1521 2634 169491 39910 2.97426 2.97426 -122.17 -2.97426 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0158553 0.0142194 135 58 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 4.43 vpr 65.07 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29816 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66636 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 25.2 MiB 2.59 2594 1106 15639 5153 7404 3082 65.1 MiB 0.09 0.00 5.08229 4.18625 -135.173 -4.18625 4.18625 0.24 0.00034271 0.000315029 0.0333882 0.030975 -1 -1 -1 -1 30 2654 25 6.87369e+06 321398 556674. 1926.21 0.39 0.0779122 0.0697554 25186 138497 -1 2046 22 1375 2028 125721 30050 3.0509 3.0509 -118.831 -3.0509 0 0 706193. 2443.58 0.03 0.04 0.10 -1 -1 0.03 0.0182401 0.0161792 136 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 4.70 vpr 64.24 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30116 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 32 32 323 276 1 156 93 17 17 289 -1 unnamed_device 24.7 MiB 2.05 2257 926 17103 5432 9461 2210 64.2 MiB 0.13 0.00 3.68501 2.85191 -105.908 -2.85191 2.85191 0.25 0.000847649 0.000787011 0.0450084 0.0415445 -1 -1 -1 -1 32 2002 22 6.87369e+06 405241 586450. 2029.24 1.10 0.152835 0.134719 25474 144626 -1 1661 17 1142 1944 120028 29235 2.07352 2.07352 -97.0447 -2.07352 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0127224 0.0113475 110 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 2.78 vpr 63.89 MiB -1 -1 0.10 17528 1 0.02 -1 -1 29868 -1 -1 15 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65420 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 24.9 MiB 0.53 1506 681 11976 4667 6344 965 63.9 MiB 0.05 0.00 2.88898 2.40568 -84.2035 -2.40568 2.40568 0.35 0.000230573 0.000210344 0.0181275 0.0165527 -1 -1 -1 -1 34 1276 19 6.87369e+06 209608 618332. 2139.56 0.88 0.0736418 0.0640869 25762 151098 -1 1140 17 567 794 53109 12483 1.81522 1.81522 -81.3143 -1.81522 0 0 787024. 2723.27 0.03 0.02 0.08 -1 -1 0.03 0.00970028 0.00862224 71 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 4.51 vpr 64.20 MiB -1 -1 0.12 18060 1 0.02 -1 -1 29796 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65744 31 32 291 243 1 178 84 17 17 289 -1 unnamed_device 24.9 MiB 2.19 2220 961 14358 5263 6619 2476 64.2 MiB 0.08 0.00 6.07113 5.06873 -151.735 -5.06873 5.06873 0.25 0.000358414 0.000333638 0.0281325 0.0259646 -1 -1 -1 -1 30 2126 21 6.87369e+06 293451 556674. 1926.21 0.97 0.119718 0.104846 25186 138497 -1 1726 21 1006 1462 90107 22146 3.69941 3.69941 -133.261 -3.69941 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0147264 0.013189 114 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 3.28 vpr 64.35 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29956 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 24.9 MiB 0.78 2270 1098 17427 5042 9940 2445 64.3 MiB 0.10 0.00 5.48809 4.18395 -137.714 -4.18395 4.18395 0.25 0.000328306 0.000300353 0.0313602 0.0288796 -1 -1 -1 -1 28 2563 20 6.87369e+06 489084 531479. 1839.03 1.15 0.149045 0.131128 24610 126494 -1 2239 21 1371 2094 147615 35637 4.016 4.016 -141.152 -4.016 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0159409 0.014208 137 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_022.v common 4.53 vpr 64.32 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29916 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65868 32 32 372 300 1 206 87 17 17 289 -1 unnamed_device 24.9 MiB 1.91 2678 1260 15255 4028 9506 1721 64.3 MiB 0.10 0.00 5.24603 4.32815 -136.261 -4.32815 4.32815 0.25 0.000453897 0.000414665 0.0367843 0.0339982 -1 -1 -1 -1 30 2840 29 6.87369e+06 321398 556674. 1926.21 1.17 0.148596 0.131521 25186 138497 -1 2225 19 1315 2150 129279 30551 3.85476 3.85476 -132.586 -3.85476 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0156418 0.0140089 138 62 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 3.40 vpr 64.21 MiB -1 -1 0.10 18060 1 0.02 -1 -1 29792 -1 -1 18 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65748 26 32 190 182 1 108 76 17 17 289 -1 unnamed_device 25.2 MiB 1.35 1317 566 8396 2777 4117 1502 64.2 MiB 0.04 0.00 3.13338 2.41583 -71.9717 -2.41583 2.41583 0.25 0.000203836 0.000182325 0.0145818 0.0134291 -1 -1 -1 -1 26 1284 21 6.87369e+06 251529 503264. 1741.40 0.75 0.0793038 0.0686608 24322 120374 -1 1126 22 717 1085 75720 19389 2.17212 2.17212 -75.7209 -2.17212 0 0 618332. 2139.56 0.02 0.03 0.06 -1 -1 0.02 0.0101223 0.00893365 67 30 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 3.30 vpr 64.92 MiB -1 -1 0.12 17676 1 0.03 -1 -1 30152 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 285 227 1 169 88 17 17 289 -1 unnamed_device 24.9 MiB 0.94 2097 1049 14908 4450 8551 1907 64.9 MiB 0.08 0.00 5.2197 4.59222 -130.8 -4.59222 4.59222 0.24 0.000295354 0.0002705 0.0241002 0.0220402 -1 -1 -1 -1 32 2268 21 6.87369e+06 335372 586450. 2029.24 1.03 0.112059 0.0980207 25474 144626 -1 1966 21 1268 2283 143914 34546 3.7121 3.7121 -127.472 -3.7121 0 0 744469. 2576.02 0.03 0.04 0.09 -1 -1 0.03 0.014224 0.0126546 120 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 2.03 vpr 64.13 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29712 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65672 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 25.2 MiB 0.51 1340 735 9836 2832 5893 1111 64.1 MiB 0.03 0.00 2.66305 2.35478 -79.4936 -2.35478 2.35478 0.25 0.000195429 0.000177475 0.0131108 0.011945 -1 -1 -1 -1 28 1349 20 6.87369e+06 167686 531479. 1839.03 0.31 0.0383427 0.0336698 24610 126494 -1 1279 18 595 720 57806 14512 1.93882 1.93882 -81.3285 -1.93882 0 0 648988. 2245.63 0.02 0.03 0.07 -1 -1 0.02 0.011158 0.00985811 64 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 2.88 vpr 63.77 MiB -1 -1 0.12 18056 1 0.02 -1 -1 30152 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65304 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 24.9 MiB 0.98 2085 932 9892 2528 6924 440 63.8 MiB 0.11 0.00 5.60262 4.76542 -131.149 -4.76542 4.76542 0.30 0.000296832 0.000272087 0.035253 0.0326811 -1 -1 -1 -1 26 2518 22 6.87369e+06 419215 503264. 1741.40 0.49 0.0786368 0.0705901 24322 120374 -1 2096 32 1737 2939 210434 50691 3.872 3.872 -127.362 -3.872 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0198711 0.0174655 120 24 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 3.39 vpr 64.89 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29944 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66452 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 24.9 MiB 0.79 2474 1054 16727 4817 9341 2569 64.9 MiB 0.09 0.00 4.54391 3.51795 -111.316 -3.51795 3.51795 0.29 0.000303592 0.000276236 0.0266519 0.0242859 -1 -1 -1 -1 28 2471 24 6.87369e+06 433189 531479. 1839.03 1.06 0.125733 0.110248 24610 126494 -1 2110 19 1290 2308 150392 36562 2.98246 2.98246 -112.166 -2.98246 0 0 648988. 2245.63 0.02 0.04 0.14 -1 -1 0.02 0.014283 0.0127629 130 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_028.v common 3.50 vpr 65.02 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29752 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 338 277 1 183 93 17 17 289 -1 unnamed_device 25.0 MiB 1.17 2236 1093 11433 2910 6842 1681 65.0 MiB 0.06 0.00 5.66492 4.81048 -136.943 -4.81048 4.81048 0.25 0.000325641 0.000298897 0.0192171 0.0176088 -1 -1 -1 -1 30 2323 24 6.87369e+06 405241 556674. 1926.21 0.99 0.124524 0.108552 25186 138497 -1 1955 23 1075 1929 108605 26660 3.99996 3.99996 -133.755 -3.99996 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0163959 0.0145775 128 50 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_029.v common 2.55 vpr 64.41 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29808 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65960 32 32 284 241 1 148 82 17 17 289 -1 unnamed_device 24.9 MiB 0.78 1785 959 11118 3077 6379 1662 64.4 MiB 0.06 0.00 3.63792 3.01142 -107.753 -3.01142 3.01142 0.35 0.000279667 0.000255769 0.0214261 0.019741 -1 -1 -1 -1 32 1994 19 6.87369e+06 251529 586450. 2029.24 0.35 0.0582033 0.0516193 25474 144626 -1 1714 18 879 1436 101674 23709 2.60666 2.60666 -105.374 -2.60666 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.012868 0.011506 101 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.41 vpr 64.49 MiB -1 -1 0.11 17912 1 0.02 -1 -1 29832 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66040 30 32 262 227 1 138 84 17 17 289 -1 unnamed_device 24.9 MiB 0.91 1644 645 11979 4232 5199 2548 64.5 MiB 0.06 0.00 3.71922 3.04032 -95.3449 -3.04032 3.04032 0.24 0.000643706 0.000601065 0.0220199 0.0202565 -1 -1 -1 -1 34 1737 24 6.87369e+06 307425 618332. 2139.56 1.12 0.115953 0.101499 25762 151098 -1 1305 21 903 1431 87262 23733 2.94926 2.94926 -95.9302 -2.94926 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0131376 0.0116079 95 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 3.63 vpr 63.98 MiB -1 -1 0.18 17676 1 0.03 -1 -1 29688 -1 -1 19 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65516 28 32 260 223 1 140 79 17 17 289 -1 unnamed_device 24.9 MiB 1.12 2176 705 11233 3031 6920 1282 64.0 MiB 0.05 0.00 4.53245 3.58631 -100.001 -3.58631 3.58631 0.24 0.000258351 0.000236282 0.018592 0.0170282 -1 -1 -1 -1 34 1817 24 6.87369e+06 265503 618332. 2139.56 1.09 0.101843 0.0884679 25762 151098 -1 1498 21 1087 2028 123464 32422 2.82496 2.82496 -100.192 -2.82496 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0132302 0.0117007 96 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_032.v common 3.29 vpr 64.43 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30216 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65972 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 24.7 MiB 1.03 2154 721 8092 1745 5645 702 64.4 MiB 0.04 0.00 4.63718 3.86314 -115.034 -3.86314 3.86314 0.26 0.000269999 0.000245848 0.0141003 0.0128609 -1 -1 -1 -1 32 1894 22 6.87369e+06 251529 586450. 2029.24 1.00 0.0989113 0.085688 25474 144626 -1 1497 16 987 1649 88162 23720 2.96326 2.96326 -109.749 -2.96326 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110703 0.00990835 101 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_033.v common 2.78 vpr 64.53 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29760 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 31 32 271 231 1 149 89 17 17 289 -1 unnamed_device 24.9 MiB 0.78 1850 927 12563 3215 8032 1316 64.5 MiB 0.06 0.00 4.00125 3.42265 -107.908 -3.42265 3.42265 0.27 0.000276398 0.000253509 0.0189718 0.0173754 -1 -1 -1 -1 32 1906 22 6.87369e+06 363320 586450. 2029.24 0.42 0.0676784 0.0597762 25474 144626 -1 1629 20 901 1604 91239 22844 2.75166 2.75166 -105.307 -2.75166 0 0 744469. 2576.02 0.04 0.05 0.14 -1 -1 0.04 0.0210922 0.018721 102 30 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 4.49 vpr 64.58 MiB -1 -1 0.18 18060 1 0.03 -1 -1 30212 -1 -1 25 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66128 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 24.9 MiB 2.38 2244 863 12938 3817 7914 1207 64.6 MiB 0.06 0.00 3.77556 3.08002 -100.294 -3.08002 3.08002 0.25 0.000282356 0.000258955 0.0207796 0.0190526 -1 -1 -1 -1 30 1838 22 6.87369e+06 349346 556674. 1926.21 0.69 0.093284 0.0814168 25186 138497 -1 1561 17 902 1386 82031 19933 2.25347 2.25347 -93.7602 -2.25347 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0118709 0.010591 105 54 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_035.v common 5.18 vpr 65.22 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29612 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 32 32 367 282 1 201 104 17 17 289 -1 unnamed_device 25.2 MiB 2.42 2344 1146 10352 2228 7273 851 65.2 MiB 0.07 0.00 4.92569 4.24719 -123.08 -4.24719 4.24719 0.27 0.000368919 0.000338189 0.0189776 0.0174183 -1 -1 -1 -1 28 2900 23 6.87369e+06 558954 531479. 1839.03 1.33 0.141629 0.123881 24610 126494 -1 2537 22 1665 3171 206581 51344 4.0723 4.0723 -130.143 -4.0723 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0174867 0.0155615 156 29 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_036.v common 4.25 vpr 64.88 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30132 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 391 311 1 194 104 17 17 289 -1 unnamed_device 24.8 MiB 2.37 2402 1081 18892 5390 10690 2812 64.9 MiB 0.10 0.00 4.68095 4.00848 -135.306 -4.00848 4.00848 0.24 0.000357663 0.00032748 0.0300492 0.0273707 -1 -1 -1 -1 32 2374 22 6.87369e+06 558954 586450. 2029.24 0.39 0.0788336 0.06992 25474 144626 -1 2026 19 1508 2475 143567 35245 3.17446 3.17446 -127.465 -3.17446 0 0 744469. 2576.02 0.03 0.04 0.16 -1 -1 0.03 0.0159635 0.0142608 149 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 3.90 vpr 64.01 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29492 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65544 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 24.9 MiB 1.82 2434 993 8831 2488 5523 820 64.0 MiB 0.05 0.00 4.95083 4.14789 -126.829 -4.14789 4.14789 0.25 0.000284845 0.000261619 0.0156499 0.0143835 -1 -1 -1 -1 32 2206 21 6.87369e+06 251529 586450. 2029.24 0.39 0.0531276 0.0469574 25474 144626 -1 1881 19 958 1525 103993 24504 3.15461 3.15461 -119.875 -3.15461 0 0 744469. 2576.02 0.04 0.05 0.14 -1 -1 0.04 0.0169656 0.0150243 106 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_038.v common 4.62 vpr 65.14 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29212 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66704 31 32 370 297 1 187 89 17 17 289 -1 unnamed_device 25.6 MiB 1.93 2217 1129 14147 4459 7560 2128 65.1 MiB 0.14 0.00 4.3461 3.7686 -123.743 -3.7686 3.7686 0.28 0.000620839 0.000567351 0.0472881 0.0432612 -1 -1 -1 -1 32 2620 20 6.87369e+06 363320 586450. 2029.24 1.22 0.166856 0.146757 25474 144626 -1 2210 20 1429 2447 155773 36552 3.00426 3.00426 -116.646 -3.00426 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0161313 0.0143767 136 61 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_039.v common 6.59 vpr 65.16 MiB -1 -1 0.17 18292 1 0.03 -1 -1 30164 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66720 31 32 377 302 1 237 92 17 17 289 -1 unnamed_device 25.3 MiB 2.75 2915 1335 13547 3729 7970 1848 65.2 MiB 0.09 0.00 6.76692 5.53978 -169.274 -5.53978 5.53978 0.26 0.000351561 0.000322679 0.025746 0.0236688 -1 -1 -1 -1 28 3654 23 6.87369e+06 405241 531479. 1839.03 2.34 0.14442 0.126946 24610 126494 -1 2988 22 2444 3552 326119 72975 5.20869 5.20869 -174.053 -5.20869 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0175115 0.0155948 155 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_040.v common 5.04 vpr 65.22 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29792 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 31 32 383 305 1 212 91 17 17 289 -1 unnamed_device 25.2 MiB 3.04 2741 1334 14575 4470 8160 1945 65.2 MiB 0.09 0.00 6.34854 5.22459 -163.482 -5.22459 5.22459 0.25 0.000351439 0.000321335 0.0270274 0.0247642 -1 -1 -1 -1 32 3169 36 6.87369e+06 391268 586450. 2029.24 0.53 0.0967574 0.0859341 25474 144626 -1 2624 20 1587 2410 208304 44942 4.5599 4.5599 -158.949 -4.5599 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164815 0.0147252 151 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 4.03 vpr 64.61 MiB -1 -1 0.18 18060 1 0.04 -1 -1 29768 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66160 31 32 352 285 1 186 92 17 17 289 -1 unnamed_device 24.9 MiB 2.19 2134 1048 14996 4681 7704 2611 64.6 MiB 0.08 0.00 4.61893 4.13563 -128.575 -4.13563 4.13563 0.24 0.000335656 0.000307486 0.025684 0.0235144 -1 -1 -1 -1 32 2650 22 6.87369e+06 405241 586450. 2029.24 0.39 0.0700836 0.0620377 25474 144626 -1 2076 22 1454 2414 153424 36772 3.09131 3.09131 -118.471 -3.09131 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0166059 0.0147621 133 55 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 4.06 vpr 64.91 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29768 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 291 242 1 183 86 17 17 289 -1 unnamed_device 24.9 MiB 1.85 2477 1095 15206 4442 8662 2102 64.9 MiB 0.08 0.00 5.51278 4.43075 -121.679 -4.43075 4.43075 0.25 0.000292028 0.0002669 0.0253669 0.0232324 -1 -1 -1 -1 28 2503 21 6.87369e+06 307425 531479. 1839.03 0.90 0.105951 0.0925844 24610 126494 -1 2252 18 1382 2015 133917 32844 4.15256 4.15256 -127.257 -4.15256 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0130387 0.0116467 114 27 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_043.v common 5.91 vpr 65.00 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29896 -1 -1 40 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 32 32 457 356 1 225 104 17 17 289 -1 unnamed_device 25.6 MiB 2.42 3065 1148 12304 2744 8146 1414 65.0 MiB 0.07 0.00 6.15708 4.89003 -155.75 -4.89003 4.89003 0.35 0.000421745 0.000385657 0.023456 0.0215124 -1 -1 -1 -1 30 3162 34 6.87369e+06 558954 556674. 1926.21 1.94 0.208648 0.182713 25186 138497 -1 2244 22 1501 2532 144540 36667 4.07996 4.07996 -146.784 -4.07996 0 0 706193. 2443.58 0.03 0.06 0.08 -1 -1 0.03 0.0238413 0.0212161 173 87 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_044.v common 3.27 vpr 64.49 MiB -1 -1 0.11 16980 1 0.03 -1 -1 29852 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 31 32 261 225 1 148 83 17 17 289 -1 unnamed_device 24.9 MiB 1.60 1997 648 8723 1892 5777 1054 64.5 MiB 0.04 0.00 4.27085 3.54105 -101.242 -3.54105 3.54105 0.24 0.000273941 0.000251112 0.0141802 0.0129943 -1 -1 -1 -1 30 1800 23 6.87369e+06 279477 556674. 1926.21 0.38 0.0500756 0.0439754 25186 138497 -1 1451 23 1102 1888 103072 27957 2.98326 2.98326 -102.512 -2.98326 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0136731 0.0120739 95 28 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_045.v common 5.40 vpr 65.09 MiB -1 -1 0.12 18064 1 0.03 -1 -1 29856 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66656 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 25.2 MiB 2.38 2833 1039 9058 2162 5891 1005 65.1 MiB 0.05 0.00 5.78298 4.80948 -141.445 -4.80948 4.80948 0.24 0.000334797 0.000307237 0.0177481 0.0163442 -1 -1 -1 -1 32 3153 40 6.87369e+06 349346 586450. 2029.24 1.70 0.143091 0.124424 25474 144626 -1 2143 18 1358 2000 125184 32958 3.90446 3.90446 -133.851 -3.90446 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0142968 0.0128029 139 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_046.v common 3.83 vpr 64.51 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29712 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66060 32 32 349 284 1 183 96 17 17 289 -1 unnamed_device 24.8 MiB 1.34 2291 1135 16740 4742 9662 2336 64.5 MiB 0.09 0.00 4.4574 3.7235 -119.349 -3.7235 3.7235 0.24 0.000325745 0.0002983 0.0287406 0.0263737 -1 -1 -1 -1 32 2604 22 6.87369e+06 447163 586450. 2029.24 1.09 0.136222 0.119082 25474 144626 -1 2160 22 1397 2353 160693 37464 2.99951 2.99951 -114.657 -2.99951 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164752 0.014613 133 53 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_047.v common 3.46 vpr 64.45 MiB -1 -1 0.14 17676 1 0.03 -1 -1 29764 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 1.06 1933 1125 13963 5217 7708 1038 64.5 MiB 0.08 0.00 4.86339 4.12259 -128.092 -4.12259 4.12259 0.34 0.000311483 0.000285719 0.023139 0.021179 -1 -1 -1 -1 30 2522 22 6.87369e+06 377294 556674. 1926.21 0.94 0.103938 0.0910827 25186 138497 -1 2070 22 1119 2125 158916 33999 3.6151 3.6151 -123.407 -3.6151 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0149392 0.0132718 123 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_048.v common 4.70 vpr 64.43 MiB -1 -1 0.12 18436 1 0.03 -1 -1 30156 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65976 32 32 353 287 1 203 88 17 17 289 -1 unnamed_device 25.1 MiB 2.35 2449 1198 10033 2856 6133 1044 64.4 MiB 0.08 0.00 5.38385 4.51686 -135.093 -4.51686 4.51686 0.24 0.000807747 0.000754987 0.0265271 0.0244839 -1 -1 -1 -1 28 2785 20 6.87369e+06 335372 531479. 1839.03 1.01 0.122769 0.108079 24610 126494 -1 2415 23 1599 2149 149891 36230 3.45411 3.45411 -130.575 -3.45411 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0173931 0.0154887 133 55 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_049.v common 4.46 vpr 64.64 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29752 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 361 291 1 189 97 17 17 289 -1 unnamed_device 25.2 MiB 2.43 2368 918 12307 3182 8052 1073 64.6 MiB 0.07 0.00 4.4072 3.86034 -120.004 -3.86034 3.86034 0.35 0.00033864 0.000309864 0.0204635 0.0187149 -1 -1 -1 -1 32 2307 29 6.87369e+06 461137 586450. 2029.24 0.44 0.0695487 0.0614194 25474 144626 -1 1780 19 1175 2009 111141 30153 3.17181 3.17181 -113.554 -3.17181 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0255044 0.0228037 137 55 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_050.v common 4.27 vpr 65.20 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30244 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 32 32 382 305 1 193 99 17 17 289 -1 unnamed_device 25.2 MiB 2.29 2780 1180 19251 5845 10953 2453 65.2 MiB 0.11 0.00 4.88053 4.12873 -137.656 -4.12873 4.12873 0.25 0.000352547 0.000322509 0.0316187 0.0288943 -1 -1 -1 -1 30 2658 24 6.87369e+06 489084 556674. 1926.21 0.42 0.0788497 0.0700438 25186 138497 -1 2203 22 1272 2103 125088 30094 3.13881 3.13881 -123.39 -3.13881 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0173831 0.0154972 145 62 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 3.73 vpr 64.93 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29780 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 306 248 1 170 97 17 17 289 -1 unnamed_device 24.9 MiB 0.73 2039 950 16747 5537 7489 3721 64.9 MiB 0.09 0.00 4.87439 4.39109 -126.937 -4.39109 4.39109 0.24 0.000739823 0.00069028 0.0312699 0.0286694 -1 -1 -1 -1 32 2421 33 6.87369e+06 461137 586450. 2029.24 1.56 0.147368 0.129021 25474 144626 -1 1887 19 1239 2208 161661 39936 3.8374 3.8374 -122.561 -3.8374 0 0 744469. 2576.02 0.04 0.07 0.11 -1 -1 0.04 0.0221875 0.0198695 124 24 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 3.98 vpr 63.73 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29584 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65256 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 24.7 MiB 1.52 2220 1156 13527 3541 8079 1907 63.7 MiB 0.08 0.00 5.73418 4.82931 -141.931 -4.82931 4.82931 0.25 0.00030882 0.000282743 0.0239023 0.0219138 -1 -1 -1 -1 32 2802 25 6.87369e+06 321398 586450. 2029.24 1.00 0.110833 0.096714 25474 144626 -1 2292 20 1462 2137 136001 32714 3.76576 3.76576 -131.742 -3.76576 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0146108 0.0130258 129 29 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 3.68 vpr 64.53 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 24 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 31 32 373 299 1 204 87 17 17 289 -1 unnamed_device 25.0 MiB 1.72 3065 1027 11415 2970 7272 1173 64.5 MiB 0.14 0.00 6.22918 4.75448 -142.391 -4.75448 4.75448 0.28 0.000987483 0.000915055 0.0501293 0.0464441 -1 -1 -1 -1 32 2875 29 6.87369e+06 335372 586450. 2029.24 0.48 0.0988957 0.0888001 25474 144626 -1 2254 24 1603 2664 177040 43531 3.86846 3.86846 -138.859 -3.86846 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0184397 0.0164021 140 62 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 5.11 vpr 64.59 MiB -1 -1 0.13 18056 1 0.04 -1 -1 30260 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 32 32 387 315 1 194 86 17 17 289 -1 unnamed_device 25.2 MiB 2.03 2512 933 14072 5096 6356 2620 64.6 MiB 0.08 0.00 5.37753 4.33435 -129.429 -4.33435 4.33435 0.26 0.00035546 0.000324775 0.0324406 0.0297238 -1 -1 -1 -1 36 2716 47 6.87369e+06 307425 648988. 2245.63 1.52 0.178156 0.156102 26050 158493 -1 1916 20 1476 2587 164969 42265 3.74066 3.74066 -126.184 -3.74066 0 0 828058. 2865.25 0.03 0.05 0.16 -1 -1 0.03 0.016656 0.0148392 134 77 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 2.54 vpr 64.50 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29788 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 251 219 1 141 87 17 17 289 -1 unnamed_device 24.7 MiB 0.72 1844 681 8727 1897 6216 614 64.5 MiB 0.04 0.00 4.11555 3.50043 -101.627 -3.50043 3.50043 0.24 0.000263113 0.000240025 0.0133071 0.0121657 -1 -1 -1 -1 28 2084 39 6.87369e+06 321398 531479. 1839.03 0.52 0.0574569 0.050311 24610 126494 -1 1578 21 1147 1792 117952 31406 2.70196 2.70196 -100.629 -2.70196 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0127218 0.0112708 93 23 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 3.75 vpr 64.36 MiB -1 -1 0.12 18060 1 0.04 -1 -1 30204 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65908 32 32 341 285 1 188 84 17 17 289 -1 unnamed_device 25.2 MiB 1.54 2256 885 8868 2113 6056 699 64.4 MiB 0.05 0.00 4.91669 4.05749 -134.722 -4.05749 4.05749 0.25 0.000319097 0.00029131 0.0168116 0.0154068 -1 -1 -1 -1 32 2587 38 6.87369e+06 279477 586450. 2029.24 0.66 0.0980793 0.0867185 25474 144626 -1 1878 20 1605 2345 172300 41500 3.30791 3.30791 -127.081 -3.30791 0 0 744469. 2576.02 0.03 0.10 0.08 -1 -1 0.03 0.0359951 0.0321136 120 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 4.72 vpr 65.30 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29816 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66864 32 32 387 293 1 236 93 17 17 289 -1 unnamed_device 25.6 MiB 2.03 2858 1452 14373 4135 8862 1376 65.3 MiB 0.09 0.00 6.54252 5.67053 -168.179 -5.67053 5.67053 0.26 0.000367846 0.000336898 0.0279177 0.0256551 -1 -1 -1 -1 32 3361 38 6.87369e+06 405241 586450. 2029.24 1.27 0.174645 0.153213 25474 144626 -1 2769 22 1643 2597 165910 40569 4.6651 4.6651 -156.548 -4.6651 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0186054 0.0166428 164 31 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_058.v common 3.95 vpr 64.71 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29944 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 32 32 340 270 1 185 98 17 17 289 -1 unnamed_device 25.2 MiB 2.19 2646 1109 17198 4503 10702 1993 64.7 MiB 0.09 0.00 5.22181 4.34585 -138.752 -4.34585 4.34585 0.24 0.000328609 0.000299932 0.0269673 0.0246622 -1 -1 -1 -1 32 2400 41 6.87369e+06 475111 586450. 2029.24 0.39 0.0787899 0.0696865 25474 144626 -1 1955 21 1277 2204 125556 30508 2.86466 2.86466 -118.79 -2.86466 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.01591 0.0142043 137 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_059.v common 2.33 vpr 64.59 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29824 -1 -1 25 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66140 30 32 278 235 1 150 87 17 17 289 -1 unnamed_device 25.2 MiB 0.61 2187 808 9879 2531 6399 949 64.6 MiB 0.05 0.00 4.30385 3.42675 -104.9 -3.42675 3.42675 0.24 0.000283569 0.000258971 0.0157083 0.0143422 -1 -1 -1 -1 26 2066 25 6.87369e+06 349346 503264. 1741.40 0.40 0.0537143 0.0471404 24322 120374 -1 1867 26 1418 2313 162293 41447 3.43946 3.43946 -116.403 -3.43946 0 0 618332. 2139.56 0.02 0.06 0.07 -1 -1 0.02 0.0217145 0.0191615 104 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_060.v common 5.58 vpr 65.42 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29800 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66992 32 32 431 332 1 239 91 17 17 289 -1 unnamed_device 25.6 MiB 3.74 2820 1401 12535 3692 7672 1171 65.4 MiB 0.08 0.00 6.88686 5.84665 -173.286 -5.84665 5.84665 0.24 0.000419434 0.000387317 0.0280962 0.0259362 -1 -1 -1 -1 32 3289 23 6.87369e+06 377294 586450. 2029.24 0.45 0.0856957 0.0766235 25474 144626 -1 2597 22 1840 2810 199075 44926 4.4923 4.4923 -155.353 -4.4923 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0201657 0.0180183 166 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 4.33 vpr 64.54 MiB -1 -1 0.19 18448 1 0.03 -1 -1 29960 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66084 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 24.9 MiB 2.38 2019 1059 12867 3257 7846 1764 64.5 MiB 0.08 0.00 5.26892 4.63938 -140.042 -4.63938 4.63938 0.33 0.000319991 0.000293027 0.0261935 0.0241675 -1 -1 -1 -1 32 2403 25 6.87369e+06 489084 586450. 2029.24 0.40 0.0756114 0.0675688 25474 144626 -1 1978 19 1375 2255 145823 36321 3.5567 3.5567 -129.487 -3.5567 0 0 744469. 2576.02 0.03 0.05 0.09 -1 -1 0.03 0.0171303 0.0153048 135 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_062.v common 2.49 vpr 64.31 MiB -1 -1 0.11 17148 1 0.02 -1 -1 30328 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 25.2 MiB 0.63 1762 855 12512 3348 8365 799 64.3 MiB 0.05 0.00 3.96025 3.6312 -105.59 -3.6312 3.6312 0.24 0.000255426 0.000233116 0.0167194 0.015257 -1 -1 -1 -1 28 1989 22 6.87369e+06 391268 531479. 1839.03 0.34 0.0495916 0.0435939 24610 126494 -1 1736 22 999 1747 115875 28970 2.92726 2.92726 -105.066 -2.92726 0 0 648988. 2245.63 0.04 0.06 0.12 -1 -1 0.04 0.0205974 0.0181628 96 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 4.97 vpr 65.02 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29572 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 349 273 1 191 101 17 17 289 -1 unnamed_device 25.6 MiB 1.72 2736 1219 17491 4613 10519 2359 65.0 MiB 0.10 0.00 6.69567 5.1464 -138.872 -5.1464 5.1464 0.31 0.000341259 0.000311913 0.0305984 0.0281463 -1 -1 -1 -1 26 2928 24 6.87369e+06 517032 503264. 1741.40 1.78 0.151555 0.13355 24322 120374 -1 2550 23 1721 3309 237917 56001 4.68785 4.68785 -144.023 -4.68785 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.017333 0.0153937 145 29 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 2.60 vpr 64.46 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30196 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 25.2 MiB 0.94 2118 750 9385 2715 5945 725 64.5 MiB 0.05 0.00 4.52145 3.49353 -105.466 -3.49353 3.49353 0.24 0.000265033 0.000242603 0.0146375 0.0133717 -1 -1 -1 -1 32 1967 23 6.87369e+06 293451 586450. 2029.24 0.35 0.0505078 0.0444585 25474 144626 -1 1595 20 1184 2094 130220 31374 2.83596 2.83596 -104.337 -2.83596 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0123439 0.0109405 99 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 4.46 vpr 64.53 MiB -1 -1 0.16 17676 1 0.03 -1 -1 29828 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 30 32 278 235 1 151 96 17 17 289 -1 unnamed_device 25.4 MiB 1.69 2241 719 10608 2312 6839 1457 64.5 MiB 0.07 0.00 4.84748 3.98828 -113.215 -3.98828 3.98828 0.25 0.000391645 0.000367026 0.0289935 0.0271019 -1 -1 -1 -1 28 2331 36 6.87369e+06 475111 531479. 1839.03 1.39 0.12692 0.111488 24610 126494 -1 1678 21 1245 2215 142434 39295 3.33286 3.33286 -116.77 -3.33286 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0160478 0.0141015 109 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 4.89 vpr 65.07 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 26 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66632 29 32 355 287 1 200 87 17 17 289 -1 unnamed_device 25.2 MiB 2.10 2696 974 15831 5641 7207 2983 65.1 MiB 0.09 0.00 5.17922 4.15337 -121.297 -4.15337 4.15337 0.24 0.000328376 0.000300502 0.0322937 0.0296945 -1 -1 -1 -1 34 2718 23 6.87369e+06 363320 618332. 2139.56 1.42 0.164397 0.143584 25762 151098 -1 2026 21 1484 2291 146376 37672 3.47616 3.47616 -116.825 -3.47616 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0161593 0.0144132 136 62 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_067.v common 3.68 vpr 64.94 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29776 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 358 289 1 183 90 17 17 289 -1 unnamed_device 25.0 MiB 1.76 2016 1105 14160 4101 8351 1708 64.9 MiB 0.08 0.00 5.27855 4.41935 -143.334 -4.41935 4.41935 0.24 0.000346002 0.000316456 0.0278664 0.0255617 -1 -1 -1 -1 32 2363 23 6.87369e+06 363320 586450. 2029.24 0.46 0.08495 0.0752392 25474 144626 -1 2046 21 1489 2340 158892 36945 3.6681 3.6681 -134.244 -3.6681 0 0 744469. 2576.02 0.03 0.05 0.16 -1 -1 0.03 0.016676 0.0148494 132 54 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_068.v common 3.76 vpr 65.11 MiB -1 -1 0.16 18056 1 0.03 -1 -1 30160 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66676 32 32 353 285 1 188 93 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2553 1054 11433 3167 7604 662 65.1 MiB 0.07 0.00 5.94852 4.77748 -139.018 -4.77748 4.77748 0.24 0.000334015 0.000305667 0.0198564 0.0181388 -1 -1 -1 -1 32 2558 25 6.87369e+06 405241 586450. 2029.24 0.40 0.0648189 0.0572644 25474 144626 -1 2013 22 1396 2524 151194 37389 3.71836 3.71836 -131.742 -3.71836 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.02815 0.0249344 134 51 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_069.v common 4.73 vpr 64.56 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30160 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66112 32 32 276 237 1 165 82 17 17 289 -1 unnamed_device 24.9 MiB 2.17 1940 852 6668 1493 4863 312 64.6 MiB 0.04 0.00 5.16415 4.88031 -136.568 -4.88031 4.88031 0.33 0.000282263 0.00025852 0.0119638 0.0109757 -1 -1 -1 -1 26 2532 37 6.87369e+06 251529 503264. 1741.40 1.14 0.0984009 0.0854727 24322 120374 -1 1898 19 1074 1463 105865 29212 3.47621 3.47621 -124.999 -3.47621 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.0128064 0.0114271 102 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_070.v common 4.05 vpr 64.92 MiB -1 -1 0.18 18048 1 0.03 -1 -1 30180 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 31 32 319 272 1 176 83 17 17 289 -1 unnamed_device 25.2 MiB 2.04 2174 1028 12503 3213 7830 1460 64.9 MiB 0.07 0.00 4.4732 3.7214 -122.26 -3.7214 3.7214 0.25 0.00040486 0.000356531 0.029162 0.0270087 -1 -1 -1 -1 32 2289 30 6.87369e+06 279477 586450. 2029.24 0.38 0.0734498 0.0653217 25474 144626 -1 1934 22 1164 1724 125099 29725 3.28891 3.28891 -122.449 -3.28891 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0151763 0.0134859 110 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_071.v common 4.41 vpr 64.98 MiB -1 -1 0.18 18436 1 0.03 -1 -1 30304 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66544 30 32 329 273 1 167 96 17 17 289 -1 unnamed_device 25.2 MiB 1.97 2361 965 13236 3751 8252 1233 65.0 MiB 0.07 0.00 4.47245 3.48795 -100.051 -3.48795 3.48795 0.25 0.00036336 0.000336979 0.0214233 0.0195433 -1 -1 -1 -1 30 1999 23 6.87369e+06 475111 556674. 1926.21 1.02 0.112542 0.0980759 25186 138497 -1 1729 16 946 1790 90841 23393 2.93826 2.93826 -100.371 -2.93826 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.0155344 0.0138624 124 57 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_072.v common 3.05 vpr 64.84 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29812 -1 -1 35 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66396 28 32 277 229 1 156 95 17 17 289 -1 unnamed_device 25.2 MiB 1.29 1945 924 16079 4874 9529 1676 64.8 MiB 0.07 0.00 5.23859 4.10437 -105.39 -4.10437 4.10437 0.25 0.000282598 0.000259458 0.0221159 0.02018 -1 -1 -1 -1 26 2118 21 6.87369e+06 489084 503264. 1741.40 0.47 0.0647093 0.0572097 24322 120374 -1 1838 21 1280 2507 173302 41037 3.6161 3.6161 -108.097 -3.6161 0 0 618332. 2139.56 0.03 0.05 0.06 -1 -1 0.03 0.0148899 0.0133326 117 27 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 5.59 vpr 64.57 MiB -1 -1 0.18 18060 1 0.03 -1 -1 29836 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 30 32 317 269 1 155 80 17 17 289 -1 unnamed_device 24.9 MiB 2.37 2041 784 11088 4549 5689 850 64.6 MiB 0.09 0.00 4.60788 3.85608 -116.241 -3.85608 3.85608 0.26 0.000373926 0.000343506 0.0399959 0.0370619 -1 -1 -1 -1 28 2449 50 6.87369e+06 251529 531479. 1839.03 1.69 0.171036 0.150399 24610 126494 -1 1896 24 1646 2865 221151 58757 3.15776 3.15776 -117.819 -3.15776 0 0 648988. 2245.63 0.02 0.06 0.09 -1 -1 0.02 0.015881 0.0140268 105 63 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 4.14 vpr 65.02 MiB -1 -1 0.15 17916 1 0.03 -1 -1 29628 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66584 32 32 335 282 1 189 84 17 17 289 -1 unnamed_device 25.6 MiB 1.66 2218 967 9966 2748 6633 585 65.0 MiB 0.06 0.00 5.10429 3.99449 -129.503 -3.99449 3.99449 0.25 0.000328462 0.000301649 0.020079 0.0184308 -1 -1 -1 -1 32 2511 25 6.87369e+06 279477 586450. 2029.24 1.09 0.117666 0.102422 25474 144626 -1 2008 18 1211 1757 119685 28936 3.4488 3.4488 -126.894 -3.4488 0 0 744469. 2576.02 0.04 0.06 0.08 -1 -1 0.04 0.023357 0.0207862 118 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_075.v common 3.32 vpr 64.91 MiB -1 -1 0.12 17916 1 0.03 -1 -1 29900 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66468 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.9 MiB 0.79 2036 1158 10170 2450 6680 1040 64.9 MiB 0.06 0.00 5.31102 4.59912 -134.752 -4.59912 4.59912 0.27 0.000342506 0.000316632 0.0162185 0.0148702 -1 -1 -1 -1 32 2499 23 6.87369e+06 461137 586450. 2029.24 1.11 0.129327 0.112575 25474 144626 -1 2100 22 1224 2150 133245 32520 3.6524 3.6524 -124.426 -3.6524 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0168294 0.014975 130 4 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 4.44 vpr 65.12 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29968 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 25.2 MiB 2.45 2819 1040 12178 3350 7228 1600 65.1 MiB 0.09 0.00 5.70484 4.82048 -149.342 -4.82048 4.82048 0.26 0.000400944 0.000372604 0.0283893 0.026235 -1 -1 -1 -1 32 3002 29 6.87369e+06 335372 586450. 2029.24 0.60 0.0908346 0.081116 25474 144626 -1 2195 18 1476 2286 156593 38820 3.90405 3.90405 -139.251 -3.90405 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0148102 0.0132845 141 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 5.94 vpr 65.12 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30176 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66688 32 32 385 308 1 195 101 17 17 289 -1 unnamed_device 25.6 MiB 3.09 2653 1152 16316 4343 10844 1129 65.1 MiB 0.08 0.00 6.91417 5.25048 -151.042 -5.25048 5.25048 0.24 0.000352849 0.000323511 0.0264732 0.0241542 -1 -1 -1 -1 28 2872 20 6.87369e+06 517032 531479. 1839.03 1.50 0.125407 0.110692 24610 126494 -1 2428 23 1830 3262 241216 56854 3.93035 3.93035 -146.382 -3.93035 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0181598 0.0161266 147 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_078.v common 5.07 vpr 65.23 MiB -1 -1 0.18 18048 1 0.03 -1 -1 30240 -1 -1 41 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66796 32 32 387 309 1 192 105 17 17 289 -1 unnamed_device 25.2 MiB 2.38 2943 1241 19618 5694 11739 2185 65.2 MiB 0.24 0.00 5.98952 4.52582 -145.898 -4.52582 4.52582 0.24 0.000822808 0.000763121 0.0762442 0.0705218 -1 -1 -1 -1 30 2850 25 6.87369e+06 572927 556674. 1926.21 1.09 0.176382 0.157475 25186 138497 -1 2346 21 1345 2673 179539 40524 3.5128 3.5128 -133.556 -3.5128 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0169879 0.0151336 148 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 3.71 vpr 64.45 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29504 -1 -1 18 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 30 32 272 232 1 151 80 17 17 289 -1 unnamed_device 24.7 MiB 1.97 2072 788 12808 4627 5785 2396 64.4 MiB 0.06 0.00 4.73318 3.87398 -115.445 -3.87398 3.87398 0.24 0.000270734 0.000246942 0.0216325 0.0197871 -1 -1 -1 -1 32 2109 26 6.87369e+06 251529 586450. 2029.24 0.39 0.0619366 0.0547203 25474 144626 -1 1731 21 1247 2177 152375 36953 2.94096 2.94096 -109.117 -2.94096 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.013509 0.0119628 99 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 5.31 vpr 64.71 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30528 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66264 30 32 375 299 1 188 85 17 17 289 -1 unnamed_device 25.4 MiB 2.75 2081 1069 9943 2328 6646 969 64.7 MiB 0.07 0.00 5.31292 4.64076 -144.318 -4.64076 4.64076 0.24 0.000345453 0.000316854 0.0247669 0.0228435 -1 -1 -1 -1 26 2497 31 6.87369e+06 321398 503264. 1741.40 1.21 0.124009 0.109075 24322 120374 -1 2213 21 1786 2855 199315 47103 3.8714 3.8714 -142.891 -3.8714 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0221423 0.0198078 137 63 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 4.20 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29864 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 25.7 MiB 1.66 2664 1115 14741 4886 7454 2401 65.1 MiB 0.09 0.00 5.92334 5.22106 -152.202 -5.22106 5.22106 0.25 0.000334817 0.000306968 0.0281764 0.0259055 -1 -1 -1 -1 30 2721 24 6.87369e+06 349346 556674. 1926.21 1.15 0.126827 0.11113 25186 138497 -1 2014 20 1447 2533 138886 35336 3.89246 3.89246 -136.446 -3.89246 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0169656 0.0152085 136 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 4.71 vpr 65.10 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30172 -1 -1 30 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 31 32 340 275 1 201 93 17 17 289 -1 unnamed_device 25.2 MiB 2.09 2886 1189 10173 2898 6614 661 65.1 MiB 0.06 0.00 6.73744 5.23384 -148.634 -5.23384 5.23384 0.24 0.000333069 0.000305994 0.0175158 0.0160644 -1 -1 -1 -1 26 2895 35 6.87369e+06 419215 503264. 1741.40 1.31 0.132751 0.11687 24322 120374 -1 2483 26 1948 3189 213646 52192 4.5628 4.5628 -152.603 -4.5628 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0183985 0.0163074 139 47 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_083.v common 4.67 vpr 64.75 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30524 -1 -1 31 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 30 32 377 310 1 181 93 17 17 289 -1 unnamed_device 25.3 MiB 2.60 2449 1224 16893 5635 9042 2216 64.7 MiB 0.12 0.00 5.39266 4.94818 -149.82 -4.94818 4.94818 0.25 0.000344756 0.000315816 0.0388335 0.0359078 -1 -1 -1 -1 28 2735 20 6.87369e+06 433189 531479. 1839.03 0.59 0.0915719 0.0819831 24610 126494 -1 2284 25 1446 2485 237805 83948 3.50651 3.50651 -131.776 -3.50651 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0187101 0.0165963 136 83 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 4.69 vpr 64.62 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30168 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 32 32 365 294 1 187 86 17 17 289 -1 unnamed_device 24.9 MiB 2.10 2716 990 11993 3472 6935 1586 64.6 MiB 0.08 0.00 5.90348 4.77578 -139.992 -4.77578 4.77578 0.24 0.000817076 0.000762471 0.0254697 0.0234016 -1 -1 -1 -1 32 2722 28 6.87369e+06 307425 586450. 2029.24 1.25 0.143023 0.125248 25474 144626 -1 2150 18 1396 2412 167928 39620 4.02096 4.02096 -141.443 -4.02096 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0148475 0.0133072 131 57 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 4.17 vpr 64.65 MiB -1 -1 0.20 18056 1 0.03 -1 -1 30008 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 29 32 378 310 1 179 90 17 17 289 -1 unnamed_device 25.2 MiB 1.85 2351 942 10944 2964 7013 967 64.7 MiB 0.08 0.00 5.07613 4.09163 -121.097 -4.09163 4.09163 0.24 0.000344576 0.000316288 0.0268546 0.0247877 -1 -1 -1 -1 30 2041 24 6.87369e+06 405241 556674. 1926.21 0.83 0.118594 0.104208 25186 138497 -1 1616 20 1131 1865 97938 24518 2.87521 2.87521 -106.946 -2.87521 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0165374 0.0147987 132 85 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.34 vpr 64.44 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29956 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 24.9 MiB 0.87 1905 855 8448 2270 5828 350 64.4 MiB 0.07 0.00 4.48878 3.94428 -118.381 -3.94428 3.94428 0.35 0.000389992 0.000357049 0.0201422 0.0184089 -1 -1 -1 -1 30 1821 20 6.87369e+06 251529 556674. 1926.21 1.08 0.110404 0.0961912 25186 138497 -1 1536 18 722 1020 59686 14633 2.76086 2.76086 -104.224 -2.76086 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0114509 0.0102269 96 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_087.v common 5.58 vpr 64.67 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29576 -1 -1 34 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 32 32 373 302 1 184 98 17 17 289 -1 unnamed_device 25.2 MiB 3.81 2454 1140 11348 2927 7443 978 64.7 MiB 0.06 0.00 5.90822 4.62608 -141.402 -4.62608 4.62608 0.24 0.000359269 0.000329782 0.0201378 0.0184997 -1 -1 -1 -1 32 2643 23 6.87369e+06 475111 586450. 2029.24 0.39 0.0672069 0.0596834 25474 144626 -1 2128 20 1410 2389 151377 37388 3.7954 3.7954 -133.896 -3.7954 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0158466 0.0141663 138 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_088.v common 5.61 vpr 65.12 MiB -1 -1 0.12 18440 1 0.03 -1 -1 30108 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 32 32 397 314 1 197 86 17 17 289 -1 unnamed_device 25.2 MiB 3.49 2187 1055 13694 4095 7104 2495 65.1 MiB 0.10 0.00 5.30372 4.6886 -155.532 -4.6886 4.6886 0.25 0.000362587 0.000331007 0.0357278 0.0329807 -1 -1 -1 -1 32 2864 30 6.87369e+06 307425 586450. 2029.24 0.68 0.12507 0.112141 25474 144626 -1 2190 22 1874 3084 201524 49363 3.9064 3.9064 -149.446 -3.9064 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0279863 0.0250155 142 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_089.v common 4.77 vpr 64.04 MiB -1 -1 0.18 17912 1 0.03 -1 -1 30160 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65576 32 32 269 231 1 170 81 17 17 289 -1 unnamed_device 24.9 MiB 2.01 2026 911 13031 5411 7150 470 64.0 MiB 0.06 0.00 4.68123 4.08363 -117.144 -4.08363 4.08363 0.25 0.000275146 0.000251503 0.021986 0.0201273 -1 -1 -1 -1 32 2111 22 6.87369e+06 237555 586450. 2029.24 1.33 0.11397 0.0992625 25474 144626 -1 1780 20 1174 1591 109623 27308 2.93201 2.93201 -108.593 -2.93201 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0129851 0.0115452 102 29 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_090.v common 3.15 vpr 64.46 MiB -1 -1 0.12 17676 1 0.02 -1 -1 30324 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 245 205 1 153 85 17 17 289 -1 unnamed_device 25.2 MiB 0.92 2028 920 14407 4467 8027 1913 64.5 MiB 0.09 0.00 4.79248 4.04068 -118.574 -4.04068 4.04068 0.26 0.000267498 0.000244558 0.0312119 0.0289087 -1 -1 -1 -1 28 2103 24 6.87369e+06 307425 531479. 1839.03 0.89 0.116531 0.102508 24610 126494 -1 1895 20 1292 2098 141548 34713 3.03526 3.03526 -115.93 -3.03526 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.012172 0.0107774 100 4 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 4.52 vpr 65.07 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30384 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 25.2 MiB 2.04 2676 1170 8083 1952 5562 569 65.1 MiB 0.06 0.00 5.61368 4.75448 -152.304 -4.75448 4.75448 0.24 0.000340485 0.000312452 0.0175897 0.0162244 -1 -1 -1 -1 28 3115 23 6.87369e+06 335372 531479. 1839.03 1.17 0.121612 0.106252 24610 126494 -1 2580 22 2029 2754 244375 55049 4.10006 4.10006 -153.878 -4.10006 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0170113 0.0151164 141 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_092.v common 4.74 vpr 64.53 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29860 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 356 289 1 201 92 17 17 289 -1 unnamed_device 25.2 MiB 2.09 2208 1201 15203 4959 7948 2296 64.5 MiB 0.09 0.00 6.10904 5.2802 -157.375 -5.2802 5.2802 0.26 0.000329459 0.000300811 0.0303446 0.0279453 -1 -1 -1 -1 32 2749 23 6.87369e+06 391268 586450. 2029.24 1.11 0.143611 0.125949 25474 144626 -1 2240 21 1434 2171 140842 33587 4.39535 4.39535 -145.45 -4.39535 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0163683 0.0146225 137 56 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_093.v common 3.58 vpr 65.16 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30184 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66724 32 32 349 260 1 204 101 17 17 289 -1 unnamed_device 25.1 MiB 0.59 2787 1264 13966 4175 8662 1129 65.2 MiB 0.09 0.00 6.34944 5.29707 -150.39 -5.29707 5.29707 0.25 0.000641819 0.000586368 0.0256625 0.023543 -1 -1 -1 -1 26 3191 27 6.87369e+06 517032 503264. 1741.40 1.55 0.15078 0.133588 24322 120374 -1 2699 24 1873 3447 292705 65551 4.85515 4.85515 -153.959 -4.85515 0 0 618332. 2139.56 0.02 0.07 0.06 -1 -1 0.02 0.018655 0.0166398 158 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_094.v common 4.68 vpr 64.82 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29784 -1 -1 34 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 30 32 316 264 1 165 96 17 17 289 -1 unnamed_device 25.2 MiB 1.81 2174 784 9732 2367 5855 1510 64.8 MiB 0.06 0.00 4.46215 3.60295 -103.566 -3.60295 3.60295 0.24 0.000311867 0.000285473 0.019448 0.0179445 -1 -1 -1 -1 28 2361 29 6.87369e+06 475111 531479. 1839.03 1.46 0.120329 0.105955 24610 126494 -1 1792 22 1436 2513 178226 45465 3.17456 3.17456 -108.253 -3.17456 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0176424 0.0156828 119 52 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_095.v common 3.21 vpr 64.41 MiB -1 -1 0.12 17672 1 0.03 -1 -1 30544 -1 -1 23 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65956 27 32 255 219 1 139 82 17 17 289 -1 unnamed_device 25.2 MiB 0.82 1612 787 10050 2715 6635 700 64.4 MiB 0.12 0.00 4.33505 3.47585 -98.4683 -3.47585 3.47585 0.24 0.000838006 0.000776448 0.0486502 0.0453067 -1 -1 -1 -1 32 1635 26 6.87369e+06 321398 586450. 2029.24 1.00 0.129214 0.114695 25474 144626 -1 1333 20 839 1234 78424 18728 2.61836 2.61836 -92.7343 -2.61836 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0122542 0.0108438 97 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 6.04 vpr 64.92 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30156 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 32 32 421 327 1 233 90 17 17 289 -1 unnamed_device 25.2 MiB 2.48 2919 1374 16371 4730 9445 2196 64.9 MiB 0.15 0.00 5.11591 4.4536 -142.768 -4.4536 4.4536 0.25 0.000385467 0.000353596 0.0502962 0.0461038 -1 -1 -1 -1 28 3929 41 6.87369e+06 363320 531479. 1839.03 2.06 0.199677 0.176685 24610 126494 -1 3169 20 2039 3316 292745 68186 4.14656 4.14656 -145.254 -4.14656 0 0 648988. 2245.63 0.02 0.07 0.07 -1 -1 0.02 0.0200713 0.0178199 162 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_097.v common 7.52 vpr 63.80 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29888 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65336 31 32 365 296 1 202 86 17 17 289 -1 unnamed_device 24.5 MiB 4.65 2567 1117 15395 4375 9100 1920 63.8 MiB 0.14 0.00 6.54132 5.50252 -165.378 -5.50252 5.50252 0.35 0.00094304 0.000877411 0.0550549 0.0509965 -1 -1 -1 -1 32 2527 22 6.87369e+06 321398 586450. 2029.24 1.17 0.172222 0.152753 25474 144626 -1 2171 20 1502 2393 131573 34068 4.315 4.315 -149.599 -4.315 0 0 744469. 2576.02 0.03 0.05 0.16 -1 -1 0.03 0.0215759 0.0193293 137 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_098.v common 6.32 vpr 64.46 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29900 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 331 280 1 185 84 17 17 289 -1 unnamed_device 24.9 MiB 3.54 2356 848 11247 3613 5403 2231 64.5 MiB 0.06 0.00 6.05365 4.34735 -140.957 -4.34735 4.34735 0.25 0.000314113 0.000285916 0.0209042 0.0191109 -1 -1 -1 -1 36 2307 30 6.87369e+06 279477 648988. 2245.63 1.38 0.125955 0.109635 26050 158493 -1 1710 21 1244 1786 130702 34809 3.71381 3.71381 -135.737 -3.71381 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0151241 0.0134502 115 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_099.v common 3.64 vpr 64.93 MiB -1 -1 0.13 18300 1 0.03 -1 -1 29928 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 326 263 1 176 97 17 17 289 -1 unnamed_device 25.2 MiB 1.05 2500 991 17191 5469 8763 2959 64.9 MiB 0.09 0.00 6.23855 4.94131 -133.771 -4.94131 4.94131 0.25 0.000319217 0.000287453 0.0282491 0.0257815 -1 -1 -1 -1 32 2541 23 6.87369e+06 461137 586450. 2029.24 1.16 0.135339 0.118369 25474 144626 -1 1967 20 1134 1814 128657 30637 3.5348 3.5348 -122.778 -3.5348 0 0 744469. 2576.02 0.03 0.04 0.11 -1 -1 0.03 0.0146995 0.0130737 129 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_100.v common 4.05 vpr 65.20 MiB -1 -1 0.19 18444 1 0.03 -1 -1 29872 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66764 31 32 373 294 1 197 97 17 17 289 -1 unnamed_device 25.2 MiB 1.63 2375 1162 12529 3039 8249 1241 65.2 MiB 0.07 0.00 5.24822 4.52085 -131.628 -4.52085 4.52085 0.24 0.000358061 0.000328139 0.0216078 0.0197952 -1 -1 -1 -1 32 2575 27 6.87369e+06 475111 586450. 2029.24 0.97 0.118535 0.103282 25474 144626 -1 2191 21 1428 2414 145484 35797 3.60116 3.60116 -127.313 -3.60116 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.016991 0.0151674 149 50 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_101.v common 3.92 vpr 64.44 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29836 -1 -1 31 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 30 32 325 268 1 172 93 17 17 289 -1 unnamed_device 24.8 MiB 2.07 2526 942 15843 4746 8425 2672 64.4 MiB 0.09 0.00 4.42088 3.6935 -105.372 -3.6935 3.6935 0.24 0.000305767 0.000279253 0.0263327 0.0240824 -1 -1 -1 -1 32 2304 24 6.87369e+06 433189 586450. 2029.24 0.37 0.0677758 0.060063 25474 144626 -1 1855 23 1310 2247 143307 35215 3.26111 3.26111 -104.441 -3.26111 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0191546 0.0170659 124 51 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_102.v common 5.92 vpr 65.10 MiB -1 -1 0.11 18440 1 0.03 -1 -1 29800 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66660 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 25.2 MiB 2.99 2913 1092 15883 6638 8299 946 65.1 MiB 0.09 0.00 5.80498 4.83838 -151.498 -4.83838 4.83838 0.24 0.00033385 0.00030469 0.0295813 0.0270307 -1 -1 -1 -1 36 3177 26 6.87369e+06 335372 648988. 2245.63 1.54 0.148107 0.129932 26050 158493 -1 2412 24 2420 3761 269815 66337 4.18536 4.18536 -142.06 -4.18536 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0188696 0.0167907 143 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 4.43 vpr 65.22 MiB -1 -1 0.20 18056 1 0.03 -1 -1 29788 -1 -1 36 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66784 32 32 386 307 1 196 100 17 17 289 -1 unnamed_device 25.2 MiB 2.49 2629 1181 18660 5371 11070 2219 65.2 MiB 0.11 0.00 5.00583 4.14663 -139.408 -4.14663 4.14663 0.26 0.000357344 0.000326842 0.0340144 0.0312299 -1 -1 -1 -1 28 2725 24 6.87369e+06 503058 531479. 1839.03 0.46 0.0869383 0.0774914 24610 126494 -1 2433 22 1625 2600 177794 43230 3.30791 3.30791 -131.404 -3.30791 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0177087 0.0157872 148 62 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 3.83 vpr 64.40 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29796 -1 -1 19 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 29 32 269 229 1 150 80 17 17 289 -1 unnamed_device 24.9 MiB 1.50 1800 855 13152 3903 8012 1237 64.4 MiB 0.06 0.00 4.51078 3.96392 -119.802 -3.96392 3.96392 0.26 0.000278562 0.000250763 0.0228269 0.0208948 -1 -1 -1 -1 28 1573 21 6.87369e+06 265503 531479. 1839.03 0.84 0.102535 0.089372 24610 126494 -1 1449 18 1081 1538 90664 22450 2.84596 2.84596 -105.452 -2.84596 0 0 648988. 2245.63 0.04 0.05 0.12 -1 -1 0.04 0.0194379 0.0172703 101 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 3.61 vpr 64.89 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29720 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66452 32 32 310 266 1 175 84 17 17 289 -1 unnamed_device 24.9 MiB 1.23 1945 989 10881 3547 5830 1504 64.9 MiB 0.06 0.00 4.46846 3.96726 -124.286 -3.96726 3.96726 0.26 0.000539246 0.000491191 0.0218895 0.020114 -1 -1 -1 -1 32 2199 21 6.87369e+06 279477 586450. 2029.24 1.07 0.120443 0.104867 25474 144626 -1 1917 19 1282 1770 134180 30773 3.22347 3.22347 -121.937 -3.22347 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0136307 0.0121427 109 58 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 3.23 vpr 64.45 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30288 -1 -1 39 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65992 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 24.8 MiB 1.16 2369 985 12716 3543 8146 1027 64.4 MiB 0.07 0.00 5.82022 4.63448 -129.081 -4.63448 4.63448 0.25 0.000313758 0.00028752 0.0185202 0.0168858 -1 -1 -1 -1 26 2817 33 6.87369e+06 544980 503264. 1741.40 0.75 0.0722394 0.063921 24322 120374 -1 2199 25 1679 3103 232332 55175 4.5252 4.5252 -139.616 -4.5252 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0171975 0.0152355 135 33 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 3.73 vpr 64.02 MiB -1 -1 0.11 17672 1 0.03 -1 -1 30200 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65560 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.9 MiB 1.93 2013 868 12143 3086 7739 1318 64.0 MiB 0.07 0.00 5.50062 4.39082 -119.863 -4.39082 4.39082 0.26 0.000638417 0.000596436 0.0244094 0.0224743 -1 -1 -1 -1 26 2317 25 6.87369e+06 307425 503264. 1741.40 0.40 0.0704772 0.0627406 24322 120374 -1 1903 21 1304 1681 120177 29907 3.4928 3.4928 -115.033 -3.4928 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.0130638 0.0115815 104 31 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 4.93 vpr 64.00 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30192 -1 -1 16 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65532 32 32 278 238 1 158 80 17 17 289 -1 unnamed_device 24.9 MiB 2.65 2071 908 11604 3546 6151 1907 64.0 MiB 0.06 0.00 4.62988 3.89598 -123.598 -3.89598 3.89598 0.24 0.00027488 0.00025107 0.0199843 0.0182973 -1 -1 -1 -1 32 2061 26 6.87369e+06 223581 586450. 2029.24 0.99 0.101454 0.0882131 25474 144626 -1 1820 19 1201 2020 146655 33744 2.79301 2.79301 -110.871 -2.79301 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0126783 0.0112607 101 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 4.03 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29784 -1 -1 37 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 31 32 373 300 1 185 100 17 17 289 -1 unnamed_device 25.2 MiB 2.20 2655 991 12396 3296 8295 805 65.0 MiB 0.12 0.00 4.74418 3.88072 -123.81 -3.88072 3.88072 0.24 0.00100784 0.000938791 0.0351059 0.0323701 -1 -1 -1 -1 30 2157 23 6.87369e+06 517032 556674. 1926.21 0.44 0.0812104 0.0724896 25186 138497 -1 1772 22 1406 2370 128493 31312 2.87096 2.87096 -113.357 -2.87096 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.0170484 0.0151613 141 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 4.53 vpr 64.52 MiB -1 -1 0.11 17676 1 0.03 -1 -1 30204 -1 -1 19 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 31 32 265 230 1 169 82 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2006 938 8270 2331 5442 497 64.5 MiB 0.04 0.00 4.2629 3.6763 -117.183 -3.6763 3.6763 0.25 0.00027393 0.000251177 0.0138467 0.0127085 -1 -1 -1 -1 26 2515 27 6.87369e+06 265503 503264. 1741.40 1.38 0.113204 0.0989182 24322 120374 -1 2077 22 1426 2063 144088 35253 3.24491 3.24491 -120.554 -3.24491 0 0 618332. 2139.56 0.02 0.05 0.07 -1 -1 0.02 0.017819 0.0156637 100 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 4.78 vpr 65.08 MiB -1 -1 0.16 18440 1 0.03 -1 -1 29780 -1 -1 32 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66640 32 32 349 286 1 177 96 17 17 289 -1 unnamed_device 25.0 MiB 2.22 2443 1058 16740 5363 9029 2348 65.1 MiB 0.09 0.00 4.43988 3.7125 -116.005 -3.7125 3.7125 0.26 0.000330638 0.000302394 0.0297324 0.0273204 -1 -1 -1 -1 32 2537 48 6.87369e+06 447163 586450. 2029.24 1.13 0.162075 0.142002 25474 144626 -1 1979 19 985 1660 107053 25693 3.14681 3.14681 -112.185 -3.14681 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0153245 0.0136416 130 57 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 4.16 vpr 64.70 MiB -1 -1 0.15 18060 1 0.03 -1 -1 29768 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66256 31 32 396 325 1 183 94 17 17 289 -1 unnamed_device 25.2 MiB 2.39 2295 980 16282 5415 8151 2716 64.7 MiB 0.09 0.00 4.1365 3.7606 -126.341 -3.7606 3.7606 0.24 0.000372826 0.000341745 0.0318259 0.0293245 -1 -1 -1 -1 32 2275 22 6.87369e+06 433189 586450. 2029.24 0.38 0.0785981 0.0701866 25474 144626 -1 1857 22 1574 2432 136184 34381 3.09951 3.09951 -122.264 -3.09951 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.017615 0.0156661 136 91 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 4.02 vpr 64.45 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29760 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 303 262 1 154 82 17 17 289 -1 unnamed_device 24.9 MiB 1.70 1892 948 13610 3927 7739 1944 64.5 MiB 0.06 0.00 4.21775 3.46595 -110.85 -3.46595 3.46595 0.25 0.000291981 0.000266784 0.023879 0.0218333 -1 -1 -1 -1 28 2163 25 6.87369e+06 251529 531479. 1839.03 0.99 0.110338 0.0961183 24610 126494 -1 1875 22 1244 1995 152174 36647 2.85796 2.85796 -109.463 -2.85796 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0145337 0.0128796 100 57 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 4.14 vpr 64.85 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30164 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66408 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.9 MiB 1.43 2269 846 15023 5112 7105 2806 64.9 MiB 0.07 0.00 5.53062 4.43872 -133.042 -4.43872 4.43872 0.24 0.000284962 0.000260591 0.0256698 0.023447 -1 -1 -1 -1 34 2491 31 6.87369e+06 265503 618332. 2139.56 1.18 0.131504 0.114323 25762 151098 -1 1812 20 1302 1953 138182 35210 3.43421 3.43421 -119.565 -3.43421 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.0182939 0.0160101 110 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 4.58 vpr 64.35 MiB -1 -1 0.11 18300 1 0.03 -1 -1 30164 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 318 257 1 196 86 17 17 289 -1 unnamed_device 25.2 MiB 1.82 2163 1060 11048 3713 5060 2275 64.3 MiB 0.06 0.00 5.70718 4.76478 -133.796 -4.76478 4.76478 0.24 0.000307552 0.000280889 0.0197149 0.0180596 -1 -1 -1 -1 30 2427 22 6.87369e+06 307425 556674. 1926.21 1.43 0.157271 0.137375 25186 138497 -1 2020 20 1254 1731 101663 25086 3.76346 3.76346 -131.36 -3.76346 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0152417 0.0136094 128 30 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 3.95 vpr 64.96 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29816 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 24.9 MiB 2.06 2255 990 10140 2558 6775 807 65.0 MiB 0.07 0.00 4.47163 4.11363 -115.607 -4.11363 4.11363 0.40 0.000313842 0.00028706 0.0212981 0.0195614 -1 -1 -1 -1 30 2125 26 6.87369e+06 405241 556674. 1926.21 0.38 0.0666518 0.0590345 25186 138497 -1 1706 22 856 1609 88635 21834 3.01151 3.01151 -103.493 -3.01151 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0154263 0.0137196 123 55 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 5.65 vpr 65.12 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 393 312 1 215 88 17 17 289 -1 unnamed_device 25.6 MiB 2.55 2550 1006 14713 4986 7296 2431 65.1 MiB 0.09 0.00 5.75531 5.22906 -161.966 -5.22906 5.22906 0.24 0.000362547 0.00033201 0.0299732 0.0274495 -1 -1 -1 -1 34 2714 38 6.87369e+06 335372 618332. 2139.56 1.66 0.174151 0.152107 25762 151098 -1 2202 24 1965 3055 205816 51673 4.28506 4.28506 -150.228 -4.28506 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0195635 0.0173908 148 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 3.35 vpr 64.40 MiB -1 -1 0.21 17676 1 0.02 -1 -1 30044 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 24.9 MiB 1.02 1779 625 4631 866 3215 550 64.4 MiB 0.02 0.00 4.01225 3.52895 -101.476 -3.52895 3.52895 0.26 0.000250149 0.000229138 0.00776917 0.00714495 -1 -1 -1 -1 30 1639 23 6.87369e+06 251529 556674. 1926.21 0.93 0.0804275 0.069412 25186 138497 -1 1219 21 737 1159 53687 15362 3.04656 3.04656 -101.409 -3.04656 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0147543 0.0131178 93 4 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 5.06 vpr 65.28 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30124 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66848 32 32 412 334 1 194 99 17 17 289 -1 unnamed_device 25.2 MiB 1.54 2354 1015 18111 5950 8835 3326 65.3 MiB 0.09 0.00 5.55115 4.44135 -143.231 -4.44135 4.44135 0.24 0.00037324 0.000341662 0.0311831 0.0284679 -1 -1 -1 -1 36 2533 50 6.87369e+06 489084 648988. 2245.63 2.14 0.218208 0.192077 26050 158493 -1 2040 21 1539 2249 177726 45330 3.99296 3.99296 -143.127 -3.99296 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0185306 0.0165275 145 90 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 5.27 vpr 64.52 MiB -1 -1 0.12 18300 1 0.03 -1 -1 30220 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 376 318 1 168 82 17 17 289 -1 unnamed_device 25.2 MiB 3.41 2123 865 10762 4115 4722 1925 64.5 MiB 0.07 0.00 4.47325 3.59615 -127.488 -3.59615 3.59615 0.25 0.000337104 0.000308034 0.0274738 0.0253226 -1 -1 -1 -1 32 2183 25 6.87369e+06 251529 586450. 2029.24 0.40 0.0761496 0.0673204 25474 144626 -1 1767 22 1484 2215 152133 36159 3.15446 3.15446 -127.944 -3.15446 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0171901 0.0152467 114 96 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 4.62 vpr 64.23 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29776 -1 -1 33 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 360 293 1 182 97 17 17 289 -1 unnamed_device 24.9 MiB 2.31 2242 1134 8533 1953 5707 873 64.2 MiB 0.09 0.00 4.26762 4.14663 -128.445 -4.14663 4.14663 0.30 0.000656918 0.000603764 0.0275667 0.025307 -1 -1 -1 -1 28 2384 22 6.87369e+06 461137 531479. 1839.03 0.80 0.104875 0.092177 24610 126494 -1 2150 21 1079 1675 108833 27521 3.38591 3.38591 -122.541 -3.38591 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0280771 0.0250376 134 60 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_122.v common 5.89 vpr 65.18 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29804 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66748 32 32 396 299 1 240 91 17 17 289 -1 unnamed_device 25.6 MiB 3.34 2861 1325 10699 2829 6710 1160 65.2 MiB 0.08 0.00 6.83115 5.96543 -180.924 -5.96543 5.96543 0.25 0.000377616 0.000346769 0.0221869 0.020377 -1 -1 -1 -1 30 3159 21 6.87369e+06 377294 556674. 1926.21 1.15 0.128384 0.113301 25186 138497 -1 2486 20 1783 2650 160621 38650 4.9295 4.9295 -162.971 -4.9295 0 0 706193. 2443.58 0.03 0.05 0.09 -1 -1 0.03 0.0179893 0.0161715 166 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_123.v common 3.42 vpr 64.37 MiB -1 -1 0.11 17676 1 0.02 -1 -1 29608 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 30 32 224 207 1 137 79 17 17 289 -1 unnamed_device 25.2 MiB 1.16 1796 583 12754 5340 6497 917 64.4 MiB 0.05 0.00 3.69857 3.16961 -92.7187 -3.16961 3.16961 0.24 0.000234624 0.000214291 0.0192412 0.0176121 -1 -1 -1 -1 30 1782 28 6.87369e+06 237555 556674. 1926.21 1.00 0.0855611 0.0741408 25186 138497 -1 1269 16 770 993 68728 19715 2.63001 2.63001 -90.3813 -2.63001 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0115953 0.0103417 78 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_124.v common 2.65 vpr 64.55 MiB -1 -1 0.11 18060 1 0.02 -1 -1 29832 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66104 30 32 286 239 1 151 83 17 17 289 -1 unnamed_device 24.9 MiB 0.84 1770 758 12863 4724 6383 1756 64.6 MiB 0.06 0.00 4.46678 3.90824 -117.819 -3.90824 3.90824 0.24 0.000282976 0.000258279 0.0218206 0.0199412 -1 -1 -1 -1 32 1677 18 6.87369e+06 293451 586450. 2029.24 0.39 0.0704146 0.0621642 25474 144626 -1 1359 23 1013 1508 94997 23267 2.89296 2.89296 -107.7 -2.89296 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0242749 0.0214518 106 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 2.82 vpr 64.59 MiB -1 -1 0.15 18056 1 0.02 -1 -1 30148 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 296 247 1 158 81 17 17 289 -1 unnamed_device 25.4 MiB 1.05 2174 940 13381 4853 6305 2223 64.6 MiB 0.07 0.00 4.05625 3.42975 -116.374 -3.42975 3.42975 0.24 0.000299088 0.000273989 0.024265 0.0222129 -1 -1 -1 -1 30 2272 22 6.87369e+06 237555 556674. 1926.21 0.41 0.0633576 0.0560039 25186 138497 -1 1909 22 1221 2293 143256 34040 2.85696 2.85696 -116.827 -2.85696 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0147316 0.0130541 106 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_126.v common 3.03 vpr 64.39 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29888 -1 -1 29 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65932 25 32 216 194 1 123 86 17 17 289 -1 unnamed_device 24.9 MiB 0.63 1478 521 12938 4434 5564 2940 64.4 MiB 0.05 0.00 4.10455 3.48943 -81.0717 -3.48943 3.48943 0.24 0.000223717 0.000203889 0.0164858 0.015004 -1 -1 -1 -1 30 1629 41 6.87369e+06 405241 556674. 1926.21 1.12 0.0952124 0.0819646 25186 138497 -1 1166 19 766 1360 77787 20476 2.73796 2.73796 -77.5522 -2.73796 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0101821 0.0089722 87 29 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_127.v common 3.81 vpr 65.07 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30176 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66628 32 32 376 307 1 192 86 17 17 289 -1 unnamed_device 25.2 MiB 1.93 2245 1110 15017 5165 7384 2468 65.1 MiB 0.09 0.00 5.02315 4.32635 -130.464 -4.32635 4.32635 0.25 0.000345488 0.000315825 0.0292868 0.026788 -1 -1 -1 -1 32 2752 22 6.87369e+06 307425 586450. 2029.24 0.39 0.0749442 0.0663177 25474 144626 -1 2132 20 1326 2357 146716 35875 3.49806 3.49806 -125.919 -3.49806 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0162152 0.0144597 131 72 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_128.v common 4.21 vpr 64.78 MiB -1 -1 0.13 18056 1 0.03 -1 -1 29828 -1 -1 34 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 31 32 409 331 1 193 97 17 17 289 -1 unnamed_device 25.2 MiB 2.25 2417 956 9199 2038 6732 429 64.8 MiB 0.06 0.00 4.74423 4.19189 -134.468 -4.19189 4.19189 0.25 0.000365815 0.000335309 0.016995 0.0155775 -1 -1 -1 -1 32 2555 23 6.87369e+06 475111 586450. 2029.24 0.40 0.0696073 0.0613481 25474 144626 -1 1959 21 1593 2492 151905 37256 3.18561 3.18561 -123.559 -3.18561 0 0 744469. 2576.02 0.04 0.08 0.13 -1 -1 0.04 0.0315952 0.0282545 145 90 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_001.v common 4.16 vpr 64.96 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29412 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66516 32 32 354 285 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2668 1268 14562 3744 8579 2239 65.0 MiB 0.09 0.00 6.46147 5.42478 -161.939 -5.42478 5.42478 0.27 0.000354138 0.000325872 0.0286551 0.0264431 -1 -1 -1 -1 28 3093 28 6.89349e+06 366440 531479. 1839.03 1.39 0.149217 0.131137 24610 126494 -1 2624 19 1777 2523 168314 41073 4.42749 4.42749 -154.329 -4.42749 0 0 648988. 2245.63 0.03 0.05 0.07 -1 -1 0.03 0.0180098 0.0159135 146 50 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_002.v common 3.13 vpr 64.73 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29756 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66288 30 32 363 293 1 229 89 17 17 289 -1 unnamed_device 25.0 MiB 1.18 2791 1263 14939 4998 7127 2814 64.7 MiB 0.08 0.00 6.19428 4.98048 -150.88 -4.98048 4.98048 0.25 0.000332168 0.000303056 0.0271095 0.0247833 -1 -1 -1 -1 32 3445 31 6.89349e+06 380534 586450. 2029.24 0.56 0.0865076 0.0767831 25474 144626 -1 2439 21 1808 2625 186782 45091 4.32429 4.32429 -146.227 -4.32429 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164687 0.014674 152 63 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_003.v common 3.92 vpr 63.83 MiB -1 -1 0.16 18060 1 0.03 -1 -1 29808 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65360 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 24.6 MiB 1.12 2478 1102 14965 5131 8043 1791 63.8 MiB 0.10 0.00 5.35819 4.28675 -123.145 -4.28675 4.28675 0.26 0.000327491 0.000280328 0.0326438 0.0301867 -1 -1 -1 -1 38 2116 21 6.89349e+06 295971 678818. 2348.85 1.23 0.129476 0.113859 26626 170182 -1 1908 22 1051 1471 95425 22642 3.6203 3.6203 -116.676 -3.6203 0 0 902133. 3121.57 0.05 0.05 0.14 -1 -1 0.05 0.0196229 0.0174739 119 29 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_004.v common 3.21 vpr 64.77 MiB -1 -1 0.11 18056 1 0.03 -1 -1 29748 -1 -1 27 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66320 29 32 308 248 1 195 88 17 17 289 -1 unnamed_device 24.9 MiB 0.81 2689 1112 15493 4685 9183 1625 64.8 MiB 0.08 0.00 6.19768 4.85518 -132.85 -4.85518 4.85518 0.24 0.000305043 0.000279294 0.0254061 0.0232564 -1 -1 -1 -1 32 2525 37 6.89349e+06 380534 586450. 2029.24 1.02 0.125355 0.10906 25474 144626 -1 2095 21 1267 2022 127854 30529 3.81286 3.81286 -122.541 -3.81286 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145113 0.0128994 130 31 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_005.v common 3.38 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29824 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66416 32 32 336 268 1 211 89 17 17 289 -1 unnamed_device 24.8 MiB 1.44 2799 1150 14741 4806 7062 2873 64.9 MiB 0.09 0.00 6.91451 5.19194 -150.686 -5.19194 5.19194 0.24 0.000325479 0.000297988 0.0258125 0.023632 -1 -1 -1 -1 32 3393 21 6.89349e+06 352346 586450. 2029.24 0.46 0.0685243 0.0608933 25474 144626 -1 2453 20 1763 3114 214478 51266 4.54675 4.54675 -150.299 -4.54675 0 0 744469. 2576.02 0.04 0.08 0.11 -1 -1 0.04 0.0249649 0.022335 141 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_006.v common 3.78 vpr 64.55 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29780 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66100 32 32 366 295 1 231 99 17 17 289 -1 unnamed_device 25.2 MiB 1.70 2831 1275 17883 5747 9425 2711 64.6 MiB 0.12 0.00 4.85631 3.97606 -129.432 -3.97606 3.97606 0.26 0.000347219 0.000318231 0.0368098 0.0340006 -1 -1 -1 -1 32 3207 27 6.89349e+06 493284 586450. 2029.24 0.65 0.101339 0.0899346 25474 144626 -1 2564 21 1683 2745 172590 41903 3.49866 3.49866 -125.251 -3.49866 0 0 744469. 2576.02 0.03 0.06 0.09 -1 -1 0.03 0.0203705 0.0179603 156 58 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_007.v common 2.73 vpr 63.64 MiB -1 -1 0.17 17672 1 0.03 -1 -1 30152 -1 -1 22 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65168 27 32 259 221 1 159 81 17 17 289 -1 unnamed_device 24.1 MiB 0.88 1787 834 12681 4344 6184 2153 63.6 MiB 0.06 0.00 4.91933 4.22379 -114.63 -4.22379 4.22379 0.25 0.000258176 0.000236283 0.020121 0.018441 -1 -1 -1 -1 32 1839 34 6.89349e+06 310065 586450. 2029.24 0.42 0.0705179 0.0621317 25474 144626 -1 1480 21 1046 1586 115082 27270 3.11381 3.11381 -103.863 -3.11381 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.013738 0.0122335 104 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 2.98 vpr 64.40 MiB -1 -1 0.16 17672 1 0.03 -1 -1 29836 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65944 31 32 271 219 1 164 96 17 17 289 -1 unnamed_device 24.8 MiB 0.58 2064 1021 15426 4233 9006 2187 64.4 MiB 0.08 0.00 4.0124 3.39815 -103.342 -3.39815 3.39815 0.25 0.000304464 0.000279784 0.0290524 0.0266819 -1 -1 -1 -1 32 2265 19 6.89349e+06 465097 586450. 2029.24 0.99 0.12256 0.107042 25474 144626 -1 1863 19 982 1779 108256 26071 2.49221 2.49221 -95.7819 -2.49221 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0130806 0.0116211 119 4 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_009.v common 3.56 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29764 -1 -1 23 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 31 32 317 271 1 207 86 17 17 289 -1 unnamed_device 24.9 MiB 1.03 2257 970 6512 1373 4783 356 64.8 MiB 0.04 0.00 4.58785 3.71075 -120.491 -3.71075 3.71075 0.26 0.000307831 0.000282316 0.0119944 0.0109864 -1 -1 -1 -1 30 2557 25 6.89349e+06 324158 556674. 1926.21 1.21 0.11422 0.0990295 25186 138497 -1 1893 22 1510 2075 128297 33350 3.17321 3.17321 -122.163 -3.17321 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0153599 0.013634 125 64 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_010.v common 3.21 vpr 64.44 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29780 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65984 32 32 298 248 1 185 83 17 17 289 -1 unnamed_device 24.9 MiB 1.12 1986 1014 8003 1763 5681 559 64.4 MiB 0.06 0.00 4.79638 4.06248 -133.531 -4.06248 4.06248 0.25 0.000293762 0.000269576 0.0208869 0.019182 -1 -1 -1 -1 30 2247 30 6.89349e+06 267783 556674. 1926.21 0.79 0.0985272 0.0859376 25186 138497 -1 1845 21 1118 1550 104372 24397 2.79711 2.79711 -117.654 -2.79711 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0142957 0.0127128 115 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_011.v common 3.56 vpr 64.48 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29804 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66024 30 32 303 262 1 191 84 17 17 289 -1 unnamed_device 25.2 MiB 1.11 2045 1034 13992 5226 7098 1668 64.5 MiB 0.07 0.00 5.30417 4.58817 -134.271 -4.58817 4.58817 0.25 0.000285823 0.000261664 0.0234962 0.0215034 -1 -1 -1 -1 32 2570 23 6.89349e+06 310065 586450. 2029.24 1.08 0.117321 0.102048 25474 144626 -1 1928 20 1166 1543 112527 25961 3.52775 3.52775 -121.933 -3.52775 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0137984 0.0122887 121 63 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_012.v common 2.79 vpr 64.41 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29740 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65956 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 24.9 MiB 1.00 2463 976 13432 3930 7414 2088 64.4 MiB 0.07 0.00 4.7073 3.6928 -114.983 -3.6928 3.6928 0.25 0.000275071 0.000252008 0.0223127 0.0204555 -1 -1 -1 -1 32 2213 22 6.89349e+06 253689 586450. 2029.24 0.39 0.0611593 0.0541867 25474 144626 -1 1780 22 1007 1381 100176 22972 2.74911 2.74911 -106.8 -2.74911 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0141439 0.0125142 103 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_013.v common 3.51 vpr 64.23 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29796 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65776 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 25.2 MiB 1.38 2413 1094 15335 5171 7707 2457 64.2 MiB 0.10 0.00 4.45968 4.21034 -134.417 -4.21034 4.21034 0.25 0.000329997 0.000301932 0.0308546 0.0282959 -1 -1 -1 -1 32 2902 28 6.89349e+06 352346 586450. 2029.24 0.75 0.12445 0.110508 25474 144626 -1 2293 23 1740 2630 196717 47360 3.47746 3.47746 -126.462 -3.47746 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169096 0.0150531 140 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_014.v common 4.58 vpr 65.01 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29772 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66568 32 32 363 295 1 232 90 17 17 289 -1 unnamed_device 24.9 MiB 1.45 2789 1385 9939 2779 6391 769 65.0 MiB 0.06 0.00 6.97451 5.52182 -162.398 -5.52182 5.52182 0.25 0.000335248 0.000306745 0.0184652 0.016897 -1 -1 -1 -1 28 3357 31 6.89349e+06 366440 531479. 1839.03 1.79 0.124115 0.10906 24610 126494 -1 2785 22 1872 2537 229756 59541 4.40835 4.40835 -155.309 -4.40835 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0181619 0.0162326 151 61 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_015.v common 3.42 vpr 64.33 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30272 -1 -1 21 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 29 32 248 215 1 160 82 17 17 289 -1 unnamed_device 24.9 MiB 0.98 1849 777 10762 2615 7615 532 64.3 MiB 0.05 0.00 4.18032 3.23418 -96.7477 -3.23418 3.23418 0.24 0.000255908 0.00023477 0.0168335 0.0154381 -1 -1 -1 -1 30 1844 21 6.89349e+06 295971 556674. 1926.21 1.12 0.122352 0.106443 25186 138497 -1 1498 22 967 1375 83682 21630 2.89731 2.89731 -98.7482 -2.89731 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.014901 0.0131379 98 27 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_016.v common 5.13 vpr 65.03 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29760 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66592 32 32 370 297 1 234 91 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2606 1335 15187 5552 7119 2516 65.0 MiB 0.11 0.00 5.16764 4.22024 -136.349 -4.22024 4.22024 0.26 0.000412992 0.000382645 0.0361098 0.0332974 -1 -1 -1 -1 30 3279 35 6.89349e+06 380534 556674. 1926.21 1.79 0.162898 0.143544 25186 138497 -1 2450 20 1777 2835 162669 40771 3.68045 3.68045 -133.182 -3.68045 0 0 706193. 2443.58 0.04 0.07 0.11 -1 -1 0.04 0.02568 0.022915 156 58 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_017.v common 3.90 vpr 64.87 MiB -1 -1 0.11 18056 1 0.03 -1 -1 30200 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66424 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 25.2 MiB 1.28 2621 1087 13911 3796 7786 2329 64.9 MiB 0.08 0.00 4.95288 4.09494 -130.17 -4.09494 4.09494 0.24 0.000327812 0.000300274 0.0254079 0.0232692 -1 -1 -1 -1 36 2373 21 6.89349e+06 324158 648988. 2245.63 1.25 0.13221 0.115644 26050 158493 -1 1986 20 1185 1718 122618 29684 3.19801 3.19801 -114.684 -3.19801 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0152461 0.013601 137 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 3.28 vpr 64.84 MiB -1 -1 0.12 17916 1 0.03 -1 -1 30116 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 323 276 1 215 89 17 17 289 -1 unnamed_device 24.8 MiB 1.33 2509 1207 11573 2908 7136 1529 64.8 MiB 0.07 0.00 4.33725 3.64971 -129.543 -3.64971 3.64971 0.25 0.000446323 0.000418476 0.0206661 0.0189407 -1 -1 -1 -1 30 2877 36 6.89349e+06 352346 556674. 1926.21 0.61 0.0867738 0.0767415 25186 138497 -1 2229 18 1150 1585 105826 24515 3.03215 3.03215 -122.568 -3.03215 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0147283 0.0131892 130 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_019.v common 2.68 vpr 64.25 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29816 -1 -1 16 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65788 30 32 222 206 1 141 78 17 17 289 -1 unnamed_device 25.2 MiB 0.61 1681 755 9872 2574 6614 684 64.2 MiB 0.04 0.00 3.29613 2.66963 -90.6547 -2.66963 2.66963 0.24 0.000244818 0.000217441 0.016279 0.0149582 -1 -1 -1 -1 28 1581 17 6.89349e+06 225501 531479. 1839.03 0.81 0.0691751 0.060157 24610 126494 -1 1395 17 749 863 62232 15664 2.11002 2.11002 -91.215 -2.11002 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.00977148 0.00866811 79 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_020.v common 3.99 vpr 64.46 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30172 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66004 31 32 291 243 1 179 84 17 17 289 -1 unnamed_device 24.7 MiB 1.29 2232 990 14358 5433 7130 1795 64.5 MiB 0.07 0.00 5.72212 4.79672 -142.478 -4.79672 4.79672 0.24 0.00047536 0.000450156 0.0250063 0.0229537 -1 -1 -1 -1 28 2553 26 6.89349e+06 295971 531479. 1839.03 1.37 0.109881 0.0966787 24610 126494 -1 2028 19 1246 1876 131016 32194 3.77545 3.77545 -139.775 -3.77545 0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.0130579 0.0116135 115 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_021.v common 3.83 vpr 64.80 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29940 -1 -1 35 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66360 32 32 342 271 1 207 99 17 17 289 -1 unnamed_device 24.8 MiB 1.07 2415 1186 18795 6653 9829 2313 64.8 MiB 0.09 0.00 6.0155 4.63443 -148.243 -4.63443 4.63443 0.25 0.000331482 0.000297849 0.0288279 0.0263868 -1 -1 -1 -1 36 2535 22 6.89349e+06 493284 648988. 2245.63 1.37 0.133607 0.116992 26050 158493 -1 2136 21 1575 2368 182986 42853 4.01424 4.01424 -140.469 -4.01424 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0195265 0.0174675 150 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_022.v common 3.80 vpr 65.02 MiB -1 -1 0.13 18064 1 0.04 -1 -1 29728 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 372 300 1 229 89 17 17 289 -1 unnamed_device 25.2 MiB 1.07 2872 1408 14741 4188 8680 1873 65.0 MiB 0.09 0.00 5.95345 4.79088 -146.55 -4.79088 4.79088 0.24 0.000345743 0.000316106 0.0275037 0.0252196 -1 -1 -1 -1 30 3072 30 6.89349e+06 352346 556674. 1926.21 1.31 0.14375 0.125667 25186 138497 -1 2494 21 1700 2463 172223 38111 3.67269 3.67269 -133.602 -3.67269 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0167697 0.0149365 152 62 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_023.v common 2.82 vpr 64.13 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30148 -1 -1 19 26 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65668 26 32 190 182 1 126 77 17 17 289 -1 unnamed_device 25.2 MiB 0.59 1378 528 11324 4722 5741 861 64.1 MiB 0.04 0.00 2.92131 2.67071 -73.9405 -2.67071 2.67071 0.25 0.000200742 0.000182777 0.0149184 0.0136176 -1 -1 -1 -1 30 1223 26 6.89349e+06 267783 556674. 1926.21 0.88 0.0684971 0.0593734 25186 138497 -1 921 17 565 672 37400 10275 1.85675 1.85675 -65.726 -1.85675 0 0 706193. 2443.58 0.03 0.02 0.13 -1 -1 0.03 0.00849785 0.00758487 72 30 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_024.v common 2.50 vpr 64.45 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29756 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 285 227 1 169 88 17 17 289 -1 unnamed_device 24.9 MiB 0.80 2097 1093 14908 4191 8870 1847 64.4 MiB 0.07 0.00 5.19194 4.58773 -130.119 -4.58773 4.58773 0.24 0.000291779 0.000266841 0.0240118 0.0219813 -1 -1 -1 -1 32 2488 23 6.89349e+06 338252 586450. 2029.24 0.38 0.0638837 0.0566624 25474 144626 -1 2145 20 1144 2016 159814 37055 3.49805 3.49805 -121.157 -3.49805 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0137382 0.0122388 120 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_025.v common 2.49 vpr 64.04 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30104 -1 -1 12 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65576 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 25.2 MiB 0.50 1343 738 9516 2733 5641 1142 64.0 MiB 0.03 0.00 2.53969 2.22522 -77.1622 -2.22522 2.22522 0.24 0.000194566 0.000176679 0.0126767 0.0115566 -1 -1 -1 -1 26 1456 18 6.89349e+06 169126 503264. 1741.40 0.55 0.0594687 0.0515478 24322 120374 -1 1353 21 670 881 68720 16870 1.77811 1.77811 -79.1079 -1.77811 0 0 618332. 2139.56 0.02 0.03 0.13 -1 -1 0.02 0.00971171 0.00855551 64 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_026.v common 3.48 vpr 64.49 MiB -1 -1 0.12 18052 1 0.03 -1 -1 29588 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66036 32 32 300 245 1 187 86 17 17 289 -1 unnamed_device 24.9 MiB 1.13 2120 1085 9536 2559 6078 899 64.5 MiB 0.05 0.00 5.62618 4.92048 -138.071 -4.92048 4.92048 0.25 0.00030219 0.000276959 0.0167141 0.015329 -1 -1 -1 -1 32 2428 20 6.89349e+06 310065 586450. 2029.24 1.01 0.131882 0.115016 25474 144626 -1 1966 16 1004 1478 88603 22258 3.7112 3.7112 -125.676 -3.7112 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.012272 0.0110367 121 24 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 3.11 vpr 64.46 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29936 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 24.6 MiB 0.69 2474 1043 16727 4808 9374 2545 64.5 MiB 0.08 0.00 4.41543 3.451 -108.699 -3.451 3.451 0.25 0.000307109 0.000276632 0.0248743 0.022735 -1 -1 -1 -1 32 2399 21 6.89349e+06 436909 586450. 2029.24 1.10 0.124692 0.108971 25474 144626 -1 2003 21 1136 2050 128645 30983 2.66571 2.66571 -101.838 -2.66571 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145269 0.0129327 130 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 3.35 vpr 63.82 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29780 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65348 32 32 338 277 1 215 89 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2459 1294 14741 4922 7916 1903 63.8 MiB 0.09 0.00 5.82658 4.85308 -136.949 -4.85308 4.85308 0.24 0.000317563 0.000290569 0.025462 0.0232995 -1 -1 -1 -1 32 2850 43 6.89349e+06 352346 586450. 2029.24 0.61 0.0964175 0.0847986 25474 144626 -1 2288 20 1262 1877 121444 29241 3.65326 3.65326 -130.716 -3.65326 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0153091 0.0136806 139 50 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_029.v common 3.54 vpr 64.44 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29808 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 32 32 284 241 1 177 84 17 17 289 -1 unnamed_device 24.9 MiB 1.26 1936 1067 12894 4344 6614 1936 64.4 MiB 0.07 0.00 4.31105 3.7646 -126.911 -3.7646 3.7646 0.24 0.000281184 0.000257399 0.0213517 0.0195486 -1 -1 -1 -1 32 2226 20 6.89349e+06 281877 586450. 2029.24 0.96 0.0987942 0.0861715 25474 144626 -1 1958 21 1103 1593 110334 26241 2.69186 2.69186 -115.097 -2.69186 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0143842 0.0127846 110 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_030.v common 2.58 vpr 64.37 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30264 -1 -1 21 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65916 30 32 262 227 1 161 83 17 17 289 -1 unnamed_device 24.9 MiB 0.86 2301 943 13043 4183 6793 2067 64.4 MiB 0.06 0.00 5.05544 4.00962 -116.333 -4.00962 4.00962 0.25 0.000274696 0.000251996 0.0211122 0.0193502 -1 -1 -1 -1 32 2109 18 6.89349e+06 295971 586450. 2029.24 0.37 0.0588309 0.0520159 25474 144626 -1 1793 21 971 1595 128041 29328 3.30785 3.30785 -109.419 -3.30785 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0162331 0.0145062 103 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_031.v common 3.34 vpr 64.19 MiB -1 -1 0.11 17916 1 0.02 -1 -1 29604 -1 -1 20 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65732 28 32 260 223 1 163 80 17 17 289 -1 unnamed_device 24.7 MiB 1.04 1953 1013 13324 4541 7089 1694 64.2 MiB 0.08 0.00 5.13107 4.43603 -124.612 -4.43603 4.43603 0.26 0.000270744 0.000248135 0.0269024 0.0247709 -1 -1 -1 -1 30 2187 21 6.89349e+06 281877 556674. 1926.21 0.98 0.110529 0.0969537 25186 138497 -1 1819 17 903 1571 100336 23266 3.3055 3.3055 -115.801 -3.3055 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0112853 0.0100418 104 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 3.17 vpr 64.25 MiB -1 -1 0.10 17676 1 0.02 -1 -1 29720 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 24.8 MiB 0.85 2155 955 10228 2872 6411 945 64.2 MiB 0.05 0.00 4.55303 3.92502 -120.982 -3.92502 3.92502 0.24 0.000264604 0.000242521 0.0173918 0.015918 -1 -1 -1 -1 32 2080 26 6.89349e+06 253689 586450. 2029.24 1.01 0.103009 0.0892271 25474 144626 -1 1800 19 1015 1740 120492 28474 2.78381 2.78381 -113.151 -2.78381 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0120413 0.0106721 101 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 3.00 vpr 64.44 MiB -1 -1 0.20 18056 1 0.02 -1 -1 29764 -1 -1 21 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 31 32 271 231 1 172 84 17 17 289 -1 unnamed_device 24.6 MiB 1.05 2571 955 9966 2827 6447 692 64.4 MiB 0.05 0.00 4.5958 3.73465 -114.886 -3.73465 3.73465 0.25 0.000280398 0.000257313 0.0163776 0.0149922 -1 -1 -1 -1 26 2565 37 6.89349e+06 295971 503264. 1741.40 0.50 0.0627421 0.0550562 24322 120374 -1 2108 18 1121 1641 117820 29274 3.19091 3.19091 -118.654 -3.19091 0 0 618332. 2139.56 0.02 0.03 0.11 -1 -1 0.02 0.0119732 0.0106622 105 30 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 3.97 vpr 63.87 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29848 -1 -1 23 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 29 32 291 250 1 185 84 17 17 289 -1 unnamed_device 24.7 MiB 1.46 2485 957 12894 3059 8335 1500 63.9 MiB 0.06 0.00 4.26057 3.6185 -104.685 -3.6185 3.6185 0.25 0.000308233 0.000278605 0.0227674 0.0209684 -1 -1 -1 -1 34 2000 20 6.89349e+06 324158 618332. 2139.56 1.16 0.133759 0.116522 25762 151098 -1 1717 18 913 1287 86496 21872 2.65071 2.65071 -97.5528 -2.65071 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0126343 0.0112802 117 54 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_035.v common 4.08 vpr 64.57 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29612 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 367 282 1 224 91 17 17 289 -1 unnamed_device 24.9 MiB 1.04 2453 1261 14371 4620 7204 2547 64.6 MiB 0.09 0.00 5.05875 4.57545 -133.583 -4.57545 4.57545 0.25 0.000352767 0.000323289 0.0269709 0.0247561 -1 -1 -1 -1 36 2825 23 6.89349e+06 380534 648988. 2245.63 1.58 0.178928 0.157203 26050 158493 -1 2396 20 1295 2069 145934 34231 3.97056 3.97056 -127.691 -3.97056 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0167835 0.0150141 154 29 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_036.v common 4.42 vpr 64.68 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30128 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66228 32 32 391 311 1 250 92 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2644 1340 16238 5326 8855 2057 64.7 MiB 0.10 0.00 4.96607 4.60807 -154.992 -4.60807 4.60807 0.25 0.000361877 0.000331603 0.0308029 0.028253 -1 -1 -1 -1 32 3395 36 6.89349e+06 394628 586450. 2029.24 1.34 0.162449 0.143043 25474 144626 -1 2714 23 2107 3054 238419 53335 3.72925 3.72925 -145.858 -3.72925 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.019568 0.017421 163 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_037.v common 2.66 vpr 64.02 MiB -1 -1 0.12 18052 1 0.02 -1 -1 29812 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65552 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 24.9 MiB 0.84 2434 989 8306 2314 5441 551 64.0 MiB 0.05 0.00 4.86668 4.04584 -122.858 -4.04584 4.04584 0.25 0.000282431 0.000258833 0.0169493 0.0155912 -1 -1 -1 -1 32 2127 23 6.89349e+06 253689 586450. 2029.24 0.40 0.0554529 0.0490594 25474 144626 -1 1912 23 1092 1705 138575 32111 3.38461 3.38461 -118.083 -3.38461 0 0 744469. 2576.02 0.04 0.06 0.12 -1 -1 0.04 0.0225944 0.0201313 107 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 4.05 vpr 64.24 MiB -1 -1 0.14 18060 1 0.03 -1 -1 30160 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65780 31 32 370 297 1 235 90 17 17 289 -1 unnamed_device 24.9 MiB 1.59 2670 1289 13155 3308 7952 1895 64.2 MiB 0.08 0.00 5.12349 4.31155 -137.727 -4.31155 4.31155 0.24 0.00034025 0.000311385 0.0239065 0.0219058 -1 -1 -1 -1 30 2812 22 6.89349e+06 380534 556674. 1926.21 1.10 0.121591 0.106877 25186 138497 -1 2328 20 1532 2286 129522 32467 3.41065 3.41065 -129.329 -3.41065 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0161074 0.0143427 154 61 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 3.89 vpr 65.05 MiB -1 -1 0.14 17676 1 0.03 -1 -1 30160 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 31 32 377 302 1 241 91 17 17 289 -1 unnamed_device 25.2 MiB 1.61 2869 1286 10291 2730 6649 912 65.0 MiB 0.07 0.00 6.59857 5.48687 -163.025 -5.48687 5.48687 0.25 0.000347488 0.000319042 0.0195108 0.0178794 -1 -1 -1 -1 32 3330 22 6.89349e+06 394628 586450. 2029.24 0.79 0.0829449 0.0732081 25474 144626 -1 2600 21 1764 2590 214962 46783 4.41735 4.41735 -155.28 -4.41735 0 0 744469. 2576.02 0.04 0.08 0.13 -1 -1 0.04 0.0280281 0.0249912 158 64 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_040.v common 3.79 vpr 64.29 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30140 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65836 31 32 383 305 1 240 92 17 17 289 -1 unnamed_device 24.9 MiB 1.77 2971 1288 18308 5162 11169 1977 64.3 MiB 0.11 0.00 7.06021 5.82563 -172.459 -5.82563 5.82563 0.24 0.000352762 0.000318106 0.0338824 0.0310012 -1 -1 -1 -1 32 3079 30 6.89349e+06 408721 586450. 2029.24 0.50 0.0862449 0.076668 25474 144626 -1 2614 23 1873 2828 219295 50747 5.21269 5.21269 -171.607 -5.21269 0 0 744469. 2576.02 0.03 0.06 0.16 -1 -1 0.03 0.0202925 0.0181011 160 64 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_041.v common 3.23 vpr 64.96 MiB -1 -1 0.13 18056 1 0.04 -1 -1 29764 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 31 32 352 285 1 223 90 17 17 289 -1 unnamed_device 25.2 MiB 1.25 2244 1364 13356 3907 7417 2032 65.0 MiB 0.08 0.00 4.56598 4.06478 -129.084 -4.06478 4.06478 0.24 0.000332109 0.000304119 0.0239262 0.0219187 -1 -1 -1 -1 30 3087 26 6.89349e+06 380534 556674. 1926.21 0.48 0.0737516 0.0650058 25186 138497 -1 2499 20 1518 2227 158913 35691 3.44916 3.44916 -121.559 -3.44916 0 0 706193. 2443.58 0.03 0.04 0.13 -1 -1 0.03 0.0158182 0.0140933 147 55 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_042.v common 3.82 vpr 64.50 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30156 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66052 32 32 291 242 1 188 86 17 17 289 -1 unnamed_device 25.2 MiB 1.22 2505 1019 15017 5391 6893 2733 64.5 MiB 0.07 0.00 5.50703 4.42605 -118.578 -4.42605 4.42605 0.24 0.000290947 0.000266089 0.024837 0.022735 -1 -1 -1 -1 30 2553 47 6.89349e+06 310065 556674. 1926.21 1.26 0.131474 0.114382 25186 138497 -1 1963 19 1069 1508 97270 23623 3.8018 3.8018 -115.623 -3.8018 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0134814 0.012024 114 27 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_043.v common 4.96 vpr 65.33 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29828 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66896 32 32 457 356 1 296 101 17 17 289 -1 unnamed_device 25.6 MiB 2.07 3202 1707 11616 2831 7740 1045 65.3 MiB 0.10 0.00 6.63 5.71166 -180.923 -5.71166 5.71166 0.24 0.000421051 0.000387062 0.029106 0.0268523 -1 -1 -1 -1 32 4457 33 6.89349e+06 521472 586450. 2029.24 1.36 0.174611 0.153493 25474 144626 -1 3340 23 2283 3484 283406 73527 4.54378 4.54378 -163.759 -4.54378 0 0 744469. 2576.02 0.03 0.08 0.08 -1 -1 0.03 0.0244152 0.0218808 199 87 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_044.v common 2.47 vpr 64.36 MiB -1 -1 0.14 17676 1 0.03 -1 -1 30212 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65904 31 32 261 225 1 171 83 17 17 289 -1 unnamed_device 24.9 MiB 0.78 2305 761 9803 2301 6865 637 64.4 MiB 0.05 0.00 4.9117 3.8019 -108.91 -3.8019 3.8019 0.25 0.000282573 0.000259542 0.0176186 0.0162018 -1 -1 -1 -1 32 2072 23 6.89349e+06 281877 586450. 2029.24 0.35 0.0559811 0.0492287 25474 144626 -1 1627 20 1015 1385 86539 22892 3.18906 3.18906 -107.56 -3.18906 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0125017 0.0110861 101 28 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_045.v common 4.29 vpr 64.86 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29856 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66412 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 24.9 MiB 1.31 2787 1139 8473 1978 5944 551 64.9 MiB 0.06 0.00 5.76922 4.83408 -143.835 -4.83408 4.83408 0.25 0.000323 0.000295931 0.0164862 0.0151597 -1 -1 -1 -1 28 3258 24 6.89349e+06 352346 531479. 1839.03 1.61 0.11073 0.0969671 24610 126494 -1 2479 21 1692 2507 182798 44288 4.1091 4.1091 -145.402 -4.1091 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0160239 0.0143004 139 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_046.v common 3.42 vpr 64.40 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29704 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65948 32 32 349 284 1 222 91 17 17 289 -1 unnamed_device 24.8 MiB 1.38 2669 1235 9475 2196 6793 486 64.4 MiB 0.07 0.00 5.26295 4.39795 -133.209 -4.39795 4.39795 0.26 0.000355222 0.000316909 0.0220287 0.0202872 -1 -1 -1 -1 30 3163 30 6.89349e+06 380534 556674. 1926.21 0.62 0.0861179 0.0762636 25186 138497 -1 2521 38 1868 3138 263695 85979 3.45195 3.45195 -128.059 -3.45195 0 0 706193. 2443.58 0.03 0.08 0.07 -1 -1 0.03 0.0244879 0.0215511 146 53 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_047.v common 3.30 vpr 64.44 MiB -1 -1 0.22 17676 1 0.02 -1 -1 29788 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65988 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 24.9 MiB 0.71 1933 1092 14575 4579 7786 2210 64.4 MiB 0.08 0.00 4.84964 4.24939 -129.722 -4.24939 4.24939 0.24 0.00086745 0.000802011 0.0241679 0.0221141 -1 -1 -1 -1 32 2496 21 6.89349e+06 380534 586450. 2029.24 1.14 0.111521 0.0978012 25474 144626 -1 2102 21 1130 2260 167469 38040 3.607 3.607 -125.377 -3.607 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0144232 0.0128114 123 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 4.01 vpr 64.57 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29752 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 353 287 1 220 90 17 17 289 -1 unnamed_device 24.9 MiB 1.31 2606 1137 13959 4872 6200 2887 64.6 MiB 0.08 0.00 4.99599 4.43611 -128.994 -4.43611 4.43611 0.24 0.000337654 0.000308984 0.0250131 0.0228926 -1 -1 -1 -1 36 2583 24 6.89349e+06 366440 648988. 2245.63 1.32 0.134965 0.117841 26050 158493 -1 2080 19 1418 1940 131258 33952 3.32661 3.32661 -114.202 -3.32661 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0151167 0.0135052 143 55 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_049.v common 4.06 vpr 64.57 MiB -1 -1 0.11 17908 1 0.03 -1 -1 29788 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 361 291 1 231 90 17 17 289 -1 unnamed_device 24.9 MiB 1.46 2568 1471 16773 5286 9456 2031 64.6 MiB 0.11 0.00 5.07339 4.21419 -136.215 -4.21419 4.21419 0.25 0.000340656 0.000312322 0.0401428 0.0371406 -1 -1 -1 -1 26 3247 37 6.89349e+06 366440 503264. 1741.40 1.17 0.154223 0.136036 24322 120374 -1 2794 20 1750 2576 179633 42531 3.67355 3.67355 -137.947 -3.67355 0 0 618332. 2139.56 0.02 0.05 0.06 -1 -1 0.02 0.0159892 0.0142241 149 55 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_050.v common 5.10 vpr 65.05 MiB -1 -1 0.12 18444 1 0.03 -1 -1 29844 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 382 305 1 243 92 17 17 289 -1 unnamed_device 25.2 MiB 1.80 2705 1368 16031 4740 8553 2738 65.1 MiB 0.09 0.00 5.02847 4.40197 -141.012 -4.40197 4.40197 0.36 0.00035782 0.000328643 0.0292191 0.0267664 -1 -1 -1 -1 36 3034 44 6.89349e+06 394628 648988. 2245.63 1.76 0.173531 0.152219 26050 158493 -1 2623 21 1990 2843 215002 49630 3.41336 3.41336 -127.927 -3.41336 0 0 828058. 2865.25 0.03 0.06 0.08 -1 -1 0.03 0.0213513 0.0191552 160 62 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_051.v common 3.39 vpr 63.93 MiB -1 -1 0.11 18300 1 0.03 -1 -1 29748 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65464 32 32 306 248 1 188 87 17 17 289 -1 unnamed_device 24.7 MiB 0.98 2196 1143 14295 3709 9126 1460 63.9 MiB 0.08 0.00 5.64975 4.52825 -134.553 -4.52825 4.52825 0.25 0.000307577 0.000281552 0.0241934 0.0221636 -1 -1 -1 -1 26 2654 43 6.89349e+06 324158 503264. 1741.40 1.10 0.126441 0.110874 24322 120374 -1 2299 20 1441 2205 153221 36540 4.2106 4.2106 -141.768 -4.2106 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.014174 0.012622 123 24 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_052.v common 2.59 vpr 64.79 MiB -1 -1 0.12 17912 1 0.03 -1 -1 29952 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66348 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 24.9 MiB 0.92 2220 1132 9303 2287 5956 1060 64.8 MiB 0.06 0.00 5.85178 4.86728 -141.077 -4.86728 4.86728 0.24 0.00031178 0.000285633 0.0165258 0.0151309 -1 -1 -1 -1 30 2732 27 6.89349e+06 324158 556674. 1926.21 0.37 0.0623473 0.0549675 25186 138497 -1 2302 22 1328 1944 126115 30047 3.82166 3.82166 -132.023 -3.82166 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.015552 0.0138663 129 29 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_053.v common 3.46 vpr 64.98 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29768 -1 -1 27 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66536 31 32 373 299 1 227 90 17 17 289 -1 unnamed_device 25.2 MiB 1.38 2459 1142 10944 2981 6313 1650 65.0 MiB 0.07 0.00 5.42896 4.77798 -141.248 -4.77798 4.77798 0.35 0.000351179 0.000321756 0.0206113 0.0188859 -1 -1 -1 -1 32 3654 30 6.89349e+06 380534 586450. 2029.24 0.54 0.0724628 0.0639195 25474 144626 -1 2569 21 1631 2555 180112 43962 4.02469 4.02469 -136.645 -4.02469 0 0 744469. 2576.02 0.03 0.05 0.13 -1 -1 0.03 0.0166904 0.0148941 154 62 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_054.v common 4.29 vpr 65.09 MiB -1 -1 0.17 18056 1 0.03 -1 -1 29528 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66652 32 32 387 315 1 247 91 17 17 289 -1 unnamed_device 25.2 MiB 1.78 2851 1347 7231 1595 5190 446 65.1 MiB 0.05 0.00 5.65933 4.38345 -134.94 -4.38345 4.38345 0.24 0.000357978 0.000328523 0.0146477 0.0134302 -1 -1 -1 -1 32 3284 25 6.89349e+06 380534 586450. 2029.24 1.09 0.112964 0.0982118 25474 144626 -1 2634 20 2010 2965 184477 44253 3.54626 3.54626 -130.981 -3.54626 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0169355 0.0150937 160 77 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_055.v common 4.33 vpr 64.33 MiB -1 -1 0.15 17676 1 0.02 -1 -1 29816 -1 -1 17 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 251 219 1 156 81 17 17 289 -1 unnamed_device 24.9 MiB 0.98 1772 720 12681 4996 6149 1536 64.3 MiB 0.05 0.00 4.27105 3.55383 -105.248 -3.55383 3.55383 0.35 0.000260874 0.00023824 0.0202907 0.0185529 -1 -1 -1 -1 32 2262 44 6.89349e+06 239595 586450. 2029.24 1.89 0.130372 0.113046 25474 144626 -1 1579 19 952 1380 99711 28807 2.81411 2.81411 -102.252 -2.81411 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0119485 0.0106421 93 23 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_056.v common 3.03 vpr 64.53 MiB -1 -1 0.11 18060 1 0.03 -1 -1 30208 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 341 285 1 219 88 17 17 289 -1 unnamed_device 24.9 MiB 1.23 2681 1141 15103 4277 8627 2199 64.5 MiB 0.09 0.00 5.91853 4.58813 -154.793 -4.58813 4.58813 0.25 0.000320476 0.000293647 0.0265283 0.0242834 -1 -1 -1 -1 32 2780 22 6.89349e+06 338252 586450. 2029.24 0.40 0.0714864 0.0634616 25474 144626 -1 2260 21 1752 2418 177496 42479 3.78384 3.78384 -143.369 -3.78384 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0157346 0.0140365 137 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_057.v common 3.73 vpr 65.04 MiB -1 -1 0.13 18444 1 0.03 -1 -1 29980 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66600 32 32 387 293 1 237 93 17 17 289 -1 unnamed_device 25.6 MiB 1.16 2868 1359 7443 1583 5363 497 65.0 MiB 0.06 0.00 6.45037 5.51607 -162.931 -5.51607 5.51607 0.24 0.000366596 0.000336094 0.0148177 0.0136169 -1 -1 -1 -1 32 3548 27 6.89349e+06 408721 586450. 2029.24 1.21 0.122099 0.106722 25474 144626 -1 2719 24 1840 2982 202888 48705 4.85635 4.85635 -159.726 -4.85635 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0194438 0.0173392 166 31 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_058.v common 2.75 vpr 64.23 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29948 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65772 32 32 340 270 1 212 88 17 17 289 -1 unnamed_device 25.2 MiB 1.00 2505 1217 15493 4661 8456 2376 64.2 MiB 0.09 0.00 5.54276 4.5126 -143.919 -4.5126 4.5126 0.24 0.000326565 0.000298191 0.0283386 0.0259713 -1 -1 -1 -1 32 2665 26 6.89349e+06 338252 586450. 2029.24 0.38 0.0732243 0.065078 25474 144626 -1 2106 18 1333 1923 122925 29624 2.94921 2.94921 -122.833 -2.94921 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145007 0.0129746 137 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_059.v common 2.83 vpr 64.14 MiB -1 -1 0.11 17672 1 0.02 -1 -1 29820 -1 -1 32 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 278 235 1 175 94 17 17 289 -1 unnamed_device 25.1 MiB 1.03 2250 1061 16282 4606 9784 1892 64.1 MiB 0.08 0.00 5.16569 4.37039 -131.236 -4.37039 4.37039 0.24 0.000283376 0.000255448 0.0231331 0.021189 -1 -1 -1 -1 30 2166 21 6.89349e+06 451003 556674. 1926.21 0.35 0.0595493 0.0527931 25186 138497 -1 1802 21 1102 1807 103448 25235 3.19625 3.19625 -118.702 -3.19625 0 0 706193. 2443.58 0.04 0.05 0.11 -1 -1 0.04 0.0200294 0.0177972 118 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_060.v common 5.65 vpr 64.85 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29820 -1 -1 30 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66408 32 32 431 332 1 270 94 17 17 289 -1 unnamed_device 25.2 MiB 1.90 3075 1543 15004 4609 8067 2328 64.9 MiB 0.11 0.00 7.91759 6.34645 -186.607 -6.34645 6.34645 0.34 0.000416403 0.000382506 0.0312082 0.0287208 -1 -1 -1 -1 34 3953 24 6.89349e+06 422815 618332. 2139.56 2.22 0.207421 0.183112 25762 151098 -1 3259 22 2492 3991 303577 69677 5.59473 5.59473 -185.938 -5.59473 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0201136 0.017945 182 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_061.v common 3.31 vpr 64.80 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29956 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66356 32 32 336 268 1 205 88 17 17 289 -1 unnamed_device 24.9 MiB 0.88 2530 936 7303 1455 5167 681 64.8 MiB 0.04 0.00 5.66882 4.76668 -140.932 -4.76668 4.76668 0.24 0.000324361 0.00029737 0.013727 0.0125967 -1 -1 -1 -1 34 2331 26 6.89349e+06 338252 618332. 2139.56 1.13 0.102032 0.089028 25762 151098 -1 1928 21 1515 2171 157974 39480 3.73286 3.73286 -126.515 -3.73286 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0156274 0.0139155 136 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_062.v common 2.77 vpr 63.61 MiB -1 -1 0.13 17676 1 0.02 -1 -1 29944 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65132 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 23.9 MiB 0.53 1762 895 10649 2847 7198 604 63.6 MiB 0.05 0.00 3.9244 3.74796 -105.814 -3.74796 3.74796 0.24 0.000268278 0.000244282 0.0179661 0.0166428 -1 -1 -1 -1 32 1907 18 6.89349e+06 394628 586450. 2029.24 0.90 0.0935599 0.0813927 25474 144626 -1 1683 19 741 1322 94047 22538 2.77811 2.77811 -100.732 -2.77811 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110016 0.00974569 96 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_063.v common 4.11 vpr 64.88 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29820 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 349 273 1 214 91 17 17 289 -1 unnamed_device 24.8 MiB 1.25 3131 1378 18043 5544 10561 1938 64.9 MiB 0.11 0.00 6.94676 5.55938 -147.432 -5.55938 5.55938 0.25 0.000339508 0.000310993 0.0322799 0.0295947 -1 -1 -1 -1 30 2968 27 6.89349e+06 380534 556674. 1926.21 1.36 0.143251 0.126546 25186 138497 -1 2443 20 1275 2357 162480 37915 4.27535 4.27535 -136.057 -4.27535 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0192963 0.0171527 146 29 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_064.v common 3.12 vpr 64.30 MiB -1 -1 0.10 17668 1 0.03 -1 -1 29808 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65844 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 24.9 MiB 0.71 2118 762 14407 5564 6574 2269 64.3 MiB 0.06 0.00 4.4685 3.6244 -108.803 -3.6244 3.6244 0.24 0.000261105 0.000238587 0.0216374 0.0197903 -1 -1 -1 -1 34 1873 19 6.89349e+06 295971 618332. 2139.56 1.12 0.118262 0.102525 25762 151098 -1 1576 20 1144 2018 129507 32747 2.93836 2.93836 -105.161 -2.93836 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0122186 0.0108317 99 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_065.v common 3.40 vpr 64.37 MiB -1 -1 0.12 17676 1 0.03 -1 -1 29832 -1 -1 24 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65912 30 32 278 235 1 175 86 17 17 289 -1 unnamed_device 24.7 MiB 1.03 2617 994 11426 3379 7154 893 64.4 MiB 0.06 0.00 5.48567 4.35797 -127.583 -4.35797 4.35797 0.25 0.000284282 0.000261237 0.0182379 0.0167215 -1 -1 -1 -1 30 2087 21 6.89349e+06 338252 556674. 1926.21 1.02 0.105116 0.0921757 25186 138497 -1 1740 21 1006 1535 104945 23844 3.05475 3.05475 -111.469 -3.05475 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0135113 0.011984 110 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_066.v common 4.35 vpr 64.92 MiB -1 -1 0.15 18064 1 0.03 -1 -1 30120 -1 -1 29 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66480 29 32 355 287 1 223 90 17 17 289 -1 unnamed_device 25.2 MiB 1.68 3036 1235 16170 4166 10388 1616 64.9 MiB 0.12 0.00 6.20943 4.65473 -135.021 -4.65473 4.65473 0.26 0.000340499 0.000312371 0.0380566 0.0352096 -1 -1 -1 -1 30 2943 33 6.89349e+06 408721 556674. 1926.21 1.24 0.150728 0.132472 25186 138497 -1 2341 19 1282 1890 114886 27835 3.41865 3.41865 -124.026 -3.41865 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0150858 0.0134617 150 62 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_067.v common 4.30 vpr 64.95 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29764 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 32 32 358 289 1 230 91 17 17 289 -1 unnamed_device 24.9 MiB 1.53 2704 1306 16819 4681 10419 1719 64.9 MiB 0.09 0.00 6.50098 4.98955 -155.576 -4.98955 4.98955 0.32 0.000334926 0.000306435 0.0292019 0.0266694 -1 -1 -1 -1 30 2937 26 6.89349e+06 380534 556674. 1926.21 1.17 0.135449 0.118337 25186 138497 -1 2245 22 1603 2359 152417 37029 4.30739 4.30739 -148.653 -4.30739 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0166872 0.0148652 149 54 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_068.v common 4.36 vpr 64.91 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30160 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 353 285 1 227 89 17 17 289 -1 unnamed_device 24.9 MiB 1.57 2686 1321 12959 3747 7875 1337 64.9 MiB 0.08 0.00 6.75127 5.45967 -157.239 -5.45967 5.45967 0.34 0.000333505 0.000305472 0.0233836 0.0214198 -1 -1 -1 -1 30 3232 23 6.89349e+06 352346 556674. 1926.21 1.24 0.13275 0.115861 25186 138497 -1 2671 21 1571 2337 162253 37482 4.45865 4.45865 -150.907 -4.45865 0 0 706193. 2443.58 0.03 0.05 0.12 -1 -1 0.03 0.016106 0.0143412 144 51 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_069.v common 3.50 vpr 64.39 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29756 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 276 237 1 165 82 17 17 289 -1 unnamed_device 24.9 MiB 1.13 1895 1005 11652 3070 6952 1630 64.4 MiB 0.07 0.00 5.1192 4.9044 -138.677 -4.9044 4.9044 0.26 0.000278309 0.000254748 0.0235075 0.0216386 -1 -1 -1 -1 32 2185 33 6.89349e+06 253689 586450. 2029.24 1.01 0.115145 0.100551 25474 144626 -1 1883 14 742 1011 79811 18262 3.27225 3.27225 -119.982 -3.27225 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0114505 0.0102782 103 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_070.v common 3.91 vpr 64.19 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30176 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65728 31 32 319 272 1 203 85 17 17 289 -1 unnamed_device 25.2 MiB 1.37 2292 1146 15523 5307 8105 2111 64.2 MiB 0.10 0.00 4.5444 3.67535 -123.05 -3.67535 3.67535 0.25 0.000307579 0.000282148 0.0348281 0.0320625 -1 -1 -1 -1 34 2599 23 6.89349e+06 310065 618332. 2139.56 1.15 0.134759 0.118755 25762 151098 -1 2270 20 1476 2059 153853 36261 3.29286 3.29286 -123.024 -3.29286 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0143522 0.0127744 125 64 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_071.v common 4.12 vpr 64.14 MiB -1 -1 0.12 18064 1 0.03 -1 -1 29804 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65684 30 32 329 273 1 213 89 17 17 289 -1 unnamed_device 24.6 MiB 1.51 2646 1203 12761 3384 8201 1176 64.1 MiB 0.07 0.00 4.5069 3.773 -110.836 -3.773 3.773 0.24 0.000311783 0.000285761 0.02181 0.0200015 -1 -1 -1 -1 28 2719 25 6.89349e+06 380534 531479. 1839.03 1.20 0.137278 0.120489 24610 126494 -1 2355 23 1698 2575 179984 42945 3.00476 3.00476 -111.209 -3.00476 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0163353 0.0144894 139 57 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_072.v common 3.37 vpr 64.45 MiB -1 -1 0.11 17676 1 0.03 -1 -1 29840 -1 -1 26 28 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 28 32 277 229 1 171 86 17 17 289 -1 unnamed_device 25.2 MiB 0.89 2290 995 14639 5073 7461 2105 64.5 MiB 0.07 0.00 5.43839 4.41095 -114.576 -4.41095 4.41095 0.24 0.000281419 0.000258556 0.0248781 0.0228497 -1 -1 -1 -1 30 2148 20 6.89349e+06 366440 556674. 1926.21 1.07 0.103487 0.0905008 25186 138497 -1 1844 17 968 1744 111480 25633 3.44096 3.44096 -108.289 -3.44096 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.011729 0.0104772 116 27 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_073.v common 3.60 vpr 64.80 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29776 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66352 30 32 317 269 1 202 85 17 17 289 -1 unnamed_device 24.9 MiB 1.62 2526 1178 15151 5407 7948 1796 64.8 MiB 0.08 0.00 6.03926 4.84252 -145.079 -4.84252 4.84252 0.36 0.000308102 0.00028241 0.0259855 0.0238032 -1 -1 -1 -1 32 2638 26 6.89349e+06 324158 586450. 2029.24 0.54 0.0727006 0.0644386 25474 144626 -1 2199 17 1333 1877 129448 30773 3.77919 3.77919 -132.955 -3.77919 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0129051 0.0115612 127 63 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_074.v common 3.30 vpr 64.90 MiB -1 -1 0.18 18060 1 0.04 -1 -1 29804 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66460 32 32 335 282 1 222 88 17 17 289 -1 unnamed_device 24.9 MiB 1.19 2501 1336 13543 3628 8253 1662 64.9 MiB 0.08 0.00 4.4454 3.9442 -135.714 -3.9442 3.9442 0.24 0.000315843 0.000288919 0.0231779 0.0211775 -1 -1 -1 -1 32 3103 40 6.89349e+06 338252 586450. 2029.24 0.56 0.0750108 0.066122 25474 144626 -1 2494 23 1598 2140 158708 36808 3.28651 3.28651 -129.749 -3.28651 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0160547 0.0142476 131 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_075.v common 2.57 vpr 64.46 MiB -1 -1 0.13 17676 1 0.03 -1 -1 29532 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.7 MiB 0.63 2002 1084 14769 4409 8006 2354 64.5 MiB 0.07 0.00 5.30012 4.68052 -134.297 -4.68052 4.68052 0.24 0.000295535 0.000269833 0.0214319 0.0196168 -1 -1 -1 -1 28 2586 32 6.89349e+06 465097 531479. 1839.03 0.54 0.0663218 0.0585427 24610 126494 -1 2233 21 1356 2590 184684 43970 3.7486 3.7486 -127.386 -3.7486 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.01425 0.0126423 130 4 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_076.v common 3.30 vpr 64.94 MiB -1 -1 0.11 17744 1 0.03 -1 -1 30352 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66496 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 24.9 MiB 1.40 2769 1083 6718 1366 4439 913 64.9 MiB 0.05 0.00 5.69108 4.83188 -148.303 -4.83188 4.83188 0.35 0.000338842 0.000310699 0.0130856 0.0120274 -1 -1 -1 -1 32 2917 37 6.89349e+06 338252 586450. 2029.24 0.48 0.0657926 0.0578615 25474 144626 -1 2309 21 1509 2317 154492 38324 3.91029 3.91029 -139.835 -3.91029 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.016088 0.0143116 142 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_077.v common 5.21 vpr 65.04 MiB -1 -1 0.13 18440 1 0.03 -1 -1 29796 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 32 32 385 308 1 244 92 17 17 289 -1 unnamed_device 25.7 MiB 1.48 2790 1274 17273 5734 8473 3066 65.0 MiB 0.12 0.00 6.85201 5.78412 -176.84 -5.78412 5.78412 0.26 0.000597265 0.000566774 0.0414682 0.0383639 -1 -1 -1 -1 34 3863 36 6.89349e+06 394628 618332. 2139.56 2.28 0.215964 0.190586 25762 151098 -1 2559 23 1887 2646 185724 45717 4.97334 4.97334 -162.157 -4.97334 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0215156 0.0190645 162 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_078.v common 3.67 vpr 64.65 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29836 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66200 32 32 387 309 1 248 93 17 17 289 -1 unnamed_device 25.2 MiB 1.66 3405 1313 11223 3015 7022 1186 64.6 MiB 0.07 0.00 6.15614 4.85896 -154.704 -4.85896 4.85896 0.24 0.000355317 0.000325773 0.0210931 0.0192759 -1 -1 -1 -1 32 3310 32 6.89349e+06 408721 586450. 2029.24 0.54 0.0745848 0.0659313 25474 144626 -1 2572 19 1527 2333 153538 35602 3.68845 3.68845 -137.066 -3.68845 0 0 744469. 2576.02 0.03 0.04 0.13 -1 -1 0.03 0.0166105 0.0147769 163 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_079.v common 3.71 vpr 64.38 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29856 -1 -1 22 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 30 32 272 232 1 175 84 17 17 289 -1 unnamed_device 25.2 MiB 1.31 2272 918 14724 4804 7694 2226 64.4 MiB 0.07 0.00 5.36037 4.39377 -130.219 -4.39377 4.39377 0.24 0.000287341 0.000264486 0.0234956 0.0215251 -1 -1 -1 -1 30 2227 25 6.89349e+06 310065 556674. 1926.21 1.10 0.108014 0.0941904 25186 138497 -1 1897 16 970 1436 106281 24291 3.2479 3.2479 -115.807 -3.2479 0 0 706193. 2443.58 0.03 0.03 0.07 -1 -1 0.03 0.0114634 0.010241 108 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_080.v common 4.51 vpr 64.62 MiB -1 -1 0.12 18060 1 0.04 -1 -1 30192 -1 -1 29 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66172 30 32 375 299 1 236 91 17 17 289 -1 unnamed_device 25.2 MiB 1.55 3003 1114 16819 5989 7667 3163 64.6 MiB 0.09 0.00 6.38211 5.54961 -163.139 -5.54961 5.54961 0.25 0.000340617 0.000311648 0.0301202 0.0275803 -1 -1 -1 -1 34 2922 32 6.89349e+06 408721 618332. 2139.56 1.39 0.156699 0.137371 25762 151098 -1 2293 19 1618 2268 162682 39870 4.68838 4.68838 -154.58 -4.68838 0 0 787024. 2723.27 0.03 0.05 0.08 -1 -1 0.03 0.015856 0.0141856 159 63 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_081.v common 3.54 vpr 64.86 MiB -1 -1 0.13 17916 1 0.03 -1 -1 29880 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 24.9 MiB 0.94 2652 1098 15731 5114 8768 1849 64.9 MiB 0.09 0.00 5.91759 5.21145 -150.283 -5.21145 5.21145 0.24 0.000328416 0.000300997 0.028151 0.0258108 -1 -1 -1 -1 32 2768 22 6.89349e+06 352346 586450. 2029.24 1.20 0.135819 0.119475 25474 144626 -1 2250 20 1419 2440 185945 44358 4.03336 4.03336 -132.792 -4.03336 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0152433 0.0136056 137 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_082.v common 4.27 vpr 64.33 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29652 -1 -1 25 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65872 31 32 340 275 1 211 88 17 17 289 -1 unnamed_device 24.7 MiB 1.65 2743 1182 11788 3318 7484 986 64.3 MiB 0.07 0.00 6.23744 5.09779 -147.137 -5.09779 5.09779 0.24 0.000321184 0.000294656 0.021254 0.0194531 -1 -1 -1 -1 32 2731 26 6.89349e+06 352346 586450. 2029.24 1.07 0.113692 0.0993541 25474 144626 -1 2290 19 1442 2154 142174 34243 4.42139 4.42139 -145.725 -4.42139 0 0 744469. 2576.02 0.03 0.04 0.09 -1 -1 0.03 0.0147709 0.0132276 139 47 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 4.19 vpr 64.57 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30520 -1 -1 30 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66120 30 32 377 310 1 239 92 17 17 289 -1 unnamed_device 24.9 MiB 1.58 3065 1308 17480 5851 9201 2428 64.6 MiB 0.11 0.00 6.31486 5.04907 -145.771 -5.04907 5.04907 0.25 0.000363407 0.000333582 0.034511 0.0317521 -1 -1 -1 -1 34 2995 23 6.89349e+06 422815 618332. 2139.56 1.11 0.131067 0.115037 25762 151098 -1 2440 29 2151 3033 223442 62433 3.98754 3.98754 -132.06 -3.98754 0 0 787024. 2723.27 0.03 0.07 0.08 -1 -1 0.03 0.0212267 0.0187147 160 83 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_084.v common 4.21 vpr 64.60 MiB -1 -1 0.14 18444 1 0.03 -1 -1 30172 -1 -1 25 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66148 32 32 365 294 1 230 89 17 17 289 -1 unnamed_device 25.1 MiB 1.54 2903 1193 13553 4146 6698 2709 64.6 MiB 0.09 0.00 6.82527 5.54847 -159.396 -5.54847 5.54847 0.24 0.000340769 0.000311467 0.0254812 0.0233158 -1 -1 -1 -1 36 2667 24 6.89349e+06 352346 648988. 2245.63 1.27 0.129417 0.113035 26050 158493 -1 2183 22 1623 2400 146356 36675 4.41775 4.41775 -145.775 -4.41775 0 0 828058. 2865.25 0.03 0.05 0.08 -1 -1 0.03 0.0172307 0.0153579 150 57 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 4.61 vpr 64.64 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30156 -1 -1 31 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66188 29 32 378 310 1 246 92 17 17 289 -1 unnamed_device 25.2 MiB 1.49 2857 1221 11684 3249 7028 1407 64.6 MiB 0.07 0.00 5.69689 4.40161 -128.825 -4.40161 4.40161 0.24 0.000347187 0.000318839 0.0212948 0.0195102 -1 -1 -1 -1 30 3093 22 6.89349e+06 436909 556674. 1926.21 1.62 0.150322 0.131694 25186 138497 -1 2297 20 1507 2044 138797 32504 3.501 3.501 -118.443 -3.501 0 0 706193. 2443.58 0.04 0.07 0.12 -1 -1 0.04 0.027885 0.0249954 162 85 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 3.09 vpr 64.28 MiB -1 -1 0.10 17672 1 0.02 -1 -1 30312 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 24.9 MiB 0.72 1910 928 13788 4105 7638 2045 64.3 MiB 0.06 0.00 4.56098 4.02268 -121.319 -4.02268 4.02268 0.25 0.000259422 0.000237335 0.0213947 0.0196035 -1 -1 -1 -1 32 1927 19 6.89349e+06 253689 586450. 2029.24 0.99 0.101249 0.0880851 25474 144626 -1 1681 21 920 1495 107983 25474 2.89716 2.89716 -108.882 -2.89716 0 0 744469. 2576.02 0.04 0.07 0.08 -1 -1 0.04 0.0266531 0.0236216 96 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_087.v common 4.16 vpr 64.99 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29764 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 32 32 373 302 1 241 92 17 17 289 -1 unnamed_device 25.2 MiB 1.26 3226 1286 16652 5101 8812 2739 65.0 MiB 0.10 0.00 7.53678 5.6817 -168.121 -5.6817 5.6817 0.25 0.000349472 0.000320694 0.0296423 0.0271629 -1 -1 -1 -1 34 3248 37 6.89349e+06 394628 618332. 2139.56 1.48 0.155596 0.136385 25762 151098 -1 2485 23 1928 2763 231875 54095 4.63118 4.63118 -153.969 -4.63118 0 0 787024. 2723.27 0.03 0.06 0.08 -1 -1 0.03 0.0185313 0.0165548 156 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_088.v common 3.82 vpr 64.70 MiB -1 -1 0.17 18060 1 0.03 -1 -1 29736 -1 -1 28 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 397 314 1 256 92 17 17 289 -1 unnamed_device 25.2 MiB 1.82 3241 1349 17066 5543 8987 2536 64.7 MiB 0.11 0.00 6.47017 5.4924 -173.425 -5.4924 5.4924 0.25 0.000365552 0.000330091 0.0320572 0.0293256 -1 -1 -1 -1 32 3371 24 6.89349e+06 394628 586450. 2029.24 0.49 0.0824342 0.0732588 25474 144626 -1 2591 21 1981 2792 182661 43773 4.46865 4.46865 -163.826 -4.46865 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.017704 0.0158097 166 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_089.v common 3.55 vpr 64.38 MiB -1 -1 0.13 17676 1 0.02 -1 -1 30172 -1 -1 18 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 269 231 1 172 82 17 17 289 -1 unnamed_device 24.9 MiB 1.01 1994 1069 14144 5297 7505 1342 64.4 MiB 0.07 0.00 4.47373 3.85823 -113.356 -3.85823 3.85823 0.25 0.000269263 0.000246111 0.0229361 0.0209552 -1 -1 -1 -1 26 2405 34 6.89349e+06 253689 503264. 1741.40 1.22 0.104104 0.090382 24322 120374 -1 2118 19 1267 1650 143777 33707 3.05266 3.05266 -112.136 -3.05266 0 0 618332. 2139.56 0.02 0.04 0.06 -1 -1 0.02 0.012389 0.0110027 104 29 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_090.v common 3.15 vpr 64.09 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30312 -1 -1 22 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65632 31 32 245 205 1 153 85 17 17 289 -1 unnamed_device 24.6 MiB 0.82 2028 838 14407 3892 9360 1155 64.1 MiB 0.07 0.00 4.70033 3.85018 -114.048 -3.85018 3.85018 0.24 0.000258947 0.000237202 0.0224492 0.0205414 -1 -1 -1 -1 32 1902 23 6.89349e+06 310065 586450. 2029.24 1.05 0.117197 0.101976 25474 144626 -1 1656 20 933 1613 114014 26385 2.82486 2.82486 -106.443 -2.82486 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.01196 0.0105886 100 4 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_091.v common 3.10 vpr 64.52 MiB -1 -1 0.12 18056 1 0.03 -1 -1 30000 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66072 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 24.9 MiB 1.32 2676 1136 9448 2110 6726 612 64.5 MiB 0.06 0.00 5.50572 4.64652 -147.013 -4.64652 4.64652 0.25 0.000337089 0.000309156 0.0178547 0.0163613 -1 -1 -1 -1 32 2903 23 6.89349e+06 338252 586450. 2029.24 0.41 0.0621535 0.0549096 25474 144626 -1 2275 18 1479 2130 167790 37316 3.63095 3.63095 -136.052 -3.63095 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0145128 0.0129763 142 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_092.v common 4.39 vpr 64.57 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29816 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 356 289 1 223 90 17 17 289 -1 unnamed_device 24.9 MiB 1.43 2323 1112 13758 4906 6702 2150 64.6 MiB 0.08 0.00 5.68208 4.94624 -146.779 -4.94624 4.94624 0.25 0.000331787 0.000302979 0.0262302 0.0240273 -1 -1 -1 -1 38 2572 49 6.89349e+06 366440 678818. 2348.85 1.52 0.168236 0.146876 26626 170182 -1 2205 27 1686 2316 190689 61677 4.12995 4.12995 -139.314 -4.12995 0 0 902133. 3121.57 0.03 0.06 0.09 -1 -1 0.03 0.0196348 0.0174401 145 56 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_093.v common 2.83 vpr 64.91 MiB -1 -1 0.14 18060 1 0.03 -1 -1 29788 -1 -1 37 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66464 32 32 349 260 1 204 101 17 17 289 -1 unnamed_device 24.9 MiB 0.51 2788 1276 12556 3435 8230 891 64.9 MiB 0.09 0.00 6.16499 5.16501 -145.808 -5.16501 5.16501 0.38 0.000394125 0.000363253 0.0265423 0.0244872 -1 -1 -1 -1 32 3172 25 6.89349e+06 521472 586450. 2029.24 0.72 0.0967584 0.0855786 25474 144626 -1 2570 21 1634 3205 242418 55454 4.33309 4.33309 -144.215 -4.33309 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0179264 0.0159944 158 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_094.v common 4.27 vpr 64.20 MiB -1 -1 0.17 18440 1 0.03 -1 -1 29780 -1 -1 28 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65736 30 32 316 264 1 208 90 17 17 289 -1 unnamed_device 25.2 MiB 1.21 2512 1137 8934 2329 5933 672 64.2 MiB 0.06 0.00 4.62558 3.87324 -113.147 -3.87324 3.87324 0.26 0.000430676 0.000404412 0.0194294 0.0180078 -1 -1 -1 -1 26 2997 43 6.89349e+06 394628 503264. 1741.40 1.64 0.141375 0.123852 24322 120374 -1 2387 26 1622 2422 199717 53667 3.36211 3.36211 -112.626 -3.36211 0 0 618332. 2139.56 0.02 0.06 0.07 -1 -1 0.02 0.0171514 0.0151399 133 52 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_095.v common 2.50 vpr 64.38 MiB -1 -1 0.11 17676 1 0.02 -1 -1 30560 -1 -1 24 27 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65928 27 32 255 219 1 162 83 17 17 289 -1 unnamed_device 24.9 MiB 0.89 1709 895 11423 3598 6289 1536 64.4 MiB 0.06 0.00 5.37186 4.45989 -120.873 -4.45989 4.45989 0.25 0.000258494 0.000236562 0.0197284 0.0181083 -1 -1 -1 -1 32 1885 21 6.89349e+06 338252 586450. 2029.24 0.33 0.0533561 0.0470861 25474 144626 -1 1605 17 829 1207 77343 18883 3.505 3.505 -112.859 -3.505 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0110978 0.00988432 104 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_096.v common 5.27 vpr 65.19 MiB -1 -1 0.15 18052 1 0.03 -1 -1 29756 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66756 32 32 421 327 1 271 95 17 17 289 -1 unnamed_device 25.2 MiB 1.78 3336 1650 16943 4550 10611 1782 65.2 MiB 0.17 0.00 5.75687 4.66636 -149.532 -4.66636 4.66636 0.28 0.000384059 0.000352114 0.0541153 0.0500458 -1 -1 -1 -1 32 4257 48 6.89349e+06 436909 586450. 2029.24 1.95 0.218959 0.193276 25474 144626 -1 3241 25 2181 3435 276689 69635 4.34439 4.34439 -149.479 -4.34439 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0212911 0.0189332 181 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_097.v common 3.79 vpr 64.60 MiB -1 -1 0.15 18060 1 0.03 -1 -1 30148 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66152 31 32 365 296 1 233 89 17 17 289 -1 unnamed_device 24.9 MiB 1.40 2877 1253 10781 3020 6724 1037 64.6 MiB 0.07 0.00 6.6941 5.817 -167.929 -5.817 5.817 0.25 0.000354766 0.00032589 0.0218487 0.0201788 -1 -1 -1 -1 30 2956 23 6.89349e+06 366440 556674. 1926.21 1.02 0.112557 0.0989778 25186 138497 -1 2341 19 1649 2421 144006 35330 4.38675 4.38675 -149.789 -4.38675 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0154389 0.0138086 151 64 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_098.v common 3.96 vpr 63.84 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29908 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65376 32 32 331 280 1 221 87 17 17 289 -1 unnamed_device 24.9 MiB 1.25 2547 1197 9303 2202 6355 746 63.8 MiB 0.06 0.00 5.09387 4.28945 -141.157 -4.28945 4.28945 0.25 0.00042315 0.000395805 0.019167 0.0177577 -1 -1 -1 -1 28 3036 35 6.89349e+06 324158 531479. 1839.03 1.34 0.126513 0.110677 24610 126494 -1 2512 25 1803 2385 195350 47064 4.2519 4.2519 -146.428 -4.2519 0 0 648988. 2245.63 0.03 0.07 0.07 -1 -1 0.03 0.0238407 0.021067 132 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_099.v common 3.83 vpr 64.82 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29904 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66380 32 32 326 263 1 203 88 17 17 289 -1 unnamed_device 25.0 MiB 1.30 2319 1186 11593 3417 7038 1138 64.8 MiB 0.07 0.00 6.11951 5.26542 -147.058 -5.26542 5.26542 0.24 0.000321945 0.000295215 0.0228394 0.0210531 -1 -1 -1 -1 30 2530 20 6.89349e+06 338252 556674. 1926.21 1.15 0.135844 0.118798 25186 138497 -1 2079 20 1172 1728 106041 25591 3.68526 3.68526 -129.365 -3.68526 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0173921 0.0156473 131 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_100.v common 3.69 vpr 65.00 MiB -1 -1 0.13 18064 1 0.03 -1 -1 30232 -1 -1 28 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 31 32 373 294 1 231 91 17 17 289 -1 unnamed_device 25.1 MiB 1.27 2701 1254 13759 3627 8626 1506 65.0 MiB 0.08 0.00 5.36757 4.57215 -129.401 -4.57215 4.57215 0.24 0.000371097 0.000341499 0.0274086 0.0252012 -1 -1 -1 -1 32 2893 23 6.89349e+06 394628 586450. 2029.24 1.04 0.127297 0.11159 25474 144626 -1 2390 20 1697 2539 165581 39636 3.8238 3.8238 -127.582 -3.8238 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0171484 0.0153377 158 50 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_101.v common 3.88 vpr 64.89 MiB -1 -1 0.12 18056 1 0.03 -1 -1 29868 -1 -1 27 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66444 30 32 325 268 1 210 89 17 17 289 -1 unnamed_device 24.9 MiB 1.36 2500 1222 15731 4428 8998 2305 64.9 MiB 0.09 0.00 5.01568 4.37438 -123.571 -4.37438 4.37438 0.24 0.000307761 0.000281755 0.0263716 0.0241537 -1 -1 -1 -1 34 2819 30 6.89349e+06 380534 618332. 2139.56 1.15 0.118553 0.103653 25762 151098 -1 2471 19 1223 1977 156412 35023 3.48615 3.48615 -117.196 -3.48615 0 0 787024. 2723.27 0.03 0.05 0.09 -1 -1 0.03 0.0169984 0.0150589 134 51 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_102.v common 4.61 vpr 64.93 MiB -1 -1 0.20 18056 1 0.03 -1 -1 29764 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66492 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 25.5 MiB 1.70 2913 1236 16468 4324 10879 1265 64.9 MiB 0.10 0.00 5.92998 4.92758 -154.078 -4.92758 4.92758 0.24 0.000375636 0.000345494 0.0296261 0.0271151 -1 -1 -1 -1 32 3235 49 6.89349e+06 338252 586450. 2029.24 1.34 0.160502 0.140912 25474 144626 -1 2641 21 1807 2827 217818 50476 3.81776 3.81776 -142.241 -3.81776 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0167762 0.0149719 143 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_103.v common 4.98 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29592 -1 -1 29 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66608 32 32 386 307 1 246 93 17 17 289 -1 unnamed_device 25.2 MiB 1.63 2578 1265 14583 4645 6831 3107 65.0 MiB 0.08 0.00 4.8916 4.45823 -142.35 -4.45823 4.45823 0.24 0.000360905 0.000330749 0.0267126 0.0244643 -1 -1 -1 -1 36 3322 50 6.89349e+06 408721 648988. 2245.63 1.94 0.173141 0.15178 26050 158493 -1 2430 26 2202 3086 217671 55907 3.43671 3.43671 -127.871 -3.43671 0 0 828058. 2865.25 0.03 0.08 0.08 -1 -1 0.03 0.0275492 0.0245357 160 62 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_104.v common 2.65 vpr 64.39 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29828 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 29 32 269 229 1 173 83 17 17 289 -1 unnamed_device 24.9 MiB 0.87 1941 905 12863 3695 7288 1880 64.4 MiB 0.06 0.00 4.94313 4.20923 -126.338 -4.20923 4.20923 0.28 0.000269427 0.000245811 0.0208088 0.0190655 -1 -1 -1 -1 32 1947 26 6.89349e+06 310065 586450. 2029.24 0.38 0.0634184 0.0559623 25474 144626 -1 1640 18 1223 1625 105232 25124 3.02451 3.02451 -110.783 -3.02451 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0116555 0.0103855 108 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_105.v common 3.55 vpr 64.53 MiB -1 -1 0.11 18440 1 0.02 -1 -1 30308 -1 -1 21 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 310 266 1 198 85 17 17 289 -1 unnamed_device 24.9 MiB 1.00 2331 1018 14593 5365 7180 2048 64.5 MiB 0.07 0.00 5.35099 4.29493 -129.187 -4.29493 4.29493 0.24 0.000296307 0.000271021 0.0248078 0.0226923 -1 -1 -1 -1 34 2466 24 6.89349e+06 295971 618332. 2139.56 1.15 0.108741 0.0947769 25762 151098 -1 1986 19 1370 1939 133873 32096 3.832 3.832 -129.652 -3.832 0 0 787024. 2723.27 0.03 0.04 0.08 -1 -1 0.03 0.0135162 0.0120723 121 58 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_106.v common 3.39 vpr 64.43 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30268 -1 -1 26 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65980 31 32 326 261 1 204 89 17 17 289 -1 unnamed_device 24.9 MiB 0.97 2471 1196 14741 4167 8661 1913 64.4 MiB 0.08 0.00 5.98928 4.87948 -139.23 -4.87948 4.87948 0.24 0.000320063 0.000293836 0.024991 0.0228928 -1 -1 -1 -1 26 2979 26 6.89349e+06 366440 503264. 1741.40 1.07 0.104685 0.0918426 24322 120374 -1 2528 23 1727 2832 223076 51486 3.8639 3.8639 -135.445 -3.8639 0 0 618332. 2139.56 0.02 0.06 0.06 -1 -1 0.02 0.0164645 0.0146522 134 33 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_107.v common 3.77 vpr 63.91 MiB -1 -1 0.12 17672 1 0.03 -1 -1 29900 -1 -1 22 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65440 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.8 MiB 1.12 2013 926 8543 2203 5453 887 63.9 MiB 0.04 0.00 5.29312 4.18332 -115.535 -4.18332 4.18332 0.26 0.000268815 0.00024715 0.0138272 0.0126803 -1 -1 -1 -1 26 2277 48 6.89349e+06 310065 503264. 1741.40 1.30 0.100987 0.0875584 24322 120374 -1 2031 27 1546 2031 172833 51950 3.3714 3.3714 -109.468 -3.3714 0 0 618332. 2139.56 0.02 0.05 0.06 -1 -1 0.02 0.0154285 0.0135584 105 31 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_108.v common 3.52 vpr 63.93 MiB -1 -1 0.11 17672 1 0.03 -1 -1 29880 -1 -1 20 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65460 32 32 278 238 1 182 84 17 17 289 -1 unnamed_device 24.7 MiB 1.16 2123 1039 14358 3958 8394 2006 63.9 MiB 0.07 0.00 5.08457 4.36857 -137.465 -4.36857 4.36857 0.24 0.000278263 0.000254499 0.0233188 0.021363 -1 -1 -1 -1 30 2385 23 6.89349e+06 281877 556674. 1926.21 1.07 0.109577 0.0957306 25186 138497 -1 2017 21 1374 2007 134054 31869 3.07751 3.07751 -120.896 -3.07751 0 0 706193. 2443.58 0.03 0.04 0.07 -1 -1 0.03 0.0134373 0.0119178 109 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 3.60 vpr 65.00 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29840 -1 -1 29 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66560 31 32 373 300 1 237 92 17 17 289 -1 unnamed_device 25.6 MiB 1.50 2847 1321 9407 2126 6476 805 65.0 MiB 0.06 0.00 5.94996 4.99396 -156.415 -4.99396 4.99396 0.24 0.000346762 0.00031781 0.0173071 0.0158311 -1 -1 -1 -1 28 3256 26 6.89349e+06 408721 531479. 1839.03 0.66 0.0811964 0.0718657 24610 126494 -1 2728 22 2029 2815 203521 48201 3.81684 3.81684 -144.87 -3.81684 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0174056 0.0154965 157 64 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_110.v common 3.81 vpr 63.98 MiB -1 -1 0.18 18056 1 0.03 -1 -1 29852 -1 -1 20 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65512 31 32 265 230 1 175 83 17 17 289 -1 unnamed_device 24.9 MiB 1.23 1998 822 6203 1282 4444 477 64.0 MiB 0.04 0.00 4.0554 3.59765 -110.566 -3.59765 3.59765 0.26 0.000325594 0.000302519 0.0132653 0.0122948 -1 -1 -1 -1 34 2076 24 6.89349e+06 281877 618332. 2139.56 1.12 0.115819 0.100786 25762 151098 -1 1723 20 1130 1580 102110 25750 2.82336 2.82336 -104.389 -2.82336 0 0 787024. 2723.27 0.03 0.03 0.08 -1 -1 0.03 0.0126467 0.0112452 103 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_111.v common 3.63 vpr 64.95 MiB -1 -1 0.12 18060 1 0.03 -1 -1 30136 -1 -1 24 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66508 32 32 349 286 1 221 88 17 17 289 -1 unnamed_device 24.9 MiB 1.25 2652 1326 9253 2409 6050 794 64.9 MiB 0.07 0.00 4.83964 4.21314 -126.908 -4.21314 4.21314 0.26 0.000335167 0.000307637 0.02296 0.0211984 -1 -1 -1 -1 32 2832 23 6.89349e+06 338252 586450. 2029.24 1.03 0.113834 0.099746 25474 144626 -1 2356 20 1336 1987 129392 30987 3.4009 3.4009 -123.821 -3.4009 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0155457 0.0138799 141 57 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_112.v common 4.76 vpr 64.70 MiB -1 -1 0.13 18060 1 0.03 -1 -1 29572 -1 -1 31 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66252 31 32 396 325 1 259 94 17 17 289 -1 unnamed_device 25.2 MiB 1.76 2853 1403 14578 4264 8207 2107 64.7 MiB 0.10 0.00 5.59288 4.8279 -156.525 -4.8279 4.8279 0.26 0.000369837 0.000335668 0.0333882 0.0308902 -1 -1 -1 -1 30 3242 26 6.89349e+06 436909 556674. 1926.21 1.56 0.142469 0.12585 25186 138497 -1 2649 19 1916 2730 173100 41045 4.05069 4.05069 -152.083 -4.05069 0 0 706193. 2443.58 0.03 0.05 0.07 -1 -1 0.03 0.0168232 0.0150458 168 91 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_113.v common 3.26 vpr 64.76 MiB -1 -1 0.11 18060 1 0.03 -1 -1 29756 -1 -1 22 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 303 262 1 200 86 17 17 289 -1 unnamed_device 24.9 MiB 1.33 2386 1003 8213 1905 5885 423 64.8 MiB 0.07 0.00 5.08019 3.80489 -115.807 -3.80489 3.80489 0.25 0.000384058 0.000353865 0.0240162 0.0223341 -1 -1 -1 -1 26 2751 41 6.89349e+06 310065 503264. 1741.40 0.56 0.0757766 0.067046 24322 120374 -1 2325 35 2024 2740 201705 49859 3.37141 3.37141 -124.682 -3.37141 0 0 618332. 2139.56 0.03 0.07 0.07 -1 -1 0.03 0.0273323 0.0239382 121 57 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 3.46 vpr 63.79 MiB -1 -1 0.12 18444 1 0.03 -1 -1 30148 -1 -1 19 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65324 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.6 MiB 0.81 2269 837 15023 5167 6942 2914 63.8 MiB 0.08 0.00 5.43847 4.34657 -130.295 -4.34657 4.34657 0.24 0.000423514 0.000388067 0.0296063 0.0270771 -1 -1 -1 -1 36 2125 20 6.89349e+06 267783 648988. 2245.63 1.29 0.13798 0.120975 26050 158493 -1 1708 21 1250 1889 158472 38821 3.16246 3.16246 -117.696 -3.16246 0 0 828058. 2865.25 0.03 0.04 0.08 -1 -1 0.03 0.0138878 0.0123302 111 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_115.v common 3.92 vpr 64.39 MiB -1 -1 0.16 18056 1 0.03 -1 -1 29808 -1 -1 23 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 318 257 1 197 87 17 17 289 -1 unnamed_device 24.9 MiB 1.51 2206 1061 15255 5362 7838 2055 64.4 MiB 0.12 0.00 5.66222 4.93863 -135.261 -4.93863 4.93863 0.38 0.000465778 0.000424965 0.0394743 0.0360442 -1 -1 -1 -1 32 2576 20 6.89349e+06 324158 586450. 2029.24 0.55 0.10291 0.0916188 25474 144626 -1 2067 20 1241 1762 109322 26595 3.75376 3.75376 -127.245 -3.75376 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.014591 0.0129818 130 30 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_116.v common 2.99 vpr 64.83 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30232 -1 -1 28 29 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66388 29 32 324 268 1 205 89 17 17 289 -1 unnamed_device 25.2 MiB 1.21 2470 1190 15335 4895 8484 1956 64.8 MiB 0.12 0.00 4.7462 4.04278 -114.91 -4.04278 4.04278 0.25 0.000470059 0.000430443 0.0387134 0.0355344 -1 -1 -1 -1 32 2572 19 6.89349e+06 394628 586450. 2029.24 0.37 0.0791568 0.070506 25474 144626 -1 2079 21 1060 1535 114324 26106 3.1022 3.1022 -107.005 -3.1022 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0151094 0.0134471 136 55 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 3.77 vpr 65.06 MiB -1 -1 0.14 18056 1 0.03 -1 -1 29764 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66620 32 32 393 312 1 243 90 17 17 289 -1 unnamed_device 25.2 MiB 1.77 2982 1296 15567 4292 8859 2416 65.1 MiB 0.11 0.00 6.82244 5.69986 -179.713 -5.69986 5.69986 0.26 0.000519859 0.000488808 0.0338423 0.0310508 -1 -1 -1 -1 32 3149 23 6.89349e+06 366440 586450. 2029.24 0.50 0.0977618 0.086857 25474 144626 -1 2680 23 2091 3202 214974 51581 4.45265 4.45265 -163.975 -4.45265 0 0 744469. 2576.02 0.03 0.06 0.11 -1 -1 0.03 0.0183996 0.016371 162 65 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 3.84 vpr 64.24 MiB -1 -1 0.12 17672 1 0.02 -1 -1 29940 -1 -1 18 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65784 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 24.9 MiB 1.21 1779 858 10231 2722 6503 1006 64.2 MiB 0.07 0.00 3.8889 3.28224 -101.713 -3.28224 3.28224 0.45 0.000385879 0.000354379 0.0241506 0.0220973 -1 -1 -1 -1 30 1861 20 6.89349e+06 253689 556674. 1926.21 0.74 0.0892488 0.0792797 25186 138497 -1 1517 18 846 1343 70273 18201 2.62851 2.62851 -97.2865 -2.62851 0 0 706193. 2443.58 0.04 0.04 0.11 -1 -1 0.04 0.0159301 0.0141792 93 4 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 7.04 vpr 65.12 MiB -1 -1 0.16 18680 1 0.03 -1 -1 30100 -1 -1 31 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66684 32 32 412 334 1 269 95 17 17 289 -1 unnamed_device 25.6 MiB 2.35 3112 1429 7871 1651 5611 609 65.1 MiB 0.06 0.00 7.06988 5.66654 -175.904 -5.66654 5.66654 0.34 0.000375537 0.000339759 0.0156753 0.0143834 -1 -1 -1 -1 24 4306 40 6.89349e+06 436909 470940. 1629.55 3.01 0.164231 0.144271 24034 113901 -1 3379 35 3463 4537 442158 133615 5.55244 5.55244 -193.596 -5.55244 0 0 586450. 2029.24 0.02 0.11 0.06 -1 -1 0.02 0.0262324 0.0232024 172 90 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 3.77 vpr 65.05 MiB -1 -1 0.13 18060 1 0.03 -1 -1 30196 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 376 318 1 259 91 17 17 289 -1 unnamed_device 25.2 MiB 1.60 2995 1457 17227 5058 10064 2105 65.1 MiB 0.20 0.00 6.59283 5.06664 -170.928 -5.06664 5.06664 0.28 0.00033737 0.000308852 0.0723416 0.0671243 -1 -1 -1 -1 32 3389 24 6.89349e+06 380534 586450. 2029.24 0.53 0.118774 0.107591 25474 144626 -1 2826 20 2173 2713 238525 51366 4.42408 4.42408 -166.095 -4.42408 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0158806 0.0141647 154 96 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 4.46 vpr 64.99 MiB -1 -1 0.16 18056 1 0.04 -1 -1 30148 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66548 32 32 360 293 1 226 90 17 17 289 -1 unnamed_device 24.9 MiB 1.76 2575 1188 14361 4167 7345 2849 65.0 MiB 0.14 0.00 4.49365 4.14004 -127.133 -4.14004 4.14004 0.44 0.000619044 0.000567785 0.0472235 0.0432217 -1 -1 -1 -1 32 2842 27 6.89349e+06 366440 586450. 2029.24 0.75 0.140806 0.125491 25474 144626 -1 2167 18 1381 1988 128583 31532 3.26765 3.26765 -116.85 -3.26765 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0154305 0.0137976 147 60 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 4.23 vpr 65.05 MiB -1 -1 0.12 18060 1 0.03 -1 -1 29792 -1 -1 27 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66616 32 32 396 299 1 240 91 17 17 289 -1 unnamed_device 25.2 MiB 1.61 2868 1421 16615 5234 8988 2393 65.1 MiB 0.10 0.00 6.7782 5.7937 -174.554 -5.7937 5.7937 0.24 0.000377195 0.000345698 0.0328161 0.0301431 -1 -1 -1 -1 32 3522 22 6.89349e+06 380534 586450. 2029.24 1.21 0.139004 0.122484 25474 144626 -1 2816 20 1940 3057 243941 59443 4.77005 4.77005 -160.085 -4.77005 0 0 744469. 2576.02 0.03 0.07 0.08 -1 -1 0.03 0.0206995 0.0185208 167 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 2.39 vpr 63.83 MiB -1 -1 0.11 17672 1 0.02 -1 -1 30220 -1 -1 17 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65364 30 32 224 207 1 138 79 17 17 289 -1 unnamed_device 24.9 MiB 0.67 1877 553 12416 4327 6159 1930 63.8 MiB 0.05 0.00 3.67846 3.05196 -89.5454 -3.05196 3.05196 0.24 0.000240967 0.000220771 0.0184976 0.0169233 -1 -1 -1 -1 32 1600 50 6.89349e+06 239595 586450. 2029.24 0.41 0.0589787 0.0516028 25474 144626 -1 1097 15 520 670 46236 12957 2.13076 2.13076 -83.1557 -2.13076 0 0 744469. 2576.02 0.03 0.02 0.08 -1 -1 0.03 0.00913946 0.00819187 79 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 2.61 vpr 64.39 MiB -1 -1 0.12 17676 1 0.02 -1 -1 29772 -1 -1 23 30 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65936 30 32 286 239 1 176 85 17 17 289 -1 unnamed_device 25.0 MiB 0.95 1847 961 11617 2788 7841 988 64.4 MiB 0.06 0.00 5.09505 4.48403 -138.191 -4.48403 4.48403 0.24 0.000279345 0.000255614 0.018968 0.0173529 -1 -1 -1 -1 32 1983 22 6.89349e+06 324158 586450. 2029.24 0.36 0.0566188 0.0499704 25474 144626 -1 1730 24 1374 2089 138709 33546 3.26135 3.26135 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-1 -1 22 25 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65776 25 32 216 194 1 138 79 17 17 289 -1 unnamed_device 24.9 MiB 0.81 1444 623 8698 3045 3646 2007 64.2 MiB 0.04 0.00 4.2673 3.669 -85.1281 -3.669 3.669 0.24 0.000223849 0.000204642 0.0128618 0.011782 -1 -1 -1 -1 34 1477 40 6.89349e+06 310065 618332. 2139.56 0.48 0.0554996 0.0482709 25762 151098 -1 1167 17 675 1007 65080 17606 2.74431 2.74431 -76.9396 -2.74431 0 0 787024. 2723.27 0.03 0.02 0.08 -1 -1 0.03 0.00963225 0.00859939 88 29 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 4.70 vpr 64.68 MiB -1 -1 0.13 18056 1 0.03 -1 -1 30176 -1 -1 26 32 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66232 32 32 376 307 1 242 90 17 17 289 -1 unnamed_device 25.2 MiB 1.91 3246 1394 13155 3589 8227 1339 64.7 MiB 0.10 0.00 5.69179 4.38685 -135.96 -4.38685 4.38685 0.27 0.00035587 0.000326364 0.0317988 0.0292838 -1 -1 -1 -1 28 3647 48 6.89349e+06 366440 531479. 1839.03 1.37 0.175343 0.154197 24610 126494 -1 2835 24 2070 3115 222959 51695 3.94436 3.94436 -138.765 -3.94436 0 0 648988. 2245.63 0.02 0.06 0.07 -1 -1 0.02 0.0182264 0.0161589 155 72 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 3.95 vpr 64.75 MiB -1 -1 0.21 18056 1 0.03 -1 -1 29792 -1 -1 33 31 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 31 32 409 331 1 264 96 17 17 289 -1 unnamed_device 25.2 MiB 1.66 3421 1405 9951 2248 6876 827 64.8 MiB 0.07 0.00 6.59166 4.95446 -159.482 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rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 3.89 vpr 66.08 MiB -1 -1 0.26 21876 14 0.31 -1 -1 36952 -1 -1 40 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67664 32 32 277 309 1 203 104 17 17 289 -1 unnamed_device 26.5 MiB 0.12 3169.62 1468 11328 2379 7541 1408 66.1 MiB 0.09 0.00 10.3228 8.34809 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7.09678 7.09678 -155.225 -7.09678 0 0 585099. 2024.56 0.04 0.08 0.10 -1 -1 0.04 0.0317698 0.0288729 191 184 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 3.12 vpr 65.70 MiB -1 -1 0.23 21876 11 0.28 -1 -1 36392 -1 -1 39 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67272 32 32 280 312 1 187 103 17 17 289 -1 unnamed_device 26.3 MiB 0.10 2827.47 1361 6128 1131 4405 592 65.7 MiB 0.05 0.00 8.30478 6.65392 -136.28 -6.65392 6.65392 0.38 0.000685019 0.000627322 0.021068 0.019208 -1 -1 -1 -1 28 3532 22 6.55708e+06 470145 500653. 1732.36 0.82 0.118722 0.105973 21310 115450 -1 2893 19 1295 4984 238971 59050 5.81978 5.81978 -132.978 -5.81978 0 0 612192. 2118.31 0.04 0.09 0.10 -1 -1 0.04 0.0348243 0.0316162 193 186 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 3.20 vpr 66.12 MiB -1 -1 0.25 21760 12 0.40 -1 -1 36592 -1 -1 40 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67712 29 32 275 307 1 194 101 17 17 289 -1 unnamed_device 26.6 MiB 0.11 2959.93 1244 8326 1689 5934 703 66.1 MiB 0.07 0.00 9.98698 7.42963 -136.806 -7.42963 7.42963 0.38 0.000669962 0.000607111 0.0283615 0.025869 -1 -1 -1 -1 22 3463 27 6.55708e+06 482200 420624. 1455.45 0.80 0.131119 0.117064 20158 92377 -1 3149 20 1718 5783 304181 76974 6.67344 6.67344 -140.022 -6.67344 0 0 500653. 1732.36 0.03 0.10 0.08 -1 -1 0.03 0.03459 0.0313747 200 190 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 3.15 vpr 66.00 MiB -1 -1 0.25 21492 13 0.34 -1 -1 36488 -1 -1 42 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67584 32 32 302 334 1 214 106 17 17 289 -1 unnamed_device 26.5 MiB 0.11 3277.06 1472 9856 1982 7031 843 66.0 MiB 0.09 0.00 10.9395 7.98333 -168.064 -7.98333 7.98333 0.38 0.00073336 0.000671344 0.0339117 0.0307888 -1 -1 -1 -1 26 3770 18 6.55708e+06 506310 477104. 1650.88 0.77 0.135199 0.121169 21022 109990 -1 3230 16 1274 3900 187211 47077 7.22463 7.22463 -162.98 -7.22463 0 0 585099. 2024.56 0.04 0.08 0.10 -1 -1 0.04 0.0318915 0.0291686 217 208 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 3.54 vpr 66.08 MiB -1 -1 0.27 22260 13 0.31 -1 -1 36232 -1 -1 42 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67668 32 32 292 324 1 212 106 17 17 289 -1 unnamed_device 26.5 MiB 0.12 2866.18 1500 7356 1329 5608 419 66.1 MiB 0.11 0.00 9.67796 7.98192 -159.937 -7.98192 7.98192 0.63 0.00139642 0.00129274 0.0459519 0.042212 -1 -1 -1 -1 30 3231 22 6.55708e+06 506310 526063. 1820.29 0.73 0.146458 0.131734 21886 126133 -1 2914 15 1161 4203 188301 46205 6.76976 6.76976 -150.378 -6.76976 0 0 666494. 2306.21 0.04 0.08 0.11 -1 -1 0.04 0.0336377 0.0309442 204 198 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 2.76 vpr 65.55 MiB -1 -1 0.23 21492 12 0.24 -1 -1 36300 -1 -1 38 27 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67124 27 32 229 261 1 167 97 17 17 289 -1 unnamed_device 25.8 MiB 0.08 2337.6 1007 8533 2013 5783 737 65.6 MiB 0.06 0.00 9.40566 7.49882 -132.896 -7.49882 7.49882 0.38 0.000552254 0.000505905 0.0245751 0.0224503 -1 -1 -1 -1 22 2846 33 6.55708e+06 458090 420624. 1455.45 0.60 0.112048 0.0994876 20158 92377 -1 2495 21 936 2825 151732 38675 7.10844 7.10844 -133.129 -7.10844 0 0 500653. 1732.36 0.03 0.07 0.08 -1 -1 0.03 0.0280295 0.025318 162 150 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 3.00 vpr 65.47 MiB -1 -1 0.25 21492 12 0.23 -1 -1 36264 -1 -1 36 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67044 31 32 229 261 1 172 99 17 17 289 -1 unnamed_device 25.8 MiB 0.10 2493.15 1182 11499 2779 7797 923 65.5 MiB 0.08 0.00 7.48917 6.1978 -123.822 -6.1978 6.1978 0.38 0.00056773 0.000506178 0.030645 0.0277267 -1 -1 -1 -1 26 3022 23 6.55708e+06 433980 477104. 1650.88 0.81 0.108706 0.0964251 21022 109990 -1 2558 15 983 3146 160300 39339 5.61152 5.61152 -124 -5.61152 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0222613 0.0201289 153 138 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 3.41 vpr 65.48 MiB -1 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67320 32 32 250 282 1 190 99 17 17 289 -1 unnamed_device 25.9 MiB 0.12 2595.52 1285 6255 1073 4701 481 65.7 MiB 0.05 0.00 9.61062 7.56812 -165.213 -7.56812 7.56812 0.38 0.000605567 0.000554364 0.0202438 0.0184769 -1 -1 -1 -1 26 3258 24 6.55708e+06 421925 477104. 1650.88 0.63 0.105188 0.0932418 21022 109990 -1 2743 21 1276 3790 183407 45756 6.89358 6.89358 -162.183 -6.89358 0 0 585099. 2024.56 0.04 0.08 0.10 -1 -1 0.04 0.0309459 0.027806 166 156 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 2.76 vpr 65.55 MiB -1 -1 0.23 21684 12 0.23 -1 -1 36512 -1 -1 33 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67128 30 32 216 248 1 160 95 17 17 289 -1 unnamed_device 25.9 MiB 0.11 2363.89 1089 9383 1996 6576 811 65.6 MiB 0.07 0.00 8.78898 6.99514 -141.661 -6.99514 6.99514 0.38 0.000529923 0.000484989 0.0259183 0.0236751 -1 -1 -1 -1 28 2591 19 6.55708e+06 397815 500653. 1732.36 0.59 0.0963312 0.0855929 21310 115450 -1 2231 16 835 2644 129323 32207 6.02864 6.02864 -134.773 -6.02864 0 0 612192. 2118.31 0.04 0.05 0.10 -1 -1 0.04 0.0221928 0.0200967 140 128 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 2.67 vpr 65.43 MiB -1 -1 0.23 21496 12 0.19 -1 -1 36556 -1 -1 33 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67000 32 32 236 268 1 171 97 17 17 289 -1 unnamed_device 25.8 MiB 0.11 2486.52 1250 7201 1363 5333 505 65.4 MiB 0.06 0.00 7.92826 6.93051 -150.969 -6.93051 6.93051 0.38 0.000563433 0.000502023 0.0212353 0.019302 -1 -1 -1 -1 22 3133 21 6.55708e+06 397815 420624. 1455.45 0.57 0.0974754 0.0865551 20158 92377 -1 2873 18 1055 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67184 29 32 225 257 1 164 100 17 17 289 -1 unnamed_device 25.9 MiB 0.08 2302.41 1071 8684 1857 6075 752 65.6 MiB 0.06 0.00 8.12271 6.84055 -135.697 -6.84055 6.84055 0.38 0.000544243 0.000498762 0.024047 0.0218994 -1 -1 -1 -1 30 2348 30 6.55708e+06 470145 526063. 1820.29 0.61 0.104735 0.093017 21886 126133 -1 2011 13 693 2200 90643 23004 5.99144 5.99144 -125.931 -5.99144 0 0 666494. 2306.21 0.04 0.04 0.11 -1 -1 0.04 0.0201167 0.018364 154 140 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_016.v common 3.41 vpr 65.44 MiB -1 -1 0.27 22068 12 0.34 -1 -1 36568 -1 -1 40 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67008 32 32 301 333 1 214 104 17 17 289 -1 unnamed_device 26.3 MiB 0.12 3731.63 1580 10108 2123 7160 825 65.4 MiB 0.09 0.00 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65.15 MiB -1 -1 0.20 21300 10 0.11 -1 -1 36812 -1 -1 25 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66716 30 32 175 207 1 133 87 17 17 289 -1 unnamed_device 25.7 MiB 0.07 1817.46 875 6615 1509 4517 589 65.2 MiB 0.04 0.00 6.36477 5.54003 -124.848 -5.54003 5.54003 0.38 0.000402815 0.000367205 0.0160888 0.0146908 -1 -1 -1 -1 26 1892 14 6.55708e+06 301375 477104. 1650.88 0.58 0.0662918 0.0587673 21022 109990 -1 1707 15 580 1538 75173 19570 4.68146 4.68146 -118.937 -4.68146 0 0 585099. 2024.56 0.04 0.04 0.10 -1 -1 0.04 0.0163289 0.0146945 100 87 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_020.v common 2.78 vpr 65.43 MiB -1 -1 0.24 21684 13 0.22 -1 -1 36636 -1 -1 33 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66996 31 32 231 263 1 172 96 17 17 289 -1 unnamed_device 25.8 MiB 0.11 2551.58 1219 5133 882 3910 341 65.4 MiB 0.04 0.00 9.56848 7.51354 -158.515 -7.51354 7.51354 0.38 0.000582667 0.00053217 0.0163642 0.0149859 -1 -1 -1 -1 26 2914 16 6.55708e+06 397815 477104. 1650.88 0.63 0.090716 0.0808875 21022 109990 -1 2616 16 912 2770 141635 35169 6.50744 6.50744 -149.665 -6.50744 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0245425 0.0223251 151 140 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_021.v common 3.60 vpr 66.33 MiB -1 -1 0.26 21504 13 0.35 -1 -1 36536 -1 -1 45 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67924 32 32 304 336 1 215 109 17 17 289 -1 unnamed_device 26.4 MiB 0.23 3300.18 1520 9729 2088 6855 786 66.3 MiB 0.08 0.00 11.3205 8.3687 -170.208 -8.3687 8.3687 0.39 0.000742441 0.000671052 0.0323155 0.0292903 -1 -1 -1 -1 26 4144 38 6.55708e+06 542475 477104. 1650.88 1.06 0.157081 0.139915 21022 109990 -1 3324 16 1386 4558 227561 55685 7.37076 7.37076 -163.235 -7.37076 0 0 585099. 2024.56 0.04 0.08 0.10 -1 -1 0.04 0.0325693 0.0297567 222 210 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_022.v common 5.23 vpr 66.06 MiB -1 -1 0.27 22068 13 0.36 -1 -1 36372 -1 -1 46 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67648 32 32 288 320 1 212 110 17 17 289 -1 unnamed_device 26.6 MiB 0.13 3011.13 1549 9841 1986 7037 818 66.1 MiB 0.08 0.00 9.94628 8.09001 -170.835 -8.09001 8.09001 0.38 0.00070156 0.000641612 0.0305594 0.0277335 -1 -1 -1 -1 30 3786 24 6.55708e+06 554530 526063. 1820.29 2.70 0.261917 0.232371 21886 126133 -1 3277 32 1409 5297 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0.23 21492 13 0.35 -1 -1 36588 -1 -1 42 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67760 32 32 287 319 1 209 106 17 17 289 -1 unnamed_device 26.5 MiB 0.12 3188.54 1475 7356 1240 5841 275 66.2 MiB 0.07 0.00 10.9129 8.3667 -168.117 -8.3667 8.3667 0.37 0.000690876 0.000623745 0.0250458 0.0228035 -1 -1 -1 -1 26 3835 20 6.55708e+06 506310 477104. 1650.88 0.89 0.123917 0.110584 21022 109990 -1 3121 17 1250 3890 189718 46969 7.40996 7.40996 -160.049 -7.40996 0 0 585099. 2024.56 0.04 0.08 0.10 -1 -1 0.04 0.0308138 0.0280513 204 193 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_025.v common 2.36 vpr 64.80 MiB -1 -1 0.17 21108 8 0.10 -1 -1 35692 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66356 32 32 154 186 1 117 91 17 17 289 -1 unnamed_device 25.4 MiB 0.05 1504.79 839 6823 1506 4714 603 64.8 MiB 0.04 0.00 4.86674 4.14794 -97.1492 -4.14794 4.14794 0.38 0.000382927 0.000348851 0.0141486 0.0128737 -1 -1 -1 -1 26 1708 16 6.55708e+06 325485 477104. 1650.88 0.55 0.0592247 0.0522262 21022 109990 -1 1465 13 445 1124 51583 13618 3.90514 3.90514 -96.8068 -3.90514 0 0 585099. 2024.56 0.04 0.03 0.10 -1 -1 0.04 0.012911 0.0116769 83 60 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_026.v common 2.97 vpr 65.87 MiB -1 -1 0.23 21684 15 0.29 -1 -1 36440 -1 -1 44 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67448 32 32 254 286 1 184 108 17 17 289 -1 unnamed_device 26.3 MiB 0.11 2794.39 1289 8846 1673 6391 782 65.9 MiB 0.07 0.00 11.4269 8.91249 -179.898 -8.91249 8.91249 0.37 0.000646871 0.000592271 0.0257522 0.0235402 -1 -1 -1 -1 28 3141 22 6.55708e+06 530420 500653. 1732.36 0.71 0.114523 0.102235 21310 115450 -1 2703 19 1085 3420 169095 41588 7.75229 7.75229 -168.555 -7.75229 0 0 612192. 2118.31 0.04 0.07 0.10 -1 -1 0.04 0.0303206 0.0275867 178 160 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_027.v common 3.31 vpr 65.83 MiB -1 -1 0.24 21684 13 0.28 -1 -1 36520 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67412 32 32 260 292 1 185 101 17 17 289 -1 unnamed_device 26.1 MiB 0.12 2553.79 1218 6446 1181 4503 762 65.8 MiB 0.06 0.00 8.41804 7.47895 -148.299 -7.47895 7.47895 0.38 0.000638188 0.000583996 0.0216083 0.0196386 -1 -1 -1 -1 28 3650 32 6.55708e+06 446035 500653. 1732.36 1.06 0.123735 0.110249 21310 115450 -1 2721 15 1115 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67324 31 32 244 276 1 183 99 17 17 289 -1 unnamed_device 26.2 MiB 0.11 2718.21 1278 7623 1628 5411 584 65.7 MiB 0.06 0.00 9.30618 7.4792 -158.92 -7.4792 7.4792 0.38 0.000584899 0.000524572 0.0234356 0.0212873 -1 -1 -1 -1 26 3486 19 6.55708e+06 433980 477104. 1650.88 0.73 0.104666 0.093153 21022 109990 -1 2982 15 1147 3679 189997 47278 6.26704 6.26704 -150.559 -6.26704 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0244164 0.0222856 165 153 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_091.v common 4.98 vpr 66.23 MiB -1 -1 0.27 21876 12 0.38 -1 -1 36680 -1 -1 44 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67820 32 32 300 332 1 217 108 17 17 289 -1 unnamed_device 26.3 MiB 0.13 3275.8 1622 10645 2328 7422 895 66.2 MiB 0.09 0.00 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0.00 10.8384 8.21927 -169.077 -8.21927 8.21927 0.38 0.00098164 0.000873449 0.0436798 0.0395753 -1 -1 -1 -1 30 5210 32 6.55708e+06 650970 526063. 1820.29 1.53 0.196367 0.176012 21886 126133 -1 4272 20 1942 7051 322540 77378 7.23124 7.23124 -159.615 -7.23124 0 0 666494. 2306.21 0.04 0.12 0.11 -1 -1 0.04 0.0472311 0.0431176 289 286 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_097.v common 3.39 vpr 66.04 MiB -1 -1 0.27 21684 14 0.32 -1 -1 36544 -1 -1 41 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67620 31 32 277 309 1 197 104 17 17 289 -1 unnamed_device 26.4 MiB 0.09 3097 1274 12304 3037 7768 1499 66.0 MiB 0.10 0.00 12.2136 8.62006 -170.085 -8.62006 8.62006 0.39 0.000667999 0.000609582 0.0386971 0.0352093 -1 -1 -1 -1 26 3603 32 6.55708e+06 494255 477104. 1650.88 1.02 0.150668 0.134668 21022 109990 -1 2789 17 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0.00 9.47524 7.25311 -136.619 -7.25311 7.25311 0.37 0.000722615 0.000659958 0.0351695 0.0319235 -1 -1 -1 -1 30 2864 16 6.55708e+06 518365 526063. 1820.29 0.68 0.124476 0.111457 21886 126133 -1 2537 18 972 3930 165233 40913 6.35004 6.35004 -128.389 -6.35004 0 0 666494. 2306.21 0.04 0.07 0.11 -1 -1 0.04 0.0313786 0.0285378 207 199 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_102.v common 3.48 vpr 66.27 MiB -1 -1 0.27 21876 15 0.44 -1 -1 36164 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67856 32 32 296 328 1 208 101 17 17 289 -1 unnamed_device 26.7 MiB 0.16 3400.28 1425 8326 1756 5851 719 66.3 MiB 0.08 0.00 12.6428 9.11323 -184.154 -9.11323 9.11323 0.38 0.000767392 0.000700592 0.0305297 0.0277115 -1 -1 -1 -1 26 3950 24 6.55708e+06 446035 477104. 1650.88 0.94 0.13878 0.124211 21022 109990 -1 3244 16 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67180 31 32 225 257 1 161 97 17 17 289 -1 unnamed_device 25.8 MiB 0.08 2415.18 1133 6757 1438 4598 721 65.6 MiB 0.05 0.00 9.26878 7.00946 -143.372 -7.00946 7.00946 0.38 0.0005471 0.000500681 0.0196931 0.0179439 -1 -1 -1 -1 26 2691 23 6.55708e+06 409870 477104. 1650.88 0.61 0.09606 0.0852533 21022 109990 -1 2292 17 845 2615 133353 32686 6.23184 6.23184 -137.649 -6.23184 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0235822 0.021336 145 134 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_111.v common 3.10 vpr 66.12 MiB -1 -1 0.26 21684 12 0.25 -1 -1 35928 -1 -1 41 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67708 32 32 288 320 1 205 105 17 17 289 -1 unnamed_device 26.3 MiB 0.12 3231.02 1460 9244 1928 6414 902 66.1 MiB 0.08 0.00 9.79864 7.07814 -148.913 -7.07814 7.07814 0.39 0.000705393 0.000642853 0.0311824 0.0282802 -1 -1 -1 -1 28 3623 19 6.55708e+06 494255 500653. 1732.36 0.79 0.128821 0.114826 21310 115450 -1 3038 18 1249 4669 234810 56737 6.41878 6.41878 -147.502 -6.41878 0 0 612192. 2118.31 0.04 0.09 0.10 -1 -1 0.04 0.031824 0.0289871 206 194 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_112.v common 3.27 vpr 65.89 MiB -1 -1 0.27 22068 13 0.36 -1 -1 36648 -1 -1 38 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67476 31 32 282 314 1 202 101 17 17 289 -1 unnamed_device 26.3 MiB 0.16 3277.26 1590 6681 1310 4868 503 65.9 MiB 0.06 0.00 10.7471 8.73972 -167.897 -8.73972 8.73972 0.38 0.000782256 0.000701307 0.0255505 0.0232175 -1 -1 -1 -1 28 3932 24 6.55708e+06 458090 500653. 1732.36 0.81 0.127745 0.114014 21310 115450 -1 3256 15 1195 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7.61712 5.81412 -100.01 -5.81412 5.81412 0.39 0.000497414 0.000457093 0.0242048 0.0220861 -1 -1 -1 -1 20 2082 17 6.55708e+06 385760 394039. 1363.46 0.32 0.0451938 0.0408559 19870 87366 -1 1921 20 716 2165 117867 32355 5.29412 5.29412 -99.9076 -5.29412 0 0 477104. 1650.88 0.03 0.05 0.08 -1 -1 0.03 0.0214092 0.0192552 117 110 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_127.v common 3.25 vpr 66.02 MiB -1 -1 0.27 21876 12 0.32 -1 -1 36388 -1 -1 43 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67600 32 32 300 332 1 216 107 17 17 289 -1 unnamed_device 26.3 MiB 0.12 3565.23 1492 7444 1324 5746 374 66.0 MiB 0.07 0.00 10.0075 7.59118 -168.041 -7.59118 7.59118 0.38 0.000741128 0.000664732 0.0261277 0.0238634 -1 -1 -1 -1 26 3908 24 6.55708e+06 518365 477104. 1650.88 0.89 0.131703 0.117775 21022 109990 -1 3205 18 1335 4400 213388 52780 6.7621 6.7621 -161.57 -6.7621 0 0 585099. 2024.56 0.04 0.08 0.10 -1 -1 0.04 0.0337771 0.0307689 214 206 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_128.v common 3.49 vpr 66.21 MiB -1 -1 0.28 22260 13 0.39 -1 -1 36436 -1 -1 40 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67800 31 32 290 322 1 209 103 17 17 289 -1 unnamed_device 26.6 MiB 0.11 3076.85 1400 9020 1816 6496 708 66.2 MiB 0.08 0.00 10.9492 8.22447 -168.698 -8.22447 8.22447 0.38 0.000715181 0.000647818 0.0310834 0.0282483 -1 -1 -1 -1 26 4161 44 6.55708e+06 482200 477104. 1650.88 1.02 0.160804 0.143338 21022 109990 -1 3404 19 1491 5035 261566 64544 7.49096 7.49096 -169.674 -7.49096 0 0 585099. 2024.56 0.04 0.10 0.10 -1 -1 0.04 0.0363177 0.0330715 210 199 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 4.14 vpr 66.19 MiB -1 -1 0.18 21752 1 0.03 -1 -1 33600 -1 -1 36 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67776 32 32 354 285 1 202 100 17 17 289 -1 unnamed_device 26.6 MiB 0.27 2678.6 1173 17500 4985 9702 2813 66.2 MiB 0.15 0.00 6.89032 5.63926 -167.548 -5.63926 5.63926 0.38 0.000539232 0.000495265 0.0435715 0.0399713 -1 -1 -1 -1 28 2978 19 6.64007e+06 452088 500653. 1732.36 1.97 0.200887 0.178051 21970 115934 -1 2332 17 1278 2090 144965 33980 4.59448 4.59448 -151.611 -4.59448 0 0 612192. 2118.31 0.04 0.06 0.10 -1 -1 0.04 0.0235894 0.0213013 152 50 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.75 vpr 66.16 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33684 -1 -1 30 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67744 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 26.5 MiB 0.26 2387 1081 16652 5378 9052 2222 66.2 MiB 0.15 0.00 6.11521 5.03341 -144.954 -5.03341 5.03341 0.39 0.000526367 0.000480763 0.0455696 0.041751 -1 -1 -1 -1 32 2152 20 6.64007e+06 376740 554710. 1919.41 0.55 0.113789 0.10162 22834 132086 -1 1994 21 1416 2247 119514 29996 4.07069 4.07069 -136.61 -4.07069 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0266096 0.0236921 147 63 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 3.22 vpr 65.73 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33932 -1 -1 30 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67304 32 32 299 247 1 188 94 17 17 289 -1 unnamed_device 26.2 MiB 0.22 2525.1 1109 11809 3137 7681 991 65.7 MiB 0.10 0.00 5.74935 4.5927 -120.357 -4.5927 4.5927 0.38 0.000479954 0.000441059 0.0285799 0.0261358 -1 -1 -1 -1 26 2480 20 6.64007e+06 376740 477104. 1650.88 1.18 0.151037 0.132704 21682 110474 -1 2175 20 1256 1776 114196 28100 3.88303 3.88303 -121.873 -3.88303 0 0 585099. 2024.56 0.04 0.05 0.11 -1 -1 0.04 0.0220046 0.0196256 129 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 3.37 vpr 65.77 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33340 -1 -1 31 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67352 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 26.2 MiB 0.06 2219.93 994 10856 2714 7244 898 65.8 MiB 0.09 0.00 5.50467 4.57786 -122.645 -4.57786 4.57786 0.38 0.000475127 0.000434689 0.0270643 0.0247508 -1 -1 -1 -1 30 2064 20 6.64007e+06 389298 526063. 1820.29 1.48 0.183381 0.160711 22546 126617 -1 1772 22 1114 2142 109786 26519 3.48623 3.48623 -112.184 -3.48623 0 0 666494. 2306.21 0.04 0.06 0.11 -1 -1 0.04 0.0241491 0.0216308 132 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.69 vpr 66.06 MiB -1 -1 0.18 21368 1 0.03 -1 -1 33792 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67644 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 26.6 MiB 0.07 2401.18 966 13340 3524 8281 1535 66.1 MiB 0.12 0.00 5.52176 4.52104 -130.33 -4.52104 4.52104 0.38 0.000539918 0.000495835 0.0367855 0.0335214 -1 -1 -1 -1 26 2424 25 6.64007e+06 351624 477104. 1650.88 0.74 0.113068 0.100665 21682 110474 -1 2104 28 1760 3359 198573 52536 3.68263 3.68263 -125.326 -3.68263 0 0 585099. 2024.56 0.04 0.08 0.10 -1 -1 0.04 0.0297169 0.0263662 134 34 -1 -1 -1 -1 + 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GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67308 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 26.2 MiB 0.07 1585.5 643 13324 5629 6929 766 65.7 MiB 0.09 0.00 4.47141 3.85458 -101.906 -3.85458 3.85458 0.38 0.000406956 0.000371976 0.0339778 0.0311288 -1 -1 -1 -1 32 1425 18 6.64007e+06 263718 554710. 1919.41 1.38 0.142441 0.12549 22834 132086 -1 1196 20 798 1400 78700 20019 2.66537 2.66537 -88.621 -2.66537 0 0 701300. 2426.64 0.04 0.04 0.12 -1 -1 0.04 0.0187116 0.0166725 97 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.61 vpr 65.16 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33468 -1 -1 35 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66728 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 25.4 MiB 0.05 2037.06 1027 15848 4746 8906 2196 65.2 MiB 0.12 0.00 4.0843 3.4441 -101.869 -3.4441 3.4441 0.38 0.000434431 0.000395939 0.0344147 0.0313115 -1 -1 -1 -1 26 2300 22 6.64007e+06 439530 477104. 1650.88 0.74 0.108325 0.0955914 21682 110474 -1 2007 20 1077 1995 121729 28059 2.93817 2.93817 -99.1235 -2.93817 0 0 585099. 2024.56 0.04 0.05 0.10 -1 -1 0.04 0.0204536 0.0182704 123 4 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.96 vpr 65.36 MiB -1 -1 0.18 21432 1 0.03 -1 -1 33700 -1 -1 25 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66928 31 32 317 271 1 168 88 17 17 289 -1 unnamed_device 25.8 MiB 0.18 2086 1000 7303 1659 5065 579 65.4 MiB 0.07 0.00 3.99239 3.60222 -119.121 -3.60222 3.60222 0.38 0.000466464 0.000426601 0.019814 0.0181323 -1 -1 -1 -1 30 1810 16 6.64007e+06 313950 526063. 1820.29 1.00 0.132238 0.115972 22546 126617 -1 1623 18 769 1162 66716 15646 2.84343 2.84343 -110.291 -2.84343 0 0 666494. 2306.21 0.04 0.04 0.11 -1 -1 0.04 0.0203925 0.0183185 117 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 3.37 vpr 65.70 MiB -1 -1 0.17 20996 1 0.03 -1 -1 33316 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67272 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 26.1 MiB 0.11 1795.16 757 10163 2134 7279 750 65.7 MiB 0.08 0.00 4.55761 3.85841 -122.256 -3.85841 3.85841 0.37 0.000495117 0.000439503 0.0286994 0.0262884 -1 -1 -1 -1 30 1936 23 6.64007e+06 238602 526063. 1820.29 1.47 0.156664 0.137332 22546 126617 -1 1528 20 1112 1832 105676 25969 2.85797 2.85797 -108.107 -2.85797 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.0216376 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release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67388 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 26.3 MiB 0.23 2346.38 829 7575 1641 5387 547 65.8 MiB 0.06 0.00 4.97492 3.71121 -113.756 -3.71121 3.71121 0.38 0.000441789 0.000403293 0.0194246 0.0177554 -1 -1 -1 -1 32 1906 18 6.64007e+06 288834 554710. 1919.41 1.45 0.15357 0.134049 22834 132086 -1 1612 20 905 1296 80962 20806 2.82797 2.82797 -104.721 -2.82797 0 0 701300. 2426.64 0.05 0.04 0.12 -1 -1 0.05 0.0200726 0.0178866 110 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 4.74 vpr 66.17 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33472 -1 -1 29 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67756 32 32 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-1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67480 32 32 338 269 1 196 92 17 17 289 -1 unnamed_device 26.4 MiB 0.21 2606.61 1193 12098 3245 7739 1114 65.9 MiB 0.11 0.00 5.47847 4.51687 -144.222 -4.51687 4.51687 0.38 0.000513298 0.000469916 0.0325709 0.0298359 -1 -1 -1 -1 32 2427 21 6.64007e+06 351624 554710. 1919.41 0.53 0.0992607 0.088158 22834 132086 -1 2069 21 1255 1738 110914 28282 3.39903 3.39903 -128.891 -3.39903 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0252593 0.022688 144 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.61 vpr 65.61 MiB -1 -1 0.17 21560 1 0.03 -1 -1 33436 -1 -1 34 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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1780 20 837 1205 72115 18192 3.60043 3.60043 -131.773 -3.60043 0 0 701300. 2426.64 0.04 0.05 0.12 -1 -1 0.04 0.0219387 0.0196082 127 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 3.51 vpr 66.00 MiB -1 -1 0.17 21292 1 0.03 -1 -1 33448 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67580 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 26.4 MiB 0.06 2331.78 1142 17961 5292 10794 1875 66.0 MiB 0.15 0.00 5.44296 4.24096 -135.283 -4.24096 4.24096 0.38 0.000533821 0.000490888 0.0454253 0.0415823 -1 -1 -1 -1 32 2254 22 6.64007e+06 464646 554710. 1919.41 1.53 0.213712 0.188252 22834 132086 -1 2002 18 1106 1845 137037 29980 3.47343 3.47343 -127.492 -3.47343 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0227489 0.0204201 140 34 -1 -1 -1 -1 + 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GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66852 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 26.2 MiB 0.07 1349.42 633 10868 3050 6437 1381 65.3 MiB 0.06 0.00 2.81093 2.39133 -70.7944 -2.39133 2.39133 0.38 0.000312303 0.000284694 0.0222114 0.0202594 -1 -1 -1 -1 26 1233 20 6.64007e+06 251160 477104. 1650.88 0.46 0.0629021 0.0556473 21682 110474 -1 1121 19 523 781 49077 12394 1.95411 1.95411 -71.0211 -1.95411 0 0 585099. 2024.56 0.04 0.03 0.10 -1 -1 0.04 0.0134941 0.0119953 81 30 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.46 vpr 65.88 MiB -1 -1 0.16 21368 1 0.03 -1 -1 33736 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67456 32 32 285 227 1 165 89 17 17 289 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7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67476 32 32 338 277 1 179 98 17 17 289 -1 unnamed_device 26.3 MiB 0.12 2285.18 1130 17873 5176 10397 2300 65.9 MiB 0.15 0.00 5.78707 4.8746 -136.214 -4.8746 4.8746 0.38 0.000516451 0.00047285 0.0436164 0.0398971 -1 -1 -1 -1 26 2505 18 6.64007e+06 426972 477104. 1650.88 0.81 0.111163 0.0993834 21682 110474 -1 2195 18 1146 1976 119096 28686 3.72963 3.72963 -128.609 -3.72963 0 0 585099. 2024.56 0.04 0.05 0.10 -1 -1 0.04 0.0229712 0.0207303 132 50 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 3.28 vpr 65.81 MiB -1 -1 0.17 21016 1 0.03 -1 -1 33624 -1 -1 21 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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0.07 0.00 3.60179 3.24119 -95.5452 -3.24119 3.24119 0.39 0.000431019 0.000395128 0.0255757 0.0233075 -1 -1 -1 -1 30 1518 17 6.64007e+06 301392 526063. 1820.29 0.49 0.0773302 0.0685628 22546 126617 -1 1212 20 661 1089 52330 13795 2.56257 2.56257 -89.8228 -2.56257 0 0 666494. 2306.21 0.04 0.04 0.11 -1 -1 0.04 0.0199032 0.0178341 100 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.43 vpr 65.72 MiB -1 -1 0.18 21368 1 0.04 -1 -1 33492 -1 -1 24 28 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67300 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 26.1 MiB 0.06 1853.45 868 11247 3492 5966 1789 65.7 MiB 0.08 0.00 4.1543 3.41886 -98.6687 -3.41886 3.41886 0.38 0.000408423 0.000373302 0.0276347 0.025309 -1 -1 -1 -1 32 1674 22 6.64007e+06 301392 554710. 1919.41 0.53 0.0820544 0.0727816 22834 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13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67576 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 26.2 MiB 0.13 2169.43 761 17273 5436 9708 2129 66.0 MiB 0.13 0.00 3.9379 3.3369 -100.749 -3.3369 3.3369 0.39 0.00043799 0.000398871 0.0409643 0.0372968 -1 -1 -1 -1 28 1765 15 6.64007e+06 389298 500653. 1732.36 1.32 0.145535 0.128265 21970 115934 -1 1514 18 925 1433 83189 21456 2.34097 2.34097 -90.2559 -2.34097 0 0 612192. 2118.31 0.04 0.05 0.10 -1 -1 0.04 0.0196898 0.0176144 112 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 2.55 vpr 66.26 MiB -1 -1 0.18 21264 1 0.03 -1 -1 33648 -1 -1 42 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67848 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 26.8 MiB 0.11 2284.34 1278 15106 3535 9651 1920 66.3 MiB 0.13 0.00 4.83776 4.35696 -123.678 -4.35696 4.35696 0.38 0.000561986 0.00051211 0.0369088 0.0337955 -1 -1 -1 -1 28 2699 20 6.64007e+06 527436 500653. 1732.36 0.55 0.109256 0.0974153 21970 115934 -1 2377 19 1185 2125 127687 30322 3.67363 3.67363 -120.199 -3.67363 0 0 612192. 2118.31 0.04 0.06 0.11 -1 -1 0.04 0.0253097 0.0227727 158 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 3.21 vpr 66.13 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33788 -1 -1 41 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67716 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 26.7 MiB 0.11 2421.23 1085 11220 2865 7703 652 66.1 MiB 0.11 0.00 4.51361 3.89275 -130.437 -3.89275 3.89275 0.40 0.000649623 0.00059623 0.0296661 0.0269941 -1 -1 -1 -1 26 2477 21 6.64007e+06 514878 477104. 1650.88 1.24 0.170575 0.149985 21682 110474 -1 1978 18 1418 2273 120507 29786 2.90297 2.90297 -116.877 -2.90297 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0240678 0.0216345 150 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.56 vpr 65.20 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33840 -1 -1 23 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66764 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 26.1 MiB 0.25 2417.74 918 9536 2320 6465 751 65.2 MiB 0.08 0.00 5.18307 4.35884 -128.706 -4.35884 4.35884 0.39 0.000520339 0.000481988 0.0254045 0.0232737 -1 -1 -1 -1 32 1849 20 6.64007e+06 288834 554710. 1919.41 0.51 0.0818004 0.0726783 22834 132086 -1 1689 20 806 1172 74453 17829 3.22283 3.22283 -115.365 -3.22283 0 0 701300. 2426.64 0.05 0.04 0.12 -1 -1 0.05 0.0206443 0.0183665 114 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 3.19 vpr 66.18 MiB -1 -1 0.19 21416 1 0.03 -1 -1 33828 -1 -1 29 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67772 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 26.6 MiB 0.10 2217.26 1086 16238 5424 8490 2324 66.2 MiB 0.14 0.00 4.8385 4.05106 -121.379 -4.05106 4.05106 0.38 0.00054402 0.000498804 0.0463865 0.0425611 -1 -1 -1 -1 30 2268 20 6.64007e+06 364182 526063. 1820.29 1.18 0.184242 0.162762 22546 126617 -1 2022 16 1112 1909 103875 25224 3.19357 3.19357 -116.973 -3.19357 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.0218996 0.0197466 145 61 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 4.06 vpr 66.18 MiB -1 -1 0.19 21596 1 0.03 -1 -1 33632 -1 -1 36 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67772 31 32 377 302 1 233 99 17 17 289 -1 unnamed_device 26.7 MiB 0.41 2995 1368 17655 5130 9594 2931 66.2 MiB 0.16 0.00 7.81519 5.77178 -175.201 -5.77178 5.77178 0.38 0.000568067 0.000520008 0.0462518 0.0422877 -1 -1 -1 -1 32 2890 22 6.64007e+06 452088 554710. 1919.41 1.69 0.228819 0.201762 22834 132086 -1 2590 20 1607 2386 140848 33685 4.83334 4.83334 -162.241 -4.83334 0 0 701300. 2426.64 0.05 0.06 0.12 -1 -1 0.05 0.0257579 0.0231691 178 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.82 vpr 66.28 MiB -1 -1 0.19 21752 1 0.03 -1 -1 33656 -1 -1 32 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67868 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 26.8 MiB 0.32 2722.35 1178 14783 4025 8612 2146 66.3 MiB 0.14 0.00 6.456 5.17379 -158.704 -5.17379 5.17379 0.39 0.000577998 0.000530745 0.0433822 0.0397451 -1 -1 -1 -1 32 2424 20 6.64007e+06 401856 554710. 1919.41 0.56 0.115763 0.103558 22834 132086 -1 2170 22 1359 2198 117919 30122 4.31208 4.31208 -146.74 -4.31208 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0280542 0.0251326 167 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 3.19 vpr 65.97 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33984 -1 -1 37 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67556 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 26.3 MiB 0.14 2150.25 1132 12396 2916 8409 1071 66.0 MiB 0.11 0.00 5.33427 4.65224 -135.504 -4.65224 4.65224 0.38 0.000560763 0.000517109 0.0313073 0.0287077 -1 -1 -1 -1 28 2484 23 6.64007e+06 464646 500653. 1732.36 1.21 0.169107 0.149236 21970 115934 -1 2211 19 1272 2115 119167 29077 3.43803 3.43803 -124.249 -3.43803 0 0 612192. 2118.31 0.04 0.06 0.10 -1 -1 0.04 0.0236787 0.0212404 140 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 3.31 vpr 65.80 MiB -1 -1 0.17 21560 1 0.03 -1 -1 33360 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67384 32 32 291 242 1 179 91 17 17 289 -1 unnamed_device 26.2 MiB 0.19 2447.23 1107 11923 3150 7642 1131 65.8 MiB 0.10 0.00 5.56996 4.42433 -118.362 -4.42433 4.42433 0.38 0.000479222 0.000439917 0.0298701 0.0273339 -1 -1 -1 -1 28 2371 17 6.64007e+06 339066 500653. 1732.36 1.31 0.166846 0.146558 21970 115934 -1 2048 18 1004 1428 83027 20803 3.98423 3.98423 -120.513 -3.98423 0 0 612192. 2118.31 0.04 0.05 0.10 -1 -1 0.04 0.0212056 0.0190808 124 27 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.58 vpr 66.48 MiB -1 -1 0.20 21648 1 0.03 -1 -1 33872 -1 -1 43 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68080 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 27.1 MiB 0.16 3089.35 1148 12504 3216 8619 669 66.5 MiB 0.13 0.00 6.38072 5.15629 -161.009 -5.15629 5.15629 0.38 0.0006407 0.000588581 0.0363732 0.0332222 -1 -1 -1 -1 30 2652 20 6.64007e+06 539994 526063. 1820.29 1.49 0.204335 0.180169 22546 126617 -1 2161 20 1395 2288 113197 28520 3.87729 3.87729 -140.565 -3.87729 0 0 666494. 2306.21 0.04 0.06 0.11 -1 -1 0.04 0.0302942 0.0272267 176 87 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.36 vpr 65.52 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33712 -1 -1 23 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67092 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 25.9 MiB 0.07 2009.57 848 14261 3741 9106 1414 65.5 MiB 0.10 0.00 4.5869 3.7565 -102.466 -3.7565 3.7565 0.38 0.000418354 0.000382969 0.0340201 0.0311137 -1 -1 -1 -1 32 1631 18 6.64007e+06 288834 554710. 1919.41 0.50 0.0868115 0.0772638 22834 132086 -1 1456 18 746 1303 80456 19380 2.76057 2.76057 -96.8843 -2.76057 0 0 701300. 2426.64 0.05 0.04 0.12 -1 -1 0.05 0.0173126 0.0154162 104 28 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 3.66 vpr 65.81 MiB -1 -1 0.18 21368 1 0.03 -1 -1 33708 -1 -1 34 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67392 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 26.4 MiB 0.26 2709.85 1110 11641 3305 7146 1190 65.8 MiB 0.11 0.00 6.25113 5.0663 -146.843 -5.0663 5.0663 0.40 0.000511984 0.000470182 0.0306182 0.0279584 -1 -1 -1 -1 32 2608 20 6.64007e+06 426972 554710. 1919.41 1.51 0.167297 0.147303 22834 132086 -1 2221 21 1249 1916 111047 27258 4.08688 4.08688 -130.721 -4.08688 0 0 701300. 2426.64 0.05 0.06 0.12 -1 -1 0.05 0.0251561 0.0225651 149 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 3.56 vpr 66.14 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33640 -1 -1 38 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67728 32 32 349 284 1 182 102 17 17 289 -1 unnamed_device 26.6 MiB 0.10 2675.2 1084 15810 4288 9334 2188 66.1 MiB 0.13 0.00 4.99666 4.09572 -115.96 -4.09572 4.09572 0.39 0.000518783 0.000475966 0.0376403 0.0344348 -1 -1 -1 -1 30 2142 18 6.64007e+06 477204 526063. 1820.29 1.59 0.223396 0.196047 22546 126617 -1 1784 19 864 1612 90283 21651 3.04917 3.04917 -108.273 -3.04917 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.0230834 0.0207608 136 53 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 2.42 vpr 65.70 MiB -1 -1 0.16 21368 1 0.03 -1 -1 33336 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67276 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 26.2 MiB 0.06 1813.35 1148 12127 3848 6621 1658 65.7 MiB 0.11 0.00 4.79356 4.19256 -126.138 -4.19256 4.19256 0.38 0.000463819 0.000423948 0.0302802 0.0277605 -1 -1 -1 -1 32 2151 21 6.64007e+06 339066 554710. 1919.41 0.54 0.0926736 0.0824875 22834 132086 -1 1914 22 904 1746 107845 24237 3.45223 3.45223 -118.392 -3.45223 0 0 701300. 2426.64 0.04 0.05 0.12 -1 -1 0.04 0.023873 0.0213621 127 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 3.65 vpr 65.93 MiB -1 -1 0.18 21652 1 0.03 -1 -1 33624 -1 -1 31 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67508 32 32 353 287 1 198 95 17 17 289 -1 unnamed_device 26.6 MiB 0.26 2439.97 1164 15863 4914 7581 3368 65.9 MiB 0.13 0.00 5.52647 4.92314 -142.963 -4.92314 4.92314 0.38 0.00052643 0.000480848 0.0435343 0.0398666 -1 -1 -1 -1 30 2453 23 6.64007e+06 389298 526063. 1820.29 1.50 0.189865 0.167163 22546 126617 -1 2055 18 1169 1594 96158 23870 3.70343 3.70343 -125.494 -3.70343 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.023554 0.0211524 142 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 3.81 vpr 66.15 MiB -1 -1 0.18 21492 1 0.03 -1 -1 33644 -1 -1 39 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67740 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 26.8 MiB 0.13 2461.47 1059 17937 5599 9322 3016 66.2 MiB 0.13 0.00 4.3595 3.8177 -119.543 -3.8177 3.8177 0.38 0.000553222 0.00050479 0.0437428 0.0398201 -1 -1 -1 -1 30 2399 24 6.64007e+06 489762 526063. 1820.29 1.78 0.191043 0.168056 22546 126617 -1 1946 19 1076 1873 116299 28160 3.03417 3.03417 -114.514 -3.03417 0 0 666494. 2306.21 0.04 0.06 0.11 -1 -1 0.04 0.0238454 0.0213975 139 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.68 vpr 66.18 MiB -1 -1 0.19 21752 1 0.03 -1 -1 33848 -1 -1 40 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67772 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 26.4 MiB 0.12 2726.91 1157 17916 4962 10607 2347 66.2 MiB 0.16 0.00 5.01327 4.29207 -131.751 -4.29207 4.29207 0.39 0.000560514 0.000514493 0.0453403 0.0414516 -1 -1 -1 -1 28 2665 23 6.64007e+06 502320 500653. 1732.36 0.62 0.12244 0.109152 21970 115934 -1 2278 23 1584 2663 174510 39479 3.04317 3.04317 -119.013 -3.04317 0 0 612192. 2118.31 0.04 0.07 0.11 -1 -1 0.04 0.0304194 0.0272639 149 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 2.63 vpr 65.71 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33432 -1 -1 36 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67284 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 26.2 MiB 0.06 1947.73 873 16108 4476 7806 3826 65.7 MiB 0.11 0.00 4.78256 4.34576 -121.313 -4.34576 4.34576 0.38 0.000468408 0.000427592 0.0363044 0.0331658 -1 -1 -1 -1 30 2090 25 6.64007e+06 452088 526063. 1820.29 0.75 0.105558 0.0939442 22546 126617 -1 1553 21 1051 1873 98927 27703 4.05503 4.05503 -119.589 -4.05503 0 0 666494. 2306.21 0.04 0.05 0.12 -1 -1 0.04 0.0224909 0.0201118 127 24 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.63 vpr 66.06 MiB -1 -1 0.17 21368 1 0.03 -1 -1 34012 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67648 32 32 319 257 1 198 92 17 17 289 -1 unnamed_device 26.6 MiB 0.23 2350.97 1147 14789 4141 8926 1722 66.1 MiB 0.13 0.00 6.11266 5.10621 -140.75 -5.10621 5.10621 0.38 0.000514818 0.000471698 0.0380407 0.0346748 -1 -1 -1 -1 32 2435 18 6.64007e+06 351624 554710. 1919.41 0.53 0.100546 0.0895444 22834 132086 -1 2057 20 1026 1498 91149 21478 3.84603 3.84603 -130.313 -3.84603 0 0 701300. 2426.64 0.04 0.05 0.12 -1 -1 0.04 0.0221485 0.0198325 137 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 4.17 vpr 66.06 MiB -1 -1 0.19 21752 1 0.03 -1 -1 33636 -1 -1 30 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67644 31 32 373 299 1 205 93 17 17 289 -1 unnamed_device 26.6 MiB 0.25 2853.45 1234 11643 3377 7498 768 66.1 MiB 0.12 0.00 6.45652 5.28887 -154.854 -5.28887 5.28887 0.38 0.000564225 0.000517568 0.0346837 0.0317608 -1 -1 -1 -1 26 3360 25 6.64007e+06 376740 477104. 1650.88 2.06 0.185293 0.163465 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13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67632 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 26.6 MiB 0.22 2329 1086 9679 2251 6735 693 66.0 MiB 0.09 0.00 5.08216 4.06153 -138.604 -4.06153 4.06153 0.38 0.000511014 0.000468196 0.0280048 0.0256383 -1 -1 -1 -1 32 2190 17 6.64007e+06 339066 554710. 1919.41 1.50 0.183212 0.160572 22834 132086 -1 2011 23 1448 2157 134764 31205 3.38103 3.38103 -128.746 -3.38103 0 0 701300. 2426.64 0.05 0.06 0.12 -1 -1 0.05 0.0253296 0.0225211 133 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.80 vpr 66.38 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33660 -1 -1 34 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67968 32 32 387 293 1 234 98 17 17 289 -1 unnamed_device 26.9 MiB 0.23 2841.47 1463 16748 4321 10445 1982 66.4 MiB 0.17 0.00 6.57692 5.46849 -162 -5.46849 5.46849 0.39 0.000586525 0.000538155 0.0477353 0.0437931 -1 -1 -1 -1 32 2947 24 6.64007e+06 426972 554710. 1919.41 0.59 0.1254 0.112112 22834 132086 -1 2701 22 1794 2822 176471 41227 4.50948 4.50948 -153.025 -4.50948 0 0 701300. 2426.64 0.05 0.07 0.12 -1 -1 0.05 0.0296503 0.0266485 174 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 3.20 vpr 66.22 MiB -1 -1 0.18 21752 1 0.03 -1 -1 33652 -1 -1 38 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67808 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 26.5 MiB 0.10 2567.03 943 10098 2147 7548 403 66.2 MiB 0.09 0.00 5.11912 4.24206 -129.354 -4.24206 4.24206 0.40 0.000579354 0.000528449 0.0249281 0.0227634 -1 -1 -1 -1 28 2286 24 6.64007e+06 477204 500653. 1732.36 1.26 0.16579 0.145757 21970 115934 -1 1946 20 1194 1844 101233 26218 3.06117 3.06117 -118.568 -3.06117 0 0 612192. 2118.31 0.04 0.05 0.10 -1 -1 0.04 0.024126 0.0214858 141 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.36 vpr 65.88 MiB -1 -1 0.17 21264 1 0.03 -1 -1 34044 -1 -1 33 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67460 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 26.3 MiB 0.05 2182.92 743 10679 2942 6832 905 65.9 MiB 0.09 0.00 4.2965 3.52427 -104.21 -3.52427 3.52427 0.37 0.000466158 0.000428071 0.026079 0.0238991 -1 -1 -1 -1 32 1599 16 6.64007e+06 414414 554710. 1919.41 0.52 0.0857108 0.0759746 22834 132086 -1 1397 17 644 1197 65700 16378 2.71257 2.71257 -96.443 -2.71257 0 0 701300. 2426.64 0.04 0.04 0.12 -1 -1 0.04 0.0188466 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release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67688 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 26.6 MiB 0.09 2019.46 1053 15334 4673 8141 2520 66.1 MiB 0.11 0.00 5.22107 4.57626 -136.603 -4.57626 4.57626 0.38 0.000564059 0.000508246 0.0370642 0.0336671 -1 -1 -1 -1 32 2211 20 6.64007e+06 477204 554710. 1919.41 1.57 0.197248 0.173229 22834 132086 -1 1913 21 1125 1862 123756 28379 3.53723 3.53723 -127.283 -3.53723 0 0 701300. 2426.64 0.06 0.06 0.12 -1 -1 0.06 0.0240052 0.0213983 136 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.27 vpr 65.20 MiB -1 -1 0.17 21176 1 0.03 -1 -1 33392 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66764 32 32 231 199 1 140 91 17 17 289 -1 unnamed_device 26.0 MiB 0.05 1906.73 764 9067 2085 6178 804 65.2 MiB 0.07 0.00 4.2445 3.5653 -97.5026 -3.5653 3.5653 0.38 0.000399752 0.000358643 0.0193415 0.0176853 -1 -1 -1 -1 26 1747 20 6.64007e+06 339066 477104. 1650.88 0.50 0.0709156 0.0626474 21682 110474 -1 1553 18 736 1243 69356 18200 3.03517 3.03517 -99.0581 -3.03517 0 0 585099. 2024.56 0.04 0.04 0.10 -1 -1 0.04 0.01633 0.0145318 103 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 3.56 vpr 66.19 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33680 -1 -1 40 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67776 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 26.8 MiB 0.09 2540.08 1200 14256 3689 9153 1414 66.2 MiB 0.12 0.00 6.69892 5.63429 -139.306 -5.63429 5.63429 0.38 0.000549317 0.000503417 0.0344161 0.0314184 -1 -1 -1 -1 26 2816 19 6.64007e+06 502320 477104. 1650.88 1.63 0.170463 0.150228 21682 110474 -1 2379 18 1072 2025 124918 29244 4.66048 4.66048 -134.207 -4.66048 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.02282 0.0205198 147 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.34 vpr 65.46 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33684 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67028 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 25.8 MiB 0.05 2164.88 893 10263 2683 6663 917 65.5 MiB 0.08 0.00 4.3277 3.5273 -108.396 -3.5273 3.5273 0.38 0.000408873 0.000372579 0.0243986 0.0221942 -1 -1 -1 -1 32 1749 18 6.64007e+06 288834 554710. 1919.41 0.50 0.0766277 0.0678269 22834 132086 -1 1533 20 784 1238 71387 17120 2.77177 2.77177 -103.397 -2.77177 0 0 701300. 2426.64 0.04 0.04 0.12 -1 -1 0.04 0.0185406 0.0165421 107 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 4.10 vpr 65.83 MiB -1 -1 0.17 21560 1 0.03 -1 -1 33660 -1 -1 38 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67408 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 26.1 MiB 0.08 2117.27 741 17964 5926 8961 3077 65.8 MiB 0.12 0.00 5.13641 4.08278 -108.305 -4.08278 4.08278 0.39 0.000454726 0.000415497 0.0366192 0.0333417 -1 -1 -1 -1 26 2016 22 6.64007e+06 477204 477104. 1650.88 2.17 0.154653 0.135905 21682 110474 -1 1660 23 1058 1963 129089 32143 3.06217 3.06217 -104.928 -3.06217 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0236552 0.0211943 110 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 3.34 vpr 66.08 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33488 -1 -1 30 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67664 29 32 355 287 1 198 91 17 17 289 -1 unnamed_device 26.5 MiB 0.23 2797.18 1152 11923 3359 7574 990 66.1 MiB 0.11 0.00 5.54667 4.63446 -132.815 -4.63446 4.63446 0.38 0.000604103 0.000555168 0.0348703 0.0319254 -1 -1 -1 -1 30 2275 20 6.64007e+06 376740 526063. 1820.29 1.25 0.166564 0.147006 22546 126617 -1 1928 21 1152 1744 93032 22364 3.25483 3.25483 -115.175 -3.25483 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.0246058 0.0219442 146 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 2.48 vpr 66.11 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33464 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67692 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 26.6 MiB 0.10 1949.16 947 7639 1677 5525 437 66.1 MiB 0.07 0.00 5.24456 4.53352 -139.004 -4.53352 4.53352 0.38 0.00056128 0.000514708 0.02285 0.0209067 -1 -1 -1 -1 32 2009 19 6.64007e+06 339066 554710. 1919.41 0.55 0.0896462 0.0795513 22834 132086 -1 1774 21 1241 1905 118138 28466 3.74782 3.74782 -129.815 -3.74782 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0253181 0.0226695 135 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.56 vpr 65.91 MiB -1 -1 0.18 21736 1 0.03 -1 -1 33904 -1 -1 34 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67488 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 26.4 MiB 0.13 2440.84 992 12473 3251 7895 1327 65.9 MiB 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13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67188 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 26.0 MiB 0.07 1932.95 905 16515 4803 9135 2577 65.6 MiB 0.12 0.00 5.16736 4.19576 -104.869 -4.19576 4.19576 0.41 0.00046413 0.000425243 0.0361769 0.0330838 -1 -1 -1 -1 26 2022 22 6.64007e+06 489762 477104. 1650.88 0.72 0.0990764 0.0882036 21682 110474 -1 1822 20 1097 2083 117673 28230 3.55243 3.55243 -105.89 -3.55243 0 0 585099. 2024.56 0.04 0.05 0.10 -1 -1 0.04 0.0199651 0.017814 122 27 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 2.54 vpr 65.82 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33780 -1 -1 21 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67400 30 32 317 269 1 152 83 17 17 289 -1 unnamed_device 26.2 MiB 0.11 2031.45 913 13403 4177 7412 1814 65.8 MiB 0.11 0.00 4.60481 3.88361 -116.394 -3.88361 3.88361 0.38 0.000467766 0.000427842 0.0382942 0.0351348 -1 -1 -1 -1 32 1838 19 6.64007e+06 263718 554710. 1919.41 0.54 0.0986744 0.0880107 22834 132086 -1 1769 18 1056 1797 115755 26567 2.93877 2.93877 -111.688 -2.93877 0 0 701300. 2426.64 0.05 0.05 0.12 -1 -1 0.05 0.0206583 0.0185106 115 63 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 2.57 vpr 65.98 MiB -1 -1 0.18 21504 1 0.03 -1 -1 33848 -1 -1 26 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67564 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 26.2 MiB 0.22 2267 1030 7728 1690 5451 587 66.0 MiB 0.08 0.00 4.51839 3.99553 -131.807 -3.99553 3.99553 0.38 0.000555192 0.000510296 0.0249521 0.0228555 -1 -1 -1 -1 28 2378 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7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67820 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 26.8 MiB 0.12 2679.98 1105 12321 3286 8354 681 66.2 MiB 0.11 0.00 5.58347 4.55563 -142.995 -4.55563 4.55563 0.38 0.000575424 0.000528449 0.0333194 0.0302703 -1 -1 -1 -1 28 2766 22 6.64007e+06 464646 500653. 1732.36 1.45 0.199397 0.175777 21970 115934 -1 2266 18 1406 2519 142299 35870 3.66263 3.66263 -136.958 -3.66263 0 0 612192. 2118.31 0.04 0.06 0.11 -1 -1 0.04 0.0250169 0.0225812 143 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.80 vpr 66.15 MiB -1 -1 0.18 21752 1 0.03 -1 -1 33852 -1 -1 43 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67736 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 26.4 MiB 0.11 2914.32 1117 18323 4981 10869 2473 66.1 MiB 0.16 0.00 5.86707 4.53303 -140.795 -4.53303 4.53303 0.38 0.000588984 0.000539545 0.0443862 0.040481 -1 -1 -1 -1 30 2465 20 6.64007e+06 539994 526063. 1820.29 1.76 0.229016 0.201722 22546 126617 -1 2042 21 1044 2088 127275 28725 3.33283 3.33283 -126.102 -3.33283 0 0 666494. 2306.21 0.04 0.07 0.11 -1 -1 0.04 0.0287099 0.0257112 147 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 3.43 vpr 65.82 MiB -1 -1 0.17 21176 1 0.03 -1 -1 33524 -1 -1 21 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67396 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 26.0 MiB 0.09 1992.43 801 11963 3849 6218 1896 65.8 MiB 0.09 0.00 4.80601 3.86158 -111.576 -3.86158 3.86158 0.40 0.00044105 0.000404668 0.0309884 0.0283896 -1 -1 -1 -1 26 2108 38 6.64007e+06 263718 477104. 1650.88 1.55 0.151719 0.133349 21682 110474 -1 1662 21 1154 2033 119522 29944 2.85277 2.85277 -105.156 -2.85277 0 0 585099. 2024.56 0.04 0.05 0.10 -1 -1 0.04 0.0214637 0.0191245 109 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 3.58 vpr 66.04 MiB -1 -1 0.19 21560 1 0.03 -1 -1 34028 -1 -1 27 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67620 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 26.6 MiB 0.12 2577.04 1104 15533 4527 9503 1503 66.0 MiB 0.14 0.00 5.94207 4.83961 -141.093 -4.83961 4.83961 0.38 0.000551154 0.000506458 0.0461981 0.0423479 -1 -1 -1 -1 32 2230 21 6.64007e+06 339066 554710. 1919.41 1.54 0.223369 0.196662 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VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67752 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 26.6 MiB 0.26 2377.18 893 16340 5207 7995 3138 66.2 MiB 0.13 0.00 5.27727 4.43587 -128.689 -4.43587 4.43587 0.38 0.000549723 0.000502149 0.0410381 0.0374745 -1 -1 -1 -1 32 2111 24 6.64007e+06 477204 554710. 1919.41 0.60 0.114088 0.101432 22834 132086 -1 1719 22 1260 2205 124944 30890 2.99843 2.99843 -109.697 -2.99843 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0265773 0.0236905 144 83 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 4.17 vpr 66.04 MiB -1 -1 0.18 21752 1 0.03 -1 -1 33400 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67624 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 26.6 MiB 0.12 2700.81 904 8603 1832 6034 737 66.0 MiB 0.08 0.00 6.07747 5.15021 -141.526 -5.15021 5.15021 0.38 0.000532971 0.000487793 0.0258791 0.0237234 -1 -1 -1 -1 30 2549 27 6.64007e+06 313950 526063. 1820.29 2.23 0.171192 0.150595 22546 126617 -1 1841 20 1155 2142 97587 26909 3.99103 3.99103 -138.944 -3.99103 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.02503 0.0224673 141 57 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 2.60 vpr 66.21 MiB -1 -1 0.20 21560 1 0.03 -1 -1 33632 -1 -1 38 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67804 29 32 378 310 1 177 99 17 17 289 -1 unnamed_device 26.6 MiB 0.11 2434.92 966 18567 6107 9865 2595 66.2 MiB 0.15 0.00 5.08141 4.25424 -118.22 -4.25424 4.25424 0.39 0.000551702 0.000505516 0.0480057 0.0437338 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13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67556 32 32 310 266 1 175 90 17 17 289 -1 unnamed_device 26.4 MiB 0.20 2147 974 14964 5514 7515 1935 66.0 MiB 0.12 0.00 5.44076 4.23876 -126.853 -4.23876 4.23876 0.39 0.000484948 0.000426849 0.0392389 0.0358757 -1 -1 -1 -1 28 2111 21 6.64007e+06 326508 500653. 1732.36 1.58 0.187092 0.165 21970 115934 -1 1792 19 1066 1470 110496 28188 3.08263 3.08263 -114.788 -3.08263 0 0 612192. 2118.31 0.04 0.05 0.10 -1 -1 0.04 0.0217874 0.0194805 123 58 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 2.77 vpr 65.86 MiB -1 -1 0.18 21368 1 0.03 -1 -1 33600 -1 -1 43 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67444 31 32 326 261 1 177 106 17 17 289 -1 unnamed_device 26.3 MiB 0.08 2343.92 977 18356 5608 9832 2916 65.9 MiB 0.14 0.00 5.80407 4.55958 -125.379 -4.55958 4.55958 0.39 0.000494438 0.000450873 0.0401815 0.0365823 -1 -1 -1 -1 28 2675 24 6.64007e+06 539994 500653. 1732.36 0.78 0.110754 0.0986358 21970 115934 -1 2199 23 1517 2932 238494 56925 3.73163 3.73163 -125.444 -3.73163 0 0 612192. 2118.31 0.04 0.08 0.11 -1 -1 0.04 0.026098 0.0232689 138 33 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 2.49 vpr 65.71 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33688 -1 -1 26 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67284 29 32 262 224 1 168 87 17 17 289 -1 unnamed_device 26.0 MiB 0.24 1919.9 838 6615 1497 4743 375 65.7 MiB 0.06 0.00 4.83596 4.01173 -107.268 -4.01173 4.01173 0.38 0.00044819 0.000413758 0.0166412 0.0152601 -1 -1 -1 -1 26 1952 15 6.64007e+06 326508 477104. 1650.88 0.53 0.0679215 0.0600754 21682 110474 -1 1680 18 868 1119 70455 16888 3.42342 3.42342 -104.585 -3.42342 0 0 585099. 2024.56 0.04 0.04 0.10 -1 -1 0.04 0.0178161 0.0159036 116 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.92 vpr 65.78 MiB -1 -1 0.16 21368 1 0.03 -1 -1 33408 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67356 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 26.2 MiB 0.11 1709.72 933 8363 1858 5897 608 65.8 MiB 0.07 0.00 4.24201 3.9428 -120.496 -3.9428 3.9428 0.40 0.000438205 0.000401765 0.0231223 0.021218 -1 -1 -1 -1 28 1911 20 6.64007e+06 238602 500653. 1732.36 1.03 0.134966 0.118556 21970 115934 -1 1675 19 1132 1950 117423 28196 2.75457 2.75457 -106.82 -2.75457 0 0 612192. 2118.31 0.04 0.05 0.10 -1 -1 0.04 0.0195361 0.0173878 111 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 4.20 vpr 65.79 MiB -1 -1 0.19 21368 1 0.03 -1 -1 34024 -1 -1 40 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67368 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 26.3 MiB 0.18 2606.52 1071 18901 5345 11303 2253 65.8 MiB 0.15 0.00 4.91801 4.13717 -125.663 -4.13717 4.13717 0.38 0.000557717 0.000506362 0.04645 0.042432 -1 -1 -1 -1 28 2309 24 6.64007e+06 502320 500653. 1732.36 2.05 0.293318 0.259893 21970 115934 -1 1945 21 1183 2019 120732 29841 2.95897 2.95897 -114.611 -2.95897 0 0 612192. 2118.31 0.04 0.06 0.10 -1 -1 0.04 0.0257208 0.0229972 141 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.64 vpr 64.86 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33884 -1 -1 25 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66416 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 26.0 MiB 0.24 1957 849 12568 3841 6272 2455 64.9 MiB 0.10 0.00 4.49165 3.90436 -116.108 -3.90436 3.90436 0.38 0.000465876 0.000429566 0.0321093 0.0294124 -1 -1 -1 -1 32 1843 22 6.64007e+06 313950 554710. 1919.41 0.54 0.0899456 0.080136 22834 132086 -1 1628 20 997 1467 92295 22084 2.90603 2.90603 -105.107 -2.90603 0 0 701300. 2426.64 0.04 0.05 0.12 -1 -1 0.04 0.0196436 0.0174594 113 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.50 vpr 66.14 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33312 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67724 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 26.6 MiB 0.11 2312.23 1076 13496 3384 8657 1455 66.1 MiB 0.11 0.00 4.37944 3.74089 -114.6 -3.74089 3.74089 0.38 0.000543244 0.000498996 0.0331757 0.0303142 -1 -1 -1 -1 26 2427 22 6.64007e+06 464646 477104. 1650.88 0.55 0.103371 0.0920225 21682 110474 -1 2048 20 1060 1809 109682 26071 3.00117 3.00117 -111.377 -3.00117 0 0 585099. 2024.56 0.04 0.05 0.10 -1 -1 0.04 0.0236632 0.0210792 131 57 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.67 vpr 66.10 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33636 -1 -1 36 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67684 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 26.5 MiB 0.22 2484.1 1014 11727 2626 8271 830 66.1 MiB 0.11 0.00 4.7433 4.0221 -125.917 -4.0221 4.0221 0.38 0.000597675 0.000547774 0.0338254 0.0310647 -1 -1 -1 -1 30 2137 22 6.64007e+06 452088 526063. 1820.29 0.57 0.11053 0.0983926 22546 126617 -1 1827 21 1316 2009 117999 28007 3.02616 3.02616 -117.524 -3.02616 0 0 666494. 2306.21 0.04 0.06 0.11 -1 -1 0.04 0.0260316 0.0232778 145 91 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.93 vpr 65.65 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33300 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67224 32 32 303 262 1 150 84 17 17 289 -1 unnamed_device 26.1 MiB 0.09 1902.05 955 13626 3828 8006 1792 65.6 MiB 0.10 0.00 3.8549 3.45804 -108.03 -3.45804 3.45804 0.39 0.000457697 0.00041478 0.0368208 0.0334038 -1 -1 -1 -1 28 1980 21 6.64007e+06 251160 500653. 1732.36 1.03 0.151554 0.133161 21970 115934 -1 1683 20 1050 1681 106756 24416 2.63877 2.63877 -102.249 -2.63877 0 0 612192. 2118.31 0.04 0.05 0.10 -1 -1 0.04 0.0210917 0.0187618 111 57 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.61 vpr 65.81 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33244 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67392 32 32 290 244 1 177 89 17 17 289 -1 unnamed_device 26.0 MiB 0.22 2414 1035 16127 4715 9194 2218 65.8 MiB 0.13 0.00 5.19407 4.38701 -135.203 -4.38701 4.38701 0.37 0.000462439 0.000423913 0.0392817 0.0359072 -1 -1 -1 -1 28 2331 19 6.64007e+06 313950 500653. 1732.36 0.57 0.0990219 0.0882017 21970 115934 -1 1998 18 1184 1766 112327 26702 3.18183 3.18183 -121.919 -3.18183 0 0 612192. 2118.31 0.04 0.05 0.11 -1 -1 0.04 0.0199017 0.0178167 123 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 3.52 vpr 66.04 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33412 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67620 32 32 318 257 1 194 92 17 17 289 -1 unnamed_device 26.6 MiB 0.21 2494.89 1051 16652 4865 9400 2387 66.0 MiB 0.14 0.00 5.8041 4.8446 -131.971 -4.8446 4.8446 0.37 0.000488655 0.000447724 0.0420325 0.0385274 -1 -1 -1 -1 32 2232 21 6.64007e+06 351624 554710. 1919.41 1.44 0.172007 0.151911 22834 132086 -1 1890 19 1132 1665 95154 23288 3.71483 3.71483 -123.139 -3.71483 0 0 701300. 2426.64 0.04 0.05 0.12 -1 -1 0.04 0.0223137 0.0200467 138 30 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 3.36 vpr 65.84 MiB -1 -1 0.19 21368 1 0.03 -1 -1 33908 -1 -1 36 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67416 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 26.4 MiB 0.13 1958.08 980 15859 4980 8483 2396 65.8 MiB 0.14 0.00 4.95367 4.35267 -118.417 -4.35267 4.35267 0.38 0.00092915 0.000859916 0.0395316 0.0362695 -1 -1 -1 -1 30 1911 15 6.64007e+06 452088 526063. 1820.29 1.35 0.187261 0.164825 22546 126617 -1 1695 19 778 1338 73788 17524 2.88723 2.88723 -97.9004 -2.88723 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.0220876 0.0197868 129 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.81 vpr 66.29 MiB -1 -1 0.19 21752 1 0.03 -1 -1 33616 -1 -1 29 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67876 32 32 393 312 1 213 93 17 17 289 -1 unnamed_device 26.9 MiB 0.26 3230.85 1190 13323 3872 8044 1407 66.3 MiB 0.13 0.00 7.0852 5.74532 -179.489 -5.74532 5.74532 0.38 0.000660198 0.000590183 0.039564 0.0362209 -1 -1 -1 -1 32 2453 22 6.64007e+06 364182 554710. 1919.41 0.57 0.117386 0.104632 22834 132086 -1 2256 19 1282 1932 121258 28855 4.34589 4.34589 -155.606 -4.34589 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0262197 0.0235765 158 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.27 vpr 65.47 MiB -1 -1 0.16 21368 1 0.03 -1 -1 33600 -1 -1 21 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67044 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 26.2 MiB 0.05 1660.37 747 7221 1683 5260 278 65.5 MiB 0.06 0.00 3.9861 3.49806 -100.112 -3.49806 3.49806 0.38 0.000413501 0.000380737 0.0175745 0.0161041 -1 -1 -1 -1 30 1664 18 6.64007e+06 263718 526063. 1820.29 0.49 0.0681388 0.0604689 22546 126617 -1 1301 16 550 893 50864 12892 2.64857 2.64857 -91.973 -2.64857 0 0 666494. 2306.21 0.04 0.03 0.11 -1 -1 0.04 0.0155399 0.0140016 100 4 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 3.34 vpr 66.49 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33400 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68088 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 26.7 MiB 0.10 2394.39 1117 16081 4509 10164 1408 66.5 MiB 0.14 0.00 5.50696 4.44233 -145.183 -4.44233 4.44233 0.38 0.000639901 0.000586108 0.043964 0.04017 -1 -1 -1 -1 26 2652 23 6.64007e+06 464646 477104. 1650.88 1.35 0.1909 0.168338 21682 110474 -1 2201 22 1473 2256 150477 35220 3.85082 3.85082 -141.208 -3.85082 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0279589 0.0249314 146 90 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.57 vpr 65.90 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33328 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67480 32 32 376 318 1 155 82 17 17 289 -1 unnamed_device 26.3 MiB 0.19 1766.54 907 11830 4057 6026 1747 65.9 MiB 0.10 0.00 4.1133 3.5251 -123.755 -3.5251 3.5251 0.39 0.000533022 0.00048754 0.0386934 0.0354894 -1 -1 -1 -1 32 1799 20 6.64007e+06 226044 554710. 1919.41 0.54 0.106619 0.0948638 22834 132086 -1 1473 21 1093 1568 91986 21714 2.66737 2.66737 -111.365 -2.66737 0 0 701300. 2426.64 0.04 0.05 0.12 -1 -1 0.04 0.0252711 0.0225298 116 96 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 3.54 vpr 66.23 MiB -1 -1 0.18 21368 1 0.03 -1 -1 33284 -1 -1 35 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67824 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 26.6 MiB 0.11 2216.7 928 17199 4960 9079 3160 66.2 MiB 0.14 0.00 4.122 4.04884 -119.605 -4.04884 4.04884 0.39 0.00053155 0.000484949 0.0434918 0.0398215 -1 -1 -1 -1 32 2062 24 6.64007e+06 439530 554710. 1919.41 1.53 0.214426 0.189119 22834 132086 -1 1679 17 885 1479 84469 21628 3.10837 3.10837 -104.18 -3.10837 0 0 701300. 2426.64 0.04 0.05 0.12 -1 -1 0.04 0.0226788 0.0202349 134 60 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.86 vpr 66.39 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33492 -1 -1 33 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67980 32 32 396 299 1 236 97 17 17 289 -1 unnamed_device 26.9 MiB 0.29 3069.29 1286 12085 3172 7944 969 66.4 MiB 0.13 0.00 7.74409 6.4338 -190.103 -6.4338 6.4338 0.38 0.000649596 0.000599463 0.0365754 0.0335079 -1 -1 -1 -1 32 2788 21 6.64007e+06 414414 554710. 1919.41 1.64 0.217927 0.192521 22834 132086 -1 2531 19 1468 2114 119551 29791 4.91134 4.91134 -164.336 -4.91134 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0261025 0.0235239 178 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.39 vpr 65.65 MiB -1 -1 0.16 21176 1 0.03 -1 -1 33268 -1 -1 23 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67228 30 32 224 207 1 138 85 17 17 289 -1 unnamed_device 26.2 MiB 0.16 1779 810 9571 2653 6227 691 65.7 MiB 0.06 0.00 3.77619 3.29107 -101.246 -3.29107 3.29107 0.38 0.000400688 0.000369368 0.0218326 0.0199894 -1 -1 -1 -1 26 1721 19 6.64007e+06 288834 477104. 1650.88 0.51 0.0695218 0.0615859 21682 110474 -1 1475 17 715 938 55370 13918 2.38617 2.38617 -94.6896 -2.38617 0 0 585099. 2024.56 0.04 0.04 0.10 -1 -1 0.04 0.0172297 0.015369 93 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.33 vpr 65.75 MiB -1 -1 0.17 21564 1 0.03 -1 -1 33660 -1 -1 19 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67328 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 26.2 MiB 0.05 1551.56 715 8831 2097 6321 413 65.8 MiB 0.07 0.00 4.64461 4.13192 -117.713 -4.13192 4.13192 0.38 0.00047885 0.000437254 0.0258501 0.0237645 -1 -1 -1 -1 32 1455 18 6.64007e+06 238602 554710. 1919.41 0.50 0.0832703 0.0741651 22834 132086 -1 1299 17 693 1155 74739 18315 2.98597 2.98597 -106.773 -2.98597 0 0 701300. 2426.64 0.05 0.04 0.12 -1 -1 0.05 0.0195047 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release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66768 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 25.8 MiB 0.05 1494.23 591 13153 4635 5984 2534 65.2 MiB 0.08 0.00 4.0913 3.45027 -80.5708 -3.45027 3.45027 0.38 0.000387302 0.000356257 0.0289135 0.0264184 -1 -1 -1 -1 28 1498 20 6.64007e+06 389298 500653. 1732.36 0.53 0.0764326 0.0679351 21970 115934 -1 1204 20 767 1265 67303 18216 2.69777 2.69777 -76.5165 -2.69777 0 0 612192. 2118.31 0.04 0.04 0.10 -1 -1 0.04 0.0165308 0.0146966 93 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 3.63 vpr 66.20 MiB -1 -1 0.19 21400 1 0.03 -1 -1 33288 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67784 32 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65.67 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33524 -1 -1 30 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67244 32 32 299 247 1 188 94 17 17 289 -1 unnamed_device 26.2 MiB 0.08 2525.1 1160 12235 3274 8047 914 65.7 MiB 0.11 0.00 5.48484 4.34297 -114.495 -4.34297 4.34297 0.40 0.000474105 0.000434871 0.0305616 0.028002 -1 -1 -1 -1 26 2538 19 6.65987e+06 380340 477104. 1650.88 0.51 0.092693 0.0825904 21682 110474 -1 2174 21 1271 1771 114907 28449 3.70877 3.70877 -118.091 -3.70877 0 0 585099. 2024.56 0.04 0.05 0.10 -1 -1 0.04 0.0226447 0.020282 129 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.68 vpr 65.55 MiB -1 -1 0.18 21368 1 0.03 -1 -1 33812 -1 -1 31 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67128 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 26.0 MiB 0.06 2219.93 1037 14996 4291 8795 1910 65.6 MiB 0.17 0.00 5.26215 4.34394 -117.35 -4.34394 4.34394 0.41 0.000496322 0.000455237 0.0528329 0.0481725 -1 -1 -1 -1 26 2152 24 6.65987e+06 393018 477104. 1650.88 0.70 0.12069 0.107844 21682 110474 -1 1952 21 1386 2657 159061 39321 3.50331 3.50331 -112.03 -3.50331 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0234306 0.0209526 132 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 3.55 vpr 65.95 MiB -1 -1 0.17 21560 1 0.03 -1 -1 33620 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67532 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 26.4 MiB 0.07 2401.18 1019 9200 2314 6299 587 65.9 MiB 0.10 0.00 5.31844 4.25766 -123.352 -4.25766 4.25766 0.39 0.000557469 0.000513124 0.0274695 0.0250548 -1 -1 -1 -1 30 2290 23 6.65987e+06 354984 526063. 1820.29 1.61 0.168429 0.14819 22546 126617 -1 2006 19 1168 2319 149327 33228 3.17551 3.17551 -115.025 -3.17551 0 0 666494. 2306.21 0.05 0.06 0.12 -1 -1 0.05 0.0232348 0.0208526 134 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 3.39 vpr 66.00 MiB -1 -1 0.18 21436 1 0.03 -1 -1 33844 -1 -1 39 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67580 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 26.3 MiB 0.07 2589.2 1082 13840 3706 8343 1791 66.0 MiB 0.12 0.00 4.08553 3.36433 -115.335 -3.36433 3.36433 0.39 0.000569516 0.000521887 0.0349532 0.0320727 -1 -1 -1 -1 32 2139 20 6.65987e+06 494442 554710. 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7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67372 31 32 317 271 1 168 88 17 17 289 -1 unnamed_device 26.0 MiB 0.07 2086 994 11788 3081 7110 1597 65.8 MiB 0.09 0.00 3.77724 3.3699 -115.577 -3.3699 3.3699 0.38 0.000473371 0.000432809 0.0313198 0.02865 -1 -1 -1 -1 32 1976 22 6.65987e+06 316950 554710. 1919.41 0.53 0.0942169 0.0837445 22834 132086 -1 1765 18 1071 1588 104573 24469 2.78811 2.78811 -108.496 -2.78811 0 0 701300. 2426.64 0.05 0.05 0.12 -1 -1 0.05 0.020808 0.0186794 117 64 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 3.45 vpr 65.50 MiB -1 -1 0.17 21056 1 0.03 -1 -1 33652 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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65.7 MiB 0.08 0.00 4.47555 3.77152 -106.755 -3.77152 3.77152 0.39 0.000462509 0.000424947 0.026569 0.0242956 -1 -1 -1 -1 32 1425 18 6.65987e+06 240882 554710. 1919.41 0.49 0.0829495 0.0735803 22834 132086 -1 1311 19 612 930 53925 14108 2.69371 2.69371 -95.6976 -2.69371 0 0 701300. 2426.64 0.04 0.04 0.12 -1 -1 0.04 0.0208478 0.0187721 101 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.42 vpr 65.43 MiB -1 -1 0.17 21356 1 0.03 -1 -1 33440 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67004 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 25.9 MiB 0.08 2346.38 806 8535 1796 5739 1000 65.4 MiB 0.06 0.00 4.65034 3.70532 -113.865 -3.70532 3.70532 0.38 0.000461526 0.000423212 0.0225621 0.0206982 -1 -1 -1 -1 30 1892 22 6.65987e+06 291594 526063. 1820.29 0.57 0.0822892 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IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67012 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 25.8 MiB 0.10 1651.02 644 11064 3432 5040 2592 65.4 MiB 0.08 0.00 3.69173 2.97053 -85.1657 -2.97053 2.97053 0.39 0.000394601 0.000360429 0.0265306 0.0242573 -1 -1 -1 -1 32 1255 21 6.65987e+06 291594 554710. 1919.41 0.49 0.0790123 0.0700473 22834 132086 -1 1067 19 701 1169 54274 15412 2.52431 2.52431 -81.3486 -2.52431 0 0 701300. 2426.64 0.04 0.04 0.12 -1 -1 0.04 0.0181819 0.0162741 103 27 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 2.53 vpr 65.98 MiB -1 -1 0.18 21464 1 0.03 -1 -1 33480 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 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2.60 vpr 65.69 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33684 -1 -1 24 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67268 31 32 291 243 1 171 87 17 17 289 -1 unnamed_device 26.3 MiB 0.22 2125.96 1049 10455 2730 6522 1203 65.7 MiB 0.09 0.00 5.78495 4.87106 -143.931 -4.87106 4.87106 0.38 0.000502741 0.00046283 0.0283689 0.026027 -1 -1 -1 -1 32 1905 19 6.65987e+06 304272 554710. 1919.41 0.52 0.0874034 0.0777873 22834 132086 -1 1769 21 928 1349 80880 20670 3.48611 3.48611 -129.461 -3.48611 0 0 701300. 2426.64 0.05 0.05 0.12 -1 -1 0.05 0.0226231 0.0202722 127 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 2.77 vpr 66.00 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33812 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67584 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 26.4 MiB 0.06 2331.78 1137 17961 5243 10805 1913 66.0 MiB 0.26 0.01 5.44296 4.2347 -133.733 -4.2347 4.2347 0.47 0.00105911 0.000968379 0.0817034 0.0749499 -1 -1 -1 -1 32 2237 19 6.65987e+06 469086 554710. 1919.41 0.60 0.149474 0.134683 22834 132086 -1 2051 19 1133 1815 133378 30052 3.54863 3.54863 -126.162 -3.54863 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0243128 0.0218435 140 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 4.49 vpr 66.12 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33468 -1 -1 31 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67712 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 26.6 MiB 0.09 2806.99 1076 13055 3622 7425 2008 66.1 MiB 0.13 0.00 5.32315 4.30524 -129.952 -4.30524 4.30524 0.39 0.000590749 0.00054255 0.0375168 0.0343728 -1 -1 -1 -1 28 3135 39 6.65987e+06 393018 500653. 1732.36 2.47 0.226845 0.199876 21970 115934 -1 2403 22 1727 2680 194271 48463 3.95811 3.95811 -127.062 -3.95811 0 0 612192. 2118.31 0.04 0.08 0.11 -1 -1 0.04 0.0286924 0.0257353 151 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.51 vpr 65.10 MiB -1 -1 0.16 21368 1 0.03 -1 -1 34008 -1 -1 20 26 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66660 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 25.8 MiB 0.07 1349.42 468 11200 4643 5749 808 65.1 MiB 0.06 0.00 2.72887 2.30927 -65.1311 -2.30927 2.30927 0.38 0.000322074 0.000293976 0.0236681 0.0216006 -1 -1 -1 -1 28 1180 20 6.65987e+06 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release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67044 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 25.8 MiB 0.06 2077.7 937 13663 4386 7373 1904 65.5 MiB 0.10 0.00 4.42935 3.71432 -111.148 -3.71432 3.71432 0.38 0.000429666 0.000393663 0.0328942 0.0300256 -1 -1 -1 -1 30 1919 20 6.65987e+06 266238 526063. 1820.29 0.51 0.0880498 0.0783579 22546 126617 -1 1728 21 1075 1786 109331 25720 2.65051 2.65051 -104.501 -2.65051 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.0203263 0.0181088 116 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 3.63 vpr 65.67 MiB -1 -1 0.17 21368 1 0.03 -1 -1 34036 -1 -1 33 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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2279 65.8 MiB 0.12 0.00 3.81664 3.21564 -100.343 -3.21564 3.21564 0.41 0.000437686 0.000401052 0.0394748 0.0360388 -1 -1 -1 -1 32 1686 19 6.65987e+06 393018 554710. 1919.41 0.51 0.0970508 0.0865207 22834 132086 -1 1502 17 804 1244 72722 18763 2.31791 2.31791 -89.8179 -2.31791 0 0 701300. 2426.64 0.05 0.04 0.12 -1 -1 0.05 0.0187247 0.0167961 112 54 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 3.67 vpr 65.99 MiB -1 -1 0.18 21560 1 0.03 -1 -1 34060 -1 -1 42 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67576 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 26.6 MiB 0.10 2284.34 1197 8356 1626 6164 566 66.0 MiB 0.09 0.00 4.39192 3.80498 -115.119 -3.80498 3.80498 0.38 0.000658284 0.000607724 0.0224872 0.0206145 -1 -1 -1 -1 28 2868 20 6.65987e+06 532476 500653. 1732.36 1.71 0.195305 0.17201 21970 115934 -1 2278 23 1319 2685 150199 37511 3.25579 3.25579 -111.369 -3.25579 0 0 612192. 2118.31 0.04 0.07 0.10 -1 -1 0.04 0.0293056 0.0262546 158 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 3.62 vpr 65.80 MiB -1 -1 0.18 21372 1 0.03 -1 -1 33284 -1 -1 41 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67384 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 26.4 MiB 0.10 2421.23 1074 11714 2932 8091 691 65.8 MiB 0.11 0.00 4.43155 3.79352 -127.84 -3.79352 3.79352 0.39 0.000602653 0.000551834 0.0316229 0.0288519 -1 -1 -1 -1 26 2556 23 6.65987e+06 519798 477104. 1650.88 1.61 0.203972 0.179488 21682 110474 -1 2044 21 1536 2508 140185 35264 2.89271 2.89271 -117.12 -2.89271 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0278928 0.0250088 150 65 -1 -1 -1 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release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67624 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 26.6 MiB 0.10 2217.26 1103 16238 5000 8812 2426 66.0 MiB 0.14 0.00 4.7803 4.0591 -120.1 -4.0591 4.0591 0.38 0.000578725 0.000530511 0.0464467 0.0425926 -1 -1 -1 -1 28 2598 19 6.65987e+06 367662 500653. 1732.36 1.45 0.188263 0.166734 21970 115934 -1 2318 21 1440 2417 161823 39094 3.18131 3.18131 -120.185 -3.18131 0 0 612192. 2118.31 0.04 0.07 0.10 -1 -1 0.04 0.0269194 0.0241018 145 61 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 3.59 vpr 66.11 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33824 -1 -1 36 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67692 31 32 377 302 1 233 99 17 17 289 -1 unnamed_device 26.7 MiB 0.12 2995 1347 13095 3606 7882 1607 66.1 MiB 0.14 0.00 7.69393 5.70449 -168.317 -5.70449 5.70449 0.38 0.000595858 0.000545024 0.0356862 0.0326771 -1 -1 -1 -1 30 2774 23 6.65987e+06 456408 526063. 1820.29 1.55 0.185131 0.1632 22546 126617 -1 2289 24 1689 2495 132956 32866 4.28377 4.28377 -151.538 -4.28377 0 0 666494. 2306.21 0.04 0.07 0.11 -1 -1 0.04 0.0299843 0.0268798 178 64 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 3.38 vpr 66.12 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33796 -1 -1 32 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67708 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 26.7 MiB 0.88 2722.35 1191 14783 4412 8272 2099 66.1 MiB 0.14 0.00 6.33474 4.98253 -155.947 -4.98253 4.98253 0.38 0.000561347 0.000514059 0.0414764 0.0376532 -1 -1 -1 -1 32 2471 20 6.65987e+06 405696 554710. 1919.41 0.57 0.118364 0.10566 22834 132086 -1 2216 20 1253 2006 113261 28444 4.12757 4.12757 -145.231 -4.12757 0 0 701300. 2426.64 0.05 0.06 0.12 -1 -1 0.05 0.0276206 0.0248614 167 64 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 3.54 vpr 65.77 MiB -1 -1 0.19 21752 1 0.03 -1 -1 33592 -1 -1 37 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67352 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 26.2 MiB 0.10 2150.25 1114 15644 4196 9054 2394 65.8 MiB 0.14 0.00 5.13095 4.43175 -130.025 -4.43175 4.43175 0.38 0.000521675 0.000478535 0.0390612 0.0357746 -1 -1 -1 -1 28 2469 22 6.65987e+06 469086 500653. 1732.36 1.54 0.183699 0.162108 21970 115934 -1 2236 19 1219 2036 126904 31305 3.24571 3.24571 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common 3.97 vpr 66.43 MiB -1 -1 0.20 21624 1 0.03 -1 -1 33920 -1 -1 43 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68020 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 26.9 MiB 0.11 3008.9 1159 20853 5989 11632 3232 66.4 MiB 0.19 0.00 6.00178 4.9754 -157.249 -4.9754 4.9754 0.38 0.000685717 0.000631228 0.0606331 0.0557393 -1 -1 -1 -1 32 2758 30 6.65987e+06 545154 554710. 1919.41 1.83 0.281918 0.250025 22834 132086 -1 2228 22 1382 2242 134818 33340 3.77497 3.77497 -138.412 -3.77497 0 0 701300. 2426.64 0.05 0.07 0.12 -1 -1 0.05 0.0342335 0.0308224 176 87 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.42 vpr 65.64 MiB -1 -1 0.17 21316 1 0.03 -1 -1 33516 -1 -1 23 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67212 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 26.1 MiB 0.07 2009.57 863 10670 2988 6580 1102 65.6 MiB 0.08 0.00 4.26232 3.49198 -99.7308 -3.49198 3.49198 0.39 0.000453222 0.000416938 0.0265956 0.0243438 -1 -1 -1 -1 26 1879 21 6.65987e+06 291594 477104. 1650.88 0.55 0.0842309 0.0749152 21682 110474 -1 1626 18 978 1697 117220 27380 2.82971 2.82971 -98.6632 -2.82971 0 0 585099. 2024.56 0.04 0.05 0.10 -1 -1 0.04 0.0192203 0.01729 104 28 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 3.68 vpr 65.95 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33564 -1 -1 34 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67528 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 26.6 MiB 0.09 2709.85 1080 11641 3126 7253 1262 65.9 MiB 0.11 0.00 5.96575 4.78092 -138.275 -4.78092 4.78092 0.38 0.000521789 0.000477843 0.0298903 0.0272268 -1 -1 -1 -1 30 2823 24 6.65987e+06 431052 526063. 1820.29 1.74 0.19991 0.175596 22546 126617 -1 2125 19 1153 1711 91981 23398 3.97031 3.97031 -126.066 -3.97031 0 0 666494. 2306.21 0.04 0.05 0.11 -1 -1 0.04 0.0236997 0.0213669 149 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 3.49 vpr 65.72 MiB -1 -1 0.18 21180 1 0.03 -1 -1 33844 -1 -1 38 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67300 32 32 349 284 1 182 102 17 17 289 -1 unnamed_device 26.2 MiB 0.08 2675.2 1109 17952 4970 9989 2993 65.7 MiB 0.15 0.00 4.8754 3.83798 -111 -3.83798 3.83798 0.38 0.000526111 0.000482297 0.0430344 0.0393997 -1 -1 -1 -1 28 2576 37 6.65987e+06 481764 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success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67628 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 26.6 MiB 0.10 2461.47 971 13599 3655 7723 2221 66.0 MiB 0.11 0.00 4.2905 3.76064 -115.976 -3.76064 3.76064 0.39 0.000557132 0.000508572 0.0342721 0.0312661 -1 -1 -1 -1 32 2312 31 6.65987e+06 494442 554710. 1919.41 0.84 0.135517 0.119577 22834 132086 -1 1776 19 1047 1748 95715 24988 2.91291 2.91291 -105.63 -2.91291 0 0 701300. 2426.64 0.05 0.05 0.12 -1 -1 0.05 0.0242557 0.021769 139 55 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.85 vpr 66.05 MiB -1 -1 0.18 21752 1 0.03 -1 -1 33676 -1 -1 40 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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65.57 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33416 -1 -1 39 28 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67148 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 26.0 MiB 0.07 1932.95 968 16515 5028 9029 2458 65.6 MiB 0.11 0.00 4.80358 3.82106 -98.9222 -3.82106 3.82106 0.40 0.000472208 0.000434761 0.0344599 0.0314441 -1 -1 -1 -1 30 1920 22 6.65987e+06 494442 526063. 1820.29 0.53 0.0922077 0.0819083 22546 126617 -1 1687 18 746 1556 78646 19064 3.06345 3.06345 -92.4917 -3.06345 0 0 666494. 2306.21 0.04 0.04 0.12 -1 -1 0.04 0.0188192 0.0168871 122 27 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 2.51 vpr 65.71 MiB -1 -1 0.18 21368 1 0.03 -1 -1 33632 -1 -1 21 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67284 30 32 317 269 1 152 83 17 17 289 -1 unnamed_device 26.2 MiB 0.10 2031.45 790 14123 5409 6959 1755 65.7 MiB 0.11 0.00 4.52275 3.80155 -112.551 -3.80155 3.80155 0.38 0.000478264 0.000438814 0.0403247 0.0369342 -1 -1 -1 -1 32 1837 18 6.65987e+06 266238 554710. 1919.41 0.55 0.104833 0.0935072 22834 132086 -1 1548 18 983 1739 115479 27859 2.69451 2.69451 -101.472 -2.69451 0 0 701300. 2426.64 0.05 0.05 0.12 -1 -1 0.05 0.021806 0.0195975 115 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 3.30 vpr 65.86 MiB -1 -1 0.17 21752 1 0.03 -1 -1 33856 -1 -1 26 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67444 32 32 335 282 1 184 90 17 17 289 -1 unnamed_device 26.4 MiB 0.11 2267 1030 6522 1299 4937 286 65.9 MiB 0.07 0.00 4.27587 3.73584 -126.486 -3.73584 3.73584 0.38 0.00053041 0.000487863 0.0191302 0.0175448 -1 -1 -1 -1 28 2512 22 6.65987e+06 329628 500653. 1732.36 1.41 0.159524 0.139471 21970 115934 -1 2122 19 1254 1869 129869 31549 3.07251 3.07251 -121.417 -3.07251 0 0 612192. 2118.31 0.04 0.06 0.10 -1 -1 0.04 0.0222874 0.0199429 127 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.47 vpr 65.67 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33440 -1 -1 37 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67244 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 26.2 MiB 0.06 2060.32 1066 14716 3823 8466 2427 65.7 MiB 0.12 0.00 4.86349 4.26143 -121.889 -4.26143 4.26143 0.38 0.000469132 0.00042593 0.0324801 0.0295096 -1 -1 -1 -1 32 2163 21 6.65987e+06 469086 554710. 1919.41 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7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67704 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 26.7 MiB 0.10 2914.32 1147 17058 4935 9734 2389 66.1 MiB 0.15 0.00 5.66375 4.31449 -136.308 -4.31449 4.31449 0.38 0.00059986 0.000547904 0.0417184 0.0380152 -1 -1 -1 -1 32 2511 20 6.65987e+06 545154 554710. 1919.41 1.76 0.220411 0.193327 22834 132086 -1 2315 23 1351 2490 169172 38813 3.21051 3.21051 -124.387 -3.21051 0 0 701300. 2426.64 0.04 0.07 0.12 -1 -1 0.04 0.0296382 0.0266206 147 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 3.28 vpr 65.70 MiB -1 -1 0.17 21524 1 0.03 -1 -1 33488 -1 -1 21 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67280 30 32 272 232 1 147 83 17 17 289 -1 unnamed_device 26.2 MiB 0.08 1945.6 753 7283 1769 5122 392 65.7 MiB 0.06 0.00 4.63389 3.70663 -109.826 -3.70663 3.70663 0.38 0.000437153 0.000400757 0.0194829 0.0178772 -1 -1 -1 -1 28 1998 21 6.65987e+06 266238 500653. 1732.36 1.44 0.146339 0.128218 21970 115934 -1 1588 19 981 1671 105950 26795 2.76365 2.76365 -102.724 -2.76365 0 0 612192. 2118.31 0.04 0.05 0.10 -1 -1 0.04 0.0196765 0.0176476 109 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 3.47 vpr 65.77 MiB -1 -1 0.18 21284 1 0.03 -1 -1 33856 -1 -1 27 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67344 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 26.2 MiB 0.12 2634.2 1004 13355 3928 8436 991 65.8 MiB 0.13 0.00 5.58041 4.67277 -135.957 -4.67277 4.67277 0.40 0.000576702 0.000529909 0.0417085 0.0382456 -1 -1 -1 -1 30 2060 19 6.65987e+06 342306 526063. 1820.29 1.45 0.187515 0.165524 22546 126617 -1 1821 20 1201 1955 93648 23805 3.30497 3.30497 -120.605 -3.30497 0 0 666494. 2306.21 0.04 0.06 0.11 -1 -1 0.04 0.0266043 0.0239778 147 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 3.61 vpr 65.84 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33284 -1 -1 30 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67420 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 26.3 MiB 0.09 2590.19 1225 16708 4680 10035 1993 65.8 MiB 0.15 0.00 6.11242 5.05783 -151.14 -5.05783 5.05783 0.38 0.000588904 0.000533884 0.046165 0.042366 -1 -1 -1 -1 32 2471 21 6.65987e+06 380340 554710. 1919.41 1.61 0.232658 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IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67444 32 32 365 294 1 185 89 17 17 289 -1 unnamed_device 26.6 MiB 0.09 2700.81 903 8603 1875 6005 723 65.9 MiB 0.08 0.00 5.82395 4.87469 -134.601 -4.87469 4.87469 0.38 0.000610673 0.000545564 0.0272552 0.0250323 -1 -1 -1 -1 32 2378 24 6.65987e+06 316950 554710. 1919.41 0.61 0.105353 0.0939021 22834 132086 -1 1998 20 1245 2249 130260 34250 3.76951 3.76951 -130.632 -3.76951 0 0 701300. 2426.64 0.05 0.06 0.12 -1 -1 0.05 0.0261665 0.0235091 141 57 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 3.64 vpr 66.03 MiB -1 -1 0.19 21752 1 0.03 -1 -1 33632 -1 -1 38 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 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common 3.40 vpr 65.59 MiB -1 -1 0.16 21368 1 0.03 -1 -1 33372 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67168 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 25.7 MiB 0.09 2060.39 1077 13751 3805 8008 1938 65.6 MiB 0.10 0.00 4.9641 4.0025 -114.881 -4.0025 4.0025 0.38 0.000424496 0.000387986 0.0322604 0.0294969 -1 -1 -1 -1 26 2369 16 6.65987e+06 316950 477104. 1650.88 1.51 0.167545 0.147142 21682 110474 -1 2027 18 886 1189 89655 21412 3.15037 3.15037 -115.519 -3.15037 0 0 585099. 2024.56 0.04 0.04 0.10 -1 -1 0.04 0.0185178 0.0165967 117 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 2.43 vpr 65.24 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33256 -1 -1 23 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66804 31 32 245 205 1 150 86 17 17 289 -1 unnamed_device 25.4 MiB 0.05 2068.08 883 14639 5191 7304 2144 65.2 MiB 0.11 0.00 4.81301 3.84841 -109.743 -3.84841 3.84841 0.38 0.000430088 0.000395671 0.0349103 0.0319464 -1 -1 -1 -1 32 1873 20 6.65987e+06 291594 554710. 1919.41 0.54 0.0915413 0.0816866 22834 132086 -1 1716 18 1042 1695 113744 27403 2.66951 2.66951 -100.595 -2.66951 0 0 701300. 2426.64 0.05 0.05 0.12 -1 -1 0.05 0.0181641 0.0162522 110 4 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 2.62 vpr 65.79 MiB -1 -1 0.18 21412 1 0.03 -1 -1 33848 -1 -1 30 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67368 32 32 348 274 1 211 94 17 17 289 -1 unnamed_device 26.4 MiB 0.09 2693.29 1154 11170 2964 7586 620 65.8 MiB 0.11 0.00 6.19807 4.91021 -151.192 -4.91021 4.91021 0.39 0.000527548 0.000485087 0.0311748 0.0285825 -1 -1 -1 -1 26 2961 21 6.65987e+06 380340 477104. 1650.88 0.67 0.104238 0.0929009 21682 110474 -1 2510 22 1756 2403 165180 40178 3.93843 3.93843 -144.43 -3.93843 0 0 585099. 2024.56 0.04 0.07 0.10 -1 -1 0.04 0.0267598 0.0239366 151 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 3.65 vpr 65.79 MiB -1 -1 0.18 21560 1 0.03 -1 -1 33432 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67368 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 26.1 MiB 0.17 2455.35 1155 17726 5493 9367 2866 65.8 MiB 0.15 0.00 6.19085 4.97841 -147.225 -4.97841 4.97841 0.38 0.00052755 0.00048279 0.0443313 0.0405578 -1 -1 -1 -1 32 2499 24 6.65987e+06 469086 554710. 1919.41 1.57 0.212887 0.187496 22834 132086 -1 2127 21 1183 1806 123210 29348 4.29791 4.29791 -136.259 -4.29791 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0261277 0.0234751 157 56 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.74 vpr 66.04 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33748 -1 -1 43 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67628 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 26.5 MiB 0.06 2789.56 1282 17058 4558 10111 2389 66.0 MiB 0.14 0.00 6.22775 5.25635 -138.9 -5.25635 5.25635 0.38 0.000581852 0.000534016 0.0403375 0.036905 -1 -1 -1 -1 30 2744 22 6.65987e+06 545154 526063. 1820.29 0.77 0.118403 0.106047 22546 126617 -1 2279 19 1165 2296 144567 32446 4.20857 4.20857 -132.092 -4.20857 0 0 666494. 2306.21 0.04 0.06 0.12 -1 -1 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-1 23 27 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67152 27 32 255 219 1 132 82 17 17 289 -1 unnamed_device 25.8 MiB 0.05 1707.48 762 11296 3316 6423 1557 65.6 MiB 0.07 0.00 4.35664 3.48247 -97.7908 -3.48247 3.48247 0.39 0.000404639 0.000371172 0.0274846 0.0251563 -1 -1 -1 -1 32 1498 19 6.65987e+06 291594 554710. 1919.41 0.51 0.0796712 0.0707712 22834 132086 -1 1390 21 750 1239 79737 19491 2.74977 2.74977 -93.2365 -2.74977 0 0 701300. 2426.64 0.04 0.04 0.12 -1 -1 0.04 0.0196735 0.017582 100 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 5.50 vpr 66.10 MiB -1 -1 0.19 21756 1 0.03 -1 -1 33992 -1 -1 34 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67684 32 32 421 327 1 232 98 17 17 289 -1 unnamed_device 26.6 MiB 0.10 3118.28 1439 17873 5278 9863 2732 66.1 MiB 0.18 0.00 5.30144 4.29603 -137.315 -4.29603 4.29603 0.39 0.000625487 0.000574956 0.0536001 0.0491478 -1 -1 -1 -1 28 3695 44 6.65987e+06 431052 500653. 1732.36 3.39 0.274566 0.242666 21970 115934 -1 2923 19 1836 3149 215793 51340 3.77085 3.77085 -133.519 -3.77085 0 0 612192. 2118.31 0.04 0.08 0.11 -1 -1 0.04 0.0278651 0.0250085 176 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 3.06 vpr 65.97 MiB -1 -1 0.19 21564 1 0.03 -1 -1 33764 -1 -1 27 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67552 31 32 365 296 1 193 90 17 17 289 -1 unnamed_device 26.4 MiB 0.57 2493.9 1189 15567 4325 9105 2137 66.0 MiB 0.13 0.00 6.19101 5.35977 -160.519 -5.35977 5.35977 0.38 0.000537895 0.000493376 0.0453793 0.0416429 -1 -1 -1 -1 32 2369 25 6.65987e+06 342306 554710. 1919.41 0.58 0.121624 0.108635 22834 132086 -1 2118 23 1311 2036 116956 29594 4.02037 4.02037 -141.808 -4.02037 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0276062 0.0247689 151 64 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 3.82 vpr 65.79 MiB -1 -1 0.18 21368 1 0.03 -1 -1 33528 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67364 32 32 331 280 1 175 87 17 17 289 -1 unnamed_device 26.2 MiB 0.57 2093.8 920 12951 4416 6088 2447 65.8 MiB 0.11 0.00 5.5891 4.3919 -134.435 -4.3919 4.3919 0.39 0.000484848 0.00044259 0.0358582 0.0328109 -1 -1 -1 -1 32 1877 17 6.65987e+06 291594 554710. 1919.41 1.40 0.147067 0.129765 22834 132086 -1 1679 14 656 908 61599 15310 3.27896 3.27896 -122.066 -3.27896 0 0 701300. 2426.64 0.05 0.04 0.12 -1 -1 0.05 0.018501 0.0168401 129 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 3.46 vpr 65.68 MiB -1 -1 0.17 21560 1 0.03 -1 -1 33436 -1 -1 36 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67252 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 26.2 MiB 0.06 2458.13 976 11932 2822 8405 705 65.7 MiB 0.10 0.00 5.92474 4.92153 -124.696 -4.92153 4.92153 0.38 0.000525754 0.000476942 0.0291991 0.0264949 -1 -1 -1 -1 30 2020 19 6.65987e+06 456408 526063. 1820.29 1.57 0.201246 0.176114 22546 126617 -1 1746 20 829 1405 72525 19108 3.30585 3.30585 -107.445 -3.30585 0 0 666494. 2306.21 0.04 0.04 0.11 -1 -1 0.04 0.023062 0.0207251 133 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.38 vpr 66.13 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33568 -1 -1 39 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67720 31 32 373 294 1 196 102 17 17 289 -1 unnamed_device 26.8 MiB 0.08 2306.64 1120 6766 1341 5034 391 66.1 MiB 0.07 0.00 5.28538 4.62052 -121.821 -4.62052 4.62052 0.37 0.000597566 0.000539634 0.0185347 0.0170501 -1 -1 -1 -1 28 2512 21 6.65987e+06 494442 500653. 1732.36 1.47 0.175619 0.15423 21970 115934 -1 2177 19 1181 1926 115990 29185 4.04905 4.04905 -126.175 -4.04905 0 0 612192. 2118.31 0.04 0.06 0.10 -1 -1 0.04 0.0251542 0.0226208 151 50 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 3.39 vpr 66.07 MiB -1 -1 0.18 21752 1 0.03 -1 -1 33880 -1 -1 36 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67660 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 26.4 MiB 0.08 2399.09 1034 15848 5113 8095 2640 66.1 MiB 0.13 0.00 4.35464 3.63344 -103.221 -3.63344 3.63344 0.38 0.000508446 0.000466408 0.0376678 0.0344909 -1 -1 -1 -1 28 2560 23 6.65987e+06 456408 500653. 1732.36 1.45 0.186383 0.164148 21970 115934 -1 2074 18 1168 2049 135149 32440 3.10931 3.10931 -103.776 -3.10931 0 0 612192. 2118.31 0.04 0.06 0.10 -1 -1 0.04 0.0218463 0.0195539 130 51 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 3.55 vpr 65.80 MiB -1 -1 0.18 21484 1 0.03 -1 -1 33452 -1 -1 31 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 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0.000573204 0.000525137 0.0480204 0.0439177 -1 -1 -1 -1 32 2382 23 6.65987e+06 532476 554710. 1919.41 1.57 0.208691 0.1837 22834 132086 -1 1860 22 1262 2005 127976 32934 2.99297 2.99297 -111.341 -2.99297 0 0 701300. 2426.64 0.04 0.06 0.12 -1 -1 0.04 0.0279192 0.0250024 151 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 3.25 vpr 65.59 MiB -1 -1 0.17 21560 1 0.03 -1 -1 33820 -1 -1 19 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67160 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 25.6 MiB 0.05 1576.62 630 12464 3295 8498 671 65.6 MiB 0.09 0.00 4.48041 4.01678 -108.089 -4.01678 4.01678 0.39 0.000417905 0.000382509 0.0341583 0.0313198 -1 -1 -1 -1 32 1431 23 6.65987e+06 240882 554710. 1919.41 1.38 0.146818 0.129059 22834 132086 -1 1321 17 727 1046 73771 17852 2.80257 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2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67132 29 32 262 224 1 168 87 17 17 289 -1 unnamed_device 26.0 MiB 0.07 1919.9 847 7575 1662 5348 565 65.6 MiB 0.06 0.00 4.7147 3.89047 -104.299 -3.89047 3.89047 0.38 0.000480717 0.000444989 0.0189001 0.0173302 -1 -1 -1 -1 26 2097 25 6.65987e+06 329628 477104. 1650.88 0.60 0.0801126 0.0708995 21682 110474 -1 1708 21 880 1127 72309 18021 3.46957 3.46957 -105.456 -3.46957 0 0 585099. 2024.56 0.04 0.04 0.10 -1 -1 0.04 0.0207275 0.018517 116 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 3.27 vpr 65.45 MiB -1 -1 0.16 21560 1 0.03 -1 -1 33428 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67020 32 32 278 238 1 148 83 17 17 289 -1 unnamed_device 25.8 MiB 0.10 1709.72 894 8183 1889 5501 793 65.4 MiB 0.07 0.00 4.06989 3.71146 -116.663 -3.71146 3.71146 0.39 0.000475404 0.000436181 0.0225042 0.0206694 -1 -1 -1 -1 28 2074 23 6.65987e+06 240882 500653. 1732.36 1.38 0.152437 0.133626 21970 115934 -1 1886 22 1249 2134 145663 33847 2.72165 2.72165 -106.731 -2.72165 0 0 612192. 2118.31 0.04 0.06 0.10 -1 -1 0.04 0.02219 0.0198037 111 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.54 vpr 65.93 MiB -1 -1 0.19 21752 1 0.03 -1 -1 33448 -1 -1 40 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67512 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 26.3 MiB 0.10 2538.36 1021 18178 5350 10275 2553 65.9 MiB 0.14 0.00 4.83595 3.99455 -120.428 -3.99455 3.99455 0.38 0.00053861 0.000494675 0.0453322 0.0415327 -1 -1 -1 -1 30 2079 20 6.65987e+06 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0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67816 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 26.6 MiB 0.54 2511.58 991 11499 2724 7874 901 66.2 MiB 0.11 0.00 4.68116 3.97713 -123.797 -3.97713 3.97713 0.38 0.000549553 0.000503027 0.0314925 0.0287828 -1 -1 -1 -1 32 2143 25 6.65987e+06 456408 554710. 1919.41 1.51 0.183002 0.16041 22834 132086 -1 1829 21 1239 1858 114185 27614 3.08931 3.08931 -117.091 -3.08931 0 0 701300. 2426.64 0.05 0.06 0.12 -1 -1 0.05 0.0280044 0.0250285 145 91 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 3.28 vpr 65.60 MiB -1 -1 0.17 21368 1 0.03 -1 -1 33488 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66852 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 26.0 MiB 0.06 1660.37 797 8502 1949 6085 468 65.3 MiB 0.07 0.00 3.86484 3.31781 -96.9676 -3.31781 3.31781 0.38 0.000387715 0.000355028 0.0216491 0.019856 -1 -1 -1 -1 32 1566 18 6.65987e+06 266238 554710. 1919.41 0.48 0.0697138 0.0617621 22834 132086 -1 1391 19 657 1075 65111 16588 2.50751 2.50751 -91.4965 -2.50751 0 0 701300. 2426.64 0.07 0.06 0.13 -1 -1 0.07 0.0304659 0.0273847 100 4 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 2.57 vpr 66.18 MiB -1 -1 0.19 21560 1 0.03 -1 -1 33396 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 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2.9965 -104.682 -2.9965 2.9965 0.40 0.000496937 0.000455978 0.0180421 0.0164969 -1 -1 -1 -1 36 2414 49 6.95648e+06 390843 648988. 2245.63 1.92 0.145256 0.127498 26050 158493 -1 2132 24 1474 2395 199348 43414 3.61137 3.61137 -119.408 -3.61137 0 0 828058. 2865.25 0.05 0.07 0.14 -1 -1 0.05 0.0258573 0.0230418 77 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_028.v common 5.57 vpr 66.77 MiB -1 -1 0.18 21184 1 0.03 -1 -1 33604 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68376 32 32 338 277 1 172 87 17 17 289 -1 unnamed_device 27.0 MiB 0.66 2669.29 874 15063 4561 8642 1860 66.8 MiB 0.12 0.00 5.40282 4.22168 -126.749 -4.22168 4.22168 0.41 0.000518625 0.000474538 0.0456285 0.0417072 -1 -1 -1 -1 36 2848 47 6.95648e+06 332941 648988. 2245.63 2.89 0.188753 0.166756 26050 158493 -1 2116 21 1518 2498 224468 49562 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0.19 21596 1 0.03 -1 -1 33600 -1 -1 17 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68344 31 32 383 305 1 201 80 17 17 289 -1 unnamed_device 27.3 MiB 2.03 2460.8 938 14012 6050 7484 478 66.7 MiB 0.11 0.00 5.07595 4.39319 -147.97 -4.39319 4.39319 0.39 0.000549337 0.000502507 0.0479444 0.0438767 -1 -1 -1 -1 46 2574 33 6.95648e+06 246087 828058. 2865.25 1.72 0.182708 0.162084 28066 200906 -1 2087 21 1723 2601 166326 39721 4.33271 4.33271 -148.753 -4.33271 0 0 1.01997e+06 3529.29 0.06 0.07 0.18 -1 -1 0.06 0.0278069 0.0250316 88 64 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_041.v common 8.92 vpr 65.74 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33660 -1 -1 23 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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5.02688 4.05268 -121.011 -4.05268 4.05268 0.40 0.000498065 0.000459385 0.0293479 0.0269344 -1 -1 -1 -1 36 2592 25 6.95648e+06 260562 648988. 2245.63 1.42 0.136277 0.120415 26050 158493 -1 2252 21 1397 2007 181674 36928 3.91432 3.91432 -125.021 -3.91432 0 0 828058. 2865.25 0.05 0.06 0.14 -1 -1 0.05 0.022993 0.0205566 70 27 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_043.v common 5.61 vpr 67.01 MiB -1 -1 0.19 21704 1 0.03 -1 -1 33712 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68616 32 32 457 356 1 214 92 17 17 289 -1 unnamed_device 27.2 MiB 1.02 3011.34 1199 9614 2248 6243 1123 67.0 MiB 0.09 0.00 5.60998 4.24958 -145.469 -4.24958 4.24958 0.40 0.00063394 0.000580856 0.0335589 0.0308212 -1 -1 -1 -1 36 3239 50 6.95648e+06 405319 648988. 2245.63 2.57 0.209889 0.185826 26050 158493 -1 2666 23 2075 3298 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0.19 21568 1 0.03 -1 -1 33708 -1 -1 18 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67608 31 32 337 267 1 199 81 17 17 289 -1 unnamed_device 27.0 MiB 1.18 2145.79 1112 10931 4151 5627 1153 66.0 MiB 0.09 0.00 4.85719 4.35599 -139.539 -4.35599 4.35599 0.40 0.000509934 0.000466216 0.0351356 0.0322251 -1 -1 -1 -1 42 2747 44 6.95648e+06 260562 744469. 2576.02 11.87 0.290009 0.254618 27202 183097 -1 2316 23 1627 2442 207799 43786 4.23236 4.23236 -142.442 -4.23236 0 0 949917. 3286.91 0.06 0.08 0.16 -1 -1 0.06 0.0283099 0.0254476 82 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 4.78 vpr 66.61 MiB -1 -1 0.18 21376 1 0.03 -1 -1 33828 -1 -1 26 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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3.99627 -123.227 -3.99627 3.99627 0.41 0.000470511 0.000429828 0.032983 0.0301714 -1 -1 -1 -1 36 2563 29 6.95648e+06 275038 648988. 2245.63 1.95 0.151156 0.134093 26050 158493 -1 2183 22 1428 2520 202696 44123 3.83276 3.83276 -133.9 -3.83276 0 0 828058. 2865.25 0.05 0.07 0.14 -1 -1 0.05 0.0239068 0.02145 70 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_048.v common 5.89 vpr 66.69 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33632 -1 -1 16 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68288 32 32 353 287 1 190 80 17 17 289 -1 unnamed_device 27.0 MiB 1.72 2163.96 1097 11948 3658 6620 1670 66.7 MiB 0.09 0.00 4.63715 4.346 -136.985 -4.346 4.346 0.40 0.000528965 0.000484968 0.0395498 0.0362681 -1 -1 -1 -1 34 2975 47 6.95648e+06 231611 618332. 2139.56 2.22 0.182341 0.160897 25762 151098 -1 2354 20 1518 2047 175086 38630 3.82676 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5.21638 4.27023 -132.909 -4.27023 4.27023 0.40 0.000484485 0.000442825 0.0409395 0.0375233 -1 -1 -1 -1 40 2457 20 6.95648e+06 246087 706193. 2443.58 5.46 0.240691 0.211262 26914 176310 -1 2218 21 1638 2223 167801 36873 3.79792 3.79792 -134.357 -3.79792 0 0 926341. 3205.33 0.05 0.06 0.16 -1 -1 0.05 0.0243007 0.0218074 78 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_053.v common 5.27 vpr 66.73 MiB -1 -1 0.19 21760 1 0.03 -1 -1 33272 -1 -1 17 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68328 31 32 373 299 1 197 80 17 17 289 -1 unnamed_device 27.3 MiB 1.25 2531.61 897 9540 3871 5214 455 66.7 MiB 0.08 0.00 5.05188 4.17558 -131.538 -4.17558 4.17558 0.40 0.000544781 0.000498664 0.0331911 0.0304137 -1 -1 -1 -1 52 2602 45 6.95648e+06 246087 926341. 3205.33 1.96 0.180273 0.159265 29218 227130 -1 1929 23 1708 2759 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5.95448 4.84692 -154.661 -4.84692 4.84692 0.40 0.000631656 0.000583233 0.0474105 0.0436087 -1 -1 -1 -1 42 3678 49 6.95648e+06 260562 744469. 2576.02 14.28 0.342335 0.302297 27202 183097 -1 2977 30 2554 3930 497468 142208 5.51526 5.51526 -166.404 -5.51526 0 0 949917. 3286.91 0.06 0.17 0.26 -1 -1 0.06 0.0382977 0.0342734 95 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_058.v common 4.28 vpr 65.98 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33644 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67560 32 32 340 270 1 174 84 17 17 289 -1 unnamed_device 27.1 MiB 0.69 1785.95 1004 12162 4142 6583 1437 66.0 MiB 0.09 0.00 3.74951 3.62421 -127.524 -3.62421 3.62421 0.40 0.000503521 0.000460272 0.0367255 0.0336355 -1 -1 -1 -1 34 2614 24 6.95648e+06 289514 618332. 2139.56 1.67 0.158174 0.139834 25762 151098 -1 2197 22 1673 2441 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21952 1 0.03 -1 -1 33700 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68596 32 32 431 332 1 227 82 17 17 289 -1 unnamed_device 27.5 MiB 1.57 2894.15 1372 10584 3239 6480 865 67.0 MiB 0.10 0.00 6.27232 5.48274 -168.026 -5.48274 5.48274 0.40 0.000614113 0.000560897 0.0403135 0.0369905 -1 -1 -1 -1 40 3261 24 6.95648e+06 260562 706193. 2443.58 2.27 0.185728 0.16535 26914 176310 -1 2808 20 2067 3042 240600 51699 5.01116 5.01116 -171.359 -5.01116 0 0 926341. 3205.33 0.05 0.09 0.15 -1 -1 0.05 0.031379 0.0283917 94 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 4.48 vpr 66.38 MiB -1 -1 0.17 21760 1 0.03 -1 -1 33848 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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4.14368 -134.376 -4.14368 4.14368 0.40 0.00051802 0.000472959 0.0436159 0.0398933 -1 -1 -1 -1 36 2481 34 6.95648e+06 275038 648988. 2245.63 1.56 0.175258 0.154848 26050 158493 -1 1947 23 1701 2459 192548 45377 4.30012 4.30012 -147.879 -4.30012 0 0 828058. 2865.25 0.05 0.09 0.14 -1 -1 0.05 0.0327992 0.0293077 74 54 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_068.v common 5.42 vpr 66.05 MiB -1 -1 0.18 21484 1 0.03 -1 -1 33888 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67636 32 32 353 285 1 175 84 17 17 289 -1 unnamed_device 27.0 MiB 0.63 1817.17 988 13443 4741 6786 1916 66.1 MiB 0.10 0.00 4.64078 4.17648 -135.842 -4.17648 4.17648 0.40 0.000535103 0.000489189 0.0430496 0.0393687 -1 -1 -1 -1 36 3048 49 6.95648e+06 289514 648988. 2245.63 2.81 0.190649 0.168717 26050 158493 -1 2385 23 1677 2692 269744 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5.96575 5.12445 -155.529 -5.12445 5.12445 0.40 0.000526048 0.000481717 0.0408116 0.0373807 -1 -1 -1 -1 38 2762 45 6.95648e+06 246087 678818. 2348.85 2.01 0.182988 0.161827 26626 170182 -1 2224 21 1531 2248 178571 38503 4.67096 4.67096 -158.865 -4.67096 0 0 902133. 3121.57 0.05 0.07 0.15 -1 -1 0.05 0.0268604 0.0241331 81 64 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_098.v common 10.12 vpr 65.79 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33860 -1 -1 13 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67368 32 32 331 280 1 171 77 17 17 289 -1 unnamed_device 27.0 MiB 3.85 2263.53 831 10346 4372 5809 165 65.8 MiB 0.08 0.00 4.65874 3.66435 -131.027 -3.66435 3.66435 0.40 0.000498035 0.000454895 0.0334609 0.0305645 -1 -1 -1 -1 36 2472 30 6.95648e+06 188184 648988. 2245.63 4.35 0.214566 0.187603 26050 158493 -1 1919 17 1310 1854 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4.77678 4.16128 -145.153 -4.16128 4.16128 0.39 0.000523961 0.000478689 0.0396166 0.0363095 -1 -1 -1 -1 40 3076 32 6.95648e+06 260562 706193. 2443.58 12.82 0.289231 0.254203 26914 176310 -1 2751 22 2174 3303 349091 81174 4.01312 4.01312 -150.318 -4.01312 0 0 926341. 3205.33 0.05 0.11 0.17 -1 -1 0.05 0.0281214 0.025272 86 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 3.80 vpr 66.56 MiB -1 -1 0.17 21760 1 0.03 -1 -1 33716 -1 -1 29 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68160 32 32 386 307 1 187 93 17 17 289 -1 unnamed_device 27.0 MiB 0.47 2024.23 1035 11643 3723 6128 1792 66.6 MiB 0.09 0.00 3.74723 3.51453 -126.992 -3.51453 3.51453 0.40 0.000580986 0.000512062 0.0349697 0.032057 -1 -1 -1 -1 38 2497 41 6.95648e+06 419795 678818. 2348.85 1.35 0.179089 0.158007 26626 170182 -1 2126 21 1643 2340 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67472 32 32 349 286 1 165 90 17 17 289 -1 unnamed_device 27.0 MiB 1.07 2297.24 786 16371 5346 8562 2463 65.9 MiB 0.11 0.00 3.67454 3.219 -105.866 -3.219 3.219 0.46 0.000535656 0.00049052 0.0452139 0.0413057 -1 -1 -1 -1 36 2478 41 6.95648e+06 376368 648988. 2245.63 2.92 0.18502 0.163667 26050 158493 -1 1746 19 1244 2022 141843 33916 3.28147 3.28147 -107.564 -3.28147 0 0 828058. 2865.25 0.05 0.06 0.14 -1 -1 0.05 0.0231938 0.020777 73 57 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_112.v common 6.11 vpr 66.09 MiB -1 -1 0.19 21376 1 0.03 -1 -1 33652 -1 -1 20 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67680 31 32 396 325 1 176 83 17 17 289 -1 unnamed_device 27.3 MiB 1.50 2367.43 760 13403 5641 7157 605 66.1 MiB 0.10 0.00 4.16215 3.42825 -117.829 -3.42825 3.42825 0.40 0.000578795 0.00053017 0.0463358 0.0425357 -1 -1 -1 -1 40 2441 42 6.95648e+06 289514 706193. 2443.58 2.60 0.193189 0.170876 26914 176310 -1 1940 25 1789 2570 188127 47601 3.62427 3.62427 -132.869 -3.62427 0 0 926341. 3205.33 0.05 0.08 0.16 -1 -1 0.05 0.030694 0.0273646 79 91 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_113.v common 3.74 vpr 65.88 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33296 -1 -1 11 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67456 32 32 303 262 1 145 75 17 17 289 -1 unnamed_device 26.6 MiB 0.35 1778.98 712 10977 4578 6228 171 65.9 MiB 0.08 0.00 3.29253 2.84005 -99.7836 -2.84005 2.84005 0.41 0.000452574 0.00041326 0.0343895 0.0314314 -1 -1 -1 -1 36 2050 34 6.95648e+06 159232 648988. 2245.63 1.48 0.148521 0.130762 26050 158493 -1 1762 20 1194 1822 154899 35238 3.11192 3.11192 -113.612 -3.11192 0 0 828058. 2865.25 0.05 0.06 0.14 -1 -1 0.05 0.0216285 0.0193336 58 57 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_114.v common 5.04 vpr 65.82 MiB -1 -1 0.17 21504 1 0.03 -1 -1 33800 -1 -1 14 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67404 32 32 290 244 1 172 78 17 17 289 -1 unnamed_device 26.9 MiB 1.27 1995 861 8378 1972 6153 253 65.8 MiB 0.07 0.00 3.97583 3.49463 -115.332 -3.49463 3.49463 0.40 0.000466792 0.000428881 0.0255097 0.0233783 -1 -1 -1 -1 40 2267 25 6.95648e+06 202660 706193. 2443.58 1.86 0.13118 0.115624 26914 176310 -1 1967 21 1553 2292 189903 41785 3.35347 3.35347 -120.801 -3.35347 0 0 926341. 3205.33 0.05 0.07 0.16 -1 -1 0.05 0.02267 0.0203207 68 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_115.v common 4.53 vpr 66.56 MiB -1 -1 0.17 21760 1 0.03 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67556 29 32 324 268 1 162 86 17 17 289 -1 unnamed_device 27.1 MiB 0.80 1715.79 960 12371 3218 7643 1510 66.0 MiB 0.09 0.00 4.12939 3.75349 -109.494 -3.75349 3.75349 0.40 0.000486926 0.000445391 0.034405 0.031575 -1 -1 -1 -1 36 2399 29 6.95648e+06 361892 648988. 2245.63 1.30 0.150994 0.133659 26050 158493 -1 2124 24 1309 2223 188987 40183 3.40282 3.40282 -112.56 -3.40282 0 0 828058. 2865.25 0.05 0.07 0.16 -1 -1 0.05 0.0259554 0.0230849 73 55 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_117.v common 14.26 vpr 66.24 MiB -1 -1 0.21 21568 1 0.03 -1 -1 33688 -1 -1 16 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67828 32 32 393 312 1 205 80 17 17 289 -1 unnamed_device 27.3 MiB 1.36 2227.78 1203 6100 1354 4308 438 66.2 MiB 0.06 0.00 5.00201 4.60106 -151.549 -4.60106 4.60106 0.40 0.00059454 0.000546421 0.023599 0.0217378 -1 -1 -1 -1 38 3032 28 6.95648e+06 231611 678818. 2348.85 10.89 0.292051 0.25604 26626 170182 -1 2502 26 2348 3415 351224 94993 4.49752 4.49752 -159.436 -4.49752 0 0 902133. 3121.57 0.05 0.12 0.15 -1 -1 0.05 0.0325418 0.0291218 86 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_118.v common 3.51 vpr 66.04 MiB -1 -1 0.16 21096 1 0.03 -1 -1 33424 -1 -1 14 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67628 31 32 229 197 1 137 77 17 17 289 -1 unnamed_device 26.8 MiB 0.63 1573.72 789 7738 2349 3877 1512 66.0 MiB 0.05 0.00 3.62318 3.27643 -101.711 -3.27643 3.27643 0.40 0.00041061 0.000377042 0.0206251 0.0189423 -1 -1 -1 -1 34 1944 27 6.95648e+06 202660 618332. 2139.56 1.04 0.110768 0.0972299 25762 151098 -1 1657 22 990 1577 151209 32013 3.17312 3.17312 -112.749 -3.17312 0 0 787024. 2723.27 0.05 0.06 0.13 -1 -1 0.05 0.0195373 0.0174351 54 4 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_119.v common 9.54 vpr 66.66 MiB -1 -1 0.19 21760 1 0.03 -1 -1 33444 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68264 32 32 412 334 1 182 92 17 17 289 -1 unnamed_device 27.1 MiB 0.60 2584.84 779 15410 4873 7828 2709 66.7 MiB 0.11 0.00 4.99926 3.90964 -132.617 -3.90964 3.90964 0.39 0.000570248 0.000520742 0.0461058 0.0421637 -1 -1 -1 -1 44 2587 43 6.95648e+06 405319 787024. 2723.27 6.92 0.307824 0.270125 27778 195446 -1 1939 24 1609 2244 191346 50758 4.07152 4.07152 -143.499 -4.07152 0 0 997811. 3452.63 0.06 0.08 0.17 -1 -1 0.06 0.0309532 0.0276718 84 90 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_120.v common 6.37 vpr 66.07 MiB -1 -1 0.18 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68084 32 32 360 293 1 172 90 17 17 289 -1 unnamed_device 27.1 MiB 0.81 1853.05 1069 14562 4604 8437 1521 66.5 MiB 0.10 0.00 3.91173 3.53583 -120.704 -3.53583 3.53583 0.40 0.00054191 0.000495906 0.0412849 0.0377285 -1 -1 -1 -1 36 2639 39 6.95648e+06 376368 648988. 2245.63 4.20 0.247835 0.217537 26050 158493 -1 2207 31 1531 2309 242940 67507 3.38327 3.38327 -125.645 -3.38327 0 0 828058. 2865.25 0.05 0.10 0.14 -1 -1 0.05 0.033609 0.0298275 78 60 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_122.v common 5.31 vpr 66.75 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33396 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68348 32 32 396 299 1 227 83 17 17 289 -1 unnamed_device 27.3 MiB 1.52 2452.15 1278 10883 3044 6597 1242 66.7 MiB 0.10 0.00 6.40588 5.67799 -169.514 -5.67799 5.67799 0.40 0.000595413 0.00054646 0.0396421 0.0364573 -1 -1 -1 -1 42 3157 23 6.95648e+06 275038 744469. 2576.02 1.67 0.176527 0.157392 27202 183097 -1 2714 35 2694 3788 394527 125732 4.9392 4.9392 -169.567 -4.9392 0 0 949917. 3286.91 0.06 0.16 0.16 -1 -1 0.06 0.0431151 0.0385084 95 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_123.v common 4.16 vpr 65.97 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33672 -1 -1 13 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67556 30 32 224 207 1 132 75 17 17 289 -1 unnamed_device 26.6 MiB 0.95 1627 598 12241 5372 6458 411 66.0 MiB 0.07 0.00 2.90706 2.40586 -87.9482 -2.40586 2.40586 0.40 0.00036752 0.000335124 0.0305603 0.0279236 -1 -1 -1 -1 40 1508 30 6.95648e+06 188184 706193. 2443.58 1.33 0.118971 0.104669 26914 176310 -1 1331 20 901 1144 111930 30811 2.88623 2.88623 -98.6954 -2.88623 0 0 926341. 3205.33 0.05 0.05 0.16 -1 -1 0.05 0.0177094 0.0158242 51 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_124.v common 4.67 vpr 66.15 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33484 -1 -1 12 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67740 30 32 286 239 1 137 74 17 17 289 -1 unnamed_device 27.0 MiB 1.42 1634.53 584 10304 2805 7001 498 66.2 MiB 0.07 0.00 3.45258 3.27614 -105.411 -3.27614 3.27614 0.40 0.000442734 0.000405762 0.0316376 0.0289534 -1 -1 -1 -1 34 1944 38 6.95648e+06 173708 618332. 2139.56 1.37 0.143419 0.126166 25762 151098 -1 1413 22 1179 1705 141397 34783 3.09482 3.09482 -117.715 -3.09482 0 0 787024. 2723.27 0.05 0.06 0.13 -1 -1 0.05 0.0217502 0.0193742 56 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 3.59 vpr 66.44 MiB -1 -1 0.16 21376 1 0.03 -1 -1 33652 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68036 32 32 296 247 1 152 83 17 17 289 -1 unnamed_device 27.0 MiB 0.17 1728.54 922 8723 2565 5365 793 66.4 MiB 0.06 0.00 3.55445 2.9873 -113.256 -2.9873 2.9873 0.41 0.000466015 0.000422705 0.0245788 0.0224403 -1 -1 -1 -1 40 2197 27 6.95648e+06 275038 706193. 2443.58 1.49 0.135937 0.11993 26914 176310 -1 2042 23 1349 2303 218886 48209 3.19827 3.19827 -121.7 -3.19827 0 0 926341. 3205.33 0.05 0.08 0.16 -1 -1 0.05 0.0241167 0.0214186 65 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_126.v common 2.58 vpr 65.86 MiB -1 -1 0.17 20960 1 0.03 -1 -1 33956 -1 -1 18 25 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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3.81054 -129.805 -3.81054 3.81054 0.40 0.000544329 0.000499283 0.0320642 0.0293185 -1 -1 -1 -1 40 2820 23 6.95648e+06 202660 706193. 2443.58 1.45 0.155512 0.137327 26914 176310 -1 2463 25 1559 2688 247418 60274 4.07062 4.07062 -139.096 -4.07062 0 0 926341. 3205.33 0.05 0.09 0.16 -1 -1 0.05 0.0309136 0.0274566 75 72 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_128.v common 3.83 vpr 66.96 MiB -1 -1 0.20 21952 1 0.03 -1 -1 33304 -1 -1 29 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68572 31 32 409 331 1 183 92 17 17 289 -1 unnamed_device 27.4 MiB 0.64 1880.17 934 14582 5336 7343 1903 67.0 MiB 0.10 0.00 3.75413 3.54189 -123.861 -3.54189 3.54189 0.40 0.000588814 0.000538716 0.0442221 0.0405122 -1 -1 -1 -1 40 2135 23 6.95648e+06 419795 706193. 2443.58 1.17 0.16971 0.150096 26914 176310 -1 1941 23 1958 2686 194478 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1 0.03 -1 -1 33496 -1 -1 23 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67956 30 32 363 293 1 224 85 17 17 289 -1 unnamed_device 27.1 MiB 0.42 2539 1213 13663 4903 6549 2211 66.4 MiB 0.10 0.00 5.97457 4.74455 -148.167 -4.74455 4.74455 0.41 0.000528115 0.0004838 0.0419132 0.0384455 -1 -1 -1 -1 38 2904 29 6.99608e+06 338461 678818. 2348.85 1.77 0.169895 0.150516 26626 170182 -1 2475 23 2204 3166 262316 53855 4.3292 4.3292 -149.244 -4.3292 0 0 902133. 3121.57 0.05 0.08 0.15 -1 -1 0.05 0.0275821 0.0246982 99 63 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_003.v common 3.78 vpr 65.79 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33512 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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5.42531 4.05748 -115.939 -4.05748 4.05748 0.46 0.000498912 0.000457319 0.0492693 0.0453299 -1 -1 -1 -1 36 2604 27 6.99608e+06 279598 648988. 2245.63 1.57 0.166458 0.148312 26050 158493 -1 1796 20 1431 2220 152925 38511 3.99626 3.99626 -126.688 -3.99626 0 0 828058. 2865.25 0.05 0.06 0.14 -1 -1 0.05 0.0254607 0.02284 79 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_005.v common 13.33 vpr 66.52 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33612 -1 -1 16 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68112 32 32 336 268 1 193 80 17 17 289 -1 unnamed_device 27.0 MiB 0.46 2057.66 952 12464 3721 7118 1625 66.5 MiB 0.10 0.00 5.56057 4.88167 -146.243 -4.88167 4.88167 0.40 0.000550685 0.000507975 0.0400858 0.036749 -1 -1 -1 -1 40 2892 45 6.99608e+06 235451 706193. 2443.58 10.88 0.297882 0.262117 26914 176310 -1 2360 24 1726 2913 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67828 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 26.8 MiB 0.19 1776.46 919 11547 2651 7976 920 66.2 MiB 0.08 0.00 3.1255 2.7565 -95.0074 -2.7565 2.7565 0.40 0.000462139 0.000415195 0.0290177 0.0264754 -1 -1 -1 -1 36 2309 50 6.99608e+06 397324 648988. 2245.63 1.67 0.150728 0.132718 26050 158493 -1 1978 22 1218 2212 171223 38751 2.65381 2.65381 -102.167 -2.65381 0 0 828058. 2865.25 0.05 0.07 0.14 -1 -1 0.05 0.0225643 0.0200958 69 4 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_009.v common 4.00 vpr 66.38 MiB -1 -1 0.18 21568 1 0.04 -1 -1 33676 -1 -1 18 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67968 31 32 317 271 1 204 81 17 17 289 -1 unnamed_device 27.0 MiB 0.38 2338 1082 14256 5263 7162 1831 66.4 MiB 0.11 0.00 4.24759 3.13884 -116.913 -3.13884 3.13884 0.40 0.000577274 0.000536877 0.0498723 0.0463397 -1 -1 -1 -1 40 2502 31 6.99608e+06 264882 706193. 2443.58 1.61 0.187656 0.168639 26914 176310 -1 2233 22 1689 2280 192202 40085 3.05882 3.05882 -122.616 -3.05882 0 0 926341. 3205.33 0.06 0.07 0.16 -1 -1 0.06 0.0238392 0.0213232 83 64 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_010.v common 3.98 vpr 66.26 MiB -1 -1 0.16 21416 1 0.03 -1 -1 33628 -1 -1 15 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67852 32 32 298 248 1 181 79 17 17 289 -1 unnamed_device 26.8 MiB 0.40 1862.66 1015 12247 3678 6923 1646 66.3 MiB 0.08 0.00 3.99837 3.64037 -128.737 -3.64037 3.64037 0.40 0.000489929 0.000430801 0.0363812 0.0332364 -1 -1 -1 -1 34 2533 32 6.99608e+06 220735 618332. 2139.56 1.69 0.147185 0.12987 25762 151098 -1 2146 19 1516 1997 164767 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0.16 21568 1 0.03 -1 -1 33276 -1 -1 14 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67624 32 32 276 237 1 165 78 17 17 289 -1 unnamed_device 26.8 MiB 0.40 1950.5 725 8212 1860 5677 675 66.0 MiB 0.06 0.00 4.10243 3.37048 -107.801 -3.37048 3.37048 0.41 0.000432639 0.000394723 0.0238882 0.0218302 -1 -1 -1 -1 38 2443 48 6.99608e+06 206020 678818. 2348.85 1.64 0.142141 0.12464 26626 170182 -1 1781 21 1241 1639 121264 31618 3.06712 3.06712 -115.463 -3.06712 0 0 902133. 3121.57 0.05 0.06 0.15 -1 -1 0.05 0.0214999 0.0192173 65 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 4.06 vpr 65.82 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33968 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67396 32 32 344 272 1 201 82 17 17 289 -1 unnamed_device 26.7 MiB 0.47 2682.74 954 13076 5089 6303 1684 65.8 MiB 0.11 0.00 4.83632 3.86972 -128.357 -3.86972 3.86972 0.41 0.000514875 0.000470707 0.0416413 0.0381935 -1 -1 -1 -1 42 2795 25 6.99608e+06 264882 744469. 2576.02 1.58 0.165196 0.146307 27202 183097 -1 2199 24 1772 2664 231395 52184 3.34801 3.34801 -126.15 -3.34801 0 0 949917. 3286.91 0.05 0.08 0.16 -1 -1 0.05 0.0291676 0.0261746 85 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_014.v common 4.21 vpr 66.67 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33704 -1 -1 21 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68268 32 32 363 295 1 228 85 17 17 289 -1 unnamed_device 27.1 MiB 0.50 2692.2 1244 14407 4661 7812 1934 66.7 MiB 0.11 0.00 5.90964 4.79277 -149.984 -4.79277 4.79277 0.40 0.0005373 0.000492285 0.0442037 0.040416 -1 -1 -1 -1 40 2811 20 6.99608e+06 309029 706193. 2443.58 1.69 0.164977 0.146055 26914 176310 -1 2538 20 1946 2619 212273 44432 4.38451 4.38451 -153.65 -4.38451 0 0 926341. 3205.33 0.06 0.08 0.16 -1 -1 0.06 0.0255759 0.0228912 96 61 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_015.v common 2.96 vpr 65.77 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33688 -1 -1 17 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67352 29 32 248 215 1 150 78 17 17 289 -1 unnamed_device 26.6 MiB 0.52 1740.66 893 9706 2711 5534 1461 65.8 MiB 0.06 0.00 3.47743 2.91415 -94.4077 -2.91415 2.91415 0.40 0.000393649 0.000359826 0.0252981 0.0231698 -1 -1 -1 -1 32 2036 22 6.99608e+06 250167 586450. 2029.24 0.61 0.0788945 0.0700011 25474 144626 -1 1646 20 1019 1427 101641 22220 2.71507 2.71507 -98.7671 -2.71507 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0191348 0.017113 62 27 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_016.v common 4.50 vpr 66.33 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33268 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67920 32 32 370 297 1 219 83 17 17 289 -1 unnamed_device 26.9 MiB 0.80 2362.64 1073 15563 6532 7835 1196 66.3 MiB 0.12 0.00 4.16944 3.57294 -125.244 -3.57294 3.57294 0.39 0.000548421 0.000502622 0.050523 0.0463051 -1 -1 -1 -1 38 2963 48 6.99608e+06 279598 678818. 2348.85 1.68 0.200995 0.178057 26626 170182 -1 2204 21 1887 2913 199419 44516 3.57851 3.57851 -131.037 -3.57851 0 0 902133. 3121.57 0.06 0.07 0.15 -1 -1 0.06 0.027032 0.024129 98 58 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_017.v common 3.85 vpr 65.68 MiB -1 -1 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4.37465 -123.584 -4.37465 4.37465 0.40 0.000464788 0.000424708 0.0305114 0.0280181 -1 -1 -1 -1 34 2652 24 6.99608e+06 250167 618332. 2139.56 1.66 0.13893 0.123047 25762 151098 -1 2217 22 1494 2515 241172 49180 3.78976 3.78976 -130.242 -3.78976 0 0 787024. 2723.27 0.05 0.08 0.13 -1 -1 0.05 0.0229297 0.0204355 66 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_025.v common 2.36 vpr 65.65 MiB -1 -1 0.15 21184 1 0.03 -1 -1 32996 -1 -1 10 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67224 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 26.6 MiB 0.09 1439.48 560 9374 3843 5323 208 65.6 MiB 0.05 0.00 2.54695 2.03911 -69.5392 -2.03911 2.03911 0.40 0.000313501 0.000278965 0.0202342 0.0183637 -1 -1 -1 -1 32 1253 27 6.99608e+06 147157 586450. 2029.24 0.51 0.0636669 0.0560859 25474 144626 -1 1084 17 554 676 57342 13979 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1 0.03 -1 -1 33616 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67672 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 26.5 MiB 0.17 1823.66 770 8047 1794 5817 436 66.1 MiB 0.06 0.00 3.17834 2.84195 -96.8757 -2.84195 2.84195 0.40 0.000545234 0.000489322 0.0218086 0.0198967 -1 -1 -1 -1 38 2286 24 6.99608e+06 397324 678818. 2348.85 1.45 0.134959 0.11927 26626 170182 -1 1846 20 1304 2290 140400 35421 2.96851 2.96851 -105.541 -2.96851 0 0 902133. 3121.57 0.05 0.06 0.15 -1 -1 0.05 0.0215709 0.0192837 77 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_028.v common 4.76 vpr 66.45 MiB -1 -1 0.17 21760 1 0.03 -1 -1 33456 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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3.74453 3.11176 -114.352 -3.11176 3.11176 0.40 0.000443959 0.000406484 0.0288662 0.0264582 -1 -1 -1 -1 34 2359 22 6.99608e+06 206020 618332. 2139.56 1.03 0.12666 0.111541 25762 151098 -1 2040 23 1396 2031 159719 34924 3.14212 3.14212 -122.708 -3.14212 0 0 787024. 2723.27 0.05 0.06 0.13 -1 -1 0.05 0.0235693 0.0210016 68 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_030.v common 8.22 vpr 65.78 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33872 -1 -1 16 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67356 30 32 262 227 1 160 78 17 17 289 -1 unnamed_device 26.4 MiB 0.29 1816.96 788 8212 1940 5916 356 65.8 MiB 0.07 0.00 4.36766 3.76823 -111.393 -3.76823 3.76823 0.41 0.00041549 0.000380289 0.0231091 0.0211332 -1 -1 -1 -1 32 2632 47 6.99608e+06 235451 586450. 2029.24 5.99 0.203225 0.177847 25474 144626 -1 2004 26 1364 2106 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3.0305 -101.634 -3.0305 3.0305 0.40 0.000438884 0.000400798 0.0377231 0.0345516 -1 -1 -1 -1 34 2394 43 6.99608e+06 264882 618332. 2139.56 1.49 0.153963 0.135797 25762 151098 -1 1866 20 1335 1783 151180 34619 2.90282 2.90282 -102.948 -2.90282 0 0 787024. 2723.27 0.05 0.06 0.13 -1 -1 0.05 0.0213603 0.0191137 75 54 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_035.v common 4.44 vpr 66.50 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33868 -1 -1 21 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68092 32 32 367 282 1 214 85 17 17 289 -1 unnamed_device 26.8 MiB 0.37 2522.83 1172 14035 4232 7971 1832 66.5 MiB 0.11 0.00 4.99868 4.08568 -124.995 -4.08568 4.08568 0.40 0.000549704 0.000501945 0.0444241 0.0406074 -1 -1 -1 -1 36 3145 22 6.99608e+06 309029 648988. 2245.63 2.08 0.172169 0.152719 26050 158493 -1 2479 23 1718 2753 202121 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3.0623 -104.163 -3.0623 3.0623 0.41 0.000420067 0.000385035 0.0220681 0.0202486 -1 -1 -1 -1 32 2111 32 6.99608e+06 206020 586450. 2029.24 0.71 0.0866925 0.0766174 25474 144626 -1 1852 20 1077 1450 120781 26826 3.31142 3.31142 -117.221 -3.31142 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0193393 0.0172765 65 28 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_045.v common 3.92 vpr 66.39 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33508 -1 -1 18 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67980 31 32 337 267 1 199 81 17 17 289 -1 unnamed_device 26.8 MiB 0.44 2145.79 1115 11106 4094 5276 1736 66.4 MiB 0.09 0.00 4.77304 4.27184 -135.826 -4.27184 4.27184 0.40 0.000508267 0.000464878 0.0352541 0.0323616 -1 -1 -1 -1 44 2697 25 6.99608e+06 264882 787024. 2723.27 1.50 0.152635 0.135017 27778 195446 -1 2120 21 1262 1981 149067 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0.17 21376 1 0.03 -1 -1 33508 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67564 32 32 291 230 1 160 83 17 17 289 -1 unnamed_device 26.6 MiB 0.33 1772.6 1011 10343 3054 6149 1140 66.0 MiB 0.08 0.00 4.52137 4.01417 -123.961 -4.01417 4.01417 0.40 0.000466775 0.00042245 0.0292141 0.0267684 -1 -1 -1 -1 36 2627 27 6.99608e+06 279598 648988. 2245.63 2.26 0.139351 0.123026 26050 158493 -1 2246 27 1497 2733 298227 86162 3.91606 3.91606 -131.254 -3.91606 0 0 828058. 2865.25 0.05 0.11 0.14 -1 -1 0.05 0.0283199 0.0253161 70 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_048.v common 4.36 vpr 66.52 MiB -1 -1 0.18 21508 1 0.03 -1 -1 33596 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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4.47599 3.61653 -127.814 -3.61653 3.61653 0.42 0.000538038 0.000492374 0.0457012 0.0417057 -1 -1 -1 -1 34 3482 45 6.99608e+06 309029 618332. 2139.56 2.11 0.192621 0.169896 25762 151098 -1 2670 20 1670 2442 197737 43022 3.59376 3.59376 -134.576 -3.59376 0 0 787024. 2723.27 0.05 0.07 0.14 -1 -1 0.05 0.0264462 0.0237716 94 55 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_050.v common 3.96 vpr 66.62 MiB -1 -1 0.18 21684 1 0.03 -1 -1 33676 -1 -1 22 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68220 32 32 382 305 1 237 86 17 17 289 -1 unnamed_device 27.1 MiB 0.42 2390.67 1306 9725 3245 4874 1606 66.6 MiB 0.08 0.00 4.47137 3.65053 -130.846 -3.65053 3.65053 0.40 0.000564083 0.000503358 0.0315777 0.0289647 -1 -1 -1 -1 40 3093 27 6.99608e+06 323745 706193. 2443.58 1.55 0.162431 0.14362 26914 176310 -1 2643 22 2052 2804 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3.3589 2.9481 -106.495 -2.9481 2.9481 0.39 0.00043285 0.000395751 0.024087 0.022114 -1 -1 -1 -1 32 1986 23 6.99608e+06 235451 586450. 2029.24 0.68 0.0810053 0.0718746 25474 144626 -1 1818 21 1207 1848 144119 31724 2.97567 2.97567 -114.332 -2.97567 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0198465 0.017666 58 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_065.v common 4.48 vpr 66.08 MiB -1 -1 0.17 21564 1 0.03 -1 -1 33520 -1 -1 17 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67668 30 32 278 235 1 168 79 17 17 289 -1 unnamed_device 26.4 MiB 0.34 1881.63 846 11740 4899 6478 363 66.1 MiB 0.08 0.00 3.88477 3.61627 -115.385 -3.61627 3.61627 0.40 0.000435594 0.000397981 0.0328011 0.0300331 -1 -1 -1 -1 34 2626 42 6.99608e+06 250167 618332. 2139.56 2.25 0.150231 0.132441 25762 151098 -1 1930 22 1548 2150 173949 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1 0.03 -1 -1 33624 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67840 32 32 358 289 1 214 83 17 17 289 -1 unnamed_device 26.8 MiB 0.55 2512.06 1102 12323 3030 8331 962 66.2 MiB 0.10 0.00 5.76244 4.57197 -150.669 -4.57197 4.57197 0.40 0.000533643 0.000488963 0.039316 0.0360107 -1 -1 -1 -1 40 2617 23 6.99608e+06 279598 706193. 2443.58 1.18 0.158879 0.140457 26914 176310 -1 2263 20 1664 2404 159920 36281 4.4118 4.4118 -149.852 -4.4118 0 0 926341. 3205.33 0.05 0.07 0.16 -1 -1 0.05 0.0258331 0.0232609 93 54 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_068.v common 5.10 vpr 66.68 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33780 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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4.43837 3.56127 -113.067 -3.56127 3.56127 0.40 0.000435584 0.000399125 0.0224384 0.0206091 -1 -1 -1 -1 38 2164 36 6.99608e+06 191304 678818. 2348.85 1.44 0.129836 0.114177 26626 170182 -1 1847 21 1125 1512 114209 25335 3.29786 3.29786 -114.972 -3.29786 0 0 902133. 3121.57 0.05 0.05 0.15 -1 -1 0.05 0.0214946 0.0191912 65 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_070.v common 3.96 vpr 65.71 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33700 -1 -1 17 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67284 31 32 319 272 1 200 80 17 17 289 -1 unnamed_device 27.0 MiB 0.46 2059 1143 8680 2684 4726 1270 65.7 MiB 0.07 0.00 3.74443 3.36163 -119.008 -3.36163 3.36163 0.40 0.000471995 0.000430878 0.0264411 0.0241839 -1 -1 -1 -1 36 2725 29 6.99608e+06 250167 648988. 2245.63 1.58 0.140656 0.123801 26050 158493 -1 2415 23 1788 2474 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0.18 21568 1 0.03 -1 -1 33636 -1 -1 20 28 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67648 28 32 277 229 1 167 80 17 17 289 -1 unnamed_device 26.6 MiB 0.31 2171.73 750 13324 5641 6785 898 66.1 MiB 0.09 0.00 4.60235 3.68935 -102.007 -3.68935 3.68935 0.40 0.000430364 0.000392765 0.0378367 0.0345911 -1 -1 -1 -1 38 2095 46 6.99608e+06 294314 678818. 2348.85 2.37 0.15747 0.138842 26626 170182 -1 1637 20 1275 2053 133456 31957 3.86712 3.86712 -107.152 -3.86712 0 0 902133. 3121.57 0.05 0.06 0.15 -1 -1 0.05 0.0217607 0.019446 70 27 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_073.v common 4.12 vpr 66.43 MiB -1 -1 0.18 21376 1 0.03 -1 -1 33588 -1 -1 18 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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21776 1 0.03 -1 -1 33988 -1 -1 19 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68412 31 32 340 275 1 195 82 17 17 289 -1 unnamed_device 27.0 MiB 0.70 2485.22 1077 6846 1660 4720 466 66.8 MiB 0.06 0.00 5.99233 5.0824 -146.792 -5.0824 5.0824 0.40 0.000528306 0.000484687 0.0233996 0.0214877 -1 -1 -1 -1 36 2949 36 6.99608e+06 279598 648988. 2245.63 1.97 0.152936 0.134832 26050 158493 -1 2436 25 1611 2368 219315 58630 4.22141 4.22141 -143.659 -4.22141 0 0 828058. 2865.25 0.05 0.09 0.14 -1 -1 0.05 0.0286536 0.0255646 87 47 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_083.v common 4.37 vpr 66.81 MiB -1 -1 0.19 21572 1 0.03 -1 -1 33588 -1 -1 23 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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5.91884 4.65647 -145.605 -4.65647 4.65647 0.39 0.000543001 0.000497332 0.0425035 0.038839 -1 -1 -1 -1 58 2339 29 6.99608e+06 279598 997811. 3452.63 1.56 0.170784 0.151206 30370 251734 -1 1947 23 1549 2349 189783 40720 4.15385 4.15385 -138.843 -4.15385 0 0 1.25153e+06 4330.55 0.07 0.07 0.23 -1 -1 0.07 0.0282687 0.0253247 94 57 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_085.v common 3.96 vpr 66.81 MiB -1 -1 0.20 21764 1 0.03 -1 -1 33464 -1 -1 23 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68412 29 32 378 310 1 232 84 17 17 289 -1 unnamed_device 27.1 MiB 0.53 2249.72 1133 10332 4059 5536 737 66.8 MiB 0.08 0.00 4.37595 3.76735 -122.856 -3.76735 3.76735 0.40 0.000552259 0.000506996 0.0332651 0.0305183 -1 -1 -1 -1 40 2918 21 6.99608e+06 338461 706193. 2443.58 1.45 0.153546 0.135741 26914 176310 -1 2367 22 1494 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3.61613 3.25618 -100.635 -3.25618 3.25618 0.40 0.000430011 0.000392849 0.030564 0.0279533 -1 -1 -1 -1 40 1864 45 6.99608e+06 191304 706193. 2443.58 1.46 0.143334 0.126342 26914 176310 -1 1561 25 1244 1653 120205 30029 3.41867 3.41867 -112.985 -3.41867 0 0 926341. 3205.33 0.05 0.06 0.16 -1 -1 0.05 0.0237753 0.0211466 66 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_090.v common 2.86 vpr 65.73 MiB -1 -1 0.16 20992 1 0.03 -1 -1 33812 -1 -1 16 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67308 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 26.4 MiB 0.18 1536.9 858 8360 2256 5168 936 65.7 MiB 0.06 0.00 3.61893 3.28943 -106.361 -3.28943 3.28943 0.41 0.000402366 0.000367962 0.0224838 0.0206102 -1 -1 -1 -1 32 2072 26 6.99608e+06 235451 586450. 2029.24 0.83 0.0812806 0.0719055 25474 144626 -1 1856 19 1171 1959 154991 34293 3.14792 3.14792 -114.535 -3.14792 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0195495 0.0173998 59 4 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_091.v common 4.54 vpr 66.56 MiB -1 -1 0.18 21756 1 0.03 -1 -1 33684 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68156 32 32 348 274 1 209 82 17 17 289 -1 unnamed_device 26.8 MiB 0.44 2619 1051 8270 2110 5627 533 66.6 MiB 0.07 0.00 4.98867 4.02312 -135.346 -4.02312 4.02312 0.40 0.000536357 0.000492547 0.0278296 0.0255611 -1 -1 -1 -1 40 2752 48 6.99608e+06 264882 706193. 2443.58 2.14 0.16914 0.149314 26914 176310 -1 2412 21 1981 2778 221710 49503 4.01046 4.01046 -144.849 -4.01046 0 0 926341. 3205.33 0.05 0.08 0.16 -1 -1 0.05 0.026789 0.0240545 85 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_092.v common 3.84 vpr 66.57 MiB -1 -1 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0.19 21444 1 0.03 -1 -1 33652 -1 -1 21 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68232 31 32 365 296 1 229 84 17 17 289 -1 unnamed_device 27.1 MiB 0.45 2811.56 1262 12894 3886 6900 2108 66.6 MiB 0.10 0.00 6.59169 5.46783 -160.186 -5.46783 5.46783 0.40 0.000532634 0.000488796 0.0407674 0.0373669 -1 -1 -1 -1 40 2874 28 6.99608e+06 309029 706193. 2443.58 1.93 0.167833 0.148854 26914 176310 -1 2401 22 2013 2891 213884 45949 4.54281 4.54281 -157.549 -4.54281 0 0 926341. 3205.33 0.05 0.08 0.16 -1 -1 0.05 0.0279005 0.0250225 97 64 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_098.v common 3.48 vpr 66.51 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33548 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68108 32 32 331 280 1 215 82 17 17 289 -1 unnamed_device 26.7 MiB 0.45 2580.32 1220 8448 2298 5647 503 66.5 MiB 0.07 0.00 4.4353 3.55199 -133.806 -3.55199 3.55199 0.40 0.000489184 0.000448929 0.0258235 0.0236961 -1 -1 -1 -1 36 2753 24 6.99608e+06 264882 648988. 2245.63 1.14 0.134549 0.118386 26050 158493 -1 2346 21 1724 2226 174140 38058 3.49956 3.49956 -137.622 -3.49956 0 0 828058. 2865.25 0.05 0.06 0.14 -1 -1 0.05 0.0237757 0.0212481 86 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_099.v common 4.04 vpr 66.54 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33440 -1 -1 17 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68132 32 32 326 263 1 198 81 17 17 289 -1 unnamed_device 26.8 MiB 0.40 2007.91 915 11806 4558 6015 1233 66.5 MiB 0.09 0.00 4.69498 4.19833 -126.153 -4.19833 4.19833 0.40 0.000822698 0.000752881 0.03786 0.0345903 -1 -1 -1 -1 44 2540 49 6.99608e+06 250167 787024. 2723.27 1.68 0.167649 0.147934 27778 195446 -1 1804 19 1192 1636 115903 27473 3.77352 3.77352 -123.719 -3.77352 0 0 997811. 3452.63 0.06 0.05 0.17 -1 -1 0.06 0.0221567 0.0199308 80 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_100.v common 4.04 vpr 66.72 MiB -1 -1 0.19 21588 1 0.03 -1 -1 33372 -1 -1 21 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68324 31 32 373 294 1 216 84 17 17 289 -1 unnamed_device 27.1 MiB 0.49 2762.08 1151 14907 5290 7728 1889 66.7 MiB 0.13 0.00 5.40098 4.12378 -127.257 -4.12378 4.12378 0.42 0.000583662 0.000536691 0.0513279 0.0471593 -1 -1 -1 -1 40 2607 25 6.99608e+06 309029 706193. 2443.58 1.46 0.177266 0.157433 26914 176310 -1 2325 22 1845 2733 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68420 32 32 386 307 1 240 85 17 17 289 -1 unnamed_device 27.3 MiB 0.47 2544.17 1330 10687 2581 6972 1134 66.8 MiB 0.09 0.00 4.10857 3.66363 -131.207 -3.66363 3.66363 0.40 0.000574639 0.000527043 0.0360721 0.0330278 -1 -1 -1 -1 36 3429 39 6.99608e+06 309029 648988. 2245.63 4.62 0.250314 0.219975 26050 158493 -1 2785 23 2245 3111 286375 61519 3.57417 3.57417 -136.233 -3.57417 0 0 828058. 2865.25 0.05 0.09 0.14 -1 -1 0.05 0.0295385 0.0264527 102 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 2.96 vpr 65.80 MiB -1 -1 0.16 21320 1 0.03 -1 -1 33788 -1 -1 18 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67380 29 32 269 229 1 166 79 17 17 289 -1 unnamed_device 26.5 MiB 0.37 1756.97 750 8867 3422 4589 856 65.8 MiB 0.06 0.00 4.44376 3.81986 -111.589 -3.81986 3.81986 0.40 0.000436774 0.00039985 0.0241024 0.0220692 -1 -1 -1 -1 32 2228 31 6.99608e+06 264882 586450. 2029.24 0.74 0.0894298 0.0791101 25474 144626 -1 1667 22 1606 2144 164445 35623 3.43772 3.43772 -115.848 -3.43772 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0214314 0.0191349 68 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 5.48 vpr 66.42 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33588 -1 -1 15 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68016 32 32 310 266 1 186 79 17 17 289 -1 unnamed_device 26.6 MiB 0.45 2114 1072 10388 2745 6664 979 66.4 MiB 0.08 0.00 4.23779 3.56989 -126.273 -3.56989 3.56989 0.41 0.000520961 0.000457891 0.0316647 0.028983 -1 -1 -1 -1 36 2699 37 6.99608e+06 220735 648988. 2245.63 3.11 0.214649 0.188687 26050 158493 -1 2229 21 1547 2091 179736 39221 3.64986 3.64986 -132.942 -3.64986 0 0 828058. 2865.25 0.05 0.07 0.14 -1 -1 0.05 0.0241107 0.0215288 78 58 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_106.v common 4.04 vpr 66.57 MiB -1 -1 0.18 21548 1 0.03 -1 -1 33772 -1 -1 20 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68168 31 32 326 261 1 197 83 17 17 289 -1 unnamed_device 27.0 MiB 0.40 2462.69 1162 13763 5234 6995 1534 66.6 MiB 0.10 0.00 5.08188 4.09932 -130.497 -4.09932 4.09932 0.41 0.000500307 0.000458428 0.0408614 0.0373983 -1 -1 -1 -1 46 2358 22 6.99608e+06 294314 828058. 2865.25 1.65 0.151324 0.134002 28066 200906 -1 2124 17 1370 2011 124268 27371 3.74866 3.74866 -129.695 -3.74866 0 0 1.01997e+06 3529.29 0.06 0.05 0.18 -1 -1 0.06 0.0212377 0.0191112 82 33 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_107.v common 3.66 vpr 65.91 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67224 32 32 278 238 1 178 79 17 17 289 -1 unnamed_device 26.7 MiB 0.44 2344 802 11233 4665 6317 251 65.6 MiB 0.08 0.00 4.87466 3.81986 -117.727 -3.81986 3.81986 0.40 0.000444014 0.000405875 0.0316948 0.0289349 -1 -1 -1 -1 36 2662 38 6.99608e+06 220735 648988. 2245.63 2.38 0.147565 0.12997 26050 158493 -1 1945 22 1737 2335 205163 46980 3.35647 3.35647 -125.635 -3.35647 0 0 828058. 2865.25 0.05 0.07 0.14 -1 -1 0.05 0.0223859 0.0200184 70 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 10.90 vpr 66.87 MiB -1 -1 0.19 21496 1 0.03 -1 -1 33612 -1 -1 22 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68472 31 32 373 300 1 230 85 17 17 289 -1 unnamed_device 27.2 MiB 0.43 2524.58 1290 13291 4296 7426 1569 66.9 MiB 0.11 0.00 5.14528 3.96644 -137.42 -3.96644 3.96644 0.40 0.000546002 0.000495708 0.0425745 0.0388214 -1 -1 -1 -1 40 2945 42 6.99608e+06 323745 706193. 2443.58 8.47 0.315484 0.276541 26914 176310 -1 2593 20 1936 2739 219535 46866 3.78255 3.78255 -145.663 -3.78255 0 0 926341. 3205.33 0.05 0.08 0.16 -1 -1 0.05 0.0265826 0.0239281 100 64 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_110.v common 3.35 vpr 65.91 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33564 -1 -1 15 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67488 31 32 265 230 1 170 78 17 17 289 -1 unnamed_device 26.6 MiB 0.37 1901 926 8378 2454 4499 1425 65.9 MiB 0.06 0.00 3.62338 3.26538 -103.352 -3.26538 3.26538 0.40 0.000415214 0.000380398 0.0232663 0.0213621 -1 -1 -1 -1 38 2049 20 6.99608e+06 220735 678818. 2348.85 1.11 0.114339 0.100601 26626 170182 -1 1809 21 1209 1714 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3.92883 3.42763 -115.198 -3.42763 3.42763 0.40 0.000453424 0.000415221 0.0349383 0.0320693 -1 -1 -1 -1 44 2260 49 6.99608e+06 220735 787024. 2723.27 1.87 0.156914 0.138365 27778 195446 -1 1939 20 1462 2114 176026 37248 3.13262 3.13262 -118.27 -3.13262 0 0 997811. 3452.63 0.06 0.06 0.17 -1 -1 0.06 0.0209652 0.0187769 70 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_115.v common 3.89 vpr 66.40 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33584 -1 -1 17 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67996 32 32 318 257 1 190 81 17 17 289 -1 unnamed_device 27.0 MiB 0.44 2008.49 1061 12156 3939 6984 1233 66.4 MiB 0.09 0.00 4.55868 4.12158 -127.831 -4.12158 4.12158 0.40 0.000485015 0.000441525 0.036549 0.0333556 -1 -1 -1 -1 36 2636 26 6.99608e+06 250167 648988. 2245.63 1.52 0.151708 0.134264 26050 158493 -1 2264 21 1654 2305 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0.20 21952 1 0.03 -1 -1 33836 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68420 32 32 393 312 1 234 83 17 17 289 -1 unnamed_device 27.3 MiB 0.54 2740.11 1187 12323 4386 6229 1708 66.8 MiB 0.11 0.00 6.3147 5.17003 -168.115 -5.17003 5.17003 0.40 0.000564746 0.000517958 0.0424674 0.0389787 -1 -1 -1 -1 46 3186 21 6.99608e+06 279598 828058. 2865.25 1.23 0.144623 0.128387 28066 200906 -1 2491 22 2174 3261 224343 48540 4.40635 4.40635 -161.33 -4.40635 0 0 1.01997e+06 3529.29 0.06 0.08 0.18 -1 -1 0.06 0.0289385 0.0259147 102 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_118.v common 3.43 vpr 65.63 MiB -1 -1 0.16 20992 1 0.03 -1 -1 33604 -1 -1 15 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67208 31 32 229 197 1 138 78 17 17 289 -1 unnamed_device 26.5 MiB 0.63 1665.37 866 10038 3879 5332 827 65.6 MiB 0.06 0.00 3.45398 3.07808 -95.6005 -3.07808 3.07808 0.40 0.000402208 0.000366342 0.0264614 0.0241888 -1 -1 -1 -1 34 1957 19 6.99608e+06 220735 618332. 2139.56 0.98 0.109624 0.0963388 25762 151098 -1 1727 19 948 1543 115724 25796 2.76232 2.76232 -99.9411 -2.76232 0 0 787024. 2723.27 0.05 0.05 0.13 -1 -1 0.05 0.0183073 0.0164545 55 4 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_119.v common 4.47 vpr 66.86 MiB -1 -1 0.19 21376 1 0.03 -1 -1 33608 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68460 32 32 412 334 1 258 87 17 17 289 -1 unnamed_device 27.1 MiB 0.48 3136.25 1376 11799 3682 6020 2097 66.9 MiB 0.10 0.00 6.25193 4.95808 -168.612 -4.95808 4.95808 0.40 0.000625422 0.000575265 0.0401248 0.036735 -1 -1 -1 -1 36 3619 37 6.99608e+06 338461 648988. 2245.63 2.01 0.191992 0.169905 26050 158493 -1 2910 20 2239 2839 225407 51024 5.3834 5.3834 -185.015 -5.3834 0 0 828058. 2865.25 0.05 0.08 0.14 -1 -1 0.05 0.0274497 0.0246365 114 90 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_120.v common 5.49 vpr 66.99 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33332 -1 -1 21 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68596 32 32 376 318 1 253 85 17 17 289 -1 unnamed_device 27.3 MiB 0.51 2503.82 1284 12919 4933 5948 2038 67.0 MiB 0.10 0.00 5.63182 4.45298 -163.199 -4.45298 4.45298 0.40 0.00055103 0.00049782 0.0406902 0.0370667 -1 -1 -1 -1 36 3534 41 6.99608e+06 309029 648988. 2245.63 2.98 0.183211 0.161633 26050 158493 -1 2786 22 2693 3443 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3.92803 -130.612 -3.92803 3.92803 0.40 0.000444945 0.000407082 0.0262114 0.0240202 -1 -1 -1 -1 34 2176 27 6.99608e+06 220735 618332. 2139.56 0.97 0.127477 0.112042 25762 151098 -1 1899 22 1246 1955 169232 36091 3.59731 3.59731 -136.68 -3.59731 0 0 787024. 2723.27 0.05 0.06 0.13 -1 -1 0.05 0.022299 0.0199139 70 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_125.v common 4.80 vpr 66.18 MiB -1 -1 0.17 20992 1 0.03 -1 -1 33652 -1 -1 15 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67768 32 32 296 247 1 182 79 17 17 289 -1 unnamed_device 26.8 MiB 0.34 1971.29 882 13261 5570 7431 260 66.2 MiB 0.09 0.00 4.19149 3.78235 -133.321 -3.78235 3.78235 0.40 0.000454618 0.000414054 0.0384596 0.0351383 -1 -1 -1 -1 38 2651 49 6.99608e+06 220735 678818. 2348.85 2.51 0.169543 0.149709 26626 170182 -1 2020 20 1450 2457 219315 48983 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0.03 -1 -1 33824 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68280 32 32 376 307 1 230 83 17 17 289 -1 unnamed_device 27.0 MiB 0.59 2657.85 1316 7463 1720 5150 593 66.7 MiB 0.07 0.00 4.40039 3.97548 -133.176 -3.97548 3.97548 0.40 0.00055875 0.000512318 0.0260869 0.0239621 -1 -1 -1 -1 38 3462 44 6.99608e+06 279598 678818. 2348.85 1.87 0.174002 0.153734 26626 170182 -1 2797 24 2179 3377 250295 53465 4.20392 4.20392 -145.444 -4.20392 0 0 902133. 3121.57 0.05 0.09 0.15 -1 -1 0.05 0.0301385 0.0269268 99 72 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_128.v common 4.93 vpr 66.76 MiB -1 -1 0.19 21376 1 0.03 -1 -1 34092 -1 -1 23 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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7.87598 -171.941 -7.87598 7.87598 0.40 0.000747841 0.000686021 0.033299 0.0304976 -1 -1 -1 -1 32 4122 48 6.79088e+06 282912 586450. 2029.24 1.52 0.167193 0.149491 24814 144142 -1 3384 26 1590 4354 315532 91570 6.90989 6.90989 -166.802 -6.90989 0 0 744469. 2576.02 0.05 0.13 0.13 -1 -1 0.05 0.0428618 0.0388623 141 188 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_037.v common 4.41 vpr 66.05 MiB -1 -1 0.23 21396 12 0.18 -1 -1 35904 -1 -1 22 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67632 31 32 241 273 1 167 85 17 17 289 -1 unnamed_device 26.4 MiB 1.34 2245.99 1124 11617 2830 7151 1636 66.0 MiB 0.09 0.00 9.13651 7.16673 -154.158 -7.16673 7.16673 0.41 0.000552441 0.000503388 0.0385391 0.0351395 -1 -1 -1 -1 32 2540 25 6.79088e+06 296384 586450. 2029.24 0.87 0.121318 0.10829 24814 144142 -1 2194 38 912 2526 247643 119222 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6.95498 -139.11 -6.95498 6.95498 0.40 0.000662899 0.0006039 0.0503753 0.0459106 -1 -1 -1 -1 36 2957 25 6.79088e+06 282912 648988. 2245.63 1.33 0.202315 0.180214 25390 158009 -1 2591 18 1136 3349 191755 44399 5.75396 5.75396 -131.866 -5.75396 0 0 828058. 2865.25 0.05 0.07 0.14 -1 -1 0.05 0.0297499 0.0270594 129 188 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_072.v common 3.98 vpr 65.54 MiB -1 -1 0.23 21560 11 0.25 -1 -1 36212 -1 -1 22 28 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67112 28 32 253 285 1 172 82 17 17 289 -1 unnamed_device 26.4 MiB 0.69 2569.59 974 5778 1226 4251 301 65.5 MiB 0.05 0.00 9.47421 6.55419 -124.806 -6.55419 6.55419 0.40 0.000605042 0.000552289 0.0231873 0.0212574 -1 -1 -1 -1 30 2829 21 6.79088e+06 296384 556674. 1926.21 1.14 0.110916 0.0988462 24526 138013 -1 2180 16 1052 3156 159340 38063 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8.03891 -164.154 -8.03891 8.03891 0.40 0.000866661 0.000791941 0.0454296 0.0413726 -1 -1 -1 -1 36 4720 50 6.79088e+06 390688 648988. 2245.63 2.63 0.304938 0.272575 25390 158009 -1 4022 18 1939 5882 349528 81642 7.24643 7.24643 -163.259 -7.24643 0 0 828058. 2865.25 0.05 0.12 0.14 -1 -1 0.05 0.04396 0.04031 194 286 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_097.v common 4.47 vpr 65.68 MiB -1 -1 0.27 21944 14 0.31 -1 -1 36736 -1 -1 21 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67256 31 32 277 309 1 194 84 17 17 289 -1 unnamed_device 26.8 MiB 0.58 2825.35 1259 8502 2170 5586 746 65.7 MiB 0.08 0.00 10.5434 8.40299 -170.106 -8.40299 8.40299 0.41 0.000691662 0.000634433 0.0364255 0.0332419 -1 -1 -1 -1 28 3607 48 6.79088e+06 282912 531479. 1839.03 1.58 0.169128 0.151324 23950 126010 -1 2799 19 1355 3498 182428 44663 7.5622 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7.00869 -152.842 -7.00869 7.00869 0.41 0.000663421 0.000604559 0.0448913 0.0408181 -1 -1 -1 -1 28 3899 44 6.79088e+06 323328 531479. 1839.03 2.64 0.172126 0.153244 23950 126010 -1 2955 20 1664 4630 280626 64993 6.12648 6.12648 -151.532 -6.12648 0 0 648988. 2245.63 0.04 0.10 0.12 -1 -1 0.04 0.0360719 0.0326906 135 194 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_112.v common 4.76 vpr 66.29 MiB -1 -1 0.28 22136 13 0.36 -1 -1 36824 -1 -1 22 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67884 31 32 282 314 1 210 85 17 17 289 -1 unnamed_device 26.7 MiB 0.94 2791.28 1262 11989 3047 7402 1540 66.3 MiB 0.11 0.00 9.30843 7.42893 -161.431 -7.42893 7.42893 0.40 0.000702752 0.000643386 0.0500698 0.0456667 -1 -1 -1 -1 30 3449 32 6.79088e+06 296384 556674. 1926.21 1.40 0.168962 0.151857 24526 138013 -1 2705 19 1433 4023 185362 45909 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6.48043 -132.63 -6.48043 6.48043 0.40 0.00066598 0.000611632 0.0212379 0.0194758 -1 -1 -1 -1 30 3018 42 6.79088e+06 309856 556674. 1926.21 6.01 0.259708 0.229649 24526 138013 -1 2480 18 1046 3154 159980 37082 5.63404 5.63404 -129.923 -5.63404 0 0 706193. 2443.58 0.04 0.07 0.12 -1 -1 0.04 0.0286893 0.0260925 118 158 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_117.v common 5.25 vpr 66.46 MiB -1 -1 0.28 22328 14 0.40 -1 -1 37156 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68056 32 32 318 350 1 238 89 17 17 289 -1 unnamed_device 26.9 MiB 0.84 3185.36 1427 9989 2338 6256 1395 66.5 MiB 0.10 0.00 11.6109 8.7465 -186.455 -8.7465 8.7465 0.41 0.000789328 0.000719601 0.0445066 0.040622 -1 -1 -1 -1 30 4195 34 6.79088e+06 336800 556674. 1926.21 1.93 0.183459 0.164897 24526 138013 -1 3114 19 1654 4325 208709 51804 7.58672 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7.48857 -162.185 -7.48857 7.48857 0.40 0.000712126 0.000651983 0.0243907 0.0223382 -1 -1 -1 -1 32 3332 43 6.79088e+06 282912 586450. 2029.24 0.99 0.146719 0.130861 24814 144142 -1 2752 17 1274 3805 210568 50438 6.37282 6.37282 -153.729 -6.37282 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.0317677 0.0289636 132 175 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_122.v common 5.86 vpr 66.05 MiB -1 -1 0.29 22328 15 0.62 -1 -1 36884 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67632 32 32 350 382 1 251 89 17 17 289 -1 unnamed_device 26.9 MiB 1.08 3569.3 1573 10583 2766 6384 1433 66.0 MiB 0.12 0.00 11.6887 9.43481 -197.257 -9.43481 9.43481 0.40 0.000932737 0.000839198 0.0525392 0.0479028 -1 -1 -1 -1 48 3820 22 6.79088e+06 336800 865456. 2994.66 1.92 0.263477 0.236303 27694 206865 -1 3410 19 1843 6055 331838 74371 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67604 32 32 264 296 1 193 87 17 17 289 -1 unnamed_device 26.3 MiB 0.61 2664.06 1204 6039 1295 4393 351 66.0 MiB 0.06 0.00 9.33663 7.42897 -167.088 -7.42897 7.42897 0.41 0.000650354 0.000595673 0.0255309 0.0233333 -1 -1 -1 -1 32 3186 39 6.79088e+06 309856 586450. 2029.24 1.12 0.1442 0.128438 24814 144142 -1 2600 14 1082 2781 153438 36660 6.37287 6.37287 -156.925 -6.37287 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0265263 0.0243786 122 170 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_126.v common 3.67 vpr 65.31 MiB -1 -1 0.20 21176 9 0.16 -1 -1 35920 -1 -1 21 25 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66876 25 32 183 215 1 134 78 17 17 289 -1 unnamed_device 25.8 MiB 0.58 1513.29 648 7216 2007 4704 505 65.3 MiB 0.05 0.00 5.889 5.1159 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4.36325 -122.998 -4.36325 4.36325 0.40 0.000470754 0.000430973 0.0400303 0.0366461 -1 -1 -1 -1 28 2792 23 6.87369e+06 293451 531479. 1839.03 1.78 0.18365 0.161509 24610 126494 -1 2295 19 1379 1769 136337 33864 4.21166 4.21166 -130.038 -4.21166 0 0 648988. 2245.63 0.04 0.06 0.11 -1 -1 0.04 0.0209954 0.0187895 118 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_004.v common 4.55 vpr 66.30 MiB -1 -1 0.18 21320 1 0.03 -1 -1 33448 -1 -1 29 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67892 29 32 308 248 1 172 90 17 17 289 -1 unnamed_device 26.3 MiB 1.35 2239.35 1008 10341 2953 6519 869 66.3 MiB 0.09 0.00 5.55862 4.60302 -124.431 -4.60302 4.60302 0.41 0.00049232 0.000453187 0.0273261 0.0249918 -1 -1 -1 -1 30 2105 21 6.87369e+06 405241 556674. 1926.21 1.28 0.154141 0.135494 25186 138497 -1 1848 19 1212 2219 131521 31021 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4.11555 3.57969 -107.766 -3.57969 3.57969 0.40 0.000448309 0.000407098 0.0280445 0.0254601 -1 -1 -1 -1 32 2056 21 6.87369e+06 461137 586450. 2029.24 0.55 0.0845142 0.0747479 25474 144626 -1 1863 18 869 1628 98904 24067 2.70166 2.70166 -100.41 -2.70166 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.018882 0.0167612 119 4 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_009.v common 5.31 vpr 66.09 MiB -1 -1 0.18 21452 1 0.03 -1 -1 33520 -1 -1 20 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67680 31 32 317 271 1 175 83 17 17 289 -1 unnamed_device 26.5 MiB 2.81 2074 1078 13943 4090 8084 1769 66.1 MiB 0.11 0.00 4.71896 3.59126 -121.465 -3.59126 3.59126 0.40 0.000464976 0.000424317 0.0384492 0.0351235 -1 -1 -1 -1 32 2363 25 6.87369e+06 279477 586450. 2029.24 0.58 0.103717 0.0922432 25474 144626 -1 1983 18 1062 1513 112397 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0.18 21568 1 0.03 -1 -1 33476 -1 -1 18 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67384 30 32 303 262 1 148 80 17 17 289 -1 unnamed_device 26.5 MiB 3.97 1634.57 812 11948 4351 5672 1925 65.8 MiB 0.08 0.00 4.23198 3.85608 -112.57 -3.85608 3.85608 0.41 0.000463725 0.000424232 0.0342554 0.0313823 -1 -1 -1 -1 32 1801 23 6.87369e+06 251529 586450. 2029.24 1.63 0.184974 0.161413 25474 144626 -1 1486 24 1140 1911 142615 34545 3.07926 3.07926 -108.637 -3.07926 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0231202 0.0204497 99 63 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_012.v common 5.96 vpr 65.82 MiB -1 -1 0.16 21184 1 0.03 -1 -1 33688 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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4.14663 -135.842 -4.14663 4.14663 0.40 0.000533394 0.000489461 0.037365 0.0342239 -1 -1 -1 -1 32 2731 23 6.87369e+06 349346 586450. 2029.24 1.65 0.185335 0.163244 25474 144626 -1 2140 20 1721 2652 168787 40643 2.94451 2.94451 -120.373 -2.94451 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0237111 0.0212024 139 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_014.v common 6.95 vpr 66.52 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33464 -1 -1 31 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68112 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 27.0 MiB 3.09 2511.11 980 18023 5207 10857 1959 66.5 MiB 0.16 0.00 5.95652 4.81568 -140.558 -4.81568 4.81568 0.40 0.000560391 0.000514078 0.0500378 0.0458405 -1 -1 -1 -1 28 2600 25 6.87369e+06 433189 531479. 1839.03 1.90 0.223522 0.196925 24610 126494 -1 2271 22 1778 2861 204487 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21760 1 0.03 -1 -1 33320 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68076 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 27.0 MiB 2.82 2351.99 1111 14908 5083 7307 2518 66.5 MiB 0.13 0.00 4.2467 3.7455 -126.337 -3.7455 3.7455 0.40 0.00054921 0.000504197 0.0445015 0.0407166 -1 -1 -1 -1 32 2713 20 6.87369e+06 335372 586450. 2029.24 0.64 0.114998 0.102546 25474 144626 -1 2239 24 1700 3012 211083 49218 3.22191 3.22191 -124.378 -3.22191 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.0280422 0.0248211 135 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 8.27 vpr 66.32 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33488 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67908 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 26.6 MiB 4.66 2594.57 1105 15639 5416 7563 2660 66.3 MiB 0.13 0.00 5.08229 4.17127 -135.424 -4.17127 4.17127 0.40 0.000524541 0.000480221 0.0449626 0.0411462 -1 -1 -1 -1 32 2751 23 6.87369e+06 321398 586450. 2029.24 1.64 0.201647 0.177611 25474 144626 -1 2178 20 1325 1895 123738 30131 3.10851 3.10851 -122.224 -3.10851 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.023241 0.0205467 136 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 5.80 vpr 66.18 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33436 -1 -1 29 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67768 32 32 323 276 1 156 93 17 17 289 -1 unnamed_device 26.4 MiB 3.31 2257.62 926 17103 5432 9461 2210 66.2 MiB 0.13 0.00 3.68501 2.85191 -105.908 -2.85191 2.85191 0.40 0.000490674 0.000447002 0.0427565 0.0390158 -1 -1 -1 -1 32 2002 22 6.87369e+06 405241 586450. 2029.24 0.58 0.106368 0.0945891 25474 144626 -1 1661 17 1142 1944 120028 29235 2.07352 2.07352 -97.0447 -2.07352 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0189586 0.0169034 110 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 4.13 vpr 65.66 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33476 -1 -1 15 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67240 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 26.5 MiB 0.95 1506.97 681 11976 4667 6344 965 65.7 MiB 0.07 0.00 2.88898 2.40568 -84.2035 -2.40568 2.40568 0.40 0.00036517 0.000333724 0.0284915 0.0260673 -1 -1 -1 -1 28 1383 18 6.87369e+06 209608 531479. 1839.03 1.39 0.131739 0.11548 24610 126494 -1 1256 17 631 890 62975 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3.13338 2.41583 -71.9717 -2.41583 2.41583 0.40 0.000328641 0.000287598 0.0181958 0.0165723 -1 -1 -1 -1 26 1284 21 6.87369e+06 251529 503264. 1741.40 0.46 0.0594057 0.05243 24322 120374 -1 1126 22 717 1085 75720 19389 2.17212 2.17212 -75.7209 -2.17212 0 0 618332. 2139.56 0.04 0.04 0.11 -1 -1 0.04 0.0158019 0.0139594 67 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 4.34 vpr 66.25 MiB -1 -1 0.17 21276 1 0.03 -1 -1 33248 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67844 32 32 285 227 1 169 88 17 17 289 -1 unnamed_device 26.6 MiB 1.68 2097.1 1049 14908 4450 8551 1907 66.3 MiB 0.12 0.00 5.2197 4.59222 -130.8 -4.59222 4.59222 0.40 0.000457864 0.000419048 0.0378562 0.0346655 -1 -1 -1 -1 32 2268 21 6.87369e+06 335372 586450. 2029.24 0.74 0.13058 0.116218 25474 144626 -1 1966 21 1268 2283 143914 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3.52778 -109.244 -3.52778 3.52778 0.40 0.000438909 0.00039274 0.0238418 0.0216635 -1 -1 -1 -1 30 1823 22 6.87369e+06 363320 556674. 1926.21 1.13 0.135302 0.118321 25186 138497 -1 1562 17 772 1405 72094 18599 2.84896 2.84896 -105.571 -2.84896 0 0 706193. 2443.58 0.05 0.04 0.12 -1 -1 0.05 0.01724 0.0154258 102 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 6.02 vpr 65.95 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33776 -1 -1 25 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67536 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 26.7 MiB 3.60 2244.68 863 12938 3817 7914 1207 66.0 MiB 0.10 0.00 3.77556 3.08002 -100.294 -3.08002 3.08002 0.41 0.000468216 0.000428507 0.032729 0.0299391 -1 -1 -1 -1 30 1838 22 6.87369e+06 349346 556674. 1926.21 0.54 0.091109 0.0808854 25186 138497 -1 1561 17 902 1386 82031 19933 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0.03 -1 -1 33612 -1 -1 40 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68228 32 32 391 311 1 194 104 17 17 289 -1 unnamed_device 27.1 MiB 4.27 2402.47 979 20356 6424 10825 3107 66.6 MiB 0.17 0.00 4.68095 3.99582 -132.692 -3.99582 3.99582 0.40 0.000602729 0.000553479 0.0535943 0.0486716 -1 -1 -1 -1 28 2877 31 6.87369e+06 558954 531479. 1839.03 1.93 0.239402 0.211171 24610 126494 -1 2129 21 1763 2863 175391 44569 3.13256 3.13256 -124.479 -3.13256 0 0 648988. 2245.63 0.04 0.07 0.12 -1 -1 0.04 0.0268316 0.0239133 149 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 5.26 vpr 65.85 MiB -1 -1 0.17 21436 1 0.03 -1 -1 33620 -1 -1 18 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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4.3461 3.7686 -123.743 -3.7686 3.7686 0.40 0.000533823 0.000488345 0.0418162 0.0382645 -1 -1 -1 -1 32 2620 20 6.87369e+06 363320 586450. 2029.24 0.63 0.1131 0.100854 25474 144626 -1 2210 20 1429 2447 155773 36552 3.00426 3.00426 -116.646 -3.00426 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0251834 0.0224984 136 61 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_039.v common 8.97 vpr 65.90 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33844 -1 -1 29 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67480 31 32 377 302 1 237 92 17 17 289 -1 unnamed_device 27.1 MiB 5.07 2915 1370 12926 3844 7737 1345 65.9 MiB 0.13 0.00 6.76692 5.51998 -168.096 -5.51998 5.51998 0.40 0.000564622 0.000517338 0.0377357 0.0344848 -1 -1 -1 -1 32 3289 25 6.87369e+06 405241 586450. 2029.24 1.90 0.229219 0.201958 25474 144626 -1 2687 20 2057 3048 204663 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1 0.03 -1 -1 33812 -1 -1 29 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68084 31 32 352 285 1 186 92 17 17 289 -1 unnamed_device 27.0 MiB 3.73 2134.83 1049 14996 4857 7380 2759 66.5 MiB 0.15 0.00 4.61893 4.13563 -128.666 -4.13563 4.13563 0.40 0.000524275 0.000481292 0.0457251 0.0418759 -1 -1 -1 -1 32 2599 19 6.87369e+06 405241 586450. 2029.24 0.61 0.112978 0.10069 25474 144626 -1 2043 20 1443 2422 155992 37550 2.96601 2.96601 -115.897 -2.96601 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0241124 0.021597 133 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 5.89 vpr 66.24 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33668 -1 -1 22 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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6.15708 4.89003 -155.777 -4.89003 4.89003 0.40 0.000645669 0.00059148 0.0598257 0.0547467 -1 -1 -1 -1 32 3164 48 6.87369e+06 558954 586450. 2029.24 1.89 0.283015 0.249894 25474 144626 -1 2370 19 1575 2581 160829 39724 3.82936 3.82936 -143.547 -3.82936 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0277139 0.0248627 173 87 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_044.v common 5.93 vpr 65.61 MiB -1 -1 0.17 21508 1 0.03 -1 -1 33492 -1 -1 20 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67188 31 32 261 225 1 148 83 17 17 289 -1 unnamed_device 26.3 MiB 2.43 1997.69 879 11603 3081 7322 1200 65.6 MiB 0.09 0.00 4.27085 3.55895 -107.565 -3.55895 3.55895 0.40 0.000432544 0.000395503 0.0287859 0.0263119 -1 -1 -1 -1 32 1897 27 6.87369e+06 279477 586450. 2029.24 1.55 0.148898 0.130006 25474 144626 -1 1731 20 1072 1867 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5.38385 4.48106 -130.463 -4.48106 4.48106 0.40 0.000546771 0.000502492 0.0415729 0.0380402 -1 -1 -1 -1 30 2915 39 6.87369e+06 335372 556674. 1926.21 1.91 0.214158 0.188442 25186 138497 -1 2162 17 1290 1817 117455 29996 3.39641 3.39641 -119.831 -3.39641 0 0 706193. 2443.58 0.05 0.05 0.12 -1 -1 0.05 0.022289 0.0200475 133 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_049.v common 6.55 vpr 66.48 MiB -1 -1 0.18 21512 1 0.03 -1 -1 33628 -1 -1 33 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68076 32 32 361 291 1 189 97 17 17 289 -1 unnamed_device 27.0 MiB 3.96 2368.33 1101 17635 5234 9819 2582 66.5 MiB 0.15 0.00 4.4072 3.86034 -124.956 -3.86034 3.86034 0.40 0.000581817 0.000535911 0.0459633 0.0420745 -1 -1 -1 -1 32 2498 21 6.87369e+06 461137 586450. 2029.24 0.59 0.115706 0.10313 25474 144626 -1 2066 21 1142 1927 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67224 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 26.6 MiB 2.83 2220.32 1101 13911 3917 7653 2341 65.6 MiB 0.13 0.00 5.73418 4.88188 -141.657 -4.88188 4.88188 0.40 0.000485327 0.000444589 0.0384415 0.0351778 -1 -1 -1 -1 28 2817 24 6.87369e+06 321398 531479. 1839.03 1.63 0.18945 0.166885 24610 126494 -1 2465 21 1761 2519 159833 39524 4.06626 4.06626 -137.879 -4.06626 0 0 648988. 2245.63 0.04 0.07 0.11 -1 -1 0.04 0.0240433 0.0214005 129 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 5.99 vpr 66.46 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33612 -1 -1 24 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68056 31 32 373 299 1 204 87 17 17 289 -1 unnamed_device 27.0 MiB 3.12 3048.36 1025 10263 2927 6018 1318 66.5 MiB 0.12 0.00 6.22918 4.76138 -141.442 -4.76138 4.76138 0.40 0.000584093 0.000534804 0.0380102 0.0348426 -1 -1 -1 -1 32 3229 31 6.87369e+06 335372 586450. 2029.24 0.89 0.122641 0.109014 25474 144626 -1 2337 22 1630 2751 195528 48326 3.99376 3.99376 -141.489 -3.99376 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0261052 0.0231948 140 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 7.20 vpr 66.23 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33684 -1 -1 22 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67816 32 32 387 315 1 194 86 17 17 289 -1 unnamed_device 26.7 MiB 3.60 2534.66 1136 7835 1846 5404 585 66.2 MiB 0.08 0.00 5.37753 4.33435 -134.782 -4.33435 4.33435 0.40 0.000625166 0.000574205 0.0263774 0.0240937 -1 -1 -1 -1 30 2672 20 6.87369e+06 307425 556674. 1926.21 1.68 0.217107 0.19027 25186 138497 -1 2278 21 1391 2545 151902 36425 3.6634 3.6634 -129.851 -3.6634 0 0 706193. 2443.58 0.04 0.06 0.12 -1 -1 0.04 0.025911 0.023042 134 77 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 3.91 vpr 66.07 MiB -1 -1 0.16 21568 1 0.03 -1 -1 33468 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67660 32 32 251 219 1 141 87 17 17 289 -1 unnamed_device 26.8 MiB 1.29 1844.41 681 8727 1897 6216 614 66.1 MiB 0.07 0.00 4.11555 3.50043 -101.627 -3.50043 3.50043 0.40 0.000426544 0.000390646 0.0205719 0.0187861 -1 -1 -1 -1 28 2084 39 6.87369e+06 321398 531479. 1839.03 0.80 0.0901592 0.0794934 24610 126494 -1 1578 21 1147 1792 117952 31406 2.70196 2.70196 -100.629 -2.70196 0 0 648988. 2245.63 0.04 0.05 0.11 -1 -1 0.04 0.0199333 0.0177583 93 23 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 5.85 vpr 66.18 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33416 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67768 32 32 341 285 1 188 84 17 17 289 -1 unnamed_device 26.6 MiB 2.57 2358 1064 9600 2581 6341 678 66.2 MiB 0.09 0.00 4.91669 4.03959 -138.624 -4.03959 4.03959 0.40 0.000508434 0.000465373 0.0291969 0.0267318 -1 -1 -1 -1 30 2465 20 6.87369e+06 279477 556674. 1926.21 1.38 0.159301 0.140245 25186 138497 -1 2013 23 1487 2143 137796 32895 3.0106 3.0106 -127.679 -3.0106 0 0 706193. 2443.58 0.05 0.06 0.12 -1 -1 0.05 0.0251764 0.0223608 120 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 6.48 vpr 66.87 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33792 -1 -1 29 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68476 32 32 387 293 1 236 93 17 17 289 -1 unnamed_device 27.1 MiB 3.75 2858.84 1406 12903 3890 7612 1401 66.9 MiB 0.13 0.00 6.54252 5.49998 -164.909 -5.49998 5.49998 0.40 0.000613498 0.000563727 0.0398268 0.0365318 -1 -1 -1 -1 32 3637 33 6.87369e+06 405241 586450. 2029.24 0.70 0.128442 0.114494 25474 144626 -1 2923 21 1876 2999 211966 49843 4.53655 4.53655 -157.367 -4.53655 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.0283217 0.0253038 164 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_058.v common 6.45 vpr 66.47 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33644 -1 -1 34 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68064 32 32 340 270 1 185 98 17 17 289 -1 unnamed_device 26.8 MiB 3.92 2646.33 1057 12698 3322 8112 1264 66.5 MiB 0.11 0.00 5.22181 4.32247 -137.244 -4.32247 4.32247 0.40 0.000560564 0.000513266 0.0329427 0.0300578 -1 -1 -1 -1 32 2300 30 6.87369e+06 475111 586450. 2029.24 0.61 0.10848 0.0961662 25474 144626 -1 1910 18 1146 1993 108348 27508 2.79566 2.79566 -116.308 -2.79566 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0221142 0.0197204 137 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_059.v common 3.57 vpr 65.84 MiB -1 -1 0.17 21240 1 0.03 -1 -1 33656 -1 -1 25 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67424 30 32 278 235 1 150 87 17 17 289 -1 unnamed_device 26.6 MiB 1.09 2187.48 808 9879 2531 6399 949 65.8 MiB 0.08 0.00 4.30385 3.42675 -104.9 -3.42675 3.42675 0.40 0.000452874 0.000412538 0.0243413 0.0221506 -1 -1 -1 -1 26 2066 25 6.87369e+06 349346 503264. 1741.40 0.64 0.0858461 0.0757647 24322 120374 -1 1867 26 1418 2313 162293 41447 3.43946 3.43946 -116.403 -3.43946 0 0 618332. 2139.56 0.04 0.07 0.11 -1 -1 0.04 0.0249291 0.0220006 104 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_060.v common 10.96 vpr 66.65 MiB -1 -1 0.19 21760 1 0.03 -1 -1 33536 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68252 32 32 431 332 1 239 91 17 17 289 -1 unnamed_device 27.1 MiB 6.13 2892.92 1424 14167 3798 8422 1947 66.7 MiB 0.17 0.00 6.88686 5.84665 -172.047 -5.84665 5.84665 0.41 0.000674231 0.000618908 0.0504943 0.0464765 -1 -1 -1 -1 30 3327 25 6.87369e+06 377294 556674. 1926.21 2.76 0.227324 0.201434 25186 138497 -1 2657 24 2096 3313 209481 48777 4.6769 4.6769 -160.08 -4.6769 0 0 706193. 2443.58 0.05 0.08 0.12 -1 -1 0.05 0.0318823 0.0284236 166 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 7.98 vpr 66.27 MiB -1 -1 0.18 21524 1 0.03 -1 -1 33448 -1 -1 35 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67856 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 26.7 MiB 4.13 2028.47 1133 14919 4275 8755 1889 66.3 MiB 0.12 0.00 5.20962 4.67542 -142.427 -4.67542 4.67542 0.40 0.000538802 0.000493062 0.0361418 0.0331095 -1 -1 -1 -1 28 2653 24 6.87369e+06 489084 531479. 1839.03 1.92 0.201731 0.177466 24610 126494 -1 2324 22 1641 2616 187134 42678 3.8894 3.8894 -141.04 -3.8894 0 0 648988. 2245.63 0.04 0.07 0.11 -1 -1 0.04 0.025903 0.0230657 135 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_062.v common 3.51 vpr 65.79 MiB -1 -1 0.16 21000 1 0.03 -1 -1 33604 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67364 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 26.5 MiB 1.14 1762.8 855 12512 3348 8365 799 65.8 MiB 0.09 0.00 3.96025 3.6312 -105.59 -3.6312 3.6312 0.40 0.000448605 0.000410629 0.025945 0.0236672 -1 -1 -1 -1 28 1989 22 6.87369e+06 391268 531479. 1839.03 0.54 0.0780238 0.0689041 24610 126494 -1 1736 22 999 1747 115875 28970 2.92726 2.92726 -105.066 -2.92726 0 0 648988. 2245.63 0.04 0.05 0.11 -1 -1 0.04 0.0195719 0.0173111 96 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 5.79 vpr 66.53 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33548 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68124 32 32 349 273 1 191 101 17 17 289 -1 unnamed_device 27.0 MiB 3.01 2736.16 1174 16316 4308 10047 1961 66.5 MiB 0.13 0.00 6.69567 5.27722 -139.358 -5.27722 5.27722 0.40 0.000539356 0.000490541 0.0392728 0.035617 -1 -1 -1 -1 26 2789 25 6.87369e+06 517032 503264. 1741.40 0.82 0.11495 0.102012 24322 120374 -1 2459 23 1559 3032 203928 48391 4.57355 4.57355 -141.119 -4.57355 0 0 618332. 2139.56 0.04 0.08 0.11 -1 -1 0.04 0.0267855 0.023861 145 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 3.95 vpr 65.77 MiB -1 -1 0.15 21376 1 0.03 -1 -1 33644 -1 -1 21 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67348 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 26.5 MiB 1.55 2118.54 750 9385 2715 5945 725 65.8 MiB 0.08 0.00 4.52145 3.49353 -105.466 -3.49353 3.49353 0.40 0.000436857 0.000399693 0.0226489 0.0206338 -1 -1 -1 -1 32 1967 23 6.87369e+06 293451 586450. 2029.24 0.57 0.0776947 0.0685878 25474 144626 -1 1595 20 1184 2094 130220 31374 2.83596 2.83596 -104.337 -2.83596 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0189643 0.0168542 99 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 6.26 vpr 65.85 MiB -1 -1 0.18 21376 1 0.03 -1 -1 33736 -1 -1 34 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67432 30 32 278 235 1 151 96 17 17 289 -1 unnamed_device 26.5 MiB 2.97 2241.44 891 16959 4812 10602 1545 65.9 MiB 0.12 0.00 4.84748 3.86298 -114.676 -3.86298 3.86298 0.40 0.000498299 0.000444631 0.0368976 0.0335199 -1 -1 -1 -1 26 2122 21 6.87369e+06 475111 503264. 1741.40 1.38 0.155787 0.136832 24322 120374 -1 1891 23 1259 2340 164590 38913 3.10226 3.10226 -115.173 -3.10226 0 0 618332. 2139.56 0.05 0.07 0.11 -1 -1 0.05 0.0245812 0.0218812 109 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 6.66 vpr 66.44 MiB -1 -1 0.20 21540 1 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4.66996 3.87398 -113.671 -3.87398 3.87398 0.40 0.000471757 0.000431899 0.0384231 0.0351931 -1 -1 -1 -1 38 1895 26 6.87369e+06 251529 678818. 2348.85 2.27 0.2129 0.18684 26626 170182 -1 1392 20 1163 1933 118518 30905 3.12156 3.12156 -106.727 -3.12156 0 0 902133. 3121.57 0.06 0.05 0.15 -1 -1 0.06 0.022646 0.0201941 105 63 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 5.54 vpr 66.20 MiB -1 -1 0.18 21764 1 0.03 -1 -1 33468 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67788 32 32 335 282 1 189 84 17 17 289 -1 unnamed_device 26.4 MiB 3.01 2218 967 9966 2748 6633 585 66.2 MiB 0.09 0.00 5.10429 3.99449 -129.503 -3.99449 3.99449 0.40 0.000557878 0.000515763 0.0294676 0.0269548 -1 -1 -1 -1 32 2511 25 6.87369e+06 279477 586450. 2029.24 0.62 0.099028 0.0878181 25474 144626 -1 2008 18 1211 1757 119685 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1 0.04 -1 -1 33620 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68064 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 26.9 MiB 4.52 2743.66 1055 13933 3990 7256 2687 66.5 MiB 0.13 0.00 5.70484 4.80258 -150.151 -4.80258 4.80258 0.40 0.000567421 0.00052318 0.042612 0.0391235 -1 -1 -1 -1 32 3314 35 6.87369e+06 335372 586450. 2029.24 0.85 0.130078 0.115991 25474 144626 -1 2440 21 1743 2591 191322 46798 4.13306 4.13306 -144.606 -4.13306 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0258422 0.023134 141 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 9.09 vpr 66.79 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33656 -1 -1 37 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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0.00 5.97852 4.52582 -144.214 -4.52582 4.52582 0.41 0.000577945 0.000529483 0.0518666 0.0472976 -1 -1 -1 -1 28 3415 34 6.87369e+06 572927 531479. 1839.03 3.74 0.218746 0.192557 24610 126494 -1 2621 22 1836 3366 261893 64507 4.082 4.082 -143.077 -4.082 0 0 648988. 2245.63 0.04 0.09 0.11 -1 -1 0.04 0.0287438 0.02554 148 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 5.86 vpr 65.57 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33892 -1 -1 18 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67140 30 32 272 232 1 151 80 17 17 289 -1 unnamed_device 26.2 MiB 3.29 2072.62 753 12808 4447 5763 2598 65.6 MiB 0.09 0.00 4.73318 3.85608 -113.888 -3.85608 3.85608 0.41 0.000450972 0.000413512 0.0341365 0.0312135 -1 -1 -1 -1 32 2278 41 6.87369e+06 251529 586450. 2029.24 0.67 0.107503 0.0951341 25474 144626 -1 1606 21 1170 1963 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4.75384 -143.273 -4.75384 4.75384 0.41 0.00054454 0.000499101 0.0336352 0.0307586 -1 -1 -1 -1 26 2541 21 6.87369e+06 433189 503264. 1741.40 1.85 0.179038 0.157618 24322 120374 -1 2323 18 1309 2055 136327 34742 3.71216 3.71216 -140.376 -3.71216 0 0 618332. 2139.56 0.04 0.06 0.11 -1 -1 0.04 0.0227384 0.0203368 136 83 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 6.16 vpr 66.23 MiB -1 -1 0.18 21308 1 0.03 -1 -1 33472 -1 -1 22 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67816 32 32 365 294 1 187 86 17 17 289 -1 unnamed_device 26.6 MiB 3.40 2693.74 1139 15584 4592 8623 2369 66.2 MiB 0.14 0.00 5.90348 4.77578 -145.748 -4.77578 4.77578 0.41 0.000556567 0.000507547 0.0474989 0.0431561 -1 -1 -1 -1 32 2707 20 6.87369e+06 307425 586450. 2029.24 0.65 0.118929 0.105965 25474 144626 -1 2264 18 1412 2507 161782 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67148 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 26.2 MiB 3.23 1865 977 12323 3350 7376 1597 65.6 MiB 0.09 0.00 4.99942 4.42918 -122.62 -4.42918 4.42918 0.42 0.000418169 0.000383799 0.0322571 0.0295953 -1 -1 -1 -1 22 2711 34 6.87369e+06 307425 443629. 1535.05 1.33 0.140579 0.123996 23458 102101 -1 2241 23 1418 1838 162165 38352 3.8887 3.8887 -120.73 -3.8887 0 0 531479. 1839.03 0.03 0.07 0.09 -1 -1 0.03 0.0212207 0.018793 104 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 7.71 vpr 65.62 MiB -1 -1 0.17 21564 1 0.03 -1 -1 33396 -1 -1 16 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67200 32 32 278 238 1 158 80 17 17 289 -1 unnamed_device 26.3 MiB 4.56 1738.22 923 5584 1140 4315 129 65.6 MiB 0.05 0.00 4.37928 3.89598 -122.108 -3.89598 3.89598 0.42 0.000471919 0.000433534 0.0165339 0.0151713 -1 -1 -1 -1 30 2085 24 6.87369e+06 223581 556674. 1926.21 1.30 0.133505 0.116831 25186 138497 -1 1761 19 1194 2072 123101 29346 2.87696 2.87696 -111.567 -2.87696 0 0 706193. 2443.58 0.04 0.05 0.12 -1 -1 0.04 0.0197954 0.0176114 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 7.24 vpr 66.30 MiB -1 -1 0.18 21376 1 0.03 -1 -1 34060 -1 -1 37 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67896 31 32 373 300 1 185 100 17 17 289 -1 unnamed_device 26.7 MiB 3.75 2655.13 998 13556 3689 8909 958 66.3 MiB 0.12 0.00 4.74418 3.88498 -123.633 -3.88498 3.88498 0.41 0.000572853 0.000525765 0.036583 0.033284 -1 -1 -1 -1 26 2407 31 6.87369e+06 517032 503264. 1741.40 1.53 0.208877 0.183095 24322 120374 -1 2086 21 1777 2796 169886 42371 3.20756 3.20756 -122.304 -3.20756 0 0 618332. 2139.56 0.04 0.07 0.11 -1 -1 0.04 0.026766 0.0239042 141 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 5.91 vpr 65.91 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33176 -1 -1 19 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67488 31 32 265 230 1 169 82 17 17 289 -1 unnamed_device 26.6 MiB 3.18 2006 938 8270 2331 5442 497 65.9 MiB 0.07 0.00 4.2629 3.6763 -117.183 -3.6763 3.6763 0.40 0.000441815 0.000401976 0.0220178 0.0201223 -1 -1 -1 -1 26 2515 27 6.87369e+06 265503 503264. 1741.40 0.88 0.0864726 0.076275 24322 120374 -1 2077 22 1426 2063 144088 35253 3.24491 3.24491 -120.554 -3.24491 0 0 618332. 2139.56 0.04 0.06 0.11 -1 -1 0.04 0.0210761 0.0187568 100 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 6.35 vpr 66.30 MiB -1 -1 0.18 21184 1 0.03 -1 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68184 31 32 396 325 1 183 94 17 17 289 -1 unnamed_device 27.0 MiB 4.22 2295.27 982 16282 5409 8281 2592 66.6 MiB 0.14 0.00 4.1365 3.7606 -126.896 -3.7606 3.7606 0.41 0.000589023 0.000538806 0.047284 0.043234 -1 -1 -1 -1 32 2317 28 6.87369e+06 433189 586450. 2029.24 0.66 0.131844 0.117486 25474 144626 -1 1871 17 1367 2069 119374 29972 3.09951 3.09951 -120.798 -3.09951 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0234313 0.0209442 136 91 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 6.49 vpr 65.79 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33484 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67372 32 32 303 262 1 154 82 17 17 289 -1 unnamed_device 26.6 MiB 3.04 1892.46 930 13610 3926 7738 1946 65.8 MiB 0.10 0.00 4.21775 3.46595 -111.116 -3.46595 3.46595 0.40 0.000453265 0.000413832 0.0371695 0.0339397 -1 -1 -1 -1 32 2010 30 6.87369e+06 251529 586450. 2029.24 1.55 0.188217 0.164957 25474 144626 -1 1620 19 948 1531 96942 23844 2.85796 2.85796 -109.295 -2.85796 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0201245 0.0179493 100 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 5.47 vpr 65.94 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33060 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67520 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 26.3 MiB 2.52 2269 846 15023 5112 7105 2806 65.9 MiB 0.12 0.00 5.53062 4.43872 -133.042 -4.43872 4.43872 0.41 0.000456333 0.000416729 0.0405279 0.036962 -1 -1 -1 -1 34 2491 31 6.87369e+06 265503 618332. 2139.56 1.01 0.147644 0.130069 25762 151098 -1 1812 20 1302 1953 138182 35210 3.43421 3.43421 -119.565 -3.43421 0 0 787024. 2723.27 0.05 0.06 0.14 -1 -1 0.05 0.021253 0.0189288 110 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 5.67 vpr 65.41 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33608 -1 -1 22 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66984 32 32 318 257 1 196 86 17 17 289 -1 unnamed_device 26.5 MiB 3.10 2163.08 1060 11048 3713 5060 2275 65.4 MiB 0.09 0.00 5.70718 4.76478 -133.796 -4.76478 4.76478 0.40 0.000505492 0.000461805 0.032269 0.0295545 -1 -1 -1 -1 30 2427 22 6.87369e+06 307425 556674. 1926.21 0.66 0.100271 0.089207 25186 138497 -1 2020 20 1254 1731 101663 25086 3.76346 3.76346 -131.36 -3.76346 0 0 706193. 2443.58 0.05 0.05 0.12 -1 -1 0.05 0.0227184 0.0202658 128 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 6.16 vpr 66.28 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33344 -1 -1 29 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67872 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 26.5 MiB 3.64 2255.59 990 10140 2558 6775 807 66.3 MiB 0.10 0.00 4.47163 4.11363 -115.607 -4.11363 4.11363 0.40 0.000564607 0.000518831 0.0281155 0.0257809 -1 -1 -1 -1 30 2125 26 6.87369e+06 405241 556674. 1926.21 0.58 0.0989464 0.0880079 25186 138497 -1 1706 22 856 1609 88635 21834 3.01151 3.01151 -103.493 -3.01151 0 0 706193. 2443.58 0.05 0.05 0.12 -1 -1 0.05 0.0240801 0.0214395 123 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 8.10 vpr 66.42 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33792 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68016 32 32 393 312 1 215 88 17 17 289 -1 unnamed_device 26.8 MiB 4.21 3044.78 1139 10618 2981 6291 1346 66.4 MiB 0.11 0.00 6.40138 5.22906 -165.517 -5.22906 5.22906 0.41 0.000584363 0.000534803 0.0347784 0.031916 -1 -1 -1 -1 30 2711 22 6.87369e+06 335372 556674. 1926.21 1.64 0.19542 0.172828 25186 138497 -1 2234 23 1527 2357 149419 35477 3.88246 3.88246 -146.011 -3.88246 0 0 706193. 2443.58 0.04 0.07 0.12 -1 -1 0.04 0.0291256 0.0259491 148 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 3.94 vpr 65.79 MiB -1 -1 0.16 21272 1 0.03 -1 -1 33404 -1 -1 18 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67364 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 26.6 MiB 1.60 1779.7 625 4631 866 3215 550 65.8 MiB 0.03 0.00 4.01225 3.52895 -101.476 -3.52895 3.52895 0.40 0.000394935 0.000362128 0.0119895 0.010982 -1 -1 -1 -1 30 1639 23 6.87369e+06 251529 556674. 1926.21 0.56 0.0635824 0.0559862 25186 138497 -1 1219 21 737 1159 53687 15362 3.04656 3.04656 -101.409 -3.04656 0 0 706193. 2443.58 0.04 0.04 0.12 -1 -1 0.04 0.0189473 0.0168676 93 4 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 7.46 vpr 66.32 MiB -1 -1 0.19 21664 1 0.03 -1 -1 33780 -1 -1 35 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67916 32 32 412 334 1 194 99 17 17 289 -1 unnamed_device 26.7 MiB 2.66 2354.73 1015 18111 5639 9784 2688 66.3 MiB 0.15 0.00 5.55115 4.44135 -142.963 -4.44135 4.44135 0.40 0.000584929 0.000534732 0.0503817 0.0460323 -1 -1 -1 -1 30 2657 25 6.87369e+06 489084 556674. 1926.21 2.80 0.2392 0.210742 25186 138497 -1 2087 20 1396 2004 147362 36614 3.76236 3.76236 -137.015 -3.76236 0 0 706193. 2443.58 0.05 0.07 0.12 -1 -1 0.05 0.0261196 0.0232323 145 90 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 9.73 vpr 66.28 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33480 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67872 32 32 376 318 1 168 82 17 17 289 -1 unnamed_device 26.8 MiB 5.91 2123.46 899 10762 4016 5455 1291 66.3 MiB 0.09 0.00 4.47325 3.59615 -128.254 -3.59615 3.59615 0.42 0.000538552 0.00049218 0.035013 0.0320247 -1 -1 -1 -1 36 1939 22 6.87369e+06 251529 648988. 2245.63 1.82 0.218678 0.191546 26050 158493 -1 1779 23 1529 2252 180862 42773 3.10426 3.10426 -129.38 -3.10426 0 0 828058. 2865.25 0.05 0.07 0.14 -1 -1 0.05 0.0265831 0.0235937 114 96 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 6.59 vpr 66.51 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33652 -1 -1 33 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68104 32 32 360 293 1 182 97 17 17 289 -1 unnamed_device 27.0 MiB 3.89 2264.61 1081 14305 4184 7699 2422 66.5 MiB 0.14 0.00 4.28962 4.12873 -128.094 -4.12873 4.12873 0.40 0.000542454 0.000494701 0.0375669 0.0343687 -1 -1 -1 -1 28 2650 26 6.87369e+06 461137 531479. 1839.03 0.73 0.115301 0.102435 24610 126494 -1 2157 20 1260 2150 145411 35208 3.29686 3.29686 -119.003 -3.29686 0 0 648988. 2245.63 0.04 0.07 0.11 -1 -1 0.04 0.0251315 0.0224331 134 60 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_122.v common 9.14 vpr 65.94 MiB -1 -1 0.19 21572 1 0.03 -1 -1 33724 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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3.16961 -92.7187 -3.16961 3.16961 0.41 0.000403208 0.000370521 0.0311903 0.0285563 -1 -1 -1 -1 30 1782 28 6.87369e+06 237555 556674. 1926.21 0.73 0.0886873 0.0783321 25186 138497 -1 1269 16 770 993 68728 19715 2.63001 2.63001 -90.3813 -2.63001 0 0 706193. 2443.58 0.05 0.04 0.12 -1 -1 0.05 0.0144262 0.0128874 78 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_124.v common 4.00 vpr 65.88 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33340 -1 -1 21 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67464 30 32 286 239 1 151 83 17 17 289 -1 unnamed_device 26.6 MiB 1.51 1770.71 758 12863 4724 6383 1756 65.9 MiB 0.10 0.00 4.46678 3.90824 -117.819 -3.90824 3.90824 0.41 0.000459309 0.000417483 0.0360566 0.032982 -1 -1 -1 -1 32 1677 18 6.87369e+06 293451 586450. 2029.24 0.57 0.0944483 0.084085 25474 144626 -1 1359 23 1013 1508 94997 23267 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0.03 -1 -1 33780 -1 -1 29 25 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67572 25 32 216 194 1 123 86 17 17 289 -1 unnamed_device 26.7 MiB 1.13 1478.16 521 12938 4434 5564 2940 66.0 MiB 0.07 0.00 4.10455 3.48943 -81.0717 -3.48943 3.48943 0.41 0.000363627 0.000330528 0.0261855 0.0238463 -1 -1 -1 -1 30 1629 41 6.87369e+06 405241 556674. 1926.21 0.67 0.0864099 0.0760073 25186 138497 -1 1166 19 766 1360 77787 20476 2.73796 2.73796 -77.5522 -2.73796 0 0 706193. 2443.58 0.04 0.04 0.12 -1 -1 0.04 0.0152874 0.0135459 87 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_127.v common 5.99 vpr 66.54 MiB -1 -1 0.19 21760 1 0.03 -1 -1 33284 -1 -1 22 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68136 32 32 376 307 1 192 86 17 17 289 -1 unnamed_device 26.8 MiB 3.33 2245.43 1112 15017 5048 7382 2587 66.5 MiB 0.14 0.00 5.02315 4.32635 -130.338 -4.32635 4.32635 0.40 0.000564638 0.000517441 0.0482881 0.0442394 -1 -1 -1 -1 32 2710 23 6.87369e+06 307425 586450. 2029.24 0.66 0.125757 0.112424 25474 144626 -1 2218 19 1232 2214 145908 34239 3.74866 3.74866 -129.54 -3.74866 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0240421 0.0214207 131 72 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_128.v common 6.68 vpr 66.48 MiB -1 -1 0.20 21568 1 0.03 -1 -1 33692 -1 -1 34 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68076 31 32 409 331 1 193 97 17 17 289 -1 unnamed_device 27.1 MiB 4.02 2417.92 956 9199 2038 6732 429 66.5 MiB 0.10 0.00 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0.18 21300 1 0.03 -1 -1 33736 -1 -1 21 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67168 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 26.2 MiB 2.06 2478.55 1058 14965 5019 7513 2433 65.6 MiB 0.13 0.00 5.35819 4.29629 -120.549 -4.29629 4.29629 0.41 0.000471613 0.000432239 0.044507 0.0409322 -1 -1 -1 -1 30 2541 22 6.89349e+06 295971 556674. 1926.21 1.61 0.18454 0.16271 25186 138497 -1 2070 19 1036 1464 91207 22505 3.7788 3.7788 -120.15 -3.7788 0 0 706193. 2443.58 0.05 0.05 0.12 -1 -1 0.05 0.0206354 0.0184397 119 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_004.v common 3.98 vpr 66.07 MiB -1 -1 0.18 21188 1 0.03 -1 -1 33984 -1 -1 27 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67656 29 32 308 248 1 195 88 17 17 289 -1 unnamed_device 26.6 MiB 1.43 2648.76 1130 14518 4432 8058 2028 66.1 MiB 0.12 0.00 6.19768 4.89353 -134.053 -4.89353 4.89353 0.40 0.00053119 0.000488927 0.0383659 0.0351314 -1 -1 -1 -1 32 2459 22 6.89349e+06 380534 586450. 2029.24 0.61 0.102723 0.0913185 25474 144626 -1 2080 21 1202 2009 122951 29583 3.58106 3.58106 -121.479 -3.58106 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0229506 0.0204211 130 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_005.v common 6.41 vpr 66.24 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33288 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67832 32 32 336 268 1 211 89 17 17 289 -1 unnamed_device 26.8 MiB 2.60 2799.55 1230 14741 4006 9022 1713 66.2 MiB 0.15 0.00 6.91451 5.26641 -153.699 -5.26641 5.26641 0.40 0.000534538 0.000491728 0.0425604 0.0390256 -1 -1 -1 -1 34 2827 22 6.89349e+06 352346 618332. 2139.56 1.82 0.188696 0.166706 25762 151098 -1 2420 22 1349 2359 162449 38184 4.58175 4.58175 -155.407 -4.58175 0 0 787024. 2723.27 0.05 0.07 0.13 -1 -1 0.05 0.0258819 0.0230602 141 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_006.v common 7.35 vpr 66.32 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33484 -1 -1 35 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67908 32 32 366 295 1 231 99 17 17 289 -1 unnamed_device 26.6 MiB 3.09 2831.91 1290 17883 5719 9477 2687 66.3 MiB 0.17 0.00 4.85631 3.86419 -127.744 -3.86419 3.86419 0.41 0.000563634 0.000516684 0.047153 0.0430497 -1 -1 -1 -1 30 3132 37 6.89349e+06 493284 556674. 1926.21 2.18 0.213776 0.188 25186 138497 -1 2477 27 1861 3080 214840 65212 3.37695 3.37695 -126.245 -3.37695 0 0 706193. 2443.58 0.05 0.10 0.12 -1 -1 0.05 0.0344005 0.0307809 156 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_007.v common 4.93 vpr 65.78 MiB -1 -1 0.17 21184 1 0.03 -1 -1 34012 -1 -1 22 27 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67356 27 32 259 221 1 159 81 17 17 289 -1 unnamed_device 26.4 MiB 1.58 1787.83 745 12506 4805 5637 2064 65.8 MiB 0.09 0.00 4.91933 4.16753 -111.453 -4.16753 4.16753 0.40 0.000416711 0.000379704 0.0319666 0.0290847 -1 -1 -1 -1 30 1770 19 6.89349e+06 310065 556674. 1926.21 1.49 0.139447 0.122359 25186 138497 -1 1516 20 1100 1639 102027 25341 2.95361 2.95361 -99.1503 -2.95361 0 0 706193. 2443.58 0.04 0.05 0.12 -1 -1 0.04 0.0198479 0.0177231 104 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 3.53 vpr 65.56 MiB -1 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67632 31 32 317 271 1 207 86 17 17 289 -1 unnamed_device 26.5 MiB 1.86 2257 1078 6701 1453 4989 259 66.0 MiB 0.07 0.00 4.58785 3.59345 -120.43 -3.59345 3.59345 0.42 0.000523122 0.0004823 0.0195415 0.0179066 -1 -1 -1 -1 32 2489 23 6.89349e+06 324158 586450. 2029.24 1.65 0.159397 0.139614 25474 144626 -1 2059 21 1403 1875 134074 31295 3.07676 3.07676 -118.62 -3.07676 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0230898 0.0205872 125 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_010.v common 5.48 vpr 65.78 MiB -1 -1 0.17 21260 1 0.03 -1 -1 33632 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67360 32 32 298 248 1 185 83 17 17 289 -1 unnamed_device 26.5 MiB 1.98 1986.9 982 6563 1442 4685 436 65.8 MiB 0.07 0.00 4.79638 4.06248 -132.59 -4.06248 4.06248 0.41 0.000494279 0.000453101 0.0192304 0.0176286 -1 -1 -1 -1 32 2287 25 6.89349e+06 267783 586450. 2029.24 1.62 0.154715 0.135584 25474 144626 -1 1930 22 1225 1621 106358 25981 3.12685 3.12685 -123.854 -3.12685 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0216857 0.0192524 115 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_011.v common 4.50 vpr 65.62 MiB -1 -1 0.18 21376 1 0.03 -1 -1 33476 -1 -1 22 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67196 30 32 303 262 1 191 84 17 17 289 -1 unnamed_device 26.4 MiB 2.00 2107 1035 13077 3841 7468 1768 65.6 MiB 0.10 0.00 5.30417 4.49997 -133.489 -4.49997 4.49997 0.40 0.000452761 0.000413717 0.0349984 0.0320192 -1 -1 -1 -1 32 2290 23 6.89349e+06 310065 586450. 2029.24 0.59 0.0985592 0.0875972 25474 144626 -1 1937 20 1170 1527 111715 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21568 1 0.03 -1 -1 33788 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67840 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 26.6 MiB 2.52 2413 1048 15335 4837 7845 2653 66.2 MiB 0.14 0.00 4.45968 4.12632 -130.881 -4.12632 4.12632 0.40 0.000534822 0.000489723 0.0449551 0.041326 -1 -1 -1 -1 32 3130 25 6.89349e+06 352346 586450. 2029.24 0.75 0.120458 0.107541 25474 144626 -1 2262 23 1701 2620 199466 47383 3.20806 3.20806 -120.104 -3.20806 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.0278091 0.0247874 140 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_014.v common 6.62 vpr 66.36 MiB -1 -1 0.18 21572 1 0.03 -1 -1 33948 -1 -1 26 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67952 32 32 363 295 1 232 90 17 17 289 -1 unnamed_device 26.6 MiB 2.65 2784.92 1124 7728 1672 5773 283 66.4 MiB 0.08 0.00 6.97451 5.45757 -155.798 -5.45757 5.45757 0.40 0.000598816 0.000551726 0.0241737 0.0221514 -1 -1 -1 -1 30 2944 41 6.89349e+06 366440 556674. 1926.21 2.05 0.219465 0.192843 25186 138497 -1 2325 23 1713 2360 150851 37432 4.40835 4.40835 -147.217 -4.40835 0 0 706193. 2443.58 0.05 0.07 0.12 -1 -1 0.05 0.0275342 0.0245083 151 61 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_015.v common 4.17 vpr 65.80 MiB -1 -1 0.16 21312 1 0.03 -1 -1 33660 -1 -1 21 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67376 29 32 248 215 1 160 82 17 17 289 -1 unnamed_device 26.4 MiB 1.74 1849.82 777 10762 2615 7615 532 65.8 MiB 0.08 0.00 4.18032 3.23418 -96.7477 -3.23418 3.23418 0.41 0.000405209 0.000371468 0.0267017 0.0244719 -1 -1 -1 -1 30 1844 21 6.89349e+06 295971 556674. 1926.21 0.55 0.0809393 0.0719469 25186 138497 -1 1498 22 967 1375 83682 21630 2.89731 2.89731 -98.7482 -2.89731 0 0 706193. 2443.58 0.05 0.05 0.12 -1 -1 0.05 0.0228992 0.0205352 98 27 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_016.v common 6.91 vpr 66.32 MiB -1 -1 0.18 21492 1 0.03 -1 -1 33452 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67912 32 32 370 297 1 234 91 17 17 289 -1 unnamed_device 26.8 MiB 3.24 2606.34 1321 16003 5265 8403 2335 66.3 MiB 0.15 0.00 5.16764 4.23814 -137.903 -4.23814 4.23814 0.40 0.000562503 0.000515937 0.0469866 0.0430102 -1 -1 -1 -1 32 3018 23 6.89349e+06 380534 586450. 2029.24 1.67 0.195949 0.173081 25474 144626 -1 2476 23 1702 2678 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67100 30 32 222 206 1 141 78 17 17 289 -1 unnamed_device 26.4 MiB 1.10 1681.49 755 9872 2574 6614 684 65.5 MiB 0.07 0.00 3.29613 2.66963 -90.6547 -2.66963 2.66963 0.40 0.000370131 0.000337924 0.023524 0.0214811 -1 -1 -1 -1 28 1581 17 6.89349e+06 225501 531479. 1839.03 0.52 0.0693463 0.0613244 24610 126494 -1 1395 17 749 863 62232 15664 2.11002 2.11002 -91.215 -2.11002 0 0 648988. 2245.63 0.04 0.03 0.11 -1 -1 0.04 0.015194 0.0135291 79 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_020.v common 5.99 vpr 65.84 MiB -1 -1 0.17 21568 1 0.03 -1 -1 34048 -1 -1 21 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67424 31 32 291 243 1 179 84 17 17 289 -1 unnamed_device 26.6 MiB 2.30 2232.26 890 14358 5131 6799 2428 65.8 MiB 0.12 0.00 5.72212 4.76092 -139.521 -4.76092 4.76092 0.40 0.000466556 0.000427974 0.0391112 0.0358833 -1 -1 -1 -1 32 2434 42 6.89349e+06 295971 586450. 2029.24 1.74 0.202416 0.177597 25474 144626 -1 1879 21 1290 1949 139476 34531 3.6142 3.6142 -129.466 -3.6142 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0209794 0.0186322 115 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_021.v common 6.58 vpr 66.29 MiB -1 -1 0.18 21376 1 0.03 -1 -1 33748 -1 -1 35 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67884 32 32 342 271 1 207 99 17 17 289 -1 unnamed_device 26.7 MiB 1.95 2415.37 1186 18795 6653 9829 2313 66.3 MiB 0.15 0.00 6.0155 4.63443 -148.243 -4.63443 4.63443 0.40 0.000524123 0.000478364 0.0462497 0.0422655 -1 -1 -1 -1 28 2995 49 6.89349e+06 493284 531479. 1839.03 2.51 0.245542 0.216072 24610 126494 -1 2535 22 1705 2598 254970 74850 4.03424 4.03424 -149.917 -4.03424 0 0 648988. 2245.63 0.04 0.10 0.11 -1 -1 0.04 0.0260103 0.0231083 150 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_022.v common 6.61 vpr 66.41 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33416 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68000 32 32 372 300 1 229 89 17 17 289 -1 unnamed_device 26.6 MiB 1.88 2941.48 1396 8999 2370 5950 679 66.4 MiB 0.10 0.00 6.09628 4.66558 -144.111 -4.66558 4.66558 0.40 0.000563979 0.000517607 0.0284843 0.0260594 -1 -1 -1 -1 28 3459 47 6.89349e+06 352346 531479. 1839.03 2.75 0.207024 0.181399 24610 126494 -1 2778 27 2327 3553 316308 106747 4.08779 4.08779 -143.915 -4.08779 0 0 648988. 2245.63 0.04 0.13 0.11 -1 -1 0.04 0.0322259 0.0286644 152 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_023.v common 3.42 vpr 65.38 MiB -1 -1 0.18 21248 1 0.03 -1 -1 33800 -1 -1 19 26 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66948 26 32 190 182 1 126 77 17 17 289 -1 unnamed_device 26.4 MiB 1.06 1378.73 528 11324 4722 5741 861 65.4 MiB 0.06 0.00 2.92131 2.67071 -73.9405 -2.67071 2.67071 0.40 0.00034072 0.000312355 0.0245276 0.0224451 -1 -1 -1 -1 30 1223 26 6.89349e+06 267783 556674. 1926.21 0.56 0.0692388 0.0612852 25186 138497 -1 921 17 565 672 37400 10275 1.85675 1.85675 -65.726 -1.85675 0 0 706193. 2443.58 0.04 0.03 0.12 -1 -1 0.04 0.0126598 0.0112944 72 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_024.v common 3.93 vpr 65.80 MiB -1 -1 0.16 21184 1 0.03 -1 -1 33276 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67376 32 32 285 227 1 169 88 17 17 289 -1 unnamed_device 26.4 MiB 1.40 2097.1 1093 14908 4191 8870 1847 65.8 MiB 0.12 0.00 5.19194 4.58773 -130.119 -4.58773 4.58773 0.40 0.000466093 0.000427547 0.0375881 0.0344047 -1 -1 -1 -1 32 2488 23 6.89349e+06 338252 586450. 2029.24 0.62 0.0994677 0.0884444 25474 144626 -1 2145 20 1144 2016 159814 37055 3.49805 3.49805 -121.157 -3.49805 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0210441 0.0187336 120 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_025.v common 2.94 vpr 65.29 MiB -1 -1 0.15 20992 1 0.03 -1 -1 33768 -1 -1 12 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66852 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 26.1 MiB 0.72 1343.56 639 6796 1773 4080 943 65.3 MiB 0.04 0.00 2.53969 2.47582 -78.0945 -2.47582 2.47582 0.40 0.00032065 0.00029286 0.0146059 0.0133263 -1 -1 -1 -1 26 1408 24 6.89349e+06 169126 503264. 1741.40 0.50 0.058136 0.0511543 24322 120374 -1 1320 21 647 839 64260 17370 2.21036 2.21036 -82.8757 -2.21036 0 0 618332. 2139.56 0.04 0.04 0.11 -1 -1 0.04 0.0145264 0.0128552 64 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_026.v common 4.49 vpr 65.64 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33836 -1 -1 22 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67216 32 32 300 245 1 187 86 17 17 289 -1 unnamed_device 26.3 MiB 2.02 2120.65 1085 9536 2559 6078 899 65.6 MiB 0.09 0.00 5.62618 4.92048 -138.071 -4.92048 4.92048 0.41 0.000515035 0.000470761 0.0278702 0.025499 -1 -1 -1 -1 32 2428 20 6.89349e+06 310065 586450. 2029.24 0.58 0.0894638 0.0794579 25474 144626 -1 1966 16 1004 1478 88603 22258 3.7112 3.7112 -125.676 -3.7112 0 0 744469. 2576.02 0.05 0.04 0.13 -1 -1 0.05 0.0186451 0.0167611 121 24 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 3.58 vpr 65.86 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33828 -1 -1 31 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67436 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 26.5 MiB 1.06 2474.01 1043 16727 4808 9374 2545 65.9 MiB 0.14 0.00 4.41543 3.451 -108.699 -3.451 3.451 0.40 0.000483506 0.000442762 0.039107 0.0356993 -1 -1 -1 -1 32 2399 21 6.89349e+06 436909 586450. 2029.24 0.59 0.100414 0.0894371 25474 144626 -1 2003 21 1136 2050 128645 30983 2.66571 2.66571 -101.838 -2.66571 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0230448 0.0206238 130 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 6.03 vpr 66.24 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33476 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67832 32 32 338 277 1 215 89 17 17 289 -1 unnamed_device 26.8 MiB 2.45 2459.59 1233 9395 2329 6263 803 66.2 MiB 0.10 0.00 5.82658 4.87098 -137.684 -4.87098 4.87098 0.40 0.000538612 0.00049509 0.0270098 0.0247351 -1 -1 -1 -1 34 2620 22 6.89349e+06 352346 618332. 2139.56 1.66 0.163173 0.143048 25762 151098 -1 2197 20 1326 2034 127959 30188 3.70146 3.70146 -127.18 -3.70146 0 0 787024. 2723.27 0.05 0.06 0.13 -1 -1 0.05 0.0232131 0.0207603 139 50 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_029.v common 4.70 vpr 65.64 MiB -1 -1 0.16 21568 1 0.03 -1 -1 33476 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67212 32 32 284 241 1 177 84 17 17 289 -1 unnamed_device 26.4 MiB 2.25 1936.29 1067 12894 4344 6614 1936 65.6 MiB 0.10 0.00 4.31105 3.7646 -126.911 -3.7646 3.7646 0.40 0.000456646 0.000418921 0.0339235 0.0310446 -1 -1 -1 -1 32 2226 20 6.89349e+06 281877 586450. 2029.24 0.57 0.0920031 0.0818246 25474 144626 -1 1958 21 1103 1593 110334 26241 2.69186 2.69186 -115.097 -2.69186 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0205211 0.0182504 110 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_030.v common 3.98 vpr 65.62 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33524 -1 -1 21 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67192 30 32 262 227 1 161 83 17 17 289 -1 unnamed_device 26.4 MiB 1.54 2301.37 943 13043 4183 6793 2067 65.6 MiB 0.09 0.00 5.05544 4.00962 -116.333 -4.00962 4.00962 0.40 0.000436134 0.00039934 0.0321671 0.029447 -1 -1 -1 -1 32 2109 18 6.89349e+06 295971 586450. 2029.24 0.57 0.0859742 0.076647 25474 144626 -1 1793 21 971 1595 128041 29328 3.30785 3.30785 -109.419 -3.30785 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0198361 0.0175877 103 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_031.v common 4.42 vpr 65.29 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33492 -1 -1 20 28 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 66852 28 32 260 223 1 163 80 17 17 289 -1 unnamed_device 26.0 MiB 1.88 1953.79 1013 13324 4541 7089 1694 65.3 MiB 0.10 0.00 5.13107 4.43603 -124.612 -4.43603 4.43603 0.40 0.000416482 0.000380791 0.034769 0.0318268 -1 -1 -1 -1 30 2187 21 6.89349e+06 281877 556674. 1926.21 0.68 0.0915218 0.0814213 25186 138497 -1 1819 17 903 1571 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0.17 21572 1 0.03 -1 -1 33644 -1 -1 21 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67396 31 32 271 231 1 172 84 17 17 289 -1 unnamed_device 26.4 MiB 1.82 2574.92 993 14175 4252 8234 1689 65.8 MiB 0.11 0.00 4.5958 3.59145 -114.024 -3.59145 3.59145 0.40 0.000433865 0.000397773 0.0350491 0.0320364 -1 -1 -1 -1 28 2384 22 6.89349e+06 295971 531479. 1839.03 1.61 0.162065 0.1419 24610 126494 -1 1995 19 1067 1607 122036 28982 2.77386 2.77386 -110.018 -2.77386 0 0 648988. 2245.63 0.04 0.05 0.11 -1 -1 0.04 0.0193294 0.0171937 105 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 4.71 vpr 65.73 MiB -1 -1 0.18 21412 1 0.03 -1 -1 33792 -1 -1 23 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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4.57545 -133.583 -4.57545 4.57545 0.40 0.000594175 0.000546966 0.0434359 0.0398021 -1 -1 -1 -1 36 2825 23 6.89349e+06 380534 648988. 2245.63 1.18 0.171408 0.152388 26050 158493 -1 2396 20 1295 2069 145934 34231 3.97056 3.97056 -127.691 -3.97056 0 0 828058. 2865.25 0.05 0.06 0.14 -1 -1 0.05 0.0251041 0.022434 154 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_036.v common 5.49 vpr 66.52 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33452 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68112 32 32 391 311 1 250 92 17 17 289 -1 unnamed_device 27.1 MiB 2.72 2630.66 1371 16031 4592 9416 2023 66.5 MiB 0.15 0.00 4.96607 4.60807 -154.693 -4.60807 4.60807 0.40 0.000581673 0.00053354 0.0473893 0.0434146 -1 -1 -1 -1 32 3408 34 6.89349e+06 394628 586450. 2029.24 0.76 0.137026 0.122102 25474 144626 -1 2828 20 2066 2899 233942 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21568 1 0.03 -1 -1 33464 -1 -1 27 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68144 31 32 370 297 1 235 90 17 17 289 -1 unnamed_device 27.1 MiB 2.84 2670.4 1289 13155 3308 7952 1895 66.5 MiB 0.12 0.00 5.12349 4.31155 -137.727 -4.31155 4.31155 0.40 0.000577622 0.000530028 0.0387482 0.0355107 -1 -1 -1 -1 30 2812 22 6.89349e+06 380534 556674. 1926.21 0.67 0.112381 0.100085 25186 138497 -1 2328 20 1532 2286 129522 32467 3.41065 3.41065 -129.329 -3.41065 0 0 706193. 2443.58 0.04 0.06 0.12 -1 -1 0.04 0.0248657 0.0222052 154 61 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 8.46 vpr 66.09 MiB -1 -1 0.19 21720 1 0.03 -1 -1 33828 -1 -1 28 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67676 31 32 377 302 1 241 91 17 17 289 -1 unnamed_device 26.6 MiB 2.82 2869 1312 10903 3033 6957 913 66.1 MiB 0.11 0.00 6.59857 5.48687 -164.386 -5.48687 5.48687 0.40 0.000596046 0.000549091 0.0330764 0.0303334 -1 -1 -1 -1 28 3699 34 6.89349e+06 394628 531479. 1839.03 3.68 0.233285 0.204978 24610 126494 -1 2843 22 2167 3172 256146 58348 4.56944 4.56944 -161.355 -4.56944 0 0 648988. 2245.63 0.04 0.09 0.11 -1 -1 0.04 0.0280258 0.0249793 158 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_040.v common 5.97 vpr 66.43 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33452 -1 -1 29 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68020 31 32 383 305 1 240 92 17 17 289 -1 unnamed_device 27.0 MiB 3.26 2971.73 1282 18308 5315 11006 1987 66.4 MiB 0.18 0.00 7.06021 5.82563 -171.495 -5.82563 5.82563 0.40 0.00059423 0.000547197 0.0545949 0.050091 -1 -1 -1 -1 32 3026 21 6.89349e+06 408721 586450. 2029.24 0.67 0.131804 0.118084 25474 144626 -1 2533 24 1820 2706 205125 48270 5.09534 5.09534 -170.517 -5.09534 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.0291484 0.0259461 160 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_041.v common 5.82 vpr 66.18 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33820 -1 -1 27 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67772 31 32 352 285 1 223 90 17 17 289 -1 unnamed_device 26.6 MiB 2.12 2244.92 1248 13356 3517 7457 2382 66.2 MiB 0.13 0.00 4.56598 4.06478 -128.105 -4.06478 4.06478 0.40 0.000568916 0.000523775 0.0392331 0.0360576 -1 -1 -1 -1 32 2930 29 6.89349e+06 380534 586450. 2029.24 1.69 0.189895 0.167413 25474 144626 -1 2292 22 1488 2132 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4.77782 -145.38 -4.77782 4.77782 0.40 0.000524219 0.000479923 0.0361489 0.0330759 -1 -1 -1 -1 30 2973 47 6.89349e+06 352346 556674. 1926.21 1.98 0.205313 0.18048 25186 138497 -1 2444 19 1321 2014 149854 33013 3.58756 3.58756 -128.726 -3.58756 0 0 706193. 2443.58 0.04 0.06 0.12 -1 -1 0.04 0.0225155 0.0200886 139 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_046.v common 6.34 vpr 65.96 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33280 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67540 32 32 349 284 1 222 91 17 17 289 -1 unnamed_device 26.4 MiB 2.50 2669.13 1215 9475 2129 6867 479 66.0 MiB 0.10 0.00 5.26295 4.30378 -130.599 -4.30378 4.30378 0.40 0.000570385 0.000517454 0.0273389 0.0249288 -1 -1 -1 -1 36 2700 23 6.89349e+06 380534 648988. 2245.63 1.91 0.194237 0.170039 26050 158493 -1 2294 20 1317 2084 137447 32519 3.4259 3.4259 -123.453 -3.4259 0 0 828058. 2865.25 0.05 0.06 0.14 -1 -1 0.05 0.0237583 0.02123 146 53 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_047.v common 3.82 vpr 65.57 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33656 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67148 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 26.3 MiB 1.27 1933.18 1092 14575 4579 7786 2210 65.6 MiB 0.12 0.00 4.84964 4.24939 -129.722 -4.24939 4.24939 0.40 0.000471035 0.000430639 0.036099 0.0329948 -1 -1 -1 -1 32 2496 21 6.89349e+06 380534 586450. 2029.24 0.64 0.0975376 0.0867117 25474 144626 -1 2102 21 1130 2260 167469 38040 3.607 3.607 -125.377 -3.607 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0217389 0.0193555 123 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 6.44 vpr 66.18 MiB -1 -1 0.18 21568 1 0.03 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36540 4.2106 4.2106 -141.768 -4.2106 0 0 618332. 2139.56 0.04 0.06 0.11 -1 -1 0.04 0.0224084 0.0200049 123 24 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_052.v common 5.18 vpr 65.50 MiB -1 -1 0.17 21760 1 0.03 -1 -1 33844 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67072 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 26.5 MiB 1.69 2220.32 1086 13911 3841 7942 2128 65.5 MiB 0.12 0.00 5.85178 4.88518 -140.805 -4.88518 4.88518 0.40 0.000504034 0.000462991 0.0382353 0.0350258 -1 -1 -1 -1 28 2852 35 6.89349e+06 324158 531479. 1839.03 1.58 0.185055 0.162824 24610 126494 -1 2420 21 1724 2477 164932 40896 3.995 3.995 -136.908 -3.995 0 0 648988. 2245.63 0.04 0.07 0.11 -1 -1 0.04 0.0233443 0.0207858 129 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_053.v common 5.48 vpr 66.34 MiB -1 -1 0.19 21568 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4.27105 3.55383 -105.248 -3.55383 3.55383 0.40 0.000415639 0.000380914 0.0317204 0.0289704 -1 -1 -1 -1 32 2262 44 6.89349e+06 239595 586450. 2029.24 0.77 0.102194 0.090194 25474 144626 -1 1579 19 952 1380 99711 28807 2.81411 2.81411 -102.252 -2.81411 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0182022 0.0162031 93 23 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_056.v common 4.72 vpr 66.12 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33604 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67708 32 32 341 285 1 219 88 17 17 289 -1 unnamed_device 26.6 MiB 2.14 2681 1185 11203 3130 7109 964 66.1 MiB 0.11 0.00 5.91853 4.57023 -156.618 -4.57023 4.57023 0.40 0.00053019 0.000486449 0.0324256 0.0296614 -1 -1 -1 -1 32 2670 21 6.89349e+06 338252 586450. 2029.24 0.65 0.100422 0.0893507 25474 144626 -1 2155 19 1529 2104 148158 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21376 1 0.03 -1 -1 33812 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67800 32 32 340 270 1 212 88 17 17 289 -1 unnamed_device 26.6 MiB 1.79 2505.15 1189 10423 2818 6712 893 66.2 MiB 0.10 0.00 5.54276 4.48922 -143.582 -4.48922 4.48922 0.40 0.000528523 0.000485736 0.0302311 0.0277262 -1 -1 -1 -1 32 2563 23 6.89349e+06 338252 586450. 2029.24 0.61 0.0995462 0.088487 25474 144626 -1 2179 17 1369 2006 128556 30453 3.11651 3.11651 -124.855 -3.11651 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0206707 0.0185081 137 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_059.v common 4.11 vpr 65.82 MiB -1 -1 0.17 21184 1 0.03 -1 -1 33672 -1 -1 32 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67400 30 32 278 235 1 175 94 17 17 289 -1 unnamed_device 26.6 MiB 1.64 2250.9 1061 16282 4606 9784 1892 65.8 MiB 0.12 0.00 5.16569 4.37039 -131.236 -4.37039 4.37039 0.40 0.000457786 0.000419925 0.0356611 0.032628 -1 -1 -1 -1 30 2166 21 6.89349e+06 451003 556674. 1926.21 0.57 0.0920933 0.0818279 25186 138497 -1 1802 21 1102 1807 103448 25235 3.19625 3.19625 -118.702 -3.19625 0 0 706193. 2443.58 0.04 0.05 0.12 -1 -1 0.04 0.0203507 0.018075 118 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_060.v common 10.52 vpr 66.52 MiB -1 -1 0.19 21760 1 0.03 -1 -1 33800 -1 -1 30 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68120 32 32 431 332 1 270 94 17 17 289 -1 unnamed_device 26.8 MiB 3.32 3146.77 1500 9040 1813 6773 454 66.5 MiB 0.11 0.00 7.91759 6.47175 -187.67 -6.47175 6.47175 0.40 0.000688519 0.00063385 0.0308727 0.028301 -1 -1 -1 -1 30 4518 33 6.89349e+06 422815 556674. 1926.21 5.22 0.211553 0.186547 25186 138497 -1 3148 20 2302 3672 257638 59939 5.19193 5.19193 -173.795 -5.19193 0 0 706193. 2443.58 0.04 0.09 0.12 -1 -1 0.04 0.029168 0.0261748 182 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_061.v common 5.26 vpr 66.21 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33824 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67796 32 32 336 268 1 205 88 17 17 289 -1 unnamed_device 26.7 MiB 1.63 2563.49 938 6133 1137 4311 685 66.2 MiB 0.06 0.00 5.66882 4.72832 -140.504 -4.72832 4.72832 0.40 0.000519492 0.000475086 0.0184036 0.0168606 -1 -1 -1 -1 30 2277 25 6.89349e+06 338252 556674. 1926.21 1.77 0.155834 0.1366 25186 138497 -1 1740 21 1371 1956 106500 28103 3.7285 3.7285 -128.734 -3.7285 0 0 706193. 2443.58 0.05 0.05 0.12 -1 -1 0.05 0.0240466 0.0213575 136 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_062.v common 3.30 vpr 65.69 MiB -1 -1 0.16 21152 1 0.03 -1 -1 33404 -1 -1 28 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67264 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 26.4 MiB 0.95 1762.8 895 10649 2847 7198 604 65.7 MiB 0.07 0.00 3.9244 3.74796 -105.814 -3.74796 3.74796 0.40 0.000421028 0.000382259 0.0219318 0.0199625 -1 -1 -1 -1 32 1907 18 6.89349e+06 394628 586450. 2029.24 0.53 0.0700311 0.0618604 25474 144626 -1 1683 19 741 1322 94047 22538 2.77811 2.77811 -100.732 -2.77811 0 0 744469. 2576.02 0.05 0.04 0.13 -1 -1 0.05 0.0164877 0.0146107 96 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_063.v common 6.36 vpr 66.18 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33328 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67764 32 32 349 273 1 214 91 17 17 289 -1 unnamed_device 26.6 MiB 2.08 3131.66 1333 16003 4726 9953 1324 66.2 MiB 0.15 0.00 6.94676 5.62842 -147.88 -5.62842 5.62842 0.40 0.000560729 0.000515901 0.0445939 0.0407675 -1 -1 -1 -1 28 3305 22 6.89349e+06 380534 531479. 1839.03 2.27 0.195241 0.172186 24610 126494 -1 2682 28 1965 3575 322377 90846 4.62905 4.62905 -145.962 -4.62905 0 0 648988. 2245.63 0.04 0.12 0.11 -1 -1 0.04 0.0322026 0.0285363 146 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_064.v common 4.04 vpr 65.56 MiB -1 -1 0.15 21188 1 0.03 -1 -1 33440 -1 -1 21 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67136 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 26.4 MiB 1.29 2118.54 762 14407 5564 6574 2269 65.6 MiB 0.10 0.00 4.4685 3.6244 -108.803 -3.6244 3.6244 0.40 0.000416214 0.00037276 0.0336968 0.0307946 -1 -1 -1 -1 34 1873 19 6.89349e+06 295971 618332. 2139.56 0.89 0.120776 0.106481 25762 151098 -1 1576 20 1144 2018 129507 32747 2.93836 2.93836 -105.161 -2.93836 0 0 787024. 2723.27 0.05 0.05 0.13 -1 -1 0.05 0.0189608 0.0169392 99 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_065.v common 5.00 vpr 65.80 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33732 -1 -1 24 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67384 30 32 278 235 1 175 86 17 17 289 -1 unnamed_device 26.6 MiB 1.32 2564.44 979 14450 4512 7827 2111 65.8 MiB 0.12 0.00 5.48567 4.35797 -127.996 -4.35797 4.35797 0.40 0.000435599 0.0003991 0.0353628 0.0324048 -1 -1 -1 -1 36 1957 19 6.89349e+06 338252 648988. 2245.63 1.77 0.173097 0.152091 26050 158493 -1 1808 20 1073 1527 119771 28008 3.03251 3.03251 -110.587 -3.03251 0 0 828058. 2865.25 0.05 0.05 0.14 -1 -1 0.05 0.0200413 0.0178419 110 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_066.v common 5.35 vpr 66.18 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33812 -1 -1 29 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67772 29 32 355 287 1 223 90 17 17 289 -1 unnamed_device 26.6 MiB 2.59 2780.49 1191 14763 4697 7304 2762 66.2 MiB 0.13 0.00 5.58293 4.61427 -132.686 -4.61427 4.61427 0.40 0.000532196 0.000487715 0.0410406 0.0375515 -1 -1 -1 -1 30 3049 25 6.89349e+06 408721 556674. 1926.21 0.81 0.117291 0.10434 25186 138497 -1 2192 20 1332 1984 126484 30449 3.53954 3.53954 -123.542 -3.53954 0 0 706193. 2443.58 0.04 0.06 0.12 -1 -1 0.04 0.0241763 0.021531 150 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_067.v common 5.30 vpr 66.20 MiB -1 -1 0.17 21760 1 0.03 -1 -1 33492 -1 -1 27 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67792 32 32 358 289 1 230 91 17 17 289 -1 unnamed_device 26.6 MiB 2.58 2704.1 1306 16819 4681 10419 1719 66.2 MiB 0.16 0.00 6.50098 4.98955 -155.576 -4.98955 4.98955 0.40 0.000571594 0.000523597 0.0475584 0.0435285 -1 -1 -1 -1 30 2937 26 6.89349e+06 380534 556674. 1926.21 0.75 0.123954 0.110487 25186 138497 -1 2245 22 1603 2359 152417 37029 4.30739 4.30739 -148.653 -4.30739 0 0 706193. 2443.58 0.04 0.07 0.12 -1 -1 0.04 0.0260223 0.023152 149 54 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_068.v common 6.47 vpr 66.34 MiB -1 -1 0.18 21376 1 0.03 -1 -1 33704 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67932 32 32 353 285 1 227 89 17 17 289 -1 unnamed_device 26.8 MiB 2.66 2686.87 1302 16325 4887 9512 1926 66.3 MiB 0.16 0.00 6.75127 5.45967 -157.907 -5.45967 5.45967 0.40 0.00056071 0.000513665 0.0490684 0.0450963 -1 -1 -1 -1 32 3207 28 6.89349e+06 352346 586450. 2029.24 1.83 0.213456 0.188821 25474 144626 -1 2586 20 1684 2404 179283 42901 4.41465 4.41465 -148.072 -4.41465 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0242825 0.021627 144 51 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_069.v common 4.12 vpr 65.60 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33836 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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4.5444 3.71371 -124.876 -3.71371 3.71371 0.40 0.000510866 0.000471346 0.0395975 0.03638 -1 -1 -1 -1 32 2615 24 6.89349e+06 310065 586450. 2029.24 0.84 0.124832 0.111207 25474 144626 -1 2155 20 1436 1979 151305 34038 3.11681 3.11681 -119.229 -3.11681 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0217191 0.0193575 125 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_071.v common 4.88 vpr 65.87 MiB -1 -1 0.18 21380 1 0.03 -1 -1 33704 -1 -1 27 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67452 30 32 329 273 1 213 89 17 17 289 -1 unnamed_device 26.4 MiB 2.28 2646.86 1203 12761 3384 8201 1176 65.9 MiB 0.11 0.00 4.5069 3.773 -110.836 -3.773 3.773 0.40 0.000495349 0.000453869 0.0339389 0.0310581 -1 -1 -1 -1 28 2719 25 6.89349e+06 380534 531479. 1839.03 0.68 0.105922 0.094156 24610 126494 -1 2355 23 1698 2575 179984 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4.68052 -134.297 -4.68052 4.68052 0.40 0.000464298 0.000424485 0.0337931 0.0308336 -1 -1 -1 -1 28 2586 32 6.89349e+06 465097 531479. 1839.03 0.83 0.105195 0.0932046 24610 126494 -1 2233 21 1356 2590 184684 43970 3.7486 3.7486 -127.386 -3.7486 0 0 648988. 2245.63 0.04 0.07 0.11 -1 -1 0.04 0.0220418 0.0195788 130 4 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_076.v common 5.14 vpr 66.27 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33428 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67860 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 26.7 MiB 2.37 2819.82 1059 14128 4377 7080 2671 66.3 MiB 0.13 0.00 5.69108 4.79682 -149.315 -4.79682 4.79682 0.40 0.000558899 0.000513841 0.0414871 0.0380499 -1 -1 -1 -1 32 3277 25 6.89349e+06 338252 586450. 2029.24 0.82 0.11718 0.104466 25474 144626 -1 2485 21 1571 2394 192040 46260 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1 0.03 -1 -1 33312 -1 -1 29 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68060 32 32 387 309 1 248 93 17 17 289 -1 unnamed_device 27.0 MiB 2.85 3397.34 1403 9753 2450 6663 640 66.5 MiB 0.11 0.00 6.15614 4.89732 -157.729 -4.89732 4.89732 0.40 0.000654561 0.000600893 0.031079 0.0284991 -1 -1 -1 -1 30 3380 44 6.89349e+06 408721 556674. 1926.21 3.03 0.230628 0.202818 25186 138497 -1 2595 25 1739 2588 198522 60893 3.6793 3.6793 -139.247 -3.6793 0 0 706193. 2443.58 0.04 0.09 0.12 -1 -1 0.04 0.030538 0.0271646 163 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_079.v common 5.59 vpr 65.62 MiB -1 -1 0.16 21440 1 0.03 -1 -1 33548 -1 -1 22 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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6.44811 5.32081 -161.537 -5.32081 5.32081 0.40 0.000597835 0.000532931 0.0316521 0.0289248 -1 -1 -1 -1 32 2776 22 6.89349e+06 408721 586450. 2029.24 0.88 0.126997 0.112127 25474 144626 -1 2263 22 1740 2440 158102 37949 4.34048 4.34048 -151.044 -4.34048 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0262967 0.0233628 159 63 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_081.v common 5.83 vpr 66.10 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33680 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67688 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 26.5 MiB 1.51 2640.23 1115 15929 4674 9363 1892 66.1 MiB 0.14 0.00 5.91759 5.15905 -149.313 -5.15905 5.15905 0.40 0.000553012 0.00050931 0.0451847 0.0414968 -1 -1 -1 -1 30 2756 43 6.89349e+06 352346 556674. 1926.21 2.35 0.207188 0.182848 25186 138497 -1 2161 22 1543 2715 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0.19 21760 1 0.03 -1 -1 33792 -1 -1 30 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67720 30 32 377 310 1 239 92 17 17 289 -1 unnamed_device 26.6 MiB 2.86 3082.09 1366 15203 4659 8048 2496 66.1 MiB 0.15 0.00 6.31486 5.05771 -146.598 -5.05771 5.05771 0.40 0.000542782 0.000497335 0.0434354 0.0398009 -1 -1 -1 -1 32 3035 25 6.89349e+06 422815 586450. 2029.24 1.12 0.167084 0.147676 25474 144626 -1 2488 19 1535 2212 153501 36168 4.07179 4.07179 -139.125 -4.07179 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.0243526 0.0218338 160 83 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_084.v common 8.87 vpr 66.28 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33656 -1 -1 25 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67872 32 32 365 294 1 230 89 17 17 289 -1 unnamed_device 26.7 MiB 2.78 2852.25 1197 16721 4780 9058 2883 66.3 MiB 0.16 0.00 6.82527 5.53568 -158.256 -5.53568 5.53568 0.40 0.000531987 0.000486476 0.0487401 0.0445979 -1 -1 -1 -1 32 3576 47 6.89349e+06 352346 586450. 2029.24 4.09 0.265897 0.234144 25474 144626 -1 2565 23 1854 2748 186626 47226 4.57575 4.57575 -152.108 -4.57575 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.0278236 0.0248116 150 57 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 5.39 vpr 66.31 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33472 -1 -1 31 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67900 29 32 378 310 1 246 92 17 17 289 -1 unnamed_device 26.8 MiB 2.61 2857.69 1221 11684 3249 7028 1407 66.3 MiB 0.11 0.00 5.69689 4.40161 -128.825 -4.40161 4.40161 0.40 0.000543002 0.000498767 0.0335662 0.0307277 -1 -1 -1 -1 30 3093 22 6.89349e+06 436909 556674. 1926.21 0.84 0.108341 0.0962044 25186 138497 -1 2297 20 1507 2044 138797 32504 3.501 3.501 -118.443 -3.501 0 0 706193. 2443.58 0.04 0.06 0.12 -1 -1 0.04 0.0241457 0.0215625 162 85 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 3.72 vpr 65.44 MiB -1 -1 0.16 21184 1 0.03 -1 -1 33596 -1 -1 18 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67012 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 26.3 MiB 1.30 1910.19 928 13788 4105 7638 2045 65.4 MiB 0.10 0.00 4.56098 4.02268 -121.319 -4.02268 4.02268 0.40 0.000403293 0.00036855 0.0331905 0.0303715 -1 -1 -1 -1 32 1927 19 6.89349e+06 253689 586450. 2029.24 0.55 0.0851728 0.0756909 25474 144626 -1 1681 21 920 1495 107983 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4.71133 3.85018 -110.918 -3.85018 3.85018 0.40 0.000416582 0.000382265 0.0175819 0.0160875 -1 -1 -1 -1 32 1849 29 6.89349e+06 310065 586450. 2029.24 0.58 0.0757516 0.0668488 25474 144626 -1 1570 22 1028 1743 120940 28119 2.68156 2.68156 -100.836 -2.68156 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0195237 0.0173184 100 4 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_091.v common 4.69 vpr 66.15 MiB -1 -1 0.18 21760 1 0.03 -1 -1 33852 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67740 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 26.5 MiB 2.14 2676 992 7498 1482 5699 317 66.2 MiB 0.08 0.00 5.50572 4.70278 -144.908 -4.70278 4.70278 0.40 0.000550001 0.000502405 0.0226492 0.0207162 -1 -1 -1 -1 32 2909 34 6.89349e+06 338252 586450. 2029.24 0.67 0.101573 0.0895928 25474 144626 -1 2253 22 1627 2244 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67800 30 32 316 264 1 208 90 17 17 289 -1 unnamed_device 26.6 MiB 2.15 2512.01 1190 14964 4488 8490 1986 66.2 MiB 0.13 0.00 4.62558 3.81699 -112.298 -3.81699 3.81699 0.40 0.000481503 0.000441445 0.0384964 0.035231 -1 -1 -1 -1 26 3067 40 6.89349e+06 394628 503264. 1741.40 0.79 0.121968 0.108323 24322 120374 -1 2498 25 1969 2907 216295 52301 3.24031 3.24031 -110.694 -3.24031 0 0 618332. 2139.56 0.04 0.08 0.11 -1 -1 0.04 0.0265804 0.023626 133 52 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_095.v common 3.96 vpr 65.61 MiB -1 -1 0.17 20992 1 0.03 -1 -1 33856 -1 -1 24 27 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67188 27 32 255 219 1 162 83 17 17 289 -1 unnamed_device 26.4 MiB 1.58 1709.45 895 11423 3598 6289 1536 65.6 MiB 0.08 0.00 5.37186 4.45989 -120.873 -4.45989 4.45989 0.40 0.000404764 0.000370527 0.0276665 0.0253438 -1 -1 -1 -1 32 1885 21 6.89349e+06 338252 586450. 2029.24 0.54 0.0800602 0.0710102 25474 144626 -1 1605 17 829 1207 77343 18883 3.505 3.505 -112.859 -3.505 0 0 744469. 2576.02 0.05 0.04 0.13 -1 -1 0.05 0.0169659 0.01519 104 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_096.v common 7.06 vpr 66.38 MiB -1 -1 0.19 21568 1 0.03 -1 -1 33428 -1 -1 31 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67968 32 32 421 327 1 271 95 17 17 289 -1 unnamed_device 26.9 MiB 2.93 3336.36 1622 10031 2688 6663 680 66.4 MiB 0.12 0.00 5.75687 4.62005 -147.849 -4.62005 4.62005 0.40 0.000696925 0.000642627 0.0327507 0.0300167 -1 -1 -1 -1 34 3780 25 6.89349e+06 436909 618332. 2139.56 2.12 0.229169 0.201909 25762 151098 -1 3115 24 2209 3436 253416 59122 4.16199 4.16199 -149.457 -4.16199 0 0 787024. 2723.27 0.05 0.09 0.13 -1 -1 0.05 0.031952 0.0284386 181 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_097.v common 6.64 vpr 66.39 MiB -1 -1 0.19 21760 1 0.03 -1 -1 33456 -1 -1 26 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67984 31 32 365 296 1 233 89 17 17 289 -1 unnamed_device 26.8 MiB 2.42 2877.21 1208 11969 3276 7602 1091 66.4 MiB 0.11 0.00 6.6941 5.72098 -165.595 -5.72098 5.72098 0.40 0.000562276 0.000516497 0.0352915 0.0323214 -1 -1 -1 -1 28 3300 41 6.89349e+06 366440 531479. 1839.03 2.25 0.20394 0.179295 24610 126494 -1 2570 24 2361 3486 283212 75169 4.70325 4.70325 -158.898 -4.70325 0 0 648988. 2245.63 0.04 0.10 0.11 -1 -1 0.04 0.0295363 0.0263604 151 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_098.v common 6.07 vpr 66.20 MiB -1 -1 0.17 21388 1 0.03 -1 -1 33228 -1 -1 23 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67792 32 32 331 280 1 221 87 17 17 289 -1 unnamed_device 26.4 MiB 2.30 2547 1236 13143 3385 7634 2124 66.2 MiB 0.11 0.00 5.09387 4.31283 -143.388 -4.31283 4.31283 0.40 0.000507181 0.000465533 0.0363921 0.0333505 -1 -1 -1 -1 32 2878 24 6.89349e+06 324158 586450. 2029.24 1.85 0.196693 0.172828 25474 144626 -1 2349 17 1428 1846 145504 32918 3.4249 3.4249 -136.914 -3.4249 0 0 744469. 2576.02 0.05 0.06 0.13 -1 -1 0.05 0.019776 0.0176732 132 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_099.v common 5.34 vpr 66.25 MiB -1 -1 0.17 21376 1 0.03 -1 -1 33996 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67844 32 32 326 263 1 203 88 17 17 289 -1 unnamed_device 26.6 MiB 2.38 2319.56 1186 11593 3417 7038 1138 66.3 MiB 0.11 0.00 6.11951 5.26542 -147.058 -5.26542 5.26542 0.40 0.000520036 0.000477215 0.0323952 0.0296997 -1 -1 -1 -1 30 2530 20 6.89349e+06 338252 556674. 1926.21 0.71 0.0982735 0.0875376 25186 138497 -1 2079 20 1172 1728 106041 25591 3.68526 3.68526 -129.365 -3.68526 0 0 706193. 2443.58 0.04 0.05 0.12 -1 -1 0.04 0.0221194 0.0196951 131 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_100.v common 5.38 vpr 66.38 MiB -1 -1 0.19 21504 1 0.03 -1 -1 33524 -1 -1 28 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67976 31 32 373 294 1 231 91 17 17 289 -1 unnamed_device 26.6 MiB 2.26 2642.2 1256 14779 4453 8038 2288 66.4 MiB 0.15 0.00 5.36757 4.59895 -134.189 -4.59895 4.59895 0.40 0.000547296 0.000500536 0.043776 0.0400592 -1 -1 -1 -1 32 3173 38 6.89349e+06 394628 586450. 2029.24 0.73 0.131644 0.117069 25474 144626 -1 2452 20 1766 2694 161607 40389 3.7049 3.7049 -127.06 -3.7049 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0248467 0.0221516 158 50 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_101.v common 5.92 vpr 65.98 MiB -1 -1 0.18 21492 1 0.03 -1 -1 33904 -1 -1 27 30 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67564 30 32 325 268 1 210 89 17 17 289 -1 unnamed_device 26.4 MiB 2.44 2491.63 1236 16127 5449 8772 1906 66.0 MiB 0.15 0.00 5.01568 4.19935 -122.054 -4.19935 4.19935 0.41 0.000496206 0.00045461 0.0428741 0.0392525 -1 -1 -1 -1 30 2823 24 6.89349e+06 380534 556674. 1926.21 1.52 0.174154 0.153708 25186 138497 -1 2147 19 1174 1822 99203 24322 3.3089 3.3089 -112.105 -3.3089 0 0 706193. 2443.58 0.04 0.05 0.12 -1 -1 0.04 0.0209029 0.0186473 134 51 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_102.v common 5.35 vpr 66.46 MiB -1 -1 0.17 21760 1 0.03 -1 -1 33652 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68060 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 26.8 MiB 2.70 2911 1310 14518 4784 8068 1666 66.5 MiB 0.14 0.00 5.92998 4.94548 -157.398 -4.94548 4.94548 0.40 0.000525289 0.000481389 0.0422505 0.0386644 -1 -1 -1 -1 32 3075 21 6.89349e+06 338252 586450. 2029.24 0.69 0.113093 0.100846 25474 144626 -1 2582 19 1599 2521 181828 41329 3.8255 3.8255 -143.285 -3.8255 0 0 744469. 2576.02 0.05 0.07 0.13 -1 -1 0.05 0.0225812 0.0201421 143 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_103.v common 7.23 vpr 66.62 MiB -1 -1 0.18 21720 1 0.03 -1 -1 33748 -1 -1 29 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68220 32 32 386 307 1 246 93 17 17 289 -1 unnamed_device 27.1 MiB 2.90 2578.38 1298 15003 5029 6794 3180 66.6 MiB 0.13 0.00 4.8916 4.41987 -141.505 -4.41987 4.41987 0.40 0.000582135 0.000533453 0.0446663 0.040999 -1 -1 -1 -1 38 2790 25 6.89349e+06 408721 678818. 2348.85 2.33 0.233436 0.205183 26626 170182 -1 2305 19 1787 2513 158448 40154 3.08571 3.08571 -121.519 -3.08571 0 0 902133. 3121.57 0.05 0.07 0.15 -1 -1 0.05 0.0251585 0.0225277 160 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_104.v common 4.00 vpr 65.43 MiB -1 -1 0.17 21572 1 0.03 -1 -1 33800 -1 -1 22 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67000 29 32 269 229 1 173 83 17 17 289 -1 unnamed_device 26.0 MiB 1.57 1941.63 910 12863 3836 6875 2152 65.4 MiB 0.10 0.00 4.94313 4.20923 -126.635 -4.20923 4.20923 0.40 0.000420108 0.000383871 0.032025 0.0292841 -1 -1 -1 -1 32 1926 20 6.89349e+06 310065 586450. 2029.24 0.56 0.0857512 0.0762094 25474 144626 -1 1656 17 1156 1555 92058 22626 3.09326 3.09326 -114.844 -3.09326 0 0 744469. 2576.02 0.05 0.04 0.13 -1 -1 0.05 0.016789 0.0149883 108 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_105.v common 5.70 vpr 65.82 MiB -1 -1 0.17 21212 1 0.03 -1 -1 33688 -1 -1 21 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67400 32 32 310 266 1 198 85 17 17 289 -1 unnamed_device 26.5 MiB 1.81 2382 1201 14407 3996 8426 1985 65.8 MiB 0.12 0.00 5.35099 4.42023 -136.119 -4.42023 4.42023 0.40 0.000470369 0.000431313 0.0388991 0.0356765 -1 -1 -1 -1 28 2784 29 6.89349e+06 295971 531479. 1839.03 1.98 0.20324 0.179166 24610 126494 -1 2361 21 1699 2350 183355 42986 3.6173 3.6173 -133.463 -3.6173 0 0 648988. 2245.63 0.04 0.07 0.11 -1 -1 0.04 0.021993 0.019535 121 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_106.v common 4.58 vpr 66.26 MiB -1 -1 0.17 21760 1 0.03 -1 -1 33396 -1 -1 26 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67852 31 32 326 261 1 204 89 17 17 289 -1 unnamed_device 26.8 MiB 1.75 2471.57 1196 14741 4167 8661 1913 66.3 MiB 0.13 0.00 5.98928 4.87948 -139.23 -4.87948 4.87948 0.40 0.000541713 0.000498559 0.0397752 0.0364746 -1 -1 -1 -1 26 2979 26 6.89349e+06 366440 503264. 1741.40 0.89 0.111783 0.0994055 24322 120374 -1 2528 23 1727 2832 223076 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0.03 -1 -1 33008 -1 -1 20 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67096 32 32 278 238 1 182 84 17 17 289 -1 unnamed_device 26.1 MiB 2.08 2104.15 987 9783 2387 6626 770 65.5 MiB 0.08 0.00 4.70867 4.35067 -135.694 -4.35067 4.35067 0.40 0.000445611 0.000408327 0.0256719 0.0235263 -1 -1 -1 -1 30 2303 24 6.89349e+06 281877 556674. 1926.21 0.68 0.0868897 0.0770788 25186 138497 -1 1908 20 1074 1579 114728 26659 2.90386 2.90386 -115.495 -2.90386 0 0 706193. 2443.58 0.04 0.05 0.12 -1 -1 0.04 0.020224 0.0180494 109 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 6.41 vpr 66.30 MiB -1 -1 0.19 21340 1 0.03 -1 -1 33616 -1 -1 29 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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3.59765 -110.566 -3.59765 3.59765 0.40 0.000428824 0.00039322 0.016294 0.0149251 -1 -1 -1 -1 34 2076 24 6.89349e+06 281877 618332. 2139.56 0.90 0.108899 0.0951904 25762 151098 -1 1723 20 1130 1580 102110 25750 2.82336 2.82336 -104.389 -2.82336 0 0 787024. 2723.27 0.05 0.05 0.13 -1 -1 0.05 0.0186244 0.0165692 103 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_111.v common 6.38 vpr 66.18 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33676 -1 -1 24 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67764 32 32 349 286 1 221 88 17 17 289 -1 unnamed_device 26.7 MiB 2.23 2652.86 1153 10618 2798 6496 1324 66.2 MiB 0.10 0.00 4.83964 4.22755 -121.823 -4.22755 4.22755 0.40 0.000556066 0.000510016 0.0313087 0.0286859 -1 -1 -1 -1 30 2832 29 6.89349e+06 338252 556674. 1926.21 2.24 0.188646 0.166223 25186 138497 -1 2128 20 1218 1839 143485 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0.17 21376 1 0.03 -1 -1 33656 -1 -1 22 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67768 32 32 303 262 1 200 86 17 17 289 -1 unnamed_device 26.4 MiB 2.47 2386 1042 7835 1872 5487 476 66.2 MiB 0.07 0.00 5.08019 3.80489 -117.759 -3.80489 3.80489 0.40 0.00047309 0.000433891 0.0211671 0.0193543 -1 -1 -1 -1 28 2564 37 6.89349e+06 310065 531479. 1839.03 1.65 0.172994 0.150813 24610 126494 -1 2193 23 1665 2221 167400 42588 3.0568 3.0568 -117.858 -3.0568 0 0 648988. 2245.63 0.04 0.07 0.11 -1 -1 0.04 0.0234319 0.0207559 121 57 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 4.40 vpr 65.49 MiB -1 -1 0.17 21568 1 0.03 -1 -1 33452 -1 -1 19 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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5.66222 4.93863 -135.261 -4.93863 4.93863 0.40 0.000510929 0.000467306 0.0423715 0.0387918 -1 -1 -1 -1 32 2576 20 6.89349e+06 324158 586450. 2029.24 0.60 0.106418 0.0949755 25474 144626 -1 2067 20 1241 1762 109322 26595 3.75376 3.75376 -127.245 -3.75376 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0219214 0.0195869 130 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_116.v common 4.66 vpr 66.23 MiB -1 -1 0.18 21376 1 0.03 -1 -1 33504 -1 -1 28 29 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67816 29 32 324 268 1 205 89 17 17 289 -1 unnamed_device 26.6 MiB 2.02 2470.58 1190 15335 4895 8484 1956 66.2 MiB 0.13 0.00 4.7462 4.04278 -114.91 -4.04278 4.04278 0.40 0.000513387 0.000469772 0.0407129 0.0372905 -1 -1 -1 -1 32 2572 19 6.89349e+06 394628 586450. 2029.24 0.57 0.103196 0.0920696 25474 144626 -1 2079 21 1060 1535 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0.16 21184 1 0.03 -1 -1 33808 -1 -1 18 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67132 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 26.4 MiB 1.35 1779.7 858 10231 2722 6503 1006 65.6 MiB 0.07 0.00 3.8889 3.28224 -101.713 -3.28224 3.28224 0.40 0.000386823 0.00035363 0.024554 0.0224561 -1 -1 -1 -1 30 1861 20 6.89349e+06 253689 556674. 1926.21 0.65 0.0751525 0.0664708 25186 138497 -1 1517 18 846 1343 70273 18201 2.62851 2.62851 -97.2865 -2.62851 0 0 706193. 2443.58 0.04 0.04 0.12 -1 -1 0.04 0.0164274 0.0146273 93 4 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 8.49 vpr 66.56 MiB -1 -1 0.18 21952 1 0.03 -1 -1 33616 -1 -1 31 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 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6.46753 4.88508 -165.762 -4.88508 4.88508 0.40 0.000575811 0.000529011 0.0462819 0.0423455 -1 -1 -1 -1 32 3183 28 6.89349e+06 380534 586450. 2029.24 0.73 0.12561 0.111809 25474 144626 -1 2491 25 2528 3166 224020 53853 4.22909 4.22909 -157.565 -4.22909 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.0285338 0.0253227 154 96 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 4.72 vpr 66.33 MiB -1 -1 0.18 21376 1 0.03 -1 -1 33472 -1 -1 26 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67924 32 32 360 293 1 226 90 17 17 289 -1 unnamed_device 26.8 MiB 2.07 2575.46 1214 14964 4303 8067 2594 66.3 MiB 0.14 0.00 4.49365 4.08378 -125.708 -4.08378 4.08378 0.40 0.000524709 0.000481381 0.042598 0.0390311 -1 -1 -1 -1 32 2729 24 6.89349e+06 366440 586450. 2029.24 0.70 0.117428 0.104625 25474 144626 -1 2198 20 1376 1919 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5.39489 4.40387 -142.112 -4.40387 4.40387 0.40 0.00047257 0.00043404 0.0181654 0.0166452 -1 -1 -1 -1 32 2461 22 6.89349e+06 310065 586450. 2029.24 0.63 0.079686 0.070405 25474 144626 -1 2000 16 1036 1938 114017 27700 3.4032 3.4032 -130.786 -3.4032 0 0 744469. 2576.02 0.05 0.05 0.13 -1 -1 0.05 0.0175707 0.0157326 117 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 4.11 vpr 65.62 MiB -1 -1 0.16 21184 1 0.03 -1 -1 33588 -1 -1 22 25 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 67200 25 32 216 194 1 138 79 17 17 289 -1 unnamed_device 26.4 MiB 1.48 1444.4 623 8698 3045 3646 2007 65.6 MiB 0.06 0.00 4.2673 3.669 -85.1281 -3.669 3.669 0.40 0.000361923 0.000332104 0.020369 0.0186684 -1 -1 -1 -1 34 1477 40 6.89349e+06 310065 618332. 2139.56 0.85 0.107181 0.0936158 25762 151098 -1 1167 17 675 1007 65080 17606 2.74431 2.74431 -76.9396 -2.74431 0 0 787024. 2723.27 0.05 0.03 0.13 -1 -1 0.05 0.014018 0.0124748 88 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 7.41 vpr 66.41 MiB -1 -1 0.18 21568 1 0.03 -1 -1 33264 -1 -1 26 32 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68008 32 32 376 307 1 242 90 17 17 289 -1 unnamed_device 26.7 MiB 3.43 3193.1 1465 10944 2673 7207 1064 66.4 MiB 0.12 0.00 5.46078 4.53299 -135.972 -4.53299 4.53299 0.40 0.000623648 0.00055563 0.0356601 0.0326692 -1 -1 -1 -1 32 3429 25 6.89349e+06 366440 586450. 2029.24 2.01 0.225054 0.197903 25474 144626 -1 2893 20 2025 3056 210442 49060 3.78786 3.78786 -136.336 -3.78786 0 0 744469. 2576.02 0.05 0.08 0.13 -1 -1 0.05 0.0257872 0.0230014 155 72 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 6.14 vpr 66.72 MiB -1 -1 0.19 21760 1 0.03 -1 -1 33708 -1 -1 33 31 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68320 31 32 409 331 1 264 96 17 17 289 -1 unnamed_device 27.0 MiB 2.98 3421.59 1405 9951 2248 6876 827 66.7 MiB 0.11 0.00 6.59166 4.95446 -159.482 -4.95446 4.95446 0.40 0.000640003 0.000586512 0.0309365 0.0282444 -1 -1 -1 -1 26 4013 41 6.89349e+06 465097 503264. 1741.40 1.19 0.132528 0.117135 24322 120374 -1 3056 21 2358 3239 221980 53983 4.35939 4.35939 -160.133 -4.35939 0 0 618332. 2139.56 0.04 0.08 0.11 -1 -1 0.04 0.0286758 0.0256049 174 90 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt index 9c26386bee3..01b902e78ab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt @@ -49,4 +49,4 @@ pass_requirements_file=pass_requirements.txt # Script Parameters # Increase relaxed channel width routing iterations to avoid potential unroutes due to RR graph changes -script_params=-track_memory_usage -crit_path_router_iterations 80 --routing_failure_predictor off --seed 5 +script_params=-track_memory_usage -crit_path_router_iterations 80 --routing_failure_predictor off --seed 3 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index 8d45c568ac5..645c75e2821 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,20 +1,20 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 212.47 vpr 279.51 MiB -1 -1 19.33 119976 20 47.22 -1 -1 68076 -1 -1 855 133 25 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 286220 133 179 14228 14085 1 7100 1192 37 37 1369 clb auto 135.8 MiB 30.67 264290 118331 588673 187049 381129 20495 196.5 MiB 10.93 0.10 32.7899 22.873 -208698 -22.873 22.873 1.43 0.0324797 0.0292432 3.84677 3.23963 -1 -1 -1 -1 110 176725 27 7.54166e+07 5.97803e+07 9.46577e+06 6914.37 87.45 21.2205 17.8322 201652 2027183 -1 162249 14 30432 117983 9007020 1696919 24.0504 24.0504 -216487 -24.0504 0 0 1.20852e+07 8827.75 0.45 3.53 1.54 -1 -1 0.45 1.77327 1.56805 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 482.62 vpr 710.52 MiB -1 -1 45.25 619668 14 76.05 -1 -1 122284 -1 -1 2726 257 0 11 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 727576 257 32 36080 33722 1 19365 3026 63 63 3969 clb auto 329.7 MiB 70.76 1 246198 2147070 770352 1350261 26457 710.5 MiB 79.70 0.59 60.4933 18.7554 -25815 -18.7554 18.7554 16.05 0.0947419 0.0860547 13.1929 10.7692 -1 -1 -1 -1 72 383970 26 2.36641e+08 1.51273e+08 1.98694e+07 5006.15 146.80 56.49 46.364 498330 4113940 -1 361584 22 95063 428737 17085321 2684393 19.1335 19.1335 -26346.5 -19.1335 0 0 2.48734e+07 6266.93 1.24 12.09 2.89 -1 -1 1.24 6.67177 5.73047 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 68.96 parmys 254.32 MiB -1 -1 10.19 260420 5 3.55 -1 -1 54908 -1 -1 495 36 0 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 143288 36 100 10178 7632 1 2724 631 29 29 841 clb auto 96.0 MiB 15.82 95360 41180 227851 69677 144196 13978 139.9 MiB 4.01 0.04 22.4661 14.8203 -2362.24 -14.8203 14.8203 0.86 0.0174468 0.0161202 1.90119 1.64273 -1 -1 -1 -1 68 66817 22 4.4999e+07 2.66775e+07 3.78783e+06 4503.96 24.80 6.79508 5.87269 99460 760244 -1 60459 14 12442 64371 2376927 356438 15.0178 15.0178 -2542.17 -15.0178 0 0 4.70015e+06 5588.76 0.18 1.64 0.67 -1 -1 0.18 0.999677 0.893759 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 15.71 vpr 71.91 MiB -1 -1 11.65 44576 3 0.60 -1 -1 35600 -1 -1 47 196 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73640 196 193 1201 1346 1 592 437 15 15 225 io auto 33.1 MiB 0.52 7097 3082 141282 36274 93188 11820 71.9 MiB 0.39 0.01 2.88013 2.23271 -1111.45 -2.23271 2.23271 0.17 0.00181996 0.00167433 0.170233 0.157242 -1 -1 -1 -1 38 6015 35 1.03862e+07 3.08102e+06 544116. 2418.30 0.99 0.562766 0.519528 21558 109668 -1 5038 10 1765 2614 165080 48924 2.65248 2.65248 -1216.21 -2.65248 0 0 690508. 3068.92 0.02 0.10 0.06 -1 -1 0.02 0.070957 0.0676966 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.27 vpr 66.99 MiB -1 -1 0.38 18464 3 0.07 -1 -1 33120 -1 -1 68 99 1 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68596 99 130 344 474 1 228 298 12 12 144 clb auto 28.3 MiB 0.16 1708 681 71938 21850 35232 14856 67.0 MiB 0.12 0.00 2.12112 1.86413 -119.258 -1.86413 1.86413 0.10 0.000566216 0.000530411 0.0447479 0.0419328 -1 -1 -1 -1 42 1388 10 5.66058e+06 4.21279e+06 345696. 2400.67 0.67 0.20809 0.190737 13090 66981 -1 1237 10 456 706 29446 8797 1.96058 1.96058 -139.503 -1.96058 0 0 434636. 3018.30 0.01 0.03 0.04 -1 -1 0.01 0.0198907 0.018763 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 6.34 vpr 70.60 MiB -1 -1 0.40 22304 5 0.21 -1 -1 33772 -1 -1 32 162 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72292 162 96 1075 892 1 666 295 16 16 256 mult_36 auto 31.3 MiB 0.47 8262 5112 85642 26726 51784 7132 70.6 MiB 0.61 0.01 16.5991 15.8982 -1286.15 -15.8982 15.8982 0.35 0.00310373 0.00289519 0.287074 0.267623 -1 -1 -1 -1 52 9636 23 1.21132e+07 3.70461e+06 805949. 3148.24 2.31 0.817068 0.760008 26552 162987 -1 8698 17 2587 4144 731400 221181 17.1356 17.1356 -1376.18 -17.1356 0 0 1.06067e+06 4143.25 0.04 0.37 0.15 -1 -1 0.04 0.174555 0.164858 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 18.31 vpr 68.98 MiB -1 -1 0.20 21540 5 0.09 -1 -1 33460 -1 -1 21 66 0 5 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70640 66 96 778 595 1 468 188 16 16 256 mult_36 auto 29.4 MiB 0.36 6204 3763 43766 14011 25945 3810 69.0 MiB 0.21 0.00 13.1588 11.8959 -748.769 -11.8959 11.8959 0.19 0.00113406 0.00106371 0.101179 0.0951234 -1 -1 -1 -1 60 7674 24 1.21132e+07 3.11177e+06 934704. 3651.19 15.60 0.842417 0.781631 27828 185084 -1 6554 21 3570 7405 1259231 373839 12.6374 12.6374 -804.724 -12.6374 0 0 1.17753e+06 4599.72 0.05 0.41 0.19 -1 -1 0.05 0.119941 0.113336 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 397.07 vpr 588.61 MiB -1 -1 47.51 442352 97 87.76 -1 -1 111932 -1 -1 2144 114 45 8 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 602736 114 102 35834 31925 1 16899 2413 56 56 3136 clb auto 309.4 MiB 53.73 920886 213746 1814349 675153 1108132 31064 588.6 MiB 55.30 0.51 154.738 72.3421 -53235.9 -72.3421 72.3421 11.14 0.111004 0.0889287 11.5817 9.28701 -1 -1 -1 -1 86 321106 26 1.8697e+08 1.43379e+08 1.79819e+07 5734.03 92.36 40.2067 32.6519 420342 3799571 -1 296141 22 64120 253670 12914238 2332073 74.2773 74.2773 -68437.4 -74.2773 0 0 2.27638e+07 7258.87 1.70 13.36 4.62 -1 -1 1.70 8.68523 7.49958 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 50.68 vpr 315.80 MiB -1 -1 10.11 117064 5 5.53 -1 -1 44796 -1 -1 468 506 44 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 323384 506 553 3236 3734 1 2870 1571 50 50 2500 memory auto 57.7 MiB 3.71 43258 16890 1151825 563056 405712 183057 315.8 MiB 3.48 0.04 10.3136 6.751 -2071.22 -6.751 6.751 9.71 0.012349 0.0113575 1.79514 1.64399 -1 -1 -1 -1 38 24480 15 1.47946e+08 4.9335e+07 6.86579e+06 2746.32 9.05 5.36946 5.00747 258216 1426232 -1 23492 14 4552 6284 1218142 310467 6.93887 6.93887 -2608.52 -6.93887 0 0 8.69102e+06 3476.41 0.38 0.71 1.07 -1 -1 0.38 0.528311 0.503268 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 8.15 vpr 73.20 MiB -1 -1 0.80 25764 2 0.10 -1 -1 34472 -1 -1 32 311 15 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74952 311 156 1015 1158 1 965 514 28 28 784 memory auto 33.9 MiB 0.79 20788 7954 214546 78290 125007 11249 73.2 MiB 0.67 0.01 5.14999 3.96264 -4383.87 -3.96264 3.96264 0.70 0.00278678 0.00248288 0.315079 0.280645 -1 -1 -1 -1 38 13997 22 4.25198e+07 9.94461e+06 2.03941e+06 2601.29 2.23 0.858239 0.774237 77878 418209 -1 12797 12 2813 3148 647576 204191 4.19809 4.19809 -4942.1 -4.19809 -0.00135869 -0.00135869 2.58563e+06 3298.00 0.09 0.23 0.25 -1 -1 0.09 0.125259 0.116996 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 19.47 vpr 83.66 MiB -1 -1 4.55 51492 5 1.45 -1 -1 39328 -1 -1 166 193 5 0 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85672 193 205 2718 2652 1 1364 569 20 20 400 memory auto 44.0 MiB 1.94 21635 10677 236269 74431 136781 25057 83.7 MiB 1.26 0.01 6.95823 5.89435 -2880.21 -5.89435 5.89435 0.33 0.00448873 0.00407934 0.520725 0.458822 -1 -1 -1 -1 50 19020 48 2.07112e+07 1.16864e+07 1.26946e+06 3173.65 7.33 2.53112 2.27541 41784 253636 -1 16909 18 4979 12133 652802 138307 6.28852 6.28852 -3109.62 -6.28852 -0.00135869 -0.00135869 1.63222e+06 4080.54 0.05 0.37 0.15 -1 -1 0.05 0.246451 0.229778 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 112.46 vpr 101.39 MiB -1 -1 3.74 61476 8 2.81 -1 -1 41920 -1 -1 247 385 2 1 success v8.0.0-12648-g60575e9eb-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T23:48:05 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 103820 385 362 4415 4299 1 2357 997 26 26 676 io auto 56.8 MiB 5.49 60367 29168 553555 209559 320264 23732 97.1 MiB 4.21 0.04 12.484 9.22286 -10001.9 -9.22286 9.22286 0.61 0.0109639 0.0102538 1.47142 1.32279 -1 -1 -1 -1 96 41816 25 3.69863e+07 1.48038e+07 4.07810e+06 6032.69 88.96 8.68882 7.83852 93088 846470 -1 40322 20 9413 32446 1640117 290110 9.26797 9.26797 -10463.8 -9.26797 0 0 5.10087e+06 7545.67 0.27 1.53 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8.66 60367.5 29168 553555 209559 320264 23732 98.7 MiB 6.03 0.07 12.484 9.22286 -10001.9 -9.22286 9.22286 0.94 0.0141125 0.0131249 1.65631 1.52379 -1 -1 -1 -1 88 42524 36 3.69863e+07 1.48038e+07 3.77884e+06 5590.00 127.98 9.9274 9.16438 89712 781758 -1 40482 22 9863 33170 1682237 299912 9.28568 9.28568 -10491.8 -9.28568 0 0 4.73879e+06 7010.04 0.27 1.33 0.83 -1 -1 0.27 0.843489 0.796689 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 21.80 vpr 86.07 MiB -1 -1 3.85 46628 3 0.84 -1 -1 40816 -1 -1 127 236 1 6 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 88132 236 305 3199 3011 1 1523 675 19 19 361 io auto 47.1 MiB 3.34 25623.3 12744 275862 97068 164529 14265 86.1 MiB 2.04 0.03 6.4321 4.87079 -2820.2 -4.87079 4.87079 0.47 0.00697433 0.00639172 0.700934 0.638537 -1 -1 -1 -1 60 23886 41 1.72706e+07 9.76854e+06 1.37250e+06 3801.94 7.52 2.61476 2.39459 40123 275431 -1 20756 17 6182 15855 1441404 366482 4.86624 4.86624 -3060.91 -4.86624 0 0 1.72840e+06 4787.81 0.10 0.67 0.27 -1 -1 0.10 0.356305 0.336015 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 16.50 vpr 85.18 MiB -1 -1 2.56 48252 3 1.66 -1 -1 43844 -1 -1 139 38 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 87220 38 36 2739 2488 1 1049 213 16 16 256 clb auto 44.8 MiB 2.05 14714.1 9079 42758 11072 28707 2979 85.2 MiB 0.93 0.01 12.21 9.99171 -2582.5 -9.99171 9.99171 0.31 0.00523116 0.0045574 0.38791 0.340407 -1 -1 -1 -1 68 12752 21 1.21132e+07 7.49127e+06 1.06067e+06 4143.25 5.93 2.3104 2.03539 29104 207894 -1 11957 22 3549 8074 273879 48978 10.757 10.757 -2778.68 -10.757 0 0 1.31810e+06 5148.84 0.07 0.40 0.20 -1 -1 0.07 0.313159 0.287447 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.01 vpr 74.98 MiB -1 -1 3.03 36180 16 0.58 -1 -1 39024 -1 -1 61 45 3 1 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 76784 45 32 1192 1151 1 792 142 14 14 196 memory auto 36.2 MiB 2.79 10230.3 6724 27522 7495 16921 3106 75.0 MiB 0.56 0.01 13.9782 11.2901 -7209.19 -11.2901 11.2901 0.23 0.00308282 0.00272246 0.262656 0.231841 -1 -1 -1 -1 68 12586 25 9.20055e+06 5.32753e+06 806220. 4113.37 3.62 1.04218 0.926769 22432 157909 -1 10569 14 3362 8864 714686 176877 11.347 11.347 -7521.29 -11.347 0 0 1.00082e+06 5106.22 0.05 0.31 0.15 -1 -1 0.05 0.16189 0.151198 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 85.96 vpr 241.52 MiB -1 -1 10.45 104380 5 8.14 -1 -1 69996 -1 -1 726 169 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 247312 169 197 23225 21365 1 6045 1092 34 34 1156 clb auto 162.4 MiB 12.93 134820 39611 551950 185813 346752 19385 209.4 MiB 7.92 0.08 7.36437 3.436 -13913.4 -3.436 3.436 1.68 0.0273396 0.0236791 3.13748 2.65935 -1 -1 -1 -1 52 59147 24 6.50233e+07 3.91272e+07 4.04437e+06 3498.59 29.46 13.3155 11.319 127884 844416 -1 53415 13 14460 23081 882903 172595 3.68442 3.68442 -15235.2 -3.68442 0 0 5.32397e+06 4605.51 0.30 1.61 0.82 -1 -1 0.30 1.57315 1.44588 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 527.98 vpr 254.72 MiB -1 -1 9.18 126264 3 12.36 -1 -1 77880 -1 -1 761 115 0 40 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 260832 115 145 22864 19301 1 9598 1061 40 40 1600 mult_36 auto 159.1 MiB 12.95 226773 78397 558188 179956 354401 23831 230.5 MiB 10.52 0.12 7.82255 5.98209 -23106.9 -5.98209 5.98209 2.36 0.029098 0.0254441 3.28642 2.83123 -1 -1 -1 -1 74 132070 49 9.16046e+07 5.68542e+07 7.91020e+06 4943.87 460.93 20.6461 17.6144 199236 1626086 -1 114600 13 30840 46528 6757057 1570534 6.21022 6.21022 -25200.8 -6.21022 0 0 9.93055e+06 6206.59 0.58 3.10 1.72 -1 -1 0.58 1.65648 1.51587 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 387.77 vpr 929.32 MiB -1 -1 13.80 198344 3 7.16 -1 -1 156276 -1 -1 1693 149 0 179 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 951628 149 182 55415 37074 1 28410 2203 80 80 6400 mult_36 auto 320.0 MiB 34.46 1.07995e+06 280222 1979467 685049 1230466 63952 929.1 MiB 60.72 0.47 30.987 13.9125 -52518.9 -13.9125 13.9125 34.55 0.0766593 0.0680655 11.3948 9.9015 -1 -1 -1 -1 92 385377 47 3.90281e+08 1.62125e+08 3.95573e+07 6180.83 175.83 48.4665 41.9196 889084 8435008 -1 370124 18 100163 118854 13485087 2834274 14.8411 14.8411 -58035.6 -14.8411 0 0 5.02851e+07 7857.05 3.63 8.54 10.16 -1 -1 3.63 4.94611 4.44879 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.28 vpr 68.27 MiB -1 -1 0.69 26388 4 0.15 -1 -1 36680 -1 -1 15 11 0 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 69912 11 2 303 283 2 85 28 7 7 49 clb auto 28.8 MiB 0.20 405.309 283 1162 244 826 92 68.3 MiB 0.03 0.00 2.07098 2.0391 -154.896 -2.0391 1.90116 0.04 0.000579648 0.000516899 0.0213209 0.0192246 -1 -1 -1 -1 34 396 9 1.07788e+06 808410 84249.8 1719.38 0.22 0.139656 0.120596 3756 15224 -1 372 8 169 280 4584 1590 2.05367 1.94778 -165.542 -2.05367 0 0 103542. 2113.11 0.00 0.02 0.01 -1 -1 0.00 0.0224002 0.0209108 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt index ad3d51601b9..7fe09abaa7f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt @@ -1,15 +1,15 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratix10_arch.timing.xml gsm_switch_stratix10_arch_timing.blif common 3108.59 vpr 5.41 GiB 136 10294 0 0 2240 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 5671508 100 36 285842 271283 4 255265 12671 180 133 23940 M20K auto 2527.2 MiB 730.92 3011592 18469421 7247443 10757173 464805 4664.2 MiB 1331.31 10.77 5.27243 -601108 -4.27243 3.68089 0.13 1.5431 1.20541 210.174 164.161 3656898 14.3263 784921 3.07502 725776 1362456 1582612799 377371570 0 0 4.25346e+08 17767.2 14 7099044 74943382 -1 4.923 3.72425 -872030 -3.923 0 0 153.01 -1 -1 5237.5 MiB 609.00 270.869 216.374 4664.2 MiB -1 146.90 - stratix10_arch.timing.xml mes_noc_stratix10_arch_timing.blif common 7581.46 vpr 9.17 GiB 5 27504 0 64 736 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9610372 3 2 594103 567321 9 545215 28317 213 158 33654 LAB auto 4750.4 MiB 1792.09 5102295 50502585 19163643 29892479 1446463 7420.9 MiB 4616.34 38.19 8.47 -2.08793e+06 -7.47 7.51349 0.30 2.44374 1.92151 322.054 253.2 5377112 9.86954 1358583 2.49364 1549998 3909661 1368166802 196574136 0 0 6.00417e+08 17840.9 17 10062936 105944661 -1 8.401 7.074 -2.4865e+06 -7.401 0 0 256.84 -1 -1 8672.7 MiB 457.18 439.184 351.634 7420.9 MiB -1 194.78 - stratix10_arch.timing.xml dart_stratix10_arch_timing.blif common 2031.82 vpr 3.34 GiB 69 8237 0 0 530 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3499228 23 46 226521 213853 1 187960 8836 118 87 10266 LAB auto 1861.9 MiB 551.12 1813042 10235332 3948422 5950168 336742 2652.3 MiB 1087.71 9.53 9.74467 -1.10278e+06 -8.74467 9.74467 0.09 1.27187 0.957962 136.171 105.082 1927267 10.2538 463994 2.46862 539735 1287436 350240304 67144518 0 0 1.81869e+08 17715.7 17 3006772 31715945 -1 9.533 9.533 -1.26754e+06 -8.533 0 0 68.61 -1 -1 3230.2 MiB 162.19 188.558 148.13 2652.3 MiB -1 58.34 - stratix10_arch.timing.xml cholesky_bdti_stratix10_arch_timing.blif common 2712.59 vpr 4.37 GiB 162 11225 48 270 342 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 4586804 94 68 340057 306706 1 294310 12047 138 102 14076 LAB auto 2459.4 MiB 769.07 2213966 16714887 6770669 9330396 613822 3519.2 MiB 1472.96 9.23 4.276 -250765 -3.276 4.276 0.11 1.06954 0.905842 148.459 122.999 2149198 7.30260 496460 1.68688 718134 1201145 444490036 92294439 0 0 2.50467e+08 17793.9 17 4149580 43753024 -1 5.075 5.075 -495851 -4.075 0 0 84.80 -1 -1 4095.6 MiB 189.04 198.894 165.629 3519.2 MiB -1 71.05 - stratix10_arch.timing.xml minres_stratix10_arch_timing.blif common 2825.20 vpr 4.72 GiB 229 12835 0 156 581 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 4948536 129 100 369949 333068 2 310446 13802 146 108 15768 LAB auto 2697.2 MiB 943.53 1801913 18713381 6993205 11119963 600213 3796.1 MiB 1425.32 10.94 3.82271 -123649 -2.82271 3.02326 0.14 1.12759 0.871274 138.705 115.252 1668600 5.37493 452112 1.45635 729015 1280545 299925516 64013199 0 0 2.81209e+08 17834.2 12 4696032 49263790 -1 4.261 2.93816 -174031 -3.261 0 0 112.45 -1 -1 4321.8 MiB 132.49 182.213 152.795 3796.1 MiB -1 75.63 - stratix10_arch.timing.xml openCV_stratix10_arch_timing.blif common 2520.60 vpr 4.19 GiB 208 9225 0 594 933 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 4393324 106 102 302246 252591 1 228391 10960 138 102 14076 DSP auto 2219.0 MiB 610.27 1807295 14491832 5656370 8244054 591408 3342.3 MiB 1440.89 9.59 11.7662 -531654 -10.7662 11.7662 0.12 1.29494 1.07573 175.7 140.736 2210926 9.68116 558557 2.44580 615090 1267660 475621933 109949248 0 0 2.50467e+08 17793.9 14 4149580 43753024 -1 10.035 10.035 -760034 -9.035 0 0 89.20 -1 -1 4091.9 MiB 191.38 229.282 186.578 3342.3 MiB -1 65.76 - stratix10_arch.timing.xml bitonic_mesh_stratix10_arch_timing.blif common 3258.62 vpr 4.54 GiB 119 9630 0 507 1495 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 4760344 87 32 260931 228346 1 227559 11751 147 109 16023 M20K auto 2269.6 MiB 801.56 2336369 14967783 5666344 8757412 544027 3562.7 MiB 1818.46 13.11 9.0885 -925997 -8.0885 9.0885 0.14 1.77298 1.38415 182.161 147.849 3256919 14.3126 814862 3.58093 774784 2221694 822171733 192870107 0 0 2.85989e+08 17848.6 18 4788948 50134206 -1 8.735 8.735 -1.0894e+06 -7.735 0 0 104.47 -1 -1 4417.3 MiB 306.09 258.611 214.16 3562.7 MiB -1 92.78 - stratix10_arch.timing.xml segmentation_stratix10_arch_timing.blif common 2512.33 vpr 6.24 GiB 441 7353 0 21 194 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 6540916 72 369 179830 142047 1 137027 8009 247 183 45201 io_cell auto 1552.7 MiB 474.75 1125790 10260297 4060063 5767979 432255 6387.6 MiB 1218.19 9.51 1017.13 -331092 -1016.13 1017.13 0.26 0.90892 0.811756 108.545 88.2479 1322267 9.65976 369634 2.70034 497135 1510446 351593875 65715267 0 0 8.14208e+08 18013.1 25 13628436 143011261 -1 898.752 898.752 -431075 -897.752 0 0 294.59 -1 -1 6387.6 MiB 159.09 155.534 127.218 6387.6 MiB -1 260.31 - stratix10_arch.timing.xml des90_stratix10_arch_timing.blif common 1622.71 vpr 2.64 GiB 117 5579 0 264 772 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2767312 85 32 151105 128345 1 128276 6732 108 80 8640 M20K auto 1408.1 MiB 458.76 1174387 6678222 2328428 4069644 280150 2114.0 MiB 821.45 6.13 9.0401 -513720 -8.0401 9.0401 0.08 0.779906 0.636591 95.1564 76.1752 1663756 12.9704 429777 3.35049 426587 1181849 413692570 98891608 0 0 1.53228e+08 17734.7 15 2557548 26745974 -1 8.24 8.24 -587849 -7.24 0 0 61.61 -1 -1 2580.0 MiB 155.35 134.524 110.058 2114.0 MiB -1 44.75 - stratix10_arch.timing.xml neuron_stratix10_arch_timing.blif common 833.04 vpr 2.00 GiB 133 5234 0 243 108 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2093464 40 93 140673 125393 2 123625 5719 94 70 6580 LAB auto 1201.5 MiB 289.44 634340 6191360 2301274 3623602 266484 1729.3 MiB 370.55 2.45 5.84744 -64925.2 -4.84744 3.3402 0.04 0.387587 0.340417 48.3195 39.815 517953 4.19141 138793 1.12315 268394 383043 84540966 19817319 0 0 1.15552e+08 17561.0 18 1898072 20093317 -1 5.799 3.20378 -122888 -4.799 0 0 43.46 -1 -1 1880.4 MiB 41.18 67.4246 56.3964 1729.3 MiB -1 33.19 - stratix10_arch.timing.xml sparcT1_core_stratix10_arch_timing.blif common 1320.68 vpr 3.03 GiB 309 4982 0 6 154 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3176516 172 137 98039 97359 1 91845 5451 163 121 19723 io_cell auto 1048.7 MiB 416.44 1174053 5471979 2094519 3176216 201244 3102.1 MiB 483.40 4.56 7.15 -378395 -6.15 7.15 0.24 0.484867 0.374331 56.8899 45.3278 1526584 16.6220 347043 3.77874 324019 943132 297819952 53503048 0 0 3.51754e+08 17834.7 17 5914532 61913217 -1 6.938 6.938 -458652 -5.938 0 0 133.69 -1 -1 3102.1 MiB 111.14 80.1902 65.1665 3102.1 MiB -1 117.12 - stratix10_arch.timing.xml stereo_vision_stratix10_arch_timing.blif common 1336.40 vpr 7.73 GiB 506 5363 0 76 83 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 8102372 172 334 150507 118033 3 110735 6028 287 213 61131 io_cell auto 1114.7 MiB 159.83 546089 6696142 2566220 3885626 244296 7912.5 MiB 322.65 2.23 7.71363 -39076.7 -6.71363 7.71363 0.65 0.328993 0.270482 46.9904 37.5447 427507 3.86091 120235 1.08587 235293 320005 60687000 12277011 0 0 1.10789e+09 18123.3 15 18464012 193849399 -1 6.984 6.984 -51229.8 -5.984 0 0 404.36 -1 -1 7912.5 MiB 33.81 63.8841 51.9403 7912.5 MiB -1 343.62 - stratix10_arch.timing.xml cholesky_mc_stratix10_arch_timing.blif common 998.97 vpr 2.81 GiB 262 4835 115 131 382 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2944676 111 151 145547 131782 1 127404 5725 147 109 16023 io_cell auto 1301.4 MiB 282.50 801498 5790534 2145233 3342854 302447 2875.7 MiB 400.69 3.54 5.008 -92090.6 -4.008 4.559 0.09 0.537432 0.455738 62.8576 51.5026 805259 6.32071 212196 1.66559 300273 509257 150845866 34700709 0 0 2.85989e+08 17848.6 13 4788948 50134206 -1 4.488 4.083 -213947 -3.488 0 0 101.11 -1 -1 2875.7 MiB 61.86 84.7937 70.3971 2875.7 MiB -1 81.78 - stratix10_arch.timing.xml LU_Network_stratix10_arch_timing.blif common 8279.37 vpr 17.68 GiB 748 30526 826 224 1026 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 18535564 325 423 817452 760174 3 681111 33351 406 301 122206 io_cell auto 5546.8 MiB 1827.39 4732164 74080701 31510919 39435236 3134546 18101.1 MiB 4227.97 28.65 4.76071 -319191 -3.76071 4.69287 0.96 2.78373 2.33996 398.847 330.305 4439564 6.52395 1123896 1.65157 1562719 2598341 607571135 128284629 0 0 2.23450e+09 18284.7 12 36989044 388958102 -1 4.7 4.64063 -440709 -3.7 0 0 899.60 -1 -1 18101.1 MiB 247.43 493.191 412.334 18101.1 MiB -1 737.58 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratix10_arch.timing.xml gsm_switch_stratix10_arch_timing.blif common 2837.84 vpr 5.40 GiB 136 10106 0 0 2240 1 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 5666428 100 36 285842 271283 4 253628 12483 180 133 23940 M20K auto 2940.6 MiB 792.05 1.48869e+07 3002858 17815626 6974722 10394347 446557 4500.7 MiB 1098.26 9.04 13.25 5.22971 -611694 -4.22971 3.82252 0.18 1.411 1.13639 179.232 145.551 3612793 14.2449 785094 3.09555 725414 1361080 1471313038 359238811 0 0 4.25346e+08 17767.2 13 7099044 74943382 -1 4.957 3.94886 -921051 -3.957 0 0 151.60 -1 -1 5232.2 MiB 545.29 236.401 196.46 4500.7 MiB -1 122.16 + stratix10_arch.timing.xml mes_noc_stratix10_arch_timing.blif common 7183.98 vpr 9.20 GiB 5 27849 0 64 736 8 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 9649604 3 2 594103 567321 9 543997 28662 214 159 34026 LAB auto 5408.6 MiB 1867.76 5.78207e+07 4919275 50886078 19210215 30226837 1449026 7237.3 MiB 4254.33 38.35 28.084 7.72633 -2.20558e+06 -6.72633 7.42597 0.27 2.23027 1.79482 285.868 232.35 5238720 9.63707 1354352 2.49145 1584310 4029497 1345116138 190951116 0 0 6.07100e+08 17842.2 17 10165140 107089206 -1 7.629 7.09655 -2.54173e+06 -6.629 0 0 221.57 -1 -1 8708.7 MiB 414.38 396.727 328.688 7237.3 MiB -1 190.93 + stratix10_arch.timing.xml dart_stratix10_arch_timing.blif common 1856.97 vpr 3.33 GiB 69 8172 0 0 530 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 3492156 23 46 226521 213853 1 187500 8771 117 87 10179 LAB auto 2092.0 MiB 569.18 1.0133e+07 1742833 9954311 3806737 5822362 325212 2534.3 MiB 936.41 7.55 21.369 9.60965 -1.0793e+06 -8.60965 9.60965 0.09 0.93812 0.732794 110.229 87.1894 1857020 9.90427 449733 2.39861 534880 1267235 332038397 63591537 0 0 1.80389e+08 17721.7 19 2986164 31462164 -1 9.513 9.513 -1.22549e+06 -8.513 0 0 61.40 -1 -1 3232.0 MiB 139.08 157.681 128.064 2534.3 MiB -1 47.54 + stratix10_arch.timing.xml cholesky_bdti_stratix10_arch_timing.blif common 2533.63 vpr 4.41 GiB 162 11233 48 270 342 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4628564 94 68 340057 306706 1 294160 12055 138 102 14076 LAB auto 2760.4 MiB 841.55 1.3019e+07 2202223 16315171 6532418 9145410 637343 3390.3 MiB 1241.16 9.03 9.569 4.276 -258107 -3.276 4.276 0.10 1.00907 0.885995 124.102 104.882 2133192 7.25191 493315 1.67705 717560 1212473 413805021 87230144 0 0 2.50467e+08 17793.9 15 4149580 43753024 -1 4.8 4.8 -507877 -3.8 0 0 87.14 -1 -1 4119.0 MiB 155.80 166.032 142.245 3390.3 MiB -1 68.28 + stratix10_arch.timing.xml minres_stratix10_arch_timing.blif common 2551.18 vpr 4.78 GiB 229 13107 0 156 581 1 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 5009080 129 100 369949 333068 2 310359 14074 148 110 16280 LAB auto 2974.7 MiB 894.41 1.56036e+07 1776417 19036714 7010623 11333034 693057 3745.3 MiB 1213.93 9.24 11.573 3.86896 -124924 -2.86896 3.04149 0.18 0.978701 0.819698 113.938 96.2578 1633788 5.26427 461872 1.48821 717594 1252357 277084813 59048296 0 0 2.90438e+08 17840.2 13 4859396 50919384 -1 6.367 3.88374 -185193 -5.367 0 0 101.02 -1 -1 4363.5 MiB 110.62 152.03 130.666 3745.3 MiB -1 80.53 + stratix10_arch.timing.xml openCV_stratix10_arch_timing.blif common 2274.35 vpr 4.20 GiB 208 9076 0 594 946 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4407976 106 102 302246 252591 1 227203 10824 138 102 14076 DSP auto 2536.6 MiB 614.06 1.41948e+07 1818571 14252625 5486221 8203289 563115 3256.0 MiB 1200.52 9.25 21.801 11.6746 -538527 -10.6746 11.6746 0.10 1.13129 0.960759 141.463 117.137 2233307 9.83030 560651 2.46781 619157 1271400 489235054 112384082 0 0 2.50467e+08 17793.9 13 4149580 43753024 -1 9.989 9.989 -767072 -8.989 0 0 87.30 -1 -1 4105.7 MiB 174.14 188.779 159.245 3256.0 MiB -1 69.67 + stratix10_arch.timing.xml bitonic_mesh_stratix10_arch_timing.blif common 3172.11 vpr 4.54 GiB 119 9793 0 507 1495 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4757640 87 32 260931 228346 1 228000 11914 147 109 16023 M20K auto 2604.2 MiB 955.22 1.87806e+07 2283082 15109246 5704540 8885960 518746 3461.2 MiB 1611.09 12.63 24.443 8.95292 -925922 -7.95292 8.95292 0.12 1.25615 1.02923 150.277 124.188 3238886 14.2058 811136 3.55766 789590 2286186 844200495 196688636 0 0 2.85989e+08 17848.6 17 4788948 50134206 -1 8.743 8.743 -1.06669e+06 -7.743 0 0 97.71 -1 -1 4414.8 MiB 288.30 218.233 184.552 3461.2 MiB -1 77.90 + stratix10_arch.timing.xml segmentation_stratix10_arch_timing.blif common 2452.03 vpr 6.05 GiB 441 7400 0 21 194 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6347536 72 369 179830 142047 1 137086 8056 247 183 45201 io_cell auto 1709.7 MiB 559.78 1.04574e+07 1163400 10582769 4237945 5961934 382890 6198.8 MiB 1104.72 9.21 1908.52 1011.59 -333443 -1010.59 1011.59 0.35 0.673369 0.55634 89.1842 74.4528 1334455 9.74460 367632 2.68456 599680 1951165 458451044 83590964 0 0 8.14208e+08 18013.1 21 13628436 143011261 -1 894.129 894.129 -437510 -893.129 0 0 290.62 -1 -1 6198.8 MiB 166.98 124.587 105.028 6198.8 MiB -1 227.46 + stratix10_arch.timing.xml des90_stratix10_arch_timing.blif common 1515.73 vpr 2.65 GiB 117 5592 0 264 772 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2781356 85 32 151105 128345 1 128569 6745 108 80 8640 M20K auto 1595.7 MiB 486.54 7.97681e+06 1172705 6567948 2222645 4062514 282789 2068.8 MiB 701.53 5.89 19.362 8.34132 -511204 -7.34132 8.34132 0.06 0.711063 0.57236 79.2583 65.0022 1671490 13.0010 430888 3.35149 435664 1212120 424171224 101000958 0 0 1.53228e+08 17734.7 15 2557548 26745974 -1 8.116 8.116 -570415 -7.116 0 0 54.61 -1 -1 2594.2 MiB 141.26 112.445 94.6108 2068.8 MiB -1 40.78 + stratix10_arch.timing.xml neuron_stratix10_arch_timing.blif common 822.63 vpr 2.06 GiB 133 5204 0 243 108 1 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2157252 40 93 140673 125393 2 123564 5689 94 70 6580 LAB auto 1306.2 MiB 328.22 3.00397e+06 630082 6148133 2246392 3632455 269286 1748.5 MiB 323.29 2.70 8.666 5.453 -64094.3 -4.453 3.44467 0.05 0.321074 0.277449 42.229 35.0887 511131 4.13824 136654 1.10638 272477 388844 87045307 20495122 0 0 1.15552e+08 17561.0 19 1898072 20093317 -1 5.556 3.32763 -105332 -4.556 0 0 43.24 -1 -1 1935.3 MiB 39.38 59.9663 50.8187 1748.5 MiB -1 26.01 + stratix10_arch.timing.xml sparcT1_core_stratix10_arch_timing.blif common 1197.58 vpr 2.94 GiB 309 4932 0 6 154 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 3078356 172 137 98039 97359 1 91819 5401 163 121 19723 io_cell auto 1156.6 MiB 410.18 6.25155e+06 1141305 5357872 2009817 3147849 200206 3006.2 MiB 417.01 3.73 16.064 7.437 -372487 -6.437 7.437 0.15 0.381452 0.322809 47.0942 38.6676 1463207 15.9365 335987 3.65939 320348 922531 290642647 52565549 0 0 3.51754e+08 17834.7 17 5914532 61913217 -1 7.206 7.206 -456400 -6.206 0 0 124.44 -1 -1 3006.2 MiB 99.82 67.3672 56.4514 3006.2 MiB -1 91.94 + stratix10_arch.timing.xml stereo_vision_stratix10_arch_timing.blif common 1265.40 vpr 7.47 GiB 506 5395 0 76 83 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7829476 172 334 150507 118033 3 110749 6060 287 213 61131 io_cell auto 1208.2 MiB 163.94 4.44837e+06 549735 6798735 2557823 3985160 255752 7646.0 MiB 289.82 2.36 21.771 7.71908 -39688.1 -6.71908 7.71908 0.66 0.286519 0.250027 40.1789 33.2375 431877 3.89988 121261 1.09500 234811 318613 59885286 12118899 0 0 1.10789e+09 18123.3 12 18464012 193849399 -1 6.997 6.997 -51674.8 -5.997 0 0 403.57 -1 -1 7646.0 MiB 27.13 52.042 43.8127 7646.0 MiB -1 307.55 + stratix10_arch.timing.xml cholesky_mc_stratix10_arch_timing.blif common 975.19 vpr 2.72 GiB 262 4840 115 131 382 0 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2852732 111 151 145547 131782 1 127161 5730 147 109 16023 io_cell auto 1442.9 MiB 329.45 4.75138e+06 827719 5694702 2059108 3338155 297439 2785.9 MiB 345.43 2.90 9.155 4.759 -92839.5 -3.759 4.557 0.12 0.465695 0.385641 54.1741 45.1607 835041 6.56701 217458 1.71015 302067 515845 154807116 35686831 0 0 2.85989e+08 17848.6 12 4788948 50134206 -1 4.341 4.341 -227847 -3.341 0 0 99.93 -1 -1 2785.9 MiB 55.80 72.0583 61.3104 2785.9 MiB -1 71.69 + stratix10_arch.timing.xml LU_Network_stratix10_arch_timing.blif common 7994.44 vpr 17.09 GiB 748 30396 826 224 1026 1 success 7998658-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-06-01T01:30:40 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 17921244 325 423 817452 760174 3 678465 33221 406 301 122206 io_cell auto 6316.2 MiB 1947.41 5.97514e+07 4730164 72628389 30574521 39029004 3024864 17501.2 MiB 3973.63 24.19 21.629 4.54496 -313434 -3.54496 4.43706 0.95 2.2884 1.88313 345.899 288.095 4455436 6.57279 1129915 1.66688 1561057 2600138 605651950 127768453 0 0 2.23450e+09 18284.7 12 36989044 388958102 -1 4.85 4.72591 -430750 -3.85 0 0 816.78 -1 -1 17501.2 MiB 222.49 435.82 369.017 17501.2 MiB -1 710.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt index e381a9de6fe..2733f9b2a28 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml 521.09 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2999364 42 35 119888 86875 1 51488 3609 129 96 12384 -1 neuron 1754.5 MiB 201.53 588950 3296458 1251917 1696829 347712 2929.1 MiB 120.52 0.99 7.81281 -83697.4 -6.81281 5.17837 0.07 0.394336 0.331354 48.5767 41.2186 -1 -1 -1 -1 -1 774816 15 0 0 2.28639e+08 18462.4 38.71 65.6047 56.4158 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml 448.82 vpr 2.85 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2992528 42 35 119888 86875 1 50882 3437 129 96 12384 -1 neuron 1746.7 MiB 106.69 578743 3192458 1206112 1829273 157073 2922.4 MiB 136.43 1.09 8.30532 -83283.1 -7.30532 5.88288 0.07 0.398109 0.334174 50.9205 42.9915 -1 -1 -1 -1 -1 751914 17 0 0 2.28639e+08 18462.4 38.69 68.6074 58.8539 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml 453.84 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2994616 42 35 119888 86875 1 50816 3438 129 96 12384 -1 neuron 1748.6 MiB 106.43 587491 3064004 1147605 1894430 21969 2924.4 MiB 135.58 1.08 7.95276 -79743.8 -6.95276 5.25276 0.07 0.397692 0.334466 49.3461 41.6555 -1 -1 -1 -1 -1 765801 15 0 0 2.28639e+08 18462.4 38.72 65.6267 56.2745 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml 737.02 vpr 2.83 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-12661-g327cee3d6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-13T19:21:08 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 2965812 42 35 119888 86875 1 51646 3595 129 96 12384 -1 neuron 1857.4 MiB 502.15 1.21569e+06 621456 3306955 1240097 1657055 409803 2896.3 MiB 98.34 0.82 8.7996 7.66945 -86149.9 -6.66945 5.25748 0.07 0.279323 0.245519 36.6534 30.8848 -1 -1 -1 -1 -1 808659 16 0 0 2.28639e+08 18462.4 33.21 49.8673 42.8255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml 310.71 vpr 2.82 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-12661-g327cee3d6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-13T19:21:08 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 2961588 42 35 119888 86875 1 50882 3437 129 96 12384 -1 neuron 1852.8 MiB 84.57 1.99271e+06 576222 3140604 1178993 1822059 139552 2892.2 MiB 94.33 0.73 12.1805 8.27534 -82556.8 -7.27534 5.60504 0.07 0.269525 0.236256 36.2376 30.2155 -1 -1 -1 -1 -1 753077 16 0 0 2.28639e+08 18462.4 30.32 49.257 41.9348 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml 317.70 vpr 2.83 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-12661-g327cee3d6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-13T19:21:08 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 2964216 42 35 119888 86875 1 50816 3438 129 96 12384 -1 neuron 1854.8 MiB 83.40 2.11213e+06 571508 3038067 1110809 1910937 16321 2894.7 MiB 96.95 0.76 10.8298 8.23402 -80998.6 -7.23402 5.59616 0.16 0.287833 0.236889 35.8374 29.6476 -1 -1 -1 -1 -1 749232 16 0 0 2.28639e+08 18462.4 30.30 48.8531 41.3864 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt index cb40c2de73c..a1a02980315 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt @@ -1,5 +1,6 @@ regression_tests/vtr_reg_nightly_test7/ap_titan regression_tests/vtr_reg_nightly_test7/titan_other_run_flat +regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_run_flat #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat #regression_tests/vtr_reg_nightly_test7/verify_router_lookahead_run_flat diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/config.txt new file mode 100644 index 00000000000..8d63b3eccc6 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/config.txt @@ -0,0 +1,58 @@ +############################################## +# Configuration file for running experiments +############################################## +# +# These are only the Titanium benchmarks which +# could be run in under around 2 hours. +# +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/titan_new/stratix10 + +# Path to directory of SDCs to use +sdc_dir=benchmarks/titan_blif/titan_new/stratix10 + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +circuit_list_add=ASU_LRN_stratix10_arch_timing.blif +# circuit_list_add=ChainNN_LRN_LG_stratix10_arch_timing.blif +# circuit_list_add=ChainNN_ELT_LG_stratix10_arch_timing.blif +# circuit_list_add=ChainNN_BSC_LG_stratix10_arch_timing.blif +circuit_list_add=ASU_ELT_stratix10_arch_timing.blif +circuit_list_add=ASU_BSC_stratix10_arch_timing.blif +circuit_list_add=tdfir_stratix10_arch_timing.blif +# circuit_list_add=pricing_stratix10_arch_timing.blif +circuit_list_add=mem_tester_stratix10_arch_timing.blif +circuit_list_add=mandelbrot_stratix10_arch_timing.blif +circuit_list_add=channelizer_stratix10_arch_timing.blif +circuit_list_add=fft1d_offchip_stratix10_arch_timing.blif +circuit_list_add=DLA_LRN_stratix10_arch_timing.blif +# circuit_list_add=matrix_mult_stratix10_arch_timing.blif +circuit_list_add=fft1d_stratix10_arch_timing.blif +circuit_list_add=fft2d_stratix10_arch_timing.blif +circuit_list_add=DLA_ELT_stratix10_arch_timing.blif +circuit_list_add=DLA_BSC_stratix10_arch_timing.blif +circuit_list_add=jpeg_deco_stratix10_arch_timing.blif +circuit_list_add=nyuzi_stratix10_arch_timing.blif +circuit_list_add=sobel_stratix10_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=stratix10_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan_s10.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan_s10.txt + +# The Titanium benchmarks are run at a fixed channel width of 400 to simulate a +# Stratix 10-like routing architecture. A large number of routing iterations is +# set to ensure the router doesn't give up too easily on the larger benchmarks. +script_params=-starting_stage vpr --route_chan_width 400 --max_router_iterations 400 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/golden_results.txt new file mode 100644 index 00000000000..ba4e2b6719a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/golden_results.txt @@ -0,0 +1,17 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratix10_arch.timing.xml ASU_LRN_stratix10_arch_timing.blif common 7993.64 vpr 13.25 GiB 229 40741 0 3036 372 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 13894356 227 2 1167270 950971 1 940838 44378 297 220 65340 DSP auto 7101.8 MiB 1047.02 7.75188e+07 9443240 106060553 43642478 59781149 2636926 11841.2 MiB 4957.00 27.91 15.352 5.686 -607673 -4.686 5.686 0.62 2.55789 2.0423 375.164 304.491 9213086 9.79513 1905771 2.02617 2126891 2998375 3494723494 1194079683 0 0 1.18403e+09 18121.0 19 19646892 206908249 -1 8.842 8.842 -1.04321e+06 -7.842 0 0 255.31 -1 -1 12398.4 MiB 1244.03 486.79 397.826 11841.2 MiB -1 261.79 + stratix10_arch.timing.xml ASU_ELT_stratix10_arch_timing.blif common 7398.88 vpr 11.51 GiB 229 33322 0 3036 344 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 12069748 227 2 922529 767696 1 776573 36931 297 220 65340 DSP auto 5855.8 MiB 954.08 6.15386e+07 8814389 83637899 34693645 46699966 2244288 11008.9 MiB 3620.96 21.17 16.314 4.9273 -486042 -3.9273 4.9273 0.54 2.17917 1.75385 311.916 254.434 8993972 11.5855 1780574 2.29363 1847958 2786821 4866103904 1910105294 0 0 1.18403e+09 18121.0 73 19646892 206908249 -1 9.172 9.172 -908907 -8.172 0 0 266.45 -1 -1 11008.9 MiB 2089.34 572.942 469.674 11008.9 MiB -1 277.58 + stratix10_arch.timing.xml ASU_BSC_stratix10_arch_timing.blif common 5392.51 vpr 11.17 GiB 229 31727 0 3036 344 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 11707808 227 2 882550 735137 1 734220 35336 297 220 65340 DSP auto 5631.8 MiB 827.57 5.68724e+07 7205050 80016410 32487238 45198029 2331143 10856.1 MiB 3485.54 30.26 16.289 4.6973 -446712 -3.6973 4.6973 0.61 2.11647 1.70775 310.174 252.473 7005422 9.54469 1427841 1.94539 1631505 2384173 1142140496 270312649 0 0 1.18403e+09 18121.0 18 19646892 206908249 -1 6.995 6.995 -757171 -5.995 0 0 263.78 -1 -1 10856.1 MiB 346.80 395.842 324.645 10856.1 MiB -1 283.77 + stratix10_arch.timing.xml tdfir_stratix10_arch_timing.blif common 5990.83 vpr 10.87 GiB 363 26622 3 512 56 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 11402484 87 276 773787 697889 1 643160 27556 209 155 32395 LAB auto 6893.8 MiB 1567.48 4.71135e+07 5459236 52445572 20326521 30477509 1641542 8663.3 MiB 3558.47 30.72 15.389 5.693 -716058 -4.693 5.693 0.18 1.78901 1.56024 261.892 214.722 5035293 7.86222 1162973 1.81589 1581627 2748464 1523969734 394631171 0 0 5.78001e+08 17842.3 14 9725652 102117791 -1 6.17 6.17 -1.12816e+06 -5.17 0 0 126.14 -1 -1 9596.5 MiB 429.12 325.283 269.71 8663.3 MiB -1 124.15 + stratix10_arch.timing.xml mem_tester_stratix10_arch_timing.blif common 3951.89 vpr 8.47 GiB 36 24820 0 0 1601 1 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 8878712 6 30 677620 619953 3 566016 26458 201 149 29949 LAB auto 5172.1 MiB 1128.17 3.55192e+07 2571998 44555464 16629960 26785757 1139747 6531.4 MiB 2302.13 18.81 12.134 4.444 -217833 -3.444 3.25024 0.16 1.97387 1.59659 242.823 197.278 1897093 3.35170 554517 0.979695 1250362 2191310 365800058 70196172 0 0 5.28462e+08 17645.4 11 8655172 93012966 -1 5.509 3.52567 -225904 -4.509 0 0 117.35 -1 -1 7904.0 MiB 125.82 305.184 251.594 6531.4 MiB -1 126.41 + stratix10_arch.timing.xml mandelbrot_stratix10_arch_timing.blif common 5182.60 vpr 10.49 GiB 399 21779 1591 250 141 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 10995216 122 277 649416 572241 2 532791 24160 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-1 5.503 5.503 -663822 -4.503 0 0 872.89 -1 -1 25635.2 MiB 126.51 235.416 194.353 25635.2 MiB -1 905.60 + stratix10_arch.timing.xml DLA_LRN_stratix10_arch_timing.blif common 2795.51 vpr 5.85 GiB 27 17602 0 448 824 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 6137904 2 25 524128 410471 1 394698 18901 171 127 21717 LAB auto 3467.2 MiB 415.51 2.19971e+07 2968477 32985706 12707237 19176825 1101644 4709.9 MiB 2006.17 13.64 15.06 5.842 -229657 -4.842 5.842 0.12 1.24962 1.04122 170.013 139.548 2878684 7.29523 665432 1.68635 908791 1472601 402036186 87057888 0 0 3.86548e+08 17799.3 14 6476260 68074081 -1 6.136 6.136 -377431 -5.136 0 0 81.99 -1 -1 5553.4 MiB 120.07 215.081 179.125 4709.9 MiB -1 75.65 + stratix10_arch.timing.xml fft1d_stratix10_arch_timing.blif common 3000.56 vpr 9.16 GiB 506 14148 196 120 367 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 9604884 165 341 428556 387960 2 349972 15337 287 213 61131 io_cell auto 3973.3 MiB 658.57 2.17639e+07 2258388 24775917 10083243 13734109 958565 9379.8 MiB 1618.92 22.30 20.557 5.782 -382681 -4.782 3.33708 0.35 1.13747 0.930452 163.442 132.202 2008783 5.74665 522867 1.49580 798484 1318486 318017072 63478487 0 0 1.10789e+09 18123.3 18 18464012 193849399 -1 5.514 3.58667 -563700 -4.514 0 0 242.36 -1 -1 9379.8 MiB 112.84 213.951 176.244 9379.8 MiB -1 251.26 + stratix10_arch.timing.xml fft2d_stratix10_arch_timing.blif common 2990.44 vpr 12.48 GiB 649 12727 163 96 714 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 13084452 243 406 393762 353562 2 325827 14349 355 263 93365 io_cell auto 3708.2 MiB 592.96 2.1839e+07 2292499 22497114 8853327 12800936 842851 12777.8 MiB 1370.54 15.06 23.152 5.782 -399793 -4.782 3.80957 0.53 1.10104 0.881526 148.329 120.144 2203185 6.76922 545124 1.67488 765778 1272606 380197869 75017131 0 0 1.70054e+09 18213.9 19 28125092 296332318 -1 5.646 3.97603 -574917 -4.646 0 0 377.44 -1 -1 12777.8 MiB 124.14 197.9 163.333 12777.8 MiB -1 404.94 + stratix10_arch.timing.xml DLA_ELT_stratix10_arch_timing.blif common 1644.66 vpr 4.34 GiB 27 12456 0 352 816 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 4547960 2 25 369016 293218 1 284141 13651 144 107 15408 LAB auto 2606.9 MiB 246.38 1.27535e+07 1864601 21376345 8580285 12067753 728307 3469.2 MiB 1131.93 7.29 12.964 5.676 -167434 -4.676 5.676 0.10 0.885128 0.734846 117.012 95.7493 1820848 6.41051 459112 1.61636 641959 1005963 290494005 65115980 0 0 2.74710e+08 17829.1 12 4580360 48098128 -1 5.762 5.762 -289987 -4.762 0 0 57.38 -1 -1 4147.7 MiB 81.01 145.875 120.806 3469.2 MiB -1 57.36 + stratix10_arch.timing.xml DLA_BSC_stratix10_arch_timing.blif common 1621.00 vpr 4.25 GiB 27 12091 0 352 816 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 4451752 2 25 356374 282496 1 275111 13286 143 106 15158 LAB auto 2547.2 MiB 230.92 1.25052e+07 1838704 20932324 8415755 11816027 700542 3402.2 MiB 1124.99 7.42 12.804 5.804 -171307 -4.804 5.804 0.08 0.85743 0.702285 116.522 95.5647 1826183 6.64045 463435 1.68516 626983 1003622 299725869 67176351 0 0 2.70680e+08 17857.3 14 4532104 47408547 -1 5.745 5.745 -303631 -4.745 0 0 55.94 -1 -1 4060.5 MiB 85.06 147.333 122.721 3402.2 MiB -1 56.16 + stratix10_arch.timing.xml jpeg_deco_stratix10_arch_timing.blif common 2182.69 vpr 13.93 GiB 710 8544 150 145 686 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 14601892 345 365 226660 204625 2 186994 10235 393 291 114363 io_cell auto 2375.5 MiB 356.50 1.32512e+07 1488867 14561060 5874212 8015424 671424 14259.7 MiB 704.52 5.02 23.995 7.32166 -365311 -6.32166 4.01799 0.65 0.796079 0.624182 108.081 85.1893 1567369 8.38246 381991 2.04293 449632 817049 272044665 58929057 0 0 2.08858e+09 18262.7 16 34532852 363579310 -1 6.671 4.26909 -505960 -5.671 0 0 478.72 -1 -1 14259.7 MiB 83.21 139.74 112.544 14259.7 MiB -1 466.96 + stratix10_arch.timing.xml nyuzi_stratix10_arch_timing.blif common 685.30 vpr 1.85 GiB 183 4473 0 96 243 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 1944604 38 145 99230 90964 1 87362 4995 101 75 7575 io_cell auto 1143.9 MiB 231.39 4.06174e+06 1061156 4699795 1702672 2853705 143418 1632.9 MiB 242.30 2.00 17.5319 9.228 -200643 -8.228 9.228 0.04 0.361714 0.284342 41.6908 33.0916 1390256 15.9146 316957 3.62830 315302 921297 447922834 92282134 0 0 1.31575e+08 17369.7 42 2069452 22717519 -1 9.199 9.199 -281959 -8.199 0 0 26.58 -1 -1 1798.9 MiB 128.26 71.5558 58.4994 1632.9 MiB -1 26.62 + stratix10_arch.timing.xml sobel_stratix10_arch_timing.blif common 324.52 vpr 3.61 GiB 362 821 0 0 53 0 success v8.0.0-12873-g98c8a0f56-dirty release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-06-02T22:10:12 betzgrp-wintermute /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor 3783208 86 276 23287 21920 1 19466 1236 201 149 29949 io_cell auto 520.2 MiB 31.31 521611 118274 710646 225250 423742 61654 3694.5 MiB 16.59 0.16 7.462 5.693 -32927.6 -4.693 5.693 0.16 0.0540046 0.0421128 6.20075 4.8796 115014 5.90967 29138 1.49717 43733 69656 19767127 4346882 0 0 5.28462e+08 17645.4 10 8655172 93012966 -1 4.791 4.791 -40474.6 -3.791 0 0 115.28 -1 -1 3694.5 MiB 5.70 8.25093 6.71974 3694.5 MiB -1 138.90 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/config.txt new file mode 100755 index 00000000000..2ecd91cf0e2 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/config.txt @@ -0,0 +1,28 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing/fixed_size + +# Add circuits to list to sweep +circuit_list_add=single_wire.v + +# Add architectures to list to sweep +arch_list_add=fixed_k6_frac_N8_22nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap.txt + +# Script parameters +script_params_common=-track_memory_usage --analytical_place --route --ap_generate_mass_report on + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/golden_results.txt new file mode 100644 index 00000000000..1ce7736a277 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_k6_frac_N8_22nm.xml single_wire.v common 1.34 vpr 76.20 MiB -1 -1 0.07 20448 1 0.02 -1 -1 33176 -1 -1 0 1 0 0 success v8.0.0-12842-ge95d71165b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-29T18:09:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78028 1 1 1 0 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 3 0 76.2 MiB 0.46 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.38 9.051e-06 5.955e-06 6.3309e-05 4.4576e-05 76.2 MiB 0.46 76.2 MiB 0.07 8 4 1 6.79088e+06 0 166176. 575.005 0.14 0.000829136 0.000770258 20206 45088 -1 4 1 1 1 21 11 0.2714 nan -0.2714 -0.2714 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.000785867 0.000731474 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt index 52747da9fdc..009b55cd6b8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt @@ -1,6 +1,6 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 10.90 vpr 81.36 MiB -1 -1 8.14 44968 3 0.57 -1 -1 35340 -1 -1 49 196 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83308 196 193 800 0 1 601 439 20 20 400 -1 vtr_extra_small -1 -1 4328 3107 92124 17877 63452 10795 81.4 MiB 1.38 0.00 2.56454 2.37946 -1137.82 -2.37946 2.37946 0.04 0.00170951 0.00159049 0.108014 0.100137 81.4 MiB 1.38 81.4 MiB 0.66 5067 8.55912 1503 2.53885 1660 2444 142383 40675 2.07112e+07 3.18881e+06 1.26946e+06 3173.65 10 38988 203232 -1 2.76727 2.76727 -1220.28 -2.76727 0 0 0.11 -1 -1 81.4 MiB 0.08 0.17114 0.160292 81.4 MiB -1 0.04 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.23 vpr 75.47 MiB -1 -1 0.22 18468 3 0.06 -1 -1 33128 -1 -1 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77280 99 130 264 0 1 226 298 20 20 400 -1 vtr_extra_small -1 -1 998 719 42088 12988 22077 7023 75.5 MiB 0.51 0.00 2.00298 1.89487 -117.095 -1.89487 1.89487 0.04 0.000568785 0.000532954 0.0270668 0.0254536 75.5 MiB 0.51 75.5 MiB 0.25 1273 7.62275 391 2.34132 403 645 32624 10084 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 11 39388 210115 -1 2.02782 2.02782 -132.929 -2.02782 0 0 0.12 -1 -1 75.5 MiB 0.03 0.0466214 0.0438046 75.5 MiB -1 0.04 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 18.99 vpr 130.75 MiB -1 -1 2.93 61476 8 2.72 -1 -1 42296 -1 -1 244 385 2 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 133892 385 362 3324 0 1 2373 994 30 30 900 -1 vtr_small -1 -1 44934 30685 486878 158175 303508 25195 130.8 MiB 10.73 0.04 10.9569 9.14069 -10026.4 -9.14069 9.14069 0.19 0.0075565 0.00697625 0.821563 0.749283 130.8 MiB 10.73 130.8 MiB 5.59 41636 17.6573 10780 4.57167 10078 33334 1771649 321112 4.8774e+07 1.46421e+07 6.56785e+06 7297.61 16 120772 1084977 -1 9.28426 9.28426 -10368.8 -9.28426 0 0 0.73 -1 -1 130.8 MiB 0.67 1.2751 1.17633 130.8 MiB -1 0.19 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.78 vpr 84.59 MiB -1 -1 1.71 32292 16 0.37 -1 -1 34988 -1 -1 59 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86620 45 32 936 0 1 764 140 20 20 400 -1 vtr_extra_small -1 -1 7967 6824 18290 3791 13097 1402 84.6 MiB 2.77 0.00 11.7422 10.6015 -6978.52 -10.6015 10.6015 0.06 0.00172166 0.00152276 0.108719 0.0971486 84.6 MiB 2.77 84.6 MiB 1.78 11182 14.6938 2948 3.87385 3523 9991 831731 205110 2.07112e+07 5.21975e+06 1.91495e+06 4787.38 14 44576 305072 -1 11.0577 11.0577 -7502.5 -11.0577 0 0 0.18 -1 -1 84.6 MiB 0.20 0.207414 0.189307 84.6 MiB -1 0.06 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.46 vpr 74.58 MiB -1 -1 0.41 22932 4 0.10 -1 -1 32968 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76368 11 2 140 0 2 81 28 20 20 400 -1 vtr_extra_small -1 -1 344 282 1246 289 767 190 74.6 MiB 0.35 0.00 2.1429 2.10685 -161.57 -2.10685 1.95087 0.04 0.000382895 0.000341958 0.0148948 0.0134952 74.6 MiB 0.35 74.6 MiB 0.22 481 6.41333 125 1.66667 162 273 5235 1511 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.13367 2.00787 -169.877 -2.13367 0 0 0.10 -1 -1 74.6 MiB 0.02 0.031341 0.0286656 74.6 MiB -1 0.04 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 13.60 vpr 84.67 MiB -1 -1 10.28 48164 3 0.64 -1 -1 38724 -1 -1 78 196 1 0 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 86700 196 193 800 0 1 617 468 20 20 400 -1 vtr_extra_small -1 -1 4551.79 3335 67660 11256 49424 6980 84.7 MiB 1.85 0.01 2.99794 2.65144 -1220.33 -2.65144 2.65144 0.00 0.00196764 0.0016933 0.0869812 0.0762881 84.7 MiB 1.85 84.7 MiB 0.87 5403 8.88651 1576 2.59211 1637 2428 148736 41047 2.07112e+07 4.75173e+06 1.26946e+06 3173.65 11 38988 203232 -1 3.14851 3.14851 -1307.1 -3.14851 0 0 0.18 -1 -1 84.7 MiB 0.10 0.253777 0.227178 41.3 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.41 vpr 77.76 MiB -1 -1 0.24 22136 3 0.07 -1 -1 37184 -1 -1 68 99 1 0 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 79628 99 130 264 0 1 225 298 20 20 400 -1 vtr_extra_small -1 -1 927.937 681 36118 11514 18619 5985 77.8 MiB 0.67 0.00 1.85007 1.85007 -115.211 -1.85007 1.85007 0.00 0.000603813 0.000534685 0.0258211 0.0231026 77.8 MiB 0.67 77.8 MiB 0.30 1223 7.36747 392 2.36145 437 680 27699 8352 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 11 39388 210115 -1 1.99059 1.99059 -134.028 -1.99059 0 0 0.19 -1 -1 77.8 MiB 0.03 0.0763687 0.0688854 39.8 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 26.75 vpr 136.18 MiB -1 -1 3.62 64888 8 3.02 -1 -1 45000 -1 -1 252 385 2 1 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 139452 385 362 3324 0 1 2371 1002 30 30 900 -1 vtr_small -1 -1 44098.1 30988 507214 164336 316622 26256 136.2 MiB 16.82 0.07 10.8167 8.97166 -10306.7 -8.97166 8.97166 0.00 0.00951912 0.00820906 1.03378 0.89695 136.2 MiB 16.82 136.2 MiB 8.33 42405 17.9987 11044 4.68761 10195 33783 1818500 332274 4.8774e+07 1.50733e+07 6.56785e+06 7297.61 19 120772 1084977 -1 9.28418 9.28418 -10617.2 -9.28418 0 0 1.20 -1 -1 136.2 MiB 0.91 2.0873 1.855 84.5 MiB -1 0.28 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 8.07 vpr 88.27 MiB -1 -1 2.71 35320 16 0.41 -1 -1 39076 -1 -1 61 45 3 1 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 90392 45 32 936 0 1 770 142 20 20 400 -1 vtr_extra_small -1 -1 7959.32 6854 9392 1467 7682 243 88.3 MiB 3.91 0.01 11.8592 10.7084 -6927.96 -10.7084 10.7084 0.00 0.00233249 0.00190785 0.0816673 0.0690512 88.3 MiB 3.91 88.3 MiB 2.55 11323 14.7627 3001 3.91265 3570 9616 762496 186695 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 15 44576 305072 -1 10.9684 10.9684 -7241.74 -10.9684 -0.00135869 -0.00135869 0.30 -1 -1 88.3 MiB 0.26 0.375846 0.327629 45.4 MiB -1 0.08 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.56 vpr 77.10 MiB -1 -1 0.48 26488 4 0.11 -1 -1 36728 -1 -1 15 11 0 0 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78948 11 2 140 0 2 85 28 20 20 400 -1 vtr_extra_small -1 -1 350.949 307 112 20 82 10 77.1 MiB 0.46 0.00 2.12187 2.12187 -168.584 -2.12187 1.99515 0.00 0.000442789 0.000363289 0.00459294 0.00425398 77.1 MiB 0.46 77.1 MiB 0.28 477 6.03797 123 1.55696 149 222 4271 1232 2.07112e+07 808410 1.12964e+06 2824.09 8 37792 180905 -1 2.20473 2.04223 -168.73 -2.20473 0 0 0.16 -1 -1 77.1 MiB 0.02 0.0430278 0.0379188 38.7 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt index 493089933c3..ebed140f180 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 10.47 vpr 81.20 MiB -1 -1 8.11 45204 3 0.57 -1 -1 35608 -1 -1 50 196 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83148 196 193 800 389 1 589 440 20 20 400 -1 vtr_extra_small -1 -1 3998 3782 18832 248 3091 15493 81.2 MiB 0.98 0.00 2.85588 2.47185 -1156.3 -2.47185 2.47185 0.04 0.00172364 0.00159607 0.0308341 0.0290834 81.2 MiB 0.98 81.2 MiB 0.63 5632 9.71035 1634 2.81724 1596 2379 162444 45554 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.84177 2.84177 -1268.87 -2.84177 0 0 0.12 -1 -1 81.2 MiB 0.09 0.105167 0.0996991 81.2 MiB -1 0.04 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.08 vpr 75.51 MiB -1 -1 0.22 18464 3 0.06 -1 -1 33404 -1 -1 69 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77320 99 130 240 229 1 222 299 20 20 400 -1 vtr_extra_small -1 -1 1001 943 16283 1928 655 13700 75.5 MiB 0.37 0.00 1.95754 1.93615 -151.243 -1.93615 1.93615 0.04 0.000568044 0.000533906 0.0123779 0.0117131 75.5 MiB 0.37 75.5 MiB 0.24 1463 8.97546 433 2.65644 390 644 29549 8534 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 9 39388 210115 -1 1.99132 1.99132 -165.748 -1.99132 0 0 0.12 -1 -1 75.5 MiB 0.02 0.0304031 0.0286853 75.5 MiB -1 0.04 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.50 vpr 84.02 MiB -1 -1 1.72 32292 16 0.36 -1 -1 35064 -1 -1 59 45 3 1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86032 45 32 936 77 1 764 140 20 20 400 -1 vtr_extra_small -1 -1 8308 6790 6311 196 3112 3003 84.0 MiB 2.52 0.00 11.697 10.6608 -7088.74 -10.6608 10.6608 0.06 0.00172403 0.00151742 0.0484196 0.0441323 84.0 MiB 2.52 84.0 MiB 1.83 11366 14.9356 2988 3.92641 3444 9377 809880 202958 2.07112e+07 5.21975e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.968 10.968 -7522.1 -10.968 0 0 0.18 -1 -1 84.0 MiB 0.19 0.146169 0.135428 84.0 MiB -1 0.06 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.39 vpr 74.81 MiB -1 -1 0.41 22692 4 0.10 -1 -1 32956 -1 -1 15 11 0 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76604 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 441 361 112 19 45 48 74.8 MiB 0.32 0.00 2.32519 2.16196 -166.836 -2.16196 1.97742 0.04 0.000403733 0.000348452 0.00435748 0.00414137 74.8 MiB 0.32 74.8 MiB 0.21 486 6.65753 142 1.94521 190 278 5599 1612 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.17143 1.9491 -169.271 -2.17143 0 0 0.10 -1 -1 74.8 MiB 0.02 0.0211176 0.0196106 74.8 MiB -1 0.04 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 12.11 vpr 84.60 MiB -1 -1 9.28 47908 3 0.67 -1 -1 38848 -1 -1 65 196 1 0 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 86628 196 193 800 389 1 595 455 20 20 400 -1 vtr_extra_small -1 -1 3930.2 3851 12698 233 1913 10552 84.6 MiB 1.31 0.01 2.92748 2.45851 -1170.35 -2.45851 2.45851 0.00 0.00195338 0.00166919 0.0256246 0.0231297 84.6 MiB 1.31 84.6 MiB 0.82 5848 9.97952 1699 2.89932 1614 2292 168336 47738 2.07112e+07 4.05111e+06 1.26946e+06 3173.65 14 38988 203232 -1 2.66317 2.66317 -1272.51 -2.66317 0 0 0.18 -1 -1 84.6 MiB 0.11 0.184198 0.166128 41.1 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.16 vpr 78.19 MiB -1 -1 0.24 22264 3 0.07 -1 -1 36924 -1 -1 80 99 1 0 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 80064 99 130 240 229 1 230 310 20 20 400 -1 vtr_extra_small -1 -1 1065.12 1030 2406 180 458 1768 78.2 MiB 0.43 0.00 2.28653 2.24089 -151.437 -2.24089 2.24089 0.00 0.000591732 0.00052278 0.00444976 0.00414593 78.2 MiB 0.43 78.2 MiB 0.27 1532 8.95906 448 2.61988 371 564 28131 8290 2.07112e+07 4.85952e+06 1.31074e+06 3276.84 9 39388 210115 -1 2.23774 2.23774 -171.733 -2.23774 0 0 0.18 -1 -1 78.2 MiB 0.03 0.0453311 0.0412991 40.1 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 7.27 vpr 87.91 MiB -1 -1 2.01 35244 16 0.41 -1 -1 39072 -1 -1 60 45 3 1 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 90020 45 32 936 77 1 775 141 20 20 400 -1 vtr_extra_small -1 -1 8451.7 6853 8559 318 4227 4014 87.9 MiB 3.76 0.01 11.2162 10.0363 -6703 -10.0363 10.0363 0.00 0.00220009 0.00179429 0.0731371 0.061547 87.9 MiB 3.76 87.9 MiB 2.70 11655 15.0971 3036 3.93264 3708 10025 802337 195270 2.07112e+07 5.27364e+06 1.91495e+06 4787.38 19 44576 305072 -1 10.6367 10.6367 -7204.03 -10.6367 0 0 0.29 -1 -1 87.9 MiB 0.28 0.361571 0.313441 45.3 MiB -1 0.08 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.50 vpr 77.10 MiB -1 -1 0.48 26364 4 0.11 -1 -1 36492 -1 -1 15 11 0 0 success v8.0.0-12807-gb9a610e4ea release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-26T12:39:19 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78952 11 2 140 13 2 85 28 20 20 400 -1 vtr_extra_small -1 -1 402.146 340 112 14 55 43 77.1 MiB 0.39 0.00 2.39119 2.10685 -164.254 -2.10685 1.95087 0.00 0.000495979 0.000402703 0.00462625 0.00427073 77.1 MiB 0.39 77.1 MiB 0.24 499 6.31646 140 1.77215 239 387 8032 2278 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.13588 1.93308 -168.701 -2.13588 0 0 0.16 -1 -1 77.1 MiB 0.02 0.0413979 0.0364008 38.9 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index 6639b016754..b30895bbc1e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml eblif_write.eblif common 0.26 vpr 57.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58440 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.7 MiB 0.00 16 14 18 7 10 1 57.1 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3418e-05 8.319e-06 9.1048e-05 6.8306e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.0012188 0.00113608 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000858214 0.00082141 +arch.xml eblif_write.eblif common 0.26 vpr 57.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58440 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.7 MiB 0.00 16 14 18 7 10 1 57.1 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3418e-05 8.319e-06 9.1048e-05 6.8306e-05 -1 -1 -1 -1 2 8 1 59253.6 29626.8 -1 -1 0.00 0.0012188 0.00113608 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000858214 0.00082141 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt index 6e72a741485..46e014cf1e6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt @@ -28,6 +28,6 @@ script_params_common=-starting_stage vpr -sdc_file tasks/regression_tests/vtr_re script_params_list_add = script_params_list_add = --route_chan_width 30 -check_incremental_sta_consistency script_params_list_add = --router_algorithm parallel --num_workers 4 -# script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -# script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 -# script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 4 --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 +script_params_list_add = --enable_parallel_connection_router on --multi_queue_num_threads 2 --multi_queue_num_queues 8 --multi_queue_direct_draining on --astar_fac 0.0 --post_target_prune_fac 0.0 --post_target_prune_offset 0.0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 86cec1613d1..eaeb5d795f6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -2,3 +2,6 @@ k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--route_chan_width_30_-check_incremental_sta_consistency 1.3344 0.595 0.781297 -1 -1 0.57 0.757256 -1 1.3344 -1 1.16524 -1 1.77873 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.6593 -1 -1 0.268 3.18526 -1 1.18303 -1 3.40324 -1 -1.46764 -1 -1 -1 -1 k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_4_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--enable_parallel_connection_router_on_--multi_queue_num_threads_2_--multi_queue_num_queues_8_--multi_queue_direct_draining_on_--astar_fac_0.0_--post_target_prune_fac_0.0_--post_target_prune_offset_0.0 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index 05b6fd95464..4c5761ad73e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml ndff.blif common 0.27 vpr 57.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58548 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 36 31 59 13 43 3 57.2 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8658e-05 1.4445e-05 0.000175579 0.000141999 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00231473 0.00196653 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00104772 0.000979247 +arch.xml ndff.blif common 0.27 vpr 57.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58548 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 36 31 59 13 43 3 57.2 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8658e-05 1.4445e-05 0.000175579 0.000141999 -1 -1 -1 -1 4 28 27 59253.6 44440.2 -1 -1 0.01 0.00231473 0.00196653 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00104772 0.000979247 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt index fbf3358dd11..44cfb179384 100755 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt @@ -15,7 +15,7 @@ circuit_list_add=s298.blif # Add architectures to list to sweep arch_list_add=k4_N4_tileable_90nm.xml - + # Parse info and how to parse parse_file=vpr_standard.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt index 2f44136a1bd..443673c35c5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt @@ -6,4 +6,4 @@ non_column.xml raygentop.v common 47.75 odin 1.93 GiB 34.32 2023384 -1 -1 3 0.8 non_column_tall_aspect_ratio.xml raygentop.v common 51.79 odin 1.93 GiB 39.18 2023256 -1 -1 3 0.83 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 102100 214 305 2963 2869 1 1441 650 23 46 1058 io auto 48.3 MiB 2.18 34433 12310 253910 86017 138818 29075 97.8 MiB 0.90 0.01 6.20818 4.74318 -2736.15 -4.74318 4.74318 0.80 0.0037281 0.0034064 0.359725 0.330304 -1 -1 -1 -1 52 22487 30 5.05849e+07 9.79696e+06 3.17293e+06 2998.99 3.53 1.28793 1.18725 97261 632982 -1 20510 16 5114 12053 1254371 346946 4.98587 4.98587 -2932.2 -4.98587 0 0 4.15960e+06 3931.57 0.12 0.33 0.42 -1 -1 0.12 0.187592 0.178023 non_column_wide_aspect_ratio.xml raygentop.v common 50.76 odin 1.93 GiB 38.21 2023656 -1 -1 3 0.84 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 98352 214 305 2963 2869 1 1441 650 43 22 946 io auto 48.4 MiB 2.19 32195 14077 256724 83624 150449 22651 94.9 MiB 0.92 0.01 6.20333 4.54267 -2819.04 -4.54267 4.54267 0.70 0.00362855 0.00334198 0.36694 0.336882 -1 -1 -1 -1 42 27740 26 4.55909e+07 9.79696e+06 2.29725e+06 2428.38 3.62 1.2805 1.17964 79978 445530 -1 23661 21 6769 17034 1969793 532017 5.2623 5.2623 -3159.48 -5.2623 0 0 2.89121e+06 3056.25 0.09 0.47 0.28 -1 -1 0.09 0.224224 0.210925 custom_sbloc.xml raygentop.v common 20.32 odin 1.51 GiB 10.16 1588048 -1 -1 3 0.82 -1 -1 39876 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88684 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.17 24028 12399 225770 74858 132033 18879 86.6 MiB 0.84 0.01 5.49355 4.39465 -2699.44 -4.39465 4.39465 0.21 0.00358021 0.0033004 0.322189 0.295867 -1 -1 -1 -1 60 25212 46 1.65001e+07 9.79696e+06 1.11685e+06 3093.75 3.18 1.03862 0.957059 34801 214773 -1 20923 16 6158 14594 1766703 471535 4.72432 4.72432 -3000.62 -4.72432 0 0 1.41014e+06 3906.19 0.03 0.37 0.13 -1 -1 0.03 0.187347 0.177768 -multiple_io_types.xml raygentop.v common 83.03 odin 1.54 GiB 10.26 1617740 -1 -1 3 0.83 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 484432 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 47.0 MiB 2.58 60956 25475 99140 5163 24781 69196 473.1 MiB 0.42 0.01 9.23589 4.60777 -3590.83 -4.60777 4.60777 11.18 0.00363304 0.00335274 0.163246 0.151042 -1 -1 -1 -1 38 47769 50 2.48753e+08 9.79696e+06 9.69761e+06 2160.30 49.39 1.31777 1.21279 366081 1845534 -1 38574 21 9565 21545 4981287 1328871 5.11017 5.11017 -4030.7 -5.11017 0 0 1.23326e+07 2747.29 0.44 0.96 1.12 -1 -1 0.44 0.226022 0.212296 +multiple_io_types.xml raygentop.v common 83.03 odin 1.54 GiB 10.26 1617740 -1 -1 3 0.83 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 484432 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 47.0 MiB 2.58 60956 25475 99140 5163 24781 69196 473.1 MiB 0.42 0.01 9.23589 4.60777 -3590.83 -4.60777 4.60777 11.18 0.00363304 0.00335274 0.163246 0.151042 -1 -1 -1 -1 42 47769 50 2.48753e+08 9.79696e+06 9.69761e+06 2160.30 49.39 1.31777 1.21279 366081 1845534 -1 38574 21 9565 21545 4981287 1328871 5.11017 5.11017 -4030.7 -5.11017 0 0 1.23326e+07 2747.29 0.44 0.96 1.12 -1 -1 0.44 0.226022 0.212296 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt index 4ac9645c21c..5e4f3c2ccb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml eblif_write.eblif common 0.26 vpr 56.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58312 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 16 14 18 7 10 1 56.9 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3321e-05 8.124e-06 8.7295e-05 6.3966e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00108886 0.00100644 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000892955 0.000854475 +arch.xml eblif_write.eblif common 0.26 vpr 56.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58312 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.3 MiB 0.00 16 14 18 7 10 1 56.9 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3321e-05 8.124e-06 8.7295e-05 6.3966e-05 -1 -1 -1 -1 2 8 1 59253.6 29626.8 -1 -1 0.00 0.00108886 0.00100644 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000892955 0.000854475 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 4ad63c55fd1..aacc8ec80ab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.21 odin 100.12 MiB 2.22 102528 -1 -1 3 0.20 -1 -1 34100 -1 52224 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68248 99 130 363 493 1 251 298 12 12 144 clb auto 27.9 MiB 0.07 2086 873 75918 23929 39390 12599 66.6 MiB 0.13 0.00 2.81842 2.17528 -220.25 -2.17528 2.17528 0.09 0.00057296 0.000536541 0.045254 0.042348 -1 -1 -1 -1 32 1783 21 5.66058e+06 4.21279e+06 281316. 1953.58 0.21 0.115911 0.106856 11950 52952 -1 1569 8 475 592 37949 12971 2.62567 2.62567 -236.989 -2.62567 0 0 345702. 2400.71 0.01 0.02 0.03 -1 -1 0.01 0.0148651 0.0139996 0.008359 0.1947 0.06177 0.7435 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.21 odin 100.12 MiB 2.22 102528 -1 -1 3 0.20 -1 -1 34100 -1 52224 68 99 1 0 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68248 99 130 363 493 1 251 298 12 12 144 clb auto 27.9 MiB 0.07 2086 873 75918 23929 39390 12599 66.6 MiB 0.13 0.00 2.81842 2.17528 -220.25 -2.17528 2.17528 0.09 0.00057296 0.000536541 0.045254 0.042348 -1 -1 -1 -1 32 1783 21 5.66058e+06 4.21279e+06 281316. 1953.58 0.21 0.115911 0.106856 11950 52952 -1 1569 8 475 592 37949 12971 2.62567 2.62567 -236.989 -2.62567 0 0 345702. 2400.71 0.01 0.02 0.03 -1 -1 0.01 0.0148651 0.0139996 0.008359 0.1947 0.06794 0.7435 k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.33 odin 87.38 MiB 2.02 89472 -1 -1 15 0.28 -1 -1 34648 -1 54320 39 162 0 5 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72896 162 96 999 932 1 692 302 16 16 256 mult_36 auto 31.6 MiB 0.22 9298 5609 93406 28941 57235 7230 71.2 MiB 0.37 0.01 25.0935 21.2697 -1792.21 -21.2697 21.2697 0.17 0.00167786 0.00157594 0.166256 0.156124 -1 -1 -1 -1 42 13435 49 1.21132e+07 4.08187e+06 666210. 2602.38 1.63 0.455209 0.425126 24208 131534 -1 10212 18 3382 6827 1034510 307036 22.5724 22.5724 -1934.15 -22.5724 0 0 835850. 3265.04 0.02 0.20 0.07 -1 -1 0.02 0.0801778 0.0759457 0.00765 0.3347 0.01582 0.6495 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt index 5dba66ce28c..6f86526d21b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml ndff.blif common 0.28 vpr 57.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58932 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.8 MiB 0.00 36 31 59 13 43 3 57.6 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8904e-05 1.4655e-05 0.00017596 0.000143236 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00219197 0.00184136 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00106544 0.00100507 +arch.xml ndff.blif common 0.28 vpr 57.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12648-g259ceba57-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-06T12:34:13 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58932 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.8 MiB 0.00 36 31 59 13 43 3 57.6 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8904e-05 1.4655e-05 0.00017596 0.000143236 -1 -1 -1 -1 4 28 27 59253.6 44440.2 -1 -1 0.01 0.00219197 0.00184136 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00106544 0.00100507

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<101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Fri, 29 Nov 2024 10:42:57 +0800 Subject: [PATCH 417/453] Create vib_test_arch.xml --- vtr_flow/arch/VIB/vib_test_arch.xml | 26861 ++++++++++++++++++++++++++ 1 file changed, 26861 insertions(+) create mode 100644 vtr_flow/arch/VIB/vib_test_arch.xml diff --git a/vtr_flow/arch/VIB/vib_test_arch.xml b/vtr_flow/arch/VIB/vib_test_arch.xml new file mode 100644 index 00000000000..48c5040b732 --- /dev/null +++ b/vtr_flow/arch/VIB/vib_test_arch.xml @@ -0,0 +1,26861 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_left_pi[6:0].a2f_o io_left_pi.lclk io_left_pi.lreset io_left_pi.clk io_left_pi.reset io_left_pi.sc_in io_left_pi.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_left_po[13:0].f2a_i io_left_po.lclk io_left_po.lreset io_left_po.clk io_left_po.reset io_left_po.sc_in io_left_po.sc_out + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_right_pi[5:0].a2f_o io_right_pi.lclk io_right_pi.lreset io_right_pi.clk io_right_pi.reset io_right_pi.sc_in io_right_pi.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_right_po[5:0].f2a_i io_right_po.lclk io_right_po.lreset io_right_po.clk io_right_po.reset io_right_po.sc_in io_right_po.sc_out + + + + + + + + + + + + + + + + + + + + + + + + + io_top_pi[23:0].a2f_o io_top_pi.lclk io_top_pi.lreset io_top_pi.clk io_top_pi.reset io_top_pi.sc_in io_top_pi.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_top_po[6:0].f2a_i io_top_po.lclk io_top_po.lreset io_top_po.clk io_top_po.reset io_top_po.sc_in io_top_po.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_bottom_pi[3:0].a2f_o io_bottom_pi.lclk io_bottom_pi.lreset io_bottom_pi.clk io_bottom_pi.reset io_bottom_pi.sc_in io_bottom_pi.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_bottom_po[7:0].f2a_i io_bottom_po.lclk io_bottom_po.lreset io_bottom_po.clk io_bottom_po.reset io_bottom_po.sc_in io_bottom_po.sc_out + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset + clb.cin + clb.I0[4:0] clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.I5[4:0] clb.O[11:0] clb.I6[4:0] clb.I7[4:0] clb.I8[4:0] clb.I9[4:0] clb.I10[4:0] clb.I11[4:0] clb.O[23:12] + clb.cout + + + + + + + + + + + + + + + + + + + + + + + + + + io_top_dsp_pi[23:0].a2f_o io_top_dsp_pi.clk io_top_dsp_pi.reset io_top_dsp_pi.lclk io_top_dsp_pi.lreset io_top_dsp_pi.sc_in io_top_dsp_pi.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_top_dsp_po[6:0].f2a_i io_top_dsp_po.clk io_top_dsp_po.reset io_top_dsp_po.lclk io_top_dsp_po.lreset io_top_dsp_po.sc_in io_top_dsp_po.sc_out + + + + + + + + + + + + + + + + + + + + + + + + + + io_top_ram_pi[23:0].a2f_o io_top_ram_pi.clk io_top_ram_pi.reset io_top_ram_pi.lclk io_top_ram_pi.lreset io_top_ram_pi.sc_in io_top_ram_pi.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_top_ram_po[6:0].f2a_i io_top_ram_po.clk io_top_ram_po.reset io_top_ram_po.lclk io_top_ram_po.lreset io_top_ram_po.sc_in io_top_ram_po.sc_out + + + + + + + + + + + + + + + + + + + + + + + io_bottom_dsp_pi[3:0].a2f_o io_bottom_dsp_pi.clk io_bottom_dsp_pi.reset io_bottom_dsp_pi.lclk io_bottom_dsp_pi.lreset io_bottom_dsp_pi.sc_in io_bottom_dsp_pi.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_bottom_dsp_po[7:0].f2a_i io_bottom_dsp_po.clk io_bottom_dsp_po.reset io_bottom_dsp_po.lclk io_bottom_dsp_po.lreset io_bottom_dsp_po.sc_in io_bottom_dsp_po.sc_out + + + + + + + + + + + + + + + + + + + + + + + + + + io_bottom_ram_pi[3:0].a2f_o io_bottom_ram_pi.clk io_bottom_ram_pi.reset io_bottom_ram_pi.lclk io_bottom_ram_pi.lreset io_bottom_ram_pi.sc_in io_bottom_ram_pi.sc_out + + + + + + + + + + + + + + + + + + + + + + + + io_bottom_ram_po[7:0].f2a_i io_bottom_ram_po.clk io_bottom_ram_po.reset io_bottom_ram_po.lclk io_bottom_ram_po.lreset io_bottom_ram_po.sc_in io_bottom_ram_po.sc_out + + + + + + + + + + + + + + + + + + + + + + + + dsp.clk dsp.reset + dsp.a[0:11] dsp.b[0:9] dsp.q_o[0:11] dsp.lclk dsp.lreset + dsp.a[24:35] dsp.b[20:29] dsp.q_o[12:23] + dsp.a[36:47] dsp.b[30:39] dsp.q_o[24:35] + dsp.a[12:23] dsp.b[10:19] dsp.q_o[36:43] + + + + + + + + + + + + + + + + + + + + + + + + + + ram9k.clk ram9k.mem_index + ram9k.raddr_i[0:2] ram9k.waddr_i[0:2] ram9k.data_i[0:8] ram9k.bwen_ni[0:8] ram9k.q_o[0:11] ram9k.lclk ram9k.lreset + ram9k.raddr_i[3:5] ram9k.waddr_i[3:5] ram9k.data_i[18:26] ram9k.bwen_ni[18:26] ram9k.q_o[12:23] + ram9k.raddr_i[6:8] ram9k.waddr_i[6:8] ram9k.data_i[27:35] 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l1.W5 l3.W8 l8.W15 + + + l1.N6 l1.N7 l3.N11 io_leftL.a2f_o[2] + + + l1.N8 l2.N1 l4.N7 io_leftL.a2f_o[1] + + + l1.N9 l3.N14 l8.N7 io_leftL.a2f_o[3] + + + l1.N10 l3.N17 l8.N15 + + + io_leftL.a2f_o[3] + + + io_leftL.a2f_o[2] + + + io_leftL.a2f_o[4] + + + l1.S3 l1.S4 l3.S5 io_leftL.a2f_o[4] + + + l1.S5 l2.S5 l4.S15 io_leftL.a2f_o[3] + + + l1.S6 l3.S8 l8.S7 io_leftL.a2f_o[5] + + + l1.S7 l3.S11 l8.S15 + + + l1.W8 l1.W9 l3.W14 io_leftL.a2f_o[5] + + + l1.W10 l2.W1 l4.W3 io_leftL.a2f_o[4] + + + l1.W11 l3.W17 l8.W7 io_leftL.a2f_o[6] + + + l1.W12 l3.W20 l8.W15 + + + l1.N0 l1.N1 l3.N23 io_leftL.a2f_o[6] + + + l1.N2 l2.N3 l4.N7 io_leftL.a2f_o[5] + + + l1.N3 l3.N2 l8.N7 io_leftL.a2f_o[0] + + + l1.N4 l3.N5 l8.N15 + + + io_leftL.a2f_o[0] + + + io_leftL.a2f_o[6] + + + io_leftL.a2f_o[1] + + + l1.S10 l1.S11 l3.S17 io_leftL.a2f_o[1] + + + l1.S12 l2.S1 l4.S15 io_leftL.a2f_o[0] + + + l1.S0 l3.S20 l8.S7 io_leftL.a2f_o[2] + + + l1.S1 l3.S23 l8.S15 + + + l1.W2 l1.W3 l3.W2 io_leftL.a2f_o[1] + + + l1.W4 l2.W3 l4.W3 io_leftL.a2f_o[0] + + + l1.W5 l3.W5 l8.W7 io_leftL.a2f_o[2] + + + l1.W6 l3.W8 l8.W15 + + + l1.N7 l1.N8 l3.N11 io_leftL.a2f_o[2] + + + l1.N9 l2.N5 l4.N7 io_leftL.a2f_o[1] + + + l1.N10 l3.N14 l8.N7 io_leftL.a2f_o[3] + + + l1.N11 l3.N17 l8.N15 + + + io_leftL.a2f_o[3] + + + io_leftL.a2f_o[2] + + + io_leftL.a2f_o[4] + + + l1.S4 l1.S5 l3.S5 io_leftL.a2f_o[4] + + + l1.S6 l2.S3 l4.S15 io_leftL.a2f_o[3] + + + l1.S7 l3.S8 l8.S7 io_leftL.a2f_o[5] + + + l1.S8 l3.S11 l8.S15 + + + l1.W9 l1.W10 l3.W14 io_leftL.a2f_o[5] + + + l1.W11 l2.W5 l4.W3 io_leftL.a2f_o[4] + + + l1.W12 l3.W17 l8.W7 io_leftL.a2f_o[6] + + + l1.W0 l3.W20 l8.W15 + + + l1.N1 l1.N2 l3.N23 io_leftL.a2f_o[6] + + + l1.N3 l2.N1 l4.N7 io_leftL.a2f_o[5] + + + l1.N4 l3.N2 l8.N7 io_leftL.a2f_o[0] + + + l1.N5 l3.N5 l8.N15 + + + io_leftL.a2f_o[0] + + + io_leftL.a2f_o[6] + + + io_leftL.a2f_o[1] + + + l1.S11 l1.S12 l3.S17 io_leftL.a2f_o[1] + + + l1.S0 l2.S5 l4.S15 io_leftL.a2f_o[0] + + + l1.S1 l3.S20 l8.S7 io_leftL.a2f_o[2] + + + l1.S2 l3.S23 l8.S15 + + + l1.W3 l1.W4 l3.W2 io_leftL.a2f_o[1] + + + l1.W5 l2.W1 l4.W3 io_leftL.a2f_o[0] + + + l1.W6 l3.W5 l8.W7 io_leftL.a2f_o[2] + + + l1.W7 l3.W8 l8.W15 + + + l1.N8 l1.N9 l3.N11 io_leftL.a2f_o[2] + + + l1.N10 l2.N3 l4.N7 io_leftL.a2f_o[1] + + + l1.N11 l3.N14 l8.N7 io_leftL.a2f_o[3] + + + l1.N12 l3.N17 l8.N15 + + + io_leftL.a2f_o[3] + + + io_leftL.a2f_o[2] + + + io_leftL.a2f_o[4] + + + l1.S5 l1.S6 l3.S5 io_leftL.a2f_o[4] + + + l1.S7 l2.S1 l4.S15 io_leftL.a2f_o[3] + + + l1.S8 l3.S8 l8.S7 io_leftL.a2f_o[5] + + + l1.S9 l3.S11 l8.S15 + + + l1.W10 l1.W11 l3.W14 io_leftL.a2f_o[5] + + + l1.W12 l2.W3 l4.W3 io_leftL.a2f_o[4] + + + l1.W0 l3.W17 l8.W7 io_leftL.a2f_o[6] + + + l1.W1 l3.W20 l8.W15 + + + l1.N2 l1.N3 l3.N23 io_leftL.a2f_o[6] + + + l1.N4 l2.N5 l4.N7 io_leftL.a2f_o[5] + + + l1.N5 l3.N2 l8.N7 io_leftL.a2f_o[0] + + + l1.N6 l3.N5 l8.N15 + + + io_leftL.a2f_o[0] + + + io_leftL.a2f_o[6] + + + io_leftL.a2f_o[1] + + + l1.S12 l1.S0 l3.S17 io_leftL.a2f_o[1] + + + l1.S1 l2.S3 l4.S15 io_leftL.a2f_o[0] + + + l1.S2 l3.S20 l8.S7 io_leftL.a2f_o[2] + + + l1.S3 l3.S23 l8.S15 + + + l1.W6 l1.W5 l2.W3 l3.W11 l4.W7 io_leftL.a2f_o[0] OG_0 + + + l1.N5 io_leftL.a2f_o[1] + + + l1.S11 l1.N4 l3.S17 io_leftL.a2f_o[2] + + + l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 io_leftL.a2f_o[1] + + + l1.S10 l3.S14 io_leftL.a2f_o[2] + + + l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 io_leftL.a2f_o[3] OG_2 l1.N2 + + + l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 io_leftL.a2f_o[2] OG_2 l1.S4 + + + l1.S2 io_leftL.a2f_o[3] OG_3 l1.N9 + + + l1.W8 l1.W1 io_leftL.a2f_o[4] OG_4 + + + l1.W8 l1.S1 l2.W3 l3.W11 l4.W3 io_leftL.a2f_o[3] + + + l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 io_leftL.a2f_o[4] + + + l1.S0 l1.S6 l3.S20 io_leftL.a2f_o[5] + + + l1.W0 l1.N6 l3.W17 l3.N2 l4.W3 io_leftL.a2f_o[4] + + + l1.N12 l3.N17 io_leftL.a2f_o[5] OG_6 + + + l1.S5 l3.S23 io_leftL.a2f_o[6] OG_6 l1.S4 + + + l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 io_leftL.a2f_o[5] OG_7 l1.N0 + + + l1.W11 l1.W10 l2.W5 l3.W11 l4.W15 io_leftL.a2f_o[6] OG_0 + + + l1.W4 l1.N10 l2.W1 l3.W23 l4.W7 io_leftL.a2f_o[0] + + + l1.N3 l1.N9 l3.N17 io_leftL.a2f_o[6] + + + l1.N9 l1.S2 l3.N8 io_leftL.a2f_o[0] + + + l1.N2 l3.N14 io_leftL.a2f_o[1] + + + l1.S8 l3.S5 io_leftL.a2f_o[0] OG_2 + + + l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 io_leftL.a2f_o[1] OG_2 l1.N10 + + + l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 io_leftL.a2f_o[2] OG_3 l1.W12 + + + l1.W0 l1.W6 io_leftL.a2f_o[0] OG_4 + + + l1.S6 io_leftL.a2f_o[1] + + + l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 io_leftL.a2f_o[2] + + + l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 io_leftL.a2f_o[1] + + + l1.W5 l1.S11 l3.W17 l3.S2 l4.W11 io_leftL.a2f_o[2] + + + l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 io_leftL.a2f_o[3] OG_6 l1.W6 + + + l1.N10 l3.N23 io_leftL.a2f_o[2] OG_6 l1.S8 + + + l1.N3 io_leftL.a2f_o[3] OG_7 + + + l1.W3 l1.W2 l2.W1 l3.W11 l4.W7 io_leftL.a2f_o[4] OG_0 + + + l1.N2 io_leftL.a2f_o[3] + + + l1.S8 l1.N1 l3.S17 io_leftL.a2f_o[4] + + + l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 io_leftL.a2f_o[5] + + + l1.S7 l3.S14 io_leftL.a2f_o[4] + + + l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 io_leftL.a2f_o[5] OG_2 l1.S6 + + + l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 io_leftL.a2f_o[6] OG_2 + + + l1.S12 io_leftL.a2f_o[5] OG_3 l1.W11 + + + l1.W5 l1.W11 io_leftL.a2f_o[6] OG_4 + + + l1.W5 l1.S11 l2.W1 l3.W11 l4.W3 io_leftL.a2f_o[0] + + + l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 io_leftL.a2f_o[6] + + + l1.S10 l1.S3 l3.S20 io_leftL.a2f_o[0] + + + l1.W10 l1.N3 l3.W17 l3.N2 l4.W3 io_leftL.a2f_o[1] + + + l1.N9 l3.N17 io_leftL.a2f_o[0] OG_6 + + + l1.S2 l3.S23 io_leftL.a2f_o[1] OG_6 l1.W3 + + + l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 io_leftL.a2f_o[2] OG_7 l1.W0 + + + l1.W8 l1.W7 l2.W3 l3.W11 l4.W15 io_leftL.a2f_o[0] OG_0 + + + l1.W1 l1.N7 l2.W5 l3.W23 l4.W7 io_leftL.a2f_o[1] + + + l1.N0 l1.N6 l3.N17 io_leftL.a2f_o[2] + + + l1.N6 l1.S12 l3.N8 io_leftL.a2f_o[1] + + + l1.N12 l3.N14 io_leftL.a2f_o[2] + + + l1.S5 l3.S5 io_leftL.a2f_o[3] OG_2 l1.W12 + + + l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 io_leftL.a2f_o[2] OG_2 l1.W4 + + + l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 io_leftL.a2f_o[3] OG_3 l1.N10 + + + l1.W10 l1.W3 io_leftL.a2f_o[4] OG_4 + + + l1.S3 io_leftL.a2f_o[3] + + + l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 io_leftL.a2f_o[4] + + + l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 io_leftL.a2f_o[5] + + + io_leftL.a2f_o[3] io_leftL.a2f_o[0] io_leftL.a2f_o[1] io_leftL.a2f_o[2] + + + io_leftL.a2f_o[3] io_leftL.a2f_o[0] io_leftL.a2f_o[1] io_leftL.a2f_o[1] + + + io_leftL.a2f_o[2] io_leftL.a2f_o[0] io_leftL.a2f_o[1] io_leftL.a2f_o[2] + + + io_leftL.a2f_o[2] io_leftL.a2f_o[1] io_leftL.a2f_o[1] io_leftL.a2f_o[2] + + + io_leftL.a2f_o[5] io_leftL.a2f_o[2] io_leftL.a2f_o[3] io_leftL.a2f_o[4] + + + io_leftL.a2f_o[5] io_leftL.a2f_o[2] io_leftL.a2f_o[3] io_leftL.a2f_o[3] + + + io_leftL.a2f_o[4] io_leftL.a2f_o[2] io_leftL.a2f_o[3] io_leftL.a2f_o[4] + + + io_leftL.a2f_o[4] io_leftL.a2f_o[3] io_leftL.a2f_o[3] io_leftL.a2f_o[4] + + + io_leftL.a2f_o[0] io_leftL.a2f_o[4] io_leftL.a2f_o[5] io_leftL.a2f_o[6] + + + io_leftL.a2f_o[0] io_leftL.a2f_o[4] io_leftL.a2f_o[5] io_leftL.a2f_o[5] + + + io_leftL.a2f_o[6] io_leftL.a2f_o[4] io_leftL.a2f_o[5] io_leftL.a2f_o[6] + + + io_leftL.a2f_o[6] io_leftL.a2f_o[5] io_leftL.a2f_o[5] io_leftL.a2f_o[6] + + + io_leftL.a2f_o[2] io_leftL.a2f_o[6] io_leftL.a2f_o[0] io_leftL.a2f_o[1] + + + io_leftL.a2f_o[2] io_leftL.a2f_o[6] io_leftL.a2f_o[0] io_leftL.a2f_o[0] + + + io_leftL.a2f_o[1] io_leftL.a2f_o[6] io_leftL.a2f_o[0] io_leftL.a2f_o[1] + + + io_leftL.a2f_o[1] io_leftL.a2f_o[0] io_leftL.a2f_o[0] io_leftL.a2f_o[1] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.N0 + mux_16 mux_21 mux_14 + + + l1.E0 + mux_32 mux_6 mux_9 mux_31 + + + l1.S0 + mux_48 mux_22 mux_13 + + + l1.N1 + mux_80 mux_23 mux_26 mux_29 + + + l1.E1 + mux_1 mux_4 mux_42 mux_47 + + + l1.S1 + mux_17 mux_20 mux_46 + + + l1.N2 + mux_49 mux_54 mux_12 + + + l1.E2 + mux_65 mux_39 mux_24 mux_62 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.N3 + mux_18 mux_52 mux_45 + + + l1.E3 + mux_34 mux_37 mux_40 mux_95 + + + l1.S3 + mux_50 mux_53 mux_44 + + + l1.N4 + mux_82 mux_87 mux_57 mux_60 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.S4 + mux_19 mux_84 mux_74 mux_77 + + + l1.N5 + mux_51 mux_85 mux_90 mux_76 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.S5 + mux_83 mux_86 mux_89 mux_92 + + + l1.N6 + mux_112 mux_117 mux_110 + + + l1.E6 + mux_0 mux_102 mux_105 mux_127 + + + l1.S6 + mux_16 mux_118 mux_109 + + + l1.N7 + mux_48 mux_119 mux_122 mux_125 + + + l1.E7 + mux_97 mux_100 mux_10 mux_15 + + + l1.S7 + mux_113 mux_116 mux_14 + + + l1.N8 + mux_17 mux_22 mux_108 + + + l1.E8 + mux_33 mux_7 mux_120 mux_30 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.N0 + mux_114 mux_20 mux_13 + + + l2.E0 + mux_2 mux_5 mux_8 mux_63 + + + l2.S0 + mux_18 mux_21 mux_12 + + + l2.N2 + mux_50 mux_55 mux_25 mux_28 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.S2 + mux_115 mux_52 mux_42 mux_45 + + + l2.N4 + mux_19 mux_53 mux_58 mux_44 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l2.S4 + mux_51 mux_54 mux_57 mux_60 + + + l3.N0 + mux_80 mux_85 mux_78 + + + l3.E0 + mux_96 mux_70 mux_73 mux_95 + + + l3.S0 + mux_112 mux_86 mux_77 + + + l3.N3 + mux_16 mux_87 mux_90 mux_93 + + + l3.E3 + mux_65 mux_68 mux_106 mux_111 + + + l3.S3 + mux_81 mux_84 mux_110 + + + l3.N6 + mux_113 mux_118 mux_76 + + + l3.E6 + mux_1 mux_103 mux_88 mux_126 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.N9 + mux_82 mux_116 mux_109 + + + l3.E9 + mux_98 mux_101 mux_104 mux_31 + + + l3.S9 + mux_114 mux_117 mux_108 + + + l3.N12 + mux_18 mux_23 mux_121 mux_124 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.S12 + mux_83 mux_20 mux_10 mux_13 + + + l3.N15 + mux_115 mux_21 mux_26 mux_12 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.S15 + mux_19 mux_22 mux_25 mux_28 + + + l3.N18 + mux_48 mux_53 mux_46 + + + l3.E18 + mux_64 mux_38 mux_41 mux_63 + + + l3.S18 + mux_80 mux_54 mux_45 + + + l3.N21 + mux_112 mux_55 mux_58 mux_61 + + + l3.E21 + mux_33 mux_36 mux_74 mux_79 + + + l3.S21 + mux_49 mux_52 mux_78 + + + l4.N0 + mux_81 mux_86 mux_44 + + + l4.E0 + mux_97 mux_71 mux_56 mux_94 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.N4 + mux_50 mux_84 mux_77 + + + l4.E4 + mux_66 mux_69 mux_72 mux_127 + + + l4.S4 + mux_82 mux_85 mux_76 + + + l4.N8 + mux_114 mux_119 mux_89 mux_92 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.S8 + mux_51 mux_116 mux_106 mux_109 + + + l4.N12 + mux_83 mux_117 mux_122 mux_108 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l4.S12 + mux_115 mux_118 mux_121 mux_124 + + + l8.N0 + mux_16 mux_21 mux_14 + + + l8.E0 + mux_32 mux_6 mux_9 mux_31 + + + l8.S0 + mux_48 mux_22 mux_13 + + + l8.N8 + mux_80 mux_23 mux_26 mux_29 + + + l8.E8 + mux_1 mux_4 mux_42 mux_47 + + + l8.S8 + mux_17 mux_20 mux_46 + + + l1.N9 + l1.W9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E9 + l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S9 + l1.W9 l1.N9 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N10 + l1.W10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E10 + l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S10 + l1.W10 l1.N10 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N11 + l1.W11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E11 + l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S11 + l1.W11 l1.N11 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N12 + l1.W12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E12 + l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S12 + l1.W12 l1.N12 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + io_leftL.f2a_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_leftL.f2a_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_leftL.f2a_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_leftL.f2a_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_leftL.f2a_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_leftL.f2a_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_leftL.f2a_i[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_leftL.f2a_i[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_leftL.f2a_i[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_leftL.f2a_i[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_leftL.f2a_i[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_leftL.f2a_i[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_leftL.f2a_i[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_leftL.f2a_i[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_leftL.f2a_i[0] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_leftL.f2a_i[1] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + io_leftL.f2a_i[2] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_leftL.f2a_i[3] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_leftL.f2a_i[4] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_leftL.f2a_i[5] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + io_leftL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_leftL.f2a_i[7] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_leftL.f2a_i[8] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_leftL.f2a_i[9] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + io_leftL.f2a_i[10] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_leftL.f2a_i[11] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_leftL.f2a_i[12] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_leftL.f2a_i[13] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + io_leftL.f2a_i[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_leftL.f2a_i[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_leftL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_leftL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + io_leftL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + io_leftL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + io_leftL.f2a_i[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_leftL.f2a_i[7] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + io_leftL.f2a_i[8] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + io_leftL.f2a_i[9] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + io_leftL.f2a_i[10] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 + + + io_leftL.f2a_i[11] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + io_leftL.f2a_i[12] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + io_leftL.f2a_i[13] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + io_leftL.f2a_i[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 + + + io_leftL.f2a_i[1] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + io_leftL.f2a_i[2] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + io_leftL.f2a_i[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + io_leftL.f2a_i[4] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 + + + io_leftL.f2a_i[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + io_leftL.f2a_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + io_leftL.f2a_i[7] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + io_leftL.f2a_i[8] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 + + + io_leftL.f2a_i[9] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + io_leftL.f2a_i[10] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + io_leftL.f2a_i[11] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + io_leftL.f2a_i[12] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 + + + io_leftL.f2a_i[13] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + io_leftL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + io_leftL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + io_leftL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + io_leftL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + io_leftL.lclk[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_leftL.lreset[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_leftL.lclk[14] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_leftL.lreset[14] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_leftL.lclk[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_leftL.lreset[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_leftL.lclk[15] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_leftL.lreset[15] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_leftL.lclk[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_leftL.lreset[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_leftL.lclk[16] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_leftL.lreset[16] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_leftL.lclk[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_leftL.lreset[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_leftL.lclk[17] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_leftL.lreset[17] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_leftL.lclk[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_leftL.lreset[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_leftL.lclk[18] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_leftL.lreset[18] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_leftL.lclk[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_leftL.lreset[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_leftL.lclk[19] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_leftL.lreset[19] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_leftL.lclk[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_leftL.lreset[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_leftL.lclk[20] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_leftL.lreset[20] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_leftL.lclk[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_leftL.lreset[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_leftL.lclk[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_leftL.lreset[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_leftL.lclk[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_leftL.lreset[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_leftL.lclk[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_leftL.lreset[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_leftL.lclk[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_leftL.lreset[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_leftL.lclk[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_leftL.lreset[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_leftL.lclk[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_leftL.lreset[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_leftL.lclk[14] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_leftL.lreset[14] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_leftL.lclk[15] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + io_leftL.lreset[15] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + io_leftL.lclk[16] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_leftL.lreset[16] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_leftL.lclk[17] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_leftL.lreset[17] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_leftL.lclk[18] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_leftL.lreset[18] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_leftL.lclk[19] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + io_leftL.lreset[19] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + io_leftL.lclk[20] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_leftL.lreset[20] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + + + + + + + + + + + + io_rightL.a2f_o[2] + + + io_rightL.a2f_o[0] + + + io_rightL.a2f_o[4] + + + l1.N5 l1.N6 l3.N11 io_rightL.a2f_o[3] + + + l1.N7 l2.N3 l4.N7 io_rightL.a2f_o[1] + + + l1.N8 l3.N14 l8.N7 io_rightL.a2f_o[5] + + + l1.N9 l3.N17 l8.N15 + + + l1.E10 l1.E11 l3.E20 io_rightL.a2f_o[4] + + + l1.E12 l2.E5 l4.E11 io_rightL.a2f_o[2] + + + l1.E0 l3.E23 l8.E7 io_rightL.a2f_o[0] + + + l1.E1 l3.E2 l8.E15 + + + l1.S2 l1.S3 l3.S5 io_rightL.a2f_o[5] + + + l1.S4 l2.S1 l4.S15 io_rightL.a2f_o[3] + + + l1.S5 l3.S8 l8.S7 io_rightL.a2f_o[1] + + + l1.S6 l3.S11 l8.S15 + + + io_rightL.a2f_o[0] + + + io_rightL.a2f_o[4] + + + io_rightL.a2f_o[2] + + + l1.N12 l1.N0 l3.N23 io_rightL.a2f_o[1] + + + l1.N1 l2.N5 l4.N7 io_rightL.a2f_o[5] + + + l1.N2 l3.N2 l8.N7 io_rightL.a2f_o[3] + + + l1.N3 l3.N5 l8.N15 + + + l1.E4 l1.E5 l3.E8 io_rightL.a2f_o[2] + + + l1.E6 l2.E1 l4.E11 io_rightL.a2f_o[0] + + + l1.E7 l3.E11 l8.E7 io_rightL.a2f_o[4] + + + l1.E8 l3.E14 l8.E15 + + + l1.S9 l1.S10 l3.S17 io_rightL.a2f_o[3] + + + l1.S11 l2.S3 l4.S15 io_rightL.a2f_o[1] + + + l1.S12 l3.S20 l8.S7 io_rightL.a2f_o[5] + + + l1.S0 l3.S23 l8.S15 + + + io_rightL.a2f_o[2] + + + io_rightL.a2f_o[0] + + + io_rightL.a2f_o[4] + + + l1.N6 l1.N7 l3.N11 io_rightL.a2f_o[3] + + + l1.N8 l2.N1 l4.N7 io_rightL.a2f_o[1] + + + l1.N9 l3.N14 l8.N7 io_rightL.a2f_o[5] + + + l1.N10 l3.N17 l8.N15 + + + l1.E11 l1.E12 l3.E20 io_rightL.a2f_o[4] + + + l1.E0 l2.E3 l4.E11 io_rightL.a2f_o[2] + + + l1.E1 l3.E23 l8.E7 io_rightL.a2f_o[0] + + + l1.E2 l3.E2 l8.E15 + + + l1.S3 l1.S4 l3.S5 io_rightL.a2f_o[5] + + + l1.S5 l2.S5 l4.S15 io_rightL.a2f_o[3] + + + l1.S6 l3.S8 l8.S7 io_rightL.a2f_o[1] + + + l1.S7 l3.S11 l8.S15 + + + io_rightL.a2f_o[0] + + + io_rightL.a2f_o[4] + + + io_rightL.a2f_o[2] + + + l1.N0 l1.N1 l3.N23 io_rightL.a2f_o[1] + + + l1.N2 l2.N3 l4.N7 io_rightL.a2f_o[5] + + + l1.N3 l3.N2 l8.N7 io_rightL.a2f_o[3] + + + l1.N4 l3.N5 l8.N15 + + + l1.E5 l1.E6 l3.E8 io_rightL.a2f_o[2] + + + l1.E7 l2.E5 l4.E11 io_rightL.a2f_o[0] + + + l1.E8 l3.E11 l8.E7 io_rightL.a2f_o[4] + + + l1.E9 l3.E14 l8.E15 + + + l1.S10 l1.S11 l3.S17 io_rightL.a2f_o[3] + + + l1.S12 l2.S1 l4.S15 io_rightL.a2f_o[1] + + + l1.S0 l3.S20 l8.S7 io_rightL.a2f_o[5] + + + l1.S1 l3.S23 l8.S15 + + + io_rightL.a2f_o[2] + + + io_rightL.a2f_o[0] + + + io_rightL.a2f_o[4] + + + l1.N7 l1.N8 l3.N11 io_rightL.a2f_o[3] + + + l1.N9 l2.N5 l4.N7 io_rightL.a2f_o[1] + + + l1.N10 l3.N14 l8.N7 io_rightL.a2f_o[5] + + + l1.N11 l3.N17 l8.N15 + + + l1.E12 l1.E0 l3.E20 io_rightL.a2f_o[4] + + + l1.E1 l2.E1 l4.E11 io_rightL.a2f_o[2] + + + l1.E2 l3.E23 l8.E7 io_rightL.a2f_o[0] + + + l1.E3 l3.E2 l8.E15 + + + l1.S4 l1.S5 l3.S5 io_rightL.a2f_o[5] + + + l1.S6 l2.S3 l4.S15 io_rightL.a2f_o[3] + + + l1.S7 l3.S8 l8.S7 io_rightL.a2f_o[1] + + + l1.S8 l3.S11 l8.S15 + + + io_rightL.a2f_o[0] + + + io_rightL.a2f_o[4] + + + io_rightL.a2f_o[2] + + + l1.N1 l1.N2 l3.N23 io_rightL.a2f_o[1] + + + l1.N3 l2.N1 l4.N7 io_rightL.a2f_o[5] + + + l1.N4 l3.N2 l8.N7 io_rightL.a2f_o[3] + + + l1.N5 l3.N5 l8.N15 + + + l1.E6 l1.E7 l3.E8 io_rightL.a2f_o[2] + + + l1.E8 l2.E3 l4.E11 io_rightL.a2f_o[0] + + + l1.E9 l3.E11 l8.E7 io_rightL.a2f_o[4] + + + l1.E10 l3.E14 l8.E15 + + + l1.S11 l1.S12 l3.S17 io_rightL.a2f_o[3] + + + l1.S0 l2.S5 l4.S15 io_rightL.a2f_o[1] + + + l1.S1 l3.S20 l8.S7 io_rightL.a2f_o[5] + + + l1.S2 l3.S23 l8.S15 + + + io_rightL.a2f_o[2] + + + io_rightL.a2f_o[0] + + + io_rightL.a2f_o[4] + + + l1.N8 l1.N9 l3.N11 io_rightL.a2f_o[3] + + + l1.N10 l2.N3 l4.N7 io_rightL.a2f_o[1] + + + l1.N11 l3.N14 l8.N7 io_rightL.a2f_o[5] + + + l1.N12 l3.N17 l8.N15 + + + l1.E0 l1.E1 l3.E20 io_rightL.a2f_o[4] + + + l1.E2 l2.E5 l4.E11 io_rightL.a2f_o[2] + + + l1.E3 l3.E23 l8.E7 io_rightL.a2f_o[0] + + + l1.E4 l3.E2 l8.E15 + + + l1.S5 l1.S6 l3.S5 io_rightL.a2f_o[5] + + + l1.S7 l2.S1 l4.S15 io_rightL.a2f_o[3] + + + l1.S8 l3.S8 l8.S7 io_rightL.a2f_o[1] + + + l1.S9 l3.S11 l8.S15 + + + io_rightL.a2f_o[0] + + + io_rightL.a2f_o[4] + + + io_rightL.a2f_o[2] + + + l1.N2 l1.N3 l3.N23 io_rightL.a2f_o[1] + + + l1.N4 l2.N5 l4.N7 io_rightL.a2f_o[5] + + + l1.N5 l3.N2 l8.N7 io_rightL.a2f_o[3] + + + l1.N6 l3.N5 l8.N15 + + + l1.E7 l1.E8 l3.E8 io_rightL.a2f_o[2] + + + l1.E9 l2.E1 l4.E11 io_rightL.a2f_o[0] + + + l1.E10 l3.E11 l8.E7 io_rightL.a2f_o[4] + + + l1.E11 l3.E14 l8.E15 + + + l1.S12 l1.S0 l3.S17 io_rightL.a2f_o[3] + + + l1.S1 l2.S3 l4.S15 io_rightL.a2f_o[1] + + + l1.S2 l3.S20 l8.S7 io_rightL.a2f_o[5] + + + l1.S3 l3.S23 l8.S15 + + + l1.E12 io_rightL.a2f_o[0] OG_0 + + + l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 io_rightL.a2f_o[2] + + + l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 io_rightL.a2f_o[4] + + + l1.N4 l1.S10 l3.N8 io_rightL.a2f_o[1] + + + l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 io_rightL.a2f_o[3] + + + l1.S3 l3.S5 io_rightL.a2f_o[5] OG_2 l1.N2 + + + l1.N9 l3.N11 io_rightL.a2f_o[2] OG_2 l1.S4 + + + l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 io_rightL.a2f_o[4] OG_3 l1.N9 + + + l1.E2 l2.E1 l3.E23 l4.E11 io_rightL.a2f_o[0] OG_4 + + + l1.S1 l1.E7 io_rightL.a2f_o[3] + + + l1.N7 l1.N0 l3.N5 io_rightL.a2f_o[5] + + + l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 io_rightL.a2f_o[1] + + + l1.N6 l1.E12 l3.N2 io_rightL.a2f_o[4] + + + l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 io_rightL.a2f_o[0] OG_6 l1.E5 + + + l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 io_rightL.a2f_o[2] OG_6 l1.S4 + + + l1.N11 io_rightL.a2f_o[5] OG_7 l1.N0 + + + l1.E4 io_rightL.a2f_o[1] OG_0 + + + l1.N10 l1.E3 io_rightL.a2f_o[3] + + + l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 io_rightL.a2f_o[0] + + + l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 io_rightL.a2f_o[2] + + + l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 io_rightL.a2f_o[4] + + + l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 io_rightL.a2f_o[1] OG_2 l1.E0 + + + l1.S1 l3.S11 io_rightL.a2f_o[3] OG_2 l1.N10 + + + l1.S7 io_rightL.a2f_o[5] OG_3 + + + l1.E7 l2.E3 l3.E23 l4.E3 io_rightL.a2f_o[0] OG_4 + + + l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 io_rightL.a2f_o[2] + + + l1.S12 l1.N5 l3.S5 io_rightL.a2f_o[4] + + + l1.S5 l1.S11 l3.S20 io_rightL.a2f_o[1] + + + l1.S11 l1.E4 l3.S2 io_rightL.a2f_o[3] + + + l1.N4 l3.N17 io_rightL.a2f_o[5] OG_6 + + + l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 io_rightL.a2f_o[2] OG_6 l1.S8 + + + l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 io_rightL.a2f_o[4] OG_7 l1.E2 + + + l1.E9 io_rightL.a2f_o[0] OG_0 + + + l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 io_rightL.a2f_o[3] + + + l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 io_rightL.a2f_o[5] + + + l1.N1 l1.S7 l3.N8 io_rightL.a2f_o[1] + + + l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 io_rightL.a2f_o[4] + + + l1.S0 l3.S5 io_rightL.a2f_o[0] OG_2 l1.S6 + + + l1.N6 l3.N11 io_rightL.a2f_o[2] OG_2 l1.E0 + + + l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 io_rightL.a2f_o[5] OG_3 + + + l1.E12 l2.E5 l3.E23 l4.E11 io_rightL.a2f_o[1] OG_4 + + + l1.S11 l1.E4 io_rightL.a2f_o[3] + + + l1.N4 l1.N10 l3.N5 io_rightL.a2f_o[0] + + + l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 io_rightL.a2f_o[2] + + + l1.N3 l1.E9 l3.N2 io_rightL.a2f_o[4] + + + l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 io_rightL.a2f_o[1] OG_6 l1.E2 + + + l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 io_rightL.a2f_o[3] OG_6 + + + l1.N8 io_rightL.a2f_o[5] OG_7 + + + l1.E1 io_rightL.a2f_o[0] OG_0 + + + l1.N7 l1.E0 io_rightL.a2f_o[2] + + + l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 io_rightL.a2f_o[4] + + + l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 io_rightL.a2f_o[1] + + + l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 io_rightL.a2f_o[3] + + + l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 io_rightL.a2f_o[5] OG_2 + + + l1.S11 l3.S11 io_rightL.a2f_o[2] OG_2 + + + l1.S4 io_rightL.a2f_o[4] OG_3 l1.N10 + + + l1.E4 l2.E1 l3.E23 l4.E3 io_rightL.a2f_o[0] OG_4 + + + l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 io_rightL.a2f_o[3] + + + l1.S9 l1.N2 l3.S5 io_rightL.a2f_o[5] + + + l1.S2 l1.S8 l3.S20 io_rightL.a2f_o[1] + + + io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[2] io_rightL.a2f_o[3] + + + io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[1] io_rightL.a2f_o[2] + + + io_rightL.a2f_o[4] io_rightL.a2f_o[0] io_rightL.a2f_o[1] io_rightL.a2f_o[3] + + + io_rightL.a2f_o[4] io_rightL.a2f_o[1] io_rightL.a2f_o[2] io_rightL.a2f_o[3] + + + io_rightL.a2f_o[1] io_rightL.a2f_o[2] io_rightL.a2f_o[4] io_rightL.a2f_o[5] + + + io_rightL.a2f_o[1] io_rightL.a2f_o[2] io_rightL.a2f_o[3] io_rightL.a2f_o[4] + + + io_rightL.a2f_o[0] io_rightL.a2f_o[2] io_rightL.a2f_o[3] io_rightL.a2f_o[5] + + + io_rightL.a2f_o[0] io_rightL.a2f_o[3] io_rightL.a2f_o[4] io_rightL.a2f_o[5] + + + io_rightL.a2f_o[3] io_rightL.a2f_o[4] io_rightL.a2f_o[0] io_rightL.a2f_o[1] + + + io_rightL.a2f_o[3] io_rightL.a2f_o[4] io_rightL.a2f_o[5] io_rightL.a2f_o[0] + + + io_rightL.a2f_o[2] io_rightL.a2f_o[4] io_rightL.a2f_o[5] io_rightL.a2f_o[1] + + + io_rightL.a2f_o[2] io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[1] + + + io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[2] io_rightL.a2f_o[3] + + + io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[1] io_rightL.a2f_o[2] + + + io_rightL.a2f_o[4] io_rightL.a2f_o[0] io_rightL.a2f_o[1] io_rightL.a2f_o[3] + + + io_rightL.a2f_o[4] io_rightL.a2f_o[1] io_rightL.a2f_o[2] io_rightL.a2f_o[3] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 mux_15 + + + l1.N0 + mux_16 mux_21 mux_11 mux_14 + + + l1.S0 + mux_48 mux_22 mux_27 mux_13 + + + l1.W1 + mux_64 mux_7 mux_25 mux_30 + + + l1.N1 + mux_80 mux_23 mux_26 mux_29 + + + l1.S1 + mux_17 mux_20 mux_43 mux_46 + + + l1.W2 + mux_33 mux_38 mux_8 mux_63 + + + l1.N2 + mux_49 mux_54 mux_59 mux_12 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.W3 + mux_2 mux_36 mux_41 mux_79 + + + l1.N3 + mux_18 mux_52 mux_75 mux_45 + + + l1.S3 + mux_50 mux_53 mux_91 mux_44 + + + l1.W4 + mux_66 mux_71 mux_56 mux_61 + + + l1.N4 + mux_82 mux_87 mux_57 mux_60 + + + l1.S4 + mux_84 mux_74 mux_77 + + + l1.W5 + mux_69 mux_72 mux_94 + + + l1.N5 + mux_85 mux_90 mux_76 + + + l1.S5 + mux_86 mux_89 mux_92 + + + l1.W6 + mux_96 mux_101 mux_106 mux_111 + + + l1.N6 + mux_112 mux_117 mux_107 mux_110 + + + l1.S6 + mux_16 mux_118 mux_123 mux_109 + + + l1.W7 + mux_32 mux_103 mux_121 mux_126 + + + l1.N7 + mux_48 mux_119 mux_122 mux_125 + + + l1.S7 + mux_113 mux_116 mux_11 mux_14 + + + l1.W8 + mux_1 mux_6 mux_104 mux_31 + + + l1.N8 + mux_17 mux_22 mux_27 mux_108 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.W0 + mux_98 mux_4 mux_9 mux_47 + + + l2.N0 + mux_114 mux_20 mux_43 mux_13 + + + l2.S0 + mux_18 mux_21 mux_59 mux_12 + + + l2.W2 + mux_34 mux_39 mux_24 mux_29 + + + l2.N2 + mux_50 mux_55 mux_25 mux_28 + + + l2.S2 + mux_52 mux_42 mux_45 + + + l2.W4 + mux_37 mux_40 mux_62 + + + l2.N4 + mux_53 mux_58 mux_44 + + + l2.S4 + mux_54 mux_57 mux_60 + + + l3.W0 + mux_64 mux_69 mux_74 mux_79 + + + l3.N0 + mux_80 mux_85 mux_75 mux_78 + + + l3.S0 + mux_112 mux_86 mux_91 mux_77 + + + l3.W3 + mux_0 mux_71 mux_89 mux_94 + + + l3.N3 + mux_16 mux_87 mux_90 mux_93 + + + l3.S3 + mux_81 mux_84 mux_107 mux_110 + + + l3.W6 + mux_97 mux_102 mux_72 mux_127 + + + l3.N6 + mux_113 mux_118 mux_123 mux_76 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.W9 + mux_66 mux_100 mux_105 mux_15 + + + l3.N9 + mux_82 mux_116 mux_11 mux_109 + + + l3.S9 + mux_114 mux_117 mux_27 mux_108 + + + l3.W12 + mux_2 mux_7 mux_120 mux_125 + + + l3.N12 + mux_18 mux_23 mux_121 mux_124 + + + l3.S12 + mux_20 mux_10 mux_13 + + + l3.W15 + mux_5 mux_8 mux_30 + + + l3.N15 + mux_21 mux_26 mux_12 + + + l3.S15 + mux_22 mux_25 mux_28 + + + l3.W18 + mux_32 mux_37 mux_42 mux_47 + + + l3.N18 + mux_48 mux_53 mux_43 mux_46 + + + l3.S18 + mux_80 mux_54 mux_59 mux_45 + + + l3.W21 + mux_96 mux_39 mux_57 mux_62 + + + l3.N21 + mux_112 mux_55 mux_58 mux_61 + + + l3.S21 + mux_49 mux_52 mux_75 mux_78 + + + l4.W0 + mux_65 mux_70 mux_40 mux_95 + + + l4.N0 + mux_81 mux_86 mux_91 mux_44 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.W4 + mux_34 mux_68 mux_73 mux_111 + + + l4.N4 + mux_50 mux_84 mux_107 mux_77 + + + l4.S4 + mux_82 mux_85 mux_123 mux_76 + + + l4.W8 + mux_98 mux_103 mux_88 mux_93 + + + l4.N8 + mux_114 mux_119 mux_89 mux_92 + + + l4.S8 + mux_116 mux_106 mux_109 + + + l4.W12 + mux_101 mux_104 mux_126 + + + l4.N12 + mux_117 mux_122 mux_108 + + + l4.S12 + mux_118 mux_121 mux_124 + + + l8.W0 + mux_0 mux_5 mux_10 mux_15 + + + l8.N0 + mux_16 mux_21 mux_11 mux_14 + + + l8.S0 + mux_48 mux_22 mux_27 mux_13 + + + l8.W8 + mux_64 mux_7 mux_25 mux_30 + + + l8.N8 + mux_80 mux_23 mux_26 mux_29 + + + l8.S8 + mux_17 mux_20 mux_43 mux_46 + + + l1.W9 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N9 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S9 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W10 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N10 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S10 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W11 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.N11 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S11 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.W12 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N12 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S12 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + io_rightL.f2a_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_rightL.f2a_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_rightL.f2a_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_rightL.f2a_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_rightL.f2a_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_rightL.f2a_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_rightL.f2a_i[0] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_rightL.f2a_i[1] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_rightL.f2a_i[2] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_rightL.f2a_i[3] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_rightL.f2a_i[4] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_rightL.f2a_i[5] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_rightL.f2a_i[0] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_rightL.f2a_i[1] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_rightL.f2a_i[2] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_rightL.f2a_i[3] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + io_rightL.f2a_i[4] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_rightL.f2a_i[5] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_rightL.f2a_i[0] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_rightL.f2a_i[1] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + io_rightL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_rightL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_rightL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_rightL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + io_rightL.f2a_i[0] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_rightL.f2a_i[1] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_rightL.f2a_i[2] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_rightL.f2a_i[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + io_rightL.f2a_i[4] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_rightL.f2a_i[5] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_rightL.f2a_i[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_rightL.f2a_i[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + io_rightL.f2a_i[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_rightL.f2a_i[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + io_rightL.f2a_i[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + io_rightL.f2a_i[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + io_rightL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 + + + io_rightL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + io_rightL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + io_rightL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + io_rightL.f2a_i[4] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 + + + io_rightL.f2a_i[5] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + io_rightL.f2a_i[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + io_rightL.f2a_i[1] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + io_rightL.f2a_i[2] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 + + + io_rightL.f2a_i[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + io_rightL.f2a_i[4] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + io_rightL.f2a_i[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + io_rightL.f2a_i[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 + + + io_rightL.f2a_i[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + io_rightL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + io_rightL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + io_rightL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 + + + io_rightL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + io_rightL.f2a_i[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + io_rightL.f2a_i[1] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + io_rightL.f2a_i[2] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + io_rightL.f2a_i[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + io_rightL.f2a_i[4] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + io_rightL.f2a_i[5] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + io_rightL.lclk[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_rightL.lreset[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_rightL.lclk[6] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_rightL.lreset[6] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_rightL.lclk[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_rightL.lreset[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_rightL.lclk[7] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_rightL.lreset[7] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_rightL.lclk[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_rightL.lreset[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_rightL.lclk[8] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_rightL.lreset[8] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_rightL.lclk[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_rightL.lreset[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_rightL.lclk[9] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_rightL.lreset[9] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_rightL.lclk[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_rightL.lreset[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_rightL.lclk[10] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_rightL.lreset[10] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_rightL.lclk[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_rightL.lreset[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_rightL.lclk[11] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_rightL.lreset[11] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_rightL.lclk[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_rightL.lreset[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_rightL.lclk[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_rightL.lreset[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_rightL.lclk[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_rightL.lreset[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_rightL.lclk[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_rightL.lreset[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_rightL.lclk[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_rightL.lreset[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_rightL.lclk[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_rightL.lreset[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 io_topL.a2f_o[8] + + + l1.W2 l2.W1 l4.W3 io_topL.a2f_o[0] + + + l1.W3 l3.W5 l8.W7 io_topL.a2f_o[16] + + + l1.W4 l3.W8 l8.W15 + + + l1.N5 l1.N6 l3.N11 io_topL.a2f_o[9] + + + l1.N7 l2.N3 l4.N7 io_topL.a2f_o[1] + + + l1.N8 l3.N14 l8.N7 io_topL.a2f_o[17] + + + l1.N9 l3.N17 l8.N15 + + + l1.E10 l1.E11 l3.E20 io_topL.a2f_o[10] + + + l1.E12 l2.E5 l4.E11 io_topL.a2f_o[2] + + + l1.E0 l3.E23 l8.E7 io_topL.a2f_o[18] + + + l1.E1 l3.E2 l8.E15 + + + io_topL.a2f_o[11] + + + io_topL.a2f_o[3] + + + io_topL.a2f_o[19] + + + l1.W7 l1.W8 l3.W14 io_topL.a2f_o[12] + + + l1.W9 l2.W3 l4.W3 io_topL.a2f_o[4] + + + l1.W10 l3.W17 l8.W7 io_topL.a2f_o[20] + + + l1.W11 l3.W20 l8.W15 + + + l1.N12 l1.N0 l3.N23 io_topL.a2f_o[13] + + + l1.N1 l2.N5 l4.N7 io_topL.a2f_o[5] + + + l1.N2 l3.N2 l8.N7 io_topL.a2f_o[21] + + + l1.N3 l3.N5 l8.N15 + + + l1.E4 l1.E5 l3.E8 io_topL.a2f_o[14] + + + l1.E6 l2.E1 l4.E11 io_topL.a2f_o[6] + + + l1.E7 l3.E11 l8.E7 io_topL.a2f_o[22] + + + l1.E8 l3.E14 l8.E15 + + + io_topL.a2f_o[15] + + + io_topL.a2f_o[7] + + + io_topL.a2f_o[23] + + + l1.W1 l1.W2 l3.W2 io_topL.a2f_o[8] + + + l1.W3 l2.W5 l4.W3 io_topL.a2f_o[0] + + + l1.W4 l3.W5 l8.W7 io_topL.a2f_o[16] + + + l1.W5 l3.W8 l8.W15 + + + l1.N6 l1.N7 l3.N11 io_topL.a2f_o[9] + + + l1.N8 l2.N1 l4.N7 io_topL.a2f_o[1] + + + l1.N9 l3.N14 l8.N7 io_topL.a2f_o[17] + + + l1.N10 l3.N17 l8.N15 + + + l1.E11 l1.E12 l3.E20 io_topL.a2f_o[10] + + + l1.E0 l2.E3 l4.E11 io_topL.a2f_o[2] + + + l1.E1 l3.E23 l8.E7 io_topL.a2f_o[18] + + + l1.E2 l3.E2 l8.E15 + + + io_topL.a2f_o[11] + + + io_topL.a2f_o[3] + + + io_topL.a2f_o[19] + + + l1.W8 l1.W9 l3.W14 io_topL.a2f_o[12] + + + l1.W10 l2.W1 l4.W3 io_topL.a2f_o[4] + + + l1.W11 l3.W17 l8.W7 io_topL.a2f_o[20] + + + l1.W12 l3.W20 l8.W15 + + + l1.N0 l1.N1 l3.N23 io_topL.a2f_o[13] + + + l1.N2 l2.N3 l4.N7 io_topL.a2f_o[5] + + + l1.N3 l3.N2 l8.N7 io_topL.a2f_o[21] + + + l1.N4 l3.N5 l8.N15 + + + l1.E5 l1.E6 l3.E8 io_topL.a2f_o[14] + + + l1.E7 l2.E5 l4.E11 io_topL.a2f_o[6] + + + l1.E8 l3.E11 l8.E7 io_topL.a2f_o[22] + + + l1.E9 l3.E14 l8.E15 + + + io_topL.a2f_o[15] + + + io_topL.a2f_o[7] + + + io_topL.a2f_o[23] + + + l1.W2 l1.W3 l3.W2 io_topL.a2f_o[8] + + + l1.W4 l2.W3 l4.W3 io_topL.a2f_o[0] + + + l1.W5 l3.W5 l8.W7 io_topL.a2f_o[16] + + + l1.W6 l3.W8 l8.W15 + + + l1.N7 l1.N8 l3.N11 io_topL.a2f_o[9] + + + l1.N9 l2.N5 l4.N7 io_topL.a2f_o[1] + + + l1.N10 l3.N14 l8.N7 io_topL.a2f_o[17] + + + l1.N11 l3.N17 l8.N15 + + + l1.E12 l1.E0 l3.E20 io_topL.a2f_o[10] + + + l1.E1 l2.E1 l4.E11 io_topL.a2f_o[2] + + + l1.E2 l3.E23 l8.E7 io_topL.a2f_o[18] + + + l1.E3 l3.E2 l8.E15 + + + io_topL.a2f_o[11] + + + io_topL.a2f_o[3] + + + io_topL.a2f_o[19] + + + l1.W9 l1.W10 l3.W14 io_topL.a2f_o[12] + + + l1.W11 l2.W5 l4.W3 io_topL.a2f_o[4] + + + l1.W12 l3.W17 l8.W7 io_topL.a2f_o[20] + + + l1.W0 l3.W20 l8.W15 + + + l1.N1 l1.N2 l3.N23 io_topL.a2f_o[13] + + + l1.N3 l2.N1 l4.N7 io_topL.a2f_o[5] + + + l1.N4 l3.N2 l8.N7 io_topL.a2f_o[21] + + + l1.N5 l3.N5 l8.N15 + + + l1.E6 l1.E7 l3.E8 io_topL.a2f_o[14] + + + l1.E8 l2.E3 l4.E11 io_topL.a2f_o[6] + + + l1.E9 l3.E11 l8.E7 io_topL.a2f_o[22] + + + l1.E10 l3.E14 l8.E15 + + + io_topL.a2f_o[15] + + + io_topL.a2f_o[7] + + + io_topL.a2f_o[23] + + + l1.W3 l1.W4 l3.W2 io_topL.a2f_o[8] + + + l1.W5 l2.W1 l4.W3 io_topL.a2f_o[0] + + + l1.W6 l3.W5 l8.W7 io_topL.a2f_o[16] + + + l1.W7 l3.W8 l8.W15 + + + l1.N8 l1.N9 l3.N11 io_topL.a2f_o[9] + + + l1.N10 l2.N3 l4.N7 io_topL.a2f_o[1] + + + l1.N11 l3.N14 l8.N7 io_topL.a2f_o[17] + + + l1.N12 l3.N17 l8.N15 + + + l1.E0 l1.E1 l3.E20 io_topL.a2f_o[10] + + + l1.E2 l2.E5 l4.E11 io_topL.a2f_o[2] + + + l1.E3 l3.E23 l8.E7 io_topL.a2f_o[18] + + + l1.E4 l3.E2 l8.E15 + + + io_topL.a2f_o[11] + + + io_topL.a2f_o[3] + + + io_topL.a2f_o[19] + + + l1.W10 l1.W11 l3.W14 io_topL.a2f_o[12] + + + l1.W12 l2.W3 l4.W3 io_topL.a2f_o[4] + + + l1.W0 l3.W17 l8.W7 io_topL.a2f_o[20] + + + l1.W1 l3.W20 l8.W15 + + + l1.N2 l1.N3 l3.N23 io_topL.a2f_o[13] + + + l1.N4 l2.N5 l4.N7 io_topL.a2f_o[5] + + + l1.N5 l3.N2 l8.N7 io_topL.a2f_o[21] + + + l1.N6 l3.N5 l8.N15 + + + l1.E7 l1.E8 l3.E8 io_topL.a2f_o[14] + + + l1.E9 l2.E1 l4.E11 io_topL.a2f_o[6] + + + l1.E10 l3.E11 l8.E7 io_topL.a2f_o[22] + + + l1.E11 l3.E14 l8.E15 + + + io_topL.a2f_o[15] + + + io_topL.a2f_o[7] + + + io_topL.a2f_o[23] + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_topL.a2f_o[0] OG_0 + + + l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 io_topL.a2f_o[8] + + + l1.E5 l1.N4 l3.E8 l4.E3 io_topL.a2f_o[16] + + + l1.W11 l1.N4 l3.W20 l3.N8 l4.W11 io_topL.a2f_o[1] + + + l1.E4 l1.E3 l3.E5 l4.E15 io_topL.a2f_o[9] + + + l1.W10 l2.W1 l3.W17 io_topL.a2f_o[17] OG_2 l1.N2 + + + l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 io_topL.a2f_o[2] OG_2 + + + l1.E9 l2.E5 l3.E14 l4.E7 io_topL.a2f_o[10] OG_3 l1.N9 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_topL.a2f_o[18] OG_4 + + + l1.W8 l1.E7 l2.W3 l3.W11 l4.W3 io_topL.a2f_o[3] + + + l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 io_topL.a2f_o[11] + + + l1.E7 l3.E8 l4.E15 io_topL.a2f_o[19] + + + l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 io_topL.a2f_o[4] + + + l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 io_topL.a2f_o[12] OG_6 l1.E5 + + + l1.E12 l2.E1 l3.E14 io_topL.a2f_o[20] OG_6 + + + l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 io_topL.a2f_o[5] OG_7 l1.N0 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_topL.a2f_o[13] OG_0 + + + l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 io_topL.a2f_o[21] + + + l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 io_topL.a2f_o[6] + + + l1.E3 l1.N9 l3.E20 l3.N8 l4.E3 io_topL.a2f_o[14] + + + l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 io_topL.a2f_o[22] + + + l1.E2 l2.E3 l3.E17 io_topL.a2f_o[7] OG_2 l1.E0 + + + l1.W8 l2.W5 l3.W2 io_topL.a2f_o[15] OG_2 l1.N10 + + + l1.W1 l2.W1 l3.W14 l4.W15 io_topL.a2f_o[23] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_topL.a2f_o[0] OG_4 + + + l1.E0 l1.E12 l2.E5 l3.E11 l4.E11 io_topL.a2f_o[8] + + + l1.W6 l1.N5 l3.W20 l4.W15 io_topL.a2f_o[16] + + + l1.W12 l3.W8 l4.W7 io_topL.a2f_o[1] + + + l1.W5 l1.E4 l3.W17 l4.W11 io_topL.a2f_o[9] + + + l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 io_topL.a2f_o[17] OG_6 l1.W6 + + + l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 io_topL.a2f_o[2] OG_6 + + + l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 io_topL.a2f_o[10] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_topL.a2f_o[18] OG_0 + + + l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 io_topL.a2f_o[3] + + + l1.E2 l1.N1 l3.E8 l4.E3 io_topL.a2f_o[11] + + + l1.W8 l1.N1 l3.W20 l3.N8 l4.W11 io_topL.a2f_o[19] + + + l1.E1 l1.E0 l3.E5 l4.E15 io_topL.a2f_o[4] + + + l1.W7 l2.W5 l3.W17 io_topL.a2f_o[12] OG_2 + + + l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 io_topL.a2f_o[20] OG_2 l1.E0 + + + l1.E6 l2.E3 l3.E14 l4.E7 io_topL.a2f_o[5] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_topL.a2f_o[13] OG_4 + + + l1.W5 l1.E4 l2.W1 l3.W11 l4.W3 io_topL.a2f_o[21] + + + l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 io_topL.a2f_o[6] + + + l1.E4 l3.E8 l4.E15 io_topL.a2f_o[14] + + + l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 io_topL.a2f_o[22] + + + l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 io_topL.a2f_o[7] OG_6 l1.E2 + + + l1.E9 l2.E5 l3.E14 io_topL.a2f_o[15] OG_6 l1.W3 + + + l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 io_topL.a2f_o[23] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_topL.a2f_o[0] OG_0 + + + l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 io_topL.a2f_o[8] + + + l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 io_topL.a2f_o[16] + + + l1.E0 l1.N6 l3.E20 l3.N8 l4.E3 io_topL.a2f_o[1] + + + l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 io_topL.a2f_o[9] + + + l1.E12 l2.E1 l3.E17 io_topL.a2f_o[17] OG_2 l1.W12 + + + l1.W5 l2.W3 l3.W2 io_topL.a2f_o[2] OG_2 l1.W4 + + + l1.W11 l2.W5 l3.W14 l4.W15 io_topL.a2f_o[10] OG_3 l1.N10 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_topL.a2f_o[18] OG_4 + + + l1.E10 l1.E9 l2.E3 l3.E11 l4.E11 io_topL.a2f_o[3] + + + l1.W3 l1.N2 l3.W20 l4.W15 io_topL.a2f_o[11] + + + l1.W9 l3.W8 l4.W7 io_topL.a2f_o[19] + + + io_topL.a2f_o[17] io_topL.a2f_o[0] io_topL.a2f_o[8] io_topL.a2f_o[9] + + + io_topL.a2f_o[17] io_topL.a2f_o[0] io_topL.a2f_o[1] io_topL.a2f_o[8] + + + io_topL.a2f_o[16] io_topL.a2f_o[0] io_topL.a2f_o[1] io_topL.a2f_o[9] + + + io_topL.a2f_o[16] io_topL.a2f_o[1] io_topL.a2f_o[8] io_topL.a2f_o[9] + + + io_topL.a2f_o[19] io_topL.a2f_o[2] io_topL.a2f_o[10] io_topL.a2f_o[11] + + + io_topL.a2f_o[19] io_topL.a2f_o[2] io_topL.a2f_o[3] io_topL.a2f_o[10] + + + io_topL.a2f_o[18] io_topL.a2f_o[2] io_topL.a2f_o[3] io_topL.a2f_o[11] + + + io_topL.a2f_o[18] io_topL.a2f_o[3] io_topL.a2f_o[10] io_topL.a2f_o[11] + + + io_topL.a2f_o[21] io_topL.a2f_o[4] io_topL.a2f_o[12] io_topL.a2f_o[13] + + + io_topL.a2f_o[21] io_topL.a2f_o[4] io_topL.a2f_o[5] io_topL.a2f_o[12] + + + io_topL.a2f_o[20] io_topL.a2f_o[4] io_topL.a2f_o[5] io_topL.a2f_o[13] + + + io_topL.a2f_o[20] io_topL.a2f_o[5] io_topL.a2f_o[12] io_topL.a2f_o[13] + + + io_topL.a2f_o[23] io_topL.a2f_o[6] io_topL.a2f_o[14] io_topL.a2f_o[15] + + + io_topL.a2f_o[23] io_topL.a2f_o[6] io_topL.a2f_o[7] io_topL.a2f_o[14] + + + io_topL.a2f_o[22] io_topL.a2f_o[6] io_topL.a2f_o[7] io_topL.a2f_o[15] + + + io_topL.a2f_o[22] io_topL.a2f_o[7] io_topL.a2f_o[14] io_topL.a2f_o[15] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 + + + l1.E0 + mux_32 mux_6 mux_9 + + + l1.S0 + mux_48 mux_22 mux_27 mux_13 + + + l1.W1 + mux_64 mux_7 mux_25 mux_30 + + + l1.E1 + mux_1 mux_4 mux_42 + + + l1.S1 + mux_17 mux_20 mux_43 mux_46 + + + l1.W2 + mux_33 mux_38 mux_8 + + + l1.E2 + mux_65 mux_39 mux_24 mux_62 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.W3 + mux_2 mux_36 mux_41 + + + l1.E3 + mux_34 mux_37 mux_40 + + + l1.S3 + mux_50 mux_53 mux_91 mux_44 + + + l1.W4 + mux_66 mux_71 mux_56 mux_61 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.S4 + mux_19 mux_84 mux_74 mux_77 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.S5 + mux_83 mux_86 mux_89 mux_92 + + + l1.W6 + mux_96 mux_101 mux_106 + + + l1.E6 + mux_0 mux_102 mux_105 + + + l1.S6 + mux_16 mux_118 mux_123 mux_109 + + + l1.W7 + mux_32 mux_103 mux_121 mux_126 + + + l1.E7 + mux_97 mux_100 mux_10 + + + l1.S7 + mux_113 mux_116 mux_11 mux_14 + + + l1.W8 + mux_1 mux_6 mux_104 + + + l1.E8 + mux_33 mux_7 mux_120 mux_30 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.W0 + mux_98 mux_4 mux_9 + + + l2.E0 + mux_2 mux_5 mux_8 + + + l2.S0 + mux_18 mux_21 mux_59 mux_12 + + + l2.W2 + mux_34 mux_39 mux_24 mux_29 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.S2 + mux_115 mux_52 mux_42 mux_45 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l2.S4 + mux_51 mux_54 mux_57 mux_60 + + + l3.W0 + mux_64 mux_69 mux_74 + + + l3.E0 + mux_96 mux_70 mux_73 + + + l3.S0 + mux_112 mux_86 mux_91 mux_77 + + + l3.W3 + mux_0 mux_71 mux_89 mux_94 + + + l3.E3 + mux_65 mux_68 mux_106 + + + l3.S3 + mux_81 mux_84 mux_107 mux_110 + + + l3.W6 + mux_97 mux_102 mux_72 + + + l3.E6 + mux_1 mux_103 mux_88 mux_126 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.W9 + mux_66 mux_100 mux_105 + + + l3.E9 + mux_98 mux_101 mux_104 + + + l3.S9 + mux_114 mux_117 mux_27 mux_108 + + + l3.W12 + mux_2 mux_7 mux_120 mux_125 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.S12 + mux_83 mux_20 mux_10 mux_13 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.S15 + mux_19 mux_22 mux_25 mux_28 + + + l3.W18 + mux_32 mux_37 mux_42 + + + l3.E18 + mux_64 mux_38 mux_41 + + + l3.S18 + mux_80 mux_54 mux_59 mux_45 + + + l3.W21 + mux_96 mux_39 mux_57 mux_62 + + + l3.E21 + mux_33 mux_36 mux_74 + + + l3.S21 + mux_49 mux_52 mux_75 mux_78 + + + l4.W0 + mux_65 mux_70 mux_40 + + + l4.E0 + mux_97 mux_71 mux_56 mux_94 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.W4 + mux_34 mux_68 mux_73 + + + l4.E4 + mux_66 mux_69 mux_72 + + + l4.S4 + mux_82 mux_85 mux_123 mux_76 + + + l4.W8 + mux_98 mux_103 mux_88 mux_93 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.S8 + mux_51 mux_116 mux_106 mux_109 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l4.S12 + mux_115 mux_118 mux_121 mux_124 + + + l8.W0 + mux_0 mux_5 mux_10 + + + l8.E0 + mux_32 mux_6 mux_9 + + + l8.S0 + mux_48 mux_22 mux_27 mux_13 + + + l8.W8 + mux_64 mux_7 mux_25 mux_30 + + + l8.E8 + mux_1 mux_4 mux_42 + + + l8.S8 + mux_17 mux_20 mux_43 mux_46 + + + l1.W9 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E9 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S9 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W10 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E10 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S10 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W11 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E11 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S11 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.W12 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E12 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S12 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + io_topL.f2a_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.f2a_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.f2a_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.f2a_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.f2a_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.f2a_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.f2a_i[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.f2a_i[0] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.f2a_i[1] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.f2a_i[2] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.f2a_i[3] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_topL.f2a_i[4] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_topL.f2a_i[5] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_topL.f2a_i[6] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_topL.f2a_i[0] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_topL.f2a_i[1] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_topL.f2a_i[2] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_topL.f2a_i[3] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_topL.f2a_i[4] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_topL.f2a_i[5] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_topL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_topL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_topL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_topL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_topL.f2a_i[4] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_topL.f2a_i[5] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_topL.f2a_i[6] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.f2a_i[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_topL.f2a_i[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_topL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_topL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_topL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + io_topL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + io_topL.f2a_i[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + io_topL.f2a_i[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 + + + io_topL.f2a_i[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + io_topL.f2a_i[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + io_topL.f2a_i[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + io_topL.f2a_i[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 + + + io_topL.f2a_i[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.f2a_i[6] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.f2a_i[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.f2a_i[1] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 + + + io_topL.f2a_i[2] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.f2a_i[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + io_topL.f2a_i[4] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + io_topL.f2a_i[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 + + + io_topL.f2a_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + io_topL.f2a_i[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + io_topL.f2a_i[1] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + io_topL.f2a_i[2] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 + + + io_topL.f2a_i[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + io_topL.f2a_i[4] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + io_topL.f2a_i[5] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + io_topL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 + + + io_topL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + io_topL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + io_topL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + io_topL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 + + + io_topL.lclk[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lreset[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lclk[7] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lreset[7] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lclk[14] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lreset[14] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lclk[21] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lreset[21] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lclk[28] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lreset[28] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_topL.lclk[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lreset[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lclk[8] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lreset[8] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lclk[15] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lreset[15] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lclk[22] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lreset[22] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lclk[29] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lreset[29] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_topL.lclk[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lreset[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lclk[9] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lreset[9] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lclk[16] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lreset[16] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lclk[23] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lreset[23] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lclk[30] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lreset[30] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_topL.lclk[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lreset[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lclk[10] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lreset[10] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lclk[17] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lreset[17] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lclk[24] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lreset[24] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lclk[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.lreset[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.lclk[11] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.lreset[11] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.lclk[18] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.lreset[18] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.lclk[25] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.lreset[25] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_topL.lclk[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.lreset[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.lclk[12] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.lreset[12] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.lclk[19] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.lreset[19] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.lclk[26] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.lreset[26] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_topL.lclk[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.lreset[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.lclk[13] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.lreset[13] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.lclk[20] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.lreset[20] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.lclk[27] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.lreset[27] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_topL.lclk[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lreset[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lclk[14] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lreset[14] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lclk[21] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lreset[21] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lclk[28] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lreset[28] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lclk[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.lreset[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.lclk[15] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.lreset[15] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.lclk[22] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.lreset[22] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.lclk[29] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.lreset[29] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_topL.lclk[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.lreset[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.lclk[16] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.lreset[16] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.lclk[23] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.lreset[23] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.lclk[30] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.lreset[30] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_topL.lclk[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_topL.lreset[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_topL.lclk[17] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_topL.lreset[17] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_topL.lclk[24] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_topL.lreset[24] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_topL.lclk[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_topL.lreset[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_topL.lclk[18] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_topL.lreset[18] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_topL.lclk[25] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_topL.lreset[25] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_topL.lclk[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_topL.lreset[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_topL.lclk[19] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_topL.lreset[19] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_topL.lclk[26] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_topL.lreset[26] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_topL.lclk[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_topL.lreset[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_topL.lclk[20] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_topL.lreset[20] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_topL.lclk[27] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_topL.lreset[27] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_topL.lclk[14] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_topL.lreset[14] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_topL.lclk[21] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_topL.lreset[21] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_topL.lclk[28] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_topL.lreset[28] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_topL.lclk[15] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_topL.lreset[15] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_topL.lclk[22] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_topL.lreset[22] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_topL.lclk[29] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_topL.lreset[29] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_topL.lclk[16] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_topL.lreset[16] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_topL.lclk[23] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_topL.lreset[23] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_topL.lclk[30] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_topL.lreset[30] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_topL.lclk[17] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_topL.lreset[17] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_topL.lclk[24] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_topL.lreset[24] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_topL.lclk[18] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_topL.lreset[18] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_topL.lclk[25] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_topL.lreset[25] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_topL.lclk[19] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_topL.lreset[19] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_topL.lclk[26] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_topL.lreset[26] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_topL.lclk[20] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_topL.lreset[20] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_topL.lclk[27] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_topL.lreset[27] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_topL.lclk[21] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_topL.lreset[21] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_topL.lclk[28] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_topL.lreset[28] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_topL.lclk[22] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_topL.lreset[22] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_topL.lclk[29] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_topL.lreset[29] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_topL.lclk[23] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lreset[23] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lclk[30] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lreset[30] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_topL.lclk[24] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_topL.lreset[24] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_topL.lclk[25] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_topL.lreset[25] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_topL.lclk[26] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_topL.lreset[26] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_topL.lclk[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lreset[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_topL.lclk[28] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_topL.lreset[28] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_topL.lclk[29] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_topL.lreset[29] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_topL.lclk[30] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_topL.lreset[30] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 io_top_dspL.a2f_o[8] + + + l1.W2 l2.W1 l4.W3 io_top_dspL.a2f_o[0] + + + l1.W3 l3.W5 l8.W7 io_top_dspL.a2f_o[16] + + + l1.W4 l3.W8 l8.W15 + + + l1.N5 l1.N6 l3.N11 io_top_dspL.a2f_o[9] + + + l1.N7 l2.N3 l4.N7 io_top_dspL.a2f_o[1] + + + l1.N8 l3.N14 l8.N7 io_top_dspL.a2f_o[17] + + + l1.N9 l3.N17 l8.N15 + + + l1.E10 l1.E11 l3.E20 io_top_dspL.a2f_o[10] + + + l1.E12 l2.E5 l4.E11 io_top_dspL.a2f_o[2] + + + l1.E0 l3.E23 l8.E7 io_top_dspL.a2f_o[18] + + + l1.E1 l3.E2 l8.E15 + + + io_top_dspL.a2f_o[11] + + + io_top_dspL.a2f_o[3] + + + io_top_dspL.a2f_o[19] + + + l1.W7 l1.W8 l3.W14 io_top_dspL.a2f_o[12] + + + l1.W9 l2.W3 l4.W3 io_top_dspL.a2f_o[4] + + + l1.W10 l3.W17 l8.W7 io_top_dspL.a2f_o[20] + + + l1.W11 l3.W20 l8.W15 + + + l1.N12 l1.N0 l3.N23 io_top_dspL.a2f_o[13] + + + l1.N1 l2.N5 l4.N7 io_top_dspL.a2f_o[5] + + + l1.N2 l3.N2 l8.N7 io_top_dspL.a2f_o[21] + + + l1.N3 l3.N5 l8.N15 + + + l1.E4 l1.E5 l3.E8 io_top_dspL.a2f_o[14] + + + l1.E6 l2.E1 l4.E11 io_top_dspL.a2f_o[6] + + + l1.E7 l3.E11 l8.E7 io_top_dspL.a2f_o[22] + + + l1.E8 l3.E14 l8.E15 + + + io_top_dspL.a2f_o[15] + + + io_top_dspL.a2f_o[7] + + + io_top_dspL.a2f_o[23] + + + l1.W1 l1.W2 l3.W2 io_top_dspL.a2f_o[8] + + + l1.W3 l2.W5 l4.W3 io_top_dspL.a2f_o[0] + + + l1.W4 l3.W5 l8.W7 io_top_dspL.a2f_o[16] + + + l1.W5 l3.W8 l8.W15 + + + l1.N6 l1.N7 l3.N11 io_top_dspL.a2f_o[9] + + + l1.N8 l2.N1 l4.N7 io_top_dspL.a2f_o[1] + + + l1.N9 l3.N14 l8.N7 io_top_dspL.a2f_o[17] + + + l1.N10 l3.N17 l8.N15 + + + l1.E11 l1.E12 l3.E20 io_top_dspL.a2f_o[10] + + + l1.E0 l2.E3 l4.E11 io_top_dspL.a2f_o[2] + + + l1.E1 l3.E23 l8.E7 io_top_dspL.a2f_o[18] + + + l1.E2 l3.E2 l8.E15 + + + io_top_dspL.a2f_o[11] + + + io_top_dspL.a2f_o[3] + + + io_top_dspL.a2f_o[19] + + + l1.W8 l1.W9 l3.W14 io_top_dspL.a2f_o[12] + + + l1.W10 l2.W1 l4.W3 io_top_dspL.a2f_o[4] + + + l1.W11 l3.W17 l8.W7 io_top_dspL.a2f_o[20] + + + l1.W12 l3.W20 l8.W15 + + + l1.N0 l1.N1 l3.N23 io_top_dspL.a2f_o[13] + + + l1.N2 l2.N3 l4.N7 io_top_dspL.a2f_o[5] + + + l1.N3 l3.N2 l8.N7 io_top_dspL.a2f_o[21] + + + l1.N4 l3.N5 l8.N15 + + + l1.E5 l1.E6 l3.E8 io_top_dspL.a2f_o[14] + + + l1.E7 l2.E5 l4.E11 io_top_dspL.a2f_o[6] + + + l1.E8 l3.E11 l8.E7 io_top_dspL.a2f_o[22] + + + l1.E9 l3.E14 l8.E15 + + + io_top_dspL.a2f_o[15] + + + io_top_dspL.a2f_o[7] + + + io_top_dspL.a2f_o[23] + + + l1.W2 l1.W3 l3.W2 io_top_dspL.a2f_o[8] + + + l1.W4 l2.W3 l4.W3 io_top_dspL.a2f_o[0] + + + l1.W5 l3.W5 l8.W7 io_top_dspL.a2f_o[16] + + + l1.W6 l3.W8 l8.W15 + + + l1.N7 l1.N8 l3.N11 io_top_dspL.a2f_o[9] + + + l1.N9 l2.N5 l4.N7 io_top_dspL.a2f_o[1] + + + l1.N10 l3.N14 l8.N7 io_top_dspL.a2f_o[17] + + + l1.N11 l3.N17 l8.N15 + + + l1.E12 l1.E0 l3.E20 io_top_dspL.a2f_o[10] + + + l1.E1 l2.E1 l4.E11 io_top_dspL.a2f_o[2] + + + l1.E2 l3.E23 l8.E7 io_top_dspL.a2f_o[18] + + + l1.E3 l3.E2 l8.E15 + + + io_top_dspL.a2f_o[11] + + + io_top_dspL.a2f_o[3] + + + io_top_dspL.a2f_o[19] + + + l1.W9 l1.W10 l3.W14 io_top_dspL.a2f_o[12] + + + l1.W11 l2.W5 l4.W3 io_top_dspL.a2f_o[4] + + + l1.W12 l3.W17 l8.W7 io_top_dspL.a2f_o[20] + + + l1.W0 l3.W20 l8.W15 + + + l1.N1 l1.N2 l3.N23 io_top_dspL.a2f_o[13] + + + l1.N3 l2.N1 l4.N7 io_top_dspL.a2f_o[5] + + + l1.N4 l3.N2 l8.N7 io_top_dspL.a2f_o[21] + + + l1.N5 l3.N5 l8.N15 + + + l1.E6 l1.E7 l3.E8 io_top_dspL.a2f_o[14] + + + l1.E8 l2.E3 l4.E11 io_top_dspL.a2f_o[6] + + + l1.E9 l3.E11 l8.E7 io_top_dspL.a2f_o[22] + + + l1.E10 l3.E14 l8.E15 + + + io_top_dspL.a2f_o[15] + + + io_top_dspL.a2f_o[7] + + + io_top_dspL.a2f_o[23] + + + l1.W3 l1.W4 l3.W2 io_top_dspL.a2f_o[8] + + + l1.W5 l2.W1 l4.W3 io_top_dspL.a2f_o[0] + + + l1.W6 l3.W5 l8.W7 io_top_dspL.a2f_o[16] + + + l1.W7 l3.W8 l8.W15 + + + l1.N8 l1.N9 l3.N11 io_top_dspL.a2f_o[9] + + + l1.N10 l2.N3 l4.N7 io_top_dspL.a2f_o[1] + + + l1.N11 l3.N14 l8.N7 io_top_dspL.a2f_o[17] + + + l1.N12 l3.N17 l8.N15 + + + l1.E0 l1.E1 l3.E20 io_top_dspL.a2f_o[10] + + + l1.E2 l2.E5 l4.E11 io_top_dspL.a2f_o[2] + + + l1.E3 l3.E23 l8.E7 io_top_dspL.a2f_o[18] + + + l1.E4 l3.E2 l8.E15 + + + io_top_dspL.a2f_o[11] + + + io_top_dspL.a2f_o[3] + + + io_top_dspL.a2f_o[19] + + + l1.W10 l1.W11 l3.W14 io_top_dspL.a2f_o[12] + + + l1.W12 l2.W3 l4.W3 io_top_dspL.a2f_o[4] + + + l1.W0 l3.W17 l8.W7 io_top_dspL.a2f_o[20] + + + l1.W1 l3.W20 l8.W15 + + + l1.N2 l1.N3 l3.N23 io_top_dspL.a2f_o[13] + + + l1.N4 l2.N5 l4.N7 io_top_dspL.a2f_o[5] + + + l1.N5 l3.N2 l8.N7 io_top_dspL.a2f_o[21] + + + l1.N6 l3.N5 l8.N15 + + + l1.E7 l1.E8 l3.E8 io_top_dspL.a2f_o[14] + + + l1.E9 l2.E1 l4.E11 io_top_dspL.a2f_o[6] + + + l1.E10 l3.E11 l8.E7 io_top_dspL.a2f_o[22] + + + l1.E11 l3.E14 l8.E15 + + + io_top_dspL.a2f_o[15] + + + io_top_dspL.a2f_o[7] + + + io_top_dspL.a2f_o[23] + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_top_dspL.a2f_o[0] OG_0 + + + l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 io_top_dspL.a2f_o[8] + + + l1.E5 l1.N4 l3.E8 l4.E3 io_top_dspL.a2f_o[16] + + + l1.W11 l1.N4 l3.W20 l3.N8 l4.W11 io_top_dspL.a2f_o[1] + + + l1.E4 l1.E3 l3.E5 l4.E15 io_top_dspL.a2f_o[9] + + + l1.W10 l2.W1 l3.W17 io_top_dspL.a2f_o[17] OG_2 l1.N2 + + + l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 io_top_dspL.a2f_o[2] OG_2 + + + l1.E9 l2.E5 l3.E14 l4.E7 io_top_dspL.a2f_o[10] OG_3 l1.N9 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_top_dspL.a2f_o[18] OG_4 + + + l1.W8 l1.E7 l2.W3 l3.W11 l4.W3 io_top_dspL.a2f_o[3] + + + l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 io_top_dspL.a2f_o[11] + + + l1.E7 l3.E8 l4.E15 io_top_dspL.a2f_o[19] + + + l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 io_top_dspL.a2f_o[4] + + + l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 io_top_dspL.a2f_o[12] OG_6 l1.E5 + + + l1.E12 l2.E1 l3.E14 io_top_dspL.a2f_o[20] OG_6 + + + l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 io_top_dspL.a2f_o[5] OG_7 l1.N0 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_top_dspL.a2f_o[13] OG_0 + + + l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 io_top_dspL.a2f_o[21] + + + l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 io_top_dspL.a2f_o[6] + + + l1.E3 l1.N9 l3.E20 l3.N8 l4.E3 io_top_dspL.a2f_o[14] + + + l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 io_top_dspL.a2f_o[22] + + + l1.E2 l2.E3 l3.E17 io_top_dspL.a2f_o[7] OG_2 l1.E0 + + + l1.W8 l2.W5 l3.W2 io_top_dspL.a2f_o[15] OG_2 l1.N10 + + + l1.W1 l2.W1 l3.W14 l4.W15 io_top_dspL.a2f_o[23] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_top_dspL.a2f_o[0] OG_4 + + + l1.E0 l1.E12 l2.E5 l3.E11 l4.E11 io_top_dspL.a2f_o[8] + + + l1.W6 l1.N5 l3.W20 l4.W15 io_top_dspL.a2f_o[16] + + + l1.W12 l3.W8 l4.W7 io_top_dspL.a2f_o[1] + + + l1.W5 l1.E4 l3.W17 l4.W11 io_top_dspL.a2f_o[9] + + + l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 io_top_dspL.a2f_o[17] OG_6 l1.W6 + + + l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 io_top_dspL.a2f_o[2] OG_6 + + + l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 io_top_dspL.a2f_o[10] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_top_dspL.a2f_o[18] OG_0 + + + l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 io_top_dspL.a2f_o[3] + + + l1.E2 l1.N1 l3.E8 l4.E3 io_top_dspL.a2f_o[11] + + + l1.W8 l1.N1 l3.W20 l3.N8 l4.W11 io_top_dspL.a2f_o[19] + + + l1.E1 l1.E0 l3.E5 l4.E15 io_top_dspL.a2f_o[4] + + + l1.W7 l2.W5 l3.W17 io_top_dspL.a2f_o[12] OG_2 + + + l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 io_top_dspL.a2f_o[20] OG_2 l1.E0 + + + l1.E6 l2.E3 l3.E14 l4.E7 io_top_dspL.a2f_o[5] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_top_dspL.a2f_o[13] OG_4 + + + l1.W5 l1.E4 l2.W1 l3.W11 l4.W3 io_top_dspL.a2f_o[21] + + + l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 io_top_dspL.a2f_o[6] + + + l1.E4 l3.E8 l4.E15 io_top_dspL.a2f_o[14] + + + l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 io_top_dspL.a2f_o[22] + + + l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 io_top_dspL.a2f_o[7] OG_6 l1.E2 + + + l1.E9 l2.E5 l3.E14 io_top_dspL.a2f_o[15] OG_6 l1.W3 + + + l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 io_top_dspL.a2f_o[23] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_top_dspL.a2f_o[0] OG_0 + + + l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 io_top_dspL.a2f_o[8] + + + l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 io_top_dspL.a2f_o[16] + + + l1.E0 l1.N6 l3.E20 l3.N8 l4.E3 io_top_dspL.a2f_o[1] + + + l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 io_top_dspL.a2f_o[9] + + + l1.E12 l2.E1 l3.E17 io_top_dspL.a2f_o[17] OG_2 l1.W12 + + + l1.W5 l2.W3 l3.W2 io_top_dspL.a2f_o[2] OG_2 l1.W4 + + + l1.W11 l2.W5 l3.W14 l4.W15 io_top_dspL.a2f_o[10] OG_3 l1.N10 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_top_dspL.a2f_o[18] OG_4 + + + l1.E10 l1.E9 l2.E3 l3.E11 l4.E11 io_top_dspL.a2f_o[3] + + + l1.W3 l1.N2 l3.W20 l4.W15 io_top_dspL.a2f_o[11] + + + l1.W9 l3.W8 l4.W7 io_top_dspL.a2f_o[19] + + + io_top_dspL.a2f_o[17] io_top_dspL.a2f_o[0] io_top_dspL.a2f_o[8] io_top_dspL.a2f_o[9] + + + io_top_dspL.a2f_o[17] io_top_dspL.a2f_o[0] io_top_dspL.a2f_o[1] io_top_dspL.a2f_o[8] + + + io_top_dspL.a2f_o[16] io_top_dspL.a2f_o[0] io_top_dspL.a2f_o[1] io_top_dspL.a2f_o[9] + + + io_top_dspL.a2f_o[16] io_top_dspL.a2f_o[1] io_top_dspL.a2f_o[8] io_top_dspL.a2f_o[9] + + + io_top_dspL.a2f_o[19] io_top_dspL.a2f_o[2] io_top_dspL.a2f_o[10] io_top_dspL.a2f_o[11] + + + io_top_dspL.a2f_o[19] io_top_dspL.a2f_o[2] io_top_dspL.a2f_o[3] io_top_dspL.a2f_o[10] + + + io_top_dspL.a2f_o[18] io_top_dspL.a2f_o[2] io_top_dspL.a2f_o[3] io_top_dspL.a2f_o[11] + + + io_top_dspL.a2f_o[18] io_top_dspL.a2f_o[3] io_top_dspL.a2f_o[10] io_top_dspL.a2f_o[11] + + + io_top_dspL.a2f_o[21] io_top_dspL.a2f_o[4] io_top_dspL.a2f_o[12] io_top_dspL.a2f_o[13] + + + io_top_dspL.a2f_o[21] io_top_dspL.a2f_o[4] io_top_dspL.a2f_o[5] io_top_dspL.a2f_o[12] + + + io_top_dspL.a2f_o[20] io_top_dspL.a2f_o[4] io_top_dspL.a2f_o[5] io_top_dspL.a2f_o[13] + + + io_top_dspL.a2f_o[20] io_top_dspL.a2f_o[5] io_top_dspL.a2f_o[12] io_top_dspL.a2f_o[13] + + + io_top_dspL.a2f_o[23] io_top_dspL.a2f_o[6] io_top_dspL.a2f_o[14] io_top_dspL.a2f_o[15] + + + io_top_dspL.a2f_o[23] io_top_dspL.a2f_o[6] io_top_dspL.a2f_o[7] io_top_dspL.a2f_o[14] + + + io_top_dspL.a2f_o[22] io_top_dspL.a2f_o[6] io_top_dspL.a2f_o[7] io_top_dspL.a2f_o[15] + + + io_top_dspL.a2f_o[22] io_top_dspL.a2f_o[7] io_top_dspL.a2f_o[14] io_top_dspL.a2f_o[15] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 + + + l1.E0 + mux_32 mux_6 mux_9 + + + l1.S0 + mux_48 mux_22 mux_27 mux_13 + + + l1.W1 + mux_64 mux_7 mux_25 mux_30 + + + l1.E1 + mux_1 mux_4 mux_42 + + + l1.S1 + mux_17 mux_20 mux_43 mux_46 + + + l1.W2 + mux_33 mux_38 mux_8 + + + l1.E2 + mux_65 mux_39 mux_24 mux_62 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.W3 + mux_2 mux_36 mux_41 + + + l1.E3 + mux_34 mux_37 mux_40 + + + l1.S3 + mux_50 mux_53 mux_91 mux_44 + + + l1.W4 + mux_66 mux_71 mux_56 mux_61 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.S4 + mux_19 mux_84 mux_74 mux_77 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.S5 + mux_83 mux_86 mux_89 mux_92 + + + l1.W6 + mux_96 mux_101 mux_106 + + + l1.E6 + mux_0 mux_102 mux_105 + + + l1.S6 + mux_16 mux_118 mux_123 mux_109 + + + l1.W7 + mux_32 mux_103 mux_121 mux_126 + + + l1.E7 + mux_97 mux_100 mux_10 + + + l1.S7 + mux_113 mux_116 mux_11 mux_14 + + + l1.W8 + mux_1 mux_6 mux_104 + + + l1.E8 + mux_33 mux_7 mux_120 mux_30 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.W0 + mux_98 mux_4 mux_9 + + + l2.E0 + mux_2 mux_5 mux_8 + + + l2.S0 + mux_18 mux_21 mux_59 mux_12 + + + l2.W2 + mux_34 mux_39 mux_24 mux_29 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.S2 + mux_115 mux_52 mux_42 mux_45 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l2.S4 + mux_51 mux_54 mux_57 mux_60 + + + l3.W0 + mux_64 mux_69 mux_74 + + + l3.E0 + mux_96 mux_70 mux_73 + + + l3.S0 + mux_112 mux_86 mux_91 mux_77 + + + l3.W3 + mux_0 mux_71 mux_89 mux_94 + + + l3.E3 + mux_65 mux_68 mux_106 + + + l3.S3 + mux_81 mux_84 mux_107 mux_110 + + + l3.W6 + mux_97 mux_102 mux_72 + + + l3.E6 + mux_1 mux_103 mux_88 mux_126 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.W9 + mux_66 mux_100 mux_105 + + + l3.E9 + mux_98 mux_101 mux_104 + + + l3.S9 + mux_114 mux_117 mux_27 mux_108 + + + l3.W12 + mux_2 mux_7 mux_120 mux_125 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.S12 + mux_83 mux_20 mux_10 mux_13 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.S15 + mux_19 mux_22 mux_25 mux_28 + + + l3.W18 + mux_32 mux_37 mux_42 + + + l3.E18 + mux_64 mux_38 mux_41 + + + l3.S18 + mux_80 mux_54 mux_59 mux_45 + + + l3.W21 + mux_96 mux_39 mux_57 mux_62 + + + l3.E21 + mux_33 mux_36 mux_74 + + + l3.S21 + mux_49 mux_52 mux_75 mux_78 + + + l4.W0 + mux_65 mux_70 mux_40 + + + l4.E0 + mux_97 mux_71 mux_56 mux_94 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.W4 + mux_34 mux_68 mux_73 + + + l4.E4 + mux_66 mux_69 mux_72 + + + l4.S4 + mux_82 mux_85 mux_123 mux_76 + + + l4.W8 + mux_98 mux_103 mux_88 mux_93 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.S8 + mux_51 mux_116 mux_106 mux_109 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l4.S12 + mux_115 mux_118 mux_121 mux_124 + + + l8.W0 + mux_0 mux_5 mux_10 + + + l8.E0 + mux_32 mux_6 mux_9 + + + l8.S0 + mux_48 mux_22 mux_27 mux_13 + + + l8.W8 + mux_64 mux_7 mux_25 mux_30 + + + l8.E8 + mux_1 mux_4 mux_42 + + + l8.S8 + mux_17 mux_20 mux_43 mux_46 + + + l1.W9 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E9 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S9 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W10 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E10 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S10 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W11 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E11 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S11 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.W12 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E12 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S12 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + io_top_dspL.f2a_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.f2a_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.f2a_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.f2a_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.f2a_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.f2a_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.f2a_i[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.f2a_i[0] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.f2a_i[1] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.f2a_i[2] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.f2a_i[3] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_dspL.f2a_i[4] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_dspL.f2a_i[5] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_dspL.f2a_i[6] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_dspL.f2a_i[0] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_dspL.f2a_i[1] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_dspL.f2a_i[2] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_dspL.f2a_i[3] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_dspL.f2a_i[4] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_dspL.f2a_i[5] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_dspL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_dspL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_dspL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_dspL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_top_dspL.f2a_i[4] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_top_dspL.f2a_i[5] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_top_dspL.f2a_i[6] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.f2a_i[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_top_dspL.f2a_i[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_top_dspL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_top_dspL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_dspL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + io_top_dspL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + io_top_dspL.f2a_i[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + io_top_dspL.f2a_i[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 + + + io_top_dspL.f2a_i[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + io_top_dspL.f2a_i[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + io_top_dspL.f2a_i[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + io_top_dspL.f2a_i[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 + + + io_top_dspL.f2a_i[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.f2a_i[6] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.f2a_i[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.f2a_i[1] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 + + + io_top_dspL.f2a_i[2] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.f2a_i[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + io_top_dspL.f2a_i[4] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + io_top_dspL.f2a_i[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 + + + io_top_dspL.f2a_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + io_top_dspL.f2a_i[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + io_top_dspL.f2a_i[1] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + io_top_dspL.f2a_i[2] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 + + + io_top_dspL.f2a_i[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + io_top_dspL.f2a_i[4] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + io_top_dspL.f2a_i[5] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + io_top_dspL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 + + + io_top_dspL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + io_top_dspL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + io_top_dspL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + io_top_dspL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 + + + io_top_dspL.lclk[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lreset[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lclk[7] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lreset[7] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lclk[14] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lreset[14] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lclk[21] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lreset[21] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lclk[28] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lreset[28] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_dspL.lclk[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lreset[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lclk[8] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lreset[8] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lclk[15] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lreset[15] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lclk[22] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lreset[22] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lclk[29] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lreset[29] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_dspL.lclk[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lreset[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lclk[9] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lreset[9] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lclk[16] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lreset[16] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lclk[23] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lreset[23] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lclk[30] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lreset[30] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_dspL.lclk[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lreset[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lclk[10] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lreset[10] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lclk[17] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lreset[17] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lclk[24] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lreset[24] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lclk[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.lreset[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.lclk[11] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.lreset[11] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.lclk[18] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.lreset[18] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.lclk[25] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.lreset[25] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_dspL.lclk[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.lreset[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.lclk[12] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.lreset[12] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.lclk[19] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.lreset[19] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.lclk[26] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.lreset[26] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_dspL.lclk[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.lreset[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.lclk[13] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.lreset[13] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.lclk[20] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.lreset[20] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.lclk[27] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.lreset[27] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_dspL.lclk[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lreset[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lclk[14] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lreset[14] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lclk[21] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lreset[21] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lclk[28] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lreset[28] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lclk[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.lreset[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.lclk[15] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.lreset[15] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.lclk[22] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.lreset[22] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.lclk[29] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.lreset[29] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_dspL.lclk[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.lreset[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.lclk[16] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.lreset[16] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.lclk[23] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.lreset[23] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.lclk[30] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.lreset[30] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_dspL.lclk[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_dspL.lreset[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_dspL.lclk[17] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_dspL.lreset[17] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_dspL.lclk[24] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_dspL.lreset[24] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_dspL.lclk[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_dspL.lreset[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_dspL.lclk[18] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_dspL.lreset[18] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_dspL.lclk[25] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_dspL.lreset[25] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_dspL.lclk[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_dspL.lreset[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_dspL.lclk[19] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_dspL.lreset[19] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_dspL.lclk[26] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_dspL.lreset[26] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_dspL.lclk[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_dspL.lreset[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_dspL.lclk[20] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_dspL.lreset[20] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_dspL.lclk[27] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_dspL.lreset[27] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_dspL.lclk[14] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_dspL.lreset[14] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_dspL.lclk[21] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_dspL.lreset[21] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_dspL.lclk[28] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_dspL.lreset[28] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_dspL.lclk[15] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_dspL.lreset[15] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_dspL.lclk[22] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_dspL.lreset[22] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_dspL.lclk[29] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_dspL.lreset[29] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_dspL.lclk[16] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_dspL.lreset[16] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_dspL.lclk[23] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_dspL.lreset[23] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_dspL.lclk[30] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_dspL.lreset[30] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_dspL.lclk[17] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_dspL.lreset[17] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_dspL.lclk[24] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_dspL.lreset[24] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_dspL.lclk[18] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_dspL.lreset[18] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_dspL.lclk[25] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_dspL.lreset[25] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_dspL.lclk[19] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_dspL.lreset[19] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_dspL.lclk[26] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_dspL.lreset[26] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_dspL.lclk[20] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_dspL.lreset[20] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_dspL.lclk[27] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_dspL.lreset[27] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_dspL.lclk[21] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_dspL.lreset[21] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_dspL.lclk[28] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_dspL.lreset[28] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_dspL.lclk[22] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_dspL.lreset[22] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_dspL.lclk[29] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_dspL.lreset[29] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_dspL.lclk[23] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lreset[23] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lclk[30] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lreset[30] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_dspL.lclk[24] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_top_dspL.lreset[24] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_top_dspL.lclk[25] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_top_dspL.lreset[25] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_top_dspL.lclk[26] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_top_dspL.lreset[26] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_top_dspL.lclk[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lreset[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_dspL.lclk[28] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_top_dspL.lreset[28] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_top_dspL.lclk[29] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_top_dspL.lreset[29] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_top_dspL.lclk[30] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_top_dspL.lreset[30] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 io_top_ramL.a2f_o[8] + + + l1.W2 l2.W1 l4.W3 io_top_ramL.a2f_o[0] + + + l1.W3 l3.W5 l8.W7 io_top_ramL.a2f_o[16] + + + l1.W4 l3.W8 l8.W15 + + + l1.N5 l1.N6 l3.N11 io_top_ramL.a2f_o[9] + + + l1.N7 l2.N3 l4.N7 io_top_ramL.a2f_o[1] + + + l1.N8 l3.N14 l8.N7 io_top_ramL.a2f_o[17] + + + l1.N9 l3.N17 l8.N15 + + + l1.E10 l1.E11 l3.E20 io_top_ramL.a2f_o[10] + + + l1.E12 l2.E5 l4.E11 io_top_ramL.a2f_o[2] + + + l1.E0 l3.E23 l8.E7 io_top_ramL.a2f_o[18] + + + l1.E1 l3.E2 l8.E15 + + + io_top_ramL.a2f_o[11] + + + io_top_ramL.a2f_o[3] + + + io_top_ramL.a2f_o[19] + + + l1.W7 l1.W8 l3.W14 io_top_ramL.a2f_o[12] + + + l1.W9 l2.W3 l4.W3 io_top_ramL.a2f_o[4] + + + l1.W10 l3.W17 l8.W7 io_top_ramL.a2f_o[20] + + + l1.W11 l3.W20 l8.W15 + + + l1.N12 l1.N0 l3.N23 io_top_ramL.a2f_o[13] + + + l1.N1 l2.N5 l4.N7 io_top_ramL.a2f_o[5] + + + l1.N2 l3.N2 l8.N7 io_top_ramL.a2f_o[21] + + + l1.N3 l3.N5 l8.N15 + + + l1.E4 l1.E5 l3.E8 io_top_ramL.a2f_o[14] + + + l1.E6 l2.E1 l4.E11 io_top_ramL.a2f_o[6] + + + l1.E7 l3.E11 l8.E7 io_top_ramL.a2f_o[22] + + + l1.E8 l3.E14 l8.E15 + + + io_top_ramL.a2f_o[15] + + + io_top_ramL.a2f_o[7] + + + io_top_ramL.a2f_o[23] + + + l1.W1 l1.W2 l3.W2 io_top_ramL.a2f_o[8] + + + l1.W3 l2.W5 l4.W3 io_top_ramL.a2f_o[0] + + + l1.W4 l3.W5 l8.W7 io_top_ramL.a2f_o[16] + + + l1.W5 l3.W8 l8.W15 + + + l1.N6 l1.N7 l3.N11 io_top_ramL.a2f_o[9] + + + l1.N8 l2.N1 l4.N7 io_top_ramL.a2f_o[1] + + + l1.N9 l3.N14 l8.N7 io_top_ramL.a2f_o[17] + + + l1.N10 l3.N17 l8.N15 + + + l1.E11 l1.E12 l3.E20 io_top_ramL.a2f_o[10] + + + l1.E0 l2.E3 l4.E11 io_top_ramL.a2f_o[2] + + + l1.E1 l3.E23 l8.E7 io_top_ramL.a2f_o[18] + + + l1.E2 l3.E2 l8.E15 + + + io_top_ramL.a2f_o[11] + + + io_top_ramL.a2f_o[3] + + + io_top_ramL.a2f_o[19] + + + l1.W8 l1.W9 l3.W14 io_top_ramL.a2f_o[12] + + + l1.W10 l2.W1 l4.W3 io_top_ramL.a2f_o[4] + + + l1.W11 l3.W17 l8.W7 io_top_ramL.a2f_o[20] + + + l1.W12 l3.W20 l8.W15 + + + l1.N0 l1.N1 l3.N23 io_top_ramL.a2f_o[13] + + + l1.N2 l2.N3 l4.N7 io_top_ramL.a2f_o[5] + + + l1.N3 l3.N2 l8.N7 io_top_ramL.a2f_o[21] + + + l1.N4 l3.N5 l8.N15 + + + l1.E5 l1.E6 l3.E8 io_top_ramL.a2f_o[14] + + + l1.E7 l2.E5 l4.E11 io_top_ramL.a2f_o[6] + + + l1.E8 l3.E11 l8.E7 io_top_ramL.a2f_o[22] + + + l1.E9 l3.E14 l8.E15 + + + io_top_ramL.a2f_o[15] + + + io_top_ramL.a2f_o[7] + + + io_top_ramL.a2f_o[23] + + + l1.W2 l1.W3 l3.W2 io_top_ramL.a2f_o[8] + + + l1.W4 l2.W3 l4.W3 io_top_ramL.a2f_o[0] + + + l1.W5 l3.W5 l8.W7 io_top_ramL.a2f_o[16] + + + l1.W6 l3.W8 l8.W15 + + + l1.N7 l1.N8 l3.N11 io_top_ramL.a2f_o[9] + + + l1.N9 l2.N5 l4.N7 io_top_ramL.a2f_o[1] + + + l1.N10 l3.N14 l8.N7 io_top_ramL.a2f_o[17] + + + l1.N11 l3.N17 l8.N15 + + + l1.E12 l1.E0 l3.E20 io_top_ramL.a2f_o[10] + + + l1.E1 l2.E1 l4.E11 io_top_ramL.a2f_o[2] + + + l1.E2 l3.E23 l8.E7 io_top_ramL.a2f_o[18] + + + l1.E3 l3.E2 l8.E15 + + + io_top_ramL.a2f_o[11] + + + io_top_ramL.a2f_o[3] + + + io_top_ramL.a2f_o[19] + + + l1.W9 l1.W10 l3.W14 io_top_ramL.a2f_o[12] + + + l1.W11 l2.W5 l4.W3 io_top_ramL.a2f_o[4] + + + l1.W12 l3.W17 l8.W7 io_top_ramL.a2f_o[20] + + + l1.W0 l3.W20 l8.W15 + + + l1.N1 l1.N2 l3.N23 io_top_ramL.a2f_o[13] + + + l1.N3 l2.N1 l4.N7 io_top_ramL.a2f_o[5] + + + l1.N4 l3.N2 l8.N7 io_top_ramL.a2f_o[21] + + + l1.N5 l3.N5 l8.N15 + + + l1.E6 l1.E7 l3.E8 io_top_ramL.a2f_o[14] + + + l1.E8 l2.E3 l4.E11 io_top_ramL.a2f_o[6] + + + l1.E9 l3.E11 l8.E7 io_top_ramL.a2f_o[22] + + + l1.E10 l3.E14 l8.E15 + + + io_top_ramL.a2f_o[15] + + + io_top_ramL.a2f_o[7] + + + io_top_ramL.a2f_o[23] + + + l1.W3 l1.W4 l3.W2 io_top_ramL.a2f_o[8] + + + l1.W5 l2.W1 l4.W3 io_top_ramL.a2f_o[0] + + + l1.W6 l3.W5 l8.W7 io_top_ramL.a2f_o[16] + + + l1.W7 l3.W8 l8.W15 + + + l1.N8 l1.N9 l3.N11 io_top_ramL.a2f_o[9] + + + l1.N10 l2.N3 l4.N7 io_top_ramL.a2f_o[1] + + + l1.N11 l3.N14 l8.N7 io_top_ramL.a2f_o[17] + + + l1.N12 l3.N17 l8.N15 + + + l1.E0 l1.E1 l3.E20 io_top_ramL.a2f_o[10] + + + l1.E2 l2.E5 l4.E11 io_top_ramL.a2f_o[2] + + + l1.E3 l3.E23 l8.E7 io_top_ramL.a2f_o[18] + + + l1.E4 l3.E2 l8.E15 + + + io_top_ramL.a2f_o[11] + + + io_top_ramL.a2f_o[3] + + + io_top_ramL.a2f_o[19] + + + l1.W10 l1.W11 l3.W14 io_top_ramL.a2f_o[12] + + + l1.W12 l2.W3 l4.W3 io_top_ramL.a2f_o[4] + + + l1.W0 l3.W17 l8.W7 io_top_ramL.a2f_o[20] + + + l1.W1 l3.W20 l8.W15 + + + l1.N2 l1.N3 l3.N23 io_top_ramL.a2f_o[13] + + + l1.N4 l2.N5 l4.N7 io_top_ramL.a2f_o[5] + + + l1.N5 l3.N2 l8.N7 io_top_ramL.a2f_o[21] + + + l1.N6 l3.N5 l8.N15 + + + l1.E7 l1.E8 l3.E8 io_top_ramL.a2f_o[14] + + + l1.E9 l2.E1 l4.E11 io_top_ramL.a2f_o[6] + + + l1.E10 l3.E11 l8.E7 io_top_ramL.a2f_o[22] + + + l1.E11 l3.E14 l8.E15 + + + io_top_ramL.a2f_o[15] + + + io_top_ramL.a2f_o[7] + + + io_top_ramL.a2f_o[23] + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_top_ramL.a2f_o[0] OG_0 + + + l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 io_top_ramL.a2f_o[8] + + + l1.E5 l1.N4 l3.E8 l4.E3 io_top_ramL.a2f_o[16] + + + l1.W11 l1.N4 l3.W20 l3.N8 l4.W11 io_top_ramL.a2f_o[1] + + + l1.E4 l1.E3 l3.E5 l4.E15 io_top_ramL.a2f_o[9] + + + l1.W10 l2.W1 l3.W17 io_top_ramL.a2f_o[17] OG_2 l1.N2 + + + l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 io_top_ramL.a2f_o[2] OG_2 + + + l1.E9 l2.E5 l3.E14 l4.E7 io_top_ramL.a2f_o[10] OG_3 l1.N9 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_top_ramL.a2f_o[18] OG_4 + + + l1.W8 l1.E7 l2.W3 l3.W11 l4.W3 io_top_ramL.a2f_o[3] + + + l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 io_top_ramL.a2f_o[11] + + + l1.E7 l3.E8 l4.E15 io_top_ramL.a2f_o[19] + + + l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 io_top_ramL.a2f_o[4] + + + l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 io_top_ramL.a2f_o[12] OG_6 l1.E5 + + + l1.E12 l2.E1 l3.E14 io_top_ramL.a2f_o[20] OG_6 + + + l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 io_top_ramL.a2f_o[5] OG_7 l1.N0 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_top_ramL.a2f_o[13] OG_0 + + + l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 io_top_ramL.a2f_o[21] + + + l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 io_top_ramL.a2f_o[6] + + + l1.E3 l1.N9 l3.E20 l3.N8 l4.E3 io_top_ramL.a2f_o[14] + + + l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 io_top_ramL.a2f_o[22] + + + l1.E2 l2.E3 l3.E17 io_top_ramL.a2f_o[7] OG_2 l1.E0 + + + l1.W8 l2.W5 l3.W2 io_top_ramL.a2f_o[15] OG_2 l1.N10 + + + l1.W1 l2.W1 l3.W14 l4.W15 io_top_ramL.a2f_o[23] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_top_ramL.a2f_o[0] OG_4 + + + l1.E0 l1.E12 l2.E5 l3.E11 l4.E11 io_top_ramL.a2f_o[8] + + + l1.W6 l1.N5 l3.W20 l4.W15 io_top_ramL.a2f_o[16] + + + l1.W12 l3.W8 l4.W7 io_top_ramL.a2f_o[1] + + + l1.W5 l1.E4 l3.W17 l4.W11 io_top_ramL.a2f_o[9] + + + l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 io_top_ramL.a2f_o[17] OG_6 l1.W6 + + + l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 io_top_ramL.a2f_o[2] OG_6 + + + l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 io_top_ramL.a2f_o[10] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_top_ramL.a2f_o[18] OG_0 + + + l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 io_top_ramL.a2f_o[3] + + + l1.E2 l1.N1 l3.E8 l4.E3 io_top_ramL.a2f_o[11] + + + l1.W8 l1.N1 l3.W20 l3.N8 l4.W11 io_top_ramL.a2f_o[19] + + + l1.E1 l1.E0 l3.E5 l4.E15 io_top_ramL.a2f_o[4] + + + l1.W7 l2.W5 l3.W17 io_top_ramL.a2f_o[12] OG_2 + + + l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 io_top_ramL.a2f_o[20] OG_2 l1.E0 + + + l1.E6 l2.E3 l3.E14 l4.E7 io_top_ramL.a2f_o[5] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_top_ramL.a2f_o[13] OG_4 + + + l1.W5 l1.E4 l2.W1 l3.W11 l4.W3 io_top_ramL.a2f_o[21] + + + l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 io_top_ramL.a2f_o[6] + + + l1.E4 l3.E8 l4.E15 io_top_ramL.a2f_o[14] + + + l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 io_top_ramL.a2f_o[22] + + + l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 io_top_ramL.a2f_o[7] OG_6 l1.E2 + + + l1.E9 l2.E5 l3.E14 io_top_ramL.a2f_o[15] OG_6 l1.W3 + + + l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 io_top_ramL.a2f_o[23] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_top_ramL.a2f_o[0] OG_0 + + + l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 io_top_ramL.a2f_o[8] + + + l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 io_top_ramL.a2f_o[16] + + + l1.E0 l1.N6 l3.E20 l3.N8 l4.E3 io_top_ramL.a2f_o[1] + + + l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 io_top_ramL.a2f_o[9] + + + l1.E12 l2.E1 l3.E17 io_top_ramL.a2f_o[17] OG_2 l1.W12 + + + l1.W5 l2.W3 l3.W2 io_top_ramL.a2f_o[2] OG_2 l1.W4 + + + l1.W11 l2.W5 l3.W14 l4.W15 io_top_ramL.a2f_o[10] OG_3 l1.N10 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_top_ramL.a2f_o[18] OG_4 + + + l1.E10 l1.E9 l2.E3 l3.E11 l4.E11 io_top_ramL.a2f_o[3] + + + l1.W3 l1.N2 l3.W20 l4.W15 io_top_ramL.a2f_o[11] + + + l1.W9 l3.W8 l4.W7 io_top_ramL.a2f_o[19] + + + io_top_ramL.a2f_o[17] io_top_ramL.a2f_o[0] io_top_ramL.a2f_o[8] io_top_ramL.a2f_o[9] + + + io_top_ramL.a2f_o[17] io_top_ramL.a2f_o[0] io_top_ramL.a2f_o[1] io_top_ramL.a2f_o[8] + + + io_top_ramL.a2f_o[16] io_top_ramL.a2f_o[0] io_top_ramL.a2f_o[1] io_top_ramL.a2f_o[9] + + + io_top_ramL.a2f_o[16] io_top_ramL.a2f_o[1] io_top_ramL.a2f_o[8] io_top_ramL.a2f_o[9] + + + io_top_ramL.a2f_o[19] io_top_ramL.a2f_o[2] io_top_ramL.a2f_o[10] io_top_ramL.a2f_o[11] + + + io_top_ramL.a2f_o[19] io_top_ramL.a2f_o[2] io_top_ramL.a2f_o[3] io_top_ramL.a2f_o[10] + + + io_top_ramL.a2f_o[18] io_top_ramL.a2f_o[2] io_top_ramL.a2f_o[3] io_top_ramL.a2f_o[11] + + + io_top_ramL.a2f_o[18] io_top_ramL.a2f_o[3] io_top_ramL.a2f_o[10] io_top_ramL.a2f_o[11] + + + io_top_ramL.a2f_o[21] io_top_ramL.a2f_o[4] io_top_ramL.a2f_o[12] io_top_ramL.a2f_o[13] + + + io_top_ramL.a2f_o[21] io_top_ramL.a2f_o[4] io_top_ramL.a2f_o[5] io_top_ramL.a2f_o[12] + + + io_top_ramL.a2f_o[20] io_top_ramL.a2f_o[4] io_top_ramL.a2f_o[5] io_top_ramL.a2f_o[13] + + + io_top_ramL.a2f_o[20] io_top_ramL.a2f_o[5] io_top_ramL.a2f_o[12] io_top_ramL.a2f_o[13] + + + io_top_ramL.a2f_o[23] io_top_ramL.a2f_o[6] io_top_ramL.a2f_o[14] io_top_ramL.a2f_o[15] + + + io_top_ramL.a2f_o[23] io_top_ramL.a2f_o[6] io_top_ramL.a2f_o[7] io_top_ramL.a2f_o[14] + + + io_top_ramL.a2f_o[22] io_top_ramL.a2f_o[6] io_top_ramL.a2f_o[7] io_top_ramL.a2f_o[15] + + + io_top_ramL.a2f_o[22] io_top_ramL.a2f_o[7] io_top_ramL.a2f_o[14] io_top_ramL.a2f_o[15] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 + + + l1.E0 + mux_32 mux_6 mux_9 + + + l1.S0 + mux_48 mux_22 mux_27 mux_13 + + + l1.W1 + mux_64 mux_7 mux_25 mux_30 + + + l1.E1 + mux_1 mux_4 mux_42 + + + l1.S1 + mux_17 mux_20 mux_43 mux_46 + + + l1.W2 + mux_33 mux_38 mux_8 + + + l1.E2 + mux_65 mux_39 mux_24 mux_62 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.W3 + mux_2 mux_36 mux_41 + + + l1.E3 + mux_34 mux_37 mux_40 + + + l1.S3 + mux_50 mux_53 mux_91 mux_44 + + + l1.W4 + mux_66 mux_71 mux_56 mux_61 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.S4 + mux_19 mux_84 mux_74 mux_77 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.S5 + mux_83 mux_86 mux_89 mux_92 + + + l1.W6 + mux_96 mux_101 mux_106 + + + l1.E6 + mux_0 mux_102 mux_105 + + + l1.S6 + mux_16 mux_118 mux_123 mux_109 + + + l1.W7 + mux_32 mux_103 mux_121 mux_126 + + + l1.E7 + mux_97 mux_100 mux_10 + + + l1.S7 + mux_113 mux_116 mux_11 mux_14 + + + l1.W8 + mux_1 mux_6 mux_104 + + + l1.E8 + mux_33 mux_7 mux_120 mux_30 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.W0 + mux_98 mux_4 mux_9 + + + l2.E0 + mux_2 mux_5 mux_8 + + + l2.S0 + mux_18 mux_21 mux_59 mux_12 + + + l2.W2 + mux_34 mux_39 mux_24 mux_29 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.S2 + mux_115 mux_52 mux_42 mux_45 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l2.S4 + mux_51 mux_54 mux_57 mux_60 + + + l3.W0 + mux_64 mux_69 mux_74 + + + l3.E0 + mux_96 mux_70 mux_73 + + + l3.S0 + mux_112 mux_86 mux_91 mux_77 + + + l3.W3 + mux_0 mux_71 mux_89 mux_94 + + + l3.E3 + mux_65 mux_68 mux_106 + + + l3.S3 + mux_81 mux_84 mux_107 mux_110 + + + l3.W6 + mux_97 mux_102 mux_72 + + + l3.E6 + mux_1 mux_103 mux_88 mux_126 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.W9 + mux_66 mux_100 mux_105 + + + l3.E9 + mux_98 mux_101 mux_104 + + + l3.S9 + mux_114 mux_117 mux_27 mux_108 + + + l3.W12 + mux_2 mux_7 mux_120 mux_125 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.S12 + mux_83 mux_20 mux_10 mux_13 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.S15 + mux_19 mux_22 mux_25 mux_28 + + + l3.W18 + mux_32 mux_37 mux_42 + + + l3.E18 + mux_64 mux_38 mux_41 + + + l3.S18 + mux_80 mux_54 mux_59 mux_45 + + + l3.W21 + mux_96 mux_39 mux_57 mux_62 + + + l3.E21 + mux_33 mux_36 mux_74 + + + l3.S21 + mux_49 mux_52 mux_75 mux_78 + + + l4.W0 + mux_65 mux_70 mux_40 + + + l4.E0 + mux_97 mux_71 mux_56 mux_94 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.W4 + mux_34 mux_68 mux_73 + + + l4.E4 + mux_66 mux_69 mux_72 + + + l4.S4 + mux_82 mux_85 mux_123 mux_76 + + + l4.W8 + mux_98 mux_103 mux_88 mux_93 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.S8 + mux_51 mux_116 mux_106 mux_109 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l4.S12 + mux_115 mux_118 mux_121 mux_124 + + + l8.W0 + mux_0 mux_5 mux_10 + + + l8.E0 + mux_32 mux_6 mux_9 + + + l8.S0 + mux_48 mux_22 mux_27 mux_13 + + + l8.W8 + mux_64 mux_7 mux_25 mux_30 + + + l8.E8 + mux_1 mux_4 mux_42 + + + l8.S8 + mux_17 mux_20 mux_43 mux_46 + + + l1.W9 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E9 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S9 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W10 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E10 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S10 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W11 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E11 + OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S11 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.W12 + OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E12 + OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S12 + OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + io_top_ramL.f2a_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.f2a_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.f2a_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.f2a_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.f2a_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.f2a_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.f2a_i[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.f2a_i[0] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.f2a_i[1] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.f2a_i[2] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.f2a_i[3] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_ramL.f2a_i[4] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_ramL.f2a_i[5] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_ramL.f2a_i[6] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_ramL.f2a_i[0] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_ramL.f2a_i[1] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_ramL.f2a_i[2] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_ramL.f2a_i[3] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_ramL.f2a_i[4] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_ramL.f2a_i[5] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_ramL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_ramL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_ramL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_ramL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_top_ramL.f2a_i[4] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_top_ramL.f2a_i[5] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_top_ramL.f2a_i[6] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.f2a_i[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_top_ramL.f2a_i[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_top_ramL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_top_ramL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_ramL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + io_top_ramL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + io_top_ramL.f2a_i[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + io_top_ramL.f2a_i[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 + + + io_top_ramL.f2a_i[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + io_top_ramL.f2a_i[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + io_top_ramL.f2a_i[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + io_top_ramL.f2a_i[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 + + + io_top_ramL.f2a_i[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.f2a_i[6] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.f2a_i[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.f2a_i[1] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 + + + io_top_ramL.f2a_i[2] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.f2a_i[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + io_top_ramL.f2a_i[4] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + io_top_ramL.f2a_i[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 + + + io_top_ramL.f2a_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + io_top_ramL.f2a_i[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + io_top_ramL.f2a_i[1] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + io_top_ramL.f2a_i[2] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 + + + io_top_ramL.f2a_i[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + io_top_ramL.f2a_i[4] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + io_top_ramL.f2a_i[5] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + io_top_ramL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 + + + io_top_ramL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + io_top_ramL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + io_top_ramL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + io_top_ramL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 + + + io_top_ramL.lclk[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lreset[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lclk[7] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lreset[7] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lclk[14] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lreset[14] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lclk[21] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lreset[21] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lclk[28] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lreset[28] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_top_ramL.lclk[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lreset[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lclk[8] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lreset[8] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lclk[15] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lreset[15] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lclk[22] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lreset[22] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lclk[29] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lreset[29] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + io_top_ramL.lclk[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lreset[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lclk[9] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lreset[9] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lclk[16] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lreset[16] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lclk[23] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lreset[23] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lclk[30] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lreset[30] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_top_ramL.lclk[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lreset[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lclk[10] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lreset[10] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lclk[17] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lreset[17] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lclk[24] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lreset[24] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lclk[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.lreset[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.lclk[11] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.lreset[11] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.lclk[18] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.lreset[18] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.lclk[25] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.lreset[25] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_top_ramL.lclk[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.lreset[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.lclk[12] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.lreset[12] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.lclk[19] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.lreset[19] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.lclk[26] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.lreset[26] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + io_top_ramL.lclk[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.lreset[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.lclk[13] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.lreset[13] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.lclk[20] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.lreset[20] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.lclk[27] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.lreset[27] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_top_ramL.lclk[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lreset[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lclk[14] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lreset[14] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lclk[21] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lreset[21] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lclk[28] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lreset[28] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lclk[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.lreset[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.lclk[15] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.lreset[15] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.lclk[22] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.lreset[22] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.lclk[29] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.lreset[29] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_top_ramL.lclk[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.lreset[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.lclk[16] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.lreset[16] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.lclk[23] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.lreset[23] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.lclk[30] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.lreset[30] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + io_top_ramL.lclk[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_ramL.lreset[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_ramL.lclk[17] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_ramL.lreset[17] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_ramL.lclk[24] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_ramL.lreset[24] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_top_ramL.lclk[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_ramL.lreset[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_ramL.lclk[18] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_ramL.lreset[18] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_ramL.lclk[25] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_ramL.lreset[25] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top_ramL.lclk[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_ramL.lreset[12] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_ramL.lclk[19] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_ramL.lreset[19] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_ramL.lclk[26] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_ramL.lreset[26] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_top_ramL.lclk[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_ramL.lreset[13] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_ramL.lclk[20] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_ramL.lreset[20] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_ramL.lclk[27] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_ramL.lreset[27] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + io_top_ramL.lclk[14] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_ramL.lreset[14] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_ramL.lclk[21] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_ramL.lreset[21] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_ramL.lclk[28] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_ramL.lreset[28] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_top_ramL.lclk[15] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_ramL.lreset[15] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_ramL.lclk[22] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_ramL.lreset[22] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_ramL.lclk[29] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_ramL.lreset[29] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_top_ramL.lclk[16] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_ramL.lreset[16] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_ramL.lclk[23] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_ramL.lreset[23] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_ramL.lclk[30] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_ramL.lreset[30] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_top_ramL.lclk[17] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_ramL.lreset[17] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_ramL.lclk[24] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_ramL.lreset[24] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + io_top_ramL.lclk[18] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_ramL.lreset[18] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_ramL.lclk[25] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_ramL.lreset[25] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_top_ramL.lclk[19] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_ramL.lreset[19] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_ramL.lclk[26] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_ramL.lreset[26] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_top_ramL.lclk[20] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_ramL.lreset[20] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_ramL.lclk[27] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_ramL.lreset[27] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_top_ramL.lclk[21] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_ramL.lreset[21] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_ramL.lclk[28] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_ramL.lreset[28] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + io_top_ramL.lclk[22] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_ramL.lreset[22] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_ramL.lclk[29] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_ramL.lreset[29] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_top_ramL.lclk[23] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lreset[23] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lclk[30] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lreset[30] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top_ramL.lclk[24] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_top_ramL.lreset[24] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_top_ramL.lclk[25] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_top_ramL.lreset[25] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + io_top_ramL.lclk[26] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_top_ramL.lreset[26] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_top_ramL.lclk[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lreset[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_top_ramL.lclk[28] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_top_ramL.lreset[28] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_top_ramL.lclk[29] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_top_ramL.lreset[29] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + io_top_ramL.lclk[30] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_top_ramL.lreset[30] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 io_bottomL.a2f_o[0] + + + l1.W2 l2.W1 l4.W3 io_bottomL.a2f_o[0] + + + l1.W3 l3.W5 l8.W7 io_bottomL.a2f_o[0] + + + l1.W4 l3.W8 l8.W15 + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + l1.E10 l1.E11 l3.E20 io_bottomL.a2f_o[2] + + + l1.E12 l2.E5 l4.E11 io_bottomL.a2f_o[2] + + + l1.E0 l3.E23 l8.E7 io_bottomL.a2f_o[2] + + + l1.E1 l3.E2 l8.E15 + + + l1.S2 l1.S3 l3.S5 io_bottomL.a2f_o[3] + + + l1.S4 l2.S1 l4.S15 io_bottomL.a2f_o[3] + + + l1.S5 l3.S8 l8.S7 io_bottomL.a2f_o[3] + + + l1.S6 l3.S11 l8.S15 + + + l1.W7 l1.W8 l3.W14 io_bottomL.a2f_o[0] + + + l1.W9 l2.W3 l4.W3 io_bottomL.a2f_o[0] + + + l1.W10 l3.W17 l8.W7 io_bottomL.a2f_o[0] + + + l1.W11 l3.W20 l8.W15 + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + l1.E4 l1.E5 l3.E8 io_bottomL.a2f_o[2] + + + l1.E6 l2.E1 l4.E11 io_bottomL.a2f_o[2] + + + l1.E7 l3.E11 l8.E7 io_bottomL.a2f_o[2] + + + l1.E8 l3.E14 l8.E15 + + + l1.S9 l1.S10 l3.S17 io_bottomL.a2f_o[3] + + + l1.S11 l2.S3 l4.S15 io_bottomL.a2f_o[3] + + + l1.S12 l3.S20 l8.S7 io_bottomL.a2f_o[3] + + + l1.S0 l3.S23 l8.S15 + + + l1.W1 l1.W2 l3.W2 io_bottomL.a2f_o[0] + + + l1.W3 l2.W5 l4.W3 io_bottomL.a2f_o[0] + + + l1.W4 l3.W5 l8.W7 io_bottomL.a2f_o[0] + + + l1.W5 l3.W8 l8.W15 + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + l1.E11 l1.E12 l3.E20 io_bottomL.a2f_o[2] + + + l1.E0 l2.E3 l4.E11 io_bottomL.a2f_o[2] + + + l1.E1 l3.E23 l8.E7 io_bottomL.a2f_o[2] + + + l1.E2 l3.E2 l8.E15 + + + l1.S3 l1.S4 l3.S5 io_bottomL.a2f_o[3] + + + l1.S5 l2.S5 l4.S15 io_bottomL.a2f_o[3] + + + l1.S6 l3.S8 l8.S7 io_bottomL.a2f_o[3] + + + l1.S7 l3.S11 l8.S15 + + + l1.W8 l1.W9 l3.W14 io_bottomL.a2f_o[0] + + + l1.W10 l2.W1 l4.W3 io_bottomL.a2f_o[0] + + + l1.W11 l3.W17 l8.W7 io_bottomL.a2f_o[0] + + + l1.W12 l3.W20 l8.W15 + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + l1.E5 l1.E6 l3.E8 io_bottomL.a2f_o[2] + + + l1.E7 l2.E5 l4.E11 io_bottomL.a2f_o[2] + + + l1.E8 l3.E11 l8.E7 io_bottomL.a2f_o[2] + + + l1.E9 l3.E14 l8.E15 + + + l1.S10 l1.S11 l3.S17 io_bottomL.a2f_o[3] + + + l1.S12 l2.S1 l4.S15 io_bottomL.a2f_o[3] + + + l1.S0 l3.S20 l8.S7 io_bottomL.a2f_o[3] + + + l1.S1 l3.S23 l8.S15 + + + l1.W2 l1.W3 l3.W2 io_bottomL.a2f_o[0] + + + l1.W4 l2.W3 l4.W3 io_bottomL.a2f_o[0] + + + l1.W5 l3.W5 l8.W7 io_bottomL.a2f_o[0] + + + l1.W6 l3.W8 l8.W15 + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + l1.E12 l1.E0 l3.E20 io_bottomL.a2f_o[2] + + + l1.E1 l2.E1 l4.E11 io_bottomL.a2f_o[2] + + + l1.E2 l3.E23 l8.E7 io_bottomL.a2f_o[2] + + + l1.E3 l3.E2 l8.E15 + + + l1.S4 l1.S5 l3.S5 io_bottomL.a2f_o[3] + + + l1.S6 l2.S3 l4.S15 io_bottomL.a2f_o[3] + + + l1.S7 l3.S8 l8.S7 io_bottomL.a2f_o[3] + + + l1.S8 l3.S11 l8.S15 + + + l1.W9 l1.W10 l3.W14 io_bottomL.a2f_o[0] + + + l1.W11 l2.W5 l4.W3 io_bottomL.a2f_o[0] + + + l1.W12 l3.W17 l8.W7 io_bottomL.a2f_o[0] + + + l1.W0 l3.W20 l8.W15 + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + l1.E6 l1.E7 l3.E8 io_bottomL.a2f_o[2] + + + l1.E8 l2.E3 l4.E11 io_bottomL.a2f_o[2] + + + l1.E9 l3.E11 l8.E7 io_bottomL.a2f_o[2] + + + l1.E10 l3.E14 l8.E15 + + + l1.S11 l1.S12 l3.S17 io_bottomL.a2f_o[3] + + + l1.S0 l2.S5 l4.S15 io_bottomL.a2f_o[3] + + + l1.S1 l3.S20 l8.S7 io_bottomL.a2f_o[3] + + + l1.S2 l3.S23 l8.S15 + + + l1.W3 l1.W4 l3.W2 io_bottomL.a2f_o[0] + + + l1.W5 l2.W1 l4.W3 io_bottomL.a2f_o[0] + + + l1.W6 l3.W5 l8.W7 io_bottomL.a2f_o[0] + + + l1.W7 l3.W8 l8.W15 + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + l1.E0 l1.E1 l3.E20 io_bottomL.a2f_o[2] + + + l1.E2 l2.E5 l4.E11 io_bottomL.a2f_o[2] + + + l1.E3 l3.E23 l8.E7 io_bottomL.a2f_o[2] + + + l1.E4 l3.E2 l8.E15 + + + l1.S5 l1.S6 l3.S5 io_bottomL.a2f_o[3] + + + l1.S7 l2.S1 l4.S15 io_bottomL.a2f_o[3] + + + l1.S8 l3.S8 l8.S7 io_bottomL.a2f_o[3] + + + l1.S9 l3.S11 l8.S15 + + + l1.W10 l1.W11 l3.W14 io_bottomL.a2f_o[0] + + + l1.W12 l2.W3 l4.W3 io_bottomL.a2f_o[0] + + + l1.W0 l3.W17 l8.W7 io_bottomL.a2f_o[0] + + + l1.W1 l3.W20 l8.W15 + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] + + + l1.E7 l1.E8 l3.E8 io_bottomL.a2f_o[2] + + + l1.E9 l2.E1 l4.E11 io_bottomL.a2f_o[2] + + + l1.E10 l3.E11 l8.E7 io_bottomL.a2f_o[2] + + + l1.E11 l3.E14 l8.E15 + + + l1.S12 l1.S0 l3.S17 io_bottomL.a2f_o[3] + + + l1.S1 l2.S3 l4.S15 io_bottomL.a2f_o[3] + + + l1.S2 l3.S20 l8.S7 io_bottomL.a2f_o[3] + + + l1.S3 l3.S23 l8.S15 + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_bottomL.a2f_o[0] OG_0 + + + l1.E12 l1.E11 l2.E5 l3.E23 l4.E15 io_bottomL.a2f_o[0] + + + l1.E5 l1.S11 l3.E8 l3.S17 l4.E3 io_bottomL.a2f_o[0] + + + l1.W11 l1.S10 l3.W20 l4.W11 io_bottomL.a2f_o[1] + + + l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 io_bottomL.a2f_o[1] + + + l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 io_bottomL.a2f_o[1] OG_2 + + + l1.W3 l2.W3 l3.W2 io_bottomL.a2f_o[2] OG_2 l1.S4 + + + l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 io_bottomL.a2f_o[2] OG_3 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_bottomL.a2f_o[2] OG_4 + + + l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 io_bottomL.a2f_o[3] + + + l1.W1 l3.W20 l4.W7 io_bottomL.a2f_o[3] + + + l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 io_bottomL.a2f_o[3] + + + l1.W0 l1.E12 l3.W17 l4.W3 io_bottomL.a2f_o[0] + + + l1.E6 l2.E5 l3.E5 io_bottomL.a2f_o[0] OG_6 l1.E5 + + + l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 io_bottomL.a2f_o[0] OG_6 l1.S4 + + + l1.W5 l2.W3 l3.W2 l4.W11 io_bottomL.a2f_o[1] OG_7 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_bottomL.a2f_o[1] OG_0 + + + l1.W4 l1.E3 l2.W1 l3.W23 l4.W7 io_bottomL.a2f_o[1] + + + l1.E10 l3.E8 l4.E11 io_bottomL.a2f_o[2] + + + l1.E3 l1.S2 l3.E20 l4.E3 io_bottomL.a2f_o[2] + + + l1.E9 l1.E8 l3.E5 l4.E7 io_bottomL.a2f_o[2] + + + l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 io_bottomL.a2f_o[3] OG_2 l1.E0 + + + l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 io_bottomL.a2f_o[3] OG_2 + + + l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 io_bottomL.a2f_o[3] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_bottomL.a2f_o[0] OG_4 + + + l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 io_bottomL.a2f_o[0] + + + l1.W6 l1.S12 l3.W20 l3.S5 l4.W15 io_bottomL.a2f_o[0] + + + l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 io_bottomL.a2f_o[1] + + + l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 io_bottomL.a2f_o[1] + + + l1.W11 l2.W1 l3.W5 io_bottomL.a2f_o[1] OG_6 l1.W6 + + + l1.E4 l2.E3 l3.E14 io_bottomL.a2f_o[2] OG_6 l1.S8 + + + l1.E10 l2.E5 l3.E2 l4.E3 io_bottomL.a2f_o[2] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_bottomL.a2f_o[2] OG_0 + + + l1.E9 l1.E8 l2.E3 l3.E23 l4.E15 io_bottomL.a2f_o[3] + + + l1.E2 l1.S8 l3.E8 l3.S17 l4.E3 io_bottomL.a2f_o[3] + + + l1.W8 l1.S7 l3.W20 l4.W11 io_bottomL.a2f_o[3] + + + l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 io_bottomL.a2f_o[0] + + + l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 io_bottomL.a2f_o[0] OG_2 l1.S6 + + + l1.W0 l2.W1 l3.W2 io_bottomL.a2f_o[0] OG_2 l1.E0 + + + l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 io_bottomL.a2f_o[1] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_bottomL.a2f_o[1] OG_4 + + + l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 io_bottomL.a2f_o[1] + + + l1.W11 l3.W20 l4.W7 io_bottomL.a2f_o[2] + + + l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 io_bottomL.a2f_o[2] + + + l1.W10 l1.E9 l3.W17 l4.W3 io_bottomL.a2f_o[2] + + + l1.E3 l2.E3 l3.E5 io_bottomL.a2f_o[3] OG_6 l1.E2 + + + l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 io_bottomL.a2f_o[3] OG_6 l1.W3 + + + l1.W2 l2.W1 l3.W2 l4.W11 io_bottomL.a2f_o[3] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_bottomL.a2f_o[0] OG_0 + + + l1.W1 l1.E0 l2.W5 l3.W23 l4.W7 io_bottomL.a2f_o[0] + + + l1.E7 l3.E8 l4.E11 io_bottomL.a2f_o[0] + + + l1.E0 l1.S12 l3.E20 l4.E3 io_bottomL.a2f_o[1] + + + l1.E6 l1.E5 l3.E5 l4.E7 io_bottomL.a2f_o[1] + + + l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 io_bottomL.a2f_o[1] OG_2 l1.W12 + + + l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 io_bottomL.a2f_o[2] OG_2 l1.W4 + + + l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 io_bottomL.a2f_o[2] OG_3 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_bottomL.a2f_o[2] OG_4 + + + l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 io_bottomL.a2f_o[3] + + + l1.W3 l1.S9 l3.W20 l3.S5 l4.W15 io_bottomL.a2f_o[3] + + + l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 io_bottomL.a2f_o[3] + + + io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] + + + io_bottomL.a2f_o[0] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] + + + io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] + + + io_bottomL.a2f_o[2] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[3] + + + io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] + + + io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] + + + io_bottomL.a2f_o[0] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] + + + io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] + + + io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] + + + io_bottomL.a2f_o[2] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[3] + + + io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 mux_15 + + + l1.N0 + mux_16 mux_21 mux_11 mux_14 + + + l1.E0 + mux_32 mux_6 mux_9 mux_31 + + + l1.W1 + mux_64 mux_25 mux_30 + + + l1.N1 + mux_80 mux_26 mux_29 + + + l1.E1 + mux_1 mux_4 mux_42 mux_47 + + + l1.W2 + mux_33 mux_38 mux_8 mux_63 + + + l1.N2 + mux_49 mux_54 mux_59 mux_12 + + + l1.E2 + mux_65 mux_24 mux_62 + + + l1.W3 + mux_2 mux_36 mux_41 mux_79 + + + l1.N3 + mux_18 mux_52 mux_75 mux_45 + + + l1.E3 + mux_34 mux_37 mux_40 mux_95 + + + l1.W4 + mux_66 mux_56 mux_61 + + + l1.N4 + mux_82 mux_57 mux_60 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.N5 + mux_51 mux_85 mux_90 mux_76 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.W6 + mux_96 mux_101 mux_106 mux_111 + + + l1.N6 + mux_112 mux_117 mux_107 mux_110 + + + l1.E6 + mux_0 mux_102 mux_105 mux_127 + + + l1.W7 + mux_32 mux_121 mux_126 + + + l1.N7 + mux_48 mux_122 mux_125 + + + l1.E7 + mux_97 mux_100 mux_10 mux_15 + + + l1.W8 + mux_1 mux_6 mux_104 mux_31 + + + l1.N8 + mux_17 mux_22 mux_27 mux_108 + + + l1.E8 + mux_33 mux_120 mux_30 + + + l2.W0 + mux_98 mux_4 mux_9 mux_47 + + + l2.N0 + mux_114 mux_20 mux_43 mux_13 + + + l2.E0 + mux_2 mux_5 mux_8 mux_63 + + + l2.W2 + mux_34 mux_24 mux_29 + + + l2.N2 + mux_50 mux_25 mux_28 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.N4 + mux_19 mux_53 mux_58 mux_44 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l3.W0 + mux_64 mux_69 mux_74 mux_79 + + + l3.N0 + mux_80 mux_85 mux_75 mux_78 + + + l3.E0 + mux_96 mux_70 mux_73 mux_95 + + + l3.W3 + mux_0 mux_89 mux_94 + + + l3.N3 + mux_16 mux_90 mux_93 + + + l3.E3 + mux_65 mux_68 mux_106 mux_111 + + + l3.W6 + mux_97 mux_102 mux_72 mux_127 + + + l3.N6 + mux_113 mux_118 mux_123 mux_76 + + + l3.E6 + mux_1 mux_88 mux_126 + + + l3.W9 + mux_66 mux_100 mux_105 mux_15 + + + l3.N9 + mux_82 mux_116 mux_11 mux_109 + + + l3.E9 + mux_98 mux_101 mux_104 mux_31 + + + l3.W12 + mux_2 mux_120 mux_125 + + + l3.N12 + mux_18 mux_121 mux_124 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.N15 + mux_115 mux_21 mux_26 mux_12 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.W18 + mux_32 mux_37 mux_42 mux_47 + + + l3.N18 + mux_48 mux_53 mux_43 mux_46 + + + l3.E18 + mux_64 mux_38 mux_41 mux_63 + + + l3.W21 + mux_96 mux_57 mux_62 + + + l3.N21 + mux_112 mux_58 mux_61 + + + l3.E21 + mux_33 mux_36 mux_74 mux_79 + + + l4.W0 + mux_65 mux_70 mux_40 mux_95 + + + l4.N0 + mux_81 mux_86 mux_91 mux_44 + + + l4.E0 + mux_97 mux_56 mux_94 + + + l4.W4 + mux_34 mux_68 mux_73 mux_111 + + + l4.N4 + mux_50 mux_84 mux_107 mux_77 + + + l4.E4 + mux_66 mux_69 mux_72 mux_127 + + + l4.W8 + mux_98 mux_88 mux_93 + + + l4.N8 + mux_114 mux_89 mux_92 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.N12 + mux_83 mux_117 mux_122 mux_108 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l8.W0 + mux_0 mux_5 mux_10 mux_15 + + + l8.N0 + mux_16 mux_21 mux_11 mux_14 + + + l8.E0 + mux_32 mux_6 mux_9 mux_31 + + + l8.W8 + mux_64 mux_25 mux_30 + + + l8.N8 + mux_80 mux_26 mux_29 + + + l8.E8 + mux_1 mux_4 mux_42 mux_47 + + + l1.W9 + l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N9 + l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E9 + l1.W9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.W10 + l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N10 + l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E10 + l1.W10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W11 + l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.N11 + l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E11 + l1.W11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W12 + l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N12 + l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E12 + l1.W12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + io_bottomL.f2a_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottomL.f2a_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottomL.f2a_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottomL.f2a_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottomL.f2a_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottomL.f2a_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottomL.f2a_i[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottomL.f2a_i[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottomL.f2a_i[0] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottomL.f2a_i[1] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottomL.f2a_i[2] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottomL.f2a_i[3] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_bottomL.f2a_i[4] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_bottomL.f2a_i[5] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_bottomL.f2a_i[6] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_bottomL.f2a_i[7] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + io_bottomL.f2a_i[0] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_bottomL.f2a_i[1] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_bottomL.f2a_i[2] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_bottomL.f2a_i[3] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + io_bottomL.f2a_i[4] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_bottomL.f2a_i[5] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottomL.f2a_i[6] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_bottomL.f2a_i[7] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + io_bottomL.f2a_i[0] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_bottomL.f2a_i[1] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottomL.f2a_i[2] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_bottomL.f2a_i[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + io_bottomL.f2a_i[4] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_bottomL.f2a_i[5] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottomL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_bottomL.f2a_i[7] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + io_bottomL.f2a_i[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + io_bottomL.f2a_i[1] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_bottomL.f2a_i[2] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + io_bottomL.f2a_i[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + io_bottomL.f2a_i[4] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + io_bottomL.f2a_i[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 + + + io_bottomL.f2a_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + io_bottomL.f2a_i[7] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + io_bottomL.f2a_i[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + io_bottomL.f2a_i[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 + + + io_bottomL.f2a_i[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + io_bottomL.f2a_i[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + io_bottomL.f2a_i[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + io_bottomL.f2a_i[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 + + + io_bottomL.f2a_i[6] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + io_bottomL.f2a_i[7] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + io_bottomL.f2a_i[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + io_bottomL.f2a_i[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 + + + io_bottomL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + io_bottomL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + io_bottomL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + io_bottomL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 + + + io_bottomL.f2a_i[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + io_bottomL.f2a_i[7] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + io_bottomL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + io_bottomL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 + + + io_bottomL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + io_bottomL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + io_bottomL.lclk[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottomL.lreset[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottomL.lclk[8] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottomL.lreset[8] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottomL.lclk[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottomL.lreset[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottomL.lclk[9] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottomL.lreset[9] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottomL.lclk[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottomL.lreset[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottomL.lclk[10] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottomL.lreset[10] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottomL.lclk[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottomL.lreset[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottomL.lclk[11] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottomL.lreset[11] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottomL.lclk[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottomL.lreset[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottomL.lclk[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottomL.lreset[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottomL.lclk[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottomL.lreset[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottomL.lclk[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottomL.lreset[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottomL.lclk[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottomL.lreset[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottomL.lclk[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottomL.lreset[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottomL.lclk[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottomL.lreset[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottomL.lclk[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_bottomL.lreset[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 io_bottom_dspL.a2f_o[0] + + + l1.W2 l2.W1 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.W3 l3.W5 l8.W7 io_bottom_dspL.a2f_o[0] + + + l1.W4 l3.W8 l8.W15 + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + l1.E10 l1.E11 l3.E20 io_bottom_dspL.a2f_o[2] + + + l1.E12 l2.E5 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E0 l3.E23 l8.E7 io_bottom_dspL.a2f_o[2] + + + l1.E1 l3.E2 l8.E15 + + + l1.S2 l1.S3 l3.S5 io_bottom_dspL.a2f_o[3] + + + l1.S4 l2.S1 l4.S15 io_bottom_dspL.a2f_o[3] + + + l1.S5 l3.S8 l8.S7 io_bottom_dspL.a2f_o[3] + + + l1.S6 l3.S11 l8.S15 + + + l1.W7 l1.W8 l3.W14 io_bottom_dspL.a2f_o[0] + + + l1.W9 l2.W3 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.W10 l3.W17 l8.W7 io_bottom_dspL.a2f_o[0] + + + l1.W11 l3.W20 l8.W15 + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + l1.E4 l1.E5 l3.E8 io_bottom_dspL.a2f_o[2] + + + l1.E6 l2.E1 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E7 l3.E11 l8.E7 io_bottom_dspL.a2f_o[2] + + + l1.E8 l3.E14 l8.E15 + + + l1.S9 l1.S10 l3.S17 io_bottom_dspL.a2f_o[3] + + + l1.S11 l2.S3 l4.S15 io_bottom_dspL.a2f_o[3] + + + l1.S12 l3.S20 l8.S7 io_bottom_dspL.a2f_o[3] + + + l1.S0 l3.S23 l8.S15 + + + l1.W1 l1.W2 l3.W2 io_bottom_dspL.a2f_o[0] + + + l1.W3 l2.W5 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.W4 l3.W5 l8.W7 io_bottom_dspL.a2f_o[0] + + + l1.W5 l3.W8 l8.W15 + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + l1.E11 l1.E12 l3.E20 io_bottom_dspL.a2f_o[2] + + + l1.E0 l2.E3 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E1 l3.E23 l8.E7 io_bottom_dspL.a2f_o[2] + + + l1.E2 l3.E2 l8.E15 + + + l1.S3 l1.S4 l3.S5 io_bottom_dspL.a2f_o[3] + + + l1.S5 l2.S5 l4.S15 io_bottom_dspL.a2f_o[3] + + + l1.S6 l3.S8 l8.S7 io_bottom_dspL.a2f_o[3] + + + l1.S7 l3.S11 l8.S15 + + + l1.W8 l1.W9 l3.W14 io_bottom_dspL.a2f_o[0] + + + l1.W10 l2.W1 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.W11 l3.W17 l8.W7 io_bottom_dspL.a2f_o[0] + + + l1.W12 l3.W20 l8.W15 + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + l1.E5 l1.E6 l3.E8 io_bottom_dspL.a2f_o[2] + + + l1.E7 l2.E5 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E8 l3.E11 l8.E7 io_bottom_dspL.a2f_o[2] + + + l1.E9 l3.E14 l8.E15 + + + l1.S10 l1.S11 l3.S17 io_bottom_dspL.a2f_o[3] + + + l1.S12 l2.S1 l4.S15 io_bottom_dspL.a2f_o[3] + + + l1.S0 l3.S20 l8.S7 io_bottom_dspL.a2f_o[3] + + + l1.S1 l3.S23 l8.S15 + + + l1.W2 l1.W3 l3.W2 io_bottom_dspL.a2f_o[0] + + + l1.W4 l2.W3 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.W5 l3.W5 l8.W7 io_bottom_dspL.a2f_o[0] + + + l1.W6 l3.W8 l8.W15 + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + l1.E12 l1.E0 l3.E20 io_bottom_dspL.a2f_o[2] + + + l1.E1 l2.E1 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E2 l3.E23 l8.E7 io_bottom_dspL.a2f_o[2] + + + l1.E3 l3.E2 l8.E15 + + + l1.S4 l1.S5 l3.S5 io_bottom_dspL.a2f_o[3] + + + l1.S6 l2.S3 l4.S15 io_bottom_dspL.a2f_o[3] + + + l1.S7 l3.S8 l8.S7 io_bottom_dspL.a2f_o[3] + + + l1.S8 l3.S11 l8.S15 + + + l1.W9 l1.W10 l3.W14 io_bottom_dspL.a2f_o[0] + + + l1.W11 l2.W5 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.W12 l3.W17 l8.W7 io_bottom_dspL.a2f_o[0] + + + l1.W0 l3.W20 l8.W15 + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + l1.E6 l1.E7 l3.E8 io_bottom_dspL.a2f_o[2] + + + l1.E8 l2.E3 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E9 l3.E11 l8.E7 io_bottom_dspL.a2f_o[2] + + + l1.E10 l3.E14 l8.E15 + + + l1.S11 l1.S12 l3.S17 io_bottom_dspL.a2f_o[3] + + + l1.S0 l2.S5 l4.S15 io_bottom_dspL.a2f_o[3] + + + l1.S1 l3.S20 l8.S7 io_bottom_dspL.a2f_o[3] + + + l1.S2 l3.S23 l8.S15 + + + l1.W3 l1.W4 l3.W2 io_bottom_dspL.a2f_o[0] + + + l1.W5 l2.W1 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.W6 l3.W5 l8.W7 io_bottom_dspL.a2f_o[0] + + + l1.W7 l3.W8 l8.W15 + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + l1.E0 l1.E1 l3.E20 io_bottom_dspL.a2f_o[2] + + + l1.E2 l2.E5 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E3 l3.E23 l8.E7 io_bottom_dspL.a2f_o[2] + + + l1.E4 l3.E2 l8.E15 + + + l1.S5 l1.S6 l3.S5 io_bottom_dspL.a2f_o[3] + + + l1.S7 l2.S1 l4.S15 io_bottom_dspL.a2f_o[3] + + + l1.S8 l3.S8 l8.S7 io_bottom_dspL.a2f_o[3] + + + l1.S9 l3.S11 l8.S15 + + + l1.W10 l1.W11 l3.W14 io_bottom_dspL.a2f_o[0] + + + l1.W12 l2.W3 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.W0 l3.W17 l8.W7 io_bottom_dspL.a2f_o[0] + + + l1.W1 l3.W20 l8.W15 + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] + + + l1.E7 l1.E8 l3.E8 io_bottom_dspL.a2f_o[2] + + + l1.E9 l2.E1 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E10 l3.E11 l8.E7 io_bottom_dspL.a2f_o[2] + + + l1.E11 l3.E14 l8.E15 + + + l1.S12 l1.S0 l3.S17 io_bottom_dspL.a2f_o[3] + + + l1.S1 l2.S3 l4.S15 io_bottom_dspL.a2f_o[3] + + + l1.S2 l3.S20 l8.S7 io_bottom_dspL.a2f_o[3] + + + l1.S3 l3.S23 l8.S15 + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_bottom_dspL.a2f_o[0] OG_0 + + + l1.E12 l1.E11 l2.E5 l3.E23 l4.E15 io_bottom_dspL.a2f_o[0] + + + l1.E5 l1.S11 l3.E8 l3.S17 l4.E3 io_bottom_dspL.a2f_o[0] + + + l1.W11 l1.S10 l3.W20 l4.W11 io_bottom_dspL.a2f_o[1] + + + l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 io_bottom_dspL.a2f_o[1] + + + l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 io_bottom_dspL.a2f_o[1] OG_2 + + + l1.W3 l2.W3 l3.W2 io_bottom_dspL.a2f_o[2] OG_2 l1.S4 + + + l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 io_bottom_dspL.a2f_o[2] OG_3 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_bottom_dspL.a2f_o[2] OG_4 + + + l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 io_bottom_dspL.a2f_o[3] + + + l1.W1 l3.W20 l4.W7 io_bottom_dspL.a2f_o[3] + + + l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 io_bottom_dspL.a2f_o[3] + + + l1.W0 l1.E12 l3.W17 l4.W3 io_bottom_dspL.a2f_o[0] + + + l1.E6 l2.E5 l3.E5 io_bottom_dspL.a2f_o[0] OG_6 l1.E5 + + + l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 io_bottom_dspL.a2f_o[0] OG_6 l1.S4 + + + l1.W5 l2.W3 l3.W2 l4.W11 io_bottom_dspL.a2f_o[1] OG_7 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_bottom_dspL.a2f_o[1] OG_0 + + + l1.W4 l1.E3 l2.W1 l3.W23 l4.W7 io_bottom_dspL.a2f_o[1] + + + l1.E10 l3.E8 l4.E11 io_bottom_dspL.a2f_o[2] + + + l1.E3 l1.S2 l3.E20 l4.E3 io_bottom_dspL.a2f_o[2] + + + l1.E9 l1.E8 l3.E5 l4.E7 io_bottom_dspL.a2f_o[2] + + + l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 io_bottom_dspL.a2f_o[3] OG_2 l1.E0 + + + l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 io_bottom_dspL.a2f_o[3] OG_2 + + + l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 io_bottom_dspL.a2f_o[3] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_bottom_dspL.a2f_o[0] OG_4 + + + l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 io_bottom_dspL.a2f_o[0] + + + l1.W6 l1.S12 l3.W20 l3.S5 l4.W15 io_bottom_dspL.a2f_o[0] + + + l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 io_bottom_dspL.a2f_o[1] + + + l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 io_bottom_dspL.a2f_o[1] + + + l1.W11 l2.W1 l3.W5 io_bottom_dspL.a2f_o[1] OG_6 l1.W6 + + + l1.E4 l2.E3 l3.E14 io_bottom_dspL.a2f_o[2] OG_6 l1.S8 + + + l1.E10 l2.E5 l3.E2 l4.E3 io_bottom_dspL.a2f_o[2] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_bottom_dspL.a2f_o[2] OG_0 + + + l1.E9 l1.E8 l2.E3 l3.E23 l4.E15 io_bottom_dspL.a2f_o[3] + + + l1.E2 l1.S8 l3.E8 l3.S17 l4.E3 io_bottom_dspL.a2f_o[3] + + + l1.W8 l1.S7 l3.W20 l4.W11 io_bottom_dspL.a2f_o[3] + + + l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 io_bottom_dspL.a2f_o[0] + + + l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 io_bottom_dspL.a2f_o[0] OG_2 l1.S6 + + + l1.W0 l2.W1 l3.W2 io_bottom_dspL.a2f_o[0] OG_2 l1.E0 + + + l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 io_bottom_dspL.a2f_o[1] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_bottom_dspL.a2f_o[1] OG_4 + + + l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 io_bottom_dspL.a2f_o[1] + + + l1.W11 l3.W20 l4.W7 io_bottom_dspL.a2f_o[2] + + + l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 io_bottom_dspL.a2f_o[2] + + + l1.W10 l1.E9 l3.W17 l4.W3 io_bottom_dspL.a2f_o[2] + + + l1.E3 l2.E3 l3.E5 io_bottom_dspL.a2f_o[3] OG_6 l1.E2 + + + l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 io_bottom_dspL.a2f_o[3] OG_6 l1.W3 + + + l1.W2 l2.W1 l3.W2 l4.W11 io_bottom_dspL.a2f_o[3] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_bottom_dspL.a2f_o[0] OG_0 + + + l1.W1 l1.E0 l2.W5 l3.W23 l4.W7 io_bottom_dspL.a2f_o[0] + + + l1.E7 l3.E8 l4.E11 io_bottom_dspL.a2f_o[0] + + + l1.E0 l1.S12 l3.E20 l4.E3 io_bottom_dspL.a2f_o[1] + + + l1.E6 l1.E5 l3.E5 l4.E7 io_bottom_dspL.a2f_o[1] + + + l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 io_bottom_dspL.a2f_o[1] OG_2 l1.W12 + + + l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 io_bottom_dspL.a2f_o[2] OG_2 l1.W4 + + + l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 io_bottom_dspL.a2f_o[2] OG_3 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_bottom_dspL.a2f_o[2] OG_4 + + + l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 io_bottom_dspL.a2f_o[3] + + + l1.W3 l1.S9 l3.W20 l3.S5 l4.W15 io_bottom_dspL.a2f_o[3] + + + l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 io_bottom_dspL.a2f_o[3] + + + io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] + + + io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] + + + io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] + + + io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[3] + + + io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] + + + io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] + + + io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] + + + io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] + + + io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] + + + io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[3] + + + io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 mux_15 + + + l1.N0 + mux_16 mux_21 mux_11 mux_14 + + + l1.E0 + mux_32 mux_6 mux_9 mux_31 + + + l1.W1 + mux_64 mux_25 mux_30 + + + l1.N1 + mux_80 mux_26 mux_29 + + + l1.E1 + mux_1 mux_4 mux_42 mux_47 + + + l1.W2 + mux_33 mux_38 mux_8 mux_63 + + + l1.N2 + mux_49 mux_54 mux_59 mux_12 + + + l1.E2 + mux_65 mux_24 mux_62 + + + l1.W3 + mux_2 mux_36 mux_41 mux_79 + + + l1.N3 + mux_18 mux_52 mux_75 mux_45 + + + l1.E3 + mux_34 mux_37 mux_40 mux_95 + + + l1.W4 + mux_66 mux_56 mux_61 + + + l1.N4 + mux_82 mux_57 mux_60 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.N5 + mux_51 mux_85 mux_90 mux_76 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.W6 + mux_96 mux_101 mux_106 mux_111 + + + l1.N6 + mux_112 mux_117 mux_107 mux_110 + + + l1.E6 + mux_0 mux_102 mux_105 mux_127 + + + l1.W7 + mux_32 mux_121 mux_126 + + + l1.N7 + mux_48 mux_122 mux_125 + + + l1.E7 + mux_97 mux_100 mux_10 mux_15 + + + l1.W8 + mux_1 mux_6 mux_104 mux_31 + + + l1.N8 + mux_17 mux_22 mux_27 mux_108 + + + l1.E8 + mux_33 mux_120 mux_30 + + + l2.W0 + mux_98 mux_4 mux_9 mux_47 + + + l2.N0 + mux_114 mux_20 mux_43 mux_13 + + + l2.E0 + mux_2 mux_5 mux_8 mux_63 + + + l2.W2 + mux_34 mux_24 mux_29 + + + l2.N2 + mux_50 mux_25 mux_28 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.N4 + mux_19 mux_53 mux_58 mux_44 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l3.W0 + mux_64 mux_69 mux_74 mux_79 + + + l3.N0 + mux_80 mux_85 mux_75 mux_78 + + + l3.E0 + mux_96 mux_70 mux_73 mux_95 + + + l3.W3 + mux_0 mux_89 mux_94 + + + l3.N3 + mux_16 mux_90 mux_93 + + + l3.E3 + mux_65 mux_68 mux_106 mux_111 + + + l3.W6 + mux_97 mux_102 mux_72 mux_127 + + + l3.N6 + mux_113 mux_118 mux_123 mux_76 + + + l3.E6 + mux_1 mux_88 mux_126 + + + l3.W9 + mux_66 mux_100 mux_105 mux_15 + + + l3.N9 + mux_82 mux_116 mux_11 mux_109 + + + l3.E9 + mux_98 mux_101 mux_104 mux_31 + + + l3.W12 + mux_2 mux_120 mux_125 + + + l3.N12 + mux_18 mux_121 mux_124 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.N15 + mux_115 mux_21 mux_26 mux_12 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.W18 + mux_32 mux_37 mux_42 mux_47 + + + l3.N18 + mux_48 mux_53 mux_43 mux_46 + + + l3.E18 + mux_64 mux_38 mux_41 mux_63 + + + l3.W21 + mux_96 mux_57 mux_62 + + + l3.N21 + mux_112 mux_58 mux_61 + + + l3.E21 + mux_33 mux_36 mux_74 mux_79 + + + l4.W0 + mux_65 mux_70 mux_40 mux_95 + + + l4.N0 + mux_81 mux_86 mux_91 mux_44 + + + l4.E0 + mux_97 mux_56 mux_94 + + + l4.W4 + mux_34 mux_68 mux_73 mux_111 + + + l4.N4 + mux_50 mux_84 mux_107 mux_77 + + + l4.E4 + mux_66 mux_69 mux_72 mux_127 + + + l4.W8 + mux_98 mux_88 mux_93 + + + l4.N8 + mux_114 mux_89 mux_92 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.N12 + mux_83 mux_117 mux_122 mux_108 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l8.W0 + mux_0 mux_5 mux_10 mux_15 + + + l8.N0 + mux_16 mux_21 mux_11 mux_14 + + + l8.E0 + mux_32 mux_6 mux_9 mux_31 + + + l8.W8 + mux_64 mux_25 mux_30 + + + l8.N8 + mux_80 mux_26 mux_29 + + + l8.E8 + mux_1 mux_4 mux_42 mux_47 + + + l1.W9 + l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N9 + l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E9 + l1.W9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.W10 + l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N10 + l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E10 + l1.W10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W11 + l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.N11 + l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E11 + l1.W11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W12 + l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N12 + l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E12 + l1.W12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + io_bottom_dspL.f2a_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_dspL.f2a_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_dspL.f2a_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_dspL.f2a_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_dspL.f2a_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottom_dspL.f2a_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottom_dspL.f2a_i[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottom_dspL.f2a_i[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottom_dspL.f2a_i[0] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottom_dspL.f2a_i[1] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottom_dspL.f2a_i[2] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottom_dspL.f2a_i[3] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_bottom_dspL.f2a_i[4] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_bottom_dspL.f2a_i[5] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_bottom_dspL.f2a_i[6] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_bottom_dspL.f2a_i[7] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + io_bottom_dspL.f2a_i[0] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_bottom_dspL.f2a_i[1] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_bottom_dspL.f2a_i[2] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_bottom_dspL.f2a_i[3] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + io_bottom_dspL.f2a_i[4] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_bottom_dspL.f2a_i[5] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_dspL.f2a_i[6] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_bottom_dspL.f2a_i[7] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + io_bottom_dspL.f2a_i[0] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_bottom_dspL.f2a_i[1] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottom_dspL.f2a_i[2] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_bottom_dspL.f2a_i[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + io_bottom_dspL.f2a_i[4] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_bottom_dspL.f2a_i[5] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottom_dspL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_bottom_dspL.f2a_i[7] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + io_bottom_dspL.f2a_i[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + io_bottom_dspL.f2a_i[1] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_bottom_dspL.f2a_i[2] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + io_bottom_dspL.f2a_i[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + io_bottom_dspL.f2a_i[4] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + io_bottom_dspL.f2a_i[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 + + + io_bottom_dspL.f2a_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + io_bottom_dspL.f2a_i[7] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + io_bottom_dspL.f2a_i[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_dspL.f2a_i[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 + + + io_bottom_dspL.f2a_i[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_dspL.f2a_i[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_dspL.f2a_i[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + io_bottom_dspL.f2a_i[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 + + + io_bottom_dspL.f2a_i[6] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + io_bottom_dspL.f2a_i[7] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + io_bottom_dspL.f2a_i[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + io_bottom_dspL.f2a_i[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 + + + io_bottom_dspL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + io_bottom_dspL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + io_bottom_dspL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + io_bottom_dspL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 + + + io_bottom_dspL.f2a_i[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + io_bottom_dspL.f2a_i[7] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + io_bottom_dspL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + io_bottom_dspL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 + + + io_bottom_dspL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + io_bottom_dspL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + io_bottom_dspL.lclk[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_dspL.lreset[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_dspL.lclk[8] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_dspL.lreset[8] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_dspL.lclk[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_dspL.lreset[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_dspL.lclk[9] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_dspL.lreset[9] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_dspL.lclk[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_dspL.lreset[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_dspL.lclk[10] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_dspL.lreset[10] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_dspL.lclk[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_dspL.lreset[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_dspL.lclk[11] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_dspL.lreset[11] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_dspL.lclk[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottom_dspL.lreset[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottom_dspL.lclk[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottom_dspL.lreset[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottom_dspL.lclk[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottom_dspL.lreset[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottom_dspL.lclk[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottom_dspL.lreset[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottom_dspL.lclk[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottom_dspL.lreset[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottom_dspL.lclk[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottom_dspL.lreset[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottom_dspL.lclk[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottom_dspL.lreset[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottom_dspL.lclk[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_bottom_dspL.lreset[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 io_bottom_ramL.a2f_o[0] + + + l1.W2 l2.W1 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.W3 l3.W5 l8.W7 io_bottom_ramL.a2f_o[0] + + + l1.W4 l3.W8 l8.W15 + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + l1.E10 l1.E11 l3.E20 io_bottom_ramL.a2f_o[2] + + + l1.E12 l2.E5 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E0 l3.E23 l8.E7 io_bottom_ramL.a2f_o[2] + + + l1.E1 l3.E2 l8.E15 + + + l1.S2 l1.S3 l3.S5 io_bottom_ramL.a2f_o[3] + + + l1.S4 l2.S1 l4.S15 io_bottom_ramL.a2f_o[3] + + + l1.S5 l3.S8 l8.S7 io_bottom_ramL.a2f_o[3] + + + l1.S6 l3.S11 l8.S15 + + + l1.W7 l1.W8 l3.W14 io_bottom_ramL.a2f_o[0] + + + l1.W9 l2.W3 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.W10 l3.W17 l8.W7 io_bottom_ramL.a2f_o[0] + + + l1.W11 l3.W20 l8.W15 + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + l1.E4 l1.E5 l3.E8 io_bottom_ramL.a2f_o[2] + + + l1.E6 l2.E1 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E7 l3.E11 l8.E7 io_bottom_ramL.a2f_o[2] + + + l1.E8 l3.E14 l8.E15 + + + l1.S9 l1.S10 l3.S17 io_bottom_ramL.a2f_o[3] + + + l1.S11 l2.S3 l4.S15 io_bottom_ramL.a2f_o[3] + + + l1.S12 l3.S20 l8.S7 io_bottom_ramL.a2f_o[3] + + + l1.S0 l3.S23 l8.S15 + + + l1.W1 l1.W2 l3.W2 io_bottom_ramL.a2f_o[0] + + + l1.W3 l2.W5 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.W4 l3.W5 l8.W7 io_bottom_ramL.a2f_o[0] + + + l1.W5 l3.W8 l8.W15 + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + l1.E11 l1.E12 l3.E20 io_bottom_ramL.a2f_o[2] + + + l1.E0 l2.E3 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E1 l3.E23 l8.E7 io_bottom_ramL.a2f_o[2] + + + l1.E2 l3.E2 l8.E15 + + + l1.S3 l1.S4 l3.S5 io_bottom_ramL.a2f_o[3] + + + l1.S5 l2.S5 l4.S15 io_bottom_ramL.a2f_o[3] + + + l1.S6 l3.S8 l8.S7 io_bottom_ramL.a2f_o[3] + + + l1.S7 l3.S11 l8.S15 + + + l1.W8 l1.W9 l3.W14 io_bottom_ramL.a2f_o[0] + + + l1.W10 l2.W1 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.W11 l3.W17 l8.W7 io_bottom_ramL.a2f_o[0] + + + l1.W12 l3.W20 l8.W15 + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + l1.E5 l1.E6 l3.E8 io_bottom_ramL.a2f_o[2] + + + l1.E7 l2.E5 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E8 l3.E11 l8.E7 io_bottom_ramL.a2f_o[2] + + + l1.E9 l3.E14 l8.E15 + + + l1.S10 l1.S11 l3.S17 io_bottom_ramL.a2f_o[3] + + + l1.S12 l2.S1 l4.S15 io_bottom_ramL.a2f_o[3] + + + l1.S0 l3.S20 l8.S7 io_bottom_ramL.a2f_o[3] + + + l1.S1 l3.S23 l8.S15 + + + l1.W2 l1.W3 l3.W2 io_bottom_ramL.a2f_o[0] + + + l1.W4 l2.W3 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.W5 l3.W5 l8.W7 io_bottom_ramL.a2f_o[0] + + + l1.W6 l3.W8 l8.W15 + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + l1.E12 l1.E0 l3.E20 io_bottom_ramL.a2f_o[2] + + + l1.E1 l2.E1 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E2 l3.E23 l8.E7 io_bottom_ramL.a2f_o[2] + + + l1.E3 l3.E2 l8.E15 + + + l1.S4 l1.S5 l3.S5 io_bottom_ramL.a2f_o[3] + + + l1.S6 l2.S3 l4.S15 io_bottom_ramL.a2f_o[3] + + + l1.S7 l3.S8 l8.S7 io_bottom_ramL.a2f_o[3] + + + l1.S8 l3.S11 l8.S15 + + + l1.W9 l1.W10 l3.W14 io_bottom_ramL.a2f_o[0] + + + l1.W11 l2.W5 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.W12 l3.W17 l8.W7 io_bottom_ramL.a2f_o[0] + + + l1.W0 l3.W20 l8.W15 + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + l1.E6 l1.E7 l3.E8 io_bottom_ramL.a2f_o[2] + + + l1.E8 l2.E3 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E9 l3.E11 l8.E7 io_bottom_ramL.a2f_o[2] + + + l1.E10 l3.E14 l8.E15 + + + l1.S11 l1.S12 l3.S17 io_bottom_ramL.a2f_o[3] + + + l1.S0 l2.S5 l4.S15 io_bottom_ramL.a2f_o[3] + + + l1.S1 l3.S20 l8.S7 io_bottom_ramL.a2f_o[3] + + + l1.S2 l3.S23 l8.S15 + + + l1.W3 l1.W4 l3.W2 io_bottom_ramL.a2f_o[0] + + + l1.W5 l2.W1 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.W6 l3.W5 l8.W7 io_bottom_ramL.a2f_o[0] + + + l1.W7 l3.W8 l8.W15 + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + l1.E0 l1.E1 l3.E20 io_bottom_ramL.a2f_o[2] + + + l1.E2 l2.E5 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E3 l3.E23 l8.E7 io_bottom_ramL.a2f_o[2] + + + l1.E4 l3.E2 l8.E15 + + + l1.S5 l1.S6 l3.S5 io_bottom_ramL.a2f_o[3] + + + l1.S7 l2.S1 l4.S15 io_bottom_ramL.a2f_o[3] + + + l1.S8 l3.S8 l8.S7 io_bottom_ramL.a2f_o[3] + + + l1.S9 l3.S11 l8.S15 + + + l1.W10 l1.W11 l3.W14 io_bottom_ramL.a2f_o[0] + + + l1.W12 l2.W3 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.W0 l3.W17 l8.W7 io_bottom_ramL.a2f_o[0] + + + l1.W1 l3.W20 l8.W15 + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] + + + l1.E7 l1.E8 l3.E8 io_bottom_ramL.a2f_o[2] + + + l1.E9 l2.E1 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E10 l3.E11 l8.E7 io_bottom_ramL.a2f_o[2] + + + l1.E11 l3.E14 l8.E15 + + + l1.S12 l1.S0 l3.S17 io_bottom_ramL.a2f_o[3] + + + l1.S1 l2.S3 l4.S15 io_bottom_ramL.a2f_o[3] + + + l1.S2 l3.S20 l8.S7 io_bottom_ramL.a2f_o[3] + + + l1.S3 l3.S23 l8.S15 + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_bottom_ramL.a2f_o[0] OG_0 + + + l1.E12 l1.E11 l2.E5 l3.E23 l4.E15 io_bottom_ramL.a2f_o[0] + + + l1.E5 l1.S11 l3.E8 l3.S17 l4.E3 io_bottom_ramL.a2f_o[0] + + + l1.W11 l1.S10 l3.W20 l4.W11 io_bottom_ramL.a2f_o[1] + + + l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 io_bottom_ramL.a2f_o[1] + + + l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 io_bottom_ramL.a2f_o[1] OG_2 + + + l1.W3 l2.W3 l3.W2 io_bottom_ramL.a2f_o[2] OG_2 l1.S4 + + + l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 io_bottom_ramL.a2f_o[2] OG_3 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_bottom_ramL.a2f_o[2] OG_4 + + + l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 io_bottom_ramL.a2f_o[3] + + + l1.W1 l3.W20 l4.W7 io_bottom_ramL.a2f_o[3] + + + l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 io_bottom_ramL.a2f_o[3] + + + l1.W0 l1.E12 l3.W17 l4.W3 io_bottom_ramL.a2f_o[0] + + + l1.E6 l2.E5 l3.E5 io_bottom_ramL.a2f_o[0] OG_6 l1.E5 + + + l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 io_bottom_ramL.a2f_o[0] OG_6 l1.S4 + + + l1.W5 l2.W3 l3.W2 l4.W11 io_bottom_ramL.a2f_o[1] OG_7 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_bottom_ramL.a2f_o[1] OG_0 + + + l1.W4 l1.E3 l2.W1 l3.W23 l4.W7 io_bottom_ramL.a2f_o[1] + + + l1.E10 l3.E8 l4.E11 io_bottom_ramL.a2f_o[2] + + + l1.E3 l1.S2 l3.E20 l4.E3 io_bottom_ramL.a2f_o[2] + + + l1.E9 l1.E8 l3.E5 l4.E7 io_bottom_ramL.a2f_o[2] + + + l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 io_bottom_ramL.a2f_o[3] OG_2 l1.E0 + + + l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 io_bottom_ramL.a2f_o[3] OG_2 + + + l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 io_bottom_ramL.a2f_o[3] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_bottom_ramL.a2f_o[0] OG_4 + + + l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 io_bottom_ramL.a2f_o[0] + + + l1.W6 l1.S12 l3.W20 l3.S5 l4.W15 io_bottom_ramL.a2f_o[0] + + + l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 io_bottom_ramL.a2f_o[1] + + + l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 io_bottom_ramL.a2f_o[1] + + + l1.W11 l2.W1 l3.W5 io_bottom_ramL.a2f_o[1] OG_6 l1.W6 + + + l1.E4 l2.E3 l3.E14 io_bottom_ramL.a2f_o[2] OG_6 l1.S8 + + + l1.E10 l2.E5 l3.E2 l4.E3 io_bottom_ramL.a2f_o[2] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_bottom_ramL.a2f_o[2] OG_0 + + + l1.E9 l1.E8 l2.E3 l3.E23 l4.E15 io_bottom_ramL.a2f_o[3] + + + l1.E2 l1.S8 l3.E8 l3.S17 l4.E3 io_bottom_ramL.a2f_o[3] + + + l1.W8 l1.S7 l3.W20 l4.W11 io_bottom_ramL.a2f_o[3] + + + l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 io_bottom_ramL.a2f_o[0] + + + l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 io_bottom_ramL.a2f_o[0] OG_2 l1.S6 + + + l1.W0 l2.W1 l3.W2 io_bottom_ramL.a2f_o[0] OG_2 l1.E0 + + + l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 io_bottom_ramL.a2f_o[1] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_bottom_ramL.a2f_o[1] OG_4 + + + l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 io_bottom_ramL.a2f_o[1] + + + l1.W11 l3.W20 l4.W7 io_bottom_ramL.a2f_o[2] + + + l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 io_bottom_ramL.a2f_o[2] + + + l1.W10 l1.E9 l3.W17 l4.W3 io_bottom_ramL.a2f_o[2] + + + l1.E3 l2.E3 l3.E5 io_bottom_ramL.a2f_o[3] OG_6 l1.E2 + + + l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 io_bottom_ramL.a2f_o[3] OG_6 l1.W3 + + + l1.W2 l2.W1 l3.W2 l4.W11 io_bottom_ramL.a2f_o[3] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_bottom_ramL.a2f_o[0] OG_0 + + + l1.W1 l1.E0 l2.W5 l3.W23 l4.W7 io_bottom_ramL.a2f_o[0] + + + l1.E7 l3.E8 l4.E11 io_bottom_ramL.a2f_o[0] + + + l1.E0 l1.S12 l3.E20 l4.E3 io_bottom_ramL.a2f_o[1] + + + l1.E6 l1.E5 l3.E5 l4.E7 io_bottom_ramL.a2f_o[1] + + + l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 io_bottom_ramL.a2f_o[1] OG_2 l1.W12 + + + l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 io_bottom_ramL.a2f_o[2] OG_2 l1.W4 + + + l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 io_bottom_ramL.a2f_o[2] OG_3 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_bottom_ramL.a2f_o[2] OG_4 + + + l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 io_bottom_ramL.a2f_o[3] + + + l1.W3 l1.S9 l3.W20 l3.S5 l4.W15 io_bottom_ramL.a2f_o[3] + + + l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 io_bottom_ramL.a2f_o[3] + + + io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] + + + io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] + + + io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] + + + io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[3] + + + io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] + + + io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] + + + io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] + + + io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] + + + io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] + + + io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[3] + + + io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 mux_15 + + + l1.N0 + mux_16 mux_21 mux_11 mux_14 + + + l1.E0 + mux_32 mux_6 mux_9 mux_31 + + + l1.W1 + mux_64 mux_25 mux_30 + + + l1.N1 + mux_80 mux_26 mux_29 + + + l1.E1 + mux_1 mux_4 mux_42 mux_47 + + + l1.W2 + mux_33 mux_38 mux_8 mux_63 + + + l1.N2 + mux_49 mux_54 mux_59 mux_12 + + + l1.E2 + mux_65 mux_24 mux_62 + + + l1.W3 + mux_2 mux_36 mux_41 mux_79 + + + l1.N3 + mux_18 mux_52 mux_75 mux_45 + + + l1.E3 + mux_34 mux_37 mux_40 mux_95 + + + l1.W4 + mux_66 mux_56 mux_61 + + + l1.N4 + mux_82 mux_57 mux_60 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.N5 + mux_51 mux_85 mux_90 mux_76 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.W6 + mux_96 mux_101 mux_106 mux_111 + + + l1.N6 + mux_112 mux_117 mux_107 mux_110 + + + l1.E6 + mux_0 mux_102 mux_105 mux_127 + + + l1.W7 + mux_32 mux_121 mux_126 + + + l1.N7 + mux_48 mux_122 mux_125 + + + l1.E7 + mux_97 mux_100 mux_10 mux_15 + + + l1.W8 + mux_1 mux_6 mux_104 mux_31 + + + l1.N8 + mux_17 mux_22 mux_27 mux_108 + + + l1.E8 + mux_33 mux_120 mux_30 + + + l2.W0 + mux_98 mux_4 mux_9 mux_47 + + + l2.N0 + mux_114 mux_20 mux_43 mux_13 + + + l2.E0 + mux_2 mux_5 mux_8 mux_63 + + + l2.W2 + mux_34 mux_24 mux_29 + + + l2.N2 + mux_50 mux_25 mux_28 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.N4 + mux_19 mux_53 mux_58 mux_44 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l3.W0 + mux_64 mux_69 mux_74 mux_79 + + + l3.N0 + mux_80 mux_85 mux_75 mux_78 + + + l3.E0 + mux_96 mux_70 mux_73 mux_95 + + + l3.W3 + mux_0 mux_89 mux_94 + + + l3.N3 + mux_16 mux_90 mux_93 + + + l3.E3 + mux_65 mux_68 mux_106 mux_111 + + + l3.W6 + mux_97 mux_102 mux_72 mux_127 + + + l3.N6 + mux_113 mux_118 mux_123 mux_76 + + + l3.E6 + mux_1 mux_88 mux_126 + + + l3.W9 + mux_66 mux_100 mux_105 mux_15 + + + l3.N9 + mux_82 mux_116 mux_11 mux_109 + + + l3.E9 + mux_98 mux_101 mux_104 mux_31 + + + l3.W12 + mux_2 mux_120 mux_125 + + + l3.N12 + mux_18 mux_121 mux_124 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.N15 + mux_115 mux_21 mux_26 mux_12 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.W18 + mux_32 mux_37 mux_42 mux_47 + + + l3.N18 + mux_48 mux_53 mux_43 mux_46 + + + l3.E18 + mux_64 mux_38 mux_41 mux_63 + + + l3.W21 + mux_96 mux_57 mux_62 + + + l3.N21 + mux_112 mux_58 mux_61 + + + l3.E21 + mux_33 mux_36 mux_74 mux_79 + + + l4.W0 + mux_65 mux_70 mux_40 mux_95 + + + l4.N0 + mux_81 mux_86 mux_91 mux_44 + + + l4.E0 + mux_97 mux_56 mux_94 + + + l4.W4 + mux_34 mux_68 mux_73 mux_111 + + + l4.N4 + mux_50 mux_84 mux_107 mux_77 + + + l4.E4 + mux_66 mux_69 mux_72 mux_127 + + + l4.W8 + mux_98 mux_88 mux_93 + + + l4.N8 + mux_114 mux_89 mux_92 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.N12 + mux_83 mux_117 mux_122 mux_108 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l8.W0 + mux_0 mux_5 mux_10 mux_15 + + + l8.N0 + mux_16 mux_21 mux_11 mux_14 + + + l8.E0 + mux_32 mux_6 mux_9 mux_31 + + + l8.W8 + mux_64 mux_25 mux_30 + + + l8.N8 + mux_80 mux_26 mux_29 + + + l8.E8 + mux_1 mux_4 mux_42 mux_47 + + + l1.W9 + l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N9 + l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E9 + l1.W9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.W10 + l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N10 + l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E10 + l1.W10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W11 + l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.N11 + l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E11 + l1.W11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W12 + l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N12 + l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E12 + l1.W12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + io_bottom_ramL.f2a_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_ramL.f2a_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_ramL.f2a_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_ramL.f2a_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_ramL.f2a_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottom_ramL.f2a_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottom_ramL.f2a_i[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottom_ramL.f2a_i[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottom_ramL.f2a_i[0] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottom_ramL.f2a_i[1] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottom_ramL.f2a_i[2] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottom_ramL.f2a_i[3] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_bottom_ramL.f2a_i[4] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + io_bottom_ramL.f2a_i[5] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_bottom_ramL.f2a_i[6] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + io_bottom_ramL.f2a_i[7] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + io_bottom_ramL.f2a_i[0] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + io_bottom_ramL.f2a_i[1] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + + io_bottom_ramL.f2a_i[2] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + io_bottom_ramL.f2a_i[3] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + io_bottom_ramL.f2a_i[4] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + io_bottom_ramL.f2a_i[5] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_ramL.f2a_i[6] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + io_bottom_ramL.f2a_i[7] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + io_bottom_ramL.f2a_i[0] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + io_bottom_ramL.f2a_i[1] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottom_ramL.f2a_i[2] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + io_bottom_ramL.f2a_i[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + io_bottom_ramL.f2a_i[4] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + io_bottom_ramL.f2a_i[5] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottom_ramL.f2a_i[6] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + io_bottom_ramL.f2a_i[7] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + io_bottom_ramL.f2a_i[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + io_bottom_ramL.f2a_i[1] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_bottom_ramL.f2a_i[2] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + io_bottom_ramL.f2a_i[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + io_bottom_ramL.f2a_i[4] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + io_bottom_ramL.f2a_i[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 + + + io_bottom_ramL.f2a_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + io_bottom_ramL.f2a_i[7] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + io_bottom_ramL.f2a_i[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_ramL.f2a_i[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 + + + io_bottom_ramL.f2a_i[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_ramL.f2a_i[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_ramL.f2a_i[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + io_bottom_ramL.f2a_i[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 + + + io_bottom_ramL.f2a_i[6] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + io_bottom_ramL.f2a_i[7] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + io_bottom_ramL.f2a_i[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + io_bottom_ramL.f2a_i[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 + + + io_bottom_ramL.f2a_i[2] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + io_bottom_ramL.f2a_i[3] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + io_bottom_ramL.f2a_i[4] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + io_bottom_ramL.f2a_i[5] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 + + + io_bottom_ramL.f2a_i[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + io_bottom_ramL.f2a_i[7] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + io_bottom_ramL.f2a_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + io_bottom_ramL.f2a_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 + + + io_bottom_ramL.f2a_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + io_bottom_ramL.f2a_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + io_bottom_ramL.lclk[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_ramL.lreset[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_ramL.lclk[8] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_ramL.lreset[8] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + io_bottom_ramL.lclk[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_ramL.lreset[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_ramL.lclk[9] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_ramL.lreset[9] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom_ramL.lclk[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_ramL.lreset[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_ramL.lclk[10] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_ramL.lreset[10] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + io_bottom_ramL.lclk[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_ramL.lreset[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_ramL.lclk[11] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_ramL.lreset[11] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + io_bottom_ramL.lclk[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottom_ramL.lreset[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + io_bottom_ramL.lclk[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottom_ramL.lreset[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + + io_bottom_ramL.lclk[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottom_ramL.lreset[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + io_bottom_ramL.lclk[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottom_ramL.lreset[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + io_bottom_ramL.lclk[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottom_ramL.lreset[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + io_bottom_ramL.lclk[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottom_ramL.lreset[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + io_bottom_ramL.lclk[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottom_ramL.lreset[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + io_bottom_ramL.lclk[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + io_bottom_ramL.lreset[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 + + + l1.W2 l2.W1 l4.W3 + + + l1.W3 l3.W5 l8.W7 + + + l1.W4 l3.W8 l8.W15 + + + l1.N5 l1.N6 l3.N11 + + + l1.N7 l2.N3 l4.N7 + + + l1.N8 l3.N14 l8.N7 + + + l1.N9 l3.N17 l8.N15 + + + l1.E10 l1.E11 l3.E20 + + + l1.E12 l2.E5 l4.E11 + + + l1.E0 l3.E23 l8.E7 + + + l1.E1 l3.E2 l8.E15 + + + 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dsp.q_o[1] + + + l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 dsp.q_o[9] + + + l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 dsp.q_o[17] OG_6 l1.W6 + + + l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 dsp.q_o[2] OG_6 l1.S8 + + + l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 dsp.q_o[10] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 dsp.q_o[18] OG_0 + + + l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 dsp.q_o[3] + + + l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 dsp.q_o[11] + + + l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 dsp.q_o[19] + + + l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 dsp.q_o[4] + + + l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 dsp.q_o[12] OG_2 l1.S6 + + + l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 dsp.q_o[20] OG_2 l1.E0 + + + l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 dsp.q_o[5] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 dsp.q_o[13] OG_4 + + + l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 dsp.q_o[21] + + + l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 dsp.q_o[6] + + + l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 dsp.q_o[14] + + + l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 dsp.q_o[22] + + + l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 dsp.q_o[7] OG_6 l1.E2 + + + l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 dsp.q_o[15] OG_6 l1.W3 + + + l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 dsp.q_o[23] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 dsp.q_o[0] OG_0 + + + l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 dsp.q_o[8] + + + l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 dsp.q_o[16] + + + l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 dsp.q_o[1] + + + l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 dsp.q_o[9] + + + l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 dsp.q_o[17] OG_2 l1.W12 + + + l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 dsp.q_o[2] OG_2 l1.W4 + + + l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 dsp.q_o[10] OG_3 l1.N10 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 dsp.q_o[18] OG_4 + + + l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 dsp.q_o[3] + + + l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 dsp.q_o[11] + + + l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 dsp.q_o[19] + + + dsp.q_o[17] dsp.q_o[0] dsp.q_o[8] dsp.q_o[9] + + + dsp.q_o[17] dsp.q_o[0] dsp.q_o[1] dsp.q_o[8] + + + dsp.q_o[16] dsp.q_o[0] dsp.q_o[1] dsp.q_o[9] + + + dsp.q_o[16] dsp.q_o[1] dsp.q_o[8] dsp.q_o[9] + + + dsp.q_o[19] dsp.q_o[2] dsp.q_o[10] dsp.q_o[11] + + + dsp.q_o[19] dsp.q_o[2] dsp.q_o[3] dsp.q_o[10] + + + dsp.q_o[18] dsp.q_o[2] dsp.q_o[3] dsp.q_o[11] + + + dsp.q_o[18] dsp.q_o[3] dsp.q_o[10] dsp.q_o[11] + + + dsp.q_o[21] dsp.q_o[4] dsp.q_o[12] dsp.q_o[13] + + + dsp.q_o[21] dsp.q_o[4] dsp.q_o[5] dsp.q_o[12] + + + dsp.q_o[20] dsp.q_o[4] dsp.q_o[5] dsp.q_o[13] + + + dsp.q_o[20] dsp.q_o[5] dsp.q_o[12] dsp.q_o[13] + + + dsp.q_o[23] dsp.q_o[6] dsp.q_o[14] dsp.q_o[15] + + + dsp.q_o[23] dsp.q_o[6] dsp.q_o[7] dsp.q_o[14] + + + dsp.q_o[22] dsp.q_o[6] dsp.q_o[7] dsp.q_o[15] + + + dsp.q_o[22] dsp.q_o[7] dsp.q_o[14] dsp.q_o[15] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 mux_15 + + + l1.N0 + mux_16 mux_21 mux_11 mux_14 + + + l1.E0 + mux_32 mux_6 mux_9 mux_31 + + + l1.S0 + mux_48 mux_22 mux_27 mux_13 + + + l1.W1 + mux_64 mux_7 mux_25 mux_30 + + + l1.N1 + mux_80 mux_23 mux_26 mux_29 + + + l1.E1 + mux_1 mux_4 mux_42 mux_47 + + + l1.S1 + mux_17 mux_20 mux_43 mux_46 + + + l1.W2 + mux_33 mux_38 mux_8 mux_63 + + + l1.N2 + mux_49 mux_54 mux_59 mux_12 + + + l1.E2 + mux_65 mux_39 mux_24 mux_62 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.W3 + mux_2 mux_36 mux_41 mux_79 + + + l1.N3 + mux_18 mux_52 mux_75 mux_45 + + + l1.E3 + mux_34 mux_37 mux_40 mux_95 + + + l1.S3 + mux_50 mux_53 mux_91 mux_44 + + + l1.W4 + mux_66 mux_71 mux_56 mux_61 + + + l1.N4 + mux_82 mux_87 mux_57 mux_60 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.S4 + mux_19 mux_84 mux_74 mux_77 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.N5 + mux_51 mux_85 mux_90 mux_76 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.S5 + mux_83 mux_86 mux_89 mux_92 + + + l1.W6 + mux_96 mux_101 mux_106 mux_111 + + + l1.N6 + mux_112 mux_117 mux_107 mux_110 + + + l1.E6 + mux_0 mux_102 mux_105 mux_127 + + + l1.S6 + mux_16 mux_118 mux_123 mux_109 + + + l1.W7 + mux_32 mux_103 mux_121 mux_126 + + + l1.N7 + mux_48 mux_119 mux_122 mux_125 + + + l1.E7 + mux_97 mux_100 mux_10 mux_15 + + + l1.S7 + mux_113 mux_116 mux_11 mux_14 + + + l1.W8 + mux_1 mux_6 mux_104 mux_31 + + + l1.N8 + mux_17 mux_22 mux_27 mux_108 + + + l1.E8 + mux_33 mux_7 mux_120 mux_30 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.W0 + mux_98 mux_4 mux_9 mux_47 + + + l2.N0 + mux_114 mux_20 mux_43 mux_13 + + + l2.E0 + mux_2 mux_5 mux_8 mux_63 + + + l2.S0 + mux_18 mux_21 mux_59 mux_12 + + + l2.W2 + mux_34 mux_39 mux_24 mux_29 + + + l2.N2 + mux_50 mux_55 mux_25 mux_28 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.S2 + mux_115 mux_52 mux_42 mux_45 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.N4 + mux_19 mux_53 mux_58 mux_44 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l2.S4 + mux_51 mux_54 mux_57 mux_60 + + + l3.W0 + mux_64 mux_69 mux_74 mux_79 + + + l3.N0 + mux_80 mux_85 mux_75 mux_78 + + + l3.E0 + mux_96 mux_70 mux_73 mux_95 + + + l3.S0 + mux_112 mux_86 mux_91 mux_77 + + + l3.W3 + mux_0 mux_71 mux_89 mux_94 + + + l3.N3 + mux_16 mux_87 mux_90 mux_93 + + + l3.E3 + mux_65 mux_68 mux_106 mux_111 + + + l3.S3 + mux_81 mux_84 mux_107 mux_110 + + + l3.W6 + mux_97 mux_102 mux_72 mux_127 + + + l3.N6 + mux_113 mux_118 mux_123 mux_76 + + + l3.E6 + mux_1 mux_103 mux_88 mux_126 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.W9 + mux_66 mux_100 mux_105 mux_15 + + + l3.N9 + mux_82 mux_116 mux_11 mux_109 + + + l3.E9 + mux_98 mux_101 mux_104 mux_31 + + + l3.S9 + mux_114 mux_117 mux_27 mux_108 + + + l3.W12 + mux_2 mux_7 mux_120 mux_125 + + + l3.N12 + mux_18 mux_23 mux_121 mux_124 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.S12 + mux_83 mux_20 mux_10 mux_13 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.N15 + mux_115 mux_21 mux_26 mux_12 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.S15 + mux_19 mux_22 mux_25 mux_28 + + + l3.W18 + mux_32 mux_37 mux_42 mux_47 + + + l3.N18 + mux_48 mux_53 mux_43 mux_46 + + + l3.E18 + mux_64 mux_38 mux_41 mux_63 + + + l3.S18 + mux_80 mux_54 mux_59 mux_45 + + + l3.W21 + mux_96 mux_39 mux_57 mux_62 + + + l3.N21 + mux_112 mux_55 mux_58 mux_61 + + + l3.E21 + mux_33 mux_36 mux_74 mux_79 + + + l3.S21 + mux_49 mux_52 mux_75 mux_78 + + + l4.W0 + mux_65 mux_70 mux_40 mux_95 + + + l4.N0 + mux_81 mux_86 mux_91 mux_44 + + + l4.E0 + mux_97 mux_71 mux_56 mux_94 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.W4 + mux_34 mux_68 mux_73 mux_111 + + + l4.N4 + mux_50 mux_84 mux_107 mux_77 + + + l4.E4 + mux_66 mux_69 mux_72 mux_127 + + + l4.S4 + mux_82 mux_85 mux_123 mux_76 + + + l4.W8 + mux_98 mux_103 mux_88 mux_93 + + + l4.N8 + mux_114 mux_119 mux_89 mux_92 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.S8 + mux_51 mux_116 mux_106 mux_109 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.N12 + mux_83 mux_117 mux_122 mux_108 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l4.S12 + mux_115 mux_118 mux_121 mux_124 + + + l8.W0 + mux_0 mux_5 mux_10 mux_15 + + + l8.N0 + mux_16 mux_21 mux_11 mux_14 + + + l8.E0 + mux_32 mux_6 mux_9 mux_31 + + + l8.S0 + mux_48 mux_22 mux_27 mux_13 + + + l8.W8 + mux_64 mux_7 mux_25 mux_30 + + + l8.N8 + mux_80 mux_23 mux_26 mux_29 + + + l8.E8 + mux_1 mux_4 mux_42 mux_47 + + + l8.S8 + mux_17 mux_20 mux_43 mux_46 + + + l1.W9 + l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N9 + l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E9 + l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S9 + l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W10 + l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N10 + l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E10 + l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S10 + l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W11 + l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.N11 + l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E11 + l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S11 + l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.W12 + l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N12 + l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E12 + l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S12 + l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + dsp.a[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + dsp.a[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + dsp.a[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + dsp.a[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + dsp.a[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + dsp.a[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + dsp.a[6] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + dsp.a[7] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + dsp.a[8] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + dsp.a[9] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + dsp.a[10] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + dsp.a[11] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + dsp.b[0] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + dsp.b[1] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + dsp.b[2] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + dsp.b[3] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + dsp.b[4] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + dsp.b[5] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + dsp.b[6] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + dsp.b[7] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + dsp.b[8] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + dsp.b[9] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + dsp.lclk[0] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + dsp.lreset[0] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + dsp.a[24] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + dsp.a[25] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + dsp.a[26] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + dsp.a[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + dsp.a[28] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + dsp.a[29] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + dsp.a[30] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + dsp.a[31] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + dsp.a[32] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + dsp.a[33] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + dsp.a[34] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + dsp.a[35] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + dsp.b[20] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + dsp.b[21] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + dsp.b[22] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + dsp.b[23] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + dsp.b[24] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + dsp.b[25] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + dsp.b[26] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + dsp.b[27] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + dsp.b[28] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + dsp.b[29] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + dsp.a[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + dsp.a[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + dsp.a[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + dsp.a[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + dsp.a[4] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + dsp.a[5] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + dsp.a[6] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + dsp.a[7] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + dsp.a[8] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + dsp.a[9] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + dsp.a[10] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + dsp.a[11] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + dsp.b[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + dsp.b[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 dsp.q_o[32] + + + l1.W2 l2.W1 l4.W3 dsp.q_o[24] + + + l1.W3 l3.W5 l8.W7 dsp.q_o[40] + + + l1.W4 l3.W8 l8.W15 + + + l1.N5 l1.N6 l3.N11 dsp.q_o[33] + + + l1.N7 l2.N3 l4.N7 dsp.q_o[25] + + + l1.N8 l3.N14 l8.N7 dsp.q_o[41] + + + l1.N9 l3.N17 l8.N15 + + + l1.E10 l1.E11 l3.E20 dsp.q_o[34] + + + l1.E12 l2.E5 l4.E11 dsp.q_o[26] + + + l1.E0 l3.E23 l8.E7 dsp.q_o[42] + + + l1.E1 l3.E2 l8.E15 + + + l1.S2 l1.S3 l3.S5 dsp.q_o[35] + + + l1.S4 l2.S1 l4.S15 dsp.q_o[27] + + + l1.S5 l3.S8 l8.S7 dsp.q_o[43] + + + l1.S6 l3.S11 l8.S15 + + + l1.W7 l1.W8 l3.W14 dsp.q_o[36] + + + l1.W9 l2.W3 l4.W3 dsp.q_o[28] + + + l1.W10 l3.W17 l8.W7 dsp.q_o[24] + + + l1.W11 l3.W20 l8.W15 + + + l1.N12 l1.N0 l3.N23 dsp.q_o[37] + + + l1.N1 l2.N5 l4.N7 dsp.q_o[29] + + + l1.N2 l3.N2 l8.N7 dsp.q_o[25] + + + l1.N3 l3.N5 l8.N15 + + + l1.E4 l1.E5 l3.E8 dsp.q_o[38] + + + l1.E6 l2.E1 l4.E11 dsp.q_o[30] + + + l1.E7 l3.E11 l8.E7 dsp.q_o[26] + + + l1.E8 l3.E14 l8.E15 + + + l1.S9 l1.S10 l3.S17 dsp.q_o[39] + + + l1.S11 l2.S3 l4.S15 dsp.q_o[31] + + + l1.S12 l3.S20 l8.S7 dsp.q_o[27] + + + l1.S0 l3.S23 l8.S15 + + + l1.W1 l1.W2 l3.W2 dsp.q_o[32] + + + l1.W3 l2.W5 l4.W3 dsp.q_o[24] + + + l1.W4 l3.W5 l8.W7 dsp.q_o[40] + + + l1.W5 l3.W8 l8.W15 + + + l1.N6 l1.N7 l3.N11 dsp.q_o[33] + + + l1.N8 l2.N1 l4.N7 dsp.q_o[25] + + + l1.N9 l3.N14 l8.N7 dsp.q_o[41] + + + l1.N10 l3.N17 l8.N15 + + + l1.E11 l1.E12 l3.E20 dsp.q_o[34] + + + l1.E0 l2.E3 l4.E11 dsp.q_o[26] + + + l1.E1 l3.E23 l8.E7 dsp.q_o[42] + + + l1.E2 l3.E2 l8.E15 + + + l1.S3 l1.S4 l3.S5 dsp.q_o[35] + + + l1.S5 l2.S5 l4.S15 dsp.q_o[27] + + + l1.S6 l3.S8 l8.S7 dsp.q_o[43] + + + l1.S7 l3.S11 l8.S15 + + + l1.W8 l1.W9 l3.W14 dsp.q_o[36] + + + l1.W10 l2.W1 l4.W3 dsp.q_o[28] + + + l1.W11 l3.W17 l8.W7 dsp.q_o[24] + + + l1.W12 l3.W20 l8.W15 + + + l1.N0 l1.N1 l3.N23 dsp.q_o[37] + + + l1.N2 l2.N3 l4.N7 dsp.q_o[29] + + + l1.N3 l3.N2 l8.N7 dsp.q_o[25] + + + l1.N4 l3.N5 l8.N15 + + + l1.E5 l1.E6 l3.E8 dsp.q_o[38] + + + l1.E7 l2.E5 l4.E11 dsp.q_o[30] + + + l1.E8 l3.E11 l8.E7 dsp.q_o[26] + + + l1.E9 l3.E14 l8.E15 + + + l1.S10 l1.S11 l3.S17 dsp.q_o[39] + + + l1.S12 l2.S1 l4.S15 dsp.q_o[31] + + + l1.S0 l3.S20 l8.S7 dsp.q_o[27] + + + l1.S1 l3.S23 l8.S15 + + + l1.W2 l1.W3 l3.W2 dsp.q_o[32] + + + l1.W4 l2.W3 l4.W3 dsp.q_o[24] + + + l1.W5 l3.W5 l8.W7 dsp.q_o[40] + + + l1.W6 l3.W8 l8.W15 + + + l1.N7 l1.N8 l3.N11 dsp.q_o[33] + + + l1.N9 l2.N5 l4.N7 dsp.q_o[25] + + + l1.N10 l3.N14 l8.N7 dsp.q_o[41] + + + l1.N11 l3.N17 l8.N15 + + + l1.E12 l1.E0 l3.E20 dsp.q_o[34] + + + l1.E1 l2.E1 l4.E11 dsp.q_o[26] + + + l1.E2 l3.E23 l8.E7 dsp.q_o[42] + + + l1.E3 l3.E2 l8.E15 + + + l1.S4 l1.S5 l3.S5 dsp.q_o[35] + + + l1.S6 l2.S3 l4.S15 dsp.q_o[27] + + + l1.S7 l3.S8 l8.S7 dsp.q_o[43] + + + l1.S8 l3.S11 l8.S15 + + + l1.W9 l1.W10 l3.W14 dsp.q_o[36] + + + l1.W11 l2.W5 l4.W3 dsp.q_o[28] + + + l1.W12 l3.W17 l8.W7 dsp.q_o[24] + + + l1.W0 l3.W20 l8.W15 + + + l1.N1 l1.N2 l3.N23 dsp.q_o[37] + + + l1.N3 l2.N1 l4.N7 dsp.q_o[29] + + + l1.N4 l3.N2 l8.N7 dsp.q_o[25] + + + l1.N5 l3.N5 l8.N15 + + + l1.E6 l1.E7 l3.E8 dsp.q_o[38] + + + l1.E8 l2.E3 l4.E11 dsp.q_o[30] + + + l1.E9 l3.E11 l8.E7 dsp.q_o[26] + + + l1.E10 l3.E14 l8.E15 + + + l1.S11 l1.S12 l3.S17 dsp.q_o[39] + + + l1.S0 l2.S5 l4.S15 dsp.q_o[31] + + + l1.S1 l3.S20 l8.S7 dsp.q_o[27] + + + l1.S2 l3.S23 l8.S15 + + + l1.W3 l1.W4 l3.W2 dsp.q_o[32] + + + l1.W5 l2.W1 l4.W3 dsp.q_o[24] + + + l1.W6 l3.W5 l8.W7 dsp.q_o[40] + + + l1.W7 l3.W8 l8.W15 + + + l1.N8 l1.N9 l3.N11 dsp.q_o[33] + + + l1.N10 l2.N3 l4.N7 dsp.q_o[25] + + + l1.N11 l3.N14 l8.N7 dsp.q_o[41] + + + l1.N12 l3.N17 l8.N15 + + + l1.E0 l1.E1 l3.E20 dsp.q_o[34] + + + l1.E2 l2.E5 l4.E11 dsp.q_o[26] + + + l1.E3 l3.E23 l8.E7 dsp.q_o[42] + + + l1.E4 l3.E2 l8.E15 + + + l1.S5 l1.S6 l3.S5 dsp.q_o[35] + + + l1.S7 l2.S1 l4.S15 dsp.q_o[27] + + + l1.S8 l3.S8 l8.S7 dsp.q_o[43] + + + l1.S9 l3.S11 l8.S15 + + + l1.W10 l1.W11 l3.W14 dsp.q_o[36] + + + l1.W12 l2.W3 l4.W3 dsp.q_o[28] + + + l1.W0 l3.W17 l8.W7 dsp.q_o[24] + + + l1.W1 l3.W20 l8.W15 + + + l1.N2 l1.N3 l3.N23 dsp.q_o[37] + + + l1.N4 l2.N5 l4.N7 dsp.q_o[29] + + + l1.N5 l3.N2 l8.N7 dsp.q_o[25] + + + l1.N6 l3.N5 l8.N15 + + + l1.E7 l1.E8 l3.E8 dsp.q_o[38] + + + l1.E9 l2.E1 l4.E11 dsp.q_o[30] + + + l1.E10 l3.E11 l8.E7 dsp.q_o[26] + + + l1.E11 l3.E14 l8.E15 + + + l1.S12 l1.S0 l3.S17 dsp.q_o[39] + + + l1.S1 l2.S3 l4.S15 dsp.q_o[31] + + + l1.S2 l3.S20 l8.S7 dsp.q_o[27] + + + l1.S3 l3.S23 l8.S15 + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 dsp.q_o[24] OG_0 + + + l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 dsp.q_o[32] + + + l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 dsp.q_o[40] + + + l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 dsp.q_o[25] + + + l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 dsp.q_o[33] + + + l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 dsp.q_o[41] OG_2 l1.N2 + + + l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 dsp.q_o[26] OG_2 l1.S4 + + + l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 dsp.q_o[34] OG_3 l1.N9 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 dsp.q_o[42] OG_4 + + + l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 dsp.q_o[27] + + + l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 dsp.q_o[35] + + + l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 dsp.q_o[43] + + + l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 dsp.q_o[28] + + + l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 dsp.q_o[36] OG_6 l1.E5 + + + l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 dsp.q_o[24] OG_6 l1.S4 + + + l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 dsp.q_o[29] OG_7 l1.N0 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 dsp.q_o[37] OG_0 + + + l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 dsp.q_o[25] + + + l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 dsp.q_o[30] + + + l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 dsp.q_o[38] + + + l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 dsp.q_o[26] + + + l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 dsp.q_o[31] OG_2 l1.E0 + + + l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 dsp.q_o[39] OG_2 l1.N10 + + + l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 dsp.q_o[27] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 dsp.q_o[24] OG_4 + + + l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 dsp.q_o[32] + + + l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 dsp.q_o[40] + + + l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 dsp.q_o[25] + + + l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 dsp.q_o[33] + + + l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 dsp.q_o[41] OG_6 l1.W6 + + + l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 dsp.q_o[26] OG_6 l1.S8 + + + l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 dsp.q_o[34] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 dsp.q_o[42] OG_0 + + + l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 dsp.q_o[27] + + + l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 dsp.q_o[35] + + + l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 dsp.q_o[43] + + + l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 dsp.q_o[28] + + + l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 dsp.q_o[36] OG_2 l1.S6 + + + l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 dsp.q_o[24] OG_2 l1.E0 + + + l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 dsp.q_o[29] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 dsp.q_o[37] OG_4 + + + l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 dsp.q_o[25] + + + l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 dsp.q_o[30] + + + l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 dsp.q_o[38] + + + l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 dsp.q_o[26] + + + l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 dsp.q_o[31] OG_6 l1.E2 + + + l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 dsp.q_o[39] OG_6 l1.W3 + + + l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 dsp.q_o[27] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 dsp.q_o[24] OG_0 + + + l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 dsp.q_o[32] + + + l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 dsp.q_o[40] + + + l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 dsp.q_o[25] + + + l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 dsp.q_o[33] + + + l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 dsp.q_o[41] OG_2 l1.W12 + + + l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 dsp.q_o[26] OG_2 l1.W4 + + + l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 dsp.q_o[34] OG_3 l1.N10 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 dsp.q_o[42] OG_4 + + + l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 dsp.q_o[27] + + + l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 dsp.q_o[35] + + + l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 dsp.q_o[43] + + + dsp.q_o[41] dsp.q_o[24] dsp.q_o[32] dsp.q_o[33] + + + dsp.q_o[41] dsp.q_o[24] dsp.q_o[25] dsp.q_o[32] + + + dsp.q_o[40] dsp.q_o[24] dsp.q_o[25] dsp.q_o[33] + + + dsp.q_o[40] dsp.q_o[25] dsp.q_o[32] dsp.q_o[33] + + + dsp.q_o[43] dsp.q_o[26] dsp.q_o[34] dsp.q_o[35] + + + dsp.q_o[43] dsp.q_o[26] dsp.q_o[27] dsp.q_o[34] + + + dsp.q_o[42] dsp.q_o[26] dsp.q_o[27] dsp.q_o[35] + + + dsp.q_o[42] dsp.q_o[27] dsp.q_o[34] dsp.q_o[35] + + + dsp.q_o[25] dsp.q_o[28] dsp.q_o[36] dsp.q_o[37] + + + dsp.q_o[25] dsp.q_o[28] dsp.q_o[29] dsp.q_o[36] + + + dsp.q_o[24] dsp.q_o[28] dsp.q_o[29] dsp.q_o[37] + + + dsp.q_o[24] dsp.q_o[29] dsp.q_o[36] dsp.q_o[37] + + + dsp.q_o[27] dsp.q_o[30] dsp.q_o[38] dsp.q_o[39] + + + dsp.q_o[27] dsp.q_o[30] dsp.q_o[31] dsp.q_o[38] + + + dsp.q_o[26] dsp.q_o[30] dsp.q_o[31] dsp.q_o[39] + + + dsp.q_o[26] dsp.q_o[31] dsp.q_o[38] dsp.q_o[39] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 mux_15 + + + l1.N0 + mux_16 mux_21 mux_11 mux_14 + + + l1.E0 + mux_32 mux_6 mux_9 mux_31 + + + l1.S0 + mux_48 mux_22 mux_27 mux_13 + + + l1.W1 + mux_64 mux_7 mux_25 mux_30 + + + l1.N1 + mux_80 mux_23 mux_26 mux_29 + + + l1.E1 + mux_1 mux_4 mux_42 mux_47 + + + l1.S1 + mux_17 mux_20 mux_43 mux_46 + + + l1.W2 + mux_33 mux_38 mux_8 mux_63 + + + l1.N2 + mux_49 mux_54 mux_59 mux_12 + + + l1.E2 + mux_65 mux_39 mux_24 mux_62 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.W3 + mux_2 mux_36 mux_41 mux_79 + + + l1.N3 + mux_18 mux_52 mux_75 mux_45 + + + l1.E3 + mux_34 mux_37 mux_40 mux_95 + + + l1.S3 + mux_50 mux_53 mux_91 mux_44 + + + l1.W4 + mux_66 mux_71 mux_56 mux_61 + + + l1.N4 + mux_82 mux_87 mux_57 mux_60 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.S4 + mux_19 mux_84 mux_74 mux_77 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.N5 + mux_51 mux_85 mux_90 mux_76 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.S5 + mux_83 mux_86 mux_89 mux_92 + + + l1.W6 + mux_96 mux_101 mux_106 mux_111 + + + l1.N6 + mux_112 mux_117 mux_107 mux_110 + + + l1.E6 + mux_0 mux_102 mux_105 mux_127 + + + l1.S6 + mux_16 mux_118 mux_123 mux_109 + + + l1.W7 + mux_32 mux_103 mux_121 mux_126 + + + l1.N7 + mux_48 mux_119 mux_122 mux_125 + + + l1.E7 + mux_97 mux_100 mux_10 mux_15 + + + l1.S7 + mux_113 mux_116 mux_11 mux_14 + + + l1.W8 + mux_1 mux_6 mux_104 mux_31 + + + l1.N8 + mux_17 mux_22 mux_27 mux_108 + + + l1.E8 + mux_33 mux_7 mux_120 mux_30 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.W0 + mux_98 mux_4 mux_9 mux_47 + + + l2.N0 + mux_114 mux_20 mux_43 mux_13 + + + l2.E0 + mux_2 mux_5 mux_8 mux_63 + + + l2.S0 + mux_18 mux_21 mux_59 mux_12 + + + l2.W2 + mux_34 mux_39 mux_24 mux_29 + + + l2.N2 + mux_50 mux_55 mux_25 mux_28 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.S2 + mux_115 mux_52 mux_42 mux_45 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.N4 + mux_19 mux_53 mux_58 mux_44 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l2.S4 + mux_51 mux_54 mux_57 mux_60 + + + l3.W0 + mux_64 mux_69 mux_74 mux_79 + + + l3.N0 + mux_80 mux_85 mux_75 mux_78 + + + l3.E0 + mux_96 mux_70 mux_73 mux_95 + + + l3.S0 + mux_112 mux_86 mux_91 mux_77 + + + l3.W3 + mux_0 mux_71 mux_89 mux_94 + + + l3.N3 + mux_16 mux_87 mux_90 mux_93 + + + l3.E3 + mux_65 mux_68 mux_106 mux_111 + + + l3.S3 + mux_81 mux_84 mux_107 mux_110 + + + l3.W6 + mux_97 mux_102 mux_72 mux_127 + + + l3.N6 + mux_113 mux_118 mux_123 mux_76 + + + l3.E6 + mux_1 mux_103 mux_88 mux_126 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.W9 + mux_66 mux_100 mux_105 mux_15 + + + l3.N9 + mux_82 mux_116 mux_11 mux_109 + + + l3.E9 + mux_98 mux_101 mux_104 mux_31 + + + l3.S9 + mux_114 mux_117 mux_27 mux_108 + + + l3.W12 + mux_2 mux_7 mux_120 mux_125 + + + l3.N12 + mux_18 mux_23 mux_121 mux_124 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.S12 + mux_83 mux_20 mux_10 mux_13 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.N15 + mux_115 mux_21 mux_26 mux_12 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.S15 + mux_19 mux_22 mux_25 mux_28 + + + l3.W18 + mux_32 mux_37 mux_42 mux_47 + + + l3.N18 + mux_48 mux_53 mux_43 mux_46 + + + l3.E18 + mux_64 mux_38 mux_41 mux_63 + + + l3.S18 + mux_80 mux_54 mux_59 mux_45 + + + l3.W21 + mux_96 mux_39 mux_57 mux_62 + + + l3.N21 + mux_112 mux_55 mux_58 mux_61 + + + l3.E21 + mux_33 mux_36 mux_74 mux_79 + + + l3.S21 + mux_49 mux_52 mux_75 mux_78 + + + l4.W0 + mux_65 mux_70 mux_40 mux_95 + + + l4.N0 + mux_81 mux_86 mux_91 mux_44 + + + l4.E0 + mux_97 mux_71 mux_56 mux_94 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.W4 + mux_34 mux_68 mux_73 mux_111 + + + l4.N4 + mux_50 mux_84 mux_107 mux_77 + + + l4.E4 + mux_66 mux_69 mux_72 mux_127 + + + l4.S4 + mux_82 mux_85 mux_123 mux_76 + + + l4.W8 + mux_98 mux_103 mux_88 mux_93 + + + l4.N8 + mux_114 mux_119 mux_89 mux_92 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.S8 + mux_51 mux_116 mux_106 mux_109 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.N12 + mux_83 mux_117 mux_122 mux_108 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l4.S12 + mux_115 mux_118 mux_121 mux_124 + + + l8.W0 + mux_0 mux_5 mux_10 mux_15 + + + l8.N0 + mux_16 mux_21 mux_11 mux_14 + + + l8.E0 + mux_32 mux_6 mux_9 mux_31 + + + l8.S0 + mux_48 mux_22 mux_27 mux_13 + + + l8.W8 + mux_64 mux_7 mux_25 mux_30 + + + l8.N8 + mux_80 mux_23 mux_26 mux_29 + + + l8.E8 + mux_1 mux_4 mux_42 mux_47 + + + l8.S8 + mux_17 mux_20 mux_43 mux_46 + + + l1.W9 + l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N9 + l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E9 + l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S9 + l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W10 + l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N10 + l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E10 + l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S10 + l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W11 + l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.N11 + l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E11 + l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S11 + l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.W12 + l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N12 + l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E12 + l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S12 + l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + dsp.a[36] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + dsp.a[37] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + dsp.a[38] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + dsp.a[39] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + dsp.a[40] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + dsp.a[41] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + dsp.a[42] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + dsp.a[43] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + dsp.a[44] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + dsp.a[45] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + dsp.a[46] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + dsp.a[47] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + dsp.b[30] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + dsp.b[31] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + dsp.b[32] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + dsp.b[33] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + dsp.b[34] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + dsp.b[35] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + dsp.b[36] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + dsp.b[37] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + dsp.b[38] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + dsp.b[39] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + dsp.a[12] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + dsp.a[13] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + dsp.a[14] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + dsp.a[15] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + dsp.a[16] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + dsp.a[17] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + dsp.a[18] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + dsp.a[19] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + dsp.a[20] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + dsp.a[21] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + dsp.a[22] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + dsp.a[23] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + dsp.b[10] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + dsp.b[11] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + dsp.b[12] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + dsp.b[13] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + dsp.b[14] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + dsp.b[15] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + dsp.b[16] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + dsp.b[17] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + dsp.b[18] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + dsp.b[19] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + dsp.a[36] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + dsp.a[37] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + dsp.a[38] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + dsp.a[39] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + dsp.a[40] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + dsp.a[41] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + dsp.a[42] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + dsp.a[43] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + dsp.a[44] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + dsp.a[45] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + dsp.a[46] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + dsp.a[47] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + dsp.b[30] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + dsp.b[31] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + dsp.b[32] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + dsp.b[33] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 ram9k.q_o[8] + + + l1.W2 l2.W1 l4.W3 ram9k.q_o[0] + + + l1.W3 l3.W5 l8.W7 ram9k.q_o[16] + + + l1.W4 l3.W8 l8.W15 + + + l1.N5 l1.N6 l3.N11 ram9k.q_o[9] + + + l1.N7 l2.N3 l4.N7 ram9k.q_o[1] + + + l1.N8 l3.N14 l8.N7 ram9k.q_o[17] + + + l1.N9 l3.N17 l8.N15 + + + l1.E10 l1.E11 l3.E20 ram9k.q_o[10] + + + l1.E12 l2.E5 l4.E11 ram9k.q_o[2] + + + l1.E0 l3.E23 l8.E7 ram9k.q_o[18] + + + l1.E1 l3.E2 l8.E15 + + + l1.S2 l1.S3 l3.S5 ram9k.q_o[11] + + + l1.S4 l2.S1 l4.S15 ram9k.q_o[3] + + + l1.S5 l3.S8 l8.S7 ram9k.q_o[19] + + + l1.S6 l3.S11 l8.S15 + + + l1.W7 l1.W8 l3.W14 ram9k.q_o[12] + + + l1.W9 l2.W3 l4.W3 ram9k.q_o[4] + + + l1.W10 l3.W17 l8.W7 ram9k.q_o[20] + + + l1.W11 l3.W20 l8.W15 + + + l1.N12 l1.N0 l3.N23 ram9k.q_o[13] + + + l1.N1 l2.N5 l4.N7 ram9k.q_o[5] + + + l1.N2 l3.N2 l8.N7 ram9k.q_o[21] + + + l1.N3 l3.N5 l8.N15 + + + l1.E4 l1.E5 l3.E8 ram9k.q_o[14] + + + l1.E6 l2.E1 l4.E11 ram9k.q_o[6] + + + l1.E7 l3.E11 l8.E7 ram9k.q_o[22] + + + l1.E8 l3.E14 l8.E15 + + + l1.S9 l1.S10 l3.S17 ram9k.q_o[15] + + + l1.S11 l2.S3 l4.S15 ram9k.q_o[7] + + + l1.S12 l3.S20 l8.S7 ram9k.q_o[23] + + + l1.S0 l3.S23 l8.S15 + + + l1.W1 l1.W2 l3.W2 ram9k.q_o[8] + + + l1.W3 l2.W5 l4.W3 ram9k.q_o[0] + + + l1.W4 l3.W5 l8.W7 ram9k.q_o[16] + + + l1.W5 l3.W8 l8.W15 + + + l1.N6 l1.N7 l3.N11 ram9k.q_o[9] + + + l1.N8 l2.N1 l4.N7 ram9k.q_o[1] + + + l1.N9 l3.N14 l8.N7 ram9k.q_o[17] + + + l1.N10 l3.N17 l8.N15 + + + l1.E11 l1.E12 l3.E20 ram9k.q_o[10] + + + l1.E0 l2.E3 l4.E11 ram9k.q_o[2] + + + l1.E1 l3.E23 l8.E7 ram9k.q_o[18] + + + l1.E2 l3.E2 l8.E15 + + + l1.S3 l1.S4 l3.S5 ram9k.q_o[11] + + + l1.S5 l2.S5 l4.S15 ram9k.q_o[3] + + + l1.S6 l3.S8 l8.S7 ram9k.q_o[19] + + + l1.S7 l3.S11 l8.S15 + + + l1.W8 l1.W9 l3.W14 ram9k.q_o[12] + + + l1.W10 l2.W1 l4.W3 ram9k.q_o[4] + + + l1.W11 l3.W17 l8.W7 ram9k.q_o[20] + + + l1.W12 l3.W20 l8.W15 + + + l1.N0 l1.N1 l3.N23 ram9k.q_o[13] + + + l1.N2 l2.N3 l4.N7 ram9k.q_o[5] + + + l1.N3 l3.N2 l8.N7 ram9k.q_o[21] + + + l1.N4 l3.N5 l8.N15 + + + l1.E5 l1.E6 l3.E8 ram9k.q_o[14] + + + l1.E7 l2.E5 l4.E11 ram9k.q_o[6] + + + l1.E8 l3.E11 l8.E7 ram9k.q_o[22] + + + l1.E9 l3.E14 l8.E15 + + + l1.S10 l1.S11 l3.S17 ram9k.q_o[15] + + + l1.S12 l2.S1 l4.S15 ram9k.q_o[7] + + + l1.S0 l3.S20 l8.S7 ram9k.q_o[23] + + + l1.S1 l3.S23 l8.S15 + + + l1.W2 l1.W3 l3.W2 ram9k.q_o[8] + + + l1.W4 l2.W3 l4.W3 ram9k.q_o[0] + + + l1.W5 l3.W5 l8.W7 ram9k.q_o[16] + + + l1.W6 l3.W8 l8.W15 + + + l1.N7 l1.N8 l3.N11 ram9k.q_o[9] + + + l1.N9 l2.N5 l4.N7 ram9k.q_o[1] + + + l1.N10 l3.N14 l8.N7 ram9k.q_o[17] + + + l1.N11 l3.N17 l8.N15 + + + l1.E12 l1.E0 l3.E20 ram9k.q_o[10] + + + l1.E1 l2.E1 l4.E11 ram9k.q_o[2] + + + l1.E2 l3.E23 l8.E7 ram9k.q_o[18] + + + l1.E3 l3.E2 l8.E15 + + + l1.S4 l1.S5 l3.S5 ram9k.q_o[11] + + + l1.S6 l2.S3 l4.S15 ram9k.q_o[3] + + + l1.S7 l3.S8 l8.S7 ram9k.q_o[19] + + + l1.S8 l3.S11 l8.S15 + + + l1.W9 l1.W10 l3.W14 ram9k.q_o[12] + + + l1.W11 l2.W5 l4.W3 ram9k.q_o[4] + + + l1.W12 l3.W17 l8.W7 ram9k.q_o[20] + + + l1.W0 l3.W20 l8.W15 + + + l1.N1 l1.N2 l3.N23 ram9k.q_o[13] + + + l1.N3 l2.N1 l4.N7 ram9k.q_o[5] + + + l1.N4 l3.N2 l8.N7 ram9k.q_o[21] + + + l1.N5 l3.N5 l8.N15 + + + l1.E6 l1.E7 l3.E8 ram9k.q_o[14] + + + l1.E8 l2.E3 l4.E11 ram9k.q_o[6] + + + l1.E9 l3.E11 l8.E7 ram9k.q_o[22] + + + l1.E10 l3.E14 l8.E15 + + + l1.S11 l1.S12 l3.S17 ram9k.q_o[15] + + + l1.S0 l2.S5 l4.S15 ram9k.q_o[7] + + + l1.S1 l3.S20 l8.S7 ram9k.q_o[23] + + + l1.S2 l3.S23 l8.S15 + + + l1.W3 l1.W4 l3.W2 ram9k.q_o[8] + + + l1.W5 l2.W1 l4.W3 ram9k.q_o[0] + + + l1.W6 l3.W5 l8.W7 ram9k.q_o[16] + + + l1.W7 l3.W8 l8.W15 + + + l1.N8 l1.N9 l3.N11 ram9k.q_o[9] + + + l1.N10 l2.N3 l4.N7 ram9k.q_o[1] + + + l1.N11 l3.N14 l8.N7 ram9k.q_o[17] + + + l1.N12 l3.N17 l8.N15 + + + l1.E0 l1.E1 l3.E20 ram9k.q_o[10] + + + l1.E2 l2.E5 l4.E11 ram9k.q_o[2] + + + l1.E3 l3.E23 l8.E7 ram9k.q_o[18] + + + l1.E4 l3.E2 l8.E15 + + + l1.S5 l1.S6 l3.S5 ram9k.q_o[11] + + + l1.S7 l2.S1 l4.S15 ram9k.q_o[3] + + + l1.S8 l3.S8 l8.S7 ram9k.q_o[19] + + + l1.S9 l3.S11 l8.S15 + + + l1.W10 l1.W11 l3.W14 ram9k.q_o[12] + + + l1.W12 l2.W3 l4.W3 ram9k.q_o[4] + + + l1.W0 l3.W17 l8.W7 ram9k.q_o[20] + + + l1.W1 l3.W20 l8.W15 + + + l1.N2 l1.N3 l3.N23 ram9k.q_o[13] + + + l1.N4 l2.N5 l4.N7 ram9k.q_o[5] + + + l1.N5 l3.N2 l8.N7 ram9k.q_o[21] + + + l1.N6 l3.N5 l8.N15 + + + l1.E7 l1.E8 l3.E8 ram9k.q_o[14] + + + l1.E9 l2.E1 l4.E11 ram9k.q_o[6] + + + l1.E10 l3.E11 l8.E7 ram9k.q_o[22] + + + l1.E11 l3.E14 l8.E15 + + + l1.S12 l1.S0 l3.S17 ram9k.q_o[15] + + + l1.S1 l2.S3 l4.S15 ram9k.q_o[7] + + + l1.S2 l3.S20 l8.S7 ram9k.q_o[23] + + + l1.S3 l3.S23 l8.S15 + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 ram9k.q_o[0] OG_0 + + + l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 ram9k.q_o[8] + + + l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 ram9k.q_o[16] + + + l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 ram9k.q_o[1] + + + l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 ram9k.q_o[9] + + + l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 ram9k.q_o[17] OG_2 l1.N2 + + + l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 ram9k.q_o[2] OG_2 l1.S4 + + + l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 ram9k.q_o[10] OG_3 l1.N9 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 ram9k.q_o[18] OG_4 + + + l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 ram9k.q_o[3] + + + l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 ram9k.q_o[11] + + + l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 ram9k.q_o[19] + + + l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 ram9k.q_o[4] + + + l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 ram9k.q_o[12] OG_6 l1.E5 + + + l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 ram9k.q_o[20] OG_6 l1.S4 + + + l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 ram9k.q_o[5] OG_7 l1.N0 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 ram9k.q_o[13] OG_0 + + + l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 ram9k.q_o[21] + + + l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 ram9k.q_o[6] + + + l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 ram9k.q_o[14] + + + l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 ram9k.q_o[22] + + + l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 ram9k.q_o[7] OG_2 l1.E0 + + + l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 ram9k.q_o[15] OG_2 l1.N10 + + + l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 ram9k.q_o[23] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 ram9k.q_o[0] OG_4 + + + l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 ram9k.q_o[8] + + + l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 ram9k.q_o[16] + + + l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 ram9k.q_o[1] + + + l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 ram9k.q_o[9] + + + l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 ram9k.q_o[17] OG_6 l1.W6 + + + l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 ram9k.q_o[2] OG_6 l1.S8 + + + l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 ram9k.q_o[10] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 ram9k.q_o[18] OG_0 + + + l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 ram9k.q_o[3] + + + l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 ram9k.q_o[11] + + + l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 ram9k.q_o[19] + + + l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 ram9k.q_o[4] + + + l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 ram9k.q_o[12] OG_2 l1.S6 + + + l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 ram9k.q_o[20] OG_2 l1.E0 + + + l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 ram9k.q_o[5] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 ram9k.q_o[13] OG_4 + + + l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 ram9k.q_o[21] + + + l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 ram9k.q_o[6] + + + l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 ram9k.q_o[14] + + + l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 ram9k.q_o[22] + + + l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 ram9k.q_o[7] OG_6 l1.E2 + + + l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 ram9k.q_o[15] OG_6 l1.W3 + + + l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 ram9k.q_o[23] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 ram9k.q_o[0] OG_0 + + + l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 ram9k.q_o[8] + + + l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 ram9k.q_o[16] + + + l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 ram9k.q_o[1] + + + l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 ram9k.q_o[9] + + + l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 ram9k.q_o[17] OG_2 l1.W12 + + + l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 ram9k.q_o[2] OG_2 l1.W4 + + + l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 ram9k.q_o[10] OG_3 l1.N10 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 ram9k.q_o[18] OG_4 + + + l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 ram9k.q_o[3] + + + l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 ram9k.q_o[11] + + + l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 ram9k.q_o[19] + + + ram9k.q_o[17] ram9k.q_o[0] ram9k.q_o[8] ram9k.q_o[9] + + + ram9k.q_o[17] ram9k.q_o[0] ram9k.q_o[1] ram9k.q_o[8] + + + ram9k.q_o[16] ram9k.q_o[0] ram9k.q_o[1] ram9k.q_o[9] + + + ram9k.q_o[16] ram9k.q_o[1] ram9k.q_o[8] ram9k.q_o[9] + + + ram9k.q_o[19] ram9k.q_o[2] ram9k.q_o[10] ram9k.q_o[11] + + + ram9k.q_o[19] ram9k.q_o[2] ram9k.q_o[3] ram9k.q_o[10] + + + ram9k.q_o[18] ram9k.q_o[2] ram9k.q_o[3] ram9k.q_o[11] + + + ram9k.q_o[18] ram9k.q_o[3] ram9k.q_o[10] ram9k.q_o[11] + + + ram9k.q_o[21] ram9k.q_o[4] ram9k.q_o[12] ram9k.q_o[13] + + + ram9k.q_o[21] ram9k.q_o[4] ram9k.q_o[5] ram9k.q_o[12] + + + ram9k.q_o[20] ram9k.q_o[4] ram9k.q_o[5] ram9k.q_o[13] + + + ram9k.q_o[20] ram9k.q_o[5] ram9k.q_o[12] ram9k.q_o[13] + + + ram9k.q_o[23] ram9k.q_o[6] ram9k.q_o[14] ram9k.q_o[15] + + + ram9k.q_o[23] ram9k.q_o[6] ram9k.q_o[7] ram9k.q_o[14] + + + ram9k.q_o[22] ram9k.q_o[6] ram9k.q_o[7] ram9k.q_o[15] + + + ram9k.q_o[22] ram9k.q_o[7] ram9k.q_o[14] ram9k.q_o[15] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 mux_15 + + + l1.N0 + mux_16 mux_21 mux_11 mux_14 + + + l1.E0 + mux_32 mux_6 mux_9 mux_31 + + + l1.S0 + mux_48 mux_22 mux_27 mux_13 + + + l1.W1 + mux_64 mux_7 mux_25 mux_30 + + + l1.N1 + mux_80 mux_23 mux_26 mux_29 + + + l1.E1 + mux_1 mux_4 mux_42 mux_47 + + + l1.S1 + mux_17 mux_20 mux_43 mux_46 + + + l1.W2 + mux_33 mux_38 mux_8 mux_63 + + + l1.N2 + mux_49 mux_54 mux_59 mux_12 + + + l1.E2 + mux_65 mux_39 mux_24 mux_62 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.W3 + mux_2 mux_36 mux_41 mux_79 + + + l1.N3 + mux_18 mux_52 mux_75 mux_45 + + + l1.E3 + mux_34 mux_37 mux_40 mux_95 + + + l1.S3 + mux_50 mux_53 mux_91 mux_44 + + + l1.W4 + mux_66 mux_71 mux_56 mux_61 + + + l1.N4 + mux_82 mux_87 mux_57 mux_60 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.S4 + mux_19 mux_84 mux_74 mux_77 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.N5 + mux_51 mux_85 mux_90 mux_76 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.S5 + mux_83 mux_86 mux_89 mux_92 + + + l1.W6 + mux_96 mux_101 mux_106 mux_111 + + + l1.N6 + mux_112 mux_117 mux_107 mux_110 + + + l1.E6 + mux_0 mux_102 mux_105 mux_127 + + + l1.S6 + mux_16 mux_118 mux_123 mux_109 + + + l1.W7 + mux_32 mux_103 mux_121 mux_126 + + + l1.N7 + mux_48 mux_119 mux_122 mux_125 + + + l1.E7 + mux_97 mux_100 mux_10 mux_15 + + + l1.S7 + mux_113 mux_116 mux_11 mux_14 + + + l1.W8 + mux_1 mux_6 mux_104 mux_31 + + + l1.N8 + mux_17 mux_22 mux_27 mux_108 + + + l1.E8 + mux_33 mux_7 mux_120 mux_30 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.W0 + mux_98 mux_4 mux_9 mux_47 + + + l2.N0 + mux_114 mux_20 mux_43 mux_13 + + + l2.E0 + mux_2 mux_5 mux_8 mux_63 + + + l2.S0 + mux_18 mux_21 mux_59 mux_12 + + + l2.W2 + mux_34 mux_39 mux_24 mux_29 + + + l2.N2 + mux_50 mux_55 mux_25 mux_28 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.S2 + mux_115 mux_52 mux_42 mux_45 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.N4 + mux_19 mux_53 mux_58 mux_44 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l2.S4 + mux_51 mux_54 mux_57 mux_60 + + + l3.W0 + mux_64 mux_69 mux_74 mux_79 + + + l3.N0 + mux_80 mux_85 mux_75 mux_78 + + + l3.E0 + mux_96 mux_70 mux_73 mux_95 + + + l3.S0 + mux_112 mux_86 mux_91 mux_77 + + + l3.W3 + mux_0 mux_71 mux_89 mux_94 + + + l3.N3 + mux_16 mux_87 mux_90 mux_93 + + + l3.E3 + mux_65 mux_68 mux_106 mux_111 + + + l3.S3 + mux_81 mux_84 mux_107 mux_110 + + + l3.W6 + mux_97 mux_102 mux_72 mux_127 + + + l3.N6 + mux_113 mux_118 mux_123 mux_76 + + + l3.E6 + mux_1 mux_103 mux_88 mux_126 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.W9 + mux_66 mux_100 mux_105 mux_15 + + + l3.N9 + mux_82 mux_116 mux_11 mux_109 + + + l3.E9 + mux_98 mux_101 mux_104 mux_31 + + + l3.S9 + mux_114 mux_117 mux_27 mux_108 + + + l3.W12 + mux_2 mux_7 mux_120 mux_125 + + + l3.N12 + mux_18 mux_23 mux_121 mux_124 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.S12 + mux_83 mux_20 mux_10 mux_13 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.N15 + mux_115 mux_21 mux_26 mux_12 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.S15 + mux_19 mux_22 mux_25 mux_28 + + + l3.W18 + mux_32 mux_37 mux_42 mux_47 + + + l3.N18 + mux_48 mux_53 mux_43 mux_46 + + + l3.E18 + mux_64 mux_38 mux_41 mux_63 + + + l3.S18 + mux_80 mux_54 mux_59 mux_45 + + + l3.W21 + mux_96 mux_39 mux_57 mux_62 + + + l3.N21 + mux_112 mux_55 mux_58 mux_61 + + + l3.E21 + mux_33 mux_36 mux_74 mux_79 + + + l3.S21 + mux_49 mux_52 mux_75 mux_78 + + + l4.W0 + mux_65 mux_70 mux_40 mux_95 + + + l4.N0 + mux_81 mux_86 mux_91 mux_44 + + + l4.E0 + mux_97 mux_71 mux_56 mux_94 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.W4 + mux_34 mux_68 mux_73 mux_111 + + + l4.N4 + mux_50 mux_84 mux_107 mux_77 + + + l4.E4 + mux_66 mux_69 mux_72 mux_127 + + + l4.S4 + mux_82 mux_85 mux_123 mux_76 + + + l4.W8 + mux_98 mux_103 mux_88 mux_93 + + + l4.N8 + mux_114 mux_119 mux_89 mux_92 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.S8 + mux_51 mux_116 mux_106 mux_109 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.N12 + mux_83 mux_117 mux_122 mux_108 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l4.S12 + mux_115 mux_118 mux_121 mux_124 + + + l8.W0 + mux_0 mux_5 mux_10 mux_15 + + + l8.N0 + mux_16 mux_21 mux_11 mux_14 + + + l8.E0 + mux_32 mux_6 mux_9 mux_31 + + + l8.S0 + mux_48 mux_22 mux_27 mux_13 + + + l8.W8 + mux_64 mux_7 mux_25 mux_30 + + + l8.N8 + mux_80 mux_23 mux_26 mux_29 + + + l8.E8 + mux_1 mux_4 mux_42 mux_47 + + + l8.S8 + mux_17 mux_20 mux_43 mux_46 + + + l1.W9 + l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N9 + l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E9 + l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S9 + l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W10 + l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N10 + l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E10 + l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S10 + l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W11 + l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.N11 + l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E11 + l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S11 + l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.W12 + l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N12 + l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E12 + l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S12 + l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + ram9k.raddr_i[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + ram9k.raddr_i[1] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + ram9k.raddr_i[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + ram9k.raddr_i[3] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + ram9k.raddr_i[4] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + ram9k.raddr_i[5] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + ram9k.waddr_i[0] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + ram9k.waddr_i[1] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + ram9k.waddr_i[2] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + ram9k.waddr_i[3] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + ram9k.waddr_i[4] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + ram9k.waddr_i[5] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + ram9k.data_i[0] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + ram9k.data_i[1] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + ram9k.data_i[2] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + ram9k.data_i[3] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + ram9k.data_i[4] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + ram9k.data_i[5] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + ram9k.data_i[6] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + ram9k.data_i[7] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + ram9k.data_i[8] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + ram9k.data_i[18] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + ram9k.data_i[19] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + ram9k.data_i[20] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + ram9k.data_i[21] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + ram9k.data_i[22] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + ram9k.data_i[23] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + ram9k.data_i[24] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + ram9k.data_i[25] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + ram9k.data_i[26] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + ram9k.bwen_ni[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + ram9k.bwen_ni[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + ram9k.bwen_ni[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + ram9k.bwen_ni[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + ram9k.bwen_ni[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + ram9k.bwen_ni[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + ram9k.bwen_ni[6] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + ram9k.bwen_ni[7] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + ram9k.bwen_ni[8] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + ram9k.bwen_ni[18] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + ram9k.bwen_ni[19] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + ram9k.bwen_ni[20] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + ram9k.bwen_ni[21] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + ram9k.bwen_ni[22] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + ram9k.bwen_ni[23] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + ram9k.bwen_ni[24] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + ram9k.bwen_ni[25] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + ram9k.bwen_ni[26] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + ram9k.lclk[0] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + ram9k.lreset[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + ram9k.raddr_i[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + ram9k.raddr_i[1] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + ram9k.raddr_i[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + ram9k.raddr_i[3] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + ram9k.raddr_i[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + ram9k.raddr_i[5] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + ram9k.waddr_i[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + ram9k.waddr_i[1] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + ram9k.waddr_i[2] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + ram9k.waddr_i[3] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + + + + + + + + + + + + l1.W0 l1.W1 l3.W2 ram9k.q_o[32] + + + l1.W2 l2.W1 l4.W3 ram9k.q_o[24] + + + l1.W3 l3.W5 l8.W7 ram9k.q_o[28] + + + l1.W4 l3.W8 l8.W15 + + + l1.N5 l1.N6 l3.N11 ram9k.q_o[33] + + + l1.N7 l2.N3 l4.N7 ram9k.q_o[25] + + + l1.N8 l3.N14 l8.N7 ram9k.q_o[29] + + + l1.N9 l3.N17 l8.N15 + + + l1.E10 l1.E11 l3.E20 ram9k.q_o[34] + + + l1.E12 l2.E5 l4.E11 ram9k.q_o[26] + + + l1.E0 l3.E23 l8.E7 ram9k.q_o[30] + + + l1.E1 l3.E2 l8.E15 + + + l1.S2 l1.S3 l3.S5 ram9k.q_o[35] + + + l1.S4 l2.S1 l4.S15 ram9k.q_o[27] + + + l1.S5 l3.S8 l8.S7 ram9k.q_o[31] + + + l1.S6 l3.S11 l8.S15 + + + l1.W7 l1.W8 l3.W14 ram9k.q_o[24] + + + l1.W9 l2.W3 l4.W3 ram9k.q_o[28] + + + l1.W10 l3.W17 l8.W7 ram9k.q_o[32] + + + l1.W11 l3.W20 l8.W15 + + + l1.N12 l1.N0 l3.N23 ram9k.q_o[25] + + + l1.N1 l2.N5 l4.N7 ram9k.q_o[29] + + + l1.N2 l3.N2 l8.N7 ram9k.q_o[33] + + + l1.N3 l3.N5 l8.N15 + + + l1.E4 l1.E5 l3.E8 ram9k.q_o[26] + + + l1.E6 l2.E1 l4.E11 ram9k.q_o[30] + + + l1.E7 l3.E11 l8.E7 ram9k.q_o[34] + + + l1.E8 l3.E14 l8.E15 + + + l1.S9 l1.S10 l3.S17 ram9k.q_o[27] + + + l1.S11 l2.S3 l4.S15 ram9k.q_o[31] + + + l1.S12 l3.S20 l8.S7 ram9k.q_o[35] + + + l1.S0 l3.S23 l8.S15 + + + l1.W1 l1.W2 l3.W2 ram9k.q_o[32] + + + l1.W3 l2.W5 l4.W3 ram9k.q_o[24] + + + l1.W4 l3.W5 l8.W7 ram9k.q_o[28] + + + l1.W5 l3.W8 l8.W15 + + + l1.N6 l1.N7 l3.N11 ram9k.q_o[33] + + + l1.N8 l2.N1 l4.N7 ram9k.q_o[25] + + + l1.N9 l3.N14 l8.N7 ram9k.q_o[29] + + + l1.N10 l3.N17 l8.N15 + + + l1.E11 l1.E12 l3.E20 ram9k.q_o[34] + + + l1.E0 l2.E3 l4.E11 ram9k.q_o[26] + + + l1.E1 l3.E23 l8.E7 ram9k.q_o[30] + + + l1.E2 l3.E2 l8.E15 + + + l1.S3 l1.S4 l3.S5 ram9k.q_o[35] + + + l1.S5 l2.S5 l4.S15 ram9k.q_o[27] + + + l1.S6 l3.S8 l8.S7 ram9k.q_o[31] + + + l1.S7 l3.S11 l8.S15 + + + l1.W8 l1.W9 l3.W14 ram9k.q_o[24] + + + l1.W10 l2.W1 l4.W3 ram9k.q_o[28] + + + l1.W11 l3.W17 l8.W7 ram9k.q_o[32] + + + l1.W12 l3.W20 l8.W15 + + + l1.N0 l1.N1 l3.N23 ram9k.q_o[25] + + + l1.N2 l2.N3 l4.N7 ram9k.q_o[29] + + + l1.N3 l3.N2 l8.N7 ram9k.q_o[33] + + + l1.N4 l3.N5 l8.N15 + + + l1.E5 l1.E6 l3.E8 ram9k.q_o[26] + + + l1.E7 l2.E5 l4.E11 ram9k.q_o[30] + + + l1.E8 l3.E11 l8.E7 ram9k.q_o[34] + + + l1.E9 l3.E14 l8.E15 + + + l1.S10 l1.S11 l3.S17 ram9k.q_o[27] + + + l1.S12 l2.S1 l4.S15 ram9k.q_o[31] + + + l1.S0 l3.S20 l8.S7 ram9k.q_o[35] + + + l1.S1 l3.S23 l8.S15 + + + l1.W2 l1.W3 l3.W2 ram9k.q_o[32] + + + l1.W4 l2.W3 l4.W3 ram9k.q_o[24] + + + l1.W5 l3.W5 l8.W7 ram9k.q_o[28] + + + l1.W6 l3.W8 l8.W15 + + + l1.N7 l1.N8 l3.N11 ram9k.q_o[33] + + + l1.N9 l2.N5 l4.N7 ram9k.q_o[25] + + + l1.N10 l3.N14 l8.N7 ram9k.q_o[29] + + + l1.N11 l3.N17 l8.N15 + + + l1.E12 l1.E0 l3.E20 ram9k.q_o[34] + + + l1.E1 l2.E1 l4.E11 ram9k.q_o[26] + + + l1.E2 l3.E23 l8.E7 ram9k.q_o[30] + + + l1.E3 l3.E2 l8.E15 + + + l1.S4 l1.S5 l3.S5 ram9k.q_o[35] + + + l1.S6 l2.S3 l4.S15 ram9k.q_o[27] + + + l1.S7 l3.S8 l8.S7 ram9k.q_o[31] + + + l1.S8 l3.S11 l8.S15 + + + l1.W9 l1.W10 l3.W14 ram9k.q_o[24] + + + l1.W11 l2.W5 l4.W3 ram9k.q_o[28] + + + l1.W12 l3.W17 l8.W7 ram9k.q_o[32] + + + l1.W0 l3.W20 l8.W15 + + + l1.N1 l1.N2 l3.N23 ram9k.q_o[25] + + + l1.N3 l2.N1 l4.N7 ram9k.q_o[29] + + + l1.N4 l3.N2 l8.N7 ram9k.q_o[33] + + + l1.N5 l3.N5 l8.N15 + + + l1.E6 l1.E7 l3.E8 ram9k.q_o[26] + + + l1.E8 l2.E3 l4.E11 ram9k.q_o[30] + + + l1.E9 l3.E11 l8.E7 ram9k.q_o[34] + + + l1.E10 l3.E14 l8.E15 + + + l1.S11 l1.S12 l3.S17 ram9k.q_o[27] + + + l1.S0 l2.S5 l4.S15 ram9k.q_o[31] + + + l1.S1 l3.S20 l8.S7 ram9k.q_o[35] + + + l1.S2 l3.S23 l8.S15 + + + l1.W3 l1.W4 l3.W2 ram9k.q_o[32] + + + l1.W5 l2.W1 l4.W3 ram9k.q_o[24] + + + l1.W6 l3.W5 l8.W7 ram9k.q_o[28] + + + l1.W7 l3.W8 l8.W15 + + + l1.N8 l1.N9 l3.N11 ram9k.q_o[33] + + + l1.N10 l2.N3 l4.N7 ram9k.q_o[25] + + + l1.N11 l3.N14 l8.N7 ram9k.q_o[29] + + + l1.N12 l3.N17 l8.N15 + + + l1.E0 l1.E1 l3.E20 ram9k.q_o[34] + + + l1.E2 l2.E5 l4.E11 ram9k.q_o[26] + + + l1.E3 l3.E23 l8.E7 ram9k.q_o[30] + + + l1.E4 l3.E2 l8.E15 + + + l1.S5 l1.S6 l3.S5 ram9k.q_o[35] + + + l1.S7 l2.S1 l4.S15 ram9k.q_o[27] + + + l1.S8 l3.S8 l8.S7 ram9k.q_o[31] + + + l1.S9 l3.S11 l8.S15 + + + l1.W10 l1.W11 l3.W14 ram9k.q_o[24] + + + l1.W12 l2.W3 l4.W3 ram9k.q_o[28] + + + l1.W0 l3.W17 l8.W7 ram9k.q_o[32] + + + l1.W1 l3.W20 l8.W15 + + + l1.N2 l1.N3 l3.N23 ram9k.q_o[25] + + + l1.N4 l2.N5 l4.N7 ram9k.q_o[29] + + + l1.N5 l3.N2 l8.N7 ram9k.q_o[33] + + + l1.N6 l3.N5 l8.N15 + + + l1.E7 l1.E8 l3.E8 ram9k.q_o[26] + + + l1.E9 l2.E1 l4.E11 ram9k.q_o[30] + + + l1.E10 l3.E11 l8.E7 ram9k.q_o[34] + + + l1.E11 l3.E14 l8.E15 + + + l1.S12 l1.S0 l3.S17 ram9k.q_o[27] + + + l1.S1 l2.S3 l4.S15 ram9k.q_o[31] + + + l1.S2 l3.S20 l8.S7 ram9k.q_o[35] + + + l1.S3 l3.S23 l8.S15 + + + l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 ram9k.q_o[24] OG_0 + + + l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 ram9k.q_o[32] + + + l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 ram9k.q_o[28] + + + l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 ram9k.q_o[25] + + + l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 ram9k.q_o[33] + + + l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 ram9k.q_o[29] OG_2 l1.N2 + + + l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 ram9k.q_o[26] OG_2 l1.S4 + + + l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 ram9k.q_o[34] OG_3 l1.N9 + + + l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 ram9k.q_o[30] OG_4 + + + l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 ram9k.q_o[27] + + + l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 ram9k.q_o[35] + + + l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 ram9k.q_o[31] + + + l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 ram9k.q_o[28] + + + l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 ram9k.q_o[24] OG_6 l1.E5 + + + l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 ram9k.q_o[32] OG_6 l1.S4 + + + l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 ram9k.q_o[29] OG_7 l1.N0 + + + l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 ram9k.q_o[25] OG_0 + + + l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 ram9k.q_o[33] + + + l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 ram9k.q_o[30] + + + l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 ram9k.q_o[26] + + + l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 ram9k.q_o[34] + + + l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 ram9k.q_o[31] OG_2 l1.E0 + + + l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 ram9k.q_o[27] OG_2 l1.N10 + + + l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 ram9k.q_o[35] OG_3 l1.W12 + + + l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 ram9k.q_o[24] OG_4 + + + l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 ram9k.q_o[32] + + + l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 ram9k.q_o[28] + + + l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 ram9k.q_o[25] + + + l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 ram9k.q_o[33] + + + l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 ram9k.q_o[29] OG_6 l1.W6 + + + l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 ram9k.q_o[26] OG_6 l1.S8 + + + l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 ram9k.q_o[34] OG_7 l1.E2 + + + l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 ram9k.q_o[30] OG_0 + + + l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 ram9k.q_o[27] + + + l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 ram9k.q_o[35] + + + l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 ram9k.q_o[31] + + + l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 ram9k.q_o[28] + + + l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 ram9k.q_o[24] OG_2 l1.S6 + + + l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 ram9k.q_o[32] OG_2 l1.E0 + + + l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 ram9k.q_o[29] OG_3 l1.W11 + + + l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 ram9k.q_o[25] OG_4 + + + l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 ram9k.q_o[33] + + + l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 ram9k.q_o[30] + + + l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 ram9k.q_o[26] + + + l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 ram9k.q_o[34] + + + l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 ram9k.q_o[31] OG_6 l1.E2 + + + l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 ram9k.q_o[27] OG_6 l1.W3 + + + l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 ram9k.q_o[35] OG_7 l1.W0 + + + l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 ram9k.q_o[24] OG_0 + + + l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 ram9k.q_o[32] + + + l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 ram9k.q_o[28] + + + l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 ram9k.q_o[25] + + + l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 ram9k.q_o[33] + + + l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 ram9k.q_o[29] OG_2 l1.W12 + + + l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 ram9k.q_o[26] OG_2 l1.W4 + + + l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 ram9k.q_o[34] OG_3 l1.N10 + + + l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 ram9k.q_o[30] OG_4 + + + l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 ram9k.q_o[27] + + + l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 ram9k.q_o[35] + + + l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 ram9k.q_o[31] + + + ram9k.q_o[29] ram9k.q_o[24] ram9k.q_o[32] ram9k.q_o[33] + + + ram9k.q_o[29] ram9k.q_o[24] ram9k.q_o[25] ram9k.q_o[32] + + + ram9k.q_o[28] ram9k.q_o[24] ram9k.q_o[25] ram9k.q_o[33] + + + ram9k.q_o[28] ram9k.q_o[25] ram9k.q_o[32] ram9k.q_o[33] + + + ram9k.q_o[31] ram9k.q_o[26] ram9k.q_o[34] ram9k.q_o[35] + + + ram9k.q_o[31] ram9k.q_o[26] ram9k.q_o[27] ram9k.q_o[34] + + + ram9k.q_o[30] ram9k.q_o[26] ram9k.q_o[27] ram9k.q_o[35] + + + ram9k.q_o[30] ram9k.q_o[27] ram9k.q_o[34] ram9k.q_o[35] + + + ram9k.q_o[33] ram9k.q_o[28] ram9k.q_o[24] ram9k.q_o[25] + + + ram9k.q_o[33] ram9k.q_o[28] ram9k.q_o[29] ram9k.q_o[24] + + + ram9k.q_o[32] ram9k.q_o[28] ram9k.q_o[29] ram9k.q_o[25] + + + ram9k.q_o[32] ram9k.q_o[29] ram9k.q_o[24] ram9k.q_o[25] + + + ram9k.q_o[35] ram9k.q_o[30] ram9k.q_o[26] ram9k.q_o[27] + + + ram9k.q_o[35] ram9k.q_o[30] ram9k.q_o[31] ram9k.q_o[26] + + + ram9k.q_o[34] ram9k.q_o[30] ram9k.q_o[31] ram9k.q_o[27] + + + ram9k.q_o[34] ram9k.q_o[31] ram9k.q_o[26] ram9k.q_o[27] + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + + OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + + OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + + + + l1.W0 + mux_0 mux_5 mux_10 mux_15 + + + l1.N0 + mux_16 mux_21 mux_11 mux_14 + + + l1.E0 + mux_32 mux_6 mux_9 mux_31 + + + l1.S0 + mux_48 mux_22 mux_27 mux_13 + + + l1.W1 + mux_64 mux_7 mux_25 mux_30 + + + l1.N1 + mux_80 mux_23 mux_26 mux_29 + + + l1.E1 + mux_1 mux_4 mux_42 mux_47 + + + l1.S1 + mux_17 mux_20 mux_43 mux_46 + + + l1.W2 + mux_33 mux_38 mux_8 mux_63 + + + l1.N2 + mux_49 mux_54 mux_59 mux_12 + + + l1.E2 + mux_65 mux_39 mux_24 mux_62 + + + l1.S2 + mux_81 mux_55 mux_58 mux_28 + + + l1.W3 + mux_2 mux_36 mux_41 mux_79 + + + l1.N3 + mux_18 mux_52 mux_75 mux_45 + + + l1.E3 + mux_34 mux_37 mux_40 mux_95 + + + l1.S3 + mux_50 mux_53 mux_91 mux_44 + + + l1.W4 + mux_66 mux_71 mux_56 mux_61 + + + l1.N4 + mux_82 mux_87 mux_57 mux_60 + + + l1.E4 + mux_3 mux_68 mux_73 mux_78 + + + l1.S4 + mux_19 mux_84 mux_74 mux_77 + + + l1.W5 + mux_35 mux_69 mux_72 mux_94 + + + l1.N5 + mux_51 mux_85 mux_90 mux_76 + + + l1.E5 + mux_67 mux_70 mux_88 mux_93 + + + l1.S5 + mux_83 mux_86 mux_89 mux_92 + + + l1.W6 + mux_96 mux_101 mux_106 mux_111 + + + l1.N6 + mux_112 mux_117 mux_107 mux_110 + + + l1.E6 + mux_0 mux_102 mux_105 mux_127 + + + l1.S6 + mux_16 mux_118 mux_123 mux_109 + + + l1.W7 + mux_32 mux_103 mux_121 mux_126 + + + l1.N7 + mux_48 mux_119 mux_122 mux_125 + + + l1.E7 + mux_97 mux_100 mux_10 mux_15 + + + l1.S7 + mux_113 mux_116 mux_11 mux_14 + + + l1.W8 + mux_1 mux_6 mux_104 mux_31 + + + l1.N8 + mux_17 mux_22 mux_27 mux_108 + + + l1.E8 + mux_33 mux_7 mux_120 mux_30 + + + l1.S8 + mux_49 mux_23 mux_26 mux_124 + + + l2.W0 + mux_98 mux_4 mux_9 mux_47 + + + l2.N0 + mux_114 mux_20 mux_43 mux_13 + + + l2.E0 + mux_2 mux_5 mux_8 mux_63 + + + l2.S0 + mux_18 mux_21 mux_59 mux_12 + + + l2.W2 + mux_34 mux_39 mux_24 mux_29 + + + l2.N2 + mux_50 mux_55 mux_25 mux_28 + + + l2.E2 + mux_99 mux_36 mux_41 mux_46 + + + l2.S2 + mux_115 mux_52 mux_42 mux_45 + + + l2.W4 + mux_3 mux_37 mux_40 mux_62 + + + l2.N4 + mux_19 mux_53 mux_58 mux_44 + + + l2.E4 + mux_35 mux_38 mux_56 mux_61 + + + l2.S4 + mux_51 mux_54 mux_57 mux_60 + + + l3.W0 + mux_64 mux_69 mux_74 mux_79 + + + l3.N0 + mux_80 mux_85 mux_75 mux_78 + + + l3.E0 + mux_96 mux_70 mux_73 mux_95 + + + l3.S0 + mux_112 mux_86 mux_91 mux_77 + + + l3.W3 + mux_0 mux_71 mux_89 mux_94 + + + l3.N3 + mux_16 mux_87 mux_90 mux_93 + + + l3.E3 + mux_65 mux_68 mux_106 mux_111 + + + l3.S3 + mux_81 mux_84 mux_107 mux_110 + + + l3.W6 + mux_97 mux_102 mux_72 mux_127 + + + l3.N6 + mux_113 mux_118 mux_123 mux_76 + + + l3.E6 + mux_1 mux_103 mux_88 mux_126 + + + l3.S6 + mux_17 mux_119 mux_122 mux_92 + + + l3.W9 + mux_66 mux_100 mux_105 mux_15 + + + l3.N9 + mux_82 mux_116 mux_11 mux_109 + + + l3.E9 + mux_98 mux_101 mux_104 mux_31 + + + l3.S9 + mux_114 mux_117 mux_27 mux_108 + + + l3.W12 + mux_2 mux_7 mux_120 mux_125 + + + l3.N12 + mux_18 mux_23 mux_121 mux_124 + + + l3.E12 + mux_67 mux_4 mux_9 mux_14 + + + l3.S12 + mux_83 mux_20 mux_10 mux_13 + + + l3.W15 + mux_99 mux_5 mux_8 mux_30 + + + l3.N15 + mux_115 mux_21 mux_26 mux_12 + + + l3.E15 + mux_3 mux_6 mux_24 mux_29 + + + l3.S15 + mux_19 mux_22 mux_25 mux_28 + + + l3.W18 + mux_32 mux_37 mux_42 mux_47 + + + l3.N18 + mux_48 mux_53 mux_43 mux_46 + + + l3.E18 + mux_64 mux_38 mux_41 mux_63 + + + l3.S18 + mux_80 mux_54 mux_59 mux_45 + + + l3.W21 + mux_96 mux_39 mux_57 mux_62 + + + l3.N21 + mux_112 mux_55 mux_58 mux_61 + + + l3.E21 + mux_33 mux_36 mux_74 mux_79 + + + l3.S21 + mux_49 mux_52 mux_75 mux_78 + + + l4.W0 + mux_65 mux_70 mux_40 mux_95 + + + l4.N0 + mux_81 mux_86 mux_91 mux_44 + + + l4.E0 + mux_97 mux_71 mux_56 mux_94 + + + l4.S0 + mux_113 mux_87 mux_90 mux_60 + + + l4.W4 + mux_34 mux_68 mux_73 mux_111 + + + l4.N4 + mux_50 mux_84 mux_107 mux_77 + + + l4.E4 + mux_66 mux_69 mux_72 mux_127 + + + l4.S4 + mux_82 mux_85 mux_123 mux_76 + + + l4.W8 + mux_98 mux_103 mux_88 mux_93 + + + l4.N8 + mux_114 mux_119 mux_89 mux_92 + + + l4.E8 + mux_35 mux_100 mux_105 mux_110 + + + l4.S8 + mux_51 mux_116 mux_106 mux_109 + + + l4.W12 + mux_67 mux_101 mux_104 mux_126 + + + l4.N12 + mux_83 mux_117 mux_122 mux_108 + + + l4.E12 + mux_99 mux_102 mux_120 mux_125 + + + l4.S12 + mux_115 mux_118 mux_121 mux_124 + + + l8.W0 + mux_0 mux_5 mux_10 mux_15 + + + l8.N0 + mux_16 mux_21 mux_11 mux_14 + + + l8.E0 + mux_32 mux_6 mux_9 mux_31 + + + l8.S0 + mux_48 mux_22 mux_27 mux_13 + + + l8.W8 + mux_64 mux_7 mux_25 mux_30 + + + l8.N8 + mux_80 mux_23 mux_26 mux_29 + + + l8.E8 + mux_1 mux_4 mux_42 mux_47 + + + l8.S8 + mux_17 mux_20 mux_43 mux_46 + + + l1.W9 + l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.N9 + l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.E9 + l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.S9 + l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.W10 + l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.N10 + l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.E10 + l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.S10 + l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.W11 + l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + l1.N11 + l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.E11 + l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.S11 + l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.W12 + l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + + l1.N12 + l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + + l1.E12 + l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + + l1.S12 + l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + + ram9k.raddr_i[6] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + + ram9k.raddr_i[7] + mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + ram9k.raddr_i[8] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + + ram9k.raddr_i[9] + mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + + ram9k.raddr_i[10] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + + ram9k.waddr_i[6] + mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + + ram9k.waddr_i[7] + mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + + ram9k.waddr_i[8] + mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + + ram9k.waddr_i[9] + mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + + ram9k.waddr_i[10] + mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + + ram9k.data_i[27] + mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + + ram9k.data_i[28] + mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + + ram9k.data_i[29] + mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + ram9k.data_i[30] + mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + + ram9k.data_i[31] + mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + + ram9k.data_i[32] + mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + + ram9k.data_i[33] + mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + ram9k.data_i[34] + mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + + ram9k.data_i[35] + mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + + ram9k.data_i[9] + mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + + ram9k.data_i[10] + mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + + ram9k.data_i[11] + mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + + ram9k.data_i[12] + mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + + ram9k.data_i[13] + mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + + ram9k.data_i[14] + mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + + ram9k.data_i[15] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + + ram9k.data_i[16] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + + ram9k.data_i[17] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + + ram9k.bwen_ni[27] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + + ram9k.bwen_ni[28] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + + ram9k.bwen_ni[29] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + + ram9k.bwen_ni[30] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + + ram9k.bwen_ni[31] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + + ram9k.bwen_ni[32] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + + ram9k.bwen_ni[33] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + + ram9k.bwen_ni[34] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + + ram9k.bwen_ni[35] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + + ram9k.bwen_ni[9] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + + ram9k.bwen_ni[10] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + + ram9k.bwen_ni[11] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + + ram9k.bwen_ni[12] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + + ram9k.bwen_ni[13] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + + ram9k.bwen_ni[14] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + + ram9k.bwen_ni[15] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + + ram9k.bwen_ni[16] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + ram9k.bwen_ni[17] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + + ram9k.wen_ni[0] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + + ram9k.ren_ni[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + + ram9k.raddr_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + + ram9k.raddr_i[7] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + + ram9k.raddr_i[8] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + + ram9k.raddr_i[9] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + + ram9k.raddr_i[10] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + + ram9k.waddr_i[6] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + + ram9k.waddr_i[7] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + + ram9k.waddr_i[8] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + + ram9k.waddr_i[9] + mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + + ram9k.waddr_i[10] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + + ram9k.data_i[27] + mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + + ram9k.data_i[28] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + + + + + + + + + + + + + + + + + + + + + + + + + From 481efce3dba7cca50decd331f5747bd7465dc0d0 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Fri, 29 Nov 2024 10:44:40 +0800 Subject: [PATCH 418/453] Create music.blif --- .../VIB/VIB_test_benchmarks/music.blif | 1170 +++++++++++++++++ 1 file changed, 1170 insertions(+) create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif new file mode 100644 index 00000000000..dc494993029 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif @@ -0,0 +1,1170 @@ +# Generated by Yosys 0.38+46 (git sha1 074b50e9c, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model music +.inputs clk +.outputs speaker +.names $false +.names $true +1 +.names $undef +.names get_fullnote.address[7] $abc$2165$new_n111 $abc$2165$new_n116 get_fullnote.address[5] $abc$2165$new_n118 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[0] +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$2165$new_n112 $abc$2165$new_n116 get_fullnote.address[6] get_fullnote.address[5] $abc$2165$new_n117 $abc$2165$new_n111 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[7] $abc$2165$new_n113 get_fullnote.address[6] $abc$2165$new_n115 get_fullnote.address[5] $abc$2165$new_n112 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[3] get_fullnote.address[5] get_fullnote.address[2] get_fullnote.address[4] $abc$2165$new_n114 $abc$2165$new_n113 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +.names get_fullnote.address[0] get_fullnote.address[1] $abc$2165$new_n114 +11 1 +.names get_fullnote.address[2] get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[0] $abc$2165$new_n115 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +.names get_fullnote.address[5] get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[4] get_fullnote.address[1] $abc$2165$new_n116 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[0] get_fullnote.address[2] $abc$2165$new_n117 +00001 1 +00011 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[4] get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[6] $abc$2165$new_n118 +01000 1 +01001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[4] $abc$2165$new_n130 $abc$2165$new_n230 get_fullnote.address[7] get_fullnote.address[6] $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[1] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$2165$new_n124 get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[0] $abc$2165$new_n123 +1001 1 +1011 1 +1110 1 +1111 1 +.names get_fullnote.address[4] get_fullnote.address[3] $abc$2165$new_n124 +10 1 +.names get_fullnote.address[4] get_fullnote.address[5] $abc$2165$new_n125 +11 1 +.names $abc$2165$new_n125 get_fullnote.address[1] get_fullnote.address[0] get_fullnote.address[2] $abc$2165$new_n126 +1100 1 +.names get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[5] get_fullnote.address[2] get_fullnote.address[1] $abc$2165$new_n127 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[0] $abc$2165$new_n129 +000 1 +010 1 +011 1 +.names get_fullnote.address[5] get_fullnote.address[1] get_fullnote.address[2] get_fullnote.address[0] get_fullnote.address[3] $abc$2165$new_n130 +00000 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[7] get_fullnote.address[6] $abc$2165$new_n232 $abc$2165$new_n136 $abc$2165$new_n138 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[2] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names get_fullnote.address[4] get_fullnote.address[3] get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] $abc$2165$new_n134 +00000 1 +00001 1 +00011 1 +00101 1 +00110 1 +00111 1 +.names get_fullnote.address[5] $abc$2165$new_n144 $abc$2165$new_n115 $abc$2165$new_n136 +000 1 +001 1 +011 1 +.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[5] $abc$2165$new_n138 +00001 1 +00011 1 +00101 1 +00111 1 +01101 1 +10001 1 +10011 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$2165$new_n143 get_fullnote.address[5] $abc$2165$new_n146 $abc$2165$new_n140 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[3] +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names get_fullnote.address[6] get_fullnote.address[7] $abc$2165$new_n141 $abc$2165$new_n124 $abc$2165$new_n142 $abc$2165$new_n140 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$2165$new_n124 get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] $abc$2165$new_n141 +1000 1 +.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[2] get_fullnote.address[3] $abc$2165$new_n142 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names get_fullnote.address[7] get_fullnote.address[6] $abc$2165$new_n145 $abc$2165$new_n144 $abc$2165$new_n143 +0000 1 +0001 1 +0100 1 +0101 1 +1001 1 +1011 1 +1100 1 +1101 1 +.names get_fullnote.address[4] get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[5] get_fullnote.address[3] $abc$2165$new_n144 +00000 1 +00001 1 +00011 1 +00100 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11110 1 +.names get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[5] $abc$2165$new_n145 +10000 1 +.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[0] get_fullnote.address[2] get_fullnote.address[3] $abc$2165$new_n146 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names get_fullnote.address[6] $abc$2165$new_n125 get_fullnote.address[7] $abc$2165$new_n141 $abc$2165$new_n142 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[4] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +11111 1 +.names get_fullnote.address[6] $abc$2165$new_n142 $abc$2165$new_n125 get_fullnote.address[7] $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[5] +1110 1 +.names counter_note[0] $abc$2165$new_n153 $abc$2165$new_n155 $abc$2165$new_n150 fullnote[1] $0\counter_note[8:0][0] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +.names $abc$2165$new_n151 counter_note[8] counter_note[7] counter_note[6] counter_note[5] $abc$2165$new_n150 +10000 1 +.names $abc$2165$new_n152 counter_note[4] $abc$2165$new_n151 +10 1 +.names counter_note[0] counter_note[3] counter_note[2] counter_note[1] $abc$2165$new_n152 +0000 1 +.names fullnote[0] $abc$2165$new_n154 $abc$2165$new_n153 +10 1 +.names fullnote[4] fullnote[5] fullnote[3] fullnote[2] $abc$2165$new_n154 +0001 1 +0110 1 +1000 1 +1011 1 +1101 1 +.names fullnote[5] fullnote[3] fullnote[4] fullnote[2] $abc$2165$new_n155 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names counter_note[0] counter_note[1] $abc$2165$new_n157 $abc$2165$new_n150 $0\counter_note[8:0][1] +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names $abc$2165$new_n154 fullnote[0] fullnote[1] $abc$2165$new_n157 +100 1 +101 1 +111 1 +.names counter_note[2] $abc$2165$new_n159 counter_note[0] counter_note[1] $0\counter_note[8:0][2] +0000 1 +1001 1 +1010 1 +1011 1 +.names $abc$2165$new_n150 $abc$2165$new_n155 fullnote[0] fullnote[1] $abc$2165$new_n154 $abc$2165$new_n159 +10000 1 +10001 1 +11011 1 +11100 1 +.names counter_note[3] $abc$2165$new_n161 counter_note[0] counter_note[2] counter_note[1] $0\counter_note[8:0][3] +00000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$2165$new_n150 fullnote[1] fullnote[0] $abc$2165$new_n155 $abc$2165$new_n154 $abc$2165$new_n161 +10000 1 +10001 1 +10011 1 +10110 1 +11010 1 +11111 1 +.names counter_note[4] $abc$2165$new_n152 $abc$2165$new_n163 $0\counter_note[8:0][4] +010 1 +100 1 +.names $abc$2165$new_n150 $abc$2165$new_n155 fullnote[1] fullnote[0] $abc$2165$new_n154 $abc$2165$new_n163 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names counter_note[5] $abc$2165$new_n151 $abc$2165$new_n165 $0\counter_note[8:0][5] +010 1 +100 1 +.names $abc$2165$new_n150 fullnote[1] $abc$2165$new_n154 fullnote[0] $abc$2165$new_n155 $abc$2165$new_n165 +10000 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names counter_note[6] $abc$2165$new_n167 $abc$2165$new_n151 counter_note[5] $0\counter_note[8:0][6] +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$2165$new_n150 fullnote[1] fullnote[0] $abc$2165$new_n154 $abc$2165$new_n155 $abc$2165$new_n167 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names counter_note[7] $abc$2165$new_n151 counter_note[6] counter_note[5] $abc$2165$new_n169 $0\counter_note[8:0][7] +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names counter_note[8] $abc$2165$new_n154 $abc$2165$new_n155 fullnote[0] fullnote[1] $abc$2165$new_n169 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names counter_note[8] $abc$2165$new_n151 counter_note[7] counter_note[6] counter_note[5] $0\counter_note[8:0][8] +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names speaker $abc$2165$new_n175 $abc$2165$new_n172 $abc$2165$new_n150 $0\speaker[0:0] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$2165$new_n173 tone[19] tone[18] tone[21] tone[20] $abc$2165$new_n172 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$2165$new_n174 fullnote[3] fullnote[2] fullnote[1] fullnote[0] $abc$2165$new_n173 +10000 1 +.names fullnote[5] fullnote[4] $abc$2165$new_n174 +00 1 +.names $abc$2165$new_n176 counter_octave[7] counter_octave[6] counter_octave[5] $abc$2165$new_n175 +1000 1 +.names $abc$2165$new_n177 counter_octave[4] $abc$2165$new_n176 +10 1 +.names counter_octave[0] counter_octave[3] counter_octave[1] counter_octave[2] $abc$2165$new_n177 +0000 1 +.names counter_octave[0] $abc$2165$new_n150 $0\counter_octave[7:0][0] +01 1 +10 1 +.names counter_octave[1] $abc$2165$new_n150 counter_octave[0] $0\counter_octave[7:0][1] +010 1 +100 1 +101 1 +111 1 +.names counter_octave[2] $abc$2165$new_n150 counter_octave[0] counter_octave[1] $0\counter_octave[7:0][2] +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$2165$new_n150 counter_octave[3] $abc$2165$new_n184 $abc$2165$new_n183 $abc$2165$new_n182 $0\counter_octave[7:0][3] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$2165$new_n175 fullnote[4] fullnote[5] $abc$2165$new_n182 +100 1 +101 1 +110 1 +.names counter_octave[3] $abc$2165$new_n175 counter_octave[0] counter_octave[1] counter_octave[2] $abc$2165$new_n183 +00000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$2165$new_n175 fullnote[2] fullnote[3] $abc$2165$new_n184 +100 1 +101 1 +110 1 +.names $abc$2165$new_n150 counter_octave[4] $abc$2165$new_n177 $abc$2165$new_n175 $abc$2165$new_n182 $0\counter_octave[7:0][4] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$2165$new_n150 counter_octave[5] $abc$2165$new_n176 $abc$2165$new_n187 $abc$2165$new_n175 $0\counter_octave[7:0][5] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$2165$new_n182 fullnote[5] fullnote[3] fullnote[2] $abc$2165$new_n187 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names counter_octave[6] $abc$2165$new_n176 $abc$2165$new_n150 counter_octave[5] $abc$2165$new_n189 $0\counter_octave[7:0][6] +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names counter_octave[7] fullnote[5] fullnote[4] fullnote[3] $abc$2165$new_n189 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$2165$new_n191 $abc$2165$new_n150 $abc$2165$new_n184 $abc$2165$new_n174 $0\counter_octave[7:0][7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names counter_octave[7] $abc$2165$new_n150 $abc$2165$new_n176 counter_octave[6] counter_octave[5] $abc$2165$new_n191 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[1] +01 1 +10 1 +.names tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[2] +011 1 +100 1 +101 1 +110 1 +.names tone[3] tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[4] tone[3] tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[5] +01 1 +10 1 +.names tone[4] tone[3] tone[2] tone[1] tone[0] $abc$2165$new_n197 +11111 1 +.names tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[6] +011 1 +100 1 +101 1 +110 1 +.names tone[7] tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[8] tone[7] tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[9] +01 1 +10 1 +.names tone[8] tone[7] tone[6] tone[5] $abc$2165$new_n197 $abc$2165$new_n202 +11111 1 +.names tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[10] +011 1 +100 1 +101 1 +110 1 +.names tone[11] tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[12] tone[11] tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[13] +01 1 +10 1 +.names tone[12] tone[11] tone[10] tone[9] $abc$2165$new_n202 $abc$2165$new_n207 +11111 1 +.names tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[14] +011 1 +100 1 +101 1 +110 1 +.names tone[15] tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[16] tone[15] tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[16] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[17] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[17] +01 1 +10 1 +.names tone[16] tone[15] tone[14] tone[13] $abc$2165$new_n207 $abc$2165$new_n212 +11111 1 +.names tone[18] tone[17] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[18] +011 1 +100 1 +101 1 +110 1 +.names tone[19] tone[17] tone[18] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[19] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[20] tone[17] tone[19] tone[18] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[20] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[21] +01 1 +10 1 +.names tone[17] tone[20] tone[19] tone[18] $abc$2165$new_n212 $abc$2165$new_n217 +11111 1 +.names get_fullnote.address[0] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[22] +011 1 +100 1 +101 1 +110 1 +.names get_fullnote.address[1] get_fullnote.address[0] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[23] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names get_fullnote.address[2] get_fullnote.address[0] get_fullnote.address[1] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[24] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names get_fullnote.address[3] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[25] +01 1 +10 1 +.names get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] tone[21] $abc$2165$new_n217 $abc$2165$new_n222 +11111 1 +.names get_fullnote.address[4] get_fullnote.address[3] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[26] +011 1 +100 1 +101 1 +110 1 +.names get_fullnote.address[5] get_fullnote.address[3] get_fullnote.address[4] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[27] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names get_fullnote.address[6] get_fullnote.address[3] $abc$2165$new_n125 $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[28] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names get_fullnote.address[7] get_fullnote.address[3] get_fullnote.address[6] $abc$2165$new_n125 $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[29] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] +0 1 +.names get_fullnote.address[6] get_fullnote.address[7] $abc$2165$new_n127 $abc$2165$new_n126 $abc$2165$new_n228 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$2165$new_n228 get_fullnote.address[7] $abc$2165$new_n125 get_fullnote.address[3] $abc$2165$new_n129 $abc$2165$new_n229 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +10100 1 +10110 1 +.names $abc$2165$new_n228 get_fullnote.address[5] $abc$2165$new_n123 $abc$2165$new_n229 $abc$2165$new_n230 +0001 1 +0101 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[5] get_fullnote.address[4] get_fullnote.address[1] $abc$2165$new_n231 +01000 1 +01001 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names get_fullnote.address[5] get_fullnote.address[7] $abc$2165$new_n134 $abc$2165$new_n231 get_fullnote.address[6] $abc$2165$new_n232 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[0] fullnote[0] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[1] fullnote[1] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[2] fullnote[2] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[3] fullnote[3] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[4] fullnote[4] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[5] fullnote[5] re clk 2 +.latch $0\speaker[0:0] speaker re clk 2 +.latch $0\counter_octave[7:0][0] counter_octave[0] re clk 2 +.latch $0\counter_octave[7:0][1] counter_octave[1] re clk 2 +.latch $0\counter_octave[7:0][2] counter_octave[2] re clk 2 +.latch $0\counter_octave[7:0][3] counter_octave[3] re clk 2 +.latch $0\counter_octave[7:0][4] counter_octave[4] re clk 2 +.latch $0\counter_octave[7:0][5] counter_octave[5] re clk 2 +.latch $0\counter_octave[7:0][6] counter_octave[6] re clk 2 +.latch $0\counter_octave[7:0][7] counter_octave[7] re clk 2 +.latch $0\counter_note[8:0][0] counter_note[0] re clk 2 +.latch $0\counter_note[8:0][1] counter_note[1] re clk 2 +.latch $0\counter_note[8:0][2] counter_note[2] re clk 2 +.latch $0\counter_note[8:0][3] counter_note[3] re clk 2 +.latch $0\counter_note[8:0][4] counter_note[4] re clk 2 +.latch $0\counter_note[8:0][5] counter_note[5] re clk 2 +.latch $0\counter_note[8:0][6] counter_note[6] re clk 2 +.latch $0\counter_note[8:0][7] counter_note[7] re clk 2 +.latch $0\counter_note[8:0][8] counter_note[8] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] tone[0] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[1] tone[1] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[2] tone[2] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[3] tone[3] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[4] tone[4] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[5] tone[5] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[6] tone[6] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[7] tone[7] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[8] tone[8] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[9] tone[9] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[10] tone[10] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[11] tone[11] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[12] tone[12] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[13] tone[13] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[14] tone[14] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[15] tone[15] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[16] tone[16] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[17] tone[17] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[18] tone[18] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[19] tone[19] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[20] tone[20] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[21] tone[21] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[22] get_fullnote.address[0] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[23] get_fullnote.address[1] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[24] get_fullnote.address[2] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[25] get_fullnote.address[3] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[26] get_fullnote.address[4] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[27] get_fullnote.address[5] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[28] get_fullnote.address[6] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[29] get_fullnote.address[7] re clk 2 +.names $false fullnote[6] +1 1 +.names $false fullnote[7] +1 1 +.names tone[1] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[1] +1 1 +.names tone[2] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[2] +1 1 +.names tone[3] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[3] +1 1 +.names tone[4] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[4] +1 1 +.names tone[5] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[5] +1 1 +.names tone[6] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[6] +1 1 +.names tone[7] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[7] +1 1 +.names tone[8] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[8] +1 1 +.names tone[9] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[9] +1 1 +.names tone[10] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[10] +1 1 +.names tone[11] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[11] +1 1 +.names tone[12] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[12] +1 1 +.names tone[13] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[13] +1 1 +.names tone[14] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[14] +1 1 +.names tone[15] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[15] +1 1 +.names tone[16] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[16] +1 1 +.names tone[17] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[17] +1 1 +.names tone[18] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[18] +1 1 +.names tone[19] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[19] +1 1 +.names tone[20] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[20] +1 1 +.names tone[21] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[21] +1 1 +.names get_fullnote.address[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[22] +1 1 +.names get_fullnote.address[1] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[23] +1 1 +.names get_fullnote.address[2] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[24] +1 1 +.names get_fullnote.address[3] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[25] +1 1 +.names get_fullnote.address[4] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[26] +1 1 +.names get_fullnote.address[5] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[27] +1 1 +.names get_fullnote.address[6] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[28] +1 1 +.names get_fullnote.address[7] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[29] +1 1 +.names tone[30] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[30] +1 1 +.names $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[0] +1 1 +.names get_fullnote.address[0] tone[22] +1 1 +.names get_fullnote.address[1] tone[23] +1 1 +.names get_fullnote.address[2] tone[24] +1 1 +.names get_fullnote.address[3] tone[25] +1 1 +.names get_fullnote.address[4] tone[26] +1 1 +.names get_fullnote.address[5] tone[27] +1 1 +.names get_fullnote.address[6] tone[28] +1 1 +.names get_fullnote.address[7] tone[29] +1 1 +.end From 9240ab640debca07c42124a41053e0889ef5e374 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Fri, 29 Nov 2024 10:50:15 +0800 Subject: [PATCH 419/453] Add files via upload --- .../VIB/VIB_test_benchmarks/Divide.blif | 2290 + .../VIB/VIB_test_benchmarks/GrayCounter.blif | 51 + .../VIB/VIB_test_benchmarks/LCDmodule.blif | 389 + .../VIB_test_benchmarks/LED_BCD8x7seg.blif | 918 + .../VIB/VIB_test_benchmarks/Murax.blif | 19659 ++++++ .../VIB/VIB_test_benchmarks/PWM.blif | 574 + .../PushButton_Debouncer.blif | 204 + .../VIB/VIB_test_benchmarks/RCServo.blif | 735 + .../TaskAck_CrossDomain.blif | 53 + .../VIB/VIB_test_benchmarks/VexRiscv.blif | 10133 +++ .../VIB_test_benchmarks/VexRiscv_full.blif | 34792 ++++++++++ .../VIB_test_benchmarks/VexRiscv_small.blif | 10133 +++ .../VIB/VIB_test_benchmarks/boxcar.blif | 1473 + .../VIB/VIB_test_benchmarks/cordic.blif | 27532 ++++++++ .../VIB/VIB_test_benchmarks/cordictanh.blif | 19093 ++++++ .../VIB/VIB_test_benchmarks/picorv32.blif | 15942 +++++ .../VIB/VIB_test_benchmarks/pong.blif | 1394 + .../VIB/VIB_test_benchmarks/quad.blif | 135 + .../VIB/VIB_test_benchmarks/seqcordic.blif | 4862 ++ .../VIB/VIB_test_benchmarks/seqpolar.blif | 6314 ++ .../VIB/VIB_test_benchmarks/smplfir.blif | 525 + .../VIB/VIB_test_benchmarks/topolar.blif | 36396 +++++++++++ .../VIB/VIB_test_benchmarks/zipcore.blif | 54152 ++++++++++++++++ 23 files changed, 247749 insertions(+) create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/pong.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif create mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif new file mode 100644 index 00000000000..884a1ede974 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif @@ -0,0 +1,2290 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model Divide +.inputs clk reset start A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[19] A[20] A[21] A[22] A[23] A[24] A[25] A[26] A[27] A[28] A[29] A[30] A[31] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] B[8] B[9] B[10] B[11] B[12] B[13] B[14] B[15] B[16] B[17] B[18] B[19] B[20] B[21] B[22] B[23] B[24] B[25] B[26] B[27] B[28] B[29] B[30] B[31] +.outputs D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] D[16] D[17] D[18] D[19] D[20] D[21] D[22] D[23] D[24] D[25] D[26] D[27] D[28] D[29] D[30] D[31] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] R[8] R[9] R[10] R[11] R[12] R[13] R[14] R[15] R[16] R[17] R[18] R[19] R[20] R[21] R[22] R[23] R[24] R[25] R[26] R[27] R[28] R[29] R[30] R[31] ok err +.names $false +.names $true +1 +.names $undef +.names start active denom[30] B[30] $abc$1738$auto$rtlil.cc:2693:MuxGate$1342 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[29] B[29] $abc$1738$auto$rtlil.cc:2693:MuxGate$1344 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[28] B[28] $abc$1738$auto$rtlil.cc:2693:MuxGate$1346 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[27] B[27] $abc$1738$auto$rtlil.cc:2693:MuxGate$1348 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[26] B[26] $abc$1738$auto$rtlil.cc:2693:MuxGate$1350 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[25] B[25] $abc$1738$auto$rtlil.cc:2693:MuxGate$1352 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[24] B[24] $abc$1738$auto$rtlil.cc:2693:MuxGate$1354 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[23] B[23] $abc$1738$auto$rtlil.cc:2693:MuxGate$1356 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[22] B[22] $abc$1738$auto$rtlil.cc:2693:MuxGate$1358 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[21] B[21] $abc$1738$auto$rtlil.cc:2693:MuxGate$1360 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[20] B[20] $abc$1738$auto$rtlil.cc:2693:MuxGate$1362 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[19] B[19] $abc$1738$auto$rtlil.cc:2693:MuxGate$1364 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[18] B[18] $abc$1738$auto$rtlil.cc:2693:MuxGate$1366 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[17] B[17] $abc$1738$auto$rtlil.cc:2693:MuxGate$1368 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[16] B[16] $abc$1738$auto$rtlil.cc:2693:MuxGate$1370 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[15] B[15] $abc$1738$auto$rtlil.cc:2693:MuxGate$1372 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[14] B[14] $abc$1738$auto$rtlil.cc:2693:MuxGate$1374 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[13] B[13] $abc$1738$auto$rtlil.cc:2693:MuxGate$1376 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[12] B[12] $abc$1738$auto$rtlil.cc:2693:MuxGate$1378 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[11] B[11] $abc$1738$auto$rtlil.cc:2693:MuxGate$1380 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[10] B[10] $abc$1738$auto$rtlil.cc:2693:MuxGate$1382 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[9] B[9] $abc$1738$auto$rtlil.cc:2693:MuxGate$1384 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[8] B[8] $abc$1738$auto$rtlil.cc:2693:MuxGate$1386 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[7] B[7] $abc$1738$auto$rtlil.cc:2693:MuxGate$1388 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[6] B[6] $abc$1738$auto$rtlil.cc:2693:MuxGate$1390 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[5] B[5] $abc$1738$auto$rtlil.cc:2693:MuxGate$1392 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[4] B[4] $abc$1738$auto$rtlil.cc:2693:MuxGate$1394 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[3] B[3] $abc$1738$auto$rtlil.cc:2693:MuxGate$1396 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[2] B[2] $abc$1738$auto$rtlil.cc:2693:MuxGate$1398 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[1] B[1] $abc$1738$auto$rtlil.cc:2693:MuxGate$1400 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[0] B[0] $abc$1738$auto$rtlil.cc:2693:MuxGate$1402 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active D[30] D[29] A[30] $abc$1738$auto$rtlil.cc:2693:MuxGate$1404 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[29] D[28] A[29] $abc$1738$auto$rtlil.cc:2693:MuxGate$1406 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[28] D[27] A[28] $abc$1738$auto$rtlil.cc:2693:MuxGate$1408 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[27] D[26] A[27] $abc$1738$auto$rtlil.cc:2693:MuxGate$1410 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[26] D[25] A[26] $abc$1738$auto$rtlil.cc:2693:MuxGate$1412 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[25] D[24] A[25] $abc$1738$auto$rtlil.cc:2693:MuxGate$1414 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[24] D[23] A[24] $abc$1738$auto$rtlil.cc:2693:MuxGate$1416 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[23] D[22] A[23] $abc$1738$auto$rtlil.cc:2693:MuxGate$1418 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[22] D[21] A[22] $abc$1738$auto$rtlil.cc:2693:MuxGate$1420 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[21] D[20] A[21] $abc$1738$auto$rtlil.cc:2693:MuxGate$1422 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[20] D[19] A[20] $abc$1738$auto$rtlil.cc:2693:MuxGate$1424 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[19] D[18] A[19] $abc$1738$auto$rtlil.cc:2693:MuxGate$1426 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[18] D[17] A[18] $abc$1738$auto$rtlil.cc:2693:MuxGate$1428 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[17] D[16] A[17] $abc$1738$auto$rtlil.cc:2693:MuxGate$1430 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[16] D[15] A[16] $abc$1738$auto$rtlil.cc:2693:MuxGate$1432 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[15] D[14] A[15] $abc$1738$auto$rtlil.cc:2693:MuxGate$1434 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[14] D[13] A[14] $abc$1738$auto$rtlil.cc:2693:MuxGate$1436 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[13] D[12] A[13] $abc$1738$auto$rtlil.cc:2693:MuxGate$1438 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[12] D[11] A[12] $abc$1738$auto$rtlil.cc:2693:MuxGate$1440 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[11] D[10] A[11] $abc$1738$auto$rtlil.cc:2693:MuxGate$1442 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[10] D[9] A[10] $abc$1738$auto$rtlil.cc:2693:MuxGate$1444 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[9] D[8] A[9] $abc$1738$auto$rtlil.cc:2693:MuxGate$1446 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[8] D[7] A[8] $abc$1738$auto$rtlil.cc:2693:MuxGate$1448 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[7] D[6] A[7] $abc$1738$auto$rtlil.cc:2693:MuxGate$1450 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[6] D[5] A[6] $abc$1738$auto$rtlil.cc:2693:MuxGate$1452 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[5] D[4] A[5] $abc$1738$auto$rtlil.cc:2693:MuxGate$1454 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[4] D[3] A[4] $abc$1738$auto$rtlil.cc:2693:MuxGate$1456 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[3] D[2] A[3] $abc$1738$auto$rtlil.cc:2693:MuxGate$1458 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[2] D[1] A[2] $abc$1738$auto$rtlil.cc:2693:MuxGate$1460 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[1] D[0] A[1] $abc$1738$auto$rtlil.cc:2693:MuxGate$1462 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[0] $abc$1738$new_n335 A[0] $abc$1738$auto$rtlil.cc:2693:MuxGate$1464 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names R[29] denom[30] denom[31] R[30] $abc$1738$new_n336 $abc$1738$new_n335 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names denom[28] R[27] R[28] denom[29] $abc$1738$new_n337 $abc$1738$new_n336 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[26] R[25] R[26] denom[27] $abc$1738$new_n338 $abc$1738$new_n337 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[24] R[23] R[24] denom[25] $abc$1738$new_n339 $abc$1738$new_n338 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[22] R[21] R[22] denom[23] $abc$1738$new_n340 $abc$1738$new_n339 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[20] R[19] R[20] denom[21] $abc$1738$new_n341 $abc$1738$new_n340 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[18] R[17] R[18] denom[19] $abc$1738$new_n342 $abc$1738$new_n341 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[16] R[15] R[16] denom[17] $abc$1738$new_n343 $abc$1738$new_n342 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[14] R[13] R[14] denom[15] $abc$1738$new_n344 $abc$1738$new_n343 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[12] R[11] R[12] denom[13] $abc$1738$new_n345 $abc$1738$new_n344 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[10] R[9] R[10] denom[11] $abc$1738$new_n346 $abc$1738$new_n345 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[8] R[7] R[8] denom[9] $abc$1738$new_n347 $abc$1738$new_n346 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[6] R[5] R[6] denom[7] $abc$1738$new_n348 $abc$1738$new_n347 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[4] R[3] R[4] denom[5] $abc$1738$new_n349 $abc$1738$new_n348 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[2] R[1] R[2] denom[3] $abc$1738$new_n350 $abc$1738$new_n349 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[0] D[31] R[0] denom[1] $abc$1738$new_n350 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names cycle[3] $abc$1738$new_n352 start active $abc$1738$auto$rtlil.cc:2693:MuxGate$1466 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names start cycle[0] cycle[1] cycle[2] $abc$1738$new_n352 +1000 1 +.names cycle[2] active start cycle[0] cycle[1] $abc$1738$auto$rtlil.cc:2693:MuxGate$1468 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names cycle[1] active start cycle[0] $abc$1738$auto$rtlil.cc:2693:MuxGate$1470 +0010 1 +0011 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names start cycle[0] active $abc$1738$auto$rtlil.cc:2693:MuxGate$1472 +010 1 +011 1 +100 1 +101 1 +110 1 +.names start R[30] active $abc$1738$new_n357 $abc$1738$new_n358 $abc$1738$auto$rtlil.cc:2693:MuxGate$1474 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names R[29] denom[31] R[30] $abc$1738$new_n357 +000 1 +010 1 +011 1 +.names denom[30] $abc$1738$new_n336 R[29] R[30] denom[31] $abc$1738$new_n358 +00000 1 +00010 1 +00011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10110 1 +10111 1 +11010 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n362 $abc$1738$new_n360 R[28] $abc$1738$auto$rtlil.cc:2693:MuxGate$1476 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[28] denom[29] R[27] denom[28] $abc$1738$new_n337 $abc$1738$new_n360 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names active start $abc$1738$new_n361 +11 1 +.names R[29] start $abc$1738$new_n362 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n368 $abc$1738$new_n367 R[26] $abc$1738$auto$rtlil.cc:2693:MuxGate$1480 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[26] denom[27] R[25] denom[26] $abc$1738$new_n338 $abc$1738$new_n367 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[27] start $abc$1738$new_n368 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n374 $abc$1738$new_n373 R[24] $abc$1738$auto$rtlil.cc:2693:MuxGate$1484 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[24] denom[25] R[23] denom[24] $abc$1738$new_n339 $abc$1738$new_n373 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[25] start $abc$1738$new_n374 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n380 $abc$1738$new_n379 R[22] $abc$1738$auto$rtlil.cc:2693:MuxGate$1488 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[22] denom[23] R[21] denom[22] $abc$1738$new_n340 $abc$1738$new_n379 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[23] start $abc$1738$new_n380 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n386 $abc$1738$new_n385 R[20] $abc$1738$auto$rtlil.cc:2693:MuxGate$1492 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[20] denom[21] R[19] denom[20] $abc$1738$new_n341 $abc$1738$new_n385 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[21] start $abc$1738$new_n386 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n392 $abc$1738$new_n391 R[18] $abc$1738$auto$rtlil.cc:2693:MuxGate$1496 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[18] denom[19] R[17] denom[18] $abc$1738$new_n342 $abc$1738$new_n391 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[19] start $abc$1738$new_n392 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n398 $abc$1738$new_n397 R[16] $abc$1738$auto$rtlil.cc:2693:MuxGate$1500 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[16] denom[17] R[15] denom[16] $abc$1738$new_n343 $abc$1738$new_n397 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[17] start $abc$1738$new_n398 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n404 $abc$1738$new_n403 R[14] $abc$1738$auto$rtlil.cc:2693:MuxGate$1504 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[14] denom[15] R[13] denom[14] $abc$1738$new_n344 $abc$1738$new_n403 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[15] start $abc$1738$new_n404 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n410 $abc$1738$new_n409 R[12] $abc$1738$auto$rtlil.cc:2693:MuxGate$1508 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[12] denom[13] R[11] denom[12] $abc$1738$new_n345 $abc$1738$new_n409 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[13] start $abc$1738$new_n410 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n416 $abc$1738$new_n415 R[10] $abc$1738$auto$rtlil.cc:2693:MuxGate$1512 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[10] denom[11] R[9] denom[10] $abc$1738$new_n346 $abc$1738$new_n415 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[11] start $abc$1738$new_n416 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n422 $abc$1738$new_n421 R[8] $abc$1738$auto$rtlil.cc:2693:MuxGate$1516 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[8] denom[9] R[7] denom[8] $abc$1738$new_n347 $abc$1738$new_n421 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[9] start $abc$1738$new_n422 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n428 $abc$1738$new_n427 R[6] $abc$1738$auto$rtlil.cc:2693:MuxGate$1520 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[6] denom[7] R[5] denom[6] $abc$1738$new_n348 $abc$1738$new_n427 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[7] start $abc$1738$new_n428 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n434 $abc$1738$new_n433 R[4] $abc$1738$auto$rtlil.cc:2693:MuxGate$1524 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[4] denom[5] R[3] denom[4] $abc$1738$new_n349 $abc$1738$new_n433 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[5] start $abc$1738$new_n434 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n440 $abc$1738$new_n439 R[2] $abc$1738$auto$rtlil.cc:2693:MuxGate$1528 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[2] denom[3] R[1] denom[2] $abc$1738$new_n350 $abc$1738$new_n439 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[3] start $abc$1738$new_n440 +10 1 +.names $abc$1738$new_n361 D[31] denom[0] $abc$1738$new_n335 $abc$1738$new_n448 $abc$1738$auto$rtlil.cc:2693:MuxGate$1534 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names R[0] start $abc$1738$new_n448 +10 1 +.names start R[31] active R[30] $abc$1738$new_n450 $abc$1738$auto$rtlil.cc:2693:MuxGate$1536 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names denom[31] R[29] denom[30] $abc$1738$new_n336 $abc$1738$new_n450 +0001 1 +0010 1 +0011 1 +0111 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names start active denom[31] B[31] $abc$1738$auto$rtlil.cc:2693:MuxGate$1538 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active D[31] D[30] A[31] $abc$1738$auto$rtlil.cc:2693:MuxGate$1540 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names cycle[4] $abc$1738$new_n352 cycle[3] start active $abc$1738$auto$rtlil.cc:2693:MuxGate$1542 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names active start $abc$1738$new_n352 cycle[4] cycle[3] $abc$1738$auto$rtlil.cc:2693:MuxGate$1544 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$1738$new_n462 $abc$1738$new_n460 $abc$1738$new_n458 $abc$1738$new_n456 err +1111 1 +.names $abc$1738$new_n457 B[31] B[0] B[1] B[2] $abc$1738$new_n456 +10000 1 +.names B[3] B[4] B[5] B[6] $abc$1738$new_n457 +0000 1 +.names $abc$1738$new_n459 B[11] B[12] B[13] B[14] $abc$1738$new_n458 +10000 1 +.names B[7] B[8] B[9] B[10] $abc$1738$new_n459 +0000 1 +.names $abc$1738$new_n461 B[19] B[20] B[21] B[22] $abc$1738$new_n460 +10000 1 +.names B[15] B[16] B[17] B[18] $abc$1738$new_n461 +0000 1 +.names $abc$1738$new_n463 B[27] B[28] B[29] B[30] $abc$1738$new_n462 +10000 1 +.names B[23] B[24] B[25] B[26] $abc$1738$new_n463 +0000 1 +.names active ok +0 1 +.names start $abc$1738$new_n337 denom[28] R[28] $abc$1738$new_n465 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[27] start $abc$1738$new_n465 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1478 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n338 denom[26] R[26] $abc$1738$new_n467 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[25] start $abc$1738$new_n467 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1482 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n339 denom[24] R[24] $abc$1738$new_n469 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[23] start $abc$1738$new_n469 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1486 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n340 denom[22] R[22] $abc$1738$new_n471 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[21] start $abc$1738$new_n471 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1490 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n341 denom[20] R[20] $abc$1738$new_n473 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[19] start $abc$1738$new_n473 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1494 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n342 denom[18] R[18] $abc$1738$new_n475 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[17] start $abc$1738$new_n475 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1498 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n343 denom[16] R[16] $abc$1738$new_n477 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[15] start $abc$1738$new_n477 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1502 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n344 denom[14] R[14] $abc$1738$new_n479 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[13] start $abc$1738$new_n479 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1506 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n345 denom[12] R[12] $abc$1738$new_n481 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[11] start $abc$1738$new_n481 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1510 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n346 denom[10] R[10] $abc$1738$new_n483 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[9] start $abc$1738$new_n483 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1514 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n347 denom[8] R[8] $abc$1738$new_n485 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[7] start $abc$1738$new_n485 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1518 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n348 denom[6] R[6] $abc$1738$new_n487 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[5] start $abc$1738$new_n487 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1522 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n349 denom[4] R[4] $abc$1738$new_n489 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[3] start $abc$1738$new_n489 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1526 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n350 denom[2] R[2] $abc$1738$new_n491 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[1] start $abc$1738$new_n491 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1530 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start denom[1] denom[0] D[31] R[1] $abc$1738$new_n493 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names active R[0] start $abc$1738$new_n493 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1532 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1534 Q=R[0] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1532 Q=R[1] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1530 Q=R[2] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1528 Q=R[3] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1526 Q=R[4] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1524 Q=R[5] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1522 Q=R[6] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1520 Q=R[7] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1518 Q=R[8] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1516 Q=R[9] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1514 Q=R[10] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1512 Q=R[11] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1510 Q=R[12] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1508 Q=R[13] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1506 Q=R[14] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1504 Q=R[15] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1502 Q=R[16] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1500 Q=R[17] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1498 Q=R[18] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1496 Q=R[19] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1494 Q=R[20] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1492 Q=R[21] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1490 Q=R[22] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1488 Q=R[23] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1486 Q=R[24] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1484 Q=R[25] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1482 Q=R[26] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1480 Q=R[27] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1478 Q=R[28] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1476 Q=R[29] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1474 Q=R[30] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1536 Q=R[31] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1544 Q=active R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1472 Q=cycle[0] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1470 Q=cycle[1] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1468 Q=cycle[2] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1466 Q=cycle[3] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1542 Q=cycle[4] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1464 Q=D[0] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1462 Q=D[1] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1460 Q=D[2] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1458 Q=D[3] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1456 Q=D[4] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1454 Q=D[5] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1452 Q=D[6] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1450 Q=D[7] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1448 Q=D[8] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1446 Q=D[9] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1444 Q=D[10] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1442 Q=D[11] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1440 Q=D[12] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1438 Q=D[13] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1436 Q=D[14] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1434 Q=D[15] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1432 Q=D[16] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1430 Q=D[17] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1428 Q=D[18] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1426 Q=D[19] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1424 Q=D[20] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1422 Q=D[21] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1420 Q=D[22] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1418 Q=D[23] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1416 Q=D[24] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1414 Q=D[25] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1412 Q=D[26] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1410 Q=D[27] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1408 Q=D[28] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1406 Q=D[29] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1404 Q=D[30] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1540 Q=D[31] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1402 Q=denom[0] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1400 Q=denom[1] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1398 Q=denom[2] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1396 Q=denom[3] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1394 Q=denom[4] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1392 Q=denom[5] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1390 Q=denom[6] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1388 Q=denom[7] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1386 Q=denom[8] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1384 Q=denom[9] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1382 Q=denom[10] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1380 Q=denom[11] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1378 Q=denom[12] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1376 Q=denom[13] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1374 Q=denom[14] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1372 Q=denom[15] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1370 Q=denom[16] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1368 Q=denom[17] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1366 Q=denom[18] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1364 Q=denom[19] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1362 Q=denom[20] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1360 Q=denom[21] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1358 Q=denom[22] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1356 Q=denom[23] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1354 Q=denom[24] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1352 Q=denom[25] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1350 Q=denom[26] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1348 Q=denom[27] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1346 Q=denom[28] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1344 Q=denom[29] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1342 Q=denom[30] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1538 Q=denom[31] R=reset +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif new file mode 100644 index 00000000000..dec03bfebde --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif @@ -0,0 +1,51 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model GrayCounter +.inputs clk +.outputs cnt_gray[0] cnt_gray[1] cnt_gray[2] cnt_gray[3] +.names $false +.names $true +1 +.names $undef +.names cnt[2] cnt[1] cnt_gray[1] +01 1 +10 1 +.names cnt_gray[3] cnt[2] cnt_gray[2] +01 1 +10 1 +.names cnt[1] cnt[0] cnt_gray[0] +01 1 +10 1 +.names cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$401.Y[2] +011 1 +100 1 +101 1 +110 1 +.names cnt_gray[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$401.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[0] $auto$alumacc.cc:485:replace_alu$401.X[0] +0 1 +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.X[0] Q=cnt[0] +.subckt dff C=clk D=cnt_gray[0] Q=cnt[1] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.Y[2] Q=cnt[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.Y[3] Q=cnt_gray[3] +.names cnt[1] $auto$alumacc.cc:485:replace_alu$401.X[1] +1 1 +.names cnt[2] $auto$alumacc.cc:485:replace_alu$401.X[2] +1 1 +.names cnt_gray[3] $auto$alumacc.cc:485:replace_alu$401.X[3] +1 1 +.names $auto$alumacc.cc:485:replace_alu$401.X[0] $auto$alumacc.cc:485:replace_alu$401.Y[0] +1 1 +.names cnt_gray[0] $auto$alumacc.cc:485:replace_alu$401.Y[1] +1 1 +.names cnt_gray[3] cnt[3] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif new file mode 100644 index 00000000000..429f2a124a8 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif @@ -0,0 +1,389 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model LCDmodule +.inputs clk RxD +.outputs LCD_RS LCD_RW LCD_E LCD_DataBus[0] LCD_DataBus[1] LCD_DataBus[2] LCD_DataBus[3] LCD_DataBus[4] LCD_DataBus[5] LCD_DataBus[6] LCD_DataBus[7] +.names $false +.names $true +1 +.names $undef +.names count[0] count[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1481 +01 1 +10 1 +.names count[0] $0\LCD_E[0:0] deserialer.RxD_data_ready $abc$1754$auto$rtlil.cc:2693:MuxGate$1483 +001 1 +010 1 +011 1 +.names count[2] count[0] count[1] $0\LCD_E[0:0] +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names deserialer.OversamplingTick deserialer.Filter_cnt[0] deserialer.Filter_cnt[1] deserialer.RxD_sync[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1485 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$1754$new_n83 LCD_RS LCD_DataBus[6] $abc$1754$auto$rtlil.cc:2693:MuxGate$1487 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_state[3] $abc$1754$new_n84 $abc$1754$new_n83 +11 1 +.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick deserialer.OversamplingCnt[2] $abc$1754$new_n84 +1110 1 +.names $abc$1754$new_n83 LCD_DataBus[6] LCD_DataBus[5] $abc$1754$auto$rtlil.cc:2693:MuxGate$1489 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[5] LCD_DataBus[4] $abc$1754$auto$rtlil.cc:2693:MuxGate$1491 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[4] LCD_DataBus[3] $abc$1754$auto$rtlil.cc:2693:MuxGate$1493 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[3] LCD_DataBus[2] $abc$1754$auto$rtlil.cc:2693:MuxGate$1495 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[2] LCD_DataBus[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1497 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[1] LCD_DataBus[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1499 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick $abc$1754$new_n92 $abc$1754$auto$rtlil.cc:2693:MuxGate$1503 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$1754$new_n92 +0000 1 +.names deserialer.OversamplingTick deserialer.OversamplingCnt[0] $abc$1754$new_n92 $abc$1754$auto$rtlil.cc:2693:MuxGate$1507 +010 1 +011 1 +100 1 +.names deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$1754$new_n95 deserialer.RxD_state[2] $abc$1754$auto$rtlil.cc:2693:MuxGate$1509 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$1754$new_n96 $abc$1754$new_n84 deserialer.RxD_bit $abc$1754$new_n92 $abc$1754$new_n95 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[1] deserialer.RxD_state[0] deserialer.RxD_state[2] $abc$1754$new_n96 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names $abc$1754$new_n95 deserialer.RxD_state[0] $abc$1754$new_n92 deserialer.RxD_state[3] $abc$1754$auto$rtlil.cc:2693:MuxGate$1511 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names deserialer.OversamplingTick RxD deserialer.RxD_sync[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1513 +001 1 +011 1 +110 1 +111 1 +.names count[2] count[0] count[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1515 +011 1 +100 1 +101 1 +110 1 +.names deserialer.OversamplingTick deserialer.RxD_sync[0] deserialer.RxD_sync[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1517 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_bit deserialer.Filter_cnt[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1521 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserialer.Filter_cnt[1] deserialer.RxD_sync[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1523 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserialer.OversamplingCnt[2] $abc$1754$new_n92 deserialer.OversamplingCnt[0] deserialer.OversamplingCnt[1] deserialer.OversamplingTick $abc$1754$auto$rtlil.cc:2693:MuxGate$1527 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$1754$new_n83 deserialer.RxD_bit LCD_RS $abc$1754$auto$rtlil.cc:2693:MuxGate$1529 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_state[2] deserialer.RxD_state[3] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$1754$new_n95 $abc$1754$auto$rtlil.cc:2693:MuxGate$1533 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$1754$new_n95 deserialer.RxD_state[2] deserialer.RxD_state[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1535 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$1754$new_n108 $abc$1754$new_n84 $abc$1754$flatten\deserialer.$0\RxD_data_ready[0:0] +11 1 +.names deserialer.RxD_bit deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] $abc$1754$new_n108 +11000 1 +.names deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[1] +00 1 +11 1 +.names deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[2] +000 1 +101 1 +110 1 +111 1 +.names deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[3] +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[4] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[5] +00 1 +11 1 +.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $abc$1754$new_n114 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[6] +010 1 +100 1 +101 1 +111 1 +.names deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1110 1 +.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[8] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[9] +01 1 +10 1 +.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $abc$1754$new_n119 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[10] +011 1 +100 1 +101 1 +110 1 +.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.CO[11] +1111 1 +.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.X[0] +0 1 +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1521 Q=deserialer.RxD_bit +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1485 Q=deserialer.Filter_cnt[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1523 Q=deserialer.Filter_cnt[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1483 Q=count[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1481 Q=count[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1515 Q=count[2] +.subckt dff C=clk D=$0\LCD_E[0:0] Q=LCD_E +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1513 Q=deserialer.RxD_sync[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1517 Q=deserialer.RxD_sync[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1511 Q=deserialer.RxD_state[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1509 Q=deserialer.RxD_state[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1535 Q=deserialer.RxD_state[3] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1533 Q=deserialer.RxD_state[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.X[0] Q=deserialer.tickgen.Acc[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[1] Q=deserialer.tickgen.Acc[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[2] Q=deserialer.tickgen.Acc[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[3] Q=deserialer.tickgen.Acc[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[4] Q=deserialer.tickgen.Acc[8] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[5] Q=deserialer.tickgen.Acc[9] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[6] Q=deserialer.tickgen.Acc[10] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[7] Q=deserialer.tickgen.Acc[11] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[8] Q=deserialer.tickgen.Acc[12] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[9] Q=deserialer.tickgen.Acc[13] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[10] Q=deserialer.tickgen.Acc[14] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[11] Q=deserialer.tickgen.Acc[15] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.CO[11] Q=deserialer.OversamplingTick +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1507 Q=deserialer.OversamplingCnt[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1503 Q=deserialer.OversamplingCnt[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1527 Q=deserialer.OversamplingCnt[2] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1499 Q=LCD_DataBus[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1497 Q=LCD_DataBus[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1495 Q=LCD_DataBus[2] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1493 Q=LCD_DataBus[3] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1491 Q=LCD_DataBus[4] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1489 Q=LCD_DataBus[5] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1487 Q=LCD_DataBus[6] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1529 Q=LCD_RS +.subckt dff C=clk D=$abc$1754$flatten\deserialer.$0\RxD_data_ready[0:0] Q=deserialer.RxD_data_ready +.names deserialer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$595.X[3] +1 1 +.names deserialer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$595.X[5] +1 1 +.names deserialer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$595.X[6] +1 1 +.names deserialer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$595.X[8] +1 1 +.names deserialer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$595.X[9] +1 1 +.names deserialer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$595.X[10] +1 1 +.names deserialer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$595.X[11] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$595.X[12] +1 1 +.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.CO[0] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$595.CO[12] +1 1 +.names $false LCD_DataBus[7] +1 1 +.names $false LCD_RW +1 1 +.names deserialer.OversamplingTick deserialer.tickgen.Acc[16] +1 1 +.names $auto$alumacc.cc:485:replace_alu$595.X[0] $auto$alumacc.cc:485:replace_alu$595.Y[0] +1 1 +.names $auto$alumacc.cc:485:replace_alu$595.CO[11] $auto$alumacc.cc:485:replace_alu$595.Y[12] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif new file mode 100644 index 00000000000..7228a4d4759 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif @@ -0,0 +1,918 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model LED_BCD8x7seg +.inputs clk +.outputs segA segB segC segD segE segF segG segDP seg_cathode[0] seg_cathode[1] seg_cathode[2] seg_cathode[3] seg_cathode[4] seg_cathode[5] seg_cathode[6] seg_cathode[7] +.names $false +.names $true +1 +.names $undef +.names BCD.BCD_digits[2] BCD.BCD_digits[1] $abc$1987$new_n130 $abc$1987$auto$rtlil.cc:2693:MuxGate$1679 +011 1 +100 1 +101 1 +110 1 +.names cnt[23] BCD.BCD_digits[0] $abc$1987$new_n131 $abc$1987$new_n130 +111 1 +.names cnt[22] cnt[21] cnt[20] cnt[19] $abc$1987$new_n132 $abc$1987$new_n131 +11111 1 +.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 seg_cathode[7] $abc$1987$new_n132 +11110 1 +.names cnt[12] cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $abc$1987$new_n133 +11111 1 +.names cnt[8] cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $abc$1987$new_n134 +11111 1 +.names cnt[4] cnt[3] cnt[2] cnt[1] cnt[0] $abc$1987$new_n135 +11111 1 +.names cnt[17] cnt[16] cnt[18] seg_cathode[7] +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[1] $abc$1987$new_n130 $abc$1987$new_n138 $abc$1987$auto$rtlil.cc:2693:MuxGate$1683 +010 1 +100 1 +.names BCD.BCD_digits[3] BCD.BCD_digits[1] BCD.BCD_digits[2] $abc$1987$new_n138 +100 1 +.names BCD.BCD_digits[0] cnt[23] $abc$1987$new_n131 $abc$1987$auto$rtlil.cc:2693:MuxGate$1687 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[6] BCD.BCD_digits[4] BCD.BCD_digits[5] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1691 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$1987$new_n138 $abc$1987$new_n130 $abc$1987$new_n141 +11 1 +.names BCD.BCD_digits[5] BCD.BCD_digits[4] $abc$1987$new_n141 BCD.BCD_digits[6] BCD.BCD_digits[7] $abc$1987$auto$rtlil.cc:2693:MuxGate$1695 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names BCD.BCD_digits[4] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1699 +01 1 +10 1 +.names BCD.BCD_digits[10] BCD.BCD_digits[8] BCD.BCD_digits[9] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1703 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[23] BCD.BCD_digits[0] $abc$1987$new_n146 $abc$1987$new_n138 $abc$1987$new_n131 $abc$1987$new_n145 +11111 1 +.names BCD.BCD_digits[7] BCD.BCD_digits[4] BCD.BCD_digits[5] BCD.BCD_digits[6] $abc$1987$new_n146 +1100 1 +.names BCD.BCD_digits[9] BCD.BCD_digits[8] $abc$1987$new_n145 BCD.BCD_digits[10] BCD.BCD_digits[11] $abc$1987$auto$rtlil.cc:2693:MuxGate$1707 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names BCD.BCD_digits[8] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1711 +01 1 +10 1 +.names BCD.BCD_digits[14] BCD.BCD_digits[13] $abc$1987$new_n150 $abc$1987$auto$rtlil.cc:2693:MuxGate$1715 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$new_n150 +11 1 +.names $abc$1987$new_n152 $abc$1987$new_n145 $abc$1987$new_n151 +11 1 +.names BCD.BCD_digits[11] BCD.BCD_digits[8] BCD.BCD_digits[9] BCD.BCD_digits[10] $abc$1987$new_n152 +1100 1 +.names $abc$1987$new_n150 BCD.BCD_digits[13] BCD.BCD_digits[14] BCD.BCD_digits[15] $abc$1987$auto$rtlil.cc:2693:MuxGate$1719 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +.names BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$auto$rtlil.cc:2693:MuxGate$1723 +01 1 +10 1 +.names BCD.BCD_digits[18] BCD.BCD_digits[16] BCD.BCD_digits[17] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1727 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$1987$new_n157 $abc$1987$new_n151 $abc$1987$new_n156 +11 1 +.names BCD.BCD_digits[15] BCD.BCD_digits[12] BCD.BCD_digits[13] BCD.BCD_digits[14] $abc$1987$new_n157 +1100 1 +.names BCD.BCD_digits[17] BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$new_n159 $abc$1987$auto$rtlil.cc:2693:MuxGate$1731 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BCD.BCD_digits[19] BCD.BCD_digits[18] $abc$1987$new_n159 +10 1 +.names BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1735 +01 1 +10 1 +.names BCD.BCD_digits[22] BCD.BCD_digits[20] BCD.BCD_digits[21] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1739 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$1987$new_n157 $abc$1987$new_n163 $abc$1987$new_n151 $abc$1987$new_n162 +111 1 +.names BCD.BCD_digits[16] $abc$1987$new_n159 BCD.BCD_digits[17] $abc$1987$new_n163 +110 1 +.names BCD.BCD_digits[21] BCD.BCD_digits[20] $abc$1987$new_n162 BCD.BCD_digits[22] BCD.BCD_digits[23] $abc$1987$auto$rtlil.cc:2693:MuxGate$1743 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names BCD.BCD_digits[20] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1747 +01 1 +10 1 +.names BCD.BCD_digits[26] BCD.BCD_digits[25] $abc$1987$new_n167 $abc$1987$auto$rtlil.cc:2693:MuxGate$1751 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$new_n167 +11 1 +.names $abc$1987$new_n169 $abc$1987$new_n157 $abc$1987$new_n152 $abc$1987$new_n163 $abc$1987$new_n145 $abc$1987$new_n168 +11111 1 +.names BCD.BCD_digits[23] BCD.BCD_digits[20] BCD.BCD_digits[21] BCD.BCD_digits[22] $abc$1987$new_n169 +1100 1 +.names $abc$1987$new_n167 BCD.BCD_digits[25] BCD.BCD_digits[26] BCD.BCD_digits[27] $abc$1987$auto$rtlil.cc:2693:MuxGate$1755 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +.names BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1759 +01 1 +10 1 +.names BCD.BCD_digits[30] BCD.BCD_digits[29] $abc$1987$new_n173 $abc$1987$auto$rtlil.cc:2693:MuxGate$1763 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[28] $abc$1987$new_n174 $abc$1987$new_n168 $abc$1987$new_n173 +111 1 +.names BCD.BCD_digits[27] BCD.BCD_digits[24] BCD.BCD_digits[25] BCD.BCD_digits[26] $abc$1987$new_n174 +1100 1 +.names $abc$1987$new_n173 BCD.BCD_digits[29] BCD.BCD_digits[30] BCD.BCD_digits[31] $abc$1987$auto$rtlil.cc:2693:MuxGate$1767 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +.names BCD.BCD_digits[28] $abc$1987$new_n174 $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1771 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[31] BCD.BCD_digits[29] BCD.BCD_digits[30] $abc$1987$new_n173 $abc$1987$auto$rtlil.cc:2693:MuxGate$1775 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names BCD.BCD_digits[27] BCD.BCD_digits[25] BCD.BCD_digits[26] BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1779 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[23] BCD.BCD_digits[21] BCD.BCD_digits[22] BCD.BCD_digits[20] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1783 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[19] BCD.BCD_digits[17] BCD.BCD_digits[18] BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1787 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[15] BCD.BCD_digits[13] BCD.BCD_digits[14] BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$auto$rtlil.cc:2693:MuxGate$1791 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[11] BCD.BCD_digits[9] BCD.BCD_digits[10] BCD.BCD_digits[8] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1795 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[7] BCD.BCD_digits[5] BCD.BCD_digits[6] BCD.BCD_digits[4] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1799 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[3] BCD.BCD_digits[1] BCD.BCD_digits[2] $abc$1987$new_n130 $abc$1987$auto$rtlil.cc:2693:MuxGate$1803 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[16] cnt[17] cnt[18] seg_cathode[1] +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names cnt[17] cnt[16] cnt[18] seg_cathode[2] +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names cnt[17] cnt[16] cnt[18] seg_cathode[3] +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names cnt[18] cnt[17] cnt[16] seg_cathode[4] +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names cnt[18] cnt[16] cnt[17] seg_cathode[5] +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names cnt[17] cnt[18] cnt[16] seg_cathode[6] +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names cnt[17] cnt[16] cnt[18] seg_cathode[0] +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n208 segG +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names cnt[18] $abc$1987$new_n194 $abc$1987$new_n196 $abc$1987$new_n193 +010 1 +011 1 +101 1 +111 1 +.names cnt[17] cnt[16] $abc$1987$new_n195 BCD.BCD_digits[10] BCD.BCD_digits[14] $abc$1987$new_n194 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names seg_cathode[1] BCD.BCD_digits[2] BCD.BCD_digits[6] $abc$1987$new_n195 +000 1 +010 1 +100 1 +101 1 +.names $abc$1987$new_n197 cnt[16] cnt[17] BCD.BCD_digits[26] BCD.BCD_digits[30] $abc$1987$new_n196 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names cnt[16] cnt[18] cnt[17] BCD.BCD_digits[18] BCD.BCD_digits[22] $abc$1987$new_n197 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names cnt[18] $abc$1987$new_n199 $abc$1987$new_n201 $abc$1987$new_n202 $abc$1987$new_n198 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names cnt[17] cnt[16] $abc$1987$new_n200 BCD.BCD_digits[31] BCD.BCD_digits[27] $abc$1987$new_n199 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names seg_cathode[5] BCD.BCD_digits[19] BCD.BCD_digits[23] $abc$1987$new_n200 +000 1 +010 1 +100 1 +101 1 +.names seg_cathode[3] BCD.BCD_digits[15] cnt[17] BCD.BCD_digits[11] $abc$1987$new_n201 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names cnt[16] cnt[17] cnt[18] BCD.BCD_digits[3] BCD.BCD_digits[7] $abc$1987$new_n202 +00010 1 +00011 1 +00110 1 +00111 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names cnt[17] $abc$1987$new_n204 $abc$1987$new_n206 $abc$1987$new_n203 +001 1 +011 1 +110 1 +111 1 +.names cnt[18] cnt[16] $abc$1987$new_n205 BCD.BCD_digits[25] BCD.BCD_digits[29] $abc$1987$new_n204 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names cnt[16] BCD.BCD_digits[9] BCD.BCD_digits[13] $abc$1987$new_n205 +000 1 +001 1 +100 1 +110 1 +.names cnt[18] cnt[16] $abc$1987$new_n207 BCD.BCD_digits[17] BCD.BCD_digits[21] $abc$1987$new_n206 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names cnt[16] BCD.BCD_digits[1] BCD.BCD_digits[5] $abc$1987$new_n207 +000 1 +001 1 +100 1 +110 1 +.names cnt[18] $abc$1987$new_n209 $abc$1987$new_n211 $abc$1987$new_n208 +001 1 +011 1 +110 1 +111 1 +.names seg_cathode[7] $abc$1987$new_n210 BCD.BCD_digits[24] cnt[17] BCD.BCD_digits[28] $abc$1987$new_n209 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names cnt[16] cnt[17] BCD.BCD_digits[16] BCD.BCD_digits[20] $abc$1987$new_n210 +0010 1 +0011 1 +1001 1 +1011 1 +.names seg_cathode[3] $abc$1987$new_n212 BCD.BCD_digits[8] cnt[17] BCD.BCD_digits[12] $abc$1987$new_n211 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names cnt[16] cnt[17] BCD.BCD_digits[0] BCD.BCD_digits[4] $abc$1987$new_n212 +0010 1 +0011 1 +1001 1 +1011 1 +.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n208 segF +0110 1 +0111 1 +1001 1 +1100 1 +1101 1 +1111 1 +.names $abc$1987$new_n208 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n198 segE +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$1987$new_n203 $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n208 segD +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n203 $abc$1987$new_n208 segC +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n208 $abc$1987$new_n193 segB +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n203 $abc$1987$new_n208 segA +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[1] +01 1 +10 1 +.names cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[2] +011 1 +100 1 +101 1 +110 1 +.names cnt[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[4] cnt[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[5] +01 1 +10 1 +.names cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[6] +011 1 +100 1 +101 1 +110 1 +.names cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[8] cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[9] +01 1 +10 1 +.names cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[10] +011 1 +100 1 +101 1 +110 1 +.names cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[12] cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[13] +01 1 +10 1 +.names cnt[14] cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[14] +011 1 +100 1 +101 1 +110 1 +.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[16] +01 1 +10 1 +.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 $abc$1987$new_n235 +1111 1 +.names cnt[17] cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[17] +011 1 +100 1 +101 1 +110 1 +.names cnt[18] cnt[17] cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[18] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[19] $abc$1987$new_n132 $auto$alumacc.cc:485:replace_alu$473.Y[19] +01 1 +10 1 +.names cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[20] +01 1 +10 1 +.names cnt[19] $abc$1987$new_n132 $abc$1987$new_n240 +11 1 +.names cnt[21] cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[21] +011 1 +100 1 +101 1 +110 1 +.names cnt[22] cnt[21] cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[22] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[23] $abc$1987$new_n131 $auto$alumacc.cc:485:replace_alu$473.Y[23] +01 1 +10 1 +.names cnt[0] $auto$alumacc.cc:485:replace_alu$473.X[0] +0 1 +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.X[0] Q=cnt[0] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[1] Q=cnt[1] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[2] Q=cnt[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[3] Q=cnt[3] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[4] Q=cnt[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[5] Q=cnt[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[6] Q=cnt[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[7] Q=cnt[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[8] Q=cnt[8] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[9] Q=cnt[9] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[10] Q=cnt[10] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[11] Q=cnt[11] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[12] Q=cnt[12] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[13] Q=cnt[13] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[14] Q=cnt[14] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[15] Q=cnt[15] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[16] Q=cnt[16] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[17] Q=cnt[17] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[18] Q=cnt[18] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[19] Q=cnt[19] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[20] Q=cnt[20] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[21] Q=cnt[21] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[22] Q=cnt[22] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[23] Q=cnt[23] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1771 Q=BCD.BCD_digits[28] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1767 Q=BCD.BCD_digits[29] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1763 Q=BCD.BCD_digits[30] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1775 Q=BCD.BCD_digits[31] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1759 Q=BCD.BCD_digits[24] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1755 Q=BCD.BCD_digits[25] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1751 Q=BCD.BCD_digits[26] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1779 Q=BCD.BCD_digits[27] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1747 Q=BCD.BCD_digits[20] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1743 Q=BCD.BCD_digits[21] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1739 Q=BCD.BCD_digits[22] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1783 Q=BCD.BCD_digits[23] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1735 Q=BCD.BCD_digits[16] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1731 Q=BCD.BCD_digits[17] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1727 Q=BCD.BCD_digits[18] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1787 Q=BCD.BCD_digits[19] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1723 Q=BCD.BCD_digits[12] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1719 Q=BCD.BCD_digits[13] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1715 Q=BCD.BCD_digits[14] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1791 Q=BCD.BCD_digits[15] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1711 Q=BCD.BCD_digits[8] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1707 Q=BCD.BCD_digits[9] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1703 Q=BCD.BCD_digits[10] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1795 Q=BCD.BCD_digits[11] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1699 Q=BCD.BCD_digits[4] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1695 Q=BCD.BCD_digits[5] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1691 Q=BCD.BCD_digits[6] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1799 Q=BCD.BCD_digits[7] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1687 Q=BCD.BCD_digits[0] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1683 Q=BCD.BCD_digits[1] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1679 Q=BCD.BCD_digits[2] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1803 Q=BCD.BCD_digits[3] +.names cnt[1] $auto$alumacc.cc:485:replace_alu$473.X[1] +1 1 +.names cnt[2] $auto$alumacc.cc:485:replace_alu$473.X[2] +1 1 +.names cnt[3] $auto$alumacc.cc:485:replace_alu$473.X[3] +1 1 +.names cnt[4] $auto$alumacc.cc:485:replace_alu$473.X[4] +1 1 +.names cnt[5] $auto$alumacc.cc:485:replace_alu$473.X[5] +1 1 +.names cnt[6] $auto$alumacc.cc:485:replace_alu$473.X[6] +1 1 +.names cnt[7] $auto$alumacc.cc:485:replace_alu$473.X[7] +1 1 +.names cnt[8] $auto$alumacc.cc:485:replace_alu$473.X[8] +1 1 +.names cnt[9] $auto$alumacc.cc:485:replace_alu$473.X[9] +1 1 +.names cnt[10] $auto$alumacc.cc:485:replace_alu$473.X[10] +1 1 +.names cnt[11] $auto$alumacc.cc:485:replace_alu$473.X[11] +1 1 +.names cnt[12] $auto$alumacc.cc:485:replace_alu$473.X[12] +1 1 +.names cnt[13] $auto$alumacc.cc:485:replace_alu$473.X[13] +1 1 +.names cnt[14] $auto$alumacc.cc:485:replace_alu$473.X[14] +1 1 +.names cnt[15] $auto$alumacc.cc:485:replace_alu$473.X[15] +1 1 +.names cnt[16] $auto$alumacc.cc:485:replace_alu$473.X[16] +1 1 +.names cnt[17] $auto$alumacc.cc:485:replace_alu$473.X[17] +1 1 +.names cnt[18] $auto$alumacc.cc:485:replace_alu$473.X[18] +1 1 +.names cnt[19] $auto$alumacc.cc:485:replace_alu$473.X[19] +1 1 +.names cnt[20] $auto$alumacc.cc:485:replace_alu$473.X[20] +1 1 +.names cnt[21] $auto$alumacc.cc:485:replace_alu$473.X[21] +1 1 +.names cnt[22] $auto$alumacc.cc:485:replace_alu$473.X[22] +1 1 +.names cnt[23] $auto$alumacc.cc:485:replace_alu$473.X[23] +1 1 +.names $auto$alumacc.cc:485:replace_alu$473.X[0] $auto$alumacc.cc:485:replace_alu$473.Y[0] +1 1 +.names $false segDP +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif new file mode 100644 index 00000000000..15b3654b812 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif @@ -0,0 +1,19659 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model Murax +.inputs io_asyncReset io_mainClk io_jtag_tms io_jtag_tdi io_jtag_tck io_gpioA_read[0] io_gpioA_read[1] io_gpioA_read[2] io_gpioA_read[3] io_gpioA_read[4] io_gpioA_read[5] io_gpioA_read[6] io_gpioA_read[7] io_gpioA_read[8] io_gpioA_read[9] io_gpioA_read[10] io_gpioA_read[11] io_gpioA_read[12] io_gpioA_read[13] io_gpioA_read[14] io_gpioA_read[15] io_gpioA_read[16] io_gpioA_read[17] io_gpioA_read[18] io_gpioA_read[19] io_gpioA_read[20] io_gpioA_read[21] io_gpioA_read[22] io_gpioA_read[23] io_gpioA_read[24] io_gpioA_read[25] io_gpioA_read[26] io_gpioA_read[27] io_gpioA_read[28] io_gpioA_read[29] io_gpioA_read[30] io_gpioA_read[31] io_uart_rxd +.outputs io_jtag_tdo io_gpioA_write[0] io_gpioA_write[1] io_gpioA_write[2] io_gpioA_write[3] io_gpioA_write[4] io_gpioA_write[5] io_gpioA_write[6] io_gpioA_write[7] io_gpioA_write[8] io_gpioA_write[9] io_gpioA_write[10] io_gpioA_write[11] io_gpioA_write[12] io_gpioA_write[13] io_gpioA_write[14] io_gpioA_write[15] io_gpioA_write[16] io_gpioA_write[17] io_gpioA_write[18] io_gpioA_write[19] io_gpioA_write[20] io_gpioA_write[21] io_gpioA_write[22] io_gpioA_write[23] io_gpioA_write[24] io_gpioA_write[25] io_gpioA_write[26] io_gpioA_write[27] io_gpioA_write[28] io_gpioA_write[29] io_gpioA_write[30] io_gpioA_write[31] io_gpioA_writeEnable[0] io_gpioA_writeEnable[1] io_gpioA_writeEnable[2] io_gpioA_writeEnable[3] io_gpioA_writeEnable[4] io_gpioA_writeEnable[5] io_gpioA_writeEnable[6] io_gpioA_writeEnable[7] io_gpioA_writeEnable[8] io_gpioA_writeEnable[9] io_gpioA_writeEnable[10] io_gpioA_writeEnable[11] io_gpioA_writeEnable[12] io_gpioA_writeEnable[13] io_gpioA_writeEnable[14] io_gpioA_writeEnable[15] io_gpioA_writeEnable[16] io_gpioA_writeEnable[17] io_gpioA_writeEnable[18] io_gpioA_writeEnable[19] io_gpioA_writeEnable[20] io_gpioA_writeEnable[21] io_gpioA_writeEnable[22] io_gpioA_writeEnable[23] io_gpioA_writeEnable[24] io_gpioA_writeEnable[25] io_gpioA_writeEnable[26] io_gpioA_writeEnable[27] io_gpioA_writeEnable[28] io_gpioA_writeEnable[29] io_gpioA_writeEnable[30] io_gpioA_writeEnable[31] io_uart_txd +.names $false +.names $true +1 +.names $undef +.names $abc$18544$new_n2708 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.timerBBridge_ticksEnable[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14552 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2713 $abc$18544$new_n2709 $abc$18544$new_n2708 +11 1 +.names $abc$18544$new_n2712 apb3Router_1._zz_selIndex_1 $abc$18544$new_n2709 +11 1 +.names apb3Router_1.io_input_PADDR[17] io_apb_decoder.io_input_PSEL $abc$18544$new_n2711 apb3Router_1.io_input_PADDR[18] apb3Router_1.io_input_PADDR[19] apb3Router_1._zz_selIndex_1 +11100 1 +.names apb3Router_1.io_input_PADDR[12] apb3Router_1.io_input_PADDR[13] apb3Router_1.io_input_PADDR[14] apb3Router_1.io_input_PADDR[15] apb3Router_1.io_input_PADDR[16] $abc$18544$new_n2711 +00000 1 +.names apb3Router_1.io_input_PENABLE apb3Router_1.io_input_PWRITE $abc$18544$new_n2712 +11 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2713 +11100 1 +.names apb3Router_1.io_input_PADDR[1] apb3Router_1.io_input_PADDR[2] apb3Router_1.io_input_PADDR[3] apb3Router_1.io_input_PADDR[0] $abc$18544$new_n2714 +0000 1 +.names $abc$18544$new_n2716 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.timerABridge_ticksEnable[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14554 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2717 $abc$18544$new_n2709 $abc$18544$new_n2716 +11 1 +.names apb3Router_1.io_input_PADDR[6] $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2717 +11000 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[14] system_timer.system_timer_timerB_io_limit_driver[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14556 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2722 $abc$18544$new_n2720 $abc$18544$new_n2719 +11 1 +.names apb3Router_1._zz_selIndex_1 $abc$18544$new_n2712 $abc$18544$new_n2720 +11 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2722 +11100 1 +.names apb3Router_1.io_input_PADDR[2] apb3Router_1.io_input_PADDR[1] apb3Router_1.io_input_PADDR[3] apb3Router_1.io_input_PADDR[0] $abc$18544$new_n2723 +1000 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[13] system_timer.system_timer_timerB_io_limit_driver[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14558 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[12] system_timer.system_timer_timerB_io_limit_driver[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14560 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l347_3 system_timer.system_timer_timerB_io_limit_driver[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14562 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l379 system_timer.system_timer_timerB_io_limit_driver[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14564 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l347_2 system_timer.system_timer_timerB_io_limit_driver[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14566 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[8] system_timer.system_timer_timerB_io_limit_driver[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14568 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[7] system_timer.system_timer_timerB_io_limit_driver[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14570 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[6] system_timer.system_timer_timerB_io_limit_driver[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14572 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[5] system_timer.system_timer_timerB_io_limit_driver[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14574 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[4] system_timer.system_timer_timerB_io_limit_driver[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14576 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[3] system_timer.system_timer_timerB_io_limit_driver[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14578 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[2] system_timer.system_timer_timerB_io_limit_driver[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14580 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.system_timer_timerB_io_limit_driver[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14582 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.system_timer_timerB_io_limit_driver[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14584 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[14] system_timer.system_timer_timerA_io_limit_driver[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14586 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2740 $abc$18544$new_n2720 $abc$18544$new_n2739 +11 1 +.names apb3Router_1.io_input_PADDR[6] $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2740 +11000 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[13] system_timer.system_timer_timerA_io_limit_driver[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14588 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[12] system_timer.system_timer_timerA_io_limit_driver[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14590 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l347_3 system_timer.system_timer_timerA_io_limit_driver[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14592 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l379 system_timer.system_timer_timerA_io_limit_driver[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14594 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l347_2 system_timer.system_timer_timerA_io_limit_driver[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14596 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[8] system_timer.system_timer_timerA_io_limit_driver[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14598 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[7] system_timer.system_timer_timerA_io_limit_driver[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14600 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[6] system_timer.system_timer_timerA_io_limit_driver[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14602 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[5] system_timer.system_timer_timerA_io_limit_driver[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14604 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[4] system_timer.system_timer_timerA_io_limit_driver[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14606 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[3] system_timer.system_timer_timerA_io_limit_driver[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14608 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[2] system_timer.system_timer_timerA_io_limit_driver[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14610 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.system_timer_timerA_io_limit_driver[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14612 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.system_timer_timerA_io_limit_driver[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14614 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[14] system_timer._zz_io_limit[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14616 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2757 $abc$18544$new_n2720 $abc$18544$new_n2756 +11 1 +.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2757 +10000 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[13] system_timer._zz_io_limit[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14618 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[12] system_timer._zz_io_limit[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14620 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_3 system_timer._zz_io_limit[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14622 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l379 system_timer._zz_io_limit[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14624 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_2 system_timer._zz_io_limit[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14626 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[8] system_timer._zz_io_limit[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14628 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[7] system_timer._zz_io_limit[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14630 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[6] system_timer._zz_io_limit[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14632 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[5] system_timer._zz_io_limit[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14634 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[4] system_timer._zz_io_limit[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14636 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[3] system_timer._zz_io_limit[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14638 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[2] system_timer._zz_io_limit[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14640 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer._zz_io_limit[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14642 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347 system_timer._zz_io_limit[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14644 +001 1 +011 1 +110 1 +111 1 +.names system_timer.timerA.counter[14] system_timer.timerA.counter[13] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$14646 +011 1 +100 1 +101 1 +110 1 +.names system_timer.timerA.counter[9] system_timer.timerA.counter[10] system_timer.timerA.counter[11] system_timer.timerA.counter[12] $abc$18544$new_n2774 $abc$18544$new_n2773 +11111 1 +.names system_timer.timerA.counter[8] $abc$18544$new_n2775 $abc$18544$new_n2774 +11 1 +.names system_timer.timerA.counter[7] $abc$18544$new_n2776 $abc$18544$new_n2775 +11 1 +.names system_timer.timerA.counter[6] $abc$18544$new_n2777 $abc$18544$new_n2776 +11 1 +.names system_timer.timerA.counter[5] $abc$18544$new_n2778 $abc$18544$new_n2777 +11 1 +.names system_timer.timerA.counter[4] $abc$18544$new_n2779 $abc$18544$new_n2778 +11 1 +.names system_timer.timerA.counter[3] $abc$18544$new_n2780 $abc$18544$new_n2779 +11 1 +.names system_timer.timerA.counter[2] $abc$18544$new_n2781 $abc$18544$new_n2780 +11 1 +.names system_timer.timerA.counter[1] $abc$18544$new_n2782 $abc$18544$new_n2781 +11 1 +.names system_timer.timerA.counter[0] $abc$18544$new_n2783 $abc$18544$new_n2782 +11 1 +.names $abc$18544$new_n5029 $abc$18544$new_n2784 $abc$18544$new_n2783 +00 1 +.names system_timer.timerABridge_ticksEnable[0] $abc$18544$new_n5026 system_timer.timerABridge_ticksEnable[1] $abc$18544$new_n2784 +000 1 +001 1 +010 1 +.names $abc$18544$new_n2789 $abc$18544$new_n2787 $abc$18544$new_n2790 system_timer.prescaler_1.counter[14] system_timer._zz_io_limit[14] $abc$18544$new_n2786 +11100 1 +11111 1 +.names $abc$18544$new_n2788 system_timer.prescaler_1.counter[4] system_timer._zz_io_limit[4] system_timer.prescaler_1.counter[12] system_timer._zz_io_limit[12] $abc$18544$new_n2787 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_timer._zz_io_limit[3] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[6] system_timer._zz_io_limit[6] $abc$18544$new_n2788 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer._zz_io_limit[7] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[13] system_timer._zz_io_limit[13] $abc$18544$new_n2789 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer._zz_io_limit[0] system_timer.prescaler_1.counter[0] system_timer.prescaler_1.counter[10] system_timer._zz_io_limit[10] $abc$18544$new_n2790 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer._zz_io_limit[8] system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[9] system_timer._zz_io_limit[9] $abc$18544$new_n2792 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n2801 $abc$18544$new_n2800 $abc$18544$new_n2799 $abc$18544$new_n2797 $abc$18544$new_n2796 +1111 1 +.names system_timer.timerA.counter[6] system_timer.system_timer_timerA_io_limit_driver[6] system_timer.timerA.counter[10] system_timer.system_timer_timerA_io_limit_driver[10] $abc$18544$new_n2798 $abc$18544$new_n2797 +00000 1 +00110 1 +11000 1 +11110 1 +.names system_timer.timerA.counter[12] system_timer.system_timer_timerA_io_limit_driver[12] $abc$18544$new_n2798 +01 1 +10 1 +.names system_timer.timerA.counter[1] system_timer.system_timer_timerA_io_limit_driver[1] system_timer.timerA.counter[11] system_timer.system_timer_timerA_io_limit_driver[11] $abc$18544$new_n2799 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerA.counter[2] system_timer.system_timer_timerA_io_limit_driver[2] system_timer.timerA.counter[7] system_timer.system_timer_timerA_io_limit_driver[7] $abc$18544$new_n2800 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerA.counter[5] system_timer.system_timer_timerA_io_limit_driver[5] system_timer.timerA.counter[13] system_timer.system_timer_timerA_io_limit_driver[13] $abc$18544$new_n2801 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerA.counter[8] system_timer.system_timer_timerA_io_limit_driver[8] system_timer.timerA.counter[9] system_timer.system_timer_timerA_io_limit_driver[9] $abc$18544$new_n2803 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerA.counter[13] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$14648 +01 1 +10 1 +.names system_timer.timerA.counter[12] system_timer.timerA.counter[9] system_timer.timerA.counter[10] system_timer.timerA.counter[11] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14650 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.timerA.counter[11] system_timer.timerA.counter[9] system_timer.timerA.counter[10] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14652 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.timerA.counter[10] system_timer.timerA.counter[9] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14654 +011 1 +100 1 +101 1 +110 1 +.names system_timer.timerA.counter[9] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14656 +01 1 +10 1 +.names system_timer.timerA.counter[8] $abc$18544$new_n2775 $abc$18544$auto$rtlil.cc:2693:MuxGate$14658 +01 1 +10 1 +.names system_timer.timerA.counter[7] $abc$18544$new_n2776 $abc$18544$auto$rtlil.cc:2693:MuxGate$14660 +01 1 +10 1 +.names system_timer.timerA.counter[6] $abc$18544$new_n2777 $abc$18544$auto$rtlil.cc:2693:MuxGate$14662 +01 1 +10 1 +.names system_timer.timerA.counter[5] $abc$18544$new_n2778 $abc$18544$auto$rtlil.cc:2693:MuxGate$14664 +01 1 +10 1 +.names system_timer.timerA.counter[4] $abc$18544$new_n2779 $abc$18544$auto$rtlil.cc:2693:MuxGate$14666 +01 1 +10 1 +.names system_timer.timerA.counter[3] $abc$18544$new_n2780 $abc$18544$auto$rtlil.cc:2693:MuxGate$14668 +01 1 +10 1 +.names system_timer.timerA.counter[2] $abc$18544$new_n2781 $abc$18544$auto$rtlil.cc:2693:MuxGate$14670 +01 1 +10 1 +.names system_timer.timerA.counter[1] $abc$18544$new_n2782 $abc$18544$auto$rtlil.cc:2693:MuxGate$14672 +01 1 +10 1 +.names system_timer.timerA.counter[0] $abc$18544$new_n2783 $abc$18544$auto$rtlil.cc:2693:MuxGate$14674 +01 1 +10 1 +.names $abc$18544$new_n2821 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.interruptCtrl_1.io_masks[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14676 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2822 $abc$18544$new_n2709 $abc$18544$new_n2821 +11 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2822 +11000 1 +.names system_timer.timerB.counter[14] system_timer.timerB.counter[13] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$14678 +011 1 +100 1 +101 1 +110 1 +.names system_timer.timerB.counter[9] system_timer.timerB.counter[10] system_timer.timerB.counter[11] system_timer.timerB.counter[12] $abc$18544$new_n2825 $abc$18544$new_n2824 +11111 1 +.names system_timer.timerB.counter[8] $abc$18544$new_n2826 $abc$18544$new_n2825 +11 1 +.names system_timer.timerB.counter[7] $abc$18544$new_n2827 $abc$18544$new_n2826 +11 1 +.names system_timer.timerB.counter[6] $abc$18544$new_n2828 $abc$18544$new_n2827 +11 1 +.names system_timer.timerB.counter[5] $abc$18544$new_n2829 $abc$18544$new_n2828 +11 1 +.names system_timer.timerB.counter[4] $abc$18544$new_n2830 $abc$18544$new_n2829 +11 1 +.names system_timer.timerB.counter[3] $abc$18544$new_n2831 $abc$18544$new_n2830 +11 1 +.names system_timer.timerB.counter[2] $abc$18544$new_n2832 $abc$18544$new_n2831 +11 1 +.names system_timer.timerB.counter[1] $abc$18544$new_n2833 $abc$18544$new_n2832 +11 1 +.names system_timer.timerB.counter[0] $abc$18544$new_n2834 $abc$18544$new_n2833 +11 1 +.names $abc$18544$new_n5032 $abc$18544$new_n2835 $abc$18544$new_n2834 +00 1 +.names system_timer.timerBBridge_ticksEnable[0] $abc$18544$new_n5026 system_timer.timerBBridge_ticksEnable[1] $abc$18544$new_n2835 +000 1 +001 1 +010 1 +.names $abc$18544$new_n2842 $abc$18544$new_n2841 $abc$18544$new_n2840 $abc$18544$new_n2838 $abc$18544$new_n2837 +1111 1 +.names system_timer.timerB.counter[6] system_timer.system_timer_timerB_io_limit_driver[6] system_timer.timerB.counter[10] system_timer.system_timer_timerB_io_limit_driver[10] $abc$18544$new_n2839 $abc$18544$new_n2838 +00000 1 +00110 1 +11000 1 +11110 1 +.names system_timer.timerB.counter[12] system_timer.system_timer_timerB_io_limit_driver[12] $abc$18544$new_n2839 +01 1 +10 1 +.names system_timer.timerB.counter[1] system_timer.system_timer_timerB_io_limit_driver[1] system_timer.timerB.counter[11] system_timer.system_timer_timerB_io_limit_driver[11] $abc$18544$new_n2840 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerB.counter[2] system_timer.system_timer_timerB_io_limit_driver[2] system_timer.timerB.counter[7] system_timer.system_timer_timerB_io_limit_driver[7] $abc$18544$new_n2841 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerB.counter[5] system_timer.system_timer_timerB_io_limit_driver[5] system_timer.timerB.counter[13] system_timer.system_timer_timerB_io_limit_driver[13] $abc$18544$new_n2842 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerB.counter[8] system_timer.system_timer_timerB_io_limit_driver[8] system_timer.timerB.counter[9] system_timer.system_timer_timerB_io_limit_driver[9] $abc$18544$new_n2845 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerB.counter[13] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$14680 +01 1 +10 1 +.names system_timer.timerB.counter[12] system_timer.timerB.counter[9] system_timer.timerB.counter[10] system_timer.timerB.counter[11] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14682 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.timerB.counter[11] system_timer.timerB.counter[9] system_timer.timerB.counter[10] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14684 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.timerB.counter[10] system_timer.timerB.counter[9] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14686 +011 1 +100 1 +101 1 +110 1 +.names system_timer.timerB.counter[9] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14688 +01 1 +10 1 +.names system_timer.timerB.counter[8] $abc$18544$new_n2826 $abc$18544$auto$rtlil.cc:2693:MuxGate$14690 +01 1 +10 1 +.names system_timer.timerB.counter[7] $abc$18544$new_n2827 $abc$18544$auto$rtlil.cc:2693:MuxGate$14692 +01 1 +10 1 +.names system_timer.timerB.counter[6] $abc$18544$new_n2828 $abc$18544$auto$rtlil.cc:2693:MuxGate$14694 +01 1 +10 1 +.names system_timer.timerB.counter[5] $abc$18544$new_n2829 $abc$18544$auto$rtlil.cc:2693:MuxGate$14696 +01 1 +10 1 +.names system_timer.timerB.counter[4] $abc$18544$new_n2830 $abc$18544$auto$rtlil.cc:2693:MuxGate$14698 +01 1 +10 1 +.names system_timer.timerB.counter[3] $abc$18544$new_n2831 $abc$18544$auto$rtlil.cc:2693:MuxGate$14700 +01 1 +10 1 +.names system_timer.timerB.counter[2] $abc$18544$new_n2832 $abc$18544$auto$rtlil.cc:2693:MuxGate$14702 +01 1 +10 1 +.names system_timer.timerB.counter[1] $abc$18544$new_n2833 $abc$18544$auto$rtlil.cc:2693:MuxGate$14704 +01 1 +10 1 +.names system_timer.timerB.counter[0] $abc$18544$new_n2834 $abc$18544$auto$rtlil.cc:2693:MuxGate$14706 +01 1 +10 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[32] jtagBridge_1.jtag_readArea_full_shifter[33] jtagBridge_1.system_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14708 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] $abc$18544$new_n2863 jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n2862 +1110 1 +.names jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n2863 +1100 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n2864 +1110 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[31] jtagBridge_1.jtag_readArea_full_shifter[32] jtagBridge_1.system_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14710 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[30] jtagBridge_1.jtag_readArea_full_shifter[31] jtagBridge_1.system_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14712 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[29] jtagBridge_1.jtag_readArea_full_shifter[30] jtagBridge_1.system_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14714 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[28] jtagBridge_1.jtag_readArea_full_shifter[29] jtagBridge_1.system_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14716 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[27] jtagBridge_1.jtag_readArea_full_shifter[28] jtagBridge_1.system_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14718 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[26] jtagBridge_1.jtag_readArea_full_shifter[27] jtagBridge_1.system_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14720 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[25] jtagBridge_1.jtag_readArea_full_shifter[26] jtagBridge_1.system_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14722 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[24] jtagBridge_1.jtag_readArea_full_shifter[25] jtagBridge_1.system_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14724 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[23] jtagBridge_1.jtag_readArea_full_shifter[24] jtagBridge_1.system_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14726 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[22] jtagBridge_1.jtag_readArea_full_shifter[23] jtagBridge_1.system_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14728 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[21] jtagBridge_1.jtag_readArea_full_shifter[22] jtagBridge_1.system_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14730 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[20] jtagBridge_1.jtag_readArea_full_shifter[21] jtagBridge_1.system_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14732 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[19] jtagBridge_1.jtag_readArea_full_shifter[20] jtagBridge_1.system_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14734 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[18] jtagBridge_1.jtag_readArea_full_shifter[19] jtagBridge_1.system_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14736 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[17] jtagBridge_1.jtag_readArea_full_shifter[18] jtagBridge_1.system_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14738 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[16] jtagBridge_1.jtag_readArea_full_shifter[17] jtagBridge_1.system_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14740 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[15] jtagBridge_1.jtag_readArea_full_shifter[16] jtagBridge_1.system_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14742 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[14] jtagBridge_1.jtag_readArea_full_shifter[15] jtagBridge_1.system_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14744 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[13] jtagBridge_1.jtag_readArea_full_shifter[14] jtagBridge_1.system_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14746 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[12] jtagBridge_1.jtag_readArea_full_shifter[13] jtagBridge_1.system_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14748 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[11] jtagBridge_1.jtag_readArea_full_shifter[12] jtagBridge_1.system_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14750 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[10] jtagBridge_1.jtag_readArea_full_shifter[11] jtagBridge_1.system_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14752 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[9] jtagBridge_1.jtag_readArea_full_shifter[10] jtagBridge_1.system_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14754 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[8] jtagBridge_1.jtag_readArea_full_shifter[9] jtagBridge_1.system_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14756 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[7] jtagBridge_1.jtag_readArea_full_shifter[8] jtagBridge_1.system_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14758 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[6] jtagBridge_1.jtag_readArea_full_shifter[7] jtagBridge_1.system_rsp_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14760 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[5] jtagBridge_1.jtag_readArea_full_shifter[6] jtagBridge_1.system_rsp_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14762 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[4] jtagBridge_1.jtag_readArea_full_shifter[5] jtagBridge_1.system_rsp_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14764 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[3] jtagBridge_1.jtag_readArea_full_shifter[4] jtagBridge_1.system_rsp_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14766 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[2] jtagBridge_1.jtag_readArea_full_shifter[3] jtagBridge_1.system_rsp_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14768 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.jtag_readArea_full_shifter[1] jtagBridge_1.system_rsp_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$14770 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[5] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] $abc$18544$new_n2897 $abc$18544$auto$rtlil.cc:2693:MuxGate$14772 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] $abc$18544$new_n2898 $abc$18544$new_n2897 +11 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.rx.break_counter[1] $abc$18544$new_n2898 +111 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[6] system_uartCtrl.uartCtrl_1.rx.break_counter[0] $abc$18544$new_n2900 system_uartCtrl.uartCtrl_1.rx.break_counter[1] system_uartCtrl.uartCtrl_1.io_readBreak +1110 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.break_counter[5] $abc$18544$new_n2900 +0000 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.break_counter[3] $abc$18544$new_n2897 $abc$18544$auto$rtlil.cc:2693:MuxGate$14774 +0011 1 +1000 1 +1001 1 +1010 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[3] $abc$18544$new_n2897 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14776 +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] $abc$18544$new_n2898 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14778 +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[1] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$14780 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$14782 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[30] $abc$18544$new_n2907 jtagBridge_1.io_remote_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14784 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[30] $abc$18544$new_n2907 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 system_cpu._zz_lastStageRegFileWrite_payload_address[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2913 system_cpu._zz_lastStageRegFileWrite_payload_address[14] $abc$18544$new_n2908 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2910 system_cpu._zz_lastStageRegFileWrite_payload_address[14] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2909 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2911 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] $abc$18544$new_n2910 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[7] $abc$18544$new_n2911 +000 1 +010 1 +100 1 +101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ENABLE system_cpu.lastStageIsFiring $abc$18544$new_n2912 +11 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] $abc$18544$new_n2913 +000 1 +010 1 +100 1 +101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2914 +10 1 +.names system_cpu.decode_to_execute_DO_EBREAK system_cpu.execute_arbitration_isValid $abc$18544$new_n2915 +11 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[29] $abc$18544$new_n2917 jtagBridge_1.io_remote_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14786 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[29] $abc$18544$new_n2917 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[28] $abc$18544$new_n2919 jtagBridge_1.io_remote_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14788 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[28] $abc$18544$new_n2919 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[27] $abc$18544$new_n2921 jtagBridge_1.io_remote_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14790 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[27] $abc$18544$new_n2921 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[26] $abc$18544$new_n2923 jtagBridge_1.io_remote_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14792 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[26] $abc$18544$new_n2923 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[25] $abc$18544$new_n2925 jtagBridge_1.io_remote_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14794 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[25] $abc$18544$new_n2925 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[24] $abc$18544$new_n2927 jtagBridge_1.io_remote_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14796 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[24] $abc$18544$new_n2927 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[23] $abc$18544$new_n2929 jtagBridge_1.io_remote_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14798 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[23] $abc$18544$new_n2929 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[22] $abc$18544$new_n2931 jtagBridge_1.io_remote_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14800 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[22] $abc$18544$new_n2931 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[21] $abc$18544$new_n2933 jtagBridge_1.io_remote_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14802 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[21] $abc$18544$new_n2933 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[20] $abc$18544$new_n2935 jtagBridge_1.io_remote_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14804 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[20] $abc$18544$new_n2935 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[19] $abc$18544$new_n2937 jtagBridge_1.io_remote_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14806 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[19] $abc$18544$new_n2937 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[18] $abc$18544$new_n2939 jtagBridge_1.io_remote_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14808 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[18] $abc$18544$new_n2939 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[17] $abc$18544$new_n2941 jtagBridge_1.io_remote_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14810 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[17] $abc$18544$new_n2941 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[16] $abc$18544$new_n2943 jtagBridge_1.io_remote_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14812 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[16] $abc$18544$new_n2943 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[15] $abc$18544$new_n2945 jtagBridge_1.io_remote_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14814 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2946 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[15] $abc$18544$new_n2912 $abc$18544$new_n2945 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2913 system_cpu._zz_lastStageRegFileWrite_payload_address[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2946 +001 1 +010 1 +011 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[14] $abc$18544$new_n2948 jtagBridge_1.io_remote_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14816 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2949 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[14] $abc$18544$new_n2912 $abc$18544$new_n2948 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2949 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[13] $abc$18544$new_n2951 jtagBridge_1.io_remote_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14818 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2952 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[13] $abc$18544$new_n2912 $abc$18544$new_n2951 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2952 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[12] $abc$18544$new_n2954 jtagBridge_1.io_remote_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14820 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2955 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[12] $abc$18544$new_n2912 $abc$18544$new_n2954 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2955 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[11] $abc$18544$new_n2957 jtagBridge_1.io_remote_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14822 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2958 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[11] $abc$18544$new_n2912 $abc$18544$new_n2957 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2958 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[10] $abc$18544$new_n2960 jtagBridge_1.io_remote_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14824 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2961 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[10] $abc$18544$new_n2912 $abc$18544$new_n2960 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2961 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[9] $abc$18544$new_n2963 jtagBridge_1.io_remote_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14826 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2964 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[9] $abc$18544$new_n2912 $abc$18544$new_n2963 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2964 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[8] $abc$18544$new_n2966 jtagBridge_1.io_remote_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14828 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2967 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[8] $abc$18544$new_n2912 $abc$18544$new_n2966 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2967 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[7] $abc$18544$new_n2969 jtagBridge_1.io_remote_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14830 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2910 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[7] $abc$18544$new_n2969 +000 1 +010 1 +110 1 +111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[6] $abc$18544$new_n2971 jtagBridge_1.io_remote_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14832 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2972 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[6] $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] $abc$18544$new_n2971 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[6] $abc$18544$new_n2972 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[5] $abc$18544$new_n2974 jtagBridge_1.io_remote_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14834 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2975 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[5] $abc$18544$new_n2974 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2976 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] $abc$18544$new_n2975 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[5] $abc$18544$new_n2976 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[4] $abc$18544$new_n2978 system_cpu.DebugPlugin_busReadDataReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14836 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2979 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[4] $abc$18544$new_n2978 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2980 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] $abc$18544$new_n2979 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[4] $abc$18544$new_n2980 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[3] $abc$18544$new_n2982 system_cpu.DebugPlugin_busReadDataReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14838 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2983 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[3] $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] $abc$18544$new_n2982 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[3] $abc$18544$new_n2983 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[2] $abc$18544$new_n2985 system_cpu.DebugPlugin_busReadDataReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14840 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2986 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[2] $abc$18544$new_n2985 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2987 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] $abc$18544$new_n2986 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[2] $abc$18544$new_n2987 +000 1 +010 1 +100 1 +101 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] $abc$18544$new_n2989 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14842 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2989 +11 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2990 +1100 1 +.names system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$new_n2991 +1000 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2989 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14844 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2994 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14846 +001 1 +011 1 +110 1 +111 1 +.names system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2994 +1100 1 +.names $abc$18544$new_n2997 $abc$18544$new_n2998 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] $abc$18544$new_n2999 $abc$18544$auto$rtlil.cc:2693:MuxGate$14848 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2997 +11 1 +.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2998 +10 1 +.names system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2999 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] $abc$18544$new_n2998 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14850 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2998 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14852 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3003 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14854 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n3003 +1000 1 +.names $abc$18544$new_n3005 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3010 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14914 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$18544$new_n2991 $abc$18544$new_n3008 $abc$18544$new_n3009 $abc$18544$new_n3005 +100 1 +.names system_uartCtrl.uartCtrl_1.rx.sampler_tick $abc$18544$new_n3007 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3006 +1100 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3007 +000 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2997 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n3008 +10000 1 +10001 1 +10010 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n2999 $abc$18544$new_n3009 +11 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3010 +100 1 +.names $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2991 $abc$18544$new_n3009 $abc$18544$auto$rtlil.cc:2693:MuxGate$14916 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14918 +001 1 +011 1 +110 1 +111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid $abc$18544$new_n3014 system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3013 +100 1 +101 1 +111 1 +.names system_uartCtrl.bridge_misc_doBreak $abc$18544$new_n3926 $abc$18544$new_n3017 $abc$18544$new_n3014 +000 1 +001 1 +010 1 +.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] $abc$18544$new_n3016 +1100 1 +.names system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] $abc$18544$new_n3017 +100 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14920 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14922 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14924 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n5035 $abc$18544$new_n3014 $abc$18544$new_n3022 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire +000 1 +001 1 +010 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3022 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3029 $abc$18544$auto$rtlil.cc:2693:MuxGate$14926 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3030 $abc$18544$new_n3029 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3031 $abc$18544$new_n3030 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$new_n3031 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3030 $abc$18544$auto$rtlil.cc:2693:MuxGate$14928 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3031 $abc$18544$auto$rtlil.cc:2693:MuxGate$14930 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$auto$rtlil.cc:2693:MuxGate$14932 +01 1 +10 1 +.names $abc$18544$new_n2712 $abc$18544$new_n3042 apb3Router_1._zz_selIndex $abc$18544$new_n3036 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 +1110 1 +.names $abc$18544$new_n3037 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3036 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +.names $abc$18544$new_n3038 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n3037 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3038 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3041 $abc$18544$new_n3040 apb3Router_1._zz_selIndex +11 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[17] apb3Router_1.io_input_PADDR[18] apb3Router_1.io_input_PADDR[19] $abc$18544$new_n3040 +1000 1 +.names apb3Router_1.io_input_PADDR[16] apb3Router_1.io_input_PADDR[12] apb3Router_1.io_input_PADDR[13] apb3Router_1.io_input_PADDR[14] apb3Router_1.io_input_PADDR[15] $abc$18544$new_n3041 +10000 1 +.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3042 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3044 $abc$18544$auto$rtlil.cc:2693:MuxGate$14934 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3045 $abc$18544$new_n3044 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3046 $abc$18544$new_n3045 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 $abc$18544$new_n3046 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3045 $abc$18544$auto$rtlil.cc:2693:MuxGate$14936 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3046 $abc$18544$auto$rtlil.cc:2693:MuxGate$14938 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$14940 +01 1 +10 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14942 +001 1 +011 1 +110 1 +111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n3052 $abc$18544$new_n3051 +10 1 +.names system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3042 apb3Router_1._zz_selIndex system_apbBridge.pipelinedMemoryBusStage_rsp_valid $abc$18544$new_n3052 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names apb3Router_1.io_input_PENABLE apb3Router_1.io_input_PWRITE system_apbBridge.pipelinedMemoryBusStage_rsp_valid +10 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14944 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14946 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14948 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n5038 $abc$18544$new_n3052 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire +000 1 +001 1 +010 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3064 $abc$18544$auto$rtlil.cc:2693:MuxGate$14950 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3065 $abc$18544$new_n3064 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3066 $abc$18544$new_n3065 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$new_n3066 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3065 $abc$18544$auto$rtlil.cc:2693:MuxGate$14952 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3066 $abc$18544$auto$rtlil.cc:2693:MuxGate$14954 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$auto$rtlil.cc:2693:MuxGate$14956 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid $abc$18544$new_n3071 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 +10 1 +.names $abc$18544$new_n3072 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3071 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$18544$new_n3073 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n3072 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] $abc$18544$new_n3073 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3075 $abc$18544$auto$rtlil.cc:2693:MuxGate$14958 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3076 $abc$18544$new_n3075 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3077 $abc$18544$new_n3076 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 $abc$18544$new_n3077 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3076 $abc$18544$auto$rtlil.cc:2693:MuxGate$14960 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3077 $abc$18544$auto$rtlil.cc:2693:MuxGate$14962 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$14964 +01 1 +10 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[30] io_gpioA_write[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14966 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3040 $abc$18544$new_n2723 $abc$18544$new_n2711 $abc$18544$new_n2712 $abc$18544$new_n3082 +1111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[29] io_gpioA_write[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14968 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[28] io_gpioA_write[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14970 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[27] io_gpioA_write[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14972 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[26] io_gpioA_write[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14974 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[25] io_gpioA_write[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14976 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[24] io_gpioA_write[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14978 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[23] io_gpioA_write[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14980 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[22] io_gpioA_write[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14982 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[21] io_gpioA_write[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14984 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[20] io_gpioA_write[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14986 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[19] io_gpioA_write[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14988 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[18] io_gpioA_write[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14990 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[17] io_gpioA_write[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14992 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[16] io_gpioA_write[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14994 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[15] io_gpioA_write[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14996 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[14] io_gpioA_write[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14998 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[13] io_gpioA_write[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15000 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[12] io_gpioA_write[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15002 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_3 io_gpioA_write[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15004 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l379 io_gpioA_write[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15006 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_2 io_gpioA_write[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15008 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[8] io_gpioA_write[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15010 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[7] io_gpioA_write[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15012 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[6] io_gpioA_write[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15014 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[5] io_gpioA_write[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15016 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[4] io_gpioA_write[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15018 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[3] io_gpioA_write[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15020 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[2] io_gpioA_write[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15022 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_1 io_gpioA_write[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15024 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347 io_gpioA_write[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15026 +001 1 +011 1 +110 1 +111 1 +.names systemDebugger_1.dispatcher_counter[1] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last systemDebugger_1.dispatcher_counter[0] jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$15028 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names systemDebugger_1.dispatcher_counter[0] jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$15030 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[65] systemDebugger_1._zz_io_mem_cmd_payload_address[66] $abc$18544$auto$rtlil.cc:2693:MuxGate$15098 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.io_mem_cmd_payload_wr systemDebugger_1._zz_io_mem_cmd_payload_address[65] $abc$18544$auto$rtlil.cc:2693:MuxGate$15100 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[63] systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$15102 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[62] systemDebugger_1._zz_io_mem_cmd_payload_address[63] $abc$18544$auto$rtlil.cc:2693:MuxGate$15104 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[61] systemDebugger_1._zz_io_mem_cmd_payload_address[62] $abc$18544$auto$rtlil.cc:2693:MuxGate$15106 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[60] systemDebugger_1._zz_io_mem_cmd_payload_address[61] $abc$18544$auto$rtlil.cc:2693:MuxGate$15108 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[59] systemDebugger_1._zz_io_mem_cmd_payload_address[60] $abc$18544$auto$rtlil.cc:2693:MuxGate$15110 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l288_1 systemDebugger_1._zz_io_mem_cmd_payload_address[59] $abc$18544$auto$rtlil.cc:2693:MuxGate$15112 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l285_1 system_cpu.when_DebugPlugin_l288_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15114 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l284_1 system_cpu.when_DebugPlugin_l285_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15116 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[55] system_cpu.when_DebugPlugin_l284_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15118 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[54] systemDebugger_1._zz_io_mem_cmd_payload_address[55] $abc$18544$auto$rtlil.cc:2693:MuxGate$15120 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[53] systemDebugger_1._zz_io_mem_cmd_payload_address[54] $abc$18544$auto$rtlil.cc:2693:MuxGate$15122 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[52] systemDebugger_1._zz_io_mem_cmd_payload_address[53] $abc$18544$auto$rtlil.cc:2693:MuxGate$15124 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[51] systemDebugger_1._zz_io_mem_cmd_payload_address[52] $abc$18544$auto$rtlil.cc:2693:MuxGate$15126 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l288 systemDebugger_1._zz_io_mem_cmd_payload_address[51] $abc$18544$auto$rtlil.cc:2693:MuxGate$15128 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l285 system_cpu.when_DebugPlugin_l288 $abc$18544$auto$rtlil.cc:2693:MuxGate$15130 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l284 system_cpu.when_DebugPlugin_l285 $abc$18544$auto$rtlil.cc:2693:MuxGate$15132 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[47] system_cpu.when_DebugPlugin_l284 $abc$18544$auto$rtlil.cc:2693:MuxGate$15134 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[46] systemDebugger_1._zz_io_mem_cmd_payload_address[47] $abc$18544$auto$rtlil.cc:2693:MuxGate$15136 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[45] systemDebugger_1._zz_io_mem_cmd_payload_address[46] $abc$18544$auto$rtlil.cc:2693:MuxGate$15138 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[44] systemDebugger_1._zz_io_mem_cmd_payload_address[45] $abc$18544$auto$rtlil.cc:2693:MuxGate$15140 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[43] systemDebugger_1._zz_io_mem_cmd_payload_address[44] $abc$18544$auto$rtlil.cc:2693:MuxGate$15142 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[42] systemDebugger_1._zz_io_mem_cmd_payload_address[43] $abc$18544$auto$rtlil.cc:2693:MuxGate$15144 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[41] systemDebugger_1._zz_io_mem_cmd_payload_address[42] $abc$18544$auto$rtlil.cc:2693:MuxGate$15146 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[40] systemDebugger_1._zz_io_mem_cmd_payload_address[41] $abc$18544$auto$rtlil.cc:2693:MuxGate$15148 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[39] systemDebugger_1._zz_io_mem_cmd_payload_address[40] $abc$18544$auto$rtlil.cc:2693:MuxGate$15150 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[38] systemDebugger_1._zz_io_mem_cmd_payload_address[39] $abc$18544$auto$rtlil.cc:2693:MuxGate$15152 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[37] systemDebugger_1._zz_io_mem_cmd_payload_address[38] $abc$18544$auto$rtlil.cc:2693:MuxGate$15154 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[36] systemDebugger_1._zz_io_mem_cmd_payload_address[37] $abc$18544$auto$rtlil.cc:2693:MuxGate$15156 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[35] systemDebugger_1._zz_io_mem_cmd_payload_address[36] $abc$18544$auto$rtlil.cc:2693:MuxGate$15158 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[34] systemDebugger_1._zz_io_mem_cmd_payload_address[35] $abc$18544$auto$rtlil.cc:2693:MuxGate$15160 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[33] systemDebugger_1._zz_io_mem_cmd_payload_address[34] $abc$18544$auto$rtlil.cc:2693:MuxGate$15162 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[32] systemDebugger_1._zz_io_mem_cmd_payload_address[33] $abc$18544$auto$rtlil.cc:2693:MuxGate$15164 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[31] systemDebugger_1._zz_io_mem_cmd_payload_address[32] $abc$18544$auto$rtlil.cc:2693:MuxGate$15166 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[30] systemDebugger_1._zz_io_mem_cmd_payload_address[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$15168 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[29] systemDebugger_1._zz_io_mem_cmd_payload_address[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15170 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[28] systemDebugger_1._zz_io_mem_cmd_payload_address[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15172 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[27] systemDebugger_1._zz_io_mem_cmd_payload_address[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15174 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[26] systemDebugger_1._zz_io_mem_cmd_payload_address[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15176 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[25] systemDebugger_1._zz_io_mem_cmd_payload_address[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15178 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[24] systemDebugger_1._zz_io_mem_cmd_payload_address[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15180 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[23] systemDebugger_1._zz_io_mem_cmd_payload_address[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15182 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[22] systemDebugger_1._zz_io_mem_cmd_payload_address[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15184 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[21] systemDebugger_1._zz_io_mem_cmd_payload_address[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15186 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[20] systemDebugger_1._zz_io_mem_cmd_payload_address[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15188 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[19] systemDebugger_1._zz_io_mem_cmd_payload_address[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15190 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[18] systemDebugger_1._zz_io_mem_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15192 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[17] systemDebugger_1._zz_io_mem_cmd_payload_address[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15194 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[16] systemDebugger_1._zz_io_mem_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15196 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[15] systemDebugger_1._zz_io_mem_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15198 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[14] systemDebugger_1._zz_io_mem_cmd_payload_address[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15200 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[13] systemDebugger_1._zz_io_mem_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15202 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[12] systemDebugger_1._zz_io_mem_cmd_payload_address[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15204 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[11] systemDebugger_1._zz_io_mem_cmd_payload_address[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15206 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[10] systemDebugger_1._zz_io_mem_cmd_payload_address[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15208 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[9] systemDebugger_1._zz_io_mem_cmd_payload_address[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15210 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[8] systemDebugger_1._zz_io_mem_cmd_payload_address[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15212 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[7] systemDebugger_1._zz_io_mem_cmd_payload_address[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15214 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[6] systemDebugger_1._zz_io_mem_cmd_payload_address[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15216 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[5] systemDebugger_1._zz_io_mem_cmd_payload_address[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15218 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[4] systemDebugger_1._zz_io_mem_cmd_payload_address[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15220 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[3] systemDebugger_1._zz_io_mem_cmd_payload_address[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15222 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[2] systemDebugger_1._zz_io_mem_cmd_payload_address[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15224 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[6] systemDebugger_1.dispatcher_header[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15230 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[5] systemDebugger_1.dispatcher_header[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15232 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[4] systemDebugger_1.dispatcher_header[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15234 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[3] systemDebugger_1.dispatcher_header[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15236 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[2] systemDebugger_1.dispatcher_header[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15238 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[1] systemDebugger_1.dispatcher_header[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15240 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[0] systemDebugger_1.dispatcher_header[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15242 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[2] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15296 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n3187 +1000 1 +.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[1] jtagBridge_1._zz_jtag_tap_isBypass[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15298 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_tdoIr jtagBridge_1._zz_jtag_tap_isBypass[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15300 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[31] jtagBridge_1.jtag_idcodeArea_shifter[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15302 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2864 jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n3191 +11000 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[30] jtagBridge_1.jtag_idcodeArea_shifter[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15304 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[29] jtagBridge_1.jtag_idcodeArea_shifter[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15306 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[28] jtagBridge_1.jtag_idcodeArea_shifter[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15308 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[27] jtagBridge_1.jtag_idcodeArea_shifter[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15310 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[26] jtagBridge_1.jtag_idcodeArea_shifter[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15312 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[25] jtagBridge_1.jtag_idcodeArea_shifter[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15314 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[24] jtagBridge_1.jtag_idcodeArea_shifter[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15316 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[23] jtagBridge_1.jtag_idcodeArea_shifter[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15318 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[22] jtagBridge_1.jtag_idcodeArea_shifter[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15320 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[21] jtagBridge_1.jtag_idcodeArea_shifter[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15322 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[20] jtagBridge_1.jtag_idcodeArea_shifter[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15324 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[19] jtagBridge_1.jtag_idcodeArea_shifter[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15326 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[18] jtagBridge_1.jtag_idcodeArea_shifter[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15328 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[17] jtagBridge_1.jtag_idcodeArea_shifter[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15330 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[16] jtagBridge_1.jtag_idcodeArea_shifter[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15332 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[15] jtagBridge_1.jtag_idcodeArea_shifter[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15334 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[14] jtagBridge_1.jtag_idcodeArea_shifter[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15336 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[13] jtagBridge_1.jtag_idcodeArea_shifter[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15338 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[12] jtagBridge_1.jtag_idcodeArea_shifter[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15340 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[11] jtagBridge_1.jtag_idcodeArea_shifter[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15342 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[10] jtagBridge_1.jtag_idcodeArea_shifter[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15344 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[9] jtagBridge_1.jtag_idcodeArea_shifter[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15346 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[8] jtagBridge_1.jtag_idcodeArea_shifter[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15348 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[7] jtagBridge_1.jtag_idcodeArea_shifter[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15350 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[6] jtagBridge_1.jtag_idcodeArea_shifter[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15352 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[5] jtagBridge_1.jtag_idcodeArea_shifter[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15354 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[4] jtagBridge_1.jtag_idcodeArea_shifter[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15356 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[3] jtagBridge_1.jtag_idcodeArea_shifter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15358 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[2] jtagBridge_1.jtag_idcodeArea_shifter[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15360 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[1] jtagBridge_1.jtag_idcodeArea_ctrl_tdo $abc$18544$auto$rtlil.cc:2693:MuxGate$15362 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[30] jtagBridge_1.system_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15364 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[29] jtagBridge_1.system_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15366 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[28] jtagBridge_1.system_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15368 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[27] jtagBridge_1.system_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15370 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[26] jtagBridge_1.system_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15372 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[25] jtagBridge_1.system_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15374 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[24] jtagBridge_1.system_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15376 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[23] jtagBridge_1.system_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15378 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[22] jtagBridge_1.system_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15380 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[21] jtagBridge_1.system_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15382 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[20] jtagBridge_1.system_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15384 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[19] jtagBridge_1.system_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15386 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[18] jtagBridge_1.system_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15388 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[17] jtagBridge_1.system_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15390 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[16] jtagBridge_1.system_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15392 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[15] jtagBridge_1.system_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15394 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[14] jtagBridge_1.system_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15396 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[13] jtagBridge_1.system_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15398 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[12] jtagBridge_1.system_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15400 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[11] jtagBridge_1.system_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15402 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[10] jtagBridge_1.system_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15404 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[9] jtagBridge_1.system_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15406 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[8] jtagBridge_1.system_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15408 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[7] jtagBridge_1.system_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15410 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[6] jtagBridge_1.system_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15412 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[5] jtagBridge_1.system_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15414 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[4] system_cpu.DebugPlugin_busReadDataReg[4] system_cpu.DebugPlugin_stepIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15416 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[3] system_cpu.DebugPlugin_busReadDataReg[3] system_cpu.DebugPlugin_haltedByBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$15418 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[2] system_cpu.DebugPlugin_busReadDataReg[2] system_cpu.DebugPlugin_isPipBusy $abc$18544$auto$rtlil.cc:2693:MuxGate$15420 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[1] system_cpu.DebugPlugin_busReadDataReg[1] system_cpu.DebugPlugin_haltIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15422 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[0] system_cpu.DebugPlugin_busReadDataReg[0] system_cpu.DebugPlugin_resetIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15424 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3254 $abc$18544$new_n3260 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15620 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$18544$new_n3258 $abc$18544$new_n3255 $abc$18544$new_n3254 +11 1 +.names $abc$18544$new_n2915 $abc$18544$new_n3256 $abc$18544$new_n3255 +00 1 +.names system_cpu.execute_to_memory_MEMORY_ENABLE system_cpu.memory_arbitration_isValid system_cpu.execute_to_memory_MEMORY_STORE $abc$18544$new_n3257 system_mainBusArbiter.rspTarget $abc$18544$new_n3256 +11000 1 +11010 1 +11011 1 +.names system_ram._zz_io_bus_rsp_valid system_apbBridge.io_pipelinedMemoryBus_rsp_valid system_mainBusArbiter.rspPending system_mainBusDecoder_logic_rspNoHit $abc$18544$new_n3257 +0000 1 +0001 1 +0010 1 +.names system_cpu.execute_arbitration_isValid $abc$18544$new_n3259 system_cpu._zz_execute_SHIFT_CTRL[0] system_cpu._zz_execute_SHIFT_CTRL[1] $abc$18544$new_n3258 +1001 1 +1010 1 +1011 1 +.names system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] system_cpu.decode_to_execute_SRC2[2] system_cpu.decode_to_execute_SRC2[3] system_cpu.decode_to_execute_SRC2[4] $abc$18544$new_n3259 +00000 1 +.names $abc$18544$new_n3261 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[2] $abc$18544$new_n3260 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.execute_LightShifterPlugin_amplitudeReg[1] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] $abc$18544$new_n3261 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$18544$new_n3254 $abc$18544$new_n3261 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15622 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$18544$new_n3254 $abc$18544$new_n3264 system_cpu.execute_LightShifterPlugin_amplitudeReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15624 +001 1 +011 1 +100 1 +101 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.execute_LightShifterPlugin_amplitudeReg[1] $abc$18544$new_n3264 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names $abc$18544$new_n3254 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.decode_to_execute_SRC2[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15626 +0010 1 +0011 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[30] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15752 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 $abc$18544$new_n3318 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3267 +100 1 +110 1 +111 1 +.names $abc$18544$new_n3269 system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[2] system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3268 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3308 $abc$18544$new_n3270 $abc$18544$new_n3317 $abc$18544$new_n3269 +101 1 +110 1 +111 1 +.names $abc$18544$new_n5050 $abc$18544$new_n3307 $abc$18544$new_n5041 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$18544$new_n3270 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3273 system_cpu.execute_to_memory_INSTRUCTION[9] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.execute_to_memory_INSTRUCTION[7] $abc$18544$new_n3272 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$18544$new_n3274 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu.execute_to_memory_INSTRUCTION[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] system_cpu.execute_to_memory_INSTRUCTION[11] $abc$18544$new_n3273 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n3275 system_cpu.execute_to_memory_INSTRUCTION[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.execute_to_memory_INSTRUCTION[7] $abc$18544$new_n3274 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names system_cpu.execute_to_memory_REGFILE_WRITE_VALID system_cpu.memory_arbitration_isValid $abc$18544$new_n3275 +11 1 +.names system_cpu._zz_lastStageRegFileWrite_valid system_cpu.lastStageIsFiring system_cpu.HazardSimplePlugin_writeBackWrites_valid +11 1 +.names system_cpu.HazardSimplePlugin_writeBackBuffer_valid system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n3288 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$18544$new_n3297 $abc$18544$new_n3292 $abc$18544$new_n3294 $abc$18544$new_n3295 $abc$18544$new_n3291 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3293 system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n3292 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n3293 +00 1 +11 1 +.names $abc$18544$new_n3275 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.execute_to_memory_INSTRUCTION[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.execute_to_memory_INSTRUCTION[11] $abc$18544$new_n3294 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n3296 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.execute_to_memory_INSTRUCTION[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu.execute_to_memory_INSTRUCTION[10] $abc$18544$new_n3295 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.execute_to_memory_INSTRUCTION[9] $abc$18544$new_n3296 +00 1 +11 1 +.names system_cpu.HazardSimplePlugin_writeBackBuffer_valid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$18544$new_n3297 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_valid system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n3299 +100 1 +111 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] $abc$18544$new_n3300 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names system_cpu.decode_to_execute_REGFILE_WRITE_VALID system_cpu.execute_arbitration_isValid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n3304 +1100 1 +1111 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n3306 +10 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$new_n3307 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3315 $abc$18544$new_n3309 system_cpu.lastStageIsFiring system_cpu._zz_writeBack_ENV_CTRL $abc$18544$new_n3308 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3313 $abc$18544$new_n3255 $abc$18544$new_n3258 $abc$18544$new_n3310 $abc$18544$new_n3309 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3312 $abc$18544$new_n3311 $abc$18544$new_n3310 +11 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[1] system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[1] system_cpu.decode_to_execute_SRC2[2] $abc$18544$new_n3311 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[4] system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] system_cpu.decode_to_execute_SRC2[4] $abc$18544$new_n3312 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names system_cpu.execute_arbitration_isValid system_cpu.decode_to_execute_IS_CSR $abc$18544$new_n3314 system_cpu.decode_to_execute_MEMORY_ENABLE system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3313 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11100 1 +11101 1 +11110 1 +.names system_cpu.lastStageIsFiring system_cpu.memory_arbitration_isValid $abc$18544$new_n3314 +00 1 +.names $abc$18544$new_n3316 system_cpu._zz_memory_ENV_CTRL system_cpu.memory_arbitration_isValid system_cpu._zz_execute_ENV_CTRL system_cpu.execute_arbitration_isValid $abc$18544$new_n3315 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names system_cpu.CsrPlugin_interrupt_valid system_cpu.DebugPlugin_haltIt system_cpu.DebugPlugin_stepIt $abc$18544$new_n3317 $abc$18544$new_n3316 +1000 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_valid system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$new_n3317 +000 1 +001 1 +011 1 +.names $abc$18544$new_n3320 $abc$18544$new_n3319 $abc$18544$new_n3318 +10 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$18544$new_n3257 system_mainBusArbiter.rspTarget $abc$18544$new_n3319 +001 1 +010 1 +011 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] $abc$18544$new_n3320 +000 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15754 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15756 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[27] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15758 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[26] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15760 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[25] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15762 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[24] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15764 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[23] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15766 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[22] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15768 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[21] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15770 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[20] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15772 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15774 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[18] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15776 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[17] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15778 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15780 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[15] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15782 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15784 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[13] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15786 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[12] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15788 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[11] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15790 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[10] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15792 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[9] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15794 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[8] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15796 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[7] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15798 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[6] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15800 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[5] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15802 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[4] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15804 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[3] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15806 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[2] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15808 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[62] $abc$18544$new_n3350 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15928 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] $abc$18544$new_n3350 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[30] system_ram._zz_ram_port0[30] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] +001 1 +011 1 +110 1 +111 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[2] system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[1] $abc$18544$new_n3352 +000 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[61] $abc$18544$new_n3354 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15930 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] $abc$18544$new_n3354 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[29] system_ram._zz_ram_port0[29] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[60] $abc$18544$new_n3357 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15932 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] $abc$18544$new_n3357 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[28] system_ram._zz_ram_port0[28] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[59] $abc$18544$new_n3360 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15934 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] $abc$18544$new_n3360 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[27] system_ram._zz_ram_port0[27] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 system_cpu.when_DebugPlugin_l288_1 $abc$18544$new_n3363 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15936 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[26] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] $abc$18544$new_n3363 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[26] system_ram._zz_ram_port0[26] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[26] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 system_cpu.when_DebugPlugin_l285_1 $abc$18544$new_n3366 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15938 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] $abc$18544$new_n3366 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[25] system_ram._zz_ram_port0[25] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[46] $abc$18544$new_n3369 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15940 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[14] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] $abc$18544$new_n3369 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[14] system_ram._zz_ram_port0[14] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[14] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[45] $abc$18544$new_n3372 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15942 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[13] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] $abc$18544$new_n3372 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[13] system_ram._zz_ram_port0[13] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[13] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[44] $abc$18544$new_n3375 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$auto$rtlil.cc:2693:MuxGate$15944 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[12] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] $abc$18544$new_n3375 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[12] system_ram._zz_ram_port0[12] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[12] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[43] $abc$18544$new_n3378 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15946 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[11] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] $abc$18544$new_n3378 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[11] system_ram._zz_ram_port0[11] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[11] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[42] $abc$18544$new_n3381 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15948 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[10] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] $abc$18544$new_n3381 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[10] system_ram._zz_ram_port0[10] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[10] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[41] $abc$18544$new_n3384 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15950 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[9] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] $abc$18544$new_n3384 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[9] system_ram._zz_ram_port0[9] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[9] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[40] $abc$18544$new_n3387 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15952 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[8] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] $abc$18544$new_n3387 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[8] system_ram._zz_ram_port0[8] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[8] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[39] $abc$18544$new_n3390 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15954 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[7] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] $abc$18544$new_n3390 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[7] system_ram._zz_ram_port0[7] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[7] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[38] $abc$18544$new_n3393 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15956 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[6] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] $abc$18544$new_n3393 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[6] system_ram._zz_ram_port0[6] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[37] $abc$18544$new_n3396 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 $abc$18544$auto$rtlil.cc:2693:MuxGate$15958 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[5] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] $abc$18544$new_n3396 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[5] system_ram._zz_ram_port0[5] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[5] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[36] $abc$18544$new_n3399 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15960 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[4] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] $abc$18544$new_n3399 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[4] system_ram._zz_ram_port0[4] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[4] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[35] $abc$18544$new_n3402 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15962 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[3] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] $abc$18544$new_n3402 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[3] system_ram._zz_ram_port0[3] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[3] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[34] $abc$18544$new_n3405 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$auto$rtlil.cc:2693:MuxGate$15964 +00100 1 +00101 1 +00110 1 +00111 1 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$abc$18544$new_n3409 system_cpu._zz_execute_SrcPlugin_addSub_2[30] $abc$18544$new_n3408 +000 1 +001 1 +100 1 +110 1 +.names $abc$18544$new_n3462 system_cpu._zz_execute_SrcPlugin_addSub_2[29] $abc$18544$new_n3463 $abc$18544$new_n3464 $abc$18544$new_n3410 $abc$18544$new_n3409 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$18544$new_n3411 $abc$18544$new_n3461 system_cpu._zz_execute_SrcPlugin_addSub_2[27] $abc$18544$new_n3460 $abc$18544$new_n3459 $abc$18544$new_n3410 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$18544$new_n3412 $abc$18544$new_n3458 system_cpu._zz_execute_SrcPlugin_addSub_2[25] $abc$18544$new_n3457 $abc$18544$new_n3456 $abc$18544$new_n3411 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$18544$new_n3413 $abc$18544$new_n3455 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system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_cpu.IBusSimplePlugin_cmd_payload_pc[17] $abc$18544$new_n3694 $abc$18544$new_n3693 +11111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[13] $abc$18544$new_n3695 $abc$18544$new_n3694 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[12] $abc$18544$new_n3696 $abc$18544$new_n3695 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[11] $abc$18544$new_n3697 $abc$18544$new_n3696 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[10] $abc$18544$new_n3698 $abc$18544$new_n3697 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[9] $abc$18544$new_n3699 $abc$18544$new_n3698 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[8] $abc$18544$new_n3700 $abc$18544$new_n3699 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[7] $abc$18544$new_n3701 $abc$18544$new_n3700 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[6] $abc$18544$new_n3702 $abc$18544$new_n3701 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[5] $abc$18544$new_n3703 $abc$18544$new_n3702 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[4] $abc$18544$new_n3704 $abc$18544$new_n3703 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[3] $abc$18544$new_n3705 $abc$18544$new_n3704 +11 1 +.names system_cpu.IBusSimplePlugin_fetchPc_inc system_cpu.IBusSimplePlugin_cmd_payload_pc[2] $abc$18544$new_n3705 +11 1 +.names system_cpu.IBusSimplePlugin_fetchPc_booted $abc$18544$new_n3707 $abc$18544$new_n3706 +10 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3708 $abc$18544$new_n3707 +10 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$18544$new_n3709 $abc$18544$new_n3710 system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3708 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_pending_value[1] system_cpu.IBusSimplePlugin_pending_value[0] system_cpu.IBusSimplePlugin_pending_value[2] $abc$18544$new_n3709 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3720 $abc$18544$new_n3711 io_apb_decoder.io_input_PSEL $abc$18544$new_n3710 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3719 $abc$18544$new_n3718 $abc$18544$new_n3716 $abc$18544$new_n3717 $abc$18544$new_n3712 $abc$18544$new_n3711 +11100 1 +.names $abc$18544$new_n3713 system_mainBusArbiter.io_dBus_cmd_payload_address[31] $abc$18544$new_n3715 system_mainBusArbiter.io_dBus_cmd_payload_address[21] system_mainBusArbiter.io_dBus_cmd_payload_address[22] $abc$18544$new_n3712 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[31] $abc$18544$new_n3714 system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[21] $abc$18544$new_n3713 +1100 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[22] system_cpu.IBusSimplePlugin_cmd_payload_pc[23] system_cpu.IBusSimplePlugin_cmd_payload_pc[26] system_cpu.IBusSimplePlugin_cmd_payload_pc[27] $abc$18544$new_n3714 +0000 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_address[23] system_mainBusArbiter.io_dBus_cmd_payload_address[26] system_mainBusArbiter.io_dBus_cmd_payload_address[27] $abc$18544$new_n3715 +1000 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[24] system_cpu.IBusSimplePlugin_cmd_payload_pc[25] system_mainBusArbiter.io_dBus_cmd_payload_address[24] system_mainBusArbiter.io_dBus_cmd_payload_address[25] $abc$18544$new_n3716 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_mainBusArbiter.io_dBus_cmd_payload_address[29] $abc$18544$new_n3717 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[20] system_mainBusArbiter.io_dBus_cmd_payload_address[20] $abc$18544$new_n3718 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[30] system_mainBusArbiter.io_dBus_cmd_payload_address[28] system_mainBusArbiter.io_dBus_cmd_payload_address[30] $abc$18544$new_n3719 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11111 1 +.names system_mainBusArbiter.rspPending $abc$18544$new_n3257 $abc$18544$new_n3720 +11 1 +.names $abc$18544$new_n3722 system_cpu.memory_arbitration_isValid system_cpu.execute_to_memory_BRANCH_DO $abc$18544$new_n3721 +100 1 +101 1 +110 1 +.names $abc$18544$new_n3723 system_cpu.lastStageIsFiring system_cpu._zz_writeBack_ENV_CTRL $abc$18544$new_n3722 +000 1 +001 1 +010 1 +.names system_cpu.CsrPlugin_interrupt_valid system_cpu.CsrPlugin_pipelineLiberator_done system_cpu.DebugPlugin_haltIt system_cpu.DebugPlugin_stepIt $abc$18544$new_n3723 +1100 1 +.names $abc$18544$new_n3721 system_cpu.BranchPlugin_jumpInterface_payload[30] $abc$18544$new_n3722 system_cpu.CsrPlugin_mepc[30] $abc$18544$new_n3725 $abc$18544$new_n3724 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names system_cpu._zz_writeBack_ENV_CTRL system_cpu.lastStageIsFiring system_cpu._zz_lastStageRegFileWrite_payload_address[28] system_cpu._zz_lastStageRegFileWrite_payload_address[29] $abc$18544$new_n3725 +1111 1 +.names $abc$18544$new_n3706 $abc$18544$new_n3721 system_cpu.IBusSimplePlugin_cmd_payload_pc[29] $abc$18544$new_n3727 $abc$18544$new_n3728 $abc$18544$auto$rtlil.cc:2693:MuxGate$16036 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_cpu.IBusSimplePlugin_cmd_payload_pc[28] $abc$18544$new_n3689 $abc$18544$new_n3727 +011 1 +100 1 +101 1 +110 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[29] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[29] $abc$18544$new_n3728 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[28] $abc$18544$new_n3689 $abc$18544$new_n3730 $abc$18544$auto$rtlil.cc:2693:MuxGate$16038 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[28] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[28] $abc$18544$new_n3730 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[27] $abc$18544$new_n3690 $abc$18544$new_n3732 $abc$18544$auto$rtlil.cc:2693:MuxGate$16040 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[27] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[27] $abc$18544$new_n3732 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[26] $abc$18544$new_n3734 $abc$18544$new_n3737 $abc$18544$auto$rtlil.cc:2693:MuxGate$16042 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[25] $abc$18544$new_n3735 $abc$18544$new_n3734 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[24] $abc$18544$new_n3736 $abc$18544$new_n3735 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[23] $abc$18544$new_n3691 $abc$18544$new_n3736 +11 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[26] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[26] $abc$18544$new_n3737 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[25] $abc$18544$new_n3735 $abc$18544$new_n3739 $abc$18544$auto$rtlil.cc:2693:MuxGate$16044 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[25] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[25] $abc$18544$new_n3739 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[24] $abc$18544$new_n3736 $abc$18544$new_n3741 $abc$18544$auto$rtlil.cc:2693:MuxGate$16046 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[24] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[24] $abc$18544$new_n3741 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[23] $abc$18544$new_n3691 $abc$18544$new_n3743 $abc$18544$auto$rtlil.cc:2693:MuxGate$16048 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[23] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[23] $abc$18544$new_n3743 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[22] $abc$18544$new_n3745 $abc$18544$new_n3748 $abc$18544$auto$rtlil.cc:2693:MuxGate$16050 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[21] $abc$18544$new_n3746 $abc$18544$new_n3745 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[20] $abc$18544$new_n3747 $abc$18544$new_n3746 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[19] $abc$18544$new_n3692 $abc$18544$new_n3747 +11 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[22] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[22] $abc$18544$new_n3748 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[21] $abc$18544$new_n3746 $abc$18544$new_n3750 $abc$18544$auto$rtlil.cc:2693:MuxGate$16052 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[21] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[21] $abc$18544$new_n3750 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[20] $abc$18544$new_n3747 $abc$18544$new_n3752 $abc$18544$auto$rtlil.cc:2693:MuxGate$16054 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[20] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[20] $abc$18544$new_n3752 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[19] $abc$18544$new_n3692 $abc$18544$new_n3754 $abc$18544$auto$rtlil.cc:2693:MuxGate$16056 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[19] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[19] $abc$18544$new_n3754 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[18] $abc$18544$new_n3693 $abc$18544$new_n3756 $abc$18544$auto$rtlil.cc:2693:MuxGate$16058 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[18] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[18] $abc$18544$new_n3756 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[17] $abc$18544$new_n3758 $abc$18544$new_n3761 $abc$18544$auto$rtlil.cc:2693:MuxGate$16060 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[16] $abc$18544$new_n3759 $abc$18544$new_n3758 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[15] $abc$18544$new_n3760 $abc$18544$new_n3759 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[14] $abc$18544$new_n3694 $abc$18544$new_n3760 +11 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[17] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[17] $abc$18544$new_n3761 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[16] $abc$18544$new_n3759 $abc$18544$new_n3763 $abc$18544$auto$rtlil.cc:2693:MuxGate$16062 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[16] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[16] $abc$18544$new_n3763 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[15] $abc$18544$new_n3760 $abc$18544$new_n3765 $abc$18544$auto$rtlil.cc:2693:MuxGate$16064 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[15] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[15] $abc$18544$new_n3765 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[14] $abc$18544$new_n3694 $abc$18544$new_n3767 $abc$18544$auto$rtlil.cc:2693:MuxGate$16066 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[14] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[14] $abc$18544$new_n3767 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[13] $abc$18544$new_n3695 $abc$18544$new_n3769 $abc$18544$auto$rtlil.cc:2693:MuxGate$16068 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[13] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[13] $abc$18544$new_n3769 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[12] $abc$18544$new_n3696 $abc$18544$new_n3771 $abc$18544$auto$rtlil.cc:2693:MuxGate$16070 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[12] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[12] $abc$18544$new_n3771 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[11] $abc$18544$new_n3697 $abc$18544$new_n3773 $abc$18544$auto$rtlil.cc:2693:MuxGate$16072 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[11] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[11] $abc$18544$new_n3773 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[10] $abc$18544$new_n3698 $abc$18544$new_n3775 $abc$18544$auto$rtlil.cc:2693:MuxGate$16074 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[10] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[10] $abc$18544$new_n3775 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[9] $abc$18544$new_n3699 $abc$18544$new_n3777 $abc$18544$auto$rtlil.cc:2693:MuxGate$16076 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[9] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[9] $abc$18544$new_n3777 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[8] $abc$18544$new_n3700 $abc$18544$new_n3779 $abc$18544$auto$rtlil.cc:2693:MuxGate$16078 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[8] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[8] $abc$18544$new_n3779 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[7] $abc$18544$new_n3701 $abc$18544$new_n3781 $abc$18544$auto$rtlil.cc:2693:MuxGate$16080 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[7] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[7] $abc$18544$new_n3781 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[6] $abc$18544$new_n3702 $abc$18544$new_n3783 $abc$18544$auto$rtlil.cc:2693:MuxGate$16082 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[6] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[6] $abc$18544$new_n3783 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[5] $abc$18544$new_n3703 $abc$18544$new_n3785 $abc$18544$auto$rtlil.cc:2693:MuxGate$16084 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$18544$new_n3722 system_cpu.BranchPlugin_jumpInterface_payload[5] $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[5] $abc$18544$new_n3785 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[4] $abc$18544$new_n3704 $abc$18544$new_n3787 $abc$18544$auto$rtlil.cc:2693:MuxGate$16086 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[4] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[4] $abc$18544$new_n3787 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[3] $abc$18544$new_n3705 $abc$18544$new_n3789 $abc$18544$auto$rtlil.cc:2693:MuxGate$16088 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[3] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[3] $abc$18544$new_n3789 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[2] system_cpu.IBusSimplePlugin_fetchPc_inc $abc$18544$new_n3791 $abc$18544$auto$rtlil.cc:2693:MuxGate$16090 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[2] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[2] $abc$18544$new_n3791 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] system_cpu.CsrPlugin_mepc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16092 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] system_cpu.CsrPlugin_mepc[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16094 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] system_cpu.CsrPlugin_mepc[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16096 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] system_cpu.CsrPlugin_mepc[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16098 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] system_cpu.CsrPlugin_mepc[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16100 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] system_cpu.CsrPlugin_mepc[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16102 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] system_cpu.CsrPlugin_mepc[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16104 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] system_cpu.CsrPlugin_mepc[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16106 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] system_cpu.CsrPlugin_mepc[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16108 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] system_cpu.CsrPlugin_mepc[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16110 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] system_cpu.CsrPlugin_mepc[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16112 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] system_cpu.CsrPlugin_mepc[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16114 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] system_cpu.CsrPlugin_mepc[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16116 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] system_cpu.CsrPlugin_mepc[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16118 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] system_cpu.CsrPlugin_mepc[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16120 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] system_cpu.CsrPlugin_mepc[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16122 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu.CsrPlugin_mepc[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16124 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu.CsrPlugin_mepc[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16126 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu.CsrPlugin_mepc[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16128 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu.CsrPlugin_mepc[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16130 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.CsrPlugin_mepc[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16132 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] system_cpu.CsrPlugin_mepc[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16134 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] system_cpu.CsrPlugin_mepc[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16136 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.CsrPlugin_mepc[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16138 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.CsrPlugin_mepc[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16140 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.CsrPlugin_mepc[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16142 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] system_cpu.CsrPlugin_mepc[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16144 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu.CsrPlugin_mepc[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16146 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu.CsrPlugin_mepc[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16148 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.lastStageIsFiring $abc$18544$new_n2915 $abc$18544$new_n3822 system_cpu.DebugPlugin_busReadDataReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16152 +0001 1 +0011 1 +1000 1 +1001 1 +.names $abc$18544$new_n2912 $abc$18544$new_n3823 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[0] $abc$18544$new_n3822 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n3824 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] $abc$18544$new_n3823 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[0] $abc$18544$new_n3824 +000 1 +010 1 +100 1 +101 1 +.names jtagBridge_1.jtag_tap_instructionShift[3] $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_instructionShift[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16156 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$18544$new_n3827 $abc$18544$new_n2864 $abc$18544$new_n3826 +00 1 +.names jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] $abc$18544$new_n3827 +1000 1 +.names jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[3] $abc$18544$new_n3828 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names jtagBridge_1.jtag_tap_instructionShift[2] $abc$18544$new_n3826 jtagBridge_1.jtag_tap_instructionShift[1] $abc$18544$new_n3828 $abc$18544$auto$rtlil.cc:2693:MuxGate$16160 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names jtagBridge_1.jtag_tap_instructionShift[1] $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_tdoIr $abc$18544$auto$rtlil.cc:2693:MuxGate$16164 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$new_n3832 $abc$18544$auto$rtlil.cc:2693:MuxGate$16166 +0100 1 +0101 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3269 $abc$18544$new_n3833 $abc$18544$new_n3832 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3837 $abc$18544$new_n3834 $abc$18544$new_n3833 +111 1 +.names systemDebugger_1.dispatcher_dataLoaded $abc$18544$new_n3835 systemDebugger_1.dispatcher_header[0] systemDebugger_1.dispatcher_header[1] $abc$18544$new_n3834 +1100 1 +.names $abc$18544$new_n3836 systemDebugger_1.dispatcher_header[4] systemDebugger_1.dispatcher_header[5] systemDebugger_1.dispatcher_header[7] systemDebugger_1.dispatcher_header[6] $abc$18544$new_n3835 +10000 1 +.names systemDebugger_1.dispatcher_header[2] systemDebugger_1.dispatcher_header[3] $abc$18544$new_n3836 +00 1 +.names systemDebugger_1._zz_io_mem_cmd_payload_address[2] $abc$18544$new_n3838 $abc$18544$new_n3837 +11 1 +.names systemDebugger_1._zz_io_mem_cmd_payload_address[3] systemDebugger_1._zz_io_mem_cmd_payload_address[4] systemDebugger_1._zz_io_mem_cmd_payload_address[5] systemDebugger_1._zz_io_mem_cmd_payload_address[6] systemDebugger_1._zz_io_mem_cmd_payload_address[7] $abc$18544$new_n3838 +00000 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3832 system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16168 +010 1 +100 1 +101 1 +111 1 +.names resetCtrl_systemClkResetCounter[5] $abc$18544$new_n3841 resetCtrl_mainClkResetUnbuffered +00 1 +01 1 +10 1 +.names resetCtrl_systemClkResetCounter[4] $abc$18544$new_n3842 $abc$18544$new_n3841 +11 1 +.names resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] resetCtrl_systemClkResetCounter[2] resetCtrl_systemClkResetCounter[3] $abc$18544$new_n3842 +1111 1 +.names $abc$18544$new_n3842 resetCtrl_systemClkResetCounter[4] resetCtrl_systemClkResetCounter[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16228 +010 1 +011 1 +100 1 +101 1 +111 1 +.names resetCtrl_mainClkResetUnbuffered resetCtrl_systemClkResetCounter[3] resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] resetCtrl_systemClkResetCounter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16230 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names resetCtrl_mainClkResetUnbuffered resetCtrl_systemClkResetCounter[2] resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16232 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names resetCtrl_mainClkResetUnbuffered resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16234 +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +.names resetCtrl_systemClkResetCounter[0] resetCtrl_mainClkResetUnbuffered $abc$18544$auto$rtlil.cc:2693:MuxGate$16236 +00 1 +01 1 +10 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16238 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$18544$new_n3320 $abc$18544$new_n3850 $abc$18544$new_n3849 +111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3318 $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3850 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3852 $abc$18544$new_n3851 +10 1 +.names $abc$18544$new_n3314 $abc$18544$new_n2915 $abc$18544$new_n3852 +11 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16240 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16242 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16244 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16246 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16248 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[24] system_ram._zz_ram_port0[24] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16250 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[23] system_ram._zz_ram_port0[23] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16252 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[22] system_ram._zz_ram_port0[22] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16254 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[21] system_ram._zz_ram_port0[21] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16256 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[20] system_ram._zz_ram_port0[20] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16258 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[19] system_ram._zz_ram_port0[19] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16260 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[18] system_ram._zz_ram_port0[18] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16262 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[17] system_ram._zz_ram_port0[17] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16264 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[16] system_ram._zz_ram_port0[16] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16266 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[15] system_ram._zz_ram_port0[15] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[15] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16268 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16270 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16272 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16274 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16276 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16278 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16280 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16282 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16284 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16286 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16288 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16290 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16292 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16294 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[30] io_gpioA_writeEnable[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16324 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3893 $abc$18544$new_n3040 $abc$18544$new_n2711 $abc$18544$new_n2712 $abc$18544$new_n3892 +1111 1 +.names apb3Router_1.io_input_PADDR[3] apb3Router_1.io_input_PADDR[1] apb3Router_1.io_input_PADDR[2] apb3Router_1.io_input_PADDR[0] $abc$18544$new_n3893 +1000 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[29] io_gpioA_writeEnable[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16326 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[28] io_gpioA_writeEnable[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16328 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[27] io_gpioA_writeEnable[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16330 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[26] io_gpioA_writeEnable[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16332 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[25] io_gpioA_writeEnable[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16334 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[24] io_gpioA_writeEnable[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16336 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[23] io_gpioA_writeEnable[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16338 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[22] io_gpioA_writeEnable[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16340 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[21] io_gpioA_writeEnable[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16342 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[20] io_gpioA_writeEnable[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16344 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[19] io_gpioA_writeEnable[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16346 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[18] io_gpioA_writeEnable[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16348 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[17] io_gpioA_writeEnable[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16350 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[16] io_gpioA_writeEnable[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16352 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[15] io_gpioA_writeEnable[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16354 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[14] io_gpioA_writeEnable[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16356 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[13] io_gpioA_writeEnable[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16358 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[12] io_gpioA_writeEnable[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16360 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l347_3 io_gpioA_writeEnable[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16362 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l379 io_gpioA_writeEnable[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16364 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l347_2 io_gpioA_writeEnable[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16366 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[8] io_gpioA_writeEnable[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16368 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[7] io_gpioA_writeEnable[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16370 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[6] io_gpioA_writeEnable[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16372 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[5] io_gpioA_writeEnable[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16374 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[4] io_gpioA_writeEnable[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16376 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[3] io_gpioA_writeEnable[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16378 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[2] io_gpioA_writeEnable[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16380 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l347_1 io_gpioA_writeEnable[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16382 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l347 io_gpioA_writeEnable[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16384 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3926 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$new_n3928 $abc$18544$auto$rtlil.cc:2693:MuxGate$16512 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n3016 $abc$18544$new_n3927 $abc$18544$new_n3926 +11 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$new_n3017 $abc$18544$new_n3927 +00000 1 +00010 1 +00100 1 +01000 1 +01100 1 +10000 1 +10100 1 +11000 1 +11100 1 +11101 1 +.names system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$new_n3928 +100 1 +.names $abc$18544$new_n3926 $abc$18544$new_n3022 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16514 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3723 system_cpu.CsrPlugin_interrupt_code[2] system_cpu.CsrPlugin_mcause_exceptionCode[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16516 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3720 $abc$18544$new_n3932 $abc$18544$new_n3934 $abc$18544$auto$rtlil.cc:2693:MuxGate$16518 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3933 $abc$18544$new_n3711 io_apb_decoder.io_input_PSEL $abc$18544$new_n3932 +100 1 +101 1 +110 1 +.names $abc$18544$new_n3720 system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$18544$new_n3709 $abc$18544$new_n3933 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names system_mainBusArbiter.io_dBus_cmd_payload_wr system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3934 +11 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3710 $abc$18544$new_n3936 $abc$18544$auto$rtlil.cc:2693:MuxGate$16520 +001 1 +011 1 +100 1 +101 1 +.names system_cpu.decode_to_execute_MEMORY_ENABLE system_cpu.execute_arbitration_isValid $abc$18544$new_n3255 $abc$18544$new_n3851 $abc$18544$new_n3936 +1111 1 +.names $abc$18544$new_n3711 $abc$18544$new_n3933 system_mainBusDecoder_logic_rspSourceId io_apb_decoder.io_input_PSEL $abc$18544$auto$rtlil.cc:2693:MuxGate$16522 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$18544$new_n3926 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16532 +010 1 +011 1 +101 1 +.names $abc$18544$auto$rtlil.cc:2582:Mux$3924 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3005 $abc$18544$auto$rtlil.cc:2693:MuxGate$16534 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3005 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3941 $abc$18544$auto$rtlil.cc:2582:Mux$3924 +1100 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_parity system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3941 +11010 1 +11100 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[6] $abc$18544$new_n3943 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$16536 +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.break_counter[5] $abc$18544$new_n2897 $abc$18544$new_n3943 +1111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16538 +010 1 +011 1 +101 1 +111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16540 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n2997 $abc$18544$new_n2989 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] $abc$18544$new_n2999 $abc$18544$auto$rtlil.cc:2693:MuxGate$16542 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16544 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n5038 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n3052 $abc$18544$auto$rtlil.cc:2693:MuxGate$16546 +000 1 +001 1 +010 1 +011 1 +111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3064 $abc$18544$auto$rtlil.cc:2693:MuxGate$16548 +011 1 +100 1 +101 1 +110 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3075 $abc$18544$auto$rtlil.cc:2693:MuxGate$16550 +011 1 +100 1 +101 1 +110 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16552 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n5035 $abc$18544$new_n3014 $abc$18544$new_n3022 $abc$18544$auto$rtlil.cc:2693:MuxGate$16554 +000 1 +001 1 +010 1 +011 1 +111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3029 $abc$18544$auto$rtlil.cc:2693:MuxGate$16556 +011 1 +100 1 +101 1 +110 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3044 $abc$18544$auto$rtlil.cc:2693:MuxGate$16558 +011 1 +100 1 +101 1 +110 1 +.names system_uartCtrl.bridge_misc_readOverflowError system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid $abc$18544$new_n3071 $abc$18544$new_n3957 system_uartCtrl.when_BusSlaveFactory_l347_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16560 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2712 $abc$18544$new_n3958 apb3Router_1._zz_selIndex $abc$18544$new_n3957 +111 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2714 $abc$18544$new_n3958 +11 1 +.names system_uartCtrl.bridge_misc_readError $abc$18544$new_n3957 $abc$18544$new_n2991 $abc$18544$new_n3960 system_uartCtrl.when_BusSlaveFactory_l347 $abc$18544$auto$rtlil.cc:2693:MuxGate$16562 +00100 1 +00101 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$18544$new_n3941 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$new_n3960 +000 1 +001 1 +011 1 +.names $abc$18544$new_n3962 system_uartCtrl.when_BusSlaveFactory_l347_1 system_uartCtrl.bridge_interruptCtrl_readIntEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16564 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2712 $abc$18544$new_n3963 apb3Router_1._zz_selIndex $abc$18544$new_n3962 +111 1 +.names $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3963 +10 1 +.names $abc$18544$new_n3962 system_uartCtrl.when_BusSlaveFactory_l347 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16566 +001 1 +011 1 +110 1 +111 1 +.names system_timer.timerB.io_clear $abc$18544$new_n3968 system_timer.timerB.inhibitFull $abc$18544$new_n2835 $abc$18544$auto$rtlil.cc:2693:MuxGate$16568 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n2709 system_timer.timerBBridge_clearsEnable $abc$18544$new_n3967 $abc$18544$new_n2722 $abc$18544$new_n3969 system_timer.timerB.io_clear +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3968 system_timer.timerB.inhibitFull $abc$18544$new_n3967 +10 1 +.names $abc$18544$new_n5032 $abc$18544$new_n2835 $abc$18544$new_n3968 +10 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3893 apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n3969 +11100 1 +.names system_timer.timerA.io_clear $abc$18544$new_n3973 system_timer.timerA.inhibitFull $abc$18544$new_n2784 $abc$18544$auto$rtlil.cc:2693:MuxGate$16570 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names system_timer.timerABridge_clearsEnable $abc$18544$new_n3972 $abc$18544$new_n2709 $abc$18544$new_n3974 system_timer.timerA.io_clear +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3973 system_timer.timerA.inhibitFull $abc$18544$new_n3972 +10 1 +.names $abc$18544$new_n5029 $abc$18544$new_n2784 $abc$18544$new_n3973 +10 1 +.names $abc$18544$new_n3975 $abc$18544$new_n2723 $abc$18544$new_n3893 $abc$18544$new_n3974 +101 1 +110 1 +111 1 +.names apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n3975 +1000 1 +.names $abc$18544$new_n2821 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16572 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2708 apb3Router_1.io_input_PWDATA[16] system_timer.timerBBridge_clearsEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16574 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2708 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.timerBBridge_ticksEnable[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16576 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2716 apb3Router_1.io_input_PWDATA[16] system_timer.timerABridge_clearsEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16578 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2716 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.timerABridge_ticksEnable[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16580 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[15] system_timer.system_timer_timerB_io_limit_driver[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16582 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[15] system_timer.system_timer_timerA_io_limit_driver[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16584 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[15] system_timer._zz_io_limit[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16586 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3932 system_mainBusArbiter.rspTarget system_mainBusArbiter.io_dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16588 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[31] io_gpioA_writeEnable[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16590 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[31] io_gpioA_write[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16592 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3850 $abc$18544$new_n3318 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_mainBusArbiter.rspTarget $abc$18544$new_n3257 $abc$18544$auto$rtlil.cc:2693:MuxGate$16594 +00100 1 +01100 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[31] system_ram._zz_ram_port0[31] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16596 +001 1 +011 1 +110 1 +111 1 +.names resetCtrl_systemClkResetCounter[5] $abc$18544$new_n3841 $abc$18544$auto$rtlil.cc:2693:MuxGate$16598 +01 1 +10 1 +11 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$new_n3832 $abc$18544$auto$rtlil.cc:2693:MuxGate$16600 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3254 $abc$18544$new_n3310 system_cpu.execute_LightShifterPlugin_isActive $abc$18544$auto$rtlil.cc:2693:MuxGate$16602 +1001 1 +1011 1 +1100 1 +1101 1 +.names system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 $abc$18544$new_n3316 $abc$18544$new_n3851 $abc$18544$auto$rtlil.cc:2693:MuxGate$16604 +111 1 +.names $abc$18544$new_n3316 $abc$18544$new_n3851 $abc$18544$new_n3256 system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 $abc$18544$auto$rtlil.cc:2693:MuxGate$16606 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3316 $abc$18544$new_n3309 system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 $abc$18544$auto$rtlil.cc:2693:MuxGate$16608 +1101 1 +1110 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[3] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3657 system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$18544$new_n3998 system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] system_cpu.CsrPlugin_mie_MSIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16610 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.decode_to_execute_CSR_WRITE_OPCODE system_cpu.decode_to_execute_IS_CSR system_cpu.execute_CsrPlugin_csr_772 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$new_n3998 +11111 1 +.names $abc$18544$new_n3998 $abc$18544$new_n4000 system_cpu.CsrPlugin_mie_MTIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16612 +001 1 +011 1 +110 1 +111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3628 $abc$18544$new_n4000 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$18544$new_n3998 $abc$18544$new_n4002 system_cpu.CsrPlugin_mie_MEIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16614 +001 1 +011 1 +110 1 +111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3599 $abc$18544$new_n4002 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_injector_decodeInput_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3318 $abc$18544$auto$rtlil.cc:2693:MuxGate$16616 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n4005 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3850 $abc$18544$auto$rtlil.cc:2693:MuxGate$16618 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3932 system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4005 +10 1 +.names $abc$18544$new_n4007 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$18544$new_n3851 $abc$18544$new_n3708 $abc$18544$auto$rtlil.cc:2693:MuxGate$16620 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_cpu.IBusSimplePlugin_fetchPc_booted $abc$18544$new_n3708 $abc$18544$new_n3722 $abc$18544$new_n4008 system_cpu.DebugPlugin_haltIt $abc$18544$new_n4007 +11110 1 +.names $abc$18544$new_n3852 $abc$18544$new_n4009 system_cpu.DebugPlugin_stepIt $abc$18544$new_n4008 +000 1 +010 1 +011 1 +.names system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid system_cpu.IBusSimplePlugin_injector_decodeInput_valid $abc$18544$new_n4009 +000 1 +.names $abc$18544$new_n4007 system_cpu.IBusSimplePlugin_fetchPc_inc $abc$18544$new_n3707 $abc$18544$auto$rtlil.cc:2693:MuxGate$16622 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n3722 $abc$18544$new_n3309 system_cpu.execute_arbitration_isValid $abc$18544$new_n3851 $abc$18544$auto$rtlil.cc:2693:MuxGate$16624 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3268 $abc$18544$new_n3317 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$auto$rtlil.cc:2693:MuxGate$16626 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names $abc$18544$new_n3255 $abc$18544$new_n4016 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] $abc$18544$new_n4014 $abc$18544$new_n3666 $abc$18544$auto$rtlil.cc:2693:MuxGate$16640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names $abc$18544$new_n3466 $abc$18544$new_n3473 $abc$18544$new_n3678 $abc$18544$new_n4015 $abc$18544$new_n4014 +1000 1 +1001 1 +1101 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[31] system_cpu.decode_to_execute_SRC2[31] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n4015 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$18544$new_n3258 system_cpu._zz_execute_SHIFT_CTRL[1] system_cpu._zz_execute_SHIFT_CTRL[0] $abc$18544$new_n3471 $abc$18544$new_n3480 $abc$18544$new_n4016 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n4018 system_cpu.execute_LightShifterPlugin_amplitudeReg[4] system_cpu.execute_LightShifterPlugin_isActive $abc$18544$new_n3254 system_cpu.decode_to_execute_SRC2[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16692 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +.names $abc$18544$new_n3260 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] $abc$18544$new_n4018 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_cpu.CsrPlugin_mstatus_MIE system_cpu.CsrPlugin_interrupt_code[3] $abc$18544$new_n4020 system_cpu.CsrPlugin_mip_MEIP system_cpu.CsrPlugin_mie_MEIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16696 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4021 system_cpu.CsrPlugin_mie_MTIE system_cpu.CsrPlugin_mip_MTIP $abc$18544$new_n4020 +100 1 +101 1 +110 1 +.names system_cpu.CsrPlugin_mip_MSIP system_cpu.CsrPlugin_mie_MSIE system_cpu.CsrPlugin_mie_MEIE system_cpu.CsrPlugin_mip_MEIP $abc$18544$new_n4021 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names system_cpu.CsrPlugin_mstatus_MIE $abc$18544$new_n4021 system_cpu.CsrPlugin_interrupt_code[2] $abc$18544$new_n4020 $abc$18544$auto$rtlil.cc:2693:MuxGate$16700 +0010 1 +0011 1 +0110 1 +0111 1 +1100 1 +1110 1 +1111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[63] $abc$18544$new_n4024 system_cpu._zz_decode_SRC2 $abc$18544$auto$rtlil.cc:2693:MuxGate$16702 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] $abc$18544$new_n4024 +000 1 +001 1 +100 1 +110 1 +.names $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l288_1 system_cpu.DebugPlugin_disableEbreak system_cpu.when_DebugPlugin_l288 $abc$18544$auto$rtlil.cc:2693:MuxGate$16704 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n3834 systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3838 systemDebugger_1._zz_io_mem_cmd_payload_address[2] $abc$18544$new_n4026 +1110 1 +.names system_cpu.DebugPlugin_debugUsed $abc$18544$new_n3834 $abc$18544$auto$rtlil.cc:2693:MuxGate$16706 +01 1 +10 1 +11 1 +.names $abc$18544$new_n4026 systemDebugger_1._zz_io_mem_cmd_payload_address[36] system_cpu.DebugPlugin_stepIt $abc$18544$auto$rtlil.cc:2693:MuxGate$16708 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l284_1 system_cpu.DebugPlugin_resetIt system_cpu.when_DebugPlugin_l284 $abc$18544$auto$rtlil.cc:2693:MuxGate$16710 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PENABLE $abc$18544$new_n3933 $abc$18544$new_n3711 $abc$18544$auto$rtlil.cc:2693:MuxGate$16712 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names systemDebugger_1.dispatcher_counter[2] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$new_n4032 jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$16724 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names systemDebugger_1.dispatcher_counter[0] systemDebugger_1.dispatcher_counter[1] $abc$18544$new_n4032 +11 1 +.names $abc$18544$new_n4034 $abc$18544$new_n4036 systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$16726 +000 1 +001 1 +011 1 +.names systemDebugger_1.dispatcher_dataLoaded systemDebugger_1.dispatcher_headerLoaded $abc$18544$new_n3833 $abc$18544$new_n4035 $abc$18544$new_n4034 +1100 1 +1101 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[2] system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[1] $abc$18544$new_n4035 +100 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$new_n4032 systemDebugger_1.dispatcher_counter[2] $abc$18544$new_n4036 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4034 systemDebugger_1.dispatcher_dataLoaded jtagBridge_1.flowCCByToggle_1.io_output_valid jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16728 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[7] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16730 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[66] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16732 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_input_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16734 +010 1 +011 1 +101 1 +111 1 +.names jtagBridge_1.flowCCByToggle_1.io_input_valid $abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] jtagBridge_1.flowCCByToggle_1.inputArea_data_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16736 +001 1 +011 1 +100 1 +101 1 +.names jtagBridge_1._zz_jtag_tap_isBypass[1] $abc$18544$new_n2864 jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] +11000 1 +.names jtagBridge_1.flowCCByToggle_1.inputArea_target jtagBridge_1.flowCCByToggle_1.io_input_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$16738 +01 1 +10 1 +.names jtagBridge_1.flowCCByToggle_1.outputArea_hit jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid +01 1 +10 1 +.names jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16740 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_last jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16742 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[31] jtagBridge_1.system_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16744 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[3] jtagBridge_1._zz_jtag_tap_isBypass[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16746 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 io_jtag_tdi jtagBridge_1.jtag_idcodeArea_shifter[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16748 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.system_rsp_valid jtagBridge_1.flowCCByToggle_1.io_output_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$16750 +10 1 +.names system_timer.timerA.counter[15] system_timer.timerA.counter[13] system_timer.timerA.counter[14] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$16752 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.timerB.counter[15] system_timer.timerB.counter[13] system_timer.timerB.counter[14] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$16754 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[31] $abc$18544$new_n4054 $abc$18544$new_n4055 $abc$18544$auto$rtlil.cc:2693:MuxGate$16758 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_cpu.IBusSimplePlugin_cmd_payload_pc[30] $abc$18544$new_n3689 $abc$18544$new_n4054 +1111 1 +.names $abc$18544$new_n3722 system_cpu.BranchPlugin_jumpInterface_payload[31] $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[31] $abc$18544$new_n4055 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3723 system_cpu.CsrPlugin_interrupt_code[3] system_cpu.CsrPlugin_mcause_exceptionCode[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16760 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[31] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16762 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu.CsrPlugin_mepc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16768 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.lastStageIsFiring $abc$18544$new_n2915 $abc$18544$new_n4060 system_cpu.DebugPlugin_busReadDataReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16772 +0001 1 +0011 1 +1000 1 +1001 1 +.names $abc$18544$new_n2912 $abc$18544$new_n4061 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[1] $abc$18544$new_n4060 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n4062 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] $abc$18544$new_n4061 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[1] $abc$18544$new_n4062 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[31] $abc$18544$new_n4064 jtagBridge_1.io_remote_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16774 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[31] $abc$18544$new_n4064 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names io_jtag_tdi $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_instructionShift[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16778 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$18544$new_n2862 jtagBridge_1.jtag_readArea_full_shifter[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_readArea_full_shifter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16782 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[33] io_jtag_tdi jtagBridge_1.system_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16784 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14856 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14858 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[28] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14860 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[27] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14862 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[26] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14864 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14866 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14868 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[23] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14870 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[22] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14872 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14874 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14876 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[19] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14878 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[18] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14880 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14882 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14884 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[15] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14886 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14888 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14890 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[12] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14892 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[11] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14894 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14896 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[9] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14898 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14900 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14902 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14904 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[5] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14906 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14908 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14910 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14912 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[0] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$15034 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[30] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15036 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[29] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15038 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[28] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15040 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[27] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15042 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[26] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15044 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[25] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15046 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[24] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15048 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[23] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15050 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[22] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15052 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[21] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15054 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[20] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15056 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[19] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15058 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[18] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15060 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[17] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15062 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[16] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15064 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[15] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15066 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[14] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15068 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[13] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15070 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[12] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15072 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_3 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15074 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l379 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15076 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_2 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15078 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[8] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15080 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[7] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15082 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[6] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15084 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[5] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15086 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[4] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15088 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[3] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15090 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[2] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15092 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15094 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15096 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4130 system_cpu._zz_execute_SrcPlugin_addSub_2[30] system_cpu._zz_RegFilePlugin_regFile_port0[30] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15244 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] 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system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4150 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4152 system_cpu._zz_execute_SrcPlugin_addSub_2[20] system_cpu._zz_RegFilePlugin_regFile_port0[20] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15264 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4152 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4154 system_cpu._zz_execute_SrcPlugin_addSub_2[19] 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system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4164 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4166 system_cpu._zz_execute_SrcPlugin_addSub_2[13] system_cpu._zz_RegFilePlugin_regFile_port0[13] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15278 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4166 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4168 system_cpu._zz_execute_SrcPlugin_addSub_2[12] system_cpu._zz_RegFilePlugin_regFile_port0[12] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15280 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4168 +11110 1 +.names $abc$18544$new_n4170 $abc$18544$new_n3309 $abc$18544$new_n4171 system_cpu._zz_RegFilePlugin_regFile_port0[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15282 +01001 1 +01011 1 +10000 1 +10001 1 +10010 1 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system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port0[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4173 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4175 system_cpu._zz_execute_SrcPlugin_addSub_2[1] $abc$18544$new_n4131 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15290 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port0[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4175 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4177 system_cpu._zz_execute_SrcPlugin_addSub_2[0] $abc$18544$new_n4131 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15294 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port0[0] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4177 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4179 system_cpu.decode_to_execute_SRC2[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15426 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] system_cpu._zz_decode_SRC2 $abc$18544$new_n4179 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4180 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4182 system_cpu.decode_to_execute_SRC2[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15428 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] system_cpu._zz_decode_SRC2 $abc$18544$new_n4182 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4184 system_cpu.decode_to_execute_SRC2[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15430 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[28] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] system_cpu._zz_decode_SRC2 $abc$18544$new_n4184 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4186 system_cpu.decode_to_execute_SRC2[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15432 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[27] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] system_cpu._zz_decode_SRC2 $abc$18544$new_n4186 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4188 system_cpu.decode_to_execute_SRC2[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15434 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[26] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] system_cpu._zz_decode_SRC2 $abc$18544$new_n4188 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4190 system_cpu.decode_to_execute_SRC2[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15436 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] system_cpu._zz_decode_SRC2 $abc$18544$new_n4190 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4192 system_cpu.decode_to_execute_SRC2[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15438 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] system_cpu._zz_decode_SRC2 $abc$18544$new_n4192 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4194 system_cpu.decode_to_execute_SRC2[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15440 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[23] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] system_cpu._zz_decode_SRC2 $abc$18544$new_n4194 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4196 system_cpu.decode_to_execute_SRC2[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15442 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[22] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] system_cpu._zz_decode_SRC2 $abc$18544$new_n4196 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4198 system_cpu.decode_to_execute_SRC2[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15444 +001 1 +011 1 +100 1 +101 1 +.names $abc$18544$new_n4180 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port1[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] system_cpu._zz_decode_SRC2 $abc$18544$new_n4198 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4200 system_cpu.decode_to_execute_SRC2[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15446 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] system_cpu._zz_decode_SRC2 $abc$18544$new_n4200 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4202 system_cpu.decode_to_execute_SRC2[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15448 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[19] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] system_cpu._zz_decode_SRC2 $abc$18544$new_n4202 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4204 system_cpu.decode_to_execute_SRC2[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15450 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[18] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] system_cpu._zz_decode_SRC2 $abc$18544$new_n4204 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4206 system_cpu.decode_to_execute_SRC2[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15452 +001 1 +011 1 +100 1 +101 1 +.names $abc$18544$new_n4180 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port1[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] system_cpu._zz_decode_SRC2 $abc$18544$new_n4206 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4208 system_cpu.decode_to_execute_SRC2[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15454 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] system_cpu._zz_decode_SRC2 $abc$18544$new_n4208 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4210 system_cpu.decode_to_execute_SRC2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15456 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[15] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] system_cpu._zz_decode_SRC2 $abc$18544$new_n4210 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4212 system_cpu.decode_to_execute_SRC2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15458 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu._zz_decode_SRC2 $abc$18544$new_n4212 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4214 system_cpu.decode_to_execute_SRC2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15460 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu._zz_decode_SRC2 $abc$18544$new_n4214 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4216 system_cpu.decode_to_execute_SRC2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15462 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[12] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu._zz_decode_SRC2 $abc$18544$new_n4216 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4218 system_cpu.decode_to_execute_SRC2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15464 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[11] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu._zz_decode_SRC2 $abc$18544$new_n4218 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4220 system_cpu.decode_to_execute_SRC2[10] system_cpu._zz_RegFilePlugin_regFile_port1[10] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15466 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$18544$new_n4180 $abc$18544$new_n4220 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4222 system_cpu.decode_to_execute_SRC2[9] system_cpu._zz_RegFilePlugin_regFile_port1[9] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15468 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$18544$new_n4180 $abc$18544$new_n4222 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4224 system_cpu.decode_to_execute_SRC2[8] system_cpu._zz_RegFilePlugin_regFile_port1[8] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15470 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$18544$new_n4180 $abc$18544$new_n4224 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4226 system_cpu.decode_to_execute_SRC2[7] system_cpu._zz_RegFilePlugin_regFile_port1[7] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15472 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4180 $abc$18544$new_n4226 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4228 system_cpu.decode_to_execute_SRC2[6] system_cpu._zz_RegFilePlugin_regFile_port1[6] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15474 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4180 $abc$18544$new_n4228 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4230 system_cpu.decode_to_execute_SRC2[5] system_cpu._zz_RegFilePlugin_regFile_port1[5] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15476 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$18544$new_n4180 $abc$18544$new_n4230 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 system_cpu.decode_to_execute_SRC2[4] $abc$18544$new_n4234 $abc$18544$new_n4232 $abc$18544$auto$rtlil.cc:2693:MuxGate$15478 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$18544$new_n4233 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4232 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4233 +1000 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[4] $abc$18544$new_n4180 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$18544$new_n4235 $abc$18544$new_n4234 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 $abc$18544$new_n4235 +00 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4237 system_cpu.decode_to_execute_SRC2[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15480 +001 1 +011 1 +100 1 +101 1 +.names $abc$18544$new_n4238 system_cpu._zz_RegFilePlugin_regFile_port1[3] $abc$18544$new_n4180 $abc$18544$new_n4235 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4237 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$18544$new_n4233 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4238 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4240 system_cpu.decode_to_execute_SRC2[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n4235 $abc$18544$auto$rtlil.cc:2693:MuxGate$15482 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n4241 system_cpu._zz_RegFilePlugin_regFile_port1[2] $abc$18544$new_n4180 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$18544$new_n4233 $abc$18544$new_n4240 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4241 +11 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4243 system_cpu.decode_to_execute_SRC2[1] system_cpu._zz_RegFilePlugin_regFile_port1[1] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15484 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$new_n4235 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$18544$new_n4233 $abc$18544$new_n4243 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4245 system_cpu.decode_to_execute_SRC2[0] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$18544$new_n4235 $abc$18544$auto$rtlil.cc:2693:MuxGate$15486 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[0] $abc$18544$new_n4180 $abc$18544$new_n4233 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$18544$new_n4245 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[30] system_cpu.decode_to_execute_RS1[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15488 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[29] system_cpu.decode_to_execute_RS1[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15490 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[28] system_cpu.decode_to_execute_RS1[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15492 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[27] system_cpu.decode_to_execute_RS1[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15494 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[26] system_cpu.decode_to_execute_RS1[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15496 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[25] system_cpu.decode_to_execute_RS1[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15498 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[24] system_cpu.decode_to_execute_RS1[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15500 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[23] system_cpu.decode_to_execute_RS1[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15502 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[22] system_cpu.decode_to_execute_RS1[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15504 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[21] system_cpu.decode_to_execute_RS1[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15506 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[20] system_cpu.decode_to_execute_RS1[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15508 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[19] system_cpu.decode_to_execute_RS1[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15510 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[18] system_cpu.decode_to_execute_RS1[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15512 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[17] system_cpu.decode_to_execute_RS1[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15514 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[16] system_cpu.decode_to_execute_RS1[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15516 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[15] system_cpu.decode_to_execute_RS1[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15518 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[14] system_cpu.decode_to_execute_RS1[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15520 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[13] system_cpu.decode_to_execute_RS1[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15522 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[12] system_cpu.decode_to_execute_RS1[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15524 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[11] system_cpu.decode_to_execute_RS1[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15526 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[10] system_cpu.decode_to_execute_RS1[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15528 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[9] system_cpu.decode_to_execute_RS1[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15530 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[8] system_cpu.decode_to_execute_RS1[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15532 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[7] system_cpu.decode_to_execute_RS1[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15534 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[6] system_cpu.decode_to_execute_RS1[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15536 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[5] system_cpu.decode_to_execute_RS1[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15538 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[4] system_cpu.decode_to_execute_RS1[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15540 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[3] system_cpu.decode_to_execute_RS1[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15542 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[2] system_cpu.decode_to_execute_RS1[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15544 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[1] system_cpu.decode_to_execute_RS1[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15546 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[0] system_cpu.decode_to_execute_RS1[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15548 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[30] system_cpu.decode_to_execute_RS2[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15550 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[29] system_cpu.decode_to_execute_RS2[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15552 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[28] system_cpu.decode_to_execute_RS2[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15554 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[27] system_cpu.decode_to_execute_RS2[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15556 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[26] system_cpu.decode_to_execute_RS2[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15558 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[25] system_cpu.decode_to_execute_RS2[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15560 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[24] system_cpu.decode_to_execute_RS2[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15562 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[23] system_cpu.decode_to_execute_RS2[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15564 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[22] system_cpu.decode_to_execute_RS2[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15566 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[21] system_cpu.decode_to_execute_RS2[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15568 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[20] system_cpu.decode_to_execute_RS2[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15570 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[19] system_cpu.decode_to_execute_RS2[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15572 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[18] system_cpu.decode_to_execute_RS2[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15574 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[17] system_cpu.decode_to_execute_RS2[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15576 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[16] system_cpu.decode_to_execute_RS2[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15578 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[15] system_cpu.decode_to_execute_RS2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15580 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[14] system_cpu.decode_to_execute_RS2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15582 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[13] system_cpu.decode_to_execute_RS2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15584 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[12] system_cpu.decode_to_execute_RS2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15586 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[11] system_cpu.decode_to_execute_RS2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15588 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[10] system_cpu.decode_to_execute_RS2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15590 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[9] system_cpu.decode_to_execute_RS2[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15592 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[8] system_cpu.decode_to_execute_RS2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15594 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[7] system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15596 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[6] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15598 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[5] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15600 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[4] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15602 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[3] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15604 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[2] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15606 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[1] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15608 +001 1 +011 1 +110 1 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$abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[11] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15666 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[10] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15668 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[9] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15670 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[8] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15672 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15674 +001 1 +011 1 +110 1 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system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15698 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15700 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15702 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15704 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15706 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15708 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15710 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15712 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15714 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15716 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15718 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15720 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15722 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.switch_Misc_l241_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15724 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15726 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15728 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15730 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15732 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15734 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15736 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4348 system_cpu.BranchPlugin_jumpInterface_payload[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15810 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n4400 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4401 $abc$18544$new_n4349 $abc$18544$new_n4348 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4399 $abc$18544$new_n4398 $abc$18544$new_n4397 $abc$18544$new_n4350 $abc$18544$new_n4349 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4396 $abc$18544$new_n4395 $abc$18544$new_n4394 $abc$18544$new_n4351 $abc$18544$new_n4350 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4393 $abc$18544$new_n4392 $abc$18544$new_n4391 $abc$18544$new_n4352 $abc$18544$new_n4351 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$18544$new_n4390 $abc$18544$new_n4388 $abc$18544$new_n4389 $abc$18544$new_n4387 $abc$18544$new_n4353 $abc$18544$new_n4352 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4386 $abc$18544$new_n4384 $abc$18544$new_n4385 $abc$18544$new_n4383 $abc$18544$new_n4354 $abc$18544$new_n4353 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4382 $abc$18544$new_n4380 $abc$18544$new_n4381 $abc$18544$new_n4379 $abc$18544$new_n4355 $abc$18544$new_n4354 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4378 $abc$18544$new_n4376 $abc$18544$new_n4377 $abc$18544$new_n4375 $abc$18544$new_n4356 $abc$18544$new_n4355 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names $abc$18544$new_n4373 $abc$18544$new_n4374 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] $abc$18544$new_n4372 $abc$18544$new_n4357 $abc$18544$new_n4356 +00011 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4371 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] $abc$18544$new_n4370 $abc$18544$new_n4358 $abc$18544$new_n4357 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$18544$new_n4365 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] $abc$18544$new_n4359 system_cpu.decode_to_execute_PC[7] system_cpu.decode_to_execute_RS1[7] $abc$18544$new_n4358 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 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1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4368 $abc$18544$new_n4363 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n4362 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4366 $abc$18544$new_n4364 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$new_n4363 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[2] system_cpu.decode_to_execute_PC[2] $abc$18544$new_n4364 +000 1 +010 1 +100 1 +101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] $abc$18544$new_n4365 +11 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[0] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[10] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[0] system_cpu.decode_to_execute_RS1[1] $abc$18544$new_n4366 +10011 1 +10111 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[3] system_cpu.decode_to_execute_PC[3] $abc$18544$new_n4368 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[4] system_cpu.decode_to_execute_PC[4] $abc$18544$new_n4369 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[9] system_cpu.decode_to_execute_PC[9] $abc$18544$new_n4370 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[8] system_cpu.decode_to_execute_PC[8] $abc$18544$new_n4371 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[11] system_cpu.decode_to_execute_PC[11] $abc$18544$new_n4372 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[10] system_cpu.decode_to_execute_PC[10] $abc$18544$new_n4373 +000 1 +010 1 +100 1 +101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[10] $abc$18544$new_n4374 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[13] system_cpu.decode_to_execute_PC[13] $abc$18544$new_n4375 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[12] system_cpu.decode_to_execute_PC[12] $abc$18544$new_n4376 +000 1 +010 1 +100 1 +101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu.switch_Misc_l241_1 $abc$18544$new_n4377 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n4378 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[15] system_cpu.decode_to_execute_PC[15] $abc$18544$new_n4379 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[14] system_cpu.decode_to_execute_PC[14] $abc$18544$new_n4380 +000 1 +010 1 +100 1 +101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[14] $abc$18544$new_n4381 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] $abc$18544$new_n4382 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[17] system_cpu.decode_to_execute_PC[17] $abc$18544$new_n4383 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[16] system_cpu.decode_to_execute_PC[16] $abc$18544$new_n4384 +000 1 +010 1 +100 1 +101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[16] $abc$18544$new_n4385 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[15] $abc$18544$new_n4386 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[19] system_cpu.decode_to_execute_PC[19] $abc$18544$new_n4387 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[18] system_cpu.decode_to_execute_PC[18] $abc$18544$new_n4388 +000 1 +010 1 +100 1 +101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[18] $abc$18544$new_n4389 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[17] $abc$18544$new_n4390 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[22] system_cpu.decode_to_execute_PC[22] $abc$18544$new_n4391 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[21] system_cpu.decode_to_execute_PC[21] $abc$18544$new_n4392 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[20] system_cpu.decode_to_execute_PC[20] $abc$18544$new_n4393 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[25] system_cpu.decode_to_execute_PC[25] $abc$18544$new_n4394 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[24] system_cpu.decode_to_execute_PC[24] $abc$18544$new_n4395 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[23] system_cpu.decode_to_execute_PC[23] $abc$18544$new_n4396 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[28] system_cpu.decode_to_execute_PC[28] $abc$18544$new_n4397 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[27] system_cpu.decode_to_execute_PC[27] $abc$18544$new_n4398 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[26] system_cpu.decode_to_execute_PC[26] $abc$18544$new_n4399 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[30] system_cpu.decode_to_execute_PC[30] $abc$18544$new_n4400 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[29] system_cpu.decode_to_execute_PC[29] $abc$18544$new_n4401 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4401 $abc$18544$new_n4349 system_cpu.BranchPlugin_jumpInterface_payload[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15812 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4397 $abc$18544$new_n4404 system_cpu.BranchPlugin_jumpInterface_payload[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15814 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4399 $abc$18544$new_n4398 $abc$18544$new_n4350 $abc$18544$new_n4404 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4406 system_cpu.BranchPlugin_jumpInterface_payload[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15816 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n4398 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4399 $abc$18544$new_n4350 $abc$18544$new_n4406 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4399 $abc$18544$new_n4350 system_cpu.BranchPlugin_jumpInterface_payload[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15818 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4394 $abc$18544$new_n4409 system_cpu.BranchPlugin_jumpInterface_payload[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15820 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n4395 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4410 $abc$18544$new_n4409 +000 1 +100 1 +101 1 +110 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4396 $abc$18544$new_n4351 $abc$18544$new_n4410 +000 1 +100 1 +101 1 +110 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4395 $abc$18544$new_n4410 system_cpu.BranchPlugin_jumpInterface_payload[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15822 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4396 $abc$18544$new_n4351 system_cpu.BranchPlugin_jumpInterface_payload[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15824 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4391 $abc$18544$new_n4414 system_cpu.BranchPlugin_jumpInterface_payload[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15826 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n4392 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4415 $abc$18544$new_n4414 +001 1 +100 1 +101 1 +111 1 +.names $abc$18544$new_n4393 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4352 $abc$18544$new_n4415 +001 1 +100 1 +101 1 +111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4392 $abc$18544$new_n4415 system_cpu.BranchPlugin_jumpInterface_payload[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15828 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4393 $abc$18544$new_n4352 system_cpu.BranchPlugin_jumpInterface_payload[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15830 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4389 $abc$18544$new_n4387 $abc$18544$new_n4419 system_cpu.BranchPlugin_jumpInterface_payload[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15832 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n4390 $abc$18544$new_n4388 $abc$18544$new_n4353 $abc$18544$new_n4419 +011 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4390 $abc$18544$new_n4388 $abc$18544$new_n4353 system_cpu.BranchPlugin_jumpInterface_payload[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15834 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 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$abc$18544$auto$rtlil.cc:2693:MuxGate$15840 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n4382 $abc$18544$new_n4380 $abc$18544$new_n4355 $abc$18544$new_n4425 +010 1 +100 1 +110 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4382 $abc$18544$new_n4380 $abc$18544$new_n4355 system_cpu.BranchPlugin_jumpInterface_payload[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15842 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4377 $abc$18544$new_n4375 $abc$18544$new_n4428 system_cpu.BranchPlugin_jumpInterface_payload[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15844 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n4378 $abc$18544$new_n4376 $abc$18544$new_n4356 $abc$18544$new_n4428 +011 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4378 $abc$18544$new_n4376 $abc$18544$new_n4356 system_cpu.BranchPlugin_jumpInterface_payload[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15846 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4374 $abc$18544$new_n4372 $abc$18544$new_n4431 system_cpu.BranchPlugin_jumpInterface_payload[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15848 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n4373 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] $abc$18544$new_n4357 $abc$18544$new_n4431 +001 1 +100 1 +101 1 +111 1 +.names $abc$18544$new_n3256 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] $abc$18544$new_n4373 $abc$18544$new_n4357 system_cpu.BranchPlugin_jumpInterface_payload[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15850 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] $abc$18544$new_n4370 $abc$18544$new_n4434 system_cpu.BranchPlugin_jumpInterface_payload[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15852 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n4371 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] $abc$18544$new_n4358 $abc$18544$new_n4434 +001 1 +100 1 +101 1 +111 1 +.names $abc$18544$new_n3256 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] $abc$18544$new_n4371 $abc$18544$new_n4358 system_cpu.BranchPlugin_jumpInterface_payload[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15854 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4359 $abc$18544$new_n4437 system_cpu.BranchPlugin_jumpInterface_payload[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15856 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[7] system_cpu.decode_to_execute_RS1[7] $abc$18544$new_n4437 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4360 $abc$18544$new_n4439 system_cpu.BranchPlugin_jumpInterface_payload[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15858 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[6] system_cpu.decode_to_execute_RS1[6] $abc$18544$new_n4439 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4361 $abc$18544$new_n4441 system_cpu.BranchPlugin_jumpInterface_payload[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15860 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[5] system_cpu.decode_to_execute_RS1[5] $abc$18544$new_n4441 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4443 system_cpu.BranchPlugin_jumpInterface_payload[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15862 +010 1 +011 1 +101 1 +111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4369 $abc$18544$new_n4362 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n4443 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4445 system_cpu.BranchPlugin_jumpInterface_payload[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15864 +010 1 +011 1 +101 1 +111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4368 $abc$18544$new_n4363 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n4445 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4447 system_cpu.BranchPlugin_jumpInterface_payload[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15866 +010 1 +011 1 +101 1 +111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4366 $abc$18544$new_n4364 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$new_n4447 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] system_cpu.decode_to_execute_PC[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15870 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] system_cpu.decode_to_execute_PC[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15872 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] system_cpu.decode_to_execute_PC[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15874 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] system_cpu.decode_to_execute_PC[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15876 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] system_cpu.decode_to_execute_PC[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15878 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] system_cpu.decode_to_execute_PC[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15880 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] system_cpu.decode_to_execute_PC[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15882 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] system_cpu.decode_to_execute_PC[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15884 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] system_cpu.decode_to_execute_PC[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15886 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] system_cpu.decode_to_execute_PC[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15888 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] system_cpu.decode_to_execute_PC[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15890 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] system_cpu.decode_to_execute_PC[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15892 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] system_cpu.decode_to_execute_PC[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15894 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] system_cpu.decode_to_execute_PC[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15896 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] system_cpu.decode_to_execute_PC[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15898 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] system_cpu.decode_to_execute_PC[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15900 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu.decode_to_execute_PC[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15902 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu.decode_to_execute_PC[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15904 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu.decode_to_execute_PC[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15906 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu.decode_to_execute_PC[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15908 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.decode_to_execute_PC[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15910 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] system_cpu.decode_to_execute_PC[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15912 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] system_cpu.decode_to_execute_PC[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15914 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.decode_to_execute_PC[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15916 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.decode_to_execute_PC[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15918 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.decode_to_execute_PC[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15920 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] system_cpu.decode_to_execute_PC[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15922 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu.decode_to_execute_PC[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15924 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu.decode_to_execute_PC[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15926 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15970 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[19] system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16192 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4480 apb3Router_1.io_input_PADDR[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16194 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[18] system_mainBusArbiter.io_dBus_cmd_payload_address[18] $abc$18544$new_n4480 +000 1 +001 1 +100 1 +110 1 +.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[17] system_cpu.IBusSimplePlugin_cmd_payload_pc[17] system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16196 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[16] system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_mainBusArbiter.io_dBus_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16198 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4484 apb3Router_1.io_input_PADDR[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16200 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[15] system_mainBusArbiter.io_dBus_cmd_payload_address[15] $abc$18544$new_n4484 +000 1 +001 1 +100 1 +110 1 +.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[14] system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_mainBusArbiter.io_dBus_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16202 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4487 apb3Router_1.io_input_PADDR[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16204 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[13] system_mainBusArbiter.io_dBus_cmd_payload_address[13] $abc$18544$new_n4487 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[12] system_mainBusArbiter.io_dBus_cmd_payload_address[12] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] apb3Router_1.io_input_PADDR[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16206 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[7] system_mainBusArbiter.io_dBus_cmd_payload_address[7] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] apb3Router_1.io_input_PADDR[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16216 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[6] system_mainBusArbiter.io_dBus_cmd_payload_address[6] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] apb3Router_1.io_input_PADDR[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16218 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[5] system_mainBusArbiter.io_dBus_cmd_payload_address[5] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] apb3Router_1.io_input_PADDR[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16220 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[4] system_mainBusArbiter.io_dBus_cmd_payload_address[4] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] apb3Router_1.io_input_PADDR[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16222 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[3] system_mainBusArbiter.io_dBus_cmd_payload_address[3] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] apb3Router_1.io_input_PADDR[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16224 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[2] system_mainBusArbiter.io_dBus_cmd_payload_address[2] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] apb3Router_1.io_input_PADDR[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16226 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[10] system_cpu._zz_RegFilePlugin_regFile_port0[10] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16302 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[9] system_cpu._zz_RegFilePlugin_regFile_port0[9] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16306 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[8] system_cpu._zz_RegFilePlugin_regFile_port0[8] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16310 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu._zz_RegFilePlugin_regFile_port0[7] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16314 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[6] system_cpu._zz_RegFilePlugin_regFile_port0[6] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16318 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[5] system_cpu._zz_RegFilePlugin_regFile_port0[5] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16322 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_size[0] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16386 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4511 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16388 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.switch_Misc_l241_1 $abc$18544$new_n4510 +00 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[30] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[14] $abc$18544$new_n4511 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4513 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16390 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[29] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[13] $abc$18544$new_n4513 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4515 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16392 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[28] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[12] $abc$18544$new_n4515 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4517 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16394 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[27] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[11] $abc$18544$new_n4517 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4519 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16396 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[26] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[10] $abc$18544$new_n4519 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4521 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16398 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[25] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[9] $abc$18544$new_n4521 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4523 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16400 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[24] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[8] $abc$18544$new_n4523 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] system_cpu.decode_to_execute_RS2[23] system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16402 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] system_cpu.decode_to_execute_RS2[22] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16404 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] system_cpu.decode_to_execute_RS2[21] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16406 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] system_cpu.decode_to_execute_RS2[20] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16408 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] system_cpu.decode_to_execute_RS2[19] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16410 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] system_cpu.decode_to_execute_RS2[18] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16412 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] system_cpu.decode_to_execute_RS2[17] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16414 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] system_cpu.decode_to_execute_RS2[16] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16416 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] system_cpu._zz_dBus_cmd_payload_data[7] system_cpu.decode_to_execute_RS2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16418 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] system_cpu._zz_dBus_cmd_payload_data[6] system_cpu.decode_to_execute_RS2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16420 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] system_cpu._zz_dBus_cmd_payload_data[5] system_cpu.decode_to_execute_RS2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16422 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] system_cpu._zz_dBus_cmd_payload_data[4] system_cpu.decode_to_execute_RS2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16424 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] system_cpu._zz_dBus_cmd_payload_data[3] system_cpu.decode_to_execute_RS2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16426 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] system_cpu._zz_dBus_cmd_payload_data[2] system_cpu.decode_to_execute_RS2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16428 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] system_cpu._zz_dBus_cmd_payload_data[1] system_cpu.decode_to_execute_RS2[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16430 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] system_cpu._zz_dBus_cmd_payload_data[0] system_cpu.decode_to_execute_RS2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16432 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16434 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16436 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16438 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16440 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16442 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16444 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16446 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16448 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3408 system_mainBusArbiter.io_dBus_cmd_payload_address[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16450 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3476 system_mainBusArbiter.io_dBus_cmd_payload_address[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16452 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[28] $abc$18544$new_n3485 system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16454 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3490 system_mainBusArbiter.io_dBus_cmd_payload_address[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16456 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3497 system_mainBusArbiter.io_dBus_cmd_payload_address[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16458 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3503 system_mainBusArbiter.io_dBus_cmd_payload_address[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16460 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[24] $abc$18544$new_n3511 system_cpu._zz_execute_SrcPlugin_addSub_2[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16462 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3515 system_mainBusArbiter.io_dBus_cmd_payload_address[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16464 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[22] $abc$18544$new_n3523 system_cpu._zz_execute_SrcPlugin_addSub_2[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16466 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3527 system_mainBusArbiter.io_dBus_cmd_payload_address[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16468 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3534 system_mainBusArbiter.io_dBus_cmd_payload_address[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16470 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3540 system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16472 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3547 system_mainBusArbiter.io_dBus_cmd_payload_address[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16474 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3553 system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16476 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3560 system_mainBusArbiter.io_dBus_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16478 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3568 system_mainBusArbiter.io_dBus_cmd_payload_address[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16480 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3574 system_mainBusArbiter.io_dBus_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16482 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3582 system_mainBusArbiter.io_dBus_cmd_payload_address[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16484 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[12] $abc$18544$new_n3589 system_cpu._zz_execute_SrcPlugin_addSub_2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16486 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3596 system_mainBusArbiter.io_dBus_cmd_payload_address[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16488 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[10] $abc$18544$new_n3606 system_cpu._zz_execute_SrcPlugin_addSub_2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16490 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3612 system_mainBusArbiter.io_dBus_cmd_payload_address[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16492 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[8] $abc$18544$new_n3619 system_cpu._zz_execute_SrcPlugin_addSub_2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16494 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3625 system_mainBusArbiter.io_dBus_cmd_payload_address[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16496 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3637 system_mainBusArbiter.io_dBus_cmd_payload_address[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16498 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3642 system_mainBusArbiter.io_dBus_cmd_payload_address[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16500 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3649 system_mainBusArbiter.io_dBus_cmd_payload_address[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16502 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3654 system_mainBusArbiter.io_dBus_cmd_payload_address[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16504 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3664 system_mainBusArbiter.io_dBus_cmd_payload_address[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16506 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3670 system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16508 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16510 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_cpu.switch_Misc_l241_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16524 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4581 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] $abc$18544$new_n4510 system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16526 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[31] system_cpu.decode_to_execute_RS2[15] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n4581 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3678 system_mainBusArbiter.io_dBus_cmd_payload_address[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16528 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_wr system_cpu.dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16530 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_834 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$new_n4585 $abc$18544$auto$rtlil.cc:2693:MuxGate$16628 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4586 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4585 +11000 1 +.names $abc$18544$new_n4587 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4586 +1000 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] system_cpu._zz_decode_SRC2 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$18544$new_n4587 +1100 1 +.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_772 $abc$18544$new_n4590 $abc$18544$new_n4589 $abc$18544$auto$rtlil.cc:2693:MuxGate$16630 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n4587 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4589 +11000 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4590 +0000 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4592 system_cpu.execute_CsrPlugin_csr_836 $abc$18544$auto$rtlil.cc:2693:MuxGate$16632 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4589 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4592 +11000 1 +.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_768 $abc$18544$new_n4586 $abc$18544$new_n4590 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16634 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_BRANCH_DO system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] $abc$18544$new_n4595 $abc$18544$auto$rtlil.cc:2693:MuxGate$16638 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.switch_Misc_l241_1 $abc$18544$new_n4596 $abc$18544$new_n4597 $abc$18544$new_n4595 +00000 1 +00010 1 +00100 1 +00101 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +10101 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3685 $abc$18544$new_n3678 $abc$18544$new_n3681 $abc$18544$new_n4596 +100 1 +101 1 +110 1 +.names $abc$18544$new_n4613 $abc$18544$new_n4611 $abc$18544$new_n4604 $abc$18544$new_n4598 $abc$18544$new_n4597 +1111 1 +.names $abc$18544$new_n4601 $abc$18544$new_n4599 $abc$18544$new_n4603 system_cpu.decode_to_execute_SRC2[17] system_cpu._zz_execute_SrcPlugin_addSub_2[17] $abc$18544$new_n4598 +11100 1 +11111 1 +.names $abc$18544$new_n4600 system_cpu.decode_to_execute_SRC2[23] system_cpu._zz_execute_SrcPlugin_addSub_2[23] system_cpu.decode_to_execute_SRC2[24] system_cpu._zz_execute_SrcPlugin_addSub_2[24] $abc$18544$new_n4599 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[16] system_cpu._zz_execute_SrcPlugin_addSub_2[16] system_cpu.decode_to_execute_SRC2[28] system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$new_n4600 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4602 $abc$18544$new_n3681 system_cpu.decode_to_execute_SRC2[0] system_cpu._zz_execute_SrcPlugin_addSub_2[0] $abc$18544$new_n4601 +1100 1 +1111 1 +.names system_cpu.decode_to_execute_SRC2[2] system_cpu._zz_execute_SrcPlugin_addSub_2[2] system_cpu.decode_to_execute_SRC2[30] system_cpu._zz_execute_SrcPlugin_addSub_2[30] $abc$18544$new_n4602 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[9] system_cpu.decode_to_execute_SRC2[9] system_cpu.decode_to_execute_SRC2[13] system_cpu._zz_execute_SrcPlugin_addSub_2[13] $abc$18544$new_n4603 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4607 $abc$18544$new_n4605 $abc$18544$new_n4609 system_cpu.decode_to_execute_SRC2[20] system_cpu._zz_execute_SrcPlugin_addSub_2[20] $abc$18544$new_n4604 +11100 1 +11111 1 +.names $abc$18544$new_n4606 system_cpu._zz_execute_SrcPlugin_addSub_2[5] system_cpu.decode_to_execute_SRC2[5] system_cpu._zz_execute_SrcPlugin_addSub_2[6] system_cpu.decode_to_execute_SRC2[6] $abc$18544$new_n4605 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[18] system_cpu._zz_execute_SrcPlugin_addSub_2[18] system_cpu.decode_to_execute_SRC2[26] system_cpu._zz_execute_SrcPlugin_addSub_2[26] $abc$18544$new_n4606 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4608 system_cpu._zz_execute_SrcPlugin_addSub_2[4] system_cpu.decode_to_execute_SRC2[4] system_cpu.decode_to_execute_SRC2[1] system_cpu._zz_execute_SrcPlugin_addSub_2[1] $abc$18544$new_n4607 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[3] system_cpu._zz_execute_SrcPlugin_addSub_2[3] system_cpu.decode_to_execute_SRC2[19] system_cpu._zz_execute_SrcPlugin_addSub_2[19] $abc$18544$new_n4608 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4610 system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu.decode_to_execute_SRC2[7] system_cpu.decode_to_execute_SRC2[22] system_cpu._zz_execute_SrcPlugin_addSub_2[22] $abc$18544$new_n4609 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[8] system_cpu._zz_execute_SrcPlugin_addSub_2[8] system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu.decode_to_execute_SRC2[11] $abc$18544$new_n4610 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4612 system_cpu.decode_to_execute_SRC2[21] system_cpu._zz_execute_SrcPlugin_addSub_2[21] system_cpu.decode_to_execute_SRC2[27] system_cpu._zz_execute_SrcPlugin_addSub_2[27] $abc$18544$new_n4611 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[12] system_cpu._zz_execute_SrcPlugin_addSub_2[12] system_cpu.decode_to_execute_SRC2[15] system_cpu._zz_execute_SrcPlugin_addSub_2[15] $abc$18544$new_n4612 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4614 system_cpu._zz_execute_SrcPlugin_addSub_2[10] system_cpu.decode_to_execute_SRC2[10] system_cpu.decode_to_execute_SRC2[14] system_cpu._zz_execute_SrcPlugin_addSub_2[14] $abc$18544$new_n4613 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[25] system_cpu._zz_execute_SrcPlugin_addSub_2[25] system_cpu.decode_to_execute_SRC2[29] system_cpu._zz_execute_SrcPlugin_addSub_2[29] $abc$18544$new_n4614 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$18544$new_n3670 $abc$18544$auto$rtlil.cc:2693:MuxGate$16642 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4617 system_cpu.decode_to_execute_DO_EBREAK $abc$18544$auto$rtlil.cc:2693:MuxGate$16644 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n4618 system_cpu.DebugPlugin_debugUsed system_cpu.DebugPlugin_haltIt system_cpu.DebugPlugin_disableEbreak system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$18544$new_n4617 +11000 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4619 $abc$18544$new_n4618 +111 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$18544$new_n4619 +00 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4621 system_cpu.decode_to_execute_SRC2[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16646 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[31] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu._zz_decode_SRC2 $abc$18544$new_n4621 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n4623 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n3309 $abc$18544$auto$rtlil.cc:2693:MuxGate$16648 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n4624 $abc$18544$new_n4310 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4623 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4625 $abc$18544$new_n4624 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4625 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[31] system_cpu.decode_to_execute_RS2[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16650 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[31] system_cpu.decode_to_execute_RS1[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16652 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4629 system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16654 +001 1 +011 1 +100 1 +101 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4629 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SHIFT_CTRL[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4310 $abc$18544$auto$rtlil.cc:2693:MuxGate$16656 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu._zz_execute_ALU_BITWISE_CTRL[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16658 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4633 system_cpu.decode_to_execute_SRC_LESS_UNSIGNED system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16660 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4633 +10 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_ALU_CTRL[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4635 $abc$18544$auto$rtlil.cc:2693:MuxGate$16662 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$new_n4635 +000 1 +010 1 +011 1 +.names $abc$18544$new_n3256 system_cpu._zz_memory_ENV_CTRL system_cpu._zz_execute_ENV_CTRL $abc$18544$auto$rtlil.cc:2693:MuxGate$16664 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_ENV_CTRL $abc$18544$new_n4618 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16666 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$18544$new_n3309 system_cpu.decode_to_execute_IS_CSR system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4619 $abc$18544$auto$rtlil.cc:2693:MuxGate$16668 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names system_cpu.dBus_cmd_payload_wr $abc$18544$new_n3256 $abc$18544$auto$rtlil.cc:2693:MuxGate$16670 +10 1 +.names $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16672 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_REGFILE_WRITE_VALID system_cpu.decode_to_execute_REGFILE_WRITE_VALID $abc$18544$auto$rtlil.cc:2693:MuxGate$16674 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4643 system_cpu.decode_to_execute_REGFILE_WRITE_VALID $abc$18544$new_n4644 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16678 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n3306 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4619 $abc$18544$new_n4643 +00100 1 +00101 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$18544$new_n4644 +0000 1 +.names system_cpu.decode_to_execute_MEMORY_ENABLE $abc$18544$new_n3256 $abc$18544$auto$rtlil.cc:2693:MuxGate$16680 +01 1 +10 1 +11 1 +.names $abc$18544$new_n3309 system_cpu.decode_to_execute_MEMORY_ENABLE system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16682 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +11000 1 +.names $abc$18544$new_n4624 $abc$18544$new_n3309 system_cpu.decode_to_execute_SRC_USE_SUB_LESS $abc$18544$auto$rtlil.cc:2693:MuxGate$16684 +001 1 +010 1 +011 1 +.names $abc$18544$new_n3309 system_cpu.decode_to_execute_CSR_WRITE_OPCODE $abc$18544$new_n4649 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16686 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$18544$new_n4649 +1000 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC2 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$auto$rtlil.cc:2693:MuxGate$16690 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[31] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16714 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[1] system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16718 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names io_apb_decoder.io_input_PSEL $abc$18544$new_n3934 apb3Router_1.io_input_PWRITE $abc$18544$auto$rtlil.cc:2693:MuxGate$16722 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4656 $abc$18544$new_n4655 system_cpu.BranchPlugin_jumpInterface_payload[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16756 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4401 $abc$18544$new_n4400 $abc$18544$new_n4349 $abc$18544$new_n4655 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[31] system_cpu.decode_to_execute_RS1[31] $abc$18544$new_n4656 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16764 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu.decode_to_execute_PC[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16766 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu._zz_RegFilePlugin_regFile_port0[11] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16788 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4661 system_cpu._zz_execute_SrcPlugin_addSub_2[4] $abc$18544$new_n4131 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16792 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port0[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4661 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4663 system_cpu._zz_execute_SrcPlugin_addSub_2[31] $abc$18544$new_n4131 system_cpu._zz_RegFilePlugin_regFile_port0[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16794 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC2 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4663 +1110 1 +.names system_timer.interruptCtrl_1.pendings[0] system_timer.interruptCtrl_1.io_masks[0] system_timer.interruptCtrl_1.pendings[1] system_timer.interruptCtrl_1.io_masks[1] system_cpu.timerInterrupt +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_idcodeArea_ctrl_capture +1100 1 +.names apb3Router_1.selIndex[0] apb3Router_1.selIndex[1] $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +10 1 +.names apb3Router_1.selIndex[1] apb3Router_1.selIndex[0] $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +01 1 +10 1 +11 1 +.names system_cpu.decode_to_execute_CSR_WRITE_OPCODE system_cpu.decode_to_execute_IS_CSR system_cpu.execute_CsrPlugin_csr_836 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$auto$opt_dff.cc:253:combine_resets$3598 +11111 1 +.names $abc$18544$new_n4670 $abc$18544$new_n3711 system_mainBusDecoder_logic_noHit +00 1 +.names $abc$18544$new_n4675 $abc$18544$new_n3716 $abc$18544$new_n4672 $abc$18544$new_n4671 $abc$18544$new_n3712 $abc$18544$new_n4670 +11110 1 +.names $abc$18544$new_n3718 $abc$18544$new_n3717 $abc$18544$new_n4671 +11 1 +.names $abc$18544$new_n4674 $abc$18544$new_n4673 $abc$18544$new_n4487 $abc$18544$new_n4484 $abc$18544$new_n4480 $abc$18544$new_n4672 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_cpu.IBusSimplePlugin_cmd_payload_pc[17] system_mainBusArbiter.io_dBus_cmd_payload_address[14] system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$new_n4673 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_mainBusArbiter.io_dBus_cmd_payload_address[16] system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$new_n4674 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[30] system_mainBusArbiter.io_dBus_cmd_payload_address[28] system_mainBusArbiter.io_dBus_cmd_payload_address[30] $abc$18544$new_n4675 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.when_JtagTap_l120 +0000 1 +.names $abc$18544$new_n4678 system_uartCtrl.uartCtrl_1.clockDivider_counter[19] system_uartCtrl.uartCtrl_1.clockDivider_tick +10 1 +.names $abc$18544$new_n4679 system_uartCtrl.uartCtrl_1.clockDivider_counter[18] $abc$18544$new_n4678 +10 1 +.names $abc$18544$new_n4680 system_uartCtrl.uartCtrl_1.clockDivider_counter[17] $abc$18544$new_n4679 +10 1 +.names $abc$18544$new_n4681 system_uartCtrl.uartCtrl_1.clockDivider_counter[16] $abc$18544$new_n4680 +10 1 +.names $abc$18544$new_n4685 $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[13] system_uartCtrl.uartCtrl_1.clockDivider_counter[15] $abc$18544$new_n4681 +1100 1 +.names $abc$18544$new_n4683 system_uartCtrl.uartCtrl_1.clockDivider_counter[9] $abc$18544$new_n4682 +10 1 +.names $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[8] system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] system_uartCtrl.uartCtrl_1.clockDivider_counter[7] $abc$18544$new_n4683 +10000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[4] system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] system_uartCtrl.uartCtrl_1.clockDivider_counter[3] $abc$18544$new_n4684 +00000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_counter[14] $abc$18544$new_n4685 +0000 1 +.names system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\sampler_value[0:0] +011 1 +101 1 +110 1 +111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid system_uartCtrl.bridge_interruptCtrl_writeIntEnable system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid system_uartCtrl.bridge_interruptCtrl_readIntEnable system_uartCtrl.uartCtrl_1.io_readBreak system_cpu.externalInterrupt +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$18544$new_n5026 $abc$18544$new_n2756 system_timer.prescaler_1.when_Prescaler_l17 +01 1 +10 1 +11 1 +.names $abc$18544$new_n3834 systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3837 $abc$18544$new_n4035 toplevel_system_cpu_debug_bus_cmd_fire +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3317 $abc$18544$new_n4009 $abc$18544$new_n3314 system_cpu.execute_arbitration_isValid $abc$18544$flatten\system_cpu.$0\DebugPlugin_isPipBusy[0:0] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n4670 $abc$18544$new_n3933 system_ram.io_bus_cmd_fire +11 1 +.names system_ram.io_bus_cmd_fire $abc$18544$new_n3934 $abc$18544$flatten\system_ram.$0\_zz_io_bus_rsp_valid[0:0] +10 1 +.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire $abc$18544$new_n4694 system_mainBusArbiter.io_dBus_cmd_payload_address[1] system_mainBusArbiter.io_dBus_cmd_payload_size[1] $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] +11001 1 +11010 1 +11011 1 +.names system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_size[0] $abc$18544$new_n4694 +000 1 +.names $abc$18544$new_n4696 system_ram.io_bus_cmd_fire $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] +11 1 +.names $abc$18544$new_n3934 system_mainBusArbiter.io_dBus_cmd_payload_address[1] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_mainBusArbiter.io_dBus_cmd_payload_size[0] $abc$18544$new_n4696 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$new_n4694 $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] +1100 1 +.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] +1100 1 +.names system_uartCtrl.bridge_misc_doBreak $abc$18544$new_n3928 $abc$18544$new_n4700 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\_zz_io_txd[0:0] +000 1 +.names system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$new_n4701 system_uartCtrl.uartCtrl_1.tx.stateMachine_parity $abc$18544$new_n4700 +10010 1 +10011 1 +11000 1 +11010 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] $abc$18544$new_n4702 $abc$18544$new_n4704 $abc$18544$new_n4701 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n4703 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[7] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[6] $abc$18544$new_n4702 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[5] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[4] $abc$18544$new_n4703 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4705 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[0] $abc$18544$new_n4704 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[2] $abc$18544$new_n4705 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_parity system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$new_n2991 $abc$18544$new_n3010 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\stateMachine_parity[0:0] +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[0] +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[1] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2997 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[2] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names system_uartCtrl.bridge_misc_breakDetected system_uartCtrl.when_BusSlaveFactory_l347_2 $abc$18544$new_n3957 system_uartCtrl.uartCtrl_1.io_readBreak system_uartCtrl.system_uartCtrl_uartCtrl_1_io_readBreak_regNext $abc$18544$flatten\system_uartCtrl.$0\bridge_misc_breakDetected[0:0] +00010 1 +00110 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3957 system_uartCtrl.when_BusSlaveFactory_l347_3 system_uartCtrl.bridge_misc_doBreak system_uartCtrl.when_BusSlaveFactory_l379 $abc$18544$flatten\system_uartCtrl.$0\bridge_misc_doBreak[0:0] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n4713 $abc$18544$new_n4723 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$new_n3963 apb3Router_1._zz_io_input_PRDATA[0] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$18544$new_n4714 $abc$18544$new_n4722 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[0] $abc$18544$new_n4713 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names apb3Router_1.selIndex[1] $abc$18544$new_n4715 $abc$18544$new_n4718 system_timer._zz_io_limit[0] $abc$18544$new_n2757 $abc$18544$new_n4714 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$18544$new_n4716 $abc$18544$new_n2717 system_timer.timerABridge_ticksEnable[0] $abc$18544$new_n4715 +100 1 +101 1 +110 1 +.names system_timer.system_timer_timerA_io_limit_driver[0] $abc$18544$new_n2740 system_timer.timerA.counter[0] $abc$18544$new_n4717 $abc$18544$new_n4716 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3893 $abc$18544$new_n3975 $abc$18544$new_n4717 +11 1 +.names $abc$18544$new_n4720 $abc$18544$new_n4719 $abc$18544$new_n3969 system_timer.timerB.counter[0] $abc$18544$new_n4718 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$18544$new_n2722 $abc$18544$new_n3969 system_timer.system_timer_timerB_io_limit_driver[0] system_timer.timerBBridge_ticksEnable[0] $abc$18544$new_n2713 $abc$18544$new_n4719 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_timer.interruptCtrl_1.io_masks[0] $abc$18544$new_n2822 system_timer.interruptCtrl_1.pendings[0] $abc$18544$new_n4721 $abc$18544$new_n4720 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n4721 +11000 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[0] $abc$18544$new_n2723 io_gpioA_write[0] $abc$18544$new_n4722 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] system_uartCtrl.bridge_misc_readError system_uartCtrl.bridge_read_streamBreaked_payload[0] $abc$18544$new_n4723 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4725 $abc$18544$new_n4734 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[1] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[1] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4726 $abc$18544$new_n4733 $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3958 system_uartCtrl.bridge_misc_readOverflowError $abc$18544$new_n4725 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names apb3Router_1.selIndex[1] $abc$18544$new_n4727 $abc$18544$new_n4732 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$new_n2822 $abc$18544$new_n4726 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4730 $abc$18544$new_n4728 $abc$18544$new_n2757 system_timer._zz_io_limit[1] $abc$18544$new_n4727 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4729 $abc$18544$new_n2722 $abc$18544$new_n2713 $abc$18544$new_n3969 $abc$18544$new_n4728 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[1] system_timer.system_timer_timerB_io_limit_driver[1] system_timer.timerBBridge_ticksEnable[1] $abc$18544$new_n4729 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n2717 system_timer.timerABridge_ticksEnable[1] system_timer.interruptCtrl_1.pendings[1] $abc$18544$new_n4721 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$new_n4730 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4717 system_timer.timerA.counter[1] $abc$18544$new_n2740 system_timer.system_timer_timerA_io_limit_driver[1] $abc$18544$new_n4732 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[1] $abc$18544$new_n3042 $abc$18544$new_n3963 system_uartCtrl.bridge_interruptCtrl_readIntEnable $abc$18544$new_n4733 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[1] $abc$18544$new_n2723 io_gpioA_write[1] $abc$18544$new_n4734 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4736 system_uartCtrl.bridge_read_streamBreaked_payload[2] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[2] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4740 $abc$18544$new_n4739 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4738 $abc$18544$new_n4736 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n4717 $abc$18544$new_n3969 $abc$18544$new_n2722 $abc$18544$new_n4737 +000 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[2] system_timer.system_timer_timerB_io_limit_driver[2] system_timer.timerA.counter[2] $abc$18544$new_n4738 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[2] $abc$18544$new_n2740 system_timer._zz_io_limit[2] $abc$18544$new_n2757 $abc$18544$new_n4739 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4741 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[2] $abc$18544$new_n2714 $abc$18544$new_n4740 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[2] $abc$18544$new_n2723 io_gpioA_write[2] $abc$18544$new_n4741 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3042 $abc$18544$new_n4742 +11 1 +.names $abc$18544$new_n4744 system_uartCtrl.bridge_read_streamBreaked_payload[3] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[3] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n4747 $abc$18544$new_n4746 $abc$18544$new_n4737 $abc$18544$new_n4745 $abc$18544$new_n4744 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[3] system_timer.system_timer_timerB_io_limit_driver[3] system_timer.timerA.counter[3] $abc$18544$new_n4745 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 system_timer.system_timer_timerA_io_limit_driver[3] $abc$18544$new_n2740 $abc$18544$new_n2757 system_timer._zz_io_limit[3] $abc$18544$new_n4746 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$new_n4748 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[3] $abc$18544$new_n4747 +0000 1 +0001 1 +0010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[3] $abc$18544$new_n2723 io_gpioA_write[3] $abc$18544$new_n4748 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4750 system_uartCtrl.bridge_read_streamBreaked_payload[4] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[4] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4753 $abc$18544$new_n4752 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4751 $abc$18544$new_n4750 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[4] system_timer.system_timer_timerB_io_limit_driver[4] system_timer.timerA.counter[4] $abc$18544$new_n4751 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[4] $abc$18544$new_n2740 system_timer._zz_io_limit[4] $abc$18544$new_n2757 $abc$18544$new_n4752 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4754 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[4] $abc$18544$new_n2714 $abc$18544$new_n4753 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[4] $abc$18544$new_n2723 io_gpioA_write[4] $abc$18544$new_n4754 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4756 system_uartCtrl.bridge_read_streamBreaked_payload[5] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[5] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4759 $abc$18544$new_n4758 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4757 $abc$18544$new_n4756 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[5] system_timer.system_timer_timerB_io_limit_driver[5] system_timer.timerA.counter[5] $abc$18544$new_n4757 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[5] $abc$18544$new_n2740 system_timer._zz_io_limit[5] $abc$18544$new_n2757 $abc$18544$new_n4758 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4760 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[5] $abc$18544$new_n2714 $abc$18544$new_n4759 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[5] $abc$18544$new_n2723 io_gpioA_write[5] $abc$18544$new_n4760 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4762 system_uartCtrl.bridge_read_streamBreaked_payload[6] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[6] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4765 $abc$18544$new_n4764 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4763 $abc$18544$new_n4762 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[6] system_timer.system_timer_timerB_io_limit_driver[6] system_timer.timerA.counter[6] $abc$18544$new_n4763 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[6] $abc$18544$new_n2740 system_timer._zz_io_limit[6] $abc$18544$new_n2757 $abc$18544$new_n4764 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4766 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[6] $abc$18544$new_n2714 $abc$18544$new_n4765 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[6] $abc$18544$new_n2723 io_gpioA_write[6] $abc$18544$new_n4766 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4768 system_uartCtrl.bridge_read_streamBreaked_payload[7] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[7] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4771 $abc$18544$new_n4770 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4769 $abc$18544$new_n4768 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[7] system_timer.system_timer_timerB_io_limit_driver[7] system_timer.timerA.counter[7] $abc$18544$new_n4769 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[7] $abc$18544$new_n2740 system_timer._zz_io_limit[7] $abc$18544$new_n2757 $abc$18544$new_n4770 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4772 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[7] $abc$18544$new_n2714 $abc$18544$new_n4771 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[7] $abc$18544$new_n2723 io_gpioA_write[7] $abc$18544$new_n4772 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names apb3Router_1.selIndex[1] apb3Router_1.selIndex[0] $abc$18544$new_n4774 $abc$18544$new_n4777 $abc$18544$new_n4779 apb3Router_1._zz_io_input_PRDATA[8] +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n4776 $abc$18544$new_n4737 $abc$18544$new_n4775 $abc$18544$new_n4774 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[8] system_timer.system_timer_timerB_io_limit_driver[8] system_timer.timerA.counter[8] $abc$18544$new_n4775 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[8] $abc$18544$new_n2740 system_timer._zz_io_limit[8] $abc$18544$new_n2757 $abc$18544$new_n4776 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4778 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[8] $abc$18544$new_n4777 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[8] $abc$18544$new_n2723 io_gpioA_write[8] $abc$18544$new_n4778 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3958 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$new_n3963 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid $abc$18544$new_n4779 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names apb3Router_1.selIndex[1] $abc$18544$new_n4781 $abc$18544$new_n4787 $abc$18544$new_n4737 $abc$18544$new_n4786 apb3Router_1._zz_io_input_PRDATA[9] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$18544$new_n4782 $abc$18544$new_n4784 $abc$18544$new_n3958 $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP system_uartCtrl.bridge_misc_breakDetected $abc$18544$new_n4781 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names system_uartCtrl.bridge_interruptCtrl_readIntEnable system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n4783 system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n4782 +1110 1 +.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3963 $abc$18544$new_n4783 +11 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4785 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[9] $abc$18544$new_n2714 $abc$18544$new_n4784 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[9] $abc$18544$new_n2723 io_gpioA_write[9] $abc$18544$new_n4785 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[9] system_timer.system_timer_timerB_io_limit_driver[9] system_timer.timerA.counter[9] $abc$18544$new_n4786 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[9] $abc$18544$new_n2740 system_timer._zz_io_limit[9] $abc$18544$new_n2757 $abc$18544$new_n4787 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4789 $abc$18544$new_n4792 $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid apb3Router_1._zz_io_input_PRDATA[15] +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names apb3Router_1.selIndex[1] $abc$18544$new_n4791 $abc$18544$new_n4737 $abc$18544$new_n4790 $abc$18544$new_n4789 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[15] system_timer.system_timer_timerB_io_limit_driver[15] system_timer.timerA.counter[15] $abc$18544$new_n4790 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[15] $abc$18544$new_n2740 system_timer._zz_io_limit[15] $abc$18544$new_n2757 $abc$18544$new_n4791 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4793 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[15] $abc$18544$new_n2714 $abc$18544$new_n4792 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[15] $abc$18544$new_n2723 io_gpioA_write[15] $abc$18544$new_n4793 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4795 $abc$18544$new_n4798 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[16] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[16] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4797 $abc$18544$new_n4796 $abc$18544$new_n4742 system_uartCtrl.uartCtrl_1.io_readBreak system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n4795 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +.names $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4796 +101 1 +110 1 +.names apb3Router_1.selIndex[1] system_timer.timerBBridge_clearsEnable $abc$18544$new_n2713 system_timer.timerABridge_clearsEnable $abc$18544$new_n2717 $abc$18544$new_n4797 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[16] $abc$18544$new_n2723 io_gpioA_write[16] $abc$18544$new_n4798 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4800 $abc$18544$new_n4801 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[17] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[17] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4800 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[17] $abc$18544$new_n2723 io_gpioA_write[17] $abc$18544$new_n4801 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4805 $abc$18544$new_n4783 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4803 apb3Router_1._zz_io_input_PRDATA[18] +0000 1 +0100 1 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4804 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[18] $abc$18544$new_n4803 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[18] $abc$18544$new_n2723 io_gpioA_write[18] $abc$18544$new_n4804 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$new_n3038 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n4805 +00000 1 +00001 1 +00011 1 +00110 1 +01010 1 +01100 1 +01101 1 +01111 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names $abc$18544$new_n4783 $abc$18544$new_n4810 $abc$18544$new_n4809 $abc$18544$new_n4807 apb3Router_1._zz_io_input_PRDATA[19] +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4808 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[19] $abc$18544$new_n2714 $abc$18544$new_n4807 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[19] $abc$18544$new_n2723 io_gpioA_write[19] $abc$18544$new_n4808 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3038 $abc$18544$new_n4809 +00000 1 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n4810 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n4783 $abc$18544$new_n4812 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4814 apb3Router_1._zz_io_input_PRDATA[20] +0000 1 +0100 1 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$new_n4813 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n4812 +00000 1 +00001 1 +00011 1 +00110 1 +01010 1 +01100 1 +01101 1 +01111 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n4809 $abc$18544$new_n4813 +00001 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names $abc$18544$new_n4815 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[20] $abc$18544$new_n4814 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[20] $abc$18544$new_n2723 io_gpioA_write[20] $abc$18544$new_n4815 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4817 apb3Router_1._zz_io_input_PRDATA[24] +0001 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4818 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[24] $abc$18544$new_n2714 $abc$18544$new_n4817 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[24] $abc$18544$new_n2723 io_gpioA_write[24] $abc$18544$new_n4818 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4820 $abc$18544$new_n4821 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[25] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[25] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] $abc$18544$new_n4820 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[25] $abc$18544$new_n2723 io_gpioA_write[25] $abc$18544$new_n4821 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$new_n4825 $abc$18544$new_n4823 apb3Router_1._zz_io_input_PRDATA[26] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4824 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[26] $abc$18544$new_n2714 $abc$18544$new_n4823 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[26] $abc$18544$new_n2723 io_gpioA_write[26] $abc$18544$new_n4824 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3073 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n4825 +000 1 +010 1 +011 1 +.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n4827 $abc$18544$new_n4828 apb3Router_1._zz_io_input_PRDATA[27] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n4825 $abc$18544$new_n4827 +001 1 +100 1 +101 1 +111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4829 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[27] $abc$18544$new_n2714 $abc$18544$new_n4828 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[27] $abc$18544$new_n2723 io_gpioA_write[27] $abc$18544$new_n4829 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4783 $abc$18544$new_n4831 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4832 apb3Router_1._zz_io_input_PRDATA[28] +0000 1 +0100 1 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n4827 $abc$18544$new_n4831 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$18544$new_n4833 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[28] $abc$18544$new_n4832 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[28] $abc$18544$new_n2723 io_gpioA_write[28] $abc$18544$new_n4833 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[0] system_ram._zz_ram_port0[0] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[0] +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[1] system_ram._zz_ram_port0[1] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[1] +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[8] system_mainBusArbiter.io_dBus_cmd_payload_address[8] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[9] system_mainBusArbiter.io_dBus_cmd_payload_address[9] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[10] system_mainBusArbiter.io_dBus_cmd_payload_address[10] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[11] system_mainBusArbiter.io_dBus_cmd_payload_address[11] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] +010 1 +011 1 +101 1 +111 1 +.names jtagBridge_1.jtag_tap_fsm_state[3] io_jtag_tms jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[0] +00000 1 +00001 1 +00100 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11111 1 +.names jtagBridge_1.jtag_tap_fsm_state[0] io_jtag_tms jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[1] +00001 1 +00011 1 +00101 1 +00111 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +11010 1 +11110 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] io_jtag_tms jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[2] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01111 1 +10001 1 +10100 1 +10101 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names jtagBridge_1.jtag_tap_fsm_state[0] io_jtag_tms jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[3] +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_5 system_cpu.HazardSimplePlugin_writeBackWrites_valid system_cpu._zz_1 +01 1 +10 1 +11 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[0] +10 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[1] +10 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[2] +10 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[3] +10 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[4] +10 1 +.names system_cpu._zz_5 $abc$18544$new_n3822 system_cpu.lastStageRegFileWrite_payload_data[0] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n4060 system_cpu.lastStageRegFileWrite_payload_data[1] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n2985 system_cpu.lastStageRegFileWrite_payload_data[2] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n2982 system_cpu.lastStageRegFileWrite_payload_data[3] +00 1 +.names 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$abc$18544$flatten\system_cpu.$0\writeBack_arbitration_isValid[0:0] +110 1 +.names $abc$18544$new_n4884 system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] $abc$18544$new_n4885 $abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names system_cpu.decode_to_execute_CSR_WRITE_OPCODE system_cpu.decode_to_execute_IS_CSR system_cpu.execute_CsrPlugin_csr_768 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$new_n4884 +11111 1 +.names $abc$18544$new_n3725 system_cpu.CsrPlugin_mstatus_MPIE system_cpu.CsrPlugin_mstatus_MIE $abc$18544$new_n3723 $abc$18544$new_n4885 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n4884 $abc$18544$new_n4000 $abc$18544$new_n4887 $abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names $abc$18544$new_n3723 $abc$18544$new_n3725 system_cpu.CsrPlugin_mstatus_MIE system_cpu.CsrPlugin_mstatus_MPIE $abc$18544$new_n4887 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system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] system_cpu.decode_INSTRUCTION_ANTICIPATED[23] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[23] systemDebugger_1._zz_io_mem_cmd_payload_address[55] $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][23] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] system_cpu.decode_INSTRUCTION_ANTICIPATED[24] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[24] system_cpu.when_DebugPlugin_l284_1 $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][24] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n4925 $abc$18544$new_n4008 $abc$18544$new_n3317 $abc$18544$new_n3852 $abc$18544$flatten\system_cpu.$0\DebugPlugin_haltIt[0:0] +0000 1 +0001 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l285_1 system_cpu.DebugPlugin_haltIt system_cpu.when_DebugPlugin_l285 $abc$18544$new_n4925 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n3852 system_cpu.DebugPlugin_haltedByBreak $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l285_1 $abc$18544$flatten\system_cpu.$0\DebugPlugin_haltedByBreak[0:0] +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3016 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3954[0] +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] $abc$18544$new_n4929 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] $abc$18544$new_n3016 $abc$18544$auto$rtlil.cc:2582:Mux$3954[1] +0011 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3016 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$new_n4929 +110 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] $abc$18544$new_n4929 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] $abc$18544$new_n3016 $abc$18544$auto$rtlil.cc:2582:Mux$3954[2] +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PENABLE $abc$18544$flatten\system_apbBridge.$0\state[0:0] +10 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4937 $abc$18544$new_n4940 $abc$18544$new_n4737 $abc$18544$new_n4939 $abc$18544$auto$rtlil.cc:2582:Mux$3626[10] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$18544$new_n4938 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[10] $abc$18544$new_n4937 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[10] $abc$18544$new_n2723 io_gpioA_write[10] $abc$18544$new_n4938 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[10] system_timer.system_timer_timerB_io_limit_driver[10] system_timer.timerA.counter[10] $abc$18544$new_n4939 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[10] $abc$18544$new_n2740 system_timer._zz_io_limit[10] $abc$18544$new_n2757 $abc$18544$new_n4940 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4942 $abc$18544$new_n4945 $abc$18544$new_n4737 $abc$18544$new_n4944 $abc$18544$auto$rtlil.cc:2582:Mux$3626[11] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$18544$new_n4943 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[11] $abc$18544$new_n4942 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[11] $abc$18544$new_n2723 io_gpioA_write[11] $abc$18544$new_n4943 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[11] system_timer.system_timer_timerB_io_limit_driver[11] system_timer.timerA.counter[11] $abc$18544$new_n4944 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[11] $abc$18544$new_n2740 system_timer._zz_io_limit[11] $abc$18544$new_n2757 $abc$18544$new_n4945 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4947 $abc$18544$new_n4950 $abc$18544$new_n4737 $abc$18544$new_n4949 $abc$18544$auto$rtlil.cc:2582:Mux$3626[12] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$18544$new_n4948 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[12] $abc$18544$new_n4947 +0000 1 +0001 1 +0010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[12] $abc$18544$new_n2723 io_gpioA_write[12] $abc$18544$new_n4948 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[12] system_timer.system_timer_timerB_io_limit_driver[12] system_timer.timerA.counter[12] $abc$18544$new_n4949 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 system_timer.system_timer_timerA_io_limit_driver[12] $abc$18544$new_n2740 $abc$18544$new_n2757 system_timer._zz_io_limit[12] $abc$18544$new_n4950 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$new_n4952 $abc$18544$new_n4955 $abc$18544$new_n4737 $abc$18544$new_n4954 $abc$18544$auto$rtlil.cc:2582:Mux$3626[13] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$18544$new_n4953 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[13] $abc$18544$new_n4952 +0000 1 +0001 1 +0010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[13] $abc$18544$new_n2723 io_gpioA_write[13] $abc$18544$new_n4953 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[13] system_timer.system_timer_timerB_io_limit_driver[13] system_timer.timerA.counter[13] $abc$18544$new_n4954 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 system_timer.system_timer_timerA_io_limit_driver[13] $abc$18544$new_n2740 $abc$18544$new_n2757 system_timer._zz_io_limit[13] $abc$18544$new_n4955 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4957 $abc$18544$new_n4960 $abc$18544$new_n4737 $abc$18544$new_n4959 $abc$18544$auto$rtlil.cc:2582:Mux$3626[14] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$18544$new_n4958 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[14] $abc$18544$new_n4957 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[14] $abc$18544$new_n2723 io_gpioA_write[14] $abc$18544$new_n4958 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[14] system_timer.system_timer_timerB_io_limit_driver[14] system_timer.timerA.counter[14] $abc$18544$new_n4959 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[14] $abc$18544$new_n2740 system_timer._zz_io_limit[14] $abc$18544$new_n2757 $abc$18544$new_n4960 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4962 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[21] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[21] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[21] $abc$18544$new_n2723 io_gpioA_write[21] $abc$18544$new_n4962 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4964 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[22] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[22] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[22] $abc$18544$new_n2723 io_gpioA_write[22] $abc$18544$new_n4964 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4966 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[23] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[23] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[23] $abc$18544$new_n2723 io_gpioA_write[23] $abc$18544$new_n4966 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4968 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[29] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[29] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[29] $abc$18544$new_n2723 io_gpioA_write[29] $abc$18544$new_n4968 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4970 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[30] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[30] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[30] $abc$18544$new_n2723 io_gpioA_write[30] $abc$18544$new_n4970 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4972 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[31] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[31] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[31] io_gpioA_write[31] $abc$18544$new_n2723 $abc$18544$new_n4972 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][1] +00 1 +11 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_tick system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][2] +0000 1 +1001 1 +1010 1 +1011 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[3] system_uartCtrl.uartCtrl_1.clockDivider_tick system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][3] +00000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[4] system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] system_uartCtrl.uartCtrl_1.clockDivider_counter[3] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][4] +00000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][5] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][6] +0010 1 +1000 1 +1001 1 +1011 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[7] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][7] +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4981 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][8] +00 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[8] $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] system_uartCtrl.uartCtrl_1.clockDivider_counter[7] $abc$18544$new_n4981 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[9] $abc$18544$new_n4683 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][9] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[10] $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][10] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[10] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][11] +0010 1 +1000 1 +1001 1 +1011 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][12] +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4987 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][13] +00 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[13] $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] $abc$18544$new_n4987 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[14] $abc$18544$new_n4989 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][14] +010 1 +100 1 +.names $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_counter[13] $abc$18544$new_n4989 +10000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[15] $abc$18544$new_n4989 system_uartCtrl.uartCtrl_1.clockDivider_counter[14] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][15] +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[16] $abc$18544$new_n4681 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][16] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[17] $abc$18544$new_n4680 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][17] +010 1 +100 1 +.names $abc$18544$new_n4679 system_uartCtrl.uartCtrl_1.clockDivider_counter[18] system_uartCtrl.uartCtrl_1.clockDivider_counter[19] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][18] +010 1 +011 1 +101 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[19] $abc$18544$new_n4678 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][19] +10 1 +.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg $abc$18544$new_n3016 system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[0] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[1] +011 1 +100 1 +101 1 +110 1 +.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[2] +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_uartCtrl.uartCtrl_1.tx.stateMachine_parity $abc$18544$new_n3016 $abc$18544$new_n4700 $abc$18544$new_n3928 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\stateMachine_parity[0:0] +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names system_uartCtrl.uartCtrl_1.rx.sampler_tick $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][0] +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][1] +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][2] +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n3972 system_timer.interruptCtrl_1.pendings[0] $abc$18544$new_n4721 $abc$18544$new_n2709 system_uartCtrl.when_BusSlaveFactory_l347 $abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][0] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3967 system_timer.interruptCtrl_1.pendings[1] $abc$18544$new_n4721 $abc$18544$new_n2709 system_uartCtrl.when_BusSlaveFactory_l347_1 $abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][1] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[1] +01 1 +10 1 +.names system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[2] +011 1 +100 1 +101 1 +110 1 +.names system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.prescaler_1.counter[4] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[5] +01 1 +10 1 +.names system_timer.prescaler_1.counter[4] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $abc$18544$new_n5009 +11111 1 +.names system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[6] +011 1 +100 1 +101 1 +110 1 +.names system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[9] +01 1 +10 1 +.names system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $abc$18544$new_n5014 +11111 1 +.names system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[10] +011 1 +100 1 +101 1 +110 1 +.names system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.prescaler_1.counter[12] system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[13] +01 1 +10 1 +.names system_timer.prescaler_1.counter[12] system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $abc$18544$new_n5019 +11111 1 +.names system_timer.prescaler_1.counter[14] system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[14] +011 1 +100 1 +101 1 +110 1 +.names system_timer.prescaler_1.counter[15] system_timer.prescaler_1.counter[14] system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.X[0] +0 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[0] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][0] +0 1 +.names $abc$18544$new_n2792 system_timer.prescaler_1.counter[15] system_timer._zz_io_limit[15] system_timer.prescaler_1.counter[1] system_timer._zz_io_limit[1] $abc$18544$new_n5024 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5024 system_timer._zz_io_limit[2] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[5] system_timer._zz_io_limit[5] $abc$18544$new_n5025 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n2786 $abc$18544$new_n5025 system_timer.prescaler_1.counter[11] system_timer._zz_io_limit[11] $abc$18544$new_n5026 +1100 1 +1111 1 +.names $abc$18544$new_n2803 system_timer.timerA.counter[15] system_timer.system_timer_timerA_io_limit_driver[15] system_timer.timerA.counter[0] system_timer.system_timer_timerA_io_limit_driver[0] $abc$18544$new_n5027 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5027 system_timer.timerA.counter[3] system_timer.system_timer_timerA_io_limit_driver[3] system_timer.timerA.counter[4] system_timer.system_timer_timerA_io_limit_driver[4] $abc$18544$new_n5028 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n2796 $abc$18544$new_n5028 system_timer.timerA.counter[14] system_timer.system_timer_timerA_io_limit_driver[14] $abc$18544$new_n5029 +1100 1 +1111 1 +.names $abc$18544$new_n2845 system_timer.timerB.counter[15] system_timer.system_timer_timerB_io_limit_driver[15] system_timer.timerB.counter[0] system_timer.system_timer_timerB_io_limit_driver[0] $abc$18544$new_n5030 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5030 system_timer.timerB.counter[3] system_timer.system_timer_timerB_io_limit_driver[3] system_timer.timerB.counter[4] system_timer.system_timer_timerB_io_limit_driver[4] $abc$18544$new_n5031 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n2837 $abc$18544$new_n5031 system_timer.timerB.counter[14] system_timer.system_timer_timerB_io_limit_driver[14] $abc$18544$new_n5032 +1100 1 +1111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] $abc$18544$new_n5033 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n5033 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n5034 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5034 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n5035 +100 1 +111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] $abc$18544$new_n5036 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n5036 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n5037 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5037 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n5038 +100 1 +111 1 +.names $abc$18544$new_n3288 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n5039 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$18544$new_n5039 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$new_n5040 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names $abc$18544$new_n5040 $abc$18544$new_n5047 $abc$18544$new_n5044 $abc$18544$new_n3272 $abc$18544$new_n5041 +1000 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_valid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n5042 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5042 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$18544$new_n5043 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5043 system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$new_n5044 +100 1 +111 1 +.names system_cpu.execute_arbitration_isValid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n5045 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_REGFILE_WRITE_VALID system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$new_n5046 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5045 $abc$18544$new_n5046 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n5047 +1100 1 +1111 1 +.names $abc$18544$new_n3300 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n5048 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$18544$new_n5048 $abc$18544$new_n3299 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$18544$new_n5052 $abc$18544$new_n5049 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$18544$new_n3306 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n5049 $abc$18544$new_n3291 $abc$18544$new_n5050 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$new_n3304 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$new_n5051 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5051 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n5052 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2[28] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n5053 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$18544$new_n3465 $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n5053 $abc$18544$new_n3485 $abc$18544$new_n5054 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$18544$new_n5054 $abc$18544$new_n3486 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] $abc$18544$new_n3255 $abc$18544$auto$rtlil.cc:2693:MuxGate$15976 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[12] $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2[12] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n5056 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$18544$new_n3466 $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n5056 $abc$18544$new_n3589 $abc$18544$new_n5057 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$18544$new_n3255 $abc$18544$new_n3592 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] $abc$18544$new_n5057 $abc$18544$new_n3590 $abc$18544$auto$rtlil.cc:2693:MuxGate$16008 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[2] jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment jtagBridge_1.jtag_idcodeArea_ctrl_tdo $abc$18544$new_n5059 +00001 1 +00011 1 +00101 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n5059 jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n5060 +1100 1 +1111 1 +.names $abc$18544$new_n2864 $abc$18544$new_n3827 $abc$18544$new_n5060 jtagBridge_1.jtag_tap_tdoIr jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment jtagBridge_1.jtag_tap_tdoUnbufferd +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14840 Q=system_cpu.DebugPlugin_busReadDataReg[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14838 Q=system_cpu.DebugPlugin_busReadDataReg[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14836 Q=system_cpu.DebugPlugin_busReadDataReg[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14834 Q=jtagBridge_1.io_remote_rsp_payload_data[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14832 Q=jtagBridge_1.io_remote_rsp_payload_data[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14830 Q=jtagBridge_1.io_remote_rsp_payload_data[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14828 Q=jtagBridge_1.io_remote_rsp_payload_data[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14826 Q=jtagBridge_1.io_remote_rsp_payload_data[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14824 Q=jtagBridge_1.io_remote_rsp_payload_data[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14822 Q=jtagBridge_1.io_remote_rsp_payload_data[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14820 Q=jtagBridge_1.io_remote_rsp_payload_data[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14818 Q=jtagBridge_1.io_remote_rsp_payload_data[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14816 Q=jtagBridge_1.io_remote_rsp_payload_data[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14814 Q=jtagBridge_1.io_remote_rsp_payload_data[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14812 Q=jtagBridge_1.io_remote_rsp_payload_data[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14810 Q=jtagBridge_1.io_remote_rsp_payload_data[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14808 Q=jtagBridge_1.io_remote_rsp_payload_data[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14806 Q=jtagBridge_1.io_remote_rsp_payload_data[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14804 Q=jtagBridge_1.io_remote_rsp_payload_data[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14802 Q=jtagBridge_1.io_remote_rsp_payload_data[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14800 Q=jtagBridge_1.io_remote_rsp_payload_data[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14798 Q=jtagBridge_1.io_remote_rsp_payload_data[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14796 Q=jtagBridge_1.io_remote_rsp_payload_data[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14794 Q=jtagBridge_1.io_remote_rsp_payload_data[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14792 Q=jtagBridge_1.io_remote_rsp_payload_data[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14790 Q=jtagBridge_1.io_remote_rsp_payload_data[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14788 Q=jtagBridge_1.io_remote_rsp_payload_data[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14786 Q=jtagBridge_1.io_remote_rsp_payload_data[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14784 Q=jtagBridge_1.io_remote_rsp_payload_data[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16774 Q=jtagBridge_1.io_remote_rsp_payload_data[31] +.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\sampler_value[0:0] Q=system_uartCtrl.uartCtrl_1.rx.sampler_value S=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.clockDivider_tickReg Q=system_uartCtrl.uartCtrl_1.rx.sampler_tick R=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16538 Q=system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 S=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14782 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14780 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14778 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14776 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14774 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14772 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[5] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16536 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[6] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3924 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=io_uart_rxd Q=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_0 R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16564 Q=system_uartCtrl.bridge_interruptCtrl_readIntEnable R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16566 Q=system_uartCtrl.bridge_interruptCtrl_writeIntEnable R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16568 Q=system_timer.timerB.inhibitFull R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=system_uartCtrl.uartCtrl_1.io_readBreak Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_readBreak_regNext +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14770 Q=jtagBridge_1.jtag_readArea_ctrl_tdo +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14768 Q=jtagBridge_1.jtag_readArea_full_shifter[2] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14766 Q=jtagBridge_1.jtag_readArea_full_shifter[3] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14764 Q=jtagBridge_1.jtag_readArea_full_shifter[4] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14762 Q=jtagBridge_1.jtag_readArea_full_shifter[5] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14760 Q=jtagBridge_1.jtag_readArea_full_shifter[6] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14758 Q=jtagBridge_1.jtag_readArea_full_shifter[7] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14756 Q=jtagBridge_1.jtag_readArea_full_shifter[8] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14754 Q=jtagBridge_1.jtag_readArea_full_shifter[9] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14752 Q=jtagBridge_1.jtag_readArea_full_shifter[10] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14750 Q=jtagBridge_1.jtag_readArea_full_shifter[11] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14748 Q=jtagBridge_1.jtag_readArea_full_shifter[12] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14746 Q=jtagBridge_1.jtag_readArea_full_shifter[13] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14744 Q=jtagBridge_1.jtag_readArea_full_shifter[14] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14742 Q=jtagBridge_1.jtag_readArea_full_shifter[15] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14740 Q=jtagBridge_1.jtag_readArea_full_shifter[16] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14738 Q=jtagBridge_1.jtag_readArea_full_shifter[17] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14736 Q=jtagBridge_1.jtag_readArea_full_shifter[18] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14734 Q=jtagBridge_1.jtag_readArea_full_shifter[19] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14732 Q=jtagBridge_1.jtag_readArea_full_shifter[20] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14730 Q=jtagBridge_1.jtag_readArea_full_shifter[21] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14728 Q=jtagBridge_1.jtag_readArea_full_shifter[22] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14726 Q=jtagBridge_1.jtag_readArea_full_shifter[23] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14724 Q=jtagBridge_1.jtag_readArea_full_shifter[24] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14722 Q=jtagBridge_1.jtag_readArea_full_shifter[25] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14720 Q=jtagBridge_1.jtag_readArea_full_shifter[26] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14718 Q=jtagBridge_1.jtag_readArea_full_shifter[27] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14716 Q=jtagBridge_1.jtag_readArea_full_shifter[28] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14714 Q=jtagBridge_1.jtag_readArea_full_shifter[29] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14712 Q=jtagBridge_1.jtag_readArea_full_shifter[30] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14710 Q=jtagBridge_1.jtag_readArea_full_shifter[31] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14708 Q=jtagBridge_1.jtag_readArea_full_shifter[32] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16784 Q=jtagBridge_1.jtag_readArea_full_shifter[33] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16782 Q=jtagBridge_1.jtag_readArea_full_shifter[1] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16562 Q=system_uartCtrl.bridge_misc_readError R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.$0\bridge_misc_breakDetected[0:0] Q=system_uartCtrl.bridge_misc_breakDetected R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.$0\bridge_misc_doBreak[0:0] Q=system_uartCtrl.bridge_misc_doBreak R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][0] Q=system_timer.interruptCtrl_1.pendings[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][1] Q=system_timer.interruptCtrl_1.pendings[1] R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14706 Q=system_timer.timerB.counter[0] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14704 Q=system_timer.timerB.counter[1] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14702 Q=system_timer.timerB.counter[2] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14700 Q=system_timer.timerB.counter[3] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14698 Q=system_timer.timerB.counter[4] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14696 Q=system_timer.timerB.counter[5] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14694 Q=system_timer.timerB.counter[6] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14692 Q=system_timer.timerB.counter[7] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14690 Q=system_timer.timerB.counter[8] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14688 Q=system_timer.timerB.counter[9] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14686 Q=system_timer.timerB.counter[10] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14684 Q=system_timer.timerB.counter[11] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14682 Q=system_timer.timerB.counter[12] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14680 Q=system_timer.timerB.counter[13] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14678 Q=system_timer.timerB.counter[14] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16754 Q=system_timer.timerB.counter[15] R=system_timer.timerB.io_clear +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16570 Q=system_timer.timerA.inhibitFull R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.X[0] Q=system_timer.prescaler_1.counter[0] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[1] Q=system_timer.prescaler_1.counter[1] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[2] Q=system_timer.prescaler_1.counter[2] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[3] Q=system_timer.prescaler_1.counter[3] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[4] Q=system_timer.prescaler_1.counter[4] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[5] Q=system_timer.prescaler_1.counter[5] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[6] Q=system_timer.prescaler_1.counter[6] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[7] Q=system_timer.prescaler_1.counter[7] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[8] Q=system_timer.prescaler_1.counter[8] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[9] Q=system_timer.prescaler_1.counter[9] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[10] Q=system_timer.prescaler_1.counter[10] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[11] Q=system_timer.prescaler_1.counter[11] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[12] Q=system_timer.prescaler_1.counter[12] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[13] Q=system_timer.prescaler_1.counter[13] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[14] Q=system_timer.prescaler_1.counter[14] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[15] Q=system_timer.prescaler_1.counter[15] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14676 Q=system_timer.interruptCtrl_1.io_masks[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16572 Q=system_timer.interruptCtrl_1.io_masks[1] R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14674 Q=system_timer.timerA.counter[0] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14672 Q=system_timer.timerA.counter[1] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14670 Q=system_timer.timerA.counter[2] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14668 Q=system_timer.timerA.counter[3] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14666 Q=system_timer.timerA.counter[4] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14664 Q=system_timer.timerA.counter[5] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14662 Q=system_timer.timerA.counter[6] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14660 Q=system_timer.timerA.counter[7] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14658 Q=system_timer.timerA.counter[8] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14656 Q=system_timer.timerA.counter[9] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14654 Q=system_timer.timerA.counter[10] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14652 Q=system_timer.timerA.counter[11] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14650 Q=system_timer.timerA.counter[12] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14648 Q=system_timer.timerA.counter[13] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14646 Q=system_timer.timerA.counter[14] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16752 Q=system_timer.timerA.counter[15] R=system_timer.timerA.io_clear +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16700 Q=system_cpu.CsrPlugin_interrupt_code[2] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][15] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][16] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][17] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][18] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][19] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][20] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][21] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][22] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][23] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][24] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14644 Q=system_timer._zz_io_limit[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14642 Q=system_timer._zz_io_limit[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14640 Q=system_timer._zz_io_limit[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14638 Q=system_timer._zz_io_limit[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14636 Q=system_timer._zz_io_limit[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14634 Q=system_timer._zz_io_limit[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14632 Q=system_timer._zz_io_limit[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14630 Q=system_timer._zz_io_limit[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14628 Q=system_timer._zz_io_limit[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14626 Q=system_timer._zz_io_limit[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14624 Q=system_timer._zz_io_limit[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14622 Q=system_timer._zz_io_limit[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14620 Q=system_timer._zz_io_limit[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14618 Q=system_timer._zz_io_limit[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14616 Q=system_timer._zz_io_limit[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16586 Q=system_timer._zz_io_limit[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14614 Q=system_timer.system_timer_timerA_io_limit_driver[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14612 Q=system_timer.system_timer_timerA_io_limit_driver[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14610 Q=system_timer.system_timer_timerA_io_limit_driver[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14608 Q=system_timer.system_timer_timerA_io_limit_driver[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14606 Q=system_timer.system_timer_timerA_io_limit_driver[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14604 Q=system_timer.system_timer_timerA_io_limit_driver[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14602 Q=system_timer.system_timer_timerA_io_limit_driver[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14600 Q=system_timer.system_timer_timerA_io_limit_driver[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14598 Q=system_timer.system_timer_timerA_io_limit_driver[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14596 Q=system_timer.system_timer_timerA_io_limit_driver[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14594 Q=system_timer.system_timer_timerA_io_limit_driver[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14592 Q=system_timer.system_timer_timerA_io_limit_driver[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14590 Q=system_timer.system_timer_timerA_io_limit_driver[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14588 Q=system_timer.system_timer_timerA_io_limit_driver[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14586 Q=system_timer.system_timer_timerA_io_limit_driver[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16584 Q=system_timer.system_timer_timerA_io_limit_driver[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14584 Q=system_timer.system_timer_timerB_io_limit_driver[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14582 Q=system_timer.system_timer_timerB_io_limit_driver[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14580 Q=system_timer.system_timer_timerB_io_limit_driver[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14578 Q=system_timer.system_timer_timerB_io_limit_driver[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14576 Q=system_timer.system_timer_timerB_io_limit_driver[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14574 Q=system_timer.system_timer_timerB_io_limit_driver[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14572 Q=system_timer.system_timer_timerB_io_limit_driver[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14570 Q=system_timer.system_timer_timerB_io_limit_driver[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14568 Q=system_timer.system_timer_timerB_io_limit_driver[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14566 Q=system_timer.system_timer_timerB_io_limit_driver[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14564 Q=system_timer.system_timer_timerB_io_limit_driver[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14562 Q=system_timer.system_timer_timerB_io_limit_driver[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14560 Q=system_timer.system_timer_timerB_io_limit_driver[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14558 Q=system_timer.system_timer_timerB_io_limit_driver[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14556 Q=system_timer.system_timer_timerB_io_limit_driver[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16582 Q=system_timer.system_timer_timerB_io_limit_driver[15] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14554 Q=system_timer.timerABridge_ticksEnable[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16580 Q=system_timer.timerABridge_ticksEnable[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16578 Q=system_timer.timerABridge_clearsEnable R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14552 Q=system_timer.timerBBridge_ticksEnable[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16576 Q=system_timer.timerBBridge_ticksEnable[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16574 Q=system_timer.timerBBridge_clearsEnable R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=apb3Router_1._zz_selIndex Q=apb3Router_1.selIndex[0] +.subckt dff C=io_mainClk D=apb3Router_1._zz_selIndex_1 Q=apb3Router_1.selIndex[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16516 Q=system_cpu.CsrPlugin_mcause_exceptionCode[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16760 Q=system_cpu.CsrPlugin_mcause_exceptionCode[3] +.subckt dffr C=io_mainClk D=toplevel_system_cpu_debug_bus_cmd_fire Q=jtagBridge_1.io_remote_rsp_fire R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dff C=io_mainClk D=system_cpu.DebugPlugin_resetIt_regNext Q=toplevel_system_cpu_debug_resetOut_regNext +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16514 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16512 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16532 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16530 Q=system_mainBusArbiter.io_dBus_cmd_payload_wr +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16510 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16508 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16506 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16504 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16502 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16500 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16498 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16496 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16494 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16492 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16490 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16488 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16486 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16484 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16482 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16480 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16478 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16476 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16474 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16472 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16470 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16468 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16466 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16464 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16462 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16460 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16458 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16456 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16454 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16452 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16450 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16528 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16448 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16446 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16444 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16442 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16440 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16438 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16436 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16434 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16432 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16430 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16428 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16426 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16424 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16422 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16420 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16418 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16416 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16414 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16412 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16410 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16408 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16406 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16404 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16402 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16400 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16398 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16396 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16394 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16392 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16390 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16388 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16526 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16386 Q=system_mainBusArbiter.io_dBus_cmd_payload_size[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16524 Q=system_mainBusArbiter.io_dBus_cmd_payload_size[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16522 Q=system_mainBusDecoder_logic_rspSourceId +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16520 Q=system_mainBusArbiter.io_dBus_cmd_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_mainBusDecoder_logic_noHit Q=system_mainBusDecoder_logic_rspNoHit R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=resetCtrl_mainClkResetUnbuffered Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt sdffs C=io_mainClk D=resetCtrl_mainClkResetUnbuffered Q=apb3Router_1.resetCtrl_systemReset S=toplevel_system_cpu_debug_resetOut_regNext +.subckt dff C=io_mainClk D=io_asyncReset_buffercc.buffers_0 Q=io_asyncReset_buffercc.buffers_1 +.subckt dff C=io_mainClk D=io_asyncReset Q=io_asyncReset_buffercc.buffers_0 +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16384 Q=io_gpioA_writeEnable[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16382 Q=io_gpioA_writeEnable[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16380 Q=io_gpioA_writeEnable[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16378 Q=io_gpioA_writeEnable[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16376 Q=io_gpioA_writeEnable[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16374 Q=io_gpioA_writeEnable[5] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16372 Q=io_gpioA_writeEnable[6] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16370 Q=io_gpioA_writeEnable[7] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16368 Q=io_gpioA_writeEnable[8] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16366 Q=io_gpioA_writeEnable[9] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16364 Q=io_gpioA_writeEnable[10] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16362 Q=io_gpioA_writeEnable[11] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16360 Q=io_gpioA_writeEnable[12] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16358 Q=io_gpioA_writeEnable[13] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16356 Q=io_gpioA_writeEnable[14] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16354 Q=io_gpioA_writeEnable[15] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16352 Q=io_gpioA_writeEnable[16] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16350 Q=io_gpioA_writeEnable[17] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16348 Q=io_gpioA_writeEnable[18] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16346 Q=io_gpioA_writeEnable[19] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16344 Q=io_gpioA_writeEnable[20] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16342 Q=io_gpioA_writeEnable[21] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16340 Q=io_gpioA_writeEnable[22] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16338 Q=io_gpioA_writeEnable[23] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16336 Q=io_gpioA_writeEnable[24] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16334 Q=io_gpioA_writeEnable[25] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16332 Q=io_gpioA_writeEnable[26] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16330 Q=io_gpioA_writeEnable[27] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16328 Q=io_gpioA_writeEnable[28] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16326 Q=io_gpioA_writeEnable[29] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16324 Q=io_gpioA_writeEnable[30] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16590 Q=io_gpioA_writeEnable[31] R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16322 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16318 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16314 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16310 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16306 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16302 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16788 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16294 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16292 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16290 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16288 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16286 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16284 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16282 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16280 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16278 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16276 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16274 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16272 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16270 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16268 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16266 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16264 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16262 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16260 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16258 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16256 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16254 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16252 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16250 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16248 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16246 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16244 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16242 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16240 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16238 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16596 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16236 Q=resetCtrl_systemClkResetCounter[0] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16234 Q=resetCtrl_systemClkResetCounter[1] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16232 Q=resetCtrl_systemClkResetCounter[2] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16230 Q=resetCtrl_systemClkResetCounter[3] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16228 Q=resetCtrl_systemClkResetCounter[4] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16598 Q=resetCtrl_systemClkResetCounter[5] R=io_asyncReset_buffercc.buffers_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16630 Q=system_cpu.execute_CsrPlugin_csr_772 +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_interrupt_valid[0:0] Q=system_cpu.CsrPlugin_interrupt_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$true Q=system_cpu.IBusSimplePlugin_fetchPc_booted R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\writeBack_arbitration_isValid[0:0] Q=system_cpu.lastStageIsFiring R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16624 Q=system_cpu.memory_arbitration_isValid R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16628 Q=system_cpu.execute_CsrPlugin_csr_834 +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16626 Q=system_cpu.execute_arbitration_isValid R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[21] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[21] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[22] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[22] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[23] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[23] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[29] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[29] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[30] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[30] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[31] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[31] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[0] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[0] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[1] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[1] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[2] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[2] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[3] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[3] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[4] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[4] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[5] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[5] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[6] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[6] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[7] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[7] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[8] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[8] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[9] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[9] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[15] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[15] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[16] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[16] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[17] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[17] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[18] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[18] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[19] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[19] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[20] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[20] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[24] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[24] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[25] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[25] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[26] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[26] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[27] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[27] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[28] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16226 Q=apb3Router_1.io_input_PADDR[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16224 Q=apb3Router_1.io_input_PADDR[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16222 Q=apb3Router_1.io_input_PADDR[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16220 Q=apb3Router_1.io_input_PADDR[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16218 Q=apb3Router_1.io_input_PADDR[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16216 Q=apb3Router_1.io_input_PADDR[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16206 Q=apb3Router_1.io_input_PADDR[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16204 Q=apb3Router_1.io_input_PADDR[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16202 Q=apb3Router_1.io_input_PADDR[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16200 Q=apb3Router_1.io_input_PADDR[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16198 Q=apb3Router_1.io_input_PADDR[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16196 Q=apb3Router_1.io_input_PADDR[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16194 Q=apb3Router_1.io_input_PADDR[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16192 Q=apb3Router_1.io_input_PADDR[19] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16168 Q=system_cpu.IBusSimplePlugin_injector_port_state[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16166 Q=system_cpu.IBusSimplePlugin_injector_port_state[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16600 Q=system_cpu.IBusSimplePlugin_injector_port_state[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16602 Q=system_cpu.execute_LightShifterPlugin_isActive R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16604 Q=system_cpu.CsrPlugin_pipelineLiberator_done R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_valid Q=system_cpu.HazardSimplePlugin_writeBackBuffer_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16606 Q=system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 R=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPP[1:0][0] Q=system_cpu.CsrPlugin_mstatus_MPP[0] S=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPP[1:0][1] Q=system_cpu.CsrPlugin_mstatus_MPP[1] S=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16616 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_isPipBusy[0:0] Q=system_cpu.DebugPlugin_isPipBusy +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16164 Q=jtagBridge_1.jtag_tap_tdoIr +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16160 Q=jtagBridge_1.jtag_tap_instructionShift[1] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16156 Q=jtagBridge_1.jtag_tap_instructionShift[2] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16778 Q=jtagBridge_1.jtag_tap_instructionShift[3] +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[0] Q=system_cpu.IBusSimplePlugin_pending_value[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[1] Q=system_cpu.IBusSimplePlugin_pending_value[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[2] Q=system_cpu.IBusSimplePlugin_pending_value[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16152 Q=system_cpu.DebugPlugin_busReadDataReg[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16772 Q=system_cpu.DebugPlugin_busReadDataReg[1] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[7] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[8] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[9] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[10] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[11] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[12] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[12] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[13] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[13] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[14] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[14] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[28] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[28] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[29] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16686 Q=system_cpu.decode_to_execute_CSR_WRITE_OPCODE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16148 Q=system_cpu.CsrPlugin_mepc[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16146 Q=system_cpu.CsrPlugin_mepc[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16144 Q=system_cpu.CsrPlugin_mepc[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16142 Q=system_cpu.CsrPlugin_mepc[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16140 Q=system_cpu.CsrPlugin_mepc[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16138 Q=system_cpu.CsrPlugin_mepc[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16136 Q=system_cpu.CsrPlugin_mepc[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16134 Q=system_cpu.CsrPlugin_mepc[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16132 Q=system_cpu.CsrPlugin_mepc[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16130 Q=system_cpu.CsrPlugin_mepc[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16128 Q=system_cpu.CsrPlugin_mepc[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16126 Q=system_cpu.CsrPlugin_mepc[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16124 Q=system_cpu.CsrPlugin_mepc[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16122 Q=system_cpu.CsrPlugin_mepc[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16120 Q=system_cpu.CsrPlugin_mepc[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16118 Q=system_cpu.CsrPlugin_mepc[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16116 Q=system_cpu.CsrPlugin_mepc[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16114 Q=system_cpu.CsrPlugin_mepc[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16112 Q=system_cpu.CsrPlugin_mepc[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16110 Q=system_cpu.CsrPlugin_mepc[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16108 Q=system_cpu.CsrPlugin_mepc[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16106 Q=system_cpu.CsrPlugin_mepc[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16104 Q=system_cpu.CsrPlugin_mepc[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16102 Q=system_cpu.CsrPlugin_mepc[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16100 Q=system_cpu.CsrPlugin_mepc[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16098 Q=system_cpu.CsrPlugin_mepc[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16096 Q=system_cpu.CsrPlugin_mepc[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16094 Q=system_cpu.CsrPlugin_mepc[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16092 Q=system_cpu.CsrPlugin_mepc[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16768 Q=system_cpu.CsrPlugin_mepc[31] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16622 Q=system_cpu.IBusSimplePlugin_fetchPc_inc R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16696 Q=system_cpu.CsrPlugin_interrupt_code[3] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16608 Q=system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16610 Q=system_cpu.CsrPlugin_mie_MSIE R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16090 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16088 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16086 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16084 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[5] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16082 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[6] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16080 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[7] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16078 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[8] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16076 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[9] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16074 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[10] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16072 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[11] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16070 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[12] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16068 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[13] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16066 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[14] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16064 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[15] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16062 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[16] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16060 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[17] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16058 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[18] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16056 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[19] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16054 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[20] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16052 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[21] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16050 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[22] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16048 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[23] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16046 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[24] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16044 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[25] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16042 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[26] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16040 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[27] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16038 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[28] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16036 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[29] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16034 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[30] R=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16758 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[31] S=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16634 Q=system_cpu.execute_CsrPlugin_csr_768 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16632 Q=system_cpu.execute_CsrPlugin_csr_836 +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16712 Q=io_apb_decoder.io_input_PSEL R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_haltIt[0:0] Q=system_cpu.DebugPlugin_haltIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16710 Q=system_cpu.DebugPlugin_resetIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_haltedByBreak[0:0] Q=system_cpu.DebugPlugin_haltedByBreak R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffs C=io_mainClk D=$false Q=system_cpu._zz_5 S=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16614 Q=system_cpu.CsrPlugin_mie_MEIE R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16612 Q=system_cpu.CsrPlugin_mie_MTIE R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16708 Q=system_cpu.DebugPlugin_stepIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16706 Q=system_cpu.DebugPlugin_debugUsed R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16704 Q=system_cpu.DebugPlugin_disableEbreak R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16638 Q=system_cpu.execute_to_memory_BRANCH_DO +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16032 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16030 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16028 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16026 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16024 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16022 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16020 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16018 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16016 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16014 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16012 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16010 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16008 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16006 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16004 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16002 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16000 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15998 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15996 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15994 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15992 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15990 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15988 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15986 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15984 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15982 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15980 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15978 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15976 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15974 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15972 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16640 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] +.subckt dff C=io_mainClk D=systemDebugger_1._zz_io_mem_cmd_payload_address[2] Q=system_cpu._zz_when_DebugPlugin_l257 +.subckt dff C=io_mainClk D=system_cpu.DebugPlugin_resetIt Q=system_cpu.DebugPlugin_resetIt_regNext +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[0] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[0] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[1] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[1] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[2] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[2] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[3] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[3] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[4] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[4] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[5] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[5] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[6] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[6] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[7] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[7] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[8] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[9] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[10] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[11] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[12] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[13] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[14] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[15] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[16] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[17] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[18] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[19] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[20] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[21] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[22] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[23] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[26] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15970 Q=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16642 Q=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15964 Q=system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15962 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15960 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15958 Q=system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15956 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15954 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15952 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15950 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15948 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15946 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15944 Q=system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15942 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15940 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15938 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15936 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15934 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15932 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15930 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15928 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16702 Q=system_cpu._zz_decode_SRC2 +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[0] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[0] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[1] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[2] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[2] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[3] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[3] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[4] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[4] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[5] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[5] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[6] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[6] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[7] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[7] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[8] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[8] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[9] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[9] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[10] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[10] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[11] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[11] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[12] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[13] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[13] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[14] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[14] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[15] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[15] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[16] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[16] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[17] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[17] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[18] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[18] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[19] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[19] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[20] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[20] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[21] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[21] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[22] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[22] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[23] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[23] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[24] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[24] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[25] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[25] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[26] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[26] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[27] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[27] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[28] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[29] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[29] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[30] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[30] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15926 Q=system_cpu.decode_to_execute_PC[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15924 Q=system_cpu.decode_to_execute_PC[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15922 Q=system_cpu.decode_to_execute_PC[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15920 Q=system_cpu.decode_to_execute_PC[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15918 Q=system_cpu.decode_to_execute_PC[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15916 Q=system_cpu.decode_to_execute_PC[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15914 Q=system_cpu.decode_to_execute_PC[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15912 Q=system_cpu.decode_to_execute_PC[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15910 Q=system_cpu.decode_to_execute_PC[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15908 Q=system_cpu.decode_to_execute_PC[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15906 Q=system_cpu.decode_to_execute_PC[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15904 Q=system_cpu.decode_to_execute_PC[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15902 Q=system_cpu.decode_to_execute_PC[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15900 Q=system_cpu.decode_to_execute_PC[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15898 Q=system_cpu.decode_to_execute_PC[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15896 Q=system_cpu.decode_to_execute_PC[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15894 Q=system_cpu.decode_to_execute_PC[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15892 Q=system_cpu.decode_to_execute_PC[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15890 Q=system_cpu.decode_to_execute_PC[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15888 Q=system_cpu.decode_to_execute_PC[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15886 Q=system_cpu.decode_to_execute_PC[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15884 Q=system_cpu.decode_to_execute_PC[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15882 Q=system_cpu.decode_to_execute_PC[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15880 Q=system_cpu.decode_to_execute_PC[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15878 Q=system_cpu.decode_to_execute_PC[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15876 Q=system_cpu.decode_to_execute_PC[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15874 Q=system_cpu.decode_to_execute_PC[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15872 Q=system_cpu.decode_to_execute_PC[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15870 Q=system_cpu.decode_to_execute_PC[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16766 Q=system_cpu.decode_to_execute_PC[31] +.subckt dff C=io_mainClk D=system_cpu.externalInterrupt Q=system_cpu.CsrPlugin_mip_MEIP +.subckt dff C=io_mainClk D=system_cpu.timerInterrupt Q=system_cpu.CsrPlugin_mip_MTIP +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15866 Q=system_cpu.BranchPlugin_jumpInterface_payload[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15864 Q=system_cpu.BranchPlugin_jumpInterface_payload[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15862 Q=system_cpu.BranchPlugin_jumpInterface_payload[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15860 Q=system_cpu.BranchPlugin_jumpInterface_payload[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15858 Q=system_cpu.BranchPlugin_jumpInterface_payload[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15856 Q=system_cpu.BranchPlugin_jumpInterface_payload[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15854 Q=system_cpu.BranchPlugin_jumpInterface_payload[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15852 Q=system_cpu.BranchPlugin_jumpInterface_payload[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15850 Q=system_cpu.BranchPlugin_jumpInterface_payload[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15848 Q=system_cpu.BranchPlugin_jumpInterface_payload[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15846 Q=system_cpu.BranchPlugin_jumpInterface_payload[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15844 Q=system_cpu.BranchPlugin_jumpInterface_payload[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15842 Q=system_cpu.BranchPlugin_jumpInterface_payload[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15840 Q=system_cpu.BranchPlugin_jumpInterface_payload[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15838 Q=system_cpu.BranchPlugin_jumpInterface_payload[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15836 Q=system_cpu.BranchPlugin_jumpInterface_payload[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15834 Q=system_cpu.BranchPlugin_jumpInterface_payload[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15832 Q=system_cpu.BranchPlugin_jumpInterface_payload[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15830 Q=system_cpu.BranchPlugin_jumpInterface_payload[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15828 Q=system_cpu.BranchPlugin_jumpInterface_payload[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15826 Q=system_cpu.BranchPlugin_jumpInterface_payload[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15824 Q=system_cpu.BranchPlugin_jumpInterface_payload[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15822 Q=system_cpu.BranchPlugin_jumpInterface_payload[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15820 Q=system_cpu.BranchPlugin_jumpInterface_payload[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15818 Q=system_cpu.BranchPlugin_jumpInterface_payload[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15816 Q=system_cpu.BranchPlugin_jumpInterface_payload[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15814 Q=system_cpu.BranchPlugin_jumpInterface_payload[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15812 Q=system_cpu.BranchPlugin_jumpInterface_payload[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15810 Q=system_cpu.BranchPlugin_jumpInterface_payload[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16756 Q=system_cpu.BranchPlugin_jumpInterface_payload[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15808 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15806 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15804 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15802 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15800 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15798 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15796 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15794 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15792 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15790 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15788 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15786 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15784 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15782 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15780 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15778 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15776 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15774 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15772 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15770 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15768 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15766 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15764 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15762 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15760 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15758 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15756 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15754 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15752 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16762 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16620 Q=system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16618 Q=system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15736 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15734 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15732 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15730 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15728 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15726 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15724 Q=system_cpu.switch_Misc_l241_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15722 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15720 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15718 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15716 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15714 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15712 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15710 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15708 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15706 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15704 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15702 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15700 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15698 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15696 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15694 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15692 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15690 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16690 Q=system_cpu._zz_execute_BranchPlugin_branch_src2 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15674 Q=system_cpu.execute_to_memory_INSTRUCTION[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15672 Q=system_cpu.execute_to_memory_INSTRUCTION[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15670 Q=system_cpu.execute_to_memory_INSTRUCTION[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15668 Q=system_cpu.execute_to_memory_INSTRUCTION[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15666 Q=system_cpu.execute_to_memory_INSTRUCTION[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15664 Q=system_cpu.execute_to_memory_INSTRUCTION[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15662 Q=system_cpu.execute_to_memory_INSTRUCTION[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15660 Q=system_cpu.execute_to_memory_INSTRUCTION[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15632 Q=system_cpu.execute_to_memory_INSTRUCTION[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15630 Q=system_cpu.execute_to_memory_INSTRUCTION[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15626 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15624 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15622 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15620 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16692 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16682 Q=system_cpu.decode_to_execute_MEMORY_ENABLE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16678 Q=system_cpu.decode_to_execute_REGFILE_WRITE_VALID +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16680 Q=system_cpu.execute_to_memory_MEMORY_ENABLE +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_VALID Q=system_cpu._zz_lastStageRegFileWrite_valid +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPIE[0:0] Q=system_cpu.CsrPlugin_mstatus_MPIE R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MIE[0:0] Q=system_cpu.CsrPlugin_mstatus_MIE R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16684 Q=system_cpu.decode_to_execute_SRC_USE_SUB_LESS +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ENABLE Q=system_cpu.memory_to_writeBack_MEMORY_ENABLE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16674 Q=system_cpu.execute_to_memory_REGFILE_WRITE_VALID +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16670 Q=system_cpu.execute_to_memory_MEMORY_STORE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16668 Q=system_cpu.decode_to_execute_IS_CSR +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16666 Q=system_cpu._zz_execute_ENV_CTRL +.subckt dff C=io_mainClk D=system_cpu._zz_memory_ENV_CTRL Q=system_cpu._zz_writeBack_ENV_CTRL +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16672 Q=system_cpu.dBus_cmd_payload_wr +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15618 Q=system_cpu._zz_execute_ALU_BITWISE_CTRL[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16658 Q=system_cpu._zz_execute_ALU_BITWISE_CTRL[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15616 Q=system_cpu._zz_execute_ALU_CTRL[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16662 Q=system_cpu._zz_execute_ALU_CTRL[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15614 Q=system_cpu._zz_execute_SHIFT_CTRL[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16656 Q=system_cpu._zz_execute_SHIFT_CTRL[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15612 Q=system_cpu._zz_execute_BRANCH_CTRL[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16654 Q=system_cpu._zz_execute_BRANCH_CTRL[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15610 Q=system_cpu._zz_dBus_cmd_payload_data[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15608 Q=system_cpu._zz_dBus_cmd_payload_data[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15606 Q=system_cpu._zz_dBus_cmd_payload_data[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15604 Q=system_cpu._zz_dBus_cmd_payload_data[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15602 Q=system_cpu._zz_dBus_cmd_payload_data[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15600 Q=system_cpu._zz_dBus_cmd_payload_data[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15598 Q=system_cpu._zz_dBus_cmd_payload_data[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15596 Q=system_cpu._zz_dBus_cmd_payload_data[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15594 Q=system_cpu.decode_to_execute_RS2[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15592 Q=system_cpu.decode_to_execute_RS2[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15590 Q=system_cpu.decode_to_execute_RS2[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15588 Q=system_cpu.decode_to_execute_RS2[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15586 Q=system_cpu.decode_to_execute_RS2[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15584 Q=system_cpu.decode_to_execute_RS2[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15582 Q=system_cpu.decode_to_execute_RS2[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15580 Q=system_cpu.decode_to_execute_RS2[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15578 Q=system_cpu.decode_to_execute_RS2[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15576 Q=system_cpu.decode_to_execute_RS2[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15574 Q=system_cpu.decode_to_execute_RS2[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15572 Q=system_cpu.decode_to_execute_RS2[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15570 Q=system_cpu.decode_to_execute_RS2[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15568 Q=system_cpu.decode_to_execute_RS2[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15566 Q=system_cpu.decode_to_execute_RS2[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15564 Q=system_cpu.decode_to_execute_RS2[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15562 Q=system_cpu.decode_to_execute_RS2[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15560 Q=system_cpu.decode_to_execute_RS2[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15558 Q=system_cpu.decode_to_execute_RS2[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15556 Q=system_cpu.decode_to_execute_RS2[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15554 Q=system_cpu.decode_to_execute_RS2[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15552 Q=system_cpu.decode_to_execute_RS2[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15550 Q=system_cpu.decode_to_execute_RS2[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16650 Q=system_cpu.decode_to_execute_RS2[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15548 Q=system_cpu.decode_to_execute_RS1[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15546 Q=system_cpu.decode_to_execute_RS1[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15544 Q=system_cpu.decode_to_execute_RS1[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15542 Q=system_cpu.decode_to_execute_RS1[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15540 Q=system_cpu.decode_to_execute_RS1[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15538 Q=system_cpu.decode_to_execute_RS1[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15536 Q=system_cpu.decode_to_execute_RS1[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15534 Q=system_cpu.decode_to_execute_RS1[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15532 Q=system_cpu.decode_to_execute_RS1[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15530 Q=system_cpu.decode_to_execute_RS1[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15528 Q=system_cpu.decode_to_execute_RS1[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15526 Q=system_cpu.decode_to_execute_RS1[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15524 Q=system_cpu.decode_to_execute_RS1[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15522 Q=system_cpu.decode_to_execute_RS1[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15520 Q=system_cpu.decode_to_execute_RS1[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15518 Q=system_cpu.decode_to_execute_RS1[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15516 Q=system_cpu.decode_to_execute_RS1[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15514 Q=system_cpu.decode_to_execute_RS1[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15512 Q=system_cpu.decode_to_execute_RS1[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15510 Q=system_cpu.decode_to_execute_RS1[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15508 Q=system_cpu.decode_to_execute_RS1[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15506 Q=system_cpu.decode_to_execute_RS1[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15504 Q=system_cpu.decode_to_execute_RS1[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15502 Q=system_cpu.decode_to_execute_RS1[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15500 Q=system_cpu.decode_to_execute_RS1[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15498 Q=system_cpu.decode_to_execute_RS1[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15496 Q=system_cpu.decode_to_execute_RS1[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15494 Q=system_cpu.decode_to_execute_RS1[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15492 Q=system_cpu.decode_to_execute_RS1[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15490 Q=system_cpu.decode_to_execute_RS1[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15488 Q=system_cpu.decode_to_execute_RS1[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16652 Q=system_cpu.decode_to_execute_RS1[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16664 Q=system_cpu._zz_memory_ENV_CTRL +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16660 Q=system_cpu.decode_to_execute_SRC_LESS_UNSIGNED +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16648 Q=system_cpu.decode_to_execute_SRC2_FORCE_ZERO +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15486 Q=system_cpu.decode_to_execute_SRC2[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15484 Q=system_cpu.decode_to_execute_SRC2[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15482 Q=system_cpu.decode_to_execute_SRC2[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15480 Q=system_cpu.decode_to_execute_SRC2[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15478 Q=system_cpu.decode_to_execute_SRC2[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15476 Q=system_cpu.decode_to_execute_SRC2[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15474 Q=system_cpu.decode_to_execute_SRC2[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15472 Q=system_cpu.decode_to_execute_SRC2[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15470 Q=system_cpu.decode_to_execute_SRC2[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15468 Q=system_cpu.decode_to_execute_SRC2[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15466 Q=system_cpu.decode_to_execute_SRC2[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15464 Q=system_cpu.decode_to_execute_SRC2[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15462 Q=system_cpu.decode_to_execute_SRC2[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15460 Q=system_cpu.decode_to_execute_SRC2[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15458 Q=system_cpu.decode_to_execute_SRC2[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15456 Q=system_cpu.decode_to_execute_SRC2[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15454 Q=system_cpu.decode_to_execute_SRC2[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15452 Q=system_cpu.decode_to_execute_SRC2[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15450 Q=system_cpu.decode_to_execute_SRC2[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15448 Q=system_cpu.decode_to_execute_SRC2[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15446 Q=system_cpu.decode_to_execute_SRC2[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15444 Q=system_cpu.decode_to_execute_SRC2[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15442 Q=system_cpu.decode_to_execute_SRC2[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15440 Q=system_cpu.decode_to_execute_SRC2[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15438 Q=system_cpu.decode_to_execute_SRC2[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15436 Q=system_cpu.decode_to_execute_SRC2[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15434 Q=system_cpu.decode_to_execute_SRC2[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15432 Q=system_cpu.decode_to_execute_SRC2[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15430 Q=system_cpu.decode_to_execute_SRC2[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15428 Q=system_cpu.decode_to_execute_SRC2[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15426 Q=system_cpu.decode_to_execute_SRC2[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16646 Q=system_cpu.decode_to_execute_SRC2[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16644 Q=system_cpu.decode_to_execute_DO_EBREAK +.subckt dffr C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid Q=jtagBridge_1.flowCCByToggle_1.io_output_valid R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 Q=jtagBridge_1.flowCCByToggle_1.outputArea_hit +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15424 Q=jtagBridge_1.system_rsp_payload_data[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15422 Q=jtagBridge_1.system_rsp_payload_data[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15420 Q=jtagBridge_1.system_rsp_payload_data[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15418 Q=jtagBridge_1.system_rsp_payload_data[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15416 Q=jtagBridge_1.system_rsp_payload_data[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15414 Q=jtagBridge_1.system_rsp_payload_data[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15412 Q=jtagBridge_1.system_rsp_payload_data[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15410 Q=jtagBridge_1.system_rsp_payload_data[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15408 Q=jtagBridge_1.system_rsp_payload_data[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15406 Q=jtagBridge_1.system_rsp_payload_data[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15404 Q=jtagBridge_1.system_rsp_payload_data[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15402 Q=jtagBridge_1.system_rsp_payload_data[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15400 Q=jtagBridge_1.system_rsp_payload_data[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15398 Q=jtagBridge_1.system_rsp_payload_data[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15396 Q=jtagBridge_1.system_rsp_payload_data[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15394 Q=jtagBridge_1.system_rsp_payload_data[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15392 Q=jtagBridge_1.system_rsp_payload_data[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15390 Q=jtagBridge_1.system_rsp_payload_data[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15388 Q=jtagBridge_1.system_rsp_payload_data[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15386 Q=jtagBridge_1.system_rsp_payload_data[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15384 Q=jtagBridge_1.system_rsp_payload_data[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15382 Q=jtagBridge_1.system_rsp_payload_data[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15380 Q=jtagBridge_1.system_rsp_payload_data[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15378 Q=jtagBridge_1.system_rsp_payload_data[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15376 Q=jtagBridge_1.system_rsp_payload_data[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15374 Q=jtagBridge_1.system_rsp_payload_data[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15372 Q=jtagBridge_1.system_rsp_payload_data[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15370 Q=jtagBridge_1.system_rsp_payload_data[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15368 Q=jtagBridge_1.system_rsp_payload_data[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15366 Q=jtagBridge_1.system_rsp_payload_data[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15364 Q=jtagBridge_1.system_rsp_payload_data[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16744 Q=jtagBridge_1.system_rsp_payload_data[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16742 Q=jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16740 Q=jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16738 Q=jtagBridge_1.flowCCByToggle_1.inputArea_target +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16736 Q=jtagBridge_1.flowCCByToggle_1.inputArea_data_last +.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_0 Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 +.subckt dff C=io_jtag_tck D=$abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] Q=jtagBridge_1.flowCCByToggle_1.io_input_valid +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15362 Q=jtagBridge_1.jtag_idcodeArea_ctrl_tdo S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15360 Q=jtagBridge_1.jtag_idcodeArea_shifter[1] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15358 Q=jtagBridge_1.jtag_idcodeArea_shifter[2] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15356 Q=jtagBridge_1.jtag_idcodeArea_shifter[3] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15354 Q=jtagBridge_1.jtag_idcodeArea_shifter[4] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15352 Q=jtagBridge_1.jtag_idcodeArea_shifter[5] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15350 Q=jtagBridge_1.jtag_idcodeArea_shifter[6] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15348 Q=jtagBridge_1.jtag_idcodeArea_shifter[7] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15346 Q=jtagBridge_1.jtag_idcodeArea_shifter[8] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15344 Q=jtagBridge_1.jtag_idcodeArea_shifter[9] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15342 Q=jtagBridge_1.jtag_idcodeArea_shifter[10] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15340 Q=jtagBridge_1.jtag_idcodeArea_shifter[11] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15338 Q=jtagBridge_1.jtag_idcodeArea_shifter[12] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15336 Q=jtagBridge_1.jtag_idcodeArea_shifter[13] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15334 Q=jtagBridge_1.jtag_idcodeArea_shifter[14] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15332 Q=jtagBridge_1.jtag_idcodeArea_shifter[15] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15330 Q=jtagBridge_1.jtag_idcodeArea_shifter[16] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15328 Q=jtagBridge_1.jtag_idcodeArea_shifter[17] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15326 Q=jtagBridge_1.jtag_idcodeArea_shifter[18] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15324 Q=jtagBridge_1.jtag_idcodeArea_shifter[19] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15322 Q=jtagBridge_1.jtag_idcodeArea_shifter[20] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15320 Q=jtagBridge_1.jtag_idcodeArea_shifter[21] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15318 Q=jtagBridge_1.jtag_idcodeArea_shifter[22] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15316 Q=jtagBridge_1.jtag_idcodeArea_shifter[23] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15314 Q=jtagBridge_1.jtag_idcodeArea_shifter[24] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15312 Q=jtagBridge_1.jtag_idcodeArea_shifter[25] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15310 Q=jtagBridge_1.jtag_idcodeArea_shifter[26] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15308 Q=jtagBridge_1.jtag_idcodeArea_shifter[27] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15306 Q=jtagBridge_1.jtag_idcodeArea_shifter[28] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15304 Q=jtagBridge_1.jtag_idcodeArea_shifter[29] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15302 Q=jtagBridge_1.jtag_idcodeArea_shifter[30] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16748 Q=jtagBridge_1.jtag_idcodeArea_shifter[31] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt dff C=io_jtag_tck D=io_jtag_tdi Q=jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15300 Q=jtagBridge_1._zz_jtag_tap_isBypass[0] S=jtagBridge_1.when_JtagTap_l120 +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15298 Q=jtagBridge_1._zz_jtag_tap_isBypass[1] R=jtagBridge_1.when_JtagTap_l120 +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15296 Q=jtagBridge_1._zz_jtag_tap_isBypass[2] R=jtagBridge_1.when_JtagTap_l120 +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16746 Q=jtagBridge_1._zz_jtag_tap_isBypass[3] R=jtagBridge_1.when_JtagTap_l120 +.subckt sdffrn C=io_mainClk D=system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] Q=system_cpu.CsrPlugin_mip_MSIP RN=$abc$18544$auto$opt_dff.cc:253:combine_resets$3598 +.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[0] Q=jtagBridge_1.jtag_tap_fsm_state[0] +.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[1] Q=jtagBridge_1.jtag_tap_fsm_state[1] +.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[2] Q=jtagBridge_1.jtag_tap_fsm_state[2] +.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[3] Q=jtagBridge_1.jtag_tap_fsm_state[3] +.subckt dffn C=io_jtag_tck D=jtagBridge_1.jtag_tap_tdoUnbufferd Q=io_jtag_tdo +.subckt sdffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16750 Q=jtagBridge_1.system_rsp_valid S=jtagBridge_1.io_remote_rsp_fire +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15294 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15290 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15286 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16792 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15282 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15280 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15278 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15276 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15274 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15272 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15270 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15268 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15266 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15264 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15262 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15260 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15258 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15256 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15254 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15252 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15250 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15248 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15246 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15244 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16794 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[31] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16518 Q=system_mainBusArbiter.rspPending R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_0 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15242 Q=systemDebugger_1.dispatcher_header[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15240 Q=systemDebugger_1.dispatcher_header[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15238 Q=systemDebugger_1.dispatcher_header[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15236 Q=systemDebugger_1.dispatcher_header[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15234 Q=systemDebugger_1.dispatcher_header[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15232 Q=systemDebugger_1.dispatcher_header[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15230 Q=systemDebugger_1.dispatcher_header[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16730 Q=systemDebugger_1.dispatcher_header[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15224 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15222 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15220 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15218 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15216 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15214 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15212 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15210 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15208 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15206 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15204 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15202 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15200 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15198 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15196 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15194 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15192 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15190 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15188 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15186 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15184 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15182 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15180 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15178 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15176 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15174 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15172 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15170 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15168 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15166 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15164 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[32] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15162 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[33] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15160 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[34] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15158 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[35] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15156 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[36] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15154 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[37] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15152 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[38] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15150 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[39] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15148 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[40] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15146 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[41] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15144 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[42] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15142 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[43] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15140 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[44] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15138 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[45] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15136 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[46] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15134 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[47] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15132 Q=system_cpu.when_DebugPlugin_l284 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15130 Q=system_cpu.when_DebugPlugin_l285 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15128 Q=system_cpu.when_DebugPlugin_l288 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15126 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[51] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15124 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[52] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15122 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[53] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15120 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[54] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15118 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[55] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15116 Q=system_cpu.when_DebugPlugin_l284_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15114 Q=system_cpu.when_DebugPlugin_l285_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15112 Q=system_cpu.when_DebugPlugin_l288_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15110 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[59] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15108 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[60] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15106 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[61] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15104 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[62] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15102 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[63] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15100 Q=systemDebugger_1.io_mem_cmd_payload_wr +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15098 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[65] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16732 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[66] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16734 Q=jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16728 Q=systemDebugger_1.dispatcher_dataLoaded R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16726 Q=systemDebugger_1.dispatcher_headerLoaded R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16588 Q=system_mainBusArbiter.rspTarget R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_ram.$0\_zz_io_bus_rsp_valid[0:0] Q=system_ram._zz_io_bus_rsp_valid R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[10] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[10] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[11] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[11] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[12] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[12] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[13] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[13] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[14] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[14] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15096 Q=system_uartCtrl.when_BusSlaveFactory_l347 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15094 Q=system_uartCtrl.when_BusSlaveFactory_l347_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15092 Q=apb3Router_1.io_input_PWDATA[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15090 Q=apb3Router_1.io_input_PWDATA[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15088 Q=apb3Router_1.io_input_PWDATA[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15086 Q=apb3Router_1.io_input_PWDATA[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15084 Q=apb3Router_1.io_input_PWDATA[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15082 Q=apb3Router_1.io_input_PWDATA[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15080 Q=apb3Router_1.io_input_PWDATA[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15078 Q=system_uartCtrl.when_BusSlaveFactory_l347_2 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15076 Q=system_uartCtrl.when_BusSlaveFactory_l379 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15074 Q=system_uartCtrl.when_BusSlaveFactory_l347_3 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15072 Q=apb3Router_1.io_input_PWDATA[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15070 Q=apb3Router_1.io_input_PWDATA[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15068 Q=apb3Router_1.io_input_PWDATA[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15066 Q=apb3Router_1.io_input_PWDATA[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15064 Q=apb3Router_1.io_input_PWDATA[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15062 Q=apb3Router_1.io_input_PWDATA[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15060 Q=apb3Router_1.io_input_PWDATA[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15058 Q=apb3Router_1.io_input_PWDATA[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15056 Q=apb3Router_1.io_input_PWDATA[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15054 Q=apb3Router_1.io_input_PWDATA[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15052 Q=apb3Router_1.io_input_PWDATA[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15050 Q=apb3Router_1.io_input_PWDATA[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15048 Q=apb3Router_1.io_input_PWDATA[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15046 Q=apb3Router_1.io_input_PWDATA[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15044 Q=apb3Router_1.io_input_PWDATA[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15042 Q=apb3Router_1.io_input_PWDATA[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15040 Q=apb3Router_1.io_input_PWDATA[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15038 Q=apb3Router_1.io_input_PWDATA[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15036 Q=apb3Router_1.io_input_PWDATA[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16714 Q=apb3Router_1.io_input_PWDATA[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16722 Q=apb3Router_1.io_input_PWRITE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15034 Q=apb3Router_1.io_input_PADDR[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16718 Q=apb3Router_1.io_input_PADDR[1] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15030 Q=systemDebugger_1.dispatcher_counter[0] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15028 Q=systemDebugger_1.dispatcher_counter[1] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16724 Q=systemDebugger_1.dispatcher_counter[2] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=system_apbBridge.pipelinedMemoryBusStage_rsp_valid Q=system_apbBridge.io_pipelinedMemoryBus_rsp_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_apbBridge.$0\state[0:0] Q=apb3Router_1.io_input_PENABLE R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[0] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[0] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[1] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[1] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[2] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[2] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[3] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[3] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[4] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[4] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[5] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[5] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[6] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[6] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[7] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[7] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[8] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[8] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[9] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[9] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[10] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[10] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[11] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[11] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[12] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[12] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[13] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[13] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[14] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[14] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[15] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[15] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[16] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[16] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[17] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[17] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[18] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[18] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[19] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[19] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[20] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[20] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[21] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[21] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[22] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[22] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[23] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[23] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[24] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[24] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[25] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[25] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[26] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[26] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[27] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[27] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[28] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[28] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[29] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[29] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[30] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[30] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[31] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[31] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16594 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15026 Q=io_gpioA_write[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15024 Q=io_gpioA_write[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15022 Q=io_gpioA_write[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15020 Q=io_gpioA_write[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15018 Q=io_gpioA_write[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15016 Q=io_gpioA_write[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15014 Q=io_gpioA_write[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15012 Q=io_gpioA_write[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15010 Q=io_gpioA_write[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15008 Q=io_gpioA_write[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15006 Q=io_gpioA_write[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15004 Q=io_gpioA_write[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15002 Q=io_gpioA_write[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15000 Q=io_gpioA_write[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14998 Q=io_gpioA_write[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14996 Q=io_gpioA_write[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14994 Q=io_gpioA_write[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14992 Q=io_gpioA_write[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14990 Q=io_gpioA_write[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14988 Q=io_gpioA_write[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14986 Q=io_gpioA_write[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14984 Q=io_gpioA_write[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14982 Q=io_gpioA_write[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14980 Q=io_gpioA_write[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14978 Q=io_gpioA_write[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14976 Q=io_gpioA_write[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14974 Q=io_gpioA_write[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14972 Q=io_gpioA_write[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14970 Q=io_gpioA_write[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14968 Q=io_gpioA_write[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14966 Q=io_gpioA_write[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16592 Q=io_gpioA_write[31] +.subckt dff C=io_mainClk D=io_gpioA_read[0] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[0] +.subckt dff C=io_mainClk D=io_gpioA_read[1] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[1] +.subckt dff C=io_mainClk D=io_gpioA_read[2] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[2] +.subckt dff C=io_mainClk D=io_gpioA_read[3] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[3] +.subckt dff C=io_mainClk D=io_gpioA_read[4] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[4] +.subckt dff C=io_mainClk D=io_gpioA_read[5] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[5] +.subckt dff C=io_mainClk D=io_gpioA_read[6] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[6] +.subckt dff C=io_mainClk D=io_gpioA_read[7] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[7] +.subckt dff C=io_mainClk D=io_gpioA_read[8] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[8] +.subckt dff C=io_mainClk D=io_gpioA_read[9] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[9] +.subckt dff C=io_mainClk D=io_gpioA_read[10] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[10] +.subckt dff C=io_mainClk D=io_gpioA_read[11] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[11] +.subckt dff C=io_mainClk D=io_gpioA_read[12] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[12] +.subckt dff C=io_mainClk D=io_gpioA_read[13] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[13] +.subckt dff C=io_mainClk D=io_gpioA_read[14] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[14] +.subckt dff C=io_mainClk D=io_gpioA_read[15] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[15] +.subckt dff C=io_mainClk D=io_gpioA_read[16] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[16] +.subckt dff C=io_mainClk D=io_gpioA_read[17] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[17] +.subckt dff C=io_mainClk D=io_gpioA_read[18] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[18] +.subckt dff C=io_mainClk D=io_gpioA_read[19] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[19] +.subckt dff C=io_mainClk D=io_gpioA_read[20] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[20] +.subckt dff C=io_mainClk D=io_gpioA_read[21] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[21] +.subckt dff C=io_mainClk D=io_gpioA_read[22] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[22] +.subckt dff C=io_mainClk D=io_gpioA_read[23] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[23] +.subckt dff C=io_mainClk D=io_gpioA_read[24] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[24] +.subckt dff C=io_mainClk D=io_gpioA_read[25] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[25] +.subckt dff C=io_mainClk D=io_gpioA_read[26] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[26] +.subckt dff C=io_mainClk D=io_gpioA_read[27] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[27] +.subckt dff C=io_mainClk D=io_gpioA_read[28] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[28] +.subckt dff C=io_mainClk D=io_gpioA_read[29] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[29] +.subckt dff C=io_mainClk D=io_gpioA_read[30] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[30] +.subckt dff C=io_mainClk D=io_gpioA_read[31] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[31] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14964 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14962 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14960 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14958 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16550 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14956 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14954 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14952 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14950 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16548 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16546 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14948 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14946 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14944 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14942 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16544 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16560 Q=system_uartCtrl.bridge_misc_readOverflowError R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14940 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14938 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14936 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14934 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16558 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14932 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14930 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14928 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14926 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16556 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16554 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14924 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14922 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14920 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14918 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16552 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][0] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][1] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][2] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][3] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][4] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][5] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[5] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][6] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[6] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][7] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[7] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][8] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[8] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][9] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[9] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][10] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[10] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][11] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[11] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][12] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[12] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][13] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[13] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][14] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[14] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][15] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[15] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][16] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[16] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][17] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[17] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][18] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[18] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][19] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[19] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.clockDivider_tick Q=system_uartCtrl.uartCtrl_1.clockDivider_tickReg R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[0] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[1] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[2] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14916 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14914 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16534 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[0] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[1] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[2] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\stateMachine_parity[0:0] Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_parity +.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\_zz_io_txd[0:0] Q=io_uart_txd S=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14912 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14910 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14908 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14906 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14904 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14902 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14900 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14898 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14896 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14894 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14892 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14890 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14888 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14886 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14884 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14882 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14880 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14878 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14876 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14874 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14872 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14870 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14868 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14866 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14864 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14862 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14860 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14858 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14856 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16764 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_0 Q=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 R=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16540 Q=system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 S=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14854 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14852 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14850 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14848 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14846 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14844 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14842 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16542 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\stateMachine_parity[0:0] Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_parity +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[0] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[1] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[2] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][0] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][1] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][2] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=system_cpu.lastStageRegFileWrite_payload_data[0] data_i[34]=system_cpu.lastStageRegFileWrite_payload_data[1] data_i[33]=system_cpu.lastStageRegFileWrite_payload_data[2] data_i[32]=system_cpu.lastStageRegFileWrite_payload_data[3] data_i[31]=system_cpu.lastStageRegFileWrite_payload_data[4] data_i[30]=system_cpu.lastStageRegFileWrite_payload_data[5] data_i[29]=system_cpu.lastStageRegFileWrite_payload_data[6] data_i[28]=system_cpu.lastStageRegFileWrite_payload_data[7] data_i[27]=system_cpu.lastStageRegFileWrite_payload_data[8] data_i[26]=system_cpu.lastStageRegFileWrite_payload_data[9] data_i[25]=system_cpu.lastStageRegFileWrite_payload_data[10] data_i[24]=system_cpu.lastStageRegFileWrite_payload_data[11] data_i[23]=system_cpu.lastStageRegFileWrite_payload_data[12] data_i[22]=system_cpu.lastStageRegFileWrite_payload_data[13] data_i[21]=system_cpu.lastStageRegFileWrite_payload_data[14] data_i[20]=system_cpu.lastStageRegFileWrite_payload_data[15] data_i[19]=system_cpu.lastStageRegFileWrite_payload_data[16] data_i[18]=system_cpu.lastStageRegFileWrite_payload_data[17] data_i[17]=system_cpu.lastStageRegFileWrite_payload_data[18] data_i[16]=system_cpu.lastStageRegFileWrite_payload_data[19] data_i[15]=system_cpu.lastStageRegFileWrite_payload_data[20] data_i[14]=system_cpu.lastStageRegFileWrite_payload_data[21] data_i[13]=system_cpu.lastStageRegFileWrite_payload_data[22] data_i[12]=system_cpu.lastStageRegFileWrite_payload_data[23] data_i[11]=system_cpu.lastStageRegFileWrite_payload_data[24] data_i[10]=system_cpu.lastStageRegFileWrite_payload_data[25] data_i[9]=system_cpu.lastStageRegFileWrite_payload_data[26] data_i[8]=system_cpu.lastStageRegFileWrite_payload_data[27] data_i[7]=system_cpu.lastStageRegFileWrite_payload_data[28] data_i[6]=system_cpu.lastStageRegFileWrite_payload_data[29] data_i[5]=system_cpu.lastStageRegFileWrite_payload_data[30] data_i[4]=system_cpu.lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=system_cpu._zz_RegFilePlugin_regFile_port1[0] q_o[34]=system_cpu._zz_RegFilePlugin_regFile_port1[1] q_o[33]=system_cpu._zz_RegFilePlugin_regFile_port1[2] q_o[32]=system_cpu._zz_RegFilePlugin_regFile_port1[3] q_o[31]=system_cpu._zz_RegFilePlugin_regFile_port1[4] q_o[30]=system_cpu._zz_RegFilePlugin_regFile_port1[5] q_o[29]=system_cpu._zz_RegFilePlugin_regFile_port1[6] q_o[28]=system_cpu._zz_RegFilePlugin_regFile_port1[7] q_o[27]=system_cpu._zz_RegFilePlugin_regFile_port1[8] q_o[26]=system_cpu._zz_RegFilePlugin_regFile_port1[9] q_o[25]=system_cpu._zz_RegFilePlugin_regFile_port1[10] q_o[24]=system_cpu._zz_RegFilePlugin_regFile_port1[11] q_o[23]=system_cpu._zz_RegFilePlugin_regFile_port1[12] q_o[22]=system_cpu._zz_RegFilePlugin_regFile_port1[13] q_o[21]=system_cpu._zz_RegFilePlugin_regFile_port1[14] q_o[20]=system_cpu._zz_RegFilePlugin_regFile_port1[15] q_o[19]=system_cpu._zz_RegFilePlugin_regFile_port1[16] q_o[18]=system_cpu._zz_RegFilePlugin_regFile_port1[17] q_o[17]=system_cpu._zz_RegFilePlugin_regFile_port1[18] q_o[16]=system_cpu._zz_RegFilePlugin_regFile_port1[19] q_o[15]=system_cpu._zz_RegFilePlugin_regFile_port1[20] q_o[14]=system_cpu._zz_RegFilePlugin_regFile_port1[21] q_o[13]=system_cpu._zz_RegFilePlugin_regFile_port1[22] q_o[12]=system_cpu._zz_RegFilePlugin_regFile_port1[23] q_o[11]=system_cpu._zz_RegFilePlugin_regFile_port1[24] q_o[10]=system_cpu._zz_RegFilePlugin_regFile_port1[25] q_o[9]=system_cpu._zz_RegFilePlugin_regFile_port1[26] q_o[8]=system_cpu._zz_RegFilePlugin_regFile_port1[27] q_o[7]=system_cpu._zz_RegFilePlugin_regFile_port1[28] q_o[6]=system_cpu._zz_RegFilePlugin_regFile_port1[29] q_o[5]=system_cpu._zz_RegFilePlugin_regFile_port1[30] q_o[4]=system_cpu._zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4542[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4542[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4542[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4542[35] raddr_i[7]=system_cpu.decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=system_cpu.decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=system_cpu.decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=system_cpu.decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=system_cpu.decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=$true waddr_i[7]=system_cpu.lastStageRegFileWrite_payload_address[0] waddr_i[6]=system_cpu.lastStageRegFileWrite_payload_address[1] waddr_i[5]=system_cpu.lastStageRegFileWrite_payload_address[2] waddr_i[4]=system_cpu.lastStageRegFileWrite_payload_address[3] waddr_i[3]=system_cpu.lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_cpu._zz_1 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=system_cpu.lastStageRegFileWrite_payload_data[0] data_i[34]=system_cpu.lastStageRegFileWrite_payload_data[1] data_i[33]=system_cpu.lastStageRegFileWrite_payload_data[2] data_i[32]=system_cpu.lastStageRegFileWrite_payload_data[3] data_i[31]=system_cpu.lastStageRegFileWrite_payload_data[4] data_i[30]=system_cpu.lastStageRegFileWrite_payload_data[5] data_i[29]=system_cpu.lastStageRegFileWrite_payload_data[6] data_i[28]=system_cpu.lastStageRegFileWrite_payload_data[7] data_i[27]=system_cpu.lastStageRegFileWrite_payload_data[8] data_i[26]=system_cpu.lastStageRegFileWrite_payload_data[9] data_i[25]=system_cpu.lastStageRegFileWrite_payload_data[10] data_i[24]=system_cpu.lastStageRegFileWrite_payload_data[11] data_i[23]=system_cpu.lastStageRegFileWrite_payload_data[12] data_i[22]=system_cpu.lastStageRegFileWrite_payload_data[13] data_i[21]=system_cpu.lastStageRegFileWrite_payload_data[14] data_i[20]=system_cpu.lastStageRegFileWrite_payload_data[15] data_i[19]=system_cpu.lastStageRegFileWrite_payload_data[16] data_i[18]=system_cpu.lastStageRegFileWrite_payload_data[17] data_i[17]=system_cpu.lastStageRegFileWrite_payload_data[18] data_i[16]=system_cpu.lastStageRegFileWrite_payload_data[19] data_i[15]=system_cpu.lastStageRegFileWrite_payload_data[20] data_i[14]=system_cpu.lastStageRegFileWrite_payload_data[21] data_i[13]=system_cpu.lastStageRegFileWrite_payload_data[22] data_i[12]=system_cpu.lastStageRegFileWrite_payload_data[23] data_i[11]=system_cpu.lastStageRegFileWrite_payload_data[24] data_i[10]=system_cpu.lastStageRegFileWrite_payload_data[25] data_i[9]=system_cpu.lastStageRegFileWrite_payload_data[26] data_i[8]=system_cpu.lastStageRegFileWrite_payload_data[27] data_i[7]=system_cpu.lastStageRegFileWrite_payload_data[28] data_i[6]=system_cpu.lastStageRegFileWrite_payload_data[29] data_i[5]=system_cpu.lastStageRegFileWrite_payload_data[30] data_i[4]=system_cpu.lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=system_cpu._zz_RegFilePlugin_regFile_port0[0] q_o[34]=system_cpu._zz_RegFilePlugin_regFile_port0[1] q_o[33]=system_cpu._zz_RegFilePlugin_regFile_port0[2] q_o[32]=system_cpu._zz_RegFilePlugin_regFile_port0[3] q_o[31]=system_cpu._zz_RegFilePlugin_regFile_port0[4] q_o[30]=system_cpu._zz_RegFilePlugin_regFile_port0[5] q_o[29]=system_cpu._zz_RegFilePlugin_regFile_port0[6] q_o[28]=system_cpu._zz_RegFilePlugin_regFile_port0[7] q_o[27]=system_cpu._zz_RegFilePlugin_regFile_port0[8] q_o[26]=system_cpu._zz_RegFilePlugin_regFile_port0[9] q_o[25]=system_cpu._zz_RegFilePlugin_regFile_port0[10] q_o[24]=system_cpu._zz_RegFilePlugin_regFile_port0[11] q_o[23]=system_cpu._zz_RegFilePlugin_regFile_port0[12] q_o[22]=system_cpu._zz_RegFilePlugin_regFile_port0[13] q_o[21]=system_cpu._zz_RegFilePlugin_regFile_port0[14] q_o[20]=system_cpu._zz_RegFilePlugin_regFile_port0[15] q_o[19]=system_cpu._zz_RegFilePlugin_regFile_port0[16] q_o[18]=system_cpu._zz_RegFilePlugin_regFile_port0[17] q_o[17]=system_cpu._zz_RegFilePlugin_regFile_port0[18] q_o[16]=system_cpu._zz_RegFilePlugin_regFile_port0[19] q_o[15]=system_cpu._zz_RegFilePlugin_regFile_port0[20] q_o[14]=system_cpu._zz_RegFilePlugin_regFile_port0[21] q_o[13]=system_cpu._zz_RegFilePlugin_regFile_port0[22] q_o[12]=system_cpu._zz_RegFilePlugin_regFile_port0[23] q_o[11]=system_cpu._zz_RegFilePlugin_regFile_port0[24] q_o[10]=system_cpu._zz_RegFilePlugin_regFile_port0[25] q_o[9]=system_cpu._zz_RegFilePlugin_regFile_port0[26] q_o[8]=system_cpu._zz_RegFilePlugin_regFile_port0[27] q_o[7]=system_cpu._zz_RegFilePlugin_regFile_port0[28] q_o[6]=system_cpu._zz_RegFilePlugin_regFile_port0[29] q_o[5]=system_cpu._zz_RegFilePlugin_regFile_port0[30] q_o[4]=system_cpu._zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4543[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4543[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4543[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4543[35] raddr_i[7]=system_cpu.decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=system_cpu.decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=system_cpu.decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=system_cpu.decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=system_cpu.decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=$true waddr_i[7]=system_cpu.lastStageRegFileWrite_payload_address[0] waddr_i[6]=system_cpu.lastStageRegFileWrite_payload_address[1] waddr_i[5]=system_cpu.lastStageRegFileWrite_payload_address[2] waddr_i[4]=system_cpu.lastStageRegFileWrite_payload_address[3] waddr_i[3]=system_cpu.lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_cpu._zz_1 +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] q_o[3]=system_ram._zz_ram_port0[0] q_o[2]=system_ram._zz_ram_port0[1] q_o[1]=system_ram._zz_ram_port0[2] q_o[0]=system_ram._zz_ram_port0[3] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] q_o[3]=system_ram._zz_ram_port0[4] q_o[2]=system_ram._zz_ram_port0[5] q_o[1]=system_ram._zz_ram_port0[6] q_o[0]=system_ram._zz_ram_port0[7] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] q_o[3]=system_ram._zz_ram_port0[8] q_o[2]=system_ram._zz_ram_port0[9] q_o[1]=system_ram._zz_ram_port0[10] q_o[0]=system_ram._zz_ram_port0[11] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] q_o[3]=system_ram._zz_ram_port0[12] q_o[2]=system_ram._zz_ram_port0[13] q_o[1]=system_ram._zz_ram_port0[14] q_o[0]=system_ram._zz_ram_port0[15] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] q_o[3]=system_ram._zz_ram_port0[16] q_o[2]=system_ram._zz_ram_port0[17] q_o[1]=system_ram._zz_ram_port0[18] q_o[0]=system_ram._zz_ram_port0[19] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] q_o[3]=system_ram._zz_ram_port0[20] q_o[2]=system_ram._zz_ram_port0[21] q_o[1]=system_ram._zz_ram_port0[22] q_o[0]=system_ram._zz_ram_port0[23] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] q_o[3]=system_ram._zz_ram_port0[24] q_o[2]=system_ram._zz_ram_port0[25] q_o[1]=system_ram._zz_ram_port0[26] q_o[0]=system_ram._zz_ram_port0[27] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] q_o[3]=system_ram._zz_ram_port0[28] q_o[2]=system_ram._zz_ram_port0[29] q_o[1]=system_ram._zz_ram_port0[30] q_o[0]=system_ram._zz_ram_port0[31] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=system_uartCtrl.when_BusSlaveFactory_l347 data_i[7]=system_uartCtrl.when_BusSlaveFactory_l347_1 data_i[6]=apb3Router_1.io_input_PWDATA[2] data_i[5]=apb3Router_1.io_input_PWDATA[3] data_i[4]=apb3Router_1.io_input_PWDATA[4] data_i[3]=apb3Router_1.io_input_PWDATA[5] data_i[2]=apb3Router_1.io_input_PWDATA[6] data_i[1]=apb3Router_1.io_input_PWDATA[7] data_i[0]=$undef q_o[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[0] q_o[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[1] q_o[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[2] q_o[5]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[3] q_o[4]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[4] q_o[3]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[5] q_o[2]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[6] q_o[1]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4558[8] raddr_i[9]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] raddr_i[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] raddr_i[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] raddr_i[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] raddr_i[5]=$false raddr_i[4]=$false raddr_i[3]=$false raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire waddr_i[9]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] waddr_i[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] waddr_i[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] waddr_i[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] waddr_i[5]=$false waddr_i[4]=$false waddr_i[3]=$false waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] data_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] data_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] data_i[5]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] data_i[4]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] data_i[3]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] data_i[2]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] data_i[1]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] data_i[0]=$undef q_o[8]=system_uartCtrl.bridge_read_streamBreaked_payload[0] q_o[7]=system_uartCtrl.bridge_read_streamBreaked_payload[1] q_o[6]=system_uartCtrl.bridge_read_streamBreaked_payload[2] q_o[5]=system_uartCtrl.bridge_read_streamBreaked_payload[3] q_o[4]=system_uartCtrl.bridge_read_streamBreaked_payload[4] q_o[3]=system_uartCtrl.bridge_read_streamBreaked_payload[5] q_o[2]=system_uartCtrl.bridge_read_streamBreaked_payload[6] q_o[1]=system_uartCtrl.bridge_read_streamBreaked_payload[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4560[8] raddr_i[9]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] raddr_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] raddr_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] raddr_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] raddr_i[5]=$false raddr_i[4]=$false raddr_i[3]=$false raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire waddr_i[9]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] waddr_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] waddr_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] waddr_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] waddr_i[5]=$false waddr_i[4]=$false waddr_i[3]=$false waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 +.names system_timer.prescaler_1.counter[1] $auto$alumacc.cc:485:replace_alu$4095.X[1] +1 1 +.names system_timer.prescaler_1.counter[2] $auto$alumacc.cc:485:replace_alu$4095.X[2] +1 1 +.names system_timer.prescaler_1.counter[3] $auto$alumacc.cc:485:replace_alu$4095.X[3] +1 1 +.names system_timer.prescaler_1.counter[4] $auto$alumacc.cc:485:replace_alu$4095.X[4] +1 1 +.names system_timer.prescaler_1.counter[5] $auto$alumacc.cc:485:replace_alu$4095.X[5] +1 1 +.names system_timer.prescaler_1.counter[6] $auto$alumacc.cc:485:replace_alu$4095.X[6] +1 1 +.names system_timer.prescaler_1.counter[7] $auto$alumacc.cc:485:replace_alu$4095.X[7] +1 1 +.names system_timer.prescaler_1.counter[8] $auto$alumacc.cc:485:replace_alu$4095.X[8] +1 1 +.names system_timer.prescaler_1.counter[9] $auto$alumacc.cc:485:replace_alu$4095.X[9] +1 1 +.names system_timer.prescaler_1.counter[10] $auto$alumacc.cc:485:replace_alu$4095.X[10] +1 1 +.names system_timer.prescaler_1.counter[11] $auto$alumacc.cc:485:replace_alu$4095.X[11] +1 1 +.names system_timer.prescaler_1.counter[12] $auto$alumacc.cc:485:replace_alu$4095.X[12] +1 1 +.names system_timer.prescaler_1.counter[13] $auto$alumacc.cc:485:replace_alu$4095.X[13] +1 1 +.names system_timer.prescaler_1.counter[14] $auto$alumacc.cc:485:replace_alu$4095.X[14] +1 1 +.names system_timer.prescaler_1.counter[15] $auto$alumacc.cc:485:replace_alu$4095.X[15] +1 1 +.names $auto$alumacc.cc:485:replace_alu$4095.X[0] $auto$alumacc.cc:485:replace_alu$4095.Y[0] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$4542[0] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$4542[1] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$4542[2] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$4542[3] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$4542[4] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$4542[5] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$4542[6] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$4542[7] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$4542[8] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$4542[9] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$4542[10] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$4542[11] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$4542[12] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$4542[13] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$4542[14] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$4542[15] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$4542[16] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$4542[17] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$4542[18] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$4542[19] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$4542[20] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$4542[21] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$4542[22] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$4542[23] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$4542[24] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$4542[25] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$4542[26] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$4542[27] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$4542[28] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$4542[29] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$4542[30] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$4542[31] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$4543[0] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$4543[1] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$4543[2] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$4543[3] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$4543[4] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[5] $auto$memory_bram.cc:844:replace_memory$4543[5] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[6] $auto$memory_bram.cc:844:replace_memory$4543[6] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[7] $auto$memory_bram.cc:844:replace_memory$4543[7] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[8] $auto$memory_bram.cc:844:replace_memory$4543[8] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[9] $auto$memory_bram.cc:844:replace_memory$4543[9] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[10] $auto$memory_bram.cc:844:replace_memory$4543[10] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[11] $auto$memory_bram.cc:844:replace_memory$4543[11] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[12] $auto$memory_bram.cc:844:replace_memory$4543[12] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[13] $auto$memory_bram.cc:844:replace_memory$4543[13] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[14] $auto$memory_bram.cc:844:replace_memory$4543[14] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[15] $auto$memory_bram.cc:844:replace_memory$4543[15] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[16] $auto$memory_bram.cc:844:replace_memory$4543[16] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[17] $auto$memory_bram.cc:844:replace_memory$4543[17] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[18] $auto$memory_bram.cc:844:replace_memory$4543[18] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[19] $auto$memory_bram.cc:844:replace_memory$4543[19] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[20] $auto$memory_bram.cc:844:replace_memory$4543[20] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[21] $auto$memory_bram.cc:844:replace_memory$4543[21] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[22] $auto$memory_bram.cc:844:replace_memory$4543[22] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[23] $auto$memory_bram.cc:844:replace_memory$4543[23] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[24] $auto$memory_bram.cc:844:replace_memory$4543[24] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[25] $auto$memory_bram.cc:844:replace_memory$4543[25] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[26] $auto$memory_bram.cc:844:replace_memory$4543[26] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[27] $auto$memory_bram.cc:844:replace_memory$4543[27] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[28] $auto$memory_bram.cc:844:replace_memory$4543[28] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[29] $auto$memory_bram.cc:844:replace_memory$4543[29] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[30] $auto$memory_bram.cc:844:replace_memory$4543[30] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[31] $auto$memory_bram.cc:844:replace_memory$4543[31] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[0] $auto$memory_bram.cc:844:replace_memory$4558[0] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[1] $auto$memory_bram.cc:844:replace_memory$4558[1] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[2] $auto$memory_bram.cc:844:replace_memory$4558[2] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[3] $auto$memory_bram.cc:844:replace_memory$4558[3] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[4] $auto$memory_bram.cc:844:replace_memory$4558[4] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[5] $auto$memory_bram.cc:844:replace_memory$4558[5] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[6] $auto$memory_bram.cc:844:replace_memory$4558[6] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[7] $auto$memory_bram.cc:844:replace_memory$4558[7] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[0] $auto$memory_bram.cc:844:replace_memory$4560[0] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[1] $auto$memory_bram.cc:844:replace_memory$4560[1] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[2] $auto$memory_bram.cc:844:replace_memory$4560[2] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[3] $auto$memory_bram.cc:844:replace_memory$4560[3] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[4] $auto$memory_bram.cc:844:replace_memory$4560[4] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[5] $auto$memory_bram.cc:844:replace_memory$4560[5] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[6] $auto$memory_bram.cc:844:replace_memory$4560[6] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[7] $auto$memory_bram.cc:844:replace_memory$4560[7] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l347 apb3Router_1.io_input_PWDATA[0] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l347_1 apb3Router_1.io_input_PWDATA[1] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l347_2 apb3Router_1.io_input_PWDATA[9] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l379 apb3Router_1.io_input_PWDATA[10] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l347_3 apb3Router_1.io_input_PWDATA[11] +1 1 +.names jtagBridge_1.jtag_idcodeArea_ctrl_tdo jtagBridge_1.jtag_idcodeArea_shifter[0] +1 1 +.names jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.jtag_readArea_full_shifter[0] +1 1 +.names jtagBridge_1.jtag_tap_tdoIr jtagBridge_1.jtag_tap_instructionShift[0] +1 1 +.names system_cpu.when_DebugPlugin_l284 systemDebugger_1._zz_io_mem_cmd_payload_address[48] +1 1 +.names system_cpu.when_DebugPlugin_l285 systemDebugger_1._zz_io_mem_cmd_payload_address[49] +1 1 +.names system_cpu.when_DebugPlugin_l288 systemDebugger_1._zz_io_mem_cmd_payload_address[50] +1 1 +.names system_cpu.when_DebugPlugin_l284_1 systemDebugger_1._zz_io_mem_cmd_payload_address[56] +1 1 +.names system_cpu.when_DebugPlugin_l285_1 systemDebugger_1._zz_io_mem_cmd_payload_address[57] +1 1 +.names system_cpu.when_DebugPlugin_l288_1 systemDebugger_1._zz_io_mem_cmd_payload_address[58] +1 1 +.names systemDebugger_1.io_mem_cmd_payload_wr systemDebugger_1._zz_io_mem_cmd_payload_address[64] +1 1 +.names $false system_cpu.BranchPlugin_jumpInterface_payload[0] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[13] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[14] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[15] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[16] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[17] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[18] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[19] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[20] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[21] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[22] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[23] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[24] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[25] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[26] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[27] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[28] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[29] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[30] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[31] +1 1 +.names $true system_cpu.CsrPlugin_interrupt_code[0] +1 1 +.names $true system_cpu.CsrPlugin_interrupt_code[1] +1 1 +.names $true system_cpu.CsrPlugin_mcause_exceptionCode[0] +1 1 +.names $true system_cpu.CsrPlugin_mcause_exceptionCode[1] +1 1 +.names $false system_cpu.CsrPlugin_mepc[0] +1 1 +.names $false system_cpu.CsrPlugin_mepc[1] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[5] system_cpu.DebugPlugin_busReadDataReg[5] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[6] system_cpu.DebugPlugin_busReadDataReg[6] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[7] system_cpu.DebugPlugin_busReadDataReg[7] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[8] system_cpu.DebugPlugin_busReadDataReg[8] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[9] system_cpu.DebugPlugin_busReadDataReg[9] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[10] system_cpu.DebugPlugin_busReadDataReg[10] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[11] system_cpu.DebugPlugin_busReadDataReg[11] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[12] system_cpu.DebugPlugin_busReadDataReg[12] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[13] system_cpu.DebugPlugin_busReadDataReg[13] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[14] system_cpu.DebugPlugin_busReadDataReg[14] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[15] system_cpu.DebugPlugin_busReadDataReg[15] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[16] system_cpu.DebugPlugin_busReadDataReg[16] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[17] system_cpu.DebugPlugin_busReadDataReg[17] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[18] system_cpu.DebugPlugin_busReadDataReg[18] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[19] system_cpu.DebugPlugin_busReadDataReg[19] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[20] system_cpu.DebugPlugin_busReadDataReg[20] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[21] system_cpu.DebugPlugin_busReadDataReg[21] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[22] system_cpu.DebugPlugin_busReadDataReg[22] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[23] system_cpu.DebugPlugin_busReadDataReg[23] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[24] system_cpu.DebugPlugin_busReadDataReg[24] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[25] system_cpu.DebugPlugin_busReadDataReg[25] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[26] system_cpu.DebugPlugin_busReadDataReg[26] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[27] system_cpu.DebugPlugin_busReadDataReg[27] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[28] system_cpu.DebugPlugin_busReadDataReg[28] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[29] system_cpu.DebugPlugin_busReadDataReg[29] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[30] system_cpu.DebugPlugin_busReadDataReg[30] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[31] system_cpu.DebugPlugin_busReadDataReg[31] +1 1 +.names $false system_cpu.IBusSimplePlugin_cmd_payload_pc[0] +1 1 +.names $false system_cpu.IBusSimplePlugin_cmd_payload_pc[1] +1 1 +.names $false system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[0] +1 1 +.names $false system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[1] +1 1 +.names $false system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[0] +1 1 +.names $false system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[1] +1 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] +1 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] +1 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] +1 1 +.names system_cpu._zz_decode_SRC2 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] +1 1 +.names system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[12] +1 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[19] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[4] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[5] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[6] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[7] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[8] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[9] +1 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[11] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu._zz_lastStageRegFileWrite_payload_address[7] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu._zz_lastStageRegFileWrite_payload_address[8] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu._zz_lastStageRegFileWrite_payload_address[9] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu._zz_lastStageRegFileWrite_payload_address[10] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] system_cpu._zz_lastStageRegFileWrite_payload_address[11] +1 1 +.names $undef system_cpu._zz_lastStageRegFileWrite_payload_address[30] +1 1 +.names $undef system_cpu._zz_lastStageRegFileWrite_payload_address[31] +1 1 +.names $false system_cpu.decode_to_execute_PC[0] +1 1 +.names $false system_cpu.decode_to_execute_PC[1] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[0] system_cpu.decode_to_execute_RS2[0] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[1] system_cpu.decode_to_execute_RS2[1] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[2] system_cpu.decode_to_execute_RS2[2] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[3] system_cpu.decode_to_execute_RS2[3] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[4] system_cpu.decode_to_execute_RS2[4] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[5] system_cpu.decode_to_execute_RS2[5] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[6] system_cpu.decode_to_execute_RS2[6] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[7] system_cpu.decode_to_execute_RS2[7] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[0] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[1] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[2] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[3] +1 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[0] +1 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[1] +1 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[2] +1 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[3] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif new file mode 100644 index 00000000000..07d5fccecba --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif @@ -0,0 +1,574 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model PWM +.inputs clk RxD +.outputs PWM_out +.names $false +.names $true +1 +.names $undef +.names deserializer.RxD_data_ready RxD_data_reg[6] deserializer.RxD_data[6] $abc$1877$auto$rtlil.cc:2693:MuxGate$1591 +010 1 +011 1 +101 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[5] RxD_data_reg[5] $abc$1877$auto$rtlil.cc:2693:MuxGate$1593 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[4] RxD_data_reg[4] $abc$1877$auto$rtlil.cc:2693:MuxGate$1595 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[3] RxD_data_reg[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1597 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[2] RxD_data_reg[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1599 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[1] RxD_data_reg[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1601 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[0] RxD_data_reg[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1603 +001 1 +011 1 +110 1 +111 1 +.names deserializer.OversamplingTick deserializer.Filter_cnt[0] deserializer.Filter_cnt[1] deserializer.RxD_sync[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1605 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[7] deserializer.RxD_data[6] $abc$1877$auto$rtlil.cc:2693:MuxGate$1607 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_state[3] $abc$1877$new_n114 $abc$1877$new_n113 +11 1 +.names deserializer.OversamplingCnt[1] deserializer.OversamplingCnt[0] deserializer.OversamplingTick deserializer.OversamplingCnt[2] $abc$1877$new_n114 +1110 1 +.names $abc$1877$new_n113 deserializer.RxD_data[6] deserializer.RxD_data[5] $abc$1877$auto$rtlil.cc:2693:MuxGate$1609 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[5] deserializer.RxD_data[4] $abc$1877$auto$rtlil.cc:2693:MuxGate$1611 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[4] deserializer.RxD_data[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1613 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[3] deserializer.RxD_data[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1615 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[2] deserializer.RxD_data[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1617 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[1] deserializer.RxD_data[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1619 +001 1 +011 1 +110 1 +111 1 +.names deserializer.OversamplingCnt[1] deserializer.OversamplingCnt[0] deserializer.OversamplingTick $abc$1877$new_n122 $abc$1877$auto$rtlil.cc:2693:MuxGate$1623 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +.names $abc$1877$new_n123 deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n122 +100 1 +.names deserializer.RxD_state[3] deserializer.RxD_state[2] $abc$1877$new_n123 +00 1 +.names deserializer.OversamplingTick deserializer.OversamplingCnt[0] $abc$1877$new_n122 $abc$1877$auto$rtlil.cc:2693:MuxGate$1627 +010 1 +011 1 +100 1 +.names deserializer.RxD_state[1] deserializer.RxD_state[3] deserializer.RxD_state[0] $abc$1877$new_n126 deserializer.RxD_state[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1629 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$1877$new_n127 $abc$1877$new_n114 deserializer.RxD_state[3] $abc$1877$new_n126 +100 1 +110 1 +111 1 +.names $abc$1877$new_n123 deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n114 deserializer.RxD_bit $abc$1877$new_n127 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$1877$new_n126 deserializer.RxD_state[0] $abc$1877$new_n122 deserializer.RxD_state[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1631 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names deserializer.OversamplingTick RxD deserializer.RxD_sync[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1633 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[7] RxD_data_reg[7] $abc$1877$auto$rtlil.cc:2693:MuxGate$1635 +001 1 +011 1 +110 1 +111 1 +.names deserializer.OversamplingTick deserializer.RxD_sync[0] deserializer.RxD_sync[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1637 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_bit deserializer.Filter_cnt[1] deserializer.OversamplingTick deserializer.Filter_cnt[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1641 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserializer.Filter_cnt[1] deserializer.RxD_sync[1] deserializer.OversamplingTick deserializer.Filter_cnt[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1643 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserializer.OversamplingCnt[2] $abc$1877$new_n122 deserializer.OversamplingCnt[0] deserializer.OversamplingCnt[1] deserializer.OversamplingTick $abc$1877$auto$rtlil.cc:2693:MuxGate$1647 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$1877$new_n113 deserializer.RxD_bit deserializer.RxD_data[7] $abc$1877$auto$rtlil.cc:2693:MuxGate$1649 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_state[3] deserializer.RxD_state[2] $abc$1877$new_n137 $abc$1877$new_n114 $abc$1877$auto$rtlil.cc:2693:MuxGate$1653 +1011 1 +1100 1 +1101 1 +1110 1 +.names deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n137 +11 1 +.names $abc$1877$new_n139 deserializer.RxD_state[3] $abc$1877$new_n114 $abc$1877$auto$rtlil.cc:2693:MuxGate$1655 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$1877$new_n127 deserializer.RxD_state[3] deserializer.RxD_state[0] deserializer.RxD_state[2] deserializer.RxD_state[1] $abc$1877$new_n139 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names deserializer.RxD_bit $abc$1877$new_n114 deserializer.RxD_state[1] $abc$1877$new_n123 deserializer.RxD_state[0] $abc$1877$flatten\deserializer.$0\RxD_data_ready[0:0] +11110 1 +.names PWM_accumulator[1] RxD_data_reg[1] PWM_accumulator[0] RxD_data_reg[0] $auto$alumacc.cc:485:replace_alu$579.Y[1] +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names PWM_accumulator[2] RxD_data_reg[2] $abc$1877$new_n143 $auto$alumacc.cc:485:replace_alu$579.Y[2] +000 1 +011 1 +101 1 +110 1 +.names RxD_data_reg[0] PWM_accumulator[0] PWM_accumulator[1] RxD_data_reg[1] $abc$1877$new_n143 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names PWM_accumulator[3] RxD_data_reg[3] PWM_accumulator[2] RxD_data_reg[2] $abc$1877$new_n143 $auto$alumacc.cc:485:replace_alu$579.Y[3] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names PWM_accumulator[4] RxD_data_reg[4] $abc$1877$new_n146 $auto$alumacc.cc:485:replace_alu$579.Y[4] +000 1 +011 1 +101 1 +110 1 +.names PWM_accumulator[2] RxD_data_reg[2] PWM_accumulator[3] RxD_data_reg[3] $abc$1877$new_n143 $abc$1877$new_n146 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names PWM_accumulator[5] RxD_data_reg[5] PWM_accumulator[4] RxD_data_reg[4] $abc$1877$new_n146 $auto$alumacc.cc:485:replace_alu$579.Y[5] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names PWM_accumulator[6] RxD_data_reg[6] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.Y[6] +000 1 +011 1 +101 1 +110 1 +.names PWM_accumulator[4] RxD_data_reg[4] PWM_accumulator[5] RxD_data_reg[5] $abc$1877$new_n146 $abc$1877$new_n149 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names PWM_accumulator[7] RxD_data_reg[7] PWM_accumulator[6] RxD_data_reg[6] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.Y[7] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names PWM_accumulator[0] RxD_data_reg[0] $auto$alumacc.cc:485:replace_alu$579.X[0] +01 1 +10 1 +.names deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[1] +00 1 +11 1 +.names deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[2] +000 1 +101 1 +110 1 +111 1 +.names deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[3] +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names deserializer.tickgen.Acc[8] deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[4] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[5] +00 1 +11 1 +.names deserializer.tickgen.Acc[8] deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $abc$1877$new_n157 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[6] +010 1 +100 1 +101 1 +111 1 +.names deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1110 1 +.names deserializer.tickgen.Acc[12] deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[8] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[9] +01 1 +10 1 +.names deserializer.tickgen.Acc[12] deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $abc$1877$new_n162 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[10] +011 1 +100 1 +101 1 +110 1 +.names deserializer.tickgen.Acc[15] deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PWM_accumulator[6] RxD_data_reg[6] PWM_accumulator[7] RxD_data_reg[7] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.CO[7] +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserializer.tickgen.Acc[15] deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.CO[11] +1111 1 +.names deserializer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$591.X[0] +0 1 +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1641 Q=deserializer.RxD_bit +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1605 Q=deserializer.Filter_cnt[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1643 Q=deserializer.Filter_cnt[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1603 Q=RxD_data_reg[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1601 Q=RxD_data_reg[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1599 Q=RxD_data_reg[2] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1597 Q=RxD_data_reg[3] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1595 Q=RxD_data_reg[4] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1593 Q=RxD_data_reg[5] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1591 Q=RxD_data_reg[6] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1635 Q=RxD_data_reg[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.X[0] Q=PWM_accumulator[0] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[1] Q=PWM_accumulator[1] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[2] Q=PWM_accumulator[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[3] Q=PWM_accumulator[3] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[4] Q=PWM_accumulator[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[5] Q=PWM_accumulator[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[6] Q=PWM_accumulator[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[7] Q=PWM_accumulator[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.CO[7] Q=PWM_out +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1633 Q=deserializer.RxD_sync[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1637 Q=deserializer.RxD_sync[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1631 Q=deserializer.RxD_state[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1629 Q=deserializer.RxD_state[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1655 Q=deserializer.RxD_state[3] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1653 Q=deserializer.RxD_state[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.X[0] Q=deserializer.tickgen.Acc[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[1] Q=deserializer.tickgen.Acc[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[2] Q=deserializer.tickgen.Acc[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[3] Q=deserializer.tickgen.Acc[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[4] Q=deserializer.tickgen.Acc[8] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[5] Q=deserializer.tickgen.Acc[9] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[6] Q=deserializer.tickgen.Acc[10] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[7] Q=deserializer.tickgen.Acc[11] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[8] Q=deserializer.tickgen.Acc[12] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[9] Q=deserializer.tickgen.Acc[13] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[10] Q=deserializer.tickgen.Acc[14] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[11] Q=deserializer.tickgen.Acc[15] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.CO[11] Q=deserializer.OversamplingTick +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1627 Q=deserializer.OversamplingCnt[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1623 Q=deserializer.OversamplingCnt[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1647 Q=deserializer.OversamplingCnt[2] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1619 Q=deserializer.RxD_data[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1617 Q=deserializer.RxD_data[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1615 Q=deserializer.RxD_data[2] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1613 Q=deserializer.RxD_data[3] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1611 Q=deserializer.RxD_data[4] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1609 Q=deserializer.RxD_data[5] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1607 Q=deserializer.RxD_data[6] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1649 Q=deserializer.RxD_data[7] +.subckt dff C=clk D=$abc$1877$flatten\deserializer.$0\RxD_data_ready[0:0] Q=deserializer.RxD_data_ready +.names deserializer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$591.CO[0] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$591.CO[12] +1 1 +.names $auto$alumacc.cc:485:replace_alu$591.X[0] $auto$alumacc.cc:485:replace_alu$591.Y[0] +1 1 +.names $auto$alumacc.cc:485:replace_alu$591.CO[11] $auto$alumacc.cc:485:replace_alu$591.Y[12] +1 1 +.names deserializer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$591.X[3] +1 1 +.names deserializer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$591.X[5] +1 1 +.names deserializer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$591.X[6] +1 1 +.names deserializer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$591.X[8] +1 1 +.names deserializer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$591.X[9] +1 1 +.names deserializer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$591.X[10] +1 1 +.names deserializer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$591.X[11] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$591.X[12] +1 1 +.names PWM_out PWM_accumulator[8] +1 1 +.names deserializer.OversamplingTick deserializer.tickgen.Acc[16] +1 1 +.names $auto$alumacc.cc:485:replace_alu$579.X[0] $auto$alumacc.cc:485:replace_alu$579.Y[0] +1 1 +.names $auto$alumacc.cc:485:replace_alu$579.CO[7] $auto$alumacc.cc:485:replace_alu$579.Y[8] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$579.X[8] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$579.CO[8] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif new file mode 100644 index 00000000000..dad3d8629d9 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif @@ -0,0 +1,204 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model PushButton_Debouncer +.inputs clk PB +.outputs PB_state PB_down PB_up +.names $false +.names $true +1 +.names $undef +.names $abc$913$new_n43 PB_sync_1 PB_state $abc$913$auto$rtlil.cc:2693:MuxGate$832 +001 1 +011 1 +110 1 +111 1 +.names PB_cnt[15] PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $abc$913$new_n43 +1111 1 +.names PB_cnt[12] PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $abc$913$new_n44 +11111 1 +.names PB_cnt[8] PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $abc$913$new_n45 +11111 1 +.names PB_cnt[4] PB_cnt[1] PB_cnt[0] PB_cnt[3] PB_cnt[2] $abc$913$new_n46 +11111 1 +.names PB_sync_1 PB_state PB_idle +00 1 +11 1 +.names PB_sync_1 $abc$913$new_n43 PB_state PB_down +110 1 +.names $abc$913$new_n43 PB_state PB_sync_1 PB_up +110 1 +.names PB_cnt[1] PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.Y[1] +01 1 +10 1 +.names PB_cnt[2] PB_cnt[1] PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.Y[2] +011 1 +100 1 +101 1 +110 1 +.names PB_cnt[3] PB_cnt[1] PB_cnt[0] PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PB_cnt[4] PB_cnt[1] PB_cnt[0] PB_cnt[3] PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[5] +01 1 +10 1 +.names PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[6] +011 1 +100 1 +101 1 +110 1 +.names PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PB_cnt[8] PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[9] +01 1 +10 1 +.names PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[10] +011 1 +100 1 +101 1 +110 1 +.names PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PB_cnt[12] PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[13] +01 1 +10 1 +.names PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[14] +011 1 +100 1 +101 1 +110 1 +.names PB_cnt[15] PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PB $0\PB_sync_0[0:0] +0 1 +.names PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.X[0] +0 1 +.subckt dff C=clk D=$abc$913$auto$rtlil.cc:2693:MuxGate$832 Q=PB_state +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.X[0] Q=PB_cnt[0] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[1] Q=PB_cnt[1] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[2] Q=PB_cnt[2] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[3] Q=PB_cnt[3] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[4] Q=PB_cnt[4] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[5] Q=PB_cnt[5] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[6] Q=PB_cnt[6] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[7] Q=PB_cnt[7] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[8] Q=PB_cnt[8] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[9] Q=PB_cnt[9] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[10] Q=PB_cnt[10] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[11] Q=PB_cnt[11] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[12] Q=PB_cnt[12] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[13] Q=PB_cnt[13] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[14] Q=PB_cnt[14] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[15] Q=PB_cnt[15] R=PB_idle +.subckt dff C=clk D=PB_sync_0 Q=PB_sync_1 +.subckt dff C=clk D=$0\PB_sync_0[0:0] Q=PB_sync_0 +.names $auto$alumacc.cc:485:replace_alu$424.X[0] $auto$alumacc.cc:485:replace_alu$424.Y[0] +1 1 +.names PB_cnt[1] $auto$alumacc.cc:485:replace_alu$424.X[1] +1 1 +.names PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.X[2] +1 1 +.names PB_cnt[3] $auto$alumacc.cc:485:replace_alu$424.X[3] +1 1 +.names PB_cnt[4] $auto$alumacc.cc:485:replace_alu$424.X[4] +1 1 +.names PB_cnt[5] $auto$alumacc.cc:485:replace_alu$424.X[5] +1 1 +.names PB_cnt[6] $auto$alumacc.cc:485:replace_alu$424.X[6] +1 1 +.names PB_cnt[7] $auto$alumacc.cc:485:replace_alu$424.X[7] +1 1 +.names PB_cnt[8] $auto$alumacc.cc:485:replace_alu$424.X[8] +1 1 +.names PB_cnt[9] $auto$alumacc.cc:485:replace_alu$424.X[9] +1 1 +.names PB_cnt[10] $auto$alumacc.cc:485:replace_alu$424.X[10] +1 1 +.names PB_cnt[11] $auto$alumacc.cc:485:replace_alu$424.X[11] +1 1 +.names PB_cnt[12] $auto$alumacc.cc:485:replace_alu$424.X[12] +1 1 +.names PB_cnt[13] $auto$alumacc.cc:485:replace_alu$424.X[13] +1 1 +.names PB_cnt[14] $auto$alumacc.cc:485:replace_alu$424.X[14] +1 1 +.names PB_cnt[15] $auto$alumacc.cc:485:replace_alu$424.X[15] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif new file mode 100644 index 00000000000..8cf4e1f6f4d --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif @@ -0,0 +1,735 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model RCServo +.inputs clk RxD +.outputs RCServo_pulse +.names $false +.names $true +1 +.names $undef +.names deserialer.RxD_data_ready RxD_data_reg[5] deserialer.RxD_data[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$1953 +010 1 +011 1 +101 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[4] RxD_data_reg[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$1955 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[3] RxD_data_reg[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1957 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[2] RxD_data_reg[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1959 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[1] RxD_data_reg[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1961 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[0] RxD_data_reg[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$1963 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingTick deserialer.Filter_cnt[0] deserialer.Filter_cnt[1] deserialer.RxD_sync[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1965 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[7] deserialer.RxD_data[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$1967 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_state[3] $abc$2311$new_n153 $abc$2311$new_n152 +11 1 +.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick deserialer.OversamplingCnt[2] $abc$2311$new_n153 +1110 1 +.names $abc$2311$new_n152 deserialer.RxD_data[6] deserialer.RxD_data[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$1969 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[5] deserialer.RxD_data[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$1971 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[4] deserialer.RxD_data[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1973 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[3] deserialer.RxD_data[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1975 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[2] deserialer.RxD_data[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1977 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[1] deserialer.RxD_data[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$1979 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick $abc$2311$new_n161 $abc$2311$auto$rtlil.cc:2693:MuxGate$1983 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$2311$new_n161 +0000 1 +.names deserialer.OversamplingTick deserialer.OversamplingCnt[0] $abc$2311$new_n161 $abc$2311$auto$rtlil.cc:2693:MuxGate$1987 +010 1 +011 1 +100 1 +.names deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$2311$new_n164 deserialer.RxD_state[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1989 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$2311$new_n165 $abc$2311$new_n161 deserialer.RxD_bit $abc$2311$new_n164 +000 1 +001 1 +010 1 +.names $abc$2311$new_n153 deserialer.RxD_state[0] deserialer.RxD_state[1] deserialer.RxD_state[2] deserialer.RxD_state[3] $abc$2311$new_n165 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names $abc$2311$new_n164 deserialer.RxD_state[0] $abc$2311$new_n161 deserialer.RxD_state[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1991 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names PulseCount[10] PulseCount[9] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$1993 +011 1 +100 1 +101 1 +110 1 +.names PulseCount[8] $abc$2311$new_n169 $abc$2311$new_n168 +11 1 +.names PulseCount[4] PulseCount[5] PulseCount[6] PulseCount[7] $abc$2311$new_n170 $abc$2311$new_n169 +11111 1 +.names PulseCount[0] PulseCount[1] PulseCount[2] PulseCount[3] ClkTick $abc$2311$new_n170 +11111 1 +.names PulseCount[9] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$1995 +01 1 +10 1 +.names PulseCount[8] $abc$2311$new_n169 $abc$2311$auto$rtlil.cc:2693:MuxGate$1997 +01 1 +10 1 +.names PulseCount[7] PulseCount[4] PulseCount[5] PulseCount[6] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$1999 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PulseCount[6] PulseCount[4] PulseCount[5] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2001 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PulseCount[5] PulseCount[4] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2003 +011 1 +100 1 +101 1 +110 1 +.names PulseCount[4] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2005 +01 1 +10 1 +.names PulseCount[3] PulseCount[0] PulseCount[1] PulseCount[2] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2007 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PulseCount[2] PulseCount[0] PulseCount[1] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2009 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PulseCount[1] PulseCount[0] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2011 +011 1 +100 1 +101 1 +110 1 +.names PulseCount[0] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2013 +01 1 +10 1 +.names $abc$2311$new_n182 RxD_data_reg[6] RCServo_position[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$2015 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n183 PulseCount[2] PulseCount[3] PulseCount[4] PulseCount[5] $abc$2311$new_n182 +10000 1 +.names $abc$2311$new_n184 PulseCount[0] PulseCount[1] PulseCount[6] PulseCount[7] $abc$2311$new_n183 +10000 1 +.names PulseCount[11] PulseCount[8] PulseCount[9] PulseCount[10] $abc$2311$new_n184 +0000 1 +.names $abc$2311$new_n182 RxD_data_reg[5] RCServo_position[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$2017 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[4] RCServo_position[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$2019 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[3] RCServo_position[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$2021 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[2] RCServo_position[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$2023 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[1] RCServo_position[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2025 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[0] RCServo_position[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2027 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingTick RxD deserialer.RxD_sync[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2029 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[7] RxD_data_reg[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2031 +001 1 +011 1 +110 1 +111 1 +.names PulseCount[11] PulseCount[9] PulseCount[10] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$2033 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$2311$new_n182 RxD_data_reg[7] RCServo_position[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2035 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingTick deserialer.RxD_sync[0] deserialer.RxD_sync[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2037 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_bit deserialer.Filter_cnt[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2041 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserialer.Filter_cnt[1] deserialer.RxD_sync[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2043 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserialer.OversamplingCnt[2] $abc$2311$new_n161 deserialer.OversamplingCnt[0] deserialer.OversamplingCnt[1] deserialer.OversamplingTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2047 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$2311$new_n152 deserialer.RxD_bit deserialer.RxD_data[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2049 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_state[2] deserialer.RxD_state[3] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$2311$new_n164 $abc$2311$auto$rtlil.cc:2693:MuxGate$2053 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$2311$new_n164 deserialer.RxD_state[2] deserialer.RxD_state[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2055 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[6] RxD_data_reg[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$2057 +001 1 +011 1 +110 1 +111 1 +.names ClkCount[5] $abc$2311$new_n204 ClkCount[4] ClkCount[3] $0\ClkTick[0:0] +1100 1 +.names ClkCount[6] ClkCount[2] ClkCount[1] ClkCount[0] $abc$2311$new_n204 +1000 1 +.names $abc$2311$new_n206 $abc$2311$new_n153 $abc$2311$flatten\deserialer.$0\RxD_data_ready[0:0] +11 1 +.names deserialer.RxD_bit deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] $abc$2311$new_n206 +11000 1 +.names PulseCount[2] RCServo_position[2] RCServo_position[3] PulseCount[3] $abc$2311$new_n210 $abc$2311$new_n209 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names PulseCount[0] RCServo_position[0] RCServo_position[1] PulseCount[1] $abc$2311$new_n210 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$2311$new_n212 RCServo_position[4] PulseCount[4] RCServo_position[5] PulseCount[5] $abc$2311$new_n211 +10000 1 +10011 1 +11100 1 +11111 1 +.names PulseCount[6] RCServo_position[6] RCServo_position[7] PulseCount[7] $abc$2311$new_n212 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$2311$new_n214 $abc$2311$new_n212 $abc$2311$new_n215 PulseCount[5] RCServo_position[5] $abc$2311$new_n213 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names RCServo_position[6] RCServo_position[7] PulseCount[6] PulseCount[7] $abc$2311$new_n214 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names RCServo_position[5] PulseCount[5] RCServo_position[4] PulseCount[4] $abc$2311$new_n215 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names RCServo_position[2] PulseCount[2] RCServo_position[3] PulseCount[3] $abc$2311$new_n217 +0000 1 +0011 1 +1100 1 +1111 1 +.names RCServo_position[0] PulseCount[0] RCServo_position[1] PulseCount[1] $abc$2311$new_n218 +0000 1 +0011 1 +1100 1 +1111 1 +.names ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[1] +01 1 +10 1 +.names ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[2] +011 1 +100 1 +101 1 +110 1 +.names ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ClkCount[4] ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names ClkCount[5] $abc$2311$new_n224 $auto$alumacc.cc:485:replace_alu$613.Y[5] +01 1 +10 1 +.names ClkCount[4] ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $abc$2311$new_n224 +11111 1 +.names ClkCount[6] ClkCount[5] $abc$2311$new_n224 $auto$alumacc.cc:485:replace_alu$613.Y[6] +011 1 +100 1 +101 1 +110 1 +.names deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.Y[1] +00 1 +11 1 +.names deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.Y[2] +000 1 +101 1 +110 1 +111 1 +.names deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $auto$alumacc.cc:485:replace_alu$628.Y[3] +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $auto$alumacc.cc:485:replace_alu$628.Y[4] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[5] +00 1 +11 1 +.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $abc$2311$new_n231 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[6] +010 1 +100 1 +101 1 +111 1 +.names deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1110 1 +.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[8] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[9] +01 1 +10 1 +.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $abc$2311$new_n236 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[10] +011 1 +100 1 +101 1 +110 1 +.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.CO[11] +1111 1 +.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.X[0] +0 1 +.names ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.X[0] +0 1 +.names $abc$2311$new_n211 $abc$2311$new_n213 $abc$2311$new_n209 $abc$2311$new_n218 $abc$2311$new_n217 $abc$2311$new_n242 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names PulseCount[9] PulseCount[11] PulseCount[10] PulseCount[8] $abc$2311$new_n242 $0\RCServo_pulse[0:0] +00000 1 +00001 1 +00010 1 +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.X[0] Q=deserialer.tickgen.Acc[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[1] Q=deserialer.tickgen.Acc[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[2] Q=deserialer.tickgen.Acc[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[3] Q=deserialer.tickgen.Acc[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[4] Q=deserialer.tickgen.Acc[8] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[5] Q=deserialer.tickgen.Acc[9] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[6] Q=deserialer.tickgen.Acc[10] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[7] Q=deserialer.tickgen.Acc[11] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[8] Q=deserialer.tickgen.Acc[12] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[9] Q=deserialer.tickgen.Acc[13] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[10] Q=deserialer.tickgen.Acc[14] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[11] Q=deserialer.tickgen.Acc[15] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.CO[11] Q=deserialer.OversamplingTick +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1987 Q=deserialer.OversamplingCnt[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1983 Q=deserialer.OversamplingCnt[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2047 Q=deserialer.OversamplingCnt[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1979 Q=deserialer.RxD_data[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1977 Q=deserialer.RxD_data[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1975 Q=deserialer.RxD_data[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1973 Q=deserialer.RxD_data[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1971 Q=deserialer.RxD_data[4] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1969 Q=deserialer.RxD_data[5] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1967 Q=deserialer.RxD_data[6] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2049 Q=deserialer.RxD_data[7] +.subckt dff C=clk D=$abc$2311$flatten\deserialer.$0\RxD_data_ready[0:0] Q=deserialer.RxD_data_ready +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.X[0] Q=ClkCount[0] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[1] Q=ClkCount[1] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[2] Q=ClkCount[2] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[3] Q=ClkCount[3] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[4] Q=ClkCount[4] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[5] Q=ClkCount[5] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[6] Q=ClkCount[6] R=ClkTick +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2041 Q=deserialer.RxD_bit +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1965 Q=deserialer.Filter_cnt[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2043 Q=deserialer.Filter_cnt[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1963 Q=RxD_data_reg[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1961 Q=RxD_data_reg[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1959 Q=RxD_data_reg[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1957 Q=RxD_data_reg[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1955 Q=RxD_data_reg[4] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1953 Q=RxD_data_reg[5] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2057 Q=RxD_data_reg[6] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2031 Q=RxD_data_reg[7] +.subckt dff C=clk D=$0\RCServo_pulse[0:0] Q=RCServo_pulse +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2029 Q=deserialer.RxD_sync[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2037 Q=deserialer.RxD_sync[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2027 Q=RCServo_position[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2025 Q=RCServo_position[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2023 Q=RCServo_position[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2021 Q=RCServo_position[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2019 Q=RCServo_position[4] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2017 Q=RCServo_position[5] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2015 Q=RCServo_position[6] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2035 Q=RCServo_position[7] +.subckt dff C=clk D=$0\ClkTick[0:0] Q=ClkTick +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2013 Q=PulseCount[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2011 Q=PulseCount[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2009 Q=PulseCount[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2007 Q=PulseCount[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2005 Q=PulseCount[4] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2003 Q=PulseCount[5] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2001 Q=PulseCount[6] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1999 Q=PulseCount[7] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1997 Q=PulseCount[8] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1995 Q=PulseCount[9] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1993 Q=PulseCount[10] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2033 Q=PulseCount[11] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1991 Q=deserialer.RxD_state[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1989 Q=deserialer.RxD_state[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2055 Q=deserialer.RxD_state[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2053 Q=deserialer.RxD_state[2] +.names $auto$alumacc.cc:485:replace_alu$628.X[0] $auto$alumacc.cc:485:replace_alu$628.Y[0] +1 1 +.names $auto$alumacc.cc:485:replace_alu$628.CO[11] $auto$alumacc.cc:485:replace_alu$628.Y[12] +1 1 +.names deserialer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$628.X[3] +1 1 +.names deserialer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$628.X[5] +1 1 +.names deserialer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$628.X[6] +1 1 +.names deserialer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$628.X[8] +1 1 +.names deserialer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$628.X[9] +1 1 +.names deserialer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$628.X[10] +1 1 +.names deserialer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$628.X[11] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$628.X[12] +1 1 +.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.CO[0] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$628.CO[12] +1 1 +.names $auto$alumacc.cc:485:replace_alu$613.X[0] $auto$alumacc.cc:485:replace_alu$613.Y[0] +1 1 +.names ClkCount[1] $auto$alumacc.cc:485:replace_alu$613.X[1] +1 1 +.names ClkCount[2] $auto$alumacc.cc:485:replace_alu$613.X[2] +1 1 +.names ClkCount[3] $auto$alumacc.cc:485:replace_alu$613.X[3] +1 1 +.names ClkCount[4] $auto$alumacc.cc:485:replace_alu$613.X[4] +1 1 +.names ClkCount[5] $auto$alumacc.cc:485:replace_alu$613.X[5] +1 1 +.names ClkCount[6] $auto$alumacc.cc:485:replace_alu$613.X[6] +1 1 +.names deserialer.OversamplingTick deserialer.tickgen.Acc[16] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif new file mode 100644 index 00000000000..909b5033223 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif @@ -0,0 +1,53 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model TaskAck_CrossDomain +.inputs clkA TaskStart_clkA clkB TaskDone_clkB +.outputs TaskBusy_clkA TaskDone_clkA TaskStart_clkB TaskBusy_clkB +.names $false +.names $true +1 +.names $undef +.names $abc$605$new_n19 FlagToggle_clkA FlagToggle_clkB $abc$605$auto$rtlil.cc:2693:MuxGate$526 +001 1 +011 1 +110 1 +111 1 +.names TaskDone_clkB SyncA_clkB[2] SyncA_clkB[1] Busyhold_clkB $abc$605$new_n19 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names SyncA_clkB[2] SyncA_clkB[1] TaskStart_clkB +01 1 +10 1 +.names SyncB_clkA[2] SyncB_clkA[1] TaskDone_clkA +01 1 +10 1 +.names SyncB_clkA[2] FlagToggle_clkA TaskBusy_clkA +01 1 +10 1 +.names TaskStart_clkA FlagToggle_clkA SyncB_clkA[2] $0\FlagToggle_clkA[0:0] +010 1 +011 1 +100 1 +110 1 +.names Busyhold_clkB TaskStart_clkB TaskBusy_clkB +01 1 +10 1 +11 1 +.names TaskDone_clkB TaskStart_clkB Busyhold_clkB $0\Busyhold_clkB[0:0] +001 1 +010 1 +011 1 +.subckt dff C=clkB D=$abc$605$auto$rtlil.cc:2693:MuxGate$526 Q=FlagToggle_clkB +.subckt dff C=clkA D=FlagToggle_clkB Q=SyncB_clkA[0] +.subckt dff C=clkA D=SyncB_clkA[0] Q=SyncB_clkA[1] +.subckt dff C=clkA D=SyncB_clkA[1] Q=SyncB_clkA[2] +.subckt dff C=clkB D=$0\Busyhold_clkB[0:0] Q=Busyhold_clkB +.subckt dff C=clkB D=FlagToggle_clkA Q=SyncA_clkB[0] +.subckt dff C=clkB D=SyncA_clkB[0] Q=SyncA_clkB[1] +.subckt dff C=clkB D=SyncA_clkB[1] Q=SyncA_clkB[2] +.subckt dff C=clkA D=$0\FlagToggle_clkA[0:0] Q=FlagToggle_clkA +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif new file mode 100644 index 00000000000..d81a68f31e7 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif @@ -0,0 +1,10133 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model VexRiscv +.inputs iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_error iBus_rsp_payload_inst[0] iBus_rsp_payload_inst[1] iBus_rsp_payload_inst[2] iBus_rsp_payload_inst[3] iBus_rsp_payload_inst[4] iBus_rsp_payload_inst[5] iBus_rsp_payload_inst[6] iBus_rsp_payload_inst[7] iBus_rsp_payload_inst[8] iBus_rsp_payload_inst[9] iBus_rsp_payload_inst[10] iBus_rsp_payload_inst[11] iBus_rsp_payload_inst[12] iBus_rsp_payload_inst[13] iBus_rsp_payload_inst[14] iBus_rsp_payload_inst[15] iBus_rsp_payload_inst[16] iBus_rsp_payload_inst[17] iBus_rsp_payload_inst[18] iBus_rsp_payload_inst[19] iBus_rsp_payload_inst[20] iBus_rsp_payload_inst[21] iBus_rsp_payload_inst[22] iBus_rsp_payload_inst[23] iBus_rsp_payload_inst[24] iBus_rsp_payload_inst[25] iBus_rsp_payload_inst[26] iBus_rsp_payload_inst[27] iBus_rsp_payload_inst[28] iBus_rsp_payload_inst[29] iBus_rsp_payload_inst[30] iBus_rsp_payload_inst[31] timerInterrupt externalInterrupt softwareInterrupt dBus_cmd_ready dBus_rsp_ready dBus_rsp_error dBus_rsp_data[0] dBus_rsp_data[1] dBus_rsp_data[2] dBus_rsp_data[3] dBus_rsp_data[4] dBus_rsp_data[5] dBus_rsp_data[6] dBus_rsp_data[7] dBus_rsp_data[8] dBus_rsp_data[9] dBus_rsp_data[10] dBus_rsp_data[11] dBus_rsp_data[12] dBus_rsp_data[13] dBus_rsp_data[14] dBus_rsp_data[15] dBus_rsp_data[16] dBus_rsp_data[17] dBus_rsp_data[18] dBus_rsp_data[19] dBus_rsp_data[20] dBus_rsp_data[21] dBus_rsp_data[22] dBus_rsp_data[23] dBus_rsp_data[24] dBus_rsp_data[25] dBus_rsp_data[26] dBus_rsp_data[27] dBus_rsp_data[28] dBus_rsp_data[29] dBus_rsp_data[30] dBus_rsp_data[31] clk reset +.outputs iBus_cmd_valid iBus_cmd_payload_pc[0] iBus_cmd_payload_pc[1] iBus_cmd_payload_pc[2] iBus_cmd_payload_pc[3] iBus_cmd_payload_pc[4] iBus_cmd_payload_pc[5] iBus_cmd_payload_pc[6] iBus_cmd_payload_pc[7] iBus_cmd_payload_pc[8] iBus_cmd_payload_pc[9] iBus_cmd_payload_pc[10] iBus_cmd_payload_pc[11] iBus_cmd_payload_pc[12] iBus_cmd_payload_pc[13] iBus_cmd_payload_pc[14] iBus_cmd_payload_pc[15] iBus_cmd_payload_pc[16] iBus_cmd_payload_pc[17] iBus_cmd_payload_pc[18] iBus_cmd_payload_pc[19] iBus_cmd_payload_pc[20] iBus_cmd_payload_pc[21] iBus_cmd_payload_pc[22] iBus_cmd_payload_pc[23] iBus_cmd_payload_pc[24] iBus_cmd_payload_pc[25] iBus_cmd_payload_pc[26] iBus_cmd_payload_pc[27] iBus_cmd_payload_pc[28] iBus_cmd_payload_pc[29] iBus_cmd_payload_pc[30] iBus_cmd_payload_pc[31] dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] +.names $false +.names $true +1 +.names $undef +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1273 iBus_cmd_payload_pc[30] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$new_n1255 $abc$8788$new_n1254 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$new_n1256 $abc$8788$new_n1255 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$new_n1257 $abc$8788$new_n1256 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1257 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1258 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1259 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1260 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1261 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$new_n1263 $abc$8788$new_n1262 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$new_n1264 $abc$8788$new_n1263 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$new_n1265 $abc$8788$new_n1264 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$new_n1266 $abc$8788$new_n1265 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$new_n1267 $abc$8788$new_n1266 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$new_n1268 $abc$8788$new_n1267 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$new_n1269 $abc$8788$new_n1268 +111 1 +.names IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$new_n1269 +111 1 +.names $abc$8788$new_n1271 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$8788$new_n1270 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1272 lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1271 +000 1 +001 1 +010 1 +.names CsrPlugin_interrupt_valid CsrPlugin_pipelineLiberator_done $abc$8788$new_n1272 +11 1 +.names BranchPlugin_jumpInterface_payload[30] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[30] $abc$8788$new_n1273 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_writeBack_ENV_CTRL lastStageIsFiring _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] $abc$8788$new_n1274 +1111 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[30] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$6999 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n2461 $abc$8788$new_n1270 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1276 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$8788$new_n2464 $abc$8788$new_n1296 $abc$8788$new_n1278 +10 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] execute_to_memory_INSTRUCTION[7] $abc$8788$new_n1283 +1100 1 +1111 1 +.names $abc$8788$new_n1286 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n1285 +10000 1 +10011 1 +11100 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n1286 +00 1 +11 1 +.names $abc$8788$new_n1289 HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1288 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n1290 HazardSimplePlugin_writeBackBuffer_valid HazardSimplePlugin_writeBackBuffer_payload_address[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1289 +1100 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1290 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_lastStageRegFileWrite_valid lastStageIsFiring HazardSimplePlugin_writeBackWrites_valid +11 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1296 +11 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n1304 +1100 1 +1111 1 +.names $abc$8788$new_n1317 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1316 $abc$8788$new_n1315 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1316 +10 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1317 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE dBus_rsp_ready execute_to_memory_MEMORY_STORE $abc$8788$new_n1321 +1100 1 +.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$8788$new_n1322 +11 1 +.names execute_arbitration_isValid $abc$8788$new_n1324 _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1323 +1001 1 +1010 1 +1011 1 +.names decode_to_execute_SRC2[0] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1324 +00000 1 +.names $abc$8788$new_n1327 $abc$8788$new_n1326 $abc$8788$new_n1325 +11 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] $abc$8788$new_n1326 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[4] execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1327 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8788$new_n1329 _zz_memory_ENV_CTRL memory_arbitration_isValid lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1328 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid execute_arbitration_isValid _zz_execute_ENV_CTRL $abc$8788$new_n1329 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n1330 +00001 1 +00010 1 +00011 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1332 iBus_cmd_payload_pc[29] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[29] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[29] $abc$8788$new_n1332 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[29] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7001 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1335 iBus_cmd_payload_pc[28] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[28] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[28] $abc$8788$new_n1335 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[28] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7003 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1338 iBus_cmd_payload_pc[27] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[27] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[27] $abc$8788$new_n1338 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[27] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7005 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1341 iBus_cmd_payload_pc[26] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[26] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[26] $abc$8788$new_n1341 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[26] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7007 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1344 iBus_cmd_payload_pc[25] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[25] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[25] $abc$8788$new_n1344 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[25] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7009 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1347 iBus_cmd_payload_pc[24] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[24] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[24] $abc$8788$new_n1347 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[24] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7011 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1350 iBus_cmd_payload_pc[23] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[23] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[23] $abc$8788$new_n1350 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[23] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7013 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1353 iBus_cmd_payload_pc[22] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[22] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[22] $abc$8788$new_n1353 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[22] IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7015 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1356 iBus_cmd_payload_pc[21] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[21] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[21] $abc$8788$new_n1356 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[21] IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7017 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1359 iBus_cmd_payload_pc[20] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[20] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[20] $abc$8788$new_n1359 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[20] IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7019 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1362 iBus_cmd_payload_pc[19] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[19] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[19] $abc$8788$new_n1362 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[19] IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7021 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1365 iBus_cmd_payload_pc[18] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[18] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[18] $abc$8788$new_n1365 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[18] IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7023 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1368 iBus_cmd_payload_pc[17] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[17] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[17] $abc$8788$new_n1368 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[17] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7025 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1371 iBus_cmd_payload_pc[16] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[16] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[16] $abc$8788$new_n1371 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[16] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7027 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1374 iBus_cmd_payload_pc[15] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[15] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[15] $abc$8788$new_n1374 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[15] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7029 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1377 iBus_cmd_payload_pc[14] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[14] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[14] $abc$8788$new_n1377 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[14] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7031 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1380 iBus_cmd_payload_pc[13] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[13] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[13] $abc$8788$new_n1380 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[13] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7033 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1383 iBus_cmd_payload_pc[12] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[12] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[12] $abc$8788$new_n1383 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[12] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7035 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1386 iBus_cmd_payload_pc[11] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[11] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[11] $abc$8788$new_n1386 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[11] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7037 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1389 iBus_cmd_payload_pc[10] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[10] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[10] $abc$8788$new_n1389 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[10] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7039 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1392 iBus_cmd_payload_pc[9] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[9] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[9] $abc$8788$new_n1392 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[9] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7041 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1395 iBus_cmd_payload_pc[8] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[8] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[8] $abc$8788$new_n1395 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[8] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7043 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1398 iBus_cmd_payload_pc[7] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[7] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[7] $abc$8788$new_n1398 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[7] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7045 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1401 iBus_cmd_payload_pc[6] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[6] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[6] $abc$8788$new_n1401 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[6] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7047 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1404 iBus_cmd_payload_pc[5] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$8788$new_n1271 BranchPlugin_jumpInterface_payload[5] $abc$8788$new_n1274 CsrPlugin_mepc[5] $abc$8788$new_n1404 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[5] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7049 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1407 iBus_cmd_payload_pc[4] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[4] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[4] $abc$8788$new_n1407 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[4] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7051 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1410 iBus_cmd_payload_pc[3] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[3] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[3] $abc$8788$new_n1410 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[3] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7053 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1413 iBus_cmd_payload_pc[2] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[2] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[2] $abc$8788$new_n1413 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[2] IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7055 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[30] CsrPlugin_mepc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7439 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[29] CsrPlugin_mepc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7441 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[28] CsrPlugin_mepc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7443 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[27] CsrPlugin_mepc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7445 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[26] CsrPlugin_mepc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7447 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[25] CsrPlugin_mepc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7449 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[24] CsrPlugin_mepc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7451 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[23] CsrPlugin_mepc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7453 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[22] CsrPlugin_mepc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7455 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[21] CsrPlugin_mepc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7457 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[20] CsrPlugin_mepc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7459 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[19] CsrPlugin_mepc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7461 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[18] CsrPlugin_mepc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7463 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[17] CsrPlugin_mepc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7465 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[16] CsrPlugin_mepc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7467 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[15] CsrPlugin_mepc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7469 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[14] CsrPlugin_mepc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7471 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[13] CsrPlugin_mepc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7473 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[12] CsrPlugin_mepc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7475 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[11] CsrPlugin_mepc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7477 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[10] CsrPlugin_mepc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7479 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[9] CsrPlugin_mepc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7481 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[8] CsrPlugin_mepc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7483 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[7] CsrPlugin_mepc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7485 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[6] CsrPlugin_mepc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7487 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[5] CsrPlugin_mepc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7489 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[4] CsrPlugin_mepc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7491 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[3] CsrPlugin_mepc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7493 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[2] CsrPlugin_mepc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7495 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1446 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7497 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1321 $abc$8788$new_n1445 +10 1 +.names $abc$8788$new_n1447 $abc$8788$new_n1326 $abc$8788$new_n1446 +11 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[0] decode_to_execute_SRC2[0] $abc$8788$new_n1447 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1449 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7499 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$new_n1449 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7501 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_amplitudeReg[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7503 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7741 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n1454 $abc$8788$new_n1453 +11 1 +.names $abc$8788$new_n1455 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n1454 +1000 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n2461 $abc$8788$new_n1455 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7743 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7745 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7747 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7749 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] iBus_rsp_payload_inst[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7751 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7753 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7755 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7757 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7759 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7761 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7763 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7765 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7767 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7769 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7771 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] iBus_rsp_payload_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7773 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7775 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7777 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7779 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7781 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7783 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] iBus_rsp_payload_inst[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7785 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] iBus_rsp_payload_inst[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7787 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7789 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7791 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7793 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7795 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7797 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[2] CsrPlugin_mcause_exceptionCode[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7861 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 $abc$8788$new_n1445 $abc$8788$new_n1325 execute_LightShifterPlugin_isActive $abc$8788$auto$rtlil.cc:2693:MuxGate$7863 +1001 1 +1011 1 +1100 1 +1101 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid CsrPlugin_pipelineLiberator_pcValids_1 $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7865 +1111 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n1488 $abc$8788$auto$rtlil.cc:2693:MuxGate$7867 +1110 1 +.names $abc$8788$new_n1321 CsrPlugin_pipelineLiberator_pcValids_1 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$new_n1488 +000 1 +010 1 +100 1 +101 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n2458 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$auto$rtlil.cc:2693:MuxGate$7869 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1492 CsrPlugin_mie_MSIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7871 +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_772 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n1491 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1493 $abc$8788$new_n1492 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1494 execute_CsrPlugin_csr_772 CsrPlugin_mie_MSIE execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MIE $abc$8788$new_n1493 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[3] CsrPlugin_mip_MSIP execute_CsrPlugin_csr_836 $abc$8788$new_n1494 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1496 CsrPlugin_mie_MTIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7873 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1497 $abc$8788$new_n1496 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1498 execute_CsrPlugin_csr_836 CsrPlugin_mip_MTIP $abc$8788$new_n1497 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MTIE CsrPlugin_mstatus_MPIE execute_CsrPlugin_csr_768 $abc$8788$new_n1498 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1500 CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7875 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[11] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1501 $abc$8788$new_n1500 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1502 execute_CsrPlugin_csr_836 CsrPlugin_mip_MEIP $abc$8788$new_n1501 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MEIE CsrPlugin_mstatus_MPP[0] execute_CsrPlugin_csr_768 $abc$8788$new_n1502 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_injector_decodeInput_valid IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7877 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1270 $abc$8788$new_n1505 $abc$8788$new_n2461 $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7879 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names iBus_cmd_ready iBus_cmd_valid $abc$8788$new_n1505 +11 1 +.names $abc$8788$new_n1507 $abc$8788$new_n2461 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid iBus_cmd_valid +1100 1 +1110 1 +1111 1 +.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n1271 IBusSimplePlugin_pending_value[2] IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[0] $abc$8788$new_n1507 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8788$new_n1509 $abc$8788$new_n1505 $abc$8788$auto$rtlil.cc:2693:MuxGate$7881 +01 1 +10 1 +11 1 +.names IBusSimplePlugin_fetchPc_inc $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$new_n1509 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names $abc$8788$new_n1271 $abc$8788$new_n1321 $abc$8788$new_n2458 execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7883 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2461 execute_arbitration_isValid $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7885 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive $abc$8788$new_n1513 execute_LightShifterPlugin_amplitudeReg[4] $abc$8788$new_n1445 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7949 +00100 1 +00101 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1445 execute_LightShifterPlugin_isActive $abc$8788$new_n1446 execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$new_n1513 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1516 $abc$8788$new_n1517 CsrPlugin_interrupt_code[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7953 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_mstatus_MIE $abc$8788$new_n1517 CsrPlugin_mip_MTIP CsrPlugin_mie_MTIE $abc$8788$new_n1516 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names CsrPlugin_mip_MSIP CsrPlugin_mie_MSIE CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$8788$new_n1517 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1516 CsrPlugin_interrupt_code[3] CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7957 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$8788$new_n1330 $abc$8788$new_n1455 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$auto$rtlil.cc:2693:MuxGate$7961 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7963 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[31] $abc$8788$new_n1522 $abc$8788$new_n1523 iBus_cmd_payload_pc[31] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$new_n1255 $abc$8788$new_n1522 +11111 1 +.names BranchPlugin_jumpInterface_payload[31] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[31] $abc$8788$new_n1523 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[31] IBusSimplePlugin_fetchPc_pcReg[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7967 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[3] CsrPlugin_mcause_exceptionCode[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7969 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[31] CsrPlugin_mepc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7975 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1594 $abc$8788$new_n1590 dBus_cmd_payload_address[30] $abc$8788$new_n1595 $abc$8788$auto$rtlil.cc:2693:MuxGate$7057 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1529 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[30] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 $abc$8788$new_n1529 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1584 $abc$8788$new_n1531 $abc$8788$new_n1530 +00 1 +.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1581 $abc$8788$new_n1531 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1533 $abc$8788$new_n1580 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1578 $abc$8788$new_n1532 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1534 $abc$8788$new_n1577 _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1575 $abc$8788$new_n1533 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1535 $abc$8788$new_n1574 _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1572 $abc$8788$new_n1534 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1536 $abc$8788$new_n1569 _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1570 $abc$8788$new_n1535 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1537 $abc$8788$new_n1568 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1565 $abc$8788$new_n1536 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1538 $abc$8788$new_n1564 _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1562 $abc$8788$new_n1537 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1559 $abc$8788$new_n1557 $abc$8788$new_n1561 $abc$8788$new_n1560 $abc$8788$new_n1539 $abc$8788$new_n1538 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1540 $abc$8788$new_n1539 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1554 $abc$8788$new_n1541 $abc$8788$new_n1553 $abc$8788$new_n1540 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1542 $abc$8788$new_n1541 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n1548 _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1549 $abc$8788$new_n1543 $abc$8788$new_n1542 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[3] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1544 $abc$8788$new_n1543 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[3] $abc$8788$new_n1544 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[2] $abc$8788$new_n1545 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[1] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[1] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1546 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01100 1 +10100 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[5] $abc$8788$new_n1547 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[4] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[4] $abc$8788$new_n1548 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[4] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[4] $abc$8788$new_n1549 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[7] $abc$8788$new_n1550 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[6] $abc$8788$new_n1551 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[9] $abc$8788$new_n1552 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[8] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[8] $abc$8788$new_n1553 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n1554 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[11] $abc$8788$new_n1555 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[10] $abc$8788$new_n1556 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1558 $abc$8788$new_n1557 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[12] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[12] $abc$8788$new_n1558 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n1559 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n1560 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] $abc$8788$new_n1561 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n1562 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[15] $abc$8788$new_n1563 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1564 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1565 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[18] $abc$8788$new_n1566 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[17] $abc$8788$new_n1567 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1568 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1569 +10 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n1570 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[19] $abc$8788$new_n1571 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n1572 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[21] $abc$8788$new_n1573 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1574 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n1575 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[23] $abc$8788$new_n1576 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1577 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n1578 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[25] $abc$8788$new_n1579 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1580 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n1581 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[27] $abc$8788$new_n1582 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[26] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[26] $abc$8788$new_n1583 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1584 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[29] $abc$8788$new_n1585 +00 1 +11 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1587 $abc$8788$new_n1586 +11 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1323 $abc$8788$new_n1587 +00 1 +.names $abc$8788$new_n1589 $abc$8788$new_n1322 $abc$8788$new_n1588 +00 1 +.names _zz_execute_ALU_CTRL[0] _zz_execute_ALU_CTRL[1] $abc$8788$new_n1589 +10 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[30] $abc$8788$new_n1323 $abc$8788$new_n1591 $abc$8788$new_n1590 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1593 execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n1591 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1592 +10 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[29] _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1593 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1594 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11100 1 +11111 1 +.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$8788$new_n1595 +10 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1598 dBus_cmd_payload_address[29] $abc$8788$new_n1601 $abc$8788$auto$rtlil.cc:2693:MuxGate$7059 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[29] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[29] $abc$8788$new_n1323 $abc$8788$new_n1599 $abc$8788$new_n1598 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1600 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n1599 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[28] _zz_execute_SrcPlugin_addSub_2[28] $abc$8788$new_n1600 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1601 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1605 dBus_cmd_payload_address[28] $abc$8788$new_n1608 $abc$8788$auto$rtlil.cc:2693:MuxGate$7061 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1604 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[28] +00000 1 +00110 1 +01010 1 +01100 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1604 +0000 1 +0001 1 +0011 1 +0101 1 +1001 1 +1101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[28] $abc$8788$new_n1323 $abc$8788$new_n1606 $abc$8788$new_n1605 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 $abc$8788$new_n1607 $abc$8788$new_n1593 $abc$8788$new_n1606 +001 1 +011 1 +110 1 +111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[27] _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1607 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1608 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1611 dBus_cmd_payload_address[27] $abc$8788$new_n1614 $abc$8788$auto$rtlil.cc:2693:MuxGate$7063 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1583 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1532 dBus_cmd_payload_address[27] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[27] $abc$8788$new_n1323 $abc$8788$new_n1612 $abc$8788$new_n1611 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 $abc$8788$new_n1613 $abc$8788$new_n1600 $abc$8788$new_n1612 +001 1 +011 1 +110 1 +111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[26] _zz_execute_SrcPlugin_addSub_2[26] $abc$8788$new_n1613 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1614 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1618 dBus_cmd_payload_address[26] $abc$8788$new_n1620 $abc$8788$auto$rtlil.cc:2693:MuxGate$7065 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1617 _zz_execute_SrcPlugin_addSub_2[26] dBus_cmd_payload_address[26] +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1578 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 $abc$8788$new_n1533 $abc$8788$new_n1617 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[26] $abc$8788$new_n1323 $abc$8788$new_n1619 $abc$8788$new_n1618 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1607 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1619 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1620 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1622 execute_to_memory_REGFILE_WRITE_DATA[25] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7067 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1624 $abc$8788$new_n1626 $abc$8788$new_n1586 dBus_cmd_payload_address[25] $abc$8788$new_n1595 $abc$8788$new_n1622 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1533 dBus_cmd_payload_address[25] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1625 $abc$8788$new_n1613 $abc$8788$new_n1624 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[24] _zz_execute_SrcPlugin_addSub_2[24] $abc$8788$new_n1625 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1626 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1631 dBus_cmd_payload_address[24] $abc$8788$new_n1634 $abc$8788$auto$rtlil.cc:2693:MuxGate$7069 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1629 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[24] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 $abc$8788$new_n1629 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1577 $abc$8788$new_n1534 $abc$8788$new_n1630 +00 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[24] $abc$8788$new_n1323 $abc$8788$new_n1632 $abc$8788$new_n1631 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1633 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1632 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[23] _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1633 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1634 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1636 execute_to_memory_REGFILE_WRITE_DATA[23] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7071 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1638 $abc$8788$new_n1640 $abc$8788$new_n1586 dBus_cmd_payload_address[23] $abc$8788$new_n1595 $abc$8788$new_n1636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[23] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1639 $abc$8788$new_n1625 $abc$8788$new_n1638 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[22] _zz_execute_SrcPlugin_addSub_2[22] $abc$8788$new_n1639 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1640 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1642 execute_to_memory_REGFILE_WRITE_DATA[22] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7073 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1646 $abc$8788$new_n1648 $abc$8788$new_n1586 dBus_cmd_payload_address[22] $abc$8788$new_n1595 $abc$8788$new_n1642 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1644 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[22] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 $abc$8788$new_n1644 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1574 $abc$8788$new_n1535 $abc$8788$new_n1645 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1647 $abc$8788$new_n1633 $abc$8788$new_n1646 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[21] _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1647 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1648 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1653 $abc$8788$new_n1650 $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7075 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 dBus_cmd_payload_address[21] $abc$8788$new_n1652 $abc$8788$new_n1650 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[21] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1652 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1654 $abc$8788$new_n1639 $abc$8788$new_n1653 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[20] _zz_execute_SrcPlugin_addSub_2[20] $abc$8788$new_n1654 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1656 execute_to_memory_REGFILE_WRITE_DATA[20] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7077 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1660 $abc$8788$new_n1662 $abc$8788$new_n1586 dBus_cmd_payload_address[20] $abc$8788$new_n1595 $abc$8788$new_n1656 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1658 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[20] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 $abc$8788$new_n1658 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1569 $abc$8788$new_n1536 $abc$8788$new_n1659 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1661 $abc$8788$new_n1647 $abc$8788$new_n1660 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[19] _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1661 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1662 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1664 execute_to_memory_REGFILE_WRITE_DATA[19] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7079 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1666 $abc$8788$new_n1586 $abc$8788$new_n1668 $abc$8788$new_n1595 dBus_cmd_payload_address[19] $abc$8788$new_n1664 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[19] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1667 $abc$8788$new_n1654 $abc$8788$new_n1666 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[18] _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1667 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1668 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11100 1 +11111 1 +.names $abc$8788$new_n1670 execute_to_memory_REGFILE_WRITE_DATA[18] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7081 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1673 $abc$8788$new_n1675 $abc$8788$new_n1586 dBus_cmd_payload_address[18] $abc$8788$new_n1595 $abc$8788$new_n1670 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1672 _zz_execute_SrcPlugin_addSub_2[18] dBus_cmd_payload_address[18] +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1565 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 $abc$8788$new_n1537 $abc$8788$new_n1672 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1674 $abc$8788$new_n1661 $abc$8788$new_n1673 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[17] _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1674 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1675 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1678 dBus_cmd_payload_address[17] $abc$8788$new_n1680 $abc$8788$auto$rtlil.cc:2693:MuxGate$7083 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1537 dBus_cmd_payload_address[17] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[17] $abc$8788$new_n1323 $abc$8788$new_n1679 $abc$8788$new_n1678 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1667 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1680 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1682 execute_to_memory_REGFILE_WRITE_DATA[16] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7085 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1686 $abc$8788$new_n1688 $abc$8788$new_n1586 dBus_cmd_payload_address[16] $abc$8788$new_n1595 $abc$8788$new_n1682 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1684 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[16] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 $abc$8788$new_n1684 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1564 $abc$8788$new_n1538 $abc$8788$new_n1685 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1687 $abc$8788$new_n1674 $abc$8788$new_n1686 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[15] _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1687 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1688 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1691 dBus_cmd_payload_address[15] $abc$8788$new_n1694 $abc$8788$auto$rtlil.cc:2693:MuxGate$7087 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[15] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[15] $abc$8788$new_n1323 $abc$8788$new_n1692 $abc$8788$new_n1691 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1693 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1692 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[14] _zz_execute_SrcPlugin_addSub_2[14] $abc$8788$new_n1693 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1694 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1696 execute_to_memory_REGFILE_WRITE_DATA[14] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7089 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1700 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[14] $abc$8788$new_n1702 $abc$8788$new_n1696 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1698 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[14] +00000 1 +00110 1 +01010 1 +01100 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1557 $abc$8788$new_n1699 $abc$8788$new_n1560 $abc$8788$new_n1698 +000 1 +001 1 +010 1 +.names $abc$8788$new_n1561 $abc$8788$new_n1539 $abc$8788$new_n1699 +10 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1701 $abc$8788$new_n1687 $abc$8788$new_n1700 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1701 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1702 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1704 execute_to_memory_REGFILE_WRITE_DATA[13] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7091 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1706 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[13] $abc$8788$new_n1708 $abc$8788$new_n1704 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1560 $abc$8788$new_n1558 $abc$8788$new_n1699 _zz_execute_SrcPlugin_addSub_2[13] dBus_cmd_payload_address[13] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1707 $abc$8788$new_n1693 $abc$8788$new_n1706 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[12] _zz_execute_SrcPlugin_addSub_2[12] $abc$8788$new_n1707 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1708 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1710 execute_to_memory_REGFILE_WRITE_DATA[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7093 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1711 $abc$8788$new_n1592 $abc$8788$new_n1323 $abc$8788$new_n1715 $abc$8788$new_n1701 $abc$8788$new_n1710 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$8788$new_n1713 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[12] $abc$8788$new_n1714 $abc$8788$new_n1711 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1539 $abc$8788$new_n1561 _zz_execute_SrcPlugin_addSub_2[12] dBus_cmd_payload_address[12] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1323 execute_CsrPlugin_csr_768 $abc$8788$new_n1322 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1713 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1714 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[11] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1715 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1717 execute_to_memory_REGFILE_WRITE_DATA[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7095 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1722 $abc$8788$new_n1718 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1501 $abc$8788$new_n1717 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[11] $abc$8788$new_n1721 $abc$8788$new_n1718 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1720 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[11] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1540 $abc$8788$new_n1720 +000 1 +100 1 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1721 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1723 $abc$8788$new_n1707 $abc$8788$new_n1722 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[10] _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1723 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1725 execute_to_memory_REGFILE_WRITE_DATA[10] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7097 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1727 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[10] $abc$8788$new_n1729 $abc$8788$new_n1725 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1556 $abc$8788$new_n1540 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[10] +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1728 $abc$8788$new_n1715 $abc$8788$new_n1727 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[9] _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1728 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1729 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[9] $abc$8788$new_n1731 $abc$8788$new_n1735 $abc$8788$auto$rtlil.cc:2693:MuxGate$7099 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1734 dBus_cmd_payload_address[9] $abc$8788$new_n1595 $abc$8788$new_n1731 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1733 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[9] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1553 $abc$8788$new_n1541 $abc$8788$new_n1554 $abc$8788$new_n1733 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1734 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1736 $abc$8788$new_n1723 $abc$8788$new_n1735 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[8] _zz_execute_SrcPlugin_addSub_2[8] $abc$8788$new_n1736 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[8] $abc$8788$new_n1738 $abc$8788$new_n1741 $abc$8788$auto$rtlil.cc:2693:MuxGate$7101 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1740 dBus_cmd_payload_address[8] $abc$8788$new_n1595 $abc$8788$new_n1738 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1541 $abc$8788$new_n1554 _zz_execute_SrcPlugin_addSub_2[8] dBus_cmd_payload_address[8] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1740 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1742 $abc$8788$new_n1728 $abc$8788$new_n1741 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[7] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1742 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1744 execute_to_memory_REGFILE_WRITE_DATA[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7103 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1749 $abc$8788$new_n1745 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1497 $abc$8788$new_n1744 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1748 dBus_cmd_payload_address[7] $abc$8788$new_n1595 $abc$8788$new_n1745 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1747 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[7] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1542 $abc$8788$new_n1747 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1748 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1750 $abc$8788$new_n1736 $abc$8788$new_n1749 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[6] _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1750 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1752 execute_to_memory_REGFILE_WRITE_DATA[6] $abc$8788$new_n1323 $abc$8788$new_n1755 $abc$8788$auto$rtlil.cc:2693:MuxGate$7105 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1754 dBus_cmd_payload_address[6] $abc$8788$new_n1595 $abc$8788$new_n1752 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1551 $abc$8788$new_n1542 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[6] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1754 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1742 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1755 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1757 execute_to_memory_REGFILE_WRITE_DATA[5] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7107 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1760 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[5] $abc$8788$new_n1762 $abc$8788$new_n1757 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1759 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[5] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1548 $abc$8788$new_n1543 $abc$8788$new_n1549 $abc$8788$new_n1759 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1761 $abc$8788$new_n1750 $abc$8788$new_n1760 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[4] _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n1761 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1762 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1764 execute_to_memory_REGFILE_WRITE_DATA[4] $abc$8788$new_n1323 $abc$8788$new_n1767 $abc$8788$auto$rtlil.cc:2693:MuxGate$7109 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1766 dBus_cmd_payload_address[4] $abc$8788$new_n1595 $abc$8788$new_n1764 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1543 $abc$8788$new_n1549 _zz_execute_SrcPlugin_addSub_2[4] dBus_cmd_payload_address[4] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1766 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1768 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1767 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[3] _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1768 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1770 execute_to_memory_REGFILE_WRITE_DATA[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7111 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1775 $abc$8788$new_n1771 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1493 $abc$8788$new_n1770 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[3] $abc$8788$new_n1774 $abc$8788$new_n1771 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1544 $abc$8788$new_n1773 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[3] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1773 +001 1 +100 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1774 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1776 $abc$8788$new_n1761 $abc$8788$new_n1775 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[2] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1776 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[2] $abc$8788$new_n1783 $abc$8788$new_n1781 $abc$8788$new_n1778 $abc$8788$auto$rtlil.cc:2693:MuxGate$7113 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 $abc$8788$new_n1323 dBus_cmd_payload_address[2] $abc$8788$new_n1780 $abc$8788$new_n1778 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1546 $abc$8788$new_n1545 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[2] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1780 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1782 $abc$8788$new_n1768 $abc$8788$new_n1781 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[1] _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n1782 +000 1 +010 1 +100 1 +101 1 +.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$8788$new_n1322 $abc$8788$new_n1323 $abc$8788$new_n1783 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1785 execute_to_memory_REGFILE_WRITE_DATA[1] $abc$8788$new_n1323 $abc$8788$new_n1790 $abc$8788$auto$rtlil.cc:2693:MuxGate$7115 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[1] $abc$8788$new_n1789 $abc$8788$new_n1785 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1322 execute_CsrPlugin_csr_834 $abc$8788$new_n1786 +000 1 +001 1 +010 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1788 _zz_execute_SrcPlugin_addSub_2[1] dBus_cmd_payload_address[1] +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] $abc$8788$new_n1788 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1789 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1776 execute_to_memory_REGFILE_WRITE_DATA[0] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1790 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$8788$new_n1803 $abc$8788$new_n1322 $abc$8788$new_n1587 $abc$8788$new_n1792 execute_CsrPlugin_csr_834 $abc$8788$auto$rtlil.cc:2693:MuxGate$7117 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1589 $abc$8788$new_n1799 $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n1792 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1796 $abc$8788$new_n1798 $abc$8788$new_n1794 _zz_execute_SrcPlugin_addSub_2[31] dBus_cmd_payload_address[31] +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1531 $abc$8788$new_n1584 _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1795 $abc$8788$new_n1794 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n1795 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$8788$new_n1797 $abc$8788$new_n1796 +01 1 +10 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] $abc$8788$new_n1797 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1798 +101 1 +110 1 +.names $abc$8788$new_n1595 $abc$8788$new_n1800 dBus_cmd_payload_address[0] $abc$8788$new_n1799 +000 1 +010 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1800 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +1010 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[0] +010 1 +100 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC_LESS_UNSIGNED decode_to_execute_SRC2[31] $abc$8788$new_n1802 +000 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1323 execute_to_memory_REGFILE_WRITE_DATA[0] $abc$8788$new_n1782 $abc$8788$new_n1592 $abc$8788$new_n1803 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_MEMORY_ADDRESS_LOW[0] dBus_cmd_payload_address[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7119 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1806 decode_to_execute_SRC2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7121 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] _zz_decode_SRC2 $abc$8788$new_n1806 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n1807 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1809 decode_to_execute_SRC2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7123 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] _zz_decode_SRC2 $abc$8788$new_n1809 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1811 decode_to_execute_SRC2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7125 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] _zz_decode_SRC2 $abc$8788$new_n1811 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1813 decode_to_execute_SRC2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7127 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] _zz_decode_SRC2 $abc$8788$new_n1813 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1815 decode_to_execute_SRC2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7129 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] _zz_decode_SRC2 $abc$8788$new_n1815 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1817 decode_to_execute_SRC2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7131 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] _zz_decode_SRC2 $abc$8788$new_n1817 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1819 decode_to_execute_SRC2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7133 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] _zz_decode_SRC2 $abc$8788$new_n1819 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1821 decode_to_execute_SRC2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7135 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] _zz_decode_SRC2 $abc$8788$new_n1821 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1823 decode_to_execute_SRC2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7137 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] _zz_decode_SRC2 $abc$8788$new_n1823 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1825 decode_to_execute_SRC2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7139 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] _zz_decode_SRC2 $abc$8788$new_n1825 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1827 decode_to_execute_SRC2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7141 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] _zz_decode_SRC2 $abc$8788$new_n1827 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1829 decode_to_execute_SRC2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7143 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] _zz_decode_SRC2 $abc$8788$new_n1829 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1831 decode_to_execute_SRC2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7145 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] _zz_decode_SRC2 $abc$8788$new_n1831 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1833 decode_to_execute_SRC2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7147 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] _zz_decode_SRC2 $abc$8788$new_n1833 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1835 decode_to_execute_SRC2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7149 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] _zz_decode_SRC2 $abc$8788$new_n1835 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1837 decode_to_execute_SRC2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7151 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] _zz_decode_SRC2 $abc$8788$new_n1837 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1839 decode_to_execute_SRC2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7153 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] _zz_decode_SRC2 $abc$8788$new_n1839 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1841 decode_to_execute_SRC2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7155 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] _zz_decode_SRC2 $abc$8788$new_n1841 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1843 decode_to_execute_SRC2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7157 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] _zz_decode_SRC2 $abc$8788$new_n1843 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1845 decode_to_execute_SRC2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7159 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] _zz_decode_SRC2 $abc$8788$new_n1845 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1847 decode_to_execute_SRC2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7161 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n1847 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1849 decode_to_execute_SRC2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7163 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$8788$new_n1849 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1851 decode_to_execute_SRC2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7165 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$8788$new_n1851 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1853 decode_to_execute_SRC2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7167 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n1853 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1855 decode_to_execute_SRC2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7169 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n1855 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1857 decode_to_execute_SRC2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7171 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$8788$new_n1857 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1859 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7173 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1860 _zz_RegFilePlugin_regFile_port1[4] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[4] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1859 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1860 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1861 +1000 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 $abc$8788$new_n1862 +00 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1864 decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7175 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1865 _zz_RegFilePlugin_regFile_port1[3] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[3] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1864 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1865 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1867 decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7177 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1868 _zz_RegFilePlugin_regFile_port1[2] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[2] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1867 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n1868 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1870 decode_to_execute_SRC2[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7179 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[1] $abc$8788$new_n1870 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1872 decode_to_execute_SRC2[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7181 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[0] $abc$8788$new_n1872 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[30] decode_to_execute_RS2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7183 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[29] decode_to_execute_RS2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7185 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[28] decode_to_execute_RS2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7187 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[27] decode_to_execute_RS2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7189 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[26] decode_to_execute_RS2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7191 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[25] decode_to_execute_RS2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7193 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[24] decode_to_execute_RS2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7195 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[23] decode_to_execute_RS2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7197 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[22] decode_to_execute_RS2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7199 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[21] decode_to_execute_RS2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7201 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[20] decode_to_execute_RS2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7203 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[19] decode_to_execute_RS2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7205 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[18] decode_to_execute_RS2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7207 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[17] decode_to_execute_RS2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7209 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[16] decode_to_execute_RS2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7211 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[15] decode_to_execute_RS2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7213 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[14] decode_to_execute_RS2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7215 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[13] decode_to_execute_RS2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7217 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[12] decode_to_execute_RS2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7219 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[11] decode_to_execute_RS2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7221 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[10] decode_to_execute_RS2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7223 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[9] decode_to_execute_RS2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7225 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[8] decode_to_execute_RS2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7227 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[7] dBus_cmd_payload_data[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7229 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[6] dBus_cmd_payload_data[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7231 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[5] dBus_cmd_payload_data[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7233 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[4] dBus_cmd_payload_data[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7235 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[3] dBus_cmd_payload_data[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7237 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[2] dBus_cmd_payload_data[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7239 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[1] dBus_cmd_payload_data[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7241 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[0] dBus_cmd_payload_data[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7243 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[30] decode_to_execute_RS1[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7245 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[29] decode_to_execute_RS1[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7247 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[28] decode_to_execute_RS1[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7249 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[27] decode_to_execute_RS1[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7251 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[26] decode_to_execute_RS1[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7253 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[25] decode_to_execute_RS1[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7255 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[24] decode_to_execute_RS1[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7257 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[23] decode_to_execute_RS1[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7259 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[22] decode_to_execute_RS1[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7261 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[21] decode_to_execute_RS1[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7263 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[20] decode_to_execute_RS1[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7265 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[19] decode_to_execute_RS1[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7267 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[18] decode_to_execute_RS1[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7269 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[17] decode_to_execute_RS1[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7271 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[16] decode_to_execute_RS1[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7273 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[15] decode_to_execute_RS1[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7275 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[14] decode_to_execute_RS1[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7277 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[13] decode_to_execute_RS1[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7279 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[12] decode_to_execute_RS1[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7281 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[11] decode_to_execute_RS1[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7283 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[10] decode_to_execute_RS1[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7285 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[9] decode_to_execute_RS1[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7287 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[8] decode_to_execute_RS1[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7289 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[7] decode_to_execute_RS1[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7291 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[6] decode_to_execute_RS1[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7293 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[5] decode_to_execute_RS1[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7295 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[4] decode_to_execute_RS1[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7297 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[3] decode_to_execute_RS1[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7299 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[2] decode_to_execute_RS1[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7301 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[1] decode_to_execute_RS1[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7303 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[0] decode_to_execute_RS1[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7305 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_BRANCH_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7307 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1937 _zz_execute_SHIFT_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7309 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n1937 +11000 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_BITWISE_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7311 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7313 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7317 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7319 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7347 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7349 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[12] dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7351 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7353 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7355 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7357 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7359 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7361 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7377 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7379 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7381 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7383 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7385 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7387 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] _zz__zz_execute_BranchPlugin_branch_src2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7389 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7391 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7393 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7395 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7397 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7399 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7401 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7403 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7405 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7407 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7409 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7411 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7413 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7415 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7417 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7419 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7421 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7423 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7505 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7507 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7509 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7511 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7513 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7515 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7517 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7519 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7521 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7523 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7525 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7527 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7529 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7531 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7533 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7535 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7537 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7539 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7541 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7543 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7545 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7547 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7549 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7551 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7553 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7555 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_injector_decodeInput_payload_pc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7557 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_injector_decodeInput_payload_pc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7559 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_injector_decodeInput_payload_pc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7561 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2004 BranchPlugin_jumpInterface_payload[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7563 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2059 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2005 $abc$8788$new_n2004 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2058 $abc$8788$new_n2057 $abc$8788$new_n2056 $abc$8788$new_n2006 $abc$8788$new_n2005 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$8788$new_n2020 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2007 decode_to_execute_PC[25] decode_to_execute_RS1[25] $abc$8788$new_n2006 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2055 $abc$8788$new_n2054 $abc$8788$new_n2008 $abc$8788$new_n2007 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2053 $abc$8788$new_n2052 $abc$8788$new_n2051 $abc$8788$new_n2009 $abc$8788$new_n2008 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$8788$new_n2050 $abc$8788$new_n2048 $abc$8788$new_n2049 $abc$8788$new_n2047 $abc$8788$new_n2010 $abc$8788$new_n2009 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2046 $abc$8788$new_n2044 $abc$8788$new_n2045 $abc$8788$new_n2043 $abc$8788$new_n2011 $abc$8788$new_n2010 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2042 $abc$8788$new_n2040 $abc$8788$new_n2041 $abc$8788$new_n2039 $abc$8788$new_n2012 $abc$8788$new_n2011 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names $abc$8788$new_n2034 $abc$8788$new_n2038 $abc$8788$new_n2037 $abc$8788$new_n2036 $abc$8788$new_n2013 $abc$8788$new_n2012 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$new_n2032 $abc$8788$new_n2033 $abc$8788$new_n2031 $abc$8788$new_n2014 $abc$8788$new_n2013 +00000 1 +00001 1 +00010 1 +00100 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$8788$new_n2030 _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$new_n2029 $abc$8788$new_n2015 $abc$8788$new_n2014 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n2028 _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$new_n2027 $abc$8788$new_n2016 $abc$8788$new_n2015 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n2026 $abc$8788$new_n2025 _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$new_n2024 $abc$8788$new_n2017 $abc$8788$new_n2016 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2023 $abc$8788$new_n2018 _zz__zz_execute_BranchPlugin_branch_src2[2] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2017 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2021 $abc$8788$new_n2019 _zz__zz_execute_BranchPlugin_branch_src2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$new_n2018 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[2] decode_to_execute_PC[2] $abc$8788$new_n2019 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] $abc$8788$new_n2020 +11 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[0] _zz__zz_execute_BranchPlugin_branch_src2[10] _zz__zz_execute_BranchPlugin_branch_src2[0] decode_to_execute_RS1[1] $abc$8788$new_n2021 +10011 1 +10111 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[3] decode_to_execute_PC[3] $abc$8788$new_n2023 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[5] decode_to_execute_PC[5] $abc$8788$new_n2024 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[4] decode_to_execute_PC[4] $abc$8788$new_n2025 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[3] _zz__zz_execute_BranchPlugin_branch_src2[3] $abc$8788$new_n2026 +000 1 +001 1 +100 1 +110 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[7] decode_to_execute_PC[7] $abc$8788$new_n2027 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[6] decode_to_execute_PC[6] $abc$8788$new_n2028 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[9] decode_to_execute_PC[9] $abc$8788$new_n2029 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[8] decode_to_execute_PC[8] $abc$8788$new_n2030 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[11] decode_to_execute_PC[11] $abc$8788$new_n2031 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[10] decode_to_execute_PC[10] $abc$8788$new_n2032 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_4[10] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[10] $abc$8788$new_n2033 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$8788$new_n2035 _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 dBus_cmd_payload_size[0] $abc$8788$new_n2034 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01110 1 +01111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[12] decode_to_execute_PC[12] $abc$8788$new_n2035 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2035 _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 dBus_cmd_payload_size[0] $abc$8788$new_n2036 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[13] decode_to_execute_PC[13] $abc$8788$new_n2037 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 switch_Misc_l241_1 $abc$8788$new_n2038 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[15] decode_to_execute_PC[15] $abc$8788$new_n2039 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[14] decode_to_execute_PC[14] $abc$8788$new_n2040 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[14] $abc$8788$new_n2041 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n2042 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[17] decode_to_execute_PC[17] $abc$8788$new_n2043 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[16] decode_to_execute_PC[16] $abc$8788$new_n2044 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[16] $abc$8788$new_n2045 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[15] $abc$8788$new_n2046 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[19] decode_to_execute_PC[19] $abc$8788$new_n2047 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[18] decode_to_execute_PC[18] $abc$8788$new_n2048 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[18] $abc$8788$new_n2049 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[17] $abc$8788$new_n2050 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[22] decode_to_execute_PC[22] $abc$8788$new_n2051 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[21] decode_to_execute_PC[21] $abc$8788$new_n2052 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[20] decode_to_execute_PC[20] $abc$8788$new_n2053 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[24] decode_to_execute_PC[24] $abc$8788$new_n2054 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[23] decode_to_execute_PC[23] $abc$8788$new_n2055 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[28] decode_to_execute_PC[28] $abc$8788$new_n2056 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[27] decode_to_execute_PC[27] $abc$8788$new_n2057 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[26] decode_to_execute_PC[26] $abc$8788$new_n2058 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[30] decode_to_execute_PC[30] $abc$8788$new_n2059 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[29] decode_to_execute_PC[29] $abc$8788$new_n2060 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2005 BranchPlugin_jumpInterface_payload[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7565 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2056 $abc$8788$new_n2063 BranchPlugin_jumpInterface_payload[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7567 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2057 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2064 $abc$8788$new_n2063 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n2058 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2006 $abc$8788$new_n2064 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2057 $abc$8788$new_n2064 BranchPlugin_jumpInterface_payload[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7569 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2058 $abc$8788$new_n2006 BranchPlugin_jumpInterface_payload[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7571 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2007 $abc$8788$new_n2068 BranchPlugin_jumpInterface_payload[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7573 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2020 decode_to_execute_PC[25] decode_to_execute_RS1[25] $abc$8788$new_n2068 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2070 BranchPlugin_jumpInterface_payload[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7575 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2054 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2055 $abc$8788$new_n2008 $abc$8788$new_n2070 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2055 $abc$8788$new_n2008 BranchPlugin_jumpInterface_payload[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7577 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2051 $abc$8788$new_n2073 BranchPlugin_jumpInterface_payload[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7579 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2052 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2074 $abc$8788$new_n2073 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n2053 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2009 $abc$8788$new_n2074 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2052 $abc$8788$new_n2074 BranchPlugin_jumpInterface_payload[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7581 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2053 $abc$8788$new_n2009 BranchPlugin_jumpInterface_payload[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7583 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2049 $abc$8788$new_n2047 $abc$8788$new_n2078 BranchPlugin_jumpInterface_payload[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7585 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2050 $abc$8788$new_n2048 $abc$8788$new_n2010 $abc$8788$new_n2078 +011 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2050 $abc$8788$new_n2048 $abc$8788$new_n2010 BranchPlugin_jumpInterface_payload[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7587 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2045 $abc$8788$new_n2043 $abc$8788$new_n2081 BranchPlugin_jumpInterface_payload[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7589 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2046 $abc$8788$new_n2044 $abc$8788$new_n2011 $abc$8788$new_n2081 +010 1 +100 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2046 $abc$8788$new_n2044 $abc$8788$new_n2011 BranchPlugin_jumpInterface_payload[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7591 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2041 $abc$8788$new_n2039 $abc$8788$new_n2084 BranchPlugin_jumpInterface_payload[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7593 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2042 $abc$8788$new_n2040 $abc$8788$new_n2012 $abc$8788$new_n2084 +011 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2042 $abc$8788$new_n2040 $abc$8788$new_n2012 BranchPlugin_jumpInterface_payload[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7595 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2038 $abc$8788$new_n2037 $abc$8788$new_n2087 BranchPlugin_jumpInterface_payload[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7597 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2034 $abc$8788$new_n2013 $abc$8788$new_n2036 $abc$8788$new_n2087 +000 1 +001 1 +010 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2036 $abc$8788$new_n2013 BranchPlugin_jumpInterface_payload[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7599 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2033 $abc$8788$new_n2031 $abc$8788$new_n2090 BranchPlugin_jumpInterface_payload[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7601 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2032 _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$new_n2014 $abc$8788$new_n2090 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$new_n2032 $abc$8788$new_n2014 BranchPlugin_jumpInterface_payload[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7603 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$new_n2029 $abc$8788$new_n2093 BranchPlugin_jumpInterface_payload[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7605 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2030 _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$new_n2015 $abc$8788$new_n2093 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$new_n2030 $abc$8788$new_n2015 BranchPlugin_jumpInterface_payload[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7607 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$new_n2027 $abc$8788$new_n2096 BranchPlugin_jumpInterface_payload[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7609 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2028 _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$new_n2016 $abc$8788$new_n2096 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$new_n2028 $abc$8788$new_n2016 BranchPlugin_jumpInterface_payload[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7611 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$new_n2024 $abc$8788$new_n2099 BranchPlugin_jumpInterface_payload[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7613 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2026 $abc$8788$new_n2025 $abc$8788$new_n2017 $abc$8788$new_n2099 +011 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2026 $abc$8788$new_n2025 $abc$8788$new_n2017 BranchPlugin_jumpInterface_payload[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7615 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2102 BranchPlugin_jumpInterface_payload[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7617 +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2023 $abc$8788$new_n2018 _zz__zz_execute_BranchPlugin_branch_src2[2] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2102 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2104 BranchPlugin_jumpInterface_payload[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7619 +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2021 $abc$8788$new_n2019 _zz__zz_execute_BranchPlugin_branch_src2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$new_n2104 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] decode_INSTRUCTION_ANTICIPATED[30] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] decode_INSTRUCTION_ANTICIPATED[29] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] decode_INSTRUCTION_ANTICIPATED[28] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] decode_INSTRUCTION_ANTICIPATED[27] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] decode_INSTRUCTION_ANTICIPATED[26] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] iBus_rsp_payload_inst[25] decode_INSTRUCTION_ANTICIPATED[25] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] iBus_rsp_payload_inst[14] decode_INSTRUCTION_ANTICIPATED[14] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] decode_INSTRUCTION_ANTICIPATED[13] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] decode_INSTRUCTION_ANTICIPATED[12] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] decode_INSTRUCTION_ANTICIPATED[11] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] decode_INSTRUCTION_ANTICIPATED[10] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] decode_INSTRUCTION_ANTICIPATED[9] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] iBus_rsp_payload_inst[8] decode_INSTRUCTION_ANTICIPATED[8] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] iBus_rsp_payload_inst[7] decode_INSTRUCTION_ANTICIPATED[7] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] decode_INSTRUCTION_ANTICIPATED[6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] decode_INSTRUCTION_ANTICIPATED[5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] decode_INSTRUCTION_ANTICIPATED[4] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] decode_INSTRUCTION_ANTICIPATED[3] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] decode_INSTRUCTION_ANTICIPATED[2] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2126 _zz_execute_SrcPlugin_addSub_2[30] _zz_RegFilePlugin_regFile_port0[30] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1296 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2125 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2126 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2128 _zz_execute_SrcPlugin_addSub_2[29] _zz_RegFilePlugin_regFile_port0[29] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2128 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2130 _zz_execute_SrcPlugin_addSub_2[28] _zz_RegFilePlugin_regFile_port0[28] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7669 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2130 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2132 _zz_execute_SrcPlugin_addSub_2[27] _zz_RegFilePlugin_regFile_port0[27] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7671 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2132 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2134 _zz_execute_SrcPlugin_addSub_2[26] _zz_RegFilePlugin_regFile_port0[26] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7673 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2134 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2136 _zz_execute_SrcPlugin_addSub_2[25] _zz_RegFilePlugin_regFile_port0[25] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7675 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2136 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2138 _zz_execute_SrcPlugin_addSub_2[24] _zz_RegFilePlugin_regFile_port0[24] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7677 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2138 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2140 _zz_execute_SrcPlugin_addSub_2[23] _zz_RegFilePlugin_regFile_port0[23] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2140 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2142 _zz_execute_SrcPlugin_addSub_2[22] _zz_RegFilePlugin_regFile_port0[22] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7681 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2142 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2144 _zz_execute_SrcPlugin_addSub_2[21] _zz_RegFilePlugin_regFile_port0[21] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7683 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2144 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2146 _zz_execute_SrcPlugin_addSub_2[20] _zz_RegFilePlugin_regFile_port0[20] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7685 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2146 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2148 _zz_execute_SrcPlugin_addSub_2[19] _zz_RegFilePlugin_regFile_port0[19] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7687 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2148 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2150 _zz_execute_SrcPlugin_addSub_2[18] _zz_RegFilePlugin_regFile_port0[18] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7689 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2150 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2152 _zz_execute_SrcPlugin_addSub_2[17] _zz_RegFilePlugin_regFile_port0[17] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7691 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2152 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2154 _zz_execute_SrcPlugin_addSub_2[16] _zz_RegFilePlugin_regFile_port0[16] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7693 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2154 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2156 _zz_execute_SrcPlugin_addSub_2[15] _zz_RegFilePlugin_regFile_port0[15] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7695 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2156 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2158 _zz_execute_SrcPlugin_addSub_2[14] _zz_RegFilePlugin_regFile_port0[14] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7697 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2158 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2160 _zz_execute_SrcPlugin_addSub_2[13] _zz_RegFilePlugin_regFile_port0[13] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7699 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2160 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2162 _zz_execute_SrcPlugin_addSub_2[12] _zz_RegFilePlugin_regFile_port0[12] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7701 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2162 +11110 1 +.names $abc$8788$new_n2164 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7703 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2165 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2164 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz_RegFilePlugin_regFile_port0[2] $abc$8788$new_n2165 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2167 _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7707 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz_RegFilePlugin_regFile_port0[3] $abc$8788$new_n2167 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2168 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8788$new_n2170 _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7711 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz_RegFilePlugin_regFile_port0[1] $abc$8788$new_n2170 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2172 _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7715 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz_RegFilePlugin_regFile_port0[0] $abc$8788$new_n2172 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[10] _zz_RegFilePlugin_regFile_port0[10] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7719 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[9] _zz_RegFilePlugin_regFile_port0[9] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7723 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[8] _zz_RegFilePlugin_regFile_port0[8] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7727 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[7] _zz_RegFilePlugin_regFile_port0[7] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7731 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[6] _zz_RegFilePlugin_regFile_port0[6] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7735 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[5] _zz_RegFilePlugin_regFile_port0[5] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7739 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[30] decode_to_execute_PC[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7803 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[29] decode_to_execute_PC[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7805 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[28] decode_to_execute_PC[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7807 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[27] decode_to_execute_PC[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7809 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[26] decode_to_execute_PC[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7811 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[25] decode_to_execute_PC[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7813 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[24] decode_to_execute_PC[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7815 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[23] decode_to_execute_PC[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7817 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[22] decode_to_execute_PC[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7819 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[21] decode_to_execute_PC[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7821 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[20] decode_to_execute_PC[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7823 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[19] decode_to_execute_PC[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7825 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[18] decode_to_execute_PC[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7827 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[17] decode_to_execute_PC[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7829 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[16] decode_to_execute_PC[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7831 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[15] decode_to_execute_PC[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7833 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[14] decode_to_execute_PC[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7835 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[13] decode_to_execute_PC[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7837 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[12] decode_to_execute_PC[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7839 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[11] decode_to_execute_PC[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7841 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[10] decode_to_execute_PC[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7843 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[9] decode_to_execute_PC[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7845 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[8] decode_to_execute_PC[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7847 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[7] decode_to_execute_PC[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7849 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[6] decode_to_execute_PC[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7851 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[5] decode_to_execute_PC[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7853 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[4] decode_to_execute_PC[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7855 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[3] decode_to_execute_PC[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7857 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[2] decode_to_execute_PC[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7859 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_834 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2209 $abc$8788$auto$rtlil.cc:2693:MuxGate$7887 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2210 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2209 +11000 1 +.names $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2210 +1000 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n2211 +1100 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_772 $abc$8788$new_n2214 $abc$8788$new_n2213 $abc$8788$auto$rtlil.cc:2693:MuxGate$7889 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2213 +11000 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2214 +0000 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2216 execute_CsrPlugin_csr_836 $abc$8788$auto$rtlil.cc:2693:MuxGate$7891 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2213 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2216 +11000 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_768 $abc$8788$new_n2210 $abc$8788$new_n2214 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7893 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$8788$new_n2245 _zz_execute_BRANCH_CTRL[0] $abc$8788$new_n2246 $abc$8788$new_n2219 $abc$8788$new_n2242 $abc$8788$auto$rtlil.cc:2693:MuxGate$7897 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2220 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n2219 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[13] switch_Misc_l241_1 $abc$8788$new_n2221 $abc$8788$new_n2220 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2236 $abc$8788$new_n2222 _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] $abc$8788$new_n2221 +1100 1 +1111 1 +.names $abc$8788$new_n2233 $abc$8788$new_n2223 $abc$8788$new_n2235 _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] $abc$8788$new_n2222 +11100 1 +11111 1 +.names $abc$8788$new_n2229 $abc$8788$new_n2224 $abc$8788$new_n2231 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n2223 +11100 1 +11111 1 +.names $abc$8788$new_n2228 $abc$8788$new_n2225 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n2227 $abc$8788$new_n2224 +11000 1 +11110 1 +.names $abc$8788$new_n2226 $abc$8788$new_n1797 _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] $abc$8788$new_n2225 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n2226 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] $abc$8788$new_n2227 +01 1 +10 1 +.names _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] $abc$8788$new_n2228 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$8788$new_n2230 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] $abc$8788$new_n2229 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n2230 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n2232 $abc$8788$new_n2231 +00000 1 +00110 1 +11000 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n2232 +01 1 +10 1 +.names $abc$8788$new_n2234 _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] $abc$8788$new_n2233 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n2234 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] $abc$8788$new_n2235 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$8788$new_n2239 $abc$8788$new_n2237 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] $abc$8788$new_n2236 +1100 1 +1111 1 +.names $abc$8788$new_n2238 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n2237 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n2238 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] $abc$8788$new_n2240 $abc$8788$new_n2239 +00000 1 +00110 1 +11000 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n2240 +01 1 +10 1 +.names $abc$8788$new_n2243 $abc$8788$new_n1802 $abc$8788$new_n2244 dBus_cmd_payload_address[31] $abc$8788$new_n1797 $abc$8788$new_n2242 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[13] dBus_cmd_payload_size[0] $abc$8788$new_n2221 switch_Misc_l241_1 $abc$8788$new_n2243 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n2244 +000 1 +.names $abc$8788$new_n1321 execute_to_memory_BRANCH_DO $abc$8788$new_n2245 +10 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n1321 $abc$8788$new_n2246 +00 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2248 execute_to_memory_REGFILE_WRITE_DATA[31] $abc$8788$new_n1323 $abc$8788$new_n2250 $abc$8788$auto$rtlil.cc:2693:MuxGate$7899 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[31] $abc$8788$new_n2249 $abc$8788$new_n2248 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n2249 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n2251 execute_LightShifterPlugin_isActive $abc$8788$new_n1592 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n2250 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n2251 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 dBus_cmd_payload_address[1] execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7901 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2254 decode_to_execute_SRC2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7903 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] _zz_decode_SRC2 $abc$8788$new_n2254 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2256 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7905 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2257 $abc$8788$new_n1937 _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2256 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2258 $abc$8788$new_n2257 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2258 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[31] decode_to_execute_RS2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7907 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[31] decode_to_execute_RS1[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7909 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2262 _zz_execute_BRANCH_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7911 +001 1 +011 1 +100 1 +101 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2262 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n2458 _zz_execute_SHIFT_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1937 $abc$8788$auto$rtlil.cc:2693:MuxGate$7913 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 _zz_execute_ALU_BITWISE_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7915 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1316 decode_to_execute_SRC_LESS_UNSIGNED IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7917 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2267 $abc$8788$auto$rtlil.cc:2693:MuxGate$7919 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$new_n2267 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1321 _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$8788$auto$rtlil.cc:2693:MuxGate$7921 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_ENV_CTRL $abc$8788$new_n1296 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7923 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1296 decode_to_execute_IS_CSR IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7925 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_wr $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7927 +10 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_47 dBus_cmd_payload_wr $abc$8788$auto$rtlil.cc:2693:MuxGate$7929 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$8788$auto$rtlil.cc:2693:MuxGate$7931 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2275 decode_to_execute_REGFILE_WRITE_VALID $abc$8788$new_n2277 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7935 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8788$new_n2276 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2275 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n2276 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n2277 +0000 1 +.names decode_to_execute_MEMORY_ENABLE $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7937 +01 1 +10 1 +11 1 +.names $abc$8788$new_n2458 decode_to_execute_MEMORY_ENABLE IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7939 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +11000 1 +.names $abc$8788$new_n2257 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_4 $abc$8788$auto$rtlil.cc:2693:MuxGate$7941 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2458 decode_to_execute_CSR_WRITE_OPCODE $abc$8788$new_n2282 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7943 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2282 +10000 1 +.names $abc$8788$new_n2458 _zz_decode_SRC2 _zz_execute_BranchPlugin_branch_src2 $abc$8788$auto$rtlil.cc:2693:MuxGate$7947 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC2 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] decode_INSTRUCTION_ANTICIPATED[31] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2287 $abc$8788$new_n2286 BranchPlugin_jumpInterface_payload[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7965 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2059 $abc$8788$new_n2005 $abc$8788$new_n2286 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2020 decode_to_execute_PC[31] decode_to_execute_RS1[31] $abc$8788$new_n2287 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7971 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[31] decode_to_execute_PC[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7973 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[11] _zz_RegFilePlugin_regFile_port0[11] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7979 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2292 _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7983 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz_RegFilePlugin_regFile_port0[4] $abc$8788$new_n2292 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2294 _zz_execute_SrcPlugin_addSub_2[31] _zz_RegFilePlugin_regFile_port0[31] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7985 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC2 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2294 +1110 1 +.names decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$new_n1321 dBus_cmd_valid +1110 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[8] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[9] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[10] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[11] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[12] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[13] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[14] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[15] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[16] dBus_cmd_payload_data[0] dBus_cmd_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[17] dBus_cmd_payload_data[1] dBus_cmd_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[18] dBus_cmd_payload_data[2] dBus_cmd_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[19] dBus_cmd_payload_data[3] dBus_cmd_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[20] dBus_cmd_payload_data[4] dBus_cmd_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[21] dBus_cmd_payload_data[5] dBus_cmd_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[22] dBus_cmd_payload_data[6] dBus_cmd_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[23] dBus_cmd_payload_data[7] dBus_cmd_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[24] decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[24] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[25] decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[25] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[26] decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[26] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[27] decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[27] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[28] decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[28] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[29] decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[29] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[30] decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[30] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[31] decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[31] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2321 $abc$8788$new_n1492 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2321 +1111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] decode_INSTRUCTION_ANTICIPATED[15] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] decode_INSTRUCTION_ANTICIPATED[16] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] decode_INSTRUCTION_ANTICIPATED[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] decode_INSTRUCTION_ANTICIPATED[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] decode_INSTRUCTION_ANTICIPATED[19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] decode_INSTRUCTION_ANTICIPATED[20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] decode_INSTRUCTION_ANTICIPATED[21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] decode_INSTRUCTION_ANTICIPATED[22] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] decode_INSTRUCTION_ANTICIPATED[23] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] decode_INSTRUCTION_ANTICIPATED[24] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1516 $abc$8788$new_n1272 $0\CsrPlugin_interrupt_valid[0:0] +10 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2334 $abc$8788$new_n2335 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] +000 1 +001 1 +100 1 +110 1 +.names IBusSimplePlugin_pending_value[0] $abc$8788$new_n1454 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2334 +0000 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2335 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01000 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2339 $abc$8788$new_n2338 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1454 IBusSimplePlugin_pending_value[0] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2337 +0001 1 +0010 1 +0011 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2338 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2339 +10001 1 +10010 1 +10011 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2341 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2339 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2341 +010 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[0] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][0] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2345 $abc$8788$new_n1500 $abc$8788$new_n2344 $abc$8788$new_n2343 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_768 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2344 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[12] switch_Misc_l241_1 dBus_cmd_payload_size[0] CsrPlugin_mstatus_MPP[1] execute_CsrPlugin_csr_768 $abc$8788$new_n2345 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][1] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2344 $abc$8788$new_n1496 $abc$8788$new_n2348 $0\CsrPlugin_mstatus_MPIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names $abc$8788$new_n1272 $abc$8788$new_n1274 CsrPlugin_mstatus_MIE CsrPlugin_mstatus_MPIE $abc$8788$new_n2348 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$8788$new_n2344 $abc$8788$new_n1492 $abc$8788$new_n2350 $0\CsrPlugin_mstatus_MIE[0:0] +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1274 CsrPlugin_mstatus_MPIE CsrPlugin_mstatus_MIE $abc$8788$new_n1272 $abc$8788$new_n2350 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names memory_arbitration_isValid $abc$8788$new_n1271 $abc$8788$new_n1321 $0\writeBack_arbitration_isValid[0:0] +110 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2353 memory_to_writeBack_REGFILE_WRITE_DATA[0] lastStageRegFileWrite_payload_data[0] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2354 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[16] $abc$8788$new_n2353 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[8] memory_to_writeBack_MEMORY_READ_DATA[0] $abc$8788$new_n2354 +000 1 +010 1 +100 1 +101 1 +.names memory_to_writeBack_MEMORY_ENABLE lastStageIsFiring $abc$8788$new_n2355 +11 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2357 memory_to_writeBack_REGFILE_WRITE_DATA[1] lastStageRegFileWrite_payload_data[1] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2358 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[17] $abc$8788$new_n2357 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[9] memory_to_writeBack_MEMORY_READ_DATA[1] $abc$8788$new_n2358 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2360 memory_to_writeBack_REGFILE_WRITE_DATA[2] lastStageRegFileWrite_payload_data[2] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2361 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[18] $abc$8788$new_n2360 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[10] memory_to_writeBack_MEMORY_READ_DATA[2] $abc$8788$new_n2361 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2363 memory_to_writeBack_REGFILE_WRITE_DATA[3] lastStageRegFileWrite_payload_data[3] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2364 writeBack_MEMORY_READ_DATA[27] memory_to_writeBack_MEMORY_READ_DATA[19] $abc$8788$new_n2363 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[11] memory_to_writeBack_MEMORY_READ_DATA[3] $abc$8788$new_n2364 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2366 memory_to_writeBack_REGFILE_WRITE_DATA[4] lastStageRegFileWrite_payload_data[4] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2367 writeBack_MEMORY_READ_DATA[28] writeBack_MEMORY_READ_DATA[20] $abc$8788$new_n2366 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[12] memory_to_writeBack_MEMORY_READ_DATA[4] $abc$8788$new_n2367 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2369 memory_to_writeBack_REGFILE_WRITE_DATA[5] lastStageRegFileWrite_payload_data[5] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2370 writeBack_MEMORY_READ_DATA[29] writeBack_MEMORY_READ_DATA[21] $abc$8788$new_n2369 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[13] memory_to_writeBack_MEMORY_READ_DATA[5] $abc$8788$new_n2370 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2372 memory_to_writeBack_REGFILE_WRITE_DATA[6] lastStageRegFileWrite_payload_data[6] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2373 writeBack_MEMORY_READ_DATA[30] writeBack_MEMORY_READ_DATA[22] $abc$8788$new_n2372 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[14] memory_to_writeBack_MEMORY_READ_DATA[6] $abc$8788$new_n2373 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2375 memory_to_writeBack_REGFILE_WRITE_DATA[7] lastStageRegFileWrite_payload_data[7] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2376 writeBack_MEMORY_READ_DATA[31] writeBack_MEMORY_READ_DATA[23] $abc$8788$new_n2375 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[15] memory_to_writeBack_MEMORY_READ_DATA[7] $abc$8788$new_n2376 +000 1 +010 1 +100 1 +101 1 +.names _zz_5 $abc$8788$new_n2379 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[8] lastStageRegFileWrite_payload_data[8] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2355 _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2375 _zz_lastStageRegFileWrite_payload_address[14] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2378 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[8] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2379 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2380 +10 1 +.names _zz_5 $abc$8788$new_n2382 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[9] lastStageRegFileWrite_payload_data[9] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[9] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2382 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2384 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[10] lastStageRegFileWrite_payload_data[10] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[10] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2384 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2386 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[11] lastStageRegFileWrite_payload_data[11] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[27] memory_to_writeBack_MEMORY_READ_DATA[11] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2386 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2388 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[12] lastStageRegFileWrite_payload_data[12] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[28] memory_to_writeBack_MEMORY_READ_DATA[12] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2388 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2390 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[13] lastStageRegFileWrite_payload_data[13] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[29] memory_to_writeBack_MEMORY_READ_DATA[13] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2390 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2392 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[14] lastStageRegFileWrite_payload_data[14] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[30] memory_to_writeBack_MEMORY_READ_DATA[14] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2392 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2394 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[15] lastStageRegFileWrite_payload_data[15] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2394 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[31] memory_to_writeBack_MEMORY_READ_DATA[15] $abc$8788$new_n2395 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2397 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[16] lastStageRegFileWrite_payload_data[16] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[16] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2397 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2378 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[14] $abc$8788$new_n2398 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2400 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[17] lastStageRegFileWrite_payload_data[17] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[17] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2400 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2402 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[18] lastStageRegFileWrite_payload_data[18] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[18] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2402 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2404 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[19] lastStageRegFileWrite_payload_data[19] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[19] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2404 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2406 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[20] lastStageRegFileWrite_payload_data[20] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[20] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2406 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2408 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[21] lastStageRegFileWrite_payload_data[21] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[21] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2408 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2410 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[22] lastStageRegFileWrite_payload_data[22] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[22] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2410 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2412 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[23] lastStageRegFileWrite_payload_data[23] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[23] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2412 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2414 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[24] lastStageRegFileWrite_payload_data[24] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[24] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2414 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2416 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[25] lastStageRegFileWrite_payload_data[25] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[25] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2416 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2418 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[26] lastStageRegFileWrite_payload_data[26] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[26] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2418 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2420 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[27] lastStageRegFileWrite_payload_data[27] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[27] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2420 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2422 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[28] lastStageRegFileWrite_payload_data[28] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[28] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2422 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2424 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[29] lastStageRegFileWrite_payload_data[29] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[29] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2424 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2426 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[30] lastStageRegFileWrite_payload_data[30] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[30] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2426 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2428 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[31] lastStageRegFileWrite_payload_data[31] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[31] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2428 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_5 lastStageRegFileWrite_payload_address[0] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_5 lastStageRegFileWrite_payload_address[1] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_5 lastStageRegFileWrite_payload_address[2] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_5 lastStageRegFileWrite_payload_address[3] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_5 lastStageRegFileWrite_payload_address[4] +10 1 +.names _zz_5 HazardSimplePlugin_writeBackWrites_valid _zz_1 +01 1 +10 1 +11 1 +.names IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[1] +001 1 +010 1 +100 1 +111 1 +.names $abc$8788$new_n1505 $abc$8788$new_n2334 $abc$8788$new_n2436 +10 1 +.names IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[2] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$8788$new_n1505 $abc$8788$new_n2334 IBusSimplePlugin_pending_next[0] +00 1 +11 1 +.names $abc$8788$new_n1283 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] execute_to_memory_INSTRUCTION[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] execute_to_memory_INSTRUCTION[9] $abc$8788$new_n2439 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2439 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] execute_to_memory_INSTRUCTION[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n2440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2442 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2442 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2443 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n1304 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] execute_to_memory_INSTRUCTION[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] execute_to_memory_INSTRUCTION[8] $abc$8788$new_n2445 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2445 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] execute_to_memory_INSTRUCTION[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] execute_to_memory_INSTRUCTION[10] $abc$8788$new_n2446 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2448 +10000 1 +10011 1 +11100 1 +11111 1 +.names decode_to_execute_REGFILE_WRITE_VALID IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2_4[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n2449 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2448 $abc$8788$new_n2449 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2450 +1100 1 +1111 1 +.names HazardSimplePlugin_writeBackBuffer_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackBuffer_payload_address[0] HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2451 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2451 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2452 +10000 1 +10011 1 +11100 1 +11111 1 +.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2454 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2454 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2455 +10000 1 +10011 1 +11100 1 +11111 1 +.names decode_to_execute_IS_CSR memory_arbitration_isValid lastStageIsFiring decode_to_execute_MEMORY_ENABLE dBus_cmd_ready $abc$8788$new_n2457 +00010 1 +00110 1 +01010 1 +01110 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_arbitration_isValid $abc$8788$new_n2457 $abc$8788$new_n1323 $abc$8788$new_n1325 $abc$8788$new_n2458 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2452 HazardSimplePlugin_writeBackBuffer_payload_address[4] $abc$8788$new_n2455 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2459 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$8788$new_n1278 $abc$8788$new_n1315 $abc$8788$new_n2446 $abc$8788$new_n2459 $abc$8788$new_n2450 $abc$8788$new_n2460 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1328 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2460 $abc$8788$new_n2461 +1100 1 +1101 1 +1110 1 +.names $abc$8788$new_n1285 decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$new_n2462 +11100 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n2443 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2462 _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2463 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2463 $abc$8788$new_n1288 $abc$8788$new_n2440 $abc$8788$new_n2464 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7861 Q=CsrPlugin_mcause_exceptionCode[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7969 Q=CsrPlugin_mcause_exceptionCode[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7957 Q=CsrPlugin_interrupt_code[3] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[15] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[16] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[17] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[18] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[19] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[20] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[21] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[22] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[23] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[24] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7859 Q=decode_to_execute_PC[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7857 Q=decode_to_execute_PC[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7855 Q=decode_to_execute_PC[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7853 Q=decode_to_execute_PC[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7851 Q=decode_to_execute_PC[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7849 Q=decode_to_execute_PC[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7847 Q=decode_to_execute_PC[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7845 Q=decode_to_execute_PC[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7843 Q=decode_to_execute_PC[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7841 Q=decode_to_execute_PC[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7839 Q=decode_to_execute_PC[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7837 Q=decode_to_execute_PC[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7835 Q=decode_to_execute_PC[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7833 Q=decode_to_execute_PC[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7831 Q=decode_to_execute_PC[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7829 Q=decode_to_execute_PC[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7827 Q=decode_to_execute_PC[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7825 Q=decode_to_execute_PC[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7823 Q=decode_to_execute_PC[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7821 Q=decode_to_execute_PC[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7819 Q=decode_to_execute_PC[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7817 Q=decode_to_execute_PC[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7815 Q=decode_to_execute_PC[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7813 Q=decode_to_execute_PC[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7811 Q=decode_to_execute_PC[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7809 Q=decode_to_execute_PC[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7807 Q=decode_to_execute_PC[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7805 Q=decode_to_execute_PC[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7803 Q=decode_to_execute_PC[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7973 Q=decode_to_execute_PC[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7797 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7795 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7793 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7791 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7789 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7787 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7785 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7783 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7781 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7779 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7777 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7775 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7773 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7771 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7769 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7767 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7765 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7763 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7761 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7759 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7757 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7755 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7753 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7751 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7749 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7747 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7745 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7743 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7741 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7963 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7953 Q=CsrPlugin_interrupt_code[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7739 Q=_zz_execute_SrcPlugin_addSub_2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7735 Q=_zz_execute_SrcPlugin_addSub_2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7731 Q=_zz_execute_SrcPlugin_addSub_2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7727 Q=_zz_execute_SrcPlugin_addSub_2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7723 Q=_zz_execute_SrcPlugin_addSub_2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7719 Q=_zz_execute_SrcPlugin_addSub_2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7979 Q=_zz_execute_SrcPlugin_addSub_2[11] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7863 Q=execute_LightShifterPlugin_isActive R=reset +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7715 Q=_zz_execute_SrcPlugin_addSub_2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7711 Q=_zz_execute_SrcPlugin_addSub_2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7707 Q=_zz_execute_SrcPlugin_addSub_2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7983 Q=_zz_execute_SrcPlugin_addSub_2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7703 Q=_zz_execute_SrcPlugin_addSub_2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7701 Q=_zz_execute_SrcPlugin_addSub_2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7699 Q=_zz_execute_SrcPlugin_addSub_2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7697 Q=_zz_execute_SrcPlugin_addSub_2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7695 Q=_zz_execute_SrcPlugin_addSub_2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7693 Q=_zz_execute_SrcPlugin_addSub_2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7691 Q=_zz_execute_SrcPlugin_addSub_2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7689 Q=_zz_execute_SrcPlugin_addSub_2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7687 Q=_zz_execute_SrcPlugin_addSub_2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7685 Q=_zz_execute_SrcPlugin_addSub_2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7683 Q=_zz_execute_SrcPlugin_addSub_2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7681 Q=_zz_execute_SrcPlugin_addSub_2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7679 Q=_zz_execute_SrcPlugin_addSub_2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7677 Q=_zz_execute_SrcPlugin_addSub_2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7675 Q=_zz_execute_SrcPlugin_addSub_2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7673 Q=_zz_execute_SrcPlugin_addSub_2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7671 Q=_zz_execute_SrcPlugin_addSub_2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7669 Q=_zz_execute_SrcPlugin_addSub_2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7667 Q=_zz_execute_SrcPlugin_addSub_2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7665 Q=_zz_execute_SrcPlugin_addSub_2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7985 Q=_zz_execute_SrcPlugin_addSub_2[31] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7961 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=reset +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[2] Q=_zz_decode_SRC_LESS_UNSIGNED_4 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[3] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[4] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[5] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_47 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[6] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[7] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[8] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[9] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[10] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[11] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[12] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_13 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[13] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[14] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[25] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[26] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[27] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[28] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[29] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[30] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[31] Q=_zz_decode_SRC2 +.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP +.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP +.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7619 Q=BranchPlugin_jumpInterface_payload[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7617 Q=BranchPlugin_jumpInterface_payload[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7615 Q=BranchPlugin_jumpInterface_payload[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7613 Q=BranchPlugin_jumpInterface_payload[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7611 Q=BranchPlugin_jumpInterface_payload[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7609 Q=BranchPlugin_jumpInterface_payload[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7607 Q=BranchPlugin_jumpInterface_payload[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7605 Q=BranchPlugin_jumpInterface_payload[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7603 Q=BranchPlugin_jumpInterface_payload[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7601 Q=BranchPlugin_jumpInterface_payload[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7599 Q=BranchPlugin_jumpInterface_payload[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7597 Q=BranchPlugin_jumpInterface_payload[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7595 Q=BranchPlugin_jumpInterface_payload[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7593 Q=BranchPlugin_jumpInterface_payload[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7591 Q=BranchPlugin_jumpInterface_payload[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7589 Q=BranchPlugin_jumpInterface_payload[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7587 Q=BranchPlugin_jumpInterface_payload[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7585 Q=BranchPlugin_jumpInterface_payload[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7583 Q=BranchPlugin_jumpInterface_payload[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7581 Q=BranchPlugin_jumpInterface_payload[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7579 Q=BranchPlugin_jumpInterface_payload[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7577 Q=BranchPlugin_jumpInterface_payload[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7575 Q=BranchPlugin_jumpInterface_payload[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7573 Q=BranchPlugin_jumpInterface_payload[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7571 Q=BranchPlugin_jumpInterface_payload[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7569 Q=BranchPlugin_jumpInterface_payload[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7567 Q=BranchPlugin_jumpInterface_payload[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7565 Q=BranchPlugin_jumpInterface_payload[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7563 Q=BranchPlugin_jumpInterface_payload[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7965 Q=BranchPlugin_jumpInterface_payload[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7561 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7559 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7557 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7555 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7553 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7551 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7549 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7547 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7545 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7543 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7541 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7539 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7537 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7535 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7533 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7531 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7529 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7527 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7525 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7523 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7521 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7519 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7517 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7515 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7513 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7511 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7509 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7507 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7505 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7971 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[31] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7503 Q=execute_LightShifterPlugin_amplitudeReg[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7501 Q=execute_LightShifterPlugin_amplitudeReg[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7499 Q=execute_LightShifterPlugin_amplitudeReg[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7497 Q=execute_LightShifterPlugin_amplitudeReg[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7949 Q=execute_LightShifterPlugin_amplitudeReg[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7495 Q=CsrPlugin_mepc[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7493 Q=CsrPlugin_mepc[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7491 Q=CsrPlugin_mepc[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7489 Q=CsrPlugin_mepc[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7487 Q=CsrPlugin_mepc[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7485 Q=CsrPlugin_mepc[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7483 Q=CsrPlugin_mepc[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7481 Q=CsrPlugin_mepc[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7479 Q=CsrPlugin_mepc[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7477 Q=CsrPlugin_mepc[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7475 Q=CsrPlugin_mepc[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7473 Q=CsrPlugin_mepc[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7471 Q=CsrPlugin_mepc[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7469 Q=CsrPlugin_mepc[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7467 Q=CsrPlugin_mepc[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7465 Q=CsrPlugin_mepc[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7463 Q=CsrPlugin_mepc[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7461 Q=CsrPlugin_mepc[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7459 Q=CsrPlugin_mepc[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7457 Q=CsrPlugin_mepc[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7455 Q=CsrPlugin_mepc[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7453 Q=CsrPlugin_mepc[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7451 Q=CsrPlugin_mepc[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7449 Q=CsrPlugin_mepc[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7447 Q=CsrPlugin_mepc[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7445 Q=CsrPlugin_mepc[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7443 Q=CsrPlugin_mepc[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7441 Q=CsrPlugin_mepc[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7439 Q=CsrPlugin_mepc[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7975 Q=CsrPlugin_mepc[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7423 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7421 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7419 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7417 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7415 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7413 Q=dBus_cmd_payload_size[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7411 Q=switch_Misc_l241_1 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7409 Q=_zz__zz_execute_BranchPlugin_branch_src2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7407 Q=_zz__zz_execute_BranchPlugin_branch_src2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7405 Q=_zz__zz_execute_BranchPlugin_branch_src2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7403 Q=_zz__zz_execute_BranchPlugin_branch_src2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7401 Q=_zz__zz_execute_BranchPlugin_branch_src2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7399 Q=_zz__zz_execute_BranchPlugin_branch_src2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7397 Q=_zz__zz_execute_BranchPlugin_branch_src2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7395 Q=_zz__zz_execute_BranchPlugin_branch_src2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7393 Q=_zz__zz_execute_BranchPlugin_branch_src2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7391 Q=_zz__zz_execute_BranchPlugin_branch_src2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7389 Q=_zz__zz_execute_BranchPlugin_branch_src2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7387 Q=_zz__zz_execute_BranchPlugin_branch_src2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7385 Q=_zz__zz_execute_BranchPlugin_branch_src2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7383 Q=_zz__zz_execute_BranchPlugin_branch_src2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7381 Q=_zz__zz_execute_BranchPlugin_branch_src2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7379 Q=_zz__zz_execute_BranchPlugin_branch_src2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7377 Q=_zz__zz_execute_BranchPlugin_branch_src2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7947 Q=_zz_execute_BranchPlugin_branch_src2 +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[7] Q=HazardSimplePlugin_writeBackWrites_payload_address[0] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[8] Q=HazardSimplePlugin_writeBackWrites_payload_address[1] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[9] Q=HazardSimplePlugin_writeBackWrites_payload_address[2] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[10] Q=HazardSimplePlugin_writeBackWrites_payload_address[3] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[11] Q=HazardSimplePlugin_writeBackWrites_payload_address[4] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[12] Q=_zz_lastStageRegFileWrite_payload_address[12] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[13] Q=_zz_lastStageRegFileWrite_payload_address[13] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[14] Q=_zz_lastStageRegFileWrite_payload_address[14] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[28] Q=_zz_lastStageRegFileWrite_payload_address[28] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[29] Q=_zz_lastStageRegFileWrite_payload_address[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7361 Q=execute_to_memory_INSTRUCTION[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7359 Q=execute_to_memory_INSTRUCTION[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7357 Q=execute_to_memory_INSTRUCTION[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7355 Q=execute_to_memory_INSTRUCTION[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7353 Q=execute_to_memory_INSTRUCTION[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7351 Q=execute_to_memory_INSTRUCTION[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7349 Q=execute_to_memory_INSTRUCTION[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7347 Q=execute_to_memory_INSTRUCTION[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7319 Q=execute_to_memory_INSTRUCTION[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7317 Q=execute_to_memory_INSTRUCTION[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7943 Q=decode_to_execute_CSR_WRITE_OPCODE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7941 Q=_zz_execute_SrcPlugin_addSub_4 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7939 Q=decode_to_execute_MEMORY_ENABLE +.subckt dff C=clk D=execute_to_memory_MEMORY_ENABLE Q=memory_to_writeBack_MEMORY_ENABLE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7935 Q=decode_to_execute_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7937 Q=execute_to_memory_MEMORY_ENABLE +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_VALID Q=_zz_lastStageRegFileWrite_valid +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7931 Q=execute_to_memory_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7929 Q=dBus_cmd_payload_wr +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7927 Q=execute_to_memory_MEMORY_STORE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7925 Q=decode_to_execute_IS_CSR +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7923 Q=_zz_execute_ENV_CTRL +.subckt dff C=clk D=_zz_memory_ENV_CTRL Q=_zz_writeBack_ENV_CTRL +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7921 Q=_zz_memory_ENV_CTRL +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7313 Q=_zz_execute_ALU_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7919 Q=_zz_execute_ALU_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7917 Q=decode_to_execute_SRC_LESS_UNSIGNED +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7311 Q=_zz_execute_ALU_BITWISE_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7915 Q=_zz_execute_ALU_BITWISE_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7309 Q=_zz_execute_SHIFT_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7913 Q=_zz_execute_SHIFT_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7307 Q=_zz_execute_BRANCH_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7911 Q=_zz_execute_BRANCH_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7305 Q=decode_to_execute_RS1[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7303 Q=decode_to_execute_RS1[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7301 Q=decode_to_execute_RS1[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7299 Q=decode_to_execute_RS1[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7297 Q=decode_to_execute_RS1[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7295 Q=decode_to_execute_RS1[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7293 Q=decode_to_execute_RS1[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7291 Q=decode_to_execute_RS1[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7289 Q=decode_to_execute_RS1[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7287 Q=decode_to_execute_RS1[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7285 Q=decode_to_execute_RS1[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7283 Q=decode_to_execute_RS1[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7281 Q=decode_to_execute_RS1[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7279 Q=decode_to_execute_RS1[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7277 Q=decode_to_execute_RS1[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7275 Q=decode_to_execute_RS1[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7273 Q=decode_to_execute_RS1[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7271 Q=decode_to_execute_RS1[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7269 Q=decode_to_execute_RS1[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7267 Q=decode_to_execute_RS1[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7265 Q=decode_to_execute_RS1[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7263 Q=decode_to_execute_RS1[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7261 Q=decode_to_execute_RS1[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7259 Q=decode_to_execute_RS1[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7257 Q=decode_to_execute_RS1[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7255 Q=decode_to_execute_RS1[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7253 Q=decode_to_execute_RS1[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7251 Q=decode_to_execute_RS1[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7249 Q=decode_to_execute_RS1[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7247 Q=decode_to_execute_RS1[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7245 Q=decode_to_execute_RS1[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7909 Q=decode_to_execute_RS1[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7243 Q=dBus_cmd_payload_data[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7241 Q=dBus_cmd_payload_data[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7239 Q=dBus_cmd_payload_data[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7237 Q=dBus_cmd_payload_data[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7235 Q=dBus_cmd_payload_data[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7233 Q=dBus_cmd_payload_data[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7231 Q=dBus_cmd_payload_data[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7229 Q=dBus_cmd_payload_data[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7227 Q=decode_to_execute_RS2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7225 Q=decode_to_execute_RS2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7223 Q=decode_to_execute_RS2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7221 Q=decode_to_execute_RS2[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7219 Q=decode_to_execute_RS2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7217 Q=decode_to_execute_RS2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7215 Q=decode_to_execute_RS2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7213 Q=decode_to_execute_RS2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7211 Q=decode_to_execute_RS2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7209 Q=decode_to_execute_RS2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7207 Q=decode_to_execute_RS2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7205 Q=decode_to_execute_RS2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7203 Q=decode_to_execute_RS2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7201 Q=decode_to_execute_RS2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7199 Q=decode_to_execute_RS2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7197 Q=decode_to_execute_RS2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7195 Q=decode_to_execute_RS2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7193 Q=decode_to_execute_RS2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7191 Q=decode_to_execute_RS2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7189 Q=decode_to_execute_RS2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7187 Q=decode_to_execute_RS2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7185 Q=decode_to_execute_RS2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7183 Q=decode_to_execute_RS2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7907 Q=decode_to_execute_RS2[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7905 Q=decode_to_execute_SRC2_FORCE_ZERO +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7181 Q=decode_to_execute_SRC2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7179 Q=decode_to_execute_SRC2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7177 Q=decode_to_execute_SRC2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7175 Q=decode_to_execute_SRC2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7173 Q=decode_to_execute_SRC2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7171 Q=decode_to_execute_SRC2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7169 Q=decode_to_execute_SRC2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7167 Q=decode_to_execute_SRC2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7165 Q=decode_to_execute_SRC2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7163 Q=decode_to_execute_SRC2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7161 Q=decode_to_execute_SRC2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7159 Q=decode_to_execute_SRC2[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7157 Q=decode_to_execute_SRC2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7155 Q=decode_to_execute_SRC2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7153 Q=decode_to_execute_SRC2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7151 Q=decode_to_execute_SRC2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7149 Q=decode_to_execute_SRC2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7147 Q=decode_to_execute_SRC2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7145 Q=decode_to_execute_SRC2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7143 Q=decode_to_execute_SRC2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7141 Q=decode_to_execute_SRC2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7139 Q=decode_to_execute_SRC2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7137 Q=decode_to_execute_SRC2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7135 Q=decode_to_execute_SRC2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7133 Q=decode_to_execute_SRC2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7131 Q=decode_to_execute_SRC2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7129 Q=decode_to_execute_SRC2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7127 Q=decode_to_execute_SRC2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7125 Q=decode_to_execute_SRC2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7123 Q=decode_to_execute_SRC2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7121 Q=decode_to_execute_SRC2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7903 Q=decode_to_execute_SRC2[31] +.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[0] +.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7119 Q=execute_to_memory_MEMORY_ADDRESS_LOW[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7901 Q=execute_to_memory_MEMORY_ADDRESS_LOW[1] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[0] Q=memory_to_writeBack_REGFILE_WRITE_DATA[0] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[1] Q=memory_to_writeBack_REGFILE_WRITE_DATA[1] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[2] Q=memory_to_writeBack_REGFILE_WRITE_DATA[2] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[3] Q=memory_to_writeBack_REGFILE_WRITE_DATA[3] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[4] Q=memory_to_writeBack_REGFILE_WRITE_DATA[4] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[5] Q=memory_to_writeBack_REGFILE_WRITE_DATA[5] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[6] Q=memory_to_writeBack_REGFILE_WRITE_DATA[6] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[7] Q=memory_to_writeBack_REGFILE_WRITE_DATA[7] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[8] Q=memory_to_writeBack_REGFILE_WRITE_DATA[8] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[9] Q=memory_to_writeBack_REGFILE_WRITE_DATA[9] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[10] Q=memory_to_writeBack_REGFILE_WRITE_DATA[10] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[11] Q=memory_to_writeBack_REGFILE_WRITE_DATA[11] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[12] Q=memory_to_writeBack_REGFILE_WRITE_DATA[12] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[13] Q=memory_to_writeBack_REGFILE_WRITE_DATA[13] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[14] Q=memory_to_writeBack_REGFILE_WRITE_DATA[14] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[15] Q=memory_to_writeBack_REGFILE_WRITE_DATA[15] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[16] Q=memory_to_writeBack_REGFILE_WRITE_DATA[16] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[17] Q=memory_to_writeBack_REGFILE_WRITE_DATA[17] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[18] Q=memory_to_writeBack_REGFILE_WRITE_DATA[18] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[19] Q=memory_to_writeBack_REGFILE_WRITE_DATA[19] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[20] Q=memory_to_writeBack_REGFILE_WRITE_DATA[20] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[21] Q=memory_to_writeBack_REGFILE_WRITE_DATA[21] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[22] Q=memory_to_writeBack_REGFILE_WRITE_DATA[22] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[23] Q=memory_to_writeBack_REGFILE_WRITE_DATA[23] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[24] Q=memory_to_writeBack_REGFILE_WRITE_DATA[24] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[25] Q=memory_to_writeBack_REGFILE_WRITE_DATA[25] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[26] Q=memory_to_writeBack_REGFILE_WRITE_DATA[26] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[27] Q=memory_to_writeBack_REGFILE_WRITE_DATA[27] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[28] Q=memory_to_writeBack_REGFILE_WRITE_DATA[28] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[29] Q=memory_to_writeBack_REGFILE_WRITE_DATA[29] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[30] Q=memory_to_writeBack_REGFILE_WRITE_DATA[30] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[31] Q=memory_to_writeBack_REGFILE_WRITE_DATA[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7897 Q=execute_to_memory_BRANCH_DO +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7117 Q=execute_to_memory_REGFILE_WRITE_DATA[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7115 Q=execute_to_memory_REGFILE_WRITE_DATA[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7113 Q=execute_to_memory_REGFILE_WRITE_DATA[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7111 Q=execute_to_memory_REGFILE_WRITE_DATA[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7109 Q=execute_to_memory_REGFILE_WRITE_DATA[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7107 Q=execute_to_memory_REGFILE_WRITE_DATA[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7105 Q=execute_to_memory_REGFILE_WRITE_DATA[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7103 Q=execute_to_memory_REGFILE_WRITE_DATA[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7101 Q=execute_to_memory_REGFILE_WRITE_DATA[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7099 Q=execute_to_memory_REGFILE_WRITE_DATA[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7097 Q=execute_to_memory_REGFILE_WRITE_DATA[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7095 Q=execute_to_memory_REGFILE_WRITE_DATA[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7093 Q=execute_to_memory_REGFILE_WRITE_DATA[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7091 Q=execute_to_memory_REGFILE_WRITE_DATA[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7089 Q=execute_to_memory_REGFILE_WRITE_DATA[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7087 Q=execute_to_memory_REGFILE_WRITE_DATA[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7085 Q=execute_to_memory_REGFILE_WRITE_DATA[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7083 Q=execute_to_memory_REGFILE_WRITE_DATA[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7081 Q=execute_to_memory_REGFILE_WRITE_DATA[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7079 Q=execute_to_memory_REGFILE_WRITE_DATA[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7077 Q=execute_to_memory_REGFILE_WRITE_DATA[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7075 Q=execute_to_memory_REGFILE_WRITE_DATA[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7073 Q=execute_to_memory_REGFILE_WRITE_DATA[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7071 Q=execute_to_memory_REGFILE_WRITE_DATA[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7069 Q=execute_to_memory_REGFILE_WRITE_DATA[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7067 Q=execute_to_memory_REGFILE_WRITE_DATA[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7065 Q=execute_to_memory_REGFILE_WRITE_DATA[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7063 Q=execute_to_memory_REGFILE_WRITE_DATA[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7061 Q=execute_to_memory_REGFILE_WRITE_DATA[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7059 Q=execute_to_memory_REGFILE_WRITE_DATA[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7057 Q=execute_to_memory_REGFILE_WRITE_DATA[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7899 Q=execute_to_memory_REGFILE_WRITE_DATA[31] +.subckt dff C=clk D=dBus_rsp_data[0] Q=memory_to_writeBack_MEMORY_READ_DATA[0] +.subckt dff C=clk D=dBus_rsp_data[1] Q=memory_to_writeBack_MEMORY_READ_DATA[1] +.subckt dff C=clk D=dBus_rsp_data[2] Q=memory_to_writeBack_MEMORY_READ_DATA[2] +.subckt dff C=clk D=dBus_rsp_data[3] Q=memory_to_writeBack_MEMORY_READ_DATA[3] +.subckt dff C=clk D=dBus_rsp_data[4] Q=memory_to_writeBack_MEMORY_READ_DATA[4] +.subckt dff C=clk D=dBus_rsp_data[5] Q=memory_to_writeBack_MEMORY_READ_DATA[5] +.subckt dff C=clk D=dBus_rsp_data[6] Q=memory_to_writeBack_MEMORY_READ_DATA[6] +.subckt dff C=clk D=dBus_rsp_data[7] Q=memory_to_writeBack_MEMORY_READ_DATA[7] +.subckt dff C=clk D=dBus_rsp_data[8] Q=memory_to_writeBack_MEMORY_READ_DATA[8] +.subckt dff C=clk D=dBus_rsp_data[9] Q=memory_to_writeBack_MEMORY_READ_DATA[9] +.subckt dff C=clk D=dBus_rsp_data[10] Q=memory_to_writeBack_MEMORY_READ_DATA[10] +.subckt dff C=clk D=dBus_rsp_data[11] Q=memory_to_writeBack_MEMORY_READ_DATA[11] +.subckt dff C=clk D=dBus_rsp_data[12] Q=memory_to_writeBack_MEMORY_READ_DATA[12] +.subckt dff C=clk D=dBus_rsp_data[13] Q=memory_to_writeBack_MEMORY_READ_DATA[13] +.subckt dff C=clk D=dBus_rsp_data[14] Q=memory_to_writeBack_MEMORY_READ_DATA[14] +.subckt dff C=clk D=dBus_rsp_data[15] Q=memory_to_writeBack_MEMORY_READ_DATA[15] +.subckt dff C=clk D=dBus_rsp_data[16] Q=memory_to_writeBack_MEMORY_READ_DATA[16] +.subckt dff C=clk D=dBus_rsp_data[17] Q=memory_to_writeBack_MEMORY_READ_DATA[17] +.subckt dff C=clk D=dBus_rsp_data[18] Q=memory_to_writeBack_MEMORY_READ_DATA[18] +.subckt dff C=clk D=dBus_rsp_data[19] Q=memory_to_writeBack_MEMORY_READ_DATA[19] +.subckt dff C=clk D=dBus_rsp_data[20] Q=writeBack_MEMORY_READ_DATA[20] +.subckt dff C=clk D=dBus_rsp_data[21] Q=writeBack_MEMORY_READ_DATA[21] +.subckt dff C=clk D=dBus_rsp_data[22] Q=writeBack_MEMORY_READ_DATA[22] +.subckt dff C=clk D=dBus_rsp_data[23] Q=writeBack_MEMORY_READ_DATA[23] +.subckt dff C=clk D=dBus_rsp_data[24] Q=writeBack_MEMORY_READ_DATA[24] +.subckt dff C=clk D=dBus_rsp_data[25] Q=writeBack_MEMORY_READ_DATA[25] +.subckt dff C=clk D=dBus_rsp_data[26] Q=writeBack_MEMORY_READ_DATA[26] +.subckt dff C=clk D=dBus_rsp_data[27] Q=writeBack_MEMORY_READ_DATA[27] +.subckt dff C=clk D=dBus_rsp_data[28] Q=writeBack_MEMORY_READ_DATA[28] +.subckt dff C=clk D=dBus_rsp_data[29] Q=writeBack_MEMORY_READ_DATA[29] +.subckt dff C=clk D=dBus_rsp_data[30] Q=writeBack_MEMORY_READ_DATA[30] +.subckt dff C=clk D=dBus_rsp_data[31] Q=writeBack_MEMORY_READ_DATA[31] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7055 Q=IBusSimplePlugin_fetchPc_pcReg[2] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7053 Q=IBusSimplePlugin_fetchPc_pcReg[3] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7051 Q=IBusSimplePlugin_fetchPc_pcReg[4] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7049 Q=IBusSimplePlugin_fetchPc_pcReg[5] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7047 Q=IBusSimplePlugin_fetchPc_pcReg[6] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7045 Q=IBusSimplePlugin_fetchPc_pcReg[7] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7043 Q=IBusSimplePlugin_fetchPc_pcReg[8] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7041 Q=IBusSimplePlugin_fetchPc_pcReg[9] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7039 Q=IBusSimplePlugin_fetchPc_pcReg[10] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7037 Q=IBusSimplePlugin_fetchPc_pcReg[11] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7035 Q=IBusSimplePlugin_fetchPc_pcReg[12] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7033 Q=IBusSimplePlugin_fetchPc_pcReg[13] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7031 Q=IBusSimplePlugin_fetchPc_pcReg[14] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7029 Q=IBusSimplePlugin_fetchPc_pcReg[15] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7027 Q=IBusSimplePlugin_fetchPc_pcReg[16] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7025 Q=IBusSimplePlugin_fetchPc_pcReg[17] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7023 Q=IBusSimplePlugin_fetchPc_pcReg[18] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7021 Q=IBusSimplePlugin_fetchPc_pcReg[19] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7019 Q=IBusSimplePlugin_fetchPc_pcReg[20] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7017 Q=IBusSimplePlugin_fetchPc_pcReg[21] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7015 Q=IBusSimplePlugin_fetchPc_pcReg[22] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7013 Q=IBusSimplePlugin_fetchPc_pcReg[23] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7011 Q=IBusSimplePlugin_fetchPc_pcReg[24] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7009 Q=IBusSimplePlugin_fetchPc_pcReg[25] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7007 Q=IBusSimplePlugin_fetchPc_pcReg[26] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7005 Q=IBusSimplePlugin_fetchPc_pcReg[27] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7003 Q=IBusSimplePlugin_fetchPc_pcReg[28] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7001 Q=IBusSimplePlugin_fetchPc_pcReg[29] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$6999 Q=IBusSimplePlugin_fetchPc_pcReg[30] R=reset +.subckt dffs C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7967 Q=IBusSimplePlugin_fetchPc_pcReg[31] S=reset +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7893 Q=execute_CsrPlugin_csr_768 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7891 Q=execute_CsrPlugin_csr_836 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7889 Q=execute_CsrPlugin_csr_772 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7887 Q=execute_CsrPlugin_csr_834 +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7885 Q=execute_arbitration_isValid R=reset +.subckt dffr C=clk D=$0\writeBack_arbitration_isValid[0:0] Q=lastStageIsFiring R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7883 Q=memory_arbitration_isValid R=reset +.subckt dffr C=clk D=$true Q=IBusSimplePlugin_fetchPc_booted R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7881 Q=IBusSimplePlugin_fetchPc_inc R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7879 Q=IBusSimplePlugin_iBusRsp_stages_1_input_valid R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[0] Q=IBusSimplePlugin_pending_value[0] R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[1] Q=IBusSimplePlugin_pending_value[1] R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[2] Q=IBusSimplePlugin_pending_value[2] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7877 Q=IBusSimplePlugin_injector_decodeInput_valid R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7875 Q=CsrPlugin_mie_MEIE R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7873 Q=CsrPlugin_mie_MTIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7871 Q=CsrPlugin_mie_MSIE R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7869 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7867 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset +.subckt dffs C=clk D=$false Q=_zz_5 S=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7865 Q=CsrPlugin_pipelineLiberator_done R=reset +.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2203[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2203[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2203[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2203[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2204[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2204[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2204[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2204[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.names $false BranchPlugin_jumpInterface_payload[0] +1 1 +.names $true CsrPlugin_interrupt_code[0] +1 1 +.names $true CsrPlugin_interrupt_code[1] +1 1 +.names $true CsrPlugin_mcause_exceptionCode[0] +1 1 +.names $true CsrPlugin_mcause_exceptionCode[1] +1 1 +.names $false CsrPlugin_mepc[0] +1 1 +.names $false CsrPlugin_mepc[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$2203[0] +1 1 +.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$2203[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$2203[2] +1 1 +.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$2203[3] +1 1 +.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$2203[4] +1 1 +.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$2203[5] +1 1 +.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$2203[6] +1 1 +.names _zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$2203[7] +1 1 +.names _zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$2203[8] +1 1 +.names _zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$2203[9] +1 1 +.names _zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$2203[10] +1 1 +.names _zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$2203[11] +1 1 +.names _zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$2203[12] +1 1 +.names _zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$2203[13] +1 1 +.names _zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$2203[14] +1 1 +.names _zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$2203[15] +1 1 +.names _zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$2203[16] +1 1 +.names _zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$2203[17] +1 1 +.names _zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$2203[18] +1 1 +.names _zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$2203[19] +1 1 +.names _zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$2203[20] +1 1 +.names _zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$2203[21] +1 1 +.names _zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$2203[22] +1 1 +.names _zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$2203[23] +1 1 +.names _zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$2203[24] +1 1 +.names _zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$2203[25] +1 1 +.names _zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$2203[26] +1 1 +.names _zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$2203[27] +1 1 +.names _zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$2203[28] +1 1 +.names _zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$2203[29] +1 1 +.names _zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$2203[30] +1 1 +.names _zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$2203[31] +1 1 +.names _zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$2204[0] +1 1 +.names _zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$2204[1] +1 1 +.names _zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$2204[2] +1 1 +.names _zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$2204[3] +1 1 +.names _zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$2204[4] +1 1 +.names _zz_RegFilePlugin_regFile_port0[5] $auto$memory_bram.cc:844:replace_memory$2204[5] +1 1 +.names _zz_RegFilePlugin_regFile_port0[6] $auto$memory_bram.cc:844:replace_memory$2204[6] +1 1 +.names _zz_RegFilePlugin_regFile_port0[7] $auto$memory_bram.cc:844:replace_memory$2204[7] +1 1 +.names _zz_RegFilePlugin_regFile_port0[8] $auto$memory_bram.cc:844:replace_memory$2204[8] +1 1 +.names _zz_RegFilePlugin_regFile_port0[9] $auto$memory_bram.cc:844:replace_memory$2204[9] +1 1 +.names _zz_RegFilePlugin_regFile_port0[10] $auto$memory_bram.cc:844:replace_memory$2204[10] +1 1 +.names _zz_RegFilePlugin_regFile_port0[11] $auto$memory_bram.cc:844:replace_memory$2204[11] +1 1 +.names _zz_RegFilePlugin_regFile_port0[12] $auto$memory_bram.cc:844:replace_memory$2204[12] +1 1 +.names _zz_RegFilePlugin_regFile_port0[13] $auto$memory_bram.cc:844:replace_memory$2204[13] +1 1 +.names _zz_RegFilePlugin_regFile_port0[14] $auto$memory_bram.cc:844:replace_memory$2204[14] +1 1 +.names _zz_RegFilePlugin_regFile_port0[15] $auto$memory_bram.cc:844:replace_memory$2204[15] +1 1 +.names _zz_RegFilePlugin_regFile_port0[16] $auto$memory_bram.cc:844:replace_memory$2204[16] +1 1 +.names _zz_RegFilePlugin_regFile_port0[17] $auto$memory_bram.cc:844:replace_memory$2204[17] +1 1 +.names _zz_RegFilePlugin_regFile_port0[18] $auto$memory_bram.cc:844:replace_memory$2204[18] +1 1 +.names _zz_RegFilePlugin_regFile_port0[19] $auto$memory_bram.cc:844:replace_memory$2204[19] +1 1 +.names _zz_RegFilePlugin_regFile_port0[20] $auto$memory_bram.cc:844:replace_memory$2204[20] +1 1 +.names _zz_RegFilePlugin_regFile_port0[21] $auto$memory_bram.cc:844:replace_memory$2204[21] +1 1 +.names _zz_RegFilePlugin_regFile_port0[22] $auto$memory_bram.cc:844:replace_memory$2204[22] +1 1 +.names _zz_RegFilePlugin_regFile_port0[23] $auto$memory_bram.cc:844:replace_memory$2204[23] +1 1 +.names _zz_RegFilePlugin_regFile_port0[24] $auto$memory_bram.cc:844:replace_memory$2204[24] +1 1 +.names _zz_RegFilePlugin_regFile_port0[25] $auto$memory_bram.cc:844:replace_memory$2204[25] +1 1 +.names _zz_RegFilePlugin_regFile_port0[26] $auto$memory_bram.cc:844:replace_memory$2204[26] +1 1 +.names _zz_RegFilePlugin_regFile_port0[27] $auto$memory_bram.cc:844:replace_memory$2204[27] +1 1 +.names _zz_RegFilePlugin_regFile_port0[28] $auto$memory_bram.cc:844:replace_memory$2204[28] +1 1 +.names _zz_RegFilePlugin_regFile_port0[29] $auto$memory_bram.cc:844:replace_memory$2204[29] +1 1 +.names _zz_RegFilePlugin_regFile_port0[30] $auto$memory_bram.cc:844:replace_memory$2204[30] +1 1 +.names _zz_RegFilePlugin_regFile_port0[31] $auto$memory_bram.cc:844:replace_memory$2204[31] +1 1 +.names $false IBusSimplePlugin_fetchPc_pcReg[0] +1 1 +.names $false IBusSimplePlugin_fetchPc_pcReg[1] +1 1 +.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[0] +1 1 +.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[1] +1 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] +1 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] +1 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] +1 1 +.names _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] +1 1 +.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[11] +1 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[12] +1 1 +.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[19] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[4] _zz__zz_execute_BranchPlugin_branch_src2_4[4] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2_4[5] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[6] _zz__zz_execute_BranchPlugin_branch_src2_4[6] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2_4[7] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[8] _zz__zz_execute_BranchPlugin_branch_src2_4[8] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[9] _zz__zz_execute_BranchPlugin_branch_src2_4[9] +1 1 +.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_4[11] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_lastStageRegFileWrite_payload_address[7] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_lastStageRegFileWrite_payload_address[8] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_lastStageRegFileWrite_payload_address[9] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_lastStageRegFileWrite_payload_address[10] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_lastStageRegFileWrite_payload_address[11] +1 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[1] +1 1 +.names $false decode_to_execute_PC[0] +1 1 +.names $false decode_to_execute_PC[1] +1 1 +.names dBus_cmd_payload_data[0] decode_to_execute_RS2[0] +1 1 +.names dBus_cmd_payload_data[1] decode_to_execute_RS2[1] +1 1 +.names dBus_cmd_payload_data[2] decode_to_execute_RS2[2] +1 1 +.names dBus_cmd_payload_data[3] decode_to_execute_RS2[3] +1 1 +.names dBus_cmd_payload_data[4] decode_to_execute_RS2[4] +1 1 +.names dBus_cmd_payload_data[5] decode_to_execute_RS2[5] +1 1 +.names dBus_cmd_payload_data[6] decode_to_execute_RS2[6] +1 1 +.names dBus_cmd_payload_data[7] decode_to_execute_RS2[7] +1 1 +.names $false iBus_cmd_payload_pc[0] +1 1 +.names $false iBus_cmd_payload_pc[1] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[0] writeBack_MEMORY_READ_DATA[0] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[1] writeBack_MEMORY_READ_DATA[1] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[2] writeBack_MEMORY_READ_DATA[2] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[3] writeBack_MEMORY_READ_DATA[3] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[4] writeBack_MEMORY_READ_DATA[4] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[5] writeBack_MEMORY_READ_DATA[5] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[6] writeBack_MEMORY_READ_DATA[6] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[7] writeBack_MEMORY_READ_DATA[7] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[8] writeBack_MEMORY_READ_DATA[8] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[9] writeBack_MEMORY_READ_DATA[9] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[10] writeBack_MEMORY_READ_DATA[10] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[11] writeBack_MEMORY_READ_DATA[11] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[12] writeBack_MEMORY_READ_DATA[12] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[13] writeBack_MEMORY_READ_DATA[13] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[14] writeBack_MEMORY_READ_DATA[14] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[15] writeBack_MEMORY_READ_DATA[15] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[16] writeBack_MEMORY_READ_DATA[16] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[17] writeBack_MEMORY_READ_DATA[17] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[18] writeBack_MEMORY_READ_DATA[18] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[19] writeBack_MEMORY_READ_DATA[19] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif new file mode 100644 index 00000000000..2cdcc440f0a --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif @@ -0,0 +1,34792 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model VexRiscv +.inputs dBus_cmd_ready dBus_rsp_valid dBus_rsp_payload_last dBus_rsp_payload_data[0] dBus_rsp_payload_data[1] dBus_rsp_payload_data[2] dBus_rsp_payload_data[3] dBus_rsp_payload_data[4] dBus_rsp_payload_data[5] dBus_rsp_payload_data[6] dBus_rsp_payload_data[7] dBus_rsp_payload_data[8] dBus_rsp_payload_data[9] dBus_rsp_payload_data[10] dBus_rsp_payload_data[11] dBus_rsp_payload_data[12] dBus_rsp_payload_data[13] dBus_rsp_payload_data[14] dBus_rsp_payload_data[15] dBus_rsp_payload_data[16] dBus_rsp_payload_data[17] dBus_rsp_payload_data[18] dBus_rsp_payload_data[19] dBus_rsp_payload_data[20] dBus_rsp_payload_data[21] dBus_rsp_payload_data[22] dBus_rsp_payload_data[23] dBus_rsp_payload_data[24] dBus_rsp_payload_data[25] dBus_rsp_payload_data[26] dBus_rsp_payload_data[27] dBus_rsp_payload_data[28] dBus_rsp_payload_data[29] dBus_rsp_payload_data[30] dBus_rsp_payload_data[31] dBus_rsp_payload_error timerInterrupt externalInterrupt softwareInterrupt debug_bus_cmd_valid debug_bus_cmd_payload_wr debug_bus_cmd_payload_address[0] debug_bus_cmd_payload_address[1] debug_bus_cmd_payload_address[2] debug_bus_cmd_payload_address[3] debug_bus_cmd_payload_address[4] debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[6] debug_bus_cmd_payload_address[7] debug_bus_cmd_payload_data[0] debug_bus_cmd_payload_data[1] debug_bus_cmd_payload_data[2] debug_bus_cmd_payload_data[3] debug_bus_cmd_payload_data[4] debug_bus_cmd_payload_data[5] debug_bus_cmd_payload_data[6] debug_bus_cmd_payload_data[7] debug_bus_cmd_payload_data[8] debug_bus_cmd_payload_data[9] debug_bus_cmd_payload_data[10] debug_bus_cmd_payload_data[11] debug_bus_cmd_payload_data[12] debug_bus_cmd_payload_data[13] debug_bus_cmd_payload_data[14] debug_bus_cmd_payload_data[15] debug_bus_cmd_payload_data[16] debug_bus_cmd_payload_data[17] debug_bus_cmd_payload_data[18] debug_bus_cmd_payload_data[19] debug_bus_cmd_payload_data[20] debug_bus_cmd_payload_data[21] debug_bus_cmd_payload_data[22] debug_bus_cmd_payload_data[23] debug_bus_cmd_payload_data[24] debug_bus_cmd_payload_data[25] debug_bus_cmd_payload_data[26] debug_bus_cmd_payload_data[27] debug_bus_cmd_payload_data[28] debug_bus_cmd_payload_data[29] debug_bus_cmd_payload_data[30] debug_bus_cmd_payload_data[31] iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_data[0] iBus_rsp_payload_data[1] iBus_rsp_payload_data[2] iBus_rsp_payload_data[3] iBus_rsp_payload_data[4] iBus_rsp_payload_data[5] iBus_rsp_payload_data[6] iBus_rsp_payload_data[7] iBus_rsp_payload_data[8] iBus_rsp_payload_data[9] iBus_rsp_payload_data[10] iBus_rsp_payload_data[11] iBus_rsp_payload_data[12] iBus_rsp_payload_data[13] iBus_rsp_payload_data[14] iBus_rsp_payload_data[15] iBus_rsp_payload_data[16] iBus_rsp_payload_data[17] iBus_rsp_payload_data[18] iBus_rsp_payload_data[19] iBus_rsp_payload_data[20] iBus_rsp_payload_data[21] iBus_rsp_payload_data[22] iBus_rsp_payload_data[23] iBus_rsp_payload_data[24] iBus_rsp_payload_data[25] iBus_rsp_payload_data[26] iBus_rsp_payload_data[27] iBus_rsp_payload_data[28] iBus_rsp_payload_data[29] iBus_rsp_payload_data[30] iBus_rsp_payload_data[31] iBus_rsp_payload_error clk reset debugReset +.outputs dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_uncached dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[1] dBus_cmd_payload_mask[2] dBus_cmd_payload_mask[3] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] dBus_cmd_payload_size[2] dBus_cmd_payload_last debug_bus_cmd_ready debug_bus_rsp_data[0] debug_bus_rsp_data[1] debug_bus_rsp_data[2] debug_bus_rsp_data[3] debug_bus_rsp_data[4] debug_bus_rsp_data[5] debug_bus_rsp_data[6] debug_bus_rsp_data[7] debug_bus_rsp_data[8] debug_bus_rsp_data[9] debug_bus_rsp_data[10] debug_bus_rsp_data[11] debug_bus_rsp_data[12] debug_bus_rsp_data[13] debug_bus_rsp_data[14] debug_bus_rsp_data[15] debug_bus_rsp_data[16] debug_bus_rsp_data[17] debug_bus_rsp_data[18] debug_bus_rsp_data[19] debug_bus_rsp_data[20] debug_bus_rsp_data[21] debug_bus_rsp_data[22] debug_bus_rsp_data[23] debug_bus_rsp_data[24] debug_bus_rsp_data[25] debug_bus_rsp_data[26] debug_bus_rsp_data[27] debug_bus_rsp_data[28] debug_bus_rsp_data[29] debug_bus_rsp_data[30] debug_bus_rsp_data[31] debug_resetOut iBus_cmd_valid iBus_cmd_payload_address[0] iBus_cmd_payload_address[1] iBus_cmd_payload_address[2] iBus_cmd_payload_address[3] iBus_cmd_payload_address[4] iBus_cmd_payload_address[5] iBus_cmd_payload_address[6] iBus_cmd_payload_address[7] iBus_cmd_payload_address[8] iBus_cmd_payload_address[9] iBus_cmd_payload_address[10] iBus_cmd_payload_address[11] iBus_cmd_payload_address[12] iBus_cmd_payload_address[13] iBus_cmd_payload_address[14] iBus_cmd_payload_address[15] iBus_cmd_payload_address[16] iBus_cmd_payload_address[17] iBus_cmd_payload_address[18] iBus_cmd_payload_address[19] iBus_cmd_payload_address[20] iBus_cmd_payload_address[21] iBus_cmd_payload_address[22] iBus_cmd_payload_address[23] iBus_cmd_payload_address[24] iBus_cmd_payload_address[25] iBus_cmd_payload_address[26] iBus_cmd_payload_address[27] iBus_cmd_payload_address[28] iBus_cmd_payload_address[29] iBus_cmd_payload_address[30] iBus_cmd_payload_address[31] iBus_cmd_payload_size[0] iBus_cmd_payload_size[1] iBus_cmd_payload_size[2] +.names $false +.names $true +1 +.names $undef +.names $abc$27210$new_n4092 $abc$27210$new_n3940 dBus_cmd_payload_address[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$21747 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n3941 $abc$27210$new_n3940 +10 1 +.names $abc$27210$new_n4089 $abc$27210$new_n3942 $abc$27210$new_n4084 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] $abc$27210$new_n3941 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n3943 $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] $abc$27210$new_n3942 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n8219 $abc$27210$new_n3988 $abc$27210$new_n8017 $abc$27210$new_n8034 $abc$27210$new_n3943 +1100 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n3950 +01 1 +10 1 +.names $abc$27210$new_n7999 $abc$27210$new_n3963 MmuPlugin_ports_1_cache_2_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_2_superPage $abc$27210$new_n3956 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$27210$new_n3964 MmuPlugin_ports_1_cache_2_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n3963 +100 1 +111 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] $abc$27210$new_n3964 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_4_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n3971 +0000 1 +0011 1 +1100 1 +1111 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n3972 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n3980 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n3983 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n3985 +00 1 +11 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n3987 +01 1 +10 1 +.names $abc$27210$new_n8203 $abc$27210$new_n8227 $abc$27210$new_n3988 +00 1 +.names $abc$27210$new_n8008 $abc$27210$new_n3997 MmuPlugin_ports_1_cache_3_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_3_superPage $abc$27210$new_n3990 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$27210$new_n3995 MmuPlugin_ports_1_cache_3_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_3_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n3994 +10000 1 +10011 1 +11100 1 +11111 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n3995 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n3998 MmuPlugin_ports_1_cache_3_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n3997 +100 1 +111 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] $abc$27210$new_n3998 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4000 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4005 +01 1 +10 1 +.names $abc$27210$new_n4015 $abc$27210$new_n4014 MmuPlugin_ports_1_cache_5_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4013 +1100 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] MmuPlugin_ports_1_cache_5_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n4014 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_5_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_5_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n4015 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n4017 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_5_virtualAddress_0[2] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n4016 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names MmuPlugin_ports_1_cache_5_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4017 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_5_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4020 +00 1 +11 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_5_virtualAddress_1[6] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n4023 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_5_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4027 +10 1 +.names MmuPlugin_ports_1_cache_1_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n4033 +10 1 +.names $abc$27210$new_n4038 MmuPlugin_ports_1_cache_1_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_1_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4037 +10000 1 +10011 1 +11100 1 +11111 1 +.names MmuPlugin_ports_1_cache_1_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_1_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n4038 +0000 1 +0011 1 +1100 1 +1111 1 +.names MmuPlugin_ports_1_cache_1_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4046 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_1_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_1_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4048 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n8034 $abc$27210$new_n8227 $abc$27210$new_n8219 $abc$27210$new_n8203 $abc$27210$new_n8017 $abc$27210$new_n4049 +00000 1 +.names MmuPlugin_ports_1_cache_4_valid MmuPlugin_ports_1_cache_4_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_4_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n4055 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4085 $abc$27210$new_n4084 +00 1 +.names $abc$27210$new_n4087 $abc$27210$new_n8034 $abc$27210$new_n4086 $abc$27210$new_n4085 +100 1 +.names $abc$27210$new_n8203 $abc$27210$new_n8017 $abc$27210$new_n4086 +00 1 +.names $abc$27210$new_n3988 $abc$27210$new_n8219 $abc$27210$new_n4087 +10 1 +.names $abc$27210$new_n4086 $abc$27210$new_n8034 $abc$27210$new_n8227 $abc$27210$new_n4088 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4087 $abc$27210$new_n4088 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] $abc$27210$new_n4089 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n4091 MmuPlugin_satp_mode CsrPlugin_mstatus_MPP[1] CsrPlugin_mstatus_MPP[0] $abc$27210$new_n4090 +11100 1 +11101 1 +11110 1 +.names MmuPlugin_status_mprv DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4091 +11000 1 +.names $abc$27210$new_n4093 dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4092 +00 1 +.names $abc$27210$new_n4094 $abc$27210$new_n4100 $abc$27210$new_n4093 +10 1 +.names $abc$27210$new_n4103 $abc$27210$new_n4095 $abc$27210$new_n4094 +11 1 +.names $abc$27210$new_n4096 dataCache_1.stageB_mmuRsp_refilling $abc$27210$new_n4095 +10 1 +.names MmuPlugin_dBusAccess_rsp_payload_error $abc$27210$new_n4102 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$new_n4096 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4098 $abc$27210$new_n4102 dBus_cmd_payload_uncached dataCache_1.stageB_mmuRsp_isPaging MmuPlugin_dBusAccess_rsp_payload_error +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$27210$new_n4099 dBus_rsp_payload_error dBus_cmd_payload_uncached dBus_rsp_valid dBus_cmd_payload_wr $abc$27210$new_n4098 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4100 dataCache_1.stageB_unaligned dataCache_1.stageB_tagsReadRsp_0_error dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4099 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names memory_to_writeBack_IS_DBUS_SHARING $abc$27210$new_n4101 $abc$27210$new_n4100 +00 1 +.names memory_to_writeBack_MEMORY_ENABLE lastStageIsValid $abc$27210$new_n4101 +11 1 +.names $abc$27210$new_n4100 dBus_cmd_payload_wr dataCache_1.stageB_mmuRsp_exception dataCache_1.stageB_mmuRsp_allowWrite dataCache_1.stageB_mmuRsp_allowRead $abc$27210$new_n4102 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names dBus_cmd_payload_wr dBus_cmd_payload_uncached dBus_cmd_ready dBus_rsp_valid dataCache_1.stageB_waysHit $abc$27210$new_n4103 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dBus_cmd_payload_wr dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4100 dBus_cmd_payload_size[2] +0000 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4106 dBus_cmd_payload_address[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$21749 +001 1 +011 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4107 $abc$27210$new_n4090 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] $abc$27210$new_n4106 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$27210$new_n4108 $abc$27210$new_n3943 $abc$27210$new_n4084 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] $abc$27210$new_n4109 $abc$27210$new_n4107 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] $abc$27210$new_n4108 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] $abc$27210$new_n4109 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4111 dBus_cmd_payload_address[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$21751 +001 1 +011 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4112 $abc$27210$new_n4090 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] $abc$27210$new_n4111 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$27210$new_n4113 $abc$27210$new_n3943 $abc$27210$new_n4084 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] $abc$27210$new_n4114 $abc$27210$new_n4112 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] $abc$27210$new_n4113 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] $abc$27210$new_n4114 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4116 dBus_cmd_payload_address[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$21753 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4117 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4116 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4120 $abc$27210$new_n4118 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] $abc$27210$new_n4117 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] $abc$27210$new_n4119 $abc$27210$new_n4118 +1000 1 +1010 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] $abc$27210$new_n4119 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] $abc$27210$new_n4120 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4122 dBus_cmd_payload_address[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$21755 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4123 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n4122 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4126 $abc$27210$new_n4124 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] $abc$27210$new_n4123 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] $abc$27210$new_n4125 $abc$27210$new_n4124 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] $abc$27210$new_n4125 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] $abc$27210$new_n4126 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4128 dBus_cmd_payload_address[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$21757 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4129 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n4128 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4132 $abc$27210$new_n4130 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] $abc$27210$new_n4129 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] $abc$27210$new_n4131 $abc$27210$new_n4130 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] $abc$27210$new_n4131 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] $abc$27210$new_n4132 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4134 dBus_cmd_payload_address[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$21759 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4135 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n4134 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4138 $abc$27210$new_n4136 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] $abc$27210$new_n4135 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] $abc$27210$new_n4137 $abc$27210$new_n4136 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] $abc$27210$new_n4137 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] $abc$27210$new_n4138 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4140 dBus_cmd_payload_address[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$21761 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4141 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4140 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4144 $abc$27210$new_n4142 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] $abc$27210$new_n4141 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] $abc$27210$new_n4143 $abc$27210$new_n4142 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] $abc$27210$new_n4143 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] $abc$27210$new_n4144 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4146 dBus_cmd_payload_address[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$21763 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4147 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n4146 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4150 $abc$27210$new_n4148 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] $abc$27210$new_n4147 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] $abc$27210$new_n4149 $abc$27210$new_n4148 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] $abc$27210$new_n4149 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] $abc$27210$new_n4150 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4152 dBus_cmd_payload_address[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$21765 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4157 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n4152 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4156 $abc$27210$new_n4154 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_superPage $abc$27210$new_n4153 +10000 1 +10001 1 +10010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_superPage $abc$27210$new_n4155 $abc$27210$new_n4154 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_superPage MmuPlugin_ports_1_cache_5_superPage $abc$27210$new_n4155 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_superPage MmuPlugin_ports_1_cache_3_superPage $abc$27210$new_n4156 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4160 $abc$27210$new_n4158 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[9] $abc$27210$new_n4157 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[9] $abc$27210$new_n4159 $abc$27210$new_n4158 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[9] MmuPlugin_ports_1_cache_5_physicalAddress_0[9] $abc$27210$new_n4159 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[9] MmuPlugin_ports_1_cache_3_physicalAddress_0[9] $abc$27210$new_n4160 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4162 dBus_cmd_payload_address[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$21767 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4163 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4162 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4166 $abc$27210$new_n4164 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[8] $abc$27210$new_n4163 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[8] $abc$27210$new_n4165 $abc$27210$new_n4164 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[8] MmuPlugin_ports_1_cache_5_physicalAddress_0[8] $abc$27210$new_n4165 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[8] MmuPlugin_ports_1_cache_3_physicalAddress_0[8] $abc$27210$new_n4166 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4168 dBus_cmd_payload_address[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$21769 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4169 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n4168 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4172 $abc$27210$new_n4170 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[7] $abc$27210$new_n4169 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[7] $abc$27210$new_n4171 $abc$27210$new_n4170 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[7] MmuPlugin_ports_1_cache_5_physicalAddress_0[7] $abc$27210$new_n4171 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[7] MmuPlugin_ports_1_cache_3_physicalAddress_0[7] $abc$27210$new_n4172 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4174 dBus_cmd_payload_address[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$21771 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4175 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n4174 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4178 $abc$27210$new_n4176 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[6] $abc$27210$new_n4175 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[6] $abc$27210$new_n4177 $abc$27210$new_n4176 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[6] MmuPlugin_ports_1_cache_5_physicalAddress_0[6] $abc$27210$new_n4177 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[6] MmuPlugin_ports_1_cache_3_physicalAddress_0[6] $abc$27210$new_n4178 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4180 dBus_cmd_payload_address[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$21773 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4181 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$new_n4180 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4184 $abc$27210$new_n4182 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[5] $abc$27210$new_n4181 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[5] $abc$27210$new_n4183 $abc$27210$new_n4182 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[5] MmuPlugin_ports_1_cache_5_physicalAddress_0[5] $abc$27210$new_n4183 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[5] MmuPlugin_ports_1_cache_3_physicalAddress_0[5] $abc$27210$new_n4184 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4186 dBus_cmd_payload_address[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$21775 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4187 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n4186 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4190 $abc$27210$new_n4188 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[4] $abc$27210$new_n4187 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[4] $abc$27210$new_n4189 $abc$27210$new_n4188 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[4] MmuPlugin_ports_1_cache_5_physicalAddress_0[4] $abc$27210$new_n4189 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[4] MmuPlugin_ports_1_cache_3_physicalAddress_0[4] $abc$27210$new_n4190 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4192 dBus_cmd_payload_address[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$21777 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4193 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4192 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4196 $abc$27210$new_n4194 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[3] $abc$27210$new_n4193 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[3] $abc$27210$new_n4195 $abc$27210$new_n4194 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[3] MmuPlugin_ports_1_cache_5_physicalAddress_0[3] $abc$27210$new_n4195 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[3] MmuPlugin_ports_1_cache_3_physicalAddress_0[3] $abc$27210$new_n4196 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4198 dBus_cmd_payload_address[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$21779 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4199 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n4198 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4202 $abc$27210$new_n4200 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[2] $abc$27210$new_n4199 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[2] $abc$27210$new_n4201 $abc$27210$new_n4200 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[2] MmuPlugin_ports_1_cache_5_physicalAddress_0[2] $abc$27210$new_n4201 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[2] MmuPlugin_ports_1_cache_3_physicalAddress_0[2] $abc$27210$new_n4202 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4204 dBus_cmd_payload_address[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$21781 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4205 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] $abc$27210$new_n4204 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4208 $abc$27210$new_n4206 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[1] $abc$27210$new_n4205 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[1] $abc$27210$new_n4207 $abc$27210$new_n4206 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[1] MmuPlugin_ports_1_cache_5_physicalAddress_0[1] $abc$27210$new_n4207 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[1] MmuPlugin_ports_1_cache_3_physicalAddress_0[1] $abc$27210$new_n4208 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4210 dBus_cmd_payload_address[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$21783 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4211 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n4210 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4214 $abc$27210$new_n4212 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[0] $abc$27210$new_n4211 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[0] $abc$27210$new_n4213 $abc$27210$new_n4212 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[0] MmuPlugin_ports_1_cache_5_physicalAddress_0[0] $abc$27210$new_n4213 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[0] MmuPlugin_ports_1_cache_3_physicalAddress_0[0] $abc$27210$new_n4214 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] dBus_cmd_payload_address[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21785 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] dBus_cmd_payload_address[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21787 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] dBus_cmd_payload_address[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21789 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] dBus_cmd_payload_address[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21791 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] dBus_cmd_payload_address[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21793 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] dBus_cmd_payload_address[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21795 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] dBus_cmd_payload_address[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21797 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] dataCache_1.stageB_mmuRsp_physicalAddress[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21799 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] dataCache_1.stageB_mmuRsp_physicalAddress[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21801 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] dataCache_1.stageB_mmuRsp_physicalAddress[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21803 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] dataCache_1.stageB_mmuRsp_physicalAddress[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21805 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] dataCache_1.stageB_mmuRsp_physicalAddress[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21807 +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.stageB_flusher_counter[5] dataCache_1.stageB_flusher_start $abc$27210$new_n4228 dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4232 $abc$27210$auto$rtlil.cc:2693:MuxGate$21817 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names dataCache_1.stageB_flusher_counter[4] $abc$27210$new_n4229 $abc$27210$new_n4228 +11 1 +.names dataCache_1.stageB_flusher_counter[3] $abc$27210$new_n4230 $abc$27210$new_n4229 +11 1 +.names dataCache_1.stageB_flusher_counter[2] $abc$27210$new_n4231 $abc$27210$new_n4230 +11 1 +.names dataCache_1.stageB_flusher_counter[0] dataCache_1.stageB_flusher_counter[1] $abc$27210$new_n4231 +11 1 +.names execute_RS1[10] $abc$27210$new_n4233 $abc$27210$new_n4232 +11 1 +.names dataCache_1.stageB_flusher_start $abc$27210$new_n4234 $abc$27210$new_n4233 +11 1 +.names decode_to_execute_MEMORY_MANAGMENT execute_arbitration_isValid $abc$27210$new_n4235 $abc$27210$new_n4234 +110 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[14] _zz__zz_execute_BranchPlugin_branch_src2_2[15] _zz__zz_execute_BranchPlugin_branch_src2_2[16] _zz__zz_execute_BranchPlugin_branch_src2_2[17] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n4235 +00000 1 +.names dataCache_1.stageB_flusher_counter[4] $abc$27210$new_n4237 $abc$27210$new_n4229 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_start $abc$27210$auto$rtlil.cc:2693:MuxGate$21819 +00100 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[9] $abc$27210$new_n4233 $abc$27210$new_n4237 +11 1 +.names $abc$27210$new_n4239 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_counter[3] dataCache_1.stageB_flusher_start $abc$27210$new_n4230 $abc$27210$auto$rtlil.cc:2693:MuxGate$21821 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +11101 1 +.names dataCache_1.stageB_flusher_start $abc$27210$new_n4229 execute_RS1[8] $abc$27210$new_n4233 $abc$27210$new_n4239 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names dataCache_1.stageB_flusher_counter[2] $abc$27210$new_n4241 $abc$27210$new_n4231 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_start $abc$27210$auto$rtlil.cc:2693:MuxGate$21823 +00100 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[7] $abc$27210$new_n4233 $abc$27210$new_n4241 +11 1 +.names dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_counter[1] $abc$27210$new_n4243 execute_RS1[6] $abc$27210$new_n4234 $abc$27210$auto$rtlil.cc:2693:MuxGate$21825 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10011 1 +10111 1 +11011 1 +11111 1 +.names dataCache_1.stageB_flusher_counter[0] dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4243 +10 1 +.names dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_counter[0] execute_RS1[5] $abc$27210$new_n4234 $abc$27210$auto$rtlil.cc:2693:MuxGate$21827 +00000 1 +00001 1 +00010 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11111 1 +.names lastStageIsValid $abc$27210$new_n4256 HazardSimplePlugin_writeBackWrites_payload_data[0] DebugPlugin_busReadDataReg[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21833 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n4253 MmuPlugin_dBusAccess_rsp_payload_data[0] DBusCachedPlugin_exceptionBus_payload_badAddr[0] HazardSimplePlugin_writeBackWrites_payload_data[0] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4248 MmuPlugin_dBusAccess_rsp_payload_data[16] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[0] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[24] $abc$27210$new_n4250 $abc$27210$new_n4251 $abc$27210$new_n4248 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[24] dataCache_1.stageB_dataMux[24] MmuPlugin_dBusAccess_rsp_payload_data[24] +001 1 +011 1 +110 1 +111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[0] dataCache_1.stageB_dataMux[0] $abc$27210$new_n4250 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[8] dataCache_1.stageB_dataMux[8] $abc$27210$new_n4251 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[16] dataCache_1.stageB_dataMux[16] MmuPlugin_dBusAccess_rsp_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4254 _zz_writeBack_MulPlugin_result_1[32] _zz_writeBack_MulPlugin_result[32] _zz__zz_decode_RS2_2[0] $abc$27210$new_n4253 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n4254 +00 1 +.names memory_to_writeBack_IS_MUL lastStageIsValid $abc$27210$new_n4255 +11 1 +.names decode_to_execute_DO_EBREAK execute_arbitration_isValid $abc$27210$new_n4256 +11 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] $abc$27210$new_n4258 $abc$27210$auto$rtlil.cc:2693:MuxGate$21835 +0100 1 +0101 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$27210$new_n4317 $abc$27210$new_n4259 $abc$27210$new_n4265 lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n4258 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n4262 DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_arbitration_isValid decode_to_execute_DO_EBREAK dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4259 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_isStuck +01 1 +10 1 +11 1 +.names execute_to_memory_IS_DIV memory_arbitration_isValid memory_DivPlugin_div_done $abc$27210$new_n4261 +110 1 +.names $abc$27210$new_n4263 decode_to_execute_MEMORY_MANAGMENT execute_arbitration_isValid dataCache_1.stageB_flusher_waitDone $abc$27210$new_n4262 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4264 memory_arbitration_isValid lastStageIsValid $abc$27210$new_n4263 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$27210$new_n4264 +11 1 +.names $abc$27210$new_n4266 $abc$27210$new_n4305 $abc$27210$new_n4291 $abc$27210$new_n4316 $abc$27210$new_n4313 $abc$27210$new_n4265 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n8213 IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.decodeStage_hit_tags_0_error $abc$27210$new_n4266 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4270 +10 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] $abc$27210$new_n4272 +01 1 +10 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] $abc$27210$new_n4274 +10 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] $abc$27210$new_n4275 +10 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] $abc$27210$new_n4279 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4280 +10 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid execute_to_memory_BYPASSABLE_MEMORY_STAGE $abc$27210$new_n4292 $abc$27210$new_n4291 +1100 1 +.names $abc$27210$new_n4298 $abc$27210$new_n4300 $abc$27210$new_n4304 $abc$27210$new_n8023 $abc$27210$new_n4303 $abc$27210$new_n4292 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4299 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4298 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4299 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$27210$new_n4302 $abc$27210$new_n4301 execute_to_memory_INSTRUCTION[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4300 +1100 1 +1111 1 +.names execute_to_memory_INSTRUCTION[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] execute_to_memory_INSTRUCTION[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4301 +0000 1 +0011 1 +1100 1 +1111 1 +.names execute_to_memory_INSTRUCTION[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] execute_to_memory_INSTRUCTION[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4302 +0000 1 +0011 1 +1100 1 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4303 +11 1 +.names _zz__zz_decode_IS_CSR_41 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n4304 +10 1 +.names decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid decode_to_execute_BYPASSABLE_EXECUTE_STAGE $abc$27210$new_n4306 $abc$27210$new_n4305 +1100 1 +.names $abc$27210$new_n4298 $abc$27210$new_n4307 $abc$27210$new_n4304 $abc$27210$new_n4310 $abc$27210$new_n4303 $abc$27210$new_n4306 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4309 $abc$27210$new_n4308 _zz__zz_execute_BranchPlugin_branch_src2_4[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4307 +1100 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2_10 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4308 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_4[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] _zz__zz_execute_BranchPlugin_branch_src2_4[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4309 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n4312 $abc$27210$new_n4311 _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n4310 +1100 1 +1111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_4[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] _zz__zz_execute_BranchPlugin_branch_src2_4[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4311 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2_10 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] _zz__zz_execute_BranchPlugin_branch_src2_4[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4312 +0000 1 +0011 1 +1100 1 +1111 1 +.names when_MmuPlugin_l281_1 $abc$27210$new_n4314 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4315 $abc$27210$new_n4313 +1100 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4314 +00 1 +.names MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[1] $abc$27210$new_n4315 +000 1 +.names CsrPlugin_interrupt_valid DebugPlugin_haltIt DebugPlugin_stepIt $abc$27210$new_n4316 +100 1 +.names $abc$27210$new_n4318 $abc$27210$new_n4319 IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] $abc$27210$new_n4317 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[2] $abc$27210$new_n4318 +00 1 +01 1 +11 1 +.names _zz_memory_ENV_CTRL memory_arbitration_isValid _zz_execute_ENV_CTRL execute_arbitration_isValid $abc$27210$new_n4319 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names debug_bus_cmd_payload_address[2] $abc$27210$new_n4321 debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[4] $abc$27210$new_n4320 +1100 1 +.names debug_bus_cmd_payload_wr debug_bus_cmd_valid debug_bus_cmd_payload_address[7] debug_bus_cmd_payload_address[6] debug_bus_cmd_payload_address[3] $abc$27210$new_n4321 +11000 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n4258 $abc$27210$new_n4320 $abc$27210$auto$rtlil.cc:2693:MuxGate$21837 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4324 $abc$27210$new_n4390 MmuPlugin_shared_state_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21839 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4325 $abc$27210$new_n4329 $abc$27210$new_n4315 $abc$27210$new_n4324 +100 1 +110 1 +111 1 +.names MmuPlugin_shared_state_1[0] MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_state_1[2] $abc$27210$new_n4326 MmuPlugin_shared_state_1[1] $abc$27210$new_n4325 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n4327 dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4326 +110 1 +.names $abc$27210$new_n4328 execute_arbitration_isValid memory_arbitration_isValid lastStageIsValid $abc$27210$new_n4318 $abc$27210$new_n4327 +10000 1 +.names CsrPlugin_exceptionPendings_3 CsrPlugin_exceptionPendings_2 CsrPlugin_exceptionPendings_1 $abc$27210$new_n4328 +000 1 +.names $abc$27210$new_n4090 $abc$27210$new_n8224 execute_to_memory_MEMORY_ENABLE memory_arbitration_isValid $abc$27210$new_n4329 +1111 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n4005 $abc$27210$new_n4000 $abc$27210$new_n4333 +0000 1 +1100 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_2_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n3950 $abc$27210$new_n4359 +00000 1 +00110 1 +11000 1 +11110 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_2_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4362 +0000 1 +0011 1 +1100 1 +1111 1 +.names MmuPlugin_ports_1_cache_2_valid MmuPlugin_ports_1_cache_2_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n4363 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] $abc$27210$new_n4368 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n3987 $abc$27210$new_n3980 $abc$27210$new_n3983 $abc$27210$new_n4369 +000 1 +.names $abc$27210$new_n4371 $abc$27210$new_n4377 MmuPlugin_ports_1_cache_0_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_ports_1_cache_0_superPage $abc$27210$new_n4370 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$27210$new_n4375 $abc$27210$new_n4372 MmuPlugin_ports_1_cache_0_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n4371 +1100 1 +1111 1 +.names $abc$27210$new_n4373 MmuPlugin_ports_1_cache_0_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_0_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4372 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_ports_1_cache_0_virtualAddress_0[6] $abc$27210$new_n4374 MmuPlugin_ports_1_cache_0_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4373 +00000 1 +00010 1 +00011 1 +11000 1 +11010 1 +11011 1 +.names MmuPlugin_ports_1_cache_0_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n4374 +10 1 +.names $abc$27210$new_n4376 MmuPlugin_ports_1_cache_0_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] $abc$27210$new_n4375 +100 1 +111 1 +.names MmuPlugin_ports_1_cache_0_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_0_virtualAddress_0[0] $abc$27210$new_n4376 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_0_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_0_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n4378 $abc$27210$new_n4377 +00000 1 +00110 1 +11000 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_0_virtualAddress_0[5] $abc$27210$new_n4378 +10 1 +.names MmuPlugin_ports_1_cache_0_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n4387 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] MmuPlugin_shared_dBusRspStaged_payload_redo $abc$27210$new_n4391 $abc$27210$new_n4390 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRspStaged_payload_error MmuPlugin_shared_dBusRsp_pte_W MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRsp_pte_X $abc$27210$new_n4391 +10000 1 +.names $abc$27210$new_n4324 $abc$27210$new_n4393 MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21841 +001 1 +011 1 +100 1 +101 1 +.names MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[1] $abc$27210$new_n4391 $abc$27210$new_n4393 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] $abc$27210$new_n4395 $abc$27210$new_n4442 $abc$27210$auto$rtlil.cc:2693:MuxGate$21945 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4421 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 $abc$27210$new_n4423 $abc$27210$new_n4395 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_6 $abc$27210$new_n4417 $abc$27210$new_n4419 $abc$27210$new_n4397 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4396 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +11110 1 +.names $abc$27210$new_n4416 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4398 $abc$27210$new_n4397 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 $abc$27210$new_n4398 +00100 1 +00110 1 +00111 1 +11010 1 +.names $abc$27210$new_n4415 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$new_n4400 $abc$27210$new_n4399 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4401 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4400 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4402 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4401 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4403 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4402 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n4404 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$new_n4403 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4405 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4404 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4406 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4405 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4407 _zz_6 _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4406 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4408 _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n4407 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$new_n4409 $abc$27210$new_n4408 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$new_n4410 $abc$27210$new_n4409 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$new_n4411 $abc$27210$new_n4410 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4412 IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4411 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4413 IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4412 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] $abc$27210$new_n4413 +1001 1 +1011 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4414 +0010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] _zz_6 $abc$27210$new_n4415 +000 1 +010 1 +100 1 +101 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4416 +000 1 +001 1 +010 1 +011 1 +100 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4417 +01 1 +10 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4419 +011 1 +100 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4436 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[30] $abc$27210$new_n4421 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4434 $abc$27210$new_n4423 $abc$27210$new_n4422 +00 1 +.names $abc$27210$new_n4431 $abc$27210$new_n4424 $abc$27210$new_n4428 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n4423 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n4425 $abc$27210$new_n4266 $abc$27210$new_n4424 +00 1 +.names _zz_10 $abc$27210$new_n4427 $abc$27210$new_n4414 $abc$27210$new_n4425 +000 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] _zz_10 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_PREDICTION_CONTEXT_line_history_2[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4427 +1100 1 +.names $abc$27210$new_n4101 MmuPlugin_dBusAccess_rsp_payload_redo $abc$27210$new_n4428 +11 1 +.names $abc$27210$new_n4430 $abc$27210$new_n4100 dataCache_1.io_cpu_execute_refilling dataCache_1.loader_valid_regNext MmuPlugin_dBusAccess_rsp_payload_redo +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +1010 1 +1110 1 +.names dataCache_1.stageB_mmuRsp_refilling dataCache_1.stageB_waysHit dataCache_1.stageB_dataColisions dBus_cmd_payload_wr dBus_cmd_payload_uncached $abc$27210$new_n4430 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n4432 lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n4431 +100 1 +101 1 +110 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 $abc$27210$new_n4432 +00 1 +.names $abc$27210$new_n4316 CsrPlugin_pipelineLiberator_pcValids_2 $abc$27210$new_n4328 CsrPlugin_hadException $abc$27210$new_n4433 +1110 1 +.names $abc$27210$new_n4428 $abc$27210$new_n4431 execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n4434 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n4424 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n4435 +10000 1 +10001 1 +10010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[30] $abc$27210$new_n4437 CsrPlugin_mepc[30] $abc$27210$new_n4438 $abc$27210$new_n4436 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n4437 +1110 1 +.names _zz_writeBack_ENV_CTRL _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] lastStageIsValid $abc$27210$new_n4438 +1111 1 +.names IBusCachedPlugin_fetchPc_booted $abc$27210$new_n4435 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n4441 $abc$27210$new_n4439 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4258 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.decodeStage_hit_tags_0_error IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 +1000 1 +1001 1 +1010 1 +.names IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$new_n8213 $abc$27210$new_n4441 +10 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4443 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4442 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] $abc$27210$new_n4444 $abc$27210$new_n4443 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] $abc$27210$new_n4445 $abc$27210$new_n4444 +11111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] $abc$27210$new_n4446 $abc$27210$new_n4445 +111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] $abc$27210$new_n4447 $abc$27210$new_n4446 +11111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] $abc$27210$new_n4448 $abc$27210$new_n4447 +11111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] $abc$27210$new_n4449 $abc$27210$new_n4448 +11111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] $abc$27210$new_n4450 $abc$27210$new_n4449 +111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] $abc$27210$new_n4451 $abc$27210$new_n4450 +111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] $abc$27210$new_n4452 $abc$27210$new_n4451 +111 1 +.names IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] $abc$27210$new_n4452 +111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] $abc$27210$new_n4454 $abc$27210$new_n4458 $abc$27210$auto$rtlil.cc:2693:MuxGate$21947 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4456 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4455 $abc$27210$new_n4423 $abc$27210$new_n4454 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_6 $abc$27210$new_n4397 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n4455 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4457 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[29] $abc$27210$new_n4456 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[29] $abc$27210$new_n4437 CsrPlugin_mepc[29] $abc$27210$new_n4438 $abc$27210$new_n4457 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4459 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4458 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] $abc$27210$new_n4444 $abc$27210$new_n4459 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] $abc$27210$new_n4461 $abc$27210$new_n4465 $abc$27210$auto$rtlil.cc:2693:MuxGate$21949 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4463 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[28] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[28] $abc$27210$new_n4461 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[28] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4464 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[28] $abc$27210$new_n4463 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[28] $abc$27210$new_n4438 $abc$27210$new_n4464 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4444 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n4465 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] $abc$27210$new_n4467 $abc$27210$new_n4471 $abc$27210$auto$rtlil.cc:2693:MuxGate$21951 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4469 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[27] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[27] $abc$27210$new_n4467 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[27] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4470 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[27] $abc$27210$new_n4469 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[27] $abc$27210$new_n4438 $abc$27210$new_n4470 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4472 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4471 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] $abc$27210$new_n4445 $abc$27210$new_n4472 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] $abc$27210$new_n4474 $abc$27210$new_n4478 $abc$27210$auto$rtlil.cc:2693:MuxGate$21953 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4476 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[26] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[26] $abc$27210$new_n4474 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4417 $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[26] +00 1 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4477 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[26] $abc$27210$new_n4476 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[26] $abc$27210$new_n4438 $abc$27210$new_n4477 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4479 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4478 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] $abc$27210$new_n4445 $abc$27210$new_n4479 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] $abc$27210$new_n4481 $abc$27210$new_n4485 $abc$27210$auto$rtlil.cc:2693:MuxGate$21955 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4483 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[25] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[25] $abc$27210$new_n4481 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4416 $abc$27210$new_n4398 IBusCachedPlugin_predictionJumpInterface_payload[25] +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10010 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4484 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[25] $abc$27210$new_n4483 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[25] $abc$27210$new_n4438 $abc$27210$new_n4484 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4486 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4485 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] $abc$27210$new_n4445 $abc$27210$new_n4486 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] $abc$27210$new_n4488 $abc$27210$new_n4492 $abc$27210$auto$rtlil.cc:2693:MuxGate$21957 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4490 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[24] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[24] $abc$27210$new_n4488 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4416 $abc$27210$new_n4398 IBusCachedPlugin_predictionJumpInterface_payload[24] +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4491 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[24] $abc$27210$new_n4490 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[24] $abc$27210$new_n4438 $abc$27210$new_n4491 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4445 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4492 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] $abc$27210$new_n4494 $abc$27210$new_n4498 $abc$27210$auto$rtlil.cc:2693:MuxGate$21959 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4496 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[23] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[23] $abc$27210$new_n4494 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[23] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4497 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[23] $abc$27210$new_n4496 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[23] $abc$27210$new_n4438 $abc$27210$new_n4497 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4499 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$new_n4498 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n4446 $abc$27210$new_n4499 +011 1 +100 1 +101 1 +110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[22] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[22] $abc$27210$new_n4437 CsrPlugin_mepc[22] $abc$27210$new_n4438 $abc$27210$new_n4504 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n4446 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4505 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[21] +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[21] $abc$27210$new_n4437 CsrPlugin_mepc[21] $abc$27210$new_n4438 $abc$27210$new_n4510 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4512 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4511 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] $abc$27210$new_n4447 $abc$27210$new_n4512 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4415 $abc$27210$new_n4400 IBusCachedPlugin_predictionJumpInterface_payload[20] +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[20] $abc$27210$new_n4437 CsrPlugin_mepc[20] $abc$27210$new_n4438 $abc$27210$new_n4517 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4415 $abc$27210$new_n4400 IBusCachedPlugin_predictionJumpInterface_payload[19] +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[19] $abc$27210$new_n4437 CsrPlugin_mepc[19] $abc$27210$new_n4438 $abc$27210$new_n4524 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4401 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] IBusCachedPlugin_predictionJumpInterface_payload[18] +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[18] $abc$27210$new_n4437 CsrPlugin_mepc[18] $abc$27210$new_n4438 $abc$27210$new_n4531 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n4447 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4532 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4402 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] IBusCachedPlugin_predictionJumpInterface_payload[17] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[17] $abc$27210$new_n4437 CsrPlugin_mepc[17] $abc$27210$new_n4438 $abc$27210$new_n4537 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4539 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4538 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] $abc$27210$new_n4448 $abc$27210$new_n4539 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4403 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] IBusCachedPlugin_predictionJumpInterface_payload[16] +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[16] $abc$27210$new_n4437 CsrPlugin_mepc[16] $abc$27210$new_n4438 $abc$27210$new_n4544 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n4404 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] IBusCachedPlugin_predictionJumpInterface_payload[15] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[15] $abc$27210$new_n4437 CsrPlugin_mepc[15] $abc$27210$new_n4438 $abc$27210$new_n4551 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4405 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_predictionJumpInterface_payload[14] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[14] $abc$27210$new_n4437 CsrPlugin_mepc[14] $abc$27210$new_n4438 $abc$27210$new_n4558 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n4448 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4559 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4406 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_predictionJumpInterface_payload[13] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[13] $abc$27210$new_n4437 CsrPlugin_mepc[13] $abc$27210$new_n4438 $abc$27210$new_n4564 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4566 $abc$27210$new_n4565 +1000 1 +1010 1 +1100 1 +1101 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] $abc$27210$new_n4449 $abc$27210$new_n4566 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4407 $abc$27210$new_n4414 _zz_6 _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_predictionJumpInterface_payload[12] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[12] $abc$27210$new_n4437 CsrPlugin_mepc[12] $abc$27210$new_n4438 $abc$27210$new_n4571 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4575 $abc$27210$new_n4578 IBusCachedPlugin_predictionJumpInterface_payload[11] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4576 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[11] $abc$27210$new_n4575 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[11] $abc$27210$new_n4437 CsrPlugin_mepc[11] $abc$27210$new_n4438 $abc$27210$new_n4576 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4408 $abc$27210$new_n4414 _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_predictionJumpInterface_payload[11] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n4449 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4578 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21983 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4581 $abc$27210$new_n4584 IBusCachedPlugin_predictionJumpInterface_payload[10] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4582 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[10] $abc$27210$new_n4581 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[10] $abc$27210$new_n4437 CsrPlugin_mepc[10] $abc$27210$new_n4438 $abc$27210$new_n4582 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4409 IBusCachedPlugin_predictionJumpInterface_payload[10] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n4449 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$new_n4584 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21985 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4587 $abc$27210$new_n4590 IBusCachedPlugin_predictionJumpInterface_payload[9] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4588 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[9] $abc$27210$new_n4587 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[9] $abc$27210$new_n4437 CsrPlugin_mepc[9] $abc$27210$new_n4438 $abc$27210$new_n4588 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4409 IBusCachedPlugin_predictionJumpInterface_payload[9] +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$new_n4450 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4590 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21987 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4593 $abc$27210$new_n4596 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n4434 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[8] $abc$27210$new_n4595 DBusCachedPlugin_redoBranch_payload[8] $abc$27210$new_n4593 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4410 IBusCachedPlugin_predictionJumpInterface_payload[8] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names BranchPlugin_branchExceptionPort_payload_badAddr[8] $abc$27210$new_n4437 CsrPlugin_mepc[8] $abc$27210$new_n4438 $abc$27210$new_n4595 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$new_n4450 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$new_n4596 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21989 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4599 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4602 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4434 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[7] $abc$27210$new_n4601 DBusCachedPlugin_redoBranch_payload[7] $abc$27210$new_n4599 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4410 IBusCachedPlugin_predictionJumpInterface_payload[7] +000 1 +011 1 +101 1 +110 1 +.names BranchPlugin_branchExceptionPort_payload_badAddr[7] $abc$27210$new_n4437 CsrPlugin_mepc[7] $abc$27210$new_n4438 $abc$27210$new_n4601 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$new_n4451 $abc$27210$new_n4602 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21991 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4605 $abc$27210$new_n4608 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] +010 1 +011 1 +100 1 +110 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4606 IBusCachedPlugin_predictionJumpInterface_payload[6] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[6] $abc$27210$new_n4605 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[6] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[6] $abc$27210$new_n4606 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4411 IBusCachedPlugin_predictionJumpInterface_payload[6] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$new_n4451 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$new_n4608 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21993 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4611 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4614 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4612 IBusCachedPlugin_predictionJumpInterface_payload[5] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[5] $abc$27210$new_n4611 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[5] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[5] $abc$27210$new_n4612 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4411 IBusCachedPlugin_predictionJumpInterface_payload[5] +000 1 +011 1 +101 1 +110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$new_n4452 $abc$27210$new_n4614 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21995 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4617 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4620 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4618 IBusCachedPlugin_predictionJumpInterface_payload[4] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[4] $abc$27210$new_n4617 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[4] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[4] $abc$27210$new_n4618 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4412 $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_predictionJumpInterface_payload[4] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$new_n4452 $abc$27210$new_n4620 +01 1 +10 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21997 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4623 $abc$27210$new_n4626 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[3] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4624 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[3] $abc$27210$new_n4623 +000 1 +001 1 +011 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[3] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[3] $abc$27210$new_n4624 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4413 $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] IBusCachedPlugin_predictionJumpInterface_payload[3] +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4626 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21999 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4629 $abc$27210$new_n4632 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[2] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4630 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[2] $abc$27210$new_n4629 +000 1 +001 1 +011 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[2] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[2] $abc$27210$new_n4630 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_predictionJumpInterface_payload[2] +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4632 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22001 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[30] DBusCachedPlugin_redoBranch_payload[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22969 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4636 $abc$27210$new_n4093 $abc$27210$new_n4635 +00 1 +.names $abc$27210$new_n4428 $abc$27210$new_n4637 CsrPlugin_exceptionPendings_3 $abc$27210$new_n4636 +001 1 +010 1 +011 1 +.names $abc$27210$new_n4101 $abc$27210$new_n4096 $abc$27210$new_n4637 +10 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[29] DBusCachedPlugin_redoBranch_payload[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22971 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[28] DBusCachedPlugin_redoBranch_payload[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22973 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[27] DBusCachedPlugin_redoBranch_payload[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22975 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[26] DBusCachedPlugin_redoBranch_payload[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22977 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[25] DBusCachedPlugin_redoBranch_payload[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22979 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[24] DBusCachedPlugin_redoBranch_payload[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22981 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[23] DBusCachedPlugin_redoBranch_payload[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22983 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[22] DBusCachedPlugin_redoBranch_payload[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22985 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[21] DBusCachedPlugin_redoBranch_payload[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22987 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[20] DBusCachedPlugin_redoBranch_payload[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22989 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[19] DBusCachedPlugin_redoBranch_payload[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22991 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[18] DBusCachedPlugin_redoBranch_payload[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22993 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[17] DBusCachedPlugin_redoBranch_payload[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22995 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[16] DBusCachedPlugin_redoBranch_payload[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22997 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[15] DBusCachedPlugin_redoBranch_payload[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22999 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[14] DBusCachedPlugin_redoBranch_payload[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23001 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[13] DBusCachedPlugin_redoBranch_payload[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23003 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[12] DBusCachedPlugin_redoBranch_payload[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23005 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[9] DBusCachedPlugin_redoBranch_payload[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23007 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[8] DBusCachedPlugin_redoBranch_payload[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23009 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[7] DBusCachedPlugin_redoBranch_payload[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23011 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[6] DBusCachedPlugin_redoBranch_payload[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23013 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[5] DBusCachedPlugin_redoBranch_payload[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23015 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[4] DBusCachedPlugin_redoBranch_payload[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23017 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[3] DBusCachedPlugin_redoBranch_payload[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23019 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[2] DBusCachedPlugin_redoBranch_payload[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23021 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[1] DBusCachedPlugin_redoBranch_payload[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23023 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[0] DBusCachedPlugin_redoBranch_payload[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23025 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] iBus_cmd_payload_address[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23027 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] iBus_cmd_payload_address[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23029 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] iBus_cmd_payload_address[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23031 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] iBus_cmd_payload_address[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23033 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] iBus_cmd_payload_address[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23035 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] iBus_cmd_payload_address[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23037 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] iBus_cmd_payload_address[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23039 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] iBus_cmd_payload_address[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23041 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] iBus_cmd_payload_address[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23043 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] iBus_cmd_payload_address[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23045 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] iBus_cmd_payload_address[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23047 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] iBus_cmd_payload_address[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23049 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] iBus_cmd_payload_address[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23051 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] iBus_cmd_payload_address[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23053 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] iBus_cmd_payload_address[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23055 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] iBus_cmd_payload_address[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23057 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] iBus_cmd_payload_address[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23059 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] iBus_cmd_payload_address[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23061 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] iBus_cmd_payload_address[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23063 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] iBus_cmd_payload_address[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23065 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] iBus_cmd_payload_address[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23067 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] iBus_cmd_payload_address[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23069 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] iBus_cmd_payload_address[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23071 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] iBus_cmd_payload_address[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23073 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] iBus_cmd_payload_address[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23075 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] iBus_cmd_payload_address[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23077 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.lineLoader_address[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23079 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache.lineLoader_address[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23081 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.lineLoader_address[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23083 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] DBusCachedPlugin_exceptionBus_payload_badAddr[30] $abc$27210$new_n4744 $abc$27210$auto$rtlil.cc:2693:MuxGate$23085 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4697 $abc$27210$new_n8208 $abc$27210$new_n4696 +10 1 +.names $abc$27210$new_n4699 $abc$27210$new_n4698 $abc$27210$new_n4697 +10 1 +.names $abc$27210$new_n4637 MmuPlugin_dBusAccess_rsp_payload_redo $abc$27210$new_n4698 +10 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 $abc$27210$new_n4699 +00 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_error IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_iBusRsp_readyForError $abc$27210$new_n8213 $abc$27210$new_n4700 +1111 1 +.names execute_to_memory_BRANCH_DO BranchPlugin_branchExceptionPort_payload_badAddr[1] memory_arbitration_isValid $abc$27210$new_n4701 +111 1 +.names $abc$27210$new_n4710 $abc$27210$new_n4706 $abc$27210$new_n4708 $abc$27210$new_n4715 $abc$27210$new_n4714 $abc$27210$new_n4705 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4707 $abc$27210$new_n4706 +1111 1 +.names _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] $abc$27210$new_n4707 +00000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n4709 IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4708 +110 1 +.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4709 +00 1 +.names $abc$27210$new_n4711 $abc$27210$new_n4713 $abc$27210$new_n4712 _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4710 +1110 1 +.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4711 +000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4712 +110 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4713 +000 1 +.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4714 +00 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4715 +10 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4721 +11000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4722 +1100 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4723 +1000 1 +1010 1 +1011 1 +.names $abc$27210$new_n4726 $abc$27210$new_n4729 $abc$27210$new_n4728 IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4725 +1110 1 +.names $abc$27210$new_n4727 _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4726 +11000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4727 +10 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4728 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4729 +0000 1 +.names $abc$27210$new_n4709 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n4732 $abc$27210$new_n4733 IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4731 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4732 +1000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4733 +1000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4735 +00000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n4736 +0000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4740 +1110 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4744 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] DBusCachedPlugin_exceptionBus_payload_badAddr[29] $abc$27210$new_n4746 $abc$27210$auto$rtlil.cc:2693:MuxGate$23087 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4746 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4752 $abc$27210$new_n4698 $abc$27210$new_n4751 +10 1 +.names $abc$27210$new_n4700 $abc$27210$new_n4701 $abc$27210$new_n4752 +10 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4272 $abc$27210$new_n4270 $abc$27210$new_n4761 +10000 1 +11100 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4763 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] $abc$27210$new_n4764 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] DBusCachedPlugin_exceptionBus_payload_badAddr[26] $abc$27210$new_n4771 $abc$27210$auto$rtlil.cc:2693:MuxGate$23093 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$new_n4771 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] $abc$27210$new_n4773 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23095 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4774 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4773 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[25] BranchPlugin_branchExceptionPort_payload_badAddr[25] $abc$27210$new_n4701 $abc$27210$new_n4774 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] DBusCachedPlugin_exceptionBus_payload_badAddr[24] $abc$27210$new_n4776 $abc$27210$auto$rtlil.cc:2693:MuxGate$23097 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4776 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] DBusCachedPlugin_exceptionBus_payload_badAddr[23] $abc$27210$new_n4778 $abc$27210$auto$rtlil.cc:2693:MuxGate$23099 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4778 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] DBusCachedPlugin_exceptionBus_payload_badAddr[21] $abc$27210$new_n4783 $abc$27210$auto$rtlil.cc:2693:MuxGate$23103 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n4783 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n4791 $abc$27210$auto$rtlil.cc:2693:MuxGate$23109 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[18] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4791 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] $abc$27210$new_n4793 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23111 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4794 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4793 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[17] BranchPlugin_branchExceptionPort_payload_badAddr[17] $abc$27210$new_n4701 $abc$27210$new_n4794 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] $abc$27210$new_n4796 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23113 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4797 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4796 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[16] BranchPlugin_branchExceptionPort_payload_badAddr[16] $abc$27210$new_n4701 $abc$27210$new_n4797 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] DBusCachedPlugin_exceptionBus_payload_badAddr[15] $abc$27210$new_n4799 $abc$27210$auto$rtlil.cc:2693:MuxGate$23115 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$new_n4799 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] DBusCachedPlugin_exceptionBus_payload_badAddr[14] $abc$27210$new_n4801 $abc$27210$auto$rtlil.cc:2693:MuxGate$23117 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4801 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] DBusCachedPlugin_exceptionBus_payload_badAddr[13] $abc$27210$new_n4803 $abc$27210$auto$rtlil.cc:2693:MuxGate$23119 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4803 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] DBusCachedPlugin_exceptionBus_payload_badAddr[10] $abc$27210$new_n4812 $abc$27210$auto$rtlil.cc:2693:MuxGate$23125 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] $abc$27210$new_n4812 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n4817 $abc$27210$auto$rtlil.cc:2693:MuxGate$23129 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] $abc$27210$new_n4817 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n4819 $abc$27210$auto$rtlil.cc:2693:MuxGate$23131 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 $abc$27210$new_n4819 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n4821 $abc$27210$auto$rtlil.cc:2693:MuxGate$23133 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[6] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4821 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] DBusCachedPlugin_exceptionBus_payload_badAddr[5] $abc$27210$new_n4823 $abc$27210$auto$rtlil.cc:2693:MuxGate$23135 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] _zz__zz_decode_IS_CSR_41 $abc$27210$new_n4823 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n4828 $abc$27210$auto$rtlil.cc:2693:MuxGate$23139 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4828 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] $abc$27210$new_n4830 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23141 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4831 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4830 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[2] BranchPlugin_branchExceptionPort_payload_badAddr[2] $abc$27210$new_n4701 $abc$27210$new_n4831 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] $abc$27210$new_n4833 $abc$27210$auto$rtlil.cc:2693:MuxGate$23143 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4698 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4752 IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$new_n4701 $abc$27210$new_n4833 +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] $abc$27210$new_n4835 $abc$27210$auto$rtlil.cc:2693:MuxGate$23145 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] $abc$27210$new_n4699 $abc$27210$new_n4835 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] CsrPlugin_mtval[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23207 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] CsrPlugin_mtval[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23209 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] CsrPlugin_mtval[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23211 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] CsrPlugin_mtval[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23213 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] CsrPlugin_mtval[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23215 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] CsrPlugin_mtval[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23217 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] CsrPlugin_mtval[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23219 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] CsrPlugin_mtval[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23221 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] CsrPlugin_mtval[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23223 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] CsrPlugin_mtval[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23225 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] CsrPlugin_mtval[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23227 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] CsrPlugin_mtval[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23229 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] CsrPlugin_mtval[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23231 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] CsrPlugin_mtval[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23233 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] CsrPlugin_mtval[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23235 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] CsrPlugin_mtval[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23237 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] CsrPlugin_mtval[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23239 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] CsrPlugin_mtval[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23241 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] CsrPlugin_mtval[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23243 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] CsrPlugin_mtval[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23245 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] CsrPlugin_mtval[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23247 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[9] CsrPlugin_mtval[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23249 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] CsrPlugin_mtval[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23251 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] CsrPlugin_mtval[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23253 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] CsrPlugin_mtval[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23255 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] CsrPlugin_mtval[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23257 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[4] CsrPlugin_mtval[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23259 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] CsrPlugin_mtval[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23261 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] CsrPlugin_mtval[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23263 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] CsrPlugin_mtval[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23265 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] CsrPlugin_mtval[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23267 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4903 _zz_memory_DivPlugin_div_result_5 $abc$27210$new_n4905 $abc$27210$new_n4868 memory_DivPlugin_div_result[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23269 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n4869 $abc$27210$new_n4902 $abc$27210$new_n4901 $abc$27210$new_n4900 $abc$27210$new_n4868 +1000 1 +.names $abc$27210$new_n4870 $abc$27210$new_n4899 $abc$27210$new_n4898 $abc$27210$new_n4897 $abc$27210$new_n4869 +1111 1 +.names $abc$27210$new_n4871 $abc$27210$new_n4896 $abc$27210$new_n4895 $abc$27210$new_n4894 $abc$27210$new_n4893 $abc$27210$new_n4870 +10000 1 +.names $abc$27210$new_n4872 $abc$27210$new_n4892 $abc$27210$new_n4891 $abc$27210$new_n4890 $abc$27210$new_n4871 +1111 1 +.names $abc$27210$new_n4873 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[17] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] $abc$27210$new_n4872 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4874 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[16] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] $abc$27210$new_n4873 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4875 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[15] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$new_n4874 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4876 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[14] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] $abc$27210$new_n4875 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4877 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] $abc$27210$new_n4876 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4878 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[12] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] $abc$27210$new_n4877 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4879 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[11] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$new_n4878 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4880 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[10] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] $abc$27210$new_n4879 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4881 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[9] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$new_n4880 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4882 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[8] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] $abc$27210$new_n4881 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4883 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[7] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$new_n4882 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4884 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[6] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] $abc$27210$new_n4883 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4885 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[5] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] $abc$27210$new_n4884 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4886 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] _zz_memory_DivPlugin_div_stage_0_outNumerator[4] $abc$27210$new_n4885 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_memory_DivPlugin_div_result_5 $abc$27210$new_n4889 $abc$27210$new_n4888 $abc$27210$new_n4887 $abc$27210$new_n4886 +1111 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] _zz_memory_DivPlugin_div_stage_0_outNumerator[1] $abc$27210$new_n4887 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] _zz_memory_DivPlugin_div_stage_0_outNumerator[2] $abc$27210$new_n4888 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] _zz_memory_DivPlugin_div_stage_0_outNumerator[3] $abc$27210$new_n4889 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] _zz_memory_DivPlugin_div_stage_0_outNumerator[18] $abc$27210$new_n4890 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] _zz_memory_DivPlugin_div_stage_0_outNumerator[19] $abc$27210$new_n4891 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] _zz_memory_DivPlugin_div_stage_0_outNumerator[20] $abc$27210$new_n4892 +000 1 +010 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[21] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] $abc$27210$new_n4893 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[22] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] $abc$27210$new_n4894 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[23] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] $abc$27210$new_n4895 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[24] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] $abc$27210$new_n4896 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] _zz_memory_DivPlugin_div_stage_0_outNumerator[25] $abc$27210$new_n4897 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] _zz_memory_DivPlugin_div_stage_0_outNumerator[26] $abc$27210$new_n4898 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] _zz_memory_DivPlugin_div_stage_0_outNumerator[27] $abc$27210$new_n4899 +000 1 +010 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[28] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] $abc$27210$new_n4900 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[29] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] $abc$27210$new_n4901 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[30] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] $abc$27210$new_n4902 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4904 memory_DivPlugin_div_counter_value[0] $abc$27210$new_n4903 +110 1 +.names memory_DivPlugin_div_counter_value[5] memory_DivPlugin_div_counter_value[4] memory_DivPlugin_div_counter_value[3] memory_DivPlugin_div_counter_value[2] memory_DivPlugin_div_counter_value[1] $abc$27210$new_n4904 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_zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] $abc$27210$new_n4964 $abc$27210$new_n4963 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] $abc$27210$new_n4965 $abc$27210$new_n4964 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[20] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] $abc$27210$new_n4966 $abc$27210$new_n4965 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] $abc$27210$new_n4967 $abc$27210$new_n4966 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] $abc$27210$new_n4968 $abc$27210$new_n4967 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] $abc$27210$new_n4969 $abc$27210$new_n4968 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] $abc$27210$new_n4970 $abc$27210$new_n4969 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] $abc$27210$new_n4971 $abc$27210$new_n4970 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] $abc$27210$new_n4972 $abc$27210$new_n4971 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] $abc$27210$new_n4973 $abc$27210$new_n4972 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] $abc$27210$new_n4974 $abc$27210$new_n4973 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] $abc$27210$new_n4975 $abc$27210$new_n4974 +001 1 +100 1 +101 1 +111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] memory_DivPlugin_div_stage_0_remainderShifted _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] $abc$27210$new_n4975 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[30] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[29] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] $abc$27210$new_n4961 $abc$27210$new_n4976 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] $abc$27210$new_n4978 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23395 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[29] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] $abc$27210$new_n4961 $abc$27210$new_n4978 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] $abc$27210$new_n4980 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23397 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[28] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[27] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] $abc$27210$new_n4962 $abc$27210$new_n4980 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] $abc$27210$new_n4982 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23399 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[27] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] $abc$27210$new_n4962 $abc$27210$new_n4982 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] $abc$27210$new_n4984 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23401 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[26] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] $abc$27210$new_n4963 $abc$27210$new_n4984 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] $abc$27210$new_n4986 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23403 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] $abc$27210$new_n4963 $abc$27210$new_n4986 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] $abc$27210$new_n4988 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23405 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[24] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[23] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] $abc$27210$new_n4964 $abc$27210$new_n4988 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] $abc$27210$new_n4990 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23407 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[23] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] $abc$27210$new_n4964 $abc$27210$new_n4990 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] $abc$27210$new_n4992 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23409 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] $abc$27210$new_n4965 $abc$27210$new_n4992 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4994 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23411 +001 1 +011 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] $abc$27210$new_n4965 $abc$27210$new_n4959 $abc$27210$new_n4994 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] $abc$27210$new_n4996 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23413 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[20] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] $abc$27210$new_n4966 $abc$27210$new_n4996 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] $abc$27210$new_n4998 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23415 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] $abc$27210$new_n4966 $abc$27210$new_n4998 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] $abc$27210$new_n5000 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23417 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] $abc$27210$new_n4967 $abc$27210$new_n5000 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n5002 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23419 +001 1 +011 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] $abc$27210$new_n4967 $abc$27210$new_n4959 $abc$27210$new_n5002 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] $abc$27210$new_n5004 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23421 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$new_n4968 $abc$27210$new_n5004 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] $abc$27210$new_n5006 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23423 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$new_n4968 $abc$27210$new_n5006 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$new_n5008 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23425 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] $abc$27210$new_n4969 $abc$27210$new_n5008 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n5010 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23427 +001 1 +011 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] $abc$27210$new_n4969 $abc$27210$new_n4959 $abc$27210$new_n5010 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] $abc$27210$new_n5012 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23429 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$new_n4970 $abc$27210$new_n5012 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] $abc$27210$new_n5014 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23431 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$new_n4970 $abc$27210$new_n5014 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$new_n5016 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23433 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$new_n4971 $abc$27210$new_n5016 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] $abc$27210$new_n5018 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23435 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$new_n4971 $abc$27210$new_n5018 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$new_n5020 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23437 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$new_n4972 $abc$27210$new_n5020 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] $abc$27210$new_n5022 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23439 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$new_n4972 $abc$27210$new_n5022 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$new_n5024 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23441 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] $abc$27210$new_n4973 $abc$27210$new_n5024 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n5026 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23443 +001 1 +011 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] $abc$27210$new_n4973 $abc$27210$new_n4959 $abc$27210$new_n5026 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] $abc$27210$new_n5028 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23445 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] $abc$27210$new_n4974 $abc$27210$new_n5028 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] $abc$27210$new_n5030 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23447 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] $abc$27210$new_n4974 $abc$27210$new_n5030 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] $abc$27210$new_n5032 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23449 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] $abc$27210$new_n4975 $abc$27210$new_n5032 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] $abc$27210$new_n5034 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23451 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] memory_DivPlugin_div_stage_0_remainderShifted $abc$27210$new_n5034 +0010 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1110 1 +.names $abc$27210$new_n4261 memory_DivPlugin_div_stage_0_remainderShifted _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23453 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[9] MmuPlugin_shared_dBusRspStaged_payload_data[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23457 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[8] MmuPlugin_shared_dBusRspStaged_payload_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23459 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[7] MmuPlugin_shared_dBusRspStaged_payload_data[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23461 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[6] MmuPlugin_shared_dBusRspStaged_payload_data[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23463 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[5] MmuPlugin_shared_dBusRspStaged_payload_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23465 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[4] MmuPlugin_shared_dBusRspStaged_payload_data[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23467 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[3] MmuPlugin_shared_dBusRspStaged_payload_data[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23469 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[2] MmuPlugin_shared_dBusRspStaged_payload_data[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23471 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[1] MmuPlugin_shared_dBusRspStaged_payload_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23473 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[0] MmuPlugin_shared_dBusRspStaged_payload_data[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23475 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[8] MmuPlugin_shared_dBusRspStaged_payload_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23477 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[7] MmuPlugin_shared_dBusRspStaged_payload_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23479 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[6] MmuPlugin_shared_dBusRspStaged_payload_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23481 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[5] MmuPlugin_shared_dBusRspStaged_payload_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23483 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[4] MmuPlugin_shared_dBusRspStaged_payload_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23485 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[3] MmuPlugin_shared_dBusRspStaged_payload_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23487 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[2] MmuPlugin_shared_dBusRspStaged_payload_data[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23489 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[1] MmuPlugin_shared_dBusRspStaged_payload_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23491 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[0] MmuPlugin_shared_dBusRspStaged_payload_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23493 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_vpn_1[8] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23495 +01 1 +10 1 +11 1 +.names $abc$27210$new_n4315 $abc$27210$new_n4329 $abc$27210$new_n5056 +11 1 +.names MmuPlugin_shared_vpn_1[7] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23497 +10 1 +.names MmuPlugin_shared_vpn_1[6] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23499 +10 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_shared_vpn_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23501 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_shared_vpn_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23503 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_shared_vpn_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23505 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_shared_vpn_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23507 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_shared_vpn_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23509 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_shared_vpn_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23511 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_shared_vpn_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23513 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_shared_vpn_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23515 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_shared_vpn_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23517 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_shared_vpn_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23519 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_shared_vpn_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23521 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_shared_vpn_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23523 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_shared_vpn_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23525 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_shared_vpn_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23527 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_shared_vpn_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23529 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23531 +001 1 +011 1 +110 1 +111 1 +.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5075 +1110 1 +.names when_MmuPlugin_l281_1 MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo $abc$27210$new_n4391 $abc$27210$new_n5076 +1100 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23533 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23535 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23537 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23539 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23541 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23543 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23545 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23547 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_5_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23549 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_5_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23551 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_5_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23553 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_5_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23555 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_5_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23557 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_5_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23559 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_5_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23561 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_5_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23563 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_5_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23565 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_5_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23567 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_5_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23569 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_5_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23571 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_5_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23573 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_5_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23575 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_5_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23577 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23579 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_5_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23581 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_5_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23583 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_5_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23585 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_5_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23587 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_5_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23589 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_5_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23591 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_5_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23593 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23595 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_5_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23597 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_5_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23599 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_5_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23601 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23603 +001 1 +011 1 +110 1 +111 1 +.names MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5113 +1100 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23605 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23607 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23609 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23611 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23613 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23615 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23617 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23619 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_4_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23621 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_4_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23623 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_4_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23625 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_4_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23627 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_4_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23629 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_4_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23631 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_4_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23633 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_4_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23635 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_4_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23637 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_4_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23639 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_4_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23641 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_4_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23643 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_4_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23645 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23647 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_4_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23649 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_4_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23651 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_4_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23653 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_4_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23655 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_4_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23657 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_4_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23659 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_4_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23661 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_4_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23663 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_4_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23665 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_4_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23667 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_4_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23669 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_4_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23671 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_4_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23673 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23675 +001 1 +011 1 +110 1 +111 1 +.names MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5150 +1110 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23677 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23679 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23681 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23683 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23685 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23687 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23689 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23691 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_3_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23693 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_3_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23695 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_3_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23697 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_3_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23699 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_3_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23701 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_3_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23703 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_3_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23705 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_3_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23707 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_3_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23709 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23711 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_3_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23713 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_3_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23715 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_3_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23717 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23719 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_3_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23721 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_3_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23723 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_3_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23725 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_3_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23727 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_3_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23729 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_3_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23731 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_3_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23733 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_3_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23735 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_3_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23737 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23739 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_3_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23741 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_3_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23743 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_3_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23745 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23747 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5187 +1100 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23749 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23751 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23753 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23755 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23757 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23759 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23761 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23763 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_2_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23765 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_2_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23767 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_2_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23769 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_2_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23771 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_2_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23773 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_2_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23775 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_2_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23777 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_2_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23779 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_2_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23781 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_2_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23783 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_2_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23785 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_2_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23787 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_2_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23789 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23791 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_2_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23793 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_2_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23795 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_2_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23797 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_2_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23799 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_2_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23801 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_2_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23803 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_2_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23805 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_2_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23807 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_2_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23809 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23811 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_2_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23813 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_2_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23815 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_2_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23817 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23819 +001 1 +011 1 +110 1 +111 1 +.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5224 +1100 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23821 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23823 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23825 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23827 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23829 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23831 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23833 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23835 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_1_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23837 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_1_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23839 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_1_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23841 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_1_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23843 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_1_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23845 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_1_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23847 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_1_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23849 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_1_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23851 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_1_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23853 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_1_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23855 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_1_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23857 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_1_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23859 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_1_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23861 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_1_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23863 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_1_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23865 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_1_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23867 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_1_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23869 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_1_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23871 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_1_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23873 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_1_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23875 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_1_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23877 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_1_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23879 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_1_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23881 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_1_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23883 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_1_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23885 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_1_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23887 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_1_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23889 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23891 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5261 +1000 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23893 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23895 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23897 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23899 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23901 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23903 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23905 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23907 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_0_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23909 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_0_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23911 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_0_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23913 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_0_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23915 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_0_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23917 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_0_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23919 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_0_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23921 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_0_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23923 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_0_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23925 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23927 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_0_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23929 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_0_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23931 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_0_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23933 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_0_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23935 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_0_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23937 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_0_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23939 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_0_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23941 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23943 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_0_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23945 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_0_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23947 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_0_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23949 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_0_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23951 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_0_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23953 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_0_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23955 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_0_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23957 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_0_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23959 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_0_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23961 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5299 MmuPlugin_satp_ppn[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23963 +001 1 +011 1 +100 1 +101 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_384 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n5298 +1111 1 +.names $abc$27210$new_n5302 switch_Misc_l241_1 $abc$27210$new_n5300 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5299 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n5301 execute_CsrPlugin_csr_833 CsrPlugin_mepc[20] $abc$27210$new_n5300 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[20] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[20] $abc$27210$new_n5301 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[20] _zz_execute_BranchPlugin_branch_src2_8 $abc$27210$new_n5302 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5304 MmuPlugin_satp_ppn[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23965 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5307 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5305 $abc$27210$new_n5304 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5306 execute_CsrPlugin_csr_835 CsrPlugin_mtval[19] MmuPlugin_satp_ppn[19] execute_CsrPlugin_csr_384 $abc$27210$new_n5305 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names MmuPlugin_status_mxr CsrPlugin_mepc[19] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5306 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10100 1 +11000 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[19] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n5307 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5309 MmuPlugin_satp_ppn[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23967 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5312 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5310 $abc$27210$new_n5309 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5311 execute_CsrPlugin_csr_835 CsrPlugin_mtval[18] MmuPlugin_satp_ppn[18] execute_CsrPlugin_csr_384 $abc$27210$new_n5310 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names MmuPlugin_status_sum CsrPlugin_mepc[18] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5311 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10100 1 +11000 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[18] _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$new_n5312 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5314 MmuPlugin_satp_ppn[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23969 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5317 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5315 $abc$27210$new_n5314 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$27210$new_n5316 execute_CsrPlugin_csr_835 CsrPlugin_mtval[17] MmuPlugin_satp_ppn[17] execute_CsrPlugin_csr_384 $abc$27210$new_n5315 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names MmuPlugin_status_mprv CsrPlugin_mepc[17] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5316 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10100 1 +11000 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[17] _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$new_n5317 +0010 1 +0011 1 +1001 1 +1011 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5319 MmuPlugin_satp_ppn[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23971 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5322 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5320 $abc$27210$new_n5319 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5321 execute_CsrPlugin_csr_833 CsrPlugin_mepc[16] $abc$27210$new_n5320 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[16] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[16] $abc$27210$new_n5321 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[16] _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$new_n5322 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5324 MmuPlugin_satp_ppn[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23973 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5327 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5325 $abc$27210$new_n5324 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5326 execute_CsrPlugin_csr_833 CsrPlugin_mepc[15] $abc$27210$new_n5325 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[15] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[15] $abc$27210$new_n5326 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[15] _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$new_n5327 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5329 MmuPlugin_satp_ppn[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23975 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5332 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5330 $abc$27210$new_n5329 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5331 execute_CsrPlugin_csr_833 CsrPlugin_mepc[14] $abc$27210$new_n5330 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[14] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[14] $abc$27210$new_n5331 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[14] _zz__zz_execute_BranchPlugin_branch_src2_2[13] $abc$27210$new_n5332 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5334 MmuPlugin_satp_ppn[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23977 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5337 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5335 $abc$27210$new_n5334 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5336 execute_CsrPlugin_csr_833 CsrPlugin_mepc[13] $abc$27210$new_n5335 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[13] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[13] $abc$27210$new_n5336 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[13] switch_Misc_l241_1 $abc$27210$new_n5337 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5339 MmuPlugin_satp_ppn[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23979 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5342 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5340 $abc$27210$new_n5339 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5341 CsrPlugin_mepc[12] execute_CsrPlugin_csr_833 CsrPlugin_mstatus_MPP[1] execute_CsrPlugin_csr_768 $abc$27210$new_n5340 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[12] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[12] $abc$27210$new_n5341 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[12] _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5342 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5344 MmuPlugin_satp_ppn[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23981 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5348 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5345 $abc$27210$new_n5344 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$27210$new_n5346 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[11] execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MPP[0] $abc$27210$new_n5345 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n5347 execute_CsrPlugin_csr_772 CsrPlugin_mie_MEIE execute_CsrPlugin_csr_836 CsrPlugin_mip_MEIP $abc$27210$new_n5346 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[11] CsrPlugin_mepc[11] execute_CsrPlugin_csr_833 $abc$27210$new_n5347 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names execute_RS1[11] $abc$27210$new_n5349 $abc$27210$new_n5348 +11 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] $abc$27210$new_n5349 +00 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5351 MmuPlugin_satp_ppn[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23983 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5352 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5353 $abc$27210$new_n5351 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[10] $abc$27210$new_n5349 $abc$27210$new_n5352 +11 1 +.names $abc$27210$new_n5354 execute_CsrPlugin_csr_833 CsrPlugin_mepc[10] $abc$27210$new_n5353 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[10] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[10] $abc$27210$new_n5354 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5356 MmuPlugin_satp_ppn[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23985 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5357 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5358 $abc$27210$new_n5356 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[9] $abc$27210$new_n5349 $abc$27210$new_n5357 +11 1 +.names $abc$27210$new_n5359 execute_CsrPlugin_csr_833 CsrPlugin_mepc[9] $abc$27210$new_n5358 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[9] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[9] $abc$27210$new_n5359 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5361 MmuPlugin_satp_ppn[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23987 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5362 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5363 $abc$27210$new_n5361 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[8] $abc$27210$new_n5349 $abc$27210$new_n5362 +11 1 +.names $abc$27210$new_n5364 execute_CsrPlugin_csr_833 CsrPlugin_mepc[8] $abc$27210$new_n5363 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[8] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[8] $abc$27210$new_n5364 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5366 MmuPlugin_satp_ppn[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23989 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5370 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5367 $abc$27210$new_n5366 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$27210$new_n5368 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[7] execute_CsrPlugin_csr_772 CsrPlugin_mie_MTIE $abc$27210$new_n5367 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n5369 CsrPlugin_mip_MTIP execute_CsrPlugin_csr_836 execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MPIE $abc$27210$new_n5368 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[7] CsrPlugin_mepc[7] execute_CsrPlugin_csr_833 $abc$27210$new_n5369 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names execute_RS1[7] $abc$27210$new_n5349 $abc$27210$new_n5370 +11 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5372 MmuPlugin_satp_ppn[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23991 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5373 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5374 $abc$27210$new_n5372 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[6] $abc$27210$new_n5349 $abc$27210$new_n5373 +11 1 +.names $abc$27210$new_n5375 execute_CsrPlugin_csr_833 CsrPlugin_mepc[6] $abc$27210$new_n5374 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[6] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[6] $abc$27210$new_n5375 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5377 MmuPlugin_satp_ppn[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23993 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5378 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5379 $abc$27210$new_n5377 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[5] $abc$27210$new_n5349 $abc$27210$new_n5378 +11 1 +.names $abc$27210$new_n5380 execute_CsrPlugin_csr_833 CsrPlugin_mepc[5] $abc$27210$new_n5379 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[5] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[5] $abc$27210$new_n5380 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5382 MmuPlugin_satp_ppn[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23995 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5385 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5383 $abc$27210$new_n5382 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5384 execute_CsrPlugin_csr_833 CsrPlugin_mepc[4] $abc$27210$new_n5383 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[4] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[4] $abc$27210$new_n5384 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[4] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n5385 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5387 MmuPlugin_satp_ppn[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23997 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5392 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5388 $abc$27210$new_n5387 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5391 $abc$27210$new_n5389 CsrPlugin_mie_MSIE execute_CsrPlugin_csr_772 $abc$27210$new_n5388 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n5390 execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[3] execute_CsrPlugin_csr_836 CsrPlugin_mip_MSIP $abc$27210$new_n5389 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[3] CsrPlugin_mstatus_MIE execute_CsrPlugin_csr_768 $abc$27210$new_n5390 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[3] CsrPlugin_mepc[3] execute_CsrPlugin_csr_833 $abc$27210$new_n5391 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[3] _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$new_n5392 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5394 MmuPlugin_satp_ppn[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23999 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5397 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5395 $abc$27210$new_n5394 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$27210$new_n5396 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[2] execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$27210$new_n5395 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[2] CsrPlugin_mepc[2] execute_CsrPlugin_csr_833 $abc$27210$new_n5396 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[2] _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$new_n5397 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5399 MmuPlugin_satp_ppn[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24001 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5402 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5400 $abc$27210$new_n5399 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5401 execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[1] execute_CsrPlugin_csr_833 CsrPlugin_mepc[1] $abc$27210$new_n5400 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[1] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[1] $abc$27210$new_n5401 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[1] _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$new_n5402 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5404 MmuPlugin_satp_ppn[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24003 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5407 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5405 $abc$27210$new_n5404 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5406 execute_CsrPlugin_csr_835 CsrPlugin_mtval[0] execute_CsrPlugin_csr_833 CsrPlugin_mepc[0] $abc$27210$new_n5405 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[0] CsrPlugin_mcause_exceptionCode[0] execute_CsrPlugin_csr_834 $abc$27210$new_n5406 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[0] _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$new_n5407 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5409 MmuPlugin_satp_asid[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24005 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5412 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5410 $abc$27210$new_n5409 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5411 execute_CsrPlugin_csr_833 CsrPlugin_mepc[29] $abc$27210$new_n5410 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[29] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[7] $abc$27210$new_n5411 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[29] _zz__zz_execute_BranchPlugin_branch_src2_2[8] $abc$27210$new_n5412 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5414 MmuPlugin_satp_asid[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24007 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5417 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5415 $abc$27210$new_n5414 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5416 execute_CsrPlugin_csr_833 CsrPlugin_mepc[28] $abc$27210$new_n5415 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[28] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[6] $abc$27210$new_n5416 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[28] _zz__zz_execute_BranchPlugin_branch_src2_2[7] $abc$27210$new_n5417 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5419 MmuPlugin_satp_asid[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24009 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5422 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5420 $abc$27210$new_n5419 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5421 execute_CsrPlugin_csr_833 CsrPlugin_mepc[27] $abc$27210$new_n5420 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[27] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[5] $abc$27210$new_n5421 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[27] _zz__zz_execute_BranchPlugin_branch_src2_2[6] $abc$27210$new_n5422 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5424 MmuPlugin_satp_asid[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24011 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5427 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5425 $abc$27210$new_n5424 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5426 execute_CsrPlugin_csr_833 CsrPlugin_mepc[26] $abc$27210$new_n5425 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[26] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[4] $abc$27210$new_n5426 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[26] _zz__zz_execute_BranchPlugin_branch_src2_2[5] $abc$27210$new_n5427 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5429 MmuPlugin_satp_asid[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24013 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5432 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5430 $abc$27210$new_n5429 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5431 execute_CsrPlugin_csr_833 CsrPlugin_mepc[25] $abc$27210$new_n5430 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[25] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[3] $abc$27210$new_n5431 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[25] _zz__zz_execute_BranchPlugin_branch_src2_2[4] $abc$27210$new_n5432 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5434 MmuPlugin_satp_asid[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24015 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5437 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5435 $abc$27210$new_n5434 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5436 execute_CsrPlugin_csr_833 CsrPlugin_mepc[24] $abc$27210$new_n5435 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[24] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[2] $abc$27210$new_n5436 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[24] _zz__zz_execute_BranchPlugin_branch_src2_2[3] $abc$27210$new_n5437 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5439 MmuPlugin_satp_asid[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24017 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5442 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5440 $abc$27210$new_n5439 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5441 execute_CsrPlugin_csr_833 CsrPlugin_mepc[23] $abc$27210$new_n5440 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[23] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[1] $abc$27210$new_n5441 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[23] _zz__zz_execute_BranchPlugin_branch_src2_2[2] $abc$27210$new_n5442 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5444 MmuPlugin_satp_asid[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24019 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5447 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5445 $abc$27210$new_n5444 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5446 execute_CsrPlugin_csr_833 CsrPlugin_mepc[22] $abc$27210$new_n5445 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[22] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[0] $abc$27210$new_n5446 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[22] _zz__zz_execute_BranchPlugin_branch_src2_2[1] $abc$27210$new_n5447 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24021 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24023 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24025 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24027 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24029 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24031 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24033 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24035 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24037 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24039 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24041 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24043 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24045 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24047 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24049 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24051 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24053 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24055 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24057 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24059 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24061 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24063 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24065 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24067 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24069 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24071 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24073 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24075 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24077 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz__zz_3_port1[0] _zz_decode_PREDICTION_CONTEXT_line_history_2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24079 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[8] _zz_decode_PREDICTION_CONTEXT_hazard_3[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24081 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[7] _zz_decode_PREDICTION_CONTEXT_hazard_3[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24083 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[6] _zz_decode_PREDICTION_CONTEXT_hazard_3[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24085 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[5] _zz_decode_PREDICTION_CONTEXT_hazard_3[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24087 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[4] _zz_decode_PREDICTION_CONTEXT_hazard_3[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24089 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[3] _zz_decode_PREDICTION_CONTEXT_hazard_3[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24091 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[2] _zz_decode_PREDICTION_CONTEXT_hazard_3[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24093 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[1] _zz_decode_PREDICTION_CONTEXT_hazard_3[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24095 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[0] _zz_decode_PREDICTION_CONTEXT_hazard_3[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24097 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_mcause_exceptionCode[0] CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24159 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[30] $abc$27210$new_n5489 _zz_memory_DivPlugin_div_stage_0_outNumerator[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24161 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[30] $abc$27210$new_n5506 $abc$27210$new_n5490 $abc$27210$new_n5489 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n5491 execute_RS1[28] execute_RS1[29] $abc$27210$new_n5490 +100 1 +.names $abc$27210$new_n5492 execute_RS1[25] execute_RS1[26] execute_RS1[27] $abc$27210$new_n5491 +1000 1 +.names $abc$27210$new_n5493 execute_RS1[22] execute_RS1[23] execute_RS1[24] $abc$27210$new_n5492 +1000 1 +.names $abc$27210$new_n5494 execute_RS1[19] execute_RS1[20] execute_RS1[21] $abc$27210$new_n5493 +1000 1 +.names $abc$27210$new_n5495 execute_RS1[18] $abc$27210$new_n5494 +10 1 +.names $abc$27210$new_n5496 execute_RS1[17] $abc$27210$new_n5495 +10 1 +.names $abc$27210$new_n5497 execute_RS1[16] $abc$27210$new_n5496 +10 1 +.names $abc$27210$new_n5498 execute_RS1[15] $abc$27210$new_n5497 +10 1 +.names $abc$27210$new_n5499 execute_RS1[14] $abc$27210$new_n5498 +10 1 +.names $abc$27210$new_n5500 execute_RS1[13] $abc$27210$new_n5499 +10 1 +.names $abc$27210$new_n5501 execute_RS1[12] $abc$27210$new_n5500 +10 1 +.names $abc$27210$new_n5502 execute_RS1[11] $abc$27210$new_n5501 +10 1 +.names $abc$27210$new_n5503 execute_RS1[10] $abc$27210$new_n5502 +10 1 +.names $abc$27210$new_n5504 execute_RS1[7] execute_RS1[8] execute_RS1[9] $abc$27210$new_n5503 +1000 1 +.names $abc$27210$new_n5505 execute_RS1[4] execute_RS1[5] execute_RS1[6] $abc$27210$new_n5504 +1000 1 +.names $abc$27210$new_n5506 execute_RS1[0] execute_RS1[1] execute_RS1[2] execute_RS1[3] $abc$27210$new_n5505 +10000 1 +.names decode_to_execute_IS_DIV decode_to_execute_IS_RS1_SIGNED execute_RS1[31] $abc$27210$new_n5506 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[29] $abc$27210$new_n5508 _zz_memory_DivPlugin_div_stage_0_outNumerator[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24163 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[29] $abc$27210$new_n5491 $abc$27210$new_n5506 execute_RS1[28] $abc$27210$new_n5508 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[28] $abc$27210$new_n5510 _zz_memory_DivPlugin_div_stage_0_outNumerator[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24165 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[28] $abc$27210$new_n5506 $abc$27210$new_n5491 $abc$27210$new_n5510 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[27] $abc$27210$new_n5512 _zz_memory_DivPlugin_div_stage_0_outNumerator[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24167 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[27] $abc$27210$new_n5506 $abc$27210$new_n5492 execute_RS1[25] execute_RS1[26] $abc$27210$new_n5512 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[26] $abc$27210$new_n5514 _zz_memory_DivPlugin_div_stage_0_outNumerator[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24169 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[26] $abc$27210$new_n5492 $abc$27210$new_n5506 execute_RS1[25] $abc$27210$new_n5514 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[25] $abc$27210$new_n5516 _zz_memory_DivPlugin_div_stage_0_outNumerator[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24171 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[25] $abc$27210$new_n5506 $abc$27210$new_n5492 $abc$27210$new_n5516 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[24] $abc$27210$new_n5518 _zz_memory_DivPlugin_div_stage_0_outNumerator[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24173 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[24] $abc$27210$new_n5506 $abc$27210$new_n5493 execute_RS1[22] execute_RS1[23] $abc$27210$new_n5518 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[23] $abc$27210$new_n5520 _zz_memory_DivPlugin_div_stage_0_outNumerator[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24175 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[23] $abc$27210$new_n5493 $abc$27210$new_n5506 execute_RS1[22] $abc$27210$new_n5520 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[22] $abc$27210$new_n5522 _zz_memory_DivPlugin_div_stage_0_outNumerator[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24177 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[22] $abc$27210$new_n5506 $abc$27210$new_n5493 $abc$27210$new_n5522 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[21] $abc$27210$new_n5524 _zz_memory_DivPlugin_div_stage_0_outNumerator[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24179 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[21] $abc$27210$new_n5506 $abc$27210$new_n5494 execute_RS1[19] execute_RS1[20] $abc$27210$new_n5524 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[20] $abc$27210$new_n5526 _zz_memory_DivPlugin_div_stage_0_outNumerator[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24181 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[20] $abc$27210$new_n5494 $abc$27210$new_n5506 execute_RS1[19] $abc$27210$new_n5526 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[19] $abc$27210$new_n5528 _zz_memory_DivPlugin_div_stage_0_outNumerator[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24183 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[19] $abc$27210$new_n5506 $abc$27210$new_n5494 $abc$27210$new_n5528 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[18] $abc$27210$new_n5530 _zz_memory_DivPlugin_div_stage_0_outNumerator[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24185 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[18] $abc$27210$new_n5506 $abc$27210$new_n5495 $abc$27210$new_n5530 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[17] $abc$27210$new_n5532 _zz_memory_DivPlugin_div_stage_0_outNumerator[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24187 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[17] $abc$27210$new_n5506 $abc$27210$new_n5496 $abc$27210$new_n5532 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[16] $abc$27210$new_n5534 _zz_memory_DivPlugin_div_stage_0_outNumerator[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24189 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[16] $abc$27210$new_n5506 $abc$27210$new_n5497 $abc$27210$new_n5534 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[15] $abc$27210$new_n5536 _zz_memory_DivPlugin_div_stage_0_outNumerator[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24191 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[15] $abc$27210$new_n5506 $abc$27210$new_n5498 $abc$27210$new_n5536 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[14] _zz_memory_DivPlugin_div_stage_0_outNumerator[15] $abc$27210$new_n5538 $abc$27210$auto$rtlil.cc:2693:MuxGate$24193 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[14] $abc$27210$new_n5506 $abc$27210$new_n5499 $abc$27210$new_n5538 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[14] $abc$27210$new_n5540 $abc$27210$auto$rtlil.cc:2693:MuxGate$24195 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[13] $abc$27210$new_n5506 $abc$27210$new_n5500 $abc$27210$new_n5540 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[12] _zz_memory_DivPlugin_div_stage_0_outNumerator[13] $abc$27210$new_n5542 $abc$27210$auto$rtlil.cc:2693:MuxGate$24197 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[12] $abc$27210$new_n5506 $abc$27210$new_n5501 $abc$27210$new_n5542 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[11] _zz_memory_DivPlugin_div_stage_0_outNumerator[12] $abc$27210$new_n5544 $abc$27210$auto$rtlil.cc:2693:MuxGate$24199 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[11] $abc$27210$new_n5506 $abc$27210$new_n5502 $abc$27210$new_n5544 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[10] _zz_memory_DivPlugin_div_stage_0_outNumerator[11] $abc$27210$new_n5546 $abc$27210$auto$rtlil.cc:2693:MuxGate$24201 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[10] $abc$27210$new_n5506 $abc$27210$new_n5503 $abc$27210$new_n5546 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[9] _zz_memory_DivPlugin_div_stage_0_outNumerator[10] $abc$27210$new_n5548 $abc$27210$auto$rtlil.cc:2693:MuxGate$24203 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[9] $abc$27210$new_n5506 $abc$27210$new_n5504 execute_RS1[7] execute_RS1[8] $abc$27210$new_n5548 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[8] _zz_memory_DivPlugin_div_stage_0_outNumerator[9] $abc$27210$new_n5550 $abc$27210$auto$rtlil.cc:2693:MuxGate$24205 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[8] $abc$27210$new_n5504 $abc$27210$new_n5506 execute_RS1[7] $abc$27210$new_n5550 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[7] _zz_memory_DivPlugin_div_stage_0_outNumerator[8] $abc$27210$new_n5552 $abc$27210$auto$rtlil.cc:2693:MuxGate$24207 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[7] $abc$27210$new_n5506 $abc$27210$new_n5504 $abc$27210$new_n5552 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[6] _zz_memory_DivPlugin_div_stage_0_outNumerator[7] $abc$27210$new_n5554 $abc$27210$auto$rtlil.cc:2693:MuxGate$24209 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[6] $abc$27210$new_n5506 $abc$27210$new_n5505 execute_RS1[4] execute_RS1[5] $abc$27210$new_n5554 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[5] _zz_memory_DivPlugin_div_stage_0_outNumerator[6] $abc$27210$new_n5556 $abc$27210$auto$rtlil.cc:2693:MuxGate$24211 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[5] $abc$27210$new_n5505 $abc$27210$new_n5506 execute_RS1[4] $abc$27210$new_n5556 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[4] _zz_memory_DivPlugin_div_stage_0_outNumerator[5] $abc$27210$new_n5558 $abc$27210$auto$rtlil.cc:2693:MuxGate$24213 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[4] $abc$27210$new_n5506 $abc$27210$new_n5505 $abc$27210$new_n5558 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[3] _zz_memory_DivPlugin_div_stage_0_outNumerator[4] $abc$27210$new_n5560 $abc$27210$auto$rtlil.cc:2693:MuxGate$24215 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[3] $abc$27210$new_n5506 execute_RS1[0] execute_RS1[1] execute_RS1[2] $abc$27210$new_n5560 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[2] _zz_memory_DivPlugin_div_stage_0_outNumerator[3] $abc$27210$new_n5562 $abc$27210$auto$rtlil.cc:2693:MuxGate$24217 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[2] $abc$27210$new_n5506 execute_RS1[0] execute_RS1[1] $abc$27210$new_n5562 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[1] _zz_memory_DivPlugin_div_stage_0_outNumerator[2] $abc$27210$new_n5564 $abc$27210$auto$rtlil.cc:2693:MuxGate$24219 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[1] execute_RS1[0] $abc$27210$new_n5506 $abc$27210$new_n5564 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outNumerator[1] execute_RS1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24221 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] CsrPlugin_interrupt_code[2] CsrPlugin_mcause_exceptionCode[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24223 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4698 $abc$27210$new_n4699 memory_to_writeBack_MEMORY_WR $abc$27210$new_n8208 CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24237 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4751 $abc$27210$new_n5569 $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24239 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4698 dataCache_1.stageB_unaligned $abc$27210$new_n5569 +10 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24241 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24243 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24245 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24247 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24249 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24251 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24253 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24255 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24257 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24259 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24261 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24263 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24265 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24267 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24269 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24271 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24273 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24275 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24277 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[30] IBusCachedPlugin_cache._zz_banks_0_port1[30] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24279 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n5590 +000 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[29] IBusCachedPlugin_cache._zz_banks_0_port1[29] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24281 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[28] IBusCachedPlugin_cache._zz_banks_0_port1[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24283 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[27] IBusCachedPlugin_cache._zz_banks_0_port1[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24285 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[26] IBusCachedPlugin_cache._zz_banks_0_port1[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24287 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[25] IBusCachedPlugin_cache._zz_banks_0_port1[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24289 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[24] IBusCachedPlugin_cache._zz_banks_0_port1[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24291 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[23] IBusCachedPlugin_cache._zz_banks_0_port1[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24293 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[22] IBusCachedPlugin_cache._zz_banks_0_port1[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24295 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[21] IBusCachedPlugin_cache._zz_banks_0_port1[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24297 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[20] IBusCachedPlugin_cache._zz_banks_0_port1[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24299 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[19] IBusCachedPlugin_cache._zz_banks_0_port1[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24301 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[18] IBusCachedPlugin_cache._zz_banks_0_port1[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24303 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[17] IBusCachedPlugin_cache._zz_banks_0_port1[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24305 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[16] IBusCachedPlugin_cache._zz_banks_0_port1[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24307 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[15] IBusCachedPlugin_cache._zz_banks_0_port1[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24309 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[14] IBusCachedPlugin_cache._zz_banks_0_port1[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24311 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[13] IBusCachedPlugin_cache._zz_banks_0_port1[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24313 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[12] IBusCachedPlugin_cache._zz_banks_0_port1[12] _zz__zz_decode_IS_CSR_21 $abc$27210$auto$rtlil.cc:2693:MuxGate$24315 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[11] IBusCachedPlugin_cache._zz_banks_0_port1[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24317 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[10] IBusCachedPlugin_cache._zz_banks_0_port1[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24319 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[9] IBusCachedPlugin_cache._zz_banks_0_port1[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24321 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[8] IBusCachedPlugin_cache._zz_banks_0_port1[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24323 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[7] IBusCachedPlugin_cache._zz_banks_0_port1[7] _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 $abc$27210$auto$rtlil.cc:2693:MuxGate$24325 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[6] IBusCachedPlugin_cache._zz_banks_0_port1[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24327 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[5] IBusCachedPlugin_cache._zz_banks_0_port1[5] _zz__zz_decode_IS_CSR_41 $abc$27210$auto$rtlil.cc:2693:MuxGate$24329 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[4] IBusCachedPlugin_cache._zz_banks_0_port1[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24331 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[3] IBusCachedPlugin_cache._zz_banks_0_port1[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24333 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[2] IBusCachedPlugin_cache._zz_banks_0_port1[2] _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24335 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[1] IBusCachedPlugin_cache._zz_banks_0_port1[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24337 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[0] IBusCachedPlugin_cache._zz_banks_0_port1[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24339 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.lineLoader_wordIndex[1] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24341 +011 1 +100 1 +101 1 +110 1 +.names IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24343 +01 1 +10 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[30] HazardSimplePlugin_writeBackWrites_payload_data[30] debug_bus_rsp_data[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24403 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5646 $abc$27210$new_n4255 $abc$27210$new_n5625 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[30] HazardSimplePlugin_writeBackWrites_payload_data[30] +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5626 $abc$27210$new_n5645 _zz__zz_decode_RS2_2[30] $abc$27210$new_n5625 +10000 1 +10001 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[61] $abc$27210$new_n5627 $abc$27210$new_n5626 +010 1 +100 1 +110 1 +111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[60] $abc$27210$new_n5628 $abc$27210$new_n5627 +000 1 +001 1 +011 1 +101 1 +.names $abc$27210$new_n5644 _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[58] _zz_writeBack_MulPlugin_result_1[59] $abc$27210$new_n5629 $abc$27210$new_n5628 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[56] _zz_writeBack_MulPlugin_result_1[57] $abc$27210$new_n5630 $abc$27210$new_n5629 +0110 1 +1000 1 +.names $abc$27210$new_n5643 _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[54] _zz_writeBack_MulPlugin_result_1[55] $abc$27210$new_n5631 $abc$27210$new_n5630 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[52] _zz_writeBack_MulPlugin_result_1[53] $abc$27210$new_n5632 $abc$27210$new_n5631 +0110 1 +1000 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[51] $abc$27210$new_n5633 $abc$27210$new_n5632 +000 1 +001 1 +011 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] _zz_writeBack_MulPlugin_result_1[50] _zz_writeBack_MulPlugin_result[50] $abc$27210$new_n5634 $abc$27210$new_n5633 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] _zz_writeBack_MulPlugin_result_1[48] _zz_writeBack_MulPlugin_result[48] $abc$27210$new_n5635 $abc$27210$new_n5634 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] _zz_writeBack_MulPlugin_result_1[46] _zz_writeBack_MulPlugin_result[46] $abc$27210$new_n5636 $abc$27210$new_n5635 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] _zz_writeBack_MulPlugin_result_1[44] _zz_writeBack_MulPlugin_result[44] $abc$27210$new_n5637 $abc$27210$new_n5636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] _zz_writeBack_MulPlugin_result_1[42] _zz_writeBack_MulPlugin_result[42] $abc$27210$new_n5638 $abc$27210$new_n5637 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] _zz_writeBack_MulPlugin_result_1[40] _zz_writeBack_MulPlugin_result[40] $abc$27210$new_n5639 $abc$27210$new_n5638 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] _zz_writeBack_MulPlugin_result_1[38] _zz_writeBack_MulPlugin_result[38] $abc$27210$new_n5640 $abc$27210$new_n5639 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] _zz_writeBack_MulPlugin_result_1[36] _zz_writeBack_MulPlugin_result[36] $abc$27210$new_n5641 $abc$27210$new_n5640 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[34] _zz_writeBack_MulPlugin_result[34] $abc$27210$new_n5642 $abc$27210$new_n5641 +000 1 +001 1 +011 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[32] _zz_writeBack_MulPlugin_result[32] _zz_writeBack_MulPlugin_result_1[33] _zz_writeBack_MulPlugin_result[33] $abc$27210$new_n5642 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[53] _zz_writeBack_MulPlugin_result_1[52] $abc$27210$new_n5643 +000 1 +001 1 +010 1 +011 1 +100 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[57] _zz_writeBack_MulPlugin_result_1[56] $abc$27210$new_n5644 +000 1 +001 1 +010 1 +011 1 +100 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[62] $abc$27210$new_n5645 +00 1 +11 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 $abc$27210$new_n5656 _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5646 +1000 1 +1010 1 +1011 1 +.names MmuPlugin_dBusAccess_rsp_payload_data[7] $abc$27210$new_n4254 _zz_lastStageRegFileWrite_payload_address[14] $abc$27210$new_n5647 +110 1 +.names $abc$27210$new_n5649 MmuPlugin_dBusAccess_rsp_payload_data[23] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5650 $abc$27210$new_n5651 $abc$27210$new_n5652 $abc$27210$new_n5649 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[31] dataCache_1.stageB_dataMux[31] $abc$27210$new_n5650 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[7] dataCache_1.stageB_dataMux[7] $abc$27210$new_n5651 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[15] dataCache_1.stageB_dataMux[15] $abc$27210$new_n5652 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[23] dataCache_1.stageB_dataMux[23] MmuPlugin_dBusAccess_rsp_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4101 _zz_lastStageRegFileWrite_payload_address[12] MmuPlugin_dBusAccess_rsp_payload_data[15] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[14] $abc$27210$new_n5654 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5650 $abc$27210$new_n5652 MmuPlugin_dBusAccess_rsp_payload_data[15] +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[30] dataCache_1.stageB_dataMux[30] $abc$27210$new_n5656 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[29] HazardSimplePlugin_writeBackWrites_payload_data[29] debug_bus_rsp_data[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24405 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5660 $abc$27210$new_n5659 _zz__zz_decode_RS2_2[29] HazardSimplePlugin_writeBackWrites_payload_data[29] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[61] $abc$27210$new_n5627 $abc$27210$new_n5659 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5661 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[29] $abc$27210$new_n5660 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[29] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5661 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[29] dataCache_1.stageB_dataMux[29] MmuPlugin_dBusAccess_rsp_payload_data[29] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[28] HazardSimplePlugin_writeBackWrites_payload_data[28] debug_bus_rsp_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24407 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5666 $abc$27210$new_n5665 _zz__zz_decode_RS2_2[28] HazardSimplePlugin_writeBackWrites_payload_data[28] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[60] $abc$27210$new_n5628 $abc$27210$new_n5665 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5667 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[28] $abc$27210$new_n5666 +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5654 MmuPlugin_dBusAccess_rsp_payload_data[28] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5667 +100 1 +101 1 +110 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[28] dataCache_1.stageB_dataMux[28] MmuPlugin_dBusAccess_rsp_payload_data[28] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[27] HazardSimplePlugin_writeBackWrites_payload_data[27] debug_bus_rsp_data[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24409 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5672 $abc$27210$new_n5671 _zz__zz_decode_RS2_2[27] HazardSimplePlugin_writeBackWrites_payload_data[27] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[59] _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[58] $abc$27210$new_n5644 $abc$27210$new_n5629 $abc$27210$new_n5671 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10111 1 +11010 1 +.names $abc$27210$new_n5673 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[27] $abc$27210$new_n5672 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[27] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5673 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[27] dataCache_1.stageB_dataMux[27] MmuPlugin_dBusAccess_rsp_payload_data[27] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[26] HazardSimplePlugin_writeBackWrites_payload_data[26] debug_bus_rsp_data[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24411 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5678 $abc$27210$new_n5677 _zz__zz_decode_RS2_2[26] HazardSimplePlugin_writeBackWrites_payload_data[26] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[58] $abc$27210$new_n5644 $abc$27210$new_n5629 $abc$27210$new_n5677 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5679 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[26] $abc$27210$new_n5678 +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5654 MmuPlugin_dBusAccess_rsp_payload_data[26] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5679 +100 1 +101 1 +110 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[26] dataCache_1.stageB_dataMux[26] MmuPlugin_dBusAccess_rsp_payload_data[26] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[25] HazardSimplePlugin_writeBackWrites_payload_data[25] debug_bus_rsp_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24413 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5684 $abc$27210$new_n5683 _zz__zz_decode_RS2_2[25] HazardSimplePlugin_writeBackWrites_payload_data[25] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[57] _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[56] $abc$27210$new_n5630 $abc$27210$new_n5683 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$27210$new_n5685 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[25] $abc$27210$new_n5684 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[25] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5685 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[25] dataCache_1.stageB_dataMux[25] MmuPlugin_dBusAccess_rsp_payload_data[25] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[24] HazardSimplePlugin_writeBackWrites_payload_data[24] debug_bus_rsp_data[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24415 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5690 $abc$27210$new_n5689 _zz__zz_decode_RS2_2[24] HazardSimplePlugin_writeBackWrites_payload_data[24] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[56] $abc$27210$new_n5630 $abc$27210$new_n5689 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5691 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[24] $abc$27210$new_n5690 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[24] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5691 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[23] HazardSimplePlugin_writeBackWrites_payload_data[23] debug_bus_rsp_data[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24417 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5696 $abc$27210$new_n5694 _zz__zz_decode_RS2_2[23] HazardSimplePlugin_writeBackWrites_payload_data[23] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[55] _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[54] $abc$27210$new_n5695 $abc$27210$new_n5694 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$27210$new_n5643 $abc$27210$new_n5631 $abc$27210$new_n5695 +10 1 +.names $abc$27210$new_n5697 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[23] $abc$27210$new_n5696 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[23] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5697 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[22] HazardSimplePlugin_writeBackWrites_payload_data[22] debug_bus_rsp_data[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24419 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5701 $abc$27210$new_n5700 _zz__zz_decode_RS2_2[22] HazardSimplePlugin_writeBackWrites_payload_data[22] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[54] $abc$27210$new_n5695 $abc$27210$new_n5700 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5702 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[22] $abc$27210$new_n5701 +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5654 MmuPlugin_dBusAccess_rsp_payload_data[22] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5702 +100 1 +101 1 +110 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[22] dataCache_1.stageB_dataMux[22] MmuPlugin_dBusAccess_rsp_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[21] HazardSimplePlugin_writeBackWrites_payload_data[21] debug_bus_rsp_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24421 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5707 $abc$27210$new_n5706 _zz__zz_decode_RS2_2[21] HazardSimplePlugin_writeBackWrites_payload_data[21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[53] _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[52] $abc$27210$new_n5632 $abc$27210$new_n5706 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$27210$new_n5708 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[21] $abc$27210$new_n5707 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[21] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5708 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[21] dataCache_1.stageB_dataMux[21] MmuPlugin_dBusAccess_rsp_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[20] HazardSimplePlugin_writeBackWrites_payload_data[20] debug_bus_rsp_data[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24423 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5713 $abc$27210$new_n5712 _zz__zz_decode_RS2_2[20] HazardSimplePlugin_writeBackWrites_payload_data[20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[52] $abc$27210$new_n5632 $abc$27210$new_n5712 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5714 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[20] $abc$27210$new_n5713 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[20] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5714 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[20] dataCache_1.stageB_dataMux[20] MmuPlugin_dBusAccess_rsp_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[19] HazardSimplePlugin_writeBackWrites_payload_data[19] debug_bus_rsp_data[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24425 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5719 $abc$27210$new_n5718 _zz__zz_decode_RS2_2[19] HazardSimplePlugin_writeBackWrites_payload_data[19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[51] $abc$27210$new_n5633 $abc$27210$new_n5718 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5720 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[19] $abc$27210$new_n5719 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[19] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5720 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[19] dataCache_1.stageB_dataMux[19] MmuPlugin_dBusAccess_rsp_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[18] HazardSimplePlugin_writeBackWrites_payload_data[18] debug_bus_rsp_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24427 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5725 $abc$27210$new_n5724 _zz__zz_decode_RS2_2[18] HazardSimplePlugin_writeBackWrites_payload_data[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[50] _zz_writeBack_MulPlugin_result[50] _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] $abc$27210$new_n5634 $abc$27210$new_n5724 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n5726 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n5725 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[18] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5726 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[18] dataCache_1.stageB_dataMux[18] MmuPlugin_dBusAccess_rsp_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[17] HazardSimplePlugin_writeBackWrites_payload_data[17] debug_bus_rsp_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24429 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5731 $abc$27210$new_n5730 _zz__zz_decode_RS2_2[17] HazardSimplePlugin_writeBackWrites_payload_data[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] $abc$27210$new_n5634 $abc$27210$new_n5730 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5732 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[17] $abc$27210$new_n5731 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[17] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5732 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[17] dataCache_1.stageB_dataMux[17] MmuPlugin_dBusAccess_rsp_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[16] HazardSimplePlugin_writeBackWrites_payload_data[16] debug_bus_rsp_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24431 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5737 $abc$27210$new_n5736 _zz__zz_decode_RS2_2[16] HazardSimplePlugin_writeBackWrites_payload_data[16] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[48] _zz_writeBack_MulPlugin_result[48] _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] $abc$27210$new_n5635 $abc$27210$new_n5736 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n5738 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[16] $abc$27210$new_n5737 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[16] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5738 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[15] HazardSimplePlugin_writeBackWrites_payload_data[15] debug_bus_rsp_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24433 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5742 $abc$27210$new_n5741 _zz__zz_decode_RS2_2[15] HazardSimplePlugin_writeBackWrites_payload_data[15] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] $abc$27210$new_n5635 $abc$27210$new_n5741 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[15] MmuPlugin_dBusAccess_rsp_payload_data[15] $abc$27210$new_n4254 $abc$27210$new_n5742 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[14] HazardSimplePlugin_writeBackWrites_payload_data[14] debug_bus_rsp_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24435 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[46] _zz_writeBack_MulPlugin_result[46] _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] $abc$27210$new_n5636 $abc$27210$new_n5745 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5656 $abc$27210$new_n5749 MmuPlugin_dBusAccess_rsp_payload_data[14] +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[14] dataCache_1.stageB_dataMux[14] $abc$27210$new_n5749 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[13] HazardSimplePlugin_writeBackWrites_payload_data[13] debug_bus_rsp_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24437 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5753 $abc$27210$new_n5752 _zz__zz_decode_RS2_2[13] HazardSimplePlugin_writeBackWrites_payload_data[13] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] $abc$27210$new_n5636 $abc$27210$new_n5752 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[13] MmuPlugin_dBusAccess_rsp_payload_data[13] $abc$27210$new_n4254 $abc$27210$new_n5753 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[29] dBus_rsp_payload_data[13] dataCache_1.stageB_dataMux[13] MmuPlugin_dBusAccess_rsp_payload_data[13] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[12] HazardSimplePlugin_writeBackWrites_payload_data[12] debug_bus_rsp_data[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24439 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[44] _zz_writeBack_MulPlugin_result[44] _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] $abc$27210$new_n5637 $abc$27210$new_n5757 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[28] dBus_rsp_payload_data[12] dataCache_1.stageB_dataMux[12] MmuPlugin_dBusAccess_rsp_payload_data[12] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[11] HazardSimplePlugin_writeBackWrites_payload_data[11] debug_bus_rsp_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24441 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5764 $abc$27210$new_n5763 _zz__zz_decode_RS2_2[11] HazardSimplePlugin_writeBackWrites_payload_data[11] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] $abc$27210$new_n5637 $abc$27210$new_n5763 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[11] MmuPlugin_dBusAccess_rsp_payload_data[11] $abc$27210$new_n4254 $abc$27210$new_n5764 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[27] $abc$27210$new_n5766 MmuPlugin_dBusAccess_rsp_payload_data[11] +000 1 +010 1 +110 1 +111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[11] dataCache_1.stageB_dataMux[11] $abc$27210$new_n5766 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[10] HazardSimplePlugin_writeBackWrites_payload_data[10] debug_bus_rsp_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24443 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[42] _zz_writeBack_MulPlugin_result[42] _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] $abc$27210$new_n5638 $abc$27210$new_n5769 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[26] $abc$27210$new_n5773 MmuPlugin_dBusAccess_rsp_payload_data[10] +000 1 +010 1 +110 1 +111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[10] dataCache_1.stageB_dataMux[10] $abc$27210$new_n5773 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[9] HazardSimplePlugin_writeBackWrites_payload_data[9] debug_bus_rsp_data[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24445 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5776 $abc$27210$new_n5779 _zz__zz_decode_RS2_2[9] HazardSimplePlugin_writeBackWrites_payload_data[9] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5777 DBusCachedPlugin_exceptionBus_payload_badAddr[9] $abc$27210$new_n5776 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n5647 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4254 MmuPlugin_dBusAccess_rsp_payload_data[25] $abc$27210$new_n5778 $abc$27210$new_n5777 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[9] dataCache_1.stageB_dataMux[9] $abc$27210$new_n5778 +000 1 +010 1 +100 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] $abc$27210$new_n5638 $abc$27210$new_n5779 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[8] HazardSimplePlugin_writeBackWrites_payload_data[8] debug_bus_rsp_data[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24447 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5782 $abc$27210$new_n5784 _zz__zz_decode_RS2_2[8] HazardSimplePlugin_writeBackWrites_payload_data[8] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4101 $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5783 DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n5782 +00001 1 +00011 1 +00101 1 +00111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4254 MmuPlugin_dBusAccess_rsp_payload_data[24] $abc$27210$new_n4251 $abc$27210$new_n5783 +0000 1 +0010 1 +1010 1 +1011 1 +.names _zz_writeBack_MulPlugin_result_1[40] _zz_writeBack_MulPlugin_result[40] _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] $abc$27210$new_n5639 $abc$27210$new_n5784 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[7] HazardSimplePlugin_writeBackWrites_payload_data[7] debug_bus_rsp_data[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24449 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5788 $abc$27210$new_n5787 _zz__zz_decode_RS2_2[7] HazardSimplePlugin_writeBackWrites_payload_data[7] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] $abc$27210$new_n5639 $abc$27210$new_n5787 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4101 $abc$27210$new_n4255 MmuPlugin_dBusAccess_rsp_payload_data[7] DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n5788 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[6] HazardSimplePlugin_writeBackWrites_payload_data[6] debug_bus_rsp_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24451 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5791 $abc$27210$new_n5795 _zz__zz_decode_RS2_2[6] HazardSimplePlugin_writeBackWrites_payload_data[6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4101 $abc$27210$new_n4255 MmuPlugin_dBusAccess_rsp_payload_data[6] DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n5791 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$27210$new_n5793 MmuPlugin_dBusAccess_rsp_payload_data[22] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[6] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5656 $abc$27210$new_n5749 $abc$27210$new_n5794 $abc$27210$new_n5793 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[6] dataCache_1.stageB_dataMux[6] $abc$27210$new_n5794 +000 1 +010 1 +100 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[38] _zz_writeBack_MulPlugin_result[38] _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] $abc$27210$new_n5640 $abc$27210$new_n5795 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[5] HazardSimplePlugin_writeBackWrites_payload_data[5] debug_bus_rsp_data[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24453 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n8115 $abc$27210$new_n5798 _zz__zz_decode_RS2_2[5] HazardSimplePlugin_writeBackWrites_payload_data[5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] $abc$27210$new_n5640 $abc$27210$new_n5798 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[4] HazardSimplePlugin_writeBackWrites_payload_data[4] DebugPlugin_busReadDataReg[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24455 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5805 $abc$27210$new_n5808 _zz__zz_decode_RS2_2[4] HazardSimplePlugin_writeBackWrites_payload_data[4] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5806 DBusCachedPlugin_exceptionBus_payload_badAddr[4] $abc$27210$new_n5805 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[12] MmuPlugin_dBusAccess_rsp_payload_data[20] $abc$27210$new_n5807 $abc$27210$new_n5806 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[4] dataCache_1.stageB_dataMux[4] $abc$27210$new_n5807 +001 1 +011 1 +110 1 +111 1 +.names _zz_writeBack_MulPlugin_result_1[36] _zz_writeBack_MulPlugin_result[36] _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] $abc$27210$new_n5641 $abc$27210$new_n5808 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[3] HazardSimplePlugin_writeBackWrites_payload_data[3] DebugPlugin_busReadDataReg[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24457 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5811 $abc$27210$new_n5814 _zz__zz_decode_RS2_2[3] HazardSimplePlugin_writeBackWrites_payload_data[3] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4101 MmuPlugin_dBusAccess_rsp_payload_data[3] DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n5811 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5813 MmuPlugin_dBusAccess_rsp_payload_data[19] $abc$27210$new_n5766 MmuPlugin_dBusAccess_rsp_payload_data[3] +00000 1 +00001 1 +00010 1 +00011 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[27] dBus_rsp_payload_data[3] dataCache_1.stageB_dataMux[3] $abc$27210$new_n5813 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] $abc$27210$new_n5641 $abc$27210$new_n5814 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[2] HazardSimplePlugin_writeBackWrites_payload_data[2] DebugPlugin_busReadDataReg[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24459 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n5820 MmuPlugin_dBusAccess_rsp_payload_data[2] DBusCachedPlugin_exceptionBus_payload_badAddr[2] HazardSimplePlugin_writeBackWrites_payload_data[2] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n5818 MmuPlugin_dBusAccess_rsp_payload_data[18] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[2] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[26] $abc$27210$new_n5773 $abc$27210$new_n5819 $abc$27210$new_n5818 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[2] dataCache_1.stageB_dataMux[2] $abc$27210$new_n5819 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4254 _zz_writeBack_MulPlugin_result_1[34] _zz_writeBack_MulPlugin_result[34] $abc$27210$new_n5642 _zz__zz_decode_RS2_2[2] $abc$27210$new_n5820 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] $abc$27210$new_n4258 $abc$27210$auto$rtlil.cc:2693:MuxGate$24461 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation MmuPlugin_dBusAccess_rsp_valid memory_to_writeBack_IS_DBUS_SHARING $abc$27210$auto$rtlil.cc:2693:MuxGate$24463 +0100 1 +0101 1 +0110 1 +1001 1 +1101 1 +.names memory_to_writeBack_IS_DBUS_SHARING dBus_cmd_payload_wr $abc$27210$new_n4094 MmuPlugin_dBusAccess_rsp_payload_redo MmuPlugin_dBusAccess_rsp_valid +1000 1 +1001 1 +1011 1 +.names $abc$27210$new_n5825 $abc$27210$new_n4093 CsrPlugin_pipelineLiberator_pcValids_2 CsrPlugin_pipelineLiberator_pcValids_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24467 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4316 $abc$27210$new_n5826 $abc$27210$new_n4266 $abc$27210$new_n5825 +110 1 +.names $abc$27210$new_n5830 $abc$27210$new_n5827 $abc$27210$new_n5826 +11 1 +.names $abc$27210$new_n5828 $abc$27210$new_n4637 $abc$27210$new_n5827 +10 1 +.names $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n5829 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n5828 +10000 1 +10001 1 +10010 1 +.names $abc$27210$new_n4256 memory_arbitration_isValid lastStageIsValid $abc$27210$new_n5829 +100 1 +.names $abc$27210$new_n4700 $abc$27210$new_n8208 $abc$27210$new_n5830 +00 1 +.names $abc$27210$new_n5825 DBusCachedPlugin_mmuBus_cmd_0_isStuck CsrPlugin_pipelineLiberator_pcValids_1 CsrPlugin_pipelineLiberator_pcValids_0 $abc$27210$auto$rtlil.cc:2693:MuxGate$24469 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n5825 $abc$27210$new_n4259 CsrPlugin_pipelineLiberator_pcValids_0 $abc$27210$auto$rtlil.cc:2693:MuxGate$24471 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5834 $abc$27210$new_n5387 CsrPlugin_mie_MSIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24473 +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_772 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n5834 +1111 1 +.names $abc$27210$new_n5834 $abc$27210$new_n5366 CsrPlugin_mie_MTIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24475 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5834 $abc$27210$new_n5344 CsrPlugin_mie_MEIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24477 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5838 $abc$27210$new_n4324 MmuPlugin_shared_state_1[2] MmuPlugin_shared_dBusRspStaged_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24479 +0010 1 +0110 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[2] $abc$27210$new_n5838 +110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5840 MmuPlugin_satp_mode $abc$27210$auto$rtlil.cc:2693:MuxGate$24481 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5843 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5841 $abc$27210$new_n5840 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5842 execute_CsrPlugin_csr_384 MmuPlugin_satp_mode execute_CsrPlugin_csr_834 CsrPlugin_mcause_interrupt $abc$27210$new_n5841 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[31] CsrPlugin_mepc[31] execute_CsrPlugin_csr_833 $abc$27210$new_n5842 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] _zz_execute_BranchPlugin_branch_src2 execute_RS1[31] $abc$27210$new_n5843 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4435 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n4441 IBusCachedPlugin_injector_nextPcCalc_valids_0 IBusCachedPlugin_iBusRsp_readyForError $abc$27210$auto$rtlil.cc:2693:MuxGate$24483 +10001 1 +10011 1 +11010 1 +11011 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_injector_nextPcCalc_valids_0 $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$auto$rtlil.cc:2693:MuxGate$24485 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5847 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$auto$rtlil.cc:2693:MuxGate$24487 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n5830 $abc$27210$new_n5827 $abc$27210$new_n4441 $abc$27210$new_n4258 $abc$27210$new_n4424 $abc$27210$new_n5847 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n5849 IBusCachedPlugin_cache.io_cpu_fetch_isValid $abc$27210$new_n5847 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24489 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n5850 $abc$27210$new_n5858 $abc$27210$new_n5856 $abc$27210$new_n5855 $abc$27210$new_n5849 +11000 1 +.names $abc$27210$new_n4432 $abc$27210$new_n5852 $abc$27210$new_n5829 $abc$27210$new_n4636 $abc$27210$new_n5851 $abc$27210$new_n5850 +11000 1 +.names CsrPlugin_exceptionPendings_1 $abc$27210$new_n5827 $abc$27210$new_n5851 +11 1 +.names $abc$27210$new_n5853 IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.lineLoader_flushPending lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n5852 +10000 1 +10001 1 +10010 1 +.names IBusCachedPlugin_cache._zz_when_InstructionCache_l342 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_fetchPc_booted DebugPlugin_haltIt $abc$27210$new_n5854 $abc$27210$new_n5853 +11100 1 +.names DebugPlugin_stepIt IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.io_cpu_fetch_isValid $abc$27210$new_n5854 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5827 $abc$27210$new_n5830 CsrPlugin_exceptionPendings_0 $abc$27210$new_n5855 +100 1 +101 1 +111 1 +.names $abc$27210$new_n4431 $abc$27210$new_n5857 $abc$27210$new_n4701 CsrPlugin_exceptionPendings_2 $abc$27210$new_n5856 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4428 $abc$27210$new_n4637 $abc$27210$new_n5857 +00 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n5859 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4266 $abc$27210$new_n5858 +1100 1 +.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n5859 +10 1 +.names $abc$27210$new_n5849 IBusCachedPlugin_fetchPc_inc $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24491 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5862 $abc$27210$new_n5857 $abc$27210$new_n4093 lastStageIsValid $abc$27210$auto$rtlil.cc:2693:MuxGate$24493 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5863 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5862 +10 1 +.names memory_arbitration_isValid $abc$27210$new_n5857 $abc$27210$new_n4431 $abc$27210$new_n4701 $abc$27210$new_n5863 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5863 $abc$27210$new_n4259 execute_arbitration_isValid $abc$27210$new_n5827 $abc$27210$auto$rtlil.cc:2693:MuxGate$24495 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5866 $abc$27210$new_n4258 $abc$27210$new_n5826 $abc$27210$new_n4266 $abc$27210$auto$rtlil.cc:2693:MuxGate$24497 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names execute_arbitration_isValid $abc$27210$new_n5827 $abc$27210$new_n4259 $abc$27210$new_n5866 +110 1 +.names $abc$27210$new_n5868 CsrPlugin_interrupt_code[2] $abc$27210$new_n5869 $abc$27210$auto$rtlil.cc:2693:MuxGate$24637 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_mstatus_MIE $abc$27210$new_n5869 CsrPlugin_mip_MTIP CsrPlugin_mie_MTIE $abc$27210$new_n5868 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +.names CsrPlugin_mip_MSIP CsrPlugin_mie_MSIE CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$27210$new_n5869 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5868 CsrPlugin_interrupt_code[3] CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24641 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] CsrPlugin_mtval[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24645 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4433 CsrPlugin_mcause_interrupt CsrPlugin_hadException $abc$27210$auto$rtlil.cc:2693:MuxGate$24647 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[31] $abc$27210$new_n5881 memory_DivPlugin_div_stage_0_remainderShifted $abc$27210$auto$rtlil.cc:2693:MuxGate$24655 +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5506 $abc$27210$new_n5490 execute_RS1[30] execute_RS1[31] $abc$27210$new_n5881 +0000 1 +0010 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[9] MmuPlugin_shared_dBusRspStaged_payload_data[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24659 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_vpn_1[9] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$24661 +01 1 +10 1 +11 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_shared_vpn_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24663 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_5_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24665 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_ports_1_cache_5_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24667 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_5_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24669 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24671 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_5_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24673 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_5_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24675 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24677 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_ports_1_cache_5_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24679 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5075 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_5_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24681 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5898 MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] $abc$27210$new_n5895 MmuPlugin_shared_state_1[2] $abc$27210$new_n5894 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5897 $abc$27210$new_n5896 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_shared_dBusRspStaged_payload_data[18] $abc$27210$new_n5895 +1100 1 +.names MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_shared_dBusRspStaged_payload_data[12] $abc$27210$new_n5896 +0000 1 +.names MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_shared_dBusRspStaged_payload_data[16] $abc$27210$new_n5897 +0000 1 +.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRsp_pte_A MmuPlugin_shared_dBusRspStaged_payload_error MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRsp_pte_W $abc$27210$new_n5898 +11000 1 +11010 1 +11011 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_4_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24683 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_ports_1_cache_4_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24685 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_4_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24687 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24689 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_4_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24691 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_4_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24693 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_4_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24695 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_ports_1_cache_4_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24697 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5113 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_4_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24699 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_3_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24701 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_ports_1_cache_3_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24703 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_3_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24705 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24707 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_3_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24709 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_3_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24711 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_3_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24713 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_ports_1_cache_3_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24715 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5150 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_3_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24717 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_2_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24719 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_ports_1_cache_2_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24721 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_2_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24723 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24725 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_2_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24727 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_2_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24729 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_2_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24731 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_ports_1_cache_2_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24733 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5187 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_2_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24735 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_1_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24737 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_ports_1_cache_1_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24739 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_1_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24741 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24743 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_1_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24745 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_1_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24747 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_1_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24749 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_ports_1_cache_1_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24751 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5224 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_1_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24753 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_0_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24755 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_ports_1_cache_0_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24757 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_0_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24759 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24761 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_0_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24763 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_0_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24765 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_0_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24767 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_ports_1_cache_0_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24769 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5261 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_0_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24771 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5945 MmuPlugin_satp_ppn[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24773 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5948 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5946 $abc$27210$new_n5945 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5947 execute_CsrPlugin_csr_833 CsrPlugin_mepc[21] $abc$27210$new_n5946 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[21] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[21] $abc$27210$new_n5947 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[21] _zz__zz_execute_BranchPlugin_branch_src2_2[0] $abc$27210$new_n5948 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5950 MmuPlugin_satp_asid[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24775 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5953 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5951 $abc$27210$new_n5950 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5952 execute_CsrPlugin_csr_833 CsrPlugin_mepc[30] $abc$27210$new_n5951 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[30] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[8] $abc$27210$new_n5952 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[30] _zz__zz_execute_BranchPlugin_branch_src2_2[9] $abc$27210$new_n5953 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz__zz_3_port1[1] _zz_decode_PREDICTION_CONTEXT_line_history_2[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24777 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5956 _zz_decode_PREDICTION_CONTEXT_hazard_4 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24779 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5957 _zz_decode_PREDICTION_CONTEXT_hazard_3[8] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] _zz_decode_PREDICTION_CONTEXT_hazard_3[9] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] $abc$27210$new_n5956 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n5958 _zz_decode_PREDICTION_CONTEXT_hazard_3[6] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] _zz_decode_PREDICTION_CONTEXT_hazard_3[7] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] $abc$27210$new_n5957 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n5959 _zz_decode_PREDICTION_CONTEXT_hazard_3[4] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] _zz_decode_PREDICTION_CONTEXT_hazard_3[5] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] $abc$27210$new_n5958 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n5960 _zz_decode_PREDICTION_CONTEXT_hazard_3[1] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] _zz_decode_PREDICTION_CONTEXT_hazard_3[3] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] $abc$27210$new_n5959 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_2 $abc$27210$new_n5961 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_3[0] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] $abc$27210$new_n5960 +11100 1 +11111 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_3[2] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] $abc$27210$new_n5961 +00 1 +11 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[9] _zz_decode_PREDICTION_CONTEXT_hazard_3[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24781 +001 1 +011 1 +110 1 +111 1 +.names _zz_memory_BRANCH_CTRL[0] $abc$27210$new_n5862 execute_to_memory_PREDICTION_CONTEXT_hazard _zz_memory_BRANCH_CTRL[1] $abc$27210$new_n5964 _zz_2 +11000 1 +.names execute_to_memory_PREDICTION_CONTEXT_line_history[1] execute_to_memory_PREDICTION_CONTEXT_line_history[0] execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n5964 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_2 _zz_decode_PREDICTION_CONTEXT_hazard_2 $abc$27210$auto$rtlil.cc:2693:MuxGate$24783 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[26] DebugPlugin_disableEbreak debug_bus_cmd_payload_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24785 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4321 debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[4] debug_bus_cmd_payload_address[2] $abc$27210$new_n5967 +1000 1 +.names debug_bus_cmd_valid DebugPlugin_debugUsed $abc$27210$auto$rtlil.cc:2693:MuxGate$24787 +01 1 +10 1 +11 1 +.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[4] DebugPlugin_stepIt $abc$27210$auto$rtlil.cc:2693:MuxGate$24789 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[24] DebugPlugin_resetIt debug_bus_cmd_payload_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24791 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_refilling $abc$27210$new_n4090 $abc$27210$new_n8224 $abc$27210$auto$rtlil.cc:2693:MuxGate$24807 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_exception $abc$27210$new_n4090 $abc$27210$new_n5973 $abc$27210$new_n8224 $abc$27210$auto$rtlil.cc:2693:MuxGate$24811 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5976 $abc$27210$new_n5974 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_exception $abc$27210$new_n5973 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_exception $abc$27210$new_n5975 $abc$27210$new_n5974 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_exception MmuPlugin_ports_1_cache_5_exception $abc$27210$new_n5975 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_exception MmuPlugin_ports_1_cache_3_exception $abc$27210$new_n5976 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n5978 $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_allowWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24815 +001 1 +010 1 +011 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4090 $abc$27210$new_n4085 $abc$27210$new_n5979 MmuPlugin_ports_1_cache_4_allowWrite $abc$27210$new_n5978 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n5980 $abc$27210$new_n3943 $abc$27210$new_n4088 MmuPlugin_ports_1_cache_1_allowWrite $abc$27210$new_n5981 $abc$27210$new_n5979 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_allowWrite MmuPlugin_ports_1_cache_3_allowWrite $abc$27210$new_n5980 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_allowWrite MmuPlugin_ports_1_cache_5_allowWrite $abc$27210$new_n5981 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n5983 $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24819 +001 1 +010 1 +011 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4090 $abc$27210$new_n4085 $abc$27210$new_n8123 $abc$27210$new_n5991 $abc$27210$new_n5983 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_5_allowRead $abc$27210$new_n5989 MmuPlugin_ports_1_cache_5_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5988 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_allowRead MmuPlugin_ports_1_cache_0_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5989 +1000 1 +1001 1 +1010 1 +.names MmuPlugin_ports_1_cache_4_allowRead MmuPlugin_ports_1_cache_4_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5991 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4090 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$auto$rtlil.cc:2693:MuxGate$24821 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n5994 dBus_cmd_payload_uncached DebugPlugin_godmode dataCache_1.io_cpu_memory_isWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24825 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n3940 $abc$27210$new_n8126 $abc$27210$new_n4111 $abc$27210$new_n4106 $abc$27210$new_n5994 +1100 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] $abc$27210$new_n5998 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n8126 dBus_cmd_payload_address[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24827 +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.tagsWriteCmd_payload_data_error dataCache_1.loader_counter_willOverflow dataCache_1.loader_error dataCache_1.io_cpu_execute_refilling $abc$27210$auto$rtlil.cc:2693:MuxGate$24841 +1001 1 +1010 1 +1011 1 +.names dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] dataCache_1.loader_counter_value[2] $abc$27210$new_n6003 dataCache_1.loader_counter_willOverflow +1111 1 +.names dBus_rsp_valid dataCache_1.io_cpu_execute_refilling $abc$27210$new_n6003 +11 1 +.names dataCache_1.loader_error dBus_rsp_valid dBus_rsp_payload_error dataCache_1.tagsWriteCmd_payload_data_error +011 1 +100 1 +101 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4095 dBus_cmd_payload_size[2] dBus_cmd_ready $abc$27210$auto$rtlil.cc:2693:MuxGate$24843 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names dataCache_1.stageB_flusher_counter[6] $abc$27210$new_n6008 $abc$27210$new_n6007 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_start $abc$27210$auto$rtlil.cc:2693:MuxGate$24845 +00100 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dataCache_1.stageB_flusher_counter[5] $abc$27210$new_n4228 $abc$27210$new_n6007 +11 1 +.names execute_RS1[11] $abc$27210$new_n4233 $abc$27210$new_n6008 +11 1 +.names dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_waitDone dataCache_1.stageB_flusher_counter[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24847 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.memCmdSent dBus_cmd_ready $abc$27210$auto$rtlil.cc:2693:MuxGate$24849 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4095 $abc$27210$new_n6012 $abc$27210$new_n4100 dBus_cmd_valid +100 1 +.names dBus_cmd_payload_wr dBus_cmd_payload_uncached dataCache_1.memCmdSent dataCache_1.stageB_waysHit $abc$27210$new_n6012 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_wordIndex[2] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid IBusCachedPlugin_cache.lineLoader_wordIndex[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24851 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n6015 IBusCachedPlugin_cache.lineLoader_cmdSent iBus_cmd_ready IBusCachedPlugin_cache.lineLoader_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24853 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names IBusCachedPlugin_cache.lineLoader_wordIndex[2] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid IBusCachedPlugin_cache.lineLoader_wordIndex[1] $abc$27210$new_n6015 +1111 1 +.names IBusCachedPlugin_cache.when_InstructionCache_l351 $abc$27210$new_n5858 IBusCachedPlugin_cache.lineLoader_flushPending $abc$27210$auto$rtlil.cc:2693:MuxGate$24855 +001 1 +010 1 +011 1 +.names IBusCachedPlugin_cache.lineLoader_flushPending IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.when_InstructionCache_l351 +100 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.lineLoader_valid $abc$27210$new_n6015 $abc$27210$auto$rtlil.cc:2693:MuxGate$24857 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[31] IBusCachedPlugin_cache._zz_banks_0_port1[31] _zz_6 $abc$27210$auto$rtlil.cc:2693:MuxGate$24859 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24861 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] IBusCachedPlugin_cache.decodeStage_hit_tags_0_error $abc$27210$auto$rtlil.cc:2693:MuxGate$24863 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24865 +001 1 +011 1 +110 1 +111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] $abc$27210$new_n4960 $abc$27210$new_n4261 memory_DivPlugin_accumulator[31] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24869 +00010 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names memory_DivPlugin_div_done $abc$27210$new_n4904 memory_DivPlugin_div_counter_value[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24871 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4439 $abc$27210$new_n6027 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] $abc$27210$new_n6026 $abc$27210$new_n6029 $abc$27210$auto$rtlil.cc:2693:MuxGate$24875 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names $abc$27210$new_n4423 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 $abc$27210$new_n6026 +10010 1 +10100 1 +10101 1 +10111 1 +11001 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n6028 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] $abc$27210$new_n6027 +1010 1 +1011 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] $abc$27210$new_n4444 $abc$27210$new_n6028 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n6030 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[31] $abc$27210$new_n6029 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[31] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[31] $abc$27210$new_n6030 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] CsrPlugin_mcause_exceptionCode[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24879 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] CsrPlugin_interrupt_code[3] CsrPlugin_mcause_exceptionCode[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24881 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24883 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] iBus_cmd_payload_address[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24887 +001 1 +011 1 +110 1 +111 1 +.names lastStageIsValid $abc$27210$new_n4256 HazardSimplePlugin_writeBackWrites_payload_data[1] DebugPlugin_busReadDataReg[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24891 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n6040 MmuPlugin_dBusAccess_rsp_payload_data[1] _zz_writeBack_DBusCachedPlugin_rspShifted_3 HazardSimplePlugin_writeBackWrites_payload_data[1] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6038 MmuPlugin_dBusAccess_rsp_payload_data[17] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[1] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[25] $abc$27210$new_n5778 $abc$27210$new_n6039 $abc$27210$new_n6038 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[1] dataCache_1.stageB_dataMux[1] $abc$27210$new_n6039 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4254 _zz__zz_decode_RS2_2[1] $abc$27210$new_n6041 $abc$27210$new_n6040 +000 1 +010 1 +100 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[33] _zz_writeBack_MulPlugin_result[33] _zz_writeBack_MulPlugin_result_1[32] _zz_writeBack_MulPlugin_result[32] $abc$27210$new_n6041 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[31] HazardSimplePlugin_writeBackWrites_payload_data[31] debug_bus_rsp_data[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24893 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n6045 $abc$27210$new_n6044 _zz__zz_decode_RS2_2[31] HazardSimplePlugin_writeBackWrites_payload_data[31] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[63] _zz_writeBack_MulPlugin_result_1[62] $abc$27210$new_n5626 $abc$27210$new_n6044 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6046 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[31] $abc$27210$new_n6045 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 $abc$27210$new_n5650 _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n6046 +1000 1 +1010 1 +1011 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[31] DBusCachedPlugin_redoBranch_payload[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24897 +001 1 +011 1 +110 1 +111 1 +.names when_MmuPlugin_l281_1 $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$24899 +01 1 +10 1 +11 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] $abc$27210$new_n4102 $abc$27210$new_n5569 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$auto$rtlil.cc:2693:MuxGate$24903 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] $abc$27210$new_n4696 $abc$27210$auto$rtlil.cc:2693:MuxGate$24905 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[30] dataCache_1._zz_ways_0_data_port0[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$21679 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[29] dataCache_1._zz_ways_0_data_port0[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$21681 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[28] dataCache_1._zz_ways_0_data_port0[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$21683 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[27] dataCache_1._zz_ways_0_data_port0[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$21685 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[26] dataCache_1._zz_ways_0_data_port0[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$21687 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[25] dataCache_1._zz_ways_0_data_port0[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$21689 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[24] dataCache_1._zz_ways_0_data_port0[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$21691 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[23] dataCache_1._zz_ways_0_data_port0[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$21693 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[22] dataCache_1._zz_ways_0_data_port0[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$21695 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[21] dataCache_1._zz_ways_0_data_port0[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$21697 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[20] dataCache_1._zz_ways_0_data_port0[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$21699 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[19] dataCache_1._zz_ways_0_data_port0[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$21701 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[18] dataCache_1._zz_ways_0_data_port0[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$21703 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[17] dataCache_1._zz_ways_0_data_port0[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$21705 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[16] dataCache_1._zz_ways_0_data_port0[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$21707 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[15] dataCache_1._zz_ways_0_data_port0[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$21709 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[14] dataCache_1._zz_ways_0_data_port0[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$21711 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[13] dataCache_1._zz_ways_0_data_port0[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$21713 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[12] dataCache_1._zz_ways_0_data_port0[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$21715 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[11] dataCache_1._zz_ways_0_data_port0[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21717 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[10] dataCache_1._zz_ways_0_data_port0[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21719 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[9] dataCache_1._zz_ways_0_data_port0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21721 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[8] dataCache_1._zz_ways_0_data_port0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21723 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[7] dataCache_1._zz_ways_0_data_port0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21725 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[6] dataCache_1._zz_ways_0_data_port0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21727 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[5] dataCache_1._zz_ways_0_data_port0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21729 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[4] dataCache_1._zz_ways_0_data_port0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21731 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[3] dataCache_1._zz_ways_0_data_port0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21733 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[2] dataCache_1._zz_ways_0_data_port0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21735 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[1] dataCache_1._zz_ways_0_data_port0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21737 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[0] dataCache_1._zz_ways_0_data_port0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21739 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_mask[2] dataCache_1.stageA_mask[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21741 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_mask[1] dataCache_1.stageA_mask[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21743 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_mask[0] dataCache_1.stageA_mask[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21745 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_request_size[0] dataCache_1.stageA_request_size[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21809 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[2] $abc$27210$new_n6087 $abc$27210$auto$rtlil.cc:2693:MuxGate$21811 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6091 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n4327 switch_Misc_l241_1 $abc$27210$new_n6088 $abc$27210$new_n6087 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11010 1 +11011 1 +.names $abc$27210$new_n6089 $abc$27210$new_n4327 $abc$27210$new_n6088 +00 1 +.names $abc$27210$new_n5407 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6090 $abc$27210$new_n6089 +000 1 +101 1 +110 1 +111 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] execute_RS2[0] _zz_execute_BranchPlugin_branch_src2_8 _zz_execute_BranchPlugin_branch_src2_10 $abc$27210$new_n6090 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5402 _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6093 $abc$27210$new_n6092 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6091 +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n5407 _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6092 +010 1 +011 1 +100 1 +110 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] execute_RS2[1] _zz__zz_execute_BranchPlugin_branch_src2_2[0] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$27210$new_n6093 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[1] $abc$27210$new_n6095 $abc$27210$auto$rtlil.cc:2693:MuxGate$21813 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6089 _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n6091 $abc$27210$new_n6095 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[0] $abc$27210$new_n6097 $abc$27210$auto$rtlil.cc:2693:MuxGate$21815 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6088 $abc$27210$new_n6091 $abc$27210$new_n4327 $abc$27210$new_n6097 +001 1 +010 1 +011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_request_size[0] _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n4327 $abc$27210$auto$rtlil.cc:2693:MuxGate$21829 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6100 _zz_memory_MUL_LOW_4[51] _zz_memory_MUL_LOW_6[51] _zz_writeBack_MulPlugin_result[50] $abc$27210$auto$rtlil.cc:2693:MuxGate$21843 +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_memory_MUL_LOW_4[51] _zz_memory_MUL_LOW_6[51] $abc$27210$new_n6176 $abc$27210$new_n6177 $abc$27210$new_n6101 $abc$27210$new_n6100 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01100 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n6172 $abc$27210$new_n6173 $abc$27210$new_n6174 $abc$27210$new_n6102 $abc$27210$new_n6175 $abc$27210$new_n6101 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6168 $abc$27210$new_n6169 $abc$27210$new_n6170 $abc$27210$new_n6103 $abc$27210$new_n6171 $abc$27210$new_n6102 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6164 $abc$27210$new_n6165 $abc$27210$new_n6166 $abc$27210$new_n6104 $abc$27210$new_n6167 $abc$27210$new_n6103 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6160 $abc$27210$new_n6161 $abc$27210$new_n6162 $abc$27210$new_n6105 $abc$27210$new_n6163 $abc$27210$new_n6104 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6156 $abc$27210$new_n6157 $abc$27210$new_n6158 $abc$27210$new_n6106 $abc$27210$new_n6159 $abc$27210$new_n6105 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6152 $abc$27210$new_n6153 $abc$27210$new_n6154 $abc$27210$new_n6107 $abc$27210$new_n6155 $abc$27210$new_n6106 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6148 $abc$27210$new_n6149 $abc$27210$new_n6150 $abc$27210$new_n6108 $abc$27210$new_n6151 $abc$27210$new_n6107 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6144 $abc$27210$new_n6145 $abc$27210$new_n6146 $abc$27210$new_n6109 $abc$27210$new_n6147 $abc$27210$new_n6108 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6141 $abc$27210$new_n6143 $abc$27210$new_n6142 $abc$27210$new_n6110 $abc$27210$new_n6109 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n6139 $abc$27210$new_n6140 $abc$27210$new_n6138 $abc$27210$new_n6137 $abc$27210$new_n6111 $abc$27210$new_n6110 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6135 $abc$27210$new_n6136 $abc$27210$new_n6134 $abc$27210$new_n6133 $abc$27210$new_n6112 $abc$27210$new_n6111 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6131 $abc$27210$new_n6132 $abc$27210$new_n6130 $abc$27210$new_n6129 $abc$27210$new_n6113 $abc$27210$new_n6112 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6127 $abc$27210$new_n6128 $abc$27210$new_n6126 $abc$27210$new_n6125 $abc$27210$new_n6114 $abc$27210$new_n6113 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6124 _zz_memory_MUL_LOW_1[21] _zz_memory_MUL_LOW_4[21] _zz_memory_MUL_LOW_6[21] $abc$27210$new_n6115 $abc$27210$new_n6114 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names $abc$27210$new_n6123 _zz_memory_MUL_LOW_1[20] _zz_memory_MUL_LOW_4[20] _zz_memory_MUL_LOW_6[20] $abc$27210$new_n6116 $abc$27210$new_n6115 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names $abc$27210$new_n6122 _zz_memory_MUL_LOW_1[19] _zz_memory_MUL_LOW_4[19] _zz_memory_MUL_LOW_6[19] $abc$27210$new_n6117 $abc$27210$new_n6116 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names $abc$27210$new_n6121 _zz_memory_MUL_LOW_1[18] _zz_memory_MUL_LOW_4[18] _zz_memory_MUL_LOW_6[18] $abc$27210$new_n6118 $abc$27210$new_n6117 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names $abc$27210$new_n6119 _zz_memory_MUL_LOW_1[17] _zz_memory_MUL_LOW_4[17] _zz_memory_MUL_LOW_6[17] $abc$27210$new_n6120 $abc$27210$new_n6118 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names _zz_memory_MUL_LOW_1[18] _zz_memory_MUL_LOW_4[18] _zz_memory_MUL_LOW_6[18] $abc$27210$new_n6119 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[16] _zz_memory_MUL_LOW_4[16] _zz_memory_MUL_LOW_6[16] $abc$27210$new_n6120 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[19] _zz_memory_MUL_LOW_4[19] _zz_memory_MUL_LOW_6[19] $abc$27210$new_n6121 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[20] _zz_memory_MUL_LOW_4[20] _zz_memory_MUL_LOW_6[20] $abc$27210$new_n6122 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[21] _zz_memory_MUL_LOW_4[21] _zz_memory_MUL_LOW_6[21] $abc$27210$new_n6123 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[22] _zz_memory_MUL_LOW_4[22] _zz_memory_MUL_LOW_6[22] $abc$27210$new_n6124 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[23] _zz_memory_MUL_LOW_4[23] _zz_memory_MUL_LOW_6[23] $abc$27210$new_n6125 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[24] _zz_memory_MUL_LOW_4[24] _zz_memory_MUL_LOW_6[24] $abc$27210$new_n6126 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[22] _zz_memory_MUL_LOW_4[22] _zz_memory_MUL_LOW_6[22] $abc$27210$new_n6127 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[23] _zz_memory_MUL_LOW_4[23] _zz_memory_MUL_LOW_6[23] $abc$27210$new_n6128 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[25] _zz_memory_MUL_LOW_4[25] _zz_memory_MUL_LOW_6[25] $abc$27210$new_n6129 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[26] _zz_memory_MUL_LOW_4[26] _zz_memory_MUL_LOW_6[26] $abc$27210$new_n6130 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[24] _zz_memory_MUL_LOW_4[24] _zz_memory_MUL_LOW_6[24] $abc$27210$new_n6131 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[25] _zz_memory_MUL_LOW_4[25] _zz_memory_MUL_LOW_6[25] $abc$27210$new_n6132 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[27] _zz_memory_MUL_LOW_4[27] _zz_memory_MUL_LOW_6[27] $abc$27210$new_n6133 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[28] _zz_memory_MUL_LOW_4[28] _zz_memory_MUL_LOW_6[28] $abc$27210$new_n6134 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[26] _zz_memory_MUL_LOW_4[26] _zz_memory_MUL_LOW_6[26] $abc$27210$new_n6135 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[27] _zz_memory_MUL_LOW_4[27] _zz_memory_MUL_LOW_6[27] $abc$27210$new_n6136 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[29] _zz_memory_MUL_LOW_4[29] _zz_memory_MUL_LOW_6[29] $abc$27210$new_n6137 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[30] _zz_memory_MUL_LOW_4[30] _zz_memory_MUL_LOW_6[30] $abc$27210$new_n6138 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[28] _zz_memory_MUL_LOW_4[28] _zz_memory_MUL_LOW_6[28] $abc$27210$new_n6139 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[29] _zz_memory_MUL_LOW_4[29] _zz_memory_MUL_LOW_6[29] $abc$27210$new_n6140 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_4[32] _zz_memory_MUL_LOW_6[32] _zz_memory_MUL_LOW_1[31] _zz_memory_MUL_LOW_4[31] _zz_memory_MUL_LOW_6[31] $abc$27210$new_n6141 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_memory_MUL_LOW_1[30] _zz_memory_MUL_LOW_4[30] _zz_memory_MUL_LOW_6[30] $abc$27210$new_n6142 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[31] _zz_memory_MUL_LOW_4[31] _zz_memory_MUL_LOW_6[31] $abc$27210$new_n6143 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_4[34] _zz_memory_MUL_LOW_6[34] _zz_memory_MUL_LOW_4[33] _zz_memory_MUL_LOW_6[33] $abc$27210$new_n6144 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[33] _zz_memory_MUL_LOW_6[33] _zz_memory_MUL_LOW_4[32] _zz_memory_MUL_LOW_6[32] $abc$27210$new_n6145 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[32] _zz_memory_MUL_LOW_6[32] _zz_memory_MUL_LOW_4[33] _zz_memory_MUL_LOW_6[33] $abc$27210$new_n6146 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_1[31] _zz_memory_MUL_LOW_4[31] _zz_memory_MUL_LOW_6[31] _zz_memory_MUL_LOW_4[32] _zz_memory_MUL_LOW_6[32] $abc$27210$new_n6147 +01101 1 +01110 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names _zz_memory_MUL_LOW_4[36] _zz_memory_MUL_LOW_6[36] _zz_memory_MUL_LOW_4[35] _zz_memory_MUL_LOW_6[35] $abc$27210$new_n6148 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[35] _zz_memory_MUL_LOW_6[35] _zz_memory_MUL_LOW_4[34] _zz_memory_MUL_LOW_6[34] $abc$27210$new_n6149 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[34] _zz_memory_MUL_LOW_6[34] _zz_memory_MUL_LOW_4[35] _zz_memory_MUL_LOW_6[35] $abc$27210$new_n6150 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[33] _zz_memory_MUL_LOW_6[33] _zz_memory_MUL_LOW_4[34] _zz_memory_MUL_LOW_6[34] $abc$27210$new_n6151 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[38] _zz_memory_MUL_LOW_6[38] _zz_memory_MUL_LOW_4[37] _zz_memory_MUL_LOW_6[37] $abc$27210$new_n6152 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[37] _zz_memory_MUL_LOW_6[37] _zz_memory_MUL_LOW_4[36] _zz_memory_MUL_LOW_6[36] $abc$27210$new_n6153 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[36] _zz_memory_MUL_LOW_6[36] _zz_memory_MUL_LOW_4[37] _zz_memory_MUL_LOW_6[37] $abc$27210$new_n6154 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[35] _zz_memory_MUL_LOW_6[35] _zz_memory_MUL_LOW_4[36] _zz_memory_MUL_LOW_6[36] $abc$27210$new_n6155 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[40] _zz_memory_MUL_LOW_6[40] _zz_memory_MUL_LOW_4[39] _zz_memory_MUL_LOW_6[39] $abc$27210$new_n6156 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[39] _zz_memory_MUL_LOW_6[39] _zz_memory_MUL_LOW_4[38] _zz_memory_MUL_LOW_6[38] $abc$27210$new_n6157 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[38] _zz_memory_MUL_LOW_6[38] _zz_memory_MUL_LOW_4[39] _zz_memory_MUL_LOW_6[39] $abc$27210$new_n6158 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[37] _zz_memory_MUL_LOW_6[37] _zz_memory_MUL_LOW_4[38] _zz_memory_MUL_LOW_6[38] $abc$27210$new_n6159 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[42] _zz_memory_MUL_LOW_6[42] _zz_memory_MUL_LOW_4[41] _zz_memory_MUL_LOW_6[41] $abc$27210$new_n6160 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[41] _zz_memory_MUL_LOW_6[41] _zz_memory_MUL_LOW_4[40] _zz_memory_MUL_LOW_6[40] $abc$27210$new_n6161 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[40] _zz_memory_MUL_LOW_6[40] _zz_memory_MUL_LOW_4[41] _zz_memory_MUL_LOW_6[41] $abc$27210$new_n6162 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[39] _zz_memory_MUL_LOW_6[39] _zz_memory_MUL_LOW_4[40] _zz_memory_MUL_LOW_6[40] $abc$27210$new_n6163 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[44] _zz_memory_MUL_LOW_6[44] _zz_memory_MUL_LOW_4[43] _zz_memory_MUL_LOW_6[43] $abc$27210$new_n6164 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[43] _zz_memory_MUL_LOW_6[43] _zz_memory_MUL_LOW_4[42] _zz_memory_MUL_LOW_6[42] $abc$27210$new_n6165 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[42] _zz_memory_MUL_LOW_6[42] _zz_memory_MUL_LOW_4[43] _zz_memory_MUL_LOW_6[43] $abc$27210$new_n6166 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[41] _zz_memory_MUL_LOW_6[41] _zz_memory_MUL_LOW_4[42] _zz_memory_MUL_LOW_6[42] $abc$27210$new_n6167 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[46] _zz_memory_MUL_LOW_6[46] _zz_memory_MUL_LOW_4[45] _zz_memory_MUL_LOW_6[45] $abc$27210$new_n6168 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[45] _zz_memory_MUL_LOW_6[45] _zz_memory_MUL_LOW_4[44] _zz_memory_MUL_LOW_6[44] $abc$27210$new_n6169 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[44] _zz_memory_MUL_LOW_6[44] _zz_memory_MUL_LOW_4[45] _zz_memory_MUL_LOW_6[45] $abc$27210$new_n6170 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[43] _zz_memory_MUL_LOW_6[43] _zz_memory_MUL_LOW_4[44] _zz_memory_MUL_LOW_6[44] $abc$27210$new_n6171 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[48] _zz_memory_MUL_LOW_6[48] _zz_memory_MUL_LOW_4[47] _zz_memory_MUL_LOW_6[47] $abc$27210$new_n6172 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[47] _zz_memory_MUL_LOW_6[47] $abc$27210$new_n6173 +01 1 +10 1 +.names _zz_memory_MUL_LOW_4[46] _zz_memory_MUL_LOW_6[46] $abc$27210$new_n6174 +11 1 +.names _zz_memory_MUL_LOW_4[45] _zz_memory_MUL_LOW_6[45] _zz_memory_MUL_LOW_4[46] _zz_memory_MUL_LOW_6[46] $abc$27210$new_n6175 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[47] _zz_memory_MUL_LOW_6[47] _zz_memory_MUL_LOW_4[48] _zz_memory_MUL_LOW_6[48] $abc$27210$new_n6176 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names _zz_memory_MUL_LOW_4[51] _zz_memory_MUL_LOW_6[51] _zz_memory_MUL_LOW_4[48] _zz_memory_MUL_LOW_6[48] $abc$27210$new_n6177 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6179 $abc$27210$new_n6177 _zz_writeBack_MulPlugin_result[49] $abc$27210$auto$rtlil.cc:2693:MuxGate$21845 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_MUL_LOW_4[47] _zz_memory_MUL_LOW_6[47] _zz_memory_MUL_LOW_4[48] _zz_memory_MUL_LOW_6[48] $abc$27210$new_n6101 $abc$27210$new_n6179 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11110 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6181 _zz_writeBack_MulPlugin_result[48] $abc$27210$auto$rtlil.cc:2693:MuxGate$21847 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6172 $abc$27210$new_n6173 $abc$27210$new_n6174 $abc$27210$new_n6102 $abc$27210$new_n6175 $abc$27210$new_n6181 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6183 _zz_writeBack_MulPlugin_result[47] $abc$27210$auto$rtlil.cc:2693:MuxGate$21849 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6174 $abc$27210$new_n6173 $abc$27210$new_n6175 $abc$27210$new_n6102 $abc$27210$new_n6183 +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6185 _zz_writeBack_MulPlugin_result[46] $abc$27210$auto$rtlil.cc:2693:MuxGate$21851 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6168 $abc$27210$new_n6170 $abc$27210$new_n6169 $abc$27210$new_n6171 $abc$27210$new_n6103 $abc$27210$new_n6185 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6187 _zz_writeBack_MulPlugin_result[45] $abc$27210$auto$rtlil.cc:2693:MuxGate$21853 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6171 $abc$27210$new_n6170 $abc$27210$new_n6169 $abc$27210$new_n6103 $abc$27210$new_n6187 +0000 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6189 _zz_writeBack_MulPlugin_result[44] $abc$27210$auto$rtlil.cc:2693:MuxGate$21855 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6164 $abc$27210$new_n6166 $abc$27210$new_n6165 $abc$27210$new_n6167 $abc$27210$new_n6104 $abc$27210$new_n6189 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6191 _zz_writeBack_MulPlugin_result[43] $abc$27210$auto$rtlil.cc:2693:MuxGate$21857 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6167 $abc$27210$new_n6166 $abc$27210$new_n6165 $abc$27210$new_n6104 $abc$27210$new_n6191 +0000 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6193 _zz_writeBack_MulPlugin_result[42] $abc$27210$auto$rtlil.cc:2693:MuxGate$21859 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6160 $abc$27210$new_n6162 $abc$27210$new_n6161 $abc$27210$new_n6163 $abc$27210$new_n6105 $abc$27210$new_n6193 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6195 _zz_writeBack_MulPlugin_result[41] $abc$27210$auto$rtlil.cc:2693:MuxGate$21861 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6163 $abc$27210$new_n6162 $abc$27210$new_n6161 $abc$27210$new_n6105 $abc$27210$new_n6195 +0000 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6197 _zz_writeBack_MulPlugin_result[40] $abc$27210$auto$rtlil.cc:2693:MuxGate$21863 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6156 $abc$27210$new_n6158 $abc$27210$new_n6157 $abc$27210$new_n6159 $abc$27210$new_n6106 $abc$27210$new_n6197 +00001 1 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_zz_writeBack_MulPlugin_result[37] $abc$27210$auto$rtlil.cc:2693:MuxGate$21869 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6155 $abc$27210$new_n6154 $abc$27210$new_n6153 $abc$27210$new_n6107 $abc$27210$new_n6203 +0000 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6205 _zz_writeBack_MulPlugin_result[36] $abc$27210$auto$rtlil.cc:2693:MuxGate$21871 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6148 $abc$27210$new_n6150 $abc$27210$new_n6149 $abc$27210$new_n6151 $abc$27210$new_n6108 $abc$27210$new_n6205 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6207 _zz_writeBack_MulPlugin_result[35] $abc$27210$auto$rtlil.cc:2693:MuxGate$21873 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6151 $abc$27210$new_n6150 $abc$27210$new_n6149 $abc$27210$new_n6108 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$abc$27210$auto$rtlil.cc:2693:MuxGate$21879 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n6143 $abc$27210$new_n6142 $abc$27210$new_n6110 $abc$27210$new_n6213 +000 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6143 $abc$27210$new_n6142 $abc$27210$new_n6110 _zz__zz_decode_RS2_2[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$21881 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6216 _zz__zz_decode_RS2_2[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$21883 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6138 $abc$27210$new_n6137 $abc$27210$new_n6139 $abc$27210$new_n6140 $abc$27210$new_n6111 $abc$27210$new_n6216 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6140 $abc$27210$new_n6139 $abc$27210$new_n6111 _zz__zz_decode_RS2_2[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$21885 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[28] $abc$27210$new_n6219 $abc$27210$auto$rtlil.cc:2693:MuxGate$21887 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6134 $abc$27210$new_n6133 $abc$27210$new_n6135 $abc$27210$new_n6136 $abc$27210$new_n6112 $abc$27210$new_n6219 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6136 $abc$27210$new_n6135 $abc$27210$new_n6112 _zz__zz_decode_RS2_2[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$21889 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[26] $abc$27210$new_n6222 $abc$27210$auto$rtlil.cc:2693:MuxGate$21891 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6130 $abc$27210$new_n6129 $abc$27210$new_n6131 $abc$27210$new_n6132 $abc$27210$new_n6113 $abc$27210$new_n6222 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6132 $abc$27210$new_n6131 $abc$27210$new_n6113 _zz__zz_decode_RS2_2[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$21893 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[24] $abc$27210$new_n6225 $abc$27210$auto$rtlil.cc:2693:MuxGate$21895 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6126 $abc$27210$new_n6125 $abc$27210$new_n6127 $abc$27210$new_n6128 $abc$27210$new_n6114 $abc$27210$new_n6225 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6128 $abc$27210$new_n6127 $abc$27210$new_n6114 _zz__zz_decode_RS2_2[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$21897 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[22] $abc$27210$new_n6228 $abc$27210$auto$rtlil.cc:2693:MuxGate$21899 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6124 $abc$27210$new_n6115 _zz_memory_MUL_LOW_1[21] _zz_memory_MUL_LOW_4[21] _zz_memory_MUL_LOW_6[21] $abc$27210$new_n6228 +00000 1 +00001 1 +00010 1 +00100 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[21] $abc$27210$new_n6230 $abc$27210$auto$rtlil.cc:2693:MuxGate$21901 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6123 $abc$27210$new_n6116 _zz_memory_MUL_LOW_1[20] _zz_memory_MUL_LOW_4[20] _zz_memory_MUL_LOW_6[20] $abc$27210$new_n6230 +00000 1 +00001 1 +00010 1 +00100 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[20] $abc$27210$new_n6232 $abc$27210$auto$rtlil.cc:2693:MuxGate$21903 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6122 $abc$27210$new_n6117 _zz_memory_MUL_LOW_1[19] _zz_memory_MUL_LOW_4[19] _zz_memory_MUL_LOW_6[19] $abc$27210$new_n6232 +00000 1 +00001 1 +00010 1 +00100 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[19] $abc$27210$new_n6234 $abc$27210$auto$rtlil.cc:2693:MuxGate$21905 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6121 $abc$27210$new_n6118 _zz_memory_MUL_LOW_1[18] _zz_memory_MUL_LOW_4[18] _zz_memory_MUL_LOW_6[18] $abc$27210$new_n6234 +00000 1 +00001 1 +00010 1 +00100 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[18] $abc$27210$new_n6236 $abc$27210$auto$rtlil.cc:2693:MuxGate$21907 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6119 _zz_memory_MUL_LOW_1[17] _zz_memory_MUL_LOW_4[17] _zz_memory_MUL_LOW_6[17] $abc$27210$new_n6120 $abc$27210$new_n6236 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +11001 1 +11110 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[17] $abc$27210$new_n6238 $abc$27210$auto$rtlil.cc:2693:MuxGate$21909 +001 1 +011 1 +110 1 +111 1 +.names _zz_memory_MUL_LOW_1[17] _zz_memory_MUL_LOW_4[17] _zz_memory_MUL_LOW_6[17] $abc$27210$new_n6120 $abc$27210$new_n6238 +0000 1 +0011 1 +0101 1 +0110 1 +1001 1 +1010 1 +1100 1 +1111 1 +.names $abc$27210$new_n4093 _zz_memory_MUL_LOW_1[16] _zz_memory_MUL_LOW_4[16] _zz_memory_MUL_LOW_6[16] _zz__zz_decode_RS2_2[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$21911 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[15] _zz_memory_MUL_LOW_1[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$21913 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[14] _zz_memory_MUL_LOW_1[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$21915 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[13] _zz_memory_MUL_LOW_1[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$21917 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[12] _zz_memory_MUL_LOW_1[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$21919 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[11] _zz_memory_MUL_LOW_1[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21921 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[10] _zz_memory_MUL_LOW_1[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21923 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[9] _zz_memory_MUL_LOW_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21925 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[8] _zz_memory_MUL_LOW_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21927 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[7] _zz_memory_MUL_LOW_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21929 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[6] _zz_memory_MUL_LOW_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21931 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[5] _zz_memory_MUL_LOW_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21933 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[4] _zz_memory_MUL_LOW_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21935 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[3] _zz_memory_MUL_LOW_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21937 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[2] _zz_memory_MUL_LOW_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21939 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[1] _zz_memory_MUL_LOW_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21941 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[0] _zz_memory_MUL_LOW_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21943 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[63] execute_to_memory_MUL_HH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22005 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[62] execute_to_memory_MUL_HH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22007 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[61] execute_to_memory_MUL_HH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22009 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[60] execute_to_memory_MUL_HH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22011 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[59] execute_to_memory_MUL_HH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22013 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[58] execute_to_memory_MUL_HH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22015 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[57] execute_to_memory_MUL_HH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22017 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[56] execute_to_memory_MUL_HH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22019 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[55] execute_to_memory_MUL_HH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22021 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[54] execute_to_memory_MUL_HH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22023 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[53] execute_to_memory_MUL_HH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22025 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[52] execute_to_memory_MUL_HH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22027 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[51] execute_to_memory_MUL_HH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22029 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[50] execute_to_memory_MUL_HH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22031 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[49] execute_to_memory_MUL_HH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22033 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[48] execute_to_memory_MUL_HH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22035 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[47] execute_to_memory_MUL_HH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22037 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[46] execute_to_memory_MUL_HH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22039 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[45] execute_to_memory_MUL_HH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22041 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[44] execute_to_memory_MUL_HH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22043 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[43] execute_to_memory_MUL_HH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22045 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[42] execute_to_memory_MUL_HH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22047 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[41] execute_to_memory_MUL_HH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22049 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[40] execute_to_memory_MUL_HH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22051 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[39] execute_to_memory_MUL_HH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22053 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[38] execute_to_memory_MUL_HH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22055 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[37] execute_to_memory_MUL_HH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22057 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[36] execute_to_memory_MUL_HH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22059 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[35] execute_to_memory_MUL_HH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22061 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[34] execute_to_memory_MUL_HH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22063 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[33] execute_to_memory_MUL_HH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22065 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[32] execute_to_memory_MUL_HH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22067 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[31] execute_MUL_HH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22071 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[30] execute_MUL_HH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22073 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[29] execute_MUL_HH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22075 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[28] execute_MUL_HH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22077 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[27] execute_MUL_HH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22079 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[26] execute_MUL_HH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22081 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[25] execute_MUL_HH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22083 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[24] execute_MUL_HH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22085 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[23] execute_MUL_HH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22087 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[22] execute_MUL_HH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22089 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[21] execute_MUL_HH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22091 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[20] execute_MUL_HH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22093 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[19] execute_MUL_HH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22095 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[18] execute_MUL_HH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22097 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[17] execute_MUL_HH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22099 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[16] execute_MUL_HH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22101 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[15] execute_MUL_HH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22103 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[14] execute_MUL_HH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22105 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[13] execute_MUL_HH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22107 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[12] execute_MUL_HH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22109 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[11] execute_MUL_HH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22111 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[10] execute_MUL_HH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22113 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[9] execute_MUL_HH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22115 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[8] execute_MUL_HH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22117 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[7] execute_MUL_HH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22119 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[6] execute_MUL_HH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22121 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[5] execute_MUL_HH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22123 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[4] execute_MUL_HH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22125 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[3] execute_MUL_HH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22127 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[2] execute_MUL_HH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22129 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[1] execute_MUL_HH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22131 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[0] execute_MUL_HH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22133 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[48] execute_MUL_HL[32] $abc$27210$auto$rtlil.cc:2693:MuxGate$22135 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[47] execute_MUL_HL[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22137 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[46] execute_MUL_HL[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22139 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[45] execute_MUL_HL[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22141 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[44] execute_MUL_HL[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22143 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[43] execute_MUL_HL[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22145 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[42] execute_MUL_HL[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22147 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[41] execute_MUL_HL[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22149 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[40] execute_MUL_HL[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22151 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[39] execute_MUL_HL[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22153 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[38] execute_MUL_HL[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22155 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[37] execute_MUL_HL[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22157 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[36] execute_MUL_HL[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22159 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[35] execute_MUL_HL[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22161 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[34] execute_MUL_HL[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22163 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[33] execute_MUL_HL[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22165 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[32] execute_MUL_HL[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22167 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[31] execute_MUL_HL[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22169 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[30] execute_MUL_HL[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22171 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[29] execute_MUL_HL[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22173 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[28] execute_MUL_HL[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22175 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[27] execute_MUL_HL[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22177 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[26] execute_MUL_HL[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22179 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[25] execute_MUL_HL[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22181 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[24] execute_MUL_HL[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22183 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[23] execute_MUL_HL[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22185 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[22] execute_MUL_HL[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22187 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[21] execute_MUL_HL[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22189 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[20] execute_MUL_HL[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22191 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[19] execute_MUL_HL[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22193 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[18] execute_MUL_HL[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22195 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[17] execute_MUL_HL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22197 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[16] execute_MUL_HL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22199 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[48] execute_MUL_LH[32] $abc$27210$auto$rtlil.cc:2693:MuxGate$22201 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[47] execute_MUL_LH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22203 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[46] execute_MUL_LH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22205 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[45] execute_MUL_LH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22207 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[44] execute_MUL_LH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22209 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[43] execute_MUL_LH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22211 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[42] execute_MUL_LH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22213 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[41] execute_MUL_LH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22215 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[40] execute_MUL_LH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22217 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[39] execute_MUL_LH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22219 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[38] execute_MUL_LH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22221 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[37] execute_MUL_LH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22223 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[36] execute_MUL_LH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22225 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[35] execute_MUL_LH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22227 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[34] execute_MUL_LH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22229 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[33] execute_MUL_LH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22231 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[32] execute_MUL_LH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22233 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[31] execute_MUL_LH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22235 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[30] execute_MUL_LH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22237 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[29] execute_MUL_LH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22239 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[28] execute_MUL_LH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22241 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[27] execute_MUL_LH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22243 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[26] execute_MUL_LH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22245 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[25] execute_MUL_LH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22247 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[24] execute_MUL_LH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22249 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[23] execute_MUL_LH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22251 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[22] execute_MUL_LH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22253 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[21] execute_MUL_LH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22255 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[20] execute_MUL_LH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22257 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[19] execute_MUL_LH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22259 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[18] execute_MUL_LH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22261 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[17] execute_MUL_LH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22263 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[16] execute_MUL_LH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22265 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[30] execute_MUL_LL[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22267 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[29] execute_MUL_LL[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22269 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[28] execute_MUL_LL[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22271 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[27] execute_MUL_LL[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22273 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[26] execute_MUL_LL[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22275 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[25] execute_MUL_LL[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22277 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[24] execute_MUL_LL[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22279 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[23] execute_MUL_LL[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22281 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[22] execute_MUL_LL[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22283 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[21] execute_MUL_LL[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22285 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[20] execute_MUL_LL[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22287 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[19] execute_MUL_LL[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22289 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[18] execute_MUL_LL[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22291 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[17] execute_MUL_LL[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22293 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[16] execute_MUL_LL[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22295 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[15] execute_MUL_LL[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22297 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[14] execute_MUL_LL[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22299 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[13] execute_MUL_LL[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22301 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[12] execute_MUL_LL[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22303 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[11] execute_MUL_LL[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22305 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[10] execute_MUL_LL[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22307 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[9] execute_MUL_LL[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22309 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[8] execute_MUL_LL[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22311 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[7] execute_MUL_LL[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22313 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[6] execute_MUL_LL[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22315 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[5] execute_MUL_LL[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22317 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[4] execute_MUL_LL[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22319 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[3] execute_MUL_LL[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22321 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[2] execute_MUL_LL[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22323 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[1] execute_MUL_LL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22325 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[0] execute_MUL_LL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22327 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[1] $abc$27210$new_n6418 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22329 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6419 $abc$27210$new_n6421 $abc$27210$new_n6418 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6420 $abc$27210$new_n6421 $abc$27210$new_n6419 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6421 $abc$27210$new_n6424 $abc$27210$new_n6420 +010 1 +011 1 +100 1 +110 1 +.names _zz_execute_SHIFT_CTRL[1] _zz_execute_SHIFT_CTRL[0] $abc$27210$new_n6422 $abc$27210$new_n6421 +110 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5407 $abc$27210$new_n5843 $abc$27210$new_n6422 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$27210$new_n6423 +10 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6422 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6424 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n6426 _zz_execute_to_memory_PC[2] _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] $abc$27210$new_n6425 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] execute_RS2[2] _zz__zz_execute_BranchPlugin_branch_src2_2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$27210$new_n6426 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6428 _zz_execute_SRC2_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[2] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6427 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] execute_RS2[3] _zz__zz_execute_BranchPlugin_branch_src2_2[2] _zz_execute_to_memory_PC[3] $abc$27210$new_n6428 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n6430 _zz_execute_SRC2_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[3] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6429 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] execute_RS2[4] _zz__zz_execute_BranchPlugin_branch_src2_2[3] _zz_execute_to_memory_PC[4] $abc$27210$new_n6430 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[2] $abc$27210$new_n6432 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22331 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6433 $abc$27210$new_n6421 $abc$27210$new_n6432 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6434 $abc$27210$new_n6421 $abc$27210$new_n6433 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6435 $abc$27210$new_n6437 $abc$27210$new_n6421 $abc$27210$new_n6434 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6436 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6435 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5397 $abc$27210$new_n5412 $abc$27210$new_n6436 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6422 $abc$27210$new_n6437 +10 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[3] $abc$27210$new_n6439 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22333 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6440 $abc$27210$new_n6421 $abc$27210$new_n6439 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6441 $abc$27210$new_n6421 $abc$27210$new_n6440 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6424 $abc$27210$new_n6442 $abc$27210$new_n6441 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6436 $abc$27210$new_n6443 $abc$27210$new_n6442 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5392 $abc$27210$new_n5417 $abc$27210$new_n6443 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[4] $abc$27210$new_n6445 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22335 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6446 $abc$27210$new_n6421 $abc$27210$new_n6445 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6421 $abc$27210$new_n6447 $abc$27210$new_n6437 $abc$27210$new_n6093 $abc$27210$new_n6446 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6435 $abc$27210$new_n6448 $abc$27210$new_n6447 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6443 $abc$27210$new_n5385 $abc$27210$new_n5422 $abc$27210$new_n6448 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[5] $abc$27210$new_n6450 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22337 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6451 $abc$27210$new_n6421 $abc$27210$new_n6450 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6452 $abc$27210$new_n6420 $abc$27210$new_n6451 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6453 $abc$27210$new_n6442 $abc$27210$new_n6452 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6454 $abc$27210$new_n5385 $abc$27210$new_n5422 $abc$27210$new_n6453 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5378 $abc$27210$new_n5427 $abc$27210$new_n6454 +001 1 +011 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[6] $abc$27210$new_n6456 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22339 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6457 $abc$27210$new_n6421 $abc$27210$new_n6456 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6458 $abc$27210$new_n6434 $abc$27210$new_n6457 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6459 $abc$27210$new_n6448 $abc$27210$new_n6458 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6454 $abc$27210$new_n5373 $abc$27210$new_n5432 $abc$27210$new_n6459 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[7] $abc$27210$new_n6461 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22341 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6462 $abc$27210$new_n6421 $abc$27210$new_n6461 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6463 $abc$27210$new_n6441 $abc$27210$new_n6462 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6453 $abc$27210$new_n6464 $abc$27210$new_n6463 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6465 $abc$27210$new_n5373 $abc$27210$new_n5432 $abc$27210$new_n6464 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5370 $abc$27210$new_n5437 $abc$27210$new_n6465 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6467 DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22343 +000 1 +001 1 +011 1 +.names $abc$27210$new_n6468 $abc$27210$new_n6427 $abc$27210$new_n6429 $abc$27210$new_n6469 $abc$27210$new_n6473 $abc$27210$new_n6467 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6421 $abc$27210$new_n6429 $abc$27210$new_n6468 +000 1 +001 1 +011 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6470 $abc$27210$new_n6447 $abc$27210$new_n6469 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6459 $abc$27210$new_n6471 $abc$27210$new_n6470 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6465 $abc$27210$new_n6472 $abc$27210$new_n6471 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5362 $abc$27210$new_n5442 $abc$27210$new_n6472 +001 1 +011 1 +100 1 +101 1 +.names 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$abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6561 $abc$27210$new_n6469 $abc$27210$new_n6473 $abc$27210$new_n6560 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6425 $abc$27210$new_n6515 $abc$27210$new_n6539 $abc$27210$new_n6562 $abc$27210$new_n6561 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6551 $abc$27210$new_n6563 $abc$27210$new_n6562 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6558 $abc$27210$new_n5370 $abc$27210$new_n5437 $abc$27210$new_n6563 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[25] $abc$27210$new_n6565 $abc$27210$auto$rtlil.cc:2693:MuxGate$22377 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6566 $abc$27210$new_n6476 $abc$27210$new_n6419 $abc$27210$new_n6565 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6425 $abc$27210$new_n6521 $abc$27210$new_n6545 $abc$27210$new_n6567 $abc$27210$new_n6566 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6557 $abc$27210$new_n6568 $abc$27210$new_n6567 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6569 $abc$27210$new_n5370 $abc$27210$new_n5437 $abc$27210$new_n6568 +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5373 $abc$27210$new_n5432 $abc$27210$new_n6569 +000 1 +001 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[26] $abc$27210$new_n6571 $abc$27210$auto$rtlil.cc:2693:MuxGate$22379 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6572 $abc$27210$new_n6481 $abc$27210$new_n6433 $abc$27210$new_n6571 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6527 $abc$27210$new_n6573 $abc$27210$new_n6572 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6550 $abc$27210$new_n6563 $abc$27210$new_n6574 $abc$27210$new_n6573 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6569 $abc$27210$new_n6575 $abc$27210$new_n6574 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5378 $abc$27210$new_n5427 $abc$27210$new_n6575 +000 1 +001 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[27] $abc$27210$new_n6577 $abc$27210$auto$rtlil.cc:2693:MuxGate$22381 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6578 $abc$27210$new_n6487 $abc$27210$new_n6440 $abc$27210$new_n6577 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6579 $abc$27210$new_n6533 $abc$27210$new_n6578 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6556 $abc$27210$new_n6568 $abc$27210$new_n6580 $abc$27210$new_n6579 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6575 $abc$27210$new_n5385 $abc$27210$new_n5422 $abc$27210$new_n6580 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[28] $abc$27210$new_n6582 $abc$27210$auto$rtlil.cc:2693:MuxGate$22383 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6492 $abc$27210$new_n6538 $abc$27210$new_n6583 $abc$27210$new_n6582 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6562 $abc$27210$new_n6574 $abc$27210$new_n6584 $abc$27210$new_n6583 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6585 $abc$27210$new_n5385 $abc$27210$new_n5422 $abc$27210$new_n6584 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5392 $abc$27210$new_n5417 $abc$27210$new_n6585 +010 1 +011 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[29] $abc$27210$new_n6587 $abc$27210$auto$rtlil.cc:2693:MuxGate$22385 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6588 $abc$27210$new_n6451 $abc$27210$new_n6498 $abc$27210$new_n6587 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6544 $abc$27210$new_n6589 $abc$27210$new_n6588 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6567 $abc$27210$new_n6580 $abc$27210$new_n6590 $abc$27210$new_n6589 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6585 $abc$27210$new_n5397 $abc$27210$new_n5412 $abc$27210$new_n6590 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[30] $abc$27210$new_n6592 $abc$27210$auto$rtlil.cc:2693:MuxGate$22387 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6593 $abc$27210$new_n6457 $abc$27210$new_n6504 $abc$27210$new_n6592 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6549 $abc$27210$new_n6594 $abc$27210$new_n6593 +000 1 +001 1 +101 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6595 $abc$27210$new_n6563 $abc$27210$new_n6574 $abc$27210$new_n6594 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6584 $abc$27210$new_n6597 $abc$27210$new_n6596 $abc$27210$new_n6595 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1100 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6596 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n6090 $abc$27210$new_n5397 $abc$27210$new_n5412 $abc$27210$new_n6597 +0000 1 +0001 1 +1001 1 +1011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[31] $abc$27210$new_n6599 $abc$27210$auto$rtlil.cc:2693:MuxGate$22389 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6600 $abc$27210$new_n6462 $abc$27210$new_n6510 $abc$27210$new_n6599 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6555 $abc$27210$new_n6601 $abc$27210$new_n6600 +000 1 +001 1 +101 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6602 $abc$27210$new_n6568 $abc$27210$new_n6580 $abc$27210$new_n6601 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6590 $abc$27210$new_n6604 $abc$27210$new_n6603 $abc$27210$new_n6602 +0000 1 +0001 1 +0010 1 +0011 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n5407 $abc$27210$new_n5843 $abc$27210$new_n6603 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n6423 $abc$27210$new_n6090 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6604 +0000 1 +0001 1 +1000 1 +1010 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[30] $abc$27210$new_n6606 $abc$27210$auto$rtlil.cc:2693:MuxGate$22391 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid execute_to_memory_IS_DIV DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n6607 memory_DivPlugin_div_result[30] $abc$27210$new_n6606 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_memory_SHIFT_CTRL[1] _zz_memory_SHIFT_CTRL[0] _zz_decode_RS2_3[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] _zz_decode_RS2_3[30] $abc$27210$new_n6607 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[29] $abc$27210$new_n6609 $abc$27210$auto$rtlil.cc:2693:MuxGate$22393 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6610 memory_DivPlugin_div_result[29] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] execute_to_memory_IS_DIV $abc$27210$new_n6609 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6611 _zz_decode_RS2_3[2] $abc$27210$new_n6610 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] _zz_decode_RS2_3[29] $abc$27210$new_n6611 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[28] $abc$27210$new_n6613 $abc$27210$auto$rtlil.cc:2693:MuxGate$22395 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6614 memory_DivPlugin_div_result[28] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] execute_to_memory_IS_DIV $abc$27210$new_n6613 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6615 _zz_decode_RS2_3[3] $abc$27210$new_n6614 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] _zz_decode_RS2_3[28] $abc$27210$new_n6615 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[27] $abc$27210$new_n6617 $abc$27210$auto$rtlil.cc:2693:MuxGate$22397 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6618 memory_DivPlugin_div_result[27] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] execute_to_memory_IS_DIV $abc$27210$new_n6617 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6619 _zz_decode_RS2_3[4] $abc$27210$new_n6618 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] _zz_decode_RS2_3[27] $abc$27210$new_n6619 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[26] $abc$27210$new_n6621 $abc$27210$auto$rtlil.cc:2693:MuxGate$22399 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6622 memory_DivPlugin_div_result[26] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] execute_to_memory_IS_DIV $abc$27210$new_n6621 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6623 _zz_decode_RS2_3[5] $abc$27210$new_n6622 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] _zz_decode_RS2_3[26] $abc$27210$new_n6623 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[25] $abc$27210$new_n6625 $abc$27210$auto$rtlil.cc:2693:MuxGate$22401 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6626 memory_DivPlugin_div_result[25] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] execute_to_memory_IS_DIV $abc$27210$new_n6625 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6627 _zz_decode_RS2_3[6] $abc$27210$new_n6626 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] _zz_decode_RS2_3[25] $abc$27210$new_n6627 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[24] $abc$27210$new_n6629 $abc$27210$auto$rtlil.cc:2693:MuxGate$22403 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6630 memory_DivPlugin_div_result[24] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] execute_to_memory_IS_DIV $abc$27210$new_n6629 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6631 _zz_decode_RS2_3[7] $abc$27210$new_n6630 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] _zz_decode_RS2_3[24] $abc$27210$new_n6631 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[23] $abc$27210$new_n6633 $abc$27210$auto$rtlil.cc:2693:MuxGate$22405 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6634 memory_DivPlugin_div_result[23] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] execute_to_memory_IS_DIV $abc$27210$new_n6633 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6635 _zz_decode_RS2_3[8] $abc$27210$new_n6634 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] _zz_decode_RS2_3[23] $abc$27210$new_n6635 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[22] $abc$27210$new_n6637 $abc$27210$auto$rtlil.cc:2693:MuxGate$22407 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6638 memory_DivPlugin_div_result[22] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] execute_to_memory_IS_DIV $abc$27210$new_n6637 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6639 _zz_decode_RS2_3[9] $abc$27210$new_n6638 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] _zz_decode_RS2_3[22] $abc$27210$new_n6639 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[21] $abc$27210$new_n6641 $abc$27210$auto$rtlil.cc:2693:MuxGate$22409 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6642 memory_DivPlugin_div_result[21] execute_to_memory_IS_DIV DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n6641 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6643 _zz_decode_RS2_3[10] $abc$27210$new_n6642 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] _zz_decode_RS2_3[21] $abc$27210$new_n6643 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[20] $abc$27210$new_n6645 $abc$27210$auto$rtlil.cc:2693:MuxGate$22411 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6646 memory_DivPlugin_div_result[20] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] execute_to_memory_IS_DIV $abc$27210$new_n6645 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6647 _zz_decode_RS2_3[11] $abc$27210$new_n6646 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] _zz_decode_RS2_3[20] $abc$27210$new_n6647 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[19] $abc$27210$new_n6649 $abc$27210$auto$rtlil.cc:2693:MuxGate$22413 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6650 memory_DivPlugin_div_result[19] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] execute_to_memory_IS_DIV $abc$27210$new_n6649 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6651 _zz_decode_RS2_3[12] $abc$27210$new_n6650 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] _zz_decode_RS2_3[19] $abc$27210$new_n6651 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n6653 $abc$27210$auto$rtlil.cc:2693:MuxGate$22415 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6654 memory_DivPlugin_div_result[18] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] execute_to_memory_IS_DIV $abc$27210$new_n6653 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6655 _zz_decode_RS2_3[13] $abc$27210$new_n6654 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] _zz_decode_RS2_3[18] $abc$27210$new_n6655 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[17] $abc$27210$new_n6657 $abc$27210$auto$rtlil.cc:2693:MuxGate$22417 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6658 memory_DivPlugin_div_result[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] execute_to_memory_IS_DIV $abc$27210$new_n6657 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6659 _zz_decode_RS2_3[14] $abc$27210$new_n6658 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] _zz_decode_RS2_3[17] $abc$27210$new_n6659 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[16] $abc$27210$new_n6661 $abc$27210$auto$rtlil.cc:2693:MuxGate$22419 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6662 memory_DivPlugin_div_result[16] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] execute_to_memory_IS_DIV $abc$27210$new_n6661 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6663 _zz_decode_RS2_3[15] $abc$27210$new_n6662 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] _zz_decode_RS2_3[16] $abc$27210$new_n6663 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[15] $abc$27210$new_n6665 $abc$27210$auto$rtlil.cc:2693:MuxGate$22421 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6666 memory_DivPlugin_div_result[15] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] execute_to_memory_IS_DIV $abc$27210$new_n6665 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6667 _zz_decode_RS2_3[16] $abc$27210$new_n6666 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] _zz_decode_RS2_3[15] $abc$27210$new_n6667 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[14] $abc$27210$new_n6669 $abc$27210$auto$rtlil.cc:2693:MuxGate$22423 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6670 memory_DivPlugin_div_result[14] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] execute_to_memory_IS_DIV $abc$27210$new_n6669 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6671 _zz_decode_RS2_3[17] $abc$27210$new_n6670 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] _zz_decode_RS2_3[14] $abc$27210$new_n6671 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[13] $abc$27210$new_n6673 $abc$27210$auto$rtlil.cc:2693:MuxGate$22425 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6674 memory_DivPlugin_div_result[13] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] execute_to_memory_IS_DIV $abc$27210$new_n6673 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6675 _zz_decode_RS2_3[18] $abc$27210$new_n6674 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] _zz_decode_RS2_3[13] $abc$27210$new_n6675 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[12] $abc$27210$new_n6677 $abc$27210$auto$rtlil.cc:2693:MuxGate$22427 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6678 memory_DivPlugin_div_result[12] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] execute_to_memory_IS_DIV $abc$27210$new_n6677 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6679 _zz_decode_RS2_3[19] $abc$27210$new_n6678 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] _zz_decode_RS2_3[12] $abc$27210$new_n6679 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[11] $abc$27210$new_n6681 $abc$27210$auto$rtlil.cc:2693:MuxGate$22429 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6682 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] memory_DivPlugin_div_result[11] execute_to_memory_IS_DIV $abc$27210$new_n6681 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6683 _zz_decode_RS2_3[20] $abc$27210$new_n6682 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] _zz_decode_RS2_3[11] $abc$27210$new_n6683 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[10] $abc$27210$new_n6685 $abc$27210$auto$rtlil.cc:2693:MuxGate$22431 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6686 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] memory_DivPlugin_div_result[10] execute_to_memory_IS_DIV $abc$27210$new_n6685 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6687 _zz_decode_RS2_3[21] $abc$27210$new_n6686 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] _zz_decode_RS2_3[10] $abc$27210$new_n6687 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[9] $abc$27210$new_n6689 $abc$27210$auto$rtlil.cc:2693:MuxGate$22433 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6690 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] memory_DivPlugin_div_result[9] execute_to_memory_IS_DIV $abc$27210$new_n6689 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6691 _zz_decode_RS2_3[22] $abc$27210$new_n6690 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] _zz_decode_RS2_3[9] $abc$27210$new_n6691 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n6693 $abc$27210$auto$rtlil.cc:2693:MuxGate$22435 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6694 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] memory_DivPlugin_div_result[8] execute_to_memory_IS_DIV $abc$27210$new_n6693 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6695 _zz_decode_RS2_3[23] $abc$27210$new_n6694 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] _zz_decode_RS2_3[8] $abc$27210$new_n6695 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n6697 $abc$27210$auto$rtlil.cc:2693:MuxGate$22437 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6698 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] memory_DivPlugin_div_result[7] execute_to_memory_IS_DIV $abc$27210$new_n6697 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6699 _zz_decode_RS2_3[24] $abc$27210$new_n6698 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] _zz_decode_RS2_3[7] $abc$27210$new_n6699 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n6701 $abc$27210$auto$rtlil.cc:2693:MuxGate$22439 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6702 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] memory_DivPlugin_div_result[6] execute_to_memory_IS_DIV $abc$27210$new_n6701 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6703 _zz_decode_RS2_3[25] $abc$27210$new_n6702 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] _zz_decode_RS2_3[6] $abc$27210$new_n6703 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[5] $abc$27210$new_n6705 $abc$27210$auto$rtlil.cc:2693:MuxGate$22441 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6706 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] memory_DivPlugin_div_result[5] execute_to_memory_IS_DIV $abc$27210$new_n6705 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6707 _zz_decode_RS2_3[26] $abc$27210$new_n6706 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] _zz_decode_RS2_3[5] $abc$27210$new_n6707 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[4] $abc$27210$new_n6709 $abc$27210$auto$rtlil.cc:2693:MuxGate$22443 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6710 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] memory_DivPlugin_div_result[4] execute_to_memory_IS_DIV $abc$27210$new_n6709 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6711 _zz_decode_RS2_3[27] $abc$27210$new_n6710 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] _zz_decode_RS2_3[4] $abc$27210$new_n6711 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n6713 $abc$27210$auto$rtlil.cc:2693:MuxGate$22445 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6714 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] memory_DivPlugin_div_result[3] execute_to_memory_IS_DIV $abc$27210$new_n6713 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6715 _zz_decode_RS2_3[28] $abc$27210$new_n6714 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] _zz_decode_RS2_3[3] $abc$27210$new_n6715 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[2] $abc$27210$new_n6717 $abc$27210$auto$rtlil.cc:2693:MuxGate$22447 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6718 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] memory_DivPlugin_div_result[2] execute_to_memory_IS_DIV $abc$27210$new_n6717 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6719 _zz_decode_RS2_3[29] $abc$27210$new_n6718 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] _zz_decode_RS2_3[2] $abc$27210$new_n6719 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n6721 $abc$27210$auto$rtlil.cc:2693:MuxGate$22449 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6722 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] memory_DivPlugin_div_result[1] execute_to_memory_IS_DIV $abc$27210$new_n6721 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6723 _zz_decode_RS2_3[30] $abc$27210$new_n6722 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] _zz_decode_RS2_3[1] $abc$27210$new_n6723 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[0] $abc$27210$new_n6725 $abc$27210$auto$rtlil.cc:2693:MuxGate$22451 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6726 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] memory_DivPlugin_div_result[0] execute_to_memory_IS_DIV $abc$27210$new_n6725 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6727 _zz_decode_RS2_3[31] $abc$27210$new_n6726 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] _zz_decode_RS2_3[0] $abc$27210$new_n6727 +010 1 +011 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8130 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22453 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n5417 $abc$27210$new_n6799 $abc$27210$new_n5412 $abc$27210$new_n6797 $abc$27210$new_n6733 $abc$27210$new_n6732 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5427 $abc$27210$new_n6795 $abc$27210$new_n5422 $abc$27210$new_n6793 $abc$27210$new_n6734 $abc$27210$new_n6733 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5437 $abc$27210$new_n6791 $abc$27210$new_n5432 $abc$27210$new_n6789 $abc$27210$new_n6735 $abc$27210$new_n6734 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5447 $abc$27210$new_n6787 $abc$27210$new_n5442 $abc$27210$new_n6785 $abc$27210$new_n6736 $abc$27210$new_n6735 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5302 $abc$27210$new_n6783 $abc$27210$new_n5948 $abc$27210$new_n6781 $abc$27210$new_n6737 $abc$27210$new_n6736 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5312 $abc$27210$new_n6779 $abc$27210$new_n5307 $abc$27210$new_n6777 $abc$27210$new_n6738 $abc$27210$new_n6737 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5317 $abc$27210$new_n5322 $abc$27210$new_n6775 $abc$27210$new_n6773 $abc$27210$new_n6739 $abc$27210$new_n6738 +00000 1 +00001 1 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n5327 $abc$27210$new_n6768 $abc$27210$new_n6772 $abc$27210$new_n6740 $abc$27210$new_n6770 $abc$27210$new_n6739 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n5342 $abc$27210$new_n6766 $abc$27210$new_n5337 $abc$27210$new_n6764 $abc$27210$new_n6741 $abc$27210$new_n6740 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6762 $abc$27210$new_n6760 $abc$27210$new_n5352 $abc$27210$new_n5348 $abc$27210$new_n6742 $abc$27210$new_n6741 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n5362 $abc$27210$new_n6758 $abc$27210$new_n6756 $abc$27210$new_n5357 $abc$27210$new_n6743 $abc$27210$new_n6742 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names $abc$27210$new_n6752 $abc$27210$new_n6754 $abc$27210$new_n5373 $abc$27210$new_n5370 $abc$27210$new_n6744 $abc$27210$new_n6743 +00000 1 +00001 1 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n5385 $abc$27210$new_n6746 $abc$27210$new_n6750 $abc$27210$new_n5378 $abc$27210$new_n6745 $abc$27210$new_n6744 +00100 1 +00101 1 +01001 1 +01100 1 +01101 1 +01111 1 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6429 $abc$27210$new_n6745 +01 1 +10 1 +.names $abc$27210$new_n5392 $abc$27210$new_n6749 $abc$27210$new_n5397 $abc$27210$new_n6748 $abc$27210$new_n6747 $abc$27210$new_n6746 +00011 1 +01001 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6428 _zz_execute_SRC2_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[2] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6747 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6426 _zz_execute_SRC2_CTRL[1] _zz_execute_to_memory_PC[2] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6748 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6093 $abc$27210$new_n6090 $abc$27210$new_n5402 $abc$27210$new_n5407 $abc$27210$new_n6749 +00011 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6751 $abc$27210$new_n6750 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[4] execute_RS2[5] _zz_execute_to_memory_PC[5] $abc$27210$new_n6751 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6753 $abc$27210$new_n6752 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[6] execute_RS2[7] _zz_execute_to_memory_PC[7] $abc$27210$new_n6753 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6755 $abc$27210$new_n6754 +00 1 +11 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[5] execute_RS2[6] _zz_execute_to_memory_PC[6] $abc$27210$new_n6755 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6757 $abc$27210$new_n6756 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[8] execute_RS2[9] _zz_execute_to_memory_PC[9] $abc$27210$new_n6757 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6759 $abc$27210$new_n6758 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[7] execute_RS2[8] _zz_execute_to_memory_PC[8] $abc$27210$new_n6759 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6761 $abc$27210$new_n6760 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[11] _zz_execute_to_memory_PC[11] $abc$27210$new_n6761 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6763 $abc$27210$new_n6762 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[9] execute_RS2[10] _zz_execute_to_memory_PC[10] $abc$27210$new_n6763 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6765 $abc$27210$new_n6764 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[13] _zz_execute_to_memory_PC[13] $abc$27210$new_n6765 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6767 $abc$27210$new_n6766 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[12] _zz_execute_to_memory_PC[12] $abc$27210$new_n6767 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6769 $abc$27210$new_n6768 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[15] _zz_execute_to_memory_PC[15] $abc$27210$new_n6769 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6771 $abc$27210$new_n5332 $abc$27210$new_n6770 +000 1 +110 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[14] _zz_execute_to_memory_PC[14] $abc$27210$new_n6771 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6771 $abc$27210$new_n5332 $abc$27210$new_n6772 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6774 $abc$27210$new_n6773 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[17] _zz_execute_to_memory_PC[17] $abc$27210$new_n6774 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6776 $abc$27210$new_n6775 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[16] _zz_execute_to_memory_PC[16] $abc$27210$new_n6776 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6778 $abc$27210$new_n6777 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[19] _zz_execute_to_memory_PC[19] $abc$27210$new_n6778 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6780 $abc$27210$new_n6779 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[18] _zz_execute_to_memory_PC[18] $abc$27210$new_n6780 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6782 $abc$27210$new_n6781 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[21] _zz_execute_to_memory_PC[21] $abc$27210$new_n6782 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6784 $abc$27210$new_n6783 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[20] _zz_execute_to_memory_PC[20] $abc$27210$new_n6784 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6786 $abc$27210$new_n6785 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[23] _zz_execute_to_memory_PC[23] $abc$27210$new_n6786 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6788 $abc$27210$new_n6787 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[22] _zz_execute_to_memory_PC[22] $abc$27210$new_n6788 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6790 $abc$27210$new_n6789 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[25] _zz_execute_to_memory_PC[25] $abc$27210$new_n6790 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6792 $abc$27210$new_n6791 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[24] _zz_execute_to_memory_PC[24] $abc$27210$new_n6792 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6794 $abc$27210$new_n6793 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[27] _zz_execute_to_memory_PC[27] $abc$27210$new_n6794 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6796 $abc$27210$new_n6795 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[26] _zz_execute_to_memory_PC[26] $abc$27210$new_n6796 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6798 $abc$27210$new_n6797 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[29] _zz_execute_to_memory_PC[29] $abc$27210$new_n6798 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6800 $abc$27210$new_n6799 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[28] _zz_execute_to_memory_PC[28] $abc$27210$new_n6800 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[30] _zz_execute_to_memory_PC[30] $abc$27210$new_n6802 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$27210$new_n6803 +10 1 +.names $abc$27210$new_n4264 _zz_execute_ALU_CTRL[0] _zz_execute_ALU_CTRL[1] $abc$27210$new_n6805 +000 1 +001 1 +011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[8] MmuPlugin_satp_ppn[18] $abc$27210$new_n6806 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8133 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22455 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n5417 $abc$27210$new_n6799 $abc$27210$new_n6733 $abc$27210$new_n6812 +010 1 +100 1 +110 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6798 $abc$27210$new_n5412 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6813 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8136 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22457 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6800 $abc$27210$new_n5417 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6819 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6821 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22459 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6825 $abc$27210$new_n6826 $abc$27210$new_n6805 $abc$27210$new_n6822 $abc$27210$new_n6821 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6824 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6823 $abc$27210$new_n5422 $abc$27210$new_n6822 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5422 $abc$27210$new_n6793 $abc$27210$new_n5427 $abc$27210$new_n6795 $abc$27210$new_n6734 $abc$27210$new_n6823 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6794 $abc$27210$new_n5422 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6824 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n4264 $abc$27210$new_n5420 $abc$27210$new_n6825 +10 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[5] MmuPlugin_satp_ppn[15] $abc$27210$new_n6826 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8139 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22461 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4264 $abc$27210$new_n5425 $abc$27210$new_n6832 +10 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[4] MmuPlugin_satp_ppn[14] $abc$27210$new_n6833 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6835 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22463 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6836 $abc$27210$new_n6840 $abc$27210$new_n4264 $abc$27210$new_n5430 $abc$27210$new_n6835 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6837 $abc$27210$new_n6839 $abc$27210$new_n6836 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5432 $abc$27210$new_n6803 $abc$27210$new_n6789 $abc$27210$new_n6838 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6837 +00000 1 +00001 1 +00011 1 +00101 1 +00110 1 +00111 1 +10010 1 +10100 1 +.names $abc$27210$new_n5437 $abc$27210$new_n6791 $abc$27210$new_n6735 $abc$27210$new_n6838 +010 1 +100 1 +110 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6790 $abc$27210$new_n5432 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6839 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[3] MmuPlugin_satp_ppn[13] $abc$27210$new_n6840 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6842 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22465 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6843 $abc$27210$new_n6846 $abc$27210$new_n4264 $abc$27210$new_n5435 $abc$27210$new_n6842 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6844 $abc$27210$new_n6845 $abc$27210$new_n5437 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6843 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n5437 $abc$27210$new_n6791 $abc$27210$new_n6735 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6844 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6792 $abc$27210$new_n5437 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6845 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[2] MmuPlugin_satp_ppn[12] $abc$27210$new_n6846 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6848 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22467 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6849 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN1[1] MmuPlugin_satp_ppn[11] $abc$27210$new_n6848 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6850 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5440 $abc$27210$new_n6849 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6852 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6851 $abc$27210$new_n5442 $abc$27210$new_n6850 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5442 $abc$27210$new_n6785 $abc$27210$new_n5447 $abc$27210$new_n6787 $abc$27210$new_n6736 $abc$27210$new_n6851 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6786 $abc$27210$new_n5442 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6852 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6854 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22469 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n8142 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN1[0] MmuPlugin_satp_ppn[10] $abc$27210$new_n6854 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6860 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22471 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6861 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[9] MmuPlugin_satp_ppn[9] $abc$27210$new_n6860 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6862 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5946 $abc$27210$new_n6861 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6864 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6863 $abc$27210$new_n5948 $abc$27210$new_n6862 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5948 $abc$27210$new_n6781 $abc$27210$new_n5302 $abc$27210$new_n6783 $abc$27210$new_n6737 $abc$27210$new_n6863 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6782 $abc$27210$new_n5948 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6864 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6866 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22473 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6867 $abc$27210$new_n6870 $abc$27210$new_n4264 $abc$27210$new_n5300 $abc$27210$new_n6866 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6869 $abc$27210$new_n6803 $abc$27210$new_n6868 $abc$27210$new_n6867 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5302 $abc$27210$new_n6783 $abc$27210$new_n6737 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6868 +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6784 $abc$27210$new_n5302 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6869 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN0[8] MmuPlugin_satp_ppn[8] $abc$27210$new_n6870 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6872 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22475 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6873 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[7] MmuPlugin_satp_ppn[7] $abc$27210$new_n6872 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6874 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5305 $abc$27210$new_n6873 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6876 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6875 $abc$27210$new_n5307 $abc$27210$new_n6874 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5307 $abc$27210$new_n6777 $abc$27210$new_n5312 $abc$27210$new_n6779 $abc$27210$new_n6738 $abc$27210$new_n6875 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6778 $abc$27210$new_n5307 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6876 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6878 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22477 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6879 $abc$27210$new_n6882 $abc$27210$new_n4264 $abc$27210$new_n5310 $abc$27210$new_n6878 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6880 $abc$27210$new_n6881 $abc$27210$new_n6879 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5312 $abc$27210$new_n6803 $abc$27210$new_n6779 $abc$27210$new_n6738 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6880 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10110 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6780 $abc$27210$new_n5312 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6881 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN0[6] MmuPlugin_satp_ppn[6] $abc$27210$new_n6882 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6884 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22479 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6885 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[5] MmuPlugin_satp_ppn[5] $abc$27210$new_n6884 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6886 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5315 $abc$27210$new_n6885 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6888 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6887 $abc$27210$new_n5317 $abc$27210$new_n6886 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5317 $abc$27210$new_n6773 $abc$27210$new_n5322 $abc$27210$new_n6775 $abc$27210$new_n6739 $abc$27210$new_n6887 +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6774 $abc$27210$new_n5317 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6888 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +11100 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8145 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22481 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6776 $abc$27210$new_n5322 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6894 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6896 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22483 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6897 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[3] MmuPlugin_satp_ppn[3] $abc$27210$new_n6896 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6898 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5325 $abc$27210$new_n6897 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6900 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6899 $abc$27210$new_n5327 $abc$27210$new_n6898 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5327 $abc$27210$new_n6768 $abc$27210$new_n6770 $abc$27210$new_n6772 $abc$27210$new_n6740 $abc$27210$new_n6899 +00000 1 +00001 1 +00011 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6769 $abc$27210$new_n5327 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6900 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8149 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22485 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN0[2] MmuPlugin_satp_ppn[2] $abc$27210$new_n6907 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6909 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22487 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6910 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[1] MmuPlugin_satp_ppn[1] $abc$27210$new_n6909 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6911 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5335 $abc$27210$new_n6910 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6913 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6912 $abc$27210$new_n5337 $abc$27210$new_n6911 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5337 $abc$27210$new_n6764 $abc$27210$new_n5342 $abc$27210$new_n6766 $abc$27210$new_n6741 $abc$27210$new_n6912 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6765 $abc$27210$new_n5337 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6913 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n6915 $abc$27210$auto$rtlil.cc:2693:MuxGate$22489 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6916 $abc$27210$new_n6919 $abc$27210$new_n4264 $abc$27210$new_n5340 $abc$27210$new_n6915 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6918 $abc$27210$new_n6803 $abc$27210$new_n6917 $abc$27210$new_n6916 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5342 $abc$27210$new_n6766 $abc$27210$new_n6741 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6917 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6767 $abc$27210$new_n5342 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6918 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN0[0] MmuPlugin_satp_ppn[0] $abc$27210$new_n6919 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] $abc$27210$new_n6921 $abc$27210$auto$rtlil.cc:2693:MuxGate$22491 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6922 $abc$27210$new_n6926 $abc$27210$new_n5345 $abc$27210$new_n4264 $abc$27210$new_n6921 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6925 $abc$27210$new_n6923 $abc$27210$new_n6803 $abc$27210$new_n6922 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n5348 $abc$27210$new_n6760 $abc$27210$new_n6924 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6923 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6762 $abc$27210$new_n5352 $abc$27210$new_n6742 $abc$27210$new_n6924 +000 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n6803 $abc$27210$new_n5348 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6761 $abc$27210$new_n6925 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11101 1 +11110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[9] MmuPlugin_shared_vpn_1[9] $abc$27210$new_n6926 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] $abc$27210$new_n8152 $abc$27210$auto$rtlil.cc:2693:MuxGate$22493 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6762 $abc$27210$new_n5352 $abc$27210$new_n6742 $abc$27210$new_n6931 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[8] MmuPlugin_shared_vpn_1[8] $abc$27210$new_n6933 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] $abc$27210$new_n6935 $abc$27210$auto$rtlil.cc:2693:MuxGate$22495 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6936 $abc$27210$new_n6940 $abc$27210$new_n5358 $abc$27210$new_n4264 $abc$27210$new_n6935 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6937 $abc$27210$new_n6939 $abc$27210$new_n6936 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$27210$new_n5357 $abc$27210$new_n6756 $abc$27210$new_n6938 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6937 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names $abc$27210$new_n6758 $abc$27210$new_n5362 $abc$27210$new_n6743 $abc$27210$new_n6938 +001 1 +100 1 +101 1 +111 1 +.names $abc$27210$new_n5357 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6757 $abc$27210$new_n6939 +0000 1 +0010 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[7] MmuPlugin_shared_vpn_1[7] $abc$27210$new_n6940 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] $abc$27210$new_n8155 $abc$27210$auto$rtlil.cc:2693:MuxGate$22497 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6758 $abc$27210$new_n5362 $abc$27210$new_n6743 $abc$27210$new_n6945 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[6] MmuPlugin_shared_vpn_1[6] $abc$27210$new_n6947 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] $abc$27210$new_n6949 $abc$27210$auto$rtlil.cc:2693:MuxGate$22499 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6950 $abc$27210$new_n6954 $abc$27210$new_n5367 $abc$27210$new_n4264 $abc$27210$new_n6949 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6951 $abc$27210$new_n6953 $abc$27210$new_n6950 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n5370 $abc$27210$new_n6752 $abc$27210$new_n6952 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6951 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6754 $abc$27210$new_n5373 $abc$27210$new_n6744 $abc$27210$new_n6952 +000 1 +001 1 +011 1 +101 1 +.names $abc$27210$new_n5370 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6753 $abc$27210$new_n6953 +0000 1 +0010 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[5] MmuPlugin_shared_vpn_1[5] $abc$27210$new_n6954 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] $abc$27210$new_n8158 $abc$27210$auto$rtlil.cc:2693:MuxGate$22501 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6754 $abc$27210$new_n5373 $abc$27210$new_n6744 $abc$27210$new_n6959 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[4] MmuPlugin_shared_vpn_1[4] $abc$27210$new_n6961 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] $abc$27210$new_n6963 $abc$27210$auto$rtlil.cc:2693:MuxGate$22503 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6964 $abc$27210$new_n6968 $abc$27210$new_n5379 $abc$27210$new_n4264 $abc$27210$new_n6963 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6967 $abc$27210$new_n6965 $abc$27210$new_n6803 $abc$27210$new_n6964 +1000 1 +1001 1 +1011 1 +.names $abc$27210$new_n5378 $abc$27210$new_n6750 $abc$27210$new_n6966 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6965 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names $abc$27210$new_n5385 $abc$27210$new_n6746 $abc$27210$new_n6745 $abc$27210$new_n6966 +011 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n5378 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6751 $abc$27210$new_n6967 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11101 1 +11110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[3] MmuPlugin_shared_vpn_1[3] $abc$27210$new_n6968 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] $abc$27210$new_n8161 $abc$27210$auto$rtlil.cc:2693:MuxGate$22505 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n5385 $abc$27210$new_n6746 $abc$27210$new_n6745 $abc$27210$new_n6973 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[2] MmuPlugin_shared_vpn_1[2] $abc$27210$new_n6975 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] $abc$27210$new_n6977 $abc$27210$auto$rtlil.cc:2693:MuxGate$22507 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6978 $abc$27210$new_n6982 $abc$27210$new_n5388 $abc$27210$new_n4264 $abc$27210$new_n6977 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6979 $abc$27210$new_n6981 $abc$27210$new_n6978 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$27210$new_n5392 $abc$27210$new_n6747 $abc$27210$new_n6980 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6979 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6749 $abc$27210$new_n5397 $abc$27210$new_n6748 $abc$27210$new_n6980 +001 1 +100 1 +101 1 +111 1 +.names _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n5392 $abc$27210$new_n6427 $abc$27210$new_n6981 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1101 1 +1110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[1] MmuPlugin_shared_vpn_1[1] $abc$27210$new_n6982 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] $abc$27210$new_n6984 $abc$27210$auto$rtlil.cc:2693:MuxGate$22509 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6985 $abc$27210$new_n6988 $abc$27210$new_n5395 $abc$27210$new_n4264 $abc$27210$new_n6984 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6986 $abc$27210$new_n6987 $abc$27210$new_n6985 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n5397 $abc$27210$new_n6749 $abc$27210$new_n6748 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6986 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names $abc$27210$new_n5397 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6425 $abc$27210$new_n6987 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1101 1 +1110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[0] MmuPlugin_shared_vpn_1[0] $abc$27210$new_n6988 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] $abc$27210$new_n6990 $abc$27210$auto$rtlil.cc:2693:MuxGate$22511 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6991 $abc$27210$new_n4264 $abc$27210$new_n5400 $abc$27210$new_n6990 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6091 $abc$27210$new_n6992 $abc$27210$new_n6991 +1000 1 +1001 1 +1100 1 +1110 1 +.names _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6093 $abc$27210$new_n5402 $abc$27210$new_n6992 +0000 1 +0011 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8163 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22513 +010 1 +011 1 +101 1 +111 1 +.names decode_to_execute_SRC_LESS_UNSIGNED $abc$27210$new_n6999 $abc$27210$new_n5843 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6997 $abc$27210$new_n6996 +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +01111 1 +10000 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6998 $abc$27210$new_n5953 $abc$27210$new_n6802 $abc$27210$new_n6732 $abc$27210$new_n6997 +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6999 $abc$27210$new_n5843 $abc$27210$new_n6998 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz_execute_to_memory_PC[31] execute_RS2[31] $abc$27210$new_n6999 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6090 $abc$27210$new_n5407 $abc$27210$new_n7001 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1101 1 +1110 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[30] execute_to_memory_MEMORY_STORE_DATA_RF[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22515 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[29] execute_to_memory_MEMORY_STORE_DATA_RF[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22517 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[28] execute_to_memory_MEMORY_STORE_DATA_RF[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22519 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[27] execute_to_memory_MEMORY_STORE_DATA_RF[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22521 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[26] execute_to_memory_MEMORY_STORE_DATA_RF[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22523 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[25] execute_to_memory_MEMORY_STORE_DATA_RF[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22525 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[24] execute_to_memory_MEMORY_STORE_DATA_RF[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22527 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[23] execute_to_memory_MEMORY_STORE_DATA_RF[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22529 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[22] execute_to_memory_MEMORY_STORE_DATA_RF[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22531 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[21] execute_to_memory_MEMORY_STORE_DATA_RF[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22533 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[20] execute_to_memory_MEMORY_STORE_DATA_RF[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22535 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[19] execute_to_memory_MEMORY_STORE_DATA_RF[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22537 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[18] execute_to_memory_MEMORY_STORE_DATA_RF[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22539 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[17] execute_to_memory_MEMORY_STORE_DATA_RF[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22541 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[16] execute_to_memory_MEMORY_STORE_DATA_RF[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22543 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[15] execute_to_memory_MEMORY_STORE_DATA_RF[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22545 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[14] execute_to_memory_MEMORY_STORE_DATA_RF[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22547 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[13] execute_to_memory_MEMORY_STORE_DATA_RF[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22549 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[12] execute_to_memory_MEMORY_STORE_DATA_RF[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22551 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[11] execute_to_memory_MEMORY_STORE_DATA_RF[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22553 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[10] execute_to_memory_MEMORY_STORE_DATA_RF[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22555 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[9] execute_to_memory_MEMORY_STORE_DATA_RF[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22557 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[8] execute_to_memory_MEMORY_STORE_DATA_RF[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22559 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[7] execute_to_memory_MEMORY_STORE_DATA_RF[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22561 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[6] execute_to_memory_MEMORY_STORE_DATA_RF[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22563 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[5] execute_to_memory_MEMORY_STORE_DATA_RF[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22565 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[4] execute_to_memory_MEMORY_STORE_DATA_RF[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22567 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[3] execute_to_memory_MEMORY_STORE_DATA_RF[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22569 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[2] execute_to_memory_MEMORY_STORE_DATA_RF[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22571 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[1] execute_to_memory_MEMORY_STORE_DATA_RF[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22573 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[0] execute_to_memory_MEMORY_STORE_DATA_RF[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22575 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[30] $abc$27210$new_n7034 $abc$27210$auto$rtlil.cc:2693:MuxGate$22577 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[30] execute_RS2[6] execute_RS2[14] $abc$27210$new_n7034 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[29] $abc$27210$new_n7036 $abc$27210$auto$rtlil.cc:2693:MuxGate$22579 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[29] execute_RS2[5] execute_RS2[13] $abc$27210$new_n7036 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[28] $abc$27210$new_n7038 $abc$27210$auto$rtlil.cc:2693:MuxGate$22581 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[28] execute_RS2[4] execute_RS2[12] $abc$27210$new_n7038 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[27] $abc$27210$new_n7040 $abc$27210$auto$rtlil.cc:2693:MuxGate$22583 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[27] execute_RS2[3] execute_RS2[11] $abc$27210$new_n7040 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[26] $abc$27210$new_n7042 $abc$27210$auto$rtlil.cc:2693:MuxGate$22585 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[26] execute_RS2[2] execute_RS2[10] $abc$27210$new_n7042 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[25] $abc$27210$new_n7044 $abc$27210$auto$rtlil.cc:2693:MuxGate$22587 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[25] execute_RS2[1] execute_RS2[9] $abc$27210$new_n7044 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[24] $abc$27210$new_n7046 $abc$27210$auto$rtlil.cc:2693:MuxGate$22589 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[24] execute_RS2[0] execute_RS2[8] $abc$27210$new_n7046 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[23] execute_RS2[7] execute_RS2[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22591 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[22] execute_RS2[6] execute_RS2[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22593 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[21] execute_RS2[5] execute_RS2[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22595 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[20] execute_RS2[4] execute_RS2[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22597 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[19] execute_RS2[3] execute_RS2[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22599 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[18] execute_RS2[2] execute_RS2[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22601 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[17] execute_RS2[1] execute_RS2[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22603 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[16] execute_RS2[0] execute_RS2[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22605 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[15] execute_RS2[7] execute_RS2[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22607 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n7056 +00 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[14] execute_RS2[6] execute_RS2[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22609 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[13] execute_RS2[5] execute_RS2[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22611 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[12] execute_RS2[4] execute_RS2[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22613 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[11] execute_RS2[3] execute_RS2[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22615 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[10] execute_RS2[2] execute_RS2[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22617 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[9] execute_RS2[1] execute_RS2[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22619 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[8] execute_RS2[0] execute_RS2[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22621 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[7] execute_RS2[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22623 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[6] execute_RS2[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22625 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[5] execute_RS2[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22627 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[4] execute_RS2[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22629 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[3] execute_RS2[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22631 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[2] execute_RS2[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22633 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[1] execute_RS2[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22635 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[0] execute_RS2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22637 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[30] $abc$27210$new_n7073 $abc$27210$new_n8130 $abc$27210$auto$rtlil.cc:2693:MuxGate$22639 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6606 HazardSimplePlugin_writeBackWrites_payload_data[30] $abc$27210$new_n7075 $abc$27210$new_n7073 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_to_memory_REGFILE_WRITE_VALID execute_to_memory_BYPASSABLE_MEMORY_STAGE memory_arbitration_isValid $abc$27210$new_n8023 $abc$27210$new_n7074 +1111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[30] _zz_RegFilePlugin_regFile_port1[30] $abc$27210$new_n7075 +000 1 +010 1 +100 1 +101 1 +.names HazardSimplePlugin_writeBackBuffer_valid IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] HazardSimplePlugin_writeBackBuffer_payload_address[0] HazardSimplePlugin_writeBackBuffer_payload_address[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n7080 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names _zz_lastStageRegFileWrite_valid lastStageIsValid $abc$27210$new_n7086 +11 1 +.names decode_to_execute_REGFILE_WRITE_VALID decode_to_execute_BYPASSABLE_EXECUTE_STAGE execute_arbitration_isValid $abc$27210$new_n4310 $abc$27210$new_n7087 +1111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[29] $abc$27210$new_n8133 $abc$27210$new_n7089 $abc$27210$auto$rtlil.cc:2693:MuxGate$22641 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6609 HazardSimplePlugin_writeBackWrites_payload_data[29] $abc$27210$new_n7090 $abc$27210$new_n7089 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[29] _zz_RegFilePlugin_regFile_port1[29] $abc$27210$new_n7090 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[28] $abc$27210$new_n8136 $abc$27210$new_n7092 $abc$27210$auto$rtlil.cc:2693:MuxGate$22643 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6613 HazardSimplePlugin_writeBackWrites_payload_data[28] $abc$27210$new_n7093 $abc$27210$new_n7092 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 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$abc$27210$new_n7096 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[26] $abc$27210$new_n8139 $abc$27210$new_n7098 $abc$27210$auto$rtlil.cc:2693:MuxGate$22647 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6621 HazardSimplePlugin_writeBackWrites_payload_data[26] $abc$27210$new_n7099 $abc$27210$new_n7098 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[26] _zz_RegFilePlugin_regFile_port1[26] $abc$27210$new_n7099 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[25] $abc$27210$new_n6835 $abc$27210$new_n7101 $abc$27210$auto$rtlil.cc:2693:MuxGate$22649 +00100 1 +00101 1 +00110 1 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$abc$27210$new_n4259 $abc$27210$new_n7269 execute_RS1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22755 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n7189 $abc$27210$new_n7185 $abc$27210$new_n6977 $abc$27210$new_n7270 $abc$27210$new_n6713 $abc$27210$new_n7269 +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7186 $abc$27210$new_n7181 HazardSimplePlugin_writeBackWrites_payload_data[3] HazardSimplePlugin_writeBackBuffer_payload_data[3] _zz_RegFilePlugin_regFile_port0[3] $abc$27210$new_n7270 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[2] $abc$27210$new_n7272 $abc$27210$new_n6984 $abc$27210$auto$rtlil.cc:2693:MuxGate$22757 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7273 $abc$27210$new_n6717 $abc$27210$new_n7272 +010 1 +011 1 +100 1 +110 1 +.names $abc$27210$new_n7186 $abc$27210$new_n7181 HazardSimplePlugin_writeBackWrites_payload_data[2] HazardSimplePlugin_writeBackBuffer_payload_data[2] _zz_RegFilePlugin_regFile_port0[2] $abc$27210$new_n7273 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[1] $abc$27210$new_n6990 $abc$27210$new_n7275 $abc$27210$auto$rtlil.cc:2693:MuxGate$22759 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n6721 HazardSimplePlugin_writeBackWrites_payload_data[1] $abc$27210$new_n7276 $abc$27210$new_n7275 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[1] _zz_RegFilePlugin_regFile_port0[1] $abc$27210$new_n7276 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[0] $abc$27210$new_n8163 $abc$27210$new_n7278 $abc$27210$auto$rtlil.cc:2693:MuxGate$22761 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n6725 HazardSimplePlugin_writeBackWrites_payload_data[0] $abc$27210$new_n7279 $abc$27210$new_n7278 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[0] _zz_RegFilePlugin_regFile_port0[0] $abc$27210$new_n7279 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_BRANCH_CTRL[0] _zz_execute_BRANCH_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22763 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_execute_BRANCH_CTRL[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22765 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22767 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7284 _zz_execute_SHIFT_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22769 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7285 $abc$27210$new_n4713 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n7284 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n7286 $abc$27210$new_n7285 +111 1 +.names _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n7286 +00 1 +.names $abc$27210$new_n4259 _zz_execute_ALU_BITWISE_CTRL[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$auto$rtlil.cc:2693:MuxGate$22771 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$27210$new_n4259 $abc$27210$new_n4304 _zz_execute_SRC2_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22773 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7290 _zz_execute_ALU_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22775 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n7290 +1100 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7292 _zz_execute_SRC1_CTRL[0] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22777 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4303 $abc$27210$new_n7292 +11 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PREDICTION_CONTEXT_line_history[0] decode_to_execute_PREDICTION_CONTEXT_line_history[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22779 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_decode_PREDICTION_CONTEXT_line_history_2[0] decode_to_execute_PREDICTION_CONTEXT_line_history[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22781 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[29] execute_to_memory_INSTRUCTION[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22785 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[28] execute_to_memory_INSTRUCTION[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22787 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[14] execute_to_memory_INSTRUCTION[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22815 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[13] execute_to_memory_INSTRUCTION[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22817 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[12] execute_to_memory_INSTRUCTION[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22819 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[4] execute_to_memory_INSTRUCTION[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22821 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[3] execute_to_memory_INSTRUCTION[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22823 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[2] execute_to_memory_INSTRUCTION[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22825 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[1] execute_to_memory_INSTRUCTION[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22827 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[0] execute_to_memory_INSTRUCTION[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22829 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[29] _zz__zz_execute_BranchPlugin_branch_src2_2[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22847 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[28] _zz__zz_execute_BranchPlugin_branch_src2_2[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22849 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[14] _zz__zz_execute_BranchPlugin_branch_src2_2[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22877 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[13] switch_Misc_l241_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$22879 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[12] _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22881 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22883 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22885 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22887 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22889 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[7] _zz_execute_BranchPlugin_branch_src2_10 $abc$27210$auto$rtlil.cc:2693:MuxGate$22891 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] _zz__zz_execute_BranchPlugin_branch_src2_2[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22907 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] _zz__zz_execute_BranchPlugin_branch_src2_2[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22909 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] _zz__zz_execute_BranchPlugin_branch_src2_2[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22911 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] _zz__zz_execute_BranchPlugin_branch_src2_2[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22913 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] _zz__zz_execute_BranchPlugin_branch_src2_2[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22915 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] _zz__zz_execute_BranchPlugin_branch_src2_2[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22917 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] _zz__zz_execute_BranchPlugin_branch_src2_2[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22919 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] _zz__zz_execute_BranchPlugin_branch_src2_2[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22921 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] _zz__zz_execute_BranchPlugin_branch_src2_2[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22923 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] _zz__zz_execute_BranchPlugin_branch_src2_2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22925 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] _zz_execute_BranchPlugin_branch_src2_8 $abc$27210$auto$rtlil.cc:2693:MuxGate$22927 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22929 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22931 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22933 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22935 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22937 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] _zz__zz_execute_BranchPlugin_branch_src2_2[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22939 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] switch_Misc_l241_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$22941 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_21 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22943 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22945 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22947 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22949 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22951 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 _zz_execute_BranchPlugin_branch_src2_10 $abc$27210$auto$rtlil.cc:2693:MuxGate$22953 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7410 $abc$27210$new_n7399 $abc$27210$new_n7340 BranchPlugin_branchExceptionPort_payload_badAddr[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23147 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 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$abc$27210$new_n7402 $abc$27210$new_n7401 $abc$27210$new_n7400 $abc$27210$new_n7345 $abc$27210$new_n7344 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$27210$new_n7398 $abc$27210$new_n7396 $abc$27210$new_n7397 $abc$27210$new_n7395 $abc$27210$new_n7346 $abc$27210$new_n7345 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7394 $abc$27210$new_n7392 $abc$27210$new_n7393 $abc$27210$new_n7391 $abc$27210$new_n7347 $abc$27210$new_n7346 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7390 $abc$27210$new_n7388 $abc$27210$new_n7389 $abc$27210$new_n7387 $abc$27210$new_n7348 $abc$27210$new_n7347 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names $abc$27210$new_n7386 $abc$27210$new_n7384 $abc$27210$new_n7385 $abc$27210$new_n7383 $abc$27210$new_n7349 $abc$27210$new_n7348 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7380 $abc$27210$new_n7382 $abc$27210$new_n7381 $abc$27210$new_n7350 $abc$27210$new_n7378 $abc$27210$new_n7349 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7376 $abc$27210$new_n7375 $abc$27210$new_n7374 $abc$27210$new_n7373 $abc$27210$new_n7351 $abc$27210$new_n7350 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n7368 $abc$27210$new_n7372 $abc$27210$new_n7371 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$abc$27210$new_n7357 _zz__zz_execute_BranchPlugin_branch_src2_4[1] _zz__zz_execute_BranchPlugin_branch_src2_2[1] $abc$27210$new_n7356 +0000 1 +0001 1 +1000 1 +1010 1 +.names decode_to_execute_PREDICTION_HAD_BRANCHED2 $abc$27210$new_n7358 $abc$27210$new_n7357 +10 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] $abc$27210$new_n7358 +11 1 +.names $abc$27210$new_n7358 _zz__zz_execute_BranchPlugin_branch_src2_2[0] execute_RS1[1] $abc$27210$new_n7361 $abc$27210$new_n7359 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz__zz_execute_BranchPlugin_branch_src2_4[0] _zz__zz_execute_BranchPlugin_branch_src2_2[0] _zz_execute_BRANCH_CTRL[0] $abc$27210$new_n7360 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10110 1 +.names _zz_execute_BranchPlugin_branch_src2_8 execute_RS1[0] $abc$27210$new_n7361 +11 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$27210$new_n7357 _zz__zz_execute_BranchPlugin_branch_src2_4[2] _zz__zz_execute_BranchPlugin_branch_src2_2[2] $abc$27210$new_n7362 +0010 1 +0011 1 +1001 1 +1011 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$27210$new_n7357 _zz__zz_execute_BranchPlugin_branch_src2_4[3] _zz__zz_execute_BranchPlugin_branch_src2_2[3] $abc$27210$new_n7363 +0010 1 +0011 1 +1001 1 +1011 1 +.names $abc$27210$new_n7358 execute_RS1[4] _zz_execute_to_memory_PC[4] $abc$27210$new_n7364 +000 1 +010 1 +100 1 +101 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[4] $abc$27210$new_n7366 $abc$27210$new_n7357 $abc$27210$new_n7365 +100 1 +.names $abc$27210$new_n7358 execute_RS1[5] _zz_execute_to_memory_PC[5] $abc$27210$new_n7366 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7366 $abc$27210$new_n7357 _zz__zz_execute_BranchPlugin_branch_src2_2[4] $abc$27210$new_n7367 +100 1 +110 1 +111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[6] $abc$27210$new_n7369 $abc$27210$new_n7357 $abc$27210$new_n7368 +100 1 +.names $abc$27210$new_n7358 execute_RS1[7] _zz_execute_to_memory_PC[7] $abc$27210$new_n7369 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7369 $abc$27210$new_n7357 _zz__zz_execute_BranchPlugin_branch_src2_2[6] $abc$27210$new_n7370 +100 1 +110 1 +111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[5] $abc$27210$new_n7357 $abc$27210$new_n7371 +10 1 +.names $abc$27210$new_n7358 execute_RS1[6] _zz_execute_to_memory_PC[6] $abc$27210$new_n7372 +000 1 +010 1 +100 1 +101 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[8] $abc$27210$new_n7357 $abc$27210$new_n7373 +10 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[7] $abc$27210$new_n7357 $abc$27210$new_n7374 +10 1 +.names $abc$27210$new_n7358 execute_RS1[9] _zz_execute_to_memory_PC[9] $abc$27210$new_n7375 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[8] _zz_execute_to_memory_PC[8] $abc$27210$new_n7376 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7379 $abc$27210$new_n7358 _zz_execute_BranchPlugin_branch_src2 $abc$27210$new_n7378 +000 1 +001 1 +010 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BranchPlugin_branch_src2_10 _zz_execute_BranchPlugin_branch_src2_8 _zz_execute_BRANCH_CTRL[0] $abc$27210$new_n7379 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10110 1 +.names $abc$27210$new_n7378 $abc$27210$new_n7358 _zz_execute_to_memory_PC[11] execute_RS1[11] $abc$27210$new_n7380 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[9] $abc$27210$new_n7357 $abc$27210$new_n7381 +10 1 +.names $abc$27210$new_n7358 execute_RS1[10] _zz_execute_to_memory_PC[10] $abc$27210$new_n7382 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[13] _zz_execute_to_memory_PC[13] $abc$27210$new_n7383 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[12] _zz_execute_to_memory_PC[12] $abc$27210$new_n7384 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 switch_Misc_l241_1 $abc$27210$new_n7385 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n7386 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n7358 execute_RS1[15] _zz_execute_to_memory_PC[15] $abc$27210$new_n7387 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[14] _zz_execute_to_memory_PC[14] $abc$27210$new_n7388 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$new_n7389 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[13] $abc$27210$new_n7390 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n7358 execute_RS1[17] _zz_execute_to_memory_PC[17] $abc$27210$new_n7391 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[16] _zz_execute_to_memory_PC[16] $abc$27210$new_n7392 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$new_n7393 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$new_n7394 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n7358 execute_RS1[19] _zz_execute_to_memory_PC[19] $abc$27210$new_n7395 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[18] _zz_execute_to_memory_PC[18] $abc$27210$new_n7396 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n7397 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$new_n7398 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$27210$new_n7357 $abc$27210$new_n7399 +10 1 +.names $abc$27210$new_n7358 execute_RS1[22] _zz_execute_to_memory_PC[22] $abc$27210$new_n7400 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[21] _zz_execute_to_memory_PC[21] $abc$27210$new_n7401 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[20] _zz_execute_to_memory_PC[20] $abc$27210$new_n7402 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[25] _zz_execute_to_memory_PC[25] $abc$27210$new_n7403 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[24] _zz_execute_to_memory_PC[24] $abc$27210$new_n7404 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[23] _zz_execute_to_memory_PC[23] $abc$27210$new_n7405 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7399 $abc$27210$new_n7358 execute_RS1[27] _zz_execute_to_memory_PC[27] $abc$27210$new_n7406 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n7358 $abc$27210$new_n7399 execute_RS1[27] _zz_execute_to_memory_PC[27] $abc$27210$new_n7407 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$27210$new_n7358 execute_RS1[28] _zz_execute_to_memory_PC[28] $abc$27210$new_n7408 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[29] _zz_execute_to_memory_PC[29] $abc$27210$new_n7409 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[30] _zz_execute_to_memory_PC[30] $abc$27210$new_n7410 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7409 $abc$27210$new_n7399 $abc$27210$new_n7341 BranchPlugin_branchExceptionPort_payload_badAddr[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23149 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7408 $abc$27210$new_n7399 $abc$27210$new_n7413 BranchPlugin_branchExceptionPort_payload_badAddr[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23151 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7406 $abc$27210$new_n7342 $abc$27210$new_n7407 $abc$27210$new_n7413 +001 1 +010 1 +011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7342 $abc$27210$new_n7407 $abc$27210$new_n7406 BranchPlugin_branchExceptionPort_payload_badAddr[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23153 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7416 BranchPlugin_branchExceptionPort_payload_badAddr[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23155 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n7399 $abc$27210$new_n7343 $abc$27210$new_n7358 _zz_execute_to_memory_PC[26] execute_RS1[26] $abc$27210$new_n7416 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7418 BranchPlugin_branchExceptionPort_payload_badAddr[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23157 +000 1 +001 1 +101 1 +111 1 +.names $abc$27210$new_n7405 $abc$27210$new_n7403 $abc$27210$new_n7404 $abc$27210$new_n7399 $abc$27210$new_n7344 $abc$27210$new_n7418 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7420 BranchPlugin_branchExceptionPort_payload_badAddr[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23159 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n7404 $abc$27210$new_n7405 $abc$27210$new_n7399 $abc$27210$new_n7344 $abc$27210$new_n7420 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7405 $abc$27210$new_n7399 $abc$27210$new_n7344 BranchPlugin_branchExceptionPort_payload_badAddr[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23161 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7400 $abc$27210$new_n7399 $abc$27210$new_n7423 BranchPlugin_branchExceptionPort_payload_badAddr[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23163 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7401 $abc$27210$new_n7399 $abc$27210$new_n7424 $abc$27210$new_n7423 +001 1 +100 1 +101 1 +111 1 +.names $abc$27210$new_n7402 $abc$27210$new_n7399 $abc$27210$new_n7345 $abc$27210$new_n7424 +001 1 +100 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7401 $abc$27210$new_n7399 $abc$27210$new_n7424 BranchPlugin_branchExceptionPort_payload_badAddr[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23165 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7402 $abc$27210$new_n7399 $abc$27210$new_n7345 BranchPlugin_branchExceptionPort_payload_badAddr[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23167 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7397 $abc$27210$new_n7395 $abc$27210$new_n7428 BranchPlugin_branchExceptionPort_payload_badAddr[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23169 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7398 $abc$27210$new_n7396 $abc$27210$new_n7346 $abc$27210$new_n7428 +011 1 +101 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7398 $abc$27210$new_n7396 $abc$27210$new_n7346 BranchPlugin_branchExceptionPort_payload_badAddr[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23171 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7431 BranchPlugin_branchExceptionPort_payload_badAddr[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23173 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n7393 $abc$27210$new_n7391 $abc$27210$new_n7394 $abc$27210$new_n7392 $abc$27210$new_n7347 $abc$27210$new_n7431 +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7394 $abc$27210$new_n7392 $abc$27210$new_n7347 BranchPlugin_branchExceptionPort_payload_badAddr[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23175 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7389 $abc$27210$new_n7387 $abc$27210$new_n7434 BranchPlugin_branchExceptionPort_payload_badAddr[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23177 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7390 $abc$27210$new_n7388 $abc$27210$new_n7348 $abc$27210$new_n7434 +011 1 +101 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7390 $abc$27210$new_n7388 $abc$27210$new_n7348 BranchPlugin_branchExceptionPort_payload_badAddr[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23179 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7385 $abc$27210$new_n7383 $abc$27210$new_n7437 BranchPlugin_branchExceptionPort_payload_badAddr[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23181 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7386 $abc$27210$new_n7384 $abc$27210$new_n7349 $abc$27210$new_n7437 +011 1 +101 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7386 $abc$27210$new_n7384 $abc$27210$new_n7349 BranchPlugin_branchExceptionPort_payload_badAddr[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23183 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7380 $abc$27210$new_n7440 BranchPlugin_branchExceptionPort_payload_badAddr[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23185 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n7382 $abc$27210$new_n7381 $abc$27210$new_n7350 $abc$27210$new_n7440 +001 1 +100 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7382 $abc$27210$new_n7381 $abc$27210$new_n7350 BranchPlugin_branchExceptionPort_payload_badAddr[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23187 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7375 $abc$27210$new_n7373 $abc$27210$new_n7443 BranchPlugin_branchExceptionPort_payload_badAddr[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23189 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7376 $abc$27210$new_n7374 $abc$27210$new_n7351 $abc$27210$new_n7443 +001 1 +100 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7376 $abc$27210$new_n7374 $abc$27210$new_n7351 BranchPlugin_branchExceptionPort_payload_badAddr[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23191 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7446 $abc$27210$new_n7370 $abc$27210$new_n7368 BranchPlugin_branchExceptionPort_payload_badAddr[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23193 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7372 $abc$27210$new_n7371 $abc$27210$new_n7352 $abc$27210$new_n7446 +001 1 +100 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7372 $abc$27210$new_n7371 $abc$27210$new_n7352 BranchPlugin_branchExceptionPort_payload_badAddr[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23195 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7353 $abc$27210$new_n7367 $abc$27210$new_n7365 BranchPlugin_branchExceptionPort_payload_badAddr[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23197 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7364 $abc$27210$new_n7363 $abc$27210$new_n7354 BranchPlugin_branchExceptionPort_payload_badAddr[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23199 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7451 $abc$27210$new_n7355 BranchPlugin_branchExceptionPort_payload_badAddr[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23201 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n7362 $abc$27210$new_n7358 _zz_execute_to_memory_PC[3] execute_RS1[3] $abc$27210$new_n7451 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck BranchPlugin_branchExceptionPort_payload_badAddr[2] $abc$27210$new_n7453 $abc$27210$auto$rtlil.cc:2693:MuxGate$23203 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7359 $abc$27210$new_n7356 $abc$27210$new_n7358 _zz_execute_to_memory_PC[2] execute_RS1[2] $abc$27210$new_n7453 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck BranchPlugin_branchExceptionPort_payload_badAddr[1] $abc$27210$new_n7455 $abc$27210$auto$rtlil.cc:2693:MuxGate$23205 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7358 $abc$27210$new_n7361 _zz__zz_execute_BranchPlugin_branch_src2_2[0] execute_RS1[1] $abc$27210$new_n7360 $abc$27210$new_n7455 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11110 1 +.names $abc$27210$new_n7457 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[30] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$23331 +011 1 +100 1 +101 1 +110 1 +111 1 +.names execute_RS2[30] $abc$27210$new_n7458 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7476 execute_RS2[29] $abc$27210$new_n7457 +00010 1 +00011 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11010 1 +.names $abc$27210$new_n7459 execute_RS2[28] $abc$27210$new_n7458 +10 1 +.names $abc$27210$new_n7460 execute_RS2[27] $abc$27210$new_n7459 +10 1 +.names $abc$27210$new_n7461 execute_RS2[26] $abc$27210$new_n7460 +10 1 +.names $abc$27210$new_n7462 execute_RS2[25] $abc$27210$new_n7461 +10 1 +.names $abc$27210$new_n7463 execute_RS2[24] $abc$27210$new_n7462 +10 1 +.names $abc$27210$new_n7464 execute_RS2[23] $abc$27210$new_n7463 +10 1 +.names $abc$27210$new_n7465 execute_RS2[22] $abc$27210$new_n7464 +10 1 +.names $abc$27210$new_n7466 execute_RS2[21] $abc$27210$new_n7465 +10 1 +.names $abc$27210$new_n7467 execute_RS2[20] $abc$27210$new_n7466 +10 1 +.names $abc$27210$new_n7468 execute_RS2[19] $abc$27210$new_n7467 +10 1 +.names $abc$27210$new_n7469 execute_RS2[18] $abc$27210$new_n7468 +10 1 +.names $abc$27210$new_n7470 execute_RS2[17] $abc$27210$new_n7469 +10 1 +.names $abc$27210$new_n7471 execute_RS2[15] execute_RS2[16] $abc$27210$new_n7470 +100 1 +.names $abc$27210$new_n7472 execute_RS2[14] $abc$27210$new_n7471 +10 1 +.names $abc$27210$new_n7473 execute_RS2[12] execute_RS2[13] $abc$27210$new_n7472 +100 1 +.names $abc$27210$new_n7474 execute_RS2[9] execute_RS2[10] execute_RS2[11] $abc$27210$new_n7473 +1000 1 +.names $abc$27210$new_n7475 execute_RS2[8] execute_RS2[7] execute_RS2[6] $abc$27210$new_n7474 +1000 1 +.names $abc$27210$new_n7477 $abc$27210$new_n7476 execute_RS2[4] execute_RS2[5] $abc$27210$new_n7475 +1100 1 +.names decode_to_execute_IS_RS1_SIGNED execute_RS2[31] $abc$27210$new_n7476 +11 1 +.names execute_RS2[0] execute_RS2[1] execute_RS2[2] execute_RS2[3] $abc$27210$new_n7477 +0000 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[29] $abc$27210$new_n7476 $abc$27210$new_n7458 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23333 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[28] $abc$27210$new_n7476 $abc$27210$new_n7459 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23335 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[27] $abc$27210$new_n7476 $abc$27210$new_n7460 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23337 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[26] $abc$27210$new_n7476 $abc$27210$new_n7461 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23339 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[25] $abc$27210$new_n7476 $abc$27210$new_n7462 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23341 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[24] $abc$27210$new_n7476 $abc$27210$new_n7463 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23343 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[23] $abc$27210$new_n7476 $abc$27210$new_n7464 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23345 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[22] $abc$27210$new_n7476 $abc$27210$new_n7465 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23347 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[21] $abc$27210$new_n7476 $abc$27210$new_n7466 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23349 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[20] $abc$27210$new_n7476 $abc$27210$new_n7467 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23351 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[19] $abc$27210$new_n7476 $abc$27210$new_n7468 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23353 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[18] $abc$27210$new_n7476 $abc$27210$new_n7469 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23355 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[17] $abc$27210$new_n7476 $abc$27210$new_n7470 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23357 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7492 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$23359 +011 1 +100 1 +101 1 +110 1 +111 1 +.names execute_RS2[16] $abc$27210$new_n7471 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7476 execute_RS2[15] $abc$27210$new_n7492 +00010 1 +00011 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11010 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[15] $abc$27210$new_n7476 $abc$27210$new_n7471 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23361 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[14] $abc$27210$new_n7476 $abc$27210$new_n7472 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23363 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7496 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$23365 +011 1 +100 1 +101 1 +110 1 +111 1 +.names execute_RS2[13] $abc$27210$new_n7473 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7476 execute_RS2[12] $abc$27210$new_n7496 +00010 1 +00011 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11010 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[12] $abc$27210$new_n7476 $abc$27210$new_n7473 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23367 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] $abc$27210$new_n7499 $abc$27210$auto$rtlil.cc:2693:MuxGate$23369 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[11] $abc$27210$new_n7476 $abc$27210$new_n7474 execute_RS2[9] execute_RS2[10] $abc$27210$new_n7499 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] $abc$27210$new_n7501 $abc$27210$auto$rtlil.cc:2693:MuxGate$23371 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[10] $abc$27210$new_n7474 $abc$27210$new_n7476 execute_RS2[9] $abc$27210$new_n7501 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[9] $abc$27210$new_n7476 $abc$27210$new_n7474 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23373 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] $abc$27210$new_n7504 $abc$27210$auto$rtlil.cc:2693:MuxGate$23375 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[8] $abc$27210$new_n7475 execute_RS2[6] $abc$27210$new_n7476 execute_RS2[7] $abc$27210$new_n7504 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] $abc$27210$new_n7506 $abc$27210$auto$rtlil.cc:2693:MuxGate$23377 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[7] $abc$27210$new_n7476 $abc$27210$new_n7475 execute_RS2[6] $abc$27210$new_n7506 +0010 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[6] $abc$27210$new_n7476 $abc$27210$new_n7475 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23379 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[5] $abc$27210$new_n7476 $abc$27210$new_n7509 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23381 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7477 execute_RS2[4] $abc$27210$new_n7509 +10 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[4] $abc$27210$new_n7476 $abc$27210$new_n7477 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23383 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[3] $abc$27210$new_n7512 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23385 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n7476 execute_RS2[1] execute_RS2[2] execute_RS2[0] $abc$27210$new_n7512 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] $abc$27210$new_n7514 $abc$27210$auto$rtlil.cc:2693:MuxGate$23387 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[2] $abc$27210$new_n7476 execute_RS2[0] execute_RS2[1] $abc$27210$new_n7514 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[1] execute_RS2[0] $abc$27210$new_n7476 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23389 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] execute_RS2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23391 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[30] _zz_execute_to_memory_PC[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24099 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[29] _zz_execute_to_memory_PC[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24101 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[28] _zz_execute_to_memory_PC[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24103 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[27] _zz_execute_to_memory_PC[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24105 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[26] _zz_execute_to_memory_PC[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24107 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[25] _zz_execute_to_memory_PC[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24109 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[24] _zz_execute_to_memory_PC[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24111 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[23] _zz_execute_to_memory_PC[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24113 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[22] _zz_execute_to_memory_PC[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24115 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[21] _zz_execute_to_memory_PC[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24117 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[20] _zz_execute_to_memory_PC[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24119 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[19] _zz_execute_to_memory_PC[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24121 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[18] _zz_execute_to_memory_PC[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24123 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[17] _zz_execute_to_memory_PC[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24125 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[16] _zz_execute_to_memory_PC[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24127 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[15] _zz_execute_to_memory_PC[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24129 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[14] _zz_execute_to_memory_PC[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24131 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[13] _zz_execute_to_memory_PC[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24133 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[12] _zz_execute_to_memory_PC[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24135 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[9] _zz_execute_to_memory_PC[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24137 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[8] _zz_execute_to_memory_PC[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24139 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[7] _zz_execute_to_memory_PC[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24141 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[6] _zz_execute_to_memory_PC[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24143 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[5] _zz_execute_to_memory_PC[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24145 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[4] _zz_execute_to_memory_PC[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24147 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[3] _zz_execute_to_memory_PC[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24149 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[2] _zz_execute_to_memory_PC[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24151 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[1] _zz_execute_to_memory_PC[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24153 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[0] _zz_execute_to_memory_PC[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24155 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] _zz_execute_to_memory_PC[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24345 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] _zz_execute_to_memory_PC[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24347 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] _zz_execute_to_memory_PC[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24349 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] _zz_execute_to_memory_PC[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24351 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] _zz_execute_to_memory_PC[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24353 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] _zz_execute_to_memory_PC[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24355 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] _zz_execute_to_memory_PC[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24357 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] _zz_execute_to_memory_PC[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24359 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] _zz_execute_to_memory_PC[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24361 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] _zz_execute_to_memory_PC[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24363 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] _zz_execute_to_memory_PC[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24365 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] _zz_execute_to_memory_PC[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24367 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] _zz_execute_to_memory_PC[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24369 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] _zz_execute_to_memory_PC[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24371 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] _zz_execute_to_memory_PC[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24373 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] _zz_execute_to_memory_PC[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24375 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] _zz_execute_to_memory_PC[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24377 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] _zz_execute_to_memory_PC[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24379 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] _zz_execute_to_memory_PC[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24381 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] _zz_execute_to_memory_PC[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24383 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] _zz_execute_to_memory_PC[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24385 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] _zz_execute_to_memory_PC[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24387 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] _zz_execute_to_memory_PC[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24389 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] _zz_execute_to_memory_PC[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24391 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] _zz_execute_to_memory_PC[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24393 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] _zz_execute_to_memory_PC[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24395 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] _zz_execute_to_memory_PC[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24397 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] _zz_execute_to_memory_PC[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24399 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] _zz_execute_to_memory_PC[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24401 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4326 DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$24465 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_835 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n7577 $abc$27210$auto$rtlil.cc:2693:MuxGate$24499 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n7578 IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n7577 +1100 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n7579 $abc$27210$new_n4709 $abc$27210$new_n7578 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n7579 +1000 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_834 $abc$27210$new_n4732 $abc$27210$new_n7578 $abc$27210$auto$rtlil.cc:2693:MuxGate$24501 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7582 execute_CsrPlugin_csr_833 $abc$27210$auto$rtlil.cc:2693:MuxGate$24503 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n7578 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n7582 +11000 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7584 execute_CsrPlugin_csr_772 $abc$27210$auto$rtlil.cc:2693:MuxGate$24505 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n7585 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n7584 +11000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4736 $abc$27210$new_n4709 $abc$27210$new_n7585 +1111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7587 execute_CsrPlugin_csr_836 $abc$27210$auto$rtlil.cc:2693:MuxGate$24507 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n7578 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n7587 +11000 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_384 IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n7589 $abc$27210$auto$rtlil.cc:2693:MuxGate$24509 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n7590 IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$new_n7589 +1000 1 +.names $abc$27210$new_n4729 $abc$27210$new_n4708 $abc$27210$new_n7590 +11 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_256 $abc$27210$new_n4736 $abc$27210$new_n7590 $abc$27210$auto$rtlil.cc:2693:MuxGate$24511 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_768 $abc$27210$new_n4729 $abc$27210$new_n7585 $abc$27210$auto$rtlil.cc:2693:MuxGate$24513 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6100 _zz_writeBack_MulPlugin_result[65] _zz_memory_MUL_LOW_6[51] _zz_memory_MUL_LOW_4[51] $abc$27210$auto$rtlil.cc:2693:MuxGate$24515 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck decode_to_execute_PREDICTION_HAD_BRANCHED2 $abc$27210$new_n7595 execute_to_memory_BRANCH_DO $abc$27210$new_n7617 $abc$27210$auto$rtlil.cc:2693:MuxGate$24517 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$27210$new_n7596 _zz_execute_BRANCH_CTRL[0] $abc$27210$new_n7595 +000 1 +010 1 +011 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[13] _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n6996 $abc$27210$new_n7597 $abc$27210$new_n7596 +00000 1 +00010 1 +00110 1 +00111 1 +01001 1 +01011 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n7598 $abc$27210$new_n6090 $abc$27210$new_n5407 $abc$27210$new_n7597 +100 1 +111 1 +.names $abc$27210$new_n7615 $abc$27210$new_n7613 $abc$27210$new_n7608 $abc$27210$new_n7603 $abc$27210$new_n7599 $abc$27210$new_n7598 +11111 1 +.names $abc$27210$new_n7602 $abc$27210$new_n7600 $abc$27210$new_n6093 $abc$27210$new_n5402 $abc$27210$new_n6998 $abc$27210$new_n7599 +11000 1 +11110 1 +.names $abc$27210$new_n7601 $abc$27210$new_n5397 $abc$27210$new_n6425 $abc$27210$new_n5385 $abc$27210$new_n6429 $abc$27210$new_n7600 +10100 1 +10111 1 +11000 1 +11011 1 +.names $abc$27210$new_n6761 $abc$27210$new_n6751 $abc$27210$new_n5378 $abc$27210$new_n5348 $abc$27210$new_n7601 +0011 1 +0101 1 +1010 1 +1100 1 +.names $abc$27210$new_n6782 $abc$27210$new_n5948 $abc$27210$new_n6794 $abc$27210$new_n5422 $abc$27210$new_n7602 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n7606 $abc$27210$new_n7604 $abc$27210$new_n6755 $abc$27210$new_n5373 $abc$27210$new_n7607 $abc$27210$new_n7603 +11010 1 +11100 1 +.names $abc$27210$new_n7605 $abc$27210$new_n6792 $abc$27210$new_n5437 $abc$27210$new_n6800 $abc$27210$new_n5417 $abc$27210$new_n7604 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6769 $abc$27210$new_n5327 $abc$27210$new_n6776 $abc$27210$new_n5322 $abc$27210$new_n7605 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n6757 $abc$27210$new_n6788 $abc$27210$new_n5447 $abc$27210$new_n5357 $abc$27210$new_n7606 +0001 1 +0111 1 +1000 1 +1110 1 +.names $abc$27210$new_n6784 $abc$27210$new_n5302 $abc$27210$new_n7607 +01 1 +10 1 +.names $abc$27210$new_n7612 $abc$27210$new_n7609 $abc$27210$new_n6771 $abc$27210$new_n5332 $abc$27210$new_n7611 $abc$27210$new_n7608 +11000 1 +11110 1 +.names $abc$27210$new_n7610 $abc$27210$new_n6802 $abc$27210$new_n5953 $abc$27210$new_n6767 $abc$27210$new_n5342 $abc$27210$new_n7609 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6774 $abc$27210$new_n6786 $abc$27210$new_n5442 $abc$27210$new_n5317 $abc$27210$new_n7610 +0001 1 +0111 1 +1000 1 +1110 1 +.names $abc$27210$new_n6759 $abc$27210$new_n5362 $abc$27210$new_n7611 +00 1 +11 1 +.names $abc$27210$new_n6753 $abc$27210$new_n6778 $abc$27210$new_n5307 $abc$27210$new_n5370 $abc$27210$new_n7612 +0001 1 +0111 1 +1000 1 +1110 1 +.names $abc$27210$new_n6763 $abc$27210$new_n6765 $abc$27210$new_n5337 $abc$27210$new_n5352 $abc$27210$new_n7614 $abc$27210$new_n7613 +00010 1 +01110 1 +10000 1 +11100 1 +.names $abc$27210$new_n6780 $abc$27210$new_n5312 $abc$27210$new_n7614 +01 1 +10 1 +.names $abc$27210$new_n7616 $abc$27210$new_n6790 $abc$27210$new_n5432 $abc$27210$new_n5392 $abc$27210$new_n6427 $abc$27210$new_n7615 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6796 $abc$27210$new_n5427 $abc$27210$new_n6798 $abc$27210$new_n5412 $abc$27210$new_n7616 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_BRANCH_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_2[0] _zz_execute_BRANCH_CTRL[0] execute_RS1[1] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$27210$new_n7617 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[51] execute_MUL_HL[33] $abc$27210$auto$rtlil.cc:2693:MuxGate$24523 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[51] execute_MUL_LH[33] $abc$27210$auto$rtlil.cc:2693:MuxGate$24525 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[31] execute_MUL_LL[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24527 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6518 _zz_decode_RS2_3[0] $abc$27210$new_n6421 $abc$27210$new_n6429 $abc$27210$auto$rtlil.cc:2693:MuxGate$24529 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[31] $abc$27210$new_n7623 $abc$27210$auto$rtlil.cc:2693:MuxGate$24531 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n7624 memory_DivPlugin_div_result[31] execute_to_memory_IS_DIV DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n7623 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n7625 _zz_decode_RS2_3[0] $abc$27210$new_n7624 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] _zz_decode_RS2_3[31] $abc$27210$new_n7625 +010 1 +011 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8171 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24533 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[9] MmuPlugin_satp_ppn[19] $abc$27210$new_n7631 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[31] execute_to_memory_MEMORY_STORE_DATA_RF[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24535 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[31] $abc$27210$new_n7634 $abc$27210$auto$rtlil.cc:2693:MuxGate$24537 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[31] execute_RS2[7] execute_RS2[15] $abc$27210$new_n7634 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4259 $abc$27210$new_n4425 decode_to_execute_PREDICTION_HAD_BRANCHED2 $abc$27210$auto$rtlil.cc:2693:MuxGate$24539 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4259 decode_to_execute_DO_EBREAK $abc$27210$new_n7637 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24541 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$27210$new_n7638 DebugPlugin_debugUsed DebugPlugin_haltIt DebugPlugin_disableEbreak $abc$27210$new_n7637 +1100 1 +.names $abc$27210$new_n4714 $abc$27210$new_n4303 $abc$27210$new_n7638 +11 1 +.names $abc$27210$new_n4259 decode_to_execute_CSR_WRITE_OPCODE IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4735 $abc$27210$auto$rtlil.cc:2693:MuxGate$24543 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n4259 decode_to_execute_SRC2_FORCE_ZERO _zz__zz_decode_IS_CSR_85 _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24545 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[31] $abc$27210$new_n8171 $abc$27210$new_n7642 $abc$27210$auto$rtlil.cc:2693:MuxGate$24547 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n7623 HazardSimplePlugin_writeBackWrites_payload_data[31] $abc$27210$new_n7643 $abc$27210$new_n7642 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[31] _zz_RegFilePlugin_regFile_port1[31] $abc$27210$new_n7643 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[31] $abc$27210$new_n8171 $abc$27210$new_n7645 $abc$27210$auto$rtlil.cc:2693:MuxGate$24549 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n7623 HazardSimplePlugin_writeBackWrites_payload_data[31] $abc$27210$new_n7646 $abc$27210$new_n7645 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[31] _zz_RegFilePlugin_regFile_port0[31] $abc$27210$new_n7646 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24551 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7649 _zz_execute_BRANCH_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24553 +001 1 +011 1 +100 1 +101 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n7649 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4093 _zz_writeBack_ENV_CTRL _zz_memory_ENV_CTRL $abc$27210$auto$rtlil.cc:2693:MuxGate$24555 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$27210$auto$rtlil.cc:2693:MuxGate$24557 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_execute_ENV_CTRL $abc$27210$new_n7638 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24559 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n4259 decode_to_execute_IS_CSR $abc$27210$new_n4303 $abc$27210$new_n4714 $abc$27210$auto$rtlil.cc:2693:MuxGate$24561 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_21 decode_to_execute_IS_RS1_SIGNED $abc$27210$auto$rtlil.cc:2693:MuxGate$24563 +001 1 +011 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_IS_DIV decode_to_execute_IS_DIV $abc$27210$auto$rtlil.cc:2693:MuxGate$24565 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 decode_to_execute_IS_DIV IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n7657 $abc$27210$auto$rtlil.cc:2693:MuxGate$24567 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n7286 $abc$27210$new_n7657 +111 1 +.names $abc$27210$new_n4093 memory_to_writeBack_IS_MUL execute_to_memory_IS_MUL $abc$27210$auto$rtlil.cc:2693:MuxGate$24569 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_IS_MUL decode_to_execute_IS_MUL $abc$27210$auto$rtlil.cc:2693:MuxGate$24571 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 decode_to_execute_IS_MUL $abc$27210$new_n4715 $abc$27210$new_n4712 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24573 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_SHIFT_CTRL[1] _zz_execute_SHIFT_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24575 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_execute_SHIFT_CTRL[1] $abc$27210$new_n7285 $abc$27210$new_n4727 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24577 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_21 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24579 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n5859 decode_to_execute_SRC_LESS_UNSIGNED IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24581 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 decode_to_execute_IS_SFENCE_VMA2 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n7638 $abc$27210$auto$rtlil.cc:2693:MuxGate$24583 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4259 decode_to_execute_MEMORY_MANAGMENT IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24585 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$27210$new_n4093 memory_to_writeBack_MEMORY_WR execute_to_memory_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24587 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_WR decode_to_execute_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24589 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_41 decode_to_execute_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24591 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_BYPASSABLE_MEMORY_STAGE decode_to_execute_BYPASSABLE_MEMORY_STAGE $abc$27210$auto$rtlil.cc:2693:MuxGate$24593 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7672 decode_to_execute_BYPASSABLE_MEMORY_STAGE $abc$27210$auto$rtlil.cc:2693:MuxGate$24595 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n7286 _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n7672 +10000 1 +10001 1 +10010 1 +10011 1 +11010 1 +11110 1 +.names $abc$27210$new_n4259 decode_to_execute_BYPASSABLE_EXECUTE_STAGE $abc$27210$new_n7674 $abc$27210$new_n4723 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24597 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n7674 +10000 1 +10010 1 +11000 1 +11001 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_valid execute_to_memory_REGFILE_WRITE_VALID $abc$27210$auto$rtlil.cc:2693:MuxGate$24599 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$27210$auto$rtlil.cc:2693:MuxGate$24601 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 decode_to_execute_REGFILE_WRITE_VALID $abc$27210$new_n4707 $abc$27210$new_n7678 $abc$27210$auto$rtlil.cc:2693:MuxGate$24605 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4304 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4714 $abc$27210$new_n7678 +00100 1 +00101 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_85 _zz_execute_SRC2_CTRL[1] $abc$27210$new_n4314 _zz__zz_decode_IS_CSR_41 $abc$27210$auto$rtlil.cc:2693:MuxGate$24607 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 _zz_execute_ALU_CTRL[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24609 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$27210$new_n4093 memory_to_writeBack_MEMORY_ENABLE execute_to_memory_MEMORY_ENABLE $abc$27210$auto$rtlil.cc:2693:MuxGate$24611 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_ENABLE decode_to_execute_MEMORY_ENABLE $abc$27210$auto$rtlil.cc:2693:MuxGate$24613 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 decode_to_execute_MEMORY_ENABLE $abc$27210$new_n4314 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24615 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$27210$new_n4259 _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n7685 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24617 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n7685 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7292 _zz_execute_SRC1_CTRL[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24619 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PREDICTION_CONTEXT_line_history[1] decode_to_execute_PREDICTION_CONTEXT_line_history[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24621 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PREDICTION_CONTEXT_hazard decode_to_execute_PREDICTION_CONTEXT_hazard $abc$27210$auto$rtlil.cc:2693:MuxGate$24623 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_decode_PREDICTION_CONTEXT_line_history_2[1] decode_to_execute_PREDICTION_CONTEXT_line_history[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24625 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_decode_PREDICTION_CONTEXT_hazard_4 decode_to_execute_PREDICTION_CONTEXT_hazard $abc$27210$auto$rtlil.cc:2693:MuxGate$24627 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_6 _zz_execute_BranchPlugin_branch_src2 $abc$27210$auto$rtlil.cc:2693:MuxGate$24633 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_result_5 $abc$27210$new_n7693 $abc$27210$auto$rtlil.cc:2693:MuxGate$24651 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7702 $abc$27210$new_n7477 $abc$27210$new_n7700 $abc$27210$new_n7694 $abc$27210$new_n7693 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$27210$new_n7697 $abc$27210$new_n7695 $abc$27210$new_n7699 execute_RS2[4] execute_RS2[5] $abc$27210$new_n7694 +11100 1 +.names $abc$27210$new_n7696 execute_RS2[21] execute_RS2[22] execute_RS2[23] execute_RS2[24] $abc$27210$new_n7695 +10000 1 +.names execute_RS2[25] execute_RS2[26] execute_RS2[27] execute_RS2[28] $abc$27210$new_n7696 +0000 1 +.names $abc$27210$new_n7698 execute_RS2[13] execute_RS2[14] execute_RS2[15] execute_RS2[16] $abc$27210$new_n7697 +10000 1 +.names execute_RS2[17] execute_RS2[18] execute_RS2[19] execute_RS2[20] $abc$27210$new_n7698 +0000 1 +.names execute_RS2[29] execute_RS2[30] execute_RS2[6] execute_RS2[7] $abc$27210$new_n7699 +0000 1 +.names $abc$27210$new_n7701 execute_RS2[9] execute_RS2[10] execute_RS2[11] execute_RS2[12] $abc$27210$new_n7700 +10000 1 +.names decode_to_execute_IS_RS1_SIGNED execute_RS2[31] switch_Misc_l241_1 execute_RS2[8] $abc$27210$new_n7701 +1000 1 +.names decode_to_execute_IS_RS1_SIGNED decode_to_execute_IS_DIV execute_RS1[31] execute_RS2[31] switch_Misc_l241_1 $abc$27210$new_n7702 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7704 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] execute_RS2[31] decode_to_execute_IS_RS1_SIGNED $abc$27210$auto$rtlil.cc:2693:MuxGate$24653 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7458 execute_RS2[29] execute_RS2[30] $abc$27210$new_n7476 $abc$27210$new_n7704 +1001 1 +1110 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_mask[3] dataCache_1.stageA_mask[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24793 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4198 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] $abc$27210$new_n7712 +10 1 +.names $abc$27210$new_n3940 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] $abc$27210$new_n4111 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] $abc$27210$new_n7714 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7716 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[5] $abc$27210$new_n4192 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[6] $abc$27210$new_n4186 $abc$27210$new_n7715 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n7717 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[21] $abc$27210$new_n8126 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] $abc$27210$new_n4146 $abc$27210$new_n7716 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4140 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[13] dataCache_1._zz_ways_0_tagsReadRsp_valid_1[16] $abc$27210$new_n4122 $abc$27210$new_n7717 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n7719 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[19] $abc$27210$new_n4106 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[11] $abc$27210$new_n4152 $abc$27210$new_n7718 +10100 1 +10111 1 +11000 1 +11011 1 +.names $abc$27210$new_n4180 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[7] dataCache_1._zz_ways_0_tagsReadRsp_valid_1[10] $abc$27210$new_n4162 $abc$27210$new_n7719 +0000 1 +0011 1 +1100 1 +1111 1 +.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] $abc$27210$new_n4198 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] $abc$27210$new_n3940 $abc$27210$new_n7721 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[0] $abc$27210$new_n4093 $abc$27210$new_n4146 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] $abc$27210$new_n7723 +1000 1 +1010 1 +1011 1 +.names dataCache_1.stageA_request_size[1] dataCache_1.stageA_request_size[0] $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24797 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataColisions dataCache_1.stage0_dataColisions_regNextWhen $abc$27210$new_n7728 $abc$27210$new_n7726 $abc$27210$auto$rtlil.cc:2693:MuxGate$24799 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6003 $abc$27210$new_n4095 $abc$27210$new_n7727 $abc$27210$new_n7726 +000 1 +001 1 +010 1 +.names dBus_cmd_payload_wr dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4100 $abc$27210$new_n7727 +1100 1 +.names $abc$27210$new_n7736 $abc$27210$new_n8181 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] dataCache_1.dataWriteCmd_payload_address[2] $abc$27210$new_n7728 +1100 1 +1111 1 +.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[1] dataCache_1.stageB_mmuRsp_physicalAddress[3] dataCache_1.dataWriteCmd_payload_address[1] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[0] dataCache_1.stageB_mmuRsp_physicalAddress[2] dataCache_1.dataWriteCmd_payload_address[0] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7739 $abc$27210$new_n7737 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] dBus_cmd_payload_address[6] $abc$27210$new_n7736 +1100 1 +1111 1 +.names $abc$27210$new_n7738 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] dBus_cmd_payload_address[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] dBus_cmd_payload_address[11] $abc$27210$new_n7737 +10000 1 +10011 1 +11100 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] dBus_cmd_payload_address[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] dBus_cmd_payload_address[10] $abc$27210$new_n7738 +0000 1 +0011 1 +1100 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] dBus_cmd_payload_address[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] dBus_cmd_payload_address[9] $abc$27210$new_n7739 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[2] dataCache_1.stageB_mmuRsp_physicalAddress[4] dataCache_1.dataWriteCmd_payload_address[2] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[31] dataCache_1._zz_ways_0_data_port0[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24801 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_tagsReadRsp_0_error dataCache_1._zz_ways_0_tagsReadRsp_valid_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24803 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_request_size[1] dataCache_1.stageA_request_size[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24829 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_wr dataCache_1.io_cpu_memory_isWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24831 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7746 dataCache_1.stage0_dataColisions_regNextWhen DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$24833 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n7747 dBus_cmd_payload_address[10] dataCache_1.dataReadCmd_payload[8] dBus_cmd_payload_address[11] dataCache_1.dataReadCmd_payload[9] $abc$27210$new_n7746 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n7748 dBus_cmd_payload_address[8] dataCache_1.dataReadCmd_payload[6] dBus_cmd_payload_address[9] dataCache_1.dataReadCmd_payload[7] $abc$27210$new_n7747 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8184 dBus_cmd_payload_address[6] dataCache_1.dataReadCmd_payload[4] dBus_cmd_payload_address[7] dataCache_1.dataReadCmd_payload[5] $abc$27210$new_n7748 +10000 1 +10011 1 +11100 1 +11111 1 +.names dataCache_1.dataWriteCmd_payload_address[0] dataCache_1.dataReadCmd_payload[0] $abc$27210$new_n7726 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7751 +0000 1 +1100 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6986 $abc$27210$new_n6988 dataCache_1.dataReadCmd_payload[0] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n6003 dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[1] $abc$27210$new_n6095 $abc$27210$new_n6097 $abc$27210$new_n7755 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n6091 $abc$27210$new_n4327 $abc$27210$new_n6089 $abc$27210$new_n7756 +00000 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6979 $abc$27210$new_n6982 dataCache_1.dataReadCmd_payload[1] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6965 $abc$27210$new_n6968 dataCache_1.dataReadCmd_payload[3] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6975 $abc$27210$new_n6973 $abc$27210$new_n5385 dataCache_1.dataReadCmd_payload[2] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6951 $abc$27210$new_n6954 dataCache_1.dataReadCmd_payload[5] +010 1 +011 1 +100 1 +110 1 +.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6961 $abc$27210$new_n6959 $abc$27210$new_n5373 dataCache_1.dataReadCmd_payload[4] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6937 $abc$27210$new_n6940 dataCache_1.dataReadCmd_payload[7] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6947 $abc$27210$new_n6945 $abc$27210$new_n5362 dataCache_1.dataReadCmd_payload[6] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6923 $abc$27210$new_n6926 dataCache_1.dataReadCmd_payload[9] +010 1 +011 1 +100 1 +110 1 +.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6933 $abc$27210$new_n6931 $abc$27210$new_n5352 dataCache_1.dataReadCmd_payload[8] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[3] $abc$27210$new_n7756 $abc$27210$auto$rtlil.cc:2693:MuxGate$24835 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_request_size[1] switch_Misc_l241_1 $abc$27210$new_n4327 $abc$27210$auto$rtlil.cc:2693:MuxGate$24837 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.io_cpu_memory_isWrite decode_to_execute_MEMORY_WR $abc$27210$new_n4327 $abc$27210$auto$rtlil.cc:2693:MuxGate$24839 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7770 DBusCachedPlugin_mmuBus_cmd_0_isStuck BranchPlugin_branchExceptionPort_payload_badAddr[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24873 +000 1 +001 1 +011 1 +.names $abc$27210$new_n7410 $abc$27210$new_n7771 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7399 $abc$27210$new_n7340 $abc$27210$new_n7770 +00000 1 +01001 1 +01010 1 +01011 1 +10011 1 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n7358 execute_RS1[31] _zz_execute_to_memory_PC[31] $abc$27210$new_n7771 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] _zz_execute_to_memory_PC[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24885 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[31] _zz_execute_to_memory_PC[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24895 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7086 $abc$27210$new_n5857 $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_valid +110 1 +.names execute_RS1[31] _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 execute_MulPlugin_aHigh[16] +101 1 +110 1 +.names execute_RS2[31] _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 execute_MulPlugin_bHigh[16] +110 1 +.names $abc$27210$new_n4636 DebugPlugin_godmode CsrPlugin_exception +10 1 +.names $abc$27210$new_n7779 $abc$27210$new_n4266 $0\DebugPlugin_isPipBusy[0:0] +00 1 +01 1 +10 1 +.names execute_arbitration_isValid memory_arbitration_isValid lastStageIsValid IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$new_n7779 +00000 1 +.names iBus_rsp_payload_error IBusCachedPlugin_cache.lineLoader_hadError IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_error +01 1 +10 1 +11 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$new_n6015 IBusCachedPlugin_cache._zz_2 +00 1 +01 1 +11 1 +.names IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.lineLoader_cmdSent iBus_cmd_valid +10 1 +.names $abc$27210$new_n7784 decode_to_execute_MEMORY_ENABLE $abc$27210$flatten\dataCache_1.$0\stageB_flusher_start[0:0] +10 1 +.names $abc$27210$new_n7785 DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation MmuPlugin_dBusAccess_rsp_payload_redo memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE $abc$27210$new_n7784 +10000 1 +10001 1 +10010 1 +.names decode_to_execute_MEMORY_MANAGMENT execute_arbitration_isValid $abc$27210$new_n4100 dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_waitDone $abc$27210$new_n7785 +11100 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n4327 dataCache_1.io_cpu_execute_refilling decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid dataCache_1._zz_ways_0_dataReadRspMem +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[3] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol3$./benchmark/VexRiscv.v:6887$1195_EN[7:0]$1223[7] +001 1 +010 1 +011 1 +.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[2] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol2$./benchmark/VexRiscv.v:6884$1194_EN[7:0]$1220[7] +001 1 +010 1 +011 1 +.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[1] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol1$./benchmark/VexRiscv.v:6881$1193_EN[7:0]$1217[7] +001 1 +010 1 +011 1 +.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[0] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol0$./benchmark/VexRiscv.v:6878$1192_EN[7:0]$1214[7] +001 1 +010 1 +011 1 +.names $abc$27210$new_n5826 $abc$27210$new_n4424 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_line_history_1 +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_hadError $abc$27210$new_n6015 iBus_rsp_payload_error iBus_rsp_valid $abc$27210$flatten\IBusCachedPlugin_cache.$0\lineLoader_hadError[0:0] +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24235 +00 1 +11 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_flushCounter[0] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24233 +010 1 +100 1 +101 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7796 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24231 +010 1 +100 1 +101 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_flushCounter[0] $abc$27210$new_n7796 +11 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24229 +01 1 +10 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7796 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$new_n7798 +110 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24227 +011 1 +100 1 +101 1 +110 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24225 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[6] IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7802 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24867 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7796 $abc$27210$new_n7802 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7802 IBusCachedPlugin_cache.lineLoader_flushCounter[6] $abc$27210$flatten\IBusCachedPlugin_cache.$procmux$1907_Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[5] IBusCachedPlugin_cache.lineLoader_flushCounter[0] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[0] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[6] IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[1] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[7] IBusCachedPlugin_cache.lineLoader_flushCounter[2] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[2] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[8] IBusCachedPlugin_cache.lineLoader_flushCounter[3] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[3] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[9] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[4] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[10] IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[5] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[11] IBusCachedPlugin_cache.lineLoader_flushCounter[6] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5829 DebugPlugin_haltedByBreak debug_bus_cmd_payload_data[25] $abc$27210$new_n5967 $0\DebugPlugin_haltedByBreak[0:0] +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names DebugPlugin_godmode debug_bus_cmd_payload_data[25] $abc$27210$new_n5967 DebugPlugin_isPipBusy DebugPlugin_haltIt $0\DebugPlugin_godmode[0:0] +00001 1 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n7814 $abc$27210$new_n5854 $abc$27210$new_n4266 $0\DebugPlugin_haltIt[0:0] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$27210$new_n5829 DebugPlugin_haltIt $abc$27210$new_n5967 debug_bus_cmd_payload_data[25] debug_bus_cmd_payload_data[17] $abc$27210$new_n7814 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +01111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n5404 CsrPlugin_mepc[0] $abc$27210$new_n4432 $0\CsrPlugin_mepc[31:0][0] +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_833 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n7816 +1111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n5399 CsrPlugin_mepc[1] $abc$27210$new_n4432 $0\CsrPlugin_mepc[31:0][1] +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5394 CsrPlugin_mepc[2] DBusCachedPlugin_redoBranch_payload[2] $0\CsrPlugin_mepc[31:0][2] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5387 CsrPlugin_mepc[3] DBusCachedPlugin_redoBranch_payload[3] $0\CsrPlugin_mepc[31:0][3] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5382 CsrPlugin_mepc[4] DBusCachedPlugin_redoBranch_payload[4] $0\CsrPlugin_mepc[31:0][4] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5377 CsrPlugin_mepc[5] DBusCachedPlugin_redoBranch_payload[5] $0\CsrPlugin_mepc[31:0][5] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5372 CsrPlugin_mepc[6] DBusCachedPlugin_redoBranch_payload[6] $0\CsrPlugin_mepc[31:0][6] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5366 CsrPlugin_mepc[7] DBusCachedPlugin_redoBranch_payload[7] $0\CsrPlugin_mepc[31:0][7] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5361 CsrPlugin_mepc[8] DBusCachedPlugin_redoBranch_payload[8] $0\CsrPlugin_mepc[31:0][8] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5356 CsrPlugin_mepc[9] DBusCachedPlugin_redoBranch_payload[9] $0\CsrPlugin_mepc[31:0][9] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5351 CsrPlugin_mepc[10] DBusCachedPlugin_redoBranch_payload[10] $0\CsrPlugin_mepc[31:0][10] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5344 CsrPlugin_mepc[11] DBusCachedPlugin_redoBranch_payload[11] $0\CsrPlugin_mepc[31:0][11] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5339 CsrPlugin_mepc[12] DBusCachedPlugin_redoBranch_payload[12] $0\CsrPlugin_mepc[31:0][12] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5334 CsrPlugin_mepc[13] DBusCachedPlugin_redoBranch_payload[13] $0\CsrPlugin_mepc[31:0][13] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5329 CsrPlugin_mepc[14] DBusCachedPlugin_redoBranch_payload[14] $0\CsrPlugin_mepc[31:0][14] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5324 CsrPlugin_mepc[15] DBusCachedPlugin_redoBranch_payload[15] $0\CsrPlugin_mepc[31:0][15] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5319 CsrPlugin_mepc[16] DBusCachedPlugin_redoBranch_payload[16] $0\CsrPlugin_mepc[31:0][16] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5314 CsrPlugin_mepc[17] DBusCachedPlugin_redoBranch_payload[17] $0\CsrPlugin_mepc[31:0][17] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5309 CsrPlugin_mepc[18] DBusCachedPlugin_redoBranch_payload[18] $0\CsrPlugin_mepc[31:0][18] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5304 CsrPlugin_mepc[19] DBusCachedPlugin_redoBranch_payload[19] $0\CsrPlugin_mepc[31:0][19] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5299 CsrPlugin_mepc[20] DBusCachedPlugin_redoBranch_payload[20] $0\CsrPlugin_mepc[31:0][20] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5945 CsrPlugin_mepc[21] DBusCachedPlugin_redoBranch_payload[21] $0\CsrPlugin_mepc[31:0][21] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5444 CsrPlugin_mepc[22] DBusCachedPlugin_redoBranch_payload[22] $0\CsrPlugin_mepc[31:0][22] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5439 CsrPlugin_mepc[23] DBusCachedPlugin_redoBranch_payload[23] $0\CsrPlugin_mepc[31:0][23] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5434 CsrPlugin_mepc[24] DBusCachedPlugin_redoBranch_payload[24] $0\CsrPlugin_mepc[31:0][24] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5429 CsrPlugin_mepc[25] DBusCachedPlugin_redoBranch_payload[25] $0\CsrPlugin_mepc[31:0][25] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5424 CsrPlugin_mepc[26] DBusCachedPlugin_redoBranch_payload[26] $0\CsrPlugin_mepc[31:0][26] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5419 CsrPlugin_mepc[27] DBusCachedPlugin_redoBranch_payload[27] $0\CsrPlugin_mepc[31:0][27] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5414 CsrPlugin_mepc[28] DBusCachedPlugin_redoBranch_payload[28] $0\CsrPlugin_mepc[31:0][28] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5409 CsrPlugin_mepc[29] DBusCachedPlugin_redoBranch_payload[29] $0\CsrPlugin_mepc[31:0][29] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5950 CsrPlugin_mepc[30] DBusCachedPlugin_redoBranch_payload[30] $0\CsrPlugin_mepc[31:0][30] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5840 CsrPlugin_mepc[31] DBusCachedPlugin_redoBranch_payload[31] $0\CsrPlugin_mepc[31:0][31] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7849 $abc$27210$new_n5387 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n7849 +1111 1 +.names $abc$27210$new_n5856 DBusCachedPlugin_mmuBus_cmd_0_isStuck $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack[0:0] +10 1 +.names $abc$27210$new_n5851 $abc$27210$new_n4259 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5856 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory[0:0] +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5855 $abc$27210$new_n4258 $abc$27210$new_n5851 $abc$27210$new_n4259 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute[0:0] +0010 1 +0110 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5855 $abc$27210$new_n4258 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode[0:0] +10 1 +.names $abc$27210$new_n5868 $abc$27210$new_n4433 $0\CsrPlugin_interrupt_valid[0:0] +00 1 +.names $abc$27210$new_n7856 $abc$27210$new_n4438 $abc$27210$new_n4432 CsrPlugin_mstatus_MPP[0] $0\CsrPlugin_mstatus_MPP[1:0][0] +0000 1 +0001 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5339 $abc$27210$new_n5344 $abc$27210$new_n7857 $abc$27210$new_n7856 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_768 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n7857 +1111 1 +.names $abc$27210$new_n7856 $abc$27210$new_n4438 $abc$27210$new_n4432 CsrPlugin_mstatus_MPP[1] $0\CsrPlugin_mstatus_MPP[1:0][1] +0000 1 +0001 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7857 $abc$27210$new_n5366 $abc$27210$new_n7860 $0\CsrPlugin_mstatus_MPIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4432 $abc$27210$new_n4438 CsrPlugin_mstatus_MPIE CsrPlugin_mstatus_MIE $abc$27210$new_n7860 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$27210$new_n7857 $abc$27210$new_n5387 $abc$27210$new_n7862 $0\CsrPlugin_mstatus_MIE[0:0] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4438 CsrPlugin_mstatus_MPIE $abc$27210$new_n4432 CsrPlugin_mstatus_MIE $abc$27210$new_n7862 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_5_valid $abc$27210$new_n5075 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_5_exception $0\MmuPlugin_ports_1_cache_5_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5827 $abc$27210$new_n4259 decode_to_execute_IS_SFENCE_VMA2 execute_arbitration_isValid $abc$27210$new_n7864 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_4_valid $abc$27210$new_n5113 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_4_exception $0\MmuPlugin_ports_1_cache_4_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_3_valid $abc$27210$new_n5150 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_3_exception $0\MmuPlugin_ports_1_cache_3_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_2_valid $abc$27210$new_n5187 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_2_exception $0\MmuPlugin_ports_1_cache_2_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_1_valid $abc$27210$new_n5224 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_1_exception $0\MmuPlugin_ports_1_cache_1_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_0_valid $abc$27210$new_n5261 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_0_exception $0\MmuPlugin_ports_1_cache_0_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7871 $abc$27210$new_n5314 MmuPlugin_status_mprv $0\MmuPlugin_status_mprv[0:0] +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE $abc$27210$new_n4264 $abc$27210$new_n4259 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n7871 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7871 $abc$27210$new_n5304 MmuPlugin_status_mxr $0\MmuPlugin_status_mxr[0:0] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7871 $abc$27210$new_n5309 MmuPlugin_status_sum $0\MmuPlugin_status_sum[0:0] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[4] DebugPlugin_stepIt debug_bus_rsp_data[4] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[2] DebugPlugin_isPipBusy debug_bus_rsp_data[2] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[1] DebugPlugin_haltIt debug_bus_rsp_data[1] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[0] DebugPlugin_resetIt debug_bus_rsp_data[0] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[3] DebugPlugin_haltedByBreak debug_bus_rsp_data[3] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4320 IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] debug_bus_cmd_ready +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names memory_DivPlugin_div_counter_value[0] $abc$27210$new_n4261 $abc$27210$new_n4093 memory_DivPlugin_div_counter_valueNext[0] +010 1 +011 1 +101 1 +.names $abc$27210$new_n7882 memory_DivPlugin_div_counter_value[1] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n4904 memory_DivPlugin_div_counter_valueNext[1] +0110 1 +0111 1 +1000 1 +1010 1 +.names memory_DivPlugin_div_counter_value[0] $abc$27210$new_n4261 $abc$27210$new_n7882 +11 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck memory_DivPlugin_div_counter_value[2] $abc$27210$new_n7884 memory_DivPlugin_div_counter_valueNext[2] +101 1 +110 1 +.names memory_DivPlugin_div_counter_value[1] $abc$27210$new_n7882 $abc$27210$new_n7884 +11 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck memory_DivPlugin_div_counter_value[3] memory_DivPlugin_div_counter_value[2] $abc$27210$new_n7884 memory_DivPlugin_div_counter_valueNext[3] +1011 1 +1100 1 +1101 1 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck memory_DivPlugin_div_counter_value[4] memory_DivPlugin_div_counter_value[3] memory_DivPlugin_div_counter_value[2] $abc$27210$new_n7884 memory_DivPlugin_div_counter_valueNext[4] +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck memory_DivPlugin_div_counter_value[5] $abc$27210$new_n7888 $abc$27210$new_n4904 $abc$27210$new_n7882 memory_DivPlugin_div_counter_valueNext[5] +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names memory_DivPlugin_div_counter_value[4] memory_DivPlugin_div_counter_value[3] memory_DivPlugin_div_counter_value[2] $abc$27210$new_n7884 $abc$27210$new_n7888 +1111 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[0] _zz_14 lastStageRegFileWrite_payload_data[0] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[1] _zz_14 lastStageRegFileWrite_payload_data[1] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[2] _zz_14 lastStageRegFileWrite_payload_data[2] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[3] _zz_14 lastStageRegFileWrite_payload_data[3] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[4] _zz_14 lastStageRegFileWrite_payload_data[4] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[5] _zz_14 lastStageRegFileWrite_payload_data[5] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[6] _zz_14 lastStageRegFileWrite_payload_data[6] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[7] _zz_14 lastStageRegFileWrite_payload_data[7] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[8] _zz_14 lastStageRegFileWrite_payload_data[8] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[9] _zz_14 lastStageRegFileWrite_payload_data[9] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[10] _zz_14 lastStageRegFileWrite_payload_data[10] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[11] _zz_14 lastStageRegFileWrite_payload_data[11] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[12] _zz_14 lastStageRegFileWrite_payload_data[12] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[13] _zz_14 lastStageRegFileWrite_payload_data[13] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[14] _zz_14 lastStageRegFileWrite_payload_data[14] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[15] _zz_14 lastStageRegFileWrite_payload_data[15] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[16] _zz_14 lastStageRegFileWrite_payload_data[16] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[17] _zz_14 lastStageRegFileWrite_payload_data[17] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[18] _zz_14 lastStageRegFileWrite_payload_data[18] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[19] _zz_14 lastStageRegFileWrite_payload_data[19] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[20] _zz_14 lastStageRegFileWrite_payload_data[20] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[21] _zz_14 lastStageRegFileWrite_payload_data[21] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[22] _zz_14 lastStageRegFileWrite_payload_data[22] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[23] _zz_14 lastStageRegFileWrite_payload_data[23] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[24] _zz_14 lastStageRegFileWrite_payload_data[24] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[25] _zz_14 lastStageRegFileWrite_payload_data[25] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[26] _zz_14 lastStageRegFileWrite_payload_data[26] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[27] _zz_14 lastStageRegFileWrite_payload_data[27] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[28] _zz_14 lastStageRegFileWrite_payload_data[28] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[29] _zz_14 lastStageRegFileWrite_payload_data[29] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[30] _zz_14 lastStageRegFileWrite_payload_data[30] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[31] _zz_14 lastStageRegFileWrite_payload_data[31] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_14 lastStageRegFileWrite_payload_address[0] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_14 lastStageRegFileWrite_payload_address[1] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_14 lastStageRegFileWrite_payload_address[2] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_14 lastStageRegFileWrite_payload_address[3] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_14 lastStageRegFileWrite_payload_address[4] +10 1 +.names _zz_14 HazardSimplePlugin_writeBackWrites_valid _zz_1 +01 1 +10 1 +11 1 +.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_valueNext[0] +01 1 +10 1 +.names MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_valueNext[1] +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_valueNext[2] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4455 IBusCachedPlugin_predictionJumpInterface_payload[29] +000 1 +011 1 +101 1 +110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 IBusCachedPlugin_predictionJumpInterface_payload[30] +000 1 +011 1 +101 1 +110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 IBusCachedPlugin_predictionJumpInterface_payload[31] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names dataCache_1.loader_counter_willOverflow dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4095 $abc$27210$new_n4100 dataCache_1._zz_2 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[5] dataCache_1.stageB_flusher_counter[0] dataCache_1.tagsWriteCmd_payload_address[0] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[6] dataCache_1.stageB_flusher_counter[1] dataCache_1.tagsWriteCmd_payload_address[1] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[7] dataCache_1.stageB_flusher_counter[2] dataCache_1.tagsWriteCmd_payload_address[2] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[8] dataCache_1.stageB_flusher_counter[3] dataCache_1.tagsWriteCmd_payload_address[3] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[9] dataCache_1.stageB_flusher_counter[4] dataCache_1.tagsWriteCmd_payload_address[4] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[10] dataCache_1.stageB_flusher_counter[5] dataCache_1.tagsWriteCmd_payload_address[5] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[11] dataCache_1.stageB_flusher_counter[6] dataCache_1.tagsWriteCmd_payload_address[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[0] dBus_cmd_payload_data[0] dataCache_1.dataWriteCmd_payload_data[0] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[1] dBus_cmd_payload_data[1] dataCache_1.dataWriteCmd_payload_data[1] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[2] dBus_cmd_payload_data[2] dataCache_1.dataWriteCmd_payload_data[2] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[3] dBus_cmd_payload_data[3] dataCache_1.dataWriteCmd_payload_data[3] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[4] dBus_cmd_payload_data[4] dataCache_1.dataWriteCmd_payload_data[4] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[5] dBus_cmd_payload_data[5] dataCache_1.dataWriteCmd_payload_data[5] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[6] dBus_cmd_payload_data[6] dataCache_1.dataWriteCmd_payload_data[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[7] dBus_cmd_payload_data[7] dataCache_1.dataWriteCmd_payload_data[7] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[8] dBus_cmd_payload_data[8] dataCache_1.dataWriteCmd_payload_data[8] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[9] dBus_cmd_payload_data[9] dataCache_1.dataWriteCmd_payload_data[9] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[10] dBus_cmd_payload_data[10] dataCache_1.dataWriteCmd_payload_data[10] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[11] dBus_cmd_payload_data[11] dataCache_1.dataWriteCmd_payload_data[11] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[12] dBus_cmd_payload_data[12] dataCache_1.dataWriteCmd_payload_data[12] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[13] dBus_cmd_payload_data[13] dataCache_1.dataWriteCmd_payload_data[13] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[14] dBus_cmd_payload_data[14] dataCache_1.dataWriteCmd_payload_data[14] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[15] dBus_cmd_payload_data[15] dataCache_1.dataWriteCmd_payload_data[15] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[16] dBus_cmd_payload_data[16] dataCache_1.dataWriteCmd_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[17] dBus_cmd_payload_data[17] dataCache_1.dataWriteCmd_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[18] dBus_cmd_payload_data[18] dataCache_1.dataWriteCmd_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[19] dBus_cmd_payload_data[19] dataCache_1.dataWriteCmd_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[20] dBus_cmd_payload_data[20] dataCache_1.dataWriteCmd_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[21] dBus_cmd_payload_data[21] dataCache_1.dataWriteCmd_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[22] dBus_cmd_payload_data[22] dataCache_1.dataWriteCmd_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[23] dBus_cmd_payload_data[23] dataCache_1.dataWriteCmd_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[24] dBus_cmd_payload_data[24] dataCache_1.dataWriteCmd_payload_data[24] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[25] dBus_cmd_payload_data[25] dataCache_1.dataWriteCmd_payload_data[25] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[26] dBus_cmd_payload_data[26] dataCache_1.dataWriteCmd_payload_data[26] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[27] dBus_cmd_payload_data[27] dataCache_1.dataWriteCmd_payload_data[27] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[28] dBus_cmd_payload_data[28] dataCache_1.dataWriteCmd_payload_data[28] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[29] dBus_cmd_payload_data[29] dataCache_1.dataWriteCmd_payload_data[29] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[30] dBus_cmd_payload_data[30] dataCache_1.dataWriteCmd_payload_data[30] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[31] dBus_cmd_payload_data[31] dataCache_1.dataWriteCmd_payload_data[31] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[0] dBus_cmd_payload_size[2] dBus_cmd_payload_address[0] +10 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[1] dBus_cmd_payload_size[2] dBus_cmd_payload_address[1] +10 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[2] dBus_cmd_payload_size[2] dBus_cmd_payload_address[2] +10 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[3] dBus_cmd_payload_size[2] dBus_cmd_payload_address[3] +10 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[4] dBus_cmd_payload_size[2] dBus_cmd_payload_address[4] +10 1 +.names dataCache_1.stageB_request_size[0] dBus_cmd_payload_size[2] dBus_cmd_payload_size[0] +01 1 +10 1 +11 1 +.names dataCache_1.stageB_request_size[1] dBus_cmd_payload_size[2] dBus_cmd_payload_size[1] +10 1 +.names dataCache_1.stageB_flusher_start $abc$27210$new_n4234 dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n6007 dataCache_1.stageB_flusher_counter[6] $abc$27210$flatten\dataCache_1.$0\stageB_flusher_counter[7:0][7] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] decode_INSTRUCTION_ANTICIPATED[15] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] decode_INSTRUCTION_ANTICIPATED[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] decode_INSTRUCTION_ANTICIPATED[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] decode_INSTRUCTION_ANTICIPATED[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] decode_INSTRUCTION_ANTICIPATED[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] decode_INSTRUCTION_ANTICIPATED[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] decode_INSTRUCTION_ANTICIPATED[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] decode_INSTRUCTION_ANTICIPATED[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] decode_INSTRUCTION_ANTICIPATED[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] decode_INSTRUCTION_ANTICIPATED[24] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[0] +01 1 +10 1 +.names dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[1] +011 1 +100 1 +101 1 +110 1 +.names dataCache_1.loader_counter_value[2] dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[2] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names execute_to_memory_PREDICTION_CONTEXT_line_history[0] execute_to_memory_BRANCH_DO memory_arbitration_isValid _zz__zz_3_port[1] +011 1 +100 1 +101 1 +110 1 +.names execute_to_memory_PREDICTION_CONTEXT_line_history[0] _zz__zz_3_port[0] +0 1 +.names $abc$27210$new_n8193 MmuPlugin_ports_1_cache_2_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_ports_1_cache_2_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n7999 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8195 MmuPlugin_ports_1_cache_4_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_4_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n8001 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names $abc$27210$new_n8001 MmuPlugin_ports_1_cache_4_superPage $abc$27210$new_n8002 +10 1 +.names $abc$27210$new_n3971 MmuPlugin_ports_1_cache_4_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_4_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n8003 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n3994 MmuPlugin_ports_1_cache_3_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_3_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n8006 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8006 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_ports_1_cache_3_virtualAddress_0[7] MmuPlugin_ports_1_cache_3_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$new_n8007 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8007 MmuPlugin_ports_1_cache_3_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n8008 +100 1 +111 1 +.names $abc$27210$new_n4013 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_5_virtualAddress_0[5] MmuPlugin_ports_1_cache_5_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n8009 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4016 MmuPlugin_ports_1_cache_5_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n8010 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n8010 $abc$27210$new_n8009 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_ports_1_cache_5_virtualAddress_0[7] MmuPlugin_ports_1_cache_5_superPage $abc$27210$new_n8011 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$27210$new_n4037 MmuPlugin_ports_1_cache_1_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_1_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n8013 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4369 MmuPlugin_ports_1_cache_4_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8015 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4368 $abc$27210$new_n4055 $abc$27210$new_n3985 MmuPlugin_ports_1_cache_4_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n8016 +11100 1 +11111 1 +.names $abc$27210$new_n8016 $abc$27210$new_n8015 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_4_virtualAddress_1[7] $abc$27210$new_n8002 $abc$27210$new_n8017 +11000 1 +11110 1 +.names execute_to_memory_INSTRUCTION[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] execute_to_memory_INSTRUCTION[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n8021 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n8021 execute_to_memory_INSTRUCTION[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] execute_to_memory_INSTRUCTION[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n8022 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8022 execute_to_memory_INSTRUCTION[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8023 +100 1 +111 1 +.names MmuPlugin_ports_1_cache_3_valid MmuPlugin_ports_1_cache_3_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8025 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_5_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] MmuPlugin_ports_1_cache_5_virtualAddress_1[8] $abc$27210$new_n4027 $abc$27210$new_n8029 +00000 1 +00110 1 +11000 1 +11110 1 +.names MmuPlugin_ports_1_cache_5_valid MmuPlugin_ports_1_cache_5_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_5_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n8030 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n4362 MmuPlugin_ports_1_cache_2_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_ports_1_cache_2_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8032 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n4363 MmuPlugin_ports_1_cache_2_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8033 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4359 $abc$27210$new_n8032 $abc$27210$new_n8033 $abc$27210$new_n3956 $abc$27210$new_n8034 +1110 1 +.names $abc$27210$new_n4387 MmuPlugin_ports_1_cache_0_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8035 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4504 DBusCachedPlugin_redoBranch_payload[22] IBusCachedPlugin_predictionJumpInterface_payload[22] $abc$27210$new_n4434 $abc$27210$new_n8038 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4505 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n8038 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21961 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4510 DBusCachedPlugin_redoBranch_payload[21] IBusCachedPlugin_predictionJumpInterface_payload[21] $abc$27210$new_n4434 $abc$27210$new_n8040 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4511 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] $abc$27210$new_n8040 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21963 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4517 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[20] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[20] $abc$27210$new_n8042 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8042 $abc$27210$new_n4447 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8043 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8043 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$new_n8044 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] $abc$27210$new_n8044 $abc$27210$auto$rtlil.cc:2693:MuxGate$21965 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4524 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[19] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[19] $abc$27210$new_n8046 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8046 $abc$27210$new_n4447 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8047 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8047 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n8048 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] $abc$27210$new_n8048 $abc$27210$auto$rtlil.cc:2693:MuxGate$21967 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4531 DBusCachedPlugin_redoBranch_payload[18] IBusCachedPlugin_predictionJumpInterface_payload[18] $abc$27210$new_n4434 $abc$27210$new_n8050 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4532 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8050 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21969 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4537 DBusCachedPlugin_redoBranch_payload[17] IBusCachedPlugin_predictionJumpInterface_payload[17] $abc$27210$new_n4434 $abc$27210$new_n8052 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4538 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] $abc$27210$new_n8052 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21971 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4544 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[16] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[16] $abc$27210$new_n8054 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8054 $abc$27210$new_n4448 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8055 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8055 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n8056 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] $abc$27210$new_n8056 $abc$27210$auto$rtlil.cc:2693:MuxGate$21973 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4551 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[15] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[15] $abc$27210$new_n8058 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8058 $abc$27210$new_n4448 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8059 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8059 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n8060 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] $abc$27210$new_n8060 $abc$27210$auto$rtlil.cc:2693:MuxGate$21975 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4558 DBusCachedPlugin_redoBranch_payload[14] IBusCachedPlugin_predictionJumpInterface_payload[14] $abc$27210$new_n4434 $abc$27210$new_n8062 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4559 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8062 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21977 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4564 DBusCachedPlugin_redoBranch_payload[13] IBusCachedPlugin_predictionJumpInterface_payload[13] $abc$27210$new_n4434 $abc$27210$new_n8064 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4565 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] $abc$27210$new_n8064 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21979 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4571 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[12] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[12] $abc$27210$new_n8066 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8066 $abc$27210$new_n4449 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n8067 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8067 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n8068 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] $abc$27210$new_n8068 $abc$27210$auto$rtlil.cc:2693:MuxGate$21981 +010 1 +011 1 +101 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4728 $abc$27210$new_n4722 $abc$27210$new_n4714 $abc$27210$new_n8071 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$27210$new_n4711 $abc$27210$new_n4721 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4712 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n8074 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n8078 IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$new_n4705 $abc$27210$new_n8074 $abc$27210$new_n8075 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n8077 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8077 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n8078 +00 1 +01 1 +11 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_41 _zz__zz_decode_IS_CSR_21 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n8079 +01100 1 +01101 1 +10001 1 +10011 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$new_n8079 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n8080 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n8081 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] $abc$27210$new_n8081 DBusCachedPlugin_exceptionBus_payload_badAddr[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23089 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n8083 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] $abc$27210$new_n8083 DBusCachedPlugin_exceptionBus_payload_badAddr[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23091 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4279 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$new_n8086 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n4763 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n8088 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4761 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n8091 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8091 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n8092 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n8094 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] $abc$27210$new_n8094 DBusCachedPlugin_exceptionBus_payload_badAddr[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23101 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n8096 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] $abc$27210$new_n8096 DBusCachedPlugin_exceptionBus_payload_badAddr[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23105 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n8098 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] $abc$27210$new_n8098 DBusCachedPlugin_exceptionBus_payload_badAddr[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23107 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n8100 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] $abc$27210$new_n8100 DBusCachedPlugin_exceptionBus_payload_badAddr[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23121 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[11] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] $abc$27210$new_n8102 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] $abc$27210$new_n8102 DBusCachedPlugin_exceptionBus_payload_badAddr[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23123 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[9] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] $abc$27210$new_n8104 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[9] $abc$27210$new_n8104 DBusCachedPlugin_exceptionBus_payload_badAddr[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23127 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[4] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n8106 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[4] $abc$27210$new_n8106 DBusCachedPlugin_exceptionBus_payload_badAddr[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23137 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 _zz__zz_decode_RS2_2[14] $abc$27210$new_n5745 MmuPlugin_dBusAccess_rsp_payload_data[14] $abc$27210$new_n8108 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n8108 DBusCachedPlugin_exceptionBus_payload_badAddr[14] $abc$27210$new_n5647 HazardSimplePlugin_writeBackWrites_payload_data[14] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 _zz__zz_decode_RS2_2[12] $abc$27210$new_n5757 MmuPlugin_dBusAccess_rsp_payload_data[12] $abc$27210$new_n8110 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n8110 DBusCachedPlugin_exceptionBus_payload_badAddr[12] $abc$27210$new_n5647 HazardSimplePlugin_writeBackWrites_payload_data[12] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 _zz__zz_decode_RS2_2[10] $abc$27210$new_n5769 MmuPlugin_dBusAccess_rsp_payload_data[10] $abc$27210$new_n8112 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n8112 DBusCachedPlugin_exceptionBus_payload_badAddr[10] $abc$27210$new_n5647 HazardSimplePlugin_writeBackWrites_payload_data[10] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[21] dBus_rsp_payload_data[5] dataCache_1.stageB_dataMux[5] $abc$27210$new_n8114 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[0] DBusCachedPlugin_exceptionBus_payload_badAddr[5] $abc$27210$new_n8114 MmuPlugin_dBusAccess_rsp_payload_data[13] $abc$27210$new_n8115 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[31] _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] $abc$27210$new_n8116 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] $abc$27210$new_n8116 DBusCachedPlugin_exceptionBus_payload_badAddr[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24643 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4903 execute_to_memory_INSTRUCTION[13] memory_DivPlugin_div_result[31] memory_DivPlugin_div_stage_0_remainderShifted memory_DivPlugin_accumulator[31] $abc$27210$new_n8118 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4869 $abc$27210$new_n4902 $abc$27210$new_n4901 $abc$27210$new_n4900 $abc$27210$new_n8119 +1000 1 +.names $abc$27210$new_n8118 $abc$27210$new_n8119 $abc$27210$new_n4903 $abc$27210$new_n4905 _zz_memory_DivPlugin_div_result_5 $abc$27210$auto$rtlil.cc:2693:MuxGate$24649 +00101 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4087 MmuPlugin_status_mxr MmuPlugin_ports_1_cache_2_allowRead MmuPlugin_ports_1_cache_3_allowExecute MmuPlugin_ports_1_cache_2_allowExecute $abc$27210$new_n8121 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +.names $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_allowRead $abc$27210$new_n5988 MmuPlugin_ports_1_cache_1_allowExecute MmuPlugin_status_mxr $abc$27210$new_n8122 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names $abc$27210$new_n4088 $abc$27210$new_n8121 $abc$27210$new_n8122 MmuPlugin_ports_1_cache_3_allowRead $abc$27210$new_n4087 $abc$27210$new_n8123 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 $abc$27210$new_n5998 DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31] $abc$27210$new_n8124 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4088 $abc$27210$new_n3943 $abc$27210$new_n4085 $abc$27210$new_n8124 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31] $abc$27210$new_n8125 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n8125 $abc$27210$new_n4090 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31] $abc$27210$new_n4085 $abc$27210$new_n8126 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6802 $abc$27210$new_n6732 _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n8127 +00000 1 +01100 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n5953 $abc$27210$new_n8127 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n8128 +00000 1 +00001 1 +00010 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8128 $abc$27210$new_n4264 $abc$27210$new_n5951 $abc$27210$new_n8129 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8129 $abc$27210$new_n6806 $abc$27210$new_n8130 +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n5412 $abc$27210$new_n6803 $abc$27210$new_n6812 $abc$27210$new_n6797 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8131 +00010 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8131 $abc$27210$new_n4264 $abc$27210$new_n5410 $abc$27210$new_n6813 $abc$27210$new_n8132 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +11000 1 +11010 1 +11110 1 +.names $abc$27210$new_n4327 $abc$27210$new_n5838 $abc$27210$new_n8132 MmuPlugin_shared_pteBuffer_PPN1[7] MmuPlugin_satp_ppn[17] $abc$27210$new_n8133 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5417 $abc$27210$new_n6803 $abc$27210$new_n6799 $abc$27210$new_n6733 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8134 +00000 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8134 $abc$27210$new_n4264 $abc$27210$new_n5415 $abc$27210$new_n6819 $abc$27210$new_n8135 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +11000 1 +11010 1 +11110 1 +.names $abc$27210$new_n4327 $abc$27210$new_n5838 $abc$27210$new_n8135 MmuPlugin_shared_pteBuffer_PPN1[6] MmuPlugin_satp_ppn[16] $abc$27210$new_n8136 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5427 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6796 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8137 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n8137 $abc$27210$new_n6795 $abc$27210$new_n6734 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8138 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01101 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6833 $abc$27210$new_n6832 $abc$27210$new_n8138 $abc$27210$new_n6805 $abc$27210$new_n8139 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n5447 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6788 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8140 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n8140 $abc$27210$new_n6787 $abc$27210$new_n6736 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8141 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01101 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8141 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5445 $abc$27210$new_n8142 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +.names $abc$27210$new_n5322 $abc$27210$new_n6803 $abc$27210$new_n6775 $abc$27210$new_n6739 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8143 +00000 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8143 $abc$27210$new_n4264 $abc$27210$new_n5320 $abc$27210$new_n6894 $abc$27210$new_n8144 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +11000 1 +11010 1 +11110 1 +.names $abc$27210$new_n4327 $abc$27210$new_n5838 $abc$27210$new_n8144 MmuPlugin_shared_pteBuffer_PPN0[4] MmuPlugin_satp_ppn[4] $abc$27210$new_n8145 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5332 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6771 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8146 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6772 $abc$27210$new_n6740 $abc$27210$new_n8146 $abc$27210$new_n8147 +00000 1 +00001 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8147 $abc$27210$new_n4264 $abc$27210$new_n5330 $abc$27210$new_n8148 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8148 $abc$27210$new_n6907 $abc$27210$new_n8149 +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n5352 $abc$27210$new_n6803 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6763 $abc$27210$new_n8150 +01000 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8150 $abc$27210$new_n6931 $abc$27210$new_n8151 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8151 $abc$27210$new_n6933 $abc$27210$new_n4264 $abc$27210$new_n5353 $abc$27210$new_n8152 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5362 $abc$27210$new_n6803 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6759 $abc$27210$new_n8153 +01000 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8153 $abc$27210$new_n6945 $abc$27210$new_n8154 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8154 $abc$27210$new_n6947 $abc$27210$new_n4264 $abc$27210$new_n5363 $abc$27210$new_n8155 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5373 $abc$27210$new_n6803 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6755 $abc$27210$new_n8156 +01000 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8156 $abc$27210$new_n6959 $abc$27210$new_n8157 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8157 $abc$27210$new_n6961 $abc$27210$new_n4264 $abc$27210$new_n5374 $abc$27210$new_n8158 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5385 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6429 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8159 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8159 $abc$27210$new_n6973 $abc$27210$new_n8160 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8160 $abc$27210$new_n6975 $abc$27210$new_n4264 $abc$27210$new_n5383 $abc$27210$new_n8161 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$27210$new_n6089 $abc$27210$new_n6996 $abc$27210$new_n7001 $abc$27210$new_n8162 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4264 $abc$27210$new_n4327 $abc$27210$new_n8162 $abc$27210$new_n5405 $abc$27210$new_n8163 +0010 1 +0011 1 +1000 1 +1010 1 +.names $abc$27210$new_n7080 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] HazardSimplePlugin_writeBackBuffer_payload_address[1] HazardSimplePlugin_writeBackBuffer_payload_address[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n8164 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n8164 IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] HazardSimplePlugin_writeBackBuffer_payload_address[3] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8165 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n7086 HazardSimplePlugin_writeBackWrites_payload_address[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n8166 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8166 HazardSimplePlugin_writeBackWrites_payload_address[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n8167 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8167 HazardSimplePlugin_writeBackWrites_payload_address[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8168 +100 1 +111 1 +.names $abc$27210$new_n5843 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6999 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8169 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8169 $abc$27210$new_n6997 $abc$27210$new_n8170 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8170 $abc$27210$new_n7631 $abc$27210$new_n4264 $abc$27210$new_n5841 $abc$27210$new_n8171 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7714 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[15] $abc$27210$new_n4128 $abc$27210$new_n4174 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[8] $abc$27210$new_n8172 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8172 $abc$27210$new_n8216 dataCache_1.stageB_waysHit $abc$27210$new_n4094 $abc$27210$new_n4100 $abc$27210$auto$rtlil.cc:2693:MuxGate$24795 +00110 1 +01110 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[14] $abc$27210$new_n4134 $abc$27210$new_n7712 $abc$27210$new_n4111 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] $abc$27210$new_n8175 +00000 1 +00001 1 +00010 1 +11000 1 +11001 1 +11010 1 +.names dataCache_1.dataWriteCmd_payload_address[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] dataCache_1.dataWriteCmd_payload_address[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] $abc$27210$new_n8178 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n6003 dBus_cmd_payload_mask[2] dBus_cmd_payload_mask[1] dataCache_1.stageA_mask[1] dataCache_1.stageA_mask[2] $abc$27210$new_n8179 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names $abc$27210$new_n6003 dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[3] dataCache_1.stageA_mask[3] dataCache_1.stageA_mask[0] $abc$27210$new_n8180 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names $abc$27210$new_n8178 $abc$27210$new_n8179 $abc$27210$new_n8180 $abc$27210$new_n8181 +100 1 +101 1 +110 1 +.names $abc$27210$new_n6003 $abc$27210$new_n6087 dBus_cmd_payload_mask[3] dBus_cmd_payload_mask[2] $abc$27210$new_n7756 $abc$27210$new_n8182 +00000 1 +00001 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n7751 dataCache_1.dataReadCmd_payload[2] dataCache_1.dataWriteCmd_payload_address[2] dataCache_1.dataReadCmd_payload[1] dataCache_1.dataWriteCmd_payload_address[1] $abc$27210$new_n8183 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8183 dataCache_1.dataReadCmd_payload[3] dBus_cmd_payload_address[5] $abc$27210$new_n7755 $abc$27210$new_n8182 $abc$27210$new_n8184 +10000 1 +10001 1 +10010 1 +11100 1 +11101 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_1_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_1_virtualAddress_0[3] $abc$27210$new_n4033 $abc$27210$new_n8185 +00000 1 +00110 1 +11000 1 +11110 1 +.names $abc$27210$new_n8185 MmuPlugin_ports_1_cache_1_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_1_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n8186 +10000 1 +10011 1 +11100 1 +11111 1 +.names MmuPlugin_ports_1_cache_0_valid DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_0_virtualAddress_1[3] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n8188 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_2_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n8191 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n8191 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_2_virtualAddress_0[4] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n8192 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n8192 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_ports_1_cache_2_virtualAddress_0[8] MmuPlugin_ports_1_cache_2_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$new_n8193 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_4_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_4_virtualAddress_0[0] $abc$27210$new_n3972 $abc$27210$new_n8194 +00000 1 +00110 1 +11000 1 +11110 1 +.names $abc$27210$new_n8003 $abc$27210$new_n8194 MmuPlugin_ports_1_cache_4_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n8195 +1100 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_ports_1_cache_1_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_1_virtualAddress_1[6] $abc$27210$new_n4046 $abc$27210$new_n8196 +00000 1 +00110 1 +11000 1 +11110 1 +.names MmuPlugin_ports_1_cache_1_valid MmuPlugin_ports_1_cache_1_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_1_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n8197 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8025 MmuPlugin_ports_1_cache_3_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8199 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n8029 MmuPlugin_ports_1_cache_5_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n8201 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8030 $abc$27210$new_n4023 $abc$27210$new_n4020 MmuPlugin_ports_1_cache_5_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n8202 +11100 1 +11111 1 +.names $abc$27210$new_n8201 $abc$27210$new_n8202 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_ports_1_cache_5_virtualAddress_1[4] $abc$27210$new_n8011 $abc$27210$new_n8203 +11000 1 +11110 1 +.names $abc$27210$new_n4736 $abc$27210$new_n4735 $abc$27210$new_n4706 $abc$27210$new_n4722 $abc$27210$new_n4731 $abc$27210$new_n8204 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4725 $abc$27210$new_n4266 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n8204 $abc$27210$new_n8080 $abc$27210$new_n8206 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names $abc$27210$new_n8206 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n8071 _zz__zz_decode_IS_CSR_41 $abc$27210$new_n4740 $abc$27210$new_n8207 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n8207 $abc$27210$new_n8075 $abc$27210$new_n4722 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4723 $abc$27210$new_n8208 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4280 $abc$27210$new_n4275 $abc$27210$new_n4274 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] $abc$27210$new_n8209 +00000 1 +00010 1 +00011 1 +.names $abc$27210$new_n8209 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n8210 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8210 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n8211 +100 1 +111 1 +.names $abc$27210$new_n4764 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n8212 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8211 $abc$27210$new_n8092 $abc$27210$new_n8088 $abc$27210$new_n8086 $abc$27210$new_n8212 $abc$27210$new_n8213 +11111 1 +.names $abc$27210$new_n7721 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[3] $abc$27210$new_n4204 $abc$27210$new_n4210 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[2] $abc$27210$new_n8214 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n7723 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[17] $abc$27210$new_n4116 $abc$27210$new_n4168 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[9] $abc$27210$new_n8215 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8175 $abc$27210$new_n7718 $abc$27210$new_n7715 $abc$27210$new_n8215 $abc$27210$new_n8214 $abc$27210$new_n8216 +11111 1 +.names $abc$27210$new_n8197 MmuPlugin_ports_1_cache_1_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_1_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8217 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8196 $abc$27210$new_n4048 $abc$27210$new_n8217 MmuPlugin_ports_1_cache_1_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8218 +11100 1 +11111 1 +.names $abc$27210$new_n8218 MmuPlugin_ports_1_cache_1_superPage $abc$27210$new_n8186 $abc$27210$new_n8013 $abc$27210$new_n8219 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n8188 MmuPlugin_ports_1_cache_0_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_0_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8220 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8035 MmuPlugin_ports_1_cache_0_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8222 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8220 MmuPlugin_ports_1_cache_0_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_0_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n8223 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n4049 $abc$27210$new_n8223 $abc$27210$new_n8222 $abc$27210$new_n4370 $abc$27210$new_n8224 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n4333 MmuPlugin_ports_1_cache_3_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8225 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8199 MmuPlugin_ports_1_cache_3_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_3_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n8226 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8226 $abc$27210$new_n8225 $abc$27210$new_n3990 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] $abc$27210$new_n8227 +11000 1 +11001 1 +11011 1 +.subckt dff C=clk D=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid Q=IBusCachedPlugin_cache._zz_when_InstructionCache_l342 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24235 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[0] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24233 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[1] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24231 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[2] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24229 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[3] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24227 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[4] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24225 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[5] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24867 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[6] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$flatten\IBusCachedPlugin_cache.$procmux$1907_Y[7] Q=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24223 Q=CsrPlugin_mcause_exceptionCode[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24881 Q=CsrPlugin_mcause_exceptionCode[3] +.subckt dffr C=clk D=$abc$27210$flatten\dataCache_1.$0\stageB_flusher_counter[7:0][7] Q=dataCache_1.stageB_flusher_counter[7] R=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24221 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24219 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24217 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24215 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24213 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24211 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24209 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24207 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24205 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24203 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24201 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24199 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24197 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24195 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24193 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24191 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24189 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24187 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24185 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24183 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24181 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24179 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24177 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24175 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24173 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24171 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24169 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24167 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24165 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24163 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24161 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24655 Q=memory_DivPlugin_div_stage_0_remainderShifted +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24641 Q=CsrPlugin_interrupt_code[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24637 Q=CsrPlugin_interrupt_code[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24159 Q=CsrPlugin_mcause_exceptionCode[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24879 Q=CsrPlugin_mcause_exceptionCode[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24903 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] +.subckt dffr C=clk D=$0\DebugPlugin_haltIt[0:0] Q=DebugPlugin_haltIt R=debugReset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24791 Q=DebugPlugin_resetIt R=debugReset +.subckt dffr C=clk D=$0\DebugPlugin_godmode[0:0] Q=DebugPlugin_godmode R=debugReset +.subckt dffr C=clk D=$0\DebugPlugin_haltedByBreak[0:0] Q=DebugPlugin_haltedByBreak R=debugReset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24789 Q=DebugPlugin_stepIt R=debugReset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24787 Q=DebugPlugin_debugUsed R=debugReset +.subckt dff C=clk D=$0\DebugPlugin_isPipBusy[0:0] Q=DebugPlugin_isPipBusy +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24785 Q=DebugPlugin_disableEbreak R=debugReset +.subckt dff C=clk D=debug_bus_cmd_payload_address[2] Q=_zz_when_DebugPlugin_l257 +.subckt dff C=clk D=DebugPlugin_resetIt Q=debug_resetOut +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24155 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24153 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24151 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24149 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24147 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24145 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24143 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24141 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24139 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24137 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24135 Q=execute_to_memory_PC[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24133 Q=execute_to_memory_PC[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24131 Q=execute_to_memory_PC[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24129 Q=execute_to_memory_PC[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24127 Q=execute_to_memory_PC[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24125 Q=execute_to_memory_PC[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24123 Q=execute_to_memory_PC[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24121 Q=execute_to_memory_PC[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24119 Q=execute_to_memory_PC[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24117 Q=execute_to_memory_PC[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24115 Q=execute_to_memory_PC[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24113 Q=execute_to_memory_PC[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24111 Q=execute_to_memory_PC[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24109 Q=execute_to_memory_PC[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24107 Q=execute_to_memory_PC[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24105 Q=execute_to_memory_PC[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24103 Q=execute_to_memory_PC[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24101 Q=execute_to_memory_PC[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24099 Q=execute_to_memory_PC[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24895 Q=execute_to_memory_PC[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24783 Q=_zz_decode_PREDICTION_CONTEXT_hazard_2 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24097 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24095 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24093 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24091 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24089 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24087 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24085 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24083 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24081 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24781 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24779 Q=_zz_decode_PREDICTION_CONTEXT_hazard_4 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24079 Q=_zz_decode_PREDICTION_CONTEXT_line_history_2[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24777 Q=_zz_decode_PREDICTION_CONTEXT_line_history_2[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24077 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24075 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24073 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24071 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24069 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24067 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24065 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24063 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24061 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24059 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24057 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24055 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24053 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24051 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24049 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24047 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24045 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24043 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24041 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24039 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24037 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24035 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24033 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24031 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24029 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24027 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24025 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24023 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24021 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24883 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24019 Q=MmuPlugin_satp_asid[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24017 Q=MmuPlugin_satp_asid[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24015 Q=MmuPlugin_satp_asid[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24013 Q=MmuPlugin_satp_asid[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24011 Q=MmuPlugin_satp_asid[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24009 Q=MmuPlugin_satp_asid[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24007 Q=MmuPlugin_satp_asid[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24005 Q=MmuPlugin_satp_asid[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24775 Q=MmuPlugin_satp_asid[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24003 Q=MmuPlugin_satp_ppn[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24001 Q=MmuPlugin_satp_ppn[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23999 Q=MmuPlugin_satp_ppn[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23997 Q=MmuPlugin_satp_ppn[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23995 Q=MmuPlugin_satp_ppn[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23993 Q=MmuPlugin_satp_ppn[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23991 Q=MmuPlugin_satp_ppn[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23989 Q=MmuPlugin_satp_ppn[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23987 Q=MmuPlugin_satp_ppn[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23985 Q=MmuPlugin_satp_ppn[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23983 Q=MmuPlugin_satp_ppn[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23981 Q=MmuPlugin_satp_ppn[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23979 Q=MmuPlugin_satp_ppn[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23977 Q=MmuPlugin_satp_ppn[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23975 Q=MmuPlugin_satp_ppn[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23973 Q=MmuPlugin_satp_ppn[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23971 Q=MmuPlugin_satp_ppn[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23969 Q=MmuPlugin_satp_ppn[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23967 Q=MmuPlugin_satp_ppn[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23965 Q=MmuPlugin_satp_ppn[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23963 Q=MmuPlugin_satp_ppn[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24773 Q=MmuPlugin_satp_ppn[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24771 Q=MmuPlugin_ports_1_cache_0_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24769 Q=MmuPlugin_ports_1_cache_0_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23961 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23959 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23957 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23955 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23953 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23951 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23949 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23947 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23945 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24767 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23943 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23941 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23939 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23937 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23935 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23933 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23931 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23929 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23927 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24765 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23925 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23923 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23921 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23919 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23917 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23915 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23913 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23911 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23909 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24763 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23907 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23905 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23903 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23901 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23899 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23897 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23895 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23893 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23891 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24761 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24759 Q=MmuPlugin_ports_1_cache_0_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24757 Q=MmuPlugin_ports_1_cache_0_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24755 Q=MmuPlugin_ports_1_cache_0_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24753 Q=MmuPlugin_ports_1_cache_1_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24751 Q=MmuPlugin_ports_1_cache_1_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23889 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23887 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23885 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23883 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23881 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23879 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23877 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23875 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23873 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24749 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23871 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23869 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23867 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23865 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23863 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23861 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23859 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23857 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23855 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24747 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23853 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23851 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23849 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23847 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23845 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23843 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23841 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23839 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23837 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24745 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23835 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23833 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23831 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23829 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23827 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23825 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23823 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23821 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23819 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24743 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24741 Q=MmuPlugin_ports_1_cache_1_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24739 Q=MmuPlugin_ports_1_cache_1_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24737 Q=MmuPlugin_ports_1_cache_1_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24735 Q=MmuPlugin_ports_1_cache_2_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24733 Q=MmuPlugin_ports_1_cache_2_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23817 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23815 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23813 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23811 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23809 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23807 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23805 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23803 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23801 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24731 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23799 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23797 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23795 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23793 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23791 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23789 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23787 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23785 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23783 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24729 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23781 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23779 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23777 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23775 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23773 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23771 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23769 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23767 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23765 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24727 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23763 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23761 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23759 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23757 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23755 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23753 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23751 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23749 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23747 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24725 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24723 Q=MmuPlugin_ports_1_cache_2_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24721 Q=MmuPlugin_ports_1_cache_2_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24719 Q=MmuPlugin_ports_1_cache_2_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24717 Q=MmuPlugin_ports_1_cache_3_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24715 Q=MmuPlugin_ports_1_cache_3_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23745 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23743 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23741 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23739 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23737 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23735 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23733 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23731 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23729 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24713 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23727 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23725 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23723 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23721 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23719 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23717 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23715 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23713 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23711 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24711 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23709 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23707 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23705 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23703 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23701 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23699 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23697 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23695 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23693 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24709 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23691 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23689 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23687 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23685 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23683 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23681 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23679 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23677 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23675 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24707 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24705 Q=MmuPlugin_ports_1_cache_3_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24703 Q=MmuPlugin_ports_1_cache_3_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24701 Q=MmuPlugin_ports_1_cache_3_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24699 Q=MmuPlugin_ports_1_cache_4_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24697 Q=MmuPlugin_ports_1_cache_4_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23673 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23671 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23669 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23667 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23665 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23663 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23661 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23659 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23657 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24695 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23655 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23653 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23651 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23649 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23647 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23645 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23643 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23641 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23639 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24693 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23637 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23635 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23633 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23631 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23629 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23627 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23625 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23623 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23621 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24691 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23619 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23617 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23615 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23613 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23611 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23609 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23607 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23605 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23603 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24689 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24687 Q=MmuPlugin_ports_1_cache_4_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24685 Q=MmuPlugin_ports_1_cache_4_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24683 Q=MmuPlugin_ports_1_cache_4_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24681 Q=MmuPlugin_ports_1_cache_5_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24679 Q=MmuPlugin_ports_1_cache_5_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23601 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23599 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23597 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23595 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23593 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23591 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23589 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23587 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23585 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24677 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23583 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23581 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23579 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23577 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23575 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23573 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23571 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23569 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23567 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24675 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23565 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23563 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23561 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23559 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23557 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23555 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23553 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23551 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23549 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24673 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23547 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23545 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23543 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23541 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23539 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23537 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23535 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23533 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23531 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24671 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24669 Q=MmuPlugin_ports_1_cache_5_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24667 Q=MmuPlugin_ports_1_cache_5_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24665 Q=MmuPlugin_ports_1_cache_5_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23529 Q=MmuPlugin_shared_vpn_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23527 Q=MmuPlugin_shared_vpn_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23525 Q=MmuPlugin_shared_vpn_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23523 Q=MmuPlugin_shared_vpn_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23521 Q=MmuPlugin_shared_vpn_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23519 Q=MmuPlugin_shared_vpn_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23517 Q=MmuPlugin_shared_vpn_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23515 Q=MmuPlugin_shared_vpn_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23513 Q=MmuPlugin_shared_vpn_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24663 Q=MmuPlugin_shared_vpn_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23511 Q=MmuPlugin_shared_vpn_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23509 Q=MmuPlugin_shared_vpn_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23507 Q=MmuPlugin_shared_vpn_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23505 Q=MmuPlugin_shared_vpn_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23503 Q=MmuPlugin_shared_vpn_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23501 Q=MmuPlugin_shared_vpn_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23499 Q=MmuPlugin_shared_vpn_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23497 Q=MmuPlugin_shared_vpn_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23495 Q=MmuPlugin_shared_vpn_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24661 Q=MmuPlugin_shared_vpn_1[9] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[0] Q=MmuPlugin_shared_dBusRsp_pte_V +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[1] Q=MmuPlugin_shared_dBusRsp_pte_R +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[2] Q=MmuPlugin_shared_dBusRsp_pte_W +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[3] Q=MmuPlugin_shared_dBusRsp_pte_X +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[6] Q=MmuPlugin_shared_dBusRsp_pte_A +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[7] Q=MmuPlugin_shared_dBusRsp_pte_D +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[10] Q=MmuPlugin_shared_dBusRspStaged_payload_data[10] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[11] Q=MmuPlugin_shared_dBusRspStaged_payload_data[11] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[12] Q=MmuPlugin_shared_dBusRspStaged_payload_data[12] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[13] Q=MmuPlugin_shared_dBusRspStaged_payload_data[13] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[14] Q=MmuPlugin_shared_dBusRspStaged_payload_data[14] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[15] Q=MmuPlugin_shared_dBusRspStaged_payload_data[15] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[16] Q=MmuPlugin_shared_dBusRspStaged_payload_data[16] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[17] Q=MmuPlugin_shared_dBusRspStaged_payload_data[17] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[18] Q=MmuPlugin_shared_dBusRspStaged_payload_data[18] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[19] Q=MmuPlugin_shared_dBusRspStaged_payload_data[19] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[20] Q=MmuPlugin_shared_dBusRspStaged_payload_data[20] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[21] Q=MmuPlugin_shared_dBusRspStaged_payload_data[21] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[22] Q=MmuPlugin_shared_dBusRspStaged_payload_data[22] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[23] Q=MmuPlugin_shared_dBusRspStaged_payload_data[23] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[24] Q=MmuPlugin_shared_dBusRspStaged_payload_data[24] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[25] Q=MmuPlugin_shared_dBusRspStaged_payload_data[25] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[26] Q=MmuPlugin_shared_dBusRspStaged_payload_data[26] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[27] Q=MmuPlugin_shared_dBusRspStaged_payload_data[27] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[28] Q=MmuPlugin_shared_dBusRspStaged_payload_data[28] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[29] Q=MmuPlugin_shared_dBusRspStaged_payload_data[29] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_error Q=MmuPlugin_shared_dBusRspStaged_payload_error +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_redo Q=MmuPlugin_shared_dBusRspStaged_payload_redo +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23493 Q=MmuPlugin_shared_pteBuffer_PPN0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23491 Q=MmuPlugin_shared_pteBuffer_PPN0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23489 Q=MmuPlugin_shared_pteBuffer_PPN0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23487 Q=MmuPlugin_shared_pteBuffer_PPN0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23485 Q=MmuPlugin_shared_pteBuffer_PPN0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23483 Q=MmuPlugin_shared_pteBuffer_PPN0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23481 Q=MmuPlugin_shared_pteBuffer_PPN0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23479 Q=MmuPlugin_shared_pteBuffer_PPN0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23477 Q=MmuPlugin_shared_pteBuffer_PPN0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24659 Q=MmuPlugin_shared_pteBuffer_PPN0[9] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[0] Q=HazardSimplePlugin_writeBackBuffer_payload_data[0] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[1] Q=HazardSimplePlugin_writeBackBuffer_payload_data[1] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[2] Q=HazardSimplePlugin_writeBackBuffer_payload_data[2] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[3] Q=HazardSimplePlugin_writeBackBuffer_payload_data[3] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[4] Q=HazardSimplePlugin_writeBackBuffer_payload_data[4] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[5] Q=HazardSimplePlugin_writeBackBuffer_payload_data[5] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[6] Q=HazardSimplePlugin_writeBackBuffer_payload_data[6] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[7] Q=HazardSimplePlugin_writeBackBuffer_payload_data[7] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[8] Q=HazardSimplePlugin_writeBackBuffer_payload_data[8] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[9] Q=HazardSimplePlugin_writeBackBuffer_payload_data[9] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[10] Q=HazardSimplePlugin_writeBackBuffer_payload_data[10] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[11] Q=HazardSimplePlugin_writeBackBuffer_payload_data[11] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[12] Q=HazardSimplePlugin_writeBackBuffer_payload_data[12] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[13] Q=HazardSimplePlugin_writeBackBuffer_payload_data[13] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[14] Q=HazardSimplePlugin_writeBackBuffer_payload_data[14] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[15] Q=HazardSimplePlugin_writeBackBuffer_payload_data[15] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[16] Q=HazardSimplePlugin_writeBackBuffer_payload_data[16] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[17] Q=HazardSimplePlugin_writeBackBuffer_payload_data[17] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[18] Q=HazardSimplePlugin_writeBackBuffer_payload_data[18] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[19] Q=HazardSimplePlugin_writeBackBuffer_payload_data[19] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[20] Q=HazardSimplePlugin_writeBackBuffer_payload_data[20] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[21] Q=HazardSimplePlugin_writeBackBuffer_payload_data[21] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[22] Q=HazardSimplePlugin_writeBackBuffer_payload_data[22] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[23] Q=HazardSimplePlugin_writeBackBuffer_payload_data[23] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[24] Q=HazardSimplePlugin_writeBackBuffer_payload_data[24] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[25] Q=HazardSimplePlugin_writeBackBuffer_payload_data[25] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[26] Q=HazardSimplePlugin_writeBackBuffer_payload_data[26] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[27] Q=HazardSimplePlugin_writeBackBuffer_payload_data[27] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[28] Q=HazardSimplePlugin_writeBackBuffer_payload_data[28] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[29] Q=HazardSimplePlugin_writeBackBuffer_payload_data[29] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[30] Q=HazardSimplePlugin_writeBackBuffer_payload_data[30] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[31] Q=HazardSimplePlugin_writeBackBuffer_payload_data[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23475 Q=MmuPlugin_shared_pteBuffer_PPN1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23473 Q=MmuPlugin_shared_pteBuffer_PPN1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23471 Q=MmuPlugin_shared_pteBuffer_PPN1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23469 Q=MmuPlugin_shared_pteBuffer_PPN1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23467 Q=MmuPlugin_shared_pteBuffer_PPN1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23465 Q=MmuPlugin_shared_pteBuffer_PPN1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23463 Q=MmuPlugin_shared_pteBuffer_PPN1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23461 Q=MmuPlugin_shared_pteBuffer_PPN1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23459 Q=MmuPlugin_shared_pteBuffer_PPN1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23457 Q=MmuPlugin_shared_pteBuffer_PPN1[9] +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23453 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23451 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23449 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23447 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23445 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23443 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23441 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23439 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23437 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23435 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23433 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23431 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23429 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23427 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23425 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23423 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23421 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23419 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23417 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23415 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23413 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23411 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23409 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23407 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23405 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23403 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23401 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23399 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23397 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23395 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23393 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24869 Q=memory_DivPlugin_accumulator[31] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23391 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23389 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23387 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23385 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23383 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23381 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23379 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23377 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23375 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23373 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23371 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23369 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23367 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23365 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23363 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23361 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23359 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23357 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23355 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23353 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23351 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23349 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23347 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23345 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23343 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23341 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23339 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23337 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23335 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23333 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23331 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24653 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24871 Q=memory_DivPlugin_div_done RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24651 Q=_zz_memory_DivPlugin_div_result_5 +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][0] Q=CsrPlugin_mepc[0] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][1] Q=CsrPlugin_mepc[1] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][2] Q=CsrPlugin_mepc[2] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][3] Q=CsrPlugin_mepc[3] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][4] Q=CsrPlugin_mepc[4] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][5] Q=CsrPlugin_mepc[5] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][6] Q=CsrPlugin_mepc[6] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][7] Q=CsrPlugin_mepc[7] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][8] Q=CsrPlugin_mepc[8] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][9] Q=CsrPlugin_mepc[9] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][10] Q=CsrPlugin_mepc[10] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][11] Q=CsrPlugin_mepc[11] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][12] Q=CsrPlugin_mepc[12] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][13] Q=CsrPlugin_mepc[13] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][14] Q=CsrPlugin_mepc[14] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][15] Q=CsrPlugin_mepc[15] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][16] Q=CsrPlugin_mepc[16] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][17] Q=CsrPlugin_mepc[17] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][18] Q=CsrPlugin_mepc[18] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][19] Q=CsrPlugin_mepc[19] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][20] Q=CsrPlugin_mepc[20] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][21] Q=CsrPlugin_mepc[21] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][22] Q=CsrPlugin_mepc[22] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][23] Q=CsrPlugin_mepc[23] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][24] Q=CsrPlugin_mepc[24] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][25] Q=CsrPlugin_mepc[25] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][26] Q=CsrPlugin_mepc[26] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][27] Q=CsrPlugin_mepc[27] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][28] Q=CsrPlugin_mepc[28] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][29] Q=CsrPlugin_mepc[29] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][30] Q=CsrPlugin_mepc[30] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][31] Q=CsrPlugin_mepc[31] +.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP +.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP +.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23329 Q=memory_DivPlugin_div_result[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23327 Q=memory_DivPlugin_div_result[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23325 Q=memory_DivPlugin_div_result[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23323 Q=memory_DivPlugin_div_result[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23321 Q=memory_DivPlugin_div_result[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23319 Q=memory_DivPlugin_div_result[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23317 Q=memory_DivPlugin_div_result[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23315 Q=memory_DivPlugin_div_result[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23313 Q=memory_DivPlugin_div_result[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23311 Q=memory_DivPlugin_div_result[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23309 Q=memory_DivPlugin_div_result[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23307 Q=memory_DivPlugin_div_result[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23305 Q=memory_DivPlugin_div_result[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23303 Q=memory_DivPlugin_div_result[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23301 Q=memory_DivPlugin_div_result[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23299 Q=memory_DivPlugin_div_result[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23297 Q=memory_DivPlugin_div_result[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23295 Q=memory_DivPlugin_div_result[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23293 Q=memory_DivPlugin_div_result[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23291 Q=memory_DivPlugin_div_result[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23289 Q=memory_DivPlugin_div_result[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23287 Q=memory_DivPlugin_div_result[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23285 Q=memory_DivPlugin_div_result[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23283 Q=memory_DivPlugin_div_result[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23281 Q=memory_DivPlugin_div_result[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23279 Q=memory_DivPlugin_div_result[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23277 Q=memory_DivPlugin_div_result[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23275 Q=memory_DivPlugin_div_result[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23273 Q=memory_DivPlugin_div_result[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23271 Q=memory_DivPlugin_div_result[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23269 Q=memory_DivPlugin_div_result[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24649 Q=memory_DivPlugin_div_result[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24647 Q=CsrPlugin_mcause_interrupt +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23267 Q=CsrPlugin_mtval[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23265 Q=CsrPlugin_mtval[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23263 Q=CsrPlugin_mtval[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23261 Q=CsrPlugin_mtval[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23259 Q=CsrPlugin_mtval[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23257 Q=CsrPlugin_mtval[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23255 Q=CsrPlugin_mtval[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23253 Q=CsrPlugin_mtval[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23251 Q=CsrPlugin_mtval[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23249 Q=CsrPlugin_mtval[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23247 Q=CsrPlugin_mtval[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23245 Q=CsrPlugin_mtval[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23243 Q=CsrPlugin_mtval[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23241 Q=CsrPlugin_mtval[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23239 Q=CsrPlugin_mtval[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23237 Q=CsrPlugin_mtval[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23235 Q=CsrPlugin_mtval[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23233 Q=CsrPlugin_mtval[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23231 Q=CsrPlugin_mtval[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23229 Q=CsrPlugin_mtval[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23227 Q=CsrPlugin_mtval[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23225 Q=CsrPlugin_mtval[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23223 Q=CsrPlugin_mtval[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23221 Q=CsrPlugin_mtval[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23219 Q=CsrPlugin_mtval[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23217 Q=CsrPlugin_mtval[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23215 Q=CsrPlugin_mtval[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23213 Q=CsrPlugin_mtval[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23211 Q=CsrPlugin_mtval[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23209 Q=CsrPlugin_mtval[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23207 Q=CsrPlugin_mtval[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24645 Q=CsrPlugin_mtval[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23205 Q=BranchPlugin_branchExceptionPort_payload_badAddr[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23203 Q=BranchPlugin_branchExceptionPort_payload_badAddr[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23201 Q=BranchPlugin_branchExceptionPort_payload_badAddr[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23199 Q=BranchPlugin_branchExceptionPort_payload_badAddr[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23197 Q=BranchPlugin_branchExceptionPort_payload_badAddr[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23195 Q=BranchPlugin_branchExceptionPort_payload_badAddr[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23193 Q=BranchPlugin_branchExceptionPort_payload_badAddr[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23191 Q=BranchPlugin_branchExceptionPort_payload_badAddr[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23189 Q=BranchPlugin_branchExceptionPort_payload_badAddr[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23187 Q=BranchPlugin_branchExceptionPort_payload_badAddr[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23185 Q=BranchPlugin_branchExceptionPort_payload_badAddr[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23183 Q=BranchPlugin_branchExceptionPort_payload_badAddr[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23181 Q=BranchPlugin_branchExceptionPort_payload_badAddr[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23179 Q=BranchPlugin_branchExceptionPort_payload_badAddr[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23177 Q=BranchPlugin_branchExceptionPort_payload_badAddr[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23175 Q=BranchPlugin_branchExceptionPort_payload_badAddr[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23173 Q=BranchPlugin_branchExceptionPort_payload_badAddr[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23171 Q=BranchPlugin_branchExceptionPort_payload_badAddr[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23169 Q=BranchPlugin_branchExceptionPort_payload_badAddr[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23167 Q=BranchPlugin_branchExceptionPort_payload_badAddr[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23165 Q=BranchPlugin_branchExceptionPort_payload_badAddr[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23163 Q=BranchPlugin_branchExceptionPort_payload_badAddr[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23161 Q=BranchPlugin_branchExceptionPort_payload_badAddr[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23159 Q=BranchPlugin_branchExceptionPort_payload_badAddr[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23157 Q=BranchPlugin_branchExceptionPort_payload_badAddr[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23155 Q=BranchPlugin_branchExceptionPort_payload_badAddr[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23153 Q=BranchPlugin_branchExceptionPort_payload_badAddr[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23151 Q=BranchPlugin_branchExceptionPort_payload_badAddr[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23149 Q=BranchPlugin_branchExceptionPort_payload_badAddr[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23147 Q=BranchPlugin_branchExceptionPort_payload_badAddr[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24873 Q=BranchPlugin_branchExceptionPort_payload_badAddr[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23145 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23143 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23141 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23139 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23137 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23135 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23133 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23131 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23129 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23127 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23125 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23123 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23121 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23119 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23117 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23115 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23113 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23111 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23109 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23107 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23105 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23103 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23101 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23099 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23097 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23095 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23093 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23091 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23089 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23087 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23085 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24643 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23083 Q=IBusCachedPlugin_cache.lineLoader_address[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23081 Q=IBusCachedPlugin_cache.lineLoader_address[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23079 Q=IBusCachedPlugin_cache.lineLoader_address[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23077 Q=iBus_cmd_payload_address[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23075 Q=iBus_cmd_payload_address[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23073 Q=iBus_cmd_payload_address[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23071 Q=iBus_cmd_payload_address[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23069 Q=iBus_cmd_payload_address[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23067 Q=iBus_cmd_payload_address[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23065 Q=iBus_cmd_payload_address[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23063 Q=iBus_cmd_payload_address[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23061 Q=iBus_cmd_payload_address[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23059 Q=iBus_cmd_payload_address[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23057 Q=iBus_cmd_payload_address[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23055 Q=iBus_cmd_payload_address[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23053 Q=iBus_cmd_payload_address[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23051 Q=iBus_cmd_payload_address[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23049 Q=iBus_cmd_payload_address[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23047 Q=iBus_cmd_payload_address[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23045 Q=iBus_cmd_payload_address[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23043 Q=iBus_cmd_payload_address[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23041 Q=iBus_cmd_payload_address[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23039 Q=iBus_cmd_payload_address[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23037 Q=iBus_cmd_payload_address[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23035 Q=iBus_cmd_payload_address[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23033 Q=iBus_cmd_payload_address[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23031 Q=iBus_cmd_payload_address[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23029 Q=iBus_cmd_payload_address[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23027 Q=iBus_cmd_payload_address[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24887 Q=iBus_cmd_payload_address[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23025 Q=DBusCachedPlugin_redoBranch_payload[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23023 Q=DBusCachedPlugin_redoBranch_payload[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23021 Q=DBusCachedPlugin_redoBranch_payload[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23019 Q=DBusCachedPlugin_redoBranch_payload[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23017 Q=DBusCachedPlugin_redoBranch_payload[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23015 Q=DBusCachedPlugin_redoBranch_payload[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23013 Q=DBusCachedPlugin_redoBranch_payload[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23011 Q=DBusCachedPlugin_redoBranch_payload[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23009 Q=DBusCachedPlugin_redoBranch_payload[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23007 Q=DBusCachedPlugin_redoBranch_payload[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23005 Q=DBusCachedPlugin_redoBranch_payload[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23003 Q=DBusCachedPlugin_redoBranch_payload[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23001 Q=DBusCachedPlugin_redoBranch_payload[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22999 Q=DBusCachedPlugin_redoBranch_payload[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22997 Q=DBusCachedPlugin_redoBranch_payload[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22995 Q=DBusCachedPlugin_redoBranch_payload[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22993 Q=DBusCachedPlugin_redoBranch_payload[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22991 Q=DBusCachedPlugin_redoBranch_payload[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22989 Q=DBusCachedPlugin_redoBranch_payload[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22987 Q=DBusCachedPlugin_redoBranch_payload[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22985 Q=DBusCachedPlugin_redoBranch_payload[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22983 Q=DBusCachedPlugin_redoBranch_payload[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22981 Q=DBusCachedPlugin_redoBranch_payload[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22979 Q=DBusCachedPlugin_redoBranch_payload[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22977 Q=DBusCachedPlugin_redoBranch_payload[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22975 Q=DBusCachedPlugin_redoBranch_payload[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22973 Q=DBusCachedPlugin_redoBranch_payload[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22971 Q=DBusCachedPlugin_redoBranch_payload[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22969 Q=DBusCachedPlugin_redoBranch_payload[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24897 Q=DBusCachedPlugin_redoBranch_payload[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22953 Q=_zz_execute_BranchPlugin_branch_src2_10 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22951 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22949 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22947 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22945 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22943 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22941 Q=switch_Misc_l241_1 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22939 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22937 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22935 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22933 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22931 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22929 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22927 Q=_zz_execute_BranchPlugin_branch_src2_8 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22925 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22923 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22921 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22919 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22917 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22915 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22913 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22911 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22909 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22907 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24633 Q=_zz_execute_BranchPlugin_branch_src2 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22891 Q=execute_to_memory_INSTRUCTION[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22889 Q=execute_to_memory_INSTRUCTION[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22887 Q=execute_to_memory_INSTRUCTION[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22885 Q=execute_to_memory_INSTRUCTION[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22883 Q=execute_to_memory_INSTRUCTION[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22881 Q=execute_to_memory_INSTRUCTION[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22879 Q=execute_to_memory_INSTRUCTION[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22877 Q=execute_to_memory_INSTRUCTION[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22849 Q=execute_to_memory_INSTRUCTION[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22847 Q=execute_to_memory_INSTRUCTION[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22829 Q=HazardSimplePlugin_writeBackWrites_payload_address[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22827 Q=HazardSimplePlugin_writeBackWrites_payload_address[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22825 Q=HazardSimplePlugin_writeBackWrites_payload_address[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22823 Q=HazardSimplePlugin_writeBackWrites_payload_address[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22821 Q=HazardSimplePlugin_writeBackWrites_payload_address[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22819 Q=_zz_lastStageRegFileWrite_payload_address[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22817 Q=_zz_lastStageRegFileWrite_payload_address[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22815 Q=_zz_lastStageRegFileWrite_payload_address[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22787 Q=_zz_lastStageRegFileWrite_payload_address[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22785 Q=_zz_lastStageRegFileWrite_payload_address[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24627 Q=decode_to_execute_PREDICTION_CONTEXT_hazard +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22781 Q=decode_to_execute_PREDICTION_CONTEXT_line_history[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24625 Q=decode_to_execute_PREDICTION_CONTEXT_line_history[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24623 Q=execute_to_memory_PREDICTION_CONTEXT_hazard +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22779 Q=execute_to_memory_PREDICTION_CONTEXT_line_history[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24621 Q=execute_to_memory_PREDICTION_CONTEXT_line_history[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22777 Q=_zz_execute_SRC1_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24619 Q=_zz_execute_SRC1_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24617 Q=_zz_execute_SrcPlugin_addSub_4 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24615 Q=decode_to_execute_MEMORY_ENABLE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24613 Q=execute_to_memory_MEMORY_ENABLE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24611 Q=memory_to_writeBack_MEMORY_ENABLE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22775 Q=_zz_execute_ALU_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24609 Q=_zz_execute_ALU_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24605 Q=decode_to_execute_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22773 Q=_zz_execute_SRC2_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24607 Q=_zz_execute_SRC2_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24601 Q=execute_to_memory_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24599 Q=_zz_lastStageRegFileWrite_valid +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24597 Q=decode_to_execute_BYPASSABLE_EXECUTE_STAGE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24595 Q=decode_to_execute_BYPASSABLE_MEMORY_STAGE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24593 Q=execute_to_memory_BYPASSABLE_MEMORY_STAGE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24591 Q=decode_to_execute_MEMORY_WR +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24589 Q=execute_to_memory_MEMORY_WR +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24587 Q=memory_to_writeBack_MEMORY_WR +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24585 Q=decode_to_execute_MEMORY_MANAGMENT +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24583 Q=decode_to_execute_IS_SFENCE_VMA2 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24581 Q=decode_to_execute_SRC_LESS_UNSIGNED +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22771 Q=_zz_execute_ALU_BITWISE_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24579 Q=_zz_execute_ALU_BITWISE_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22769 Q=_zz_execute_SHIFT_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24577 Q=_zz_execute_SHIFT_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22767 Q=_zz_memory_SHIFT_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24575 Q=_zz_memory_SHIFT_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24573 Q=decode_to_execute_IS_MUL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24571 Q=execute_to_memory_IS_MUL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24569 Q=memory_to_writeBack_IS_MUL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24567 Q=decode_to_execute_IS_DIV +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24565 Q=execute_to_memory_IS_DIV +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24563 Q=decode_to_execute_IS_RS1_SIGNED +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24561 Q=decode_to_execute_IS_CSR +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24559 Q=_zz_execute_ENV_CTRL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24557 Q=_zz_memory_ENV_CTRL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24555 Q=_zz_writeBack_ENV_CTRL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22765 Q=_zz_execute_BRANCH_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24553 Q=_zz_execute_BRANCH_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22763 Q=_zz_memory_BRANCH_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24551 Q=_zz_memory_BRANCH_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22761 Q=execute_RS1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22759 Q=execute_RS1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22757 Q=execute_RS1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22755 Q=execute_RS1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22753 Q=execute_RS1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22751 Q=execute_RS1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22749 Q=execute_RS1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22747 Q=execute_RS1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22745 Q=execute_RS1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22743 Q=execute_RS1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22741 Q=execute_RS1[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22739 Q=execute_RS1[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22737 Q=execute_RS1[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22735 Q=execute_RS1[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22733 Q=execute_RS1[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22731 Q=execute_RS1[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22729 Q=execute_RS1[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22727 Q=execute_RS1[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22725 Q=execute_RS1[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22723 Q=execute_RS1[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22721 Q=execute_RS1[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22719 Q=execute_RS1[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22717 Q=execute_RS1[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22715 Q=execute_RS1[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22713 Q=execute_RS1[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22711 Q=execute_RS1[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22709 Q=execute_RS1[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22707 Q=execute_RS1[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22705 Q=execute_RS1[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22703 Q=execute_RS1[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22701 Q=execute_RS1[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24549 Q=execute_RS1[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22699 Q=execute_RS2[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22697 Q=execute_RS2[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22695 Q=execute_RS2[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22693 Q=execute_RS2[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22691 Q=execute_RS2[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22689 Q=execute_RS2[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22687 Q=execute_RS2[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22685 Q=execute_RS2[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22683 Q=execute_RS2[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22681 Q=execute_RS2[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22679 Q=execute_RS2[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22677 Q=execute_RS2[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22675 Q=execute_RS2[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22673 Q=execute_RS2[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22671 Q=execute_RS2[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22669 Q=execute_RS2[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22667 Q=execute_RS2[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22665 Q=execute_RS2[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22663 Q=execute_RS2[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22661 Q=execute_RS2[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22659 Q=execute_RS2[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22657 Q=execute_RS2[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22655 Q=execute_RS2[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22653 Q=execute_RS2[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22651 Q=execute_RS2[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22649 Q=execute_RS2[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22647 Q=execute_RS2[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22645 Q=execute_RS2[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22643 Q=execute_RS2[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22641 Q=execute_RS2[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22639 Q=execute_RS2[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24547 Q=execute_RS2[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24545 Q=decode_to_execute_SRC2_FORCE_ZERO +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24543 Q=decode_to_execute_CSR_WRITE_OPCODE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24541 Q=decode_to_execute_DO_EBREAK +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24539 Q=decode_to_execute_PREDICTION_HAD_BRANCHED2 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22637 Q=execute_to_memory_MEMORY_STORE_DATA_RF[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22635 Q=execute_to_memory_MEMORY_STORE_DATA_RF[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22633 Q=execute_to_memory_MEMORY_STORE_DATA_RF[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22631 Q=execute_to_memory_MEMORY_STORE_DATA_RF[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22629 Q=execute_to_memory_MEMORY_STORE_DATA_RF[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22627 Q=execute_to_memory_MEMORY_STORE_DATA_RF[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22625 Q=execute_to_memory_MEMORY_STORE_DATA_RF[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22623 Q=execute_to_memory_MEMORY_STORE_DATA_RF[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22621 Q=execute_to_memory_MEMORY_STORE_DATA_RF[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22619 Q=execute_to_memory_MEMORY_STORE_DATA_RF[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22617 Q=execute_to_memory_MEMORY_STORE_DATA_RF[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22615 Q=execute_to_memory_MEMORY_STORE_DATA_RF[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22613 Q=execute_to_memory_MEMORY_STORE_DATA_RF[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22611 Q=execute_to_memory_MEMORY_STORE_DATA_RF[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22609 Q=execute_to_memory_MEMORY_STORE_DATA_RF[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22607 Q=execute_to_memory_MEMORY_STORE_DATA_RF[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22605 Q=execute_to_memory_MEMORY_STORE_DATA_RF[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22603 Q=execute_to_memory_MEMORY_STORE_DATA_RF[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22601 Q=execute_to_memory_MEMORY_STORE_DATA_RF[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22599 Q=execute_to_memory_MEMORY_STORE_DATA_RF[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22597 Q=execute_to_memory_MEMORY_STORE_DATA_RF[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22595 Q=execute_to_memory_MEMORY_STORE_DATA_RF[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22593 Q=execute_to_memory_MEMORY_STORE_DATA_RF[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22591 Q=execute_to_memory_MEMORY_STORE_DATA_RF[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22589 Q=execute_to_memory_MEMORY_STORE_DATA_RF[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22587 Q=execute_to_memory_MEMORY_STORE_DATA_RF[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22585 Q=execute_to_memory_MEMORY_STORE_DATA_RF[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22583 Q=execute_to_memory_MEMORY_STORE_DATA_RF[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22581 Q=execute_to_memory_MEMORY_STORE_DATA_RF[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22579 Q=execute_to_memory_MEMORY_STORE_DATA_RF[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22577 Q=execute_to_memory_MEMORY_STORE_DATA_RF[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24537 Q=execute_to_memory_MEMORY_STORE_DATA_RF[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22575 Q=dBus_cmd_payload_data[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22573 Q=dBus_cmd_payload_data[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22571 Q=dBus_cmd_payload_data[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22569 Q=dBus_cmd_payload_data[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22567 Q=dBus_cmd_payload_data[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22565 Q=dBus_cmd_payload_data[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22563 Q=dBus_cmd_payload_data[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22561 Q=dBus_cmd_payload_data[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22559 Q=dBus_cmd_payload_data[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22557 Q=dBus_cmd_payload_data[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22555 Q=dBus_cmd_payload_data[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22553 Q=dBus_cmd_payload_data[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22551 Q=dBus_cmd_payload_data[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22549 Q=dBus_cmd_payload_data[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22547 Q=dBus_cmd_payload_data[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22545 Q=dBus_cmd_payload_data[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22543 Q=dBus_cmd_payload_data[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22541 Q=dBus_cmd_payload_data[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22539 Q=dBus_cmd_payload_data[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22537 Q=dBus_cmd_payload_data[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22535 Q=dBus_cmd_payload_data[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22533 Q=dBus_cmd_payload_data[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22531 Q=dBus_cmd_payload_data[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22529 Q=dBus_cmd_payload_data[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22527 Q=dBus_cmd_payload_data[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22525 Q=dBus_cmd_payload_data[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22523 Q=dBus_cmd_payload_data[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22521 Q=dBus_cmd_payload_data[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22519 Q=dBus_cmd_payload_data[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22517 Q=dBus_cmd_payload_data[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22515 Q=dBus_cmd_payload_data[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24535 Q=dBus_cmd_payload_data[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22513 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22511 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22509 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22507 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22505 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22503 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22501 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22499 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22497 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22495 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22493 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22491 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22489 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22487 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22485 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22483 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22481 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22479 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22477 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22475 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22473 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22471 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22469 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22467 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22465 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22463 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22461 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22459 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22457 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22455 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22453 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24533 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22451 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22449 Q=_zz_writeBack_DBusCachedPlugin_rspShifted_3 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22447 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22445 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22443 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22441 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22439 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22437 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22435 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22433 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22431 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22429 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22427 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22425 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22423 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22421 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22419 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22417 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22415 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22413 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22411 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22409 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22407 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22405 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22403 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22401 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22399 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22397 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22395 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22393 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22391 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24531 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22389 Q=_zz_decode_RS2_3[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22387 Q=_zz_decode_RS2_3[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22385 Q=_zz_decode_RS2_3[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22383 Q=_zz_decode_RS2_3[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22381 Q=_zz_decode_RS2_3[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22379 Q=_zz_decode_RS2_3[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22377 Q=_zz_decode_RS2_3[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22375 Q=_zz_decode_RS2_3[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22373 Q=_zz_decode_RS2_3[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22371 Q=_zz_decode_RS2_3[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22369 Q=_zz_decode_RS2_3[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22367 Q=_zz_decode_RS2_3[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22365 Q=_zz_decode_RS2_3[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22363 Q=_zz_decode_RS2_3[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22361 Q=_zz_decode_RS2_3[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22359 Q=_zz_decode_RS2_3[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22357 Q=_zz_decode_RS2_3[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22355 Q=_zz_decode_RS2_3[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22353 Q=_zz_decode_RS2_3[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22351 Q=_zz_decode_RS2_3[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22349 Q=_zz_decode_RS2_3[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22347 Q=_zz_decode_RS2_3[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22345 Q=_zz_decode_RS2_3[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22343 Q=_zz_decode_RS2_3[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22341 Q=_zz_decode_RS2_3[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22339 Q=_zz_decode_RS2_3[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22337 Q=_zz_decode_RS2_3[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22335 Q=_zz_decode_RS2_3[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22333 Q=_zz_decode_RS2_3[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22331 Q=_zz_decode_RS2_3[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22329 Q=_zz_decode_RS2_3[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24529 Q=_zz_decode_RS2_3[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22327 Q=_zz_memory_MUL_LOW_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22325 Q=_zz_memory_MUL_LOW_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22323 Q=_zz_memory_MUL_LOW_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22321 Q=_zz_memory_MUL_LOW_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22319 Q=_zz_memory_MUL_LOW_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22317 Q=_zz_memory_MUL_LOW_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22315 Q=_zz_memory_MUL_LOW_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22313 Q=_zz_memory_MUL_LOW_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22311 Q=_zz_memory_MUL_LOW_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22309 Q=_zz_memory_MUL_LOW_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22307 Q=_zz_memory_MUL_LOW_1[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22305 Q=_zz_memory_MUL_LOW_1[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22303 Q=_zz_memory_MUL_LOW_1[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22301 Q=_zz_memory_MUL_LOW_1[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22299 Q=_zz_memory_MUL_LOW_1[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22297 Q=_zz_memory_MUL_LOW_1[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22295 Q=_zz_memory_MUL_LOW_1[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22293 Q=_zz_memory_MUL_LOW_1[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22291 Q=_zz_memory_MUL_LOW_1[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22289 Q=_zz_memory_MUL_LOW_1[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22287 Q=_zz_memory_MUL_LOW_1[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22285 Q=_zz_memory_MUL_LOW_1[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22283 Q=_zz_memory_MUL_LOW_1[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22281 Q=_zz_memory_MUL_LOW_1[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22279 Q=_zz_memory_MUL_LOW_1[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22277 Q=_zz_memory_MUL_LOW_1[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22275 Q=_zz_memory_MUL_LOW_1[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22273 Q=_zz_memory_MUL_LOW_1[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22271 Q=_zz_memory_MUL_LOW_1[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22269 Q=_zz_memory_MUL_LOW_1[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22267 Q=_zz_memory_MUL_LOW_1[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24527 Q=_zz_memory_MUL_LOW_1[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22265 Q=_zz_memory_MUL_LOW_4[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22263 Q=_zz_memory_MUL_LOW_4[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22261 Q=_zz_memory_MUL_LOW_4[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22259 Q=_zz_memory_MUL_LOW_4[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22257 Q=_zz_memory_MUL_LOW_4[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22255 Q=_zz_memory_MUL_LOW_4[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22253 Q=_zz_memory_MUL_LOW_4[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22251 Q=_zz_memory_MUL_LOW_4[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22249 Q=_zz_memory_MUL_LOW_4[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22247 Q=_zz_memory_MUL_LOW_4[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22245 Q=_zz_memory_MUL_LOW_4[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22243 Q=_zz_memory_MUL_LOW_4[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22241 Q=_zz_memory_MUL_LOW_4[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22239 Q=_zz_memory_MUL_LOW_4[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22237 Q=_zz_memory_MUL_LOW_4[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22235 Q=_zz_memory_MUL_LOW_4[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22233 Q=_zz_memory_MUL_LOW_4[32] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22231 Q=_zz_memory_MUL_LOW_4[33] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22229 Q=_zz_memory_MUL_LOW_4[34] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22227 Q=_zz_memory_MUL_LOW_4[35] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22225 Q=_zz_memory_MUL_LOW_4[36] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22223 Q=_zz_memory_MUL_LOW_4[37] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22221 Q=_zz_memory_MUL_LOW_4[38] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22219 Q=_zz_memory_MUL_LOW_4[39] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22217 Q=_zz_memory_MUL_LOW_4[40] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22215 Q=_zz_memory_MUL_LOW_4[41] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22213 Q=_zz_memory_MUL_LOW_4[42] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22211 Q=_zz_memory_MUL_LOW_4[43] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22209 Q=_zz_memory_MUL_LOW_4[44] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22207 Q=_zz_memory_MUL_LOW_4[45] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22205 Q=_zz_memory_MUL_LOW_4[46] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22203 Q=_zz_memory_MUL_LOW_4[47] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22201 Q=_zz_memory_MUL_LOW_4[48] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24525 Q=_zz_memory_MUL_LOW_4[51] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22199 Q=_zz_memory_MUL_LOW_6[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22197 Q=_zz_memory_MUL_LOW_6[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22195 Q=_zz_memory_MUL_LOW_6[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22193 Q=_zz_memory_MUL_LOW_6[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22191 Q=_zz_memory_MUL_LOW_6[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22189 Q=_zz_memory_MUL_LOW_6[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22187 Q=_zz_memory_MUL_LOW_6[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22185 Q=_zz_memory_MUL_LOW_6[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22183 Q=_zz_memory_MUL_LOW_6[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22181 Q=_zz_memory_MUL_LOW_6[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22179 Q=_zz_memory_MUL_LOW_6[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22177 Q=_zz_memory_MUL_LOW_6[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22175 Q=_zz_memory_MUL_LOW_6[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22173 Q=_zz_memory_MUL_LOW_6[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22171 Q=_zz_memory_MUL_LOW_6[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22169 Q=_zz_memory_MUL_LOW_6[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22167 Q=_zz_memory_MUL_LOW_6[32] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22165 Q=_zz_memory_MUL_LOW_6[33] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22163 Q=_zz_memory_MUL_LOW_6[34] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22161 Q=_zz_memory_MUL_LOW_6[35] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22159 Q=_zz_memory_MUL_LOW_6[36] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22157 Q=_zz_memory_MUL_LOW_6[37] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22155 Q=_zz_memory_MUL_LOW_6[38] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22153 Q=_zz_memory_MUL_LOW_6[39] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22151 Q=_zz_memory_MUL_LOW_6[40] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22149 Q=_zz_memory_MUL_LOW_6[41] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22147 Q=_zz_memory_MUL_LOW_6[42] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22145 Q=_zz_memory_MUL_LOW_6[43] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22143 Q=_zz_memory_MUL_LOW_6[44] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22141 Q=_zz_memory_MUL_LOW_6[45] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22139 Q=_zz_memory_MUL_LOW_6[46] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22137 Q=_zz_memory_MUL_LOW_6[47] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22135 Q=_zz_memory_MUL_LOW_6[48] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24523 Q=_zz_memory_MUL_LOW_6[51] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22133 Q=execute_to_memory_MUL_HH[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22131 Q=execute_to_memory_MUL_HH[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22129 Q=execute_to_memory_MUL_HH[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22127 Q=execute_to_memory_MUL_HH[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22125 Q=execute_to_memory_MUL_HH[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22123 Q=execute_to_memory_MUL_HH[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22121 Q=execute_to_memory_MUL_HH[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22119 Q=execute_to_memory_MUL_HH[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22117 Q=execute_to_memory_MUL_HH[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22115 Q=execute_to_memory_MUL_HH[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22113 Q=execute_to_memory_MUL_HH[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22111 Q=execute_to_memory_MUL_HH[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22109 Q=execute_to_memory_MUL_HH[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22107 Q=execute_to_memory_MUL_HH[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22105 Q=execute_to_memory_MUL_HH[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22103 Q=execute_to_memory_MUL_HH[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22101 Q=execute_to_memory_MUL_HH[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22099 Q=execute_to_memory_MUL_HH[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22097 Q=execute_to_memory_MUL_HH[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22095 Q=execute_to_memory_MUL_HH[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22093 Q=execute_to_memory_MUL_HH[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22091 Q=execute_to_memory_MUL_HH[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22089 Q=execute_to_memory_MUL_HH[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22087 Q=execute_to_memory_MUL_HH[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22085 Q=execute_to_memory_MUL_HH[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22083 Q=execute_to_memory_MUL_HH[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22081 Q=execute_to_memory_MUL_HH[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22079 Q=execute_to_memory_MUL_HH[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22077 Q=execute_to_memory_MUL_HH[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22075 Q=execute_to_memory_MUL_HH[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22073 Q=execute_to_memory_MUL_HH[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22071 Q=execute_to_memory_MUL_HH[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22067 Q=_zz_writeBack_MulPlugin_result_1[32] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22065 Q=_zz_writeBack_MulPlugin_result_1[33] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22063 Q=_zz_writeBack_MulPlugin_result_1[34] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22061 Q=_zz_writeBack_MulPlugin_result_1[35] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22059 Q=_zz_writeBack_MulPlugin_result_1[36] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22057 Q=_zz_writeBack_MulPlugin_result_1[37] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22055 Q=_zz_writeBack_MulPlugin_result_1[38] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22053 Q=_zz_writeBack_MulPlugin_result_1[39] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22051 Q=_zz_writeBack_MulPlugin_result_1[40] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22049 Q=_zz_writeBack_MulPlugin_result_1[41] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22047 Q=_zz_writeBack_MulPlugin_result_1[42] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22045 Q=_zz_writeBack_MulPlugin_result_1[43] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22043 Q=_zz_writeBack_MulPlugin_result_1[44] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22041 Q=_zz_writeBack_MulPlugin_result_1[45] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22039 Q=_zz_writeBack_MulPlugin_result_1[46] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22037 Q=_zz_writeBack_MulPlugin_result_1[47] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22035 Q=_zz_writeBack_MulPlugin_result_1[48] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22033 Q=_zz_writeBack_MulPlugin_result_1[49] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22031 Q=_zz_writeBack_MulPlugin_result_1[50] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22029 Q=_zz_writeBack_MulPlugin_result_1[51] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22027 Q=_zz_writeBack_MulPlugin_result_1[52] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22025 Q=_zz_writeBack_MulPlugin_result_1[53] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22023 Q=_zz_writeBack_MulPlugin_result_1[54] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22021 Q=_zz_writeBack_MulPlugin_result_1[55] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22019 Q=_zz_writeBack_MulPlugin_result_1[56] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22017 Q=_zz_writeBack_MulPlugin_result_1[57] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22015 Q=_zz_writeBack_MulPlugin_result_1[58] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22013 Q=_zz_writeBack_MulPlugin_result_1[59] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22011 Q=_zz_writeBack_MulPlugin_result_1[60] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22009 Q=_zz_writeBack_MulPlugin_result_1[61] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22007 Q=_zz_writeBack_MulPlugin_result_1[62] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22005 Q=_zz_writeBack_MulPlugin_result_1[63] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24517 Q=execute_to_memory_BRANCH_DO +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22001 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21999 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21997 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21995 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21993 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21991 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21989 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21987 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21985 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21983 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21981 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21979 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21977 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21975 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21973 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21971 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21969 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21967 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21965 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21963 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21961 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21959 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21957 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21955 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21953 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21951 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21949 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21947 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21945 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] R=reset +.subckt dffs C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24875 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] S=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21943 Q=_zz__zz_decode_RS2_2[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21941 Q=_zz__zz_decode_RS2_2[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21939 Q=_zz__zz_decode_RS2_2[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21937 Q=_zz__zz_decode_RS2_2[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21935 Q=_zz__zz_decode_RS2_2[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21933 Q=_zz__zz_decode_RS2_2[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21931 Q=_zz__zz_decode_RS2_2[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21929 Q=_zz__zz_decode_RS2_2[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21927 Q=_zz__zz_decode_RS2_2[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21925 Q=_zz__zz_decode_RS2_2[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21923 Q=_zz__zz_decode_RS2_2[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21921 Q=_zz__zz_decode_RS2_2[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21919 Q=_zz__zz_decode_RS2_2[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21917 Q=_zz__zz_decode_RS2_2[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21915 Q=_zz__zz_decode_RS2_2[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21913 Q=_zz__zz_decode_RS2_2[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21911 Q=_zz__zz_decode_RS2_2[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21909 Q=_zz__zz_decode_RS2_2[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21907 Q=_zz__zz_decode_RS2_2[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21905 Q=_zz__zz_decode_RS2_2[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21903 Q=_zz__zz_decode_RS2_2[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21901 Q=_zz__zz_decode_RS2_2[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21899 Q=_zz__zz_decode_RS2_2[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21897 Q=_zz__zz_decode_RS2_2[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21895 Q=_zz__zz_decode_RS2_2[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21893 Q=_zz__zz_decode_RS2_2[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21891 Q=_zz__zz_decode_RS2_2[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21889 Q=_zz__zz_decode_RS2_2[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21887 Q=_zz__zz_decode_RS2_2[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21885 Q=_zz__zz_decode_RS2_2[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21883 Q=_zz__zz_decode_RS2_2[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21881 Q=_zz__zz_decode_RS2_2[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21879 Q=_zz_writeBack_MulPlugin_result[32] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21877 Q=_zz_writeBack_MulPlugin_result[33] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21875 Q=_zz_writeBack_MulPlugin_result[34] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21873 Q=_zz_writeBack_MulPlugin_result[35] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21871 Q=_zz_writeBack_MulPlugin_result[36] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21869 Q=_zz_writeBack_MulPlugin_result[37] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21867 Q=_zz_writeBack_MulPlugin_result[38] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21865 Q=_zz_writeBack_MulPlugin_result[39] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21863 Q=_zz_writeBack_MulPlugin_result[40] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21861 Q=_zz_writeBack_MulPlugin_result[41] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21859 Q=_zz_writeBack_MulPlugin_result[42] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21857 Q=_zz_writeBack_MulPlugin_result[43] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21855 Q=_zz_writeBack_MulPlugin_result[44] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21853 Q=_zz_writeBack_MulPlugin_result[45] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21851 Q=_zz_writeBack_MulPlugin_result[46] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21849 Q=_zz_writeBack_MulPlugin_result[47] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21847 Q=_zz_writeBack_MulPlugin_result[48] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21845 Q=_zz_writeBack_MulPlugin_result[49] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21843 Q=_zz_writeBack_MulPlugin_result[50] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24515 Q=_zz_writeBack_MulPlugin_result[65] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24513 Q=execute_CsrPlugin_csr_768 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24511 Q=execute_CsrPlugin_csr_256 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24509 Q=execute_CsrPlugin_csr_384 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24507 Q=execute_CsrPlugin_csr_836 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24505 Q=execute_CsrPlugin_csr_772 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24503 Q=execute_CsrPlugin_csr_833 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24501 Q=execute_CsrPlugin_csr_834 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24499 Q=execute_CsrPlugin_csr_835 +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24497 Q=execute_arbitration_isValid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24495 Q=memory_arbitration_isValid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24493 Q=lastStageIsValid R=reset +.subckt dffr C=clk D=$true Q=IBusCachedPlugin_fetchPc_booted R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24491 Q=IBusCachedPlugin_fetchPc_inc R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24489 Q=IBusCachedPlugin_cache.io_cpu_fetch_isValid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24487 Q=IBusCachedPlugin_cache.io_cpu_decode_isValid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24485 Q=IBusCachedPlugin_injector_nextPcCalc_valids_0 R=reset +.subckt dffr C=clk D=$0\MmuPlugin_status_sum[0:0] Q=MmuPlugin_status_sum R=reset +.subckt dffr C=clk D=$0\MmuPlugin_status_mxr[0:0] Q=MmuPlugin_status_mxr R=reset +.subckt dffr C=clk D=$0\MmuPlugin_status_mprv[0:0] Q=MmuPlugin_status_mprv R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24483 Q=IBusCachedPlugin_iBusRsp_readyForError R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_0_valid[0:0] Q=MmuPlugin_ports_1_cache_0_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_1_valid[0:0] Q=MmuPlugin_ports_1_cache_1_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_2_valid[0:0] Q=MmuPlugin_ports_1_cache_2_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_3_valid[0:0] Q=MmuPlugin_ports_1_cache_3_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_4_valid[0:0] Q=MmuPlugin_ports_1_cache_4_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_5_valid[0:0] Q=MmuPlugin_ports_1_cache_5_valid R=reset +.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[0] Q=MmuPlugin_ports_1_entryToReplace_value[0] R=reset +.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[1] Q=MmuPlugin_ports_1_entryToReplace_value[1] R=reset +.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[2] Q=MmuPlugin_ports_1_entryToReplace_value[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24481 Q=MmuPlugin_satp_mode R=reset +.subckt dffr C=clk D=MmuPlugin_dBusAccess_rsp_valid Q=MmuPlugin_shared_dBusRspStaged_valid R=reset +.subckt dffs C=clk D=$false Q=_zz_14 S=reset +.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[0] Q=memory_DivPlugin_div_counter_value[0] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[1] Q=memory_DivPlugin_div_counter_value[1] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[2] Q=memory_DivPlugin_div_counter_value[2] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[3] Q=memory_DivPlugin_div_counter_value[3] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[4] Q=memory_DivPlugin_div_counter_value[4] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[5] Q=memory_DivPlugin_div_counter_value[5] R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21841 Q=MmuPlugin_shared_state_1[0] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21839 Q=MmuPlugin_shared_state_1[1] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24479 Q=MmuPlugin_shared_state_1[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24477 Q=CsrPlugin_mie_MEIE R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24475 Q=CsrPlugin_mie_MTIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode[0:0] Q=CsrPlugin_exceptionPendings_0 R=reset +.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute[0:0] Q=CsrPlugin_exceptionPendings_1 R=reset +.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory[0:0] Q=CsrPlugin_exceptionPendings_2 R=reset +.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack[0:0] Q=CsrPlugin_exceptionPendings_3 R=reset +.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24473 Q=CsrPlugin_mie_MSIE R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24471 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24469 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset +.subckt dffr C=clk D=CsrPlugin_exception Q=CsrPlugin_hadException R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24467 Q=CsrPlugin_pipelineLiberator_pcValids_2 R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24465 Q=DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24463 Q=memory_to_writeBack_IS_DBUS_SHARING R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21837 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21835 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24461 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] R=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21833 Q=DebugPlugin_busReadDataReg[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24891 Q=DebugPlugin_busReadDataReg[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21829 Q=dataCache_1.stageA_request_size[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24837 Q=dataCache_1.stageA_request_size[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24839 Q=dataCache_1.io_cpu_memory_isWrite +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24841 Q=dataCache_1.loader_error R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24843 Q=dataCache_1.io_cpu_execute_refilling R=reset +.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[0] Q=dataCache_1.loader_counter_value[0] R=reset +.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[1] Q=dataCache_1.loader_counter_value[1] R=reset +.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[2] Q=dataCache_1.loader_counter_value[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21827 Q=dataCache_1.stageB_flusher_counter[0] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21825 Q=dataCache_1.stageB_flusher_counter[1] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21823 Q=dataCache_1.stageB_flusher_counter[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21821 Q=dataCache_1.stageB_flusher_counter[3] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21819 Q=dataCache_1.stageB_flusher_counter[4] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21817 Q=dataCache_1.stageB_flusher_counter[5] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24845 Q=dataCache_1.stageB_flusher_counter[6] R=reset +.subckt dffs C=clk D=$abc$27210$flatten\dataCache_1.$0\stageB_flusher_start[0:0] Q=dataCache_1.stageB_flusher_start S=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24847 Q=dataCache_1.stageB_flusher_waitDone R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24849 Q=dataCache_1.memCmdSent R=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24797 Q=dataCache_1.stageB_unaligned +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24795 Q=dataCache_1.stageB_waysHit +.subckt dff C=clk D=dataCache_1.io_cpu_execute_refilling Q=dataCache_1.loader_valid_regNext +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21815 Q=dataCache_1.stageA_mask[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21813 Q=dataCache_1.stageA_mask[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21811 Q=dataCache_1.stageA_mask[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24835 Q=dataCache_1.stageA_mask[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24833 Q=dataCache_1.stage0_dataColisions_regNextWhen +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24831 Q=dBus_cmd_payload_wr +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21809 Q=dataCache_1.stageB_request_size[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24829 Q=dataCache_1.stageB_request_size[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24825 Q=dBus_cmd_payload_uncached +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21807 Q=dataCache_1.stageB_mmuRsp_physicalAddress[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21805 Q=dataCache_1.stageB_mmuRsp_physicalAddress[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21803 Q=dataCache_1.stageB_mmuRsp_physicalAddress[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21801 Q=dataCache_1.stageB_mmuRsp_physicalAddress[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21799 Q=dataCache_1.stageB_mmuRsp_physicalAddress[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21797 Q=dBus_cmd_payload_address[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21795 Q=dBus_cmd_payload_address[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21793 Q=dBus_cmd_payload_address[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21791 Q=dBus_cmd_payload_address[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21789 Q=dBus_cmd_payload_address[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21787 Q=dBus_cmd_payload_address[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21785 Q=dBus_cmd_payload_address[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21783 Q=dBus_cmd_payload_address[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21781 Q=dBus_cmd_payload_address[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21779 Q=dBus_cmd_payload_address[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21777 Q=dBus_cmd_payload_address[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21775 Q=dBus_cmd_payload_address[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21773 Q=dBus_cmd_payload_address[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21771 Q=dBus_cmd_payload_address[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21769 Q=dBus_cmd_payload_address[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21767 Q=dBus_cmd_payload_address[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21765 Q=dBus_cmd_payload_address[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21763 Q=dBus_cmd_payload_address[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21761 Q=dBus_cmd_payload_address[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21759 Q=dBus_cmd_payload_address[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21757 Q=dBus_cmd_payload_address[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21755 Q=dBus_cmd_payload_address[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21753 Q=dBus_cmd_payload_address[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21751 Q=dBus_cmd_payload_address[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21749 Q=dBus_cmd_payload_address[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21747 Q=dBus_cmd_payload_address[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24827 Q=dBus_cmd_payload_address[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24819 Q=dataCache_1.stageB_mmuRsp_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24815 Q=dataCache_1.stageB_mmuRsp_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24811 Q=dataCache_1.stageB_mmuRsp_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24807 Q=dataCache_1.stageB_mmuRsp_refilling +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24821 Q=dataCache_1.stageB_mmuRsp_isPaging +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24803 Q=dataCache_1.stageB_tagsReadRsp_0_error +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21745 Q=dBus_cmd_payload_mask[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21743 Q=dBus_cmd_payload_mask[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21741 Q=dBus_cmd_payload_mask[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24793 Q=dBus_cmd_payload_mask[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21739 Q=dataCache_1.stageB_dataMux[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21737 Q=dataCache_1.stageB_dataMux[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21735 Q=dataCache_1.stageB_dataMux[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21733 Q=dataCache_1.stageB_dataMux[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21731 Q=dataCache_1.stageB_dataMux[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21729 Q=dataCache_1.stageB_dataMux[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21727 Q=dataCache_1.stageB_dataMux[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21725 Q=dataCache_1.stageB_dataMux[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21723 Q=dataCache_1.stageB_dataMux[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21721 Q=dataCache_1.stageB_dataMux[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21719 Q=dataCache_1.stageB_dataMux[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21717 Q=dataCache_1.stageB_dataMux[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21715 Q=dataCache_1.stageB_dataMux[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21713 Q=dataCache_1.stageB_dataMux[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21711 Q=dataCache_1.stageB_dataMux[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21709 Q=dataCache_1.stageB_dataMux[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21707 Q=dataCache_1.stageB_dataMux[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21705 Q=dataCache_1.stageB_dataMux[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21703 Q=dataCache_1.stageB_dataMux[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21701 Q=dataCache_1.stageB_dataMux[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21699 Q=dataCache_1.stageB_dataMux[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21697 Q=dataCache_1.stageB_dataMux[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21695 Q=dataCache_1.stageB_dataMux[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21693 Q=dataCache_1.stageB_dataMux[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21691 Q=dataCache_1.stageB_dataMux[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21689 Q=dataCache_1.stageB_dataMux[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21687 Q=dataCache_1.stageB_dataMux[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21685 Q=dataCache_1.stageB_dataMux[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21683 Q=dataCache_1.stageB_dataMux[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21681 Q=dataCache_1.stageB_dataMux[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21679 Q=dataCache_1.stageB_dataMux[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24801 Q=dataCache_1.stageB_dataMux[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24799 Q=dataCache_1.stageB_dataColisions +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24899 Q=when_MmuPlugin_l281_1 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24459 Q=DebugPlugin_busReadDataReg[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24457 Q=DebugPlugin_busReadDataReg[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24455 Q=DebugPlugin_busReadDataReg[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24453 Q=debug_bus_rsp_data[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24451 Q=debug_bus_rsp_data[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24449 Q=debug_bus_rsp_data[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24447 Q=debug_bus_rsp_data[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24445 Q=debug_bus_rsp_data[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24443 Q=debug_bus_rsp_data[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24441 Q=debug_bus_rsp_data[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24439 Q=debug_bus_rsp_data[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24437 Q=debug_bus_rsp_data[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24435 Q=debug_bus_rsp_data[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24433 Q=debug_bus_rsp_data[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24431 Q=debug_bus_rsp_data[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24429 Q=debug_bus_rsp_data[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24427 Q=debug_bus_rsp_data[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24425 Q=debug_bus_rsp_data[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24423 Q=debug_bus_rsp_data[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24421 Q=debug_bus_rsp_data[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24419 Q=debug_bus_rsp_data[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24417 Q=debug_bus_rsp_data[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24415 Q=debug_bus_rsp_data[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24413 Q=debug_bus_rsp_data[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24411 Q=debug_bus_rsp_data[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24409 Q=debug_bus_rsp_data[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24407 Q=debug_bus_rsp_data[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24405 Q=debug_bus_rsp_data[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24403 Q=debug_bus_rsp_data[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24893 Q=debug_bus_rsp_data[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24401 Q=_zz_execute_to_memory_PC[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24399 Q=_zz_execute_to_memory_PC[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24397 Q=_zz_execute_to_memory_PC[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24395 Q=_zz_execute_to_memory_PC[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24393 Q=_zz_execute_to_memory_PC[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24391 Q=_zz_execute_to_memory_PC[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24389 Q=_zz_execute_to_memory_PC[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24387 Q=_zz_execute_to_memory_PC[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24385 Q=_zz_execute_to_memory_PC[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24383 Q=_zz_execute_to_memory_PC[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24381 Q=_zz_execute_to_memory_PC[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24379 Q=_zz_execute_to_memory_PC[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24377 Q=_zz_execute_to_memory_PC[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24375 Q=_zz_execute_to_memory_PC[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24373 Q=_zz_execute_to_memory_PC[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24371 Q=_zz_execute_to_memory_PC[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24369 Q=_zz_execute_to_memory_PC[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24367 Q=_zz_execute_to_memory_PC[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24365 Q=_zz_execute_to_memory_PC[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24363 Q=_zz_execute_to_memory_PC[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24361 Q=_zz_execute_to_memory_PC[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24359 Q=_zz_execute_to_memory_PC[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24357 Q=_zz_execute_to_memory_PC[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24355 Q=_zz_execute_to_memory_PC[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24353 Q=_zz_execute_to_memory_PC[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24351 Q=_zz_execute_to_memory_PC[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24349 Q=_zz_execute_to_memory_PC[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24347 Q=_zz_execute_to_memory_PC[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24345 Q=_zz_execute_to_memory_PC[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24885 Q=_zz_execute_to_memory_PC[31] +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24343 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[0] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24341 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[1] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24851 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24853 Q=IBusCachedPlugin_cache.lineLoader_cmdSent R=reset +.subckt dffs C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24855 Q=IBusCachedPlugin_cache.lineLoader_flushPending S=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24857 Q=IBusCachedPlugin_cache.lineLoader_valid R=reset +.subckt dffr C=clk D=$abc$27210$flatten\IBusCachedPlugin_cache.$0\lineLoader_hadError[0:0] Q=IBusCachedPlugin_cache.lineLoader_hadError R=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24339 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24337 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24335 Q=_zz__zz_decode_IS_CSR_85 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24333 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24331 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24329 Q=_zz__zz_decode_IS_CSR_41 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24327 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24325 Q=_zz_IBusCachedPlugin_predictionJumpInterface_payload_6 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24323 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24321 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24319 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24317 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24315 Q=_zz__zz_decode_IS_CSR_21 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24313 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24311 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24309 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24307 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24305 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24303 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24301 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24299 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24297 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24295 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24293 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24291 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24289 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24287 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24285 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24283 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24281 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24279 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24859 Q=_zz_6 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24277 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24275 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24273 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24271 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24269 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24267 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24265 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24263 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24261 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24259 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24257 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24255 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24253 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24251 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24249 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24247 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24245 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24243 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24241 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24861 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24863 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_error +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24865 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24239 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24237 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24905 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] +.subckt mult24x20 A[23]=execute_RS1[16] A[22]=execute_RS1[17] A[21]=execute_RS1[18] A[20]=execute_RS1[19] A[19]=execute_RS1[20] A[18]=execute_RS1[21] A[17]=execute_RS1[22] A[16]=execute_RS1[23] A[15]=execute_RS1[24] A[14]=execute_RS1[25] A[13]=execute_RS1[26] A[12]=execute_RS1[27] A[11]=execute_RS1[28] A[10]=execute_RS1[29] A[9]=execute_RS1[30] A[8]=execute_RS1[31] A[7]=execute_MulPlugin_aHigh[16] A[6]=execute_MulPlugin_aHigh[16] A[5]=execute_MulPlugin_aHigh[16] A[4]=execute_MulPlugin_aHigh[16] A[3]=execute_MulPlugin_aHigh[16] A[2]=execute_MulPlugin_aHigh[16] A[1]=execute_MulPlugin_aHigh[16] A[0]=execute_MulPlugin_aHigh[16] B[19]=execute_RS2[16] B[18]=execute_RS2[17] B[17]=execute_RS2[18] B[16]=execute_RS2[19] B[15]=execute_RS2[20] B[14]=execute_RS2[21] B[13]=execute_RS2[22] B[12]=execute_RS2[23] B[11]=execute_RS2[24] B[10]=execute_RS2[25] B[9]=execute_RS2[26] B[8]=execute_RS2[27] B[7]=execute_RS2[28] B[6]=execute_RS2[29] B[5]=execute_RS2[30] B[4]=execute_RS2[31] B[3]=execute_MulPlugin_bHigh[16] B[2]=execute_MulPlugin_bHigh[16] B[1]=execute_MulPlugin_bHigh[16] B[0]=execute_MulPlugin_bHigh[16] Y[43]=execute_MUL_HH[0] Y[42]=execute_MUL_HH[1] Y[41]=execute_MUL_HH[2] Y[40]=execute_MUL_HH[3] Y[39]=execute_MUL_HH[4] Y[38]=execute_MUL_HH[5] Y[37]=execute_MUL_HH[6] Y[36]=execute_MUL_HH[7] Y[35]=execute_MUL_HH[8] Y[34]=execute_MUL_HH[9] Y[33]=execute_MUL_HH[10] Y[32]=execute_MUL_HH[11] Y[31]=execute_MUL_HH[12] Y[30]=execute_MUL_HH[13] Y[29]=execute_MUL_HH[14] Y[28]=execute_MUL_HH[15] Y[27]=execute_MUL_HH[16] Y[26]=execute_MUL_HH[17] Y[25]=execute_MUL_HH[18] Y[24]=execute_MUL_HH[19] Y[23]=execute_MUL_HH[20] Y[22]=execute_MUL_HH[21] Y[21]=execute_MUL_HH[22] Y[20]=execute_MUL_HH[23] Y[19]=execute_MUL_HH[24] Y[18]=execute_MUL_HH[25] Y[17]=execute_MUL_HH[26] Y[16]=execute_MUL_HH[27] Y[15]=execute_MUL_HH[28] Y[14]=execute_MUL_HH[29] Y[13]=execute_MUL_HH[30] Y[12]=execute_MUL_HH[31] Y[11]=execute_MUL_HH[32] Y[10]=execute_MUL_HH[33] Y[9]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[9] Y[8]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[8] Y[7]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[7] Y[6]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[6] Y[5]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[5] Y[4]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[4] Y[3]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[3] Y[2]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[2] Y[1]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[1] Y[0]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[0] +.subckt mult24x20 A[23]=execute_RS1[16] A[22]=execute_RS1[17] A[21]=execute_RS1[18] A[20]=execute_RS1[19] A[19]=execute_RS1[20] A[18]=execute_RS1[21] A[17]=execute_RS1[22] A[16]=execute_RS1[23] A[15]=execute_RS1[24] A[14]=execute_RS1[25] A[13]=execute_RS1[26] A[12]=execute_RS1[27] A[11]=execute_RS1[28] A[10]=execute_RS1[29] A[9]=execute_RS1[30] A[8]=execute_RS1[31] A[7]=execute_MulPlugin_aHigh[16] A[6]=execute_MulPlugin_aHigh[16] A[5]=execute_MulPlugin_aHigh[16] A[4]=execute_MulPlugin_aHigh[16] A[3]=execute_MulPlugin_aHigh[16] A[2]=execute_MulPlugin_aHigh[16] A[1]=execute_MulPlugin_aHigh[16] A[0]=execute_MulPlugin_aHigh[16] B[19]=execute_RS2[0] B[18]=execute_RS2[1] B[17]=execute_RS2[2] B[16]=execute_RS2[3] B[15]=execute_RS2[4] B[14]=execute_RS2[5] B[13]=execute_RS2[6] B[12]=execute_RS2[7] B[11]=execute_RS2[8] B[10]=execute_RS2[9] B[9]=execute_RS2[10] B[8]=execute_RS2[11] B[7]=execute_RS2[12] B[6]=execute_RS2[13] B[5]=execute_RS2[14] B[4]=execute_RS2[15] B[3]=$false B[2]=$false B[1]=$false B[0]=$false Y[43]=execute_MUL_HL[0] Y[42]=execute_MUL_HL[1] Y[41]=execute_MUL_HL[2] Y[40]=execute_MUL_HL[3] Y[39]=execute_MUL_HL[4] Y[38]=execute_MUL_HL[5] Y[37]=execute_MUL_HL[6] Y[36]=execute_MUL_HL[7] Y[35]=execute_MUL_HL[8] Y[34]=execute_MUL_HL[9] Y[33]=execute_MUL_HL[10] Y[32]=execute_MUL_HL[11] Y[31]=execute_MUL_HL[12] Y[30]=execute_MUL_HL[13] Y[29]=execute_MUL_HL[14] Y[28]=execute_MUL_HL[15] Y[27]=execute_MUL_HL[16] Y[26]=execute_MUL_HL[17] Y[25]=execute_MUL_HL[18] Y[24]=execute_MUL_HL[19] Y[23]=execute_MUL_HL[20] Y[22]=execute_MUL_HL[21] Y[21]=execute_MUL_HL[22] Y[20]=execute_MUL_HL[23] Y[19]=execute_MUL_HL[24] Y[18]=execute_MUL_HL[25] Y[17]=execute_MUL_HL[26] Y[16]=execute_MUL_HL[27] Y[15]=execute_MUL_HL[28] Y[14]=execute_MUL_HL[29] Y[13]=execute_MUL_HL[30] Y[12]=execute_MUL_HL[31] Y[11]=execute_MUL_HL[32] Y[10]=execute_MUL_HL[33] Y[9]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[9] Y[8]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[8] Y[7]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[7] Y[6]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[6] Y[5]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[5] Y[4]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[4] Y[3]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[3] Y[2]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[2] Y[1]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[1] Y[0]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[0] +.subckt mult24x20 A[23]=execute_RS1[0] A[22]=execute_RS1[1] A[21]=execute_RS1[2] A[20]=execute_RS1[3] A[19]=execute_RS1[4] A[18]=execute_RS1[5] A[17]=execute_RS1[6] A[16]=execute_RS1[7] A[15]=execute_RS1[8] A[14]=execute_RS1[9] A[13]=execute_RS1[10] A[12]=execute_RS1[11] A[11]=execute_RS1[12] A[10]=execute_RS1[13] A[9]=execute_RS1[14] A[8]=execute_RS1[15] A[7]=$false A[6]=$false A[5]=$false A[4]=$false A[3]=$false A[2]=$false A[1]=$false A[0]=$false B[19]=execute_RS2[16] B[18]=execute_RS2[17] B[17]=execute_RS2[18] B[16]=execute_RS2[19] B[15]=execute_RS2[20] B[14]=execute_RS2[21] B[13]=execute_RS2[22] B[12]=execute_RS2[23] B[11]=execute_RS2[24] B[10]=execute_RS2[25] B[9]=execute_RS2[26] B[8]=execute_RS2[27] B[7]=execute_RS2[28] B[6]=execute_RS2[29] B[5]=execute_RS2[30] B[4]=execute_RS2[31] B[3]=execute_MulPlugin_bHigh[16] B[2]=execute_MulPlugin_bHigh[16] B[1]=execute_MulPlugin_bHigh[16] B[0]=execute_MulPlugin_bHigh[16] Y[43]=execute_MUL_LH[0] Y[42]=execute_MUL_LH[1] Y[41]=execute_MUL_LH[2] Y[40]=execute_MUL_LH[3] Y[39]=execute_MUL_LH[4] Y[38]=execute_MUL_LH[5] Y[37]=execute_MUL_LH[6] Y[36]=execute_MUL_LH[7] Y[35]=execute_MUL_LH[8] Y[34]=execute_MUL_LH[9] Y[33]=execute_MUL_LH[10] Y[32]=execute_MUL_LH[11] Y[31]=execute_MUL_LH[12] Y[30]=execute_MUL_LH[13] Y[29]=execute_MUL_LH[14] Y[28]=execute_MUL_LH[15] Y[27]=execute_MUL_LH[16] Y[26]=execute_MUL_LH[17] Y[25]=execute_MUL_LH[18] Y[24]=execute_MUL_LH[19] Y[23]=execute_MUL_LH[20] Y[22]=execute_MUL_LH[21] Y[21]=execute_MUL_LH[22] Y[20]=execute_MUL_LH[23] Y[19]=execute_MUL_LH[24] Y[18]=execute_MUL_LH[25] Y[17]=execute_MUL_LH[26] Y[16]=execute_MUL_LH[27] Y[15]=execute_MUL_LH[28] Y[14]=execute_MUL_LH[29] Y[13]=execute_MUL_LH[30] Y[12]=execute_MUL_LH[31] Y[11]=execute_MUL_LH[32] Y[10]=execute_MUL_LH[33] Y[9]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[9] Y[8]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[8] Y[7]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[7] Y[6]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[6] Y[5]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[5] Y[4]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[4] Y[3]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[3] Y[2]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[2] Y[1]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[1] Y[0]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[0] +.subckt mult24x20 A[23]=execute_RS1[0] A[22]=execute_RS1[1] A[21]=execute_RS1[2] A[20]=execute_RS1[3] A[19]=execute_RS1[4] A[18]=execute_RS1[5] A[17]=execute_RS1[6] A[16]=execute_RS1[7] A[15]=execute_RS1[8] A[14]=execute_RS1[9] A[13]=execute_RS1[10] A[12]=execute_RS1[11] A[11]=execute_RS1[12] A[10]=execute_RS1[13] A[9]=execute_RS1[14] A[8]=execute_RS1[15] A[7]=$false A[6]=$false A[5]=$false A[4]=$false A[3]=$false A[2]=$false A[1]=$false A[0]=$false B[19]=execute_RS2[0] B[18]=execute_RS2[1] B[17]=execute_RS2[2] B[16]=execute_RS2[3] B[15]=execute_RS2[4] B[14]=execute_RS2[5] B[13]=execute_RS2[6] B[12]=execute_RS2[7] B[11]=execute_RS2[8] B[10]=execute_RS2[9] B[9]=execute_RS2[10] B[8]=execute_RS2[11] B[7]=execute_RS2[12] B[6]=execute_RS2[13] B[5]=execute_RS2[14] B[4]=execute_RS2[15] B[3]=$false B[2]=$false B[1]=$false B[0]=$false Y[43]=execute_MUL_LL[0] Y[42]=execute_MUL_LL[1] Y[41]=execute_MUL_LL[2] Y[40]=execute_MUL_LL[3] Y[39]=execute_MUL_LL[4] Y[38]=execute_MUL_LL[5] Y[37]=execute_MUL_LL[6] Y[36]=execute_MUL_LL[7] Y[35]=execute_MUL_LL[8] Y[34]=execute_MUL_LL[9] Y[33]=execute_MUL_LL[10] Y[32]=execute_MUL_LL[11] Y[31]=execute_MUL_LL[12] Y[30]=execute_MUL_LL[13] Y[29]=execute_MUL_LL[14] Y[28]=execute_MUL_LL[15] Y[27]=execute_MUL_LL[16] Y[26]=execute_MUL_LL[17] Y[25]=execute_MUL_LL[18] Y[24]=execute_MUL_LL[19] Y[23]=execute_MUL_LL[20] Y[22]=execute_MUL_LL[21] Y[21]=execute_MUL_LL[22] Y[20]=execute_MUL_LL[23] Y[19]=execute_MUL_LL[24] Y[18]=execute_MUL_LL[25] Y[17]=execute_MUL_LL[26] Y[16]=execute_MUL_LL[27] Y[15]=execute_MUL_LL[28] Y[14]=execute_MUL_LL[29] Y[13]=execute_MUL_LL[30] Y[12]=execute_MUL_LL[31] Y[11]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[11] Y[10]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[10] Y[9]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[9] Y[8]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[8] Y[7]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[7] Y[6]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[6] Y[5]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[5] Y[4]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[4] Y[3]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[3] Y[2]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[2] Y[1]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[1] Y[0]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[0] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[0] data_i[7]=iBus_rsp_payload_data[1] data_i[6]=iBus_rsp_payload_data[2] data_i[5]=iBus_rsp_payload_data[3] data_i[4]=iBus_rsp_payload_data[4] data_i[3]=iBus_rsp_payload_data[5] data_i[2]=iBus_rsp_payload_data[6] data_i[1]=iBus_rsp_payload_data[7] data_i[0]=iBus_rsp_payload_data[8] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[0] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[1] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[2] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[3] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[4] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[5] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[6] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[7] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[8] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[9] data_i[7]=iBus_rsp_payload_data[10] data_i[6]=iBus_rsp_payload_data[11] data_i[5]=iBus_rsp_payload_data[12] data_i[4]=iBus_rsp_payload_data[13] data_i[3]=iBus_rsp_payload_data[14] data_i[2]=iBus_rsp_payload_data[15] data_i[1]=iBus_rsp_payload_data[16] data_i[0]=iBus_rsp_payload_data[17] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[9] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[10] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[11] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[12] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[13] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[14] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[15] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[16] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[17] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[18] data_i[7]=iBus_rsp_payload_data[19] data_i[6]=iBus_rsp_payload_data[20] data_i[5]=iBus_rsp_payload_data[21] data_i[4]=iBus_rsp_payload_data[22] data_i[3]=iBus_rsp_payload_data[23] data_i[2]=iBus_rsp_payload_data[24] data_i[1]=iBus_rsp_payload_data[25] data_i[0]=iBus_rsp_payload_data[26] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[18] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[19] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[20] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[21] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[22] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[23] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[24] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[25] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[26] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[27] data_i[7]=iBus_rsp_payload_data[28] data_i[6]=iBus_rsp_payload_data[29] data_i[5]=iBus_rsp_payload_data[30] data_i[4]=iBus_rsp_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[27] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[28] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[29] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[30] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6842[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6842[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6842[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6842[35] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid data_i[34]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_error data_i[33]=iBus_cmd_payload_address[12] data_i[32]=iBus_cmd_payload_address[13] data_i[31]=iBus_cmd_payload_address[14] data_i[30]=iBus_cmd_payload_address[15] data_i[29]=iBus_cmd_payload_address[16] data_i[28]=iBus_cmd_payload_address[17] data_i[27]=iBus_cmd_payload_address[18] data_i[26]=iBus_cmd_payload_address[19] data_i[25]=iBus_cmd_payload_address[20] data_i[24]=iBus_cmd_payload_address[21] data_i[23]=iBus_cmd_payload_address[22] data_i[22]=iBus_cmd_payload_address[23] data_i[21]=iBus_cmd_payload_address[24] data_i[20]=iBus_cmd_payload_address[25] data_i[19]=iBus_cmd_payload_address[26] data_i[18]=iBus_cmd_payload_address[27] data_i[17]=iBus_cmd_payload_address[28] data_i[16]=iBus_cmd_payload_address[29] data_i[15]=iBus_cmd_payload_address[30] data_i[14]=iBus_cmd_payload_address[31] data_i[13]=$undef data_i[12]=$undef data_i[11]=$undef data_i[10]=$undef data_i[9]=$undef data_i[8]=$undef data_i[7]=$undef data_i[6]=$undef data_i[5]=$undef data_i[4]=$undef data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] q_o[34]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] q_o[33]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] q_o[32]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] q_o[31]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] q_o[30]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] q_o[29]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] q_o[28]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] q_o[27]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] q_o[26]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] q_o[25]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] q_o[24]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] q_o[23]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] q_o[22]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] q_o[21]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] q_o[20]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] q_o[19]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] q_o[18]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] q_o[17]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] q_o[16]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] q_o[15]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] q_o[14]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] q_o[13]=$auto$memory_bram.cc:844:replace_memory$6847[22] q_o[12]=$auto$memory_bram.cc:844:replace_memory$6847[23] q_o[11]=$auto$memory_bram.cc:844:replace_memory$6847[24] q_o[10]=$auto$memory_bram.cc:844:replace_memory$6847[25] q_o[9]=$auto$memory_bram.cc:844:replace_memory$6847[26] q_o[8]=$auto$memory_bram.cc:844:replace_memory$6847[27] q_o[7]=$auto$memory_bram.cc:844:replace_memory$6847[28] q_o[6]=$auto$memory_bram.cc:844:replace_memory$6847[29] q_o[5]=$auto$memory_bram.cc:844:replace_memory$6847[30] q_o[4]=$auto$memory_bram.cc:844:replace_memory$6847[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6847[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6847[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6847[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6847[35] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] raddr_i[0]=$false rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[7]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[0] waddr_i[6]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[1] waddr_i[5]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[2] waddr_i[4]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[3] waddr_i[3]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[4] waddr_i[2]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[5] waddr_i[1]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[6] waddr_i[0]=$false wclk_i=clk wen_ni=IBusCachedPlugin_cache._zz_2 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6849[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6849[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6849[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6849[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6850[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6850[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6850[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6850[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=_zz__zz_3_port[0] data_i[2]=_zz__zz_3_port[1] data_i[1]=$undef data_i[0]=$undef q_o[3]=_zz__zz_3_port1[0] q_o[2]=_zz__zz_3_port1[1] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6853[2] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6853[3] raddr_i[10]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] raddr_i[0]=$false rclk_i=clk ren_ni=_zz_decode_PREDICTION_CONTEXT_line_history_1 waddr_i[10]=_zz_decode_PREDICTION_CONTEXT_hazard_1[0] waddr_i[9]=_zz_decode_PREDICTION_CONTEXT_hazard_1[1] waddr_i[8]=_zz_decode_PREDICTION_CONTEXT_hazard_1[2] waddr_i[7]=_zz_decode_PREDICTION_CONTEXT_hazard_1[3] waddr_i[6]=_zz_decode_PREDICTION_CONTEXT_hazard_1[4] waddr_i[5]=_zz_decode_PREDICTION_CONTEXT_hazard_1[5] waddr_i[4]=_zz_decode_PREDICTION_CONTEXT_hazard_1[6] waddr_i[3]=_zz_decode_PREDICTION_CONTEXT_hazard_1[7] waddr_i[2]=_zz_decode_PREDICTION_CONTEXT_hazard_1[8] waddr_i[1]=_zz_decode_PREDICTION_CONTEXT_hazard_1[9] waddr_i[0]=$false wclk_i=clk wen_ni=_zz_2 +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[0] data_i[7]=dataCache_1.dataWriteCmd_payload_data[1] data_i[6]=dataCache_1.dataWriteCmd_payload_data[2] data_i[5]=dataCache_1.dataWriteCmd_payload_data[3] data_i[4]=dataCache_1.dataWriteCmd_payload_data[4] data_i[3]=dataCache_1.dataWriteCmd_payload_data[5] data_i[2]=dataCache_1.dataWriteCmd_payload_data[6] data_i[1]=dataCache_1.dataWriteCmd_payload_data[7] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[0] q_o[7]=dataCache_1._zz_ways_0_data_port0[1] q_o[6]=dataCache_1._zz_ways_0_data_port0[2] q_o[5]=dataCache_1._zz_ways_0_data_port0[3] q_o[4]=dataCache_1._zz_ways_0_data_port0[4] q_o[3]=dataCache_1._zz_ways_0_data_port0[5] q_o[2]=dataCache_1._zz_ways_0_data_port0[6] q_o[1]=dataCache_1._zz_ways_0_data_port0[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6855[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol0$./benchmark/VexRiscv.v:6878$1192_EN[7:0]$1214[7] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[8] data_i[7]=dataCache_1.dataWriteCmd_payload_data[9] data_i[6]=dataCache_1.dataWriteCmd_payload_data[10] data_i[5]=dataCache_1.dataWriteCmd_payload_data[11] data_i[4]=dataCache_1.dataWriteCmd_payload_data[12] data_i[3]=dataCache_1.dataWriteCmd_payload_data[13] data_i[2]=dataCache_1.dataWriteCmd_payload_data[14] data_i[1]=dataCache_1.dataWriteCmd_payload_data[15] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[8] q_o[7]=dataCache_1._zz_ways_0_data_port0[9] q_o[6]=dataCache_1._zz_ways_0_data_port0[10] q_o[5]=dataCache_1._zz_ways_0_data_port0[11] q_o[4]=dataCache_1._zz_ways_0_data_port0[12] q_o[3]=dataCache_1._zz_ways_0_data_port0[13] q_o[2]=dataCache_1._zz_ways_0_data_port0[14] q_o[1]=dataCache_1._zz_ways_0_data_port0[15] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6857[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol1$./benchmark/VexRiscv.v:6881$1193_EN[7:0]$1217[7] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[16] data_i[7]=dataCache_1.dataWriteCmd_payload_data[17] data_i[6]=dataCache_1.dataWriteCmd_payload_data[18] data_i[5]=dataCache_1.dataWriteCmd_payload_data[19] data_i[4]=dataCache_1.dataWriteCmd_payload_data[20] data_i[3]=dataCache_1.dataWriteCmd_payload_data[21] data_i[2]=dataCache_1.dataWriteCmd_payload_data[22] data_i[1]=dataCache_1.dataWriteCmd_payload_data[23] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[16] q_o[7]=dataCache_1._zz_ways_0_data_port0[17] q_o[6]=dataCache_1._zz_ways_0_data_port0[18] q_o[5]=dataCache_1._zz_ways_0_data_port0[19] q_o[4]=dataCache_1._zz_ways_0_data_port0[20] q_o[3]=dataCache_1._zz_ways_0_data_port0[21] q_o[2]=dataCache_1._zz_ways_0_data_port0[22] q_o[1]=dataCache_1._zz_ways_0_data_port0[23] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6859[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol2$./benchmark/VexRiscv.v:6884$1194_EN[7:0]$1220[7] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[24] data_i[7]=dataCache_1.dataWriteCmd_payload_data[25] data_i[6]=dataCache_1.dataWriteCmd_payload_data[26] data_i[5]=dataCache_1.dataWriteCmd_payload_data[27] data_i[4]=dataCache_1.dataWriteCmd_payload_data[28] data_i[3]=dataCache_1.dataWriteCmd_payload_data[29] data_i[2]=dataCache_1.dataWriteCmd_payload_data[30] data_i[1]=dataCache_1.dataWriteCmd_payload_data[31] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[24] q_o[7]=dataCache_1._zz_ways_0_data_port0[25] q_o[6]=dataCache_1._zz_ways_0_data_port0[26] q_o[5]=dataCache_1._zz_ways_0_data_port0[27] q_o[4]=dataCache_1._zz_ways_0_data_port0[28] q_o[3]=dataCache_1._zz_ways_0_data_port0[29] q_o[2]=dataCache_1._zz_ways_0_data_port0[30] q_o[1]=dataCache_1._zz_ways_0_data_port0[31] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6861[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol3$./benchmark/VexRiscv.v:6887$1195_EN[7:0]$1223[7] +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=dataCache_1.loader_counter_willOverflow data_i[34]=dataCache_1.tagsWriteCmd_payload_data_error data_i[33]=dBus_cmd_payload_address[12] data_i[32]=dBus_cmd_payload_address[13] data_i[31]=dBus_cmd_payload_address[14] data_i[30]=dBus_cmd_payload_address[15] data_i[29]=dBus_cmd_payload_address[16] data_i[28]=dBus_cmd_payload_address[17] data_i[27]=dBus_cmd_payload_address[18] data_i[26]=dBus_cmd_payload_address[19] data_i[25]=dBus_cmd_payload_address[20] data_i[24]=dBus_cmd_payload_address[21] data_i[23]=dBus_cmd_payload_address[22] data_i[22]=dBus_cmd_payload_address[23] data_i[21]=dBus_cmd_payload_address[24] data_i[20]=dBus_cmd_payload_address[25] data_i[19]=dBus_cmd_payload_address[26] data_i[18]=dBus_cmd_payload_address[27] data_i[17]=dBus_cmd_payload_address[28] data_i[16]=dBus_cmd_payload_address[29] data_i[15]=dBus_cmd_payload_address[30] data_i[14]=dBus_cmd_payload_address[31] data_i[13]=$undef data_i[12]=$undef data_i[11]=$undef data_i[10]=$undef data_i[9]=$undef data_i[8]=$undef data_i[7]=$undef data_i[6]=$undef data_i[5]=$undef data_i[4]=$undef data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[0] q_o[34]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[1] q_o[33]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[2] q_o[32]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[3] q_o[31]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] q_o[30]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[5] q_o[29]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[6] q_o[28]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[7] q_o[27]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[8] q_o[26]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[9] q_o[25]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[10] q_o[24]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[11] q_o[23]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] q_o[22]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[13] q_o[21]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[14] q_o[20]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[15] q_o[19]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[16] q_o[18]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[17] q_o[17]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] q_o[16]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[19] q_o[15]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] q_o[14]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[21] q_o[13]=$auto$memory_bram.cc:844:replace_memory$6863[22] q_o[12]=$auto$memory_bram.cc:844:replace_memory$6863[23] q_o[11]=$auto$memory_bram.cc:844:replace_memory$6863[24] q_o[10]=$auto$memory_bram.cc:844:replace_memory$6863[25] q_o[9]=$auto$memory_bram.cc:844:replace_memory$6863[26] q_o[8]=$auto$memory_bram.cc:844:replace_memory$6863[27] q_o[7]=$auto$memory_bram.cc:844:replace_memory$6863[28] q_o[6]=$auto$memory_bram.cc:844:replace_memory$6863[29] q_o[5]=$auto$memory_bram.cc:844:replace_memory$6863[30] q_o[4]=$auto$memory_bram.cc:844:replace_memory$6863[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6863[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6863[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6863[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6863[35] raddr_i[7]=dataCache_1.dataReadCmd_payload[3] raddr_i[6]=dataCache_1.dataReadCmd_payload[4] raddr_i[5]=dataCache_1.dataReadCmd_payload[5] raddr_i[4]=dataCache_1.dataReadCmd_payload[6] raddr_i[3]=dataCache_1.dataReadCmd_payload[7] raddr_i[2]=dataCache_1.dataReadCmd_payload[8] raddr_i[1]=dataCache_1.dataReadCmd_payload[9] raddr_i[0]=$false rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[7]=dataCache_1.tagsWriteCmd_payload_address[0] waddr_i[6]=dataCache_1.tagsWriteCmd_payload_address[1] waddr_i[5]=dataCache_1.tagsWriteCmd_payload_address[2] waddr_i[4]=dataCache_1.tagsWriteCmd_payload_address[3] waddr_i[3]=dataCache_1.tagsWriteCmd_payload_address[4] waddr_i[2]=dataCache_1.tagsWriteCmd_payload_address[5] waddr_i[1]=dataCache_1.tagsWriteCmd_payload_address[6] waddr_i[0]=$false wclk_i=clk wen_ni=dataCache_1._zz_2 +.names $false BranchPlugin_branchExceptionPort_payload_badAddr[0] +1 1 +.names $true CsrPlugin_interrupt_code[0] +1 1 +.names $true CsrPlugin_interrupt_code[1] +1 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[21] +1 1 +.names $false DBusCachedPlugin_redoBranch_payload[0] +1 1 +.names $false DBusCachedPlugin_redoBranch_payload[1] +1 1 +.names debug_bus_rsp_data[5] DebugPlugin_busReadDataReg[5] +1 1 +.names debug_bus_rsp_data[6] DebugPlugin_busReadDataReg[6] +1 1 +.names debug_bus_rsp_data[7] DebugPlugin_busReadDataReg[7] +1 1 +.names debug_bus_rsp_data[8] DebugPlugin_busReadDataReg[8] +1 1 +.names debug_bus_rsp_data[9] DebugPlugin_busReadDataReg[9] +1 1 +.names debug_bus_rsp_data[10] DebugPlugin_busReadDataReg[10] +1 1 +.names debug_bus_rsp_data[11] DebugPlugin_busReadDataReg[11] +1 1 +.names debug_bus_rsp_data[12] DebugPlugin_busReadDataReg[12] +1 1 +.names debug_bus_rsp_data[13] DebugPlugin_busReadDataReg[13] +1 1 +.names debug_bus_rsp_data[14] DebugPlugin_busReadDataReg[14] +1 1 +.names debug_bus_rsp_data[15] DebugPlugin_busReadDataReg[15] +1 1 +.names debug_bus_rsp_data[16] DebugPlugin_busReadDataReg[16] +1 1 +.names debug_bus_rsp_data[17] DebugPlugin_busReadDataReg[17] +1 1 +.names debug_bus_rsp_data[18] DebugPlugin_busReadDataReg[18] +1 1 +.names debug_bus_rsp_data[19] DebugPlugin_busReadDataReg[19] +1 1 +.names debug_bus_rsp_data[20] DebugPlugin_busReadDataReg[20] +1 1 +.names debug_bus_rsp_data[21] DebugPlugin_busReadDataReg[21] +1 1 +.names debug_bus_rsp_data[22] DebugPlugin_busReadDataReg[22] +1 1 +.names debug_bus_rsp_data[23] DebugPlugin_busReadDataReg[23] +1 1 +.names debug_bus_rsp_data[24] DebugPlugin_busReadDataReg[24] +1 1 +.names debug_bus_rsp_data[25] DebugPlugin_busReadDataReg[25] +1 1 +.names debug_bus_rsp_data[26] DebugPlugin_busReadDataReg[26] +1 1 +.names debug_bus_rsp_data[27] DebugPlugin_busReadDataReg[27] +1 1 +.names debug_bus_rsp_data[28] DebugPlugin_busReadDataReg[28] +1 1 +.names debug_bus_rsp_data[29] DebugPlugin_busReadDataReg[29] +1 1 +.names debug_bus_rsp_data[30] DebugPlugin_busReadDataReg[30] +1 1 +.names debug_bus_rsp_data[31] DebugPlugin_busReadDataReg[31] +1 1 +.names _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[2] +1 1 +.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[5] +1 1 +.names _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[7] +1 1 +.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[12] +1 1 +.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[31] +1 1 +.names $false IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[0] +1 1 +.names $false IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[1] +1 1 +.names $false IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[0] +1 1 +.names $false IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[1] +1 1 +.names $false IBusCachedPlugin_cache.lineLoader_address[0] +1 1 +.names $false IBusCachedPlugin_cache.lineLoader_address[1] +1 1 +.names iBus_cmd_payload_address[5] IBusCachedPlugin_cache.lineLoader_address[5] +1 1 +.names iBus_cmd_payload_address[6] IBusCachedPlugin_cache.lineLoader_address[6] +1 1 +.names iBus_cmd_payload_address[7] IBusCachedPlugin_cache.lineLoader_address[7] +1 1 +.names iBus_cmd_payload_address[8] IBusCachedPlugin_cache.lineLoader_address[8] +1 1 +.names iBus_cmd_payload_address[9] IBusCachedPlugin_cache.lineLoader_address[9] +1 1 +.names iBus_cmd_payload_address[10] IBusCachedPlugin_cache.lineLoader_address[10] +1 1 +.names iBus_cmd_payload_address[11] IBusCachedPlugin_cache.lineLoader_address[11] +1 1 +.names iBus_cmd_payload_address[12] IBusCachedPlugin_cache.lineLoader_address[12] +1 1 +.names iBus_cmd_payload_address[13] IBusCachedPlugin_cache.lineLoader_address[13] +1 1 +.names iBus_cmd_payload_address[14] IBusCachedPlugin_cache.lineLoader_address[14] +1 1 +.names iBus_cmd_payload_address[15] IBusCachedPlugin_cache.lineLoader_address[15] +1 1 +.names iBus_cmd_payload_address[16] IBusCachedPlugin_cache.lineLoader_address[16] +1 1 +.names iBus_cmd_payload_address[17] IBusCachedPlugin_cache.lineLoader_address[17] +1 1 +.names iBus_cmd_payload_address[18] IBusCachedPlugin_cache.lineLoader_address[18] +1 1 +.names iBus_cmd_payload_address[19] IBusCachedPlugin_cache.lineLoader_address[19] +1 1 +.names iBus_cmd_payload_address[20] IBusCachedPlugin_cache.lineLoader_address[20] +1 1 +.names iBus_cmd_payload_address[21] IBusCachedPlugin_cache.lineLoader_address[21] +1 1 +.names iBus_cmd_payload_address[22] IBusCachedPlugin_cache.lineLoader_address[22] +1 1 +.names iBus_cmd_payload_address[23] IBusCachedPlugin_cache.lineLoader_address[23] +1 1 +.names iBus_cmd_payload_address[24] IBusCachedPlugin_cache.lineLoader_address[24] +1 1 +.names iBus_cmd_payload_address[25] IBusCachedPlugin_cache.lineLoader_address[25] +1 1 +.names iBus_cmd_payload_address[26] IBusCachedPlugin_cache.lineLoader_address[26] +1 1 +.names iBus_cmd_payload_address[27] IBusCachedPlugin_cache.lineLoader_address[27] +1 1 +.names iBus_cmd_payload_address[28] IBusCachedPlugin_cache.lineLoader_address[28] +1 1 +.names iBus_cmd_payload_address[29] IBusCachedPlugin_cache.lineLoader_address[29] +1 1 +.names iBus_cmd_payload_address[30] IBusCachedPlugin_cache.lineLoader_address[30] +1 1 +.names iBus_cmd_payload_address[31] IBusCachedPlugin_cache.lineLoader_address[31] +1 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[7] +1 1 +.names $false IBusCachedPlugin_predictionJumpInterface_payload[0] +1 1 +.names _zz_10 IBusCachedPlugin_predictionJumpInterface_payload[1] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRspStaged_payload_data[0] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRspStaged_payload_data[1] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_W MmuPlugin_shared_dBusRspStaged_payload_data[2] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_shared_dBusRspStaged_payload_data[3] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_A MmuPlugin_shared_dBusRspStaged_payload_data[6] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRspStaged_payload_data[7] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[0] $auto$memory_bram.cc:844:replace_memory$6842[0] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[1] $auto$memory_bram.cc:844:replace_memory$6842[1] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[2] $auto$memory_bram.cc:844:replace_memory$6842[2] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[3] $auto$memory_bram.cc:844:replace_memory$6842[3] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[4] $auto$memory_bram.cc:844:replace_memory$6842[4] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[5] $auto$memory_bram.cc:844:replace_memory$6842[5] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[6] $auto$memory_bram.cc:844:replace_memory$6842[6] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[7] $auto$memory_bram.cc:844:replace_memory$6842[7] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[8] $auto$memory_bram.cc:844:replace_memory$6842[8] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[9] $auto$memory_bram.cc:844:replace_memory$6842[9] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[10] $auto$memory_bram.cc:844:replace_memory$6842[10] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[11] $auto$memory_bram.cc:844:replace_memory$6842[11] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[12] $auto$memory_bram.cc:844:replace_memory$6842[12] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[13] $auto$memory_bram.cc:844:replace_memory$6842[13] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[14] $auto$memory_bram.cc:844:replace_memory$6842[14] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[15] $auto$memory_bram.cc:844:replace_memory$6842[15] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[16] $auto$memory_bram.cc:844:replace_memory$6842[16] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[17] $auto$memory_bram.cc:844:replace_memory$6842[17] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[18] $auto$memory_bram.cc:844:replace_memory$6842[18] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[19] $auto$memory_bram.cc:844:replace_memory$6842[19] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[20] $auto$memory_bram.cc:844:replace_memory$6842[20] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[21] $auto$memory_bram.cc:844:replace_memory$6842[21] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[22] $auto$memory_bram.cc:844:replace_memory$6842[22] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[23] $auto$memory_bram.cc:844:replace_memory$6842[23] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[24] $auto$memory_bram.cc:844:replace_memory$6842[24] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[25] $auto$memory_bram.cc:844:replace_memory$6842[25] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[26] $auto$memory_bram.cc:844:replace_memory$6842[26] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[27] $auto$memory_bram.cc:844:replace_memory$6842[27] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[28] $auto$memory_bram.cc:844:replace_memory$6842[28] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[29] $auto$memory_bram.cc:844:replace_memory$6842[29] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[30] $auto$memory_bram.cc:844:replace_memory$6842[30] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[31] $auto$memory_bram.cc:844:replace_memory$6842[31] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] $auto$memory_bram.cc:844:replace_memory$6847[0] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] $auto$memory_bram.cc:844:replace_memory$6847[1] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] $auto$memory_bram.cc:844:replace_memory$6847[2] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] $auto$memory_bram.cc:844:replace_memory$6847[3] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] $auto$memory_bram.cc:844:replace_memory$6847[4] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] $auto$memory_bram.cc:844:replace_memory$6847[5] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] $auto$memory_bram.cc:844:replace_memory$6847[6] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] $auto$memory_bram.cc:844:replace_memory$6847[7] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] $auto$memory_bram.cc:844:replace_memory$6847[8] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] $auto$memory_bram.cc:844:replace_memory$6847[9] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] $auto$memory_bram.cc:844:replace_memory$6847[10] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] $auto$memory_bram.cc:844:replace_memory$6847[11] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] $auto$memory_bram.cc:844:replace_memory$6847[12] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] $auto$memory_bram.cc:844:replace_memory$6847[13] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] $auto$memory_bram.cc:844:replace_memory$6847[14] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] $auto$memory_bram.cc:844:replace_memory$6847[15] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] $auto$memory_bram.cc:844:replace_memory$6847[16] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] $auto$memory_bram.cc:844:replace_memory$6847[17] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] $auto$memory_bram.cc:844:replace_memory$6847[18] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] $auto$memory_bram.cc:844:replace_memory$6847[19] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] $auto$memory_bram.cc:844:replace_memory$6847[20] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] $auto$memory_bram.cc:844:replace_memory$6847[21] +1 1 +.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$6849[0] +1 1 +.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$6849[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$6849[2] +1 1 +.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$6849[3] +1 1 +.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$6849[4] +1 1 +.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$6849[5] +1 1 +.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$6849[6] +1 1 +.names _zz_RegFilePlugin_regFile_port1[7] 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_zz_writeBack_MulPlugin_result[25] +1 1 +.names _zz__zz_decode_RS2_2[26] _zz_writeBack_MulPlugin_result[26] +1 1 +.names _zz__zz_decode_RS2_2[27] _zz_writeBack_MulPlugin_result[27] +1 1 +.names _zz__zz_decode_RS2_2[28] _zz_writeBack_MulPlugin_result[28] +1 1 +.names _zz__zz_decode_RS2_2[29] _zz_writeBack_MulPlugin_result[29] +1 1 +.names _zz__zz_decode_RS2_2[30] _zz_writeBack_MulPlugin_result[30] +1 1 +.names _zz__zz_decode_RS2_2[31] _zz_writeBack_MulPlugin_result[31] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[51] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[52] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[53] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[54] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[55] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[56] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[57] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[58] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[59] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[60] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[61] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[62] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[63] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[64] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[0] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[1] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[2] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[3] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[4] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[5] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[6] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[7] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[8] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[9] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[10] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[11] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[12] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[13] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[14] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[15] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[16] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[17] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[18] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[19] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[20] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[21] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[22] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[23] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[24] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[25] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[26] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[27] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[28] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[29] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[30] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[31] +1 1 +.names $true dBus_cmd_payload_last +1 1 +.names dBus_cmd_payload_address[5] dataCache_1.dataWriteCmd_payload_address[3] +1 1 +.names dBus_cmd_payload_address[6] dataCache_1.dataWriteCmd_payload_address[4] +1 1 +.names dBus_cmd_payload_address[7] dataCache_1.dataWriteCmd_payload_address[5] +1 1 +.names dBus_cmd_payload_address[8] dataCache_1.dataWriteCmd_payload_address[6] +1 1 +.names dBus_cmd_payload_address[9] dataCache_1.dataWriteCmd_payload_address[7] +1 1 +.names dBus_cmd_payload_address[10] dataCache_1.dataWriteCmd_payload_address[8] +1 1 +.names dBus_cmd_payload_address[11] dataCache_1.dataWriteCmd_payload_address[9] +1 1 +.names dBus_cmd_payload_address[5] dataCache_1.stageB_mmuRsp_physicalAddress[5] +1 1 +.names dBus_cmd_payload_address[6] dataCache_1.stageB_mmuRsp_physicalAddress[6] +1 1 +.names dBus_cmd_payload_address[7] dataCache_1.stageB_mmuRsp_physicalAddress[7] +1 1 +.names dBus_cmd_payload_address[8] dataCache_1.stageB_mmuRsp_physicalAddress[8] +1 1 +.names dBus_cmd_payload_address[9] dataCache_1.stageB_mmuRsp_physicalAddress[9] +1 1 +.names dBus_cmd_payload_address[10] dataCache_1.stageB_mmuRsp_physicalAddress[10] +1 1 +.names dBus_cmd_payload_address[11] dataCache_1.stageB_mmuRsp_physicalAddress[11] +1 1 +.names dBus_cmd_payload_address[12] dataCache_1.stageB_mmuRsp_physicalAddress[12] +1 1 +.names dBus_cmd_payload_address[13] dataCache_1.stageB_mmuRsp_physicalAddress[13] +1 1 +.names dBus_cmd_payload_address[14] dataCache_1.stageB_mmuRsp_physicalAddress[14] +1 1 +.names dBus_cmd_payload_address[15] dataCache_1.stageB_mmuRsp_physicalAddress[15] +1 1 +.names dBus_cmd_payload_address[16] dataCache_1.stageB_mmuRsp_physicalAddress[16] +1 1 +.names dBus_cmd_payload_address[17] dataCache_1.stageB_mmuRsp_physicalAddress[17] +1 1 +.names dBus_cmd_payload_address[18] dataCache_1.stageB_mmuRsp_physicalAddress[18] +1 1 +.names dBus_cmd_payload_address[19] dataCache_1.stageB_mmuRsp_physicalAddress[19] +1 1 +.names dBus_cmd_payload_address[20] dataCache_1.stageB_mmuRsp_physicalAddress[20] +1 1 +.names dBus_cmd_payload_address[21] dataCache_1.stageB_mmuRsp_physicalAddress[21] +1 1 +.names dBus_cmd_payload_address[22] dataCache_1.stageB_mmuRsp_physicalAddress[22] +1 1 +.names dBus_cmd_payload_address[23] dataCache_1.stageB_mmuRsp_physicalAddress[23] +1 1 +.names dBus_cmd_payload_address[24] dataCache_1.stageB_mmuRsp_physicalAddress[24] +1 1 +.names dBus_cmd_payload_address[25] dataCache_1.stageB_mmuRsp_physicalAddress[25] +1 1 +.names dBus_cmd_payload_address[26] dataCache_1.stageB_mmuRsp_physicalAddress[26] +1 1 +.names dBus_cmd_payload_address[27] dataCache_1.stageB_mmuRsp_physicalAddress[27] +1 1 +.names dBus_cmd_payload_address[28] dataCache_1.stageB_mmuRsp_physicalAddress[28] +1 1 +.names dBus_cmd_payload_address[29] dataCache_1.stageB_mmuRsp_physicalAddress[29] +1 1 +.names dBus_cmd_payload_address[30] dataCache_1.stageB_mmuRsp_physicalAddress[30] +1 1 +.names dBus_cmd_payload_address[31] dataCache_1.stageB_mmuRsp_physicalAddress[31] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[25] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[26] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[27] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[28] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[29] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[30] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[31] +1 1 +.names execute_RS1[16] execute_MulPlugin_aHigh[0] +1 1 +.names execute_RS1[17] execute_MulPlugin_aHigh[1] +1 1 +.names execute_RS1[18] execute_MulPlugin_aHigh[2] +1 1 +.names execute_RS1[19] execute_MulPlugin_aHigh[3] +1 1 +.names execute_RS1[20] execute_MulPlugin_aHigh[4] +1 1 +.names execute_RS1[21] execute_MulPlugin_aHigh[5] +1 1 +.names execute_RS1[22] execute_MulPlugin_aHigh[6] +1 1 +.names execute_RS1[23] execute_MulPlugin_aHigh[7] +1 1 +.names execute_RS1[24] execute_MulPlugin_aHigh[8] +1 1 +.names execute_RS1[25] execute_MulPlugin_aHigh[9] +1 1 +.names execute_RS1[26] execute_MulPlugin_aHigh[10] +1 1 +.names execute_RS1[27] execute_MulPlugin_aHigh[11] +1 1 +.names execute_RS1[28] execute_MulPlugin_aHigh[12] +1 1 +.names execute_RS1[29] execute_MulPlugin_aHigh[13] +1 1 +.names execute_RS1[30] execute_MulPlugin_aHigh[14] +1 1 +.names execute_RS1[31] execute_MulPlugin_aHigh[15] +1 1 +.names execute_RS2[16] execute_MulPlugin_bHigh[0] +1 1 +.names execute_RS2[17] execute_MulPlugin_bHigh[1] +1 1 +.names execute_RS2[18] execute_MulPlugin_bHigh[2] +1 1 +.names execute_RS2[19] execute_MulPlugin_bHigh[3] +1 1 +.names execute_RS2[20] execute_MulPlugin_bHigh[4] +1 1 +.names execute_RS2[21] execute_MulPlugin_bHigh[5] +1 1 +.names execute_RS2[22] execute_MulPlugin_bHigh[6] +1 1 +.names execute_RS2[23] execute_MulPlugin_bHigh[7] +1 1 +.names execute_RS2[24] execute_MulPlugin_bHigh[8] +1 1 +.names execute_RS2[25] execute_MulPlugin_bHigh[9] +1 1 +.names execute_RS2[26] execute_MulPlugin_bHigh[10] +1 1 +.names execute_RS2[27] execute_MulPlugin_bHigh[11] +1 1 +.names execute_RS2[28] execute_MulPlugin_bHigh[12] +1 1 +.names execute_RS2[29] execute_MulPlugin_bHigh[13] +1 1 +.names execute_RS2[30] execute_MulPlugin_bHigh[14] +1 1 +.names execute_RS2[31] execute_MulPlugin_bHigh[15] +1 1 +.names $false execute_to_memory_PC[0] +1 1 +.names $false execute_to_memory_PC[1] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[0] execute_to_memory_PC[2] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[1] execute_to_memory_PC[3] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[2] execute_to_memory_PC[4] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[3] execute_to_memory_PC[5] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[4] execute_to_memory_PC[6] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[5] execute_to_memory_PC[7] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[6] execute_to_memory_PC[8] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[7] execute_to_memory_PC[9] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[8] execute_to_memory_PC[10] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[9] execute_to_memory_PC[11] +1 1 +.names $false iBus_cmd_payload_address[0] +1 1 +.names $false iBus_cmd_payload_address[1] +1 1 +.names $false iBus_cmd_payload_address[2] +1 1 +.names $false iBus_cmd_payload_address[3] +1 1 +.names $false iBus_cmd_payload_address[4] +1 1 +.names $true iBus_cmd_payload_size[0] +1 1 +.names $false iBus_cmd_payload_size[1] +1 1 +.names $true iBus_cmd_payload_size[2] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] memory_DivPlugin_accumulator[0] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] memory_DivPlugin_accumulator[1] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] memory_DivPlugin_accumulator[2] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] memory_DivPlugin_accumulator[3] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] memory_DivPlugin_accumulator[4] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] memory_DivPlugin_accumulator[5] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] memory_DivPlugin_accumulator[6] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] memory_DivPlugin_accumulator[7] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] memory_DivPlugin_accumulator[8] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] memory_DivPlugin_accumulator[9] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] memory_DivPlugin_accumulator[10] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] memory_DivPlugin_accumulator[11] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] memory_DivPlugin_accumulator[12] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] memory_DivPlugin_accumulator[13] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] memory_DivPlugin_accumulator[14] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] memory_DivPlugin_accumulator[15] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] memory_DivPlugin_accumulator[16] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] memory_DivPlugin_accumulator[17] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] memory_DivPlugin_accumulator[18] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] memory_DivPlugin_accumulator[19] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] memory_DivPlugin_accumulator[20] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] memory_DivPlugin_accumulator[21] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] memory_DivPlugin_accumulator[22] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] memory_DivPlugin_accumulator[23] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] memory_DivPlugin_accumulator[24] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] memory_DivPlugin_accumulator[25] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] memory_DivPlugin_accumulator[26] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] memory_DivPlugin_accumulator[27] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] memory_DivPlugin_accumulator[28] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] memory_DivPlugin_accumulator[29] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] memory_DivPlugin_accumulator[30] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif new file mode 100644 index 00000000000..d81a68f31e7 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif @@ -0,0 +1,10133 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model VexRiscv +.inputs iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_error iBus_rsp_payload_inst[0] iBus_rsp_payload_inst[1] iBus_rsp_payload_inst[2] iBus_rsp_payload_inst[3] iBus_rsp_payload_inst[4] iBus_rsp_payload_inst[5] iBus_rsp_payload_inst[6] iBus_rsp_payload_inst[7] iBus_rsp_payload_inst[8] iBus_rsp_payload_inst[9] iBus_rsp_payload_inst[10] iBus_rsp_payload_inst[11] iBus_rsp_payload_inst[12] iBus_rsp_payload_inst[13] iBus_rsp_payload_inst[14] iBus_rsp_payload_inst[15] iBus_rsp_payload_inst[16] iBus_rsp_payload_inst[17] iBus_rsp_payload_inst[18] iBus_rsp_payload_inst[19] iBus_rsp_payload_inst[20] iBus_rsp_payload_inst[21] iBus_rsp_payload_inst[22] iBus_rsp_payload_inst[23] iBus_rsp_payload_inst[24] iBus_rsp_payload_inst[25] iBus_rsp_payload_inst[26] iBus_rsp_payload_inst[27] iBus_rsp_payload_inst[28] iBus_rsp_payload_inst[29] iBus_rsp_payload_inst[30] iBus_rsp_payload_inst[31] timerInterrupt externalInterrupt softwareInterrupt dBus_cmd_ready dBus_rsp_ready dBus_rsp_error dBus_rsp_data[0] dBus_rsp_data[1] dBus_rsp_data[2] dBus_rsp_data[3] dBus_rsp_data[4] dBus_rsp_data[5] dBus_rsp_data[6] dBus_rsp_data[7] dBus_rsp_data[8] dBus_rsp_data[9] dBus_rsp_data[10] dBus_rsp_data[11] dBus_rsp_data[12] dBus_rsp_data[13] dBus_rsp_data[14] dBus_rsp_data[15] dBus_rsp_data[16] dBus_rsp_data[17] dBus_rsp_data[18] dBus_rsp_data[19] dBus_rsp_data[20] dBus_rsp_data[21] dBus_rsp_data[22] dBus_rsp_data[23] dBus_rsp_data[24] dBus_rsp_data[25] dBus_rsp_data[26] dBus_rsp_data[27] dBus_rsp_data[28] dBus_rsp_data[29] dBus_rsp_data[30] dBus_rsp_data[31] clk reset +.outputs iBus_cmd_valid iBus_cmd_payload_pc[0] iBus_cmd_payload_pc[1] iBus_cmd_payload_pc[2] iBus_cmd_payload_pc[3] iBus_cmd_payload_pc[4] iBus_cmd_payload_pc[5] iBus_cmd_payload_pc[6] iBus_cmd_payload_pc[7] iBus_cmd_payload_pc[8] iBus_cmd_payload_pc[9] iBus_cmd_payload_pc[10] iBus_cmd_payload_pc[11] iBus_cmd_payload_pc[12] iBus_cmd_payload_pc[13] iBus_cmd_payload_pc[14] iBus_cmd_payload_pc[15] iBus_cmd_payload_pc[16] iBus_cmd_payload_pc[17] iBus_cmd_payload_pc[18] iBus_cmd_payload_pc[19] iBus_cmd_payload_pc[20] iBus_cmd_payload_pc[21] iBus_cmd_payload_pc[22] iBus_cmd_payload_pc[23] iBus_cmd_payload_pc[24] iBus_cmd_payload_pc[25] iBus_cmd_payload_pc[26] iBus_cmd_payload_pc[27] iBus_cmd_payload_pc[28] iBus_cmd_payload_pc[29] iBus_cmd_payload_pc[30] iBus_cmd_payload_pc[31] dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] +.names $false +.names $true +1 +.names $undef +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1273 iBus_cmd_payload_pc[30] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$new_n1255 $abc$8788$new_n1254 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$new_n1256 $abc$8788$new_n1255 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$new_n1257 $abc$8788$new_n1256 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1257 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1258 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1259 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1260 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1261 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$new_n1263 $abc$8788$new_n1262 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$new_n1264 $abc$8788$new_n1263 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$new_n1265 $abc$8788$new_n1264 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$new_n1266 $abc$8788$new_n1265 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$new_n1267 $abc$8788$new_n1266 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$new_n1268 $abc$8788$new_n1267 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$new_n1269 $abc$8788$new_n1268 +111 1 +.names IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$new_n1269 +111 1 +.names $abc$8788$new_n1271 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$8788$new_n1270 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1272 lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1271 +000 1 +001 1 +010 1 +.names CsrPlugin_interrupt_valid CsrPlugin_pipelineLiberator_done $abc$8788$new_n1272 +11 1 +.names BranchPlugin_jumpInterface_payload[30] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[30] $abc$8788$new_n1273 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_writeBack_ENV_CTRL lastStageIsFiring _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] $abc$8788$new_n1274 +1111 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[30] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$6999 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n2461 $abc$8788$new_n1270 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1276 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$8788$new_n2464 $abc$8788$new_n1296 $abc$8788$new_n1278 +10 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] execute_to_memory_INSTRUCTION[7] $abc$8788$new_n1283 +1100 1 +1111 1 +.names $abc$8788$new_n1286 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n1285 +10000 1 +10011 1 +11100 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n1286 +00 1 +11 1 +.names $abc$8788$new_n1289 HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1288 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n1290 HazardSimplePlugin_writeBackBuffer_valid HazardSimplePlugin_writeBackBuffer_payload_address[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1289 +1100 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1290 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_lastStageRegFileWrite_valid lastStageIsFiring HazardSimplePlugin_writeBackWrites_valid +11 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1296 +11 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n1304 +1100 1 +1111 1 +.names $abc$8788$new_n1317 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1316 $abc$8788$new_n1315 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1316 +10 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1317 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE dBus_rsp_ready execute_to_memory_MEMORY_STORE $abc$8788$new_n1321 +1100 1 +.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$8788$new_n1322 +11 1 +.names execute_arbitration_isValid $abc$8788$new_n1324 _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1323 +1001 1 +1010 1 +1011 1 +.names decode_to_execute_SRC2[0] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1324 +00000 1 +.names $abc$8788$new_n1327 $abc$8788$new_n1326 $abc$8788$new_n1325 +11 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] $abc$8788$new_n1326 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[4] execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1327 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8788$new_n1329 _zz_memory_ENV_CTRL memory_arbitration_isValid lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1328 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid execute_arbitration_isValid _zz_execute_ENV_CTRL $abc$8788$new_n1329 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n1330 +00001 1 +00010 1 +00011 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1332 iBus_cmd_payload_pc[29] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[29] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[29] $abc$8788$new_n1332 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[29] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7001 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1335 iBus_cmd_payload_pc[28] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[28] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[28] $abc$8788$new_n1335 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[28] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7003 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1338 iBus_cmd_payload_pc[27] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[27] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[27] $abc$8788$new_n1338 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[27] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7005 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1341 iBus_cmd_payload_pc[26] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[26] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[26] $abc$8788$new_n1341 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[26] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7007 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1344 iBus_cmd_payload_pc[25] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[25] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[25] $abc$8788$new_n1344 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[25] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7009 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1347 iBus_cmd_payload_pc[24] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[24] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[24] $abc$8788$new_n1347 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[24] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7011 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1350 iBus_cmd_payload_pc[23] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[23] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[23] $abc$8788$new_n1350 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[23] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7013 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1353 iBus_cmd_payload_pc[22] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[22] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[22] $abc$8788$new_n1353 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[22] IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7015 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1356 iBus_cmd_payload_pc[21] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[21] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[21] $abc$8788$new_n1356 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[21] IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7017 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1359 iBus_cmd_payload_pc[20] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[20] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[20] $abc$8788$new_n1359 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[20] IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7019 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1362 iBus_cmd_payload_pc[19] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[19] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[19] $abc$8788$new_n1362 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[19] IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7021 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1365 iBus_cmd_payload_pc[18] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[18] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[18] $abc$8788$new_n1365 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[18] IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7023 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1368 iBus_cmd_payload_pc[17] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[17] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[17] $abc$8788$new_n1368 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[17] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7025 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1371 iBus_cmd_payload_pc[16] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[16] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[16] $abc$8788$new_n1371 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[16] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7027 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1374 iBus_cmd_payload_pc[15] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[15] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[15] $abc$8788$new_n1374 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[15] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7029 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1377 iBus_cmd_payload_pc[14] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[14] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[14] $abc$8788$new_n1377 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[14] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7031 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1380 iBus_cmd_payload_pc[13] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[13] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[13] $abc$8788$new_n1380 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[13] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7033 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1383 iBus_cmd_payload_pc[12] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[12] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[12] $abc$8788$new_n1383 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[12] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7035 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1386 iBus_cmd_payload_pc[11] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[11] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[11] $abc$8788$new_n1386 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[11] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7037 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1389 iBus_cmd_payload_pc[10] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[10] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[10] $abc$8788$new_n1389 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[10] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7039 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1392 iBus_cmd_payload_pc[9] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[9] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[9] $abc$8788$new_n1392 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[9] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7041 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1395 iBus_cmd_payload_pc[8] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[8] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[8] $abc$8788$new_n1395 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[8] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7043 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1398 iBus_cmd_payload_pc[7] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[7] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[7] $abc$8788$new_n1398 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[7] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7045 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1401 iBus_cmd_payload_pc[6] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[6] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[6] $abc$8788$new_n1401 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[6] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7047 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1404 iBus_cmd_payload_pc[5] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$8788$new_n1271 BranchPlugin_jumpInterface_payload[5] $abc$8788$new_n1274 CsrPlugin_mepc[5] $abc$8788$new_n1404 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[5] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7049 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1407 iBus_cmd_payload_pc[4] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[4] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[4] $abc$8788$new_n1407 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[4] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7051 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1410 iBus_cmd_payload_pc[3] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[3] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[3] $abc$8788$new_n1410 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[3] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7053 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1413 iBus_cmd_payload_pc[2] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[2] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[2] $abc$8788$new_n1413 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[2] IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7055 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[30] CsrPlugin_mepc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7439 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[29] CsrPlugin_mepc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7441 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[28] CsrPlugin_mepc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7443 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[27] CsrPlugin_mepc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7445 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[26] CsrPlugin_mepc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7447 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[25] CsrPlugin_mepc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7449 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[24] CsrPlugin_mepc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7451 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[23] CsrPlugin_mepc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7453 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[22] CsrPlugin_mepc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7455 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[21] CsrPlugin_mepc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7457 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[20] CsrPlugin_mepc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7459 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[19] CsrPlugin_mepc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7461 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[18] CsrPlugin_mepc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7463 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[17] CsrPlugin_mepc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7465 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[16] CsrPlugin_mepc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7467 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[15] CsrPlugin_mepc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7469 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[14] CsrPlugin_mepc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7471 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[13] CsrPlugin_mepc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7473 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[12] CsrPlugin_mepc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7475 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[11] CsrPlugin_mepc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7477 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[10] CsrPlugin_mepc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7479 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[9] CsrPlugin_mepc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7481 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[8] CsrPlugin_mepc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7483 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[7] CsrPlugin_mepc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7485 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[6] CsrPlugin_mepc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7487 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[5] CsrPlugin_mepc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7489 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[4] CsrPlugin_mepc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7491 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[3] CsrPlugin_mepc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7493 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[2] CsrPlugin_mepc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7495 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1446 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7497 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1321 $abc$8788$new_n1445 +10 1 +.names $abc$8788$new_n1447 $abc$8788$new_n1326 $abc$8788$new_n1446 +11 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[0] decode_to_execute_SRC2[0] $abc$8788$new_n1447 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1449 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7499 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$new_n1449 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7501 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_amplitudeReg[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7503 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7741 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n1454 $abc$8788$new_n1453 +11 1 +.names $abc$8788$new_n1455 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n1454 +1000 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n2461 $abc$8788$new_n1455 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7743 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7745 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7747 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7749 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] iBus_rsp_payload_inst[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7751 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7753 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7755 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7757 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7759 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7761 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7763 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7765 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7767 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7769 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7771 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] iBus_rsp_payload_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7773 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7775 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7777 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7779 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7781 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7783 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] iBus_rsp_payload_inst[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7785 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] iBus_rsp_payload_inst[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7787 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7789 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7791 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7793 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7795 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7797 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[2] CsrPlugin_mcause_exceptionCode[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7861 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 $abc$8788$new_n1445 $abc$8788$new_n1325 execute_LightShifterPlugin_isActive $abc$8788$auto$rtlil.cc:2693:MuxGate$7863 +1001 1 +1011 1 +1100 1 +1101 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid CsrPlugin_pipelineLiberator_pcValids_1 $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7865 +1111 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n1488 $abc$8788$auto$rtlil.cc:2693:MuxGate$7867 +1110 1 +.names $abc$8788$new_n1321 CsrPlugin_pipelineLiberator_pcValids_1 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$new_n1488 +000 1 +010 1 +100 1 +101 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n2458 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$auto$rtlil.cc:2693:MuxGate$7869 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1492 CsrPlugin_mie_MSIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7871 +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_772 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n1491 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1493 $abc$8788$new_n1492 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1494 execute_CsrPlugin_csr_772 CsrPlugin_mie_MSIE execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MIE $abc$8788$new_n1493 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[3] CsrPlugin_mip_MSIP execute_CsrPlugin_csr_836 $abc$8788$new_n1494 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1496 CsrPlugin_mie_MTIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7873 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1497 $abc$8788$new_n1496 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1498 execute_CsrPlugin_csr_836 CsrPlugin_mip_MTIP $abc$8788$new_n1497 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MTIE CsrPlugin_mstatus_MPIE execute_CsrPlugin_csr_768 $abc$8788$new_n1498 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1500 CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7875 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[11] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1501 $abc$8788$new_n1500 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1502 execute_CsrPlugin_csr_836 CsrPlugin_mip_MEIP $abc$8788$new_n1501 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MEIE CsrPlugin_mstatus_MPP[0] execute_CsrPlugin_csr_768 $abc$8788$new_n1502 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_injector_decodeInput_valid IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7877 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1270 $abc$8788$new_n1505 $abc$8788$new_n2461 $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7879 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names iBus_cmd_ready iBus_cmd_valid $abc$8788$new_n1505 +11 1 +.names $abc$8788$new_n1507 $abc$8788$new_n2461 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid iBus_cmd_valid +1100 1 +1110 1 +1111 1 +.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n1271 IBusSimplePlugin_pending_value[2] IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[0] $abc$8788$new_n1507 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8788$new_n1509 $abc$8788$new_n1505 $abc$8788$auto$rtlil.cc:2693:MuxGate$7881 +01 1 +10 1 +11 1 +.names IBusSimplePlugin_fetchPc_inc $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$new_n1509 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names $abc$8788$new_n1271 $abc$8788$new_n1321 $abc$8788$new_n2458 execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7883 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2461 execute_arbitration_isValid $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7885 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive $abc$8788$new_n1513 execute_LightShifterPlugin_amplitudeReg[4] $abc$8788$new_n1445 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7949 +00100 1 +00101 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1445 execute_LightShifterPlugin_isActive $abc$8788$new_n1446 execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$new_n1513 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1516 $abc$8788$new_n1517 CsrPlugin_interrupt_code[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7953 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_mstatus_MIE $abc$8788$new_n1517 CsrPlugin_mip_MTIP CsrPlugin_mie_MTIE $abc$8788$new_n1516 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names CsrPlugin_mip_MSIP CsrPlugin_mie_MSIE CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$8788$new_n1517 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1516 CsrPlugin_interrupt_code[3] CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7957 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$8788$new_n1330 $abc$8788$new_n1455 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$auto$rtlil.cc:2693:MuxGate$7961 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7963 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[31] $abc$8788$new_n1522 $abc$8788$new_n1523 iBus_cmd_payload_pc[31] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$new_n1255 $abc$8788$new_n1522 +11111 1 +.names BranchPlugin_jumpInterface_payload[31] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[31] $abc$8788$new_n1523 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[31] IBusSimplePlugin_fetchPc_pcReg[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7967 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[3] CsrPlugin_mcause_exceptionCode[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7969 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[31] CsrPlugin_mepc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7975 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1594 $abc$8788$new_n1590 dBus_cmd_payload_address[30] $abc$8788$new_n1595 $abc$8788$auto$rtlil.cc:2693:MuxGate$7057 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1529 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[30] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 $abc$8788$new_n1529 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1584 $abc$8788$new_n1531 $abc$8788$new_n1530 +00 1 +.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1581 $abc$8788$new_n1531 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1533 $abc$8788$new_n1580 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1578 $abc$8788$new_n1532 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1534 $abc$8788$new_n1577 _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1575 $abc$8788$new_n1533 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1535 $abc$8788$new_n1574 _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1572 $abc$8788$new_n1534 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1536 $abc$8788$new_n1569 _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1570 $abc$8788$new_n1535 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1537 $abc$8788$new_n1568 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1565 $abc$8788$new_n1536 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1538 $abc$8788$new_n1564 _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1562 $abc$8788$new_n1537 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1559 $abc$8788$new_n1557 $abc$8788$new_n1561 $abc$8788$new_n1560 $abc$8788$new_n1539 $abc$8788$new_n1538 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1540 $abc$8788$new_n1539 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1554 $abc$8788$new_n1541 $abc$8788$new_n1553 $abc$8788$new_n1540 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1542 $abc$8788$new_n1541 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n1548 _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1549 $abc$8788$new_n1543 $abc$8788$new_n1542 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[3] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1544 $abc$8788$new_n1543 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[3] $abc$8788$new_n1544 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[2] $abc$8788$new_n1545 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[1] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[1] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1546 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01100 1 +10100 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[5] $abc$8788$new_n1547 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[4] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[4] $abc$8788$new_n1548 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[4] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[4] $abc$8788$new_n1549 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[7] $abc$8788$new_n1550 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[6] $abc$8788$new_n1551 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[9] $abc$8788$new_n1552 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[8] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[8] $abc$8788$new_n1553 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n1554 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[11] $abc$8788$new_n1555 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[10] $abc$8788$new_n1556 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1558 $abc$8788$new_n1557 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[12] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[12] $abc$8788$new_n1558 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n1559 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n1560 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] $abc$8788$new_n1561 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n1562 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[15] $abc$8788$new_n1563 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1564 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1565 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[18] $abc$8788$new_n1566 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[17] $abc$8788$new_n1567 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1568 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1569 +10 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n1570 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[19] $abc$8788$new_n1571 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n1572 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[21] $abc$8788$new_n1573 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1574 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n1575 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[23] $abc$8788$new_n1576 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1577 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n1578 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[25] $abc$8788$new_n1579 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1580 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n1581 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[27] $abc$8788$new_n1582 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[26] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[26] $abc$8788$new_n1583 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1584 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[29] $abc$8788$new_n1585 +00 1 +11 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1587 $abc$8788$new_n1586 +11 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1323 $abc$8788$new_n1587 +00 1 +.names $abc$8788$new_n1589 $abc$8788$new_n1322 $abc$8788$new_n1588 +00 1 +.names _zz_execute_ALU_CTRL[0] _zz_execute_ALU_CTRL[1] $abc$8788$new_n1589 +10 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[30] $abc$8788$new_n1323 $abc$8788$new_n1591 $abc$8788$new_n1590 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1593 execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n1591 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1592 +10 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[29] _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1593 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1594 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11100 1 +11111 1 +.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$8788$new_n1595 +10 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1598 dBus_cmd_payload_address[29] $abc$8788$new_n1601 $abc$8788$auto$rtlil.cc:2693:MuxGate$7059 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[29] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[29] $abc$8788$new_n1323 $abc$8788$new_n1599 $abc$8788$new_n1598 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1600 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n1599 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[28] _zz_execute_SrcPlugin_addSub_2[28] $abc$8788$new_n1600 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1601 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1605 dBus_cmd_payload_address[28] $abc$8788$new_n1608 $abc$8788$auto$rtlil.cc:2693:MuxGate$7061 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1604 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[28] +00000 1 +00110 1 +01010 1 +01100 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1604 +0000 1 +0001 1 +0011 1 +0101 1 +1001 1 +1101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[28] $abc$8788$new_n1323 $abc$8788$new_n1606 $abc$8788$new_n1605 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 $abc$8788$new_n1607 $abc$8788$new_n1593 $abc$8788$new_n1606 +001 1 +011 1 +110 1 +111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[27] _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1607 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1608 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1611 dBus_cmd_payload_address[27] $abc$8788$new_n1614 $abc$8788$auto$rtlil.cc:2693:MuxGate$7063 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1583 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1532 dBus_cmd_payload_address[27] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[27] $abc$8788$new_n1323 $abc$8788$new_n1612 $abc$8788$new_n1611 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 $abc$8788$new_n1613 $abc$8788$new_n1600 $abc$8788$new_n1612 +001 1 +011 1 +110 1 +111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[26] _zz_execute_SrcPlugin_addSub_2[26] $abc$8788$new_n1613 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1614 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1618 dBus_cmd_payload_address[26] $abc$8788$new_n1620 $abc$8788$auto$rtlil.cc:2693:MuxGate$7065 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1617 _zz_execute_SrcPlugin_addSub_2[26] dBus_cmd_payload_address[26] +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1578 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 $abc$8788$new_n1533 $abc$8788$new_n1617 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[26] $abc$8788$new_n1323 $abc$8788$new_n1619 $abc$8788$new_n1618 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1607 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1619 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1620 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1622 execute_to_memory_REGFILE_WRITE_DATA[25] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7067 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1624 $abc$8788$new_n1626 $abc$8788$new_n1586 dBus_cmd_payload_address[25] $abc$8788$new_n1595 $abc$8788$new_n1622 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1533 dBus_cmd_payload_address[25] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1625 $abc$8788$new_n1613 $abc$8788$new_n1624 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[24] _zz_execute_SrcPlugin_addSub_2[24] $abc$8788$new_n1625 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1626 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1631 dBus_cmd_payload_address[24] $abc$8788$new_n1634 $abc$8788$auto$rtlil.cc:2693:MuxGate$7069 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1629 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[24] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 $abc$8788$new_n1629 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1577 $abc$8788$new_n1534 $abc$8788$new_n1630 +00 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[24] $abc$8788$new_n1323 $abc$8788$new_n1632 $abc$8788$new_n1631 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1633 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1632 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[23] _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1633 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1634 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1636 execute_to_memory_REGFILE_WRITE_DATA[23] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7071 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1638 $abc$8788$new_n1640 $abc$8788$new_n1586 dBus_cmd_payload_address[23] $abc$8788$new_n1595 $abc$8788$new_n1636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[23] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1639 $abc$8788$new_n1625 $abc$8788$new_n1638 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[22] _zz_execute_SrcPlugin_addSub_2[22] $abc$8788$new_n1639 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1640 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1642 execute_to_memory_REGFILE_WRITE_DATA[22] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7073 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1646 $abc$8788$new_n1648 $abc$8788$new_n1586 dBus_cmd_payload_address[22] $abc$8788$new_n1595 $abc$8788$new_n1642 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1644 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[22] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 $abc$8788$new_n1644 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1574 $abc$8788$new_n1535 $abc$8788$new_n1645 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1647 $abc$8788$new_n1633 $abc$8788$new_n1646 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[21] _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1647 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1648 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1653 $abc$8788$new_n1650 $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7075 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 dBus_cmd_payload_address[21] $abc$8788$new_n1652 $abc$8788$new_n1650 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[21] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1652 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1654 $abc$8788$new_n1639 $abc$8788$new_n1653 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[20] _zz_execute_SrcPlugin_addSub_2[20] $abc$8788$new_n1654 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1656 execute_to_memory_REGFILE_WRITE_DATA[20] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7077 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1660 $abc$8788$new_n1662 $abc$8788$new_n1586 dBus_cmd_payload_address[20] $abc$8788$new_n1595 $abc$8788$new_n1656 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1658 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[20] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 $abc$8788$new_n1658 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1569 $abc$8788$new_n1536 $abc$8788$new_n1659 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1661 $abc$8788$new_n1647 $abc$8788$new_n1660 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[19] _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1661 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1662 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1664 execute_to_memory_REGFILE_WRITE_DATA[19] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7079 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1666 $abc$8788$new_n1586 $abc$8788$new_n1668 $abc$8788$new_n1595 dBus_cmd_payload_address[19] $abc$8788$new_n1664 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[19] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1667 $abc$8788$new_n1654 $abc$8788$new_n1666 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[18] _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1667 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1668 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11100 1 +11111 1 +.names $abc$8788$new_n1670 execute_to_memory_REGFILE_WRITE_DATA[18] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7081 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1673 $abc$8788$new_n1675 $abc$8788$new_n1586 dBus_cmd_payload_address[18] $abc$8788$new_n1595 $abc$8788$new_n1670 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1672 _zz_execute_SrcPlugin_addSub_2[18] dBus_cmd_payload_address[18] +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1565 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 $abc$8788$new_n1537 $abc$8788$new_n1672 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1674 $abc$8788$new_n1661 $abc$8788$new_n1673 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[17] _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1674 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1675 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1678 dBus_cmd_payload_address[17] $abc$8788$new_n1680 $abc$8788$auto$rtlil.cc:2693:MuxGate$7083 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1537 dBus_cmd_payload_address[17] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[17] $abc$8788$new_n1323 $abc$8788$new_n1679 $abc$8788$new_n1678 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1667 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1680 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1682 execute_to_memory_REGFILE_WRITE_DATA[16] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7085 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1686 $abc$8788$new_n1688 $abc$8788$new_n1586 dBus_cmd_payload_address[16] $abc$8788$new_n1595 $abc$8788$new_n1682 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1684 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[16] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 $abc$8788$new_n1684 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1564 $abc$8788$new_n1538 $abc$8788$new_n1685 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1687 $abc$8788$new_n1674 $abc$8788$new_n1686 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[15] _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1687 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1688 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1691 dBus_cmd_payload_address[15] $abc$8788$new_n1694 $abc$8788$auto$rtlil.cc:2693:MuxGate$7087 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[15] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[15] $abc$8788$new_n1323 $abc$8788$new_n1692 $abc$8788$new_n1691 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1693 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1692 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[14] _zz_execute_SrcPlugin_addSub_2[14] $abc$8788$new_n1693 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1694 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1696 execute_to_memory_REGFILE_WRITE_DATA[14] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7089 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1700 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[14] $abc$8788$new_n1702 $abc$8788$new_n1696 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1698 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[14] +00000 1 +00110 1 +01010 1 +01100 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1557 $abc$8788$new_n1699 $abc$8788$new_n1560 $abc$8788$new_n1698 +000 1 +001 1 +010 1 +.names $abc$8788$new_n1561 $abc$8788$new_n1539 $abc$8788$new_n1699 +10 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1701 $abc$8788$new_n1687 $abc$8788$new_n1700 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1701 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1702 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1704 execute_to_memory_REGFILE_WRITE_DATA[13] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7091 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1706 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[13] $abc$8788$new_n1708 $abc$8788$new_n1704 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1560 $abc$8788$new_n1558 $abc$8788$new_n1699 _zz_execute_SrcPlugin_addSub_2[13] dBus_cmd_payload_address[13] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1707 $abc$8788$new_n1693 $abc$8788$new_n1706 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[12] _zz_execute_SrcPlugin_addSub_2[12] $abc$8788$new_n1707 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1708 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1710 execute_to_memory_REGFILE_WRITE_DATA[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7093 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1711 $abc$8788$new_n1592 $abc$8788$new_n1323 $abc$8788$new_n1715 $abc$8788$new_n1701 $abc$8788$new_n1710 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$8788$new_n1713 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[12] $abc$8788$new_n1714 $abc$8788$new_n1711 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1539 $abc$8788$new_n1561 _zz_execute_SrcPlugin_addSub_2[12] dBus_cmd_payload_address[12] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1323 execute_CsrPlugin_csr_768 $abc$8788$new_n1322 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1713 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1714 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[11] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1715 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1717 execute_to_memory_REGFILE_WRITE_DATA[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7095 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1722 $abc$8788$new_n1718 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1501 $abc$8788$new_n1717 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[11] $abc$8788$new_n1721 $abc$8788$new_n1718 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1720 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[11] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1540 $abc$8788$new_n1720 +000 1 +100 1 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1721 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1723 $abc$8788$new_n1707 $abc$8788$new_n1722 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[10] _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1723 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1725 execute_to_memory_REGFILE_WRITE_DATA[10] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7097 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1727 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[10] $abc$8788$new_n1729 $abc$8788$new_n1725 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1556 $abc$8788$new_n1540 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[10] +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1728 $abc$8788$new_n1715 $abc$8788$new_n1727 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[9] _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1728 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1729 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[9] $abc$8788$new_n1731 $abc$8788$new_n1735 $abc$8788$auto$rtlil.cc:2693:MuxGate$7099 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1734 dBus_cmd_payload_address[9] $abc$8788$new_n1595 $abc$8788$new_n1731 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1733 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[9] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1553 $abc$8788$new_n1541 $abc$8788$new_n1554 $abc$8788$new_n1733 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1734 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1736 $abc$8788$new_n1723 $abc$8788$new_n1735 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[8] _zz_execute_SrcPlugin_addSub_2[8] $abc$8788$new_n1736 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[8] $abc$8788$new_n1738 $abc$8788$new_n1741 $abc$8788$auto$rtlil.cc:2693:MuxGate$7101 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1740 dBus_cmd_payload_address[8] $abc$8788$new_n1595 $abc$8788$new_n1738 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1541 $abc$8788$new_n1554 _zz_execute_SrcPlugin_addSub_2[8] dBus_cmd_payload_address[8] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1740 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1742 $abc$8788$new_n1728 $abc$8788$new_n1741 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[7] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1742 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1744 execute_to_memory_REGFILE_WRITE_DATA[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7103 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1749 $abc$8788$new_n1745 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1497 $abc$8788$new_n1744 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1748 dBus_cmd_payload_address[7] $abc$8788$new_n1595 $abc$8788$new_n1745 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1747 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[7] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1542 $abc$8788$new_n1747 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1748 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1750 $abc$8788$new_n1736 $abc$8788$new_n1749 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[6] _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1750 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1752 execute_to_memory_REGFILE_WRITE_DATA[6] $abc$8788$new_n1323 $abc$8788$new_n1755 $abc$8788$auto$rtlil.cc:2693:MuxGate$7105 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1754 dBus_cmd_payload_address[6] $abc$8788$new_n1595 $abc$8788$new_n1752 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1551 $abc$8788$new_n1542 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[6] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1754 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1742 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1755 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1757 execute_to_memory_REGFILE_WRITE_DATA[5] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7107 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1760 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[5] $abc$8788$new_n1762 $abc$8788$new_n1757 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1759 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[5] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1548 $abc$8788$new_n1543 $abc$8788$new_n1549 $abc$8788$new_n1759 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1761 $abc$8788$new_n1750 $abc$8788$new_n1760 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[4] _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n1761 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1762 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1764 execute_to_memory_REGFILE_WRITE_DATA[4] $abc$8788$new_n1323 $abc$8788$new_n1767 $abc$8788$auto$rtlil.cc:2693:MuxGate$7109 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1766 dBus_cmd_payload_address[4] $abc$8788$new_n1595 $abc$8788$new_n1764 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1543 $abc$8788$new_n1549 _zz_execute_SrcPlugin_addSub_2[4] dBus_cmd_payload_address[4] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1766 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1768 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1767 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[3] _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1768 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1770 execute_to_memory_REGFILE_WRITE_DATA[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7111 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1775 $abc$8788$new_n1771 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1493 $abc$8788$new_n1770 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[3] $abc$8788$new_n1774 $abc$8788$new_n1771 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1544 $abc$8788$new_n1773 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[3] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1773 +001 1 +100 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1774 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1776 $abc$8788$new_n1761 $abc$8788$new_n1775 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[2] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1776 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[2] $abc$8788$new_n1783 $abc$8788$new_n1781 $abc$8788$new_n1778 $abc$8788$auto$rtlil.cc:2693:MuxGate$7113 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 $abc$8788$new_n1323 dBus_cmd_payload_address[2] $abc$8788$new_n1780 $abc$8788$new_n1778 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1546 $abc$8788$new_n1545 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[2] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1780 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1782 $abc$8788$new_n1768 $abc$8788$new_n1781 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[1] _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n1782 +000 1 +010 1 +100 1 +101 1 +.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$8788$new_n1322 $abc$8788$new_n1323 $abc$8788$new_n1783 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1785 execute_to_memory_REGFILE_WRITE_DATA[1] $abc$8788$new_n1323 $abc$8788$new_n1790 $abc$8788$auto$rtlil.cc:2693:MuxGate$7115 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[1] $abc$8788$new_n1789 $abc$8788$new_n1785 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1322 execute_CsrPlugin_csr_834 $abc$8788$new_n1786 +000 1 +001 1 +010 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1788 _zz_execute_SrcPlugin_addSub_2[1] dBus_cmd_payload_address[1] +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] $abc$8788$new_n1788 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1789 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1776 execute_to_memory_REGFILE_WRITE_DATA[0] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1790 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$8788$new_n1803 $abc$8788$new_n1322 $abc$8788$new_n1587 $abc$8788$new_n1792 execute_CsrPlugin_csr_834 $abc$8788$auto$rtlil.cc:2693:MuxGate$7117 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1589 $abc$8788$new_n1799 $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n1792 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1796 $abc$8788$new_n1798 $abc$8788$new_n1794 _zz_execute_SrcPlugin_addSub_2[31] dBus_cmd_payload_address[31] +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1531 $abc$8788$new_n1584 _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1795 $abc$8788$new_n1794 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n1795 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$8788$new_n1797 $abc$8788$new_n1796 +01 1 +10 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] $abc$8788$new_n1797 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1798 +101 1 +110 1 +.names $abc$8788$new_n1595 $abc$8788$new_n1800 dBus_cmd_payload_address[0] $abc$8788$new_n1799 +000 1 +010 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1800 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +1010 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[0] +010 1 +100 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC_LESS_UNSIGNED decode_to_execute_SRC2[31] $abc$8788$new_n1802 +000 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1323 execute_to_memory_REGFILE_WRITE_DATA[0] $abc$8788$new_n1782 $abc$8788$new_n1592 $abc$8788$new_n1803 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_MEMORY_ADDRESS_LOW[0] dBus_cmd_payload_address[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7119 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1806 decode_to_execute_SRC2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7121 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] _zz_decode_SRC2 $abc$8788$new_n1806 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n1807 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1809 decode_to_execute_SRC2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7123 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] _zz_decode_SRC2 $abc$8788$new_n1809 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1811 decode_to_execute_SRC2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7125 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] _zz_decode_SRC2 $abc$8788$new_n1811 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1813 decode_to_execute_SRC2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7127 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] _zz_decode_SRC2 $abc$8788$new_n1813 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1815 decode_to_execute_SRC2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7129 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] _zz_decode_SRC2 $abc$8788$new_n1815 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1817 decode_to_execute_SRC2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7131 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] _zz_decode_SRC2 $abc$8788$new_n1817 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1819 decode_to_execute_SRC2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7133 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] _zz_decode_SRC2 $abc$8788$new_n1819 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1821 decode_to_execute_SRC2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7135 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] _zz_decode_SRC2 $abc$8788$new_n1821 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1823 decode_to_execute_SRC2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7137 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] _zz_decode_SRC2 $abc$8788$new_n1823 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1825 decode_to_execute_SRC2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7139 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] _zz_decode_SRC2 $abc$8788$new_n1825 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1827 decode_to_execute_SRC2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7141 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] _zz_decode_SRC2 $abc$8788$new_n1827 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1829 decode_to_execute_SRC2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7143 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] _zz_decode_SRC2 $abc$8788$new_n1829 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1831 decode_to_execute_SRC2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7145 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] _zz_decode_SRC2 $abc$8788$new_n1831 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1833 decode_to_execute_SRC2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7147 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] _zz_decode_SRC2 $abc$8788$new_n1833 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1835 decode_to_execute_SRC2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7149 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] _zz_decode_SRC2 $abc$8788$new_n1835 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1837 decode_to_execute_SRC2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7151 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] _zz_decode_SRC2 $abc$8788$new_n1837 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1839 decode_to_execute_SRC2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7153 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] _zz_decode_SRC2 $abc$8788$new_n1839 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1841 decode_to_execute_SRC2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7155 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] _zz_decode_SRC2 $abc$8788$new_n1841 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1843 decode_to_execute_SRC2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7157 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] _zz_decode_SRC2 $abc$8788$new_n1843 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1845 decode_to_execute_SRC2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7159 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] _zz_decode_SRC2 $abc$8788$new_n1845 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1847 decode_to_execute_SRC2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7161 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n1847 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1849 decode_to_execute_SRC2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7163 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$8788$new_n1849 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1851 decode_to_execute_SRC2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7165 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$8788$new_n1851 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1853 decode_to_execute_SRC2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7167 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n1853 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1855 decode_to_execute_SRC2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7169 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n1855 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1857 decode_to_execute_SRC2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7171 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$8788$new_n1857 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1859 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7173 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1860 _zz_RegFilePlugin_regFile_port1[4] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[4] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1859 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1860 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1861 +1000 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 $abc$8788$new_n1862 +00 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1864 decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7175 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1865 _zz_RegFilePlugin_regFile_port1[3] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[3] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1864 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1865 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1867 decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7177 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1868 _zz_RegFilePlugin_regFile_port1[2] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[2] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1867 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n1868 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1870 decode_to_execute_SRC2[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7179 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[1] $abc$8788$new_n1870 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1872 decode_to_execute_SRC2[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7181 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[0] $abc$8788$new_n1872 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[30] decode_to_execute_RS2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7183 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[29] decode_to_execute_RS2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7185 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[28] decode_to_execute_RS2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7187 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[27] decode_to_execute_RS2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7189 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[26] decode_to_execute_RS2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7191 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[25] decode_to_execute_RS2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7193 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[24] decode_to_execute_RS2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7195 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[23] decode_to_execute_RS2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7197 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[22] decode_to_execute_RS2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7199 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[21] decode_to_execute_RS2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7201 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[20] decode_to_execute_RS2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7203 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[19] decode_to_execute_RS2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7205 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[18] decode_to_execute_RS2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7207 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[17] decode_to_execute_RS2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7209 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[16] decode_to_execute_RS2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7211 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[15] decode_to_execute_RS2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7213 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[14] decode_to_execute_RS2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7215 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[13] decode_to_execute_RS2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7217 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[12] decode_to_execute_RS2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7219 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[11] decode_to_execute_RS2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7221 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[10] decode_to_execute_RS2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7223 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[9] decode_to_execute_RS2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7225 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[8] decode_to_execute_RS2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7227 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[7] dBus_cmd_payload_data[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7229 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[6] dBus_cmd_payload_data[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7231 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[5] dBus_cmd_payload_data[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7233 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[4] dBus_cmd_payload_data[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7235 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[3] dBus_cmd_payload_data[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7237 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[2] dBus_cmd_payload_data[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7239 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[1] dBus_cmd_payload_data[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7241 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[0] dBus_cmd_payload_data[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7243 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[30] decode_to_execute_RS1[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7245 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[29] decode_to_execute_RS1[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7247 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[28] decode_to_execute_RS1[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7249 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[27] decode_to_execute_RS1[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7251 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[26] decode_to_execute_RS1[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7253 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[25] decode_to_execute_RS1[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7255 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[24] decode_to_execute_RS1[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7257 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[23] decode_to_execute_RS1[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7259 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[22] decode_to_execute_RS1[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7261 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[21] decode_to_execute_RS1[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7263 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[20] decode_to_execute_RS1[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7265 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[19] decode_to_execute_RS1[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7267 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[18] decode_to_execute_RS1[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7269 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[17] decode_to_execute_RS1[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7271 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[16] decode_to_execute_RS1[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7273 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[15] decode_to_execute_RS1[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7275 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[14] decode_to_execute_RS1[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7277 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[13] decode_to_execute_RS1[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7279 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[12] decode_to_execute_RS1[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7281 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[11] decode_to_execute_RS1[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7283 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[10] decode_to_execute_RS1[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7285 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[9] decode_to_execute_RS1[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7287 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[8] decode_to_execute_RS1[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7289 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[7] decode_to_execute_RS1[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7291 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[6] decode_to_execute_RS1[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7293 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[5] decode_to_execute_RS1[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7295 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[4] decode_to_execute_RS1[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7297 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[3] decode_to_execute_RS1[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7299 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[2] decode_to_execute_RS1[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7301 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[1] decode_to_execute_RS1[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7303 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[0] decode_to_execute_RS1[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7305 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_BRANCH_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7307 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1937 _zz_execute_SHIFT_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7309 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n1937 +11000 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_BITWISE_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7311 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7313 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7317 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7319 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7347 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7349 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[12] dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7351 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7353 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7355 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7357 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7359 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7361 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7377 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7379 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7381 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7383 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7385 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7387 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] _zz__zz_execute_BranchPlugin_branch_src2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7389 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7391 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7393 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7395 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7397 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7399 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7401 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7403 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7405 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7407 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7409 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7411 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7413 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7415 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7417 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7419 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7421 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7423 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7505 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7507 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7509 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7511 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7513 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7515 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7517 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7519 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7521 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7523 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7525 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7527 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7529 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7531 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7533 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7535 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7537 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7539 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7541 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7543 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7545 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7547 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7549 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7551 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7553 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7555 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_injector_decodeInput_payload_pc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7557 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_injector_decodeInput_payload_pc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7559 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_injector_decodeInput_payload_pc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7561 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2004 BranchPlugin_jumpInterface_payload[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7563 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2059 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2005 $abc$8788$new_n2004 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2058 $abc$8788$new_n2057 $abc$8788$new_n2056 $abc$8788$new_n2006 $abc$8788$new_n2005 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$8788$new_n2020 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2007 decode_to_execute_PC[25] decode_to_execute_RS1[25] $abc$8788$new_n2006 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2055 $abc$8788$new_n2054 $abc$8788$new_n2008 $abc$8788$new_n2007 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2053 $abc$8788$new_n2052 $abc$8788$new_n2051 $abc$8788$new_n2009 $abc$8788$new_n2008 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$8788$new_n2050 $abc$8788$new_n2048 $abc$8788$new_n2049 $abc$8788$new_n2047 $abc$8788$new_n2010 $abc$8788$new_n2009 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2046 $abc$8788$new_n2044 $abc$8788$new_n2045 $abc$8788$new_n2043 $abc$8788$new_n2011 $abc$8788$new_n2010 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 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$abc$8788$new_n2015 $abc$8788$new_n2014 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n2028 _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$new_n2027 $abc$8788$new_n2016 $abc$8788$new_n2015 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n2026 $abc$8788$new_n2025 _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$new_n2024 $abc$8788$new_n2017 $abc$8788$new_n2016 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2023 $abc$8788$new_n2018 _zz__zz_execute_BranchPlugin_branch_src2[2] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2017 +00100 1 +00110 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_zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$new_n2015 $abc$8788$new_n2093 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$new_n2030 $abc$8788$new_n2015 BranchPlugin_jumpInterface_payload[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7607 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$new_n2027 $abc$8788$new_n2096 BranchPlugin_jumpInterface_payload[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7609 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2028 _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$new_n2016 $abc$8788$new_n2096 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$new_n2028 $abc$8788$new_n2016 BranchPlugin_jumpInterface_payload[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7611 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$new_n2024 $abc$8788$new_n2099 BranchPlugin_jumpInterface_payload[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7613 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2026 $abc$8788$new_n2025 $abc$8788$new_n2017 $abc$8788$new_n2099 +011 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2026 $abc$8788$new_n2025 $abc$8788$new_n2017 BranchPlugin_jumpInterface_payload[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7615 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2102 BranchPlugin_jumpInterface_payload[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7617 +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2023 $abc$8788$new_n2018 _zz__zz_execute_BranchPlugin_branch_src2[2] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2102 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2104 BranchPlugin_jumpInterface_payload[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7619 +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2021 $abc$8788$new_n2019 _zz__zz_execute_BranchPlugin_branch_src2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$new_n2104 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] decode_INSTRUCTION_ANTICIPATED[30] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] decode_INSTRUCTION_ANTICIPATED[29] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] decode_INSTRUCTION_ANTICIPATED[28] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] decode_INSTRUCTION_ANTICIPATED[27] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] decode_INSTRUCTION_ANTICIPATED[26] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 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IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] decode_INSTRUCTION_ANTICIPATED[13] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] decode_INSTRUCTION_ANTICIPATED[12] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] decode_INSTRUCTION_ANTICIPATED[11] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] decode_INSTRUCTION_ANTICIPATED[10] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] decode_INSTRUCTION_ANTICIPATED[9] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 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IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] decode_INSTRUCTION_ANTICIPATED[6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] decode_INSTRUCTION_ANTICIPATED[5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] decode_INSTRUCTION_ANTICIPATED[4] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] decode_INSTRUCTION_ANTICIPATED[3] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] decode_INSTRUCTION_ANTICIPATED[2] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2126 _zz_execute_SrcPlugin_addSub_2[30] _zz_RegFilePlugin_regFile_port0[30] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1296 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2125 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2126 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2128 _zz_execute_SrcPlugin_addSub_2[29] _zz_RegFilePlugin_regFile_port0[29] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2128 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2130 _zz_execute_SrcPlugin_addSub_2[28] _zz_RegFilePlugin_regFile_port0[28] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7669 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2130 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2132 _zz_execute_SrcPlugin_addSub_2[27] _zz_RegFilePlugin_regFile_port0[27] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7671 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2132 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2134 _zz_execute_SrcPlugin_addSub_2[26] _zz_RegFilePlugin_regFile_port0[26] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7673 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2134 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2136 _zz_execute_SrcPlugin_addSub_2[25] _zz_RegFilePlugin_regFile_port0[25] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7675 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2136 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2138 _zz_execute_SrcPlugin_addSub_2[24] _zz_RegFilePlugin_regFile_port0[24] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7677 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2138 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2140 _zz_execute_SrcPlugin_addSub_2[23] _zz_RegFilePlugin_regFile_port0[23] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2140 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2142 _zz_execute_SrcPlugin_addSub_2[22] _zz_RegFilePlugin_regFile_port0[22] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7681 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2142 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2144 _zz_execute_SrcPlugin_addSub_2[21] _zz_RegFilePlugin_regFile_port0[21] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7683 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2144 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2146 _zz_execute_SrcPlugin_addSub_2[20] _zz_RegFilePlugin_regFile_port0[20] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7685 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2146 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2148 _zz_execute_SrcPlugin_addSub_2[19] _zz_RegFilePlugin_regFile_port0[19] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7687 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2148 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2150 _zz_execute_SrcPlugin_addSub_2[18] _zz_RegFilePlugin_regFile_port0[18] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7689 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2150 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2152 _zz_execute_SrcPlugin_addSub_2[17] _zz_RegFilePlugin_regFile_port0[17] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7691 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2152 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2154 _zz_execute_SrcPlugin_addSub_2[16] _zz_RegFilePlugin_regFile_port0[16] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7693 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2154 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2156 _zz_execute_SrcPlugin_addSub_2[15] _zz_RegFilePlugin_regFile_port0[15] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7695 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2156 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2158 _zz_execute_SrcPlugin_addSub_2[14] _zz_RegFilePlugin_regFile_port0[14] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7697 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2158 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2160 _zz_execute_SrcPlugin_addSub_2[13] _zz_RegFilePlugin_regFile_port0[13] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7699 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2160 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2162 _zz_execute_SrcPlugin_addSub_2[12] _zz_RegFilePlugin_regFile_port0[12] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7701 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2162 +11110 1 +.names $abc$8788$new_n2164 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7703 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2165 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2164 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz_RegFilePlugin_regFile_port0[2] $abc$8788$new_n2165 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2167 _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7707 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz_RegFilePlugin_regFile_port0[3] $abc$8788$new_n2167 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2168 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8788$new_n2170 _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7711 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz_RegFilePlugin_regFile_port0[1] $abc$8788$new_n2170 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2172 _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7715 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz_RegFilePlugin_regFile_port0[0] $abc$8788$new_n2172 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[10] _zz_RegFilePlugin_regFile_port0[10] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7719 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[9] _zz_RegFilePlugin_regFile_port0[9] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7723 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[8] _zz_RegFilePlugin_regFile_port0[8] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7727 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[7] _zz_RegFilePlugin_regFile_port0[7] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7731 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[6] _zz_RegFilePlugin_regFile_port0[6] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7735 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[5] _zz_RegFilePlugin_regFile_port0[5] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7739 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[30] decode_to_execute_PC[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7803 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[29] decode_to_execute_PC[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7805 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[28] decode_to_execute_PC[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7807 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[27] decode_to_execute_PC[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7809 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[26] decode_to_execute_PC[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7811 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[25] decode_to_execute_PC[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7813 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[24] decode_to_execute_PC[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7815 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[23] decode_to_execute_PC[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7817 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[22] decode_to_execute_PC[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7819 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[21] decode_to_execute_PC[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7821 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[20] decode_to_execute_PC[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7823 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[19] decode_to_execute_PC[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7825 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[18] decode_to_execute_PC[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7827 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[17] decode_to_execute_PC[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7829 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[16] decode_to_execute_PC[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7831 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[15] decode_to_execute_PC[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7833 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[14] decode_to_execute_PC[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7835 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[13] decode_to_execute_PC[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7837 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[12] decode_to_execute_PC[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7839 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[11] decode_to_execute_PC[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7841 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[10] decode_to_execute_PC[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7843 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[9] decode_to_execute_PC[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7845 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[8] decode_to_execute_PC[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7847 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[7] decode_to_execute_PC[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7849 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[6] decode_to_execute_PC[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7851 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[5] decode_to_execute_PC[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7853 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[4] decode_to_execute_PC[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7855 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[3] decode_to_execute_PC[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7857 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[2] decode_to_execute_PC[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7859 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_834 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2209 $abc$8788$auto$rtlil.cc:2693:MuxGate$7887 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2210 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2209 +11000 1 +.names $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2210 +1000 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n2211 +1100 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_772 $abc$8788$new_n2214 $abc$8788$new_n2213 $abc$8788$auto$rtlil.cc:2693:MuxGate$7889 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2213 +11000 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2214 +0000 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2216 execute_CsrPlugin_csr_836 $abc$8788$auto$rtlil.cc:2693:MuxGate$7891 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2213 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2216 +11000 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_768 $abc$8788$new_n2210 $abc$8788$new_n2214 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7893 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$8788$new_n2245 _zz_execute_BRANCH_CTRL[0] $abc$8788$new_n2246 $abc$8788$new_n2219 $abc$8788$new_n2242 $abc$8788$auto$rtlil.cc:2693:MuxGate$7897 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2220 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n2219 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[13] switch_Misc_l241_1 $abc$8788$new_n2221 $abc$8788$new_n2220 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2236 $abc$8788$new_n2222 _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] $abc$8788$new_n2221 +1100 1 +1111 1 +.names $abc$8788$new_n2233 $abc$8788$new_n2223 $abc$8788$new_n2235 _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] $abc$8788$new_n2222 +11100 1 +11111 1 +.names $abc$8788$new_n2229 $abc$8788$new_n2224 $abc$8788$new_n2231 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n2223 +11100 1 +11111 1 +.names $abc$8788$new_n2228 $abc$8788$new_n2225 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n2227 $abc$8788$new_n2224 +11000 1 +11110 1 +.names $abc$8788$new_n2226 $abc$8788$new_n1797 _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] $abc$8788$new_n2225 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n2226 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] $abc$8788$new_n2227 +01 1 +10 1 +.names _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] $abc$8788$new_n2228 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$8788$new_n2230 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] $abc$8788$new_n2229 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n2230 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n2232 $abc$8788$new_n2231 +00000 1 +00110 1 +11000 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n2232 +01 1 +10 1 +.names $abc$8788$new_n2234 _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] $abc$8788$new_n2233 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n2234 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] $abc$8788$new_n2235 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$8788$new_n2239 $abc$8788$new_n2237 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] $abc$8788$new_n2236 +1100 1 +1111 1 +.names $abc$8788$new_n2238 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n2237 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n2238 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] $abc$8788$new_n2240 $abc$8788$new_n2239 +00000 1 +00110 1 +11000 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n2240 +01 1 +10 1 +.names $abc$8788$new_n2243 $abc$8788$new_n1802 $abc$8788$new_n2244 dBus_cmd_payload_address[31] $abc$8788$new_n1797 $abc$8788$new_n2242 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[13] dBus_cmd_payload_size[0] $abc$8788$new_n2221 switch_Misc_l241_1 $abc$8788$new_n2243 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n2244 +000 1 +.names $abc$8788$new_n1321 execute_to_memory_BRANCH_DO $abc$8788$new_n2245 +10 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n1321 $abc$8788$new_n2246 +00 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2248 execute_to_memory_REGFILE_WRITE_DATA[31] $abc$8788$new_n1323 $abc$8788$new_n2250 $abc$8788$auto$rtlil.cc:2693:MuxGate$7899 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[31] $abc$8788$new_n2249 $abc$8788$new_n2248 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n2249 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n2251 execute_LightShifterPlugin_isActive $abc$8788$new_n1592 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n2250 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n2251 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 dBus_cmd_payload_address[1] execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7901 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2254 decode_to_execute_SRC2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7903 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] _zz_decode_SRC2 $abc$8788$new_n2254 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2256 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7905 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2257 $abc$8788$new_n1937 _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2256 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2258 $abc$8788$new_n2257 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2258 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[31] decode_to_execute_RS2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7907 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[31] decode_to_execute_RS1[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7909 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2262 _zz_execute_BRANCH_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7911 +001 1 +011 1 +100 1 +101 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2262 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n2458 _zz_execute_SHIFT_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1937 $abc$8788$auto$rtlil.cc:2693:MuxGate$7913 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 _zz_execute_ALU_BITWISE_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7915 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1316 decode_to_execute_SRC_LESS_UNSIGNED IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7917 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2267 $abc$8788$auto$rtlil.cc:2693:MuxGate$7919 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$new_n2267 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1321 _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$8788$auto$rtlil.cc:2693:MuxGate$7921 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_ENV_CTRL $abc$8788$new_n1296 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7923 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1296 decode_to_execute_IS_CSR IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7925 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_wr $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7927 +10 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_47 dBus_cmd_payload_wr $abc$8788$auto$rtlil.cc:2693:MuxGate$7929 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$8788$auto$rtlil.cc:2693:MuxGate$7931 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2275 decode_to_execute_REGFILE_WRITE_VALID $abc$8788$new_n2277 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7935 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8788$new_n2276 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2275 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n2276 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n2277 +0000 1 +.names decode_to_execute_MEMORY_ENABLE $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7937 +01 1 +10 1 +11 1 +.names $abc$8788$new_n2458 decode_to_execute_MEMORY_ENABLE IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7939 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +11000 1 +.names $abc$8788$new_n2257 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_4 $abc$8788$auto$rtlil.cc:2693:MuxGate$7941 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2458 decode_to_execute_CSR_WRITE_OPCODE $abc$8788$new_n2282 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7943 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2282 +10000 1 +.names $abc$8788$new_n2458 _zz_decode_SRC2 _zz_execute_BranchPlugin_branch_src2 $abc$8788$auto$rtlil.cc:2693:MuxGate$7947 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC2 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] decode_INSTRUCTION_ANTICIPATED[31] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2287 $abc$8788$new_n2286 BranchPlugin_jumpInterface_payload[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7965 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2059 $abc$8788$new_n2005 $abc$8788$new_n2286 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2020 decode_to_execute_PC[31] decode_to_execute_RS1[31] $abc$8788$new_n2287 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7971 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[31] decode_to_execute_PC[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7973 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[11] _zz_RegFilePlugin_regFile_port0[11] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7979 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2292 _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7983 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz_RegFilePlugin_regFile_port0[4] $abc$8788$new_n2292 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2294 _zz_execute_SrcPlugin_addSub_2[31] _zz_RegFilePlugin_regFile_port0[31] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7985 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC2 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2294 +1110 1 +.names decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$new_n1321 dBus_cmd_valid +1110 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[8] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[9] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[10] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[11] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[12] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[13] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[14] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[15] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[16] dBus_cmd_payload_data[0] dBus_cmd_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[17] dBus_cmd_payload_data[1] dBus_cmd_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[18] dBus_cmd_payload_data[2] dBus_cmd_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[19] dBus_cmd_payload_data[3] dBus_cmd_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[20] dBus_cmd_payload_data[4] dBus_cmd_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[21] dBus_cmd_payload_data[5] dBus_cmd_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[22] dBus_cmd_payload_data[6] dBus_cmd_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[23] dBus_cmd_payload_data[7] dBus_cmd_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[24] decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[24] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[25] decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[25] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[26] decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[26] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[27] decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[27] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[28] decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[28] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[29] decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[29] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[30] decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[30] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[31] decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[31] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2321 $abc$8788$new_n1492 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2321 +1111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] decode_INSTRUCTION_ANTICIPATED[15] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] decode_INSTRUCTION_ANTICIPATED[16] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] decode_INSTRUCTION_ANTICIPATED[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] decode_INSTRUCTION_ANTICIPATED[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] decode_INSTRUCTION_ANTICIPATED[19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] decode_INSTRUCTION_ANTICIPATED[20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] decode_INSTRUCTION_ANTICIPATED[21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] decode_INSTRUCTION_ANTICIPATED[22] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] decode_INSTRUCTION_ANTICIPATED[23] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] decode_INSTRUCTION_ANTICIPATED[24] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1516 $abc$8788$new_n1272 $0\CsrPlugin_interrupt_valid[0:0] +10 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2334 $abc$8788$new_n2335 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] +000 1 +001 1 +100 1 +110 1 +.names IBusSimplePlugin_pending_value[0] $abc$8788$new_n1454 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2334 +0000 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2335 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01000 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2339 $abc$8788$new_n2338 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1454 IBusSimplePlugin_pending_value[0] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2337 +0001 1 +0010 1 +0011 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2338 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2339 +10001 1 +10010 1 +10011 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2341 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2339 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2341 +010 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[0] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][0] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2345 $abc$8788$new_n1500 $abc$8788$new_n2344 $abc$8788$new_n2343 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_768 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2344 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[12] switch_Misc_l241_1 dBus_cmd_payload_size[0] CsrPlugin_mstatus_MPP[1] execute_CsrPlugin_csr_768 $abc$8788$new_n2345 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][1] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2344 $abc$8788$new_n1496 $abc$8788$new_n2348 $0\CsrPlugin_mstatus_MPIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names $abc$8788$new_n1272 $abc$8788$new_n1274 CsrPlugin_mstatus_MIE CsrPlugin_mstatus_MPIE $abc$8788$new_n2348 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$8788$new_n2344 $abc$8788$new_n1492 $abc$8788$new_n2350 $0\CsrPlugin_mstatus_MIE[0:0] +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1274 CsrPlugin_mstatus_MPIE CsrPlugin_mstatus_MIE $abc$8788$new_n1272 $abc$8788$new_n2350 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names memory_arbitration_isValid $abc$8788$new_n1271 $abc$8788$new_n1321 $0\writeBack_arbitration_isValid[0:0] +110 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2353 memory_to_writeBack_REGFILE_WRITE_DATA[0] lastStageRegFileWrite_payload_data[0] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2354 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[16] $abc$8788$new_n2353 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[8] memory_to_writeBack_MEMORY_READ_DATA[0] $abc$8788$new_n2354 +000 1 +010 1 +100 1 +101 1 +.names memory_to_writeBack_MEMORY_ENABLE lastStageIsFiring $abc$8788$new_n2355 +11 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2357 memory_to_writeBack_REGFILE_WRITE_DATA[1] lastStageRegFileWrite_payload_data[1] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2358 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[17] $abc$8788$new_n2357 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[9] memory_to_writeBack_MEMORY_READ_DATA[1] $abc$8788$new_n2358 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2360 memory_to_writeBack_REGFILE_WRITE_DATA[2] lastStageRegFileWrite_payload_data[2] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2361 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[18] $abc$8788$new_n2360 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[10] memory_to_writeBack_MEMORY_READ_DATA[2] $abc$8788$new_n2361 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2363 memory_to_writeBack_REGFILE_WRITE_DATA[3] lastStageRegFileWrite_payload_data[3] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2364 writeBack_MEMORY_READ_DATA[27] memory_to_writeBack_MEMORY_READ_DATA[19] $abc$8788$new_n2363 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[11] memory_to_writeBack_MEMORY_READ_DATA[3] $abc$8788$new_n2364 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2366 memory_to_writeBack_REGFILE_WRITE_DATA[4] lastStageRegFileWrite_payload_data[4] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2367 writeBack_MEMORY_READ_DATA[28] writeBack_MEMORY_READ_DATA[20] $abc$8788$new_n2366 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[12] memory_to_writeBack_MEMORY_READ_DATA[4] $abc$8788$new_n2367 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2369 memory_to_writeBack_REGFILE_WRITE_DATA[5] lastStageRegFileWrite_payload_data[5] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2370 writeBack_MEMORY_READ_DATA[29] writeBack_MEMORY_READ_DATA[21] $abc$8788$new_n2369 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[13] memory_to_writeBack_MEMORY_READ_DATA[5] $abc$8788$new_n2370 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2372 memory_to_writeBack_REGFILE_WRITE_DATA[6] lastStageRegFileWrite_payload_data[6] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2373 writeBack_MEMORY_READ_DATA[30] writeBack_MEMORY_READ_DATA[22] $abc$8788$new_n2372 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[14] memory_to_writeBack_MEMORY_READ_DATA[6] $abc$8788$new_n2373 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2375 memory_to_writeBack_REGFILE_WRITE_DATA[7] lastStageRegFileWrite_payload_data[7] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2376 writeBack_MEMORY_READ_DATA[31] writeBack_MEMORY_READ_DATA[23] $abc$8788$new_n2375 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[15] memory_to_writeBack_MEMORY_READ_DATA[7] $abc$8788$new_n2376 +000 1 +010 1 +100 1 +101 1 +.names _zz_5 $abc$8788$new_n2379 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[8] lastStageRegFileWrite_payload_data[8] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2355 _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2375 _zz_lastStageRegFileWrite_payload_address[14] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2378 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[8] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2379 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2380 +10 1 +.names _zz_5 $abc$8788$new_n2382 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[9] lastStageRegFileWrite_payload_data[9] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[9] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2382 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2384 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[10] lastStageRegFileWrite_payload_data[10] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[10] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2384 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2386 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[11] lastStageRegFileWrite_payload_data[11] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[27] memory_to_writeBack_MEMORY_READ_DATA[11] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2386 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2388 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[12] lastStageRegFileWrite_payload_data[12] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[28] memory_to_writeBack_MEMORY_READ_DATA[12] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2388 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2390 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[13] lastStageRegFileWrite_payload_data[13] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[29] memory_to_writeBack_MEMORY_READ_DATA[13] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2390 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2392 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[14] lastStageRegFileWrite_payload_data[14] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[30] memory_to_writeBack_MEMORY_READ_DATA[14] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2392 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2394 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[15] lastStageRegFileWrite_payload_data[15] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2394 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[31] memory_to_writeBack_MEMORY_READ_DATA[15] $abc$8788$new_n2395 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2397 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[16] lastStageRegFileWrite_payload_data[16] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[16] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2397 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2378 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[14] $abc$8788$new_n2398 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2400 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[17] lastStageRegFileWrite_payload_data[17] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[17] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2400 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2402 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[18] lastStageRegFileWrite_payload_data[18] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[18] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2402 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2404 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[19] lastStageRegFileWrite_payload_data[19] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[19] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2404 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2406 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[20] lastStageRegFileWrite_payload_data[20] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[20] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2406 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2408 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[21] lastStageRegFileWrite_payload_data[21] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[21] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2408 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2410 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[22] lastStageRegFileWrite_payload_data[22] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[22] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2410 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2412 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[23] lastStageRegFileWrite_payload_data[23] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[23] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2412 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2414 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[24] lastStageRegFileWrite_payload_data[24] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[24] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2414 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2416 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[25] lastStageRegFileWrite_payload_data[25] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[25] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2416 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2418 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[26] lastStageRegFileWrite_payload_data[26] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[26] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2418 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2420 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[27] lastStageRegFileWrite_payload_data[27] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[27] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2420 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2422 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[28] lastStageRegFileWrite_payload_data[28] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[28] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2422 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2424 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[29] lastStageRegFileWrite_payload_data[29] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[29] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2424 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2426 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[30] lastStageRegFileWrite_payload_data[30] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[30] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2426 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2428 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[31] lastStageRegFileWrite_payload_data[31] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[31] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2428 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_5 lastStageRegFileWrite_payload_address[0] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_5 lastStageRegFileWrite_payload_address[1] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_5 lastStageRegFileWrite_payload_address[2] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_5 lastStageRegFileWrite_payload_address[3] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_5 lastStageRegFileWrite_payload_address[4] +10 1 +.names _zz_5 HazardSimplePlugin_writeBackWrites_valid _zz_1 +01 1 +10 1 +11 1 +.names IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[1] +001 1 +010 1 +100 1 +111 1 +.names $abc$8788$new_n1505 $abc$8788$new_n2334 $abc$8788$new_n2436 +10 1 +.names IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[2] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$8788$new_n1505 $abc$8788$new_n2334 IBusSimplePlugin_pending_next[0] +00 1 +11 1 +.names $abc$8788$new_n1283 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] execute_to_memory_INSTRUCTION[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] execute_to_memory_INSTRUCTION[9] $abc$8788$new_n2439 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2439 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] execute_to_memory_INSTRUCTION[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n2440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2442 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2442 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2443 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n1304 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] execute_to_memory_INSTRUCTION[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] execute_to_memory_INSTRUCTION[8] $abc$8788$new_n2445 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2445 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] execute_to_memory_INSTRUCTION[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] execute_to_memory_INSTRUCTION[10] $abc$8788$new_n2446 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2448 +10000 1 +10011 1 +11100 1 +11111 1 +.names decode_to_execute_REGFILE_WRITE_VALID IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2_4[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n2449 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2448 $abc$8788$new_n2449 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2450 +1100 1 +1111 1 +.names HazardSimplePlugin_writeBackBuffer_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackBuffer_payload_address[0] HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2451 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2451 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2452 +10000 1 +10011 1 +11100 1 +11111 1 +.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2454 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2454 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2455 +10000 1 +10011 1 +11100 1 +11111 1 +.names decode_to_execute_IS_CSR memory_arbitration_isValid lastStageIsFiring decode_to_execute_MEMORY_ENABLE dBus_cmd_ready $abc$8788$new_n2457 +00010 1 +00110 1 +01010 1 +01110 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_arbitration_isValid $abc$8788$new_n2457 $abc$8788$new_n1323 $abc$8788$new_n1325 $abc$8788$new_n2458 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2452 HazardSimplePlugin_writeBackBuffer_payload_address[4] $abc$8788$new_n2455 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2459 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$8788$new_n1278 $abc$8788$new_n1315 $abc$8788$new_n2446 $abc$8788$new_n2459 $abc$8788$new_n2450 $abc$8788$new_n2460 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1328 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2460 $abc$8788$new_n2461 +1100 1 +1101 1 +1110 1 +.names $abc$8788$new_n1285 decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$new_n2462 +11100 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n2443 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2462 _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2463 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2463 $abc$8788$new_n1288 $abc$8788$new_n2440 $abc$8788$new_n2464 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7861 Q=CsrPlugin_mcause_exceptionCode[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7969 Q=CsrPlugin_mcause_exceptionCode[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7957 Q=CsrPlugin_interrupt_code[3] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[15] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[16] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[17] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[18] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[19] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[20] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[21] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[22] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[23] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[24] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7859 Q=decode_to_execute_PC[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7857 Q=decode_to_execute_PC[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7855 Q=decode_to_execute_PC[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7853 Q=decode_to_execute_PC[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7851 Q=decode_to_execute_PC[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7849 Q=decode_to_execute_PC[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7847 Q=decode_to_execute_PC[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7845 Q=decode_to_execute_PC[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7843 Q=decode_to_execute_PC[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7841 Q=decode_to_execute_PC[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7839 Q=decode_to_execute_PC[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7837 Q=decode_to_execute_PC[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7835 Q=decode_to_execute_PC[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7833 Q=decode_to_execute_PC[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7831 Q=decode_to_execute_PC[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7829 Q=decode_to_execute_PC[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7827 Q=decode_to_execute_PC[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7825 Q=decode_to_execute_PC[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7823 Q=decode_to_execute_PC[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7821 Q=decode_to_execute_PC[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7819 Q=decode_to_execute_PC[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7817 Q=decode_to_execute_PC[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7815 Q=decode_to_execute_PC[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7813 Q=decode_to_execute_PC[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7811 Q=decode_to_execute_PC[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7809 Q=decode_to_execute_PC[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7807 Q=decode_to_execute_PC[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7805 Q=decode_to_execute_PC[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7803 Q=decode_to_execute_PC[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7973 Q=decode_to_execute_PC[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7797 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7795 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7793 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7791 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7789 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7787 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7785 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7783 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7781 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7779 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7777 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7775 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7773 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7771 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7769 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7767 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7765 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7763 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7761 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7759 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7757 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7755 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7753 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7751 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7749 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7747 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7745 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7743 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7741 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7963 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7953 Q=CsrPlugin_interrupt_code[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7739 Q=_zz_execute_SrcPlugin_addSub_2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7735 Q=_zz_execute_SrcPlugin_addSub_2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7731 Q=_zz_execute_SrcPlugin_addSub_2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7727 Q=_zz_execute_SrcPlugin_addSub_2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7723 Q=_zz_execute_SrcPlugin_addSub_2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7719 Q=_zz_execute_SrcPlugin_addSub_2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7979 Q=_zz_execute_SrcPlugin_addSub_2[11] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7863 Q=execute_LightShifterPlugin_isActive R=reset +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7715 Q=_zz_execute_SrcPlugin_addSub_2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7711 Q=_zz_execute_SrcPlugin_addSub_2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7707 Q=_zz_execute_SrcPlugin_addSub_2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7983 Q=_zz_execute_SrcPlugin_addSub_2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7703 Q=_zz_execute_SrcPlugin_addSub_2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7701 Q=_zz_execute_SrcPlugin_addSub_2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7699 Q=_zz_execute_SrcPlugin_addSub_2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7697 Q=_zz_execute_SrcPlugin_addSub_2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7695 Q=_zz_execute_SrcPlugin_addSub_2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7693 Q=_zz_execute_SrcPlugin_addSub_2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7691 Q=_zz_execute_SrcPlugin_addSub_2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7689 Q=_zz_execute_SrcPlugin_addSub_2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7687 Q=_zz_execute_SrcPlugin_addSub_2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7685 Q=_zz_execute_SrcPlugin_addSub_2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7683 Q=_zz_execute_SrcPlugin_addSub_2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7681 Q=_zz_execute_SrcPlugin_addSub_2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7679 Q=_zz_execute_SrcPlugin_addSub_2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7677 Q=_zz_execute_SrcPlugin_addSub_2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7675 Q=_zz_execute_SrcPlugin_addSub_2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7673 Q=_zz_execute_SrcPlugin_addSub_2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7671 Q=_zz_execute_SrcPlugin_addSub_2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7669 Q=_zz_execute_SrcPlugin_addSub_2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7667 Q=_zz_execute_SrcPlugin_addSub_2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7665 Q=_zz_execute_SrcPlugin_addSub_2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7985 Q=_zz_execute_SrcPlugin_addSub_2[31] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7961 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=reset +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[2] Q=_zz_decode_SRC_LESS_UNSIGNED_4 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[3] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[4] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[5] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_47 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[6] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[7] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[8] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[9] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[10] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[11] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[12] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_13 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[13] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[14] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[25] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[26] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[27] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[28] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[29] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[30] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[31] Q=_zz_decode_SRC2 +.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP +.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP +.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7619 Q=BranchPlugin_jumpInterface_payload[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7617 Q=BranchPlugin_jumpInterface_payload[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7615 Q=BranchPlugin_jumpInterface_payload[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7613 Q=BranchPlugin_jumpInterface_payload[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7611 Q=BranchPlugin_jumpInterface_payload[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7609 Q=BranchPlugin_jumpInterface_payload[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7607 Q=BranchPlugin_jumpInterface_payload[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7605 Q=BranchPlugin_jumpInterface_payload[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7603 Q=BranchPlugin_jumpInterface_payload[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7601 Q=BranchPlugin_jumpInterface_payload[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7599 Q=BranchPlugin_jumpInterface_payload[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7597 Q=BranchPlugin_jumpInterface_payload[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7595 Q=BranchPlugin_jumpInterface_payload[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7593 Q=BranchPlugin_jumpInterface_payload[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7591 Q=BranchPlugin_jumpInterface_payload[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7589 Q=BranchPlugin_jumpInterface_payload[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7587 Q=BranchPlugin_jumpInterface_payload[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7585 Q=BranchPlugin_jumpInterface_payload[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7583 Q=BranchPlugin_jumpInterface_payload[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7581 Q=BranchPlugin_jumpInterface_payload[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7579 Q=BranchPlugin_jumpInterface_payload[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7577 Q=BranchPlugin_jumpInterface_payload[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7575 Q=BranchPlugin_jumpInterface_payload[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7573 Q=BranchPlugin_jumpInterface_payload[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7571 Q=BranchPlugin_jumpInterface_payload[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7569 Q=BranchPlugin_jumpInterface_payload[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7567 Q=BranchPlugin_jumpInterface_payload[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7565 Q=BranchPlugin_jumpInterface_payload[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7563 Q=BranchPlugin_jumpInterface_payload[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7965 Q=BranchPlugin_jumpInterface_payload[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7561 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7559 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7557 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7555 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7553 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7551 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7549 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7547 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7545 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7543 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7541 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7539 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7537 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7535 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7533 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7531 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7529 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7527 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7525 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7523 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7521 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7519 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7517 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7515 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7513 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7511 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7509 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7507 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7505 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7971 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[31] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7503 Q=execute_LightShifterPlugin_amplitudeReg[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7501 Q=execute_LightShifterPlugin_amplitudeReg[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7499 Q=execute_LightShifterPlugin_amplitudeReg[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7497 Q=execute_LightShifterPlugin_amplitudeReg[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7949 Q=execute_LightShifterPlugin_amplitudeReg[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7495 Q=CsrPlugin_mepc[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7493 Q=CsrPlugin_mepc[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7491 Q=CsrPlugin_mepc[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7489 Q=CsrPlugin_mepc[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7487 Q=CsrPlugin_mepc[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7485 Q=CsrPlugin_mepc[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7483 Q=CsrPlugin_mepc[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7481 Q=CsrPlugin_mepc[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7479 Q=CsrPlugin_mepc[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7477 Q=CsrPlugin_mepc[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7475 Q=CsrPlugin_mepc[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7473 Q=CsrPlugin_mepc[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7471 Q=CsrPlugin_mepc[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7469 Q=CsrPlugin_mepc[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7467 Q=CsrPlugin_mepc[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7465 Q=CsrPlugin_mepc[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7463 Q=CsrPlugin_mepc[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7461 Q=CsrPlugin_mepc[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7459 Q=CsrPlugin_mepc[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7457 Q=CsrPlugin_mepc[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7455 Q=CsrPlugin_mepc[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7453 Q=CsrPlugin_mepc[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7451 Q=CsrPlugin_mepc[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7449 Q=CsrPlugin_mepc[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7447 Q=CsrPlugin_mepc[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7445 Q=CsrPlugin_mepc[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7443 Q=CsrPlugin_mepc[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7441 Q=CsrPlugin_mepc[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7439 Q=CsrPlugin_mepc[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7975 Q=CsrPlugin_mepc[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7423 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7421 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7419 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7417 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7415 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7413 Q=dBus_cmd_payload_size[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7411 Q=switch_Misc_l241_1 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7409 Q=_zz__zz_execute_BranchPlugin_branch_src2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7407 Q=_zz__zz_execute_BranchPlugin_branch_src2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7405 Q=_zz__zz_execute_BranchPlugin_branch_src2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7403 Q=_zz__zz_execute_BranchPlugin_branch_src2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7401 Q=_zz__zz_execute_BranchPlugin_branch_src2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7399 Q=_zz__zz_execute_BranchPlugin_branch_src2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7397 Q=_zz__zz_execute_BranchPlugin_branch_src2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7395 Q=_zz__zz_execute_BranchPlugin_branch_src2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7393 Q=_zz__zz_execute_BranchPlugin_branch_src2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7391 Q=_zz__zz_execute_BranchPlugin_branch_src2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7389 Q=_zz__zz_execute_BranchPlugin_branch_src2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7387 Q=_zz__zz_execute_BranchPlugin_branch_src2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7385 Q=_zz__zz_execute_BranchPlugin_branch_src2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7383 Q=_zz__zz_execute_BranchPlugin_branch_src2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7381 Q=_zz__zz_execute_BranchPlugin_branch_src2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7379 Q=_zz__zz_execute_BranchPlugin_branch_src2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7377 Q=_zz__zz_execute_BranchPlugin_branch_src2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7947 Q=_zz_execute_BranchPlugin_branch_src2 +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[7] Q=HazardSimplePlugin_writeBackWrites_payload_address[0] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[8] Q=HazardSimplePlugin_writeBackWrites_payload_address[1] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[9] Q=HazardSimplePlugin_writeBackWrites_payload_address[2] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[10] Q=HazardSimplePlugin_writeBackWrites_payload_address[3] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[11] Q=HazardSimplePlugin_writeBackWrites_payload_address[4] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[12] Q=_zz_lastStageRegFileWrite_payload_address[12] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[13] Q=_zz_lastStageRegFileWrite_payload_address[13] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[14] Q=_zz_lastStageRegFileWrite_payload_address[14] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[28] Q=_zz_lastStageRegFileWrite_payload_address[28] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[29] Q=_zz_lastStageRegFileWrite_payload_address[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7361 Q=execute_to_memory_INSTRUCTION[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7359 Q=execute_to_memory_INSTRUCTION[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7357 Q=execute_to_memory_INSTRUCTION[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7355 Q=execute_to_memory_INSTRUCTION[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7353 Q=execute_to_memory_INSTRUCTION[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7351 Q=execute_to_memory_INSTRUCTION[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7349 Q=execute_to_memory_INSTRUCTION[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7347 Q=execute_to_memory_INSTRUCTION[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7319 Q=execute_to_memory_INSTRUCTION[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7317 Q=execute_to_memory_INSTRUCTION[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7943 Q=decode_to_execute_CSR_WRITE_OPCODE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7941 Q=_zz_execute_SrcPlugin_addSub_4 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7939 Q=decode_to_execute_MEMORY_ENABLE +.subckt dff C=clk D=execute_to_memory_MEMORY_ENABLE Q=memory_to_writeBack_MEMORY_ENABLE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7935 Q=decode_to_execute_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7937 Q=execute_to_memory_MEMORY_ENABLE +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_VALID Q=_zz_lastStageRegFileWrite_valid +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7931 Q=execute_to_memory_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7929 Q=dBus_cmd_payload_wr +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7927 Q=execute_to_memory_MEMORY_STORE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7925 Q=decode_to_execute_IS_CSR +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7923 Q=_zz_execute_ENV_CTRL +.subckt dff C=clk D=_zz_memory_ENV_CTRL Q=_zz_writeBack_ENV_CTRL +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7921 Q=_zz_memory_ENV_CTRL +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7313 Q=_zz_execute_ALU_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7919 Q=_zz_execute_ALU_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7917 Q=decode_to_execute_SRC_LESS_UNSIGNED +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7311 Q=_zz_execute_ALU_BITWISE_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7915 Q=_zz_execute_ALU_BITWISE_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7309 Q=_zz_execute_SHIFT_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7913 Q=_zz_execute_SHIFT_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7307 Q=_zz_execute_BRANCH_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7911 Q=_zz_execute_BRANCH_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7305 Q=decode_to_execute_RS1[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7303 Q=decode_to_execute_RS1[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7301 Q=decode_to_execute_RS1[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7299 Q=decode_to_execute_RS1[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7297 Q=decode_to_execute_RS1[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7295 Q=decode_to_execute_RS1[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7293 Q=decode_to_execute_RS1[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7291 Q=decode_to_execute_RS1[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7289 Q=decode_to_execute_RS1[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7287 Q=decode_to_execute_RS1[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7285 Q=decode_to_execute_RS1[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7283 Q=decode_to_execute_RS1[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7281 Q=decode_to_execute_RS1[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7279 Q=decode_to_execute_RS1[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7277 Q=decode_to_execute_RS1[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7275 Q=decode_to_execute_RS1[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7273 Q=decode_to_execute_RS1[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7271 Q=decode_to_execute_RS1[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7269 Q=decode_to_execute_RS1[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7267 Q=decode_to_execute_RS1[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7265 Q=decode_to_execute_RS1[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7263 Q=decode_to_execute_RS1[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7261 Q=decode_to_execute_RS1[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7259 Q=decode_to_execute_RS1[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7257 Q=decode_to_execute_RS1[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7255 Q=decode_to_execute_RS1[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7253 Q=decode_to_execute_RS1[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7251 Q=decode_to_execute_RS1[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7249 Q=decode_to_execute_RS1[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7247 Q=decode_to_execute_RS1[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7245 Q=decode_to_execute_RS1[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7909 Q=decode_to_execute_RS1[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7243 Q=dBus_cmd_payload_data[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7241 Q=dBus_cmd_payload_data[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7239 Q=dBus_cmd_payload_data[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7237 Q=dBus_cmd_payload_data[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7235 Q=dBus_cmd_payload_data[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7233 Q=dBus_cmd_payload_data[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7231 Q=dBus_cmd_payload_data[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7229 Q=dBus_cmd_payload_data[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7227 Q=decode_to_execute_RS2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7225 Q=decode_to_execute_RS2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7223 Q=decode_to_execute_RS2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7221 Q=decode_to_execute_RS2[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7219 Q=decode_to_execute_RS2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7217 Q=decode_to_execute_RS2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7215 Q=decode_to_execute_RS2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7213 Q=decode_to_execute_RS2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7211 Q=decode_to_execute_RS2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7209 Q=decode_to_execute_RS2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7207 Q=decode_to_execute_RS2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7205 Q=decode_to_execute_RS2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7203 Q=decode_to_execute_RS2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7201 Q=decode_to_execute_RS2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7199 Q=decode_to_execute_RS2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7197 Q=decode_to_execute_RS2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7195 Q=decode_to_execute_RS2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7193 Q=decode_to_execute_RS2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7191 Q=decode_to_execute_RS2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7189 Q=decode_to_execute_RS2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7187 Q=decode_to_execute_RS2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7185 Q=decode_to_execute_RS2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7183 Q=decode_to_execute_RS2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7907 Q=decode_to_execute_RS2[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7905 Q=decode_to_execute_SRC2_FORCE_ZERO +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7181 Q=decode_to_execute_SRC2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7179 Q=decode_to_execute_SRC2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7177 Q=decode_to_execute_SRC2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7175 Q=decode_to_execute_SRC2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7173 Q=decode_to_execute_SRC2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7171 Q=decode_to_execute_SRC2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7169 Q=decode_to_execute_SRC2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7167 Q=decode_to_execute_SRC2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7165 Q=decode_to_execute_SRC2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7163 Q=decode_to_execute_SRC2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7161 Q=decode_to_execute_SRC2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7159 Q=decode_to_execute_SRC2[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7157 Q=decode_to_execute_SRC2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7155 Q=decode_to_execute_SRC2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7153 Q=decode_to_execute_SRC2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7151 Q=decode_to_execute_SRC2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7149 Q=decode_to_execute_SRC2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7147 Q=decode_to_execute_SRC2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7145 Q=decode_to_execute_SRC2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7143 Q=decode_to_execute_SRC2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7141 Q=decode_to_execute_SRC2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7139 Q=decode_to_execute_SRC2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7137 Q=decode_to_execute_SRC2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7135 Q=decode_to_execute_SRC2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7133 Q=decode_to_execute_SRC2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7131 Q=decode_to_execute_SRC2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7129 Q=decode_to_execute_SRC2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7127 Q=decode_to_execute_SRC2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7125 Q=decode_to_execute_SRC2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7123 Q=decode_to_execute_SRC2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7121 Q=decode_to_execute_SRC2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7903 Q=decode_to_execute_SRC2[31] +.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[0] +.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7119 Q=execute_to_memory_MEMORY_ADDRESS_LOW[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7901 Q=execute_to_memory_MEMORY_ADDRESS_LOW[1] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[0] Q=memory_to_writeBack_REGFILE_WRITE_DATA[0] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[1] Q=memory_to_writeBack_REGFILE_WRITE_DATA[1] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[2] Q=memory_to_writeBack_REGFILE_WRITE_DATA[2] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[3] Q=memory_to_writeBack_REGFILE_WRITE_DATA[3] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[4] Q=memory_to_writeBack_REGFILE_WRITE_DATA[4] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[5] Q=memory_to_writeBack_REGFILE_WRITE_DATA[5] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[6] Q=memory_to_writeBack_REGFILE_WRITE_DATA[6] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[7] Q=memory_to_writeBack_REGFILE_WRITE_DATA[7] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[8] Q=memory_to_writeBack_REGFILE_WRITE_DATA[8] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[9] Q=memory_to_writeBack_REGFILE_WRITE_DATA[9] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[10] Q=memory_to_writeBack_REGFILE_WRITE_DATA[10] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[11] Q=memory_to_writeBack_REGFILE_WRITE_DATA[11] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[12] Q=memory_to_writeBack_REGFILE_WRITE_DATA[12] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[13] Q=memory_to_writeBack_REGFILE_WRITE_DATA[13] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[14] Q=memory_to_writeBack_REGFILE_WRITE_DATA[14] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[15] Q=memory_to_writeBack_REGFILE_WRITE_DATA[15] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[16] Q=memory_to_writeBack_REGFILE_WRITE_DATA[16] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[17] Q=memory_to_writeBack_REGFILE_WRITE_DATA[17] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[18] Q=memory_to_writeBack_REGFILE_WRITE_DATA[18] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[19] Q=memory_to_writeBack_REGFILE_WRITE_DATA[19] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[20] Q=memory_to_writeBack_REGFILE_WRITE_DATA[20] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[21] Q=memory_to_writeBack_REGFILE_WRITE_DATA[21] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[22] Q=memory_to_writeBack_REGFILE_WRITE_DATA[22] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[23] Q=memory_to_writeBack_REGFILE_WRITE_DATA[23] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[24] Q=memory_to_writeBack_REGFILE_WRITE_DATA[24] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[25] Q=memory_to_writeBack_REGFILE_WRITE_DATA[25] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[26] Q=memory_to_writeBack_REGFILE_WRITE_DATA[26] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[27] Q=memory_to_writeBack_REGFILE_WRITE_DATA[27] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[28] Q=memory_to_writeBack_REGFILE_WRITE_DATA[28] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[29] Q=memory_to_writeBack_REGFILE_WRITE_DATA[29] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[30] Q=memory_to_writeBack_REGFILE_WRITE_DATA[30] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[31] Q=memory_to_writeBack_REGFILE_WRITE_DATA[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7897 Q=execute_to_memory_BRANCH_DO +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7117 Q=execute_to_memory_REGFILE_WRITE_DATA[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7115 Q=execute_to_memory_REGFILE_WRITE_DATA[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7113 Q=execute_to_memory_REGFILE_WRITE_DATA[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7111 Q=execute_to_memory_REGFILE_WRITE_DATA[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7109 Q=execute_to_memory_REGFILE_WRITE_DATA[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7107 Q=execute_to_memory_REGFILE_WRITE_DATA[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7105 Q=execute_to_memory_REGFILE_WRITE_DATA[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7103 Q=execute_to_memory_REGFILE_WRITE_DATA[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7101 Q=execute_to_memory_REGFILE_WRITE_DATA[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7099 Q=execute_to_memory_REGFILE_WRITE_DATA[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7097 Q=execute_to_memory_REGFILE_WRITE_DATA[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7095 Q=execute_to_memory_REGFILE_WRITE_DATA[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7093 Q=execute_to_memory_REGFILE_WRITE_DATA[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7091 Q=execute_to_memory_REGFILE_WRITE_DATA[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7089 Q=execute_to_memory_REGFILE_WRITE_DATA[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7087 Q=execute_to_memory_REGFILE_WRITE_DATA[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7085 Q=execute_to_memory_REGFILE_WRITE_DATA[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7083 Q=execute_to_memory_REGFILE_WRITE_DATA[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7081 Q=execute_to_memory_REGFILE_WRITE_DATA[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7079 Q=execute_to_memory_REGFILE_WRITE_DATA[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7077 Q=execute_to_memory_REGFILE_WRITE_DATA[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7075 Q=execute_to_memory_REGFILE_WRITE_DATA[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7073 Q=execute_to_memory_REGFILE_WRITE_DATA[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7071 Q=execute_to_memory_REGFILE_WRITE_DATA[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7069 Q=execute_to_memory_REGFILE_WRITE_DATA[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7067 Q=execute_to_memory_REGFILE_WRITE_DATA[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7065 Q=execute_to_memory_REGFILE_WRITE_DATA[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7063 Q=execute_to_memory_REGFILE_WRITE_DATA[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7061 Q=execute_to_memory_REGFILE_WRITE_DATA[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7059 Q=execute_to_memory_REGFILE_WRITE_DATA[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7057 Q=execute_to_memory_REGFILE_WRITE_DATA[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7899 Q=execute_to_memory_REGFILE_WRITE_DATA[31] +.subckt dff C=clk D=dBus_rsp_data[0] Q=memory_to_writeBack_MEMORY_READ_DATA[0] +.subckt dff C=clk D=dBus_rsp_data[1] Q=memory_to_writeBack_MEMORY_READ_DATA[1] +.subckt dff C=clk D=dBus_rsp_data[2] Q=memory_to_writeBack_MEMORY_READ_DATA[2] +.subckt dff C=clk D=dBus_rsp_data[3] Q=memory_to_writeBack_MEMORY_READ_DATA[3] +.subckt dff C=clk D=dBus_rsp_data[4] Q=memory_to_writeBack_MEMORY_READ_DATA[4] +.subckt dff C=clk D=dBus_rsp_data[5] Q=memory_to_writeBack_MEMORY_READ_DATA[5] +.subckt dff C=clk D=dBus_rsp_data[6] Q=memory_to_writeBack_MEMORY_READ_DATA[6] +.subckt dff C=clk D=dBus_rsp_data[7] Q=memory_to_writeBack_MEMORY_READ_DATA[7] +.subckt dff C=clk D=dBus_rsp_data[8] Q=memory_to_writeBack_MEMORY_READ_DATA[8] +.subckt dff C=clk D=dBus_rsp_data[9] Q=memory_to_writeBack_MEMORY_READ_DATA[9] +.subckt dff C=clk D=dBus_rsp_data[10] Q=memory_to_writeBack_MEMORY_READ_DATA[10] +.subckt dff C=clk D=dBus_rsp_data[11] Q=memory_to_writeBack_MEMORY_READ_DATA[11] +.subckt dff C=clk D=dBus_rsp_data[12] Q=memory_to_writeBack_MEMORY_READ_DATA[12] +.subckt dff C=clk D=dBus_rsp_data[13] Q=memory_to_writeBack_MEMORY_READ_DATA[13] +.subckt dff C=clk D=dBus_rsp_data[14] Q=memory_to_writeBack_MEMORY_READ_DATA[14] +.subckt dff C=clk D=dBus_rsp_data[15] Q=memory_to_writeBack_MEMORY_READ_DATA[15] +.subckt dff C=clk D=dBus_rsp_data[16] Q=memory_to_writeBack_MEMORY_READ_DATA[16] +.subckt dff C=clk D=dBus_rsp_data[17] Q=memory_to_writeBack_MEMORY_READ_DATA[17] +.subckt dff C=clk D=dBus_rsp_data[18] Q=memory_to_writeBack_MEMORY_READ_DATA[18] +.subckt dff C=clk D=dBus_rsp_data[19] Q=memory_to_writeBack_MEMORY_READ_DATA[19] +.subckt dff C=clk D=dBus_rsp_data[20] Q=writeBack_MEMORY_READ_DATA[20] +.subckt dff C=clk D=dBus_rsp_data[21] Q=writeBack_MEMORY_READ_DATA[21] +.subckt dff C=clk D=dBus_rsp_data[22] Q=writeBack_MEMORY_READ_DATA[22] +.subckt dff C=clk D=dBus_rsp_data[23] Q=writeBack_MEMORY_READ_DATA[23] +.subckt dff C=clk D=dBus_rsp_data[24] Q=writeBack_MEMORY_READ_DATA[24] +.subckt dff C=clk D=dBus_rsp_data[25] Q=writeBack_MEMORY_READ_DATA[25] +.subckt dff C=clk D=dBus_rsp_data[26] Q=writeBack_MEMORY_READ_DATA[26] +.subckt dff C=clk D=dBus_rsp_data[27] Q=writeBack_MEMORY_READ_DATA[27] +.subckt dff C=clk D=dBus_rsp_data[28] Q=writeBack_MEMORY_READ_DATA[28] +.subckt dff C=clk D=dBus_rsp_data[29] Q=writeBack_MEMORY_READ_DATA[29] +.subckt dff C=clk D=dBus_rsp_data[30] Q=writeBack_MEMORY_READ_DATA[30] +.subckt dff C=clk D=dBus_rsp_data[31] Q=writeBack_MEMORY_READ_DATA[31] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7055 Q=IBusSimplePlugin_fetchPc_pcReg[2] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7053 Q=IBusSimplePlugin_fetchPc_pcReg[3] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7051 Q=IBusSimplePlugin_fetchPc_pcReg[4] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7049 Q=IBusSimplePlugin_fetchPc_pcReg[5] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7047 Q=IBusSimplePlugin_fetchPc_pcReg[6] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7045 Q=IBusSimplePlugin_fetchPc_pcReg[7] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7043 Q=IBusSimplePlugin_fetchPc_pcReg[8] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7041 Q=IBusSimplePlugin_fetchPc_pcReg[9] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7039 Q=IBusSimplePlugin_fetchPc_pcReg[10] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7037 Q=IBusSimplePlugin_fetchPc_pcReg[11] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7035 Q=IBusSimplePlugin_fetchPc_pcReg[12] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7033 Q=IBusSimplePlugin_fetchPc_pcReg[13] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7031 Q=IBusSimplePlugin_fetchPc_pcReg[14] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7029 Q=IBusSimplePlugin_fetchPc_pcReg[15] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7027 Q=IBusSimplePlugin_fetchPc_pcReg[16] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7025 Q=IBusSimplePlugin_fetchPc_pcReg[17] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7023 Q=IBusSimplePlugin_fetchPc_pcReg[18] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7021 Q=IBusSimplePlugin_fetchPc_pcReg[19] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7019 Q=IBusSimplePlugin_fetchPc_pcReg[20] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7017 Q=IBusSimplePlugin_fetchPc_pcReg[21] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7015 Q=IBusSimplePlugin_fetchPc_pcReg[22] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7013 Q=IBusSimplePlugin_fetchPc_pcReg[23] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7011 Q=IBusSimplePlugin_fetchPc_pcReg[24] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7009 Q=IBusSimplePlugin_fetchPc_pcReg[25] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7007 Q=IBusSimplePlugin_fetchPc_pcReg[26] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7005 Q=IBusSimplePlugin_fetchPc_pcReg[27] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7003 Q=IBusSimplePlugin_fetchPc_pcReg[28] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7001 Q=IBusSimplePlugin_fetchPc_pcReg[29] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$6999 Q=IBusSimplePlugin_fetchPc_pcReg[30] R=reset +.subckt dffs C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7967 Q=IBusSimplePlugin_fetchPc_pcReg[31] S=reset +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7893 Q=execute_CsrPlugin_csr_768 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7891 Q=execute_CsrPlugin_csr_836 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7889 Q=execute_CsrPlugin_csr_772 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7887 Q=execute_CsrPlugin_csr_834 +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7885 Q=execute_arbitration_isValid R=reset +.subckt dffr C=clk D=$0\writeBack_arbitration_isValid[0:0] Q=lastStageIsFiring R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7883 Q=memory_arbitration_isValid R=reset +.subckt dffr C=clk D=$true Q=IBusSimplePlugin_fetchPc_booted R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7881 Q=IBusSimplePlugin_fetchPc_inc R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7879 Q=IBusSimplePlugin_iBusRsp_stages_1_input_valid R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[0] Q=IBusSimplePlugin_pending_value[0] R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[1] Q=IBusSimplePlugin_pending_value[1] R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[2] Q=IBusSimplePlugin_pending_value[2] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7877 Q=IBusSimplePlugin_injector_decodeInput_valid R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7875 Q=CsrPlugin_mie_MEIE R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7873 Q=CsrPlugin_mie_MTIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7871 Q=CsrPlugin_mie_MSIE R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7869 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7867 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset +.subckt dffs C=clk D=$false Q=_zz_5 S=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7865 Q=CsrPlugin_pipelineLiberator_done R=reset +.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2203[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2203[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2203[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2203[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2204[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2204[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2204[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2204[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.names $false BranchPlugin_jumpInterface_payload[0] +1 1 +.names $true CsrPlugin_interrupt_code[0] +1 1 +.names $true CsrPlugin_interrupt_code[1] +1 1 +.names $true CsrPlugin_mcause_exceptionCode[0] +1 1 +.names $true CsrPlugin_mcause_exceptionCode[1] +1 1 +.names $false CsrPlugin_mepc[0] +1 1 +.names $false CsrPlugin_mepc[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$2203[0] +1 1 +.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$2203[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$2203[2] +1 1 +.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$2203[3] +1 1 +.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$2203[4] +1 1 +.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$2203[5] +1 1 +.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$2203[6] +1 1 +.names _zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$2203[7] +1 1 +.names _zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$2203[8] +1 1 +.names _zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$2203[9] +1 1 +.names _zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$2203[10] +1 1 +.names _zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$2203[11] +1 1 +.names _zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$2203[12] +1 1 +.names _zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$2203[13] +1 1 +.names _zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$2203[14] +1 1 +.names _zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$2203[15] +1 1 +.names _zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$2203[16] +1 1 +.names _zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$2203[17] +1 1 +.names _zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$2203[18] +1 1 +.names _zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$2203[19] +1 1 +.names _zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$2203[20] +1 1 +.names _zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$2203[21] +1 1 +.names _zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$2203[22] +1 1 +.names _zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$2203[23] +1 1 +.names _zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$2203[24] +1 1 +.names _zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$2203[25] +1 1 +.names _zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$2203[26] +1 1 +.names _zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$2203[27] +1 1 +.names _zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$2203[28] +1 1 +.names _zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$2203[29] +1 1 +.names _zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$2203[30] +1 1 +.names _zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$2203[31] +1 1 +.names _zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$2204[0] +1 1 +.names _zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$2204[1] +1 1 +.names _zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$2204[2] +1 1 +.names _zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$2204[3] +1 1 +.names _zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$2204[4] +1 1 +.names _zz_RegFilePlugin_regFile_port0[5] $auto$memory_bram.cc:844:replace_memory$2204[5] +1 1 +.names _zz_RegFilePlugin_regFile_port0[6] $auto$memory_bram.cc:844:replace_memory$2204[6] +1 1 +.names _zz_RegFilePlugin_regFile_port0[7] $auto$memory_bram.cc:844:replace_memory$2204[7] +1 1 +.names _zz_RegFilePlugin_regFile_port0[8] $auto$memory_bram.cc:844:replace_memory$2204[8] +1 1 +.names _zz_RegFilePlugin_regFile_port0[9] $auto$memory_bram.cc:844:replace_memory$2204[9] +1 1 +.names _zz_RegFilePlugin_regFile_port0[10] $auto$memory_bram.cc:844:replace_memory$2204[10] +1 1 +.names _zz_RegFilePlugin_regFile_port0[11] $auto$memory_bram.cc:844:replace_memory$2204[11] +1 1 +.names _zz_RegFilePlugin_regFile_port0[12] $auto$memory_bram.cc:844:replace_memory$2204[12] +1 1 +.names _zz_RegFilePlugin_regFile_port0[13] $auto$memory_bram.cc:844:replace_memory$2204[13] +1 1 +.names _zz_RegFilePlugin_regFile_port0[14] $auto$memory_bram.cc:844:replace_memory$2204[14] +1 1 +.names _zz_RegFilePlugin_regFile_port0[15] $auto$memory_bram.cc:844:replace_memory$2204[15] +1 1 +.names _zz_RegFilePlugin_regFile_port0[16] $auto$memory_bram.cc:844:replace_memory$2204[16] +1 1 +.names _zz_RegFilePlugin_regFile_port0[17] $auto$memory_bram.cc:844:replace_memory$2204[17] +1 1 +.names _zz_RegFilePlugin_regFile_port0[18] $auto$memory_bram.cc:844:replace_memory$2204[18] +1 1 +.names _zz_RegFilePlugin_regFile_port0[19] $auto$memory_bram.cc:844:replace_memory$2204[19] +1 1 +.names _zz_RegFilePlugin_regFile_port0[20] $auto$memory_bram.cc:844:replace_memory$2204[20] +1 1 +.names _zz_RegFilePlugin_regFile_port0[21] $auto$memory_bram.cc:844:replace_memory$2204[21] +1 1 +.names _zz_RegFilePlugin_regFile_port0[22] $auto$memory_bram.cc:844:replace_memory$2204[22] +1 1 +.names _zz_RegFilePlugin_regFile_port0[23] $auto$memory_bram.cc:844:replace_memory$2204[23] +1 1 +.names _zz_RegFilePlugin_regFile_port0[24] $auto$memory_bram.cc:844:replace_memory$2204[24] +1 1 +.names _zz_RegFilePlugin_regFile_port0[25] $auto$memory_bram.cc:844:replace_memory$2204[25] +1 1 +.names _zz_RegFilePlugin_regFile_port0[26] $auto$memory_bram.cc:844:replace_memory$2204[26] +1 1 +.names _zz_RegFilePlugin_regFile_port0[27] $auto$memory_bram.cc:844:replace_memory$2204[27] +1 1 +.names _zz_RegFilePlugin_regFile_port0[28] $auto$memory_bram.cc:844:replace_memory$2204[28] +1 1 +.names _zz_RegFilePlugin_regFile_port0[29] $auto$memory_bram.cc:844:replace_memory$2204[29] +1 1 +.names _zz_RegFilePlugin_regFile_port0[30] $auto$memory_bram.cc:844:replace_memory$2204[30] +1 1 +.names _zz_RegFilePlugin_regFile_port0[31] $auto$memory_bram.cc:844:replace_memory$2204[31] +1 1 +.names $false IBusSimplePlugin_fetchPc_pcReg[0] +1 1 +.names $false IBusSimplePlugin_fetchPc_pcReg[1] +1 1 +.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[0] +1 1 +.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[1] +1 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] +1 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] +1 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] +1 1 +.names _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] +1 1 +.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[11] +1 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[12] +1 1 +.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[19] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[4] _zz__zz_execute_BranchPlugin_branch_src2_4[4] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2_4[5] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[6] _zz__zz_execute_BranchPlugin_branch_src2_4[6] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2_4[7] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[8] _zz__zz_execute_BranchPlugin_branch_src2_4[8] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[9] _zz__zz_execute_BranchPlugin_branch_src2_4[9] +1 1 +.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_4[11] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_lastStageRegFileWrite_payload_address[7] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_lastStageRegFileWrite_payload_address[8] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_lastStageRegFileWrite_payload_address[9] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_lastStageRegFileWrite_payload_address[10] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_lastStageRegFileWrite_payload_address[11] +1 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[1] +1 1 +.names $false decode_to_execute_PC[0] +1 1 +.names $false decode_to_execute_PC[1] +1 1 +.names dBus_cmd_payload_data[0] decode_to_execute_RS2[0] +1 1 +.names dBus_cmd_payload_data[1] decode_to_execute_RS2[1] +1 1 +.names dBus_cmd_payload_data[2] decode_to_execute_RS2[2] +1 1 +.names dBus_cmd_payload_data[3] decode_to_execute_RS2[3] +1 1 +.names dBus_cmd_payload_data[4] decode_to_execute_RS2[4] +1 1 +.names dBus_cmd_payload_data[5] decode_to_execute_RS2[5] +1 1 +.names dBus_cmd_payload_data[6] decode_to_execute_RS2[6] +1 1 +.names dBus_cmd_payload_data[7] decode_to_execute_RS2[7] +1 1 +.names $false iBus_cmd_payload_pc[0] +1 1 +.names $false iBus_cmd_payload_pc[1] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[0] writeBack_MEMORY_READ_DATA[0] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[1] writeBack_MEMORY_READ_DATA[1] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[2] writeBack_MEMORY_READ_DATA[2] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[3] writeBack_MEMORY_READ_DATA[3] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[4] writeBack_MEMORY_READ_DATA[4] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[5] writeBack_MEMORY_READ_DATA[5] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[6] writeBack_MEMORY_READ_DATA[6] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[7] writeBack_MEMORY_READ_DATA[7] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[8] writeBack_MEMORY_READ_DATA[8] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[9] writeBack_MEMORY_READ_DATA[9] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[10] writeBack_MEMORY_READ_DATA[10] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[11] writeBack_MEMORY_READ_DATA[11] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[12] writeBack_MEMORY_READ_DATA[12] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[13] writeBack_MEMORY_READ_DATA[13] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[14] writeBack_MEMORY_READ_DATA[14] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[15] writeBack_MEMORY_READ_DATA[15] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[16] writeBack_MEMORY_READ_DATA[16] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[17] writeBack_MEMORY_READ_DATA[17] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[18] writeBack_MEMORY_READ_DATA[18] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[19] writeBack_MEMORY_READ_DATA[19] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif new file mode 100644 index 00000000000..66d55f64118 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif @@ -0,0 +1,1473 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model boxcar +.inputs i_clk i_reset i_navg[0] i_navg[1] i_navg[2] i_navg[3] i_navg[4] i_navg[5] i_ce i_sample[0] i_sample[1] i_sample[2] i_sample[3] i_sample[4] i_sample[5] i_sample[6] i_sample[7] i_sample[8] i_sample[9] i_sample[10] i_sample[11] i_sample[12] i_sample[13] i_sample[14] i_sample[15] +.outputs o_result[0] o_result[1] o_result[2] o_result[3] o_result[4] o_result[5] o_result[6] o_result[7] o_result[8] o_result[9] o_result[10] o_result[11] o_result[12] o_result[13] o_result[14] o_result[15] o_result[16] o_result[17] o_result[18] o_result[19] o_result[20] o_result[21] +.names $false +.names $true +1 +.names $undef +.names wraddr[4] $abc$1868$new_n225 $abc$1868$auto$rtlil.cc:2693:MuxGate$1509 +01 1 +10 1 +.names wraddr[0] wraddr[1] wraddr[2] wraddr[3] i_ce $abc$1868$new_n225 +11111 1 +.names wraddr[3] wraddr[0] wraddr[1] wraddr[2] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1511 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names wraddr[2] wraddr[0] wraddr[1] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1513 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names wraddr[1] wraddr[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1515 +011 1 +100 1 +101 1 +110 1 +.names wraddr[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1517 +01 1 +10 1 +.names i_ce i_sample[14] preval[14] $abc$1868$auto$rtlil.cc:2693:MuxGate$1519 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[13] preval[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1521 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[12] preval[12] $abc$1868$auto$rtlil.cc:2693:MuxGate$1523 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[11] preval[11] $abc$1868$auto$rtlil.cc:2693:MuxGate$1525 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[10] preval[10] $abc$1868$auto$rtlil.cc:2693:MuxGate$1527 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[9] preval[9] $abc$1868$auto$rtlil.cc:2693:MuxGate$1529 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[8] preval[8] $abc$1868$auto$rtlil.cc:2693:MuxGate$1531 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[7] preval[7] $abc$1868$auto$rtlil.cc:2693:MuxGate$1533 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[6] preval[6] $abc$1868$auto$rtlil.cc:2693:MuxGate$1535 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[5] preval[5] $abc$1868$auto$rtlil.cc:2693:MuxGate$1537 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[4] preval[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1539 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[3] preval[3] $abc$1868$auto$rtlil.cc:2693:MuxGate$1541 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[2] preval[2] $abc$1868$auto$rtlil.cc:2693:MuxGate$1543 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[1] preval[1] $abc$1868$auto$rtlil.cc:2693:MuxGate$1545 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[0] preval[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1547 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[20] o_result[20] $abc$1868$auto$rtlil.cc:2693:MuxGate$1549 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[19] o_result[19] $abc$1868$auto$rtlil.cc:2693:MuxGate$1551 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[18] o_result[18] $abc$1868$auto$rtlil.cc:2693:MuxGate$1553 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[17] o_result[17] $abc$1868$auto$rtlil.cc:2693:MuxGate$1555 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[16] o_result[16] $abc$1868$auto$rtlil.cc:2693:MuxGate$1557 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[15] o_result[15] $abc$1868$auto$rtlil.cc:2693:MuxGate$1559 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[14] o_result[14] $abc$1868$auto$rtlil.cc:2693:MuxGate$1561 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[13] o_result[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1563 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[12] o_result[12] $abc$1868$auto$rtlil.cc:2693:MuxGate$1565 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[11] o_result[11] $abc$1868$auto$rtlil.cc:2693:MuxGate$1567 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[10] o_result[10] $abc$1868$auto$rtlil.cc:2693:MuxGate$1569 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[9] o_result[9] $abc$1868$auto$rtlil.cc:2693:MuxGate$1571 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[8] o_result[8] $abc$1868$auto$rtlil.cc:2693:MuxGate$1573 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[7] o_result[7] $abc$1868$auto$rtlil.cc:2693:MuxGate$1575 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[6] o_result[6] $abc$1868$auto$rtlil.cc:2693:MuxGate$1577 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[5] o_result[5] $abc$1868$auto$rtlil.cc:2693:MuxGate$1579 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[4] o_result[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1581 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[3] o_result[3] $abc$1868$auto$rtlil.cc:2693:MuxGate$1583 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[2] o_result[2] $abc$1868$auto$rtlil.cc:2693:MuxGate$1585 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[1] o_result[1] $abc$1868$auto$rtlil.cc:2693:MuxGate$1587 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[0] o_result[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1589 +001 1 +011 1 +110 1 +111 1 +.names i_ce $abc$1868$new_n267 sub[15] full preval[15] $abc$1868$auto$rtlil.cc:2693:MuxGate$1591 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names full $abc$1868$new_n288 preval[14] $abc$1868$new_n287 $abc$1868$new_n268 $abc$1868$new_n267 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names preval[13] $abc$1868$new_n284 $abc$1868$new_n286 $abc$1868$new_n269 $abc$1868$new_n285 $abc$1868$new_n268 +00001 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names preval[10] preval[11] $abc$1868$new_n283 $abc$1868$new_n282 $abc$1868$new_n270 $abc$1868$new_n269 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$1868$new_n281 preval[8] preval[9] $abc$1868$new_n280 $abc$1868$new_n271 $abc$1868$new_n270 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names preval[6] preval[7] $abc$1868$new_n279 $abc$1868$new_n278 $abc$1868$new_n272 $abc$1868$new_n271 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$1868$new_n277 preval[4] preval[5] $abc$1868$new_n276 $abc$1868$new_n273 $abc$1868$new_n272 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[3] $auto$mem.cc:1432:emulate_reset$543 preval[3] $abc$1868$new_n274 $abc$1868$new_n273 +0001 1 +0101 1 +1001 1 +1100 1 +1101 1 +1111 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[2] $auto$mem.cc:1432:emulate_reset$543 preval[2] $abc$1868$new_n275 $abc$1868$new_n274 +0001 1 +0101 1 +1001 1 +1100 1 +1101 1 +1111 1 +.names $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] $abc$1868$auto$mem.cc:1434:emulate_reset$545[1] preval[0] preval[1] $abc$1868$new_n275 +10100 1 +10110 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[5] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n276 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[4] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n277 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[7] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n278 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[6] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n279 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[9] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n280 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[8] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n281 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[11] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n282 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[10] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n283 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[13] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n284 +11 1 +.names preval[12] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $abc$1868$new_n285 +100 1 +101 1 +110 1 +.names preval[12] $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n286 +000 1 +001 1 +010 1 +111 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[14] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n287 +11 1 +.names preval[15] $abc$1868$auto$mem.cc:1434:emulate_reset$545[15] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n288 +000 1 +001 1 +010 1 +111 1 +.names i_ce full sub[14] $abc$1868$new_n290 preval[14] $abc$1868$auto$rtlil.cc:2693:MuxGate$1593 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[14] $abc$1868$new_n287 $abc$1868$new_n268 $abc$1868$new_n290 +000 1 +011 1 +101 1 +110 1 +.names i_ce full sub[12] $abc$1868$new_n295 preval[12] $abc$1868$auto$rtlil.cc:2693:MuxGate$1597 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$1868$new_n286 $abc$1868$new_n269 $abc$1868$new_n295 +01 1 +10 1 +.names i_ce full sub[10] $abc$1868$new_n300 preval[10] $abc$1868$auto$rtlil.cc:2693:MuxGate$1601 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[10] $abc$1868$new_n283 $abc$1868$new_n270 $abc$1868$new_n300 +001 1 +010 1 +100 1 +111 1 +.names i_ce full sub[8] $abc$1868$new_n305 preval[8] $abc$1868$auto$rtlil.cc:2693:MuxGate$1605 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[8] $abc$1868$new_n281 $abc$1868$new_n271 $abc$1868$new_n305 +000 1 +011 1 +101 1 +110 1 +.names i_ce full sub[7] $abc$1868$new_n307 preval[7] $abc$1868$auto$rtlil.cc:2693:MuxGate$1607 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[7] $abc$1868$new_n278 preval[6] $abc$1868$new_n279 $abc$1868$new_n272 $abc$1868$new_n307 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_ce full sub[6] $abc$1868$new_n309 preval[6] $abc$1868$auto$rtlil.cc:2693:MuxGate$1609 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[6] $abc$1868$new_n279 $abc$1868$new_n272 $abc$1868$new_n309 +001 1 +010 1 +100 1 +111 1 +.names i_ce full sub[5] $abc$1868$new_n311 preval[5] $abc$1868$auto$rtlil.cc:2693:MuxGate$1611 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[5] $abc$1868$new_n276 preval[4] $abc$1868$new_n277 $abc$1868$new_n273 $abc$1868$new_n311 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_ce full sub[4] $abc$1868$new_n313 preval[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1613 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[4] $abc$1868$new_n277 $abc$1868$new_n273 $abc$1868$new_n313 +001 1 +010 1 +100 1 +111 1 +.names i_ce full sub[3] $abc$1868$new_n315 preval[3] $abc$1868$auto$rtlil.cc:2693:MuxGate$1615 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[3] $abc$1868$new_n274 $abc$1868$auto$mem.cc:1434:emulate_reset$545[3] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n315 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names i_ce full sub[2] $abc$1868$new_n317 preval[2] $abc$1868$auto$rtlil.cc:2693:MuxGate$1617 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[2] $abc$1868$new_n275 $abc$1868$auto$mem.cc:1434:emulate_reset$545[2] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n317 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names i_ce full sub[1] $abc$1868$new_n319 preval[1] $abc$1868$auto$rtlil.cc:2693:MuxGate$1619 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[1] $abc$1868$auto$mem.cc:1434:emulate_reset$545[1] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] preval[0] $abc$1868$new_n319 +00110 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names i_ce $abc$1868$new_n321 sub[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1621 +001 1 +011 1 +100 1 +101 1 +.names preval[0] $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] $auto$mem.cc:1432:emulate_reset$543 full $abc$1868$new_n321 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1111 1 +.names acc[20] acc[18] acc[19] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1623 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[17] i_ce sub[16] acc[16] $abc$1868$new_n324 $abc$1868$new_n323 +11010 1 +11100 1 +11110 1 +11111 1 +.names sub[14] acc[14] sub[15] acc[15] $abc$1868$new_n325 $abc$1868$new_n324 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[12] acc[12] sub[13] acc[13] $abc$1868$new_n326 $abc$1868$new_n325 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[10] acc[10] sub[11] acc[11] $abc$1868$new_n327 $abc$1868$new_n326 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[8] acc[8] sub[9] acc[9] $abc$1868$new_n328 $abc$1868$new_n327 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[6] acc[6] sub[7] acc[7] $abc$1868$new_n329 $abc$1868$new_n328 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[4] acc[4] sub[5] acc[5] $abc$1868$new_n330 $abc$1868$new_n329 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[2] acc[2] sub[3] acc[3] $abc$1868$new_n331 $abc$1868$new_n330 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[0] acc[0] sub[1] acc[1] $abc$1868$new_n331 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names acc[19] acc[18] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1625 +011 1 +100 1 +101 1 +110 1 +.names acc[18] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1627 +01 1 +10 1 +.names acc[17] i_ce sub[16] acc[16] $abc$1868$new_n324 $abc$1868$auto$rtlil.cc:2693:MuxGate$1629 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names acc[16] sub[16] $abc$1868$new_n324 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1631 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[15] sub[15] $abc$1868$new_n337 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1633 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[14] acc[14] $abc$1868$new_n325 $abc$1868$new_n337 +000 1 +001 1 +011 1 +101 1 +.names acc[14] sub[14] $abc$1868$new_n325 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1635 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[13] sub[13] $abc$1868$new_n340 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1637 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[12] acc[12] $abc$1868$new_n326 $abc$1868$new_n340 +000 1 +001 1 +011 1 +101 1 +.names acc[12] sub[12] $abc$1868$new_n326 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1639 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[11] sub[11] $abc$1868$new_n343 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1641 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[10] acc[10] $abc$1868$new_n327 $abc$1868$new_n343 +000 1 +001 1 +011 1 +101 1 +.names acc[10] sub[10] $abc$1868$new_n327 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1643 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[9] sub[9] $abc$1868$new_n346 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1645 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[8] acc[8] $abc$1868$new_n328 $abc$1868$new_n346 +000 1 +001 1 +011 1 +101 1 +.names acc[8] sub[8] $abc$1868$new_n328 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1647 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[7] sub[7] $abc$1868$new_n349 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1649 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[6] acc[6] $abc$1868$new_n329 $abc$1868$new_n349 +000 1 +001 1 +011 1 +101 1 +.names acc[6] sub[6] $abc$1868$new_n329 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1651 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[5] sub[5] $abc$1868$new_n352 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1653 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[4] acc[4] $abc$1868$new_n330 $abc$1868$new_n352 +000 1 +001 1 +011 1 +101 1 +.names acc[4] sub[4] $abc$1868$new_n330 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1655 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[3] sub[3] $abc$1868$new_n355 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1657 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[2] acc[2] $abc$1868$new_n331 $abc$1868$new_n355 +000 1 +001 1 +011 1 +101 1 +.names acc[2] sub[2] $abc$1868$new_n331 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1659 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[1] sub[1] sub[0] acc[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1661 +00111 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names acc[0] sub[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1663 +011 1 +100 1 +101 1 +110 1 +.names i_reset rdaddr[4] $abc$1868$new_n360 $abc$1868$new_n363 $abc$1868$auto$rtlil.cc:2693:MuxGate$1665 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names rdaddr[3] i_ce $abc$1868$new_n361 $abc$1868$new_n360 +111 1 +.names rdaddr[2] $abc$1868$new_n362 $abc$1868$new_n361 +11 1 +.names rdaddr[0] rdaddr[1] $abc$1868$new_n362 +11 1 +.names i_navg[4] i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n363 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_reset rdaddr[3] i_ce $abc$1868$new_n361 $abc$1868$new_n365 $abc$1868$auto$rtlil.cc:2693:MuxGate$1667 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n365 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_reset rdaddr[2] i_ce $abc$1868$new_n362 $abc$1868$new_n367 $abc$1868$auto$rtlil.cc:2693:MuxGate$1669 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n367 +001 1 +010 1 +011 1 +100 1 +.names rdaddr[1] $abc$1868$new_n369 rdaddr[0] i_ce i_reset $abc$1868$auto$rtlil.cc:2693:MuxGate$1671 +00110 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_reset i_navg[1] i_navg[0] $abc$1868$new_n369 +101 1 +110 1 +.names i_reset rdaddr[0] i_ce i_navg[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1673 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names i_reset rdaddr[5] i_ce $abc$1868$new_n372 $abc$1868$new_n373 $abc$1868$auto$rtlil.cc:2693:MuxGate$1675 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names rdaddr[3] rdaddr[4] $abc$1868$new_n361 $abc$1868$new_n372 +111 1 +.names i_navg[5] $abc$1868$new_n374 $abc$1868$new_n373 +01 1 +10 1 +.names i_navg[4] i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n374 +00000 1 +.names i_ce acc[21] o_result[21] $abc$1868$auto$rtlil.cc:2693:MuxGate$1677 +001 1 +011 1 +110 1 +111 1 +.names acc[21] acc[18] acc[19] acc[20] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1679 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce sub[16] $abc$1868$new_n379 $abc$1868$new_n378 $abc$1868$auto$rtlil.cc:2693:MuxGate$1681 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$1868$new_n288 preval[14] $abc$1868$new_n287 $abc$1868$new_n268 $abc$1868$new_n378 +1001 1 +1100 1 +1101 1 +1111 1 +.names full preval[15] $abc$1868$auto$mem.cc:1434:emulate_reset$545[15] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n379 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names full $abc$1868$new_n381 i_ce rdaddr[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1683 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rdaddr[5] rdaddr[0] rdaddr[1] rdaddr[2] rdaddr[3] $abc$1868$new_n381 +00000 1 +.names i_ce i_sample[15] preval[15] $abc$1868$auto$rtlil.cc:2693:MuxGate$1685 +001 1 +011 1 +110 1 +111 1 +.names wraddr[5] wraddr[4] $abc$1868$new_n225 $abc$1868$auto$rtlil.cc:2693:MuxGate$1687 +011 1 +100 1 +101 1 +110 1 +.names $auto$mem.cc:1432:emulate_reset$543 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1689 +01 1 +10 1 +11 1 +.names $abc$1868$new_n284 $abc$1868$new_n269 preval[12] $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n385 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce preval[13] full $abc$1868$new_n385 sub[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1595 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[11] $abc$1868$new_n270 preval[10] $abc$1868$auto$mem.cc:1434:emulate_reset$545[10] $abc$1868$new_n387 +00100 1 +00101 1 +01100 1 +01101 1 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names i_ce preval[11] full $abc$1868$new_n387 sub[11] $abc$1868$auto$rtlil.cc:2693:MuxGate$1599 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[9] $abc$1868$new_n271 preval[8] $abc$1868$auto$mem.cc:1434:emulate_reset$545[8] $abc$1868$new_n389 +00000 1 +00001 1 +01000 1 +01001 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_ce preval[9] full $abc$1868$new_n389 sub[9] $abc$1868$auto$rtlil.cc:2693:MuxGate$1603 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1673 Q=rdaddr[0] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1671 Q=rdaddr[1] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1669 Q=rdaddr[2] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1667 Q=rdaddr[3] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1665 Q=rdaddr[4] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1675 Q=rdaddr[5] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1689 Q=$auto$mem.cc:1432:emulate_reset$543 +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1663 Q=acc[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1661 Q=acc[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1659 Q=acc[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1657 Q=acc[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1655 Q=acc[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1653 Q=acc[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1651 Q=acc[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1649 Q=acc[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1647 Q=acc[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1645 Q=acc[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1643 Q=acc[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1641 Q=acc[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1639 Q=acc[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1637 Q=acc[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1635 Q=acc[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1633 Q=acc[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1631 Q=acc[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1629 Q=acc[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1627 Q=acc[18] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1625 Q=acc[19] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1623 Q=acc[20] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1679 Q=acc[21] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1621 Q=sub[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1619 Q=sub[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1617 Q=sub[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1615 Q=sub[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1613 Q=sub[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1611 Q=sub[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1609 Q=sub[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1607 Q=sub[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1605 Q=sub[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1603 Q=sub[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1601 Q=sub[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1599 Q=sub[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1597 Q=sub[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1595 Q=sub[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1593 Q=sub[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1591 Q=sub[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1681 Q=sub[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1683 Q=full R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1589 Q=o_result[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1587 Q=o_result[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1585 Q=o_result[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1583 Q=o_result[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1581 Q=o_result[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1579 Q=o_result[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1577 Q=o_result[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1575 Q=o_result[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1573 Q=o_result[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1571 Q=o_result[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1569 Q=o_result[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1567 Q=o_result[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1565 Q=o_result[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1563 Q=o_result[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1561 Q=o_result[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1559 Q=o_result[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1557 Q=o_result[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1555 Q=o_result[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1553 Q=o_result[18] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1551 Q=o_result[19] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1549 Q=o_result[20] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1677 Q=o_result[21] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1547 Q=preval[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1545 Q=preval[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1543 Q=preval[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1541 Q=preval[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1539 Q=preval[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1537 Q=preval[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1535 Q=preval[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1533 Q=preval[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1531 Q=preval[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1529 Q=preval[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1527 Q=preval[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1525 Q=preval[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1523 Q=preval[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1521 Q=preval[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1519 Q=preval[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1685 Q=preval[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1517 Q=wraddr[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1515 Q=wraddr[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1513 Q=wraddr[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1511 Q=wraddr[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1509 Q=wraddr[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1687 Q=wraddr[5] R=i_reset +.subckt dpram512x18 bwen_ni[17]=$true bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[17]=i_sample[0] data_i[16]=i_sample[1] data_i[15]=i_sample[2] data_i[14]=i_sample[3] data_i[13]=i_sample[4] data_i[12]=i_sample[5] data_i[11]=i_sample[6] data_i[10]=i_sample[7] data_i[9]=i_sample[8] data_i[8]=i_sample[9] data_i[7]=i_sample[10] data_i[6]=i_sample[11] data_i[5]=i_sample[12] data_i[4]=i_sample[13] data_i[3]=i_sample[14] data_i[2]=i_sample[15] data_i[1]=$undef data_i[0]=$undef q_o[17]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[0] q_o[16]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[1] q_o[15]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[2] q_o[14]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[3] q_o[13]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[4] q_o[12]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[5] q_o[11]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[6] q_o[10]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[7] q_o[9]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[8] q_o[8]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[9] q_o[7]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[10] q_o[6]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[11] q_o[5]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[12] q_o[4]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[13] q_o[3]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[14] q_o[2]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[15] q_o[1]=$auto$memory_bram.cc:844:replace_memory$547[16] q_o[0]=$auto$memory_bram.cc:844:replace_memory$547[17] raddr_i[8]=rdaddr[0] raddr_i[7]=rdaddr[1] raddr_i[6]=rdaddr[2] raddr_i[5]=rdaddr[3] raddr_i[4]=rdaddr[4] raddr_i[3]=rdaddr[5] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=i_clk ren_ni=i_ce waddr_i[8]=wraddr[0] waddr_i[7]=wraddr[1] waddr_i[6]=wraddr[2] waddr_i[5]=wraddr[3] waddr_i[4]=wraddr[4] waddr_i[3]=wraddr[5] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=i_clk wen_ni=i_ce +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] $auto$memory_bram.cc:844:replace_memory$547[0] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[1] $auto$memory_bram.cc:844:replace_memory$547[1] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[2] $auto$memory_bram.cc:844:replace_memory$547[2] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[3] $auto$memory_bram.cc:844:replace_memory$547[3] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[4] $auto$memory_bram.cc:844:replace_memory$547[4] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[5] $auto$memory_bram.cc:844:replace_memory$547[5] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[6] $auto$memory_bram.cc:844:replace_memory$547[6] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[7] $auto$memory_bram.cc:844:replace_memory$547[7] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[8] $auto$memory_bram.cc:844:replace_memory$547[8] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[9] $auto$memory_bram.cc:844:replace_memory$547[9] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[10] $auto$memory_bram.cc:844:replace_memory$547[10] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[11] $auto$memory_bram.cc:844:replace_memory$547[11] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $auto$memory_bram.cc:844:replace_memory$547[12] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[13] $auto$memory_bram.cc:844:replace_memory$547[13] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[14] $auto$memory_bram.cc:844:replace_memory$547[14] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[15] $auto$memory_bram.cc:844:replace_memory$547[15] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif new file mode 100644 index 00000000000..5c089e7eadc --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif @@ -0,0 +1,27532 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model cordic +.inputs i_clk i_reset i_ce i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_phase[0] i_phase[1] i_phase[2] i_phase[3] i_phase[4] i_phase[5] i_phase[6] i_phase[7] i_phase[8] i_phase[9] i_phase[10] i_phase[11] i_phase[12] i_phase[13] i_phase[14] i_phase[15] i_phase[16] i_phase[17] i_phase[18] i_phase[19] i_aux +.outputs o_xval[0] o_xval[1] o_xval[2] o_xval[3] o_xval[4] o_xval[5] o_xval[6] o_xval[7] o_xval[8] o_xval[9] o_xval[10] o_xval[11] o_xval[12] o_yval[0] o_yval[1] o_yval[2] o_yval[3] o_yval[4] o_yval[5] o_yval[6] o_yval[7] o_yval[8] o_yval[9] o_yval[10] o_yval[11] o_yval[12] o_aux +.names $false +.names $true +1 +.names $undef +.names i_ce ax[15] ax[14] $abc$23348$auto$rtlil.cc:2693:MuxGate$19848 +010 1 +011 1 +101 1 +111 1 +.names i_ce ax[14] ax[13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19850 +010 1 +011 1 +101 1 +111 1 +.names i_ce ax[12] ax[13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19852 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[11] ax[12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19854 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[10] ax[11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19856 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[9] ax[10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19858 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[8] ax[9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19860 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[7] ax[8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19862 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[6] ax[7] $abc$23348$auto$rtlil.cc:2693:MuxGate$19864 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[5] ax[6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19866 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[4] ax[5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19868 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[3] ax[4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19870 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[2] ax[3] $abc$23348$auto$rtlil.cc:2693:MuxGate$19872 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[1] ax[2] $abc$23348$auto$rtlil.cc:2693:MuxGate$19874 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[0] ax[1] $abc$23348$auto$rtlil.cc:2693:MuxGate$19876 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_aux ax[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19878 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[17] ph[0][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$19880 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[17] ph[0][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$19882 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[16] ph[0][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$19884 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[15] ph[0][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$19886 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[14] ph[0][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$19888 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[13] ph[0][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19890 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[12] ph[0][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19892 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[11] ph[0][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19894 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[10] ph[0][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19896 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[9] ph[0][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19898 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[8] ph[0][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19900 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[7] ph[0][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$19902 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[6] ph[0][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19904 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[5] ph[0][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19906 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[4] ph[0][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19908 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[3] ph[0][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$19910 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[2] ph[0][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$19912 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[1] ph[0][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$19914 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[0] ph[0][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19916 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][14] $abc$23348$new_n1870 $abc$23348$new_n1874 $abc$23348$new_n1864 $abc$23348$auto$rtlil.cc:2693:MuxGate$19918 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$23348$new_n1869 i_yval[12] $abc$23348$new_n1865 $abc$23348$new_n1864 +100 1 +111 1 +.names $abc$23348$new_n1866 i_yval[11] i_yval[10] $abc$23348$new_n1865 +100 1 +.names $abc$23348$new_n1867 i_yval[9] $abc$23348$new_n1866 +10 1 +.names $abc$23348$new_n1868 i_yval[8] i_yval[7] i_yval[6] i_yval[5] $abc$23348$new_n1867 +10000 1 +.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1868 +00000 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1869 +011 1 +100 1 +.names i_xval[12] i_phase[19] $abc$23348$new_n1871 i_phase[18] i_phase[17] $abc$23348$new_n1870 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10011 1 +10100 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names $abc$23348$new_n1872 i_xval[11] i_xval[10] i_xval[9] $abc$23348$new_n1871 +1000 1 +.names $abc$23348$new_n1873 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$23348$new_n1872 +10000 1 +.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1873 +00000 1 +.names i_ce $abc$23348$new_n1875 i_yval[12] $abc$23348$new_n1874 +100 1 +101 1 +110 1 +.names i_phase[18] i_phase[19] i_phase[17] $abc$23348$new_n1875 +000 1 +111 1 +.names i_ce $abc$23348$new_n1877 yv[0][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19920 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1878 $abc$23348$new_n1881 $abc$23348$new_n1880 $abc$23348$new_n1875 i_yval[11] $abc$23348$new_n1877 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names i_phase[18] i_phase[17] i_phase[19] i_xval[11] $abc$23348$new_n1879 $abc$23348$new_n1878 +00101 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11011 1 +.names i_yval[11] $abc$23348$new_n1866 i_yval[10] $abc$23348$new_n1879 +000 1 +001 1 +011 1 +110 1 +.names i_xval[11] $abc$23348$new_n1872 i_xval[10] i_xval[9] $abc$23348$new_n1880 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1881 +101 1 +110 1 +.names i_ce $abc$23348$new_n1883 yv[0][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19922 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1884 $abc$23348$new_n1881 $abc$23348$new_n1886 $abc$23348$new_n1875 i_yval[10] $abc$23348$new_n1883 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[10] $abc$23348$new_n1866 i_xval[10] $abc$23348$new_n1884 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1885 +001 1 +010 1 +011 1 +100 1 +.names i_xval[10] $abc$23348$new_n1872 i_xval[9] $abc$23348$new_n1886 +000 1 +001 1 +011 1 +110 1 +.names i_ce $abc$23348$new_n1888 yv[0][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19924 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1889 $abc$23348$new_n1881 $abc$23348$new_n1890 $abc$23348$new_n1875 i_yval[9] $abc$23348$new_n1888 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[9] $abc$23348$new_n1867 i_xval[9] $abc$23348$new_n1889 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_xval[9] $abc$23348$new_n1872 $abc$23348$new_n1890 +00 1 +11 1 +.names i_ce $abc$23348$new_n1892 yv[0][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19926 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1893 $abc$23348$new_n1881 $abc$23348$new_n1895 $abc$23348$new_n1875 i_yval[8] $abc$23348$new_n1892 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n1894 i_xval[8] $abc$23348$new_n1893 +1001 1 +1011 1 +1110 1 +1111 1 +.names i_yval[8] $abc$23348$new_n1868 i_yval[7] i_yval[6] i_yval[5] $abc$23348$new_n1894 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names i_xval[8] $abc$23348$new_n1873 i_xval[7] i_xval[6] i_xval[5] $abc$23348$new_n1895 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names $abc$23348$new_n1899 $abc$23348$new_n1897 yv[0][9] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19928 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n1898 i_xval[7] $abc$23348$new_n1897 +1001 1 +1011 1 +1110 1 +1111 1 +.names i_yval[7] $abc$23348$new_n1868 i_yval[6] i_yval[5] $abc$23348$new_n1898 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n1900 $abc$23348$new_n1881 $abc$23348$new_n1875 i_yval[7] $abc$23348$new_n1899 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names i_xval[7] $abc$23348$new_n1873 i_xval[6] i_xval[5] $abc$23348$new_n1900 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n1902 yv[0][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19930 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1903 $abc$23348$new_n1881 $abc$23348$new_n1905 $abc$23348$new_n1875 i_yval[6] $abc$23348$new_n1902 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n1904 i_xval[6] $abc$23348$new_n1903 +1001 1 +1011 1 +1110 1 +1111 1 +.names i_yval[6] $abc$23348$new_n1868 i_yval[5] $abc$23348$new_n1904 +000 1 +001 1 +011 1 +110 1 +.names i_xval[6] $abc$23348$new_n1873 i_xval[5] $abc$23348$new_n1905 +000 1 +001 1 +011 1 +110 1 +.names i_ce yv[0][7] $abc$23348$new_n1909 $abc$23348$new_n1908 $abc$23348$new_n1907 $abc$23348$auto$rtlil.cc:2693:MuxGate$19932 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[5] $abc$23348$new_n1868 i_xval[5] $abc$23348$new_n1907 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n1881 i_xval[5] $abc$23348$new_n1873 $abc$23348$new_n1908 +100 1 +111 1 +.names i_yval[5] $abc$23348$new_n1875 $abc$23348$new_n1909 +11 1 +.names i_ce $abc$23348$new_n1911 yv[0][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19934 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1912 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1914 i_xval[4] $abc$23348$new_n1911 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n1913 $abc$23348$new_n1881 i_yval[4] $abc$23348$new_n1875 $abc$23348$new_n1912 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1913 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1914 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_ce $abc$23348$new_n1916 yv[0][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19936 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1917 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1919 i_xval[3] $abc$23348$new_n1916 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n1918 $abc$23348$new_n1881 i_yval[3] $abc$23348$new_n1875 $abc$23348$new_n1917 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1918 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1919 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_ce $abc$23348$new_n1921 yv[0][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19938 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1922 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1924 i_xval[2] $abc$23348$new_n1921 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n1923 $abc$23348$new_n1881 i_yval[2] $abc$23348$new_n1875 $abc$23348$new_n1922 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1923 +001 1 +010 1 +011 1 +100 1 +.names i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1924 +001 1 +010 1 +011 1 +100 1 +.names i_ce yv[0][3] $abc$23348$new_n1927 $abc$23348$new_n1926 $abc$23348$auto$rtlil.cc:2693:MuxGate$19940 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[1] i_yval[0] i_xval[1] $abc$23348$new_n1926 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n1881 i_xval[1] i_xval[0] i_yval[1] $abc$23348$new_n1875 $abc$23348$new_n1927 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n1929 yv[0][2] i_yval[0] i_xval[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19942 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$23348$new_n1875 $abc$23348$new_n1869 $abc$23348$new_n1929 +01 1 +10 1 +11 1 +.names yv[0][1] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19944 +10 1 +.names yv[0][0] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19946 +10 1 +.names $abc$23348$new_n1935 $abc$23348$new_n1933 xv[0][14] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19948 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[12] $abc$23348$new_n1865 $abc$23348$new_n1934 $abc$23348$new_n1933 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_xval[12] $abc$23348$new_n1871 $abc$23348$new_n1934 +01 1 +10 1 +.names i_ce i_yval[12] $abc$23348$new_n1881 i_xval[12] $abc$23348$new_n1875 $abc$23348$new_n1935 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n1937 xv[0][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19950 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1938 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1879 $abc$23348$new_n1880 $abc$23348$new_n1937 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_yval[11] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[11] $abc$23348$new_n1938 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1940 xv[0][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19952 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1941 i_yval[10] $abc$23348$new_n1881 i_xval[10] $abc$23348$new_n1875 $abc$23348$new_n1940 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[10] $abc$23348$new_n1866 $abc$23348$new_n1886 $abc$23348$new_n1941 +10000 1 +10001 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n1943 xv[0][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19954 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1944 i_yval[9] $abc$23348$new_n1881 i_xval[9] $abc$23348$new_n1875 $abc$23348$new_n1943 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[9] $abc$23348$new_n1867 $abc$23348$new_n1890 $abc$23348$new_n1944 +10000 1 +10001 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n1946 xv[0][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19956 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1947 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1894 $abc$23348$new_n1895 $abc$23348$new_n1946 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_yval[8] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[8] $abc$23348$new_n1947 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1949 xv[0][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19958 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1950 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1898 $abc$23348$new_n1900 $abc$23348$new_n1949 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_yval[7] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[7] $abc$23348$new_n1950 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1952 xv[0][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19960 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1953 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1904 $abc$23348$new_n1905 $abc$23348$new_n1952 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_yval[6] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[6] $abc$23348$new_n1953 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1956 xv[0][7] $abc$23348$new_n1885 $abc$23348$new_n1955 $abc$23348$auto$rtlil.cc:2693:MuxGate$19962 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$23348$new_n1869 i_xval[5] $abc$23348$new_n1873 i_yval[5] $abc$23348$new_n1868 $abc$23348$new_n1955 +00001 1 +00010 1 +00101 1 +00110 1 +01001 1 +01010 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_yval[5] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[5] $abc$23348$new_n1956 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1958 xv[0][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19964 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1959 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1913 $abc$23348$new_n1914 $abc$23348$new_n1958 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_yval[4] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[4] $abc$23348$new_n1959 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1961 xv[0][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19966 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1962 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1918 $abc$23348$new_n1919 $abc$23348$new_n1961 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_yval[3] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[3] $abc$23348$new_n1962 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1965 xv[0][4] $abc$23348$new_n1885 $abc$23348$new_n1964 $abc$23348$auto$rtlil.cc:2693:MuxGate$19968 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$23348$new_n1869 $abc$23348$new_n1923 $abc$23348$new_n1924 $abc$23348$new_n1964 +000 1 +010 1 +100 1 +101 1 +.names i_yval[2] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[2] $abc$23348$new_n1965 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_yval[1] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[1] $abc$23348$new_n1969 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1929 xv[0][2] i_xval[0] i_yval[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19972 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[0][1] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19974 +10 1 +.names xv[0][0] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19976 +10 1 +.names i_ce yv[16][14] yv[16][13] $abc$23348$new_n1974 o_yval[11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19978 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[16][11] yv[16][12] $abc$23348$new_n1975 $abc$23348$new_n1974 +111 1 +.names yv[16][7] yv[16][8] yv[16][9] yv[16][10] $abc$23348$new_n1976 $abc$23348$new_n1975 +11111 1 +.names yv[16][2] yv[16][3] yv[16][4] yv[16][5] yv[16][6] $abc$23348$new_n1976 +11111 1 +.names i_ce yv[16][13] $abc$23348$new_n1974 o_yval[10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19980 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[16][12] yv[16][11] $abc$23348$new_n1975 o_yval[9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19982 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[16][11] $abc$23348$new_n1975 o_yval[8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19984 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n1981 o_yval[7] $abc$23348$auto$rtlil.cc:2693:MuxGate$19986 +001 1 +011 1 +110 1 +111 1 +.names yv[16][10] yv[16][7] yv[16][8] yv[16][9] $abc$23348$new_n1976 $abc$23348$new_n1981 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n1983 o_yval[6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19988 +001 1 +011 1 +110 1 +111 1 +.names yv[16][9] yv[16][7] yv[16][8] $abc$23348$new_n1976 $abc$23348$new_n1983 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce yv[16][8] yv[16][7] $abc$23348$new_n1976 o_yval[5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19990 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[16][7] $abc$23348$new_n1976 o_yval[4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19992 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n1987 o_yval[3] $abc$23348$auto$rtlil.cc:2693:MuxGate$19994 +001 1 +011 1 +110 1 +111 1 +.names yv[16][6] yv[16][2] yv[16][3] yv[16][4] yv[16][5] $abc$23348$new_n1987 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n1989 o_yval[2] $abc$23348$auto$rtlil.cc:2693:MuxGate$19996 +001 1 +011 1 +110 1 +111 1 +.names yv[16][5] yv[16][2] yv[16][3] yv[16][4] $abc$23348$new_n1989 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce yv[16][4] yv[16][2] yv[16][3] o_yval[1] $abc$23348$auto$rtlil.cc:2693:MuxGate$19998 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n1992 o_yval[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20000 +001 1 +011 1 +110 1 +111 1 +.names yv[16][2] yv[16][3] yv[16][1] yv[16][0] $abc$23348$new_n1992 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names i_ce xv[16][14] xv[16][13] $abc$23348$new_n1994 o_xval[11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20002 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[16][11] xv[16][12] $abc$23348$new_n1995 $abc$23348$new_n1994 +111 1 +.names xv[16][7] xv[16][8] xv[16][9] xv[16][10] $abc$23348$new_n1996 $abc$23348$new_n1995 +11111 1 +.names xv[16][2] xv[16][3] xv[16][4] xv[16][5] xv[16][6] $abc$23348$new_n1996 +11111 1 +.names i_ce xv[16][13] $abc$23348$new_n1994 o_xval[10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20004 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][12] xv[16][11] $abc$23348$new_n1995 o_xval[9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20006 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[16][11] $abc$23348$new_n1995 o_xval[8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20008 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2001 o_xval[7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20010 +001 1 +011 1 +110 1 +111 1 +.names xv[16][10] xv[16][7] xv[16][8] xv[16][9] $abc$23348$new_n1996 $abc$23348$new_n2001 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n2003 o_xval[6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20012 +001 1 +011 1 +110 1 +111 1 +.names xv[16][9] xv[16][7] xv[16][8] $abc$23348$new_n1996 $abc$23348$new_n2003 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[16][8] xv[16][7] $abc$23348$new_n1996 o_xval[5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20014 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[16][7] $abc$23348$new_n1996 o_xval[4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20016 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2007 o_xval[3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20018 +001 1 +011 1 +110 1 +111 1 +.names xv[16][6] xv[16][2] xv[16][3] xv[16][4] xv[16][5] $abc$23348$new_n2007 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n2009 o_xval[2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20020 +001 1 +011 1 +110 1 +111 1 +.names xv[16][5] xv[16][2] xv[16][3] xv[16][4] $abc$23348$new_n2009 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[16][4] xv[16][2] xv[16][3] o_xval[1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20022 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2012 o_xval[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20024 +001 1 +011 1 +110 1 +111 1 +.names xv[16][2] xv[16][3] xv[16][1] xv[16][0] $abc$23348$new_n2012 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names i_ce ph[0][18] $abc$23348$new_n2019 $abc$23348$new_n2014 ph[1][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20026 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2015 ph[0][17] ph[0][19] $abc$23348$new_n2014 +000 1 +010 1 +011 1 +.names ph[0][19] ph[0][16] $abc$23348$new_n2016 ph[0][15] ph[0][14] $abc$23348$new_n2015 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names ph[0][13] ph[0][12] $abc$23348$new_n2017 ph[0][11] $abc$23348$new_n2016 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$23348$new_n2018 ph[0][10] $abc$23348$new_n2017 +10 1 +.names ph[0][9] ph[0][7] ph[0][8] ph[0][6] $abc$23348$new_n2018 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[0][19] ph[0][17] ph[0][16] $abc$23348$new_n2020 $abc$23348$new_n2019 +0000 1 +0001 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[0][14] ph[0][15] $abc$23348$new_n2021 $abc$23348$new_n2020 +000 1 +.names ph[0][13] ph[0][12] ph[0][11] $abc$23348$new_n2022 $abc$23348$new_n2021 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[0][10] $abc$23348$new_n2023 $abc$23348$new_n2022 +11 1 +.names ph[0][9] ph[0][7] ph[0][8] ph[0][6] $abc$23348$new_n2023 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n2025 ph[1][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20028 +001 1 +011 1 +100 1 +101 1 +.names ph[0][17] $abc$23348$new_n2015 ph[0][16] ph[0][19] $abc$23348$new_n2020 $abc$23348$new_n2025 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names i_ce $abc$23348$new_n2027 ph[1][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20030 +001 1 +011 1 +110 1 +111 1 +.names ph[0][16] ph[0][14] ph[0][15] $abc$23348$new_n2029 $abc$23348$new_n2028 $abc$23348$new_n2027 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11101 1 +11111 1 +.names ph[0][19] $abc$23348$new_n2016 $abc$23348$new_n2028 +10 1 +.names ph[0][19] $abc$23348$new_n2021 $abc$23348$new_n2029 +00 1 +.names i_ce $abc$23348$new_n2031 ph[1][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20032 +001 1 +011 1 +110 1 +111 1 +.names ph[0][15] ph[0][14] $abc$23348$new_n2029 $abc$23348$new_n2028 $abc$23348$new_n2031 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[0][14] $abc$23348$new_n2029 $abc$23348$new_n2028 ph[1][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20034 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2034 ph[0][13] ph[1][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20036 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[0][19] ph[0][12] ph[0][11] $abc$23348$new_n2017 $abc$23348$new_n2022 $abc$23348$new_n2034 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2036 ph[1][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20038 +001 1 +011 1 +100 1 +101 1 +.names ph[0][10] ph[0][12] ph[0][11] $abc$23348$new_n2038 $abc$23348$new_n2037 $abc$23348$new_n2036 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] $abc$23348$new_n2018 $abc$23348$new_n2037 +11 1 +.names $abc$23348$new_n2023 ph[0][19] $abc$23348$new_n2038 +10 1 +.names i_ce $abc$23348$new_n2040 ph[1][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20040 +001 1 +011 1 +100 1 +101 1 +.names ph[0][10] ph[0][11] $abc$23348$new_n2038 $abc$23348$new_n2037 $abc$23348$new_n2040 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[0][10] $abc$23348$new_n2038 $abc$23348$new_n2037 ph[1][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20042 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2043 ph[1][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20044 +001 1 +011 1 +110 1 +111 1 +.names ph[0][9] ph[0][19] ph[0][6] ph[0][7] ph[0][8] $abc$23348$new_n2043 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11111 1 +.names i_ce $abc$23348$new_n2045 ph[1][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20046 +001 1 +011 1 +100 1 +101 1 +.names ph[0][8] ph[0][19] ph[0][6] ph[0][7] $abc$23348$new_n2045 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[0][19] ph[0][6] ph[0][7] ph[1][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20048 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[0][6] ph[1][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20050 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[0][5] ph[1][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20052 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][4] ph[1][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20054 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][3] ph[1][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20056 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][2] ph[1][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20058 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][1] ph[1][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20060 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][0] ph[1][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20062 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[0][15] yv[0][14] $abc$23348$new_n2055 yv[1][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20064 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] $abc$23348$new_n2056 $abc$23348$new_n2063 $abc$23348$new_n2055 +000 1 +001 1 +101 1 +111 1 +.names xv[0][13] yv[0][12] xv[0][14] yv[0][13] $abc$23348$new_n2057 $abc$23348$new_n2056 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][11] yv[0][10] xv[0][12] yv[0][11] $abc$23348$new_n2058 $abc$23348$new_n2057 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][9] yv[0][8] xv[0][10] yv[0][9] $abc$23348$new_n2059 $abc$23348$new_n2058 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][7] yv[0][6] xv[0][8] yv[0][7] $abc$23348$new_n2060 $abc$23348$new_n2059 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][5] yv[0][4] xv[0][6] yv[0][5] $abc$23348$new_n2061 $abc$23348$new_n2060 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][3] yv[0][2] xv[0][4] yv[0][3] $abc$23348$new_n2062 $abc$23348$new_n2061 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][1] yv[0][0] xv[0][2] yv[0][1] $abc$23348$new_n2062 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[0][13] xv[0][14] yv[0][12] yv[0][13] $abc$23348$new_n2064 $abc$23348$new_n2063 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][11] xv[0][12] yv[0][10] yv[0][11] $abc$23348$new_n2065 $abc$23348$new_n2064 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][9] xv[0][10] yv[0][8] yv[0][9] $abc$23348$new_n2066 $abc$23348$new_n2065 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][7] xv[0][8] yv[0][6] yv[0][7] $abc$23348$new_n2067 $abc$23348$new_n2066 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][5] xv[0][6] yv[0][4] yv[0][5] $abc$23348$new_n2068 $abc$23348$new_n2067 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][3] xv[0][4] yv[0][2] yv[0][3] $abc$23348$new_n2069 $abc$23348$new_n2068 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[0][1] xv[0][2] yv[0][0] yv[0][1] $abc$23348$new_n2069 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce $abc$23348$new_n2075 yv[1][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20068 +001 1 +011 1 +110 1 +111 1 +.names ph[0][19] xv[0][13] yv[0][12] $abc$23348$new_n2064 $abc$23348$new_n2057 $abc$23348$new_n2075 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2081 yv[1][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20072 +001 1 +011 1 +100 1 +101 1 +.names ph[0][19] xv[0][11] yv[0][10] $abc$23348$new_n2065 $abc$23348$new_n2058 $abc$23348$new_n2081 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[0][10] yv[0][9] $abc$23348$new_n2083 yv[1][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20074 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][9] yv[0][8] $abc$23348$new_n2066 $abc$23348$new_n2059 $abc$23348$new_n2083 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2085 yv[1][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20076 +001 1 +011 1 +100 1 +101 1 +.names ph[0][19] xv[0][9] yv[0][8] $abc$23348$new_n2066 $abc$23348$new_n2059 $abc$23348$new_n2085 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[0][8] yv[0][7] $abc$23348$new_n2087 yv[1][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20078 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][7] yv[0][6] $abc$23348$new_n2067 $abc$23348$new_n2060 $abc$23348$new_n2087 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2089 yv[1][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20080 +001 1 +011 1 +100 1 +101 1 +.names ph[0][19] xv[0][7] yv[0][6] $abc$23348$new_n2067 $abc$23348$new_n2060 $abc$23348$new_n2089 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[0][6] yv[0][5] $abc$23348$new_n2091 yv[1][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20082 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][5] yv[0][4] $abc$23348$new_n2068 $abc$23348$new_n2061 $abc$23348$new_n2091 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2093 yv[1][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20084 +001 1 +011 1 +110 1 +111 1 +.names ph[0][19] xv[0][5] yv[0][4] $abc$23348$new_n2068 $abc$23348$new_n2061 $abc$23348$new_n2093 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[0][4] yv[0][3] $abc$23348$new_n2095 yv[1][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20086 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] yv[0][2] xv[0][3] $abc$23348$new_n2069 $abc$23348$new_n2062 $abc$23348$new_n2095 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[0][3] yv[0][2] $abc$23348$new_n2097 yv[1][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20088 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] $abc$23348$new_n2062 $abc$23348$new_n2069 $abc$23348$new_n2097 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$23348$new_n2099 yv[1][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20090 +001 1 +011 1 +110 1 +111 1 +.names xv[0][2] yv[0][1] ph[0][19] yv[0][0] xv[0][1] $abc$23348$new_n2099 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[0][1] yv[0][0] yv[1][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20092 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[0][15] xv[0][14] $abc$23348$new_n2102 xv[1][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20094 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] $abc$23348$new_n2103 $abc$23348$new_n2110 $abc$23348$new_n2102 +001 1 +011 1 +100 1 +101 1 +.names xv[0][12] yv[0][13] xv[0][13] yv[0][14] $abc$23348$new_n2104 $abc$23348$new_n2103 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][10] yv[0][11] xv[0][11] yv[0][12] $abc$23348$new_n2105 $abc$23348$new_n2104 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][8] yv[0][9] xv[0][9] yv[0][10] $abc$23348$new_n2106 $abc$23348$new_n2105 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][6] yv[0][7] xv[0][7] yv[0][8] $abc$23348$new_n2107 $abc$23348$new_n2106 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][4] yv[0][5] xv[0][5] yv[0][6] $abc$23348$new_n2108 $abc$23348$new_n2107 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[0][2] yv[0][3] xv[0][3] yv[0][4] $abc$23348$new_n2109 $abc$23348$new_n2108 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][0] yv[0][1] xv[0][1] yv[0][2] $abc$23348$new_n2109 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[0][13] xv[0][12] xv[0][13] yv[0][14] $abc$23348$new_n2111 $abc$23348$new_n2110 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[0][10] xv[0][11] yv[0][11] yv[0][12] $abc$23348$new_n2112 $abc$23348$new_n2111 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[0][9] xv[0][8] xv[0][9] yv[0][10] $abc$23348$new_n2113 $abc$23348$new_n2112 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[0][6] xv[0][7] yv[0][7] yv[0][8] $abc$23348$new_n2114 $abc$23348$new_n2113 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[0][5] xv[0][4] xv[0][5] yv[0][6] $abc$23348$new_n2115 $abc$23348$new_n2114 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][3] xv[0][2] xv[0][3] yv[0][4] $abc$23348$new_n2116 $abc$23348$new_n2115 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][1] xv[0][0] xv[0][1] yv[0][2] $abc$23348$new_n2116 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names i_ce xv[0][13] yv[0][14] $abc$23348$new_n2118 xv[1][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20096 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][12] yv[0][13] $abc$23348$new_n2111 $abc$23348$new_n2104 $abc$23348$new_n2118 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2120 xv[1][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20098 +001 1 +011 1 +100 1 +101 1 +.names xv[0][12] yv[0][13] ph[0][19] $abc$23348$new_n2111 $abc$23348$new_n2104 $abc$23348$new_n2120 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][11] yv[0][12] $abc$23348$new_n2122 xv[1][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20100 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][10] yv[0][11] $abc$23348$new_n2112 $abc$23348$new_n2105 $abc$23348$new_n2122 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2124 xv[1][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20102 +001 1 +011 1 +110 1 +111 1 +.names xv[0][10] yv[0][11] ph[0][19] $abc$23348$new_n2112 $abc$23348$new_n2105 $abc$23348$new_n2124 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][9] yv[0][10] $abc$23348$new_n2126 xv[1][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20104 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][8] yv[0][9] $abc$23348$new_n2113 $abc$23348$new_n2106 $abc$23348$new_n2126 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2128 xv[1][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20106 +001 1 +011 1 +100 1 +101 1 +.names xv[0][8] yv[0][9] ph[0][19] $abc$23348$new_n2113 $abc$23348$new_n2106 $abc$23348$new_n2128 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][7] yv[0][8] $abc$23348$new_n2130 xv[1][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20108 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][6] yv[0][7] $abc$23348$new_n2114 $abc$23348$new_n2107 $abc$23348$new_n2130 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2132 xv[1][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20110 +001 1 +011 1 +110 1 +111 1 +.names xv[0][6] yv[0][7] ph[0][19] $abc$23348$new_n2114 $abc$23348$new_n2107 $abc$23348$new_n2132 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][5] yv[0][6] $abc$23348$new_n2134 xv[1][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20112 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][4] yv[0][5] $abc$23348$new_n2115 $abc$23348$new_n2108 $abc$23348$new_n2134 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names i_ce $abc$23348$new_n2136 xv[1][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20114 +001 1 +011 1 +110 1 +111 1 +.names xv[0][4] yv[0][5] ph[0][19] $abc$23348$new_n2115 $abc$23348$new_n2108 $abc$23348$new_n2136 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][3] yv[0][4] $abc$23348$new_n2138 xv[1][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20116 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][2] yv[0][3] $abc$23348$new_n2116 $abc$23348$new_n2109 $abc$23348$new_n2138 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[0][2] yv[0][3] $abc$23348$new_n2140 xv[1][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20118 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] $abc$23348$new_n2109 $abc$23348$new_n2116 $abc$23348$new_n2140 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n2142 xv[1][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20120 +001 1 +011 1 +110 1 +111 1 +.names xv[0][1] yv[0][2] ph[0][19] xv[0][0] yv[0][1] $abc$23348$new_n2142 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[0][0] yv[0][1] xv[1][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20122 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2145 ph[2][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20124 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] ph[1][18] ph[1][17] $abc$23348$new_n2151 $abc$23348$new_n2146 $abc$23348$new_n2145 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[1][16] ph[1][15] ph[1][13] $abc$23348$new_n2147 $abc$23348$new_n2146 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[1][14] $abc$23348$new_n2148 $abc$23348$new_n2147 +10 1 +.names $abc$23348$new_n2150 ph[1][7] ph[1][6] $abc$23348$new_n2149 ph[1][5] $abc$23348$new_n2148 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +.names ph[1][4] ph[1][3] ph[1][2] ph[1][0] ph[1][1] $abc$23348$new_n2149 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +.names ph[1][8] ph[1][9] ph[1][10] ph[1][11] ph[1][12] $abc$23348$new_n2150 +00000 1 +.names ph[1][16] ph[1][15] $abc$23348$new_n2152 ph[1][13] $abc$23348$new_n2151 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names ph[1][14] $abc$23348$new_n2153 $abc$23348$new_n2152 +00 1 +.names ph[1][7] $abc$23348$new_n2155 ph[1][6] ph[1][5] $abc$23348$new_n2154 $abc$23348$new_n2153 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[1][4] ph[1][3] ph[1][2] ph[1][0] ph[1][1] $abc$23348$new_n2154 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[1][8] ph[1][9] ph[1][10] ph[1][11] ph[1][12] $abc$23348$new_n2155 +11111 1 +.names i_ce $abc$23348$new_n2157 ph[2][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20126 +001 1 +011 1 +110 1 +111 1 +.names ph[1][17] ph[1][19] $abc$23348$new_n2151 $abc$23348$new_n2146 $abc$23348$new_n2157 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n2159 ph[1][16] ph[2][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20128 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[1][19] ph[1][15] ph[1][13] $abc$23348$new_n2147 $abc$23348$new_n2152 $abc$23348$new_n2159 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names i_ce $abc$23348$new_n2161 ph[2][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20130 +001 1 +011 1 +110 1 +111 1 +.names ph[1][15] ph[1][13] ph[1][14] $abc$23348$new_n2163 $abc$23348$new_n2162 $abc$23348$new_n2161 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2153 $abc$23348$new_n2162 +00 1 +.names ph[1][19] $abc$23348$new_n2148 $abc$23348$new_n2163 +10 1 +.names i_ce $abc$23348$new_n2165 ph[2][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20132 +001 1 +011 1 +110 1 +111 1 +.names ph[1][13] ph[1][14] $abc$23348$new_n2163 $abc$23348$new_n2162 $abc$23348$new_n2165 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[1][13] $abc$23348$new_n2163 $abc$23348$new_n2162 ph[2][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20134 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2168 ph[2][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20136 +001 1 +011 1 +110 1 +111 1 +.names ph[1][11] ph[1][12] $abc$23348$new_n2172 $abc$23348$new_n2169 $abc$23348$new_n2168 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$23348$new_n2170 ph[1][8] ph[1][9] ph[1][10] $abc$23348$new_n2169 +1000 1 +.names $abc$23348$new_n2171 ph[1][7] $abc$23348$new_n2170 +10 1 +.names ph[1][19] ph[1][6] $abc$23348$new_n2149 ph[1][5] $abc$23348$new_n2171 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names ph[1][8] ph[1][9] ph[1][10] $abc$23348$new_n2173 $abc$23348$new_n2172 +1111 1 +.names ph[1][7] $abc$23348$new_n2174 $abc$23348$new_n2173 +11 1 +.names ph[1][19] ph[1][6] ph[1][5] $abc$23348$new_n2154 $abc$23348$new_n2174 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce ph[1][11] $abc$23348$new_n2172 $abc$23348$new_n2169 ph[2][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20138 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2177 ph[2][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20140 +001 1 +011 1 +110 1 +111 1 +.names ph[1][8] ph[1][10] ph[1][9] $abc$23348$new_n2173 $abc$23348$new_n2170 $abc$23348$new_n2177 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2179 ph[2][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20142 +001 1 +011 1 +110 1 +111 1 +.names ph[1][8] ph[1][9] $abc$23348$new_n2173 $abc$23348$new_n2170 $abc$23348$new_n2179 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[1][8] $abc$23348$new_n2173 $abc$23348$new_n2170 ph[2][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20144 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[1][7] $abc$23348$new_n2174 $abc$23348$new_n2171 ph[2][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20146 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2183 ph[2][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20148 +001 1 +011 1 +110 1 +111 1 +.names ph[1][6] ph[1][5] $abc$23348$new_n2185 $abc$23348$new_n2184 $abc$23348$new_n2183 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$23348$new_n2154 ph[1][19] $abc$23348$new_n2184 +10 1 +.names ph[1][19] $abc$23348$new_n2149 $abc$23348$new_n2185 +11 1 +.names i_ce ph[1][5] $abc$23348$new_n2185 $abc$23348$new_n2184 ph[2][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20150 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2188 ph[1][4] ph[2][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20152 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[1][19] ph[1][2] ph[1][3] ph[1][0] ph[1][1] $abc$23348$new_n2188 +00000 1 +00001 1 +00010 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2190 ph[2][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20154 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] ph[1][3] ph[1][2] ph[1][0] ph[1][1] $abc$23348$new_n2190 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$23348$new_n2192 ph[2][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20156 +001 1 +011 1 +110 1 +111 1 +.names ph[1][2] ph[1][19] ph[1][0] ph[1][1] $abc$23348$new_n2192 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce ph[1][19] ph[1][0] ph[1][1] ph[2][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20158 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[1][0] ph[2][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20160 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[1][15] yv[1][14] $abc$23348$new_n2196 yv[2][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20162 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2197 $abc$23348$new_n2204 $abc$23348$new_n2196 +000 1 +001 1 +101 1 +111 1 +.names xv[1][14] yv[1][12] xv[1][15] yv[1][13] $abc$23348$new_n2198 $abc$23348$new_n2197 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][12] yv[1][10] xv[1][13] yv[1][11] $abc$23348$new_n2199 $abc$23348$new_n2198 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][10] yv[1][8] xv[1][11] yv[1][9] $abc$23348$new_n2200 $abc$23348$new_n2199 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][8] yv[1][6] xv[1][9] yv[1][7] $abc$23348$new_n2201 $abc$23348$new_n2200 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][6] yv[1][4] xv[1][7] yv[1][5] $abc$23348$new_n2202 $abc$23348$new_n2201 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][4] yv[1][2] xv[1][5] yv[1][3] $abc$23348$new_n2203 $abc$23348$new_n2202 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][2] yv[1][0] xv[1][3] yv[1][1] $abc$23348$new_n2203 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[1][14] xv[1][15] yv[1][12] yv[1][13] $abc$23348$new_n2205 $abc$23348$new_n2204 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][12] xv[1][13] yv[1][10] yv[1][11] $abc$23348$new_n2206 $abc$23348$new_n2205 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][10] xv[1][11] yv[1][8] yv[1][9] $abc$23348$new_n2207 $abc$23348$new_n2206 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][8] xv[1][9] yv[1][6] yv[1][7] $abc$23348$new_n2208 $abc$23348$new_n2207 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][6] xv[1][7] yv[1][4] yv[1][5] $abc$23348$new_n2209 $abc$23348$new_n2208 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][4] xv[1][5] yv[1][2] yv[1][3] $abc$23348$new_n2210 $abc$23348$new_n2209 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[1][2] xv[1][3] yv[1][0] yv[1][1] $abc$23348$new_n2210 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce $abc$23348$new_n2216 yv[2][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20166 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] xv[1][14] yv[1][12] $abc$23348$new_n2205 $abc$23348$new_n2198 $abc$23348$new_n2216 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2222 yv[2][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20170 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] xv[1][12] yv[1][10] $abc$23348$new_n2206 $abc$23348$new_n2199 $abc$23348$new_n2222 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[1][11] yv[1][9] $abc$23348$new_n2224 yv[2][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20172 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][10] yv[1][8] $abc$23348$new_n2207 $abc$23348$new_n2200 $abc$23348$new_n2224 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2226 yv[2][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20174 +001 1 +011 1 +100 1 +101 1 +.names ph[1][19] xv[1][10] yv[1][8] $abc$23348$new_n2207 $abc$23348$new_n2200 $abc$23348$new_n2226 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][9] yv[1][7] $abc$23348$new_n2228 yv[2][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20176 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][8] yv[1][6] $abc$23348$new_n2208 $abc$23348$new_n2201 $abc$23348$new_n2228 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][8] yv[1][6] $abc$23348$new_n2230 yv[2][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20178 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2201 $abc$23348$new_n2208 $abc$23348$new_n2230 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][7] yv[1][5] $abc$23348$new_n2232 yv[2][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20180 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][6] yv[1][4] $abc$23348$new_n2209 $abc$23348$new_n2202 $abc$23348$new_n2232 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][6] yv[1][4] $abc$23348$new_n2234 yv[2][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20182 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2202 $abc$23348$new_n2209 $abc$23348$new_n2234 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][5] yv[1][3] $abc$23348$new_n2236 yv[2][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20184 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][4] yv[1][2] $abc$23348$new_n2210 $abc$23348$new_n2203 $abc$23348$new_n2236 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][4] yv[1][2] $abc$23348$new_n2238 yv[2][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20186 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] $abc$23348$new_n2203 $abc$23348$new_n2210 $abc$23348$new_n2238 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2240 yv[2][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20188 +001 1 +011 1 +110 1 +111 1 +.names xv[1][3] yv[1][1] ph[1][19] yv[1][0] xv[1][2] $abc$23348$new_n2240 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[1][2] yv[1][0] yv[2][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20190 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[1][15] xv[1][14] $abc$23348$new_n2243 xv[2][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20192 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] $abc$23348$new_n2244 $abc$23348$new_n2251 $abc$23348$new_n2243 +000 1 +001 1 +101 1 +111 1 +.names yv[1][14] yv[1][15] xv[1][12] xv[1][13] $abc$23348$new_n2245 $abc$23348$new_n2244 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[1][10] xv[1][11] yv[1][12] yv[1][13] $abc$23348$new_n2246 $abc$23348$new_n2245 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[1][10] xv[1][8] xv[1][9] yv[1][11] $abc$23348$new_n2247 $abc$23348$new_n2246 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[1][6] xv[1][7] yv[1][8] yv[1][9] $abc$23348$new_n2248 $abc$23348$new_n2247 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[1][6] xv[1][4] xv[1][5] yv[1][7] $abc$23348$new_n2249 $abc$23348$new_n2248 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][4] xv[1][2] xv[1][3] yv[1][5] $abc$23348$new_n2250 $abc$23348$new_n2249 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][2] xv[1][0] xv[1][1] yv[1][3] $abc$23348$new_n2250 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names xv[1][12] yv[1][14] yv[1][15] xv[1][13] $abc$23348$new_n2252 $abc$23348$new_n2251 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][10] yv[1][12] xv[1][11] yv[1][13] $abc$23348$new_n2253 $abc$23348$new_n2252 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][8] yv[1][10] xv[1][9] yv[1][11] $abc$23348$new_n2254 $abc$23348$new_n2253 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][6] yv[1][8] xv[1][7] yv[1][9] $abc$23348$new_n2255 $abc$23348$new_n2254 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][4] yv[1][6] xv[1][5] yv[1][7] $abc$23348$new_n2256 $abc$23348$new_n2255 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[1][2] yv[1][4] xv[1][3] yv[1][5] $abc$23348$new_n2257 $abc$23348$new_n2256 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][0] yv[1][2] xv[1][1] yv[1][3] $abc$23348$new_n2257 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[1][15] xv[1][13] $abc$23348$new_n2259 xv[2][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20194 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][12] yv[1][14] $abc$23348$new_n2252 $abc$23348$new_n2245 $abc$23348$new_n2259 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2261 xv[2][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20196 +001 1 +011 1 +100 1 +101 1 +.names ph[1][19] xv[1][12] yv[1][14] $abc$23348$new_n2252 $abc$23348$new_n2245 $abc$23348$new_n2261 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[1][11] yv[1][13] $abc$23348$new_n2263 xv[2][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20198 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][10] yv[1][12] $abc$23348$new_n2253 $abc$23348$new_n2246 $abc$23348$new_n2263 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2265 xv[2][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20200 +001 1 +011 1 +100 1 +101 1 +.names ph[1][19] xv[1][10] yv[1][12] $abc$23348$new_n2253 $abc$23348$new_n2246 $abc$23348$new_n2265 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[1][9] yv[1][11] $abc$23348$new_n2267 xv[2][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20202 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][8] yv[1][10] $abc$23348$new_n2254 $abc$23348$new_n2247 $abc$23348$new_n2267 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[1][8] yv[1][10] $abc$23348$new_n2269 xv[2][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20204 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2247 $abc$23348$new_n2254 $abc$23348$new_n2269 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[1][7] yv[1][9] $abc$23348$new_n2271 xv[2][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20206 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][6] yv[1][8] $abc$23348$new_n2255 $abc$23348$new_n2248 $abc$23348$new_n2271 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2273 xv[2][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20208 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] xv[1][6] yv[1][8] $abc$23348$new_n2255 $abc$23348$new_n2248 $abc$23348$new_n2273 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2279 xv[2][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20212 +001 1 +011 1 +100 1 +101 1 +.names ph[1][19] xv[1][4] yv[1][6] $abc$23348$new_n2256 $abc$23348$new_n2249 $abc$23348$new_n2279 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][3] yv[1][5] $abc$23348$new_n2281 xv[2][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20214 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][2] yv[1][4] $abc$23348$new_n2257 $abc$23348$new_n2250 $abc$23348$new_n2281 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[1][2] yv[1][4] $abc$23348$new_n2283 xv[2][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20216 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] $abc$23348$new_n2250 $abc$23348$new_n2257 $abc$23348$new_n2283 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2285 xv[2][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20218 +001 1 +011 1 +110 1 +111 1 +.names xv[1][1] yv[1][3] ph[1][19] xv[1][0] yv[1][2] $abc$23348$new_n2285 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[1][0] yv[1][2] xv[2][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20220 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2288 ph[3][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20222 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] ph[2][18] ph[2][17] $abc$23348$new_n2294 $abc$23348$new_n2289 $abc$23348$new_n2288 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[2][15] ph[2][16] ph[2][14] ph[2][13] $abc$23348$new_n2290 $abc$23348$new_n2289 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[2][12] ph[2][11] $abc$23348$new_n2291 ph[2][10] $abc$23348$new_n2290 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[2][9] ph[2][8] ph[2][7] $abc$23348$new_n2292 ph[2][6] $abc$23348$new_n2291 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[2][5] ph[2][4] ph[2][3] $abc$23348$new_n2293 ph[2][2] $abc$23348$new_n2292 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[2][0] ph[2][1] $abc$23348$new_n2293 +11 1 +.names ph[2][15] ph[2][16] ph[2][14] ph[2][13] $abc$23348$new_n2295 $abc$23348$new_n2294 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names ph[2][12] $abc$23348$new_n2296 ph[2][10] ph[2][11] $abc$23348$new_n2295 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[2][9] ph[2][8] $abc$23348$new_n2297 ph[2][6] ph[2][7] $abc$23348$new_n2296 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names ph[2][5] ph[2][4] $abc$23348$new_n2298 ph[2][2] ph[2][3] $abc$23348$new_n2297 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names ph[2][0] ph[2][1] $abc$23348$new_n2298 +00 1 +.names i_ce $abc$23348$new_n2300 ph[3][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20224 +001 1 +011 1 +100 1 +101 1 +.names ph[2][17] ph[2][19] $abc$23348$new_n2294 $abc$23348$new_n2289 $abc$23348$new_n2300 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$23348$new_n2302 ph[3][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20226 +001 1 +011 1 +110 1 +111 1 +.names ph[2][15] ph[2][16] $abc$23348$new_n2304 $abc$23348$new_n2303 $abc$23348$new_n2302 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[2][19] ph[2][14] ph[2][13] $abc$23348$new_n2295 $abc$23348$new_n2303 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[2][19] ph[2][14] ph[2][13] $abc$23348$new_n2290 $abc$23348$new_n2304 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce ph[2][15] $abc$23348$new_n2304 $abc$23348$new_n2303 ph[3][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20228 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2307 ph[3][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20230 +001 1 +011 1 +110 1 +111 1 +.names ph[2][14] ph[2][19] ph[2][13] $abc$23348$new_n2295 $abc$23348$new_n2290 $abc$23348$new_n2307 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n2309 ph[3][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20232 +001 1 +011 1 +100 1 +101 1 +.names ph[2][13] ph[2][19] $abc$23348$new_n2295 $abc$23348$new_n2290 $abc$23348$new_n2309 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n2311 ph[3][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20234 +001 1 +011 1 +100 1 +101 1 +.names ph[2][10] ph[2][12] ph[2][11] $abc$23348$new_n2314 $abc$23348$new_n2312 $abc$23348$new_n2311 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2313 ph[2][9] $abc$23348$new_n2312 +10 1 +.names ph[2][19] ph[2][8] $abc$23348$new_n2297 ph[2][6] ph[2][7] $abc$23348$new_n2313 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names ph[2][9] $abc$23348$new_n2315 $abc$23348$new_n2314 +11 1 +.names ph[2][19] ph[2][8] ph[2][7] $abc$23348$new_n2292 ph[2][6] $abc$23348$new_n2315 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2317 ph[3][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20236 +001 1 +011 1 +110 1 +111 1 +.names ph[2][10] ph[2][11] $abc$23348$new_n2314 $abc$23348$new_n2312 $abc$23348$new_n2317 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[2][10] $abc$23348$new_n2314 $abc$23348$new_n2312 ph[3][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20238 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[2][9] $abc$23348$new_n2315 $abc$23348$new_n2313 ph[3][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20240 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2321 ph[3][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20242 +001 1 +011 1 +100 1 +101 1 +.names ph[2][6] ph[2][8] ph[2][7] $abc$23348$new_n2324 $abc$23348$new_n2322 $abc$23348$new_n2321 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2323 ph[2][5] $abc$23348$new_n2322 +10 1 +.names ph[2][19] ph[2][4] $abc$23348$new_n2298 ph[2][2] ph[2][3] $abc$23348$new_n2323 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names ph[2][5] $abc$23348$new_n2325 $abc$23348$new_n2324 +11 1 +.names ph[2][19] ph[2][4] ph[2][3] $abc$23348$new_n2293 ph[2][2] $abc$23348$new_n2325 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2327 ph[3][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20244 +001 1 +011 1 +110 1 +111 1 +.names ph[2][6] ph[2][7] $abc$23348$new_n2324 $abc$23348$new_n2322 $abc$23348$new_n2327 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[2][6] $abc$23348$new_n2324 $abc$23348$new_n2322 ph[3][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20246 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[2][5] $abc$23348$new_n2325 $abc$23348$new_n2323 ph[3][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20248 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[2][4] $abc$23348$new_n2331 ph[3][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20250 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[2][19] ph[2][0] ph[2][1] ph[2][2] ph[2][3] $abc$23348$new_n2331 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n2333 ph[3][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20252 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] ph[2][3] ph[2][0] ph[2][1] ph[2][2] $abc$23348$new_n2333 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n2335 ph[3][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20254 +001 1 +011 1 +100 1 +101 1 +.names ph[2][2] ph[2][19] ph[2][0] ph[2][1] $abc$23348$new_n2335 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[2][19] ph[2][0] ph[2][1] ph[3][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20256 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[2][0] ph[3][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20258 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[2][15] yv[2][14] $abc$23348$new_n2339 yv[3][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20260 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] $abc$23348$new_n2340 $abc$23348$new_n2347 $abc$23348$new_n2339 +000 1 +001 1 +101 1 +111 1 +.names xv[2][15] $abc$23348$new_n2341 yv[2][12] yv[2][13] $abc$23348$new_n2340 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[2][13] yv[2][10] xv[2][14] yv[2][11] $abc$23348$new_n2342 $abc$23348$new_n2341 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][11] yv[2][8] xv[2][12] yv[2][9] $abc$23348$new_n2343 $abc$23348$new_n2342 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][9] yv[2][6] xv[2][10] yv[2][7] $abc$23348$new_n2344 $abc$23348$new_n2343 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][7] yv[2][4] xv[2][8] yv[2][5] $abc$23348$new_n2345 $abc$23348$new_n2344 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[2][5] yv[2][2] xv[2][6] yv[2][3] $abc$23348$new_n2346 $abc$23348$new_n2345 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][3] yv[2][0] xv[2][4] yv[2][1] $abc$23348$new_n2346 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[2][15] $abc$23348$new_n2348 yv[2][12] yv[2][13] $abc$23348$new_n2347 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[2][13] xv[2][14] yv[2][10] yv[2][11] $abc$23348$new_n2349 $abc$23348$new_n2348 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][11] xv[2][12] yv[2][8] yv[2][9] $abc$23348$new_n2350 $abc$23348$new_n2349 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][9] xv[2][10] yv[2][6] yv[2][7] $abc$23348$new_n2351 $abc$23348$new_n2350 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][7] xv[2][8] yv[2][4] yv[2][5] $abc$23348$new_n2352 $abc$23348$new_n2351 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][5] xv[2][6] yv[2][2] yv[2][3] $abc$23348$new_n2353 $abc$23348$new_n2352 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[2][3] xv[2][4] yv[2][0] yv[2][1] $abc$23348$new_n2353 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce $abc$23348$new_n2359 yv[3][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20264 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] xv[2][15] yv[2][12] $abc$23348$new_n2348 $abc$23348$new_n2341 $abc$23348$new_n2359 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][14] yv[2][11] $abc$23348$new_n2361 yv[3][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20266 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] yv[2][10] xv[2][13] $abc$23348$new_n2349 $abc$23348$new_n2342 $abc$23348$new_n2361 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][13] yv[2][10] $abc$23348$new_n2363 yv[3][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20268 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] $abc$23348$new_n2342 $abc$23348$new_n2349 $abc$23348$new_n2363 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][12] yv[2][9] $abc$23348$new_n2365 yv[3][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20270 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][11] yv[2][8] $abc$23348$new_n2350 $abc$23348$new_n2343 $abc$23348$new_n2365 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2367 yv[3][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20272 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] xv[2][11] yv[2][8] $abc$23348$new_n2350 $abc$23348$new_n2343 $abc$23348$new_n2367 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][10] yv[2][7] $abc$23348$new_n2369 yv[3][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20274 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][9] yv[2][6] $abc$23348$new_n2351 $abc$23348$new_n2344 $abc$23348$new_n2369 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][9] yv[2][6] $abc$23348$new_n2371 yv[3][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20276 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] $abc$23348$new_n2344 $abc$23348$new_n2351 $abc$23348$new_n2371 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][8] yv[2][5] $abc$23348$new_n2373 yv[3][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20278 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][7] yv[2][4] $abc$23348$new_n2352 $abc$23348$new_n2345 $abc$23348$new_n2373 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][7] yv[2][4] $abc$23348$new_n2375 yv[3][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20280 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] $abc$23348$new_n2345 $abc$23348$new_n2352 $abc$23348$new_n2375 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[2][6] yv[2][3] $abc$23348$new_n2377 yv[3][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20282 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] yv[2][2] xv[2][5] $abc$23348$new_n2353 $abc$23348$new_n2346 $abc$23348$new_n2377 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][5] yv[2][2] $abc$23348$new_n2379 yv[3][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20284 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] $abc$23348$new_n2346 $abc$23348$new_n2353 $abc$23348$new_n2379 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2381 yv[3][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20286 +001 1 +011 1 +110 1 +111 1 +.names xv[2][4] yv[2][1] ph[2][19] yv[2][0] xv[2][3] $abc$23348$new_n2381 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[2][3] yv[2][0] yv[3][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20288 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[2][15] xv[2][14] $abc$23348$new_n2384 xv[3][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20290 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] $abc$23348$new_n2385 $abc$23348$new_n2392 $abc$23348$new_n2384 +000 1 +001 1 +101 1 +111 1 +.names yv[2][15] xv[2][12] xv[2][13] $abc$23348$new_n2386 $abc$23348$new_n2385 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[2][10] xv[2][11] yv[2][13] yv[2][14] $abc$23348$new_n2387 $abc$23348$new_n2386 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[2][11] xv[2][8] xv[2][9] yv[2][12] $abc$23348$new_n2388 $abc$23348$new_n2387 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[2][6] xv[2][7] yv[2][9] yv[2][10] $abc$23348$new_n2389 $abc$23348$new_n2388 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[2][7] xv[2][4] xv[2][5] yv[2][8] $abc$23348$new_n2390 $abc$23348$new_n2389 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][5] xv[2][2] xv[2][3] yv[2][6] $abc$23348$new_n2391 $abc$23348$new_n2390 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][3] xv[2][0] xv[2][1] yv[2][4] $abc$23348$new_n2391 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[2][15] $abc$23348$new_n2393 xv[2][12] xv[2][13] $abc$23348$new_n2392 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[2][10] yv[2][13] xv[2][11] yv[2][14] $abc$23348$new_n2394 $abc$23348$new_n2393 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][8] yv[2][11] xv[2][9] yv[2][12] $abc$23348$new_n2395 $abc$23348$new_n2394 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][6] yv[2][9] xv[2][7] yv[2][10] $abc$23348$new_n2396 $abc$23348$new_n2395 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][4] yv[2][7] xv[2][5] yv[2][8] $abc$23348$new_n2397 $abc$23348$new_n2396 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[2][2] yv[2][5] xv[2][3] yv[2][6] $abc$23348$new_n2398 $abc$23348$new_n2397 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][0] yv[2][3] xv[2][1] yv[2][4] $abc$23348$new_n2398 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[2][15] xv[2][13] $abc$23348$new_n2400 xv[3][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20292 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] yv[2][15] xv[2][12] $abc$23348$new_n2393 $abc$23348$new_n2386 $abc$23348$new_n2400 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2402 xv[3][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20294 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] yv[2][15] xv[2][12] $abc$23348$new_n2393 $abc$23348$new_n2386 $abc$23348$new_n2402 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][11] yv[2][14] $abc$23348$new_n2404 xv[3][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20296 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] xv[2][10] yv[2][13] $abc$23348$new_n2394 $abc$23348$new_n2387 $abc$23348$new_n2404 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2406 xv[3][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20298 +001 1 +011 1 +100 1 +101 1 +.names ph[2][19] xv[2][10] yv[2][13] $abc$23348$new_n2394 $abc$23348$new_n2387 $abc$23348$new_n2406 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2412 xv[3][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20302 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] xv[2][8] yv[2][11] $abc$23348$new_n2395 $abc$23348$new_n2388 $abc$23348$new_n2412 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][7] yv[2][10] $abc$23348$new_n2414 xv[3][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20304 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] xv[2][6] yv[2][9] $abc$23348$new_n2396 $abc$23348$new_n2389 $abc$23348$new_n2414 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2416 xv[3][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20306 +001 1 +011 1 +100 1 +101 1 +.names ph[2][19] xv[2][6] yv[2][9] $abc$23348$new_n2396 $abc$23348$new_n2389 $abc$23348$new_n2416 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2422 xv[3][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20310 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] xv[2][4] yv[2][7] $abc$23348$new_n2397 $abc$23348$new_n2390 $abc$23348$new_n2422 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][3] yv[2][6] $abc$23348$new_n2424 xv[3][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20312 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] xv[2][2] yv[2][5] $abc$23348$new_n2398 $abc$23348$new_n2391 $abc$23348$new_n2424 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[2][2] yv[2][5] $abc$23348$new_n2426 xv[3][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20314 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] $abc$23348$new_n2391 $abc$23348$new_n2398 $abc$23348$new_n2426 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2428 xv[3][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20316 +001 1 +011 1 +110 1 +111 1 +.names xv[2][1] yv[2][4] ph[2][19] xv[2][0] yv[2][3] $abc$23348$new_n2428 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[2][0] yv[2][3] xv[3][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20318 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[3][18] $abc$23348$new_n2435 $abc$23348$new_n2431 ph[4][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20320 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[3][19] $abc$23348$new_n2440 ph[3][17] $abc$23348$new_n2431 +100 1 +101 1 +110 1 +.names ph[3][11] ph[3][10] $abc$23348$new_n2434 ph[3][9] $abc$23348$new_n2433 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[3][8] ph[3][6] ph[3][7] ph[3][5] ph[3][4] $abc$23348$new_n2434 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[3][19] $abc$23348$new_n2440 ph[3][17] $abc$23348$new_n2435 +001 1 +010 1 +011 1 +.names ph[3][11] $abc$23348$new_n2438 ph[3][9] ph[3][10] $abc$23348$new_n2437 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[3][8] ph[3][6] ph[3][7] ph[3][5] ph[3][4] $abc$23348$new_n2438 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names i_ce $abc$23348$new_n2440 ph[4][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20322 +001 1 +011 1 +100 1 +101 1 +.names ph[3][17] ph[3][15] ph[3][16] $abc$23348$new_n2442 $abc$23348$new_n2441 $abc$23348$new_n2440 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names ph[3][19] ph[3][14] ph[3][13] ph[3][12] $abc$23348$new_n2437 $abc$23348$new_n2441 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names ph[3][19] ph[3][14] ph[3][13] ph[3][12] $abc$23348$new_n2433 $abc$23348$new_n2442 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2444 ph[4][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20324 +001 1 +011 1 +100 1 +101 1 +.names ph[3][15] ph[3][16] $abc$23348$new_n2442 $abc$23348$new_n2441 $abc$23348$new_n2444 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[3][15] $abc$23348$new_n2442 $abc$23348$new_n2441 ph[4][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20326 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2447 ph[3][14] ph[4][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20328 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[3][19] ph[3][13] ph[3][12] $abc$23348$new_n2433 $abc$23348$new_n2437 $abc$23348$new_n2447 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names i_ce $abc$23348$new_n2449 ph[4][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20330 +001 1 +011 1 +110 1 +111 1 +.names ph[3][13] ph[3][19] ph[3][12] $abc$23348$new_n2437 $abc$23348$new_n2433 $abc$23348$new_n2449 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n2451 ph[4][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20332 +001 1 +011 1 +110 1 +111 1 +.names ph[3][12] ph[3][19] $abc$23348$new_n2437 $abc$23348$new_n2433 $abc$23348$new_n2451 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[3][11] $abc$23348$new_n2453 ph[4][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20334 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[3][19] ph[3][9] ph[3][10] $abc$23348$new_n2434 $abc$23348$new_n2438 $abc$23348$new_n2453 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2455 ph[4][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20336 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] ph[3][10] ph[3][9] $abc$23348$new_n2438 $abc$23348$new_n2434 $abc$23348$new_n2455 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n2457 ph[4][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20338 +001 1 +011 1 +110 1 +111 1 +.names ph[3][9] ph[3][19] $abc$23348$new_n2438 $abc$23348$new_n2434 $abc$23348$new_n2457 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n2459 ph[3][8] ph[4][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20340 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[3][19] ph[3][7] ph[3][4] ph[3][5] ph[3][6] $abc$23348$new_n2459 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +.names i_ce $abc$23348$new_n2461 ph[4][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20342 +001 1 +011 1 +110 1 +111 1 +.names ph[3][7] ph[3][19] ph[3][6] ph[3][4] ph[3][5] $abc$23348$new_n2461 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +10000 1 +10001 1 +10010 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2463 ph[4][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20344 +001 1 +011 1 +110 1 +111 1 +.names ph[3][6] ph[3][19] ph[3][4] ph[3][5] $abc$23348$new_n2463 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce ph[3][19] ph[3][4] ph[3][5] ph[4][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20346 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[3][4] ph[4][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20348 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[3][3] ph[4][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20350 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[3][2] ph[4][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20352 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[3][1] ph[4][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20354 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[3][0] ph[4][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20356 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[3][15] yv[3][14] $abc$23348$new_n2471 yv[4][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20358 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] $abc$23348$new_n2472 $abc$23348$new_n2479 $abc$23348$new_n2471 +000 1 +001 1 +101 1 +111 1 +.names xv[3][15] $abc$23348$new_n2473 yv[3][11] yv[3][12] yv[3][13] $abc$23348$new_n2472 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[3][13] yv[3][9] xv[3][14] yv[3][10] $abc$23348$new_n2474 $abc$23348$new_n2473 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][11] yv[3][7] xv[3][12] yv[3][8] $abc$23348$new_n2475 $abc$23348$new_n2474 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][9] yv[3][5] xv[3][10] yv[3][6] $abc$23348$new_n2476 $abc$23348$new_n2475 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][7] yv[3][3] xv[3][8] yv[3][4] $abc$23348$new_n2477 $abc$23348$new_n2476 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][6] yv[3][2] $abc$23348$new_n2478 $abc$23348$new_n2477 +000 1 +001 1 +011 1 +101 1 +.names xv[3][4] yv[3][0] xv[3][5] yv[3][1] $abc$23348$new_n2478 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[3][15] $abc$23348$new_n2480 yv[3][12] yv[3][13] $abc$23348$new_n2479 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[3][14] xv[3][15] yv[3][10] yv[3][11] $abc$23348$new_n2481 $abc$23348$new_n2480 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][12] xv[3][13] yv[3][8] yv[3][9] $abc$23348$new_n2482 $abc$23348$new_n2481 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][10] xv[3][11] yv[3][6] yv[3][7] $abc$23348$new_n2483 $abc$23348$new_n2482 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][8] xv[3][9] yv[3][4] yv[3][5] $abc$23348$new_n2484 $abc$23348$new_n2483 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][6] xv[3][7] yv[3][2] yv[3][3] $abc$23348$new_n2485 $abc$23348$new_n2484 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[3][4] xv[3][5] yv[3][0] yv[3][1] $abc$23348$new_n2485 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names xv[3][15] $abc$23348$new_n2473 yv[3][11] yv[3][12] $abc$23348$new_n2489 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[3][15] yv[3][12] $abc$23348$new_n2491 yv[4][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20362 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][15] yv[3][11] $abc$23348$new_n2492 $abc$23348$new_n2473 $abc$23348$new_n2491 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[3][14] yv[3][10] $abc$23348$new_n2481 $abc$23348$new_n2492 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2494 yv[4][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20364 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] xv[3][15] yv[3][11] $abc$23348$new_n2492 $abc$23348$new_n2473 $abc$23348$new_n2494 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[3][14] yv[3][10] $abc$23348$new_n2496 yv[4][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20366 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][13] yv[3][9] $abc$23348$new_n2474 $abc$23348$new_n2481 $abc$23348$new_n2496 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[3][13] yv[3][9] $abc$23348$new_n2498 yv[4][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20368 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][12] yv[3][8] $abc$23348$new_n2482 $abc$23348$new_n2474 $abc$23348$new_n2498 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][12] yv[3][8] $abc$23348$new_n2500 yv[4][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20370 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][11] yv[3][7] $abc$23348$new_n2475 $abc$23348$new_n2482 $abc$23348$new_n2500 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[3][11] yv[3][7] $abc$23348$new_n2502 yv[4][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20372 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][10] yv[3][6] $abc$23348$new_n2483 $abc$23348$new_n2475 $abc$23348$new_n2502 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][10] yv[3][6] $abc$23348$new_n2504 yv[4][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20374 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][9] yv[3][5] $abc$23348$new_n2476 $abc$23348$new_n2483 $abc$23348$new_n2504 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[3][9] yv[3][5] $abc$23348$new_n2506 yv[4][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20376 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][8] yv[3][4] $abc$23348$new_n2484 $abc$23348$new_n2476 $abc$23348$new_n2506 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][8] yv[3][4] $abc$23348$new_n2508 yv[4][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20378 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][7] yv[3][3] $abc$23348$new_n2477 $abc$23348$new_n2484 $abc$23348$new_n2508 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[3][7] yv[3][3] $abc$23348$new_n2510 yv[4][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20380 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][6] yv[3][2] $abc$23348$new_n2485 $abc$23348$new_n2478 $abc$23348$new_n2510 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][6] yv[3][2] $abc$23348$new_n2512 yv[4][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20382 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] $abc$23348$new_n2478 $abc$23348$new_n2485 $abc$23348$new_n2512 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2514 yv[4][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20384 +001 1 +011 1 +110 1 +111 1 +.names xv[3][5] yv[3][1] ph[3][19] yv[3][0] xv[3][4] $abc$23348$new_n2514 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[3][4] yv[3][0] yv[4][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20386 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[3][15] xv[3][14] $abc$23348$new_n2517 xv[4][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20388 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] $abc$23348$new_n2518 $abc$23348$new_n2525 $abc$23348$new_n2517 +000 1 +001 1 +101 1 +111 1 +.names yv[3][15] xv[3][12] xv[3][13] $abc$23348$new_n2519 $abc$23348$new_n2518 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[3][10] yv[3][14] yv[3][15] xv[3][11] $abc$23348$new_n2520 $abc$23348$new_n2519 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[3][12] xv[3][8] xv[3][9] yv[3][13] $abc$23348$new_n2521 $abc$23348$new_n2520 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[3][6] xv[3][7] yv[3][10] yv[3][11] $abc$23348$new_n2522 $abc$23348$new_n2521 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[3][8] xv[3][4] xv[3][5] yv[3][9] $abc$23348$new_n2523 $abc$23348$new_n2522 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][6] xv[3][2] xv[3][3] yv[3][7] $abc$23348$new_n2524 $abc$23348$new_n2523 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][4] xv[3][0] xv[3][1] yv[3][5] $abc$23348$new_n2524 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[3][15] $abc$23348$new_n2526 xv[3][12] xv[3][13] $abc$23348$new_n2525 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[3][10] yv[3][14] yv[3][15] xv[3][11] $abc$23348$new_n2527 $abc$23348$new_n2526 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][8] yv[3][12] xv[3][9] yv[3][13] $abc$23348$new_n2528 $abc$23348$new_n2527 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][6] yv[3][10] xv[3][7] yv[3][11] $abc$23348$new_n2529 $abc$23348$new_n2528 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][4] yv[3][8] xv[3][5] yv[3][9] $abc$23348$new_n2530 $abc$23348$new_n2529 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][2] yv[3][6] xv[3][3] yv[3][7] $abc$23348$new_n2531 $abc$23348$new_n2530 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][0] yv[3][4] xv[3][1] yv[3][5] $abc$23348$new_n2531 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[3][15] xv[3][13] $abc$23348$new_n2533 xv[4][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20390 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] yv[3][15] xv[3][12] $abc$23348$new_n2526 $abc$23348$new_n2519 $abc$23348$new_n2533 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2535 xv[4][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20392 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] yv[3][15] xv[3][12] $abc$23348$new_n2526 $abc$23348$new_n2519 $abc$23348$new_n2535 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[3][15] xv[3][11] $abc$23348$new_n2537 xv[4][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20394 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][10] yv[3][14] $abc$23348$new_n2527 $abc$23348$new_n2520 $abc$23348$new_n2537 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2539 xv[4][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20396 +001 1 +011 1 +100 1 +101 1 +.names ph[3][19] xv[3][10] yv[3][14] $abc$23348$new_n2527 $abc$23348$new_n2520 $abc$23348$new_n2539 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[3][9] yv[3][13] $abc$23348$new_n2541 xv[4][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20398 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][8] yv[3][12] $abc$23348$new_n2528 $abc$23348$new_n2521 $abc$23348$new_n2541 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2543 xv[4][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20400 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] xv[3][8] yv[3][12] $abc$23348$new_n2528 $abc$23348$new_n2521 $abc$23348$new_n2543 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][7] yv[3][11] $abc$23348$new_n2545 xv[4][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20402 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][6] yv[3][10] $abc$23348$new_n2529 $abc$23348$new_n2522 $abc$23348$new_n2545 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[3][6] yv[3][10] $abc$23348$new_n2547 xv[4][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20404 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] $abc$23348$new_n2522 $abc$23348$new_n2529 $abc$23348$new_n2547 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[3][5] yv[3][9] $abc$23348$new_n2549 xv[4][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20406 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][4] yv[3][8] $abc$23348$new_n2530 $abc$23348$new_n2523 $abc$23348$new_n2549 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2551 xv[4][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20408 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] xv[3][4] yv[3][8] $abc$23348$new_n2530 $abc$23348$new_n2523 $abc$23348$new_n2551 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][3] yv[3][7] $abc$23348$new_n2553 xv[4][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20410 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][2] yv[3][6] $abc$23348$new_n2531 $abc$23348$new_n2524 $abc$23348$new_n2553 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[3][2] yv[3][6] $abc$23348$new_n2555 xv[4][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20412 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] $abc$23348$new_n2524 $abc$23348$new_n2531 $abc$23348$new_n2555 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2557 xv[4][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20414 +001 1 +011 1 +110 1 +111 1 +.names xv[3][1] yv[3][5] ph[3][19] xv[3][0] yv[3][4] $abc$23348$new_n2557 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[3][0] yv[3][4] xv[4][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20416 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[4][18] $abc$23348$new_n2567 $abc$23348$new_n2560 ph[5][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20418 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[4][19] ph[4][16] ph[4][17] $abc$23348$new_n2561 ph[4][15] $abc$23348$new_n2560 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names ph[4][14] ph[4][13] $abc$23348$new_n2562 ph[4][12] $abc$23348$new_n2561 +1101 1 +1110 1 +1111 1 +.names ph[4][11] $abc$23348$new_n2563 $abc$23348$new_n2562 +10 1 +.names ph[4][10] ph[4][8] ph[4][9] ph[4][7] $abc$23348$new_n2564 $abc$23348$new_n2563 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[4][6] ph[4][5] $abc$23348$new_n2565 ph[4][4] $abc$23348$new_n2564 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$23348$new_n2566 ph[4][3] $abc$23348$new_n2565 +10 1 +.names ph[4][2] ph[4][1] ph[4][0] $abc$23348$new_n2566 +000 1 +001 1 +010 1 +.names ph[4][19] $abc$23348$new_n2568 ph[4][16] ph[4][17] ph[4][15] $abc$23348$new_n2567 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names ph[4][14] ph[4][13] $abc$23348$new_n2569 ph[4][12] $abc$23348$new_n2568 +0000 1 +0010 1 +0011 1 +.names ph[4][11] $abc$23348$new_n2570 $abc$23348$new_n2569 +00 1 +.names ph[4][10] ph[4][9] $abc$23348$new_n2571 ph[4][7] ph[4][8] $abc$23348$new_n2570 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[4][6] ph[4][5] ph[4][4] $abc$23348$new_n2572 $abc$23348$new_n2571 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[4][3] $abc$23348$new_n2573 $abc$23348$new_n2572 +11 1 +.names ph[4][2] ph[4][1] ph[4][0] $abc$23348$new_n2573 +101 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n2575 ph[5][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20420 +001 1 +011 1 +110 1 +111 1 +.names ph[4][15] ph[4][17] ph[4][16] $abc$23348$new_n2577 $abc$23348$new_n2576 $abc$23348$new_n2575 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[4][19] $abc$23348$new_n2561 $abc$23348$new_n2576 +11 1 +.names $abc$23348$new_n2568 ph[4][19] $abc$23348$new_n2577 +10 1 +.names i_ce $abc$23348$new_n2579 ph[5][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20422 +001 1 +011 1 +110 1 +111 1 +.names ph[4][16] ph[4][15] $abc$23348$new_n2577 $abc$23348$new_n2576 $abc$23348$new_n2579 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[4][15] $abc$23348$new_n2577 $abc$23348$new_n2576 ph[5][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20424 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[4][14] $abc$23348$new_n2582 ph[5][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20426 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[4][19] ph[4][13] ph[4][12] $abc$23348$new_n2562 $abc$23348$new_n2569 $abc$23348$new_n2582 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2584 ph[5][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20428 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] ph[4][13] ph[4][12] $abc$23348$new_n2569 $abc$23348$new_n2562 $abc$23348$new_n2584 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2586 ph[5][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20430 +001 1 +011 1 +110 1 +111 1 +.names ph[4][12] ph[4][11] $abc$23348$new_n2588 $abc$23348$new_n2587 $abc$23348$new_n2586 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names ph[4][19] $abc$23348$new_n2563 $abc$23348$new_n2587 +10 1 +.names ph[4][19] $abc$23348$new_n2570 $abc$23348$new_n2588 +00 1 +.names i_ce ph[4][11] $abc$23348$new_n2588 $abc$23348$new_n2587 ph[5][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20432 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2591 ph[5][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20434 +001 1 +011 1 +100 1 +101 1 +.names ph[4][8] ph[4][10] ph[4][9] $abc$23348$new_n2594 $abc$23348$new_n2592 $abc$23348$new_n2591 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[4][7] $abc$23348$new_n2593 $abc$23348$new_n2592 +11 1 +.names ph[4][19] $abc$23348$new_n2564 $abc$23348$new_n2593 +10 1 +.names $abc$23348$new_n2595 ph[4][7] $abc$23348$new_n2594 +10 1 +.names ph[4][19] $abc$23348$new_n2571 $abc$23348$new_n2595 +00 1 +.names i_ce $abc$23348$new_n2597 ph[5][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20436 +001 1 +011 1 +110 1 +111 1 +.names ph[4][9] ph[4][8] $abc$23348$new_n2594 $abc$23348$new_n2592 $abc$23348$new_n2597 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[4][8] $abc$23348$new_n2594 $abc$23348$new_n2592 ph[5][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20438 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[4][7] $abc$23348$new_n2595 $abc$23348$new_n2593 ph[5][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20440 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2601 ph[4][6] ph[5][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20442 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[4][19] ph[4][5] ph[4][4] $abc$23348$new_n2565 $abc$23348$new_n2572 $abc$23348$new_n2601 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce ph[4][5] $abc$23348$new_n2603 ph[5][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20444 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[4][3] ph[4][4] ph[4][19] $abc$23348$new_n2566 $abc$23348$new_n2573 $abc$23348$new_n2603 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2605 ph[4][4] ph[5][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20446 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[4][3] ph[4][19] $abc$23348$new_n2566 $abc$23348$new_n2573 $abc$23348$new_n2605 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n2607 ph[5][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20448 +001 1 +011 1 +110 1 +111 1 +.names ph[4][3] ph[4][19] $abc$23348$new_n2573 $abc$23348$new_n2566 $abc$23348$new_n2607 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n2609 ph[5][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20450 +001 1 +011 1 +110 1 +111 1 +.names ph[4][2] ph[4][19] ph[4][0] ph[4][1] $abc$23348$new_n2609 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[4][19] ph[4][0] ph[4][1] ph[5][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20452 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[4][0] ph[5][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20454 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[4][15] yv[4][14] $abc$23348$new_n2613 yv[5][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20456 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] $abc$23348$new_n2614 $abc$23348$new_n2621 $abc$23348$new_n2613 +000 1 +001 1 +101 1 +111 1 +.names xv[4][15] $abc$23348$new_n2615 yv[4][12] yv[4][13] $abc$23348$new_n2614 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[4][15] $abc$23348$new_n2616 yv[4][10] yv[4][11] $abc$23348$new_n2615 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[4][13] yv[4][8] xv[4][14] yv[4][9] $abc$23348$new_n2617 $abc$23348$new_n2616 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][11] yv[4][6] xv[4][12] yv[4][7] $abc$23348$new_n2618 $abc$23348$new_n2617 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][9] yv[4][4] xv[4][10] yv[4][5] $abc$23348$new_n2619 $abc$23348$new_n2618 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[4][7] yv[4][2] xv[4][8] yv[4][3] $abc$23348$new_n2620 $abc$23348$new_n2619 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[4][5] yv[4][0] xv[4][6] yv[4][1] $abc$23348$new_n2620 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[4][15] yv[4][13] $abc$23348$new_n2622 $abc$23348$new_n2621 +001 1 +100 1 +101 1 +111 1 +.names xv[4][15] $abc$23348$new_n2623 yv[4][10] yv[4][11] yv[4][12] $abc$23348$new_n2622 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[4][13] xv[4][14] yv[4][8] yv[4][9] $abc$23348$new_n2624 $abc$23348$new_n2623 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][11] xv[4][12] yv[4][6] yv[4][7] $abc$23348$new_n2625 $abc$23348$new_n2624 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][9] xv[4][10] yv[4][4] yv[4][5] $abc$23348$new_n2626 $abc$23348$new_n2625 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][7] xv[4][8] yv[4][2] yv[4][3] $abc$23348$new_n2627 $abc$23348$new_n2626 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[4][5] xv[4][6] yv[4][0] yv[4][1] $abc$23348$new_n2627 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[4][15] yv[4][13] $abc$23348$new_n2629 yv[5][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20458 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2622 $abc$23348$new_n2615 ph[4][19] yv[4][12] $abc$23348$new_n2629 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[4][15] yv[4][10] $abc$23348$new_n2623 $abc$23348$new_n2633 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2638 yv[5][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20464 +001 1 +011 1 +110 1 +111 1 +.names ph[4][19] xv[4][15] yv[4][10] $abc$23348$new_n2623 $abc$23348$new_n2616 $abc$23348$new_n2638 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][14] yv[4][9] $abc$23348$new_n2640 yv[5][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20466 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][13] yv[4][8] $abc$23348$new_n2624 $abc$23348$new_n2617 $abc$23348$new_n2640 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2642 yv[5][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20468 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] xv[4][13] yv[4][8] $abc$23348$new_n2624 $abc$23348$new_n2617 $abc$23348$new_n2642 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][12] yv[4][7] $abc$23348$new_n2644 yv[5][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20470 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][11] yv[4][6] $abc$23348$new_n2625 $abc$23348$new_n2618 $abc$23348$new_n2644 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[4][11] yv[4][6] $abc$23348$new_n2646 yv[5][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20472 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] $abc$23348$new_n2618 $abc$23348$new_n2625 $abc$23348$new_n2646 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[4][10] yv[4][5] $abc$23348$new_n2648 yv[5][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20474 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][9] yv[4][4] $abc$23348$new_n2626 $abc$23348$new_n2619 $abc$23348$new_n2648 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2650 yv[5][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20476 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] xv[4][9] yv[4][4] $abc$23348$new_n2626 $abc$23348$new_n2619 $abc$23348$new_n2650 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][8] yv[4][3] $abc$23348$new_n2652 yv[5][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20478 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][7] yv[4][2] $abc$23348$new_n2627 $abc$23348$new_n2620 $abc$23348$new_n2652 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][7] yv[4][2] $abc$23348$new_n2654 yv[5][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20480 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] $abc$23348$new_n2620 $abc$23348$new_n2627 $abc$23348$new_n2654 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2656 yv[5][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20482 +001 1 +011 1 +110 1 +111 1 +.names xv[4][6] yv[4][1] ph[4][19] yv[4][0] xv[4][5] $abc$23348$new_n2656 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[4][5] yv[4][0] yv[5][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20484 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[4][15] xv[4][14] $abc$23348$new_n2659 xv[5][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20486 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] $abc$23348$new_n2660 $abc$23348$new_n2667 $abc$23348$new_n2659 +000 1 +001 1 +101 1 +111 1 +.names yv[4][15] $abc$23348$new_n2661 xv[4][12] xv[4][13] $abc$23348$new_n2660 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[4][15] $abc$23348$new_n2662 xv[4][10] xv[4][11] $abc$23348$new_n2661 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[4][13] xv[4][8] xv[4][9] yv[4][14] $abc$23348$new_n2663 $abc$23348$new_n2662 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[4][6] xv[4][7] yv[4][11] yv[4][12] $abc$23348$new_n2664 $abc$23348$new_n2663 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[4][9] xv[4][4] xv[4][5] yv[4][10] $abc$23348$new_n2665 $abc$23348$new_n2664 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][7] xv[4][2] xv[4][3] yv[4][8] $abc$23348$new_n2666 $abc$23348$new_n2665 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][5] xv[4][0] xv[4][1] yv[4][6] $abc$23348$new_n2666 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[4][15] xv[4][13] $abc$23348$new_n2668 $abc$23348$new_n2667 +000 1 +001 1 +011 1 +101 1 +.names yv[4][15] $abc$23348$new_n2669 xv[4][10] xv[4][11] xv[4][12] $abc$23348$new_n2668 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[4][8] yv[4][13] xv[4][9] yv[4][14] $abc$23348$new_n2670 $abc$23348$new_n2669 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][6] yv[4][11] xv[4][7] yv[4][12] $abc$23348$new_n2671 $abc$23348$new_n2670 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][4] yv[4][9] xv[4][5] yv[4][10] $abc$23348$new_n2672 $abc$23348$new_n2671 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][2] yv[4][7] xv[4][3] yv[4][8] $abc$23348$new_n2673 $abc$23348$new_n2672 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][0] yv[4][5] xv[4][1] yv[4][6] $abc$23348$new_n2673 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[4][15] xv[4][13] $abc$23348$new_n2675 xv[5][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20488 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] yv[4][15] xv[4][12] $abc$23348$new_n2676 $abc$23348$new_n2661 $abc$23348$new_n2675 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[4][15] $abc$23348$new_n2669 xv[4][10] xv[4][11] $abc$23348$new_n2676 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n2678 xv[5][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20490 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] yv[4][15] xv[4][12] $abc$23348$new_n2676 $abc$23348$new_n2661 $abc$23348$new_n2678 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[4][15] xv[4][11] $abc$23348$new_n2680 xv[5][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20492 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][10] yv[4][15] $abc$23348$new_n2669 $abc$23348$new_n2662 $abc$23348$new_n2680 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2682 xv[5][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20494 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] yv[4][15] xv[4][10] $abc$23348$new_n2669 $abc$23348$new_n2662 $abc$23348$new_n2682 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][9] yv[4][14] $abc$23348$new_n2684 xv[5][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20496 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][8] yv[4][13] $abc$23348$new_n2670 $abc$23348$new_n2663 $abc$23348$new_n2684 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2686 xv[5][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20498 +001 1 +011 1 +110 1 +111 1 +.names ph[4][19] xv[4][8] yv[4][13] $abc$23348$new_n2670 $abc$23348$new_n2663 $abc$23348$new_n2686 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][7] yv[4][12] $abc$23348$new_n2688 xv[5][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20500 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][6] yv[4][11] $abc$23348$new_n2671 $abc$23348$new_n2664 $abc$23348$new_n2688 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2690 xv[5][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20502 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] xv[4][6] yv[4][11] $abc$23348$new_n2671 $abc$23348$new_n2664 $abc$23348$new_n2690 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][5] yv[4][10] $abc$23348$new_n2692 xv[5][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20504 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][4] yv[4][9] $abc$23348$new_n2672 $abc$23348$new_n2665 $abc$23348$new_n2692 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2694 xv[5][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20506 +001 1 +011 1 +110 1 +111 1 +.names ph[4][19] xv[4][4] yv[4][9] $abc$23348$new_n2672 $abc$23348$new_n2665 $abc$23348$new_n2694 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][3] yv[4][8] $abc$23348$new_n2696 xv[5][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20508 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][2] yv[4][7] $abc$23348$new_n2673 $abc$23348$new_n2666 $abc$23348$new_n2696 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[4][2] yv[4][7] $abc$23348$new_n2698 xv[5][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20510 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] $abc$23348$new_n2666 $abc$23348$new_n2673 $abc$23348$new_n2698 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2700 xv[5][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20512 +001 1 +011 1 +110 1 +111 1 +.names xv[4][1] yv[4][6] ph[4][19] xv[4][0] yv[4][5] $abc$23348$new_n2700 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[4][0] yv[4][5] xv[5][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20514 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2703 ph[6][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20516 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][18] ph[5][17] $abc$23348$new_n2711 $abc$23348$new_n2704 $abc$23348$new_n2703 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[5][16] $abc$23348$new_n2705 $abc$23348$new_n2704 +11 1 +.names ph[5][15] $abc$23348$new_n2706 $abc$23348$new_n2705 +11 1 +.names ph[5][14] ph[5][12] ph[5][13] $abc$23348$new_n2707 ph[5][11] $abc$23348$new_n2706 +11101 1 +11110 1 +11111 1 +.names ph[5][10] ph[5][9] ph[5][8] $abc$23348$new_n2708 $abc$23348$new_n2707 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[5][7] $abc$23348$new_n2709 $abc$23348$new_n2708 +11 1 +.names ph[5][6] $abc$23348$new_n2710 ph[5][5] $abc$23348$new_n2709 +101 1 +110 1 +111 1 +.names ph[5][4] ph[5][2] ph[5][3] ph[5][0] ph[5][1] $abc$23348$new_n2710 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n2712 ph[5][15] ph[5][16] $abc$23348$new_n2711 +100 1 +.names ph[5][14] ph[5][12] ph[5][13] $abc$23348$new_n2713 ph[5][11] $abc$23348$new_n2712 +00000 1 +00010 1 +00011 1 +.names ph[5][10] ph[5][9] $abc$23348$new_n2714 ph[5][8] $abc$23348$new_n2713 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$23348$new_n2715 ph[5][7] $abc$23348$new_n2714 +10 1 +.names ph[5][6] $abc$23348$new_n2716 ph[5][5] $abc$23348$new_n2715 +000 1 +010 1 +011 1 +.names ph[5][4] ph[5][2] ph[5][3] ph[5][0] ph[5][1] $abc$23348$new_n2716 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_ce $abc$23348$new_n2718 ph[6][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20518 +001 1 +011 1 +100 1 +101 1 +.names ph[5][17] ph[5][19] $abc$23348$new_n2711 $abc$23348$new_n2704 $abc$23348$new_n2718 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$23348$new_n2720 ph[6][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20520 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][16] ph[5][15] $abc$23348$new_n2706 $abc$23348$new_n2712 $abc$23348$new_n2720 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2722 ph[6][15] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$20522 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[5][19] ph[5][15] $abc$23348$new_n2706 $abc$23348$new_n2712 $abc$23348$new_n2722 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2724 ph[6][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20524 +001 1 +011 1 +110 1 +111 1 +.names ph[5][12] ph[5][14] ph[5][13] $abc$23348$new_n2726 $abc$23348$new_n2725 $abc$23348$new_n2724 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] $abc$23348$new_n2713 ph[5][11] $abc$23348$new_n2725 +000 1 +010 1 +011 1 +.names ph[5][19] $abc$23348$new_n2707 ph[5][11] $abc$23348$new_n2726 +101 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n2728 ph[6][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20526 +001 1 +011 1 +110 1 +111 1 +.names ph[5][12] ph[5][13] $abc$23348$new_n2726 $abc$23348$new_n2725 $abc$23348$new_n2728 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[5][12] $abc$23348$new_n2726 $abc$23348$new_n2725 ph[6][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20528 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2731 ph[6][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20530 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][11] $abc$23348$new_n2707 $abc$23348$new_n2713 $abc$23348$new_n2731 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[5][10] $abc$23348$new_n2733 ph[6][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20532 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[5][19] ph[5][8] ph[5][9] $abc$23348$new_n2714 $abc$23348$new_n2708 $abc$23348$new_n2733 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2735 ph[6][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20534 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] ph[5][9] ph[5][8] $abc$23348$new_n2708 $abc$23348$new_n2714 $abc$23348$new_n2735 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2737 ph[6][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20536 +001 1 +011 1 +100 1 +101 1 +.names ph[5][8] ph[5][19] ph[5][7] $abc$23348$new_n2709 $abc$23348$new_n2715 $abc$23348$new_n2737 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2739 ph[6][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20538 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][7] $abc$23348$new_n2709 $abc$23348$new_n2715 $abc$23348$new_n2739 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2741 ph[6][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20540 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] ph[5][6] ph[5][5] $abc$23348$new_n2710 $abc$23348$new_n2716 $abc$23348$new_n2741 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2743 ph[6][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20542 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][5] $abc$23348$new_n2710 $abc$23348$new_n2716 $abc$23348$new_n2743 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[5][4] $abc$23348$new_n2745 ph[6][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20544 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[5][19] ph[5][0] ph[5][1] ph[5][2] ph[5][3] $abc$23348$new_n2745 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2747 ph[6][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20546 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][3] ph[5][0] ph[5][1] ph[5][2] $abc$23348$new_n2747 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2749 ph[6][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20548 +001 1 +011 1 +100 1 +101 1 +.names ph[5][2] ph[5][19] ph[5][0] ph[5][1] $abc$23348$new_n2749 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce ph[5][19] ph[5][0] ph[5][1] ph[6][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20550 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[5][0] ph[6][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20552 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[5][15] yv[5][14] $abc$23348$new_n2753 yv[6][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20554 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] $abc$23348$new_n2754 $abc$23348$new_n2761 $abc$23348$new_n2753 +000 1 +001 1 +101 1 +111 1 +.names xv[5][15] $abc$23348$new_n2755 yv[5][12] yv[5][13] $abc$23348$new_n2754 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[5][15] $abc$23348$new_n2756 yv[5][9] yv[5][10] yv[5][11] $abc$23348$new_n2755 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[5][13] yv[5][7] xv[5][14] yv[5][8] $abc$23348$new_n2757 $abc$23348$new_n2756 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][11] yv[5][5] xv[5][12] yv[5][6] $abc$23348$new_n2758 $abc$23348$new_n2757 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][9] yv[5][3] xv[5][10] yv[5][4] $abc$23348$new_n2759 $abc$23348$new_n2758 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][8] yv[5][2] $abc$23348$new_n2760 $abc$23348$new_n2759 +000 1 +001 1 +011 1 +101 1 +.names xv[5][6] yv[5][0] xv[5][7] yv[5][1] $abc$23348$new_n2760 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[5][15] yv[5][13] $abc$23348$new_n2762 $abc$23348$new_n2761 +001 1 +100 1 +101 1 +111 1 +.names xv[5][15] $abc$23348$new_n2763 yv[5][10] yv[5][11] yv[5][12] $abc$23348$new_n2762 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][14] xv[5][15] yv[5][8] yv[5][9] $abc$23348$new_n2764 $abc$23348$new_n2763 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][12] xv[5][13] yv[5][6] yv[5][7] $abc$23348$new_n2765 $abc$23348$new_n2764 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][10] xv[5][11] yv[5][4] yv[5][5] $abc$23348$new_n2766 $abc$23348$new_n2765 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][8] xv[5][9] yv[5][2] yv[5][3] $abc$23348$new_n2767 $abc$23348$new_n2766 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[5][6] xv[5][7] yv[5][0] yv[5][1] $abc$23348$new_n2767 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[5][15] yv[5][13] $abc$23348$new_n2769 yv[6][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20556 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 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1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names xv[5][15] $abc$23348$new_n2756 yv[5][9] yv[5][10] $abc$23348$new_n2775 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[5][15] yv[5][10] $abc$23348$new_n2777 yv[6][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20562 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][15] yv[5][9] $abc$23348$new_n2756 $abc$23348$new_n2763 $abc$23348$new_n2777 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][15] yv[5][9] $abc$23348$new_n2779 yv[6][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20564 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][14] yv[5][8] $abc$23348$new_n2764 $abc$23348$new_n2756 $abc$23348$new_n2779 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][14] yv[5][8] $abc$23348$new_n2781 yv[6][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20566 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][13] yv[5][7] $abc$23348$new_n2757 $abc$23348$new_n2764 $abc$23348$new_n2781 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][13] yv[5][7] $abc$23348$new_n2783 yv[6][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20568 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][12] yv[5][6] $abc$23348$new_n2765 $abc$23348$new_n2757 $abc$23348$new_n2783 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][12] yv[5][6] $abc$23348$new_n2785 yv[6][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20570 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][11] yv[5][5] $abc$23348$new_n2758 $abc$23348$new_n2765 $abc$23348$new_n2785 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][11] yv[5][5] $abc$23348$new_n2787 yv[6][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20572 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][10] yv[5][4] $abc$23348$new_n2766 $abc$23348$new_n2758 $abc$23348$new_n2787 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][10] yv[5][4] $abc$23348$new_n2789 yv[6][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20574 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][9] yv[5][3] $abc$23348$new_n2759 $abc$23348$new_n2766 $abc$23348$new_n2789 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][9] yv[5][3] $abc$23348$new_n2791 yv[6][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20576 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] yv[5][2] xv[5][8] $abc$23348$new_n2767 $abc$23348$new_n2760 $abc$23348$new_n2791 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][8] yv[5][2] $abc$23348$new_n2793 yv[6][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20578 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] $abc$23348$new_n2760 $abc$23348$new_n2767 $abc$23348$new_n2793 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[5][7] yv[5][1] $abc$23348$new_n2795 yv[6][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20580 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[5][6] ph[5][19] yv[5][0] $abc$23348$new_n2795 +101 1 +110 1 +.names i_ce xv[5][6] yv[5][0] yv[6][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20582 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[5][15] xv[5][14] $abc$23348$new_n2798 xv[6][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20584 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] $abc$23348$new_n2799 $abc$23348$new_n2806 $abc$23348$new_n2798 +000 1 +001 1 +101 1 +111 1 +.names yv[5][15] $abc$23348$new_n2800 xv[5][12] xv[5][13] $abc$23348$new_n2799 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[5][15] $abc$23348$new_n2801 xv[5][9] xv[5][10] xv[5][11] $abc$23348$new_n2800 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[5][14] xv[5][8] $abc$23348$new_n2802 $abc$23348$new_n2801 +000 1 +100 1 +101 1 +110 1 +.names xv[5][6] xv[5][7] yv[5][12] yv[5][13] $abc$23348$new_n2803 $abc$23348$new_n2802 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[5][10] xv[5][4] xv[5][5] yv[5][11] $abc$23348$new_n2804 $abc$23348$new_n2803 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][8] xv[5][2] xv[5][3] yv[5][9] $abc$23348$new_n2805 $abc$23348$new_n2804 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][6] xv[5][0] xv[5][1] yv[5][7] $abc$23348$new_n2805 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[5][15] $abc$23348$new_n2807 xv[5][12] xv[5][13] $abc$23348$new_n2806 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[5][15] $abc$23348$new_n2808 xv[5][9] xv[5][10] xv[5][11] $abc$23348$new_n2807 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[5][8] yv[5][14] $abc$23348$new_n2809 $abc$23348$new_n2808 +000 1 +001 1 +011 1 +101 1 +.names xv[5][6] yv[5][12] xv[5][7] yv[5][13] $abc$23348$new_n2810 $abc$23348$new_n2809 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][4] yv[5][10] xv[5][5] yv[5][11] $abc$23348$new_n2811 $abc$23348$new_n2810 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[5][2] yv[5][8] xv[5][3] yv[5][9] $abc$23348$new_n2812 $abc$23348$new_n2811 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][0] yv[5][6] xv[5][1] yv[5][7] $abc$23348$new_n2812 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[5][15] xv[5][13] $abc$23348$new_n2814 xv[6][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20586 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] yv[5][15] xv[5][12] $abc$23348$new_n2807 $abc$23348$new_n2800 $abc$23348$new_n2814 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2816 xv[6][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20588 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] yv[5][15] xv[5][12] $abc$23348$new_n2807 $abc$23348$new_n2800 $abc$23348$new_n2816 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[5][15] xv[5][11] $abc$23348$new_n2818 xv[6][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20590 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][10] yv[5][15] $abc$23348$new_n2820 $abc$23348$new_n2819 $abc$23348$new_n2818 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names yv[5][15] xv[5][9] $abc$23348$new_n2801 $abc$23348$new_n2819 +001 1 +100 1 +101 1 +111 1 +.names yv[5][15] xv[5][9] $abc$23348$new_n2808 $abc$23348$new_n2820 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n2822 xv[6][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20592 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] yv[5][15] xv[5][10] $abc$23348$new_n2820 $abc$23348$new_n2819 $abc$23348$new_n2822 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2824 xv[6][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20594 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] yv[5][15] xv[5][9] $abc$23348$new_n2808 $abc$23348$new_n2801 $abc$23348$new_n2824 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2826 xv[6][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20596 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] xv[5][8] yv[5][14] $abc$23348$new_n2809 $abc$23348$new_n2802 $abc$23348$new_n2826 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][7] yv[5][13] $abc$23348$new_n2828 xv[6][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20598 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][6] yv[5][12] $abc$23348$new_n2810 $abc$23348$new_n2803 $abc$23348$new_n2828 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2830 xv[6][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20600 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] xv[5][6] yv[5][12] $abc$23348$new_n2810 $abc$23348$new_n2803 $abc$23348$new_n2830 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[5][5] yv[5][11] $abc$23348$new_n2832 xv[6][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20602 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][4] yv[5][10] $abc$23348$new_n2811 $abc$23348$new_n2804 $abc$23348$new_n2832 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2834 xv[6][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20604 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] xv[5][4] yv[5][10] $abc$23348$new_n2811 $abc$23348$new_n2804 $abc$23348$new_n2834 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[5][3] yv[5][9] $abc$23348$new_n2836 xv[6][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20606 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][2] yv[5][8] $abc$23348$new_n2812 $abc$23348$new_n2805 $abc$23348$new_n2836 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[5][2] yv[5][8] $abc$23348$new_n2838 xv[6][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20608 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] $abc$23348$new_n2805 $abc$23348$new_n2812 $abc$23348$new_n2838 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2840 xv[6][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20610 +001 1 +011 1 +110 1 +111 1 +.names xv[5][1] yv[5][7] ph[5][19] xv[5][0] yv[5][6] $abc$23348$new_n2840 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[5][0] yv[5][6] xv[6][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20612 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][18] $abc$23348$new_n2843 ph[7][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20614 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$23348$new_n2844 ph[6][19] ph[6][17] $abc$23348$new_n2850 ph[6][16] $abc$23348$new_n2843 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01111 1 +.names $abc$23348$new_n2845 ph[6][19] ph[6][16] ph[6][17] $abc$23348$new_n2844 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[6][19] $abc$23348$new_n2846 ph[6][14] ph[6][15] ph[6][13] $abc$23348$new_n2845 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names ph[6][12] ph[6][11] $abc$23348$new_n2847 ph[6][10] $abc$23348$new_n2846 +0000 1 +0010 1 +0011 1 +.names ph[6][9] $abc$23348$new_n2848 $abc$23348$new_n2847 +00 1 +.names ph[6][8] ph[6][7] $abc$23348$new_n2849 ph[6][5] ph[6][6] $abc$23348$new_n2848 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[6][4] ph[6][3] ph[6][1] ph[6][2] ph[6][0] $abc$23348$new_n2849 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[6][14] ph[6][15] $abc$23348$new_n2851 $abc$23348$new_n2850 +111 1 +.names ph[6][13] $abc$23348$new_n2852 $abc$23348$new_n2851 +11 1 +.names ph[6][12] ph[6][11] $abc$23348$new_n2853 ph[6][10] $abc$23348$new_n2852 +1101 1 +1110 1 +1111 1 +.names ph[6][9] $abc$23348$new_n2854 $abc$23348$new_n2853 +10 1 +.names ph[6][8] ph[6][6] ph[6][7] ph[6][5] $abc$23348$new_n2855 $abc$23348$new_n2854 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[6][4] ph[6][3] ph[6][1] ph[6][2] ph[6][0] $abc$23348$new_n2855 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names i_ce $abc$23348$new_n2857 ph[7][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20616 +001 1 +011 1 +110 1 +111 1 +.names ph[6][17] ph[6][19] ph[6][16] $abc$23348$new_n2845 $abc$23348$new_n2850 $abc$23348$new_n2857 +00000 1 +00001 1 +01101 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2859 ph[7][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20618 +001 1 +011 1 +110 1 +111 1 +.names ph[6][16] $abc$23348$new_n2845 ph[6][19] $abc$23348$new_n2850 $abc$23348$new_n2859 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n2864 ph[7][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20622 +001 1 +011 1 +100 1 +101 1 +.names ph[6][14] ph[6][19] ph[6][13] $abc$23348$new_n2852 $abc$23348$new_n2846 $abc$23348$new_n2864 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names $abc$23348$new_n2866 ph[7][13] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$20624 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[6][19] ph[6][13] $abc$23348$new_n2852 $abc$23348$new_n2846 $abc$23348$new_n2866 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2868 ph[6][12] ph[7][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20626 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[6][19] ph[6][10] ph[6][11] $abc$23348$new_n2847 $abc$23348$new_n2853 $abc$23348$new_n2868 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2870 ph[7][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20628 +001 1 +011 1 +110 1 +111 1 +.names ph[6][11] ph[6][19] ph[6][10] $abc$23348$new_n2853 $abc$23348$new_n2847 $abc$23348$new_n2870 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2872 ph[7][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20630 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] ph[6][10] $abc$23348$new_n2853 $abc$23348$new_n2847 $abc$23348$new_n2872 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2874 ph[7][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20632 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] ph[6][9] $abc$23348$new_n2854 $abc$23348$new_n2848 $abc$23348$new_n2874 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n2876 ph[7][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20634 +001 1 +011 1 +100 1 +101 1 +.names ph[6][6] ph[6][8] ph[6][7] $abc$23348$new_n2878 $abc$23348$new_n2877 $abc$23348$new_n2876 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] ph[6][5] $abc$23348$new_n2849 $abc$23348$new_n2877 +000 1 +.names ph[6][19] ph[6][5] $abc$23348$new_n2855 $abc$23348$new_n2878 +110 1 +.names i_ce $abc$23348$new_n2880 ph[7][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20636 +001 1 +011 1 +110 1 +111 1 +.names ph[6][6] ph[6][7] $abc$23348$new_n2878 $abc$23348$new_n2877 $abc$23348$new_n2880 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][6] $abc$23348$new_n2878 $abc$23348$new_n2877 ph[7][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20638 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2883 ph[7][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20640 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] ph[6][5] $abc$23348$new_n2855 $abc$23348$new_n2849 $abc$23348$new_n2883 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][4] $abc$23348$new_n2885 ph[7][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20642 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[6][19] ph[6][0] ph[6][1] ph[6][2] ph[6][3] $abc$23348$new_n2885 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n2887 ph[7][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20644 +001 1 +011 1 +110 1 +111 1 +.names ph[6][3] ph[6][19] ph[6][0] ph[6][1] ph[6][2] $abc$23348$new_n2887 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +.names i_ce $abc$23348$new_n2889 ph[7][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20646 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] ph[6][2] ph[6][0] ph[6][1] $abc$23348$new_n2889 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names i_ce ph[6][19] ph[6][0] ph[6][1] ph[7][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20648 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[6][0] ph[7][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20650 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[6][15] yv[6][14] $abc$23348$new_n2893 yv[7][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20652 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] $abc$23348$new_n2894 $abc$23348$new_n2906 $abc$23348$new_n2893 +000 1 +001 1 +101 1 +111 1 +.names xv[6][15] $abc$23348$new_n2895 yv[6][12] yv[6][13] $abc$23348$new_n2894 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[6][9] $abc$23348$new_n2903 $abc$23348$new_n2905 $abc$23348$new_n2896 $abc$23348$new_n2904 $abc$23348$new_n2895 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names xv[6][14] yv[6][7] $abc$23348$new_n2897 $abc$23348$new_n2896 +000 1 +001 1 +011 1 +101 1 +.names xv[6][12] yv[6][5] xv[6][13] yv[6][6] $abc$23348$new_n2898 $abc$23348$new_n2897 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][10] yv[6][3] xv[6][11] yv[6][4] $abc$23348$new_n2899 $abc$23348$new_n2898 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][9] yv[6][2] $abc$23348$new_n2900 $abc$23348$new_n2899 +000 1 +001 1 +011 1 +101 1 +.names xv[6][7] yv[6][0] xv[6][8] yv[6][1] $abc$23348$new_n2900 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[6][8] yv[6][9] $abc$23348$new_n2902 +00 1 +.names xv[6][15] yv[6][9] $abc$23348$new_n2903 +00 1 +11 1 +.names xv[6][15] yv[6][8] $abc$23348$new_n2904 +00 1 +11 1 +.names xv[6][15] yv[6][10] yv[6][11] $abc$23348$new_n2905 +011 1 +100 1 +.names xv[6][15] $abc$23348$new_n2907 yv[6][12] yv[6][13] $abc$23348$new_n2906 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][15] yv[6][10] yv[6][11] $abc$23348$new_n2908 $abc$23348$new_n2902 $abc$23348$new_n2907 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2904 $abc$23348$new_n2903 $abc$23348$new_n2909 $abc$23348$new_n2908 +110 1 +.names xv[6][13] xv[6][14] yv[6][6] yv[6][7] $abc$23348$new_n2910 $abc$23348$new_n2909 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][11] xv[6][12] yv[6][4] yv[6][5] $abc$23348$new_n2911 $abc$23348$new_n2910 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][9] xv[6][10] yv[6][2] yv[6][3] $abc$23348$new_n2912 $abc$23348$new_n2911 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[6][7] xv[6][8] yv[6][0] yv[6][1] $abc$23348$new_n2912 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[6][15] yv[6][13] $abc$23348$new_n2914 yv[7][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20654 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][15] yv[6][12] $abc$23348$new_n2907 $abc$23348$new_n2895 $abc$23348$new_n2914 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2916 yv[7][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20656 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] xv[6][15] yv[6][12] $abc$23348$new_n2907 $abc$23348$new_n2895 $abc$23348$new_n2916 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[6][15] yv[6][11] $abc$23348$new_n2918 yv[7][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20658 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][10] ph[6][19] $abc$23348$new_n2919 xv[6][15] $abc$23348$new_n2920 $abc$23348$new_n2918 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names ph[6][19] $abc$23348$new_n2908 xv[6][15] $abc$23348$new_n2902 $abc$23348$new_n2919 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][15] $abc$23348$new_n2896 yv[6][8] yv[6][9] $abc$23348$new_n2920 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n2922 yv[7][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20660 +001 1 +011 1 +110 1 +111 1 +.names xv[6][15] yv[6][10] $abc$23348$new_n2919 $abc$23348$new_n2920 ph[6][19] $abc$23348$new_n2922 +00000 1 +00001 1 +00011 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2903 $abc$23348$new_n2924 yv[7][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20662 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[6][19] yv[6][8] xv[6][15] $abc$23348$new_n2909 $abc$23348$new_n2896 $abc$23348$new_n2924 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2926 yv[7][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20664 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] $abc$23348$new_n2904 $abc$23348$new_n2909 $abc$23348$new_n2896 $abc$23348$new_n2926 +0000 1 +0010 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[6][14] yv[6][7] $abc$23348$new_n2928 yv[7][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20666 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][13] yv[6][6] $abc$23348$new_n2910 $abc$23348$new_n2897 $abc$23348$new_n2928 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][13] yv[6][6] $abc$23348$new_n2930 yv[7][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20668 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][12] yv[6][5] $abc$23348$new_n2898 $abc$23348$new_n2910 $abc$23348$new_n2930 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][12] yv[6][5] $abc$23348$new_n2932 yv[7][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20670 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][11] yv[6][4] $abc$23348$new_n2911 $abc$23348$new_n2898 $abc$23348$new_n2932 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][11] yv[6][4] $abc$23348$new_n2934 yv[7][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20672 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][10] yv[6][3] $abc$23348$new_n2899 $abc$23348$new_n2911 $abc$23348$new_n2934 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][10] yv[6][3] $abc$23348$new_n2936 yv[7][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20674 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] yv[6][2] xv[6][9] $abc$23348$new_n2912 $abc$23348$new_n2900 $abc$23348$new_n2936 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][9] yv[6][2] $abc$23348$new_n2938 yv[7][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20676 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] $abc$23348$new_n2900 $abc$23348$new_n2912 $abc$23348$new_n2938 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[6][8] yv[6][1] $abc$23348$new_n2940 yv[7][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20678 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[6][7] ph[6][19] yv[6][0] $abc$23348$new_n2940 +101 1 +110 1 +.names i_ce xv[6][7] yv[6][0] yv[7][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20680 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[6][15] xv[6][14] $abc$23348$new_n2943 xv[7][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20682 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] $abc$23348$new_n2944 $abc$23348$new_n2955 $abc$23348$new_n2943 +000 1 +001 1 +101 1 +111 1 +.names yv[6][15] $abc$23348$new_n2945 xv[6][12] xv[6][13] $abc$23348$new_n2944 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][9] $abc$23348$new_n2952 $abc$23348$new_n2954 $abc$23348$new_n2946 $abc$23348$new_n2953 $abc$23348$new_n2945 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names xv[6][6] xv[6][7] yv[6][13] yv[6][14] $abc$23348$new_n2947 $abc$23348$new_n2946 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[6][12] xv[6][5] $abc$23348$new_n2948 $abc$23348$new_n2947 +001 1 +100 1 +101 1 +111 1 +.names yv[6][10] xv[6][3] xv[6][4] yv[6][11] $abc$23348$new_n2949 $abc$23348$new_n2948 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[6][9] xv[6][2] $abc$23348$new_n2950 $abc$23348$new_n2949 +001 1 +100 1 +101 1 +111 1 +.names yv[6][7] xv[6][0] xv[6][1] yv[6][8] $abc$23348$new_n2950 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[6][15] xv[6][9] $abc$23348$new_n2952 +01 1 +10 1 +.names yv[6][15] xv[6][8] $abc$23348$new_n2953 +01 1 +10 1 +.names yv[6][15] xv[6][10] xv[6][11] $abc$23348$new_n2954 +000 1 +111 1 +.names yv[6][15] $abc$23348$new_n2956 xv[6][12] xv[6][13] $abc$23348$new_n2955 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[6][8] $abc$23348$new_n2953 $abc$23348$new_n2963 $abc$23348$new_n2952 $abc$23348$new_n2957 $abc$23348$new_n2956 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][7] yv[6][14] $abc$23348$new_n2958 $abc$23348$new_n2957 +000 1 +001 1 +011 1 +101 1 +.names xv[6][5] yv[6][12] xv[6][6] yv[6][13] $abc$23348$new_n2959 $abc$23348$new_n2958 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][3] yv[6][10] xv[6][4] yv[6][11] $abc$23348$new_n2960 $abc$23348$new_n2959 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][2] yv[6][9] $abc$23348$new_n2961 $abc$23348$new_n2960 +000 1 +001 1 +011 1 +101 1 +.names xv[6][0] yv[6][7] xv[6][1] yv[6][8] $abc$23348$new_n2961 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[6][15] xv[6][10] xv[6][11] $abc$23348$new_n2963 +011 1 +100 1 +.names i_ce yv[6][15] xv[6][13] $abc$23348$new_n2965 xv[7][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20684 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] xv[6][12] yv[6][15] $abc$23348$new_n2956 $abc$23348$new_n2945 $abc$23348$new_n2965 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2967 xv[7][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20686 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] yv[6][15] xv[6][12] $abc$23348$new_n2956 $abc$23348$new_n2945 $abc$23348$new_n2967 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[6][15] xv[6][11] $abc$23348$new_n2969 xv[7][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20688 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] xv[6][10] yv[6][15] $abc$23348$new_n2971 $abc$23348$new_n2970 $abc$23348$new_n2969 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names yv[6][15] $abc$23348$new_n2957 xv[6][8] xv[6][9] $abc$23348$new_n2970 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[6][15] xv[6][8] xv[6][9] $abc$23348$new_n2946 $abc$23348$new_n2971 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$23348$new_n2973 xv[7][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20690 +001 1 +011 1 +100 1 +101 1 +.names yv[6][15] xv[6][10] ph[6][19] $abc$23348$new_n2971 $abc$23348$new_n2970 $abc$23348$new_n2973 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n2975 $abc$23348$new_n2952 xv[7][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20692 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[6][19] xv[6][8] yv[6][15] $abc$23348$new_n2957 $abc$23348$new_n2946 $abc$23348$new_n2975 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2977 xv[7][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20694 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] $abc$23348$new_n2953 $abc$23348$new_n2957 $abc$23348$new_n2946 $abc$23348$new_n2977 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[6][7] yv[6][14] $abc$23348$new_n2979 xv[7][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20696 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] xv[6][6] yv[6][13] $abc$23348$new_n2947 $abc$23348$new_n2958 $abc$23348$new_n2979 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][6] yv[6][13] $abc$23348$new_n2981 xv[7][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20698 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] yv[6][12] xv[6][5] $abc$23348$new_n2959 $abc$23348$new_n2948 $abc$23348$new_n2981 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2983 xv[7][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20700 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] xv[6][5] yv[6][12] $abc$23348$new_n2959 $abc$23348$new_n2948 $abc$23348$new_n2983 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[6][4] yv[6][11] $abc$23348$new_n2985 xv[7][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20702 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] yv[6][10] xv[6][3] $abc$23348$new_n2960 $abc$23348$new_n2949 $abc$23348$new_n2985 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2987 xv[7][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20704 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] xv[6][3] yv[6][10] $abc$23348$new_n2960 $abc$23348$new_n2949 $abc$23348$new_n2987 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[6][2] yv[6][9] $abc$23348$new_n2989 xv[7][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20706 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] $abc$23348$new_n2950 $abc$23348$new_n2961 $abc$23348$new_n2989 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[6][1] yv[6][8] $abc$23348$new_n2991 xv[7][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20708 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][7] ph[6][19] xv[6][0] $abc$23348$new_n2991 +100 1 +111 1 +.names i_ce xv[6][0] yv[6][7] xv[7][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20710 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2994 ph[8][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20712 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] ph[7][18] ph[7][17] $abc$23348$new_n3001 $abc$23348$new_n2995 $abc$23348$new_n2994 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2996 ph[7][14] ph[7][15] ph[7][16] $abc$23348$new_n2995 +1000 1 +.names $abc$23348$new_n2997 ph[7][13] $abc$23348$new_n2996 +10 1 +.names ph[7][10] ph[7][11] ph[7][12] $abc$23348$new_n2998 $abc$23348$new_n2997 +0000 1 +.names ph[7][9] ph[7][8] ph[7][7] $abc$23348$new_n2999 $abc$23348$new_n2998 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[7][4] ph[7][5] ph[7][6] $abc$23348$new_n3000 $abc$23348$new_n2999 +0000 1 +.names ph[7][3] ph[7][2] ph[7][0] ph[7][1] $abc$23348$new_n3000 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[7][14] ph[7][15] ph[7][16] $abc$23348$new_n3002 $abc$23348$new_n3001 +1111 1 +.names ph[7][11] ph[7][12] ph[7][13] $abc$23348$new_n3003 $abc$23348$new_n3002 +1111 1 +.names ph[7][10] ph[7][8] ph[7][9] $abc$23348$new_n3004 ph[7][7] $abc$23348$new_n3003 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[7][5] ph[7][6] $abc$23348$new_n3005 $abc$23348$new_n3004 +111 1 +.names ph[7][4] ph[7][2] ph[7][3] ph[7][1] ph[7][0] $abc$23348$new_n3005 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3007 ph[8][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20714 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] ph[7][17] $abc$23348$new_n3001 $abc$23348$new_n2995 $abc$23348$new_n3007 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[7][16] $abc$23348$new_n3009 ph[8][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20716 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[7][19] ph[7][14] ph[7][15] $abc$23348$new_n2996 $abc$23348$new_n3002 $abc$23348$new_n3009 +00010 1 +00011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n3014 ph[8][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20720 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] ph[7][14] $abc$23348$new_n3002 $abc$23348$new_n2996 $abc$23348$new_n3014 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3019 ph[8][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20724 +001 1 +011 1 +110 1 +111 1 +.names ph[7][11] ph[7][12] $abc$23348$new_n3022 $abc$23348$new_n3020 $abc$23348$new_n3019 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$23348$new_n3021 ph[7][10] $abc$23348$new_n3020 +10 1 +.names ph[7][19] $abc$23348$new_n2998 $abc$23348$new_n3021 +00 1 +.names ph[7][10] $abc$23348$new_n3023 $abc$23348$new_n3022 +11 1 +.names ph[7][19] ph[7][8] ph[7][9] $abc$23348$new_n3004 ph[7][7] $abc$23348$new_n3023 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce ph[7][11] $abc$23348$new_n3022 $abc$23348$new_n3020 ph[8][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20726 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[7][10] $abc$23348$new_n3023 $abc$23348$new_n3021 ph[8][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20728 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3027 ph[8][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20730 +001 1 +011 1 +110 1 +111 1 +.names ph[7][9] ph[7][8] $abc$23348$new_n3029 $abc$23348$new_n3028 $abc$23348$new_n3027 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names ph[7][19] $abc$23348$new_n3004 ph[7][7] $abc$23348$new_n3028 +101 1 +110 1 +111 1 +.names ph[7][19] $abc$23348$new_n2999 ph[7][7] $abc$23348$new_n3029 +000 1 +010 1 +011 1 +.names i_ce ph[7][8] $abc$23348$new_n3029 $abc$23348$new_n3028 ph[8][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20732 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3032 ph[8][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20734 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] ph[7][7] $abc$23348$new_n3004 $abc$23348$new_n2999 $abc$23348$new_n3032 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3034 ph[7][6] ph[8][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20736 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[7][19] ph[7][5] $abc$23348$new_n3005 ph[7][4] $abc$23348$new_n3000 $abc$23348$new_n3034 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3036 ph[8][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20738 +001 1 +011 1 +110 1 +111 1 +.names ph[7][5] ph[7][19] ph[7][4] $abc$23348$new_n3000 $abc$23348$new_n3005 $abc$23348$new_n3036 +00000 1 +00001 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3038 ph[7][4] ph[8][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20740 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[7][19] ph[7][3] ph[7][0] ph[7][1] ph[7][2] $abc$23348$new_n3038 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +.names i_ce $abc$23348$new_n3040 ph[8][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20742 +001 1 +011 1 +110 1 +111 1 +.names ph[7][3] ph[7][19] ph[7][2] ph[7][0] ph[7][1] $abc$23348$new_n3040 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +10000 1 +10001 1 +10010 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3042 ph[8][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20744 +001 1 +011 1 +110 1 +111 1 +.names ph[7][2] ph[7][19] ph[7][0] ph[7][1] $abc$23348$new_n3042 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce ph[7][19] ph[7][0] ph[7][1] ph[8][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20746 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[7][0] ph[8][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20748 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[7][15] yv[7][14] $abc$23348$new_n3046 yv[8][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20750 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] $abc$23348$new_n3047 $abc$23348$new_n3055 $abc$23348$new_n3046 +000 1 +001 1 +101 1 +111 1 +.names xv[7][15] $abc$23348$new_n3048 yv[7][12] yv[7][13] $abc$23348$new_n3047 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[7][15] yv[7][10] yv[7][11] $abc$23348$new_n3049 $abc$23348$new_n3054 $abc$23348$new_n3048 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[7][8] yv[7][9] xv[7][15] yv[7][7] $abc$23348$new_n3050 $abc$23348$new_n3049 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[7][13] yv[7][5] xv[7][14] yv[7][6] $abc$23348$new_n3051 $abc$23348$new_n3050 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][11] yv[7][3] xv[7][12] yv[7][4] $abc$23348$new_n3052 $abc$23348$new_n3051 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][10] yv[7][2] $abc$23348$new_n3053 $abc$23348$new_n3052 +000 1 +001 1 +011 1 +101 1 +.names xv[7][8] yv[7][0] xv[7][9] yv[7][1] $abc$23348$new_n3053 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[7][8] yv[7][9] $abc$23348$new_n3054 +00 1 +.names xv[7][15] $abc$23348$new_n3056 yv[7][12] yv[7][13] $abc$23348$new_n3055 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[7][15] yv[7][10] yv[7][11] $abc$23348$new_n3057 $abc$23348$new_n3054 $abc$23348$new_n3056 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[7][15] yv[7][8] yv[7][9] $abc$23348$new_n3058 $abc$23348$new_n3057 +0000 1 +1110 1 +.names xv[7][14] xv[7][15] yv[7][6] yv[7][7] $abc$23348$new_n3059 $abc$23348$new_n3058 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][12] xv[7][13] yv[7][4] yv[7][5] $abc$23348$new_n3060 $abc$23348$new_n3059 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][10] xv[7][11] yv[7][2] yv[7][3] $abc$23348$new_n3061 $abc$23348$new_n3060 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[7][8] xv[7][9] yv[7][0] yv[7][1] $abc$23348$new_n3061 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[7][15] yv[7][13] $abc$23348$new_n3063 yv[8][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20752 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][15] yv[7][12] $abc$23348$new_n3056 $abc$23348$new_n3048 $abc$23348$new_n3063 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3065 yv[8][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20754 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] xv[7][15] yv[7][12] $abc$23348$new_n3056 $abc$23348$new_n3048 $abc$23348$new_n3065 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[7][15] yv[7][11] $abc$23348$new_n3067 yv[8][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20756 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][15] yv[7][10] $abc$23348$new_n3069 $abc$23348$new_n3068 $abc$23348$new_n3067 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$23348$new_n3057 $abc$23348$new_n3054 xv[7][15] $abc$23348$new_n3068 +001 1 +010 1 +011 1 +.names $abc$23348$new_n3049 $abc$23348$new_n3054 xv[7][15] $abc$23348$new_n3069 +000 1 +010 1 +011 1 +.names i_ce xv[7][15] yv[7][10] $abc$23348$new_n3071 yv[8][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20758 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] $abc$23348$new_n3068 $abc$23348$new_n3069 $abc$23348$new_n3071 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[7][15] yv[7][9] $abc$23348$new_n3073 yv[8][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20760 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] yv[7][8] xv[7][15] $abc$23348$new_n3058 $abc$23348$new_n3074 $abc$23348$new_n3073 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[7][15] yv[7][7] $abc$23348$new_n3050 $abc$23348$new_n3074 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3076 yv[8][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20762 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] xv[7][15] yv[7][8] $abc$23348$new_n3058 $abc$23348$new_n3074 $abc$23348$new_n3076 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[7][15] yv[7][7] $abc$23348$new_n3078 yv[8][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20764 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][14] yv[7][6] $abc$23348$new_n3059 $abc$23348$new_n3050 $abc$23348$new_n3078 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][14] yv[7][6] $abc$23348$new_n3080 yv[8][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20766 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][13] yv[7][5] $abc$23348$new_n3051 $abc$23348$new_n3059 $abc$23348$new_n3080 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][13] yv[7][5] $abc$23348$new_n3082 yv[8][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20768 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][12] yv[7][4] $abc$23348$new_n3060 $abc$23348$new_n3051 $abc$23348$new_n3082 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][12] yv[7][4] $abc$23348$new_n3084 yv[8][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20770 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][11] yv[7][3] $abc$23348$new_n3052 $abc$23348$new_n3060 $abc$23348$new_n3084 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][11] yv[7][3] $abc$23348$new_n3086 yv[8][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20772 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][10] yv[7][2] $abc$23348$new_n3061 $abc$23348$new_n3053 $abc$23348$new_n3086 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[7][10] yv[7][2] $abc$23348$new_n3088 yv[8][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20774 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] $abc$23348$new_n3053 $abc$23348$new_n3061 $abc$23348$new_n3088 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3090 yv[8][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20776 +001 1 +011 1 +110 1 +111 1 +.names xv[7][9] yv[7][1] ph[7][19] yv[7][0] xv[7][8] $abc$23348$new_n3090 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[7][8] yv[7][0] yv[8][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20778 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[7][15] xv[7][14] $abc$23348$new_n3093 xv[8][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20780 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] $abc$23348$new_n3094 $abc$23348$new_n3102 $abc$23348$new_n3093 +000 1 +001 1 +101 1 +111 1 +.names yv[7][15] $abc$23348$new_n3095 xv[7][12] xv[7][13] $abc$23348$new_n3094 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[7][15] xv[7][10] xv[7][11] $abc$23348$new_n3096 $abc$23348$new_n3101 $abc$23348$new_n3095 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3097 yv[7][15] xv[7][8] xv[7][9] $abc$23348$new_n3096 +1000 1 +1111 1 +.names xv[7][6] yv[7][14] yv[7][15] xv[7][7] $abc$23348$new_n3098 $abc$23348$new_n3097 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[7][12] xv[7][4] xv[7][5] yv[7][13] $abc$23348$new_n3099 $abc$23348$new_n3098 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][10] xv[7][2] xv[7][3] yv[7][11] $abc$23348$new_n3100 $abc$23348$new_n3099 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][8] xv[7][0] xv[7][1] yv[7][9] $abc$23348$new_n3100 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names xv[7][8] xv[7][9] $abc$23348$new_n3101 +00 1 +.names yv[7][15] $abc$23348$new_n3103 xv[7][12] xv[7][13] $abc$23348$new_n3102 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[7][15] xv[7][10] xv[7][11] $abc$23348$new_n3104 $abc$23348$new_n3101 $abc$23348$new_n3103 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[7][8] xv[7][9] yv[7][15] xv[7][7] $abc$23348$new_n3105 $abc$23348$new_n3104 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[7][5] yv[7][13] xv[7][6] yv[7][14] $abc$23348$new_n3106 $abc$23348$new_n3105 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][4] yv[7][12] $abc$23348$new_n3107 $abc$23348$new_n3106 +000 1 +001 1 +011 1 +101 1 +.names xv[7][2] yv[7][10] xv[7][3] yv[7][11] $abc$23348$new_n3108 $abc$23348$new_n3107 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][0] yv[7][8] xv[7][1] yv[7][9] $abc$23348$new_n3108 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[7][15] xv[7][13] $abc$23348$new_n3110 xv[8][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20782 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][12] yv[7][15] $abc$23348$new_n3103 $abc$23348$new_n3095 $abc$23348$new_n3110 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3112 xv[8][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20784 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] yv[7][15] xv[7][12] $abc$23348$new_n3103 $abc$23348$new_n3095 $abc$23348$new_n3112 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[7][15] xv[7][11] $abc$23348$new_n3114 xv[8][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20786 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][10] yv[7][15] $abc$23348$new_n3116 $abc$23348$new_n3115 $abc$23348$new_n3114 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3104 $abc$23348$new_n3101 yv[7][15] $abc$23348$new_n3115 +000 1 +010 1 +011 1 +.names $abc$23348$new_n3096 $abc$23348$new_n3101 yv[7][15] $abc$23348$new_n3116 +001 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3118 xv[8][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20788 +001 1 +011 1 +100 1 +101 1 +.names yv[7][15] xv[7][10] ph[7][19] $abc$23348$new_n3116 $abc$23348$new_n3115 $abc$23348$new_n3118 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[7][15] xv[7][9] $abc$23348$new_n3120 xv[8][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20790 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][8] yv[7][15] $abc$23348$new_n3097 $abc$23348$new_n3121 $abc$23348$new_n3120 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names yv[7][15] xv[7][7] $abc$23348$new_n3105 $abc$23348$new_n3121 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3123 xv[8][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20792 +001 1 +011 1 +100 1 +101 1 +.names yv[7][15] xv[7][8] ph[7][19] $abc$23348$new_n3097 $abc$23348$new_n3121 $abc$23348$new_n3123 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce yv[7][15] xv[7][7] $abc$23348$new_n3125 xv[8][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20794 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][6] yv[7][14] $abc$23348$new_n3098 $abc$23348$new_n3105 $abc$23348$new_n3125 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][6] yv[7][14] $abc$23348$new_n3127 xv[8][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20796 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][5] yv[7][13] $abc$23348$new_n3106 $abc$23348$new_n3098 $abc$23348$new_n3127 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[7][5] yv[7][13] $abc$23348$new_n3129 xv[8][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20798 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][4] yv[7][12] $abc$23348$new_n3107 $abc$23348$new_n3099 $abc$23348$new_n3129 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3131 xv[8][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20800 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] xv[7][4] yv[7][12] $abc$23348$new_n3107 $abc$23348$new_n3099 $abc$23348$new_n3131 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[7][3] yv[7][11] $abc$23348$new_n3133 xv[8][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20802 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][2] yv[7][10] $abc$23348$new_n3108 $abc$23348$new_n3100 $abc$23348$new_n3133 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[7][2] yv[7][10] $abc$23348$new_n3135 xv[8][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20804 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] $abc$23348$new_n3100 $abc$23348$new_n3108 $abc$23348$new_n3135 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[7][1] yv[7][9] $abc$23348$new_n3137 xv[8][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20806 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][8] ph[7][19] xv[7][0] $abc$23348$new_n3137 +100 1 +111 1 +.names i_ce xv[7][0] yv[7][8] xv[8][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20808 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[8][18] $abc$23348$new_n3140 ph[9][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20810 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[8][19] ph[8][16] ph[8][17] $abc$23348$new_n3148 $abc$23348$new_n3141 $abc$23348$new_n3140 +00000 1 +00001 1 +11101 1 +.names ph[8][14] ph[8][15] $abc$23348$new_n3142 $abc$23348$new_n3141 +111 1 +.names ph[8][13] $abc$23348$new_n3147 $abc$23348$new_n3143 $abc$23348$new_n3142 +111 1 +.names ph[8][9] $abc$23348$new_n3144 ph[8][8] $abc$23348$new_n3143 +101 1 +110 1 +111 1 +.names ph[8][7] ph[8][6] ph[8][5] $abc$23348$new_n3145 $abc$23348$new_n3144 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[8][4] $abc$23348$new_n3146 $abc$23348$new_n3145 +11 1 +.names ph[8][3] ph[8][2] ph[8][0] ph[8][1] $abc$23348$new_n3146 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[8][10] ph[8][11] ph[8][12] $abc$23348$new_n3147 +111 1 +.names ph[8][19] $abc$23348$new_n3149 ph[8][14] ph[8][15] $abc$23348$new_n3148 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names $abc$23348$new_n3150 $abc$23348$new_n3154 ph[8][13] $abc$23348$new_n3149 +110 1 +.names ph[8][9] $abc$23348$new_n3151 ph[8][8] $abc$23348$new_n3150 +000 1 +010 1 +011 1 +.names ph[8][7] ph[8][6] $abc$23348$new_n3152 ph[8][5] $abc$23348$new_n3151 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$23348$new_n3153 ph[8][4] $abc$23348$new_n3152 +10 1 +.names ph[8][3] ph[8][2] ph[8][0] ph[8][1] $abc$23348$new_n3153 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[8][10] ph[8][11] ph[8][12] $abc$23348$new_n3154 +000 1 +.names i_ce $abc$23348$new_n3156 ph[9][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20812 +001 1 +011 1 +110 1 +111 1 +.names ph[8][17] ph[8][19] ph[8][16] $abc$23348$new_n3148 $abc$23348$new_n3141 $abc$23348$new_n3156 +00000 1 +00001 1 +01101 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3158 ph[9][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20814 +001 1 +011 1 +110 1 +111 1 +.names ph[8][16] $abc$23348$new_n3148 ph[8][19] $abc$23348$new_n3141 $abc$23348$new_n3158 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3163 ph[9][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20818 +001 1 +011 1 +110 1 +111 1 +.names ph[8][14] ph[8][19] $abc$23348$new_n3149 $abc$23348$new_n3142 $abc$23348$new_n3163 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n3168 ph[9][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20822 +001 1 +011 1 +110 1 +111 1 +.names ph[8][10] ph[8][12] ph[8][11] $abc$23348$new_n3170 $abc$23348$new_n3169 $abc$23348$new_n3168 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[8][19] $abc$23348$new_n3143 $abc$23348$new_n3169 +11 1 +.names $abc$23348$new_n3150 ph[8][19] $abc$23348$new_n3170 +10 1 +.names i_ce $abc$23348$new_n3172 ph[9][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20824 +001 1 +011 1 +110 1 +111 1 +.names ph[8][11] ph[8][10] $abc$23348$new_n3170 $abc$23348$new_n3169 $abc$23348$new_n3172 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[8][10] $abc$23348$new_n3170 $abc$23348$new_n3169 ph[9][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20826 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3175 ph[9][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20828 +001 1 +011 1 +100 1 +101 1 +.names ph[8][19] ph[8][9] ph[8][8] $abc$23348$new_n3151 $abc$23348$new_n3144 $abc$23348$new_n3175 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3177 ph[9][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20830 +001 1 +011 1 +110 1 +111 1 +.names ph[8][8] ph[8][19] $abc$23348$new_n3151 $abc$23348$new_n3144 $abc$23348$new_n3177 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[8][7] $abc$23348$new_n3179 ph[9][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20832 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[8][19] ph[8][5] ph[8][6] $abc$23348$new_n3145 $abc$23348$new_n3152 $abc$23348$new_n3179 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3181 ph[9][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20834 +001 1 +011 1 +100 1 +101 1 +.names ph[8][4] ph[8][6] ph[8][5] $abc$23348$new_n3183 $abc$23348$new_n3182 $abc$23348$new_n3181 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3153 ph[8][19] $abc$23348$new_n3182 +10 1 +.names ph[8][19] $abc$23348$new_n3146 $abc$23348$new_n3183 +11 1 +.names i_ce $abc$23348$new_n3185 ph[9][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20836 +001 1 +011 1 +100 1 +101 1 +.names ph[8][4] ph[8][5] $abc$23348$new_n3183 $abc$23348$new_n3182 $abc$23348$new_n3185 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[8][4] $abc$23348$new_n3183 $abc$23348$new_n3182 ph[9][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20838 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3188 ph[9][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20840 +001 1 +011 1 +110 1 +111 1 +.names ph[8][3] ph[8][19] ph[8][2] ph[8][0] ph[8][1] $abc$23348$new_n3188 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n3190 ph[9][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20842 +001 1 +011 1 +100 1 +101 1 +.names ph[8][19] ph[8][2] ph[8][0] ph[8][1] $abc$23348$new_n3190 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[8][19] ph[8][0] ph[8][1] ph[9][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20844 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[8][0] ph[9][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20846 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[8][15] yv[8][14] $abc$23348$new_n3194 yv[9][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20848 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] $abc$23348$new_n3195 $abc$23348$new_n3204 $abc$23348$new_n3194 +000 1 +001 1 +101 1 +111 1 +.names xv[8][15] yv[8][12] yv[8][13] $abc$23348$new_n3196 $abc$23348$new_n3202 $abc$23348$new_n3195 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names $abc$23348$new_n3197 xv[8][15] yv[8][9] yv[8][10] yv[8][11] $abc$23348$new_n3196 +10111 1 +11000 1 +.names yv[8][8] xv[8][15] yv[8][6] yv[8][7] $abc$23348$new_n3198 $abc$23348$new_n3197 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[8][14] yv[8][5] $abc$23348$new_n3199 $abc$23348$new_n3198 +000 1 +001 1 +011 1 +101 1 +.names xv[8][12] yv[8][3] xv[8][13] yv[8][4] $abc$23348$new_n3200 $abc$23348$new_n3199 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][11] yv[8][2] $abc$23348$new_n3201 $abc$23348$new_n3200 +000 1 +001 1 +011 1 +101 1 +.names xv[8][9] yv[8][0] xv[8][10] yv[8][1] $abc$23348$new_n3201 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$23348$new_n3203 yv[8][10] yv[8][11] $abc$23348$new_n3202 +100 1 +.names yv[8][8] yv[8][9] $abc$23348$new_n3203 +00 1 +.names xv[8][15] $abc$23348$new_n3205 yv[8][12] yv[8][13] $abc$23348$new_n3204 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[8][15] yv[8][10] yv[8][11] $abc$23348$new_n3206 $abc$23348$new_n3203 $abc$23348$new_n3205 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[8][15] yv[8][8] yv[8][9] $abc$23348$new_n3207 $abc$23348$new_n3206 +0000 1 +1110 1 +.names xv[8][15] $abc$23348$new_n3208 yv[8][6] yv[8][7] $abc$23348$new_n3207 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[8][13] xv[8][14] yv[8][4] yv[8][5] $abc$23348$new_n3209 $abc$23348$new_n3208 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[8][11] xv[8][12] yv[8][2] yv[8][3] $abc$23348$new_n3210 $abc$23348$new_n3209 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[8][9] xv[8][10] yv[8][0] yv[8][1] $abc$23348$new_n3210 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[8][15] yv[8][13] $abc$23348$new_n3212 yv[9][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20850 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][15] yv[8][12] $abc$23348$new_n3205 $abc$23348$new_n3213 $abc$23348$new_n3212 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$23348$new_n3196 $abc$23348$new_n3202 xv[8][15] $abc$23348$new_n3213 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3215 yv[9][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20852 +001 1 +011 1 +110 1 +111 1 +.names ph[8][19] xv[8][15] yv[8][12] $abc$23348$new_n3205 $abc$23348$new_n3213 $abc$23348$new_n3215 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][15] yv[8][11] $abc$23348$new_n3217 yv[9][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20854 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][15] yv[8][10] $abc$23348$new_n3219 $abc$23348$new_n3218 $abc$23348$new_n3217 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$23348$new_n3206 $abc$23348$new_n3203 xv[8][15] $abc$23348$new_n3218 +001 1 +010 1 +011 1 +.names xv[8][15] $abc$23348$new_n3197 yv[8][9] $abc$23348$new_n3203 $abc$23348$new_n3219 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1111 1 +.names i_ce xv[8][15] yv[8][10] $abc$23348$new_n3221 yv[9][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20856 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] $abc$23348$new_n3218 $abc$23348$new_n3219 $abc$23348$new_n3221 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[8][15] yv[8][9] $abc$23348$new_n3223 yv[9][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20858 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] yv[8][8] xv[8][15] $abc$23348$new_n3207 $abc$23348$new_n3224 $abc$23348$new_n3223 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[8][15] $abc$23348$new_n3198 yv[8][6] yv[8][7] $abc$23348$new_n3224 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3226 yv[9][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20860 +001 1 +011 1 +110 1 +111 1 +.names ph[8][19] xv[8][15] yv[8][8] $abc$23348$new_n3207 $abc$23348$new_n3224 $abc$23348$new_n3226 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][15] yv[8][7] $abc$23348$new_n3228 yv[9][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20862 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] yv[8][6] xv[8][15] $abc$23348$new_n3208 $abc$23348$new_n3198 $abc$23348$new_n3228 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n3230 yv[9][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20864 +001 1 +011 1 +100 1 +101 1 +.names ph[8][19] xv[8][15] yv[8][6] $abc$23348$new_n3208 $abc$23348$new_n3198 $abc$23348$new_n3230 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][14] yv[8][5] $abc$23348$new_n3232 yv[9][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20866 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][13] yv[8][4] $abc$23348$new_n3209 $abc$23348$new_n3199 $abc$23348$new_n3232 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[8][13] yv[8][4] $abc$23348$new_n3234 yv[9][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20868 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][12] yv[8][3] $abc$23348$new_n3200 $abc$23348$new_n3209 $abc$23348$new_n3234 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[8][12] yv[8][3] $abc$23348$new_n3236 yv[9][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20870 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][11] yv[8][2] $abc$23348$new_n3210 $abc$23348$new_n3201 $abc$23348$new_n3236 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][11] yv[8][2] $abc$23348$new_n3238 yv[9][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20872 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3201 $abc$23348$new_n3210 $abc$23348$new_n3238 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3240 yv[9][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20874 +001 1 +011 1 +110 1 +111 1 +.names xv[8][10] yv[8][1] ph[8][19] yv[8][0] xv[8][9] $abc$23348$new_n3240 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[8][9] yv[8][0] yv[9][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20876 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[8][15] xv[8][14] $abc$23348$new_n3243 xv[9][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20878 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3244 $abc$23348$new_n3254 $abc$23348$new_n3243 +000 1 +001 1 +101 1 +111 1 +.names yv[8][15] xv[8][12] xv[8][13] $abc$23348$new_n3245 $abc$23348$new_n3252 $abc$23348$new_n3244 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3251 yv[8][15] xv[8][8] xv[8][9] $abc$23348$new_n3246 $abc$23348$new_n3245 +10000 1 +11110 1 +.names yv[8][15] $abc$23348$new_n3247 xv[8][6] xv[8][7] $abc$23348$new_n3246 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[8][14] xv[8][5] $abc$23348$new_n3248 $abc$23348$new_n3247 +001 1 +100 1 +101 1 +111 1 +.names yv[8][12] xv[8][3] xv[8][4] yv[8][13] $abc$23348$new_n3249 $abc$23348$new_n3248 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[8][11] xv[8][2] $abc$23348$new_n3250 $abc$23348$new_n3249 +001 1 +100 1 +101 1 +111 1 +.names yv[8][9] xv[8][0] xv[8][1] yv[8][10] $abc$23348$new_n3250 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[8][15] xv[8][10] xv[8][11] $abc$23348$new_n3251 +000 1 +111 1 +.names $abc$23348$new_n3253 xv[8][10] xv[8][11] $abc$23348$new_n3252 +100 1 +.names xv[8][8] xv[8][9] $abc$23348$new_n3253 +00 1 +.names yv[8][15] $abc$23348$new_n3255 xv[8][12] xv[8][13] $abc$23348$new_n3254 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[8][15] xv[8][10] xv[8][11] $abc$23348$new_n3256 $abc$23348$new_n3253 $abc$23348$new_n3255 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[8][8] xv[8][9] yv[8][15] xv[8][7] $abc$23348$new_n3257 $abc$23348$new_n3256 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[8][5] yv[8][14] yv[8][15] xv[8][6] $abc$23348$new_n3258 $abc$23348$new_n3257 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][3] yv[8][12] xv[8][4] yv[8][13] $abc$23348$new_n3259 $abc$23348$new_n3258 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][2] yv[8][11] $abc$23348$new_n3260 $abc$23348$new_n3259 +000 1 +001 1 +011 1 +101 1 +.names xv[8][0] yv[8][9] xv[8][1] yv[8][10] $abc$23348$new_n3260 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[8][15] xv[8][13] $abc$23348$new_n3262 xv[9][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20880 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][12] yv[8][15] $abc$23348$new_n3255 $abc$23348$new_n3263 $abc$23348$new_n3262 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$23348$new_n3245 $abc$23348$new_n3252 yv[8][15] $abc$23348$new_n3263 +001 1 +010 1 +011 1 +.names i_ce yv[8][15] xv[8][12] $abc$23348$new_n3265 xv[9][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20882 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3263 $abc$23348$new_n3255 $abc$23348$new_n3265 +000 1 +001 1 +101 1 +111 1 +.names i_ce yv[8][15] xv[8][11] $abc$23348$new_n3267 xv[9][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20884 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][10] yv[8][15] $abc$23348$new_n3269 $abc$23348$new_n3268 $abc$23348$new_n3267 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3256 $abc$23348$new_n3253 yv[8][15] $abc$23348$new_n3268 +000 1 +010 1 +011 1 +.names yv[8][15] $abc$23348$new_n3246 xv[8][8] xv[8][9] $abc$23348$new_n3269 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce yv[8][15] xv[8][10] $abc$23348$new_n3271 xv[9][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20886 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] $abc$23348$new_n3268 $abc$23348$new_n3269 $abc$23348$new_n3271 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[8][15] xv[8][9] $abc$23348$new_n3273 xv[9][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20888 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][8] yv[8][15] $abc$23348$new_n3274 $abc$23348$new_n3246 $abc$23348$new_n3273 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names yv[8][15] xv[8][7] $abc$23348$new_n3257 $abc$23348$new_n3274 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3276 xv[9][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20890 +001 1 +011 1 +100 1 +101 1 +.names ph[8][19] yv[8][15] xv[8][8] $abc$23348$new_n3274 $abc$23348$new_n3246 $abc$23348$new_n3276 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[8][15] xv[8][7] $abc$23348$new_n3278 xv[9][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20892 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][6] yv[8][15] $abc$23348$new_n3247 $abc$23348$new_n3257 $abc$23348$new_n3278 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce yv[8][15] xv[8][6] $abc$23348$new_n3280 xv[9][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20894 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] yv[8][14] xv[8][5] $abc$23348$new_n3258 $abc$23348$new_n3248 $abc$23348$new_n3280 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3282 xv[9][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20896 +001 1 +011 1 +110 1 +111 1 +.names ph[8][19] xv[8][5] yv[8][14] $abc$23348$new_n3258 $abc$23348$new_n3248 $abc$23348$new_n3282 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][4] yv[8][13] $abc$23348$new_n3284 xv[9][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20898 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][3] yv[8][12] $abc$23348$new_n3259 $abc$23348$new_n3249 $abc$23348$new_n3284 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[8][3] yv[8][12] $abc$23348$new_n3286 xv[9][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20900 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3249 $abc$23348$new_n3259 $abc$23348$new_n3286 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[8][2] yv[8][11] $abc$23348$new_n3288 xv[9][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20902 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3250 $abc$23348$new_n3260 $abc$23348$new_n3288 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3290 xv[9][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20904 +001 1 +011 1 +110 1 +111 1 +.names xv[8][1] yv[8][10] ph[8][19] xv[8][0] yv[8][9] $abc$23348$new_n3290 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[8][0] yv[8][9] xv[9][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20906 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3293 ph[10][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20908 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] ph[9][18] ph[9][17] $abc$23348$new_n3299 $abc$23348$new_n3294 $abc$23348$new_n3293 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[9][14] ph[9][15] ph[9][16] $abc$23348$new_n3295 $abc$23348$new_n3294 +1111 1 +.names ph[9][10] ph[9][11] ph[9][12] ph[9][13] $abc$23348$new_n3296 $abc$23348$new_n3295 +11111 1 +.names ph[9][9] ph[9][8] $abc$23348$new_n3297 ph[9][7] $abc$23348$new_n3296 +1101 1 +1110 1 +1111 1 +.names ph[9][6] $abc$23348$new_n3298 $abc$23348$new_n3297 +10 1 +.names ph[9][5] ph[9][3] ph[9][4] ph[9][1] ph[9][2] $abc$23348$new_n3298 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$23348$new_n3300 ph[9][14] ph[9][15] ph[9][16] $abc$23348$new_n3299 +1000 1 +.names $abc$23348$new_n3301 ph[9][10] ph[9][11] ph[9][12] ph[9][13] $abc$23348$new_n3300 +10000 1 +.names ph[9][9] ph[9][8] $abc$23348$new_n3302 ph[9][7] $abc$23348$new_n3301 +0000 1 +0010 1 +0011 1 +.names ph[9][6] $abc$23348$new_n3303 $abc$23348$new_n3302 +00 1 +.names ph[9][5] ph[9][3] ph[9][4] ph[9][1] ph[9][2] $abc$23348$new_n3303 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3305 ph[10][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20910 +001 1 +011 1 +100 1 +101 1 +.names ph[9][17] ph[9][19] $abc$23348$new_n3299 $abc$23348$new_n3294 $abc$23348$new_n3305 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[9][16] $abc$23348$new_n3307 ph[10][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20912 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[9][19] ph[9][14] ph[9][15] $abc$23348$new_n3295 $abc$23348$new_n3300 $abc$23348$new_n3307 +00001 1 +00011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3309 ph[10][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20914 +001 1 +011 1 +110 1 +111 1 +.names ph[9][15] ph[9][14] $abc$23348$new_n3313 $abc$23348$new_n3310 $abc$23348$new_n3309 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names ph[9][11] ph[9][12] ph[9][13] $abc$23348$new_n3311 $abc$23348$new_n3310 +1111 1 +.names ph[9][10] $abc$23348$new_n3312 $abc$23348$new_n3311 +11 1 +.names ph[9][19] $abc$23348$new_n3296 $abc$23348$new_n3312 +11 1 +.names $abc$23348$new_n3300 ph[9][19] $abc$23348$new_n3313 +10 1 +.names i_ce ph[9][14] $abc$23348$new_n3313 $abc$23348$new_n3310 ph[10][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20916 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3316 ph[10][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20918 +001 1 +011 1 +100 1 +101 1 +.names ph[9][13] ph[9][11] ph[9][12] $abc$23348$new_n3317 $abc$23348$new_n3311 $abc$23348$new_n3316 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11101 1 +11111 1 +.names $abc$23348$new_n3318 ph[9][10] $abc$23348$new_n3317 +10 1 +.names $abc$23348$new_n3301 ph[9][19] $abc$23348$new_n3318 +10 1 +.names $abc$23348$new_n3320 ph[10][12] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$20920 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[9][12] ph[9][11] $abc$23348$new_n3317 $abc$23348$new_n3311 $abc$23348$new_n3320 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce ph[9][11] $abc$23348$new_n3317 $abc$23348$new_n3311 ph[10][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20922 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[9][10] $abc$23348$new_n3318 $abc$23348$new_n3312 ph[10][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20924 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3324 ph[9][9] ph[10][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20926 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[9][19] ph[9][7] ph[9][8] $abc$23348$new_n3297 $abc$23348$new_n3302 $abc$23348$new_n3324 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3326 ph[10][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20928 +001 1 +011 1 +110 1 +111 1 +.names ph[9][8] ph[9][19] ph[9][7] $abc$23348$new_n3302 $abc$23348$new_n3297 $abc$23348$new_n3326 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$23348$new_n3328 ph[10][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20930 +001 1 +011 1 +110 1 +111 1 +.names ph[9][6] ph[9][7] $abc$23348$new_n3330 $abc$23348$new_n3329 $abc$23348$new_n3328 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[9][19] $abc$23348$new_n3303 $abc$23348$new_n3329 +00 1 +.names ph[9][19] $abc$23348$new_n3298 $abc$23348$new_n3330 +10 1 +.names i_ce ph[9][6] $abc$23348$new_n3330 $abc$23348$new_n3329 ph[10][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20932 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[9][5] $abc$23348$new_n3333 ph[10][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20934 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[9][19] ph[9][1] ph[9][2] ph[9][3] ph[9][4] $abc$23348$new_n3333 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3335 ph[10][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20936 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] ph[9][4] ph[9][1] ph[9][2] ph[9][3] $abc$23348$new_n3335 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3337 ph[10][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20938 +001 1 +011 1 +100 1 +101 1 +.names ph[9][3] ph[9][19] ph[9][1] ph[9][2] $abc$23348$new_n3337 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[9][19] ph[9][1] ph[9][2] ph[10][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20940 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[9][1] ph[10][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20942 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[9][0] ph[10][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20944 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[9][15] yv[9][14] $abc$23348$new_n3342 yv[10][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20946 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] $abc$23348$new_n3343 $abc$23348$new_n3351 $abc$23348$new_n3342 +000 1 +001 1 +101 1 +111 1 +.names xv[9][15] $abc$23348$new_n3344 yv[9][12] yv[9][13] $abc$23348$new_n3343 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[9][15] yv[9][10] yv[9][11] $abc$23348$new_n3345 $abc$23348$new_n3350 $abc$23348$new_n3344 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[9][15] yv[9][8] yv[9][9] $abc$23348$new_n3346 $abc$23348$new_n3345 +0110 1 +1000 1 +.names xv[9][15] $abc$23348$new_n3347 yv[9][5] yv[9][6] yv[9][7] $abc$23348$new_n3346 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[9][13] yv[9][3] xv[9][14] yv[9][4] $abc$23348$new_n3348 $abc$23348$new_n3347 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][12] yv[9][2] $abc$23348$new_n3349 $abc$23348$new_n3348 +000 1 +001 1 +011 1 +101 1 +.names xv[9][10] yv[9][0] xv[9][11] yv[9][1] $abc$23348$new_n3349 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[9][8] yv[9][9] $abc$23348$new_n3350 +00 1 +.names xv[9][15] $abc$23348$new_n3352 yv[9][12] yv[9][13] $abc$23348$new_n3351 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[9][15] yv[9][10] yv[9][11] $abc$23348$new_n3353 $abc$23348$new_n3350 $abc$23348$new_n3352 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[9][15] yv[9][9] yv[9][8] yv[9][7] $abc$23348$new_n3354 $abc$23348$new_n3353 +00000 1 +00010 1 +00011 1 +11110 1 +.names xv[9][15] yv[9][6] $abc$23348$new_n3355 $abc$23348$new_n3354 +001 1 +100 1 +101 1 +111 1 +.names xv[9][14] xv[9][15] yv[9][4] yv[9][5] $abc$23348$new_n3356 $abc$23348$new_n3355 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[9][12] xv[9][13] yv[9][2] yv[9][3] $abc$23348$new_n3357 $abc$23348$new_n3356 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[9][10] xv[9][11] yv[9][0] yv[9][1] $abc$23348$new_n3357 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[9][15] yv[9][13] $abc$23348$new_n3359 yv[10][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20948 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][15] yv[9][12] $abc$23348$new_n3352 $abc$23348$new_n3344 $abc$23348$new_n3359 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3361 yv[10][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20950 +001 1 +011 1 +100 1 +101 1 +.names ph[9][19] xv[9][15] yv[9][12] $abc$23348$new_n3352 $abc$23348$new_n3344 $abc$23348$new_n3361 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][15] yv[9][11] $abc$23348$new_n3363 yv[10][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20952 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][15] yv[9][10] $abc$23348$new_n3365 $abc$23348$new_n3364 $abc$23348$new_n3363 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$23348$new_n3353 $abc$23348$new_n3350 xv[9][15] $abc$23348$new_n3364 +001 1 +010 1 +011 1 +.names $abc$23348$new_n3345 $abc$23348$new_n3350 xv[9][15] $abc$23348$new_n3365 +000 1 +010 1 +011 1 +.names i_ce xv[9][15] yv[9][10] $abc$23348$new_n3367 yv[10][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20954 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] $abc$23348$new_n3364 $abc$23348$new_n3365 $abc$23348$new_n3367 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[9][15] yv[9][9] $abc$23348$new_n3369 yv[10][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20956 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] yv[9][8] xv[9][15] $abc$23348$new_n3346 $abc$23348$new_n3370 $abc$23348$new_n3369 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names xv[9][15] yv[9][7] $abc$23348$new_n3354 $abc$23348$new_n3370 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3372 yv[10][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20958 +001 1 +011 1 +110 1 +111 1 +.names xv[9][15] yv[9][8] ph[9][19] $abc$23348$new_n3346 $abc$23348$new_n3370 $abc$23348$new_n3372 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[9][15] yv[9][7] $abc$23348$new_n3374 yv[10][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20960 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] yv[9][6] xv[9][15] $abc$23348$new_n3355 $abc$23348$new_n3375 $abc$23348$new_n3374 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[9][15] yv[9][5] $abc$23348$new_n3347 $abc$23348$new_n3375 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3377 yv[10][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20962 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] xv[9][15] yv[9][6] $abc$23348$new_n3355 $abc$23348$new_n3375 $abc$23348$new_n3377 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[9][15] yv[9][5] $abc$23348$new_n3379 yv[10][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20964 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][14] yv[9][4] $abc$23348$new_n3356 $abc$23348$new_n3347 $abc$23348$new_n3379 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[9][14] yv[9][4] $abc$23348$new_n3381 yv[10][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20966 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][13] yv[9][3] $abc$23348$new_n3348 $abc$23348$new_n3356 $abc$23348$new_n3381 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][13] yv[9][3] $abc$23348$new_n3383 yv[10][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20968 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][12] yv[9][2] $abc$23348$new_n3357 $abc$23348$new_n3349 $abc$23348$new_n3383 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][12] yv[9][2] $abc$23348$new_n3385 yv[10][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20970 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] $abc$23348$new_n3349 $abc$23348$new_n3357 $abc$23348$new_n3385 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3387 yv[10][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20972 +001 1 +011 1 +110 1 +111 1 +.names xv[9][11] yv[9][1] ph[9][19] yv[9][0] xv[9][10] $abc$23348$new_n3387 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[9][10] yv[9][0] yv[10][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20974 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[9][15] xv[9][14] $abc$23348$new_n3390 xv[10][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20976 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] $abc$23348$new_n3391 $abc$23348$new_n3399 $abc$23348$new_n3390 +000 1 +001 1 +101 1 +111 1 +.names yv[9][15] $abc$23348$new_n3392 xv[9][12] xv[9][13] $abc$23348$new_n3391 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[9][15] xv[9][10] xv[9][11] $abc$23348$new_n3393 $abc$23348$new_n3398 $abc$23348$new_n3392 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][15] xv[9][8] xv[9][9] $abc$23348$new_n3394 $abc$23348$new_n3393 +0000 1 +1110 1 +.names yv[9][15] $abc$23348$new_n3395 xv[9][5] xv[9][6] xv[9][7] $abc$23348$new_n3394 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[9][14] xv[9][4] $abc$23348$new_n3396 $abc$23348$new_n3395 +001 1 +100 1 +101 1 +111 1 +.names yv[9][12] xv[9][2] xv[9][3] yv[9][13] $abc$23348$new_n3397 $abc$23348$new_n3396 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][10] xv[9][0] xv[9][1] yv[9][11] $abc$23348$new_n3397 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names xv[9][8] xv[9][9] $abc$23348$new_n3398 +00 1 +.names yv[9][15] $abc$23348$new_n3400 xv[9][12] xv[9][13] $abc$23348$new_n3399 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[9][15] xv[9][10] xv[9][11] $abc$23348$new_n3401 $abc$23348$new_n3398 $abc$23348$new_n3400 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[9][15] xv[9][8] xv[9][9] $abc$23348$new_n3402 $abc$23348$new_n3401 +0110 1 +1000 1 +.names yv[9][15] $abc$23348$new_n3403 xv[9][5] xv[9][6] xv[9][7] $abc$23348$new_n3402 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[9][3] yv[9][13] xv[9][4] yv[9][14] $abc$23348$new_n3404 $abc$23348$new_n3403 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][2] yv[9][12] $abc$23348$new_n3405 $abc$23348$new_n3404 +000 1 +001 1 +011 1 +101 1 +.names xv[9][0] yv[9][10] xv[9][1] yv[9][11] $abc$23348$new_n3405 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[9][15] xv[9][13] $abc$23348$new_n3407 xv[10][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20978 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][12] yv[9][15] $abc$23348$new_n3400 $abc$23348$new_n3392 $abc$23348$new_n3407 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3409 xv[10][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20980 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] yv[9][15] xv[9][12] $abc$23348$new_n3400 $abc$23348$new_n3392 $abc$23348$new_n3409 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[9][15] xv[9][11] $abc$23348$new_n3411 xv[10][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20982 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][10] yv[9][15] $abc$23348$new_n3413 $abc$23348$new_n3412 $abc$23348$new_n3411 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3401 $abc$23348$new_n3398 yv[9][15] $abc$23348$new_n3412 +000 1 +010 1 +011 1 +.names $abc$23348$new_n3393 $abc$23348$new_n3398 yv[9][15] $abc$23348$new_n3413 +001 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3415 xv[10][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20984 +001 1 +011 1 +100 1 +101 1 +.names yv[9][15] xv[9][10] ph[9][19] $abc$23348$new_n3413 $abc$23348$new_n3412 $abc$23348$new_n3415 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[9][15] xv[9][9] $abc$23348$new_n3417 xv[10][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20986 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][8] yv[9][15] $abc$23348$new_n3402 $abc$23348$new_n3394 $abc$23348$new_n3417 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3419 xv[10][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20988 +001 1 +011 1 +100 1 +101 1 +.names ph[9][19] yv[9][15] xv[9][8] $abc$23348$new_n3402 $abc$23348$new_n3394 $abc$23348$new_n3419 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[9][15] xv[9][7] $abc$23348$new_n3421 xv[10][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20990 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][6] yv[9][15] $abc$23348$new_n3423 $abc$23348$new_n3422 $abc$23348$new_n3421 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names yv[9][15] xv[9][5] $abc$23348$new_n3395 $abc$23348$new_n3422 +001 1 +100 1 +101 1 +111 1 +.names yv[9][15] xv[9][5] $abc$23348$new_n3403 $abc$23348$new_n3423 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3425 xv[10][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20992 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] yv[9][15] xv[9][6] $abc$23348$new_n3423 $abc$23348$new_n3422 $abc$23348$new_n3425 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[9][15] xv[9][5] $abc$23348$new_n3427 xv[10][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20994 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] $abc$23348$new_n3395 $abc$23348$new_n3403 $abc$23348$new_n3427 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[9][4] yv[9][14] $abc$23348$new_n3429 xv[10][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20996 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][3] yv[9][13] $abc$23348$new_n3404 $abc$23348$new_n3396 $abc$23348$new_n3429 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[9][3] yv[9][13] $abc$23348$new_n3431 xv[10][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20998 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][2] yv[9][12] $abc$23348$new_n3405 $abc$23348$new_n3397 $abc$23348$new_n3431 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[9][2] yv[9][12] $abc$23348$new_n3433 xv[10][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21000 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] $abc$23348$new_n3397 $abc$23348$new_n3405 $abc$23348$new_n3433 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3435 xv[10][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21002 +001 1 +011 1 +110 1 +111 1 +.names xv[9][1] yv[9][11] ph[9][19] xv[9][0] yv[9][10] $abc$23348$new_n3435 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[9][0] yv[9][10] xv[10][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21004 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[10][18] $abc$23348$new_n3438 ph[11][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21006 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[10][19] ph[10][16] ph[10][17] $abc$23348$new_n3445 $abc$23348$new_n3439 $abc$23348$new_n3438 +00000 1 +00001 1 +11101 1 +.names ph[10][14] ph[10][15] $abc$23348$new_n3440 $abc$23348$new_n3439 +111 1 +.names ph[10][13] $abc$23348$new_n3441 $abc$23348$new_n3440 +11 1 +.names ph[10][9] ph[10][10] ph[10][11] ph[10][12] $abc$23348$new_n3442 $abc$23348$new_n3441 +11111 1 +.names ph[10][8] ph[10][7] $abc$23348$new_n3443 ph[10][6] $abc$23348$new_n3442 +1101 1 +1110 1 +1111 1 +.names ph[10][5] $abc$23348$new_n3444 $abc$23348$new_n3443 +10 1 +.names ph[10][4] ph[10][2] ph[10][3] ph[10][0] ph[10][1] $abc$23348$new_n3444 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names ph[10][19] $abc$23348$new_n3446 ph[10][14] ph[10][15] ph[10][13] $abc$23348$new_n3445 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$23348$new_n3447 ph[10][9] ph[10][10] ph[10][11] ph[10][12] $abc$23348$new_n3446 +10000 1 +.names ph[10][8] ph[10][7] $abc$23348$new_n3448 ph[10][6] $abc$23348$new_n3447 +0000 1 +0010 1 +0011 1 +.names ph[10][5] $abc$23348$new_n3449 $abc$23348$new_n3448 +00 1 +.names ph[10][4] ph[10][2] ph[10][3] ph[10][0] ph[10][1] $abc$23348$new_n3449 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3451 ph[11][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$21008 +001 1 +011 1 +110 1 +111 1 +.names ph[10][17] ph[10][19] ph[10][16] $abc$23348$new_n3445 $abc$23348$new_n3439 $abc$23348$new_n3451 +00000 1 +00001 1 +01101 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3453 ph[11][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21010 +001 1 +011 1 +110 1 +111 1 +.names ph[10][16] $abc$23348$new_n3445 ph[10][19] $abc$23348$new_n3439 $abc$23348$new_n3453 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3458 ph[11][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21014 +001 1 +011 1 +110 1 +111 1 +.names ph[10][19] ph[10][14] ph[10][13] $abc$23348$new_n3446 $abc$23348$new_n3441 $abc$23348$new_n3458 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$23348$new_n3460 ph[11][13] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$21016 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[10][13] ph[10][19] $abc$23348$new_n3446 $abc$23348$new_n3441 $abc$23348$new_n3460 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3462 ph[11][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21018 +001 1 +011 1 +110 1 +111 1 +.names ph[10][10] ph[10][12] ph[10][11] $abc$23348$new_n3465 $abc$23348$new_n3463 $abc$23348$new_n3462 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[10][9] $abc$23348$new_n3464 $abc$23348$new_n3463 +11 1 +.names ph[10][19] $abc$23348$new_n3442 $abc$23348$new_n3464 +11 1 +.names $abc$23348$new_n3466 ph[10][9] $abc$23348$new_n3465 +10 1 +.names $abc$23348$new_n3447 ph[10][19] $abc$23348$new_n3466 +10 1 +.names i_ce $abc$23348$new_n3468 ph[11][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21020 +001 1 +011 1 +110 1 +111 1 +.names ph[10][11] ph[10][10] $abc$23348$new_n3465 $abc$23348$new_n3463 $abc$23348$new_n3468 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[10][10] $abc$23348$new_n3465 $abc$23348$new_n3463 ph[11][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21022 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[10][9] $abc$23348$new_n3466 $abc$23348$new_n3464 ph[11][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21024 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3472 ph[10][8] ph[11][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21026 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[10][19] ph[10][6] ph[10][7] $abc$23348$new_n3443 $abc$23348$new_n3448 $abc$23348$new_n3472 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3474 ph[11][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21028 +001 1 +011 1 +110 1 +111 1 +.names ph[10][7] ph[10][19] ph[10][6] $abc$23348$new_n3448 $abc$23348$new_n3443 $abc$23348$new_n3474 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$23348$new_n3476 ph[11][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21030 +001 1 +011 1 +110 1 +111 1 +.names ph[10][6] ph[10][19] ph[10][5] $abc$23348$new_n3449 $abc$23348$new_n3444 $abc$23348$new_n3476 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3478 ph[11][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21032 +001 1 +011 1 +100 1 +101 1 +.names ph[10][5] ph[10][19] $abc$23348$new_n3449 $abc$23348$new_n3444 $abc$23348$new_n3478 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[10][4] $abc$23348$new_n3480 ph[11][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21034 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[10][19] ph[10][0] ph[10][1] ph[10][2] ph[10][3] $abc$23348$new_n3480 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3482 ph[11][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21036 +001 1 +011 1 +110 1 +111 1 +.names ph[10][19] ph[10][3] ph[10][0] ph[10][1] ph[10][2] $abc$23348$new_n3482 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3484 ph[11][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21038 +001 1 +011 1 +100 1 +101 1 +.names ph[10][2] ph[10][19] ph[10][0] ph[10][1] $abc$23348$new_n3484 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[10][19] ph[10][0] ph[10][1] ph[11][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21040 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[10][0] ph[11][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21042 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[10][15] yv[10][14] $abc$23348$new_n3488 yv[11][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21044 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] $abc$23348$new_n3489 $abc$23348$new_n3501 $abc$23348$new_n3488 +000 1 +001 1 +101 1 +111 1 +.names xv[10][15] $abc$23348$new_n3490 yv[10][12] yv[10][13] $abc$23348$new_n3489 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$23348$new_n3496 $abc$23348$new_n3491 $abc$23348$new_n3499 $abc$23348$new_n3498 $abc$23348$new_n3500 $abc$23348$new_n3490 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names yv[10][8] xv[10][15] yv[10][6] yv[10][7] $abc$23348$new_n3492 $abc$23348$new_n3491 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[10][15] yv[10][4] yv[10][5] $abc$23348$new_n3493 $abc$23348$new_n3492 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[10][14] yv[10][3] $abc$23348$new_n3494 $abc$23348$new_n3493 +010 1 +100 1 +110 1 +111 1 +.names xv[10][13] yv[10][2] $abc$23348$new_n3495 $abc$23348$new_n3494 +000 1 +001 1 +011 1 +101 1 +.names xv[10][11] yv[10][0] xv[10][12] yv[10][1] $abc$23348$new_n3495 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[10][15] $abc$23348$new_n3497 yv[10][10] yv[10][11] $abc$23348$new_n3496 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names yv[10][8] yv[10][9] $abc$23348$new_n3497 +00 1 +.names xv[10][15] yv[10][9] $abc$23348$new_n3498 +00 1 +11 1 +.names xv[10][15] yv[10][11] $abc$23348$new_n3499 +00 1 +11 1 +.names xv[10][15] yv[10][10] $abc$23348$new_n3500 +00 1 +11 1 +.names xv[10][15] $abc$23348$new_n3502 yv[10][12] yv[10][13] $abc$23348$new_n3501 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[10][15] $abc$23348$new_n3511 $abc$23348$new_n3498 $abc$23348$new_n3510 $abc$23348$new_n3503 $abc$23348$new_n3502 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[10][15] yv[10][6] yv[10][7] $abc$23348$new_n3504 $abc$23348$new_n3508 $abc$23348$new_n3503 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3505 xv[10][15] yv[10][5] $abc$23348$new_n3504 +100 1 +111 1 +.names xv[10][14] yv[10][3] xv[10][15] yv[10][4] $abc$23348$new_n3506 $abc$23348$new_n3505 +00001 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +11001 1 +11111 1 +.names yv[10][2] xv[10][13] $abc$23348$new_n3507 $abc$23348$new_n3506 +001 1 +100 1 +101 1 +111 1 +.names xv[10][11] xv[10][12] yv[10][0] yv[10][1] $abc$23348$new_n3507 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[10][4] yv[10][5] $abc$23348$new_n3508 +00 1 +.names $abc$23348$new_n3500 $abc$23348$new_n3499 $abc$23348$new_n3510 +11 1 +.names xv[10][15] yv[10][8] $abc$23348$new_n3511 +00 1 +11 1 +.names i_ce xv[10][15] yv[10][13] $abc$23348$new_n3513 yv[11][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21046 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] xv[10][15] yv[10][12] $abc$23348$new_n3502 $abc$23348$new_n3490 $abc$23348$new_n3513 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3515 yv[11][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21048 +001 1 +011 1 +110 1 +111 1 +.names ph[10][19] xv[10][15] yv[10][12] $abc$23348$new_n3502 $abc$23348$new_n3490 $abc$23348$new_n3515 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4370 $abc$23348$new_n3499 yv[11][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21050 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n4372 $abc$23348$new_n3500 yv[11][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21052 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3525 $abc$23348$new_n3498 yv[11][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21054 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[10][19] xv[10][15] yv[10][8] $abc$23348$new_n3503 $abc$23348$new_n3526 $abc$23348$new_n3525 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[10][15] $abc$23348$new_n3492 yv[10][6] yv[10][7] $abc$23348$new_n3526 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3528 yv[11][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21056 +001 1 +011 1 +100 1 +101 1 +.names ph[10][19] $abc$23348$new_n3511 $abc$23348$new_n3503 $abc$23348$new_n3526 $abc$23348$new_n3528 +0000 1 +0010 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[10][15] yv[10][7] $abc$23348$new_n3530 yv[11][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21058 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][6] ph[10][19] $abc$23348$new_n3531 xv[10][15] $abc$23348$new_n3492 $abc$23348$new_n3530 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names ph[10][19] $abc$23348$new_n3504 xv[10][15] $abc$23348$new_n3508 $abc$23348$new_n3531 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3533 yv[11][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21060 +001 1 +011 1 +110 1 +111 1 +.names xv[10][15] yv[10][6] $abc$23348$new_n3531 $abc$23348$new_n3492 ph[10][19] $abc$23348$new_n3533 +00000 1 +00001 1 +00011 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names i_ce xv[10][15] yv[10][5] $abc$23348$new_n3535 yv[11][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21062 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] xv[10][15] yv[10][4] $abc$23348$new_n3505 $abc$23348$new_n3493 $abc$23348$new_n3535 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_ce xv[10][15] yv[10][4] $abc$23348$new_n3537 yv[11][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21064 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] xv[10][14] yv[10][3] $abc$23348$new_n3506 $abc$23348$new_n3494 $abc$23348$new_n3537 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[10][14] yv[10][3] $abc$23348$new_n3539 yv[11][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21066 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] $abc$23348$new_n3494 $abc$23348$new_n3506 $abc$23348$new_n3539 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[10][13] yv[10][2] $abc$23348$new_n3541 yv[11][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21068 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] $abc$23348$new_n3495 $abc$23348$new_n3507 $abc$23348$new_n3541 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3543 yv[11][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21070 +001 1 +011 1 +110 1 +111 1 +.names xv[10][12] yv[10][1] ph[10][19] yv[10][0] xv[10][11] $abc$23348$new_n3543 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[10][11] yv[10][0] yv[11][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21072 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[10][15] xv[10][14] $abc$23348$new_n3546 xv[11][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21074 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] $abc$23348$new_n3547 $abc$23348$new_n3557 $abc$23348$new_n3546 +000 1 +001 1 +101 1 +111 1 +.names yv[10][15] $abc$23348$new_n3548 xv[10][12] xv[10][13] $abc$23348$new_n3547 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[10][15] xv[10][10] xv[10][11] $abc$23348$new_n3549 $abc$23348$new_n3556 $abc$23348$new_n3548 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3555 $abc$23348$new_n3554 $abc$23348$new_n3550 $abc$23348$new_n3549 +000 1 +.names yv[10][15] $abc$23348$new_n3551 xv[10][6] xv[10][7] $abc$23348$new_n3550 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[10][15] $abc$23348$new_n3552 xv[10][4] xv[10][5] $abc$23348$new_n3551 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[10][13] xv[10][2] xv[10][3] yv[10][14] $abc$23348$new_n3553 $abc$23348$new_n3552 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[10][11] xv[10][0] xv[10][1] yv[10][12] $abc$23348$new_n3553 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[10][15] xv[10][9] $abc$23348$new_n3554 +01 1 +10 1 +.names yv[10][15] xv[10][8] $abc$23348$new_n3555 +01 1 +10 1 +.names xv[10][8] xv[10][9] $abc$23348$new_n3556 +00 1 +.names yv[10][15] $abc$23348$new_n3558 xv[10][12] xv[10][13] $abc$23348$new_n3557 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[10][15] $abc$23348$new_n3566 $abc$23348$new_n3555 $abc$23348$new_n3554 $abc$23348$new_n3559 $abc$23348$new_n3558 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +11111 1 +.names yv[10][15] xv[10][6] xv[10][7] $abc$23348$new_n3560 $abc$23348$new_n3564 $abc$23348$new_n3559 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names $abc$23348$new_n3561 yv[10][15] xv[10][5] $abc$23348$new_n3560 +101 1 +110 1 +.names yv[10][15] xv[10][4] xv[10][3] yv[10][14] $abc$23348$new_n3562 $abc$23348$new_n3561 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +.names xv[10][2] yv[10][13] $abc$23348$new_n3563 $abc$23348$new_n3562 +000 1 +001 1 +011 1 +101 1 +.names xv[10][0] yv[10][11] xv[10][1] yv[10][12] $abc$23348$new_n3563 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[10][4] xv[10][5] $abc$23348$new_n3564 +00 1 +.names yv[10][15] xv[10][10] xv[10][11] $abc$23348$new_n3566 +011 1 +100 1 +.names i_ce yv[10][15] xv[10][13] $abc$23348$new_n3568 xv[11][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21076 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][12] yv[10][15] $abc$23348$new_n3558 $abc$23348$new_n3548 $abc$23348$new_n3568 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3570 xv[11][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21078 +001 1 +011 1 +100 1 +101 1 +.names ph[10][19] yv[10][15] xv[10][12] $abc$23348$new_n3558 $abc$23348$new_n3548 $abc$23348$new_n3570 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[10][15] xv[10][11] $abc$23348$new_n3572 xv[11][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21080 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][10] yv[10][15] $abc$23348$new_n3574 $abc$23348$new_n3573 $abc$23348$new_n3572 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names yv[10][15] $abc$23348$new_n3559 xv[10][8] xv[10][9] $abc$23348$new_n3573 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$23348$new_n3549 $abc$23348$new_n3556 yv[10][15] $abc$23348$new_n3574 +001 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3576 xv[11][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21082 +001 1 +011 1 +110 1 +111 1 +.names yv[10][15] xv[10][10] ph[10][19] $abc$23348$new_n3574 $abc$23348$new_n3573 $abc$23348$new_n3576 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3578 $abc$23348$new_n3554 xv[11][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21084 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[10][19] xv[10][8] yv[10][15] $abc$23348$new_n3550 $abc$23348$new_n3559 $abc$23348$new_n3578 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n3580 xv[11][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21086 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n3555 ph[10][19] $abc$23348$new_n3550 $abc$23348$new_n3559 $abc$23348$new_n3580 +0000 1 +0001 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names i_ce yv[10][15] xv[10][7] $abc$23348$new_n3582 xv[11][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21088 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][6] yv[10][15] $abc$23348$new_n3551 $abc$23348$new_n3583 $abc$23348$new_n3582 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3560 $abc$23348$new_n3564 yv[10][15] $abc$23348$new_n3583 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3585 xv[11][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21090 +001 1 +011 1 +100 1 +101 1 +.names yv[10][15] xv[10][6] ph[10][19] $abc$23348$new_n3551 $abc$23348$new_n3583 $abc$23348$new_n3585 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[10][15] xv[10][5] $abc$23348$new_n3587 xv[11][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21092 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][4] yv[10][15] $abc$23348$new_n3552 $abc$23348$new_n3561 $abc$23348$new_n3587 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names i_ce yv[10][15] xv[10][4] $abc$23348$new_n3589 xv[11][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21094 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][3] yv[10][14] $abc$23348$new_n3562 $abc$23348$new_n3552 $abc$23348$new_n3589 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[10][3] yv[10][14] $abc$23348$new_n3591 xv[11][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21096 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][2] yv[10][13] $abc$23348$new_n3563 $abc$23348$new_n3553 $abc$23348$new_n3591 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[10][2] yv[10][13] $abc$23348$new_n3593 xv[11][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21098 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] $abc$23348$new_n3553 $abc$23348$new_n3563 $abc$23348$new_n3593 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3595 xv[11][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21100 +001 1 +011 1 +110 1 +111 1 +.names xv[10][1] yv[10][12] ph[10][19] xv[10][0] yv[10][11] $abc$23348$new_n3595 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[10][0] yv[10][11] xv[11][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21102 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3598 ph[12][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21104 +001 1 +011 1 +100 1 +101 1 +.names ph[11][18] ph[11][19] ph[11][17] $abc$23348$new_n3605 $abc$23348$new_n3599 $abc$23348$new_n3598 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names $abc$23348$new_n3600 ph[11][16] $abc$23348$new_n3599 +10 1 +.names $abc$23348$new_n3601 ph[11][13] ph[11][14] ph[11][15] $abc$23348$new_n3600 +1000 1 +.names $abc$23348$new_n3602 $abc$23348$new_n3604 ph[11][12] $abc$23348$new_n3601 +110 1 +.names $abc$23348$new_n3603 ph[11][10] ph[11][11] $abc$23348$new_n3602 +100 1 +.names ph[11][7] ph[11][8] ph[11][9] $abc$23348$new_n3603 +000 1 +.names ph[11][6] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3604 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[11][16] $abc$23348$new_n3606 $abc$23348$new_n3605 +11 1 +.names ph[11][13] ph[11][14] ph[11][15] $abc$23348$new_n3607 $abc$23348$new_n3606 +1111 1 +.names ph[11][12] $abc$23348$new_n3608 $abc$23348$new_n3607 +11 1 +.names $abc$23348$new_n3609 ph[11][6] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3608 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[11][7] ph[11][8] ph[11][9] ph[11][10] ph[11][11] $abc$23348$new_n3609 +11111 1 +.names i_ce $abc$23348$new_n3611 ph[12][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$21106 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] ph[11][17] $abc$23348$new_n3605 $abc$23348$new_n3599 $abc$23348$new_n3611 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3613 ph[12][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21108 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] ph[11][16] $abc$23348$new_n3606 $abc$23348$new_n3600 $abc$23348$new_n3613 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[11][15] $abc$23348$new_n3615 ph[12][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21110 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[11][19] ph[11][13] ph[11][14] $abc$23348$new_n3601 $abc$23348$new_n3607 $abc$23348$new_n3615 +00010 1 +00011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n3620 ph[12][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21114 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] ph[11][13] $abc$23348$new_n3607 $abc$23348$new_n3601 $abc$23348$new_n3620 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3622 ph[12][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21116 +001 1 +011 1 +110 1 +111 1 +.names ph[11][12] ph[11][19] $abc$23348$new_n3604 $abc$23348$new_n3602 $abc$23348$new_n3608 $abc$23348$new_n3622 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3624 ph[12][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21118 +001 1 +011 1 +110 1 +111 1 +.names ph[11][11] ph[11][10] $abc$23348$new_n3603 $abc$23348$new_n3625 $abc$23348$new_n3626 $abc$23348$new_n3624 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$23348$new_n3604 ph[11][19] $abc$23348$new_n3625 +10 1 +.names ph[11][7] ph[11][8] ph[11][9] $abc$23348$new_n3627 $abc$23348$new_n3626 +1111 1 +.names ph[11][19] ph[11][6] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3627 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3629 ph[11][10] ph[12][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21120 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$23348$new_n3626 $abc$23348$new_n3625 $abc$23348$new_n3603 $abc$23348$new_n3629 +000 1 +001 1 +010 1 +.names i_ce ph[12][9] $abc$23348$new_n3631 $abc$23348$new_n3626 $abc$23348$auto$rtlil.cc:2693:MuxGate$21122 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names ph[11][9] ph[11][7] ph[11][8] $abc$23348$new_n3625 $abc$23348$new_n3627 $abc$23348$new_n3631 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +.names i_ce $abc$23348$new_n3633 ph[12][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21124 +001 1 +011 1 +110 1 +111 1 +.names ph[11][7] ph[11][8] $abc$23348$new_n3627 $abc$23348$new_n3625 $abc$23348$new_n3633 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[11][7] $abc$23348$new_n3627 $abc$23348$new_n3625 ph[12][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21126 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3636 ph[12][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21128 +001 1 +011 1 +110 1 +111 1 +.names ph[11][6] ph[11][19] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n3638 ph[12][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21130 +001 1 +011 1 +100 1 +101 1 +.names ph[11][19] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3638 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[11][19] ph[11][3] ph[11][4] ph[12][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21132 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[11][3] ph[12][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21134 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[11][2] ph[12][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21136 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[11][1] ph[12][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21138 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[11][0] ph[12][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21140 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[11][15] yv[11][14] $abc$23348$new_n3645 yv[12][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21142 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] $abc$23348$new_n3646 $abc$23348$new_n3653 $abc$23348$new_n3645 +000 1 +001 1 +101 1 +111 1 +.names xv[11][15] $abc$23348$new_n3647 yv[11][12] yv[11][13] $abc$23348$new_n3646 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3648 yv[11][10] yv[11][11] $abc$23348$new_n3647 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3649 yv[11][8] yv[11][9] $abc$23348$new_n3648 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3650 yv[11][6] yv[11][7] $abc$23348$new_n3649 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3651 yv[11][3] yv[11][4] yv[11][5] $abc$23348$new_n3650 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[11][14] yv[11][2] $abc$23348$new_n3652 $abc$23348$new_n3651 +000 1 +001 1 +011 1 +101 1 +.names xv[11][12] yv[11][0] xv[11][13] yv[11][1] $abc$23348$new_n3652 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3654 yv[11][11] yv[11][12] yv[11][13] $abc$23348$new_n3653 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[11][15] yv[11][9] yv[11][10] $abc$23348$new_n3655 $abc$23348$new_n3654 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names yv[11][8] xv[11][15] $abc$23348$new_n4376 $abc$23348$new_n3655 +000 1 +100 1 +101 1 +110 1 +.names yv[11][2] xv[11][14] $abc$23348$new_n3659 $abc$23348$new_n3658 +001 1 +100 1 +101 1 +111 1 +.names xv[11][12] xv[11][13] yv[11][0] yv[11][1] $abc$23348$new_n3659 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[11][15] yv[11][13] $abc$23348$new_n3662 yv[12][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21144 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] yv[11][12] xv[11][15] $abc$23348$new_n3647 $abc$23348$new_n3663 $abc$23348$new_n3662 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names xv[11][15] yv[11][11] $abc$23348$new_n3654 $abc$23348$new_n3663 +001 1 +100 1 +101 1 +111 1 +.names i_ce xv[11][15] yv[11][12] $abc$23348$new_n3665 yv[12][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21146 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] $abc$23348$new_n3663 $abc$23348$new_n3647 $abc$23348$new_n3665 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[11][15] yv[11][11] $abc$23348$new_n3667 yv[12][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21148 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] yv[11][10] xv[11][15] $abc$23348$new_n3648 $abc$23348$new_n3668 $abc$23348$new_n3667 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names xv[11][15] yv[11][9] $abc$23348$new_n3655 $abc$23348$new_n3668 +000 1 +100 1 +101 1 +110 1 +.names i_ce $abc$23348$new_n3670 yv[12][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21150 +001 1 +011 1 +110 1 +111 1 +.names xv[11][15] yv[11][10] ph[11][19] $abc$23348$new_n3648 $abc$23348$new_n3668 $abc$23348$new_n3670 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[11][15] yv[11][9] $abc$23348$new_n3672 yv[12][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21152 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] xv[11][15] yv[11][8] $abc$23348$new_n4376 $abc$23348$new_n3649 $abc$23348$new_n3672 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3674 yv[12][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21154 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] xv[11][15] yv[11][8] $abc$23348$new_n4376 $abc$23348$new_n3649 $abc$23348$new_n3674 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[11][15] yv[11][7] $abc$23348$new_n3676 yv[12][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21156 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][6] ph[11][19] $abc$23348$new_n3677 xv[11][15] $abc$23348$new_n3650 $abc$23348$new_n3676 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names ph[11][19] xv[11][15] yv[11][5] $abc$23348$new_n3678 yv[11][4] $abc$23348$new_n3677 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names xv[11][15] yv[11][4] yv[11][3] $abc$23348$new_n3658 $abc$23348$new_n3678 +0001 1 +0010 1 +0011 1 +1111 1 +.names i_ce $abc$23348$new_n3680 yv[12][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21158 +001 1 +011 1 +100 1 +101 1 +.names xv[11][15] yv[11][6] $abc$23348$new_n3677 $abc$23348$new_n3650 ph[11][19] $abc$23348$new_n3680 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10011 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[11][15] yv[11][5] $abc$23348$new_n3682 yv[12][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21160 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] yv[11][4] $abc$23348$new_n3685 xv[11][15] $abc$23348$new_n3682 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[11][15] yv[11][4] $abc$23348$new_n3685 yv[12][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21162 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] xv[11][15] yv[11][3] $abc$23348$new_n3658 $abc$23348$new_n3651 $abc$23348$new_n3685 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n3687 yv[12][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21164 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] xv[11][15] yv[11][3] $abc$23348$new_n3658 $abc$23348$new_n3651 $abc$23348$new_n3687 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[11][14] yv[11][2] $abc$23348$new_n3689 yv[12][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21166 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] $abc$23348$new_n3652 $abc$23348$new_n3659 $abc$23348$new_n3689 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$23348$new_n3691 yv[12][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21168 +001 1 +011 1 +110 1 +111 1 +.names xv[11][13] yv[11][1] ph[11][19] yv[11][0] xv[11][12] $abc$23348$new_n3691 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[11][12] yv[11][0] yv[12][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21170 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3694 xv[12][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21172 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][14] $abc$23348$new_n3702 $abc$23348$new_n3695 $abc$23348$new_n3694 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][15] $abc$23348$new_n3696 xv[11][12] xv[11][13] $abc$23348$new_n3695 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[11][15] $abc$23348$new_n3697 xv[11][10] xv[11][11] $abc$23348$new_n3696 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[11][15] $abc$23348$new_n3698 xv[11][8] xv[11][9] $abc$23348$new_n3697 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[11][15] $abc$23348$new_n3699 xv[11][6] xv[11][7] $abc$23348$new_n3698 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[11][15] $abc$23348$new_n3700 xv[11][3] xv[11][4] xv[11][5] $abc$23348$new_n3699 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[11][14] xv[11][2] $abc$23348$new_n3701 $abc$23348$new_n3700 +001 1 +100 1 +101 1 +111 1 +.names yv[11][12] xv[11][0] xv[11][1] yv[11][13] $abc$23348$new_n3701 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[11][15] $abc$23348$new_n3703 xv[11][12] xv[11][13] $abc$23348$new_n3702 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[11][15] $abc$23348$new_n3704 xv[11][10] xv[11][11] $abc$23348$new_n3703 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[11][15] $abc$23348$new_n3705 xv[11][8] xv[11][9] $abc$23348$new_n3704 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[11][15] xv[11][6] xv[11][7] $abc$23348$new_n3706 $abc$23348$new_n3709 $abc$23348$new_n3705 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[11][4] xv[11][5] yv[11][15] xv[11][3] $abc$23348$new_n3707 $abc$23348$new_n3706 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[11][2] yv[11][14] $abc$23348$new_n3708 $abc$23348$new_n3707 +000 1 +001 1 +011 1 +101 1 +.names xv[11][0] yv[11][12] xv[11][1] yv[11][13] $abc$23348$new_n3708 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[11][4] xv[11][5] $abc$23348$new_n3709 +00 1 +.names i_ce yv[11][15] xv[11][13] $abc$23348$new_n3711 xv[12][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21174 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][12] yv[11][15] $abc$23348$new_n3703 $abc$23348$new_n3696 $abc$23348$new_n3711 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3713 xv[12][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21176 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][12] $abc$23348$new_n3703 $abc$23348$new_n3696 $abc$23348$new_n3713 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[11][15] xv[11][11] $abc$23348$new_n3715 xv[12][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21178 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][10] yv[11][15] $abc$23348$new_n3704 $abc$23348$new_n3697 $abc$23348$new_n3715 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3717 xv[12][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21180 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][10] $abc$23348$new_n3704 $abc$23348$new_n3697 $abc$23348$new_n3717 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[11][15] xv[11][9] $abc$23348$new_n3719 xv[12][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21182 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][8] yv[11][15] $abc$23348$new_n3705 $abc$23348$new_n3698 $abc$23348$new_n3719 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3721 xv[12][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21184 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][8] $abc$23348$new_n3705 $abc$23348$new_n3698 $abc$23348$new_n3721 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[11][15] xv[11][7] $abc$23348$new_n3723 xv[12][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21186 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][6] yv[11][15] $abc$23348$new_n3699 $abc$23348$new_n3724 $abc$23348$new_n3723 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3706 $abc$23348$new_n3709 yv[11][15] $abc$23348$new_n3724 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3726 xv[12][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21188 +001 1 +011 1 +100 1 +101 1 +.names yv[11][15] xv[11][6] ph[11][19] $abc$23348$new_n3699 $abc$23348$new_n3724 $abc$23348$new_n3726 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[11][15] xv[11][5] $abc$23348$new_n3728 xv[12][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21190 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] yv[11][15] xv[11][4] $abc$23348$new_n3730 $abc$23348$new_n3729 $abc$23348$new_n3728 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[11][15] xv[11][3] $abc$23348$new_n3700 $abc$23348$new_n3729 +001 1 +100 1 +101 1 +111 1 +.names yv[11][15] xv[11][3] $abc$23348$new_n3707 $abc$23348$new_n3730 +010 1 +100 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n3732 xv[12][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21192 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][4] $abc$23348$new_n3730 $abc$23348$new_n3729 $abc$23348$new_n3732 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3734 xv[12][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21194 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][3] $abc$23348$new_n3707 $abc$23348$new_n3700 $abc$23348$new_n3734 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[11][2] yv[11][14] $abc$23348$new_n3736 xv[12][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21196 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] $abc$23348$new_n3701 $abc$23348$new_n3708 $abc$23348$new_n3736 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3738 xv[12][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21198 +001 1 +011 1 +110 1 +111 1 +.names xv[11][1] yv[11][13] ph[11][19] xv[11][0] yv[11][12] $abc$23348$new_n3738 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[11][0] yv[11][12] xv[12][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21200 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3741 ph[13][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21202 +001 1 +011 1 +100 1 +101 1 +.names ph[12][18] $abc$23348$new_n3746 ph[12][19] $abc$23348$new_n3742 ph[12][17] $abc$23348$new_n3741 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$23348$new_n3743 ph[12][14] ph[12][15] ph[12][16] $abc$23348$new_n3742 +1000 1 +.names $abc$23348$new_n3744 ph[12][10] ph[12][11] ph[12][12] ph[12][13] $abc$23348$new_n3743 +10000 1 +.names $abc$23348$new_n3745 ph[12][6] ph[12][7] ph[12][8] ph[12][9] $abc$23348$new_n3744 +10000 1 +.names ph[12][5] ph[12][4] ph[12][2] ph[12][3] $abc$23348$new_n3745 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[12][19] $abc$23348$new_n3747 ph[12][17] $abc$23348$new_n3746 +100 1 +101 1 +110 1 +.names ph[12][13] ph[12][16] $abc$23348$new_n3750 $abc$23348$new_n3749 $abc$23348$new_n3748 $abc$23348$new_n3747 +11111 1 +.names ph[12][6] ph[12][7] ph[12][8] ph[12][14] ph[12][15] $abc$23348$new_n3748 +11111 1 +.names ph[12][5] ph[12][4] ph[12][2] ph[12][3] $abc$23348$new_n3749 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[12][9] ph[12][10] ph[12][11] ph[12][12] $abc$23348$new_n3750 +1111 1 +.names i_ce $abc$23348$new_n3752 ph[13][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$21204 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] ph[12][17] $abc$23348$new_n3747 $abc$23348$new_n3742 $abc$23348$new_n3752 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3754 ph[13][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21206 +001 1 +011 1 +100 1 +101 1 +.names ph[12][16] ph[12][14] ph[12][15] $abc$23348$new_n3760 $abc$23348$new_n3755 $abc$23348$new_n3754 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names $abc$23348$new_n3756 ph[12][10] ph[12][11] ph[12][12] ph[12][13] $abc$23348$new_n3755 +10000 1 +.names $abc$23348$new_n3757 ph[12][8] ph[12][9] $abc$23348$new_n3756 +100 1 +.names $abc$23348$new_n3758 ph[12][7] $abc$23348$new_n3757 +10 1 +.names $abc$23348$new_n3759 ph[12][6] $abc$23348$new_n3758 +10 1 +.names $abc$23348$new_n3745 ph[12][19] $abc$23348$new_n3759 +10 1 +.names ph[12][8] ph[12][13] $abc$23348$new_n3750 $abc$23348$new_n3761 $abc$23348$new_n3760 +1111 1 +.names ph[12][7] $abc$23348$new_n3762 $abc$23348$new_n3761 +11 1 +.names ph[12][6] $abc$23348$new_n3763 $abc$23348$new_n3762 +11 1 +.names ph[12][19] $abc$23348$new_n3749 $abc$23348$new_n3763 +11 1 +.names i_ce $abc$23348$new_n3765 ph[13][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21208 +001 1 +011 1 +100 1 +101 1 +.names ph[12][14] ph[12][15] $abc$23348$new_n3760 $abc$23348$new_n3755 $abc$23348$new_n3765 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[12][14] $abc$23348$new_n3760 $abc$23348$new_n3755 ph[13][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21210 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3768 ph[12][13] ph[13][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21212 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[12][10] ph[12][11] ph[12][12] $abc$23348$new_n3769 $abc$23348$new_n3756 $abc$23348$new_n3768 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][8] ph[12][9] $abc$23348$new_n3761 $abc$23348$new_n3769 +111 1 +.names i_ce $abc$23348$new_n3771 ph[13][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21214 +001 1 +011 1 +110 1 +111 1 +.names ph[12][10] ph[12][12] ph[12][11] $abc$23348$new_n3756 $abc$23348$new_n3769 $abc$23348$new_n3771 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3773 ph[13][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21216 +001 1 +011 1 +100 1 +101 1 +.names ph[12][11] ph[12][10] $abc$23348$new_n3756 $abc$23348$new_n3769 $abc$23348$new_n3773 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[12][10] $abc$23348$new_n3756 $abc$23348$new_n3769 ph[13][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21218 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3776 ph[12][9] ph[13][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21220 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[12][8] $abc$23348$new_n3761 $abc$23348$new_n3757 $abc$23348$new_n3776 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[12][8] $abc$23348$new_n3757 $abc$23348$new_n3761 ph[13][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21222 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[12][7] $abc$23348$new_n3758 $abc$23348$new_n3762 ph[13][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21224 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[12][6] $abc$23348$new_n3759 $abc$23348$new_n3763 ph[13][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21226 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3781 ph[13][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21228 +001 1 +011 1 +110 1 +111 1 +.names ph[12][5] ph[12][19] ph[12][4] ph[12][2] ph[12][3] $abc$23348$new_n3781 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n3783 ph[13][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21230 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] ph[12][4] ph[12][2] ph[12][3] $abc$23348$new_n3783 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[12][19] ph[12][2] ph[12][3] ph[13][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21232 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[12][2] ph[13][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21234 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[12][1] ph[13][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21236 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[12][0] ph[13][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21238 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[12][15] yv[12][14] $abc$23348$new_n3789 yv[13][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21240 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[12][19] $abc$23348$new_n3790 $abc$23348$new_n3797 $abc$23348$new_n3789 +000 1 +001 1 +101 1 +111 1 +.names xv[12][15] $abc$23348$new_n3791 yv[12][12] yv[12][13] $abc$23348$new_n3790 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][15] yv[12][11] $abc$23348$new_n3792 $abc$23348$new_n3791 +000 1 +001 1 +011 1 +101 1 +.names xv[12][15] $abc$23348$new_n3793 yv[12][8] yv[12][9] yv[12][10] $abc$23348$new_n3792 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[12][15] $abc$23348$new_n3794 yv[12][6] yv[12][7] $abc$23348$new_n3793 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][15] $abc$23348$new_n3795 yv[12][4] yv[12][5] $abc$23348$new_n3794 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][15] $abc$23348$new_n3796 yv[12][2] yv[12][3] $abc$23348$new_n3795 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][13] yv[12][0] xv[12][14] yv[12][1] $abc$23348$new_n3796 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[12][15] yv[12][13] $abc$23348$new_n3798 $abc$23348$new_n3797 +000 1 +100 1 +101 1 +110 1 +.names yv[12][12] xv[12][15] $abc$23348$new_n3799 $abc$23348$new_n3798 +000 1 +100 1 +101 1 +110 1 +.names xv[12][15] yv[12][10] yv[12][11] $abc$23348$new_n3800 $abc$23348$new_n3804 $abc$23348$new_n3799 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[12][15] yv[12][9] yv[12][8] yv[12][7] $abc$23348$new_n3801 $abc$23348$new_n3800 +00000 1 +00010 1 +00011 1 +11110 1 +.names xv[12][15] $abc$23348$new_n3802 yv[12][5] yv[12][6] $abc$23348$new_n3801 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[12][15] yv[12][2] yv[12][3] yv[12][4] $abc$23348$new_n3803 $abc$23348$new_n3802 +00000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[12][13] xv[12][14] yv[12][0] yv[12][1] $abc$23348$new_n3803 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[12][8] yv[12][9] $abc$23348$new_n3804 +00 1 +.names i_ce xv[12][15] yv[12][13] $abc$23348$new_n3806 yv[13][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21242 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n3798 yv[12][12] ph[12][19] $abc$23348$new_n3791 $abc$23348$new_n3806 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3808 yv[13][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21244 +001 1 +011 1 +110 1 +111 1 +.names ph[12][19] xv[12][15] yv[12][12] $abc$23348$new_n3799 $abc$23348$new_n3791 $abc$23348$new_n3808 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[12][15] yv[12][11] $abc$23348$new_n3810 yv[13][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21246 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][10] $abc$23348$new_n3811 $abc$23348$new_n3792 ph[12][19] $abc$23348$new_n3810 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names ph[12][19] $abc$23348$new_n3800 xv[12][15] $abc$23348$new_n3804 $abc$23348$new_n3811 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3813 yv[13][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21248 +001 1 +011 1 +110 1 +111 1 +.names xv[12][15] yv[12][10] $abc$23348$new_n3814 $abc$23348$new_n3811 $abc$23348$new_n3813 +0000 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names ph[12][19] xv[12][15] $abc$23348$new_n3793 yv[12][8] yv[12][9] $abc$23348$new_n3814 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names i_ce xv[12][15] yv[12][9] $abc$23348$new_n3816 yv[13][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21250 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] yv[12][8] xv[12][15] $abc$23348$new_n3817 $abc$23348$new_n3793 $abc$23348$new_n3816 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[12][15] yv[12][7] $abc$23348$new_n3801 $abc$23348$new_n3817 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3819 yv[13][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21252 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] xv[12][15] yv[12][8] $abc$23348$new_n3817 $abc$23348$new_n3793 $abc$23348$new_n3819 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[12][15] yv[12][7] $abc$23348$new_n3821 yv[13][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21254 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3801 $abc$23348$new_n3794 ph[12][19] yv[12][6] $abc$23348$new_n3821 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[12][15] yv[12][6] $abc$23348$new_n3823 yv[13][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21256 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n3794 ph[12][19] $abc$23348$new_n3802 yv[12][5] $abc$23348$new_n3823 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names i_ce xv[12][15] yv[12][5] $abc$23348$new_n3825 yv[13][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21258 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3802 $abc$23348$new_n3795 ph[12][19] yv[12][4] $abc$23348$new_n3825 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3827 yv[13][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21260 +001 1 +011 1 +110 1 +111 1 +.names ph[12][19] xv[12][15] yv[12][4] $abc$23348$new_n3828 $abc$23348$new_n3795 $abc$23348$new_n3827 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[12][15] yv[12][2] yv[12][3] $abc$23348$new_n3803 $abc$23348$new_n3828 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[12][15] yv[12][3] $abc$23348$new_n3830 yv[13][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21262 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] yv[12][2] xv[12][15] $abc$23348$new_n3803 $abc$23348$new_n3796 $abc$23348$new_n3830 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[12][15] yv[12][2] $abc$23348$new_n3832 yv[13][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21264 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] $abc$23348$new_n3796 $abc$23348$new_n3803 $abc$23348$new_n3832 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3834 yv[13][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21266 +001 1 +011 1 +110 1 +111 1 +.names xv[12][14] yv[12][1] ph[12][19] yv[12][0] xv[12][13] $abc$23348$new_n3834 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[12][13] yv[12][0] yv[13][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21268 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3837 xv[13][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21270 +001 1 +011 1 +110 1 +111 1 +.names ph[12][19] yv[12][15] xv[12][14] $abc$23348$new_n3845 $abc$23348$new_n3838 $abc$23348$new_n3837 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][15] $abc$23348$new_n3839 xv[12][12] xv[12][13] $abc$23348$new_n3838 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3840 xv[12][10] xv[12][11] $abc$23348$new_n3839 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3841 xv[12][8] xv[12][9] $abc$23348$new_n3840 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3842 xv[12][6] xv[12][7] $abc$23348$new_n3841 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3843 xv[12][4] xv[12][5] $abc$23348$new_n3842 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3844 xv[12][2] xv[12][3] $abc$23348$new_n3843 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][13] xv[12][0] xv[12][1] yv[12][14] $abc$23348$new_n3844 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[12][15] $abc$23348$new_n3846 xv[12][12] xv[12][13] $abc$23348$new_n3845 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[12][15] $abc$23348$new_n3860 xv[12][10] xv[12][11] $abc$23348$new_n3846 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[12][15] xv[12][6] xv[12][7] $abc$23348$new_n3849 $abc$23348$new_n3852 $abc$23348$new_n3848 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[12][4] xv[12][5] yv[12][15] xv[12][3] $abc$23348$new_n3850 $abc$23348$new_n3849 +00100 1 +00110 1 +00111 1 +11010 1 +.names yv[12][15] xv[12][2] $abc$23348$new_n3851 $abc$23348$new_n3850 +000 1 +001 1 +011 1 +101 1 +.names xv[12][0] yv[12][13] xv[12][1] yv[12][14] $abc$23348$new_n3851 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[12][4] xv[12][5] $abc$23348$new_n3852 +00 1 +.names i_ce yv[12][15] xv[12][13] $abc$23348$new_n3855 xv[13][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21272 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][12] yv[12][15] $abc$23348$new_n3846 $abc$23348$new_n3839 $abc$23348$new_n3855 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3857 xv[13][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21274 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] yv[12][15] xv[12][12] $abc$23348$new_n3846 $abc$23348$new_n3839 $abc$23348$new_n3857 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[12][15] xv[12][11] $abc$23348$new_n3859 xv[13][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21276 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][10] yv[12][15] $abc$23348$new_n3860 $abc$23348$new_n3840 $abc$23348$new_n3859 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names yv[12][15] $abc$23348$new_n3848 xv[12][8] xv[12][9] $abc$23348$new_n3860 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3862 xv[13][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21278 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] yv[12][15] xv[12][10] $abc$23348$new_n3860 $abc$23348$new_n3840 $abc$23348$new_n3862 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[12][15] xv[12][9] $abc$23348$new_n3864 xv[13][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21280 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][8] yv[12][15] $abc$23348$new_n3848 $abc$23348$new_n3841 $abc$23348$new_n3864 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3866 xv[13][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21282 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] yv[12][15] xv[12][8] $abc$23348$new_n3848 $abc$23348$new_n3841 $abc$23348$new_n3866 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[12][15] xv[12][7] $abc$23348$new_n3868 xv[13][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21284 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][6] yv[12][15] $abc$23348$new_n3842 $abc$23348$new_n3869 $abc$23348$new_n3868 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3849 $abc$23348$new_n3852 yv[12][15] $abc$23348$new_n3869 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3871 xv[13][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21286 +001 1 +011 1 +100 1 +101 1 +.names yv[12][15] xv[12][6] ph[12][19] $abc$23348$new_n3842 $abc$23348$new_n3869 $abc$23348$new_n3871 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[12][15] xv[12][5] $abc$23348$new_n3873 xv[13][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21288 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][4] yv[12][15] $abc$23348$new_n3843 $abc$23348$new_n3874 $abc$23348$new_n3873 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names yv[12][15] xv[12][3] $abc$23348$new_n3850 $abc$23348$new_n3874 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3876 xv[13][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21290 +001 1 +011 1 +100 1 +101 1 +.names yv[12][15] xv[12][4] ph[12][19] $abc$23348$new_n3843 $abc$23348$new_n3874 $abc$23348$new_n3876 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[12][15] xv[12][3] $abc$23348$new_n3878 xv[13][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21292 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[12][19] yv[12][15] xv[12][2] $abc$23348$new_n3851 $abc$23348$new_n3844 $abc$23348$new_n3878 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce yv[12][15] xv[12][2] $abc$23348$new_n3880 xv[13][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21294 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] $abc$23348$new_n3844 $abc$23348$new_n3851 $abc$23348$new_n3880 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3882 xv[13][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21296 +001 1 +011 1 +110 1 +111 1 +.names xv[12][1] yv[12][14] ph[12][19] xv[12][0] yv[12][13] $abc$23348$new_n3882 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[12][0] yv[12][13] xv[13][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21298 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[13][18] $abc$23348$new_n3890 $abc$23348$new_n3885 ph[14][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21300 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[13][19] $abc$23348$new_n3886 ph[13][17] $abc$23348$new_n3885 +000 1 +001 1 +011 1 +.names $abc$23348$new_n3887 ph[13][13] ph[13][14] ph[13][15] ph[13][16] $abc$23348$new_n3886 +10000 1 +.names $abc$23348$new_n3888 ph[13][9] ph[13][10] ph[13][11] ph[13][12] $abc$23348$new_n3887 +10000 1 +.names $abc$23348$new_n3889 ph[13][5] ph[13][6] ph[13][7] ph[13][8] $abc$23348$new_n3888 +10000 1 +.names ph[13][4] ph[13][3] ph[13][1] ph[13][2] $abc$23348$new_n3889 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[13][19] ph[13][16] $abc$23348$new_n3904 ph[13][17] ph[13][15] $abc$23348$new_n3890 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3896 ph[14][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$21302 +001 1 +011 1 +100 1 +101 1 +.names ph[13][16] ph[13][17] $abc$23348$new_n3903 $abc$23348$new_n3897 $abc$23348$new_n3896 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$23348$new_n3898 ph[13][15] $abc$23348$new_n3897 +10 1 +.names $abc$23348$new_n3899 ph[13][12] ph[13][13] ph[13][14] $abc$23348$new_n3898 +1000 1 +.names $abc$23348$new_n3900 ph[13][11] $abc$23348$new_n3899 +10 1 +.names $abc$23348$new_n3901 ph[13][7] ph[13][8] ph[13][9] ph[13][10] $abc$23348$new_n3900 +10000 1 +.names $abc$23348$new_n3902 ph[13][5] ph[13][6] $abc$23348$new_n3901 +100 1 +.names $abc$23348$new_n3889 ph[13][19] $abc$23348$new_n3902 +10 1 +.names ph[13][15] $abc$23348$new_n3904 $abc$23348$new_n3903 +11 1 +.names ph[13][12] ph[13][13] ph[13][14] $abc$23348$new_n3905 $abc$23348$new_n3904 +1111 1 +.names ph[13][11] $abc$23348$new_n3906 $abc$23348$new_n3905 +11 1 +.names ph[13][7] ph[13][8] ph[13][9] ph[13][10] $abc$23348$new_n3907 $abc$23348$new_n3906 +11111 1 +.names ph[13][5] ph[13][6] $abc$23348$new_n3908 $abc$23348$new_n3907 +111 1 +.names ph[13][4] ph[13][19] $abc$23348$new_n3928 $abc$23348$new_n3908 +110 1 +.names i_ce ph[13][16] $abc$23348$new_n3903 $abc$23348$new_n3897 ph[14][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21304 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][15] $abc$23348$new_n3904 $abc$23348$new_n3898 ph[14][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21306 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3912 ph[14][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21308 +001 1 +011 1 +100 1 +101 1 +.names ph[13][14] ph[13][12] ph[13][13] $abc$23348$new_n3905 $abc$23348$new_n3899 $abc$23348$new_n3912 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3914 ph[14][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21310 +001 1 +011 1 +110 1 +111 1 +.names ph[13][12] ph[13][13] $abc$23348$new_n3905 $abc$23348$new_n3899 $abc$23348$new_n3914 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[13][12] $abc$23348$new_n3905 $abc$23348$new_n3899 ph[14][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21312 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][11] $abc$23348$new_n3906 $abc$23348$new_n3900 ph[14][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21314 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][10] $abc$23348$new_n3918 ph[14][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21316 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[13][7] ph[13][8] ph[13][9] $abc$23348$new_n3901 $abc$23348$new_n3907 $abc$23348$new_n3918 +00010 1 +00011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n3920 ph[14][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21318 +001 1 +011 1 +100 1 +101 1 +.names ph[13][9] ph[13][7] ph[13][8] $abc$23348$new_n3907 $abc$23348$new_n3901 $abc$23348$new_n3920 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3922 ph[13][8] ph[14][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21320 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[13][7] $abc$23348$new_n3901 $abc$23348$new_n3907 $abc$23348$new_n3922 +000 1 +001 1 +100 1 +110 1 +.names i_ce ph[13][7] $abc$23348$new_n3907 $abc$23348$new_n3901 ph[14][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21322 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3925 ph[14][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21324 +001 1 +011 1 +110 1 +111 1 +.names ph[13][5] ph[13][6] $abc$23348$new_n3908 $abc$23348$new_n3902 $abc$23348$new_n3925 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[13][5] $abc$23348$new_n3908 $abc$23348$new_n3902 ph[14][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21326 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3928 ph[14][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21328 +001 1 +011 1 +110 1 +111 1 +.names ph[13][4] ph[13][19] ph[13][3] ph[13][1] ph[13][2] $abc$23348$new_n3928 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n3930 ph[14][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21330 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] ph[13][3] ph[13][1] ph[13][2] $abc$23348$new_n3930 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[13][19] ph[13][1] ph[13][2] ph[14][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21332 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[13][1] ph[14][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21334 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[13][0] ph[14][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21336 +001 1 +011 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n3935 yv[14][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21338 +001 1 +011 1 +110 1 +111 1 +.names ph[13][19] xv[13][15] yv[13][14] $abc$23348$new_n3943 $abc$23348$new_n3936 $abc$23348$new_n3935 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[13][15] $abc$23348$new_n3937 yv[13][12] yv[13][13] $abc$23348$new_n3936 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][15] $abc$23348$new_n3938 yv[13][10] yv[13][11] $abc$23348$new_n3937 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][15] $abc$23348$new_n3939 yv[13][8] yv[13][9] $abc$23348$new_n3938 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][15] yv[13][7] $abc$23348$new_n3940 $abc$23348$new_n3939 +000 1 +001 1 +011 1 +101 1 +.names xv[13][15] $abc$23348$new_n3941 yv[13][4] yv[13][5] yv[13][6] $abc$23348$new_n3940 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[13][15] $abc$23348$new_n3942 yv[13][2] yv[13][3] $abc$23348$new_n3941 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[13][0] xv[13][14] xv[13][15] yv[13][1] $abc$23348$new_n3942 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[13][15] $abc$23348$new_n3944 yv[13][12] yv[13][13] $abc$23348$new_n3943 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][15] $abc$23348$new_n3958 yv[13][10] yv[13][11] $abc$23348$new_n3944 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][15] yv[13][6] yv[13][7] $abc$23348$new_n3948 $abc$23348$new_n3950 $abc$23348$new_n3947 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[13][15] yv[13][5] yv[13][4] yv[13][3] $abc$23348$new_n3949 $abc$23348$new_n3948 +00001 1 +00010 1 +00011 1 +11111 1 +.names xv[13][15] xv[13][14] yv[13][0] yv[13][1] yv[13][2] $abc$23348$new_n3949 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11111 1 +.names yv[13][4] yv[13][5] $abc$23348$new_n3950 +00 1 +.names i_ce xv[13][15] yv[13][13] $abc$23348$new_n3953 yv[14][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21340 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][19] xv[13][15] yv[13][12] $abc$23348$new_n3944 $abc$23348$new_n3937 $abc$23348$new_n3953 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3955 yv[14][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21342 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] xv[13][15] yv[13][12] $abc$23348$new_n3944 $abc$23348$new_n3937 $abc$23348$new_n3955 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][15] yv[13][11] $abc$23348$new_n3957 yv[14][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21344 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][19] xv[13][15] yv[13][10] $abc$23348$new_n3958 $abc$23348$new_n3938 $abc$23348$new_n3957 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[13][15] $abc$23348$new_n3947 yv[13][8] yv[13][9] $abc$23348$new_n3958 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3960 yv[14][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21346 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] xv[13][15] yv[13][10] $abc$23348$new_n3958 $abc$23348$new_n3938 $abc$23348$new_n3960 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][15] yv[13][9] $abc$23348$new_n3962 yv[14][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21348 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] yv[13][8] xv[13][15] $abc$23348$new_n3939 $abc$23348$new_n3947 $abc$23348$new_n3962 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3964 yv[14][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21350 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] xv[13][15] yv[13][8] $abc$23348$new_n3947 $abc$23348$new_n3939 $abc$23348$new_n3964 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][15] yv[13][7] $abc$23348$new_n3966 yv[14][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21352 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][6] $abc$23348$new_n3967 $abc$23348$new_n3940 ph[13][19] $abc$23348$new_n3966 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names ph[13][19] $abc$23348$new_n3948 xv[13][15] $abc$23348$new_n3950 $abc$23348$new_n3967 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3969 yv[14][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21354 +001 1 +011 1 +110 1 +111 1 +.names xv[13][15] yv[13][6] $abc$23348$new_n3970 $abc$23348$new_n3967 $abc$23348$new_n3969 +0000 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names ph[13][19] xv[13][15] $abc$23348$new_n3941 yv[13][4] yv[13][5] $abc$23348$new_n3970 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names i_ce xv[13][15] yv[13][5] $abc$23348$new_n3972 yv[14][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21356 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][19] xv[13][15] yv[13][4] $abc$23348$new_n3973 $abc$23348$new_n3941 $abc$23348$new_n3972 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[13][15] yv[13][3] $abc$23348$new_n3949 $abc$23348$new_n3973 +000 1 +100 1 +101 1 +110 1 +.names i_ce $abc$23348$new_n3975 yv[14][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21358 +001 1 +011 1 +110 1 +111 1 +.names ph[13][19] xv[13][15] yv[13][4] $abc$23348$new_n3973 $abc$23348$new_n3941 $abc$23348$new_n3975 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[13][15] yv[13][3] $abc$23348$new_n3977 yv[14][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21360 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n3949 yv[13][2] ph[13][19] $abc$23348$new_n3942 $abc$23348$new_n3977 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[13][15] yv[13][2] $abc$23348$new_n3979 yv[14][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21362 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][14] xv[13][15] yv[13][0] yv[13][1] $abc$23348$new_n3979 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_ce $abc$23348$new_n3981 yv[14][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21364 +001 1 +011 1 +110 1 +111 1 +.names xv[13][15] yv[13][1] ph[13][19] yv[13][0] xv[13][14] $abc$23348$new_n3981 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[13][14] yv[13][0] yv[14][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21366 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[13][15] xv[13][14] $abc$23348$new_n3984 xv[14][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21368 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] $abc$23348$new_n3985 $abc$23348$new_n3992 $abc$23348$new_n3984 +000 1 +001 1 +101 1 +111 1 +.names yv[13][15] $abc$23348$new_n3986 xv[13][12] xv[13][13] $abc$23348$new_n3985 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3987 xv[13][10] xv[13][11] $abc$23348$new_n3986 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3988 xv[13][8] xv[13][9] $abc$23348$new_n3987 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3989 xv[13][6] xv[13][7] $abc$23348$new_n3988 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3990 xv[13][4] xv[13][5] $abc$23348$new_n3989 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3991 xv[13][2] xv[13][3] $abc$23348$new_n3990 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][14] yv[13][15] xv[13][0] xv[13][1] $abc$23348$new_n3991 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names yv[13][15] $abc$23348$new_n3993 xv[13][12] xv[13][13] $abc$23348$new_n3992 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[13][15] $abc$23348$new_n3994 xv[13][10] xv[13][11] $abc$23348$new_n3993 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[13][15] $abc$23348$new_n3995 xv[13][8] xv[13][9] $abc$23348$new_n3994 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[13][15] xv[13][6] xv[13][7] $abc$23348$new_n3996 $abc$23348$new_n3999 $abc$23348$new_n3995 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[13][15] xv[13][4] xv[13][5] $abc$23348$new_n3997 $abc$23348$new_n3996 +0110 1 +1000 1 +.names yv[13][15] xv[13][3] $abc$23348$new_n3998 $abc$23348$new_n3997 +000 1 +001 1 +011 1 +101 1 +.names yv[13][15] xv[13][0] yv[13][14] xv[13][1] xv[13][2] $abc$23348$new_n3998 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +11000 1 +.names xv[13][4] xv[13][5] $abc$23348$new_n3999 +00 1 +.names i_ce yv[13][15] xv[13][13] $abc$23348$new_n4001 xv[14][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21370 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][12] yv[13][15] $abc$23348$new_n3993 $abc$23348$new_n3986 $abc$23348$new_n4001 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4003 xv[14][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21372 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] yv[13][15] xv[13][12] $abc$23348$new_n3993 $abc$23348$new_n3986 $abc$23348$new_n4003 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[13][15] xv[13][11] $abc$23348$new_n4005 xv[14][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21374 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][10] yv[13][15] $abc$23348$new_n3994 $abc$23348$new_n3987 $abc$23348$new_n4005 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4007 xv[14][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21376 +001 1 +011 1 +110 1 +111 1 +.names ph[13][19] yv[13][15] xv[13][10] $abc$23348$new_n3994 $abc$23348$new_n3987 $abc$23348$new_n4007 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[13][15] xv[13][9] $abc$23348$new_n4009 xv[14][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21378 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][8] yv[13][15] $abc$23348$new_n3995 $abc$23348$new_n3988 $abc$23348$new_n4009 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4011 xv[14][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21380 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] yv[13][15] xv[13][8] $abc$23348$new_n3995 $abc$23348$new_n3988 $abc$23348$new_n4011 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[13][15] xv[13][7] $abc$23348$new_n4013 xv[14][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21382 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][6] yv[13][15] $abc$23348$new_n3989 $abc$23348$new_n4014 $abc$23348$new_n4013 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3996 $abc$23348$new_n3999 yv[13][15] $abc$23348$new_n4014 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n4016 xv[14][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21384 +001 1 +011 1 +100 1 +101 1 +.names yv[13][15] xv[13][6] ph[13][19] $abc$23348$new_n3989 $abc$23348$new_n4014 $abc$23348$new_n4016 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[13][15] xv[13][5] $abc$23348$new_n4018 xv[14][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21386 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][4] yv[13][15] $abc$23348$new_n3997 $abc$23348$new_n3990 $abc$23348$new_n4018 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4020 xv[14][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21388 +001 1 +011 1 +110 1 +111 1 +.names ph[13][19] yv[13][15] xv[13][4] $abc$23348$new_n3997 $abc$23348$new_n3990 $abc$23348$new_n4020 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[13][15] xv[13][3] $abc$23348$new_n4022 xv[14][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21390 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n3998 $abc$23348$new_n3991 ph[13][19] xv[13][2] $abc$23348$new_n4022 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce yv[13][15] xv[13][2] $abc$23348$new_n4024 xv[14][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21392 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] yv[13][14] yv[13][15] xv[13][0] xv[13][1] $abc$23348$new_n4024 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names i_ce $abc$23348$new_n4026 xv[14][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21394 +001 1 +011 1 +110 1 +111 1 +.names yv[13][15] xv[13][1] ph[13][19] xv[13][0] yv[13][14] $abc$23348$new_n4026 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[13][0] yv[13][14] xv[14][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21396 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[14][15] yv[14][14] $abc$23348$new_n4029 yv[15][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21436 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] $abc$23348$new_n4030 xv[14][15] $abc$23348$new_n4038 $abc$23348$new_n4029 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n4031 xv[14][15] yv[14][12] yv[14][13] $abc$23348$new_n4030 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$23348$new_n4032 yv[14][11] xv[14][15] $abc$23348$new_n4031 +100 1 +110 1 +111 1 +.names $abc$23348$new_n4033 xv[14][15] yv[14][9] yv[14][10] $abc$23348$new_n4032 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$23348$new_n4034 yv[14][8] xv[14][15] $abc$23348$new_n4033 +000 1 +010 1 +011 1 +.names xv[14][15] yv[14][7] $abc$23348$new_n4035 yv[14][6] $abc$23348$new_n4034 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$23348$new_n4036 xv[14][15] yv[14][4] yv[14][5] $abc$23348$new_n4035 +1000 1 +1111 1 +.names xv[14][15] yv[14][1] yv[14][2] yv[14][3] yv[14][0] $abc$23348$new_n4036 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$23348$new_n4039 yv[14][11] yv[14][12] yv[14][13] $abc$23348$new_n4038 +1000 1 +.names $abc$23348$new_n4040 yv[14][9] yv[14][10] $abc$23348$new_n4039 +100 1 +.names $abc$23348$new_n4041 yv[14][8] $abc$23348$new_n4040 +10 1 +.names $abc$23348$new_n4042 yv[14][5] yv[14][6] yv[14][7] $abc$23348$new_n4041 +1000 1 +.names $abc$23348$new_n4043 yv[14][4] $abc$23348$new_n4042 +10 1 +.names yv[14][0] yv[14][1] yv[14][2] yv[14][3] $abc$23348$new_n4043 +0000 1 +.names i_ce xv[14][15] yv[14][13] $abc$23348$new_n4045 yv[15][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21438 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][12] $abc$23348$new_n4031 xv[14][15] $abc$23348$new_n4046 $abc$23348$new_n4045 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n4039 yv[14][11] $abc$23348$new_n4046 +10 1 +.names i_ce xv[14][15] yv[14][12] $abc$23348$new_n4048 yv[15][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21440 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] $abc$23348$new_n4031 xv[14][15] $abc$23348$new_n4046 $abc$23348$new_n4048 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n4050 yv[15][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21442 +001 1 +011 1 +110 1 +111 1 +.names yv[14][11] ph[14][19] xv[14][15] $abc$23348$new_n4032 $abc$23348$new_n4039 $abc$23348$new_n4050 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[14][15] yv[14][10] $abc$23348$new_n4052 yv[15][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21444 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][9] $abc$23348$new_n4033 xv[14][15] $abc$23348$new_n4040 $abc$23348$new_n4052 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4054 yv[15][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21446 +001 1 +011 1 +110 1 +111 1 +.names yv[14][9] ph[14][19] xv[14][15] $abc$23348$new_n4033 $abc$23348$new_n4040 $abc$23348$new_n4054 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4056 yv[15][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21448 +001 1 +011 1 +110 1 +111 1 +.names yv[14][8] ph[14][19] xv[14][15] $abc$23348$new_n4034 $abc$23348$new_n4041 $abc$23348$new_n4056 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[14][15] yv[14][7] $abc$23348$new_n4058 yv[15][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21450 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][6] xv[14][15] ph[14][19] $abc$23348$new_n4060 $abc$23348$new_n4059 $abc$23348$new_n4058 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$23348$new_n4042 yv[14][5] $abc$23348$new_n4059 +10 1 +.names ph[14][19] $abc$23348$new_n4035 xv[14][15] $abc$23348$new_n4060 +100 1 +110 1 +111 1 +.names i_ce xv[14][15] yv[14][6] $abc$23348$new_n4062 yv[15][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21452 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n4060 ph[14][19] xv[14][15] $abc$23348$new_n4059 $abc$23348$new_n4062 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce xv[14][15] yv[14][5] $abc$23348$new_n4064 yv[15][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21454 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][4] xv[14][15] $abc$23348$new_n4036 $abc$23348$new_n4043 $abc$23348$new_n4064 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4066 yv[15][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21456 +001 1 +011 1 +110 1 +111 1 +.names yv[14][4] ph[14][19] xv[14][15] $abc$23348$new_n4036 $abc$23348$new_n4043 $abc$23348$new_n4066 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[14][15] yv[14][3] $abc$23348$new_n4068 yv[15][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21458 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][2] yv[14][0] yv[14][1] xv[14][15] $abc$23348$new_n4068 +00000 1 +00001 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4070 yv[15][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21460 +001 1 +011 1 +110 1 +111 1 +.names yv[14][2] ph[14][19] yv[14][0] yv[14][1] xv[14][15] $abc$23348$new_n4070 +00001 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n4072 yv[15][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21462 +001 1 +011 1 +100 1 +101 1 +.names yv[14][1] ph[14][19] yv[14][0] xv[14][15] $abc$23348$new_n4072 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1001 1 +1111 1 +.names i_ce xv[14][15] yv[14][0] yv[15][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21464 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[14][15] xv[14][14] $abc$23348$new_n4075 xv[15][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21466 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4084 $abc$23348$new_n4076 ph[14][19] $abc$23348$new_n4075 +100 1 +110 1 +111 1 +.names $abc$23348$new_n4077 yv[14][15] xv[14][12] xv[14][13] $abc$23348$new_n4076 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$23348$new_n4083 yv[14][15] $abc$23348$new_n4079 xv[14][10] xv[14][11] $abc$23348$new_n4077 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$23348$new_n4082 yv[14][15] $abc$23348$new_n4081 xv[14][6] xv[14][7] $abc$23348$new_n4079 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names yv[14][15] xv[14][1] xv[14][2] xv[14][3] xv[14][0] $abc$23348$new_n4081 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[14][15] xv[14][5] xv[14][4] $abc$23348$new_n4082 +000 1 +001 1 +010 1 +011 1 +100 1 +.names yv[14][15] xv[14][9] xv[14][8] $abc$23348$new_n4083 +000 1 +001 1 +010 1 +011 1 +100 1 +.names $abc$23348$new_n4085 yv[14][15] ph[14][19] xv[14][13] $abc$23348$new_n4084 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n4086 yv[14][15] ph[14][19] xv[14][12] xv[14][11] $abc$23348$new_n4085 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[14][15] ph[14][19] xv[14][9] xv[14][10] $abc$23348$new_n4087 $abc$23348$new_n4086 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[14][5] xv[14][6] xv[14][7] xv[14][8] $abc$23348$new_n4088 $abc$23348$new_n4087 +11111 1 +.names xv[14][4] $abc$23348$new_n4089 $abc$23348$new_n4088 +11 1 +.names xv[14][0] xv[14][1] xv[14][2] xv[14][3] $abc$23348$new_n4089 +1111 1 +.names i_ce yv[14][15] xv[14][13] $abc$23348$new_n4091 xv[15][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21468 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4085 $abc$23348$new_n4077 ph[14][19] xv[14][12] yv[14][15] $abc$23348$new_n4091 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce yv[14][15] xv[14][12] $abc$23348$new_n4093 xv[15][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21470 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4086 ph[14][19] $abc$23348$new_n4077 xv[14][11] $abc$23348$new_n4093 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names i_ce yv[14][15] xv[14][11] $abc$23348$new_n4095 xv[15][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21472 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4086 $abc$23348$new_n4096 xv[14][10] yv[14][15] ph[14][19] $abc$23348$new_n4095 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names ph[14][19] $abc$23348$new_n4079 $abc$23348$new_n4083 $abc$23348$new_n4096 +100 1 +101 1 +110 1 +.names i_ce yv[14][15] xv[14][10] $abc$23348$new_n4098 xv[15][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21474 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4096 yv[14][15] ph[14][19] $abc$23348$new_n4087 xv[14][9] $abc$23348$new_n4098 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce yv[14][15] xv[14][9] $abc$23348$new_n4100 xv[15][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21476 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][15] xv[14][8] $abc$23348$new_n4079 $abc$23348$new_n4087 $abc$23348$new_n4100 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[14][15] xv[14][8] $abc$23348$new_n4102 xv[15][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21478 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4103 $abc$23348$new_n4079 xv[14][7] ph[14][19] $abc$23348$new_n4102 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names yv[14][15] ph[14][19] $abc$23348$new_n4088 xv[14][6] xv[14][5] $abc$23348$new_n4103 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names i_ce yv[14][15] xv[14][7] $abc$23348$new_n4105 xv[15][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21480 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4103 $abc$23348$new_n4106 xv[14][6] yv[14][15] ph[14][19] $abc$23348$new_n4105 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names ph[14][19] $abc$23348$new_n4081 $abc$23348$new_n4082 $abc$23348$new_n4106 +100 1 +101 1 +110 1 +.names i_ce yv[14][15] xv[14][6] $abc$23348$new_n4108 xv[15][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21482 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4106 yv[14][15] ph[14][19] $abc$23348$new_n4088 xv[14][5] $abc$23348$new_n4108 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce yv[14][15] xv[14][5] $abc$23348$new_n4110 xv[15][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21484 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] xv[14][4] yv[14][15] $abc$23348$new_n4081 $abc$23348$new_n4089 $abc$23348$new_n4110 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4112 xv[15][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21486 +001 1 +011 1 +110 1 +111 1 +.names xv[14][4] ph[14][19] yv[14][15] $abc$23348$new_n4081 $abc$23348$new_n4089 $abc$23348$new_n4112 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[14][15] xv[14][3] $abc$23348$new_n4114 xv[15][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21488 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] xv[14][2] xv[14][0] xv[14][1] yv[14][15] $abc$23348$new_n4114 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4116 xv[15][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21490 +001 1 +011 1 +110 1 +111 1 +.names xv[14][2] ph[14][19] xv[14][0] xv[14][1] yv[14][15] $abc$23348$new_n4116 +00111 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4118 xv[15][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21492 +001 1 +011 1 +110 1 +111 1 +.names xv[14][1] ph[14][19] xv[14][0] yv[14][15] $abc$23348$new_n4118 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce yv[14][15] xv[14][0] xv[15][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21494 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[15][15] yv[15][14] $abc$23348$new_n4121 yv[16][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21496 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] $abc$23348$new_n4130 xv[15][15] $abc$23348$new_n4122 $abc$23348$new_n4121 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n4123 yv[15][13] $abc$23348$new_n4122 +10 1 +.names $abc$23348$new_n4124 yv[15][12] $abc$23348$new_n4123 +10 1 +.names $abc$23348$new_n4125 yv[15][10] yv[15][11] $abc$23348$new_n4124 +100 1 +.names $abc$23348$new_n4129 $abc$23348$new_n4126 $abc$23348$new_n4125 +11 1 +.names $abc$23348$new_n4127 yv[15][5] yv[15][6] yv[15][7] $abc$23348$new_n4126 +1000 1 +.names $abc$23348$new_n4128 yv[15][4] $abc$23348$new_n4127 +10 1 +.names yv[15][0] yv[15][1] yv[15][2] yv[15][3] $abc$23348$new_n4128 +0000 1 +.names yv[15][8] yv[15][9] $abc$23348$new_n4129 +00 1 +.names $abc$23348$new_n4131 xv[15][15] yv[15][12] yv[15][13] $abc$23348$new_n4130 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names xv[15][15] yv[15][11] $abc$23348$new_n4132 yv[15][10] $abc$23348$new_n4131 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[15][15] yv[15][8] yv[15][9] $abc$23348$new_n4133 $abc$23348$new_n4132 +0000 1 +1110 1 +.names xv[15][15] yv[15][7] $abc$23348$new_n4134 yv[15][6] $abc$23348$new_n4133 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$23348$new_n4135 xv[15][15] yv[15][4] yv[15][5] $abc$23348$new_n4134 +1000 1 +1111 1 +.names xv[15][15] yv[15][1] yv[15][2] yv[15][3] yv[15][0] $abc$23348$new_n4135 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names i_ce xv[15][15] yv[15][13] $abc$23348$new_n4138 yv[16][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21498 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][12] $abc$23348$new_n4131 xv[15][15] $abc$23348$new_n4124 $abc$23348$new_n4138 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4140 yv[16][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21500 +001 1 +011 1 +110 1 +111 1 +.names yv[15][12] ph[15][19] xv[15][15] $abc$23348$new_n4131 $abc$23348$new_n4124 $abc$23348$new_n4140 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[15][15] yv[15][11] $abc$23348$new_n4142 yv[16][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21502 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[15][19] xv[15][15] yv[15][10] $abc$23348$new_n4143 $abc$23348$new_n4125 $abc$23348$new_n4142 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[15][15] $abc$23348$new_n4132 $abc$23348$new_n4143 +10 1 +.names i_ce $abc$23348$new_n4145 yv[16][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21504 +001 1 +011 1 +110 1 +111 1 +.names yv[15][10] ph[15][19] xv[15][15] $abc$23348$new_n4143 $abc$23348$new_n4125 $abc$23348$new_n4145 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[15][15] yv[15][9] $abc$23348$new_n4147 yv[16][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21506 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][8] xv[15][15] $abc$23348$new_n4133 $abc$23348$new_n4126 $abc$23348$new_n4147 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4149 yv[16][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21508 +001 1 +011 1 +110 1 +111 1 +.names yv[15][8] ph[15][19] xv[15][15] $abc$23348$new_n4133 $abc$23348$new_n4126 $abc$23348$new_n4149 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[15][15] yv[15][7] $abc$23348$new_n4151 yv[16][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21510 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[15][6] xv[15][15] ph[15][19] $abc$23348$new_n4153 $abc$23348$new_n4152 $abc$23348$new_n4151 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$23348$new_n4127 yv[15][5] $abc$23348$new_n4152 +10 1 +.names ph[15][19] $abc$23348$new_n4134 xv[15][15] $abc$23348$new_n4153 +100 1 +110 1 +111 1 +.names i_ce xv[15][15] yv[15][6] $abc$23348$new_n4155 yv[16][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21512 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n4153 ph[15][19] xv[15][15] $abc$23348$new_n4152 $abc$23348$new_n4155 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce xv[15][15] yv[15][5] $abc$23348$new_n4157 yv[16][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21514 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][4] xv[15][15] $abc$23348$new_n4135 $abc$23348$new_n4128 $abc$23348$new_n4157 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4159 yv[16][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21516 +001 1 +011 1 +110 1 +111 1 +.names yv[15][4] ph[15][19] xv[15][15] $abc$23348$new_n4135 $abc$23348$new_n4128 $abc$23348$new_n4159 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[15][15] yv[15][3] $abc$23348$new_n4161 yv[16][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21518 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][2] yv[15][0] yv[15][1] xv[15][15] $abc$23348$new_n4161 +00000 1 +00001 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4163 yv[16][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21520 +001 1 +011 1 +110 1 +111 1 +.names yv[15][2] ph[15][19] yv[15][0] yv[15][1] xv[15][15] $abc$23348$new_n4163 +00001 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n4165 yv[16][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21522 +001 1 +011 1 +100 1 +101 1 +.names yv[15][1] ph[15][19] yv[15][0] xv[15][15] $abc$23348$new_n4165 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1001 1 +1111 1 +.names i_ce xv[15][15] yv[15][0] yv[16][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21524 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[15][15] xv[15][14] $abc$23348$new_n4168 xv[16][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21526 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4177 $abc$23348$new_n4169 ph[15][19] $abc$23348$new_n4168 +100 1 +110 1 +111 1 +.names $abc$23348$new_n4170 yv[15][15] xv[15][12] xv[15][13] $abc$23348$new_n4169 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$23348$new_n4176 yv[15][15] $abc$23348$new_n4172 xv[15][10] xv[15][11] $abc$23348$new_n4170 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$23348$new_n4175 yv[15][15] $abc$23348$new_n4174 xv[15][6] xv[15][7] $abc$23348$new_n4172 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names yv[15][15] xv[15][1] xv[15][2] xv[15][3] xv[15][0] $abc$23348$new_n4174 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[15][15] xv[15][5] xv[15][4] $abc$23348$new_n4175 +000 1 +001 1 +010 1 +011 1 +100 1 +.names yv[15][15] xv[15][9] xv[15][8] $abc$23348$new_n4176 +000 1 +001 1 +010 1 +011 1 +100 1 +.names $abc$23348$new_n4178 yv[15][15] ph[15][19] xv[15][13] $abc$23348$new_n4177 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n4179 yv[15][15] ph[15][19] xv[15][12] xv[15][11] $abc$23348$new_n4178 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[15][15] ph[15][19] xv[15][9] xv[15][10] $abc$23348$new_n4180 $abc$23348$new_n4179 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[15][5] xv[15][6] xv[15][7] xv[15][8] $abc$23348$new_n4181 $abc$23348$new_n4180 +11111 1 +.names xv[15][4] $abc$23348$new_n4182 $abc$23348$new_n4181 +11 1 +.names xv[15][0] xv[15][1] xv[15][2] xv[15][3] $abc$23348$new_n4182 +1111 1 +.names i_ce yv[15][15] xv[15][13] $abc$23348$new_n4184 xv[16][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21528 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4178 $abc$23348$new_n4170 ph[15][19] xv[15][12] yv[15][15] $abc$23348$new_n4184 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce yv[15][15] xv[15][12] $abc$23348$new_n4186 xv[16][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21530 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4179 ph[15][19] $abc$23348$new_n4170 xv[15][11] $abc$23348$new_n4186 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names i_ce yv[15][15] xv[15][11] $abc$23348$new_n4188 xv[16][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21532 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4179 $abc$23348$new_n4189 xv[15][10] yv[15][15] ph[15][19] $abc$23348$new_n4188 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names ph[15][19] $abc$23348$new_n4172 $abc$23348$new_n4176 $abc$23348$new_n4189 +100 1 +101 1 +110 1 +.names i_ce yv[15][15] xv[15][10] $abc$23348$new_n4191 xv[16][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21534 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4189 yv[15][15] ph[15][19] $abc$23348$new_n4180 xv[15][9] $abc$23348$new_n4191 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce yv[15][15] xv[15][9] $abc$23348$new_n4193 xv[16][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21536 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][15] xv[15][8] $abc$23348$new_n4172 $abc$23348$new_n4180 $abc$23348$new_n4193 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[15][15] xv[15][8] $abc$23348$new_n4195 xv[16][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21538 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4196 $abc$23348$new_n4172 xv[15][7] ph[15][19] $abc$23348$new_n4195 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names yv[15][15] ph[15][19] $abc$23348$new_n4181 xv[15][6] xv[15][5] $abc$23348$new_n4196 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names i_ce yv[15][15] xv[15][7] $abc$23348$new_n4198 xv[16][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21540 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4196 $abc$23348$new_n4199 xv[15][6] yv[15][15] ph[15][19] $abc$23348$new_n4198 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names ph[15][19] $abc$23348$new_n4174 $abc$23348$new_n4175 $abc$23348$new_n4199 +100 1 +101 1 +110 1 +.names i_ce yv[15][15] xv[15][6] $abc$23348$new_n4201 xv[16][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21542 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4199 yv[15][15] ph[15][19] $abc$23348$new_n4181 xv[15][5] $abc$23348$new_n4201 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce yv[15][15] xv[15][5] $abc$23348$new_n4203 xv[16][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21544 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] xv[15][4] yv[15][15] $abc$23348$new_n4174 $abc$23348$new_n4182 $abc$23348$new_n4203 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4205 xv[16][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21546 +001 1 +011 1 +110 1 +111 1 +.names xv[15][4] ph[15][19] yv[15][15] $abc$23348$new_n4174 $abc$23348$new_n4182 $abc$23348$new_n4205 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[15][15] xv[15][3] $abc$23348$new_n4207 xv[16][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21548 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] xv[15][2] xv[15][0] xv[15][1] yv[15][15] $abc$23348$new_n4207 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4209 xv[16][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21550 +001 1 +011 1 +110 1 +111 1 +.names xv[15][2] ph[15][19] xv[15][0] xv[15][1] yv[15][15] $abc$23348$new_n4209 +00111 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4211 xv[16][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21552 +001 1 +011 1 +110 1 +111 1 +.names xv[15][1] ph[15][19] xv[15][0] yv[15][15] $abc$23348$new_n4211 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce yv[15][15] xv[15][0] xv[16][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21554 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[15][15] xv[15][15] $abc$23348$new_n4214 xv[16][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21556 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4177 xv[15][14] ph[15][19] $abc$23348$new_n4169 yv[15][15] $abc$23348$new_n4214 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names i_ce yv[15][15] xv[15][15] $abc$23348$new_n4216 yv[16][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21558 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[15][19] xv[15][15] yv[15][14] $abc$23348$new_n4130 $abc$23348$new_n4122 $abc$23348$new_n4216 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[14][15] xv[14][15] $abc$23348$new_n4218 xv[15][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21560 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4084 xv[14][14] ph[14][19] $abc$23348$new_n4076 yv[14][15] $abc$23348$new_n4218 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names i_ce yv[14][15] xv[14][15] $abc$23348$new_n4220 yv[15][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21562 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[14][19] xv[14][15] yv[14][14] $abc$23348$new_n4030 $abc$23348$new_n4038 $abc$23348$new_n4220 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4222 ph[15][19] ph[14][19] $abc$23348$new_n4227 $abc$23348$auto$rtlil.cc:2693:MuxGate$21564 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n4223 $abc$23348$new_n4226 ph[14][16] ph[14][17] ph[14][18] $abc$23348$new_n4222 +11000 1 +.names $abc$23348$new_n4224 $abc$23348$new_n4225 ph[14][7] ph[14][10] ph[14][15] $abc$23348$new_n4223 +11000 1 +.names ph[14][3] ph[14][4] ph[14][5] ph[14][6] $abc$23348$new_n4224 +0000 1 +.names ph[14][9] ph[14][8] ph[14][2] ph[14][0] ph[14][1] $abc$23348$new_n4225 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names ph[14][11] ph[14][12] ph[14][13] ph[14][14] $abc$23348$new_n4226 +0000 1 +.names $abc$23348$new_n4228 $abc$23348$new_n4230 ph[14][2] ph[14][0] ph[14][1] $abc$23348$new_n4227 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[14][15] ph[14][16] ph[14][17] ph[14][18] $abc$23348$new_n4229 $abc$23348$new_n4228 +11111 1 +.names ph[14][11] ph[14][12] ph[14][13] ph[14][14] $abc$23348$new_n4229 +1111 1 +.names ph[14][7] ph[14][8] ph[14][9] ph[14][10] $abc$23348$new_n4231 $abc$23348$new_n4230 +11111 1 +.names ph[14][3] ph[14][4] ph[14][5] ph[14][6] $abc$23348$new_n4231 +1111 1 +.names i_ce yv[13][15] xv[13][15] $abc$23348$new_n4233 xv[14][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21566 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][14] yv[13][15] $abc$23348$new_n3992 $abc$23348$new_n3985 $abc$23348$new_n4233 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[13][15] xv[13][15] $abc$23348$new_n4235 yv[14][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21568 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][19] xv[13][15] yv[13][14] $abc$23348$new_n3943 $abc$23348$new_n3936 $abc$23348$new_n4235 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3885 ph[14][19] $abc$23348$new_n3890 ph[13][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21570 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names i_ce yv[12][15] xv[12][15] $abc$23348$new_n4238 xv[13][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21572 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][14] yv[12][15] $abc$23348$new_n3845 $abc$23348$new_n3838 $abc$23348$new_n4238 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[12][15] xv[12][15] $abc$23348$new_n4240 yv[13][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21574 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[12][19] xv[12][15] yv[12][14] $abc$23348$new_n3797 $abc$23348$new_n3790 $abc$23348$new_n4240 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce ph[13][19] $abc$23348$new_n4242 $abc$23348$new_n3746 $abc$23348$auto$rtlil.cc:2693:MuxGate$21576 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[12][18] ph[12][19] $abc$23348$new_n3742 ph[12][17] $abc$23348$new_n4242 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce yv[11][15] xv[11][15] $abc$23348$new_n4244 xv[12][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21578 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][14] yv[11][15] $abc$23348$new_n3702 $abc$23348$new_n3695 $abc$23348$new_n4244 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[11][15] xv[11][15] $abc$23348$new_n4246 yv[12][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21580 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] xv[11][15] yv[11][14] $abc$23348$new_n3653 $abc$23348$new_n3646 $abc$23348$new_n4246 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[10][15] xv[10][15] $abc$23348$new_n4251 xv[11][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21584 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][14] yv[10][15] $abc$23348$new_n3557 $abc$23348$new_n3547 $abc$23348$new_n4251 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[10][15] xv[10][15] $abc$23348$new_n4253 yv[11][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21586 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] xv[10][15] yv[10][14] $abc$23348$new_n3501 $abc$23348$new_n3489 $abc$23348$new_n4253 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[9][15] xv[9][15] $abc$23348$new_n4258 xv[10][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21590 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][14] yv[9][15] $abc$23348$new_n3399 $abc$23348$new_n3391 $abc$23348$new_n4258 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[9][15] xv[9][15] $abc$23348$new_n4260 yv[10][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21592 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][15] yv[9][14] $abc$23348$new_n3351 $abc$23348$new_n3343 $abc$23348$new_n4260 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[8][15] xv[8][15] $abc$23348$new_n4265 xv[9][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21596 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][14] yv[8][15] $abc$23348$new_n3254 $abc$23348$new_n3244 $abc$23348$new_n4265 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[8][15] xv[8][15] $abc$23348$new_n4267 yv[9][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21598 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][15] yv[8][14] $abc$23348$new_n3204 $abc$23348$new_n3195 $abc$23348$new_n4267 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce ph[9][19] $abc$23348$new_n4269 $abc$23348$new_n4270 $abc$23348$auto$rtlil.cc:2693:MuxGate$21600 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[8][19] ph[8][16] ph[8][17] $abc$23348$new_n3141 $abc$23348$new_n4269 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$23348$new_n3148 ph[8][18] ph[8][19] ph[8][16] ph[8][17] $abc$23348$new_n4270 +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names i_ce yv[7][15] xv[7][15] $abc$23348$new_n4272 xv[8][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21602 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][14] yv[7][15] $abc$23348$new_n3102 $abc$23348$new_n3094 $abc$23348$new_n4272 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[7][15] xv[7][15] $abc$23348$new_n4274 yv[8][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21604 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][15] yv[7][14] $abc$23348$new_n3055 $abc$23348$new_n3047 $abc$23348$new_n4274 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[6][15] xv[6][15] $abc$23348$new_n4279 xv[7][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21608 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] xv[6][14] yv[6][15] $abc$23348$new_n2955 $abc$23348$new_n2944 $abc$23348$new_n4279 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[6][15] xv[6][15] $abc$23348$new_n4281 yv[7][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21610 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][15] yv[6][14] $abc$23348$new_n2906 $abc$23348$new_n2894 $abc$23348$new_n4281 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce ph[7][19] $abc$23348$new_n4283 $abc$23348$new_n2844 $abc$23348$auto$rtlil.cc:2693:MuxGate$21612 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names ph[6][18] ph[6][19] ph[6][16] ph[6][17] $abc$23348$new_n2850 $abc$23348$new_n4283 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11111 1 +.names i_ce yv[5][15] xv[5][15] $abc$23348$new_n4285 xv[6][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21614 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][14] yv[5][15] $abc$23348$new_n2806 $abc$23348$new_n2799 $abc$23348$new_n4285 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[5][15] xv[5][15] $abc$23348$new_n4287 yv[6][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21616 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][15] yv[5][14] $abc$23348$new_n2761 $abc$23348$new_n2754 $abc$23348$new_n4287 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[4][15] xv[4][15] $abc$23348$new_n4292 xv[5][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21620 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][14] yv[4][15] $abc$23348$new_n2667 $abc$23348$new_n2660 $abc$23348$new_n4292 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[4][15] xv[4][15] $abc$23348$new_n4294 yv[5][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21622 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][15] yv[4][14] $abc$23348$new_n2621 $abc$23348$new_n2614 $abc$23348$new_n4294 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2560 ph[5][19] $abc$23348$new_n2567 ph[4][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21624 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce yv[3][15] xv[3][15] $abc$23348$new_n4297 xv[4][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21626 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][14] yv[3][15] $abc$23348$new_n2525 $abc$23348$new_n2518 $abc$23348$new_n4297 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[3][15] xv[3][15] $abc$23348$new_n4299 yv[4][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21628 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][15] yv[3][14] $abc$23348$new_n2479 $abc$23348$new_n2472 $abc$23348$new_n4299 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2431 ph[4][19] $abc$23348$new_n2435 ph[3][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21630 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce yv[2][15] xv[2][15] $abc$23348$new_n4302 xv[3][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21632 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] xv[2][14] yv[2][15] $abc$23348$new_n2392 $abc$23348$new_n2385 $abc$23348$new_n4302 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[2][15] xv[2][15] $abc$23348$new_n4304 yv[3][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21634 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][15] yv[2][14] $abc$23348$new_n2347 $abc$23348$new_n2340 $abc$23348$new_n4304 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[1][15] xv[1][15] $abc$23348$new_n4309 xv[2][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21638 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][14] yv[1][15] $abc$23348$new_n2251 $abc$23348$new_n2244 $abc$23348$new_n4309 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[1][15] xv[1][15] $abc$23348$new_n4311 yv[2][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21640 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][15] yv[1][14] $abc$23348$new_n2204 $abc$23348$new_n2197 $abc$23348$new_n4311 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[0][15] xv[0][15] $abc$23348$new_n4316 xv[1][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21644 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][14] yv[0][15] $abc$23348$new_n2110 $abc$23348$new_n2103 $abc$23348$new_n4316 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce yv[0][15] xv[0][15] $abc$23348$new_n4318 yv[1][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21646 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][15] yv[0][14] $abc$23348$new_n2063 $abc$23348$new_n2056 $abc$23348$new_n4318 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2014 ph[1][19] $abc$23348$new_n2019 ph[0][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21648 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names i_ce $abc$23348$new_n4321 o_xval[12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21650 +001 1 +011 1 +110 1 +111 1 +.names xv[16][15] xv[16][13] xv[16][14] $abc$23348$new_n1994 $abc$23348$new_n4321 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$23348$new_n4323 o_yval[12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21652 +001 1 +011 1 +110 1 +111 1 +.names yv[16][15] yv[16][13] yv[16][14] $abc$23348$new_n1974 $abc$23348$new_n4323 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ax[16] o_aux $abc$23348$auto$rtlil.cc:2693:MuxGate$21654 +001 1 +011 1 +110 1 +111 1 +.names $abc$23348$new_n1935 $abc$23348$new_n4326 xv[0][15] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$21656 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n4327 $abc$23348$new_n4328 $abc$23348$new_n4326 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_yval[12] $abc$23348$new_n1865 $abc$23348$new_n4327 +00 1 +.names i_xval[12] $abc$23348$new_n1871 $abc$23348$new_n4328 +00 1 +.names $abc$23348$new_n4330 $abc$23348$new_n4328 $abc$23348$new_n1881 i_ce yv[0][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21658 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n1874 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n4327 i_xval[12] $abc$23348$new_n4330 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_phase[17] ph[0][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21660 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[15] ax[16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21662 +001 1 +011 1 +110 1 +111 1 +.names $abc$23348$new_n1869 i_yval[1] i_yval[0] i_xval[1] i_xval[0] $abc$23348$new_n4333 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n1969 xv[0][3] $abc$23348$new_n1885 $abc$23348$new_n4333 $abc$23348$auto$rtlil.cc:2693:MuxGate$19970 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names ph[0][19] xv[0][13] yv[0][12] $abc$23348$new_n2057 $abc$23348$new_n2064 $abc$23348$new_n4335 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][14] $abc$23348$new_n4335 yv[0][13] yv[1][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20066 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][11] yv[0][10] $abc$23348$new_n2058 $abc$23348$new_n2065 $abc$23348$new_n4337 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][12] $abc$23348$new_n4337 yv[0][11] yv[1][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20070 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][14] yv[1][12] $abc$23348$new_n2198 $abc$23348$new_n2205 $abc$23348$new_n4339 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[1][15] $abc$23348$new_n4339 yv[1][13] yv[2][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20164 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][12] yv[1][10] $abc$23348$new_n2199 $abc$23348$new_n2206 $abc$23348$new_n4341 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[1][13] $abc$23348$new_n4341 yv[1][11] yv[2][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20168 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][4] yv[1][6] $abc$23348$new_n2249 $abc$23348$new_n2256 $abc$23348$new_n4343 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[1][5] $abc$23348$new_n4343 yv[1][7] xv[2][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20210 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][15] yv[2][12] $abc$23348$new_n2348 $abc$23348$new_n2341 $abc$23348$new_n4345 +00100 1 +00110 1 +01001 1 +01011 1 +10010 1 +10011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4345 yv[2][13] yv[3][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20262 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[2][19] xv[2][8] yv[2][11] $abc$23348$new_n2388 $abc$23348$new_n2395 $abc$23348$new_n4347 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[2][9] $abc$23348$new_n4347 yv[2][12] xv[3][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20300 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][4] yv[2][7] $abc$23348$new_n2390 $abc$23348$new_n2397 $abc$23348$new_n4349 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[2][5] $abc$23348$new_n4349 yv[2][8] xv[3][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20308 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][15] $abc$23348$new_n2480 yv[3][12] $abc$23348$new_n2489 $abc$23348$new_n4351 +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4351 yv[3][13] yv[4][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20360 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[4][19] xv[4][15] $abc$23348$new_n2633 yv[4][11] $abc$23348$new_n2615 $abc$23348$new_n4353 +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4353 yv[4][12] yv[5][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20460 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[4][15] ph[4][19] $abc$23348$new_n2616 yv[4][10] $abc$23348$new_n2633 $abc$23348$new_n4355 +00010 1 +00011 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4355 yv[4][11] yv[5][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20462 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[6][14] ph[6][19] $abc$23348$new_n2851 $abc$23348$new_n2846 ph[6][13] $abc$23348$new_n4357 +00010 1 +00110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4357 ph[6][15] ph[7][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20620 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[7][19] ph[7][15] ph[7][14] $abc$23348$new_n2996 $abc$23348$new_n3002 $abc$23348$new_n4359 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4359 ph[8][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20718 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] $abc$23348$new_n2997 $abc$23348$new_n3003 ph[7][12] ph[7][11] $abc$23348$new_n4361 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names i_ce $abc$23348$new_n4361 ph[7][13] ph[8][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20722 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[8][19] ph[8][15] ph[8][14] $abc$23348$new_n3149 $abc$23348$new_n3142 $abc$23348$new_n4363 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4363 ph[9][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20816 +001 1 +011 1 +110 1 +111 1 +.names ph[8][19] $abc$23348$new_n3147 $abc$23348$new_n3143 $abc$23348$new_n3154 $abc$23348$new_n3150 $abc$23348$new_n4365 +00011 1 +00111 1 +01011 1 +01111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4365 ph[8][13] ph[9][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20820 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[10][19] ph[10][14] $abc$23348$new_n3440 $abc$23348$new_n3446 ph[10][13] $abc$23348$new_n4367 +00010 1 +00110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4367 ph[10][15] ph[11][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21012 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$23348$new_n3498 ph[10][19] $abc$23348$new_n3491 $abc$23348$new_n3511 $abc$23348$new_n3503 $abc$23348$new_n4369 +00100 1 +00101 1 +00110 1 +00111 1 +11010 1 +11110 1 +.names $abc$23348$new_n4369 yv[10][10] xv[10][15] $abc$23348$new_n3497 ph[10][19] $abc$23348$new_n4370 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$23348$new_n3498 ph[10][19] $abc$23348$new_n3491 $abc$23348$new_n3511 $abc$23348$new_n3503 $abc$23348$new_n4371 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$23348$new_n4371 $abc$23348$new_n3497 ph[10][19] xv[10][15] $abc$23348$new_n4372 +0000 1 +0001 1 +0100 1 +0101 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names ph[11][19] ph[11][14] ph[11][13] $abc$23348$new_n3601 $abc$23348$new_n3607 $abc$23348$new_n4373 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4373 ph[12][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21112 +001 1 +011 1 +110 1 +111 1 +.names yv[11][3] yv[11][4] yv[11][5] yv[11][6] yv[11][7] $abc$23348$new_n4375 +00000 1 +11111 1 +.names xv[11][15] $abc$23348$new_n4375 $abc$23348$new_n3658 yv[11][7] $abc$23348$new_n4376 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ph[11][19] ph[11][17] ph[11][18] $abc$23348$new_n3605 $abc$23348$new_n3599 $abc$23348$new_n4377 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4377 ph[12][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21582 +001 1 +011 1 +110 1 +111 1 +.names ph[10][19] ph[10][16] ph[10][17] ph[10][18] $abc$23348$new_n3439 $abc$23348$new_n4379 +00000 1 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce ph[11][19] $abc$23348$new_n4379 $abc$23348$new_n3445 $abc$23348$auto$rtlil.cc:2693:MuxGate$21588 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names ph[9][19] ph[9][17] ph[9][18] $abc$23348$new_n3294 $abc$23348$new_n3299 $abc$23348$new_n4381 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4381 ph[10][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21594 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] ph[7][17] ph[7][18] $abc$23348$new_n3001 $abc$23348$new_n2995 $abc$23348$new_n4383 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4383 ph[8][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21606 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][17] ph[5][18] $abc$23348$new_n2704 $abc$23348$new_n2711 $abc$23348$new_n4385 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4385 ph[6][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21618 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] ph[2][17] ph[2][18] $abc$23348$new_n2289 $abc$23348$new_n2294 $abc$23348$new_n4387 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4387 ph[3][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21636 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] ph[1][17] ph[1][18] $abc$23348$new_n2146 $abc$23348$new_n2151 $abc$23348$new_n4389 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4389 ph[2][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21642 +001 1 +011 1 +110 1 +111 1 +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21554 Q=xv[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21552 Q=xv[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21550 Q=xv[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21548 Q=xv[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21546 Q=xv[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21544 Q=xv[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21542 Q=xv[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21540 Q=xv[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21538 Q=xv[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21536 Q=xv[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21534 Q=xv[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21532 Q=xv[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21530 Q=xv[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21528 Q=xv[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21526 Q=xv[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21556 Q=xv[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21524 Q=yv[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21522 Q=yv[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21520 Q=yv[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21518 Q=yv[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21516 Q=yv[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21514 Q=yv[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21512 Q=yv[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21510 Q=yv[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21508 Q=yv[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21506 Q=yv[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21504 Q=yv[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21502 Q=yv[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21500 Q=yv[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21498 Q=yv[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21496 Q=yv[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21558 Q=yv[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21494 Q=xv[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21492 Q=xv[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21490 Q=xv[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21488 Q=xv[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21486 Q=xv[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21484 Q=xv[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21482 Q=xv[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21480 Q=xv[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21478 Q=xv[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21476 Q=xv[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21474 Q=xv[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21472 Q=xv[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21470 Q=xv[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21468 Q=xv[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21466 Q=xv[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21560 Q=xv[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21464 Q=yv[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21462 Q=yv[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21460 Q=yv[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21458 Q=yv[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21456 Q=yv[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21454 Q=yv[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21452 Q=yv[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21450 Q=yv[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21448 Q=yv[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21446 Q=yv[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21444 Q=yv[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21442 Q=yv[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21440 Q=yv[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21438 Q=yv[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21436 Q=yv[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21562 Q=yv[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21564 Q=ph[15][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21396 Q=xv[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21394 Q=xv[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21392 Q=xv[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21390 Q=xv[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21388 Q=xv[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21386 Q=xv[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21384 Q=xv[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21382 Q=xv[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21380 Q=xv[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21378 Q=xv[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21376 Q=xv[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21374 Q=xv[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21372 Q=xv[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21370 Q=xv[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21368 Q=xv[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21566 Q=xv[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21366 Q=yv[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21364 Q=yv[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21362 Q=yv[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21360 Q=yv[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21358 Q=yv[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21356 Q=yv[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21354 Q=yv[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21352 Q=yv[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21350 Q=yv[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21348 Q=yv[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21346 Q=yv[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21344 Q=yv[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21342 Q=yv[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21340 Q=yv[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21338 Q=yv[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21568 Q=yv[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21336 Q=ph[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21334 Q=ph[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21332 Q=ph[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21330 Q=ph[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21328 Q=ph[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21326 Q=ph[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21324 Q=ph[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21322 Q=ph[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21320 Q=ph[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21318 Q=ph[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21316 Q=ph[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21314 Q=ph[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21312 Q=ph[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21310 Q=ph[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21308 Q=ph[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21306 Q=ph[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21304 Q=ph[14][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21302 Q=ph[14][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21300 Q=ph[14][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21570 Q=ph[14][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21298 Q=xv[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21296 Q=xv[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21294 Q=xv[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21292 Q=xv[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21290 Q=xv[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21288 Q=xv[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21286 Q=xv[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21284 Q=xv[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21282 Q=xv[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21280 Q=xv[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21278 Q=xv[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21276 Q=xv[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21274 Q=xv[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21272 Q=xv[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21270 Q=xv[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21572 Q=xv[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21268 Q=yv[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21266 Q=yv[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21264 Q=yv[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21262 Q=yv[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21260 Q=yv[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21258 Q=yv[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21256 Q=yv[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21254 Q=yv[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21252 Q=yv[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21250 Q=yv[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21248 Q=yv[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21246 Q=yv[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21244 Q=yv[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21242 Q=yv[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21240 Q=yv[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21574 Q=yv[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21238 Q=ph[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21236 Q=ph[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21234 Q=ph[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21232 Q=ph[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21230 Q=ph[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21228 Q=ph[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21226 Q=ph[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21224 Q=ph[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21222 Q=ph[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21220 Q=ph[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21218 Q=ph[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21216 Q=ph[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21214 Q=ph[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21212 Q=ph[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21210 Q=ph[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21208 Q=ph[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21206 Q=ph[13][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21204 Q=ph[13][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21202 Q=ph[13][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21576 Q=ph[13][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21200 Q=xv[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21198 Q=xv[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21196 Q=xv[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21194 Q=xv[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21192 Q=xv[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21190 Q=xv[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21188 Q=xv[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21186 Q=xv[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21184 Q=xv[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21182 Q=xv[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21180 Q=xv[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21178 Q=xv[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21176 Q=xv[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21174 Q=xv[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21172 Q=xv[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21578 Q=xv[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21170 Q=yv[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21168 Q=yv[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21166 Q=yv[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21164 Q=yv[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21162 Q=yv[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21160 Q=yv[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21158 Q=yv[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21156 Q=yv[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21154 Q=yv[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21152 Q=yv[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21150 Q=yv[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21148 Q=yv[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21146 Q=yv[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21144 Q=yv[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21142 Q=yv[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21580 Q=yv[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21140 Q=ph[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21138 Q=ph[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21136 Q=ph[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21134 Q=ph[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21132 Q=ph[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21130 Q=ph[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21128 Q=ph[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21126 Q=ph[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21124 Q=ph[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21122 Q=ph[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21120 Q=ph[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21118 Q=ph[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21116 Q=ph[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21114 Q=ph[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21112 Q=ph[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21110 Q=ph[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21108 Q=ph[12][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21106 Q=ph[12][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21104 Q=ph[12][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21582 Q=ph[12][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21102 Q=xv[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21100 Q=xv[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21098 Q=xv[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21096 Q=xv[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21094 Q=xv[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21092 Q=xv[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21090 Q=xv[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21088 Q=xv[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21086 Q=xv[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21084 Q=xv[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21082 Q=xv[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21080 Q=xv[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21078 Q=xv[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21076 Q=xv[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21074 Q=xv[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21584 Q=xv[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21072 Q=yv[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21070 Q=yv[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21068 Q=yv[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21066 Q=yv[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21064 Q=yv[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21062 Q=yv[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21060 Q=yv[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21058 Q=yv[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21056 Q=yv[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21054 Q=yv[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21052 Q=yv[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21050 Q=yv[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21048 Q=yv[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21046 Q=yv[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21044 Q=yv[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21586 Q=yv[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21042 Q=ph[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21040 Q=ph[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21038 Q=ph[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21036 Q=ph[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21034 Q=ph[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21032 Q=ph[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21030 Q=ph[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21028 Q=ph[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21026 Q=ph[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21024 Q=ph[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21022 Q=ph[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21020 Q=ph[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21018 Q=ph[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21016 Q=ph[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21014 Q=ph[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21012 Q=ph[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21010 Q=ph[11][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21008 Q=ph[11][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21006 Q=ph[11][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21588 Q=ph[11][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21004 Q=xv[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21002 Q=xv[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21000 Q=xv[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20998 Q=xv[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20996 Q=xv[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20994 Q=xv[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20992 Q=xv[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20990 Q=xv[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20988 Q=xv[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20986 Q=xv[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20984 Q=xv[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20982 Q=xv[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20980 Q=xv[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20978 Q=xv[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20976 Q=xv[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21590 Q=xv[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20974 Q=yv[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20972 Q=yv[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20970 Q=yv[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20968 Q=yv[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20966 Q=yv[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20964 Q=yv[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20962 Q=yv[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20960 Q=yv[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20958 Q=yv[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20956 Q=yv[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20954 Q=yv[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20952 Q=yv[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20950 Q=yv[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20948 Q=yv[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20946 Q=yv[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21592 Q=yv[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20944 Q=ph[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20942 Q=ph[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20940 Q=ph[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20938 Q=ph[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20936 Q=ph[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20934 Q=ph[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20932 Q=ph[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20930 Q=ph[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20928 Q=ph[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20926 Q=ph[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20924 Q=ph[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20922 Q=ph[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20920 Q=ph[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20918 Q=ph[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20916 Q=ph[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20914 Q=ph[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20912 Q=ph[10][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20910 Q=ph[10][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20908 Q=ph[10][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21594 Q=ph[10][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20906 Q=xv[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20904 Q=xv[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20902 Q=xv[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20900 Q=xv[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20898 Q=xv[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20896 Q=xv[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20894 Q=xv[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20892 Q=xv[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20890 Q=xv[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20888 Q=xv[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20886 Q=xv[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20884 Q=xv[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20882 Q=xv[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20880 Q=xv[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20878 Q=xv[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21596 Q=xv[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20876 Q=yv[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20874 Q=yv[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20872 Q=yv[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20870 Q=yv[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20868 Q=yv[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20866 Q=yv[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20864 Q=yv[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20862 Q=yv[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20860 Q=yv[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20858 Q=yv[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20856 Q=yv[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20854 Q=yv[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20852 Q=yv[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20850 Q=yv[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20848 Q=yv[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21598 Q=yv[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20846 Q=ph[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20844 Q=ph[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20842 Q=ph[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20840 Q=ph[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20838 Q=ph[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20836 Q=ph[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20834 Q=ph[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20832 Q=ph[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20830 Q=ph[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20828 Q=ph[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20826 Q=ph[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20824 Q=ph[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20822 Q=ph[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20820 Q=ph[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20818 Q=ph[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20816 Q=ph[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20814 Q=ph[9][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20812 Q=ph[9][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20810 Q=ph[9][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21600 Q=ph[9][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20808 Q=xv[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20806 Q=xv[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20804 Q=xv[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20802 Q=xv[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20800 Q=xv[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20798 Q=xv[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20796 Q=xv[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20794 Q=xv[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20792 Q=xv[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20790 Q=xv[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20788 Q=xv[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20786 Q=xv[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20784 Q=xv[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20782 Q=xv[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20780 Q=xv[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21602 Q=xv[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20778 Q=yv[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20776 Q=yv[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20774 Q=yv[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20772 Q=yv[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20770 Q=yv[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20768 Q=yv[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20766 Q=yv[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20764 Q=yv[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20762 Q=yv[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20760 Q=yv[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20758 Q=yv[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20756 Q=yv[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20754 Q=yv[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20752 Q=yv[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20750 Q=yv[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21604 Q=yv[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20748 Q=ph[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20746 Q=ph[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20744 Q=ph[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20742 Q=ph[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20740 Q=ph[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20738 Q=ph[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20736 Q=ph[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20734 Q=ph[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20732 Q=ph[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20730 Q=ph[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20728 Q=ph[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20726 Q=ph[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20724 Q=ph[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20722 Q=ph[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20720 Q=ph[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20718 Q=ph[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20716 Q=ph[8][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20714 Q=ph[8][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20712 Q=ph[8][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21606 Q=ph[8][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20710 Q=xv[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20708 Q=xv[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20706 Q=xv[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20704 Q=xv[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20702 Q=xv[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20700 Q=xv[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20698 Q=xv[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20696 Q=xv[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20694 Q=xv[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20692 Q=xv[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20690 Q=xv[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20688 Q=xv[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20686 Q=xv[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20684 Q=xv[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20682 Q=xv[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21608 Q=xv[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20680 Q=yv[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20678 Q=yv[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20676 Q=yv[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20674 Q=yv[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20672 Q=yv[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20670 Q=yv[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20668 Q=yv[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20666 Q=yv[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20664 Q=yv[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20662 Q=yv[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20660 Q=yv[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20658 Q=yv[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20656 Q=yv[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20654 Q=yv[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20652 Q=yv[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21610 Q=yv[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20650 Q=ph[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20648 Q=ph[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20646 Q=ph[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20644 Q=ph[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20642 Q=ph[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20640 Q=ph[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20638 Q=ph[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20636 Q=ph[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20634 Q=ph[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20632 Q=ph[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20630 Q=ph[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20628 Q=ph[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20626 Q=ph[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20624 Q=ph[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20622 Q=ph[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20620 Q=ph[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20618 Q=ph[7][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20616 Q=ph[7][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20614 Q=ph[7][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21612 Q=ph[7][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20612 Q=xv[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20610 Q=xv[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20608 Q=xv[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20606 Q=xv[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20604 Q=xv[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20602 Q=xv[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20600 Q=xv[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20598 Q=xv[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20596 Q=xv[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20594 Q=xv[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20592 Q=xv[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20590 Q=xv[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20588 Q=xv[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20586 Q=xv[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20584 Q=xv[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21614 Q=xv[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20582 Q=yv[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20580 Q=yv[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20578 Q=yv[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20576 Q=yv[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20574 Q=yv[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20572 Q=yv[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20570 Q=yv[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20568 Q=yv[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20566 Q=yv[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20564 Q=yv[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20562 Q=yv[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20560 Q=yv[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20558 Q=yv[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20556 Q=yv[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20554 Q=yv[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21616 Q=yv[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20552 Q=ph[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20550 Q=ph[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20548 Q=ph[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20546 Q=ph[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20544 Q=ph[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20542 Q=ph[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20540 Q=ph[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20538 Q=ph[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20536 Q=ph[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20534 Q=ph[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20532 Q=ph[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20530 Q=ph[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20528 Q=ph[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20526 Q=ph[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20524 Q=ph[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20522 Q=ph[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20520 Q=ph[6][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20518 Q=ph[6][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20516 Q=ph[6][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21618 Q=ph[6][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20514 Q=xv[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20512 Q=xv[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20510 Q=xv[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20508 Q=xv[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20506 Q=xv[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20504 Q=xv[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20502 Q=xv[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20500 Q=xv[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20498 Q=xv[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20496 Q=xv[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20494 Q=xv[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20492 Q=xv[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20490 Q=xv[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20488 Q=xv[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20486 Q=xv[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21620 Q=xv[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20484 Q=yv[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20482 Q=yv[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20480 Q=yv[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20478 Q=yv[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20476 Q=yv[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20474 Q=yv[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20472 Q=yv[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20470 Q=yv[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20468 Q=yv[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20466 Q=yv[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20464 Q=yv[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20462 Q=yv[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20460 Q=yv[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20458 Q=yv[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20456 Q=yv[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21622 Q=yv[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20454 Q=ph[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20452 Q=ph[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20450 Q=ph[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20448 Q=ph[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20446 Q=ph[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20444 Q=ph[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20442 Q=ph[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20440 Q=ph[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20438 Q=ph[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20436 Q=ph[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20434 Q=ph[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20432 Q=ph[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20430 Q=ph[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20428 Q=ph[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20426 Q=ph[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20424 Q=ph[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20422 Q=ph[5][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20420 Q=ph[5][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20418 Q=ph[5][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21624 Q=ph[5][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20416 Q=xv[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20414 Q=xv[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20412 Q=xv[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20410 Q=xv[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20408 Q=xv[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20406 Q=xv[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20404 Q=xv[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20402 Q=xv[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20400 Q=xv[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20398 Q=xv[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20396 Q=xv[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20394 Q=xv[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20392 Q=xv[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20390 Q=xv[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20388 Q=xv[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21626 Q=xv[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20386 Q=yv[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20384 Q=yv[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20382 Q=yv[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20380 Q=yv[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20378 Q=yv[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20376 Q=yv[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20374 Q=yv[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20372 Q=yv[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20370 Q=yv[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20368 Q=yv[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20366 Q=yv[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20364 Q=yv[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20362 Q=yv[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20360 Q=yv[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20358 Q=yv[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21628 Q=yv[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20356 Q=ph[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20354 Q=ph[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20352 Q=ph[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20350 Q=ph[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20348 Q=ph[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20346 Q=ph[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20344 Q=ph[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20342 Q=ph[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20340 Q=ph[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20338 Q=ph[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20336 Q=ph[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20334 Q=ph[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20332 Q=ph[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20330 Q=ph[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20328 Q=ph[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20326 Q=ph[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20324 Q=ph[4][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20322 Q=ph[4][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20320 Q=ph[4][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21630 Q=ph[4][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20318 Q=xv[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20316 Q=xv[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20314 Q=xv[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20312 Q=xv[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20310 Q=xv[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20308 Q=xv[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20306 Q=xv[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20304 Q=xv[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20302 Q=xv[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20300 Q=xv[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20298 Q=xv[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20296 Q=xv[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20294 Q=xv[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20292 Q=xv[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20290 Q=xv[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21632 Q=xv[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20288 Q=yv[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20286 Q=yv[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20284 Q=yv[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20282 Q=yv[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20280 Q=yv[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20278 Q=yv[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20276 Q=yv[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20274 Q=yv[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20272 Q=yv[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20270 Q=yv[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20268 Q=yv[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20266 Q=yv[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20264 Q=yv[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20262 Q=yv[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20260 Q=yv[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21634 Q=yv[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20258 Q=ph[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20256 Q=ph[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20254 Q=ph[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20252 Q=ph[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20250 Q=ph[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20248 Q=ph[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20246 Q=ph[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20244 Q=ph[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20242 Q=ph[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20240 Q=ph[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20238 Q=ph[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20236 Q=ph[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20234 Q=ph[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20232 Q=ph[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20230 Q=ph[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20228 Q=ph[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20226 Q=ph[3][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20224 Q=ph[3][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20222 Q=ph[3][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21636 Q=ph[3][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20220 Q=xv[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20218 Q=xv[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20216 Q=xv[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20214 Q=xv[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20212 Q=xv[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20210 Q=xv[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20208 Q=xv[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20206 Q=xv[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20204 Q=xv[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20202 Q=xv[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20200 Q=xv[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20198 Q=xv[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20196 Q=xv[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20194 Q=xv[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20192 Q=xv[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21638 Q=xv[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20190 Q=yv[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20188 Q=yv[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20186 Q=yv[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20184 Q=yv[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20182 Q=yv[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20180 Q=yv[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20178 Q=yv[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20176 Q=yv[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20174 Q=yv[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20172 Q=yv[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20170 Q=yv[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20168 Q=yv[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20166 Q=yv[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20164 Q=yv[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20162 Q=yv[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21640 Q=yv[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20160 Q=ph[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20158 Q=ph[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20156 Q=ph[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20154 Q=ph[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20152 Q=ph[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20150 Q=ph[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20148 Q=ph[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20146 Q=ph[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20144 Q=ph[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20142 Q=ph[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20140 Q=ph[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20138 Q=ph[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20136 Q=ph[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20134 Q=ph[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20132 Q=ph[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20130 Q=ph[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20128 Q=ph[2][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20126 Q=ph[2][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20124 Q=ph[2][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21642 Q=ph[2][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20122 Q=xv[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20120 Q=xv[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20118 Q=xv[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20116 Q=xv[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20114 Q=xv[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20112 Q=xv[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20110 Q=xv[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20108 Q=xv[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20106 Q=xv[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20104 Q=xv[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20102 Q=xv[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20100 Q=xv[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20098 Q=xv[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20096 Q=xv[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20094 Q=xv[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21644 Q=xv[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20092 Q=yv[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20090 Q=yv[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20088 Q=yv[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20086 Q=yv[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20084 Q=yv[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20082 Q=yv[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20080 Q=yv[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20078 Q=yv[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20076 Q=yv[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20074 Q=yv[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20072 Q=yv[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20070 Q=yv[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20068 Q=yv[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20066 Q=yv[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20064 Q=yv[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21646 Q=yv[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20062 Q=ph[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20060 Q=ph[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20058 Q=ph[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20056 Q=ph[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20054 Q=ph[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20052 Q=ph[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20050 Q=ph[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20048 Q=ph[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20046 Q=ph[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20044 Q=ph[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20042 Q=ph[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20040 Q=ph[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20038 Q=ph[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20036 Q=ph[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20034 Q=ph[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20032 Q=ph[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20030 Q=ph[1][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20028 Q=ph[1][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20026 Q=ph[1][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21648 Q=ph[1][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20024 Q=o_xval[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20022 Q=o_xval[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20020 Q=o_xval[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20018 Q=o_xval[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20016 Q=o_xval[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20014 Q=o_xval[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20012 Q=o_xval[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20010 Q=o_xval[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20008 Q=o_xval[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20006 Q=o_xval[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20004 Q=o_xval[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20002 Q=o_xval[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21650 Q=o_xval[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20000 Q=o_yval[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19998 Q=o_yval[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19996 Q=o_yval[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19994 Q=o_yval[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19992 Q=o_yval[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19990 Q=o_yval[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19988 Q=o_yval[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19986 Q=o_yval[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19984 Q=o_yval[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19982 Q=o_yval[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19980 Q=o_yval[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19978 Q=o_yval[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21652 Q=o_yval[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21654 Q=o_aux R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19976 Q=xv[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19974 Q=xv[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19972 Q=xv[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19970 Q=xv[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19968 Q=xv[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19966 Q=xv[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19964 Q=xv[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19962 Q=xv[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19960 Q=xv[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19958 Q=xv[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19956 Q=xv[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19954 Q=xv[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19952 Q=xv[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19950 Q=xv[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19948 Q=xv[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21656 Q=xv[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19946 Q=yv[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19944 Q=yv[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19942 Q=yv[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19940 Q=yv[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19938 Q=yv[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19936 Q=yv[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19934 Q=yv[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19932 Q=yv[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19930 Q=yv[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19928 Q=yv[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19926 Q=yv[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19924 Q=yv[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19922 Q=yv[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19920 Q=yv[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19918 Q=yv[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21658 Q=yv[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19916 Q=ph[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19914 Q=ph[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19912 Q=ph[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19910 Q=ph[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19908 Q=ph[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19906 Q=ph[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19904 Q=ph[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19902 Q=ph[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19900 Q=ph[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19898 Q=ph[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19896 Q=ph[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19894 Q=ph[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19892 Q=ph[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19890 Q=ph[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19888 Q=ph[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19886 Q=ph[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19884 Q=ph[0][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19882 Q=ph[0][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19880 Q=ph[0][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21660 Q=ph[0][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19878 Q=ax[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19876 Q=ax[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19874 Q=ax[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19872 Q=ax[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19870 Q=ax[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19868 Q=ax[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19866 Q=ax[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19864 Q=ax[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19862 Q=ax[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19860 Q=ax[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19858 Q=ax[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19856 Q=ax[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19854 Q=ax[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19852 Q=ax[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19850 Q=ax[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19848 Q=ax[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21662 Q=ax[16] R=i_reset +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif new file mode 100644 index 00000000000..b9328ff6c7b --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif @@ -0,0 +1,19093 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model cordictanh +.inputs CLK EN z[-24] z[-23] z[-22] z[-21] z[-20] z[-19] z[-18] z[-17] z[-16] z[-15] z[-14] z[-13] z[-12] z[-11] z[-10] z[-9] z[-8] z[-7] z[-6] z[-5] z[-4] z[-3] z[-2] z[-1] z[0] z[1] z[2] z[3] z[4] z[5] z[6] z[7] +.outputs out[-24] out[-23] out[-22] out[-21] out[-20] out[-19] out[-18] out[-17] out[-16] out[-15] out[-14] out[-13] out[-12] out[-11] out[-10] out[-9] out[-8] out[-7] out[-6] out[-5] out[-4] out[-3] out[-2] out[-1] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] +.names $false +.names $true +1 +.names $undef +.names $abc$10488$new_n419 $abc$10488$new_n384 z[-13] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10002 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names z_[-13] $abc$10488$new_n416 z_[7] $abc$10488$new_n407 $abc$10488$new_n385 $abc$10488$new_n384 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$10488$new_n406 z_[-14] $abc$10488$new_n386 $abc$10488$new_n385 +001 1 +100 1 +101 1 +111 1 +.names $abc$10488$new_n403 $abc$10488$new_n405 z_[-15] $abc$10488$new_n387 $abc$10488$new_n386 +0000 1 +0001 1 +0010 1 +0100 1 +1000 1 +1100 1 +.names z_[-16] $abc$10488$new_n402 $abc$10488$new_n388 $abc$10488$new_n387 +001 1 +100 1 +101 1 +111 1 +.names z_[-17] $abc$10488$new_n401 $abc$10488$new_n389 $abc$10488$new_n388 +000 1 +100 1 +101 1 +110 1 +.names $abc$10488$new_n400 z_[-18] $abc$10488$new_n390 $abc$10488$new_n389 +000 1 +100 1 +101 1 +110 1 +.names z_[-19] $abc$10488$new_n399 $abc$10488$new_n391 $abc$10488$new_n390 +001 1 +100 1 +101 1 +111 1 +.names z_[-20] $abc$10488$new_n398 $abc$10488$new_n392 $abc$10488$new_n391 +001 1 +100 1 +101 1 +111 1 +.names z_[-22] z_[-21] $abc$10488$new_n397 $abc$10488$new_n396 $abc$10488$new_n393 $abc$10488$new_n392 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names z_[-24] z_[-23] $abc$10488$new_n395 $abc$10488$new_n394 $abc$10488$new_n393 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names LOOKUP.index[0] LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[1] $abc$10488$new_n394 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[0] LOOKUP.index[1] $abc$10488$new_n395 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[0] $abc$10488$new_n396 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[0] $abc$10488$new_n397 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +.names LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[0] LOOKUP.index[2] LOOKUP.index[1] $abc$10488$new_n398 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names LOOKUP.index[2] LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n399 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names LOOKUP.index[2] LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[3] LOOKUP.index[0] $abc$10488$new_n400 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names LOOKUP.index[2] LOOKUP.index[0] LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[1] $abc$10488$new_n401 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[2] $abc$10488$new_n402 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n404 LOOKUP.index[4] $abc$10488$new_n403 +10 1 +.names LOOKUP.index[2] LOOKUP.index[3] $abc$10488$new_n404 +00 1 +.names LOOKUP.index[0] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[1] $abc$10488$new_n405 +11110 1 +.names LOOKUP.index[0] LOOKUP.index[2] LOOKUP.index[1] LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n406 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[-14] $abc$10488$new_n406 $abc$10488$new_n408 $abc$10488$new_n407 +000 1 +001 1 +011 1 +101 1 +.names z_[-15] $abc$10488$new_n405 $abc$10488$new_n403 $abc$10488$new_n409 $abc$10488$new_n408 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1101 1 +1111 1 +.names z_[-16] $abc$10488$new_n402 $abc$10488$new_n410 $abc$10488$new_n409 +000 1 +001 1 +011 1 +101 1 +.names z_[-17] $abc$10488$new_n401 $abc$10488$new_n411 $abc$10488$new_n410 +000 1 +001 1 +010 1 +100 1 +.names z_[-18] $abc$10488$new_n400 $abc$10488$new_n412 $abc$10488$new_n411 +010 1 +100 1 +110 1 +111 1 +.names z_[-19] $abc$10488$new_n399 $abc$10488$new_n413 $abc$10488$new_n412 +000 1 +001 1 +011 1 +101 1 +.names z_[-20] $abc$10488$new_n398 $abc$10488$new_n414 $abc$10488$new_n413 +000 1 +001 1 +011 1 +101 1 +.names z_[-22] $abc$10488$new_n397 z_[-21] $abc$10488$new_n396 $abc$10488$new_n415 $abc$10488$new_n414 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names z_[-24] $abc$10488$new_n395 z_[-23] $abc$10488$new_n394 $abc$10488$new_n415 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names LOOKUP.index[0] $abc$10488$new_n418 $abc$10488$new_n403 $abc$10488$new_n417 $abc$10488$new_n416 +0000 1 +0010 1 +1000 1 +1001 1 +.names LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n417 +1111 1 +.names LOOKUP.index[0] LOOKUP.index[3] LOOKUP.index[2] LOOKUP.index[1] LOOKUP.index[4] $abc$10488$new_n418 +11100 1 +.names EN $abc$10488$new_n420 $abc$10488$new_n419 +00 1 +.names $abc$10488$new_n427 $abc$10488$new_n425 $abc$10488$new_n423 $abc$10488$new_n421 $abc$10488$new_n420 +1111 1 +.names $abc$10488$new_n422 z_[0] z_[1] z_[6] z_[-23] $abc$10488$new_n421 +10000 1 +.names z_[-4] z_[-3] z_[-2] z_[-1] $abc$10488$new_n422 +0000 1 +.names $abc$10488$new_n424 z_[-8] z_[-7] z_[-6] z_[-5] $abc$10488$new_n423 +10000 1 +.names z_[-12] z_[-11] z_[-10] z_[-9] $abc$10488$new_n424 +0000 1 +.names $abc$10488$new_n426 z_[2] z_[3] z_[-14] z_[-13] $abc$10488$new_n425 +10000 1 +.names z_[4] z_[5] z_[7] z_[-24] $abc$10488$new_n426 +0000 1 +.names $abc$10488$new_n428 z_[-22] z_[-21] z_[-20] z_[-19] $abc$10488$new_n427 +10000 1 +.names z_[-18] z_[-17] z_[-16] z_[-15] $abc$10488$new_n428 +0000 1 +.names $abc$10488$new_n430 z[-14] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10004 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-14] $abc$10488$new_n406 $abc$10488$new_n431 $abc$10488$new_n430 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n386 $abc$10488$new_n408 $abc$10488$new_n431 +000 1 +010 1 +110 1 +111 1 +.names $abc$10488$new_n419 $abc$10488$new_n433 z[-15] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10006 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$10488$new_n434 z_[7] $abc$10488$new_n409 $abc$10488$new_n387 $abc$10488$new_n433 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names z_[-15] $abc$10488$new_n405 $abc$10488$new_n403 $abc$10488$new_n434 +001 1 +010 1 +011 1 +100 1 +.names $abc$10488$new_n436 z[-16] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10008 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-16] $abc$10488$new_n402 $abc$10488$new_n437 $abc$10488$new_n436 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n388 $abc$10488$new_n410 $abc$10488$new_n437 +000 1 +010 1 +100 1 +101 1 +.names $abc$10488$new_n439 z[-17] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10010 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-17] $abc$10488$new_n401 $abc$10488$new_n440 $abc$10488$new_n439 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n389 $abc$10488$new_n411 $abc$10488$new_n440 +001 1 +011 1 +110 1 +111 1 +.names $abc$10488$new_n442 z[-18] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10012 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-18] $abc$10488$new_n400 $abc$10488$new_n443 $abc$10488$new_n442 +1000 1 +1011 1 +1101 1 +1110 1 +.names z_[7] $abc$10488$new_n390 $abc$10488$new_n412 $abc$10488$new_n443 +001 1 +011 1 +110 1 +111 1 +.names $abc$10488$new_n445 z[-19] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10014 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-19] $abc$10488$new_n399 $abc$10488$new_n446 $abc$10488$new_n445 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n391 $abc$10488$new_n413 $abc$10488$new_n446 +000 1 +010 1 +100 1 +101 1 +.names $abc$10488$new_n448 z[-20] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10016 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-20] $abc$10488$new_n398 $abc$10488$new_n449 $abc$10488$new_n448 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n392 $abc$10488$new_n414 $abc$10488$new_n449 +000 1 +010 1 +100 1 +101 1 +.names $abc$10488$new_n451 z[-21] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10018 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-21] $abc$10488$new_n396 $abc$10488$new_n452 $abc$10488$new_n451 +1000 1 +1011 1 +1101 1 +1110 1 +.names z_[7] z_[-22] $abc$10488$new_n397 $abc$10488$new_n415 $abc$10488$new_n393 $abc$10488$new_n452 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$10488$new_n454 z[-22] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10020 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-22] $abc$10488$new_n397 $abc$10488$new_n455 $abc$10488$new_n454 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n393 $abc$10488$new_n415 $abc$10488$new_n455 +001 1 +011 1 +110 1 +111 1 +.names EN z[-23] $abc$10488$new_n420 $abc$10488$new_n457 $abc$10488$auto$rtlil.cc:2693:MuxGate$10022 +0000 1 +0100 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names z_[-23] $abc$10488$new_n394 z_[7] z_[-24] $abc$10488$new_n395 $abc$10488$new_n457 +00000 1 +00110 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11110 1 +.names EN $abc$10488$new_n395 z_[-24] $abc$10488$new_n420 z[-24] $abc$10488$auto$rtlil.cc:2693:MuxGate$10024 +00000 1 +00001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names EN $abc$10488$new_n419 z[7] $abc$10488$new_n460 $abc$10488$new_n485 $abc$10488$auto$rtlil.cc:2693:MuxGate$10026 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[6] $abc$10488$new_n461 z_[7] $abc$10488$new_n460 +001 1 +010 1 +011 1 +.names z_[2] z_[3] z_[4] z_[5] $abc$10488$new_n462 $abc$10488$new_n461 +00000 1 +.names z_[0] z_[1] $abc$10488$new_n417 $abc$10488$new_n405 $abc$10488$new_n463 $abc$10488$new_n462 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names z_[-2] $abc$10488$new_n484 z_[-1] $abc$10488$new_n483 $abc$10488$new_n464 $abc$10488$new_n463 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[-4] $abc$10488$new_n482 z_[-3] $abc$10488$new_n479 $abc$10488$new_n465 $abc$10488$new_n464 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names z_[-6] $abc$10488$new_n478 z_[-5] $abc$10488$new_n477 $abc$10488$new_n466 $abc$10488$new_n465 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[-8] $abc$10488$new_n476 z_[-7] $abc$10488$new_n475 $abc$10488$new_n467 $abc$10488$new_n466 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names z_[-10] $abc$10488$new_n474 z_[-9] $abc$10488$new_n473 $abc$10488$new_n468 $abc$10488$new_n467 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[-11] $abc$10488$new_n472 $abc$10488$new_n469 $abc$10488$new_n468 +000 1 +001 1 +010 1 +100 1 +.names z_[-12] $abc$10488$new_n471 $abc$10488$new_n470 $abc$10488$new_n469 +011 1 +101 1 +110 1 +111 1 +.names z_[-13] $abc$10488$new_n416 $abc$10488$new_n407 $abc$10488$new_n470 +010 1 +100 1 +110 1 +111 1 +.names LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n471 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[0] LOOKUP.index[3] $abc$10488$new_n472 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[0] $abc$10488$new_n473 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names LOOKUP.index[0] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[1] LOOKUP.index[3] $abc$10488$new_n474 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[0] LOOKUP.index[1] $abc$10488$new_n475 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names LOOKUP.index[2] LOOKUP.index[4] LOOKUP.index[0] LOOKUP.index[1] LOOKUP.index[3] $abc$10488$new_n476 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[1] LOOKUP.index[4] LOOKUP.index[0] LOOKUP.index[2] $abc$10488$new_n477 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names LOOKUP.index[0] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n478 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n481 $abc$10488$new_n403 $abc$10488$new_n480 $abc$10488$new_n479 +100 1 +101 1 +110 1 +.names LOOKUP.index[0] LOOKUP.index[1] $abc$10488$new_n480 +11 1 +.names LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[0] $abc$10488$new_n481 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[0] LOOKUP.index[1] LOOKUP.index[2] $abc$10488$new_n482 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[1] $abc$10488$new_n403 $abc$10488$new_n481 $abc$10488$new_n483 +000 1 +001 1 +101 1 +110 1 +111 1 +.names LOOKUP.index[0] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[1] $abc$10488$new_n484 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names z_[7] z_[5] $abc$10488$new_n486 z_[4] $abc$10488$new_n485 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names z_[2] z_[3] $abc$10488$new_n487 $abc$10488$new_n486 +111 1 +.names z_[0] $abc$10488$new_n417 z_[1] $abc$10488$new_n405 $abc$10488$new_n488 $abc$10488$new_n487 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n484 z_[-2] z_[-1] $abc$10488$new_n483 $abc$10488$new_n489 $abc$10488$new_n488 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n482 z_[-4] z_[-3] $abc$10488$new_n479 $abc$10488$new_n490 $abc$10488$new_n489 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n478 z_[-6] z_[-5] $abc$10488$new_n477 $abc$10488$new_n491 $abc$10488$new_n490 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n476 z_[-8] z_[-7] $abc$10488$new_n475 $abc$10488$new_n492 $abc$10488$new_n491 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n474 z_[-10] z_[-9] $abc$10488$new_n473 $abc$10488$new_n493 $abc$10488$new_n492 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n472 z_[-11] $abc$10488$new_n494 $abc$10488$new_n493 +001 1 +100 1 +101 1 +111 1 +.names $abc$10488$new_n471 z_[-12] $abc$10488$new_n495 $abc$10488$new_n494 +001 1 +100 1 +101 1 +111 1 +.names $abc$10488$new_n416 z_[-13] $abc$10488$new_n385 $abc$10488$new_n495 +001 1 +100 1 +101 1 +111 1 +.names $abc$10488$new_n658 divider.x[7] $abc$10488$new_n497 $abc$10488$new_n671 $abc$10488$auto$rtlil.cc:2693:MuxGate$10028 +0000 1 +0010 1 +0100 1 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$10488$new_n657 divider.y_[6] divider.y_[7] $abc$10488$new_n642 $abc$10488$new_n498 $abc$10488$new_n497 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11101 1 +11111 1 +.names $abc$10488$new_n641 $abc$10488$new_n638 $abc$10488$new_n639 $abc$10488$new_n499 $abc$10488$new_n636 $abc$10488$new_n498 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$10488$new_n634 divider.y_[2] $abc$10488$new_n635 $abc$10488$new_n500 $abc$10488$new_n632 $abc$10488$new_n499 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$10488$new_n631 divider.y_[0] divider.y_[1] $abc$10488$new_n630 $abc$10488$new_n501 $abc$10488$new_n500 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n629 divider.y_[-2] divider.y_[-1] $abc$10488$new_n628 $abc$10488$new_n502 $abc$10488$new_n501 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n627 divider.y_[-4] divider.y_[-3] $abc$10488$new_n626 $abc$10488$new_n503 $abc$10488$new_n502 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names divider.y_[-6] divider.y_[-5] $abc$10488$new_n625 $abc$10488$new_n624 $abc$10488$new_n504 $abc$10488$new_n503 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n623 divider.y_[-8] divider.y_[-7] $abc$10488$new_n622 $abc$10488$new_n505 $abc$10488$new_n504 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names divider.y_[-10] divider.y_[-9] $abc$10488$new_n619 $abc$10488$new_n621 $abc$10488$new_n506 $abc$10488$new_n505 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n617 divider.y_[-12] divider.y_[-11] $abc$10488$new_n615 $abc$10488$new_n507 $abc$10488$new_n506 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n611 divider.y_[-14] divider.y_[-13] $abc$10488$new_n613 $abc$10488$new_n508 $abc$10488$new_n507 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n609 divider.y_[-16] divider.y_[-15] $abc$10488$new_n607 $abc$10488$new_n509 $abc$10488$new_n508 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n2199 divider.y_[-18] divider.y_[-17] $abc$10488$new_n596 $abc$10488$new_n510 $abc$10488$new_n509 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n591 divider.y_[-20] divider.y_[-19] $abc$10488$new_n586 $abc$10488$new_n511 $abc$10488$new_n510 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n572 divider.y_[-22] divider.y_[-21] $abc$10488$new_n560 $abc$10488$new_n512 $abc$10488$new_n511 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names divider.y_[-23] $abc$10488$new_n513 $abc$10488$new_n549 $abc$10488$new_n537 divider.y_[-24] $abc$10488$new_n512 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n529 $abc$10488$new_n514 divider.i[4] $abc$10488$new_n536 $abc$10488$new_n524 $abc$10488$new_n513 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names divider.i[3] $abc$10488$new_n515 $abc$10488$new_n519 $abc$10488$new_n514 +001 1 +011 1 +110 1 +111 1 +.names divider.i[2] $abc$10488$new_n516 $abc$10488$new_n518 $abc$10488$new_n515 +010 1 +011 1 +101 1 +111 1 +.names divider.i[1] divider.i[0] $abc$10488$new_n517 divider.x[2] divider.x[1] $abc$10488$new_n516 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 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divider.x[-16] $abc$10488$new_n996 $abc$10488$new_n999 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-15] divider.x[-15] $abc$10488$new_n999 $abc$10488$new_n1000 +001 1 +010 1 +100 1 +111 1 +.names divider.y[-12] divider.x[-12] divider.y[-13] divider.x[-13] $abc$10488$new_n1002 $abc$10488$new_n1001 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names divider.y[-15] divider.x[-15] divider.y[-14] divider.x[-14] $abc$10488$new_n999 $abc$10488$new_n1002 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-13] divider.x[-13] $abc$10488$new_n1002 $abc$10488$new_n1003 +001 1 +010 1 +100 1 +111 1 +.names divider.y[-10] divider.x[-10] divider.y[-11] divider.x[-11] $abc$10488$new_n1005 $abc$10488$new_n1004 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names divider.y[-13] divider.x[-13] divider.y[-12] divider.x[-12] $abc$10488$new_n1002 $abc$10488$new_n1005 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-11] divider.x[-11] $abc$10488$new_n1005 $abc$10488$new_n1006 +001 1 +010 1 +100 1 +111 1 +.names divider.y[-8] divider.x[-8] divider.y[-9] divider.x[-9] $abc$10488$new_n1008 $abc$10488$new_n1007 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names divider.y[-11] divider.x[-11] divider.y[-10] divider.x[-10] $abc$10488$new_n1005 $abc$10488$new_n1008 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 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divider.x[0] divider.y[-1] divider.x[-1] $abc$10488$new_n1020 $abc$10488$new_n1019 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names divider.y[-3] divider.x[-3] divider.y[-2] divider.x[-2] $abc$10488$new_n1017 $abc$10488$new_n1020 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-1] divider.x[-1] $abc$10488$new_n1020 $abc$10488$new_n1021 +000 1 +011 1 +101 1 +110 1 +.names divider.y[2] divider.x[2] divider.y[1] divider.x[1] $abc$10488$new_n1023 $abc$10488$new_n1022 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names divider.y[-1] divider.x[-1] divider.y[0] divider.x[0] $abc$10488$new_n1020 $abc$10488$new_n1023 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 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$abc$10488$new_n1026 $abc$10488$new_n1029 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[5] divider.x[5] $abc$10488$new_n1029 $abc$10488$new_n1030 +001 1 +010 1 +100 1 +111 1 +.names divider.y[5] divider.x[5] divider.y[6] divider.x[6] $abc$10488$new_n1029 $abc$10488$new_n1031 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[4] $abc$10488$new_n1180 $abc$10488$new_n1035 z_[7] $abc$10488$new_n1034 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$10488$new_n1179 $abc$10488$new_n1177 $abc$10488$new_n1176 $abc$10488$new_n1203 $abc$10488$new_n1036 $abc$10488$new_n1035 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.y[0] $abc$10488$new_n1173 divider.y[1] $abc$10488$new_n1172 $abc$10488$new_n1037 $abc$10488$new_n1036 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n1166 $abc$10488$new_n1161 $abc$10488$new_n1170 $abc$10488$new_n1038 $abc$10488$new_n1171 $abc$10488$new_n1037 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.y[-6] $abc$10488$new_n1160 divider.y[-5] $abc$10488$new_n1159 $abc$10488$new_n1039 $abc$10488$new_n1038 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-8] $abc$10488$new_n1158 divider.y[-7] $abc$10488$new_n1157 $abc$10488$new_n1040 $abc$10488$new_n1039 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 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$abc$10488$new_n1043 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names divider.y[-18] $abc$10488$new_n1136 divider.y[-17] $abc$10488$new_n1131 $abc$10488$new_n1045 $abc$10488$new_n1044 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-20] $abc$10488$new_n1126 divider.y[-19] $abc$10488$new_n1121 $abc$10488$new_n1046 $abc$10488$new_n1045 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-22] $abc$10488$new_n1107 divider.y[-21] $abc$10488$new_n2217 $abc$10488$new_n1047 $abc$10488$new_n1046 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +.names $abc$10488$new_n2213 divider.y[-24] divider.y[-23] $abc$10488$new_n2210 $abc$10488$new_n1047 +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names LOOKUP.index[2] $abc$10488$new_n1051 $abc$10488$new_n1053 $abc$10488$new_n1050 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1052 divider.x[-8] divider.x[-9] $abc$10488$new_n1051 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-10] divider.x[-11] $abc$10488$new_n1052 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1054 divider.x[-12] divider.x[-13] $abc$10488$new_n1053 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-14] divider.x[-15] $abc$10488$new_n1054 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1056 divider.x[-18] divider.x[-19] $abc$10488$new_n1055 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.x[-16] divider.x[-17] $abc$10488$new_n1056 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1059 $abc$10488$new_n1062 $abc$10488$new_n1058 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] $abc$10488$new_n1060 $abc$10488$new_n1061 $abc$10488$new_n1059 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.x[4] divider.x[3] $abc$10488$new_n1060 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.x[2] divider.x[1] $abc$10488$new_n1061 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] divider.x[7] divider.x[6] divider.x[5] $abc$10488$new_n1062 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] $abc$10488$new_n1064 $abc$10488$new_n1066 $abc$10488$new_n1063 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1065 divider.x[0] divider.x[-1] $abc$10488$new_n1064 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-2] divider.x[-3] $abc$10488$new_n1065 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1067 divider.x[-4] divider.x[-5] $abc$10488$new_n1066 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-6] divider.x[-7] $abc$10488$new_n1067 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1073 $abc$10488$new_n1075 $abc$10488$new_n1072 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1074 divider.x[-9] divider.x[-10] $abc$10488$new_n1073 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-11] divider.x[-12] $abc$10488$new_n1074 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1076 divider.x[-13] divider.x[-14] $abc$10488$new_n1075 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-15] divider.x[-16] $abc$10488$new_n1076 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] $abc$10488$new_n1079 $abc$10488$new_n1080 $abc$10488$new_n1078 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.x[-17] divider.x[-18] $abc$10488$new_n1079 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.x[-19] divider.x[-20] $abc$10488$new_n1080 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.x[-21] divider.x[-22] $abc$10488$new_n1082 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1085 $abc$10488$new_n1087 $abc$10488$new_n1084 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1086 divider.x[7] divider.x[6] $abc$10488$new_n1085 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[5] divider.x[4] $abc$10488$new_n1086 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1088 divider.x[3] divider.x[2] $abc$10488$new_n1087 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[1] divider.x[0] $abc$10488$new_n1088 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1090 $abc$10488$new_n1092 $abc$10488$new_n1089 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1091 divider.x[-1] divider.x[-2] $abc$10488$new_n1090 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-3] divider.x[-4] $abc$10488$new_n1091 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1093 divider.x[-5] divider.x[-6] $abc$10488$new_n1092 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-7] divider.x[-8] $abc$10488$new_n1093 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1096 $abc$10488$new_n1099 divider.x[7] $abc$10488$new_n1095 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1097 $abc$10488$new_n1098 $abc$10488$new_n1096 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1065 divider.x[-4] divider.x[-5] $abc$10488$new_n1097 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1061 divider.x[0] divider.x[-1] $abc$10488$new_n1098 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1060 divider.x[6] divider.x[5] $abc$10488$new_n1099 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[2] $abc$10488$new_n1102 $abc$10488$new_n1103 $abc$10488$new_n1101 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1067 divider.x[-8] divider.x[-9] $abc$10488$new_n1102 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1052 divider.x[-12] divider.x[-13] $abc$10488$new_n1103 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] $abc$10488$new_n1108 $abc$10488$new_n1115 $abc$10488$new_n1107 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1109 $abc$10488$new_n1112 $abc$10488$new_n1108 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1110 $abc$10488$new_n1111 $abc$10488$new_n1109 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1086 divider.x[3] divider.x[2] $abc$10488$new_n1110 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] LOOKUP.index[1] divider.x[7] divider.x[6] $abc$10488$new_n1111 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[2] $abc$10488$new_n1113 $abc$10488$new_n1114 $abc$10488$new_n1112 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1091 divider.x[-5] divider.x[-6] $abc$10488$new_n1113 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1088 divider.x[-1] divider.x[-2] $abc$10488$new_n1114 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1116 $abc$10488$new_n1119 $abc$10488$new_n1120 $abc$10488$new_n1115 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1117 $abc$10488$new_n1118 $abc$10488$new_n1116 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1093 divider.x[-9] divider.x[-10] $abc$10488$new_n1117 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1074 divider.x[-13] divider.x[-14] $abc$10488$new_n1118 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] $abc$10488$new_n1076 $abc$10488$new_n1079 $abc$10488$new_n1119 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] $abc$10488$new_n1080 $abc$10488$new_n1082 $abc$10488$new_n1120 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] $abc$10488$new_n1122 $abc$10488$new_n1124 $abc$10488$new_n403 $abc$10488$new_n1055 $abc$10488$new_n1121 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1123 $abc$10488$new_n1062 divider.x[7] $abc$10488$new_n1122 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1059 $abc$10488$new_n1064 $abc$10488$new_n1123 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1125 LOOKUP.index[2] $abc$10488$new_n1053 $abc$10488$new_n1124 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names LOOKUP.index[2] $abc$10488$new_n1066 $abc$10488$new_n1051 $abc$10488$new_n1125 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] $abc$10488$new_n1127 $abc$10488$new_n1129 $abc$10488$new_n1126 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1128 $abc$10488$new_n1085 divider.x[7] $abc$10488$new_n1127 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1087 $abc$10488$new_n1090 $abc$10488$new_n1128 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1130 $abc$10488$new_n1075 $abc$10488$new_n1078 $abc$10488$new_n1129 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1092 $abc$10488$new_n1073 $abc$10488$new_n1130 +001 1 +011 1 +110 1 +111 1 +.names $abc$10488$new_n1132 LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n1135 divider.x[7] $abc$10488$new_n1131 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$10488$new_n1133 LOOKUP.index[1] $abc$10488$new_n403 $abc$10488$new_n1054 $abc$10488$new_n1056 $abc$10488$new_n1132 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n1134 LOOKUP.index[2] $abc$10488$new_n1103 $abc$10488$new_n1133 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1097 $abc$10488$new_n1102 $abc$10488$new_n1134 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1099 $abc$10488$new_n1098 $abc$10488$new_n1135 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] $abc$10488$new_n1137 $abc$10488$new_n1139 $abc$10488$new_n1136 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1138 $abc$10488$new_n1118 $abc$10488$new_n1119 $abc$10488$new_n1137 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1113 $abc$10488$new_n1117 $abc$10488$new_n1138 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1140 $abc$10488$new_n1141 $abc$10488$new_n1139 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1110 $abc$10488$new_n1114 $abc$10488$new_n1140 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1111 divider.x[7] $abc$10488$new_n1141 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1143 $abc$10488$new_n1063 $abc$10488$new_n1050 $abc$10488$new_n1142 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1058 divider.x[7] $abc$10488$new_n1143 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1145 $abc$10488$new_n1089 $abc$10488$new_n1072 $abc$10488$new_n1144 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1084 divider.x[7] $abc$10488$new_n1145 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1147 $abc$10488$new_n1112 $abc$10488$new_n1116 $abc$10488$new_n1146 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1109 divider.x[7] $abc$10488$new_n1147 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1149 $abc$10488$new_n1096 $abc$10488$new_n1101 $abc$10488$new_n1148 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1099 $abc$10488$new_n1149 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1151 $abc$10488$new_n1123 $abc$10488$new_n1125 $abc$10488$new_n1150 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1062 $abc$10488$new_n1151 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1153 $abc$10488$new_n1128 $abc$10488$new_n1130 $abc$10488$new_n1152 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] LOOKUP.index[3] divider.x[7] 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$abc$10488$new_n1503 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1507 $abc$10488$new_n1509 $abc$10488$new_n1506 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1508 divider.y[-10] divider.y[-11] $abc$10488$new_n1507 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[-8] divider.y[-9] $abc$10488$new_n1508 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] $abc$10488$new_n1510 $abc$10488$new_n1511 $abc$10488$new_n1509 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.y[-12] divider.y[-13] $abc$10488$new_n1510 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.y[-14] divider.y[-15] $abc$10488$new_n1511 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] $abc$10488$new_n1513 $abc$10488$new_n1514 $abc$10488$new_n1512 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.y[-16] divider.y[-17] $abc$10488$new_n1513 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.y[-18] divider.y[-19] $abc$10488$new_n1514 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.y[-20] divider.y[-21] $abc$10488$new_n1516 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1519 $abc$10488$new_n1521 $abc$10488$new_n1518 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1520 divider.y[2] divider.y[1] $abc$10488$new_n1519 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[4] divider.y[3] $abc$10488$new_n1520 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] divider.y[7] divider.y[6] divider.y[5] $abc$10488$new_n1521 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] $abc$10488$new_n1523 $abc$10488$new_n1525 $abc$10488$new_n1522 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1524 divider.y[-2] divider.y[-3] $abc$10488$new_n1523 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[0] divider.y[-1] $abc$10488$new_n1524 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1526 divider.y[-6] divider.y[-7] $abc$10488$new_n1525 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[-4] divider.y[-5] $abc$10488$new_n1526 +000 1 +010 1 +100 1 +101 1 +.names divider.x[-24] LOOKUP.index[4] $abc$10488$new_n1528 $abc$10488$new_n1535 $abc$10488$new_n1527 +1000 1 +1010 1 +1100 1 +1101 1 +.names LOOKUP.index[3] $abc$10488$new_n1529 $abc$10488$new_n1532 $abc$10488$new_n1528 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1530 $abc$10488$new_n1531 $abc$10488$new_n1529 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1486 divider.y[7] divider.y[6] $abc$10488$new_n1530 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1490 divider.y[3] divider.y[2] $abc$10488$new_n1531 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[2] $abc$10488$new_n1533 $abc$10488$new_n1534 $abc$10488$new_n1532 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1492 divider.y[-1] divider.y[-2] $abc$10488$new_n1533 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1496 divider.y[-5] divider.y[-6] $abc$10488$new_n1534 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1536 $abc$10488$new_n1539 $abc$10488$new_n1540 $abc$10488$new_n1535 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1537 $abc$10488$new_n1538 $abc$10488$new_n1536 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1498 divider.y[-9] divider.y[-10] $abc$10488$new_n1537 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1500 divider.y[-13] divider.y[-14] $abc$10488$new_n1538 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1501 divider.y[-19] divider.y[-20] $abc$10488$new_n1539 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1503 divider.y[-23] divider.y[-24] $abc$10488$new_n1540 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] $abc$10488$new_n1544 $abc$10488$new_n1542 $abc$10488$new_n1539 $abc$10488$new_n404 $abc$10488$new_n1541 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1543 $abc$10488$new_n1530 divider.y[7] $abc$10488$new_n1542 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1531 $abc$10488$new_n1533 $abc$10488$new_n1543 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1545 LOOKUP.index[2] $abc$10488$new_n1538 $abc$10488$new_n1544 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names LOOKUP.index[2] $abc$10488$new_n1534 $abc$10488$new_n1537 $abc$10488$new_n1545 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1548 $abc$10488$new_n1551 divider.y[7] $abc$10488$new_n1547 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1549 $abc$10488$new_n1550 $abc$10488$new_n1548 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1524 divider.y[2] divider.y[1] $abc$10488$new_n1549 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1526 divider.y[-2] divider.y[-3] $abc$10488$new_n1550 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1520 divider.y[6] divider.y[5] $abc$10488$new_n1551 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[2] $abc$10488$new_n1554 $abc$10488$new_n1555 $abc$10488$new_n1553 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1508 divider.y[-6] divider.y[-7] $abc$10488$new_n1554 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1510 divider.y[-10] divider.y[-11] $abc$10488$new_n1555 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] $abc$10488$new_n1511 $abc$10488$new_n1513 $abc$10488$new_n1556 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1491 $abc$10488$new_n1495 $abc$10488$new_n1561 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1485 $abc$10488$new_n1489 $abc$10488$new_n1562 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1487 divider.y[7] $abc$10488$new_n1563 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1565 $abc$10488$new_n1567 $abc$10488$new_n1564 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1566 $abc$10488$new_n1521 divider.y[7] $abc$10488$new_n1565 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1519 $abc$10488$new_n1523 $abc$10488$new_n1566 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1568 $abc$10488$new_n1509 $abc$10488$new_n1512 $abc$10488$new_n1567 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1525 $abc$10488$new_n1507 $abc$10488$new_n1568 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1570 $abc$10488$new_n1532 $abc$10488$new_n1536 $abc$10488$new_n1569 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1529 divider.y[7] $abc$10488$new_n1570 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1572 $abc$10488$new_n1574 $abc$10488$new_n1571 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1573 divider.y[7] $abc$10488$new_n1572 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[2] $abc$10488$new_n1551 $abc$10488$new_n1549 $abc$10488$new_n1573 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1575 $abc$10488$new_n1555 $abc$10488$new_n1556 $abc$10488$new_n1574 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1550 $abc$10488$new_n1554 $abc$10488$new_n1575 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1577 $abc$10488$new_n1488 $abc$10488$new_n1494 $abc$10488$new_n1576 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1484 divider.y[7] $abc$10488$new_n1577 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1579 $abc$10488$new_n1522 $abc$10488$new_n1506 $abc$10488$new_n1578 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1518 divider.y[7] $abc$10488$new_n1579 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1581 $abc$10488$new_n1543 $abc$10488$new_n1545 $abc$10488$new_n1580 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1530 $abc$10488$new_n1581 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1583 $abc$10488$new_n1548 $abc$10488$new_n1553 $abc$10488$new_n1582 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1551 $abc$10488$new_n1583 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1585 $abc$10488$new_n1562 $abc$10488$new_n1561 $abc$10488$new_n1584 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1563 divider.y[7] $abc$10488$new_n1585 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1587 $abc$10488$new_n1566 $abc$10488$new_n1568 $abc$10488$new_n1586 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1521 $abc$10488$new_n1587 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[4] $abc$10488$new_n1528 divider.y[7] $abc$10488$new_n1588 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1573 $abc$10488$new_n1575 $abc$10488$new_n1589 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[4] $abc$10488$new_n1483 divider.y[7] $abc$10488$new_n1590 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1518 $abc$10488$new_n1522 $abc$10488$new_n1591 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 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1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1581 divider.y[7] $abc$10488$new_n1600 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1583 divider.y[7] $abc$10488$new_n1601 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1585 divider.y[7] $abc$10488$new_n1603 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1587 divider.y[7] $abc$10488$new_n1605 +010 1 +011 1 +100 1 +110 1 +.names divider.x[3] $abc$10488$new_n1601 divider.x[4] $abc$10488$new_n1600 $abc$10488$new_n1608 $abc$10488$new_n1607 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.x[1] $abc$10488$new_n1599 divider.x[2] $abc$10488$new_n1598 $abc$10488$new_n1609 $abc$10488$new_n1608 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.x[-1] 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$abc$10488$new_n2202 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$10488$new_n1209 $abc$10488$new_n1212 $abc$10488$new_n2201 $abc$10488$new_n2202 $abc$10488$new_n736 $abc$10488$auto$rtlil.cc:2693:MuxGate$10034 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n815 divider.x[-22] divider.x[-23] $abc$10488$new_n2204 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n759 $abc$10488$new_n764 $abc$10488$new_n2204 $abc$10488$new_n776 $abc$10488$new_n2205 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$10488$new_n779 $abc$10488$new_n835 $abc$10488$new_n2205 $abc$10488$new_n840 $abc$10488$new_n2206 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names LOOKUP.index[0] LOOKUP.index[1] divider.x[-20] divider.x[-21] $abc$10488$new_n2207 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$10488$new_n2207 LOOKUP.index[1] divider.x[-23] divider.x[-22] $abc$10488$new_n2208 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1050 $abc$10488$new_n2208 $abc$10488$new_n1055 $abc$10488$new_n2209 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n2209 $abc$10488$new_n1058 $abc$10488$new_n1063 $abc$10488$new_n2210 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1082 divider.x[-23] divider.x[-24] $abc$10488$new_n2211 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[2] $abc$10488$new_n1089 $abc$10488$new_n2211 $abc$10488$new_n1078 $abc$10488$new_n2212 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n2212 $abc$10488$new_n1084 $abc$10488$new_n1072 $abc$10488$new_n2213 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] LOOKUP.index[1] divider.x[-18] divider.x[-19] $abc$10488$new_n2214 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$10488$new_n2214 LOOKUP.index[2] LOOKUP.index[1] divider.x[-20] divider.x[-21] $abc$10488$new_n2215 +00001 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n2215 LOOKUP.index[2] $abc$10488$new_n1054 $abc$10488$new_n1056 $abc$10488$new_n2216 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1095 $abc$10488$new_n2216 $abc$10488$new_n1101 $abc$10488$new_n2217 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$10488$new_n1603 $abc$10488$new_n1605 $abc$10488$new_n1607 divider.x[5] divider.x[6] $abc$10488$new_n2218 +00011 1 +01001 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n1209 $abc$10488$new_n1212 divider.x[7] $abc$10488$new_n2390 $abc$10488$new_n2222 $abc$10488$auto$rtlil.cc:2693:MuxGate$10038 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names divider.x[7] z_[7] $abc$10488$new_n1379 divider.y[6] divider.x[6] $abc$10488$new_n2221 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$10488$new_n2221 z_[7] $abc$10488$new_n1220 $abc$10488$new_n1031 $abc$10488$new_n1380 $abc$10488$new_n2222 +00010 1 +00011 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$10488$new_n759 $abc$10488$new_n758 $abc$10488$new_n1258 $abc$10488$new_n1255 $abc$10488$new_n2223 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$10488$new_n2223 $abc$10488$new_n764 $abc$10488$new_n758 $abc$10488$new_n1250 $abc$10488$new_n1259 $abc$10488$new_n2224 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n779 $abc$10488$new_n1301 $abc$10488$new_n2224 $abc$10488$new_n1308 $abc$10488$new_n2225 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$10488$new_n759 $abc$10488$new_n758 $abc$10488$new_n1250 $abc$10488$new_n1259 $abc$10488$new_n2226 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$10488$new_n2226 $abc$10488$new_n758 $abc$10488$new_n1249 $abc$10488$new_n1258 $abc$10488$new_n2227 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$10488$new_n779 $abc$10488$new_n764 $abc$10488$new_n1322 $abc$10488$new_n2227 $abc$10488$new_n1325 $abc$10488$new_n2228 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1516 divider.y[-22] divider.y[-23] $abc$10488$new_n2229 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[2] $abc$10488$new_n1522 $abc$10488$new_n1512 $abc$10488$new_n2229 $abc$10488$new_n2230 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n2230 $abc$10488$new_n1518 $abc$10488$new_n1506 $abc$10488$new_n2231 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[2] LOOKUP.index[1] $abc$10488$new_n1556 $abc$10488$new_n1514 $abc$10488$new_n1516 $abc$10488$new_n2232 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1547 $abc$10488$new_n1553 $abc$10488$new_n2232 $abc$10488$new_n2233 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[4] LOOKUP.index[2] $abc$10488$new_n1563 $abc$10488$new_n1497 $abc$10488$new_n1499 $abc$10488$new_n2234 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n2234 $abc$10488$new_n1562 $abc$10488$new_n1561 $abc$10488$new_n2235 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n683 divider.y_[7] $abc$10488$new_n697 $abc$10488$new_n536 divider.i[2] $abc$10488$new_n2236 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10111 1 +11111 1 +.names divider.z_[-13] $abc$10488$new_n2236 $abc$10488$new_n659 $abc$10488$new_n724 divider.y_[7] $abc$10488$auto$rtlil.cc:2693:MuxGate$9738 +00100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$10488$new_n687 divider.y_[7] $abc$10488$new_n697 $abc$10488$new_n693 divider.i[2] $abc$10488$new_n2238 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10110 1 +11110 1 +.names divider.z_[-17] $abc$10488$new_n2238 $abc$10488$new_n659 $abc$10488$new_n728 divider.y_[7] $abc$10488$auto$rtlil.cc:2693:MuxGate$9746 +00100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$10488$new_n691 divider.y_[7] $abc$10488$new_n697 $abc$10488$new_n693 divider.i[2] $abc$10488$new_n2240 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10111 1 +11111 1 +.names divider.z_[-21] $abc$10488$new_n2240 $abc$10488$new_n659 $abc$10488$new_n732 divider.y_[7] $abc$10488$auto$rtlil.cc:2693:MuxGate$9754 +00100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names z_[7] $abc$10488$new_n1605 $abc$10488$new_n1212 $abc$10488$new_n1468 $abc$10488$new_n1607 $abc$10488$new_n2244 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names z_[7] $abc$10488$new_n1378 $abc$10488$new_n1030 $abc$10488$new_n1462 $abc$10488$new_n1461 $abc$10488$new_n2245 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names $abc$10488$new_n2245 $abc$10488$new_n2244 $abc$10488$new_n1221 $abc$10488$new_n1381 $abc$10488$new_n2246 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$10488$new_n1209 $abc$10488$new_n1212 divider.x[5] $abc$10488$new_n2244 $abc$10488$new_n2246 $abc$10488$auto$rtlil.cc:2693:MuxGate$9772 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$10488$new_n1457 $abc$10488$new_n1382 $abc$10488$new_n1377 divider.y[3] divider.x[3] $abc$10488$new_n2248 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$10488$new_n1209 z_[7] $abc$10488$new_n1456 $abc$10488$new_n2248 $abc$10488$new_n1706 $abc$10488$new_n2249 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11011 1 +11101 1 +.names divider.x[4] $abc$10488$new_n1212 $abc$10488$new_n1709 $abc$10488$new_n1600 $abc$10488$new_n1209 $abc$10488$new_n2250 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$10488$new_n2250 $abc$10488$new_n2249 $abc$10488$new_n1209 $abc$10488$auto$rtlil.cc:2693:MuxGate$9774 +001 1 +011 1 +110 1 +111 1 +.names z_[7] $abc$10488$new_n1601 $abc$10488$new_n1212 $abc$10488$new_n1469 $abc$10488$new_n1608 $abc$10488$new_n2252 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$10488$new_n2252 $abc$10488$new_n1377 $abc$10488$new_n1457 divider.y[3] $abc$10488$new_n1027 $abc$10488$new_n2253 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$10488$new_n2253 $abc$10488$new_n2252 $abc$10488$new_n1222 $abc$10488$new_n1382 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+01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$10488$new_n419 $abc$10488$new_n477 z_[-5] $abc$10488$new_n2386 $abc$10488$new_n2387 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names $abc$10488$new_n2387 z[-5] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9986 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$10488$new_n1603 $abc$10488$new_n1605 $abc$10488$new_n1468 divider.x[5] divider.x[6] $abc$10488$new_n2389 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +.names $abc$10488$new_n1213 z_[7] $abc$10488$new_n2389 $abc$10488$new_n2218 $abc$10488$new_n2390 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$10488$new_n1212 $abc$10488$new_n1698 $abc$10488$new_n1603 $abc$10488$new_n1695 $abc$10488$new_n1694 $abc$10488$new_n2391 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n2391 $abc$10488$new_n1209 divider.x[6] $abc$10488$new_n1212 $abc$10488$auto$rtlil.cc:2693:MuxGate$9770 +0010 1 +0011 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names z_[7] $abc$10488$new_n1597 $abc$10488$new_n1212 $abc$10488$new_n1471 $abc$10488$new_n1610 $abc$10488$new_n2393 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$10488$new_n2393 $abc$10488$new_n1372 $abc$10488$new_n1449 divider.y[-1] $abc$10488$new_n1021 $abc$10488$new_n2394 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$10488$new_n2394 $abc$10488$new_n2393 $abc$10488$new_n1224 $abc$10488$new_n1384 $abc$10488$new_n2395 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$10488$new_n1212 divider.x[-1] $abc$10488$new_n1209 $abc$10488$new_n2393 $abc$10488$new_n2395 $abc$10488$auto$rtlil.cc:2693:MuxGate$9784 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names z_[7] $abc$10488$new_n1023 $abc$10488$new_n973 $abc$10488$new_n1997 $abc$10488$new_n947 $abc$10488$new_n2397 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names $abc$10488$new_n1212 $abc$10488$new_n1999 $abc$10488$new_n1172 $abc$10488$new_n950 divider.x[1] $abc$10488$new_n2398 +00001 1 +00010 1 +00101 1 +00110 1 +01001 1 +01010 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names divider.y[1] $abc$10488$new_n2398 $abc$10488$new_n1209 $abc$10488$new_n2397 $abc$10488$new_n1212 $abc$10488$auto$rtlil.cc:2693:MuxGate$9912 +00110 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names z_[7] $abc$10488$new_n1146 $abc$10488$new_n1212 $abc$10488$new_n1193 $abc$10488$new_n1043 $abc$10488$new_n2400 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$10488$new_n2400 $abc$10488$new_n900 $abc$10488$new_n747 $abc$10488$new_n2085 $abc$10488$new_n2401 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$10488$new_n1209 $abc$10488$new_n2400 $abc$10488$new_n1212 divider.y[-14] $abc$10488$new_n2401 $abc$10488$auto$rtlil.cc:2693:MuxGate$9942 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10024 Q=z_[-24] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10022 Q=z_[-23] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10020 Q=z_[-22] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10018 Q=z_[-21] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10016 Q=z_[-20] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10014 Q=z_[-19] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10012 Q=z_[-18] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10010 Q=z_[-17] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10008 Q=z_[-16] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10006 Q=z_[-15] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10004 Q=z_[-14] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10002 Q=z_[-13] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10000 Q=z_[-12] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9998 Q=z_[-11] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9996 Q=z_[-10] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9994 Q=z_[-9] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9992 Q=z_[-8] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9990 Q=z_[-7] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9988 Q=z_[-6] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9986 Q=z_[-5] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9984 Q=z_[-4] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9982 Q=z_[-3] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9980 Q=z_[-2] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9978 Q=z_[-1] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9976 Q=z_[0] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9974 Q=z_[1] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9972 Q=z_[2] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9970 Q=z_[3] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9968 Q=z_[4] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9966 Q=z_[5] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9964 Q=z_[6] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10026 Q=z_[7] +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9962 Q=divider.y[-24] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9960 Q=divider.y[-23] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9958 Q=divider.y[-22] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9956 Q=divider.y[-21] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9954 Q=divider.y[-20] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9952 Q=divider.y[-19] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9950 Q=divider.y[-18] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9948 Q=divider.y[-17] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9946 Q=divider.y[-16] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9944 Q=divider.y[-15] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9942 Q=divider.y[-14] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9940 Q=divider.y[-13] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9938 Q=divider.y[-12] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9936 Q=divider.y[-11] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9934 Q=divider.y[-10] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9932 Q=divider.y[-9] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9930 Q=divider.y[-8] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9928 Q=divider.y[-7] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9926 Q=divider.y[-6] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9924 Q=divider.y[-5] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9922 Q=divider.y[-4] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9920 Q=divider.y[-3] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9918 Q=divider.y[-2] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9916 Q=divider.y[-1] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9914 Q=divider.y[0] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9912 Q=divider.y[1] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9910 Q=divider.y[2] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9908 Q=divider.y[3] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9906 Q=divider.y[4] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9904 Q=divider.y[5] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9902 Q=divider.y[6] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10034 Q=divider.y[7] R=EN +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9900 Q=divider.y_[-24] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9898 Q=divider.y_[-23] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9896 Q=divider.y_[-22] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9894 Q=divider.y_[-21] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9892 Q=divider.y_[-20] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9890 Q=divider.y_[-19] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9888 Q=divider.y_[-18] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9886 Q=divider.y_[-17] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9884 Q=divider.y_[-16] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9882 Q=divider.y_[-15] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9880 Q=divider.y_[-14] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9878 Q=divider.y_[-13] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9876 Q=divider.y_[-12] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9874 Q=divider.y_[-11] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9872 Q=divider.y_[-10] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9870 Q=divider.y_[-9] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9868 Q=divider.y_[-8] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9866 Q=divider.y_[-7] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9864 Q=divider.y_[-6] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9862 Q=divider.y_[-5] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9860 Q=divider.y_[-4] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9858 Q=divider.y_[-3] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9856 Q=divider.y_[-2] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9854 Q=divider.y_[-1] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9852 Q=divider.y_[0] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9850 Q=divider.y_[1] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9848 Q=divider.y_[2] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9846 Q=divider.y_[3] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9844 Q=divider.y_[4] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9842 Q=divider.y_[5] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9840 Q=divider.y_[6] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10028 Q=divider.y_[7] +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9838 Q=LOOKUP.index[0] S=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9836 Q=LOOKUP.index[1] R=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9834 Q=LOOKUP.index[2] S=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9832 Q=LOOKUP.index[3] S=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10036 Q=LOOKUP.index[4] S=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9830 Q=divider.x[-24] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9828 Q=divider.x[-23] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9826 Q=divider.x[-22] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9824 Q=divider.x[-21] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9822 Q=divider.x[-20] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9820 Q=divider.x[-19] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9818 Q=divider.x[-18] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9816 Q=divider.x[-17] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9814 Q=divider.x[-16] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9812 Q=divider.x[-15] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9810 Q=divider.x[-14] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9808 Q=divider.x[-13] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9806 Q=divider.x[-12] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9804 Q=divider.x[-11] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9802 Q=divider.x[-10] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9800 Q=divider.x[-9] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9798 Q=divider.x[-8] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9796 Q=divider.x[-7] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9794 Q=divider.x[-6] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9792 Q=divider.x[-5] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9790 Q=divider.x[-4] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9788 Q=divider.x[-3] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9786 Q=divider.x[-2] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9784 Q=divider.x[-1] R=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9782 Q=divider.x[0] S=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9780 Q=divider.x[1] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9778 Q=divider.x[2] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9776 Q=divider.x[3] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9774 Q=divider.x[4] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9772 Q=divider.x[5] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9770 Q=divider.x[6] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10038 Q=divider.x[7] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10040 Q=div_en R=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10042 Q=IS_FIRST4 S=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10044 Q=IS_FIRST13 S=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10046 Q=IS_Z_ZERO R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9768 Q=divider.i[0] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9766 Q=divider.i[1] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9764 Q=divider.i[2] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9762 Q=divider.i[3] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10032 Q=divider.i[4] R=div_en +.subckt sdffr C=CLK D=divider.z_[-24] Q=out[-24] R=div_en +.subckt sdffr C=CLK D=divider.z_[-23] Q=out[-23] R=div_en +.subckt sdffr C=CLK D=divider.z_[-22] Q=out[-22] R=div_en +.subckt sdffr C=CLK D=divider.z_[-21] Q=out[-21] R=div_en +.subckt sdffr C=CLK D=divider.z_[-20] Q=out[-20] R=div_en +.subckt sdffr C=CLK D=divider.z_[-19] Q=out[-19] R=div_en +.subckt sdffr C=CLK D=divider.z_[-18] Q=out[-18] R=div_en +.subckt sdffr C=CLK D=divider.z_[-17] Q=out[-17] R=div_en +.subckt sdffr C=CLK D=divider.z_[-16] Q=out[-16] R=div_en +.subckt sdffr C=CLK D=divider.z_[-15] Q=out[-15] R=div_en +.subckt sdffr C=CLK D=divider.z_[-14] Q=out[-14] R=div_en +.subckt sdffr C=CLK D=divider.z_[-13] Q=out[-13] R=div_en +.subckt sdffr C=CLK D=divider.z_[-12] Q=out[-12] R=div_en +.subckt sdffr C=CLK D=divider.z_[-11] Q=out[-11] R=div_en +.subckt sdffr C=CLK D=divider.z_[-10] Q=out[-10] R=div_en +.subckt sdffr C=CLK D=divider.z_[-9] Q=out[-9] R=div_en +.subckt sdffr C=CLK D=divider.z_[-8] Q=out[-8] R=div_en +.subckt sdffr C=CLK D=divider.z_[-7] Q=out[-7] R=div_en +.subckt sdffr C=CLK D=divider.z_[-6] Q=out[-6] R=div_en +.subckt sdffr C=CLK D=divider.z_[-5] Q=out[-5] R=div_en +.subckt sdffr C=CLK D=divider.z_[-4] Q=out[-4] R=div_en +.subckt sdffr C=CLK D=divider.z_[-3] Q=out[-3] R=div_en +.subckt sdffr C=CLK D=divider.z_[-2] Q=out[-2] R=div_en +.subckt sdffr C=CLK D=divider.z_[-1] Q=out[-1] R=div_en +.subckt sdffr C=CLK D=divider.z_[0] Q=out[0] R=div_en +.subckt sdffr C=CLK D=divider.z_[1] Q=out[1] R=div_en +.subckt sdffr C=CLK D=divider.z_[2] Q=out[2] R=div_en +.subckt sdffr C=CLK D=divider.z_[3] Q=out[3] R=div_en +.subckt sdffr C=CLK D=divider.z_[4] Q=out[4] R=div_en +.subckt sdffr C=CLK D=divider.z_[5] Q=out[5] R=div_en +.subckt sdffr C=CLK D=divider.z_[6] Q=out[6] R=div_en +.subckt sdffr C=CLK D=divider.z_[7] Q=out[7] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9760 Q=divider.z_[-24] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9758 Q=divider.z_[-23] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9756 Q=divider.z_[-22] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9754 Q=divider.z_[-21] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9752 Q=divider.z_[-20] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9750 Q=divider.z_[-19] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9748 Q=divider.z_[-18] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9746 Q=divider.z_[-17] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9744 Q=divider.z_[-16] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9742 Q=divider.z_[-15] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9740 Q=divider.z_[-14] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9738 Q=divider.z_[-13] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9736 Q=divider.z_[-12] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9734 Q=divider.z_[-11] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9732 Q=divider.z_[-10] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9730 Q=divider.z_[-9] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9728 Q=divider.z_[-8] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9726 Q=divider.z_[-7] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9724 Q=divider.z_[-6] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9722 Q=divider.z_[-5] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9720 Q=divider.z_[-4] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9718 Q=divider.z_[-3] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9716 Q=divider.z_[-2] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9714 Q=divider.z_[-1] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9712 Q=divider.z_[0] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9710 Q=divider.z_[1] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9708 Q=divider.z_[2] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9706 Q=divider.z_[3] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9704 Q=divider.z_[4] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9702 Q=divider.z_[5] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9700 Q=divider.z_[6] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10030 Q=divider.z_[7] R=div_en +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif new file mode 100644 index 00000000000..56a80c9fc49 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif @@ -0,0 +1,15942 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model picorv32 +.inputs clk resetn mem_ready mem_rdata[0] mem_rdata[1] mem_rdata[2] mem_rdata[3] mem_rdata[4] mem_rdata[5] mem_rdata[6] mem_rdata[7] mem_rdata[8] mem_rdata[9] mem_rdata[10] mem_rdata[11] mem_rdata[12] mem_rdata[13] mem_rdata[14] mem_rdata[15] mem_rdata[16] mem_rdata[17] mem_rdata[18] mem_rdata[19] mem_rdata[20] mem_rdata[21] mem_rdata[22] mem_rdata[23] mem_rdata[24] mem_rdata[25] mem_rdata[26] mem_rdata[27] mem_rdata[28] mem_rdata[29] mem_rdata[30] mem_rdata[31] pcpi_wr pcpi_rd[0] pcpi_rd[1] pcpi_rd[2] pcpi_rd[3] pcpi_rd[4] pcpi_rd[5] pcpi_rd[6] pcpi_rd[7] pcpi_rd[8] pcpi_rd[9] pcpi_rd[10] pcpi_rd[11] pcpi_rd[12] pcpi_rd[13] pcpi_rd[14] pcpi_rd[15] pcpi_rd[16] pcpi_rd[17] pcpi_rd[18] pcpi_rd[19] pcpi_rd[20] pcpi_rd[21] pcpi_rd[22] pcpi_rd[23] pcpi_rd[24] pcpi_rd[25] pcpi_rd[26] pcpi_rd[27] pcpi_rd[28] pcpi_rd[29] pcpi_rd[30] pcpi_rd[31] pcpi_wait pcpi_ready irq[0] irq[1] irq[2] irq[3] irq[4] irq[5] irq[6] irq[7] irq[8] irq[9] irq[10] irq[11] irq[12] irq[13] irq[14] irq[15] irq[16] irq[17] irq[18] irq[19] irq[20] irq[21] irq[22] irq[23] irq[24] irq[25] irq[26] irq[27] irq[28] irq[29] irq[30] irq[31] +.outputs trap mem_valid mem_instr mem_addr[0] mem_addr[1] mem_addr[2] mem_addr[3] mem_addr[4] mem_addr[5] mem_addr[6] mem_addr[7] mem_addr[8] mem_addr[9] mem_addr[10] mem_addr[11] mem_addr[12] mem_addr[13] mem_addr[14] mem_addr[15] mem_addr[16] mem_addr[17] mem_addr[18] mem_addr[19] mem_addr[20] mem_addr[21] mem_addr[22] mem_addr[23] mem_addr[24] mem_addr[25] mem_addr[26] mem_addr[27] mem_addr[28] mem_addr[29] mem_addr[30] mem_addr[31] mem_wdata[0] mem_wdata[1] mem_wdata[2] mem_wdata[3] mem_wdata[4] mem_wdata[5] mem_wdata[6] mem_wdata[7] mem_wdata[8] mem_wdata[9] mem_wdata[10] mem_wdata[11] mem_wdata[12] mem_wdata[13] mem_wdata[14] mem_wdata[15] mem_wdata[16] mem_wdata[17] mem_wdata[18] mem_wdata[19] mem_wdata[20] mem_wdata[21] mem_wdata[22] mem_wdata[23] mem_wdata[24] mem_wdata[25] mem_wdata[26] mem_wdata[27] mem_wdata[28] mem_wdata[29] mem_wdata[30] mem_wdata[31] mem_wstrb[0] mem_wstrb[1] mem_wstrb[2] mem_wstrb[3] mem_la_read mem_la_write mem_la_addr[0] mem_la_addr[1] mem_la_addr[2] mem_la_addr[3] mem_la_addr[4] mem_la_addr[5] mem_la_addr[6] mem_la_addr[7] mem_la_addr[8] mem_la_addr[9] mem_la_addr[10] mem_la_addr[11] mem_la_addr[12] mem_la_addr[13] mem_la_addr[14] mem_la_addr[15] mem_la_addr[16] mem_la_addr[17] mem_la_addr[18] mem_la_addr[19] mem_la_addr[20] mem_la_addr[21] mem_la_addr[22] mem_la_addr[23] mem_la_addr[24] mem_la_addr[25] mem_la_addr[26] mem_la_addr[27] mem_la_addr[28] mem_la_addr[29] mem_la_addr[30] mem_la_addr[31] mem_la_wdata[0] mem_la_wdata[1] mem_la_wdata[2] mem_la_wdata[3] mem_la_wdata[4] mem_la_wdata[5] mem_la_wdata[6] mem_la_wdata[7] mem_la_wdata[8] mem_la_wdata[9] mem_la_wdata[10] mem_la_wdata[11] mem_la_wdata[12] mem_la_wdata[13] mem_la_wdata[14] mem_la_wdata[15] mem_la_wdata[16] mem_la_wdata[17] mem_la_wdata[18] mem_la_wdata[19] mem_la_wdata[20] mem_la_wdata[21] mem_la_wdata[22] mem_la_wdata[23] mem_la_wdata[24] mem_la_wdata[25] mem_la_wdata[26] mem_la_wdata[27] mem_la_wdata[28] mem_la_wdata[29] mem_la_wdata[30] mem_la_wdata[31] mem_la_wstrb[0] mem_la_wstrb[1] mem_la_wstrb[2] mem_la_wstrb[3] pcpi_valid pcpi_insn[0] pcpi_insn[1] pcpi_insn[2] pcpi_insn[3] pcpi_insn[4] pcpi_insn[5] pcpi_insn[6] pcpi_insn[7] pcpi_insn[8] pcpi_insn[9] pcpi_insn[10] pcpi_insn[11] pcpi_insn[12] pcpi_insn[13] pcpi_insn[14] pcpi_insn[15] pcpi_insn[16] pcpi_insn[17] pcpi_insn[18] pcpi_insn[19] pcpi_insn[20] pcpi_insn[21] pcpi_insn[22] pcpi_insn[23] pcpi_insn[24] pcpi_insn[25] pcpi_insn[26] pcpi_insn[27] pcpi_insn[28] pcpi_insn[29] pcpi_insn[30] pcpi_insn[31] pcpi_rs1[0] pcpi_rs1[1] pcpi_rs1[2] pcpi_rs1[3] pcpi_rs1[4] pcpi_rs1[5] pcpi_rs1[6] pcpi_rs1[7] pcpi_rs1[8] pcpi_rs1[9] pcpi_rs1[10] pcpi_rs1[11] pcpi_rs1[12] pcpi_rs1[13] pcpi_rs1[14] pcpi_rs1[15] pcpi_rs1[16] pcpi_rs1[17] pcpi_rs1[18] pcpi_rs1[19] pcpi_rs1[20] pcpi_rs1[21] pcpi_rs1[22] pcpi_rs1[23] pcpi_rs1[24] pcpi_rs1[25] pcpi_rs1[26] pcpi_rs1[27] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs1[30] pcpi_rs1[31] pcpi_rs2[0] pcpi_rs2[1] pcpi_rs2[2] pcpi_rs2[3] pcpi_rs2[4] pcpi_rs2[5] pcpi_rs2[6] pcpi_rs2[7] pcpi_rs2[8] pcpi_rs2[9] pcpi_rs2[10] pcpi_rs2[11] pcpi_rs2[12] pcpi_rs2[13] pcpi_rs2[14] pcpi_rs2[15] pcpi_rs2[16] pcpi_rs2[17] pcpi_rs2[18] pcpi_rs2[19] pcpi_rs2[20] pcpi_rs2[21] pcpi_rs2[22] pcpi_rs2[23] pcpi_rs2[24] pcpi_rs2[25] pcpi_rs2[26] pcpi_rs2[27] pcpi_rs2[28] pcpi_rs2[29] pcpi_rs2[30] pcpi_rs2[31] eoi[0] eoi[1] eoi[2] eoi[3] eoi[4] eoi[5] eoi[6] eoi[7] eoi[8] eoi[9] eoi[10] eoi[11] eoi[12] eoi[13] eoi[14] eoi[15] eoi[16] eoi[17] eoi[18] eoi[19] eoi[20] eoi[21] eoi[22] eoi[23] eoi[24] eoi[25] eoi[26] eoi[27] eoi[28] eoi[29] eoi[30] eoi[31] trace_valid trace_data[0] trace_data[1] trace_data[2] trace_data[3] trace_data[4] trace_data[5] trace_data[6] trace_data[7] trace_data[8] trace_data[9] trace_data[10] trace_data[11] trace_data[12] trace_data[13] trace_data[14] trace_data[15] trace_data[16] trace_data[17] trace_data[18] trace_data[19] trace_data[20] trace_data[21] trace_data[22] trace_data[23] trace_data[24] trace_data[25] trace_data[26] trace_data[27] trace_data[28] trace_data[29] trace_data[30] trace_data[31] trace_data[32] trace_data[33] trace_data[34] trace_data[35] +.names $false +.names $true +1 +.names $undef +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[30] mem_la_wdata[6] pcpi_rs2[14] mem_la_wdata[30] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[30] mem_wdata[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14337 +001 1 +011 1 +110 1 +111 1 +.names mem_la_write trap $abc$16053$new_n1410 +10 1 +.names resetn mem_do_wdata mem_state[1] mem_state[0] mem_la_write +1100 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[29] mem_la_wdata[5] pcpi_rs2[13] mem_la_wdata[29] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[29] mem_wdata[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14339 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[28] mem_la_wdata[4] pcpi_rs2[12] mem_la_wdata[28] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[28] mem_wdata[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14341 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[27] mem_la_wdata[3] pcpi_rs2[11] mem_la_wdata[27] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[27] mem_wdata[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14343 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[26] mem_la_wdata[2] pcpi_rs2[10] mem_la_wdata[26] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[26] mem_wdata[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14345 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[25] mem_la_wdata[1] pcpi_rs2[9] mem_la_wdata[25] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[25] mem_wdata[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14347 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[24] mem_la_wdata[0] pcpi_rs2[8] mem_la_wdata[24] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[24] mem_wdata[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14349 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[23] mem_la_wdata[7] mem_la_wdata[23] +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] $abc$16053$new_n1425 +00 1 +11 1 +.names $abc$16053$new_n1410 mem_la_wdata[23] mem_wdata[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14351 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[22] mem_la_wdata[6] mem_la_wdata[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[22] mem_wdata[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14353 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[21] mem_la_wdata[5] mem_la_wdata[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[21] mem_wdata[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14355 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[20] mem_la_wdata[4] mem_la_wdata[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[20] mem_wdata[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14357 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[19] mem_la_wdata[3] mem_la_wdata[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[19] mem_wdata[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14359 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[18] mem_la_wdata[2] mem_la_wdata[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[18] mem_wdata[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14361 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[17] mem_la_wdata[1] mem_la_wdata[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[17] mem_wdata[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14363 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[16] mem_la_wdata[0] mem_la_wdata[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[16] mem_wdata[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14365 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[7] pcpi_rs2[15] mem_la_wdata[15] +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[1] mem_wordsize[0] $abc$16053$new_n1442 +10 1 +.names $abc$16053$new_n1410 mem_la_wdata[15] mem_wdata[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14367 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[6] pcpi_rs2[14] mem_la_wdata[14] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[14] mem_wdata[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14369 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[5] pcpi_rs2[13] mem_la_wdata[13] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[13] mem_wdata[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14371 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[4] pcpi_rs2[12] mem_la_wdata[12] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[12] mem_wdata[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14373 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[3] pcpi_rs2[11] mem_la_wdata[11] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[11] mem_wdata[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14375 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[2] pcpi_rs2[10] mem_la_wdata[10] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[10] mem_wdata[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14377 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[1] pcpi_rs2[9] mem_la_wdata[9] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[9] mem_wdata[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14379 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[0] pcpi_rs2[8] mem_la_wdata[8] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[8] mem_wdata[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14381 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[7] mem_wdata[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14383 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[6] mem_wdata[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14385 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[5] mem_wdata[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14387 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[4] mem_wdata[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14389 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[3] mem_wdata[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14391 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[2] mem_wdata[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14393 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[1] mem_wdata[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14395 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[0] mem_wdata[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14397 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1475 $abc$16053$new_n1467 mem_state[0] mem_do_wdata $abc$16053$auto$rtlil.cc:2693:MuxGate$14401 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$16053$new_n1468 trap resetn $abc$16053$new_n1474 mem_do_rinst $abc$16053$new_n1467 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n1473 $abc$16053$new_n1471 $abc$16053$new_n1469 $abc$16053$new_n1468 +110 1 +.names mem_state[1] mem_state[0] $abc$16053$new_n1470 mem_do_rdata $abc$16053$new_n1469 +0000 1 +0001 1 +0011 1 +.names mem_do_rinst mem_do_prefetch $abc$16053$new_n1470 +00 1 +.names mem_state[1] mem_state[0] $abc$16053$new_n1472 mem_do_wdata $abc$16053$new_n1471 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names mem_ready mem_valid $abc$16053$new_n1472 +11 1 +.names resetn trap $abc$16053$new_n1473 +10 1 +.names mem_state[1] mem_state[0] $abc$16053$new_n1474 +11 1 +.names $abc$16053$new_n1473 mem_state[1] mem_state[0] mem_do_rdata mem_do_rinst $abc$16053$new_n1475 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[30] $abc$16053$new_n1477 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14403 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[30] instr_jal decoded_imm_j[30] $abc$16053$new_n1477 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names instr_lui instr_auipc $abc$16053$new_n1478 +00 1 +.names decoder_trigger decoder_pseudo_trigger $abc$16053$new_n1479 +10 1 +.names is_beq_bne_blt_bge_bltu_bgeu instr_jalr is_lb_lh_lw_lbu_lhu is_sb_sh_sw is_alu_reg_imm $abc$16053$new_n1480 +00000 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[29] $abc$16053$new_n1482 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14405 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[29] instr_jal decoded_imm_j[29] $abc$16053$new_n1482 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[28] $abc$16053$new_n1484 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14407 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[28] instr_jal decoded_imm_j[28] $abc$16053$new_n1484 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[27] $abc$16053$new_n1486 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14409 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[27] instr_jal decoded_imm_j[27] $abc$16053$new_n1486 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[26] $abc$16053$new_n1488 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14411 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[26] instr_jal decoded_imm_j[26] $abc$16053$new_n1488 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[25] $abc$16053$new_n1490 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14413 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[25] instr_jal decoded_imm_j[25] $abc$16053$new_n1490 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[24] $abc$16053$new_n1492 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14415 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[24] instr_jal decoded_imm_j[24] $abc$16053$new_n1492 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[23] $abc$16053$new_n1494 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14417 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[23] instr_jal decoded_imm_j[23] $abc$16053$new_n1494 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[22] $abc$16053$new_n1496 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14419 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[22] instr_jal decoded_imm_j[22] $abc$16053$new_n1496 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[21] $abc$16053$new_n1498 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14421 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[21] instr_jal decoded_imm_j[21] $abc$16053$new_n1498 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[20] $abc$16053$new_n1500 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14423 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[20] instr_jal decoded_imm_j[20] $abc$16053$new_n1500 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[19] $abc$16053$new_n1502 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14425 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[19] instr_jal decoded_imm_j[19] $abc$16053$new_n1502 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[18] $abc$16053$new_n1504 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14427 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[18] instr_jal decoded_imm_j[18] $abc$16053$new_n1504 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[17] $abc$16053$new_n1506 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14429 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[17] instr_jal decoded_imm_j[17] $abc$16053$new_n1506 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[16] $abc$16053$new_n1508 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14431 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[16] instr_jal decoded_imm_j[16] $abc$16053$new_n1508 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[15] $abc$16053$new_n1510 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14433 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[15] instr_jal decoded_imm_j[15] $abc$16053$new_n1510 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[14] $abc$16053$new_n1512 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14435 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[14] instr_jal decoded_imm_j[14] $abc$16053$new_n1512 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[13] $abc$16053$new_n1514 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14437 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[13] instr_jal decoded_imm_j[13] $abc$16053$new_n1514 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[12] $abc$16053$new_n1516 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14439 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[12] instr_jal decoded_imm_j[12] $abc$16053$new_n1516 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1518 decoded_imm[11] $abc$16053$new_n1519 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14441 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[11] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1518 +11111 1 +.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[31] mem_rdata_q[7] $abc$16053$new_n1519 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1521 decoded_imm[10] mem_rdata_q[30] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14443 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[10] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1521 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1523 decoded_imm[9] mem_rdata_q[29] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14445 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[9] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1523 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1525 decoded_imm[8] mem_rdata_q[28] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14447 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[8] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1525 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1527 decoded_imm[7] mem_rdata_q[27] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14449 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[7] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1527 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1529 decoded_imm[6] mem_rdata_q[26] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14451 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[6] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1529 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1531 decoded_imm[5] mem_rdata_q[25] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14453 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[5] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1531 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1533 decoded_imm[4] $abc$16053$new_n1534 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14455 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[4] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1533 +11111 1 +.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[11] mem_rdata_q[24] $abc$16053$new_n1534 +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1536 decoded_imm[3] $abc$16053$new_n1537 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14457 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[3] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1536 +11111 1 +.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[10] mem_rdata_q[23] $abc$16053$new_n1537 +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n1479 decoded_imm[2] $abc$16053$new_n1539 $abc$16053$new_n1540 $abc$16053$auto$rtlil.cc:2693:MuxGate$14459 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instr_jal decoded_imm_j[2] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1539 +1111 1 +.names $abc$16053$new_n1480 is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[9] mem_rdata_q[22] $abc$16053$new_n1540 +00001 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1542 decoded_imm[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14461 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1480 $abc$16053$new_n1543 decoded_imm_j[1] $abc$16053$new_n1478 instr_jal $abc$16053$new_n1542 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[8] mem_rdata_q[21] $abc$16053$new_n1543 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names $abc$16053$new_n1479 decoded_imm[0] $abc$16053$new_n1545 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14463 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names is_sb_sh_sw mem_rdata_q[7] mem_rdata_q[20] is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1545 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$16053$new_n1472 mem_rdata[10] mem_rdata_q[10] mem_rdata_latched[10] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[10] decoded_rd[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14465 +001 1 +011 1 +110 1 +111 1 +.names mem_do_rinst $abc$16053$new_n1549 $abc$16053$new_n1548 +10 1 +.names resetn mem_do_rinst $abc$16053$new_n1550 $abc$16053$new_n1551 $abc$16053$new_n1474 $abc$16053$new_n1549 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$16053$new_n1472 mem_state[0] mem_state[1] $abc$16053$new_n1550 +101 1 +110 1 +111 1 +.names mem_do_wdata mem_do_rdata $abc$16053$new_n1551 +00 1 +.names $abc$16053$new_n1472 mem_rdata[9] mem_rdata_q[9] mem_rdata_latched[9] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[9] decoded_rd[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14467 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[8] mem_rdata_q[8] mem_rdata_latched[8] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[8] decoded_rd[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14469 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[7] mem_rdata_q[7] mem_rdata_latched[7] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[7] decoded_rd[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14471 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[31] mem_rdata_q[31] mem_rdata_latched[31] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14473 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14475 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14477 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14479 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14481 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14483 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14485 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14487 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14489 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14491 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14493 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[19] mem_rdata_q[19] mem_rdata_latched[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[19] decoded_imm_j[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14495 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[18] mem_rdata_q[18] mem_rdata_latched[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[18] decoded_imm_j[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14497 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[17] mem_rdata_q[17] mem_rdata_latched[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[17] decoded_imm_j[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14499 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[16] mem_rdata_q[16] mem_rdata_latched[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[16] decoded_imm_j[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14501 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[15] mem_rdata_q[15] mem_rdata_latched[15] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[15] decoded_imm_j[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14503 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[14] mem_rdata_q[14] mem_rdata_latched[14] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[14] decoded_imm_j[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14505 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[13] mem_rdata_q[13] mem_rdata_latched[13] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[13] decoded_imm_j[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14507 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[12] mem_rdata_q[12] mem_rdata_latched[12] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[12] decoded_imm_j[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14509 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[20] mem_rdata_q[20] mem_rdata_latched[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[20] decoded_imm_j[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14511 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[30] mem_rdata_q[30] mem_rdata_latched[30] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[30] decoded_imm_j[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14513 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[29] mem_rdata_q[29] mem_rdata_latched[29] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[29] decoded_imm_j[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14515 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[28] mem_rdata_q[28] mem_rdata_latched[28] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[28] decoded_imm_j[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14517 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[27] mem_rdata_q[27] mem_rdata_latched[27] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[27] decoded_imm_j[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14519 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[26] mem_rdata_q[26] mem_rdata_latched[26] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[26] decoded_imm_j[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14521 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[25] mem_rdata_q[25] mem_rdata_latched[25] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[25] decoded_imm_j[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14523 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[24] mem_rdata_q[24] mem_rdata_latched[24] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[24] decoded_imm_j[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14525 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[23] mem_rdata_q[23] mem_rdata_latched[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[23] decoded_imm_j[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14527 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[22] mem_rdata_q[22] mem_rdata_latched[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[22] decoded_imm_j[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14529 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[21] mem_rdata_q[21] mem_rdata_latched[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[21] decoded_imm_j[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14531 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1609 latched_rd[3] $abc$16053$new_n1612 decoded_rd[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14535 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names resetn $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1612 $abc$16053$new_n1609 +1001 1 +1011 1 +1110 1 +1111 1 +.names cpu_state[3] $abc$16053$new_n1611 cpu_state[1] cpu_state[0] cpu_state[2] $abc$16053$new_n1610 +11000 1 +.names cpu_state[7] cpu_state[6] cpu_state[4] cpu_state[5] $abc$16053$new_n1611 +0000 1 +.names $abc$16053$new_n1614 $abc$16053$new_n1613 $abc$16053$new_n1612 +11 1 +.names cpu_state[3] cpu_state[1] cpu_state[0] cpu_state[2] $abc$16053$new_n1613 +0000 1 +.names cpu_state[6] cpu_state[7] cpu_state[4] cpu_state[5] $abc$16053$new_n1614 +1000 1 +.names $abc$16053$new_n1609 latched_rd[2] $abc$16053$new_n1612 decoded_rd[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14539 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1609 latched_rd[1] $abc$16053$new_n1612 decoded_rd[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14543 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1609 latched_rd[0] $abc$16053$new_n1612 decoded_rd[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14547 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[30] decoded_imm[30] $abc$16053$new_n1625 $abc$16053$auto$rtlil.cc:2693:MuxGate$14549 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names resetn $abc$16053$new_n1620 $abc$16053$new_n1619 +10 1 +.names $abc$16053$new_n1622 $abc$16053$new_n1621 $abc$16053$new_n1620 +00 1 +.names cpu_state[4] $abc$16053$new_n1613 cpu_state[7] cpu_state[6] cpu_state[5] $abc$16053$new_n1621 +11000 1 +.names $abc$16053$new_n1613 cpu_state[5] cpu_state[7] cpu_state[6] cpu_state[4] $abc$16053$new_n1622 +11000 1 +.names $abc$16053$new_n1624 $abc$16053$new_n1621 $abc$16053$new_n1623 +00 1 +.names is_lui_auipc_jal is_jalr_addi_slti_sltiu_xori_ori_andi $abc$16053$new_n1624 +00 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[30] $abc$16053$new_n1625 +0001 1 +0011 1 +1010 1 +1011 1 +.names decoded_rs2[4] decoded_rs2[3] decoded_rs2[2] decoded_rs2[1] decoded_rs2[0] $abc$16053$new_n1626 +00000 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[29] decoded_imm[29] $abc$16053$new_n1628 $abc$16053$auto$rtlil.cc:2693:MuxGate$14551 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[29] $abc$16053$new_n1628 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[28] decoded_imm[28] $abc$16053$new_n1630 $abc$16053$auto$rtlil.cc:2693:MuxGate$14553 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[28] $abc$16053$new_n1630 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[27] decoded_imm[27] $abc$16053$new_n1632 $abc$16053$auto$rtlil.cc:2693:MuxGate$14555 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[27] $abc$16053$new_n1632 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[26] decoded_imm[26] $abc$16053$new_n1634 $abc$16053$auto$rtlil.cc:2693:MuxGate$14557 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[26] $abc$16053$new_n1634 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[25] decoded_imm[25] $abc$16053$new_n1636 $abc$16053$auto$rtlil.cc:2693:MuxGate$14559 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[25] $abc$16053$new_n1636 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[24] decoded_imm[24] $abc$16053$new_n1638 $abc$16053$auto$rtlil.cc:2693:MuxGate$14561 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[24] $abc$16053$new_n1638 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[23] decoded_imm[23] $abc$16053$new_n1640 $abc$16053$auto$rtlil.cc:2693:MuxGate$14563 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[23] $abc$16053$new_n1640 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[22] decoded_imm[22] $abc$16053$new_n1642 $abc$16053$auto$rtlil.cc:2693:MuxGate$14565 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[22] $abc$16053$new_n1642 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[21] decoded_imm[21] $abc$16053$new_n1644 $abc$16053$auto$rtlil.cc:2693:MuxGate$14567 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[21] $abc$16053$new_n1644 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[20] decoded_imm[20] $abc$16053$new_n1646 $abc$16053$auto$rtlil.cc:2693:MuxGate$14569 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[20] $abc$16053$new_n1646 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[19] decoded_imm[19] $abc$16053$new_n1648 $abc$16053$auto$rtlil.cc:2693:MuxGate$14571 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[19] $abc$16053$new_n1648 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[18] decoded_imm[18] $abc$16053$new_n1650 $abc$16053$auto$rtlil.cc:2693:MuxGate$14573 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[18] $abc$16053$new_n1650 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[17] decoded_imm[17] $abc$16053$new_n1652 $abc$16053$auto$rtlil.cc:2693:MuxGate$14575 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[17] $abc$16053$new_n1652 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[16] decoded_imm[16] $abc$16053$new_n1654 $abc$16053$auto$rtlil.cc:2693:MuxGate$14577 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[16] $abc$16053$new_n1654 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[15] decoded_imm[15] $abc$16053$new_n1656 $abc$16053$auto$rtlil.cc:2693:MuxGate$14579 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[15] $abc$16053$new_n1656 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[14] decoded_imm[14] $abc$16053$new_n1658 $abc$16053$auto$rtlil.cc:2693:MuxGate$14581 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[14] $abc$16053$new_n1658 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[13] decoded_imm[13] $abc$16053$new_n1660 $abc$16053$auto$rtlil.cc:2693:MuxGate$14583 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[13] $abc$16053$new_n1660 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[12] decoded_imm[12] $abc$16053$new_n1662 $abc$16053$auto$rtlil.cc:2693:MuxGate$14585 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[12] $abc$16053$new_n1662 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[11] decoded_imm[11] $abc$16053$new_n1664 $abc$16053$auto$rtlil.cc:2693:MuxGate$14587 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[11] $abc$16053$new_n1664 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[10] decoded_imm[10] $abc$16053$new_n1666 $abc$16053$auto$rtlil.cc:2693:MuxGate$14589 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[10] $abc$16053$new_n1666 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[9] decoded_imm[9] $abc$16053$new_n1668 $abc$16053$auto$rtlil.cc:2693:MuxGate$14591 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[9] $abc$16053$new_n1668 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[8] decoded_imm[8] $abc$16053$new_n1670 $abc$16053$auto$rtlil.cc:2693:MuxGate$14593 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[8] $abc$16053$new_n1670 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[7] decoded_imm[7] $abc$16053$new_n1672 $abc$16053$auto$rtlil.cc:2693:MuxGate$14595 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[7] $abc$16053$new_n1672 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[6] decoded_imm[6] $abc$16053$new_n1674 $abc$16053$auto$rtlil.cc:2693:MuxGate$14597 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[6] $abc$16053$new_n1674 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[5] decoded_imm[5] $abc$16053$new_n1676 $abc$16053$auto$rtlil.cc:2693:MuxGate$14599 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[5] $abc$16053$new_n1676 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[4] decoded_imm[4] $abc$16053$new_n1678 $abc$16053$auto$rtlil.cc:2693:MuxGate$14601 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[4] $abc$16053$new_n1678 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[3] decoded_imm[3] $abc$16053$new_n1680 $abc$16053$auto$rtlil.cc:2693:MuxGate$14603 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[3] $abc$16053$new_n1680 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[2] decoded_imm[2] $abc$16053$new_n1682 $abc$16053$auto$rtlil.cc:2693:MuxGate$14605 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[2] $abc$16053$new_n1682 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[1] decoded_imm[1] $abc$16053$new_n1684 $abc$16053$auto$rtlil.cc:2693:MuxGate$14607 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[1] $abc$16053$new_n1684 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[0] decoded_imm[0] $abc$16053$new_n1686 $abc$16053$auto$rtlil.cc:2693:MuxGate$14609 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[0] $abc$16053$new_n1686 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1691 $abc$16053$new_n1748 $abc$16053$new_n1747 $abc$16053$new_n1690 +100 1 +.names $abc$16053$new_n1692 $abc$16053$new_n1745 $abc$16053$new_n1743 $abc$16053$new_n1741 $abc$16053$new_n1739 $abc$16053$new_n1691 +10000 1 +.names $abc$16053$new_n1693 $abc$16053$new_n1737 $abc$16053$new_n1692 +10 1 +.names $abc$16053$new_n1694 $abc$16053$new_n1735 $abc$16053$new_n1693 +10 1 +.names $abc$16053$new_n1695 $abc$16053$new_n1733 $abc$16053$new_n1731 $abc$16053$new_n1694 +100 1 +.names $abc$16053$new_n1696 $abc$16053$new_n1729 $abc$16053$new_n1728 $abc$16053$new_n1727 $abc$16053$new_n1725 $abc$16053$new_n1695 +10000 1 +.names $abc$16053$new_n1697 $abc$16053$new_n1723 $abc$16053$new_n1722 $abc$16053$new_n1721 $abc$16053$new_n1719 $abc$16053$new_n1696 +10000 1 +.names $abc$16053$new_n1698 $abc$16053$new_n1718 $abc$16053$new_n1717 $abc$16053$new_n1715 $abc$16053$new_n1697 +1000 1 +.names $abc$16053$new_n1699 $abc$16053$new_n1713 $abc$16053$new_n1698 +10 1 +.names $abc$16053$new_n1700 $abc$16053$new_n1711 $abc$16053$new_n1699 +10 1 +.names $abc$16053$new_n1701 $abc$16053$new_n1710 $abc$16053$new_n1700 +10 1 +.names $abc$16053$new_n1702 $abc$16053$new_n1708 $abc$16053$new_n1707 $abc$16053$new_n1701 +100 1 +.names $abc$16053$new_n1706 $abc$16053$new_n1703 $abc$16053$new_n1702 +00 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1705 reg_next_pc[3] $abc$16053$new_n1703 +000 1 +010 1 +110 1 +111 1 +.names latched_branch latched_store $abc$16053$new_n1704 +11 1 +.names latched_stalu alu_out_q[3] reg_out[3] $abc$16053$new_n1705 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[2] alu_out_q[2] reg_out[2] $abc$16053$new_n1706 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[5] alu_out_q[5] reg_out[5] $abc$16053$new_n1707 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1709 reg_next_pc[4] $abc$16053$new_n1708 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[4] reg_out[4] $abc$16053$new_n1709 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[6] alu_out_q[6] reg_out[6] $abc$16053$new_n1710 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1712 reg_next_pc[7] $abc$16053$new_n1711 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[7] reg_out[7] $abc$16053$new_n1712 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1714 reg_next_pc[8] $abc$16053$new_n1713 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[8] reg_out[8] $abc$16053$new_n1714 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1716 reg_next_pc[11] $abc$16053$new_n1715 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[11] reg_out[11] $abc$16053$new_n1716 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[10] alu_out_q[10] reg_out[10] $abc$16053$new_n1717 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[9] alu_out_q[9] reg_out[9] $abc$16053$new_n1718 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1720 reg_next_pc[15] $abc$16053$new_n1719 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[15] reg_out[15] $abc$16053$new_n1720 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[14] alu_out_q[14] reg_out[14] $abc$16053$new_n1721 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[13] alu_out_q[13] reg_out[13] $abc$16053$new_n1722 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1724 reg_next_pc[12] $abc$16053$new_n1723 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[12] reg_out[12] $abc$16053$new_n1724 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1726 reg_next_pc[19] $abc$16053$new_n1725 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[19] reg_out[19] $abc$16053$new_n1726 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[18] alu_out_q[18] reg_out[18] $abc$16053$new_n1727 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[17] alu_out_q[17] reg_out[17] $abc$16053$new_n1728 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1730 reg_next_pc[16] $abc$16053$new_n1729 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[16] reg_out[16] $abc$16053$new_n1730 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1732 reg_next_pc[21] $abc$16053$new_n1731 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[21] reg_out[21] $abc$16053$new_n1732 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1734 reg_next_pc[20] $abc$16053$new_n1733 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[20] reg_out[20] $abc$16053$new_n1734 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1736 reg_next_pc[22] $abc$16053$new_n1735 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[22] reg_out[22] $abc$16053$new_n1736 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1738 reg_next_pc[23] $abc$16053$new_n1737 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[23] reg_out[23] $abc$16053$new_n1738 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1740 reg_next_pc[27] $abc$16053$new_n1739 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[27] reg_out[27] $abc$16053$new_n1740 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1742 reg_next_pc[26] $abc$16053$new_n1741 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[26] reg_out[26] $abc$16053$new_n1742 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1744 reg_next_pc[25] $abc$16053$new_n1743 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[25] reg_out[25] $abc$16053$new_n1744 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1746 reg_next_pc[24] $abc$16053$new_n1745 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[24] reg_out[24] $abc$16053$new_n1746 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[29] alu_out_q[29] reg_out[29] $abc$16053$new_n1747 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1749 reg_next_pc[28] $abc$16053$new_n1748 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[28] reg_out[28] $abc$16053$new_n1749 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[30] alu_out_q[30] reg_out[30] $abc$16053$new_n1750 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1748 decoded_imm_j[28] decoded_imm_j[29] $abc$16053$new_n1747 $abc$16053$new_n1752 $abc$16053$new_n1751 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1741 decoded_imm_j[26] decoded_imm_j[27] $abc$16053$new_n1739 $abc$16053$new_n1753 $abc$16053$new_n1752 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1745 decoded_imm_j[24] decoded_imm_j[25] $abc$16053$new_n1743 $abc$16053$new_n1754 $abc$16053$new_n1753 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1735 decoded_imm_j[22] decoded_imm_j[23] $abc$16053$new_n1737 $abc$16053$new_n1755 $abc$16053$new_n1754 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1733 decoded_imm_j[20] decoded_imm_j[21] $abc$16053$new_n1731 $abc$16053$new_n1756 $abc$16053$new_n1755 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1727 decoded_imm_j[18] decoded_imm_j[19] $abc$16053$new_n1725 $abc$16053$new_n1757 $abc$16053$new_n1756 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1729 decoded_imm_j[16] decoded_imm_j[17] $abc$16053$new_n1728 $abc$16053$new_n1758 $abc$16053$new_n1757 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1721 decoded_imm_j[14] decoded_imm_j[15] $abc$16053$new_n1719 $abc$16053$new_n1759 $abc$16053$new_n1758 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1723 decoded_imm_j[12] decoded_imm_j[13] $abc$16053$new_n1722 $abc$16053$new_n1760 $abc$16053$new_n1759 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1717 decoded_imm_j[10] decoded_imm_j[11] $abc$16053$new_n1715 $abc$16053$new_n1761 $abc$16053$new_n1760 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1713 decoded_imm_j[8] decoded_imm_j[9] $abc$16053$new_n1718 $abc$16053$new_n1762 $abc$16053$new_n1761 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1710 decoded_imm_j[6] decoded_imm_j[7] $abc$16053$new_n1711 $abc$16053$new_n1763 $abc$16053$new_n1762 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1708 decoded_imm_j[4] decoded_imm_j[5] $abc$16053$new_n1707 $abc$16053$new_n1764 $abc$16053$new_n1763 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names decoded_imm_j[3] decoded_imm_j[2] $abc$16053$new_n1765 $abc$16053$new_n1706 $abc$16053$new_n1703 $abc$16053$new_n1764 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +.names decoded_imm_j[1] $abc$16053$new_n1704 $abc$16053$new_n1766 reg_next_pc[1] $abc$16053$new_n1765 +1001 1 +1011 1 +1100 1 +1101 1 +.names latched_stalu alu_out_q[1] reg_out[1] $abc$16053$new_n1766 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1748 decoded_imm_j[28] $abc$16053$new_n1752 $abc$16053$new_n1769 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1778 $abc$16053$new_n1743 $abc$16053$new_n1777 +10 1 +.names $abc$16053$new_n1692 $abc$16053$new_n1745 $abc$16053$new_n1778 +10 1 +.names decoded_imm_j[24] $abc$16053$new_n1745 $abc$16053$new_n1754 $abc$16053$new_n1787 +000 1 +100 1 +101 1 +110 1 +.names $abc$16053$new_n1735 decoded_imm_j[22] $abc$16053$new_n1755 $abc$16053$new_n1793 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1733 decoded_imm_j[20] $abc$16053$new_n1756 $abc$16053$new_n1800 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1809 $abc$16053$new_n1728 $abc$16053$new_n1808 +10 1 +.names $abc$16053$new_n1696 $abc$16053$new_n1729 $abc$16053$new_n1809 +10 1 +.names decoded_imm_j[16] $abc$16053$new_n1729 $abc$16053$new_n1758 $abc$16053$new_n1818 +000 1 +100 1 +101 1 +110 1 +.names $abc$16053$new_n1826 $abc$16053$new_n1722 $abc$16053$new_n1825 +10 1 +.names $abc$16053$new_n1697 $abc$16053$new_n1723 $abc$16053$new_n1826 +10 1 +.names $abc$16053$new_n1723 decoded_imm_j[12] $abc$16053$new_n1760 $abc$16053$new_n1835 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1698 $abc$16053$new_n1718 $abc$16053$new_n1842 +10 1 +.names $abc$16053$new_n1713 decoded_imm_j[8] $abc$16053$new_n1762 $abc$16053$new_n1851 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1710 decoded_imm_j[6] $abc$16053$new_n1763 $abc$16053$new_n1858 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1612 decoder_trigger reg_next_pc[6] $abc$16053$new_n1860 $abc$16053$new_n1710 $abc$16053$auto$rtlil.cc:2693:MuxGate$14659 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instr_jal $abc$16053$new_n1710 decoded_imm_j[6] $abc$16053$new_n1763 $abc$16053$new_n1701 $abc$16053$new_n1860 +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 decoder_trigger reg_next_pc[4] $abc$16053$new_n1866 $abc$16053$new_n1708 $abc$16053$auto$rtlil.cc:2693:MuxGate$14663 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instr_jal $abc$16053$new_n1708 decoded_imm_j[4] $abc$16053$new_n1764 $abc$16053$new_n1702 $abc$16053$new_n1866 +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1872 reg_next_pc[2] $abc$16053$new_n1706 decoder_trigger $abc$16053$auto$rtlil.cc:2693:MuxGate$14667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names decoder_trigger $abc$16053$new_n1706 decoded_imm_j[2] $abc$16053$new_n1765 instr_jal $abc$16053$new_n1872 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names $abc$16053$new_n1874 reg_next_pc[1] $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$14669 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1875 decoder_trigger instr_jal decoded_imm_j[1] $abc$16053$new_n1874 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11111 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1766 reg_next_pc[1] $abc$16053$new_n1875 +000 1 +010 1 +110 1 +111 1 +.names reg_next_pc[0] $abc$16053$new_n1612 $abc$16053$new_n1704 $abc$16053$auto$rtlil.cc:2693:MuxGate$14671 +100 1 +101 1 +110 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1750 reg_pc[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14673 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1747 reg_pc[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14675 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1748 reg_pc[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14677 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1739 reg_pc[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14679 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1741 reg_pc[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14681 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1743 reg_pc[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14683 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1745 reg_pc[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14685 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1737 reg_pc[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14687 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1735 reg_pc[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14689 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1731 reg_pc[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14691 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1733 reg_pc[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14693 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1725 reg_pc[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14695 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1727 reg_pc[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14697 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1728 reg_pc[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14699 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1729 reg_pc[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14701 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1719 reg_pc[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14703 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1721 reg_pc[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14705 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1722 reg_pc[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14707 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1723 reg_pc[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14709 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1715 reg_pc[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14711 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1717 reg_pc[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14713 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1718 reg_pc[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14715 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1713 reg_pc[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14717 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1711 reg_pc[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14719 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1710 reg_pc[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14721 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1707 reg_pc[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14723 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1708 reg_pc[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14725 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1703 reg_pc[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14727 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1706 reg_pc[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14729 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1875 reg_pc[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14731 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 reg_pc[0] reg_next_pc[0] $abc$16053$new_n1704 $abc$16053$auto$rtlil.cc:2693:MuxGate$14733 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names count_instr[62] $abc$16053$new_n1909 $abc$16053$auto$rtlil.cc:2693:MuxGate$14735 +01 1 +10 1 +.names count_instr[58] count_instr[59] count_instr[60] count_instr[61] $abc$16053$new_n1910 $abc$16053$new_n1909 +11111 1 +.names count_instr[54] count_instr[55] count_instr[56] count_instr[57] $abc$16053$new_n1911 $abc$16053$new_n1910 +11111 1 +.names count_instr[50] count_instr[51] count_instr[52] count_instr[53] $abc$16053$new_n1912 $abc$16053$new_n1911 +11111 1 +.names count_instr[46] count_instr[47] count_instr[48] count_instr[49] $abc$16053$new_n1913 $abc$16053$new_n1912 +11111 1 +.names count_instr[42] count_instr[43] count_instr[44] count_instr[45] $abc$16053$new_n1914 $abc$16053$new_n1913 +11111 1 +.names count_instr[38] count_instr[39] count_instr[40] count_instr[41] $abc$16053$new_n1915 $abc$16053$new_n1914 +11111 1 +.names count_instr[34] count_instr[35] count_instr[36] count_instr[37] $abc$16053$new_n1916 $abc$16053$new_n1915 +11111 1 +.names count_instr[30] count_instr[31] count_instr[32] count_instr[33] $abc$16053$new_n1917 $abc$16053$new_n1916 +11111 1 +.names count_instr[26] count_instr[27] count_instr[28] count_instr[29] $abc$16053$new_n1918 $abc$16053$new_n1917 +11111 1 +.names count_instr[22] count_instr[23] count_instr[24] count_instr[25] $abc$16053$new_n1919 $abc$16053$new_n1918 +11111 1 +.names count_instr[18] count_instr[19] count_instr[20] count_instr[21] $abc$16053$new_n1920 $abc$16053$new_n1919 +11111 1 +.names count_instr[14] count_instr[15] count_instr[16] count_instr[17] $abc$16053$new_n1921 $abc$16053$new_n1920 +11111 1 +.names count_instr[10] count_instr[11] count_instr[12] count_instr[13] $abc$16053$new_n1922 $abc$16053$new_n1921 +11111 1 +.names count_instr[6] count_instr[7] count_instr[8] count_instr[9] $abc$16053$new_n1923 $abc$16053$new_n1922 +11111 1 +.names count_instr[2] count_instr[3] count_instr[4] count_instr[5] $abc$16053$new_n1924 $abc$16053$new_n1923 +11111 1 +.names decoder_trigger count_instr[0] count_instr[1] $abc$16053$new_n1614 $abc$16053$new_n1613 $abc$16053$new_n1924 +11111 1 +.names count_instr[61] count_instr[58] count_instr[59] count_instr[60] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14737 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[60] count_instr[58] count_instr[59] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14739 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[59] count_instr[58] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14741 +011 1 +100 1 +101 1 +110 1 +.names count_instr[58] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14743 +01 1 +10 1 +.names count_instr[57] count_instr[54] count_instr[55] count_instr[56] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14745 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[56] count_instr[54] count_instr[55] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14747 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[55] count_instr[54] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14749 +011 1 +100 1 +101 1 +110 1 +.names count_instr[54] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14751 +01 1 +10 1 +.names count_instr[53] count_instr[50] count_instr[51] count_instr[52] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14753 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[52] count_instr[50] count_instr[51] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14755 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[51] count_instr[50] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14757 +011 1 +100 1 +101 1 +110 1 +.names count_instr[50] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14759 +01 1 +10 1 +.names count_instr[49] count_instr[46] count_instr[47] count_instr[48] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14761 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[48] count_instr[46] count_instr[47] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14763 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[47] count_instr[46] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14765 +011 1 +100 1 +101 1 +110 1 +.names count_instr[46] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14767 +01 1 +10 1 +.names count_instr[45] count_instr[42] count_instr[43] count_instr[44] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14769 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[44] count_instr[42] count_instr[43] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14771 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[43] count_instr[42] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14773 +011 1 +100 1 +101 1 +110 1 +.names count_instr[42] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14775 +01 1 +10 1 +.names count_instr[41] count_instr[38] count_instr[39] count_instr[40] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14777 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[40] count_instr[38] count_instr[39] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14779 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[39] count_instr[38] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14781 +011 1 +100 1 +101 1 +110 1 +.names count_instr[38] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14783 +01 1 +10 1 +.names count_instr[37] count_instr[34] count_instr[35] count_instr[36] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14785 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[36] count_instr[34] count_instr[35] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14787 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[35] count_instr[34] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14789 +011 1 +100 1 +101 1 +110 1 +.names count_instr[34] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14791 +01 1 +10 1 +.names count_instr[33] count_instr[30] count_instr[31] count_instr[32] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14793 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[32] count_instr[30] count_instr[31] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14795 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[31] count_instr[30] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14797 +011 1 +100 1 +101 1 +110 1 +.names count_instr[30] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14799 +01 1 +10 1 +.names count_instr[29] count_instr[26] count_instr[27] count_instr[28] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14801 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[28] count_instr[26] count_instr[27] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14803 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[27] count_instr[26] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14805 +011 1 +100 1 +101 1 +110 1 +.names count_instr[26] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14807 +01 1 +10 1 +.names count_instr[25] count_instr[22] count_instr[23] count_instr[24] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14809 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[24] count_instr[22] count_instr[23] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14811 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[23] count_instr[22] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14813 +011 1 +100 1 +101 1 +110 1 +.names count_instr[22] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14815 +01 1 +10 1 +.names count_instr[21] count_instr[18] count_instr[19] count_instr[20] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14817 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[20] count_instr[18] count_instr[19] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14819 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[19] count_instr[18] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14821 +011 1 +100 1 +101 1 +110 1 +.names count_instr[18] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14823 +01 1 +10 1 +.names count_instr[17] count_instr[16] $abc$16053$new_n1970 $abc$16053$auto$rtlil.cc:2693:MuxGate$14825 +011 1 +100 1 +101 1 +110 1 +.names count_instr[14] count_instr[15] $abc$16053$new_n1921 $abc$16053$new_n1970 +111 1 +.names count_instr[16] $abc$16053$new_n1970 $abc$16053$auto$rtlil.cc:2693:MuxGate$14827 +01 1 +10 1 +.names count_instr[15] count_instr[14] $abc$16053$new_n1921 $abc$16053$auto$rtlil.cc:2693:MuxGate$14829 +011 1 +100 1 +101 1 +110 1 +.names count_instr[14] $abc$16053$new_n1921 $abc$16053$auto$rtlil.cc:2693:MuxGate$14831 +01 1 +10 1 +.names count_instr[13] count_instr[12] $abc$16053$new_n1975 $abc$16053$auto$rtlil.cc:2693:MuxGate$14833 +011 1 +100 1 +101 1 +110 1 +.names count_instr[10] count_instr[11] $abc$16053$new_n1922 $abc$16053$new_n1975 +111 1 +.names count_instr[12] $abc$16053$new_n1975 $abc$16053$auto$rtlil.cc:2693:MuxGate$14835 +01 1 +10 1 +.names count_instr[11] count_instr[10] $abc$16053$new_n1922 $abc$16053$auto$rtlil.cc:2693:MuxGate$14837 +011 1 +100 1 +101 1 +110 1 +.names count_instr[10] $abc$16053$new_n1922 $abc$16053$auto$rtlil.cc:2693:MuxGate$14839 +01 1 +10 1 +.names count_instr[9] count_instr[8] $abc$16053$new_n1980 $abc$16053$auto$rtlil.cc:2693:MuxGate$14841 +011 1 +100 1 +101 1 +110 1 +.names count_instr[6] count_instr[7] $abc$16053$new_n1923 $abc$16053$new_n1980 +111 1 +.names count_instr[8] $abc$16053$new_n1980 $abc$16053$auto$rtlil.cc:2693:MuxGate$14843 +01 1 +10 1 +.names count_instr[7] count_instr[6] $abc$16053$new_n1923 $abc$16053$auto$rtlil.cc:2693:MuxGate$14845 +011 1 +100 1 +101 1 +110 1 +.names count_instr[6] $abc$16053$new_n1923 $abc$16053$auto$rtlil.cc:2693:MuxGate$14847 +01 1 +10 1 +.names count_instr[5] count_instr[3] count_instr[4] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14849 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[2] $abc$16053$new_n1924 $abc$16053$new_n1985 +11 1 +.names count_instr[4] count_instr[3] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14851 +011 1 +100 1 +101 1 +110 1 +.names count_instr[3] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14853 +01 1 +10 1 +.names count_instr[2] $abc$16053$new_n1924 $abc$16053$auto$rtlil.cc:2693:MuxGate$14855 +01 1 +10 1 +.names count_instr[1] decoder_trigger count_instr[0] $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$14857 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[0] $abc$16053$new_n1991 $abc$16053$auto$rtlil.cc:2693:MuxGate$14859 +01 1 +10 1 +.names decoder_trigger $abc$16053$new_n1612 $abc$16053$new_n1991 +11 1 +.names $abc$16053$new_n1472 mem_rdata[11] mem_rdata_q[11] mem_rdata_latched[11] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[6] mem_rdata_q[6] mem_rdata_latched[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[5] mem_rdata_q[5] mem_rdata_latched[5] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[4] mem_rdata_q[4] mem_rdata_latched[4] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[3] mem_rdata_q[3] mem_rdata_latched[3] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[2] mem_rdata_q[2] mem_rdata_latched[2] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[1] mem_rdata_q[1] mem_rdata_latched[1] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[0] mem_rdata_q[0] mem_rdata_latched[0] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2001 pcpi_rs1[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14923 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2017 pcpi_rs1[29] decoded_imm[29] $abc$16053$new_n2002 $abc$16053$new_n2019 $abc$16053$new_n2001 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs1[27] decoded_imm[27] pcpi_rs1[28] decoded_imm[28] $abc$16053$new_n2003 $abc$16053$new_n2002 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[25] decoded_imm[25] pcpi_rs1[26] decoded_imm[26] $abc$16053$new_n2004 $abc$16053$new_n2003 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[23] decoded_imm[23] pcpi_rs1[24] decoded_imm[24] $abc$16053$new_n2005 $abc$16053$new_n2004 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[21] decoded_imm[21] pcpi_rs1[22] decoded_imm[22] $abc$16053$new_n2006 $abc$16053$new_n2005 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[19] decoded_imm[19] pcpi_rs1[20] decoded_imm[20] $abc$16053$new_n2007 $abc$16053$new_n2006 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[17] decoded_imm[17] pcpi_rs1[18] decoded_imm[18] $abc$16053$new_n2008 $abc$16053$new_n2007 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[15] decoded_imm[15] pcpi_rs1[16] decoded_imm[16] $abc$16053$new_n2009 $abc$16053$new_n2008 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[13] decoded_imm[13] pcpi_rs1[14] decoded_imm[14] $abc$16053$new_n2010 $abc$16053$new_n2009 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[11] decoded_imm[11] pcpi_rs1[12] decoded_imm[12] $abc$16053$new_n2011 $abc$16053$new_n2010 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[9] decoded_imm[9] pcpi_rs1[10] decoded_imm[10] $abc$16053$new_n2012 $abc$16053$new_n2011 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[7] decoded_imm[7] pcpi_rs1[8] decoded_imm[8] $abc$16053$new_n2013 $abc$16053$new_n2012 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[5] decoded_imm[5] pcpi_rs1[6] decoded_imm[6] $abc$16053$new_n2014 $abc$16053$new_n2013 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[3] decoded_imm[3] pcpi_rs1[4] decoded_imm[4] $abc$16053$new_n2015 $abc$16053$new_n2014 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[2] decoded_imm[2] $abc$16053$new_n2016 $abc$16053$new_n2015 +000 1 +001 1 +011 1 +101 1 +.names pcpi_rs1[0] decoded_imm[0] pcpi_rs1[1] decoded_imm[1] $abc$16053$new_n2016 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$16053$new_n2023 $abc$16053$new_n2029 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[29] $abc$16053$new_n2017 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2018 +10 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2020 $abc$16053$new_n2019 +00 1 +.names $abc$16053$new_n1611 cpu_state[1] cpu_state[3] cpu_state[0] cpu_state[2] $abc$16053$new_n2020 +11000 1 +.names cpu_state[0] $abc$16053$new_n1611 cpu_state[3] cpu_state[1] cpu_state[2] $abc$16053$new_n2021 +11000 1 +.names $abc$16053$new_n1611 cpu_state[2] cpu_state[3] cpu_state[1] cpu_state[0] $abc$16053$new_n2022 +11000 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2024 $abc$16053$new_n2028 pcpi_rs1[25] $abc$16053$new_n2025 $abc$16053$new_n2023 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[28] pcpi_rs1[30] $abc$16053$new_n2024 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n2026 instr_srl instr_srli $abc$16053$new_n2025 +100 1 +.names instr_sra instr_srai $abc$16053$new_n2026 +00 1 +.names reg_sh[3] reg_sh[2] reg_sh[4] $abc$16053$new_n2027 +000 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2026 pcpi_rs1[31] $abc$16053$new_n2028 +000 1 +010 1 +011 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[29] $abc$16053$new_n2029 +1001 1 +1011 1 +1110 1 +1111 1 +.names is_lui_auipc_jal $abc$16053$new_n2031 $abc$16053$new_n2030 +00 1 +.names decoded_rs1[4] decoded_rs1[3] decoded_rs1[2] decoded_rs1[1] decoded_rs1[0] $abc$16053$new_n2031 +00000 1 +.names is_lui_auipc_jal instr_lui $abc$16053$new_n2032 +10 1 +.names resetn $abc$16053$new_n2036 $abc$16053$new_n2034 $abc$16053$new_n2035 $abc$16053$new_n2021 $abc$16053$new_n2033 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2035 $abc$16053$new_n2020 mem_do_wdata mem_do_rdata $abc$16053$new_n2021 $abc$16053$new_n2034 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names mem_do_prefetch $abc$16053$new_n1549 $abc$16053$new_n2035 +11 1 +.names $abc$16053$new_n2038 $abc$16053$new_n2018 $abc$16053$new_n2039 cpu_state[2] $abc$16053$new_n1622 $abc$16053$new_n2036 +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2027 reg_sh[0] reg_sh[1] $abc$16053$new_n2038 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2025 instr_sll instr_slli $abc$16053$new_n2039 +100 1 +.names $abc$16053$new_n2033 $abc$16053$new_n3156 pcpi_rs1[28] $abc$16053$new_n2041 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14925 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names pcpi_rs1[28] decoded_imm[28] pcpi_rs1[27] decoded_imm[27] $abc$16053$new_n2003 $abc$16053$new_n2041 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2044 reg_pc[28] $abc$16053$new_n2032 $abc$16053$new_n2043 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[28] $abc$16053$new_n2044 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[27] $abc$16053$new_n2049 $abc$16053$new_n2048 $abc$16053$auto$rtlil.cc:2693:MuxGate$14927 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names pcpi_rs1[27] decoded_imm[27] $abc$16053$new_n2003 $abc$16053$new_n2019 $abc$16053$new_n2048 +0000 1 +0110 1 +1010 1 +1100 1 +.names $abc$16053$new_n2050 $abc$16053$new_n2052 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[27] $abc$16053$new_n2049 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2051 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[23] pcpi_rs1[31] $abc$16053$new_n2050 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[26] pcpi_rs1[28] $abc$16053$new_n2051 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[27] $abc$16053$new_n2052 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2055 pcpi_rs1[26] $abc$16053$new_n2054 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14929 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[26] decoded_imm[26] pcpi_rs1[25] decoded_imm[25] $abc$16053$new_n2004 $abc$16053$new_n2054 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2056 $abc$16053$new_n2058 $abc$16053$new_n2055 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2057 pcpi_rs1[22] pcpi_rs1[30] $abc$16053$new_n2056 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2025 pcpi_rs1[25] pcpi_rs1[27] $abc$16053$new_n2057 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2059 $abc$16053$new_n2032 reg_pc[26] $abc$16053$new_n2058 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[26] $abc$16053$new_n2059 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[25] $abc$16053$new_n2061 $abc$16053$new_n2062 $abc$16053$auto$rtlil.cc:2693:MuxGate$14931 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[25] decoded_imm[25] $abc$16053$new_n2004 $abc$16053$new_n2019 $abc$16053$new_n2061 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2063 $abc$16053$new_n2065 $abc$16053$new_n2062 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2064 pcpi_rs1[24] pcpi_rs1[26] $abc$16053$new_n2063 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[21] pcpi_rs1[29] $abc$16053$new_n2064 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2066 $abc$16053$new_n2032 reg_pc[25] $abc$16053$new_n2065 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[25] $abc$16053$new_n2066 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2069 pcpi_rs1[24] $abc$16053$new_n2068 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14933 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[24] decoded_imm[24] pcpi_rs1[23] decoded_imm[23] $abc$16053$new_n2005 $abc$16053$new_n2068 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2070 $abc$16053$new_n2072 $abc$16053$new_n2069 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2071 pcpi_rs1[23] pcpi_rs1[25] $abc$16053$new_n2070 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[20] pcpi_rs1[28] $abc$16053$new_n2071 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2073 $abc$16053$new_n2032 reg_pc[24] $abc$16053$new_n2072 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[24] $abc$16053$new_n2073 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[23] $abc$16053$new_n2075 $abc$16053$new_n2076 $abc$16053$auto$rtlil.cc:2693:MuxGate$14935 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[23] decoded_imm[23] $abc$16053$new_n2005 $abc$16053$new_n2019 $abc$16053$new_n2075 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2077 $abc$16053$new_n2079 $abc$16053$new_n2076 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2078 pcpi_rs1[22] pcpi_rs1[24] $abc$16053$new_n2077 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[19] pcpi_rs1[27] $abc$16053$new_n2078 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2080 $abc$16053$new_n2032 reg_pc[23] $abc$16053$new_n2079 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[23] $abc$16053$new_n2080 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[21] decoded_imm[21] $abc$16053$new_n2006 $abc$16053$new_n2084 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2086 $abc$16053$new_n2032 reg_pc[22] $abc$16053$new_n2085 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[22] $abc$16053$new_n2086 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2090 pcpi_rs1[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14939 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2091 pcpi_rs1[21] decoded_imm[21] $abc$16053$new_n2006 $abc$16053$new_n2019 $abc$16053$new_n2090 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2092 $abc$16053$new_n2094 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[21] $abc$16053$new_n2091 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2093 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[17] pcpi_rs1[25] $abc$16053$new_n2092 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[20] pcpi_rs1[22] $abc$16053$new_n2093 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[21] $abc$16053$new_n2094 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2097 pcpi_rs1[20] $abc$16053$new_n2096 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14941 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[20] decoded_imm[20] pcpi_rs1[19] decoded_imm[19] $abc$16053$new_n2007 $abc$16053$new_n2096 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2098 $abc$16053$new_n2100 $abc$16053$new_n2097 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2099 pcpi_rs1[19] pcpi_rs1[21] $abc$16053$new_n2098 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[16] pcpi_rs1[24] $abc$16053$new_n2099 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2101 $abc$16053$new_n2032 reg_pc[20] $abc$16053$new_n2100 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[20] $abc$16053$new_n2101 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[19] $abc$16053$new_n2106 $abc$16053$new_n2104 $abc$16053$new_n2103 $abc$16053$auto$rtlil.cc:2693:MuxGate$14943 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs1[19] decoded_imm[19] $abc$16053$new_n2007 $abc$16053$new_n2019 $abc$16053$new_n2103 +0000 1 +0110 1 +1010 1 +1100 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2105 reg_pc[19] $abc$16053$new_n2032 $abc$16053$new_n2104 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[19] $abc$16053$new_n2105 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2107 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[18] pcpi_rs1[20] $abc$16053$new_n2106 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[15] pcpi_rs1[23] $abc$16053$new_n2107 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2110 pcpi_rs1[18] $abc$16053$new_n2109 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14945 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[18] decoded_imm[18] pcpi_rs1[17] decoded_imm[17] $abc$16053$new_n2008 $abc$16053$new_n2109 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2111 $abc$16053$new_n2113 $abc$16053$new_n2110 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2112 pcpi_rs1[17] pcpi_rs1[19] $abc$16053$new_n2111 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[14] pcpi_rs1[22] $abc$16053$new_n2112 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2114 $abc$16053$new_n2032 reg_pc[18] $abc$16053$new_n2113 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[18] $abc$16053$new_n2114 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[17] $abc$16053$new_n2116 $abc$16053$new_n2117 $abc$16053$auto$rtlil.cc:2693:MuxGate$14947 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[17] decoded_imm[17] $abc$16053$new_n2008 $abc$16053$new_n2019 $abc$16053$new_n2116 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2118 $abc$16053$new_n2120 $abc$16053$new_n2117 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2119 pcpi_rs1[16] pcpi_rs1[18] $abc$16053$new_n2118 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[21] $abc$16053$new_n2119 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2121 $abc$16053$new_n2032 reg_pc[17] $abc$16053$new_n2120 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[17] $abc$16053$new_n2121 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2124 pcpi_rs1[16] $abc$16053$new_n2123 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14949 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[16] decoded_imm[16] pcpi_rs1[15] decoded_imm[15] $abc$16053$new_n2009 $abc$16053$new_n2123 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2125 $abc$16053$new_n2128 $abc$16053$new_n2127 $abc$16053$new_n2124 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2126 $abc$16053$new_n2032 reg_pc[16] $abc$16053$new_n2125 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[16] $abc$16053$new_n2126 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[15] pcpi_rs1[17] $abc$16053$new_n2127 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[12] pcpi_rs1[20] $abc$16053$new_n2128 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$16053$new_n2033 pcpi_rs1[15] $abc$16053$new_n2130 $abc$16053$new_n2131 $abc$16053$auto$rtlil.cc:2693:MuxGate$14951 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[15] decoded_imm[15] $abc$16053$new_n2009 $abc$16053$new_n2019 $abc$16053$new_n2130 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2132 $abc$16053$new_n2134 $abc$16053$new_n2131 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2133 pcpi_rs1[14] pcpi_rs1[16] $abc$16053$new_n2132 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[11] pcpi_rs1[19] $abc$16053$new_n2133 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2135 $abc$16053$new_n2032 reg_pc[15] $abc$16053$new_n2134 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[15] $abc$16053$new_n2135 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[13] decoded_imm[13] $abc$16053$new_n2010 $abc$16053$new_n2139 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2141 $abc$16053$new_n2032 reg_pc[14] $abc$16053$new_n2140 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[14] $abc$16053$new_n2141 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[13] $abc$16053$new_n2146 $abc$16053$new_n2145 $abc$16053$auto$rtlil.cc:2693:MuxGate$14955 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names pcpi_rs1[13] decoded_imm[13] $abc$16053$new_n2010 $abc$16053$new_n2019 $abc$16053$new_n2145 +0000 1 +0110 1 +1010 1 +1100 1 +.names $abc$16053$new_n2147 $abc$16053$new_n2149 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[13] $abc$16053$new_n2146 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2148 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[9] pcpi_rs1[17] $abc$16053$new_n2147 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[12] pcpi_rs1[14] $abc$16053$new_n2148 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[13] $abc$16053$new_n2149 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[11] decoded_imm[11] $abc$16053$new_n2011 $abc$16053$new_n2153 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2155 $abc$16053$new_n2032 reg_pc[12] $abc$16053$new_n2154 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[12] $abc$16053$new_n2155 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[11] $abc$16053$new_n2162 $abc$16053$new_n2160 $abc$16053$new_n2159 $abc$16053$auto$rtlil.cc:2693:MuxGate$14959 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs1[11] decoded_imm[11] $abc$16053$new_n2011 $abc$16053$new_n2019 $abc$16053$new_n2159 +0000 1 +0110 1 +1010 1 +1100 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2161 reg_pc[11] $abc$16053$new_n2032 $abc$16053$new_n2160 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[11] $abc$16053$new_n2161 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2163 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[7] pcpi_rs1[15] $abc$16053$new_n2162 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[10] pcpi_rs1[12] $abc$16053$new_n2163 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2166 pcpi_rs1[10] $abc$16053$new_n2165 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14961 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[10] decoded_imm[10] pcpi_rs1[9] decoded_imm[9] $abc$16053$new_n2012 $abc$16053$new_n2165 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2167 $abc$16053$new_n2169 $abc$16053$new_n2166 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2168 pcpi_rs1[9] pcpi_rs1[11] $abc$16053$new_n2167 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[6] pcpi_rs1[14] $abc$16053$new_n2168 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2170 $abc$16053$new_n2032 reg_pc[10] $abc$16053$new_n2169 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[10] $abc$16053$new_n2170 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[9] $abc$16053$new_n2173 $abc$16053$new_n2172 $abc$16053$auto$rtlil.cc:2693:MuxGate$14963 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[9] decoded_imm[9] $abc$16053$new_n2012 $abc$16053$new_n2019 $abc$16053$new_n2172 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2174 $abc$16053$new_n2176 $abc$16053$new_n2173 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2175 pcpi_rs1[8] pcpi_rs1[10] $abc$16053$new_n2174 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[5] pcpi_rs1[13] $abc$16053$new_n2175 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2177 $abc$16053$new_n2032 reg_pc[9] $abc$16053$new_n2176 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[9] $abc$16053$new_n2177 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2179 pcpi_rs1[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14965 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2181 $abc$16053$new_n2183 $abc$16053$new_n2180 $abc$16053$new_n2019 $abc$16053$new_n2179 +0000 1 +0001 1 +0011 1 +.names pcpi_rs1[8] decoded_imm[8] pcpi_rs1[7] decoded_imm[7] $abc$16053$new_n2013 $abc$16053$new_n2180 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2182 reg_pc[8] $abc$16053$new_n2032 $abc$16053$new_n2181 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[8] $abc$16053$new_n2182 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2184 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[4] pcpi_rs1[12] $abc$16053$new_n2183 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[7] pcpi_rs1[9] $abc$16053$new_n2184 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2189 pcpi_rs1[6] pcpi_rs1[8] $abc$16053$new_n2188 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[3] pcpi_rs1[11] $abc$16053$new_n2189 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2191 $abc$16053$new_n2032 reg_pc[7] $abc$16053$new_n2190 +000 1 +001 1 +010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[7] $abc$16053$new_n2191 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2193 pcpi_rs1[6] $abc$16053$new_n2197 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14969 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$16053$new_n2194 $abc$16053$new_n2196 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[6] $abc$16053$new_n2193 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2195 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[2] pcpi_rs1[10] $abc$16053$new_n2194 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[5] pcpi_rs1[7] $abc$16053$new_n2195 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[6] $abc$16053$new_n2196 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[6] decoded_imm[6] pcpi_rs1[5] decoded_imm[5] $abc$16053$new_n2014 $abc$16053$new_n2197 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2199 pcpi_rs1[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14971 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2200 pcpi_rs1[5] decoded_imm[5] $abc$16053$new_n2014 $abc$16053$new_n2019 $abc$16053$new_n2199 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2201 $abc$16053$new_n2203 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[5] $abc$16053$new_n2200 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2202 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[4] pcpi_rs1[6] $abc$16053$new_n2201 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[1] pcpi_rs1[9] $abc$16053$new_n2202 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[5] $abc$16053$new_n2203 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2205 pcpi_rs1[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14973 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2206 $abc$16053$new_n2210 $abc$16053$new_n2208 $abc$16053$new_n2205 +00010 1 +00011 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2207 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[0] pcpi_rs1[8] $abc$16053$new_n2206 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[3] pcpi_rs1[5] $abc$16053$new_n2207 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n2209 $abc$16053$new_n2032 reg_pc[4] $abc$16053$new_n2208 +000 1 +001 1 +010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[4] $abc$16053$new_n2209 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[4] decoded_imm[4] pcpi_rs1[3] decoded_imm[3] $abc$16053$new_n2015 $abc$16053$new_n2210 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2213 reg_pc[3] $abc$16053$new_n2032 $abc$16053$new_n2212 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[3] $abc$16053$new_n2213 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2218 pcpi_rs1[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14977 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2222 $abc$16053$new_n2221 $abc$16053$new_n2219 $abc$16053$new_n2218 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2220 $abc$16053$new_n2032 reg_pc[2] $abc$16053$new_n2219 +000 1 +001 1 +010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[2] $abc$16053$new_n2220 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[1] pcpi_rs1[3] pcpi_rs1[6] $abc$16053$new_n2221 +00001 1 +00011 1 +00101 1 +00111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs1[2] decoded_imm[2] $abc$16053$new_n2016 $abc$16053$new_n2222 +000 1 +011 1 +101 1 +110 1 +.names $abc$16053$new_n2226 $abc$16053$new_n2227 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[1] $abc$16053$new_n2225 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names pcpi_rs1[1] decoded_imm[1] $abc$16053$new_n2019 pcpi_rs1[0] decoded_imm[0] $abc$16053$new_n2226 +00011 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +11011 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[1] $abc$16053$new_n2227 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2230 $abc$16053$new_n2033 pcpi_rs1[0] decoded_imm[0] $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14981 +00100 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n2232 $abc$16053$new_n2231 reg_pc[0] $abc$16053$new_n2032 $abc$16053$new_n2230 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$16053$new_n2018 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[0] $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] $abc$16053$new_n2231 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[1] pcpi_rs1[4] $abc$16053$new_n2232 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[30] reg_out[30] reg_next_pc[30] mem_la_addr[30] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[30] mem_addr[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14983 +001 1 +011 1 +110 1 +111 1 +.names trap mem_la_read mem_la_write $abc$16053$new_n2235 +001 1 +010 1 +011 1 +.names resetn $abc$16053$new_n1469 mem_la_read +11 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[29] reg_out[29] reg_next_pc[29] mem_la_addr[29] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[29] mem_addr[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14985 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[28] reg_out[28] reg_next_pc[28] mem_la_addr[28] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[28] mem_addr[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14987 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[27] reg_out[27] reg_next_pc[27] mem_la_addr[27] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[27] mem_addr[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14989 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[26] reg_out[26] reg_next_pc[26] mem_la_addr[26] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[26] mem_addr[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14991 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[25] reg_out[25] reg_next_pc[25] mem_la_addr[25] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[25] mem_addr[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14993 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[24] reg_out[24] reg_next_pc[24] mem_la_addr[24] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[24] mem_addr[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14995 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[23] reg_out[23] reg_next_pc[23] mem_la_addr[23] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[23] mem_addr[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14997 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[22] reg_out[22] reg_next_pc[22] mem_la_addr[22] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[22] mem_addr[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14999 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[21] reg_out[21] reg_next_pc[21] mem_la_addr[21] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[21] mem_addr[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$15001 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[20] reg_out[20] reg_next_pc[20] mem_la_addr[20] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[20] mem_addr[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$15003 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[19] reg_out[19] reg_next_pc[19] mem_la_addr[19] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[19] mem_addr[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$15005 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[18] reg_out[18] reg_next_pc[18] mem_la_addr[18] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[18] mem_addr[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$15007 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[17] reg_out[17] reg_next_pc[17] mem_la_addr[17] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[17] mem_addr[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$15009 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[16] reg_out[16] reg_next_pc[16] mem_la_addr[16] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[16] mem_addr[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$15011 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[15] reg_out[15] reg_next_pc[15] mem_la_addr[15] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[15] mem_addr[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$15013 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[14] reg_out[14] reg_next_pc[14] mem_la_addr[14] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[14] mem_addr[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$15015 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[13] reg_out[13] reg_next_pc[13] mem_la_addr[13] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[13] mem_addr[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$15017 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[12] reg_out[12] reg_next_pc[12] mem_la_addr[12] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[12] mem_addr[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$15019 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[11] reg_out[11] reg_next_pc[11] mem_la_addr[11] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[11] mem_addr[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$15021 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[10] reg_out[10] reg_next_pc[10] mem_la_addr[10] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[10] mem_addr[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$15023 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[9] reg_out[9] reg_next_pc[9] mem_la_addr[9] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[9] mem_addr[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$15025 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[8] reg_out[8] reg_next_pc[8] mem_la_addr[8] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[8] mem_addr[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$15027 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[7] reg_out[7] reg_next_pc[7] mem_la_addr[7] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[7] mem_addr[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$15029 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[6] reg_out[6] reg_next_pc[6] mem_la_addr[6] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[6] mem_addr[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$15031 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[5] reg_out[5] reg_next_pc[5] mem_la_addr[5] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[5] mem_addr[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$15033 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[4] reg_out[4] reg_next_pc[4] mem_la_addr[4] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[4] mem_addr[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15035 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[3] reg_out[3] reg_next_pc[3] mem_la_addr[3] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[3] mem_addr[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$15037 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[2] reg_out[2] reg_next_pc[2] mem_la_addr[2] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[2] mem_addr[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15039 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[31] mem_la_wdata[7] pcpi_rs2[15] mem_la_wdata[31] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[31] mem_wdata[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15045 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2235 mem_instr mem_do_wdata $abc$16053$new_n1470 $abc$16053$auto$rtlil.cc:2693:MuxGate$15049 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$16053$new_n1548 is_alu_reg_reg $abc$16053$new_n2299 $abc$16053$new_n2297 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15051 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n2298 mem_rdata_latched[2] mem_rdata_latched[3] $abc$16053$new_n2297 +100 1 +.names mem_rdata_latched[0] mem_rdata_latched[1] $abc$16053$new_n2298 +11 1 +.names mem_rdata_latched[5] mem_rdata_latched[6] $abc$16053$new_n2299 +10 1 +.names $abc$16053$new_n1548 is_alu_reg_imm $abc$16053$new_n2301 $abc$16053$new_n2297 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15053 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names mem_rdata_latched[5] mem_rdata_latched[6] $abc$16053$new_n2301 +00 1 +.names $abc$16053$new_n1479 is_sll_srl_sra $abc$16053$new_n2303 is_alu_reg_reg $abc$16053$auto$rtlil.cc:2693:MuxGate$15055 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n2306 $abc$16053$new_n2304 mem_rdata_q[30] mem_rdata_q[14] $abc$16053$new_n2303 +1100 1 +1101 1 +1111 1 +.names $abc$16053$new_n2305 mem_rdata_q[31] mem_rdata_q[25] mem_rdata_q[26] mem_rdata_q[27] $abc$16053$new_n2304 +10000 1 +.names mem_rdata_q[28] mem_rdata_q[29] $abc$16053$new_n2305 +00 1 +.names mem_rdata_q[12] mem_rdata_q[13] $abc$16053$new_n2306 +10 1 +.names $abc$16053$new_n1548 is_sb_sh_sw $abc$16053$new_n2297 $abc$16053$new_n2299 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15057 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$16053$new_n1479 instr_jalr is_jalr_addi_slti_sltiu_xori_ori_andi is_alu_reg_imm $abc$16053$new_n2306 $abc$16053$auto$rtlil.cc:2693:MuxGate$15059 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1479 is_slli_srli_srai $abc$16053$new_n2303 is_alu_reg_imm $abc$16053$auto$rtlil.cc:2693:MuxGate$15061 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1548 is_lb_lh_lw_lbu_lhu $abc$16053$new_n2297 $abc$16053$new_n2301 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15063 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n2312 decoded_imm[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15065 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1478 $abc$16053$new_n1480 mem_rdata_q[31] decoded_imm_j[31] instr_jal $abc$16053$new_n2312 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n1548 mem_rdata_latched[11] decoded_rd[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15067 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2322 $abc$16053$new_n2315 instr_rdinstrh $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15069 +0010 1 +0110 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2316 mem_rdata_q[21] mem_rdata_q[20] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2315 +11000 1 +.names $abc$16053$new_n2321 $abc$16053$new_n2320 $abc$16053$new_n1479 $abc$16053$new_n2318 $abc$16053$new_n2317 $abc$16053$new_n2316 +11111 1 +.names $abc$16053$new_n2305 mem_rdata_q[30] mem_rdata_q[17] mem_rdata_q[18] mem_rdata_q[19] $abc$16053$new_n2317 +11000 1 +.names mem_rdata_q[31] mem_rdata_q[4] $abc$16053$new_n2319 mem_rdata_q[2] mem_rdata_q[3] $abc$16053$new_n2318 +11100 1 +.names mem_rdata_q[5] mem_rdata_q[6] mem_rdata_q[15] mem_rdata_q[16] $abc$16053$new_n2319 +1100 1 +.names mem_rdata_q[13] mem_rdata_q[12] mem_rdata_q[14] $abc$16053$new_n2320 +100 1 +.names mem_rdata_q[0] mem_rdata_q[1] $abc$16053$new_n2321 +11 1 +.names mem_rdata_q[27] mem_rdata_q[24] mem_rdata_q[25] mem_rdata_q[26] $abc$16053$new_n2322 +1000 1 +.names $abc$16053$new_n2324 $abc$16053$new_n2315 instr_rdinstr $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15071 +0010 1 +0110 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names mem_rdata_q[24] mem_rdata_q[25] mem_rdata_q[26] mem_rdata_q[27] $abc$16053$new_n2324 +0000 1 +.names $abc$16053$new_n2326 instr_rdcycleh $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15073 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2316 $abc$16053$new_n2322 mem_rdata_q[21] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2326 +11000 1 +.names $abc$16053$new_n2328 instr_rdcycle $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15075 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2316 $abc$16053$new_n2324 mem_rdata_q[21] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2328 +11000 1 +.names $abc$16053$new_n1479 instr_srai $abc$16053$new_n2331 is_alu_reg_imm $abc$16053$new_n2330 $abc$16053$auto$rtlil.cc:2693:MuxGate$15077 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names mem_rdata_q[30] $abc$16053$new_n1479 $abc$16053$new_n2304 $abc$16053$new_n2330 +111 1 +.names mem_rdata_q[14] $abc$16053$new_n2306 $abc$16053$new_n2331 +11 1 +.names $abc$16053$new_n1479 instr_srli is_alu_reg_imm $abc$16053$new_n2331 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15079 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n2304 mem_rdata_q[30] $abc$16053$new_n2333 +10 1 +.names $abc$16053$new_n1479 instr_slli is_alu_reg_imm $abc$16053$new_n2335 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15081 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n2306 mem_rdata_q[14] $abc$16053$new_n2335 +10 1 +.names $abc$16053$new_n1479 instr_sw is_sb_sh_sw $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15083 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_sh $abc$16053$new_n2335 is_sb_sh_sw $abc$16053$auto$rtlil.cc:2693:MuxGate$15085 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_sb is_sb_sh_sw $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15087 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2339 +000 1 +.names $abc$16053$new_n1479 instr_lhu $abc$16053$new_n2331 is_lb_lh_lw_lbu_lhu $abc$16053$auto$rtlil.cc:2693:MuxGate$15089 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_lbu is_lb_lh_lw_lbu_lhu $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15091 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[14] mem_rdata_q[12] mem_rdata_q[13] $abc$16053$new_n2342 +100 1 +.names $abc$16053$new_n1479 instr_lw is_lb_lh_lw_lbu_lhu $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15093 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_lh $abc$16053$new_n2335 is_lb_lh_lw_lbu_lhu $abc$16053$auto$rtlil.cc:2693:MuxGate$15095 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_lb is_lb_lh_lw_lbu_lhu $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15097 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1548 instr_jalr $abc$16053$new_n2347 $abc$16053$new_n2349 mem_rdata_latched[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$15099 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$16053$new_n2348 mem_rdata_latched[13] mem_rdata_latched[14] $abc$16053$new_n2347 +100 1 +.names mem_rdata_latched[6] mem_rdata_latched[5] mem_rdata_latched[4] $abc$16053$new_n2348 +110 1 +.names mem_rdata_latched[2] $abc$16053$new_n2298 mem_rdata_latched[3] $abc$16053$new_n2349 +110 1 +.names $abc$16053$new_n1548 instr_jal $abc$16053$new_n2348 $abc$16053$new_n2298 $abc$16053$new_n2351 $abc$16053$auto$rtlil.cc:2693:MuxGate$15101 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names mem_rdata_latched[2] mem_rdata_latched[3] $abc$16053$new_n2351 +11 1 +.names $abc$16053$new_n1548 instr_auipc $abc$16053$new_n2301 $abc$16053$new_n2349 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15103 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1548 instr_lui $abc$16053$new_n2299 $abc$16053$new_n2349 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15105 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[31] decoded_imm[31] $abc$16053$new_n2355 $abc$16053$auto$rtlil.cc:2693:MuxGate$15107 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[31] $abc$16053$new_n2355 +0001 1 +0011 1 +1010 1 +1011 1 +.names pcpi_rs1[29] decoded_imm[29] pcpi_rs1[30] decoded_imm[30] $abc$16053$new_n2002 $abc$16053$new_n2358 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$16053$new_n2362 $abc$16053$new_n2361 $abc$16053$new_n2022 $abc$16053$new_n2032 reg_pc[31] $abc$16053$new_n2360 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[31] $abc$16053$new_n2361 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[30] pcpi_rs1[27] $abc$16053$new_n2362 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2365 pcpi_rs1[30] $abc$16053$new_n2364 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$15111 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[30] decoded_imm[30] pcpi_rs1[29] decoded_imm[29] $abc$16053$new_n2002 $abc$16053$new_n2364 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2366 $abc$16053$new_n2368 $abc$16053$new_n2369 $abc$16053$new_n2365 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2367 $abc$16053$new_n2032 reg_pc[30] $abc$16053$new_n2366 +000 1 +001 1 +010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[30] $abc$16053$new_n2367 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[29] pcpi_rs1[31] $abc$16053$new_n2368 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n2028 $abc$16053$new_n2025 pcpi_rs1[26] $abc$16053$new_n2369 +100 1 +101 1 +110 1 +.names count_instr[63] count_instr[62] $abc$16053$new_n1909 $abc$16053$auto$rtlil.cc:2693:MuxGate$15113 +011 1 +100 1 +101 1 +110 1 +.names $abc$16053$new_n1612 $abc$16053$new_n2372 reg_pc[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15115 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n2373 reg_next_pc[31] $abc$16053$new_n2372 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[31] reg_out[31] $abc$16053$new_n2373 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n2378 reg_next_pc[31] $abc$16053$new_n2375 $abc$16053$new_n2377 $abc$16053$auto$rtlil.cc:2693:MuxGate$15117 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names instr_jal $abc$16053$new_n2376 $abc$16053$new_n1750 decoded_imm_j[30] $abc$16053$new_n1751 $abc$16053$new_n2375 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names decoded_imm_j[31] $abc$16053$new_n2372 $abc$16053$new_n2376 +01 1 +10 1 +.names $abc$16053$new_n2372 instr_jal $abc$16053$new_n1690 $abc$16053$new_n1750 decoder_trigger $abc$16053$new_n2377 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2372 decoder_trigger $abc$16053$new_n2378 +10 1 +.names mem_do_prefetch resetn $abc$16053$new_n2380 $abc$16053$new_n1612 instr_jalr $abc$16053$auto$rtlil.cc:2693:MuxGate$15119 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names decoder_trigger instr_jal $abc$16053$new_n2380 +10 1 +.names $abc$16053$new_n2399 $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$new_n2382 mem_do_rinst $abc$16053$auto$rtlil.cc:2693:MuxGate$15121 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n2022 $abc$16053$new_n1621 mem_do_prefetch $abc$16053$new_n2383 $abc$16053$new_n2398 $abc$16053$new_n2382 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1622 $abc$16053$new_n2384 $abc$16053$new_n2380 $abc$16053$new_n2383 +000 1 +010 1 +110 1 +111 1 +.names $abc$16053$new_n2385 mem_do_prefetch is_lb_lh_lw_lbu_lhu $abc$16053$new_n2398 $abc$16053$new_n2384 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1624 $abc$16053$new_n2394 is_slli_srli_srai $abc$16053$new_n2386 $abc$16053$new_n2385 +1100 1 +.names $abc$16053$new_n2397 $abc$16053$new_n2396 $abc$16053$new_n2387 $0\is_lui_auipc_jal[0:0] $abc$16053$new_n2386 +1110 1 +.names $abc$16053$new_n2394 $abc$16053$new_n2393 $abc$16053$new_n2391 $abc$16053$new_n2389 $abc$16053$new_n2388 $abc$16053$new_n2387 +11111 1 +.names $abc$16053$new_n2025 instr_lb instr_lbu instr_sh instr_sw $abc$16053$new_n2388 +10000 1 +.names $abc$16053$new_n2390 instr_fence instr_xor instr_sub instr_add $abc$16053$new_n2389 +10000 1 +.names instr_xori instr_addi instr_bgeu instr_bltu $abc$16053$new_n2390 +0000 1 +.names $abc$16053$new_n2392 instr_bge instr_blt instr_bne instr_beq $abc$16053$new_n2391 +10000 1 +.names instr_sll instr_jalr instr_sb instr_slli $abc$16053$new_n2392 +0000 1 +.names instr_and instr_or instr_andi instr_ori $abc$16053$new_n2393 +0000 1 +.names instr_rdcycle instr_rdcycleh instr_rdinstr instr_rdinstrh $abc$16053$new_n2394 +0000 1 +.names $abc$16053$new_n1478 instr_jal $0\is_lui_auipc_jal[0:0] +00 1 +01 1 +11 1 +.names instr_sltu instr_slt instr_sltiu instr_slti $abc$16053$new_n2396 +0000 1 +.names instr_lh instr_lw instr_lhu $abc$16053$new_n2397 +000 1 +.names is_sll_srl_sra mem_do_rinst mem_do_prefetch is_sb_sh_sw $abc$16053$new_n2398 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2038 $abc$16053$new_n1621 $abc$16053$new_n2400 $abc$16053$new_n2022 $abc$16053$new_n2399 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$16053$new_n1622 $abc$16053$new_n1624 $abc$16053$new_n2385 resetn $abc$16053$new_n1612 $abc$16053$new_n2400 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names resetn $abc$16053$new_n1549 $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] +00 1 +01 1 +10 1 +.names mem_do_rdata $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15123 +10 1 +.names mem_do_wdata $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15125 +10 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2452 $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2405 $abc$16053$auto$rtlil.cc:2693:MuxGate$15127 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2450 instr_bgeu $abc$16053$new_n2406 is_sltiu_bltu_sltu is_slti_blt_slt $abc$16053$new_n2405 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instr_bge instr_bne $abc$16053$new_n2448 $abc$16053$new_n2407 $abc$16053$new_n2406 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$16053$new_n2408 pcpi_rs1[31] pcpi_rs2[31] $abc$16053$new_n2407 +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$16053$new_n2444 $abc$16053$new_n2929 $abc$16053$new_n2440 $abc$16053$new_n2408 +000 1 +001 1 +010 1 +.names pcpi_rs1[14] pcpi_rs2[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2416 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2424 $abc$16053$new_n2416 $abc$16053$new_n2423 $abc$16053$new_n2422 $abc$16053$new_n2419 $abc$16053$new_n2418 +11111 1 +.names $abc$16053$new_n2420 pcpi_rs1[2] mem_la_wdata[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2419 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$16053$new_n2421 pcpi_rs1[4] mem_la_wdata[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2420 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[6] mem_la_wdata[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2421 +0000 1 +0011 1 +1100 1 +1111 1 +.names pcpi_rs1[12] pcpi_rs2[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2422 +0000 1 +0011 1 +1100 1 +1111 1 +.names pcpi_rs1[10] pcpi_rs2[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2423 +0000 1 +0011 1 +1100 1 +1111 1 +.names pcpi_rs1[8] pcpi_rs2[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2424 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2438 $abc$16053$new_n2436 $abc$16053$new_n2435 +11 1 +.names $abc$16053$new_n2437 pcpi_rs1[22] pcpi_rs2[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2436 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[20] pcpi_rs2[20] pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2437 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2439 pcpi_rs1[16] pcpi_rs2[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2438 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[18] pcpi_rs2[18] pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2439 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2441 pcpi_rs1[31] pcpi_rs2[31] pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2440 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[28] pcpi_rs2[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2441 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2443 pcpi_rs1[24] pcpi_rs2[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2442 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[26] pcpi_rs2[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2443 +0000 1 +0011 1 +1100 1 +1111 1 +.names pcpi_rs1[31] pcpi_rs2[31] pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2445 $abc$16053$new_n2444 +00001 1 +00010 1 +00011 1 +00111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pcpi_rs2[28] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2445 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$16053$new_n2440 $abc$16053$new_n2449 $abc$16053$new_n2435 $abc$16053$new_n2418 $abc$16053$new_n2448 +1111 1 +.names $abc$16053$new_n2442 pcpi_rs1[0] mem_la_wdata[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2449 +10000 1 +10011 1 +11100 1 +11111 1 +.names is_sltiu_bltu_sltu is_slti_blt_slt $abc$16053$new_n2451 $abc$16053$new_n2407 instr_bgeu $abc$16053$new_n2450 +00001 1 +00011 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2408 pcpi_rs2[31] pcpi_rs1[31] $abc$16053$new_n2451 +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$16053$new_n1622 latched_store $abc$16053$new_n2453 $abc$16053$new_n2394 $abc$16053$new_n1612 $abc$16053$new_n2452 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2454 $abc$16053$new_n1610 $abc$16053$new_n2453 +10 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2021 $abc$16053$new_n2454 +00 1 +.names $abc$16053$new_n1612 latched_stalu $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$auto$rtlil.cc:2693:MuxGate$15129 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$16053$new_n1610 $abc$16053$new_n1612 $abc$16053$new_n2458 $abc$16053$new_n2457 latched_branch $abc$16053$auto$rtlil.cc:2693:MuxGate$15131 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2405 $abc$16053$new_n2457 +10 1 +.names $abc$16053$new_n1610 instr_jalr is_beq_bne_blt_bge_bltu_bgeu decoder_trigger instr_jal $abc$16053$new_n2458 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2460 instr_lh latched_is_lh $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$15133 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2021 mem_do_rdata $abc$16053$new_n2035 $abc$16053$new_n2460 +100 1 +.names $abc$16053$new_n2460 instr_lb latched_is_lb $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$15135 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1479 instr_beq is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15137 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_bne is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2335 $abc$16053$auto$rtlil.cc:2693:MuxGate$15139 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_blt is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15141 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_bge is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2331 $abc$16053$auto$rtlil.cc:2693:MuxGate$15143 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_bltu is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2467 $abc$16053$auto$rtlil.cc:2693:MuxGate$15145 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[14] mem_rdata_q[13] mem_rdata_q[12] $abc$16053$new_n2467 +110 1 +.names $abc$16053$new_n1479 instr_bgeu is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15147 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2469 +111 1 +.names $abc$16053$new_n1479 instr_addi is_alu_reg_imm $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15149 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_slti is_alu_reg_imm $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15151 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_sltiu is_alu_reg_imm $abc$16053$new_n2473 $abc$16053$auto$rtlil.cc:2693:MuxGate$15153 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2473 +110 1 +.names $abc$16053$new_n1479 instr_xori is_alu_reg_imm $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15155 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_ori is_alu_reg_imm $abc$16053$new_n2467 $abc$16053$auto$rtlil.cc:2693:MuxGate$15157 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_andi is_alu_reg_imm $abc$16053$new_n2469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15159 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_add is_alu_reg_reg $abc$16053$new_n2339 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15161 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_sub $abc$16053$new_n2330 is_alu_reg_reg $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15163 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_sll is_alu_reg_reg $abc$16053$new_n2335 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15165 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_slt is_alu_reg_reg $abc$16053$new_n2320 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15167 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_sltu is_alu_reg_reg $abc$16053$new_n2473 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15169 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_xor is_alu_reg_reg $abc$16053$new_n2342 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15171 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_srl is_alu_reg_reg $abc$16053$new_n2331 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15173 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_sra $abc$16053$new_n2331 is_alu_reg_reg $abc$16053$new_n2330 $abc$16053$auto$rtlil.cc:2693:MuxGate$15175 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_or is_alu_reg_reg $abc$16053$new_n2467 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15177 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_and is_alu_reg_reg $abc$16053$new_n2469 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15179 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_fence $abc$16053$new_n2339 $abc$16053$new_n2321 $abc$16053$new_n2488 $abc$16053$auto$rtlil.cc:2693:MuxGate$15181 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names mem_rdata_q[2] mem_rdata_q[3] mem_rdata_q[4] mem_rdata_q[5] mem_rdata_q[6] $abc$16053$new_n2488 +11000 1 +.names $abc$16053$new_n1548 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2348 $abc$16053$new_n2297 $abc$16053$auto$rtlil.cc:2693:MuxGate$15183 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15185 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2235 mem_valid $abc$16053$new_n2492 $abc$16053$new_n1468 $abc$16053$auto$rtlil.cc:2693:MuxGate$15189 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1473 $abc$16053$new_n1474 resetn mem_ready $abc$16053$new_n2492 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$16053$new_n1467 $abc$16053$new_n1475 mem_state[1] mem_state[0] mem_do_wdata $abc$16053$auto$rtlil.cc:2693:MuxGate$15193 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2495 $abc$16053$new_n2498 mem_wordsize[1] $abc$16053$new_n2397 $abc$16053$new_n2021 $abc$16053$auto$rtlil.cc:2693:MuxGate$15197 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2501 $abc$16053$new_n2034 $abc$16053$new_n2496 $abc$16053$new_n2495 +111 1 +.names $abc$16053$new_n2498 instr_sb $abc$16053$new_n2500 $abc$16053$new_n2460 $abc$16053$new_n2496 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names mem_do_wdata $abc$16053$new_n2035 $abc$16053$new_n2497 +00 1 +.names $abc$16053$new_n2499 instr_sh $abc$16053$new_n2498 +10 1 +.names $abc$16053$new_n2020 instr_sw $abc$16053$new_n2499 +10 1 +.names $abc$16053$new_n2397 instr_lb instr_lbu $abc$16053$new_n2500 +100 1 +.names resetn $abc$16053$new_n1612 $abc$16053$new_n2019 $abc$16053$new_n2035 $abc$16053$new_n2501 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1609 latched_rd[4] $abc$16053$new_n1612 decoded_rd[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15201 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[31] reg_out[31] reg_next_pc[31] mem_la_addr[31] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[31] mem_addr[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15203 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2495 $abc$16053$new_n2506 mem_wordsize[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$15207 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2499 instr_sh $abc$16053$new_n2021 instr_lw $abc$16053$new_n2397 $abc$16053$new_n2506 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n2235 mem_wstrb[2] mem_la_wstrb[2] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14331 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names mem_wordsize[1] mem_wordsize[0] pcpi_rs1[1] pcpi_rs1[0] mem_la_wstrb[2] +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2235 mem_wstrb[1] mem_la_wstrb[1] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14333 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$16053$new_n2512 pcpi_rs1[0] pcpi_rs1[1] mem_la_wstrb[1] +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2513 $abc$16053$new_n1442 $abc$16053$new_n2512 +00 1 +.names mem_wordsize[0] pcpi_rs1[1] mem_wordsize[1] $abc$16053$new_n2513 +110 1 +.names $abc$16053$new_n2235 mem_wstrb[0] mem_la_wstrb[0] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14335 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$16053$new_n2512 pcpi_rs1[0] pcpi_rs1[1] mem_la_wstrb[0] +000 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2235 mem_wstrb[3] mem_la_wstrb[3] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15043 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names mem_wordsize[1] mem_wordsize[0] pcpi_rs1[1] pcpi_rs1[0] mem_la_wstrb[3] +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instr_slt instr_slti instr_blt $0\is_slti_blt_slt[0:0] +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names instr_sltu instr_sltiu instr_bltu $0\is_sltiu_bltu_sltu[0:0] +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2396 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$reduce_or$./benchmark/picorv32.v:863$175_Y +00 1 +01 1 +11 1 +.names resetn $abc$16053$new_n2019 $abc$16053$new_n2035 $abc$16053$auto$opt_dff.cc:253:combine_resets$4218 +100 1 +.names cpu_state[7] $abc$16053$new_n1613 cpu_state[6] cpu_state[4] cpu_state[5] $abc$16053$procmux$1608_CMP +11000 1 +.names resetn $abc$16053$new_n1479 $abc$16053$auto$opt_dff.cc:253:combine_resets$4160 +00 1 +01 1 +11 1 +.names resetn $abc$16053$new_n1612 $abc$16053$new_n2527 latched_store latched_branch $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] +11001 1 +11010 1 +11011 1 +.names latched_rd[4] latched_rd[0] latched_rd[1] latched_rd[2] latched_rd[3] $abc$16053$new_n2527 +00000 1 +.names mem_do_prefetch $abc$16053$new_n1549 $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y +00 1 +.names resetn mem_do_rinst reg_pc[1] reg_pc[0] $abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2022 reg_sh[0] $abc$16053$new_n2027 $abc$16053$new_n2531 $0\reg_sh[4:0][0] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$16053$new_n2532 decoded_rs2[0] $abc$16053$new_n1686 $abc$16053$new_n2531 +000 1 +010 1 +100 1 +101 1 +.names is_slli_srli_srai $abc$16053$new_n1621 $abc$16053$new_n2532 +10 1 +.names $abc$16053$new_n2022 reg_sh[1] $abc$16053$new_n2027 reg_sh[0] $abc$16053$new_n2534 $0\reg_sh[4:0][1] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2532 decoded_rs2[1] $abc$16053$new_n1684 $abc$16053$new_n2534 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2536 $abc$16053$new_n2038 reg_sh[2] $abc$16053$new_n2027 $0\reg_sh[4:0][2] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[2] $abc$16053$new_n1682 $abc$16053$new_n2536 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$16053$new_n2538 reg_sh[3] reg_sh[2] $abc$16053$new_n2038 reg_sh[4] $0\reg_sh[4:0][3] +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[3] $abc$16053$new_n1680 $abc$16053$new_n2538 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$16053$new_n2540 reg_sh[4] $abc$16053$new_n2038 reg_sh[2] reg_sh[3] $0\reg_sh[4:0][4] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[4] $abc$16053$new_n1678 $abc$16053$new_n2540 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2542 $abc$16053$new_n2546 pcpi_rs1[0] $0\reg_out[31:0][0] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2543 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[16] mem_rdata[0] $abc$16053$new_n2542 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2544 mem_rdata[0] mem_la_wstrb[0] mem_rdata[24] $abc$16053$new_n2545 $abc$16053$new_n2543 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names pcpi_rs1[1] mem_rdata[16] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[8] $abc$16053$new_n2544 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names pcpi_rs1[0] pcpi_rs1[1] $abc$16053$new_n2545 +11 1 +.names $abc$16053$new_n1610 reg_pc[0] decoded_imm[0] $abc$16053$new_n2547 $abc$16053$new_n2546 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names instr_rdinstrh instr_rdinstr count_instr[32] $abc$16053$new_n2548 count_instr[0] $abc$16053$new_n2547 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdcycleh count_cycle[32] count_cycle[0] $abc$16053$new_n2548 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1610 reg_pc[1] decoded_imm[1] $abc$16053$new_n2556 $abc$16053$new_n2554 $abc$16053$new_n2553 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instr_rdinstrh instr_rdinstr count_instr[33] $abc$16053$new_n2555 count_instr[1] $abc$16053$new_n2554 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[33] count_cycle[1] $abc$16053$new_n2555 +000 1 +010 1 +100 1 +101 1 +.names reg_pc[0] decoded_imm[0] $abc$16053$new_n2556 +11 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2559 $abc$16053$new_n2562 pcpi_rs1[2] $0\reg_out[31:0][2] +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2560 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[18] mem_rdata[2] $abc$16053$new_n2559 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2561 mem_rdata[2] mem_la_wstrb[0] mem_rdata[26] $abc$16053$new_n2545 $abc$16053$new_n2560 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names pcpi_rs1[1] mem_rdata[18] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[10] $abc$16053$new_n2561 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n1610 reg_pc[2] decoded_imm[2] $abc$16053$new_n2565 $abc$16053$new_n2563 $abc$16053$new_n2562 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names instr_rdinstrh instr_rdinstr count_instr[34] $abc$16053$new_n2564 count_instr[2] $abc$16053$new_n2563 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[34] count_cycle[2] $abc$16053$new_n2564 +000 1 +010 1 +100 1 +101 1 +.names reg_pc[0] decoded_imm[0] reg_pc[1] decoded_imm[1] $abc$16053$new_n2565 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$16053$new_n2568 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[19] mem_rdata[3] $abc$16053$new_n2567 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2569 mem_rdata[3] mem_la_wstrb[0] mem_rdata[27] $abc$16053$new_n2545 $abc$16053$new_n2568 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names pcpi_rs1[1] mem_rdata[19] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[11] $abc$16053$new_n2569 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names reg_pc[3] decoded_imm[3] reg_pc[2] decoded_imm[2] $abc$16053$new_n2565 $abc$16053$new_n2571 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2575 $abc$16053$new_n2578 $abc$16053$new_n2512 mem_rdata[4] $0\reg_out[31:0][4] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n2576 $abc$16053$new_n2513 mem_rdata[20] $abc$16053$new_n2575 +000 1 +001 1 +011 1 +.names $abc$16053$new_n2577 mem_rdata[4] mem_la_wstrb[0] mem_rdata[28] $abc$16053$new_n2545 $abc$16053$new_n2576 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names pcpi_rs1[1] mem_rdata[20] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[12] $abc$16053$new_n2577 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n1610 pcpi_rs1[4] $abc$16053$new_n2579 $abc$16053$new_n2581 $abc$16053$new_n2578 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names reg_pc[4] decoded_imm[4] $abc$16053$new_n2580 $abc$16053$new_n2579 +000 1 +011 1 +101 1 +110 1 +.names reg_pc[2] decoded_imm[2] reg_pc[3] decoded_imm[3] $abc$16053$new_n2565 $abc$16053$new_n2580 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[36] $abc$16053$new_n2582 count_instr[4] $abc$16053$new_n2581 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[36] count_cycle[4] $abc$16053$new_n2582 +000 1 +010 1 +100 1 +101 1 +.names reg_pc[5] decoded_imm[5] reg_pc[4] decoded_imm[4] $abc$16053$new_n2580 $abc$16053$new_n2585 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names pcpi_rs1[0] pcpi_rs1[1] mem_rdata[29] mem_rdata[13] $abc$16053$new_n2590 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n1610 reg_pc[6] decoded_imm[6] $abc$16053$new_n2600 $abc$16053$new_n2593 $0\reg_out[31:0][6] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2594 $abc$16053$new_n2598 $abc$16053$new_n2453 $abc$16053$new_n2022 pcpi_rs1[6] $abc$16053$new_n2593 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$16053$new_n2595 mem_la_wstrb[0] $abc$16053$new_n2596 mem_rdata[6] $abc$16053$new_n2594 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2513 mem_rdata[22] $abc$16053$new_n2595 +100 1 +101 1 +111 1 +.names $abc$16053$new_n2597 $abc$16053$new_n2545 mem_rdata[30] $abc$16053$new_n2596 +100 1 +101 1 +110 1 +.names pcpi_rs1[1] mem_rdata[22] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[14] $abc$16053$new_n2597 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names instr_rdinstrh instr_rdinstr count_instr[38] $abc$16053$new_n2599 count_instr[6] $abc$16053$new_n2598 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdcycleh count_cycle[38] count_cycle[6] $abc$16053$new_n2599 +001 1 +011 1 +110 1 +111 1 +.names reg_pc[4] decoded_imm[4] reg_pc[5] decoded_imm[5] $abc$16053$new_n2580 $abc$16053$new_n2600 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2021 $abc$16053$new_n2606 pcpi_rs1[7] $abc$16053$new_n2602 $0\reg_out[31:0][7] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n1610 reg_pc[7] decoded_imm[7] $abc$16053$new_n2603 $abc$16053$new_n2604 $abc$16053$new_n2602 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[6] decoded_imm[6] $abc$16053$new_n2600 $abc$16053$new_n2603 +000 1 +001 1 +011 1 +101 1 +.names instr_rdinstrh instr_rdinstr count_instr[39] $abc$16053$new_n2605 count_instr[7] $abc$16053$new_n2604 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[39] count_cycle[7] $abc$16053$new_n2605 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1442 $abc$16053$new_n2513 $abc$16053$new_n2607 mem_rdata[23] mem_rdata[7] $abc$16053$new_n2606 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2608 pcpi_rs1[1] pcpi_rs1[0] mem_rdata[15] mem_rdata[31] $abc$16053$new_n2607 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names pcpi_rs1[1] pcpi_rs1[0] mem_rdata[23] mem_rdata[7] $abc$16053$new_n2608 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2613 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[8] $abc$16053$new_n2611 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2606 latched_is_lb $abc$16053$new_n2612 +100 1 +110 1 +111 1 +.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[24] mem_rdata[8] $abc$16053$new_n2613 +1001 1 +1011 1 +1110 1 +1111 1 +.names latched_is_lb $abc$16053$new_n1442 $abc$16053$new_n2614 +00 1 +.names reg_pc[7] decoded_imm[7] $abc$16053$new_n2603 $abc$16053$new_n2617 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2623 $abc$16053$new_n2619 $abc$16053$new_n2021 pcpi_rs1[9] $0\reg_out[31:0][9] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[9] decoded_imm[9] $abc$16053$new_n2620 $abc$16053$new_n2621 $abc$16053$new_n2619 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[7] decoded_imm[7] reg_pc[8] decoded_imm[8] $abc$16053$new_n2603 $abc$16053$new_n2620 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[41] $abc$16053$new_n2622 count_instr[9] $abc$16053$new_n2621 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdcycleh count_cycle[41] count_cycle[9] $abc$16053$new_n2622 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[25] mem_rdata[9] $abc$16053$new_n2623 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n2626 $abc$16053$new_n1610 $abc$16053$new_n2625 $abc$16053$new_n2453 $abc$16053$new_n2628 $0\reg_out[31:0][10] +00010 1 +00110 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[10] decoded_imm[10] reg_pc[9] decoded_imm[9] $abc$16053$new_n2620 $abc$16053$new_n2625 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2627 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[10] $abc$16053$new_n2626 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[26] mem_rdata[10] $abc$16053$new_n2627 +1001 1 +1011 1 +1110 1 +1111 1 +.names instr_rdinstrh instr_rdinstr count_instr[42] $abc$16053$new_n2629 count_instr[10] $abc$16053$new_n2628 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[42] count_cycle[10] $abc$16053$new_n2629 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2635 $abc$16053$new_n2021 $abc$16053$new_n2631 pcpi_rs1[11] $0\reg_out[31:0][11] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[11] decoded_imm[11] $abc$16053$new_n2632 $abc$16053$new_n2633 $abc$16053$new_n2631 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[9] decoded_imm[9] reg_pc[10] decoded_imm[10] $abc$16053$new_n2620 $abc$16053$new_n2632 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[43] $abc$16053$new_n2634 count_instr[11] $abc$16053$new_n2633 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdcycleh count_cycle[43] count_cycle[11] $abc$16053$new_n2634 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[27] mem_rdata[11] $abc$16053$new_n2635 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n2638 $abc$16053$new_n1610 $abc$16053$new_n2637 $abc$16053$new_n2453 $abc$16053$new_n2640 $0\reg_out[31:0][12] +00010 1 +00110 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[12] decoded_imm[12] reg_pc[11] decoded_imm[11] $abc$16053$new_n2632 $abc$16053$new_n2637 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2639 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[12] $abc$16053$new_n2638 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[28] mem_rdata[12] $abc$16053$new_n2639 +1001 1 +1011 1 +1110 1 +1111 1 +.names instr_rdinstrh instr_rdinstr count_instr[44] $abc$16053$new_n2641 count_instr[12] $abc$16053$new_n2640 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[44] count_cycle[12] $abc$16053$new_n2641 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2647 $abc$16053$new_n2021 $abc$16053$new_n2643 pcpi_rs1[13] $0\reg_out[31:0][13] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[13] decoded_imm[13] $abc$16053$new_n2644 $abc$16053$new_n2645 $abc$16053$new_n2643 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[11] decoded_imm[11] reg_pc[12] decoded_imm[12] $abc$16053$new_n2632 $abc$16053$new_n2644 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[45] $abc$16053$new_n2646 count_instr[13] $abc$16053$new_n2645 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[45] count_cycle[13] $abc$16053$new_n2646 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[29] mem_rdata[13] $abc$16053$new_n2647 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n1610 $abc$16053$new_n2650 $abc$16053$new_n2649 $abc$16053$new_n2454 $abc$16053$new_n2652 $0\reg_out[31:0][14] +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[14] decoded_imm[14] reg_pc[13] decoded_imm[13] $abc$16053$new_n2644 $abc$16053$new_n2649 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2651 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[14] $abc$16053$new_n2650 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[30] mem_rdata[14] $abc$16053$new_n2651 +1001 1 +1011 1 +1110 1 +1111 1 +.names instr_rdinstrh instr_rdinstr count_instr[46] $abc$16053$new_n2653 count_instr[14] $abc$16053$new_n2652 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[46] count_cycle[14] $abc$16053$new_n2653 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2659 $abc$16053$new_n2021 $abc$16053$new_n2655 pcpi_rs1[15] $0\reg_out[31:0][15] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[15] decoded_imm[15] $abc$16053$new_n2656 $abc$16053$new_n2657 $abc$16053$new_n2655 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[13] decoded_imm[13] reg_pc[14] decoded_imm[14] $abc$16053$new_n2644 $abc$16053$new_n2656 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[47] $abc$16053$new_n2658 count_instr[15] $abc$16053$new_n2657 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[47] count_cycle[15] $abc$16053$new_n2658 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2660 latched_is_lb $abc$16053$new_n2659 +100 1 +101 1 +111 1 +.names $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[31] mem_rdata[15] $abc$16053$new_n2660 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n2663 $abc$16053$new_n1610 $abc$16053$new_n2662 $abc$16053$new_n2453 $abc$16053$new_n2667 $0\reg_out[31:0][16] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[16] decoded_imm[16] reg_pc[15] decoded_imm[15] $abc$16053$new_n2656 $abc$16053$new_n2662 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2664 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[16] $abc$16053$new_n2663 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[16] $abc$16053$new_n2666 $abc$16053$new_n2664 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names latched_is_lh $abc$16053$new_n2660 $abc$16053$new_n2665 +11 1 +.names $abc$16053$new_n1425 latched_is_lh $abc$16053$new_n2666 +10 1 +.names instr_rdinstrh $abc$16053$new_n2668 count_instr[48] count_instr[16] instr_rdinstr $abc$16053$new_n2667 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[48] count_cycle[16] $abc$16053$new_n2668 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2674 $abc$16053$new_n2670 $abc$16053$new_n2021 pcpi_rs1[17] $0\reg_out[31:0][17] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[17] decoded_imm[17] $abc$16053$new_n2671 $abc$16053$new_n2672 $abc$16053$new_n2670 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[15] decoded_imm[15] reg_pc[16] decoded_imm[16] $abc$16053$new_n2656 $abc$16053$new_n2671 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[49] $abc$16053$new_n2673 count_instr[17] $abc$16053$new_n2672 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[49] count_cycle[17] $abc$16053$new_n2673 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[17] $abc$16053$new_n2674 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2677 $abc$16053$new_n1610 $abc$16053$new_n2676 $abc$16053$new_n2453 $abc$16053$new_n2679 $0\reg_out[31:0][18] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[18] decoded_imm[18] reg_pc[17] decoded_imm[17] $abc$16053$new_n2671 $abc$16053$new_n2676 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2678 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[18] $abc$16053$new_n2677 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[18] $abc$16053$new_n2666 $abc$16053$new_n2678 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2680 count_instr[50] count_instr[18] instr_rdinstr $abc$16053$new_n2679 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[50] count_cycle[18] $abc$16053$new_n2680 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2686 $abc$16053$new_n2021 $abc$16053$new_n2682 pcpi_rs1[19] $0\reg_out[31:0][19] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[19] decoded_imm[19] $abc$16053$new_n2683 $abc$16053$new_n2684 $abc$16053$new_n2682 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[17] decoded_imm[17] reg_pc[18] decoded_imm[18] $abc$16053$new_n2671 $abc$16053$new_n2683 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[51] $abc$16053$new_n2685 count_instr[19] $abc$16053$new_n2684 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[51] count_cycle[19] $abc$16053$new_n2685 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[19] $abc$16053$new_n2686 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[19] decoded_imm[19] $abc$16053$new_n2683 $abc$16053$new_n2688 +010 1 +100 1 +110 1 +111 1 +.names $abc$16053$new_n2691 $abc$16053$new_n2021 pcpi_rs1[20] $abc$16053$new_n2022 $abc$16053$new_n2690 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[20] $abc$16053$new_n2691 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2699 $abc$16053$new_n2021 $abc$16053$new_n2695 pcpi_rs1[21] $0\reg_out[31:0][21] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[21] decoded_imm[21] $abc$16053$new_n2696 $abc$16053$new_n2697 $abc$16053$new_n2695 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[19] decoded_imm[19] reg_pc[20] decoded_imm[20] $abc$16053$new_n2683 $abc$16053$new_n2696 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[53] $abc$16053$new_n2698 count_instr[21] $abc$16053$new_n2697 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[53] count_cycle[21] $abc$16053$new_n2698 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[21] $abc$16053$new_n2699 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2702 $abc$16053$new_n1610 $abc$16053$new_n2701 $abc$16053$new_n2453 $abc$16053$new_n2704 $0\reg_out[31:0][22] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[22] decoded_imm[22] reg_pc[21] decoded_imm[21] $abc$16053$new_n2696 $abc$16053$new_n2701 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2703 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[22] $abc$16053$new_n2702 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[22] $abc$16053$new_n2666 $abc$16053$new_n2703 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2705 count_instr[54] count_instr[22] instr_rdinstr $abc$16053$new_n2704 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[54] count_cycle[22] $abc$16053$new_n2705 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2711 $abc$16053$new_n2707 $abc$16053$new_n2021 pcpi_rs1[23] $0\reg_out[31:0][23] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[23] decoded_imm[23] $abc$16053$new_n2708 $abc$16053$new_n2709 $abc$16053$new_n2707 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[21] decoded_imm[21] reg_pc[22] decoded_imm[22] $abc$16053$new_n2696 $abc$16053$new_n2708 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[55] $abc$16053$new_n2710 count_instr[23] $abc$16053$new_n2709 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[55] count_cycle[23] $abc$16053$new_n2710 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[23] $abc$16053$new_n2711 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2714 $abc$16053$new_n1610 $abc$16053$new_n2713 $abc$16053$new_n2453 $abc$16053$new_n2716 $0\reg_out[31:0][24] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[24] decoded_imm[24] reg_pc[23] decoded_imm[23] $abc$16053$new_n2708 $abc$16053$new_n2713 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2715 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[24] $abc$16053$new_n2714 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[24] $abc$16053$new_n2666 $abc$16053$new_n2715 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2717 count_instr[56] count_instr[24] instr_rdinstr $abc$16053$new_n2716 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[56] count_cycle[24] $abc$16053$new_n2717 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2723 $abc$16053$new_n2719 $abc$16053$new_n2021 pcpi_rs1[25] $0\reg_out[31:0][25] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[25] decoded_imm[25] $abc$16053$new_n2720 $abc$16053$new_n2721 $abc$16053$new_n2719 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[23] decoded_imm[23] reg_pc[24] decoded_imm[24] $abc$16053$new_n2708 $abc$16053$new_n2720 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[57] $abc$16053$new_n2722 count_instr[25] $abc$16053$new_n2721 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[57] count_cycle[25] $abc$16053$new_n2722 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[25] $abc$16053$new_n2723 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2726 $abc$16053$new_n1610 $abc$16053$new_n2725 $abc$16053$new_n2453 $abc$16053$new_n2728 $0\reg_out[31:0][26] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[26] decoded_imm[26] reg_pc[25] decoded_imm[25] $abc$16053$new_n2720 $abc$16053$new_n2725 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2727 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[26] $abc$16053$new_n2726 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[26] $abc$16053$new_n2666 $abc$16053$new_n2727 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2729 count_instr[58] count_instr[26] instr_rdinstr $abc$16053$new_n2728 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[58] count_cycle[26] $abc$16053$new_n2729 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2735 $abc$16053$new_n2731 $abc$16053$new_n2021 pcpi_rs1[27] $0\reg_out[31:0][27] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[27] decoded_imm[27] $abc$16053$new_n2732 $abc$16053$new_n2733 $abc$16053$new_n2731 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[25] decoded_imm[25] reg_pc[26] decoded_imm[26] $abc$16053$new_n2720 $abc$16053$new_n2732 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[59] $abc$16053$new_n2734 count_instr[27] $abc$16053$new_n2733 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[59] count_cycle[27] $abc$16053$new_n2734 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[27] $abc$16053$new_n2735 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2738 $abc$16053$new_n1610 $abc$16053$new_n2737 $abc$16053$new_n2453 $abc$16053$new_n2740 $0\reg_out[31:0][28] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[28] decoded_imm[28] reg_pc[27] decoded_imm[27] $abc$16053$new_n2732 $abc$16053$new_n2737 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2739 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[28] $abc$16053$new_n2738 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[28] $abc$16053$new_n2666 $abc$16053$new_n2739 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2741 count_instr[60] count_instr[28] instr_rdinstr $abc$16053$new_n2740 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[60] count_cycle[28] $abc$16053$new_n2741 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2745 $abc$16053$new_n2743 $abc$16053$new_n2453 $abc$16053$new_n2747 $0\reg_out[31:0][29] +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1610 reg_pc[29] decoded_imm[29] $abc$16053$new_n2744 $abc$16053$new_n2743 +1000 1 +1011 1 +1101 1 +1110 1 +.names reg_pc[27] decoded_imm[27] reg_pc[28] decoded_imm[28] $abc$16053$new_n2732 $abc$16053$new_n2744 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2746 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[29] $abc$16053$new_n2745 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[29] $abc$16053$new_n2666 $abc$16053$new_n2746 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2748 count_instr[61] count_instr[29] instr_rdinstr $abc$16053$new_n2747 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[61] count_cycle[29] $abc$16053$new_n2748 +00000 1 +00010 1 +10000 1 +10001 1 +.names reg_pc[29] decoded_imm[29] $abc$16053$new_n2744 $abc$16053$new_n2750 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2753 $abc$16053$new_n2021 pcpi_rs1[30] $abc$16053$new_n2022 $abc$16053$new_n2752 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[30] $abc$16053$new_n2753 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2761 $abc$16053$new_n2021 $abc$16053$new_n2757 pcpi_rs1[31] $0\reg_out[31:0][31] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[31] decoded_imm[31] $abc$16053$new_n2758 $abc$16053$new_n2759 $abc$16053$new_n2757 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[29] decoded_imm[29] reg_pc[30] decoded_imm[30] $abc$16053$new_n2744 $abc$16053$new_n2758 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[63] $abc$16053$new_n2760 count_instr[31] $abc$16053$new_n2759 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[63] count_cycle[31] $abc$16053$new_n2760 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[31] $abc$16053$new_n2761 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2453 $abc$16053$new_n2497 $abc$16053$new_n2763 $abc$16053$procmux$1608_CMP $abc$16053$new_n1612 $0\set_mem_do_wdata[0:0] +11100 1 +.names resetn $abc$16053$new_n1620 $abc$16053$new_n2763 +11 1 +.names resetn $abc$16053$new_n2460 $0\set_mem_do_rdata[0:0] +11 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2457 $abc$16053$new_n2763 $abc$16053$procmux$1608_CMP $abc$16053$new_n1612 $0\set_mem_do_rinst[0:0] +11100 1 +.names $abc$16053$new_n2767 $abc$16053$new_n1548 $abc$16053$new_n1610 $abc$16053$new_n2457 $0\decoder_trigger[0:0] +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2019 $abc$16053$new_n2767 +10 1 +.names $abc$16053$new_n2772 $abc$16053$new_n2770 cpu_state[0] $abc$16053$new_n2769 $abc$16053$new_n2771 $abc$16053$procmux$2235_Y[0] +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names is_lb_lh_lw_lbu_lhu $abc$16053$new_n2386 $abc$16053$new_n2769 +10 1 +.names $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2453 $abc$16053$new_n2770 +10 1 +.names $abc$16053$new_n1622 $abc$16053$new_n1624 is_slli_srli_srai $abc$16053$new_n2771 +110 1 +.names resetn $abc$16053$new_n2773 $abc$16053$new_n2772 +10 1 +.names resetn $abc$16053$new_n2774 mem_wordsize[1] $abc$16053$new_n1551 $abc$16053$new_n2773 +1100 1 +.names pcpi_rs1[0] pcpi_rs1[1] mem_wordsize[0] $abc$16053$new_n2774 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2772 $abc$16053$new_n2020 $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2776 $abc$16053$procmux$2235_Y[1] +1000 1 +1010 1 +1100 1 +1101 1 +.names cpu_state[1] is_sb_sh_sw is_sll_srl_sra $abc$16053$new_n1620 $abc$16053$new_n2777 $abc$16053$new_n2776 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n1621 $abc$16053$new_n2385 is_lb_lh_lw_lbu_lhu $abc$16053$new_n2777 +000 1 +001 1 +011 1 +.names $abc$16053$new_n2772 $abc$16053$new_n2779 $abc$16053$new_n2038 cpu_state[2] $abc$16053$new_n2018 $abc$16053$procmux$2235_Y[2] +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1620 is_sll_srl_sra $abc$16053$new_n2777 $abc$16053$new_n1624 $abc$16053$new_n2532 $abc$16053$new_n2779 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +.names $abc$16053$new_n2782 $abc$16053$new_n2781 cpu_state[3] $abc$16053$procmux$2235_Y[3] +101 1 +110 1 +111 1 +.names $abc$16053$new_n1620 $abc$16053$new_n1623 is_sll_srl_sra $abc$16053$new_n2777 is_sb_sh_sw $abc$16053$new_n2781 +00000 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2772 $abc$16053$new_n2018 $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1549 $abc$16053$new_n2782 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names cpu_state[4] $abc$16053$new_n2772 $abc$16053$new_n1620 $abc$16053$procmux$2235_Y[4] +111 1 +.names $abc$16053$new_n1620 $abc$16053$new_n2772 cpu_state[5] $abc$16053$new_n1991 instr_jal $abc$16053$procmux$2235_Y[5] +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names resetn cpu_state[6] $abc$16053$new_n1612 $abc$16053$new_n2380 $abc$16053$new_n2789 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +.names resetn $abc$16053$new_n2773 cpu_state[7] $abc$16053$new_n2771 $abc$16053$new_n2386 $abc$16053$procmux$2235_Y[7] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2792 $abc$16053$new_n2793 pcpi_rs1[0] mem_la_wdata[0] $abc$16053$new_n2794 alu_out[0] +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names is_compare $abc$16053$new_n2393 instr_xor instr_xori $abc$16053$new_n2405 $abc$16053$new_n2792 +11000 1 +.names $abc$16053$new_n2393 pcpi_rs1[0] instr_and instr_andi mem_la_wdata[0] $abc$16053$new_n2793 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names $abc$16053$new_n2393 is_compare instr_xor instr_xori $abc$16053$new_n2794 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2794 pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2797 $abc$16053$new_n2796 alu_out[1] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[1] instr_and instr_andi mem_la_wdata[1] $abc$16053$new_n2796 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names mem_la_wdata[0] instr_sub pcpi_rs1[0] instr_xor instr_xori $abc$16053$new_n2797 +10100 1 +11000 1 +.names $abc$16053$new_n2794 pcpi_rs1[2] mem_la_wdata[2] $abc$16053$new_n2799 $abc$16053$new_n2802 alu_out[2] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2800 $abc$16053$new_n2801 $abc$16053$new_n2799 +00000 1 +00010 1 +10000 1 +10001 1 +.names mem_la_wdata[0] pcpi_rs1[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2800 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names pcpi_rs1[0] mem_la_wdata[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2801 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$16053$new_n2393 pcpi_rs1[2] instr_and instr_andi mem_la_wdata[2] $abc$16053$new_n2802 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2794 $abc$16053$new_n2804 $abc$16053$new_n2806 alu_out[3] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2805 $abc$16053$new_n2804 +000 1 +.names instr_sub pcpi_rs1[2] mem_la_wdata[2] $abc$16053$new_n2801 $abc$16053$new_n2800 $abc$16053$new_n2805 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[3] mem_la_wdata[3] instr_and instr_andi $abc$16053$new_n2806 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[4] mem_la_wdata[4] $abc$16053$new_n2808 $abc$16053$new_n2811 alu_out[4] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2809 $abc$16053$new_n2810 $abc$16053$new_n2808 +00000 1 +00001 1 +10001 1 +10011 1 +.names pcpi_rs1[2] mem_la_wdata[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2801 $abc$16053$new_n2809 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names mem_la_wdata[2] pcpi_rs1[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2800 $abc$16053$new_n2810 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names $abc$16053$new_n2393 pcpi_rs1[4] instr_and instr_andi mem_la_wdata[4] $abc$16053$new_n2811 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2794 $abc$16053$new_n3203 $abc$16053$new_n2816 alu_out[5] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[5] mem_la_wdata[5] instr_and instr_andi $abc$16053$new_n2816 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[6] mem_la_wdata[6] $abc$16053$new_n2818 $abc$16053$new_n2821 alu_out[6] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2819 $abc$16053$new_n2820 $abc$16053$new_n2818 +00000 1 +00001 1 +10001 1 +10011 1 +.names pcpi_rs1[4] mem_la_wdata[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2809 $abc$16053$new_n2819 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names mem_la_wdata[4] pcpi_rs1[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2810 $abc$16053$new_n2820 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[6] instr_and instr_andi mem_la_wdata[6] $abc$16053$new_n2821 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2794 $abc$16053$new_n3205 $abc$16053$new_n2826 alu_out[7] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[7] mem_la_wdata[7] instr_and instr_andi $abc$16053$new_n2826 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[8] pcpi_rs2[8] $abc$16053$new_n2828 $abc$16053$new_n2831 alu_out[8] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2829 $abc$16053$new_n2830 $abc$16053$new_n2828 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[6] mem_la_wdata[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2819 $abc$16053$new_n2829 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names mem_la_wdata[6] pcpi_rs1[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2820 $abc$16053$new_n2830 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[8] instr_and instr_andi pcpi_rs2[8] $abc$16053$new_n2831 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2794 $abc$16053$new_n3207 $abc$16053$new_n2835 alu_out[9] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[9] pcpi_rs2[9] instr_and instr_andi $abc$16053$new_n2835 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[10] pcpi_rs2[10] $abc$16053$new_n2837 $abc$16053$new_n2840 alu_out[10] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2838 $abc$16053$new_n2839 $abc$16053$new_n2837 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[8] pcpi_rs2[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2829 $abc$16053$new_n2838 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[8] pcpi_rs1[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2830 $abc$16053$new_n2839 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[10] instr_and instr_andi pcpi_rs2[10] $abc$16053$new_n2840 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2794 $abc$16053$new_n3209 $abc$16053$new_n2845 alu_out[11] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[11] pcpi_rs2[11] instr_and instr_andi $abc$16053$new_n2845 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[12] pcpi_rs2[12] $abc$16053$new_n2847 $abc$16053$new_n2850 alu_out[12] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2848 $abc$16053$new_n2849 $abc$16053$new_n2847 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[10] pcpi_rs2[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2838 $abc$16053$new_n2848 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[10] pcpi_rs1[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2839 $abc$16053$new_n2849 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[12] instr_and instr_andi pcpi_rs2[12] $abc$16053$new_n2850 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2794 $abc$16053$new_n3211 $abc$16053$new_n2855 alu_out[13] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[13] pcpi_rs2[13] instr_and instr_andi $abc$16053$new_n2855 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[14] pcpi_rs2[14] $abc$16053$new_n2857 $abc$16053$new_n2860 alu_out[14] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2858 $abc$16053$new_n2859 $abc$16053$new_n2857 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[12] pcpi_rs2[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2848 $abc$16053$new_n2858 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[12] pcpi_rs1[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2849 $abc$16053$new_n2859 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[14] instr_and instr_andi pcpi_rs2[14] $abc$16053$new_n2860 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2794 $abc$16053$new_n3213 $abc$16053$new_n2864 alu_out[15] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[15] pcpi_rs2[15] instr_and instr_andi $abc$16053$new_n2864 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[16] pcpi_rs2[16] $abc$16053$new_n2866 $abc$16053$new_n2869 alu_out[16] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2867 $abc$16053$new_n2868 $abc$16053$new_n2866 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[14] pcpi_rs2[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2858 $abc$16053$new_n2867 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[14] pcpi_rs1[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2859 $abc$16053$new_n2868 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[16] instr_and instr_andi pcpi_rs2[16] $abc$16053$new_n2869 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2794 $abc$16053$new_n3215 $abc$16053$new_n2873 alu_out[17] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[17] pcpi_rs2[17] instr_and instr_andi $abc$16053$new_n2873 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[18] pcpi_rs2[18] $abc$16053$new_n2875 $abc$16053$new_n2878 alu_out[18] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2876 $abc$16053$new_n2877 $abc$16053$new_n2875 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[16] pcpi_rs2[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2867 $abc$16053$new_n2876 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[16] pcpi_rs1[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2868 $abc$16053$new_n2877 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[18] instr_and instr_andi pcpi_rs2[18] $abc$16053$new_n2878 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2794 $abc$16053$new_n3217 $abc$16053$new_n2883 alu_out[19] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[19] pcpi_rs2[19] instr_and instr_andi $abc$16053$new_n2883 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[20] pcpi_rs2[20] $abc$16053$new_n2885 $abc$16053$new_n2889 alu_out[20] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor $abc$16053$new_n2887 instr_xori $abc$16053$new_n2886 instr_sub $abc$16053$new_n2885 +00001 1 +00010 1 +00011 1 +.names pcpi_rs1[18] pcpi_rs2[18] pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2876 $abc$16053$new_n2886 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_sub $abc$16053$new_n2888 $abc$16053$new_n2439 $abc$16053$new_n2877 $abc$16053$new_n2887 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pcpi_rs1[18] pcpi_rs1[19] pcpi_rs2[18] pcpi_rs2[19] $abc$16053$new_n2888 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2393 pcpi_rs1[20] instr_and instr_andi pcpi_rs2[20] $abc$16053$new_n2889 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2794 $abc$16053$new_n2891 $abc$16053$new_n2893 alu_out[21] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2892 pcpi_rs1[20] $abc$16053$new_n2886 instr_sub pcpi_rs2[20] $abc$16053$new_n2891 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2887 pcpi_rs2[20] pcpi_rs1[20] $abc$16053$new_n2892 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +.names $abc$16053$new_n2393 pcpi_rs1[21] pcpi_rs2[21] instr_and instr_andi $abc$16053$new_n2893 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[22] pcpi_rs2[22] $abc$16053$new_n2895 $abc$16053$new_n2899 alu_out[22] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2897 instr_xor instr_xori $abc$16053$new_n2896 instr_sub $abc$16053$new_n2895 +10001 1 +10010 1 +10011 1 +.names pcpi_rs1[20] pcpi_rs2[20] pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2886 $abc$16053$new_n2896 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2437 $abc$16053$new_n2887 instr_sub $abc$16053$new_n2898 $abc$16053$new_n2897 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names pcpi_rs1[20] pcpi_rs1[21] pcpi_rs2[20] pcpi_rs2[21] $abc$16053$new_n2898 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$16053$new_n2393 pcpi_rs1[22] instr_and instr_andi pcpi_rs2[22] $abc$16053$new_n2899 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2794 $abc$16053$new_n2901 $abc$16053$new_n2903 alu_out[23] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2902 pcpi_rs1[22] $abc$16053$new_n2896 instr_sub pcpi_rs2[22] $abc$16053$new_n2901 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2897 pcpi_rs2[22] pcpi_rs1[22] $abc$16053$new_n2902 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names $abc$16053$new_n2393 pcpi_rs1[23] pcpi_rs2[23] instr_and instr_andi $abc$16053$new_n2903 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[24] pcpi_rs2[24] $abc$16053$new_n2905 $abc$16053$new_n2910 alu_out[24] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor $abc$16053$new_n2907 instr_xori $abc$16053$new_n2906 instr_sub $abc$16053$new_n2905 +00001 1 +00010 1 +00011 1 +.names pcpi_rs1[22] pcpi_rs2[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2896 $abc$16053$new_n2906 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_sub $abc$16053$new_n2908 $abc$16053$new_n2907 +10 1 +.names $abc$16053$new_n2909 $abc$16053$new_n2888 $abc$16053$new_n2436 $abc$16053$new_n2877 $abc$16053$new_n2439 $abc$16053$new_n2908 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pcpi_rs2[22] pcpi_rs1[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2898 $abc$16053$new_n2909 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[24] instr_and instr_andi pcpi_rs2[24] $abc$16053$new_n2910 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2794 $abc$16053$new_n2912 $abc$16053$new_n2914 alu_out[25] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2913 pcpi_rs1[24] $abc$16053$new_n2906 instr_sub pcpi_rs2[24] $abc$16053$new_n2912 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2907 pcpi_rs2[24] pcpi_rs1[24] $abc$16053$new_n2913 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +.names $abc$16053$new_n2393 pcpi_rs1[25] pcpi_rs2[25] instr_and instr_andi $abc$16053$new_n2914 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[26] pcpi_rs2[26] $abc$16053$new_n2916 $abc$16053$new_n2920 alu_out[26] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor $abc$16053$new_n2918 instr_xori $abc$16053$new_n2917 instr_sub $abc$16053$new_n2916 +00001 1 +00010 1 +00011 1 +.names pcpi_rs1[24] pcpi_rs2[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2906 $abc$16053$new_n2917 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_sub $abc$16053$new_n2919 $abc$16053$new_n2918 +10 1 +.names pcpi_rs2[24] pcpi_rs1[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2908 $abc$16053$new_n2919 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[26] instr_and instr_andi pcpi_rs2[26] $abc$16053$new_n2920 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2794 $abc$16053$new_n2922 $abc$16053$new_n2924 alu_out[27] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2923 pcpi_rs1[26] $abc$16053$new_n2917 instr_sub pcpi_rs2[26] $abc$16053$new_n2922 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2918 pcpi_rs2[26] pcpi_rs1[26] $abc$16053$new_n2923 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +.names $abc$16053$new_n2393 pcpi_rs1[27] pcpi_rs2[27] instr_and instr_andi $abc$16053$new_n2924 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names pcpi_rs1[28] pcpi_rs2[28] $abc$16053$new_n2794 $abc$16053$new_n2926 $abc$16053$new_n2930 alu_out[28] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor $abc$16053$new_n2928 instr_xori $abc$16053$new_n2927 instr_sub $abc$16053$new_n2926 +00001 1 +00010 1 +00011 1 +.names pcpi_rs1[26] pcpi_rs2[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2917 $abc$16053$new_n2927 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_sub $abc$16053$new_n2929 $abc$16053$new_n2928 +10 1 +.names pcpi_rs2[26] pcpi_rs1[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2919 $abc$16053$new_n2929 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[28] pcpi_rs2[28] instr_and instr_andi $abc$16053$new_n2930 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2794 $abc$16053$new_n2932 $abc$16053$new_n2934 alu_out[29] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2933 pcpi_rs1[28] $abc$16053$new_n2927 instr_sub pcpi_rs2[28] $abc$16053$new_n2932 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2928 pcpi_rs2[28] pcpi_rs1[28] $abc$16053$new_n2933 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +.names $abc$16053$new_n2393 pcpi_rs1[29] pcpi_rs2[29] instr_and instr_andi $abc$16053$new_n2934 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2794 $abc$16053$new_n2936 $abc$16053$new_n2940 alu_out[30] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2938 instr_xor instr_xori $abc$16053$new_n2937 instr_sub $abc$16053$new_n2936 +10000 1 +10001 1 +10011 1 +.names pcpi_rs1[28] pcpi_rs2[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2927 $abc$16053$new_n2937 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names instr_sub $abc$16053$new_n2939 $abc$16053$new_n2938 +00 1 +01 1 +11 1 +.names pcpi_rs2[28] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2929 $abc$16053$new_n2939 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[30] pcpi_rs2[30] instr_and instr_andi $abc$16053$new_n2940 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names pcpi_rs1[31] pcpi_rs2[31] $abc$16053$new_n2794 $abc$16053$new_n2942 $abc$16053$new_n2944 alu_out[31] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2943 pcpi_rs1[30] instr_sub $abc$16053$new_n2937 pcpi_rs2[30] $abc$16053$new_n2942 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2938 pcpi_rs2[30] pcpi_rs1[30] $abc$16053$new_n2943 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names $abc$16053$new_n2393 pcpi_rs1[31] pcpi_rs2[31] instr_and instr_andi $abc$16053$new_n2944 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2946 latched_stalu reg_pc[0] alu_out_q[0] reg_out[0] cpuregs_wrdata[0] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names latched_store latched_branch $abc$16053$new_n2946 +10 1 +.names $abc$16053$new_n2946 $abc$16053$new_n1766 reg_pc[1] cpuregs_wrdata[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2946 latched_stalu reg_pc[2] alu_out_q[2] reg_out[2] cpuregs_wrdata[2] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2946 reg_pc[2] reg_pc[3] $abc$16053$new_n1705 cpuregs_wrdata[3] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$16053$new_n2946 reg_pc[4] reg_pc[2] reg_pc[3] $abc$16053$new_n1709 cpuregs_wrdata[4] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2952 alu_out_q[5] reg_out[5] cpuregs_wrdata[5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[5] reg_pc[2] reg_pc[3] reg_pc[4] $abc$16053$new_n2952 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2954 alu_out_q[6] reg_out[6] cpuregs_wrdata[6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[6] reg_pc[2] reg_pc[3] reg_pc[4] reg_pc[5] $abc$16053$new_n2954 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[7] $abc$16053$new_n2956 $abc$16053$new_n1712 cpuregs_wrdata[7] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[2] reg_pc[3] reg_pc[4] reg_pc[5] reg_pc[6] $abc$16053$new_n2956 +11111 1 +.names $abc$16053$new_n2946 reg_pc[8] reg_pc[7] $abc$16053$new_n2956 $abc$16053$new_n1714 cpuregs_wrdata[8] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2959 alu_out_q[9] reg_out[9] cpuregs_wrdata[9] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[9] reg_pc[7] reg_pc[8] $abc$16053$new_n2956 $abc$16053$new_n2959 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2961 alu_out_q[10] reg_out[10] cpuregs_wrdata[10] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[10] reg_pc[7] reg_pc[8] reg_pc[9] $abc$16053$new_n2956 $abc$16053$new_n2961 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[11] $abc$16053$new_n2963 $abc$16053$new_n1716 cpuregs_wrdata[11] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[7] reg_pc[8] reg_pc[9] reg_pc[10] $abc$16053$new_n2956 $abc$16053$new_n2963 +11111 1 +.names $abc$16053$new_n2946 reg_pc[12] reg_pc[11] $abc$16053$new_n2963 $abc$16053$new_n1724 cpuregs_wrdata[12] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2966 alu_out_q[13] reg_out[13] cpuregs_wrdata[13] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[13] reg_pc[11] reg_pc[12] $abc$16053$new_n2963 $abc$16053$new_n2966 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2968 alu_out_q[14] reg_out[14] cpuregs_wrdata[14] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[14] reg_pc[11] reg_pc[12] reg_pc[13] $abc$16053$new_n2963 $abc$16053$new_n2968 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[15] $abc$16053$new_n2970 $abc$16053$new_n1720 cpuregs_wrdata[15] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[11] reg_pc[12] reg_pc[13] reg_pc[14] $abc$16053$new_n2963 $abc$16053$new_n2970 +11111 1 +.names $abc$16053$new_n2946 reg_pc[16] reg_pc[15] $abc$16053$new_n2970 $abc$16053$new_n1730 cpuregs_wrdata[16] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2973 alu_out_q[17] reg_out[17] cpuregs_wrdata[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[17] reg_pc[15] reg_pc[16] $abc$16053$new_n2970 $abc$16053$new_n2973 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2975 alu_out_q[18] reg_out[18] cpuregs_wrdata[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[18] reg_pc[15] reg_pc[16] reg_pc[17] $abc$16053$new_n2970 $abc$16053$new_n2975 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[19] $abc$16053$new_n2977 $abc$16053$new_n1726 cpuregs_wrdata[19] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[15] reg_pc[16] reg_pc[17] reg_pc[18] $abc$16053$new_n2970 $abc$16053$new_n2977 +11111 1 +.names $abc$16053$new_n2946 reg_pc[20] reg_pc[19] $abc$16053$new_n2977 $abc$16053$new_n1734 cpuregs_wrdata[20] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[21] $abc$16053$new_n2980 $abc$16053$new_n1732 cpuregs_wrdata[21] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[19] reg_pc[20] $abc$16053$new_n2977 $abc$16053$new_n2980 +111 1 +.names $abc$16053$new_n2946 reg_pc[22] reg_pc[21] $abc$16053$new_n2980 $abc$16053$new_n1736 cpuregs_wrdata[22] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[23] $abc$16053$new_n2983 $abc$16053$new_n1738 cpuregs_wrdata[23] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[21] reg_pc[22] $abc$16053$new_n2980 $abc$16053$new_n2983 +111 1 +.names $abc$16053$new_n2946 reg_pc[24] reg_pc[23] $abc$16053$new_n2983 $abc$16053$new_n1746 cpuregs_wrdata[24] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[25] $abc$16053$new_n2986 $abc$16053$new_n1744 cpuregs_wrdata[25] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[23] reg_pc[24] $abc$16053$new_n2983 $abc$16053$new_n2986 +111 1 +.names $abc$16053$new_n2946 reg_pc[26] reg_pc[25] $abc$16053$new_n2986 $abc$16053$new_n1742 cpuregs_wrdata[26] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[27] $abc$16053$new_n2989 $abc$16053$new_n1740 cpuregs_wrdata[27] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[25] reg_pc[26] $abc$16053$new_n2986 $abc$16053$new_n2989 +111 1 +.names $abc$16053$new_n2946 reg_pc[28] reg_pc[27] $abc$16053$new_n2989 $abc$16053$new_n1749 cpuregs_wrdata[28] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2992 alu_out_q[29] reg_out[29] cpuregs_wrdata[29] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[29] reg_pc[27] reg_pc[28] $abc$16053$new_n2989 $abc$16053$new_n2992 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2994 alu_out_q[30] reg_out[30] cpuregs_wrdata[30] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[30] reg_pc[27] reg_pc[28] reg_pc[29] $abc$16053$new_n2989 $abc$16053$new_n2994 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[31] $abc$16053$new_n2996 $abc$16053$new_n2373 cpuregs_wrdata[31] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[27] reg_pc[28] reg_pc[29] reg_pc[30] $abc$16053$new_n2989 $abc$16053$new_n2996 +11111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[19] decoded_rs1[4] $0\decoded_rs1[4:0][4] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[15] decoded_rs1[0] $0\decoded_rs1[4:0][0] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[16] decoded_rs1[1] $0\decoded_rs1[4:0][1] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[17] decoded_rs1[2] $0\decoded_rs1[4:0][2] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[18] decoded_rs1[3] $0\decoded_rs1[4:0][3] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[20] decoded_rs2[0] $0\decoded_rs2[4:0][0] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[21] decoded_rs2[1] $0\decoded_rs2[4:0][1] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[22] decoded_rs2[2] $0\decoded_rs2[4:0][2] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[23] decoded_rs2[3] $0\decoded_rs2[4:0][3] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[24] decoded_rs2[4] $0\decoded_rs2[4:0][4] +001 1 +011 1 +110 1 +111 1 +.names count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[1] +01 1 +10 1 +.names count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[2] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[4] count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[5] +01 1 +10 1 +.names count_cycle[4] count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $abc$16053$new_n3012 +11111 1 +.names count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[6] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[8] count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[9] +01 1 +10 1 +.names count_cycle[8] count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $abc$16053$new_n3017 +11111 1 +.names count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[10] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[12] count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[13] +01 1 +10 1 +.names count_cycle[12] count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $abc$16053$new_n3022 +11111 1 +.names count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[14] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[16] count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[16] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[17] $abc$16053$new_n3027 $auto$alumacc.cc:485:replace_alu$4638.Y[17] +01 1 +10 1 +.names count_cycle[16] count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $abc$16053$new_n3027 +11111 1 +.names count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[18] +01 1 +10 1 +.names count_cycle[17] $abc$16053$new_n3027 $abc$16053$new_n3029 +11 1 +.names count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[19] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[20] count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[20] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[21] +01 1 +10 1 +.names count_cycle[20] count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $abc$16053$new_n3033 +1111 1 +.names count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[22] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[23] count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[23] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[24] +01 1 +10 1 +.names count_cycle[23] count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $abc$16053$new_n3037 +1111 1 +.names count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[25] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[26] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[27] count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[27] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[28] +01 1 +10 1 +.names count_cycle[27] count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $abc$16053$new_n3042 +11111 1 +.names count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[29] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[30] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[31] count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[31] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[32] $abc$16053$new_n3047 $auto$alumacc.cc:485:replace_alu$4638.Y[32] +01 1 +10 1 +.names count_cycle[31] count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $abc$16053$new_n3047 +11111 1 +.names count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[33] +01 1 +10 1 +.names count_cycle[32] $abc$16053$new_n3047 $abc$16053$new_n3049 +11 1 +.names count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[34] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[35] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[36] count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[36] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[37] +01 1 +10 1 +.names count_cycle[36] count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $abc$16053$new_n3054 +11111 1 +.names count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[38] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[39] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[40] count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[40] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[41] +01 1 +10 1 +.names count_cycle[40] count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $abc$16053$new_n3059 +11111 1 +.names count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[42] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[43] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[44] count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[44] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[45] +01 1 +10 1 +.names count_cycle[44] count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $abc$16053$new_n3064 +11111 1 +.names count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[46] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[47] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[48] count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[48] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[49] +01 1 +10 1 +.names count_cycle[48] count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $abc$16053$new_n3069 +11111 1 +.names count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[50] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[51] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[52] count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[52] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[53] +01 1 +10 1 +.names count_cycle[52] count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $abc$16053$new_n3074 +11111 1 +.names count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[54] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[55] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[56] count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[56] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[57] +01 1 +10 1 +.names count_cycle[56] count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $abc$16053$new_n3079 +11111 1 +.names count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[58] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[59] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[60] count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[60] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[61] +01 1 +10 1 +.names count_cycle[60] count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $abc$16053$new_n3084 +11111 1 +.names count_cycle[62] count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[62] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[63] count_cycle[62] count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[63] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0\decoded_rs1[4:0][2] latched_rd[2] latched_rd[1] $0\decoded_rs1[4:0][1] $abc$16053$new_n3091 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0\decoded_rs2[4:0][2] latched_rd[2] latched_rd[1] $0\decoded_rs2[4:0][1] $abc$16053$new_n3096 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.X[0] +0 1 +.names decoder_trigger instr_jal $abc$16053$new_n1751 decoded_imm_j[30] $abc$16053$new_n1690 $abc$16053$new_n3098 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1750 $abc$16053$new_n3098 reg_next_pc[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14611 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names instr_jal $abc$16053$new_n1769 decoded_imm_j[29] $abc$16053$new_n1691 $abc$16053$new_n1748 $abc$16053$new_n3100 +00010 1 +00110 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1747 decoder_trigger $abc$16053$new_n3100 reg_next_pc[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14613 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11110 1 +11111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1752 decoded_imm_j[28] $abc$16053$new_n1691 $abc$16053$new_n3102 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1748 $abc$16053$new_n3102 reg_next_pc[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14615 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[27] $abc$16053$new_n1741 instr_jal decoded_imm_j[26] $abc$16053$new_n1753 $abc$16053$new_n3104 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1739 decoder_trigger $abc$16053$new_n3104 $abc$16053$new_n1777 instr_jal $abc$16053$new_n3105 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3105 reg_next_pc[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14617 +001 1 +011 1 +110 1 +111 1 +.names decoder_trigger instr_jal decoded_imm_j[26] $abc$16053$new_n1753 $abc$16053$new_n1777 $abc$16053$new_n3107 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1741 $abc$16053$new_n3107 reg_next_pc[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14619 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1787 decoded_imm_j[25] $abc$16053$new_n1778 $abc$16053$new_n3109 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1743 $abc$16053$new_n3109 reg_next_pc[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14621 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1754 decoded_imm_j[24] $abc$16053$new_n1692 $abc$16053$new_n3111 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1745 $abc$16053$new_n3111 reg_next_pc[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14623 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1793 decoded_imm_j[23] $abc$16053$new_n1693 $abc$16053$new_n3113 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1737 $abc$16053$new_n3113 reg_next_pc[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14625 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1755 decoded_imm_j[22] $abc$16053$new_n1694 $abc$16053$new_n3115 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1735 $abc$16053$new_n3115 reg_next_pc[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14627 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names instr_jal $abc$16053$new_n1800 decoded_imm_j[21] $abc$16053$new_n1695 $abc$16053$new_n1733 $abc$16053$new_n3117 +00010 1 +00110 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1731 decoder_trigger $abc$16053$new_n3117 reg_next_pc[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14629 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11110 1 +11111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1756 decoded_imm_j[20] $abc$16053$new_n1695 $abc$16053$new_n3119 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1733 $abc$16053$new_n3119 reg_next_pc[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14631 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[19] $abc$16053$new_n1727 instr_jal decoded_imm_j[18] $abc$16053$new_n1757 $abc$16053$new_n3121 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1725 decoder_trigger $abc$16053$new_n3121 $abc$16053$new_n1808 instr_jal $abc$16053$new_n3122 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3122 reg_next_pc[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14633 +001 1 +011 1 +110 1 +111 1 +.names decoder_trigger instr_jal decoded_imm_j[18] $abc$16053$new_n1757 $abc$16053$new_n1808 $abc$16053$new_n3124 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1727 $abc$16053$new_n3124 reg_next_pc[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14635 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1818 decoded_imm_j[17] $abc$16053$new_n1809 $abc$16053$new_n3126 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1728 $abc$16053$new_n3126 reg_next_pc[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14637 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1758 decoded_imm_j[16] $abc$16053$new_n1696 $abc$16053$new_n3128 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1729 $abc$16053$new_n3128 reg_next_pc[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14639 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[15] $abc$16053$new_n1721 instr_jal decoded_imm_j[14] $abc$16053$new_n1759 $abc$16053$new_n3130 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1719 decoder_trigger $abc$16053$new_n3130 $abc$16053$new_n1825 instr_jal $abc$16053$new_n3131 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3131 reg_next_pc[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14641 +001 1 +011 1 +110 1 +111 1 +.names decoder_trigger instr_jal decoded_imm_j[14] $abc$16053$new_n1759 $abc$16053$new_n1825 $abc$16053$new_n3133 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1721 $abc$16053$new_n3133 reg_next_pc[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14643 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1835 decoded_imm_j[13] $abc$16053$new_n1826 $abc$16053$new_n3135 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1722 $abc$16053$new_n3135 reg_next_pc[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14645 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1760 decoded_imm_j[12] $abc$16053$new_n1697 $abc$16053$new_n3137 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1723 $abc$16053$new_n3137 reg_next_pc[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14647 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[11] $abc$16053$new_n1717 instr_jal decoded_imm_j[10] $abc$16053$new_n1761 $abc$16053$new_n3139 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1715 decoder_trigger $abc$16053$new_n3139 $abc$16053$new_n1842 instr_jal $abc$16053$new_n3140 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3140 reg_next_pc[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14649 +001 1 +011 1 +110 1 +111 1 +.names decoder_trigger instr_jal decoded_imm_j[10] $abc$16053$new_n1761 $abc$16053$new_n1842 $abc$16053$new_n3142 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1717 $abc$16053$new_n3142 reg_next_pc[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14651 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1851 decoded_imm_j[9] $abc$16053$new_n1698 $abc$16053$new_n3144 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1718 $abc$16053$new_n3144 reg_next_pc[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14653 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1762 decoded_imm_j[8] $abc$16053$new_n1699 $abc$16053$new_n3146 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1713 $abc$16053$new_n3146 reg_next_pc[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14655 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1858 decoded_imm_j[7] $abc$16053$new_n1700 $abc$16053$new_n3148 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1711 $abc$16053$new_n3148 reg_next_pc[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14657 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[5] $abc$16053$new_n1708 instr_jal decoded_imm_j[4] $abc$16053$new_n1764 $abc$16053$new_n3150 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1707 decoder_trigger $abc$16053$new_n3150 $abc$16053$new_n1702 instr_jal $abc$16053$new_n3151 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3151 reg_next_pc[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14661 +001 1 +011 1 +110 1 +111 1 +.names decoded_imm_j[3] $abc$16053$new_n1706 instr_jal $abc$16053$new_n1765 decoded_imm_j[2] $abc$16053$new_n3153 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1703 decoder_trigger $abc$16053$new_n3153 reg_next_pc[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14665 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[29] pcpi_rs1[27] $abc$16053$new_n3155 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$16053$new_n2043 $abc$16053$new_n2028 $abc$16053$new_n3155 pcpi_rs1[24] $abc$16053$new_n2025 $abc$16053$new_n3156 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names pcpi_rs1[22] $abc$16053$new_n2084 decoded_imm[22] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3157 +00001 1 +00011 1 +00111 1 +01011 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[21] pcpi_rs1[18] $abc$16053$new_n3158 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n3158 $abc$16053$new_n2025 pcpi_rs1[23] pcpi_rs1[26] $abc$16053$new_n3159 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$16053$new_n3157 $abc$16053$new_n2033 $abc$16053$new_n3159 $abc$16053$new_n2085 $abc$16053$auto$rtlil.cc:2693:MuxGate$14937 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names pcpi_rs1[14] $abc$16053$new_n2139 decoded_imm[14] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3161 +00001 1 +00011 1 +00111 1 +01011 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[10] $abc$16053$new_n3162 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n3162 $abc$16053$new_n2025 pcpi_rs1[15] pcpi_rs1[18] $abc$16053$new_n3163 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$16053$new_n3161 $abc$16053$new_n2033 $abc$16053$new_n3163 $abc$16053$new_n2140 $abc$16053$auto$rtlil.cc:2693:MuxGate$14953 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names pcpi_rs1[12] $abc$16053$new_n2153 decoded_imm[12] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3165 +00001 1 +00011 1 +00111 1 +01011 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[11] pcpi_rs1[8] $abc$16053$new_n3166 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n3166 $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[16] $abc$16053$new_n3167 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$16053$new_n3165 $abc$16053$new_n2033 $abc$16053$new_n3167 $abc$16053$new_n2154 $abc$16053$auto$rtlil.cc:2693:MuxGate$14957 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2013 $abc$16053$new_n2188 $abc$16053$new_n2190 $abc$16053$new_n3169 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n3169 pcpi_rs1[7] $abc$16053$new_n2033 decoded_imm[7] $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14967 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names pcpi_rs1[3] $abc$16053$new_n2015 decoded_imm[3] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3171 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[7] pcpi_rs1[4] pcpi_rs1[2] $abc$16053$new_n3172 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$16053$new_n3171 $abc$16053$new_n2033 $abc$16053$new_n2212 $abc$16053$new_n3172 $abc$16053$new_n2022 $abc$16053$auto$rtlil.cc:2693:MuxGate$14975 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[5] pcpi_rs1[2] pcpi_rs1[0] $abc$16053$new_n3174 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$16053$new_n2033 pcpi_rs1[1] $abc$16053$new_n2225 $abc$16053$new_n3174 $abc$16053$new_n2022 $abc$16053$auto$rtlil.cc:2693:MuxGate$14979 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2358 decoded_imm[31] $abc$16053$new_n2019 $abc$16053$new_n2038 $abc$16053$new_n2026 $abc$16053$new_n3176 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n3176 pcpi_rs1[31] $abc$16053$new_n2019 $abc$16053$new_n2360 $abc$16053$auto$rtlil.cc:2693:MuxGate$15109 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11110 1 +.names pcpi_rs1[0] mem_rdata[9] mem_rdata[1] $abc$16053$new_n3178 +001 1 +011 1 +110 1 +111 1 +.names pcpi_rs1[1] pcpi_rs1[0] $abc$16053$new_n3178 mem_rdata[25] mem_rdata[17] $abc$16053$new_n3179 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n1442 $abc$16053$new_n2513 $abc$16053$new_n3179 mem_rdata[17] mem_rdata[1] $abc$16053$new_n3180 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n3180 pcpi_rs1[1] $abc$16053$new_n2553 $0\reg_out[31:0][1] +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdinstr instr_rdcycleh count_instr[3] count_cycle[35] count_cycle[3] $abc$16053$new_n3182 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1610 instr_rdinstrh $abc$16053$new_n2571 count_instr[35] $abc$16053$new_n3182 $abc$16053$new_n3183 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2567 $abc$16053$new_n3183 pcpi_rs1[3] $0\reg_out[31:0][3] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdinstr instr_rdcycleh count_instr[5] count_cycle[37] count_cycle[5] $abc$16053$new_n3185 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1610 instr_rdinstrh $abc$16053$new_n2585 count_instr[37] $abc$16053$new_n3185 $abc$16053$new_n3186 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n3189 $abc$16053$new_n2454 $abc$16053$new_n3186 $abc$16053$new_n2022 pcpi_rs1[5] $0\reg_out[31:0][5] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1442 mem_rdata[5] $abc$16053$new_n2513 pcpi_rs1[1] mem_rdata[21] $abc$16053$new_n3188 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n1442 $abc$16053$new_n3188 pcpi_rs1[0] $abc$16053$new_n2590 $abc$16053$new_n3189 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instr_rdinstr instr_rdcycleh count_instr[8] count_cycle[40] count_cycle[8] $abc$16053$new_n3190 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2611 instr_rdinstrh $abc$16053$new_n2453 count_instr[40] $abc$16053$new_n3190 $abc$16053$new_n3191 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$16053$new_n1610 $abc$16053$new_n2617 reg_pc[8] decoded_imm[8] $abc$16053$new_n3191 $0\reg_out[31:0][8] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names instr_rdinstr instr_rdcycleh count_instr[20] count_cycle[52] count_cycle[20] $abc$16053$new_n3193 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2690 instr_rdinstrh $abc$16053$new_n2453 count_instr[52] $abc$16053$new_n3193 $abc$16053$new_n3194 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$16053$new_n1610 $abc$16053$new_n2688 reg_pc[20] decoded_imm[20] $abc$16053$new_n3194 $0\reg_out[31:0][20] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names instr_rdinstr instr_rdcycleh count_instr[30] count_cycle[62] count_cycle[30] $abc$16053$new_n3196 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2752 instr_rdinstrh $abc$16053$new_n2453 count_instr[62] $abc$16053$new_n3196 $abc$16053$new_n3197 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$16053$new_n1610 $abc$16053$new_n2750 reg_pc[30] decoded_imm[30] $abc$16053$new_n3197 $0\reg_out[31:0][30] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2038 $abc$16053$new_n1610 $abc$16053$new_n2022 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1549 $abc$16053$new_n3199 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2789 $abc$16053$new_n2767 $abc$16053$new_n2394 $abc$16053$new_n2769 $abc$16053$new_n2771 $abc$16053$new_n3200 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names $abc$16053$new_n2773 $abc$16053$new_n3200 $abc$16053$new_n3199 $abc$16053$new_n2019 $abc$16053$procmux$2235_Y[6] +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names instr_sub pcpi_rs1[4] mem_la_wdata[4] $abc$16053$new_n2810 $abc$16053$new_n2809 $abc$16053$new_n3202 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3202 instr_xor instr_xori $abc$16053$new_n3203 +100 1 +.names instr_sub pcpi_rs1[6] mem_la_wdata[6] $abc$16053$new_n2820 $abc$16053$new_n2819 $abc$16053$new_n3204 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3204 instr_xor instr_xori $abc$16053$new_n3205 +100 1 +.names instr_sub pcpi_rs1[8] pcpi_rs2[8] $abc$16053$new_n2830 $abc$16053$new_n2829 $abc$16053$new_n3206 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3206 instr_xor instr_xori $abc$16053$new_n3207 +100 1 +.names instr_sub pcpi_rs1[10] pcpi_rs2[10] $abc$16053$new_n2839 $abc$16053$new_n2838 $abc$16053$new_n3208 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3208 instr_xor instr_xori $abc$16053$new_n3209 +100 1 +.names instr_sub pcpi_rs1[12] pcpi_rs2[12] $abc$16053$new_n2849 $abc$16053$new_n2848 $abc$16053$new_n3210 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3210 instr_xor instr_xori $abc$16053$new_n3211 +100 1 +.names instr_sub pcpi_rs1[14] pcpi_rs2[14] $abc$16053$new_n2859 $abc$16053$new_n2858 $abc$16053$new_n3212 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3212 instr_xor instr_xori $abc$16053$new_n3213 +100 1 +.names instr_sub pcpi_rs1[16] pcpi_rs2[16] $abc$16053$new_n2868 $abc$16053$new_n2867 $abc$16053$new_n3214 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3214 instr_xor instr_xori $abc$16053$new_n3215 +100 1 +.names instr_sub pcpi_rs1[18] pcpi_rs2[18] $abc$16053$new_n2877 $abc$16053$new_n2876 $abc$16053$new_n3216 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3216 instr_xor instr_xori $abc$16053$new_n3217 +100 1 +.names $abc$16053$new_n3091 latched_rd[4] $0\decoded_rs1[4:0][4] $0\decoded_rs1[4:0][0] latched_rd[0] $abc$16053$new_n3218 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$16053$new_n3218 $0\decoded_rs1[4:0][3] latched_rd[3] $0\decoded_rs1[4:0][1] latched_rd[1] $abc$16053$auto$rtlil.cc:2515:And$4922 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n3096 $0\decoded_rs2[4:0][4] latched_rd[4] $0\decoded_rs2[4:0][0] latched_rd[0] $abc$16053$new_n3220 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$16053$new_n3220 $0\decoded_rs2[4:0][3] latched_rd[3] $0\decoded_rs2[4:0][1] latched_rd[1] $abc$16053$auto$rtlil.cc:2515:And$4912 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.subckt dff C=clk D=cpuregs_wrdata[0] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] +.subckt dff C=clk D=cpuregs_wrdata[1] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] +.subckt dff C=clk D=cpuregs_wrdata[2] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] +.subckt dff C=clk D=cpuregs_wrdata[3] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] +.subckt dff C=clk D=cpuregs_wrdata[4] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] +.subckt dff C=clk D=cpuregs_wrdata[5] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] +.subckt dff C=clk D=cpuregs_wrdata[6] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] +.subckt dff C=clk D=cpuregs_wrdata[7] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] +.subckt dff C=clk D=cpuregs_wrdata[8] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] +.subckt dff C=clk D=cpuregs_wrdata[9] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] +.subckt dff C=clk D=cpuregs_wrdata[10] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] +.subckt dff C=clk D=cpuregs_wrdata[11] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] +.subckt dff C=clk D=cpuregs_wrdata[12] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] +.subckt dff C=clk D=cpuregs_wrdata[13] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] +.subckt dff C=clk D=cpuregs_wrdata[14] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] +.subckt dff C=clk D=cpuregs_wrdata[15] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] +.subckt dff C=clk D=cpuregs_wrdata[16] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] +.subckt dff C=clk D=cpuregs_wrdata[17] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] +.subckt dff C=clk D=cpuregs_wrdata[18] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] +.subckt dff C=clk D=cpuregs_wrdata[19] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] +.subckt dff C=clk D=cpuregs_wrdata[20] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] +.subckt dff C=clk D=cpuregs_wrdata[21] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] +.subckt dff C=clk D=cpuregs_wrdata[22] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] +.subckt dff C=clk D=cpuregs_wrdata[23] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] +.subckt dff C=clk D=cpuregs_wrdata[24] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] +.subckt dff C=clk D=cpuregs_wrdata[25] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] +.subckt dff C=clk D=cpuregs_wrdata[26] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] +.subckt dff C=clk D=cpuregs_wrdata[27] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] +.subckt dff C=clk D=cpuregs_wrdata[28] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] +.subckt dff C=clk D=cpuregs_wrdata[29] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] +.subckt dff C=clk D=cpuregs_wrdata[30] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] +.subckt dff C=clk D=cpuregs_wrdata[31] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2515:And$4922 Q=$abc$16053$auto$mem.cc:1172:emulate_transparency$4923 +.subckt sdffrn C=clk D=$abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y Q=decoder_pseudo_trigger RN=$abc$16053$auto$opt_dff.cc:253:combine_resets$4218 +.subckt sdffr C=clk D=$abc$16053$reduce_or$./benchmark/picorv32.v:863$175_Y Q=is_compare R=$abc$16053$auto$opt_dff.cc:253:combine_resets$4160 +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15039 Q=mem_addr[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15037 Q=mem_addr[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15035 Q=mem_addr[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15033 Q=mem_addr[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15031 Q=mem_addr[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15029 Q=mem_addr[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15027 Q=mem_addr[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15025 Q=mem_addr[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15023 Q=mem_addr[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15021 Q=mem_addr[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15019 Q=mem_addr[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15017 Q=mem_addr[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15015 Q=mem_addr[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15013 Q=mem_addr[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15011 Q=mem_addr[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15009 Q=mem_addr[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15007 Q=mem_addr[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15005 Q=mem_addr[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15003 Q=mem_addr[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15001 Q=mem_addr[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14999 Q=mem_addr[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14997 Q=mem_addr[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14995 Q=mem_addr[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14993 Q=mem_addr[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14991 Q=mem_addr[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14989 Q=mem_addr[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14987 Q=mem_addr[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14985 Q=mem_addr[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14983 Q=mem_addr[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15203 Q=mem_addr[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2515:And$4912 Q=$abc$16053$auto$mem.cc:1172:emulate_transparency$4913 +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14981 Q=pcpi_rs1[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14979 Q=pcpi_rs1[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14977 Q=pcpi_rs1[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14975 Q=pcpi_rs1[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14973 Q=pcpi_rs1[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14971 Q=pcpi_rs1[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14969 Q=pcpi_rs1[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14967 Q=pcpi_rs1[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14965 Q=pcpi_rs1[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14963 Q=pcpi_rs1[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14961 Q=pcpi_rs1[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14959 Q=pcpi_rs1[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14957 Q=pcpi_rs1[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14955 Q=pcpi_rs1[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14953 Q=pcpi_rs1[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14951 Q=pcpi_rs1[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14949 Q=pcpi_rs1[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14947 Q=pcpi_rs1[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14945 Q=pcpi_rs1[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14943 Q=pcpi_rs1[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14941 Q=pcpi_rs1[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14939 Q=pcpi_rs1[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14937 Q=pcpi_rs1[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14935 Q=pcpi_rs1[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14933 Q=pcpi_rs1[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14931 Q=pcpi_rs1[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14929 Q=pcpi_rs1[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14927 Q=pcpi_rs1[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14925 Q=pcpi_rs1[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14923 Q=pcpi_rs1[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15111 Q=pcpi_rs1[30] +.subckt dff C=clk D=mem_rdata_latched[0] Q=mem_rdata_q[0] +.subckt dff C=clk D=mem_rdata_latched[1] Q=mem_rdata_q[1] +.subckt dff C=clk D=mem_rdata_latched[2] Q=mem_rdata_q[2] +.subckt dff C=clk D=mem_rdata_latched[3] Q=mem_rdata_q[3] +.subckt dff C=clk D=mem_rdata_latched[4] Q=mem_rdata_q[4] +.subckt dff C=clk D=mem_rdata_latched[5] Q=mem_rdata_q[5] +.subckt dff C=clk D=mem_rdata_latched[6] Q=mem_rdata_q[6] +.subckt dff C=clk D=mem_rdata_latched[7] Q=mem_rdata_q[7] +.subckt dff C=clk D=mem_rdata_latched[8] Q=mem_rdata_q[8] +.subckt dff C=clk D=mem_rdata_latched[9] Q=mem_rdata_q[9] +.subckt dff C=clk D=mem_rdata_latched[10] Q=mem_rdata_q[10] +.subckt dff C=clk D=mem_rdata_latched[11] Q=mem_rdata_q[11] +.subckt dff C=clk D=mem_rdata_latched[12] Q=mem_rdata_q[12] +.subckt dff C=clk D=mem_rdata_latched[13] Q=mem_rdata_q[13] +.subckt dff C=clk D=mem_rdata_latched[14] Q=mem_rdata_q[14] +.subckt dff C=clk D=mem_rdata_latched[15] Q=mem_rdata_q[15] +.subckt dff C=clk D=mem_rdata_latched[16] Q=mem_rdata_q[16] +.subckt dff C=clk D=mem_rdata_latched[17] Q=mem_rdata_q[17] +.subckt dff C=clk D=mem_rdata_latched[18] Q=mem_rdata_q[18] +.subckt dff C=clk D=mem_rdata_latched[19] Q=mem_rdata_q[19] +.subckt dff C=clk D=mem_rdata_latched[20] Q=mem_rdata_q[20] +.subckt dff C=clk D=mem_rdata_latched[21] Q=mem_rdata_q[21] +.subckt dff C=clk D=mem_rdata_latched[22] Q=mem_rdata_q[22] +.subckt dff C=clk D=mem_rdata_latched[23] Q=mem_rdata_q[23] +.subckt dff C=clk D=mem_rdata_latched[24] Q=mem_rdata_q[24] +.subckt dff C=clk D=mem_rdata_latched[25] Q=mem_rdata_q[25] +.subckt dff C=clk D=mem_rdata_latched[26] Q=mem_rdata_q[26] +.subckt dff C=clk D=mem_rdata_latched[27] Q=mem_rdata_q[27] +.subckt dff C=clk D=mem_rdata_latched[28] Q=mem_rdata_q[28] +.subckt dff C=clk D=mem_rdata_latched[29] Q=mem_rdata_q[29] +.subckt dff C=clk D=mem_rdata_latched[30] Q=mem_rdata_q[30] +.subckt dff C=clk D=mem_rdata_latched[31] Q=mem_rdata_q[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15189 Q=mem_valid +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14859 Q=count_instr[0] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14857 Q=count_instr[1] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14855 Q=count_instr[2] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14853 Q=count_instr[3] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14851 Q=count_instr[4] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14849 Q=count_instr[5] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14847 Q=count_instr[6] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14845 Q=count_instr[7] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14843 Q=count_instr[8] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14841 Q=count_instr[9] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14839 Q=count_instr[10] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14837 Q=count_instr[11] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14835 Q=count_instr[12] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14833 Q=count_instr[13] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14831 Q=count_instr[14] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14829 Q=count_instr[15] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14827 Q=count_instr[16] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14825 Q=count_instr[17] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14823 Q=count_instr[18] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14821 Q=count_instr[19] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14819 Q=count_instr[20] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14817 Q=count_instr[21] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14815 Q=count_instr[22] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14813 Q=count_instr[23] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14811 Q=count_instr[24] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14809 Q=count_instr[25] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14807 Q=count_instr[26] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14805 Q=count_instr[27] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14803 Q=count_instr[28] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14801 Q=count_instr[29] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14799 Q=count_instr[30] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14797 Q=count_instr[31] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14795 Q=count_instr[32] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14793 Q=count_instr[33] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14791 Q=count_instr[34] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14789 Q=count_instr[35] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14787 Q=count_instr[36] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14785 Q=count_instr[37] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14783 Q=count_instr[38] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14781 Q=count_instr[39] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14779 Q=count_instr[40] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14777 Q=count_instr[41] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14775 Q=count_instr[42] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14773 Q=count_instr[43] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14771 Q=count_instr[44] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14769 Q=count_instr[45] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14767 Q=count_instr[46] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14765 Q=count_instr[47] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14763 Q=count_instr[48] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14761 Q=count_instr[49] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14759 Q=count_instr[50] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14757 Q=count_instr[51] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14755 Q=count_instr[52] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14753 Q=count_instr[53] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14751 Q=count_instr[54] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14749 Q=count_instr[55] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14747 Q=count_instr[56] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14745 Q=count_instr[57] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14743 Q=count_instr[58] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14741 Q=count_instr[59] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14739 Q=count_instr[60] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14737 Q=count_instr[61] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14735 Q=count_instr[62] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15113 Q=count_instr[63] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$procmux$1608_CMP Q=trap RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.X[0] Q=count_cycle[0] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[1] Q=count_cycle[1] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[2] Q=count_cycle[2] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[3] Q=count_cycle[3] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[4] Q=count_cycle[4] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[5] Q=count_cycle[5] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[6] Q=count_cycle[6] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[7] Q=count_cycle[7] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[8] Q=count_cycle[8] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[9] Q=count_cycle[9] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[10] Q=count_cycle[10] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[11] Q=count_cycle[11] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[12] Q=count_cycle[12] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[13] Q=count_cycle[13] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[14] Q=count_cycle[14] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[15] Q=count_cycle[15] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[16] Q=count_cycle[16] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[17] Q=count_cycle[17] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[18] Q=count_cycle[18] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[19] Q=count_cycle[19] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[20] Q=count_cycle[20] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[21] Q=count_cycle[21] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[22] Q=count_cycle[22] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[23] Q=count_cycle[23] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[24] Q=count_cycle[24] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[25] Q=count_cycle[25] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[26] Q=count_cycle[26] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[27] Q=count_cycle[27] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[28] Q=count_cycle[28] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[29] Q=count_cycle[29] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[30] Q=count_cycle[30] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[31] Q=count_cycle[31] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[32] Q=count_cycle[32] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[33] Q=count_cycle[33] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[34] Q=count_cycle[34] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[35] Q=count_cycle[35] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[36] Q=count_cycle[36] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[37] Q=count_cycle[37] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[38] Q=count_cycle[38] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[39] Q=count_cycle[39] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[40] Q=count_cycle[40] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[41] Q=count_cycle[41] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[42] Q=count_cycle[42] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[43] Q=count_cycle[43] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[44] Q=count_cycle[44] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[45] Q=count_cycle[45] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[46] Q=count_cycle[46] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[47] Q=count_cycle[47] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[48] Q=count_cycle[48] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[49] Q=count_cycle[49] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[50] Q=count_cycle[50] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[51] Q=count_cycle[51] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[52] Q=count_cycle[52] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[53] Q=count_cycle[53] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[54] Q=count_cycle[54] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[55] Q=count_cycle[55] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[56] Q=count_cycle[56] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[57] Q=count_cycle[57] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[58] Q=count_cycle[58] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[59] Q=count_cycle[59] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[60] Q=count_cycle[60] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[61] Q=count_cycle[61] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[62] Q=count_cycle[62] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[63] Q=count_cycle[63] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14733 Q=reg_pc[0] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14731 Q=reg_pc[1] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14729 Q=reg_pc[2] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14727 Q=reg_pc[3] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14725 Q=reg_pc[4] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14723 Q=reg_pc[5] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14721 Q=reg_pc[6] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14719 Q=reg_pc[7] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14717 Q=reg_pc[8] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14715 Q=reg_pc[9] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14713 Q=reg_pc[10] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14711 Q=reg_pc[11] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14709 Q=reg_pc[12] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14707 Q=reg_pc[13] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14705 Q=reg_pc[14] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14703 Q=reg_pc[15] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14701 Q=reg_pc[16] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14699 Q=reg_pc[17] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14697 Q=reg_pc[18] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14695 Q=reg_pc[19] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14693 Q=reg_pc[20] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14691 Q=reg_pc[21] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14689 Q=reg_pc[22] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14687 Q=reg_pc[23] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14685 Q=reg_pc[24] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14683 Q=reg_pc[25] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14681 Q=reg_pc[26] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14679 Q=reg_pc[27] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14677 Q=reg_pc[28] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14675 Q=reg_pc[29] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14673 Q=reg_pc[30] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15115 Q=reg_pc[31] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14671 Q=reg_next_pc[0] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14669 Q=reg_next_pc[1] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14667 Q=reg_next_pc[2] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14665 Q=reg_next_pc[3] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14663 Q=reg_next_pc[4] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14661 Q=reg_next_pc[5] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14659 Q=reg_next_pc[6] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14657 Q=reg_next_pc[7] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14655 Q=reg_next_pc[8] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14653 Q=reg_next_pc[9] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14651 Q=reg_next_pc[10] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14649 Q=reg_next_pc[11] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14647 Q=reg_next_pc[12] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14645 Q=reg_next_pc[13] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14643 Q=reg_next_pc[14] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14641 Q=reg_next_pc[15] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14639 Q=reg_next_pc[16] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14637 Q=reg_next_pc[17] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14635 Q=reg_next_pc[18] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14633 Q=reg_next_pc[19] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14631 Q=reg_next_pc[20] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14629 Q=reg_next_pc[21] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14627 Q=reg_next_pc[22] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14625 Q=reg_next_pc[23] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14623 Q=reg_next_pc[24] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14621 Q=reg_next_pc[25] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14619 Q=reg_next_pc[26] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14617 Q=reg_next_pc[27] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14615 Q=reg_next_pc[28] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14613 Q=reg_next_pc[29] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14611 Q=reg_next_pc[30] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15117 Q=reg_next_pc[31] RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15109 Q=pcpi_rs1[31] +.subckt dff C=clk D=$0\reg_out[31:0][0] Q=reg_out[0] +.subckt dff C=clk D=$0\reg_out[31:0][1] Q=reg_out[1] +.subckt dff C=clk D=$0\reg_out[31:0][2] Q=reg_out[2] +.subckt dff C=clk D=$0\reg_out[31:0][3] Q=reg_out[3] +.subckt dff C=clk D=$0\reg_out[31:0][4] Q=reg_out[4] +.subckt dff C=clk D=$0\reg_out[31:0][5] Q=reg_out[5] +.subckt dff C=clk D=$0\reg_out[31:0][6] Q=reg_out[6] +.subckt dff C=clk D=$0\reg_out[31:0][7] Q=reg_out[7] +.subckt dff C=clk D=$0\reg_out[31:0][8] Q=reg_out[8] +.subckt dff C=clk D=$0\reg_out[31:0][9] Q=reg_out[9] +.subckt dff C=clk D=$0\reg_out[31:0][10] Q=reg_out[10] +.subckt dff C=clk D=$0\reg_out[31:0][11] Q=reg_out[11] +.subckt dff C=clk D=$0\reg_out[31:0][12] Q=reg_out[12] +.subckt dff C=clk D=$0\reg_out[31:0][13] Q=reg_out[13] +.subckt dff C=clk D=$0\reg_out[31:0][14] Q=reg_out[14] +.subckt dff C=clk D=$0\reg_out[31:0][15] Q=reg_out[15] +.subckt dff C=clk D=$0\reg_out[31:0][16] Q=reg_out[16] +.subckt dff C=clk D=$0\reg_out[31:0][17] Q=reg_out[17] +.subckt dff C=clk D=$0\reg_out[31:0][18] Q=reg_out[18] +.subckt dff C=clk D=$0\reg_out[31:0][19] Q=reg_out[19] +.subckt dff C=clk D=$0\reg_out[31:0][20] Q=reg_out[20] +.subckt dff C=clk D=$0\reg_out[31:0][21] Q=reg_out[21] +.subckt dff C=clk D=$0\reg_out[31:0][22] Q=reg_out[22] +.subckt dff C=clk D=$0\reg_out[31:0][23] Q=reg_out[23] +.subckt dff C=clk D=$0\reg_out[31:0][24] Q=reg_out[24] +.subckt dff C=clk D=$0\reg_out[31:0][25] Q=reg_out[25] +.subckt dff C=clk D=$0\reg_out[31:0][26] Q=reg_out[26] +.subckt dff C=clk D=$0\reg_out[31:0][27] Q=reg_out[27] +.subckt dff C=clk D=$0\reg_out[31:0][28] Q=reg_out[28] +.subckt dff C=clk D=$0\reg_out[31:0][29] Q=reg_out[29] +.subckt dff C=clk D=$0\reg_out[31:0][30] Q=reg_out[30] +.subckt dff C=clk D=$0\reg_out[31:0][31] Q=reg_out[31] +.subckt dff C=clk D=$0\reg_sh[4:0][0] Q=reg_sh[0] +.subckt dff C=clk D=$0\reg_sh[4:0][1] Q=reg_sh[1] +.subckt dff C=clk D=$0\reg_sh[4:0][2] Q=reg_sh[2] +.subckt dff C=clk D=$0\reg_sh[4:0][3] Q=reg_sh[3] +.subckt dff C=clk D=$0\reg_sh[4:0][4] Q=reg_sh[4] +.subckt sdffr C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15119 Q=mem_do_prefetch R=$abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14609 Q=mem_la_wdata[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14607 Q=mem_la_wdata[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14605 Q=mem_la_wdata[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14603 Q=mem_la_wdata[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14601 Q=mem_la_wdata[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14599 Q=mem_la_wdata[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14597 Q=mem_la_wdata[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14595 Q=mem_la_wdata[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14593 Q=pcpi_rs2[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14591 Q=pcpi_rs2[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14589 Q=pcpi_rs2[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14587 Q=pcpi_rs2[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14585 Q=pcpi_rs2[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14583 Q=pcpi_rs2[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14581 Q=pcpi_rs2[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14579 Q=pcpi_rs2[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14577 Q=pcpi_rs2[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14575 Q=pcpi_rs2[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14573 Q=pcpi_rs2[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14571 Q=pcpi_rs2[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14569 Q=pcpi_rs2[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14567 Q=pcpi_rs2[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14565 Q=pcpi_rs2[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14563 Q=pcpi_rs2[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14561 Q=pcpi_rs2[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14559 Q=pcpi_rs2[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14557 Q=pcpi_rs2[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14555 Q=pcpi_rs2[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14553 Q=pcpi_rs2[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14551 Q=pcpi_rs2[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14549 Q=pcpi_rs2[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15107 Q=pcpi_rs2[31] +.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15121 Q=mem_do_rinst S=$0\set_mem_do_rinst[0:0] +.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15123 Q=mem_do_rdata S=$0\set_mem_do_rdata[0:0] +.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15125 Q=mem_do_wdata S=$0\set_mem_do_wdata[0:0] +.subckt dff C=clk D=$0\decoder_trigger[0:0] Q=decoder_trigger +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15127 Q=latched_store RN=resetn +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[0] Q=cpu_state[0] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[1] Q=cpu_state[1] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[2] Q=cpu_state[2] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[3] Q=cpu_state[3] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[4] Q=cpu_state[4] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[5] Q=cpu_state[5] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[6] Q=cpu_state[6] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffs C=clk D=$abc$16053$procmux$2235_Y[7] Q=cpu_state[7] S=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15129 Q=latched_stalu RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15131 Q=latched_branch RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14547 Q=latched_rd[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14543 Q=latched_rd[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14539 Q=latched_rd[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14535 Q=latched_rd[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15201 Q=latched_rd[4] +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15133 Q=latched_is_lh RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15135 Q=latched_is_lb RN=resetn +.subckt dff C=clk D=alu_out[0] Q=alu_out_q[0] +.subckt dff C=clk D=alu_out[1] Q=alu_out_q[1] +.subckt dff C=clk D=alu_out[2] Q=alu_out_q[2] +.subckt dff C=clk D=alu_out[3] Q=alu_out_q[3] +.subckt dff C=clk D=alu_out[4] Q=alu_out_q[4] +.subckt dff C=clk D=alu_out[5] Q=alu_out_q[5] +.subckt dff C=clk D=alu_out[6] Q=alu_out_q[6] +.subckt dff C=clk D=alu_out[7] Q=alu_out_q[7] +.subckt dff C=clk D=alu_out[8] Q=alu_out_q[8] +.subckt dff C=clk D=alu_out[9] Q=alu_out_q[9] +.subckt dff C=clk D=alu_out[10] Q=alu_out_q[10] +.subckt dff C=clk D=alu_out[11] Q=alu_out_q[11] +.subckt dff C=clk D=alu_out[12] Q=alu_out_q[12] +.subckt dff C=clk D=alu_out[13] Q=alu_out_q[13] +.subckt dff C=clk D=alu_out[14] Q=alu_out_q[14] +.subckt dff C=clk D=alu_out[15] Q=alu_out_q[15] +.subckt dff C=clk D=alu_out[16] Q=alu_out_q[16] +.subckt dff C=clk D=alu_out[17] Q=alu_out_q[17] +.subckt dff C=clk D=alu_out[18] Q=alu_out_q[18] +.subckt dff C=clk D=alu_out[19] Q=alu_out_q[19] +.subckt dff C=clk D=alu_out[20] Q=alu_out_q[20] +.subckt dff C=clk D=alu_out[21] Q=alu_out_q[21] +.subckt dff C=clk D=alu_out[22] Q=alu_out_q[22] +.subckt dff C=clk D=alu_out[23] Q=alu_out_q[23] +.subckt dff C=clk D=alu_out[24] Q=alu_out_q[24] +.subckt dff C=clk D=alu_out[25] Q=alu_out_q[25] +.subckt dff C=clk D=alu_out[26] Q=alu_out_q[26] +.subckt dff C=clk D=alu_out[27] Q=alu_out_q[27] +.subckt dff C=clk D=alu_out[28] Q=alu_out_q[28] +.subckt dff C=clk D=alu_out[29] Q=alu_out_q[29] +.subckt dff C=clk D=alu_out[30] Q=alu_out_q[30] +.subckt dff C=clk D=alu_out[31] Q=alu_out_q[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15105 Q=instr_lui +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15103 Q=instr_auipc +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15101 Q=instr_jal +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15137 Q=instr_beq RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15139 Q=instr_bne RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15141 Q=instr_blt RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15143 Q=instr_bge RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15145 Q=instr_bltu RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15147 Q=instr_bgeu RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15099 Q=instr_jalr +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15097 Q=instr_lb +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15095 Q=instr_lh +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15093 Q=instr_lw +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15091 Q=instr_lbu +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15089 Q=instr_lhu +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15087 Q=instr_sb +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15085 Q=instr_sh +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15149 Q=instr_addi RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15151 Q=instr_slti RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15153 Q=instr_sltiu RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15155 Q=instr_xori RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15157 Q=instr_ori RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15159 Q=instr_andi RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15083 Q=instr_sw +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15081 Q=instr_slli +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15079 Q=instr_srli +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15161 Q=instr_add RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15163 Q=instr_sub RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15165 Q=instr_sll RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15167 Q=instr_slt RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15169 Q=instr_sltu RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15171 Q=instr_xor RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15173 Q=instr_srl RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15175 Q=instr_sra RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15177 Q=instr_or RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15179 Q=instr_and RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15077 Q=instr_srai +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15075 Q=instr_rdcycle +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15073 Q=instr_rdcycleh +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15071 Q=instr_rdinstr +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15181 Q=instr_fence RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15069 Q=instr_rdinstrh +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14531 Q=decoded_imm_j[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14529 Q=decoded_imm_j[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14527 Q=decoded_imm_j[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14525 Q=decoded_imm_j[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14523 Q=decoded_imm_j[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14521 Q=decoded_imm_j[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14519 Q=decoded_imm_j[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14517 Q=decoded_imm_j[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14515 Q=decoded_imm_j[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14513 Q=decoded_imm_j[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14511 Q=decoded_imm_j[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14509 Q=decoded_imm_j[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14507 Q=decoded_imm_j[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14505 Q=decoded_imm_j[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14503 Q=decoded_imm_j[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14501 Q=decoded_imm_j[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14499 Q=decoded_imm_j[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14497 Q=decoded_imm_j[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14495 Q=decoded_imm_j[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14493 Q=decoded_imm_j[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14491 Q=decoded_imm_j[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14489 Q=decoded_imm_j[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14487 Q=decoded_imm_j[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14485 Q=decoded_imm_j[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14483 Q=decoded_imm_j[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14481 Q=decoded_imm_j[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14479 Q=decoded_imm_j[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14477 Q=decoded_imm_j[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14475 Q=decoded_imm_j[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14473 Q=decoded_imm_j[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15185 Q=decoded_imm_j[31] +.subckt dff C=clk D=$0\decoded_rs1[4:0][0] Q=decoded_rs1[0] +.subckt dff C=clk D=$0\decoded_rs1[4:0][1] Q=decoded_rs1[1] +.subckt dff C=clk D=$0\decoded_rs1[4:0][2] Q=decoded_rs1[2] +.subckt dff C=clk D=$0\decoded_rs1[4:0][3] Q=decoded_rs1[3] +.subckt dff C=clk D=$0\decoded_rs1[4:0][4] Q=decoded_rs1[4] +.subckt dff C=clk D=$0\decoded_rs2[4:0][0] Q=decoded_rs2[0] +.subckt dff C=clk D=$0\decoded_rs2[4:0][1] Q=decoded_rs2[1] +.subckt dff C=clk D=$0\decoded_rs2[4:0][2] Q=decoded_rs2[2] +.subckt dff C=clk D=$0\decoded_rs2[4:0][3] Q=decoded_rs2[3] +.subckt dff C=clk D=$0\decoded_rs2[4:0][4] Q=decoded_rs2[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14471 Q=decoded_rd[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14469 Q=decoded_rd[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14467 Q=decoded_rd[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14465 Q=decoded_rd[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15067 Q=decoded_rd[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14463 Q=decoded_imm[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14461 Q=decoded_imm[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14459 Q=decoded_imm[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14457 Q=decoded_imm[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14455 Q=decoded_imm[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14453 Q=decoded_imm[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14451 Q=decoded_imm[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14449 Q=decoded_imm[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14447 Q=decoded_imm[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14445 Q=decoded_imm[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14443 Q=decoded_imm[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14441 Q=decoded_imm[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14439 Q=decoded_imm[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14437 Q=decoded_imm[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14435 Q=decoded_imm[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14433 Q=decoded_imm[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14431 Q=decoded_imm[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14429 Q=decoded_imm[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14427 Q=decoded_imm[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14425 Q=decoded_imm[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14423 Q=decoded_imm[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14421 Q=decoded_imm[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14419 Q=decoded_imm[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14417 Q=decoded_imm[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14415 Q=decoded_imm[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14413 Q=decoded_imm[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14411 Q=decoded_imm[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14409 Q=decoded_imm[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14407 Q=decoded_imm[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14405 Q=decoded_imm[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14403 Q=decoded_imm[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15065 Q=decoded_imm[31] +.subckt dff C=clk D=$0\is_lui_auipc_jal[0:0] Q=is_lui_auipc_jal +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15063 Q=is_lb_lh_lw_lbu_lhu +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15061 Q=is_slli_srli_srai +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15059 Q=is_jalr_addi_slti_sltiu_xori_ori_andi +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15057 Q=is_sb_sh_sw +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15183 Q=is_beq_bne_blt_bge_bltu_bgeu RN=resetn +.subckt dff C=clk D=$0\is_slti_blt_slt[0:0] Q=is_slti_blt_slt +.subckt dff C=clk D=$0\is_sltiu_bltu_sltu[0:0] Q=is_sltiu_bltu_sltu +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15055 Q=is_sll_srl_sra +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15053 Q=is_alu_reg_imm +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15051 Q=is_alu_reg_reg +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15049 Q=mem_instr +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14401 Q=mem_state[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15193 Q=mem_state[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14397 Q=mem_wdata[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14395 Q=mem_wdata[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14393 Q=mem_wdata[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14391 Q=mem_wdata[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14389 Q=mem_wdata[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14387 Q=mem_wdata[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14385 Q=mem_wdata[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14383 Q=mem_wdata[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14381 Q=mem_wdata[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14379 Q=mem_wdata[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14377 Q=mem_wdata[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14375 Q=mem_wdata[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14373 Q=mem_wdata[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14371 Q=mem_wdata[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14369 Q=mem_wdata[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14367 Q=mem_wdata[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14365 Q=mem_wdata[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14363 Q=mem_wdata[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14361 Q=mem_wdata[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14359 Q=mem_wdata[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14357 Q=mem_wdata[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14355 Q=mem_wdata[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14353 Q=mem_wdata[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14351 Q=mem_wdata[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14349 Q=mem_wdata[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14347 Q=mem_wdata[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14345 Q=mem_wdata[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14343 Q=mem_wdata[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14341 Q=mem_wdata[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14339 Q=mem_wdata[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14337 Q=mem_wdata[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15045 Q=mem_wdata[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14335 Q=mem_wstrb[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14333 Q=mem_wstrb[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14331 Q=mem_wstrb[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15043 Q=mem_wstrb[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15207 Q=mem_wordsize[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15197 Q=mem_wordsize[1] +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=cpuregs_wrdata[0] data_i[34]=cpuregs_wrdata[1] data_i[33]=cpuregs_wrdata[2] data_i[32]=cpuregs_wrdata[3] data_i[31]=cpuregs_wrdata[4] data_i[30]=cpuregs_wrdata[5] data_i[29]=cpuregs_wrdata[6] data_i[28]=cpuregs_wrdata[7] data_i[27]=cpuregs_wrdata[8] data_i[26]=cpuregs_wrdata[9] data_i[25]=cpuregs_wrdata[10] data_i[24]=cpuregs_wrdata[11] data_i[23]=cpuregs_wrdata[12] data_i[22]=cpuregs_wrdata[13] data_i[21]=cpuregs_wrdata[14] data_i[20]=cpuregs_wrdata[15] data_i[19]=cpuregs_wrdata[16] data_i[18]=cpuregs_wrdata[17] data_i[17]=cpuregs_wrdata[18] data_i[16]=cpuregs_wrdata[19] data_i[15]=cpuregs_wrdata[20] data_i[14]=cpuregs_wrdata[21] data_i[13]=cpuregs_wrdata[22] data_i[12]=cpuregs_wrdata[23] data_i[11]=cpuregs_wrdata[24] data_i[10]=cpuregs_wrdata[25] data_i[9]=cpuregs_wrdata[26] data_i[8]=cpuregs_wrdata[27] data_i[7]=cpuregs_wrdata[28] data_i[6]=cpuregs_wrdata[29] data_i[5]=cpuregs_wrdata[30] data_i[4]=cpuregs_wrdata[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[0] q_o[34]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[1] q_o[33]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[2] q_o[32]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[3] q_o[31]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[4] q_o[30]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[5] q_o[29]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[6] q_o[28]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[7] q_o[27]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[8] q_o[26]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[9] q_o[25]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[10] q_o[24]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[11] q_o[23]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[12] q_o[22]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[13] q_o[21]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[14] q_o[20]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[15] q_o[19]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[16] q_o[18]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[17] q_o[17]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[18] q_o[16]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[19] q_o[15]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[20] q_o[14]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[21] q_o[13]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[22] q_o[12]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[23] q_o[11]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[24] q_o[10]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[25] q_o[9]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[26] q_o[8]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[27] q_o[7]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[28] q_o[6]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[29] q_o[5]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[30] q_o[4]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4926[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4926[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4926[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4926[35] raddr_i[7]=$0\decoded_rs2[4:0][0] raddr_i[6]=$0\decoded_rs2[4:0][1] raddr_i[5]=$0\decoded_rs2[4:0][2] raddr_i[4]=$0\decoded_rs2[4:0][3] raddr_i[3]=$0\decoded_rs2[4:0][4] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=latched_rd[0] waddr_i[6]=latched_rd[1] waddr_i[5]=latched_rd[2] waddr_i[4]=latched_rd[3] waddr_i[3]=latched_rd[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=$0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=cpuregs_wrdata[0] data_i[34]=cpuregs_wrdata[1] data_i[33]=cpuregs_wrdata[2] data_i[32]=cpuregs_wrdata[3] data_i[31]=cpuregs_wrdata[4] data_i[30]=cpuregs_wrdata[5] data_i[29]=cpuregs_wrdata[6] data_i[28]=cpuregs_wrdata[7] data_i[27]=cpuregs_wrdata[8] data_i[26]=cpuregs_wrdata[9] data_i[25]=cpuregs_wrdata[10] data_i[24]=cpuregs_wrdata[11] data_i[23]=cpuregs_wrdata[12] data_i[22]=cpuregs_wrdata[13] data_i[21]=cpuregs_wrdata[14] data_i[20]=cpuregs_wrdata[15] data_i[19]=cpuregs_wrdata[16] data_i[18]=cpuregs_wrdata[17] data_i[17]=cpuregs_wrdata[18] data_i[16]=cpuregs_wrdata[19] data_i[15]=cpuregs_wrdata[20] data_i[14]=cpuregs_wrdata[21] data_i[13]=cpuregs_wrdata[22] data_i[12]=cpuregs_wrdata[23] data_i[11]=cpuregs_wrdata[24] data_i[10]=cpuregs_wrdata[25] data_i[9]=cpuregs_wrdata[26] data_i[8]=cpuregs_wrdata[27] data_i[7]=cpuregs_wrdata[28] data_i[6]=cpuregs_wrdata[29] data_i[5]=cpuregs_wrdata[30] data_i[4]=cpuregs_wrdata[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[0] q_o[34]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[1] q_o[33]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[2] q_o[32]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[3] q_o[31]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[4] q_o[30]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[5] q_o[29]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[6] q_o[28]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[7] q_o[27]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[8] q_o[26]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[9] q_o[25]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[10] q_o[24]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[11] q_o[23]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[12] q_o[22]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[13] q_o[21]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[14] q_o[20]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[15] q_o[19]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[16] q_o[18]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[17] q_o[17]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[18] q_o[16]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[19] q_o[15]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[20] q_o[14]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[21] q_o[13]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[22] q_o[12]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[23] q_o[11]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[24] q_o[10]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[25] q_o[9]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[26] q_o[8]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[27] q_o[7]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[28] q_o[6]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[29] q_o[5]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[30] q_o[4]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4927[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4927[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4927[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4927[35] raddr_i[7]=$0\decoded_rs1[4:0][0] raddr_i[6]=$0\decoded_rs1[4:0][1] raddr_i[5]=$0\decoded_rs1[4:0][2] raddr_i[4]=$0\decoded_rs1[4:0][3] raddr_i[3]=$0\decoded_rs1[4:0][4] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=latched_rd[0] waddr_i[6]=latched_rd[1] waddr_i[5]=latched_rd[2] waddr_i[4]=latched_rd[3] waddr_i[3]=latched_rd[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=$0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[0] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[1] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[2] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[3] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[4] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[5] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[6] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[7] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[8] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[9] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[10] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[11] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[12] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[13] 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$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[30] $auto$memory_bram.cc:844:replace_memory$4927[30] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[31] $auto$memory_bram.cc:844:replace_memory$4927[31] +1 1 +.names $false decoded_imm_j[0] +1 1 +.names $false eoi[0] +1 1 +.names $false eoi[1] +1 1 +.names $false eoi[2] +1 1 +.names $false eoi[3] +1 1 +.names $false eoi[4] +1 1 +.names $false eoi[5] +1 1 +.names $false eoi[6] +1 1 +.names $false eoi[7] +1 1 +.names $false eoi[8] +1 1 +.names $false eoi[9] +1 1 +.names $false eoi[10] +1 1 +.names $false eoi[11] +1 1 +.names $false eoi[12] +1 1 +.names $false eoi[13] +1 1 +.names $false eoi[14] +1 1 +.names $false eoi[15] +1 1 +.names $false eoi[16] +1 1 +.names $false eoi[17] +1 1 +.names $false eoi[18] +1 1 +.names $false eoi[19] +1 1 +.names $false eoi[20] +1 1 +.names $false eoi[21] +1 1 +.names $false eoi[22] +1 1 +.names $false eoi[23] +1 1 +.names $false eoi[24] +1 1 +.names $false eoi[25] +1 1 +.names $false eoi[26] +1 1 +.names $false eoi[27] +1 1 +.names $false eoi[28] +1 1 +.names $false eoi[29] +1 1 +.names $false eoi[30] +1 1 +.names $false eoi[31] +1 1 +.names $false mem_addr[0] +1 1 +.names $false mem_addr[1] +1 1 +.names $false mem_la_addr[0] +1 1 +.names $false mem_la_addr[1] +1 1 +.names $undef pcpi_insn[0] +1 1 +.names $undef pcpi_insn[1] +1 1 +.names $undef pcpi_insn[2] +1 1 +.names $undef pcpi_insn[3] +1 1 +.names $undef pcpi_insn[4] +1 1 +.names $undef pcpi_insn[5] +1 1 +.names $undef pcpi_insn[6] +1 1 +.names $undef pcpi_insn[7] +1 1 +.names $undef pcpi_insn[8] +1 1 +.names $undef pcpi_insn[9] +1 1 +.names $undef pcpi_insn[10] +1 1 +.names $undef pcpi_insn[11] +1 1 +.names $undef pcpi_insn[12] +1 1 +.names $undef pcpi_insn[13] +1 1 +.names $undef pcpi_insn[14] +1 1 +.names $undef pcpi_insn[15] +1 1 +.names $undef pcpi_insn[16] +1 1 +.names $undef pcpi_insn[17] +1 1 +.names $undef pcpi_insn[18] +1 1 +.names $undef pcpi_insn[19] +1 1 +.names $undef pcpi_insn[20] +1 1 +.names $undef pcpi_insn[21] +1 1 +.names $undef pcpi_insn[22] +1 1 +.names $undef pcpi_insn[23] +1 1 +.names $undef pcpi_insn[24] +1 1 +.names $undef pcpi_insn[25] +1 1 +.names $undef pcpi_insn[26] +1 1 +.names $undef pcpi_insn[27] +1 1 +.names $undef pcpi_insn[28] +1 1 +.names $undef pcpi_insn[29] +1 1 +.names $undef pcpi_insn[30] +1 1 +.names $undef pcpi_insn[31] +1 1 +.names mem_la_wdata[0] pcpi_rs2[0] +1 1 +.names mem_la_wdata[1] pcpi_rs2[1] +1 1 +.names mem_la_wdata[2] pcpi_rs2[2] +1 1 +.names mem_la_wdata[3] pcpi_rs2[3] +1 1 +.names mem_la_wdata[4] pcpi_rs2[4] +1 1 +.names mem_la_wdata[5] pcpi_rs2[5] +1 1 +.names mem_la_wdata[6] pcpi_rs2[6] +1 1 +.names mem_la_wdata[7] pcpi_rs2[7] +1 1 +.names $false pcpi_valid +1 1 +.names $undef trace_data[0] +1 1 +.names $undef trace_data[1] +1 1 +.names $undef trace_data[2] +1 1 +.names $undef trace_data[3] +1 1 +.names $undef trace_data[4] +1 1 +.names $undef trace_data[5] +1 1 +.names $undef trace_data[6] +1 1 +.names $undef trace_data[7] +1 1 +.names $undef trace_data[8] +1 1 +.names $undef trace_data[9] +1 1 +.names $undef trace_data[10] +1 1 +.names $undef trace_data[11] +1 1 +.names $undef trace_data[12] +1 1 +.names $undef trace_data[13] +1 1 +.names $undef trace_data[14] +1 1 +.names $undef trace_data[15] +1 1 +.names $undef trace_data[16] +1 1 +.names $undef trace_data[17] +1 1 +.names $undef trace_data[18] +1 1 +.names $undef trace_data[19] +1 1 +.names $undef trace_data[20] +1 1 +.names $undef trace_data[21] +1 1 +.names $undef trace_data[22] +1 1 +.names $undef trace_data[23] +1 1 +.names $undef trace_data[24] +1 1 +.names $undef trace_data[25] +1 1 +.names $undef trace_data[26] +1 1 +.names $undef trace_data[27] +1 1 +.names $undef trace_data[28] +1 1 +.names $undef trace_data[29] +1 1 +.names $undef trace_data[30] +1 1 +.names $undef trace_data[31] +1 1 +.names $undef trace_data[32] +1 1 +.names $undef trace_data[33] +1 1 +.names $undef trace_data[34] +1 1 +.names $undef trace_data[35] +1 1 +.names $false trace_valid +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/pong.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/pong.blif new file mode 100644 index 00000000000..6944f7510e3 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/pong.blif @@ -0,0 +1,1394 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model pong +.inputs clk quadA quadB +.outputs vga_h_sync vga_v_sync vga_R vga_G vga_B +.names $false +.names $true +1 +.names $undef +.names ballY[7] ball_dirY ballY[6] $abc$3008$new_n130 $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2661 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballY[5] $abc$3008$new_n131 ball_dirY ballY[4] $abc$3008$new_n130 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names ballY[4] ball_dirY ballY[3] $abc$3008$new_n132 $abc$3008$new_n131 +0100 1 +0110 1 +0111 1 +1010 1 +.names ball_dirY ballY[0] ballY[1] ballY[2] $abc$3008$new_n132 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names ResetCollision CollisionY2 CollisionY1 $abc$3008$new_n133 +100 1 +101 1 +110 1 +.names ballY[6] ball_dirY $abc$3008$new_n130 $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2663 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballY[5] ball_dirY $abc$3008$new_n131 $abc$3008$new_n133 ballY[4] $abc$3008$auto$rtlil.cc:2693:MuxGate$2665 +00110 1 +00111 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballY[4] ball_dirY ballY[3] $abc$3008$new_n132 $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2667 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballY[3] ball_dirY $abc$3008$new_n132 $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2669 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballY[2] ball_dirY ballY[0] ballY[1] $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2671 +00111 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballY[1] ball_dirY ballY[0] $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2673 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names ballY[0] $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2675 +01 1 +10 1 +.names ballX[8] ball_dirX $abc$3008$new_n142 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2677 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$3008$new_n146 ball_dirX ballX[6] ballX[7] $abc$3008$new_n143 $abc$3008$new_n142 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names ball_dirX ballX[4] ballX[5] $abc$3008$new_n144 $abc$3008$new_n143 +0110 1 +1000 1 +.names ball_dirX ballX[3] $abc$3008$new_n145 $abc$3008$new_n144 +000 1 +001 1 +011 1 +101 1 +.names ball_dirX ballX[0] ballX[1] ballX[2] $abc$3008$new_n145 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names ball_dirX ballX[5] ballX[4] $abc$3008$new_n146 +000 1 +001 1 +010 1 +011 1 +100 1 +.names ResetCollision CollisionX2 CollisionX1 $abc$3008$new_n147 +100 1 +101 1 +110 1 +.names ballX[7] ball_dirX ballX[6] $abc$3008$new_n149 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2679 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$3008$new_n146 $abc$3008$new_n143 $abc$3008$new_n149 +10 1 +.names ballX[6] ball_dirX $abc$3008$new_n149 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2681 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballX[5] ball_dirX ballX[4] $abc$3008$new_n144 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2683 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballX[4] ball_dirX $abc$3008$new_n144 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2685 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballX[3] ball_dirX $abc$3008$new_n145 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2687 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballX[2] ball_dirX ballX[0] ballX[1] $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2689 +00111 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballX[1] ball_dirX ballX[0] $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2691 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names ballX[0] $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2693 +01 1 +10 1 +.names CounterY[7] CounterY[4] CounterY[5] CounterY[6] $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2695 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names CounterY[0] CounterY[1] CounterY[2] CounterY[3] syncgen.CounterXmaxed $abc$3008$new_n158 +11111 1 +.names CounterX[7] $abc$3008$new_n162 $abc$3008$new_n160 syncgen.CounterXmaxed +111 1 +.names CounterX[6] CounterX[4] CounterX[5] $abc$3008$new_n161 $abc$3008$new_n160 +1111 1 +.names CounterX[1] CounterX[0] CounterX[2] CounterX[3] $abc$3008$new_n161 +1111 1 +.names CounterX[9] CounterX[8] $abc$3008$new_n162 +10 1 +.names CounterY[6] CounterY[4] CounterY[5] $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2697 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterY[5] CounterY[4] $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2699 +011 1 +100 1 +101 1 +110 1 +.names CounterY[4] $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2701 +01 1 +10 1 +.names CounterY[3] CounterY[0] CounterY[1] CounterY[2] syncgen.CounterXmaxed $abc$3008$auto$rtlil.cc:2693:MuxGate$2703 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names CounterY[2] CounterY[0] CounterY[1] syncgen.CounterXmaxed $abc$3008$auto$rtlil.cc:2693:MuxGate$2705 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterY[1] CounterY[0] syncgen.CounterXmaxed $abc$3008$auto$rtlil.cc:2693:MuxGate$2707 +011 1 +100 1 +101 1 +110 1 +.names CounterY[0] syncgen.CounterXmaxed $abc$3008$auto$rtlil.cc:2693:MuxGate$2709 +01 1 +10 1 +.names PaddlePosition[7] $abc$3008$new_n171 $abc$3008$new_n172 $abc$3008$new_n181 $abc$3008$new_n179 $abc$3008$auto$rtlil.cc:2693:MuxGate$2711 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names $abc$3008$new_n176 PaddlePosition[7] $abc$3008$new_n172 PaddlePosition[8] $abc$3008$new_n171 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$3008$new_n175 $abc$3008$new_n173 $abc$3008$new_n172 +11 1 +.names PaddlePosition[5] PaddlePosition[6] $abc$3008$new_n174 $abc$3008$new_n173 +111 1 +.names PaddlePosition[3] PaddlePosition[4] $abc$3008$new_n174 +11 1 +.names PaddlePosition[1] PaddlePosition[2] PaddlePosition[0] quadBr[1] quadAr[2] $abc$3008$new_n175 +11101 1 +11110 1 +.names quadBr[2] quadAr[1] quadBr[1] quadAr[2] $abc$3008$new_n177 $abc$3008$new_n176 +00000 1 +00001 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$3008$new_n178 PaddlePosition[8] PaddlePosition[0] PaddlePosition[1] PaddlePosition[2] $abc$3008$new_n177 +10000 1 +.names PaddlePosition[3] PaddlePosition[4] PaddlePosition[5] PaddlePosition[6] PaddlePosition[7] $abc$3008$new_n178 +00000 1 +.names $abc$3008$new_n180 PaddlePosition[5] PaddlePosition[6] $abc$3008$new_n179 +100 1 +.names PaddlePosition[3] PaddlePosition[4] $abc$3008$new_n180 +00 1 +.names quadBr[1] quadAr[2] PaddlePosition[0] PaddlePosition[1] PaddlePosition[2] $abc$3008$new_n181 +00000 1 +11000 1 +.names PaddlePosition[6] $abc$3008$new_n171 $abc$3008$new_n183 $abc$3008$auto$rtlil.cc:2693:MuxGate$2713 +010 1 +100 1 +101 1 +111 1 +.names PaddlePosition[3] PaddlePosition[4] PaddlePosition[5] $abc$3008$new_n175 $abc$3008$new_n181 $abc$3008$new_n183 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names PaddlePosition[5] $abc$3008$new_n185 $abc$3008$auto$rtlil.cc:2693:MuxGate$2715 +01 1 +10 1 +.names $abc$3008$new_n171 PaddlePosition[3] PaddlePosition[4] $abc$3008$new_n175 $abc$3008$new_n181 $abc$3008$new_n185 +10001 1 +10011 1 +11110 1 +11111 1 +.names PaddlePosition[4] PaddlePosition[3] $abc$3008$new_n171 $abc$3008$new_n181 $abc$3008$new_n175 $abc$3008$auto$rtlil.cc:2693:MuxGate$2717 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names PaddlePosition[3] $abc$3008$new_n171 $abc$3008$new_n181 $abc$3008$new_n175 $abc$3008$auto$rtlil.cc:2693:MuxGate$2719 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names PaddlePosition[2] $abc$3008$new_n189 $abc$3008$auto$rtlil.cc:2693:MuxGate$2721 +01 1 +10 1 +.names $abc$3008$new_n171 quadBr[1] quadAr[2] PaddlePosition[0] PaddlePosition[1] $abc$3008$new_n189 +10000 1 +10111 1 +11011 1 +11100 1 +.names PaddlePosition[1] quadBr[1] quadAr[2] PaddlePosition[0] $abc$3008$new_n171 $abc$3008$auto$rtlil.cc:2693:MuxGate$2723 +00001 1 +00111 1 +01011 1 +01101 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names PaddlePosition[0] $abc$3008$new_n171 $abc$3008$auto$rtlil.cc:2693:MuxGate$2725 +01 1 +10 1 +.names PaddlePosition[8] $abc$3008$new_n193 $abc$3008$auto$rtlil.cc:2693:MuxGate$2727 +01 1 +10 1 +.names $abc$3008$new_n171 $abc$3008$new_n194 quadBr[1] quadAr[2] PaddlePosition[7] $abc$3008$new_n193 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$3008$new_n172 $abc$3008$new_n178 PaddlePosition[1] PaddlePosition[2] PaddlePosition[0] $abc$3008$new_n194 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names ball_dirY ResetCollision CollisionY2 CollisionY1 $abc$3008$auto$rtlil.cc:2693:MuxGate$2731 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names ball_dirX ResetCollision CollisionX2 CollisionX1 $abc$3008$auto$rtlil.cc:2693:MuxGate$2735 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names ballX[9] ball_dirX ballX[8] $abc$3008$new_n142 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2739 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names CounterY[8] $abc$3008$new_n203 $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2741 +011 1 +100 1 +101 1 +110 1 +.names CounterY[4] CounterY[5] CounterY[6] CounterY[7] $abc$3008$new_n203 +1111 1 +.names CollisionY2 $abc$3008$new_n205 $abc$3008$new_n250 $abc$3008$auto$rtlil.cc:2693:MuxGate$2743 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$3008$new_n231 $abc$3008$new_n315 $abc$3008$new_n228 $abc$3008$new_n206 $abc$3008$new_n220 $abc$3008$new_n205 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$3008$new_n219 CounterX[7] $abc$3008$new_n208 $abc$3008$new_n207 $abc$3008$new_n218 $abc$3008$new_n206 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$3008$new_n179 PaddlePosition[7] $abc$3008$new_n207 +00 1 +11 1 +.names $abc$3008$new_n216 $abc$3008$new_n217 $abc$3008$new_n215 $abc$3008$new_n209 $abc$3008$new_n211 $abc$3008$new_n208 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names PaddlePosition[2] CounterX[2] CounterX[3] PaddlePosition[3] $abc$3008$new_n210 $abc$3008$new_n209 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names PaddlePosition[0] CounterX[0] CounterX[1] PaddlePosition[1] $abc$3008$new_n210 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$3008$new_n214 $abc$3008$new_n212 $abc$3008$new_n213 CounterX[0] PaddlePosition[0] $abc$3008$new_n211 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +.names CounterX[3] CounterX[2] PaddlePosition[2] PaddlePosition[3] $abc$3008$new_n212 +0001 1 +0111 1 +1000 1 +1110 1 +.names CounterX[1] PaddlePosition[1] $abc$3008$new_n213 +00 1 +11 1 +.names PaddlePosition[4] PaddlePosition[3] CounterX[4] $abc$3008$new_n214 +000 1 +110 1 +.names $abc$3008$new_n180 PaddlePosition[5] PaddlePosition[6] CounterX[6] CounterX[5] $abc$3008$new_n215 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01111 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names CounterX[6] PaddlePosition[6] $abc$3008$new_n180 PaddlePosition[5] $abc$3008$new_n216 +1000 1 +1001 1 +1011 1 +1110 1 +.names PaddlePosition[3] PaddlePosition[4] CounterX[5] PaddlePosition[5] CounterX[4] $abc$3008$new_n217 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01110 1 +10000 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names CounterX[8] PaddlePosition[8] PaddlePosition[7] $abc$3008$new_n179 $abc$3008$new_n218 +1000 1 +1001 1 +1011 1 +1110 1 +.names PaddlePosition[8] PaddlePosition[7] $abc$3008$new_n179 CounterX[8] CounterX[9] $abc$3008$new_n219 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$3008$new_n226 $abc$3008$new_n223 $abc$3008$new_n225 $abc$3008$new_n221 $abc$3008$new_n227 $abc$3008$new_n220 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$3008$new_n222 PaddlePosition[3] PaddlePosition[4] CounterX[4] $abc$3008$new_n209 $abc$3008$new_n221 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +.names CounterX[5] PaddlePosition[5] $abc$3008$new_n174 $abc$3008$new_n222 +100 1 +111 1 +.names PaddlePosition[6] $abc$3008$new_n224 CounterX[7] PaddlePosition[7] CounterX[6] $abc$3008$new_n223 +00000 1 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +.names PaddlePosition[5] $abc$3008$new_n174 $abc$3008$new_n224 +11 1 +.names PaddlePosition[7] $abc$3008$new_n173 PaddlePosition[8] CounterX[8] CounterX[7] $abc$3008$new_n225 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01111 1 +10001 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names CounterX[9] PaddlePosition[8] $abc$3008$new_n173 CounterX[8] $abc$3008$new_n226 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names PaddlePosition[5] $abc$3008$new_n174 PaddlePosition[6] CounterX[6] CounterX[5] $abc$3008$new_n227 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01111 1 +10001 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$3008$new_n230 $abc$3008$new_n229 $abc$3008$new_n228 +11 1 +.names CounterX[9] PaddlePosition[8] PaddlePosition[7] $abc$3008$new_n173 $abc$3008$new_n179 $abc$3008$new_n229 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +11100 1 +11110 1 +.names CounterY[8] CounterY[4] CounterY[5] CounterY[7] CounterY[6] $abc$3008$new_n230 +11110 1 +.names $abc$3008$new_n243 $abc$3008$new_n232 $abc$3008$new_n244 $abc$3008$new_n278 $abc$3008$new_n239 $abc$3008$new_n231 +11100 1 +.names $abc$3008$new_n235 $abc$3008$new_n237 ballX[3] CounterX[3] $abc$3008$new_n280 $abc$3008$new_n232 +11010 1 +11011 1 +11100 1 +.names ballX[4] ballX[5] ballX[6] ballX[7] $abc$3008$new_n234 +1111 1 +.names $abc$3008$new_n236 CounterX[1] ballX[1] $abc$3008$new_n235 +100 1 +111 1 +.names CounterX[0] ballX[0] CounterX[2] ballX[2] $abc$3008$new_n236 +0000 1 +0011 1 +1100 1 +1111 1 +.names ballX[3] $abc$3008$new_n238 CounterX[8] ballX[8] $abc$3008$new_n234 $abc$3008$new_n237 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names CounterX[4] ballX[4] $abc$3008$new_n238 +00 1 +11 1 +.names $abc$3008$new_n240 ballX[3] ballX[4] ballX[5] ballX[6] $abc$3008$new_n239 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +11111 1 +.names CounterX[7] ballX[7] $abc$3008$new_n240 +00 1 +11 1 +.names CounterX[6] ballX[6] ballX[3] ballX[4] ballX[5] $abc$3008$new_n243 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names CounterX[5] ballX[5] ballX[3] ballX[4] $abc$3008$new_n244 +0000 1 +0001 1 +0010 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterX[8] CounterX[7] $abc$3008$new_n246 +00 1 +.names CounterX[6] CounterX[4] CounterX[5] CounterX[3] CounterX[9] $abc$3008$new_n247 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$3008$new_n251 $abc$3008$new_n260 $abc$3008$new_n257 $abc$3008$new_n259 $abc$3008$new_n250 +1001 1 +1110 1 +1111 1 +.names $abc$3008$new_n252 $abc$3008$new_n255 CounterY[8] ballY[8] $abc$3008$new_n256 $abc$3008$new_n251 +11000 1 +11101 1 +11110 1 +.names $abc$3008$new_n253 CounterY[3] ballY[3] $abc$3008$new_n252 +100 1 +111 1 +.names $abc$3008$new_n254 CounterY[0] ballY[0] $abc$3008$new_n253 +100 1 +111 1 +.names CounterY[1] ballY[1] CounterY[2] ballY[2] $abc$3008$new_n254 +0000 1 +0011 1 +1100 1 +1111 1 +.names CounterY[4] CounterY[5] ballY[4] ballY[5] $abc$3008$new_n255 +0011 1 +0110 1 +1000 1 +1101 1 +.names ballY[4] ballY[5] ballY[6] ballY[7] $abc$3008$new_n256 +1111 1 +.names $abc$3008$new_n258 CounterY[7] ballY[7] $abc$3008$new_n259 $abc$3008$new_n257 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ballY[6] CounterY[6] $abc$3008$new_n258 +10 1 +.names ballY[4] ballY[5] $abc$3008$new_n259 +11 1 +.names CounterY[7] ballY[7] CounterY[6] ballY[6] $abc$3008$new_n260 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names CollisionY1 $abc$3008$new_n205 $abc$3008$new_n262 $abc$3008$auto$rtlil.cc:2693:MuxGate$2745 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$3008$new_n252 $abc$3008$new_n263 CounterY[8] ballY[8] $abc$3008$new_n258 $abc$3008$new_n262 +11000 1 +11110 1 +.names $abc$3008$new_n260 CounterY[4] ballY[4] CounterY[5] ballY[5] $abc$3008$new_n263 +10000 1 +10011 1 +11100 1 +11111 1 +.names CollisionX2 $abc$3008$new_n324 $abc$3008$new_n326 $abc$3008$auto$rtlil.cc:2693:MuxGate$2747 +011 1 +100 1 +101 1 +110 1 +111 1 +.names CounterY[8] ballY[8] CounterY[4] ballY[4] $abc$3008$new_n258 $abc$3008$new_n271 +00000 1 +00110 1 +11000 1 +11110 1 +.names $abc$3008$new_n255 CounterY[5] ballY[5] ballY[3] $abc$3008$new_n272 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names $abc$3008$new_n235 CounterX[3] ballX[3] $abc$3008$new_n274 +100 1 +111 1 +.names ballX[9] CounterX[9] ballX[8] CounterX[8] $abc$3008$new_n278 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names CounterX[4] CounterX[5] ballX[4] ballX[5] $abc$3008$new_n279 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$3008$new_n234 CounterX[9] ballX[9] CounterX[8] ballX[8] $abc$3008$new_n280 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11111 1 +.names CollisionX1 $abc$3008$new_n324 $abc$3008$new_n283 $abc$3008$auto$rtlil.cc:2693:MuxGate$2749 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$3008$new_n284 $abc$3008$new_n274 $abc$3008$new_n238 CounterX[9] ballX[9] $abc$3008$new_n283 +11100 1 +11111 1 +.names $abc$3008$new_n285 $abc$3008$new_n240 CounterX[5] ballX[5] $abc$3008$new_n284 +1100 1 +1111 1 +.names ballX[6] CounterX[6] CounterX[8] ballX[8] $abc$3008$new_n285 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$3008$new_n287 $abc$3008$new_n203 $abc$3008$eq$./benchmark/pong.v:56$43_Y +11 1 +.names CounterY[8] CounterY[2] CounterY[0] CounterY[1] CounterY[3] $abc$3008$new_n287 +11000 1 +.names CounterX[7] CounterX[6] CounterX[4] $abc$3008$new_n162 CounterX[5] $abc$3008$flatten\syncgen.$0\vga_HS[0:0] +11110 1 +.names inDisplayArea CounterX[7] $abc$3008$new_n162 $abc$3008$new_n160 $abc$3008$new_n290 $abc$3008$flatten\syncgen.$0\inDisplayArea[0:0] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names CounterY[8] CounterY[5] CounterY[6] CounterY[7] $abc$3008$new_n290 +1111 1 +.names ball_inY $abc$3008$new_n250 $abc$3008$new_n262 $0\ball_inY[0:0] +001 1 +011 1 +100 1 +101 1 +.names ball_inX $abc$3008$new_n326 ball_inY $abc$3008$new_n283 $0\ball_inX[0:0] +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$3008$new_n294 $abc$3008$eq$./benchmark/pong.v:56$43_Y $0\ResetCollision[0:0] +11 1 +.names $abc$3008$new_n246 $abc$3008$new_n295 CounterX[1] CounterX[0] CounterX[2] $abc$3008$new_n294 +11000 1 +.names CounterX[6] CounterX[4] CounterX[5] CounterX[3] CounterX[9] $abc$3008$new_n295 +00000 1 +.names inDisplayArea $abc$3008$new_n297 $abc$3008$new_n298 ball_inX ball_inY $0\vga_R[0:0] +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$3008$new_n315 $abc$3008$new_n228 $abc$3008$new_n206 $abc$3008$new_n220 $abc$3008$new_n297 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names CounterX[3] CounterY[3] $abc$3008$new_n298 +00 1 +11 1 +.names inDisplayArea $abc$3008$new_n297 ball_inX ball_inY $0\vga_B[0:0] +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names CounterX[1] CounterX[0] $auto$alumacc.cc:485:replace_alu$666.Y[1] +01 1 +10 1 +.names CounterX[2] CounterX[1] CounterX[0] $auto$alumacc.cc:485:replace_alu$666.Y[2] +011 1 +100 1 +101 1 +110 1 +.names CounterX[3] CounterX[1] CounterX[0] CounterX[2] $auto$alumacc.cc:485:replace_alu$666.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterX[4] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[4] +01 1 +10 1 +.names CounterX[5] CounterX[4] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[5] +011 1 +100 1 +101 1 +110 1 +.names CounterX[6] CounterX[4] CounterX[5] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[6] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[7] +01 1 +10 1 +.names CounterX[8] CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[8] +011 1 +100 1 +101 1 +110 1 +.names CounterX[9] CounterX[8] CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[9] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterX[0] $auto$alumacc.cc:485:replace_alu$666.X[0] +0 1 +.names syncgen.vga_VS vga_v_sync +0 1 +.names syncgen.vga_HS vga_h_sync +0 1 +.names $abc$3008$new_n133 ball_dirY ballY[5] ballY[6] ballY[7] $abc$3008$new_n312 +10111 1 +11000 1 +.names ballY[8] $abc$3008$new_n131 $abc$3008$new_n312 ballY[4] ballY[7] $abc$3008$auto$rtlil.cc:2693:MuxGate$2737 +00100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names CounterY[8] CounterY[3] CounterY[4] CounterY[6] CounterY[7] $abc$3008$new_n314 +00000 1 +11111 1 +.names $abc$3008$new_n314 CounterY[5] $abc$3008$new_n246 $abc$3008$new_n247 $abc$3008$new_n315 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names ballY[3] CounterY[3] CounterY[8] ballY[8] $abc$3008$new_n256 $abc$3008$new_n316 +01000 1 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10101 1 +10110 1 +.names $abc$3008$new_n240 CounterX[6] ballX[6] ballX[4] ballX[5] $abc$3008$new_n319 +00111 1 +10000 1 +10001 1 +10010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names ballY[3] $abc$3008$new_n260 $abc$3008$new_n257 $abc$3008$new_n271 $abc$3008$new_n259 $abc$3008$new_n322 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$3008$new_n316 $abc$3008$new_n322 $abc$3008$new_n253 $abc$3008$new_n272 $abc$3008$new_n323 +1110 1 +.names $abc$3008$new_n323 $abc$3008$new_n315 $abc$3008$new_n228 $abc$3008$new_n220 $abc$3008$new_n206 $abc$3008$new_n324 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names CounterX[8] $abc$3008$new_n234 CounterX[9] ballX[9] ballX[8] $abc$3008$new_n325 +00000 1 +00110 1 +01101 1 +10001 1 +10111 1 +11000 1 +11110 1 +.names $abc$3008$new_n319 $abc$3008$new_n325 $abc$3008$new_n274 $abc$3008$new_n279 $abc$3008$new_n326 +1110 1 +.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2743 Q=CollisionY2 R=ResetCollision +.subckt dff C=clk D=$abc$3008$eq$./benchmark/pong.v:56$43_Y Q=syncgen.vga_VS +.subckt dff C=clk D=$abc$3008$flatten\syncgen.$0\vga_HS[0:0] Q=syncgen.vga_HS +.subckt dff C=clk D=$abc$3008$flatten\syncgen.$0\inDisplayArea[0:0] Q=inDisplayArea +.subckt dff C=clk D=$0\vga_R[0:0] Q=vga_R +.subckt dff C=clk D=$0\vga_B[0:0] Q=vga_B +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2709 Q=CounterY[0] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2707 Q=CounterY[1] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2705 Q=CounterY[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2703 Q=CounterY[3] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2701 Q=CounterY[4] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2699 Q=CounterY[5] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2697 Q=CounterY[6] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2695 Q=CounterY[7] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2741 Q=CounterY[8] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2693 Q=ballX[0] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2691 Q=ballX[1] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2689 Q=ballX[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2687 Q=ballX[3] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2685 Q=ballX[4] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2683 Q=ballX[5] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2681 Q=ballX[6] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2679 Q=ballX[7] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2677 Q=ballX[8] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2739 Q=ballX[9] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2735 Q=ball_dirX +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2731 Q=ball_dirY +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.X[0] Q=CounterX[0] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[1] Q=CounterX[1] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[2] Q=CounterX[2] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[3] Q=CounterX[3] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[4] Q=CounterX[4] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[5] Q=CounterX[5] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[6] Q=CounterX[6] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[7] Q=CounterX[7] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[8] Q=CounterX[8] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[9] Q=CounterX[9] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2745 Q=CollisionY1 R=ResetCollision +.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2747 Q=CollisionX2 R=ResetCollision +.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2749 Q=CollisionX1 R=ResetCollision +.subckt dff C=clk D=$0\ResetCollision[0:0] Q=ResetCollision +.subckt dff C=clk D=$0\ball_inY[0:0] Q=ball_inY +.subckt dff C=clk D=$0\ball_inX[0:0] Q=ball_inX +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2675 Q=ballY[0] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2673 Q=ballY[1] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2671 Q=ballY[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2669 Q=ballY[3] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2667 Q=ballY[4] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2665 Q=ballY[5] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2663 Q=ballY[6] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2661 Q=ballY[7] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2737 Q=ballY[8] +.subckt dff C=clk D=quadB Q=quadBr[0] +.subckt dff C=clk D=quadBr[0] Q=quadBr[1] +.subckt dff C=clk D=quadBr[1] Q=quadBr[2] +.subckt dff C=clk D=quadA Q=quadAr[0] +.subckt dff C=clk D=quadAr[0] Q=quadAr[1] +.subckt dff C=clk D=quadAr[1] Q=quadAr[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2725 Q=PaddlePosition[0] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2723 Q=PaddlePosition[1] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2721 Q=PaddlePosition[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2719 Q=PaddlePosition[3] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2717 Q=PaddlePosition[4] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2715 Q=PaddlePosition[5] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2713 Q=PaddlePosition[6] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2711 Q=PaddlePosition[7] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2727 Q=PaddlePosition[8] +.names $auto$alumacc.cc:485:replace_alu$666.X[0] $auto$alumacc.cc:485:replace_alu$666.Y[0] +1 1 +.names CounterX[1] $auto$alumacc.cc:485:replace_alu$666.X[1] +1 1 +.names CounterX[2] $auto$alumacc.cc:485:replace_alu$666.X[2] +1 1 +.names CounterX[3] $auto$alumacc.cc:485:replace_alu$666.X[3] +1 1 +.names CounterX[4] $auto$alumacc.cc:485:replace_alu$666.X[4] +1 1 +.names CounterX[5] $auto$alumacc.cc:485:replace_alu$666.X[5] +1 1 +.names CounterX[6] $auto$alumacc.cc:485:replace_alu$666.X[6] +1 1 +.names CounterX[7] $auto$alumacc.cc:485:replace_alu$666.X[7] +1 1 +.names CounterX[8] $auto$alumacc.cc:485:replace_alu$666.X[8] +1 1 +.names CounterX[9] $auto$alumacc.cc:485:replace_alu$666.X[9] +1 1 +.names vga_B vga_G +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif new file mode 100644 index 00000000000..c6ffa8f4984 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif @@ -0,0 +1,135 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model quad +.inputs clk quadA quadB +.outputs count[0] count[1] count[2] count[3] count[4] count[5] count[6] count[7] +.names $false +.names $true +1 +.names $undef +.names count[6] $abc$833$new_n27 $abc$833$new_n25 $abc$833$new_n23 $abc$833$auto$rtlil.cc:2693:MuxGate$715 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names count[3] count[4] count[5] $abc$833$new_n24 $abc$833$new_n23 +1111 1 +.names count[1] count[2] count[0] quadB_delayed[2] quadA_delayed[1] $abc$833$new_n24 +11101 1 +11110 1 +.names $abc$833$new_n26 count[3] count[4] count[5] $abc$833$new_n25 +1000 1 +.names quadB_delayed[2] quadA_delayed[1] count[0] count[1] count[2] $abc$833$new_n26 +00000 1 +11000 1 +.names quadB_delayed[2] quadB_delayed[1] quadA_delayed[2] quadA_delayed[1] $abc$833$new_n27 +0001 1 +0010 1 +0100 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names count[5] $abc$833$new_n29 $abc$833$auto$rtlil.cc:2693:MuxGate$717 +01 1 +10 1 +.names $abc$833$new_n27 count[3] count[4] $abc$833$new_n24 $abc$833$new_n26 $abc$833$new_n29 +10001 1 +10011 1 +11110 1 +11111 1 +.names count[4] count[3] $abc$833$new_n27 $abc$833$new_n26 $abc$833$new_n24 $abc$833$auto$rtlil.cc:2693:MuxGate$719 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names count[3] $abc$833$new_n27 $abc$833$new_n26 $abc$833$new_n24 $abc$833$auto$rtlil.cc:2693:MuxGate$721 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names count[2] count[0] count[1] $abc$833$new_n33 $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$723 +00011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names quadB_delayed[2] quadA_delayed[1] $abc$833$new_n33 +00 1 +11 1 +.names count[1] count[0] $abc$833$new_n33 $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$725 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names count[0] $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$727 +01 1 +10 1 +.names count[7] count[6] $abc$833$new_n27 $abc$833$new_n25 $abc$833$new_n23 $abc$833$auto$rtlil.cc:2693:MuxGate$729 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$727 Q=count[0] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$725 Q=count[1] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$723 Q=count[2] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$721 Q=count[3] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$719 Q=count[4] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$717 Q=count[5] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$715 Q=count[6] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$729 Q=count[7] +.subckt dff C=clk D=quadB Q=quadB_delayed[0] +.subckt dff C=clk D=quadB_delayed[0] Q=quadB_delayed[1] +.subckt dff C=clk D=quadB_delayed[1] Q=quadB_delayed[2] +.subckt dff C=clk D=quadA Q=quadA_delayed[0] +.subckt dff C=clk D=quadA_delayed[0] Q=quadA_delayed[1] +.subckt dff C=clk D=quadA_delayed[1] Q=quadA_delayed[2] +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif new file mode 100644 index 00000000000..51d0c4d3cdb --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif @@ -0,0 +1,4862 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model seqcordic +.inputs i_clk i_reset i_stb i_aux i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_phase[0] i_phase[1] i_phase[2] i_phase[3] i_phase[4] i_phase[5] i_phase[6] i_phase[7] i_phase[8] i_phase[9] i_phase[10] i_phase[11] i_phase[12] i_phase[13] i_phase[14] i_phase[15] i_phase[16] i_phase[17] i_phase[18] i_phase[19] +.outputs o_busy o_done o_xval[0] o_xval[1] o_xval[2] o_xval[3] o_xval[4] o_xval[5] o_xval[6] o_xval[7] o_xval[8] o_xval[9] o_xval[10] o_xval[11] o_xval[12] o_yval[0] o_yval[1] o_yval[2] o_yval[3] o_yval[4] o_yval[5] o_yval[6] o_yval[7] o_yval[8] o_yval[9] o_yval[10] o_yval[11] o_yval[12] o_aux +.names $false +.names $true +1 +.names $undef +.names state[1] state[3] state[2] state[0] $auto$alumacc.cc:485:replace_alu$688.CO[3] +1111 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[14] $abc$4039$new_n329 o_yval[11] $abc$4039$auto$rtlil.cc:2693:MuxGate$3820 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[13] yv[12] $abc$4039$new_n330 $abc$4039$new_n329 +111 1 +.names yv[11] yv[10] $abc$4039$new_n331 $abc$4039$new_n330 +111 1 +.names yv[9] yv[8] $abc$4039$new_n332 $abc$4039$new_n331 +111 1 +.names yv[7] $abc$4039$new_n333 $abc$4039$new_n332 +11 1 +.names yv[6] yv[5] yv[4] $abc$4039$new_n334 $abc$4039$new_n333 +1111 1 +.names yv[2] yv[3] $abc$4039$new_n334 +11 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[13] yv[12] $abc$4039$new_n330 o_yval[10] $abc$4039$auto$rtlil.cc:2693:MuxGate$3822 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[12] $abc$4039$new_n330 o_yval[9] $abc$4039$auto$rtlil.cc:2693:MuxGate$3824 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[11] yv[10] $abc$4039$new_n331 o_yval[8] $abc$4039$auto$rtlil.cc:2693:MuxGate$3826 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[10] $abc$4039$new_n331 o_yval[7] $abc$4039$auto$rtlil.cc:2693:MuxGate$3828 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[9] yv[8] $abc$4039$new_n332 o_yval[6] $abc$4039$auto$rtlil.cc:2693:MuxGate$3830 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[8] $abc$4039$new_n332 o_yval[5] $abc$4039$auto$rtlil.cc:2693:MuxGate$3832 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[7] $abc$4039$new_n333 o_yval[4] $abc$4039$auto$rtlil.cc:2693:MuxGate$3834 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n343 o_yval[3] $abc$4039$auto$rtlil.cc:2693:MuxGate$3836 +001 1 +011 1 +110 1 +111 1 +.names yv[6] yv[5] yv[4] $abc$4039$new_n334 $abc$4039$new_n343 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[5] yv[4] $abc$4039$new_n334 o_yval[2] $abc$4039$auto$rtlil.cc:2693:MuxGate$3838 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[4] $abc$4039$new_n334 o_yval[1] $abc$4039$auto$rtlil.cc:2693:MuxGate$3840 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n347 o_yval[0] $abc$4039$auto$rtlil.cc:2693:MuxGate$3842 +001 1 +011 1 +110 1 +111 1 +.names yv[2] yv[3] yv[0] yv[1] $abc$4039$new_n347 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[14] xv[13] $abc$4039$new_n349 o_xval[11] $abc$4039$auto$rtlil.cc:2693:MuxGate$3844 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[12] xv[11] $abc$4039$new_n350 $abc$4039$new_n349 +111 1 +.names xv[10] xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n350 +11111 1 +.names xv[6] xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n351 +11111 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[13] $abc$4039$new_n349 o_xval[10] $abc$4039$auto$rtlil.cc:2693:MuxGate$3846 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[12] xv[11] $abc$4039$new_n350 o_xval[9] $abc$4039$auto$rtlil.cc:2693:MuxGate$3848 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[11] $abc$4039$new_n350 o_xval[8] $abc$4039$auto$rtlil.cc:2693:MuxGate$3850 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n356 o_xval[7] $abc$4039$auto$rtlil.cc:2693:MuxGate$3852 +001 1 +011 1 +110 1 +111 1 +.names xv[10] xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n356 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n358 o_xval[6] $abc$4039$auto$rtlil.cc:2693:MuxGate$3854 +001 1 +011 1 +110 1 +111 1 +.names xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n358 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[8] xv[7] $abc$4039$new_n351 o_xval[5] $abc$4039$auto$rtlil.cc:2693:MuxGate$3856 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[7] $abc$4039$new_n351 o_xval[4] $abc$4039$auto$rtlil.cc:2693:MuxGate$3858 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n362 o_xval[3] $abc$4039$auto$rtlil.cc:2693:MuxGate$3860 +001 1 +011 1 +110 1 +111 1 +.names xv[6] xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n362 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n364 o_xval[2] $abc$4039$auto$rtlil.cc:2693:MuxGate$3862 +001 1 +011 1 +110 1 +111 1 +.names xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n364 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[4] xv[2] xv[3] o_xval[1] $abc$4039$auto$rtlil.cc:2693:MuxGate$3864 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n367 o_xval[0] $abc$4039$auto$rtlil.cc:2693:MuxGate$3866 +001 1 +011 1 +110 1 +111 1 +.names xv[2] xv[3] xv[0] xv[1] $abc$4039$new_n367 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] aux o_aux $abc$4039$auto$rtlil.cc:2693:MuxGate$3868 +001 1 +011 1 +110 1 +111 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[15] yv[14] $abc$4039$new_n329 o_yval[12] $abc$4039$auto$rtlil.cc:2693:MuxGate$3870 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n371 o_xval[12] $abc$4039$auto$rtlil.cc:2693:MuxGate$3872 +001 1 +011 1 +110 1 +111 1 +.names xv[15] xv[14] xv[13] $abc$4039$new_n349 $abc$4039$new_n371 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_stb $auto$alumacc.cc:485:replace_alu$688.CO[3] idle $abc$4039$auto$rtlil.cc:2693:MuxGate$3874 +001 1 +010 1 +011 1 +.names i_stb idle $abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y +11 1 +.names $abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y i_aux aux $abc$4039$auto$rtlil.cc:2693:MuxGate$3876 +001 1 +011 1 +110 1 +111 1 +.names state[3] state[2] $abc$4039$auto$opt_dff.cc:253:combine_resets$910 +01 1 +10 1 +11 1 +.names state[1] $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$auto$opt_dff.cc:253:combine_resets$907 +00 1 +01 1 +11 1 +.names i_reset idle $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$auto$opt_dff.cc:253:combine_resets$636 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$4039$auto$rtlil.cc:2516:Or$645 +000 1 +101 1 +110 1 +111 1 +.names $abc$4039$new_n381 $abc$4039$new_n380 i_xval[0] i_yval[0] $0\prex[15:0][2] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names i_phase[18] i_phase[17] i_phase[19] $abc$4039$new_n380 +000 1 +111 1 +.names i_phase[18] i_phase[17] i_phase[19] $abc$4039$new_n381 +001 1 +110 1 +.names $abc$4039$new_n383 i_xval[1] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[1] $0\prex[15:0][3] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[1] i_yval[0] $abc$4039$new_n384 $abc$4039$new_n383 +00010 1 +00011 1 +00100 1 +00101 1 +10001 1 +10011 1 +10101 1 +10111 1 +.names i_xval[1] i_xval[0] $abc$4039$new_n384 +01 1 +10 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$4039$new_n385 +101 1 +110 1 +.names $abc$4039$new_n387 i_xval[2] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[2] $0\prex[15:0][4] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n388 $abc$4039$new_n389 $abc$4039$new_n387 +0001 1 +0011 1 +1010 1 +1011 1 +.names i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n388 +001 1 +010 1 +011 1 +100 1 +.names i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n389 +001 1 +010 1 +011 1 +100 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n391 $abc$4039$new_n393 $abc$4039$new_n392 $0\prex[15:0][5] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_xval[3] $abc$4039$new_n380 i_yval[3] $abc$4039$new_n385 $abc$4039$new_n391 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n392 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n393 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names $abc$4039$new_n381 $abc$4039$new_n395 $abc$4039$new_n397 $abc$4039$new_n396 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][6] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[4] $abc$4039$new_n380 i_yval[4] $abc$4039$new_n385 $abc$4039$new_n395 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n396 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n397 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names $abc$4039$new_n399 i_xval[5] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[5] $0\prex[15:0][7] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[5] $abc$4039$new_n402 $abc$4039$new_n400 $abc$4039$new_n399 +00000 1 +00001 1 +00110 1 +00111 1 +10001 1 +10011 1 +10101 1 +10111 1 +.names i_xval[5] $abc$4039$new_n401 $abc$4039$new_n400 +00 1 +11 1 +.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n401 +00000 1 +.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n402 +00000 1 +.names $abc$4039$new_n381 $abc$4039$new_n405 $abc$4039$new_n406 $abc$4039$new_n404 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][8] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[6] $abc$4039$new_n402 i_yval[5] $abc$4039$new_n404 +000 1 +001 1 +011 1 +110 1 +.names i_xval[6] $abc$4039$new_n380 i_yval[6] $abc$4039$new_n385 $abc$4039$new_n405 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[6] $abc$4039$new_n401 i_xval[5] $abc$4039$new_n406 +000 1 +001 1 +011 1 +110 1 +.names $abc$4039$new_n381 $abc$4039$new_n409 $abc$4039$new_n410 $abc$4039$new_n408 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][9] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[7] $abc$4039$new_n402 i_yval[6] i_yval[5] $abc$4039$new_n408 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_xval[7] $abc$4039$new_n380 i_yval[7] $abc$4039$new_n385 $abc$4039$new_n409 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[7] $abc$4039$new_n401 i_xval[6] i_xval[5] $abc$4039$new_n410 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$4039$new_n381 $abc$4039$new_n413 $abc$4039$new_n414 $abc$4039$new_n412 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][10] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[8] $abc$4039$new_n402 i_yval[7] i_yval[6] i_yval[5] $abc$4039$new_n412 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names i_xval[8] $abc$4039$new_n380 i_yval[8] $abc$4039$new_n385 $abc$4039$new_n413 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[8] $abc$4039$new_n401 i_xval[7] i_xval[6] i_xval[5] $abc$4039$new_n414 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names $abc$4039$new_n416 i_xval[9] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[9] $0\prex[15:0][11] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_xval[9] $abc$4039$new_n419 $abc$4039$new_n417 $abc$4039$new_n416 +00001 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10110 1 +10111 1 +.names i_yval[9] $abc$4039$new_n418 $abc$4039$new_n417 +00 1 +11 1 +.names $abc$4039$new_n402 i_yval[8] i_yval[7] i_yval[6] i_yval[5] $abc$4039$new_n418 +10000 1 +.names $abc$4039$new_n401 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$4039$new_n419 +10000 1 +.names $abc$4039$new_n381 $abc$4039$new_n423 $abc$4039$new_n422 $abc$4039$new_n421 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][12] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[10] $abc$4039$new_n418 i_yval[9] $abc$4039$new_n421 +000 1 +001 1 +011 1 +110 1 +.names i_xval[10] $abc$4039$new_n419 i_xval[9] $abc$4039$new_n422 +000 1 +001 1 +011 1 +110 1 +.names i_xval[10] $abc$4039$new_n380 i_yval[10] $abc$4039$new_n385 $abc$4039$new_n423 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$new_n427 $abc$4039$new_n426 $abc$4039$new_n425 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][13] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[11] $abc$4039$new_n418 i_yval[10] i_yval[9] $abc$4039$new_n425 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_xval[11] $abc$4039$new_n419 i_xval[10] i_xval[9] $abc$4039$new_n426 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_xval[11] $abc$4039$new_n380 i_yval[11] $abc$4039$new_n385 $abc$4039$new_n427 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n433 i_yval[12] $abc$4039$new_n432 $abc$4039$new_n381 $abc$4039$new_n429 $0\prex[15:0][14] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n381 $abc$4039$new_n430 $abc$4039$new_n431 $abc$4039$new_n429 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names i_xval[12] $abc$4039$new_n419 i_xval[10] i_xval[9] i_xval[11] $abc$4039$new_n430 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_xval[12] $abc$4039$new_n419 i_xval[11] i_xval[10] i_xval[9] $abc$4039$new_n431 +11000 1 +.names $abc$4039$new_n418 i_yval[11] i_yval[10] i_yval[9] $abc$4039$new_n432 +1000 1 +.names i_xval[12] $abc$4039$new_n380 i_yval[12] $abc$4039$new_n385 $abc$4039$new_n433 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n433 $abc$4039$new_n435 $abc$4039$new_n430 $0\prex[15:0][15] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_yval[12] $abc$4039$new_n432 $abc$4039$new_n435 +00 1 +.names $abc$4039$new_n381 $abc$4039$new_n380 i_yval[0] i_xval[0] $0\prey[15:0][2] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n380 $abc$4039$new_n438 i_yval[1] $abc$4039$new_n384 $0\prey[15:0][3] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[1] i_yval[0] i_xval[1] $abc$4039$new_n438 +00001 1 +00011 1 +00101 1 +00111 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n381 $abc$4039$new_n440 $abc$4039$new_n389 i_xval[2] $0\prey[15:0][4] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n380 i_yval[2] $abc$4039$new_n388 $abc$4039$new_n440 +000 1 +010 1 +100 1 +101 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n442 $abc$4039$new_n392 i_xval[3] $0\prey[15:0][5] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_yval[3] $abc$4039$new_n380 $abc$4039$new_n385 $abc$4039$new_n393 $abc$4039$new_n442 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n444 $abc$4039$new_n396 i_xval[4] $0\prey[15:0][6] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_yval[4] $abc$4039$new_n380 $abc$4039$new_n385 $abc$4039$new_n397 $abc$4039$new_n444 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n446 $abc$4039$new_n385 $abc$4039$new_n400 $abc$4039$new_n380 i_yval[5] $0\prey[15:0][7] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[5] $abc$4039$new_n402 i_xval[5] $abc$4039$new_n446 +00001 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10110 1 +10111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n448 $abc$4039$new_n404 i_xval[6] $0\prey[15:0][8] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n406 i_yval[6] $abc$4039$new_n380 $abc$4039$new_n448 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n450 $abc$4039$new_n408 i_xval[7] $0\prey[15:0][9] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n410 i_yval[7] $abc$4039$new_n380 $abc$4039$new_n450 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n452 $abc$4039$new_n412 i_xval[8] $0\prey[15:0][10] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n414 i_yval[8] $abc$4039$new_n380 $abc$4039$new_n452 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n454 $abc$4039$new_n417 i_xval[9] $0\prey[15:0][11] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n419 i_xval[9] i_yval[9] $abc$4039$new_n380 $abc$4039$new_n454 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n456 $abc$4039$new_n421 i_xval[10] $0\prey[15:0][12] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n422 i_yval[10] $abc$4039$new_n380 $abc$4039$new_n456 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n458 $abc$4039$new_n385 $abc$4039$new_n426 $abc$4039$new_n380 i_yval[11] $0\prey[15:0][13] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_phase[18] i_phase[17] i_phase[19] i_xval[11] $abc$4039$new_n425 $abc$4039$new_n458 +00101 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11011 1 +.names $abc$4039$new_n462 $0\prey[15:0][15] $0\prey[15:0][14] +00 1 +01 1 +11 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n461 $abc$4039$new_n435 i_xval[12] $0\prey[15:0][15] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n430 i_yval[12] $abc$4039$new_n380 $abc$4039$new_n461 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n431 $abc$4039$new_n385 $abc$4039$new_n381 i_yval[12] $abc$4039$new_n432 $abc$4039$new_n462 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[15] +10 1 +.names state[2] state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[9] +000 1 +010 1 +110 1 +111 1 +.names state[2] state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[10] +000 1 +010 1 +100 1 +101 1 +.names state[1] state[2] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[11] +000 1 +001 1 +011 1 +101 1 +.names state[1] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[6] +00 1 +.names state[1] state[2] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[12] +001 1 +010 1 +100 1 +.names state[1] state[0] $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] +00 1 +11 1 +.names pre_valid ph[0] cangle[0] preph[0] $0\ph[19:0][0] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names pre_valid $abc$4039$new_n472 preph[1] $0\ph[19:0][1] +010 1 +011 1 +101 1 +111 1 +.names ph[1] cangle[1] ph[0] ph[19] cangle[0] $abc$4039$new_n472 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names pre_valid ph[2] cangle[2] $abc$4039$new_n474 preph[2] $0\ph[19:0][2] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n475 $abc$4039$new_n476 $abc$4039$new_n474 +000 1 +001 1 +101 1 +111 1 +.names cangle[0] ph[0] ph[1] cangle[1] $abc$4039$new_n475 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names cangle[0] ph[0] ph[1] cangle[1] $abc$4039$new_n476 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names pre_valid ph[3] cangle[3] $abc$4039$new_n478 preph[3] $0\ph[19:0][3] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[2] ph[19] cangle[2] $abc$4039$new_n476 $abc$4039$new_n475 $abc$4039$new_n478 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +.names pre_valid $abc$4039$new_n480 preph[4] $0\ph[19:0][4] +010 1 +011 1 +101 1 +111 1 +.names ph[19] ph[4] cangle[4] $abc$4039$new_n482 $abc$4039$new_n481 $abc$4039$new_n480 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names cangle[2] ph[2] ph[3] cangle[3] $abc$4039$new_n475 $abc$4039$new_n481 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names ph[2] cangle[2] ph[3] cangle[3] $abc$4039$new_n476 $abc$4039$new_n482 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pre_valid ph[5] cangle[5] $abc$4039$new_n484 preph[5] $0\ph[19:0][5] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[4] ph[19] cangle[4] $abc$4039$new_n482 $abc$4039$new_n481 $abc$4039$new_n484 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +.names pre_valid ph[6] cangle[6] $abc$4039$new_n486 preph[6] $0\ph[19:0][6] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] ph[5] cangle[5] $abc$4039$new_n487 $abc$4039$new_n488 $abc$4039$new_n486 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names ph[4] cangle[4] $abc$4039$new_n482 $abc$4039$new_n487 +000 1 +001 1 +011 1 +101 1 +.names cangle[4] ph[4] ph[5] cangle[5] $abc$4039$new_n481 $abc$4039$new_n488 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pre_valid ph[7] cangle[7] $abc$4039$new_n490 preph[7] $0\ph[19:0][7] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] ph[6] cangle[6] $abc$4039$new_n488 $abc$4039$new_n491 $abc$4039$new_n490 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[5] cangle[5] ph[6] cangle[6] $abc$4039$new_n487 $abc$4039$new_n491 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pre_valid $abc$4039$new_n493 preph[8] $0\ph[19:0][8] +000 1 +001 1 +101 1 +111 1 +.names ph[8] cangle[8] ph[19] $abc$4039$new_n495 $abc$4039$new_n494 $abc$4039$new_n493 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names ph[7] cangle[7] $abc$4039$new_n491 $abc$4039$new_n494 +000 1 +001 1 +011 1 +101 1 +.names cangle[6] ph[6] ph[7] cangle[7] $abc$4039$new_n488 $abc$4039$new_n495 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pre_valid ph[9] cangle[9] $abc$4039$new_n497 preph[9] $0\ph[19:0][9] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[8] ph[19] cangle[8] $abc$4039$new_n495 $abc$4039$new_n494 $abc$4039$new_n497 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11001 1 +11011 1 +.names pre_valid $abc$4039$new_n499 preph[10] $0\ph[19:0][10] +010 1 +011 1 +101 1 +111 1 +.names ph[10] cangle[10] ph[19] $abc$4039$new_n501 $abc$4039$new_n500 $abc$4039$new_n499 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names ph[8] cangle[8] ph[9] cangle[9] $abc$4039$new_n494 $abc$4039$new_n500 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[8] ph[9] cangle[8] cangle[9] $abc$4039$new_n495 $abc$4039$new_n501 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names pre_valid ph[11] cangle[11] $abc$4039$new_n503 preph[11] $0\ph[19:0][11] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[10] ph[19] cangle[10] $abc$4039$new_n501 $abc$4039$new_n500 $abc$4039$new_n503 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names pre_valid $abc$4039$new_n505 preph[12] $0\ph[19:0][12] +010 1 +011 1 +101 1 +111 1 +.names ph[12] cangle[12] ph[19] $abc$4039$new_n507 $abc$4039$new_n506 $abc$4039$new_n505 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[10] cangle[10] ph[11] cangle[11] $abc$4039$new_n500 $abc$4039$new_n506 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names cangle[10] ph[10] ph[11] cangle[11] $abc$4039$new_n501 $abc$4039$new_n507 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names pre_valid ph[13] cangle[13] $abc$4039$new_n509 preph[13] $0\ph[19:0][13] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[12] ph[19] cangle[12] $abc$4039$new_n507 $abc$4039$new_n506 $abc$4039$new_n509 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11001 1 +11011 1 +.names pre_valid $abc$4039$new_n511 preph[14] $0\ph[19:0][14] +010 1 +011 1 +101 1 +111 1 +.names ph[14] cangle[14] ph[19] $abc$4039$new_n513 $abc$4039$new_n512 $abc$4039$new_n511 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names ph[12] cangle[12] ph[13] cangle[13] $abc$4039$new_n506 $abc$4039$new_n512 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names cangle[12] ph[12] ph[13] cangle[13] $abc$4039$new_n507 $abc$4039$new_n513 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pre_valid ph[15] cangle[15] $abc$4039$new_n515 preph[15] $0\ph[19:0][15] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[14] ph[19] cangle[14] $abc$4039$new_n513 $abc$4039$new_n512 $abc$4039$new_n515 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names pre_valid ph[16] cangle[16] $abc$4039$new_n517 preph[16] $0\ph[19:0][16] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n518 $abc$4039$new_n519 $abc$4039$new_n517 +000 1 +010 1 +110 1 +111 1 +.names ph[14] cangle[14] ph[15] cangle[15] $abc$4039$new_n512 $abc$4039$new_n518 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names cangle[14] ph[14] ph[15] cangle[15] $abc$4039$new_n513 $abc$4039$new_n519 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pre_valid ph[17] $abc$4039$new_n521 preph[17] $0\ph[19:0][17] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names ph[16] cangle[16] ph[19] $abc$4039$new_n519 $abc$4039$new_n518 $abc$4039$new_n521 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid ph[18] $abc$4039$new_n524 $abc$4039$new_n523 preph[18] $0\ph[19:0][18] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[17] ph[16] cangle[16] $abc$4039$new_n518 ph[19] $abc$4039$new_n523 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[17] cangle[16] ph[16] $abc$4039$new_n519 ph[19] $abc$4039$new_n524 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4039$new_n523 preph[19] $abc$4039$new_n524 ph[18] $0\ph[19:0][19] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid yv[0] $abc$4039$new_n527 prey[0] $0\yv[15:0][0] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$4039$new_n533 $abc$4039$new_n536 $abc$4039$new_n528 state[3] $abc$4039$new_n527 +0000 1 +0010 1 +0011 1 +.names state[2] $abc$4039$new_n530 $abc$4039$new_n529 $abc$4039$new_n532 $abc$4039$new_n531 $abc$4039$new_n528 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names state[0] state[1] xv[9] xv[8] $abc$4039$new_n529 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] xv[11] xv[10] $abc$4039$new_n530 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[0] state[1] xv[13] xv[12] $abc$4039$new_n531 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] xv[15] xv[14] $abc$4039$new_n532 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[2] state[1] state[3] $abc$4039$new_n534 $abc$4039$new_n535 $abc$4039$new_n533 +10000 1 +10001 1 +11000 1 +11010 1 +.names state[0] xv[5] xv[4] $abc$4039$new_n534 +000 1 +010 1 +100 1 +101 1 +.names state[0] xv[7] xv[6] $abc$4039$new_n535 +000 1 +010 1 +100 1 +101 1 +.names $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$new_n538 state[1] $abc$4039$new_n537 $abc$4039$new_n536 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names state[0] xv[3] xv[2] $abc$4039$new_n537 +000 1 +010 1 +100 1 +101 1 +.names state[0] state[1] xv[1] xv[0] $abc$4039$new_n538 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid $abc$4039$new_n540 prey[1] $0\yv[15:0][1] +010 1 +011 1 +101 1 +111 1 +.names yv[1] $abc$4039$new_n541 yv[0] ph[19] $abc$4039$new_n527 $abc$4039$new_n540 +00000 1 +00001 1 +00011 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] $abc$4039$new_n542 $abc$4039$new_n546 $abc$4039$new_n548 $abc$4039$new_n541 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] state[1] $abc$4039$new_n545 $abc$4039$new_n543 $abc$4039$new_n544 $abc$4039$new_n542 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[10] xv[9] $abc$4039$new_n543 +000 1 +010 1 +100 1 +101 1 +.names state[0] xv[12] xv[11] $abc$4039$new_n544 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] xv[15] xv[14] xv[13] $abc$4039$new_n545 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[1] state[0] $abc$4039$new_n547 xv[8] xv[7] $abc$4039$new_n546 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[6] xv[5] $abc$4039$new_n547 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4039$new_n549 xv[2] xv[1] $abc$4039$new_n548 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[4] xv[3] $abc$4039$new_n549 +000 1 +010 1 +100 1 +101 1 +.names pre_valid yv[2] $abc$4039$new_n552 $abc$4039$new_n551 prey[2] $0\yv[15:0][2] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[1] yv[0] ph[19] $abc$4039$new_n527 $abc$4039$new_n541 $abc$4039$new_n551 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] $abc$4039$new_n557 $abc$4039$new_n553 $abc$4039$new_n558 state[2] $abc$4039$new_n552 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] state[1] $abc$4039$new_n556 $abc$4039$new_n554 $abc$4039$new_n555 $abc$4039$new_n553 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[11] xv[10] $abc$4039$new_n554 +000 1 +010 1 +100 1 +101 1 +.names state[0] xv[13] xv[12] $abc$4039$new_n555 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] xv[15] xv[14] $abc$4039$new_n556 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names state[1] state[2] $abc$4039$new_n534 $abc$4039$new_n537 $abc$4039$new_n557 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[1] state[0] $abc$4039$new_n535 xv[9] xv[8] $abc$4039$new_n558 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid yv[3] $abc$4039$new_n565 $abc$4039$new_n560 prey[3] $0\yv[15:0][3] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n561 $abc$4039$new_n563 $abc$4039$new_n560 +000 1 +001 1 +101 1 +111 1 +.names $abc$4039$new_n541 yv[1] yv[2] $abc$4039$new_n552 $abc$4039$new_n562 $abc$4039$new_n561 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[0] $abc$4039$new_n533 $abc$4039$new_n536 state[3] $abc$4039$new_n528 $abc$4039$new_n562 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[1] $abc$4039$new_n541 yv[2] $abc$4039$new_n552 $abc$4039$new_n564 $abc$4039$new_n563 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names yv[0] $abc$4039$new_n533 $abc$4039$new_n536 state[3] $abc$4039$new_n528 $abc$4039$new_n564 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names state[3] $abc$4039$new_n566 $abc$4039$new_n568 $abc$4039$new_n565 +001 1 +011 1 +110 1 +111 1 +.names state[2] $abc$4039$new_n567 xv[15] $abc$4039$new_n566 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] $abc$4039$new_n544 xv[14] xv[13] $abc$4039$new_n567 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[2] state[1] $abc$4039$new_n569 $abc$4039$new_n547 $abc$4039$new_n549 $abc$4039$new_n568 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4039$new_n543 xv[8] xv[7] $abc$4039$new_n569 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid yv[4] $abc$4039$new_n572 $abc$4039$new_n571 prey[4] $0\yv[15:0][4] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[3] ph[19] $abc$4039$new_n565 $abc$4039$new_n563 $abc$4039$new_n561 $abc$4039$new_n571 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +.names state[3] state[2] $abc$4039$new_n575 $abc$4039$new_n573 $abc$4039$new_n574 $abc$4039$new_n572 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n530 $abc$4039$new_n529 $abc$4039$new_n573 +00 1 +.names state[1] $abc$4039$new_n534 $abc$4039$new_n535 $abc$4039$new_n574 +010 1 +011 1 +101 1 +111 1 +.names state[2] xv[15] $abc$4039$new_n531 $abc$4039$new_n532 $abc$4039$new_n575 +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names pre_valid $abc$4039$new_n577 prey[5] $0\yv[15:0][5] +010 1 +011 1 +101 1 +111 1 +.names ph[19] yv[5] $abc$4039$new_n580 $abc$4039$new_n579 $abc$4039$new_n578 $abc$4039$new_n577 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$4039$new_n561 yv[3] yv[4] $abc$4039$new_n572 $abc$4039$new_n565 $abc$4039$new_n578 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$4039$new_n563 yv[3] yv[4] $abc$4039$new_n572 $abc$4039$new_n565 $abc$4039$new_n579 +00000 1 +00001 1 +00010 1 +00100 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names state[3] state[2] $abc$4039$new_n582 $abc$4039$new_n581 $abc$4039$new_n546 $abc$4039$new_n580 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] $abc$4039$new_n543 $abc$4039$new_n544 $abc$4039$new_n581 +010 1 +011 1 +101 1 +111 1 +.names state[2] $abc$4039$new_n545 xv[15] $abc$4039$new_n582 +010 1 +011 1 +100 1 +110 1 +.names state[3] state[2] $abc$4039$new_n589 $abc$4039$new_n588 $abc$4039$new_n558 $abc$4039$new_n587 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] $abc$4039$new_n554 $abc$4039$new_n555 $abc$4039$new_n588 +010 1 +011 1 +101 1 +111 1 +.names state[2] $abc$4039$new_n556 xv[15] $abc$4039$new_n589 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n591 prey[7] $0\yv[15:0][7] +010 1 +011 1 +101 1 +111 1 +.names yv[7] $abc$4039$new_n594 ph[19] $abc$4039$new_n593 $abc$4039$new_n592 $abc$4039$new_n591 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names yv[5] $abc$4039$new_n580 yv[6] $abc$4039$new_n587 $abc$4039$new_n579 $abc$4039$new_n592 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$4039$new_n580 yv[5] yv[6] $abc$4039$new_n587 $abc$4039$new_n578 $abc$4039$new_n593 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names state[3] state[2] xv[15] $abc$4039$new_n567 $abc$4039$new_n569 $abc$4039$new_n594 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid yv[8] $abc$4039$new_n597 $abc$4039$new_n596 prey[8] $0\yv[15:0][8] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[7] ph[19] $abc$4039$new_n594 $abc$4039$new_n593 $abc$4039$new_n592 $abc$4039$new_n596 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11001 1 +11011 1 +.names state[3] $abc$4039$new_n528 xv[15] $abc$4039$new_n597 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n599 prey[9] $0\yv[15:0][9] +010 1 +011 1 +101 1 +111 1 +.names yv[9] $abc$4039$new_n602 ph[19] $abc$4039$new_n601 $abc$4039$new_n600 $abc$4039$new_n599 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names yv[7] $abc$4039$new_n594 yv[8] $abc$4039$new_n597 $abc$4039$new_n592 $abc$4039$new_n600 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n594 yv[7] yv[8] $abc$4039$new_n597 $abc$4039$new_n593 $abc$4039$new_n601 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names state[3] $abc$4039$new_n542 xv[15] $abc$4039$new_n602 +010 1 +011 1 +100 1 +110 1 +.names state[3] $abc$4039$new_n553 xv[15] $abc$4039$new_n607 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n609 prey[11] $0\yv[15:0][11] +010 1 +011 1 +101 1 +111 1 +.names yv[11] $abc$4039$new_n612 ph[19] $abc$4039$new_n611 $abc$4039$new_n610 $abc$4039$new_n609 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names yv[9] $abc$4039$new_n602 yv[10] $abc$4039$new_n607 $abc$4039$new_n600 $abc$4039$new_n610 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names yv[9] yv[10] $abc$4039$new_n602 $abc$4039$new_n607 $abc$4039$new_n601 $abc$4039$new_n611 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names state[3] $abc$4039$new_n566 xv[15] $abc$4039$new_n612 +010 1 +011 1 +100 1 +110 1 +.names pre_valid yv[12] $abc$4039$new_n615 $abc$4039$new_n614 prey[12] $0\yv[15:0][12] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[11] ph[19] $abc$4039$new_n612 $abc$4039$new_n611 $abc$4039$new_n610 $abc$4039$new_n614 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names state[3] $abc$4039$new_n575 xv[15] $abc$4039$new_n615 +010 1 +011 1 +100 1 +110 1 +.names pre_valid yv[13] $abc$4039$new_n620 $abc$4039$new_n617 prey[13] $0\yv[15:0][13] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n618 $abc$4039$new_n619 $abc$4039$new_n617 +000 1 +010 1 +100 1 +101 1 +.names yv[11] $abc$4039$new_n612 yv[12] $abc$4039$new_n615 $abc$4039$new_n610 $abc$4039$new_n618 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names yv[11] yv[12] $abc$4039$new_n612 $abc$4039$new_n615 $abc$4039$new_n611 $abc$4039$new_n619 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names state[3] $abc$4039$new_n582 xv[15] $abc$4039$new_n620 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n623 $abc$4039$new_n622 prey[14] $0\yv[15:0][14] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[13] $abc$4039$new_n620 ph[19] $abc$4039$new_n619 $abc$4039$new_n618 $abc$4039$new_n622 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[14] $abc$4039$new_n624 $abc$4039$new_n623 +01 1 +10 1 +.names state[3] $abc$4039$new_n589 xv[15] $abc$4039$new_n624 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n631 $abc$4039$new_n628 $abc$4039$new_n626 prey[15] $0\yv[15:0][15] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$new_n627 $abc$4039$new_n620 yv[13] $abc$4039$new_n619 $abc$4039$new_n623 $abc$4039$new_n626 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n624 yv[14] $abc$4039$new_n627 +000 1 +010 1 +011 1 +.names $abc$4039$new_n630 yv[13] $abc$4039$new_n620 $abc$4039$new_n618 $abc$4039$new_n623 $abc$4039$new_n628 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[19] $abc$4039$new_n624 yv[14] $abc$4039$new_n630 +101 1 +110 1 +111 1 +.names yv[15] xv[15] $abc$4039$new_n631 +00 1 +11 1 +.names pre_valid xv[0] $abc$4039$new_n633 prex[0] $0\xv[15:0][0] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$4039$new_n639 $abc$4039$new_n642 $abc$4039$new_n634 state[3] $abc$4039$new_n633 +0000 1 +0010 1 +0011 1 +.names state[2] $abc$4039$new_n636 $abc$4039$new_n635 $abc$4039$new_n638 $abc$4039$new_n637 $abc$4039$new_n634 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names state[0] state[1] yv[9] yv[8] $abc$4039$new_n635 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] yv[11] yv[10] $abc$4039$new_n636 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[0] state[1] yv[13] yv[12] $abc$4039$new_n637 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] yv[15] yv[14] $abc$4039$new_n638 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[2] state[1] state[3] $abc$4039$new_n640 $abc$4039$new_n641 $abc$4039$new_n639 +10000 1 +10001 1 +11000 1 +11010 1 +.names state[0] yv[5] yv[4] $abc$4039$new_n640 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[7] yv[6] $abc$4039$new_n641 +000 1 +010 1 +100 1 +101 1 +.names $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$new_n644 state[1] $abc$4039$new_n643 $abc$4039$new_n642 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names state[0] yv[3] yv[2] $abc$4039$new_n643 +000 1 +010 1 +100 1 +101 1 +.names state[0] state[1] yv[1] yv[0] $abc$4039$new_n644 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid $abc$4039$new_n646 prex[1] $0\xv[15:0][1] +010 1 +011 1 +101 1 +111 1 +.names xv[1] $abc$4039$new_n769 xv[0] ph[19] $abc$4039$new_n633 $abc$4039$new_n646 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01110 1 +10000 1 +10110 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names state[2] state[1] $abc$4039$new_n651 $abc$4039$new_n649 $abc$4039$new_n650 $abc$4039$new_n648 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] yv[10] yv[9] $abc$4039$new_n649 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[12] yv[11] $abc$4039$new_n650 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] yv[15] yv[14] yv[13] $abc$4039$new_n651 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[1] state[0] $abc$4039$new_n653 yv[8] yv[7] $abc$4039$new_n652 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[6] yv[5] $abc$4039$new_n653 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[4] yv[3] $abc$4039$new_n655 +000 1 +010 1 +100 1 +101 1 +.names pre_valid xv[2] $abc$4039$new_n659 $abc$4039$new_n658 prex[2] $0\xv[15:0][2] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[1] xv[0] ph[19] $abc$4039$new_n633 $abc$4039$new_n769 $abc$4039$new_n658 +00000 1 +00001 1 +00010 1 +01000 1 +01010 1 +01100 1 +10000 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +.names state[3] $abc$4039$new_n664 $abc$4039$new_n660 $abc$4039$new_n665 state[2] $abc$4039$new_n659 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] state[1] $abc$4039$new_n663 $abc$4039$new_n661 $abc$4039$new_n662 $abc$4039$new_n660 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] yv[11] yv[10] $abc$4039$new_n661 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[13] yv[12] $abc$4039$new_n662 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] yv[15] yv[14] $abc$4039$new_n663 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names state[1] state[2] $abc$4039$new_n640 $abc$4039$new_n643 $abc$4039$new_n664 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[1] state[0] $abc$4039$new_n641 yv[9] yv[8] $abc$4039$new_n665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid $abc$4039$new_n667 prex[3] $0\xv[15:0][3] +010 1 +011 1 +101 1 +111 1 +.names ph[19] xv[3] $abc$4039$new_n668 $abc$4039$new_n675 $abc$4039$new_n673 $abc$4039$new_n667 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names state[3] $abc$4039$new_n671 $abc$4039$new_n669 $abc$4039$new_n672 state[2] $abc$4039$new_n668 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] $abc$4039$new_n670 yv[15] $abc$4039$new_n669 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] $abc$4039$new_n650 yv[14] yv[13] $abc$4039$new_n670 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[1] state[2] $abc$4039$new_n653 $abc$4039$new_n655 $abc$4039$new_n671 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[1] state[0] $abc$4039$new_n649 yv[8] yv[7] $abc$4039$new_n672 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1] $abc$4039$new_n769 xv[2] $abc$4039$new_n659 $abc$4039$new_n674 $abc$4039$new_n673 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0] $abc$4039$new_n639 $abc$4039$new_n642 state[3] $abc$4039$new_n634 $abc$4039$new_n674 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$4039$new_n769 xv[1] xv[2] $abc$4039$new_n659 $abc$4039$new_n676 $abc$4039$new_n675 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[0] $abc$4039$new_n639 $abc$4039$new_n642 state[3] $abc$4039$new_n634 $abc$4039$new_n676 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid xv[4] $abc$4039$new_n679 $abc$4039$new_n678 prex[4] $0\xv[15:0][4] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[3] $abc$4039$new_n668 ph[19] $abc$4039$new_n675 $abc$4039$new_n673 $abc$4039$new_n678 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names state[3] state[2] $abc$4039$new_n682 $abc$4039$new_n680 $abc$4039$new_n681 $abc$4039$new_n679 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n636 $abc$4039$new_n635 $abc$4039$new_n680 +00 1 +.names state[1] $abc$4039$new_n640 $abc$4039$new_n641 $abc$4039$new_n681 +010 1 +011 1 +101 1 +111 1 +.names state[2] yv[15] $abc$4039$new_n637 $abc$4039$new_n638 $abc$4039$new_n682 +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names pre_valid $abc$4039$new_n684 prex[5] $0\xv[15:0][5] +000 1 +001 1 +101 1 +111 1 +.names xv[5] $abc$4039$new_n687 ph[19] $abc$4039$new_n686 $abc$4039$new_n685 $abc$4039$new_n684 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$4039$new_n675 xv[3] xv[4] $abc$4039$new_n679 $abc$4039$new_n668 $abc$4039$new_n685 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$4039$new_n673 xv[3] xv[4] $abc$4039$new_n679 $abc$4039$new_n668 $abc$4039$new_n686 +00000 1 +00001 1 +00010 1 +00100 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names state[3] state[2] $abc$4039$new_n689 $abc$4039$new_n688 $abc$4039$new_n652 $abc$4039$new_n687 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] $abc$4039$new_n649 $abc$4039$new_n650 $abc$4039$new_n688 +010 1 +011 1 +101 1 +111 1 +.names state[2] $abc$4039$new_n651 yv[15] $abc$4039$new_n689 +010 1 +011 1 +100 1 +110 1 +.names state[3] state[2] $abc$4039$new_n696 $abc$4039$new_n695 $abc$4039$new_n665 $abc$4039$new_n694 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] $abc$4039$new_n661 $abc$4039$new_n662 $abc$4039$new_n695 +010 1 +011 1 +101 1 +111 1 +.names state[2] $abc$4039$new_n663 yv[15] $abc$4039$new_n696 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n698 prex[7] $0\xv[15:0][7] +000 1 +001 1 +101 1 +111 1 +.names xv[7] $abc$4039$new_n701 ph[19] $abc$4039$new_n700 $abc$4039$new_n699 $abc$4039$new_n698 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$4039$new_n687 xv[5] xv[6] $abc$4039$new_n694 $abc$4039$new_n685 $abc$4039$new_n699 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names xv[5] $abc$4039$new_n687 xv[6] $abc$4039$new_n694 $abc$4039$new_n686 $abc$4039$new_n700 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names state[3] state[2] yv[15] $abc$4039$new_n670 $abc$4039$new_n672 $abc$4039$new_n701 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n701 xv[7] $abc$4039$new_n699 $abc$4039$new_n705 +001 1 +100 1 +101 1 +111 1 +.names xv[8] $abc$4039$new_n707 $abc$4039$new_n706 +01 1 +10 1 +.names state[3] $abc$4039$new_n634 yv[15] $abc$4039$new_n707 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[9] $abc$4039$new_n712 $abc$4039$new_n709 prex[9] $0\xv[15:0][9] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n710 $abc$4039$new_n711 $abc$4039$new_n706 $abc$4039$new_n705 $abc$4039$new_n709 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[7] $abc$4039$new_n701 xv[8] $abc$4039$new_n707 $abc$4039$new_n700 $abc$4039$new_n710 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[8] $abc$4039$new_n707 $abc$4039$new_n711 +10 1 +.names state[3] $abc$4039$new_n648 yv[15] $abc$4039$new_n712 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[10] $abc$4039$new_n717 $abc$4039$new_n714 prex[10] $0\xv[15:0][10] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[9] ph[19] $abc$4039$new_n712 $abc$4039$new_n710 $abc$4039$new_n715 $abc$4039$new_n714 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$new_n716 $abc$4039$new_n701 xv[7] $abc$4039$new_n699 $abc$4039$new_n706 $abc$4039$new_n715 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n711 $abc$4039$new_n712 xv[9] $abc$4039$new_n716 +000 1 +010 1 +011 1 +.names state[3] $abc$4039$new_n660 yv[15] $abc$4039$new_n717 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n719 prex[11] $0\xv[15:0][11] +010 1 +011 1 +101 1 +111 1 +.names xv[11] $abc$4039$new_n723 ph[19] $abc$4039$new_n722 $abc$4039$new_n720 $abc$4039$new_n719 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names xv[10] $abc$4039$new_n715 $abc$4039$new_n721 $abc$4039$new_n717 $abc$4039$new_n720 +0000 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +.names $abc$4039$new_n712 xv[9] $abc$4039$new_n721 +10 1 +.names xv[9] $abc$4039$new_n712 xv[10] $abc$4039$new_n717 $abc$4039$new_n710 $abc$4039$new_n722 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names state[3] $abc$4039$new_n669 yv[15] $abc$4039$new_n723 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n730 $abc$4039$new_n725 prex[12] $0\xv[15:0][12] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names ph[19] $abc$4039$new_n726 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n725 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names xv[11] $abc$4039$new_n723 $abc$4039$new_n722 $abc$4039$new_n726 +010 1 +100 1 +110 1 +111 1 +.names xv[10] $abc$4039$new_n715 $abc$4039$new_n721 $abc$4039$new_n717 $abc$4039$new_n728 $abc$4039$new_n727 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names xv[11] $abc$4039$new_n723 $abc$4039$new_n728 +10 1 +.names $abc$4039$new_n723 xv[11] $abc$4039$new_n729 +10 1 +.names xv[12] $abc$4039$new_n731 $abc$4039$new_n730 +01 1 +10 1 +.names state[3] $abc$4039$new_n682 yv[15] $abc$4039$new_n731 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n733 $abc$4039$new_n735 prex[13] $0\xv[15:0][13] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names xv[12] ph[19] $abc$4039$new_n731 $abc$4039$new_n726 $abc$4039$new_n734 $abc$4039$new_n733 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$new_n730 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n734 +000 1 +.names xv[13] $abc$4039$new_n736 $abc$4039$new_n735 +01 1 +10 1 +.names state[3] $abc$4039$new_n689 yv[15] $abc$4039$new_n736 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n738 $abc$4039$new_n742 prex[14] $0\xv[15:0][14] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names ph[19] xv[13] $abc$4039$new_n736 $abc$4039$new_n739 $abc$4039$new_n740 $abc$4039$new_n738 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names xv[11] $abc$4039$new_n723 xv[12] $abc$4039$new_n731 $abc$4039$new_n722 $abc$4039$new_n739 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n741 $abc$4039$new_n730 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n735 $abc$4039$new_n740 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names xv[12] xv[13] $abc$4039$new_n731 $abc$4039$new_n736 $abc$4039$new_n741 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names xv[14] $abc$4039$new_n743 $abc$4039$new_n742 +00 1 +11 1 +.names state[3] $abc$4039$new_n696 yv[15] $abc$4039$new_n743 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n631 $abc$4039$new_n747 $abc$4039$new_n745 prex[15] $0\xv[15:0][15] +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$new_n746 xv[13] $abc$4039$new_n736 $abc$4039$new_n739 $abc$4039$new_n742 $abc$4039$new_n745 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n743 xv[14] $abc$4039$new_n746 +000 1 +001 1 +010 1 +.names ph[19] xv[14] $abc$4039$new_n743 $abc$4039$new_n740 $abc$4039$new_n747 +1001 1 +1100 1 +1101 1 +1111 1 +.names state[3] state[0] state[2] state[1] $\cordic_angle$rdreg[0]$d[0] +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names state[1] state[2] state[0] state[3] $\cordic_angle$rdreg[0]$d[1] +0010 1 +0011 1 +0110 1 +0111 1 +1100 1 +1110 1 +1111 1 +.names state[2] state[3] state[1] state[0] $\cordic_angle$rdreg[0]$d[2] +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +.names state[2] state[1] state[3] state[0] $\cordic_angle$rdreg[0]$d[3] +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names state[0] state[1] state[2] state[3] $\cordic_angle$rdreg[0]$d[4] +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1100 1 +.names state[0] state[2] state[1] state[3] $\cordic_angle$rdreg[0]$d[5] +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names state[3] state[0] state[2] state[1] $\cordic_angle$rdreg[0]$d[6] +0000 1 +0010 1 +1000 1 +1001 1 +.names state[0] state[1] state[2] state[3] $\cordic_angle$rdreg[0]$d[7] +1000 1 +1001 1 +1100 1 +1110 1 +.names state[3] state[0] state[1] state[2] $\cordic_angle$rdreg[0]$d[8] +0010 1 +0011 1 +0100 1 +1000 1 +.names state[2] state[1] state[0] $auto$alumacc.cc:485:replace_alu$688.Y[2] +011 1 +100 1 +101 1 +110 1 +.names state[3] state[1] state[2] state[0] $auto$alumacc.cc:485:replace_alu$688.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names state[0] $auto$alumacc.cc:485:replace_alu$688.Y[0] +0 1 +.names idle o_busy +0 1 +.names $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] $auto$alumacc.cc:485:replace_alu$688.Y[1] +0 1 +.names yv[5] $abc$4039$new_n580 ph[19] $abc$4039$new_n579 $abc$4039$new_n578 $abc$4039$new_n764 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10101 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4039$new_n587 yv[6] $abc$4039$new_n764 prey[6] $0\yv[15:0][6] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[9] $abc$4039$new_n602 ph[19] $abc$4039$new_n600 $abc$4039$new_n601 $abc$4039$new_n766 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4039$new_n607 yv[10] $abc$4039$new_n766 prey[10] $0\yv[15:0][10] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names state[1] state[0] $abc$4039$new_n655 yv[2] yv[1] $abc$4039$new_n768 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] $abc$4039$new_n648 $abc$4039$new_n768 $abc$4039$new_n652 $abc$4039$new_n769 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5] $abc$4039$new_n687 ph[19] $abc$4039$new_n686 $abc$4039$new_n685 $abc$4039$new_n770 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4039$new_n694 xv[6] $abc$4039$new_n770 prex[6] $0\xv[15:0][6] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[7] $abc$4039$new_n701 ph[19] $abc$4039$new_n700 $abc$4039$new_n699 $abc$4039$new_n772 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4039$new_n706 $abc$4039$new_n772 prex[8] $0\xv[15:0][8] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3868 Q=o_aux +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] Q=cangle[13] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[15] Q=cangle[15] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[6] Q=cangle[16] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[0] Q=cangle[0] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[1] Q=cangle[1] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[2] Q=cangle[2] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[3] Q=cangle[3] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[4] Q=cangle[4] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[5] Q=cangle[5] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[6] Q=cangle[6] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[7] Q=cangle[7] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[8] Q=cangle[8] +.subckt dff C=i_clk D=$0\prex[15:0][2] Q=prex[2] +.subckt dff C=i_clk D=$0\prex[15:0][3] Q=prex[3] +.subckt dff C=i_clk D=$0\prex[15:0][4] Q=prex[4] +.subckt dff C=i_clk D=$0\prex[15:0][5] Q=prex[5] +.subckt dff C=i_clk D=$0\prex[15:0][6] Q=prex[6] +.subckt dff C=i_clk D=$0\prex[15:0][7] Q=prex[7] +.subckt dff C=i_clk D=$0\prex[15:0][8] Q=prex[8] +.subckt dff C=i_clk D=$0\prex[15:0][9] Q=prex[9] +.subckt dff C=i_clk D=$0\prex[15:0][10] Q=prex[10] +.subckt dff C=i_clk D=$0\prex[15:0][11] Q=prex[11] +.subckt dff C=i_clk D=$0\prex[15:0][12] Q=prex[12] +.subckt dff C=i_clk D=$0\prex[15:0][13] Q=prex[13] +.subckt dff C=i_clk D=$0\prex[15:0][14] Q=prex[14] +.subckt dff C=i_clk D=$0\prex[15:0][15] Q=prex[15] +.subckt sdffr C=i_clk D=$false Q=prex[0] R=$abc$4039$auto$rtlil.cc:2516:Or$645 +.subckt sdffr C=i_clk D=$false Q=prex[1] R=$abc$4039$auto$rtlil.cc:2516:Or$645 +.subckt sdffs C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3874 Q=idle S=i_reset +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3866 Q=o_xval[0] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3864 Q=o_xval[1] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3862 Q=o_xval[2] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3860 Q=o_xval[3] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3858 Q=o_xval[4] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3856 Q=o_xval[5] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3854 Q=o_xval[6] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3852 Q=o_xval[7] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3850 Q=o_xval[8] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3848 Q=o_xval[9] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3846 Q=o_xval[10] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3844 Q=o_xval[11] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3872 Q=o_xval[12] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3842 Q=o_yval[0] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3840 Q=o_yval[1] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3838 Q=o_yval[2] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3836 Q=o_yval[3] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3834 Q=o_yval[4] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3832 Q=o_yval[5] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3830 Q=o_yval[6] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3828 Q=o_yval[7] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3826 Q=o_yval[8] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3824 Q=o_yval[9] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3822 Q=o_yval[10] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3820 Q=o_yval[11] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3870 Q=o_yval[12] +.subckt dff C=i_clk D=$0\xv[15:0][0] Q=xv[0] +.subckt dff C=i_clk D=$0\xv[15:0][1] Q=xv[1] +.subckt dff C=i_clk D=$0\xv[15:0][2] Q=xv[2] +.subckt dff C=i_clk D=$0\xv[15:0][3] Q=xv[3] +.subckt dff C=i_clk D=$0\xv[15:0][4] Q=xv[4] +.subckt dff C=i_clk D=$0\xv[15:0][5] Q=xv[5] +.subckt dff C=i_clk D=$0\xv[15:0][6] Q=xv[6] +.subckt dff C=i_clk D=$0\xv[15:0][7] Q=xv[7] +.subckt dff C=i_clk D=$0\xv[15:0][8] Q=xv[8] +.subckt dff C=i_clk D=$0\xv[15:0][9] Q=xv[9] +.subckt dff C=i_clk D=$0\xv[15:0][10] Q=xv[10] +.subckt dff C=i_clk D=$0\xv[15:0][11] Q=xv[11] +.subckt dff C=i_clk D=$0\xv[15:0][12] Q=xv[12] +.subckt dff C=i_clk D=$0\xv[15:0][13] Q=xv[13] +.subckt dff C=i_clk D=$0\xv[15:0][14] Q=xv[14] +.subckt dff C=i_clk D=$0\xv[15:0][15] Q=xv[15] +.subckt dff C=i_clk D=$0\yv[15:0][0] Q=yv[0] +.subckt dff C=i_clk D=$0\yv[15:0][1] Q=yv[1] +.subckt dff C=i_clk D=$0\yv[15:0][2] Q=yv[2] +.subckt dff C=i_clk D=$0\yv[15:0][3] Q=yv[3] +.subckt dff C=i_clk D=$0\yv[15:0][4] Q=yv[4] +.subckt dff C=i_clk D=$0\yv[15:0][5] Q=yv[5] +.subckt dff C=i_clk D=$0\yv[15:0][6] Q=yv[6] +.subckt dff C=i_clk D=$0\yv[15:0][7] Q=yv[7] +.subckt dff C=i_clk D=$0\yv[15:0][8] Q=yv[8] +.subckt dff C=i_clk D=$0\yv[15:0][9] Q=yv[9] +.subckt dff C=i_clk D=$0\yv[15:0][10] Q=yv[10] +.subckt dff C=i_clk D=$0\yv[15:0][11] Q=yv[11] +.subckt dff C=i_clk D=$0\yv[15:0][12] Q=yv[12] +.subckt dff C=i_clk D=$0\yv[15:0][13] Q=yv[13] +.subckt dff C=i_clk D=$0\yv[15:0][14] Q=yv[14] +.subckt dff C=i_clk D=$0\yv[15:0][15] Q=yv[15] +.subckt dff C=i_clk D=$0\ph[19:0][0] Q=ph[0] +.subckt dff C=i_clk D=$0\ph[19:0][1] Q=ph[1] +.subckt dff C=i_clk D=$0\ph[19:0][2] Q=ph[2] +.subckt dff C=i_clk D=$0\ph[19:0][3] Q=ph[3] +.subckt dff C=i_clk D=$0\ph[19:0][4] Q=ph[4] +.subckt dff C=i_clk D=$0\ph[19:0][5] Q=ph[5] +.subckt dff C=i_clk D=$0\ph[19:0][6] Q=ph[6] +.subckt dff C=i_clk D=$0\ph[19:0][7] Q=ph[7] +.subckt dff C=i_clk D=$0\ph[19:0][8] Q=ph[8] +.subckt dff C=i_clk D=$0\ph[19:0][9] Q=ph[9] +.subckt dff C=i_clk D=$0\ph[19:0][10] Q=ph[10] +.subckt dff C=i_clk D=$0\ph[19:0][11] Q=ph[11] +.subckt dff C=i_clk D=$0\ph[19:0][12] Q=ph[12] +.subckt dff C=i_clk D=$0\ph[19:0][13] Q=ph[13] +.subckt dff C=i_clk D=$0\ph[19:0][14] Q=ph[14] +.subckt dff C=i_clk D=$0\ph[19:0][15] Q=ph[15] +.subckt dff C=i_clk D=$0\ph[19:0][16] Q=ph[16] +.subckt dff C=i_clk D=$0\ph[19:0][17] Q=ph[17] +.subckt dff C=i_clk D=$0\ph[19:0][18] Q=ph[18] +.subckt dff C=i_clk D=$0\ph[19:0][19] Q=ph[19] +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.CO[3] Q=o_done R=i_reset +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[9] Q=cangle[9] R=state[3] +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[10] Q=cangle[10] R=state[3] +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[11] Q=cangle[11] R=state[3] +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[12] Q=cangle[12] R=state[3] +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[0] Q=state[0] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[1] Q=state[1] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[2] Q=state[2] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[3] Q=state[3] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 +.subckt sdffr C=i_clk D=$abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y Q=pre_valid R=i_reset +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[0] Q=cangle[14] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$907 +.subckt dff C=i_clk D=$false Q=prey[0] +.subckt dff C=i_clk D=$false Q=prey[1] +.subckt dff C=i_clk D=$0\prey[15:0][2] Q=prey[2] +.subckt dff C=i_clk D=$0\prey[15:0][3] Q=prey[3] +.subckt dff C=i_clk D=$0\prey[15:0][4] Q=prey[4] +.subckt dff C=i_clk D=$0\prey[15:0][5] Q=prey[5] +.subckt dff C=i_clk D=$0\prey[15:0][6] Q=prey[6] +.subckt dff C=i_clk D=$0\prey[15:0][7] Q=prey[7] +.subckt dff C=i_clk D=$0\prey[15:0][8] Q=prey[8] +.subckt dff C=i_clk D=$0\prey[15:0][9] Q=prey[9] +.subckt dff C=i_clk D=$0\prey[15:0][10] Q=prey[10] +.subckt dff C=i_clk D=$0\prey[15:0][11] Q=prey[11] +.subckt dff C=i_clk D=$0\prey[15:0][12] Q=prey[12] +.subckt dff C=i_clk D=$0\prey[15:0][13] Q=prey[13] +.subckt dff C=i_clk D=$0\prey[15:0][14] Q=prey[14] +.subckt dff C=i_clk D=$0\prey[15:0][15] Q=prey[15] +.subckt dff C=i_clk D=i_phase[0] Q=preph[0] +.subckt dff C=i_clk D=i_phase[1] Q=preph[1] +.subckt dff C=i_clk D=i_phase[2] Q=preph[2] +.subckt dff C=i_clk D=i_phase[3] Q=preph[3] +.subckt dff C=i_clk D=i_phase[4] Q=preph[4] +.subckt dff C=i_clk D=i_phase[5] Q=preph[5] +.subckt dff C=i_clk D=i_phase[6] Q=preph[6] +.subckt dff C=i_clk D=i_phase[7] Q=preph[7] +.subckt dff C=i_clk D=i_phase[8] Q=preph[8] +.subckt dff C=i_clk D=i_phase[9] Q=preph[9] +.subckt dff C=i_clk D=i_phase[10] Q=preph[10] +.subckt dff C=i_clk D=i_phase[11] Q=preph[11] +.subckt dff C=i_clk D=i_phase[12] Q=preph[12] +.subckt dff C=i_clk D=i_phase[13] Q=preph[13] +.subckt dff C=i_clk D=i_phase[14] Q=preph[14] +.subckt dff C=i_clk D=i_phase[15] Q=preph[15] +.subckt dff C=i_clk D=i_phase[16] Q=preph[16] +.subckt dff C=i_clk D=i_phase[17] Q=preph[17] +.subckt dff C=i_clk D=i_phase[17] Q=preph[18] +.subckt dff C=i_clk D=i_phase[17] Q=preph[19] +.subckt sdffr C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3876 Q=aux R=i_reset +.names $false $0\prex[15:0][0] +1 1 +.names $false $0\prex[15:0][1] +1 1 +.names $false $0\prey[15:0][0] +1 1 +.names $false $0\prey[15:0][1] +1 1 +.names state[0] $auto$alumacc.cc:485:replace_alu$688.CO[0] +1 1 +.names $false cangle[17] +1 1 +.names $false cangle[18] +1 1 +.names $false cangle[19] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif new file mode 100644 index 00000000000..fd71bc8657f --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif @@ -0,0 +1,6314 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model seqpolar +.inputs i_clk i_reset i_stb i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_aux +.outputs o_busy o_done o_mag[0] o_mag[1] o_mag[2] o_mag[3] o_mag[4] o_mag[5] o_mag[6] o_mag[7] o_mag[8] o_mag[9] o_mag[10] o_mag[11] o_mag[12] o_phase[0] o_phase[1] o_phase[2] o_phase[3] o_phase[4] o_phase[5] o_phase[6] o_phase[7] o_phase[8] o_phase[9] o_phase[10] o_phase[11] o_phase[12] o_phase[13] o_phase[14] o_phase[15] o_phase[16] o_phase[17] o_phase[18] o_phase[19] o_phase[20] o_aux +.names $false +.names $true +1 +.names $undef +.names state[4] $abc$4719$new_n362 state[1] state[0] last_state +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names state[3] state[2] $abc$4719$new_n362 +00 1 +.names last_state ph[19] o_phase[19] $abc$4719$auto$rtlil.cc:2693:MuxGate$4488 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[18] o_phase[18] $abc$4719$auto$rtlil.cc:2693:MuxGate$4490 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[17] o_phase[17] $abc$4719$auto$rtlil.cc:2693:MuxGate$4492 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[16] o_phase[16] $abc$4719$auto$rtlil.cc:2693:MuxGate$4494 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[15] o_phase[15] $abc$4719$auto$rtlil.cc:2693:MuxGate$4496 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[14] o_phase[14] $abc$4719$auto$rtlil.cc:2693:MuxGate$4498 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[13] o_phase[13] $abc$4719$auto$rtlil.cc:2693:MuxGate$4500 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[12] o_phase[12] $abc$4719$auto$rtlil.cc:2693:MuxGate$4502 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[11] o_phase[11] $abc$4719$auto$rtlil.cc:2693:MuxGate$4504 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[10] o_phase[10] $abc$4719$auto$rtlil.cc:2693:MuxGate$4506 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[9] o_phase[9] $abc$4719$auto$rtlil.cc:2693:MuxGate$4508 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[8] o_phase[8] $abc$4719$auto$rtlil.cc:2693:MuxGate$4510 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[7] o_phase[7] $abc$4719$auto$rtlil.cc:2693:MuxGate$4512 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[6] o_phase[6] $abc$4719$auto$rtlil.cc:2693:MuxGate$4514 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[5] o_phase[5] $abc$4719$auto$rtlil.cc:2693:MuxGate$4516 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[4] o_phase[4] $abc$4719$auto$rtlil.cc:2693:MuxGate$4518 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[3] o_phase[3] $abc$4719$auto$rtlil.cc:2693:MuxGate$4520 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[2] o_phase[2] $abc$4719$auto$rtlil.cc:2693:MuxGate$4522 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[1] o_phase[1] $abc$4719$auto$rtlil.cc:2693:MuxGate$4524 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[0] o_phase[0] $abc$4719$auto$rtlil.cc:2693:MuxGate$4526 +001 1 +011 1 +110 1 +111 1 +.names last_state xv[19] xv[18] $abc$4719$new_n384 o_mag[11] $abc$4719$auto$rtlil.cc:2693:MuxGate$4528 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[17] xv[16] $abc$4719$new_n385 $abc$4719$new_n384 +111 1 +.names xv[15] xv[14] $abc$4719$new_n386 $abc$4719$new_n385 +111 1 +.names xv[13] xv[12] $abc$4719$new_n387 $abc$4719$new_n386 +111 1 +.names xv[11] xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n387 +11111 1 +.names last_state xv[18] $abc$4719$new_n384 o_mag[10] $abc$4719$auto$rtlil.cc:2693:MuxGate$4530 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names last_state xv[17] xv[16] $abc$4719$new_n385 o_mag[9] $abc$4719$auto$rtlil.cc:2693:MuxGate$4532 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names last_state xv[16] $abc$4719$new_n385 o_mag[8] $abc$4719$auto$rtlil.cc:2693:MuxGate$4534 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names last_state xv[15] xv[14] $abc$4719$new_n386 o_mag[7] $abc$4719$auto$rtlil.cc:2693:MuxGate$4536 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names last_state xv[14] $abc$4719$new_n386 o_mag[6] $abc$4719$auto$rtlil.cc:2693:MuxGate$4538 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names last_state xv[13] xv[12] $abc$4719$new_n387 o_mag[5] $abc$4719$auto$rtlil.cc:2693:MuxGate$4540 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names last_state xv[12] $abc$4719$new_n387 o_mag[4] $abc$4719$auto$rtlil.cc:2693:MuxGate$4542 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names last_state $abc$4719$new_n396 o_mag[3] $abc$4719$auto$rtlil.cc:2693:MuxGate$4544 +001 1 +011 1 +110 1 +111 1 +.names xv[11] xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n396 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names last_state $abc$4719$new_n398 o_mag[2] $abc$4719$auto$rtlil.cc:2693:MuxGate$4546 +001 1 +011 1 +110 1 +111 1 +.names xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n398 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names last_state xv[9] xv[7] xv[8] o_mag[1] $abc$4719$auto$rtlil.cc:2693:MuxGate$4548 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names last_state xv[7] xv[8] o_mag[0] $abc$4719$new_n401 $abc$4719$auto$rtlil.cc:2693:MuxGate$4550 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$4719$new_n402 xv[2] xv[1] xv[0] $abc$4719$new_n401 +1000 1 +.names xv[6] xv[5] xv[4] xv[3] $abc$4719$new_n402 +0000 1 +.names last_state aux o_aux $abc$4719$auto$rtlil.cc:2693:MuxGate$4552 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[20] o_phase[20] $abc$4719$auto$rtlil.cc:2693:MuxGate$4554 +001 1 +011 1 +110 1 +111 1 +.names last_state xv[20] $abc$4719$new_n406 o_mag[12] $abc$4719$auto$rtlil.cc:2693:MuxGate$4556 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[19] xv[18] $abc$4719$new_n384 $abc$4719$new_n406 +111 1 +.names i_stb last_state idle $abc$4719$auto$rtlil.cc:2693:MuxGate$4558 +001 1 +010 1 +011 1 +.names i_stb idle $abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y +11 1 +.names $abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y i_aux aux $abc$4719$auto$rtlil.cc:2693:MuxGate$4560 +001 1 +011 1 +110 1 +111 1 +.names i_reset idle last_state $abc$4719$auto$opt_dff.cc:253:combine_resets$656 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names state[1] $abc$4719$auto$opt_dff.cc:253:combine_resets$904 $abc$4719$auto$opt_dff.cc:253:combine_resets$901 +00 1 +01 1 +11 1 +.names $abc$4719$new_n362 state[4] $abc$4719$auto$opt_dff.cc:253:combine_resets$904 +00 1 +01 1 +11 1 +.names state[3] state[4] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 +01 1 +10 1 +11 1 +.names i_xval[0] i_yval[0] $0\prex[20:0][6] +01 1 +10 1 +.names i_xval[12] i_xval[0] i_yval[12] $abc$4719$new_n418 $abc$4719$new_n419 $0\prey[20:0][7] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_yval[1] i_xval[1] i_xval[0] i_yval[0] $abc$4719$new_n418 +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names i_yval[1] i_xval[1] i_xval[0] i_yval[0] $abc$4719$new_n419 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$4719$new_n421 $abc$4719$new_n434 $abc$4719$new_n432 $0\prey[20:0][8] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n422 $abc$4719$new_n427 $abc$4719$new_n430 $abc$4719$new_n421 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n426 $abc$4719$new_n423 $abc$4719$new_n422 +00 1 +11 1 +.names i_yval[2] $abc$4719$new_n424 $abc$4719$new_n423 +00 1 +11 1 +.names i_xval[2] $abc$4719$new_n425 $abc$4719$new_n424 +00 1 +11 1 +.names i_xval[1] i_xval[0] $abc$4719$new_n425 +00 1 +.names i_xval[1] i_yval[1] i_xval[0] i_yval[0] $abc$4719$new_n426 +0001 1 +0100 1 +0101 1 +1101 1 +1110 1 +1111 1 +.names $abc$4719$new_n429 i_xval[1] i_yval[1] $abc$4719$new_n428 $abc$4719$new_n427 +0000 1 +0100 1 +0101 1 +0110 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_yval[0] i_xval[0] $abc$4719$new_n428 +10 1 +.names i_yval[2] i_xval[2] $abc$4719$new_n429 +00 1 +11 1 +.names $abc$4719$new_n431 $abc$4719$new_n429 $abc$4719$new_n430 +01 1 +10 1 +.names i_xval[0] i_yval[0] i_yval[1] i_xval[1] $abc$4719$new_n431 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$4719$new_n433 $abc$4719$new_n423 $abc$4719$new_n432 +00 1 +11 1 +.names i_xval[1] i_yval[1] i_xval[0] i_yval[0] $abc$4719$new_n433 +0011 1 +0110 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n434 +00 1 +.names $abc$4719$new_n445 i_xval[3] i_yval[3] $abc$4719$new_n444 $abc$4719$new_n436 $0\prey[20:0][9] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n437 $abc$4719$new_n440 $abc$4719$new_n442 $abc$4719$new_n436 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$4719$new_n438 i_yval[2] $abc$4719$new_n426 $abc$4719$new_n424 $abc$4719$new_n437 +0000 1 +0001 1 +0011 1 +0101 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_yval[3] $abc$4719$new_n439 $abc$4719$new_n438 +00 1 +11 1 +.names i_xval[3] $abc$4719$new_n425 i_xval[2] $abc$4719$new_n439 +000 1 +001 1 +011 1 +110 1 +.names $abc$4719$new_n441 $abc$4719$new_n438 $abc$4719$new_n440 +01 1 +10 1 +.names i_yval[2] $abc$4719$new_n433 $abc$4719$new_n424 $abc$4719$new_n441 +000 1 +001 1 +010 1 +100 1 +.names i_xval[3] i_yval[3] $abc$4719$new_n443 $abc$4719$new_n442 +001 1 +010 1 +100 1 +111 1 +.names i_yval[1] i_yval[2] i_xval[1] i_xval[2] $abc$4719$new_n428 $abc$4719$new_n443 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[2] i_xval[2] $abc$4719$new_n431 $abc$4719$new_n444 +000 1 +001 1 +011 1 +101 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n445 +10 1 +.names $abc$4719$new_n447 $abc$4719$new_n445 $abc$4719$new_n455 $0\prey[20:0][10] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n448 $abc$4719$new_n451 $abc$4719$new_n453 $abc$4719$new_n447 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n449 $abc$4719$new_n448 +000 1 +011 1 +101 1 +110 1 +.names i_yval[3] $abc$4719$new_n439 $abc$4719$new_n441 $abc$4719$new_n449 +000 1 +001 1 +011 1 +101 1 +.names i_xval[4] $abc$4719$new_n425 i_xval[3] i_xval[2] $abc$4719$new_n450 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n452 $abc$4719$new_n451 +001 1 +010 1 +100 1 +111 1 +.names i_yval[2] $abc$4719$new_n426 i_yval[3] $abc$4719$new_n439 $abc$4719$new_n424 $abc$4719$new_n452 +00100 1 +00101 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n454 i_xval[3] i_yval[3] $abc$4719$new_n443 $abc$4719$new_n453 +0000 1 +0100 1 +0101 1 +0110 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_yval[4] i_xval[4] $abc$4719$new_n454 +00 1 +11 1 +.names $abc$4719$new_n454 i_xval[3] i_yval[3] $abc$4719$new_n444 $abc$4719$new_n455 +0000 1 +0001 1 +0011 1 +0101 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$4719$new_n457 $abc$4719$new_n445 $abc$4719$new_n466 $0\prey[20:0][11] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n458 $abc$4719$new_n462 $abc$4719$new_n464 $abc$4719$new_n457 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n459 $abc$4719$new_n458 +000 1 +011 1 +101 1 +110 1 +.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n449 $abc$4719$new_n459 +000 1 +001 1 +011 1 +101 1 +.names i_xval[5] $abc$4719$new_n461 $abc$4719$new_n460 +00 1 +11 1 +.names $abc$4719$new_n425 i_xval[4] i_xval[3] i_xval[2] $abc$4719$new_n461 +1000 1 +.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n463 $abc$4719$new_n462 +001 1 +010 1 +100 1 +111 1 +.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n452 $abc$4719$new_n463 +001 1 +100 1 +101 1 +111 1 +.names i_xval[5] i_yval[5] $abc$4719$new_n465 $abc$4719$new_n464 +001 1 +010 1 +100 1 +111 1 +.names i_yval[3] i_yval[4] i_xval[3] i_xval[4] $abc$4719$new_n443 $abc$4719$new_n465 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_xval[5] i_yval[5] $abc$4719$new_n467 $abc$4719$new_n466 +000 1 +011 1 +101 1 +110 1 +.names i_xval[3] i_yval[3] i_yval[4] i_xval[4] $abc$4719$new_n444 $abc$4719$new_n467 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$4719$new_n469 i_xval[12] $abc$4719$new_n474 i_yval[12] $0\prey[20:0][12] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n470 $abc$4719$new_n472 $abc$4719$new_n473 $abc$4719$new_n469 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[6] i_xval[6] $abc$4719$new_n471 $abc$4719$new_n461 i_xval[5] $abc$4719$new_n470 +00010 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01110 1 +10000 1 +10001 1 +10011 1 +10110 1 +11010 1 +11100 1 +11101 1 +11111 1 +.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n459 $abc$4719$new_n471 +000 1 +001 1 +011 1 +101 1 +.names i_yval[6] i_xval[6] i_xval[5] i_yval[5] $abc$4719$new_n467 $abc$4719$new_n472 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[6] i_xval[6] i_xval[5] i_yval[5] $abc$4719$new_n465 $abc$4719$new_n473 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_yval[6] i_xval[6] $abc$4719$new_n475 $abc$4719$new_n461 i_xval[5] $abc$4719$new_n474 +00000 1 +00001 1 +00011 1 +00110 1 +01010 1 +01100 1 +01101 1 +01111 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n463 $abc$4719$new_n475 +001 1 +100 1 +101 1 +111 1 +.names $abc$4719$new_n477 $abc$4719$new_n445 $abc$4719$new_n485 $0\prey[20:0][13] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n478 $abc$4719$new_n481 $abc$4719$new_n483 $abc$4719$new_n477 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n479 $abc$4719$new_n478 +000 1 +011 1 +101 1 +110 1 +.names i_xval[6] $abc$4719$new_n461 i_xval[5] i_yval[6] $abc$4719$new_n471 $abc$4719$new_n479 +00001 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_xval[7] $abc$4719$new_n461 i_xval[6] i_xval[5] $abc$4719$new_n480 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n482 $abc$4719$new_n481 +001 1 +010 1 +100 1 +111 1 +.names i_xval[6] $abc$4719$new_n461 i_yval[6] i_xval[5] $abc$4719$new_n475 $abc$4719$new_n482 +00101 1 +00111 1 +01001 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_yval[7] i_xval[7] $abc$4719$new_n484 $abc$4719$new_n483 +001 1 +010 1 +100 1 +111 1 +.names i_yval[5] i_yval[6] i_xval[5] i_xval[6] $abc$4719$new_n465 $abc$4719$new_n484 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[7] i_xval[7] $abc$4719$new_n486 $abc$4719$new_n485 +000 1 +011 1 +101 1 +110 1 +.names i_xval[5] i_yval[5] i_yval[6] i_xval[6] $abc$4719$new_n467 $abc$4719$new_n486 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$4719$new_n488 $abc$4719$new_n445 $abc$4719$new_n495 $0\prey[20:0][14] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n489 $abc$4719$new_n492 $abc$4719$new_n494 $abc$4719$new_n488 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[8] $abc$4719$new_n491 $abc$4719$new_n490 $abc$4719$new_n489 +000 1 +011 1 +101 1 +110 1 +.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n479 $abc$4719$new_n490 +000 1 +001 1 +011 1 +101 1 +.names i_xval[8] $abc$4719$new_n461 i_xval[7] i_xval[6] i_xval[5] $abc$4719$new_n491 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names i_yval[8] $abc$4719$new_n491 $abc$4719$new_n493 $abc$4719$new_n492 +001 1 +010 1 +100 1 +111 1 +.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n482 $abc$4719$new_n493 +001 1 +100 1 +101 1 +111 1 +.names i_yval[8] i_xval[8] i_yval[7] i_xval[7] $abc$4719$new_n484 $abc$4719$new_n494 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[8] i_xval[8] i_yval[7] i_xval[7] $abc$4719$new_n486 $abc$4719$new_n495 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n499 $abc$4719$new_n498 +000 1 +011 1 +101 1 +110 1 +.names i_yval[8] $abc$4719$new_n491 $abc$4719$new_n490 $abc$4719$new_n499 +000 1 +001 1 +011 1 +101 1 +.names i_xval[9] $abc$4719$new_n501 $abc$4719$new_n500 +00 1 +11 1 +.names $abc$4719$new_n461 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$4719$new_n501 +10000 1 +.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n503 $abc$4719$new_n502 +001 1 +010 1 +100 1 +111 1 +.names i_yval[8] $abc$4719$new_n491 $abc$4719$new_n493 $abc$4719$new_n503 +001 1 +100 1 +101 1 +111 1 +.names i_yval[9] i_xval[9] $abc$4719$new_n505 $abc$4719$new_n504 +000 1 +011 1 +101 1 +110 1 +.names i_yval[7] i_xval[7] i_yval[8] i_xval[8] $abc$4719$new_n486 $abc$4719$new_n505 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[7] i_yval[8] i_xval[7] i_xval[8] $abc$4719$new_n484 $abc$4719$new_n507 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$new_n509 $abc$4719$new_n445 $abc$4719$new_n517 $0\prey[20:0][16] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n510 $abc$4719$new_n514 $abc$4719$new_n516 $abc$4719$new_n509 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$4719$new_n512 $abc$4719$new_n511 $abc$4719$new_n510 +01 1 +10 1 +.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n499 $abc$4719$new_n511 +000 1 +001 1 +011 1 +101 1 +.names i_yval[10] $abc$4719$new_n513 $abc$4719$new_n512 +00 1 +11 1 +.names i_xval[10] $abc$4719$new_n501 i_xval[9] $abc$4719$new_n513 +000 1 +001 1 +011 1 +110 1 +.names $abc$4719$new_n512 $abc$4719$new_n515 $abc$4719$new_n514 +00 1 +11 1 +.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n503 $abc$4719$new_n515 +001 1 +100 1 +101 1 +111 1 +.names i_xval[10] i_yval[10] i_yval[9] i_xval[9] $abc$4719$new_n507 $abc$4719$new_n516 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_xval[10] i_yval[10] i_yval[9] i_xval[9] $abc$4719$new_n505 $abc$4719$new_n517 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$4719$new_n523 $abc$4719$new_n434 $abc$4719$new_n519 $0\prey[20:0][17] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$4719$new_n521 $abc$4719$new_n520 $abc$4719$new_n519 +01 1 +10 1 +.names i_yval[10] $abc$4719$new_n513 $abc$4719$new_n511 $abc$4719$new_n520 +000 1 +001 1 +011 1 +101 1 +.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n521 +00 1 +11 1 +.names i_xval[11] $abc$4719$new_n501 i_xval[10] i_xval[9] $abc$4719$new_n522 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n524 $abc$4719$new_n526 $abc$4719$new_n528 $abc$4719$new_n523 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$4719$new_n521 $abc$4719$new_n525 $abc$4719$new_n524 +00 1 +11 1 +.names i_yval[10] $abc$4719$new_n513 $abc$4719$new_n515 $abc$4719$new_n525 +001 1 +100 1 +101 1 +111 1 +.names i_yval[11] i_xval[11] $abc$4719$new_n527 $abc$4719$new_n526 +000 1 +011 1 +101 1 +110 1 +.names i_yval[9] i_xval[9] i_xval[10] i_yval[10] $abc$4719$new_n505 $abc$4719$new_n527 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[11] i_xval[11] $abc$4719$new_n529 $abc$4719$new_n528 +001 1 +010 1 +100 1 +111 1 +.names i_yval[9] i_xval[9] i_xval[10] i_yval[10] $abc$4719$new_n507 $abc$4719$new_n529 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_xval[12] $abc$4719$new_n535 $abc$4719$new_n537 i_yval[12] $abc$4719$new_n967 $0\prey[20:0][18] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n520 $abc$4719$new_n533 +000 1 +001 1 +011 1 +101 1 +.names i_yval[11] i_xval[11] $abc$4719$new_n527 $abc$4719$new_n534 +000 1 +001 1 +011 1 +101 1 +.names $abc$4719$new_n501 i_xval[11] i_xval[10] i_xval[9] $abc$4719$new_n535 +1000 1 +.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n525 $abc$4719$new_n537 +001 1 +100 1 +101 1 +111 1 +.names $abc$4719$new_n967 i_xval[12] $abc$4719$new_n537 i_yval[12] $abc$4719$new_n535 $0\prey[20:0][19] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +.names state[1] state[3] state[2] state[4] state[0] $\cordic_angle$rdreg[0]$d[0] +00001 1 +00011 1 +01000 1 +01001 1 +10001 1 +10100 1 +10101 1 +11001 1 +11101 1 +.names state[4] state[0] state[3] state[1] state[2] $\cordic_angle$rdreg[0]$d[1] +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +10000 1 +.names state[1] state[2] state[0] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[2] +0010 1 +0011 1 +0110 1 +0111 1 +1100 1 +1110 1 +1111 1 +.names state[3] state[1] state[0] state[2] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[3] +0001 1 +0011 1 +0101 1 +1000 1 +1001 1 +1101 1 +.names state[2] state[0] state[1] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[4] +0111 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names state[0] state[1] state[2] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[5] +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1100 1 +.names state[0] state[2] state[1] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[6] +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names state[1] state[0] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] +00 1 +.names state[3] state[0] state[2] state[1] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[7] +0000 1 +0010 1 +1000 1 +1001 1 +.names state[0] state[1] state[2] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[8] +1000 1 +1001 1 +1100 1 +1110 1 +.names state[0] state[3] state[1] state[2] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[9] +0010 1 +0011 1 +0100 1 +1000 1 +.names state[0] state[1] $abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[16] +10 1 +.names state[2] state[0] state[1] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[10] +000 1 +010 1 +110 1 +111 1 +.names state[2] state[0] state[1] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[11] +000 1 +010 1 +100 1 +101 1 +.names state[0] state[1] state[2] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[12] +000 1 +100 1 +101 1 +110 1 +.names state[1] state[0] state[2] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[13] +001 1 +010 1 +100 1 +.names cangle[0] ph[0] $abc$4719$procmux$562_Y[0] +01 1 +10 1 +.names cangle[1] ph[1] yv[20] ph[0] cangle[0] $abc$4719$procmux$562_Y[1] +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names yv[20] cangle[2] ph[2] $abc$4719$new_n559 $abc$4719$new_n558 $abc$4719$procmux$562_Y[2] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0] cangle[0] cangle[1] ph[1] $abc$4719$new_n558 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names cangle[0] cangle[1] ph[0] ph[1] $abc$4719$new_n559 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[20] cangle[3] ph[3] $abc$4719$new_n562 $abc$4719$new_n561 $abc$4719$procmux$562_Y[3] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names cangle[2] ph[2] $abc$4719$new_n558 $abc$4719$new_n561 +000 1 +001 1 +011 1 +101 1 +.names ph[2] cangle[2] $abc$4719$new_n559 $abc$4719$new_n562 +001 1 +100 1 +101 1 +111 1 +.names yv[20] cangle[4] ph[4] $abc$4719$new_n565 $abc$4719$new_n564 $abc$4719$procmux$562_Y[4] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[3] ph[3] $abc$4719$new_n561 $abc$4719$new_n564 +000 1 +001 1 +011 1 +101 1 +.names cangle[3] ph[3] $abc$4719$new_n562 $abc$4719$new_n565 +000 1 +100 1 +101 1 +110 1 +.names cangle[5] ph[5] $abc$4719$new_n567 $abc$4719$procmux$562_Y[5] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[4] ph[4] $abc$4719$new_n565 $abc$4719$new_n564 $abc$4719$new_n567 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[20] cangle[6] ph[6] $abc$4719$new_n570 $abc$4719$new_n569 $abc$4719$procmux$562_Y[6] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[4] ph[4] cangle[5] ph[5] $abc$4719$new_n564 $abc$4719$new_n569 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names cangle[4] cangle[5] ph[4] ph[5] $abc$4719$new_n565 $abc$4719$new_n570 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names cangle[7] ph[7] $abc$4719$new_n572 $abc$4719$procmux$562_Y[7] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[6] ph[6] $abc$4719$new_n570 $abc$4719$new_n569 $abc$4719$new_n572 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[20] cangle[8] ph[8] $abc$4719$new_n575 $abc$4719$new_n574 $abc$4719$procmux$562_Y[8] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[6] ph[6] cangle[7] ph[7] $abc$4719$new_n569 $abc$4719$new_n574 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names cangle[6] cangle[7] ph[6] ph[7] $abc$4719$new_n570 $abc$4719$new_n575 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names cangle[9] ph[9] $abc$4719$new_n577 $abc$4719$procmux$562_Y[9] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[8] ph[8] $abc$4719$new_n575 $abc$4719$new_n574 $abc$4719$new_n577 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[20] cangle[10] ph[10] $abc$4719$new_n582 $abc$4719$new_n579 $abc$4719$procmux$562_Y[10] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$4719$new_n581 $abc$4719$new_n580 $abc$4719$new_n579 +10 1 +.names cangle[9] cangle[8] ph[8] ph[9] $abc$4719$new_n574 $abc$4719$new_n580 +00110 1 +01010 1 +10100 1 +11000 1 +.names ph[8] cangle[8] cangle[9] ph[9] $abc$4719$new_n581 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names ph[8] cangle[8] cangle[9] ph[9] $abc$4719$new_n575 $abc$4719$new_n582 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names cangle[11] ph[11] $abc$4719$new_n584 $abc$4719$procmux$562_Y[11] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[10] ph[10] $abc$4719$new_n582 $abc$4719$new_n579 $abc$4719$new_n584 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[20] cangle[12] ph[12] $abc$4719$new_n589 $abc$4719$new_n586 $abc$4719$procmux$562_Y[12] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$4719$new_n588 $abc$4719$new_n587 $abc$4719$new_n586 +10 1 +.names $abc$4719$new_n580 cangle[11] cangle[10] ph[10] ph[11] $abc$4719$new_n587 +10011 1 +10101 1 +11010 1 +11100 1 +.names cangle[10] ph[10] cangle[11] ph[11] $abc$4719$new_n581 $abc$4719$new_n588 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names cangle[10] cangle[11] ph[10] ph[11] $abc$4719$new_n582 $abc$4719$new_n589 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[20] cangle[13] ph[13] $abc$4719$new_n592 $abc$4719$new_n591 $abc$4719$procmux$562_Y[13] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[12] ph[12] $abc$4719$new_n586 $abc$4719$new_n591 +000 1 +001 1 +011 1 +101 1 +.names cangle[12] ph[12] $abc$4719$new_n589 $abc$4719$new_n592 +001 1 +100 1 +101 1 +111 1 +.names yv[20] cangle[14] ph[14] $abc$4719$new_n595 $abc$4719$new_n594 $abc$4719$procmux$562_Y[14] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names cangle[13] ph[13] $abc$4719$new_n591 $abc$4719$new_n594 +000 1 +001 1 +011 1 +101 1 +.names ph[13] cangle[13] $abc$4719$new_n592 $abc$4719$new_n595 +000 1 +100 1 +101 1 +110 1 +.names cangle[15] ph[15] $abc$4719$new_n597 $abc$4719$procmux$562_Y[15] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[14] ph[14] $abc$4719$new_n595 $abc$4719$new_n594 $abc$4719$new_n597 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[20] cangle[16] ph[16] $abc$4719$new_n600 $abc$4719$new_n599 $abc$4719$procmux$562_Y[16] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[14] ph[14] cangle[15] ph[15] $abc$4719$new_n594 $abc$4719$new_n599 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names cangle[14] cangle[15] ph[14] ph[15] $abc$4719$new_n595 $abc$4719$new_n600 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[20] cangle[17] ph[17] $abc$4719$new_n603 $abc$4719$new_n602 $abc$4719$procmux$562_Y[17] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[16] ph[16] $abc$4719$new_n599 $abc$4719$new_n602 +000 1 +001 1 +011 1 +101 1 +.names cangle[16] ph[16] $abc$4719$new_n600 $abc$4719$new_n603 +001 1 +100 1 +101 1 +111 1 +.names ph[18] $abc$4719$new_n605 $abc$4719$procmux$562_Y[18] +00 1 +11 1 +.names yv[20] ph[17] cangle[17] $abc$4719$new_n603 $abc$4719$new_n602 $abc$4719$new_n605 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names pre_valid ph[19] $abc$4719$new_n608 $abc$4719$new_n607 preph[19] $0\ph[20:0][19] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[18] yv[20] cangle[17] ph[17] $abc$4719$new_n602 $abc$4719$new_n607 +10010 1 +10100 1 +10110 1 +10111 1 +.names yv[20] ph[18] cangle[17] ph[17] $abc$4719$new_n603 $abc$4719$new_n608 +10001 1 +10100 1 +10101 1 +10111 1 +.names pre_valid $abc$4719$new_n610 preph[20] $0\ph[20:0][20] +010 1 +011 1 +101 1 +111 1 +.names ph[20] ph[19] $abc$4719$new_n608 $abc$4719$new_n607 $abc$4719$new_n610 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names pre_valid yv[0] $abc$4719$new_n612 prey[0] $0\yv[20:0][0] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$4719$new_n613 $abc$4719$new_n619 state[4] $abc$4719$new_n616 $abc$4719$new_n612 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names state[4] state[3] state[2] xv[20] $abc$4719$new_n614 $abc$4719$new_n613 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[1] state[0] $abc$4719$new_n615 xv[19] xv[18] $abc$4719$new_n614 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[17] xv[16] $abc$4719$new_n615 +000 1 +010 1 +100 1 +101 1 +.names state[2] state[3] $abc$4719$new_n617 $abc$4719$new_n616 +100 1 +.names state[1] state[0] $abc$4719$new_n618 xv[5] xv[4] $abc$4719$new_n617 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[7] xv[6] $abc$4719$new_n618 +000 1 +010 1 +100 1 +101 1 +.names $abc$4719$new_n624 state[2] state[3] $abc$4719$new_n620 $abc$4719$new_n622 $abc$4719$new_n619 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +.names state[1] state[0] $abc$4719$new_n621 xv[11] xv[10] $abc$4719$new_n620 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[9] xv[8] $abc$4719$new_n621 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n623 xv[15] xv[14] $abc$4719$new_n622 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[13] xv[12] $abc$4719$new_n623 +000 1 +010 1 +100 1 +101 1 +.names $abc$4719$new_n362 $abc$4719$new_n625 xv[0] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] $abc$4719$new_n624 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names state[1] state[0] xv[3] xv[1] xv[2] $abc$4719$new_n625 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid $abc$4719$new_n627 prey[1] $0\yv[20:0][1] +010 1 +011 1 +101 1 +111 1 +.names yv[1] $abc$4719$new_n1009 yv[0] yv[20] $abc$4719$new_n612 $abc$4719$new_n627 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n631 xv[20] xv[19] $abc$4719$new_n630 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[18] xv[17] $abc$4719$new_n631 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n634 xv[12] xv[11] $abc$4719$new_n633 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[10] xv[9] $abc$4719$new_n634 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n636 xv[16] xv[15] $abc$4719$new_n635 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[14] xv[13] $abc$4719$new_n636 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n639 xv[6] xv[5] $abc$4719$new_n638 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[8] xv[7] $abc$4719$new_n639 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n642 xv[2] xv[1] $abc$4719$new_n641 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[4] xv[3] $abc$4719$new_n642 +000 1 +010 1 +100 1 +101 1 +.names yv[0] $abc$4719$new_n613 $abc$4719$new_n616 $abc$4719$new_n619 state[4] $abc$4719$new_n646 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names yv[0] $abc$4719$new_n613 $abc$4719$new_n616 $abc$4719$new_n619 state[4] $abc$4719$new_n648 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$4719$new_n657 $abc$4719$new_n654 $abc$4719$new_n650 $abc$4719$new_n649 +000 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n653 $abc$4719$new_n652 $abc$4719$new_n651 state[2] $abc$4719$new_n650 +00000 1 +00010 1 +00011 1 +.names state[1] $abc$4719$new_n621 $abc$4719$new_n618 $abc$4719$new_n651 +001 1 +011 1 +110 1 +111 1 +.names state[0] state[2] state[1] xv[3] xv[2] $abc$4719$new_n652 +00001 1 +00011 1 +10010 1 +10011 1 +.names state[1] state[0] state[2] xv[5] xv[4] $abc$4719$new_n653 +10001 1 +10011 1 +11010 1 +11011 1 +.names state[3] state[2] state[4] $abc$4719$new_n655 $abc$4719$new_n656 $abc$4719$new_n654 +10010 1 +10011 1 +11001 1 +11011 1 +.names state[1] state[0] $abc$4719$new_n623 xv[11] xv[10] $abc$4719$new_n655 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n615 xv[15] xv[14] $abc$4719$new_n656 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[4] state[3] state[2] xv[20] $abc$4719$new_n658 $abc$4719$new_n657 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[1] state[0] xv[20] xv[19] xv[18] $abc$4719$new_n658 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid yv[3] $abc$4719$new_n976 $abc$4719$new_n660 prey[3] $0\yv[20:0][3] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n661 $abc$4719$new_n974 $abc$4719$new_n660 +000 1 +010 1 +100 1 +101 1 +.names yv[1] $abc$4719$new_n1009 yv[2] $abc$4719$new_n649 $abc$4719$new_n648 $abc$4719$new_n661 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names state[4] state[3] $abc$4719$new_n667 $abc$4719$new_n670 xv[20] $abc$4719$new_n666 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names state[2] $abc$4719$new_n668 $abc$4719$new_n669 $abc$4719$new_n667 +010 1 +011 1 +101 1 +111 1 +.names state[1] state[0] $abc$4719$new_n636 xv[12] xv[11] $abc$4719$new_n668 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n631 xv[16] xv[15] $abc$4719$new_n669 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] $abc$4719$new_n671 xv[20] $abc$4719$new_n670 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] xv[20] xv[19] $abc$4719$new_n671 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names state[1] $abc$4719$new_n634 $abc$4719$new_n639 $abc$4719$new_n672 +001 1 +011 1 +110 1 +111 1 +.names pre_valid yv[4] $abc$4719$new_n677 $abc$4719$new_n676 prey[4] $0\yv[20:0][4] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[3] yv[20] $abc$4719$new_n976 $abc$4719$new_n974 $abc$4719$new_n661 $abc$4719$new_n676 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names state[4] $abc$4719$new_n678 $abc$4719$new_n679 xv[20] $abc$4719$new_n677 +0010 1 +0011 1 +1000 1 +1010 1 +.names state[3] state[2] state[4] $abc$4719$new_n614 $abc$4719$new_n622 $abc$4719$new_n678 +10000 1 +10010 1 +11000 1 +11001 1 +.names state[2] state[3] $abc$4719$new_n620 $abc$4719$new_n617 $abc$4719$new_n679 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid $abc$4719$new_n681 prey[5] $0\yv[20:0][5] +000 1 +001 1 +101 1 +111 1 +.names yv[5] $abc$4719$new_n684 yv[20] $abc$4719$new_n683 $abc$4719$new_n682 $abc$4719$new_n681 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$4719$new_n661 yv[3] yv[4] $abc$4719$new_n677 $abc$4719$new_n976 $abc$4719$new_n682 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[3] $abc$4719$new_n974 yv[4] $abc$4719$new_n677 $abc$4719$new_n976 $abc$4719$new_n683 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[4] $abc$4719$new_n686 xv[20] $abc$4719$new_n685 state[3] $abc$4719$new_n684 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n630 $abc$4719$new_n635 $abc$4719$new_n685 +001 1 +011 1 +110 1 +111 1 +.names state[2] state[3] $abc$4719$new_n633 $abc$4719$new_n638 $abc$4719$new_n686 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[6] $abc$4719$new_n692 $abc$4719$new_n691 +01 1 +10 1 +.names state[4] $abc$4719$new_n694 xv[20] $abc$4719$new_n693 state[3] $abc$4719$new_n692 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n656 $abc$4719$new_n658 $abc$4719$new_n693 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n651 $abc$4719$new_n655 $abc$4719$new_n694 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid yv[7] $abc$4719$new_n700 $abc$4719$new_n696 prey[7] $0\yv[20:0][7] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n697 $abc$4719$new_n699 $abc$4719$new_n698 $abc$4719$new_n696 +0000 1 +0001 1 +0010 1 +0011 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names yv[5] $abc$4719$new_n684 yv[6] $abc$4719$new_n692 $abc$4719$new_n683 $abc$4719$new_n697 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n691 yv[5] $abc$4719$new_n684 $abc$4719$new_n682 $abc$4719$new_n698 +0000 1 +0100 1 +0101 1 +0110 1 +.names yv[6] $abc$4719$new_n692 $abc$4719$new_n699 +10 1 +.names state[4] $abc$4719$new_n702 xv[20] $abc$4719$new_n701 state[3] $abc$4719$new_n700 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n669 $abc$4719$new_n671 $abc$4719$new_n701 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n672 $abc$4719$new_n668 $abc$4719$new_n702 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid yv[8] $abc$4719$new_n707 $abc$4719$new_n704 prey[8] $0\yv[20:0][8] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[7] yv[20] $abc$4719$new_n696 $abc$4719$new_n700 $abc$4719$new_n704 +0001 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$4719$new_n699 $abc$4719$new_n700 yv[7] $abc$4719$new_n706 +000 1 +010 1 +011 1 +.names $abc$4719$new_n708 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n620 $abc$4719$new_n622 $abc$4719$new_n707 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] xv[20] $abc$4719$new_n614 $abc$4719$new_n708 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid $abc$4719$new_n710 prey[9] $0\yv[20:0][9] +010 1 +011 1 +101 1 +111 1 +.names yv[9] $abc$4719$new_n714 yv[20] $abc$4719$new_n713 $abc$4719$new_n711 $abc$4719$new_n710 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names yv[8] $abc$4719$new_n707 $abc$4719$new_n706 $abc$4719$new_n698 $abc$4719$new_n712 $abc$4719$new_n711 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$new_n700 yv[7] $abc$4719$new_n712 +10 1 +.names yv[7] $abc$4719$new_n700 yv[8] $abc$4719$new_n707 $abc$4719$new_n697 $abc$4719$new_n713 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n715 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n633 $abc$4719$new_n635 $abc$4719$new_n714 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] xv[20] $abc$4719$new_n630 $abc$4719$new_n715 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n721 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n655 $abc$4719$new_n656 $abc$4719$new_n720 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] xv[20] $abc$4719$new_n658 $abc$4719$new_n721 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid $abc$4719$new_n723 prey[11] $0\yv[20:0][11] +010 1 +011 1 +101 1 +111 1 +.names yv[11] $abc$4719$new_n726 yv[20] $abc$4719$new_n725 $abc$4719$new_n724 $abc$4719$new_n723 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$4719$new_n714 yv[9] yv[10] $abc$4719$new_n720 $abc$4719$new_n711 $abc$4719$new_n724 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9] $abc$4719$new_n714 yv[10] $abc$4719$new_n720 $abc$4719$new_n713 $abc$4719$new_n725 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[4] state[3] xv[20] $abc$4719$new_n667 $abc$4719$new_n670 $abc$4719$new_n726 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid yv[12] $abc$4719$new_n729 $abc$4719$new_n728 prey[12] $0\yv[20:0][12] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[11] $abc$4719$new_n726 yv[20] $abc$4719$new_n725 $abc$4719$new_n724 $abc$4719$new_n728 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 state[2] xv[20] $abc$4719$new_n614 $abc$4719$new_n622 $abc$4719$new_n729 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid $abc$4719$new_n731 prey[13] $0\yv[20:0][13] +000 1 +001 1 +101 1 +111 1 +.names yv[13] $abc$4719$new_n734 yv[20] $abc$4719$new_n733 $abc$4719$new_n732 $abc$4719$new_n731 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$4719$new_n726 yv[11] yv[12] $abc$4719$new_n729 $abc$4719$new_n724 $abc$4719$new_n732 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[11] $abc$4719$new_n726 yv[12] $abc$4719$new_n729 $abc$4719$new_n725 $abc$4719$new_n733 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n685 xv[20] $abc$4719$new_n734 +010 1 +011 1 +100 1 +110 1 +.names yv[13] $abc$4719$new_n734 $abc$4719$new_n732 $abc$4719$new_n737 +000 1 +100 1 +101 1 +110 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n693 xv[20] $abc$4719$new_n739 +010 1 +011 1 +100 1 +110 1 +.names pre_valid yv[15] $abc$4719$new_n745 $abc$4719$new_n741 prey[15] $0\yv[20:0][15] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n742 $abc$4719$new_n743 $abc$4719$new_n744 $abc$4719$new_n737 $abc$4719$new_n741 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[13] $abc$4719$new_n734 yv[14] $abc$4719$new_n739 $abc$4719$new_n733 $abc$4719$new_n742 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names $abc$4719$new_n739 yv[14] $abc$4719$new_n743 +10 1 +.names yv[14] $abc$4719$new_n739 $abc$4719$new_n744 +10 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n701 xv[20] $abc$4719$new_n745 +010 1 +011 1 +100 1 +110 1 +.names pre_valid yv[16] $abc$4719$new_n750 $abc$4719$new_n747 prey[16] $0\yv[20:0][16] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[15] yv[20] $abc$4719$new_n745 $abc$4719$new_n742 $abc$4719$new_n748 $abc$4719$new_n747 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$4719$new_n749 yv[13] $abc$4719$new_n734 $abc$4719$new_n732 $abc$4719$new_n744 $abc$4719$new_n748 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$new_n743 $abc$4719$new_n745 yv[15] $abc$4719$new_n749 +000 1 +001 1 +011 1 +.names xv[20] state[3] state[2] state[4] $abc$4719$new_n614 $abc$4719$new_n750 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +.names pre_valid yv[17] $abc$4719$new_n755 $abc$4719$new_n752 prey[17] $0\yv[20:0][17] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n753 $abc$4719$new_n754 $abc$4719$new_n752 +000 1 +010 1 +100 1 +101 1 +.names $abc$4719$new_n748 yv[16] $abc$4719$new_n750 yv[15] $abc$4719$new_n745 $abc$4719$new_n753 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names yv[15] $abc$4719$new_n745 yv[16] $abc$4719$new_n750 $abc$4719$new_n742 $abc$4719$new_n754 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[20] state[3] state[2] state[4] $abc$4719$new_n630 $abc$4719$new_n755 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +.names pre_valid yv[18] $abc$4719$new_n758 $abc$4719$new_n757 prey[18] $0\yv[20:0][18] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[17] $abc$4719$new_n755 yv[20] $abc$4719$new_n754 $abc$4719$new_n753 $abc$4719$new_n757 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[20] state[3] state[2] state[4] $abc$4719$new_n658 $abc$4719$new_n758 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +.names pre_valid yv[19] $abc$4719$new_n763 $abc$4719$new_n760 prey[19] $0\yv[20:0][19] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n761 $abc$4719$new_n762 $abc$4719$new_n760 +000 1 +001 1 +100 1 +110 1 +.names yv[17] $abc$4719$new_n755 yv[18] $abc$4719$new_n758 $abc$4719$new_n754 $abc$4719$new_n761 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n755 yv[17] yv[18] $abc$4719$new_n758 $abc$4719$new_n753 $abc$4719$new_n762 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names state[3] state[4] xv[20] $abc$4719$new_n670 $abc$4719$new_n763 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names pre_valid xv[20] $abc$4719$new_n765 prey[20] $0\yv[20:0][20] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[20] $abc$4719$new_n763 yv[19] $abc$4719$new_n762 $abc$4719$new_n761 $abc$4719$new_n765 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names pre_valid xv[0] $abc$4719$new_n767 prex[0] $0\xv[20:0][0] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n767 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names state[2] $abc$4719$new_n769 yv[20] $abc$4719$new_n768 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] $abc$4719$new_n770 yv[19] yv[18] $abc$4719$new_n769 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[17] yv[16] $abc$4719$new_n770 +000 1 +010 1 +100 1 +101 1 +.names $abc$4719$new_n777 state[4] $abc$4719$new_n779 $abc$4719$new_n772 state[3] $abc$4719$new_n771 +00000 1 +00010 1 +00011 1 +.names state[2] $abc$4719$new_n774 $abc$4719$new_n773 $abc$4719$new_n776 $abc$4719$new_n775 $abc$4719$new_n772 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names state[0] state[1] yv[9] yv[8] $abc$4719$new_n773 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] yv[11] yv[10] $abc$4719$new_n774 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[0] state[1] yv[13] yv[12] $abc$4719$new_n775 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] yv[15] yv[14] $abc$4719$new_n776 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$4719$new_n362 $abc$4719$new_n778 yv[0] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] $abc$4719$new_n777 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names state[1] state[0] yv[3] yv[1] yv[2] $abc$4719$new_n778 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] state[1] state[3] $abc$4719$new_n780 $abc$4719$new_n781 $abc$4719$new_n779 +10000 1 +10001 1 +11000 1 +11010 1 +.names state[0] yv[5] yv[4] $abc$4719$new_n780 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[7] yv[6] $abc$4719$new_n781 +000 1 +010 1 +100 1 +101 1 +.names state[4] state[3] yv[20] $abc$4719$new_n782 +100 1 +101 1 +110 1 +.names pre_valid $abc$4719$new_n784 prex[1] $0\xv[20:0][1] +010 1 +011 1 +101 1 +111 1 +.names xv[1] $abc$4719$new_n984 xv[0] yv[20] $abc$4719$new_n767 $abc$4719$new_n784 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names state[1] state[0] $abc$4719$new_n788 yv[12] yv[11] $abc$4719$new_n787 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[10] yv[9] $abc$4719$new_n788 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n790 yv[16] yv[15] $abc$4719$new_n789 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[14] yv[13] $abc$4719$new_n790 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n793 yv[6] yv[5] $abc$4719$new_n792 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] yv[8] yv[7] $abc$4719$new_n793 +000 1 +010 1 +100 1 +101 1 +.names state[4] state[3] state[2] yv[20] $abc$4719$new_n795 $abc$4719$new_n794 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[1] state[0] $abc$4719$new_n796 yv[20] yv[19] $abc$4719$new_n795 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[18] yv[17] $abc$4719$new_n796 +000 1 +010 1 +100 1 +101 1 +.names state[4] $abc$4719$new_n798 $abc$4719$new_n362 $abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[16] yv[2] $abc$4719$new_n797 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names state[1] state[0] yv[4] yv[3] yv[1] $abc$4719$new_n798 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid xv[2] $abc$4719$new_n801 $abc$4719$new_n800 prex[2] $0\xv[20:0][2] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[1] $abc$4719$new_n767 xv[0] yv[20] $abc$4719$new_n984 $abc$4719$new_n800 +00011 1 +00111 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10101 1 +11001 1 +11011 1 +11100 1 +11101 1 +.names $abc$4719$new_n810 $abc$4719$new_n986 $abc$4719$new_n802 $abc$4719$new_n801 +000 1 +.names state[3] state[2] state[4] $abc$4719$new_n803 $abc$4719$new_n805 $abc$4719$new_n802 +10000 1 +10001 1 +11000 1 +11010 1 +.names state[1] state[0] $abc$4719$new_n804 yv[11] yv[10] $abc$4719$new_n803 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] yv[13] yv[12] $abc$4719$new_n804 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n770 yv[15] yv[14] $abc$4719$new_n805 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n781 yv[9] yv[8] $abc$4719$new_n807 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[4] state[3] state[2] yv[20] $abc$4719$new_n811 $abc$4719$new_n810 +10000 1 +10010 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names state[1] state[0] yv[20] yv[19] yv[18] $abc$4719$new_n811 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid $abc$4719$new_n813 prex[3] $0\xv[20:0][3] +010 1 +011 1 +101 1 +111 1 +.names yv[20] xv[3] $abc$4719$new_n992 $abc$4719$new_n818 $abc$4719$new_n988 $abc$4719$new_n813 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[0] $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n815 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names $abc$4719$new_n984 xv[1] xv[2] $abc$4719$new_n801 $abc$4719$new_n819 $abc$4719$new_n818 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names xv[0] $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n819 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names state[2] $abc$4719$new_n823 yv[20] $abc$4719$new_n822 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] yv[20] yv[19] $abc$4719$new_n823 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names state[1] $abc$4719$new_n788 $abc$4719$new_n793 $abc$4719$new_n825 +001 1 +011 1 +110 1 +111 1 +.names state[2] $abc$4719$new_n829 $abc$4719$new_n830 $abc$4719$new_n828 +010 1 +011 1 +101 1 +111 1 +.names state[1] state[0] $abc$4719$new_n790 yv[12] yv[11] $abc$4719$new_n829 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n796 yv[16] yv[15] $abc$4719$new_n830 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid xv[4] $abc$4719$new_n995 $abc$4719$new_n832 prex[4] $0\xv[20:0][4] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[3] $abc$4719$new_n992 yv[20] $abc$4719$new_n818 $abc$4719$new_n988 $abc$4719$new_n832 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names state[2] $abc$4719$new_n769 $abc$4719$new_n835 $abc$4719$new_n834 +001 1 +011 1 +110 1 +111 1 +.names $abc$4719$new_n776 $abc$4719$new_n775 $abc$4719$new_n835 +00 1 +.names pre_valid $abc$4719$new_n840 prex[5] $0\xv[20:0][5] +000 1 +001 1 +101 1 +111 1 +.names yv[20] xv[5] $abc$4719$new_n843 $abc$4719$new_n842 $abc$4719$new_n841 $abc$4719$new_n840 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[3] $abc$4719$new_n992 xv[4] $abc$4719$new_n995 $abc$4719$new_n988 $abc$4719$new_n841 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +.names $abc$4719$new_n992 xv[3] xv[4] $abc$4719$new_n995 $abc$4719$new_n818 $abc$4719$new_n842 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names state[4] $abc$4719$new_n845 yv[20] $abc$4719$new_n844 state[3] $abc$4719$new_n843 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n789 $abc$4719$new_n795 $abc$4719$new_n844 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n787 $abc$4719$new_n792 $abc$4719$new_n845 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[4] $abc$4719$new_n852 yv[20] $abc$4719$new_n851 state[3] $abc$4719$new_n850 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n805 $abc$4719$new_n811 $abc$4719$new_n851 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n803 $abc$4719$new_n807 $abc$4719$new_n852 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid $abc$4719$new_n854 prex[7] $0\xv[20:0][7] +010 1 +011 1 +101 1 +111 1 +.names xv[7] $abc$4719$new_n857 yv[20] $abc$4719$new_n856 $abc$4719$new_n855 $abc$4719$new_n854 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names xv[5] $abc$4719$new_n843 xv[6] $abc$4719$new_n850 $abc$4719$new_n842 $abc$4719$new_n855 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$4719$new_n843 xv[5] xv[6] $abc$4719$new_n850 $abc$4719$new_n841 $abc$4719$new_n856 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names state[4] $abc$4719$new_n859 yv[20] $abc$4719$new_n858 state[3] $abc$4719$new_n857 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n830 $abc$4719$new_n823 $abc$4719$new_n858 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n825 $abc$4719$new_n829 $abc$4719$new_n859 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[4] state[3] yv[20] $abc$4719$new_n768 $abc$4719$new_n772 $abc$4719$new_n864 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid $abc$4719$new_n866 prex[9] $0\xv[20:0][9] +010 1 +011 1 +101 1 +111 1 +.names xv[9] $abc$4719$new_n869 yv[20] $abc$4719$new_n868 $abc$4719$new_n867 $abc$4719$new_n866 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names xv[7] $abc$4719$new_n857 xv[8] $abc$4719$new_n864 $abc$4719$new_n855 $abc$4719$new_n867 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7] xv[8] $abc$4719$new_n857 $abc$4719$new_n864 $abc$4719$new_n856 $abc$4719$new_n868 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$4719$new_n870 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n787 $abc$4719$new_n789 $abc$4719$new_n869 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] yv[20] $abc$4719$new_n795 $abc$4719$new_n870 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid xv[10] $abc$4719$new_n873 $abc$4719$new_n872 prex[10] $0\xv[20:0][10] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[9] yv[20] $abc$4719$new_n869 $abc$4719$new_n868 $abc$4719$new_n867 $abc$4719$new_n872 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names $abc$4719$new_n874 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n803 $abc$4719$new_n805 $abc$4719$new_n873 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] yv[20] $abc$4719$new_n811 $abc$4719$new_n874 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid $abc$4719$new_n876 prex[11] $0\xv[20:0][11] +010 1 +011 1 +101 1 +111 1 +.names xv[11] $abc$4719$new_n879 yv[20] $abc$4719$new_n878 $abc$4719$new_n877 $abc$4719$new_n876 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names xv[9] $abc$4719$new_n869 xv[10] $abc$4719$new_n873 $abc$4719$new_n867 $abc$4719$new_n877 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9] xv[10] $abc$4719$new_n869 $abc$4719$new_n873 $abc$4719$new_n868 $abc$4719$new_n878 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names state[4] state[3] yv[20] $abc$4719$new_n828 $abc$4719$new_n822 $abc$4719$new_n879 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid xv[12] $abc$4719$new_n882 $abc$4719$new_n881 prex[12] $0\xv[20:0][12] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[11] yv[20] $abc$4719$new_n879 $abc$4719$new_n878 $abc$4719$new_n877 $abc$4719$new_n881 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n834 yv[20] $abc$4719$new_n882 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4719$new_n884 prex[13] $0\xv[20:0][13] +000 1 +001 1 +101 1 +111 1 +.names xv[13] $abc$4719$new_n887 yv[20] $abc$4719$new_n886 $abc$4719$new_n885 $abc$4719$new_n884 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[11] $abc$4719$new_n879 xv[12] $abc$4719$new_n882 $abc$4719$new_n877 $abc$4719$new_n885 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11] xv[12] $abc$4719$new_n879 $abc$4719$new_n882 $abc$4719$new_n878 $abc$4719$new_n886 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n844 yv[20] $abc$4719$new_n887 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4719$new_n889 prex[14] $0\xv[20:0][14] +000 1 +001 1 +101 1 +111 1 +.names $abc$4719$new_n892 yv[20] $abc$4719$new_n891 $abc$4719$new_n890 $abc$4719$new_n889 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names xv[13] $abc$4719$new_n887 $abc$4719$new_n885 $abc$4719$new_n890 +010 1 +100 1 +110 1 +111 1 +.names xv[13] $abc$4719$new_n887 $abc$4719$new_n886 $abc$4719$new_n891 +001 1 +100 1 +101 1 +111 1 +.names xv[14] $abc$4719$new_n893 $abc$4719$new_n892 +01 1 +10 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n851 yv[20] $abc$4719$new_n893 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[15] $abc$4719$new_n896 $abc$4719$new_n895 prex[15] $0\xv[20:0][15] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[14] yv[20] $abc$4719$new_n893 $abc$4719$new_n891 $abc$4719$new_n890 $abc$4719$new_n895 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n858 yv[20] $abc$4719$new_n896 +010 1 +011 1 +100 1 +110 1 +.names $abc$4719$new_n892 xv[13] $abc$4719$new_n887 $abc$4719$new_n886 $abc$4719$new_n900 +0001 1 +0100 1 +0101 1 +0111 1 +.names $abc$4719$new_n896 xv[15] $abc$4719$new_n901 +10 1 +.names xv[14] $abc$4719$new_n893 xv[15] $abc$4719$new_n896 $abc$4719$new_n902 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$4719$new_n906 xv[13] $abc$4719$new_n887 $abc$4719$new_n885 $abc$4719$new_n892 $abc$4719$new_n904 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[14] $abc$4719$new_n893 xv[15] $abc$4719$new_n896 $abc$4719$new_n906 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n768 yv[20] $abc$4719$new_n907 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[17] $abc$4719$new_n912 $abc$4719$new_n909 prex[17] $0\xv[20:0][17] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n910 $abc$4719$new_n911 $abc$4719$new_n909 +010 1 +011 1 +100 1 +110 1 +.names xv[16] $abc$4719$new_n907 $abc$4719$new_n902 $abc$4719$new_n900 $abc$4719$new_n901 $abc$4719$new_n910 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$new_n904 xv[16] $abc$4719$new_n907 xv[15] $abc$4719$new_n896 $abc$4719$new_n911 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 yv[20] $abc$4719$new_n795 $abc$4719$new_n912 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names pre_valid xv[18] $abc$4719$new_n915 $abc$4719$new_n914 prex[18] $0\xv[20:0][18] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[17] yv[20] $abc$4719$new_n912 $abc$4719$new_n911 $abc$4719$new_n910 $abc$4719$new_n914 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 yv[20] $abc$4719$new_n811 $abc$4719$new_n915 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names pre_valid xv[19] $abc$4719$new_n920 $abc$4719$new_n917 prex[19] $0\xv[20:0][19] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n918 $abc$4719$new_n919 $abc$4719$new_n917 +001 1 +011 1 +110 1 +111 1 +.names xv[17] $abc$4719$new_n912 xv[18] $abc$4719$new_n915 $abc$4719$new_n911 $abc$4719$new_n918 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n912 xv[17] xv[18] $abc$4719$new_n915 $abc$4719$new_n910 $abc$4719$new_n919 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n822 yv[20] $abc$4719$new_n920 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[20] $abc$4719$new_n922 prex[20] $0\xv[20:0][20] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[20] xv[19] $abc$4719$new_n920 $abc$4719$new_n919 $abc$4719$new_n918 $abc$4719$new_n922 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] $0\preph[20:0][19] +01 1 +10 1 +.names state[1] state[0] $auto$alumacc.cc:485:replace_alu$735.Y[1] +01 1 +10 1 +.names i_yval[12] i_xval[0] i_xval[12] $abc$4719$new_n418 $abc$4719$new_n419 $0\prex[20:0][7] +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$4719$new_n928 $abc$4719$new_n434 $abc$4719$new_n430 $0\prex[20:0][8] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n422 $abc$4719$new_n432 $abc$4719$new_n427 $abc$4719$new_n928 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4719$new_n933 $abc$4719$new_n445 $abc$4719$new_n453 $0\prex[20:0][10] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n448 $abc$4719$new_n451 $abc$4719$new_n455 $abc$4719$new_n933 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n935 $abc$4719$new_n445 $abc$4719$new_n464 $0\prex[20:0][11] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n458 $abc$4719$new_n462 $abc$4719$new_n466 $abc$4719$new_n935 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n937 $abc$4719$new_n445 $abc$4719$new_n473 $0\prex[20:0][12] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n470 $abc$4719$new_n474 $abc$4719$new_n472 $abc$4719$new_n937 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n939 $abc$4719$new_n445 $abc$4719$new_n483 $0\prex[20:0][13] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n478 $abc$4719$new_n481 $abc$4719$new_n485 $abc$4719$new_n939 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n941 $abc$4719$new_n445 $abc$4719$new_n494 $0\prex[20:0][14] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n489 $abc$4719$new_n492 $abc$4719$new_n495 $abc$4719$new_n941 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n445 i_yval[9] i_xval[9] $abc$4719$new_n507 $abc$4719$new_n943 $0\prex[20:0][15] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n498 $abc$4719$new_n502 $abc$4719$new_n504 $abc$4719$new_n943 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n945 $abc$4719$new_n445 $abc$4719$new_n516 $0\prex[20:0][16] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n510 $abc$4719$new_n514 $abc$4719$new_n517 $abc$4719$new_n945 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n947 $abc$4719$new_n445 $abc$4719$new_n528 $0\prex[20:0][17] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n519 $abc$4719$new_n524 $abc$4719$new_n526 $abc$4719$new_n947 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n535 $abc$4719$new_n537 $0\prex[20:0][19] +1110 1 +.names state[2] state[1] state[0] $auto$alumacc.cc:485:replace_alu$735.Y[2] +011 1 +100 1 +101 1 +110 1 +.names state[3] state[1] state[0] state[2] $auto$alumacc.cc:485:replace_alu$735.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names state[4] state[1] state[0] state[3] state[2] $auto$alumacc.cc:485:replace_alu$735.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names idle o_busy +0 1 +.names state[0] $auto$alumacc.cc:485:replace_alu$735.X[0] +0 1 +.names $auto$alumacc.cc:485:replace_alu$735.Y[1] $abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[14] +0 1 +.names $abc$4719$new_n967 i_xval[12] $abc$4719$new_n537 i_yval[12] $abc$4719$new_n535 $0\prey[20:0][20] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +.names i_yval[12] $abc$4719$new_n507 i_yval[9] i_xval[9] $abc$4719$new_n502 $abc$4719$new_n964 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n964 $abc$4719$new_n504 $abc$4719$new_n498 $0\prey[20:0][15] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[12] $abc$4719$new_n529 i_yval[11] i_xval[11] $abc$4719$new_n535 $abc$4719$new_n966 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n966 $abc$4719$new_n533 $abc$4719$new_n534 $abc$4719$new_n967 +00000 1 +00001 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[3] state[2] $abc$4719$new_n635 $abc$4719$new_n638 $abc$4719$new_n633 $abc$4719$new_n968 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[1] $abc$4719$new_n1009 yv[20] $abc$4719$new_n648 $abc$4719$new_n646 $abc$4719$new_n971 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4719$new_n649 yv[2] $abc$4719$new_n971 prey[2] $0\yv[20:0][2] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$4719$new_n657 $abc$4719$new_n654 $abc$4719$new_n650 $abc$4719$new_n973 +000 1 +.names $abc$4719$new_n1009 $abc$4719$new_n646 $abc$4719$new_n973 yv[2] yv[1] $abc$4719$new_n974 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +.names state[1] state[0] $abc$4719$new_n642 xv[6] xv[5] $abc$4719$new_n975 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$4719$new_n666 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n672 $abc$4719$new_n975 $abc$4719$new_n976 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[5] $abc$4719$new_n684 yv[20] $abc$4719$new_n683 $abc$4719$new_n682 $abc$4719$new_n977 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4719$new_n691 $abc$4719$new_n977 prey[6] $0\yv[20:0][6] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[9] $abc$4719$new_n714 yv[20] $abc$4719$new_n713 $abc$4719$new_n711 $abc$4719$new_n979 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4719$new_n720 yv[10] $abc$4719$new_n979 prey[10] $0\yv[20:0][10] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[13] $abc$4719$new_n734 yv[20] $abc$4719$new_n733 $abc$4719$new_n732 $abc$4719$new_n981 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4719$new_n739 yv[14] $abc$4719$new_n981 prey[14] $0\yv[20:0][14] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names state[3] state[2] $abc$4719$new_n789 $abc$4719$new_n792 $abc$4719$new_n787 $abc$4719$new_n983 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n794 $abc$4719$new_n983 $abc$4719$new_n797 $abc$4719$new_n984 +000 1 +001 1 +010 1 +.names state[1] state[0] $abc$4719$new_n780 yv[3] yv[2] $abc$4719$new_n985 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n807 $abc$4719$new_n985 $abc$4719$new_n986 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$4719$new_n986 $abc$4719$new_n810 $abc$4719$new_n802 $abc$4719$new_n987 +000 1 +.names $abc$4719$new_n987 $abc$4719$new_n984 $abc$4719$new_n815 xv[2] xv[1] $abc$4719$new_n988 +00000 1 +00001 1 +00100 1 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +.names state[1] state[0] yv[6] yv[4] $abc$4719$new_n989 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$4719$new_n989 state[3] state[0] yv[5] yv[3] $abc$4719$new_n990 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names state[4] state[3] state[2] $abc$4719$new_n825 $abc$4719$new_n990 $abc$4719$new_n991 +00001 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names state[3] $abc$4719$new_n782 $abc$4719$new_n991 $abc$4719$new_n822 $abc$4719$new_n828 $abc$4719$new_n992 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names state[2] state[0] state[1] yv[9] yv[8] $abc$4719$new_n993 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n993 state[2] $abc$4719$new_n774 $abc$4719$new_n781 $abc$4719$new_n780 $abc$4719$new_n994 +00001 1 +00011 1 +00101 1 +00111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[4] state[3] yv[20] $abc$4719$new_n994 $abc$4719$new_n834 $abc$4719$new_n995 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names xv[5] $abc$4719$new_n843 yv[20] $abc$4719$new_n842 $abc$4719$new_n841 $abc$4719$new_n996 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10101 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4719$new_n850 xv[6] $abc$4719$new_n996 prex[6] $0\xv[20:0][6] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[7] $abc$4719$new_n857 yv[20] $abc$4719$new_n855 $abc$4719$new_n856 $abc$4719$new_n998 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10101 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4719$new_n864 xv[8] $abc$4719$new_n998 prex[8] $0\xv[20:0][8] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4719$new_n907 xv[16] prex[16] $abc$4719$new_n1000 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[20] $abc$4719$new_n896 xv[15] $abc$4719$new_n902 $abc$4719$new_n900 $abc$4719$new_n1001 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4719$new_n1000 $abc$4719$new_n1001 pre_valid yv[20] $abc$4719$new_n904 $0\xv[20:0][16] +00010 1 +00011 1 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[12] i_xval[3] i_xval[12] $abc$4719$new_n444 $abc$4719$new_n443 $abc$4719$new_n1003 +00000 1 +00001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[12] $abc$4719$new_n1003 i_yval[3] $abc$4719$new_n437 $abc$4719$new_n440 $0\prex[20:0][9] +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_xval[12] $abc$4719$new_n529 i_yval[11] i_xval[11] $abc$4719$new_n535 $abc$4719$new_n1005 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_xval[12] $abc$4719$new_n533 $abc$4719$new_n1005 $abc$4719$new_n534 $abc$4719$new_n1006 +0000 1 +0010 1 +0100 1 +0110 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_yval[12] $abc$4719$new_n1005 i_xval[12] $abc$4719$new_n537 $abc$4719$new_n1006 $0\prex[20:0][18] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] xv[20] $abc$4719$new_n630 $abc$4719$new_n1008 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01110 1 +01111 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$4719$new_n1008 state[4] $abc$4719$new_n968 $abc$4719$new_n641 $abc$4719$new_n1009 +0000 1 +0001 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4552 Q=o_aux +.subckt dff C=i_clk D=$0\preph[20:0][19] Q=preph[19] +.subckt dff C=i_clk D=i_yval[12] Q=preph[20] +.subckt sdffrn C=i_clk D=$false Q=prex[0] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[1] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[2] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[3] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[4] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[5] RN=i_xval[12] +.subckt dff C=i_clk D=$0\prex[20:0][6] Q=prex[6] +.subckt dff C=i_clk D=$0\prex[20:0][7] Q=prex[7] +.subckt dff C=i_clk D=$0\prex[20:0][8] Q=prex[8] +.subckt dff C=i_clk D=$0\prex[20:0][9] Q=prex[9] +.subckt dff C=i_clk D=$0\prex[20:0][10] Q=prex[10] +.subckt dff C=i_clk D=$0\prex[20:0][11] Q=prex[11] +.subckt dff C=i_clk D=$0\prex[20:0][12] Q=prex[12] +.subckt dff C=i_clk D=$0\prex[20:0][13] Q=prex[13] +.subckt dff C=i_clk D=$0\prex[20:0][14] Q=prex[14] +.subckt dff C=i_clk D=$0\prex[20:0][15] Q=prex[15] +.subckt dff C=i_clk D=$0\prex[20:0][16] Q=prex[16] +.subckt dff C=i_clk D=$0\prex[20:0][17] Q=prex[17] +.subckt dff C=i_clk D=$0\prex[20:0][18] Q=prex[18] +.subckt dff C=i_clk D=$0\prex[20:0][19] Q=prex[19] +.subckt dff C=i_clk D=$false Q=prex[20] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[14] Q=cangle[14] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[16] Q=cangle[16] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] Q=cangle[17] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[10] Q=cangle[10] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[11] Q=cangle[11] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[12] Q=cangle[12] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[13] Q=cangle[13] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[2] Q=cangle[2] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[3] Q=cangle[3] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[4] Q=cangle[4] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[5] Q=cangle[5] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[6] Q=cangle[6] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[7] Q=cangle[7] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[8] Q=cangle[8] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[9] Q=cangle[9] R=state[4] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[0] Q=cangle[0] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[1] Q=cangle[1] +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[0] Q=ph[0] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[1] Q=ph[1] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[2] Q=ph[2] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[3] Q=ph[3] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[4] Q=ph[4] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[5] Q=ph[5] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[6] Q=ph[6] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[7] Q=ph[7] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[8] Q=ph[8] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[9] Q=ph[9] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[10] Q=ph[10] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[11] Q=ph[11] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[12] Q=ph[12] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[13] Q=ph[13] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[14] Q=ph[14] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[15] Q=ph[15] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[16] Q=ph[16] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[17] Q=ph[17] R=pre_valid +.subckt sdffs C=i_clk D=$abc$4719$procmux$562_Y[18] Q=ph[18] S=pre_valid +.subckt sdffs C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4558 Q=idle S=i_reset +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4550 Q=o_mag[0] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4548 Q=o_mag[1] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4546 Q=o_mag[2] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4544 Q=o_mag[3] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4542 Q=o_mag[4] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4540 Q=o_mag[5] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4538 Q=o_mag[6] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4536 Q=o_mag[7] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4534 Q=o_mag[8] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4532 Q=o_mag[9] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4530 Q=o_mag[10] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4528 Q=o_mag[11] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4556 Q=o_mag[12] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4526 Q=o_phase[0] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4524 Q=o_phase[1] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4522 Q=o_phase[2] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4520 Q=o_phase[3] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4518 Q=o_phase[4] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4516 Q=o_phase[5] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4514 Q=o_phase[6] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4512 Q=o_phase[7] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4510 Q=o_phase[8] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4508 Q=o_phase[9] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4506 Q=o_phase[10] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4504 Q=o_phase[11] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4502 Q=o_phase[12] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4500 Q=o_phase[13] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4498 Q=o_phase[14] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4496 Q=o_phase[15] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4494 Q=o_phase[16] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4492 Q=o_phase[17] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4490 Q=o_phase[18] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4488 Q=o_phase[19] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4554 Q=o_phase[20] +.subckt dff C=i_clk D=$0\xv[20:0][0] Q=xv[0] +.subckt dff C=i_clk D=$0\xv[20:0][1] Q=xv[1] +.subckt dff C=i_clk D=$0\xv[20:0][2] Q=xv[2] +.subckt dff C=i_clk D=$0\xv[20:0][3] Q=xv[3] +.subckt dff C=i_clk D=$0\xv[20:0][4] Q=xv[4] +.subckt dff C=i_clk D=$0\xv[20:0][5] Q=xv[5] +.subckt dff C=i_clk D=$0\xv[20:0][6] Q=xv[6] +.subckt dff C=i_clk D=$0\xv[20:0][7] Q=xv[7] +.subckt dff C=i_clk D=$0\xv[20:0][8] Q=xv[8] +.subckt dff C=i_clk D=$0\xv[20:0][9] Q=xv[9] +.subckt dff C=i_clk D=$0\xv[20:0][10] Q=xv[10] +.subckt dff C=i_clk D=$0\xv[20:0][11] Q=xv[11] +.subckt dff C=i_clk D=$0\xv[20:0][12] Q=xv[12] +.subckt dff C=i_clk D=$0\xv[20:0][13] Q=xv[13] +.subckt dff C=i_clk D=$0\xv[20:0][14] Q=xv[14] +.subckt dff C=i_clk D=$0\xv[20:0][15] Q=xv[15] +.subckt dff C=i_clk D=$0\xv[20:0][16] Q=xv[16] +.subckt dff C=i_clk D=$0\xv[20:0][17] Q=xv[17] +.subckt dff C=i_clk D=$0\xv[20:0][18] Q=xv[18] +.subckt dff C=i_clk D=$0\xv[20:0][19] Q=xv[19] +.subckt dff C=i_clk D=$0\xv[20:0][20] Q=xv[20] +.subckt dff C=i_clk D=$0\yv[20:0][0] Q=yv[0] +.subckt dff C=i_clk D=$0\yv[20:0][1] Q=yv[1] +.subckt dff C=i_clk D=$0\yv[20:0][2] Q=yv[2] +.subckt dff C=i_clk D=$0\yv[20:0][3] Q=yv[3] +.subckt dff C=i_clk D=$0\yv[20:0][4] Q=yv[4] +.subckt dff C=i_clk D=$0\yv[20:0][5] Q=yv[5] +.subckt dff C=i_clk D=$0\yv[20:0][6] Q=yv[6] +.subckt dff C=i_clk D=$0\yv[20:0][7] Q=yv[7] +.subckt dff C=i_clk D=$0\yv[20:0][8] Q=yv[8] +.subckt dff C=i_clk D=$0\yv[20:0][9] Q=yv[9] +.subckt dff C=i_clk D=$0\yv[20:0][10] Q=yv[10] +.subckt dff C=i_clk D=$0\yv[20:0][11] Q=yv[11] +.subckt dff C=i_clk D=$0\yv[20:0][12] Q=yv[12] +.subckt dff C=i_clk D=$0\yv[20:0][13] Q=yv[13] +.subckt dff C=i_clk D=$0\yv[20:0][14] Q=yv[14] +.subckt dff C=i_clk D=$0\yv[20:0][15] Q=yv[15] +.subckt dff C=i_clk D=$0\yv[20:0][16] Q=yv[16] +.subckt dff C=i_clk D=$0\yv[20:0][17] Q=yv[17] +.subckt dff C=i_clk D=$0\yv[20:0][18] Q=yv[18] +.subckt dff C=i_clk D=$0\yv[20:0][19] Q=yv[19] +.subckt dff C=i_clk D=$0\yv[20:0][20] Q=yv[20] +.subckt sdffr C=i_clk D=last_state Q=o_done R=i_reset +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.X[0] Q=state[0] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[1] Q=state[1] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[2] Q=state[2] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[3] Q=state[3] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[4] Q=state[4] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y Q=pre_valid R=i_reset +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.X[0] Q=cangle[15] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$901 +.subckt dff C=i_clk D=$false Q=prey[0] +.subckt dff C=i_clk D=$false Q=prey[1] +.subckt dff C=i_clk D=$false Q=prey[2] +.subckt dff C=i_clk D=$false Q=prey[3] +.subckt dff C=i_clk D=$false Q=prey[4] +.subckt dff C=i_clk D=$false Q=prey[5] +.subckt dff C=i_clk D=$0\prex[20:0][6] Q=prey[6] +.subckt dff C=i_clk D=$0\prey[20:0][7] Q=prey[7] +.subckt dff C=i_clk D=$0\prey[20:0][8] Q=prey[8] +.subckt dff C=i_clk D=$0\prey[20:0][9] Q=prey[9] +.subckt dff C=i_clk D=$0\prey[20:0][10] Q=prey[10] +.subckt dff C=i_clk D=$0\prey[20:0][11] Q=prey[11] +.subckt dff C=i_clk D=$0\prey[20:0][12] Q=prey[12] +.subckt dff C=i_clk D=$0\prey[20:0][13] Q=prey[13] +.subckt dff C=i_clk D=$0\prey[20:0][14] Q=prey[14] +.subckt dff C=i_clk D=$0\prey[20:0][15] Q=prey[15] +.subckt dff C=i_clk D=$0\prey[20:0][16] Q=prey[16] +.subckt dff C=i_clk D=$0\prey[20:0][17] Q=prey[17] +.subckt dff C=i_clk D=$0\prey[20:0][18] Q=prey[18] +.subckt dff C=i_clk D=$0\prey[20:0][19] Q=prey[19] +.subckt dff C=i_clk D=$0\prey[20:0][20] Q=prey[20] +.subckt dff C=i_clk D=$0\ph[20:0][19] Q=ph[19] +.subckt dff C=i_clk D=$0\ph[20:0][20] Q=ph[20] +.subckt sdffr C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4560 Q=aux R=i_reset +.names $false $0\preph[20:0][0] +1 1 +.names $false $0\preph[20:0][1] +1 1 +.names $false $0\preph[20:0][2] +1 1 +.names $false $0\preph[20:0][3] +1 1 +.names $false $0\preph[20:0][4] +1 1 +.names $false $0\preph[20:0][5] +1 1 +.names $false $0\preph[20:0][6] +1 1 +.names $false $0\preph[20:0][7] +1 1 +.names $false $0\preph[20:0][8] +1 1 +.names $false $0\preph[20:0][9] +1 1 +.names $false $0\preph[20:0][10] +1 1 +.names $false $0\preph[20:0][11] +1 1 +.names $false $0\preph[20:0][12] +1 1 +.names $false $0\preph[20:0][13] +1 1 +.names $false $0\preph[20:0][14] +1 1 +.names $false $0\preph[20:0][15] +1 1 +.names $false $0\preph[20:0][16] +1 1 +.names $false $0\preph[20:0][17] +1 1 +.names $true $0\preph[20:0][18] +1 1 +.names i_yval[12] $0\preph[20:0][20] +1 1 +.names $false $0\prex[20:0][0] +1 1 +.names $false $0\prex[20:0][1] +1 1 +.names $false $0\prex[20:0][2] +1 1 +.names $false $0\prex[20:0][3] +1 1 +.names $false $0\prex[20:0][4] +1 1 +.names $false $0\prex[20:0][5] +1 1 +.names $false $0\prex[20:0][20] +1 1 +.names $false $0\prey[20:0][0] +1 1 +.names $false $0\prey[20:0][1] +1 1 +.names $false $0\prey[20:0][2] +1 1 +.names $false $0\prey[20:0][3] +1 1 +.names $false $0\prey[20:0][4] +1 1 +.names $false $0\prey[20:0][5] +1 1 +.names $0\prex[20:0][6] $0\prey[20:0][6] +1 1 +.names state[1] $auto$alumacc.cc:485:replace_alu$735.X[1] +1 1 +.names state[2] $auto$alumacc.cc:485:replace_alu$735.X[2] +1 1 +.names state[3] $auto$alumacc.cc:485:replace_alu$735.X[3] +1 1 +.names state[4] $auto$alumacc.cc:485:replace_alu$735.X[4] +1 1 +.names $auto$alumacc.cc:485:replace_alu$735.X[0] $auto$alumacc.cc:485:replace_alu$735.Y[0] +1 1 +.names $false cangle[18] +1 1 +.names $false cangle[19] +1 1 +.names $false cangle[20] +1 1 +.names $false preph[0] +1 1 +.names $false preph[1] +1 1 +.names $false preph[2] +1 1 +.names $false preph[3] +1 1 +.names $false preph[4] +1 1 +.names $false preph[5] +1 1 +.names $false preph[6] +1 1 +.names $false preph[7] +1 1 +.names $false preph[8] +1 1 +.names $false preph[9] +1 1 +.names $false preph[10] +1 1 +.names $false preph[11] +1 1 +.names $false preph[12] +1 1 +.names $false preph[13] +1 1 +.names $false preph[14] +1 1 +.names $false preph[15] +1 1 +.names $false preph[16] +1 1 +.names $false preph[17] +1 1 +.names $true preph[18] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif new file mode 100644 index 00000000000..4f7f6ef8200 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif @@ -0,0 +1,525 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model smplfir +.inputs i_clk i_ce i_val[0] i_val[1] i_val[2] i_val[3] i_val[4] i_val[5] i_val[6] i_val[7] i_val[8] i_val[9] i_val[10] i_val[11] i_val[12] i_val[13] i_val[14] +.outputs o_val[0] o_val[1] o_val[2] o_val[3] o_val[4] o_val[5] o_val[6] o_val[7] o_val[8] o_val[9] o_val[10] o_val[11] o_val[12] o_val[13] o_val[14] o_val[15] +.names $false +.names $true +1 +.names $undef +.names i_ce i_val[14] delayed[14] $abc$921$new_n81 o_val[14] $abc$921$auto$rtlil.cc:2693:MuxGate$752 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[12] delayed[12] i_val[13] delayed[13] $abc$921$new_n82 $abc$921$new_n81 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[10] delayed[10] i_val[11] delayed[11] $abc$921$new_n83 $abc$921$new_n82 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[8] delayed[8] i_val[9] delayed[9] $abc$921$new_n84 $abc$921$new_n83 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[6] delayed[6] i_val[7] delayed[7] $abc$921$new_n85 $abc$921$new_n84 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[4] delayed[4] i_val[5] delayed[5] $abc$921$new_n86 $abc$921$new_n85 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[2] delayed[2] i_val[3] delayed[3] $abc$921$new_n87 $abc$921$new_n86 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[0] delayed[0] i_val[1] delayed[1] $abc$921$new_n87 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce i_val[13] delayed[13] $abc$921$new_n89 o_val[13] $abc$921$auto$rtlil.cc:2693:MuxGate$754 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[12] delayed[12] $abc$921$new_n82 $abc$921$new_n89 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[12] delayed[12] $abc$921$new_n82 o_val[12] $abc$921$auto$rtlil.cc:2693:MuxGate$756 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[11] delayed[11] $abc$921$new_n92 o_val[11] $abc$921$auto$rtlil.cc:2693:MuxGate$758 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[10] delayed[10] $abc$921$new_n83 $abc$921$new_n92 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[10] delayed[10] $abc$921$new_n83 o_val[10] $abc$921$auto$rtlil.cc:2693:MuxGate$760 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[9] delayed[9] $abc$921$new_n95 o_val[9] $abc$921$auto$rtlil.cc:2693:MuxGate$762 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[8] delayed[8] $abc$921$new_n84 $abc$921$new_n95 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[8] delayed[8] $abc$921$new_n84 o_val[8] $abc$921$auto$rtlil.cc:2693:MuxGate$764 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$921$new_n98 o_val[7] $abc$921$auto$rtlil.cc:2693:MuxGate$766 +001 1 +011 1 +110 1 +111 1 +.names i_val[7] delayed[7] i_val[6] delayed[6] $abc$921$new_n85 $abc$921$new_n98 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_ce i_val[6] delayed[6] $abc$921$new_n85 o_val[6] $abc$921$auto$rtlil.cc:2693:MuxGate$768 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[5] delayed[5] $abc$921$new_n101 o_val[5] $abc$921$auto$rtlil.cc:2693:MuxGate$770 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[4] delayed[4] $abc$921$new_n86 $abc$921$new_n101 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[4] delayed[4] $abc$921$new_n86 o_val[4] $abc$921$auto$rtlil.cc:2693:MuxGate$772 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[3] delayed[3] $abc$921$new_n104 o_val[3] $abc$921$auto$rtlil.cc:2693:MuxGate$774 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[2] delayed[2] $abc$921$new_n87 $abc$921$new_n104 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[2] delayed[2] $abc$921$new_n87 o_val[2] $abc$921$auto$rtlil.cc:2693:MuxGate$776 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[1] delayed[1] $abc$921$new_n107 o_val[1] $abc$921$auto$rtlil.cc:2693:MuxGate$778 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_val[0] delayed[0] $abc$921$new_n107 +11 1 +.names i_ce i_val[0] delayed[0] o_val[0] $abc$921$auto$rtlil.cc:2693:MuxGate$780 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce i_val[13] delayed[13] $abc$921$auto$rtlil.cc:2693:MuxGate$782 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[12] delayed[12] $abc$921$auto$rtlil.cc:2693:MuxGate$784 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[11] delayed[11] $abc$921$auto$rtlil.cc:2693:MuxGate$786 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[10] delayed[10] $abc$921$auto$rtlil.cc:2693:MuxGate$788 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[9] delayed[9] $abc$921$auto$rtlil.cc:2693:MuxGate$790 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[8] delayed[8] $abc$921$auto$rtlil.cc:2693:MuxGate$792 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[7] delayed[7] $abc$921$auto$rtlil.cc:2693:MuxGate$794 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[6] delayed[6] $abc$921$auto$rtlil.cc:2693:MuxGate$796 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[5] delayed[5] $abc$921$auto$rtlil.cc:2693:MuxGate$798 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[4] delayed[4] $abc$921$auto$rtlil.cc:2693:MuxGate$800 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[3] delayed[3] $abc$921$auto$rtlil.cc:2693:MuxGate$802 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[2] delayed[2] $abc$921$auto$rtlil.cc:2693:MuxGate$804 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[1] delayed[1] $abc$921$auto$rtlil.cc:2693:MuxGate$806 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[0] delayed[0] $abc$921$auto$rtlil.cc:2693:MuxGate$808 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[14] delayed[14] $abc$921$auto$rtlil.cc:2693:MuxGate$810 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[14] delayed[14] $abc$921$new_n81 o_val[15] $abc$921$auto$rtlil.cc:2693:MuxGate$812 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$808 Q=delayed[0] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$806 Q=delayed[1] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$804 Q=delayed[2] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$802 Q=delayed[3] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$800 Q=delayed[4] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$798 Q=delayed[5] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$796 Q=delayed[6] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$794 Q=delayed[7] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$792 Q=delayed[8] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$790 Q=delayed[9] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$788 Q=delayed[10] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$786 Q=delayed[11] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$784 Q=delayed[12] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$782 Q=delayed[13] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$810 Q=delayed[14] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$780 Q=o_val[0] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$778 Q=o_val[1] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$776 Q=o_val[2] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$774 Q=o_val[3] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$772 Q=o_val[4] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$770 Q=o_val[5] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$768 Q=o_val[6] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$766 Q=o_val[7] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$764 Q=o_val[8] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$762 Q=o_val[9] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$760 Q=o_val[10] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$758 Q=o_val[11] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$756 Q=o_val[12] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$754 Q=o_val[13] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$752 Q=o_val[14] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$812 Q=o_val[15] +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif new file mode 100644 index 00000000000..eadfe9f56b9 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif @@ -0,0 +1,36396 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model topolar +.inputs i_clk i_reset i_ce i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_aux +.outputs o_mag[0] o_mag[1] o_mag[2] o_mag[3] o_mag[4] o_mag[5] o_mag[6] o_mag[7] o_mag[8] o_mag[9] o_mag[10] o_mag[11] o_mag[12] o_phase[0] o_phase[1] o_phase[2] o_phase[3] o_phase[4] o_phase[5] o_phase[6] o_phase[7] o_phase[8] o_phase[9] o_phase[10] o_phase[11] o_phase[12] o_phase[13] o_phase[14] o_phase[15] o_phase[16] o_phase[17] o_phase[18] o_phase[19] o_phase[20] o_aux +.names $false +.names $true +1 +.names $undef +.names i_ce ax[17] ax[16] $abc$30358$auto$rtlil.cc:2693:MuxGate$25855 +010 1 +011 1 +101 1 +111 1 +.names i_ce ax[16] ax[15] $abc$30358$auto$rtlil.cc:2693:MuxGate$25857 +010 1 +011 1 +101 1 +111 1 +.names i_ce ax[14] ax[15] $abc$30358$auto$rtlil.cc:2693:MuxGate$25859 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[13] ax[14] $abc$30358$auto$rtlil.cc:2693:MuxGate$25861 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[12] ax[13] $abc$30358$auto$rtlil.cc:2693:MuxGate$25863 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[11] ax[12] $abc$30358$auto$rtlil.cc:2693:MuxGate$25865 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[10] ax[11] $abc$30358$auto$rtlil.cc:2693:MuxGate$25867 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[9] ax[10] $abc$30358$auto$rtlil.cc:2693:MuxGate$25869 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[8] ax[9] $abc$30358$auto$rtlil.cc:2693:MuxGate$25871 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[7] ax[8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25873 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[6] ax[7] $abc$30358$auto$rtlil.cc:2693:MuxGate$25875 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[5] ax[6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25877 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[4] ax[5] $abc$30358$auto$rtlil.cc:2693:MuxGate$25879 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[3] ax[4] $abc$30358$auto$rtlil.cc:2693:MuxGate$25881 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[2] ax[3] $abc$30358$auto$rtlil.cc:2693:MuxGate$25883 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[1] ax[2] $abc$30358$auto$rtlil.cc:2693:MuxGate$25885 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[0] ax[1] $abc$30358$auto$rtlil.cc:2693:MuxGate$25887 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_aux ax[0] $abc$30358$auto$rtlil.cc:2693:MuxGate$25889 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n6162 yv[0][19] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25891 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2426 $abc$30358$new_n2425 +000 1 +001 1 +011 1 +101 1 +.names i_yval[8] $abc$30358$new_n2440 i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2427 $abc$30358$new_n2426 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[6] $abc$30358$new_n2437 i_yval[7] $abc$30358$new_n2436 $abc$30358$new_n2428 $abc$30358$new_n2427 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_xval[5] $abc$30358$new_n2435 i_yval[5] $abc$30358$new_n2429 $abc$30358$new_n2428 +0001 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2430 $abc$30358$new_n2429 +000 1 +001 1 +011 1 +101 1 +.names i_yval[3] $abc$30358$new_n2433 $abc$30358$new_n2431 $abc$30358$new_n2430 +000 1 +001 1 +011 1 +101 1 +.names i_xval[2] i_xval[0] i_xval[1] i_yval[2] $abc$30358$new_n2432 $abc$30358$new_n2431 +00000 1 +00001 1 +00011 1 +00101 1 +01001 1 +01101 1 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_xval[1] i_xval[0] i_yval[0] i_yval[1] $abc$30358$new_n2432 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names i_xval[3] i_xval[0] i_xval[2] i_xval[1] $abc$30358$new_n2433 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_xval[4] i_xval[0] i_xval[3] i_xval[2] i_xval[1] $abc$30358$new_n2434 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_xval[0] i_xval[4] i_xval[3] i_xval[2] i_xval[1] $abc$30358$new_n2435 +00000 1 +.names i_xval[7] $abc$30358$new_n2435 i_xval[6] i_xval[5] $abc$30358$new_n2436 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_xval[6] $abc$30358$new_n2435 i_xval[5] $abc$30358$new_n2437 +000 1 +001 1 +011 1 +110 1 +.names i_xval[9] $abc$30358$new_n2439 $abc$30358$new_n2438 +00 1 +11 1 +.names $abc$30358$new_n2435 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$30358$new_n2439 +10000 1 +.names i_xval[8] $abc$30358$new_n2435 i_xval[7] i_xval[6] i_xval[5] $abc$30358$new_n2440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names i_xval[10] $abc$30358$new_n2439 i_xval[9] $abc$30358$new_n2441 +000 1 +001 1 +011 1 +110 1 +.names $abc$30358$new_n2439 i_xval[10] i_xval[9] $abc$30358$new_n2442 +100 1 +.names $abc$30358$new_n2453 i_yval[11] $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2456 $abc$30358$new_n2444 +10000 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names i_yval[9] $abc$30358$new_n2438 i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2446 $abc$30358$new_n2445 +00000 1 +00110 1 +01000 1 +01001 1 +01110 1 +01111 1 +11000 1 +11110 1 +.names i_yval[7] i_yval[8] $abc$30358$new_n2436 $abc$30358$new_n2440 $abc$30358$new_n2447 $abc$30358$new_n2446 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2448 $abc$30358$new_n2447 +001 1 +100 1 +101 1 +111 1 +.names i_xval[5] $abc$30358$new_n2435 i_yval[5] $abc$30358$new_n2449 $abc$30358$new_n2448 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2450 $abc$30358$new_n2449 +001 1 +100 1 +101 1 +111 1 +.names i_yval[3] $abc$30358$new_n2433 $abc$30358$new_n2451 $abc$30358$new_n2450 +001 1 +100 1 +101 1 +111 1 +.names i_xval[2] i_yval[2] i_xval[0] i_xval[1] $abc$30358$new_n2452 $abc$30358$new_n2451 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[0] i_yval[1] i_xval[1] i_yval[0] $abc$30358$new_n2452 +0001 1 +0100 1 +0101 1 +0111 1 +1110 1 +1111 1 +.names $abc$30358$new_n2455 $abc$30358$new_n2454 $abc$30358$new_n2453 +10 1 +.names $abc$30358$new_n2442 i_xval[11] $abc$30358$new_n2454 +10 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2455 +10 1 +.names i_xval[11] $abc$30358$new_n2442 $abc$30358$new_n2456 +00 1 +11 1 +.names $abc$30358$new_n2441 i_yval[10] $abc$30358$new_n2457 +10 1 +.names i_yval[9] i_yval[10] i_xval[9] i_xval[10] $abc$30358$new_n2461 $abc$30358$new_n2460 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[7] i_yval[8] i_xval[7] i_xval[8] $abc$30358$new_n2462 $abc$30358$new_n2461 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[5] i_yval[6] i_xval[5] i_xval[6] $abc$30358$new_n2463 $abc$30358$new_n2462 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[3] i_yval[4] i_xval[3] i_xval[4] $abc$30358$new_n2464 $abc$30358$new_n2463 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[1] i_yval[2] i_xval[1] i_xval[2] $abc$30358$new_n2465 $abc$30358$new_n2464 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[0] i_xval[0] $abc$30358$new_n2465 +10 1 +.names i_yval[9] i_xval[9] i_yval[10] i_xval[10] $abc$30358$new_n2468 $abc$30358$new_n2467 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[7] i_xval[7] i_yval[8] i_xval[8] $abc$30358$new_n2469 $abc$30358$new_n2468 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[5] i_xval[5] i_yval[6] i_xval[6] $abc$30358$new_n2470 $abc$30358$new_n2469 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[3] i_xval[3] i_yval[4] i_xval[4] $abc$30358$new_n2471 $abc$30358$new_n2470 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[1] i_xval[1] i_yval[2] i_xval[2] $abc$30358$new_n2472 $abc$30358$new_n2471 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names i_yval[0] i_xval[0] $abc$30358$new_n2472 +11 1 +.names i_ce yv[0][18] $abc$30358$new_n2475 $abc$30358$new_n6162 $abc$30358$auto$rtlil.cc:2693:MuxGate$25893 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_xval[12] $abc$30358$new_n2454 $abc$30358$new_n2476 i_yval[12] $abc$30358$new_n2475 +1010 1 +1100 1 +.names i_yval[11] $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2456 $abc$30358$new_n2476 +0000 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n2478 yv[0][17] $abc$30358$new_n2483 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25895 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2479 $abc$30358$new_n2481 $abc$30358$new_n2482 $abc$30358$new_n2478 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$30358$new_n2480 $abc$30358$new_n2425 $abc$30358$new_n2479 +01 1 +10 1 +.names i_yval[11] $abc$30358$new_n2456 $abc$30358$new_n2480 +01 1 +10 1 +.names i_yval[11] i_xval[11] $abc$30358$new_n2467 $abc$30358$new_n2481 +000 1 +011 1 +101 1 +110 1 +.names i_yval[11] i_xval[11] $abc$30358$new_n2460 $abc$30358$new_n2482 +000 1 +011 1 +101 1 +110 1 +.names $abc$30358$new_n2480 $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2483 +000 1 +101 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n2485 yv[0][16] $abc$30358$new_n2489 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25897 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2486 $abc$30358$new_n2487 $abc$30358$new_n2488 $abc$30358$new_n2485 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2426 $abc$30358$new_n2486 +000 1 +011 1 +101 1 +110 1 +.names i_yval[10] i_xval[10] i_yval[9] i_xval[9] $abc$30358$new_n2468 $abc$30358$new_n2487 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[10] i_xval[10] i_yval[9] i_xval[9] $abc$30358$new_n2461 $abc$30358$new_n2488 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[10] $abc$30358$new_n2441 i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2446 $abc$30358$new_n2489 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2492 yv[0][15] $abc$30358$new_n2491 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25899 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2446 $abc$30358$new_n2491 +001 1 +010 1 +100 1 +111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2493 $abc$30358$new_n2494 $abc$30358$new_n2495 $abc$30358$new_n2492 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_yval[9] $abc$30358$new_n2438 i_yval[8] $abc$30358$new_n2440 $abc$30358$new_n2427 $abc$30358$new_n2493 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[9] i_xval[9] $abc$30358$new_n2468 $abc$30358$new_n2494 +001 1 +010 1 +100 1 +111 1 +.names i_yval[9] i_xval[9] $abc$30358$new_n2461 $abc$30358$new_n2495 +000 1 +011 1 +101 1 +110 1 +.names i_ce $abc$30358$new_n2497 yv[0][14] $abc$30358$new_n2501 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25901 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2498 $abc$30358$new_n2499 $abc$30358$new_n2500 $abc$30358$new_n2497 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[8] $abc$30358$new_n2440 $abc$30358$new_n2427 $abc$30358$new_n2498 +000 1 +011 1 +101 1 +110 1 +.names i_yval[8] i_xval[8] i_yval[7] i_xval[7] $abc$30358$new_n2469 $abc$30358$new_n2499 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[8] i_xval[8] i_yval[7] i_xval[7] $abc$30358$new_n2462 $abc$30358$new_n2500 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[8] $abc$30358$new_n2440 i_yval[7] $abc$30358$new_n2436 $abc$30358$new_n2447 $abc$30358$new_n2501 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2504 yv[0][13] $abc$30358$new_n2503 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25903 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[7] $abc$30358$new_n2436 $abc$30358$new_n2447 $abc$30358$new_n2503 +001 1 +010 1 +100 1 +111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2505 $abc$30358$new_n2506 $abc$30358$new_n2507 $abc$30358$new_n2504 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_yval[7] $abc$30358$new_n2436 i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2428 $abc$30358$new_n2505 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[7] i_xval[7] $abc$30358$new_n2469 $abc$30358$new_n2506 +000 1 +011 1 +101 1 +110 1 +.names i_yval[7] i_xval[7] $abc$30358$new_n2462 $abc$30358$new_n2507 +000 1 +011 1 +101 1 +110 1 +.names i_ce $abc$30358$new_n2509 yv[0][12] $abc$30358$new_n2513 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25905 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2510 $abc$30358$new_n2511 $abc$30358$new_n2512 $abc$30358$new_n2509 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2428 $abc$30358$new_n2510 +000 1 +011 1 +101 1 +110 1 +.names i_yval[6] i_xval[6] i_yval[5] i_xval[5] $abc$30358$new_n2470 $abc$30358$new_n2511 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[6] i_xval[6] i_yval[5] i_xval[5] $abc$30358$new_n2463 $abc$30358$new_n2512 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2448 $abc$30358$new_n2513 +001 1 +010 1 +100 1 +111 1 +.names i_ce $abc$30358$new_n2515 yv[0][11] $abc$30358$new_n2519 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25907 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2516 $abc$30358$new_n2517 $abc$30358$new_n2518 $abc$30358$new_n2515 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[5] i_xval[5] $abc$30358$new_n2435 $abc$30358$new_n2429 $abc$30358$new_n2516 +0001 1 +0010 1 +0100 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names i_yval[5] i_xval[5] $abc$30358$new_n2435 $abc$30358$new_n2449 $abc$30358$new_n2517 +0000 1 +0011 1 +0101 1 +0110 1 +1001 1 +1010 1 +1100 1 +1111 1 +.names i_yval[5] i_xval[5] $abc$30358$new_n2470 $abc$30358$new_n2518 +001 1 +010 1 +100 1 +111 1 +.names i_yval[5] i_xval[5] $abc$30358$new_n2463 $abc$30358$new_n2519 +001 1 +010 1 +100 1 +111 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2520 +11 1 +.names i_ce $abc$30358$new_n2522 yv[0][10] $abc$30358$new_n2526 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25909 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2523 $abc$30358$new_n2524 $abc$30358$new_n2525 $abc$30358$new_n2522 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2430 $abc$30358$new_n2523 +000 1 +011 1 +101 1 +110 1 +.names i_yval[4] i_xval[4] i_yval[3] i_xval[3] $abc$30358$new_n2471 $abc$30358$new_n2524 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[4] i_xval[4] i_yval[3] i_xval[3] $abc$30358$new_n2464 $abc$30358$new_n2525 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2450 $abc$30358$new_n2526 +001 1 +010 1 +100 1 +111 1 +.names $abc$30358$new_n2532 $abc$30358$new_n2471 $abc$30358$new_n2531 +00 1 +11 1 +.names i_yval[3] i_xval[3] $abc$30358$new_n2532 +00 1 +11 1 +.names $abc$30358$new_n2534 $abc$30358$new_n2431 $abc$30358$new_n2533 +01 1 +10 1 +.names i_yval[3] $abc$30358$new_n2433 $abc$30358$new_n2534 +00 1 +11 1 +.names $abc$30358$new_n2451 $abc$30358$new_n2534 $abc$30358$new_n2535 +00 1 +11 1 +.names $abc$30358$new_n2537 i_ce yv[0][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25913 +001 1 +010 1 +011 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2538 $abc$30358$new_n2542 $abc$30358$new_n2543 $abc$30358$new_n2537 +00100 1 +00110 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_yval[12] i_xval[12] i_ce $abc$30358$new_n2539 $abc$30358$new_n2541 $abc$30358$new_n2538 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2452 $abc$30358$new_n2540 $abc$30358$new_n2539 +00 1 +11 1 +.names i_yval[2] i_xval[2] i_xval[0] i_xval[1] $abc$30358$new_n2540 +0000 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names i_yval[2] i_xval[2] i_yval[1] i_xval[1] $abc$30358$new_n2472 $abc$30358$new_n2541 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_yval[2] i_xval[2] i_yval[1] i_xval[1] $abc$30358$new_n2465 $abc$30358$new_n2542 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$30358$new_n2540 $abc$30358$new_n2432 $abc$30358$new_n2543 +01 1 +10 1 +.names i_ce yv[0][7] $abc$30358$new_n2548 $abc$30358$new_n2546 $abc$30358$new_n2545 $abc$30358$auto$rtlil.cc:2693:MuxGate$25915 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2455 i_yval[1] i_xval[1] i_yval[0] i_xval[0] $abc$30358$new_n2545 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2520 $abc$30358$new_n2465 $abc$30358$new_n2547 $abc$30358$new_n2546 +100 1 +111 1 +.names i_yval[1] i_xval[1] $abc$30358$new_n2547 +00 1 +11 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2472 $abc$30358$new_n2547 $abc$30358$new_n2549 $abc$30358$new_n2548 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10110 1 +10111 1 +.names i_yval[1] i_xval[1] i_xval[0] i_yval[0] $abc$30358$new_n2549 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names i_ce i_yval[0] i_xval[0] yv[0][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25917 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[0][5] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25919 +10 1 +.names yv[0][4] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25921 +10 1 +.names yv[0][3] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25923 +10 1 +.names yv[0][2] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25925 +10 1 +.names yv[0][1] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25927 +10 1 +.names yv[0][0] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25929 +10 1 +.names $abc$30358$new_n2558 xv[0][19] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25931 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_xval[12] i_yval[12] i_ce $abc$30358$new_n2454 $abc$30358$new_n2476 $abc$30358$new_n2558 +11110 1 +.names i_xval[11] i_yval[11] $abc$30358$new_n2442 $abc$30358$new_n2425 $abc$30358$new_n2455 $abc$30358$new_n2563 +00001 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10101 1 +11001 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2565 xv[0][17] $abc$30358$new_n2455 $abc$30358$new_n2479 $abc$30358$auto$rtlil.cc:2693:MuxGate$25935 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2483 $abc$30358$new_n2481 $abc$30358$new_n2482 $abc$30358$new_n2565 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2568 xv[0][16] $abc$30358$new_n2489 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25937 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2486 $abc$30358$new_n2487 $abc$30358$new_n2488 $abc$30358$new_n2568 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2570 xv[0][15] $abc$30358$new_n2491 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25939 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2493 $abc$30358$new_n2494 $abc$30358$new_n2495 $abc$30358$new_n2570 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2572 xv[0][14] $abc$30358$new_n2498 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25941 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2501 $abc$30358$new_n2499 $abc$30358$new_n2500 $abc$30358$new_n2572 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2574 xv[0][13] $abc$30358$new_n2503 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25943 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2505 $abc$30358$new_n2506 $abc$30358$new_n2507 $abc$30358$new_n2574 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2576 xv[0][12] $abc$30358$new_n2513 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25945 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2510 $abc$30358$new_n2511 $abc$30358$new_n2512 $abc$30358$new_n2576 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2578 xv[0][11] $abc$30358$new_n2517 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25947 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2516 $abc$30358$new_n2519 $abc$30358$new_n2518 $abc$30358$new_n2578 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2580 xv[0][10] $abc$30358$new_n2523 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25949 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2526 $abc$30358$new_n2524 $abc$30358$new_n2525 $abc$30358$new_n2580 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$30358$new_n2583 $abc$30358$new_n2582 xv[0][9] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25951 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names i_ce i_xval[12] i_yval[12] $abc$30358$new_n2531 $abc$30358$new_n2533 $abc$30358$new_n2582 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2532 $abc$30358$new_n2464 $abc$30358$new_n2535 $abc$30358$new_n2583 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$30358$new_n2585 i_ce xv[0][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25953 +001 1 +010 1 +011 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2586 $abc$30358$new_n2542 $abc$30358$new_n2543 $abc$30358$new_n2585 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] i_ce $abc$30358$new_n2539 $abc$30358$new_n2541 $abc$30358$new_n2586 +00100 1 +00110 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce i_yval[0] i_xval[0] xv[0][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25957 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[0][5] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25959 +10 1 +.names xv[0][4] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25961 +10 1 +.names xv[0][3] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25963 +10 1 +.names xv[0][2] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25965 +10 1 +.names xv[0][1] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25967 +10 1 +.names xv[0][0] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25969 +10 1 +.names i_ce ph[18][19] o_phase[19] $abc$30358$auto$rtlil.cc:2693:MuxGate$25971 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][18] o_phase[18] $abc$30358$auto$rtlil.cc:2693:MuxGate$25973 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][17] o_phase[17] $abc$30358$auto$rtlil.cc:2693:MuxGate$25975 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][16] o_phase[16] $abc$30358$auto$rtlil.cc:2693:MuxGate$25977 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][15] o_phase[15] $abc$30358$auto$rtlil.cc:2693:MuxGate$25979 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][14] o_phase[14] $abc$30358$auto$rtlil.cc:2693:MuxGate$25981 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][13] o_phase[13] $abc$30358$auto$rtlil.cc:2693:MuxGate$25983 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][12] o_phase[12] $abc$30358$auto$rtlil.cc:2693:MuxGate$25985 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][11] o_phase[11] $abc$30358$auto$rtlil.cc:2693:MuxGate$25987 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][10] o_phase[10] $abc$30358$auto$rtlil.cc:2693:MuxGate$25989 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][9] o_phase[9] $abc$30358$auto$rtlil.cc:2693:MuxGate$25991 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][8] o_phase[8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25993 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][7] o_phase[7] $abc$30358$auto$rtlil.cc:2693:MuxGate$25995 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][6] o_phase[6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25997 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][5] o_phase[5] $abc$30358$auto$rtlil.cc:2693:MuxGate$25999 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][4] o_phase[4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26001 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][3] o_phase[3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26003 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][2] o_phase[2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26005 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][1] o_phase[1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26007 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][0] o_phase[0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26009 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[18][19] xv[18][18] $abc$30358$new_n2619 o_mag[11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26011 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[18][16] xv[18][17] $abc$30358$new_n2620 $abc$30358$new_n2619 +111 1 +.names xv[18][14] xv[18][15] $abc$30358$new_n2621 $abc$30358$new_n2620 +111 1 +.names xv[18][12] xv[18][13] $abc$30358$new_n2622 $abc$30358$new_n2621 +111 1 +.names xv[18][7] xv[18][8] xv[18][9] xv[18][10] xv[18][11] $abc$30358$new_n2622 +11111 1 +.names i_ce xv[18][18] $abc$30358$new_n2619 o_mag[10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26013 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[18][17] xv[18][16] $abc$30358$new_n2620 o_mag[9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26015 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[18][16] $abc$30358$new_n2620 o_mag[8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26017 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[18][15] xv[18][14] $abc$30358$new_n2621 o_mag[7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26019 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[18][14] $abc$30358$new_n2621 o_mag[6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26021 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[18][13] xv[18][12] $abc$30358$new_n2622 o_mag[5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26023 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[18][12] $abc$30358$new_n2622 o_mag[4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26025 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n2631 o_mag[3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26027 +001 1 +011 1 +110 1 +111 1 +.names xv[18][11] xv[18][7] xv[18][8] xv[18][9] xv[18][10] $abc$30358$new_n2631 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n2633 o_mag[2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26029 +001 1 +011 1 +110 1 +111 1 +.names xv[18][10] xv[18][7] xv[18][8] xv[18][9] $abc$30358$new_n2633 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[18][9] xv[18][7] xv[18][8] o_mag[1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26031 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[18][7] xv[18][8] o_mag[0] $abc$30358$new_n2636 $abc$30358$auto$rtlil.cc:2693:MuxGate$26033 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$30358$new_n2637 xv[18][4] xv[18][5] xv[18][6] $abc$30358$new_n2636 +1000 1 +.names xv[18][0] xv[18][1] xv[18][2] xv[18][3] $abc$30358$new_n2637 +0000 1 +.names i_ce xv[0][20] yv[0][19] $abc$30358$new_n2639 yv[1][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26035 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] xv[0][19] yv[0][18] $abc$30358$new_n2640 $abc$30358$new_n2649 $abc$30358$new_n2639 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][17] yv[0][16] xv[0][18] yv[0][17] $abc$30358$new_n2641 $abc$30358$new_n2640 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[0][15] yv[0][14] xv[0][16] yv[0][15] $abc$30358$new_n2642 $abc$30358$new_n2641 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][13] yv[0][12] xv[0][14] yv[0][13] $abc$30358$new_n2643 $abc$30358$new_n2642 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][11] yv[0][10] xv[0][12] yv[0][11] $abc$30358$new_n2644 $abc$30358$new_n2643 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][9] yv[0][8] xv[0][10] yv[0][9] $abc$30358$new_n2645 $abc$30358$new_n2644 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][7] yv[0][6] xv[0][8] yv[0][7] $abc$30358$new_n2646 $abc$30358$new_n2645 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][5] yv[0][4] xv[0][6] yv[0][5] $abc$30358$new_n2647 $abc$30358$new_n2646 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][3] yv[0][2] xv[0][4] yv[0][3] $abc$30358$new_n2648 $abc$30358$new_n2647 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][1] yv[0][0] xv[0][2] yv[0][1] $abc$30358$new_n2648 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[0][18] xv[0][19] yv[0][17] yv[0][18] $abc$30358$new_n2650 $abc$30358$new_n2649 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][16] xv[0][17] yv[0][15] yv[0][16] $abc$30358$new_n2651 $abc$30358$new_n2650 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][14] xv[0][15] yv[0][13] yv[0][14] $abc$30358$new_n2652 $abc$30358$new_n2651 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][13] yv[0][12] $abc$30358$new_n2665 $abc$30358$new_n2653 $abc$30358$new_n2664 $abc$30358$new_n2652 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][10] $abc$30358$new_n2654 $abc$30358$new_n2663 yv[0][9] $abc$30358$new_n2662 $abc$30358$new_n2653 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$30358$new_n2659 $abc$30358$new_n2658 $abc$30358$new_n2661 $abc$30358$new_n2655 $abc$30358$new_n2660 $abc$30358$new_n2654 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names xv[0][5] xv[0][6] yv[0][4] yv[0][5] $abc$30358$new_n2656 $abc$30358$new_n2655 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][3] xv[0][4] yv[0][2] yv[0][3] $abc$30358$new_n2657 $abc$30358$new_n2656 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][1] xv[0][2] yv[0][0] yv[0][1] $abc$30358$new_n2657 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[0][9] yv[0][8] $abc$30358$new_n2658 +01 1 +10 1 +.names xv[0][8] yv[0][7] $abc$30358$new_n2659 +10 1 +.names xv[0][7] yv[0][6] $abc$30358$new_n2660 +01 1 +10 1 +.names yv[0][7] xv[0][8] yv[0][6] xv[0][7] $abc$30358$new_n2661 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[0][11] yv[0][10] $abc$30358$new_n2662 +01 1 +10 1 +.names yv[0][8] xv[0][9] $abc$30358$new_n2663 +10 1 +.names xv[0][12] yv[0][11] $abc$30358$new_n2664 +10 1 +.names yv[0][11] xv[0][12] yv[0][10] xv[0][11] $abc$30358$new_n2665 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names i_ce xv[0][19] yv[0][18] $abc$30358$new_n2667 yv[1][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26037 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] xv[0][18] yv[0][17] $abc$30358$new_n2650 $abc$30358$new_n2668 $abc$30358$new_n2667 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][17] yv[0][16] $abc$30358$new_n2641 $abc$30358$new_n2668 +011 1 +101 1 +110 1 +111 1 +.names i_ce xv[0][18] yv[0][17] $abc$30358$new_n2670 yv[1][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26039 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2668 $abc$30358$new_n2650 $abc$30358$new_n2670 +000 1 +010 1 +100 1 +101 1 +.names i_ce xv[0][17] yv[0][16] $abc$30358$new_n2672 yv[1][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26041 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][15] xv[0][16] $abc$30358$new_n2651 $abc$30358$new_n2673 $abc$30358$new_n2672 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[0][15] yv[0][14] $abc$30358$new_n2642 $abc$30358$new_n2673 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n2675 yv[1][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26043 +001 1 +011 1 +110 1 +111 1 +.names xv[0][16] yv[0][15] yv[0][20] $abc$30358$new_n2651 $abc$30358$new_n2673 $abc$30358$new_n2675 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][15] yv[0][14] $abc$30358$new_n2677 yv[1][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26045 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] xv[0][14] yv[0][13] $abc$30358$new_n2652 $abc$30358$new_n2642 $abc$30358$new_n2677 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[0][14] yv[0][13] $abc$30358$new_n2679 yv[1][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26047 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] xv[0][13] yv[0][12] $abc$30358$new_n2643 $abc$30358$new_n2652 $abc$30358$new_n2679 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[0][13] yv[0][12] $abc$30358$new_n2681 yv[1][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26049 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2664 $abc$30358$new_n2643 $abc$30358$new_n2653 $abc$30358$new_n2665 $abc$30358$new_n2681 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[0][12] yv[0][11] $abc$30358$new_n2683 yv[1][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26051 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][10] xv[0][11] $abc$30358$new_n2644 $abc$30358$new_n2653 $abc$30358$new_n2683 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2662 $abc$30358$new_n2685 yv[1][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26053 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[0][20] xv[0][10] yv[0][9] $abc$30358$new_n2687 $abc$30358$new_n2686 $abc$30358$new_n2685 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][9] yv[0][8] $abc$30358$new_n2645 $abc$30358$new_n2686 +000 1 +001 1 +011 1 +101 1 +.names $abc$30358$new_n2663 $abc$30358$new_n2654 $abc$30358$new_n2687 +00 1 +.names i_ce $abc$30358$new_n2689 yv[1][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26055 +001 1 +011 1 +110 1 +111 1 +.names xv[0][10] yv[0][9] yv[0][20] $abc$30358$new_n2687 $abc$30358$new_n2686 $abc$30358$new_n2689 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n2691 yv[1][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26057 +001 1 +011 1 +100 1 +101 1 +.names $abc$30358$new_n2658 yv[0][20] $abc$30358$new_n2692 $abc$30358$new_n2645 $abc$30358$new_n2691 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n2659 $abc$30358$new_n2661 $abc$30358$new_n2655 $abc$30358$new_n2660 $abc$30358$new_n2692 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce xv[0][8] yv[0][7] $abc$30358$new_n2694 yv[1][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26059 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][6] xv[0][7] $abc$30358$new_n2655 $abc$30358$new_n2646 $abc$30358$new_n2694 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n2696 yv[1][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26061 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n2660 yv[0][20] $abc$30358$new_n2655 $abc$30358$new_n2646 $abc$30358$new_n2696 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names i_ce xv[0][6] yv[0][5] $abc$30358$new_n2698 yv[1][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26063 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][4] xv[0][5] $abc$30358$new_n2656 $abc$30358$new_n2647 $abc$30358$new_n2698 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[0][5] yv[0][4] $abc$30358$new_n2700 yv[1][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26065 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2647 $abc$30358$new_n2656 $abc$30358$new_n2700 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[0][4] yv[0][3] $abc$30358$new_n2702 yv[1][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26067 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][2] xv[0][3] $abc$30358$new_n2657 $abc$30358$new_n2648 $abc$30358$new_n2702 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[0][3] yv[0][2] $abc$30358$new_n2704 yv[1][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26069 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2648 $abc$30358$new_n2657 $abc$30358$new_n2704 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][2] yv[0][1] $abc$30358$new_n2706 yv[1][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26071 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[0][1] yv[0][20] yv[0][0] $abc$30358$new_n2706 +100 1 +111 1 +.names i_ce xv[0][1] yv[0][0] yv[1][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26073 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n2709 xv[0][19] xv[1][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26075 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[0][20] yv[0][19] xv[0][18] $abc$30358$new_n2719 $abc$30358$new_n2710 $abc$30358$new_n2709 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names yv[0][17] xv[0][16] xv[0][17] yv[0][18] $abc$30358$new_n2711 $abc$30358$new_n2710 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[0][14] xv[0][15] yv[0][15] yv[0][16] $abc$30358$new_n2712 $abc$30358$new_n2711 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[0][13] xv[0][12] xv[0][13] yv[0][14] $abc$30358$new_n2713 $abc$30358$new_n2712 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][11] xv[0][10] xv[0][11] yv[0][12] $abc$30358$new_n2714 $abc$30358$new_n2713 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][9] xv[0][8] xv[0][9] yv[0][10] $abc$30358$new_n2715 $abc$30358$new_n2714 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][7] xv[0][6] xv[0][7] yv[0][8] $abc$30358$new_n2716 $abc$30358$new_n2715 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][5] xv[0][4] xv[0][5] yv[0][6] $abc$30358$new_n2717 $abc$30358$new_n2716 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][3] xv[0][2] xv[0][3] yv[0][4] $abc$30358$new_n2718 $abc$30358$new_n2717 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[0][1] xv[0][0] xv[0][1] yv[0][2] $abc$30358$new_n2718 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[0][16] yv[0][17] xv[0][17] yv[0][18] $abc$30358$new_n2720 $abc$30358$new_n2719 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][14] yv[0][15] xv[0][15] yv[0][16] $abc$30358$new_n2721 $abc$30358$new_n2720 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][12] yv[0][13] xv[0][13] yv[0][14] $abc$30358$new_n2722 $abc$30358$new_n2721 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][10] yv[0][11] xv[0][11] yv[0][12] $abc$30358$new_n2723 $abc$30358$new_n2722 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][8] yv[0][9] xv[0][9] yv[0][10] $abc$30358$new_n2724 $abc$30358$new_n2723 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][6] yv[0][7] xv[0][7] yv[0][8] $abc$30358$new_n2725 $abc$30358$new_n2724 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][4] yv[0][5] xv[0][5] yv[0][6] $abc$30358$new_n2726 $abc$30358$new_n2725 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][2] yv[0][3] xv[0][3] yv[0][4] $abc$30358$new_n2727 $abc$30358$new_n2726 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][0] yv[0][1] xv[0][1] yv[0][2] $abc$30358$new_n2727 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[0][18] yv[0][19] $abc$30358$new_n2729 xv[1][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26077 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2710 $abc$30358$new_n2719 $abc$30358$new_n2729 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[0][17] yv[0][18] $abc$30358$new_n2731 xv[1][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26079 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][17] xv[0][16] $abc$30358$new_n2720 $abc$30358$new_n2711 $abc$30358$new_n2731 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][16] yv[0][17] $abc$30358$new_n2733 xv[1][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26081 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2711 $abc$30358$new_n2720 $abc$30358$new_n2733 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[0][15] yv[0][16] $abc$30358$new_n2735 xv[1][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26083 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][15] xv[0][14] $abc$30358$new_n2721 $abc$30358$new_n2712 $abc$30358$new_n2735 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2737 xv[1][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26085 +001 1 +011 1 +110 1 +111 1 +.names xv[0][14] yv[0][15] yv[0][20] $abc$30358$new_n2721 $abc$30358$new_n2712 $abc$30358$new_n2737 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[0][13] yv[0][14] $abc$30358$new_n2739 xv[1][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26087 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] xv[0][12] yv[0][13] $abc$30358$new_n2722 $abc$30358$new_n2713 $abc$30358$new_n2739 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][12] yv[0][13] $abc$30358$new_n2741 xv[1][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26089 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2713 $abc$30358$new_n2722 $abc$30358$new_n2741 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][11] yv[0][12] $abc$30358$new_n2743 xv[1][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26091 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][11] xv[0][10] $abc$30358$new_n2723 $abc$30358$new_n2714 $abc$30358$new_n2743 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][10] yv[0][11] $abc$30358$new_n2745 xv[1][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26093 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2714 $abc$30358$new_n2723 $abc$30358$new_n2745 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][9] yv[0][10] $abc$30358$new_n2747 xv[1][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26095 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][9] xv[0][8] $abc$30358$new_n2724 $abc$30358$new_n2715 $abc$30358$new_n2747 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][8] yv[0][9] $abc$30358$new_n2749 xv[1][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26097 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2715 $abc$30358$new_n2724 $abc$30358$new_n2749 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][7] yv[0][8] $abc$30358$new_n2751 xv[1][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26099 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][7] xv[0][6] $abc$30358$new_n2725 $abc$30358$new_n2716 $abc$30358$new_n2751 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][6] yv[0][7] $abc$30358$new_n2753 xv[1][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26101 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2716 $abc$30358$new_n2725 $abc$30358$new_n2753 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][5] yv[0][6] $abc$30358$new_n2755 xv[1][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26103 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][5] xv[0][4] $abc$30358$new_n2726 $abc$30358$new_n2717 $abc$30358$new_n2755 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][4] yv[0][5] $abc$30358$new_n2757 xv[1][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26105 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2717 $abc$30358$new_n2726 $abc$30358$new_n2757 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][3] yv[0][4] $abc$30358$new_n2759 xv[1][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26107 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][3] xv[0][2] $abc$30358$new_n2727 $abc$30358$new_n2718 $abc$30358$new_n2759 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][2] yv[0][3] $abc$30358$new_n2761 xv[1][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26109 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2718 $abc$30358$new_n2727 $abc$30358$new_n2761 +000 1 +010 1 +100 1 +101 1 +.names i_ce $abc$30358$new_n2763 xv[1][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26111 +001 1 +011 1 +110 1 +111 1 +.names xv[0][1] yv[0][2] yv[0][20] xv[0][0] yv[0][1] $abc$30358$new_n2763 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[0][0] yv[0][1] xv[1][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26113 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[1][19] $abc$30358$new_n2766 ph[2][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26115 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[1][18] $abc$30358$new_n2767 $abc$30358$new_n2770 $abc$30358$new_n2766 +000 1 +010 1 +100 1 +101 1 +.names ph[1][17] yv[1][20] ph[1][16] ph[1][15] $abc$30358$new_n2768 $abc$30358$new_n2767 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names ph[1][14] $abc$30358$new_n2769 ph[1][13] $abc$30358$new_n2768 +100 1 +101 1 +111 1 +.names ph[1][8] ph[1][9] ph[1][10] ph[1][11] ph[1][12] $abc$30358$new_n2769 +00000 1 +.names yv[1][20] ph[1][17] ph[1][16] $abc$30358$new_n2771 ph[1][15] $abc$30358$new_n2770 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +.names ph[1][14] ph[1][12] $abc$30358$new_n2772 ph[1][11] $abc$30358$new_n2771 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[1][7] ph[1][8] ph[1][9] ph[1][10] ph[1][13] $abc$30358$new_n2772 +11111 1 +.names i_ce ph[1][18] $abc$30358$new_n2770 $abc$30358$new_n2767 ph[2][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26117 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[1][17] $abc$30358$new_n2775 ph[2][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26119 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[1][20] ph[1][16] ph[1][15] $abc$30358$new_n2768 $abc$30358$new_n2771 $abc$30358$new_n2775 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2777 ph[2][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26121 +001 1 +011 1 +110 1 +111 1 +.names ph[1][16] ph[1][15] yv[1][20] $abc$30358$new_n2771 $abc$30358$new_n2768 $abc$30358$new_n2777 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n2779 ph[2][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26123 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] ph[1][15] $abc$30358$new_n2771 $abc$30358$new_n2768 $abc$30358$new_n2779 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[1][14] $abc$30358$new_n2781 ph[2][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26125 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[1][11] ph[1][12] ph[1][13] $abc$30358$new_n2782 $abc$30358$new_n2783 $abc$30358$new_n2781 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[1][8] ph[1][9] ph[1][10] yv[1][20] $abc$30358$new_n2782 +0000 1 +.names ph[1][7] ph[1][8] ph[1][9] ph[1][10] yv[1][20] $abc$30358$new_n2783 +11111 1 +.names i_ce $abc$30358$new_n2785 ph[2][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26127 +001 1 +011 1 +110 1 +111 1 +.names ph[1][11] ph[1][13] ph[1][12] $abc$30358$new_n2783 $abc$30358$new_n2782 $abc$30358$new_n2785 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n2787 ph[2][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26129 +001 1 +011 1 +100 1 +101 1 +.names ph[1][11] ph[1][12] $abc$30358$new_n2783 $abc$30358$new_n2782 $abc$30358$new_n2787 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[1][11] $abc$30358$new_n2783 $abc$30358$new_n2782 ph[2][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26131 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n2790 ph[2][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26133 +001 1 +011 1 +110 1 +111 1 +.names ph[1][8] ph[1][10] ph[1][9] yv[1][20] ph[1][7] $abc$30358$new_n2790 +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n2792 ph[2][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26135 +001 1 +011 1 +100 1 +101 1 +.names ph[1][8] ph[1][9] yv[1][20] ph[1][7] $abc$30358$new_n2792 +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names i_ce ph[1][8] yv[1][20] ph[1][7] ph[2][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26137 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce ph[1][7] yv[1][20] ph[2][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26139 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[1][20] ph[2][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26141 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[1][20] ph[2][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26143 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[1][20] ph[2][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26145 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[1][20] ph[2][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26147 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[1][20] ph[2][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26149 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[1][20] ph[2][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26151 +001 1 +011 1 +100 1 +101 1 +.names ph[2][0] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26153 +01 1 +10 1 +11 1 +.names i_ce xv[1][20] yv[1][19] $abc$30358$new_n2803 yv[2][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26155 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] xv[1][20] yv[1][18] $abc$30358$new_n2821 $abc$30358$new_n2804 $abc$30358$new_n2803 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][19] yv[1][17] $abc$30358$new_n2805 $abc$30358$new_n2804 +001 1 +100 1 +101 1 +111 1 +.names xv[1][17] xv[1][18] yv[1][15] yv[1][16] $abc$30358$new_n2806 $abc$30358$new_n2805 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][15] xv[1][16] yv[1][13] yv[1][14] $abc$30358$new_n2807 $abc$30358$new_n2806 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][14] yv[1][12] $abc$30358$new_n2820 $abc$30358$new_n2808 $abc$30358$new_n2819 $abc$30358$new_n2807 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][11] $abc$30358$new_n2809 $abc$30358$new_n2818 yv[1][9] $abc$30358$new_n2817 $abc$30358$new_n2808 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$30358$new_n2814 $abc$30358$new_n2813 $abc$30358$new_n2816 $abc$30358$new_n2810 $abc$30358$new_n2815 $abc$30358$new_n2809 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names xv[1][6] xv[1][7] yv[1][4] yv[1][5] $abc$30358$new_n2811 $abc$30358$new_n2810 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][4] xv[1][5] yv[1][2] yv[1][3] $abc$30358$new_n2812 $abc$30358$new_n2811 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][2] xv[1][3] yv[1][0] yv[1][1] $abc$30358$new_n2812 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[1][10] yv[1][8] $abc$30358$new_n2813 +01 1 +10 1 +.names xv[1][9] yv[1][7] $abc$30358$new_n2814 +10 1 +.names xv[1][8] yv[1][6] $abc$30358$new_n2815 +01 1 +10 1 +.names yv[1][7] xv[1][9] yv[1][6] xv[1][8] $abc$30358$new_n2816 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[1][12] yv[1][10] $abc$30358$new_n2817 +01 1 +10 1 +.names yv[1][8] xv[1][10] $abc$30358$new_n2818 +10 1 +.names xv[1][13] yv[1][11] $abc$30358$new_n2819 +10 1 +.names yv[1][11] xv[1][13] yv[1][10] xv[1][12] $abc$30358$new_n2820 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[1][18] yv[1][16] xv[1][19] yv[1][17] $abc$30358$new_n2822 $abc$30358$new_n2821 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[1][16] yv[1][14] xv[1][17] yv[1][15] $abc$30358$new_n2823 $abc$30358$new_n2822 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][14] yv[1][12] xv[1][15] yv[1][13] $abc$30358$new_n2824 $abc$30358$new_n2823 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][12] yv[1][10] xv[1][13] yv[1][11] $abc$30358$new_n2825 $abc$30358$new_n2824 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][10] yv[1][8] xv[1][11] yv[1][9] $abc$30358$new_n2826 $abc$30358$new_n2825 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][8] yv[1][6] xv[1][9] yv[1][7] $abc$30358$new_n2827 $abc$30358$new_n2826 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][6] yv[1][4] xv[1][7] yv[1][5] $abc$30358$new_n2828 $abc$30358$new_n2827 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[1][4] yv[1][2] xv[1][5] yv[1][3] $abc$30358$new_n2829 $abc$30358$new_n2828 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][2] yv[1][0] xv[1][3] yv[1][1] $abc$30358$new_n2829 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[1][20] yv[1][18] $abc$30358$new_n2831 yv[2][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26157 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] $abc$30358$new_n2804 $abc$30358$new_n2821 $abc$30358$new_n2831 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][19] yv[1][17] $abc$30358$new_n2833 yv[2][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26159 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] xv[1][18] yv[1][16] $abc$30358$new_n2822 $abc$30358$new_n2805 $abc$30358$new_n2833 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names i_ce xv[1][18] yv[1][16] $abc$30358$new_n2835 yv[2][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26161 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][15] xv[1][17] $abc$30358$new_n2806 $abc$30358$new_n2822 $abc$30358$new_n2835 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[1][17] yv[1][15] $abc$30358$new_n2837 yv[2][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26163 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] xv[1][16] yv[1][14] $abc$30358$new_n2823 $abc$30358$new_n2806 $abc$30358$new_n2837 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[1][16] yv[1][14] $abc$30358$new_n2839 yv[2][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26165 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] xv[1][15] yv[1][13] $abc$30358$new_n2807 $abc$30358$new_n2823 $abc$30358$new_n2839 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[1][15] yv[1][13] $abc$30358$new_n2841 yv[2][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26167 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] xv[1][14] yv[1][12] $abc$30358$new_n2824 $abc$30358$new_n2842 $abc$30358$new_n2841 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2819 $abc$30358$new_n2808 $abc$30358$new_n2820 $abc$30358$new_n2842 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n2844 yv[2][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26169 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] xv[1][14] yv[1][12] $abc$30358$new_n2824 $abc$30358$new_n2842 $abc$30358$new_n2844 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][13] yv[1][11] $abc$30358$new_n2846 yv[2][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26171 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][10] xv[1][12] $abc$30358$new_n2825 $abc$30358$new_n2808 $abc$30358$new_n2846 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2817 $abc$30358$new_n2848 yv[2][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26173 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[1][20] xv[1][11] yv[1][9] $abc$30358$new_n2850 $abc$30358$new_n2849 $abc$30358$new_n2848 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2818 $abc$30358$new_n2809 $abc$30358$new_n2849 +00 1 +.names xv[1][10] yv[1][8] $abc$30358$new_n2826 $abc$30358$new_n2850 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n2852 yv[2][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26175 +001 1 +011 1 +100 1 +101 1 +.names yv[1][20] xv[1][11] yv[1][9] $abc$30358$new_n2850 $abc$30358$new_n2849 $abc$30358$new_n2852 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2854 yv[2][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26177 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] $abc$30358$new_n2813 $abc$30358$new_n2826 $abc$30358$new_n2855 $abc$30358$new_n2854 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$30358$new_n2814 $abc$30358$new_n2816 $abc$30358$new_n2810 $abc$30358$new_n2815 $abc$30358$new_n2855 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce xv[1][9] yv[1][7] $abc$30358$new_n2857 yv[2][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26179 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][6] xv[1][8] $abc$30358$new_n2827 $abc$30358$new_n2810 $abc$30358$new_n2857 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2859 yv[2][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26181 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] $abc$30358$new_n2815 $abc$30358$new_n2827 $abc$30358$new_n2810 $abc$30358$new_n2859 +0001 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[1][7] yv[1][5] $abc$30358$new_n2861 yv[2][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26183 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][4] xv[1][6] $abc$30358$new_n2828 $abc$30358$new_n2811 $abc$30358$new_n2861 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n2863 yv[2][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26185 +001 1 +011 1 +100 1 +101 1 +.names yv[1][20] xv[1][6] yv[1][4] $abc$30358$new_n2828 $abc$30358$new_n2811 $abc$30358$new_n2863 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][5] yv[1][3] $abc$30358$new_n2865 yv[2][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26187 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][2] xv[1][4] $abc$30358$new_n2829 $abc$30358$new_n2812 $abc$30358$new_n2865 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[1][4] yv[1][2] $abc$30358$new_n2867 yv[2][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26189 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] $abc$30358$new_n2812 $abc$30358$new_n2829 $abc$30358$new_n2867 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][3] yv[1][1] $abc$30358$new_n2869 yv[2][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26191 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[1][2] yv[1][20] yv[1][0] $abc$30358$new_n2869 +100 1 +111 1 +.names i_ce xv[1][2] yv[1][0] yv[2][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26193 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n2872 xv[2][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26195 +001 1 +011 1 +110 1 +111 1 +.names xv[1][19] yv[1][20] xv[1][18] $abc$30358$new_n2882 $abc$30358$new_n2873 $abc$30358$new_n2872 +00100 1 +00110 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[1][16] yv[1][18] xv[1][17] yv[1][19] $abc$30358$new_n2874 $abc$30358$new_n2873 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][14] yv[1][16] xv[1][15] yv[1][17] $abc$30358$new_n2875 $abc$30358$new_n2874 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][12] yv[1][14] xv[1][13] yv[1][15] $abc$30358$new_n2876 $abc$30358$new_n2875 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][10] yv[1][12] xv[1][11] yv[1][13] $abc$30358$new_n2877 $abc$30358$new_n2876 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][8] yv[1][10] xv[1][9] yv[1][11] $abc$30358$new_n2878 $abc$30358$new_n2877 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][6] yv[1][8] xv[1][7] yv[1][9] $abc$30358$new_n2879 $abc$30358$new_n2878 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][4] yv[1][6] xv[1][5] yv[1][7] $abc$30358$new_n2880 $abc$30358$new_n2879 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[1][2] yv[1][4] xv[1][3] yv[1][5] $abc$30358$new_n2881 $abc$30358$new_n2880 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][0] yv[1][2] xv[1][1] yv[1][3] $abc$30358$new_n2881 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[1][18] xv[1][16] xv[1][17] yv[1][19] $abc$30358$new_n2883 $abc$30358$new_n2882 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[1][14] xv[1][15] yv[1][16] yv[1][17] $abc$30358$new_n2884 $abc$30358$new_n2883 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[1][14] xv[1][12] xv[1][13] yv[1][15] $abc$30358$new_n2885 $abc$30358$new_n2884 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][12] xv[1][10] xv[1][11] yv[1][13] $abc$30358$new_n2886 $abc$30358$new_n2885 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][10] xv[1][8] xv[1][9] yv[1][11] $abc$30358$new_n2887 $abc$30358$new_n2886 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][8] xv[1][6] xv[1][7] yv[1][9] $abc$30358$new_n2888 $abc$30358$new_n2887 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][6] xv[1][4] xv[1][5] yv[1][7] $abc$30358$new_n2889 $abc$30358$new_n2888 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][4] xv[1][2] xv[1][3] yv[1][5] $abc$30358$new_n2890 $abc$30358$new_n2889 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[1][2] xv[1][0] xv[1][1] yv[1][3] $abc$30358$new_n2890 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n2899 xv[2][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26201 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] xv[1][16] yv[1][18] $abc$30358$new_n2883 $abc$30358$new_n2874 $abc$30358$new_n2899 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][15] yv[1][17] $abc$30358$new_n2901 xv[2][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26203 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] xv[1][14] yv[1][16] $abc$30358$new_n2884 $abc$30358$new_n2875 $abc$30358$new_n2901 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n2903 xv[2][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26205 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] xv[1][14] yv[1][16] $abc$30358$new_n2884 $abc$30358$new_n2875 $abc$30358$new_n2903 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[1][13] yv[1][15] $abc$30358$new_n2905 xv[2][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26207 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][14] xv[1][12] $abc$30358$new_n2885 $abc$30358$new_n2876 $abc$30358$new_n2905 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2907 xv[2][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26209 +001 1 +011 1 +100 1 +101 1 +.names yv[1][20] xv[1][12] yv[1][14] $abc$30358$new_n2885 $abc$30358$new_n2876 $abc$30358$new_n2907 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][11] yv[1][13] $abc$30358$new_n2909 xv[2][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26211 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][12] xv[1][10] $abc$30358$new_n2886 $abc$30358$new_n2877 $abc$30358$new_n2909 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][10] yv[1][12] $abc$30358$new_n2911 xv[2][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26213 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] $abc$30358$new_n2877 $abc$30358$new_n2886 $abc$30358$new_n2911 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][9] yv[1][11] $abc$30358$new_n2913 xv[2][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26215 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][10] xv[1][8] $abc$30358$new_n2887 $abc$30358$new_n2878 $abc$30358$new_n2913 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][8] yv[1][10] $abc$30358$new_n2915 xv[2][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26217 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] $abc$30358$new_n2878 $abc$30358$new_n2887 $abc$30358$new_n2915 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][7] yv[1][9] $abc$30358$new_n2917 xv[2][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26219 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][8] xv[1][6] $abc$30358$new_n2888 $abc$30358$new_n2879 $abc$30358$new_n2917 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][6] yv[1][8] $abc$30358$new_n2919 xv[2][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26221 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] $abc$30358$new_n2879 $abc$30358$new_n2888 $abc$30358$new_n2919 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][5] yv[1][7] $abc$30358$new_n2921 xv[2][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26223 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][6] xv[1][4] $abc$30358$new_n2889 $abc$30358$new_n2880 $abc$30358$new_n2921 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2923 xv[2][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26225 +001 1 +011 1 +100 1 +101 1 +.names yv[1][20] xv[1][4] yv[1][6] $abc$30358$new_n2889 $abc$30358$new_n2880 $abc$30358$new_n2923 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][3] yv[1][5] $abc$30358$new_n2925 xv[2][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26227 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] xv[1][2] yv[1][4] $abc$30358$new_n2890 $abc$30358$new_n2881 $abc$30358$new_n2925 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][2] yv[1][4] $abc$30358$new_n2927 xv[2][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26229 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] $abc$30358$new_n2881 $abc$30358$new_n2890 $abc$30358$new_n2927 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n2929 xv[2][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26231 +001 1 +011 1 +110 1 +111 1 +.names xv[1][1] yv[1][3] yv[1][20] xv[1][0] yv[1][2] $abc$30358$new_n2929 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[1][0] yv[1][2] xv[2][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26233 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n2932 ph[2][19] ph[3][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26235 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[2][18] $abc$30358$new_n2933 $abc$30358$new_n2940 $abc$30358$new_n2932 +000 1 +001 1 +100 1 +110 1 +.names yv[2][20] $abc$30358$new_n2934 ph[2][17] $abc$30358$new_n2933 +110 1 +.names ph[2][16] $abc$30358$new_n2935 $abc$30358$new_n2934 +00 1 +.names ph[2][15] $abc$30358$new_n2936 ph[2][14] $abc$30358$new_n2935 +101 1 +110 1 +111 1 +.names ph[2][13] $abc$30358$new_n2937 ph[2][11] ph[2][12] $abc$30358$new_n2936 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[2][10] $abc$30358$new_n2938 $abc$30358$new_n2937 +00 1 +.names ph[2][9] ph[2][8] $abc$30358$new_n2939 ph[2][6] ph[2][7] $abc$30358$new_n2938 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[2][5] ph[2][3] ph[2][4] ph[2][1] ph[2][2] $abc$30358$new_n2939 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2941 ph[2][17] yv[2][20] $abc$30358$new_n2940 +110 1 +.names ph[2][16] $abc$30358$new_n2942 $abc$30358$new_n2941 +10 1 +.names ph[2][15] $abc$30358$new_n2943 ph[2][14] $abc$30358$new_n2942 +000 1 +010 1 +011 1 +.names ph[2][13] ph[2][12] $abc$30358$new_n2944 ph[2][11] $abc$30358$new_n2943 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[2][10] $abc$30358$new_n2945 $abc$30358$new_n2944 +10 1 +.names ph[2][9] ph[2][7] ph[2][8] ph[2][6] $abc$30358$new_n2946 $abc$30358$new_n2945 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[2][5] ph[2][3] ph[2][4] ph[2][1] ph[2][2] $abc$30358$new_n2946 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_ce ph[2][18] $abc$30358$new_n2940 $abc$30358$new_n2933 ph[3][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26237 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n2949 ph[3][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26239 +001 1 +011 1 +110 1 +111 1 +.names ph[2][17] yv[2][20] $abc$30358$new_n2941 $abc$30358$new_n2934 $abc$30358$new_n2949 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n2951 ph[3][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26241 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[2][16] yv[2][20] $abc$30358$new_n2942 $abc$30358$new_n2935 $abc$30358$new_n2951 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2953 ph[3][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26243 +001 1 +011 1 +110 1 +111 1 +.names ph[2][14] ph[2][15] $abc$30358$new_n2955 $abc$30358$new_n2954 $abc$30358$new_n2953 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[2][20] $abc$30358$new_n2936 $abc$30358$new_n2954 +10 1 +.names yv[2][20] $abc$30358$new_n2943 $abc$30358$new_n2955 +00 1 +.names i_ce ph[2][14] $abc$30358$new_n2955 $abc$30358$new_n2954 ph[3][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26245 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[2][13] $abc$30358$new_n2958 ph[3][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26247 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[2][11] ph[2][12] yv[2][20] $abc$30358$new_n2937 $abc$30358$new_n2944 $abc$30358$new_n2958 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2960 ph[3][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26249 +001 1 +011 1 +100 1 +101 1 +.names ph[2][12] yv[2][20] ph[2][11] $abc$30358$new_n2944 $abc$30358$new_n2937 $abc$30358$new_n2960 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n2962 ph[3][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26251 +001 1 +011 1 +110 1 +111 1 +.names ph[2][11] yv[2][20] $abc$30358$new_n2944 $abc$30358$new_n2937 $abc$30358$new_n2962 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n2964 ph[3][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26253 +001 1 +011 1 +100 1 +101 1 +.names ph[2][10] yv[2][20] $abc$30358$new_n2945 $abc$30358$new_n2938 $abc$30358$new_n2964 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n2966 ph[3][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26255 +001 1 +011 1 +100 1 +101 1 +.names ph[2][9] ph[2][8] $abc$30358$new_n2968 ph[2][7] $abc$30358$new_n2967 $abc$30358$new_n2966 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names ph[2][7] ph[2][6] yv[2][20] $abc$30358$new_n2946 $abc$30358$new_n2967 +1100 1 +.names yv[2][20] ph[2][6] $abc$30358$new_n2939 $abc$30358$new_n2968 +100 1 +.names i_ce $abc$30358$new_n2970 ph[3][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26257 +001 1 +011 1 +110 1 +111 1 +.names ph[2][8] $abc$30358$new_n2967 $abc$30358$new_n2968 ph[2][7] $abc$30358$new_n2970 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names i_ce $abc$30358$new_n2972 ph[3][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26259 +001 1 +011 1 +100 1 +101 1 +.names ph[2][7] yv[2][20] ph[2][6] $abc$30358$new_n2946 $abc$30358$new_n2939 $abc$30358$new_n2972 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n2974 ph[3][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26261 +001 1 +011 1 +100 1 +101 1 +.names ph[2][6] yv[2][20] $abc$30358$new_n2946 $abc$30358$new_n2939 $abc$30358$new_n2974 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[2][5] $abc$30358$new_n2976 ph[3][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26263 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[2][20] ph[2][1] ph[2][2] ph[2][3] ph[2][4] $abc$30358$new_n2976 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2978 ph[3][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26265 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] ph[2][4] ph[2][1] ph[2][2] ph[2][3] $abc$30358$new_n2978 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2980 ph[3][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26267 +001 1 +011 1 +100 1 +101 1 +.names ph[2][3] yv[2][20] ph[2][1] ph[2][2] $abc$30358$new_n2980 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[2][20] ph[2][1] ph[2][2] ph[3][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26269 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[2][1] ph[3][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26271 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[2][0] ph[3][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26273 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[2][20] yv[2][19] $abc$30358$new_n2985 yv[3][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26275 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][20] yv[2][18] $abc$30358$new_n3003 $abc$30358$new_n2986 $abc$30358$new_n2985 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][20] yv[2][17] $abc$30358$new_n2987 $abc$30358$new_n2986 +001 1 +100 1 +101 1 +111 1 +.names xv[2][18] xv[2][19] yv[2][15] yv[2][16] $abc$30358$new_n2988 $abc$30358$new_n2987 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][16] xv[2][17] yv[2][13] yv[2][14] $abc$30358$new_n2989 $abc$30358$new_n2988 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][15] yv[2][12] $abc$30358$new_n3002 $abc$30358$new_n2990 $abc$30358$new_n3001 $abc$30358$new_n2989 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][12] $abc$30358$new_n2991 $abc$30358$new_n3000 yv[2][9] $abc$30358$new_n2999 $abc$30358$new_n2990 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$30358$new_n2996 $abc$30358$new_n2995 $abc$30358$new_n2998 $abc$30358$new_n2992 $abc$30358$new_n2997 $abc$30358$new_n2991 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names xv[2][7] xv[2][8] yv[2][4] yv[2][5] $abc$30358$new_n2993 $abc$30358$new_n2992 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][5] xv[2][6] yv[2][2] yv[2][3] $abc$30358$new_n2994 $abc$30358$new_n2993 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][3] xv[2][4] yv[2][0] yv[2][1] $abc$30358$new_n2994 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[2][11] yv[2][8] $abc$30358$new_n2995 +01 1 +10 1 +.names xv[2][10] yv[2][7] $abc$30358$new_n2996 +10 1 +.names xv[2][9] yv[2][6] $abc$30358$new_n2997 +01 1 +10 1 +.names yv[2][7] xv[2][10] yv[2][6] xv[2][9] $abc$30358$new_n2998 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[2][13] yv[2][10] $abc$30358$new_n2999 +01 1 +10 1 +.names yv[2][8] xv[2][11] $abc$30358$new_n3000 +10 1 +.names xv[2][14] yv[2][11] $abc$30358$new_n3001 +10 1 +.names yv[2][11] xv[2][14] yv[2][10] xv[2][13] $abc$30358$new_n3002 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[2][19] yv[2][16] xv[2][20] yv[2][17] $abc$30358$new_n3004 $abc$30358$new_n3003 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][17] yv[2][14] xv[2][18] yv[2][15] $abc$30358$new_n3005 $abc$30358$new_n3004 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][15] yv[2][12] xv[2][16] yv[2][13] $abc$30358$new_n3006 $abc$30358$new_n3005 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][13] yv[2][10] xv[2][14] yv[2][11] $abc$30358$new_n3007 $abc$30358$new_n3006 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][11] yv[2][8] xv[2][12] yv[2][9] $abc$30358$new_n3008 $abc$30358$new_n3007 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][9] yv[2][6] xv[2][10] yv[2][7] $abc$30358$new_n3009 $abc$30358$new_n3008 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][7] yv[2][4] xv[2][8] yv[2][5] $abc$30358$new_n3010 $abc$30358$new_n3009 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[2][5] yv[2][2] xv[2][6] yv[2][3] $abc$30358$new_n3011 $abc$30358$new_n3010 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][3] yv[2][0] xv[2][4] yv[2][1] $abc$30358$new_n3011 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[2][20] yv[2][18] $abc$30358$new_n3013 yv[3][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26277 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] $abc$30358$new_n2986 $abc$30358$new_n3003 $abc$30358$new_n3013 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[2][20] yv[2][17] $abc$30358$new_n3015 yv[3][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26279 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][16] xv[2][19] $abc$30358$new_n3004 $abc$30358$new_n3016 $abc$30358$new_n3015 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names xv[2][18] yv[2][15] $abc$30358$new_n2988 $abc$30358$new_n3016 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3018 yv[3][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26281 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][19] yv[2][16] $abc$30358$new_n3004 $abc$30358$new_n3016 $abc$30358$new_n3018 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][18] yv[2][15] $abc$30358$new_n3020 yv[3][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26283 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][17] yv[2][14] $abc$30358$new_n3005 $abc$30358$new_n2988 $abc$30358$new_n3020 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[2][17] yv[2][14] $abc$30358$new_n3022 yv[3][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26285 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][16] yv[2][13] $abc$30358$new_n2989 $abc$30358$new_n3005 $abc$30358$new_n3022 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[2][16] yv[2][13] $abc$30358$new_n3024 yv[3][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26287 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][15] yv[2][12] $abc$30358$new_n3006 $abc$30358$new_n2989 $abc$30358$new_n3024 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[2][15] yv[2][12] $abc$30358$new_n3026 yv[3][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26289 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] $abc$30358$new_n3006 $abc$30358$new_n3001 $abc$30358$new_n3002 $abc$30358$new_n2990 $abc$30358$new_n3026 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce xv[2][14] yv[2][11] $abc$30358$new_n3028 yv[3][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26291 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][10] xv[2][13] $abc$30358$new_n3007 $abc$30358$new_n2990 $abc$30358$new_n3028 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2999 $abc$30358$new_n3030 yv[3][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26293 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[2][20] xv[2][12] yv[2][9] $abc$30358$new_n3032 $abc$30358$new_n3031 $abc$30358$new_n3030 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n3000 $abc$30358$new_n2991 $abc$30358$new_n3031 +00 1 +.names xv[2][11] yv[2][8] $abc$30358$new_n3008 $abc$30358$new_n3032 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n3034 yv[3][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26295 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][12] yv[2][9] $abc$30358$new_n3032 $abc$30358$new_n3031 $abc$30358$new_n3034 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n2995 $abc$30358$new_n3036 yv[3][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26297 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[2][20] $abc$30358$new_n3037 $abc$30358$new_n3008 $abc$30358$new_n3036 +000 1 +001 1 +100 1 +110 1 +.names $abc$30358$new_n2996 $abc$30358$new_n2998 $abc$30358$new_n2992 $abc$30358$new_n2997 $abc$30358$new_n3037 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce xv[2][10] yv[2][7] $abc$30358$new_n3039 yv[3][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26299 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][6] xv[2][9] $abc$30358$new_n3009 $abc$30358$new_n2992 $abc$30358$new_n3039 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3041 $abc$30358$new_n2997 yv[3][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26301 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[2][20] $abc$30358$new_n2992 $abc$30358$new_n3009 $abc$30358$new_n3041 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][8] yv[2][5] $abc$30358$new_n3043 yv[3][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26303 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][4] xv[2][7] $abc$30358$new_n3010 $abc$30358$new_n2993 $abc$30358$new_n3043 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3045 yv[3][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26305 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][7] yv[2][4] $abc$30358$new_n3010 $abc$30358$new_n2993 $abc$30358$new_n3045 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][6] yv[2][3] $abc$30358$new_n3047 yv[3][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26307 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][2] xv[2][5] $abc$30358$new_n3011 $abc$30358$new_n2994 $abc$30358$new_n3047 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[2][5] yv[2][2] $abc$30358$new_n3049 yv[3][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26309 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] $abc$30358$new_n2994 $abc$30358$new_n3011 $abc$30358$new_n3049 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3051 yv[3][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26311 +001 1 +011 1 +110 1 +111 1 +.names xv[2][4] yv[2][1] yv[2][20] yv[2][0] xv[2][3] $abc$30358$new_n3051 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[2][3] yv[2][0] yv[3][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26313 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[2][19] $abc$30358$new_n3054 xv[3][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26315 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[2][18] yv[2][20] $abc$30358$new_n3055 $abc$30358$new_n3064 $abc$30358$new_n3054 +1010 1 +1011 1 +1101 1 +1111 1 +.names xv[2][17] xv[2][16] yv[2][19] $abc$30358$new_n3056 $abc$30358$new_n3055 +1011 1 +1101 1 +1110 1 +1111 1 +.names xv[2][14] yv[2][17] xv[2][15] yv[2][18] $abc$30358$new_n3057 $abc$30358$new_n3056 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][12] yv[2][15] xv[2][13] yv[2][16] $abc$30358$new_n3058 $abc$30358$new_n3057 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][10] yv[2][13] xv[2][11] yv[2][14] $abc$30358$new_n3059 $abc$30358$new_n3058 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][8] yv[2][11] xv[2][9] yv[2][12] $abc$30358$new_n3060 $abc$30358$new_n3059 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][6] yv[2][9] xv[2][7] yv[2][10] $abc$30358$new_n3061 $abc$30358$new_n3060 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][4] yv[2][7] xv[2][5] yv[2][8] $abc$30358$new_n3062 $abc$30358$new_n3061 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[2][2] yv[2][5] xv[2][3] yv[2][6] $abc$30358$new_n3063 $abc$30358$new_n3062 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][0] yv[2][3] xv[2][1] yv[2][4] $abc$30358$new_n3063 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[2][17] xv[2][16] yv[2][19] $abc$30358$new_n3065 $abc$30358$new_n3064 +1000 1 +1100 1 +1101 1 +1110 1 +.names yv[2][17] xv[2][14] xv[2][15] yv[2][18] $abc$30358$new_n3066 $abc$30358$new_n3065 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[2][12] xv[2][13] yv[2][15] yv[2][16] $abc$30358$new_n3067 $abc$30358$new_n3066 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][10] xv[2][11] yv[2][13] yv[2][14] $abc$30358$new_n3068 $abc$30358$new_n3067 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[2][11] xv[2][8] xv[2][9] yv[2][12] $abc$30358$new_n3069 $abc$30358$new_n3068 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][9] xv[2][6] xv[2][7] yv[2][10] $abc$30358$new_n3070 $abc$30358$new_n3069 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][7] xv[2][4] xv[2][5] yv[2][8] $abc$30358$new_n3071 $abc$30358$new_n3070 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][5] xv[2][2] xv[2][3] yv[2][6] $abc$30358$new_n3072 $abc$30358$new_n3071 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[2][3] xv[2][0] xv[2][1] yv[2][4] $abc$30358$new_n3072 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce xv[2][17] $abc$30358$new_n3077 xv[3][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26319 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[2][20] xv[2][16] yv[2][19] $abc$30358$new_n3065 $abc$30358$new_n3056 $abc$30358$new_n3077 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n3079 xv[3][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26321 +001 1 +011 1 +100 1 +101 1 +.names yv[2][20] xv[2][16] yv[2][19] $abc$30358$new_n3065 $abc$30358$new_n3056 $abc$30358$new_n3079 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][15] yv[2][18] $abc$30358$new_n3081 xv[3][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26323 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] yv[2][17] xv[2][14] $abc$30358$new_n3066 $abc$30358$new_n3057 $abc$30358$new_n3081 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][14] yv[2][17] $abc$30358$new_n3083 xv[3][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26325 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] $abc$30358$new_n3057 $abc$30358$new_n3066 $abc$30358$new_n3083 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3089 xv[3][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26329 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][12] yv[2][15] $abc$30358$new_n3067 $abc$30358$new_n3058 $abc$30358$new_n3089 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][10] yv[2][13] $abc$30358$new_n3095 xv[3][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26333 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] $abc$30358$new_n3059 $abc$30358$new_n3068 $abc$30358$new_n3095 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][9] yv[2][12] $abc$30358$new_n3097 xv[3][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26335 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] yv[2][11] xv[2][8] $abc$30358$new_n3069 $abc$30358$new_n3060 $abc$30358$new_n3097 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][8] yv[2][11] $abc$30358$new_n3099 xv[3][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26337 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] $abc$30358$new_n3060 $abc$30358$new_n3069 $abc$30358$new_n3099 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][7] yv[2][10] $abc$30358$new_n3101 xv[3][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26339 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] yv[2][9] xv[2][6] $abc$30358$new_n3070 $abc$30358$new_n3061 $abc$30358$new_n3101 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][6] yv[2][9] $abc$30358$new_n3103 xv[3][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26341 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] $abc$30358$new_n3061 $abc$30358$new_n3070 $abc$30358$new_n3103 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][5] yv[2][8] $abc$30358$new_n3105 xv[3][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26343 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] yv[2][7] xv[2][4] $abc$30358$new_n3071 $abc$30358$new_n3062 $abc$30358$new_n3105 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3107 xv[3][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26345 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][4] yv[2][7] $abc$30358$new_n3071 $abc$30358$new_n3062 $abc$30358$new_n3107 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][3] yv[2][6] $abc$30358$new_n3109 xv[3][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26347 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] xv[2][2] yv[2][5] $abc$30358$new_n3072 $abc$30358$new_n3063 $abc$30358$new_n3109 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][2] yv[2][5] $abc$30358$new_n3111 xv[3][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26349 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] $abc$30358$new_n3063 $abc$30358$new_n3072 $abc$30358$new_n3111 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3113 xv[3][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26351 +001 1 +011 1 +110 1 +111 1 +.names xv[2][1] yv[2][4] yv[2][20] xv[2][0] yv[2][3] $abc$30358$new_n3113 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[2][0] yv[2][3] xv[3][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26353 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[3][19] $abc$30358$new_n3122 $abc$30358$new_n3116 ph[4][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26355 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n3117 ph[3][16] ph[3][17] ph[3][18] yv[3][20] $abc$30358$new_n3116 +11110 1 +.names ph[3][15] ph[3][14] ph[3][13] $abc$30358$new_n3118 $abc$30358$new_n3117 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[3][12] ph[3][10] ph[3][11] ph[3][9] $abc$30358$new_n3119 $abc$30358$new_n3118 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[3][8] $abc$30358$new_n3120 $abc$30358$new_n3119 +00 1 +.names ph[3][7] ph[3][6] $abc$30358$new_n3121 ph[3][5] $abc$30358$new_n3120 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[3][0] ph[3][1] ph[3][2] ph[3][3] ph[3][4] $abc$30358$new_n3121 +11111 1 +.names yv[3][20] $abc$30358$new_n3123 ph[3][16] ph[3][17] ph[3][18] $abc$30358$new_n3122 +11000 1 +.names ph[3][15] ph[3][14] ph[3][13] $abc$30358$new_n3124 $abc$30358$new_n3123 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[3][12] ph[3][11] $abc$30358$new_n3125 ph[3][9] ph[3][10] $abc$30358$new_n3124 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[3][8] $abc$30358$new_n3126 $abc$30358$new_n3125 +10 1 +.names ph[3][7] ph[3][5] ph[3][6] $abc$30358$new_n3127 $abc$30358$new_n3126 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names ph[3][0] ph[3][1] ph[3][2] ph[3][3] ph[3][4] $abc$30358$new_n3127 +00000 1 +.names i_ce $abc$30358$new_n3129 ph[3][18] ph[4][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26357 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[3][20] ph[3][17] ph[3][16] $abc$30358$new_n3117 $abc$30358$new_n3123 $abc$30358$new_n3129 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3131 ph[4][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26359 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][17] ph[3][16] $abc$30358$new_n3123 $abc$30358$new_n3117 $abc$30358$new_n3131 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3133 ph[4][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26361 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][16] $abc$30358$new_n3123 $abc$30358$new_n3117 $abc$30358$new_n3133 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3138 ph[4][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26365 +001 1 +011 1 +100 1 +101 1 +.names yv[3][20] ph[3][14] ph[3][13] $abc$30358$new_n3124 $abc$30358$new_n3118 $abc$30358$new_n3138 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3140 ph[4][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26367 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][13] $abc$30358$new_n3124 $abc$30358$new_n3118 $abc$30358$new_n3140 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n3142 ph[4][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26369 +001 1 +011 1 +100 1 +101 1 +.names ph[3][10] ph[3][12] ph[3][11] $abc$30358$new_n3145 $abc$30358$new_n3143 $abc$30358$new_n3142 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[3][9] $abc$30358$new_n3144 $abc$30358$new_n3143 +11 1 +.names yv[3][20] $abc$30358$new_n3119 $abc$30358$new_n3144 +00 1 +.names $abc$30358$new_n3146 ph[3][9] $abc$30358$new_n3145 +10 1 +.names yv[3][20] $abc$30358$new_n3125 $abc$30358$new_n3146 +10 1 +.names i_ce $abc$30358$new_n3148 ph[4][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26371 +001 1 +011 1 +110 1 +111 1 +.names ph[3][11] ph[3][10] $abc$30358$new_n3145 $abc$30358$new_n3143 $abc$30358$new_n3148 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[3][10] $abc$30358$new_n3145 $abc$30358$new_n3143 ph[4][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26373 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[3][9] $abc$30358$new_n3146 $abc$30358$new_n3144 ph[4][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26375 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3152 ph[4][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26377 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][8] $abc$30358$new_n3126 $abc$30358$new_n3120 $abc$30358$new_n3152 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n3154 ph[3][7] ph[4][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26379 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[3][20] ph[3][5] ph[3][6] $abc$30358$new_n3121 $abc$30358$new_n3127 $abc$30358$new_n3154 +00000 1 +00001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3156 ph[4][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26381 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][6] ph[3][5] $abc$30358$new_n3127 $abc$30358$new_n3121 $abc$30358$new_n3156 +00000 1 +00010 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3158 ph[4][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26383 +001 1 +011 1 +100 1 +101 1 +.names ph[3][3] ph[3][5] ph[3][4] $abc$30358$new_n3160 $abc$30358$new_n3159 $abc$30358$new_n3158 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[3][2] ph[3][0] ph[3][1] yv[3][20] $abc$30358$new_n3159 +1110 1 +.names yv[3][20] ph[3][0] ph[3][1] ph[3][2] $abc$30358$new_n3160 +1000 1 +.names i_ce $abc$30358$new_n3162 ph[3][4] ph[4][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26385 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[3][3] $abc$30358$new_n3159 $abc$30358$new_n3160 $abc$30358$new_n3162 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[3][3] $abc$30358$new_n3160 $abc$30358$new_n3159 ph[4][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26387 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3165 ph[4][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26389 +001 1 +011 1 +100 1 +101 1 +.names ph[3][2] yv[3][20] ph[3][0] ph[3][1] $abc$30358$new_n3165 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[3][20] ph[3][0] ph[3][1] ph[4][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26391 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[3][0] ph[4][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26393 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[3][20] yv[3][19] $abc$30358$new_n3169 yv[4][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26395 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][18] xv[3][20] $abc$30358$new_n3189 $abc$30358$new_n3170 $abc$30358$new_n3169 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$30358$new_n3171 xv[3][20] yv[3][16] yv[3][17] $abc$30358$new_n3170 +0000 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$30358$new_n3187 $abc$30358$new_n3188 yv[3][15] xv[3][19] $abc$30358$new_n3172 $abc$30358$new_n3171 +10000 1 +10100 1 +10101 1 +10110 1 +.names xv[3][17] xv[3][18] yv[3][13] yv[3][14] $abc$30358$new_n3173 $abc$30358$new_n3172 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][16] yv[3][12] $abc$30358$new_n3186 $abc$30358$new_n3174 $abc$30358$new_n3185 $abc$30358$new_n3173 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][13] $abc$30358$new_n3175 $abc$30358$new_n3184 yv[3][9] $abc$30358$new_n3183 $abc$30358$new_n3174 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$30358$new_n3180 $abc$30358$new_n3179 $abc$30358$new_n3182 $abc$30358$new_n3176 $abc$30358$new_n3181 $abc$30358$new_n3175 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names xv[3][8] xv[3][9] yv[3][4] yv[3][5] $abc$30358$new_n3177 $abc$30358$new_n3176 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][6] xv[3][7] yv[3][2] yv[3][3] $abc$30358$new_n3178 $abc$30358$new_n3177 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][4] xv[3][5] yv[3][0] yv[3][1] $abc$30358$new_n3178 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[3][12] yv[3][8] $abc$30358$new_n3179 +01 1 +10 1 +.names xv[3][11] yv[3][7] $abc$30358$new_n3180 +10 1 +.names xv[3][10] yv[3][6] $abc$30358$new_n3181 +01 1 +10 1 +.names yv[3][7] xv[3][11] yv[3][6] xv[3][10] $abc$30358$new_n3182 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[3][14] yv[3][10] $abc$30358$new_n3183 +01 1 +10 1 +.names yv[3][8] xv[3][12] $abc$30358$new_n3184 +10 1 +.names xv[3][15] yv[3][11] $abc$30358$new_n3185 +10 1 +.names yv[3][11] xv[3][15] yv[3][10] xv[3][14] $abc$30358$new_n3186 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[3][20] yv[3][17] $abc$30358$new_n3187 +00 1 +11 1 +.names xv[3][20] yv[3][16] $abc$30358$new_n3188 +01 1 +10 1 +.names xv[3][20] yv[3][16] yv[3][17] $abc$30358$new_n3190 $abc$30358$new_n3189 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[3][18] yv[3][14] xv[3][19] yv[3][15] $abc$30358$new_n3191 $abc$30358$new_n3190 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[3][16] yv[3][12] xv[3][17] yv[3][13] $abc$30358$new_n3192 $abc$30358$new_n3191 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][14] yv[3][10] xv[3][15] yv[3][11] $abc$30358$new_n3193 $abc$30358$new_n3192 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][12] yv[3][8] xv[3][13] yv[3][9] $abc$30358$new_n3194 $abc$30358$new_n3193 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][10] yv[3][6] xv[3][11] yv[3][7] $abc$30358$new_n3195 $abc$30358$new_n3194 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][8] yv[3][4] xv[3][9] yv[3][5] $abc$30358$new_n3196 $abc$30358$new_n3195 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][6] yv[3][2] xv[3][7] yv[3][3] $abc$30358$new_n3197 $abc$30358$new_n3196 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][4] yv[3][0] xv[3][5] yv[3][1] $abc$30358$new_n3197 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce $abc$30358$new_n3199 yv[4][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26397 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] xv[3][20] yv[3][18] $abc$30358$new_n3189 $abc$30358$new_n3170 $abc$30358$new_n3199 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n3201 $abc$30358$new_n3187 yv[4][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26399 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[3][20] xv[3][20] yv[3][16] $abc$30358$new_n3190 $abc$30358$new_n3202 $abc$30358$new_n3201 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[3][19] yv[3][15] $abc$30358$new_n3172 $abc$30358$new_n3202 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3204 yv[4][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26401 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] $abc$30358$new_n3188 $abc$30358$new_n3190 $abc$30358$new_n3202 $abc$30358$new_n3204 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[3][19] yv[3][15] $abc$30358$new_n3206 yv[4][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26403 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] xv[3][18] yv[3][14] $abc$30358$new_n3191 $abc$30358$new_n3172 $abc$30358$new_n3206 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[3][18] yv[3][14] $abc$30358$new_n3208 yv[4][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26405 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] xv[3][17] yv[3][13] $abc$30358$new_n3173 $abc$30358$new_n3191 $abc$30358$new_n3208 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[3][17] yv[3][13] $abc$30358$new_n3210 yv[4][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26407 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] xv[3][16] yv[3][12] $abc$30358$new_n3192 $abc$30358$new_n3173 $abc$30358$new_n3210 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[3][16] yv[3][12] $abc$30358$new_n3212 yv[4][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26409 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] $abc$30358$new_n3192 $abc$30358$new_n3185 $abc$30358$new_n3186 $abc$30358$new_n3174 $abc$30358$new_n3212 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce xv[3][15] yv[3][11] $abc$30358$new_n3214 yv[4][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26411 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][10] xv[3][14] $abc$30358$new_n3193 $abc$30358$new_n3174 $abc$30358$new_n3214 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3183 $abc$30358$new_n3216 yv[4][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26413 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[3][20] xv[3][13] yv[3][9] $abc$30358$new_n3218 $abc$30358$new_n3217 $abc$30358$new_n3216 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n3184 $abc$30358$new_n3175 $abc$30358$new_n3217 +00 1 +.names xv[3][12] yv[3][8] $abc$30358$new_n3194 $abc$30358$new_n3218 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n3220 yv[4][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26415 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] xv[3][13] yv[3][9] $abc$30358$new_n3218 $abc$30358$new_n3217 $abc$30358$new_n3220 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n3222 yv[4][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26417 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] $abc$30358$new_n3179 $abc$30358$new_n3194 $abc$30358$new_n3223 $abc$30358$new_n3222 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$30358$new_n3180 $abc$30358$new_n3182 $abc$30358$new_n3176 $abc$30358$new_n3181 $abc$30358$new_n3223 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce xv[3][11] yv[3][7] $abc$30358$new_n3225 yv[4][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26419 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][6] xv[3][10] $abc$30358$new_n3195 $abc$30358$new_n3176 $abc$30358$new_n3225 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3227 yv[4][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26421 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] $abc$30358$new_n3181 $abc$30358$new_n3195 $abc$30358$new_n3176 $abc$30358$new_n3227 +0001 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[3][9] yv[3][5] $abc$30358$new_n3229 yv[4][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26423 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][4] xv[3][8] $abc$30358$new_n3196 $abc$30358$new_n3177 $abc$30358$new_n3229 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3231 yv[4][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26425 +001 1 +011 1 +100 1 +101 1 +.names yv[3][20] xv[3][8] yv[3][4] $abc$30358$new_n3196 $abc$30358$new_n3177 $abc$30358$new_n3231 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[3][7] yv[3][3] $abc$30358$new_n3233 yv[4][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26427 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][2] xv[3][6] $abc$30358$new_n3197 $abc$30358$new_n3178 $abc$30358$new_n3233 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[3][6] yv[3][2] $abc$30358$new_n3235 yv[4][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26429 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] $abc$30358$new_n3178 $abc$30358$new_n3197 $abc$30358$new_n3235 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3237 yv[4][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26431 +001 1 +011 1 +110 1 +111 1 +.names xv[3][5] yv[3][1] yv[3][20] yv[3][0] xv[3][4] $abc$30358$new_n3237 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[3][4] yv[3][0] yv[4][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26433 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[3][19] $abc$30358$new_n3249 $abc$30358$new_n3240 xv[4][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26435 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[3][20] xv[3][17] xv[3][18] $abc$30358$new_n3241 xv[3][16] $abc$30358$new_n3240 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names xv[3][14] yv[3][18] xv[3][15] yv[3][19] $abc$30358$new_n3242 $abc$30358$new_n3241 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[3][12] yv[3][16] xv[3][13] yv[3][17] $abc$30358$new_n3243 $abc$30358$new_n3242 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][10] yv[3][14] xv[3][11] yv[3][15] $abc$30358$new_n3244 $abc$30358$new_n3243 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][8] yv[3][12] xv[3][9] yv[3][13] $abc$30358$new_n3245 $abc$30358$new_n3244 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][6] yv[3][10] xv[3][7] yv[3][11] $abc$30358$new_n3246 $abc$30358$new_n3245 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][4] yv[3][8] xv[3][5] yv[3][9] $abc$30358$new_n3247 $abc$30358$new_n3246 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[3][2] yv[3][6] xv[3][3] yv[3][7] $abc$30358$new_n3248 $abc$30358$new_n3247 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[3][0] yv[3][4] xv[3][1] yv[3][5] $abc$30358$new_n3248 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[3][20] xv[3][16] xv[3][17] xv[3][18] $abc$30358$new_n3250 $abc$30358$new_n3249 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names yv[3][18] xv[3][14] xv[3][15] yv[3][19] $abc$30358$new_n3251 $abc$30358$new_n3250 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][16] xv[3][12] xv[3][13] yv[3][17] $abc$30358$new_n3252 $abc$30358$new_n3251 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[3][10] xv[3][11] yv[3][14] yv[3][15] $abc$30358$new_n3253 $abc$30358$new_n3252 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[3][12] xv[3][8] xv[3][9] yv[3][13] $abc$30358$new_n3254 $abc$30358$new_n3253 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][10] xv[3][6] xv[3][7] yv[3][11] $abc$30358$new_n3255 $abc$30358$new_n3254 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][8] xv[3][4] xv[3][5] yv[3][9] $abc$30358$new_n3256 $abc$30358$new_n3255 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][6] xv[3][2] xv[3][3] yv[3][7] $abc$30358$new_n3257 $abc$30358$new_n3256 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[3][4] xv[3][0] xv[3][1] yv[3][5] $abc$30358$new_n3257 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce xv[3][17] xv[3][16] $abc$30358$new_n3262 xv[4][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26439 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] $abc$30358$new_n3241 $abc$30358$new_n3250 $abc$30358$new_n3262 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[3][16] $abc$30358$new_n3262 xv[4][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26441 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[3][15] yv[3][19] $abc$30358$new_n3265 xv[4][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26443 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][18] xv[3][14] $abc$30358$new_n3251 $abc$30358$new_n3242 $abc$30358$new_n3265 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3267 xv[4][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26445 +001 1 +011 1 +100 1 +101 1 +.names yv[3][20] xv[3][14] yv[3][18] $abc$30358$new_n3251 $abc$30358$new_n3242 $abc$30358$new_n3267 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][13] yv[3][17] $abc$30358$new_n3269 xv[4][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26447 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][16] xv[3][12] $abc$30358$new_n3252 $abc$30358$new_n3243 $abc$30358$new_n3269 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][12] yv[3][16] $abc$30358$new_n3271 xv[4][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26449 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] $abc$30358$new_n3243 $abc$30358$new_n3252 $abc$30358$new_n3271 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3277 xv[4][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26453 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] xv[3][10] yv[3][14] $abc$30358$new_n3253 $abc$30358$new_n3244 $abc$30358$new_n3277 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[3][9] yv[3][13] $abc$30358$new_n3279 xv[4][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26455 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][12] xv[3][8] $abc$30358$new_n3254 $abc$30358$new_n3245 $abc$30358$new_n3279 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3281 xv[4][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26457 +001 1 +011 1 +100 1 +101 1 +.names yv[3][20] xv[3][8] yv[3][12] $abc$30358$new_n3254 $abc$30358$new_n3245 $abc$30358$new_n3281 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][7] yv[3][11] $abc$30358$new_n3283 xv[4][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26459 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][10] xv[3][6] $abc$30358$new_n3255 $abc$30358$new_n3246 $abc$30358$new_n3283 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][6] yv[3][10] $abc$30358$new_n3285 xv[4][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26461 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] $abc$30358$new_n3246 $abc$30358$new_n3255 $abc$30358$new_n3285 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[3][5] yv[3][9] $abc$30358$new_n3287 xv[4][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26463 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][8] xv[3][4] $abc$30358$new_n3256 $abc$30358$new_n3247 $abc$30358$new_n3287 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][4] yv[3][8] $abc$30358$new_n3289 xv[4][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26465 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] $abc$30358$new_n3247 $abc$30358$new_n3256 $abc$30358$new_n3289 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[3][3] yv[3][7] $abc$30358$new_n3291 xv[4][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26467 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] xv[3][2] yv[3][6] $abc$30358$new_n3257 $abc$30358$new_n3248 $abc$30358$new_n3291 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][2] yv[3][6] $abc$30358$new_n3293 xv[4][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26469 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] $abc$30358$new_n3248 $abc$30358$new_n3257 $abc$30358$new_n3293 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3295 xv[4][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26471 +001 1 +011 1 +110 1 +111 1 +.names xv[3][1] yv[3][5] yv[3][20] xv[3][0] yv[3][4] $abc$30358$new_n3295 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[3][0] yv[3][4] xv[4][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26473 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3298 ph[4][19] ph[5][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26475 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[4][18] $abc$30358$new_n3299 ph[4][17] $abc$30358$new_n3307 $abc$30358$new_n3298 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names yv[4][20] $abc$30358$new_n3300 ph[4][17] $abc$30358$new_n3299 +110 1 +.names $abc$30358$new_n3301 ph[4][16] $abc$30358$new_n3300 +10 1 +.names $abc$30358$new_n3302 ph[4][15] $abc$30358$new_n3301 +10 1 +.names ph[4][14] ph[4][13] ph[4][12] $abc$30358$new_n3303 $abc$30358$new_n3302 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[4][11] ph[4][10] $abc$30358$new_n3304 ph[4][8] ph[4][9] $abc$30358$new_n3303 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[4][7] ph[4][6] ph[4][5] $abc$30358$new_n3305 $abc$30358$new_n3304 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[4][4] $abc$30358$new_n3306 $abc$30358$new_n3305 +11 1 +.names ph[4][3] ph[4][2] ph[4][1] $abc$30358$new_n3306 +101 1 +110 1 +111 1 +.names $abc$30358$new_n3308 ph[4][16] yv[4][20] $abc$30358$new_n3307 +110 1 +.names ph[4][15] $abc$30358$new_n3309 $abc$30358$new_n3308 +11 1 +.names ph[4][14] ph[4][13] ph[4][12] $abc$30358$new_n3310 $abc$30358$new_n3309 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[4][11] ph[4][9] ph[4][10] ph[4][8] $abc$30358$new_n3311 $abc$30358$new_n3310 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[4][7] ph[4][6] $abc$30358$new_n3312 ph[4][5] $abc$30358$new_n3311 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$30358$new_n3313 ph[4][4] $abc$30358$new_n3312 +10 1 +.names ph[4][3] ph[4][2] ph[4][1] $abc$30358$new_n3313 +000 1 +001 1 +010 1 +.names i_ce $abc$30358$new_n3315 ph[5][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26477 +001 1 +011 1 +110 1 +111 1 +.names ph[4][18] $abc$30358$new_n3299 ph[4][17] $abc$30358$new_n3307 $abc$30358$new_n3315 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$30358$new_n3317 ph[5][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26479 +001 1 +011 1 +110 1 +111 1 +.names ph[4][17] $abc$30358$new_n3307 yv[4][20] $abc$30358$new_n3300 $abc$30358$new_n3317 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$30358$new_n3319 ph[5][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26481 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[4][16] yv[4][20] $abc$30358$new_n3308 $abc$30358$new_n3301 $abc$30358$new_n3319 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3321 ph[5][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26483 +001 1 +011 1 +110 1 +111 1 +.names ph[4][15] yv[4][20] $abc$30358$new_n3309 $abc$30358$new_n3302 $abc$30358$new_n3321 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n3323 ph[4][14] ph[5][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26485 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[4][20] ph[4][13] ph[4][12] $abc$30358$new_n3303 $abc$30358$new_n3310 $abc$30358$new_n3323 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3325 ph[5][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26487 +001 1 +011 1 +110 1 +111 1 +.names ph[4][13] yv[4][20] ph[4][12] $abc$30358$new_n3310 $abc$30358$new_n3303 $abc$30358$new_n3325 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n3327 ph[5][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26489 +001 1 +011 1 +110 1 +111 1 +.names ph[4][12] yv[4][20] $abc$30358$new_n3310 $abc$30358$new_n3303 $abc$30358$new_n3327 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3329 ph[5][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26491 +001 1 +011 1 +110 1 +111 1 +.names ph[4][10] ph[4][11] $abc$30358$new_n3331 $abc$30358$new_n3330 $abc$30358$new_n3329 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[4][20] ph[4][8] ph[4][9] $abc$30358$new_n3304 $abc$30358$new_n3330 +1000 1 +.names ph[4][9] ph[4][8] yv[4][20] $abc$30358$new_n3311 $abc$30358$new_n3331 +1100 1 +.names i_ce ph[4][10] $abc$30358$new_n3331 $abc$30358$new_n3330 ph[5][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26493 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3334 ph[5][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26495 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] ph[4][9] ph[4][8] $abc$30358$new_n3311 $abc$30358$new_n3304 $abc$30358$new_n3334 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3336 ph[5][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26497 +001 1 +011 1 +100 1 +101 1 +.names ph[4][8] yv[4][20] $abc$30358$new_n3311 $abc$30358$new_n3304 $abc$30358$new_n3336 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[4][7] $abc$30358$new_n3338 ph[5][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26499 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[4][20] ph[4][5] ph[4][6] $abc$30358$new_n3305 $abc$30358$new_n3312 $abc$30358$new_n3338 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3340 ph[5][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26501 +001 1 +011 1 +110 1 +111 1 +.names ph[4][6] yv[4][20] ph[4][5] $abc$30358$new_n3312 $abc$30358$new_n3305 $abc$30358$new_n3340 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11101 1 +11111 1 +.names i_ce ph[4][5] $abc$30358$new_n3342 ph[5][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26503 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[4][20] ph[4][4] $abc$30358$new_n3306 $abc$30358$new_n3313 $abc$30358$new_n3342 +0001 1 +0011 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n3344 ph[5][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26505 +001 1 +011 1 +110 1 +111 1 +.names ph[4][4] yv[4][20] $abc$30358$new_n3313 $abc$30358$new_n3306 $abc$30358$new_n3344 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n3346 ph[5][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26507 +001 1 +011 1 +110 1 +111 1 +.names ph[4][3] yv[4][20] ph[4][1] ph[4][2] $abc$30358$new_n3346 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[4][20] ph[4][1] ph[4][2] ph[5][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26509 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[4][1] ph[5][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26511 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[4][0] ph[5][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26513 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[4][20] yv[4][19] $abc$30358$new_n3351 yv[5][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26515 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][18] xv[4][20] $abc$30358$new_n3363 $abc$30358$new_n3352 $abc$30358$new_n3351 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[4][20] $abc$30358$new_n3353 yv[4][15] yv[4][16] yv[4][17] $abc$30358$new_n3352 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[4][18] xv[4][19] yv[4][13] yv[4][14] $abc$30358$new_n3354 $abc$30358$new_n3353 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][17] yv[4][12] $abc$30358$new_n3362 $abc$30358$new_n3355 $abc$30358$new_n3361 $abc$30358$new_n3354 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][14] yv[4][9] xv[4][15] yv[4][10] $abc$30358$new_n3356 $abc$30358$new_n3355 +00000 1 +00110 1 +01000 1 +01001 1 +01110 1 +01111 1 +11000 1 +11110 1 +.names xv[4][13] yv[4][8] $abc$30358$new_n3357 $abc$30358$new_n3356 +000 1 +100 1 +101 1 +110 1 +.names yv[4][6] xv[4][11] xv[4][12] yv[4][7] $abc$30358$new_n3358 $abc$30358$new_n3357 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[4][9] xv[4][10] yv[4][4] yv[4][5] $abc$30358$new_n3359 $abc$30358$new_n3358 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][7] xv[4][8] yv[4][2] yv[4][3] $abc$30358$new_n3360 $abc$30358$new_n3359 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][5] xv[4][6] yv[4][0] yv[4][1] $abc$30358$new_n3360 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[4][16] yv[4][11] $abc$30358$new_n3361 +10 1 +.names yv[4][11] xv[4][16] yv[4][10] xv[4][15] $abc$30358$new_n3362 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[4][20] $abc$30358$new_n3364 yv[4][15] yv[4][16] yv[4][17] $abc$30358$new_n3363 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[4][19] yv[4][14] $abc$30358$new_n3365 $abc$30358$new_n3364 +000 1 +001 1 +011 1 +101 1 +.names xv[4][17] yv[4][12] xv[4][18] yv[4][13] $abc$30358$new_n3366 $abc$30358$new_n3365 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][15] yv[4][10] xv[4][16] yv[4][11] $abc$30358$new_n3367 $abc$30358$new_n3366 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][13] yv[4][8] xv[4][14] yv[4][9] $abc$30358$new_n3368 $abc$30358$new_n3367 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][11] yv[4][6] xv[4][12] yv[4][7] $abc$30358$new_n3369 $abc$30358$new_n3368 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][9] yv[4][4] xv[4][10] yv[4][5] $abc$30358$new_n3370 $abc$30358$new_n3369 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][7] yv[4][2] xv[4][8] yv[4][3] $abc$30358$new_n3371 $abc$30358$new_n3370 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][5] yv[4][0] xv[4][6] yv[4][1] $abc$30358$new_n3371 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[4][20] yv[4][18] $abc$30358$new_n3373 yv[5][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26517 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] $abc$30358$new_n3352 $abc$30358$new_n3363 $abc$30358$new_n3373 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[4][20] yv[4][17] $abc$30358$new_n3375 yv[5][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26519 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][16] yv[4][20] $abc$30358$new_n3379 xv[4][20] $abc$30358$new_n3375 +0000 1 +0001 1 +0011 1 +0101 1 +1001 1 +1100 1 +1101 1 +1111 1 +.names i_ce xv[4][20] yv[4][16] $abc$30358$new_n3379 yv[5][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26521 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][15] xv[4][20] $abc$30358$new_n3364 $abc$30358$new_n3353 $abc$30358$new_n3379 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3381 yv[5][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26523 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][20] yv[4][15] $abc$30358$new_n3364 $abc$30358$new_n3353 $abc$30358$new_n3381 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n3383 yv[5][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26525 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][19] yv[4][14] $abc$30358$new_n3365 $abc$30358$new_n3384 $abc$30358$new_n3383 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[4][18] yv[4][13] $abc$30358$new_n3354 $abc$30358$new_n3384 +001 1 +100 1 +101 1 +111 1 +.names i_ce xv[4][18] yv[4][13] $abc$30358$new_n3386 yv[5][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26527 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] xv[4][17] yv[4][12] $abc$30358$new_n3366 $abc$30358$new_n3387 $abc$30358$new_n3386 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n3361 $abc$30358$new_n3355 $abc$30358$new_n3362 $abc$30358$new_n3387 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n3389 yv[5][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26529 +001 1 +011 1 +100 1 +101 1 +.names yv[4][20] xv[4][17] yv[4][12] $abc$30358$new_n3366 $abc$30358$new_n3387 $abc$30358$new_n3389 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][16] yv[4][11] $abc$30358$new_n3391 yv[5][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26531 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][10] xv[4][15] $abc$30358$new_n3367 $abc$30358$new_n3355 $abc$30358$new_n3391 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[4][15] yv[4][10] $abc$30358$new_n3393 yv[5][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26533 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] xv[4][14] yv[4][9] $abc$30358$new_n3356 $abc$30358$new_n3367 $abc$30358$new_n3393 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[4][14] yv[4][9] $abc$30358$new_n3395 yv[5][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26535 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][8] xv[4][13] $abc$30358$new_n3368 $abc$30358$new_n3357 $abc$30358$new_n3395 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3397 yv[5][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26537 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][13] yv[4][8] $abc$30358$new_n3368 $abc$30358$new_n3357 $abc$30358$new_n3397 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][12] yv[4][7] $abc$30358$new_n3399 yv[5][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26539 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][6] xv[4][11] $abc$30358$new_n3369 $abc$30358$new_n3358 $abc$30358$new_n3399 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3401 yv[5][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26541 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][11] yv[4][6] $abc$30358$new_n3369 $abc$30358$new_n3358 $abc$30358$new_n3401 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][10] yv[4][5] $abc$30358$new_n3403 yv[5][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26543 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][4] xv[4][9] $abc$30358$new_n3370 $abc$30358$new_n3359 $abc$30358$new_n3403 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3405 yv[5][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26545 +001 1 +011 1 +100 1 +101 1 +.names yv[4][20] xv[4][9] yv[4][4] $abc$30358$new_n3370 $abc$30358$new_n3359 $abc$30358$new_n3405 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][8] yv[4][3] $abc$30358$new_n3407 yv[5][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26547 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][2] xv[4][7] $abc$30358$new_n3371 $abc$30358$new_n3360 $abc$30358$new_n3407 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[4][7] yv[4][2] $abc$30358$new_n3409 yv[5][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26549 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] $abc$30358$new_n3360 $abc$30358$new_n3371 $abc$30358$new_n3409 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3411 yv[5][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26551 +001 1 +011 1 +110 1 +111 1 +.names xv[4][6] yv[4][1] yv[4][20] yv[4][0] xv[4][5] $abc$30358$new_n3411 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[4][5] yv[4][0] yv[5][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26553 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[4][19] $abc$30358$new_n3414 xv[5][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26555 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n3415 $abc$30358$new_n3424 yv[4][20] $abc$30358$new_n3414 +000 1 +010 1 +011 1 +.names yv[4][20] xv[4][16] xv[4][17] xv[4][18] $abc$30358$new_n3416 $abc$30358$new_n3415 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names xv[4][15] xv[4][14] yv[4][19] $abc$30358$new_n3417 $abc$30358$new_n3416 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names xv[4][12] yv[4][17] xv[4][13] yv[4][18] $abc$30358$new_n3418 $abc$30358$new_n3417 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][10] yv[4][15] xv[4][11] yv[4][16] $abc$30358$new_n3419 $abc$30358$new_n3418 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][8] yv[4][13] xv[4][9] yv[4][14] $abc$30358$new_n3420 $abc$30358$new_n3419 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][6] yv[4][11] xv[4][7] yv[4][12] $abc$30358$new_n3421 $abc$30358$new_n3420 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][4] yv[4][9] xv[4][5] yv[4][10] $abc$30358$new_n3422 $abc$30358$new_n3421 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[4][2] yv[4][7] xv[4][3] yv[4][8] $abc$30358$new_n3423 $abc$30358$new_n3422 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[4][0] yv[4][5] xv[4][1] yv[4][6] $abc$30358$new_n3423 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[4][18] xv[4][16] xv[4][17] $abc$30358$new_n3425 $abc$30358$new_n3424 +1110 1 +.names xv[4][15] xv[4][14] yv[4][19] $abc$30358$new_n3426 $abc$30358$new_n3425 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +1110 1 +.names xv[4][12] xv[4][13] yv[4][17] yv[4][18] $abc$30358$new_n3427 $abc$30358$new_n3426 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][10] xv[4][11] yv[4][15] yv[4][16] $abc$30358$new_n3428 $abc$30358$new_n3427 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[4][13] xv[4][8] xv[4][9] yv[4][14] $abc$30358$new_n3429 $abc$30358$new_n3428 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][11] xv[4][6] xv[4][7] yv[4][12] $abc$30358$new_n3430 $abc$30358$new_n3429 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][9] xv[4][4] xv[4][5] yv[4][10] $abc$30358$new_n3431 $abc$30358$new_n3430 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][7] xv[4][2] xv[4][3] yv[4][8] $abc$30358$new_n3432 $abc$30358$new_n3431 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[4][5] xv[4][0] xv[4][1] yv[4][6] $abc$30358$new_n3432 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce xv[4][17] xv[4][16] $abc$30358$new_n3437 xv[5][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26559 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] $abc$30358$new_n3416 $abc$30358$new_n3425 $abc$30358$new_n3437 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[4][16] $abc$30358$new_n3437 xv[5][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26561 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[4][20] xv[4][15] $abc$30358$new_n3440 xv[5][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26563 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] yv[4][19] xv[4][14] $abc$30358$new_n3426 $abc$30358$new_n3417 $abc$30358$new_n3440 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][14] yv[4][19] $abc$30358$new_n3442 xv[5][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26565 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] $abc$30358$new_n3417 $abc$30358$new_n3426 $abc$30358$new_n3442 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[4][12] yv[4][17] $abc$30358$new_n3448 xv[5][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26569 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] $abc$30358$new_n3418 $abc$30358$new_n3427 $abc$30358$new_n3448 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3454 xv[5][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26573 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][10] yv[4][15] $abc$30358$new_n3428 $abc$30358$new_n3419 $abc$30358$new_n3454 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][9] yv[4][14] $abc$30358$new_n3456 xv[5][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26575 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] yv[4][13] xv[4][8] $abc$30358$new_n3429 $abc$30358$new_n3420 $abc$30358$new_n3456 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3458 xv[5][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26577 +001 1 +011 1 +100 1 +101 1 +.names yv[4][20] xv[4][8] yv[4][13] $abc$30358$new_n3429 $abc$30358$new_n3420 $abc$30358$new_n3458 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][7] yv[4][12] $abc$30358$new_n3460 xv[5][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26579 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] yv[4][11] xv[4][6] $abc$30358$new_n3430 $abc$30358$new_n3421 $abc$30358$new_n3460 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3462 xv[5][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26581 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][6] yv[4][11] $abc$30358$new_n3430 $abc$30358$new_n3421 $abc$30358$new_n3462 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][5] yv[4][10] $abc$30358$new_n3464 xv[5][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26583 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] yv[4][9] xv[4][4] $abc$30358$new_n3431 $abc$30358$new_n3422 $abc$30358$new_n3464 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[4][4] yv[4][9] $abc$30358$new_n3466 xv[5][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26585 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] $abc$30358$new_n3422 $abc$30358$new_n3431 $abc$30358$new_n3466 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[4][3] yv[4][8] $abc$30358$new_n3468 xv[5][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26587 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] xv[4][2] yv[4][7] $abc$30358$new_n3432 $abc$30358$new_n3423 $abc$30358$new_n3468 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[4][2] yv[4][7] $abc$30358$new_n3470 xv[5][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26589 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] $abc$30358$new_n3423 $abc$30358$new_n3432 $abc$30358$new_n3470 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3472 xv[5][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26591 +001 1 +011 1 +110 1 +111 1 +.names xv[4][1] yv[4][6] yv[4][20] xv[4][0] yv[4][5] $abc$30358$new_n3472 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[4][0] yv[4][5] xv[5][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26593 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[5][19] $abc$30358$new_n3475 ph[6][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26595 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[5][18] $abc$30358$new_n3476 $abc$30358$new_n3484 $abc$30358$new_n3475 +010 1 +011 1 +101 1 +111 1 +.names yv[5][20] $abc$30358$new_n3477 ph[5][17] $abc$30358$new_n3476 +110 1 +.names $abc$30358$new_n3478 ph[5][16] $abc$30358$new_n3477 +10 1 +.names $abc$30358$new_n3479 ph[5][15] $abc$30358$new_n3478 +10 1 +.names ph[5][13] ph[5][14] $abc$30358$new_n3480 $abc$30358$new_n3479 +000 1 +.names ph[5][12] $abc$30358$new_n3481 ph[5][11] $abc$30358$new_n3480 +101 1 +110 1 +111 1 +.names ph[5][10] $abc$30358$new_n3482 ph[5][9] $abc$30358$new_n3481 +100 1 +101 1 +111 1 +.names ph[5][8] ph[5][7] $abc$30358$new_n3483 ph[5][6] $abc$30358$new_n3482 +0000 1 +0010 1 +0011 1 +.names ph[5][5] ph[5][3] ph[5][4] ph[5][1] ph[5][2] $abc$30358$new_n3483 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names ph[5][17] $abc$30358$new_n3485 $abc$30358$new_n3484 +11 1 +.names $abc$30358$new_n3486 ph[5][16] yv[5][20] $abc$30358$new_n3485 +110 1 +.names ph[5][14] $abc$30358$new_n3487 $abc$30358$new_n3486 +11 1 +.names ph[5][13] ph[5][15] ph[5][12] ph[5][11] $abc$30358$new_n3488 $abc$30358$new_n3487 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[5][10] $abc$30358$new_n3489 ph[5][9] $abc$30358$new_n3488 +000 1 +001 1 +010 1 +.names ph[5][8] ph[5][7] $abc$30358$new_n3490 ph[5][6] $abc$30358$new_n3489 +1101 1 +1110 1 +1111 1 +.names ph[5][5] ph[5][3] ph[5][4] ph[5][1] ph[5][2] $abc$30358$new_n3490 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce ph[5][18] $abc$30358$new_n3484 $abc$30358$new_n3476 ph[6][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26597 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3493 ph[6][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26599 +001 1 +011 1 +110 1 +111 1 +.names ph[5][17] $abc$30358$new_n3485 yv[5][20] $abc$30358$new_n3477 $abc$30358$new_n3493 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$30358$new_n3495 ph[6][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26601 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[5][16] yv[5][20] $abc$30358$new_n3486 $abc$30358$new_n3478 $abc$30358$new_n3495 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3497 ph[6][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26603 +001 1 +011 1 +110 1 +111 1 +.names ph[5][14] ph[5][15] $abc$30358$new_n3500 $abc$30358$new_n3498 $abc$30358$new_n3497 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n3499 ph[5][13] $abc$30358$new_n3498 +10 1 +.names yv[5][20] $abc$30358$new_n3480 $abc$30358$new_n3499 +10 1 +.names ph[5][13] $abc$30358$new_n3501 $abc$30358$new_n3500 +11 1 +.names yv[5][20] ph[5][12] ph[5][11] $abc$30358$new_n3488 $abc$30358$new_n3501 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce ph[5][14] $abc$30358$new_n3500 $abc$30358$new_n3498 ph[6][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26605 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[5][13] $abc$30358$new_n3501 $abc$30358$new_n3499 ph[6][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26607 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3505 ph[6][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26609 +001 1 +011 1 +110 1 +111 1 +.names ph[5][12] yv[5][20] ph[5][11] $abc$30358$new_n3488 $abc$30358$new_n3481 $abc$30358$new_n3505 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n3507 ph[6][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26611 +001 1 +011 1 +110 1 +111 1 +.names ph[5][11] yv[5][20] $abc$30358$new_n3488 $abc$30358$new_n3481 $abc$30358$new_n3507 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3509 ph[6][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26613 +001 1 +011 1 +100 1 +101 1 +.names ph[5][8] ph[5][10] ph[5][9] $abc$30358$new_n3511 $abc$30358$new_n3510 $abc$30358$new_n3509 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] ph[5][7] $abc$30358$new_n3483 ph[5][6] $abc$30358$new_n3510 +1000 1 +1010 1 +1011 1 +.names ph[5][7] yv[5][20] $abc$30358$new_n3490 ph[5][6] $abc$30358$new_n3511 +1001 1 +1010 1 +1011 1 +.names i_ce $abc$30358$new_n3513 ph[6][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26615 +001 1 +011 1 +100 1 +101 1 +.names ph[5][8] ph[5][9] $abc$30358$new_n3511 $abc$30358$new_n3510 $abc$30358$new_n3513 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[5][8] $abc$30358$new_n3511 $abc$30358$new_n3510 ph[6][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26617 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3516 ph[6][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26619 +001 1 +011 1 +110 1 +111 1 +.names ph[5][7] yv[5][20] ph[5][6] $abc$30358$new_n3490 $abc$30358$new_n3483 $abc$30358$new_n3516 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3518 ph[6][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26621 +001 1 +011 1 +100 1 +101 1 +.names ph[5][6] yv[5][20] $abc$30358$new_n3490 $abc$30358$new_n3483 $abc$30358$new_n3518 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[5][5] $abc$30358$new_n3520 ph[6][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26623 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[5][20] ph[5][1] ph[5][2] ph[5][3] ph[5][4] $abc$30358$new_n3520 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n3522 ph[6][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26625 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] ph[5][4] ph[5][1] ph[5][2] ph[5][3] $abc$30358$new_n3522 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n3524 ph[6][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26627 +001 1 +011 1 +100 1 +101 1 +.names ph[5][3] yv[5][20] ph[5][1] ph[5][2] $abc$30358$new_n3524 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce yv[5][20] ph[5][1] ph[5][2] ph[6][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26629 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[5][1] ph[6][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26631 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[5][0] ph[6][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26633 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[5][20] yv[5][19] $abc$30358$new_n3529 yv[6][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26635 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][18] xv[5][20] $abc$30358$new_n3539 $abc$30358$new_n3530 $abc$30358$new_n3529 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[5][20] $abc$30358$new_n3531 yv[5][16] yv[5][17] $abc$30358$new_n3530 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[5][20] $abc$30358$new_n3532 yv[5][14] yv[5][15] $abc$30358$new_n3531 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[5][18] xv[5][19] yv[5][12] yv[5][13] $abc$30358$new_n3533 $abc$30358$new_n3532 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][16] xv[5][17] yv[5][10] yv[5][11] $abc$30358$new_n3534 $abc$30358$new_n3533 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[5][8] xv[5][14] xv[5][15] yv[5][9] $abc$30358$new_n3535 $abc$30358$new_n3534 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][6] xv[5][12] xv[5][13] yv[5][7] $abc$30358$new_n3536 $abc$30358$new_n3535 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[5][10] xv[5][11] yv[5][4] yv[5][5] $abc$30358$new_n3537 $abc$30358$new_n3536 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][8] xv[5][9] yv[5][2] yv[5][3] $abc$30358$new_n3538 $abc$30358$new_n3537 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][6] xv[5][7] yv[5][0] yv[5][1] $abc$30358$new_n3538 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[5][20] yv[5][16] yv[5][17] $abc$30358$new_n3540 $abc$30358$new_n3539 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[5][20] yv[5][14] yv[5][15] $abc$30358$new_n3541 $abc$30358$new_n3540 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[5][18] yv[5][12] xv[5][19] yv[5][13] $abc$30358$new_n3542 $abc$30358$new_n3541 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][16] yv[5][10] xv[5][17] yv[5][11] $abc$30358$new_n3543 $abc$30358$new_n3542 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][14] yv[5][8] xv[5][15] yv[5][9] $abc$30358$new_n3544 $abc$30358$new_n3543 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][12] yv[5][6] xv[5][13] yv[5][7] $abc$30358$new_n3545 $abc$30358$new_n3544 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][10] yv[5][4] xv[5][11] yv[5][5] $abc$30358$new_n3546 $abc$30358$new_n3545 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][8] yv[5][2] xv[5][9] yv[5][3] $abc$30358$new_n3547 $abc$30358$new_n3546 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][6] yv[5][0] xv[5][7] yv[5][1] $abc$30358$new_n3547 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[5][20] yv[5][18] $abc$30358$new_n3549 yv[6][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26637 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] $abc$30358$new_n3530 $abc$30358$new_n3539 $abc$30358$new_n3549 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[5][20] yv[5][17] $abc$30358$new_n3551 yv[6][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26639 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][20] yv[5][16] $abc$30358$new_n3540 $abc$30358$new_n3531 $abc$30358$new_n3551 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3553 yv[6][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26641 +001 1 +011 1 +100 1 +101 1 +.names yv[5][20] xv[5][20] yv[5][16] $abc$30358$new_n3540 $abc$30358$new_n3531 $abc$30358$new_n3553 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][20] yv[5][15] $abc$30358$new_n3555 yv[6][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26643 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][20] yv[5][14] $abc$30358$new_n3541 $abc$30358$new_n3532 $abc$30358$new_n3555 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3557 yv[6][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26645 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][20] yv[5][14] $abc$30358$new_n3541 $abc$30358$new_n3532 $abc$30358$new_n3557 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][19] yv[5][13] $abc$30358$new_n3559 yv[6][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26647 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][12] xv[5][18] $abc$30358$new_n3542 $abc$30358$new_n3533 $abc$30358$new_n3559 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[5][18] yv[5][12] $abc$30358$new_n3561 yv[6][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26649 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] $abc$30358$new_n3533 $abc$30358$new_n3542 $abc$30358$new_n3561 +010 1 +011 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n3567 yv[6][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26653 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][16] yv[5][10] $abc$30358$new_n3543 $abc$30358$new_n3534 $abc$30358$new_n3567 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][15] yv[5][9] $abc$30358$new_n3569 yv[6][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26655 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][8] xv[5][14] $abc$30358$new_n3544 $abc$30358$new_n3535 $abc$30358$new_n3569 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3571 yv[6][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26657 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][14] yv[5][8] $abc$30358$new_n3544 $abc$30358$new_n3535 $abc$30358$new_n3571 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][13] yv[5][7] $abc$30358$new_n3573 yv[6][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26659 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][6] xv[5][12] $abc$30358$new_n3545 $abc$30358$new_n3536 $abc$30358$new_n3573 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3575 yv[6][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26661 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][12] yv[5][6] $abc$30358$new_n3545 $abc$30358$new_n3536 $abc$30358$new_n3575 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][11] yv[5][5] $abc$30358$new_n3577 yv[6][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26663 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][4] xv[5][10] $abc$30358$new_n3546 $abc$30358$new_n3537 $abc$30358$new_n3577 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3579 yv[6][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26665 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][10] yv[5][4] $abc$30358$new_n3546 $abc$30358$new_n3537 $abc$30358$new_n3579 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][9] yv[5][3] $abc$30358$new_n3581 yv[6][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26667 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][2] xv[5][8] $abc$30358$new_n3547 $abc$30358$new_n3538 $abc$30358$new_n3581 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[5][8] yv[5][2] $abc$30358$new_n3583 yv[6][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26669 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] $abc$30358$new_n3538 $abc$30358$new_n3547 $abc$30358$new_n3583 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3585 yv[6][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26671 +001 1 +011 1 +110 1 +111 1 +.names xv[5][7] yv[5][1] yv[5][20] yv[5][0] xv[5][6] $abc$30358$new_n3585 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[5][6] yv[5][0] yv[6][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26673 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[5][14] xv[5][15] $abc$30358$new_n3590 $abc$30358$new_n3589 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[5][12] yv[5][18] xv[5][13] yv[5][19] $abc$30358$new_n3591 $abc$30358$new_n3590 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][10] yv[5][16] xv[5][11] yv[5][17] $abc$30358$new_n3592 $abc$30358$new_n3591 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][9] yv[5][15] $abc$30358$new_n3593 $abc$30358$new_n3592 +000 1 +001 1 +011 1 +101 1 +.names xv[5][7] yv[5][13] xv[5][8] yv[5][14] $abc$30358$new_n3594 $abc$30358$new_n3593 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][5] yv[5][11] xv[5][6] yv[5][12] $abc$30358$new_n3595 $abc$30358$new_n3594 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][3] yv[5][9] xv[5][4] yv[5][10] $abc$30358$new_n3596 $abc$30358$new_n3595 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][2] yv[5][8] $abc$30358$new_n3597 $abc$30358$new_n3596 +000 1 +001 1 +011 1 +101 1 +.names xv[5][0] yv[5][6] xv[5][1] yv[5][7] $abc$30358$new_n3597 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$30358$new_n3611 xv[5][14] xv[5][15] $abc$30358$new_n3600 $abc$30358$new_n3599 +1110 1 +.names $abc$30358$new_n3608 $abc$30358$new_n3601 $abc$30358$new_n3600 +10 1 +.names $abc$30358$new_n3602 xv[5][12] yv[5][18] xv[5][13] yv[5][19] $abc$30358$new_n3601 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$30358$new_n3603 xv[5][10] yv[5][16] xv[5][11] yv[5][17] $abc$30358$new_n3602 +10000 1 +10011 1 +11100 1 +11111 1 +.names xv[5][8] yv[5][14] xv[5][9] yv[5][15] $abc$30358$new_n3604 $abc$30358$new_n3603 +00000 1 +00110 1 +11000 1 +11110 1 +.names yv[5][12] xv[5][6] xv[5][7] yv[5][13] $abc$30358$new_n3605 $abc$30358$new_n3604 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][10] xv[5][4] xv[5][5] yv[5][11] $abc$30358$new_n3606 $abc$30358$new_n3605 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][8] xv[5][2] xv[5][3] yv[5][9] $abc$30358$new_n3607 $abc$30358$new_n3606 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[5][6] xv[5][0] xv[5][1] yv[5][7] $abc$30358$new_n3607 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[5][18] xv[5][12] xv[5][13] yv[5][19] $abc$30358$new_n3609 $abc$30358$new_n3608 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][16] xv[5][10] xv[5][11] yv[5][17] $abc$30358$new_n3610 $abc$30358$new_n3609 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names xv[5][8] xv[5][9] yv[5][14] yv[5][15] $abc$30358$new_n3610 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[5][20] xv[5][16] xv[5][17] $abc$30358$new_n3611 +000 1 +111 1 +.names i_ce $abc$30358$new_n3616 xv[6][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26679 +001 1 +011 1 +110 1 +111 1 +.names xv[5][17] yv[5][20] xv[5][16] $abc$30358$new_n3617 $abc$30358$new_n3589 $abc$30358$new_n3616 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[5][14] xv[5][15] $abc$30358$new_n3600 $abc$30358$new_n3617 +110 1 +.names $abc$30358$new_n3619 i_ce xv[6][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26681 +001 1 +010 1 +011 1 +.names i_ce yv[5][20] xv[5][16] $abc$30358$new_n3617 $abc$30358$new_n3589 $abc$30358$new_n3619 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3621 xv[6][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26683 +001 1 +011 1 +110 1 +111 1 +.names xv[5][15] yv[5][20] xv[5][14] $abc$30358$new_n3600 $abc$30358$new_n3590 $abc$30358$new_n3621 +00101 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n3623 i_ce xv[6][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26685 +001 1 +010 1 +011 1 +.names i_ce yv[5][20] xv[5][14] $abc$30358$new_n3600 $abc$30358$new_n3590 $abc$30358$new_n3623 +10000 1 +10010 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][13] yv[5][19] $abc$30358$new_n3625 xv[6][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26687 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] yv[5][18] xv[5][12] $abc$30358$new_n3626 $abc$30358$new_n3591 $abc$30358$new_n3625 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n3609 $abc$30358$new_n3602 $abc$30358$new_n3626 +10 1 +.names i_ce $abc$30358$new_n3628 xv[6][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26689 +001 1 +011 1 +100 1 +101 1 +.names yv[5][20] xv[5][12] yv[5][18] $abc$30358$new_n3626 $abc$30358$new_n3591 $abc$30358$new_n3628 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][11] yv[5][17] $abc$30358$new_n3630 xv[6][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26691 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[5][10] yv[5][20] $abc$30358$new_n3631 yv[5][16] $abc$30358$new_n3592 $abc$30358$new_n3630 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names yv[5][20] $abc$30358$new_n3603 $abc$30358$new_n3610 $abc$30358$new_n3631 +100 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n3633 xv[6][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26693 +001 1 +011 1 +110 1 +111 1 +.names xv[5][10] yv[5][16] $abc$30358$new_n3631 yv[5][20] $abc$30358$new_n3592 $abc$30358$new_n3633 +00000 1 +00010 1 +00011 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +.names i_ce xv[5][9] yv[5][15] $abc$30358$new_n3635 xv[6][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26695 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] xv[5][8] yv[5][14] $abc$30358$new_n3604 $abc$30358$new_n3593 $abc$30358$new_n3635 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][8] yv[5][14] $abc$30358$new_n3637 xv[6][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26697 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][7] yv[5][13] $abc$30358$new_n3594 $abc$30358$new_n3604 $abc$30358$new_n3637 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][7] yv[5][13] $abc$30358$new_n3639 xv[6][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26699 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] yv[5][12] xv[5][6] $abc$30358$new_n3605 $abc$30358$new_n3594 $abc$30358$new_n3639 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][6] yv[5][12] $abc$30358$new_n3641 xv[6][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26701 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][5] yv[5][11] $abc$30358$new_n3595 $abc$30358$new_n3605 $abc$30358$new_n3641 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][5] yv[5][11] $abc$30358$new_n3643 xv[6][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26703 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] yv[5][10] xv[5][4] $abc$30358$new_n3606 $abc$30358$new_n3595 $abc$30358$new_n3643 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][4] yv[5][10] $abc$30358$new_n3645 xv[6][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26705 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][3] yv[5][9] $abc$30358$new_n3596 $abc$30358$new_n3606 $abc$30358$new_n3645 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][3] yv[5][9] $abc$30358$new_n3647 xv[6][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26707 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] xv[5][2] yv[5][8] $abc$30358$new_n3607 $abc$30358$new_n3597 $abc$30358$new_n3647 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][2] yv[5][8] $abc$30358$new_n3649 xv[6][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26709 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] $abc$30358$new_n3597 $abc$30358$new_n3607 $abc$30358$new_n3649 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3651 xv[6][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26711 +001 1 +011 1 +110 1 +111 1 +.names xv[5][1] yv[5][7] yv[5][20] xv[5][0] yv[5][6] $abc$30358$new_n3651 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[5][0] yv[5][6] xv[6][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26713 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3654 ph[6][19] ph[7][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26715 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[6][17] ph[6][18] $abc$30358$new_n3655 $abc$30358$new_n3663 $abc$30358$new_n3654 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names yv[6][20] $abc$30358$new_n3656 ph[6][16] $abc$30358$new_n3655 +110 1 +.names $abc$30358$new_n3657 ph[6][15] $abc$30358$new_n3656 +10 1 +.names $abc$30358$new_n3658 ph[6][14] $abc$30358$new_n3657 +10 1 +.names ph[6][12] ph[6][13] $abc$30358$new_n3659 $abc$30358$new_n3658 +000 1 +.names ph[6][11] $abc$30358$new_n3660 ph[6][10] $abc$30358$new_n3659 +101 1 +110 1 +111 1 +.names ph[6][9] $abc$30358$new_n3661 ph[6][8] $abc$30358$new_n3660 +100 1 +101 1 +111 1 +.names ph[6][7] ph[6][6] $abc$30358$new_n3662 ph[6][5] $abc$30358$new_n3661 +0000 1 +0010 1 +0011 1 +.names ph[6][4] ph[6][2] ph[6][3] ph[6][0] ph[6][1] $abc$30358$new_n3662 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names ph[6][16] $abc$30358$new_n3664 $abc$30358$new_n3663 +11 1 +.names $abc$30358$new_n3665 ph[6][15] yv[6][20] $abc$30358$new_n3664 +110 1 +.names ph[6][13] $abc$30358$new_n3666 $abc$30358$new_n3665 +11 1 +.names ph[6][12] ph[6][14] ph[6][11] ph[6][10] $abc$30358$new_n3667 $abc$30358$new_n3666 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[6][9] $abc$30358$new_n3668 ph[6][8] $abc$30358$new_n3667 +000 1 +001 1 +010 1 +.names ph[6][7] ph[6][6] $abc$30358$new_n3669 ph[6][5] $abc$30358$new_n3668 +1101 1 +1110 1 +1111 1 +.names ph[6][4] ph[6][2] ph[6][3] ph[6][0] ph[6][1] $abc$30358$new_n3669 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3671 ph[7][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26717 +001 1 +011 1 +110 1 +111 1 +.names ph[6][17] ph[6][18] $abc$30358$new_n3663 $abc$30358$new_n3655 $abc$30358$new_n3671 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][17] $abc$30358$new_n3663 $abc$30358$new_n3655 ph[7][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26719 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3674 ph[7][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26721 +001 1 +011 1 +100 1 +101 1 +.names ph[6][16] $abc$30358$new_n3664 yv[6][20] $abc$30358$new_n3656 $abc$30358$new_n3674 +0000 1 +0001 1 +0010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n3676 ph[7][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26723 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[6][15] yv[6][20] $abc$30358$new_n3665 $abc$30358$new_n3657 $abc$30358$new_n3676 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3678 ph[7][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26725 +001 1 +011 1 +110 1 +111 1 +.names ph[6][13] ph[6][14] $abc$30358$new_n3681 $abc$30358$new_n3679 $abc$30358$new_n3678 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n3680 ph[6][12] $abc$30358$new_n3679 +10 1 +.names yv[6][20] $abc$30358$new_n3659 $abc$30358$new_n3680 +10 1 +.names ph[6][12] $abc$30358$new_n3682 $abc$30358$new_n3681 +11 1 +.names yv[6][20] ph[6][11] ph[6][10] $abc$30358$new_n3667 $abc$30358$new_n3682 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce ph[6][13] $abc$30358$new_n3681 $abc$30358$new_n3679 ph[7][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26727 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[6][12] $abc$30358$new_n3682 $abc$30358$new_n3680 ph[7][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26729 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3686 ph[7][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26731 +001 1 +011 1 +110 1 +111 1 +.names ph[6][11] yv[6][20] ph[6][10] $abc$30358$new_n3667 $abc$30358$new_n3660 $abc$30358$new_n3686 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n3688 ph[7][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26733 +001 1 +011 1 +110 1 +111 1 +.names ph[6][10] yv[6][20] $abc$30358$new_n3667 $abc$30358$new_n3660 $abc$30358$new_n3688 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3690 ph[7][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26735 +001 1 +011 1 +100 1 +101 1 +.names ph[6][7] ph[6][9] ph[6][8] $abc$30358$new_n3692 $abc$30358$new_n3691 $abc$30358$new_n3690 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] ph[6][6] $abc$30358$new_n3662 ph[6][5] $abc$30358$new_n3691 +1000 1 +1010 1 +1011 1 +.names ph[6][6] yv[6][20] $abc$30358$new_n3669 ph[6][5] $abc$30358$new_n3692 +1001 1 +1010 1 +1011 1 +.names i_ce $abc$30358$new_n3694 ph[7][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26737 +001 1 +011 1 +110 1 +111 1 +.names ph[6][7] ph[6][8] $abc$30358$new_n3692 $abc$30358$new_n3691 $abc$30358$new_n3694 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][7] $abc$30358$new_n3692 $abc$30358$new_n3691 ph[7][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26739 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3697 ph[7][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26741 +001 1 +011 1 +110 1 +111 1 +.names ph[6][6] yv[6][20] ph[6][5] $abc$30358$new_n3669 $abc$30358$new_n3662 $abc$30358$new_n3697 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3699 ph[7][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26743 +001 1 +011 1 +110 1 +111 1 +.names ph[6][5] yv[6][20] $abc$30358$new_n3669 $abc$30358$new_n3662 $abc$30358$new_n3699 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[6][4] $abc$30358$new_n3701 ph[7][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26745 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[6][20] ph[6][0] ph[6][1] ph[6][2] ph[6][3] $abc$30358$new_n3701 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n3703 ph[7][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26747 +001 1 +011 1 +110 1 +111 1 +.names yv[6][20] ph[6][3] ph[6][0] ph[6][1] ph[6][2] $abc$30358$new_n3703 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n3705 ph[7][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26749 +001 1 +011 1 +100 1 +101 1 +.names ph[6][2] yv[6][20] ph[6][0] ph[6][1] $abc$30358$new_n3705 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce yv[6][20] ph[6][0] ph[6][1] ph[7][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26751 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[6][0] ph[7][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26753 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[6][20] yv[6][19] $abc$30358$new_n3709 yv[7][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26755 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][18] yv[6][20] $abc$30358$new_n3710 xv[6][20] $abc$30358$new_n3719 $abc$30358$new_n3709 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[6][20] xv[6][20] yv[6][16] yv[6][17] $abc$30358$new_n3711 $abc$30358$new_n3710 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][20] yv[6][14] yv[6][15] $abc$30358$new_n3712 $abc$30358$new_n3711 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][19] yv[6][12] xv[6][20] yv[6][13] $abc$30358$new_n3713 $abc$30358$new_n3712 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][17] yv[6][10] xv[6][18] yv[6][11] $abc$30358$new_n3714 $abc$30358$new_n3713 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][15] yv[6][8] xv[6][16] yv[6][9] $abc$30358$new_n3715 $abc$30358$new_n3714 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][13] yv[6][6] xv[6][14] yv[6][7] $abc$30358$new_n3716 $abc$30358$new_n3715 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][11] yv[6][4] xv[6][12] yv[6][5] $abc$30358$new_n3717 $abc$30358$new_n3716 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][9] yv[6][2] xv[6][10] yv[6][3] $abc$30358$new_n3718 $abc$30358$new_n3717 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][7] yv[6][0] xv[6][8] yv[6][1] $abc$30358$new_n3718 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[6][20] $abc$30358$new_n3720 yv[6][16] yv[6][17] $abc$30358$new_n3719 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][20] $abc$30358$new_n3721 yv[6][13] yv[6][14] yv[6][15] $abc$30358$new_n3720 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][18] xv[6][19] yv[6][11] yv[6][12] $abc$30358$new_n3722 $abc$30358$new_n3721 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][17] yv[6][10] $abc$30358$new_n3723 $abc$30358$new_n3722 +000 1 +100 1 +101 1 +110 1 +.names yv[6][8] xv[6][15] xv[6][16] yv[6][9] $abc$30358$new_n3724 $abc$30358$new_n3723 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[6][6] xv[6][13] xv[6][14] yv[6][7] $abc$30358$new_n3725 $abc$30358$new_n3724 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[6][11] xv[6][12] yv[6][4] yv[6][5] $abc$30358$new_n3726 $abc$30358$new_n3725 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][9] xv[6][10] yv[6][2] yv[6][3] $abc$30358$new_n3727 $abc$30358$new_n3726 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][7] xv[6][8] yv[6][0] yv[6][1] $abc$30358$new_n3727 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$30358$new_n3729 yv[7][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26757 +001 1 +011 1 +110 1 +111 1 +.names xv[6][20] yv[6][18] $abc$30358$new_n3710 $abc$30358$new_n3719 yv[6][20] $abc$30358$new_n3729 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10011 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[6][20] yv[6][17] $abc$30358$new_n3731 yv[7][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26759 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][20] yv[6][16] $abc$30358$new_n3720 $abc$30358$new_n3711 $abc$30358$new_n3731 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3733 yv[7][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26761 +001 1 +011 1 +110 1 +111 1 +.names xv[6][20] yv[6][16] yv[6][20] $abc$30358$new_n3720 $abc$30358$new_n3711 $abc$30358$new_n3733 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[6][20] $abc$30358$new_n3721 yv[6][13] yv[6][14] $abc$30358$new_n3737 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[6][20] yv[6][14] $abc$30358$new_n3739 yv[7][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26765 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][20] yv[6][13] $abc$30358$new_n3721 $abc$30358$new_n3740 $abc$30358$new_n3739 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][19] yv[6][12] $abc$30358$new_n3713 $abc$30358$new_n3740 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n3742 yv[7][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26767 +001 1 +011 1 +100 1 +101 1 +.names xv[6][20] yv[6][13] yv[6][20] $abc$30358$new_n3721 $abc$30358$new_n3740 $abc$30358$new_n3742 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[6][19] yv[6][12] $abc$30358$new_n3744 yv[7][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26769 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][11] xv[6][18] $abc$30358$new_n3722 $abc$30358$new_n3713 $abc$30358$new_n3744 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][18] yv[6][11] $abc$30358$new_n3746 yv[7][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26771 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][17] yv[6][10] $abc$30358$new_n3723 $abc$30358$new_n3714 $abc$30358$new_n3746 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3748 yv[7][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26773 +001 1 +011 1 +110 1 +111 1 +.names xv[6][17] yv[6][10] yv[6][20] $abc$30358$new_n3723 $abc$30358$new_n3714 $abc$30358$new_n3748 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[6][16] yv[6][9] $abc$30358$new_n3750 yv[7][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26775 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][8] xv[6][15] $abc$30358$new_n3724 $abc$30358$new_n3715 $abc$30358$new_n3750 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3752 yv[7][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26777 +001 1 +011 1 +110 1 +111 1 +.names xv[6][15] yv[6][8] yv[6][20] $abc$30358$new_n3724 $abc$30358$new_n3715 $abc$30358$new_n3752 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[6][14] yv[6][7] $abc$30358$new_n3754 yv[7][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26779 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][6] xv[6][13] $abc$30358$new_n3725 $abc$30358$new_n3716 $abc$30358$new_n3754 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[6][13] yv[6][6] $abc$30358$new_n3756 yv[7][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26781 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] $abc$30358$new_n3716 $abc$30358$new_n3725 $abc$30358$new_n3756 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[6][12] yv[6][5] $abc$30358$new_n3758 yv[7][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26783 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][4] xv[6][11] $abc$30358$new_n3726 $abc$30358$new_n3717 $abc$30358$new_n3758 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3760 yv[7][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26785 +001 1 +011 1 +110 1 +111 1 +.names xv[6][11] yv[6][4] yv[6][20] $abc$30358$new_n3726 $abc$30358$new_n3717 $abc$30358$new_n3760 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[6][10] yv[6][3] $abc$30358$new_n3762 yv[7][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26787 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][2] xv[6][9] $abc$30358$new_n3727 $abc$30358$new_n3718 $abc$30358$new_n3762 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[6][9] yv[6][2] $abc$30358$new_n3764 yv[7][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26789 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] $abc$30358$new_n3718 $abc$30358$new_n3727 $abc$30358$new_n3764 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n3766 yv[7][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26791 +001 1 +011 1 +110 1 +111 1 +.names xv[6][8] yv[6][1] yv[6][20] yv[6][0] xv[6][7] $abc$30358$new_n3766 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[6][7] yv[6][0] yv[7][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26793 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[6][15] xv[6][13] xv[6][14] $abc$30358$new_n3771 $abc$30358$new_n3770 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names xv[6][12] yv[6][19] $abc$30358$new_n3772 $abc$30358$new_n3771 +000 1 +001 1 +010 1 +100 1 +.names xv[6][10] yv[6][17] xv[6][11] yv[6][18] $abc$30358$new_n3773 $abc$30358$new_n3772 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][9] yv[6][16] $abc$30358$new_n3774 $abc$30358$new_n3773 +000 1 +001 1 +011 1 +101 1 +.names xv[6][7] yv[6][14] xv[6][8] yv[6][15] $abc$30358$new_n3775 $abc$30358$new_n3774 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][5] yv[6][12] xv[6][6] yv[6][13] $abc$30358$new_n3776 $abc$30358$new_n3775 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][3] yv[6][10] xv[6][4] yv[6][11] $abc$30358$new_n3777 $abc$30358$new_n3776 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][2] yv[6][9] $abc$30358$new_n3778 $abc$30358$new_n3777 +000 1 +001 1 +011 1 +101 1 +.names xv[6][0] yv[6][7] xv[6][1] yv[6][8] $abc$30358$new_n3778 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[6][16] xv[6][17] $abc$30358$new_n3781 $abc$30358$new_n3780 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n3792 $abc$30358$new_n3790 $abc$30358$new_n3791 $abc$30358$new_n3782 $abc$30358$new_n3788 $abc$30358$new_n3781 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$30358$new_n3783 xv[6][10] yv[6][17] xv[6][11] yv[6][18] $abc$30358$new_n3782 +10000 1 +10011 1 +11100 1 +11111 1 +.names xv[6][8] yv[6][15] xv[6][9] yv[6][16] $abc$30358$new_n3784 $abc$30358$new_n3783 +00000 1 +00110 1 +11000 1 +11110 1 +.names yv[6][13] xv[6][6] xv[6][7] yv[6][14] $abc$30358$new_n3785 $abc$30358$new_n3784 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[6][11] xv[6][4] xv[6][5] yv[6][12] $abc$30358$new_n3786 $abc$30358$new_n3785 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[6][9] xv[6][2] xv[6][3] yv[6][10] $abc$30358$new_n3787 $abc$30358$new_n3786 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[6][7] xv[6][0] xv[6][1] yv[6][8] $abc$30358$new_n3787 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[6][17] xv[6][10] xv[6][11] yv[6][18] $abc$30358$new_n3789 $abc$30358$new_n3788 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names xv[6][8] xv[6][9] yv[6][15] yv[6][16] $abc$30358$new_n3789 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[6][20] xv[6][13] xv[6][12] yv[6][19] $abc$30358$new_n3790 +0000 1 +0011 1 +1100 1 +1111 1 +.names xv[6][12] yv[6][19] yv[6][20] xv[6][13] $abc$30358$new_n3791 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[6][20] xv[6][14] xv[6][15] $abc$30358$new_n3792 +000 1 +111 1 +.names i_ce xv[6][17] $abc$30358$new_n3798 xv[7][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26799 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[6][16] yv[6][20] $abc$30358$new_n3770 $abc$30358$new_n3781 $abc$30358$new_n3798 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$30358$new_n3800 i_ce xv[7][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26801 +001 1 +010 1 +011 1 +.names i_ce yv[6][20] xv[6][16] $abc$30358$new_n3781 $abc$30358$new_n3770 $abc$30358$new_n3800 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[6][15] $abc$30358$new_n3802 xv[7][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26803 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[6][14] yv[6][20] $abc$30358$new_n3803 $abc$30358$new_n3804 $abc$30358$new_n3802 +1000 1 +1001 1 +1100 1 +1110 1 +.names xv[6][13] $abc$30358$new_n3771 $abc$30358$new_n3803 +00 1 +01 1 +11 1 +.names $abc$30358$new_n3791 $abc$30358$new_n3790 $abc$30358$new_n3788 $abc$30358$new_n3782 $abc$30358$new_n3804 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$30358$new_n3806 i_ce xv[7][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26805 +001 1 +010 1 +011 1 +.names i_ce yv[6][20] xv[6][14] $abc$30358$new_n3804 $abc$30358$new_n3803 $abc$30358$new_n3806 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[6][13] $abc$30358$new_n3808 xv[7][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26807 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[6][20] xv[6][12] yv[6][19] $abc$30358$new_n3809 $abc$30358$new_n3772 $abc$30358$new_n3808 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n3788 $abc$30358$new_n3782 $abc$30358$new_n3809 +10 1 +.names i_ce $abc$30358$new_n3811 xv[7][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26809 +001 1 +011 1 +110 1 +111 1 +.names yv[6][20] xv[6][12] yv[6][19] $abc$30358$new_n3809 $abc$30358$new_n3772 $abc$30358$new_n3811 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[6][11] yv[6][18] $abc$30358$new_n3813 xv[7][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26811 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[6][10] yv[6][20] $abc$30358$new_n3814 yv[6][17] $abc$30358$new_n3773 $abc$30358$new_n3813 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names yv[6][20] $abc$30358$new_n3783 $abc$30358$new_n3789 $abc$30358$new_n3814 +100 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n3816 xv[7][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26813 +001 1 +011 1 +110 1 +111 1 +.names xv[6][10] yv[6][17] $abc$30358$new_n3814 yv[6][20] $abc$30358$new_n3773 $abc$30358$new_n3816 +00000 1 +00010 1 +00011 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +.names i_ce xv[6][9] yv[6][16] $abc$30358$new_n3818 xv[7][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26815 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] xv[6][8] yv[6][15] $abc$30358$new_n3784 $abc$30358$new_n3774 $abc$30358$new_n3818 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[6][8] yv[6][15] $abc$30358$new_n3820 xv[7][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26817 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][7] yv[6][14] $abc$30358$new_n3775 $abc$30358$new_n3784 $abc$30358$new_n3820 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][7] yv[6][14] $abc$30358$new_n3822 xv[7][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26819 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] yv[6][13] xv[6][6] $abc$30358$new_n3785 $abc$30358$new_n3775 $abc$30358$new_n3822 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][6] yv[6][13] $abc$30358$new_n3824 xv[7][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26821 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][5] yv[6][12] $abc$30358$new_n3776 $abc$30358$new_n3785 $abc$30358$new_n3824 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][5] yv[6][12] $abc$30358$new_n3826 xv[7][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26823 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] yv[6][11] xv[6][4] $abc$30358$new_n3786 $abc$30358$new_n3776 $abc$30358$new_n3826 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][4] yv[6][11] $abc$30358$new_n3828 xv[7][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26825 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][3] yv[6][10] $abc$30358$new_n3777 $abc$30358$new_n3786 $abc$30358$new_n3828 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][3] yv[6][10] $abc$30358$new_n3830 xv[7][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26827 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] xv[6][2] yv[6][9] $abc$30358$new_n3787 $abc$30358$new_n3778 $abc$30358$new_n3830 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][2] yv[6][9] $abc$30358$new_n3832 xv[7][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26829 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] $abc$30358$new_n3778 $abc$30358$new_n3787 $abc$30358$new_n3832 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3834 xv[7][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26831 +001 1 +011 1 +110 1 +111 1 +.names xv[6][1] yv[6][8] yv[6][20] xv[6][0] yv[6][7] $abc$30358$new_n3834 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[6][0] yv[6][7] xv[7][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26833 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3837 ph[7][19] ph[8][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26835 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[7][18] $abc$30358$new_n3838 ph[7][17] $abc$30358$new_n3844 ph[7][16] $abc$30358$new_n3837 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[7][20] $abc$30358$new_n3839 ph[7][16] ph[7][17] $abc$30358$new_n3838 +1100 1 +.names $abc$30358$new_n3840 ph[7][15] $abc$30358$new_n3839 +10 1 +.names $abc$30358$new_n3841 ph[7][12] ph[7][13] ph[7][14] $abc$30358$new_n3840 +1000 1 +.names ph[7][11] ph[7][10] ph[7][9] $abc$30358$new_n3842 $abc$30358$new_n3841 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[7][8] ph[7][7] $abc$30358$new_n3843 ph[7][5] ph[7][6] $abc$30358$new_n3842 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[7][4] ph[7][3] ph[7][1] ph[7][2] ph[7][0] $abc$30358$new_n3843 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n3845 yv[7][20] $abc$30358$new_n3844 +10 1 +.names ph[7][15] $abc$30358$new_n3846 $abc$30358$new_n3845 +11 1 +.names ph[7][12] ph[7][13] ph[7][14] $abc$30358$new_n3847 $abc$30358$new_n3846 +1111 1 +.names ph[7][11] ph[7][10] ph[7][9] $abc$30358$new_n3848 $abc$30358$new_n3847 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[7][8] ph[7][6] ph[7][7] ph[7][5] $abc$30358$new_n3849 $abc$30358$new_n3848 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[7][4] ph[7][3] ph[7][1] ph[7][2] ph[7][0] $abc$30358$new_n3849 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names i_ce $abc$30358$new_n3851 ph[7][18] ph[8][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26837 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$30358$new_n3838 ph[7][17] $abc$30358$new_n3844 ph[7][16] $abc$30358$new_n3851 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names i_ce $abc$30358$new_n3853 ph[8][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26839 +001 1 +011 1 +110 1 +111 1 +.names yv[7][20] ph[7][17] ph[7][16] $abc$30358$new_n3845 $abc$30358$new_n3839 $abc$30358$new_n3853 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3855 ph[8][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26841 +001 1 +011 1 +100 1 +101 1 +.names ph[7][16] yv[7][20] $abc$30358$new_n3845 $abc$30358$new_n3839 $abc$30358$new_n3855 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$30358$new_n3857 ph[8][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26843 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[7][15] yv[7][20] $abc$30358$new_n3846 $abc$30358$new_n3840 $abc$30358$new_n3857 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce ph[7][14] $abc$30358$new_n3859 ph[8][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26845 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[7][12] ph[7][13] yv[7][20] $abc$30358$new_n3841 $abc$30358$new_n3847 $abc$30358$new_n3859 +00110 1 +00111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3864 ph[8][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26849 +001 1 +011 1 +110 1 +111 1 +.names ph[7][12] yv[7][20] $abc$30358$new_n3847 $abc$30358$new_n3841 $abc$30358$new_n3864 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[7][11] $abc$30358$new_n3866 ph[8][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26851 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[7][20] ph[7][9] ph[7][10] $abc$30358$new_n3842 $abc$30358$new_n3848 $abc$30358$new_n3866 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3868 ph[8][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26853 +001 1 +011 1 +110 1 +111 1 +.names ph[7][10] yv[7][20] ph[7][9] $abc$30358$new_n3848 $abc$30358$new_n3842 $abc$30358$new_n3868 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n3870 ph[8][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26855 +001 1 +011 1 +110 1 +111 1 +.names ph[7][9] yv[7][20] $abc$30358$new_n3848 $abc$30358$new_n3842 $abc$30358$new_n3870 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3872 ph[8][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26857 +001 1 +011 1 +100 1 +101 1 +.names ph[7][6] ph[7][8] ph[7][7] $abc$30358$new_n3874 $abc$30358$new_n3873 $abc$30358$new_n3872 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] ph[7][5] $abc$30358$new_n3843 $abc$30358$new_n3873 +100 1 +.names ph[7][5] yv[7][20] $abc$30358$new_n3849 $abc$30358$new_n3874 +100 1 +.names i_ce $abc$30358$new_n3876 ph[8][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26859 +001 1 +011 1 +110 1 +111 1 +.names ph[7][6] ph[7][7] $abc$30358$new_n3874 $abc$30358$new_n3873 $abc$30358$new_n3876 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[7][6] $abc$30358$new_n3874 $abc$30358$new_n3873 ph[8][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26861 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3879 ph[8][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26863 +001 1 +011 1 +110 1 +111 1 +.names ph[7][5] yv[7][20] $abc$30358$new_n3849 $abc$30358$new_n3843 $abc$30358$new_n3879 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[7][4] $abc$30358$new_n3881 ph[8][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26865 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[7][20] ph[7][0] ph[7][1] ph[7][2] ph[7][3] $abc$30358$new_n3881 +00000 1 +00001 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3883 ph[8][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26867 +001 1 +011 1 +110 1 +111 1 +.names ph[7][3] yv[7][20] ph[7][0] ph[7][1] ph[7][2] $abc$30358$new_n3883 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11111 1 +.names i_ce $abc$30358$new_n3885 ph[8][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26869 +001 1 +011 1 +100 1 +101 1 +.names ph[7][2] yv[7][20] ph[7][0] ph[7][1] $abc$30358$new_n3885 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce yv[7][20] ph[7][0] ph[7][1] ph[8][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26871 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[7][0] ph[8][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26873 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[7][20] yv[7][19] $abc$30358$new_n3889 yv[8][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26875 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][18] yv[7][20] $abc$30358$new_n3890 xv[7][20] $abc$30358$new_n3903 $abc$30358$new_n3889 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[7][20] xv[7][20] yv[7][16] yv[7][17] $abc$30358$new_n3891 $abc$30358$new_n3890 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[7][13] $abc$30358$new_n3900 $abc$30358$new_n3902 $abc$30358$new_n3901 $abc$30358$new_n3892 $abc$30358$new_n3891 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][19] yv[7][11] $abc$30358$new_n3893 $abc$30358$new_n3892 +000 1 +001 1 +011 1 +101 1 +.names xv[7][17] yv[7][9] xv[7][18] yv[7][10] $abc$30358$new_n3894 $abc$30358$new_n3893 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][16] yv[7][8] $abc$30358$new_n3895 $abc$30358$new_n3894 +000 1 +001 1 +011 1 +101 1 +.names xv[7][14] yv[7][6] xv[7][15] yv[7][7] $abc$30358$new_n3896 $abc$30358$new_n3895 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][12] yv[7][4] xv[7][13] yv[7][5] $abc$30358$new_n3897 $abc$30358$new_n3896 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][10] yv[7][2] xv[7][11] yv[7][3] $abc$30358$new_n3898 $abc$30358$new_n3897 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][8] yv[7][0] xv[7][9] yv[7][1] $abc$30358$new_n3898 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[7][20] yv[7][13] $abc$30358$new_n3900 +01 1 +10 1 +.names xv[7][20] yv[7][12] $abc$30358$new_n3901 +01 1 +10 1 +.names xv[7][20] yv[7][14] yv[7][15] $abc$30358$new_n3902 +011 1 +100 1 +.names xv[7][20] $abc$30358$new_n3904 yv[7][16] yv[7][17] $abc$30358$new_n3903 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[7][13] $abc$30358$new_n3900 $abc$30358$new_n3913 $abc$30358$new_n3905 $abc$30358$new_n3901 $abc$30358$new_n3904 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names xv[7][19] yv[7][11] yv[7][10] xv[7][18] $abc$30358$new_n3906 $abc$30358$new_n3905 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][17] yv[7][9] xv[7][18] yv[7][10] $abc$30358$new_n3907 $abc$30358$new_n3906 +00000 1 +00110 1 +01000 1 +01001 1 +01110 1 +01111 1 +11000 1 +11110 1 +.names xv[7][16] yv[7][8] $abc$30358$new_n3908 $abc$30358$new_n3907 +000 1 +100 1 +101 1 +110 1 +.names yv[7][6] xv[7][14] xv[7][15] yv[7][7] $abc$30358$new_n3909 $abc$30358$new_n3908 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[7][12] xv[7][13] yv[7][4] yv[7][5] $abc$30358$new_n3910 $abc$30358$new_n3909 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][10] xv[7][11] yv[7][2] yv[7][3] $abc$30358$new_n3911 $abc$30358$new_n3910 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][8] xv[7][9] yv[7][0] yv[7][1] $abc$30358$new_n3911 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[7][20] yv[7][14] yv[7][15] $abc$30358$new_n3913 +000 1 +111 1 +.names i_ce xv[7][20] yv[7][18] $abc$30358$new_n3915 yv[8][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26877 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n3890 $abc$30358$new_n3903 yv[7][20] $abc$30358$new_n3915 +000 1 +001 1 +011 1 +.names i_ce xv[7][20] yv[7][17] $abc$30358$new_n3917 yv[8][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26879 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][20] yv[7][16] $abc$30358$new_n3904 $abc$30358$new_n3891 $abc$30358$new_n3917 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3919 yv[8][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26881 +001 1 +011 1 +100 1 +101 1 +.names xv[7][20] yv[7][16] yv[7][20] $abc$30358$new_n3904 $abc$30358$new_n3891 $abc$30358$new_n3919 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[7][20] yv[7][15] $abc$30358$new_n3921 yv[8][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26883 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] yv[7][14] xv[7][20] $abc$30358$new_n3923 $abc$30358$new_n3922 $abc$30358$new_n3921 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[7][20] $abc$30358$new_n3892 yv[7][12] yv[7][13] $abc$30358$new_n3922 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[7][20] yv[7][12] yv[7][13] $abc$30358$new_n3905 $abc$30358$new_n3923 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$30358$new_n3925 yv[8][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26885 +001 1 +011 1 +110 1 +111 1 +.names xv[7][20] yv[7][14] yv[7][20] $abc$30358$new_n3923 $abc$30358$new_n3922 $abc$30358$new_n3925 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3900 $abc$30358$new_n3927 yv[8][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26887 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[7][20] xv[7][20] yv[7][12] $abc$30358$new_n3905 $abc$30358$new_n3892 $abc$30358$new_n3927 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3929 yv[8][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26889 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n3901 yv[7][20] $abc$30358$new_n3905 $abc$30358$new_n3892 $abc$30358$new_n3929 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce xv[7][19] yv[7][11] $abc$30358$new_n3931 yv[8][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26891 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] $abc$30358$new_n3893 $abc$30358$new_n3906 yv[7][10] xv[7][18] $abc$30358$new_n3931 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[7][18] yv[7][10] $abc$30358$new_n3933 yv[8][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26893 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][17] yv[7][9] $abc$30358$new_n3907 $abc$30358$new_n3894 $abc$30358$new_n3933 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3935 yv[8][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26895 +001 1 +011 1 +110 1 +111 1 +.names xv[7][17] yv[7][9] yv[7][20] $abc$30358$new_n3907 $abc$30358$new_n3894 $abc$30358$new_n3935 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3937 yv[8][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26897 +001 1 +011 1 +110 1 +111 1 +.names xv[7][16] yv[7][8] yv[7][20] $abc$30358$new_n3908 $abc$30358$new_n3895 $abc$30358$new_n3937 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[7][15] yv[7][7] $abc$30358$new_n3939 yv[8][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26899 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] yv[7][6] xv[7][14] $abc$30358$new_n3909 $abc$30358$new_n3896 $abc$30358$new_n3939 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3941 yv[8][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26901 +001 1 +011 1 +110 1 +111 1 +.names xv[7][14] yv[7][6] yv[7][20] $abc$30358$new_n3909 $abc$30358$new_n3896 $abc$30358$new_n3941 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[7][13] yv[7][5] $abc$30358$new_n3943 yv[8][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26903 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] yv[7][4] xv[7][12] $abc$30358$new_n3910 $abc$30358$new_n3897 $abc$30358$new_n3943 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3945 yv[8][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26905 +001 1 +011 1 +110 1 +111 1 +.names xv[7][12] yv[7][4] yv[7][20] $abc$30358$new_n3910 $abc$30358$new_n3897 $abc$30358$new_n3945 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[7][11] yv[7][3] $abc$30358$new_n3947 yv[8][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26907 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] yv[7][2] xv[7][10] $abc$30358$new_n3911 $abc$30358$new_n3898 $abc$30358$new_n3947 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[7][10] yv[7][2] $abc$30358$new_n3949 yv[8][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26909 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] $abc$30358$new_n3898 $abc$30358$new_n3911 $abc$30358$new_n3949 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n3951 yv[8][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26911 +001 1 +011 1 +110 1 +111 1 +.names xv[7][9] yv[7][1] yv[7][20] yv[7][0] xv[7][8] $abc$30358$new_n3951 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[7][8] yv[7][0] yv[8][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26913 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[7][19] $abc$30358$new_n3969 $abc$30358$new_n3954 xv[8][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26915 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[7][20] $abc$30358$new_n3955 xv[7][18] $abc$30358$new_n3954 +000 1 +001 1 +010 1 +.names xv[7][16] xv[7][17] $abc$30358$new_n3956 $abc$30358$new_n3955 +110 1 +.names $abc$30358$new_n3968 $abc$30358$new_n3966 $abc$30358$new_n3967 $abc$30358$new_n3957 $abc$30358$new_n3956 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names xv[7][11] yv[7][19] $abc$30358$new_n3958 $abc$30358$new_n3957 +000 1 +001 1 +011 1 +101 1 +.names xv[7][9] yv[7][17] xv[7][10] yv[7][18] $abc$30358$new_n3959 $abc$30358$new_n3958 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][7] yv[7][15] xv[7][8] yv[7][16] $abc$30358$new_n3960 $abc$30358$new_n3959 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][5] yv[7][13] xv[7][6] yv[7][14] $abc$30358$new_n3961 $abc$30358$new_n3960 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][3] yv[7][11] xv[7][4] yv[7][12] $abc$30358$new_n3962 $abc$30358$new_n3961 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][2] yv[7][10] $abc$30358$new_n3963 $abc$30358$new_n3962 +000 1 +001 1 +011 1 +101 1 +.names xv[7][0] yv[7][8] xv[7][1] yv[7][9] $abc$30358$new_n3963 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[7][20] xv[7][12] xv[7][13] $abc$30358$new_n3966 +011 1 +100 1 +.names yv[7][20] xv[7][15] $abc$30358$new_n3967 +00 1 +11 1 +.names yv[7][20] xv[7][14] $abc$30358$new_n3968 +01 1 +10 1 +.names yv[7][20] xv[7][16] xv[7][17] xv[7][18] $abc$30358$new_n3970 $abc$30358$new_n3969 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$30358$new_n3971 xv[7][14] xv[7][15] $abc$30358$new_n3970 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n3972 xv[7][12] xv[7][13] $abc$30358$new_n3971 +111 1 +.names xv[7][10] xv[7][11] yv[7][18] yv[7][19] $abc$30358$new_n3973 $abc$30358$new_n3972 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[7][16] xv[7][8] xv[7][9] yv[7][17] $abc$30358$new_n3974 $abc$30358$new_n3973 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][14] xv[7][6] xv[7][7] yv[7][15] $abc$30358$new_n3975 $abc$30358$new_n3974 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][12] xv[7][4] xv[7][5] yv[7][13] $abc$30358$new_n3976 $abc$30358$new_n3975 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][10] xv[7][2] xv[7][3] yv[7][11] $abc$30358$new_n3977 $abc$30358$new_n3976 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[7][8] xv[7][0] xv[7][1] yv[7][9] $abc$30358$new_n3977 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$30358$new_n3971 $abc$30358$new_n3967 $abc$30358$new_n3968 $abc$30358$new_n3984 +110 1 +.names $abc$30358$new_n3986 i_ce xv[8][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26921 +001 1 +010 1 +011 1 +.names i_ce yv[7][20] xv[7][16] $abc$30358$new_n3984 $abc$30358$new_n3956 $abc$30358$new_n3986 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[7][15] xv[7][14] $abc$30358$new_n3988 xv[8][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26923 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[7][13] $abc$30358$new_n3989 $abc$30358$new_n3988 +00 1 +01 1 +10 1 +.names xv[7][12] yv[7][20] $abc$30358$new_n3957 $abc$30358$new_n3972 $abc$30358$new_n3989 +1000 1 +1001 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3988 xv[7][14] xv[8][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26925 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[7][13] $abc$30358$new_n3989 xv[8][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26927 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3993 xv[8][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26929 +001 1 +011 1 +110 1 +111 1 +.names yv[7][20] xv[7][12] $abc$30358$new_n3972 $abc$30358$new_n3957 $abc$30358$new_n3993 +0000 1 +0010 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[7][11] yv[7][19] $abc$30358$new_n3995 xv[8][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26931 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] xv[7][10] yv[7][18] $abc$30358$new_n3973 $abc$30358$new_n3958 $abc$30358$new_n3995 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[7][10] yv[7][18] $abc$30358$new_n3997 xv[8][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26933 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][9] yv[7][17] $abc$30358$new_n3959 $abc$30358$new_n3973 $abc$30358$new_n3997 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][9] yv[7][17] $abc$30358$new_n3999 xv[8][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26935 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] yv[7][16] xv[7][8] $abc$30358$new_n3974 $abc$30358$new_n3959 $abc$30358$new_n3999 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][8] yv[7][16] $abc$30358$new_n4001 xv[8][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26937 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][7] yv[7][15] $abc$30358$new_n3960 $abc$30358$new_n3974 $abc$30358$new_n4001 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][7] yv[7][15] $abc$30358$new_n4003 xv[8][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26939 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] yv[7][14] xv[7][6] $abc$30358$new_n3975 $abc$30358$new_n3960 $abc$30358$new_n4003 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][6] yv[7][14] $abc$30358$new_n4005 xv[8][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26941 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][5] yv[7][13] $abc$30358$new_n3961 $abc$30358$new_n3975 $abc$30358$new_n4005 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][5] yv[7][13] $abc$30358$new_n4007 xv[8][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26943 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] yv[7][12] xv[7][4] $abc$30358$new_n3976 $abc$30358$new_n3961 $abc$30358$new_n4007 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][4] yv[7][12] $abc$30358$new_n4009 xv[8][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26945 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][3] yv[7][11] $abc$30358$new_n3962 $abc$30358$new_n3976 $abc$30358$new_n4009 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][3] yv[7][11] $abc$30358$new_n4011 xv[8][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26947 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] xv[7][2] yv[7][10] $abc$30358$new_n3977 $abc$30358$new_n3963 $abc$30358$new_n4011 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][2] yv[7][10] $abc$30358$new_n4013 xv[8][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26949 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] $abc$30358$new_n3963 $abc$30358$new_n3977 $abc$30358$new_n4013 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4015 xv[8][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26951 +001 1 +011 1 +110 1 +111 1 +.names xv[7][1] yv[7][9] yv[7][20] xv[7][0] yv[7][8] $abc$30358$new_n4015 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[7][0] yv[7][8] xv[8][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26953 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[8][19] $abc$30358$new_n4018 ph[9][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26955 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[8][18] $abc$30358$new_n4019 $abc$30358$new_n4027 $abc$30358$new_n4018 +010 1 +011 1 +101 1 +111 1 +.names yv[8][20] $abc$30358$new_n4020 ph[8][16] ph[8][17] $abc$30358$new_n4019 +1100 1 +.names $abc$30358$new_n4021 ph[8][14] ph[8][15] $abc$30358$new_n4020 +100 1 +.names $abc$30358$new_n4022 ph[8][13] $abc$30358$new_n4021 +10 1 +.names ph[8][10] ph[8][11] ph[8][12] $abc$30358$new_n4023 $abc$30358$new_n4022 +0000 1 +.names ph[8][9] $abc$30358$new_n4024 $abc$30358$new_n4023 +10 1 +.names ph[8][8] ph[8][7] $abc$30358$new_n4025 ph[8][6] $abc$30358$new_n4024 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$30358$new_n4026 ph[8][5] $abc$30358$new_n4025 +10 1 +.names ph[8][4] ph[8][2] ph[8][3] ph[8][1] ph[8][0] $abc$30358$new_n4026 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$30358$new_n4028 ph[8][16] ph[8][17] yv[8][20] $abc$30358$new_n4027 +1110 1 +.names ph[8][14] ph[8][15] $abc$30358$new_n4029 $abc$30358$new_n4028 +111 1 +.names ph[8][13] $abc$30358$new_n4030 $abc$30358$new_n4029 +11 1 +.names ph[8][11] ph[8][12] $abc$30358$new_n4031 $abc$30358$new_n4030 +111 1 +.names ph[8][10] $abc$30358$new_n4032 ph[8][9] $abc$30358$new_n4031 +101 1 +110 1 +111 1 +.names ph[8][8] ph[8][7] ph[8][6] $abc$30358$new_n4033 $abc$30358$new_n4032 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[8][5] $abc$30358$new_n4034 $abc$30358$new_n4033 +11 1 +.names ph[8][4] ph[8][2] ph[8][3] ph[8][1] ph[8][0] $abc$30358$new_n4034 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce ph[8][18] $abc$30358$new_n4027 $abc$30358$new_n4019 ph[9][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26957 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4037 ph[9][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26959 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] ph[8][17] ph[8][16] $abc$30358$new_n4028 $abc$30358$new_n4020 $abc$30358$new_n4037 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4039 ph[9][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26961 +001 1 +011 1 +110 1 +111 1 +.names ph[8][16] yv[8][20] $abc$30358$new_n4028 $abc$30358$new_n4020 $abc$30358$new_n4039 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n4044 ph[9][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26965 +001 1 +011 1 +110 1 +111 1 +.names ph[8][14] yv[8][20] $abc$30358$new_n4029 $abc$30358$new_n4021 $abc$30358$new_n4044 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n4046 ph[9][13] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26967 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[8][13] yv[8][20] $abc$30358$new_n4030 $abc$30358$new_n4022 $abc$30358$new_n4046 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4048 ph[8][12] ph[9][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26969 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[8][20] ph[8][11] $abc$30358$new_n4031 ph[8][10] $abc$30358$new_n4023 $abc$30358$new_n4048 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4050 ph[9][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26971 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] ph[8][11] ph[8][10] $abc$30358$new_n4023 $abc$30358$new_n4031 $abc$30358$new_n4050 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4052 ph[9][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26973 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] ph[8][10] ph[8][9] $abc$30358$new_n4032 $abc$30358$new_n4024 $abc$30358$new_n4052 +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n4054 ph[9][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26975 +001 1 +011 1 +100 1 +101 1 +.names ph[8][9] yv[8][20] $abc$30358$new_n4032 $abc$30358$new_n4024 $abc$30358$new_n4054 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n4056 ph[8][8] ph[9][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26977 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[8][20] ph[8][7] ph[8][6] $abc$30358$new_n4025 $abc$30358$new_n4033 $abc$30358$new_n4056 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4058 ph[9][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26979 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] ph[8][7] ph[8][6] $abc$30358$new_n4033 $abc$30358$new_n4025 $abc$30358$new_n4058 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4060 ph[9][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26981 +001 1 +011 1 +110 1 +111 1 +.names ph[8][5] ph[8][6] $abc$30358$new_n4062 $abc$30358$new_n4061 $abc$30358$new_n4060 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[8][20] $abc$30358$new_n4026 $abc$30358$new_n4061 +11 1 +.names $abc$30358$new_n4034 yv[8][20] $abc$30358$new_n4062 +10 1 +.names i_ce ph[8][5] $abc$30358$new_n4062 $abc$30358$new_n4061 ph[9][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26983 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4065 ph[8][4] ph[9][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26985 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[8][20] ph[8][3] ph[8][0] ph[8][1] ph[8][2] $abc$30358$new_n4065 +00000 1 +00001 1 +00010 1 +00100 1 +00110 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4067 ph[9][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26987 +001 1 +011 1 +110 1 +111 1 +.names ph[8][3] yv[8][20] ph[8][2] ph[8][0] ph[8][1] $abc$30358$new_n4067 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$30358$new_n4069 ph[9][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26989 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] ph[8][2] ph[8][0] ph[8][1] $abc$30358$new_n4069 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce yv[8][20] ph[8][0] ph[8][1] ph[9][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26991 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[8][0] ph[9][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26993 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[8][20] yv[8][19] $abc$30358$new_n4073 yv[9][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26995 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][18] xv[8][20] $abc$30358$new_n4087 $abc$30358$new_n4074 $abc$30358$new_n4073 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[8][20] $abc$30358$new_n4075 yv[8][16] yv[8][17] $abc$30358$new_n4074 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[8][13] $abc$30358$new_n4084 $abc$30358$new_n4086 $abc$30358$new_n4076 $abc$30358$new_n4085 $abc$30358$new_n4075 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names yv[8][10] xv[8][19] xv[8][20] yv[8][11] $abc$30358$new_n4077 $abc$30358$new_n4076 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[8][18] yv[8][9] $abc$30358$new_n4078 $abc$30358$new_n4077 +001 1 +100 1 +101 1 +111 1 +.names xv[8][17] yv[8][8] $abc$30358$new_n4079 $abc$30358$new_n4078 +000 1 +100 1 +101 1 +110 1 +.names yv[8][6] xv[8][15] xv[8][16] yv[8][7] $abc$30358$new_n4080 $abc$30358$new_n4079 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[8][13] xv[8][14] yv[8][4] yv[8][5] $abc$30358$new_n4081 $abc$30358$new_n4080 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[8][11] xv[8][12] yv[8][2] yv[8][3] $abc$30358$new_n4082 $abc$30358$new_n4081 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[8][9] xv[8][10] yv[8][0] yv[8][1] $abc$30358$new_n4082 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[8][20] yv[8][13] $abc$30358$new_n4084 +01 1 +10 1 +.names xv[8][20] yv[8][12] $abc$30358$new_n4085 +01 1 +10 1 +.names xv[8][20] yv[8][14] yv[8][15] $abc$30358$new_n4086 +000 1 +111 1 +.names xv[8][20] $abc$30358$new_n4088 yv[8][16] yv[8][17] $abc$30358$new_n4087 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[8][20] $abc$30358$new_n4097 $abc$30358$new_n4084 $abc$30358$new_n4085 $abc$30358$new_n4089 $abc$30358$new_n4088 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +11111 1 +.names xv[8][19] yv[8][10] xv[8][20] yv[8][11] $abc$30358$new_n4090 $abc$30358$new_n4089 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][18] yv[8][9] $abc$30358$new_n4091 $abc$30358$new_n4090 +000 1 +001 1 +011 1 +101 1 +.names xv[8][17] yv[8][8] $abc$30358$new_n4092 $abc$30358$new_n4091 +000 1 +001 1 +011 1 +101 1 +.names xv[8][15] yv[8][6] xv[8][16] yv[8][7] $abc$30358$new_n4093 $abc$30358$new_n4092 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][13] yv[8][4] xv[8][14] yv[8][5] $abc$30358$new_n4094 $abc$30358$new_n4093 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][11] yv[8][2] xv[8][12] yv[8][3] $abc$30358$new_n4095 $abc$30358$new_n4094 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][9] yv[8][0] xv[8][10] yv[8][1] $abc$30358$new_n4095 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[8][20] yv[8][14] yv[8][15] $abc$30358$new_n4097 +011 1 +100 1 +.names i_ce $abc$30358$new_n4099 yv[9][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26997 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] xv[8][20] yv[8][18] $abc$30358$new_n4087 $abc$30358$new_n4074 $abc$30358$new_n4099 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][20] yv[8][17] $abc$30358$new_n4101 yv[9][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26999 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] xv[8][20] yv[8][16] $abc$30358$new_n4088 $abc$30358$new_n4075 $abc$30358$new_n4101 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4103 yv[9][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27001 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] xv[8][20] yv[8][16] $abc$30358$new_n4088 $abc$30358$new_n4075 $abc$30358$new_n4103 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][20] yv[8][15] $abc$30358$new_n4105 yv[9][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27003 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][14] yv[8][20] $abc$30358$new_n4106 xv[8][20] $abc$30358$new_n4107 $abc$30358$new_n4105 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[8][20] xv[8][20] yv[8][12] yv[8][13] $abc$30358$new_n4089 $abc$30358$new_n4106 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[8][20] yv[8][12] yv[8][13] $abc$30358$new_n4076 $abc$30358$new_n4107 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$30358$new_n4109 yv[9][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27005 +001 1 +011 1 +110 1 +111 1 +.names xv[8][20] yv[8][14] $abc$30358$new_n4106 $abc$30358$new_n4107 yv[8][20] $abc$30358$new_n4109 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10011 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4084 $abc$30358$new_n4111 yv[9][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27007 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[8][20] xv[8][20] yv[8][12] $abc$30358$new_n4089 $abc$30358$new_n4076 $abc$30358$new_n4111 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4113 yv[9][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27009 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] $abc$30358$new_n4085 $abc$30358$new_n4089 $abc$30358$new_n4076 $abc$30358$new_n4113 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[8][20] yv[8][11] $abc$30358$new_n4115 yv[9][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27011 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][10] xv[8][19] $abc$30358$new_n4090 $abc$30358$new_n4077 $abc$30358$new_n4115 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4117 yv[9][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27013 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] xv[8][19] yv[8][10] $abc$30358$new_n4090 $abc$30358$new_n4077 $abc$30358$new_n4117 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4119 yv[9][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27015 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] xv[8][18] yv[8][9] $abc$30358$new_n4091 $abc$30358$new_n4078 $abc$30358$new_n4119 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n4121 yv[9][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27017 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] xv[8][17] yv[8][8] $abc$30358$new_n4092 $abc$30358$new_n4079 $abc$30358$new_n4121 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][16] yv[8][7] $abc$30358$new_n4123 yv[9][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27019 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][6] xv[8][15] $abc$30358$new_n4093 $abc$30358$new_n4080 $abc$30358$new_n4123 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4125 yv[9][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27021 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] xv[8][15] yv[8][6] $abc$30358$new_n4093 $abc$30358$new_n4080 $abc$30358$new_n4125 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][14] yv[8][5] $abc$30358$new_n4127 yv[9][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27023 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][4] xv[8][13] $abc$30358$new_n4094 $abc$30358$new_n4081 $abc$30358$new_n4127 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4129 yv[9][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27025 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] xv[8][13] yv[8][4] $abc$30358$new_n4094 $abc$30358$new_n4081 $abc$30358$new_n4129 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][12] yv[8][3] $abc$30358$new_n4131 yv[9][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27027 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][2] xv[8][11] $abc$30358$new_n4095 $abc$30358$new_n4082 $abc$30358$new_n4131 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[8][11] yv[8][2] $abc$30358$new_n4133 yv[9][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27029 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] $abc$30358$new_n4082 $abc$30358$new_n4095 $abc$30358$new_n4133 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4135 yv[9][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27031 +001 1 +011 1 +110 1 +111 1 +.names xv[8][10] yv[8][1] yv[8][20] yv[8][0] xv[8][9] $abc$30358$new_n4135 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[8][9] yv[8][0] yv[9][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27033 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[8][14] xv[8][15] $abc$30358$new_n4140 $abc$30358$new_n4139 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[8][13] xv[8][12] $abc$30358$new_n4141 $abc$30358$new_n4140 +111 1 +.names xv[8][10] yv[8][19] $abc$30358$new_n4142 yv[8][20] xv[8][11] $abc$30358$new_n4141 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names xv[8][9] yv[8][18] $abc$30358$new_n4143 $abc$30358$new_n4142 +000 1 +001 1 +011 1 +101 1 +.names xv[8][7] yv[8][16] xv[8][8] yv[8][17] $abc$30358$new_n4144 $abc$30358$new_n4143 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][5] yv[8][14] xv[8][6] yv[8][15] $abc$30358$new_n4145 $abc$30358$new_n4144 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][3] yv[8][12] xv[8][4] yv[8][13] $abc$30358$new_n4146 $abc$30358$new_n4145 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][2] yv[8][11] $abc$30358$new_n4147 $abc$30358$new_n4146 +000 1 +001 1 +011 1 +101 1 +.names xv[8][0] yv[8][9] xv[8][1] yv[8][10] $abc$30358$new_n4147 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[8][14] xv[8][15] $abc$30358$new_n4151 $abc$30358$new_n4150 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[8][13] xv[8][12] $abc$30358$new_n4152 $abc$30358$new_n4151 +111 1 +.names yv[8][19] xv[8][10] $abc$30358$new_n4153 yv[8][20] xv[8][11] $abc$30358$new_n4152 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names yv[8][18] xv[8][9] $abc$30358$new_n4154 $abc$30358$new_n4153 +001 1 +100 1 +101 1 +111 1 +.names yv[8][17] xv[8][8] $abc$30358$new_n4155 $abc$30358$new_n4154 +001 1 +100 1 +101 1 +111 1 +.names yv[8][15] xv[8][6] xv[8][7] yv[8][16] $abc$30358$new_n4156 $abc$30358$new_n4155 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[8][13] xv[8][4] xv[8][5] yv[8][14] $abc$30358$new_n4157 $abc$30358$new_n4156 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[8][11] xv[8][2] xv[8][3] yv[8][12] $abc$30358$new_n4158 $abc$30358$new_n4157 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[8][9] xv[8][0] xv[8][1] yv[8][10] $abc$30358$new_n4158 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4163 xv[9][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27039 +001 1 +011 1 +110 1 +111 1 +.names xv[8][17] yv[8][20] xv[8][16] $abc$30358$new_n4150 $abc$30358$new_n4139 $abc$30358$new_n4163 +00100 1 +00110 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n4166 i_ce xv[9][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27041 +001 1 +010 1 +011 1 +.names i_ce xv[8][16] yv[8][20] $abc$30358$new_n4139 $abc$30358$new_n4150 $abc$30358$new_n4166 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4169 xv[9][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27043 +001 1 +011 1 +110 1 +111 1 +.names xv[8][15] yv[8][20] xv[8][14] $abc$30358$new_n4151 $abc$30358$new_n4140 $abc$30358$new_n4169 +00101 1 +00111 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4171 i_ce xv[9][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27045 +001 1 +010 1 +011 1 +.names i_ce yv[8][20] xv[8][14] $abc$30358$new_n4151 $abc$30358$new_n4140 $abc$30358$new_n4171 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4173 xv[9][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27047 +001 1 +011 1 +100 1 +101 1 +.names xv[8][13] yv[8][20] xv[8][12] $abc$30358$new_n4152 $abc$30358$new_n4141 $abc$30358$new_n4173 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10101 1 +10111 1 +11110 1 +11111 1 +.names $abc$30358$new_n4175 i_ce xv[9][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27049 +001 1 +010 1 +011 1 +.names i_ce yv[8][20] xv[8][12] $abc$30358$new_n4152 $abc$30358$new_n4141 $abc$30358$new_n4175 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][11] $abc$30358$new_n4177 xv[9][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27051 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[8][20] xv[8][10] yv[8][19] $abc$30358$new_n4153 $abc$30358$new_n4142 $abc$30358$new_n4177 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][10] yv[8][19] $abc$30358$new_n4179 xv[9][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27053 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] $abc$30358$new_n4142 $abc$30358$new_n4153 $abc$30358$new_n4179 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[8][9] yv[8][18] $abc$30358$new_n4181 xv[9][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27055 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] $abc$30358$new_n4143 $abc$30358$new_n4154 $abc$30358$new_n4181 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[8][8] yv[8][17] $abc$30358$new_n4183 xv[9][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27057 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] xv[8][7] yv[8][16] $abc$30358$new_n4144 $abc$30358$new_n4155 $abc$30358$new_n4183 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[8][7] yv[8][16] $abc$30358$new_n4185 xv[9][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27059 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] yv[8][15] xv[8][6] $abc$30358$new_n4156 $abc$30358$new_n4144 $abc$30358$new_n4185 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[8][6] yv[8][15] $abc$30358$new_n4187 xv[9][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27061 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] xv[8][5] yv[8][14] $abc$30358$new_n4145 $abc$30358$new_n4156 $abc$30358$new_n4187 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[8][5] yv[8][14] $abc$30358$new_n4189 xv[9][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27063 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] yv[8][13] xv[8][4] $abc$30358$new_n4157 $abc$30358$new_n4145 $abc$30358$new_n4189 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[8][4] yv[8][13] $abc$30358$new_n4191 xv[9][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27065 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] xv[8][3] yv[8][12] $abc$30358$new_n4146 $abc$30358$new_n4157 $abc$30358$new_n4191 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[8][3] yv[8][12] $abc$30358$new_n4193 xv[9][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27067 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] xv[8][2] yv[8][11] $abc$30358$new_n4158 $abc$30358$new_n4147 $abc$30358$new_n4193 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[8][2] yv[8][11] $abc$30358$new_n4195 xv[9][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27069 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] $abc$30358$new_n4147 $abc$30358$new_n4158 $abc$30358$new_n4195 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n4197 xv[9][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27071 +001 1 +011 1 +110 1 +111 1 +.names xv[8][1] yv[8][10] yv[8][20] xv[8][0] yv[8][9] $abc$30358$new_n4197 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[8][0] yv[8][9] xv[9][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27073 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4200 ph[9][19] ph[10][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27075 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[9][18] $abc$30358$new_n4201 $abc$30358$new_n4210 $abc$30358$new_n4200 +000 1 +010 1 +100 1 +101 1 +.names ph[9][17] $abc$30358$new_n4219 yv[9][20] $abc$30358$new_n4201 +100 1 +.names ph[9][14] ph[9][15] $abc$30358$new_n4204 $abc$30358$new_n4203 +111 1 +.names ph[9][13] $abc$30358$new_n4209 $abc$30358$new_n4205 $abc$30358$new_n4204 +111 1 +.names ph[9][9] $abc$30358$new_n4206 ph[9][8] $abc$30358$new_n4205 +101 1 +110 1 +111 1 +.names ph[9][7] ph[9][6] ph[9][5] $abc$30358$new_n4207 $abc$30358$new_n4206 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[9][4] $abc$30358$new_n4208 $abc$30358$new_n4207 +11 1 +.names ph[9][3] ph[9][2] ph[9][0] ph[9][1] $abc$30358$new_n4208 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[9][10] ph[9][11] ph[9][12] $abc$30358$new_n4209 +111 1 +.names yv[9][20] $abc$30358$new_n4211 ph[9][16] ph[9][17] $abc$30358$new_n4210 +1100 1 +.names $abc$30358$new_n4212 ph[9][14] ph[9][15] $abc$30358$new_n4211 +100 1 +.names $abc$30358$new_n4213 ph[9][12] ph[9][13] $abc$30358$new_n4212 +100 1 +.names ph[9][11] ph[9][9] ph[9][10] $abc$30358$new_n4214 ph[9][8] $abc$30358$new_n4213 +00000 1 +00010 1 +00011 1 +.names ph[9][7] ph[9][6] $abc$30358$new_n4215 ph[9][5] $abc$30358$new_n4214 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$30358$new_n4216 ph[9][4] $abc$30358$new_n4215 +10 1 +.names ph[9][3] ph[9][2] ph[9][0] ph[9][1] $abc$30358$new_n4216 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce ph[9][18] $abc$30358$new_n4210 $abc$30358$new_n4201 ph[10][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27077 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4219 ph[10][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27079 +001 1 +011 1 +110 1 +111 1 +.names yv[9][20] ph[9][17] ph[9][16] $abc$30358$new_n4211 $abc$30358$new_n4203 $abc$30358$new_n4219 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4221 ph[10][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27081 +001 1 +011 1 +110 1 +111 1 +.names yv[9][20] ph[9][16] $abc$30358$new_n4211 $abc$30358$new_n4203 $abc$30358$new_n4221 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4226 ph[10][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27085 +001 1 +011 1 +100 1 +101 1 +.names yv[9][20] ph[9][14] $abc$30358$new_n4212 $abc$30358$new_n4204 $abc$30358$new_n4226 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4231 ph[10][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27089 +001 1 +011 1 +110 1 +111 1 +.names ph[9][10] ph[9][12] ph[9][11] $abc$30358$new_n4234 $abc$30358$new_n4232 $abc$30358$new_n4231 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[9][9] $abc$30358$new_n4233 $abc$30358$new_n4232 +11 1 +.names yv[9][20] $abc$30358$new_n4206 ph[9][8] $abc$30358$new_n4233 +001 1 +010 1 +011 1 +.names $abc$30358$new_n4235 ph[9][9] $abc$30358$new_n4234 +10 1 +.names yv[9][20] $abc$30358$new_n4214 ph[9][8] $abc$30358$new_n4235 +100 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4237 ph[10][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27091 +001 1 +011 1 +110 1 +111 1 +.names ph[9][11] ph[9][10] $abc$30358$new_n4234 $abc$30358$new_n4232 $abc$30358$new_n4237 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[9][10] $abc$30358$new_n4234 $abc$30358$new_n4232 ph[10][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27093 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[9][9] $abc$30358$new_n4235 $abc$30358$new_n4233 ph[10][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27095 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4241 ph[10][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27097 +001 1 +011 1 +100 1 +101 1 +.names yv[9][20] ph[9][8] $abc$30358$new_n4214 $abc$30358$new_n4206 $abc$30358$new_n4241 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[9][7] $abc$30358$new_n4243 ph[10][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27099 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[9][20] ph[9][5] ph[9][6] $abc$30358$new_n4207 $abc$30358$new_n4215 $abc$30358$new_n4243 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4245 ph[10][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27101 +001 1 +011 1 +100 1 +101 1 +.names ph[9][4] ph[9][6] ph[9][5] $abc$30358$new_n4247 $abc$30358$new_n4246 $abc$30358$new_n4245 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$30358$new_n4208 yv[9][20] $abc$30358$new_n4246 +10 1 +.names yv[9][20] $abc$30358$new_n4216 $abc$30358$new_n4247 +11 1 +.names i_ce $abc$30358$new_n4249 ph[10][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27103 +001 1 +011 1 +110 1 +111 1 +.names ph[9][5] ph[9][4] $abc$30358$new_n4247 $abc$30358$new_n4246 $abc$30358$new_n4249 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[9][4] $abc$30358$new_n4247 $abc$30358$new_n4246 ph[10][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27105 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4252 ph[10][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27107 +001 1 +011 1 +100 1 +101 1 +.names yv[9][20] ph[9][3] ph[9][2] ph[9][0] ph[9][1] $abc$30358$new_n4252 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n4254 ph[10][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27109 +001 1 +011 1 +110 1 +111 1 +.names ph[9][2] yv[9][20] ph[9][0] ph[9][1] $abc$30358$new_n4254 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[9][20] ph[9][0] ph[9][1] ph[10][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27111 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[9][0] ph[10][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27113 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[9][20] yv[9][19] $abc$30358$new_n4258 yv[10][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27115 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][18] yv[9][20] $abc$30358$new_n4259 xv[9][20] $abc$30358$new_n4269 $abc$30358$new_n4258 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[9][20] xv[9][20] yv[9][16] yv[9][17] $abc$30358$new_n4260 $abc$30358$new_n4259 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[9][20] yv[9][14] yv[9][15] $abc$30358$new_n4261 $abc$30358$new_n4268 $abc$30358$new_n4260 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[9][12] yv[9][13] xv[9][20] yv[9][11] $abc$30358$new_n4262 $abc$30358$new_n4261 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[9][20] yv[9][10] $abc$30358$new_n4263 $abc$30358$new_n4262 +000 1 +001 1 +011 1 +101 1 +.names xv[9][18] yv[9][8] xv[9][19] yv[9][9] $abc$30358$new_n4264 $abc$30358$new_n4263 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][16] yv[9][6] xv[9][17] yv[9][7] $abc$30358$new_n4265 $abc$30358$new_n4264 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][14] yv[9][4] xv[9][15] yv[9][5] $abc$30358$new_n4266 $abc$30358$new_n4265 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][12] yv[9][2] xv[9][13] yv[9][3] $abc$30358$new_n4267 $abc$30358$new_n4266 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][10] yv[9][0] xv[9][11] yv[9][1] $abc$30358$new_n4267 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[9][12] yv[9][13] $abc$30358$new_n4268 +00 1 +.names xv[9][20] $abc$30358$new_n4270 yv[9][16] yv[9][17] $abc$30358$new_n4269 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[9][20] yv[9][14] yv[9][15] $abc$30358$new_n4271 $abc$30358$new_n4268 $abc$30358$new_n4270 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[9][20] yv[9][12] yv[9][13] $abc$30358$new_n4272 $abc$30358$new_n4271 +0000 1 +1110 1 +.names xv[9][20] yv[9][10] yv[9][11] $abc$30358$new_n4273 $abc$30358$new_n4272 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names yv[9][8] xv[9][18] xv[9][19] yv[9][9] $abc$30358$new_n4274 $abc$30358$new_n4273 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][6] xv[9][16] xv[9][17] yv[9][7] $abc$30358$new_n4275 $abc$30358$new_n4274 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[9][14] xv[9][15] yv[9][4] yv[9][5] $abc$30358$new_n4276 $abc$30358$new_n4275 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[9][12] xv[9][13] yv[9][2] yv[9][3] $abc$30358$new_n4277 $abc$30358$new_n4276 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[9][10] xv[9][11] yv[9][0] yv[9][1] $abc$30358$new_n4277 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[9][20] yv[9][18] $abc$30358$new_n4279 yv[10][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27117 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4259 $abc$30358$new_n4269 yv[9][20] $abc$30358$new_n4279 +000 1 +001 1 +011 1 +.names i_ce xv[9][20] yv[9][17] $abc$30358$new_n4281 yv[10][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27119 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][20] yv[9][16] $abc$30358$new_n4270 $abc$30358$new_n4260 $abc$30358$new_n4281 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4283 yv[10][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27121 +001 1 +011 1 +100 1 +101 1 +.names xv[9][20] yv[9][16] yv[9][20] $abc$30358$new_n4270 $abc$30358$new_n4260 $abc$30358$new_n4283 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[9][20] yv[9][15] $abc$30358$new_n4285 yv[10][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27123 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][14] xv[9][20] $abc$30358$new_n4287 $abc$30358$new_n4286 $abc$30358$new_n4285 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$30358$new_n4271 $abc$30358$new_n4268 xv[9][20] $abc$30358$new_n4286 +001 1 +010 1 +011 1 +.names $abc$30358$new_n4261 $abc$30358$new_n4268 xv[9][20] $abc$30358$new_n4287 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n4289 yv[10][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27125 +001 1 +011 1 +110 1 +111 1 +.names yv[9][20] xv[9][20] yv[9][14] $abc$30358$new_n4287 $abc$30358$new_n4286 $abc$30358$new_n4289 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][20] yv[9][13] $abc$30358$new_n4291 yv[10][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27127 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][20] yv[9][12] $abc$30358$new_n4272 $abc$30358$new_n4292 $abc$30358$new_n4291 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[9][20] yv[9][11] $abc$30358$new_n4262 $abc$30358$new_n4292 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n4294 yv[10][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27129 +001 1 +011 1 +100 1 +101 1 +.names xv[9][20] yv[9][12] yv[9][20] $abc$30358$new_n4272 $abc$30358$new_n4292 $abc$30358$new_n4294 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[9][20] yv[9][11] $abc$30358$new_n4296 yv[10][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27131 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][20] yv[9][10] $abc$30358$new_n4273 $abc$30358$new_n4263 $abc$30358$new_n4296 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4298 yv[10][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27133 +001 1 +011 1 +110 1 +111 1 +.names xv[9][20] yv[9][10] yv[9][20] $abc$30358$new_n4273 $abc$30358$new_n4263 $abc$30358$new_n4298 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[9][19] yv[9][9] $abc$30358$new_n4300 yv[10][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27135 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][8] xv[9][18] $abc$30358$new_n4274 $abc$30358$new_n4264 $abc$30358$new_n4300 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4302 yv[10][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27137 +001 1 +011 1 +100 1 +101 1 +.names xv[9][18] yv[9][8] yv[9][20] $abc$30358$new_n4274 $abc$30358$new_n4264 $abc$30358$new_n4302 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][17] yv[9][7] $abc$30358$new_n4304 yv[10][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27139 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][6] xv[9][16] $abc$30358$new_n4275 $abc$30358$new_n4265 $abc$30358$new_n4304 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4306 yv[10][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27141 +001 1 +011 1 +110 1 +111 1 +.names xv[9][16] yv[9][6] yv[9][20] $abc$30358$new_n4275 $abc$30358$new_n4265 $abc$30358$new_n4306 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[9][15] yv[9][5] $abc$30358$new_n4308 yv[10][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27143 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][4] xv[9][14] $abc$30358$new_n4276 $abc$30358$new_n4266 $abc$30358$new_n4308 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4310 yv[10][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27145 +001 1 +011 1 +100 1 +101 1 +.names xv[9][14] yv[9][4] yv[9][20] $abc$30358$new_n4276 $abc$30358$new_n4266 $abc$30358$new_n4310 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[9][13] yv[9][3] $abc$30358$new_n4312 yv[10][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27147 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][2] xv[9][12] $abc$30358$new_n4277 $abc$30358$new_n4267 $abc$30358$new_n4312 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[9][12] yv[9][2] $abc$30358$new_n4314 yv[10][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27149 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] $abc$30358$new_n4267 $abc$30358$new_n4277 $abc$30358$new_n4314 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4316 yv[10][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27151 +001 1 +011 1 +110 1 +111 1 +.names xv[9][11] yv[9][1] yv[9][20] yv[9][0] xv[9][10] $abc$30358$new_n4316 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[9][10] yv[9][0] yv[10][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27153 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4319 xv[10][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27155 +001 1 +011 1 +110 1 +111 1 +.names xv[9][19] $abc$30358$new_n4330 yv[9][20] xv[9][18] $abc$30358$new_n4320 $abc$30358$new_n4319 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[9][16] xv[9][17] $abc$30358$new_n4321 $abc$30358$new_n4320 +111 1 +.names $abc$30358$new_n4322 xv[9][13] xv[9][14] xv[9][15] $abc$30358$new_n4321 +1111 1 +.names xv[9][12] yv[9][20] xv[9][10] xv[9][11] $abc$30358$new_n4323 $abc$30358$new_n4322 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[9][9] yv[9][19] $abc$30358$new_n4324 $abc$30358$new_n4323 +000 1 +001 1 +011 1 +101 1 +.names xv[9][7] yv[9][17] xv[9][8] yv[9][18] $abc$30358$new_n4325 $abc$30358$new_n4324 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][5] yv[9][15] xv[9][6] yv[9][16] $abc$30358$new_n4326 $abc$30358$new_n4325 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][3] yv[9][13] xv[9][4] yv[9][14] $abc$30358$new_n4327 $abc$30358$new_n4326 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][2] yv[9][12] $abc$30358$new_n4328 $abc$30358$new_n4327 +000 1 +001 1 +011 1 +101 1 +.names xv[9][0] yv[9][10] xv[9][1] yv[9][11] $abc$30358$new_n4328 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[9][20] xv[9][16] xv[9][17] xv[9][18] $abc$30358$new_n4331 $abc$30358$new_n4330 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$30358$new_n4332 xv[9][14] $abc$30358$new_n4331 +00 1 +01 1 +10 1 +.names yv[9][20] xv[9][12] xv[9][13] xv[9][15] $abc$30358$new_n4333 $abc$30358$new_n4332 +00000 1 +11110 1 +.names yv[9][20] $abc$30358$new_n4334 xv[9][10] xv[9][11] $abc$30358$new_n4333 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[9][18] xv[9][8] xv[9][9] yv[9][19] $abc$30358$new_n4335 $abc$30358$new_n4334 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][16] xv[9][6] xv[9][7] yv[9][17] $abc$30358$new_n4336 $abc$30358$new_n4335 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][14] xv[9][4] xv[9][5] yv[9][15] $abc$30358$new_n4337 $abc$30358$new_n4336 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][12] xv[9][2] xv[9][3] yv[9][13] $abc$30358$new_n4338 $abc$30358$new_n4337 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[9][10] xv[9][0] xv[9][1] yv[9][11] $abc$30358$new_n4338 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4343 xv[10][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27159 +001 1 +011 1 +110 1 +111 1 +.names xv[9][17] yv[9][20] xv[9][16] $abc$30358$new_n4331 $abc$30358$new_n4321 $abc$30358$new_n4343 +00101 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n4345 i_ce xv[10][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27161 +001 1 +010 1 +011 1 +.names i_ce yv[9][20] xv[9][16] $abc$30358$new_n4331 $abc$30358$new_n4321 $abc$30358$new_n4345 +10000 1 +10010 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][15] $abc$30358$new_n4347 xv[10][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27163 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[9][14] $abc$30358$new_n4348 yv[9][20] $abc$30358$new_n4322 $abc$30358$new_n4347 +1001 1 +1010 1 +1011 1 +.names xv[9][13] xv[9][12] $abc$30358$new_n4333 $abc$30358$new_n4348 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4359 xv[10][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27171 +001 1 +011 1 +100 1 +101 1 +.names xv[9][11] yv[9][20] xv[9][10] $abc$30358$new_n4334 $abc$30358$new_n4323 $abc$30358$new_n4359 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11100 1 +11101 1 +.names $abc$30358$new_n4361 i_ce xv[10][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27173 +001 1 +010 1 +011 1 +.names i_ce yv[9][20] xv[9][10] $abc$30358$new_n4334 $abc$30358$new_n4323 $abc$30358$new_n4361 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][9] yv[9][19] $abc$30358$new_n4363 xv[10][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27175 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] yv[9][18] xv[9][8] $abc$30358$new_n4335 $abc$30358$new_n4324 $abc$30358$new_n4363 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[9][8] yv[9][18] $abc$30358$new_n4365 xv[10][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27177 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][7] yv[9][17] $abc$30358$new_n4325 $abc$30358$new_n4335 $abc$30358$new_n4365 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][7] yv[9][17] $abc$30358$new_n4367 xv[10][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27179 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] yv[9][16] xv[9][6] $abc$30358$new_n4336 $abc$30358$new_n4325 $abc$30358$new_n4367 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[9][6] yv[9][16] $abc$30358$new_n4369 xv[10][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27181 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][5] yv[9][15] $abc$30358$new_n4326 $abc$30358$new_n4336 $abc$30358$new_n4369 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][5] yv[9][15] $abc$30358$new_n4371 xv[10][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27183 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] yv[9][14] xv[9][4] $abc$30358$new_n4337 $abc$30358$new_n4326 $abc$30358$new_n4371 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[9][4] yv[9][14] $abc$30358$new_n4373 xv[10][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27185 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][3] yv[9][13] $abc$30358$new_n4327 $abc$30358$new_n4337 $abc$30358$new_n4373 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][3] yv[9][13] $abc$30358$new_n4375 xv[10][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27187 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] yv[9][12] xv[9][2] $abc$30358$new_n4338 $abc$30358$new_n4328 $abc$30358$new_n4375 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][2] yv[9][12] $abc$30358$new_n4377 xv[10][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27189 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] $abc$30358$new_n4328 $abc$30358$new_n4338 $abc$30358$new_n4377 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n4379 xv[10][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27191 +001 1 +011 1 +110 1 +111 1 +.names xv[9][1] yv[9][11] yv[9][20] xv[9][0] yv[9][10] $abc$30358$new_n4379 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[9][0] yv[9][10] xv[10][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27193 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4382 ph[10][19] ph[11][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27195 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[10][17] ph[10][18] yv[10][20] $abc$30358$new_n4383 $abc$30358$new_n4389 $abc$30358$new_n4382 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4384 ph[10][16] $abc$30358$new_n4383 +10 1 +.names $abc$30358$new_n4385 ph[10][14] ph[10][15] $abc$30358$new_n4384 +100 1 +.names $abc$30358$new_n4386 ph[10][10] ph[10][11] ph[10][12] ph[10][13] $abc$30358$new_n4385 +10000 1 +.names ph[10][9] ph[10][8] $abc$30358$new_n4387 ph[10][7] $abc$30358$new_n4386 +0000 1 +0010 1 +0011 1 +.names ph[10][6] $abc$30358$new_n4388 $abc$30358$new_n4387 +00 1 +.names ph[10][5] ph[10][3] ph[10][4] ph[10][1] ph[10][2] $abc$30358$new_n4388 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[10][16] $abc$30358$new_n4390 $abc$30358$new_n4389 +11 1 +.names ph[10][14] ph[10][15] $abc$30358$new_n4391 $abc$30358$new_n4390 +111 1 +.names ph[10][10] ph[10][11] ph[10][12] ph[10][13] $abc$30358$new_n4392 $abc$30358$new_n4391 +11111 1 +.names ph[10][9] ph[10][8] $abc$30358$new_n4393 ph[10][7] $abc$30358$new_n4392 +1101 1 +1110 1 +1111 1 +.names ph[10][6] $abc$30358$new_n4394 $abc$30358$new_n4393 +10 1 +.names ph[10][5] ph[10][3] ph[10][4] ph[10][1] ph[10][2] $abc$30358$new_n4394 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_ce $abc$30358$new_n4396 ph[11][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27197 +001 1 +011 1 +110 1 +111 1 +.names yv[10][20] ph[10][18] ph[10][17] $abc$30358$new_n4389 $abc$30358$new_n4383 $abc$30358$new_n4396 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4398 ph[11][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27199 +001 1 +011 1 +110 1 +111 1 +.names ph[10][17] yv[10][20] $abc$30358$new_n4389 $abc$30358$new_n4383 $abc$30358$new_n4398 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n4400 ph[11][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27201 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[10][16] yv[10][20] $abc$30358$new_n4390 $abc$30358$new_n4384 $abc$30358$new_n4400 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4402 ph[11][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27203 +001 1 +011 1 +110 1 +111 1 +.names yv[10][20] ph[10][15] ph[10][14] $abc$30358$new_n4391 $abc$30358$new_n4385 $abc$30358$new_n4402 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4404 ph[11][14] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27205 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[10][14] yv[10][20] $abc$30358$new_n4391 $abc$30358$new_n4385 $abc$30358$new_n4404 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4406 ph[11][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27207 +001 1 +011 1 +110 1 +111 1 +.names ph[10][11] ph[10][13] ph[10][12] $abc$30358$new_n4409 $abc$30358$new_n4407 $abc$30358$new_n4406 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[10][10] $abc$30358$new_n4408 $abc$30358$new_n4407 +11 1 +.names $abc$30358$new_n4392 yv[10][20] $abc$30358$new_n4408 +10 1 +.names $abc$30358$new_n4410 ph[10][10] $abc$30358$new_n4409 +10 1 +.names yv[10][20] $abc$30358$new_n4386 $abc$30358$new_n4410 +11 1 +.names i_ce $abc$30358$new_n4412 ph[11][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27209 +001 1 +011 1 +110 1 +111 1 +.names ph[10][12] ph[10][11] $abc$30358$new_n4409 $abc$30358$new_n4407 $abc$30358$new_n4412 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[10][11] $abc$30358$new_n4409 $abc$30358$new_n4407 ph[11][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27211 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[10][10] $abc$30358$new_n4410 $abc$30358$new_n4408 ph[11][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27213 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[10][9] $abc$30358$new_n4416 ph[11][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27215 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[10][20] ph[10][8] ph[10][7] $abc$30358$new_n4387 $abc$30358$new_n4393 $abc$30358$new_n4416 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names i_ce $abc$30358$new_n4418 ph[11][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27217 +001 1 +011 1 +110 1 +111 1 +.names ph[10][8] yv[10][20] ph[10][7] $abc$30358$new_n4393 $abc$30358$new_n4387 $abc$30358$new_n4418 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4420 ph[11][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27219 +001 1 +011 1 +100 1 +101 1 +.names yv[10][20] ph[10][7] ph[10][6] $abc$30358$new_n4394 $abc$30358$new_n4388 $abc$30358$new_n4420 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4422 ph[11][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27221 +001 1 +011 1 +100 1 +101 1 +.names ph[10][6] yv[10][20] $abc$30358$new_n4394 $abc$30358$new_n4388 $abc$30358$new_n4422 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[10][5] $abc$30358$new_n4424 ph[11][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27223 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[10][20] ph[10][1] ph[10][2] ph[10][3] ph[10][4] $abc$30358$new_n4424 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4426 ph[11][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27225 +001 1 +011 1 +110 1 +111 1 +.names yv[10][20] ph[10][4] ph[10][1] ph[10][2] ph[10][3] $abc$30358$new_n4426 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4428 ph[11][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27227 +001 1 +011 1 +100 1 +101 1 +.names ph[10][3] yv[10][20] ph[10][1] ph[10][2] $abc$30358$new_n4428 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[10][20] ph[10][1] ph[10][2] ph[11][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27229 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[10][1] ph[11][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27231 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[10][0] ph[11][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27233 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[10][20] yv[10][19] $abc$30358$new_n4433 yv[11][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27235 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][18] yv[10][20] $abc$30358$new_n4434 xv[10][20] $abc$30358$new_n4449 $abc$30358$new_n4433 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[10][20] xv[10][20] yv[10][16] yv[10][17] $abc$30358$new_n4435 $abc$30358$new_n4434 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4443 $abc$30358$new_n4446 $abc$30358$new_n4436 $abc$30358$new_n4448 $abc$30358$new_n4447 $abc$30358$new_n4435 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names yv[10][12] xv[10][20] yv[10][10] yv[10][11] $abc$30358$new_n4437 $abc$30358$new_n4436 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[10][19] yv[10][8] xv[10][20] yv[10][9] $abc$30358$new_n4438 $abc$30358$new_n4437 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][17] yv[10][6] xv[10][18] yv[10][7] $abc$30358$new_n4439 $abc$30358$new_n4438 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][16] yv[10][5] $abc$30358$new_n4440 $abc$30358$new_n4439 +000 1 +001 1 +011 1 +101 1 +.names xv[10][14] yv[10][3] xv[10][15] yv[10][4] $abc$30358$new_n4441 $abc$30358$new_n4440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][13] yv[10][2] $abc$30358$new_n4442 $abc$30358$new_n4441 +000 1 +001 1 +011 1 +101 1 +.names xv[10][11] yv[10][0] xv[10][12] yv[10][1] $abc$30358$new_n4442 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[10][20] $abc$30358$new_n4444 $abc$30358$new_n4443 +10 1 +.names $abc$30358$new_n4445 yv[10][14] yv[10][15] $abc$30358$new_n4444 +100 1 +.names yv[10][12] yv[10][13] $abc$30358$new_n4445 +00 1 +.names xv[10][20] yv[10][13] $abc$30358$new_n4446 +01 1 +10 1 +.names xv[10][20] yv[10][14] $abc$30358$new_n4447 +01 1 +10 1 +.names xv[10][20] yv[10][15] $abc$30358$new_n4448 +01 1 +10 1 +.names xv[10][20] yv[10][16] yv[10][17] $abc$30358$new_n4450 $abc$30358$new_n4444 $abc$30358$new_n4449 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4458 xv[10][20] yv[10][12] yv[10][13] $abc$30358$new_n4451 $abc$30358$new_n4450 +10000 1 +11110 1 +.names xv[10][20] $abc$30358$new_n4452 yv[10][9] yv[10][10] yv[10][11] $abc$30358$new_n4451 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[10][19] yv[10][8] $abc$30358$new_n4453 $abc$30358$new_n4452 +000 1 +100 1 +101 1 +110 1 +.names yv[10][6] xv[10][17] xv[10][18] yv[10][7] $abc$30358$new_n4454 $abc$30358$new_n4453 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[10][16] yv[10][5] $abc$30358$new_n4455 $abc$30358$new_n4454 +001 1 +100 1 +101 1 +111 1 +.names xv[10][14] xv[10][15] yv[10][3] yv[10][4] $abc$30358$new_n4456 $abc$30358$new_n4455 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[10][13] yv[10][2] $abc$30358$new_n4457 $abc$30358$new_n4456 +001 1 +100 1 +101 1 +111 1 +.names xv[10][11] xv[10][12] yv[10][0] yv[10][1] $abc$30358$new_n4457 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$30358$new_n4448 $abc$30358$new_n4447 $abc$30358$new_n4458 +00 1 +.names i_ce xv[10][20] yv[10][18] $abc$30358$new_n4460 yv[11][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27237 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4434 $abc$30358$new_n4449 yv[10][20] $abc$30358$new_n4460 +000 1 +001 1 +011 1 +.names i_ce xv[10][20] yv[10][17] $abc$30358$new_n4462 yv[11][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27239 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] xv[10][20] yv[10][16] $abc$30358$new_n4435 $abc$30358$new_n4463 $abc$30358$new_n4462 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4450 $abc$30358$new_n4444 xv[10][20] $abc$30358$new_n4463 +001 1 +010 1 +011 1 +.names i_ce xv[10][20] yv[10][16] $abc$30358$new_n4465 yv[11][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27241 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] $abc$30358$new_n4463 $abc$30358$new_n4435 $abc$30358$new_n4465 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4467 $abc$30358$new_n4448 yv[11][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27243 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[10][20] yv[10][14] xv[10][20] $abc$30358$new_n4470 $abc$30358$new_n4468 $abc$30358$new_n4467 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[10][20] yv[10][12] yv[10][13] $abc$30358$new_n4469 $abc$30358$new_n4468 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[10][20] yv[10][10] yv[10][11] $abc$30358$new_n4437 $abc$30358$new_n4469 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[10][20] $abc$30358$new_n4451 yv[10][12] yv[10][13] $abc$30358$new_n4470 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4446 $abc$30358$new_n4475 yv[11][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27247 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[10][20] xv[10][20] yv[10][12] $abc$30358$new_n4451 $abc$30358$new_n4469 $abc$30358$new_n4475 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4477 yv[11][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27249 +001 1 +011 1 +100 1 +101 1 +.names xv[10][20] yv[10][12] yv[10][20] $abc$30358$new_n4451 $abc$30358$new_n4469 $abc$30358$new_n4477 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[10][20] yv[10][11] $abc$30358$new_n4479 yv[11][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27251 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] yv[10][10] xv[10][20] $abc$30358$new_n4437 $abc$30358$new_n4480 $abc$30358$new_n4479 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[10][20] yv[10][9] $abc$30358$new_n4452 $abc$30358$new_n4480 +001 1 +100 1 +101 1 +111 1 +.names i_ce xv[10][20] yv[10][10] $abc$30358$new_n4482 yv[11][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27253 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] $abc$30358$new_n4480 $abc$30358$new_n4437 $abc$30358$new_n4482 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[10][20] yv[10][9] $abc$30358$new_n4484 yv[11][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27255 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] yv[10][8] xv[10][19] $abc$30358$new_n4453 $abc$30358$new_n4438 $abc$30358$new_n4484 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4486 yv[11][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27257 +001 1 +011 1 +100 1 +101 1 +.names xv[10][19] yv[10][8] yv[10][20] $abc$30358$new_n4453 $abc$30358$new_n4438 $abc$30358$new_n4486 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[10][18] yv[10][7] $abc$30358$new_n4488 yv[11][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27259 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] yv[10][6] xv[10][17] $abc$30358$new_n4454 $abc$30358$new_n4439 $abc$30358$new_n4488 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4490 yv[11][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27261 +001 1 +011 1 +110 1 +111 1 +.names xv[10][17] yv[10][6] yv[10][20] $abc$30358$new_n4454 $abc$30358$new_n4439 $abc$30358$new_n4490 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4492 yv[11][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27263 +001 1 +011 1 +100 1 +101 1 +.names xv[10][16] yv[10][5] yv[10][20] $abc$30358$new_n4455 $abc$30358$new_n4440 $abc$30358$new_n4492 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[10][15] yv[10][4] $abc$30358$new_n4494 yv[11][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27265 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] yv[10][3] xv[10][14] $abc$30358$new_n4456 $abc$30358$new_n4441 $abc$30358$new_n4494 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[10][14] yv[10][3] $abc$30358$new_n4496 yv[11][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27267 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] $abc$30358$new_n4441 $abc$30358$new_n4456 $abc$30358$new_n4496 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[10][13] yv[10][2] $abc$30358$new_n4498 yv[11][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27269 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] $abc$30358$new_n4442 $abc$30358$new_n4457 $abc$30358$new_n4498 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4500 yv[11][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27271 +001 1 +011 1 +110 1 +111 1 +.names xv[10][12] yv[10][1] yv[10][20] yv[10][0] xv[10][11] $abc$30358$new_n4500 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[10][11] yv[10][0] yv[11][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27273 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[10][19] $abc$30358$new_n4514 $abc$30358$new_n4503 xv[11][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27275 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[10][18] xv[10][16] xv[10][17] $abc$30358$new_n4504 $abc$30358$new_n4503 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names xv[10][14] xv[10][15] $abc$30358$new_n4505 $abc$30358$new_n4504 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[10][12] xv[10][13] $abc$30358$new_n4506 $abc$30358$new_n4505 +110 1 +.names yv[10][20] $abc$30358$new_n4507 xv[10][9] xv[10][10] xv[10][11] $abc$30358$new_n4506 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[10][7] yv[10][18] xv[10][8] yv[10][19] $abc$30358$new_n4508 $abc$30358$new_n4507 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][5] yv[10][16] xv[10][6] yv[10][17] $abc$30358$new_n4509 $abc$30358$new_n4508 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][3] yv[10][14] xv[10][4] yv[10][15] $abc$30358$new_n4510 $abc$30358$new_n4509 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][2] yv[10][13] $abc$30358$new_n4511 $abc$30358$new_n4510 +000 1 +001 1 +011 1 +101 1 +.names xv[10][0] yv[10][11] xv[10][1] yv[10][12] $abc$30358$new_n4511 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[10][14] xv[10][15] $abc$30358$new_n4515 $abc$30358$new_n4514 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n4516 xv[10][12] xv[10][13] $abc$30358$new_n4515 +111 1 +.names yv[10][20] xv[10][10] xv[10][11] $abc$30358$new_n4517 xv[10][9] $abc$30358$new_n4516 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11110 1 +11111 1 +.names yv[10][19] xv[10][8] $abc$30358$new_n4518 yv[10][20] xv[10][9] $abc$30358$new_n4517 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names yv[10][17] xv[10][6] xv[10][7] yv[10][18] $abc$30358$new_n4519 $abc$30358$new_n4518 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[10][15] xv[10][4] xv[10][5] yv[10][16] $abc$30358$new_n4520 $abc$30358$new_n4519 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[10][13] xv[10][2] xv[10][3] yv[10][14] $abc$30358$new_n4521 $abc$30358$new_n4520 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[10][11] xv[10][0] xv[10][1] yv[10][12] $abc$30358$new_n4521 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4526 xv[11][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27279 +001 1 +011 1 +110 1 +111 1 +.names xv[10][17] xv[10][16] $abc$30358$new_n4527 $abc$30358$new_n4514 $abc$30358$new_n4526 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$30358$new_n4505 xv[10][14] xv[10][15] $abc$30358$new_n4527 +111 1 +.names i_ce $abc$30358$new_n4531 xv[11][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27283 +001 1 +011 1 +100 1 +101 1 +.names xv[10][15] xv[10][14] $abc$30358$new_n4505 $abc$30358$new_n4515 $abc$30358$new_n4531 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1111 1 +.names i_ce xv[10][13] $abc$30358$new_n4536 xv[11][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27287 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[10][12] $abc$30358$new_n4516 $abc$30358$new_n4506 $abc$30358$new_n4536 +110 1 +.names i_ce xv[10][11] $abc$30358$new_n4540 xv[11][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27291 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[10][10] yv[10][20] $abc$30358$new_n4541 $abc$30358$new_n4517 $abc$30358$new_n4540 +1010 1 +1011 1 +1101 1 +1111 1 +.names xv[10][9] $abc$30358$new_n4507 $abc$30358$new_n4541 +10 1 +.names $abc$30358$new_n4543 i_ce xv[11][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27293 +001 1 +010 1 +011 1 +.names i_ce yv[10][20] xv[10][10] $abc$30358$new_n4517 $abc$30358$new_n4541 $abc$30358$new_n4543 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4545 xv[10][9] xv[11][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27295 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[10][20] yv[10][19] xv[10][8] $abc$30358$new_n4518 $abc$30358$new_n4507 $abc$30358$new_n4545 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][8] yv[10][19] $abc$30358$new_n4547 xv[11][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27297 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] xv[10][7] yv[10][18] $abc$30358$new_n4508 $abc$30358$new_n4518 $abc$30358$new_n4547 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[10][7] yv[10][18] $abc$30358$new_n4549 xv[11][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27299 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] yv[10][17] xv[10][6] $abc$30358$new_n4519 $abc$30358$new_n4508 $abc$30358$new_n4549 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][6] yv[10][17] $abc$30358$new_n4551 xv[11][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27301 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] xv[10][5] yv[10][16] $abc$30358$new_n4509 $abc$30358$new_n4519 $abc$30358$new_n4551 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[10][5] yv[10][16] $abc$30358$new_n4553 xv[11][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27303 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] yv[10][15] xv[10][4] $abc$30358$new_n4520 $abc$30358$new_n4509 $abc$30358$new_n4553 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][4] yv[10][15] $abc$30358$new_n4555 xv[11][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27305 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] xv[10][3] yv[10][14] $abc$30358$new_n4510 $abc$30358$new_n4520 $abc$30358$new_n4555 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[10][3] yv[10][14] $abc$30358$new_n4557 xv[11][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27307 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] xv[10][2] yv[10][13] $abc$30358$new_n4521 $abc$30358$new_n4511 $abc$30358$new_n4557 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][2] yv[10][13] $abc$30358$new_n4559 xv[11][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27309 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] $abc$30358$new_n4511 $abc$30358$new_n4521 $abc$30358$new_n4559 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4561 xv[11][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27311 +001 1 +011 1 +110 1 +111 1 +.names xv[10][1] yv[10][12] yv[10][20] xv[10][0] yv[10][11] $abc$30358$new_n4561 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[10][0] yv[10][11] xv[11][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27313 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4564 ph[11][19] ph[12][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27315 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[11][18] $abc$30358$new_n4565 $abc$30358$new_n4571 $abc$30358$new_n4564 +000 1 +001 1 +100 1 +110 1 +.names $abc$30358$new_n4566 ph[11][16] ph[11][17] $abc$30358$new_n4565 +100 1 +.names yv[11][20] $abc$30358$new_n4567 ph[11][15] $abc$30358$new_n4566 +110 1 +.names $abc$30358$new_n4568 ph[11][13] ph[11][14] $abc$30358$new_n4567 +100 1 +.names $abc$30358$new_n4569 ph[11][9] ph[11][10] ph[11][11] ph[11][12] $abc$30358$new_n4568 +10000 1 +.names ph[11][7] ph[11][8] ph[11][6] ph[11][5] $abc$30358$new_n4570 $abc$30358$new_n4569 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names ph[11][4] ph[11][2] ph[11][3] ph[11][0] ph[11][1] $abc$30358$new_n4570 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[11][16] ph[11][17] $abc$30358$new_n4572 $abc$30358$new_n4571 +111 1 +.names $abc$30358$new_n4573 ph[11][15] yv[11][20] $abc$30358$new_n4572 +110 1 +.names $abc$30358$new_n4574 ph[11][6] ph[11][5] $abc$30358$new_n4576 $abc$30358$new_n4573 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[11][10] ph[11][11] ph[11][12] $abc$30358$new_n4575 $abc$30358$new_n4574 +1111 1 +.names ph[11][7] ph[11][8] ph[11][9] ph[11][13] ph[11][14] $abc$30358$new_n4575 +11111 1 +.names ph[11][4] ph[11][2] ph[11][3] ph[11][0] ph[11][1] $abc$30358$new_n4576 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_ce ph[11][18] $abc$30358$new_n4571 $abc$30358$new_n4565 ph[12][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27317 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n4579 i_ce ph[12][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27319 +001 1 +010 1 +011 1 +.names i_ce ph[11][16] ph[11][17] $abc$30358$new_n4572 $abc$30358$new_n4566 $abc$30358$new_n4579 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[11][16] $abc$30358$new_n4572 $abc$30358$new_n4566 ph[12][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27321 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n4582 ph[12][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27323 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[11][15] yv[11][20] $abc$30358$new_n4573 $abc$30358$new_n4567 $abc$30358$new_n4582 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4584 ph[12][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27325 +001 1 +011 1 +100 1 +101 1 +.names ph[11][14] ph[11][12] ph[11][13] $abc$30358$new_n4590 $abc$30358$new_n4585 $abc$30358$new_n4584 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11101 1 +11111 1 +.names ph[11][11] $abc$30358$new_n4586 $abc$30358$new_n4585 +11 1 +.names ph[11][10] $abc$30358$new_n4587 $abc$30358$new_n4586 +11 1 +.names ph[11][9] $abc$30358$new_n4588 $abc$30358$new_n4587 +11 1 +.names ph[11][8] $abc$30358$new_n4589 $abc$30358$new_n4588 +11 1 +.names ph[11][7] yv[11][20] ph[11][6] ph[11][5] $abc$30358$new_n4576 $abc$30358$new_n4589 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$30358$new_n4591 ph[11][11] $abc$30358$new_n4590 +10 1 +.names $abc$30358$new_n4592 ph[11][10] $abc$30358$new_n4591 +10 1 +.names $abc$30358$new_n4593 ph[11][9] $abc$30358$new_n4592 +10 1 +.names $abc$30358$new_n4594 ph[11][8] $abc$30358$new_n4593 +10 1 +.names yv[11][20] ph[11][7] ph[11][6] ph[11][5] $abc$30358$new_n4570 $abc$30358$new_n4594 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names i_ce $abc$30358$new_n4596 ph[11][13] ph[12][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27327 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[11][12] $abc$30358$new_n4585 $abc$30358$new_n4590 $abc$30358$new_n4596 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[11][12] $abc$30358$new_n4590 $abc$30358$new_n4585 ph[12][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27329 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[11][11] $abc$30358$new_n4591 $abc$30358$new_n4586 ph[12][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27331 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[11][10] $abc$30358$new_n4592 $abc$30358$new_n4587 ph[12][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27333 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[11][9] $abc$30358$new_n4593 $abc$30358$new_n4588 ph[12][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27335 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[11][8] $abc$30358$new_n4594 $abc$30358$new_n4589 ph[12][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27337 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4603 ph[11][7] ph[12][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27339 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[11][20] ph[11][6] ph[11][5] $abc$30358$new_n4570 $abc$30358$new_n4576 $abc$30358$new_n4603 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4605 ph[12][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27341 +001 1 +011 1 +110 1 +111 1 +.names ph[11][6] yv[11][20] ph[11][5] $abc$30358$new_n4576 $abc$30358$new_n4570 $abc$30358$new_n4605 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n4607 ph[12][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27343 +001 1 +011 1 +110 1 +111 1 +.names ph[11][5] yv[11][20] $abc$30358$new_n4576 $abc$30358$new_n4570 $abc$30358$new_n4607 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[11][4] $abc$30358$new_n4609 ph[12][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27345 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[11][20] ph[11][0] ph[11][1] ph[11][2] ph[11][3] $abc$30358$new_n4609 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4611 ph[12][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27347 +001 1 +011 1 +110 1 +111 1 +.names yv[11][20] ph[11][3] ph[11][0] ph[11][1] ph[11][2] $abc$30358$new_n4611 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4613 ph[12][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27349 +001 1 +011 1 +100 1 +101 1 +.names ph[11][2] yv[11][20] ph[11][0] ph[11][1] $abc$30358$new_n4613 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[11][20] ph[11][0] ph[11][1] ph[12][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27351 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[11][0] ph[12][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27353 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[11][20] yv[11][19] $abc$30358$new_n4617 yv[12][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27355 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][18] xv[11][20] $abc$30358$new_n4633 $abc$30358$new_n4618 $abc$30358$new_n4617 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[11][20] $abc$30358$new_n4619 yv[11][16] yv[11][17] $abc$30358$new_n4618 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][20] $abc$30358$new_n4628 $abc$30358$new_n4620 yv[11][12] $abc$30358$new_n4619 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names xv[11][20] $abc$30358$new_n4662 yv[11][10] yv[11][11] $abc$30358$new_n4620 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][19] yv[11][7] $abc$30358$new_n4623 $abc$30358$new_n4622 +000 1 +001 1 +011 1 +101 1 +.names xv[11][17] yv[11][5] xv[11][18] yv[11][6] $abc$30358$new_n4624 $abc$30358$new_n4623 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11][15] yv[11][3] xv[11][16] yv[11][4] $abc$30358$new_n4625 $abc$30358$new_n4624 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11][14] yv[11][2] $abc$30358$new_n4626 $abc$30358$new_n4625 +000 1 +001 1 +011 1 +101 1 +.names xv[11][12] yv[11][0] xv[11][13] yv[11][1] $abc$30358$new_n4626 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$30358$new_n4631 $abc$30358$new_n4630 $abc$30358$new_n4629 $abc$30358$new_n4628 +111 1 +.names xv[11][20] yv[11][13] $abc$30358$new_n4629 +01 1 +10 1 +.names xv[11][20] yv[11][15] $abc$30358$new_n4630 +01 1 +10 1 +.names xv[11][20] yv[11][14] $abc$30358$new_n4631 +01 1 +10 1 +.names xv[11][20] $abc$30358$new_n6046 yv[11][16] yv[11][17] $abc$30358$new_n4633 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[11][20] yv[11][8] yv[11][9] $abc$30358$new_n4637 $abc$30358$new_n4636 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names yv[11][6] xv[11][18] xv[11][19] yv[11][7] $abc$30358$new_n4638 $abc$30358$new_n4637 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[11][17] yv[11][5] $abc$30358$new_n4639 $abc$30358$new_n4638 +001 1 +100 1 +101 1 +111 1 +.names xv[11][15] xv[11][16] yv[11][3] yv[11][4] $abc$30358$new_n4640 $abc$30358$new_n4639 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[11][14] yv[11][2] $abc$30358$new_n4641 $abc$30358$new_n4640 +001 1 +100 1 +101 1 +111 1 +.names xv[11][12] xv[11][13] yv[11][0] yv[11][1] $abc$30358$new_n4641 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[11][20] yv[11][18] $abc$30358$new_n4644 yv[12][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27357 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] $abc$30358$new_n4618 $abc$30358$new_n4633 $abc$30358$new_n4644 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[11][20] yv[11][17] $abc$30358$new_n4646 yv[12][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27359 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][16] xv[11][20] $abc$30358$new_n6046 $abc$30358$new_n4619 $abc$30358$new_n4646 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4648 yv[12][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27361 +001 1 +011 1 +100 1 +101 1 +.names xv[11][20] yv[11][16] yv[11][20] $abc$30358$new_n6046 $abc$30358$new_n4619 $abc$30358$new_n4648 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n4650 $abc$30358$new_n4630 yv[12][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27363 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[11][20] yv[11][14] xv[11][20] $abc$30358$new_n4652 $abc$30358$new_n4651 $abc$30358$new_n4650 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names xv[11][20] yv[11][12] yv[11][13] $abc$30358$new_n4620 $abc$30358$new_n4651 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[11][20] $abc$30358$new_n4653 yv[11][12] yv[11][13] $abc$30358$new_n4652 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[11][20] $abc$30358$new_n4636 yv[11][10] yv[11][11] $abc$30358$new_n4653 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4655 yv[12][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27365 +001 1 +011 1 +100 1 +101 1 +.names $abc$30358$new_n4631 yv[11][20] $abc$30358$new_n4652 $abc$30358$new_n4651 $abc$30358$new_n4655 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n4657 $abc$30358$new_n4629 yv[12][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27367 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[11][20] yv[11][12] xv[11][20] $abc$30358$new_n4653 $abc$30358$new_n4620 $abc$30358$new_n4657 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4659 yv[12][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27369 +001 1 +011 1 +100 1 +101 1 +.names xv[11][20] yv[11][12] yv[11][20] $abc$30358$new_n4653 $abc$30358$new_n4620 $abc$30358$new_n4659 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[11][20] yv[11][11] $abc$30358$new_n4661 yv[12][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27371 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][10] xv[11][20] $abc$30358$new_n4662 $abc$30358$new_n4636 $abc$30358$new_n4661 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[11][20] $abc$30358$new_n4622 yv[11][8] yv[11][9] $abc$30358$new_n4662 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$30358$new_n4664 yv[12][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27373 +001 1 +011 1 +110 1 +111 1 +.names yv[11][20] xv[11][20] yv[11][10] $abc$30358$new_n4662 $abc$30358$new_n4636 $abc$30358$new_n4664 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[11][20] yv[11][9] $abc$30358$new_n4666 yv[12][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27375 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][8] xv[11][20] $abc$30358$new_n4637 $abc$30358$new_n4622 $abc$30358$new_n4666 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4668 yv[12][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27377 +001 1 +011 1 +100 1 +101 1 +.names xv[11][20] yv[11][8] yv[11][20] $abc$30358$new_n4637 $abc$30358$new_n4622 $abc$30358$new_n4668 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[11][19] yv[11][7] $abc$30358$new_n4670 yv[12][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27379 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][6] xv[11][18] $abc$30358$new_n4638 $abc$30358$new_n4623 $abc$30358$new_n4670 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[11][18] yv[11][6] $abc$30358$new_n4672 yv[12][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27381 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] xv[11][17] yv[11][5] $abc$30358$new_n4639 $abc$30358$new_n4624 $abc$30358$new_n4672 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4674 yv[12][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27383 +001 1 +011 1 +110 1 +111 1 +.names xv[11][17] yv[11][5] yv[11][20] $abc$30358$new_n4639 $abc$30358$new_n4624 $abc$30358$new_n4674 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[11][16] yv[11][4] $abc$30358$new_n4676 yv[12][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27385 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] xv[11][15] yv[11][3] $abc$30358$new_n4640 $abc$30358$new_n4625 $abc$30358$new_n4676 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[11][15] yv[11][3] $abc$30358$new_n4678 yv[12][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27387 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] $abc$30358$new_n4625 $abc$30358$new_n4640 $abc$30358$new_n4678 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[11][14] yv[11][2] $abc$30358$new_n4680 yv[12][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27389 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] $abc$30358$new_n4626 $abc$30358$new_n4641 $abc$30358$new_n4680 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4682 yv[12][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27391 +001 1 +011 1 +110 1 +111 1 +.names xv[11][13] yv[11][1] yv[11][20] yv[11][0] xv[11][12] $abc$30358$new_n4682 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[11][12] yv[11][0] yv[12][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27393 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4685 xv[12][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27395 +001 1 +011 1 +110 1 +111 1 +.names xv[11][19] $abc$30358$new_n4697 yv[11][20] xv[11][18] $abc$30358$new_n4686 $abc$30358$new_n4685 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[11][16] xv[11][17] $abc$30358$new_n4687 $abc$30358$new_n4686 +111 1 +.names $abc$30358$new_n4695 xv[11][12] xv[11][13] $abc$30358$new_n4688 $abc$30358$new_n4687 +1110 1 +.names xv[11][11] $abc$30358$new_n4689 yv[11][20] xv[11][10] $abc$30358$new_n4688 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names xv[11][10] yv[11][20] xv[11][8] xv[11][9] $abc$30358$new_n4690 $abc$30358$new_n4689 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[11][7] yv[11][19] $abc$30358$new_n4691 $abc$30358$new_n4690 +000 1 +001 1 +011 1 +101 1 +.names xv[11][5] yv[11][17] xv[11][6] yv[11][18] $abc$30358$new_n4692 $abc$30358$new_n4691 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11][3] yv[11][15] xv[11][4] yv[11][16] $abc$30358$new_n4693 $abc$30358$new_n4692 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11][2] yv[11][14] $abc$30358$new_n4694 $abc$30358$new_n4693 +000 1 +001 1 +011 1 +101 1 +.names xv[11][0] yv[11][12] xv[11][1] yv[11][13] $abc$30358$new_n4694 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[11][20] xv[11][14] xv[11][15] $abc$30358$new_n4695 +011 1 +100 1 +.names yv[11][20] xv[11][17] $abc$30358$new_n4699 xv[11][18] xv[11][16] $abc$30358$new_n4697 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$30358$new_n4700 yv[11][20] xv[11][13] xv[11][14] xv[11][15] $abc$30358$new_n4699 +10000 1 +11111 1 +.names yv[11][20] xv[11][12] $abc$30358$new_n4701 $abc$30358$new_n4700 +000 1 +110 1 +.names yv[11][20] $abc$30358$new_n4707 $abc$30358$new_n4702 xv[11][8] $abc$30358$new_n4701 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names yv[11][18] xv[11][6] xv[11][7] yv[11][19] $abc$30358$new_n4703 $abc$30358$new_n4702 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[11][16] xv[11][4] xv[11][5] yv[11][17] $abc$30358$new_n4704 $abc$30358$new_n4703 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[11][14] xv[11][2] xv[11][3] yv[11][15] $abc$30358$new_n4705 $abc$30358$new_n4704 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[11][12] xv[11][0] xv[11][1] yv[11][13] $abc$30358$new_n4705 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[11][20] xv[11][9] xv[11][10] xv[11][11] $abc$30358$new_n4707 +0000 1 +1111 1 +.names i_ce $abc$30358$new_n4712 xv[12][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27399 +001 1 +011 1 +110 1 +111 1 +.names xv[11][17] yv[11][20] xv[11][16] $abc$30358$new_n4699 $abc$30358$new_n4687 $abc$30358$new_n4712 +00101 1 +00111 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4714 i_ce xv[12][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27401 +001 1 +010 1 +011 1 +.names i_ce yv[11][20] xv[11][16] $abc$30358$new_n4699 $abc$30358$new_n4687 $abc$30358$new_n4714 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4716 xv[12][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27403 +001 1 +011 1 +110 1 +111 1 +.names xv[11][15] xv[11][14] $abc$30358$new_n4717 $abc$30358$new_n4718 $abc$30358$new_n4716 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names xv[11][12] xv[11][13] $abc$30358$new_n4688 $abc$30358$new_n4717 +110 1 +.names yv[11][20] $abc$30358$new_n4701 xv[11][12] xv[11][13] $abc$30358$new_n4718 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4722 xv[12][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27407 +001 1 +011 1 +110 1 +111 1 +.names xv[11][13] yv[11][20] $abc$30358$new_n4700 $abc$30358$new_n4688 $abc$30358$new_n4722 +0000 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[11][11] xv[11][10] $abc$30358$new_n4726 xv[12][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27411 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[11][9] $abc$30358$new_n4728 $abc$30358$new_n4727 $abc$30358$new_n4726 +100 1 +.names yv[11][20] $abc$30358$new_n4690 xv[11][8] $abc$30358$new_n4727 +000 1 +010 1 +011 1 +.names yv[11][20] $abc$30358$new_n4702 xv[11][8] $abc$30358$new_n4728 +100 1 +110 1 +111 1 +.names i_ce xv[11][10] $abc$30358$new_n4726 xv[12][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27413 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[11][9] $abc$30358$new_n4728 $abc$30358$new_n4727 xv[12][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27415 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4732 i_ce xv[12][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27417 +001 1 +010 1 +011 1 +.names i_ce yv[11][20] xv[11][8] $abc$30358$new_n4702 $abc$30358$new_n4690 $abc$30358$new_n4732 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[11][7] yv[11][19] $abc$30358$new_n4734 xv[12][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27419 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] yv[11][18] xv[11][6] $abc$30358$new_n4703 $abc$30358$new_n4691 $abc$30358$new_n4734 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[11][6] yv[11][18] $abc$30358$new_n4736 xv[12][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27421 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] xv[11][5] yv[11][17] $abc$30358$new_n4692 $abc$30358$new_n4703 $abc$30358$new_n4736 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[11][5] yv[11][17] $abc$30358$new_n4738 xv[12][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27423 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] yv[11][16] xv[11][4] $abc$30358$new_n4704 $abc$30358$new_n4692 $abc$30358$new_n4738 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[11][4] yv[11][16] $abc$30358$new_n4740 xv[12][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27425 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] xv[11][3] yv[11][15] $abc$30358$new_n4693 $abc$30358$new_n4704 $abc$30358$new_n4740 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[11][3] yv[11][15] $abc$30358$new_n4742 xv[12][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27427 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] xv[11][2] yv[11][14] $abc$30358$new_n4705 $abc$30358$new_n4694 $abc$30358$new_n4742 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[11][2] yv[11][14] $abc$30358$new_n4744 xv[12][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27429 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] $abc$30358$new_n4694 $abc$30358$new_n4705 $abc$30358$new_n4744 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4746 xv[12][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27431 +001 1 +011 1 +110 1 +111 1 +.names xv[11][1] yv[11][13] yv[11][20] xv[11][0] yv[11][12] $abc$30358$new_n4746 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[11][0] yv[11][12] xv[12][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27433 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[12][19] $abc$30358$new_n4749 ph[13][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27435 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[12][18] yv[12][20] $abc$30358$new_n4750 $abc$30358$new_n4754 $abc$30358$new_n4749 +0110 1 +0111 1 +1001 1 +1011 1 +.names $abc$30358$new_n4751 ph[12][15] ph[12][16] ph[12][17] $abc$30358$new_n4750 +1000 1 +.names $abc$30358$new_n4752 ph[12][11] ph[12][12] ph[12][13] ph[12][14] $abc$30358$new_n4751 +10000 1 +.names $abc$30358$new_n4753 ph[12][7] ph[12][8] ph[12][9] ph[12][10] $abc$30358$new_n4752 +10000 1 +.names ph[12][6] ph[12][5] ph[12][3] ph[12][4] $abc$30358$new_n4753 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[12][15] ph[12][16] $abc$30358$new_n4757 $abc$30358$new_n4755 $abc$30358$new_n4754 +1111 1 +.names $abc$30358$new_n4756 ph[12][6] ph[12][5] ph[12][3] ph[12][4] $abc$30358$new_n4755 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[12][7] ph[12][8] ph[12][9] ph[12][14] ph[12][17] $abc$30358$new_n4756 +11111 1 +.names ph[12][10] ph[12][11] ph[12][12] ph[12][13] $abc$30358$new_n4757 +1111 1 +.names $abc$30358$new_n4759 ph[13][18] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27437 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[12][18] yv[12][20] $abc$30358$new_n4754 $abc$30358$new_n4750 $abc$30358$new_n4759 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4761 ph[13][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27439 +001 1 +011 1 +110 1 +111 1 +.names ph[12][17] ph[12][16] $abc$30358$new_n4767 ph[12][15] $abc$30358$new_n4762 $abc$30358$new_n4761 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names ph[12][15] $abc$30358$new_n4763 $abc$30358$new_n4762 +11 1 +.names ph[12][14] $abc$30358$new_n4757 $abc$30358$new_n4764 $abc$30358$new_n4763 +111 1 +.names ph[12][9] $abc$30358$new_n4765 $abc$30358$new_n4764 +11 1 +.names ph[12][7] ph[12][8] $abc$30358$new_n4766 $abc$30358$new_n4765 +111 1 +.names ph[12][6] yv[12][20] ph[12][5] ph[12][3] ph[12][4] $abc$30358$new_n4766 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$30358$new_n4768 ph[12][12] ph[12][13] ph[12][14] $abc$30358$new_n4767 +1000 1 +.names $abc$30358$new_n4769 ph[12][9] ph[12][10] ph[12][11] $abc$30358$new_n4768 +1000 1 +.names $abc$30358$new_n4770 ph[12][7] ph[12][8] $abc$30358$new_n4769 +100 1 +.names yv[12][20] $abc$30358$new_n4753 $abc$30358$new_n4770 +11 1 +.names i_ce $abc$30358$new_n4772 ph[13][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27441 +001 1 +011 1 +100 1 +101 1 +.names ph[12][16] $abc$30358$new_n4762 $abc$30358$new_n4767 ph[12][15] $abc$30358$new_n4772 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce ph[12][15] $abc$30358$new_n4763 $abc$30358$new_n4767 ph[13][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27443 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4775 ph[13][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27445 +001 1 +011 1 +110 1 +111 1 +.names ph[12][12] ph[12][14] ph[12][13] $abc$30358$new_n4768 $abc$30358$new_n4776 $abc$30358$new_n4775 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[12][10] ph[12][11] $abc$30358$new_n4764 $abc$30358$new_n4776 +111 1 +.names i_ce $abc$30358$new_n4778 ph[12][13] ph[13][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27447 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[12][12] $abc$30358$new_n4776 $abc$30358$new_n4768 $abc$30358$new_n4778 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[12][12] $abc$30358$new_n4768 $abc$30358$new_n4776 ph[13][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27449 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][11] $abc$30358$new_n4768 $abc$30358$new_n4781 $abc$30358$auto$rtlil.cc:2693:MuxGate$27451 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[12][10] ph[12][11] $abc$30358$new_n4764 $abc$30358$new_n4769 ph[12][9] $abc$30358$new_n4781 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4783 ph[12][10] ph[13][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27453 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[12][9] $abc$30358$new_n4769 $abc$30358$new_n4765 $abc$30358$new_n4783 +000 1 +001 1 +100 1 +110 1 +.names i_ce ph[12][9] $abc$30358$new_n4765 $abc$30358$new_n4769 ph[13][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27455 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4786 ph[13][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27457 +001 1 +011 1 +100 1 +101 1 +.names ph[12][7] ph[12][8] $abc$30358$new_n4766 $abc$30358$new_n4770 $abc$30358$new_n4786 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[12][7] $abc$30358$new_n4766 $abc$30358$new_n4770 ph[13][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27459 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4789 ph[13][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27461 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] ph[12][6] ph[12][5] ph[12][3] ph[12][4] $abc$30358$new_n4789 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n4791 ph[13][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27463 +001 1 +011 1 +110 1 +111 1 +.names ph[12][5] yv[12][20] ph[12][3] ph[12][4] $abc$30358$new_n4791 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[12][20] ph[12][3] ph[12][4] ph[13][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27465 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[12][3] ph[13][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27467 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[12][2] ph[13][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27469 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[12][1] ph[13][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27471 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[12][0] ph[13][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27473 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[12][20] yv[12][19] $abc$30358$new_n4798 yv[13][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27475 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] yv[12][18] xv[12][20] $abc$30358$new_n4813 $abc$30358$new_n4799 $abc$30358$new_n4798 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[12][20] $abc$30358$new_n6052 yv[12][16] yv[12][17] $abc$30358$new_n4799 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[12][20] yv[12][8] yv[12][9] $abc$30358$new_n4803 $abc$30358$new_n4802 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names yv[12][6] xv[12][19] xv[12][20] yv[12][7] $abc$30358$new_n4804 $abc$30358$new_n4803 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[12][18] yv[12][5] $abc$30358$new_n4805 $abc$30358$new_n4804 +001 1 +100 1 +101 1 +111 1 +.names xv[12][16] xv[12][17] yv[12][3] yv[12][4] $abc$30358$new_n4806 $abc$30358$new_n4805 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[12][15] yv[12][2] $abc$30358$new_n4807 $abc$30358$new_n4806 +001 1 +100 1 +101 1 +111 1 +.names xv[12][13] xv[12][14] yv[12][0] yv[12][1] $abc$30358$new_n4807 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[12][20] yv[12][13] $abc$30358$new_n4810 +01 1 +10 1 +.names xv[12][20] yv[12][15] $abc$30358$new_n4811 +01 1 +10 1 +.names xv[12][20] yv[12][14] $abc$30358$new_n4812 +01 1 +10 1 +.names xv[12][20] $abc$30358$new_n4814 yv[12][16] yv[12][17] $abc$30358$new_n4813 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][20] $abc$30358$new_n4822 $abc$30358$new_n4815 yv[12][12] $abc$30358$new_n4814 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names xv[12][20] yv[12][10] yv[12][11] $abc$30358$new_n4816 $abc$30358$new_n4821 $abc$30358$new_n4815 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[12][8] yv[12][9] xv[12][20] yv[12][7] $abc$30358$new_n4817 $abc$30358$new_n4816 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[12][18] yv[12][5] xv[12][19] yv[12][6] $abc$30358$new_n4818 $abc$30358$new_n4817 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[12][16] yv[12][3] xv[12][17] yv[12][4] $abc$30358$new_n4819 $abc$30358$new_n4818 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[12][15] yv[12][2] $abc$30358$new_n4820 $abc$30358$new_n4819 +000 1 +001 1 +011 1 +101 1 +.names xv[12][13] yv[12][0] xv[12][14] yv[12][1] $abc$30358$new_n4820 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[12][8] yv[12][9] $abc$30358$new_n4821 +00 1 +.names $abc$30358$new_n4812 $abc$30358$new_n4811 $abc$30358$new_n4810 $abc$30358$new_n4822 +111 1 +.names i_ce xv[12][20] yv[12][18] $abc$30358$new_n4824 yv[13][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27477 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] $abc$30358$new_n4799 $abc$30358$new_n4813 $abc$30358$new_n4824 +010 1 +011 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n4829 yv[13][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27481 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] xv[12][20] yv[12][16] $abc$30358$new_n4814 $abc$30358$new_n6052 $abc$30358$new_n4829 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4831 $abc$30358$new_n4811 yv[13][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27483 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[12][14] yv[12][20] $abc$30358$new_n4834 xv[12][20] $abc$30358$new_n4832 $abc$30358$new_n4831 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names xv[12][20] $abc$30358$new_n4833 yv[12][12] yv[12][13] $abc$30358$new_n4832 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[12][20] $abc$30358$new_n4802 yv[12][10] yv[12][11] $abc$30358$new_n4833 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][20] xv[12][20] yv[12][12] yv[12][13] $abc$30358$new_n4815 $abc$30358$new_n4834 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4836 yv[13][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27485 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n4812 $abc$30358$new_n4834 yv[12][20] $abc$30358$new_n4832 $abc$30358$new_n4836 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +.names i_ce $abc$30358$new_n4838 $abc$30358$new_n4810 yv[13][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27487 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[12][20] yv[12][12] xv[12][20] $abc$30358$new_n4815 $abc$30358$new_n4833 $abc$30358$new_n4838 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4840 yv[13][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27489 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] xv[12][20] yv[12][12] $abc$30358$new_n4815 $abc$30358$new_n4833 $abc$30358$new_n4840 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[12][20] yv[12][11] $abc$30358$new_n4842 yv[13][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27491 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] yv[12][10] xv[12][20] $abc$30358$new_n4843 $abc$30358$new_n4802 $abc$30358$new_n4842 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$30358$new_n4816 $abc$30358$new_n4821 xv[12][20] $abc$30358$new_n4843 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n4845 yv[13][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27493 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] xv[12][20] yv[12][10] $abc$30358$new_n4843 $abc$30358$new_n4802 $abc$30358$new_n4845 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[12][20] yv[12][9] $abc$30358$new_n4847 yv[13][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27495 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] yv[12][8] xv[12][20] $abc$30358$new_n4803 $abc$30358$new_n4848 $abc$30358$new_n4847 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[12][20] yv[12][7] $abc$30358$new_n4817 $abc$30358$new_n4848 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n4850 yv[13][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27497 +001 1 +011 1 +110 1 +111 1 +.names xv[12][20] yv[12][8] yv[12][20] $abc$30358$new_n4803 $abc$30358$new_n4848 $abc$30358$new_n4850 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[12][20] yv[12][7] $abc$30358$new_n4852 yv[13][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27499 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] yv[12][6] xv[12][19] $abc$30358$new_n4804 $abc$30358$new_n4817 $abc$30358$new_n4852 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[12][19] yv[12][6] $abc$30358$new_n4854 yv[13][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27501 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][18] yv[12][5] $abc$30358$new_n4805 $abc$30358$new_n4818 $abc$30358$new_n4854 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4856 yv[13][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27503 +001 1 +011 1 +110 1 +111 1 +.names xv[12][18] yv[12][5] yv[12][20] $abc$30358$new_n4805 $abc$30358$new_n4818 $abc$30358$new_n4856 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[12][17] yv[12][4] $abc$30358$new_n4858 yv[13][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27505 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][16] yv[12][3] $abc$30358$new_n4806 $abc$30358$new_n4819 $abc$30358$new_n4858 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[12][16] yv[12][3] $abc$30358$new_n4860 yv[13][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27507 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] $abc$30358$new_n4819 $abc$30358$new_n4806 $abc$30358$new_n4860 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[12][15] yv[12][2] $abc$30358$new_n4862 yv[13][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27509 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] $abc$30358$new_n4820 $abc$30358$new_n4807 $abc$30358$new_n4862 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4864 yv[13][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27511 +001 1 +011 1 +110 1 +111 1 +.names xv[12][14] yv[12][1] yv[12][20] yv[12][0] xv[12][13] $abc$30358$new_n4864 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[12][13] yv[12][0] yv[13][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27513 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[12][19] $abc$30358$new_n4867 xv[13][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27515 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[12][18] yv[12][20] $abc$30358$new_n4878 $abc$30358$new_n4889 $abc$30358$new_n4869 $abc$30358$new_n4867 +10011 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4870 xv[12][14] xv[12][15] $abc$30358$new_n4869 +111 1 +.names yv[12][20] xv[12][12] xv[12][13] $abc$30358$new_n4871 $abc$30358$new_n4870 +0110 1 +1000 1 +.names yv[12][20] $abc$30358$new_n4872 xv[12][10] xv[12][11] $abc$30358$new_n4871 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[12][20] $abc$30358$new_n4873 xv[12][7] xv[12][8] xv[12][9] $abc$30358$new_n4872 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[12][5] yv[12][18] xv[12][6] yv[12][19] $abc$30358$new_n4874 $abc$30358$new_n4873 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[12][3] yv[12][16] xv[12][4] yv[12][17] $abc$30358$new_n4875 $abc$30358$new_n4874 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[12][2] yv[12][15] $abc$30358$new_n4876 $abc$30358$new_n4875 +000 1 +001 1 +011 1 +101 1 +.names xv[12][0] yv[12][13] xv[12][1] yv[12][14] $abc$30358$new_n4876 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[12][16] xv[12][17] $abc$30358$new_n4879 $abc$30358$new_n4878 +111 1 +.names $abc$30358$new_n4888 $abc$30358$new_n6056 $abc$30358$new_n4879 +10 1 +.names yv[12][20] xv[12][8] xv[12][7] $abc$30358$new_n4883 $abc$30358$new_n4882 +0000 1 +0010 1 +0011 1 +1110 1 +.names yv[12][19] xv[12][6] $abc$30358$new_n4884 $abc$30358$new_n4883 +001 1 +100 1 +101 1 +111 1 +.names yv[12][17] xv[12][4] xv[12][5] yv[12][18] $abc$30358$new_n4885 $abc$30358$new_n4884 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[12][15] xv[12][2] xv[12][3] yv[12][16] $abc$30358$new_n4886 $abc$30358$new_n4885 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[12][13] xv[12][0] xv[12][1] yv[12][14] $abc$30358$new_n4886 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[12][20] xv[12][12] xv[12][13] xv[12][14] xv[12][15] $abc$30358$new_n4888 +00000 1 +11111 1 +.names yv[12][20] xv[12][16] xv[12][17] $abc$30358$new_n4889 +011 1 +100 1 +.names i_ce xv[12][17] $abc$30358$new_n4894 xv[13][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27519 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[12][16] yv[12][20] $abc$30358$new_n4869 $abc$30358$new_n4879 $abc$30358$new_n4894 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$30358$new_n4896 i_ce xv[13][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27521 +001 1 +010 1 +011 1 +.names i_ce yv[12][20] xv[12][16] $abc$30358$new_n4879 $abc$30358$new_n4869 $abc$30358$new_n4896 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4898 xv[13][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27523 +001 1 +011 1 +110 1 +111 1 +.names xv[12][15] yv[12][20] xv[12][14] $abc$30358$new_n4870 $abc$30358$new_n4899 $abc$30358$new_n4898 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[12][13] xv[12][12] $abc$30358$new_n6056 $abc$30358$new_n4899 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$30358$new_n4901 i_ce xv[13][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27525 +001 1 +010 1 +011 1 +.names i_ce xv[12][14] yv[12][20] $abc$30358$new_n4870 $abc$30358$new_n4899 $abc$30358$new_n4901 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4903 xv[13][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27527 +001 1 +011 1 +110 1 +111 1 +.names xv[12][13] xv[12][12] $abc$30358$new_n4871 $abc$30358$new_n6056 $abc$30358$new_n4903 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[12][11] xv[12][10] $abc$30358$new_n4907 xv[13][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27531 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[12][9] $abc$30358$new_n4908 $abc$30358$new_n4882 yv[12][20] $abc$30358$new_n4907 +1000 1 +1010 1 +1011 1 +.names yv[12][20] xv[12][8] xv[12][7] $abc$30358$new_n4873 $abc$30358$new_n4908 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names i_ce xv[12][10] $abc$30358$new_n4907 xv[13][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27533 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4911 xv[13][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27535 +001 1 +011 1 +110 1 +111 1 +.names xv[12][9] $abc$30358$new_n4908 yv[12][20] $abc$30358$new_n4882 $abc$30358$new_n4911 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4916 xv[13][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27539 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] xv[12][7] $abc$30358$new_n4883 $abc$30358$new_n4873 $abc$30358$new_n4916 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[12][6] yv[12][19] $abc$30358$new_n4918 xv[13][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27541 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][5] yv[12][18] $abc$30358$new_n4874 $abc$30358$new_n4884 $abc$30358$new_n4918 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[12][5] yv[12][18] $abc$30358$new_n4920 xv[13][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27543 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] yv[12][17] xv[12][4] $abc$30358$new_n4885 $abc$30358$new_n4874 $abc$30358$new_n4920 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[12][4] yv[12][17] $abc$30358$new_n4922 xv[13][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27545 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][3] yv[12][16] $abc$30358$new_n4875 $abc$30358$new_n4885 $abc$30358$new_n4922 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[12][3] yv[12][16] $abc$30358$new_n4924 xv[13][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27547 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] xv[12][2] yv[12][15] $abc$30358$new_n4886 $abc$30358$new_n4876 $abc$30358$new_n4924 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[12][2] yv[12][15] $abc$30358$new_n4926 xv[13][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27549 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] $abc$30358$new_n4876 $abc$30358$new_n4886 $abc$30358$new_n4926 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4928 xv[13][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27551 +001 1 +011 1 +110 1 +111 1 +.names xv[12][1] yv[12][14] yv[12][20] xv[12][0] yv[12][13] $abc$30358$new_n4928 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[12][0] yv[12][13] xv[13][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27553 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4931 ph[13][19] ph[14][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27555 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[13][18] $abc$30358$new_n4932 $abc$30358$new_n4938 $abc$30358$new_n4931 +000 1 +001 1 +100 1 +110 1 +.names $abc$30358$new_n4933 ph[13][17] $abc$30358$new_n4932 +10 1 +.names $abc$30358$new_n4937 $abc$30358$new_n4934 ph[13][13] ph[13][16] $abc$30358$new_n4933 +1100 1 +.names $abc$30358$new_n4952 ph[13][14] ph[13][15] $abc$30358$new_n4934 +100 1 +.names ph[13][5] ph[13][4] ph[13][2] ph[13][3] $abc$30358$new_n4935 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[13][9] ph[13][10] ph[13][11] ph[13][12] $abc$30358$new_n4937 +0000 1 +.names ph[13][17] $abc$30358$new_n4939 $abc$30358$new_n4938 +11 1 +.names $abc$30358$new_n4956 ph[13][13] ph[13][16] $abc$30358$new_n4940 $abc$30358$new_n4939 +1111 1 +.names $abc$30358$new_n4958 ph[13][14] ph[13][15] $abc$30358$new_n4940 +111 1 +.names ph[13][5] ph[13][4] ph[13][2] ph[13][3] $abc$30358$new_n4941 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce ph[13][18] $abc$30358$new_n4938 $abc$30358$new_n4932 ph[14][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27557 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][17] $abc$30358$new_n4939 $abc$30358$new_n4933 ph[14][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27559 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4947 ph[14][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27561 +001 1 +011 1 +110 1 +111 1 +.names ph[13][14] ph[13][16] ph[13][15] $abc$30358$new_n4955 $abc$30358$new_n4948 $abc$30358$new_n4947 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4949 ph[13][13] $abc$30358$new_n4948 +10 1 +.names $abc$30358$new_n4950 ph[13][11] ph[13][12] $abc$30358$new_n4949 +100 1 +.names $abc$30358$new_n4951 ph[13][10] $abc$30358$new_n4950 +10 1 +.names $abc$30358$new_n4952 ph[13][9] $abc$30358$new_n4951 +10 1 +.names $abc$30358$new_n4953 ph[13][8] $abc$30358$new_n4952 +10 1 +.names $abc$30358$new_n4954 ph[13][6] ph[13][7] $abc$30358$new_n4953 +100 1 +.names yv[13][20] $abc$30358$new_n4935 $abc$30358$new_n4954 +11 1 +.names ph[13][13] $abc$30358$new_n4956 $abc$30358$new_n4955 +11 1 +.names ph[13][10] ph[13][11] ph[13][12] $abc$30358$new_n4957 $abc$30358$new_n4956 +1111 1 +.names ph[13][9] $abc$30358$new_n4958 $abc$30358$new_n4957 +11 1 +.names ph[13][8] $abc$30358$new_n4959 $abc$30358$new_n4958 +11 1 +.names ph[13][6] ph[13][7] $abc$30358$new_n4960 $abc$30358$new_n4959 +111 1 +.names $abc$30358$new_n4941 yv[13][20] $abc$30358$new_n4960 +10 1 +.names i_ce $abc$30358$new_n4962 ph[14][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27563 +001 1 +011 1 +110 1 +111 1 +.names ph[13][14] ph[13][15] $abc$30358$new_n4955 $abc$30358$new_n4948 $abc$30358$new_n4962 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[13][14] $abc$30358$new_n4955 $abc$30358$new_n4948 ph[14][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27565 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][13] $abc$30358$new_n4956 $abc$30358$new_n4949 ph[14][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27567 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n4966 i_ce ph[14][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27569 +001 1 +010 1 +011 1 +.names i_ce ph[13][11] ph[13][12] $abc$30358$new_n4967 $abc$30358$new_n4950 $abc$30358$new_n4966 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][10] $abc$30358$new_n4957 $abc$30358$new_n4967 +11 1 +.names i_ce ph[13][11] $abc$30358$new_n4967 $abc$30358$new_n4950 ph[14][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27571 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][10] $abc$30358$new_n4951 $abc$30358$new_n4957 ph[14][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27573 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][9] $abc$30358$new_n4952 $abc$30358$new_n4958 ph[14][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27575 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][8] $abc$30358$new_n4953 $abc$30358$new_n4959 ph[14][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27577 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4973 ph[14][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27579 +001 1 +011 1 +100 1 +101 1 +.names ph[13][7] ph[13][6] $abc$30358$new_n4954 $abc$30358$new_n4960 $abc$30358$new_n4973 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[13][6] $abc$30358$new_n4954 $abc$30358$new_n4960 ph[14][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27581 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4976 ph[14][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27583 +001 1 +011 1 +100 1 +101 1 +.names yv[13][20] ph[13][5] ph[13][4] ph[13][2] ph[13][3] $abc$30358$new_n4976 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n4978 ph[14][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27585 +001 1 +011 1 +110 1 +111 1 +.names ph[13][4] yv[13][20] ph[13][2] ph[13][3] $abc$30358$new_n4978 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[13][20] ph[13][2] ph[13][3] ph[14][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27587 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[13][2] ph[14][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27589 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[13][1] ph[14][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27591 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[13][0] ph[14][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27593 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[13][20] yv[13][19] $abc$30358$new_n4984 yv[14][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27595 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][18] xv[13][20] $abc$30358$new_n4996 $abc$30358$new_n4985 $abc$30358$new_n4984 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[13][20] $abc$30358$new_n6063 yv[13][16] yv[13][17] $abc$30358$new_n4985 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][20] yv[13][10] yv[13][11] $abc$30358$new_n4989 $abc$30358$new_n4994 $abc$30358$new_n4988 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[13][20] yv[13][8] yv[13][9] $abc$30358$new_n4990 $abc$30358$new_n4989 +0110 1 +1000 1 +.names xv[13][20] $abc$30358$new_n4991 yv[13][6] yv[13][7] $abc$30358$new_n4990 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][18] yv[13][4] xv[13][19] yv[13][5] $abc$30358$new_n4992 $abc$30358$new_n4991 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[13][16] yv[13][2] xv[13][17] yv[13][3] $abc$30358$new_n4993 $abc$30358$new_n4992 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[13][14] yv[13][0] xv[13][15] yv[13][1] $abc$30358$new_n4993 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[13][8] yv[13][9] $abc$30358$new_n4994 +00 1 +.names xv[13][20] $abc$30358$new_n4997 yv[13][16] yv[13][17] $abc$30358$new_n4996 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][20] yv[13][14] yv[13][15] $abc$30358$new_n4998 $abc$30358$new_n5005 $abc$30358$new_n4997 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[13][20] yv[13][12] yv[13][13] $abc$30358$new_n4999 $abc$30358$new_n4998 +0000 1 +1110 1 +.names xv[13][20] $abc$30358$new_n5000 yv[13][10] yv[13][11] $abc$30358$new_n4999 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][20] $abc$30358$new_n5001 yv[13][8] yv[13][9] $abc$30358$new_n5000 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][20] $abc$30358$new_n5002 yv[13][6] yv[13][7] $abc$30358$new_n5001 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][18] xv[13][19] yv[13][4] yv[13][5] $abc$30358$new_n5003 $abc$30358$new_n5002 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[13][16] xv[13][17] yv[13][2] yv[13][3] $abc$30358$new_n5004 $abc$30358$new_n5003 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[13][14] xv[13][15] yv[13][0] yv[13][1] $abc$30358$new_n5004 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names yv[13][12] yv[13][13] $abc$30358$new_n5005 +00 1 +.names i_ce xv[13][20] yv[13][18] $abc$30358$new_n5007 yv[14][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27597 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][20] $abc$30358$new_n4985 $abc$30358$new_n4996 $abc$30358$new_n5007 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[13][20] yv[13][17] $abc$30358$new_n5009 yv[14][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27599 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][16] xv[13][20] $abc$30358$new_n4997 $abc$30358$new_n6063 $abc$30358$new_n5009 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5011 yv[14][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27601 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][16] yv[13][20] $abc$30358$new_n4997 $abc$30358$new_n6063 $abc$30358$new_n5011 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][20] yv[13][15] $abc$30358$new_n5013 yv[14][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27603 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][14] yv[13][20] $abc$30358$new_n5015 xv[13][20] $abc$30358$new_n5014 $abc$30358$new_n5013 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names $abc$30358$new_n4998 $abc$30358$new_n5005 xv[13][20] $abc$30358$new_n5014 +001 1 +010 1 +011 1 +.names yv[13][20] xv[13][20] yv[13][12] yv[13][13] $abc$30358$new_n4988 $abc$30358$new_n5015 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[13][20] yv[13][14] $abc$30358$new_n5017 yv[14][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27605 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5015 $abc$30358$new_n5014 yv[13][20] $abc$30358$new_n5017 +000 1 +001 1 +011 1 +.names i_ce xv[13][20] yv[13][13] $abc$30358$new_n5019 yv[14][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27607 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][12] xv[13][20] $abc$30358$new_n4999 $abc$30358$new_n4988 $abc$30358$new_n5019 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5021 yv[14][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27609 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][12] yv[13][20] $abc$30358$new_n4999 $abc$30358$new_n4988 $abc$30358$new_n5021 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][20] yv[13][11] $abc$30358$new_n5023 yv[14][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27611 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][10] xv[13][20] $abc$30358$new_n5000 $abc$30358$new_n5024 $abc$30358$new_n5023 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n4989 $abc$30358$new_n4994 xv[13][20] $abc$30358$new_n5024 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5026 yv[14][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27613 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][10] yv[13][20] $abc$30358$new_n5000 $abc$30358$new_n5024 $abc$30358$new_n5026 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][20] yv[13][9] $abc$30358$new_n5028 yv[14][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27615 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][8] xv[13][20] $abc$30358$new_n5001 $abc$30358$new_n4990 $abc$30358$new_n5028 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5030 yv[14][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27617 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][8] yv[13][20] $abc$30358$new_n5001 $abc$30358$new_n4990 $abc$30358$new_n5030 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][20] yv[13][7] $abc$30358$new_n5032 yv[14][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27619 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][6] xv[13][20] $abc$30358$new_n5002 $abc$30358$new_n4991 $abc$30358$new_n5032 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5034 yv[14][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27621 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][6] yv[13][20] $abc$30358$new_n5002 $abc$30358$new_n4991 $abc$30358$new_n5034 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][19] yv[13][5] $abc$30358$new_n5036 yv[14][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27623 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][4] xv[13][18] $abc$30358$new_n5003 $abc$30358$new_n4992 $abc$30358$new_n5036 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5038 yv[14][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27625 +001 1 +011 1 +110 1 +111 1 +.names xv[13][18] yv[13][4] yv[13][20] $abc$30358$new_n5003 $abc$30358$new_n4992 $abc$30358$new_n5038 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[13][17] yv[13][3] $abc$30358$new_n5040 yv[14][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27627 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][2] xv[13][16] $abc$30358$new_n5004 $abc$30358$new_n4993 $abc$30358$new_n5040 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[13][16] yv[13][2] $abc$30358$new_n5042 yv[14][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27629 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] $abc$30358$new_n4993 $abc$30358$new_n5004 $abc$30358$new_n5042 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5044 yv[14][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27631 +001 1 +011 1 +110 1 +111 1 +.names xv[13][15] yv[13][1] yv[13][20] yv[13][0] xv[13][14] $abc$30358$new_n5044 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[13][14] yv[13][0] yv[14][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27633 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[13][19] $abc$30358$new_n5060 $abc$30358$new_n5047 xv[14][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27635 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[13][20] $abc$30358$new_n5048 $abc$30358$new_n5047 +10 1 +.names xv[13][18] $abc$30358$new_n5049 $abc$30358$new_n5048 +10 1 +.names xv[13][16] xv[13][17] $abc$30358$new_n5050 $abc$30358$new_n5049 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n5058 $abc$30358$new_n6065 $abc$30358$new_n5050 +10 1 +.names yv[13][20] xv[13][8] xv[13][6] xv[13][7] $abc$30358$new_n5054 $abc$30358$new_n5053 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +11110 1 +.names yv[13][18] xv[13][4] xv[13][5] yv[13][19] $abc$30358$new_n5055 $abc$30358$new_n5054 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[13][16] xv[13][2] xv[13][3] yv[13][17] $abc$30358$new_n5056 $abc$30358$new_n5055 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[13][14] xv[13][0] xv[13][1] yv[13][15] $abc$30358$new_n5056 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[13][20] xv[13][12] xv[13][13] xv[13][14] xv[13][15] $abc$30358$new_n5058 +00000 1 +11111 1 +.names yv[13][20] xv[13][17] xv[13][18] $abc$30358$new_n6067 $abc$30358$new_n5060 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$30358$new_n5064 yv[13][20] xv[13][9] xv[13][10] xv[13][11] $abc$30358$new_n5063 +10111 1 +11000 1 +.names xv[13][8] yv[13][20] xv[13][6] xv[13][7] $abc$30358$new_n5065 $abc$30358$new_n5064 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[13][5] yv[13][19] $abc$30358$new_n5066 $abc$30358$new_n5065 +000 1 +001 1 +011 1 +101 1 +.names xv[13][3] yv[13][17] xv[13][4] yv[13][18] $abc$30358$new_n5067 $abc$30358$new_n5066 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[13][2] yv[13][16] $abc$30358$new_n5068 $abc$30358$new_n5067 +000 1 +001 1 +011 1 +101 1 +.names xv[13][0] yv[13][14] xv[13][1] yv[13][15] $abc$30358$new_n5068 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[13][20] xv[13][12] xv[13][13] $abc$30358$new_n5070 +011 1 +100 1 +.names i_ce xv[13][17] xv[13][16] $abc$30358$new_n5075 xv[14][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27639 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[13][15] $abc$30358$new_n5076 $abc$30358$new_n5075 +00 1 +01 1 +10 1 +.names $abc$30358$new_n5077 yv[13][20] $abc$30358$new_n5063 $abc$30358$new_n5076 +001 1 +010 1 +011 1 +.names xv[13][14] xv[13][12] xv[13][13] $abc$30358$new_n6065 $abc$30358$new_n5077 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n5075 xv[13][16] xv[14][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27641 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[13][15] $abc$30358$new_n5076 xv[14][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27643 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5084 xv[14][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27647 +001 1 +011 1 +110 1 +111 1 +.names xv[13][13] yv[13][20] xv[13][12] $abc$30358$new_n6065 $abc$30358$new_n5063 $abc$30358$new_n5084 +00101 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n5086 i_ce xv[14][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27649 +001 1 +010 1 +011 1 +.names i_ce yv[13][20] xv[13][12] $abc$30358$new_n6065 $abc$30358$new_n5063 $abc$30358$new_n5086 +10000 1 +10010 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][11] xv[13][10] $abc$30358$new_n5088 xv[14][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27651 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[13][9] yv[13][20] $abc$30358$new_n5064 $abc$30358$new_n5053 $abc$30358$new_n5088 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce xv[13][10] $abc$30358$new_n5088 xv[14][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27653 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5091 xv[14][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27655 +001 1 +011 1 +110 1 +111 1 +.names yv[13][20] xv[13][9] $abc$30358$new_n5053 $abc$30358$new_n5064 $abc$30358$new_n5091 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5096 xv[14][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27659 +001 1 +011 1 +110 1 +111 1 +.names xv[13][7] yv[13][20] xv[13][6] $abc$30358$new_n5054 $abc$30358$new_n5065 $abc$30358$new_n5096 +00100 1 +00110 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n5098 i_ce xv[14][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27661 +001 1 +010 1 +011 1 +.names i_ce yv[13][20] xv[13][6] $abc$30358$new_n5054 $abc$30358$new_n5065 $abc$30358$new_n5098 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][5] yv[13][19] $abc$30358$new_n5100 xv[14][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27663 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][20] yv[13][18] xv[13][4] $abc$30358$new_n5055 $abc$30358$new_n5066 $abc$30358$new_n5100 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[13][4] yv[13][18] $abc$30358$new_n5102 xv[14][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27665 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][20] xv[13][3] yv[13][17] $abc$30358$new_n5067 $abc$30358$new_n5055 $abc$30358$new_n5102 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[13][3] yv[13][17] $abc$30358$new_n5104 xv[14][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27667 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] xv[13][2] yv[13][16] $abc$30358$new_n5056 $abc$30358$new_n5068 $abc$30358$new_n5104 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[13][2] yv[13][16] $abc$30358$new_n5106 xv[14][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27669 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][20] $abc$30358$new_n5068 $abc$30358$new_n5056 $abc$30358$new_n5106 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n5108 xv[14][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27671 +001 1 +011 1 +110 1 +111 1 +.names xv[13][1] yv[13][15] yv[13][20] xv[13][0] yv[13][14] $abc$30358$new_n5108 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[13][0] yv[13][14] xv[14][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27673 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[14][19] $abc$30358$new_n5111 ph[15][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27675 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[14][17] ph[14][18] yv[14][20] $abc$30358$new_n5112 $abc$30358$new_n5117 $abc$30358$new_n5111 +00110 1 +00111 1 +11001 1 +11011 1 +.names $abc$30358$new_n5113 ph[14][16] $abc$30358$new_n5112 +10 1 +.names $abc$30358$new_n5114 ph[14][13] ph[14][14] ph[14][15] $abc$30358$new_n5113 +1000 1 +.names $abc$30358$new_n5115 ph[14][9] ph[14][10] ph[14][11] ph[14][12] $abc$30358$new_n5114 +10000 1 +.names $abc$30358$new_n5116 ph[14][5] ph[14][6] ph[14][7] ph[14][8] $abc$30358$new_n5115 +10000 1 +.names ph[14][4] ph[14][3] ph[14][1] ph[14][2] $abc$30358$new_n5116 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[14][16] $abc$30358$new_n5118 $abc$30358$new_n5117 +11 1 +.names ph[14][13] ph[14][14] ph[14][15] $abc$30358$new_n5119 $abc$30358$new_n5118 +1111 1 +.names ph[14][9] ph[14][10] ph[14][11] ph[14][12] $abc$30358$new_n5120 $abc$30358$new_n5119 +11111 1 +.names ph[14][5] ph[14][6] ph[14][7] ph[14][8] $abc$30358$new_n5121 $abc$30358$new_n5120 +11111 1 +.names ph[14][4] ph[14][3] ph[14][1] ph[14][2] $abc$30358$new_n5121 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n5123 ph[15][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27677 +001 1 +011 1 +110 1 +111 1 +.names yv[14][20] ph[14][18] ph[14][17] $abc$30358$new_n5117 $abc$30358$new_n5112 $abc$30358$new_n5123 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5125 ph[15][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27679 +001 1 +011 1 +110 1 +111 1 +.names ph[14][17] yv[14][20] $abc$30358$new_n5117 $abc$30358$new_n5112 $abc$30358$new_n5125 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n5127 ph[15][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27681 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[14][16] yv[14][20] $abc$30358$new_n5118 $abc$30358$new_n5113 $abc$30358$new_n5127 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n5129 ph[15][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27683 +001 1 +011 1 +110 1 +111 1 +.names ph[14][13] ph[14][15] ph[14][14] $abc$30358$new_n5136 $abc$30358$new_n5130 $abc$30358$new_n5129 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[14][11] ph[14][12] $abc$30358$new_n5131 $abc$30358$new_n5130 +111 1 +.names ph[14][9] ph[14][10] $abc$30358$new_n5132 $abc$30358$new_n5131 +111 1 +.names ph[14][8] $abc$30358$new_n5133 $abc$30358$new_n5132 +11 1 +.names ph[14][7] $abc$30358$new_n5134 $abc$30358$new_n5133 +11 1 +.names ph[14][5] ph[14][6] $abc$30358$new_n5135 $abc$30358$new_n5134 +111 1 +.names $abc$30358$new_n5121 yv[14][20] $abc$30358$new_n5135 +10 1 +.names $abc$30358$new_n5137 ph[14][11] ph[14][12] $abc$30358$new_n5136 +100 1 +.names $abc$30358$new_n5138 ph[14][9] ph[14][10] $abc$30358$new_n5137 +100 1 +.names $abc$30358$new_n5139 ph[14][8] $abc$30358$new_n5138 +10 1 +.names $abc$30358$new_n5140 ph[14][7] $abc$30358$new_n5139 +10 1 +.names $abc$30358$new_n5141 ph[14][5] ph[14][6] $abc$30358$new_n5140 +100 1 +.names yv[14][20] $abc$30358$new_n5116 $abc$30358$new_n5141 +11 1 +.names i_ce $abc$30358$new_n5143 ph[15][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27685 +001 1 +011 1 +110 1 +111 1 +.names ph[14][14] ph[14][13] $abc$30358$new_n5136 $abc$30358$new_n5130 $abc$30358$new_n5143 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[14][13] $abc$30358$new_n5136 $abc$30358$new_n5130 ph[15][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27687 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5146 ph[14][12] ph[15][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27689 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[14][11] $abc$30358$new_n5131 $abc$30358$new_n5137 $abc$30358$new_n5146 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[14][11] $abc$30358$new_n5137 $abc$30358$new_n5131 ph[15][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27691 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5149 i_ce ph[15][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27693 +001 1 +010 1 +011 1 +.names i_ce ph[14][10] ph[14][9] $abc$30358$new_n5138 $abc$30358$new_n5132 $abc$30358$new_n5149 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce ph[14][9] $abc$30358$new_n5138 $abc$30358$new_n5132 ph[15][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27695 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[14][8] $abc$30358$new_n5139 $abc$30358$new_n5133 ph[15][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27697 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[14][7] $abc$30358$new_n5140 $abc$30358$new_n5134 ph[15][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27699 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5154 ph[15][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27701 +001 1 +011 1 +100 1 +101 1 +.names ph[14][6] ph[14][5] $abc$30358$new_n5141 $abc$30358$new_n5135 $abc$30358$new_n5154 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[14][5] $abc$30358$new_n5141 $abc$30358$new_n5135 ph[15][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27703 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5157 ph[15][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27705 +001 1 +011 1 +100 1 +101 1 +.names yv[14][20] ph[14][4] ph[14][3] ph[14][1] ph[14][2] $abc$30358$new_n5157 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n5159 ph[15][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27707 +001 1 +011 1 +110 1 +111 1 +.names ph[14][3] yv[14][20] ph[14][1] ph[14][2] $abc$30358$new_n5159 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[14][20] ph[14][1] ph[14][2] ph[15][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27709 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[14][1] ph[15][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27711 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[14][0] ph[15][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27713 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[14][20] yv[14][19] $abc$30358$new_n5164 yv[15][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27715 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][18] xv[14][20] $abc$30358$new_n5177 $abc$30358$new_n5165 $abc$30358$new_n5164 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[14][20] $abc$30358$new_n5166 yv[14][16] yv[14][17] $abc$30358$new_n5165 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n5176 $abc$30358$new_n5167 xv[14][20] $abc$30358$new_n5166 +001 1 +011 1 +110 1 +111 1 +.names xv[14][20] yv[14][10] yv[14][11] $abc$30358$new_n5168 $abc$30358$new_n5174 $abc$30358$new_n5167 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[14][20] yv[14][8] yv[14][9] $abc$30358$new_n5169 $abc$30358$new_n5168 +0000 1 +1110 1 +.names xv[14][20] $abc$30358$new_n5170 yv[14][6] yv[14][7] $abc$30358$new_n5169 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[14][20] yv[14][5] $abc$30358$new_n5171 $abc$30358$new_n5170 +001 1 +100 1 +101 1 +111 1 +.names xv[14][19] yv[14][4] $abc$30358$new_n5172 $abc$30358$new_n5171 +001 1 +100 1 +101 1 +111 1 +.names xv[14][17] xv[14][18] yv[14][2] yv[14][3] $abc$30358$new_n5173 $abc$30358$new_n5172 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[14][15] xv[14][16] yv[14][0] yv[14][1] $abc$30358$new_n5173 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names yv[14][8] yv[14][9] $abc$30358$new_n5174 +00 1 +.names xv[14][20] yv[14][12] yv[14][13] yv[14][14] yv[14][15] $abc$30358$new_n5176 +00000 1 +11111 1 +.names xv[14][20] $abc$30358$new_n5178 yv[14][16] yv[14][17] $abc$30358$new_n5177 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$30358$new_n5185 $abc$30358$new_n5179 xv[14][20] $abc$30358$new_n5178 +000 1 +010 1 +110 1 +111 1 +.names xv[14][20] yv[14][10] yv[14][11] $abc$30358$new_n5180 $abc$30358$new_n5174 $abc$30358$new_n5179 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[14][20] yv[14][8] yv[14][9] $abc$30358$new_n5181 $abc$30358$new_n5180 +0110 1 +1000 1 +.names xv[14][20] $abc$30358$new_n5182 yv[14][5] yv[14][6] yv[14][7] $abc$30358$new_n5181 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[14][19] yv[14][4] $abc$30358$new_n5183 $abc$30358$new_n5182 +000 1 +001 1 +011 1 +101 1 +.names xv[14][17] yv[14][2] xv[14][18] yv[14][3] $abc$30358$new_n5184 $abc$30358$new_n5183 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[14][15] yv[14][0] xv[14][16] yv[14][1] $abc$30358$new_n5184 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[14][20] yv[14][12] yv[14][13] yv[14][14] yv[14][15] $abc$30358$new_n5185 +01111 1 +10000 1 +.names i_ce xv[14][20] yv[14][18] $abc$30358$new_n5187 yv[15][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27717 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] $abc$30358$new_n5165 $abc$30358$new_n5177 $abc$30358$new_n5187 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[14][20] yv[14][17] $abc$30358$new_n5189 yv[15][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27719 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] xv[14][20] yv[14][16] $abc$30358$new_n5178 $abc$30358$new_n5166 $abc$30358$new_n5189 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5191 yv[15][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27721 +001 1 +011 1 +100 1 +101 1 +.names yv[14][20] xv[14][20] yv[14][16] $abc$30358$new_n5178 $abc$30358$new_n5166 $abc$30358$new_n5191 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[14][20] yv[14][15] $abc$30358$new_n5193 yv[15][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27723 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][14] xv[14][20] $abc$30358$new_n5195 $abc$30358$new_n5194 $abc$30358$new_n5193 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names xv[14][20] $abc$30358$new_n5167 yv[14][12] yv[14][13] $abc$30358$new_n5194 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[14][20] yv[14][12] yv[14][13] $abc$30358$new_n5179 $abc$30358$new_n5195 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[14][20] yv[14][14] $abc$30358$new_n5197 yv[15][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27725 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] $abc$30358$new_n5194 $abc$30358$new_n5195 $abc$30358$new_n5197 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[14][20] yv[14][13] $abc$30358$new_n5199 yv[15][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27727 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] xv[14][20] yv[14][12] $abc$30358$new_n5179 $abc$30358$new_n5167 $abc$30358$new_n5199 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5201 yv[15][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27729 +001 1 +011 1 +100 1 +101 1 +.names yv[14][20] xv[14][20] yv[14][12] $abc$30358$new_n5179 $abc$30358$new_n5167 $abc$30358$new_n5201 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[14][20] yv[14][11] $abc$30358$new_n5203 yv[15][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27731 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][10] xv[14][20] $abc$30358$new_n5205 $abc$30358$new_n5204 $abc$30358$new_n5203 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$30358$new_n5168 $abc$30358$new_n5174 xv[14][20] $abc$30358$new_n5204 +001 1 +010 1 +011 1 +.names $abc$30358$new_n5180 $abc$30358$new_n5174 xv[14][20] $abc$30358$new_n5205 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5207 yv[15][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27733 +001 1 +011 1 +110 1 +111 1 +.names yv[14][20] xv[14][20] yv[14][10] $abc$30358$new_n5205 $abc$30358$new_n5204 $abc$30358$new_n5207 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[14][20] yv[14][9] $abc$30358$new_n5209 yv[15][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27735 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][8] xv[14][20] $abc$30358$new_n5181 $abc$30358$new_n5169 $abc$30358$new_n5209 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n5211 yv[15][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27737 +001 1 +011 1 +110 1 +111 1 +.names yv[14][20] xv[14][20] yv[14][8] $abc$30358$new_n5181 $abc$30358$new_n5169 $abc$30358$new_n5211 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[14][20] yv[14][7] $abc$30358$new_n5213 yv[15][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27739 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][6] xv[14][20] $abc$30358$new_n5170 $abc$30358$new_n5214 $abc$30358$new_n5213 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[14][20] yv[14][5] $abc$30358$new_n5182 $abc$30358$new_n5214 +000 1 +001 1 +011 1 +101 1 +.names i_ce xv[14][20] yv[14][6] $abc$30358$new_n5216 yv[15][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27741 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] $abc$30358$new_n5214 $abc$30358$new_n5170 $abc$30358$new_n5216 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[14][20] yv[14][5] $abc$30358$new_n5218 yv[15][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27743 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] $abc$30358$new_n5182 $abc$30358$new_n5171 $abc$30358$new_n5218 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5220 yv[15][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27745 +001 1 +011 1 +100 1 +101 1 +.names xv[14][19] yv[14][4] yv[14][20] $abc$30358$new_n5172 $abc$30358$new_n5183 $abc$30358$new_n5220 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[14][18] yv[14][3] $abc$30358$new_n5222 yv[15][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27747 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][2] xv[14][17] $abc$30358$new_n5173 $abc$30358$new_n5184 $abc$30358$new_n5222 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[14][17] yv[14][2] $abc$30358$new_n5224 yv[15][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27749 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] $abc$30358$new_n5184 $abc$30358$new_n5173 $abc$30358$new_n5224 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5226 yv[15][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27751 +001 1 +011 1 +110 1 +111 1 +.names xv[14][16] yv[14][1] yv[14][20] yv[14][0] xv[14][15] $abc$30358$new_n5226 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[14][15] yv[14][0] yv[15][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27753 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[14][19] $abc$30358$new_n5229 xv[15][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27755 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5243 yv[14][20] $abc$30358$new_n5230 $abc$30358$new_n5229 +100 1 +110 1 +111 1 +.names xv[14][17] $abc$30358$new_n5231 $abc$30358$new_n5230 +00 1 +01 1 +10 1 +.names xv[14][16] $abc$30358$new_n5232 $abc$30358$new_n5231 +11 1 +.names $abc$30358$new_n5241 $abc$30358$new_n5233 $abc$30358$new_n5232 +10 1 +.names $abc$30358$new_n5240 $abc$30358$new_n5234 yv[14][20] $abc$30358$new_n5239 $abc$30358$new_n5233 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$30358$new_n5235 yv[14][20] xv[14][8] $abc$30358$new_n5234 +101 1 +110 1 +.names yv[14][20] xv[14][5] xv[14][6] xv[14][7] $abc$30358$new_n5236 $abc$30358$new_n5235 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[14][3] yv[14][18] xv[14][4] yv[14][19] $abc$30358$new_n5237 $abc$30358$new_n5236 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[14][2] yv[14][17] $abc$30358$new_n5238 $abc$30358$new_n5237 +000 1 +001 1 +011 1 +101 1 +.names xv[14][0] yv[14][15] xv[14][1] yv[14][16] $abc$30358$new_n5238 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[14][8] xv[14][9] xv[14][10] xv[14][11] $abc$30358$new_n5239 +0000 1 +.names yv[14][20] xv[14][9] xv[14][10] xv[14][11] $abc$30358$new_n5240 +0111 1 +1000 1 +.names yv[14][20] xv[14][12] xv[14][13] xv[14][14] xv[14][15] $abc$30358$new_n5241 +01111 1 +10000 1 +.names xv[14][18] $abc$30358$new_n5244 $abc$30358$new_n5243 +10 1 +.names xv[14][17] xv[14][16] $abc$30358$new_n5245 $abc$30358$new_n5244 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$30358$new_n5252 $abc$30358$new_n5246 yv[14][20] $abc$30358$new_n5239 $abc$30358$new_n5245 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$30358$new_n5247 yv[14][20] xv[14][9] xv[14][10] xv[14][11] $abc$30358$new_n5246 +10000 1 +11111 1 +.names $abc$30358$new_n5248 yv[14][20] xv[14][8] $abc$30358$new_n5247 +100 1 +111 1 +.names yv[14][20] xv[14][6] xv[14][7] $abc$30358$new_n5249 xv[14][5] $abc$30358$new_n5248 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11110 1 +11111 1 +.names yv[14][19] xv[14][4] $abc$30358$new_n5250 yv[14][20] xv[14][5] $abc$30358$new_n5249 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names yv[14][17] xv[14][2] xv[14][3] yv[14][18] $abc$30358$new_n5251 $abc$30358$new_n5250 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[14][15] xv[14][0] xv[14][1] yv[14][16] $abc$30358$new_n5251 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[14][20] xv[14][12] xv[14][13] xv[14][14] xv[14][15] $abc$30358$new_n5252 +00000 1 +11111 1 +.names i_ce xv[14][17] xv[14][16] $abc$30358$new_n5257 xv[15][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27759 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[14][15] $abc$30358$new_n5258 $abc$30358$new_n5257 +00 1 +01 1 +10 1 +.names xv[14][14] yv[14][20] $abc$30358$new_n5259 $abc$30358$new_n5260 $abc$30358$new_n5258 +1000 1 +1010 1 +1110 1 +1111 1 +.names xv[14][12] xv[14][13] $abc$30358$new_n5246 $abc$30358$new_n5259 +111 1 +.names xv[14][13] xv[14][12] $abc$30358$new_n5233 $abc$30358$new_n5260 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n5257 xv[14][16] xv[15][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27761 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[14][15] $abc$30358$new_n5258 xv[15][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27763 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5264 i_ce xv[15][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27765 +001 1 +010 1 +011 1 +.names i_ce xv[14][14] yv[14][20] $abc$30358$new_n5260 $abc$30358$new_n5259 $abc$30358$new_n5264 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n5266 xv[15][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27767 +001 1 +011 1 +110 1 +111 1 +.names xv[14][13] yv[14][20] xv[14][12] $abc$30358$new_n5246 $abc$30358$new_n5233 $abc$30358$new_n5266 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5268 i_ce xv[15][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27769 +001 1 +010 1 +011 1 +.names i_ce yv[14][20] xv[14][12] $abc$30358$new_n5246 $abc$30358$new_n5233 $abc$30358$new_n5268 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[14][11] xv[14][10] $abc$30358$new_n5270 xv[15][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27771 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[14][9] $abc$30358$new_n5271 $abc$30358$new_n5270 +11 1 +.names yv[14][20] $abc$30358$new_n5234 $abc$30358$new_n5247 $abc$30358$new_n5271 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[14][10] $abc$30358$new_n5270 xv[15][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27773 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[14][9] $abc$30358$new_n5271 xv[15][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27775 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[14][7] $abc$30358$new_n5277 xv[15][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27779 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[14][6] yv[14][20] $abc$30358$new_n5278 $abc$30358$new_n5249 $abc$30358$new_n5277 +1010 1 +1011 1 +1101 1 +1111 1 +.names xv[14][5] $abc$30358$new_n5236 $abc$30358$new_n5278 +10 1 +.names $abc$30358$new_n5280 i_ce xv[15][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27781 +001 1 +010 1 +011 1 +.names i_ce yv[14][20] xv[14][6] $abc$30358$new_n5249 $abc$30358$new_n5278 $abc$30358$new_n5280 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5282 xv[14][5] xv[15][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27783 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[14][20] yv[14][19] xv[14][4] $abc$30358$new_n5250 $abc$30358$new_n5236 $abc$30358$new_n5282 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[14][4] yv[14][19] $abc$30358$new_n5284 xv[15][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27785 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] xv[14][3] yv[14][18] $abc$30358$new_n5237 $abc$30358$new_n5250 $abc$30358$new_n5284 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[14][3] yv[14][18] $abc$30358$new_n5286 xv[15][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27787 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] xv[14][2] yv[14][17] $abc$30358$new_n5251 $abc$30358$new_n5238 $abc$30358$new_n5286 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[14][2] yv[14][17] $abc$30358$new_n5288 xv[15][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27789 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] $abc$30358$new_n5238 $abc$30358$new_n5251 $abc$30358$new_n5288 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n5290 xv[15][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27791 +001 1 +011 1 +110 1 +111 1 +.names xv[14][1] yv[14][16] yv[14][20] xv[14][0] yv[14][15] $abc$30358$new_n5290 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[14][0] yv[14][15] xv[15][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27793 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5293 ph[15][19] ph[16][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27795 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[15][17] ph[15][18] $abc$30358$new_n5294 $abc$30358$new_n5302 $abc$30358$new_n5293 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[15][16] $abc$30358$new_n5295 $abc$30358$new_n5294 +11 1 +.names $abc$30358$new_n5296 ph[15][15] yv[15][20] $abc$30358$new_n5295 +110 1 +.names ph[15][14] $abc$30358$new_n5297 $abc$30358$new_n5296 +11 1 +.names ph[15][13] $abc$30358$new_n5298 $abc$30358$new_n5297 +11 1 +.names ph[15][12] $abc$30358$new_n5299 $abc$30358$new_n5298 +11 1 +.names ph[15][8] ph[15][9] ph[15][10] ph[15][11] $abc$30358$new_n5300 $abc$30358$new_n5299 +11111 1 +.names ph[15][4] ph[15][5] ph[15][6] ph[15][7] $abc$30358$new_n5301 $abc$30358$new_n5300 +11111 1 +.names ph[15][3] ph[15][2] ph[15][0] ph[15][1] $abc$30358$new_n5301 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n5303 ph[15][16] $abc$30358$new_n5302 +10 1 +.names yv[15][20] $abc$30358$new_n5304 ph[15][15] $abc$30358$new_n5303 +110 1 +.names $abc$30358$new_n5305 ph[15][14] $abc$30358$new_n5304 +10 1 +.names $abc$30358$new_n5306 ph[15][13] $abc$30358$new_n5305 +10 1 +.names $abc$30358$new_n5307 ph[15][9] ph[15][10] ph[15][11] ph[15][12] $abc$30358$new_n5306 +10000 1 +.names $abc$30358$new_n5308 ph[15][5] ph[15][6] ph[15][7] ph[15][8] $abc$30358$new_n5307 +10000 1 +.names ph[15][4] ph[15][3] ph[15][2] ph[15][0] ph[15][1] $abc$30358$new_n5308 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names i_ce $abc$30358$new_n5310 ph[15][18] ph[16][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27797 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[15][17] $abc$30358$new_n5294 $abc$30358$new_n5302 $abc$30358$new_n5310 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[15][17] $abc$30358$new_n5302 $abc$30358$new_n5294 ph[16][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27799 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[15][16] $abc$30358$new_n5303 $abc$30358$new_n5295 ph[16][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27801 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5314 ph[16][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27803 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce yv[15][20] ph[15][15] $abc$30358$new_n5304 $abc$30358$new_n5296 $abc$30358$new_n5314 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5316 ph[16][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27805 +001 1 +011 1 +110 1 +111 1 +.names yv[15][20] ph[15][14] $abc$30358$new_n5305 $abc$30358$new_n5297 $abc$30358$new_n5316 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5318 ph[16][13] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27807 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce yv[15][20] ph[15][13] $abc$30358$new_n5306 $abc$30358$new_n5298 $abc$30358$new_n5318 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[15][12] $abc$30358$new_n5320 ph[16][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27809 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[15][9] ph[15][10] ph[15][11] $abc$30358$new_n5321 $abc$30358$new_n5325 $abc$30358$new_n5320 +00001 1 +00011 1 +11110 1 +11111 1 +.names ph[15][8] $abc$30358$new_n5322 $abc$30358$new_n5321 +11 1 +.names ph[15][6] ph[15][7] $abc$30358$new_n5323 $abc$30358$new_n5322 +111 1 +.names ph[15][4] ph[15][5] $abc$30358$new_n5324 $abc$30358$new_n5323 +111 1 +.names $abc$30358$new_n5301 yv[15][20] $abc$30358$new_n5324 +10 1 +.names $abc$30358$new_n5326 ph[15][8] $abc$30358$new_n5325 +10 1 +.names $abc$30358$new_n5327 ph[15][6] ph[15][7] $abc$30358$new_n5326 +100 1 +.names $abc$30358$new_n5328 ph[15][4] ph[15][5] $abc$30358$new_n5327 +100 1 +.names yv[15][20] ph[15][3] ph[15][2] ph[15][0] ph[15][1] $abc$30358$new_n5328 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names i_ce $abc$30358$new_n5330 ph[15][11] ph[16][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27811 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[15][9] ph[15][10] $abc$30358$new_n5321 $abc$30358$new_n5325 $abc$30358$new_n5330 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5332 ph[16][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27813 +001 1 +011 1 +100 1 +101 1 +.names ph[15][10] ph[15][9] $abc$30358$new_n5325 $abc$30358$new_n5321 $abc$30358$new_n5332 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[15][9] $abc$30358$new_n5325 $abc$30358$new_n5321 ph[16][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27815 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[15][8] $abc$30358$new_n5326 $abc$30358$new_n5322 ph[16][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27817 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5336 i_ce ph[16][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27819 +001 1 +010 1 +011 1 +.names i_ce ph[15][7] ph[15][6] $abc$30358$new_n5327 $abc$30358$new_n5323 $abc$30358$new_n5336 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce ph[15][6] $abc$30358$new_n5327 $abc$30358$new_n5323 ph[16][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27821 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5339 ph[16][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27823 +001 1 +011 1 +100 1 +101 1 +.names ph[15][5] ph[15][4] $abc$30358$new_n5328 $abc$30358$new_n5324 $abc$30358$new_n5339 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[15][4] $abc$30358$new_n5328 $abc$30358$new_n5324 ph[16][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27825 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5342 ph[16][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27827 +001 1 +011 1 +100 1 +101 1 +.names yv[15][20] ph[15][3] ph[15][2] ph[15][0] ph[15][1] $abc$30358$new_n5342 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n5344 ph[16][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27829 +001 1 +011 1 +110 1 +111 1 +.names ph[15][2] yv[15][20] ph[15][0] ph[15][1] $abc$30358$new_n5344 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[15][20] ph[15][0] ph[15][1] ph[16][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27831 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[15][0] ph[16][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27833 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[15][20] yv[15][19] $abc$30358$new_n5348 yv[16][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27835 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][18] xv[15][20] $abc$30358$new_n5365 $abc$30358$new_n5349 $abc$30358$new_n5348 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n5350 xv[15][20] yv[15][16] yv[15][17] $abc$30358$new_n5349 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$30358$new_n5364 $abc$30358$new_n5362 $abc$30358$new_n5360 $abc$30358$new_n5363 $abc$30358$new_n5351 $abc$30358$new_n5350 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[15][20] $abc$30358$new_n5393 yv[15][10] yv[15][11] $abc$30358$new_n5351 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[15][20] yv[15][6] yv[15][7] $abc$30358$new_n5354 $abc$30358$new_n5358 $abc$30358$new_n5353 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names $abc$30358$new_n5355 xv[15][20] yv[15][5] $abc$30358$new_n5354 +101 1 +110 1 +.names xv[15][19] yv[15][3] xv[15][20] yv[15][4] $abc$30358$new_n5356 $abc$30358$new_n5355 +01010 1 +01100 1 +10010 1 +10100 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[15][18] yv[15][2] $abc$30358$new_n5357 $abc$30358$new_n5356 +000 1 +001 1 +011 1 +101 1 +.names xv[15][16] yv[15][0] xv[15][17] yv[15][1] $abc$30358$new_n5357 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[15][4] yv[15][5] $abc$30358$new_n5358 +00 1 +.names xv[15][20] $abc$30358$new_n5361 yv[15][14] yv[15][15] $abc$30358$new_n5360 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names yv[15][12] yv[15][13] $abc$30358$new_n5361 +00 1 +.names xv[15][20] yv[15][16] $abc$30358$new_n5362 +01 1 +10 1 +.names xv[15][20] yv[15][12] yv[15][13] yv[15][14] yv[15][15] $abc$30358$new_n5363 +01111 1 +10000 1 +.names xv[15][20] yv[15][17] $abc$30358$new_n5364 +01 1 +10 1 +.names xv[15][20] $abc$30358$new_n5366 yv[15][16] yv[15][17] $abc$30358$new_n5365 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][20] yv[15][14] yv[15][15] $abc$30358$new_n5367 $abc$30358$new_n5361 $abc$30358$new_n5366 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[15][20] yv[15][12] yv[15][13] $abc$30358$new_n5368 $abc$30358$new_n5367 +0000 1 +1110 1 +.names xv[15][20] $abc$30358$new_n5369 yv[15][10] yv[15][11] $abc$30358$new_n5368 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][20] $abc$30358$new_n5370 yv[15][8] yv[15][9] $abc$30358$new_n5369 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][20] $abc$30358$new_n5371 yv[15][6] yv[15][7] $abc$30358$new_n5370 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][20] $abc$30358$new_n5372 yv[15][4] yv[15][5] $abc$30358$new_n5371 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][18] xv[15][19] yv[15][2] yv[15][3] $abc$30358$new_n5373 $abc$30358$new_n5372 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[15][16] xv[15][17] yv[15][0] yv[15][1] $abc$30358$new_n5373 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[15][20] yv[15][18] $abc$30358$new_n5375 yv[16][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27837 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[15][20] $abc$30358$new_n5349 $abc$30358$new_n5365 $abc$30358$new_n5375 +001 1 +011 1 +100 1 +101 1 +.names i_ce $abc$30358$new_n5377 $abc$30358$new_n5364 yv[16][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27839 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[15][20] yv[15][16] xv[15][20] $abc$30358$new_n5366 $abc$30358$new_n5378 $abc$30358$new_n5377 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n5360 $abc$30358$new_n5351 $abc$30358$new_n5363 $abc$30358$new_n5378 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5380 $abc$30358$new_n5362 yv[16][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27841 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[15][20] $abc$30358$new_n5378 $abc$30358$new_n5366 $abc$30358$new_n5380 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[15][20] yv[15][15] $abc$30358$new_n5382 yv[16][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27843 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][14] xv[15][20] $abc$30358$new_n5384 $abc$30358$new_n5383 $abc$30358$new_n5382 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names xv[15][20] yv[15][12] yv[15][13] $abc$30358$new_n5351 $abc$30358$new_n5383 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n5367 $abc$30358$new_n5361 xv[15][20] $abc$30358$new_n5384 +001 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5386 yv[16][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27845 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][14] yv[15][20] $abc$30358$new_n5384 $abc$30358$new_n5383 $abc$30358$new_n5386 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[15][20] yv[15][13] $abc$30358$new_n5388 yv[16][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27847 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][12] xv[15][20] $abc$30358$new_n5368 $abc$30358$new_n5351 $abc$30358$new_n5388 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5390 yv[16][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27849 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][12] yv[15][20] $abc$30358$new_n5368 $abc$30358$new_n5351 $abc$30358$new_n5390 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[15][20] yv[15][11] $abc$30358$new_n5392 yv[16][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27851 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][10] xv[15][20] $abc$30358$new_n5369 $abc$30358$new_n5393 $abc$30358$new_n5392 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[15][20] $abc$30358$new_n5353 yv[15][8] yv[15][9] $abc$30358$new_n5393 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$30358$new_n5395 yv[16][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27853 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][10] yv[15][20] $abc$30358$new_n5369 $abc$30358$new_n5393 $abc$30358$new_n5395 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[15][20] yv[15][9] $abc$30358$new_n5397 yv[16][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27855 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][8] xv[15][20] $abc$30358$new_n5370 $abc$30358$new_n5353 $abc$30358$new_n5397 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5399 yv[16][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27857 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][8] yv[15][20] $abc$30358$new_n5370 $abc$30358$new_n5353 $abc$30358$new_n5399 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[15][20] yv[15][7] $abc$30358$new_n5401 yv[16][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27859 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][6] xv[15][20] $abc$30358$new_n5371 $abc$30358$new_n5402 $abc$30358$new_n5401 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n5354 $abc$30358$new_n5358 xv[15][20] $abc$30358$new_n5402 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5404 yv[16][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27861 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][6] yv[15][20] $abc$30358$new_n5371 $abc$30358$new_n5402 $abc$30358$new_n5404 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[15][20] yv[15][5] $abc$30358$new_n5406 yv[16][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27863 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][4] xv[15][20] $abc$30358$new_n5372 $abc$30358$new_n5355 $abc$30358$new_n5406 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names i_ce xv[15][20] yv[15][4] $abc$30358$new_n5408 yv[16][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27865 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] xv[15][19] yv[15][3] $abc$30358$new_n5356 $abc$30358$new_n5372 $abc$30358$new_n5408 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[15][19] yv[15][3] $abc$30358$new_n5410 yv[16][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27867 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][2] xv[15][18] $abc$30358$new_n5373 $abc$30358$new_n5357 $abc$30358$new_n5410 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[15][18] yv[15][2] $abc$30358$new_n5412 yv[16][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27869 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] $abc$30358$new_n5357 $abc$30358$new_n5373 $abc$30358$new_n5412 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5414 yv[16][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27871 +001 1 +011 1 +110 1 +111 1 +.names xv[15][17] yv[15][1] yv[15][20] yv[15][0] xv[15][16] $abc$30358$new_n5414 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[15][16] yv[15][0] yv[16][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27873 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[15][19] $abc$30358$new_n5417 xv[16][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27875 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[15][18] yv[15][20] $abc$30358$new_n5418 $abc$30358$new_n5429 $abc$30358$new_n5417 +1000 1 +1001 1 +1101 1 +1111 1 +.names xv[15][17] xv[15][16] $abc$30358$new_n5419 $abc$30358$new_n5418 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names xv[15][14] xv[15][15] $abc$30358$new_n5420 $abc$30358$new_n5419 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names yv[15][20] xv[15][12] xv[15][13] $abc$30358$new_n5421 $abc$30358$new_n5420 +0110 1 +1000 1 +.names yv[15][20] $abc$30358$new_n5427 $abc$30358$new_n5422 xv[15][10] xv[15][11] $abc$30358$new_n5421 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +.names yv[15][20] xv[15][7] xv[15][8] $abc$30358$new_n5423 xv[15][6] $abc$30358$new_n5422 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[15][6] yv[15][20] xv[15][4] xv[15][5] $abc$30358$new_n5424 $abc$30358$new_n5423 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +.names xv[15][3] yv[15][19] $abc$30358$new_n5425 $abc$30358$new_n5424 +010 1 +100 1 +110 1 +111 1 +.names xv[15][2] yv[15][18] $abc$30358$new_n5426 $abc$30358$new_n5425 +000 1 +001 1 +011 1 +101 1 +.names xv[15][0] yv[15][16] xv[15][1] yv[15][17] $abc$30358$new_n5426 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[15][9] yv[15][20] xv[15][7] xv[15][8] $abc$30358$new_n5423 $abc$30358$new_n5427 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[15][16] xv[15][17] $abc$30358$new_n5430 $abc$30358$new_n5429 +111 1 +.names $abc$30358$new_n5441 $abc$30358$new_n6078 $abc$30358$new_n5430 +10 1 +.names yv[15][20] xv[15][8] $abc$30358$new_n5434 $abc$30358$new_n5433 +000 1 +110 1 +.names yv[15][20] $abc$30358$new_n5439 $abc$30358$new_n5435 xv[15][4] $abc$30358$new_n5434 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names yv[15][19] xv[15][3] $abc$30358$new_n5436 $abc$30358$new_n5435 +000 1 +100 1 +101 1 +110 1 +.names xv[15][2] yv[15][18] $abc$30358$new_n5437 $abc$30358$new_n5436 +001 1 +100 1 +101 1 +111 1 +.names yv[15][16] xv[15][0] xv[15][1] yv[15][17] $abc$30358$new_n5437 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[15][20] xv[15][5] xv[15][6] xv[15][7] $abc$30358$new_n5439 +0000 1 +1111 1 +.names yv[15][20] xv[15][12] xv[15][13] xv[15][14] xv[15][15] $abc$30358$new_n5441 +00000 1 +11111 1 +.names i_ce $abc$30358$new_n5447 xv[16][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27879 +001 1 +011 1 +110 1 +111 1 +.names xv[15][17] yv[15][20] xv[15][16] $abc$30358$new_n5430 $abc$30358$new_n5419 $abc$30358$new_n5447 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5449 i_ce xv[16][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27881 +001 1 +010 1 +011 1 +.names i_ce yv[15][20] xv[15][16] $abc$30358$new_n5430 $abc$30358$new_n5419 $abc$30358$new_n5449 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5451 xv[16][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27883 +001 1 +011 1 +110 1 +111 1 +.names xv[15][15] yv[15][20] xv[15][14] $abc$30358$new_n5420 $abc$30358$new_n5452 $abc$30358$new_n5451 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[15][13] xv[15][12] $abc$30358$new_n6078 $abc$30358$new_n5452 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$30358$new_n5454 i_ce xv[16][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27885 +001 1 +010 1 +011 1 +.names i_ce xv[15][14] yv[15][20] $abc$30358$new_n5420 $abc$30358$new_n5452 $abc$30358$new_n5454 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n5456 xv[16][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27887 +001 1 +011 1 +110 1 +111 1 +.names xv[15][13] xv[15][12] $abc$30358$new_n5421 $abc$30358$new_n6078 $abc$30358$new_n5456 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[15][11] xv[15][10] $abc$30358$new_n5460 xv[16][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27891 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5427 $abc$30358$new_n5461 $abc$30358$new_n5460 +10 1 +.names yv[15][20] $abc$30358$new_n5433 $abc$30358$new_n5461 +10 1 +.names i_ce xv[15][10] $abc$30358$new_n5460 xv[16][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27893 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[15][9] $abc$30358$new_n5461 $abc$30358$new_n5464 xv[16][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27895 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[15][20] $abc$30358$new_n5465 xv[15][8] $abc$30358$new_n5464 +000 1 +010 1 +011 1 +.names xv[15][7] $abc$30358$new_n5423 $abc$30358$new_n5465 +00 1 +01 1 +10 1 +.names $abc$30358$new_n5467 i_ce xv[16][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27897 +001 1 +010 1 +011 1 +.names i_ce yv[15][20] xv[15][8] $abc$30358$new_n5434 $abc$30358$new_n5465 $abc$30358$new_n5467 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[15][7] xv[15][6] $abc$30358$new_n5469 xv[16][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27899 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[15][5] $abc$30358$new_n5471 $abc$30358$new_n5470 $abc$30358$new_n5469 +100 1 +.names yv[15][20] $abc$30358$new_n5424 xv[15][4] $abc$30358$new_n5470 +000 1 +001 1 +010 1 +.names yv[15][20] $abc$30358$new_n5435 xv[15][4] $abc$30358$new_n5471 +100 1 +110 1 +111 1 +.names i_ce xv[15][6] $abc$30358$new_n5469 xv[16][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27901 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[15][5] $abc$30358$new_n5471 $abc$30358$new_n5470 xv[16][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27903 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n5475 i_ce xv[16][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27905 +001 1 +010 1 +011 1 +.names i_ce yv[15][20] xv[15][4] $abc$30358$new_n5435 $abc$30358$new_n5424 $abc$30358$new_n5475 +10000 1 +10010 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5477 xv[16][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27907 +001 1 +011 1 +100 1 +101 1 +.names yv[15][20] xv[15][3] yv[15][19] $abc$30358$new_n5436 $abc$30358$new_n5425 $abc$30358$new_n5477 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[15][2] yv[15][18] $abc$30358$new_n5479 xv[16][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27909 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] $abc$30358$new_n5426 $abc$30358$new_n5437 $abc$30358$new_n5479 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[15][1] yv[15][17] $abc$30358$new_n5481 xv[16][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27911 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[15][16] yv[15][20] xv[15][0] $abc$30358$new_n5481 +101 1 +110 1 +.names i_ce xv[15][0] yv[15][16] xv[16][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27913 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5484 ph[16][19] ph[17][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27915 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[16][18] $abc$30358$new_n5485 $abc$30358$new_n5491 $abc$30358$new_n5484 +000 1 +001 1 +100 1 +110 1 +.names yv[16][20] $abc$30358$new_n5486 ph[16][17] $abc$30358$new_n5485 +110 1 +.names $abc$30358$new_n5487 ph[16][16] $abc$30358$new_n5486 +10 1 +.names $abc$30358$new_n5488 ph[16][14] ph[16][15] $abc$30358$new_n5487 +100 1 +.names $abc$30358$new_n5489 ph[16][10] ph[16][11] ph[16][12] ph[16][13] $abc$30358$new_n5488 +10000 1 +.names $abc$30358$new_n5490 ph[16][6] ph[16][7] ph[16][8] ph[16][9] $abc$30358$new_n5489 +10000 1 +.names ph[16][1] ph[16][2] ph[16][3] ph[16][4] ph[16][5] $abc$30358$new_n5490 +00000 1 +.names $abc$30358$new_n5492 ph[16][17] yv[16][20] $abc$30358$new_n5491 +110 1 +.names ph[16][16] $abc$30358$new_n5493 $abc$30358$new_n5492 +11 1 +.names ph[16][4] ph[16][6] ph[16][9] $abc$30358$new_n5496 $abc$30358$new_n5494 $abc$30358$new_n5493 +11111 1 +.names ph[16][3] ph[16][5] ph[16][7] ph[16][8] $abc$30358$new_n5495 $abc$30358$new_n5494 +11111 1 +.names ph[16][1] ph[16][2] ph[16][14] ph[16][15] $abc$30358$new_n5495 +1111 1 +.names ph[16][10] ph[16][11] ph[16][12] ph[16][13] $abc$30358$new_n5496 +1111 1 +.names i_ce ph[16][18] $abc$30358$new_n5491 $abc$30358$new_n5485 ph[17][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27917 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5499 ph[17][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27919 +001 1 +011 1 +110 1 +111 1 +.names ph[16][17] yv[16][20] $abc$30358$new_n5492 $abc$30358$new_n5486 $abc$30358$new_n5499 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n5501 ph[17][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27921 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[16][16] yv[16][20] $abc$30358$new_n5493 $abc$30358$new_n5487 $abc$30358$new_n5501 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n5503 ph[16][15] ph[17][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27923 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[16][14] $abc$30358$new_n5504 ph[16][13] $abc$30358$new_n5509 ph[16][12] $abc$30358$new_n5503 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$30358$new_n5505 ph[16][11] ph[16][12] ph[16][13] $abc$30358$new_n5504 +1000 1 +.names $abc$30358$new_n5506 ph[16][9] ph[16][10] $abc$30358$new_n5505 +100 1 +.names $abc$30358$new_n5507 ph[16][6] ph[16][7] ph[16][8] $abc$30358$new_n5506 +1000 1 +.names $abc$30358$new_n5508 ph[16][5] $abc$30358$new_n5507 +10 1 +.names yv[16][20] ph[16][1] ph[16][2] ph[16][3] ph[16][4] $abc$30358$new_n5508 +10000 1 +.names ph[16][11] $abc$30358$new_n5510 $abc$30358$new_n5509 +11 1 +.names ph[16][9] ph[16][10] $abc$30358$new_n5511 $abc$30358$new_n5510 +111 1 +.names ph[16][6] ph[16][7] ph[16][8] $abc$30358$new_n5512 $abc$30358$new_n5511 +1111 1 +.names ph[16][5] $abc$30358$new_n5513 $abc$30358$new_n5512 +11 1 +.names ph[16][4] ph[16][1] ph[16][2] ph[16][3] yv[16][20] $abc$30358$new_n5513 +11110 1 +.names i_ce $abc$30358$new_n5515 ph[17][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27925 +001 1 +011 1 +110 1 +111 1 +.names ph[16][14] $abc$30358$new_n5504 ph[16][12] ph[16][13] $abc$30358$new_n5509 $abc$30358$new_n5515 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names i_ce ph[17][13] $abc$30358$new_n5504 $abc$30358$new_n5517 $abc$30358$auto$rtlil.cc:2693:MuxGate$27927 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[16][11] ph[16][13] ph[16][12] $abc$30358$new_n5510 $abc$30358$new_n5505 $abc$30358$new_n5517 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5519 ph[16][12] ph[17][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27929 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[16][11] $abc$30358$new_n5505 $abc$30358$new_n5510 $abc$30358$new_n5519 +000 1 +001 1 +100 1 +110 1 +.names i_ce ph[16][11] $abc$30358$new_n5510 $abc$30358$new_n5505 ph[17][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27931 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5522 i_ce ph[17][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27933 +001 1 +010 1 +011 1 +.names i_ce ph[16][9] ph[16][10] $abc$30358$new_n5511 $abc$30358$new_n5506 $abc$30358$new_n5522 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[16][9] $abc$30358$new_n5511 $abc$30358$new_n5506 ph[17][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27935 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5506 ph[17][8] $abc$30358$new_n5525 $abc$30358$new_n5511 $abc$30358$auto$rtlil.cc:2693:MuxGate$27937 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[16][8] ph[16][6] ph[16][7] $abc$30358$new_n5507 $abc$30358$new_n5512 $abc$30358$new_n5525 +01101 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5527 ph[16][7] ph[17][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27939 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[16][6] $abc$30358$new_n5507 $abc$30358$new_n5512 $abc$30358$new_n5527 +000 1 +001 1 +100 1 +110 1 +.names i_ce ph[16][6] $abc$30358$new_n5512 $abc$30358$new_n5507 ph[17][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27941 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[16][5] $abc$30358$new_n5513 $abc$30358$new_n5508 ph[17][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27943 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5531 ph[17][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27945 +001 1 +011 1 +100 1 +101 1 +.names ph[16][4] yv[16][20] ph[16][1] ph[16][2] ph[16][3] $abc$30358$new_n5531 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +.names i_ce $abc$30358$new_n5533 ph[17][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27947 +001 1 +011 1 +100 1 +101 1 +.names ph[16][3] yv[16][20] ph[16][1] ph[16][2] $abc$30358$new_n5533 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[16][20] ph[16][1] ph[16][2] ph[17][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27949 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[16][1] ph[17][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27951 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[16][0] ph[17][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27953 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[16][20] yv[16][19] $abc$30358$new_n5538 yv[17][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27955 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[16][20] yv[16][18] xv[16][20] $abc$30358$new_n5551 $abc$30358$new_n5539 $abc$30358$new_n5538 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n6084 xv[16][20] yv[16][16] yv[16][17] $abc$30358$new_n5539 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names xv[16][20] $abc$30358$new_n5546 $abc$30358$new_n5543 yv[16][4] $abc$30358$new_n5542 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names xv[16][19] yv[16][2] $abc$30358$new_n5544 xv[16][20] yv[16][3] $abc$30358$new_n5543 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +.names xv[16][17] yv[16][0] xv[16][18] yv[16][1] $abc$30358$new_n5544 +0011 1 +0111 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names yv[16][6] yv[16][7] yv[16][5] xv[16][20] yv[16][3] $abc$30358$new_n5546 +00010 1 +00011 1 +11101 1 +.names xv[16][20] yv[16][8] yv[16][9] yv[16][10] yv[16][11] $abc$30358$new_n5549 +01111 1 +10000 1 +.names xv[16][20] $abc$30358$new_n5552 yv[16][16] yv[16][17] $abc$30358$new_n5551 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n5558 $abc$30358$new_n5559 xv[16][20] $abc$30358$new_n5554 $abc$30358$new_n5552 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names xv[16][20] $abc$30358$new_n5557 $abc$30358$new_n5555 yv[16][7] $abc$30358$new_n5554 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names yv[16][2] xv[16][19] $abc$30358$new_n5556 yv[16][3] xv[16][20] $abc$30358$new_n5555 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11100 1 +11101 1 +11111 1 +.names xv[16][17] xv[16][18] yv[16][0] yv[16][1] $abc$30358$new_n5556 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[16][20] yv[16][6] yv[16][4] yv[16][5] yv[16][3] $abc$30358$new_n5557 +00000 1 +00001 1 +11111 1 +.names xv[16][20] yv[16][8] yv[16][9] yv[16][10] yv[16][11] $abc$30358$new_n5558 +00000 1 +11111 1 +.names xv[16][20] yv[16][12] yv[16][13] yv[16][14] yv[16][15] $abc$30358$new_n5559 +00000 1 +11111 1 +.names i_ce xv[16][20] yv[16][18] $abc$30358$new_n5561 yv[17][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27957 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[16][20] $abc$30358$new_n5539 $abc$30358$new_n5551 $abc$30358$new_n5561 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[16][19] $abc$30358$new_n6086 $abc$30358$new_n5580 xv[17][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27995 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n5578 $abc$30358$new_n6086 $abc$30358$new_n5565 +10 1 +.names $abc$30358$new_n5571 yv[16][20] xv[16][4] $abc$30358$new_n5570 +100 1 +111 1 +.names xv[16][2] yv[16][19] yv[16][20] xv[16][3] $abc$30358$new_n5572 $abc$30358$new_n5571 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[16][17] xv[16][0] xv[16][1] yv[16][18] $abc$30358$new_n5572 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[16][20] xv[16][12] xv[16][13] xv[16][14] xv[16][15] $abc$30358$new_n5578 +00000 1 +11111 1 +.names xv[16][18] xv[16][16] xv[16][17] $abc$30358$new_n5581 $abc$30358$new_n5580 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$30358$new_n5582 xv[16][14] xv[16][15] $abc$30358$new_n5581 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[16][12] xv[16][13] $abc$30358$new_n5583 $abc$30358$new_n5582 +110 1 +.names yv[16][20] $abc$30358$new_n5584 xv[16][10] xv[16][11] $abc$30358$new_n5583 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[16][20] xv[16][8] xv[16][9] $abc$30358$new_n5585 $abc$30358$new_n5584 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[16][7] $abc$30358$new_n5586 yv[16][20] xv[16][6] $abc$30358$new_n5585 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[16][6] yv[16][20] xv[16][4] xv[16][5] $abc$30358$new_n5587 $abc$30358$new_n5586 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +.names xv[16][2] yv[16][19] yv[16][20] xv[16][3] $abc$30358$new_n5588 $abc$30358$new_n5587 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[16][0] yv[16][17] xv[16][1] yv[16][18] $abc$30358$new_n5588 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[16][17] $abc$30358$new_n5593 xv[17][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27999 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[16][16] yv[16][20] $abc$30358$new_n5581 $abc$30358$new_n5565 $abc$30358$new_n5593 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$30358$new_n5595 i_ce xv[17][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$28001 +001 1 +010 1 +011 1 +.names i_ce yv[16][20] xv[16][16] $abc$30358$new_n5565 $abc$30358$new_n5581 $abc$30358$new_n5595 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[16][15] $abc$30358$new_n5597 xv[17][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$28003 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[16][14] $abc$30358$new_n5582 $abc$30358$new_n5598 $abc$30358$new_n5597 +110 1 +.names xv[16][13] xv[16][12] $abc$30358$new_n6086 $abc$30358$new_n5598 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n5602 xv[17][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$28007 +001 1 +011 1 +110 1 +111 1 +.names xv[16][13] xv[16][12] $abc$30358$new_n5583 $abc$30358$new_n6086 $abc$30358$new_n5602 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[16][11] xv[16][10] $abc$30358$new_n5606 xv[17][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$28011 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[16][9] $abc$30358$new_n5607 $abc$30358$new_n5606 +11 1 +.names xv[16][8] $abc$30358$new_n5585 $abc$30358$new_n6088 $abc$30358$new_n5607 +110 1 +.names i_ce xv[16][10] $abc$30358$new_n5606 xv[17][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$28013 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][9] $abc$30358$new_n5607 xv[17][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$28015 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][7] xv[16][6] $abc$30358$new_n5613 xv[17][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$28019 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[16][5] $abc$30358$new_n5615 $abc$30358$new_n5614 $abc$30358$new_n5613 +100 1 +.names yv[16][20] $abc$30358$new_n5570 $abc$30358$new_n5614 +10 1 +.names $abc$30358$new_n5587 xv[16][4] $abc$30358$new_n5615 +00 1 +01 1 +10 1 +.names i_ce xv[16][6] $abc$30358$new_n5613 xv[17][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$28021 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][5] $abc$30358$new_n5615 $abc$30358$new_n5614 xv[17][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$28023 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[16][3] $abc$30358$new_n5621 xv[17][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$28027 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[16][20] xv[16][2] yv[16][19] $abc$30358$new_n5572 $abc$30358$new_n5588 $abc$30358$new_n5621 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[16][2] yv[16][19] $abc$30358$new_n5623 xv[17][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$28029 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[16][20] $abc$30358$new_n5588 $abc$30358$new_n5572 $abc$30358$new_n5623 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n5625 xv[17][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$28031 +001 1 +011 1 +110 1 +111 1 +.names xv[16][1] yv[16][18] yv[16][20] xv[16][0] yv[16][17] $abc$30358$new_n5625 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[16][0] yv[16][17] xv[17][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$28033 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[17][19] $abc$30358$new_n5628 ph[18][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$28035 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[17][17] ph[17][18] yv[17][20] $abc$30358$new_n5629 $abc$30358$new_n5635 $abc$30358$new_n5628 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n5630 ph[17][16] $abc$30358$new_n5629 +10 1 +.names $abc$30358$new_n5631 ph[17][15] $abc$30358$new_n5630 +10 1 +.names $abc$30358$new_n5632 ph[17][13] ph[17][14] $abc$30358$new_n5631 +100 1 +.names $abc$30358$new_n5633 ph[17][9] ph[17][10] ph[17][11] ph[17][12] $abc$30358$new_n5632 +10000 1 +.names $abc$30358$new_n5634 ph[17][5] ph[17][6] ph[17][7] ph[17][8] $abc$30358$new_n5633 +10000 1 +.names ph[17][0] ph[17][1] ph[17][2] ph[17][3] ph[17][4] $abc$30358$new_n5634 +00000 1 +.names ph[17][16] $abc$30358$new_n5636 $abc$30358$new_n5635 +11 1 +.names ph[17][15] $abc$30358$new_n5637 $abc$30358$new_n5636 +11 1 +.names ph[17][3] ph[17][5] ph[17][8] $abc$30358$new_n5640 $abc$30358$new_n5638 $abc$30358$new_n5637 +11111 1 +.names ph[17][2] ph[17][4] ph[17][6] ph[17][7] $abc$30358$new_n5639 $abc$30358$new_n5638 +11111 1 +.names ph[17][0] ph[17][1] ph[17][13] ph[17][14] $abc$30358$new_n5639 +1111 1 +.names ph[17][9] ph[17][10] ph[17][11] ph[17][12] $abc$30358$new_n5640 +1111 1 +.names i_ce $abc$30358$new_n5645 ph[18][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$28039 +001 1 +011 1 +110 1 +111 1 +.names ph[17][17] yv[17][20] $abc$30358$new_n5635 $abc$30358$new_n5629 $abc$30358$new_n5645 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n5647 ph[18][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$28041 +001 1 +011 1 +110 1 +111 1 +.names ph[17][16] yv[17][20] $abc$30358$new_n5636 $abc$30358$new_n5630 $abc$30358$new_n5647 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n5649 ph[18][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28043 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[17][15] yv[17][20] $abc$30358$new_n5637 $abc$30358$new_n5631 $abc$30358$new_n5649 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce ph[17][14] $abc$30358$new_n5651 ph[18][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$28045 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[17][13] $abc$30358$new_n5652 $abc$30358$new_n5640 $abc$30358$new_n5657 ph[17][8] $abc$30358$new_n5651 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$30358$new_n5653 ph[17][10] ph[17][11] ph[17][12] $abc$30358$new_n5652 +1000 1 +.names $abc$30358$new_n5654 ph[17][8] ph[17][9] $abc$30358$new_n5653 +100 1 +.names $abc$30358$new_n5655 ph[17][7] $abc$30358$new_n5654 +10 1 +.names $abc$30358$new_n5656 ph[17][4] ph[17][5] ph[17][6] $abc$30358$new_n5655 +1000 1 +.names yv[17][20] ph[17][0] ph[17][1] ph[17][2] ph[17][3] $abc$30358$new_n5656 +10000 1 +.names ph[17][7] $abc$30358$new_n5658 $abc$30358$new_n5657 +11 1 +.names ph[17][4] ph[17][5] ph[17][6] $abc$30358$new_n5659 $abc$30358$new_n5658 +1111 1 +.names ph[17][3] ph[17][0] ph[17][1] ph[17][2] yv[17][20] $abc$30358$new_n5659 +11110 1 +.names i_ce $abc$30358$new_n5661 ph[18][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$28047 +001 1 +011 1 +110 1 +111 1 +.names ph[17][13] $abc$30358$new_n5652 ph[17][8] $abc$30358$new_n5640 $abc$30358$new_n5657 $abc$30358$new_n5661 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names i_ce $abc$30358$new_n5663 ph[18][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28049 +001 1 +011 1 +110 1 +111 1 +.names ph[17][10] ph[17][12] ph[17][11] $abc$30358$new_n5653 $abc$30358$new_n5664 $abc$30358$new_n5663 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[17][8] ph[17][9] $abc$30358$new_n5657 $abc$30358$new_n5664 +111 1 +.names i_ce ph[17][11] $abc$30358$new_n5666 ph[18][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$28051 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[17][10] $abc$30358$new_n5664 $abc$30358$new_n5653 $abc$30358$new_n5666 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[17][10] $abc$30358$new_n5653 $abc$30358$new_n5664 ph[18][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$28053 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5669 i_ce ph[18][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$28055 +001 1 +010 1 +011 1 +.names i_ce ph[17][9] ph[17][8] $abc$30358$new_n5654 $abc$30358$new_n5657 $abc$30358$new_n5669 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce ph[17][8] $abc$30358$new_n5654 $abc$30358$new_n5657 ph[18][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$28057 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[17][7] $abc$30358$new_n5655 $abc$30358$new_n5658 ph[18][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$28059 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[18][6] $abc$30358$new_n5655 $abc$30358$new_n5673 $abc$30358$auto$rtlil.cc:2693:MuxGate$28061 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[17][4] ph[17][6] ph[17][5] $abc$30358$new_n5659 $abc$30358$new_n5656 $abc$30358$new_n5673 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5675 ph[18][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$28063 +001 1 +011 1 +100 1 +101 1 +.names ph[17][5] ph[17][4] $abc$30358$new_n5656 $abc$30358$new_n5659 $abc$30358$new_n5675 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[17][4] $abc$30358$new_n5656 $abc$30358$new_n5659 ph[18][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$28065 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5678 ph[18][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$28067 +001 1 +011 1 +100 1 +101 1 +.names ph[17][3] yv[17][20] ph[17][0] ph[17][1] ph[17][2] $abc$30358$new_n5678 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +.names i_ce $abc$30358$new_n5680 ph[18][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$28069 +001 1 +011 1 +100 1 +101 1 +.names ph[17][2] yv[17][20] ph[17][0] ph[17][1] $abc$30358$new_n5680 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[17][20] ph[17][0] ph[17][1] ph[18][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$28071 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[17][0] ph[18][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$28073 +001 1 +011 1 +100 1 +101 1 +.names i_ce i_xval[12] i_yval[12] ph[0][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$28075 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[0][18] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28077 +01 1 +10 1 +11 1 +.names i_ce ph[0][19] yv[0][20] ph[0][18] ph[1][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$28079 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[0][20] ph[0][18] ph[1][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$28081 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[0][20] ph[1][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$28083 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$28085 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][20] ph[1][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$28087 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][20] ph[1][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$28089 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$28091 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][20] ph[1][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28093 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$28095 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$28097 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$28099 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][20] ph[1][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$28101 +001 1 +011 1 +110 1 +111 1 +.names ph[1][7] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28103 +01 1 +10 1 +11 1 +.names i_ce $abc$30358$new_n5699 xv[18][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$28105 +001 1 +011 1 +100 1 +101 1 +.names xv[17][19] yv[17][20] xv[17][18] $abc$30358$new_n5712 $abc$30358$new_n5700 $abc$30358$new_n5699 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11100 1 +11101 1 +.names xv[17][17] xv[17][16] $abc$30358$new_n5701 $abc$30358$new_n5700 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$30358$new_n5711 $abc$30358$new_n5702 $abc$30358$new_n5701 +00 1 +01 1 +11 1 +.names $abc$30358$new_n5703 $abc$30358$new_n5709 yv[17][20] $abc$30358$new_n5702 +000 1 +010 1 +011 1 +.names $abc$30358$new_n5704 yv[17][20] xv[17][9] xv[17][10] xv[17][11] $abc$30358$new_n5703 +10111 1 +11000 1 +.names xv[17][8] yv[17][20] xv[17][6] xv[17][7] $abc$30358$new_n6098 $abc$30358$new_n5704 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[17][0] yv[17][18] xv[17][1] yv[17][19] $abc$30358$new_n5707 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[17][8] xv[17][9] xv[17][10] xv[17][11] $abc$30358$new_n5709 +0000 1 +.names yv[17][20] xv[17][12] xv[17][13] xv[17][14] xv[17][15] $abc$30358$new_n5711 +01111 1 +10000 1 +.names $abc$30358$new_n5725 xv[17][16] xv[17][17] $abc$30358$new_n5712 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n5715 $abc$30358$new_n5709 yv[17][20] $abc$30358$new_n5714 +001 1 +010 1 +011 1 +.names $abc$30358$new_n5716 yv[17][20] xv[17][9] xv[17][10] xv[17][11] $abc$30358$new_n5715 +10000 1 +11111 1 +.names yv[17][20] xv[17][8] xv[17][6] xv[17][7] $abc$30358$new_n5717 $abc$30358$new_n5716 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +11111 1 +.names yv[17][20] xv[17][3] xv[17][4] xv[17][5] $abc$30358$new_n5718 $abc$30358$new_n5717 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11110 1 +.names yv[17][20] xv[17][2] $abc$30358$new_n5719 $abc$30358$new_n5718 +000 1 +100 1 +101 1 +110 1 +.names yv[17][18] xv[17][0] xv[17][1] yv[17][19] $abc$30358$new_n5719 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[17][20] xv[17][12] xv[17][13] xv[17][14] xv[17][15] $abc$30358$new_n5720 +00000 1 +11111 1 +.names $abc$30358$new_n5722 i_ce xv[18][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$28107 +001 1 +010 1 +011 1 +.names i_ce yv[17][20] xv[17][18] $abc$30358$new_n5712 $abc$30358$new_n5700 $abc$30358$new_n5722 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5724 xv[18][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$28109 +001 1 +011 1 +110 1 +111 1 +.names xv[17][17] yv[17][20] xv[17][16] $abc$30358$new_n5725 $abc$30358$new_n5701 $abc$30358$new_n5724 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5720 $abc$30358$new_n5715 $abc$30358$new_n5725 +11 1 +.names $abc$30358$new_n5727 i_ce xv[18][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$28111 +001 1 +010 1 +011 1 +.names i_ce yv[17][20] xv[17][16] $abc$30358$new_n5725 $abc$30358$new_n5701 $abc$30358$new_n5727 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5729 xv[18][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$28113 +001 1 +011 1 +110 1 +111 1 +.names xv[17][15] xv[17][14] $abc$30358$new_n5731 $abc$30358$new_n5730 $abc$30358$new_n5729 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[17][12] xv[17][13] $abc$30358$new_n5714 $abc$30358$new_n5730 +110 1 +.names xv[17][12] xv[17][13] $abc$30358$new_n5702 $abc$30358$new_n5731 +110 1 +.names i_ce $abc$30358$new_n5735 xv[18][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$28117 +001 1 +011 1 +110 1 +111 1 +.names xv[17][13] yv[17][20] xv[17][12] $abc$30358$new_n5715 $abc$30358$new_n5703 $abc$30358$new_n5735 +00101 1 +00111 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5737 i_ce xv[18][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28119 +001 1 +010 1 +011 1 +.names i_ce xv[17][12] yv[17][20] $abc$30358$new_n5703 $abc$30358$new_n5714 $abc$30358$new_n5737 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[17][11] xv[17][10] $abc$30358$new_n5739 xv[18][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$28121 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[17][9] yv[17][20] $abc$30358$new_n5704 $abc$30358$new_n5716 $abc$30358$new_n5739 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce xv[17][10] $abc$30358$new_n5739 xv[18][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$28123 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5742 xv[18][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$28125 +001 1 +011 1 +110 1 +111 1 +.names yv[17][20] xv[17][9] $abc$30358$new_n5716 $abc$30358$new_n5704 $abc$30358$new_n5742 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5747 xv[18][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$28129 +001 1 +011 1 +110 1 +111 1 +.names xv[17][7] xv[17][6] $abc$30358$new_n5717 $abc$30358$new_n6098 $abc$30358$new_n5747 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names i_ce xv[17][5] xv[17][4] $abc$30358$new_n5751 xv[18][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$28133 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[17][3] xv[17][2] yv[17][20] $abc$30358$new_n5707 $abc$30358$new_n5719 $abc$30358$new_n5751 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce yv[17][20] xv[17][4] $abc$30358$new_n5753 xv[18][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$28135 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[17][20] xv[17][2] xv[17][3] $abc$30358$new_n5707 $abc$30358$new_n5719 $abc$30358$new_n5753 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n5755 xv[18][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$28137 +001 1 +011 1 +110 1 +111 1 +.names xv[17][3] yv[17][20] xv[17][2] $abc$30358$new_n5719 $abc$30358$new_n5707 $abc$30358$new_n5755 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5757 i_ce xv[18][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$28139 +001 1 +010 1 +011 1 +.names i_ce yv[17][20] xv[17][2] $abc$30358$new_n5719 $abc$30358$new_n5707 $abc$30358$new_n5757 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5759 xv[18][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$28141 +001 1 +011 1 +110 1 +111 1 +.names xv[17][1] yv[17][19] yv[17][20] xv[17][0] yv[17][18] $abc$30358$new_n5759 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[17][0] yv[17][18] xv[18][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$28143 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[17][20] $abc$30358$new_n5762 xv[18][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28145 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names xv[17][18] xv[17][19] $abc$30358$new_n5712 yv[17][20] $abc$30358$new_n5700 $abc$30358$new_n5762 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5766 ph[18][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28147 +001 1 +011 1 +100 1 +101 1 +.names ph[17][20] yv[17][20] ph[17][19] $abc$30358$new_n5628 $abc$30358$new_n5766 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[16][20] $abc$30358$new_n5768 xv[17][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28149 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[16][17] xv[16][18] xv[16][19] $abc$30358$new_n5593 $abc$30358$new_n5768 +1111 1 +.names i_ce yv[16][20] yv[17][20] $abc$30358$new_n5770 $abc$30358$new_n5773 $abc$30358$auto$rtlil.cc:2693:MuxGate$28151 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names xv[16][20] yv[16][19] $abc$30358$new_n5771 $abc$30358$new_n5772 $abc$30358$new_n5770 +0001 1 +1110 1 +1111 1 +.names xv[16][20] yv[16][16] yv[16][17] yv[16][18] $abc$30358$new_n5552 $abc$30358$new_n5771 +00000 1 +11110 1 +.names yv[16][16] yv[16][17] yv[16][18] $abc$30358$new_n5772 +000 1 +.names xv[16][20] yv[16][19] $abc$30358$new_n6084 yv[16][18] $abc$30358$new_n5772 $abc$30358$new_n5773 +01110 1 +01111 1 +10001 1 +10011 1 +.names i_ce $abc$30358$new_n5775 ph[17][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28153 +001 1 +011 1 +100 1 +101 1 +.names ph[16][20] yv[16][20] ph[16][19] $abc$30358$new_n5484 $abc$30358$new_n5775 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[15][20] xv[15][19] $abc$30358$new_n5417 xv[16][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28155 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[15][20] yv[16][20] $abc$30358$new_n5778 $abc$30358$new_n5781 $abc$30358$auto$rtlil.cc:2693:MuxGate$28157 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names xv[15][20] yv[15][19] $abc$30358$new_n5779 $abc$30358$new_n5780 $abc$30358$new_n5778 +0001 1 +1110 1 +1111 1 +.names xv[15][20] yv[15][16] yv[15][17] yv[15][18] $abc$30358$new_n5366 $abc$30358$new_n5779 +00000 1 +11110 1 +.names yv[15][16] yv[15][17] yv[15][18] $abc$30358$new_n5780 +000 1 +.names xv[15][20] yv[15][19] $abc$30358$new_n5350 yv[15][18] $abc$30358$new_n5780 $abc$30358$new_n5781 +01110 1 +01111 1 +10001 1 +10011 1 +.names i_ce ph[15][20] $abc$30358$new_n5783 ph[16][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28159 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[15][20] ph[15][19] $abc$30358$new_n5293 $abc$30358$new_n5783 +010 1 +100 1 +.names i_ce xv[14][20] $abc$30358$new_n5785 xv[15][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28161 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names xv[14][19] $abc$30358$new_n5243 yv[14][20] $abc$30358$new_n5231 $abc$30358$new_n5785 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names i_ce $abc$30358$new_n5796 ph[15][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28165 +001 1 +011 1 +100 1 +101 1 +.names ph[14][20] yv[14][20] ph[14][19] $abc$30358$new_n5111 $abc$30358$new_n5796 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names i_ce xv[13][20] $abc$30358$new_n5798 xv[14][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28167 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[13][19] $abc$30358$new_n5060 $abc$30358$new_n5048 yv[13][20] $abc$30358$new_n5798 +1000 1 +1010 1 +1011 1 +.names i_ce $abc$30358$new_n5809 ph[14][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28171 +001 1 +011 1 +100 1 +101 1 +.names ph[13][20] yv[13][20] ph[13][19] $abc$30358$new_n4931 $abc$30358$new_n5809 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[12][20] xv[12][19] $abc$30358$new_n4867 xv[13][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28173 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5821 ph[13][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28177 +001 1 +011 1 +100 1 +101 1 +.names ph[12][20] yv[12][20] ph[12][19] $abc$30358$new_n4749 $abc$30358$new_n5821 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names i_ce xv[11][20] $abc$30358$new_n5823 xv[12][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28179 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[11][19] $abc$30358$new_n4697 yv[11][20] $abc$30358$new_n4686 xv[11][18] $abc$30358$new_n5823 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce $abc$30358$new_n5834 ph[12][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28183 +001 1 +011 1 +100 1 +101 1 +.names ph[11][20] yv[11][20] ph[11][19] $abc$30358$new_n4564 $abc$30358$new_n5834 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[10][20] $abc$30358$new_n5836 xv[11][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28185 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[10][19] $abc$30358$new_n4514 $abc$30358$new_n4503 $abc$30358$new_n5836 +100 1 +.names i_ce yv[11][20] $abc$30358$new_n6127 $abc$30358$new_n5842 $abc$30358$auto$rtlil.cc:2693:MuxGate$28187 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n4449 xv[10][20] yv[10][19] yv[10][18] $abc$30358$new_n5842 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5846 ph[11][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28189 +001 1 +011 1 +100 1 +101 1 +.names ph[10][20] yv[10][20] ph[10][19] $abc$30358$new_n4382 $abc$30358$new_n5846 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[9][20] $abc$30358$new_n5848 xv[10][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28191 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[9][19] $abc$30358$new_n4330 yv[9][20] $abc$30358$new_n4320 xv[9][18] $abc$30358$new_n5848 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce yv[10][20] $abc$30358$new_n5853 $abc$30358$new_n6129 $abc$30358$auto$rtlil.cc:2693:MuxGate$28193 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n4269 xv[9][20] yv[9][18] yv[9][19] $abc$30358$new_n5853 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5857 ph[10][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28195 +001 1 +011 1 +100 1 +101 1 +.names ph[9][20] yv[9][20] ph[9][19] $abc$30358$new_n4200 $abc$30358$new_n5857 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names xv[8][18] xv[8][19] $abc$30358$new_n5860 +11 1 +.names i_ce ph[8][20] $abc$30358$new_n4018 $abc$30358$new_n5871 ph[9][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28201 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[8][20] ph[8][19] $abc$30358$new_n5871 +00 1 +11 1 +.names i_ce xv[7][20] $abc$30358$new_n5873 xv[8][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28203 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[7][19] $abc$30358$new_n3969 yv[7][20] $abc$30358$new_n3955 xv[7][18] $abc$30358$new_n5873 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce ph[7][20] $abc$30358$new_n5884 ph[8][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28207 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[7][20] ph[7][19] $abc$30358$new_n3837 $abc$30358$new_n5884 +010 1 +100 1 +.names i_ce xv[6][20] $abc$30358$new_n5886 xv[7][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28209 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5887 yv[6][20] xv[6][16] xv[6][17] $abc$30358$new_n3770 $abc$30358$new_n5886 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][19] xv[6][18] $abc$30358$new_n3780 yv[6][20] $abc$30358$new_n5887 +1100 1 +1101 1 +1110 1 +.names $abc$30358$new_n3719 xv[6][20] yv[6][18] yv[6][19] $abc$30358$new_n5894 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5898 ph[7][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28213 +001 1 +011 1 +100 1 +101 1 +.names ph[6][20] yv[6][20] ph[6][19] $abc$30358$new_n3654 $abc$30358$new_n5898 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[5][20] $abc$30358$new_n5900 xv[6][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28215 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5902 yv[5][20] $abc$30358$new_n3599 xv[5][17] $abc$30358$new_n5901 $abc$30358$new_n5900 +10011 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][16] xv[5][14] xv[5][15] $abc$30358$new_n3590 $abc$30358$new_n5901 +1111 1 +.names xv[5][18] xv[5][19] $abc$30358$new_n5902 +11 1 +.names i_ce yv[6][20] $abc$30358$new_n6150 $abc$30358$new_n6152 $abc$30358$auto$rtlil.cc:2693:MuxGate$28217 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n5912 ph[6][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28219 +001 1 +011 1 +100 1 +101 1 +.names ph[5][20] yv[5][20] ph[5][19] $abc$30358$new_n3475 $abc$30358$new_n5912 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names i_ce xv[4][20] $abc$30358$new_n5914 xv[5][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28221 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[4][19] $abc$30358$new_n3415 $abc$30358$new_n3424 yv[4][20] $abc$30358$new_n5914 +1000 1 +1010 1 +1011 1 +.names i_ce yv[5][20] $abc$30358$new_n5916 $abc$30358$new_n6154 $abc$30358$auto$rtlil.cc:2693:MuxGate$28223 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n3352 xv[4][20] yv[4][19] yv[4][18] $abc$30358$new_n5916 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5924 ph[5][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28225 +001 1 +011 1 +100 1 +101 1 +.names ph[4][20] yv[4][20] ph[4][19] $abc$30358$new_n3298 $abc$30358$new_n5924 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[3][20] $abc$30358$new_n5926 xv[4][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28227 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[3][19] $abc$30358$new_n3249 $abc$30358$new_n3240 $abc$30358$new_n5926 +100 1 +.names i_ce yv[4][20] $abc$30358$new_n6156 $abc$30358$new_n5932 $abc$30358$auto$rtlil.cc:2693:MuxGate$28229 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n3170 xv[3][20] yv[3][19] yv[3][18] $abc$30358$new_n5932 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5935 ph[4][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28231 +001 1 +011 1 +100 1 +101 1 +.names ph[3][20] ph[3][19] $abc$30358$new_n3122 $abc$30358$new_n3116 $abc$30358$new_n5935 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce xv[2][20] $abc$30358$new_n5937 xv[3][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28233 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[2][19] xv[2][18] yv[2][20] $abc$30358$new_n3055 $abc$30358$new_n3064 $abc$30358$new_n5937 +11010 1 +11011 1 +11101 1 +11111 1 +.names yv[2][19] xv[2][20] yv[2][18] $abc$30358$new_n2986 $abc$30358$new_n5939 +0001 1 +1110 1 +.names i_ce $abc$30358$new_n5944 ph[3][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28237 +001 1 +011 1 +100 1 +101 1 +.names ph[2][20] yv[2][20] ph[2][19] $abc$30358$new_n2932 $abc$30358$new_n5944 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[1][20] $abc$30358$new_n5946 xv[2][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28239 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[1][19] xv[1][18] yv[1][20] $abc$30358$new_n2873 $abc$30358$new_n2882 $abc$30358$new_n5946 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[1][20] yv[1][18] yv[1][19] $abc$30358$new_n2804 $abc$30358$new_n5950 +10001 1 +11110 1 +.names i_ce $abc$30358$new_n5953 ph[2][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28243 +001 1 +011 1 +100 1 +101 1 +.names ph[1][20] ph[1][19] yv[1][20] $abc$30358$new_n2766 $abc$30358$new_n5953 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[0][20] xv[0][19] $abc$30358$new_n2709 xv[1][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28245 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[0][20] $abc$30358$new_n5959 $abc$30358$new_n5956 yv[1][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28247 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n5958 xv[0][19] yv[0][18] $abc$30358$new_n2640 $abc$30358$new_n5957 $abc$30358$new_n5956 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][20] yv[0][19] $abc$30358$new_n5957 +11 1 +.names yv[0][20] yv[0][19] xv[0][20] $abc$30358$new_n5958 +101 1 +110 1 +111 1 +.names yv[0][20] yv[0][19] xv[0][20] $abc$30358$new_n2649 $abc$30358$new_n5959 +0000 1 +0100 1 +0101 1 +0110 1 +.names i_ce $abc$30358$new_n5961 o_mag[12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28249 +001 1 +011 1 +110 1 +111 1 +.names xv[18][20] xv[18][18] xv[18][19] $abc$30358$new_n2619 $abc$30358$new_n5961 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[18][20] o_phase[20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28251 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[18] o_aux $abc$30358$auto$rtlil.cc:2693:MuxGate$28253 +001 1 +011 1 +110 1 +111 1 +.names xv[0][20] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28255 +10 1 +.names $abc$30358$new_n6162 yv[0][20] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28257 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ax[17] ax[18] $abc$30358$auto$rtlil.cc:2693:MuxGate$28259 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_yval[12] ph[0][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28261 +001 1 +011 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5969 ph[1][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28263 +001 1 +011 1 +100 1 +101 1 +.names ph[0][20] yv[0][20] ph[0][18] ph[0][19] $abc$30358$new_n5969 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_yval[11] i_xval[11] i_xval[12] $abc$30358$new_n2460 $abc$30358$new_n2467 $abc$30358$new_n5970 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_xval[12] $abc$30358$new_n2532 $abc$30358$new_n2464 i_yval[12] $abc$30358$new_n2531 $abc$30358$new_n5972 +00011 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5972 i_yval[12] $abc$30358$new_n2533 $abc$30358$new_n2535 $abc$30358$new_n5973 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +.names i_ce $abc$30358$new_n5973 yv[0][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$25911 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[0][18] $abc$30358$new_n6164 $abc$30358$new_n2563 $abc$30358$auto$rtlil.cc:2693:MuxGate$25933 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names yv[1][20] xv[1][18] $abc$30358$new_n2873 $abc$30358$new_n2882 $abc$30358$new_n5980 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n5980 xv[2][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26197 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] xv[1][16] yv[1][18] $abc$30358$new_n2883 $abc$30358$new_n2874 $abc$30358$new_n5982 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce xv[1][17] $abc$30358$new_n5982 yv[1][19] xv[2][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26199 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][18] $abc$30358$new_n3055 $abc$30358$new_n3064 $abc$30358$new_n5984 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n5984 xv[3][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26317 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][12] yv[2][15] $abc$30358$new_n3067 $abc$30358$new_n3058 $abc$30358$new_n5986 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce xv[2][13] $abc$30358$new_n5986 yv[2][16] xv[3][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26327 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][10] yv[2][13] $abc$30358$new_n3068 $abc$30358$new_n3059 $abc$30358$new_n5988 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_ce xv[2][11] $abc$30358$new_n5988 yv[2][14] xv[3][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26331 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] ph[3][13] ph[3][14] $abc$30358$new_n3118 $abc$30358$new_n3124 $abc$30358$new_n5990 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n5990 ph[3][15] ph[4][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26363 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[3][17] xv[3][16] yv[3][20] $abc$30358$new_n3250 $abc$30358$new_n3241 $abc$30358$new_n5992 +11001 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5992 xv[3][18] xv[4][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26437 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[3][20] xv[3][10] yv[3][14] $abc$30358$new_n3253 $abc$30358$new_n3244 $abc$30358$new_n5994 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_ce xv[3][11] $abc$30358$new_n5994 yv[3][15] xv[4][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26451 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[4][17] xv[4][16] yv[4][20] $abc$30358$new_n3425 $abc$30358$new_n3416 $abc$30358$new_n5996 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5996 xv[4][18] xv[5][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26557 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[4][20] xv[4][12] yv[4][17] $abc$30358$new_n3427 $abc$30358$new_n3418 $abc$30358$new_n5998 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce xv[4][13] $abc$30358$new_n5998 yv[4][18] xv[5][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26567 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] xv[4][10] yv[4][15] $abc$30358$new_n3428 $abc$30358$new_n3419 $abc$30358$new_n6000 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_ce xv[4][11] $abc$30358$new_n6000 yv[4][16] xv[5][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26571 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][16] yv[5][10] $abc$30358$new_n3534 $abc$30358$new_n3543 $abc$30358$new_n6002 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[5][17] $abc$30358$new_n6002 yv[5][11] yv[6][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26651 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] $abc$30358$new_n3599 xv[5][17] xv[5][16] $abc$30358$new_n3589 $abc$30358$new_n6004 +00110 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[5][19] $abc$30358$new_n6004 xv[5][18] xv[6][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26675 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] $abc$30358$new_n3599 xv[5][17] xv[5][16] $abc$30358$new_n3589 $abc$30358$new_n6006 +00110 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6006 xv[5][18] xv[6][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26677 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[6][20] xv[6][20] $abc$30358$new_n3712 yv[6][14] $abc$30358$new_n3737 $abc$30358$new_n6008 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6008 yv[6][15] yv[7][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26763 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[6][20] $abc$30358$new_n3780 xv[6][17] xv[6][16] $abc$30358$new_n3770 $abc$30358$new_n6010 +00110 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce xv[6][19] $abc$30358$new_n6010 xv[6][18] xv[7][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26795 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] $abc$30358$new_n3780 xv[6][17] xv[6][16] $abc$30358$new_n3770 $abc$30358$new_n6012 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6012 xv[6][18] xv[7][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26797 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[7][20] ph[7][13] ph[7][12] $abc$30358$new_n3841 $abc$30358$new_n3847 $abc$30358$new_n6014 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6014 ph[8][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26847 +001 1 +011 1 +110 1 +111 1 +.names yv[7][20] $abc$30358$new_n3955 xv[7][16] xv[7][17] $abc$30358$new_n3970 $abc$30358$new_n6016 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names i_ce $abc$30358$new_n6016 xv[7][18] xv[8][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26917 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[7][17] yv[7][20] xv[7][16] $abc$30358$new_n3956 $abc$30358$new_n3984 $abc$30358$new_n6018 +00100 1 +00101 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n6018 xv[8][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26919 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] ph[8][15] ph[8][14] $abc$30358$new_n4021 $abc$30358$new_n4029 $abc$30358$new_n6020 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6020 ph[9][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26963 +001 1 +011 1 +110 1 +111 1 +.names xv[8][17] xv[8][16] yv[8][20] $abc$30358$new_n4150 $abc$30358$new_n4139 $abc$30358$new_n6022 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce xv[8][19] $abc$30358$new_n6022 xv[8][18] xv[9][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27035 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[8][17] xv[8][16] yv[8][20] $abc$30358$new_n4150 $abc$30358$new_n4139 $abc$30358$new_n6024 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6024 xv[8][18] xv[9][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27037 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[9][20] ph[9][15] ph[9][14] $abc$30358$new_n4212 $abc$30358$new_n4204 $abc$30358$new_n6026 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6026 ph[10][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27083 +001 1 +011 1 +110 1 +111 1 +.names yv[9][20] $abc$30358$new_n4213 ph[9][12] $abc$30358$new_n4209 $abc$30358$new_n4205 $abc$30358$new_n6028 +00011 1 +00111 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n6028 ph[9][13] ph[10][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27087 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[9][17] xv[9][16] yv[9][20] $abc$30358$new_n4331 $abc$30358$new_n4321 $abc$30358$new_n6030 +11001 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6030 xv[9][18] xv[10][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27157 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[9][20] xv[9][14] $abc$30358$new_n4322 xv[9][13] $abc$30358$new_n4348 $abc$30358$new_n6032 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n6032 xv[10][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27165 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n4333 yv[9][20] xv[9][10] xv[9][11] $abc$30358$new_n4323 $abc$30358$new_n6034 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce xv[9][13] $abc$30358$new_n6034 xv[9][12] xv[10][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27167 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] $abc$30358$new_n4333 xv[9][11] xv[9][10] $abc$30358$new_n4323 $abc$30358$new_n6036 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6036 xv[9][12] xv[10][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27169 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$30358$new_n4447 yv[10][20] $abc$30358$new_n4470 $abc$30358$new_n4468 $abc$30358$new_n6038 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n6038 yv[11][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27245 +001 1 +011 1 +110 1 +111 1 +.names xv[10][17] xv[10][16] yv[10][20] $abc$30358$new_n4514 $abc$30358$new_n4504 $abc$30358$new_n6040 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6040 xv[10][18] xv[11][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27277 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[10][16] $abc$30358$new_n4527 $abc$30358$new_n4514 xv[11][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27281 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][14] $abc$30358$new_n4515 $abc$30358$new_n4505 xv[11][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27285 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[10][12] $abc$30358$new_n4516 $abc$30358$new_n4506 xv[11][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27289 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[11][10] yv[11][11] yv[11][12] yv[11][13] yv[11][15] $abc$30358$new_n6045 +00000 1 +11111 1 +.names xv[11][20] $abc$30358$new_n4636 $abc$30358$new_n6045 yv[11][14] yv[11][15] $abc$30358$new_n6046 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[11][17] xv[11][16] yv[11][20] $abc$30358$new_n4699 $abc$30358$new_n4687 $abc$30358$new_n6047 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6047 xv[11][18] xv[12][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27397 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[11][14] $abc$30358$new_n4717 $abc$30358$new_n4718 xv[12][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27405 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[11][12] $abc$30358$new_n4701 $abc$30358$new_n4688 xv[12][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27409 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[12][10] yv[12][11] yv[12][12] yv[12][13] yv[12][15] $abc$30358$new_n6051 +00000 1 +11111 1 +.names xv[12][20] $abc$30358$new_n4802 $abc$30358$new_n6051 yv[12][14] yv[12][15] $abc$30358$new_n6052 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][20] yv[12][16] $abc$30358$new_n6052 $abc$30358$new_n4814 $abc$30358$new_n6053 +00010 1 +00011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n6053 yv[12][17] yv[13][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27479 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n4882 xv[12][11] xv[12][9] xv[12][10] xv[12][8] $abc$30358$new_n6055 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n6055 xv[12][11] yv[12][20] $abc$30358$new_n6056 +000 1 +001 1 +101 1 +111 1 +.names yv[12][20] xv[12][18] $abc$30358$new_n4889 $abc$30358$new_n4869 $abc$30358$new_n4878 $abc$30358$new_n6057 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n6057 xv[13][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27517 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[12][12] $abc$30358$new_n6056 $abc$30358$new_n4871 xv[13][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27529 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[12][8] yv[12][20] xv[12][7] $abc$30358$new_n4873 $abc$30358$new_n4883 $abc$30358$new_n6060 +00100 1 +00101 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n6060 xv[13][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27537 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n4988 yv[13][12] yv[13][13] yv[13][14] yv[13][15] $abc$30358$new_n6062 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n6062 yv[13][15] xv[13][20] $abc$30358$new_n6063 +000 1 +001 1 +100 1 +110 1 +.names $abc$30358$new_n5053 xv[13][11] xv[13][9] xv[13][10] xv[13][8] $abc$30358$new_n6064 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n6064 xv[13][11] yv[13][20] $abc$30358$new_n6065 +000 1 +001 1 +101 1 +111 1 +.names yv[13][20] xv[13][9] xv[13][10] xv[13][11] xv[13][14] $abc$30358$new_n6066 +01111 1 +10000 1 +.names $abc$30358$new_n5070 $abc$30358$new_n5064 $abc$30358$new_n6066 xv[13][15] xv[13][16] $abc$30358$new_n6067 +11111 1 +.names yv[13][20] xv[13][18] $abc$30358$new_n6067 xv[13][17] $abc$30358$new_n5049 $abc$30358$new_n6068 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n6068 xv[14][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27637 +001 1 +011 1 +110 1 +111 1 +.names xv[13][13] xv[13][12] yv[13][20] $abc$30358$new_n6065 $abc$30358$new_n5063 $abc$30358$new_n6070 +11001 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6070 xv[13][14] xv[14][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27645 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[13][6] xv[13][7] yv[13][20] $abc$30358$new_n5054 $abc$30358$new_n5065 $abc$30358$new_n6072 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6072 xv[13][8] xv[14][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27657 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[14][20] xv[14][18] $abc$30358$new_n5230 $abc$30358$new_n5244 $abc$30358$new_n6074 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n6074 xv[15][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27757 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[14][8] $abc$30358$new_n5248 $abc$30358$new_n5235 xv[15][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27777 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5433 xv[15][11] xv[15][9] xv[15][10] xv[15][8] $abc$30358$new_n6077 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n6077 xv[15][11] yv[15][20] $abc$30358$new_n6078 +000 1 +001 1 +101 1 +111 1 +.names yv[15][20] xv[15][18] $abc$30358$new_n5418 $abc$30358$new_n5429 $abc$30358$new_n6079 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n6079 xv[16][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27877 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[15][12] $abc$30358$new_n6078 $abc$30358$new_n5421 xv[16][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27889 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[16][12] yv[16][13] yv[16][14] yv[16][15] yv[16][17] $abc$30358$new_n6082 +00000 1 +11111 1 +.names yv[16][17] yv[16][16] xv[16][20] $abc$30358$new_n6082 $abc$30358$new_n5542 $abc$30358$new_n6083 +00100 1 +00101 1 +00110 1 +11010 1 +.names $abc$30358$new_n5549 $abc$30358$new_n6083 xv[16][20] yv[16][17] yv[16][16] $abc$30358$new_n6084 +00100 1 +01100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n6088 xv[16][8] xv[16][9] xv[16][10] xv[16][11] $abc$30358$new_n6085 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n6085 xv[16][11] yv[16][20] $abc$30358$new_n6086 +000 1 +001 1 +101 1 +111 1 +.names $abc$30358$new_n5570 xv[16][7] xv[16][5] xv[16][6] xv[16][4] $abc$30358$new_n6087 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n6087 xv[16][7] yv[16][20] $abc$30358$new_n6088 +000 1 +001 1 +101 1 +111 1 +.names xv[16][16] xv[16][17] yv[16][20] $abc$30358$new_n5565 $abc$30358$new_n5581 $abc$30358$new_n6089 +11000 1 +11010 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6089 xv[16][18] xv[17][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27997 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][14] $abc$30358$new_n5582 $abc$30358$new_n5598 xv[17][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$28005 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[16][12] $abc$30358$new_n6086 $abc$30358$new_n5583 xv[17][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28009 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[16][8] $abc$30358$new_n5585 $abc$30358$new_n6088 xv[17][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$28017 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[16][4] $abc$30358$new_n5587 $abc$30358$new_n5571 xv[17][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$28025 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[17][20] ph[17][18] ph[17][17] $abc$30358$new_n5629 $abc$30358$new_n5635 $abc$30358$new_n6095 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6095 ph[18][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$28037 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n5707 xv[17][2] xv[17][3] xv[17][4] xv[17][5] $abc$30358$new_n6097 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n6097 xv[17][5] yv[17][20] $abc$30358$new_n6098 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[17][14] $abc$30358$new_n5731 $abc$30358$new_n5730 xv[18][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$28115 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[17][6] xv[17][7] yv[17][20] $abc$30358$new_n5717 $abc$30358$new_n6098 $abc$30358$new_n6100 +11000 1 +11010 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6100 xv[17][8] xv[18][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$28127 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[17][6] $abc$30358$new_n5717 $abc$30358$new_n6098 xv[18][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$28131 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[14][20] yv[14][16] yv[14][17] yv[14][18] yv[14][19] $abc$30358$new_n6103 +00000 1 +11111 1 +.names $abc$30358$new_n6103 $abc$30358$new_n5166 yv[14][19] $abc$30358$new_n6107 $abc$30358$new_n6104 +0001 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n6104 yv[15][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28163 +001 1 +011 1 +110 1 +111 1 +.names xv[14][20] yv[14][18] yv[14][19] yv[14][16] yv[14][17] $abc$30358$new_n6106 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[14][20] $abc$30358$new_n5177 yv[14][19] $abc$30358$new_n6106 $abc$30358$new_n6107 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[13][20] yv[13][16] yv[13][17] yv[13][18] yv[13][19] $abc$30358$new_n6108 +01111 1 +10000 1 +.names xv[13][20] yv[13][16] yv[13][17] yv[13][18] yv[13][19] $abc$30358$new_n6110 +00000 1 +11111 1 +.names xv[12][20] yv[12][18] yv[12][19] yv[12][16] yv[12][17] $abc$30358$new_n6114 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names xv[12][20] yv[12][16] yv[12][17] yv[12][18] yv[12][19] $abc$30358$new_n6116 +00000 1 +11111 1 +.names xv[11][20] yv[11][16] yv[11][17] yv[11][18] yv[11][19] $abc$30358$new_n6120 +01111 1 +10000 1 +.names xv[11][20] yv[11][16] yv[11][17] yv[11][18] yv[11][19] $abc$30358$new_n6122 +00000 1 +11111 1 +.names xv[10][20] yv[10][18] yv[10][19] yv[10][16] yv[10][17] $abc$30358$new_n6126 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[10][20] $abc$30358$new_n4434 yv[10][19] $abc$30358$new_n6126 $abc$30358$new_n6127 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[9][20] yv[9][16] yv[9][17] yv[9][18] yv[9][19] $abc$30358$new_n6128 +01111 1 +10000 1 +.names yv[9][20] $abc$30358$new_n4260 yv[9][19] $abc$30358$new_n6128 $abc$30358$new_n6129 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$30358$new_n5860 xv[8][16] yv[8][20] $abc$30358$new_n4150 $abc$30358$new_n4139 $abc$30358$new_n6130 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce xv[8][20] $abc$30358$new_n6130 xv[8][17] xv[9][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28197 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[8][20] yv[8][16] yv[8][17] yv[8][18] yv[8][19] $abc$30358$new_n6132 +01111 1 +10000 1 +.names xv[8][20] yv[8][16] yv[8][17] yv[8][18] yv[8][19] $abc$30358$new_n6134 +00000 1 +11111 1 +.names xv[7][20] yv[7][16] yv[7][17] yv[7][18] yv[7][19] $abc$30358$new_n6138 +01111 1 +10000 1 +.names xv[7][20] yv[7][16] yv[7][17] yv[7][18] yv[7][19] $abc$30358$new_n6140 +00000 1 +11111 1 +.names xv[6][20] yv[6][14] yv[6][15] yv[6][16] yv[6][19] $abc$30358$new_n6144 +01111 1 +10000 1 +.names $abc$30358$new_n6144 $abc$30358$new_n3712 yv[6][17] yv[6][18] yv[6][19] $abc$30358$new_n6145 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[6][20] $abc$30358$new_n6145 $abc$30358$new_n6146 +11 1 +.names xv[5][20] yv[5][18] yv[5][19] yv[5][16] yv[5][17] $abc$30358$new_n6149 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[5][20] $abc$30358$new_n3539 yv[5][19] $abc$30358$new_n6149 $abc$30358$new_n6150 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[5][20] yv[5][16] yv[5][17] yv[5][18] yv[5][19] $abc$30358$new_n6151 +00000 1 +11111 1 +.names $abc$30358$new_n6151 $abc$30358$new_n3531 yv[5][19] $abc$30358$new_n6152 +101 1 +110 1 +.names xv[4][20] yv[4][18] yv[4][19] yv[4][16] yv[4][17] $abc$30358$new_n6153 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[4][20] $abc$30358$new_n3363 yv[4][19] $abc$30358$new_n6153 $abc$30358$new_n6154 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[3][20] yv[3][18] yv[3][19] yv[3][16] yv[3][17] $abc$30358$new_n6155 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[3][20] $abc$30358$new_n3189 yv[3][19] $abc$30358$new_n6155 $abc$30358$new_n6156 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[2][20] $abc$30358$new_n3003 yv[2][19] yv[2][18] yv[2][20] $abc$30358$new_n6157 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce yv[3][20] $abc$30358$new_n6157 $abc$30358$new_n5939 $abc$30358$auto$rtlil.cc:2693:MuxGate$28235 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$30358$new_n2821 xv[1][20] yv[1][19] yv[1][18] yv[1][20] $abc$30358$new_n6159 +00001 1 +00011 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n5950 $abc$30358$new_n6159 yv[2][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28241 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_xval[12] $abc$30358$new_n2425 $abc$30358$new_n2442 i_yval[11] i_xval[11] $abc$30358$new_n6161 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +.names i_ce i_yval[12] $abc$30358$new_n2444 $abc$30358$new_n5970 $abc$30358$new_n6161 $abc$30358$new_n6162 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[11] i_xval[11] i_yval[12] $abc$30358$new_n2460 $abc$30358$new_n2467 $abc$30358$new_n6163 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2476 $abc$30358$new_n2454 $abc$30358$new_n6163 $abc$30358$new_n6164 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_yval[1] i_yval[0] i_xval[0] i_xval[12] i_yval[12] $abc$30358$new_n6165 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11101 1 +11110 1 +.names i_ce i_xval[1] $abc$30358$new_n6165 xv[0][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$25955 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[13][20] yv[13][19] $abc$30358$new_n6108 $abc$30358$new_n6063 $abc$30358$new_n4997 $abc$30358$new_n6169 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6169 yv[13][20] yv[14][20] $abc$30358$new_n6110 $abc$30358$auto$rtlil.cc:2693:MuxGate$28169 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names yv[12][20] yv[12][19] $abc$30358$new_n6114 $abc$30358$new_n4813 $abc$30358$new_n6052 $abc$30358$new_n6173 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6173 yv[12][20] yv[13][20] $abc$30358$new_n6116 $abc$30358$auto$rtlil.cc:2693:MuxGate$28175 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names yv[11][20] yv[11][19] $abc$30358$new_n6120 $abc$30358$new_n4619 $abc$30358$new_n6046 $abc$30358$new_n6177 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6177 yv[11][20] yv[12][20] $abc$30358$new_n6122 $abc$30358$auto$rtlil.cc:2693:MuxGate$28181 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names yv[8][20] yv[8][19] $abc$30358$new_n6132 $abc$30358$new_n4088 $abc$30358$new_n4075 $abc$30358$new_n6181 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6181 yv[8][20] yv[9][20] $abc$30358$new_n6134 $abc$30358$auto$rtlil.cc:2693:MuxGate$28199 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names yv[7][20] yv[7][19] $abc$30358$new_n6138 $abc$30358$new_n3891 $abc$30358$new_n3904 $abc$30358$new_n6185 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6185 yv[7][20] yv[8][20] $abc$30358$new_n6140 $abc$30358$auto$rtlil.cc:2693:MuxGate$28205 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names i_ce yv[7][20] $abc$30358$new_n6146 $abc$30358$new_n5894 $abc$30358$auto$rtlil.cc:2693:MuxGate$28211 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28143 Q=xv[18][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28141 Q=xv[18][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28139 Q=xv[18][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28137 Q=xv[18][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28135 Q=xv[18][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28133 Q=xv[18][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28131 Q=xv[18][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28129 Q=xv[18][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28127 Q=xv[18][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28125 Q=xv[18][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28123 Q=xv[18][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28121 Q=xv[18][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28119 Q=xv[18][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28117 Q=xv[18][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28115 Q=xv[18][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28113 Q=xv[18][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28111 Q=xv[18][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28109 Q=xv[18][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28107 Q=xv[18][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28105 Q=xv[18][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28145 Q=xv[18][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28103 Q=ph[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28101 Q=ph[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28099 Q=ph[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28097 Q=ph[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28095 Q=ph[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28093 Q=ph[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28091 Q=ph[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28089 Q=ph[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28087 Q=ph[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28085 Q=ph[1][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28083 Q=ph[1][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28081 Q=ph[1][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28079 Q=ph[1][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28263 Q=ph[1][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28077 Q=ph[0][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28075 Q=ph[0][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28261 Q=ph[0][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28073 Q=ph[18][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28071 Q=ph[18][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28069 Q=ph[18][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28067 Q=ph[18][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28065 Q=ph[18][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28063 Q=ph[18][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28061 Q=ph[18][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28059 Q=ph[18][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28057 Q=ph[18][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28055 Q=ph[18][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28053 Q=ph[18][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28051 Q=ph[18][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28049 Q=ph[18][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28047 Q=ph[18][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28045 Q=ph[18][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28043 Q=ph[18][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28041 Q=ph[18][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28039 Q=ph[18][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28037 Q=ph[18][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28035 Q=ph[18][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28147 Q=ph[18][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28033 Q=xv[17][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28031 Q=xv[17][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28029 Q=xv[17][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28027 Q=xv[17][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28025 Q=xv[17][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28023 Q=xv[17][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28021 Q=xv[17][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28019 Q=xv[17][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28017 Q=xv[17][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28015 Q=xv[17][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28013 Q=xv[17][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28011 Q=xv[17][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28009 Q=xv[17][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28007 Q=xv[17][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28005 Q=xv[17][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28003 Q=xv[17][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28001 Q=xv[17][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27999 Q=xv[17][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27997 Q=xv[17][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27995 Q=xv[17][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28149 Q=xv[17][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27957 Q=yv[17][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27955 Q=yv[17][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28151 Q=yv[17][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27953 Q=ph[17][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27951 Q=ph[17][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27949 Q=ph[17][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27947 Q=ph[17][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27945 Q=ph[17][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27943 Q=ph[17][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27941 Q=ph[17][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27939 Q=ph[17][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27937 Q=ph[17][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27935 Q=ph[17][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27933 Q=ph[17][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27931 Q=ph[17][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27929 Q=ph[17][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27927 Q=ph[17][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27925 Q=ph[17][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27923 Q=ph[17][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27921 Q=ph[17][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27919 Q=ph[17][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27917 Q=ph[17][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27915 Q=ph[17][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28153 Q=ph[17][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27913 Q=xv[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27911 Q=xv[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27909 Q=xv[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27907 Q=xv[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27905 Q=xv[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27903 Q=xv[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27901 Q=xv[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27899 Q=xv[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27897 Q=xv[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27895 Q=xv[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27893 Q=xv[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27891 Q=xv[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27889 Q=xv[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27887 Q=xv[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27885 Q=xv[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27883 Q=xv[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27881 Q=xv[16][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27879 Q=xv[16][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27877 Q=xv[16][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27875 Q=xv[16][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28155 Q=xv[16][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27873 Q=yv[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27871 Q=yv[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27869 Q=yv[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27867 Q=yv[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27865 Q=yv[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27863 Q=yv[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27861 Q=yv[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27859 Q=yv[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27857 Q=yv[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27855 Q=yv[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27853 Q=yv[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27851 Q=yv[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27849 Q=yv[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27847 Q=yv[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27845 Q=yv[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27843 Q=yv[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27841 Q=yv[16][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27839 Q=yv[16][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27837 Q=yv[16][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27835 Q=yv[16][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28157 Q=yv[16][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27833 Q=ph[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27831 Q=ph[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27829 Q=ph[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27827 Q=ph[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27825 Q=ph[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27823 Q=ph[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27821 Q=ph[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27819 Q=ph[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27817 Q=ph[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27815 Q=ph[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27813 Q=ph[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27811 Q=ph[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27809 Q=ph[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27807 Q=ph[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27805 Q=ph[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27803 Q=ph[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27801 Q=ph[16][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27799 Q=ph[16][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27797 Q=ph[16][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27795 Q=ph[16][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28159 Q=ph[16][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27793 Q=xv[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27791 Q=xv[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27789 Q=xv[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27787 Q=xv[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27785 Q=xv[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27783 Q=xv[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27781 Q=xv[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27779 Q=xv[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27777 Q=xv[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27775 Q=xv[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27773 Q=xv[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27771 Q=xv[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27769 Q=xv[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27767 Q=xv[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27765 Q=xv[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27763 Q=xv[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27761 Q=xv[15][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27759 Q=xv[15][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27757 Q=xv[15][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27755 Q=xv[15][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28161 Q=xv[15][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27753 Q=yv[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27751 Q=yv[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27749 Q=yv[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27747 Q=yv[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27745 Q=yv[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27743 Q=yv[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27741 Q=yv[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27739 Q=yv[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27737 Q=yv[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27735 Q=yv[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27733 Q=yv[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27731 Q=yv[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27729 Q=yv[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27727 Q=yv[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27725 Q=yv[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27723 Q=yv[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27721 Q=yv[15][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27719 Q=yv[15][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27717 Q=yv[15][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27715 Q=yv[15][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28163 Q=yv[15][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27713 Q=ph[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27711 Q=ph[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27709 Q=ph[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27707 Q=ph[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27705 Q=ph[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27703 Q=ph[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27701 Q=ph[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27699 Q=ph[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27697 Q=ph[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27695 Q=ph[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27693 Q=ph[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27691 Q=ph[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27689 Q=ph[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27687 Q=ph[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27685 Q=ph[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27683 Q=ph[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27681 Q=ph[15][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27679 Q=ph[15][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27677 Q=ph[15][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27675 Q=ph[15][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28165 Q=ph[15][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27673 Q=xv[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27671 Q=xv[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27669 Q=xv[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27667 Q=xv[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27665 Q=xv[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27663 Q=xv[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27661 Q=xv[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27659 Q=xv[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27657 Q=xv[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27655 Q=xv[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27653 Q=xv[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27651 Q=xv[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27649 Q=xv[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27647 Q=xv[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27645 Q=xv[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27643 Q=xv[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27641 Q=xv[14][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27639 Q=xv[14][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27637 Q=xv[14][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27635 Q=xv[14][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28167 Q=xv[14][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27633 Q=yv[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27631 Q=yv[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27629 Q=yv[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27627 Q=yv[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27625 Q=yv[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27623 Q=yv[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27621 Q=yv[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27619 Q=yv[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27617 Q=yv[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27615 Q=yv[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27613 Q=yv[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27611 Q=yv[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27609 Q=yv[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27607 Q=yv[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27605 Q=yv[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27603 Q=yv[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27601 Q=yv[14][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27599 Q=yv[14][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27597 Q=yv[14][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27595 Q=yv[14][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28169 Q=yv[14][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27593 Q=ph[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27591 Q=ph[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27589 Q=ph[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27587 Q=ph[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27585 Q=ph[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27583 Q=ph[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27581 Q=ph[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27579 Q=ph[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27577 Q=ph[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27575 Q=ph[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27573 Q=ph[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27571 Q=ph[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27569 Q=ph[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27567 Q=ph[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27565 Q=ph[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27563 Q=ph[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27561 Q=ph[14][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27559 Q=ph[14][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27557 Q=ph[14][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27555 Q=ph[14][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28171 Q=ph[14][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27553 Q=xv[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27551 Q=xv[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27549 Q=xv[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27547 Q=xv[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27545 Q=xv[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27543 Q=xv[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27541 Q=xv[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27539 Q=xv[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27537 Q=xv[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27535 Q=xv[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27533 Q=xv[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27531 Q=xv[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27529 Q=xv[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27527 Q=xv[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27525 Q=xv[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27523 Q=xv[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27521 Q=xv[13][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27519 Q=xv[13][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27517 Q=xv[13][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27515 Q=xv[13][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28173 Q=xv[13][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27513 Q=yv[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27511 Q=yv[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27509 Q=yv[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27507 Q=yv[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27505 Q=yv[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27503 Q=yv[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27501 Q=yv[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27499 Q=yv[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27497 Q=yv[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27495 Q=yv[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27493 Q=yv[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27491 Q=yv[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27489 Q=yv[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27487 Q=yv[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27485 Q=yv[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27483 Q=yv[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27481 Q=yv[13][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27479 Q=yv[13][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27477 Q=yv[13][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27475 Q=yv[13][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28175 Q=yv[13][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27473 Q=ph[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27471 Q=ph[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27469 Q=ph[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27467 Q=ph[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27465 Q=ph[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27463 Q=ph[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27461 Q=ph[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27459 Q=ph[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27457 Q=ph[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27455 Q=ph[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27453 Q=ph[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27451 Q=ph[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27449 Q=ph[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27447 Q=ph[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27445 Q=ph[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27443 Q=ph[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27441 Q=ph[13][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27439 Q=ph[13][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27437 Q=ph[13][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27435 Q=ph[13][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28177 Q=ph[13][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27433 Q=xv[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27431 Q=xv[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27429 Q=xv[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27427 Q=xv[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27425 Q=xv[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27423 Q=xv[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27421 Q=xv[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27419 Q=xv[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27417 Q=xv[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27415 Q=xv[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27413 Q=xv[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27411 Q=xv[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27409 Q=xv[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27407 Q=xv[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27405 Q=xv[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27403 Q=xv[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27401 Q=xv[12][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27399 Q=xv[12][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27397 Q=xv[12][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27395 Q=xv[12][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28179 Q=xv[12][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27393 Q=yv[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27391 Q=yv[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27389 Q=yv[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27387 Q=yv[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27385 Q=yv[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27383 Q=yv[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27381 Q=yv[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27379 Q=yv[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27377 Q=yv[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27375 Q=yv[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27373 Q=yv[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27371 Q=yv[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27369 Q=yv[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27367 Q=yv[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27365 Q=yv[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27363 Q=yv[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27361 Q=yv[12][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27359 Q=yv[12][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27357 Q=yv[12][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27355 Q=yv[12][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28181 Q=yv[12][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27353 Q=ph[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27351 Q=ph[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27349 Q=ph[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27347 Q=ph[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27345 Q=ph[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27343 Q=ph[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27341 Q=ph[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27339 Q=ph[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27337 Q=ph[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27335 Q=ph[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27333 Q=ph[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27331 Q=ph[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27329 Q=ph[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27327 Q=ph[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27325 Q=ph[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27323 Q=ph[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27321 Q=ph[12][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27319 Q=ph[12][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27317 Q=ph[12][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27315 Q=ph[12][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28183 Q=ph[12][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27313 Q=xv[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27311 Q=xv[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27309 Q=xv[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27307 Q=xv[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27305 Q=xv[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27303 Q=xv[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27301 Q=xv[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27299 Q=xv[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27297 Q=xv[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27295 Q=xv[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27293 Q=xv[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27291 Q=xv[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27289 Q=xv[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27287 Q=xv[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27285 Q=xv[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27283 Q=xv[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27281 Q=xv[11][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27279 Q=xv[11][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27277 Q=xv[11][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27275 Q=xv[11][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28185 Q=xv[11][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27273 Q=yv[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27271 Q=yv[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27269 Q=yv[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27267 Q=yv[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27265 Q=yv[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27263 Q=yv[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27261 Q=yv[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27259 Q=yv[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27257 Q=yv[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27255 Q=yv[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27253 Q=yv[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27251 Q=yv[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27249 Q=yv[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27247 Q=yv[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27245 Q=yv[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27243 Q=yv[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27241 Q=yv[11][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27239 Q=yv[11][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27237 Q=yv[11][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27235 Q=yv[11][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28187 Q=yv[11][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27233 Q=ph[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27231 Q=ph[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27229 Q=ph[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27227 Q=ph[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27225 Q=ph[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27223 Q=ph[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27221 Q=ph[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27219 Q=ph[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27217 Q=ph[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27215 Q=ph[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27213 Q=ph[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27211 Q=ph[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27209 Q=ph[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27207 Q=ph[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27205 Q=ph[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27203 Q=ph[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27201 Q=ph[11][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27199 Q=ph[11][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27197 Q=ph[11][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27195 Q=ph[11][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28189 Q=ph[11][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27193 Q=xv[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27191 Q=xv[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27189 Q=xv[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27187 Q=xv[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27185 Q=xv[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27183 Q=xv[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27181 Q=xv[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27179 Q=xv[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27177 Q=xv[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27175 Q=xv[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27173 Q=xv[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27171 Q=xv[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27169 Q=xv[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27167 Q=xv[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27165 Q=xv[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27163 Q=xv[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27161 Q=xv[10][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27159 Q=xv[10][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27157 Q=xv[10][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27155 Q=xv[10][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28191 Q=xv[10][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27153 Q=yv[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27151 Q=yv[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27149 Q=yv[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27147 Q=yv[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27145 Q=yv[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27143 Q=yv[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27141 Q=yv[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27139 Q=yv[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27137 Q=yv[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27135 Q=yv[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27133 Q=yv[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27131 Q=yv[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27129 Q=yv[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27127 Q=yv[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27125 Q=yv[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27123 Q=yv[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27121 Q=yv[10][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27119 Q=yv[10][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27117 Q=yv[10][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27115 Q=yv[10][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28193 Q=yv[10][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27113 Q=ph[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27111 Q=ph[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27109 Q=ph[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27107 Q=ph[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27105 Q=ph[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27103 Q=ph[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27101 Q=ph[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27099 Q=ph[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27097 Q=ph[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27095 Q=ph[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27093 Q=ph[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27091 Q=ph[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27089 Q=ph[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27087 Q=ph[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27085 Q=ph[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27083 Q=ph[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27081 Q=ph[10][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27079 Q=ph[10][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27077 Q=ph[10][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27075 Q=ph[10][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28195 Q=ph[10][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27073 Q=xv[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27071 Q=xv[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27069 Q=xv[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27067 Q=xv[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27065 Q=xv[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27063 Q=xv[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27061 Q=xv[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27059 Q=xv[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27057 Q=xv[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27055 Q=xv[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27053 Q=xv[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27051 Q=xv[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27049 Q=xv[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27047 Q=xv[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27045 Q=xv[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27043 Q=xv[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27041 Q=xv[9][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27039 Q=xv[9][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27037 Q=xv[9][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27035 Q=xv[9][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28197 Q=xv[9][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27033 Q=yv[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27031 Q=yv[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27029 Q=yv[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27027 Q=yv[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27025 Q=yv[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27023 Q=yv[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27021 Q=yv[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27019 Q=yv[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27017 Q=yv[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27015 Q=yv[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27013 Q=yv[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27011 Q=yv[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27009 Q=yv[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27007 Q=yv[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27005 Q=yv[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27003 Q=yv[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27001 Q=yv[9][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26999 Q=yv[9][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26997 Q=yv[9][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26995 Q=yv[9][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28199 Q=yv[9][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26993 Q=ph[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26991 Q=ph[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26989 Q=ph[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26987 Q=ph[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26985 Q=ph[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26983 Q=ph[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26981 Q=ph[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26979 Q=ph[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26977 Q=ph[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26975 Q=ph[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26973 Q=ph[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26971 Q=ph[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26969 Q=ph[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26967 Q=ph[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26965 Q=ph[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26963 Q=ph[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26961 Q=ph[9][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26959 Q=ph[9][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26957 Q=ph[9][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26955 Q=ph[9][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28201 Q=ph[9][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26953 Q=xv[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26951 Q=xv[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26949 Q=xv[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26947 Q=xv[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26945 Q=xv[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26943 Q=xv[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26941 Q=xv[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26939 Q=xv[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26937 Q=xv[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26935 Q=xv[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26933 Q=xv[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26931 Q=xv[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26929 Q=xv[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26927 Q=xv[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26925 Q=xv[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26923 Q=xv[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26921 Q=xv[8][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26919 Q=xv[8][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26917 Q=xv[8][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26915 Q=xv[8][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28203 Q=xv[8][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26913 Q=yv[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26911 Q=yv[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26909 Q=yv[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26907 Q=yv[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26905 Q=yv[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26903 Q=yv[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26901 Q=yv[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26899 Q=yv[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26897 Q=yv[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26895 Q=yv[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26893 Q=yv[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26891 Q=yv[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26889 Q=yv[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26887 Q=yv[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26885 Q=yv[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26883 Q=yv[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26881 Q=yv[8][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26879 Q=yv[8][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26877 Q=yv[8][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26875 Q=yv[8][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28205 Q=yv[8][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26873 Q=ph[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26871 Q=ph[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26869 Q=ph[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26867 Q=ph[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26865 Q=ph[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26863 Q=ph[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26861 Q=ph[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26859 Q=ph[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26857 Q=ph[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26855 Q=ph[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26853 Q=ph[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26851 Q=ph[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26849 Q=ph[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26847 Q=ph[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26845 Q=ph[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26843 Q=ph[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26841 Q=ph[8][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26839 Q=ph[8][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26837 Q=ph[8][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26835 Q=ph[8][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28207 Q=ph[8][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26833 Q=xv[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26831 Q=xv[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26829 Q=xv[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26827 Q=xv[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26825 Q=xv[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26823 Q=xv[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26821 Q=xv[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26819 Q=xv[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26817 Q=xv[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26815 Q=xv[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26813 Q=xv[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26811 Q=xv[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26809 Q=xv[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26807 Q=xv[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26805 Q=xv[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26803 Q=xv[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26801 Q=xv[7][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26799 Q=xv[7][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26797 Q=xv[7][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26795 Q=xv[7][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28209 Q=xv[7][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26793 Q=yv[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26791 Q=yv[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26789 Q=yv[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26787 Q=yv[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26785 Q=yv[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26783 Q=yv[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26781 Q=yv[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26779 Q=yv[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26777 Q=yv[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26775 Q=yv[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26773 Q=yv[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26771 Q=yv[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26769 Q=yv[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26767 Q=yv[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26765 Q=yv[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26763 Q=yv[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26761 Q=yv[7][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26759 Q=yv[7][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26757 Q=yv[7][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26755 Q=yv[7][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28211 Q=yv[7][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26753 Q=ph[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26751 Q=ph[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26749 Q=ph[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26747 Q=ph[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26745 Q=ph[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26743 Q=ph[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26741 Q=ph[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26739 Q=ph[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26737 Q=ph[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26735 Q=ph[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26733 Q=ph[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26731 Q=ph[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26729 Q=ph[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26727 Q=ph[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26725 Q=ph[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26723 Q=ph[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26721 Q=ph[7][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26719 Q=ph[7][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26717 Q=ph[7][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26715 Q=ph[7][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28213 Q=ph[7][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26713 Q=xv[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26711 Q=xv[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26709 Q=xv[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26707 Q=xv[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26705 Q=xv[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26703 Q=xv[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26701 Q=xv[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26699 Q=xv[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26697 Q=xv[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26695 Q=xv[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26693 Q=xv[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26691 Q=xv[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26689 Q=xv[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26687 Q=xv[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26685 Q=xv[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26683 Q=xv[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26681 Q=xv[6][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26679 Q=xv[6][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26677 Q=xv[6][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26675 Q=xv[6][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28215 Q=xv[6][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26673 Q=yv[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26671 Q=yv[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26669 Q=yv[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26667 Q=yv[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26665 Q=yv[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26663 Q=yv[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26661 Q=yv[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26659 Q=yv[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26657 Q=yv[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26655 Q=yv[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26653 Q=yv[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26651 Q=yv[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26649 Q=yv[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26647 Q=yv[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26645 Q=yv[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26643 Q=yv[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26641 Q=yv[6][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26639 Q=yv[6][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26637 Q=yv[6][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26635 Q=yv[6][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28217 Q=yv[6][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26633 Q=ph[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26631 Q=ph[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26629 Q=ph[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26627 Q=ph[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26625 Q=ph[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26623 Q=ph[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26621 Q=ph[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26619 Q=ph[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26617 Q=ph[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26615 Q=ph[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26613 Q=ph[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26611 Q=ph[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26609 Q=ph[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26607 Q=ph[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26605 Q=ph[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26603 Q=ph[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26601 Q=ph[6][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26599 Q=ph[6][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26597 Q=ph[6][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26595 Q=ph[6][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28219 Q=ph[6][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26593 Q=xv[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26591 Q=xv[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26589 Q=xv[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26587 Q=xv[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26585 Q=xv[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26583 Q=xv[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26581 Q=xv[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26579 Q=xv[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26577 Q=xv[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26575 Q=xv[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26573 Q=xv[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26571 Q=xv[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26569 Q=xv[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26567 Q=xv[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26565 Q=xv[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26563 Q=xv[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26561 Q=xv[5][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26559 Q=xv[5][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26557 Q=xv[5][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26555 Q=xv[5][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28221 Q=xv[5][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26553 Q=yv[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26551 Q=yv[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26549 Q=yv[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26547 Q=yv[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26545 Q=yv[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26543 Q=yv[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26541 Q=yv[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26539 Q=yv[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26537 Q=yv[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26535 Q=yv[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26533 Q=yv[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26531 Q=yv[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26529 Q=yv[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26527 Q=yv[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26525 Q=yv[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26523 Q=yv[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26521 Q=yv[5][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26519 Q=yv[5][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26517 Q=yv[5][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26515 Q=yv[5][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28223 Q=yv[5][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26513 Q=ph[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26511 Q=ph[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26509 Q=ph[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26507 Q=ph[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26505 Q=ph[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26503 Q=ph[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26501 Q=ph[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26499 Q=ph[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26497 Q=ph[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26495 Q=ph[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26493 Q=ph[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26491 Q=ph[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26489 Q=ph[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26487 Q=ph[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26485 Q=ph[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26483 Q=ph[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26481 Q=ph[5][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26479 Q=ph[5][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26477 Q=ph[5][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26475 Q=ph[5][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28225 Q=ph[5][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26473 Q=xv[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26471 Q=xv[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26469 Q=xv[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26467 Q=xv[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26465 Q=xv[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26463 Q=xv[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26461 Q=xv[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26459 Q=xv[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26457 Q=xv[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26455 Q=xv[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26453 Q=xv[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26451 Q=xv[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26449 Q=xv[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26447 Q=xv[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26445 Q=xv[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26443 Q=xv[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26441 Q=xv[4][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26439 Q=xv[4][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26437 Q=xv[4][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26435 Q=xv[4][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28227 Q=xv[4][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26433 Q=yv[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26431 Q=yv[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26429 Q=yv[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26427 Q=yv[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26425 Q=yv[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26423 Q=yv[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26421 Q=yv[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26419 Q=yv[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26417 Q=yv[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26415 Q=yv[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26413 Q=yv[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26411 Q=yv[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26409 Q=yv[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26407 Q=yv[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26405 Q=yv[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26403 Q=yv[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26401 Q=yv[4][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26399 Q=yv[4][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26397 Q=yv[4][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26395 Q=yv[4][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28229 Q=yv[4][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26393 Q=ph[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26391 Q=ph[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26389 Q=ph[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26387 Q=ph[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26385 Q=ph[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26383 Q=ph[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26381 Q=ph[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26379 Q=ph[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26377 Q=ph[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26375 Q=ph[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26373 Q=ph[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26371 Q=ph[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26369 Q=ph[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26367 Q=ph[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26365 Q=ph[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26363 Q=ph[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26361 Q=ph[4][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26359 Q=ph[4][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26357 Q=ph[4][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26355 Q=ph[4][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28231 Q=ph[4][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26353 Q=xv[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26351 Q=xv[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26349 Q=xv[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26347 Q=xv[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26345 Q=xv[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26343 Q=xv[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26341 Q=xv[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26339 Q=xv[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26337 Q=xv[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26335 Q=xv[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26333 Q=xv[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26331 Q=xv[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26329 Q=xv[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26327 Q=xv[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26325 Q=xv[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26323 Q=xv[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26321 Q=xv[3][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26319 Q=xv[3][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26317 Q=xv[3][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26315 Q=xv[3][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28233 Q=xv[3][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26313 Q=yv[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26311 Q=yv[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26309 Q=yv[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26307 Q=yv[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26305 Q=yv[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26303 Q=yv[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26301 Q=yv[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26299 Q=yv[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26297 Q=yv[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26295 Q=yv[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26293 Q=yv[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26291 Q=yv[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26289 Q=yv[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26287 Q=yv[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26285 Q=yv[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26283 Q=yv[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26281 Q=yv[3][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26279 Q=yv[3][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26277 Q=yv[3][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26275 Q=yv[3][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28235 Q=yv[3][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26273 Q=ph[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26271 Q=ph[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26269 Q=ph[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26267 Q=ph[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26265 Q=ph[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26263 Q=ph[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26261 Q=ph[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26259 Q=ph[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26257 Q=ph[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26255 Q=ph[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26253 Q=ph[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26251 Q=ph[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26249 Q=ph[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26247 Q=ph[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26245 Q=ph[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26243 Q=ph[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26241 Q=ph[3][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26239 Q=ph[3][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26237 Q=ph[3][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26235 Q=ph[3][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28237 Q=ph[3][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26233 Q=xv[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26231 Q=xv[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26229 Q=xv[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26227 Q=xv[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26225 Q=xv[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26223 Q=xv[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26221 Q=xv[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26219 Q=xv[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26217 Q=xv[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26215 Q=xv[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26213 Q=xv[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26211 Q=xv[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26209 Q=xv[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26207 Q=xv[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26205 Q=xv[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26203 Q=xv[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26201 Q=xv[2][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26199 Q=xv[2][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26197 Q=xv[2][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26195 Q=xv[2][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28239 Q=xv[2][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26193 Q=yv[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26191 Q=yv[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26189 Q=yv[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26187 Q=yv[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26185 Q=yv[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26183 Q=yv[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26181 Q=yv[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26179 Q=yv[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26177 Q=yv[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26175 Q=yv[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26173 Q=yv[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26171 Q=yv[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26169 Q=yv[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26167 Q=yv[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26165 Q=yv[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26163 Q=yv[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26161 Q=yv[2][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26159 Q=yv[2][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26157 Q=yv[2][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26155 Q=yv[2][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28241 Q=yv[2][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26153 Q=ph[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26151 Q=ph[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26149 Q=ph[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26147 Q=ph[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26145 Q=ph[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26143 Q=ph[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26141 Q=ph[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26139 Q=ph[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26137 Q=ph[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26135 Q=ph[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26133 Q=ph[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26131 Q=ph[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26129 Q=ph[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26127 Q=ph[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26125 Q=ph[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26123 Q=ph[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26121 Q=ph[2][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26119 Q=ph[2][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26117 Q=ph[2][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26115 Q=ph[2][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28243 Q=ph[2][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26113 Q=xv[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26111 Q=xv[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26109 Q=xv[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26107 Q=xv[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26105 Q=xv[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26103 Q=xv[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26101 Q=xv[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26099 Q=xv[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26097 Q=xv[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26095 Q=xv[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26093 Q=xv[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26091 Q=xv[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26089 Q=xv[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26087 Q=xv[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26085 Q=xv[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26083 Q=xv[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26081 Q=xv[1][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26079 Q=xv[1][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26077 Q=xv[1][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26075 Q=xv[1][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28245 Q=xv[1][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26073 Q=yv[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26071 Q=yv[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26069 Q=yv[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26067 Q=yv[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26065 Q=yv[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26063 Q=yv[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26061 Q=yv[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26059 Q=yv[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26057 Q=yv[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26055 Q=yv[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26053 Q=yv[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26051 Q=yv[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26049 Q=yv[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26047 Q=yv[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26045 Q=yv[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26043 Q=yv[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26041 Q=yv[1][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26039 Q=yv[1][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26037 Q=yv[1][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26035 Q=yv[1][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28247 Q=yv[1][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26033 Q=o_mag[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26031 Q=o_mag[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26029 Q=o_mag[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26027 Q=o_mag[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26025 Q=o_mag[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26023 Q=o_mag[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26021 Q=o_mag[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26019 Q=o_mag[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26017 Q=o_mag[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26015 Q=o_mag[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26013 Q=o_mag[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26011 Q=o_mag[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28249 Q=o_mag[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26009 Q=o_phase[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26007 Q=o_phase[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26005 Q=o_phase[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26003 Q=o_phase[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26001 Q=o_phase[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25999 Q=o_phase[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25997 Q=o_phase[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25995 Q=o_phase[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25993 Q=o_phase[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25991 Q=o_phase[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25989 Q=o_phase[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25987 Q=o_phase[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25985 Q=o_phase[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25983 Q=o_phase[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25981 Q=o_phase[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25979 Q=o_phase[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25977 Q=o_phase[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25975 Q=o_phase[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25973 Q=o_phase[18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25971 Q=o_phase[19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28251 Q=o_phase[20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28253 Q=o_aux R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25969 Q=xv[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25967 Q=xv[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25965 Q=xv[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25963 Q=xv[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25961 Q=xv[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25959 Q=xv[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25957 Q=xv[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25955 Q=xv[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25953 Q=xv[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25951 Q=xv[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25949 Q=xv[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25947 Q=xv[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25945 Q=xv[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25943 Q=xv[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25941 Q=xv[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25939 Q=xv[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25937 Q=xv[0][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25935 Q=xv[0][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25933 Q=xv[0][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25931 Q=xv[0][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28255 Q=xv[0][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25929 Q=yv[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25927 Q=yv[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25925 Q=yv[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25923 Q=yv[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25921 Q=yv[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25919 Q=yv[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25917 Q=yv[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25915 Q=yv[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25913 Q=yv[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25911 Q=yv[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25909 Q=yv[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25907 Q=yv[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25905 Q=yv[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25903 Q=yv[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25901 Q=yv[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25899 Q=yv[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25897 Q=yv[0][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25895 Q=yv[0][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25893 Q=yv[0][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25891 Q=yv[0][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28257 Q=yv[0][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25889 Q=ax[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25887 Q=ax[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25885 Q=ax[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25883 Q=ax[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25881 Q=ax[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25879 Q=ax[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25877 Q=ax[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25875 Q=ax[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25873 Q=ax[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25871 Q=ax[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25869 Q=ax[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25867 Q=ax[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25865 Q=ax[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25863 Q=ax[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25861 Q=ax[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25859 Q=ax[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25857 Q=ax[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25855 Q=ax[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28259 Q=ax[18] R=i_reset +.names $false ph[0][0] +1 1 +.names $false ph[0][1] +1 1 +.names $false ph[0][2] +1 1 +.names $false ph[0][3] +1 1 +.names $false ph[0][4] +1 1 +.names $false ph[0][5] +1 1 +.names $false ph[0][6] +1 1 +.names $false ph[0][7] +1 1 +.names $false ph[0][8] +1 1 +.names $false ph[0][9] +1 1 +.names $false ph[0][10] +1 1 +.names $false ph[0][11] +1 1 +.names $false ph[0][12] +1 1 +.names $false ph[0][13] +1 1 +.names $false ph[0][14] +1 1 +.names $false ph[0][15] +1 1 +.names $false ph[0][16] +1 1 +.names $false ph[0][17] +1 1 +.names $false ph[1][0] +1 1 +.names $false ph[1][1] +1 1 +.names $false ph[1][2] +1 1 +.names $false ph[1][3] +1 1 +.names $false ph[1][4] +1 1 +.names $false ph[1][5] +1 1 +.names $false ph[1][6] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif new file mode 100644 index 00000000000..ad4923c7d2e --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif @@ -0,0 +1,54152 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model zipcore +.inputs i_clk i_reset i_interrupt i_halt i_clear_cache i_dbg_wreg[0] i_dbg_wreg[1] i_dbg_wreg[2] i_dbg_wreg[3] i_dbg_wreg[4] i_dbg_we i_dbg_data[0] i_dbg_data[1] i_dbg_data[2] i_dbg_data[3] i_dbg_data[4] i_dbg_data[5] i_dbg_data[6] i_dbg_data[7] i_dbg_data[8] i_dbg_data[9] i_dbg_data[10] i_dbg_data[11] i_dbg_data[12] i_dbg_data[13] i_dbg_data[14] i_dbg_data[15] i_dbg_data[16] i_dbg_data[17] i_dbg_data[18] i_dbg_data[19] i_dbg_data[20] i_dbg_data[21] i_dbg_data[22] i_dbg_data[23] i_dbg_data[24] i_dbg_data[25] i_dbg_data[26] i_dbg_data[27] i_dbg_data[28] i_dbg_data[29] i_dbg_data[30] i_dbg_data[31] i_dbg_rreg[0] i_dbg_rreg[1] i_dbg_rreg[2] i_dbg_rreg[3] i_dbg_rreg[4] i_pf_valid i_pf_illegal i_pf_instruction[0] i_pf_instruction[1] i_pf_instruction[2] i_pf_instruction[3] i_pf_instruction[4] i_pf_instruction[5] i_pf_instruction[6] i_pf_instruction[7] i_pf_instruction[8] i_pf_instruction[9] i_pf_instruction[10] i_pf_instruction[11] i_pf_instruction[12] i_pf_instruction[13] i_pf_instruction[14] i_pf_instruction[15] i_pf_instruction[16] i_pf_instruction[17] i_pf_instruction[18] i_pf_instruction[19] i_pf_instruction[20] i_pf_instruction[21] i_pf_instruction[22] i_pf_instruction[23] i_pf_instruction[24] i_pf_instruction[25] i_pf_instruction[26] i_pf_instruction[27] i_pf_instruction[28] i_pf_instruction[29] i_pf_instruction[30] i_pf_instruction[31] i_pf_instruction_pc[0] i_pf_instruction_pc[1] i_pf_instruction_pc[2] i_pf_instruction_pc[3] i_pf_instruction_pc[4] i_pf_instruction_pc[5] i_pf_instruction_pc[6] i_pf_instruction_pc[7] i_pf_instruction_pc[8] i_pf_instruction_pc[9] i_pf_instruction_pc[10] i_pf_instruction_pc[11] i_pf_instruction_pc[12] i_pf_instruction_pc[13] i_pf_instruction_pc[14] i_pf_instruction_pc[15] i_pf_instruction_pc[16] i_pf_instruction_pc[17] i_pf_instruction_pc[18] i_pf_instruction_pc[19] i_pf_instruction_pc[20] i_pf_instruction_pc[21] i_pf_instruction_pc[22] i_pf_instruction_pc[23] i_pf_instruction_pc[24] i_pf_instruction_pc[25] i_pf_instruction_pc[26] i_pf_instruction_pc[27] i_pf_instruction_pc[28] i_pf_instruction_pc[29] i_pf_instruction_pc[30] i_pf_instruction_pc[31] i_mem_busy i_mem_rdbusy i_mem_pipe_stalled i_mem_valid i_bus_err i_mem_wreg[0] i_mem_wreg[1] i_mem_wreg[2] i_mem_wreg[3] i_mem_wreg[4] i_mem_result[0] i_mem_result[1] i_mem_result[2] i_mem_result[3] i_mem_result[4] i_mem_result[5] i_mem_result[6] i_mem_result[7] i_mem_result[8] i_mem_result[9] i_mem_result[10] i_mem_result[11] i_mem_result[12] i_mem_result[13] i_mem_result[14] i_mem_result[15] i_mem_result[16] i_mem_result[17] i_mem_result[18] i_mem_result[19] i_mem_result[20] i_mem_result[21] i_mem_result[22] i_mem_result[23] i_mem_result[24] i_mem_result[25] i_mem_result[26] i_mem_result[27] i_mem_result[28] i_mem_result[29] i_mem_result[30] i_mem_result[31] +.outputs o_clken o_dbg_stall o_dbg_reg[0] o_dbg_reg[1] o_dbg_reg[2] o_dbg_reg[3] o_dbg_reg[4] o_dbg_reg[5] o_dbg_reg[6] o_dbg_reg[7] o_dbg_reg[8] o_dbg_reg[9] o_dbg_reg[10] o_dbg_reg[11] o_dbg_reg[12] o_dbg_reg[13] o_dbg_reg[14] o_dbg_reg[15] o_dbg_reg[16] o_dbg_reg[17] o_dbg_reg[18] o_dbg_reg[19] o_dbg_reg[20] o_dbg_reg[21] o_dbg_reg[22] o_dbg_reg[23] o_dbg_reg[24] o_dbg_reg[25] o_dbg_reg[26] o_dbg_reg[27] o_dbg_reg[28] o_dbg_reg[29] o_dbg_reg[30] o_dbg_reg[31] o_dbg_cc[0] o_dbg_cc[1] o_dbg_cc[2] o_break o_pf_new_pc o_clear_icache o_pf_ready o_pf_request_address[0] o_pf_request_address[1] o_pf_request_address[2] o_pf_request_address[3] o_pf_request_address[4] o_pf_request_address[5] o_pf_request_address[6] o_pf_request_address[7] o_pf_request_address[8] o_pf_request_address[9] o_pf_request_address[10] o_pf_request_address[11] o_pf_request_address[12] o_pf_request_address[13] o_pf_request_address[14] o_pf_request_address[15] o_pf_request_address[16] o_pf_request_address[17] o_pf_request_address[18] o_pf_request_address[19] o_pf_request_address[20] o_pf_request_address[21] o_pf_request_address[22] o_pf_request_address[23] o_pf_request_address[24] o_pf_request_address[25] o_pf_request_address[26] o_pf_request_address[27] o_pf_request_address[28] o_pf_request_address[29] o_pf_request_address[30] o_pf_request_address[31] o_clear_dcache o_mem_ce o_bus_lock o_mem_op[0] o_mem_op[1] o_mem_op[2] o_mem_addr[0] o_mem_addr[1] o_mem_addr[2] o_mem_addr[3] o_mem_addr[4] o_mem_addr[5] o_mem_addr[6] o_mem_addr[7] o_mem_addr[8] o_mem_addr[9] o_mem_addr[10] o_mem_addr[11] o_mem_addr[12] o_mem_addr[13] o_mem_addr[14] o_mem_addr[15] o_mem_addr[16] o_mem_addr[17] o_mem_addr[18] o_mem_addr[19] o_mem_addr[20] o_mem_addr[21] o_mem_addr[22] o_mem_addr[23] o_mem_addr[24] o_mem_addr[25] o_mem_addr[26] o_mem_addr[27] o_mem_addr[28] o_mem_addr[29] o_mem_addr[30] o_mem_addr[31] o_mem_data[0] o_mem_data[1] o_mem_data[2] o_mem_data[3] o_mem_data[4] o_mem_data[5] o_mem_data[6] o_mem_data[7] o_mem_data[8] o_mem_data[9] o_mem_data[10] o_mem_data[11] o_mem_data[12] o_mem_data[13] o_mem_data[14] o_mem_data[15] o_mem_data[16] o_mem_data[17] o_mem_data[18] o_mem_data[19] o_mem_data[20] o_mem_data[21] o_mem_data[22] o_mem_data[23] o_mem_data[24] o_mem_data[25] o_mem_data[26] o_mem_data[27] o_mem_data[28] o_mem_data[29] o_mem_data[30] o_mem_data[31] o_mem_lock_pc[0] o_mem_lock_pc[1] o_mem_lock_pc[2] o_mem_lock_pc[3] o_mem_lock_pc[4] o_mem_lock_pc[5] o_mem_lock_pc[6] o_mem_lock_pc[7] o_mem_lock_pc[8] o_mem_lock_pc[9] o_mem_lock_pc[10] o_mem_lock_pc[11] o_mem_lock_pc[12] o_mem_lock_pc[13] o_mem_lock_pc[14] o_mem_lock_pc[15] o_mem_lock_pc[16] o_mem_lock_pc[17] o_mem_lock_pc[18] o_mem_lock_pc[19] o_mem_lock_pc[20] o_mem_lock_pc[21] o_mem_lock_pc[22] o_mem_lock_pc[23] o_mem_lock_pc[24] o_mem_lock_pc[25] o_mem_lock_pc[26] o_mem_lock_pc[27] o_mem_lock_pc[28] o_mem_lock_pc[29] o_mem_lock_pc[30] o_mem_lock_pc[31] o_mem_reg[0] o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] o_mem_reg[4] o_op_stall o_pf_stall o_i_count o_debug[0] o_debug[1] o_debug[2] o_debug[3] o_debug[4] o_debug[5] o_debug[6] o_debug[7] o_debug[8] o_debug[9] o_debug[10] o_debug[11] o_debug[12] o_debug[13] o_debug[14] o_debug[15] o_debug[16] o_debug[17] o_debug[18] o_debug[19] o_debug[20] o_debug[21] o_debug[22] o_debug[23] o_debug[24] o_debug[25] o_debug[26] o_debug[27] o_debug[28] o_debug[29] o_debug[30] o_debug[31] o_prof_stb o_prof_addr[0] o_prof_addr[1] o_prof_addr[2] o_prof_addr[3] o_prof_addr[4] o_prof_addr[5] o_prof_addr[6] o_prof_addr[7] o_prof_addr[8] o_prof_addr[9] o_prof_addr[10] o_prof_addr[11] o_prof_addr[12] o_prof_addr[13] o_prof_addr[14] o_prof_addr[15] o_prof_addr[16] o_prof_addr[17] o_prof_addr[18] o_prof_addr[19] o_prof_addr[20] o_prof_addr[21] o_prof_addr[22] o_prof_addr[23] o_prof_addr[24] o_prof_addr[25] o_prof_addr[26] o_prof_addr[27] o_prof_addr[28] o_prof_addr[29] o_prof_addr[30] o_prof_addr[31] o_prof_ticks[0] o_prof_ticks[1] o_prof_ticks[2] o_prof_ticks[3] o_prof_ticks[4] o_prof_ticks[5] o_prof_ticks[6] o_prof_ticks[7] o_prof_ticks[8] o_prof_ticks[9] o_prof_ticks[10] o_prof_ticks[11] o_prof_ticks[12] o_prof_ticks[13] o_prof_ticks[14] o_prof_ticks[15] o_prof_ticks[16] o_prof_ticks[17] o_prof_ticks[18] o_prof_ticks[19] o_prof_ticks[20] o_prof_ticks[21] o_prof_ticks[22] o_prof_ticks[23] o_prof_ticks[24] o_prof_ticks[25] o_prof_ticks[26] o_prof_ticks[27] o_prof_ticks[28] o_prof_ticks[29] o_prof_ticks[30] o_prof_ticks[31] +.names $false +.names $true +1 +.names $undef +.names $abc$24881$new_n3673 DIVIDE.thedivide.r_dividend[27] DIVIDE.thedivide.r_dividend[28] $abc$24881$new_n3672 +100 1 +.names $abc$24881$new_n3674 DIVIDE.thedivide.r_dividend[25] DIVIDE.thedivide.r_dividend[26] $abc$24881$new_n3673 +100 1 +.names $abc$24881$new_n3675 DIVIDE.thedivide.r_dividend[24] $abc$24881$new_n3674 +10 1 +.names $abc$24881$new_n3676 DIVIDE.thedivide.r_dividend[21] DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.r_dividend[23] $abc$24881$new_n3675 +1000 1 +.names $abc$24881$new_n3677 DIVIDE.thedivide.r_dividend[20] $abc$24881$new_n3676 +10 1 +.names $abc$24881$new_n3678 DIVIDE.thedivide.r_dividend[17] DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.r_dividend[19] $abc$24881$new_n3677 +1000 1 +.names $abc$24881$new_n3679 DIVIDE.thedivide.r_dividend[16] $abc$24881$new_n3678 +10 1 +.names $abc$24881$new_n3680 DIVIDE.thedivide.r_dividend[15] $abc$24881$new_n3679 +10 1 +.names $abc$24881$new_n3681 DIVIDE.thedivide.r_dividend[13] DIVIDE.thedivide.r_dividend[14] $abc$24881$new_n3680 +100 1 +.names $abc$24881$new_n3682 DIVIDE.thedivide.r_dividend[12] $abc$24881$new_n3681 +10 1 +.names $abc$24881$new_n3683 DIVIDE.thedivide.r_dividend[11] $abc$24881$new_n3682 +10 1 +.names $abc$24881$new_n3684 DIVIDE.thedivide.r_dividend[10] $abc$24881$new_n3683 +10 1 +.names $abc$24881$new_n3685 DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3684 +10 1 +.names $abc$24881$new_n3686 DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3685 +10 1 +.names $abc$24881$new_n3687 DIVIDE.thedivide.r_dividend[6] DIVIDE.thedivide.r_dividend[7] $abc$24881$new_n3686 +100 1 +.names $abc$24881$new_n3688 DIVIDE.thedivide.r_dividend[3] DIVIDE.thedivide.r_dividend[4] DIVIDE.thedivide.r_dividend[5] $abc$24881$new_n3687 +1000 1 +.names $abc$24881$new_n3689 DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3688 +10 1 +.names DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_dividend[1] $abc$24881$new_n3689 +00 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3702 r_op_Av[30] o_mem_data[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3692 +111 1 +.names o_mem_reg[4] o_mem_reg[3] $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n3693 +0011 1 +0101 1 +1010 1 +1100 1 +.names i_mem_valid alu_reg[4] i_mem_wreg[4] $abc$24881$new_n3694 +000 1 +001 1 +100 1 +110 1 +.names i_mem_valid alu_reg[3] i_mem_wreg[3] $abc$24881$new_n3695 +000 1 +001 1 +100 1 +110 1 +.names o_mem_reg[0] o_mem_reg[1] $abc$24881$new_n3698 $abc$24881$new_n3697 $abc$24881$new_n3696 +0011 1 +0101 1 +1010 1 +1100 1 +.names i_mem_valid alu_reg[0] i_mem_wreg[0] $abc$24881$new_n3697 +000 1 +001 1 +100 1 +110 1 +.names i_mem_valid alu_reg[1] i_mem_wreg[1] $abc$24881$new_n3698 +000 1 +001 1 +100 1 +110 1 +.names o_mem_reg[2] $abc$24881$new_n3701 i_mem_valid dbgv $abc$24881$new_n3700 $abc$24881$new_n3699 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names new_pc DIVIDE.thedivide.o_valid DIVIDE.thedivide.o_err doalu.o_valid alu_wR $abc$24881$new_n3700 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +.names i_mem_valid alu_reg[2] i_mem_wreg[2] $abc$24881$new_n3701 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n3703 i_mem_result[30] wr_index[0] wr_index[1] $abc$24881$new_n3702 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[30] alu_result[30] dbg_val[30] $abc$24881$new_n3703 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3704 +10 1 +.names DIVIDE.thedivide.r_dividend[29] $abc$24881$new_n3704 DIVIDE.thedivide.pre_sign $abc$24881$new_n3672 $abc$24881$new_n3706 $abc$24881$auto$rtlil.cc:2693:MuxGate$22568 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[29] DIVIDE.thedivide.r_dividend[28] $abc$24881$new_n3706 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3708 r_op_Av[29] o_mem_data[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3709 i_mem_result[29] wr_index[0] wr_index[1] $abc$24881$new_n3708 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[29] alu_result[29] dbg_val[29] $abc$24881$new_n3709 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3714 r_op_Av[28] o_mem_data[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3715 i_mem_result[28] wr_index[0] wr_index[1] $abc$24881$new_n3714 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[28] alu_result[28] dbg_val[28] $abc$24881$new_n3715 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3717 DIVIDE.thedivide.r_dividend[27] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3673 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22572 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[27] DIVIDE.thedivide.r_dividend[26] $abc$24881$new_n3717 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3719 r_op_Av[27] o_mem_data[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3720 i_mem_result[27] wr_index[0] wr_index[1] $abc$24881$new_n3719 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[27] alu_result[27] dbg_val[27] $abc$24881$new_n3720 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3725 r_op_Av[26] o_mem_data[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3726 i_mem_result[26] wr_index[0] wr_index[1] $abc$24881$new_n3725 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[26] alu_result[26] dbg_val[26] $abc$24881$new_n3726 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3728 DIVIDE.thedivide.r_dividend[25] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3674 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22576 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[25] DIVIDE.thedivide.r_dividend[24] $abc$24881$new_n3728 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3730 r_op_Av[25] o_mem_data[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3731 i_mem_result[25] wr_index[0] wr_index[1] $abc$24881$new_n3730 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[25] alu_result[25] dbg_val[25] $abc$24881$new_n3731 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3733 DIVIDE.thedivide.r_dividend[24] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3675 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22578 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[24] DIVIDE.thedivide.r_dividend[23] $abc$24881$new_n3733 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3735 r_op_Av[24] o_mem_data[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3736 i_mem_result[24] wr_index[0] wr_index[1] $abc$24881$new_n3735 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[24] alu_result[24] dbg_val[24] $abc$24881$new_n3736 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3741 r_op_Av[23] o_mem_data[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3742 i_mem_result[23] wr_index[0] wr_index[1] $abc$24881$new_n3741 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[23] alu_result[23] dbg_val[23] $abc$24881$new_n3742 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3747 r_op_Av[22] o_mem_data[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3748 i_mem_result[22] wr_index[0] wr_index[1] $abc$24881$new_n3747 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[22] alu_result[22] dbg_val[22] $abc$24881$new_n3748 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3750 DIVIDE.thedivide.r_dividend[21] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3676 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22584 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[21] DIVIDE.thedivide.r_dividend[20] $abc$24881$new_n3750 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3752 r_op_Av[21] o_mem_data[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3753 i_mem_result[21] wr_index[0] wr_index[1] $abc$24881$new_n3752 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[21] alu_result[21] dbg_val[21] $abc$24881$new_n3753 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3755 DIVIDE.thedivide.r_dividend[20] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3677 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22586 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[20] DIVIDE.thedivide.r_dividend[19] $abc$24881$new_n3755 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3757 r_op_Av[20] o_mem_data[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3758 i_mem_result[20] wr_index[0] wr_index[1] $abc$24881$new_n3757 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[20] alu_result[20] dbg_val[20] $abc$24881$new_n3758 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3763 r_op_Av[19] o_mem_data[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3764 i_mem_result[19] wr_index[0] wr_index[1] $abc$24881$new_n3763 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[19] alu_result[19] dbg_val[19] $abc$24881$new_n3764 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3769 r_op_Av[18] o_mem_data[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3770 i_mem_result[18] wr_index[0] wr_index[1] $abc$24881$new_n3769 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[18] alu_result[18] dbg_val[18] $abc$24881$new_n3770 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3772 DIVIDE.thedivide.r_dividend[17] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3678 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22592 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[17] DIVIDE.thedivide.r_dividend[16] $abc$24881$new_n3772 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3774 r_op_Av[17] o_mem_data[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3775 i_mem_result[17] wr_index[0] wr_index[1] $abc$24881$new_n3774 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[17] alu_result[17] dbg_val[17] $abc$24881$new_n3775 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3777 DIVIDE.thedivide.r_dividend[16] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3679 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22594 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[16] DIVIDE.thedivide.r_dividend[15] $abc$24881$new_n3777 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3779 r_op_Av[16] o_mem_data[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3780 i_mem_result[16] wr_index[0] wr_index[1] $abc$24881$new_n3779 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[16] alu_result[16] dbg_val[16] $abc$24881$new_n3780 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3782 DIVIDE.thedivide.r_dividend[15] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3680 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22596 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[15] DIVIDE.thedivide.r_dividend[14] $abc$24881$new_n3782 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3784 r_op_Av[15] o_mem_data[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3785 i_mem_result[15] wr_index[0] wr_index[1] $abc$24881$new_n3784 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[15] alu_result[15] dbg_val[15] $abc$24881$new_n3785 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3790 r_op_Av[14] o_mem_data[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3791 i_mem_result[14] wr_index[0] wr_index[1] $abc$24881$new_n3790 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[14] alu_result[14] dbg_val[14] $abc$24881$new_n3791 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3793 DIVIDE.thedivide.r_dividend[13] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3681 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22600 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[13] DIVIDE.thedivide.r_dividend[12] $abc$24881$new_n3793 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3795 r_op_Av[13] o_mem_data[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3796 i_mem_result[13] wr_index[0] wr_index[1] $abc$24881$new_n3795 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[13] alu_result[13] dbg_val[13] $abc$24881$new_n3796 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3798 DIVIDE.thedivide.r_dividend[12] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3682 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22602 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[12] DIVIDE.thedivide.r_dividend[11] $abc$24881$new_n3798 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3800 r_op_Av[12] o_mem_data[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3801 i_mem_result[12] wr_index[0] wr_index[1] $abc$24881$new_n3800 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[12] alu_result[12] dbg_val[12] $abc$24881$new_n3801 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3803 DIVIDE.thedivide.r_dividend[11] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3683 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22604 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[11] DIVIDE.thedivide.r_dividend[10] $abc$24881$new_n3803 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3805 r_op_Av[11] o_mem_data[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3806 i_mem_result[11] wr_index[0] wr_index[1] $abc$24881$new_n3805 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[11] alu_result[11] dbg_val[11] $abc$24881$new_n3806 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3808 DIVIDE.thedivide.r_dividend[10] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3684 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22606 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[10] DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3808 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3810 r_op_Av[10] o_mem_data[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3811 i_mem_result[10] wr_index[0] wr_index[1] $abc$24881$new_n3810 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[10] alu_result[10] dbg_val[10] $abc$24881$new_n3811 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign $abc$24881$new_n3813 DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3685 $abc$24881$auto$rtlil.cc:2693:MuxGate$22608 +0000 1 +0001 1 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] o_mem_data[9] DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3813 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3815 r_op_Av[9] o_mem_data[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3816 i_mem_result[9] wr_index[0] wr_index[1] $abc$24881$new_n3815 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[9] alu_result[9] dbg_val[9] $abc$24881$new_n3816 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign $abc$24881$new_n3818 DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3686 $abc$24881$auto$rtlil.cc:2693:MuxGate$22610 +0000 1 +0001 1 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] o_mem_data[8] DIVIDE.thedivide.r_dividend[7] $abc$24881$new_n3818 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3820 r_op_Av[8] o_mem_data[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3821 i_mem_result[8] wr_index[0] wr_index[1] $abc$24881$new_n3820 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[8] alu_result[8] dbg_val[8] $abc$24881$new_n3821 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3825 r_op_Av[7] o_mem_data[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3826 i_mem_result[7] wr_index[0] wr_index[1] $abc$24881$new_n3825 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[7] alu_result[7] dbg_val[7] $abc$24881$new_n3826 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy $abc$24881$new_n3828 +00 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign $abc$24881$new_n3829 +10 1 +.names $abc$24881$new_n3704 $abc$24881$new_n3834 DIVIDE.thedivide.r_dividend[6] o_mem_data[6] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22614 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3832 r_op_Av[6] o_mem_data[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3833 i_mem_result[6] wr_index[0] wr_index[1] $abc$24881$new_n3832 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[6] alu_result[6] dbg_val[6] $abc$24881$new_n3833 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[6] $abc$24881$new_n3687 DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[5] $abc$24881$new_n3834 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3838 r_op_Av[5] o_mem_data[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3839 i_mem_result[5] wr_index[0] wr_index[1] $abc$24881$new_n3838 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[5] alu_result[5] dbg_val[5] $abc$24881$new_n3839 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3704 $abc$24881$new_n3845 DIVIDE.thedivide.r_dividend[4] o_mem_data[4] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22618 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3843 r_op_Av[4] o_mem_data[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3844 i_mem_result[4] wr_index[0] wr_index[1] $abc$24881$new_n3843 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[4] alu_result[4] dbg_val[4] $abc$24881$new_n3844 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[4] DIVIDE.thedivide.r_dividend[3] $abc$24881$new_n3688 DIVIDE.thedivide.r_busy $abc$24881$new_n3845 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3704 $abc$24881$new_n3850 DIVIDE.thedivide.r_dividend[3] o_mem_data[3] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22620 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3848 r_op_Av[3] o_mem_data[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3849 i_mem_result[3] wr_index[0] wr_index[1] $abc$24881$new_n3848 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[3] alu_result[3] dbg_val[3] $abc$24881$new_n3849 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[3] DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3689 DIVIDE.thedivide.r_busy $abc$24881$new_n3850 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3855 o_mem_data[2] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22622 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3853 r_op_Av[2] o_mem_data[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3854 i_mem_result[2] wr_index[0] wr_index[1] $abc$24881$new_n3853 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[2] alu_result[2] dbg_val[2] $abc$24881$new_n3854 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[2] DIVIDE.thedivide.r_dividend[1] DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_busy $abc$24881$new_n3855 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3704 $abc$24881$new_n3857 DIVIDE.thedivide.r_dividend[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22624 +000 1 +001 1 +101 1 +111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[1] o_mem_data[1] $abc$24881$new_n3857 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +10000 1 +10001 1 +10100 1 +10101 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names r_op_Av[1] $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3859 o_mem_data[1] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names wr_index[0] wr_index[1] $abc$24881$new_n3860 DIVIDE.thedivide.o_quotient[1] i_mem_result[1] $abc$24881$new_n3859 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names wr_index[1] alu_result[1] dbg_val[1] $abc$24881$new_n3860 +000 1 +010 1 +100 1 +101 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[0] o_mem_data[0] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$22626 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names r_op_Av[0] $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3863 o_mem_data[0] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n3864 dbg_val[0] wr_index[1] wr_index[0] $abc$24881$new_n3863 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[0] i_mem_result[0] alu_result[0] $abc$24881$new_n3864 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3866 DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22630 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[60] DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n3870 $abc$24881$new_n3867 $abc$24881$new_n3866 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[31] DIVIDE.thedivide.r_dividend[62] $abc$24881$new_n3868 $abc$24881$new_n3867 +001 1 +100 1 +101 1 +111 1 +.names DIVIDE.thedivide.r_divisor[30] DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n3869 $abc$24881$new_n3868 +000 1 +100 1 +101 1 +110 1 +.names DIVIDE.thedivide.r_dividend[60] DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n3870 $abc$24881$new_n3869 +000 1 +100 1 +101 1 +110 1 +.names DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_divisor[28] DIVIDE.thedivide.r_dividend[58] DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3871 $abc$24881$new_n3870 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_divisor[26] DIVIDE.thedivide.r_dividend[56] DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3872 $abc$24881$new_n3871 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_dividend[54] DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3873 $abc$24881$new_n3872 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_dividend[52] DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3874 $abc$24881$new_n3873 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_dividend[50] DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3875 $abc$24881$new_n3874 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_dividend[48] DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3876 $abc$24881$new_n3875 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_divisor[16] DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3877 $abc$24881$new_n3876 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3878 $abc$24881$new_n3877 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[42] DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3879 $abc$24881$new_n3878 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_dividend[40] DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3880 $abc$24881$new_n3879 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_divisor[8] DIVIDE.thedivide.r_dividend[38] DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3881 $abc$24881$new_n3880 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_divisor[6] DIVIDE.thedivide.r_dividend[36] DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3882 $abc$24881$new_n3881 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_divisor[4] DIVIDE.thedivide.r_dividend[34] DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3883 $abc$24881$new_n3882 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3884 $abc$24881$new_n3883 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3884 +10 1 +.names $abc$24881$new_n3886 DIVIDE.thedivide.r_dividend[60] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22634 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3887 $abc$24881$new_n3886 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[28] DIVIDE.thedivide.r_dividend[59] DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3871 $abc$24881$new_n3887 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3889 DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22638 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[58] DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n3871 $abc$24881$new_n3867 $abc$24881$new_n3889 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3891 DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22642 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3892 $abc$24881$new_n3891 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[26] DIVIDE.thedivide.r_dividend[57] DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3872 $abc$24881$new_n3892 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3894 DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22646 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[56] DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n3872 $abc$24881$new_n3867 $abc$24881$new_n3894 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3896 DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22650 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3897 $abc$24881$new_n3896 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_dividend[55] DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3873 $abc$24881$new_n3897 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3899 DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22654 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[54] DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n3873 $abc$24881$new_n3867 $abc$24881$new_n3899 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3901 DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22658 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3902 $abc$24881$new_n3901 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_dividend[53] DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3874 $abc$24881$new_n3902 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3904 DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22662 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[52] DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n3874 $abc$24881$new_n3867 $abc$24881$new_n3904 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3906 DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22666 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3907 $abc$24881$new_n3906 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_dividend[51] DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3875 $abc$24881$new_n3907 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3909 DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22670 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[50] DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n3875 $abc$24881$new_n3867 $abc$24881$new_n3909 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3911 DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22674 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3912 $abc$24881$new_n3911 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_dividend[49] DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3876 $abc$24881$new_n3912 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3914 DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22678 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[48] DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n3876 $abc$24881$new_n3867 $abc$24881$new_n3914 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3916 DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22682 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3917 $abc$24881$new_n3916 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[16] DIVIDE.thedivide.r_dividend[47] DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_dividend[46] $abc$24881$new_n3877 $abc$24881$new_n3917 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3919 DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22686 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n3877 $abc$24881$new_n3867 $abc$24881$new_n3919 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3921 DIVIDE.thedivide.r_dividend[46] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22690 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3922 $abc$24881$new_n3921 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_dividend[45] DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_dividend[44] $abc$24881$new_n3878 $abc$24881$new_n3922 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3924 DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22694 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n3878 $abc$24881$new_n3867 $abc$24881$new_n3924 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3926 DIVIDE.thedivide.r_dividend[44] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22698 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3927 $abc$24881$new_n3926 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[43] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n3879 $abc$24881$new_n3927 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3929 DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22702 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[42] DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n3879 $abc$24881$new_n3867 $abc$24881$new_n3929 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3931 DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22706 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3932 $abc$24881$new_n3931 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_dividend[41] DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3880 $abc$24881$new_n3932 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3934 DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22710 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[40] DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n3880 $abc$24881$new_n3867 $abc$24881$new_n3934 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3936 DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22714 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3937 $abc$24881$new_n3936 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[8] DIVIDE.thedivide.r_dividend[39] DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3881 $abc$24881$new_n3937 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3939 DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22718 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[38] DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n3881 $abc$24881$new_n3867 $abc$24881$new_n3939 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3941 DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22722 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3942 $abc$24881$new_n3941 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[6] DIVIDE.thedivide.r_dividend[37] DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3882 $abc$24881$new_n3942 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3944 DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22726 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[36] DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n3882 $abc$24881$new_n3867 $abc$24881$new_n3944 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3946 DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22730 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3947 $abc$24881$new_n3946 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[4] DIVIDE.thedivide.r_dividend[35] DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3883 $abc$24881$new_n3947 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3949 DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22734 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3950 $abc$24881$new_n3949 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3883 $abc$24881$new_n3950 +001 1 +010 1 +100 1 +111 1 +.names $abc$24881$new_n3952 DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22738 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3953 $abc$24881$new_n3952 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_dividend[33] DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_dividend[32] $abc$24881$new_n3884 $abc$24881$new_n3953 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3955 DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22742 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n3884 $abc$24881$new_n3867 $abc$24881$new_n3955 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3963 GEN_ALU_PC.r_alu_pc[30] SET_USER_PC.r_upc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$22744 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3958 $abc$24881$new_n3701 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n3957 +1000 1 +.names $abc$24881$new_n3698 $abc$24881$new_n3697 $abc$24881$new_n3959 $abc$24881$new_n3958 +000 1 +.names i_mem_valid dbgv $abc$24881$new_n3700 $abc$24881$new_n3959 +000 1 +.names SET_GIE.r_gie $abc$24881$new_n3961 $abc$24881$new_n3960 +10 1 +.names mem_pc_valid o_i_count SET_ALU_ILLEGAL.r_alu_illegal $abc$24881$new_n3961 +000 1 +001 1 +011 1 +.names r_alu_pc_valid new_pc DIVIDE.thedivide.o_busy o_i_count +100 1 +.names wr_index[1] wr_index[0] alu_result[30] i_mem_result[30] dbg_val[30] $abc$24881$new_n3963 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3965 GEN_ALU_PC.r_alu_pc[29] SET_USER_PC.r_upc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$22746 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[29] i_mem_result[29] dbg_val[29] $abc$24881$new_n3965 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3967 GEN_ALU_PC.r_alu_pc[28] SET_USER_PC.r_upc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$22748 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[28] i_mem_result[28] dbg_val[28] $abc$24881$new_n3967 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3969 GEN_ALU_PC.r_alu_pc[27] SET_USER_PC.r_upc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$22750 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[27] i_mem_result[27] dbg_val[27] $abc$24881$new_n3969 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3971 GEN_ALU_PC.r_alu_pc[26] SET_USER_PC.r_upc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$22752 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[26] i_mem_result[26] dbg_val[26] $abc$24881$new_n3971 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3973 GEN_ALU_PC.r_alu_pc[25] SET_USER_PC.r_upc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$22754 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[25] i_mem_result[25] dbg_val[25] $abc$24881$new_n3973 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3975 GEN_ALU_PC.r_alu_pc[24] SET_USER_PC.r_upc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$22756 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[24] i_mem_result[24] dbg_val[24] $abc$24881$new_n3975 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3977 GEN_ALU_PC.r_alu_pc[23] SET_USER_PC.r_upc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$22758 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[23] i_mem_result[23] dbg_val[23] $abc$24881$new_n3977 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3979 GEN_ALU_PC.r_alu_pc[22] SET_USER_PC.r_upc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$22760 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[22] i_mem_result[22] dbg_val[22] $abc$24881$new_n3979 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3981 GEN_ALU_PC.r_alu_pc[21] SET_USER_PC.r_upc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$22762 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[21] i_mem_result[21] dbg_val[21] $abc$24881$new_n3981 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3983 GEN_ALU_PC.r_alu_pc[20] SET_USER_PC.r_upc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$22764 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[20] i_mem_result[20] dbg_val[20] $abc$24881$new_n3983 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3985 GEN_ALU_PC.r_alu_pc[19] SET_USER_PC.r_upc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$22766 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[19] i_mem_result[19] dbg_val[19] $abc$24881$new_n3985 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3987 GEN_ALU_PC.r_alu_pc[18] SET_USER_PC.r_upc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$22768 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[18] i_mem_result[18] dbg_val[18] $abc$24881$new_n3987 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3989 GEN_ALU_PC.r_alu_pc[17] SET_USER_PC.r_upc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$22770 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[17] i_mem_result[17] dbg_val[17] $abc$24881$new_n3989 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3991 GEN_ALU_PC.r_alu_pc[16] SET_USER_PC.r_upc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$22772 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[16] i_mem_result[16] dbg_val[16] $abc$24881$new_n3991 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3993 GEN_ALU_PC.r_alu_pc[15] SET_USER_PC.r_upc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$22774 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[15] i_mem_result[15] dbg_val[15] $abc$24881$new_n3993 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3995 GEN_ALU_PC.r_alu_pc[14] SET_USER_PC.r_upc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$22776 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[14] i_mem_result[14] dbg_val[14] $abc$24881$new_n3995 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3997 GEN_ALU_PC.r_alu_pc[13] SET_USER_PC.r_upc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22778 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[13] i_mem_result[13] dbg_val[13] $abc$24881$new_n3997 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3999 GEN_ALU_PC.r_alu_pc[12] SET_USER_PC.r_upc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$22780 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[12] i_mem_result[12] dbg_val[12] $abc$24881$new_n3999 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4001 GEN_ALU_PC.r_alu_pc[11] SET_USER_PC.r_upc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22782 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[11] i_mem_result[11] dbg_val[11] $abc$24881$new_n4001 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4003 GEN_ALU_PC.r_alu_pc[10] SET_USER_PC.r_upc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$22784 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[10] i_mem_result[10] dbg_val[10] $abc$24881$new_n4003 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4005 GEN_ALU_PC.r_alu_pc[9] SET_USER_PC.r_upc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$22786 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[9] i_mem_result[9] dbg_val[9] $abc$24881$new_n4005 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4007 GEN_ALU_PC.r_alu_pc[8] SET_USER_PC.r_upc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22788 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[8] i_mem_result[8] dbg_val[8] $abc$24881$new_n4007 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4009 GEN_ALU_PC.r_alu_pc[7] SET_USER_PC.r_upc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22790 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[7] i_mem_result[7] dbg_val[7] $abc$24881$new_n4009 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4011 GEN_ALU_PC.r_alu_pc[6] SET_USER_PC.r_upc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22792 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[6] i_mem_result[6] dbg_val[6] $abc$24881$new_n4011 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4013 GEN_ALU_PC.r_alu_pc[5] SET_USER_PC.r_upc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22794 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[5] i_mem_result[5] dbg_val[5] $abc$24881$new_n4013 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4015 GEN_ALU_PC.r_alu_pc[4] SET_USER_PC.r_upc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22796 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[4] i_mem_result[4] dbg_val[4] $abc$24881$new_n4015 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4017 GEN_ALU_PC.r_alu_pc[3] SET_USER_PC.r_upc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22798 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[3] i_mem_result[3] dbg_val[3] $abc$24881$new_n4017 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4019 GEN_ALU_PC.r_alu_pc[2] SET_USER_PC.r_upc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22800 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[2] i_mem_result[2] dbg_val[2] $abc$24881$new_n4019 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4123 $abc$24881$new_n4021 $abc$24881$new_n4122 $abc$24881$new_n3963 $abc$24881$auto$rtlil.cc:2693:MuxGate$22802 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4022 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4106 $abc$24881$new_n4121 $abc$24881$new_n4021 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4023 $abc$24881$new_n4087 SET_USER_PC.r_upc[30] $abc$24881$new_n4022 +0001 1 +0010 1 +0011 1 +.names $abc$24881$new_n4024 pf_pc[30] pf_pc[28] pf_pc[29] $abc$24881$new_n4090 $abc$24881$new_n4023 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4024 +10 1 +.names $abc$24881$new_n4026 $abc$24881$new_n4086 i_reset $abc$24881$new_n4025 +000 1 +001 1 +011 1 +.names $abc$24881$new_n4075 $abc$24881$new_n4081 new_pc $abc$24881$new_n4085 o_pf_ready $abc$24881$new_n4026 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4028 o_pf_ready +00 1 +.names instruction_decoder.r_valid $abc$24881$new_n4029 $abc$24881$new_n4028 +10 1 +.names instruction_decoder.r_valid op_valid $abc$24881$new_n4030 $abc$24881$new_n4051 $abc$24881$new_n4073 $abc$24881$new_n4029 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10110 1 +11010 1 +.names mem_ce $abc$24881$new_n4031 $abc$24881$new_n4030 +00 1 +.names $abc$24881$new_n4032 i_mem_rdbusy op_valid_mem $abc$24881$new_n4047 $abc$24881$new_n4031 +1000 1 +.names $abc$24881$new_n4033 $abc$24881$new_n4040 r_op_break BUSLOCK.r_prelock_stall DIVERR.r_idiv_err_flag $abc$24881$new_n4032 +11000 1 +.names $abc$24881$new_n4037 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n4033 +10 1 +.names $abc$24881$new_n3697 $abc$24881$new_n4035 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y +11 1 +.names $abc$24881$new_n4036 $abc$24881$new_n3959 $abc$24881$new_n4035 +10 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3698 $abc$24881$new_n3695 $abc$24881$new_n4036 +000 1 +.names last_write_to_cc o_break sleep GEN_ALU_PHASE.r_alu_phase i_halt $abc$24881$new_n4037 +00000 1 +00010 1 +00011 1 +.names $abc$24881$new_n4039 ill_err_i SET_GIE.r_gie i_bus_err DIVIDE.thedivide.o_err o_break +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names new_pc GEN_PENDING_BREAK.r_break_pending SET_GIE.r_gie SET_ALU_ILLEGAL.r_alu_illegal break_en $abc$24881$new_n4039 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4044 $abc$24881$new_n4046 $abc$24881$new_n4041 $abc$24881$new_n4040 +100 1 +.names $abc$24881$new_n4042 GEN_PENDING_INTERRUPT.r_pending_interrupt i_halt $abc$24881$new_n4041 +110 1 +.names GEN_ALU_PHASE.r_alu_phase o_bus_lock $abc$24881$new_n4042 +00 1 +.names BUSLOCK.r_bus_lock[1] BUSLOCK.r_bus_lock[0] o_bus_lock +01 1 +10 1 +11 1 +.names $abc$24881$new_n4045 i_mem_busy op_valid_div op_illegal $abc$24881$new_n4044 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names op_valid SET_ALU_ILLEGAL.r_alu_illegal ibus_err_flag DIVIDE.thedivide.o_busy $abc$24881$new_n4045 +1000 1 +.names user_step GEN_PENDING_INTERRUPT.r_user_stepped SET_GIE.r_gie $abc$24881$new_n4046 +111 1 +.names i_mem_busy $abc$24881$new_n4048 SET_GIE.r_gie o_mem_reg[4] o_mem_reg[0] $abc$24881$new_n4047 +11000 1 +11110 1 +.names GEN_OP_WR.r_op_wR o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] $abc$24881$new_n4048 +1111 1 +.names $abc$24881$new_n4050 $abc$24881$new_n4032 i_bus_err DIVIDE.thedivide.o_err $abc$24881$new_n4035 mem_ce +11000 1 +.names op_valid_mem i_mem_pipe_stalled new_pc GEN_OP_PIPE.r_op_pipe i_mem_busy $abc$24881$new_n4050 +10000 1 +10010 1 +10011 1 +.names i_halt $abc$24881$new_n4064 $abc$24881$new_n9842 $abc$24881$new_n4072 dcd_rB $abc$24881$new_n4051 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names instruction_decoder.o_dcdB[3] alu_reg[3] alu_reg[4] instruction_decoder.o_dcdB[4] $abc$24881$new_n4062 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$24881$new_n4065 $abc$24881$new_n4067 dcd_F[3] instruction_decoder.o_dcdA[2] $abc$24881$new_n4070 $abc$24881$new_n4064 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names GEN_OP_STALL.r_pending_sreg_write op_valid $abc$24881$new_n4048 $abc$24881$new_n4066 $abc$24881$new_n4065 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names o_mem_reg[0] SET_GIE.r_gie o_mem_reg[4] $abc$24881$new_n4066 +100 1 +111 1 +.names dcd_rB $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] $abc$24881$new_n4068 instruction_decoder.o_dcdB[0] $abc$24881$new_n4067 +11100 1 +11101 1 +11110 1 +.names SET_GIE.r_gie instruction_decoder.o_dcdB[4] $abc$24881$new_n4068 +00 1 +11 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4069 +11 1 +.names dcd_rA instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n4071 instruction_decoder.o_dcdA[0] $abc$24881$new_n4070 +11100 1 +11101 1 +11110 1 +.names SET_GIE.r_gie instruction_decoder.o_dcdA[4] $abc$24881$new_n4071 +00 1 +11 1 +.names i_mem_rdbusy op_valid DIVIDE.thedivide.o_busy $abc$24881$new_n4072 +000 1 +.names GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n4074 $abc$24881$new_n4072 dcd_Bcc dcd_rB $abc$24881$new_n4073 +01000 1 +01001 1 +01010 1 +01011 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_rA dcd_Acc op_wF GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n4074 +1101 1 +1110 1 +1111 1 +.names $abc$24881$auto$opt_dff.cc:253:combine_resets$3432 SET_GIE.r_gie dbg_clear_pipe o_clear_icache $abc$24881$new_n4075 +0000 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_reset $abc$24881$new_n4077 $abc$24881$auto$opt_dff.cc:253:combine_resets$3432 +01 1 +10 1 +11 1 +.names SET_GIE.r_gie $abc$24881$new_n4078 $abc$24881$new_n4077 +10 1 +.names $abc$24881$new_n4080 $abc$24881$new_n4079 $abc$24881$new_n4013 $abc$24881$new_n4078 +100 1 +101 1 +110 1 +.names $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n3694 $abc$24881$new_n4079 +10 1 +.names i_bus_err DIVIDE.thedivide.o_err $abc$24881$new_n4041 i_mem_busy $abc$24881$new_n4080 +0000 1 +0001 1 +0011 1 +.names $abc$24881$new_n4082 $abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y SET_GIE.r_gie dbg_clear_pipe o_clear_icache $abc$24881$new_n4081 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names $abc$24881$new_n4083 i_interrupt SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n4082 +1000 1 +.names $abc$24881$new_n3694 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n4083 +11 1 +.names $abc$24881$new_n4035 SET_GIE.r_gie $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y +1010 1 +1100 1 +.names i_pf_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb $abc$24881$new_n4085 +10 1 +.names dbgv $abc$24881$new_n4036 SET_GIE.r_gie $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$new_n4086 +11010 1 +11100 1 +.names $abc$24881$new_n4088 o_pf_new_pc o_pf_ready $abc$24881$new_n4085 $abc$24881$new_n4087 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4081 $abc$24881$new_n4075 $abc$24881$new_n4088 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc o_pf_new_pc +01 1 +10 1 +11 1 +.names pf_pc[27] $abc$24881$new_n4091 $abc$24881$new_n4090 +11 1 +.names pf_pc[26] $abc$24881$new_n4092 $abc$24881$new_n4091 +11 1 +.names pf_pc[25] $abc$24881$new_n4093 $abc$24881$new_n4092 +11 1 +.names pf_pc[22] pf_pc[23] pf_pc[24] $abc$24881$new_n4094 $abc$24881$new_n4093 +1111 1 +.names pf_pc[19] pf_pc[20] pf_pc[21] $abc$24881$new_n4095 $abc$24881$new_n4094 +1111 1 +.names pf_pc[18] $abc$24881$new_n4096 $abc$24881$new_n4095 +11 1 +.names pf_pc[17] $abc$24881$new_n4097 $abc$24881$new_n4096 +11 1 +.names pf_pc[16] $abc$24881$new_n4098 $abc$24881$new_n4097 +11 1 +.names pf_pc[13] pf_pc[14] pf_pc[15] $abc$24881$new_n4099 $abc$24881$new_n4098 +1111 1 +.names pf_pc[11] pf_pc[12] $abc$24881$new_n4100 $abc$24881$new_n4099 +111 1 +.names pf_pc[7] pf_pc[8] pf_pc[9] pf_pc[10] $abc$24881$new_n4101 $abc$24881$new_n4100 +11111 1 +.names pf_pc[6] $abc$24881$new_n4102 $abc$24881$new_n4101 +11 1 +.names pf_pc[2] pf_pc[3] pf_pc[4] pf_pc[5] $abc$24881$new_n4102 +1111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4026 $abc$24881$new_n4104 $abc$24881$new_n4103 +000 1 +001 1 +010 1 +.names i_reset $abc$24881$new_n4086 $abc$24881$new_n4105 $abc$24881$new_n4104 +000 1 +.names dbg_clear_pipe o_clear_icache $abc$24881$new_n4082 $abc$24881$new_n4077 $abc$24881$new_n4105 +0000 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n4107 $abc$24881$new_n4106 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n4108 $abc$24881$new_n4107 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$new_n4109 $abc$24881$new_n4108 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n4110 $abc$24881$new_n4109 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n4111 $abc$24881$new_n4110 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$new_n4112 $abc$24881$new_n4111 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$new_n4113 $abc$24881$new_n4112 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] $abc$24881$new_n4114 $abc$24881$new_n4113 +11111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n4115 $abc$24881$new_n4114 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] $abc$24881$new_n4116 $abc$24881$new_n4115 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n4117 $abc$24881$new_n4116 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] $abc$24881$new_n4118 $abc$24881$new_n4117 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] $abc$24881$new_n4119 $abc$24881$new_n4118 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$new_n4120 $abc$24881$new_n4119 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] $abc$24881$new_n4120 +111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4121 +11 1 +.names $abc$24881$new_n4104 $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4122 +000 1 +.names ipc[30] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[30] $abc$24881$new_n4123 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4104 $abc$24881$new_n4026 $abc$24881$new_n4124 +10 1 +.names $abc$24881$new_n4088 o_pf_new_pc o_pf_ready $abc$24881$new_n4085 $abc$24881$new_n4125 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4129 $abc$24881$new_n4127 $abc$24881$new_n4128 $abc$24881$new_n4103 $abc$24881$auto$rtlil.cc:2693:MuxGate$22804 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names $abc$24881$new_n4121 $abc$24881$new_n4024 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4106 SET_USER_PC.r_upc[29] $abc$24881$new_n4127 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10110 1 +10111 1 +.names $abc$24881$new_n4024 pf_pc[29] pf_pc[28] $abc$24881$new_n4090 $abc$24881$new_n4128 +1000 1 +1001 1 +1010 1 +1111 1 +.names $abc$24881$new_n4130 $abc$24881$new_n4122 $abc$24881$new_n3965 $abc$24881$new_n4129 +100 1 +101 1 +111 1 +.names ipc[29] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[29] $abc$24881$new_n4130 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4132 pf_pc[28] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22806 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4133 $abc$24881$new_n3967 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[28] $abc$24881$new_n4132 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n4107 $abc$24881$new_n4134 $abc$24881$new_n4133 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 pf_pc[28] $abc$24881$new_n4090 $abc$24881$new_n4025 SET_USER_PC.r_upc[28] $abc$24881$new_n4134 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4136 pf_pc[27] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22808 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4137 $abc$24881$new_n3969 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[27] $abc$24881$new_n4136 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[27] $abc$24881$new_n4091 $abc$24881$new_n4138 $abc$24881$new_n4137 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n4108 SET_USER_PC.r_upc[27] $abc$24881$new_n4138 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4140 pf_pc[26] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22810 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4141 $abc$24881$new_n3971 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[26] $abc$24881$new_n4140 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$new_n4109 $abc$24881$new_n4142 $abc$24881$new_n4141 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 pf_pc[26] $abc$24881$new_n4092 $abc$24881$new_n4025 SET_USER_PC.r_upc[26] $abc$24881$new_n4142 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4144 ipc[25] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22812 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4145 $abc$24881$new_n3973 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[25] $abc$24881$new_n4144 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[25] $abc$24881$new_n4093 $abc$24881$new_n4146 $abc$24881$new_n4145 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n4110 SET_USER_PC.r_upc[25] $abc$24881$new_n4146 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4148 $abc$24881$new_n4122 $abc$24881$new_n3975 $abc$24881$auto$rtlil.cc:2693:MuxGate$22814 +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$24881$new_n4151 $abc$24881$new_n4103 $abc$24881$new_n4150 $abc$24881$new_n4149 $abc$24881$new_n4148 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[24] pf_pc[22] pf_pc[23] $abc$24881$new_n4094 $abc$24881$new_n4149 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n4111 SET_USER_PC.r_upc[24] $abc$24881$new_n4150 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ipc[24] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[24] $abc$24881$new_n4151 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4153 pf_pc[23] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22816 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4155 $abc$24881$new_n4103 $abc$24881$new_n4156 $abc$24881$new_n4154 $abc$24881$new_n4153 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[23] pf_pc[22] $abc$24881$new_n4094 $abc$24881$new_n4154 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3977 ipc[23] $abc$24881$new_n4124 $abc$24881$new_n4155 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$new_n4112 SET_USER_PC.r_upc[23] $abc$24881$new_n4156 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3979 pf_pc[22] $abc$24881$new_n4125 $abc$24881$new_n4160 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4163 ipc[21] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22820 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4165 $abc$24881$new_n4103 $abc$24881$new_n4166 $abc$24881$new_n4164 $abc$24881$new_n4163 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[21] pf_pc[19] pf_pc[20] $abc$24881$new_n4095 $abc$24881$new_n4164 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3981 pf_pc[21] $abc$24881$new_n4125 $abc$24881$new_n4165 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] $abc$24881$new_n4113 SET_USER_PC.r_upc[21] $abc$24881$new_n4166 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4125 $abc$24881$new_n4168 pf_pc[20] $abc$24881$new_n4169 $abc$24881$new_n4103 $abc$24881$auto$rtlil.cc:2693:MuxGate$22822 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4124 ipc[20] $abc$24881$new_n4122 $abc$24881$new_n3983 $abc$24881$new_n4168 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[20] $abc$24881$new_n4171 $abc$24881$new_n4170 $abc$24881$new_n4169 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names pf_pc[20] pf_pc[19] $abc$24881$new_n4095 $abc$24881$new_n4170 +011 1 +100 1 +101 1 +110 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] $abc$24881$new_n4114 $abc$24881$new_n4171 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4173 ipc[19] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22824 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4175 $abc$24881$new_n4103 $abc$24881$new_n4176 $abc$24881$new_n4174 $abc$24881$new_n4173 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] $abc$24881$new_n4114 $abc$24881$new_n4174 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3985 pf_pc[19] $abc$24881$new_n4125 $abc$24881$new_n4175 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 pf_pc[19] $abc$24881$new_n4095 $abc$24881$new_n4025 SET_USER_PC.r_upc[19] $abc$24881$new_n4176 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4178 ipc[18] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22826 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4179 $abc$24881$new_n3987 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[18] $abc$24881$new_n4178 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4180 $abc$24881$new_n4181 SET_USER_PC.r_upc[18] $abc$24881$new_n4087 $abc$24881$new_n4179 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4024 pf_pc[18] $abc$24881$new_n4096 $abc$24881$new_n4180 +101 1 +110 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n4114 $abc$24881$new_n4181 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4183 ipc[17] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22828 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4184 $abc$24881$new_n3989 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[17] $abc$24881$new_n4183 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[17] $abc$24881$new_n4097 $abc$24881$new_n4185 $abc$24881$new_n4184 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n4114 SET_USER_PC.r_upc[17] $abc$24881$new_n4185 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4187 ipc[16] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22830 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4188 $abc$24881$new_n3991 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[16] $abc$24881$new_n4187 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[16] $abc$24881$new_n4098 $abc$24881$new_n4189 $abc$24881$new_n4188 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n4115 SET_USER_PC.r_upc[16] $abc$24881$new_n4189 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4194 $abc$24881$new_n3993 $abc$24881$new_n4122 $abc$24881$new_n4103 $abc$24881$new_n4191 $abc$24881$auto$rtlil.cc:2693:MuxGate$22832 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[15] $abc$24881$new_n4192 $abc$24881$new_n4193 $abc$24881$new_n4191 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n4116 $abc$24881$new_n4192 +011 1 +100 1 +101 1 +110 1 +.names pf_pc[15] pf_pc[13] pf_pc[14] $abc$24881$new_n4099 $abc$24881$new_n4193 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ipc[15] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[15] $abc$24881$new_n4194 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3995 pf_pc[14] $abc$24881$new_n4125 $abc$24881$new_n4198 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3997 pf_pc[13] $abc$24881$new_n4125 $abc$24881$new_n4203 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4208 $abc$24881$new_n4103 $abc$24881$new_n4206 $abc$24881$new_n4122 $abc$24881$new_n3999 $abc$24881$auto$rtlil.cc:2693:MuxGate$22838 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11110 1 +.names $abc$24881$new_n4207 pf_pc[12] pf_pc[11] $abc$24881$new_n4100 $abc$24881$new_n4024 $abc$24881$new_n4206 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n4117 SET_USER_PC.r_upc[12] $abc$24881$new_n4207 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ipc[12] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[12] $abc$24881$new_n4208 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4210 ipc[11] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22840 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4212 $abc$24881$new_n4103 $abc$24881$new_n4213 $abc$24881$new_n4211 $abc$24881$new_n4210 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] $abc$24881$new_n4118 $abc$24881$new_n4211 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n4001 pf_pc[11] $abc$24881$new_n4125 $abc$24881$new_n4212 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 pf_pc[11] $abc$24881$new_n4100 $abc$24881$new_n4025 SET_USER_PC.r_upc[11] $abc$24881$new_n4213 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4218 $abc$24881$new_n4103 $abc$24881$new_n4215 $abc$24881$new_n4122 $abc$24881$new_n4003 $abc$24881$auto$rtlil.cc:2693:MuxGate$22842 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11110 1 +.names $abc$24881$new_n4024 $abc$24881$new_n4216 $abc$24881$new_n4217 SET_USER_PC.r_upc[10] $abc$24881$new_n4087 $abc$24881$new_n4215 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n4118 $abc$24881$new_n4216 +1000 1 +1001 1 +1010 1 +1111 1 +.names pf_pc[10] pf_pc[7] pf_pc[8] pf_pc[9] $abc$24881$new_n4101 $abc$24881$new_n4217 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names ipc[10] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[10] $abc$24881$new_n4218 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4220 pf_pc[9] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22844 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4222 $abc$24881$new_n4103 $abc$24881$new_n4221 $abc$24881$new_n4223 $abc$24881$new_n4220 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[9] pf_pc[7] pf_pc[8] $abc$24881$new_n4101 $abc$24881$new_n4221 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n4005 ipc[9] $abc$24881$new_n4124 $abc$24881$new_n4222 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n4118 SET_USER_PC.r_upc[9] $abc$24881$new_n4223 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4228 $abc$24881$new_n4007 $abc$24881$new_n4122 $abc$24881$new_n4103 $abc$24881$new_n4225 $abc$24881$auto$rtlil.cc:2693:MuxGate$22846 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[8] $abc$24881$new_n4227 $abc$24881$new_n4226 $abc$24881$new_n4225 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pf_pc[8] pf_pc[7] $abc$24881$new_n4101 $abc$24881$new_n4226 +011 1 +100 1 +101 1 +110 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$new_n4119 $abc$24881$new_n4227 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ipc[8] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[8] $abc$24881$new_n4228 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4122 $abc$24881$new_n4009 pf_pc[7] $abc$24881$new_n4125 $abc$24881$new_n4232 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4235 ipc[6] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22850 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4236 $abc$24881$new_n4011 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[6] $abc$24881$new_n4235 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[6] $abc$24881$new_n4102 $abc$24881$new_n4237 $abc$24881$new_n4236 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n4119 SET_USER_PC.r_upc[6] $abc$24881$new_n4237 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4239 pf_pc[5] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22852 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4241 $abc$24881$new_n4103 $abc$24881$new_n4240 $abc$24881$new_n4242 $abc$24881$new_n4239 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[5] pf_pc[2] pf_pc[3] pf_pc[4] $abc$24881$new_n4240 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n4013 ipc[5] $abc$24881$new_n4124 $abc$24881$new_n4241 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$new_n4120 SET_USER_PC.r_upc[5] $abc$24881$new_n4242 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4244 pf_pc[4] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22854 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4245 $abc$24881$new_n4015 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[4] $abc$24881$new_n4244 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4246 $abc$24881$new_n4247 SET_USER_PC.r_upc[4] $abc$24881$new_n4087 $abc$24881$new_n4245 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4024 pf_pc[4] pf_pc[2] pf_pc[3] $abc$24881$new_n4246 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] $abc$24881$new_n4247 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4249 pf_pc[3] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22856 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4250 $abc$24881$new_n4017 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[3] $abc$24881$new_n4249 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[2] pf_pc[3] $abc$24881$new_n4251 $abc$24881$new_n4250 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] SET_USER_PC.r_upc[3] $abc$24881$new_n4251 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4087 SET_USER_PC.r_upc[2] $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] $abc$24881$new_n4255 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 dcd_Bpc $abc$24881$new_n4257 $abc$24881$new_n4292 $abc$24881$auto$rtlil.cc:2693:MuxGate$22860 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4284 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n4258 $abc$24881$new_n4257 +1100 1 +.names $abc$24881$new_n4281 $abc$24881$new_n4266 $abc$24881$new_n4259 $abc$24881$new_n4274 $abc$24881$new_n4283 $abc$24881$new_n4258 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$24881$new_n4260 $abc$24881$new_n4271 $abc$24881$new_n4273 $abc$24881$new_n4259 +001 1 +010 1 +011 1 +.names $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4261 $abc$24881$new_n4260 +110 1 +.names $abc$24881$new_n4268 $abc$24881$new_n4262 $abc$24881$new_n4261 +10 1 +.names $abc$24881$new_n4267 $abc$24881$new_n4263 $abc$24881$new_n4266 $abc$24881$new_n4262 +001 1 +010 1 +011 1 +.names $abc$24881$new_n4265 $abc$24881$new_n4264 $abc$24881$new_n4263 +00 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[9] i_pf_instruction[25] $abc$24881$new_n4264 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[10] i_pf_instruction[26] $abc$24881$new_n4265 +000 1 +010 1 +100 1 +101 1 +.names i_pf_instruction[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4266 +00 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[8] i_pf_instruction[24] $abc$24881$new_n4267 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 $abc$24881$new_n4265 $abc$24881$new_n4264 i_pf_instruction[23] $abc$24881$new_n4267 $abc$24881$new_n4268 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n4263 $abc$24881$new_n4266 i_pf_instruction[25] $abc$24881$new_n4269 +000 1 +001 1 +010 1 +.names $abc$24881$new_n4265 $abc$24881$new_n4267 $abc$24881$new_n4264 $abc$24881$new_n4266 $abc$24881$new_n4270 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names $abc$24881$new_n4268 $abc$24881$new_n4272 $abc$24881$new_n4271 +11 1 +.names $abc$24881$new_n4267 $abc$24881$new_n4263 $abc$24881$new_n4272 +11 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[7] i_pf_instruction[23] $abc$24881$new_n4273 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 $abc$24881$new_n4275 $abc$24881$new_n4271 $abc$24881$new_n4274 +100 1 +.names $abc$24881$new_n4276 $abc$24881$new_n4277 $abc$24881$new_n4267 $abc$24881$new_n4275 +110 1 +.names i_pf_instruction[25] $abc$24881$new_n4266 $abc$24881$new_n4265 $abc$24881$new_n4276 +110 1 +.names $abc$24881$new_n4280 $abc$24881$new_n4279 $abc$24881$new_n4278 $abc$24881$new_n4277 +000 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[13] i_pf_instruction[29] $abc$24881$new_n4278 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[12] i_pf_instruction[28] $abc$24881$new_n4279 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[14] i_pf_instruction[30] $abc$24881$new_n4280 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4268 $abc$24881$new_n4267 $abc$24881$new_n4282 $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4281 +10000 1 +.names $abc$24881$new_n4266 i_pf_instruction[22] $abc$24881$new_n4267 $abc$24881$new_n4265 $abc$24881$new_n4264 $abc$24881$new_n4282 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[2] i_pf_instruction[18] $abc$24881$new_n4283 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 i_pf_instruction[17] $abc$24881$new_n4287 $abc$24881$new_n4285 $abc$24881$new_n4284 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4273 $abc$24881$new_n4286 $abc$24881$new_n4285 +11 1 +.names $abc$24881$new_n4264 $abc$24881$new_n4265 $abc$24881$new_n4286 +10 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[6] i_pf_instruction[22] $abc$24881$new_n4287 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 i_pf_instruction[16] $abc$24881$new_n4289 $abc$24881$new_n4285 $abc$24881$new_n4288 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[5] i_pf_instruction[21] $abc$24881$new_n4289 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 i_pf_instruction[15] $abc$24881$new_n4291 $abc$24881$new_n4285 $abc$24881$new_n4290 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[4] i_pf_instruction[20] $abc$24881$new_n4291 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4293 i_pf_instruction[31] $abc$24881$new_n4285 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction[14] $abc$24881$new_n4292 +00000 1 +00100 1 +10000 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[3] i_pf_instruction[19] $abc$24881$new_n4293 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[4] SET_GIE.r_gie $abc$24881$new_n4295 i_pf_instruction[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22862 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n4281 $abc$24881$new_n4295 +11 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[3] $abc$24881$new_n4284 $abc$24881$auto$rtlil.cc:2693:MuxGate$22864 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[2] $abc$24881$new_n4288 $abc$24881$auto$rtlil.cc:2693:MuxGate$22866 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[1] $abc$24881$new_n4290 $abc$24881$auto$rtlil.cc:2693:MuxGate$22868 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[0] $abc$24881$new_n4292 $abc$24881$auto$rtlil.cc:2693:MuxGate$22870 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 dcd_Apc $abc$24881$new_n4301 $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$22872 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4277 $abc$24881$new_n4295 SET_GIE.r_gie $abc$24881$new_n4283 $abc$24881$new_n4301 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[11] i_pf_instruction[27] $abc$24881$new_n4302 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[4] SET_GIE.r_gie $abc$24881$new_n4295 $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$22874 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[3] $abc$24881$new_n4280 $abc$24881$auto$rtlil.cc:2693:MuxGate$22876 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[2] $abc$24881$new_n4278 $abc$24881$auto$rtlil.cc:2693:MuxGate$22878 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[1] $abc$24881$new_n4279 $abc$24881$auto$rtlil.cc:2693:MuxGate$22880 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[0] $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$22882 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[13] i_pf_instruction[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22884 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[12] i_pf_instruction[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$22886 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[11] i_pf_instruction[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22888 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[10] i_pf_instruction[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$22890 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[9] i_pf_instruction[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$22892 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[8] i_pf_instruction[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22894 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[7] i_pf_instruction[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22896 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[6] i_pf_instruction[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22898 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[5] i_pf_instruction[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22900 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[4] i_pf_instruction[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22902 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[3] i_pf_instruction[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22904 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[2] i_pf_instruction[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22906 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[1] i_pf_instruction[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22908 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[0] i_pf_instruction[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22910 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 dcd_opn[2] $abc$24881$new_n4323 $abc$24881$new_n4262 $abc$24881$auto$rtlil.cc:2693:MuxGate$22914 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4271 $abc$24881$new_n4275 $abc$24881$new_n4287 $abc$24881$new_n4273 $abc$24881$new_n4323 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$24881$new_n4028 dcd_opn[1] $abc$24881$new_n4323 $abc$24881$new_n4268 $abc$24881$auto$rtlil.cc:2693:MuxGate$22918 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 dcd_opn[0] $abc$24881$new_n4282 $abc$24881$new_n4323 $abc$24881$auto$rtlil.cc:2693:MuxGate$22922 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5065 $abc$24881$new_n5090 dcd_I[31] $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n4327 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11111 1 +.names $abc$24881$new_n4995 dcd_I[31] $abc$24881$new_n9877 $abc$24881$new_n5041 $abc$24881$new_n4329 $abc$24881$new_n4328 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4972 $abc$24881$new_n4925 $abc$24881$new_n4948 $abc$24881$new_n9843 $abc$24881$new_n4971 $abc$24881$new_n4329 +11000 1 +11001 1 +11011 1 +.names $abc$24881$new_n9502 dcd_I[13] dcd_I[14] $abc$24881$new_n9505 $abc$24881$new_n9847 $abc$24881$new_n4334 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n4635 dcd_I[10] $abc$24881$new_n9496 $abc$24881$new_n4658 $abc$24881$new_n4337 $abc$24881$new_n4336 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n4566 dcd_I[8] $abc$24881$new_n4591 $abc$24881$new_n4590 $abc$24881$new_n4338 $abc$24881$new_n4337 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9489 dcd_I[5] dcd_I[6] $abc$24881$new_n9873 $abc$24881$new_n4339 $abc$24881$new_n4338 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n4406 dcd_I[4] dcd_I[3] $abc$24881$new_n9436 $abc$24881$new_n9858 $abc$24881$new_n4339 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4345 regset[29][4] regset[25][4] $abc$24881$new_n4344 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][4] regset[24][4] $abc$24881$new_n4345 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4348 regset[21][4] regset[17][4] $abc$24881$new_n4347 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][4] regset[16][4] $abc$24881$new_n4348 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4349 +00 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4352 regset[31][4] regset[27][4] $abc$24881$new_n4351 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][4] regset[26][4] $abc$24881$new_n4352 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4355 regset[23][4] regset[19][4] $abc$24881$new_n4354 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][4] regset[18][4] $abc$24881$new_n4355 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4356 +10 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4359 $abc$24881$new_n4361 $abc$24881$new_n4363 $abc$24881$new_n4358 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4360 regset[5][4] regset[1][4] $abc$24881$new_n4359 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][4] regset[0][4] $abc$24881$new_n4360 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4362 regset[7][4] regset[3][4] $abc$24881$new_n4361 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][4] regset[2][4] $abc$24881$new_n4362 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4364 regset[15][4] regset[11][4] $abc$24881$new_n4363 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][4] regset[10][4] $abc$24881$new_n4364 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4366 regset[13][4] regset[9][4] $abc$24881$new_n4365 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][4] regset[8][4] $abc$24881$new_n4366 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4368 $abc$24881$new_n3843 $abc$24881$new_n4367 +10 1 +.names dcd_rB $abc$24881$new_n4371 $abc$24881$new_n4369 $abc$24881$new_n3959 $abc$24881$new_n4368 +1110 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] $abc$24881$new_n3701 $abc$24881$new_n3698 $abc$24881$new_n4370 $abc$24881$new_n4369 +00110 1 +01010 1 +10100 1 +11000 1 +.names instruction_decoder.o_dcdB[0] i_mem_valid alu_reg[0] i_mem_wreg[0] $abc$24881$new_n4370 +1000 1 +1001 1 +1100 1 +1110 1 +.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n4372 $abc$24881$new_n4371 +00110 1 +01010 1 +10100 1 +11000 1 +.names i_mem_valid instruction_decoder.o_dcdB[0] alu_reg[0] i_mem_wreg[0] $abc$24881$new_n4372 +0010 1 +0011 1 +1001 1 +1011 1 +.names dcd_rB $abc$24881$new_n4369 $abc$24881$new_n4371 $abc$24881$new_n3959 $abc$24881$new_n4373 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][3] regset[18][3] $abc$24881$new_n4381 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][3] regset[19][3] $abc$24881$new_n4382 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4384 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][3] regset[16][3] $abc$24881$new_n4383 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][3] regset[17][3] $abc$24881$new_n4384 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4386 regset[31][3] regset[27][3] $abc$24881$new_n4385 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][3] regset[26][3] $abc$24881$new_n4386 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4389 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][3] regset[3][3] $abc$24881$new_n4388 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][3] regset[2][3] $abc$24881$new_n4389 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4391 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][3] regset[0][3] $abc$24881$new_n4390 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][3] regset[1][3] $abc$24881$new_n4391 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4394 regset[15][3] regset[11][3] $abc$24881$new_n4393 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][3] regset[10][3] $abc$24881$new_n4394 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4396 $abc$24881$new_n4395 +100 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4397 regset[13][3] regset[9][3] $abc$24881$new_n4396 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][3] regset[8][3] $abc$24881$new_n4397 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n4398 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4400 $abc$24881$new_n4403 flags[3] $abc$24881$new_n4399 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4402 $abc$24881$new_n4401 $abc$24881$new_n4400 +11 1 +.names alu_wF doalu.o_valid DIVIDE.thedivide.o_valid DIVIDE.thedivide.o_err $abc$24881$new_n4401 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names SET_GIE.r_gie new_pc $abc$24881$new_n4402 +10 1 +.names doalu.set_ovfl wr_index[1] doalu.n doalu.pre_sign wr_index[0] $abc$24881$new_n4403 +11010 1 +11100 1 +.names $abc$24881$new_n4405 $abc$24881$new_n4403 iflags[3] $abc$24881$new_n4404 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4401 new_pc SET_GIE.r_gie $abc$24881$new_n4405 +100 1 +.names dcd_I[2] dcd_I[1] $abc$24881$new_n4471 $abc$24881$new_n4439 $abc$24881$new_n9442 $abc$24881$new_n4406 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][2] regset[11][2] $abc$24881$new_n4413 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][2] regset[10][2] $abc$24881$new_n4414 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[1] $abc$24881$new_n4417 $abc$24881$new_n4418 $abc$24881$new_n4416 +10000 1 +10010 1 +11000 1 +11001 1 +.names instruction_decoder.o_dcdB[2] regset[29][2] regset[25][2] $abc$24881$new_n4417 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[2] regset[28][2] regset[24][2] $abc$24881$new_n4418 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4430 regset[4][2] regset[0][2] $abc$24881$new_n4429 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[5][2] regset[1][2] $abc$24881$new_n4430 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] regset[13][2] regset[9][2] $abc$24881$new_n4432 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] regset[12][2] regset[8][2] $abc$24881$new_n4433 +001 1 +011 1 +110 1 +111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4373 $abc$24881$new_n4435 $abc$24881$new_n4438 $abc$24881$new_n4434 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n4405 $abc$24881$new_n4436 iflags[2] $abc$24881$new_n4435 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4437 wr_index[1] wr_index[0] DIVIDE.thedivide.w_n $abc$24881$new_n4436 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names wr_index[1] doalu.keep_sgn_on_ovfl wr_index[0] doalu.pre_sign doalu.n $abc$24881$new_n4437 +10001 1 +10011 1 +11010 1 +11011 1 +.names $abc$24881$new_n4400 $abc$24881$new_n4436 flags[2] $abc$24881$new_n4438 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4467 $abc$24881$new_n9455 $abc$24881$new_n4368 $abc$24881$new_n3859 $abc$24881$new_n4439 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][1] regset[3][1] $abc$24881$new_n4465 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][1] regset[2][1] $abc$24881$new_n4466 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4468 $abc$24881$new_n4470 $abc$24881$new_n4467 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$24881$new_n4405 $abc$24881$new_n4469 iflags[1] $abc$24881$new_n4468 +000 1 +010 1 +110 1 +111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.r_c doalu.c $abc$24881$new_n4469 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n4400 $abc$24881$new_n4469 flags[1] $abc$24881$new_n4470 +000 1 +010 1 +110 1 +111 1 +.names dcd_I[0] $abc$24881$new_n4500 $abc$24881$new_n4473 $abc$24881$new_n4472 $abc$24881$new_n4474 $abc$24881$new_n4471 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4373 $abc$24881$new_n4472 +11 1 +.names $abc$24881$new_n4368 $abc$24881$new_n3863 $abc$24881$new_n4473 +10 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9868 $abc$24881$new_n4475 $abc$24881$new_n4476 dcd_Bcc $abc$24881$new_n4474 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names iflags[0] $abc$24881$new_n4405 $abc$24881$new_n4475 +10 1 +.names $abc$24881$new_n4405 $abc$24881$new_n4486 $abc$24881$new_n4480 $abc$24881$new_n4477 $abc$24881$new_n4482 $abc$24881$new_n4476 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4478 $abc$24881$new_n4479 alu_result[22] alu_result[21] alu_result[20] $abc$24881$new_n4477 +11000 1 +.names alu_result[27] alu_result[26] alu_result[25] alu_result[24] $abc$24881$new_n4478 +0000 1 +.names doalu.n alu_result[30] alu_result[29] alu_result[28] alu_result[23] $abc$24881$new_n4479 +00000 1 +.names $abc$24881$new_n4481 alu_result[7] alu_result[6] alu_result[5] alu_result[4] $abc$24881$new_n4480 +10000 1 +.names alu_result[11] alu_result[10] alu_result[9] alu_result[8] $abc$24881$new_n4481 +0000 1 +.names wr_index[1] $abc$24881$new_n4483 $abc$24881$new_n4485 $abc$24881$new_n4484 wr_index[0] $abc$24881$new_n4482 +11110 1 +.names alu_result[3] alu_result[2] alu_result[1] alu_result[0] $abc$24881$new_n4483 +0000 1 +.names alu_result[19] alu_result[18] alu_result[17] alu_result[16] $abc$24881$new_n4484 +0000 1 +.names alu_result[15] alu_result[14] alu_result[13] alu_result[12] $abc$24881$new_n4485 +0000 1 +.names wr_index[1] DIVIDE.thedivide.r_z wr_index[0] $abc$24881$new_n4486 +111 1 +.names instruction_decoder.o_dcdB[2] regset[5][0] regset[1][0] $abc$24881$new_n4495 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[2] regset[4][0] regset[0][0] $abc$24881$new_n4496 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9871 $abc$24881$new_n4400 $abc$24881$new_n4516 $abc$24881$new_n4501 flags[0] $abc$24881$new_n4500 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n4486 $abc$24881$new_n4482 $abc$24881$new_n4480 $abc$24881$new_n4477 $abc$24881$new_n4501 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4504 +10 1 +.names instruction_decoder.o_dcdB[2] regset[31][0] regset[27][0] $abc$24881$new_n4508 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] regset[30][0] regset[26][0] $abc$24881$new_n4509 +001 1 +011 1 +110 1 +111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4516 +11 1 +.names $abc$24881$new_n4373 dcd_Bcc $abc$24881$new_n4519 +10 1 +.names user_step SET_GIE.r_gie $abc$24881$new_n4520 +10 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4525 regset[13][6] regset[9][6] $abc$24881$new_n4524 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][6] regset[8][6] $abc$24881$new_n4525 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4530 regset[15][6] regset[11][6] $abc$24881$new_n4529 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][6] regset[10][6] $abc$24881$new_n4530 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4534 regset[31][6] regset[27][6] $abc$24881$new_n4533 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][6] regset[26][6] $abc$24881$new_n4534 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4537 regset[21][6] regset[17][6] $abc$24881$new_n4536 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][6] regset[16][6] $abc$24881$new_n4537 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4539 regset[29][6] regset[25][6] $abc$24881$new_n4538 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][6] regset[24][6] $abc$24881$new_n4539 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4541 regset[23][6] regset[19][6] $abc$24881$new_n4540 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][6] regset[18][6] $abc$24881$new_n4541 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4543 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][6] regset[2][6] $abc$24881$new_n4542 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][6] regset[3][6] $abc$24881$new_n4543 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4548 regset[13][5] regset[9][5] $abc$24881$new_n4547 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][5] regset[8][5] $abc$24881$new_n4548 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][5] regset[0][5] $abc$24881$new_n4549 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][5] regset[1][5] $abc$24881$new_n4550 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4553 regset[15][5] regset[11][5] $abc$24881$new_n4552 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][5] regset[10][5] $abc$24881$new_n4553 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4555 regset[7][5] regset[3][5] $abc$24881$new_n4554 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][5] regset[2][5] $abc$24881$new_n4555 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4504 $abc$24881$new_n4557 $abc$24881$new_n4069 $abc$24881$new_n4564 $abc$24881$new_n4556 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$24881$new_n4558 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4560 $abc$24881$new_n4562 $abc$24881$new_n4557 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4559 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][5] regset[18][5] $abc$24881$new_n4558 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][5] regset[19][5] $abc$24881$new_n4559 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4561 regset[21][5] regset[20][5] $abc$24881$new_n4560 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][5] regset[16][5] $abc$24881$new_n4561 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4563 regset[29][5] regset[25][5] $abc$24881$new_n4562 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][5] regset[24][5] $abc$24881$new_n4563 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4565 regset[31][5] regset[27][5] $abc$24881$new_n4564 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][5] regset[26][5] $abc$24881$new_n4565 +001 1 +011 1 +110 1 +111 1 +.names dcd_I[7] $abc$24881$new_n9493 $abc$24881$new_n4566 +10 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4571 $abc$24881$new_n4573 $abc$24881$new_n4575 $abc$24881$new_n4570 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4572 regset[21][7] regset[17][7] $abc$24881$new_n4571 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][7] regset[16][7] $abc$24881$new_n4572 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4574 regset[29][7] regset[28][7] $abc$24881$new_n4573 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][7] regset[24][7] $abc$24881$new_n4574 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4576 regset[23][7] regset[19][7] $abc$24881$new_n4575 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][7] regset[18][7] $abc$24881$new_n4576 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4578 regset[31][7] regset[30][7] $abc$24881$new_n4577 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][7] regset[26][7] $abc$24881$new_n4578 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4581 $abc$24881$new_n4583 $abc$24881$new_n4585 $abc$24881$new_n4580 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4582 regset[5][7] regset[1][7] $abc$24881$new_n4581 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][7] regset[0][7] $abc$24881$new_n4582 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4584 regset[13][7] regset[9][7] $abc$24881$new_n4583 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][7] regset[8][7] $abc$24881$new_n4584 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4586 regset[7][7] regset[3][7] $abc$24881$new_n4585 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][7] regset[2][7] $abc$24881$new_n4586 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4588 regset[15][7] regset[11][7] $abc$24881$new_n4587 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][7] regset[10][7] $abc$24881$new_n4588 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9493 dcd_I[7] $abc$24881$new_n4590 +10 1 +.names $abc$24881$new_n4612 $abc$24881$new_n4592 $abc$24881$new_n4368 $abc$24881$new_n3820 $abc$24881$new_n4591 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4593 $abc$24881$new_n4603 $abc$24881$new_n4605 $abc$24881$new_n4592 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names $abc$24881$new_n4594 $abc$24881$new_n4601 $abc$24881$new_n4069 $abc$24881$new_n4593 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4595 $abc$24881$new_n4597 $abc$24881$new_n4599 $abc$24881$new_n4594 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4596 regset[5][8] regset[1][8] $abc$24881$new_n4595 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][8] regset[0][8] $abc$24881$new_n4596 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4598 regset[13][8] regset[9][8] $abc$24881$new_n4597 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][8] regset[8][8] $abc$24881$new_n4598 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4600 regset[7][8] regset[3][8] $abc$24881$new_n4599 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][8] regset[2][8] $abc$24881$new_n4600 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4602 regset[15][8] regset[11][8] $abc$24881$new_n4601 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][8] regset[10][8] $abc$24881$new_n4602 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4604 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][8] regset[26][8] $abc$24881$new_n4603 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][8] regset[27][8] $abc$24881$new_n4604 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4606 $abc$24881$new_n4608 $abc$24881$new_n4610 $abc$24881$new_n4605 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4607 regset[21][8] regset[17][8] $abc$24881$new_n4606 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][8] regset[16][8] $abc$24881$new_n4607 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4609 regset[29][8] regset[28][8] $abc$24881$new_n4608 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][8] regset[24][8] $abc$24881$new_n4609 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4611 regset[23][8] regset[19][8] $abc$24881$new_n4610 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][8] regset[18][8] $abc$24881$new_n4611 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc SET_USER_ILLEGAL_INSN.r_ill_err_u ill_err_i $abc$24881$new_n4612 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4617 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4619 $abc$24881$new_n4621 $abc$24881$new_n4616 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4618 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][10] regset[3][10] $abc$24881$new_n4617 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][10] regset[2][10] $abc$24881$new_n4618 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4620 regset[5][10] regset[1][10] $abc$24881$new_n4619 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][10] regset[0][10] $abc$24881$new_n4620 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4622 regset[13][10] regset[9][10] $abc$24881$new_n4621 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][10] regset[8][10] $abc$24881$new_n4622 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4624 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][10] regset[26][10] $abc$24881$new_n4623 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][10] regset[27][10] $abc$24881$new_n4624 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4626 $abc$24881$new_n4628 $abc$24881$new_n4630 $abc$24881$new_n4625 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4627 regset[21][10] regset[17][10] $abc$24881$new_n4626 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][10] regset[16][10] $abc$24881$new_n4627 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4629 regset[29][10] regset[28][10] $abc$24881$new_n4628 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][10] regset[24][10] $abc$24881$new_n4629 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4631 regset[23][10] regset[19][10] $abc$24881$new_n4630 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][10] regset[18][10] $abc$24881$new_n4631 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4633 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][10] regset[10][10] $abc$24881$new_n4632 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][10] regset[11][10] $abc$24881$new_n4633 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names dcd_I[9] $abc$24881$new_n4636 $abc$24881$new_n4635 +10 1 +.names $abc$24881$new_n4657 dcd_Bcc $abc$24881$new_n4373 $abc$24881$new_n4637 SET_TRAP_N_UBREAK.r_trap $abc$24881$new_n4636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names $abc$24881$new_n4638 $abc$24881$new_n4648 instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4655 $abc$24881$new_n4637 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4639 $abc$24881$new_n4642 $abc$24881$new_n4644 $abc$24881$new_n4646 $abc$24881$new_n4069 $abc$24881$new_n4638 +10000 1 +10010 1 +10011 1 +.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4640 $abc$24881$new_n4639 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4641 regset[29][9] regset[25][9] $abc$24881$new_n4640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][9] regset[24][9] $abc$24881$new_n4641 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4643 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][9] regset[16][9] $abc$24881$new_n4642 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][9] regset[17][9] $abc$24881$new_n4643 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4645 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][9] regset[18][9] $abc$24881$new_n4644 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][9] regset[19][9] $abc$24881$new_n4645 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4647 regset[31][9] regset[27][9] $abc$24881$new_n4646 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][9] regset[26][9] $abc$24881$new_n4647 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4649 $abc$24881$new_n4651 $abc$24881$new_n4653 $abc$24881$new_n4648 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4650 regset[13][9] regset[9][9] $abc$24881$new_n4649 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][9] regset[8][9] $abc$24881$new_n4650 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4652 regset[15][9] regset[11][9] $abc$24881$new_n4651 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][9] regset[10][9] $abc$24881$new_n4652 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4654 regset[5][9] regset[1][9] $abc$24881$new_n4653 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][9] regset[0][9] $abc$24881$new_n4654 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4656 regset[7][9] regset[3][9] $abc$24881$new_n4655 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][9] regset[2][9] $abc$24881$new_n4656 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4368 $abc$24881$new_n3815 $abc$24881$new_n4657 +10 1 +.names $abc$24881$new_n4636 dcd_I[9] $abc$24881$new_n4658 +10 1 +.names $abc$24881$new_n4681 $abc$24881$new_n4661 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3805 $abc$24881$new_n4660 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4662 $abc$24881$new_n4669 $abc$24881$new_n4679 $abc$24881$new_n4069 $abc$24881$new_n4661 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4663 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4665 $abc$24881$new_n4667 $abc$24881$new_n4662 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4664 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][11] regset[3][11] $abc$24881$new_n4663 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][11] regset[2][11] $abc$24881$new_n4664 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4666 regset[5][11] regset[1][11] $abc$24881$new_n4665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][11] regset[0][11] $abc$24881$new_n4666 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4668 regset[13][11] regset[9][11] $abc$24881$new_n4667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][11] regset[8][11] $abc$24881$new_n4668 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4672 $abc$24881$new_n4670 $abc$24881$new_n4675 $abc$24881$new_n4677 $abc$24881$new_n4069 $abc$24881$new_n4669 +00000 1 +00010 1 +00011 1 +.names $abc$24881$new_n4671 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][11] regset[18][11] $abc$24881$new_n4670 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][11] regset[19][11] $abc$24881$new_n4671 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4673 $abc$24881$new_n4672 +100 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4674 regset[29][11] regset[25][11] $abc$24881$new_n4673 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][11] regset[24][11] $abc$24881$new_n4674 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4676 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][11] regset[17][11] $abc$24881$new_n4675 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][11] regset[16][11] $abc$24881$new_n4676 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4678 regset[31][11] regset[27][11] $abc$24881$new_n4677 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][11] regset[26][11] $abc$24881$new_n4678 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4680 regset[15][11] regset[11][11] $abc$24881$new_n4679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][11] regset[10][11] $abc$24881$new_n4680 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc DIVERR.USER_DIVERR.r_udiv_err_flag DIVERR.r_idiv_err_flag $abc$24881$new_n4681 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4687 $abc$24881$new_n4689 $abc$24881$new_n4686 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4688 regset[15][12] regset[11][12] $abc$24881$new_n4687 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][12] regset[10][12] $abc$24881$new_n4688 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4690 regset[13][12] regset[9][12] $abc$24881$new_n4689 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][12] regset[8][12] $abc$24881$new_n4690 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4692 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][12] regset[2][12] $abc$24881$new_n4691 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][12] regset[3][12] $abc$24881$new_n4692 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4695 $abc$24881$new_n4697 $abc$24881$new_n4699 $abc$24881$new_n4694 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4696 regset[21][12] regset[17][12] $abc$24881$new_n4695 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][12] regset[16][12] $abc$24881$new_n4696 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4698 regset[29][12] regset[25][12] $abc$24881$new_n4697 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][12] regset[24][12] $abc$24881$new_n4698 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4700 regset[31][12] regset[27][12] $abc$24881$new_n4699 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][12] regset[26][12] $abc$24881$new_n4700 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4702 regset[23][12] regset[19][12] $abc$24881$new_n4701 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][12] regset[18][12] $abc$24881$new_n4702 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4704 regset[5][12] regset[1][12] $abc$24881$new_n4703 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][12] regset[0][12] $abc$24881$new_n4704 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4709 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4711 $abc$24881$new_n4713 $abc$24881$new_n4708 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4710 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][13] regset[3][13] $abc$24881$new_n4709 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][13] regset[2][13] $abc$24881$new_n4710 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4712 regset[5][13] regset[1][13] $abc$24881$new_n4711 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][13] regset[0][13] $abc$24881$new_n4712 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4714 regset[13][13] regset[9][13] $abc$24881$new_n4713 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][13] regset[8][13] $abc$24881$new_n4714 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4716 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][13] regset[26][13] $abc$24881$new_n4715 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][13] regset[27][13] $abc$24881$new_n4716 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4718 $abc$24881$new_n4720 $abc$24881$new_n4722 $abc$24881$new_n4717 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4719 regset[21][13] regset[17][13] $abc$24881$new_n4718 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][13] regset[16][13] $abc$24881$new_n4719 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4721 regset[29][13] regset[28][13] $abc$24881$new_n4720 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][13] regset[24][13] $abc$24881$new_n4721 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4723 regset[23][13] regset[19][13] $abc$24881$new_n4722 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][13] regset[18][13] $abc$24881$new_n4723 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4725 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][13] regset[10][13] $abc$24881$new_n4724 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][13] regset[11][13] $abc$24881$new_n4725 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4731 $abc$24881$new_n4733 $abc$24881$new_n4730 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4732 regset[15][14] regset[11][14] $abc$24881$new_n4731 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][14] regset[10][14] $abc$24881$new_n4732 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4734 regset[13][14] regset[9][14] $abc$24881$new_n4733 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][14] regset[8][14] $abc$24881$new_n4734 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4736 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][14] regset[2][14] $abc$24881$new_n4735 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][14] regset[3][14] $abc$24881$new_n4736 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4739 $abc$24881$new_n4741 $abc$24881$new_n4743 $abc$24881$new_n4738 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4740 regset[21][14] regset[17][14] $abc$24881$new_n4739 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][14] regset[16][14] $abc$24881$new_n4740 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4742 regset[29][14] regset[25][14] $abc$24881$new_n4741 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][14] regset[24][14] $abc$24881$new_n4742 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4744 regset[31][14] regset[27][14] $abc$24881$new_n4743 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][14] regset[26][14] $abc$24881$new_n4744 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4746 regset[23][14] regset[19][14] $abc$24881$new_n4745 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][14] regset[18][14] $abc$24881$new_n4746 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4748 regset[5][14] regset[1][14] $abc$24881$new_n4747 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][14] regset[0][14] $abc$24881$new_n4748 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4754 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][16] regset[18][16] $abc$24881$new_n4753 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][16] regset[19][16] $abc$24881$new_n4754 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4756 regset[21][16] regset[20][16] $abc$24881$new_n4755 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][16] regset[16][16] $abc$24881$new_n4756 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4758 regset[29][16] regset[25][16] $abc$24881$new_n4757 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][16] regset[24][16] $abc$24881$new_n4758 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4760 regset[31][16] regset[27][16] $abc$24881$new_n4759 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][16] regset[26][16] $abc$24881$new_n4760 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4762 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4764 $abc$24881$new_n4766 $abc$24881$new_n4761 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4763 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][16] regset[11][16] $abc$24881$new_n4762 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][16] regset[10][16] $abc$24881$new_n4763 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4765 regset[13][16] regset[12][16] $abc$24881$new_n4764 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[9][16] regset[8][16] $abc$24881$new_n4765 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4767 regset[5][16] regset[1][16] $abc$24881$new_n4766 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][16] regset[0][16] $abc$24881$new_n4767 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4769 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][16] regset[2][16] $abc$24881$new_n4768 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][16] regset[3][16] $abc$24881$new_n4769 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4775 $abc$24881$new_n4777 $abc$24881$new_n4779 $abc$24881$new_n4774 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4776 regset[13][15] regset[9][15] $abc$24881$new_n4775 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][15] regset[8][15] $abc$24881$new_n4776 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4778 regset[7][15] regset[3][15] $abc$24881$new_n4777 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][15] regset[2][15] $abc$24881$new_n4778 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4780 regset[5][15] regset[1][15] $abc$24881$new_n4779 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][15] regset[0][15] $abc$24881$new_n4780 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4782 regset[15][15] regset[11][15] $abc$24881$new_n4781 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][15] regset[10][15] $abc$24881$new_n4782 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4785 $abc$24881$new_n4787 $abc$24881$new_n4784 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4786 regset[31][15] regset[27][15] $abc$24881$new_n4785 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][15] regset[26][15] $abc$24881$new_n4786 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4788 regset[29][15] regset[25][15] $abc$24881$new_n4787 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][15] regset[24][15] $abc$24881$new_n4788 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4790 regset[23][15] regset[19][15] $abc$24881$new_n4789 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][15] regset[18][15] $abc$24881$new_n4790 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4792 regset[21][15] regset[17][15] $abc$24881$new_n4791 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][15] regset[16][15] $abc$24881$new_n4792 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4800 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][17] regset[18][17] $abc$24881$new_n4799 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][17] regset[19][17] $abc$24881$new_n4800 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4802 regset[21][17] regset[20][17] $abc$24881$new_n4801 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][17] regset[16][17] $abc$24881$new_n4802 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4804 regset[29][17] regset[25][17] $abc$24881$new_n4803 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][17] regset[24][17] $abc$24881$new_n4804 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4806 regset[31][17] regset[27][17] $abc$24881$new_n4805 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][17] regset[26][17] $abc$24881$new_n4806 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4808 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4810 $abc$24881$new_n4812 $abc$24881$new_n4807 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4809 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][17] regset[11][17] $abc$24881$new_n4808 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][17] regset[10][17] $abc$24881$new_n4809 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4811 regset[13][17] regset[12][17] $abc$24881$new_n4810 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[9][17] regset[8][17] $abc$24881$new_n4811 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4813 regset[5][17] regset[1][17] $abc$24881$new_n4812 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][17] regset[0][17] $abc$24881$new_n4813 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4815 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][17] regset[2][17] $abc$24881$new_n4814 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][17] regset[3][17] $abc$24881$new_n4815 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4373 $abc$24881$new_n4818 $abc$24881$new_n4368 $abc$24881$new_n3769 $abc$24881$new_n4817 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4819 $abc$24881$new_n4826 $abc$24881$new_n4349 $abc$24881$new_n4836 $abc$24881$new_n4818 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4820 $abc$24881$new_n4822 $abc$24881$new_n4824 $abc$24881$new_n4819 +00000 1 +00001 1 +00010 1 +00011 1 +01010 1 +01011 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4821 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][18] regset[10][18] $abc$24881$new_n4820 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][18] regset[11][18] $abc$24881$new_n4821 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4823 regset[13][18] regset[9][18] $abc$24881$new_n4822 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][18] regset[8][18] $abc$24881$new_n4823 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4825 regset[7][18] regset[3][18] $abc$24881$new_n4824 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][18] regset[2][18] $abc$24881$new_n4825 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4827 $abc$24881$new_n4834 $abc$24881$new_n4356 $abc$24881$new_n4826 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4828 $abc$24881$new_n4830 $abc$24881$new_n4832 $abc$24881$new_n4827 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4829 regset[21][18] regset[17][18] $abc$24881$new_n4828 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][18] regset[16][18] $abc$24881$new_n4829 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4831 regset[29][18] regset[25][18] $abc$24881$new_n4830 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][18] regset[24][18] $abc$24881$new_n4831 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4833 regset[31][18] regset[27][18] $abc$24881$new_n4832 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][18] regset[26][18] $abc$24881$new_n4833 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4835 regset[23][18] regset[19][18] $abc$24881$new_n4834 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][18] regset[18][18] $abc$24881$new_n4835 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4837 regset[5][18] regset[1][18] $abc$24881$new_n4836 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][18] regset[0][18] $abc$24881$new_n4837 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n4840 $abc$24881$new_n4368 $abc$24881$new_n3763 $abc$24881$new_n4839 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4843 $abc$24881$new_n4841 $abc$24881$new_n4852 $abc$24881$new_n4850 $abc$24881$new_n4840 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n4842 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][19] regset[2][19] $abc$24881$new_n4841 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][19] regset[3][19] $abc$24881$new_n4842 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4844 $abc$24881$new_n4846 $abc$24881$new_n4848 $abc$24881$new_n4843 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4845 regset[5][19] regset[4][19] $abc$24881$new_n4844 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[1][19] regset[0][19] $abc$24881$new_n4845 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4847 regset[15][19] regset[11][19] $abc$24881$new_n4846 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][19] regset[10][19] $abc$24881$new_n4847 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4849 regset[13][19] regset[9][19] $abc$24881$new_n4848 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][19] regset[8][19] $abc$24881$new_n4849 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4851 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][19] regset[27][19] $abc$24881$new_n4850 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][19] regset[26][19] $abc$24881$new_n4851 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4853 $abc$24881$new_n4855 $abc$24881$new_n4857 $abc$24881$new_n4852 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4854 regset[29][19] regset[25][19] $abc$24881$new_n4853 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][19] regset[24][19] $abc$24881$new_n4854 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4856 regset[23][19] regset[19][19] $abc$24881$new_n4855 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][19] regset[18][19] $abc$24881$new_n4856 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4858 regset[21][19] regset[17][19] $abc$24881$new_n4857 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][19] regset[16][19] $abc$24881$new_n4858 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n4861 $abc$24881$new_n4368 $abc$24881$new_n3757 $abc$24881$new_n4860 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4864 $abc$24881$new_n4862 $abc$24881$new_n4873 $abc$24881$new_n4871 $abc$24881$new_n4861 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n4863 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][20] regset[11][20] $abc$24881$new_n4862 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][20] regset[10][20] $abc$24881$new_n4863 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4865 $abc$24881$new_n4867 $abc$24881$new_n4869 $abc$24881$new_n4864 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4866 regset[13][20] regset[9][20] $abc$24881$new_n4865 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][20] regset[8][20] $abc$24881$new_n4866 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4868 regset[7][20] regset[3][20] $abc$24881$new_n4867 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][20] regset[2][20] $abc$24881$new_n4868 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4870 regset[5][20] regset[1][20] $abc$24881$new_n4869 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][20] regset[0][20] $abc$24881$new_n4870 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4872 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][20] regset[18][20] $abc$24881$new_n4871 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][20] regset[19][20] $abc$24881$new_n4872 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4874 $abc$24881$new_n4876 $abc$24881$new_n4878 $abc$24881$new_n4873 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4875 regset[21][20] regset[20][20] $abc$24881$new_n4874 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][20] regset[16][20] $abc$24881$new_n4875 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4877 regset[31][20] regset[27][20] $abc$24881$new_n4876 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][20] regset[26][20] $abc$24881$new_n4877 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4879 regset[29][20] regset[25][20] $abc$24881$new_n4878 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][20] regset[24][20] $abc$24881$new_n4879 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4885 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4887 $abc$24881$new_n4889 $abc$24881$new_n4884 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +.names $abc$24881$new_n4886 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][21] regset[16][21] $abc$24881$new_n4885 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][21] regset[17][21] $abc$24881$new_n4886 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4888 regset[29][21] regset[25][21] $abc$24881$new_n4887 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][21] regset[24][21] $abc$24881$new_n4888 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4890 regset[31][21] regset[27][21] $abc$24881$new_n4889 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][21] regset[26][21] $abc$24881$new_n4890 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] $abc$24881$new_n4894 $abc$24881$new_n4901 instruction_decoder.o_dcdB[3] $abc$24881$new_n4899 $abc$24881$new_n4893 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] $abc$24881$new_n4895 $abc$24881$new_n4897 $abc$24881$new_n4898 $abc$24881$new_n4894 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4896 regset[13][21] regset[9][21] $abc$24881$new_n4895 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][21] regset[8][21] $abc$24881$new_n4896 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[2] regset[4][21] regset[0][21] $abc$24881$new_n4897 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] regset[5][21] regset[1][21] $abc$24881$new_n4898 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4900 regset[15][21] regset[11][21] $abc$24881$new_n4899 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][21] regset[10][21] $abc$24881$new_n4900 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4902 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][21] regset[2][21] $abc$24881$new_n4901 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][21] regset[3][21] $abc$24881$new_n4902 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n4905 $abc$24881$new_n4368 $abc$24881$new_n3747 $abc$24881$new_n4904 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4906 $abc$24881$new_n4913 $abc$24881$new_n4356 $abc$24881$new_n4923 $abc$24881$new_n4905 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4907 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4909 $abc$24881$new_n4911 $abc$24881$new_n4906 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n4908 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][22] regset[0][22] $abc$24881$new_n4907 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][22] regset[1][22] $abc$24881$new_n4908 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4910 regset[15][22] regset[11][22] $abc$24881$new_n4909 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][22] regset[10][22] $abc$24881$new_n4910 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4912 regset[13][22] regset[9][22] $abc$24881$new_n4911 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][22] regset[8][22] $abc$24881$new_n4912 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4914 $abc$24881$new_n4921 $abc$24881$new_n4069 $abc$24881$new_n4913 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4915 $abc$24881$new_n4917 $abc$24881$new_n4919 $abc$24881$new_n4914 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4916 regset[21][22] regset[17][22] $abc$24881$new_n4915 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][22] regset[16][22] $abc$24881$new_n4916 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4918 regset[22][22] regset[18][22] $abc$24881$new_n4917 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[23][22] regset[19][22] $abc$24881$new_n4918 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4920 regset[29][22] regset[25][22] $abc$24881$new_n4919 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][22] regset[24][22] $abc$24881$new_n4920 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4922 regset[31][22] regset[27][22] $abc$24881$new_n4921 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][22] regset[26][22] $abc$24881$new_n4922 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4924 regset[7][22] regset[3][22] $abc$24881$new_n4923 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][22] regset[2][22] $abc$24881$new_n4924 +001 1 +011 1 +110 1 +111 1 +.names dcd_I[31] $abc$24881$new_n9521 $abc$24881$new_n4925 +00 1 +11 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4930 $abc$24881$new_n4932 $abc$24881$new_n4934 $abc$24881$new_n4929 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4931 regset[23][24] regset[19][24] $abc$24881$new_n4930 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][24] regset[18][24] $abc$24881$new_n4931 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4933 regset[21][24] regset[17][24] $abc$24881$new_n4932 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][24] regset[16][24] $abc$24881$new_n4933 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4935 regset[29][24] regset[28][24] $abc$24881$new_n4934 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][24] regset[24][24] $abc$24881$new_n4935 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4937 regset[31][24] regset[30][24] $abc$24881$new_n4936 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][24] regset[26][24] $abc$24881$new_n4937 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4940 $abc$24881$new_n4942 $abc$24881$new_n4944 $abc$24881$new_n4939 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4941 regset[7][24] regset[3][24] $abc$24881$new_n4940 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][24] regset[2][24] $abc$24881$new_n4941 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4943 regset[5][24] regset[1][24] $abc$24881$new_n4942 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][24] regset[0][24] $abc$24881$new_n4943 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4945 regset[13][24] regset[9][24] $abc$24881$new_n4944 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][24] regset[8][24] $abc$24881$new_n4945 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4947 regset[15][24] regset[11][24] $abc$24881$new_n4946 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][24] regset[10][24] $abc$24881$new_n4947 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9524 dcd_I[31] $abc$24881$new_n4948 +10 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4953 $abc$24881$new_n4955 $abc$24881$new_n4957 $abc$24881$new_n4952 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4954 regset[23][23] regset[19][23] $abc$24881$new_n4953 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][23] regset[18][23] $abc$24881$new_n4954 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4956 regset[21][23] regset[17][23] $abc$24881$new_n4955 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][23] regset[16][23] $abc$24881$new_n4956 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4958 regset[29][23] regset[28][23] $abc$24881$new_n4957 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][23] regset[24][23] $abc$24881$new_n4958 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4960 regset[31][23] regset[30][23] $abc$24881$new_n4959 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][23] regset[26][23] $abc$24881$new_n4960 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4963 $abc$24881$new_n4965 $abc$24881$new_n4967 $abc$24881$new_n4962 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4964 regset[7][23] regset[3][23] $abc$24881$new_n4963 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][23] regset[2][23] $abc$24881$new_n4964 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4966 regset[5][23] regset[1][23] $abc$24881$new_n4965 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][23] regset[0][23] $abc$24881$new_n4966 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4968 regset[13][23] regset[9][23] $abc$24881$new_n4967 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][23] regset[8][23] $abc$24881$new_n4968 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4970 regset[15][23] regset[11][23] $abc$24881$new_n4969 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][23] regset[10][23] $abc$24881$new_n4970 +001 1 +011 1 +110 1 +111 1 +.names dcd_I[31] $abc$24881$new_n9524 $abc$24881$new_n4971 +10 1 +.names dcd_I[31] $abc$24881$new_n9527 $abc$24881$new_n4972 +00 1 +11 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4977 $abc$24881$new_n4979 $abc$24881$new_n4981 $abc$24881$new_n4976 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4978 regset[23][25] regset[19][25] $abc$24881$new_n4977 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][25] regset[18][25] $abc$24881$new_n4978 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4980 regset[21][25] regset[17][25] $abc$24881$new_n4979 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][25] regset[16][25] $abc$24881$new_n4980 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4982 regset[29][25] regset[28][25] $abc$24881$new_n4981 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][25] regset[24][25] $abc$24881$new_n4982 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4984 regset[31][25] regset[30][25] $abc$24881$new_n4983 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][25] regset[26][25] $abc$24881$new_n4984 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4987 $abc$24881$new_n4989 $abc$24881$new_n4991 $abc$24881$new_n4986 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4988 regset[7][25] regset[3][25] $abc$24881$new_n4987 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][25] regset[2][25] $abc$24881$new_n4988 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4990 regset[5][25] regset[1][25] $abc$24881$new_n4989 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][25] regset[0][25] $abc$24881$new_n4990 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4992 regset[13][25] regset[9][25] $abc$24881$new_n4991 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][25] regset[8][25] $abc$24881$new_n4992 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4994 regset[15][25] regset[11][25] $abc$24881$new_n4993 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][25] regset[10][25] $abc$24881$new_n4994 +001 1 +011 1 +110 1 +111 1 +.names dcd_I[31] $abc$24881$new_n9533 $abc$24881$new_n9530 $abc$24881$new_n4996 $abc$24881$new_n4995 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names dcd_I[31] $abc$24881$new_n9521 $abc$24881$new_n9527 $abc$24881$new_n4996 +000 1 +001 1 +010 1 +011 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5001 $abc$24881$new_n5003 $abc$24881$new_n5005 $abc$24881$new_n5000 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5002 regset[23][27] regset[19][27] $abc$24881$new_n5001 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][27] regset[18][27] $abc$24881$new_n5002 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5004 regset[21][27] regset[17][27] $abc$24881$new_n5003 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][27] regset[16][27] $abc$24881$new_n5004 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5006 regset[29][27] regset[28][27] $abc$24881$new_n5005 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][27] regset[24][27] $abc$24881$new_n5006 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5008 regset[31][27] regset[30][27] $abc$24881$new_n5007 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][27] regset[26][27] $abc$24881$new_n5008 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5011 $abc$24881$new_n5013 $abc$24881$new_n5015 $abc$24881$new_n5010 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5012 regset[15][27] regset[11][27] $abc$24881$new_n5011 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][27] regset[10][27] $abc$24881$new_n5012 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5014 regset[13][27] regset[9][27] $abc$24881$new_n5013 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][27] regset[8][27] $abc$24881$new_n5014 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5016 regset[5][27] regset[1][27] $abc$24881$new_n5015 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][27] regset[0][27] $abc$24881$new_n5016 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5018 regset[7][27] regset[3][27] $abc$24881$new_n5017 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][27] regset[2][27] $abc$24881$new_n5018 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5023 $abc$24881$new_n5025 $abc$24881$new_n5027 $abc$24881$new_n5022 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5024 regset[13][26] regset[9][26] $abc$24881$new_n5023 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][26] regset[8][26] $abc$24881$new_n5024 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5026 regset[7][26] regset[3][26] $abc$24881$new_n5025 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][26] regset[2][26] $abc$24881$new_n5026 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5028 regset[5][26] regset[1][26] $abc$24881$new_n5027 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][26] regset[0][26] $abc$24881$new_n5028 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5030 regset[15][26] regset[11][26] $abc$24881$new_n5029 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][26] regset[10][26] $abc$24881$new_n5030 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5033 $abc$24881$new_n5035 $abc$24881$new_n5032 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5034 regset[31][26] regset[27][26] $abc$24881$new_n5033 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][26] regset[26][26] $abc$24881$new_n5034 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5036 regset[29][26] regset[25][26] $abc$24881$new_n5035 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][26] regset[24][26] $abc$24881$new_n5036 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5038 regset[23][26] regset[19][26] $abc$24881$new_n5037 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][26] regset[18][26] $abc$24881$new_n5038 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5040 regset[21][26] regset[17][26] $abc$24881$new_n5039 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][26] regset[16][26] $abc$24881$new_n5040 +000 1 +010 1 +100 1 +101 1 +.names dcd_I[31] $abc$24881$new_n9533 $abc$24881$new_n9530 $abc$24881$new_n5041 +000 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5046 regset[31][28] regset[27][28] $abc$24881$new_n5045 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][28] regset[26][28] $abc$24881$new_n5046 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5049 regset[29][28] regset[25][28] $abc$24881$new_n5048 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][28] regset[24][28] $abc$24881$new_n5049 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5051 regset[21][28] regset[17][28] $abc$24881$new_n5050 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][28] regset[16][28] $abc$24881$new_n5051 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5053 regset[23][28] regset[19][28] $abc$24881$new_n5052 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][28] regset[18][28] $abc$24881$new_n5053 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5056 regset[7][28] regset[3][28] $abc$24881$new_n5055 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][28] regset[2][28] $abc$24881$new_n5056 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5059 regset[15][28] regset[11][28] $abc$24881$new_n5058 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][28] regset[10][28] $abc$24881$new_n5059 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5062 regset[13][28] regset[9][28] $abc$24881$new_n5061 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][28] regset[8][28] $abc$24881$new_n5062 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5064 regset[5][28] regset[1][28] $abc$24881$new_n5063 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][28] regset[0][28] $abc$24881$new_n5064 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5065 +10 1 +.names $abc$24881$new_n4029 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$new_n5066 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names dcd_rB dcd_Bpc $abc$24881$new_n5067 +11 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5073 regset[7][29] regset[3][29] $abc$24881$new_n5072 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][29] regset[2][29] $abc$24881$new_n5073 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5075 regset[13][29] regset[9][29] $abc$24881$new_n5074 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][29] regset[8][29] $abc$24881$new_n5075 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5077 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][29] regset[0][29] $abc$24881$new_n5076 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][29] regset[1][29] $abc$24881$new_n5077 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5079 regset[15][29] regset[11][29] $abc$24881$new_n5078 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][29] regset[10][29] $abc$24881$new_n5079 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5081 instruction_decoder.o_dcdB[3] $abc$24881$new_n5089 $abc$24881$new_n5088 instruction_decoder.o_dcdB[1] $abc$24881$new_n5080 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5082 $abc$24881$new_n5084 $abc$24881$new_n5086 $abc$24881$new_n5081 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5083 regset[23][29] regset[22][29] $abc$24881$new_n5082 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[19][29] regset[18][29] $abc$24881$new_n5083 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5085 regset[21][29] regset[17][29] $abc$24881$new_n5084 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][29] regset[16][29] $abc$24881$new_n5085 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5087 regset[31][29] regset[27][29] $abc$24881$new_n5086 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][29] regset[26][29] $abc$24881$new_n5087 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[28][29] regset[24][29] $abc$24881$new_n5088 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][29] regset[25][29] $abc$24881$new_n5089 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n3702 $abc$24881$new_n4368 $abc$24881$new_n4519 $abc$24881$new_n5091 $abc$24881$new_n5101 $abc$24881$new_n5090 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5092 instruction_decoder.o_dcdB[4] $abc$24881$new_n5099 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5091 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5093 $abc$24881$new_n5095 $abc$24881$new_n5097 $abc$24881$new_n5092 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5094 regset[5][30] regset[1][30] $abc$24881$new_n5093 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][30] regset[0][30] $abc$24881$new_n5094 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5096 regset[15][30] regset[11][30] $abc$24881$new_n5095 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][30] regset[10][30] $abc$24881$new_n5096 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5098 regset[7][30] regset[3][30] $abc$24881$new_n5097 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][30] regset[2][30] $abc$24881$new_n5098 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5100 regset[13][30] regset[9][30] $abc$24881$new_n5099 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][30] regset[8][30] $abc$24881$new_n5100 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n5102 $abc$24881$new_n5109 $abc$24881$new_n4349 $abc$24881$new_n5101 +1100 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5103 $abc$24881$new_n5105 $abc$24881$new_n5107 $abc$24881$new_n5102 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5104 regset[31][30] regset[27][30] $abc$24881$new_n5103 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][30] regset[26][30] $abc$24881$new_n5104 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5106 regset[29][30] regset[25][30] $abc$24881$new_n5105 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][30] regset[24][30] $abc$24881$new_n5106 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5108 regset[23][30] regset[19][30] $abc$24881$new_n5107 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][30] regset[18][30] $abc$24881$new_n5108 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5110 regset[21][30] regset[17][30] $abc$24881$new_n5109 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][30] regset[16][30] $abc$24881$new_n5110 +000 1 +010 1 +100 1 +101 1 +.names dcd_I[31] $abc$24881$new_n5146 $abc$24881$new_n5145 $abc$24881$new_n5144 $abc$24881$new_n5114 $abc$24881$new_n5113 +00000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[31] $abc$24881$new_n5115 SET_USER_PC.r_upc[24] instruction_decoder.o_pc[24] $abc$24881$new_n5114 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[21] $abc$24881$new_n5116 SET_USER_PC.r_upc[23] instruction_decoder.o_pc[23] $abc$24881$new_n5115 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n5143 dcd_I[19] dcd_I[20] $abc$24881$new_n5142 $abc$24881$new_n5117 $abc$24881$new_n5116 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5141 dcd_I[17] dcd_I[18] $abc$24881$new_n5140 $abc$24881$new_n5118 $abc$24881$new_n5117 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5139 dcd_I[15] dcd_I[16] $abc$24881$new_n5138 $abc$24881$new_n5119 $abc$24881$new_n5118 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5137 dcd_I[13] dcd_I[14] $abc$24881$new_n5136 $abc$24881$new_n5120 $abc$24881$new_n5119 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5135 dcd_I[11] dcd_I[12] $abc$24881$new_n5134 $abc$24881$new_n5121 $abc$24881$new_n5120 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5133 dcd_I[9] dcd_I[10] $abc$24881$new_n5132 $abc$24881$new_n5122 $abc$24881$new_n5121 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5131 dcd_I[7] dcd_I[8] $abc$24881$new_n5130 $abc$24881$new_n5123 $abc$24881$new_n5122 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n4068 dcd_I[6] $abc$24881$new_n5124 SET_USER_PC.r_upc[8] instruction_decoder.o_pc[8] $abc$24881$new_n5123 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[5] $abc$24881$new_n5125 SET_USER_PC.r_upc[7] instruction_decoder.o_pc[7] $abc$24881$new_n5124 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[4] $abc$24881$new_n5126 SET_USER_PC.r_upc[6] instruction_decoder.o_pc[6] $abc$24881$new_n5125 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[3] $abc$24881$new_n5127 SET_USER_PC.r_upc[5] instruction_decoder.o_pc[5] $abc$24881$new_n5126 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[2] $abc$24881$new_n5128 SET_USER_PC.r_upc[4] instruction_decoder.o_pc[4] $abc$24881$new_n5127 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[1] $abc$24881$new_n5129 SET_USER_PC.r_upc[3] instruction_decoder.o_pc[3] $abc$24881$new_n5128 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names dcd_I[0] SET_GIE.r_gie instruction_decoder.o_dcdB[4] instruction_decoder.o_pc[2] SET_USER_PC.r_upc[2] $abc$24881$new_n5129 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[10] SET_USER_PC.r_upc[10] $abc$24881$new_n5130 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[9] SET_USER_PC.r_upc[9] $abc$24881$new_n5131 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[12] SET_USER_PC.r_upc[12] $abc$24881$new_n5132 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[11] SET_USER_PC.r_upc[11] $abc$24881$new_n5133 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[14] SET_USER_PC.r_upc[14] $abc$24881$new_n5134 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[13] SET_USER_PC.r_upc[13] $abc$24881$new_n5135 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[16] SET_USER_PC.r_upc[16] $abc$24881$new_n5136 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[15] SET_USER_PC.r_upc[15] $abc$24881$new_n5137 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[18] SET_USER_PC.r_upc[18] $abc$24881$new_n5138 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[17] SET_USER_PC.r_upc[17] $abc$24881$new_n5139 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[20] SET_USER_PC.r_upc[20] $abc$24881$new_n5140 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[19] SET_USER_PC.r_upc[19] $abc$24881$new_n5141 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[22] SET_USER_PC.r_upc[22] $abc$24881$new_n5142 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[21] SET_USER_PC.r_upc[21] $abc$24881$new_n5143 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[27] SET_USER_PC.r_upc[27] $abc$24881$new_n5144 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[26] SET_USER_PC.r_upc[26] $abc$24881$new_n5145 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[25] SET_USER_PC.r_upc[25] $abc$24881$new_n5146 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[29] SET_USER_PC.r_upc[29] $abc$24881$new_n5147 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[28] SET_USER_PC.r_upc[28] $abc$24881$new_n5148 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[30] SET_USER_PC.r_upc[30] $abc$24881$new_n5149 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3702 r_op_Bv[30] o_mem_addr[30] +001 1 +011 1 +100 1 +101 1 +.names OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n5151 +111 1 +.names $abc$24881$new_n5153 $abc$24881$new_n5154 $abc$24881$new_n3700 dbgv i_mem_valid $abc$24881$new_n5152 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[2] i_mem_wreg[2] alu_reg[2] $abc$24881$new_n5153 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names OP_REG_ADVANEC.r_op_Bid[1] i_mem_valid alu_reg[1] i_mem_wreg[1] $abc$24881$new_n5154 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n5157 $abc$24881$new_n5156 OP_REG_ADVANEC.r_op_Bid[0] $abc$24881$new_n3697 $abc$24881$new_n5158 $abc$24881$new_n5155 +11010 1 +11100 1 +.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[3] i_mem_wreg[3] alu_reg[3] $abc$24881$new_n5156 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[4] i_mem_wreg[4] alu_reg[4] $abc$24881$new_n5157 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[1] alu_reg[1] i_mem_wreg[1] $abc$24881$new_n5158 +0010 1 +0011 1 +1001 1 +1011 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3708 r_op_Bv[29] o_mem_addr[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4995 $abc$24881$new_n4329 $abc$24881$new_n5041 $abc$24881$new_n5166 +100 1 +101 1 +110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3714 r_op_Bv[28] o_mem_addr[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5170 o_mem_addr[27] $abc$24881$new_n5067 $abc$24881$new_n5172 $abc$24881$auto$rtlil.cc:2693:MuxGate$22930 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9530 dcd_I[31] $abc$24881$new_n5067 $abc$24881$new_n9533 $abc$24881$new_n5171 $abc$24881$new_n5170 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +10000 1 +11011 1 +.names $abc$24881$new_n4996 $abc$24881$new_n4329 $abc$24881$new_n5171 +10 1 +.names dcd_I[31] $abc$24881$new_n5144 $abc$24881$new_n5146 $abc$24881$new_n5145 $abc$24881$new_n5114 $abc$24881$new_n5172 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3719 r_op_Bv[27] o_mem_addr[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n9548 $abc$24881$new_n3725 r_op_Bv[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$22932 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n5066 $abc$24881$new_n5177 +11 1 +.names $abc$24881$new_n5066 dcd_I[31] $abc$24881$new_n5146 $abc$24881$new_n5114 $abc$24881$new_n5067 $abc$24881$new_n5182 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 o_mem_addr[24] $abc$24881$new_n5185 $abc$24881$new_n5186 $abc$24881$auto$rtlil.cc:2693:MuxGate$22936 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5065 $abc$24881$new_n4925 $abc$24881$new_n4948 $abc$24881$new_n4971 $abc$24881$new_n9843 $abc$24881$new_n5185 +10000 1 +10010 1 +10011 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n5187 $abc$24881$new_n5115 $abc$24881$new_n5186 +100 1 +111 1 +.names dcd_I[31] $abc$24881$new_n4068 SET_USER_PC.r_upc[24] instruction_decoder.o_pc[24] $abc$24881$new_n5187 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3735 r_op_Bv[24] o_mem_addr[24] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[21] $abc$24881$new_n5116 $abc$24881$new_n4068 SET_USER_PC.r_upc[23] instruction_decoder.o_pc[23] $abc$24881$new_n5192 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names dcd_I[20] $abc$24881$new_n5142 dcd_I[19] $abc$24881$new_n5143 $abc$24881$new_n5117 $abc$24881$new_n5196 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3747 r_op_Bv[22] o_mem_addr[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5177 dcd_I[19] $abc$24881$new_n5143 $abc$24881$new_n5117 $abc$24881$new_n5201 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[18] $abc$24881$new_n5140 dcd_I[17] $abc$24881$new_n5141 $abc$24881$new_n5118 $abc$24881$new_n5205 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3757 r_op_Bv[20] o_mem_addr[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[19] $abc$24881$new_n5208 $abc$24881$new_n5209 $abc$24881$auto$rtlil.cc:2693:MuxGate$22946 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names dcd_I[19] $abc$24881$new_n4839 $abc$24881$new_n9845 $abc$24881$new_n5208 +001 1 +010 1 +100 1 +111 1 +.names dcd_I[17] $abc$24881$new_n5141 $abc$24881$new_n5118 $abc$24881$new_n5209 +000 1 +011 1 +101 1 +110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3763 r_op_Bv[19] o_mem_addr[19] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[16] $abc$24881$new_n5138 dcd_I[15] $abc$24881$new_n5139 $abc$24881$new_n5119 $abc$24881$new_n5214 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3769 r_op_Bv[18] o_mem_addr[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5177 dcd_I[15] $abc$24881$new_n5139 $abc$24881$new_n5119 $abc$24881$new_n5219 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[14] $abc$24881$new_n5136 dcd_I[13] $abc$24881$new_n5137 $abc$24881$new_n5120 $abc$24881$new_n5223 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names dcd_I[16] $abc$24881$new_n9508 $abc$24881$new_n5224 +00 1 +11 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3779 r_op_Bv[16] o_mem_addr[16] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[13] $abc$24881$new_n5137 $abc$24881$new_n5120 $abc$24881$new_n5229 +001 1 +010 1 +100 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5231 o_mem_addr[14] $abc$24881$new_n5067 $abc$24881$new_n5233 $abc$24881$auto$rtlil.cc:2693:MuxGate$22956 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5065 dcd_I[14] $abc$24881$new_n9505 $abc$24881$new_n5232 $abc$24881$new_n5231 +1001 1 +1010 1 +1100 1 +1111 1 +.names $abc$24881$new_n9502 dcd_I[13] $abc$24881$new_n9847 $abc$24881$new_n5232 +001 1 +100 1 +101 1 +111 1 +.names dcd_I[12] $abc$24881$new_n5134 dcd_I[11] $abc$24881$new_n5135 $abc$24881$new_n5121 $abc$24881$new_n5233 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3790 r_op_Bv[14] o_mem_addr[14] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[11] $abc$24881$new_n5135 $abc$24881$new_n5121 $abc$24881$new_n5238 +001 1 +010 1 +100 1 +111 1 +.names dcd_I[10] $abc$24881$new_n5132 dcd_I[9] $abc$24881$new_n5133 $abc$24881$new_n5122 $abc$24881$new_n5242 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3800 r_op_Bv[12] o_mem_addr[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5245 $abc$24881$new_n3805 r_op_Bv[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22962 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5246 dcd_I[9] $abc$24881$new_n5133 $abc$24881$new_n5122 $abc$24881$new_n5177 $abc$24881$new_n5245 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n5065 dcd_I[11] $abc$24881$new_n4660 $abc$24881$new_n4336 $abc$24881$new_n5246 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[8] $abc$24881$new_n5130 dcd_I[7] $abc$24881$new_n5131 $abc$24881$new_n5123 $abc$24881$new_n5250 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3810 r_op_Bv[10] o_mem_addr[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5066 o_mem_addr[9] $abc$24881$new_n5253 $abc$24881$new_n5254 $abc$24881$auto$rtlil.cc:2693:MuxGate$22966 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5065 $abc$24881$new_n4337 $abc$24881$new_n4658 $abc$24881$new_n4635 $abc$24881$new_n5253 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n5067 dcd_I[7] $abc$24881$new_n5131 $abc$24881$new_n5123 $abc$24881$new_n5254 +1001 1 +1010 1 +1100 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3815 r_op_Bv[9] o_mem_addr[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5257 $abc$24881$new_n3820 r_op_Bv[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22968 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5259 $abc$24881$new_n5258 $abc$24881$new_n5260 $abc$24881$new_n5257 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4566 $abc$24881$new_n4338 $abc$24881$new_n4590 $abc$24881$new_n5258 +001 1 +010 1 +011 1 +.names dcd_I[8] $abc$24881$new_n4591 $abc$24881$new_n5259 +00 1 +11 1 +.names dcd_I[6] $abc$24881$new_n5124 $abc$24881$new_n4068 SET_USER_PC.r_upc[8] instruction_decoder.o_pc[8] $abc$24881$new_n5260 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5262 $abc$24881$new_n3825 r_op_Bv[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22970 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5263 $abc$24881$new_n5264 $abc$24881$new_n5125 $abc$24881$new_n5177 $abc$24881$new_n5262 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +.names $abc$24881$new_n5065 dcd_I[7] $abc$24881$new_n9493 $abc$24881$new_n4338 $abc$24881$new_n5263 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[5] $abc$24881$new_n4068 SET_USER_PC.r_upc[7] instruction_decoder.o_pc[7] $abc$24881$new_n5264 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5266 $abc$24881$new_n3832 r_op_Bv[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22972 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5268 $abc$24881$new_n5267 $abc$24881$new_n5269 $abc$24881$new_n5266 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n9489 dcd_I[5] $abc$24881$new_n4339 $abc$24881$new_n5267 +001 1 +100 1 +101 1 +111 1 +.names dcd_I[6] $abc$24881$new_n9873 $abc$24881$new_n5268 +00 1 +11 1 +.names dcd_I[4] $abc$24881$new_n5126 $abc$24881$new_n4068 SET_USER_PC.r_upc[6] instruction_decoder.o_pc[6] $abc$24881$new_n5269 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5271 $abc$24881$new_n3838 r_op_Bv[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22974 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5272 $abc$24881$new_n5273 $abc$24881$new_n5127 $abc$24881$new_n5177 $abc$24881$new_n5271 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +.names $abc$24881$new_n5065 dcd_I[5] $abc$24881$new_n9489 $abc$24881$new_n4339 $abc$24881$new_n5272 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[3] $abc$24881$new_n4068 SET_USER_PC.r_upc[5] instruction_decoder.o_pc[5] $abc$24881$new_n5273 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n4406 dcd_I[3] $abc$24881$new_n9436 $abc$24881$new_n5276 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3843 r_op_Bv[4] o_mem_addr[4] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[2] $abc$24881$new_n4068 SET_USER_PC.r_upc[4] instruction_decoder.o_pc[4] $abc$24881$new_n5279 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5281 o_mem_addr[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22978 +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5067 $abc$24881$new_n5129 $abc$24881$new_n5283 $abc$24881$new_n5282 $abc$24881$new_n5281 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names dcd_I[3] $abc$24881$new_n4406 $abc$24881$new_n9436 $abc$24881$new_n5282 +000 1 +011 1 +101 1 +110 1 +.names dcd_I[1] $abc$24881$new_n4068 SET_USER_PC.r_upc[3] instruction_decoder.o_pc[3] $abc$24881$new_n5283 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names r_op_Bv[3] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3848 o_mem_addr[3] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5286 $abc$24881$new_n3853 r_op_Bv[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22980 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5287 $abc$24881$new_n5065 $abc$24881$new_n5288 $abc$24881$new_n5286 +000 1 +001 1 +011 1 +.names $abc$24881$new_n5177 dcd_I[0] $abc$24881$new_n4068 SET_USER_PC.r_upc[2] instruction_decoder.o_pc[2] $abc$24881$new_n5287 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names dcd_I[2] $abc$24881$new_n9442 dcd_I[1] $abc$24881$new_n4471 $abc$24881$new_n4439 $abc$24881$new_n5288 +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5290 o_mem_addr[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22982 +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5067 $abc$24881$new_n4471 $abc$24881$new_n5291 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4068 $abc$24881$new_n5290 +00000 1 +00001 1 +00010 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names dcd_I[1] $abc$24881$new_n4439 $abc$24881$new_n5291 +00 1 +11 1 +.names r_op_Bv[1] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3859 o_mem_addr[1] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 dcd_I[0] $abc$24881$new_n5294 $abc$24881$new_n5067 o_mem_addr[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22984 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11101 1 +.names $abc$24881$new_n4473 $abc$24881$new_n4500 $abc$24881$new_n4472 $abc$24881$new_n4474 $abc$24881$new_n5294 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names r_op_Bv[0] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3863 o_mem_addr[0] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[5] r_op_F[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22986 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[4] r_op_F[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22988 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[3] r_op_F[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22990 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[2] r_op_F[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22992 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[1] r_op_F[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22994 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[0] r_op_F[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22996 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] instruction_decoder.o_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$22998 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] instruction_decoder.o_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23000 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[28] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] instruction_decoder.o_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23002 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[27] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] instruction_decoder.o_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23004 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[26] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] instruction_decoder.o_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23006 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[25] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] instruction_decoder.o_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23008 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[24] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] instruction_decoder.o_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23010 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[23] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] instruction_decoder.o_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23012 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[22] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] instruction_decoder.o_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23014 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] instruction_decoder.o_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23016 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] instruction_decoder.o_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23018 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.o_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23020 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.o_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23022 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.o_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23024 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[16] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] instruction_decoder.o_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23026 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] instruction_decoder.o_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23028 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] instruction_decoder.o_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23030 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] instruction_decoder.o_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23032 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] instruction_decoder.o_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23034 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] instruction_decoder.o_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23036 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.o_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23038 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.o_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23040 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] instruction_decoder.o_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23042 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] instruction_decoder.o_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23044 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.o_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23046 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[5] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] instruction_decoder.o_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23048 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] instruction_decoder.o_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23050 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] instruction_decoder.o_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23052 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.o_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23054 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4030 wr_index[0] op_valid_div op_valid_mem $abc$24881$auto$rtlil.cc:2693:MuxGate$23056 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3963 GEN_ALU_PC.r_alu_pc[30] ipc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23058 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4035 $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$new_n5333 +110 1 +.names SET_GIE.r_gie GEN_ALU_PHASE.r_alu_phase $abc$24881$new_n3961 $abc$24881$new_n5334 +000 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3965 GEN_ALU_PC.r_alu_pc[29] ipc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23060 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3967 GEN_ALU_PC.r_alu_pc[28] ipc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23062 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3969 GEN_ALU_PC.r_alu_pc[27] ipc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23064 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3971 GEN_ALU_PC.r_alu_pc[26] ipc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23066 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3973 GEN_ALU_PC.r_alu_pc[25] ipc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23068 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3975 GEN_ALU_PC.r_alu_pc[24] ipc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23070 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3977 GEN_ALU_PC.r_alu_pc[23] ipc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23072 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3979 GEN_ALU_PC.r_alu_pc[22] ipc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23074 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3981 GEN_ALU_PC.r_alu_pc[21] ipc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23076 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3983 GEN_ALU_PC.r_alu_pc[20] ipc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23078 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3985 GEN_ALU_PC.r_alu_pc[19] ipc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23080 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3987 GEN_ALU_PC.r_alu_pc[18] ipc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23082 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3989 GEN_ALU_PC.r_alu_pc[17] ipc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23084 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3991 GEN_ALU_PC.r_alu_pc[16] ipc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23086 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3993 GEN_ALU_PC.r_alu_pc[15] ipc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23088 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3995 GEN_ALU_PC.r_alu_pc[14] ipc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23090 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3997 GEN_ALU_PC.r_alu_pc[13] ipc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23092 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3999 GEN_ALU_PC.r_alu_pc[12] ipc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23094 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4001 GEN_ALU_PC.r_alu_pc[11] ipc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23096 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4003 GEN_ALU_PC.r_alu_pc[10] ipc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23098 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4005 GEN_ALU_PC.r_alu_pc[9] ipc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23100 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4007 GEN_ALU_PC.r_alu_pc[8] ipc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23102 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4009 GEN_ALU_PC.r_alu_pc[7] ipc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23104 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4011 GEN_ALU_PC.r_alu_pc[6] ipc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23106 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4013 GEN_ALU_PC.r_alu_pc[5] ipc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23108 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4015 GEN_ALU_PC.r_alu_pc[4] ipc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23110 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4017 GEN_ALU_PC.r_alu_pc[3] ipc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23112 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4019 GEN_ALU_PC.r_alu_pc[2] ipc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23114 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[3] OP_REG_ADVANEC.r_op_Bid[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23116 +001 1 +011 1 +110 1 +111 1 +.names dcd_rB $abc$24881$new_n5066 instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n5364 +1100 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[2] OP_REG_ADVANEC.r_op_Bid[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23118 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[1] OP_REG_ADVANEC.r_op_Bid[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23120 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[0] OP_REG_ADVANEC.r_op_Bid[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23122 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[3] o_mem_reg[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23124 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[2] o_mem_reg[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23126 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[1] o_mem_reg[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23128 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[0] o_mem_reg[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23130 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[3] i_dbg_wreg[3] alu_reg[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23132 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5383 alu_ce o_mem_ce $abc$24881$new_n5373 +000 1 +.names $abc$24881$new_n5375 mem_ce o_mem_ce +11 1 +.names $abc$24881$new_n5378 $abc$24881$new_n5376 r_op_F[2] $abc$24881$new_n5381 $abc$24881$new_n5375 +1100 1 +1111 1 +.names $abc$24881$new_n5377 SET_GIE.r_gie r_op_F[3] $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n5376 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names r_op_F[1] SET_GIE.r_gie r_op_F[5] $abc$24881$new_n4470 $abc$24881$new_n4468 $abc$24881$new_n5377 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11100 1 +11101 1 +.names r_op_F[0] SET_GIE.r_gie r_op_F[4] $abc$24881$new_n5380 $abc$24881$new_n5379 $abc$24881$new_n5378 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11100 1 +11101 1 +.names $abc$24881$new_n4476 $abc$24881$new_n4475 $abc$24881$new_n5379 +00 1 +.names $abc$24881$new_n4400 $abc$24881$new_n4501 flags[0] $abc$24881$new_n5380 +000 1 +010 1 +110 1 +111 1 +.names r_op_F[6] SET_GIE.r_gie $abc$24881$new_n4435 $abc$24881$new_n4438 $abc$24881$new_n5381 +1000 1 +1001 1 +1100 1 +1110 1 +.names op_valid_alu $abc$24881$new_n4031 alu_ce +11 1 +.names op_valid_div $abc$24881$new_n5375 $abc$24881$new_n4031 $abc$24881$new_n5383 +111 1 +.names i_dbg_we o_dbg_stall $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y +10 1 +.names r_halted r_dbg_stall o_dbg_stall +00 1 +01 1 +11 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[2] i_dbg_wreg[2] alu_reg[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23134 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[1] i_dbg_wreg[1] alu_reg[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23136 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[0] i_dbg_wreg[0] alu_reg[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23138 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 o_mem_op[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[2] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23142 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 o_mem_op[1] dcd_opn[1] instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23146 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$24881$new_n5066 DIVIDE.thedivide.i_signed instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[0] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23150 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[30] $abc$24881$new_n5393 SET_OP_PC.r_op_pc[29] o_mem_lock_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23152 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5394 SET_OP_PC.r_op_pc[28] $abc$24881$new_n5393 +10 1 +.names $abc$24881$new_n5395 SET_OP_PC.r_op_pc[26] SET_OP_PC.r_op_pc[27] $abc$24881$new_n5394 +100 1 +.names $abc$24881$new_n5396 SET_OP_PC.r_op_pc[24] SET_OP_PC.r_op_pc[25] $abc$24881$new_n5395 +100 1 +.names $abc$24881$new_n5397 SET_OP_PC.r_op_pc[22] SET_OP_PC.r_op_pc[23] $abc$24881$new_n5396 +100 1 +.names $abc$24881$new_n5398 SET_OP_PC.r_op_pc[20] SET_OP_PC.r_op_pc[21] $abc$24881$new_n5397 +100 1 +.names $abc$24881$new_n5399 SET_OP_PC.r_op_pc[19] $abc$24881$new_n5398 +10 1 +.names $abc$24881$new_n5400 SET_OP_PC.r_op_pc[17] SET_OP_PC.r_op_pc[18] $abc$24881$new_n5399 +100 1 +.names $abc$24881$new_n5401 SET_OP_PC.r_op_pc[15] SET_OP_PC.r_op_pc[16] $abc$24881$new_n5400 +100 1 +.names $abc$24881$new_n5402 SET_OP_PC.r_op_pc[13] SET_OP_PC.r_op_pc[14] $abc$24881$new_n5401 +100 1 +.names $abc$24881$new_n5403 SET_OP_PC.r_op_pc[11] SET_OP_PC.r_op_pc[12] $abc$24881$new_n5402 +100 1 +.names $abc$24881$new_n5404 SET_OP_PC.r_op_pc[9] SET_OP_PC.r_op_pc[10] $abc$24881$new_n5403 +100 1 +.names $abc$24881$new_n5405 SET_OP_PC.r_op_pc[7] SET_OP_PC.r_op_pc[8] $abc$24881$new_n5404 +100 1 +.names $abc$24881$new_n5406 SET_OP_PC.r_op_pc[5] SET_OP_PC.r_op_pc[6] $abc$24881$new_n5405 +100 1 +.names SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] SET_OP_PC.r_op_pc[4] $abc$24881$new_n5406 +000 1 +.names op_valid GEN_OPLOCK.r_op_lock $abc$24881$new_n5066 $abc$24881$new_n5407 +111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[29] $abc$24881$new_n5393 o_mem_lock_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23154 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[28] $abc$24881$new_n5394 o_mem_lock_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23156 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[27] $abc$24881$new_n5395 SET_OP_PC.r_op_pc[26] o_mem_lock_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23158 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[26] $abc$24881$new_n5395 o_mem_lock_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23160 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[25] $abc$24881$new_n5396 SET_OP_PC.r_op_pc[24] o_mem_lock_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23162 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[24] $abc$24881$new_n5396 o_mem_lock_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23164 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[23] $abc$24881$new_n5397 SET_OP_PC.r_op_pc[22] o_mem_lock_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23166 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[22] $abc$24881$new_n5397 o_mem_lock_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23168 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[21] $abc$24881$new_n5398 SET_OP_PC.r_op_pc[20] o_mem_lock_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23170 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[20] $abc$24881$new_n5398 o_mem_lock_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23172 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[19] $abc$24881$new_n5399 o_mem_lock_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23174 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[18] $abc$24881$new_n5400 SET_OP_PC.r_op_pc[17] o_mem_lock_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23176 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[17] $abc$24881$new_n5400 o_mem_lock_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23178 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[16] $abc$24881$new_n5401 SET_OP_PC.r_op_pc[15] o_mem_lock_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23180 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[15] $abc$24881$new_n5401 o_mem_lock_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23182 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[14] $abc$24881$new_n5402 SET_OP_PC.r_op_pc[13] o_mem_lock_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23184 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[13] $abc$24881$new_n5402 o_mem_lock_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23186 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[12] $abc$24881$new_n5403 SET_OP_PC.r_op_pc[11] o_mem_lock_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23188 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[11] $abc$24881$new_n5403 o_mem_lock_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23190 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[10] $abc$24881$new_n5404 SET_OP_PC.r_op_pc[9] o_mem_lock_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23192 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[9] $abc$24881$new_n5404 o_mem_lock_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23194 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[8] $abc$24881$new_n5405 SET_OP_PC.r_op_pc[7] o_mem_lock_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23196 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[7] $abc$24881$new_n5405 o_mem_lock_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23198 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[6] $abc$24881$new_n5406 SET_OP_PC.r_op_pc[5] o_mem_lock_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23200 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[5] $abc$24881$new_n5406 o_mem_lock_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23202 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[4] SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] o_mem_lock_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23204 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] o_mem_lock_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23206 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[2] o_mem_lock_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23208 +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[1] o_mem_lock_pc[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23210 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5438 $abc$24881$new_n4028 dcd_I[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23212 +000 1 +001 1 +011 1 +.names $abc$24881$new_n5443 $abc$24881$new_n5439 $abc$24881$new_n4028 $abc$24881$new_n5438 +000 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4289 $abc$24881$new_n5439 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$24881$new_n5441 $abc$24881$new_n4283 $abc$24881$new_n4281 $abc$24881$new_n4271 $abc$24881$new_n5442 $abc$24881$new_n5440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4281 i_pf_instruction[12] i_pf_instruction[13] $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5441 +00100 1 +01100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[1] i_pf_instruction[17] $abc$24881$new_n5442 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4273 $abc$24881$new_n4266 $abc$24881$new_n4272 $abc$24881$new_n4283 $abc$24881$new_n4287 $abc$24881$new_n5443 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10010 1 +.names $abc$24881$new_n4028 dcd_I[20] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5445 $abc$24881$auto$rtlil.cc:2693:MuxGate$23214 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4291 $abc$24881$new_n5445 +100 1 +101 1 +110 1 +.names $abc$24881$new_n4028 dcd_I[19] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5447 $abc$24881$auto$rtlil.cc:2693:MuxGate$23216 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4293 $abc$24881$new_n5447 +100 1 +101 1 +111 1 +.names $abc$24881$new_n4028 dcd_I[18] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5449 $abc$24881$auto$rtlil.cc:2693:MuxGate$23218 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5449 +100 1 +101 1 +111 1 +.names $abc$24881$new_n4028 dcd_I[17] $abc$24881$new_n5451 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23220 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5441 i_pf_instruction[17] $abc$24881$new_n5452 $abc$24881$new_n5451 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4281 $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5452 +001 1 +010 1 +011 1 +.names $abc$24881$new_n4028 dcd_I[16] $abc$24881$new_n5454 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23222 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5441 $abc$24881$new_n5452 $abc$24881$new_n5455 $abc$24881$new_n5454 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[0] i_pf_instruction[16] $abc$24881$new_n5455 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4028 dcd_I[15] $abc$24881$new_n5457 $abc$24881$new_n4266 $abc$24881$new_n5441 $abc$24881$auto$rtlil.cc:2693:MuxGate$23224 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5452 i_pf_instruction[15] $abc$24881$new_n5457 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$24881$new_n4028 dcd_I[14] $abc$24881$new_n5459 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23226 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5441 i_pf_instruction[14] $abc$24881$new_n5452 $abc$24881$new_n5459 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4028 dcd_I[13] $abc$24881$new_n5443 $abc$24881$new_n5461 $abc$24881$auto$rtlil.cc:2693:MuxGate$23228 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n4281 i_pf_instruction[12] i_pf_instruction[13] $abc$24881$new_n5461 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 dcd_I[12] $abc$24881$new_n5443 i_pf_instruction[12] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23230 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[11] $abc$24881$new_n5443 i_pf_instruction[11] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23232 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[10] $abc$24881$new_n5443 i_pf_instruction[10] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23234 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[9] $abc$24881$new_n5443 i_pf_instruction[9] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23236 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[8] $abc$24881$new_n5443 i_pf_instruction[8] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23238 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[7] $abc$24881$new_n5443 i_pf_instruction[7] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23240 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[6] $abc$24881$new_n5469 $abc$24881$auto$rtlil.cc:2693:MuxGate$23242 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[6] $abc$24881$new_n4283 $abc$24881$new_n4287 $abc$24881$new_n5469 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4273 $abc$24881$new_n4272 $abc$24881$new_n5470 +00 1 +.names $abc$24881$new_n4028 dcd_I[5] $abc$24881$new_n5472 $abc$24881$auto$rtlil.cc:2693:MuxGate$23244 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[5] $abc$24881$new_n4283 $abc$24881$new_n4289 $abc$24881$new_n5472 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[4] $abc$24881$new_n5474 $abc$24881$auto$rtlil.cc:2693:MuxGate$23246 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[4] $abc$24881$new_n4283 $abc$24881$new_n4291 $abc$24881$new_n5474 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4028 dcd_I[3] $abc$24881$new_n5476 $abc$24881$auto$rtlil.cc:2693:MuxGate$23248 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n5477 $abc$24881$new_n5470 $abc$24881$new_n4283 $abc$24881$new_n4266 $abc$24881$new_n5476 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 i_pf_instruction[3] $abc$24881$new_n5470 $abc$24881$new_n4293 $abc$24881$new_n5477 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[2] i_pf_instruction[2] $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$23250 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[1] i_pf_instruction[1] $abc$24881$new_n5442 $abc$24881$auto$rtlil.cc:2693:MuxGate$23252 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[0] i_pf_instruction[0] $abc$24881$new_n5455 $abc$24881$auto$rtlil.cc:2693:MuxGate$23254 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names BUSLOCK.r_bus_lock[0] $abc$24881$new_n4030 BUSLOCK.r_bus_lock[1] GEN_OPLOCK.r_op_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23256 +0001 1 +0010 1 +0011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[30] SET_OP_PC.r_op_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23258 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[29] SET_OP_PC.r_op_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23260 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[28] SET_OP_PC.r_op_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23262 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[27] SET_OP_PC.r_op_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23264 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[26] SET_OP_PC.r_op_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23266 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[25] SET_OP_PC.r_op_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23268 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[24] SET_OP_PC.r_op_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23270 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[23] SET_OP_PC.r_op_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23272 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[22] SET_OP_PC.r_op_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23274 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[21] SET_OP_PC.r_op_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23276 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[20] SET_OP_PC.r_op_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23278 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[19] SET_OP_PC.r_op_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23280 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[18] SET_OP_PC.r_op_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23282 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[17] SET_OP_PC.r_op_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23284 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[16] SET_OP_PC.r_op_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23286 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[15] SET_OP_PC.r_op_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23288 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[14] SET_OP_PC.r_op_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23290 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[13] SET_OP_PC.r_op_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23292 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[12] SET_OP_PC.r_op_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23294 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[11] SET_OP_PC.r_op_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23296 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[10] SET_OP_PC.r_op_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23298 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[9] SET_OP_PC.r_op_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23300 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[8] SET_OP_PC.r_op_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23302 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[7] SET_OP_PC.r_op_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23304 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[6] SET_OP_PC.r_op_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23306 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[5] SET_OP_PC.r_op_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23308 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[4] SET_OP_PC.r_op_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23310 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[3] SET_OP_PC.r_op_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23312 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[2] SET_OP_PC.r_op_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23314 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n5529 $abc$24881$new_n5512 o_mem_addr[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23318 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5513 DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_divisor[28] $abc$24881$new_n5512 +100 1 +.names $abc$24881$new_n5514 DIVIDE.thedivide.r_divisor[26] $abc$24881$new_n5513 +10 1 +.names $abc$24881$new_n5515 DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n5514 +100 1 +.names $abc$24881$new_n5516 DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n5515 +100 1 +.names $abc$24881$new_n5517 DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n5516 +100 1 +.names $abc$24881$new_n5518 DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n5517 +100 1 +.names $abc$24881$new_n5519 DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n5518 +10 1 +.names $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_divisor[16] $abc$24881$new_n5519 +1000 1 +.names $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n5520 +10000 1 +.names $abc$24881$new_n5522 DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n5521 +10 1 +.names $abc$24881$new_n5523 DIVIDE.thedivide.r_divisor[8] $abc$24881$new_n5522 +10 1 +.names $abc$24881$new_n5524 DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n5523 +10 1 +.names $abc$24881$new_n5525 DIVIDE.thedivide.r_divisor[6] $abc$24881$new_n5524 +10 1 +.names $abc$24881$new_n5526 DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n5525 +10 1 +.names $abc$24881$new_n5527 DIVIDE.thedivide.r_divisor[4] $abc$24881$new_n5526 +10 1 +.names $abc$24881$new_n5528 DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5527 +100 1 +.names DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n5528 +00 1 +.names DIVIDE.thedivide.r_busy $abc$24881$new_n5530 $abc$24881$new_n5529 +10 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n5530 +11 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy $abc$24881$new_n5531 +11 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5533 DIVIDE.thedivide.r_divisor[28] o_mem_addr[28] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23320 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[28] $abc$24881$new_n5513 DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n5533 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n5529 $abc$24881$new_n5513 o_mem_addr[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23322 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[26] $abc$24881$new_n5529 $abc$24881$new_n5514 o_mem_addr[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23324 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3725 r_op_Bv[26] o_mem_addr[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5540 DIVIDE.thedivide.r_divisor[25] o_mem_addr[25] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23326 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n5515 DIVIDE.thedivide.r_divisor[24] $abc$24881$new_n5540 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3730 r_op_Bv[25] o_mem_addr[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[24] $abc$24881$new_n5529 $abc$24881$new_n5515 o_mem_addr[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23328 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5545 DIVIDE.thedivide.r_divisor[23] o_mem_addr[23] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23330 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n5516 DIVIDE.thedivide.r_divisor[22] $abc$24881$new_n5545 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3741 r_op_Bv[23] o_mem_addr[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[22] $abc$24881$new_n5529 $abc$24881$new_n5516 o_mem_addr[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23332 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5550 DIVIDE.thedivide.r_divisor[21] o_mem_addr[21] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23334 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n5517 DIVIDE.thedivide.r_divisor[20] $abc$24881$new_n5550 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3752 r_op_Bv[21] o_mem_addr[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[20] $abc$24881$new_n5529 $abc$24881$new_n5517 o_mem_addr[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23336 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5555 DIVIDE.thedivide.r_divisor[19] o_mem_addr[19] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23338 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n5518 DIVIDE.thedivide.r_divisor[18] $abc$24881$new_n5555 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[18] $abc$24881$new_n5529 $abc$24881$new_n5518 o_mem_addr[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23340 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n5529 $abc$24881$new_n5519 o_mem_addr[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23342 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3774 r_op_Bv[17] o_mem_addr[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5560 DIVIDE.thedivide.r_divisor[16] o_mem_addr[16] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23344 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[16] $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n5560 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5562 DIVIDE.thedivide.r_divisor[15] o_mem_addr[15] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23346 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] $abc$24881$new_n5562 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3784 r_op_Bv[15] o_mem_addr[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[14] $abc$24881$new_n5529 $abc$24881$new_n5520 o_mem_addr[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23348 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy $abc$24881$new_n5529 DIVIDE.thedivide.r_divisor[13] o_mem_addr[13] $abc$24881$new_n5568 $abc$24881$auto$rtlil.cc:2693:MuxGate$23350 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] $abc$24881$new_n5568 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3795 r_op_Bv[13] o_mem_addr[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5571 DIVIDE.thedivide.r_divisor[12] o_mem_addr[12] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23352 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[12] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n5571 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5573 DIVIDE.thedivide.r_divisor[11] o_mem_addr[11] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23354 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] $abc$24881$new_n5573 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3805 r_op_Bv[11] o_mem_addr[11] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[10] $abc$24881$new_n5521 $abc$24881$new_n5529 o_mem_addr[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23356 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n5530 $abc$24881$new_n5522 o_mem_addr[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23358 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[8] $abc$24881$new_n5530 $abc$24881$new_n5523 o_mem_addr[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23360 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3820 r_op_Bv[8] o_mem_addr[8] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n5530 $abc$24881$new_n5524 o_mem_addr[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23362 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3825 r_op_Bv[7] o_mem_addr[7] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[6] $abc$24881$new_n5529 $abc$24881$new_n5525 o_mem_addr[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23364 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3832 r_op_Bv[6] o_mem_addr[6] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n5530 $abc$24881$new_n5526 o_mem_addr[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23366 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3838 r_op_Bv[5] o_mem_addr[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[4] $abc$24881$new_n5529 $abc$24881$new_n5527 o_mem_addr[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23368 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 DIVIDE.thedivide.r_busy o_mem_addr[3] DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5588 $abc$24881$auto$rtlil.cc:2693:MuxGate$23370 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5528 DIVIDE.thedivide.r_divisor[2] $abc$24881$new_n5588 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[2] $abc$24881$new_n5529 $abc$24881$new_n5528 o_mem_addr[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23372 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3853 r_op_Bv[2] o_mem_addr[2] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_divisor[0] $abc$24881$new_n5530 o_mem_addr[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23374 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names DIVIDE.thedivide.r_busy o_mem_addr[0] DIVIDE.thedivide.r_divisor[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23376 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n5595 +10 1 +.names $abc$24881$new_n5599 $abc$24881$new_n5597 instruction_decoder.o_dcdA[0] $abc$24881$new_n3697 $abc$24881$new_n5066 $abc$24881$new_n5596 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11111 1 +.names $abc$24881$new_n5598 instruction_decoder.o_dcdA[3] $abc$24881$new_n3695 $abc$24881$new_n3959 $abc$24881$new_n5597 +1010 1 +1100 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[2] $abc$24881$new_n3701 $abc$24881$new_n3694 $abc$24881$new_n5598 +0011 1 +0101 1 +1010 1 +1100 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n3698 $abc$24881$new_n5599 +01 1 +10 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[30] SET_USER_PC.r_upc[30] $abc$24881$new_n5601 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n5603 $abc$24881$new_n5613 $abc$24881$new_n5618 $abc$24881$new_n5602 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5604 $abc$24881$new_n5611 $abc$24881$new_n5609 $abc$24881$new_n5603 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5605 $abc$24881$new_n5608 $abc$24881$new_n5607 $abc$24881$new_n5604 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$24881$new_n5606 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][30] regset[18][30] $abc$24881$new_n5605 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][30] regset[19][30] $abc$24881$new_n5606 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][30] regset[26][30] $abc$24881$new_n5607 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][30] regset[27][30] $abc$24881$new_n5608 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n5610 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[21][30] regset[17][30] $abc$24881$new_n5609 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][30] regset[16][30] $abc$24881$new_n5610 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n5612 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][30] regset[24][30] $abc$24881$new_n5611 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][30] regset[25][30] $abc$24881$new_n5612 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5614 $abc$24881$new_n5616 $abc$24881$new_n5613 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5615 regset[13][30] regset[9][30] $abc$24881$new_n5614 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][30] regset[8][30] $abc$24881$new_n5615 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5617 regset[4][30] regset[0][30] $abc$24881$new_n5616 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[5][30] regset[1][30] $abc$24881$new_n5617 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5620 $abc$24881$new_n5619 $abc$24881$new_n5622 $abc$24881$new_n5621 $abc$24881$new_n5618 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[14][30] regset[6][30] $abc$24881$new_n5619 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[10][30] regset[2][30] $abc$24881$new_n5620 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[15][30] regset[7][30] $abc$24881$new_n5621 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[11][30] regset[3][30] $abc$24881$new_n5622 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$24881$new_n5066 $abc$24881$new_n3692 OP_REG_ADVANEC.r_op_rA $abc$24881$new_n5623 +000 1 +001 1 +010 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5629 $abc$24881$new_n5631 $abc$24881$new_n5633 $abc$24881$new_n5628 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5630 regset[5][29] regset[1][29] $abc$24881$new_n5629 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][29] regset[0][29] $abc$24881$new_n5630 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5632 regset[15][29] regset[11][29] $abc$24881$new_n5631 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][29] regset[10][29] $abc$24881$new_n5632 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5634 regset[7][29] regset[3][29] $abc$24881$new_n5633 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][29] regset[2][29] $abc$24881$new_n5634 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5636 regset[13][29] regset[9][29] $abc$24881$new_n5635 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][29] regset[8][29] $abc$24881$new_n5636 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5637 +10 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5640 $abc$24881$new_n5642 $abc$24881$new_n5644 $abc$24881$new_n5639 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5641 regset[31][29] regset[27][29] $abc$24881$new_n5640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][29] regset[26][29] $abc$24881$new_n5641 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5643 regset[21][29] regset[17][29] $abc$24881$new_n5642 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][29] regset[16][29] $abc$24881$new_n5643 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5645 regset[23][29] regset[19][29] $abc$24881$new_n5644 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][29] regset[18][29] $abc$24881$new_n5645 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5647 regset[29][29] regset[25][29] $abc$24881$new_n5646 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][29] regset[24][29] $abc$24881$new_n5647 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5660 $abc$24881$new_n5653 $abc$24881$new_n5658 instruction_decoder.o_dcdA[3] $abc$24881$new_n5652 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5654 $abc$24881$new_n5656 $abc$24881$new_n5653 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5655 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[23][28] regset[19][28] $abc$24881$new_n5654 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[31][28] regset[27][28] $abc$24881$new_n5655 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n5657 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[22][28] regset[18][28] $abc$24881$new_n5656 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[30][28] regset[26][28] $abc$24881$new_n5657 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5659 regset[21][28] regset[17][28] $abc$24881$new_n5658 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][28] regset[16][28] $abc$24881$new_n5659 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5661 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][28] regset[24][28] $abc$24881$new_n5660 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][28] regset[25][28] $abc$24881$new_n5661 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5663 $abc$24881$new_n5670 $abc$24881$new_n5668 $abc$24881$new_n5662 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5664 $abc$24881$new_n5666 $abc$24881$new_n5663 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5665 regset[13][28] regset[9][28] $abc$24881$new_n5664 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][28] regset[8][28] $abc$24881$new_n5665 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5667 regset[4][28] regset[0][28] $abc$24881$new_n5666 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[5][28] regset[1][28] $abc$24881$new_n5667 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5669 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][28] regset[2][28] $abc$24881$new_n5668 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[7][28] regset[3][28] $abc$24881$new_n5669 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n5671 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[14][28] regset[10][28] $abc$24881$new_n5670 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[15][28] regset[11][28] $abc$24881$new_n5671 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names dcd_Apc $abc$24881$new_n5596 $abc$24881$new_n5672 +11 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5679 $abc$24881$new_n5686 $abc$24881$new_n5684 $abc$24881$new_n5678 +0000 1 +0100 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[0] $abc$24881$new_n5680 $abc$24881$new_n5682 $abc$24881$new_n5683 $abc$24881$new_n5679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n5681 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][27] regset[24][27] $abc$24881$new_n5680 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][27] regset[25][27] $abc$24881$new_n5681 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] regset[31][27] regset[27][27] $abc$24881$new_n5682 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[2] regset[30][27] regset[26][27] $abc$24881$new_n5683 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5685 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[18][27] regset[16][27] $abc$24881$new_n5684 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[22][27] regset[20][27] $abc$24881$new_n5685 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n5687 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[19][27] regset[17][27] $abc$24881$new_n5686 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[23][27] regset[21][27] $abc$24881$new_n5687 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5690 regset[15][27] regset[11][27] $abc$24881$new_n5689 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][27] regset[10][27] $abc$24881$new_n5690 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5692 regset[13][27] regset[9][27] $abc$24881$new_n5691 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][27] regset[8][27] $abc$24881$new_n5692 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5695 regset[5][27] regset[1][27] $abc$24881$new_n5694 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][27] regset[0][27] $abc$24881$new_n5695 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5698 regset[7][27] regset[3][27] $abc$24881$new_n5697 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][27] regset[2][27] $abc$24881$new_n5698 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5709 $abc$24881$new_n5704 $abc$24881$new_n5711 instruction_decoder.o_dcdA[1] $abc$24881$new_n5703 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5705 $abc$24881$new_n5708 $abc$24881$new_n5707 $abc$24881$new_n5704 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5706 regset[5][26] regset[1][26] $abc$24881$new_n5705 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][26] regset[0][26] $abc$24881$new_n5706 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][26] regset[2][26] $abc$24881$new_n5707 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][26] regset[3][26] $abc$24881$new_n5708 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n5710 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][26] regset[9][26] $abc$24881$new_n5709 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][26] regset[8][26] $abc$24881$new_n5710 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5712 regset[15][26] regset[11][26] $abc$24881$new_n5711 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][26] regset[10][26] $abc$24881$new_n5712 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5714 $abc$24881$new_n5719 $abc$24881$new_n5721 $abc$24881$new_n5713 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5715 $abc$24881$new_n5717 $abc$24881$new_n5714 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5716 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][26] regset[26][26] $abc$24881$new_n5715 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][26] regset[27][26] $abc$24881$new_n5716 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5718 regset[29][26] regset[25][26] $abc$24881$new_n5717 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][26] regset[24][26] $abc$24881$new_n5718 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5720 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][26] regset[18][26] $abc$24881$new_n5719 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][26] regset[19][26] $abc$24881$new_n5720 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5722 regset[21][26] regset[17][26] $abc$24881$new_n5721 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][26] regset[16][26] $abc$24881$new_n5722 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5725 r_op_Av[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23388 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n5726 $abc$24881$new_n5672 $abc$24881$new_n5595 $abc$24881$new_n5747 $abc$24881$new_n3730 $abc$24881$new_n5725 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n5595 instruction_decoder.o_dcdA[1] dcd_Acc $abc$24881$new_n5727 $abc$24881$new_n5737 $abc$24881$new_n5726 +10001 1 +10011 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] $abc$24881$new_n5728 $abc$24881$new_n5733 $abc$24881$new_n5735 $abc$24881$new_n5727 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5730 $abc$24881$new_n5729 $abc$24881$new_n5732 $abc$24881$new_n5731 $abc$24881$new_n5728 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][25] regset[19][25] $abc$24881$new_n5729 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][25] regset[18][25] $abc$24881$new_n5730 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][25] regset[27][25] $abc$24881$new_n5731 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][25] regset[26][25] $abc$24881$new_n5732 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5734 regset[15][25] regset[11][25] $abc$24881$new_n5733 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][25] regset[10][25] $abc$24881$new_n5734 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5736 regset[6][25] regset[2][25] $abc$24881$new_n5735 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[7][25] regset[3][25] $abc$24881$new_n5736 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] $abc$24881$new_n5738 $abc$24881$new_n5743 $abc$24881$new_n5745 $abc$24881$new_n5737 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5740 $abc$24881$new_n5739 $abc$24881$new_n5742 $abc$24881$new_n5741 $abc$24881$new_n5738 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[21][25] regset[17][25] $abc$24881$new_n5739 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][25] regset[16][25] $abc$24881$new_n5740 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][25] regset[25][25] $abc$24881$new_n5741 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][25] regset[24][25] $abc$24881$new_n5742 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5744 regset[12][25] regset[8][25] $abc$24881$new_n5743 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[13][25] regset[9][25] $abc$24881$new_n5744 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5746 regset[4][25] regset[0][25] $abc$24881$new_n5745 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[5][25] regset[1][25] $abc$24881$new_n5746 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[25] SET_USER_PC.r_upc[25] $abc$24881$new_n5747 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5753 $abc$24881$new_n5755 $abc$24881$new_n5757 $abc$24881$new_n5752 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5754 regset[21][24] regset[17][24] $abc$24881$new_n5753 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][24] regset[16][24] $abc$24881$new_n5754 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5756 regset[31][24] regset[27][24] $abc$24881$new_n5755 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][24] regset[26][24] $abc$24881$new_n5756 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5758 regset[23][24] regset[19][24] $abc$24881$new_n5757 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][24] regset[18][24] $abc$24881$new_n5758 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5760 regset[29][24] regset[25][24] $abc$24881$new_n5759 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][24] regset[24][24] $abc$24881$new_n5760 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5763 $abc$24881$new_n5765 $abc$24881$new_n5767 $abc$24881$new_n5762 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5764 regset[5][24] regset[1][24] $abc$24881$new_n5763 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][24] regset[0][24] $abc$24881$new_n5764 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5766 regset[15][24] regset[11][24] $abc$24881$new_n5765 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][24] regset[10][24] $abc$24881$new_n5766 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5768 regset[7][24] regset[3][24] $abc$24881$new_n5767 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][24] regset[2][24] $abc$24881$new_n5768 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5770 regset[13][24] regset[9][24] $abc$24881$new_n5769 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][24] regset[8][24] $abc$24881$new_n5770 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n9598 r_op_Av[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23392 +000 1 +001 1 +101 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5777 $abc$24881$new_n5779 $abc$24881$new_n5781 $abc$24881$new_n5776 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5778 regset[15][23] regset[11][23] $abc$24881$new_n5777 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][23] regset[10][23] $abc$24881$new_n5778 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5780 regset[13][23] regset[9][23] $abc$24881$new_n5779 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][23] regset[8][23] $abc$24881$new_n5780 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5782 regset[7][23] regset[3][23] $abc$24881$new_n5781 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][23] regset[2][23] $abc$24881$new_n5782 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5784 regset[5][23] regset[1][23] $abc$24881$new_n5783 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][23] regset[0][23] $abc$24881$new_n5784 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5787 $abc$24881$new_n5789 $abc$24881$new_n5791 $abc$24881$new_n5786 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5788 regset[31][23] regset[27][23] $abc$24881$new_n5787 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][23] regset[26][23] $abc$24881$new_n5788 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5790 regset[29][23] regset[25][23] $abc$24881$new_n5789 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][23] regset[24][23] $abc$24881$new_n5790 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5792 regset[21][23] regset[17][23] $abc$24881$new_n5791 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][23] regset[16][23] $abc$24881$new_n5792 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5794 regset[23][23] regset[19][23] $abc$24881$new_n5793 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][23] regset[18][23] $abc$24881$new_n5794 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[23] SET_USER_PC.r_upc[23] $abc$24881$new_n5795 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5800 $abc$24881$new_n5805 $abc$24881$new_n5807 $abc$24881$new_n5799 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5801 $abc$24881$new_n5803 $abc$24881$new_n5800 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5802 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][22] regset[26][22] $abc$24881$new_n5801 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][22] regset[27][22] $abc$24881$new_n5802 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5804 regset[29][22] regset[25][22] $abc$24881$new_n5803 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][22] regset[24][22] $abc$24881$new_n5804 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5806 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][22] regset[18][22] $abc$24881$new_n5805 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][22] regset[19][22] $abc$24881$new_n5806 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5808 regset[21][22] regset[17][22] $abc$24881$new_n5807 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][22] regset[16][22] $abc$24881$new_n5808 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5810 $abc$24881$new_n5813 $abc$24881$new_n5812 $abc$24881$new_n5809 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5811 regset[5][22] regset[1][22] $abc$24881$new_n5810 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][22] regset[0][22] $abc$24881$new_n5811 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][22] regset[2][22] $abc$24881$new_n5812 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][22] regset[3][22] $abc$24881$new_n5813 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5816 regset[15][22] regset[14][22] $abc$24881$new_n5815 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[11][22] regset[10][22] $abc$24881$new_n5816 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5818 regset[13][22] regset[12][22] $abc$24881$new_n5817 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[9][22] regset[8][22] $abc$24881$new_n5818 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[22] SET_USER_PC.r_upc[22] $abc$24881$new_n5819 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5823 $abc$24881$new_n5828 $abc$24881$new_n5830 $abc$24881$new_n5822 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5824 $abc$24881$new_n5827 $abc$24881$new_n5826 $abc$24881$new_n5823 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5825 regset[29][21] regset[25][21] $abc$24881$new_n5824 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][21] regset[24][21] $abc$24881$new_n5825 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][21] regset[27][21] $abc$24881$new_n5826 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][21] regset[26][21] $abc$24881$new_n5827 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5829 regset[23][21] regset[19][21] $abc$24881$new_n5828 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][21] regset[18][21] $abc$24881$new_n5829 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5831 regset[21][21] regset[17][21] $abc$24881$new_n5830 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][21] regset[16][21] $abc$24881$new_n5831 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5833 $abc$24881$new_n5838 $abc$24881$new_n5637 $abc$24881$new_n5840 $abc$24881$new_n5832 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5834 $abc$24881$new_n5837 $abc$24881$new_n5836 $abc$24881$new_n5833 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5835 regset[5][21] regset[1][21] $abc$24881$new_n5834 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][21] regset[0][21] $abc$24881$new_n5835 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][21] regset[2][21] $abc$24881$new_n5836 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][21] regset[3][21] $abc$24881$new_n5837 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n5839 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[15][21] regset[11][21] $abc$24881$new_n5838 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[14][21] regset[10][21] $abc$24881$new_n5839 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5841 regset[13][21] regset[9][21] $abc$24881$new_n5840 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][21] regset[8][21] $abc$24881$new_n5841 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[21] SET_USER_PC.r_upc[21] $abc$24881$new_n5843 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5848 $abc$24881$new_n5853 $abc$24881$new_n5855 $abc$24881$new_n5847 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5849 $abc$24881$new_n5852 $abc$24881$new_n5851 $abc$24881$new_n5848 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5850 regset[5][20] regset[1][20] $abc$24881$new_n5849 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][20] regset[0][20] $abc$24881$new_n5850 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][20] regset[2][20] $abc$24881$new_n5851 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][20] regset[3][20] $abc$24881$new_n5852 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5854 regset[13][20] regset[9][20] $abc$24881$new_n5853 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][20] regset[8][20] $abc$24881$new_n5854 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5856 regset[15][20] regset[11][20] $abc$24881$new_n5855 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][20] regset[10][20] $abc$24881$new_n5856 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5858 $abc$24881$new_n5863 $abc$24881$new_n5865 $abc$24881$new_n5857 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5859 $abc$24881$new_n5861 $abc$24881$new_n5858 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5860 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][20] regset[26][20] $abc$24881$new_n5859 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][20] regset[27][20] $abc$24881$new_n5860 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5862 regset[29][20] regset[25][20] $abc$24881$new_n5861 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][20] regset[24][20] $abc$24881$new_n5862 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5864 regset[23][20] regset[19][20] $abc$24881$new_n5863 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][20] regset[18][20] $abc$24881$new_n5864 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5866 regset[21][20] regset[17][20] $abc$24881$new_n5865 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][20] regset[16][20] $abc$24881$new_n5866 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5869 r_op_Av[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23400 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3763 $abc$24881$new_n5870 $abc$24881$new_n5891 $abc$24881$new_n5869 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n5871 $abc$24881$new_n5881 $abc$24881$new_n5886 $abc$24881$new_n5870 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5872 $abc$24881$new_n5877 $abc$24881$new_n5879 instruction_decoder.o_dcdA[3] $abc$24881$new_n5871 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5875 $abc$24881$new_n5873 instruction_decoder.o_dcdA[3] $abc$24881$new_n5872 +010 1 +100 1 +101 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5874 regset[20][19] regset[16][19] $abc$24881$new_n5873 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[21][19] regset[17][19] $abc$24881$new_n5874 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5876 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][19] regset[24][19] $abc$24881$new_n5875 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][19] regset[25][19] $abc$24881$new_n5876 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5878 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][19] regset[26][19] $abc$24881$new_n5877 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[31][19] regset[27][19] $abc$24881$new_n5878 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5880 regset[22][19] regset[18][19] $abc$24881$new_n5879 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[23][19] regset[19][19] $abc$24881$new_n5880 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5884 $abc$24881$new_n5882 instruction_decoder.o_dcdA[3] $abc$24881$new_n5881 +010 1 +100 1 +101 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5883 regset[4][19] regset[0][19] $abc$24881$new_n5882 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[5][19] regset[1][19] $abc$24881$new_n5883 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5885 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][19] regset[8][19] $abc$24881$new_n5884 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][19] regset[9][19] $abc$24881$new_n5885 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5888 $abc$24881$new_n5887 $abc$24881$new_n5890 $abc$24881$new_n5889 $abc$24881$new_n5886 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[14][19] regset[10][19] $abc$24881$new_n5887 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[6][19] regset[2][19] $abc$24881$new_n5888 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[15][19] regset[11][19] $abc$24881$new_n5889 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[7][19] regset[3][19] $abc$24881$new_n5890 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[19] SET_USER_PC.r_upc[19] $abc$24881$new_n5891 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5896 $abc$24881$new_n5901 $abc$24881$new_n5903 $abc$24881$new_n5895 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5897 $abc$24881$new_n5899 $abc$24881$new_n5896 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5898 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][18] regset[26][18] $abc$24881$new_n5897 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][18] regset[27][18] $abc$24881$new_n5898 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5900 regset[29][18] regset[25][18] $abc$24881$new_n5899 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][18] regset[24][18] $abc$24881$new_n5900 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5902 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][18] regset[18][18] $abc$24881$new_n5901 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][18] regset[19][18] $abc$24881$new_n5902 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5904 regset[21][18] regset[17][18] $abc$24881$new_n5903 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][18] regset[16][18] $abc$24881$new_n5904 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5906 $abc$24881$new_n5909 $abc$24881$new_n5908 $abc$24881$new_n5905 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5907 regset[5][18] regset[1][18] $abc$24881$new_n5906 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][18] regset[0][18] $abc$24881$new_n5907 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][18] regset[2][18] $abc$24881$new_n5908 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][18] regset[3][18] $abc$24881$new_n5909 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5912 regset[13][18] regset[12][18] $abc$24881$new_n5911 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[9][18] regset[8][18] $abc$24881$new_n5912 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5914 regset[15][18] regset[14][18] $abc$24881$new_n5913 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[11][18] regset[10][18] $abc$24881$new_n5914 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[18] SET_USER_PC.r_upc[18] $abc$24881$new_n5915 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5917 r_op_Av[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23404 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3774 $abc$24881$new_n5918 $abc$24881$new_n5939 $abc$24881$new_n5917 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n5934 $abc$24881$new_n5919 $abc$24881$new_n5929 instruction_decoder.o_dcdA[3] $abc$24881$new_n5918 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5920 $abc$24881$new_n5925 $abc$24881$new_n5927 $abc$24881$new_n5919 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5921 $abc$24881$new_n5923 $abc$24881$new_n5920 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5922 regset[23][17] regset[19][17] $abc$24881$new_n5921 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][17] regset[18][17] $abc$24881$new_n5922 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5924 regset[21][17] regset[17][17] $abc$24881$new_n5923 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][17] regset[16][17] $abc$24881$new_n5924 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5926 regset[30][17] regset[26][17] $abc$24881$new_n5925 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[31][17] regset[27][17] $abc$24881$new_n5926 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5928 regset[29][17] regset[25][17] $abc$24881$new_n5927 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][17] regset[24][17] $abc$24881$new_n5928 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5930 $abc$24881$new_n5933 $abc$24881$new_n5932 $abc$24881$new_n5929 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5931 regset[5][17] regset[1][17] $abc$24881$new_n5930 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][17] regset[0][17] $abc$24881$new_n5931 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][17] regset[2][17] $abc$24881$new_n5932 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][17] regset[3][17] $abc$24881$new_n5933 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5935 $abc$24881$new_n5938 $abc$24881$new_n5937 $abc$24881$new_n5934 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5936 regset[15][17] regset[11][17] $abc$24881$new_n5935 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][17] regset[10][17] $abc$24881$new_n5936 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[13][17] regset[9][17] $abc$24881$new_n5937 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][17] regset[8][17] $abc$24881$new_n5938 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[17] SET_USER_PC.r_upc[17] $abc$24881$new_n5939 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5944 $abc$24881$new_n5949 $abc$24881$new_n5951 $abc$24881$new_n5943 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5945 $abc$24881$new_n5947 $abc$24881$new_n5944 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5946 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][16] regset[26][16] $abc$24881$new_n5945 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][16] regset[27][16] $abc$24881$new_n5946 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5948 regset[29][16] regset[25][16] $abc$24881$new_n5947 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][16] regset[24][16] $abc$24881$new_n5948 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5950 regset[23][16] regset[19][16] $abc$24881$new_n5949 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][16] regset[18][16] $abc$24881$new_n5950 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5952 regset[21][16] regset[17][16] $abc$24881$new_n5951 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][16] regset[16][16] $abc$24881$new_n5952 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5954 $abc$24881$new_n5957 $abc$24881$new_n5956 $abc$24881$new_n5953 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5955 regset[5][16] regset[1][16] $abc$24881$new_n5954 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][16] regset[0][16] $abc$24881$new_n5955 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][16] regset[2][16] $abc$24881$new_n5956 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][16] regset[3][16] $abc$24881$new_n5957 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5960 regset[15][16] regset[11][16] $abc$24881$new_n5959 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][16] regset[10][16] $abc$24881$new_n5960 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5962 regset[13][16] regset[9][16] $abc$24881$new_n5961 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][16] regset[8][16] $abc$24881$new_n5962 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[16] SET_USER_PC.r_upc[16] $abc$24881$new_n5963 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5968 $abc$24881$new_n5973 $abc$24881$new_n5975 $abc$24881$new_n5967 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5969 $abc$24881$new_n5971 $abc$24881$new_n5968 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5970 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][15] regset[26][15] $abc$24881$new_n5969 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][15] regset[27][15] $abc$24881$new_n5970 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5972 regset[29][15] regset[25][15] $abc$24881$new_n5971 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][15] regset[24][15] $abc$24881$new_n5972 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5974 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][15] regset[18][15] $abc$24881$new_n5973 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][15] regset[19][15] $abc$24881$new_n5974 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5976 regset[21][15] regset[17][15] $abc$24881$new_n5975 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][15] regset[16][15] $abc$24881$new_n5976 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5983 $abc$24881$new_n5978 $abc$24881$new_n5985 instruction_decoder.o_dcdA[1] $abc$24881$new_n5977 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5979 $abc$24881$new_n5982 $abc$24881$new_n5981 $abc$24881$new_n5978 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5980 regset[5][15] regset[1][15] $abc$24881$new_n5979 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][15] regset[0][15] $abc$24881$new_n5980 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][15] regset[2][15] $abc$24881$new_n5981 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][15] regset[3][15] $abc$24881$new_n5982 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n5984 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][15] regset[8][15] $abc$24881$new_n5983 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][15] regset[9][15] $abc$24881$new_n5984 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5986 regset[15][15] regset[11][15] $abc$24881$new_n5985 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][15] regset[10][15] $abc$24881$new_n5986 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5993 $abc$24881$new_n5996 $abc$24881$new_n5995 $abc$24881$new_n5992 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5994 regset[5][14] regset[1][14] $abc$24881$new_n5993 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][14] regset[0][14] $abc$24881$new_n5994 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][14] regset[2][14] $abc$24881$new_n5995 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][14] regset[3][14] $abc$24881$new_n5996 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5999 regset[15][14] regset[11][14] $abc$24881$new_n5998 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][14] regset[10][14] $abc$24881$new_n5999 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6001 regset[13][14] regset[9][14] $abc$24881$new_n6000 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][14] regset[8][14] $abc$24881$new_n6001 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6003 $abc$24881$new_n6008 $abc$24881$new_n6010 $abc$24881$new_n6002 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n6004 $abc$24881$new_n6006 $abc$24881$new_n6003 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6005 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][14] regset[26][14] $abc$24881$new_n6004 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][14] regset[27][14] $abc$24881$new_n6005 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6007 regset[29][14] regset[25][14] $abc$24881$new_n6006 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][14] regset[24][14] $abc$24881$new_n6007 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6009 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][14] regset[18][14] $abc$24881$new_n6008 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][14] regset[19][14] $abc$24881$new_n6009 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6011 regset[21][14] regset[17][14] $abc$24881$new_n6010 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][14] regset[16][14] $abc$24881$new_n6011 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6014 r_op_Av[13] $abc$24881$new_n5595 $abc$24881$new_n6016 $abc$24881$auto$rtlil.cc:2693:MuxGate$23412 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5596 $abc$24881$new_n3795 dcd_Apc $abc$24881$new_n6015 $abc$24881$new_n6014 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[13] SET_USER_PC.r_upc[13] $abc$24881$new_n6015 +000 1 +010 1 +100 1 +101 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6017 GEN_UHALT_PHASE.r_uhalt_phase GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n6016 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6018 $abc$24881$new_n6030 $abc$24881$new_n6028 $abc$24881$new_n6017 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$24881$new_n6019 $abc$24881$new_n6026 $abc$24881$new_n5637 $abc$24881$new_n6018 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6020 $abc$24881$new_n6022 $abc$24881$new_n6024 $abc$24881$new_n6019 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6021 regset[21][13] regset[17][13] $abc$24881$new_n6020 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][13] regset[16][13] $abc$24881$new_n6021 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6023 regset[23][13] regset[19][13] $abc$24881$new_n6022 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][13] regset[18][13] $abc$24881$new_n6023 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6025 regset[31][13] regset[27][13] $abc$24881$new_n6024 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][13] regset[26][13] $abc$24881$new_n6025 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6027 regset[29][13] regset[25][13] $abc$24881$new_n6026 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][13] regset[24][13] $abc$24881$new_n6027 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6029 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][13] regset[8][13] $abc$24881$new_n6028 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][13] regset[9][13] $abc$24881$new_n6029 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6031 $abc$24881$new_n6033 $abc$24881$new_n6035 $abc$24881$new_n6030 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6032 regset[5][13] regset[1][13] $abc$24881$new_n6031 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][13] regset[0][13] $abc$24881$new_n6032 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6034 regset[15][13] regset[11][13] $abc$24881$new_n6033 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][13] regset[10][13] $abc$24881$new_n6034 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6036 regset[7][13] regset[6][13] $abc$24881$new_n6035 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[3][13] regset[2][13] $abc$24881$new_n6036 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[12] SET_USER_PC.r_upc[12] $abc$24881$new_n6040 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n6042 $abc$24881$new_n6052 $abc$24881$new_n6057 $abc$24881$new_n6041 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n6043 $abc$24881$new_n6050 $abc$24881$new_n6048 $abc$24881$new_n6042 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n6044 $abc$24881$new_n6047 $abc$24881$new_n6046 $abc$24881$new_n6043 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$24881$new_n6045 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][12] regset[18][12] $abc$24881$new_n6044 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][12] regset[19][12] $abc$24881$new_n6045 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][12] regset[26][12] $abc$24881$new_n6046 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][12] regset[27][12] $abc$24881$new_n6047 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n6049 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[21][12] regset[17][12] $abc$24881$new_n6048 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][12] regset[16][12] $abc$24881$new_n6049 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n6051 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][12] regset[24][12] $abc$24881$new_n6050 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][12] regset[25][12] $abc$24881$new_n6051 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n6053 $abc$24881$new_n6055 $abc$24881$new_n6052 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6054 regset[13][12] regset[9][12] $abc$24881$new_n6053 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][12] regset[8][12] $abc$24881$new_n6054 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6056 regset[4][12] regset[0][12] $abc$24881$new_n6055 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[5][12] regset[1][12] $abc$24881$new_n6056 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] $abc$24881$new_n6059 $abc$24881$new_n6058 $abc$24881$new_n6061 $abc$24881$new_n6060 $abc$24881$new_n6057 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[14][12] regset[6][12] $abc$24881$new_n6058 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[10][12] regset[2][12] $abc$24881$new_n6059 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[15][12] regset[7][12] $abc$24881$new_n6060 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[11][12] regset[3][12] $abc$24881$new_n6061 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6063 r_op_Av[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23416 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3805 $abc$24881$new_n9625 $abc$24881$new_n6086 $abc$24881$new_n6063 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6068 $abc$24881$new_n6070 $abc$24881$new_n6072 $abc$24881$new_n6067 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6069 regset[21][11] regset[17][11] $abc$24881$new_n6068 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][11] regset[16][11] $abc$24881$new_n6069 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6071 regset[31][11] regset[27][11] $abc$24881$new_n6070 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][11] regset[26][11] $abc$24881$new_n6071 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6073 regset[23][11] regset[19][11] $abc$24881$new_n6072 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][11] regset[18][11] $abc$24881$new_n6073 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6077 $abc$24881$new_n5637 $abc$24881$new_n6085 $abc$24881$new_n6084 $abc$24881$new_n6076 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6078 $abc$24881$new_n6080 $abc$24881$new_n6082 $abc$24881$new_n6077 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6079 regset[15][11] regset[11][11] $abc$24881$new_n6078 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][11] regset[10][11] $abc$24881$new_n6079 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6081 regset[7][11] regset[6][11] $abc$24881$new_n6080 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[3][11] regset[2][11] $abc$24881$new_n6081 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6083 regset[5][11] regset[1][11] $abc$24881$new_n6082 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][11] regset[0][11] $abc$24881$new_n6083 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[13][11] regset[9][11] $abc$24881$new_n6084 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][11] regset[8][11] $abc$24881$new_n6085 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[11] SET_USER_PC.r_upc[11] $abc$24881$new_n6086 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6088 r_op_Av[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23418 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3810 $abc$24881$new_n6089 $abc$24881$new_n6110 $abc$24881$new_n6088 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6090 SET_USER_BUSERR.r_ubus_err_flag ibus_err_flag $abc$24881$new_n6089 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6091 $abc$24881$new_n6103 $abc$24881$new_n6101 $abc$24881$new_n6090 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n6092 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6097 $abc$24881$new_n6099 $abc$24881$new_n6091 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6093 $abc$24881$new_n6095 $abc$24881$new_n6092 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6094 regset[5][10] regset[1][10] $abc$24881$new_n6093 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][10] regset[0][10] $abc$24881$new_n6094 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6096 regset[7][10] regset[3][10] $abc$24881$new_n6095 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][10] regset[2][10] $abc$24881$new_n6096 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6098 regset[15][10] regset[11][10] $abc$24881$new_n6097 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][10] regset[10][10] $abc$24881$new_n6098 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6100 regset[13][10] regset[9][10] $abc$24881$new_n6099 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][10] regset[8][10] $abc$24881$new_n6100 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6102 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][10] regset[25][10] $abc$24881$new_n6101 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][10] regset[24][10] $abc$24881$new_n6102 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6104 $abc$24881$new_n6106 $abc$24881$new_n6108 $abc$24881$new_n6103 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6105 regset[21][10] regset[17][10] $abc$24881$new_n6104 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][10] regset[16][10] $abc$24881$new_n6105 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6107 regset[23][10] regset[19][10] $abc$24881$new_n6106 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][10] regset[18][10] $abc$24881$new_n6107 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6109 regset[31][10] regset[27][10] $abc$24881$new_n6108 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][10] regset[26][10] $abc$24881$new_n6109 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[10] SET_USER_PC.r_upc[10] $abc$24881$new_n6110 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6112 r_op_Av[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23420 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3815 $abc$24881$new_n6113 $abc$24881$new_n6134 $abc$24881$new_n6112 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names dcd_Acc $abc$24881$new_n6114 SET_TRAP_N_UBREAK.r_trap $abc$24881$new_n6113 +010 1 +011 1 +100 1 +110 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6115 $abc$24881$new_n6127 $abc$24881$new_n6125 $abc$24881$new_n6114 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$24881$new_n6116 $abc$24881$new_n6123 $abc$24881$new_n5637 $abc$24881$new_n6115 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6117 $abc$24881$new_n6119 $abc$24881$new_n6121 $abc$24881$new_n6116 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6118 regset[23][9] regset[19][9] $abc$24881$new_n6117 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][9] regset[18][9] $abc$24881$new_n6118 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6120 regset[21][9] regset[17][9] $abc$24881$new_n6119 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][9] regset[16][9] $abc$24881$new_n6120 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6122 regset[31][9] regset[27][9] $abc$24881$new_n6121 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][9] regset[26][9] $abc$24881$new_n6122 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6124 regset[29][9] regset[25][9] $abc$24881$new_n6123 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][9] regset[24][9] $abc$24881$new_n6124 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6126 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][9] regset[8][9] $abc$24881$new_n6125 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][9] regset[9][9] $abc$24881$new_n6126 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6128 $abc$24881$new_n6130 $abc$24881$new_n6132 $abc$24881$new_n6127 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6129 regset[7][9] regset[6][9] $abc$24881$new_n6128 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[3][9] regset[2][9] $abc$24881$new_n6129 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6131 regset[15][9] regset[11][9] $abc$24881$new_n6130 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][9] regset[10][9] $abc$24881$new_n6131 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6133 regset[5][9] regset[1][9] $abc$24881$new_n6132 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][9] regset[0][9] $abc$24881$new_n6133 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[9] SET_USER_PC.r_upc[9] $abc$24881$new_n6134 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6136 r_op_Av[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23422 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3820 $abc$24881$new_n6137 $abc$24881$new_n6159 $abc$24881$new_n6136 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6138 SET_USER_ILLEGAL_INSN.r_ill_err_u ill_err_i $abc$24881$new_n6137 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n6139 $abc$24881$new_n6149 $abc$24881$new_n6154 $abc$24881$new_n6138 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names $abc$24881$new_n6140 $abc$24881$new_n6147 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6145 $abc$24881$new_n6139 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6141 $abc$24881$new_n6143 $abc$24881$new_n6144 $abc$24881$new_n6140 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6142 regset[15][8] regset[11][8] $abc$24881$new_n6141 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][8] regset[10][8] $abc$24881$new_n6142 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][8] regset[2][8] $abc$24881$new_n6143 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][8] regset[3][8] $abc$24881$new_n6144 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6146 regset[13][8] regset[9][8] $abc$24881$new_n6145 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][8] regset[8][8] $abc$24881$new_n6146 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6148 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[4][8] regset[0][8] $abc$24881$new_n6147 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[5][8] regset[1][8] $abc$24881$new_n6148 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6150 $abc$24881$new_n6152 $abc$24881$new_n6149 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6151 regset[23][8] regset[19][8] $abc$24881$new_n6150 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][8] regset[18][8] $abc$24881$new_n6151 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6153 regset[29][8] regset[25][8] $abc$24881$new_n6152 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][8] regset[24][8] $abc$24881$new_n6153 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6155 $abc$24881$new_n6157 $abc$24881$new_n6154 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6156 regset[31][8] regset[27][8] $abc$24881$new_n6155 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][8] regset[26][8] $abc$24881$new_n6156 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6158 regset[21][8] regset[17][8] $abc$24881$new_n6157 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][8] regset[16][8] $abc$24881$new_n6158 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[8] SET_USER_PC.r_upc[8] $abc$24881$new_n6159 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6161 r_op_Av[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23424 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3825 $abc$24881$new_n6162 $abc$24881$new_n6183 $abc$24881$new_n6161 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6163 SET_TRAP_N_UBREAK.r_ubreak break_en $abc$24881$new_n6162 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n6164 $abc$24881$new_n6174 $abc$24881$new_n6176 $abc$24881$new_n6163 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$24881$new_n6165 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6172 $abc$24881$new_n6164 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6166 $abc$24881$new_n6168 $abc$24881$new_n6170 $abc$24881$new_n6165 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6167 regset[21][7] regset[17][7] $abc$24881$new_n6166 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][7] regset[16][7] $abc$24881$new_n6167 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6169 regset[23][7] regset[22][7] $abc$24881$new_n6168 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[19][7] regset[18][7] $abc$24881$new_n6169 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6171 regset[29][7] regset[25][7] $abc$24881$new_n6170 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][7] regset[24][7] $abc$24881$new_n6171 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6173 regset[31][7] regset[30][7] $abc$24881$new_n6172 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[27][7] regset[26][7] $abc$24881$new_n6173 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6175 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][7] regset[9][7] $abc$24881$new_n6174 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][7] regset[8][7] $abc$24881$new_n6175 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6177 $abc$24881$new_n6179 $abc$24881$new_n6181 $abc$24881$new_n6176 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6178 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][7] regset[2][7] $abc$24881$new_n6177 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[7][7] regset[3][7] $abc$24881$new_n6178 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6180 regset[15][7] regset[11][7] $abc$24881$new_n6179 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][7] regset[10][7] $abc$24881$new_n6180 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6182 regset[4][7] regset[0][7] $abc$24881$new_n6181 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[5][7] regset[1][7] $abc$24881$new_n6182 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[7] SET_USER_PC.r_upc[7] $abc$24881$new_n6183 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6185 r_op_Av[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23426 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3832 $abc$24881$new_n9887 $abc$24881$new_n6209 $abc$24881$new_n6185 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6191 regset[5][6] regset[1][6] $abc$24881$new_n6190 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][6] regset[0][6] $abc$24881$new_n6191 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6193 regset[13][6] regset[9][6] $abc$24881$new_n6192 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][6] regset[8][6] $abc$24881$new_n6193 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6198 regset[15][6] regset[11][6] $abc$24881$new_n6197 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][6] regset[10][6] $abc$24881$new_n6198 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6200 $abc$24881$new_n6207 $abc$24881$new_n5637 $abc$24881$new_n6199 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6201 $abc$24881$new_n6203 $abc$24881$new_n6205 $abc$24881$new_n6200 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6202 regset[31][6] regset[27][6] $abc$24881$new_n6201 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][6] regset[26][6] $abc$24881$new_n6202 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6204 regset[23][6] regset[19][6] $abc$24881$new_n6203 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][6] regset[18][6] $abc$24881$new_n6204 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6206 regset[21][6] regset[17][6] $abc$24881$new_n6205 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][6] regset[16][6] $abc$24881$new_n6206 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6208 regset[29][6] regset[25][6] $abc$24881$new_n6207 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][6] regset[24][6] $abc$24881$new_n6208 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[6] SET_USER_PC.r_upc[6] $abc$24881$new_n6209 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6214 $abc$24881$new_n5637 $abc$24881$new_n6222 $abc$24881$new_n6221 $abc$24881$new_n6213 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6215 $abc$24881$new_n6217 $abc$24881$new_n6219 $abc$24881$new_n6214 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6216 regset[31][5] regset[27][5] $abc$24881$new_n6215 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][5] regset[26][5] $abc$24881$new_n6216 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6218 regset[23][5] regset[19][5] $abc$24881$new_n6217 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][5] regset[18][5] $abc$24881$new_n6218 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6220 regset[21][5] regset[17][5] $abc$24881$new_n6219 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][5] regset[16][5] $abc$24881$new_n6220 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][5] regset[25][5] $abc$24881$new_n6221 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][5] regset[24][5] $abc$24881$new_n6222 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$24881$new_n6224 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6231 $abc$24881$new_n6223 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6225 $abc$24881$new_n6227 $abc$24881$new_n6229 $abc$24881$new_n6224 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6226 regset[12][5] regset[8][5] $abc$24881$new_n6225 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[13][5] regset[9][5] $abc$24881$new_n6226 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6228 regset[15][5] regset[11][5] $abc$24881$new_n6227 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][5] regset[10][5] $abc$24881$new_n6228 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6230 regset[5][5] regset[1][5] $abc$24881$new_n6229 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][5] regset[0][5] $abc$24881$new_n6230 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6232 regset[7][5] regset[3][5] $abc$24881$new_n6231 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][5] regset[2][5] $abc$24881$new_n6232 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6235 r_op_Av[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23430 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3843 $abc$24881$new_n9635 $abc$24881$new_n6258 $abc$24881$new_n6235 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6240 regset[21][4] regset[17][4] $abc$24881$new_n6239 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][4] regset[16][4] $abc$24881$new_n6240 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6242 regset[29][4] regset[25][4] $abc$24881$new_n6241 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][4] regset[24][4] $abc$24881$new_n6242 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6244 $abc$24881$new_n6246 $abc$24881$new_n6243 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6245 regset[31][4] regset[27][4] $abc$24881$new_n6244 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][4] regset[26][4] $abc$24881$new_n6245 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6247 regset[23][4] regset[19][4] $abc$24881$new_n6246 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][4] regset[18][4] $abc$24881$new_n6247 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6250 regset[15][4] regset[11][4] $abc$24881$new_n6249 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][4] regset[10][4] $abc$24881$new_n6250 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6254 $abc$24881$new_n6252 $abc$24881$new_n6256 $abc$24881$new_n6251 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6253 regset[13][4] regset[9][4] $abc$24881$new_n6252 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][4] regset[8][4] $abc$24881$new_n6253 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6255 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[4][4] regset[0][4] $abc$24881$new_n6254 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[5][4] regset[1][4] $abc$24881$new_n6255 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6257 regset[6][4] regset[2][4] $abc$24881$new_n6256 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[7][4] regset[3][4] $abc$24881$new_n6257 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[4] SET_USER_PC.r_upc[4] $abc$24881$new_n6258 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6260 r_op_Av[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23432 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3848 $abc$24881$new_n9639 $abc$24881$new_n6285 $abc$24881$new_n6260 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6265 regset[21][3] regset[20][3] $abc$24881$new_n6264 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[17][3] regset[16][3] $abc$24881$new_n6265 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6267 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][3] regset[25][3] $abc$24881$new_n6266 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][3] regset[24][3] $abc$24881$new_n6267 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6270 regset[23][3] regset[22][3] $abc$24881$new_n6269 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[19][3] regset[18][3] $abc$24881$new_n6270 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6273 regset[31][3] regset[27][3] $abc$24881$new_n6272 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][3] regset[26][3] $abc$24881$new_n6273 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6276 $abc$24881$new_n6278 $abc$24881$new_n6275 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6277 regset[13][3] regset[9][3] $abc$24881$new_n6276 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][3] regset[8][3] $abc$24881$new_n6277 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6279 regset[7][3] regset[3][3] $abc$24881$new_n6278 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][3] regset[2][3] $abc$24881$new_n6279 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6281 regset[5][3] regset[1][3] $abc$24881$new_n6280 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][3] regset[0][3] $abc$24881$new_n6281 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6283 regset[15][3] regset[11][3] $abc$24881$new_n6282 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][3] regset[10][3] $abc$24881$new_n6283 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[3] SET_USER_PC.r_upc[3] $abc$24881$new_n6285 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6292 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][2] regset[25][2] $abc$24881$new_n6291 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][2] regset[24][2] $abc$24881$new_n6292 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6295 regset[31][2] regset[27][2] $abc$24881$new_n6294 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][2] regset[26][2] $abc$24881$new_n6295 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6298 regset[23][2] regset[22][2] $abc$24881$new_n6297 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[19][2] regset[18][2] $abc$24881$new_n6298 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6301 regset[21][2] regset[20][2] $abc$24881$new_n6300 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[17][2] regset[16][2] $abc$24881$new_n6301 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6304 $abc$24881$new_n6306 $abc$24881$new_n6303 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6305 regset[13][2] regset[9][2] $abc$24881$new_n6304 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][2] regset[8][2] $abc$24881$new_n6305 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6307 regset[7][2] regset[3][2] $abc$24881$new_n6306 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][2] regset[2][2] $abc$24881$new_n6307 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6309 regset[5][2] regset[1][2] $abc$24881$new_n6308 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][2] regset[0][2] $abc$24881$new_n6309 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6311 regset[15][2] regset[11][2] $abc$24881$new_n6310 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][2] regset[10][2] $abc$24881$new_n6311 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6318 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][1] regset[25][1] $abc$24881$new_n6317 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][1] regset[24][1] $abc$24881$new_n6318 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6321 regset[31][1] regset[27][1] $abc$24881$new_n6320 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][1] regset[26][1] $abc$24881$new_n6321 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6324 regset[23][1] regset[22][1] $abc$24881$new_n6323 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[19][1] regset[18][1] $abc$24881$new_n6324 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6327 regset[21][1] regset[20][1] $abc$24881$new_n6326 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[17][1] regset[16][1] $abc$24881$new_n6327 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6329 $abc$24881$new_n6334 $abc$24881$new_n6336 $abc$24881$new_n6328 +00100 1 +00101 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6330 $abc$24881$new_n6332 $abc$24881$new_n6329 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6331 regset[7][1] regset[3][1] $abc$24881$new_n6330 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][1] regset[2][1] $abc$24881$new_n6331 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6333 regset[13][1] regset[9][1] $abc$24881$new_n6332 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][1] regset[8][1] $abc$24881$new_n6333 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6335 regset[5][1] regset[1][1] $abc$24881$new_n6334 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][1] regset[0][1] $abc$24881$new_n6335 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6337 regset[15][1] regset[11][1] $abc$24881$new_n6336 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][1] regset[10][1] $abc$24881$new_n6337 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5672 $abc$24881$new_n3859 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4071 $abc$24881$new_n6338 +0000 1 +0001 1 +0010 1 +0011 1 +1010 1 +1110 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6345 $abc$24881$new_n6347 $abc$24881$new_n6349 $abc$24881$new_n6344 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6346 regset[7][0] regset[3][0] $abc$24881$new_n6345 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][0] regset[2][0] $abc$24881$new_n6346 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6348 regset[13][0] regset[9][0] $abc$24881$new_n6347 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][0] regset[8][0] $abc$24881$new_n6348 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6350 regset[15][0] regset[11][0] $abc$24881$new_n6349 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][0] regset[10][0] $abc$24881$new_n6350 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6352 regset[5][0] regset[1][0] $abc$24881$new_n6351 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][0] regset[0][0] $abc$24881$new_n6352 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6355 $abc$24881$new_n6357 $abc$24881$new_n6359 $abc$24881$new_n6354 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6356 regset[31][0] regset[27][0] $abc$24881$new_n6355 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][0] regset[26][0] $abc$24881$new_n6356 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6358 regset[29][0] regset[25][0] $abc$24881$new_n6357 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][0] regset[24][0] $abc$24881$new_n6358 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6360 regset[23][0] regset[22][0] $abc$24881$new_n6359 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] regset[19][0] regset[18][0] $abc$24881$new_n6360 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6362 regset[21][0] regset[17][0] $abc$24881$new_n6361 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][0] regset[16][0] $abc$24881$new_n6362 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4028 $abc$24881$new_n6364 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23440 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[30] $abc$24881$new_n6365 $abc$24881$new_n4280 $abc$24881$new_n6364 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n6382 i_pf_instruction[17] i_pf_instruction_pc[29] i_pf_instruction_pc[28] $abc$24881$new_n6366 $abc$24881$new_n6365 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names i_pf_instruction[17] i_pf_instruction_pc[27] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n6366 +0110 1 +1000 1 +.names $abc$24881$new_n6380 i_pf_instruction[17] $abc$24881$new_n6368 $abc$24881$new_n6367 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n6379 i_pf_instruction[17] i_pf_instruction_pc[21] i_pf_instruction_pc[20] $abc$24881$new_n6369 $abc$24881$new_n6368 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names i_pf_instruction_pc[18] i_pf_instruction_pc[19] i_pf_instruction[17] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6369 +00100 1 +00110 1 +00111 1 +11010 1 +.names i_pf_instruction[15] i_pf_instruction_pc[15] i_pf_instruction[16] i_pf_instruction_pc[16] $abc$24881$new_n6371 $abc$24881$new_n6370 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_pf_instruction_pc[13] i_pf_instruction[13] i_pf_instruction_pc[14] i_pf_instruction[14] $abc$24881$new_n6372 $abc$24881$new_n6371 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_pf_instruction_pc[11] i_pf_instruction[11] i_pf_instruction_pc[12] i_pf_instruction[12] $abc$24881$new_n6373 $abc$24881$new_n6372 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_pf_instruction_pc[9] i_pf_instruction[9] i_pf_instruction_pc[10] i_pf_instruction[10] $abc$24881$new_n6374 $abc$24881$new_n6373 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_pf_instruction_pc[8] i_pf_instruction[8] $abc$24881$new_n6375 $abc$24881$new_n6374 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n6376 i_pf_instruction_pc[7] i_pf_instruction[7] i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6375 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names i_pf_instruction_pc[5] i_pf_instruction[5] i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6377 $abc$24881$new_n6376 +01010 1 +01100 1 +10010 1 +10100 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[4] i_pf_instruction[4] $abc$24881$new_n6378 $abc$24881$new_n6377 +000 1 +001 1 +011 1 +101 1 +.names i_pf_instruction[2] i_pf_instruction_pc[2] i_pf_instruction_pc[3] i_pf_instruction[3] $abc$24881$new_n6378 +0000 1 +0001 1 +0010 1 +0100 1 +1000 1 +1100 1 +.names i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[19] $abc$24881$new_n6379 +000 1 +001 1 +010 1 +011 1 +100 1 +.names i_pf_instruction[17] i_pf_instruction_pc[25] i_pf_instruction_pc[24] i_pf_instruction_pc[23] i_pf_instruction_pc[22] $abc$24881$new_n6380 +01111 1 +10000 1 +.names i_pf_instruction[17] i_pf_instruction_pc[26] i_pf_instruction_pc[27] $abc$24881$new_n6382 +000 1 +001 1 +010 1 +011 1 +100 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n6387 $abc$24881$new_n4279 $abc$24881$auto$rtlil.cc:2693:MuxGate$23444 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[17] i_pf_instruction_pc[28] $abc$24881$new_n6382 $abc$24881$new_n6366 $abc$24881$new_n6387 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n6389 $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$23446 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[27] i_pf_instruction[17] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n6389 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$24881$new_n4028 $abc$24881$new_n6391 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23448 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n4265 $abc$24881$new_n6391 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n6393 $abc$24881$new_n4264 $abc$24881$auto$rtlil.cc:2693:MuxGate$23450 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[25] i_pf_instruction[17] i_pf_instruction_pc[24] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n6393 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11001 1 +.names i_pf_instruction[17] i_pf_instruction_pc[22] $abc$24881$new_n6368 $abc$24881$new_n6394 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n6396 $abc$24881$new_n4267 $abc$24881$auto$rtlil.cc:2693:MuxGate$23452 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[17] i_pf_instruction_pc[24] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n6396 +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 $abc$24881$new_n6398 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23454 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n4273 $abc$24881$new_n6398 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4028 $abc$24881$new_n6400 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23456 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[22] $abc$24881$new_n6368 $abc$24881$new_n4287 $abc$24881$new_n6400 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] $abc$24881$new_n6402 $abc$24881$new_n4289 $abc$24881$auto$rtlil.cc:2693:MuxGate$23458 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[21] i_pf_instruction[17] i_pf_instruction_pc[20] $abc$24881$new_n6379 $abc$24881$new_n6369 $abc$24881$new_n6402 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10111 1 +11010 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] $abc$24881$new_n6404 $abc$24881$new_n4291 $abc$24881$auto$rtlil.cc:2693:MuxGate$23460 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[17] i_pf_instruction_pc[20] $abc$24881$new_n6379 $abc$24881$new_n6369 $abc$24881$new_n6404 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] $abc$24881$new_n6406 $abc$24881$new_n4293 $abc$24881$auto$rtlil.cc:2693:MuxGate$23462 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[19] i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6406 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11001 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] $abc$24881$new_n6408 $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$23464 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6408 +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n6410 $abc$24881$auto$rtlil.cc:2693:MuxGate$23466 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n5442 $abc$24881$new_n6410 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n6412 $abc$24881$new_n5455 $abc$24881$auto$rtlil.cc:2693:MuxGate$23468 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[16] i_pf_instruction_pc[16] i_pf_instruction[15] i_pf_instruction_pc[15] $abc$24881$new_n6371 $abc$24881$new_n6412 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] $abc$24881$new_n6414 $abc$24881$auto$rtlil.cc:2693:MuxGate$23470 +001 1 +011 1 +110 1 +111 1 +.names i_pf_instruction[15] i_pf_instruction_pc[15] $abc$24881$new_n6371 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6414 +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n6416 i_pf_instruction[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23472 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[14] i_pf_instruction[14] i_pf_instruction_pc[13] i_pf_instruction[13] $abc$24881$new_n6372 $abc$24881$new_n6416 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n6418 $abc$24881$auto$rtlil.cc:2693:MuxGate$23474 +001 1 +011 1 +110 1 +111 1 +.names i_pf_instruction[13] i_pf_instruction_pc[13] $abc$24881$new_n6372 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6418 +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n6420 i_pf_instruction[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23476 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[12] i_pf_instruction[12] i_pf_instruction_pc[11] i_pf_instruction[11] $abc$24881$new_n6373 $abc$24881$new_n6420 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] $abc$24881$new_n6422 $abc$24881$auto$rtlil.cc:2693:MuxGate$23478 +000 1 +010 1 +110 1 +111 1 +.names i_pf_instruction[11] i_pf_instruction_pc[11] $abc$24881$new_n6373 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6422 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] $abc$24881$new_n6424 i_pf_instruction[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23480 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[10] i_pf_instruction[10] i_pf_instruction_pc[9] i_pf_instruction[9] $abc$24881$new_n6374 $abc$24881$new_n6424 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n6426 $abc$24881$auto$rtlil.cc:2693:MuxGate$23482 +000 1 +010 1 +110 1 +111 1 +.names i_pf_instruction[9] i_pf_instruction_pc[9] $abc$24881$new_n6374 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6426 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] $abc$24881$new_n6428 $abc$24881$auto$rtlil.cc:2693:MuxGate$23484 +000 1 +010 1 +110 1 +111 1 +.names i_pf_instruction[8] i_pf_instruction_pc[8] $abc$24881$new_n6375 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6428 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1110 1 +.names $abc$24881$new_n4028 i_pf_instruction[7] $abc$24881$new_n6430 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23486 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names i_pf_instruction_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6376 i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6430 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n6432 i_pf_instruction[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23488 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[6] i_pf_instruction[6] i_pf_instruction_pc[5] i_pf_instruction[5] $abc$24881$new_n6377 $abc$24881$new_n6432 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 i_pf_instruction[5] $abc$24881$new_n6434 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23490 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names i_pf_instruction_pc[5] $abc$24881$new_n6377 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6434 +000 1 +110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] $abc$24881$new_n6436 i_pf_instruction[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23492 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[4] i_pf_instruction[4] $abc$24881$new_n6378 $abc$24881$new_n6436 +000 1 +011 1 +101 1 +110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] $abc$24881$new_n6438 $abc$24881$auto$rtlil.cc:2693:MuxGate$23494 +000 1 +010 1 +110 1 +111 1 +.names i_pf_instruction[3] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6438 +00000 1 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +11000 1 +.names $abc$24881$new_n4028 i_pf_instruction[2] i_pf_instruction_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23496 +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[30] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6441 $abc$24881$new_n6459 $abc$24881$auto$rtlil.cc:2693:MuxGate$23498 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_pc[27] instruction_decoder.o_pc[28] instruction_decoder.o_pc[29] $abc$24881$new_n6442 $abc$24881$new_n6441 +1111 1 +.names instruction_decoder.o_pc[23] instruction_decoder.o_pc[24] instruction_decoder.o_pc[25] instruction_decoder.o_pc[26] $abc$24881$new_n6443 $abc$24881$new_n6442 +11111 1 +.names instruction_decoder.o_pc[20] instruction_decoder.o_pc[21] instruction_decoder.o_pc[22] $abc$24881$new_n6444 $abc$24881$new_n6443 +1111 1 +.names instruction_decoder.o_pc[18] instruction_decoder.o_pc[19] $abc$24881$new_n6445 $abc$24881$new_n6444 +111 1 +.names instruction_decoder.o_pc[17] $abc$24881$new_n6446 $abc$24881$new_n6445 +11 1 +.names instruction_decoder.o_pc[16] $abc$24881$new_n6447 $abc$24881$new_n6446 +11 1 +.names instruction_decoder.o_pc[15] $abc$24881$new_n6448 $abc$24881$new_n6447 +11 1 +.names instruction_decoder.o_pc[14] $abc$24881$new_n6449 $abc$24881$new_n6448 +11 1 +.names instruction_decoder.o_pc[13] $abc$24881$new_n6450 $abc$24881$new_n6449 +11 1 +.names instruction_decoder.o_pc[12] $abc$24881$new_n6451 $abc$24881$new_n6450 +11 1 +.names instruction_decoder.o_pc[11] $abc$24881$new_n6452 $abc$24881$new_n6451 +11 1 +.names instruction_decoder.o_pc[10] $abc$24881$new_n6453 $abc$24881$new_n6452 +11 1 +.names instruction_decoder.o_pc[9] $abc$24881$new_n6454 $abc$24881$new_n6453 +11 1 +.names instruction_decoder.o_pc[8] $abc$24881$new_n6455 $abc$24881$new_n6454 +11 1 +.names instruction_decoder.o_pc[6] instruction_decoder.o_pc[7] $abc$24881$new_n6456 $abc$24881$new_n6455 +111 1 +.names instruction_decoder.o_pc[5] $abc$24881$new_n6457 $abc$24881$new_n6456 +11 1 +.names instruction_decoder.o_pc[4] $abc$24881$new_n6458 $abc$24881$new_n6457 +11 1 +.names instruction_decoder.o_pc[1] instruction_decoder.o_pc[2] instruction_decoder.o_pc[3] $abc$24881$new_n6458 +111 1 +.names i_pf_instruction_pc[30] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6460 i_pf_instruction[31] $abc$24881$new_n6459 +0010 1 +1000 1 +1001 1 +1011 1 +.names i_pf_instruction_pc[29] $abc$24881$new_n6461 $abc$24881$new_n6460 +11 1 +.names i_pf_instruction_pc[28] $abc$24881$new_n6462 $abc$24881$new_n6461 +11 1 +.names i_pf_instruction_pc[27] i_pf_instruction_pc[26] $abc$24881$new_n6463 $abc$24881$new_n6462 +111 1 +.names i_pf_instruction_pc[25] i_pf_instruction_pc[24] $abc$24881$new_n6464 $abc$24881$new_n6463 +111 1 +.names i_pf_instruction_pc[23] i_pf_instruction_pc[22] i_pf_instruction_pc[21] $abc$24881$new_n6465 $abc$24881$new_n6464 +1111 1 +.names i_pf_instruction_pc[20] i_pf_instruction_pc[19] i_pf_instruction_pc[18] $abc$24881$new_n6466 $abc$24881$new_n6465 +1111 1 +.names i_pf_instruction_pc[17] $abc$24881$new_n6467 $abc$24881$new_n6466 +11 1 +.names i_pf_instruction_pc[16] $abc$24881$new_n6468 $abc$24881$new_n6467 +11 1 +.names i_pf_instruction_pc[15] $abc$24881$new_n6469 $abc$24881$new_n6468 +11 1 +.names i_pf_instruction_pc[14] $abc$24881$new_n6470 $abc$24881$new_n6469 +11 1 +.names i_pf_instruction_pc[13] $abc$24881$new_n6471 $abc$24881$new_n6470 +11 1 +.names i_pf_instruction_pc[12] $abc$24881$new_n6472 $abc$24881$new_n6471 +11 1 +.names i_pf_instruction_pc[11] i_pf_instruction_pc[10] $abc$24881$new_n6473 $abc$24881$new_n6472 +111 1 +.names i_pf_instruction_pc[9] i_pf_instruction_pc[8] i_pf_instruction_pc[7] $abc$24881$new_n6474 $abc$24881$new_n6473 +1111 1 +.names i_pf_instruction_pc[6] i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] $abc$24881$new_n6474 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_valid $abc$24881$new_n6475 +001 1 +010 1 +011 1 +.names $abc$24881$new_n6475 $abc$24881$new_n6477 instruction_decoder.o_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23500 +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n6478 i_pf_instruction_pc[29] $abc$24881$new_n6461 i_pf_instruction[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6477 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.o_pc[29] instruction_decoder.o_pc[27] instruction_decoder.o_pc[28] $abc$24881$new_n6442 $abc$24881$new_n6478 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[28] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6480 $abc$24881$new_n6481 $abc$24881$auto$rtlil.cc:2693:MuxGate$23502 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[27] $abc$24881$new_n6442 $abc$24881$new_n6480 +11 1 +.names i_pf_instruction_pc[28] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6462 i_pf_instruction[31] $abc$24881$new_n6481 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[27] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6442 $abc$24881$new_n6483 $abc$24881$auto$rtlil.cc:2693:MuxGate$23504 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names i_pf_instruction_pc[27] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[26] $abc$24881$new_n6463 i_pf_instruction[31] $abc$24881$new_n6483 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[26] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6485 $abc$24881$new_n6488 $abc$24881$auto$rtlil.cc:2693:MuxGate$23506 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[25] $abc$24881$new_n6486 $abc$24881$new_n6485 +11 1 +.names instruction_decoder.o_pc[24] $abc$24881$new_n6487 $abc$24881$new_n6486 +11 1 +.names instruction_decoder.o_pc[23] $abc$24881$new_n6443 $abc$24881$new_n6487 +11 1 +.names i_pf_instruction_pc[26] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6463 i_pf_instruction[31] $abc$24881$new_n6488 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[25] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6486 $abc$24881$new_n6490 $abc$24881$auto$rtlil.cc:2693:MuxGate$23508 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names i_pf_instruction_pc[25] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[24] $abc$24881$new_n6464 i_pf_instruction[31] $abc$24881$new_n6490 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6487 $abc$24881$new_n6492 $abc$24881$auto$rtlil.cc:2693:MuxGate$23510 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6464 i_pf_instruction[31] $abc$24881$new_n6492 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[23] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6443 $abc$24881$new_n6494 $abc$24881$auto$rtlil.cc:2693:MuxGate$23512 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[23] $abc$24881$new_n6495 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6494 +010 1 +100 1 +.names i_pf_instruction_pc[22] i_pf_instruction_pc[21] $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6495 +1110 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[22] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6497 $abc$24881$new_n6499 $abc$24881$auto$rtlil.cc:2693:MuxGate$23514 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[21] $abc$24881$new_n6498 $abc$24881$new_n6497 +11 1 +.names instruction_decoder.o_pc[20] $abc$24881$new_n6444 $abc$24881$new_n6498 +11 1 +.names i_pf_instruction_pc[22] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[21] $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6499 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[21] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6498 $abc$24881$new_n6501 $abc$24881$auto$rtlil.cc:2693:MuxGate$23516 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[21] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6501 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[20] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6444 $abc$24881$new_n6503 $abc$24881$auto$rtlil.cc:2693:MuxGate$23518 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[20] $abc$24881$new_n6504 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6503 +010 1 +100 1 +.names i_pf_instruction_pc[19] i_pf_instruction_pc[18] $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6504 +1110 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[19] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6506 $abc$24881$new_n6507 $abc$24881$auto$rtlil.cc:2693:MuxGate$23520 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[18] $abc$24881$new_n6445 $abc$24881$new_n6506 +11 1 +.names i_pf_instruction_pc[19] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[18] $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6507 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[18] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6445 $abc$24881$new_n6509 $abc$24881$auto$rtlil.cc:2693:MuxGate$23522 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[18] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6509 +0010 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[17] $abc$24881$new_n6446 $abc$24881$new_n6511 $abc$24881$auto$rtlil.cc:2693:MuxGate$23524 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[17] $abc$24881$new_n6467 i_pf_instruction[31] $abc$24881$new_n6511 +000 1 +001 1 +011 1 +110 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[16] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6447 $abc$24881$new_n6513 $abc$24881$auto$rtlil.cc:2693:MuxGate$23526 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[16] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6468 i_pf_instruction[31] $abc$24881$new_n6513 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[15] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6448 $abc$24881$new_n6515 $abc$24881$auto$rtlil.cc:2693:MuxGate$23528 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[15] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6469 i_pf_instruction[31] $abc$24881$new_n6515 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[14] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6449 $abc$24881$new_n6517 $abc$24881$auto$rtlil.cc:2693:MuxGate$23530 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[14] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6470 i_pf_instruction[31] $abc$24881$new_n6517 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[13] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6450 $abc$24881$new_n6519 $abc$24881$auto$rtlil.cc:2693:MuxGate$23532 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[13] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6471 i_pf_instruction[31] $abc$24881$new_n6519 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[12] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6451 $abc$24881$new_n6521 $abc$24881$auto$rtlil.cc:2693:MuxGate$23534 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[12] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6472 i_pf_instruction[31] $abc$24881$new_n6521 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[11] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6452 $abc$24881$new_n6523 $abc$24881$auto$rtlil.cc:2693:MuxGate$23536 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[11] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[10] $abc$24881$new_n6473 i_pf_instruction[31] $abc$24881$new_n6523 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[10] $abc$24881$new_n6453 $abc$24881$new_n6525 $abc$24881$auto$rtlil.cc:2693:MuxGate$23538 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[10] $abc$24881$new_n6473 i_pf_instruction[31] $abc$24881$new_n6525 +010 1 +100 1 +101 1 +111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[9] $abc$24881$new_n6454 $abc$24881$new_n6527 $abc$24881$auto$rtlil.cc:2693:MuxGate$23540 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[9] i_pf_instruction_pc[8] i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6527 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6528 +11110 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[8] $abc$24881$new_n6455 $abc$24881$new_n6530 $abc$24881$auto$rtlil.cc:2693:MuxGate$23542 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[8] i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6530 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[7] $abc$24881$new_n6532 $abc$24881$new_n6533 $abc$24881$auto$rtlil.cc:2693:MuxGate$23544 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_pc[6] $abc$24881$new_n6456 $abc$24881$new_n6532 +11 1 +.names i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6533 +011 1 +100 1 +101 1 +110 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[6] $abc$24881$new_n6456 $abc$24881$new_n6535 $abc$24881$auto$rtlil.cc:2693:MuxGate$23546 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6535 +01 1 +10 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[5] $abc$24881$new_n6457 $abc$24881$new_n6537 $abc$24881$auto$rtlil.cc:2693:MuxGate$23548 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6537 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[4] $abc$24881$new_n6458 $abc$24881$new_n6539 $abc$24881$auto$rtlil.cc:2693:MuxGate$23550 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6539 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[3] $abc$24881$new_n6541 $abc$24881$new_n6542 $abc$24881$auto$rtlil.cc:2693:MuxGate$23552 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_pc[1] instruction_decoder.o_pc[2] $abc$24881$new_n6541 +11 1 +.names i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6542 +010 1 +100 1 +101 1 +111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[2] instruction_decoder.o_pc[1] $abc$24881$new_n6544 $abc$24881$auto$rtlil.cc:2693:MuxGate$23554 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6544 +00 1 +11 1 +.names $abc$24881$new_n6546 $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[31] $abc$24881$new_n6568 $abc$24881$auto$rtlil.cc:2693:MuxGate$23556 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11010 1 +11011 1 +.names $abc$24881$new_n9657 $abc$24881$new_n4071 $abc$24881$new_n5672 instruction_decoder.o_pc[31] SET_USER_PC.r_upc[31] $abc$24881$new_n6546 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6550 $abc$24881$new_n6552 $abc$24881$new_n6554 $abc$24881$new_n6549 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6551 regset[15][31] regset[11][31] $abc$24881$new_n6550 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][31] regset[10][31] $abc$24881$new_n6551 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6553 regset[7][31] regset[3][31] $abc$24881$new_n6552 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][31] regset[2][31] $abc$24881$new_n6553 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6555 regset[5][31] regset[1][31] $abc$24881$new_n6554 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][31] regset[0][31] $abc$24881$new_n6555 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6557 regset[13][31] regset[9][31] $abc$24881$new_n6556 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][31] regset[8][31] $abc$24881$new_n6557 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6559 $abc$24881$new_n6561 $abc$24881$new_n6563 $abc$24881$new_n6558 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6560 regset[23][31] regset[19][31] $abc$24881$new_n6559 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][31] regset[18][31] $abc$24881$new_n6560 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6562 regset[31][31] regset[27][31] $abc$24881$new_n6561 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][31] regset[26][31] $abc$24881$new_n6562 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6564 regset[21][31] regset[20][31] $abc$24881$new_n6563 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] regset[17][31] regset[16][31] $abc$24881$new_n6564 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6567 regset[29][31] regset[25][31] $abc$24881$new_n6566 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][31] regset[24][31] $abc$24881$new_n6567 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6569 i_mem_result[31] wr_index[0] wr_index[1] $abc$24881$new_n6568 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.w_n doalu.n dbg_val[31] $abc$24881$new_n6569 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6576 $abc$24881$new_n5065 $abc$24881$new_n6577 $abc$24881$new_n6571 $abc$24881$new_n6572 $abc$24881$auto$rtlil.cc:2693:MuxGate$23558 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_I[31] $abc$24881$new_n5090 $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n6571 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n6575 $abc$24881$new_n6573 $abc$24881$new_n6574 $abc$24881$new_n6572 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names dcd_I[31] $abc$24881$new_n5148 $abc$24881$new_n5147 $abc$24881$new_n5149 $abc$24881$new_n5113 $abc$24881$new_n6573 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n6568 $abc$24881$new_n6574 +10 1 +.names dcd_I[31] $abc$24881$new_n4068 SET_USER_PC.r_upc[31] instruction_decoder.o_pc[31] $abc$24881$new_n6575 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names r_op_Bv[31] $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n6576 +100 1 +.names dcd_I[31] $abc$24881$new_n6568 $abc$24881$new_n4373 $abc$24881$new_n4368 $abc$24881$new_n6578 $abc$24881$new_n6577 +00000 1 +00001 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n6579 $abc$24881$new_n6589 $abc$24881$new_n6596 $abc$24881$new_n6578 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$24881$new_n6580 $abc$24881$new_n6587 $abc$24881$new_n4069 $abc$24881$new_n6579 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n6581 $abc$24881$new_n6583 $abc$24881$new_n6585 $abc$24881$new_n6580 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6582 regset[7][31] regset[3][31] $abc$24881$new_n6581 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][31] regset[2][31] $abc$24881$new_n6582 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6584 regset[5][31] regset[1][31] $abc$24881$new_n6583 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][31] regset[0][31] $abc$24881$new_n6584 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6586 regset[13][31] regset[12][31] $abc$24881$new_n6585 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[9][31] regset[8][31] $abc$24881$new_n6586 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6588 regset[15][31] regset[14][31] $abc$24881$new_n6587 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[11][31] regset[10][31] $abc$24881$new_n6588 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n6590 $abc$24881$new_n6592 $abc$24881$new_n6594 $abc$24881$new_n6589 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6591 regset[29][31] regset[25][31] $abc$24881$new_n6590 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][31] regset[24][31] $abc$24881$new_n6591 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6593 regset[31][31] regset[27][31] $abc$24881$new_n6592 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][31] regset[26][31] $abc$24881$new_n6593 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6595 regset[21][31] regset[20][31] $abc$24881$new_n6594 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][31] regset[16][31] $abc$24881$new_n6595 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6597 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][31] regset[18][31] $abc$24881$new_n6596 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][31] regset[19][31] $abc$24881$new_n6597 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[6] r_op_F[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23560 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n6600 op_wF $abc$24881$auto$rtlil.cc:2693:MuxGate$23562 +001 1 +011 1 +110 1 +111 1 +.names dcd_wF instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_wR dcd_Acc $abc$24881$new_n6600 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n5364 OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5066 $abc$24881$auto$rtlil.cc:2693:MuxGate$23564 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n5066 OP_REG_ADVANEC.r_op_rA dcd_rA instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23566 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[4] OP_REG_ADVANEC.r_op_Bid[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23568 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[4] o_mem_reg[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23570 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 GEN_OP_WR.r_op_wR dcd_wR instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23572 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$24881$new_n5066 FWD_OPERATION.r_op_opn[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[3] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23576 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[4] i_dbg_wreg[4] alu_reg[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23578 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.o_pc[1] i_pf_instruction[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23582 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4028 dcd_I[31] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n6610 $abc$24881$auto$rtlil.cc:2693:MuxGate$23584 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4287 $abc$24881$new_n6610 +100 1 +101 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[14] i_pf_instruction[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23586 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 dcd_rB $abc$24881$new_n4258 $abc$24881$auto$rtlil.cc:2693:MuxGate$23588 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n6614 $abc$24881$new_n4028 dcd_rA $abc$24881$auto$rtlil.cc:2693:MuxGate$23590 +000 1 +001 1 +011 1 +.names $abc$24881$new_n6620 $abc$24881$new_n6615 $abc$24881$new_n6617 $abc$24881$new_n6616 $abc$24881$new_n6614 +1100 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4269 $abc$24881$new_n4261 $abc$24881$new_n4270 $abc$24881$new_n6615 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$24881$new_n4260 $abc$24881$new_n4282 $abc$24881$new_n6616 +10 1 +.names $abc$24881$new_n6618 $abc$24881$new_n4281 $abc$24881$new_n6619 $abc$24881$new_n4267 $abc$24881$new_n6617 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4268 $abc$24881$new_n4267 $abc$24881$new_n6618 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_pf_instruction[25] $abc$24881$new_n4266 $abc$24881$new_n4282 $abc$24881$new_n4268 $abc$24881$new_n6619 +1111 1 +.names $abc$24881$new_n6622 $abc$24881$new_n6621 $abc$24881$new_n6620 +00 1 +.names $abc$24881$new_n4276 $abc$24881$new_n4277 $abc$24881$new_n4273 $abc$24881$new_n4267 $abc$24881$new_n6621 +1000 1 +1001 1 +1010 1 +.names i_pf_instruction[25] $abc$24881$new_n4265 $abc$24881$new_n4266 $abc$24881$new_n4267 $abc$24881$new_n4273 $abc$24881$new_n6622 +11100 1 +.names $abc$24881$new_n4028 dcd_wR $abc$24881$new_n6615 $abc$24881$new_n4275 $abc$24881$new_n6616 $abc$24881$auto$rtlil.cc:2693:MuxGate$23592 +00100 1 +01100 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_lock $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n4287 $abc$24881$auto$rtlil.cc:2693:MuxGate$23594 +00110 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_DV $abc$24881$new_n6622 $abc$24881$auto$rtlil.cc:2693:MuxGate$23596 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 dcd_M $abc$24881$new_n4260 $abc$24881$auto$rtlil.cc:2693:MuxGate$23598 +001 1 +011 1 +110 1 +111 1 +.names dcd_ALU $abc$24881$new_n4028 $abc$24881$new_n6615 $abc$24881$new_n6628 $abc$24881$new_n6618 $abc$24881$auto$rtlil.cc:2693:MuxGate$23600 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n4271 $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n6628 +000 1 +001 1 +011 1 +.names $abc$24881$new_n4028 dcd_opn[3] $abc$24881$new_n4269 $abc$24881$auto$rtlil.cc:2693:MuxGate$23604 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n6615 $abc$24881$new_n4028 dcd_wF $abc$24881$new_n6633 $abc$24881$new_n6631 $abc$24881$auto$rtlil.cc:2693:MuxGate$23606 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4274 $abc$24881$new_n4293 $abc$24881$new_n6632 $abc$24881$new_n6631 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$24881$new_n4289 $abc$24881$new_n4291 $abc$24881$new_n6632 +10 1 +.names $abc$24881$new_n6620 $abc$24881$new_n6634 $abc$24881$new_n6617 $abc$24881$new_n6633 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4277 $abc$24881$new_n4267 $abc$24881$new_n4268 $abc$24881$new_n4269 $abc$24881$new_n6634 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names $abc$24881$new_n6631 dcd_F[3] $abc$24881$new_n4028 $abc$24881$auto$rtlil.cc:2693:MuxGate$23608 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n6637 dcd_zI $abc$24881$new_n4028 $abc$24881$auto$rtlil.cc:2693:MuxGate$23610 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n5459 $abc$24881$new_n6639 $abc$24881$new_n6638 $abc$24881$new_n5438 $abc$24881$new_n6637 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5449 $abc$24881$new_n5447 $abc$24881$new_n5445 $abc$24881$new_n6610 $abc$24881$new_n6638 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$24881$new_n6640 $abc$24881$new_n5457 $abc$24881$new_n5454 $abc$24881$new_n5451 $abc$24881$new_n5461 $abc$24881$new_n6639 +11110 1 +.names $abc$24881$new_n6641 $abc$24881$new_n4266 i_pf_instruction[7] i_pf_instruction[8] $abc$24881$new_n6640 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n6642 $abc$24881$new_n5477 $abc$24881$new_n5474 $abc$24881$new_n5472 $abc$24881$new_n5469 $abc$24881$new_n6641 +11100 1 +.names $abc$24881$new_n6643 $abc$24881$new_n6644 $abc$24881$new_n4266 i_pf_instruction[2] $abc$24881$new_n4283 $abc$24881$new_n6642 +11001 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4266 i_pf_instruction[0] i_pf_instruction[1] $abc$24881$new_n5455 $abc$24881$new_n5442 $abc$24881$new_n6643 +00011 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$24881$new_n4266 i_pf_instruction[11] i_pf_instruction[12] i_pf_instruction[9] i_pf_instruction[10] $abc$24881$new_n6644 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names $abc$24881$new_n4028 dcd_Bcc $abc$24881$new_n4292 $abc$24881$new_n4257 $abc$24881$auto$rtlil.cc:2693:MuxGate$23612 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 dcd_Acc $abc$24881$new_n4302 $abc$24881$new_n4301 $abc$24881$auto$rtlil.cc:2693:MuxGate$23614 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 dcd_break $abc$24881$new_n4273 $abc$24881$new_n4275 $abc$24881$new_n4287 $abc$24881$auto$rtlil.cc:2693:MuxGate$23616 +00111 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names alu_ce $abc$24881$new_n6649 doalu.set_ovfl $abc$24881$new_n6657 $abc$24881$new_n6658 $abc$24881$auto$rtlil.cc:2693:MuxGate$23618 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$24881$new_n6650 $abc$24881$new_n6653 $abc$24881$new_n6655 $abc$24881$new_n6649 +000 1 +010 1 +100 1 +101 1 +.names o_mem_data[31] o_mem_addr[31] $abc$24881$new_n6650 +01 1 +10 1 +.names $abc$24881$new_n5151 $abc$24881$new_n6568 r_op_Bv[31] o_mem_addr[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3692 $abc$24881$new_n6568 r_op_Av[31] o_mem_data[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n6654 DIVIDE.thedivide.i_signed $abc$24881$new_n6653 +10 1 +.names FWD_OPERATION.r_op_opn[3] o_mem_op[1] o_mem_op[2] $abc$24881$new_n6654 +000 1 +.names $abc$24881$new_n6656 DIVIDE.thedivide.i_signed $abc$24881$new_n6655 +10 1 +.names o_mem_op[1] FWD_OPERATION.r_op_opn[3] o_mem_op[2] $abc$24881$new_n6656 +100 1 +.names o_mem_op[2] FWD_OPERATION.r_op_opn[3] o_mem_op[1] DIVIDE.thedivide.i_signed $abc$24881$new_n6657 +1001 1 +1010 1 +1011 1 +.names o_mem_op[2] DIVIDE.thedivide.i_signed o_mem_op[1] FWD_OPERATION.r_op_opn[3] $abc$24881$new_n6658 +1110 1 +.names alu_ce $abc$24881$new_n6649 doalu.keep_sgn_on_ovfl $abc$24881$auto$rtlil.cc:2693:MuxGate$23620 +001 1 +011 1 +100 1 +101 1 +.names o_mem_addr[28] o_mem_data[28] o_mem_addr[29] o_mem_data[29] $abc$24881$new_n6663 $abc$24881$new_n6662 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names o_mem_addr[26] o_mem_data[26] o_mem_addr[27] o_mem_data[27] $abc$24881$new_n6664 $abc$24881$new_n6663 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[24] o_mem_data[24] o_mem_addr[25] o_mem_data[25] $abc$24881$new_n6665 $abc$24881$new_n6664 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[22] o_mem_data[22] o_mem_addr[23] o_mem_data[23] $abc$24881$new_n6666 $abc$24881$new_n6665 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[20] o_mem_data[20] o_mem_addr[21] o_mem_data[21] $abc$24881$new_n6667 $abc$24881$new_n6666 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names o_mem_addr[18] o_mem_data[18] o_mem_addr[19] o_mem_data[19] $abc$24881$new_n6668 $abc$24881$new_n6667 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[16] o_mem_data[16] o_mem_addr[17] o_mem_data[17] $abc$24881$new_n6669 $abc$24881$new_n6668 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names o_mem_addr[14] o_mem_data[14] o_mem_addr[15] o_mem_data[15] $abc$24881$new_n6670 $abc$24881$new_n6669 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[12] o_mem_data[12] o_mem_addr[13] o_mem_data[13] $abc$24881$new_n6671 $abc$24881$new_n6670 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names o_mem_addr[10] o_mem_data[10] o_mem_addr[11] o_mem_data[11] $abc$24881$new_n6672 $abc$24881$new_n6671 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[8] o_mem_data[8] o_mem_addr[9] o_mem_data[9] $abc$24881$new_n6673 $abc$24881$new_n6672 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names o_mem_addr[6] o_mem_data[6] o_mem_addr[7] o_mem_data[7] $abc$24881$new_n6674 $abc$24881$new_n6673 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names o_mem_addr[4] o_mem_data[4] o_mem_addr[5] o_mem_data[5] $abc$24881$new_n9661 $abc$24881$new_n6674 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3692 $abc$24881$new_n3853 r_op_Av[2] r_op_Bv[2] $abc$24881$new_n6678 +00011 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3692 r_op_Av[2] r_op_Bv[2] $abc$24881$new_n3853 $abc$24881$new_n6679 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01011 1 +01100 1 +01111 1 +10000 1 +10010 1 +10101 1 +10111 1 +.names o_mem_addr[0] o_mem_data[0] o_mem_addr[1] o_mem_data[1] $abc$24881$new_n6680 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names o_mem_addr[30] o_mem_data[30] $abc$24881$new_n6682 +11 1 +.names o_mem_addr[30] o_mem_data[30] $abc$24881$new_n6683 +01 1 +10 1 +.names $abc$24881$new_n6723 $abc$24881$new_n6788 $abc$24881$new_n6686 $abc$24881$new_n6650 $abc$24881$new_n6685 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n6722 $abc$24881$new_n6683 $abc$24881$new_n6687 $abc$24881$new_n6686 +000 1 +.names $abc$24881$new_n6721 $abc$24881$new_n6688 o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6720 $abc$24881$new_n6687 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10100 1 +10110 1 +11000 1 +11100 1 +11110 1 +.names $abc$24881$new_n6719 $abc$24881$new_n6689 o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6718 $abc$24881$new_n6688 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10100 1 +10110 1 +11000 1 +11100 1 +11110 1 +.names $abc$24881$new_n6717 $abc$24881$new_n6690 o_mem_addr[24] o_mem_data[24] $abc$24881$new_n6716 $abc$24881$new_n6689 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10100 1 +10110 1 +11000 1 +11100 1 +11110 1 +.names $abc$24881$new_n6714 o_mem_addr[22] $abc$24881$new_n6691 $abc$24881$new_n6715 o_mem_data[22] $abc$24881$new_n6690 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +.names $abc$24881$new_n6711 o_mem_addr[20] $abc$24881$new_n6692 o_mem_data[20] $abc$24881$new_n6713 $abc$24881$new_n6691 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01110 1 +10010 1 +10100 1 +10110 1 +11110 1 +.names o_mem_addr[17] $abc$24881$new_n6693 $abc$24881$new_n6710 o_mem_data[17] $abc$24881$new_n6707 $abc$24881$new_n6692 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10111 1 +11011 1 +11111 1 +.names o_mem_addr[15] $abc$24881$new_n6694 $abc$24881$new_n6706 o_mem_data[15] $abc$24881$new_n6705 $abc$24881$new_n6693 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$24881$new_n6701 $abc$24881$new_n6704 $abc$24881$new_n6695 $abc$24881$new_n6703 $abc$24881$new_n6702 $abc$24881$new_n6694 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names o_mem_data[10] o_mem_addr[10] o_mem_addr[11] o_mem_data[11] $abc$24881$new_n6696 $abc$24881$new_n6695 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names o_mem_addr[8] o_mem_addr[9] o_mem_data[8] o_mem_data[9] $abc$24881$new_n6697 $abc$24881$new_n6696 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[6] o_mem_addr[7] o_mem_data[6] o_mem_data[7] $abc$24881$new_n6698 $abc$24881$new_n6697 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[4] o_mem_addr[5] o_mem_data[4] o_mem_data[5] $abc$24881$new_n6699 $abc$24881$new_n6698 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n6700 o_mem_addr[2] o_mem_data[2] o_mem_data[3] $abc$24881$new_n6699 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_addr[1] o_mem_data[0] o_mem_data[1] $abc$24881$new_n6700 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names o_mem_addr[14] o_mem_data[14] $abc$24881$new_n6701 +00 1 +11 1 +.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6702 +01 1 +10 1 +.names o_mem_addr[13] o_mem_data[13] $abc$24881$new_n6703 +01 1 +10 1 +.names o_mem_data[12] o_mem_addr[12] o_mem_addr[13] o_mem_data[13] $abc$24881$new_n6704 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names o_mem_addr[16] o_mem_data[16] $abc$24881$new_n6705 +01 1 +10 1 +.names o_mem_data[14] o_mem_addr[14] $abc$24881$new_n6706 +10 1 +.names $abc$24881$new_n6709 $abc$24881$new_n6708 $abc$24881$new_n6707 +00 1 +.names o_mem_addr[18] o_mem_data[18] $abc$24881$new_n6708 +01 1 +10 1 +.names o_mem_addr[19] o_mem_data[19] $abc$24881$new_n6709 +01 1 +10 1 +.names o_mem_data[16] o_mem_addr[16] $abc$24881$new_n6710 +10 1 +.names o_mem_addr[19] o_mem_data[19] $abc$24881$new_n6712 $abc$24881$new_n6711 +000 1 +100 1 +101 1 +110 1 +.names o_mem_data[18] o_mem_addr[18] $abc$24881$new_n6712 +10 1 +.names o_mem_addr[21] o_mem_data[21] $abc$24881$new_n6713 +10 1 +.names o_mem_data[23] o_mem_addr[23] $abc$24881$new_n6714 +10 1 +.names o_mem_data[21] o_mem_addr[21] $abc$24881$new_n6715 +10 1 +.names o_mem_data[25] o_mem_addr[25] $abc$24881$new_n6716 +10 1 +.names o_mem_addr[23] o_mem_data[23] $abc$24881$new_n6717 +10 1 +.names o_mem_data[27] o_mem_addr[27] $abc$24881$new_n6718 +10 1 +.names o_mem_addr[25] o_mem_data[25] $abc$24881$new_n6719 +10 1 +.names o_mem_data[29] o_mem_addr[29] $abc$24881$new_n6720 +10 1 +.names o_mem_addr[27] o_mem_data[27] $abc$24881$new_n6721 +10 1 +.names o_mem_addr[29] o_mem_data[29] $abc$24881$new_n6722 +10 1 +.names $abc$24881$new_n6657 $abc$24881$new_n6724 $abc$24881$new_n6787 $abc$24881$new_n6785 $abc$24881$new_n6751 $abc$24881$new_n6723 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6777 $abc$24881$new_n6658 $abc$24881$new_n9664 $abc$24881$new_n6784 o_mem_addr[5] $abc$24881$new_n6724 +10000 1 +10010 1 +10011 1 +.names o_mem_addr[3] $abc$24881$new_n6728 $abc$24881$new_n6733 $abc$24881$new_n6727 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6729 $abc$24881$new_n6731 $abc$24881$new_n6728 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6730 o_mem_data[14] o_mem_data[13] $abc$24881$new_n6729 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[16] o_mem_data[15] $abc$24881$new_n6730 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6732 o_mem_data[10] o_mem_data[9] $abc$24881$new_n6731 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[12] o_mem_data[11] $abc$24881$new_n6732 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[2] $abc$24881$new_n6734 $abc$24881$new_n6736 $abc$24881$new_n6733 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6735 o_mem_data[6] o_mem_data[5] $abc$24881$new_n6734 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[8] o_mem_data[7] $abc$24881$new_n6735 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[1] $abc$24881$new_n6737 $abc$24881$new_n6738 $abc$24881$new_n6736 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[4] o_mem_data[3] $abc$24881$new_n6737 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[0] o_mem_data[2] o_mem_data[1] $abc$24881$new_n6738 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[1] $abc$24881$new_n6742 $abc$24881$new_n6743 $abc$24881$new_n6741 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[28] o_mem_data[27] $abc$24881$new_n6742 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[0] o_mem_data[26] o_mem_data[25] $abc$24881$new_n6743 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n6744 +00 1 +.names o_mem_addr[0] o_mem_addr[1] o_mem_data[30] o_mem_data[29] o_mem_data[31] $abc$24881$new_n6745 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n6747 $abc$24881$new_n6749 $abc$24881$new_n6746 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6748 o_mem_data[24] o_mem_data[23] $abc$24881$new_n6747 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[22] o_mem_data[21] $abc$24881$new_n6748 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6750 o_mem_data[20] o_mem_data[19] $abc$24881$new_n6749 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[18] o_mem_data[17] $abc$24881$new_n6750 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[4] $abc$24881$new_n6769 $abc$24881$new_n6752 $abc$24881$new_n6764 o_mem_addr[3] $abc$24881$new_n6751 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names o_mem_addr[3] $abc$24881$new_n6753 $abc$24881$new_n6759 $abc$24881$new_n6752 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6754 $abc$24881$new_n6757 $abc$24881$new_n6753 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] $abc$24881$new_n6755 $abc$24881$new_n6756 $abc$24881$new_n6754 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[16] o_mem_data[15] $abc$24881$new_n6755 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[18] o_mem_data[17] $abc$24881$new_n6756 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6758 o_mem_data[20] o_mem_data[19] $abc$24881$new_n6757 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[22] o_mem_data[21] $abc$24881$new_n6758 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[2] $abc$24881$new_n6760 $abc$24881$new_n6762 $abc$24881$new_n6759 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6761 o_mem_data[24] o_mem_data[23] $abc$24881$new_n6760 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[26] o_mem_data[25] $abc$24881$new_n6761 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6763 o_mem_data[28] o_mem_data[27] $abc$24881$new_n6762 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[30] o_mem_data[29] $abc$24881$new_n6763 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[2] $abc$24881$new_n6765 $abc$24881$new_n6767 $abc$24881$new_n6764 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6766 o_mem_data[10] o_mem_data[9] $abc$24881$new_n6765 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[0] o_mem_data[8] o_mem_data[7] $abc$24881$new_n6766 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6768 o_mem_data[14] o_mem_data[13] $abc$24881$new_n6767 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[0] o_mem_data[12] o_mem_data[11] $abc$24881$new_n6768 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n6770 $abc$24881$new_n6773 $abc$24881$new_n6769 +1001 1 +1011 1 +1100 1 +1101 1 +.names o_mem_addr[1] $abc$24881$new_n6771 $abc$24881$new_n6772 $abc$24881$new_n6770 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[4] o_mem_data[3] $abc$24881$new_n6771 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[6] o_mem_data[5] $abc$24881$new_n6772 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] $abc$24881$new_n6774 $abc$24881$new_n6775 $abc$24881$new_n6773 +001 1 +011 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[2] o_mem_data[1] $abc$24881$new_n6774 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[0] $abc$24881$new_n6775 +11 1 +.names o_mem_op[1] o_mem_op[2] FWD_OPERATION.r_op_opn[3] DIVIDE.thedivide.i_signed $abc$24881$new_n6776 +1100 1 +.names $abc$24881$new_n6781 $abc$24881$new_n6778 $abc$24881$new_n6783 o_mem_addr[29] o_mem_addr[30] $abc$24881$new_n6777 +11100 1 +.names $abc$24881$new_n6779 o_mem_addr[31] o_mem_addr[6] o_mem_addr[7] o_mem_addr[8] $abc$24881$new_n6778 +10000 1 +.names $abc$24881$new_n6780 o_mem_addr[11] o_mem_addr[13] o_mem_addr[15] o_mem_addr[17] $abc$24881$new_n6779 +10000 1 +.names o_mem_addr[21] o_mem_addr[23] o_mem_addr[25] o_mem_addr[26] $abc$24881$new_n6780 +0000 1 +.names $abc$24881$new_n6782 o_mem_addr[9] o_mem_addr[10] o_mem_addr[12] o_mem_addr[14] $abc$24881$new_n6781 +10000 1 +.names o_mem_addr[16] o_mem_addr[18] o_mem_addr[19] o_mem_addr[20] $abc$24881$new_n6782 +0000 1 +.names o_mem_addr[22] o_mem_addr[24] o_mem_addr[27] o_mem_addr[28] $abc$24881$new_n6783 +0000 1 +.names $abc$24881$new_n6744 o_mem_addr[0] o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n6784 +1000 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6786 $abc$24881$new_n6785 +11 1 +.names $abc$24881$new_n6777 o_mem_addr[5] $abc$24881$new_n6786 +10 1 +.names $abc$24881$new_n6658 o_mem_data[31] $abc$24881$new_n6786 $abc$24881$new_n6787 +110 1 +.names o_mem_data[30] o_mem_data[31] o_mem_addr[30] o_mem_addr[31] $abc$24881$new_n6653 $abc$24881$new_n6788 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01111 1 +10011 1 +10101 1 +10111 1 +11111 1 +.names alu_ce o_mem_data[31] doalu.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$23624 +001 1 +011 1 +110 1 +111 1 +.names op_valid_div $abc$24881$new_n5375 $abc$24881$new_n4031 DIVIDE.thedivide.i_wr +111 1 +.names $abc$24881$new_n5383 DIVIDE.thedivide.zero_divisor $abc$24881$new_n6786 $abc$24881$new_n6784 $abc$24881$auto$rtlil.cc:2693:MuxGate$23626 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4085 $abc$24881$auto$rtlil.cc:2693:MuxGate$23628 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$new_n6794 $abc$24881$auto$rtlil.cc:2693:MuxGate$23630 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6796 $abc$24881$new_n6795 $abc$24881$new_n6798 instruction_decoder.o_dcdB[3] $abc$24881$new_n4284 $abc$24881$new_n6794 +11100 1 +11111 1 +.names $abc$24881$new_n4260 $abc$24881$new_n4258 $abc$24881$new_n6795 +10 1 +.names $abc$24881$new_n6797 dcd_opn[0] $abc$24881$new_n4282 instruction_decoder.o_dcdB[2] $abc$24881$new_n4288 $abc$24881$new_n6796 +10100 1 +10111 1 +11000 1 +11011 1 +.names instruction_decoder.GEN_OPIPE.r_insn_is_pipeable $abc$24881$new_n4085 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6797 +101 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[1] $abc$24881$new_n4290 $abc$24881$new_n4292 $abc$24881$new_n6798 +0011 1 +0101 1 +1010 1 +1100 1 +.names $abc$24881$new_n6795 $abc$24881$new_n4277 $abc$24881$new_n4284 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n6801 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n4085 $abc$24881$flatten\instruction_decoder.$procmux$2071_Y $abc$24881$auto$rtlil.cc:2693:MuxGate$23634 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[30] $abc$24881$new_n6806 i_pf_instruction[21] i_pf_instruction[25] $abc$24881$flatten\instruction_decoder.$procmux$2071_Y +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[29] $abc$24881$new_n6807 i_pf_instruction[20] i_pf_instruction[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6806 +11000 1 +.names $abc$24881$new_n6808 i_pf_instruction[23] i_pf_instruction[28] i_pf_instruction[27] i_pf_instruction[26] $abc$24881$new_n6807 +11110 1 +.names i_pf_instruction[31] i_pf_instruction[18] i_pf_instruction[19] i_pf_instruction[22] $abc$24881$new_n6808 +0000 1 +.names $abc$24881$new_n6475 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb $abc$24881$new_n6810 $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$auto$rtlil.cc:2693:MuxGate$23636 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6820 $abc$24881$new_n4277 $abc$24881$new_n4286 $abc$24881$new_n6811 $abc$24881$new_n6818 $abc$24881$new_n6810 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6812 $abc$24881$new_n4293 $abc$24881$new_n6816 $abc$24881$new_n6814 $abc$24881$new_n5455 $abc$24881$new_n6811 +11110 1 +.names i_pf_instruction[17] $abc$24881$new_n6632 $abc$24881$new_n6813 $abc$24881$new_n4085 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6812 +11110 1 +.names i_pf_instruction[14] i_pf_instruction[31] i_pf_instruction[11] i_pf_instruction[12] $abc$24881$new_n6813 +1000 1 +.names i_pf_instruction[15] i_pf_instruction[18] $abc$24881$new_n6815 i_pf_instruction[0] i_pf_instruction[1] $abc$24881$new_n6814 +11100 1 +.names i_pf_instruction[2] i_pf_instruction[3] i_pf_instruction[4] i_pf_instruction[5] $abc$24881$new_n6815 +0000 1 +.names $abc$24881$new_n6817 $abc$24881$new_n4287 i_pf_instruction[10] i_pf_instruction[13] $abc$24881$new_n4273 $abc$24881$new_n6816 +11000 1 +.names i_pf_instruction[6] i_pf_instruction[7] i_pf_instruction[8] i_pf_instruction[9] $abc$24881$new_n6817 +0000 1 +.names $abc$24881$new_n4291 $abc$24881$new_n6819 $abc$24881$new_n4283 $abc$24881$new_n4289 $abc$24881$new_n4293 $abc$24881$new_n6818 +11100 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[7] $abc$24881$new_n5442 $abc$24881$new_n5455 $abc$24881$new_n4287 $abc$24881$new_n6819 +11110 1 +.names $abc$24881$new_n4267 $abc$24881$new_n4302 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_valid $abc$24881$new_n6820 +10000 1 +10001 1 +10010 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction[31] $abc$24881$new_n4085 i_pf_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23638 +00110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_valid o_pf_ready instruction_decoder.o_illegal $abc$24881$new_n6825 $abc$24881$new_n6823 $abc$24881$auto$rtlil.cc:2693:MuxGate$23640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4277 $abc$24881$new_n6622 $abc$24881$new_n4269 $abc$24881$new_n6824 $abc$24881$new_n4261 $abc$24881$new_n6823 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n4270 $abc$24881$new_n4262 $abc$24881$new_n4277 $abc$24881$new_n4282 $abc$24881$new_n4268 $abc$24881$new_n6824 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_illegal $abc$24881$new_n6621 $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n4287 $abc$24881$new_n6825 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +.names $abc$24881$new_n6827 o_mem_addr[31] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23642 +000 1 +001 1 +010 1 +011 1 +110 1 +.names DIVIDE.thedivide.r_divisor[31] DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign $abc$24881$new_n6828 DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n6827 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n5512 DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n6828 +10 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n5529 $abc$24881$new_n6828 o_mem_addr[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23644 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_z $abc$24881$new_n3867 $abc$24881$new_n3829 $abc$24881$auto$rtlil.cc:2693:MuxGate$23646 +100 1 +110 1 +111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor DIVIDE.thedivide.last_bit DIVIDE.thedivide.o_valid $abc$24881$auto$rtlil.cc:2693:MuxGate$23648 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6834 $abc$24881$new_n5383 $abc$24881$auto$rtlil.cc:2693:MuxGate$23650 +01 1 +10 1 +11 1 +.names DIVIDE.thedivide.o_busy DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor DIVIDE.thedivide.last_bit DIVIDE.thedivide.r_sign $abc$24881$new_n6834 +11000 1 +11001 1 +11011 1 +.names $abc$24881$new_n5383 DIVIDE.thedivide.r_busy DIVIDE.thedivide.last_bit DIVIDE.thedivide.zero_divisor $abc$24881$auto$rtlil.cc:2693:MuxGate$23652 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n6837 GEN_ALU_PC.r_alu_pc[31] SET_USER_PC.r_upc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23654 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] doalu.n i_mem_result[31] dbg_val[31] $abc$24881$new_n6837 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names SET_GIE.r_gie $abc$24881$new_n3957 $abc$24881$new_n6840 $abc$24881$new_n6839 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23656 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names wr_index[0] wr_index[1] $abc$24881$new_n3860 i_mem_result[1] $abc$24881$new_n6839 +0010 1 +0011 1 +0110 1 +0111 1 +1000 1 +1010 1 +1110 1 +1111 1 +.names r_alu_pc_valid DIVIDE.thedivide.o_busy GEN_UHALT_PHASE.r_uhalt_phase GEN_ALU_PHASE.r_alu_phase $abc$24881$new_n6840 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names o_i_count SET_GIE.r_gie GEN_IHALT_PHASE.r_ihalt_phase GEN_ALU_PHASE.r_alu_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23658 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n6843 DIVERR.USER_DIVERR.r_udiv_err_flag $abc$24881$new_n4001 DIVIDE.thedivide.o_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23660 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4079 SET_GIE.r_gie dbgv $abc$24881$new_n6843 +100 1 +101 1 +111 1 +.names $abc$24881$new_n6845 DIVERR.r_idiv_err_flag $abc$24881$new_n4001 DIVIDE.thedivide.o_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23662 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dbgv $abc$24881$new_n3697 $abc$24881$new_n3694 $abc$24881$new_n4036 $abc$24881$new_n6845 +1111 1 +.names $abc$24881$new_n6843 SET_USER_BUSERR.r_ubus_err_flag $abc$24881$new_n4003 i_bus_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23664 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6843 SET_USER_ILLEGAL_INSN.r_ill_err_u $abc$24881$new_n4007 SET_ALU_ILLEGAL.r_alu_illegal $abc$24881$new_n4402 $abc$24881$auto$rtlil.cc:2693:MuxGate$23666 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names SET_TRAP_N_UBREAK.r_ubreak GEN_PENDING_BREAK.r_break_pending $abc$24881$new_n4077 $abc$24881$new_n6843 $abc$24881$new_n4009 $abc$24881$auto$rtlil.cc:2693:MuxGate$23668 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names SET_TRAP_N_UBREAK.r_trap SET_GIE.r_gie $abc$24881$new_n6850 dbgv $abc$24881$new_n4005 $abc$24881$auto$rtlil.cc:2693:MuxGate$23670 +01000 1 +01001 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4079 SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n6850 +000 1 +001 1 +010 1 +011 1 +110 1 +.names SET_GIE.r_gie $abc$24881$new_n4082 $abc$24881$auto$rtlil.cc:2693:MuxGate$23672 +01 1 +10 1 +11 1 +.names $abc$24881$new_n6853 op_illegal $abc$24881$new_n4031 $abc$24881$auto$rtlil.cc:2693:MuxGate$23674 +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_interrupt GEN_PENDING_BREAK.r_break_pending GEN_PENDING_INTERRUPT.r_pending_interrupt $abc$24881$new_n6854 $abc$24881$new_n6853 +0000 1 +.names user_step GEN_PENDING_INTERRUPT.r_user_stepped $abc$24881$new_n3959 $abc$24881$new_n6855 $abc$24881$new_n6854 +1100 1 +1101 1 +1111 1 +.names i_mem_busy DIVIDE.thedivide.o_busy $abc$24881$new_n6855 +00 1 +.names GEN_PENDING_INTERRUPT.r_user_stepped $abc$24881$new_n6857 $abc$24881$auto$rtlil.cc:2693:MuxGate$23676 +01 1 +10 1 +11 1 +.names GEN_OPLOCK.r_op_lock OPT_CIS_OP_PHASE.r_op_phase BUSLOCK.r_bus_lock[1] $abc$24881$new_n4030 $abc$24881$new_n6857 +0000 1 +.names $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y SET_GIE.r_gie $abc$24881$new_n4013 sleep $abc$24881$new_n6859 $abc$24881$auto$rtlil.cc:2693:MuxGate$23678 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4015 i_interrupt SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n6859 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names GEN_PENDING_BREAK.r_break_pending $abc$24881$new_n3959 $abc$24881$new_n6855 r_op_break $abc$24881$new_n4046 $abc$24881$auto$rtlil.cc:2693:MuxGate$23680 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names BUSLOCK.r_bus_lock[1] BUSLOCK.r_bus_lock[0] $abc$24881$new_n4030 GEN_OPLOCK.r_op_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23682 +0001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n6863 GEN_OPLOCK.r_op_lock $abc$24881$new_n4031 o_bus_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23684 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names BUSLOCK.r_prelock_stall instruction_decoder.r_valid op_valid i_pf_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6863 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$24881$new_n4030 GEN_ALU_PHASE.r_alu_phase OPT_CIS_OP_PHASE.r_op_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23686 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_CIS_PHASE.r_phase OPT_CIS_OP_PHASE.r_op_phase dcd_Apc dcd_wR $abc$24881$auto$rtlil.cc:2693:MuxGate$23688 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 GEN_OPLOCK.r_op_lock instruction_decoder.o_lock instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23690 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$24881$new_n5066 $abc$24881$new_n6868 op_valid_mem instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$auto$rtlil.cc:2693:MuxGate$23692 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names GEN_OP_PIPE.r_op_pipe mem_ce $abc$24881$new_n5152 $abc$24881$new_n5155 $abc$24881$new_n6868 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n6870 $abc$24881$new_n4030 i_mem_rdbusy GEN_OP_STALL.r_pending_sreg_write $abc$24881$auto$rtlil.cc:2693:MuxGate$23694 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] $abc$24881$new_n6871 $abc$24881$new_n4066 $abc$24881$new_n6870 +11110 1 +.names $abc$24881$new_n5375 GEN_OP_WR.r_op_wR op_illegal $abc$24881$new_n6871 +110 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n6837 GEN_ALU_PC.r_alu_pc[31] ipc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23696 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6845 ibus_err_flag $abc$24881$new_n4003 i_bus_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23698 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names ill_err_i $abc$24881$new_n6845 $abc$24881$new_n6875 $abc$24881$new_n4007 $abc$24881$auto$rtlil.cc:2693:MuxGate$23700 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names SET_ALU_ILLEGAL.r_alu_illegal new_pc SET_GIE.r_gie $abc$24881$new_n6875 +100 1 +.names $abc$24881$new_n4079 SET_GIE.r_gie user_step $abc$24881$new_n4011 $abc$24881$auto$rtlil.cc:2693:MuxGate$23702 +0010 1 +0011 1 +0110 1 +0111 1 +1000 1 +1010 1 +1110 1 +1111 1 +.names $abc$24881$new_n4083 $abc$24881$new_n4009 break_en $abc$24881$auto$rtlil.cc:2693:MuxGate$23704 +001 1 +011 1 +100 1 +101 1 +.names OPT_CIS_OP_PHASE.r_op_phase $abc$24881$new_n4031 DIVIDE.thedivide.o_busy r_alu_pc_valid new_pc $abc$24881$auto$rtlil.cc:2693:MuxGate$23706 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$24881$new_n4030 wr_index[1] op_valid_div op_valid_alu $abc$24881$auto$rtlil.cc:2693:MuxGate$23708 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n6881 op_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23710 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_illegal instruction_decoder.r_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6881 +1100 1 +.names $abc$24881$new_n5066 r_op_break dcd_break instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23712 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$24881$new_n6884 op_valid $abc$24881$new_n4030 $abc$24881$auto$rtlil.cc:2693:MuxGate$23714 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch instruction_decoder.r_valid new_pc instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6884 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6886 op_valid_mem $abc$24881$new_n6887 dcd_M instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23716 +00110 1 +01110 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4030 $abc$24881$new_n5066 $abc$24881$new_n6886 +10 1 +.names $abc$24881$new_n5066 instruction_decoder.r_valid new_pc instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6887 +11000 1 +.names $abc$24881$new_n6887 op_valid_alu $abc$24881$new_n6886 dcd_ALU instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23718 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6886 op_valid_div $abc$24881$new_n6887 instruction_decoder.o_DV instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23720 +00110 1 +01110 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6891 $abc$24881$new_n6892 $abc$24881$auto$rtlil.cc:2693:MuxGate$23722 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[30] $abc$24881$new_n6441 $abc$24881$new_n6891 +11 1 +.names i_pf_instruction_pc[31] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[30] $abc$24881$new_n6460 i_pf_instruction[31] $abc$24881$new_n6892 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] $abc$24881$new_n6894 $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23724 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[31] i_pf_instruction[17] i_pf_instruction_pc[30] $abc$24881$new_n6365 $abc$24881$new_n6894 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$24881$new_n5066 SET_OP_PC.r_op_pc[1] instruction_decoder.o_pc[1] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23728 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$24881$new_n3829 $abc$24881$new_n6897 DIVIDE.thedivide.r_dividend[62] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$23732 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names DIVIDE.thedivide.r_dividend[61] DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n3869 DIVIDE.thedivide.r_dividend[62] DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n6897 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n6899 DIVIDE.thedivide.r_dividend[32] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$23734 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[0] $abc$24881$new_n3867 $abc$24881$new_n6899 +000 1 +001 1 +011 1 +110 1 +.names $abc$24881$new_n6901 ipc[31] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$23736 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n6902 $abc$24881$new_n6837 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[31] $abc$24881$new_n6901 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] $abc$24881$new_n6903 $abc$24881$new_n6904 $abc$24881$new_n6902 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] $abc$24881$new_n4106 $abc$24881$new_n6903 +111 1 +.names $abc$24881$new_n4024 pf_pc[31] $abc$24881$new_n6905 SET_USER_PC.r_upc[31] $abc$24881$new_n4087 $abc$24881$new_n6904 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names pf_pc[28] pf_pc[29] pf_pc[30] $abc$24881$new_n4090 $abc$24881$new_n6905 +1111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[31] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] instruction_decoder.o_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23738 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[31] SET_OP_PC.r_op_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23740 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5407 $abc$24881$new_n6909 o_mem_lock_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23742 +001 1 +011 1 +110 1 +111 1 +.names SET_OP_PC.r_op_pc[31] $abc$24881$new_n5393 SET_OP_PC.r_op_pc[29] SET_OP_PC.r_op_pc[30] $abc$24881$new_n6909 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names o_clear_icache DIVIDE.thedivide.i_reset instruction_decoder.i_reset +01 1 +10 1 +11 1 +.names new_pc i_reset DIVIDE.thedivide.i_reset +01 1 +10 1 +11 1 +.names $abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y o_pf_ready $abc$24881$new_n4085 i_pf_illegal $abc$24881$auto$opt_dff.cc:253:combine_resets$3478 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.i_reset $abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y +01 1 +10 1 +11 1 +.names $abc$24881$new_n4028 dcd_F[1] $abc$24881$new_n4291 $abc$24881$new_n4274 $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] $abc$24881$auto$opt_dff.cc:253:combine_resets$4528 +00 1 +01 1 +11 1 +.names $abc$24881$new_n4028 dcd_F[2] $abc$24881$new_n4274 $abc$24881$new_n4289 $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4085 instruction_decoder.i_reset $abc$24881$new_n4028 $abc$24881$auto$opt_dff.cc:253:combine_resets$3474 +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3460 +00 1 +01 1 +11 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +00 1 +01 1 +11 1 +.names $abc$24881$new_n4078 i_reset $abc$24881$new_n4046 $abc$24881$new_n4402 $abc$24881$auto$opt_dff.cc:253:combine_resets$3429 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4031 new_pc $abc$24881$auto$opt_dff.cc:253:combine_resets$3420 +00 1 +01 1 +11 1 +.names $abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y $abc$24881$new_n4035 $abc$24881$auto$opt_dff.cc:253:combine_resets$3407 +01 1 +10 1 +11 1 +.names r_halted i_reset $abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y +00 1 +01 1 +11 1 +.names $abc$24881$new_n4105 i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3404 +00 1 +01 1 +11 1 +.names $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3389 +00 1 +01 1 +11 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor $abc$24881$auto$simplemap.cc:240:simplemap_eqne$9293[0] +11 1 +.names alu_ce i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3485 +00 1 +01 1 +11 1 +.names DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[4] DIVIDE.thedivide.r_bit[0] $abc$24881$flatten\DIVIDE.thedivide.$eq$./benchmark/div.v:248$1635_Y +11110 1 +.names $abc$24881$new_n6931 $abc$24881$new_n6930 $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y +11 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n6930 +11 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n6931 +11 1 +.names $abc$24881$new_n6933 DIVIDE.thedivide.r_dividend[62] DIVIDE.thedivide.r_divisor[31] $abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:372$1666_Y +100 1 +111 1 +.names $abc$24881$new_n6934 $abc$24881$new_n6949 DIVIDE.thedivide.r_divisor[29] DIVIDE.thedivide.r_dividend[60] $abc$24881$new_n6933 +1100 1 +1111 1 +.names $abc$24881$new_n6935 DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3887 $abc$24881$new_n6934 +1000 1 +1110 1 +.names $abc$24881$new_n6936 DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3892 $abc$24881$new_n6935 +1000 1 +1110 1 +.names $abc$24881$new_n6937 DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3897 $abc$24881$new_n6936 +1000 1 +1110 1 +.names $abc$24881$new_n6938 DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3902 $abc$24881$new_n6937 +1000 1 +1110 1 +.names $abc$24881$new_n6939 DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3907 $abc$24881$new_n6938 +1000 1 +1110 1 +.names $abc$24881$new_n9670 DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3912 $abc$24881$new_n6939 +1000 1 +1110 1 +.names $abc$24881$new_n6944 DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3937 $abc$24881$new_n6943 +1000 1 +1110 1 +.names $abc$24881$new_n6945 DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3942 $abc$24881$new_n6944 +1000 1 +1110 1 +.names $abc$24881$new_n6946 DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3947 $abc$24881$new_n6945 +1000 1 +1110 1 +.names $abc$24881$new_n6947 $abc$24881$new_n3953 $abc$24881$new_n3950 $abc$24881$new_n6946 +100 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n6947 +10000 1 +10011 1 +11100 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[30] DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n6949 +00 1 +11 1 +.names DIVIDE.thedivide.i_signed DIVIDE.thedivide.i_wr o_mem_addr[31] o_mem_data[31] $abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:263$1639_Y +1101 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.o_valid DIVIDE.thedivide.i_reset $abc$24881$flatten\DIVIDE.thedivide.$logic_or$./benchmark/div.v:189$1625_Y +01 1 +10 1 +11 1 +.names $abc$24881$new_n4033 $abc$24881$new_n4029 o_op_stall +10 1 +.names $abc$24881$new_n4033 i_pf_valid o_pf_stall +10 1 +.names i_halt new_pc $abc$24881$logic_or$./benchmark/zipcore.v:728$452_Y +01 1 +10 1 +11 1 +.names $abc$24881$new_n5375 op_wF op_illegal $abc$24881$logic_and$./benchmark/zipcore.v:1613$573_Y +110 1 +.names op_valid new_pc $abc$24881$logic_or$./benchmark/zipcore.v:2501$630_Y +00 1 +01 1 +11 1 +.names GEN_CLOCK_GATE.r_clken i_clear_cache i_dbg_we $abc$24881$new_n6958 o_clken +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_halt sleep i_interrupt $abc$24881$new_n6958 +000 1 +001 1 +011 1 +.names SET_GIE.r_gie user_step i_reset $abc$24881$logic_or$./benchmark/zipcore.v:2741$689_Y +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names i_reset $abc$24881$new_n4082 $abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +01 1 +10 1 +11 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3863 regset[15][0] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3859 regset[15][1] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3853 regset[15][2] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3848 regset[15][3] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3843 regset[15][4] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3838 regset[15][5] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3832 regset[15][6] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3825 regset[15][7] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3820 regset[15][8] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3815 regset[15][9] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3810 regset[15][10] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3805 regset[15][11] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3800 regset[15][12] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3795 regset[15][13] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3790 regset[15][14] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3784 regset[15][15] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3779 regset[15][16] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3774 regset[15][17] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3769 regset[15][18] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3763 regset[15][19] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3757 regset[15][20] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3752 regset[15][21] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3747 regset[15][22] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3741 regset[15][23] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3735 regset[15][24] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3730 regset[15][25] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3725 regset[15][26] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3719 regset[15][27] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3714 regset[15][28] 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$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3810 regset[3][10] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3805 regset[3][11] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3800 regset[3][12] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3795 regset[3][13] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3790 regset[3][14] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3784 regset[3][15] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3779 regset[3][16] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3774 regset[3][17] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3769 regset[3][18] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3763 regset[3][19] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3757 regset[3][20] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3752 regset[3][21] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3747 regset[3][22] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3741 regset[3][23] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3735 regset[3][24] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3730 regset[3][25] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3725 regset[3][26] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3719 regset[3][27] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3714 regset[3][28] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3708 regset[3][29] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3702 regset[3][30] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n6568 regset[3][31] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[31] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign $abc$24881$new_n7342 o_mem_data[31] DIVIDE.thedivide.r_dividend[30] $abc$24881$flatten\DIVIDE.thedivide.$0\r_dividend[62:0][31] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.pre_sign $abc$24881$new_n3672 DIVIDE.thedivide.r_dividend[29] DIVIDE.thedivide.r_dividend[30] $abc$24881$new_n7342 +11100 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3863 regset[16][0] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3695 $abc$24881$new_n7027 $abc$24881$new_n3694 $abc$24881$new_n7344 +1110 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3859 regset[16][1] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3853 regset[16][2] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3848 regset[16][3] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3843 regset[16][4] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3838 regset[16][5] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3832 regset[16][6] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3825 regset[16][7] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3820 regset[16][8] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3815 regset[16][9] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3810 regset[16][10] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3805 regset[16][11] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3800 regset[16][12] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3795 regset[16][13] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3790 regset[16][14] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3784 regset[16][15] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3779 regset[16][16] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3774 regset[16][17] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3769 regset[16][18] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3763 regset[16][19] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3757 regset[16][20] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3752 regset[16][21] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3747 regset[16][22] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3741 regset[16][23] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3735 regset[16][24] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3730 regset[16][25] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3725 regset[16][26] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3719 regset[16][27] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3714 regset[16][28] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3708 regset[16][29] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3702 regset[16][30] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n6568 regset[16][31] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[31] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n7377 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2314_Y +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor $abc$24881$new_n7377 +110 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3863 regset[2][0] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n7143 $abc$24881$new_n7379 +1111 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3859 regset[2][1] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3853 regset[2][2] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3848 regset[2][3] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3843 regset[2][4] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3838 regset[2][5] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3832 regset[2][6] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3825 regset[2][7] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3820 regset[2][8] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3815 regset[2][9] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3810 regset[2][10] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3805 regset[2][11] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3800 regset[2][12] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3795 regset[2][13] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3790 regset[2][14] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3784 regset[2][15] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3779 regset[2][16] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3774 regset[2][17] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3769 regset[2][18] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3763 regset[2][19] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3757 regset[2][20] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3752 regset[2][21] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3747 regset[2][22] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3741 regset[2][23] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3735 regset[2][24] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3730 regset[2][25] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3725 regset[2][26] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3719 regset[2][27] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3714 regset[2][28] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3708 regset[2][29] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3702 regset[2][30] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n6568 regset[2][31] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[31] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy $abc$24881$new_n3867 DIVIDE.thedivide.o_quotient[0] DIVIDE.thedivide.r_sign $abc$24881$flatten\DIVIDE.thedivide.$procmux$2305_Y +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names DIVIDE.thedivide.o_quotient[0] DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.r_busy $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[0] +0110 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[2] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.o_quotient[0] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[1] +00110 1 +00111 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7415 DIVIDE.thedivide.o_quotient[2] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[2] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.o_quotient[2] DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.o_quotient[0] $abc$24881$new_n7415 +000 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[4] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7415 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[3] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7418 DIVIDE.thedivide.o_quotient[4] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[4] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7415 DIVIDE.thedivide.o_quotient[4] DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7418 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[6] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7418 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[5] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7421 DIVIDE.thedivide.o_quotient[6] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[6] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7418 DIVIDE.thedivide.o_quotient[6] DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7421 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[8] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7421 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[7] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7424 DIVIDE.thedivide.o_quotient[8] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[8] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7421 DIVIDE.thedivide.o_quotient[8] DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7424 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[10] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7424 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[9] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7427 DIVIDE.thedivide.o_quotient[10] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[10] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7424 DIVIDE.thedivide.o_quotient[10] DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7427 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[12] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7427 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[11] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7430 DIVIDE.thedivide.o_quotient[12] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[12] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7427 DIVIDE.thedivide.o_quotient[12] DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7430 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[14] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7430 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[13] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7433 DIVIDE.thedivide.o_quotient[14] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[14] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7430 DIVIDE.thedivide.o_quotient[14] DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7433 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[16] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7433 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[15] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[17] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[16] $abc$24881$new_n7436 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[16] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7433 DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7436 +10 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[18] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[17] $abc$24881$new_n7438 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[17] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7436 DIVIDE.thedivide.o_quotient[16] $abc$24881$new_n7438 +10 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7440 DIVIDE.thedivide.o_quotient[18] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[18] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7438 DIVIDE.thedivide.o_quotient[18] DIVIDE.thedivide.o_quotient[17] $abc$24881$new_n7440 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[20] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7440 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[19] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[21] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[20] $abc$24881$new_n7443 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[20] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7440 DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7443 +10 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7445 DIVIDE.thedivide.o_quotient[21] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[21] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7443 DIVIDE.thedivide.o_quotient[21] DIVIDE.thedivide.o_quotient[20] $abc$24881$new_n7445 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[23] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7445 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[22] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[24] $abc$24881$new_n7448 DIVIDE.thedivide.o_quotient[23] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[23] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7445 DIVIDE.thedivide.o_quotient[23] DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7448 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[25] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[24] $abc$24881$new_n7448 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[24] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[26] $abc$24881$new_n7451 DIVIDE.thedivide.o_quotient[25] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[25] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7448 DIVIDE.thedivide.o_quotient[25] DIVIDE.thedivide.o_quotient[24] $abc$24881$new_n7451 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[27] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[26] $abc$24881$new_n7451 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[26] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[28] $abc$24881$new_n7454 DIVIDE.thedivide.o_quotient[27] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[27] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7451 DIVIDE.thedivide.o_quotient[27] DIVIDE.thedivide.o_quotient[26] $abc$24881$new_n7454 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[29] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[28] $abc$24881$new_n7454 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[28] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[30] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[29] $abc$24881$new_n7457 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[29] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7454 DIVIDE.thedivide.o_quotient[28] $abc$24881$new_n7457 +10 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.w_n DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[30] $abc$24881$new_n7459 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[30] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7457 DIVIDE.thedivide.o_quotient[29] $abc$24881$new_n7459 +10 1 +.names $abc$24881$new_n4079 $abc$24881$new_n3863 regset[30][0] $abc$24881$memory\regset$wrmux[30][0][0]$y$4516[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4079 $abc$24881$new_n3859 regset[30][1] $abc$24881$memory\regset$wrmux[30][0][0]$y$4516[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4079 $abc$24881$new_n3853 regset[30][2] $abc$24881$memory\regset$wrmux[30][0][0]$y$4516[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4079 $abc$24881$new_n3848 regset[30][3] $abc$24881$memory\regset$wrmux[30][0][0]$y$4516[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4079 $abc$24881$new_n3843 regset[30][4] $abc$24881$memory\regset$wrmux[30][0][0]$y$4516[4] +001 1 +011 1 +100 1 +101 1 +.names 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1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3747 regset[28][22] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3741 regset[28][23] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3735 regset[28][24] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3730 regset[28][25] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3725 regset[28][26] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3719 regset[28][27] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3714 regset[28][28] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3708 regset[28][29] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3702 regset[28][30] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n6568 regset[28][31] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[31] +001 1 +011 1 +100 1 +101 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] o_pf_request_address[2] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] o_pf_request_address[3] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] o_pf_request_address[4] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[5] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] o_pf_request_address[5] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] o_pf_request_address[6] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] o_pf_request_address[7] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] o_pf_request_address[8] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] o_pf_request_address[9] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] o_pf_request_address[10] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] o_pf_request_address[11] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] o_pf_request_address[12] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] o_pf_request_address[13] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] o_pf_request_address[14] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] o_pf_request_address[15] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[16] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] o_pf_request_address[16] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] o_pf_request_address[17] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] o_pf_request_address[18] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] o_pf_request_address[19] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] o_pf_request_address[20] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] o_pf_request_address[21] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[22] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] o_pf_request_address[22] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[23] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] o_pf_request_address[23] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[24] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] o_pf_request_address[24] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[25] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] o_pf_request_address[25] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[26] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] o_pf_request_address[26] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[27] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] o_pf_request_address[27] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[28] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] o_pf_request_address[28] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] o_pf_request_address[29] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] o_pf_request_address[30] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[31] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] o_pf_request_address[31] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3863 regset[27][0] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3958 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n7589 +1100 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3859 regset[27][1] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3853 regset[27][2] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3848 regset[27][3] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3843 regset[27][4] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3838 regset[27][5] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3832 regset[27][6] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3825 regset[27][7] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3820 regset[27][8] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3815 regset[27][9] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3810 regset[27][10] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3805 regset[27][11] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3800 regset[27][12] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3795 regset[27][13] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3790 regset[27][14] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3784 regset[27][15] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3779 regset[27][16] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3774 regset[27][17] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3769 regset[27][18] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3763 regset[27][19] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3757 regset[27][20] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3752 regset[27][21] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3747 regset[27][22] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3741 regset[27][23] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3735 regset[27][24] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3730 regset[27][25] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3725 regset[27][26] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3719 regset[27][27] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3714 regset[27][28] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3708 regset[27][29] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3702 regset[27][30] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n6568 regset[27][31] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3863 regset[22][0] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7143 $abc$24881$new_n3695 $abc$24881$new_n3701 $abc$24881$new_n3694 $abc$24881$new_n7622 +1100 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3859 regset[22][1] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3853 regset[22][2] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3848 regset[22][3] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3843 regset[22][4] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3838 regset[22][5] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3832 regset[22][6] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3825 regset[22][7] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3820 regset[22][8] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3815 regset[22][9] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3810 regset[22][10] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3805 regset[22][11] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3800 regset[22][12] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3795 regset[22][13] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3790 regset[22][14] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3784 regset[22][15] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3779 regset[22][16] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[16] +001 1 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o_mem_addr[2] $abc$24881$new_n7701 $abc$24881$new_n7703 $abc$24881$new_n7700 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7702 o_mem_data[27] o_mem_data[26] $abc$24881$new_n7701 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[0] o_mem_data[25] o_mem_data[24] $abc$24881$new_n7702 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] $abc$24881$new_n7704 $abc$24881$new_n7705 $abc$24881$new_n7703 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[29] o_mem_data[28] $abc$24881$new_n7704 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[30] o_mem_data[31] $abc$24881$new_n7705 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[2] $abc$24881$new_n7707 $abc$24881$new_n7709 $abc$24881$new_n7706 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7708 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7707 +00100 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+010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[7] o_mem_data[6] $abc$24881$new_n7714 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] $abc$24881$new_n7716 o_mem_addr[0] o_mem_data[1] $abc$24881$new_n7715 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names o_mem_addr[0] o_mem_data[3] o_mem_data[2] $abc$24881$new_n7716 +000 1 +010 1 +100 1 +101 1 +.names o_mem_data[0] o_mem_addr[0] o_mem_addr[1] $abc$24881$new_n7717 +100 1 +.names $abc$24881$new_n7717 o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n7718 +100 1 +.names $abc$24881$new_n7721 $abc$24881$new_n6653 o_mem_addr[0] $abc$24881$new_n7720 o_mem_data[0] $abc$24881$new_n7719 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +.names o_mem_data[0] o_mem_addr[0] $abc$24881$new_n7723 $abc$24881$new_n7724 $abc$24881$new_n7721 $abc$24881$new_n7720 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 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$abc$24881$new_n7730 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n6787 $abc$24881$new_n9679 $abc$24881$new_n6785 $abc$24881$new_n7739 o_mem_addr[4] $abc$24881$new_n7731 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names o_mem_addr[2] $abc$24881$new_n7734 $abc$24881$new_n7735 $abc$24881$new_n7733 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6768 o_mem_data[10] o_mem_data[9] $abc$24881$new_n7734 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6755 o_mem_data[14] o_mem_data[13] $abc$24881$new_n7735 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] $abc$24881$new_n6766 $abc$24881$new_n6772 $abc$24881$new_n7737 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[3] $abc$24881$new_n7740 $abc$24881$new_n7743 $abc$24881$new_n7739 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7741 $abc$24881$new_n7742 $abc$24881$new_n7740 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6756 o_mem_data[20] o_mem_data[19] $abc$24881$new_n7741 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6758 o_mem_data[24] o_mem_data[23] $abc$24881$new_n7742 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7744 $abc$24881$new_n6763 o_mem_data[31] $abc$24881$new_n7743 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6761 o_mem_data[28] o_mem_data[27] $abc$24881$new_n7744 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n9679 $abc$24881$new_n7746 $abc$24881$new_n7750 $abc$24881$new_n7745 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7740 $abc$24881$new_n7747 $abc$24881$new_n7746 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7744 $abc$24881$new_n7748 $abc$24881$new_n7747 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] $abc$24881$new_n6763 $abc$24881$new_n7749 $abc$24881$new_n7748 +010 1 +011 1 +100 1 +110 1 +.names o_mem_data[31] o_mem_addr[0] $abc$24881$new_n7749 +10 1 +.names o_mem_addr[1] o_mem_addr[3] $abc$24881$new_n7751 o_mem_addr[2] $abc$24881$new_n7750 +0000 1 +.names o_mem_addr[0] o_mem_data[1] o_mem_data[0] $abc$24881$new_n7751 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7781 $abc$24881$new_n7785 $abc$24881$new_n7727 $abc$24881$new_n7760 $abc$24881$auto$rtlil.cc:2582:Mux$3529[2] +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7761 $abc$24881$new_n7690 $abc$24881$new_n7776 $abc$24881$new_n7760 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n6787 $abc$24881$new_n7769 $abc$24881$new_n6785 $abc$24881$new_n7762 o_mem_addr[4] $abc$24881$new_n7761 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names o_mem_addr[3] $abc$24881$new_n7763 $abc$24881$new_n7766 $abc$24881$new_n7762 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n7764 o_mem_data[31] o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7763 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names o_mem_addr[2] $abc$24881$new_n7765 o_mem_addr[1] $abc$24881$new_n7705 $abc$24881$new_n7764 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7704 o_mem_data[27] o_mem_data[26] $abc$24881$new_n7765 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n7767 $abc$24881$new_n7768 $abc$24881$new_n7766 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7699 o_mem_data[19] o_mem_data[18] $abc$24881$new_n7767 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7702 o_mem_data[23] o_mem_data[22] $abc$24881$new_n7768 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7773 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7770 $abc$24881$new_n7769 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names o_mem_addr[2] $abc$24881$new_n7771 $abc$24881$new_n7772 $abc$24881$new_n7770 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7710 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7771 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7697 o_mem_data[15] o_mem_data[14] $abc$24881$new_n7772 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n7774 $abc$24881$new_n7775 $abc$24881$new_n7773 +1001 1 +1011 1 +1100 1 +1101 1 +.names o_mem_addr[1] $abc$24881$new_n7708 $abc$24881$new_n7714 $abc$24881$new_n7774 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] $abc$24881$new_n7713 $abc$24881$new_n7716 $abc$24881$new_n7775 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7769 $abc$24881$new_n7777 $abc$24881$new_n7778 $abc$24881$new_n7776 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7766 $abc$24881$new_n7764 $abc$24881$new_n7777 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n7779 o_mem_addr[3] $abc$24881$new_n7778 +10 1 +.names o_mem_addr[2] $abc$24881$new_n7780 $abc$24881$new_n7779 +00 1 +.names o_mem_addr[1] $abc$24881$new_n6738 o_mem_data[0] o_mem_addr[0] $abc$24881$new_n7780 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n7782 $abc$24881$new_n6679 $abc$24881$new_n6680 $abc$24881$new_n7722 $abc$24881$new_n6655 $abc$24881$new_n7781 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +.names $abc$24881$new_n7784 $abc$24881$new_n6653 $abc$24881$new_n6700 $abc$24881$new_n6679 $abc$24881$new_n7783 $abc$24881$new_n7782 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n7721 o_mem_addr[2] $abc$24881$new_n6654 o_mem_data[2] DIVIDE.thedivide.i_signed $abc$24881$new_n7783 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7724 o_mem_data[2] o_mem_addr[2] $abc$24881$new_n7784 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[29] o_mem_addr[2] $abc$24881$new_n7785 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n7787 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n7802 $abc$24881$new_n7804 $abc$24881$auto$rtlil.cc:2582:Mux$3529[3] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n7801 $abc$24881$new_n7788 $abc$24881$new_n7728 $abc$24881$new_n7690 $abc$24881$new_n7795 $abc$24881$new_n7787 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6787 $abc$24881$new_n7789 $abc$24881$new_n6785 $abc$24881$new_n7792 o_mem_addr[4] $abc$24881$new_n7788 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n7791 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7790 $abc$24881$new_n7789 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names o_mem_addr[2] $abc$24881$new_n6754 $abc$24881$new_n6767 $abc$24881$new_n7790 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n6765 $abc$24881$new_n6770 $abc$24881$new_n7791 +1000 1 +1010 1 +1100 1 +1101 1 +.names o_mem_addr[3] $abc$24881$new_n7793 $abc$24881$new_n7794 $abc$24881$new_n7792 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6757 $abc$24881$new_n6760 $abc$24881$new_n7793 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6762 o_mem_data[31] $abc$24881$new_n7794 +010 1 +011 1 +100 1 +110 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7789 $abc$24881$new_n7796 $abc$24881$new_n7798 $abc$24881$new_n7795 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7793 $abc$24881$new_n7797 $abc$24881$new_n7796 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6762 $abc$24881$new_n7749 o_mem_addr[1] $abc$24881$new_n7797 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n7799 o_mem_addr[3] $abc$24881$new_n7798 +10 1 +.names o_mem_addr[2] $abc$24881$new_n7800 $abc$24881$new_n7799 +00 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7751 o_mem_data[3] o_mem_data[2] $abc$24881$new_n7800 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_addr[28] o_mem_addr[3] $abc$24881$new_n7801 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names o_mem_addr[3] o_mem_data[3] $abc$24881$new_n7803 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7802 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[2] o_mem_data[2] $abc$24881$new_n6700 $abc$24881$new_n7803 +001 1 +100 1 +101 1 +111 1 +.names o_mem_addr[3] o_mem_data[3] $abc$24881$new_n7805 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n7804 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +10000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n6678 $abc$24881$new_n6679 $abc$24881$new_n6680 $abc$24881$new_n7805 +000 1 +001 1 +011 1 +.names $abc$24881$new_n7807 $abc$24881$new_n7722 o_mem_addr[4] o_mem_data[4] $abc$24881$new_n7822 $abc$24881$auto$rtlil.cc:2582:Mux$3529[4] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n7819 $abc$24881$new_n7728 $abc$24881$new_n7808 $abc$24881$new_n7821 o_mem_addr[4] $abc$24881$new_n7807 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n7809 $abc$24881$new_n7817 $abc$24881$new_n7689 $abc$24881$new_n7692 $abc$24881$new_n7811 $abc$24881$new_n7808 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6786 o_mem_data[31] o_mem_addr[4] $abc$24881$new_n7810 $abc$24881$new_n7809 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[3] o_mem_data[31] o_mem_addr[2] $abc$24881$new_n7810 +111 1 +.names o_mem_addr[4] o_mem_addr[3] $abc$24881$new_n7812 $abc$24881$new_n7815 $abc$24881$new_n7816 $abc$24881$new_n7811 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7813 $abc$24881$new_n7814 $abc$24881$new_n7812 +001 1 +011 1 +100 1 +101 1 +.names o_mem_addr[2] $abc$24881$new_n7703 $abc$24881$new_n7813 +00 1 +.names o_mem_addr[2] $abc$24881$new_n7698 $abc$24881$new_n7701 $abc$24881$new_n7814 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7696 $abc$24881$new_n7709 $abc$24881$new_n7815 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7707 $abc$24881$new_n7712 $abc$24881$new_n7816 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[3] $abc$24881$new_n7818 $abc$24881$new_n7817 +00 1 +.names o_mem_addr[2] $abc$24881$new_n6736 $abc$24881$new_n7717 $abc$24881$new_n7818 +010 1 +011 1 +100 1 +110 1 +.names $abc$24881$new_n7727 o_mem_addr[27] $abc$24881$new_n7820 $abc$24881$new_n7819 +000 1 +001 1 +010 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed $abc$24881$new_n7820 +10 1 +.names DIVIDE.thedivide.i_signed $abc$24881$new_n7726 $abc$24881$new_n7821 +11 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7824 $abc$24881$new_n7823 $abc$24881$new_n7721 $abc$24881$new_n7822 +1000 1 +1010 1 +1011 1 +.names o_mem_addr[4] o_mem_data[4] $abc$24881$new_n6699 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7823 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n6656 o_mem_addr[4] o_mem_data[4] $abc$24881$new_n9661 DIVIDE.thedivide.i_signed $abc$24881$new_n7824 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7827 $abc$24881$new_n7690 $abc$24881$new_n7835 $abc$24881$new_n7826 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7829 $abc$24881$new_n6785 $abc$24881$new_n7832 o_mem_addr[4] $abc$24881$new_n7827 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n6657 $abc$24881$new_n6787 $abc$24881$new_n7828 +10 1 +.names $abc$24881$new_n7831 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7830 $abc$24881$new_n7829 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names o_mem_addr[2] $abc$24881$new_n7735 $abc$24881$new_n7741 $abc$24881$new_n7830 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n7734 $abc$24881$new_n7737 $abc$24881$new_n7831 +1000 1 +1010 1 +1100 1 +1101 1 +.names o_mem_addr[3] $abc$24881$new_n7810 $abc$24881$new_n7833 $abc$24881$new_n7834 $abc$24881$new_n7832 +0010 1 +0011 1 +1000 1 +1010 1 +.names o_mem_addr[2] $abc$24881$new_n7742 $abc$24881$new_n7744 $abc$24881$new_n7833 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n6763 o_mem_data[31] $abc$24881$new_n7834 +0000 1 +0001 1 +1001 1 +1011 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7829 $abc$24881$new_n7836 $abc$24881$new_n7837 $abc$24881$new_n7835 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7833 o_mem_addr[2] $abc$24881$new_n7748 $abc$24881$new_n7836 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[3] $abc$24881$new_n7838 $abc$24881$new_n7837 +00 1 +.names o_mem_addr[2] $abc$24881$new_n7839 o_mem_addr[1] $abc$24881$new_n7751 $abc$24881$new_n7838 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7840 o_mem_data[3] o_mem_data[2] $abc$24881$new_n7839 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[5] o_mem_data[4] $abc$24881$new_n7840 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[4] o_mem_data[4] $abc$24881$new_n6699 $abc$24881$new_n7843 +001 1 +100 1 +101 1 +111 1 +.names o_mem_addr[5] o_mem_data[5] $abc$24881$new_n7845 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n7844 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names o_mem_addr[4] o_mem_data[4] $abc$24881$new_n9661 $abc$24881$new_n7845 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[26] o_mem_addr[5] $abc$24881$new_n7847 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n7863 $abc$24881$new_n7849 $abc$24881$new_n7867 $abc$24881$new_n7821 o_mem_addr[6] $abc$24881$auto$rtlil.cc:2582:Mux$3529[6] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7850 $abc$24881$new_n7690 $abc$24881$new_n7857 $abc$24881$new_n7849 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7851 $abc$24881$new_n6785 $abc$24881$new_n7854 o_mem_addr[4] $abc$24881$new_n7850 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n7853 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7852 $abc$24881$new_n7851 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names o_mem_addr[2] $abc$24881$new_n7772 $abc$24881$new_n7767 $abc$24881$new_n7852 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n7771 $abc$24881$new_n7774 $abc$24881$new_n7853 +1000 1 +1010 1 +1100 1 +1101 1 +.names o_mem_addr[3] $abc$24881$new_n7855 $abc$24881$new_n7856 $abc$24881$new_n7854 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7768 $abc$24881$new_n7765 $abc$24881$new_n7855 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[2] o_mem_data[31] $abc$24881$new_n7705 $abc$24881$new_n7856 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7851 $abc$24881$new_n7858 $abc$24881$new_n7860 $abc$24881$new_n7857 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7855 $abc$24881$new_n7859 $abc$24881$new_n7858 +010 1 +011 1 +100 1 +110 1 +.names o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n7705 $abc$24881$new_n7859 +000 1 +.names o_mem_addr[3] $abc$24881$new_n7861 $abc$24881$new_n7860 +00 1 +.names o_mem_addr[2] $abc$24881$new_n7780 $abc$24881$new_n7862 $abc$24881$new_n7861 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6737 o_mem_data[6] o_mem_data[5] $abc$24881$new_n7862 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7864 $abc$24881$new_n7727 $abc$24881$new_n7866 $abc$24881$new_n7721 $abc$24881$new_n7863 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n7865 o_mem_addr[6] o_mem_data[6] $abc$24881$new_n7722 $abc$24881$new_n7864 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +.names $abc$24881$new_n6656 o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6674 DIVIDE.thedivide.i_signed $abc$24881$new_n7865 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6698 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7866 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n7820 o_mem_addr[25] $abc$24881$new_n7867 +11 1 +.names $abc$24881$new_n7870 $abc$24881$new_n7820 o_mem_addr[24] $abc$24881$new_n7821 o_mem_addr[7] $abc$24881$new_n7869 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7871 $abc$24881$new_n7690 $abc$24881$new_n7874 $abc$24881$new_n7870 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n7828 $abc$24881$new_n6785 $abc$24881$new_n7872 $abc$24881$new_n7871 +100 1 +101 1 +111 1 +.names $abc$24881$new_n7873 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n6759 o_mem_data[31] $abc$24881$new_n7872 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n6753 $abc$24881$new_n6764 $abc$24881$new_n7873 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7873 $abc$24881$new_n7876 $abc$24881$new_n7875 $abc$24881$new_n7874 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n6759 $abc$24881$new_n7749 o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n7875 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6776 o_mem_addr[3] $abc$24881$new_n7877 $abc$24881$new_n7876 +100 1 +.names o_mem_addr[2] $abc$24881$new_n7878 $abc$24881$new_n7800 $abc$24881$new_n7877 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7840 o_mem_data[7] o_mem_data[6] $abc$24881$new_n7878 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6674 $abc$24881$new_n7881 +000 1 +001 1 +011 1 +101 1 +.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6698 $abc$24881$new_n7884 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n7828 o_mem_data[31] o_mem_addr[4] $abc$24881$new_n6658 o_mem_addr[3] $abc$24881$new_n7888 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[3] $abc$24881$new_n6733 $abc$24881$new_n7717 o_mem_addr[2] $abc$24881$new_n7891 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7896 $abc$24881$new_n7893 $abc$24881$new_n7895 $abc$24881$new_n7722 $abc$24881$new_n7892 +10000 1 +10001 1 +10010 1 +.names $abc$24881$new_n7721 $abc$24881$new_n7894 $abc$24881$new_n7723 o_mem_addr[8] o_mem_data[8] $abc$24881$new_n7893 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +.names $abc$24881$new_n6654 $abc$24881$new_n7895 $abc$24881$new_n6697 DIVIDE.thedivide.i_signed o_mem_addr[8] $abc$24881$new_n7894 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +11100 1 +11101 1 +.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n7895 +01 1 +10 1 +.names $abc$24881$new_n6656 o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6673 DIVIDE.thedivide.i_signed $abc$24881$new_n7896 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[23] o_mem_addr[8] $abc$24881$new_n7897 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n7899 o_mem_addr[9] $abc$24881$new_n7821 $abc$24881$new_n7727 $abc$24881$new_n7909 $abc$24881$auto$rtlil.cc:2582:Mux$3529[9] +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7900 $abc$24881$new_n7903 o_mem_addr[22] $abc$24881$new_n7820 $abc$24881$new_n7899 +00100 1 +00101 1 +00110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[4] $abc$24881$new_n7902 $abc$24881$new_n7901 o_mem_addr[3] $abc$24881$new_n7747 $abc$24881$new_n7900 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 $abc$24881$new_n7901 +10 1 +.names $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7743 o_mem_data[31] $abc$24881$new_n7902 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7904 $abc$24881$new_n7689 $abc$24881$new_n7905 $abc$24881$new_n7903 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7733 $abc$24881$new_n7740 $abc$24881$new_n7904 +10000 1 +10001 1 +11000 1 +11010 1 +.names o_mem_addr[3] $abc$24881$new_n7906 $abc$24881$new_n7751 o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7905 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n7839 $abc$24881$new_n7907 $abc$24881$new_n7906 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7908 o_mem_data[7] o_mem_data[6] $abc$24881$new_n7907 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[9] o_mem_data[8] $abc$24881$new_n7908 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7910 $abc$24881$new_n7913 o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7722 $abc$24881$new_n7909 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n7911 o_mem_data[9] o_mem_addr[9] $abc$24881$new_n7723 $abc$24881$new_n7910 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7912 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7911 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6697 $abc$24881$new_n7912 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n6656 o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7914 DIVIDE.thedivide.i_signed $abc$24881$new_n7913 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11110 1 +.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6673 $abc$24881$new_n7914 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7928 $abc$24881$new_n7916 $abc$24881$new_n7727 $abc$24881$new_n9694 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[10] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +.names $abc$24881$new_n7917 $abc$24881$new_n7919 $abc$24881$new_n7918 $abc$24881$new_n7689 $abc$24881$new_n7920 $abc$24881$new_n7916 +10000 1 +10001 1 +10011 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7901 o_mem_addr[4] o_mem_addr[3] $abc$24881$new_n7764 $abc$24881$new_n7917 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[4] $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7763 o_mem_data[31] $abc$24881$new_n7918 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7770 $abc$24881$new_n7766 $abc$24881$new_n7919 +10000 1 +10001 1 +11000 1 +11010 1 +.names o_mem_addr[3] $abc$24881$new_n7779 $abc$24881$new_n7921 $abc$24881$new_n7920 +001 1 +011 1 +100 1 +101 1 +.names o_mem_addr[2] $abc$24881$new_n7862 $abc$24881$new_n7922 $abc$24881$new_n7921 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6735 o_mem_data[10] o_mem_data[9] $abc$24881$new_n7922 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[10] o_mem_addr[21] $abc$24881$new_n7928 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7943 $abc$24881$new_n7930 $abc$24881$new_n7727 $abc$24881$new_n7937 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[11] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7931 $abc$24881$new_n7933 $abc$24881$new_n7689 $abc$24881$new_n7934 $abc$24881$new_n7930 +10000 1 +10001 1 +10011 1 +.names o_mem_addr[4] $abc$24881$new_n7932 $abc$24881$new_n7901 o_mem_addr[3] $abc$24881$new_n7797 $abc$24881$new_n7931 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6785 o_mem_addr[3] o_mem_addr[2] o_mem_data[31] $abc$24881$new_n6762 $abc$24881$new_n7932 +10000 1 +10010 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7790 $abc$24881$new_n7793 $abc$24881$new_n7933 +10000 1 +10001 1 +11000 1 +11010 1 +.names o_mem_addr[3] $abc$24881$new_n7935 $abc$24881$new_n7799 $abc$24881$new_n7934 +010 1 +011 1 +100 1 +110 1 +.names o_mem_addr[2] $abc$24881$new_n7878 $abc$24881$new_n7936 $abc$24881$new_n7935 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7908 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7936 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7938 $abc$24881$new_n7941 $abc$24881$new_n7721 $abc$24881$new_n7937 +100 1 +110 1 +111 1 +.names $abc$24881$new_n7939 o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7722 $abc$24881$new_n7938 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +.names $abc$24881$new_n6656 o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7940 DIVIDE.thedivide.i_signed $abc$24881$new_n7939 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6672 $abc$24881$new_n7940 +000 1 +001 1 +011 1 +101 1 +.names o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7942 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7941 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6696 $abc$24881$new_n7942 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[20] o_mem_addr[11] $abc$24881$new_n7943 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n7951 $abc$24881$new_n7946 $abc$24881$new_n7728 $abc$24881$new_n7692 $abc$24881$new_n7950 $abc$24881$new_n7945 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7947 $abc$24881$new_n6787 $abc$24881$new_n7690 $abc$24881$new_n7948 $abc$24881$new_n7691 $abc$24881$new_n7946 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +.names o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6785 o_mem_addr[2] o_mem_addr[3] $abc$24881$new_n7947 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7818 $abc$24881$new_n7949 $abc$24881$new_n7948 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6731 $abc$24881$new_n6734 $abc$24881$new_n7949 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7813 $abc$24881$new_n7814 $abc$24881$new_n7815 $abc$24881$new_n7950 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_addr[19] o_mem_addr[12] $abc$24881$new_n7951 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names $abc$24881$new_n7955 $abc$24881$new_n6702 $abc$24881$new_n6695 $abc$24881$new_n6653 $abc$24881$new_n7954 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n6654 o_mem_addr[12] o_mem_data[12] DIVIDE.thedivide.i_signed $abc$24881$new_n7955 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n7968 $abc$24881$new_n7728 $abc$24881$new_n7962 $abc$24881$new_n7959 $abc$24881$new_n7967 $abc$24881$new_n7958 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[4] $abc$24881$new_n7961 $abc$24881$new_n7901 $abc$24881$new_n6785 $abc$24881$new_n7960 $abc$24881$new_n7959 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7834 o_mem_data[31] o_mem_addr[2] $abc$24881$new_n7960 +0000 1 +0001 1 +0010 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n7748 $abc$24881$new_n7961 +000 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7689 $abc$24881$new_n7963 $abc$24881$new_n7962 +100 1 +101 1 +111 1 +.names o_mem_addr[3] $abc$24881$new_n7838 $abc$24881$new_n7964 $abc$24881$new_n7963 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7907 $abc$24881$new_n7965 $abc$24881$new_n7964 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7966 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7965 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[13] o_mem_data[12] $abc$24881$new_n7966 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7830 $abc$24881$new_n7833 $abc$24881$new_n7967 +10000 1 +10001 1 +11000 1 +11010 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[18] o_mem_addr[13] $abc$24881$new_n7968 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6671 $abc$24881$new_n7971 +000 1 +001 1 +010 1 +100 1 +.names o_mem_addr[13] o_mem_data[13] $abc$24881$new_n7973 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7972 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6695 $abc$24881$new_n7973 +000 1 +100 1 +101 1 +110 1 +.names $abc$24881$new_n7986 $abc$24881$new_n7975 $abc$24881$new_n7982 $abc$24881$new_n7985 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[14] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10110 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7976 $abc$24881$new_n7978 $abc$24881$new_n7689 $abc$24881$new_n7979 $abc$24881$new_n7975 +10000 1 +10001 1 +10011 1 +.names o_mem_addr[4] $abc$24881$new_n7977 $abc$24881$new_n7901 $abc$24881$new_n7859 o_mem_addr[3] $abc$24881$new_n7976 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7856 o_mem_data[31] $abc$24881$new_n7977 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7852 $abc$24881$new_n7855 $abc$24881$new_n7978 +10000 1 +10001 1 +11000 1 +11010 1 +.names o_mem_addr[3] $abc$24881$new_n7861 $abc$24881$new_n7980 $abc$24881$new_n7979 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7922 $abc$24881$new_n7981 $abc$24881$new_n7980 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6732 o_mem_data[14] o_mem_data[13] $abc$24881$new_n7981 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7983 $abc$24881$new_n7721 $abc$24881$new_n7722 $abc$24881$new_n6701 $abc$24881$new_n7982 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[14] o_mem_data[14] $abc$24881$new_n7984 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7983 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10001 1 +10011 1 +10111 1 +11101 1 +.names $abc$24881$new_n6704 $abc$24881$new_n6695 $abc$24881$new_n6703 $abc$24881$new_n6702 $abc$24881$new_n7984 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$24881$new_n6656 o_mem_addr[14] o_mem_data[14] $abc$24881$new_n6670 $abc$24881$new_n7724 $abc$24881$new_n7985 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[14] o_mem_addr[17] $abc$24881$new_n7986 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7988 $abc$24881$new_n8001 $abc$24881$new_n7728 $abc$24881$new_n7994 $abc$24881$auto$rtlil.cc:2582:Mux$3529[15] +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7989 $abc$24881$new_n7992 o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7722 $abc$24881$new_n7988 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n7990 o_mem_data[15] o_mem_addr[15] $abc$24881$new_n7723 $abc$24881$new_n7989 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7991 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7990 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n6706 $abc$24881$new_n6694 $abc$24881$new_n7991 +00 1 +.names $abc$24881$new_n6656 o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7993 DIVIDE.thedivide.i_signed $abc$24881$new_n7992 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11110 1 +.names o_mem_addr[14] o_mem_data[14] $abc$24881$new_n6670 $abc$24881$new_n7993 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7995 $abc$24881$new_n7997 $abc$24881$new_n7689 $abc$24881$new_n7998 $abc$24881$new_n7994 +0000 1 +0001 1 +0011 1 +.names $abc$24881$new_n7901 o_mem_addr[4] $abc$24881$new_n6752 $abc$24881$new_n7996 $abc$24881$new_n7995 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$24881$new_n7749 o_mem_addr[1] o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n7996 +1000 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6786 o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6752 $abc$24881$new_n7997 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7877 $abc$24881$new_n7999 $abc$24881$new_n7998 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7936 $abc$24881$new_n8000 $abc$24881$new_n7999 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7966 o_mem_data[15] o_mem_data[14] $abc$24881$new_n8000 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[16] o_mem_addr[15] $abc$24881$new_n8001 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8006 $abc$24881$new_n8011 $abc$24881$new_n8003 $abc$24881$new_n8012 $abc$24881$auto$rtlil.cc:2582:Mux$3529[16] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7721 $abc$24881$new_n8004 o_mem_addr[16] o_mem_data[16] $abc$24881$new_n7723 $abc$24881$new_n8003 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11111 1 +.names o_mem_addr[16] o_mem_data[16] $abc$24881$new_n8005 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8004 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7991 $abc$24881$new_n8005 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n9702 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[16] o_mem_addr[15] $abc$24881$new_n8006 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6656 o_mem_addr[16] o_mem_data[16] $abc$24881$new_n6669 DIVIDE.thedivide.i_signed $abc$24881$new_n8011 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7722 $abc$24881$new_n6705 $abc$24881$new_n8012 +11 1 +.names $abc$24881$new_n8014 $abc$24881$new_n8019 $abc$24881$new_n7820 o_mem_addr[14] $abc$24881$auto$rtlil.cc:2582:Mux$3529[17] +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7721 $abc$24881$new_n8015 $abc$24881$new_n8017 $abc$24881$new_n8014 +1000 1 +1001 1 +1101 1 +1111 1 +.names o_mem_addr[17] o_mem_data[17] $abc$24881$new_n8016 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n8015 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names o_mem_addr[16] o_mem_data[16] $abc$24881$new_n6669 $abc$24881$new_n8016 +000 1 +001 1 +010 1 +100 1 +.names o_mem_addr[17] o_mem_data[17] $abc$24881$new_n8018 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8017 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n6710 $abc$24881$new_n6693 $abc$24881$new_n8018 +00 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8020 $abc$24881$new_n8025 o_mem_data[17] $abc$24881$new_n7821 $abc$24881$new_n8019 +00000 1 +00001 1 +00010 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n8021 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7906 $abc$24881$new_n8022 $abc$24881$new_n8020 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7746 $abc$24881$new_n7750 $abc$24881$new_n8021 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n7965 $abc$24881$new_n8023 $abc$24881$new_n8022 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8024 o_mem_data[15] o_mem_data[14] $abc$24881$new_n8023 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[17] o_mem_data[16] $abc$24881$new_n8024 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7739 o_mem_data[31] $abc$24881$new_n8025 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n6786 o_mem_addr[4] $abc$24881$new_n8026 +10 1 +.names $abc$24881$new_n8031 $abc$24881$new_n8028 $abc$24881$new_n8038 $abc$24881$auto$rtlil.cc:2582:Mux$3529[18] +000 1 +001 1 +011 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8029 $abc$24881$new_n7721 $abc$24881$new_n6708 $abc$24881$new_n7722 $abc$24881$new_n8028 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[18] o_mem_data[18] $abc$24881$new_n8030 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8029 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[17] o_mem_data[17] $abc$24881$new_n8018 $abc$24881$new_n8030 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n8032 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[18] o_mem_addr[13] $abc$24881$new_n8031 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8033 $abc$24881$new_n8037 $abc$24881$new_n8032 +000 1 +010 1 +011 1 +.names $abc$24881$new_n8034 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7777 $abc$24881$new_n7778 $abc$24881$new_n8033 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7690 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7921 $abc$24881$new_n8035 $abc$24881$new_n8034 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names o_mem_addr[2] $abc$24881$new_n7981 $abc$24881$new_n8036 $abc$24881$new_n8035 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] $abc$24881$new_n6730 $abc$24881$new_n6750 $abc$24881$new_n8036 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6657 $abc$24881$new_n8026 $abc$24881$new_n6658 $abc$24881$new_n7762 o_mem_data[31] $abc$24881$new_n8037 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n6656 o_mem_addr[18] o_mem_data[18] $abc$24881$new_n6668 DIVIDE.thedivide.i_signed $abc$24881$new_n8038 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n8045 $abc$24881$new_n8043 $abc$24881$new_n8040 o_mem_addr[12] $abc$24881$new_n7820 $abc$24881$auto$rtlil.cc:2582:Mux$3529[19] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +11011 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8041 $abc$24881$new_n7721 $abc$24881$new_n6709 $abc$24881$new_n7722 $abc$24881$new_n8040 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n6653 $abc$24881$new_n8042 o_mem_addr[19] $abc$24881$new_n6654 o_mem_data[19] $abc$24881$new_n8041 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6709 o_mem_data[18] o_mem_addr[18] $abc$24881$new_n8030 $abc$24881$new_n8042 +0000 1 +0100 1 +0101 1 +0110 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$24881$new_n6656 o_mem_addr[19] o_mem_data[19] $abc$24881$new_n8044 DIVIDE.thedivide.i_signed $abc$24881$new_n8043 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[18] o_mem_data[18] $abc$24881$new_n6668 $abc$24881$new_n8044 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8046 $abc$24881$new_n8050 o_mem_data[19] $abc$24881$new_n7821 $abc$24881$new_n8045 +00000 1 +00001 1 +00010 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n8047 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7935 $abc$24881$new_n8048 $abc$24881$new_n8046 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7796 $abc$24881$new_n7798 $abc$24881$new_n8047 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n8000 $abc$24881$new_n8049 $abc$24881$new_n8048 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8024 o_mem_data[19] o_mem_data[18] $abc$24881$new_n8049 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7792 o_mem_data[31] $abc$24881$new_n8050 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n6656 o_mem_addr[20] o_mem_data[20] $abc$24881$new_n6667 DIVIDE.thedivide.i_signed $abc$24881$new_n8056 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8026 o_mem_data[31] $abc$24881$new_n7812 $abc$24881$new_n7810 $abc$24881$new_n8058 +0000 1 +0001 1 +0010 1 +0011 1 +1010 1 +1110 1 +.names o_mem_addr[2] $abc$24881$new_n6729 $abc$24881$new_n6749 $abc$24881$new_n8062 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[20] o_mem_addr[11] $abc$24881$new_n8063 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8065 $abc$24881$new_n8078 $abc$24881$new_n8071 $abc$24881$auto$rtlil.cc:2582:Mux$3529[21] +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n8066 $abc$24881$new_n8068 o_mem_addr[21] o_mem_data[21] $abc$24881$new_n7722 $abc$24881$new_n8065 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names $abc$24881$new_n6656 o_mem_addr[21] o_mem_data[21] $abc$24881$new_n8067 DIVIDE.thedivide.i_signed $abc$24881$new_n8066 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11110 1 +.names o_mem_addr[20] o_mem_data[20] $abc$24881$new_n6667 $abc$24881$new_n8067 +000 1 +001 1 +010 1 +100 1 +.names $abc$24881$new_n8070 o_mem_addr[21] o_mem_data[21] $abc$24881$new_n8069 $abc$24881$new_n6653 $abc$24881$new_n8068 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n6711 o_mem_addr[20] $abc$24881$new_n6692 o_mem_data[20] $abc$24881$new_n8069 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n6654 o_mem_addr[21] o_mem_data[21] DIVIDE.thedivide.i_signed $abc$24881$new_n8070 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8072 $abc$24881$new_n6657 $abc$24881$new_n6658 $abc$24881$new_n8077 $abc$24881$new_n8071 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n8073 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7964 $abc$24881$new_n8074 $abc$24881$new_n8072 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7836 $abc$24881$new_n7837 $abc$24881$new_n8073 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n8023 $abc$24881$new_n8075 $abc$24881$new_n8074 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8076 o_mem_data[19] o_mem_data[18] $abc$24881$new_n8075 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[21] o_mem_data[20] $abc$24881$new_n8076 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n8026 $abc$24881$new_n7832 o_mem_data[31] $abc$24881$new_n8077 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[21] o_mem_addr[10] $abc$24881$new_n8078 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n8080 $abc$24881$new_n8085 $abc$24881$new_n7820 o_mem_addr[9] $abc$24881$auto$rtlil.cc:2582:Mux$3529[22] +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$24881$new_n8084 $abc$24881$new_n8081 $abc$24881$new_n8082 $abc$24881$new_n7721 $abc$24881$new_n8080 +1000 1 +1010 1 +1011 1 +.names $abc$24881$new_n6656 o_mem_addr[22] o_mem_data[22] $abc$24881$new_n6666 DIVIDE.thedivide.i_signed $abc$24881$new_n8081 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[22] o_mem_data[22] $abc$24881$new_n8083 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8082 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n6715 $abc$24881$new_n6691 $abc$24881$new_n8083 +00 1 +.names $abc$24881$new_n7727 o_mem_data[22] o_mem_addr[22] $abc$24881$new_n7722 $abc$24881$new_n8084 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8086 $abc$24881$new_n8090 o_mem_data[22] $abc$24881$new_n7821 $abc$24881$new_n8085 +00000 1 +00001 1 +00010 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n8087 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7980 $abc$24881$new_n8088 $abc$24881$new_n8086 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7858 $abc$24881$new_n7860 $abc$24881$new_n8087 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n8036 $abc$24881$new_n8089 $abc$24881$new_n8088 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6748 o_mem_data[20] o_mem_data[19] $abc$24881$new_n8089 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7854 o_mem_data[31] $abc$24881$new_n8090 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8092 $abc$24881$new_n8104 $abc$24881$new_n8098 $abc$24881$auto$rtlil.cc:2582:Mux$3529[23] +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n8093 $abc$24881$new_n8096 o_mem_addr[23] o_mem_data[23] $abc$24881$new_n7722 $abc$24881$new_n8092 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n8094 o_mem_data[23] o_mem_addr[23] $abc$24881$new_n7723 $abc$24881$new_n8093 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names o_mem_addr[23] o_mem_data[23] $abc$24881$new_n8095 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8094 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[22] o_mem_data[22] $abc$24881$new_n8083 $abc$24881$new_n8095 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n6656 o_mem_addr[23] o_mem_data[23] $abc$24881$new_n8097 DIVIDE.thedivide.i_signed $abc$24881$new_n8096 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11110 1 +.names o_mem_addr[22] o_mem_data[22] $abc$24881$new_n6666 $abc$24881$new_n8097 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7728 $abc$24881$new_n6657 $abc$24881$new_n8099 $abc$24881$new_n8103 $abc$24881$new_n8098 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names $abc$24881$new_n8100 o_mem_addr[4] $abc$24881$new_n7876 $abc$24881$new_n7875 $abc$24881$new_n6776 $abc$24881$new_n8099 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7999 $abc$24881$new_n8101 $abc$24881$new_n8100 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names o_mem_addr[2] $abc$24881$new_n8049 $abc$24881$new_n8102 $abc$24881$new_n8101 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8076 o_mem_data[23] o_mem_data[22] $abc$24881$new_n8102 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 o_mem_addr[3] o_mem_data[31] $abc$24881$new_n6759 $abc$24881$new_n8103 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[23] o_mem_addr[8] $abc$24881$new_n8104 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names o_mem_addr[24] o_mem_data[24] $abc$24881$new_n8109 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8108 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n6717 $abc$24881$new_n6690 $abc$24881$new_n8109 +00 1 +.names $abc$24881$new_n6656 o_mem_addr[24] o_mem_data[24] $abc$24881$new_n6665 DIVIDE.thedivide.i_signed $abc$24881$new_n8110 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8113 o_mem_data[24] $abc$24881$new_n7821 $abc$24881$new_n8112 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n8114 $abc$24881$new_n8115 $abc$24881$new_n8116 o_mem_addr[4] $abc$24881$new_n7891 $abc$24881$new_n8113 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7828 $abc$24881$new_n6744 $abc$24881$new_n6785 $abc$24881$new_n7700 o_mem_data[31] $abc$24881$new_n8114 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 $abc$24881$new_n6744 $abc$24881$new_n7700 $abc$24881$new_n8115 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n7691 o_mem_addr[3] $abc$24881$new_n6728 $abc$24881$new_n6746 $abc$24881$new_n8116 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n8123 $abc$24881$new_n8118 $abc$24881$new_n7721 $abc$24881$new_n8121 $abc$24881$auto$rtlil.cc:2582:Mux$3529[25] +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8119 o_mem_addr[25] o_mem_data[25] $abc$24881$new_n7722 $abc$24881$new_n8118 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +.names $abc$24881$new_n6656 o_mem_addr[25] o_mem_data[25] $abc$24881$new_n8120 DIVIDE.thedivide.i_signed $abc$24881$new_n8119 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[24] o_mem_data[24] $abc$24881$new_n6665 $abc$24881$new_n8120 +000 1 +001 1 +010 1 +100 1 +.names o_mem_addr[25] o_mem_data[25] $abc$24881$new_n8122 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8121 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[24] o_mem_data[24] $abc$24881$new_n8109 $abc$24881$new_n8122 +000 1 +100 1 +101 1 +110 1 +.names $abc$24881$new_n8131 $abc$24881$new_n8124 $abc$24881$new_n7728 $abc$24881$new_n8123 +101 1 +110 1 +111 1 +.names $abc$24881$new_n8125 $abc$24881$new_n7691 $abc$24881$new_n7690 $abc$24881$new_n8127 $abc$24881$new_n8128 $abc$24881$new_n8124 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n6657 $abc$24881$new_n8126 $abc$24881$new_n8026 $abc$24881$new_n7743 o_mem_addr[3] $abc$24881$new_n8125 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6658 o_mem_data[31] $abc$24881$new_n6786 $abc$24881$new_n6744 $abc$24881$new_n8126 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n6776 $abc$24881$new_n7905 $abc$24881$new_n6744 $abc$24881$new_n7747 $abc$24881$new_n8127 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8022 $abc$24881$new_n8075 $abc$24881$new_n8129 $abc$24881$new_n8128 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8130 o_mem_data[23] o_mem_data[22] $abc$24881$new_n8129 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[25] o_mem_data[24] $abc$24881$new_n8130 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[25] o_mem_addr[6] $abc$24881$new_n8131 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n8133 $abc$24881$new_n8143 $abc$24881$new_n7728 $abc$24881$new_n8138 $abc$24881$auto$rtlil.cc:2582:Mux$3529[26] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$24881$new_n8134 $abc$24881$new_n7727 $abc$24881$new_n8136 $abc$24881$new_n7721 $abc$24881$new_n8133 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n8135 o_mem_addr[26] o_mem_data[26] $abc$24881$new_n7722 $abc$24881$new_n8134 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6664 $abc$24881$new_n7724 $abc$24881$new_n6655 $abc$24881$new_n8135 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01100 1 +01101 1 +10000 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n8137 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8136 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10001 1 +10011 1 +10111 1 +11101 1 +.names $abc$24881$new_n6719 $abc$24881$new_n6689 $abc$24881$new_n8137 +00 1 +.names $abc$24881$new_n8139 $abc$24881$new_n7690 $abc$24881$new_n8140 $abc$24881$new_n7691 $abc$24881$new_n8141 $abc$24881$new_n8138 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6744 $abc$24881$new_n6786 o_mem_data[31] $abc$24881$new_n7763 $abc$24881$new_n8139 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7920 o_mem_addr[3] $abc$24881$new_n7764 $abc$24881$new_n8140 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8035 $abc$24881$new_n8089 $abc$24881$new_n8142 $abc$24881$new_n8141 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6743 o_mem_data[24] o_mem_data[23] $abc$24881$new_n8142 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[26] o_mem_addr[5] $abc$24881$new_n8143 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8150 $abc$24881$new_n8145 $abc$24881$new_n8148 $abc$24881$auto$rtlil.cc:2582:Mux$3529[27] +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n7722 o_mem_addr[27] o_mem_data[27] $abc$24881$new_n7721 $abc$24881$new_n8146 $abc$24881$new_n8145 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[27] o_mem_data[27] $abc$24881$new_n8147 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8146 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n8137 $abc$24881$new_n8147 +000 1 +100 1 +101 1 +110 1 +.names $abc$24881$new_n6656 o_mem_addr[27] o_mem_data[27] $abc$24881$new_n8149 DIVIDE.thedivide.i_signed $abc$24881$new_n8148 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6664 $abc$24881$new_n8149 +000 1 +001 1 +010 1 +100 1 +.names $abc$24881$new_n8156 $abc$24881$new_n8151 $abc$24881$new_n7728 $abc$24881$new_n8150 +101 1 +110 1 +111 1 +.names $abc$24881$new_n8152 $abc$24881$new_n7690 $abc$24881$new_n8153 $abc$24881$new_n7691 $abc$24881$new_n8154 $abc$24881$new_n8151 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n8126 $abc$24881$new_n7794 $abc$24881$new_n6786 $abc$24881$new_n6744 $abc$24881$new_n8152 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7934 o_mem_addr[3] $abc$24881$new_n7797 $abc$24881$new_n8153 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8048 $abc$24881$new_n8102 $abc$24881$new_n8155 $abc$24881$new_n8154 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8130 o_mem_data[27] o_mem_data[26] $abc$24881$new_n8155 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[27] o_mem_addr[4] $abc$24881$new_n8156 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7721 $abc$24881$new_n8160 $abc$24881$new_n6653 $abc$24881$new_n8159 $abc$24881$new_n8158 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6721 $abc$24881$new_n6688 $abc$24881$new_n8159 +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[28] $abc$24881$new_n6654 DIVIDE.thedivide.i_signed o_mem_data[28] $abc$24881$new_n8160 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6663 $abc$24881$new_n7724 $abc$24881$new_n6655 $abc$24881$new_n8161 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01100 1 +01101 1 +10000 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +.names $abc$24881$new_n8166 $abc$24881$new_n8164 $abc$24881$new_n6658 $abc$24881$new_n8167 $abc$24881$new_n7691 $abc$24881$new_n8163 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +11001 1 +11101 1 +.names $abc$24881$new_n8026 $abc$24881$new_n8165 o_mem_data[31] o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8164 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names $abc$24881$new_n7813 o_mem_addr[3] $abc$24881$new_n8165 +10 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7948 $abc$24881$new_n8165 $abc$24881$new_n8166 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8062 $abc$24881$new_n6741 $abc$24881$new_n6747 $abc$24881$new_n8167 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6656 o_mem_addr[29] o_mem_data[29] $abc$24881$new_n8172 DIVIDE.thedivide.i_signed $abc$24881$new_n8171 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6663 $abc$24881$new_n8172 +000 1 +001 1 +010 1 +100 1 +.names $abc$24881$new_n7721 $abc$24881$new_n6653 $abc$24881$new_n8174 $abc$24881$new_n8175 $abc$24881$new_n8176 $abc$24881$new_n8173 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n6721 $abc$24881$new_n6688 o_mem_addr[28] o_mem_data[28] $abc$24881$new_n8174 +0010 1 +0100 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names o_mem_addr[29] o_mem_data[29] $abc$24881$new_n8175 +00 1 +11 1 +.names o_mem_addr[29] $abc$24881$new_n6654 DIVIDE.thedivide.i_signed o_mem_data[29] $abc$24881$new_n8176 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7960 o_mem_data[31] $abc$24881$new_n8179 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7691 o_mem_addr[3] $abc$24881$new_n8074 $abc$24881$new_n8182 $abc$24881$new_n8181 +1001 1 +1011 1 +1110 1 +1111 1 +.names o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n8129 $abc$24881$new_n8183 $abc$24881$new_n8184 $abc$24881$new_n8182 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[27] o_mem_data[26] $abc$24881$new_n8183 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[0] o_mem_data[29] o_mem_data[28] $abc$24881$new_n8184 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[29] o_mem_addr[2] $abc$24881$new_n8185 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7722 $abc$24881$new_n8175 $abc$24881$new_n8186 +10 1 +.names $abc$24881$new_n8191 $abc$24881$new_n8190 $abc$24881$new_n8199 $abc$24881$new_n7721 $abc$24881$new_n8188 $abc$24881$auto$rtlil.cc:2582:Mux$3529[30] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names DIVIDE.thedivide.i_signed o_mem_addr[30] $abc$24881$new_n6654 $abc$24881$new_n8189 o_mem_data[30] $abc$24881$new_n8188 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n6683 $abc$24881$new_n6722 $abc$24881$new_n6687 $abc$24881$new_n8189 +001 1 +010 1 +011 1 +100 1 +.names $abc$24881$new_n6655 $abc$24881$new_n6683 $abc$24881$new_n6662 $abc$24881$new_n8190 +100 1 +111 1 +.names $abc$24881$new_n8198 $abc$24881$new_n8192 $abc$24881$new_n7728 $abc$24881$new_n8191 +101 1 +110 1 +111 1 +.names $abc$24881$new_n8194 $abc$24881$new_n8193 $abc$24881$new_n8195 o_mem_addr[4] $abc$24881$new_n7979 $abc$24881$new_n8192 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 $abc$24881$new_n7859 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n8193 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6657 $abc$24881$new_n8126 $abc$24881$new_n8026 $abc$24881$new_n7856 o_mem_addr[3] $abc$24881$new_n8194 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7691 o_mem_addr[3] $abc$24881$new_n8088 $abc$24881$new_n8196 $abc$24881$new_n8195 +1001 1 +1011 1 +1110 1 +1111 1 +.names o_mem_addr[2] $abc$24881$new_n8142 $abc$24881$new_n8197 $abc$24881$new_n8196 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6742 o_mem_data[30] o_mem_data[29] $abc$24881$new_n8197 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[30] o_mem_addr[1] $abc$24881$new_n8198 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7727 o_mem_data[30] o_mem_addr[30] $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n8199 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11100 1 +11101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n9720 $abc$24881$new_n8207 $abc$24881$new_n8201 $abc$24881$new_n8213 $abc$24881$auto$rtlil.cc:2582:Mux$3529[31] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6650 $abc$24881$new_n7724 $abc$24881$new_n6682 $abc$24881$new_n6683 $abc$24881$new_n6662 $abc$24881$new_n8201 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10011 1 +.names $abc$24881$new_n6650 o_mem_addr[30] o_mem_data[30] $abc$24881$new_n6722 $abc$24881$new_n6687 $abc$24881$new_n8203 +00000 1 +00100 1 +00101 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$abc$24881$new_n3763 regset[12][19] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3757 regset[12][20] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3752 regset[12][21] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3747 regset[12][22] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3741 regset[12][23] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3735 regset[12][24] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3730 regset[12][25] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3725 regset[12][26] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3719 regset[12][27] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3714 regset[12][28] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3708 regset[12][29] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3702 regset[12][30] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n6568 regset[12][31] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4083 $abc$24881$new_n3993 i_clear_cache o_dbg_stall $abc$24881$procmux$2463_Y +0010 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9727 GEN_UHALT_PHASE.r_uhalt_phase GEN_IHALT_PHASE.r_ihalt_phase $0\genblk43.SETDBG.r_dbg_reg[31:0][1] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8517 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][1] regset[28][1] $abc$24881$new_n8515 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] $abc$24881$new_n8516 +10 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][1] regset[30][1] $abc$24881$new_n8517 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8521 $abc$24881$new_n8520 $abc$24881$new_n8519 $abc$24881$new_n8522 $abc$24881$new_n8518 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][1] regset[16][1] $abc$24881$new_n8519 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][1] regset[18][1] $abc$24881$new_n8520 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][1] regset[20][1] $abc$24881$new_n8521 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][1] regset[22][1] $abc$24881$new_n8522 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8524 regset[27][1] regset[26][1] $abc$24881$new_n8523 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][1] regset[24][1] $abc$24881$new_n8524 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8526 $abc$24881$new_n6930 $abc$24881$new_n8525 +11 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8526 +10 1 +.names $abc$24881$new_n8530 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][1] regset[4][1] $abc$24881$new_n8529 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][1] regset[6][1] $abc$24881$new_n8530 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8532 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][1] regset[0][1] $abc$24881$new_n8531 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][1] regset[2][1] $abc$24881$new_n8532 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8534 regset[11][1] regset[10][1] $abc$24881$new_n8533 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][1] regset[8][1] $abc$24881$new_n8534 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8536 regset[15][1] regset[14][1] $abc$24881$new_n8535 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[13][1] regset[12][1] $abc$24881$new_n8536 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8542 regset[23][2] regset[22][2] $abc$24881$new_n8541 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][2] regset[20][2] $abc$24881$new_n8542 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8544 regset[19][2] regset[18][2] $abc$24881$new_n8543 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][2] regset[16][2] $abc$24881$new_n8544 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8546 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][2] regset[28][2] $abc$24881$new_n8545 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][2] regset[30][2] $abc$24881$new_n8546 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8548 regset[27][2] regset[26][2] $abc$24881$new_n8547 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][2] regset[24][2] $abc$24881$new_n8548 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8550 $abc$24881$new_n8555 $abc$24881$new_n8558 $abc$24881$new_n8549 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n8551 $abc$24881$new_n8553 $abc$24881$new_n8550 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8552 regset[7][2] regset[6][2] $abc$24881$new_n8551 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][2] regset[4][2] $abc$24881$new_n8552 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8554 regset[3][2] regset[2][2] $abc$24881$new_n8553 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][2] regset[0][2] $abc$24881$new_n8554 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8556 regset[11][2] regset[10][2] $abc$24881$new_n8555 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][2] regset[8][2] $abc$24881$new_n8556 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][2] regset[13][2] regset[12][2] $abc$24881$new_n8558 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n8582 $abc$24881$new_n9734 $abc$24881$new_n9738 $0\genblk43.SETDBG.r_dbg_reg[31:0][3] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8567 regset[19][3] regset[18][3] $abc$24881$new_n8566 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][3] regset[16][3] $abc$24881$new_n8567 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8569 regset[27][3] regset[26][3] $abc$24881$new_n8568 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][3] regset[24][3] $abc$24881$new_n8569 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][3] regset[2][3] $abc$24881$new_n8575 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8577 regset[7][3] regset[6][3] $abc$24881$new_n8576 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][3] regset[4][3] $abc$24881$new_n8577 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[9][3] regset[8][3] $abc$24881$new_n8579 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8583 i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n8582 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[3] ipc[3] $abc$24881$new_n8583 +1001 1 +1011 1 +1110 1 +1111 1 +.names i_dbg_rreg[1] $abc$24881$new_n6930 $abc$24881$new_n8584 +11 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n8586 SET_USER_PC.r_upc[4] ipc[4] $0\genblk43.SETDBG.r_dbg_reg[31:0][4] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8525 i_dbg_rreg[4] sleep $abc$24881$new_n8587 $abc$24881$new_n8597 $abc$24881$new_n8586 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n8588 i_dbg_rreg[3] $abc$24881$new_n8590 $abc$24881$new_n8595 i_dbg_rreg[2] $abc$24881$new_n8587 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8589 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][4] regset[28][4] $abc$24881$new_n8588 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][4] regset[30][4] $abc$24881$new_n8589 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8593 $abc$24881$new_n8592 $abc$24881$new_n8591 $abc$24881$new_n8594 $abc$24881$new_n8590 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][4] regset[16][4] $abc$24881$new_n8591 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][4] regset[18][4] $abc$24881$new_n8592 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][4] regset[20][4] $abc$24881$new_n8593 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][4] regset[22][4] $abc$24881$new_n8594 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8596 regset[27][4] regset[26][4] $abc$24881$new_n8595 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][4] regset[24][4] $abc$24881$new_n8596 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8598 $abc$24881$new_n8603 $abc$24881$new_n8606 $abc$24881$new_n8597 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n8601 $abc$24881$new_n8599 i_dbg_rreg[2] $abc$24881$new_n8598 +000 1 +001 1 +010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8600 regset[7][4] regset[6][4] $abc$24881$new_n8599 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][4] regset[4][4] $abc$24881$new_n8600 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8602 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][4] regset[0][4] $abc$24881$new_n8601 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][4] regset[2][4] $abc$24881$new_n8602 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8604 regset[11][4] regset[10][4] $abc$24881$new_n8603 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][4] regset[8][4] $abc$24881$new_n8604 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][4] regset[13][4] regset[12][4] $abc$24881$new_n8606 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n8611 $abc$24881$new_n8614 $abc$24881$new_n8613 $abc$24881$new_n8610 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8612 regset[3][0] regset[2][0] $abc$24881$new_n8611 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][0] regset[0][0] $abc$24881$new_n8612 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[5][0] regset[4][0] $abc$24881$new_n8613 +0001 1 +0011 1 +1010 1 +1011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] regset[7][0] regset[6][0] $abc$24881$new_n8614 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n8616 i_dbg_rreg[0] $abc$24881$new_n8516 regset[13][0] regset[12][0] $abc$24881$new_n8615 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] $abc$24881$new_n6930 i_dbg_rreg[0] regset[15][0] regset[14][0] $abc$24881$new_n8616 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8618 regset[11][0] regset[10][0] $abc$24881$new_n8617 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][0] regset[8][0] $abc$24881$new_n8618 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8622 regset[23][0] regset[22][0] $abc$24881$new_n8621 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][0] regset[20][0] $abc$24881$new_n8622 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8624 regset[19][0] regset[18][0] $abc$24881$new_n8623 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][0] regset[16][0] $abc$24881$new_n8624 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8626 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][0] regset[28][0] $abc$24881$new_n8625 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][0] regset[30][0] $abc$24881$new_n8626 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8628 regset[27][0] regset[26][0] $abc$24881$new_n8627 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][0] regset[24][0] $abc$24881$new_n8628 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n8630 SET_USER_PC.r_upc[5] ipc[5] $0\genblk43.SETDBG.r_dbg_reg[31:0][5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n8641 $abc$24881$new_n8631 $abc$24881$new_n8630 +0000 1 +0010 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8632 $abc$24881$new_n8637 $abc$24881$new_n8640 $abc$24881$new_n8631 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n8635 $abc$24881$new_n8633 i_dbg_rreg[2] $abc$24881$new_n8632 +000 1 +001 1 +011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8634 regset[3][5] regset[2][5] $abc$24881$new_n8633 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][5] regset[0][5] $abc$24881$new_n8634 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8636 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][5] regset[4][5] $abc$24881$new_n8635 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][5] regset[6][5] $abc$24881$new_n8636 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8638 regset[11][5] regset[10][5] $abc$24881$new_n8637 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][5] regset[8][5] $abc$24881$new_n8638 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][5] regset[13][5] regset[12][5] $abc$24881$new_n8640 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8642 i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n8647 $abc$24881$new_n8649 $abc$24881$new_n8641 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8643 $abc$24881$new_n8645 $abc$24881$new_n8642 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8644 regset[27][5] regset[26][5] $abc$24881$new_n8643 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][5] regset[24][5] $abc$24881$new_n8644 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8646 regset[31][5] regset[30][5] $abc$24881$new_n8645 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][5] regset[28][5] $abc$24881$new_n8646 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8648 regset[19][5] regset[18][5] $abc$24881$new_n8647 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][5] regset[16][5] $abc$24881$new_n8648 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8650 regset[23][5] regset[22][5] $abc$24881$new_n8649 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][5] regset[20][5] $abc$24881$new_n8650 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n8653 +10 1 +.names i_dbg_rreg[3] $abc$24881$new_n8657 $abc$24881$new_n8655 $abc$24881$new_n6930 $abc$24881$new_n8660 $abc$24881$new_n8654 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8656 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][6] regset[20][6] $abc$24881$new_n8655 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][6] regset[22][6] $abc$24881$new_n8656 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8658 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][6] regset[16][6] $abc$24881$new_n8657 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][6] regset[18][6] $abc$24881$new_n8658 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[29][6] regset[28][6] $abc$24881$new_n8660 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8662 regset[27][6] regset[26][6] $abc$24881$new_n8661 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][6] regset[24][6] $abc$24881$new_n8662 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8668 $abc$24881$new_n8667 $abc$24881$new_n8666 $abc$24881$new_n8669 $abc$24881$new_n8665 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[1][6] regset[0][6] $abc$24881$new_n8666 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][6] regset[2][6] $abc$24881$new_n8667 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[5][6] regset[4][6] $abc$24881$new_n8668 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][6] regset[6][6] $abc$24881$new_n8669 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8671 regset[11][6] regset[10][6] $abc$24881$new_n8670 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][6] regset[8][6] $abc$24881$new_n8671 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][6] regset[13][6] regset[12][6] $abc$24881$new_n8673 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8679 regset[3][7] regset[2][7] $abc$24881$new_n8678 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][7] regset[0][7] $abc$24881$new_n8679 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8681 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][7] regset[4][7] $abc$24881$new_n8680 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][7] regset[6][7] $abc$24881$new_n8681 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8684 regset[11][7] regset[10][7] $abc$24881$new_n8683 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][7] regset[8][7] $abc$24881$new_n8684 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] regset[13][7] regset[12][7] $abc$24881$new_n8686 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8689 $abc$24881$new_n8697 $abc$24881$new_n8694 $abc$24881$new_n8688 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] $abc$24881$new_n8692 $abc$24881$new_n8691 $abc$24881$new_n8690 $abc$24881$new_n8693 $abc$24881$new_n8689 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[21][7] regset[20][7] $abc$24881$new_n8690 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][7] regset[22][7] $abc$24881$new_n8691 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][7] regset[16][7] $abc$24881$new_n8692 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][7] regset[18][7] $abc$24881$new_n8693 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8695 regset[27][7] regset[26][7] $abc$24881$new_n8694 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][7] regset[24][7] $abc$24881$new_n8695 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[29][7] regset[28][7] $abc$24881$new_n8697 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[4] i_dbg_rreg[0] $abc$24881$new_n8584 SET_TRAP_N_UBREAK.r_ubreak break_en $abc$24881$new_n8698 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n8700 i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y SET_USER_PC.r_upc[8] ipc[8] $0\genblk43.SETDBG.r_dbg_reg[31:0][8] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n8721 i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n8701 $abc$24881$new_n9754 $abc$24881$new_n8700 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8702 $abc$24881$new_n8707 $abc$24881$new_n8710 $abc$24881$new_n8701 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n8703 $abc$24881$new_n8705 $abc$24881$new_n8702 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8704 regset[7][8] regset[6][8] $abc$24881$new_n8703 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][8] regset[4][8] $abc$24881$new_n8704 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8706 regset[3][8] regset[2][8] $abc$24881$new_n8705 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][8] regset[0][8] $abc$24881$new_n8706 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8708 regset[11][8] regset[10][8] $abc$24881$new_n8707 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][8] regset[8][8] $abc$24881$new_n8708 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][8] regset[13][8] regset[12][8] $abc$24881$new_n8710 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8714 regset[23][8] regset[22][8] $abc$24881$new_n8713 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][8] regset[20][8] $abc$24881$new_n8714 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8720 regset[27][8] regset[26][8] $abc$24881$new_n8719 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][8] regset[24][8] $abc$24881$new_n8720 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[4] i_dbg_rreg[0] $abc$24881$new_n8584 SET_USER_ILLEGAL_INSN.r_ill_err_u ill_err_i $abc$24881$new_n8721 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n8723 i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y SET_USER_PC.r_upc[9] ipc[9] $0\genblk43.SETDBG.r_dbg_reg[31:0][9] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n8724 $abc$24881$new_n8734 $abc$24881$new_n8653 $abc$24881$new_n8525 SET_TRAP_N_UBREAK.r_trap $abc$24881$new_n8723 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n8725 $abc$24881$new_n8732 i_dbg_rreg[3] $abc$24881$new_n8730 i_dbg_rreg[2] $abc$24881$new_n8724 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8726 i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n8727 $abc$24881$new_n8729 $abc$24881$new_n8725 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +.names $abc$24881$new_n8584 i_dbg_rreg[0] i_dbg_rreg[4] $abc$24881$new_n8726 +001 1 +011 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8728 regset[11][9] regset[10][9] $abc$24881$new_n8727 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][9] regset[8][9] $abc$24881$new_n8728 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][9] regset[13][9] regset[12][9] $abc$24881$new_n8729 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8731 regset[3][9] regset[2][9] $abc$24881$new_n8730 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][9] regset[0][9] $abc$24881$new_n8731 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8733 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][9] regset[4][9] $abc$24881$new_n8732 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][9] regset[6][9] $abc$24881$new_n8733 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8740 i_dbg_rreg[3] $abc$24881$new_n8735 $abc$24881$new_n8742 i_dbg_rreg[2] $abc$24881$new_n8734 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8736 $abc$24881$new_n8738 i_dbg_rreg[2] $abc$24881$new_n8735 +000 1 +001 1 +011 1 +.names $abc$24881$new_n8737 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][9] regset[20][9] $abc$24881$new_n8736 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][9] regset[22][9] $abc$24881$new_n8737 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8739 regset[19][9] regset[18][9] $abc$24881$new_n8738 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][9] regset[16][9] $abc$24881$new_n8739 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8741 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][9] regset[28][9] $abc$24881$new_n8740 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][9] regset[30][9] $abc$24881$new_n8741 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8743 regset[27][9] regset[26][9] $abc$24881$new_n8742 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][9] regset[24][9] $abc$24881$new_n8743 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n8745 SET_USER_PC.r_upc[10] ipc[10] $0\genblk43.SETDBG.r_dbg_reg[31:0][10] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8766 i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n9758 $abc$24881$new_n8756 $abc$24881$new_n8745 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][10] regset[18][10] $abc$24881$new_n8749 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8751 regset[23][10] regset[22][10] $abc$24881$new_n8750 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][10] regset[20][10] $abc$24881$new_n8751 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[25][10] regset[24][10] $abc$24881$new_n8753 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8757 $abc$24881$new_n8765 $abc$24881$new_n8762 $abc$24881$new_n8756 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n8760 $abc$24881$new_n8758 $abc$24881$new_n8757 +000 1 +.names $abc$24881$new_n8759 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][10] regset[0][10] $abc$24881$new_n8758 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][10] regset[2][10] $abc$24881$new_n8759 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n8761 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][10] regset[4][10] $abc$24881$new_n8760 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][10] regset[6][10] $abc$24881$new_n8761 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8763 regset[11][10] regset[10][10] $abc$24881$new_n8762 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][10] regset[8][10] $abc$24881$new_n8763 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][10] regset[13][10] regset[12][10] $abc$24881$new_n8765 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] i_dbg_rreg[0] $abc$24881$new_n8584 SET_USER_BUSERR.r_ubus_err_flag ibus_err_flag $abc$24881$new_n8766 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[4] $abc$24881$new_n8770 $abc$24881$new_n8775 $abc$24881$new_n8777 i_dbg_rreg[3] $abc$24881$new_n8769 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8771 $abc$24881$new_n8773 $abc$24881$new_n8770 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8772 regset[27][11] regset[26][11] $abc$24881$new_n8771 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][11] regset[24][11] $abc$24881$new_n8772 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8774 regset[31][11] regset[30][11] $abc$24881$new_n8773 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][11] regset[28][11] $abc$24881$new_n8774 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8776 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][11] regset[16][11] $abc$24881$new_n8775 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][11] regset[18][11] $abc$24881$new_n8776 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n8778 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][11] regset[20][11] $abc$24881$new_n8777 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][11] regset[22][11] $abc$24881$new_n8778 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8782 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][11] regset[4][11] $abc$24881$new_n8781 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][11] regset[6][11] $abc$24881$new_n8782 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8784 regset[3][11] regset[2][11] $abc$24881$new_n8783 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][11] regset[0][11] $abc$24881$new_n8784 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8786 regset[11][11] regset[10][11] $abc$24881$new_n8785 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][11] regset[8][11] $abc$24881$new_n8786 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[4] $abc$24881$new_n8788 $abc$24881$new_n6930 $abc$24881$new_n6931 regset[15][11] $abc$24881$new_n8787 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][11] regset[13][11] regset[12][11] $abc$24881$new_n8788 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8584 i_dbg_rreg[4] DIVERR.USER_DIVERR.r_udiv_err_flag DIVERR.r_idiv_err_flag $abc$24881$new_n8789 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n8795 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][12] regset[0][12] $abc$24881$new_n8794 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][12] regset[2][12] $abc$24881$new_n8795 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8797 regset[7][12] regset[6][12] $abc$24881$new_n8796 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][12] regset[4][12] $abc$24881$new_n8797 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8799 regset[11][12] regset[10][12] $abc$24881$new_n8798 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][12] regset[8][12] $abc$24881$new_n8799 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] regset[13][12] regset[12][12] $abc$24881$new_n8801 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8804 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][12] regset[20][12] $abc$24881$new_n8803 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][12] regset[22][12] $abc$24881$new_n8804 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8806 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][12] regset[16][12] $abc$24881$new_n8805 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][12] regset[18][12] $abc$24881$new_n8806 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8808 $abc$24881$new_n8810 $abc$24881$new_n8807 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8809 regset[27][12] regset[26][12] $abc$24881$new_n8808 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][12] regset[24][12] $abc$24881$new_n8809 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8811 regset[31][12] regset[30][12] $abc$24881$new_n8810 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][12] regset[28][12] $abc$24881$new_n8811 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8817 regset[23][13] regset[22][13] $abc$24881$new_n8816 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][13] regset[20][13] $abc$24881$new_n8817 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8819 regset[19][13] regset[18][13] $abc$24881$new_n8818 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][13] regset[16][13] $abc$24881$new_n8819 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8822 regset[27][13] regset[26][13] $abc$24881$new_n8821 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][13] regset[24][13] $abc$24881$new_n8822 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8516 i_dbg_rreg[0] regset[29][13] regset[28][13] $abc$24881$new_n8823 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8826 $abc$24881$new_n8831 $abc$24881$new_n8833 $abc$24881$new_n8825 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n8827 $abc$24881$new_n8829 $abc$24881$new_n8826 +010 1 +011 1 +101 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8828 regset[3][13] regset[2][13] $abc$24881$new_n8827 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][13] regset[0][13] $abc$24881$new_n8828 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8830 regset[7][13] regset[6][13] $abc$24881$new_n8829 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][13] regset[4][13] $abc$24881$new_n8830 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8832 regset[11][13] regset[10][13] $abc$24881$new_n8831 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][13] regset[8][13] $abc$24881$new_n8832 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][13] regset[13][13] regset[12][13] $abc$24881$new_n8833 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8841 regset[27][14] regset[26][14] $abc$24881$new_n8840 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][14] regset[24][14] $abc$24881$new_n8841 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8843 regset[31][14] regset[30][14] $abc$24881$new_n8842 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][14] regset[28][14] $abc$24881$new_n8843 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8845 regset[19][14] regset[18][14] $abc$24881$new_n8844 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][14] regset[16][14] $abc$24881$new_n8845 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8847 regset[23][14] regset[22][14] $abc$24881$new_n8846 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][14] regset[20][14] $abc$24881$new_n8847 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8849 $abc$24881$new_n8857 $abc$24881$new_n8854 $abc$24881$new_n8848 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8850 $abc$24881$new_n8852 i_dbg_rreg[2] $abc$24881$new_n8849 +000 1 +001 1 +011 1 +.names $abc$24881$new_n8851 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][14] regset[4][14] $abc$24881$new_n8850 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][14] regset[6][14] $abc$24881$new_n8851 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8853 regset[3][14] regset[2][14] $abc$24881$new_n8852 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][14] regset[0][14] $abc$24881$new_n8853 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8855 regset[11][14] regset[10][14] $abc$24881$new_n8854 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][14] regset[8][14] $abc$24881$new_n8855 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][14] regset[13][14] regset[12][14] $abc$24881$new_n8857 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8864 regset[7][15] regset[6][15] $abc$24881$new_n8863 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][15] regset[4][15] $abc$24881$new_n8864 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8866 regset[3][15] regset[2][15] $abc$24881$new_n8865 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][15] regset[0][15] $abc$24881$new_n8866 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8868 regset[11][15] regset[10][15] $abc$24881$new_n8867 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][15] regset[8][15] $abc$24881$new_n8868 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][15] regset[13][15] regset[12][15] $abc$24881$new_n8870 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8872 $abc$24881$new_n8877 $abc$24881$new_n8879 $abc$24881$new_n8871 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8875 $abc$24881$new_n8874 $abc$24881$new_n8873 $abc$24881$new_n8876 $abc$24881$new_n8872 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[21][15] regset[20][15] $abc$24881$new_n8873 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][15] regset[22][15] $abc$24881$new_n8874 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][15] regset[16][15] $abc$24881$new_n8875 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][15] regset[18][15] $abc$24881$new_n8876 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8878 regset[27][15] regset[26][15] $abc$24881$new_n8877 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][15] regset[24][15] $abc$24881$new_n8878 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8880 regset[31][15] regset[30][15] $abc$24881$new_n8879 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][15] regset[28][15] $abc$24881$new_n8880 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n8903 $abc$24881$new_n8883 $abc$24881$new_n8893 $0\genblk43.SETDBG.r_dbg_reg[31:0][16] +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n8884 i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n8889 $abc$24881$new_n8891 $abc$24881$new_n8883 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8885 $abc$24881$new_n8887 $abc$24881$new_n8884 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8886 regset[11][16] regset[10][16] $abc$24881$new_n8885 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][16] regset[8][16] $abc$24881$new_n8886 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8888 regset[15][16] regset[14][16] $abc$24881$new_n8887 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[13][16] regset[12][16] $abc$24881$new_n8888 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8890 regset[3][16] regset[2][16] $abc$24881$new_n8889 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][16] regset[0][16] $abc$24881$new_n8890 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8892 regset[7][16] regset[6][16] $abc$24881$new_n8891 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][16] regset[4][16] $abc$24881$new_n8892 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8894 $abc$24881$new_n8899 $abc$24881$new_n8901 $abc$24881$new_n8893 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8897 $abc$24881$new_n8896 $abc$24881$new_n8895 $abc$24881$new_n8898 $abc$24881$new_n8894 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[21][16] regset[20][16] $abc$24881$new_n8895 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][16] regset[22][16] $abc$24881$new_n8896 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][16] regset[16][16] $abc$24881$new_n8897 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][16] regset[18][16] $abc$24881$new_n8898 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8900 regset[27][16] regset[26][16] $abc$24881$new_n8899 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][16] regset[24][16] $abc$24881$new_n8900 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8902 regset[31][16] regset[30][16] $abc$24881$new_n8901 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][16] regset[28][16] $abc$24881$new_n8902 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[4] SET_USER_PC.r_upc[16] ipc[16] $abc$24881$new_n8903 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8908 regset[11][17] regset[10][17] $abc$24881$new_n8907 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][17] regset[8][17] $abc$24881$new_n8908 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8910 regset[15][17] regset[14][17] $abc$24881$new_n8909 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[13][17] regset[12][17] $abc$24881$new_n8910 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8912 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][17] regset[0][17] $abc$24881$new_n8911 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][17] regset[2][17] $abc$24881$new_n8912 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n8914 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][17] regset[4][17] $abc$24881$new_n8913 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][17] regset[6][17] $abc$24881$new_n8914 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8916 $abc$24881$new_n8921 $abc$24881$new_n8923 $abc$24881$new_n8915 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8919 $abc$24881$new_n8918 $abc$24881$new_n8917 $abc$24881$new_n8920 $abc$24881$new_n8916 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][17] regset[16][17] $abc$24881$new_n8917 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][17] regset[18][17] $abc$24881$new_n8918 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][17] regset[20][17] $abc$24881$new_n8919 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][17] regset[22][17] $abc$24881$new_n8920 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8922 regset[27][17] regset[26][17] $abc$24881$new_n8921 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][17] regset[24][17] $abc$24881$new_n8922 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8924 regset[31][17] regset[30][17] $abc$24881$new_n8923 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][17] regset[28][17] $abc$24881$new_n8924 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8930 regset[19][18] regset[18][18] $abc$24881$new_n8929 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][18] regset[16][18] $abc$24881$new_n8930 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8932 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][18] regset[20][18] $abc$24881$new_n8931 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][18] regset[22][18] $abc$24881$new_n8932 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8934 regset[27][18] regset[26][18] $abc$24881$new_n8933 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][18] regset[24][18] $abc$24881$new_n8934 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8936 regset[31][18] regset[30][18] $abc$24881$new_n8935 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][18] regset[28][18] $abc$24881$new_n8936 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8938 $abc$24881$new_n8946 $abc$24881$new_n8943 $abc$24881$new_n8937 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n8939 $abc$24881$new_n8941 $abc$24881$new_n8938 +0000 1 +0001 1 +1000 1 +1010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8940 regset[3][18] regset[2][18] $abc$24881$new_n8939 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][18] regset[0][18] $abc$24881$new_n8940 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8942 regset[7][18] regset[6][18] $abc$24881$new_n8941 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][18] regset[4][18] $abc$24881$new_n8942 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8944 regset[11][18] regset[10][18] $abc$24881$new_n8943 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][18] regset[8][18] $abc$24881$new_n8944 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][18] regset[13][18] regset[12][18] $abc$24881$new_n8946 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8955 regset[23][19] regset[22][19] $abc$24881$new_n8954 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][19] regset[20][19] $abc$24881$new_n8955 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8959 regset[27][19] regset[26][19] $abc$24881$new_n8958 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][19] regset[24][19] $abc$24881$new_n8959 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] $abc$24881$new_n6930 i_dbg_rreg[0] regset[15][19] regset[14][19] $abc$24881$new_n8963 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8966 regset[7][19] regset[6][19] $abc$24881$new_n8965 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][19] regset[4][19] $abc$24881$new_n8966 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8968 regset[3][19] regset[2][19] $abc$24881$new_n8967 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][19] regset[0][19] $abc$24881$new_n8968 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8970 regset[11][19] regset[10][19] $abc$24881$new_n8969 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][19] regset[8][19] $abc$24881$new_n8970 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8976 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][20] regset[20][20] $abc$24881$new_n8975 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][20] regset[22][20] $abc$24881$new_n8976 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8978 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][20] regset[16][20] $abc$24881$new_n8977 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][20] regset[18][20] $abc$24881$new_n8978 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8983 regset[27][20] regset[26][20] $abc$24881$new_n8982 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][20] regset[24][20] $abc$24881$new_n8983 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8988 $abc$24881$new_n8986 i_dbg_rreg[2] $abc$24881$new_n8985 +000 1 +001 1 +010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8987 regset[7][20] regset[6][20] $abc$24881$new_n8986 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][20] regset[4][20] $abc$24881$new_n8987 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8989 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][20] regset[0][20] $abc$24881$new_n8988 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][20] regset[2][20] $abc$24881$new_n8989 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8991 regset[11][20] regset[10][20] $abc$24881$new_n8990 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][20] regset[8][20] $abc$24881$new_n8991 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][20] regset[13][20] regset[12][20] $abc$24881$new_n8993 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9002 regset[11][21] regset[10][21] $abc$24881$new_n9001 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][21] regset[8][21] $abc$24881$new_n9002 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9007 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][21] regset[20][21] $abc$24881$new_n9006 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][21] regset[22][21] $abc$24881$new_n9007 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9010 regset[27][21] regset[26][21] $abc$24881$new_n9009 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][21] regset[24][21] $abc$24881$new_n9010 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9013 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][21] regset[4][21] $abc$24881$new_n9012 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][21] regset[6][21] $abc$24881$new_n9013 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9015 regset[3][21] regset[2][21] $abc$24881$new_n9014 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][21] regset[0][21] $abc$24881$new_n9015 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[29][21] regset[28][21] $abc$24881$new_n9018 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9040 $abc$24881$new_n9020 $abc$24881$new_n9030 $0\genblk43.SETDBG.r_dbg_reg[31:0][22] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9021 $abc$24881$new_n9026 $abc$24881$new_n9028 $abc$24881$new_n9020 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n9022 $abc$24881$new_n9024 $abc$24881$new_n9021 +000 1 +001 1 +100 1 +110 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9023 regset[19][22] regset[18][22] $abc$24881$new_n9022 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][22] regset[16][22] $abc$24881$new_n9023 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9025 regset[23][22] regset[22][22] $abc$24881$new_n9024 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][22] regset[20][22] $abc$24881$new_n9025 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9027 regset[27][22] regset[26][22] $abc$24881$new_n9026 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][22] regset[24][22] $abc$24881$new_n9027 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9029 regset[31][22] regset[30][22] $abc$24881$new_n9028 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][22] regset[28][22] $abc$24881$new_n9029 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9031 $abc$24881$new_n9036 $abc$24881$new_n9038 $abc$24881$new_n9030 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n9032 $abc$24881$new_n9034 $abc$24881$new_n9031 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9033 regset[7][22] regset[6][22] $abc$24881$new_n9032 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][22] regset[4][22] $abc$24881$new_n9033 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9035 regset[3][22] regset[2][22] $abc$24881$new_n9034 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][22] regset[0][22] $abc$24881$new_n9035 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9037 regset[11][22] regset[10][22] $abc$24881$new_n9036 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][22] regset[8][22] $abc$24881$new_n9037 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9039 regset[15][22] regset[14][22] $abc$24881$new_n9038 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[13][22] regset[12][22] $abc$24881$new_n9039 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[4] SET_USER_PC.r_upc[22] ipc[22] $abc$24881$new_n9040 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9046 regset[23][23] regset[22][23] $abc$24881$new_n9045 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][23] regset[20][23] $abc$24881$new_n9046 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9048 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][23] regset[16][23] $abc$24881$new_n9047 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][23] regset[18][23] $abc$24881$new_n9048 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n9050 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][23] regset[28][23] $abc$24881$new_n9049 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][23] regset[30][23] $abc$24881$new_n9050 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9052 regset[27][23] regset[26][23] $abc$24881$new_n9051 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][23] regset[24][23] $abc$24881$new_n9052 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9054 $abc$24881$new_n9059 $abc$24881$new_n9061 $abc$24881$new_n9053 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n9057 $abc$24881$new_n9055 i_dbg_rreg[2] $abc$24881$new_n9054 +000 1 +001 1 +010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9056 regset[7][23] regset[6][23] $abc$24881$new_n9055 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][23] regset[4][23] $abc$24881$new_n9056 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9058 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][23] regset[0][23] $abc$24881$new_n9057 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][23] regset[2][23] $abc$24881$new_n9058 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9060 regset[11][23] regset[10][23] $abc$24881$new_n9059 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][23] regset[8][23] $abc$24881$new_n9060 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][23] regset[13][23] regset[12][23] $abc$24881$new_n9061 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[11][24] regset[9][24] regset[8][24] $abc$24881$new_n9068 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9070 regset[7][24] regset[6][24] $abc$24881$new_n9069 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][24] regset[4][24] $abc$24881$new_n9070 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[1][24] regset[0][24] $abc$24881$new_n9072 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9076 regset[23][24] regset[22][24] $abc$24881$new_n9075 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][24] regset[20][24] $abc$24881$new_n9076 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9078 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][24] regset[16][24] $abc$24881$new_n9077 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][24] regset[18][24] $abc$24881$new_n9078 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n9080 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][24] regset[28][24] $abc$24881$new_n9079 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][24] regset[30][24] $abc$24881$new_n9080 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9082 regset[27][24] regset[26][24] $abc$24881$new_n9081 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][24] regset[24][24] $abc$24881$new_n9082 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9084 SET_USER_PC.r_upc[25] ipc[25] $0\genblk43.SETDBG.r_dbg_reg[31:0][25] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9095 $abc$24881$new_n9085 $abc$24881$new_n9084 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n9086 i_dbg_rreg[3] $abc$24881$new_n9088 $abc$24881$new_n9093 i_dbg_rreg[2] $abc$24881$new_n9085 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9087 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][25] regset[28][25] $abc$24881$new_n9086 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][25] regset[30][25] $abc$24881$new_n9087 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9091 $abc$24881$new_n9090 $abc$24881$new_n9089 $abc$24881$new_n9092 $abc$24881$new_n9088 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][25] regset[16][25] $abc$24881$new_n9089 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][25] regset[18][25] $abc$24881$new_n9090 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][25] regset[20][25] $abc$24881$new_n9091 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][25] regset[22][25] $abc$24881$new_n9092 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9094 regset[27][25] regset[26][25] $abc$24881$new_n9093 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][25] regset[24][25] $abc$24881$new_n9094 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9096 $abc$24881$new_n9101 $abc$24881$new_n9103 $abc$24881$new_n9095 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n9097 $abc$24881$new_n9099 $abc$24881$new_n9096 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9098 regset[7][25] regset[6][25] $abc$24881$new_n9097 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][25] regset[4][25] $abc$24881$new_n9098 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9100 regset[3][25] regset[2][25] $abc$24881$new_n9099 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][25] regset[0][25] $abc$24881$new_n9100 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9102 regset[11][25] regset[10][25] $abc$24881$new_n9101 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][25] regset[8][25] $abc$24881$new_n9102 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][25] regset[13][25] regset[12][25] $abc$24881$new_n9103 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9109 regset[3][26] regset[2][26] $abc$24881$new_n9108 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][26] regset[0][26] $abc$24881$new_n9109 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9113 regset[11][26] regset[10][26] $abc$24881$new_n9112 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][26] regset[8][26] $abc$24881$new_n9113 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][26] regset[18][26] $abc$24881$new_n9119 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n9121 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][26] regset[20][26] $abc$24881$new_n9120 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][26] regset[22][26] $abc$24881$new_n9121 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][26] regset[24][26] $abc$24881$new_n9123 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8653 i_dbg_rreg[0] $abc$24881$new_n8516 regset[13][27] regset[12][27] $abc$24881$new_n9129 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9133 $abc$24881$new_n9132 $abc$24881$new_n9131 $abc$24881$new_n9134 $abc$24881$new_n9130 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[1][27] regset[0][27] $abc$24881$new_n9131 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][27] regset[2][27] $abc$24881$new_n9132 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[5][27] regset[4][27] $abc$24881$new_n9133 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][27] regset[6][27] $abc$24881$new_n9134 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9136 regset[11][27] regset[10][27] $abc$24881$new_n9135 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][27] regset[8][27] $abc$24881$new_n9136 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9140 regset[23][27] regset[22][27] $abc$24881$new_n9139 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][27] regset[20][27] $abc$24881$new_n9140 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9142 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][27] regset[16][27] $abc$24881$new_n9141 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][27] regset[18][27] $abc$24881$new_n9142 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9145 regset[27][27] regset[26][27] $abc$24881$new_n9144 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][27] regset[24][27] $abc$24881$new_n9145 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9154 regset[27][28] regset[26][28] $abc$24881$new_n9153 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][28] regset[24][28] $abc$24881$new_n9154 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9156 regset[31][28] regset[30][28] $abc$24881$new_n9155 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][28] regset[28][28] $abc$24881$new_n9156 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9158 regset[19][28] regset[18][28] $abc$24881$new_n9157 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][28] regset[16][28] $abc$24881$new_n9158 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9160 regset[23][28] regset[22][28] $abc$24881$new_n9159 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][28] regset[20][28] $abc$24881$new_n9160 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9166 regset[3][28] regset[2][28] $abc$24881$new_n9165 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][28] regset[0][28] $abc$24881$new_n9166 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9168 regset[11][28] regset[10][28] $abc$24881$new_n9167 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][28] regset[8][28] $abc$24881$new_n9168 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9177 regset[19][29] regset[18][29] $abc$24881$new_n9176 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][29] regset[16][29] $abc$24881$new_n9177 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9179 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][29] regset[20][29] $abc$24881$new_n9178 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][29] regset[22][29] $abc$24881$new_n9179 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n9181 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][29] regset[28][29] $abc$24881$new_n9180 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][29] regset[30][29] $abc$24881$new_n9181 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9183 regset[27][29] regset[26][29] $abc$24881$new_n9182 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][29] regset[24][29] $abc$24881$new_n9183 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9185 $abc$24881$new_n9190 $abc$24881$new_n9192 $abc$24881$new_n9184 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n9188 $abc$24881$new_n9186 i_dbg_rreg[2] $abc$24881$new_n9185 +000 1 +001 1 +010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9187 regset[7][29] regset[6][29] $abc$24881$new_n9186 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][29] regset[4][29] $abc$24881$new_n9187 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9189 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][29] regset[0][29] $abc$24881$new_n9188 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][29] regset[2][29] $abc$24881$new_n9189 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9191 regset[11][29] regset[10][29] $abc$24881$new_n9190 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][29] regset[8][29] $abc$24881$new_n9191 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][29] regset[13][29] regset[12][29] $abc$24881$new_n9192 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] $abc$24881$new_n9199 $abc$24881$new_n9198 $abc$24881$new_n9197 $abc$24881$new_n9200 $abc$24881$new_n9196 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[21][30] regset[20][30] $abc$24881$new_n9197 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][30] regset[22][30] $abc$24881$new_n9198 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][30] regset[16][30] $abc$24881$new_n9199 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][30] regset[18][30] $abc$24881$new_n9200 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9202 regset[27][30] regset[26][30] $abc$24881$new_n9201 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][30] regset[24][30] $abc$24881$new_n9202 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9209 $abc$24881$new_n9208 $abc$24881$new_n9207 $abc$24881$new_n9210 $abc$24881$new_n9206 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[5][30] regset[4][30] $abc$24881$new_n9207 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][30] regset[6][30] $abc$24881$new_n9208 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][30] regset[0][30] $abc$24881$new_n9209 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][30] regset[2][30] $abc$24881$new_n9210 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9212 regset[11][30] regset[10][30] $abc$24881$new_n9211 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][30] regset[8][30] $abc$24881$new_n9212 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9217 SET_USER_PC.r_upc[31] ipc[31] $0\genblk43.SETDBG.r_dbg_reg[31:0][31] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9218 $abc$24881$new_n9228 $abc$24881$new_n9217 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9219 i_dbg_rreg[3] $abc$24881$new_n9221 $abc$24881$new_n9226 i_dbg_rreg[2] $abc$24881$new_n9218 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9220 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][31] regset[28][31] $abc$24881$new_n9219 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][31] regset[30][31] $abc$24881$new_n9220 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9224 $abc$24881$new_n9223 $abc$24881$new_n9222 $abc$24881$new_n9225 $abc$24881$new_n9221 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][31] regset[16][31] $abc$24881$new_n9222 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][31] regset[18][31] $abc$24881$new_n9223 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][31] regset[20][31] $abc$24881$new_n9224 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][31] regset[22][31] $abc$24881$new_n9225 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9227 regset[27][31] regset[26][31] $abc$24881$new_n9226 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][31] regset[24][31] $abc$24881$new_n9227 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9229 $abc$24881$new_n9234 $abc$24881$new_n9236 $abc$24881$new_n9228 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9232 $abc$24881$new_n9231 $abc$24881$new_n9230 $abc$24881$new_n9233 $abc$24881$new_n9229 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[1][31] regset[0][31] $abc$24881$new_n9230 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][31] regset[2][31] $abc$24881$new_n9231 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[5][31] regset[4][31] $abc$24881$new_n9232 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][31] regset[6][31] $abc$24881$new_n9233 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9235 regset[11][31] regset[10][31] $abc$24881$new_n9234 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][31] regset[8][31] $abc$24881$new_n9235 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][31] regset[13][31] regset[12][31] $abc$24881$new_n9236 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_halt r_halted $abc$24881$new_n4042 $abc$24881$new_n9238 $abc$24881$procmux$2428_Y +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_pf_valid $abc$24881$new_n6855 instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$new_n9238 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3863 regset[11][0] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3958 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9240 +1110 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3859 regset[11][1] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3853 regset[11][2] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3848 regset[11][3] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3843 regset[11][4] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3838 regset[11][5] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3832 regset[11][6] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3825 regset[11][7] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3820 regset[11][8] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3815 regset[11][9] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3810 regset[11][10] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3805 regset[11][11] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3800 regset[11][12] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3795 regset[11][13] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3790 regset[11][14] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3784 regset[11][15] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3779 regset[11][16] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3774 regset[11][17] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3769 regset[11][18] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3763 regset[11][19] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3757 regset[11][20] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3752 regset[11][21] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3747 regset[11][22] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3741 regset[11][23] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3735 regset[11][24] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3730 regset[11][25] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3725 regset[11][26] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3719 regset[11][27] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3714 regset[11][28] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3708 regset[11][29] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3702 regset[11][30] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n6568 regset[11][31] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4042 i_bus_err i_halt GEN_PENDING_INTERRUPT.r_pending_interrupt $abc$24881$new_n6958 $abc$24881$new_n9274 +10000 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3863 regset[10][0] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n7143 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9277 +1110 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3859 regset[10][1] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3853 regset[10][2] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3848 regset[10][3] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3843 regset[10][4] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3838 regset[10][5] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3832 regset[10][6] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3825 regset[10][7] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3820 regset[10][8] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3815 regset[10][9] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3810 regset[10][10] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3805 regset[10][11] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3800 regset[10][12] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3795 regset[10][13] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3790 regset[10][14] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3784 regset[10][15] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3779 regset[10][16] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3774 regset[10][17] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3769 regset[10][18] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3763 regset[10][19] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3757 regset[10][20] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3752 regset[10][21] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3747 regset[10][22] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3741 regset[10][23] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3735 regset[10][24] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3730 regset[10][25] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3725 regset[10][26] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3719 regset[10][27] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3714 regset[10][28] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3708 regset[10][29] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3702 regset[10][30] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n6568 regset[10][31] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[31] +001 1 +011 1 +100 1 +101 1 +.names alu_ce $abc$24881$new_n6871 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y $abc$24881$procmux$2659_Y +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3863 regset[9][0] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n7177 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9311 +1110 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3859 regset[9][1] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3853 regset[9][2] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3848 regset[9][3] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3843 regset[9][4] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3838 regset[9][5] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3832 regset[9][6] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3825 regset[9][7] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3820 regset[9][8] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3815 regset[9][9] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3810 regset[9][10] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3805 regset[9][11] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3800 regset[9][12] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3795 regset[9][13] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3790 regset[9][14] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3784 regset[9][15] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3779 regset[9][16] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3774 regset[9][17] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3769 regset[9][18] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3763 regset[9][19] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3757 regset[9][20] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3752 regset[9][21] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3747 regset[9][22] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3741 regset[9][23] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3735 regset[9][24] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3730 regset[9][25] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3725 regset[9][26] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3719 regset[9][27] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3714 regset[9][28] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3708 regset[9][29] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3702 regset[9][30] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n6568 regset[9][31] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9344 GEN_OP_STALL.r_cc_invalid_for_dcd i_mem_rdbusy DIVIDE.thedivide.o_busy $abc$24881$procmux$2728_Y +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5375 $abc$24881$new_n9345 alu_ce mem_ce $abc$24881$new_n9344 +1001 1 +1010 1 +1011 1 +.names $abc$24881$new_n4048 SET_GIE.r_gie o_mem_reg[4] o_mem_reg[0] op_wF $abc$24881$new_n9345 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11110 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3863 regset[8][0] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n7027 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9347 +1110 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3859 regset[8][1] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3853 regset[8][2] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3848 regset[8][3] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3843 regset[8][4] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3838 regset[8][5] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3832 regset[8][6] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3825 regset[8][7] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3820 regset[8][8] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3815 regset[8][9] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3810 regset[8][10] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3805 regset[8][11] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3800 regset[8][12] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3795 regset[8][13] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3790 regset[8][14] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3784 regset[8][15] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3779 regset[8][16] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3774 regset[8][17] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3769 regset[8][18] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3763 regset[8][19] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3757 regset[8][20] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3752 regset[8][21] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3747 regset[8][22] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3741 regset[8][23] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3735 regset[8][24] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3730 regset[8][25] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3725 regset[8][26] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3719 regset[8][27] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3714 regset[8][28] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3708 regset[8][29] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3702 regset[8][30] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n6568 regset[8][31] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4083 $abc$24881$new_n3995 i_clear_cache o_dbg_stall $abc$24881$procmux$2755_Y +0010 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[1] +01 1 +10 1 +.names DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[2] +011 1 +100 1 +101 1 +110 1 +.names DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names DIVIDE.thedivide.r_bit[4] DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.X[0] +0 1 +.names $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][0] $abc$24881$memory$auto$proc_rom.cc:150:do_switch$1988$rdmux[0][1][0]$b$3899[6] +0 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[29] $abc$24881$new_n3672 o_mem_data[30] $abc$24881$new_n9386 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9386 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[30] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22566 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[27] $abc$24881$new_n3673 o_mem_data[28] $abc$24881$new_n9388 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9388 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[28] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22570 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[25] $abc$24881$new_n3674 o_mem_data[26] $abc$24881$new_n9390 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9390 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[26] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22574 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.r_dividend[21] o_mem_data[23] $abc$24881$new_n9392 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[23] DIVIDE.thedivide.pre_sign $abc$24881$new_n9392 $abc$24881$new_n3676 $abc$24881$auto$rtlil.cc:2693:MuxGate$22580 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[21] $abc$24881$new_n3676 o_mem_data[22] $abc$24881$new_n9394 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9394 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22582 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.r_dividend[17] o_mem_data[19] $abc$24881$new_n9396 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[19] DIVIDE.thedivide.pre_sign $abc$24881$new_n9396 $abc$24881$new_n3678 $abc$24881$auto$rtlil.cc:2693:MuxGate$22588 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[17] $abc$24881$new_n3678 o_mem_data[18] $abc$24881$new_n9398 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9398 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22590 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[13] $abc$24881$new_n3681 o_mem_data[14] $abc$24881$new_n9400 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9400 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[14] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22598 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[6] $abc$24881$new_n3687 o_mem_data[7] $abc$24881$new_n9402 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9402 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[7] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22612 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[4] $abc$24881$new_n3688 o_mem_data[5] $abc$24881$new_n9404 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[5] DIVIDE.thedivide.pre_sign $abc$24881$new_n9404 DIVIDE.thedivide.r_dividend[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22616 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4062 alu_reg[0] instruction_decoder.o_dcdB[0] alu_reg[1] instruction_decoder.o_dcdB[1] $abc$24881$new_n9406 +10000 1 +10011 1 +11100 1 +11111 1 +.names GEN_OP_WR.r_op_wR o_mem_reg[0] instruction_decoder.o_dcdB[0] o_mem_reg[1] instruction_decoder.o_dcdB[1] $abc$24881$new_n9410 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$24881$new_n9410 o_mem_reg[2] instruction_decoder.o_dcdB[2] o_mem_reg[3] instruction_decoder.o_dcdB[3] $abc$24881$new_n9411 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$24881$new_n9411 o_mem_reg[4] instruction_decoder.o_dcdB[4] $abc$24881$new_n9412 +100 1 +111 1 +.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$new_n4113 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] pf_pc[22] $abc$24881$new_n9413 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4087 $abc$24881$new_n9413 $abc$24881$new_n4094 $abc$24881$new_n4025 SET_USER_PC.r_upc[22] $abc$24881$new_n9414 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4160 $abc$24881$new_n4103 $abc$24881$new_n9414 ipc[22] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22818 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4025 pf_pc[14] $abc$24881$new_n4099 pf_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n9416 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n9416 $abc$24881$new_n4116 $abc$24881$new_n4025 SET_USER_PC.r_upc[14] $abc$24881$new_n9417 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4198 $abc$24881$new_n4103 $abc$24881$new_n9417 ipc[14] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22834 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n4117 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n4099 $abc$24881$new_n9419 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4087 $abc$24881$new_n9419 pf_pc[13] $abc$24881$new_n4025 SET_USER_PC.r_upc[13] $abc$24881$new_n9420 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4203 $abc$24881$new_n4103 $abc$24881$new_n9420 ipc[13] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22836 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$new_n4119 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n4101 $abc$24881$new_n9422 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4087 $abc$24881$new_n9422 pf_pc[7] $abc$24881$new_n4025 SET_USER_PC.r_upc[7] $abc$24881$new_n9423 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4232 $abc$24881$new_n4103 $abc$24881$new_n9423 ipc[7] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22848 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4103 pf_pc[2] $abc$24881$new_n4125 $abc$24881$new_n4255 $abc$24881$new_n4024 $abc$24881$new_n9425 +00010 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9425 ipc[2] $abc$24881$new_n4124 $abc$24881$new_n4122 $abc$24881$new_n4019 $abc$24881$auto$rtlil.cc:2693:MuxGate$22858 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5149 $abc$24881$new_n5148 $abc$24881$new_n5113 $abc$24881$new_n5147 dcd_I[31] $abc$24881$new_n9427 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11011 1 +.names $abc$24881$new_n5066 $abc$24881$new_n4327 o_mem_addr[30] $abc$24881$new_n9427 $abc$24881$new_n5067 $abc$24881$auto$rtlil.cc:2693:MuxGate$22924 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4351 $abc$24881$new_n4344 $abc$24881$new_n9429 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4395 $abc$24881$new_n4390 $abc$24881$new_n4388 $abc$24881$new_n9433 +00000 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n9439 instruction_decoder.o_dcdB[4] $abc$24881$new_n4383 $abc$24881$new_n4069 $abc$24881$new_n4385 $abc$24881$new_n9434 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4398 $abc$24881$new_n9434 instruction_decoder.o_dcdB[4] $abc$24881$new_n9433 $abc$24881$new_n4393 $abc$24881$new_n9435 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9435 $abc$24881$new_n3848 $abc$24881$new_n4368 $abc$24881$new_n9436 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][3] regset[28][3] $abc$24881$new_n9437 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n9437 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][3] regset[24][3] $abc$24881$new_n9438 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] $abc$24881$new_n9438 instruction_decoder.o_dcdB[1] $abc$24881$new_n4382 $abc$24881$new_n4381 $abc$24881$new_n9439 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] $abc$24881$new_n4429 $abc$24881$new_n4432 $abc$24881$new_n4433 $abc$24881$new_n9440 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n9449 instruction_decoder.o_dcdB[4] $abc$24881$new_n9445 $abc$24881$new_n9440 instruction_decoder.o_dcdB[1] $abc$24881$new_n9441 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4434 $abc$24881$new_n9441 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3853 $abc$24881$new_n9442 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][2] regset[6][2] $abc$24881$new_n9443 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdB[1] $abc$24881$new_n9443 instruction_decoder.o_dcdB[2] regset[3][2] regset[2][2] $abc$24881$new_n9444 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n9444 $abc$24881$new_n4414 $abc$24881$new_n4413 $abc$24881$new_n9445 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][2] regset[17][2] $abc$24881$new_n9446 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4349 $abc$24881$new_n9446 instruction_decoder.o_dcdB[0] regset[20][2] regset[16][2] $abc$24881$new_n9447 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9860 $abc$24881$new_n9447 $abc$24881$new_n9451 $abc$24881$new_n4416 $abc$24881$new_n9449 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][2] regset[22][2] $abc$24881$new_n9450 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9450 instruction_decoder.o_dcdB[2] regset[19][2] regset[18][2] $abc$24881$new_n9451 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[31][1] regset[30][1] $abc$24881$new_n9452 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4069 $abc$24881$new_n9452 instruction_decoder.o_dcdB[2] regset[27][1] regset[26][1] $abc$24881$new_n9453 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n9453 $abc$24881$new_n9863 $abc$24881$new_n9464 $abc$24881$new_n9455 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[21][1] regset[20][1] $abc$24881$new_n9456 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4349 $abc$24881$new_n9456 instruction_decoder.o_dcdB[2] regset[17][1] regset[16][1] $abc$24881$new_n9457 +10000 1 +10010 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][1] regset[22][1] $abc$24881$new_n9458 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9458 instruction_decoder.o_dcdB[2] regset[19][1] regset[18][1] $abc$24881$new_n9459 +10000 1 +10010 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4466 $abc$24881$new_n4465 $abc$24881$new_n9460 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][1] regset[4][1] $abc$24881$new_n9462 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9462 instruction_decoder.o_dcdB[2] regset[1][1] regset[0][1] $abc$24881$new_n9463 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n9460 $abc$24881$new_n9466 instruction_decoder.o_dcdB[1] $abc$24881$new_n9865 $abc$24881$new_n9463 $abc$24881$new_n9464 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][1] regset[14][1] $abc$24881$new_n9465 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4069 $abc$24881$new_n9465 instruction_decoder.o_dcdB[2] regset[11][1] regset[10][1] $abc$24881$new_n9466 +10000 1 +10010 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][0] regset[14][0] $abc$24881$new_n9467 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4069 $abc$24881$new_n9467 instruction_decoder.o_dcdB[2] regset[11][0] regset[10][0] $abc$24881$new_n9468 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names dcd_Bcc instruction_decoder.o_dcdB[0] $abc$24881$new_n4349 $abc$24881$new_n4495 $abc$24881$new_n4496 $abc$24881$new_n9469 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][0] regset[6][0] $abc$24881$new_n9471 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9471 instruction_decoder.o_dcdB[2] regset[3][0] regset[2][0] $abc$24881$new_n9472 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][0] regset[22][0] $abc$24881$new_n9473 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9473 instruction_decoder.o_dcdB[2] regset[19][0] regset[18][0] $abc$24881$new_n9474 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$24881$new_n4504 instruction_decoder.o_dcdB[0] $abc$24881$new_n4069 $abc$24881$new_n4508 $abc$24881$new_n4509 $abc$24881$new_n9475 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[21][0] regset[20][0] $abc$24881$new_n9477 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4349 $abc$24881$new_n9477 instruction_decoder.o_dcdB[2] regset[17][0] regset[16][0] $abc$24881$new_n9478 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4529 $abc$24881$new_n4524 $abc$24881$new_n4542 $abc$24881$new_n9479 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][6] regset[4][6] $abc$24881$new_n9483 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4349 $abc$24881$new_n9483 instruction_decoder.o_dcdB[2] regset[1][6] regset[0][6] $abc$24881$new_n9484 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4533 $abc$24881$new_n4538 $abc$24881$new_n9485 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4504 $abc$24881$new_n9485 instruction_decoder.o_dcdB[3] $abc$24881$new_n4540 $abc$24881$new_n4536 $abc$24881$new_n9486 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4554 $abc$24881$new_n4550 $abc$24881$new_n4549 $abc$24881$new_n9487 +00000 1 +00100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9487 instruction_decoder.o_dcdB[3] $abc$24881$new_n4552 $abc$24881$new_n4547 $abc$24881$new_n9488 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +.names $abc$24881$new_n4556 $abc$24881$new_n9488 $abc$24881$new_n4368 $abc$24881$new_n3838 $abc$24881$new_n4472 $abc$24881$new_n9489 +01000 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] SET_TRAP_N_UBREAK.r_ubreak break_en $abc$24881$new_n4580 $abc$24881$new_n9490 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4570 $abc$24881$new_n4577 $abc$24881$new_n4587 $abc$24881$new_n9491 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9490 dcd_Bcc $abc$24881$new_n9491 $abc$24881$new_n9492 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n9492 $abc$24881$new_n3825 $abc$24881$new_n4368 $abc$24881$new_n9493 +100 1 +110 1 +111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] SET_USER_BUSERR.r_ubus_err_flag $abc$24881$new_n4625 $abc$24881$new_n4623 $abc$24881$new_n9494 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9494 instruction_decoder.o_dcdB[4] ibus_err_flag $abc$24881$new_n4616 $abc$24881$new_n4632 $abc$24881$new_n9495 +00010 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9495 $abc$24881$new_n4368 $abc$24881$new_n3810 $abc$24881$new_n9496 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4703 $abc$24881$new_n4349 $abc$24881$new_n4691 $abc$24881$new_n9497 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01101 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9497 $abc$24881$new_n4694 $abc$24881$new_n4701 $abc$24881$new_n4686 $abc$24881$new_n9498 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9498 $abc$24881$new_n4368 $abc$24881$new_n3800 $abc$24881$new_n9499 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4717 $abc$24881$new_n4715 $abc$24881$new_n9500 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9500 instruction_decoder.o_dcdB[4] GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n4708 $abc$24881$new_n4724 $abc$24881$new_n9501 +00010 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9501 $abc$24881$new_n4368 $abc$24881$new_n3795 $abc$24881$new_n9502 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4747 $abc$24881$new_n4349 $abc$24881$new_n4735 $abc$24881$new_n9503 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01101 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9503 $abc$24881$new_n4738 $abc$24881$new_n4745 $abc$24881$new_n4730 $abc$24881$new_n9504 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9504 $abc$24881$new_n4368 $abc$24881$new_n3790 $abc$24881$new_n9505 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4759 $abc$24881$new_n4757 $abc$24881$new_n4755 $abc$24881$new_n9506 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9506 $abc$24881$new_n4753 $abc$24881$new_n4761 $abc$24881$new_n4768 $abc$24881$new_n9507 +00010 1 +00110 1 +01010 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9507 $abc$24881$new_n4368 $abc$24881$new_n3779 $abc$24881$new_n9508 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n4784 $abc$24881$new_n4791 $abc$24881$new_n4349 $abc$24881$new_n4356 $abc$24881$new_n4789 $abc$24881$new_n9509 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9509 $abc$24881$new_n4774 $abc$24881$new_n4069 $abc$24881$new_n4781 $abc$24881$new_n9510 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9510 $abc$24881$new_n4368 $abc$24881$new_n3784 $abc$24881$new_n9511 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4805 $abc$24881$new_n4803 $abc$24881$new_n4801 $abc$24881$new_n9512 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9512 $abc$24881$new_n4799 $abc$24881$new_n4807 $abc$24881$new_n4814 $abc$24881$new_n9513 +00010 1 +00110 1 +01010 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9513 $abc$24881$new_n4368 $abc$24881$new_n3774 $abc$24881$new_n9514 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][21] regset[22][21] $abc$24881$new_n9515 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9515 instruction_decoder.o_dcdB[2] regset[19][21] regset[18][21] $abc$24881$new_n9516 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] $abc$24881$new_n4893 $abc$24881$new_n4884 $abc$24881$new_n9516 $abc$24881$new_n9517 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n9517 $abc$24881$new_n3752 $abc$24881$new_n4368 $abc$24881$new_n9518 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4929 $abc$24881$new_n4936 $abc$24881$new_n4946 $abc$24881$new_n9519 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9519 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4939 $abc$24881$new_n9520 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11100 1 +11101 1 +.names $abc$24881$new_n9520 $abc$24881$new_n3735 $abc$24881$new_n4368 $abc$24881$new_n9521 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4952 $abc$24881$new_n4959 $abc$24881$new_n4969 $abc$24881$new_n9522 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9522 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4962 $abc$24881$new_n9523 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11100 1 +11101 1 +.names $abc$24881$new_n9523 $abc$24881$new_n3741 $abc$24881$new_n4368 $abc$24881$new_n9524 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4976 $abc$24881$new_n4983 $abc$24881$new_n4993 $abc$24881$new_n9525 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9525 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4986 $abc$24881$new_n9526 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11100 1 +11101 1 +.names $abc$24881$new_n9526 $abc$24881$new_n3730 $abc$24881$new_n4368 $abc$24881$new_n9527 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[4] $abc$24881$new_n5007 $abc$24881$new_n5017 $abc$24881$new_n9528 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9528 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n5000 $abc$24881$new_n5010 $abc$24881$new_n9529 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9529 $abc$24881$new_n4368 $abc$24881$new_n3719 $abc$24881$new_n9530 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n5032 $abc$24881$new_n5039 $abc$24881$new_n4349 $abc$24881$new_n4356 $abc$24881$new_n5037 $abc$24881$new_n9531 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9531 $abc$24881$new_n5022 $abc$24881$new_n4069 $abc$24881$new_n5029 $abc$24881$new_n9532 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9532 $abc$24881$new_n4368 $abc$24881$new_n3725 $abc$24881$new_n9533 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[4] $abc$24881$new_n5058 $abc$24881$new_n5055 $abc$24881$new_n9534 +0000 1 +0010 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5078 $abc$24881$new_n5074 $abc$24881$new_n5072 $abc$24881$new_n9539 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9539 $abc$24881$new_n5080 instruction_decoder.o_dcdB[1] $abc$24881$new_n5076 $abc$24881$new_n9540 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9540 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3708 $abc$24881$new_n9541 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names $abc$24881$new_n5147 $abc$24881$new_n5148 $abc$24881$new_n5067 dcd_I[31] $abc$24881$new_n5113 $abc$24881$new_n9542 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +11010 1 +11011 1 +11110 1 +.names $abc$24881$new_n9542 $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n5067 $abc$24881$new_n9543 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n9543 o_mem_addr[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$22926 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n9877 $abc$24881$new_n5166 $abc$24881$new_n5148 $abc$24881$new_n5113 $abc$24881$new_n9545 +00000 1 +00001 1 +00010 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 dcd_I[31] $abc$24881$new_n9545 o_mem_addr[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$22928 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$24881$new_n5145 $abc$24881$new_n5146 $abc$24881$new_n5067 dcd_I[31] $abc$24881$new_n5114 $abc$24881$new_n9547 +00010 1 +00011 1 +00100 1 +01010 1 +01011 1 +01111 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 $abc$24881$new_n9547 $abc$24881$new_n9533 $abc$24881$new_n5171 $abc$24881$new_n5067 $abc$24881$new_n9548 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11110 1 +.names dcd_I[31] $abc$24881$new_n9524 $abc$24881$new_n9521 $abc$24881$new_n9843 $abc$24881$new_n9549 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n5182 $abc$24881$new_n9549 $abc$24881$new_n4972 $abc$24881$new_n5067 $abc$24881$new_n9550 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n9550 $abc$24881$new_n5066 r_op_Bv[25] $abc$24881$new_n3730 $abc$24881$auto$rtlil.cc:2693:MuxGate$22934 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n9524 $abc$24881$new_n9843 dcd_I[31] $abc$24881$new_n5192 $abc$24881$new_n9552 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9552 r_op_Bv[23] $abc$24881$new_n3741 $abc$24881$auto$rtlil.cc:2693:MuxGate$22938 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4904 dcd_I[31] $abc$24881$new_n9518 $abc$24881$new_n9844 dcd_I[21] $abc$24881$new_n9554 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[22] $abc$24881$new_n9554 $abc$24881$new_n5196 $abc$24881$auto$rtlil.cc:2693:MuxGate$22940 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5201 $abc$24881$new_n9518 $abc$24881$new_n9844 dcd_I[21] $abc$24881$new_n5065 $abc$24881$new_n9556 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n9556 $abc$24881$new_n5066 r_op_Bv[21] $abc$24881$new_n3752 $abc$24881$auto$rtlil.cc:2693:MuxGate$22942 +00010 1 +00011 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4860 dcd_I[20] $abc$24881$new_n4839 $abc$24881$new_n9845 dcd_I[19] $abc$24881$new_n9558 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[20] $abc$24881$new_n9558 $abc$24881$new_n5205 $abc$24881$auto$rtlil.cc:2693:MuxGate$22944 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n4817 dcd_I[18] $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] $abc$24881$new_n9560 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[18] $abc$24881$new_n9560 $abc$24881$new_n5214 $abc$24881$auto$rtlil.cc:2693:MuxGate$22948 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5219 $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] $abc$24881$new_n5065 $abc$24881$new_n9562 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n9562 $abc$24881$new_n5066 r_op_Bv[17] $abc$24881$new_n3774 $abc$24881$auto$rtlil.cc:2693:MuxGate$22950 +00010 1 +00011 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5224 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] $abc$24881$new_n9564 +0000 1 +0001 1 +0011 1 +0101 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[16] $abc$24881$new_n9564 $abc$24881$new_n5223 $abc$24881$auto$rtlil.cc:2693:MuxGate$22952 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] $abc$24881$new_n5229 $abc$24881$new_n9566 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9566 r_op_Bv[15] $abc$24881$new_n3784 $abc$24881$auto$rtlil.cc:2693:MuxGate$22954 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n9502 $abc$24881$new_n9847 dcd_I[13] $abc$24881$new_n5238 $abc$24881$new_n9568 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9568 r_op_Bv[13] $abc$24881$new_n3795 $abc$24881$auto$rtlil.cc:2693:MuxGate$22958 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9499 dcd_I[12] $abc$24881$new_n4660 $abc$24881$new_n4336 dcd_I[11] $abc$24881$new_n9570 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[12] $abc$24881$new_n9570 $abc$24881$new_n5242 $abc$24881$auto$rtlil.cc:2693:MuxGate$22960 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n9496 dcd_I[10] $abc$24881$new_n4636 $abc$24881$new_n4337 dcd_I[9] $abc$24881$new_n9572 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[10] $abc$24881$new_n9572 $abc$24881$new_n5250 $abc$24881$auto$rtlil.cc:2693:MuxGate$22964 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n5279 $abc$24881$new_n5128 $abc$24881$new_n9858 dcd_I[4] $abc$24881$new_n9574 +00001 1 +00010 1 +00101 1 +00110 1 +01001 1 +01010 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5066 $abc$24881$new_n9574 $abc$24881$new_n5276 $abc$24881$new_n5067 o_mem_addr[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22976 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names dcd_Apc $abc$24881$new_n5601 $abc$24881$new_n5602 dcd_Acc $abc$24881$new_n9576 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[30] $abc$24881$new_n9576 $abc$24881$new_n3702 $abc$24881$auto$rtlil.cc:2693:MuxGate$23378 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n5646 $abc$24881$new_n5635 $abc$24881$new_n9578 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[28] SET_USER_PC.r_upc[28] $abc$24881$new_n9582 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9582 dcd_Acc dcd_Apc $abc$24881$new_n5652 $abc$24881$new_n5662 $abc$24881$new_n9583 +00000 1 +00010 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[28] $abc$24881$new_n9583 $abc$24881$new_n3714 $abc$24881$auto$rtlil.cc:2693:MuxGate$23382 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5689 $abc$24881$new_n5691 $abc$24881$new_n9585 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9585 instruction_decoder.o_dcdA[3] $abc$24881$new_n5694 $abc$24881$new_n5697 $abc$24881$new_n9586 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[26] SET_USER_PC.r_upc[26] $abc$24881$new_n9589 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9589 dcd_Acc dcd_Apc $abc$24881$new_n5713 $abc$24881$new_n5703 $abc$24881$new_n9590 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[26] $abc$24881$new_n9590 $abc$24881$new_n3725 $abc$24881$auto$rtlil.cc:2693:MuxGate$23386 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n5759 $abc$24881$new_n5769 $abc$24881$new_n9592 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5793 $abc$24881$new_n5783 $abc$24881$new_n9596 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9596 instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n5786 $abc$24881$new_n5776 $abc$24881$new_n9597 +10001 1 +10011 1 +11010 1 +11011 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3741 $abc$24881$new_n5795 $abc$24881$new_n9597 $abc$24881$new_n9598 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5809 $abc$24881$new_n5815 $abc$24881$new_n5817 $abc$24881$new_n9599 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5819 $abc$24881$new_n5799 $abc$24881$new_n9599 $abc$24881$new_n9600 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[22] $abc$24881$new_n9600 $abc$24881$new_n3747 $abc$24881$auto$rtlil.cc:2693:MuxGate$23394 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5843 $abc$24881$new_n5822 $abc$24881$new_n5832 $abc$24881$new_n9602 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[21] $abc$24881$new_n9602 $abc$24881$new_n3752 $abc$24881$auto$rtlil.cc:2693:MuxGate$23396 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[20] SET_USER_PC.r_upc[20] $abc$24881$new_n9604 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9604 dcd_Apc $abc$24881$new_n5857 $abc$24881$new_n5847 $abc$24881$new_n9605 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[20] $abc$24881$new_n9605 $abc$24881$new_n3757 $abc$24881$auto$rtlil.cc:2693:MuxGate$23398 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5905 $abc$24881$new_n5913 $abc$24881$new_n5911 $abc$24881$new_n9607 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5915 $abc$24881$new_n5895 $abc$24881$new_n9607 $abc$24881$new_n9608 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[18] $abc$24881$new_n9608 $abc$24881$new_n3769 $abc$24881$auto$rtlil.cc:2693:MuxGate$23402 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5953 $abc$24881$new_n5959 $abc$24881$new_n5961 $abc$24881$new_n9610 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5963 $abc$24881$new_n5943 $abc$24881$new_n9610 $abc$24881$new_n9611 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[16] $abc$24881$new_n9611 $abc$24881$new_n3779 $abc$24881$auto$rtlil.cc:2693:MuxGate$23406 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[15] SET_USER_PC.r_upc[15] $abc$24881$new_n9613 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9613 dcd_Acc dcd_Apc $abc$24881$new_n5967 $abc$24881$new_n5977 $abc$24881$new_n9614 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[15] $abc$24881$new_n9614 $abc$24881$new_n3784 $abc$24881$auto$rtlil.cc:2693:MuxGate$23408 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[14] SET_USER_PC.r_upc[14] $abc$24881$new_n9616 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9616 dcd_Acc dcd_Apc $abc$24881$new_n6002 $abc$24881$new_n9619 $abc$24881$new_n9617 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[14] $abc$24881$new_n9617 $abc$24881$new_n3790 $abc$24881$auto$rtlil.cc:2693:MuxGate$23410 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5992 $abc$24881$new_n5998 $abc$24881$new_n6000 $abc$24881$new_n9619 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc $abc$24881$new_n6040 $abc$24881$new_n6041 dcd_Acc $abc$24881$new_n9620 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[12] $abc$24881$new_n9620 $abc$24881$new_n3800 $abc$24881$auto$rtlil.cc:2693:MuxGate$23414 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][11] regset[28][11] $abc$24881$new_n9622 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5637 $abc$24881$new_n9622 instruction_decoder.o_dcdA[2] regset[25][11] regset[24][11] $abc$24881$new_n9623 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names dcd_Acc DIVERR.USER_DIVERR.r_udiv_err_flag $abc$24881$new_n6067 $abc$24881$new_n9623 $abc$24881$new_n9624 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n9624 DIVERR.r_idiv_err_flag $abc$24881$new_n6076 $abc$24881$new_n9625 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6197 $abc$24881$new_n6192 $abc$24881$new_n9626 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[5] SET_USER_PC.r_upc[5] $abc$24881$new_n9630 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9630 dcd_Acc dcd_Apc $abc$24881$new_n6213 $abc$24881$new_n6223 $abc$24881$new_n9631 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[5] $abc$24881$new_n9631 $abc$24881$new_n3838 $abc$24881$auto$rtlil.cc:2693:MuxGate$23428 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[4] $abc$24881$new_n6241 $abc$24881$new_n6239 $abc$24881$new_n6249 $abc$24881$new_n9633 +01000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6251 instruction_decoder.o_dcdA[1] $abc$24881$new_n9633 $abc$24881$new_n6243 $abc$24881$new_n9634 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names dcd_Acc $abc$24881$new_n9634 sleep $abc$24881$new_n9635 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6272 $abc$24881$new_n6269 $abc$24881$new_n6264 $abc$24881$new_n9636 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6275 $abc$24881$new_n6282 $abc$24881$new_n6280 $abc$24881$new_n9637 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9637 $abc$24881$new_n9636 $abc$24881$new_n6266 $abc$24881$new_n9638 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n9638 $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n9639 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc $abc$24881$new_n4071 $abc$24881$new_n9645 SET_USER_PC.r_upc[2] instruction_decoder.o_pc[2] $abc$24881$new_n9640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[2] $abc$24881$new_n9640 $abc$24881$new_n3853 $abc$24881$auto$rtlil.cc:2693:MuxGate$23434 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6294 $abc$24881$new_n6297 $abc$24881$new_n6300 $abc$24881$new_n9642 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6303 $abc$24881$new_n6310 $abc$24881$new_n6308 $abc$24881$new_n9643 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9643 $abc$24881$new_n9642 $abc$24881$new_n6291 $abc$24881$new_n9644 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n9644 $abc$24881$new_n4438 $abc$24881$new_n4435 $abc$24881$new_n9645 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n4468 $abc$24881$new_n6328 $abc$24881$new_n9646 +0001 1 +0011 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6320 $abc$24881$new_n6323 $abc$24881$new_n6326 $abc$24881$new_n9648 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6361 $abc$24881$new_n6351 $abc$24881$new_n9650 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[29] $abc$24881$new_n6382 i_pf_instruction[17] $abc$24881$new_n6366 i_pf_instruction_pc[28] $abc$24881$new_n9654 +00001 1 +00011 1 +01011 1 +01100 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4278 $abc$24881$new_n9654 $abc$24881$auto$rtlil.cc:2693:MuxGate$23442 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n6566 $abc$24881$new_n6556 $abc$24881$new_n9656 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n5595 instruction_decoder.o_dcdA[4] $abc$24881$new_n9656 $abc$24881$new_n6558 $abc$24881$new_n6549 $abc$24881$new_n9657 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names o_mem_data[31] o_mem_addr[31] $abc$24881$new_n6683 $abc$24881$new_n6662 $abc$24881$new_n6682 $abc$24881$new_n9658 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names alu_ce doalu.c $abc$24881$new_n6685 $abc$24881$new_n6655 $abc$24881$new_n9658 $abc$24881$auto$rtlil.cc:2693:MuxGate$23622 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n3692 r_op_Av[3] $abc$24881$new_n3848 $abc$24881$new_n9660 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n6678 o_mem_addr[3] $abc$24881$new_n9660 $abc$24881$new_n6680 $abc$24881$new_n6679 $abc$24881$new_n9661 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n6746 $abc$24881$new_n6741 $abc$24881$new_n6745 $abc$24881$new_n9662 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[5] o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6727 $abc$24881$new_n9662 $abc$24881$new_n9663 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[5] $abc$24881$new_n6776 $abc$24881$new_n9663 o_mem_data[0] $abc$24881$new_n6751 $abc$24881$new_n9664 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n4282 $abc$24881$new_n4284 $abc$24881$new_n4302 $abc$24881$new_n4292 $abc$24881$new_n4280 $abc$24881$new_n9665 +10001 1 +10111 1 +11000 1 +11110 1 +.names $abc$24881$new_n9665 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n4279 $abc$24881$new_n4278 $abc$24881$new_n9666 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_OPIPE.r_insn_is_pipeable $abc$24881$new_n6801 $abc$24881$new_n9666 $abc$24881$auto$rtlil.cc:2693:MuxGate$23632 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n3932 $abc$24881$new_n9668 +00000 1 +00110 1 +11000 1 +11110 1 +.names $abc$24881$new_n3879 DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[43] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n9669 +00000 1 +00011 1 +01100 1 +01111 1 +10100 1 +10111 1 +11000 1 +11011 1 +.names $abc$24881$new_n6943 $abc$24881$new_n9669 $abc$24881$new_n9668 $abc$24881$new_n3922 $abc$24881$new_n3917 $abc$24881$new_n9670 +11100 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7726 o_mem_addr[0] o_mem_data[0] $abc$24881$new_n9671 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names o_mem_addr[1] o_mem_data[1] $abc$24881$new_n9671 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9672 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_data[1] $abc$24881$new_n6775 DIVIDE.thedivide.i_signed $abc$24881$new_n7722 $abc$24881$new_n9674 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7737 $abc$24881$new_n6771 $abc$24881$new_n6774 $abc$24881$new_n9678 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7733 $abc$24881$new_n9678 $abc$24881$new_n9679 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[5] o_mem_data[5] $abc$24881$new_n7843 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9680 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7721 $abc$24881$new_n9680 $abc$24881$new_n7844 $abc$24881$new_n9681 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9681 $abc$24881$new_n7826 $abc$24881$new_n7847 $abc$24881$auto$rtlil.cc:2582:Mux$3529[5] +100 1 +110 1 +111 1 +.names o_mem_addr[7] o_mem_data[7] $abc$24881$new_n7884 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9683 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[7] o_mem_data[7] $abc$24881$new_n7881 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9684 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7700 $abc$24881$new_n7695 $abc$24881$new_n7706 $abc$24881$new_n9688 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$24881$new_n7888 $abc$24881$new_n7692 $abc$24881$new_n9688 $abc$24881$new_n7689 $abc$24881$new_n7891 $abc$24881$new_n9689 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7892 $abc$24881$new_n7897 $abc$24881$new_n9689 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[8] +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6696 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9691 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n7722 o_mem_addr[10] o_mem_data[10] $abc$24881$new_n9691 $abc$24881$new_n9692 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6672 DIVIDE.thedivide.i_signed $abc$24881$new_n7722 $abc$24881$new_n9693 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +10000 1 +11100 1 +11101 1 +.names $abc$24881$new_n6656 $abc$24881$new_n9692 $abc$24881$new_n9693 $abc$24881$new_n9694 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6671 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9695 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01100 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7722 $abc$24881$new_n9695 $abc$24881$new_n6656 $abc$24881$new_n7954 $abc$24881$new_n9696 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9696 $abc$24881$new_n7945 $abc$24881$auto$rtlil.cc:2582:Mux$3529[12] +10 1 +.names o_mem_addr[13] o_mem_data[13] $abc$24881$new_n7971 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9698 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names $abc$24881$new_n7958 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n9698 $abc$24881$new_n7972 $abc$24881$auto$rtlil.cc:2582:Mux$3529[13] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6776 o_mem_addr[4] o_mem_data[31] $abc$24881$new_n7718 $abc$24881$new_n9700 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$24881$new_n9700 $abc$24881$new_n7728 o_mem_addr[4] $abc$24881$new_n6727 $abc$24881$new_n7694 $abc$24881$new_n9701 +00000 1 +00010 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n6786 $abc$24881$new_n9701 o_mem_data[31] $abc$24881$new_n6658 $abc$24881$new_n7728 $abc$24881$new_n9702 +00110 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6653 $abc$24881$new_n6654 $abc$24881$new_n6711 $abc$24881$new_n6692 $abc$24881$new_n9703 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names o_mem_addr[20] o_mem_data[20] $abc$24881$new_n9703 $abc$24881$new_n7722 $abc$24881$new_n6653 $abc$24881$new_n9704 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +10000 1 +10001 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7722 $abc$24881$new_n8056 $abc$24881$new_n9704 $abc$24881$new_n6656 $abc$24881$new_n9705 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9705 $abc$24881$new_n9709 $abc$24881$new_n8063 $abc$24881$auto$rtlil.cc:2582:Mux$3529[20] +100 1 +110 1 +111 1 +.names o_mem_addr[4] o_mem_addr[3] $abc$24881$new_n7817 $abc$24881$new_n7949 $abc$24881$new_n8062 $abc$24881$new_n9707 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n9707 $abc$24881$new_n7812 $abc$24881$new_n9708 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7728 $abc$24881$new_n9708 $abc$24881$new_n6657 $abc$24881$new_n6658 $abc$24881$new_n8058 $abc$24881$new_n9709 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +.names o_mem_addr[24] o_mem_data[24] $abc$24881$new_n7722 $abc$24881$new_n7723 $abc$24881$new_n7721 $abc$24881$new_n9710 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n7727 $abc$24881$new_n9710 $abc$24881$new_n8110 $abc$24881$new_n7721 $abc$24881$new_n8108 $abc$24881$new_n9711 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9711 $abc$24881$new_n8112 $abc$24881$new_n7820 o_mem_addr[7] $abc$24881$auto$rtlil.cc:2582:Mux$3529[24] +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$24881$new_n7727 o_mem_data[28] o_mem_addr[28] DIVIDE.thedivide.i_signed o_mem_addr[3] $abc$24881$new_n9713 +00001 1 +00101 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n7727 $abc$24881$new_n9713 $abc$24881$new_n7726 $abc$24881$new_n8163 $abc$24881$new_n7728 $abc$24881$new_n9714 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8161 $abc$24881$new_n7727 $abc$24881$new_n8158 $abc$24881$new_n9714 $abc$24881$new_n7722 $abc$24881$auto$rtlil.cc:2582:Mux$3529[28] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8181 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7961 $abc$24881$new_n7963 $abc$24881$new_n9716 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8185 $abc$24881$new_n8179 $abc$24881$new_n9716 $abc$24881$new_n7690 $abc$24881$new_n9717 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9717 $abc$24881$new_n7727 $abc$24881$new_n8186 $abc$24881$new_n8173 $abc$24881$new_n8171 $abc$24881$auto$rtlil.cc:2582:Mux$3529[29] +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7722 o_mem_data[31] o_mem_addr[31] $abc$24881$new_n6656 $abc$24881$new_n7723 $abc$24881$new_n9719 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9719 $abc$24881$new_n7722 $abc$24881$new_n8206 $abc$24881$new_n8203 $abc$24881$new_n6653 $abc$24881$new_n9720 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8101 $abc$24881$new_n8155 $abc$24881$new_n8212 $abc$24881$new_n9721 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7998 $abc$24881$new_n9721 $abc$24881$new_n7996 $abc$24881$new_n9722 +00001 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7690 $abc$24881$new_n9722 o_mem_data[31] $abc$24881$new_n6658 $abc$24881$new_n9723 +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_dbg_rreg[4] i_dbg_rreg[2] $abc$24881$new_n8535 $abc$24881$new_n8523 $abc$24881$new_n8533 $abc$24881$new_n9724 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names i_dbg_rreg[4] $abc$24881$new_n8529 $abc$24881$new_n8531 $abc$24881$new_n8515 $abc$24881$new_n8518 $abc$24881$new_n9725 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11010 1 +11110 1 +.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9724 $abc$24881$new_n9725 $abc$24881$new_n8515 $abc$24881$new_n9726 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names $abc$24881$new_n8525 i_dbg_rreg[4] $abc$24881$new_n9726 $abc$24881$new_n4470 $abc$24881$new_n4468 $abc$24881$new_n9727 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9895 SET_USER_PC.r_upc[2] ipc[2] $0\genblk43.SETDBG.r_dbg_reg[31:0][2] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] regset[21][3] regset[20][3] $abc$24881$new_n9731 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9731 regset[23][3] regset[22][3] $abc$24881$new_n9732 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] i_dbg_rreg[0] $abc$24881$new_n9732 regset[29][3] regset[28][3] $abc$24881$new_n9733 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n9733 $abc$24881$new_n8568 $abc$24881$new_n8566 $abc$24881$new_n9734 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n8575 regset[1][3] regset[0][3] $abc$24881$new_n9735 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8579 regset[11][3] regset[10][3] $abc$24881$new_n9736 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] $abc$24881$new_n9736 regset[13][3] regset[12][3] $abc$24881$new_n9737 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] $abc$24881$new_n9735 $abc$24881$new_n9737 $abc$24881$new_n8576 i_dbg_rreg[2] $abc$24881$new_n9738 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8621 $abc$24881$new_n8627 $abc$24881$new_n8623 $abc$24881$new_n9739 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n8615 $abc$24881$new_n8610 $abc$24881$new_n8617 i_dbg_rreg[2] $abc$24881$new_n9740 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +.names i_dbg_rreg[4] $abc$24881$new_n9740 $abc$24881$new_n8625 $abc$24881$new_n9739 $abc$24881$new_n9741 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n8525 i_dbg_rreg[4] $abc$24881$new_n9741 $abc$24881$new_n5380 $abc$24881$new_n5379 $abc$24881$procmux$2451_Y[0] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[4] i_dbg_rreg[2] $abc$24881$new_n8673 $abc$24881$new_n8661 $abc$24881$new_n8670 $abc$24881$new_n9743 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names i_dbg_rreg[4] i_dbg_rreg[3] $abc$24881$new_n9743 $abc$24881$new_n8654 $abc$24881$new_n8665 $abc$24881$new_n9744 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8525 $abc$24881$new_n9744 $abc$24881$new_n4520 i_dbg_rreg[4] $abc$24881$new_n9745 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9745 SET_USER_PC.r_upc[6] ipc[6] $0\genblk43.SETDBG.r_dbg_reg[31:0][6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[7] ipc[7] $abc$24881$new_n9747 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8686 $abc$24881$new_n8683 $abc$24881$new_n8678 $abc$24881$new_n9748 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$new_n9748 $abc$24881$new_n8688 $abc$24881$new_n8680 i_dbg_rreg[3] $abc$24881$new_n9749 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9747 $abc$24881$new_n8698 $abc$24881$new_n9749 $abc$24881$new_n8525 $0\genblk43.SETDBG.r_dbg_reg[31:0][7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names i_dbg_rreg[0] i_dbg_rreg[2] regset[29][8] regset[28][8] $abc$24881$new_n9751 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9751 i_dbg_rreg[1] regset[19][8] regset[18][8] $abc$24881$new_n9752 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9752 i_dbg_rreg[2] i_dbg_rreg[1] regset[17][8] regset[16][8] $abc$24881$new_n9753 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9753 $abc$24881$new_n8713 $abc$24881$new_n8719 $abc$24881$new_n9754 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n8749 regset[17][10] regset[16][10] $abc$24881$new_n9755 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8753 regset[27][10] regset[26][10] $abc$24881$new_n9756 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] $abc$24881$new_n9756 regset[29][10] regset[28][10] $abc$24881$new_n9757 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] $abc$24881$new_n9755 $abc$24881$new_n9757 $abc$24881$new_n8750 i_dbg_rreg[2] $abc$24881$new_n9758 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n8781 i_dbg_rreg[2] $abc$24881$new_n8785 $abc$24881$new_n8783 $abc$24881$new_n9759 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8789 $abc$24881$new_n8525 $abc$24881$new_n8769 $abc$24881$new_n8787 $abc$24881$new_n9759 $abc$24881$new_n9760 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9760 SET_USER_PC.r_upc[11] ipc[11] $0\genblk43.SETDBG.r_dbg_reg[31:0][11] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] i_dbg_rreg[3] $abc$24881$new_n8807 $abc$24881$new_n8805 $abc$24881$new_n8803 $abc$24881$new_n9762 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9762 i_dbg_rreg[2] $abc$24881$new_n8801 $abc$24881$new_n8796 $abc$24881$new_n8798 $abc$24881$new_n9763 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8816 $abc$24881$new_n8821 $abc$24881$new_n8818 $abc$24881$new_n9767 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[14] ipc[14] $abc$24881$new_n9770 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8842 $abc$24881$new_n8846 $abc$24881$new_n9771 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9771 i_dbg_rreg[2] $abc$24881$new_n8844 $abc$24881$new_n8840 $abc$24881$new_n9772 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n9770 $abc$24881$new_n9772 $abc$24881$new_n8848 $0\genblk43.SETDBG.r_dbg_reg[31:0][14] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[15] ipc[15] $abc$24881$new_n9774 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8870 $abc$24881$new_n8863 $abc$24881$new_n9775 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9775 i_dbg_rreg[2] $abc$24881$new_n8865 $abc$24881$new_n8867 $abc$24881$new_n9776 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n9774 $abc$24881$new_n9776 $abc$24881$new_n8871 $0\genblk43.SETDBG.r_dbg_reg[31:0][15] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[4] i_dbg_rreg[2] SET_USER_PC.r_upc[17] $abc$24881$new_n8909 $abc$24881$new_n8907 $abc$24881$new_n9778 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] i_dbg_rreg[3] $abc$24881$new_n9778 $abc$24881$new_n8913 $abc$24881$new_n8911 $abc$24881$new_n9779 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y $abc$24881$new_n9779 ipc[17] $abc$24881$new_n8915 $0\genblk43.SETDBG.r_dbg_reg[31:0][17] +00000 1 +00001 1 +00010 1 +00011 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8935 $abc$24881$new_n8933 $abc$24881$new_n8929 $abc$24881$new_n9781 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y $abc$24881$new_n9781 i_dbg_rreg[3] SET_USER_PC.r_upc[18] $abc$24881$new_n8931 $abc$24881$new_n9782 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y $abc$24881$new_n9782 ipc[18] $abc$24881$new_n8937 $0\genblk43.SETDBG.r_dbg_reg[31:0][18] +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8965 $abc$24881$new_n8969 $abc$24881$new_n8967 $abc$24881$new_n9785 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[2] regset[31][19] regset[30][19] $abc$24881$new_n9787 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9787 i_dbg_rreg[1] regset[17][19] regset[16][19] $abc$24881$new_n9788 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n9788 i_dbg_rreg[2] i_dbg_rreg[1] regset[19][19] regset[18][19] $abc$24881$new_n9789 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9789 $abc$24881$new_n8954 $abc$24881$new_n8958 $abc$24881$new_n9790 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[4] i_dbg_rreg[2] $abc$24881$new_n8993 $abc$24881$new_n8982 $abc$24881$new_n8990 $abc$24881$new_n9792 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names i_dbg_rreg[4] $abc$24881$new_n9797 $abc$24881$new_n8985 $abc$24881$new_n8975 $abc$24881$new_n8977 $abc$24881$new_n9793 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9792 $abc$24881$new_n9793 $abc$24881$new_n9797 $abc$24881$new_n9794 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9794 SET_USER_PC.r_upc[20] ipc[20] $0\genblk43.SETDBG.r_dbg_reg[31:0][20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[31][20] regset[30][20] $abc$24881$new_n9796 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n6930 $abc$24881$new_n9796 i_dbg_rreg[1] regset[29][20] regset[28][20] $abc$24881$new_n9797 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9012 i_dbg_rreg[2] $abc$24881$new_n9001 $abc$24881$new_n9014 $abc$24881$new_n9798 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9922 SET_USER_PC.r_upc[21] ipc[21] $0\genblk43.SETDBG.r_dbg_reg[31:0][21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9047 i_dbg_rreg[2] $abc$24881$new_n9051 $abc$24881$new_n9045 $abc$24881$new_n9801 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9053 $abc$24881$new_n9801 $abc$24881$new_n9049 $abc$24881$new_n9802 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9802 SET_USER_PC.r_upc[23] ipc[23] $0\genblk43.SETDBG.r_dbg_reg[31:0][23] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9077 i_dbg_rreg[2] $abc$24881$new_n9081 $abc$24881$new_n9075 $abc$24881$new_n9804 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9810 $abc$24881$new_n9079 $abc$24881$new_n9804 $abc$24881$new_n9805 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9805 SET_USER_PC.r_upc[24] ipc[24] $0\genblk43.SETDBG.r_dbg_reg[31:0][24] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][24] regset[13][24] regset[12][24] $abc$24881$new_n9807 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] i_dbg_rreg[3] regset[10][24] regset[3][24] regset[2][24] $abc$24881$new_n9808 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names i_dbg_rreg[3] i_dbg_rreg[1] $abc$24881$new_n9808 $abc$24881$new_n9068 $abc$24881$new_n9072 $abc$24881$new_n9809 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n9809 $abc$24881$new_n9807 $abc$24881$new_n9069 $abc$24881$new_n9810 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[26] ipc[26] $abc$24881$new_n9811 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n9911 i_dbg_rreg[2] $abc$24881$new_n9112 $abc$24881$new_n9108 $abc$24881$new_n9813 +0000 1 +0010 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n9811 $abc$24881$new_n9813 $abc$24881$new_n9818 $0\genblk43.SETDBG.r_dbg_reg[31:0][26] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n9119 regset[17][26] regset[16][26] $abc$24881$new_n9815 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9123 regset[27][26] regset[26][26] $abc$24881$new_n9816 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] $abc$24881$new_n9816 regset[29][26] regset[28][26] $abc$24881$new_n9817 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] $abc$24881$new_n9817 $abc$24881$new_n9815 $abc$24881$new_n9120 $abc$24881$new_n9818 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9141 i_dbg_rreg[2] $abc$24881$new_n9135 $abc$24881$new_n9139 $abc$24881$new_n9819 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9915 SET_USER_PC.r_upc[27] ipc[27] $0\genblk43.SETDBG.r_dbg_reg[31:0][27] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[28] ipc[28] $abc$24881$new_n9823 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9155 $abc$24881$new_n9159 $abc$24881$new_n9824 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9824 i_dbg_rreg[2] $abc$24881$new_n9157 $abc$24881$new_n9153 $abc$24881$new_n9825 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n9823 $abc$24881$new_n9825 $abc$24881$new_n9830 $0\genblk43.SETDBG.r_dbg_reg[31:0][28] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] regset[5][28] regset[4][28] $abc$24881$new_n9827 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9827 regset[7][28] regset[6][28] $abc$24881$new_n9828 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] i_dbg_rreg[0] $abc$24881$new_n9828 regset[13][28] regset[12][28] $abc$24881$new_n9829 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n9829 $abc$24881$new_n9167 $abc$24881$new_n9165 $abc$24881$new_n9830 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9178 i_dbg_rreg[2] $abc$24881$new_n9182 $abc$24881$new_n9176 $abc$24881$new_n9831 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9184 $abc$24881$new_n9831 $abc$24881$new_n9180 $abc$24881$new_n9832 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9832 SET_USER_PC.r_upc[29] ipc[29] $0\genblk43.SETDBG.r_dbg_reg[31:0][29] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[4] $abc$24881$new_n9917 $abc$24881$new_n9201 $abc$24881$new_n9211 $abc$24881$new_n9835 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9835 $abc$24881$new_n9196 $abc$24881$new_n9206 $abc$24881$new_n9836 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9836 SET_USER_PC.r_upc[30] ipc[30] $0\genblk43.SETDBG.r_dbg_reg[31:0][30] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names r_halted i_halt $abc$24881$new_n9274 $abc$24881$new_n3959 DIVIDE.thedivide.o_busy $abc$24881$new_n9838 +00110 1 +01110 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9838 o_mem_ce i_dbg_we i_mem_busy $abc$24881$procmux$2578_Y +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_mem_rdbusy alu_reg[2] instruction_decoder.o_dcdB[2] $abc$24881$new_n9406 instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$new_n9840 +00010 1 +00011 1 +01110 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +.names i_mem_rdbusy $abc$24881$new_n9412 $abc$24881$new_n4035 $abc$24881$new_n9840 DIVIDE.thedivide.o_busy $abc$24881$new_n9841 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Bcc dcd_zI $abc$24881$new_n9841 op_wF GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n9842 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +11000 1 +11100 1 +.names $abc$24881$new_n9518 $abc$24881$new_n9844 $abc$24881$new_n4904 dcd_I[31] dcd_I[21] $abc$24881$new_n9843 +00100 1 +00101 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4860 $abc$24881$new_n4839 $abc$24881$new_n9845 dcd_I[19] dcd_I[20] $abc$24881$new_n9844 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4817 $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] dcd_I[18] $abc$24881$new_n9845 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9508 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] dcd_I[16] $abc$24881$new_n9846 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9499 $abc$24881$new_n4660 $abc$24881$new_n4336 dcd_I[11] dcd_I[12] $abc$24881$new_n9847 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[27] SET_USER_PC.r_upc[27] $abc$24881$new_n9848 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9848 dcd_Acc dcd_Apc $abc$24881$new_n9586 $abc$24881$new_n5678 $abc$24881$new_n9849 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[27] $abc$24881$new_n9849 $abc$24881$new_n3719 $abc$24881$auto$rtlil.cc:2693:MuxGate$23384 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9646 instruction_decoder.o_dcdA[4] $abc$24881$new_n4470 $abc$24881$new_n9648 $abc$24881$new_n6317 $abc$24881$new_n9851 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5595 r_op_Av[1] $abc$24881$new_n9851 $abc$24881$new_n6338 $abc$24881$auto$rtlil.cc:2693:MuxGate$23436 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9650 dcd_Acc $abc$24881$new_n6344 $abc$24881$new_n6354 $abc$24881$new_n9853 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9853 dcd_Apc dcd_Acc $abc$24881$new_n5380 $abc$24881$new_n5379 $abc$24881$new_n9854 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[0] $abc$24881$new_n9854 $abc$24881$new_n3863 $abc$24881$auto$rtlil.cc:2693:MuxGate$23438 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9429 instruction_decoder.o_dcdB[3] $abc$24881$new_n4354 $abc$24881$new_n4347 $abc$24881$new_n9856 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9856 $abc$24881$new_n4358 $abc$24881$new_n4365 instruction_decoder.o_dcdB[1] $abc$24881$new_n9857 +00100 1 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4367 dcd_Bcc $abc$24881$new_n4373 $abc$24881$new_n9857 sleep $abc$24881$new_n9858 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[31][2] regset[30][2] $abc$24881$new_n9859 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4069 $abc$24881$new_n9859 instruction_decoder.o_dcdB[2] regset[27][2] regset[26][2] $abc$24881$new_n9860 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][1] regset[28][1] $abc$24881$new_n9861 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n9861 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][1] regset[24][1] $abc$24881$new_n9862 +00000 1 +00010 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9459 $abc$24881$new_n9457 instruction_decoder.o_dcdB[3] $abc$24881$new_n9862 $abc$24881$new_n9863 +0000 1 +0001 1 +0010 1 +.names instruction_decoder.o_dcdB[0] regset[9][1] regset[8][1] $abc$24881$new_n9864 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n9864 regset[13][1] regset[12][1] $abc$24881$new_n9865 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[13][0] regset[12][0] $abc$24881$new_n9866 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9866 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[9][0] regset[8][0] $abc$24881$new_n9867 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9468 $abc$24881$new_n9469 $abc$24881$new_n9472 instruction_decoder.o_dcdB[3] $abc$24881$new_n9867 $abc$24881$new_n9868 +11000 1 +11001 1 +11010 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][0] regset[28][0] $abc$24881$new_n9869 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9869 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][0] regset[24][0] $abc$24881$new_n9870 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9474 $abc$24881$new_n9475 $abc$24881$new_n9478 instruction_decoder.o_dcdB[3] $abc$24881$new_n9870 $abc$24881$new_n9871 +11000 1 +11001 1 +11010 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4520 $abc$24881$new_n9479 $abc$24881$new_n9484 $abc$24881$new_n9872 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3832 $abc$24881$new_n4368 $abc$24881$new_n9872 $abc$24881$new_n4373 $abc$24881$new_n9486 $abc$24881$new_n9873 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] $abc$24881$new_n5045 $abc$24881$new_n5061 $abc$24881$new_n5063 $abc$24881$new_n9874 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9534 instruction_decoder.o_dcdB[1] $abc$24881$new_n5048 $abc$24881$new_n5050 $abc$24881$new_n9875 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n9875 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[4] $abc$24881$new_n9874 $abc$24881$new_n5052 $abc$24881$new_n9876 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9876 $abc$24881$new_n4368 $abc$24881$new_n3714 $abc$24881$new_n9877 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[29] SET_USER_PC.r_upc[29] $abc$24881$new_n9878 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9878 $abc$24881$new_n9578 dcd_Apc $abc$24881$new_n5628 $abc$24881$new_n5639 $abc$24881$new_n9879 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[29] $abc$24881$new_n9879 $abc$24881$new_n3708 $abc$24881$auto$rtlil.cc:2693:MuxGate$23380 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[24] SET_USER_PC.r_upc[24] $abc$24881$new_n9881 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9881 $abc$24881$new_n9592 dcd_Apc $abc$24881$new_n5762 $abc$24881$new_n5752 $abc$24881$new_n9882 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[24] $abc$24881$new_n9882 $abc$24881$new_n3735 $abc$24881$auto$rtlil.cc:2693:MuxGate$23390 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][6] regset[6][6] $abc$24881$new_n9884 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9626 $abc$24881$new_n9884 instruction_decoder.o_dcdA[2] regset[2][6] regset[3][6] $abc$24881$new_n9885 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$24881$new_n9626 dcd_Acc instruction_decoder.o_dcdA[3] $abc$24881$new_n9885 $abc$24881$new_n6190 $abc$24881$new_n9886 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n9886 $abc$24881$new_n4520 $abc$24881$new_n6199 $abc$24881$new_n9887 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n7727 o_mem_addr[1] o_mem_data[1] DIVIDE.thedivide.i_signed o_mem_addr[30] $abc$24881$new_n9888 +00001 1 +00101 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7722 $abc$24881$new_n9888 $abc$24881$new_n9671 $abc$24881$new_n9672 $abc$24881$new_n9889 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n6656 $abc$24881$new_n9889 $abc$24881$new_n7730 $abc$24881$new_n9674 $abc$24881$auto$rtlil.cc:2582:Mux$3529[1] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7869 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n9683 $abc$24881$new_n9684 $abc$24881$auto$rtlil.cc:2582:Mux$3529[7] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8541 $abc$24881$new_n8547 $abc$24881$new_n8543 $abc$24881$new_n9893 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8525 $abc$24881$new_n4438 $abc$24881$new_n8545 $abc$24881$new_n9893 $abc$24881$new_n9894 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n9894 $abc$24881$new_n4435 $abc$24881$new_n8549 $abc$24881$new_n9895 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9762 $abc$24881$new_n8584 $abc$24881$new_n9763 i_dbg_rreg[4] $abc$24881$new_n8794 $abc$24881$new_n9896 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9896 SET_USER_PC.r_upc[12] ipc[12] $0\genblk43.SETDBG.r_dbg_reg[31:0][12] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8525 i_dbg_rreg[4] GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n9767 $abc$24881$new_n8823 $abc$24881$new_n9898 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9898 i_dbg_rreg[4] $abc$24881$new_n8726 $abc$24881$new_n8825 GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n9899 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +.names $abc$24881$new_n9899 i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y SET_USER_PC.r_upc[13] ipc[13] $0\genblk43.SETDBG.r_dbg_reg[31:0][13] +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[4] regset[29][19] regset[28][19] $abc$24881$new_n9901 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n8516 $abc$24881$new_n9901 i_dbg_rreg[4] regset[13][19] regset[12][19] $abc$24881$new_n9902 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$24881$new_n9902 i_dbg_rreg[4] $abc$24881$new_n9790 $abc$24881$new_n9785 $abc$24881$new_n8963 $abc$24881$new_n9903 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9903 SET_USER_PC.r_upc[19] ipc[19] $0\genblk43.SETDBG.r_dbg_reg[31:0][19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[19][21] regset[18][21] $abc$24881$new_n9905 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9905 i_dbg_rreg[3] i_dbg_rreg[1] regset[16][21] regset[17][21] $abc$24881$new_n9906 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10010 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9006 $abc$24881$new_n9906 $abc$24881$new_n9009 $abc$24881$new_n9907 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] regset[7][26] regset[5][26] $abc$24881$new_n9909 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9909 i_dbg_rreg[3] i_dbg_rreg[0] regset[6][26] regset[4][26] $abc$24881$new_n9910 +00001 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9910 i_dbg_rreg[2] regset[13][26] regset[12][26] $abc$24881$new_n9911 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[31][27] regset[30][27] $abc$24881$new_n9912 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9912 i_dbg_rreg[1] regset[29][27] regset[28][27] $abc$24881$new_n9913 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9130 $abc$24881$new_n9913 $abc$24881$new_n9144 $abc$24881$new_n9914 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9819 $abc$24881$new_n9129 $abc$24881$new_n9914 $abc$24881$new_n9915 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] i_dbg_rreg[0] regset[29][30] regset[13][30] $abc$24881$new_n9916 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9916 i_dbg_rreg[1] i_dbg_rreg[0] regset[28][30] regset[12][30] $abc$24881$new_n9917 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_dbg_rreg[0] i_dbg_rreg[4] regset[31][21] regset[30][21] $abc$24881$new_n9918 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9918 i_dbg_rreg[1] regset[15][21] regset[14][21] $abc$24881$new_n9919 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n6930 $abc$24881$new_n9919 i_dbg_rreg[1] regset[13][21] regset[12][21] $abc$24881$new_n9920 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] $abc$24881$new_n9907 $abc$24881$new_n9918 $abc$24881$new_n9018 $abc$24881$new_n9921 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$new_n9921 $abc$24881$new_n9798 $abc$24881$new_n9920 $abc$24881$new_n9922 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.subckt sdffr C=i_clk D=$abc$24881$procmux$2451_Y[0] Q=o_dbg_reg[0] R=$abc$24881$eq$./benchmark/zipcore.v:3393$815_Y +.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[4] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[4] +.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[5] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[5] +.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[6] +.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[4] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[0] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] +.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[5] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[1] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] +.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[2] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23656 Q=GEN_UHALT_PHASE.r_uhalt_phase R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[0] Q=regset[4][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[1] Q=regset[4][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[2] Q=regset[4][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[3] Q=regset[4][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[4] Q=regset[4][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[5] Q=regset[4][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[6] Q=regset[4][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[7] Q=regset[4][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[8] Q=regset[4][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[9] Q=regset[4][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[10] Q=regset[4][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[11] Q=regset[4][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[12] Q=regset[4][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[13] Q=regset[4][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[14] Q=regset[4][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[15] Q=regset[4][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[16] Q=regset[4][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[17] Q=regset[4][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[18] Q=regset[4][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[19] Q=regset[4][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[20] Q=regset[4][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[21] Q=regset[4][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[22] Q=regset[4][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[23] Q=regset[4][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[24] Q=regset[4][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[25] Q=regset[4][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[26] Q=regset[4][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[27] Q=regset[4][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[28] Q=regset[4][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[29] Q=regset[4][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[30] Q=regset[4][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[31] Q=regset[4][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[0] Q=regset[11][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[1] Q=regset[11][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[2] Q=regset[11][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[3] Q=regset[11][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[4] Q=regset[11][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[5] Q=regset[11][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[6] Q=regset[11][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[7] Q=regset[11][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[8] Q=regset[11][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[9] Q=regset[11][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[10] Q=regset[11][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[11] Q=regset[11][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[12] Q=regset[11][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[13] Q=regset[11][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[14] Q=regset[11][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[15] Q=regset[11][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[16] Q=regset[11][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[17] Q=regset[11][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[18] Q=regset[11][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[19] Q=regset[11][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[20] Q=regset[11][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[21] Q=regset[11][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[22] Q=regset[11][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[23] Q=regset[11][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[24] Q=regset[11][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[25] Q=regset[11][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[26] Q=regset[11][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[27] Q=regset[11][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[28] Q=regset[11][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[29] Q=regset[11][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[30] Q=regset[11][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[31] Q=regset[11][31] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][1] Q=o_dbg_reg[1] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][2] Q=o_dbg_reg[2] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][3] Q=o_dbg_reg[3] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][4] Q=o_dbg_reg[4] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][5] Q=o_dbg_reg[5] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][6] Q=o_dbg_reg[6] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][7] Q=o_dbg_reg[7] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][8] Q=o_dbg_reg[8] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][9] Q=o_dbg_reg[9] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][10] Q=o_dbg_reg[10] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][11] Q=o_dbg_reg[11] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][12] Q=o_dbg_reg[12] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][13] Q=o_dbg_reg[13] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][14] Q=o_dbg_reg[14] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][15] Q=o_dbg_reg[15] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][16] Q=o_dbg_reg[16] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][17] Q=o_dbg_reg[17] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][18] Q=o_dbg_reg[18] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][19] Q=o_dbg_reg[19] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][20] Q=o_dbg_reg[20] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][21] Q=o_dbg_reg[21] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][22] Q=o_dbg_reg[22] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][23] Q=o_dbg_reg[23] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][24] Q=o_dbg_reg[24] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][25] Q=o_dbg_reg[25] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][26] Q=o_dbg_reg[26] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][27] Q=o_dbg_reg[27] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][28] Q=o_dbg_reg[28] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][29] Q=o_dbg_reg[29] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][30] Q=o_dbg_reg[30] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][31] Q=o_dbg_reg[31] +.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1613$573_Y Q=alu_wF R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3485 +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[0] Q=regset[5][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[1] Q=regset[5][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[2] Q=regset[5][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[3] Q=regset[5][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[4] Q=regset[5][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[5] Q=regset[5][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[6] Q=regset[5][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[7] Q=regset[5][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[8] Q=regset[5][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[9] Q=regset[5][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[10] Q=regset[5][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[11] Q=regset[5][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[12] Q=regset[5][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[13] Q=regset[5][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[14] Q=regset[5][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[15] Q=regset[5][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[16] Q=regset[5][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[17] Q=regset[5][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[18] Q=regset[5][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[19] Q=regset[5][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[20] Q=regset[5][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[21] Q=regset[5][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[22] Q=regset[5][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[23] Q=regset[5][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[24] Q=regset[5][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[25] Q=regset[5][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[26] Q=regset[5][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[27] Q=regset[5][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[28] Q=regset[5][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[29] Q=regset[5][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[30] Q=regset[5][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[31] Q=regset[5][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[0] Q=regset[10][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[1] Q=regset[10][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[2] Q=regset[10][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[3] Q=regset[10][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[4] Q=regset[10][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[5] Q=regset[10][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[6] Q=regset[10][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[7] Q=regset[10][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[8] Q=regset[10][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[9] Q=regset[10][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[10] Q=regset[10][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[11] Q=regset[10][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[12] Q=regset[10][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[13] Q=regset[10][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[14] Q=regset[10][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[15] Q=regset[10][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[16] Q=regset[10][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[17] Q=regset[10][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[18] Q=regset[10][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[19] Q=regset[10][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[20] Q=regset[10][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[21] Q=regset[10][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[22] Q=regset[10][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[23] Q=regset[10][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[24] Q=regset[10][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[25] Q=regset[10][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[26] Q=regset[10][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[27] Q=regset[10][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[28] Q=regset[10][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[29] Q=regset[10][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[30] Q=regset[10][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[31] Q=regset[10][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[0] Q=regset[27][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[1] Q=regset[27][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[2] Q=regset[27][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[3] Q=regset[27][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[4] Q=regset[27][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[5] Q=regset[27][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[6] Q=regset[27][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[7] Q=regset[27][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[8] Q=regset[27][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[9] Q=regset[27][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[10] Q=regset[27][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[11] Q=regset[27][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[12] Q=regset[27][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[13] Q=regset[27][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[14] Q=regset[27][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[15] Q=regset[27][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[16] Q=regset[27][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[17] Q=regset[27][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[18] Q=regset[27][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[19] Q=regset[27][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[20] Q=regset[27][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[21] Q=regset[27][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[22] Q=regset[27][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[23] Q=regset[27][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[24] Q=regset[27][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[25] Q=regset[27][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[26] Q=regset[27][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[27] Q=regset[27][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[28] Q=regset[27][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[29] Q=regset[27][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[30] Q=regset[27][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[31] Q=regset[27][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23314 Q=GEN_ALU_PC.r_alu_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23312 Q=GEN_ALU_PC.r_alu_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23310 Q=GEN_ALU_PC.r_alu_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23308 Q=GEN_ALU_PC.r_alu_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23306 Q=GEN_ALU_PC.r_alu_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23304 Q=GEN_ALU_PC.r_alu_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23302 Q=GEN_ALU_PC.r_alu_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23300 Q=GEN_ALU_PC.r_alu_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23298 Q=GEN_ALU_PC.r_alu_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23296 Q=GEN_ALU_PC.r_alu_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23294 Q=GEN_ALU_PC.r_alu_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23292 Q=GEN_ALU_PC.r_alu_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23290 Q=GEN_ALU_PC.r_alu_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23288 Q=GEN_ALU_PC.r_alu_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23286 Q=GEN_ALU_PC.r_alu_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23284 Q=GEN_ALU_PC.r_alu_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23282 Q=GEN_ALU_PC.r_alu_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23280 Q=GEN_ALU_PC.r_alu_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23278 Q=GEN_ALU_PC.r_alu_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23276 Q=GEN_ALU_PC.r_alu_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23274 Q=GEN_ALU_PC.r_alu_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23272 Q=GEN_ALU_PC.r_alu_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23270 Q=GEN_ALU_PC.r_alu_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23268 Q=GEN_ALU_PC.r_alu_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23266 Q=GEN_ALU_PC.r_alu_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23264 Q=GEN_ALU_PC.r_alu_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23262 Q=GEN_ALU_PC.r_alu_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23260 Q=GEN_ALU_PC.r_alu_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23258 Q=GEN_ALU_PC.r_alu_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23740 Q=GEN_ALU_PC.r_alu_pc[31] +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[0] Q=alu_result[0] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[1] Q=alu_result[1] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[2] Q=alu_result[2] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[3] Q=alu_result[3] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[4] Q=alu_result[4] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[5] Q=alu_result[5] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[6] Q=alu_result[6] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[7] Q=alu_result[7] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[8] Q=alu_result[8] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[9] Q=alu_result[9] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[10] Q=alu_result[10] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[11] Q=alu_result[11] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[12] Q=alu_result[12] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[13] Q=alu_result[13] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[14] Q=alu_result[14] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[15] Q=alu_result[15] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[16] Q=alu_result[16] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[17] Q=alu_result[17] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[18] Q=alu_result[18] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[19] Q=alu_result[19] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[20] Q=alu_result[20] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[21] Q=alu_result[21] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[22] Q=alu_result[22] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[23] Q=alu_result[23] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[24] Q=alu_result[24] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[25] Q=alu_result[25] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[26] Q=alu_result[26] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[27] Q=alu_result[27] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[28] Q=alu_result[28] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[29] Q=alu_result[29] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[30] Q=alu_result[30] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[31] Q=doalu.n RN=alu_ce +.subckt sdffr C=i_clk D=$abc$24881$memory$auto$proc_rom.cc:150:do_switch$1988$rdmux[0][1][0]$b$3899[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[3] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$4528 +.subckt sdffs C=i_clk D=$abc$24881$procmux$2428_Y Q=r_halted S=i_reset +.subckt sdffr C=i_clk D=$abc$24881$procmux$2463_Y Q=o_clear_dcache R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23658 Q=GEN_IHALT_PHASE.r_ihalt_phase R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23660 Q=DIVERR.USER_DIVERR.r_udiv_err_flag R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23662 Q=DIVERR.r_idiv_err_flag R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23664 Q=SET_USER_BUSERR.r_ubus_err_flag R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23666 Q=SET_USER_ILLEGAL_INSN.r_ill_err_u R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23668 Q=SET_TRAP_N_UBREAK.r_ubreak R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23670 Q=SET_TRAP_N_UBREAK.r_trap R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23672 Q=SET_GIE.r_gie R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3432 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23674 Q=GEN_PENDING_INTERRUPT.r_pending_interrupt R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3429 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23676 Q=GEN_PENDING_INTERRUPT.r_user_stepped R=$abc$24881$logic_or$./benchmark/zipcore.v:2741$689_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23678 Q=sleep R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3432 +.subckt sdffr C=i_clk D=$abc$24881$procmux$2578_Y Q=GEN_CLOCK_GATE.r_clken R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23680 Q=GEN_PENDING_BREAK.r_break_pending R=$abc$24881$logic_or$./benchmark/zipcore.v:2501$630_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23256 Q=BUSLOCK.r_bus_lock[0] R=new_pc +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23682 Q=BUSLOCK.r_bus_lock[1] R=new_pc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23254 Q=dcd_I[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23252 Q=dcd_I[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23250 Q=dcd_I[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23248 Q=dcd_I[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23246 Q=dcd_I[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23244 Q=dcd_I[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23242 Q=dcd_I[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23240 Q=dcd_I[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23238 Q=dcd_I[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23236 Q=dcd_I[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23234 Q=dcd_I[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23232 Q=dcd_I[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23230 Q=dcd_I[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23228 Q=dcd_I[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23226 Q=dcd_I[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23224 Q=dcd_I[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23222 Q=dcd_I[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23220 Q=dcd_I[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23218 Q=dcd_I[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23216 Q=dcd_I[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23214 Q=dcd_I[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23212 Q=dcd_I[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23584 Q=dcd_I[31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23684 Q=BUSLOCK.r_prelock_stall R=new_pc +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23686 Q=GEN_ALU_PHASE.r_alu_phase R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23210 Q=o_mem_lock_pc[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23208 Q=o_mem_lock_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23206 Q=o_mem_lock_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23204 Q=o_mem_lock_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23202 Q=o_mem_lock_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23200 Q=o_mem_lock_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23198 Q=o_mem_lock_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23196 Q=o_mem_lock_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23194 Q=o_mem_lock_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23192 Q=o_mem_lock_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23190 Q=o_mem_lock_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23188 Q=o_mem_lock_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23186 Q=o_mem_lock_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23184 Q=o_mem_lock_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23182 Q=o_mem_lock_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23180 Q=o_mem_lock_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23178 Q=o_mem_lock_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23176 Q=o_mem_lock_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23174 Q=o_mem_lock_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23172 Q=o_mem_lock_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23170 Q=o_mem_lock_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23168 Q=o_mem_lock_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23166 Q=o_mem_lock_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23164 Q=o_mem_lock_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23162 Q=o_mem_lock_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23160 Q=o_mem_lock_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23158 Q=o_mem_lock_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23156 Q=o_mem_lock_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23154 Q=o_mem_lock_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23152 Q=o_mem_lock_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23742 Q=o_mem_lock_pc[31] +.subckt sdffr C=i_clk D=op_illegal Q=SET_ALU_ILLEGAL.r_alu_illegal R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3420 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23688 Q=OPT_CIS_OP_PHASE.r_op_phase R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$procmux$2659_Y Q=alu_wR R=i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23150 Q=DIVIDE.thedivide.i_signed +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23146 Q=o_mem_op[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23142 Q=o_mem_op[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23576 Q=FWD_OPERATION.r_op_opn[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23138 Q=alu_reg[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23136 Q=alu_reg[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23134 Q=alu_reg[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23132 Q=alu_reg[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23578 Q=alu_reg[4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[0] Q=regset[25][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[1] Q=regset[25][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[2] Q=regset[25][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[3] Q=regset[25][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[4] Q=regset[25][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[5] Q=regset[25][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[6] Q=regset[25][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[7] Q=regset[25][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[8] Q=regset[25][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[9] Q=regset[25][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[10] Q=regset[25][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[11] Q=regset[25][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[12] Q=regset[25][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[13] Q=regset[25][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[14] Q=regset[25][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[15] Q=regset[25][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[16] Q=regset[25][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[17] Q=regset[25][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[18] Q=regset[25][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[19] Q=regset[25][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[20] Q=regset[25][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[21] Q=regset[25][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[22] Q=regset[25][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[23] Q=regset[25][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[24] Q=regset[25][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[25] Q=regset[25][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[26] Q=regset[25][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[27] Q=regset[25][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[28] Q=regset[25][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[29] Q=regset[25][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[30] Q=regset[25][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[31] Q=regset[25][31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23690 Q=GEN_OPLOCK.r_op_lock R=new_pc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23572 Q=GEN_OP_WR.r_op_wR +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23728 Q=SET_OP_PC.r_op_pc[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23130 Q=o_mem_reg[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23128 Q=o_mem_reg[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23126 Q=o_mem_reg[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23124 Q=o_mem_reg[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23570 Q=o_mem_reg[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23122 Q=OP_REG_ADVANEC.r_op_Bid[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23120 Q=OP_REG_ADVANEC.r_op_Bid[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23118 Q=OP_REG_ADVANEC.r_op_Bid[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23116 Q=OP_REG_ADVANEC.r_op_Bid[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23568 Q=OP_REG_ADVANEC.r_op_Bid[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23566 Q=OP_REG_ADVANEC.r_op_rA +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23692 Q=GEN_OP_PIPE.r_op_pipe R=$abc$24881$logic_or$./benchmark/zipcore.v:728$452_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23694 Q=GEN_OP_STALL.r_pending_sreg_write R=new_pc +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23114 Q=ipc[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23112 Q=ipc[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23110 Q=ipc[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23108 Q=ipc[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23106 Q=ipc[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23104 Q=ipc[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23102 Q=ipc[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23100 Q=ipc[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23098 Q=ipc[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23096 Q=ipc[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23094 Q=ipc[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23092 Q=ipc[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23090 Q=ipc[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23088 Q=ipc[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23086 Q=ipc[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23084 Q=ipc[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23082 Q=ipc[18] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23080 Q=ipc[19] R=i_reset +.subckt sdffs C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23078 Q=ipc[20] S=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23076 Q=ipc[21] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23074 Q=ipc[22] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23072 Q=ipc[23] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23070 Q=ipc[24] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23068 Q=ipc[25] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23066 Q=ipc[26] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23064 Q=ipc[27] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23062 Q=ipc[28] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23060 Q=ipc[29] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23058 Q=ipc[30] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23696 Q=ipc[31] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$procmux$2728_Y Q=GEN_OP_STALL.r_cc_invalid_for_dcd R=new_pc +.subckt dff C=i_clk D=sleep Q=o_dbg_cc[0] +.subckt dff C=i_clk D=SET_GIE.r_gie Q=o_dbg_cc[1] +.subckt dff C=i_clk D=i_bus_err Q=o_dbg_cc[2] +.subckt sdffs C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y Q=r_dbg_stall S=$abc$24881$auto$opt_dff.cc:253:combine_resets$3407 +.subckt sdffs C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y Q=new_pc S=$abc$24881$auto$opt_dff.cc:253:combine_resets$3404 +.subckt sdffr C=i_clk D=$abc$24881$procmux$2755_Y Q=o_clear_icache R=i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23564 Q=OP_REG_ADVANEC.r_op_rB +.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y Q=last_write_to_cc R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23698 Q=ibus_err_flag R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23700 Q=ill_err_i R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23702 Q=user_step R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23704 Q=break_en R=i_reset +.subckt dff C=i_clk D=$0\iflags[3:0][0] Q=iflags[0] +.subckt dff C=i_clk D=$0\iflags[3:0][1] Q=iflags[1] +.subckt dff C=i_clk D=$0\iflags[3:0][2] Q=iflags[2] +.subckt dff C=i_clk D=$0\iflags[3:0][3] Q=iflags[3] +.subckt dff C=i_clk D=$0\flags[3:0][0] Q=flags[0] +.subckt dff C=i_clk D=$0\flags[3:0][1] Q=flags[1] +.subckt dff C=i_clk D=$0\flags[3:0][2] Q=flags[2] +.subckt dff C=i_clk D=$0\flags[3:0][3] Q=flags[3] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23706 Q=r_alu_pc_valid R=new_pc +.subckt sdffr C=i_clk D=mem_ce Q=mem_pc_valid R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23056 Q=wr_index[0] R=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23708 Q=wr_index[1] R=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y +.subckt dff C=i_clk D=i_dbg_data[0] Q=dbg_val[0] +.subckt dff C=i_clk D=i_dbg_data[1] Q=dbg_val[1] +.subckt dff C=i_clk D=i_dbg_data[2] Q=dbg_val[2] +.subckt dff C=i_clk D=i_dbg_data[3] Q=dbg_val[3] +.subckt dff C=i_clk D=i_dbg_data[4] Q=dbg_val[4] +.subckt dff C=i_clk D=i_dbg_data[5] Q=dbg_val[5] +.subckt dff C=i_clk D=i_dbg_data[6] Q=dbg_val[6] +.subckt dff C=i_clk D=i_dbg_data[7] Q=dbg_val[7] +.subckt dff C=i_clk D=i_dbg_data[8] Q=dbg_val[8] +.subckt dff C=i_clk D=i_dbg_data[9] Q=dbg_val[9] +.subckt dff C=i_clk D=i_dbg_data[10] Q=dbg_val[10] +.subckt dff C=i_clk D=i_dbg_data[11] Q=dbg_val[11] +.subckt dff C=i_clk D=i_dbg_data[12] Q=dbg_val[12] +.subckt dff C=i_clk D=i_dbg_data[13] Q=dbg_val[13] +.subckt dff C=i_clk D=i_dbg_data[14] Q=dbg_val[14] +.subckt dff C=i_clk D=i_dbg_data[15] Q=dbg_val[15] +.subckt dff C=i_clk D=i_dbg_data[16] Q=dbg_val[16] +.subckt dff C=i_clk D=i_dbg_data[17] Q=dbg_val[17] +.subckt dff C=i_clk D=i_dbg_data[18] Q=dbg_val[18] +.subckt dff C=i_clk D=i_dbg_data[19] Q=dbg_val[19] +.subckt dff C=i_clk D=i_dbg_data[20] Q=dbg_val[20] +.subckt dff C=i_clk D=i_dbg_data[21] Q=dbg_val[21] +.subckt dff C=i_clk D=i_dbg_data[22] Q=dbg_val[22] +.subckt dff C=i_clk D=i_dbg_data[23] Q=dbg_val[23] +.subckt dff C=i_clk D=i_dbg_data[24] Q=dbg_val[24] +.subckt dff C=i_clk D=i_dbg_data[25] Q=dbg_val[25] +.subckt dff C=i_clk D=i_dbg_data[26] Q=dbg_val[26] +.subckt dff C=i_clk D=i_dbg_data[27] Q=dbg_val[27] +.subckt dff C=i_clk D=i_dbg_data[28] Q=dbg_val[28] +.subckt dff C=i_clk D=i_dbg_data[29] Q=dbg_val[29] +.subckt dff C=i_clk D=i_dbg_data[30] Q=dbg_val[30] +.subckt dff C=i_clk D=i_dbg_data[31] Q=dbg_val[31] +.subckt sdffr C=i_clk D=$abc$24881$procmux$3022_Y Q=dbg_clear_pipe R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3389 +.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y Q=dbgv R=$abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23054 Q=SET_OP_PC.r_op_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23052 Q=SET_OP_PC.r_op_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23050 Q=SET_OP_PC.r_op_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23048 Q=SET_OP_PC.r_op_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23046 Q=SET_OP_PC.r_op_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23044 Q=SET_OP_PC.r_op_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23042 Q=SET_OP_PC.r_op_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23040 Q=SET_OP_PC.r_op_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23038 Q=SET_OP_PC.r_op_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23036 Q=SET_OP_PC.r_op_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23034 Q=SET_OP_PC.r_op_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23032 Q=SET_OP_PC.r_op_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23030 Q=SET_OP_PC.r_op_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23028 Q=SET_OP_PC.r_op_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23026 Q=SET_OP_PC.r_op_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23024 Q=SET_OP_PC.r_op_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23022 Q=SET_OP_PC.r_op_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23020 Q=SET_OP_PC.r_op_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23018 Q=SET_OP_PC.r_op_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23016 Q=SET_OP_PC.r_op_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23014 Q=SET_OP_PC.r_op_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23012 Q=SET_OP_PC.r_op_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23010 Q=SET_OP_PC.r_op_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23008 Q=SET_OP_PC.r_op_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23006 Q=SET_OP_PC.r_op_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23004 Q=SET_OP_PC.r_op_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23002 Q=SET_OP_PC.r_op_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23000 Q=SET_OP_PC.r_op_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22998 Q=SET_OP_PC.r_op_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23738 Q=SET_OP_PC.r_op_pc[31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23710 Q=op_illegal R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23712 Q=r_op_break R=new_pc +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23714 Q=op_valid R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23716 Q=op_valid_mem R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23718 Q=op_valid_alu R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23720 Q=op_valid_div R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23562 Q=op_wF +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22996 Q=r_op_F[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22994 Q=r_op_F[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22992 Q=r_op_F[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22990 Q=r_op_F[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22988 Q=r_op_F[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22986 Q=r_op_F[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23560 Q=r_op_F[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22984 Q=r_op_Bv[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22982 Q=r_op_Bv[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22980 Q=r_op_Bv[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22978 Q=r_op_Bv[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22976 Q=r_op_Bv[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22974 Q=r_op_Bv[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22972 Q=r_op_Bv[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22970 Q=r_op_Bv[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22968 Q=r_op_Bv[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22966 Q=r_op_Bv[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22964 Q=r_op_Bv[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22962 Q=r_op_Bv[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22960 Q=r_op_Bv[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22958 Q=r_op_Bv[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22956 Q=r_op_Bv[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22954 Q=r_op_Bv[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22952 Q=r_op_Bv[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22950 Q=r_op_Bv[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22948 Q=r_op_Bv[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22946 Q=r_op_Bv[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22944 Q=r_op_Bv[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22942 Q=r_op_Bv[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22940 Q=r_op_Bv[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22938 Q=r_op_Bv[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22936 Q=r_op_Bv[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22934 Q=r_op_Bv[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22932 Q=r_op_Bv[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22930 Q=r_op_Bv[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22928 Q=r_op_Bv[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22926 Q=r_op_Bv[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22924 Q=r_op_Bv[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23558 Q=r_op_Bv[31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[0] Q=regset[23][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[1] Q=regset[23][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[2] Q=regset[23][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[3] Q=regset[23][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[4] Q=regset[23][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[5] Q=regset[23][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[6] Q=regset[23][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[7] Q=regset[23][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[8] Q=regset[23][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[9] Q=regset[23][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[10] Q=regset[23][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[11] Q=regset[23][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[12] Q=regset[23][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[13] Q=regset[23][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[14] Q=regset[23][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[15] Q=regset[23][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[16] Q=regset[23][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[17] Q=regset[23][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[18] Q=regset[23][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[19] Q=regset[23][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[20] Q=regset[23][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[21] Q=regset[23][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[22] Q=regset[23][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[23] Q=regset[23][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[24] Q=regset[23][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[25] Q=regset[23][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[26] Q=regset[23][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[27] Q=regset[23][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[28] Q=regset[23][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[29] Q=regset[23][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[30] Q=regset[23][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[31] Q=regset[23][31] +.subckt dff C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$0\r_dividend[62:0][31] Q=DIVIDE.thedivide.r_dividend[31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23618 Q=doalu.set_ovfl +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23636 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp R=instruction_decoder.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23610 Q=dcd_zI +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23608 Q=dcd_F[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22922 Q=dcd_opn[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22918 Q=dcd_opn[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22914 Q=dcd_opn[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23604 Q=dcd_opn[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23606 Q=dcd_wF +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23592 Q=dcd_wR +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23588 Q=dcd_rB +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23600 Q=dcd_ALU +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23598 Q=dcd_M +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22910 Q=instruction_decoder.r_nxt_half[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22908 Q=instruction_decoder.r_nxt_half[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22906 Q=instruction_decoder.r_nxt_half[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22904 Q=instruction_decoder.r_nxt_half[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22902 Q=instruction_decoder.r_nxt_half[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22900 Q=instruction_decoder.r_nxt_half[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22898 Q=instruction_decoder.r_nxt_half[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22896 Q=instruction_decoder.r_nxt_half[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22894 Q=instruction_decoder.r_nxt_half[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22892 Q=instruction_decoder.r_nxt_half[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22890 Q=instruction_decoder.r_nxt_half[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22888 Q=instruction_decoder.r_nxt_half[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22886 Q=instruction_decoder.r_nxt_half[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22884 Q=instruction_decoder.r_nxt_half[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23586 Q=instruction_decoder.r_nxt_half[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23590 Q=dcd_rA +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23582 Q=instruction_decoder.o_pc[1] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23640 Q=instruction_decoder.o_illegal R=instruction_decoder.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22882 Q=instruction_decoder.o_dcdA[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22880 Q=instruction_decoder.o_dcdA[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22878 Q=instruction_decoder.o_dcdA[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22876 Q=instruction_decoder.o_dcdA[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22874 Q=instruction_decoder.o_dcdA[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22872 Q=dcd_Apc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23614 Q=dcd_Acc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22870 Q=instruction_decoder.o_dcdB[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22868 Q=instruction_decoder.o_dcdB[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22866 Q=instruction_decoder.o_dcdB[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22864 Q=instruction_decoder.o_dcdB[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22862 Q=instruction_decoder.o_dcdB[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22860 Q=dcd_Bpc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23612 Q=dcd_Bcc +.subckt sdffr C=i_clk D=$abc$24881$flatten\instruction_decoder.$procmux$2071_Y Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3474 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23638 Q=instruction_decoder.GEN_CIS_PHASE.r_phase R=$abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23616 Q=dcd_break +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[0] Q=regset[28][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[1] Q=regset[28][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[2] Q=regset[28][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[3] Q=regset[28][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[4] Q=regset[28][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[5] Q=regset[28][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[6] Q=regset[28][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[7] Q=regset[28][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[8] Q=regset[28][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[9] Q=regset[28][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[10] Q=regset[28][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[11] Q=regset[28][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[12] Q=regset[28][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[13] Q=regset[28][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[14] Q=regset[28][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[15] Q=regset[28][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[16] Q=regset[28][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[17] Q=regset[28][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[18] Q=regset[28][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[19] Q=regset[28][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[20] Q=regset[28][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[21] Q=regset[28][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[22] Q=regset[28][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[23] Q=regset[28][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[24] Q=regset[28][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[25] Q=regset[28][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[26] Q=regset[28][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[27] Q=regset[28][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[28] Q=regset[28][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[29] Q=regset[28][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[30] Q=regset[28][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[31] Q=regset[28][31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23630 Q=instruction_decoder.GEN_OPIPE.r_pipe R=instruction_decoder.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23632 Q=instruction_decoder.GEN_OPIPE.r_insn_is_pipeable R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3478 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23634 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch R=instruction_decoder.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23596 Q=instruction_decoder.o_DV +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23594 Q=instruction_decoder.o_lock +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22858 Q=pf_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22856 Q=pf_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22854 Q=pf_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22852 Q=pf_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22850 Q=pf_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22848 Q=pf_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22846 Q=pf_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22844 Q=pf_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22842 Q=pf_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22840 Q=pf_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22838 Q=pf_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22836 Q=pf_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22834 Q=pf_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22832 Q=pf_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22830 Q=pf_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22828 Q=pf_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22826 Q=pf_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22824 Q=pf_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22822 Q=pf_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22820 Q=pf_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22818 Q=pf_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22816 Q=pf_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22814 Q=pf_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22812 Q=pf_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22810 Q=pf_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22808 Q=pf_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22806 Q=pf_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22804 Q=pf_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22802 Q=pf_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23736 Q=pf_pc[31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23626 Q=DIVIDE.thedivide.zero_divisor +.subckt sdffr C=i_clk D=alu_ce Q=doalu.o_valid R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22800 Q=SET_USER_PC.r_upc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22798 Q=SET_USER_PC.r_upc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22796 Q=SET_USER_PC.r_upc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22794 Q=SET_USER_PC.r_upc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22792 Q=SET_USER_PC.r_upc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22790 Q=SET_USER_PC.r_upc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22788 Q=SET_USER_PC.r_upc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22786 Q=SET_USER_PC.r_upc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22784 Q=SET_USER_PC.r_upc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22782 Q=SET_USER_PC.r_upc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22780 Q=SET_USER_PC.r_upc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22778 Q=SET_USER_PC.r_upc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22776 Q=SET_USER_PC.r_upc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22774 Q=SET_USER_PC.r_upc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22772 Q=SET_USER_PC.r_upc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22770 Q=SET_USER_PC.r_upc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22768 Q=SET_USER_PC.r_upc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22766 Q=SET_USER_PC.r_upc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22764 Q=SET_USER_PC.r_upc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22762 Q=SET_USER_PC.r_upc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22760 Q=SET_USER_PC.r_upc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22758 Q=SET_USER_PC.r_upc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22756 Q=SET_USER_PC.r_upc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22754 Q=SET_USER_PC.r_upc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22752 Q=SET_USER_PC.r_upc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22750 Q=SET_USER_PC.r_upc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22748 Q=SET_USER_PC.r_upc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22746 Q=SET_USER_PC.r_upc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22744 Q=SET_USER_PC.r_upc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23654 Q=SET_USER_PC.r_upc[31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23622 Q=doalu.c +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23620 Q=doalu.keep_sgn_on_ovfl +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23624 Q=doalu.pre_sign +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22742 Q=DIVIDE.thedivide.r_dividend[33] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22738 Q=DIVIDE.thedivide.r_dividend[34] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22734 Q=DIVIDE.thedivide.r_dividend[35] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22730 Q=DIVIDE.thedivide.r_dividend[36] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22726 Q=DIVIDE.thedivide.r_dividend[37] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22722 Q=DIVIDE.thedivide.r_dividend[38] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22718 Q=DIVIDE.thedivide.r_dividend[39] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22714 Q=DIVIDE.thedivide.r_dividend[40] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22710 Q=DIVIDE.thedivide.r_dividend[41] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22706 Q=DIVIDE.thedivide.r_dividend[42] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22702 Q=DIVIDE.thedivide.r_dividend[43] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22698 Q=DIVIDE.thedivide.r_dividend[44] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22694 Q=DIVIDE.thedivide.r_dividend[45] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22690 Q=DIVIDE.thedivide.r_dividend[46] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22686 Q=DIVIDE.thedivide.r_dividend[47] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22682 Q=DIVIDE.thedivide.r_dividend[48] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22678 Q=DIVIDE.thedivide.r_dividend[49] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22674 Q=DIVIDE.thedivide.r_dividend[50] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22670 Q=DIVIDE.thedivide.r_dividend[51] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22666 Q=DIVIDE.thedivide.r_dividend[52] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22662 Q=DIVIDE.thedivide.r_dividend[53] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22658 Q=DIVIDE.thedivide.r_dividend[54] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22654 Q=DIVIDE.thedivide.r_dividend[55] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22650 Q=DIVIDE.thedivide.r_dividend[56] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22646 Q=DIVIDE.thedivide.r_dividend[57] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22642 Q=DIVIDE.thedivide.r_dividend[58] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22638 Q=DIVIDE.thedivide.r_dividend[59] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22634 Q=DIVIDE.thedivide.r_dividend[60] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22630 Q=DIVIDE.thedivide.r_dividend[61] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23732 Q=DIVIDE.thedivide.r_dividend[62] +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.X[0] Q=DIVIDE.thedivide.r_bit[0] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[1] Q=DIVIDE.thedivide.r_bit[1] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[2] Q=DIVIDE.thedivide.r_bit[2] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[3] Q=DIVIDE.thedivide.r_bit[3] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[4] Q=DIVIDE.thedivide.r_bit[4] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$eq$./benchmark/div.v:248$1635_Y Q=DIVIDE.thedivide.last_bit R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3460 +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:263$1639_Y Q=DIVIDE.thedivide.pre_sign R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23648 Q=DIVIDE.thedivide.o_valid R=$abc$24881$flatten\DIVIDE.thedivide.$logic_or$./benchmark/div.v:189$1625_Y +.subckt sdffs C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23646 Q=DIVIDE.thedivide.r_z S=DIVIDE.thedivide.i_wr +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23628 Q=instruction_decoder.r_valid R=instruction_decoder.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2314_Y Q=DIVIDE.thedivide.r_sign R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2305_Y Q=DIVIDE.thedivide.o_quotient[0] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[0] Q=DIVIDE.thedivide.o_quotient[1] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[1] Q=DIVIDE.thedivide.o_quotient[2] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[2] Q=DIVIDE.thedivide.o_quotient[3] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[3] Q=DIVIDE.thedivide.o_quotient[4] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[4] Q=DIVIDE.thedivide.o_quotient[5] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[5] Q=DIVIDE.thedivide.o_quotient[6] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[6] Q=DIVIDE.thedivide.o_quotient[7] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[7] Q=DIVIDE.thedivide.o_quotient[8] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[8] Q=DIVIDE.thedivide.o_quotient[9] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[9] Q=DIVIDE.thedivide.o_quotient[10] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[10] Q=DIVIDE.thedivide.o_quotient[11] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[11] Q=DIVIDE.thedivide.o_quotient[12] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[12] Q=DIVIDE.thedivide.o_quotient[13] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[13] Q=DIVIDE.thedivide.o_quotient[14] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[14] Q=DIVIDE.thedivide.o_quotient[15] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[15] Q=DIVIDE.thedivide.o_quotient[16] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[16] Q=DIVIDE.thedivide.o_quotient[17] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[17] Q=DIVIDE.thedivide.o_quotient[18] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[18] Q=DIVIDE.thedivide.o_quotient[19] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[19] Q=DIVIDE.thedivide.o_quotient[20] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[20] Q=DIVIDE.thedivide.o_quotient[21] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[21] Q=DIVIDE.thedivide.o_quotient[22] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[22] Q=DIVIDE.thedivide.o_quotient[23] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[23] Q=DIVIDE.thedivide.o_quotient[24] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[24] Q=DIVIDE.thedivide.o_quotient[25] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[25] Q=DIVIDE.thedivide.o_quotient[26] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[26] Q=DIVIDE.thedivide.o_quotient[27] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[27] Q=DIVIDE.thedivide.o_quotient[28] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[28] Q=DIVIDE.thedivide.o_quotient[29] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[29] Q=DIVIDE.thedivide.o_quotient[30] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[30] Q=DIVIDE.thedivide.w_n R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:372$1666_Y Q=DIVIDE.thedivide.r_c R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23642 Q=DIVIDE.thedivide.r_divisor[31] R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[0] Q=regset[9][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[1] Q=regset[9][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[2] Q=regset[9][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[3] Q=regset[9][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[4] Q=regset[9][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[5] Q=regset[9][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[6] Q=regset[9][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[7] Q=regset[9][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[8] Q=regset[9][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[9] Q=regset[9][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[10] Q=regset[9][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[11] Q=regset[9][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[12] Q=regset[9][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[13] Q=regset[9][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[14] Q=regset[9][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[15] Q=regset[9][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[16] Q=regset[9][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[17] Q=regset[9][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[18] Q=regset[9][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[19] Q=regset[9][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[20] Q=regset[9][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[21] Q=regset[9][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[22] Q=regset[9][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[23] Q=regset[9][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[24] Q=regset[9][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[25] Q=regset[9][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[26] Q=regset[9][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[27] Q=regset[9][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[28] Q=regset[9][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[29] Q=regset[9][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[30] Q=regset[9][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[31] Q=regset[9][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[0] Q=regset[8][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[1] Q=regset[8][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[2] Q=regset[8][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[3] Q=regset[8][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[4] Q=regset[8][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[5] Q=regset[8][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[6] Q=regset[8][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[7] Q=regset[8][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[8] Q=regset[8][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[9] Q=regset[8][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[10] Q=regset[8][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[11] Q=regset[8][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[12] Q=regset[8][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[13] Q=regset[8][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[14] Q=regset[8][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[15] Q=regset[8][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[16] Q=regset[8][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[17] Q=regset[8][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[18] Q=regset[8][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[19] Q=regset[8][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[20] Q=regset[8][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[21] Q=regset[8][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[22] Q=regset[8][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[23] Q=regset[8][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[24] Q=regset[8][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[25] Q=regset[8][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[26] Q=regset[8][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[27] Q=regset[8][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[28] Q=regset[8][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[29] Q=regset[8][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[30] Q=regset[8][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[31] Q=regset[8][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22626 Q=DIVIDE.thedivide.r_dividend[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22624 Q=DIVIDE.thedivide.r_dividend[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22622 Q=DIVIDE.thedivide.r_dividend[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22620 Q=DIVIDE.thedivide.r_dividend[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22618 Q=DIVIDE.thedivide.r_dividend[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22616 Q=DIVIDE.thedivide.r_dividend[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22614 Q=DIVIDE.thedivide.r_dividend[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22612 Q=DIVIDE.thedivide.r_dividend[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22610 Q=DIVIDE.thedivide.r_dividend[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22608 Q=DIVIDE.thedivide.r_dividend[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22606 Q=DIVIDE.thedivide.r_dividend[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22604 Q=DIVIDE.thedivide.r_dividend[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22602 Q=DIVIDE.thedivide.r_dividend[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22600 Q=DIVIDE.thedivide.r_dividend[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22598 Q=DIVIDE.thedivide.r_dividend[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22596 Q=DIVIDE.thedivide.r_dividend[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22594 Q=DIVIDE.thedivide.r_dividend[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22592 Q=DIVIDE.thedivide.r_dividend[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22590 Q=DIVIDE.thedivide.r_dividend[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22588 Q=DIVIDE.thedivide.r_dividend[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22586 Q=DIVIDE.thedivide.r_dividend[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22584 Q=DIVIDE.thedivide.r_dividend[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22582 Q=DIVIDE.thedivide.r_dividend[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22580 Q=DIVIDE.thedivide.r_dividend[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22578 Q=DIVIDE.thedivide.r_dividend[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22576 Q=DIVIDE.thedivide.r_dividend[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22574 Q=DIVIDE.thedivide.r_dividend[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22572 Q=DIVIDE.thedivide.r_dividend[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22570 Q=DIVIDE.thedivide.r_dividend[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22568 Q=DIVIDE.thedivide.r_dividend[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22566 Q=DIVIDE.thedivide.r_dividend[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23734 Q=DIVIDE.thedivide.r_dividend[32] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[0] Q=regset[6][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[1] Q=regset[6][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[2] Q=regset[6][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[3] Q=regset[6][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[4] Q=regset[6][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[5] Q=regset[6][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[6] Q=regset[6][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[7] Q=regset[6][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[8] Q=regset[6][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[9] Q=regset[6][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[10] Q=regset[6][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[11] Q=regset[6][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[12] Q=regset[6][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[13] Q=regset[6][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[14] Q=regset[6][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[15] Q=regset[6][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[16] Q=regset[6][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[17] Q=regset[6][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[18] Q=regset[6][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[19] Q=regset[6][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[20] Q=regset[6][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[21] Q=regset[6][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[22] Q=regset[6][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[23] Q=regset[6][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[24] Q=regset[6][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[25] Q=regset[6][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[26] Q=regset[6][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[27] Q=regset[6][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[28] Q=regset[6][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[29] Q=regset[6][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[30] Q=regset[6][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[31] Q=regset[6][31] +.subckt sdffr C=i_clk D=$abc$24881$auto$simplemap.cc:240:simplemap_eqne$9293[0] Q=DIVIDE.thedivide.o_err R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23650 Q=DIVIDE.thedivide.o_busy R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23652 Q=DIVIDE.thedivide.r_busy R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[0] Q=regset[29][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[1] Q=regset[29][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[2] Q=regset[29][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[3] Q=regset[29][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[4] Q=regset[29][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[5] Q=regset[29][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[6] Q=regset[29][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[7] Q=regset[29][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[8] Q=regset[29][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[9] Q=regset[29][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[10] Q=regset[29][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[11] Q=regset[29][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[12] Q=regset[29][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[13] Q=regset[29][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[14] Q=regset[29][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[15] Q=regset[29][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[16] Q=regset[29][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[17] Q=regset[29][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[18] Q=regset[29][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[19] Q=regset[29][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[20] Q=regset[29][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[21] Q=regset[29][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[22] Q=regset[29][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[23] Q=regset[29][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[24] Q=regset[29][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[25] Q=regset[29][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[26] Q=regset[29][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[27] Q=regset[29][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[28] Q=regset[29][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[29] Q=regset[29][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[30] Q=regset[29][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[31] Q=regset[29][31] +.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][0] Q=dcd_F[0] +.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] Q=dcd_F[1] +.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] Q=dcd_F[2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[0] Q=regset[20][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[1] Q=regset[20][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[2] Q=regset[20][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[3] Q=regset[20][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[4] Q=regset[20][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[5] Q=regset[20][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[6] Q=regset[20][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[7] Q=regset[20][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[8] Q=regset[20][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[9] Q=regset[20][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[10] Q=regset[20][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[11] Q=regset[20][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[12] Q=regset[20][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[13] Q=regset[20][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[14] Q=regset[20][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[15] Q=regset[20][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[16] Q=regset[20][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[17] Q=regset[20][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[18] Q=regset[20][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[19] Q=regset[20][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[20] Q=regset[20][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[21] Q=regset[20][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[22] Q=regset[20][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[23] Q=regset[20][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[24] Q=regset[20][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[25] Q=regset[20][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[26] Q=regset[20][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[27] Q=regset[20][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[28] Q=regset[20][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[29] Q=regset[20][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[30] Q=regset[20][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[31] Q=regset[20][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23554 Q=instruction_decoder.o_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23552 Q=instruction_decoder.o_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23550 Q=instruction_decoder.o_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23548 Q=instruction_decoder.o_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23546 Q=instruction_decoder.o_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23544 Q=instruction_decoder.o_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23542 Q=instruction_decoder.o_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23540 Q=instruction_decoder.o_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23538 Q=instruction_decoder.o_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23536 Q=instruction_decoder.o_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23534 Q=instruction_decoder.o_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23532 Q=instruction_decoder.o_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23530 Q=instruction_decoder.o_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23528 Q=instruction_decoder.o_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23526 Q=instruction_decoder.o_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23524 Q=instruction_decoder.o_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23522 Q=instruction_decoder.o_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23520 Q=instruction_decoder.o_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23518 Q=instruction_decoder.o_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23516 Q=instruction_decoder.o_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23514 Q=instruction_decoder.o_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23512 Q=instruction_decoder.o_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23510 Q=instruction_decoder.o_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23508 Q=instruction_decoder.o_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23506 Q=instruction_decoder.o_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23504 Q=instruction_decoder.o_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23502 Q=instruction_decoder.o_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23500 Q=instruction_decoder.o_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23498 Q=instruction_decoder.o_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23722 Q=instruction_decoder.o_pc[31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[0] Q=regset[7][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[1] Q=regset[7][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[2] Q=regset[7][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[3] Q=regset[7][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[4] Q=regset[7][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[5] Q=regset[7][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[6] Q=regset[7][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[7] Q=regset[7][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[8] Q=regset[7][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[9] Q=regset[7][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[10] Q=regset[7][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[11] Q=regset[7][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[12] Q=regset[7][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[13] Q=regset[7][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[14] Q=regset[7][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[15] Q=regset[7][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[16] Q=regset[7][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[17] Q=regset[7][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[18] Q=regset[7][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[19] Q=regset[7][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[20] Q=regset[7][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[21] Q=regset[7][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[22] Q=regset[7][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[23] Q=regset[7][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[24] Q=regset[7][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[25] Q=regset[7][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[26] Q=regset[7][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[27] Q=regset[7][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[28] Q=regset[7][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[29] Q=regset[7][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[30] Q=regset[7][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[31] Q=regset[7][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[0] Q=regset[31][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[1] Q=regset[31][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[2] Q=regset[31][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[3] Q=regset[31][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[4] Q=regset[31][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[5] Q=regset[31][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[6] Q=regset[31][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[7] Q=regset[31][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[8] Q=regset[31][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[9] Q=regset[31][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[10] Q=regset[31][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[11] Q=regset[31][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[12] Q=regset[31][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[13] Q=regset[31][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[14] Q=regset[31][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[15] Q=regset[31][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[16] Q=regset[31][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[17] Q=regset[31][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[18] Q=regset[31][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[19] Q=regset[31][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[20] Q=regset[31][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[21] Q=regset[31][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[22] Q=regset[31][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[23] Q=regset[31][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[24] Q=regset[31][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[25] Q=regset[31][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[26] Q=regset[31][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[27] Q=regset[31][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[28] Q=regset[31][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[29] Q=regset[31][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[30] Q=regset[31][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[31] Q=regset[31][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23496 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23494 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23492 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23490 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23488 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23486 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23484 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23482 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23480 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23478 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23476 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23474 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23472 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23470 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23468 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23466 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23464 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23462 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23460 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23458 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23456 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23454 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23452 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23450 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23448 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23446 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23444 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23442 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23440 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23724 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[0] Q=regset[21][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[1] Q=regset[21][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[2] Q=regset[21][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[3] Q=regset[21][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[4] Q=regset[21][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[5] Q=regset[21][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[6] Q=regset[21][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[7] Q=regset[21][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[8] Q=regset[21][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[9] Q=regset[21][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[10] Q=regset[21][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[11] Q=regset[21][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[12] Q=regset[21][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[13] Q=regset[21][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[14] Q=regset[21][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[15] Q=regset[21][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[16] Q=regset[21][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[17] Q=regset[21][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[18] Q=regset[21][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[19] Q=regset[21][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[20] Q=regset[21][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[21] Q=regset[21][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[22] Q=regset[21][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[23] Q=regset[21][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[24] Q=regset[21][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[25] Q=regset[21][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[26] Q=regset[21][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[27] Q=regset[21][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[28] Q=regset[21][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[29] Q=regset[21][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[30] Q=regset[21][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[31] Q=regset[21][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[0] Q=regset[24][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[1] Q=regset[24][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[2] Q=regset[24][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[3] Q=regset[24][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[4] Q=regset[24][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[5] Q=regset[24][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[6] Q=regset[24][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[7] Q=regset[24][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[8] Q=regset[24][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[9] Q=regset[24][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[10] Q=regset[24][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[11] Q=regset[24][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[12] Q=regset[24][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[13] Q=regset[24][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[14] Q=regset[24][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[15] Q=regset[24][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[16] Q=regset[24][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[17] Q=regset[24][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[18] Q=regset[24][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[19] Q=regset[24][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[20] Q=regset[24][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[21] Q=regset[24][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[22] Q=regset[24][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[23] Q=regset[24][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[24] Q=regset[24][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[25] Q=regset[24][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[26] Q=regset[24][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[27] Q=regset[24][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[28] Q=regset[24][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[29] Q=regset[24][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[30] Q=regset[24][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[31] Q=regset[24][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[0] Q=regset[22][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[1] Q=regset[22][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[2] Q=regset[22][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[3] Q=regset[22][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[4] Q=regset[22][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[5] Q=regset[22][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[6] Q=regset[22][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[7] Q=regset[22][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[8] Q=regset[22][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[9] Q=regset[22][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[10] Q=regset[22][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[11] Q=regset[22][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[12] Q=regset[22][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[13] Q=regset[22][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[14] Q=regset[22][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[15] Q=regset[22][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[16] Q=regset[22][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[17] Q=regset[22][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[18] Q=regset[22][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[19] Q=regset[22][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[20] Q=regset[22][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[21] Q=regset[22][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[22] Q=regset[22][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[23] Q=regset[22][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[24] Q=regset[22][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[25] Q=regset[22][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[26] Q=regset[22][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[27] Q=regset[22][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[28] Q=regset[22][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[29] Q=regset[22][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[30] Q=regset[22][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[31] Q=regset[22][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[0] Q=regset[26][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[1] Q=regset[26][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[2] Q=regset[26][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[3] Q=regset[26][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[4] Q=regset[26][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[5] Q=regset[26][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[6] Q=regset[26][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[7] Q=regset[26][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[8] Q=regset[26][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[9] Q=regset[26][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[10] Q=regset[26][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[11] Q=regset[26][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[12] Q=regset[26][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[13] Q=regset[26][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[14] Q=regset[26][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[15] Q=regset[26][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[16] Q=regset[26][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[17] Q=regset[26][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[18] Q=regset[26][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[19] Q=regset[26][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[20] Q=regset[26][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[21] Q=regset[26][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[22] Q=regset[26][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[23] Q=regset[26][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[24] Q=regset[26][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[25] Q=regset[26][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[26] Q=regset[26][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[27] Q=regset[26][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[28] Q=regset[26][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[29] Q=regset[26][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[30] Q=regset[26][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[31] Q=regset[26][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23438 Q=r_op_Av[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23436 Q=r_op_Av[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23434 Q=r_op_Av[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23432 Q=r_op_Av[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23430 Q=r_op_Av[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23428 Q=r_op_Av[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23426 Q=r_op_Av[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23424 Q=r_op_Av[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23422 Q=r_op_Av[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23420 Q=r_op_Av[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23418 Q=r_op_Av[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23416 Q=r_op_Av[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23414 Q=r_op_Av[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23412 Q=r_op_Av[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23410 Q=r_op_Av[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23408 Q=r_op_Av[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23406 Q=r_op_Av[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23404 Q=r_op_Av[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23402 Q=r_op_Av[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23400 Q=r_op_Av[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23398 Q=r_op_Av[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23396 Q=r_op_Av[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23394 Q=r_op_Av[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23392 Q=r_op_Av[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23390 Q=r_op_Av[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23388 Q=r_op_Av[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23386 Q=r_op_Av[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23384 Q=r_op_Av[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23382 Q=r_op_Av[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23380 Q=r_op_Av[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23378 Q=r_op_Av[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23556 Q=r_op_Av[31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[0] Q=regset[30][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[1] Q=regset[30][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[2] Q=regset[30][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[3] Q=regset[30][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[4] Q=regset[30][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[5] Q=regset[30][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[6] Q=regset[30][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[7] Q=regset[30][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[8] Q=regset[30][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[9] Q=regset[30][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[10] Q=regset[30][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[11] Q=regset[30][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[12] Q=regset[30][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[13] Q=regset[30][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[14] Q=regset[30][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[15] Q=regset[30][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[16] Q=regset[30][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[17] Q=regset[30][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[18] Q=regset[30][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[19] Q=regset[30][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[20] Q=regset[30][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[21] Q=regset[30][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[22] Q=regset[30][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[23] Q=regset[30][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[24] Q=regset[30][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[25] Q=regset[30][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[26] Q=regset[30][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[27] Q=regset[30][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[28] Q=regset[30][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[29] Q=regset[30][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[30] Q=regset[30][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[31] Q=regset[30][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[0] Q=regset[19][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[1] Q=regset[19][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[2] Q=regset[19][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[3] Q=regset[19][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[4] Q=regset[19][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[5] Q=regset[19][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[6] Q=regset[19][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[7] Q=regset[19][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[8] Q=regset[19][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[9] Q=regset[19][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[10] Q=regset[19][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[11] Q=regset[19][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[12] Q=regset[19][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[13] Q=regset[19][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[14] Q=regset[19][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[15] Q=regset[19][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[16] Q=regset[19][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[17] Q=regset[19][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[18] Q=regset[19][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[19] Q=regset[19][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[20] Q=regset[19][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[21] Q=regset[19][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[22] Q=regset[19][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[23] Q=regset[19][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[24] Q=regset[19][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[25] Q=regset[19][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[26] Q=regset[19][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[27] Q=regset[19][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[28] Q=regset[19][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[29] Q=regset[19][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[30] Q=regset[19][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[31] Q=regset[19][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[0] Q=regset[18][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[1] Q=regset[18][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[2] Q=regset[18][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[3] Q=regset[18][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[4] Q=regset[18][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[5] Q=regset[18][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[6] Q=regset[18][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[7] Q=regset[18][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[8] Q=regset[18][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[9] Q=regset[18][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[10] Q=regset[18][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[11] Q=regset[18][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[12] Q=regset[18][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[13] Q=regset[18][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[14] Q=regset[18][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[15] Q=regset[18][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[16] Q=regset[18][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[17] Q=regset[18][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[18] Q=regset[18][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[19] Q=regset[18][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[20] Q=regset[18][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[21] Q=regset[18][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[22] Q=regset[18][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[23] Q=regset[18][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[24] Q=regset[18][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[25] Q=regset[18][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[26] Q=regset[18][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[27] Q=regset[18][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[28] Q=regset[18][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[29] Q=regset[18][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[30] Q=regset[18][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[31] Q=regset[18][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[0] Q=regset[16][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[1] Q=regset[16][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[2] Q=regset[16][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[3] Q=regset[16][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[4] Q=regset[16][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[5] Q=regset[16][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[6] Q=regset[16][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[7] Q=regset[16][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[8] Q=regset[16][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[9] Q=regset[16][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[10] Q=regset[16][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[11] Q=regset[16][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[12] Q=regset[16][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[13] Q=regset[16][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[14] Q=regset[16][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[15] Q=regset[16][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[16] Q=regset[16][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[17] Q=regset[16][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[18] Q=regset[16][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[19] Q=regset[16][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[20] Q=regset[16][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[21] Q=regset[16][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[22] Q=regset[16][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[23] Q=regset[16][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[24] Q=regset[16][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[25] Q=regset[16][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[26] Q=regset[16][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[27] Q=regset[16][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[28] Q=regset[16][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[29] Q=regset[16][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[30] Q=regset[16][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[31] Q=regset[16][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[0] Q=regset[0][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[1] Q=regset[0][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[2] Q=regset[0][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[3] Q=regset[0][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[4] Q=regset[0][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[5] Q=regset[0][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[6] Q=regset[0][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[7] Q=regset[0][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[8] Q=regset[0][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[9] Q=regset[0][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[10] Q=regset[0][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[11] Q=regset[0][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[12] Q=regset[0][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[13] Q=regset[0][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[14] Q=regset[0][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[15] Q=regset[0][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[16] Q=regset[0][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[17] Q=regset[0][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[18] Q=regset[0][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[19] Q=regset[0][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[20] Q=regset[0][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[21] Q=regset[0][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[22] Q=regset[0][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[23] Q=regset[0][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[24] Q=regset[0][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[25] Q=regset[0][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[26] Q=regset[0][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[27] Q=regset[0][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[28] Q=regset[0][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[29] Q=regset[0][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[30] Q=regset[0][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[31] Q=regset[0][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[0] Q=regset[17][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[1] Q=regset[17][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[2] Q=regset[17][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[3] Q=regset[17][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[4] Q=regset[17][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[5] Q=regset[17][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[6] Q=regset[17][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[7] Q=regset[17][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[8] Q=regset[17][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[9] Q=regset[17][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[10] Q=regset[17][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[11] Q=regset[17][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[12] Q=regset[17][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[13] Q=regset[17][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[14] Q=regset[17][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[15] Q=regset[17][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[16] Q=regset[17][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[17] Q=regset[17][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[18] Q=regset[17][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[19] Q=regset[17][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[20] Q=regset[17][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[21] Q=regset[17][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[22] Q=regset[17][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[23] Q=regset[17][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[24] Q=regset[17][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[25] Q=regset[17][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[26] Q=regset[17][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[27] Q=regset[17][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[28] Q=regset[17][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[29] Q=regset[17][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[30] Q=regset[17][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[31] Q=regset[17][31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23376 Q=DIVIDE.thedivide.r_divisor[0] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23374 Q=DIVIDE.thedivide.r_divisor[1] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23372 Q=DIVIDE.thedivide.r_divisor[2] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23370 Q=DIVIDE.thedivide.r_divisor[3] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23368 Q=DIVIDE.thedivide.r_divisor[4] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23366 Q=DIVIDE.thedivide.r_divisor[5] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23364 Q=DIVIDE.thedivide.r_divisor[6] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23362 Q=DIVIDE.thedivide.r_divisor[7] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23360 Q=DIVIDE.thedivide.r_divisor[8] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23358 Q=DIVIDE.thedivide.r_divisor[9] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23356 Q=DIVIDE.thedivide.r_divisor[10] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23354 Q=DIVIDE.thedivide.r_divisor[11] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23352 Q=DIVIDE.thedivide.r_divisor[12] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23350 Q=DIVIDE.thedivide.r_divisor[13] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23348 Q=DIVIDE.thedivide.r_divisor[14] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23346 Q=DIVIDE.thedivide.r_divisor[15] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23344 Q=DIVIDE.thedivide.r_divisor[16] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23342 Q=DIVIDE.thedivide.r_divisor[17] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23340 Q=DIVIDE.thedivide.r_divisor[18] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23338 Q=DIVIDE.thedivide.r_divisor[19] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23336 Q=DIVIDE.thedivide.r_divisor[20] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23334 Q=DIVIDE.thedivide.r_divisor[21] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23332 Q=DIVIDE.thedivide.r_divisor[22] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23330 Q=DIVIDE.thedivide.r_divisor[23] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23328 Q=DIVIDE.thedivide.r_divisor[24] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23326 Q=DIVIDE.thedivide.r_divisor[25] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23324 Q=DIVIDE.thedivide.r_divisor[26] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23322 Q=DIVIDE.thedivide.r_divisor[27] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23320 Q=DIVIDE.thedivide.r_divisor[28] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23318 Q=DIVIDE.thedivide.r_divisor[29] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23644 Q=DIVIDE.thedivide.r_divisor[30] R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[0] Q=regset[1][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[1] Q=regset[1][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[2] Q=regset[1][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[3] Q=regset[1][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[4] Q=regset[1][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[5] Q=regset[1][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[6] Q=regset[1][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[7] Q=regset[1][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[8] Q=regset[1][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[9] Q=regset[1][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[10] Q=regset[1][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[11] Q=regset[1][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[12] Q=regset[1][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[13] Q=regset[1][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[14] Q=regset[1][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[15] Q=regset[1][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[16] Q=regset[1][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[17] Q=regset[1][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[18] Q=regset[1][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[19] Q=regset[1][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[20] Q=regset[1][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[21] Q=regset[1][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[22] Q=regset[1][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[23] Q=regset[1][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[24] Q=regset[1][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[25] Q=regset[1][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[26] Q=regset[1][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[27] Q=regset[1][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[28] Q=regset[1][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[29] Q=regset[1][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[30] Q=regset[1][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[31] Q=regset[1][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[0] Q=regset[15][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[1] Q=regset[15][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[2] Q=regset[15][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[3] Q=regset[15][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[4] Q=regset[15][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[5] Q=regset[15][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[6] Q=regset[15][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[7] Q=regset[15][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[8] Q=regset[15][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[9] Q=regset[15][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[10] Q=regset[15][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[11] Q=regset[15][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[12] Q=regset[15][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[13] Q=regset[15][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[14] Q=regset[15][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[15] Q=regset[15][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[16] Q=regset[15][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[17] Q=regset[15][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[18] Q=regset[15][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[19] Q=regset[15][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[20] Q=regset[15][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[21] Q=regset[15][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[22] Q=regset[15][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[23] Q=regset[15][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[24] Q=regset[15][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[25] Q=regset[15][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[26] Q=regset[15][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[27] Q=regset[15][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[28] Q=regset[15][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[29] Q=regset[15][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[30] Q=regset[15][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[31] Q=regset[15][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[0] Q=regset[14][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[1] Q=regset[14][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[2] Q=regset[14][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[3] Q=regset[14][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[4] Q=regset[14][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[5] Q=regset[14][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[6] Q=regset[14][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[7] Q=regset[14][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[8] Q=regset[14][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[9] Q=regset[14][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[10] Q=regset[14][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[11] Q=regset[14][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[12] Q=regset[14][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[13] Q=regset[14][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[14] Q=regset[14][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[15] Q=regset[14][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[16] Q=regset[14][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[17] Q=regset[14][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[18] Q=regset[14][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[19] Q=regset[14][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[20] Q=regset[14][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[21] Q=regset[14][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[22] Q=regset[14][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[23] Q=regset[14][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[24] Q=regset[14][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[25] Q=regset[14][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[26] Q=regset[14][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[27] Q=regset[14][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[28] Q=regset[14][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[29] Q=regset[14][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[30] Q=regset[14][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[31] Q=regset[14][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[0] Q=regset[2][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[1] Q=regset[2][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[2] Q=regset[2][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[3] Q=regset[2][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[4] Q=regset[2][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[5] Q=regset[2][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[6] Q=regset[2][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[7] Q=regset[2][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[8] Q=regset[2][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[9] Q=regset[2][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[10] Q=regset[2][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[11] Q=regset[2][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[12] Q=regset[2][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[13] Q=regset[2][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[14] Q=regset[2][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[15] Q=regset[2][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[16] Q=regset[2][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[17] Q=regset[2][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[18] Q=regset[2][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[19] Q=regset[2][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[20] Q=regset[2][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[21] Q=regset[2][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[22] Q=regset[2][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[23] Q=regset[2][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[24] Q=regset[2][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[25] Q=regset[2][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[26] Q=regset[2][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[27] Q=regset[2][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[28] Q=regset[2][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[29] Q=regset[2][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[30] Q=regset[2][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[31] Q=regset[2][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[0] Q=regset[13][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[1] Q=regset[13][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[2] Q=regset[13][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[3] Q=regset[13][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[4] Q=regset[13][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[5] Q=regset[13][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[6] Q=regset[13][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[7] Q=regset[13][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[8] Q=regset[13][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[9] Q=regset[13][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[10] Q=regset[13][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[11] Q=regset[13][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[12] Q=regset[13][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[13] Q=regset[13][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[14] Q=regset[13][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[15] Q=regset[13][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[16] Q=regset[13][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[17] Q=regset[13][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[18] Q=regset[13][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[19] Q=regset[13][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[20] Q=regset[13][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[21] Q=regset[13][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[22] Q=regset[13][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[23] Q=regset[13][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[24] Q=regset[13][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[25] Q=regset[13][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[26] Q=regset[13][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[27] Q=regset[13][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[28] Q=regset[13][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[29] Q=regset[13][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[30] Q=regset[13][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[31] Q=regset[13][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[0] Q=regset[3][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[1] Q=regset[3][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[2] Q=regset[3][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[3] Q=regset[3][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[4] Q=regset[3][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[5] Q=regset[3][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[6] Q=regset[3][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[7] Q=regset[3][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[8] Q=regset[3][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[9] Q=regset[3][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[10] Q=regset[3][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[11] Q=regset[3][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[12] Q=regset[3][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[13] Q=regset[3][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[14] Q=regset[3][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[15] Q=regset[3][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[16] Q=regset[3][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[17] Q=regset[3][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[18] Q=regset[3][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[19] Q=regset[3][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[20] Q=regset[3][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[21] Q=regset[3][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[22] Q=regset[3][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[23] Q=regset[3][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[24] Q=regset[3][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[25] Q=regset[3][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[26] Q=regset[3][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[27] Q=regset[3][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[28] Q=regset[3][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[29] Q=regset[3][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[30] Q=regset[3][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[31] Q=regset[3][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[0] Q=regset[12][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[1] Q=regset[12][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[2] Q=regset[12][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[3] Q=regset[12][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[4] Q=regset[12][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[5] Q=regset[12][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[6] Q=regset[12][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[7] Q=regset[12][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[8] Q=regset[12][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[9] Q=regset[12][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[10] Q=regset[12][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[11] Q=regset[12][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[12] Q=regset[12][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[13] Q=regset[12][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[14] Q=regset[12][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[15] Q=regset[12][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[16] Q=regset[12][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[17] Q=regset[12][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[18] Q=regset[12][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[19] Q=regset[12][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[20] Q=regset[12][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[21] Q=regset[12][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[22] Q=regset[12][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[23] Q=regset[12][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[24] Q=regset[12][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[25] Q=regset[12][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[26] Q=regset[12][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[27] Q=regset[12][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[28] Q=regset[12][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[29] Q=regset[12][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[30] Q=regset[12][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[31] Q=regset[12][31] +.names DIVIDE.thedivide.r_bit[1] $auto$alumacc.cc:485:replace_alu$3654.X[1] +1 1 +.names DIVIDE.thedivide.r_bit[2] $auto$alumacc.cc:485:replace_alu$3654.X[2] +1 1 +.names DIVIDE.thedivide.r_bit[3] $auto$alumacc.cc:485:replace_alu$3654.X[3] +1 1 +.names DIVIDE.thedivide.r_bit[4] $auto$alumacc.cc:485:replace_alu$3654.X[4] +1 1 +.names $auto$alumacc.cc:485:replace_alu$3654.X[0] $auto$alumacc.cc:485:replace_alu$3654.Y[0] +1 1 +.names DIVIDE.thedivide.w_n DIVIDE.thedivide.o_quotient[31] +1 1 +.names DIVIDE.thedivide.i_signed FWD_OPERATION.r_op_opn[0] +1 1 +.names o_mem_op[1] FWD_OPERATION.r_op_opn[1] +1 1 +.names o_mem_op[2] FWD_OPERATION.r_op_opn[2] +1 1 +.names $false GEN_ALU_PC.r_alu_pc[0] +1 1 +.names $false SET_OP_PC.r_op_pc[0] +1 1 +.names doalu.n alu_result[31] +1 1 +.names dcd_I[31] dcd_I[22] +1 1 +.names dcd_I[31] dcd_I[23] +1 1 +.names dcd_I[31] dcd_I[24] +1 1 +.names dcd_I[31] dcd_I[25] +1 1 +.names dcd_I[31] dcd_I[26] +1 1 +.names dcd_I[31] dcd_I[27] +1 1 +.names dcd_I[31] dcd_I[28] +1 1 +.names dcd_I[31] dcd_I[29] +1 1 +.names dcd_I[31] dcd_I[30] +1 1 +.names $false instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[0] +1 1 +.names $false instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[1] +1 1 +.names dcd_Apc instruction_decoder.o_dcdA[5] +1 1 +.names dcd_Acc instruction_decoder.o_dcdA[6] +1 1 +.names dcd_Bpc instruction_decoder.o_dcdB[5] +1 1 +.names dcd_Bcc instruction_decoder.o_dcdB[6] +1 1 +.names $false instruction_decoder.o_pc[0] +1 1 +.names $false o_debug[0] +1 1 +.names $false o_debug[1] +1 1 +.names $false o_debug[2] +1 1 +.names $false o_debug[3] +1 1 +.names $false o_debug[4] +1 1 +.names $false o_debug[5] +1 1 +.names $false o_debug[6] +1 1 +.names $false o_debug[7] +1 1 +.names $false o_debug[8] +1 1 +.names $false o_debug[9] +1 1 +.names $false o_debug[10] +1 1 +.names $false o_debug[11] +1 1 +.names $false o_debug[12] +1 1 +.names $false o_debug[13] +1 1 +.names $false o_debug[14] +1 1 +.names $false o_debug[15] +1 1 +.names $false o_debug[16] +1 1 +.names $false o_debug[17] +1 1 +.names $false o_debug[18] +1 1 +.names $false o_debug[19] +1 1 +.names $false o_debug[20] +1 1 +.names $false o_debug[21] +1 1 +.names $false o_debug[22] +1 1 +.names $false o_debug[23] +1 1 +.names $false o_debug[24] +1 1 +.names $false o_debug[25] +1 1 +.names $false o_debug[26] +1 1 +.names $false o_debug[27] +1 1 +.names $false o_debug[28] +1 1 +.names $false o_debug[29] +1 1 +.names $false o_debug[30] +1 1 +.names $false o_debug[31] +1 1 +.names $false o_mem_lock_pc[0] +1 1 +.names DIVIDE.thedivide.i_signed o_mem_op[0] +1 1 +.names $false o_pf_request_address[0] +1 1 +.names $false o_pf_request_address[1] +1 1 +.names $false o_prof_addr[0] +1 1 +.names $false o_prof_addr[1] +1 1 +.names $false o_prof_addr[2] +1 1 +.names $false o_prof_addr[3] +1 1 +.names $false o_prof_addr[4] +1 1 +.names $false o_prof_addr[5] +1 1 +.names $false o_prof_addr[6] +1 1 +.names $false o_prof_addr[7] +1 1 +.names $false o_prof_addr[8] +1 1 +.names $false o_prof_addr[9] +1 1 +.names $false o_prof_addr[10] +1 1 +.names $false o_prof_addr[11] +1 1 +.names $false o_prof_addr[12] +1 1 +.names $false o_prof_addr[13] +1 1 +.names $false o_prof_addr[14] +1 1 +.names $false o_prof_addr[15] +1 1 +.names $false o_prof_addr[16] +1 1 +.names $false o_prof_addr[17] +1 1 +.names $false o_prof_addr[18] +1 1 +.names $false o_prof_addr[19] +1 1 +.names $false o_prof_addr[20] +1 1 +.names $false o_prof_addr[21] +1 1 +.names $false o_prof_addr[22] +1 1 +.names $false o_prof_addr[23] +1 1 +.names $false o_prof_addr[24] +1 1 +.names $false o_prof_addr[25] +1 1 +.names $false o_prof_addr[26] +1 1 +.names $false o_prof_addr[27] +1 1 +.names $false o_prof_addr[28] +1 1 +.names $false o_prof_addr[29] +1 1 +.names $false o_prof_addr[30] +1 1 +.names $false o_prof_addr[31] +1 1 +.names $false o_prof_stb +1 1 +.names $false o_prof_ticks[0] +1 1 +.names $false o_prof_ticks[1] +1 1 +.names $false o_prof_ticks[2] +1 1 +.names $false o_prof_ticks[3] +1 1 +.names $false o_prof_ticks[4] +1 1 +.names $false o_prof_ticks[5] +1 1 +.names $false o_prof_ticks[6] +1 1 +.names $false o_prof_ticks[7] +1 1 +.names $false o_prof_ticks[8] +1 1 +.names $false o_prof_ticks[9] +1 1 +.names $false o_prof_ticks[10] +1 1 +.names $false o_prof_ticks[11] +1 1 +.names $false o_prof_ticks[12] +1 1 +.names $false o_prof_ticks[13] +1 1 +.names $false o_prof_ticks[14] +1 1 +.names $false o_prof_ticks[15] +1 1 +.names $false o_prof_ticks[16] +1 1 +.names $false o_prof_ticks[17] +1 1 +.names $false o_prof_ticks[18] +1 1 +.names $false o_prof_ticks[19] +1 1 +.names $false o_prof_ticks[20] +1 1 +.names $false o_prof_ticks[21] +1 1 +.names $false o_prof_ticks[22] +1 1 +.names $false o_prof_ticks[23] +1 1 +.names $false o_prof_ticks[24] +1 1 +.names $false o_prof_ticks[25] +1 1 +.names $false o_prof_ticks[26] +1 1 +.names $false o_prof_ticks[27] +1 1 +.names $false o_prof_ticks[28] +1 1 +.names $false o_prof_ticks[29] +1 1 +.names $false o_prof_ticks[30] +1 1 +.names $false o_prof_ticks[31] +1 1 +.names $false pf_pc[0] +1 1 +.names $false pf_pc[1] +1 1 +.names $false wr_index[2] +1 1 +.end From ec6da7f2496c92998d6a5c609757bed28dcc5ab7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Jan 2025 11:31:39 -0800 Subject: [PATCH 420/453] [core] syntax --- libs/EXTERNAL/libcatch2 | 2 +- libs/EXTERNAL/sockpp | 2 +- vpr/src/base/SetupVPR.cpp | 21 ++++++++----------- vpr/src/route/connection_router.cpp | 10 ++++----- .../tileable_rr_graph_edge_builder.cpp | 20 +----------------- .../tileable_rr_graph_edge_builder.h | 9 -------- .../tileable_rr_graph_gsb.cpp | 15 +++---------- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 1 - 8 files changed, 19 insertions(+), 61 deletions(-) diff --git a/libs/EXTERNAL/libcatch2 b/libs/EXTERNAL/libcatch2 index 119a7bbe53a..fa43b77429b 160000 --- a/libs/EXTERNAL/libcatch2 +++ b/libs/EXTERNAL/libcatch2 @@ -1 +1 @@ -Subproject commit 119a7bbe53ae8959f51c021c63bbd5a1734c5261 +Subproject commit fa43b77429ba76c462b1898d6cd2f2d7a9416b14 diff --git a/libs/EXTERNAL/sockpp b/libs/EXTERNAL/sockpp index 599f750c8b6..5388c4b5659 160000 --- a/libs/EXTERNAL/sockpp +++ b/libs/EXTERNAL/sockpp @@ -1 +1 @@ -Subproject commit 599f750c8b6532950d4bb43b2b756700e41dbae9 +Subproject commit 5388c4b5659e99a86bc906dd6ac2eef66f1dd51e diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index d571390b7dd..53c6831b676 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -44,13 +44,12 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch); static void SetupVibInf(const std::vector& PhysicalTileTypes, - const int num_switches, - const t_arch_switch_inf* Switches, + const std::vector& Switches, const std::vector& Segments, std::vector& vib_infs); static void ProcessFromOrToTokens(const std::vector Tokens, const std::vector& PhysicalTileTypes, const std::vector segments, std::vector& froms); -static void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); +static void parse_pin_name(const char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); /** @@ -242,7 +241,7 @@ void SetupVPR(const t_options* options, routingArch->write_rr_graph_filename = options->write_rr_graph_file; routingArch->read_rr_graph_filename = options->read_rr_graph_file; - SetupVibInf(device_ctx.physical_tile_types, arch->num_switches, arch->Switches, arch->Segments, arch->vib_infs); + SetupVibInf(device_ctx.physical_tile_types, arch->switches, arch->Segments, arch->vib_infs); for (auto has_global_routing : arch->layer_global_routing) { device_ctx.inter_cluster_prog_routing_resources.emplace_back(has_global_routing); @@ -1019,14 +1018,13 @@ static void do_reachability_analysis(t_physical_tile_type* physical_tile, } static void SetupVibInf(const std::vector& PhysicalTileTypes, - const int num_switches, - const t_arch_switch_inf* Switches, + const std::vector& switches, const std::vector& Segments, std::vector& vib_infs) { VTR_ASSERT(!vib_infs.empty()); for (auto& vib_inf : vib_infs) { - for (int i_switch = 0; i_switch < num_switches; i_switch++) { - if (vib_inf.get_switch_name() == Switches[i_switch].name) { + for (size_t i_switch = 0; i_switch < switches.size(); i_switch++) { + if (vib_inf.get_switch_name() == switches[i_switch].name) { vib_inf.set_switch_idx(i_switch); break; } @@ -1095,7 +1093,7 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s port_name = nullptr; pb_type_name = new char[strlen(Token_char)]; port_name = new char[strlen(Token_char)]; - parse_pin_name((char*)Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); + parse_pin_name(Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); std::vector all_sub_tile_to_tile_pin_indices; for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { @@ -1213,17 +1211,16 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s } } -static void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name) { +static void parse_pin_name(const char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name) { /* Parses out the pb_type_name and port_name * * If the start_pin_index and end_pin_index is specified, parse them too. * * Return the values parsed by reference. */ char source_string[128]; - char* find_format = nullptr; int ichar, match_count; // parse out the pb_type and port name, possibly pin_indices - find_format = strstr(src_string, "["); + const char* find_format = strstr(src_string, "["); if (find_format == nullptr) { /* Format "pb_type_name.port_name" */ *start_pin_index = *end_pin_index = -1; diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index 4a880ae7234..8ec7ecc8e2a 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -1064,18 +1064,16 @@ static inline void update_router_stats(RouterStats* router_stats, auto node_type = rr_graph->node_type(rr_node_id); VTR_ASSERT(node_type != NUM_RR_TYPES); - + /* TODO: Eliminate the use of global var here!!! */ const VibInf* vib; - if (!device_ctx.arch->vib_infs.empty()) { - vib = device_ctx.vib_grid[rr_graph->node_layer(rr_node_id)][rr_graph->node_xlow(rr_node_id)][rr_graph->node_ylow(rr_node_id)]; + if (!g_vpr_ctx.device().arch->vib_infs.empty()) { + vib = g_vpr_ctx.device().vib_grid.get_vib(rr_graph->node_layer(rr_node_id), rr_graph->node_xlow(rr_node_id), rr_graph->node_ylow(rr_node_id)); } else { vib = nullptr; } if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - auto node_type = rr_graph->node_type(rr_node_id); - VTR_ASSERT(node_type != NUM_RR_TYPES); - + t_physical_tile_type_ptr physical_type = g_vpr_ctx.device().grid.get_physical_type({rr_graph->node_xlow(rr_node_id), rr_graph->node_ylow(rr_node_id), rr_graph->node_layer(rr_node_id)}); if (is_inter_cluster_node(physical_type, vib, node_type, rr_graph->node_ptc_num(rr_node_id))) { if (is_push) { router_stats->inter_cluster_node_pushes++; diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index 17a1c8cb9a5..d242a0b9bf1 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -134,16 +134,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, segment_inf, segment_inf_x, segment_inf_y, - Fc_in, - Fc_out, - sb_type, - Fs, - sb_subtype, - subFs, perimeter_cb, - opin2all_sides, - concat_wire, - wire_opposite_side, delayless_switch); } else { @@ -375,16 +366,7 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, const std::vector& segment_inf, const std::vector& segment_inf_x, const std::vector& segment_inf_y, - const std::vector>& Fc_in, - const std::vector>& Fc_out, - const e_switch_block_type& sb_type, - const int& Fs, - const e_switch_block_type& sb_subtype, - const int& subFs, const bool& perimeter_cb, - const bool& opin2all_sides, - const bool& concat_wire, - const bool& wire_opposite_side, const RRSwitchId& delayless_switch) { /* Create map from medium mux name to index */ // std::vector>>> medium_mux_name2medium_index; @@ -423,7 +405,7 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, /* adapt the bend_conn */ t_bend_track2track_map sb_bend_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ sb_bend_conn = build_bend_track_to_track_map(grids, rr_graph_builder, rr_graph, - device_chan_width, segment_inf, + segment_inf, layer, gsb_coord, delayless_switch, rr_node_driver_switches); /* Create a GSB object */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h index 0028cfd0e93..a697c689be5 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -74,16 +74,7 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, const std::vector& segment_inf, const std::vector& segment_inf_x, const std::vector& segment_inf_y, - const std::vector>& Fc_in, - const std::vector>& Fc_out, - const e_switch_block_type& sb_type, - const int& Fs, - const e_switch_block_type& sb_subtype, - const int& subFs, const bool& perimeter_cb, - const bool& opin2all_sides, - const bool& concat_wire, - const bool& wire_opposite_side, const RRSwitchId& delayless_switch); void build_rr_graph_regular_edges(const RRGraphView& rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index a6633cfdd42..a3f2d7f70de 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -537,7 +537,6 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, RRGraphBuilder& rr_graph_builder, const RRGraphView& rr_graph, - const vtr::Point& device_chan_width, const std::vector& segment_inf, const size_t& layer, const vtr::Point& gsb_coordinate, @@ -582,12 +581,10 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, CHANY); for (auto inode : rr_nodes) { - VTR_ASSERT(rr_graph.node_type(inode) ==CHANY); + VTR_ASSERT(rr_graph.node_type(inode) == CHANY); Direction direction = rr_graph.node_direction(inode); size_t xlow = rr_graph.node_xlow(inode); - size_t xhigh = rr_graph.node_xhigh(inode); size_t ylow = rr_graph.node_ylow(inode); - size_t yhigh = rr_graph.node_yhigh(inode); int bend_start = rr_graph.node_bend_start(inode); int bend_end = rr_graph.node_bend_end(inode); @@ -624,9 +621,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(rr_graph.node_type(inode) == CHANX); Direction direction = rr_graph.node_direction(inode); size_t xlow = rr_graph.node_xlow(inode); - size_t xhigh = rr_graph.node_xhigh(inode); size_t ylow = rr_graph.node_ylow(inode); - size_t yhigh = rr_graph.node_yhigh(inode); int bend_start = rr_graph.node_bend_start(inode); int bend_end = rr_graph.node_bend_end(inode); @@ -661,9 +656,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANY); Direction direction = rr_graph.node_direction(inode); - size_t xlow = rr_graph.node_xlow(inode); size_t xhigh = rr_graph.node_xhigh(inode); - size_t ylow = rr_graph.node_ylow(inode); size_t yhigh = rr_graph.node_yhigh(inode); int bend_start = rr_graph.node_bend_start(inode); int bend_end = rr_graph.node_bend_end(inode); @@ -699,9 +692,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANX); Direction direction = rr_graph.node_direction(inode); - size_t xlow = rr_graph.node_xlow(inode); size_t xhigh = rr_graph.node_xhigh(inode); - size_t ylow = rr_graph.node_ylow(inode); size_t yhigh = rr_graph.node_yhigh(inode); int bend_start = rr_graph.node_bend_start(inode); int bend_end = rr_graph.node_bend_end(inode); @@ -726,7 +717,7 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, } } std::map bend_seg_head2bend_seg_end_map; - for (size_t ibend_seg = 0; ibend_seg < bend_seg_num; ibend_seg++) { + for (size_t ibend_seg = 0; ibend_seg < (size_t)bend_seg_num; ibend_seg++) { int bend_type = bend_seg_type[ibend_seg]; //bend_type 1:U 2:D VTR_ASSERT(bend_type == 1 || bend_type == 2); @@ -1820,7 +1811,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, const VibInf* vib = vib_grid.get_vib(layer, actual_coordinate.x(), actual_coordinate.y()); auto phy_type = grids.get_physical_type({(int)actual_coordinate.x(), (int)actual_coordinate.y(), (int)layer}); - VTR_ASSERT(!strcmp(vib->get_pbtype_name().c_str(), phy_type->name)); + VTR_ASSERT(vib->get_pbtype_name() == phy_type->name); const std::vector first_stages = vib->get_first_stages(); for (size_t i_first_stage = 0; i_first_stage < first_stages.size(); i_first_stage++) { std::vector froms = first_stages[i_first_stage].froms; diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 66a50524df7..5e7ca853700 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -46,7 +46,6 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, RRGraphBuilder& rr_graph_builder, const RRGraphView& rr_graph, - const vtr::Point& device_chan_width, const std::vector& segment_inf, const size_t& layer, const vtr::Point& gsb_coordinate, From bb5235ea7a4f523e4c76bde30e2e7c00cef96858 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 16 Jan 2025 17:26:24 -0800 Subject: [PATCH 421/453] [core] clang warning --- libs/libarchfpga/src/vib_inf.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/vib_inf.cpp b/libs/libarchfpga/src/vib_inf.cpp index 33b77a17f59..4fcebadfebd 100644 --- a/libs/libarchfpga/src/vib_inf.cpp +++ b/libs/libarchfpga/src/vib_inf.cpp @@ -125,7 +125,7 @@ size_t VibInf::medium_mux_index_by_name(const std::string& name) const{ return i_medium; } } - VTR_LOG_ERROR("No medium mux named %s!", name); + VTR_LOG_ERROR("No medium mux named %s!", name.c_str()); } From 0eb7de5e9b63385d431c0ed43019d638dd6549c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 16 Jan 2025 21:39:33 -0800 Subject: [PATCH 422/453] [core] clang warning --- vpr/src/base/SetupVibGrid.cpp | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/vpr/src/base/SetupVibGrid.cpp b/vpr/src/base/SetupVibGrid.cpp index 8892e7056f8..cb8b844d94e 100644 --- a/vpr/src/base/SetupVibGrid.cpp +++ b/vpr/src/base/SetupVibGrid.cpp @@ -157,7 +157,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ if (startx > grid_width - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", - type->get_name(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); + type->get_name().c_str(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); } continue; //No instances will be created } @@ -165,7 +165,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ if (starty > grid_height - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", - type->get_name(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); + type->get_name().c_str(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); } continue; //No instances will be created } @@ -174,14 +174,14 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ if (endx > grid_width - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", - type->get_name(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); + type->get_name().c_str(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); } } if (endy > grid_height - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", - type->get_name(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); + type->get_name().c_str(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); } } @@ -204,7 +204,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incrx for block type '%s' must be at least" " block width (%d) to avoid overlapping instances (was %s = %d)", - type->get_name(), 1, xspec.incr_expr.c_str(), incrx); + type->get_name().c_str(), 1, xspec.incr_expr.c_str(), incrx); } //VTR_ASSERT(type->height > 0); @@ -212,7 +212,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incry for block type '%s' must be at least" " block height (%d) to avoid overlapping instances (was %s = %d)", - type->get_name(), 1, yspec.incr_expr.c_str(), incry); + type->get_name().c_str(), 1, yspec.incr_expr.c_str(), incry); } //The minimum repeat is the region dimension @@ -221,7 +221,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification repeatx for block type '%s' must be at least" " the region width (%d) to avoid overlapping instances (was %s = %d)", - type->get_name(), region_width, xspec.repeat_expr.c_str(), repeatx); + type->get_name().c_str(), region_width, xspec.repeat_expr.c_str(), repeatx); } size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive @@ -229,7 +229,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification repeaty for block type '%s' must be at least" " the region height (%d) to avoid overlapping instances (was %s = %d)", - type->get_name(), region_height, xspec.repeat_expr.c_str(), repeaty); + type->get_name().c_str(), region_height, xspec.repeat_expr.c_str(), repeaty); } //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", @@ -325,7 +325,7 @@ static void set_vib_grid_block_type(int priority, //Lower priority, do not override #ifdef VERBOSE VTR_LOG("Not creating block '%s' at (%zu,%zu) since overlaps block '%s' at (%zu,%zu) with higher priority (%d > %d)\n", - type->name, x_root, y_root, max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, + type->name.c_str(), x_root, y_root, max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, max_priority_type_loc.priority, priority); #endif return; @@ -341,8 +341,8 @@ static void set_vib_grid_block_type(int priority, " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." " The last specification will apply.\n", x_root, y_root, - max_priority_type_loc.type->get_name(), max_priority_type_loc.x, max_priority_type_loc.y, - priority, type->get_name()); + max_priority_type_loc.type->get_name().c_str(), max_priority_type_loc.x, max_priority_type_loc.y, + priority, type->get_name().c_str()); } //Mark all the grid tiles 'covered' by this block with the appropriate type @@ -405,9 +405,9 @@ static void set_vib_grid_block_type(int priority, #ifdef VERBOSE VTR_LOG("Ripping up block '%s' at (%d,%d) offset (%d,%d). Overlapped by '%s' at (%d,%d)\n", - invalidated_root.type->name, invalidated_root.x, invalidated_root.y, + invalidated_root.type->name.c_str(), invalidated_root.x, invalidated_root.y, x_offset, y_offset, - type->name, x_root, y_root); + type->name.c_str(), x_root, y_root); #endif vib_grid[layer_num][x][y] = nullptr; From 6aa89f20b0fc26b6b4f616f07a5446a9e6dc3b51 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 16 Jan 2025 21:40:18 -0800 Subject: [PATCH 423/453] [core] compiler warning --- vpr/src/base/SetupVibGrid.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/vpr/src/base/SetupVibGrid.cpp b/vpr/src/base/SetupVibGrid.cpp index cb8b844d94e..d34343aacaf 100644 --- a/vpr/src/base/SetupVibGrid.cpp +++ b/vpr/src/base/SetupVibGrid.cpp @@ -348,7 +348,6 @@ static void set_vib_grid_block_type(int priority, //Mark all the grid tiles 'covered' by this block with the appropriate type //and width/height offsets std::set root_blocks_to_rip_up; - auto& device_ctx = g_vpr_ctx.device(); for (size_t x = x_root; x < x_root + 1; ++x) { VTR_ASSERT(x < vib_grid.end_index(1)); From 195980566cacc84bec10509d3f05c0dcd68168c2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 17 Jan 2025 10:19:26 -0800 Subject: [PATCH 424/453] [core] clang syntax --- vpr/src/base/SetupVibGrid.cpp | 4 ++-- vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 10 +++++----- .../tileable_rr_graph_node_builder.cpp | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/vpr/src/base/SetupVibGrid.cpp b/vpr/src/base/SetupVibGrid.cpp index d34343aacaf..98bd676f058 100644 --- a/vpr/src/base/SetupVibGrid.cpp +++ b/vpr/src/base/SetupVibGrid.cpp @@ -189,13 +189,13 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ if (endx < startx) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", - xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->get_name()); + xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->get_name().c_str()); } if (endy < starty) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", - yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->get_name()); + yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->get_name().c_str()); } //The minimum increment is the block dimension diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index a3f2d7f70de..a0e8494718a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1371,7 +1371,7 @@ static void build_gsb_one_ipin_track2pin_map(const RRGraphView& rr_graph, } /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ - int track_cnt = 0; + //int track_cnt = 0; /* Keep assigning until we meet the Fc requirement */ for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) { /* Update pin2track map */ @@ -1388,7 +1388,7 @@ static void build_gsb_one_ipin_track2pin_map(const RRGraphView& rr_graph, track2ipin_map[chan_side_index][track_index].push_back(ipin_node); - track_cnt += 2; + //track_cnt += 2; } /* Ensure the number of tracks is similar to Fc */ @@ -1835,7 +1835,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!from_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, - "Can not find from node %s:%d!\n", from.type_name, from.phy_pin_index); + "Can not find from node %s:%d!\n", from.type_name.c_str(), from.phy_pin_index); continue; } if (!rr_gsb.is_opin_node(from_node)) { @@ -1946,7 +1946,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!to_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, - "Can not find from node %s:%d!\n", to.type_name, to.phy_pin_index); + "Can not find from node %s:%d!\n", to.type_name.c_str(), to.phy_pin_index); continue; } if (!rr_gsb.is_ipin_node(to_node)) { @@ -2034,7 +2034,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!from_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, - "Can not find from node %s:%d!\n", from.type_name, from.phy_pin_index); + "Can not find from node %s:%d!\n", from.type_name.c_str(), from.phy_pin_index); continue; } if (!rr_gsb.is_opin_node(from_node)) { diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index eec63682481..08d80b5936d 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -103,7 +103,7 @@ static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, auto first_stage = vib->get_first_stages()[i_first_stage]; if (first_stage.froms.size() == 0) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "VIB first stage '%s' at (%d, %d) has no from!\n", first_stage.mux_name, ix, iy); + "VIB first stage '%s' at (%d, %d) has no from!\n", first_stage.mux_name.c_str(), ix, iy); exit(1); } count++; From 9e417cffb7cfd1e6dbffb693b490972fe535841c Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 18 Jan 2025 10:37:59 +0800 Subject: [PATCH 425/453] Update vib_test_arch.xml --- vtr_flow/arch/VIB/vib_test_arch.xml | 31846 ++++++++------------------ 1 file changed, 9137 insertions(+), 22709 deletions(-) diff --git a/vtr_flow/arch/VIB/vib_test_arch.xml b/vtr_flow/arch/VIB/vib_test_arch.xml index 48c5040b732..eb3ba461032 100644 --- a/vtr_flow/arch/VIB/vib_test_arch.xml +++ b/vtr_flow/arch/VIB/vib_test_arch.xml @@ -1,26861 +1,13289 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - + - - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - - io_left_pi[6:0].a2f_o io_left_pi.lclk io_left_pi.lreset io_left_pi.clk io_left_pi.reset io_left_pi.sc_in io_left_pi.sc_out - - - - - + + - + - - - - - - - + + + - - - + io_topL[7:0].outpad io_topL[7:0].inpad io_topL.clock + - io_left_po[13:0].f2a_i io_left_po.lclk io_left_po.lreset io_left_po.clk io_left_po.reset io_left_po.sc_in io_left_po.sc_out - - - - - - - - - - - - - - - - - - - - - - - - io_right_pi[5:0].a2f_o io_right_pi.lclk io_right_pi.lreset io_right_pi.clk io_right_pi.reset io_right_pi.sc_in io_right_pi.sc_out - - - + + - + - - - - - - - + + + - - - + io_leftL[7:0].outpad io_leftL[7:0].inpad io_leftL.clock - - io_right_po[5:0].f2a_i io_right_po.lclk io_right_po.lreset io_right_po.clk io_right_po.reset io_right_po.sc_in io_right_po.sc_out - - - - - - - - - - - - - - - - - - - - - - - - - io_top_pi[23:0].a2f_o io_top_pi.lclk io_top_pi.lreset io_top_pi.clk io_top_pi.reset io_top_pi.sc_in io_top_pi.sc_out - - - - - - - - - - - - - - - - - - - - - - - - io_top_po[6:0].f2a_i io_top_po.lclk io_top_po.lreset io_top_po.clk io_top_po.reset io_top_po.sc_in io_top_po.sc_out - - - - - - - - - - - - - - - - - - - - io_bottom_pi[3:0].a2f_o io_bottom_pi.lclk io_bottom_pi.lreset io_bottom_pi.clk io_bottom_pi.reset io_bottom_pi.sc_in io_bottom_pi.sc_out - - - - - - + + - + - - - - - - - + + + - - - - io_bottom_po[7:0].f2a_i io_bottom_po.lclk io_bottom_po.lreset io_bottom_po.clk io_bottom_po.reset io_bottom_po.sc_in io_bottom_po.sc_out + io_rightL[7:0].outpad io_rightL[7:0].inpad io_rightL.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk clb.reset - clb.cin - clb.I0[4:0] clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.I5[4:0] clb.O[11:0] clb.I6[4:0] clb.I7[4:0] clb.I8[4:0] clb.I9[4:0] clb.I10[4:0] clb.I11[4:0] clb.O[23:12] - clb.cout - - - - - - - - - - - - - - - - - - - - - - - - - - io_top_dsp_pi[23:0].a2f_o io_top_dsp_pi.clk io_top_dsp_pi.reset io_top_dsp_pi.lclk io_top_dsp_pi.lreset io_top_dsp_pi.sc_in io_top_dsp_pi.sc_out - - - - - - - - - - - - - - - - - - - - - - - - io_top_dsp_po[6:0].f2a_i io_top_dsp_po.clk io_top_dsp_po.reset io_top_dsp_po.lclk io_top_dsp_po.lreset io_top_dsp_po.sc_in io_top_dsp_po.sc_out - - - - - - - - - - - - - - - - - - - - - - - - - - io_top_ram_pi[23:0].a2f_o io_top_ram_pi.clk io_top_ram_pi.reset io_top_ram_pi.lclk io_top_ram_pi.lreset io_top_ram_pi.sc_in io_top_ram_pi.sc_out - - - - - - - - - - - - - - - - - - - - - - - io_top_ram_po[6:0].f2a_i io_top_ram_po.clk io_top_ram_po.reset io_top_ram_po.lclk io_top_ram_po.lreset io_top_ram_po.sc_in io_top_ram_po.sc_out - - - - - - - - - - - - - - - - - - - - - - - io_bottom_dsp_pi[3:0].a2f_o io_bottom_dsp_pi.clk io_bottom_dsp_pi.reset io_bottom_dsp_pi.lclk io_bottom_dsp_pi.lreset io_bottom_dsp_pi.sc_in io_bottom_dsp_pi.sc_out - - - - - - - - - - - - - - - - - - - - - - - - io_bottom_dsp_po[7:0].f2a_i io_bottom_dsp_po.clk io_bottom_dsp_po.reset io_bottom_dsp_po.lclk io_bottom_dsp_po.lreset io_bottom_dsp_po.sc_in io_bottom_dsp_po.sc_out - - - - - + + - + - - - - - - - + + + - - - - io_bottom_ram_pi[3:0].a2f_o io_bottom_ram_pi.clk io_bottom_ram_pi.reset io_bottom_ram_pi.lclk io_bottom_ram_pi.lreset io_bottom_ram_pi.sc_in io_bottom_ram_pi.sc_out + io_bottomL[7:0].outpad io_bottomL[7:0].inpad io_bottomL.clock - - - - - - - - - - - - - - - - - - - - - - io_bottom_ram_po[7:0].f2a_i io_bottom_ram_po.clk io_bottom_ram_po.reset io_bottom_ram_po.lclk io_bottom_ram_po.lreset io_bottom_ram_po.sc_in io_bottom_ram_po.sc_out - - - - - - - - - - - - - - - - - - - - - - - dsp.clk dsp.reset - dsp.a[0:11] dsp.b[0:9] dsp.q_o[0:11] dsp.lclk dsp.lreset - dsp.a[24:35] dsp.b[20:29] dsp.q_o[12:23] - dsp.a[36:47] dsp.b[30:39] dsp.q_o[24:35] - dsp.a[12:23] dsp.b[10:19] dsp.q_o[36:43] - - - - - - - - - - - - - - - - - - - - - - - - - - ram9k.clk ram9k.mem_index - ram9k.raddr_i[0:2] ram9k.waddr_i[0:2] ram9k.data_i[0:8] ram9k.bwen_ni[0:8] ram9k.q_o[0:11] ram9k.lclk ram9k.lreset - ram9k.raddr_i[3:5] ram9k.waddr_i[3:5] ram9k.data_i[18:26] ram9k.bwen_ni[18:26] ram9k.q_o[12:23] - ram9k.raddr_i[6:8] ram9k.waddr_i[6:8] ram9k.data_i[27:35] ram9k.bwen_ni[27:35] ram9k.q_o[24:35] - ram9k.wen_ni ram9k.ren_ni ram9k.raddr_i[9:10] ram9k.waddr_i[9:10] ram9k.data_i[9:17] ram9k.bwen_ni[9:17] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - 1 - - - - 1 0 1 - 1 1 - - - - 1 0 0 1 - 1 0 1 - - - - 1 0 0 0 1 - 1 0 0 1 - - - - 1 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 1 - - - - - - U - - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1.67286e-10 - 1.67286e-10 - 1.67286e-10 - 1.67286e-10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2.25042e-10 - 2.25042e-10 - 2.25042e-10 - 2.25042e-10 - 2.25042e-10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 clb.O[8] - - - l1.W2 l2.W1 l4.W3 clb.O[0] - - - l1.W3 l3.W5 l8.W7 clb.O[16] - - - l1.W4 l3.W8 l8.W15 - - - l1.N5 l1.N6 l3.N11 clb.O[9] - - - l1.N7 l2.N3 l4.N7 clb.O[1] - - - l1.N8 l3.N14 l8.N7 clb.O[17] - - - l1.N9 l3.N17 l8.N15 - - - l1.E10 l1.E11 l3.E20 clb.O[10] - - - l1.E12 l2.E5 l4.E11 clb.O[2] - - - l1.E0 l3.E23 l8.E7 clb.O[18] - - - l1.E1 l3.E2 l8.E15 - - - l1.S2 l1.S3 l3.S5 clb.O[11] - - - l1.S4 l2.S1 l4.S15 clb.O[3] - - - l1.S5 l3.S8 l8.S7 clb.O[19] - - - l1.S6 l3.S11 l8.S15 - - - l1.W7 l1.W8 l3.W14 clb.O[12] - - - l1.W9 l2.W3 l4.W3 clb.O[4] - - - l1.W10 l3.W17 l8.W7 clb.O[20] - - - l1.W11 l3.W20 l8.W15 - - - l1.N12 l1.N0 l3.N23 clb.O[13] - - - l1.N1 l2.N5 l4.N7 clb.O[5] - - - l1.N2 l3.N2 l8.N7 clb.O[21] - - - l1.N3 l3.N5 l8.N15 - - - l1.E4 l1.E5 l3.E8 clb.O[14] - - - l1.E6 l2.E1 l4.E11 clb.O[6] - - - l1.E7 l3.E11 l8.E7 clb.O[22] - - - l1.E8 l3.E14 l8.E15 - - - l1.S9 l1.S10 l3.S17 clb.O[15] - - - l1.S11 l2.S3 l4.S15 clb.O[7] - - - l1.S12 l3.S20 l8.S7 clb.O[23] - - - l1.S0 l3.S23 l8.S15 - - - l1.W1 l1.W2 l3.W2 clb.O[8] - - - l1.W3 l2.W5 l4.W3 clb.O[0] - - - l1.W4 l3.W5 l8.W7 clb.O[16] - - - l1.W5 l3.W8 l8.W15 - - - l1.N6 l1.N7 l3.N11 clb.O[9] - - - l1.N8 l2.N1 l4.N7 clb.O[1] - - - l1.N9 l3.N14 l8.N7 clb.O[17] - - - l1.N10 l3.N17 l8.N15 - - - l1.E11 l1.E12 l3.E20 clb.O[10] - - - l1.E0 l2.E3 l4.E11 clb.O[2] - - - l1.E1 l3.E23 l8.E7 clb.O[18] - - - l1.E2 l3.E2 l8.E15 - - - l1.S3 l1.S4 l3.S5 clb.O[11] - - - l1.S5 l2.S5 l4.S15 clb.O[3] - - - l1.S6 l3.S8 l8.S7 clb.O[19] - - - l1.S7 l3.S11 l8.S15 - - - l1.W8 l1.W9 l3.W14 clb.O[12] - - - l1.W10 l2.W1 l4.W3 clb.O[4] - - - l1.W11 l3.W17 l8.W7 clb.O[20] - - - l1.W12 l3.W20 l8.W15 - - - l1.N0 l1.N1 l3.N23 clb.O[13] - - - l1.N2 l2.N3 l4.N7 clb.O[5] - - - l1.N3 l3.N2 l8.N7 clb.O[21] - - - l1.N4 l3.N5 l8.N15 - - - l1.E5 l1.E6 l3.E8 clb.O[14] - - - l1.E7 l2.E5 l4.E11 clb.O[6] - - - l1.E8 l3.E11 l8.E7 clb.O[22] - - - l1.E9 l3.E14 l8.E15 - - - l1.S10 l1.S11 l3.S17 clb.O[15] - - - l1.S12 l2.S1 l4.S15 clb.O[7] - - - l1.S0 l3.S20 l8.S7 clb.O[23] - - - l1.S1 l3.S23 l8.S15 - - - l1.W2 l1.W3 l3.W2 clb.O[8] - - - l1.W4 l2.W3 l4.W3 clb.O[0] - - - l1.W5 l3.W5 l8.W7 clb.O[16] - - - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 clb.O[9] - - - l1.N9 l2.N5 l4.N7 clb.O[1] - - - l1.N10 l3.N14 l8.N7 clb.O[17] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 clb.O[10] - - - l1.E1 l2.E1 l4.E11 clb.O[2] - - - l1.E2 l3.E23 l8.E7 clb.O[18] - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 clb.O[11] - - - l1.S6 l2.S3 l4.S15 clb.O[3] - - - l1.S7 l3.S8 l8.S7 clb.O[19] - - - l1.S8 l3.S11 l8.S15 - - - l1.W9 l1.W10 l3.W14 clb.O[12] - - - l1.W11 l2.W5 l4.W3 clb.O[4] - - - l1.W12 l3.W17 l8.W7 clb.O[20] - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 clb.O[13] - - - l1.N3 l2.N1 l4.N7 clb.O[5] - - - l1.N4 l3.N2 l8.N7 clb.O[21] - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 clb.O[14] - - - l1.E8 l2.E3 l4.E11 clb.O[6] - - - l1.E9 l3.E11 l8.E7 clb.O[22] - - - l1.E10 l3.E14 l8.E15 - - - l1.S11 l1.S12 l3.S17 clb.O[15] - - - l1.S0 l2.S5 l4.S15 clb.O[7] - - - l1.S1 l3.S20 l8.S7 clb.O[23] - - - l1.S2 l3.S23 l8.S15 - - - l1.W3 l1.W4 l3.W2 clb.O[8] - - - l1.W5 l2.W1 l4.W3 clb.O[0] - - - l1.W6 l3.W5 l8.W7 clb.O[16] - - - l1.W7 l3.W8 l8.W15 - - - l1.N8 l1.N9 l3.N11 clb.O[9] - - - l1.N10 l2.N3 l4.N7 clb.O[1] - - - l1.N11 l3.N14 l8.N7 clb.O[17] - - - l1.N12 l3.N17 l8.N15 - - - l1.E0 l1.E1 l3.E20 clb.O[10] - - - l1.E2 l2.E5 l4.E11 clb.O[2] - - - l1.E3 l3.E23 l8.E7 clb.O[18] - - - l1.E4 l3.E2 l8.E15 - - - l1.S5 l1.S6 l3.S5 clb.O[11] - - - l1.S7 l2.S1 l4.S15 clb.O[3] - - - l1.S8 l3.S8 l8.S7 clb.O[19] - - - l1.S9 l3.S11 l8.S15 - - - l1.W10 l1.W11 l3.W14 clb.O[12] - - - l1.W12 l2.W3 l4.W3 clb.O[4] - - - l1.W0 l3.W17 l8.W7 clb.O[20] - - - l1.W1 l3.W20 l8.W15 - - - l1.N2 l1.N3 l3.N23 clb.O[13] - - - l1.N4 l2.N5 l4.N7 clb.O[5] - - - l1.N5 l3.N2 l8.N7 clb.O[21] - - - l1.N6 l3.N5 l8.N15 - - - l1.E7 l1.E8 l3.E8 clb.O[14] - - - l1.E9 l2.E1 l4.E11 clb.O[6] - - - l1.E10 l3.E11 l8.E7 clb.O[22] - - - l1.E11 l3.E14 l8.E15 - - - l1.S12 l1.S0 l3.S17 clb.O[15] - - - l1.S1 l2.S3 l4.S15 clb.O[7] - - - l1.S2 l3.S20 l8.S7 clb.O[23] - - - l1.S3 l3.S23 l8.S15 - - - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 clb.O[0] OG_0 - - - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 clb.O[8] - - - l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 clb.O[16] - - - l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 clb.O[1] - - - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 clb.O[9] - - - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 clb.O[17] OG_2 l1.N2 - - - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 clb.O[2] OG_2 l1.S4 - - - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 clb.O[10] OG_3 l1.N9 - - - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 clb.O[18] OG_4 - - - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 clb.O[3] - - - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 clb.O[11] - - - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 clb.O[19] - - - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 clb.O[4] - - - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 clb.O[12] OG_6 l1.E5 - - - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 clb.O[20] OG_6 l1.S4 - - - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 clb.O[5] OG_7 l1.N0 - - - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 clb.O[13] OG_0 - - - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 clb.O[21] - - - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 clb.O[6] - - - l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 clb.O[14] - - - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 clb.O[22] - - - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 clb.O[7] OG_2 l1.E0 - - - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 clb.O[15] OG_2 l1.N10 - - - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 clb.O[23] OG_3 l1.W12 - - - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 clb.O[0] OG_4 - - - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 clb.O[8] - - - l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 clb.O[16] - - - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 clb.O[1] - - - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 clb.O[9] - - - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 clb.O[17] OG_6 l1.W6 - - - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 clb.O[2] OG_6 l1.S8 - - - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 clb.O[10] OG_7 l1.E2 - - - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 clb.O[18] OG_0 - - - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 clb.O[3] - - - l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 clb.O[11] - - - l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 clb.O[19] - - - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 clb.O[4] - - - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 clb.O[12] OG_2 l1.S6 - - - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 clb.O[20] OG_2 l1.E0 - - - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 clb.O[5] OG_3 l1.W11 - - - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 clb.O[13] OG_4 - - - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 clb.O[21] - - - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 clb.O[6] - - - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 clb.O[14] - - - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 clb.O[22] - - - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 clb.O[7] OG_6 l1.E2 - - - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 clb.O[15] OG_6 l1.W3 - - - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 clb.O[23] OG_7 l1.W0 - - - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 clb.O[0] OG_0 - - - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 clb.O[8] - - - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 clb.O[16] - - - l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 clb.O[1] - - - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 clb.O[9] - - - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 clb.O[17] OG_2 l1.W12 - - - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 clb.O[2] OG_2 l1.W4 - - - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 clb.O[10] OG_3 l1.N10 - - - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 clb.O[18] OG_4 - - - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 clb.O[3] - - - l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 clb.O[11] - - - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 clb.O[19] - - - clb.O[17] clb.O[0] clb.O[8] clb.O[9] - - - clb.O[17] clb.O[0] clb.O[1] clb.O[8] - - - clb.O[16] clb.O[0] clb.O[1] clb.O[9] - - - clb.O[16] clb.O[1] clb.O[8] clb.O[9] - - - clb.O[19] clb.O[2] clb.O[10] clb.O[11] - - - clb.O[19] clb.O[2] clb.O[3] clb.O[10] - - - clb.O[18] clb.O[2] clb.O[3] clb.O[11] - - - clb.O[18] clb.O[3] clb.O[10] clb.O[11] - - - clb.O[21] clb.O[4] clb.O[12] clb.O[13] - - - clb.O[21] clb.O[4] clb.O[5] clb.O[12] - - - clb.O[20] clb.O[4] clb.O[5] clb.O[13] - - - clb.O[20] clb.O[5] clb.O[12] clb.O[13] - - - clb.O[23] clb.O[6] clb.O[14] clb.O[15] - - - clb.O[23] clb.O[6] clb.O[7] clb.O[14] - - - clb.O[22] clb.O[6] clb.O[7] clb.O[15] - - - clb.O[22] clb.O[7] clb.O[14] clb.O[15] - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - - - l1.W0 - mux_0 mux_5 mux_10 mux_15 - - - l1.N0 - mux_16 mux_21 mux_11 mux_14 - - - l1.E0 - mux_32 mux_6 mux_9 mux_31 - - - l1.S0 - mux_48 mux_22 mux_27 mux_13 - - - l1.W1 - mux_64 mux_7 mux_25 mux_30 - - - l1.N1 - mux_80 mux_23 mux_26 mux_29 - - - l1.E1 - mux_1 mux_4 mux_42 mux_47 - - - l1.S1 - mux_17 mux_20 mux_43 mux_46 - - - l1.W2 - mux_33 mux_38 mux_8 mux_63 - - - l1.N2 - mux_49 mux_54 mux_59 mux_12 - - - l1.E2 - mux_65 mux_39 mux_24 mux_62 - - - l1.S2 - mux_81 mux_55 mux_58 mux_28 - - - l1.W3 - mux_2 mux_36 mux_41 mux_79 - - - l1.N3 - mux_18 mux_52 mux_75 mux_45 - - - l1.E3 - mux_34 mux_37 mux_40 mux_95 - - - l1.S3 - mux_50 mux_53 mux_91 mux_44 - - - l1.W4 - mux_66 mux_71 mux_56 mux_61 - - - l1.N4 - mux_82 mux_87 mux_57 mux_60 - - - l1.E4 - mux_3 mux_68 mux_73 mux_78 - - - l1.S4 - mux_19 mux_84 mux_74 mux_77 - - - l1.W5 - mux_35 mux_69 mux_72 mux_94 - - - l1.N5 - mux_51 mux_85 mux_90 mux_76 - - - l1.E5 - mux_67 mux_70 mux_88 mux_93 - - - l1.S5 - mux_83 mux_86 mux_89 mux_92 - - - l1.W6 - mux_96 mux_101 mux_106 mux_111 - - - l1.N6 - mux_112 mux_117 mux_107 mux_110 - - - l1.E6 - mux_0 mux_102 mux_105 mux_127 - - - l1.S6 - mux_16 mux_118 mux_123 mux_109 - - - l1.W7 - mux_32 mux_103 mux_121 mux_126 - - - l1.N7 - mux_48 mux_119 mux_122 mux_125 - - - l1.E7 - mux_97 mux_100 mux_10 mux_15 - - - l1.S7 - mux_113 mux_116 mux_11 mux_14 - - - l1.W8 - mux_1 mux_6 mux_104 mux_31 - - - l1.N8 - mux_17 mux_22 mux_27 mux_108 - - - l1.E8 - mux_33 mux_7 mux_120 mux_30 - - - l1.S8 - mux_49 mux_23 mux_26 mux_124 - - - l2.W0 - mux_98 mux_4 mux_9 mux_47 - - - l2.N0 - mux_114 mux_20 mux_43 mux_13 - - - l2.E0 - mux_2 mux_5 mux_8 mux_63 - - - l2.S0 - mux_18 mux_21 mux_59 mux_12 - - - l2.W2 - mux_34 mux_39 mux_24 mux_29 - - - l2.N2 - mux_50 mux_55 mux_25 mux_28 - - - l2.E2 - mux_99 mux_36 mux_41 mux_46 - - - l2.S2 - mux_115 mux_52 mux_42 mux_45 - - - l2.W4 - mux_3 mux_37 mux_40 mux_62 - - - l2.N4 - mux_19 mux_53 mux_58 mux_44 - - - l2.E4 - mux_35 mux_38 mux_56 mux_61 - - - l2.S4 - mux_51 mux_54 mux_57 mux_60 - - - l3.W0 - mux_64 mux_69 mux_74 mux_79 - - - l3.N0 - mux_80 mux_85 mux_75 mux_78 - - - l3.E0 - mux_96 mux_70 mux_73 mux_95 - - - l3.S0 - mux_112 mux_86 mux_91 mux_77 - - - l3.W3 - mux_0 mux_71 mux_89 mux_94 - - - l3.N3 - mux_16 mux_87 mux_90 mux_93 - - - l3.E3 - mux_65 mux_68 mux_106 mux_111 - - - l3.S3 - mux_81 mux_84 mux_107 mux_110 - - - l3.W6 - mux_97 mux_102 mux_72 mux_127 - - - l3.N6 - mux_113 mux_118 mux_123 mux_76 - - - l3.E6 - mux_1 mux_103 mux_88 mux_126 - - - l3.S6 - mux_17 mux_119 mux_122 mux_92 - - - l3.W9 - mux_66 mux_100 mux_105 mux_15 - - - l3.N9 - mux_82 mux_116 mux_11 mux_109 - - - l3.E9 - mux_98 mux_101 mux_104 mux_31 - - - l3.S9 - mux_114 mux_117 mux_27 mux_108 - - - l3.W12 - mux_2 mux_7 mux_120 mux_125 - - - l3.N12 - mux_18 mux_23 mux_121 mux_124 - - - l3.E12 - mux_67 mux_4 mux_9 mux_14 - - - l3.S12 - mux_83 mux_20 mux_10 mux_13 - - - l3.W15 - mux_99 mux_5 mux_8 mux_30 - - - l3.N15 - mux_115 mux_21 mux_26 mux_12 - - - l3.E15 - mux_3 mux_6 mux_24 mux_29 - - - l3.S15 - mux_19 mux_22 mux_25 mux_28 - - - l3.W18 - mux_32 mux_37 mux_42 mux_47 - - - l3.N18 - mux_48 mux_53 mux_43 mux_46 - - - l3.E18 - mux_64 mux_38 mux_41 mux_63 - - - l3.S18 - mux_80 mux_54 mux_59 mux_45 - - - l3.W21 - mux_96 mux_39 mux_57 mux_62 - - - l3.N21 - mux_112 mux_55 mux_58 mux_61 - - - l3.E21 - mux_33 mux_36 mux_74 mux_79 - - - l3.S21 - mux_49 mux_52 mux_75 mux_78 - - - l4.W0 - mux_65 mux_70 mux_40 mux_95 - - - l4.N0 - mux_81 mux_86 mux_91 mux_44 - - - l4.E0 - mux_97 mux_71 mux_56 mux_94 - - - l4.S0 - mux_113 mux_87 mux_90 mux_60 - - - l4.W4 - mux_34 mux_68 mux_73 mux_111 - - - l4.N4 - mux_50 mux_84 mux_107 mux_77 - - - l4.E4 - mux_66 mux_69 mux_72 mux_127 - - - l4.S4 - mux_82 mux_85 mux_123 mux_76 - - - l4.W8 - mux_98 mux_103 mux_88 mux_93 - - - l4.N8 - mux_114 mux_119 mux_89 mux_92 - - - l4.E8 - mux_35 mux_100 mux_105 mux_110 - - - l4.S8 - mux_51 mux_116 mux_106 mux_109 - - - l4.W12 - mux_67 mux_101 mux_104 mux_126 - - - l4.N12 - mux_83 mux_117 mux_122 mux_108 - - - l4.E12 - mux_99 mux_102 mux_120 mux_125 - - - l4.S12 - mux_115 mux_118 mux_121 mux_124 - - - l8.W0 - mux_0 mux_5 mux_10 mux_15 - - - l8.N0 - mux_16 mux_21 mux_11 mux_14 - - - l8.E0 - mux_32 mux_6 mux_9 mux_31 - - - l8.S0 - mux_48 mux_22 mux_27 mux_13 - - - l8.W8 - mux_64 mux_7 mux_25 mux_30 - - - l8.N8 - mux_80 mux_23 mux_26 mux_29 - - - l8.E8 - mux_1 mux_4 mux_42 mux_47 - - - l8.S8 - mux_17 mux_20 mux_43 mux_46 - - - l1.W9 - l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.N9 - l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.E9 - l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.S9 - l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.W10 - l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.N10 - l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.E10 - l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.S10 - l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.W11 - l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.N11 - l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.E11 - l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.S11 - l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.W12 - l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.N12 - l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.E12 - l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.S12 - l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - clb.I0[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - clb.I0[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - clb.I0[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - clb.I0[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - clb.I0[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - clb.I1[0] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - clb.I1[1] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - clb.I1[2] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - clb.I1[3] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - clb.I1[4] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - clb.I2[0] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - clb.I2[1] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 - - - clb.I2[2] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - clb.I2[3] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - clb.I2[4] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - clb.I3[0] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 - - - clb.I3[1] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - clb.I3[2] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - clb.I3[3] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 - - - clb.I3[4] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 - - - clb.I4[0] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - clb.I4[1] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - clb.I4[2] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 - - - clb.I4[3] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 - - - clb.I4[4] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 - - - clb.I5[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 - - - clb.I5[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 - - - clb.I5[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 - - - clb.I5[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 - - - clb.I5[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 - - - clb.I6[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 - - - clb.I6[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 - - - clb.I6[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 - - - clb.I6[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 - - - clb.I6[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 - - - clb.I7[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 - - - clb.I7[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 - - - clb.I7[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 - - - clb.I7[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 - - - clb.I7[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 - - - clb.I8[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 - - - clb.I8[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 - - - clb.I8[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 - - - clb.I8[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 - - - clb.I8[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 - - - clb.I9[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 - - - clb.I9[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 - - - clb.I9[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 - - - clb.I9[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 - - - clb.I9[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 - - - clb.I10[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 - - - clb.I10[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 - - - clb.I10[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 - - - clb.I10[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 - - - clb.I10[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 - - - clb.I11[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 - - - clb.I11[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 - - - clb.I11[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 - - - clb.I11[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 - - - clb.I11[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 - - - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 io_leftL.a2f_o[1] - - - l1.W2 l2.W1 l4.W3 io_leftL.a2f_o[0] - - - l1.W3 l3.W5 l8.W7 io_leftL.a2f_o[2] - - - l1.W4 l3.W8 l8.W15 - - - l1.N5 l1.N6 l3.N11 io_leftL.a2f_o[2] - - - l1.N7 l2.N3 l4.N7 io_leftL.a2f_o[1] - - - l1.N8 l3.N14 l8.N7 io_leftL.a2f_o[3] - - - l1.N9 l3.N17 l8.N15 - - - io_leftL.a2f_o[3] - - - io_leftL.a2f_o[2] - - - io_leftL.a2f_o[4] - - - l1.S2 l1.S3 l3.S5 io_leftL.a2f_o[4] - - - l1.S4 l2.S1 l4.S15 io_leftL.a2f_o[3] - - - l1.S5 l3.S8 l8.S7 io_leftL.a2f_o[5] - - - l1.S6 l3.S11 l8.S15 - - - l1.W7 l1.W8 l3.W14 io_leftL.a2f_o[5] - - - l1.W9 l2.W3 l4.W3 io_leftL.a2f_o[4] - - - l1.W10 l3.W17 l8.W7 io_leftL.a2f_o[6] - - - l1.W11 l3.W20 l8.W15 - - - l1.N12 l1.N0 l3.N23 io_leftL.a2f_o[6] - - - l1.N1 l2.N5 l4.N7 io_leftL.a2f_o[5] - - - l1.N2 l3.N2 l8.N7 io_leftL.a2f_o[0] - - - l1.N3 l3.N5 l8.N15 - - - io_leftL.a2f_o[0] - - - io_leftL.a2f_o[6] - - - io_leftL.a2f_o[1] - - - l1.S9 l1.S10 l3.S17 io_leftL.a2f_o[1] - - - l1.S11 l2.S3 l4.S15 io_leftL.a2f_o[0] - - - l1.S12 l3.S20 l8.S7 io_leftL.a2f_o[2] - - - l1.S0 l3.S23 l8.S15 - - - l1.W1 l1.W2 l3.W2 io_leftL.a2f_o[1] - - - l1.W3 l2.W5 l4.W3 io_leftL.a2f_o[0] - - - l1.W4 l3.W5 l8.W7 io_leftL.a2f_o[2] - - - l1.W5 l3.W8 l8.W15 - - - l1.N6 l1.N7 l3.N11 io_leftL.a2f_o[2] - - - l1.N8 l2.N1 l4.N7 io_leftL.a2f_o[1] - - - l1.N9 l3.N14 l8.N7 io_leftL.a2f_o[3] - - - l1.N10 l3.N17 l8.N15 - - - io_leftL.a2f_o[3] - - - io_leftL.a2f_o[2] - - - io_leftL.a2f_o[4] - - - l1.S3 l1.S4 l3.S5 io_leftL.a2f_o[4] - - - l1.S5 l2.S5 l4.S15 io_leftL.a2f_o[3] - - - l1.S6 l3.S8 l8.S7 io_leftL.a2f_o[5] - - - l1.S7 l3.S11 l8.S15 - - - l1.W8 l1.W9 l3.W14 io_leftL.a2f_o[5] - - - l1.W10 l2.W1 l4.W3 io_leftL.a2f_o[4] - - - l1.W11 l3.W17 l8.W7 io_leftL.a2f_o[6] - - - l1.W12 l3.W20 l8.W15 - - - l1.N0 l1.N1 l3.N23 io_leftL.a2f_o[6] - - - l1.N2 l2.N3 l4.N7 io_leftL.a2f_o[5] - - - l1.N3 l3.N2 l8.N7 io_leftL.a2f_o[0] - - - l1.N4 l3.N5 l8.N15 - - - io_leftL.a2f_o[0] - - - io_leftL.a2f_o[6] - - - io_leftL.a2f_o[1] - - - l1.S10 l1.S11 l3.S17 io_leftL.a2f_o[1] - - - l1.S12 l2.S1 l4.S15 io_leftL.a2f_o[0] - - - l1.S0 l3.S20 l8.S7 io_leftL.a2f_o[2] - - - l1.S1 l3.S23 l8.S15 - - - l1.W2 l1.W3 l3.W2 io_leftL.a2f_o[1] - - - l1.W4 l2.W3 l4.W3 io_leftL.a2f_o[0] - - - l1.W5 l3.W5 l8.W7 io_leftL.a2f_o[2] - - - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 io_leftL.a2f_o[2] - - - l1.N9 l2.N5 l4.N7 io_leftL.a2f_o[1] - - - l1.N10 l3.N14 l8.N7 io_leftL.a2f_o[3] - - - l1.N11 l3.N17 l8.N15 - - - io_leftL.a2f_o[3] - - - io_leftL.a2f_o[2] - - - io_leftL.a2f_o[4] - - - l1.S4 l1.S5 l3.S5 io_leftL.a2f_o[4] - - - l1.S6 l2.S3 l4.S15 io_leftL.a2f_o[3] - - - l1.S7 l3.S8 l8.S7 io_leftL.a2f_o[5] - - - l1.S8 l3.S11 l8.S15 - - - l1.W9 l1.W10 l3.W14 io_leftL.a2f_o[5] - - - l1.W11 l2.W5 l4.W3 io_leftL.a2f_o[4] - - - l1.W12 l3.W17 l8.W7 io_leftL.a2f_o[6] - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 io_leftL.a2f_o[6] - - - l1.N3 l2.N1 l4.N7 io_leftL.a2f_o[5] - - - l1.N4 l3.N2 l8.N7 io_leftL.a2f_o[0] - - - l1.N5 l3.N5 l8.N15 - - - io_leftL.a2f_o[0] - - - io_leftL.a2f_o[6] - - - io_leftL.a2f_o[1] - - - l1.S11 l1.S12 l3.S17 io_leftL.a2f_o[1] - - - l1.S0 l2.S5 l4.S15 io_leftL.a2f_o[0] - - - l1.S1 l3.S20 l8.S7 io_leftL.a2f_o[2] - - - l1.S2 l3.S23 l8.S15 - - - l1.W3 l1.W4 l3.W2 io_leftL.a2f_o[1] - - - l1.W5 l2.W1 l4.W3 io_leftL.a2f_o[0] - - - l1.W6 l3.W5 l8.W7 io_leftL.a2f_o[2] - - - l1.W7 l3.W8 l8.W15 - - - l1.N8 l1.N9 l3.N11 io_leftL.a2f_o[2] - - - l1.N10 l2.N3 l4.N7 io_leftL.a2f_o[1] - - - l1.N11 l3.N14 l8.N7 io_leftL.a2f_o[3] - - - l1.N12 l3.N17 l8.N15 - - - io_leftL.a2f_o[3] - - - io_leftL.a2f_o[2] - - - io_leftL.a2f_o[4] - - - l1.S5 l1.S6 l3.S5 io_leftL.a2f_o[4] - - - l1.S7 l2.S1 l4.S15 io_leftL.a2f_o[3] - - - l1.S8 l3.S8 l8.S7 io_leftL.a2f_o[5] - - - l1.S9 l3.S11 l8.S15 - - - l1.W10 l1.W11 l3.W14 io_leftL.a2f_o[5] - - - l1.W12 l2.W3 l4.W3 io_leftL.a2f_o[4] - - - l1.W0 l3.W17 l8.W7 io_leftL.a2f_o[6] - - - l1.W1 l3.W20 l8.W15 - - - l1.N2 l1.N3 l3.N23 io_leftL.a2f_o[6] - - - l1.N4 l2.N5 l4.N7 io_leftL.a2f_o[5] - - - l1.N5 l3.N2 l8.N7 io_leftL.a2f_o[0] - - - l1.N6 l3.N5 l8.N15 - - - io_leftL.a2f_o[0] - - - io_leftL.a2f_o[6] - - - io_leftL.a2f_o[1] - - - l1.S12 l1.S0 l3.S17 io_leftL.a2f_o[1] - - - l1.S1 l2.S3 l4.S15 io_leftL.a2f_o[0] - - - l1.S2 l3.S20 l8.S7 io_leftL.a2f_o[2] - - - l1.S3 l3.S23 l8.S15 - - - l1.W6 l1.W5 l2.W3 l3.W11 l4.W7 io_leftL.a2f_o[0] OG_0 - - - l1.N5 io_leftL.a2f_o[1] - - - l1.S11 l1.N4 l3.S17 io_leftL.a2f_o[2] - - - l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 io_leftL.a2f_o[1] - - - l1.S10 l3.S14 io_leftL.a2f_o[2] - - - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 io_leftL.a2f_o[3] OG_2 l1.N2 - - - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 io_leftL.a2f_o[2] OG_2 l1.S4 - - - l1.S2 io_leftL.a2f_o[3] OG_3 l1.N9 - - - l1.W8 l1.W1 io_leftL.a2f_o[4] OG_4 - - - l1.W8 l1.S1 l2.W3 l3.W11 l4.W3 io_leftL.a2f_o[3] - - - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 io_leftL.a2f_o[4] - - - l1.S0 l1.S6 l3.S20 io_leftL.a2f_o[5] - - - l1.W0 l1.N6 l3.W17 l3.N2 l4.W3 io_leftL.a2f_o[4] - - - l1.N12 l3.N17 io_leftL.a2f_o[5] OG_6 - - - l1.S5 l3.S23 io_leftL.a2f_o[6] OG_6 l1.S4 - - - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 io_leftL.a2f_o[5] OG_7 l1.N0 - - - l1.W11 l1.W10 l2.W5 l3.W11 l4.W15 io_leftL.a2f_o[6] OG_0 - - - l1.W4 l1.N10 l2.W1 l3.W23 l4.W7 io_leftL.a2f_o[0] - - - l1.N3 l1.N9 l3.N17 io_leftL.a2f_o[6] - - - l1.N9 l1.S2 l3.N8 io_leftL.a2f_o[0] - - - l1.N2 l3.N14 io_leftL.a2f_o[1] - - - l1.S8 l3.S5 io_leftL.a2f_o[0] OG_2 - - - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 io_leftL.a2f_o[1] OG_2 l1.N10 - - - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 io_leftL.a2f_o[2] OG_3 l1.W12 - - - l1.W0 l1.W6 io_leftL.a2f_o[0] OG_4 - - - l1.S6 io_leftL.a2f_o[1] - - - l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 io_leftL.a2f_o[2] - - - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 io_leftL.a2f_o[1] - - - l1.W5 l1.S11 l3.W17 l3.S2 l4.W11 io_leftL.a2f_o[2] - - - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 io_leftL.a2f_o[3] OG_6 l1.W6 - - - l1.N10 l3.N23 io_leftL.a2f_o[2] OG_6 l1.S8 - - - l1.N3 io_leftL.a2f_o[3] OG_7 - - - l1.W3 l1.W2 l2.W1 l3.W11 l4.W7 io_leftL.a2f_o[4] OG_0 - - - l1.N2 io_leftL.a2f_o[3] - - - l1.S8 l1.N1 l3.S17 io_leftL.a2f_o[4] - - - l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 io_leftL.a2f_o[5] - - - l1.S7 l3.S14 io_leftL.a2f_o[4] - - - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 io_leftL.a2f_o[5] OG_2 l1.S6 - - - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 io_leftL.a2f_o[6] OG_2 - - - l1.S12 io_leftL.a2f_o[5] OG_3 l1.W11 - - - l1.W5 l1.W11 io_leftL.a2f_o[6] OG_4 - - - l1.W5 l1.S11 l2.W1 l3.W11 l4.W3 io_leftL.a2f_o[0] - - - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 io_leftL.a2f_o[6] - - - l1.S10 l1.S3 l3.S20 io_leftL.a2f_o[0] - - - l1.W10 l1.N3 l3.W17 l3.N2 l4.W3 io_leftL.a2f_o[1] - - - l1.N9 l3.N17 io_leftL.a2f_o[0] OG_6 - - - l1.S2 l3.S23 io_leftL.a2f_o[1] OG_6 l1.W3 - - - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 io_leftL.a2f_o[2] OG_7 l1.W0 - - - l1.W8 l1.W7 l2.W3 l3.W11 l4.W15 io_leftL.a2f_o[0] OG_0 - - - l1.W1 l1.N7 l2.W5 l3.W23 l4.W7 io_leftL.a2f_o[1] - - - l1.N0 l1.N6 l3.N17 io_leftL.a2f_o[2] - - - l1.N6 l1.S12 l3.N8 io_leftL.a2f_o[1] - - - l1.N12 l3.N14 io_leftL.a2f_o[2] - - - l1.S5 l3.S5 io_leftL.a2f_o[3] OG_2 l1.W12 - - - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 io_leftL.a2f_o[2] OG_2 l1.W4 - - - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 io_leftL.a2f_o[3] OG_3 l1.N10 - - - l1.W10 l1.W3 io_leftL.a2f_o[4] OG_4 - - - l1.S3 io_leftL.a2f_o[3] - - - l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 io_leftL.a2f_o[4] - - - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 io_leftL.a2f_o[5] - - - io_leftL.a2f_o[3] io_leftL.a2f_o[0] io_leftL.a2f_o[1] io_leftL.a2f_o[2] - - - io_leftL.a2f_o[3] io_leftL.a2f_o[0] io_leftL.a2f_o[1] io_leftL.a2f_o[1] - - - io_leftL.a2f_o[2] io_leftL.a2f_o[0] io_leftL.a2f_o[1] io_leftL.a2f_o[2] - - - io_leftL.a2f_o[2] io_leftL.a2f_o[1] io_leftL.a2f_o[1] io_leftL.a2f_o[2] - - - io_leftL.a2f_o[5] io_leftL.a2f_o[2] io_leftL.a2f_o[3] io_leftL.a2f_o[4] - - - io_leftL.a2f_o[5] io_leftL.a2f_o[2] io_leftL.a2f_o[3] io_leftL.a2f_o[3] - - - io_leftL.a2f_o[4] io_leftL.a2f_o[2] io_leftL.a2f_o[3] io_leftL.a2f_o[4] - - - io_leftL.a2f_o[4] io_leftL.a2f_o[3] io_leftL.a2f_o[3] io_leftL.a2f_o[4] - - - io_leftL.a2f_o[0] io_leftL.a2f_o[4] io_leftL.a2f_o[5] io_leftL.a2f_o[6] - - - io_leftL.a2f_o[0] io_leftL.a2f_o[4] io_leftL.a2f_o[5] io_leftL.a2f_o[5] - - - io_leftL.a2f_o[6] io_leftL.a2f_o[4] io_leftL.a2f_o[5] io_leftL.a2f_o[6] - - - io_leftL.a2f_o[6] io_leftL.a2f_o[5] io_leftL.a2f_o[5] io_leftL.a2f_o[6] - - - io_leftL.a2f_o[2] io_leftL.a2f_o[6] io_leftL.a2f_o[0] io_leftL.a2f_o[1] - - - io_leftL.a2f_o[2] io_leftL.a2f_o[6] io_leftL.a2f_o[0] io_leftL.a2f_o[0] - - - io_leftL.a2f_o[1] io_leftL.a2f_o[6] io_leftL.a2f_o[0] io_leftL.a2f_o[1] - - - io_leftL.a2f_o[1] io_leftL.a2f_o[0] io_leftL.a2f_o[0] io_leftL.a2f_o[1] - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - - - l1.N0 - mux_16 mux_21 mux_14 - - - l1.E0 - mux_32 mux_6 mux_9 mux_31 - - - l1.S0 - mux_48 mux_22 mux_13 - - - l1.N1 - mux_80 mux_23 mux_26 mux_29 - - - l1.E1 - mux_1 mux_4 mux_42 mux_47 - - - l1.S1 - mux_17 mux_20 mux_46 - - - l1.N2 - mux_49 mux_54 mux_12 - - - l1.E2 - mux_65 mux_39 mux_24 mux_62 - - - l1.S2 - mux_81 mux_55 mux_58 mux_28 - - - l1.N3 - mux_18 mux_52 mux_45 - - - l1.E3 - mux_34 mux_37 mux_40 mux_95 - - - l1.S3 - mux_50 mux_53 mux_44 - - - l1.N4 - mux_82 mux_87 mux_57 mux_60 - - - l1.E4 - mux_3 mux_68 mux_73 mux_78 - - - l1.S4 - mux_19 mux_84 mux_74 mux_77 - - - l1.N5 - mux_51 mux_85 mux_90 mux_76 - - - l1.E5 - mux_67 mux_70 mux_88 mux_93 - - - l1.S5 - mux_83 mux_86 mux_89 mux_92 - - - l1.N6 - mux_112 mux_117 mux_110 - - - l1.E6 - mux_0 mux_102 mux_105 mux_127 - - - l1.S6 - mux_16 mux_118 mux_109 - - - l1.N7 - mux_48 mux_119 mux_122 mux_125 - - - l1.E7 - mux_97 mux_100 mux_10 mux_15 - - - l1.S7 - mux_113 mux_116 mux_14 - - - l1.N8 - mux_17 mux_22 mux_108 - - - l1.E8 - mux_33 mux_7 mux_120 mux_30 - - - l1.S8 - mux_49 mux_23 mux_26 mux_124 - - - l2.N0 - mux_114 mux_20 mux_13 - - - l2.E0 - mux_2 mux_5 mux_8 mux_63 - - - l2.S0 - mux_18 mux_21 mux_12 - - - l2.N2 - mux_50 mux_55 mux_25 mux_28 - - - l2.E2 - mux_99 mux_36 mux_41 mux_46 - - - l2.S2 - mux_115 mux_52 mux_42 mux_45 - - - l2.N4 - mux_19 mux_53 mux_58 mux_44 - - - l2.E4 - mux_35 mux_38 mux_56 mux_61 - - - l2.S4 - mux_51 mux_54 mux_57 mux_60 - - - l3.N0 - mux_80 mux_85 mux_78 - - - l3.E0 - mux_96 mux_70 mux_73 mux_95 - - - l3.S0 - mux_112 mux_86 mux_77 - - - l3.N3 - mux_16 mux_87 mux_90 mux_93 - - - l3.E3 - mux_65 mux_68 mux_106 mux_111 - - - l3.S3 - mux_81 mux_84 mux_110 - - - l3.N6 - mux_113 mux_118 mux_76 - - - l3.E6 - mux_1 mux_103 mux_88 mux_126 - - - l3.S6 - mux_17 mux_119 mux_122 mux_92 - - - l3.N9 - mux_82 mux_116 mux_109 - - - l3.E9 - mux_98 mux_101 mux_104 mux_31 - - - l3.S9 - mux_114 mux_117 mux_108 - - - l3.N12 - mux_18 mux_23 mux_121 mux_124 - - - l3.E12 - mux_67 mux_4 mux_9 mux_14 - - - l3.S12 - mux_83 mux_20 mux_10 mux_13 - - - l3.N15 - mux_115 mux_21 mux_26 mux_12 - - - l3.E15 - mux_3 mux_6 mux_24 mux_29 - - - l3.S15 - mux_19 mux_22 mux_25 mux_28 - - - l3.N18 - mux_48 mux_53 mux_46 - - - l3.E18 - mux_64 mux_38 mux_41 mux_63 - - - l3.S18 - mux_80 mux_54 mux_45 - - - l3.N21 - mux_112 mux_55 mux_58 mux_61 - - - l3.E21 - mux_33 mux_36 mux_74 mux_79 - - - l3.S21 - mux_49 mux_52 mux_78 - - - l4.N0 - mux_81 mux_86 mux_44 - - - l4.E0 - mux_97 mux_71 mux_56 mux_94 - - - l4.S0 - mux_113 mux_87 mux_90 mux_60 - - - l4.N4 - mux_50 mux_84 mux_77 - - - l4.E4 - mux_66 mux_69 mux_72 mux_127 - - - l4.S4 - mux_82 mux_85 mux_76 - - - l4.N8 - mux_114 mux_119 mux_89 mux_92 - - - l4.E8 - mux_35 mux_100 mux_105 mux_110 - - - l4.S8 - mux_51 mux_116 mux_106 mux_109 - - - l4.N12 - mux_83 mux_117 mux_122 mux_108 - - - l4.E12 - mux_99 mux_102 mux_120 mux_125 - - - l4.S12 - mux_115 mux_118 mux_121 mux_124 - - - l8.N0 - mux_16 mux_21 mux_14 - - - l8.E0 - mux_32 mux_6 mux_9 mux_31 - - - l8.S0 - mux_48 mux_22 mux_13 - - - l8.N8 - mux_80 mux_23 mux_26 mux_29 - - - l8.E8 - mux_1 mux_4 mux_42 mux_47 - - - l8.S8 - mux_17 mux_20 mux_46 - - - l1.N9 - l1.W9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.E9 - l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.S9 - l1.W9 l1.N9 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.N10 - l1.W10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.E10 - l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.S10 - l1.W10 l1.N10 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.N11 - l1.W11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.E11 - l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.S11 - l1.W11 l1.N11 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.N12 - l1.W12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.E12 - l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.S12 - l1.W12 l1.N12 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - io_leftL.f2a_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_leftL.f2a_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_leftL.f2a_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_leftL.f2a_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_leftL.f2a_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_leftL.f2a_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_leftL.f2a_i[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_leftL.f2a_i[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - io_leftL.f2a_i[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_leftL.f2a_i[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_leftL.f2a_i[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_leftL.f2a_i[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 - - - io_leftL.f2a_i[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_leftL.f2a_i[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_leftL.f2a_i[0] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_leftL.f2a_i[1] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 - - - io_leftL.f2a_i[2] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_leftL.f2a_i[3] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_leftL.f2a_i[4] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_leftL.f2a_i[5] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 - - - io_leftL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - io_leftL.f2a_i[7] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - io_leftL.f2a_i[8] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_leftL.f2a_i[9] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 - - - io_leftL.f2a_i[10] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 - - - io_leftL.f2a_i[11] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 - - - io_leftL.f2a_i[12] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_leftL.f2a_i[13] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 - - - io_leftL.f2a_i[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 - - - io_leftL.f2a_i[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 - - - io_leftL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_leftL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 - - - io_leftL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 - - - io_leftL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 - - - io_leftL.f2a_i[6] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_leftL.f2a_i[7] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 - - - io_leftL.f2a_i[8] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 - - - io_leftL.f2a_i[9] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 - - - io_leftL.f2a_i[10] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 - - - io_leftL.f2a_i[11] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 - - - io_leftL.f2a_i[12] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 - - - io_leftL.f2a_i[13] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 - - - io_leftL.f2a_i[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 - - - io_leftL.f2a_i[1] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 - - - io_leftL.f2a_i[2] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 - - - io_leftL.f2a_i[3] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 - - - io_leftL.f2a_i[4] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 - - - io_leftL.f2a_i[5] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 - - - io_leftL.f2a_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 - - - io_leftL.f2a_i[7] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 - - - io_leftL.f2a_i[8] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 - - - io_leftL.f2a_i[9] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 - - - io_leftL.f2a_i[10] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 - - - io_leftL.f2a_i[11] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 - - - io_leftL.f2a_i[12] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 - - - io_leftL.f2a_i[13] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 - - - io_leftL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 - - - io_leftL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 - - - io_leftL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - - io_leftL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 - - - io_leftL.lclk[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_leftL.lreset[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_leftL.lclk[14] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_leftL.lreset[14] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_leftL.lclk[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_leftL.lreset[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_leftL.lclk[15] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_leftL.lreset[15] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_leftL.lclk[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_leftL.lreset[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_leftL.lclk[16] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_leftL.lreset[16] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_leftL.lclk[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_leftL.lreset[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_leftL.lclk[17] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_leftL.lreset[17] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_leftL.lclk[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_leftL.lreset[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_leftL.lclk[18] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_leftL.lreset[18] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_leftL.lclk[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_leftL.lreset[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_leftL.lclk[19] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_leftL.lreset[19] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_leftL.lclk[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_leftL.lreset[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_leftL.lclk[20] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_leftL.lreset[20] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_leftL.lclk[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - io_leftL.lreset[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - io_leftL.lclk[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_leftL.lreset[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_leftL.lclk[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_leftL.lreset[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_leftL.lclk[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_leftL.lreset[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_leftL.lclk[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 - - - io_leftL.lreset[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 - - - io_leftL.lclk[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_leftL.lreset[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_leftL.lclk[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_leftL.lreset[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_leftL.lclk[14] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_leftL.lreset[14] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_leftL.lclk[15] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 - - - io_leftL.lreset[15] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 - - - io_leftL.lclk[16] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_leftL.lreset[16] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_leftL.lclk[17] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_leftL.lreset[17] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_leftL.lclk[18] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_leftL.lreset[18] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_leftL.lclk[19] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 - - - io_leftL.lreset[19] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 - - - io_leftL.lclk[20] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - io_leftL.lreset[20] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - - - - - - - - - - - - io_rightL.a2f_o[2] - - - io_rightL.a2f_o[0] - - - io_rightL.a2f_o[4] - - - l1.N5 l1.N6 l3.N11 io_rightL.a2f_o[3] - - - l1.N7 l2.N3 l4.N7 io_rightL.a2f_o[1] - - - l1.N8 l3.N14 l8.N7 io_rightL.a2f_o[5] - - - l1.N9 l3.N17 l8.N15 - - - l1.E10 l1.E11 l3.E20 io_rightL.a2f_o[4] - - - l1.E12 l2.E5 l4.E11 io_rightL.a2f_o[2] - - - l1.E0 l3.E23 l8.E7 io_rightL.a2f_o[0] - - - l1.E1 l3.E2 l8.E15 - - - l1.S2 l1.S3 l3.S5 io_rightL.a2f_o[5] - - - l1.S4 l2.S1 l4.S15 io_rightL.a2f_o[3] - - - l1.S5 l3.S8 l8.S7 io_rightL.a2f_o[1] - - - l1.S6 l3.S11 l8.S15 - - - io_rightL.a2f_o[0] - - - io_rightL.a2f_o[4] - - - io_rightL.a2f_o[2] - - - l1.N12 l1.N0 l3.N23 io_rightL.a2f_o[1] - - - l1.N1 l2.N5 l4.N7 io_rightL.a2f_o[5] - - - l1.N2 l3.N2 l8.N7 io_rightL.a2f_o[3] - - - l1.N3 l3.N5 l8.N15 - - - l1.E4 l1.E5 l3.E8 io_rightL.a2f_o[2] - - - l1.E6 l2.E1 l4.E11 io_rightL.a2f_o[0] - - - l1.E7 l3.E11 l8.E7 io_rightL.a2f_o[4] - - - l1.E8 l3.E14 l8.E15 - - - l1.S9 l1.S10 l3.S17 io_rightL.a2f_o[3] - - - l1.S11 l2.S3 l4.S15 io_rightL.a2f_o[1] - - - l1.S12 l3.S20 l8.S7 io_rightL.a2f_o[5] - - - l1.S0 l3.S23 l8.S15 - - - io_rightL.a2f_o[2] - - - io_rightL.a2f_o[0] - - - io_rightL.a2f_o[4] - - - l1.N6 l1.N7 l3.N11 io_rightL.a2f_o[3] - - - l1.N8 l2.N1 l4.N7 io_rightL.a2f_o[1] - - - l1.N9 l3.N14 l8.N7 io_rightL.a2f_o[5] - - - l1.N10 l3.N17 l8.N15 - - - l1.E11 l1.E12 l3.E20 io_rightL.a2f_o[4] - - - l1.E0 l2.E3 l4.E11 io_rightL.a2f_o[2] - - - l1.E1 l3.E23 l8.E7 io_rightL.a2f_o[0] - - - l1.E2 l3.E2 l8.E15 - - - l1.S3 l1.S4 l3.S5 io_rightL.a2f_o[5] - - - l1.S5 l2.S5 l4.S15 io_rightL.a2f_o[3] - - - l1.S6 l3.S8 l8.S7 io_rightL.a2f_o[1] - - - l1.S7 l3.S11 l8.S15 - - - io_rightL.a2f_o[0] - - - io_rightL.a2f_o[4] - - - io_rightL.a2f_o[2] - - - l1.N0 l1.N1 l3.N23 io_rightL.a2f_o[1] - - - l1.N2 l2.N3 l4.N7 io_rightL.a2f_o[5] - - - l1.N3 l3.N2 l8.N7 io_rightL.a2f_o[3] - - - l1.N4 l3.N5 l8.N15 - - - l1.E5 l1.E6 l3.E8 io_rightL.a2f_o[2] - - - l1.E7 l2.E5 l4.E11 io_rightL.a2f_o[0] - - - l1.E8 l3.E11 l8.E7 io_rightL.a2f_o[4] - - - l1.E9 l3.E14 l8.E15 - - - l1.S10 l1.S11 l3.S17 io_rightL.a2f_o[3] - - - l1.S12 l2.S1 l4.S15 io_rightL.a2f_o[1] - - - l1.S0 l3.S20 l8.S7 io_rightL.a2f_o[5] - - - l1.S1 l3.S23 l8.S15 - - - io_rightL.a2f_o[2] - - - io_rightL.a2f_o[0] - - - io_rightL.a2f_o[4] - - - l1.N7 l1.N8 l3.N11 io_rightL.a2f_o[3] - - - l1.N9 l2.N5 l4.N7 io_rightL.a2f_o[1] - - - l1.N10 l3.N14 l8.N7 io_rightL.a2f_o[5] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 io_rightL.a2f_o[4] - - - l1.E1 l2.E1 l4.E11 io_rightL.a2f_o[2] - - - l1.E2 l3.E23 l8.E7 io_rightL.a2f_o[0] - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 io_rightL.a2f_o[5] - - - l1.S6 l2.S3 l4.S15 io_rightL.a2f_o[3] - - - l1.S7 l3.S8 l8.S7 io_rightL.a2f_o[1] - - - l1.S8 l3.S11 l8.S15 - - - io_rightL.a2f_o[0] - - - io_rightL.a2f_o[4] - - - io_rightL.a2f_o[2] - - - l1.N1 l1.N2 l3.N23 io_rightL.a2f_o[1] - - - l1.N3 l2.N1 l4.N7 io_rightL.a2f_o[5] - - - l1.N4 l3.N2 l8.N7 io_rightL.a2f_o[3] - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 io_rightL.a2f_o[2] - - - l1.E8 l2.E3 l4.E11 io_rightL.a2f_o[0] - - - l1.E9 l3.E11 l8.E7 io_rightL.a2f_o[4] - - - l1.E10 l3.E14 l8.E15 - - - l1.S11 l1.S12 l3.S17 io_rightL.a2f_o[3] - - - l1.S0 l2.S5 l4.S15 io_rightL.a2f_o[1] - - - l1.S1 l3.S20 l8.S7 io_rightL.a2f_o[5] - - - l1.S2 l3.S23 l8.S15 - - - io_rightL.a2f_o[2] - - - io_rightL.a2f_o[0] - - - io_rightL.a2f_o[4] - - - l1.N8 l1.N9 l3.N11 io_rightL.a2f_o[3] - - - l1.N10 l2.N3 l4.N7 io_rightL.a2f_o[1] - - - l1.N11 l3.N14 l8.N7 io_rightL.a2f_o[5] - - - l1.N12 l3.N17 l8.N15 - - - l1.E0 l1.E1 l3.E20 io_rightL.a2f_o[4] - - - l1.E2 l2.E5 l4.E11 io_rightL.a2f_o[2] - - - l1.E3 l3.E23 l8.E7 io_rightL.a2f_o[0] - - - l1.E4 l3.E2 l8.E15 - - - l1.S5 l1.S6 l3.S5 io_rightL.a2f_o[5] - - - l1.S7 l2.S1 l4.S15 io_rightL.a2f_o[3] - - - l1.S8 l3.S8 l8.S7 io_rightL.a2f_o[1] - - - l1.S9 l3.S11 l8.S15 - - - io_rightL.a2f_o[0] - - - io_rightL.a2f_o[4] - - - io_rightL.a2f_o[2] - - - l1.N2 l1.N3 l3.N23 io_rightL.a2f_o[1] - - - l1.N4 l2.N5 l4.N7 io_rightL.a2f_o[5] - - - l1.N5 l3.N2 l8.N7 io_rightL.a2f_o[3] - - - l1.N6 l3.N5 l8.N15 - - - l1.E7 l1.E8 l3.E8 io_rightL.a2f_o[2] - - - l1.E9 l2.E1 l4.E11 io_rightL.a2f_o[0] - - - l1.E10 l3.E11 l8.E7 io_rightL.a2f_o[4] - - - l1.E11 l3.E14 l8.E15 - - - l1.S12 l1.S0 l3.S17 io_rightL.a2f_o[3] - - - l1.S1 l2.S3 l4.S15 io_rightL.a2f_o[1] - - - l1.S2 l3.S20 l8.S7 io_rightL.a2f_o[5] - - - l1.S3 l3.S23 l8.S15 - - - l1.E12 io_rightL.a2f_o[0] OG_0 - - - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 io_rightL.a2f_o[2] - - - l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 io_rightL.a2f_o[4] - - - l1.N4 l1.S10 l3.N8 io_rightL.a2f_o[1] - - - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 io_rightL.a2f_o[3] - - - l1.S3 l3.S5 io_rightL.a2f_o[5] OG_2 l1.N2 - - - l1.N9 l3.N11 io_rightL.a2f_o[2] OG_2 l1.S4 - - - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 io_rightL.a2f_o[4] OG_3 l1.N9 - - - l1.E2 l2.E1 l3.E23 l4.E11 io_rightL.a2f_o[0] OG_4 - - - l1.S1 l1.E7 io_rightL.a2f_o[3] - - - l1.N7 l1.N0 l3.N5 io_rightL.a2f_o[5] - - - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 io_rightL.a2f_o[1] - - - l1.N6 l1.E12 l3.N2 io_rightL.a2f_o[4] - - - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 io_rightL.a2f_o[0] OG_6 l1.E5 - - - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 io_rightL.a2f_o[2] OG_6 l1.S4 - - - l1.N11 io_rightL.a2f_o[5] OG_7 l1.N0 - - - l1.E4 io_rightL.a2f_o[1] OG_0 - - - l1.N10 l1.E3 io_rightL.a2f_o[3] - - - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 io_rightL.a2f_o[0] - - - l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 io_rightL.a2f_o[2] - - - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 io_rightL.a2f_o[4] - - - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 io_rightL.a2f_o[1] OG_2 l1.E0 - - - l1.S1 l3.S11 io_rightL.a2f_o[3] OG_2 l1.N10 - - - l1.S7 io_rightL.a2f_o[5] OG_3 - - - l1.E7 l2.E3 l3.E23 l4.E3 io_rightL.a2f_o[0] OG_4 - - - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 io_rightL.a2f_o[2] - - - l1.S12 l1.N5 l3.S5 io_rightL.a2f_o[4] - - - l1.S5 l1.S11 l3.S20 io_rightL.a2f_o[1] - - - l1.S11 l1.E4 l3.S2 io_rightL.a2f_o[3] - - - l1.N4 l3.N17 io_rightL.a2f_o[5] OG_6 - - - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 io_rightL.a2f_o[2] OG_6 l1.S8 - - - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 io_rightL.a2f_o[4] OG_7 l1.E2 - - - l1.E9 io_rightL.a2f_o[0] OG_0 - - - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 io_rightL.a2f_o[3] - - - l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 io_rightL.a2f_o[5] - - - l1.N1 l1.S7 l3.N8 io_rightL.a2f_o[1] - - - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 io_rightL.a2f_o[4] - - - l1.S0 l3.S5 io_rightL.a2f_o[0] OG_2 l1.S6 - - - l1.N6 l3.N11 io_rightL.a2f_o[2] OG_2 l1.E0 - - - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 io_rightL.a2f_o[5] OG_3 - - - l1.E12 l2.E5 l3.E23 l4.E11 io_rightL.a2f_o[1] OG_4 - - - l1.S11 l1.E4 io_rightL.a2f_o[3] - - - l1.N4 l1.N10 l3.N5 io_rightL.a2f_o[0] - - - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 io_rightL.a2f_o[2] - - - l1.N3 l1.E9 l3.N2 io_rightL.a2f_o[4] - - - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 io_rightL.a2f_o[1] OG_6 l1.E2 - - - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 io_rightL.a2f_o[3] OG_6 - - - l1.N8 io_rightL.a2f_o[5] OG_7 - - - l1.E1 io_rightL.a2f_o[0] OG_0 - - - l1.N7 l1.E0 io_rightL.a2f_o[2] - - - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 io_rightL.a2f_o[4] - - - l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 io_rightL.a2f_o[1] - - - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 io_rightL.a2f_o[3] - - - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 io_rightL.a2f_o[5] OG_2 - - - l1.S11 l3.S11 io_rightL.a2f_o[2] OG_2 - - - l1.S4 io_rightL.a2f_o[4] OG_3 l1.N10 - - - l1.E4 l2.E1 l3.E23 l4.E3 io_rightL.a2f_o[0] OG_4 - - - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 io_rightL.a2f_o[3] - - - l1.S9 l1.N2 l3.S5 io_rightL.a2f_o[5] - - - l1.S2 l1.S8 l3.S20 io_rightL.a2f_o[1] - - - io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[2] io_rightL.a2f_o[3] - - - io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[1] io_rightL.a2f_o[2] - - - io_rightL.a2f_o[4] io_rightL.a2f_o[0] io_rightL.a2f_o[1] io_rightL.a2f_o[3] - - - io_rightL.a2f_o[4] io_rightL.a2f_o[1] io_rightL.a2f_o[2] io_rightL.a2f_o[3] - - - io_rightL.a2f_o[1] io_rightL.a2f_o[2] io_rightL.a2f_o[4] io_rightL.a2f_o[5] - - - io_rightL.a2f_o[1] io_rightL.a2f_o[2] io_rightL.a2f_o[3] io_rightL.a2f_o[4] - - - io_rightL.a2f_o[0] io_rightL.a2f_o[2] io_rightL.a2f_o[3] io_rightL.a2f_o[5] - - - io_rightL.a2f_o[0] io_rightL.a2f_o[3] io_rightL.a2f_o[4] io_rightL.a2f_o[5] - - - io_rightL.a2f_o[3] io_rightL.a2f_o[4] io_rightL.a2f_o[0] io_rightL.a2f_o[1] - - - io_rightL.a2f_o[3] io_rightL.a2f_o[4] io_rightL.a2f_o[5] io_rightL.a2f_o[0] - - - io_rightL.a2f_o[2] io_rightL.a2f_o[4] io_rightL.a2f_o[5] io_rightL.a2f_o[1] - - - io_rightL.a2f_o[2] io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[1] - - - io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[2] io_rightL.a2f_o[3] - - - io_rightL.a2f_o[5] io_rightL.a2f_o[0] io_rightL.a2f_o[1] io_rightL.a2f_o[2] - - - io_rightL.a2f_o[4] io_rightL.a2f_o[0] io_rightL.a2f_o[1] io_rightL.a2f_o[3] - - - io_rightL.a2f_o[4] io_rightL.a2f_o[1] io_rightL.a2f_o[2] io_rightL.a2f_o[3] - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - - - l1.W0 - mux_0 mux_5 mux_10 mux_15 - - - l1.N0 - mux_16 mux_21 mux_11 mux_14 - - - l1.S0 - mux_48 mux_22 mux_27 mux_13 - - - l1.W1 - mux_64 mux_7 mux_25 mux_30 - - - l1.N1 - mux_80 mux_23 mux_26 mux_29 - - - l1.S1 - mux_17 mux_20 mux_43 mux_46 - - - l1.W2 - mux_33 mux_38 mux_8 mux_63 - - - l1.N2 - mux_49 mux_54 mux_59 mux_12 - - - l1.S2 - mux_81 mux_55 mux_58 mux_28 - - - l1.W3 - mux_2 mux_36 mux_41 mux_79 - - - l1.N3 - mux_18 mux_52 mux_75 mux_45 - - - l1.S3 - mux_50 mux_53 mux_91 mux_44 - - - l1.W4 - mux_66 mux_71 mux_56 mux_61 - - - l1.N4 - mux_82 mux_87 mux_57 mux_60 - - - l1.S4 - mux_84 mux_74 mux_77 - - - l1.W5 - mux_69 mux_72 mux_94 - - - l1.N5 - mux_85 mux_90 mux_76 - - - l1.S5 - mux_86 mux_89 mux_92 - - - l1.W6 - mux_96 mux_101 mux_106 mux_111 - - - l1.N6 - mux_112 mux_117 mux_107 mux_110 - - - l1.S6 - mux_16 mux_118 mux_123 mux_109 - - - l1.W7 - mux_32 mux_103 mux_121 mux_126 - - - l1.N7 - mux_48 mux_119 mux_122 mux_125 - - - l1.S7 - mux_113 mux_116 mux_11 mux_14 - - - l1.W8 - mux_1 mux_6 mux_104 mux_31 - - - l1.N8 - mux_17 mux_22 mux_27 mux_108 - - - l1.S8 - mux_49 mux_23 mux_26 mux_124 - - - l2.W0 - mux_98 mux_4 mux_9 mux_47 - - - l2.N0 - mux_114 mux_20 mux_43 mux_13 - - - l2.S0 - mux_18 mux_21 mux_59 mux_12 - - - l2.W2 - mux_34 mux_39 mux_24 mux_29 - - - l2.N2 - mux_50 mux_55 mux_25 mux_28 - - - l2.S2 - mux_52 mux_42 mux_45 - - - l2.W4 - mux_37 mux_40 mux_62 - - - l2.N4 - mux_53 mux_58 mux_44 - - - l2.S4 - mux_54 mux_57 mux_60 - - - l3.W0 - mux_64 mux_69 mux_74 mux_79 - - - l3.N0 - mux_80 mux_85 mux_75 mux_78 - - - l3.S0 - mux_112 mux_86 mux_91 mux_77 - - - l3.W3 - mux_0 mux_71 mux_89 mux_94 - - - l3.N3 - mux_16 mux_87 mux_90 mux_93 - - - l3.S3 - mux_81 mux_84 mux_107 mux_110 - - - l3.W6 - mux_97 mux_102 mux_72 mux_127 - - - l3.N6 - mux_113 mux_118 mux_123 mux_76 - - - l3.S6 - mux_17 mux_119 mux_122 mux_92 - - - l3.W9 - mux_66 mux_100 mux_105 mux_15 - - - l3.N9 - mux_82 mux_116 mux_11 mux_109 - - - l3.S9 - mux_114 mux_117 mux_27 mux_108 - - - l3.W12 - mux_2 mux_7 mux_120 mux_125 - - - l3.N12 - mux_18 mux_23 mux_121 mux_124 - - - l3.S12 - mux_20 mux_10 mux_13 - - - l3.W15 - mux_5 mux_8 mux_30 - - - l3.N15 - mux_21 mux_26 mux_12 - - - l3.S15 - mux_22 mux_25 mux_28 - - - l3.W18 - mux_32 mux_37 mux_42 mux_47 - - - l3.N18 - mux_48 mux_53 mux_43 mux_46 - - - l3.S18 - mux_80 mux_54 mux_59 mux_45 - - - l3.W21 - mux_96 mux_39 mux_57 mux_62 - - - l3.N21 - mux_112 mux_55 mux_58 mux_61 - - - l3.S21 - mux_49 mux_52 mux_75 mux_78 - - - l4.W0 - mux_65 mux_70 mux_40 mux_95 - - - l4.N0 - mux_81 mux_86 mux_91 mux_44 - - - l4.S0 - mux_113 mux_87 mux_90 mux_60 - - - l4.W4 - mux_34 mux_68 mux_73 mux_111 - - - l4.N4 - mux_50 mux_84 mux_107 mux_77 - - - l4.S4 - mux_82 mux_85 mux_123 mux_76 - - - l4.W8 - mux_98 mux_103 mux_88 mux_93 - - - l4.N8 - mux_114 mux_119 mux_89 mux_92 - - - l4.S8 - mux_116 mux_106 mux_109 - - - l4.W12 - mux_101 mux_104 mux_126 - - - l4.N12 - mux_117 mux_122 mux_108 - - - l4.S12 - mux_118 mux_121 mux_124 - - - l8.W0 - mux_0 mux_5 mux_10 mux_15 - - - l8.N0 - mux_16 mux_21 mux_11 mux_14 - - - l8.S0 - mux_48 mux_22 mux_27 mux_13 - - - l8.W8 - mux_64 mux_7 mux_25 mux_30 - - - l8.N8 - mux_80 mux_23 mux_26 mux_29 - - - l8.S8 - mux_17 mux_20 mux_43 mux_46 - - - l1.W9 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.N9 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.S9 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.W10 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.N10 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.S10 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.W11 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.N11 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.S11 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.W12 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.N12 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.S12 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - io_rightL.f2a_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_rightL.f2a_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_rightL.f2a_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_rightL.f2a_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_rightL.f2a_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_rightL.f2a_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_rightL.f2a_i[0] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_rightL.f2a_i[1] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - io_rightL.f2a_i[2] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_rightL.f2a_i[3] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_rightL.f2a_i[4] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_rightL.f2a_i[5] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 - - - io_rightL.f2a_i[0] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_rightL.f2a_i[1] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_rightL.f2a_i[2] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_rightL.f2a_i[3] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 - - - io_rightL.f2a_i[4] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_rightL.f2a_i[5] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_rightL.f2a_i[0] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 - - - io_rightL.f2a_i[1] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 - - - io_rightL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_rightL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - io_rightL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 - - - io_rightL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 - - - io_rightL.f2a_i[0] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_rightL.f2a_i[1] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 - - - io_rightL.f2a_i[2] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 - - - io_rightL.f2a_i[3] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 - - - io_rightL.f2a_i[4] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_rightL.f2a_i[5] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 - - - io_rightL.f2a_i[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 - - - io_rightL.f2a_i[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 - - - io_rightL.f2a_i[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_rightL.f2a_i[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 - - - io_rightL.f2a_i[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 - - - io_rightL.f2a_i[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 - - - io_rightL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 - - - io_rightL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 - - - io_rightL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 - - - io_rightL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 - - - io_rightL.f2a_i[4] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 - - - io_rightL.f2a_i[5] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 - - - io_rightL.f2a_i[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 - - - io_rightL.f2a_i[1] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 - - - io_rightL.f2a_i[2] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 - - - io_rightL.f2a_i[3] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 - - - io_rightL.f2a_i[4] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 - - - io_rightL.f2a_i[5] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 - - - io_rightL.f2a_i[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 - - - io_rightL.f2a_i[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 - - - io_rightL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 - - - io_rightL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 - - - io_rightL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 - - - io_rightL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 - - - io_rightL.f2a_i[0] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 - - - io_rightL.f2a_i[1] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 - - - io_rightL.f2a_i[2] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - - io_rightL.f2a_i[3] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 - - - io_rightL.f2a_i[4] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 - - - io_rightL.f2a_i[5] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 - - - io_rightL.lclk[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_rightL.lreset[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_rightL.lclk[6] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_rightL.lreset[6] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_rightL.lclk[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_rightL.lreset[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_rightL.lclk[7] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_rightL.lreset[7] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_rightL.lclk[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_rightL.lreset[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_rightL.lclk[8] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_rightL.lreset[8] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_rightL.lclk[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_rightL.lreset[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_rightL.lclk[9] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_rightL.lreset[9] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - io_rightL.lclk[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_rightL.lreset[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_rightL.lclk[10] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_rightL.lreset[10] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_rightL.lclk[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_rightL.lreset[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_rightL.lclk[11] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_rightL.lreset[11] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_rightL.lclk[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_rightL.lreset[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_rightL.lclk[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - io_rightL.lreset[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - io_rightL.lclk[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_rightL.lreset[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_rightL.lclk[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_rightL.lreset[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_rightL.lclk[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_rightL.lreset[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_rightL.lclk[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 - - - io_rightL.lreset[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 - - - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 io_topL.a2f_o[8] - - - l1.W2 l2.W1 l4.W3 io_topL.a2f_o[0] - - - l1.W3 l3.W5 l8.W7 io_topL.a2f_o[16] - - - l1.W4 l3.W8 l8.W15 - - - l1.N5 l1.N6 l3.N11 io_topL.a2f_o[9] - - - l1.N7 l2.N3 l4.N7 io_topL.a2f_o[1] - - - l1.N8 l3.N14 l8.N7 io_topL.a2f_o[17] - - - l1.N9 l3.N17 l8.N15 - - - l1.E10 l1.E11 l3.E20 io_topL.a2f_o[10] - - - l1.E12 l2.E5 l4.E11 io_topL.a2f_o[2] - - - l1.E0 l3.E23 l8.E7 io_topL.a2f_o[18] - - - l1.E1 l3.E2 l8.E15 - - - io_topL.a2f_o[11] - - - io_topL.a2f_o[3] - - - io_topL.a2f_o[19] - - - l1.W7 l1.W8 l3.W14 io_topL.a2f_o[12] - - - l1.W9 l2.W3 l4.W3 io_topL.a2f_o[4] - - - l1.W10 l3.W17 l8.W7 io_topL.a2f_o[20] - - - l1.W11 l3.W20 l8.W15 - - - l1.N12 l1.N0 l3.N23 io_topL.a2f_o[13] - - - l1.N1 l2.N5 l4.N7 io_topL.a2f_o[5] - - - l1.N2 l3.N2 l8.N7 io_topL.a2f_o[21] - - - l1.N3 l3.N5 l8.N15 - - - l1.E4 l1.E5 l3.E8 io_topL.a2f_o[14] - - - l1.E6 l2.E1 l4.E11 io_topL.a2f_o[6] - - - l1.E7 l3.E11 l8.E7 io_topL.a2f_o[22] - - - l1.E8 l3.E14 l8.E15 - - - io_topL.a2f_o[15] - - - io_topL.a2f_o[7] - - - io_topL.a2f_o[23] - - - l1.W1 l1.W2 l3.W2 io_topL.a2f_o[8] - - - l1.W3 l2.W5 l4.W3 io_topL.a2f_o[0] - - - l1.W4 l3.W5 l8.W7 io_topL.a2f_o[16] - - - l1.W5 l3.W8 l8.W15 - - - l1.N6 l1.N7 l3.N11 io_topL.a2f_o[9] - - - l1.N8 l2.N1 l4.N7 io_topL.a2f_o[1] - - - l1.N9 l3.N14 l8.N7 io_topL.a2f_o[17] - - - l1.N10 l3.N17 l8.N15 - - - l1.E11 l1.E12 l3.E20 io_topL.a2f_o[10] - - - l1.E0 l2.E3 l4.E11 io_topL.a2f_o[2] - - - l1.E1 l3.E23 l8.E7 io_topL.a2f_o[18] - - - l1.E2 l3.E2 l8.E15 - - - io_topL.a2f_o[11] - - - io_topL.a2f_o[3] - - - io_topL.a2f_o[19] - - - l1.W8 l1.W9 l3.W14 io_topL.a2f_o[12] - - - l1.W10 l2.W1 l4.W3 io_topL.a2f_o[4] - - - l1.W11 l3.W17 l8.W7 io_topL.a2f_o[20] - - - l1.W12 l3.W20 l8.W15 - - - l1.N0 l1.N1 l3.N23 io_topL.a2f_o[13] - - - l1.N2 l2.N3 l4.N7 io_topL.a2f_o[5] - - - l1.N3 l3.N2 l8.N7 io_topL.a2f_o[21] - - - l1.N4 l3.N5 l8.N15 - - - l1.E5 l1.E6 l3.E8 io_topL.a2f_o[14] - - - l1.E7 l2.E5 l4.E11 io_topL.a2f_o[6] - - - l1.E8 l3.E11 l8.E7 io_topL.a2f_o[22] - - - l1.E9 l3.E14 l8.E15 - - - io_topL.a2f_o[15] - - - io_topL.a2f_o[7] - - - io_topL.a2f_o[23] - - - l1.W2 l1.W3 l3.W2 io_topL.a2f_o[8] - - - l1.W4 l2.W3 l4.W3 io_topL.a2f_o[0] - - - l1.W5 l3.W5 l8.W7 io_topL.a2f_o[16] - - - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 io_topL.a2f_o[9] - - - l1.N9 l2.N5 l4.N7 io_topL.a2f_o[1] - - - l1.N10 l3.N14 l8.N7 io_topL.a2f_o[17] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 io_topL.a2f_o[10] - - - l1.E1 l2.E1 l4.E11 io_topL.a2f_o[2] - - - l1.E2 l3.E23 l8.E7 io_topL.a2f_o[18] - - - l1.E3 l3.E2 l8.E15 - - - io_topL.a2f_o[11] - - - io_topL.a2f_o[3] - - - io_topL.a2f_o[19] - - - l1.W9 l1.W10 l3.W14 io_topL.a2f_o[12] - - - l1.W11 l2.W5 l4.W3 io_topL.a2f_o[4] - - - l1.W12 l3.W17 l8.W7 io_topL.a2f_o[20] - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 io_topL.a2f_o[13] - - - l1.N3 l2.N1 l4.N7 io_topL.a2f_o[5] - - - l1.N4 l3.N2 l8.N7 io_topL.a2f_o[21] - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 io_topL.a2f_o[14] - - - l1.E8 l2.E3 l4.E11 io_topL.a2f_o[6] - - - l1.E9 l3.E11 l8.E7 io_topL.a2f_o[22] - - - l1.E10 l3.E14 l8.E15 - - - io_topL.a2f_o[15] - - - io_topL.a2f_o[7] - - - io_topL.a2f_o[23] - - - l1.W3 l1.W4 l3.W2 io_topL.a2f_o[8] - - - l1.W5 l2.W1 l4.W3 io_topL.a2f_o[0] - - - l1.W6 l3.W5 l8.W7 io_topL.a2f_o[16] - - - l1.W7 l3.W8 l8.W15 - - - l1.N8 l1.N9 l3.N11 io_topL.a2f_o[9] - - - l1.N10 l2.N3 l4.N7 io_topL.a2f_o[1] - - - l1.N11 l3.N14 l8.N7 io_topL.a2f_o[17] - - - l1.N12 l3.N17 l8.N15 - - - l1.E0 l1.E1 l3.E20 io_topL.a2f_o[10] - - - l1.E2 l2.E5 l4.E11 io_topL.a2f_o[2] - - - l1.E3 l3.E23 l8.E7 io_topL.a2f_o[18] - - - l1.E4 l3.E2 l8.E15 - - - io_topL.a2f_o[11] - - - io_topL.a2f_o[3] - - - io_topL.a2f_o[19] - - - l1.W10 l1.W11 l3.W14 io_topL.a2f_o[12] - - - l1.W12 l2.W3 l4.W3 io_topL.a2f_o[4] - - - l1.W0 l3.W17 l8.W7 io_topL.a2f_o[20] - - - l1.W1 l3.W20 l8.W15 - - - l1.N2 l1.N3 l3.N23 io_topL.a2f_o[13] - - - l1.N4 l2.N5 l4.N7 io_topL.a2f_o[5] - - - l1.N5 l3.N2 l8.N7 io_topL.a2f_o[21] - - - l1.N6 l3.N5 l8.N15 - - - l1.E7 l1.E8 l3.E8 io_topL.a2f_o[14] - - - l1.E9 l2.E1 l4.E11 io_topL.a2f_o[6] - - - l1.E10 l3.E11 l8.E7 io_topL.a2f_o[22] - - - l1.E11 l3.E14 l8.E15 - - - io_topL.a2f_o[15] - - - io_topL.a2f_o[7] - - - io_topL.a2f_o[23] - - - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_topL.a2f_o[0] OG_0 - - - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 io_topL.a2f_o[8] - - - l1.E5 l1.N4 l3.E8 l4.E3 io_topL.a2f_o[16] - - - l1.W11 l1.N4 l3.W20 l3.N8 l4.W11 io_topL.a2f_o[1] - - - l1.E4 l1.E3 l3.E5 l4.E15 io_topL.a2f_o[9] - - - l1.W10 l2.W1 l3.W17 io_topL.a2f_o[17] OG_2 l1.N2 - - - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 io_topL.a2f_o[2] OG_2 - - - l1.E9 l2.E5 l3.E14 l4.E7 io_topL.a2f_o[10] OG_3 l1.N9 - - - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_topL.a2f_o[18] OG_4 - - - l1.W8 l1.E7 l2.W3 l3.W11 l4.W3 io_topL.a2f_o[3] - - - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 io_topL.a2f_o[11] - - - l1.E7 l3.E8 l4.E15 io_topL.a2f_o[19] - - - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 io_topL.a2f_o[4] - - - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 io_topL.a2f_o[12] OG_6 l1.E5 - - - l1.E12 l2.E1 l3.E14 io_topL.a2f_o[20] OG_6 - - - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 io_topL.a2f_o[5] OG_7 l1.N0 - - - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_topL.a2f_o[13] OG_0 - - - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 io_topL.a2f_o[21] - - - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 io_topL.a2f_o[6] - - - l1.E3 l1.N9 l3.E20 l3.N8 l4.E3 io_topL.a2f_o[14] - - - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 io_topL.a2f_o[22] - - - l1.E2 l2.E3 l3.E17 io_topL.a2f_o[7] OG_2 l1.E0 - - - l1.W8 l2.W5 l3.W2 io_topL.a2f_o[15] OG_2 l1.N10 - - - l1.W1 l2.W1 l3.W14 l4.W15 io_topL.a2f_o[23] OG_3 l1.W12 - - - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_topL.a2f_o[0] OG_4 - - - l1.E0 l1.E12 l2.E5 l3.E11 l4.E11 io_topL.a2f_o[8] - - - l1.W6 l1.N5 l3.W20 l4.W15 io_topL.a2f_o[16] - - - l1.W12 l3.W8 l4.W7 io_topL.a2f_o[1] - - - l1.W5 l1.E4 l3.W17 l4.W11 io_topL.a2f_o[9] - - - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 io_topL.a2f_o[17] OG_6 l1.W6 - - - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 io_topL.a2f_o[2] OG_6 - - - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 io_topL.a2f_o[10] OG_7 l1.E2 - - - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_topL.a2f_o[18] OG_0 - - - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 io_topL.a2f_o[3] - - - l1.E2 l1.N1 l3.E8 l4.E3 io_topL.a2f_o[11] - - - l1.W8 l1.N1 l3.W20 l3.N8 l4.W11 io_topL.a2f_o[19] - - - l1.E1 l1.E0 l3.E5 l4.E15 io_topL.a2f_o[4] - - - l1.W7 l2.W5 l3.W17 io_topL.a2f_o[12] OG_2 - - - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 io_topL.a2f_o[20] OG_2 l1.E0 - - - l1.E6 l2.E3 l3.E14 l4.E7 io_topL.a2f_o[5] OG_3 l1.W11 - - - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_topL.a2f_o[13] OG_4 - - - l1.W5 l1.E4 l2.W1 l3.W11 l4.W3 io_topL.a2f_o[21] - - - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 io_topL.a2f_o[6] - - - l1.E4 l3.E8 l4.E15 io_topL.a2f_o[14] - - - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 io_topL.a2f_o[22] - - - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 io_topL.a2f_o[7] OG_6 l1.E2 - - - l1.E9 l2.E5 l3.E14 io_topL.a2f_o[15] OG_6 l1.W3 - - - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 io_topL.a2f_o[23] OG_7 l1.W0 - - - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_topL.a2f_o[0] OG_0 - - - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 io_topL.a2f_o[8] - - - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 io_topL.a2f_o[16] - - - l1.E0 l1.N6 l3.E20 l3.N8 l4.E3 io_topL.a2f_o[1] - - - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 io_topL.a2f_o[9] - - - l1.E12 l2.E1 l3.E17 io_topL.a2f_o[17] OG_2 l1.W12 - - - l1.W5 l2.W3 l3.W2 io_topL.a2f_o[2] OG_2 l1.W4 - - - l1.W11 l2.W5 l3.W14 l4.W15 io_topL.a2f_o[10] OG_3 l1.N10 - - - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_topL.a2f_o[18] OG_4 - - - l1.E10 l1.E9 l2.E3 l3.E11 l4.E11 io_topL.a2f_o[3] - - - l1.W3 l1.N2 l3.W20 l4.W15 io_topL.a2f_o[11] - - - l1.W9 l3.W8 l4.W7 io_topL.a2f_o[19] - - - io_topL.a2f_o[17] io_topL.a2f_o[0] io_topL.a2f_o[8] io_topL.a2f_o[9] - - - io_topL.a2f_o[17] io_topL.a2f_o[0] io_topL.a2f_o[1] io_topL.a2f_o[8] - - - io_topL.a2f_o[16] io_topL.a2f_o[0] io_topL.a2f_o[1] io_topL.a2f_o[9] - - - io_topL.a2f_o[16] io_topL.a2f_o[1] io_topL.a2f_o[8] io_topL.a2f_o[9] - - - io_topL.a2f_o[19] io_topL.a2f_o[2] io_topL.a2f_o[10] io_topL.a2f_o[11] - - - io_topL.a2f_o[19] io_topL.a2f_o[2] io_topL.a2f_o[3] io_topL.a2f_o[10] - - - io_topL.a2f_o[18] io_topL.a2f_o[2] io_topL.a2f_o[3] io_topL.a2f_o[11] - - - io_topL.a2f_o[18] io_topL.a2f_o[3] io_topL.a2f_o[10] io_topL.a2f_o[11] - - - io_topL.a2f_o[21] io_topL.a2f_o[4] io_topL.a2f_o[12] io_topL.a2f_o[13] - - - io_topL.a2f_o[21] io_topL.a2f_o[4] io_topL.a2f_o[5] io_topL.a2f_o[12] - - - io_topL.a2f_o[20] io_topL.a2f_o[4] io_topL.a2f_o[5] io_topL.a2f_o[13] - - - io_topL.a2f_o[20] io_topL.a2f_o[5] io_topL.a2f_o[12] io_topL.a2f_o[13] - - - io_topL.a2f_o[23] io_topL.a2f_o[6] io_topL.a2f_o[14] io_topL.a2f_o[15] - - - io_topL.a2f_o[23] io_topL.a2f_o[6] io_topL.a2f_o[7] io_topL.a2f_o[14] - - - io_topL.a2f_o[22] io_topL.a2f_o[6] io_topL.a2f_o[7] io_topL.a2f_o[15] - - - io_topL.a2f_o[22] io_topL.a2f_o[7] io_topL.a2f_o[14] io_topL.a2f_o[15] - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - - - l1.W0 - mux_0 mux_5 mux_10 - - - l1.E0 - mux_32 mux_6 mux_9 - - - l1.S0 - mux_48 mux_22 mux_27 mux_13 - - - l1.W1 - mux_64 mux_7 mux_25 mux_30 - - - l1.E1 - mux_1 mux_4 mux_42 - - - l1.S1 - mux_17 mux_20 mux_43 mux_46 - - - l1.W2 - mux_33 mux_38 mux_8 - - - l1.E2 - mux_65 mux_39 mux_24 mux_62 - - - l1.S2 - mux_81 mux_55 mux_58 mux_28 - - - l1.W3 - mux_2 mux_36 mux_41 - - - l1.E3 - mux_34 mux_37 mux_40 - - - l1.S3 - mux_50 mux_53 mux_91 mux_44 - - - l1.W4 - mux_66 mux_71 mux_56 mux_61 - - - l1.E4 - mux_3 mux_68 mux_73 mux_78 - - - l1.S4 - mux_19 mux_84 mux_74 mux_77 - - - l1.W5 - mux_35 mux_69 mux_72 mux_94 - - - l1.E5 - mux_67 mux_70 mux_88 mux_93 - - - l1.S5 - mux_83 mux_86 mux_89 mux_92 - - - l1.W6 - mux_96 mux_101 mux_106 - - - l1.E6 - mux_0 mux_102 mux_105 - - - l1.S6 - mux_16 mux_118 mux_123 mux_109 - - - l1.W7 - mux_32 mux_103 mux_121 mux_126 - - - l1.E7 - mux_97 mux_100 mux_10 - - - l1.S7 - mux_113 mux_116 mux_11 mux_14 - - - l1.W8 - mux_1 mux_6 mux_104 - - - l1.E8 - mux_33 mux_7 mux_120 mux_30 - - - l1.S8 - mux_49 mux_23 mux_26 mux_124 - - - l2.W0 - mux_98 mux_4 mux_9 - - - l2.E0 - mux_2 mux_5 mux_8 - - - l2.S0 - mux_18 mux_21 mux_59 mux_12 - - - l2.W2 - mux_34 mux_39 mux_24 mux_29 - - - l2.E2 - mux_99 mux_36 mux_41 mux_46 - - - l2.S2 - mux_115 mux_52 mux_42 mux_45 - - - l2.W4 - mux_3 mux_37 mux_40 mux_62 - - - l2.E4 - mux_35 mux_38 mux_56 mux_61 - - - l2.S4 - mux_51 mux_54 mux_57 mux_60 - - - l3.W0 - mux_64 mux_69 mux_74 - - - l3.E0 - mux_96 mux_70 mux_73 - - - l3.S0 - mux_112 mux_86 mux_91 mux_77 - - - l3.W3 - mux_0 mux_71 mux_89 mux_94 - - - l3.E3 - mux_65 mux_68 mux_106 - - - l3.S3 - mux_81 mux_84 mux_107 mux_110 - - - l3.W6 - mux_97 mux_102 mux_72 - - - l3.E6 - mux_1 mux_103 mux_88 mux_126 - - - l3.S6 - mux_17 mux_119 mux_122 mux_92 - - - l3.W9 - mux_66 mux_100 mux_105 - - - l3.E9 - mux_98 mux_101 mux_104 - - - l3.S9 - mux_114 mux_117 mux_27 mux_108 - - - l3.W12 - mux_2 mux_7 mux_120 mux_125 - - - l3.E12 - mux_67 mux_4 mux_9 mux_14 - - - l3.S12 - mux_83 mux_20 mux_10 mux_13 - - - l3.W15 - mux_99 mux_5 mux_8 mux_30 - - - l3.E15 - mux_3 mux_6 mux_24 mux_29 - - - l3.S15 - mux_19 mux_22 mux_25 mux_28 - - - l3.W18 - mux_32 mux_37 mux_42 - - - l3.E18 - mux_64 mux_38 mux_41 - - - l3.S18 - mux_80 mux_54 mux_59 mux_45 - - - l3.W21 - mux_96 mux_39 mux_57 mux_62 - - - l3.E21 - mux_33 mux_36 mux_74 - - - l3.S21 - mux_49 mux_52 mux_75 mux_78 - - - l4.W0 - mux_65 mux_70 mux_40 - - - l4.E0 - mux_97 mux_71 mux_56 mux_94 - - - l4.S0 - mux_113 mux_87 mux_90 mux_60 - - - l4.W4 - mux_34 mux_68 mux_73 - - - l4.E4 - mux_66 mux_69 mux_72 - - - l4.S4 - mux_82 mux_85 mux_123 mux_76 - - - l4.W8 - mux_98 mux_103 mux_88 mux_93 - - - l4.E8 - mux_35 mux_100 mux_105 mux_110 - - - l4.S8 - mux_51 mux_116 mux_106 mux_109 - - - l4.W12 - mux_67 mux_101 mux_104 mux_126 - - - l4.E12 - mux_99 mux_102 mux_120 mux_125 - - - l4.S12 - mux_115 mux_118 mux_121 mux_124 - - - l8.W0 - mux_0 mux_5 mux_10 - - - l8.E0 - mux_32 mux_6 mux_9 - - - l8.S0 - mux_48 mux_22 mux_27 mux_13 - - - l8.W8 - mux_64 mux_7 mux_25 mux_30 - - - l8.E8 - mux_1 mux_4 mux_42 - - - l8.S8 - mux_17 mux_20 mux_43 mux_46 - - - l1.W9 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.E9 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.S9 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.W10 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.E10 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.S10 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.W11 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.E11 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.S11 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.W12 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.E12 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.S12 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - io_topL.f2a_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.f2a_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.f2a_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.f2a_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.f2a_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.f2a_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.f2a_i[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.f2a_i[0] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.f2a_i[1] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.f2a_i[2] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.f2a_i[3] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_topL.f2a_i[4] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_topL.f2a_i[5] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_topL.f2a_i[6] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_topL.f2a_i[0] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_topL.f2a_i[1] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_topL.f2a_i[2] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_topL.f2a_i[3] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_topL.f2a_i[4] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 - - - io_topL.f2a_i[5] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_topL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - io_topL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - io_topL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 - - - io_topL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 - - - io_topL.f2a_i[4] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 - - - io_topL.f2a_i[5] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 - - - io_topL.f2a_i[6] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.f2a_i[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 - - - io_topL.f2a_i[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 - - - io_topL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 - - - io_topL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_topL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 - - - io_topL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 - - - io_topL.f2a_i[6] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 - - - io_topL.f2a_i[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 - - - io_topL.f2a_i[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 - - - io_topL.f2a_i[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 - - - io_topL.f2a_i[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 - - - io_topL.f2a_i[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 - - - io_topL.f2a_i[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.f2a_i[6] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.f2a_i[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.f2a_i[1] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 - - - io_topL.f2a_i[2] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.f2a_i[3] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 - - - io_topL.f2a_i[4] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 - - - io_topL.f2a_i[5] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 - - - io_topL.f2a_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 - - - io_topL.f2a_i[0] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 - - - io_topL.f2a_i[1] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 - - - io_topL.f2a_i[2] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 - - - io_topL.f2a_i[3] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 - - - io_topL.f2a_i[4] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 - - - io_topL.f2a_i[5] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 - - - io_topL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 - - - io_topL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 - - - io_topL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 - - - io_topL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 - - - io_topL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 - - - io_topL.lclk[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lreset[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lclk[7] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lreset[7] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lclk[14] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lreset[14] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lclk[21] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lreset[21] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lclk[28] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lreset[28] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_topL.lclk[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lreset[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lclk[8] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lreset[8] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lclk[15] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lreset[15] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lclk[22] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lreset[22] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lclk[29] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lreset[29] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_topL.lclk[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lreset[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lclk[9] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lreset[9] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lclk[16] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lreset[16] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lclk[23] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lreset[23] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lclk[30] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lreset[30] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_topL.lclk[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lreset[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lclk[10] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lreset[10] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lclk[17] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lreset[17] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lclk[24] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lreset[24] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lclk[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.lreset[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.lclk[11] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.lreset[11] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.lclk[18] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.lreset[18] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.lclk[25] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.lreset[25] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_topL.lclk[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.lreset[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.lclk[12] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.lreset[12] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.lclk[19] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.lreset[19] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.lclk[26] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.lreset[26] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_topL.lclk[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.lreset[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.lclk[13] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.lreset[13] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.lclk[20] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.lreset[20] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.lclk[27] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.lreset[27] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_topL.lclk[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lreset[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lclk[14] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lreset[14] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lclk[21] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lreset[21] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lclk[28] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lreset[28] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lclk[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.lreset[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.lclk[15] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.lreset[15] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.lclk[22] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.lreset[22] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.lclk[29] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.lreset[29] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_topL.lclk[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.lreset[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.lclk[16] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.lreset[16] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.lclk[23] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.lreset[23] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.lclk[30] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.lreset[30] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_topL.lclk[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_topL.lreset[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_topL.lclk[17] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_topL.lreset[17] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_topL.lclk[24] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_topL.lreset[24] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_topL.lclk[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_topL.lreset[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_topL.lclk[18] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_topL.lreset[18] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_topL.lclk[25] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_topL.lreset[25] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_topL.lclk[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_topL.lreset[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_topL.lclk[19] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_topL.lreset[19] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_topL.lclk[26] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_topL.lreset[26] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_topL.lclk[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_topL.lreset[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_topL.lclk[20] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_topL.lreset[20] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_topL.lclk[27] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_topL.lreset[27] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_topL.lclk[14] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_topL.lreset[14] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_topL.lclk[21] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_topL.lreset[21] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_topL.lclk[28] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_topL.lreset[28] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_topL.lclk[15] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_topL.lreset[15] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_topL.lclk[22] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_topL.lreset[22] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_topL.lclk[29] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_topL.lreset[29] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_topL.lclk[16] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_topL.lreset[16] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_topL.lclk[23] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_topL.lreset[23] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_topL.lclk[30] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_topL.lreset[30] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_topL.lclk[17] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_topL.lreset[17] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_topL.lclk[24] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_topL.lreset[24] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_topL.lclk[18] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 - - - io_topL.lreset[18] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 - - - io_topL.lclk[25] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 - - - io_topL.lreset[25] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 - - - io_topL.lclk[19] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_topL.lreset[19] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_topL.lclk[26] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_topL.lreset[26] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_topL.lclk[20] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - io_topL.lreset[20] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - io_topL.lclk[27] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - io_topL.lreset[27] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - io_topL.lclk[21] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - io_topL.lreset[21] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - io_topL.lclk[28] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - io_topL.lreset[28] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - io_topL.lclk[22] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 - - - io_topL.lreset[22] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 - - - io_topL.lclk[29] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 - - - io_topL.lreset[29] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 - - - io_topL.lclk[23] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lreset[23] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lclk[30] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lreset[30] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_topL.lclk[24] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 - - - io_topL.lreset[24] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 - - - io_topL.lclk[25] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 - - - io_topL.lreset[25] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 - - - io_topL.lclk[26] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 - - - io_topL.lreset[26] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 - - - io_topL.lclk[27] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lreset[27] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_topL.lclk[28] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 - - - io_topL.lreset[28] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 - - - io_topL.lclk[29] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 - - - io_topL.lreset[29] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 - - - io_topL.lclk[30] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 - - - io_topL.lreset[30] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 - - - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 io_top_dspL.a2f_o[8] - - - l1.W2 l2.W1 l4.W3 io_top_dspL.a2f_o[0] - - - l1.W3 l3.W5 l8.W7 io_top_dspL.a2f_o[16] - - - l1.W4 l3.W8 l8.W15 - - - l1.N5 l1.N6 l3.N11 io_top_dspL.a2f_o[9] - - - l1.N7 l2.N3 l4.N7 io_top_dspL.a2f_o[1] - - - l1.N8 l3.N14 l8.N7 io_top_dspL.a2f_o[17] - - - l1.N9 l3.N17 l8.N15 - - - l1.E10 l1.E11 l3.E20 io_top_dspL.a2f_o[10] - - - l1.E12 l2.E5 l4.E11 io_top_dspL.a2f_o[2] - - - l1.E0 l3.E23 l8.E7 io_top_dspL.a2f_o[18] - - - l1.E1 l3.E2 l8.E15 - - - io_top_dspL.a2f_o[11] - - - io_top_dspL.a2f_o[3] - - - io_top_dspL.a2f_o[19] - - - l1.W7 l1.W8 l3.W14 io_top_dspL.a2f_o[12] - - - l1.W9 l2.W3 l4.W3 io_top_dspL.a2f_o[4] - - - l1.W10 l3.W17 l8.W7 io_top_dspL.a2f_o[20] - - - l1.W11 l3.W20 l8.W15 - - - l1.N12 l1.N0 l3.N23 io_top_dspL.a2f_o[13] - - - l1.N1 l2.N5 l4.N7 io_top_dspL.a2f_o[5] - - - l1.N2 l3.N2 l8.N7 io_top_dspL.a2f_o[21] - - - l1.N3 l3.N5 l8.N15 - - - l1.E4 l1.E5 l3.E8 io_top_dspL.a2f_o[14] - - - l1.E6 l2.E1 l4.E11 io_top_dspL.a2f_o[6] - - - l1.E7 l3.E11 l8.E7 io_top_dspL.a2f_o[22] - - - l1.E8 l3.E14 l8.E15 - - - io_top_dspL.a2f_o[15] - - - io_top_dspL.a2f_o[7] - - - io_top_dspL.a2f_o[23] - - - l1.W1 l1.W2 l3.W2 io_top_dspL.a2f_o[8] - - - l1.W3 l2.W5 l4.W3 io_top_dspL.a2f_o[0] - - - l1.W4 l3.W5 l8.W7 io_top_dspL.a2f_o[16] - - - l1.W5 l3.W8 l8.W15 - - - l1.N6 l1.N7 l3.N11 io_top_dspL.a2f_o[9] - - - l1.N8 l2.N1 l4.N7 io_top_dspL.a2f_o[1] - - - l1.N9 l3.N14 l8.N7 io_top_dspL.a2f_o[17] - - - l1.N10 l3.N17 l8.N15 - - - l1.E11 l1.E12 l3.E20 io_top_dspL.a2f_o[10] - - - l1.E0 l2.E3 l4.E11 io_top_dspL.a2f_o[2] - - - l1.E1 l3.E23 l8.E7 io_top_dspL.a2f_o[18] - - - l1.E2 l3.E2 l8.E15 - - - io_top_dspL.a2f_o[11] - - - io_top_dspL.a2f_o[3] - - - io_top_dspL.a2f_o[19] - - - l1.W8 l1.W9 l3.W14 io_top_dspL.a2f_o[12] - - - l1.W10 l2.W1 l4.W3 io_top_dspL.a2f_o[4] - - - l1.W11 l3.W17 l8.W7 io_top_dspL.a2f_o[20] - - - l1.W12 l3.W20 l8.W15 - - - l1.N0 l1.N1 l3.N23 io_top_dspL.a2f_o[13] - - - l1.N2 l2.N3 l4.N7 io_top_dspL.a2f_o[5] - - - l1.N3 l3.N2 l8.N7 io_top_dspL.a2f_o[21] - - - l1.N4 l3.N5 l8.N15 - - - l1.E5 l1.E6 l3.E8 io_top_dspL.a2f_o[14] - - - l1.E7 l2.E5 l4.E11 io_top_dspL.a2f_o[6] - - - l1.E8 l3.E11 l8.E7 io_top_dspL.a2f_o[22] - - - l1.E9 l3.E14 l8.E15 - - - io_top_dspL.a2f_o[15] - - - io_top_dspL.a2f_o[7] - - - io_top_dspL.a2f_o[23] - - - l1.W2 l1.W3 l3.W2 io_top_dspL.a2f_o[8] - - - l1.W4 l2.W3 l4.W3 io_top_dspL.a2f_o[0] - - - l1.W5 l3.W5 l8.W7 io_top_dspL.a2f_o[16] - - - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 io_top_dspL.a2f_o[9] - - - l1.N9 l2.N5 l4.N7 io_top_dspL.a2f_o[1] - - - l1.N10 l3.N14 l8.N7 io_top_dspL.a2f_o[17] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 io_top_dspL.a2f_o[10] - - - l1.E1 l2.E1 l4.E11 io_top_dspL.a2f_o[2] - - - l1.E2 l3.E23 l8.E7 io_top_dspL.a2f_o[18] - - - l1.E3 l3.E2 l8.E15 - - - io_top_dspL.a2f_o[11] - - - io_top_dspL.a2f_o[3] - - - io_top_dspL.a2f_o[19] - - - l1.W9 l1.W10 l3.W14 io_top_dspL.a2f_o[12] - - - l1.W11 l2.W5 l4.W3 io_top_dspL.a2f_o[4] - - - l1.W12 l3.W17 l8.W7 io_top_dspL.a2f_o[20] - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 io_top_dspL.a2f_o[13] - - - l1.N3 l2.N1 l4.N7 io_top_dspL.a2f_o[5] - - - l1.N4 l3.N2 l8.N7 io_top_dspL.a2f_o[21] - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 io_top_dspL.a2f_o[14] - - - l1.E8 l2.E3 l4.E11 io_top_dspL.a2f_o[6] - - - l1.E9 l3.E11 l8.E7 io_top_dspL.a2f_o[22] - - - l1.E10 l3.E14 l8.E15 - - - io_top_dspL.a2f_o[15] - - - io_top_dspL.a2f_o[7] - - - io_top_dspL.a2f_o[23] - - - l1.W3 l1.W4 l3.W2 io_top_dspL.a2f_o[8] - - - l1.W5 l2.W1 l4.W3 io_top_dspL.a2f_o[0] - - - l1.W6 l3.W5 l8.W7 io_top_dspL.a2f_o[16] - - - l1.W7 l3.W8 l8.W15 - - - l1.N8 l1.N9 l3.N11 io_top_dspL.a2f_o[9] - - - l1.N10 l2.N3 l4.N7 io_top_dspL.a2f_o[1] - - - l1.N11 l3.N14 l8.N7 io_top_dspL.a2f_o[17] - - - l1.N12 l3.N17 l8.N15 - - - l1.E0 l1.E1 l3.E20 io_top_dspL.a2f_o[10] - - - l1.E2 l2.E5 l4.E11 io_top_dspL.a2f_o[2] - - - l1.E3 l3.E23 l8.E7 io_top_dspL.a2f_o[18] - - - l1.E4 l3.E2 l8.E15 - - - io_top_dspL.a2f_o[11] - - - io_top_dspL.a2f_o[3] - - - io_top_dspL.a2f_o[19] - - - l1.W10 l1.W11 l3.W14 io_top_dspL.a2f_o[12] - - - l1.W12 l2.W3 l4.W3 io_top_dspL.a2f_o[4] - - - l1.W0 l3.W17 l8.W7 io_top_dspL.a2f_o[20] - - - l1.W1 l3.W20 l8.W15 - - - l1.N2 l1.N3 l3.N23 io_top_dspL.a2f_o[13] - - - l1.N4 l2.N5 l4.N7 io_top_dspL.a2f_o[5] - - - l1.N5 l3.N2 l8.N7 io_top_dspL.a2f_o[21] - - - l1.N6 l3.N5 l8.N15 - - - l1.E7 l1.E8 l3.E8 io_top_dspL.a2f_o[14] - - - l1.E9 l2.E1 l4.E11 io_top_dspL.a2f_o[6] - - - l1.E10 l3.E11 l8.E7 io_top_dspL.a2f_o[22] - - - l1.E11 l3.E14 l8.E15 - - - io_top_dspL.a2f_o[15] - - - io_top_dspL.a2f_o[7] - - - io_top_dspL.a2f_o[23] - - - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_top_dspL.a2f_o[0] OG_0 - - - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 io_top_dspL.a2f_o[8] - - - l1.E5 l1.N4 l3.E8 l4.E3 io_top_dspL.a2f_o[16] - - - l1.W11 l1.N4 l3.W20 l3.N8 l4.W11 io_top_dspL.a2f_o[1] - - - l1.E4 l1.E3 l3.E5 l4.E15 io_top_dspL.a2f_o[9] - - - l1.W10 l2.W1 l3.W17 io_top_dspL.a2f_o[17] OG_2 l1.N2 - - - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 io_top_dspL.a2f_o[2] OG_2 - - - l1.E9 l2.E5 l3.E14 l4.E7 io_top_dspL.a2f_o[10] OG_3 l1.N9 - - - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_top_dspL.a2f_o[18] OG_4 - - - l1.W8 l1.E7 l2.W3 l3.W11 l4.W3 io_top_dspL.a2f_o[3] - - - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 io_top_dspL.a2f_o[11] - - - l1.E7 l3.E8 l4.E15 io_top_dspL.a2f_o[19] - - - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 io_top_dspL.a2f_o[4] - - - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 io_top_dspL.a2f_o[12] OG_6 l1.E5 - - - l1.E12 l2.E1 l3.E14 io_top_dspL.a2f_o[20] OG_6 - - - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 io_top_dspL.a2f_o[5] OG_7 l1.N0 - - - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_top_dspL.a2f_o[13] OG_0 - - - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 io_top_dspL.a2f_o[21] - - - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 io_top_dspL.a2f_o[6] - - - l1.E3 l1.N9 l3.E20 l3.N8 l4.E3 io_top_dspL.a2f_o[14] - - - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 io_top_dspL.a2f_o[22] - - - l1.E2 l2.E3 l3.E17 io_top_dspL.a2f_o[7] OG_2 l1.E0 - - - l1.W8 l2.W5 l3.W2 io_top_dspL.a2f_o[15] OG_2 l1.N10 - - - l1.W1 l2.W1 l3.W14 l4.W15 io_top_dspL.a2f_o[23] OG_3 l1.W12 - - - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_top_dspL.a2f_o[0] OG_4 - - - l1.E0 l1.E12 l2.E5 l3.E11 l4.E11 io_top_dspL.a2f_o[8] - - - l1.W6 l1.N5 l3.W20 l4.W15 io_top_dspL.a2f_o[16] - - - l1.W12 l3.W8 l4.W7 io_top_dspL.a2f_o[1] - - - l1.W5 l1.E4 l3.W17 l4.W11 io_top_dspL.a2f_o[9] - - - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 io_top_dspL.a2f_o[17] OG_6 l1.W6 - - - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 io_top_dspL.a2f_o[2] OG_6 - - - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 io_top_dspL.a2f_o[10] OG_7 l1.E2 - - - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_top_dspL.a2f_o[18] OG_0 - - - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 io_top_dspL.a2f_o[3] - - - l1.E2 l1.N1 l3.E8 l4.E3 io_top_dspL.a2f_o[11] - - - l1.W8 l1.N1 l3.W20 l3.N8 l4.W11 io_top_dspL.a2f_o[19] - - - l1.E1 l1.E0 l3.E5 l4.E15 io_top_dspL.a2f_o[4] - - - l1.W7 l2.W5 l3.W17 io_top_dspL.a2f_o[12] OG_2 - - - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 io_top_dspL.a2f_o[20] OG_2 l1.E0 - - - l1.E6 l2.E3 l3.E14 l4.E7 io_top_dspL.a2f_o[5] OG_3 l1.W11 - - - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_top_dspL.a2f_o[13] OG_4 - - - l1.W5 l1.E4 l2.W1 l3.W11 l4.W3 io_top_dspL.a2f_o[21] - - - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 io_top_dspL.a2f_o[6] - - - l1.E4 l3.E8 l4.E15 io_top_dspL.a2f_o[14] - - - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 io_top_dspL.a2f_o[22] - - - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 io_top_dspL.a2f_o[7] OG_6 l1.E2 - - - l1.E9 l2.E5 l3.E14 io_top_dspL.a2f_o[15] OG_6 l1.W3 - - - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 io_top_dspL.a2f_o[23] OG_7 l1.W0 - - - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_top_dspL.a2f_o[0] OG_0 - - - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 io_top_dspL.a2f_o[8] - - - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 io_top_dspL.a2f_o[16] - - - l1.E0 l1.N6 l3.E20 l3.N8 l4.E3 io_top_dspL.a2f_o[1] - - - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 io_top_dspL.a2f_o[9] - - - l1.E12 l2.E1 l3.E17 io_top_dspL.a2f_o[17] OG_2 l1.W12 - - - l1.W5 l2.W3 l3.W2 io_top_dspL.a2f_o[2] OG_2 l1.W4 - - - l1.W11 l2.W5 l3.W14 l4.W15 io_top_dspL.a2f_o[10] OG_3 l1.N10 - - - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_top_dspL.a2f_o[18] OG_4 - - - l1.E10 l1.E9 l2.E3 l3.E11 l4.E11 io_top_dspL.a2f_o[3] - - - l1.W3 l1.N2 l3.W20 l4.W15 io_top_dspL.a2f_o[11] - - - l1.W9 l3.W8 l4.W7 io_top_dspL.a2f_o[19] - - - io_top_dspL.a2f_o[17] io_top_dspL.a2f_o[0] io_top_dspL.a2f_o[8] io_top_dspL.a2f_o[9] - - - io_top_dspL.a2f_o[17] io_top_dspL.a2f_o[0] io_top_dspL.a2f_o[1] io_top_dspL.a2f_o[8] - - - io_top_dspL.a2f_o[16] io_top_dspL.a2f_o[0] io_top_dspL.a2f_o[1] io_top_dspL.a2f_o[9] - - - io_top_dspL.a2f_o[16] io_top_dspL.a2f_o[1] io_top_dspL.a2f_o[8] io_top_dspL.a2f_o[9] - - - io_top_dspL.a2f_o[19] io_top_dspL.a2f_o[2] io_top_dspL.a2f_o[10] io_top_dspL.a2f_o[11] - - - io_top_dspL.a2f_o[19] io_top_dspL.a2f_o[2] io_top_dspL.a2f_o[3] io_top_dspL.a2f_o[10] - - - io_top_dspL.a2f_o[18] io_top_dspL.a2f_o[2] io_top_dspL.a2f_o[3] io_top_dspL.a2f_o[11] - - - io_top_dspL.a2f_o[18] io_top_dspL.a2f_o[3] io_top_dspL.a2f_o[10] io_top_dspL.a2f_o[11] - - - io_top_dspL.a2f_o[21] io_top_dspL.a2f_o[4] io_top_dspL.a2f_o[12] io_top_dspL.a2f_o[13] - - - io_top_dspL.a2f_o[21] io_top_dspL.a2f_o[4] io_top_dspL.a2f_o[5] io_top_dspL.a2f_o[12] - - - io_top_dspL.a2f_o[20] io_top_dspL.a2f_o[4] io_top_dspL.a2f_o[5] io_top_dspL.a2f_o[13] - - - io_top_dspL.a2f_o[20] io_top_dspL.a2f_o[5] io_top_dspL.a2f_o[12] io_top_dspL.a2f_o[13] - - - io_top_dspL.a2f_o[23] io_top_dspL.a2f_o[6] io_top_dspL.a2f_o[14] io_top_dspL.a2f_o[15] - - - io_top_dspL.a2f_o[23] io_top_dspL.a2f_o[6] io_top_dspL.a2f_o[7] io_top_dspL.a2f_o[14] - - - io_top_dspL.a2f_o[22] io_top_dspL.a2f_o[6] io_top_dspL.a2f_o[7] io_top_dspL.a2f_o[15] - - - io_top_dspL.a2f_o[22] io_top_dspL.a2f_o[7] io_top_dspL.a2f_o[14] io_top_dspL.a2f_o[15] - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - - - l1.W0 - mux_0 mux_5 mux_10 - - - l1.E0 - mux_32 mux_6 mux_9 - - - l1.S0 - mux_48 mux_22 mux_27 mux_13 - - - l1.W1 - mux_64 mux_7 mux_25 mux_30 - - - l1.E1 - mux_1 mux_4 mux_42 - - - l1.S1 - mux_17 mux_20 mux_43 mux_46 - - - l1.W2 - mux_33 mux_38 mux_8 - - - l1.E2 - mux_65 mux_39 mux_24 mux_62 - - - l1.S2 - mux_81 mux_55 mux_58 mux_28 - - - l1.W3 - mux_2 mux_36 mux_41 - - - l1.E3 - mux_34 mux_37 mux_40 - - - l1.S3 - mux_50 mux_53 mux_91 mux_44 - - - l1.W4 - mux_66 mux_71 mux_56 mux_61 - - - l1.E4 - mux_3 mux_68 mux_73 mux_78 - - - l1.S4 - mux_19 mux_84 mux_74 mux_77 - - - l1.W5 - mux_35 mux_69 mux_72 mux_94 - - - l1.E5 - mux_67 mux_70 mux_88 mux_93 - - - l1.S5 - mux_83 mux_86 mux_89 mux_92 - - - l1.W6 - mux_96 mux_101 mux_106 - - - l1.E6 - mux_0 mux_102 mux_105 - - - l1.S6 - mux_16 mux_118 mux_123 mux_109 - - - l1.W7 - mux_32 mux_103 mux_121 mux_126 - - - l1.E7 - mux_97 mux_100 mux_10 - - - l1.S7 - mux_113 mux_116 mux_11 mux_14 - - - l1.W8 - mux_1 mux_6 mux_104 - - - l1.E8 - mux_33 mux_7 mux_120 mux_30 - - - l1.S8 - mux_49 mux_23 mux_26 mux_124 - - - l2.W0 - mux_98 mux_4 mux_9 - - - l2.E0 - mux_2 mux_5 mux_8 - - - l2.S0 - mux_18 mux_21 mux_59 mux_12 - - - l2.W2 - mux_34 mux_39 mux_24 mux_29 - - - l2.E2 - mux_99 mux_36 mux_41 mux_46 - - - l2.S2 - mux_115 mux_52 mux_42 mux_45 - - - l2.W4 - mux_3 mux_37 mux_40 mux_62 - - - l2.E4 - mux_35 mux_38 mux_56 mux_61 - - - l2.S4 - mux_51 mux_54 mux_57 mux_60 - - - l3.W0 - mux_64 mux_69 mux_74 - - - l3.E0 - mux_96 mux_70 mux_73 - - - l3.S0 - mux_112 mux_86 mux_91 mux_77 - - - l3.W3 - mux_0 mux_71 mux_89 mux_94 - - - l3.E3 - mux_65 mux_68 mux_106 - - - l3.S3 - mux_81 mux_84 mux_107 mux_110 - - - l3.W6 - mux_97 mux_102 mux_72 - - - l3.E6 - mux_1 mux_103 mux_88 mux_126 - - - l3.S6 - mux_17 mux_119 mux_122 mux_92 - - - l3.W9 - mux_66 mux_100 mux_105 - - - l3.E9 - mux_98 mux_101 mux_104 - - - l3.S9 - mux_114 mux_117 mux_27 mux_108 - - - l3.W12 - mux_2 mux_7 mux_120 mux_125 - - - l3.E12 - mux_67 mux_4 mux_9 mux_14 - - - l3.S12 - mux_83 mux_20 mux_10 mux_13 - - - l3.W15 - mux_99 mux_5 mux_8 mux_30 - - - l3.E15 - mux_3 mux_6 mux_24 mux_29 - - - l3.S15 - mux_19 mux_22 mux_25 mux_28 - - - l3.W18 - mux_32 mux_37 mux_42 - - - l3.E18 - mux_64 mux_38 mux_41 - - - l3.S18 - mux_80 mux_54 mux_59 mux_45 - - - l3.W21 - mux_96 mux_39 mux_57 mux_62 - - - l3.E21 - mux_33 mux_36 mux_74 - - - l3.S21 - mux_49 mux_52 mux_75 mux_78 - - - l4.W0 - mux_65 mux_70 mux_40 - - - l4.E0 - mux_97 mux_71 mux_56 mux_94 - - - l4.S0 - mux_113 mux_87 mux_90 mux_60 - - - l4.W4 - mux_34 mux_68 mux_73 - - - l4.E4 - mux_66 mux_69 mux_72 - - - l4.S4 - mux_82 mux_85 mux_123 mux_76 - - - l4.W8 - mux_98 mux_103 mux_88 mux_93 - - - l4.E8 - mux_35 mux_100 mux_105 mux_110 - - - l4.S8 - mux_51 mux_116 mux_106 mux_109 - - - l4.W12 - mux_67 mux_101 mux_104 mux_126 - - - l4.E12 - mux_99 mux_102 mux_120 mux_125 - - - l4.S12 - mux_115 mux_118 mux_121 mux_124 - - - l8.W0 - mux_0 mux_5 mux_10 - - - l8.E0 - mux_32 mux_6 mux_9 - - - l8.S0 - mux_48 mux_22 mux_27 mux_13 - - - l8.W8 - mux_64 mux_7 mux_25 mux_30 - - - l8.E8 - mux_1 mux_4 mux_42 - - - l8.S8 - mux_17 mux_20 mux_43 mux_46 - - - l1.W9 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.E9 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.S9 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.W10 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.E10 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.S10 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.W11 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.E11 - OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.S11 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.W12 - OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.E12 - OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.S12 - OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - io_top_dspL.f2a_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.f2a_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.f2a_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - io_top_dspL.f2a_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_top_dspL.f2a_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - io_top_dspL.f2a_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - io_top_dspL.f2a_i[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - io_top_dspL.f2a_i[0] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_top_dspL.f2a_i[1] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - io_top_dspL.f2a_i[2] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - io_top_dspL.f2a_i[3] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - io_top_dspL.f2a_i[4] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_top_dspL.f2a_i[5] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 - - - io_top_dspL.f2a_i[6] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 - - - io_top_dspL.f2a_i[0] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 - - - io_top_dspL.f2a_i[1] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 - - - io_top_dspL.f2a_i[2] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 - - - io_top_dspL.f2a_i[3] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 - - - io_top_dspL.f2a_i[4] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 - - - io_top_dspL.f2a_i[5] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 - - - io_top_dspL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 - - - io_top_dspL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 - - - io_top_dspL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 - - - io_top_dspL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - - io_top_dspL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 - - - io_top_dspL.f2a_i[4] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 - - - io_top_dspL.f2a_i[5] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 - - - io_top_dspL.f2a_i[6] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 - - - io_top_dspL.f2a_i[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 - - - io_top_dspL.f2a_i[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 - - - io_top_dspL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 - - - io_top_dspL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 - - - io_top_dspL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 - - - io_top_dspL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 - - - io_top_dspL.f2a_i[6] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 - - - io_top_dspL.f2a_i[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 - - - io_top_dspL.f2a_i[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 - - - io_top_dspL.f2a_i[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 - - - io_top_dspL.f2a_i[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 - - - io_top_dspL.f2a_i[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 - - - io_top_dspL.f2a_i[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.f2a_i[6] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.f2a_i[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 - - - io_top_dspL.f2a_i[1] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 - - - io_top_dspL.f2a_i[2] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 - - - io_top_dspL.f2a_i[3] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 - - - io_top_dspL.f2a_i[4] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 - - - io_top_dspL.f2a_i[5] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 - - - io_top_dspL.f2a_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 - - - io_top_dspL.f2a_i[0] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 - - - io_top_dspL.f2a_i[1] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 - - - io_top_dspL.f2a_i[2] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 - - - io_top_dspL.f2a_i[3] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 - - - io_top_dspL.f2a_i[4] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 - - - io_top_dspL.f2a_i[5] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 - - - io_top_dspL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 - - - io_top_dspL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 - - - io_top_dspL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 - - - io_top_dspL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 - - - io_top_dspL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 - - - io_top_dspL.lclk[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lreset[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lclk[7] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lreset[7] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lclk[14] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lreset[14] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lclk[21] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lreset[21] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lclk[28] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lreset[28] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - io_top_dspL.lclk[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.lreset[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.lclk[8] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.lreset[8] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.lclk[15] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.lreset[15] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.lclk[22] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.lreset[22] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - io_top_dspL.lclk[29] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + + + + + + + + + + + + + + + + + + + clb.Ia[5:0] clb.Ib[5:0] clb.Ic[5:0] clb.Id[5:0] clb.Ie[5:0] clb.If[5:0] clb.Ig[5:0] clb.Ih[5:0] clb.o[7:0] clb.q[7:0] + clb.clk + + + + + + + + + + + + + + mult_36.a[0:8] mult_36.b[0:8] mult_36.out[0:17] + mult_36.a[9:17] mult_36.b[9:17] mult_36.out[18:35] + mult_36.a[18:26] mult_36.b[18:26] mult_36.out[36:53] + mult_36.a[27:35] mult_36.b[27:35] mult_36.out[54:71] + + + + + + + + + + + + + + + + + + + + memory.clk memory.addr1[0:2] memory.addr2[0:2] memory.data[0:9] memory.out[0:10] + memory.addr1[3:5] memory.addr2[3:5] memory.data[10:19] memory.out[11:21] + memory.addr1[6:8] memory.addr2[6:8] memory.data[20:29] memory.out[22:32] + memory.addr1[9:11] memory.addr2[9:11] memory.data[30:39] memory.out[33:43] + memory.addr1[12:14] memory.addr2[12:14] memory.data[40:49] memory.out[44:53] + memory.we1 memory.we2 memory.data[50:63] memory.out[54:63] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1.43259e-10 + 1.43259e-10 + 1.43259e-10 + 1.43259e-10 + 1.43259e-10 + 1.43259e-10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 0 1 + 1 1 + + + + 1 0 0 1 + 1 0 1 + - D + + + + 1 0 0 0 0 0 1 + 1 0 0 0 0 1 + + + + 1 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 1 + + + + 1 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 1 + - - D - - - - - - - - + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + clb.o[0] clb.q[0] clb.o[1] clb.q[1] clb.o[2] clb.q[2] clb.o[3] clb.q[3] - - io_top_dspL.lreset[29] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + clb.o[4] clb.q[4] clb.o[5] clb.q[5] clb.o[6] clb.q[6] clb.o[7] clb.q[7] - - io_top_dspL.lclk[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[0] clb.q[0] clb.o[1] clb.q[1] clb.o[2] clb.q[2] clb.o[3] clb.q[3] - - io_top_dspL.lreset[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[4] clb.q[4] clb.o[5] clb.q[5] clb.o[6] clb.q[6] clb.o[7] clb.q[7] - - io_top_dspL.lclk[9] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[0] clb.q[0] clb.o[1] clb.q[1] clb.o[2] clb.q[2] clb.o[3] clb.q[3] - - io_top_dspL.lreset[9] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[4] clb.q[4] clb.o[5] clb.q[5] clb.o[6] clb.q[6] clb.o[7] clb.q[7] - - io_top_dspL.lclk[16] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[0] clb.q[0] clb.o[1] clb.q[1] clb.o[2] clb.q[2] clb.o[3] clb.q[3] - - io_top_dspL.lreset[16] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[4] clb.q[4] clb.o[5] clb.q[5] clb.o[6] clb.q[6] clb.o[7] clb.q[7] - - io_top_dspL.lclk[23] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[0] clb.q[0] clb.o[1] clb.q[1] clb.o[2] clb.q[2] clb.o[3] clb.q[3] - - io_top_dspL.lreset[23] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[4] clb.q[4] clb.o[5] clb.q[5] clb.o[6] clb.q[6] clb.o[7] clb.q[7] - - io_top_dspL.lclk[30] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[0] clb.q[0] clb.o[1] clb.q[1] clb.o[2] clb.q[2] clb.o[3] clb.q[3] - - io_top_dspL.lreset[30] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + clb.o[4] clb.q[4] clb.o[5] clb.q[5] clb.o[6] clb.q[6] clb.o[7] clb.q[7] - - io_top_dspL.lclk[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + clb.o[0] clb.q[0] clb.o[1] clb.q[1] clb.o[2] clb.q[2] clb.o[3] clb.q[3] - - io_top_dspL.lreset[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + clb.o[4] clb.q[4] clb.o[5] clb.q[5] clb.o[6] clb.q[6] clb.o[7] clb.q[7] - - io_top_dspL.lclk[10] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + clb.o[0] clb.q[0] clb.o[1] clb.q[1] clb.o[2] clb.q[2] clb.o[3] clb.q[3] - - io_top_dspL.lreset[10] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + clb.o[4] clb.q[4] clb.o[5] clb.q[5] clb.o[6] clb.q[6] clb.o[7] clb.q[7] - - io_top_dspL.lclk[17] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 clb.o[0] - - io_top_dspL.lreset[17] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 clb.o[1] - - io_top_dspL.lclk[24] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 clb.o[2] - - io_top_dspL.lreset[24] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 clb.o[3] - - io_top_dspL.lclk[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.N1 l6.N1 l6.N18 l8.N11 clb.o[4] - - io_top_dspL.lreset[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.E1 l6.E1 l6.E18 l8.E11 clb.o[5] - - io_top_dspL.lclk[11] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.S1 l6.S1 l6.S18 l8.S11 clb.o[6] - - io_top_dspL.lreset[11] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.W1 l6.W1 l6.W18 l8.W11 clb.o[7] - - io_top_dspL.lclk[18] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.N2 l6.N2 l6.N19 l8.N12 clb.q[0] - - io_top_dspL.lreset[18] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.E2 l6.E2 l6.E19 l8.E12 clb.q[1] - - io_top_dspL.lclk[25] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.S2 l6.S2 l6.S19 l8.S12 clb.q[2] - - io_top_dspL.lreset[25] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.W2 l6.W2 l6.W19 l8.W12 clb.q[3] - - io_top_dspL.lclk[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.N3 l6.N3 l6.N20 l8.N13 clb.q[4] - - io_top_dspL.lreset[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.E3 l6.E3 l6.E20 l8.E13 clb.q[5] - - io_top_dspL.lclk[12] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.S3 l6.S3 l6.S20 l8.S13 clb.q[6] - - io_top_dspL.lreset[12] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.W3 l6.W3 l6.W20 l8.W13 clb.q[7] - - io_top_dspL.lclk[19] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - - io_top_dspL.lreset[19] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - - io_top_dspL.lclk[26] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - - io_top_dspL.lreset[26] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - - io_top_dspL.lclk[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - - io_top_dspL.lreset[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - - io_top_dspL.lclk[13] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - - io_top_dspL.lreset[13] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - - io_top_dspL.lclk[20] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - - io_top_dspL.lreset[20] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - - io_top_dspL.lclk[27] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - - io_top_dspL.lreset[27] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - - io_top_dspL.lclk[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - - io_top_dspL.lreset[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - - io_top_dspL.lclk[14] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - - io_top_dspL.lreset[14] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - - io_top_dspL.lclk[21] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.N3 l6.N8 l8.N1 l12.N2 clb.o[0] - - io_top_dspL.lreset[21] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.E3 l6.E8 l8.E1 l12.E2 clb.o[1] - - io_top_dspL.lclk[28] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.S3 l6.S8 l8.S1 l12.S2 clb.o[2] - - io_top_dspL.lreset[28] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.W3 l6.W8 l8.W1 l12.W2 clb.o[3] - - io_top_dspL.lclk[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.N4 l6.N9 l8.N2 l12.N3 clb.o[4] - - io_top_dspL.lreset[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.E4 l6.E9 l8.E2 l12.E3 clb.o[5] - - io_top_dspL.lclk[15] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.S4 l6.S9 l8.S2 l12.S3 clb.o[6] - - io_top_dspL.lreset[15] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.W4 l6.W9 l8.W2 l12.W3 clb.o[7] - - io_top_dspL.lclk[22] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.N5 l6.N10 l8.N3 l12.N4 clb.q[0] - - io_top_dspL.lreset[22] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.E5 l6.E10 l8.E3 l12.E4 clb.q[1] - - io_top_dspL.lclk[29] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.S5 l6.S10 l8.S3 l12.S4 clb.q[2] - - io_top_dspL.lreset[29] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.W5 l6.W10 l8.W3 l12.W4 clb.q[3] - - io_top_dspL.lclk[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.N0 l6.N11 l8.N4 l12.N5 clb.q[4] - - io_top_dspL.lreset[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.E0 l6.E11 l8.E4 l12.E5 clb.q[5] - - io_top_dspL.lclk[16] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.S0 l6.S11 l8.S4 l12.S5 clb.q[6] - - io_top_dspL.lreset[16] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.W0 l6.W11 l8.W4 l12.W5 clb.q[7] - - io_top_dspL.lclk[23] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - - io_top_dspL.lreset[23] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - - io_top_dspL.lclk[30] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - - io_top_dspL.lreset[30] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - - io_top_dspL.lclk[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - - io_top_dspL.lreset[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - - io_top_dspL.lclk[17] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - - io_top_dspL.lreset[17] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - - io_top_dspL.lclk[24] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - - io_top_dspL.lreset[24] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - - io_top_dspL.lclk[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - - io_top_dspL.lreset[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - io_top_dspL.lclk[18] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - io_top_dspL.lreset[18] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - io_top_dspL.lclk[25] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - io_top_dspL.lreset[25] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - io_top_dspL.lclk[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.N5 l6.N16 l8.N9 l12.N10 clb.o[0] - - io_top_dspL.lreset[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.E5 l6.E16 l8.E9 l12.E10 clb.o[1] - - io_top_dspL.lclk[19] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.S5 l6.S16 l8.S9 l12.S10 clb.o[2] - - io_top_dspL.lreset[19] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.W5 l6.W16 l8.W9 l12.W10 clb.o[3] - - io_top_dspL.lclk[26] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l1.N0 l3.N0 l6.N5 l6.N16 clb.o[0] - - io_top_dspL.lreset[26] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l1.E0 l3.E0 l6.E5 l6.E16 clb.o[1] - - io_top_dspL.lclk[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.S0 l3.S0 l6.S5 l6.S16 clb.o[2] - - io_top_dspL.lreset[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.W0 l3.W0 l6.W5 l6.W16 clb.o[3] - - io_top_dspL.lclk[20] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.N1 l3.N1 l6.N6 l6.N17 clb.o[4] - - io_top_dspL.lreset[20] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.E1 l3.E1 l6.E6 l6.E17 clb.o[5] - - io_top_dspL.lclk[27] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.S1 l3.S1 l6.S6 l6.S17 clb.o[6] - - io_top_dspL.lreset[27] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.W1 l3.W1 l6.W6 l6.W17 clb.o[7] - - io_top_dspL.lclk[14] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.N2 l3.N2 l6.N7 l6.N18 clb.q[0] - - io_top_dspL.lreset[14] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.E2 l3.E2 l6.E7 l6.E18 clb.q[1] - - io_top_dspL.lclk[21] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.S2 l3.S2 l6.S7 l6.S18 clb.q[2] - - io_top_dspL.lreset[21] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.W2 l3.W2 l6.W7 l6.W18 clb.q[3] - - io_top_dspL.lclk[28] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.N3 l3.N3 l6.N8 l6.N19 clb.q[4] - - io_top_dspL.lreset[28] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.E3 l3.E3 l6.E8 l6.E19 clb.q[5] - - io_top_dspL.lclk[15] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.S3 l3.S3 l6.S8 l6.S19 clb.q[6] - - io_top_dspL.lreset[15] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.W3 l3.W3 l6.W8 l6.W19 clb.q[7] - - io_top_dspL.lclk[22] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - io_top_dspL.lreset[22] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - io_top_dspL.lclk[29] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - io_top_dspL.lreset[29] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - io_top_dspL.lclk[16] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + + clb.Ia[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - io_top_dspL.lreset[16] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + clb.Ib[0] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - io_top_dspL.lclk[23] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + clb.Ic[0] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - io_top_dspL.lreset[23] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + clb.Id[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - io_top_dspL.lclk[30] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + clb.Ie[0] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - io_top_dspL.lreset[30] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + clb.If[0] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - io_top_dspL.lclk[17] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + clb.Ig[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - io_top_dspL.lreset[17] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + clb.Ih[0] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - io_top_dspL.lclk[24] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + clb.Ia[1] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - io_top_dspL.lreset[24] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + clb.Ib[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - io_top_dspL.lclk[18] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + clb.Ic[1] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - io_top_dspL.lreset[18] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + clb.Id[1] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - io_top_dspL.lclk[25] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + clb.Ie[1] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - io_top_dspL.lreset[25] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + clb.If[1] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - io_top_dspL.lclk[19] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + clb.Ig[1] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - io_top_dspL.lreset[19] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + clb.Ih[1] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - io_top_dspL.lclk[26] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + clb.Ia[2] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - io_top_dspL.lreset[26] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + clb.Ib[2] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - io_top_dspL.lclk[20] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + clb.Ic[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - io_top_dspL.lreset[20] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + clb.Id[2] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - io_top_dspL.lclk[27] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + clb.Ie[2] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - io_top_dspL.lreset[27] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + clb.If[2] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - io_top_dspL.lclk[21] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + clb.Ig[2] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - io_top_dspL.lreset[21] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + clb.Ih[2] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - io_top_dspL.lclk[28] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + clb.Ia[3] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - io_top_dspL.lreset[28] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + clb.Ib[3] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - io_top_dspL.lclk[22] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + clb.Ic[3] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - io_top_dspL.lreset[22] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + clb.Id[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - io_top_dspL.lclk[29] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + clb.Ie[3] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - io_top_dspL.lreset[29] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + clb.If[3] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - io_top_dspL.lclk[23] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + clb.Ig[3] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - io_top_dspL.lreset[23] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + clb.Ih[3] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - io_top_dspL.lclk[30] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + clb.Ia[4] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - io_top_dspL.lreset[30] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + clb.Ib[4] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - io_top_dspL.lclk[24] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + clb.Ic[4] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - io_top_dspL.lreset[24] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + clb.Id[4] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - io_top_dspL.lclk[25] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + clb.Ie[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - io_top_dspL.lreset[25] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + clb.If[4] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - io_top_dspL.lclk[26] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + clb.Ig[4] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - io_top_dspL.lreset[26] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + clb.Ih[4] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - io_top_dspL.lclk[27] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + clb.Ia[5] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - io_top_dspL.lreset[27] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + clb.Ib[5] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - io_top_dspL.lclk[28] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + clb.Ic[5] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - io_top_dspL.lreset[28] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + clb.Id[5] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - io_top_dspL.lclk[29] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + clb.Ie[5] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - io_top_dspL.lreset[29] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + clb.If[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - io_top_dspL.lclk[30] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + clb.Ig[5] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - io_top_dspL.lreset[30] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + clb.Ih[5] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 io_top_ramL.a2f_o[8] + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - l1.W2 l2.W1 l4.W3 io_top_ramL.a2f_o[0] + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - l1.W3 l3.W5 l8.W7 io_top_ramL.a2f_o[16] + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - l1.W4 l3.W8 l8.W15 + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - l1.N5 l1.N6 l3.N11 io_top_ramL.a2f_o[9] + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - l1.N7 l2.N3 l4.N7 io_top_ramL.a2f_o[1] + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - l1.N8 l3.N14 l8.N7 io_top_ramL.a2f_o[17] + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - l1.N9 l3.N17 l8.N15 + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - l1.E10 l1.E11 l3.E20 io_top_ramL.a2f_o[10] + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - l1.E12 l2.E5 l4.E11 io_top_ramL.a2f_o[2] + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - l1.E0 l3.E23 l8.E7 io_top_ramL.a2f_o[18] + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - l1.E1 l3.E2 l8.E15 + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - io_top_ramL.a2f_o[11] + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - io_top_ramL.a2f_o[3] + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - io_top_ramL.a2f_o[19] + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - l1.W7 l1.W8 l3.W14 io_top_ramL.a2f_o[12] + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - l1.W9 l2.W3 l4.W3 io_top_ramL.a2f_o[4] + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - l1.W10 l3.W17 l8.W7 io_top_ramL.a2f_o[20] + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - l1.W11 l3.W20 l8.W15 + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - l1.N12 l1.N0 l3.N23 io_top_ramL.a2f_o[13] + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - l1.N1 l2.N5 l4.N7 io_top_ramL.a2f_o[5] + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - l1.N2 l3.N2 l8.N7 io_top_ramL.a2f_o[21] + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - l1.N3 l3.N5 l8.N15 + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - l1.E4 l1.E5 l3.E8 io_top_ramL.a2f_o[14] + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - l1.E6 l2.E1 l4.E11 io_top_ramL.a2f_o[6] + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - l1.E7 l3.E11 l8.E7 io_top_ramL.a2f_o[22] + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - l1.E8 l3.E14 l8.E15 + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - io_top_ramL.a2f_o[15] + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - io_top_ramL.a2f_o[7] + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - io_top_ramL.a2f_o[23] + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - l1.W1 l1.W2 l3.W2 io_top_ramL.a2f_o[8] + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - l1.W3 l2.W5 l4.W3 io_top_ramL.a2f_o[0] + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - l1.W4 l3.W5 l8.W7 io_top_ramL.a2f_o[16] + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - l1.W5 l3.W8 l8.W15 + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - l1.N6 l1.N7 l3.N11 io_top_ramL.a2f_o[9] + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - l1.N8 l2.N1 l4.N7 io_top_ramL.a2f_o[1] + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - l1.N9 l3.N14 l8.N7 io_top_ramL.a2f_o[17] + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - l1.N10 l3.N17 l8.N15 + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - l1.E11 l1.E12 l3.E20 io_top_ramL.a2f_o[10] + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - l1.E0 l2.E3 l4.E11 io_top_ramL.a2f_o[2] + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - l1.E1 l3.E23 l8.E7 io_top_ramL.a2f_o[18] + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - l1.E2 l3.E2 l8.E15 + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - io_top_ramL.a2f_o[11] + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - io_top_ramL.a2f_o[3] + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - io_top_ramL.a2f_o[19] + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - l1.W8 l1.W9 l3.W14 io_top_ramL.a2f_o[12] + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - l1.W10 l2.W1 l4.W3 io_top_ramL.a2f_o[4] + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - l1.W11 l3.W17 l8.W7 io_top_ramL.a2f_o[20] + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - l1.W12 l3.W20 l8.W15 + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - l1.N0 l1.N1 l3.N23 io_top_ramL.a2f_o[13] + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - l1.N2 l2.N3 l4.N7 io_top_ramL.a2f_o[5] + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - l1.N3 l3.N2 l8.N7 io_top_ramL.a2f_o[21] + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - l1.N4 l3.N5 l8.N15 + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - l1.E5 l1.E6 l3.E8 io_top_ramL.a2f_o[14] + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - l1.E7 l2.E5 l4.E11 io_top_ramL.a2f_o[6] + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - l1.E8 l3.E11 l8.E7 io_top_ramL.a2f_o[22] + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - l1.E9 l3.E14 l8.E15 + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - io_top_ramL.a2f_o[15] + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - io_top_ramL.a2f_o[7] + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - io_top_ramL.a2f_o[23] + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - l1.W2 l1.W3 l3.W2 io_top_ramL.a2f_o[8] + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - l1.W4 l2.W3 l4.W3 io_top_ramL.a2f_o[0] + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - l1.W5 l3.W5 l8.W7 io_top_ramL.a2f_o[16] + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 io_top_ramL.a2f_o[9] - - - l1.N9 l2.N5 l4.N7 io_top_ramL.a2f_o[1] - - - l1.N10 l3.N14 l8.N7 io_top_ramL.a2f_o[17] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 io_top_ramL.a2f_o[10] - - - l1.E1 l2.E1 l4.E11 io_top_ramL.a2f_o[2] - - - l1.E2 l3.E23 l8.E7 io_top_ramL.a2f_o[18] - - - l1.E3 l3.E2 l8.E15 - - - io_top_ramL.a2f_o[11] - - - io_top_ramL.a2f_o[3] - - - io_top_ramL.a2f_o[19] - - - l1.W9 l1.W10 l3.W14 io_top_ramL.a2f_o[12] - - - l1.W11 l2.W5 l4.W3 io_top_ramL.a2f_o[4] - - - l1.W12 l3.W17 l8.W7 io_top_ramL.a2f_o[20] - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 io_top_ramL.a2f_o[13] - - - l1.N3 l2.N1 l4.N7 io_top_ramL.a2f_o[5] + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.N4 l3.N2 l8.N7 io_top_ramL.a2f_o[21] - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 io_top_ramL.a2f_o[14] - - - l1.E8 l2.E3 l4.E11 io_top_ramL.a2f_o[6] - - - l1.E9 l3.E11 l8.E7 io_top_ramL.a2f_o[22] - - - l1.E10 l3.E14 l8.E15 - - - io_top_ramL.a2f_o[15] - - - io_top_ramL.a2f_o[7] - - - io_top_ramL.a2f_o[23] - - - l1.W3 l1.W4 l3.W2 io_top_ramL.a2f_o[8] - - - l1.W5 l2.W1 l4.W3 io_top_ramL.a2f_o[0] - - - l1.W6 l3.W5 l8.W7 io_top_ramL.a2f_o[16] - - - l1.W7 l3.W8 l8.W15 - - - l1.N8 l1.N9 l3.N11 io_top_ramL.a2f_o[9] - - - l1.N10 l2.N3 l4.N7 io_top_ramL.a2f_o[1] - - - l1.N11 l3.N14 l8.N7 io_top_ramL.a2f_o[17] - - - l1.N12 l3.N17 l8.N15 - - - l1.E0 l1.E1 l3.E20 io_top_ramL.a2f_o[10] - - - l1.E2 l2.E5 l4.E11 io_top_ramL.a2f_o[2] - - - l1.E3 l3.E23 l8.E7 io_top_ramL.a2f_o[18] - - - l1.E4 l3.E2 l8.E15 - - - io_top_ramL.a2f_o[11] - - - io_top_ramL.a2f_o[3] - - - io_top_ramL.a2f_o[19] + + + + + + + + + + + + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] - - l1.W10 l1.W11 l3.W14 io_top_ramL.a2f_o[12] + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] - - l1.W12 l2.W3 l4.W3 io_top_ramL.a2f_o[4] + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] - - l1.W0 l3.W17 l8.W7 io_top_ramL.a2f_o[20] + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] - - l1.W1 l3.W20 l8.W15 + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] - - l1.N2 l1.N3 l3.N23 io_top_ramL.a2f_o[13] + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] - - l1.N4 l2.N5 l4.N7 io_top_ramL.a2f_o[5] + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] - - l1.N5 l3.N2 l8.N7 io_top_ramL.a2f_o[21] + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] - - l1.N6 l3.N5 l8.N15 + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] - - l1.E7 l1.E8 l3.E8 io_top_ramL.a2f_o[14] + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] - - l1.E9 l2.E1 l4.E11 io_top_ramL.a2f_o[6] + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] - - l1.E10 l3.E11 l8.E7 io_top_ramL.a2f_o[22] + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] - - l1.E11 l3.E14 l8.E15 + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] - - io_top_ramL.a2f_o[15] + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] - - io_top_ramL.a2f_o[7] + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] - - io_top_ramL.a2f_o[23] + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_top_ramL.a2f_o[0] OG_0 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 io_left.inpad[0] - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 io_top_ramL.a2f_o[8] + io_left.inpad[1] - l1.E5 l1.N4 l3.E8 l4.E3 io_top_ramL.a2f_o[16] + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 io_left.inpad[2] - l1.W11 l1.N4 l3.W20 l3.N8 l4.W11 io_top_ramL.a2f_o[1] + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 io_left.inpad[3] - l1.E4 l1.E3 l3.E5 l4.E15 io_top_ramL.a2f_o[9] + l1.N1 l6.N1 l6.N18 l8.N11 io_left.inpad[4] - l1.W10 l2.W1 l3.W17 io_top_ramL.a2f_o[17] OG_2 l1.N2 + io_left.inpad[5] - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 io_top_ramL.a2f_o[2] OG_2 + l1.S1 l6.S1 l6.S18 l8.S11 io_left.inpad[6] - l1.E9 l2.E5 l3.E14 l4.E7 io_top_ramL.a2f_o[10] OG_3 l1.N9 + l1.W1 l6.W1 l6.W18 l8.W11 io_left.inpad[7] - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_top_ramL.a2f_o[18] OG_4 + l1.N2 l6.N2 l6.N19 l8.N12 io_left.inpad[0] - l1.W8 l1.E7 l2.W3 l3.W11 l4.W3 io_top_ramL.a2f_o[3] + io_left.inpad[1] - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 io_top_ramL.a2f_o[11] + l1.S2 l6.S2 l6.S19 l8.S12 io_left.inpad[2] - l1.E7 l3.E8 l4.E15 io_top_ramL.a2f_o[19] + l1.W2 l6.W2 l6.W19 l8.W12 io_left.inpad[3] - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 io_top_ramL.a2f_o[4] + l1.N3 l6.N3 l6.N20 l8.N13 io_left.inpad[4] - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 io_top_ramL.a2f_o[12] OG_6 l1.E5 + io_left.inpad[5] - l1.E12 l2.E1 l3.E14 io_top_ramL.a2f_o[20] OG_6 + l1.S3 l6.S3 l6.S20 l8.S13 io_left.inpad[6] - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 io_top_ramL.a2f_o[5] OG_7 l1.N0 + l1.W3 l6.W3 l6.W20 l8.W13 io_left.inpad[7] - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_top_ramL.a2f_o[13] OG_0 + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 io_top_ramL.a2f_o[21] + omux-1 - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 io_top_ramL.a2f_o[6] + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - l1.E3 l1.N9 l3.E20 l3.N8 l4.E3 io_top_ramL.a2f_o[14] + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 io_top_ramL.a2f_o[22] + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - l1.E2 l2.E3 l3.E17 io_top_ramL.a2f_o[7] OG_2 l1.E0 + omux-5 - l1.W8 l2.W5 l3.W2 io_top_ramL.a2f_o[15] OG_2 l1.N10 + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - l1.W1 l2.W1 l3.W14 l4.W15 io_top_ramL.a2f_o[23] OG_3 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_top_ramL.a2f_o[0] OG_4 + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - l1.E0 l1.E12 l2.E5 l3.E11 l4.E11 io_top_ramL.a2f_o[8] + omux-9 - l1.W6 l1.N5 l3.W20 l4.W15 io_top_ramL.a2f_o[16] + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - l1.W12 l3.W8 l4.W7 io_top_ramL.a2f_o[1] + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - l1.W5 l1.E4 l3.W17 l4.W11 io_top_ramL.a2f_o[9] + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 io_top_ramL.a2f_o[17] OG_6 l1.W6 + omux-13 - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 io_top_ramL.a2f_o[2] OG_6 + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 io_top_ramL.a2f_o[10] OG_7 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_top_ramL.a2f_o[18] OG_0 + l2.N3 l6.N8 l8.N1 l12.N2 io_left.inpad[0] - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 io_top_ramL.a2f_o[3] + io_left.inpad[1] - l1.E2 l1.N1 l3.E8 l4.E3 io_top_ramL.a2f_o[11] + l2.S3 l6.S8 l8.S1 l12.S2 io_left.inpad[2] - l1.W8 l1.N1 l3.W20 l3.N8 l4.W11 io_top_ramL.a2f_o[19] + l2.W3 l6.W8 l8.W1 l12.W2 io_left.inpad[3] - l1.E1 l1.E0 l3.E5 l4.E15 io_top_ramL.a2f_o[4] + l2.N4 l6.N9 l8.N2 l12.N3 io_left.inpad[4] - l1.W7 l2.W5 l3.W17 io_top_ramL.a2f_o[12] OG_2 + io_left.inpad[5] - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 io_top_ramL.a2f_o[20] OG_2 l1.E0 + l2.S4 l6.S9 l8.S2 l12.S3 io_left.inpad[6] - l1.E6 l2.E3 l3.E14 l4.E7 io_top_ramL.a2f_o[5] OG_3 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 io_left.inpad[7] - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_top_ramL.a2f_o[13] OG_4 + l2.N5 l6.N10 l8.N3 l12.N4 io_left.inpad[0] - l1.W5 l1.E4 l2.W1 l3.W11 l4.W3 io_top_ramL.a2f_o[21] + io_left.inpad[1] - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 io_top_ramL.a2f_o[6] + l2.S5 l6.S10 l8.S3 l12.S4 io_left.inpad[2] - l1.E4 l3.E8 l4.E15 io_top_ramL.a2f_o[14] + l2.W5 l6.W10 l8.W3 l12.W4 io_left.inpad[3] - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 io_top_ramL.a2f_o[22] + l3.N0 l6.N11 l8.N4 l12.N5 io_left.inpad[4] - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 io_top_ramL.a2f_o[7] OG_6 l1.E2 + io_left.inpad[5] - l1.E9 l2.E5 l3.E14 io_top_ramL.a2f_o[15] OG_6 l1.W3 + l3.S0 l6.S11 l8.S4 l12.S5 io_left.inpad[6] - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 io_top_ramL.a2f_o[23] OG_7 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 io_left.inpad[7] - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_top_ramL.a2f_o[0] OG_0 + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 io_top_ramL.a2f_o[8] + omux-1 - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 io_top_ramL.a2f_o[16] + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - l1.E0 l1.N6 l3.E20 l3.N8 l4.E3 io_top_ramL.a2f_o[1] + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 io_top_ramL.a2f_o[9] + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - l1.E12 l2.E1 l3.E17 io_top_ramL.a2f_o[17] OG_2 l1.W12 + omux-5 - l1.W5 l2.W3 l3.W2 io_top_ramL.a2f_o[2] OG_2 l1.W4 + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - l1.W11 l2.W5 l3.W14 l4.W15 io_top_ramL.a2f_o[10] OG_3 l1.N10 + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_top_ramL.a2f_o[18] OG_4 + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - l1.E10 l1.E9 l2.E3 l3.E11 l4.E11 io_top_ramL.a2f_o[3] + omux-9 - l1.W3 l1.N2 l3.W20 l4.W15 io_top_ramL.a2f_o[11] + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - l1.W9 l3.W8 l4.W7 io_top_ramL.a2f_o[19] - - - io_top_ramL.a2f_o[17] io_top_ramL.a2f_o[0] io_top_ramL.a2f_o[8] io_top_ramL.a2f_o[9] - - - io_top_ramL.a2f_o[17] io_top_ramL.a2f_o[0] io_top_ramL.a2f_o[1] io_top_ramL.a2f_o[8] + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - io_top_ramL.a2f_o[16] io_top_ramL.a2f_o[0] io_top_ramL.a2f_o[1] io_top_ramL.a2f_o[9] + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - io_top_ramL.a2f_o[16] io_top_ramL.a2f_o[1] io_top_ramL.a2f_o[8] io_top_ramL.a2f_o[9] + + omux-13 - - io_top_ramL.a2f_o[19] io_top_ramL.a2f_o[2] io_top_ramL.a2f_o[10] io_top_ramL.a2f_o[11] + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - io_top_ramL.a2f_o[19] io_top_ramL.a2f_o[2] io_top_ramL.a2f_o[3] io_top_ramL.a2f_o[10] + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - io_top_ramL.a2f_o[18] io_top_ramL.a2f_o[2] io_top_ramL.a2f_o[3] io_top_ramL.a2f_o[11] + + l3.N5 l6.N16 l8.N9 l12.N10 io_left.inpad[0] - - io_top_ramL.a2f_o[18] io_top_ramL.a2f_o[3] io_top_ramL.a2f_o[10] io_top_ramL.a2f_o[11] + + io_left.inpad[1] - - io_top_ramL.a2f_o[21] io_top_ramL.a2f_o[4] io_top_ramL.a2f_o[12] io_top_ramL.a2f_o[13] + + l3.S5 l6.S16 l8.S9 l12.S10 io_left.inpad[2] - - io_top_ramL.a2f_o[21] io_top_ramL.a2f_o[4] io_top_ramL.a2f_o[5] io_top_ramL.a2f_o[12] + + l3.W5 l6.W16 l8.W9 l12.W10 io_left.inpad[3] - - io_top_ramL.a2f_o[20] io_top_ramL.a2f_o[4] io_top_ramL.a2f_o[5] io_top_ramL.a2f_o[13] + + l1.N0 l3.N0 l6.N5 l6.N16 io_left.inpad[0] - - io_top_ramL.a2f_o[20] io_top_ramL.a2f_o[5] io_top_ramL.a2f_o[12] io_top_ramL.a2f_o[13] + + io_left.inpad[1] - - io_top_ramL.a2f_o[23] io_top_ramL.a2f_o[6] io_top_ramL.a2f_o[14] io_top_ramL.a2f_o[15] + + l1.S0 l3.S0 l6.S5 l6.S16 io_left.inpad[2] - - io_top_ramL.a2f_o[23] io_top_ramL.a2f_o[6] io_top_ramL.a2f_o[7] io_top_ramL.a2f_o[14] + + l1.W0 l3.W0 l6.W5 l6.W16 io_left.inpad[3] - - io_top_ramL.a2f_o[22] io_top_ramL.a2f_o[6] io_top_ramL.a2f_o[7] io_top_ramL.a2f_o[15] + + l1.N1 l3.N1 l6.N6 l6.N17 io_left.inpad[4] - - io_top_ramL.a2f_o[22] io_top_ramL.a2f_o[7] io_top_ramL.a2f_o[14] io_top_ramL.a2f_o[15] + + io_left.inpad[5] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.S1 l3.S1 l6.S6 l6.S17 io_left.inpad[6] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.W1 l3.W1 l6.W6 l6.W17 io_left.inpad[7] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.N2 l3.N2 l6.N7 l6.N18 io_left.inpad[0] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + io_left.inpad[1] - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.S2 l3.S2 l6.S7 l6.S18 io_left.inpad[2] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.W2 l3.W2 l6.W7 l6.W18 io_left.inpad[3] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.N3 l3.N3 l6.N8 l6.N19 io_left.inpad[4] - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + io_left.inpad[5] - - - - l1.W0 - mux_0 mux_5 mux_10 - - - l1.E0 - mux_32 mux_6 mux_9 - - - l1.S0 - mux_48 mux_22 mux_27 mux_13 - - - l1.W1 - mux_64 mux_7 mux_25 mux_30 - - - l1.E1 - mux_1 mux_4 mux_42 - - - l1.S1 - mux_17 mux_20 mux_43 mux_46 - - - l1.W2 - mux_33 mux_38 mux_8 - - - l1.E2 - mux_65 mux_39 mux_24 mux_62 - - - l1.S2 - mux_81 mux_55 mux_58 mux_28 - - - l1.W3 - mux_2 mux_36 mux_41 - - - l1.E3 - mux_34 mux_37 mux_40 - - - l1.S3 - mux_50 mux_53 mux_91 mux_44 - - - l1.W4 - mux_66 mux_71 mux_56 mux_61 - - - l1.E4 - mux_3 mux_68 mux_73 mux_78 - - - l1.S4 - mux_19 mux_84 mux_74 mux_77 - - - l1.W5 - mux_35 mux_69 mux_72 mux_94 - - - l1.E5 - mux_67 mux_70 mux_88 mux_93 - - - l1.S5 - mux_83 mux_86 mux_89 mux_92 - - - l1.W6 - mux_96 mux_101 mux_106 - - - l1.E6 - mux_0 mux_102 mux_105 - - - l1.S6 - mux_16 mux_118 mux_123 mux_109 - - - l1.W7 - mux_32 mux_103 mux_121 mux_126 - - - l1.E7 - mux_97 mux_100 mux_10 - - - l1.S7 - mux_113 mux_116 mux_11 mux_14 - - - l1.W8 - mux_1 mux_6 mux_104 - - - l1.E8 - mux_33 mux_7 mux_120 mux_30 - - - l1.S8 - mux_49 mux_23 mux_26 mux_124 - - - l2.W0 - mux_98 mux_4 mux_9 - - - l2.E0 - mux_2 mux_5 mux_8 - - - l2.S0 - mux_18 mux_21 mux_59 mux_12 - - - l2.W2 - mux_34 mux_39 mux_24 mux_29 - - - l2.E2 - mux_99 mux_36 mux_41 mux_46 - - - l2.S2 - mux_115 mux_52 mux_42 mux_45 - - - l2.W4 - mux_3 mux_37 mux_40 mux_62 - - - l2.E4 - mux_35 mux_38 mux_56 mux_61 - - - l2.S4 - mux_51 mux_54 mux_57 mux_60 - - - l3.W0 - mux_64 mux_69 mux_74 - - - l3.E0 - mux_96 mux_70 mux_73 - - - l3.S0 - mux_112 mux_86 mux_91 mux_77 - - - l3.W3 - mux_0 mux_71 mux_89 mux_94 - - - l3.E3 - mux_65 mux_68 mux_106 - - - l3.S3 - mux_81 mux_84 mux_107 mux_110 - - - l3.W6 - mux_97 mux_102 mux_72 - - - l3.E6 - mux_1 mux_103 mux_88 mux_126 - - - l3.S6 - mux_17 mux_119 mux_122 mux_92 - - - l3.W9 - mux_66 mux_100 mux_105 - - - l3.E9 - mux_98 mux_101 mux_104 - - - l3.S9 - mux_114 mux_117 mux_27 mux_108 - - - l3.W12 - mux_2 mux_7 mux_120 mux_125 + + l1.S3 l3.S3 l6.S8 l6.S19 io_left.inpad[6] - - l3.E12 - mux_67 mux_4 mux_9 mux_14 + + l1.W3 l3.W3 l6.W8 l6.W19 io_left.inpad[7] - - l3.S12 - mux_83 mux_20 mux_10 mux_13 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - l3.W15 - mux_99 mux_5 mux_8 mux_30 + + omux-1 - - l3.E15 - mux_3 mux_6 mux_24 mux_29 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - l3.S15 - mux_19 mux_22 mux_25 mux_28 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - l3.W18 - mux_32 mux_37 mux_42 - - - l3.E18 - mux_64 mux_38 mux_41 - - - l3.S18 - mux_80 mux_54 mux_59 mux_45 - - - l3.W21 - mux_96 mux_39 mux_57 mux_62 - - - l3.E21 - mux_33 mux_36 mux_74 - - - l3.S21 - mux_49 mux_52 mux_75 mux_78 - - - l4.W0 - mux_65 mux_70 mux_40 - - - l4.E0 - mux_97 mux_71 mux_56 mux_94 - - - l4.S0 - mux_113 mux_87 mux_90 mux_60 - - - l4.W4 - mux_34 mux_68 mux_73 - - - l4.E4 - mux_66 mux_69 mux_72 - - - l4.S4 - mux_82 mux_85 mux_123 mux_76 - - - l4.W8 - mux_98 mux_103 mux_88 mux_93 - - - l4.E8 - mux_35 mux_100 mux_105 mux_110 - - - l4.S8 - mux_51 mux_116 mux_106 mux_109 - - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + + + io_left.outpad[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - l4.E12 - mux_99 mux_102 mux_120 mux_125 + + io_left.outpad[1] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - l4.S12 - mux_115 mux_118 mux_121 mux_124 + + io_left.outpad[2] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - l8.W0 - mux_0 mux_5 mux_10 + + io_left.outpad[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - l8.E0 - mux_32 mux_6 mux_9 + + io_left.outpad[4] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - l8.S0 - mux_48 mux_22 mux_27 mux_13 + + io_left.outpad[5] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - l8.W8 - mux_64 mux_7 mux_25 mux_30 + + io_left.outpad[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - l8.E8 - mux_1 mux_4 mux_42 + + io_left.outpad[7] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - l8.S8 - mux_17 mux_20 mux_43 mux_46 + + io_left.outpad[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - l1.W9 - OG_1ST_1 OG_1ST_5 OG_1ST_9 + + io_left.outpad[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - l1.E9 - OG_1ST_3 OG_1ST_7 OG_1ST_11 + + io_left.outpad[2] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - l1.S9 - OG_1ST_0 OG_1ST_4 OG_1ST_8 + + io_left.outpad[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - l1.W10 - OG_1ST_2 OG_1ST_6 OG_1ST_10 + + io_left.outpad[4] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - l1.E10 - OG_1ST_0 OG_1ST_4 OG_1ST_8 + + io_left.outpad[5] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - l1.S10 - OG_1ST_1 OG_1ST_5 OG_1ST_9 + + io_left.outpad[6] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - l1.W11 - OG_1ST_3 OG_1ST_7 OG_1ST_11 + + io_left.outpad[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - l1.E11 - OG_1ST_1 OG_1ST_5 OG_1ST_9 + + io_left.outpad[0] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - l1.S11 - OG_1ST_2 OG_1ST_6 OG_1ST_10 + + io_left.outpad[1] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - l1.W12 - OG_1ST_0 OG_1ST_4 OG_1ST_8 + + io_left.outpad[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - l1.E12 - OG_1ST_2 OG_1ST_6 OG_1ST_10 + + io_left.outpad[3] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - l1.S12 - OG_1ST_3 OG_1ST_7 OG_1ST_11 + + io_left.outpad[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - io_top_ramL.f2a_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + io_left.outpad[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - io_top_ramL.f2a_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + io_left.outpad[6] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - io_top_ramL.f2a_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_left.outpad[7] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - io_top_ramL.f2a_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_left.outpad[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - io_top_ramL.f2a_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + io_left.outpad[1] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - io_top_ramL.f2a_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + io_left.outpad[2] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - io_top_ramL.f2a_i[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + io_left.outpad[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - io_top_ramL.f2a_i[0] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + io_left.outpad[4] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - io_top_ramL.f2a_i[1] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + io_left.outpad[5] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - io_top_ramL.f2a_i[2] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + io_left.outpad[6] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - io_top_ramL.f2a_i[3] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + io_left.outpad[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - io_top_ramL.f2a_i[4] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + io_left.outpad[0] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - io_top_ramL.f2a_i[5] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + io_left.outpad[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - io_top_ramL.f2a_i[6] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + io_left.outpad[2] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - io_top_ramL.f2a_i[0] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + io_left.outpad[3] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - io_top_ramL.f2a_i[1] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + io_left.outpad[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - io_top_ramL.f2a_i[2] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + io_left.outpad[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - io_top_ramL.f2a_i[3] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + io_left.outpad[6] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - io_top_ramL.f2a_i[4] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + io_left.outpad[7] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - io_top_ramL.f2a_i[5] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + io_left.outpad[0] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - io_top_ramL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + io_left.outpad[1] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - io_top_ramL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + io_left.outpad[2] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - io_top_ramL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + io_left.outpad[3] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - io_top_ramL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_left.outpad[4] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - io_top_ramL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + io_left.outpad[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - io_top_ramL.f2a_i[4] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + io_left.outpad[6] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - io_top_ramL.f2a_i[5] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + io_left.outpad[7] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - io_top_ramL.f2a_i[6] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - - io_top_ramL.f2a_i[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - - io_top_ramL.f2a_i[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - - io_top_ramL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - - io_top_ramL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - - io_top_ramL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - - io_top_ramL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - - io_top_ramL.f2a_i[6] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - - io_top_ramL.f2a_i[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - - io_top_ramL.f2a_i[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - - io_top_ramL.f2a_i[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - - io_top_ramL.f2a_i[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - - io_top_ramL.f2a_i[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - - io_top_ramL.f2a_i[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - - io_top_ramL.f2a_i[6] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - - io_top_ramL.f2a_i[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - - io_top_ramL.f2a_i[1] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - - io_top_ramL.f2a_i[2] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - - io_top_ramL.f2a_i[3] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - - io_top_ramL.f2a_i[4] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - - io_top_ramL.f2a_i[5] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - - io_top_ramL.f2a_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - - io_top_ramL.f2a_i[0] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - - io_top_ramL.f2a_i[1] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - - io_top_ramL.f2a_i[2] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - - io_top_ramL.f2a_i[3] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - - io_top_ramL.f2a_i[4] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - - io_top_ramL.f2a_i[5] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - - io_top_ramL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - - io_top_ramL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - - io_top_ramL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - - io_top_ramL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - - io_top_ramL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - - io_top_ramL.lclk[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - - io_top_ramL.lreset[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - - io_top_ramL.lclk[7] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - - io_top_ramL.lreset[7] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - - io_top_ramL.lclk[14] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - - io_top_ramL.lreset[14] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - - io_top_ramL.lclk[21] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - - io_top_ramL.lreset[21] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - - io_top_ramL.lclk[28] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - - io_top_ramL.lreset[28] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - - io_top_ramL.lclk[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - - io_top_ramL.lreset[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - - io_top_ramL.lclk[8] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - - io_top_ramL.lreset[8] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - - io_top_ramL.lclk[15] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - - io_top_ramL.lreset[15] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - - io_top_ramL.lclk[22] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - - io_top_ramL.lreset[22] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - - io_top_ramL.lclk[29] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + + + + + + + + + + + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] - - io_top_ramL.lreset[29] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] - - io_top_ramL.lclk[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] - - io_top_ramL.lreset[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] - - io_top_ramL.lclk[9] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] - - io_top_ramL.lreset[9] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] - - io_top_ramL.lclk[16] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] - - io_top_ramL.lreset[16] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] - - io_top_ramL.lclk[23] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] - - io_top_ramL.lreset[23] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] - - io_top_ramL.lclk[30] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] - - io_top_ramL.lreset[30] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] - - io_top_ramL.lclk[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] - - io_top_ramL.lreset[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] - - io_top_ramL.lclk[10] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] - - io_top_ramL.lreset[10] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] - - io_top_ramL.lclk[17] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 io_right.inpad[0] - - io_top_ramL.lreset[17] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 io_right.inpad[1] - - io_top_ramL.lclk[24] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 io_right.inpad[2] - - io_top_ramL.lreset[24] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.inpad[3] - - io_top_ramL.lclk[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.N1 l6.N1 l6.N18 l8.N11 io_right.inpad[4] - - io_top_ramL.lreset[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.E1 l6.E1 l6.E18 l8.E11 io_right.inpad[5] - - io_top_ramL.lclk[11] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.S1 l6.S1 l6.S18 l8.S11 io_right.inpad[6] - - io_top_ramL.lreset[11] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + io_right.inpad[7] - - io_top_ramL.lclk[18] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.N2 l6.N2 l6.N19 l8.N12 io_right.inpad[0] - - io_top_ramL.lreset[18] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.E2 l6.E2 l6.E19 l8.E12 io_right.inpad[1] - - io_top_ramL.lclk[25] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.S2 l6.S2 l6.S19 l8.S12 io_right.inpad[2] - - io_top_ramL.lreset[25] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + io_right.inpad[3] - - io_top_ramL.lclk[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.N3 l6.N3 l6.N20 l8.N13 io_right.inpad[4] - - io_top_ramL.lreset[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.E3 l6.E3 l6.E20 l8.E13 io_right.inpad[5] - - io_top_ramL.lclk[12] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.S3 l6.S3 l6.S20 l8.S13 io_right.inpad[6] - - io_top_ramL.lreset[12] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + io_right.inpad[7] - - io_top_ramL.lclk[19] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - - io_top_ramL.lreset[19] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - - io_top_ramL.lclk[26] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - - io_top_ramL.lreset[26] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + omux-3 - - io_top_ramL.lclk[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - - io_top_ramL.lreset[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - - io_top_ramL.lclk[13] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - - io_top_ramL.lreset[13] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + omux-7 - - io_top_ramL.lclk[20] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - - io_top_ramL.lreset[20] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - - io_top_ramL.lclk[27] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - - io_top_ramL.lreset[27] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + omux-11 - - io_top_ramL.lclk[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - - io_top_ramL.lreset[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - - io_top_ramL.lclk[14] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - - io_top_ramL.lreset[14] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + omux-15 - - io_top_ramL.lclk[21] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.N3 l6.N8 l8.N1 l12.N2 io_right.inpad[0] - - io_top_ramL.lreset[21] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.E3 l6.E8 l8.E1 l12.E2 io_right.inpad[1] - - io_top_ramL.lclk[28] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l2.S3 l6.S8 l8.S1 l12.S2 io_right.inpad[2] - - io_top_ramL.lreset[28] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + io_right.inpad[3] - - io_top_ramL.lclk[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.N4 l6.N9 l8.N2 l12.N3 io_right.inpad[4] - - io_top_ramL.lreset[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.E4 l6.E9 l8.E2 l12.E3 io_right.inpad[5] - - io_top_ramL.lclk[15] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.S4 l6.S9 l8.S2 l12.S3 io_right.inpad[6] - - io_top_ramL.lreset[15] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + io_right.inpad[7] - - io_top_ramL.lclk[22] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.N5 l6.N10 l8.N3 l12.N4 io_right.inpad[0] - - io_top_ramL.lreset[22] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.E5 l6.E10 l8.E3 l12.E4 io_right.inpad[1] - - io_top_ramL.lclk[29] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l2.S5 l6.S10 l8.S3 l12.S4 io_right.inpad[2] - - io_top_ramL.lreset[29] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + io_right.inpad[3] - - io_top_ramL.lclk[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.N0 l6.N11 l8.N4 l12.N5 io_right.inpad[4] - - io_top_ramL.lreset[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.E0 l6.E11 l8.E4 l12.E5 io_right.inpad[5] - - io_top_ramL.lclk[16] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.S0 l6.S11 l8.S4 l12.S5 io_right.inpad[6] - - io_top_ramL.lreset[16] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + io_right.inpad[7] - - io_top_ramL.lclk[23] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - - io_top_ramL.lreset[23] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - - io_top_ramL.lclk[30] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - - io_top_ramL.lreset[30] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + omux-3 - - io_top_ramL.lclk[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - - io_top_ramL.lreset[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - - io_top_ramL.lclk[17] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - - io_top_ramL.lreset[17] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + omux-7 - - io_top_ramL.lclk[24] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - - io_top_ramL.lreset[24] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - - io_top_ramL.lclk[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - - io_top_ramL.lreset[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + omux-11 - - io_top_ramL.lclk[18] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - io_top_ramL.lreset[18] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - io_top_ramL.lclk[25] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - io_top_ramL.lreset[25] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + omux-15 - - io_top_ramL.lclk[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.N5 l6.N16 l8.N9 l12.N10 io_right.inpad[0] - - io_top_ramL.lreset[12] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.E5 l6.E16 l8.E9 l12.E10 io_right.inpad[1] - - io_top_ramL.lclk[19] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.S5 l6.S16 l8.S9 l12.S10 io_right.inpad[2] - - io_top_ramL.lreset[19] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + io_right.inpad[3] - - io_top_ramL.lclk[26] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l1.N0 l3.N0 l6.N5 l6.N16 io_right.inpad[0] - - io_top_ramL.lreset[26] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l1.E0 l3.E0 l6.E5 l6.E16 io_right.inpad[1] - - io_top_ramL.lclk[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.S0 l3.S0 l6.S5 l6.S16 io_right.inpad[2] - - io_top_ramL.lreset[13] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + io_right.inpad[3] - - io_top_ramL.lclk[20] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.N1 l3.N1 l6.N6 l6.N17 io_right.inpad[4] - - io_top_ramL.lreset[20] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.E1 l3.E1 l6.E6 l6.E17 io_right.inpad[5] - - io_top_ramL.lclk[27] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.S1 l3.S1 l6.S6 l6.S17 io_right.inpad[6] - - io_top_ramL.lreset[27] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + io_right.inpad[7] - - io_top_ramL.lclk[14] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.N2 l3.N2 l6.N7 l6.N18 io_right.inpad[0] - - io_top_ramL.lreset[14] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.E2 l3.E2 l6.E7 l6.E18 io_right.inpad[1] - - io_top_ramL.lclk[21] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.S2 l3.S2 l6.S7 l6.S18 io_right.inpad[2] - - io_top_ramL.lreset[21] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + io_right.inpad[3] - - io_top_ramL.lclk[28] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.N3 l3.N3 l6.N8 l6.N19 io_right.inpad[4] - - io_top_ramL.lreset[28] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l1.E3 l3.E3 l6.E8 l6.E19 io_right.inpad[5] - - io_top_ramL.lclk[15] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.S3 l3.S3 l6.S8 l6.S19 io_right.inpad[6] - - io_top_ramL.lreset[15] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + io_right.inpad[7] - - io_top_ramL.lclk[22] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - io_top_ramL.lreset[22] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - io_top_ramL.lclk[29] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - io_top_ramL.lreset[29] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + omux-3 - - io_top_ramL.lclk[16] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + + + io_right.outpad[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - io_top_ramL.lreset[16] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + io_right.outpad[1] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - io_top_ramL.lclk[23] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + io_right.outpad[2] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - io_top_ramL.lreset[23] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + io_right.outpad[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - io_top_ramL.lclk[30] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + io_right.outpad[4] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - io_top_ramL.lreset[30] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + io_right.outpad[5] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - io_top_ramL.lclk[17] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + io_right.outpad[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - io_top_ramL.lreset[17] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + io_right.outpad[7] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - io_top_ramL.lclk[24] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + io_right.outpad[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - io_top_ramL.lreset[24] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + io_right.outpad[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - io_top_ramL.lclk[18] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + io_right.outpad[2] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - io_top_ramL.lreset[18] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + io_right.outpad[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - io_top_ramL.lclk[25] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + io_right.outpad[4] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - io_top_ramL.lreset[25] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + io_right.outpad[5] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - io_top_ramL.lclk[19] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + io_right.outpad[6] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - io_top_ramL.lreset[19] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + io_right.outpad[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - io_top_ramL.lclk[26] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + io_right.outpad[0] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - io_top_ramL.lreset[26] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + io_right.outpad[1] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - io_top_ramL.lclk[20] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + io_right.outpad[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - io_top_ramL.lreset[20] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + io_right.outpad[3] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - io_top_ramL.lclk[27] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + io_right.outpad[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - io_top_ramL.lreset[27] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + io_right.outpad[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - io_top_ramL.lclk[21] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + io_right.outpad[6] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - io_top_ramL.lreset[21] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + io_right.outpad[7] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - io_top_ramL.lclk[28] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + io_right.outpad[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - io_top_ramL.lreset[28] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + io_right.outpad[1] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - io_top_ramL.lclk[22] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + io_right.outpad[2] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - io_top_ramL.lreset[22] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + io_right.outpad[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - io_top_ramL.lclk[29] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + io_right.outpad[4] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - io_top_ramL.lreset[29] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + io_right.outpad[5] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - io_top_ramL.lclk[23] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.outpad[6] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - io_top_ramL.lreset[23] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.outpad[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - io_top_ramL.lclk[30] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.outpad[0] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - io_top_ramL.lreset[30] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_right.outpad[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - io_top_ramL.lclk[24] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + io_right.outpad[2] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - io_top_ramL.lreset[24] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + io_right.outpad[3] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - io_top_ramL.lclk[25] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + io_right.outpad[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - io_top_ramL.lreset[25] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + io_right.outpad[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - io_top_ramL.lclk[26] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + io_right.outpad[6] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - io_top_ramL.lreset[26] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + io_right.outpad[7] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - io_top_ramL.lclk[27] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + io_right.outpad[0] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - io_top_ramL.lreset[27] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + io_right.outpad[1] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - io_top_ramL.lclk[28] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + io_right.outpad[2] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - io_top_ramL.lreset[28] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + io_right.outpad[3] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - io_top_ramL.lclk[29] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + io_right.outpad[4] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - io_top_ramL.lreset[29] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + io_right.outpad[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - io_top_ramL.lclk[30] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + io_right.outpad[6] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - io_top_ramL.lreset[30] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + io_right.outpad[7] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 io_bottomL.a2f_o[0] + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - l1.W2 l2.W1 l4.W3 io_bottomL.a2f_o[0] + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - l1.W3 l3.W5 l8.W7 io_bottomL.a2f_o[0] + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - l1.W4 l3.W8 l8.W15 + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - io_bottomL.a2f_o[1] + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - io_bottomL.a2f_o[1] + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - io_bottomL.a2f_o[1] + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - l1.E10 l1.E11 l3.E20 io_bottomL.a2f_o[2] + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - l1.E12 l2.E5 l4.E11 io_bottomL.a2f_o[2] + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - l1.E0 l3.E23 l8.E7 io_bottomL.a2f_o[2] + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - l1.E1 l3.E2 l8.E15 + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - l1.S2 l1.S3 l3.S5 io_bottomL.a2f_o[3] + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - l1.S4 l2.S1 l4.S15 io_bottomL.a2f_o[3] + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - l1.S5 l3.S8 l8.S7 io_bottomL.a2f_o[3] + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - l1.S6 l3.S11 l8.S15 + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - l1.W7 l1.W8 l3.W14 io_bottomL.a2f_o[0] - - - l1.W9 l2.W3 l4.W3 io_bottomL.a2f_o[0] - - - l1.W10 l3.W17 l8.W7 io_bottomL.a2f_o[0] - - - l1.W11 l3.W20 l8.W15 - - - io_bottomL.a2f_o[1] - - - io_bottomL.a2f_o[1] - - - io_bottomL.a2f_o[1] - - - l1.E4 l1.E5 l3.E8 io_bottomL.a2f_o[2] - - - l1.E6 l2.E1 l4.E11 io_bottomL.a2f_o[2] - - - l1.E7 l3.E11 l8.E7 io_bottomL.a2f_o[2] - - - l1.E8 l3.E14 l8.E15 - - - l1.S9 l1.S10 l3.S17 io_bottomL.a2f_o[3] - - - l1.S11 l2.S3 l4.S15 io_bottomL.a2f_o[3] - - - l1.S12 l3.S20 l8.S7 io_bottomL.a2f_o[3] - - - l1.S0 l3.S23 l8.S15 - - - l1.W1 l1.W2 l3.W2 io_bottomL.a2f_o[0] - - - l1.W3 l2.W5 l4.W3 io_bottomL.a2f_o[0] + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - l1.W4 l3.W5 l8.W7 io_bottomL.a2f_o[0] + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - l1.W5 l3.W8 l8.W15 + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - io_bottomL.a2f_o[1] + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - io_bottomL.a2f_o[1] + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - io_bottomL.a2f_o[1] + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - l1.E11 l1.E12 l3.E20 io_bottomL.a2f_o[2] + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - l1.E0 l2.E3 l4.E11 io_bottomL.a2f_o[2] + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - l1.E1 l3.E23 l8.E7 io_bottomL.a2f_o[2] + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - l1.E2 l3.E2 l8.E15 + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - l1.S3 l1.S4 l3.S5 io_bottomL.a2f_o[3] + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - l1.S5 l2.S5 l4.S15 io_bottomL.a2f_o[3] + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - l1.S6 l3.S8 l8.S7 io_bottomL.a2f_o[3] + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - l1.S7 l3.S11 l8.S15 + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - l1.W8 l1.W9 l3.W14 io_bottomL.a2f_o[0] + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - l1.W10 l2.W1 l4.W3 io_bottomL.a2f_o[0] + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - l1.W11 l3.W17 l8.W7 io_bottomL.a2f_o[0] + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - l1.W12 l3.W20 l8.W15 + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - io_bottomL.a2f_o[1] + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - io_bottomL.a2f_o[1] + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - io_bottomL.a2f_o[1] + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - l1.E5 l1.E6 l3.E8 io_bottomL.a2f_o[2] + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - l1.E7 l2.E5 l4.E11 io_bottomL.a2f_o[2] + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - l1.E8 l3.E11 l8.E7 io_bottomL.a2f_o[2] + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - l1.E9 l3.E14 l8.E15 + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - l1.S10 l1.S11 l3.S17 io_bottomL.a2f_o[3] + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - l1.S12 l2.S1 l4.S15 io_bottomL.a2f_o[3] - - - l1.S0 l3.S20 l8.S7 io_bottomL.a2f_o[3] - - - l1.S1 l3.S23 l8.S15 - - - l1.W2 l1.W3 l3.W2 io_bottomL.a2f_o[0] - - - l1.W4 l2.W3 l4.W3 io_bottomL.a2f_o[0] - - - l1.W5 l3.W5 l8.W7 io_bottomL.a2f_o[0] - - - l1.W6 l3.W8 l8.W15 - - - io_bottomL.a2f_o[1] - - - io_bottomL.a2f_o[1] - - - io_bottomL.a2f_o[1] - - - l1.E12 l1.E0 l3.E20 io_bottomL.a2f_o[2] - - - l1.E1 l2.E1 l4.E11 io_bottomL.a2f_o[2] - - - l1.E2 l3.E23 l8.E7 io_bottomL.a2f_o[2] - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 io_bottomL.a2f_o[3] - - - l1.S6 l2.S3 l4.S15 io_bottomL.a2f_o[3] - - - l1.S7 l3.S8 l8.S7 io_bottomL.a2f_o[3] - - - l1.S8 l3.S11 l8.S15 - - - l1.W9 l1.W10 l3.W14 io_bottomL.a2f_o[0] - - - l1.W11 l2.W5 l4.W3 io_bottomL.a2f_o[0] - - - l1.W12 l3.W17 l8.W7 io_bottomL.a2f_o[0] - - - l1.W0 l3.W20 l8.W15 - - - io_bottomL.a2f_o[1] - - - io_bottomL.a2f_o[1] - - - io_bottomL.a2f_o[1] - - - l1.E6 l1.E7 l3.E8 io_bottomL.a2f_o[2] - - - l1.E8 l2.E3 l4.E11 io_bottomL.a2f_o[2] - - - l1.E9 l3.E11 l8.E7 io_bottomL.a2f_o[2] - - - l1.E10 l3.E14 l8.E15 - - - l1.S11 l1.S12 l3.S17 io_bottomL.a2f_o[3] - - - l1.S0 l2.S5 l4.S15 io_bottomL.a2f_o[3] - - - l1.S1 l3.S20 l8.S7 io_bottomL.a2f_o[3] - - - l1.S2 l3.S23 l8.S15 - - - l1.W3 l1.W4 l3.W2 io_bottomL.a2f_o[0] - - - l1.W5 l2.W1 l4.W3 io_bottomL.a2f_o[0] - - - l1.W6 l3.W5 l8.W7 io_bottomL.a2f_o[0] - - - l1.W7 l3.W8 l8.W15 - - - io_bottomL.a2f_o[1] - - - io_bottomL.a2f_o[1] - - - io_bottomL.a2f_o[1] - - - l1.E0 l1.E1 l3.E20 io_bottomL.a2f_o[2] + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - l1.E2 l2.E5 l4.E11 io_bottomL.a2f_o[2] + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - - l1.E3 l3.E23 l8.E7 io_bottomL.a2f_o[2] + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - - l1.E4 l3.E2 l8.E15 + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - - l1.S5 l1.S6 l3.S5 io_bottomL.a2f_o[3] + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - - l1.S7 l2.S1 l4.S15 io_bottomL.a2f_o[3] + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - - l1.S8 l3.S8 l8.S7 io_bottomL.a2f_o[3] + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.S9 l3.S11 l8.S15 + + + + + + + + + + + + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] - - l1.W10 l1.W11 l3.W14 io_bottomL.a2f_o[0] + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] - - l1.W12 l2.W3 l4.W3 io_bottomL.a2f_o[0] + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] - - l1.W0 l3.W17 l8.W7 io_bottomL.a2f_o[0] + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] - - l1.W1 l3.W20 l8.W15 + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] - - io_bottomL.a2f_o[1] + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] - - io_bottomL.a2f_o[1] + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] - - io_bottomL.a2f_o[1] + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] - - l1.E7 l1.E8 l3.E8 io_bottomL.a2f_o[2] + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] - - l1.E9 l2.E1 l4.E11 io_bottomL.a2f_o[2] + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] - - l1.E10 l3.E11 l8.E7 io_bottomL.a2f_o[2] + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] - - l1.E11 l3.E14 l8.E15 + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] - - l1.S12 l1.S0 l3.S17 io_bottomL.a2f_o[3] + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] - - l1.S1 l2.S3 l4.S15 io_bottomL.a2f_o[3] + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] - - l1.S2 l3.S20 l8.S7 io_bottomL.a2f_o[3] + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] - - l1.S3 l3.S23 l8.S15 + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_bottomL.a2f_o[0] OG_0 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 io_top.inpad[0] - l1.E12 l1.E11 l2.E5 l3.E23 l4.E15 io_bottomL.a2f_o[0] + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 io_top.inpad[1] - l1.E5 l1.S11 l3.E8 l3.S17 l4.E3 io_bottomL.a2f_o[0] + io_top.inpad[2] - l1.W11 l1.S10 l3.W20 l4.W11 io_bottomL.a2f_o[1] + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 io_top.inpad[3] - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 io_bottomL.a2f_o[1] + l1.N1 l6.N1 l6.N18 l8.N11 io_top.inpad[4] - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 io_bottomL.a2f_o[1] OG_2 + l1.E1 l6.E1 l6.E18 l8.E11 io_top.inpad[5] - l1.W3 l2.W3 l3.W2 io_bottomL.a2f_o[2] OG_2 l1.S4 + io_top.inpad[6] - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 io_bottomL.a2f_o[2] OG_3 + l1.W1 l6.W1 l6.W18 l8.W11 io_top.inpad[7] - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_bottomL.a2f_o[2] OG_4 + l1.N2 l6.N2 l6.N19 l8.N12 io_top.inpad[0] - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 io_bottomL.a2f_o[3] + l1.E2 l6.E2 l6.E19 l8.E12 io_top.inpad[1] - l1.W1 l3.W20 l4.W7 io_bottomL.a2f_o[3] + io_top.inpad[2] - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 io_bottomL.a2f_o[3] + l1.W2 l6.W2 l6.W19 l8.W12 io_top.inpad[3] - l1.W0 l1.E12 l3.W17 l4.W3 io_bottomL.a2f_o[0] + l1.N3 l6.N3 l6.N20 l8.N13 io_top.inpad[4] - l1.E6 l2.E5 l3.E5 io_bottomL.a2f_o[0] OG_6 l1.E5 + l1.E3 l6.E3 l6.E20 l8.E13 io_top.inpad[5] - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 io_bottomL.a2f_o[0] OG_6 l1.S4 + io_top.inpad[6] - l1.W5 l2.W3 l3.W2 l4.W11 io_bottomL.a2f_o[1] OG_7 + l1.W3 l6.W3 l6.W20 l8.W13 io_top.inpad[7] - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_bottomL.a2f_o[1] OG_0 + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - l1.W4 l1.E3 l2.W1 l3.W23 l4.W7 io_bottomL.a2f_o[1] + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - l1.E10 l3.E8 l4.E11 io_bottomL.a2f_o[2] + omux-2 - l1.E3 l1.S2 l3.E20 l4.E3 io_bottomL.a2f_o[2] + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - l1.E9 l1.E8 l3.E5 l4.E7 io_bottomL.a2f_o[2] + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 io_bottomL.a2f_o[3] OG_2 l1.E0 + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 io_bottomL.a2f_o[3] OG_2 + omux-6 - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 io_bottomL.a2f_o[3] OG_3 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_bottomL.a2f_o[0] OG_4 + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 io_bottomL.a2f_o[0] + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - l1.W6 l1.S12 l3.W20 l3.S5 l4.W15 io_bottomL.a2f_o[0] + omux-10 - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 io_bottomL.a2f_o[1] + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 io_bottomL.a2f_o[1] + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - l1.W11 l2.W1 l3.W5 io_bottomL.a2f_o[1] OG_6 l1.W6 + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - l1.E4 l2.E3 l3.E14 io_bottomL.a2f_o[2] OG_6 l1.S8 + omux-14 - l1.E10 l2.E5 l3.E2 l4.E3 io_bottomL.a2f_o[2] OG_7 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_bottomL.a2f_o[2] OG_0 + l2.N3 l6.N8 l8.N1 l12.N2 io_top.inpad[0] - l1.E9 l1.E8 l2.E3 l3.E23 l4.E15 io_bottomL.a2f_o[3] + l2.E3 l6.E8 l8.E1 l12.E2 io_top.inpad[1] - l1.E2 l1.S8 l3.E8 l3.S17 l4.E3 io_bottomL.a2f_o[3] + io_top.inpad[2] - l1.W8 l1.S7 l3.W20 l4.W11 io_bottomL.a2f_o[3] + l2.W3 l6.W8 l8.W1 l12.W2 io_top.inpad[3] - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 io_bottomL.a2f_o[0] + l2.N4 l6.N9 l8.N2 l12.N3 io_top.inpad[4] - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 io_bottomL.a2f_o[0] OG_2 l1.S6 + l2.E4 l6.E9 l8.E2 l12.E3 io_top.inpad[5] - l1.W0 l2.W1 l3.W2 io_bottomL.a2f_o[0] OG_2 l1.E0 + io_top.inpad[6] - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 io_bottomL.a2f_o[1] OG_3 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 io_top.inpad[7] - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_bottomL.a2f_o[1] OG_4 + l2.N5 l6.N10 l8.N3 l12.N4 io_top.inpad[0] - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 io_bottomL.a2f_o[1] + l2.E5 l6.E10 l8.E3 l12.E4 io_top.inpad[1] - l1.W11 l3.W20 l4.W7 io_bottomL.a2f_o[2] + io_top.inpad[2] - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 io_bottomL.a2f_o[2] + l2.W5 l6.W10 l8.W3 l12.W4 io_top.inpad[3] - l1.W10 l1.E9 l3.W17 l4.W3 io_bottomL.a2f_o[2] + l3.N0 l6.N11 l8.N4 l12.N5 io_top.inpad[4] - l1.E3 l2.E3 l3.E5 io_bottomL.a2f_o[3] OG_6 l1.E2 + l3.E0 l6.E11 l8.E4 l12.E5 io_top.inpad[5] - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 io_bottomL.a2f_o[3] OG_6 l1.W3 + io_top.inpad[6] - l1.W2 l2.W1 l3.W2 l4.W11 io_bottomL.a2f_o[3] OG_7 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 io_top.inpad[7] - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_bottomL.a2f_o[0] OG_0 + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - l1.W1 l1.E0 l2.W5 l3.W23 l4.W7 io_bottomL.a2f_o[0] + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - l1.E7 l3.E8 l4.E11 io_bottomL.a2f_o[0] + omux-2 - l1.E0 l1.S12 l3.E20 l4.E3 io_bottomL.a2f_o[1] + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - l1.E6 l1.E5 l3.E5 l4.E7 io_bottomL.a2f_o[1] + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 io_bottomL.a2f_o[1] OG_2 l1.W12 + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 io_bottomL.a2f_o[2] OG_2 l1.W4 + omux-6 - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 io_bottomL.a2f_o[2] OG_3 + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_bottomL.a2f_o[2] OG_4 + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 io_bottomL.a2f_o[3] + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - l1.W3 l1.S9 l3.W20 l3.S5 l4.W15 io_bottomL.a2f_o[3] + omux-10 - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 io_bottomL.a2f_o[3] + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] + + omux-14 - - io_bottomL.a2f_o[0] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[1] + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] + + l3.N5 l6.N16 l8.N9 l12.N10 io_top.inpad[0] - - io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] + + l3.E5 l6.E16 l8.E9 l12.E10 io_top.inpad[1] - - io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] + + io_top.inpad[2] - - io_bottomL.a2f_o[2] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[3] + + l3.W5 l6.W16 l8.W9 l12.W10 io_top.inpad[3] - - io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] + + l1.N0 l3.N0 l6.N5 l6.N16 io_top.inpad[0] - - io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] + + l1.E0 l3.E0 l6.E5 l6.E16 io_top.inpad[1] - - io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] + + io_top.inpad[2] - - io_bottomL.a2f_o[0] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[1] + + l1.W0 l3.W0 l6.W5 l6.W16 io_top.inpad[3] - - io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] io_bottomL.a2f_o[0] io_bottomL.a2f_o[1] + + l1.N1 l3.N1 l6.N6 l6.N17 io_top.inpad[4] - - io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] + + l1.E1 l3.E1 l6.E6 l6.E17 io_top.inpad[5] - - io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] + + io_top.inpad[6] - - io_bottomL.a2f_o[2] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[3] + + l1.W1 l3.W1 l6.W6 l6.W17 io_top.inpad[7] - - io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] io_bottomL.a2f_o[2] io_bottomL.a2f_o[3] + + l1.N2 l3.N2 l6.N7 l6.N18 io_top.inpad[0] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.E2 l3.E2 l6.E7 l6.E18 io_top.inpad[1] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + io_top.inpad[2] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.W2 l3.W2 l6.W7 l6.W18 io_top.inpad[3] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.N3 l3.N3 l6.N8 l6.N19 io_top.inpad[4] - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.E3 l3.E3 l6.E8 l6.E19 io_top.inpad[5] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + io_top.inpad[6] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.W3 l3.W3 l6.W8 l6.W19 io_top.inpad[7] - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - l1.W0 - mux_0 mux_5 mux_10 mux_15 + + io_top.outpad[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - l1.N0 - mux_16 mux_21 mux_11 mux_14 + + io_top.outpad[1] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - l1.E0 - mux_32 mux_6 mux_9 mux_31 + + io_top.outpad[2] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - l1.W1 - mux_64 mux_25 mux_30 + + io_top.outpad[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - l1.N1 - mux_80 mux_26 mux_29 + + io_top.outpad[4] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - l1.E1 - mux_1 mux_4 mux_42 mux_47 + + io_top.outpad[5] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - l1.W2 - mux_33 mux_38 mux_8 mux_63 + + io_top.outpad[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - l1.N2 - mux_49 mux_54 mux_59 mux_12 + + io_top.outpad[7] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - l1.E2 - mux_65 mux_24 mux_62 + + io_top.outpad[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - l1.W3 - mux_2 mux_36 mux_41 mux_79 + + io_top.outpad[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - l1.N3 - mux_18 mux_52 mux_75 mux_45 + + io_top.outpad[2] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - l1.E3 - mux_34 mux_37 mux_40 mux_95 + + io_top.outpad[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - l1.W4 - mux_66 mux_56 mux_61 + + io_top.outpad[4] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - l1.N4 - mux_82 mux_57 mux_60 + + io_top.outpad[5] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - l1.E4 - mux_3 mux_68 mux_73 mux_78 + + io_top.outpad[6] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - l1.W5 - mux_35 mux_69 mux_72 mux_94 + + io_top.outpad[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - l1.N5 - mux_51 mux_85 mux_90 mux_76 + + io_top.outpad[0] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - l1.E5 - mux_67 mux_70 mux_88 mux_93 + + io_top.outpad[1] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - l1.W6 - mux_96 mux_101 mux_106 mux_111 + + io_top.outpad[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - l1.N6 - mux_112 mux_117 mux_107 mux_110 + + io_top.outpad[3] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - l1.E6 - mux_0 mux_102 mux_105 mux_127 + + io_top.outpad[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - l1.W7 - mux_32 mux_121 mux_126 + + io_top.outpad[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - l1.N7 - mux_48 mux_122 mux_125 + + io_top.outpad[6] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - l1.E7 - mux_97 mux_100 mux_10 mux_15 + + io_top.outpad[7] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - l1.W8 - mux_1 mux_6 mux_104 mux_31 + + io_top.outpad[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - l1.N8 - mux_17 mux_22 mux_27 mux_108 + + io_top.outpad[1] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - l1.E8 - mux_33 mux_120 mux_30 + + io_top.outpad[2] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - l2.W0 - mux_98 mux_4 mux_9 mux_47 + + io_top.outpad[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - l2.N0 - mux_114 mux_20 mux_43 mux_13 + + io_top.outpad[4] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - l2.E0 - mux_2 mux_5 mux_8 mux_63 + + io_top.outpad[5] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - l2.W2 - mux_34 mux_24 mux_29 + + io_top.outpad[6] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - l2.N2 - mux_50 mux_25 mux_28 + + io_top.outpad[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - l2.E2 - mux_99 mux_36 mux_41 mux_46 + + io_top.outpad[0] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - l2.W4 - mux_3 mux_37 mux_40 mux_62 + + io_top.outpad[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - l2.N4 - mux_19 mux_53 mux_58 mux_44 + + io_top.outpad[2] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - l2.E4 - mux_35 mux_38 mux_56 mux_61 + + io_top.outpad[3] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - l3.W0 - mux_64 mux_69 mux_74 mux_79 + + io_top.outpad[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - l3.N0 - mux_80 mux_85 mux_75 mux_78 + + io_top.outpad[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - l3.E0 - mux_96 mux_70 mux_73 mux_95 + + io_top.outpad[6] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - l3.W3 - mux_0 mux_89 mux_94 + + io_top.outpad[7] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - l3.N3 - mux_16 mux_90 mux_93 + + io_top.outpad[0] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - l3.E3 - mux_65 mux_68 mux_106 mux_111 + + io_top.outpad[1] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - l3.W6 - mux_97 mux_102 mux_72 mux_127 + + io_top.outpad[2] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - l3.N6 - mux_113 mux_118 mux_123 mux_76 + + io_top.outpad[3] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - l3.E6 - mux_1 mux_88 mux_126 + + io_top.outpad[4] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - l3.W9 - mux_66 mux_100 mux_105 mux_15 + + io_top.outpad[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - l3.N9 - mux_82 mux_116 mux_11 mux_109 + + io_top.outpad[6] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - l3.E9 - mux_98 mux_101 mux_104 mux_31 + + io_top.outpad[7] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - l3.W12 - mux_2 mux_120 mux_125 + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - - l3.N12 - mux_18 mux_121 mux_124 + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - - l3.E12 - mux_67 mux_4 mux_9 mux_14 + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - - l3.W15 - mux_99 mux_5 mux_8 mux_30 + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - - l3.N15 - mux_115 mux_21 mux_26 mux_12 + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - - l3.E15 - mux_3 mux_6 mux_24 mux_29 + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - - l3.W18 - mux_32 mux_37 mux_42 mux_47 + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - - l3.N18 - mux_48 mux_53 mux_43 mux_46 + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - - l3.E18 - mux_64 mux_38 mux_41 mux_63 + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - - l3.W21 - mux_96 mux_57 mux_62 + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - - l3.N21 - mux_112 mux_58 mux_61 + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - - l3.E21 - mux_33 mux_36 mux_74 mux_79 + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - - l4.W0 - mux_65 mux_70 mux_40 mux_95 + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - - l4.N0 - mux_81 mux_86 mux_91 mux_44 + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - - l4.E0 - mux_97 mux_56 mux_94 + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - - l4.W4 - mux_34 mux_68 mux_73 mux_111 + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - - l4.N4 - mux_50 mux_84 mux_107 mux_77 + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - - l4.E4 - mux_66 mux_69 mux_72 mux_127 + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - - l4.W8 - mux_98 mux_88 mux_93 + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - - l4.N8 - mux_114 mux_89 mux_92 + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - - l4.E8 - mux_35 mux_100 mux_105 mux_110 + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - - l4.N12 - mux_83 mux_117 mux_122 mux_108 + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - - l4.E12 - mux_99 mux_102 mux_120 mux_125 + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - - l8.W0 - mux_0 mux_5 mux_10 mux_15 + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - - l8.N0 - mux_16 mux_21 mux_11 mux_14 + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - - l8.E0 - mux_32 mux_6 mux_9 mux_31 + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - - l8.W8 - mux_64 mux_25 mux_30 + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - - l8.N8 - mux_80 mux_26 mux_29 + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - - l8.E8 - mux_1 mux_4 mux_42 mux_47 + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - - l1.W9 - l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - - l1.N9 - l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - - l1.E9 - l1.W9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - - l1.W10 - l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - - l1.N10 - l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - - l1.E10 - l1.W10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - - l1.W11 - l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - - l1.N11 - l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - - l1.E11 - l1.W11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - - l1.W12 - l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - - l1.N12 - l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - - l1.E12 - l1.W12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - - io_bottomL.f2a_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - - io_bottomL.f2a_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - - io_bottomL.f2a_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - io_bottomL.f2a_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - - io_bottomL.f2a_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - - io_bottomL.f2a_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - - io_bottomL.f2a_i[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - - io_bottomL.f2a_i[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - - io_bottomL.f2a_i[0] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - io_bottomL.f2a_i[1] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + + + + + + + + + + + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] - - io_bottomL.f2a_i[2] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] - - io_bottomL.f2a_i[3] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] - - io_bottomL.f2a_i[4] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] - - io_bottomL.f2a_i[5] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] - - io_bottomL.f2a_i[6] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] - - io_bottomL.f2a_i[7] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] - - io_bottomL.f2a_i[0] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] - - io_bottomL.f2a_i[1] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] - - io_bottomL.f2a_i[2] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] - - io_bottomL.f2a_i[3] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] - - io_bottomL.f2a_i[4] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] - - io_bottomL.f2a_i[5] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] - - io_bottomL.f2a_i[6] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] - - io_bottomL.f2a_i[7] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] - - io_bottomL.f2a_i[0] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] - - io_bottomL.f2a_i[1] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + io_bottom.inpad[0] - - io_bottomL.f2a_i[2] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 io_bottom.inpad[1] - - io_bottomL.f2a_i[3] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 io_bottom.inpad[2] - - io_bottomL.f2a_i[4] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 io_bottom.inpad[3] - - io_bottomL.f2a_i[5] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + io_bottom.inpad[4] - - io_bottomL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + l1.E1 l6.E1 l6.E18 l8.E11 io_bottom.inpad[5] - - io_bottomL.f2a_i[7] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + l1.S1 l6.S1 l6.S18 l8.S11 io_bottom.inpad[6] - - io_bottomL.f2a_i[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + l1.W1 l6.W1 l6.W18 l8.W11 io_bottom.inpad[7] - - io_bottomL.f2a_i[1] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 + + io_bottom.inpad[0] - - io_bottomL.f2a_i[2] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + l1.E2 l6.E2 l6.E19 l8.E12 io_bottom.inpad[1] - - io_bottomL.f2a_i[3] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + l1.S2 l6.S2 l6.S19 l8.S12 io_bottom.inpad[2] - - io_bottomL.f2a_i[4] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + l1.W2 l6.W2 l6.W19 l8.W12 io_bottom.inpad[3] - - io_bottomL.f2a_i[5] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 + + io_bottom.inpad[4] - - io_bottomL.f2a_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + l1.E3 l6.E3 l6.E20 l8.E13 io_bottom.inpad[5] - - io_bottomL.f2a_i[7] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + l1.S3 l6.S3 l6.S20 l8.S13 io_bottom.inpad[6] - - io_bottomL.f2a_i[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + l1.W3 l6.W3 l6.W20 l8.W13 io_bottom.inpad[7] - - io_bottomL.f2a_i[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 + + omux-0 - - io_bottomL.f2a_i[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - - io_bottomL.f2a_i[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - - io_bottomL.f2a_i[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - - io_bottomL.f2a_i[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 + + omux-4 - - io_bottomL.f2a_i[6] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - - io_bottomL.f2a_i[7] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - - io_bottomL.f2a_i[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - - io_bottomL.f2a_i[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 + + omux-8 - - io_bottomL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - - io_bottomL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - - io_bottomL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - - io_bottomL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 + + omux-12 - - io_bottomL.f2a_i[6] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - - io_bottomL.f2a_i[7] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - - io_bottomL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - - io_bottomL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 + + io_bottom.inpad[0] - - io_bottomL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + l2.E3 l6.E8 l8.E1 l12.E2 io_bottom.inpad[1] - - io_bottomL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + l2.S3 l6.S8 l8.S1 l12.S2 io_bottom.inpad[2] - - io_bottomL.lclk[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l2.W3 l6.W8 l8.W1 l12.W2 io_bottom.inpad[3] - - io_bottomL.lreset[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + io_bottom.inpad[4] - - io_bottomL.lclk[8] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l2.E4 l6.E9 l8.E2 l12.E3 io_bottom.inpad[5] - - io_bottomL.lreset[8] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l2.S4 l6.S9 l8.S2 l12.S3 io_bottom.inpad[6] - - io_bottomL.lclk[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l2.W4 l6.W9 l8.W2 l12.W3 io_bottom.inpad[7] - - io_bottomL.lreset[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + io_bottom.inpad[0] - - io_bottomL.lclk[9] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l2.E5 l6.E10 l8.E3 l12.E4 io_bottom.inpad[1] - - io_bottomL.lreset[9] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l2.S5 l6.S10 l8.S3 l12.S4 io_bottom.inpad[2] - - io_bottomL.lclk[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + l2.W5 l6.W10 l8.W3 l12.W4 io_bottom.inpad[3] - - io_bottomL.lreset[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + io_bottom.inpad[4] - - io_bottomL.lclk[10] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + l3.E0 l6.E11 l8.E4 l12.E5 io_bottom.inpad[5] - - io_bottomL.lreset[10] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + l3.S0 l6.S11 l8.S4 l12.S5 io_bottom.inpad[6] - - io_bottomL.lclk[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + l3.W0 l6.W11 l8.W4 l12.W5 io_bottom.inpad[7] - - io_bottomL.lreset[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + omux-0 - - io_bottomL.lclk[11] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - - io_bottomL.lreset[11] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - - io_bottomL.lclk[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - - io_bottomL.lreset[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + omux-4 - - io_bottomL.lclk[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - - io_bottomL.lreset[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - - io_bottomL.lclk[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - - io_bottomL.lreset[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + omux-8 - - io_bottomL.lclk[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - - io_bottomL.lreset[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - - io_bottomL.lclk[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - io_bottomL.lreset[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + omux-12 - - io_bottomL.lclk[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - io_bottomL.lreset[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - io_bottomL.lclk[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - io_bottomL.lreset[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + io_bottom.inpad[0] - - io_bottomL.lclk[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + l3.E5 l6.E16 l8.E9 l12.E10 io_bottom.inpad[1] - - io_bottomL.lreset[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + l3.S5 l6.S16 l8.S9 l12.S10 io_bottom.inpad[2] - - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 io_bottom_dspL.a2f_o[0] + + l3.W5 l6.W16 l8.W9 l12.W10 io_bottom.inpad[3] - - l1.W2 l2.W1 l4.W3 io_bottom_dspL.a2f_o[0] + + io_bottom.inpad[0] - - l1.W3 l3.W5 l8.W7 io_bottom_dspL.a2f_o[0] + + l1.E0 l3.E0 l6.E5 l6.E16 io_bottom.inpad[1] - - l1.W4 l3.W8 l8.W15 + + l1.S0 l3.S0 l6.S5 l6.S16 io_bottom.inpad[2] - - io_bottom_dspL.a2f_o[1] + + l1.W0 l3.W0 l6.W5 l6.W16 io_bottom.inpad[3] - - io_bottom_dspL.a2f_o[1] + + io_bottom.inpad[4] - - io_bottom_dspL.a2f_o[1] + + l1.E1 l3.E1 l6.E6 l6.E17 io_bottom.inpad[5] - - l1.E10 l1.E11 l3.E20 io_bottom_dspL.a2f_o[2] + + l1.S1 l3.S1 l6.S6 l6.S17 io_bottom.inpad[6] - - l1.E12 l2.E5 l4.E11 io_bottom_dspL.a2f_o[2] + + l1.W1 l3.W1 l6.W6 l6.W17 io_bottom.inpad[7] - - l1.E0 l3.E23 l8.E7 io_bottom_dspL.a2f_o[2] + + io_bottom.inpad[0] - - l1.E1 l3.E2 l8.E15 + + l1.E2 l3.E2 l6.E7 l6.E18 io_bottom.inpad[1] - - l1.S2 l1.S3 l3.S5 io_bottom_dspL.a2f_o[3] + + l1.S2 l3.S2 l6.S7 l6.S18 io_bottom.inpad[2] - - l1.S4 l2.S1 l4.S15 io_bottom_dspL.a2f_o[3] + + l1.W2 l3.W2 l6.W7 l6.W18 io_bottom.inpad[3] - - l1.S5 l3.S8 l8.S7 io_bottom_dspL.a2f_o[3] + + io_bottom.inpad[4] - - l1.S6 l3.S11 l8.S15 + + l1.E3 l3.E3 l6.E8 l6.E19 io_bottom.inpad[5] - - l1.W7 l1.W8 l3.W14 io_bottom_dspL.a2f_o[0] + + l1.S3 l3.S3 l6.S8 l6.S19 io_bottom.inpad[6] - - l1.W9 l2.W3 l4.W3 io_bottom_dspL.a2f_o[0] + + l1.W3 l3.W3 l6.W8 l6.W19 io_bottom.inpad[7] - - l1.W10 l3.W17 l8.W7 io_bottom_dspL.a2f_o[0] + + omux-0 - - l1.W11 l3.W20 l8.W15 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - io_bottom_dspL.a2f_o[1] + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - io_bottom_dspL.a2f_o[1] + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - io_bottom_dspL.a2f_o[1] + + + + io_bottom.outpad[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - l1.E4 l1.E5 l3.E8 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[1] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - l1.E6 l2.E1 l4.E11 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[2] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - l1.E7 l3.E11 l8.E7 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - l1.E8 l3.E14 l8.E15 + + io_bottom.outpad[4] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - l1.S9 l1.S10 l3.S17 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[5] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - l1.S11 l2.S3 l4.S15 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - l1.S12 l3.S20 l8.S7 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[7] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - l1.S0 l3.S23 l8.S15 + + io_bottom.outpad[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - l1.W1 l1.W2 l3.W2 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - l1.W3 l2.W5 l4.W3 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[2] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - l1.W4 l3.W5 l8.W7 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - l1.W5 l3.W8 l8.W15 + + io_bottom.outpad[4] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[5] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[6] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - l1.E11 l1.E12 l3.E20 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[0] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - l1.E0 l2.E3 l4.E11 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[1] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - l1.E1 l3.E23 l8.E7 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - l1.E2 l3.E2 l8.E15 + + io_bottom.outpad[3] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - l1.S3 l1.S4 l3.S5 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - l1.S5 l2.S5 l4.S15 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - l1.S6 l3.S8 l8.S7 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[6] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - l1.S7 l3.S11 l8.S15 + + io_bottom.outpad[7] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - l1.W8 l1.W9 l3.W14 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - l1.W10 l2.W1 l4.W3 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[1] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - l1.W11 l3.W17 l8.W7 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[2] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - l1.W12 l3.W20 l8.W15 + + io_bottom.outpad[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[4] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[5] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[6] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - l1.E5 l1.E6 l3.E8 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - l1.E7 l2.E5 l4.E11 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[0] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - l1.E8 l3.E11 l8.E7 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - l1.E9 l3.E14 l8.E15 + + io_bottom.outpad[2] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - l1.S10 l1.S11 l3.S17 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[3] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - l1.S12 l2.S1 l4.S15 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - l1.S0 l3.S20 l8.S7 io_bottom_dspL.a2f_o[3] + + io_bottom.outpad[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - l1.S1 l3.S23 l8.S15 + + io_bottom.outpad[6] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - l1.W2 l1.W3 l3.W2 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[7] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - l1.W4 l2.W3 l4.W3 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[0] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - l1.W5 l3.W5 l8.W7 io_bottom_dspL.a2f_o[0] + + io_bottom.outpad[1] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - l1.W6 l3.W8 l8.W15 + + io_bottom.outpad[2] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[3] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[4] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - io_bottom_dspL.a2f_o[1] + + io_bottom.outpad[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - l1.E12 l1.E0 l3.E20 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[6] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - l1.E1 l2.E1 l4.E11 io_bottom_dspL.a2f_o[2] + + io_bottom.outpad[7] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - l1.E2 l3.E23 l8.E7 io_bottom_dspL.a2f_o[2] + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - - l1.E3 l3.E2 l8.E15 + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - - l1.S4 l1.S5 l3.S5 io_bottom_dspL.a2f_o[3] + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - - l1.S6 l2.S3 l4.S15 io_bottom_dspL.a2f_o[3] + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - - l1.S7 l3.S8 l8.S7 io_bottom_dspL.a2f_o[3] + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - - l1.S8 l3.S11 l8.S15 + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - - l1.W9 l1.W10 l3.W14 io_bottom_dspL.a2f_o[0] + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - - l1.W11 l2.W5 l4.W3 io_bottom_dspL.a2f_o[0] + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - - l1.W12 l3.W17 l8.W7 io_bottom_dspL.a2f_o[0] + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - - l1.W0 l3.W20 l8.W15 + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - - io_bottom_dspL.a2f_o[1] + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - - io_bottom_dspL.a2f_o[1] + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - - io_bottom_dspL.a2f_o[1] + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - - l1.E6 l1.E7 l3.E8 io_bottom_dspL.a2f_o[2] + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - - l1.E8 l2.E3 l4.E11 io_bottom_dspL.a2f_o[2] + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - - l1.E9 l3.E11 l8.E7 io_bottom_dspL.a2f_o[2] + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - - l1.E10 l3.E14 l8.E15 + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - - l1.S11 l1.S12 l3.S17 io_bottom_dspL.a2f_o[3] + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - - l1.S0 l2.S5 l4.S15 io_bottom_dspL.a2f_o[3] + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - - l1.S1 l3.S20 l8.S7 io_bottom_dspL.a2f_o[3] + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - - l1.S2 l3.S23 l8.S15 + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - - l1.W3 l1.W4 l3.W2 io_bottom_dspL.a2f_o[0] + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - - l1.W5 l2.W1 l4.W3 io_bottom_dspL.a2f_o[0] + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - - l1.W6 l3.W5 l8.W7 io_bottom_dspL.a2f_o[0] + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - - l1.W7 l3.W8 l8.W15 + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - - io_bottom_dspL.a2f_o[1] + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - - io_bottom_dspL.a2f_o[1] + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - - io_bottom_dspL.a2f_o[1] + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - - l1.E0 l1.E1 l3.E20 io_bottom_dspL.a2f_o[2] + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - - l1.E2 l2.E5 l4.E11 io_bottom_dspL.a2f_o[2] + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - - l1.E3 l3.E23 l8.E7 io_bottom_dspL.a2f_o[2] + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - - l1.E4 l3.E2 l8.E15 + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - - l1.S5 l1.S6 l3.S5 io_bottom_dspL.a2f_o[3] + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - - l1.S7 l2.S1 l4.S15 io_bottom_dspL.a2f_o[3] + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - - l1.S8 l3.S8 l8.S7 io_bottom_dspL.a2f_o[3] + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - - l1.S9 l3.S11 l8.S15 + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - - l1.W10 l1.W11 l3.W14 io_bottom_dspL.a2f_o[0] + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - - l1.W12 l2.W3 l4.W3 io_bottom_dspL.a2f_o[0] + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - - l1.W0 l3.W17 l8.W7 io_bottom_dspL.a2f_o[0] + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - - l1.W1 l3.W20 l8.W15 + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - - io_bottom_dspL.a2f_o[1] + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - - io_bottom_dspL.a2f_o[1] + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - - io_bottom_dspL.a2f_o[1] + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - - l1.E7 l1.E8 l3.E8 io_bottom_dspL.a2f_o[2] + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - - l1.E9 l2.E1 l4.E11 io_bottom_dspL.a2f_o[2] + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - l1.E10 l3.E11 l8.E7 io_bottom_dspL.a2f_o[2] + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - - l1.E11 l3.E14 l8.E15 + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - - l1.S12 l1.S0 l3.S17 io_bottom_dspL.a2f_o[3] + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - - l1.S1 l2.S3 l4.S15 io_bottom_dspL.a2f_o[3] + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - - l1.S2 l3.S20 l8.S7 io_bottom_dspL.a2f_o[3] + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - - l1.S3 l3.S23 l8.S15 + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_bottom_dspL.a2f_o[0] OG_0 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 - l1.E12 l1.E11 l2.E5 l3.E23 l4.E15 io_bottom_dspL.a2f_o[0] + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 - l1.E5 l1.S11 l3.E8 l3.S17 l4.E3 io_bottom_dspL.a2f_o[0] + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 - l1.W11 l1.S10 l3.W20 l4.W11 io_bottom_dspL.a2f_o[1] + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 io_bottom_dspL.a2f_o[1] + l1.N1 l6.N1 l6.N18 l8.N11 - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 io_bottom_dspL.a2f_o[1] OG_2 + l1.E1 l6.E1 l6.E18 l8.E11 - l1.W3 l2.W3 l3.W2 io_bottom_dspL.a2f_o[2] OG_2 l1.S4 + l1.S1 l6.S1 l6.S18 l8.S11 - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 io_bottom_dspL.a2f_o[2] OG_3 + l1.W1 l6.W1 l6.W18 l8.W11 - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_bottom_dspL.a2f_o[2] OG_4 + l1.N2 l6.N2 l6.N19 l8.N12 - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 io_bottom_dspL.a2f_o[3] + l1.E2 l6.E2 l6.E19 l8.E12 - l1.W1 l3.W20 l4.W7 io_bottom_dspL.a2f_o[3] + l1.S2 l6.S2 l6.S19 l8.S12 - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 io_bottom_dspL.a2f_o[3] + l1.W2 l6.W2 l6.W19 l8.W12 - l1.W0 l1.E12 l3.W17 l4.W3 io_bottom_dspL.a2f_o[0] + l1.N3 l6.N3 l6.N20 l8.N13 - l1.E6 l2.E5 l3.E5 io_bottom_dspL.a2f_o[0] OG_6 l1.E5 + l1.E3 l6.E3 l6.E20 l8.E13 - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 io_bottom_dspL.a2f_o[0] OG_6 l1.S4 + l1.S3 l6.S3 l6.S20 l8.S13 - l1.W5 l2.W3 l3.W2 l4.W11 io_bottom_dspL.a2f_o[1] OG_7 + l1.W3 l6.W3 l6.W20 l8.W13 - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_bottom_dspL.a2f_o[1] OG_0 + l1.N4 l6.N4 l6.N21 l8.N14 - l1.W4 l1.E3 l2.W1 l3.W23 l4.W7 io_bottom_dspL.a2f_o[1] + l1.E4 l6.E4 l6.E21 l8.E14 - l1.E10 l3.E8 l4.E11 io_bottom_dspL.a2f_o[2] + l1.S4 l6.S4 l6.S21 l8.S14 - l1.E3 l1.S2 l3.E20 l4.E3 io_bottom_dspL.a2f_o[2] + l1.W4 l6.W4 l6.W21 l8.W14 - l1.E9 l1.E8 l3.E5 l4.E7 io_bottom_dspL.a2f_o[2] + l2.N0 l6.N5 l6.N22 l8.N15 - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 io_bottom_dspL.a2f_o[3] OG_2 l1.E0 + l2.E0 l6.E5 l6.E22 l8.E15 - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 io_bottom_dspL.a2f_o[3] OG_2 + l2.S0 l6.S5 l6.S22 l8.S15 - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 io_bottom_dspL.a2f_o[3] OG_3 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_bottom_dspL.a2f_o[0] OG_4 + l2.N1 l6.N6 l6.N23 l12.N0 - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 io_bottom_dspL.a2f_o[0] + l2.E1 l6.E6 l6.E23 l12.E0 - l1.W6 l1.S12 l3.W20 l3.S5 l4.W15 io_bottom_dspL.a2f_o[0] + l2.S1 l6.S6 l6.S23 l12.S0 - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 io_bottom_dspL.a2f_o[1] + l2.W1 l6.W6 l6.W23 l12.W0 - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 io_bottom_dspL.a2f_o[1] + l2.N2 l6.N7 l8.N0 l12.N1 - l1.W11 l2.W1 l3.W5 io_bottom_dspL.a2f_o[1] OG_6 l1.W6 + l2.E2 l6.E7 l8.E0 l12.E1 - l1.E4 l2.E3 l3.E14 io_bottom_dspL.a2f_o[2] OG_6 l1.S8 + l2.S2 l6.S7 l8.S0 l12.S1 - l1.E10 l2.E5 l3.E2 l4.E3 io_bottom_dspL.a2f_o[2] OG_7 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_bottom_dspL.a2f_o[2] OG_0 + l2.N3 l6.N8 l8.N1 l12.N2 - l1.E9 l1.E8 l2.E3 l3.E23 l4.E15 io_bottom_dspL.a2f_o[3] + l2.E3 l6.E8 l8.E1 l12.E2 - l1.E2 l1.S8 l3.E8 l3.S17 l4.E3 io_bottom_dspL.a2f_o[3] + l2.S3 l6.S8 l8.S1 l12.S2 - l1.W8 l1.S7 l3.W20 l4.W11 io_bottom_dspL.a2f_o[3] + l2.W3 l6.W8 l8.W1 l12.W2 - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 io_bottom_dspL.a2f_o[0] + l2.N4 l6.N9 l8.N2 l12.N3 - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 io_bottom_dspL.a2f_o[0] OG_2 l1.S6 + l2.E4 l6.E9 l8.E2 l12.E3 - l1.W0 l2.W1 l3.W2 io_bottom_dspL.a2f_o[0] OG_2 l1.E0 + l2.S4 l6.S9 l8.S2 l12.S3 - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 io_bottom_dspL.a2f_o[1] OG_3 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_bottom_dspL.a2f_o[1] OG_4 + l2.N5 l6.N10 l8.N3 l12.N4 - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 io_bottom_dspL.a2f_o[1] + l2.E5 l6.E10 l8.E3 l12.E4 - l1.W11 l3.W20 l4.W7 io_bottom_dspL.a2f_o[2] + l2.S5 l6.S10 l8.S3 l12.S4 - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 io_bottom_dspL.a2f_o[2] + l2.W5 l6.W10 l8.W3 l12.W4 - l1.W10 l1.E9 l3.W17 l4.W3 io_bottom_dspL.a2f_o[2] + l3.N0 l6.N11 l8.N4 l12.N5 - l1.E3 l2.E3 l3.E5 io_bottom_dspL.a2f_o[3] OG_6 l1.E2 + l3.E0 l6.E11 l8.E4 l12.E5 - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 io_bottom_dspL.a2f_o[3] OG_6 l1.W3 + l3.S0 l6.S11 l8.S4 l12.S5 - l1.W2 l2.W1 l3.W2 l4.W11 io_bottom_dspL.a2f_o[3] OG_7 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_bottom_dspL.a2f_o[0] OG_0 + l3.N1 l6.N12 l8.N5 l12.N6 - l1.W1 l1.E0 l2.W5 l3.W23 l4.W7 io_bottom_dspL.a2f_o[0] + l3.E1 l6.E12 l8.E5 l12.E6 - l1.E7 l3.E8 l4.E11 io_bottom_dspL.a2f_o[0] + l3.S1 l6.S12 l8.S5 l12.S6 - l1.E0 l1.S12 l3.E20 l4.E3 io_bottom_dspL.a2f_o[1] + l3.W1 l6.W12 l8.W5 l12.W6 - l1.E6 l1.E5 l3.E5 l4.E7 io_bottom_dspL.a2f_o[1] + l3.N2 l6.N13 l8.N6 l12.N7 - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 io_bottom_dspL.a2f_o[1] OG_2 l1.W12 + l3.E2 l6.E13 l8.E6 l12.E7 - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 io_bottom_dspL.a2f_o[2] OG_2 l1.W4 + l3.S2 l6.S13 l8.S6 l12.S7 - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 io_bottom_dspL.a2f_o[2] OG_3 + l3.W2 l6.W13 l8.W6 l12.W7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_bottom_dspL.a2f_o[2] OG_4 + l3.N3 l6.N14 l8.N7 l12.N8 - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 io_bottom_dspL.a2f_o[3] + l3.E3 l6.E14 l8.E7 l12.E8 - l1.W3 l1.S9 l3.W20 l3.S5 l4.W15 io_bottom_dspL.a2f_o[3] + l3.S3 l6.S14 l8.S7 l12.S8 - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 io_bottom_dspL.a2f_o[3] + l3.W3 l6.W14 l8.W7 l12.W8 + + + l3.N4 l6.N15 l8.N8 l12.N9 + + + l3.E4 l6.E15 l8.E8 l12.E9 + + + l3.S4 l6.S15 l8.S8 l12.S9 + + + l3.W4 l6.W15 l8.W8 l12.W9 + + + l3.N5 l6.N16 l8.N9 l12.N10 + + + l3.E5 l6.E16 l8.E9 l12.E10 + + + l3.S5 l6.S16 l8.S9 l12.S10 + + + l3.W5 l6.W16 l8.W9 l12.W10 - - io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] + + l1.N0 l3.N0 l6.N5 l6.N16 - - io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] + + l1.E0 l3.E0 l6.E5 l6.E16 - - io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[1] + + l1.S0 l3.S0 l6.S5 l6.S16 - - io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] + + l1.W0 l3.W0 l6.W5 l6.W16 - - io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] + + l1.N1 l3.N1 l6.N6 l6.N17 - - io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] + + l1.E1 l3.E1 l6.E6 l6.E17 - - io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[3] + + l1.S1 l3.S1 l6.S6 l6.S17 - - io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] + + l1.W1 l3.W1 l6.W6 l6.W17 - - io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] + + l1.N2 l3.N2 l6.N7 l6.N18 - - io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] + + l1.E2 l3.E2 l6.E7 l6.E18 - - io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[1] + + l1.S2 l3.S2 l6.S7 l6.S18 - - io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] io_bottom_dspL.a2f_o[0] io_bottom_dspL.a2f_o[1] + + l1.W2 l3.W2 l6.W7 l6.W18 - - io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] + + l1.N3 l3.N3 l6.N8 l6.N19 - - io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] + + l1.E3 l3.E3 l6.E8 l6.E19 - - io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[3] + + l1.S3 l3.S3 l6.S8 l6.S19 - - io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] io_bottom_dspL.a2f_o[2] io_bottom_dspL.a2f_o[3] + + l1.W3 l3.W3 l6.W8 l6.W19 - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.N4 l3.N4 l6.N9 l6.N20 - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.E4 l3.E4 l6.E9 l6.E20 + + + l1.S4 l3.S4 l6.S9 l6.S20 + + + l1.W4 l3.W4 l6.W9 l6.W20 + + + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 - - - + l1.W0 - mux_0 mux_5 mux_10 mux_15 - - - l1.N0 - mux_16 mux_21 mux_11 mux_14 - - - l1.E0 - mux_32 mux_6 mux_9 mux_31 + mux-60 mux-61 mux-62 mux-63 mux-56 - + l1.W1 - mux_64 mux_25 mux_30 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - l1.N1 - mux_80 mux_26 mux_29 - - - l1.E1 - mux_1 mux_4 mux_42 mux_47 - - + l1.W2 - mux_33 mux_38 mux_8 mux_63 - - - l1.N2 - mux_49 mux_54 mux_59 mux_12 - - - l1.E2 - mux_65 mux_24 mux_62 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - + l1.W3 - mux_2 mux_36 mux_41 mux_79 - - - l1.N3 - mux_18 mux_52 mux_75 mux_45 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - l1.E3 - mux_34 mux_37 mux_40 mux_95 - - + l1.W4 - mux_66 mux_56 mux_61 - - - l1.N4 - mux_82 mux_57 mux_60 - - - l1.E4 - mux_3 mux_68 mux_73 mux_78 - - - l1.W5 - mux_35 mux_69 mux_72 mux_94 + mux-5 mux-6 mux-7 mux-0 mux-1 - - l1.N5 - mux_51 mux_85 mux_90 mux_76 - - - l1.E5 - mux_67 mux_70 mux_88 mux_93 - - - l1.W6 - mux_96 mux_101 mux_106 mux_111 + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 - - l1.N6 - mux_112 mux_117 mux_107 mux_110 + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 - - l1.E6 - mux_0 mux_102 mux_105 mux_127 + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 - - l1.W7 - mux_32 mux_121 mux_126 + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 - - l1.N7 - mux_48 mux_122 mux_125 + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 - - l1.E7 - mux_97 mux_100 mux_10 mux_15 + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 - - l1.W8 - mux_1 mux_6 mux_104 mux_31 + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 - - l1.N8 - mux_17 mux_22 mux_27 mux_108 + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 - - l1.E8 - mux_33 mux_120 mux_30 + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 - - l2.W0 - mux_98 mux_4 mux_9 mux_47 + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 - - l2.N0 - mux_114 mux_20 mux_43 mux_13 + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 - - l2.E0 - mux_2 mux_5 mux_8 mux_63 + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 - - l2.W2 - mux_34 mux_24 mux_29 + + + + + + + + + + + + + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] - - l2.N2 - mux_50 mux_25 mux_28 + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] - - l2.E2 - mux_99 mux_36 mux_41 mux_46 + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] - - l2.W4 - mux_3 mux_37 mux_40 mux_62 + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] - - l2.N4 - mux_19 mux_53 mux_58 mux_44 + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] - - l2.E4 - mux_35 mux_38 mux_56 mux_61 + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] - - l3.W0 - mux_64 mux_69 mux_74 mux_79 + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] - - l3.N0 - mux_80 mux_85 mux_75 mux_78 + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] - - l3.E0 - mux_96 mux_70 mux_73 mux_95 + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] - - l3.W3 - mux_0 mux_89 mux_94 + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] - - l3.N3 - mux_16 mux_90 mux_93 + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] - - l3.E3 - mux_65 mux_68 mux_106 mux_111 + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] - - l3.W6 - mux_97 mux_102 mux_72 mux_127 + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] - - l3.N6 - mux_113 mux_118 mux_123 mux_76 + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] - - l3.E6 - mux_1 mux_88 mux_126 + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] - - l3.W9 - mux_66 mux_100 mux_105 mux_15 + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] - - l3.N9 - mux_82 mux_116 mux_11 mux_109 + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 mult_36.out[54] mult_36.out[70] - - l3.E9 - mux_98 mux_101 mux_104 mux_31 + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 mult_36.out[55] mult_36.out[71] - - l3.W12 - mux_2 mux_120 mux_125 + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 mult_36.out[56] - - l3.N12 - mux_18 mux_121 mux_124 + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 mult_36.out[57] - - l3.E12 - mux_67 mux_4 mux_9 mux_14 + + l1.N1 l6.N1 l6.N18 l8.N11 mult_36.out[58] - - l3.W15 - mux_99 mux_5 mux_8 mux_30 + + l1.E1 l6.E1 l6.E18 l8.E11 mult_36.out[59] - - l3.N15 - mux_115 mux_21 mux_26 mux_12 + + l1.S1 l6.S1 l6.S18 l8.S11 mult_36.out[60] - - l3.E15 - mux_3 mux_6 mux_24 mux_29 + + l1.W1 l6.W1 l6.W18 l8.W11 mult_36.out[61] - - l3.W18 - mux_32 mux_37 mux_42 mux_47 + + l1.N2 l6.N2 l6.N19 l8.N12 mult_36.out[62] - - l3.N18 - mux_48 mux_53 mux_43 mux_46 + + l1.E2 l6.E2 l6.E19 l8.E12 mult_36.out[63] - - l3.E18 - mux_64 mux_38 mux_41 mux_63 + + l1.S2 l6.S2 l6.S19 l8.S12 mult_36.out[64] - - l3.W21 - mux_96 mux_57 mux_62 + + l1.W2 l6.W2 l6.W19 l8.W12 mult_36.out[65] - - l3.N21 - mux_112 mux_58 mux_61 + + l1.N3 l6.N3 l6.N20 l8.N13 mult_36.out[66] - - l3.E21 - mux_33 mux_36 mux_74 mux_79 + + l1.E3 l6.E3 l6.E20 l8.E13 mult_36.out[67] - - l4.W0 - mux_65 mux_70 mux_40 mux_95 + + l1.S3 l6.S3 l6.S20 l8.S13 mult_36.out[68] - - l4.N0 - mux_81 mux_86 mux_91 mux_44 + + l1.W3 l6.W3 l6.W20 l8.W13 mult_36.out[69] - - l4.E0 - mux_97 mux_56 mux_94 + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - - l4.W4 - mux_34 mux_68 mux_73 mux_111 + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - - l4.N4 - mux_50 mux_84 mux_107 mux_77 + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - - l4.E4 - mux_66 mux_69 mux_72 mux_127 + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - - l4.W8 - mux_98 mux_88 mux_93 + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - - l4.N8 - mux_114 mux_89 mux_92 + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - - l4.E8 - mux_35 mux_100 mux_105 mux_110 + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - - l4.N12 - mux_83 mux_117 mux_122 mux_108 + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - - l4.E12 - mux_99 mux_102 mux_120 mux_125 + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - - l8.W0 - mux_0 mux_5 mux_10 mux_15 + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - - l8.N0 - mux_16 mux_21 mux_11 mux_14 + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - - l8.E0 - mux_32 mux_6 mux_9 mux_31 + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - - l8.W8 - mux_64 mux_25 mux_30 + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - - l8.N8 - mux_80 mux_26 mux_29 + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - - l8.E8 - mux_1 mux_4 mux_42 mux_47 + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - - l1.W9 - l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l2.N3 l6.N8 l8.N1 l12.N2 mult_36.out[54] mult_36.out[70] - - l1.N9 - l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l2.E3 l6.E8 l8.E1 l12.E2 mult_36.out[55] mult_36.out[71] - - l1.E9 - l1.W9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l2.S3 l6.S8 l8.S1 l12.S2 mult_36.out[56] - - l1.W10 - l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l2.W3 l6.W8 l8.W1 l12.W2 mult_36.out[57] - - l1.N10 - l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l2.N4 l6.N9 l8.N2 l12.N3 mult_36.out[58] - - l1.E10 - l1.W10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l2.E4 l6.E9 l8.E2 l12.E3 mult_36.out[59] - - l1.W11 - l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l2.S4 l6.S9 l8.S2 l12.S3 mult_36.out[60] - - l1.N11 - l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l2.W4 l6.W9 l8.W2 l12.W3 mult_36.out[61] - - l1.E11 - l1.W11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l2.N5 l6.N10 l8.N3 l12.N4 mult_36.out[62] - - l1.W12 - l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l2.E5 l6.E10 l8.E3 l12.E4 mult_36.out[63] - - l1.N12 - l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l2.S5 l6.S10 l8.S3 l12.S4 mult_36.out[64] - - l1.E12 - l1.W12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l2.W5 l6.W10 l8.W3 l12.W4 mult_36.out[65] - - io_bottom_dspL.f2a_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l3.N0 l6.N11 l8.N4 l12.N5 mult_36.out[66] - - io_bottom_dspL.f2a_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.E0 l6.E11 l8.E4 l12.E5 mult_36.out[67] - - io_bottom_dspL.f2a_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + l3.S0 l6.S11 l8.S4 l12.S5 mult_36.out[68] - - io_bottom_dspL.f2a_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + l3.W0 l6.W11 l8.W4 l12.W5 mult_36.out[69] - - io_bottom_dspL.f2a_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - - io_bottom_dspL.f2a_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - - io_bottom_dspL.f2a_i[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - - io_bottom_dspL.f2a_i[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - - io_bottom_dspL.f2a_i[0] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - - io_bottom_dspL.f2a_i[1] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - - io_bottom_dspL.f2a_i[2] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - - io_bottom_dspL.f2a_i[3] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - - io_bottom_dspL.f2a_i[4] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - - io_bottom_dspL.f2a_i[5] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - - io_bottom_dspL.f2a_i[6] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - - io_bottom_dspL.f2a_i[7] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - io_bottom_dspL.f2a_i[0] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - io_bottom_dspL.f2a_i[1] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - io_bottom_dspL.f2a_i[2] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - io_bottom_dspL.f2a_i[3] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - io_bottom_dspL.f2a_i[4] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + l3.N5 l6.N16 l8.N9 l12.N10 mult_36.out[54] mult_36.out[70] - - io_bottom_dspL.f2a_i[5] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.E5 l6.E16 l8.E9 l12.E10 mult_36.out[55] mult_36.out[71] - - io_bottom_dspL.f2a_i[6] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + l3.S5 l6.S16 l8.S9 l12.S10 mult_36.out[56] - - io_bottom_dspL.f2a_i[7] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + l3.W5 l6.W16 l8.W9 l12.W10 mult_36.out[57] - - io_bottom_dspL.f2a_i[0] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + l1.N0 l3.N0 l6.N5 l6.N16 mult_36.out[54] mult_36.out[70] - - io_bottom_dspL.f2a_i[1] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.E0 l3.E0 l6.E5 l6.E16 mult_36.out[55] mult_36.out[71] - - io_bottom_dspL.f2a_i[2] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + l1.S0 l3.S0 l6.S5 l6.S16 mult_36.out[56] - - io_bottom_dspL.f2a_i[3] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + l1.W0 l3.W0 l6.W5 l6.W16 mult_36.out[57] - - io_bottom_dspL.f2a_i[4] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + l1.N1 l3.N1 l6.N6 l6.N17 mult_36.out[58] - - io_bottom_dspL.f2a_i[5] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + l1.E1 l3.E1 l6.E6 l6.E17 mult_36.out[59] - - io_bottom_dspL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + l1.S1 l3.S1 l6.S6 l6.S17 mult_36.out[60] - - io_bottom_dspL.f2a_i[7] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + l1.W1 l3.W1 l6.W6 l6.W17 mult_36.out[61] - - io_bottom_dspL.f2a_i[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + l1.N2 l3.N2 l6.N7 l6.N18 mult_36.out[62] - - io_bottom_dspL.f2a_i[1] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.E2 l3.E2 l6.E7 l6.E18 mult_36.out[63] - - io_bottom_dspL.f2a_i[2] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + l1.S2 l3.S2 l6.S7 l6.S18 mult_36.out[64] - - io_bottom_dspL.f2a_i[3] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + l1.W2 l3.W2 l6.W7 l6.W18 mult_36.out[65] - - io_bottom_dspL.f2a_i[4] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + l1.N3 l3.N3 l6.N8 l6.N19 mult_36.out[66] - - io_bottom_dspL.f2a_i[5] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 + + l1.E3 l3.E3 l6.E8 l6.E19 mult_36.out[67] - - io_bottom_dspL.f2a_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + l1.S3 l3.S3 l6.S8 l6.S19 mult_36.out[68] - - io_bottom_dspL.f2a_i[7] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + l1.W3 l3.W3 l6.W8 l6.W19 mult_36.out[69] - - io_bottom_dspL.f2a_i[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - io_bottom_dspL.f2a_i[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - io_bottom_dspL.f2a_i[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - io_bottom_dspL.f2a_i[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - io_bottom_dspL.f2a_i[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + + mult_36.a[27] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - io_bottom_dspL.f2a_i[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 + + mult_36.a[33] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - io_bottom_dspL.f2a_i[6] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + mult_36.b[30] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - io_bottom_dspL.f2a_i[7] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + mult_36.a[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - io_bottom_dspL.f2a_i[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + mult_36.a[33] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - io_bottom_dspL.f2a_i[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 + + mult_36.b[30] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - io_bottom_dspL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + mult_36.a[27] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - io_bottom_dspL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + mult_36.a[33] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - io_bottom_dspL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + mult_36.a[28] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - io_bottom_dspL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 + + mult_36.a[34] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - io_bottom_dspL.f2a_i[6] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + mult_36.b[31] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - io_bottom_dspL.f2a_i[7] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + mult_36.a[28] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - io_bottom_dspL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + mult_36.a[34] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - io_bottom_dspL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 + + mult_36.b[31] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - io_bottom_dspL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + mult_36.a[28] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - io_bottom_dspL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + mult_36.a[34] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - io_bottom_dspL.lclk[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + mult_36.a[29] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - io_bottom_dspL.lreset[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + mult_36.a[35] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - io_bottom_dspL.lclk[8] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + mult_36.b[32] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - io_bottom_dspL.lreset[8] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + mult_36.a[29] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - io_bottom_dspL.lclk[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + mult_36.a[35] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - io_bottom_dspL.lreset[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + mult_36.b[32] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - io_bottom_dspL.lclk[9] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + mult_36.a[29] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - io_bottom_dspL.lreset[9] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + mult_36.a[35] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - io_bottom_dspL.lclk[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + mult_36.a[30] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - io_bottom_dspL.lreset[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + mult_36.b[27] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - io_bottom_dspL.lclk[10] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + mult_36.b[33] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - io_bottom_dspL.lreset[10] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + mult_36.a[30] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - io_bottom_dspL.lclk[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + mult_36.b[27] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - io_bottom_dspL.lreset[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + mult_36.b[33] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - io_bottom_dspL.lclk[11] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + mult_36.a[30] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - io_bottom_dspL.lreset[11] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + mult_36.b[27] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - io_bottom_dspL.lclk[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + mult_36.a[31] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - io_bottom_dspL.lreset[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + mult_36.b[28] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - io_bottom_dspL.lclk[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + mult_36.b[34] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - io_bottom_dspL.lreset[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + mult_36.a[31] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - io_bottom_dspL.lclk[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + mult_36.b[28] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - io_bottom_dspL.lreset[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + mult_36.b[34] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - io_bottom_dspL.lclk[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + mult_36.a[31] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - io_bottom_dspL.lreset[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + mult_36.b[28] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - io_bottom_dspL.lclk[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + mult_36.a[32] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - io_bottom_dspL.lreset[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + mult_36.b[29] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - io_bottom_dspL.lclk[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + mult_36.b[35] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - io_bottom_dspL.lreset[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + mult_36.a[32] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - io_bottom_dspL.lclk[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + mult_36.b[29] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - io_bottom_dspL.lreset[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + mult_36.b[35] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - io_bottom_dspL.lclk[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + mult_36.a[32] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - io_bottom_dspL.lreset[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + mult_36.b[29] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 io_bottom_ramL.a2f_o[0] + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - l1.W2 l2.W1 l4.W3 io_bottom_ramL.a2f_o[0] + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - l1.W3 l3.W5 l8.W7 io_bottom_ramL.a2f_o[0] + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - l1.W4 l3.W8 l8.W15 + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - io_bottom_ramL.a2f_o[1] + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - io_bottom_ramL.a2f_o[1] + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - io_bottom_ramL.a2f_o[1] + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - l1.E10 l1.E11 l3.E20 io_bottom_ramL.a2f_o[2] + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - l1.E12 l2.E5 l4.E11 io_bottom_ramL.a2f_o[2] + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - l1.E0 l3.E23 l8.E7 io_bottom_ramL.a2f_o[2] + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - l1.E1 l3.E2 l8.E15 + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - l1.S2 l1.S3 l3.S5 io_bottom_ramL.a2f_o[3] + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - l1.S4 l2.S1 l4.S15 io_bottom_ramL.a2f_o[3] + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - l1.S5 l3.S8 l8.S7 io_bottom_ramL.a2f_o[3] + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - l1.S6 l3.S11 l8.S15 + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - l1.W7 l1.W8 l3.W14 io_bottom_ramL.a2f_o[0] + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - l1.W9 l2.W3 l4.W3 io_bottom_ramL.a2f_o[0] + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - l1.W10 l3.W17 l8.W7 io_bottom_ramL.a2f_o[0] + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - l1.W11 l3.W20 l8.W15 + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - io_bottom_ramL.a2f_o[1] + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - io_bottom_ramL.a2f_o[1] + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - io_bottom_ramL.a2f_o[1] + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - l1.E4 l1.E5 l3.E8 io_bottom_ramL.a2f_o[2] + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - l1.E6 l2.E1 l4.E11 io_bottom_ramL.a2f_o[2] + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - l1.E7 l3.E11 l8.E7 io_bottom_ramL.a2f_o[2] + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - l1.E8 l3.E14 l8.E15 + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - l1.S9 l1.S10 l3.S17 io_bottom_ramL.a2f_o[3] + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - l1.S11 l2.S3 l4.S15 io_bottom_ramL.a2f_o[3] + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - l1.S12 l3.S20 l8.S7 io_bottom_ramL.a2f_o[3] + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - l1.S0 l3.S23 l8.S15 + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - l1.W1 l1.W2 l3.W2 io_bottom_ramL.a2f_o[0] + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - l1.W3 l2.W5 l4.W3 io_bottom_ramL.a2f_o[0] + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - l1.W4 l3.W5 l8.W7 io_bottom_ramL.a2f_o[0] + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - l1.W5 l3.W8 l8.W15 + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - io_bottom_ramL.a2f_o[1] + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - io_bottom_ramL.a2f_o[1] + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - io_bottom_ramL.a2f_o[1] + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - l1.E11 l1.E12 l3.E20 io_bottom_ramL.a2f_o[2] + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - l1.E0 l2.E3 l4.E11 io_bottom_ramL.a2f_o[2] + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - l1.E1 l3.E23 l8.E7 io_bottom_ramL.a2f_o[2] + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - l1.E2 l3.E2 l8.E15 + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - l1.S3 l1.S4 l3.S5 io_bottom_ramL.a2f_o[3] + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - l1.S5 l2.S5 l4.S15 io_bottom_ramL.a2f_o[3] + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - l1.S6 l3.S8 l8.S7 io_bottom_ramL.a2f_o[3] + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - l1.S7 l3.S11 l8.S15 + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - l1.W8 l1.W9 l3.W14 io_bottom_ramL.a2f_o[0] + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - l1.W10 l2.W1 l4.W3 io_bottom_ramL.a2f_o[0] + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - l1.W11 l3.W17 l8.W7 io_bottom_ramL.a2f_o[0] + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - l1.W12 l3.W20 l8.W15 + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - io_bottom_ramL.a2f_o[1] + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - io_bottom_ramL.a2f_o[1] + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - io_bottom_ramL.a2f_o[1] + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - l1.E5 l1.E6 l3.E8 io_bottom_ramL.a2f_o[2] + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - l1.E7 l2.E5 l4.E11 io_bottom_ramL.a2f_o[2] + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - l1.E8 l3.E11 l8.E7 io_bottom_ramL.a2f_o[2] + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - l1.E9 l3.E14 l8.E15 + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - l1.S10 l1.S11 l3.S17 io_bottom_ramL.a2f_o[3] + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - l1.S12 l2.S1 l4.S15 io_bottom_ramL.a2f_o[3] + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - l1.S0 l3.S20 l8.S7 io_bottom_ramL.a2f_o[3] + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - l1.S1 l3.S23 l8.S15 + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - l1.W2 l1.W3 l3.W2 io_bottom_ramL.a2f_o[0] + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - l1.W4 l2.W3 l4.W3 io_bottom_ramL.a2f_o[0] + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - l1.W5 l3.W5 l8.W7 io_bottom_ramL.a2f_o[0] + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - l1.W6 l3.W8 l8.W15 - - - io_bottom_ramL.a2f_o[1] - - - io_bottom_ramL.a2f_o[1] - - - io_bottom_ramL.a2f_o[1] - - - l1.E12 l1.E0 l3.E20 io_bottom_ramL.a2f_o[2] - - - l1.E1 l2.E1 l4.E11 io_bottom_ramL.a2f_o[2] - - - l1.E2 l3.E23 l8.E7 io_bottom_ramL.a2f_o[2] - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 io_bottom_ramL.a2f_o[3] - - - l1.S6 l2.S3 l4.S15 io_bottom_ramL.a2f_o[3] - - - l1.S7 l3.S8 l8.S7 io_bottom_ramL.a2f_o[3] - - - l1.S8 l3.S11 l8.S15 - - - l1.W9 l1.W10 l3.W14 io_bottom_ramL.a2f_o[0] - - - l1.W11 l2.W5 l4.W3 io_bottom_ramL.a2f_o[0] - - - l1.W12 l3.W17 l8.W7 io_bottom_ramL.a2f_o[0] + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.W0 l3.W20 l8.W15 - - - io_bottom_ramL.a2f_o[1] - - - io_bottom_ramL.a2f_o[1] - - - io_bottom_ramL.a2f_o[1] - - - l1.E6 l1.E7 l3.E8 io_bottom_ramL.a2f_o[2] - - - l1.E8 l2.E3 l4.E11 io_bottom_ramL.a2f_o[2] - - - l1.E9 l3.E11 l8.E7 io_bottom_ramL.a2f_o[2] - - - l1.E10 l3.E14 l8.E15 - - - l1.S11 l1.S12 l3.S17 io_bottom_ramL.a2f_o[3] - - - l1.S0 l2.S5 l4.S15 io_bottom_ramL.a2f_o[3] - - - l1.S1 l3.S20 l8.S7 io_bottom_ramL.a2f_o[3] - - - l1.S2 l3.S23 l8.S15 - - - l1.W3 l1.W4 l3.W2 io_bottom_ramL.a2f_o[0] - - - l1.W5 l2.W1 l4.W3 io_bottom_ramL.a2f_o[0] - - - l1.W6 l3.W5 l8.W7 io_bottom_ramL.a2f_o[0] - - - l1.W7 l3.W8 l8.W15 - - - io_bottom_ramL.a2f_o[1] - - - io_bottom_ramL.a2f_o[1] - - - io_bottom_ramL.a2f_o[1] - - - l1.E0 l1.E1 l3.E20 io_bottom_ramL.a2f_o[2] - - - l1.E2 l2.E5 l4.E11 io_bottom_ramL.a2f_o[2] - - - l1.E3 l3.E23 l8.E7 io_bottom_ramL.a2f_o[2] - - - l1.E4 l3.E2 l8.E15 - - - l1.S5 l1.S6 l3.S5 io_bottom_ramL.a2f_o[3] - - - l1.S7 l2.S1 l4.S15 io_bottom_ramL.a2f_o[3] - - - l1.S8 l3.S8 l8.S7 io_bottom_ramL.a2f_o[3] - - - l1.S9 l3.S11 l8.S15 + + + + + + + + + + + + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] - - l1.W10 l1.W11 l3.W14 io_bottom_ramL.a2f_o[0] + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] - - l1.W12 l2.W3 l4.W3 io_bottom_ramL.a2f_o[0] + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] - - l1.W0 l3.W17 l8.W7 io_bottom_ramL.a2f_o[0] + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] - - l1.W1 l3.W20 l8.W15 + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] - - io_bottom_ramL.a2f_o[1] + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] - - io_bottom_ramL.a2f_o[1] + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] - - io_bottom_ramL.a2f_o[1] + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] - - l1.E7 l1.E8 l3.E8 io_bottom_ramL.a2f_o[2] + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] - - l1.E9 l2.E1 l4.E11 io_bottom_ramL.a2f_o[2] + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] - - l1.E10 l3.E11 l8.E7 io_bottom_ramL.a2f_o[2] + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] - - l1.E11 l3.E14 l8.E15 + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] - - l1.S12 l1.S0 l3.S17 io_bottom_ramL.a2f_o[3] + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] - - l1.S1 l2.S3 l4.S15 io_bottom_ramL.a2f_o[3] + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] - - l1.S2 l3.S20 l8.S7 io_bottom_ramL.a2f_o[3] + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] - - l1.S3 l3.S23 l8.S15 + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 io_bottom_ramL.a2f_o[0] OG_0 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 mult_36.out[36] mult_36.out[52] - l1.E12 l1.E11 l2.E5 l3.E23 l4.E15 io_bottom_ramL.a2f_o[0] + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 mult_36.out[37] mult_36.out[53] - l1.E5 l1.S11 l3.E8 l3.S17 l4.E3 io_bottom_ramL.a2f_o[0] + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 mult_36.out[38] - l1.W11 l1.S10 l3.W20 l4.W11 io_bottom_ramL.a2f_o[1] + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 mult_36.out[39] - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 io_bottom_ramL.a2f_o[1] + l1.N1 l6.N1 l6.N18 l8.N11 mult_36.out[40] - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 io_bottom_ramL.a2f_o[1] OG_2 + l1.E1 l6.E1 l6.E18 l8.E11 mult_36.out[41] - l1.W3 l2.W3 l3.W2 io_bottom_ramL.a2f_o[2] OG_2 l1.S4 + l1.S1 l6.S1 l6.S18 l8.S11 mult_36.out[42] - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 io_bottom_ramL.a2f_o[2] OG_3 + l1.W1 l6.W1 l6.W18 l8.W11 mult_36.out[43] - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 io_bottom_ramL.a2f_o[2] OG_4 + l1.N2 l6.N2 l6.N19 l8.N12 mult_36.out[44] - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 io_bottom_ramL.a2f_o[3] + l1.E2 l6.E2 l6.E19 l8.E12 mult_36.out[45] - l1.W1 l3.W20 l4.W7 io_bottom_ramL.a2f_o[3] + l1.S2 l6.S2 l6.S19 l8.S12 mult_36.out[46] - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 io_bottom_ramL.a2f_o[3] + l1.W2 l6.W2 l6.W19 l8.W12 mult_36.out[47] - l1.W0 l1.E12 l3.W17 l4.W3 io_bottom_ramL.a2f_o[0] + l1.N3 l6.N3 l6.N20 l8.N13 mult_36.out[48] - l1.E6 l2.E5 l3.E5 io_bottom_ramL.a2f_o[0] OG_6 l1.E5 + l1.E3 l6.E3 l6.E20 l8.E13 mult_36.out[49] - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 io_bottom_ramL.a2f_o[0] OG_6 l1.S4 + l1.S3 l6.S3 l6.S20 l8.S13 mult_36.out[50] - l1.W5 l2.W3 l3.W2 l4.W11 io_bottom_ramL.a2f_o[1] OG_7 + l1.W3 l6.W3 l6.W20 l8.W13 mult_36.out[51] - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 io_bottom_ramL.a2f_o[1] OG_0 + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - l1.W4 l1.E3 l2.W1 l3.W23 l4.W7 io_bottom_ramL.a2f_o[1] + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - l1.E10 l3.E8 l4.E11 io_bottom_ramL.a2f_o[2] + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - l1.E3 l1.S2 l3.E20 l4.E3 io_bottom_ramL.a2f_o[2] + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - l1.E9 l1.E8 l3.E5 l4.E7 io_bottom_ramL.a2f_o[2] + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 io_bottom_ramL.a2f_o[3] OG_2 l1.E0 + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 io_bottom_ramL.a2f_o[3] OG_2 + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 io_bottom_ramL.a2f_o[3] OG_3 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 io_bottom_ramL.a2f_o[0] OG_4 + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 io_bottom_ramL.a2f_o[0] + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - l1.W6 l1.S12 l3.W20 l3.S5 l4.W15 io_bottom_ramL.a2f_o[0] + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 io_bottom_ramL.a2f_o[1] + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 io_bottom_ramL.a2f_o[1] + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - l1.W11 l2.W1 l3.W5 io_bottom_ramL.a2f_o[1] OG_6 l1.W6 + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - l1.E4 l2.E3 l3.E14 io_bottom_ramL.a2f_o[2] OG_6 l1.S8 + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - l1.E10 l2.E5 l3.E2 l4.E3 io_bottom_ramL.a2f_o[2] OG_7 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 io_bottom_ramL.a2f_o[2] OG_0 + l2.N3 l6.N8 l8.N1 l12.N2 mult_36.out[36] mult_36.out[52] - l1.E9 l1.E8 l2.E3 l3.E23 l4.E15 io_bottom_ramL.a2f_o[3] + l2.E3 l6.E8 l8.E1 l12.E2 mult_36.out[37] mult_36.out[53] - l1.E2 l1.S8 l3.E8 l3.S17 l4.E3 io_bottom_ramL.a2f_o[3] + l2.S3 l6.S8 l8.S1 l12.S2 mult_36.out[38] - l1.W8 l1.S7 l3.W20 l4.W11 io_bottom_ramL.a2f_o[3] + l2.W3 l6.W8 l8.W1 l12.W2 mult_36.out[39] - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 io_bottom_ramL.a2f_o[0] + l2.N4 l6.N9 l8.N2 l12.N3 mult_36.out[40] - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 io_bottom_ramL.a2f_o[0] OG_2 l1.S6 + l2.E4 l6.E9 l8.E2 l12.E3 mult_36.out[41] - l1.W0 l2.W1 l3.W2 io_bottom_ramL.a2f_o[0] OG_2 l1.E0 + l2.S4 l6.S9 l8.S2 l12.S3 mult_36.out[42] - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 io_bottom_ramL.a2f_o[1] OG_3 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 mult_36.out[43] - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 io_bottom_ramL.a2f_o[1] OG_4 + l2.N5 l6.N10 l8.N3 l12.N4 mult_36.out[44] - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 io_bottom_ramL.a2f_o[1] + l2.E5 l6.E10 l8.E3 l12.E4 mult_36.out[45] - l1.W11 l3.W20 l4.W7 io_bottom_ramL.a2f_o[2] + l2.S5 l6.S10 l8.S3 l12.S4 mult_36.out[46] - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 io_bottom_ramL.a2f_o[2] + l2.W5 l6.W10 l8.W3 l12.W4 mult_36.out[47] - l1.W10 l1.E9 l3.W17 l4.W3 io_bottom_ramL.a2f_o[2] + l3.N0 l6.N11 l8.N4 l12.N5 mult_36.out[48] - l1.E3 l2.E3 l3.E5 io_bottom_ramL.a2f_o[3] OG_6 l1.E2 + l3.E0 l6.E11 l8.E4 l12.E5 mult_36.out[49] - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 io_bottom_ramL.a2f_o[3] OG_6 l1.W3 + l3.S0 l6.S11 l8.S4 l12.S5 mult_36.out[50] - l1.W2 l2.W1 l3.W2 l4.W11 io_bottom_ramL.a2f_o[3] OG_7 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 mult_36.out[51] - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 io_bottom_ramL.a2f_o[0] OG_0 + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - l1.W1 l1.E0 l2.W5 l3.W23 l4.W7 io_bottom_ramL.a2f_o[0] + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - l1.E7 l3.E8 l4.E11 io_bottom_ramL.a2f_o[0] + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - l1.E0 l1.S12 l3.E20 l4.E3 io_bottom_ramL.a2f_o[1] + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - l1.E6 l1.E5 l3.E5 l4.E7 io_bottom_ramL.a2f_o[1] + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 io_bottom_ramL.a2f_o[1] OG_2 l1.W12 + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 io_bottom_ramL.a2f_o[2] OG_2 l1.W4 + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 io_bottom_ramL.a2f_o[2] OG_3 + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 io_bottom_ramL.a2f_o[2] OG_4 + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 io_bottom_ramL.a2f_o[3] + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - l1.W3 l1.S9 l3.W20 l3.S5 l4.W15 io_bottom_ramL.a2f_o[3] + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 io_bottom_ramL.a2f_o[3] + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] + + l3.N5 l6.N16 l8.N9 l12.N10 mult_36.out[36] mult_36.out[52] - - io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[1] + + l3.E5 l6.E16 l8.E9 l12.E10 mult_36.out[37] mult_36.out[53] - - io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] + + l3.S5 l6.S16 l8.S9 l12.S10 mult_36.out[38] - - io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] + + l3.W5 l6.W16 l8.W9 l12.W10 mult_36.out[39] - - io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] + + l1.N0 l3.N0 l6.N5 l6.N16 mult_36.out[36] mult_36.out[52] - - io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[3] + + l1.E0 l3.E0 l6.E5 l6.E16 mult_36.out[37] mult_36.out[53] - - io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] + + l1.S0 l3.S0 l6.S5 l6.S16 mult_36.out[38] - - io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] + + l1.W0 l3.W0 l6.W5 l6.W16 mult_36.out[39] - - io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] + + l1.N1 l3.N1 l6.N6 l6.N17 mult_36.out[40] - - io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[1] + + l1.E1 l3.E1 l6.E6 l6.E17 mult_36.out[41] - - io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] io_bottom_ramL.a2f_o[0] io_bottom_ramL.a2f_o[1] + + l1.S1 l3.S1 l6.S6 l6.S17 mult_36.out[42] - - io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] + + l1.W1 l3.W1 l6.W6 l6.W17 mult_36.out[43] - - io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] + + l1.N2 l3.N2 l6.N7 l6.N18 mult_36.out[44] - - io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[3] + + l1.E2 l3.E2 l6.E7 l6.E18 mult_36.out[45] - - io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] io_bottom_ramL.a2f_o[2] io_bottom_ramL.a2f_o[3] + + l1.S2 l3.S2 l6.S7 l6.S18 mult_36.out[46] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.W2 l3.W2 l6.W7 l6.W18 mult_36.out[47] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.N3 l3.N3 l6.N8 l6.N19 mult_36.out[48] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.E3 l3.E3 l6.E8 l6.E19 mult_36.out[49] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.S3 l3.S3 l6.S8 l6.S19 mult_36.out[50] - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.W3 l3.W3 l6.W8 l6.W19 mult_36.out[51] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - l1.W0 - mux_0 mux_5 mux_10 mux_15 + + mult_36.a[18] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - l1.N0 - mux_16 mux_21 mux_11 mux_14 + + mult_36.a[24] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - l1.E0 - mux_32 mux_6 mux_9 mux_31 + + mult_36.b[21] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - l1.W1 - mux_64 mux_25 mux_30 + + mult_36.a[18] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - l1.N1 - mux_80 mux_26 mux_29 + + mult_36.a[24] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - l1.E1 - mux_1 mux_4 mux_42 mux_47 + + mult_36.b[21] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - l1.W2 - mux_33 mux_38 mux_8 mux_63 + + mult_36.a[18] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - l1.N2 - mux_49 mux_54 mux_59 mux_12 + + mult_36.a[24] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - l1.E2 - mux_65 mux_24 mux_62 + + mult_36.a[19] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - l1.W3 - mux_2 mux_36 mux_41 mux_79 + + mult_36.a[25] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - l1.N3 - mux_18 mux_52 mux_75 mux_45 + + mult_36.b[22] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - l1.E3 - mux_34 mux_37 mux_40 mux_95 + + mult_36.a[19] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - l1.W4 - mux_66 mux_56 mux_61 + + mult_36.a[25] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - l1.N4 - mux_82 mux_57 mux_60 + + mult_36.b[22] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - l1.E4 - mux_3 mux_68 mux_73 mux_78 + + mult_36.a[19] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - l1.W5 - mux_35 mux_69 mux_72 mux_94 + + mult_36.a[25] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - l1.N5 - mux_51 mux_85 mux_90 mux_76 + + mult_36.a[20] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - l1.E5 - mux_67 mux_70 mux_88 mux_93 + + mult_36.a[26] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - l1.W6 - mux_96 mux_101 mux_106 mux_111 + + mult_36.b[23] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - l1.N6 - mux_112 mux_117 mux_107 mux_110 + + mult_36.a[20] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - l1.E6 - mux_0 mux_102 mux_105 mux_127 + + mult_36.a[26] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - l1.W7 - mux_32 mux_121 mux_126 + + mult_36.b[23] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - l1.N7 - mux_48 mux_122 mux_125 + + mult_36.a[20] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - l1.E7 - mux_97 mux_100 mux_10 mux_15 + + mult_36.a[26] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - l1.W8 - mux_1 mux_6 mux_104 mux_31 + + mult_36.a[21] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - l1.N8 - mux_17 mux_22 mux_27 mux_108 + + mult_36.b[18] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - l1.E8 - mux_33 mux_120 mux_30 + + mult_36.b[24] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - l2.W0 - mux_98 mux_4 mux_9 mux_47 + + mult_36.a[21] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - l2.N0 - mux_114 mux_20 mux_43 mux_13 + + mult_36.b[18] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - l2.E0 - mux_2 mux_5 mux_8 mux_63 + + mult_36.b[24] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - l2.W2 - mux_34 mux_24 mux_29 + + mult_36.a[21] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - l2.N2 - mux_50 mux_25 mux_28 + + mult_36.b[18] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - l2.E2 - mux_99 mux_36 mux_41 mux_46 + + mult_36.a[22] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - l2.W4 - mux_3 mux_37 mux_40 mux_62 + + mult_36.b[19] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - l2.N4 - mux_19 mux_53 mux_58 mux_44 + + mult_36.b[25] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - l2.E4 - mux_35 mux_38 mux_56 mux_61 + + mult_36.a[22] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - l3.W0 - mux_64 mux_69 mux_74 mux_79 + + mult_36.b[19] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + mult_36.b[25] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + mult_36.a[22] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + mult_36.b[19] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + mult_36.a[23] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + mult_36.b[20] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + mult_36.b[26] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + mult_36.a[23] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + mult_36.b[20] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + mult_36.b[26] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + mult_36.a[23] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + mult_36.b[20] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - + l3.N0 - mux_80 mux_85 mux_75 mux_78 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - + l3.E0 - mux_96 mux_70 mux_73 mux_95 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - + l3.W3 - mux_0 mux_89 mux_94 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - - l3.N3 - mux_16 mux_90 mux_93 + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - l3.E3 - mux_65 mux_68 mux_106 mux_111 + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] - - l3.W6 - mux_97 mux_102 mux_72 mux_127 + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] - - l3.N6 - mux_113 mux_118 mux_123 mux_76 + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] - - l3.E6 - mux_1 mux_88 mux_126 + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] - - l3.W9 - mux_66 mux_100 mux_105 mux_15 + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] - - l3.N9 - mux_82 mux_116 mux_11 mux_109 + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] - - l3.E9 - mux_98 mux_101 mux_104 mux_31 + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 mult_36.out[18] mult_36.out[34] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 mult_36.out[19] mult_36.out[35] - - l3.W12 - mux_2 mux_120 mux_125 + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 mult_36.out[20] - - l3.N12 - mux_18 mux_121 mux_124 + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 mult_36.out[21] - - l3.E12 - mux_67 mux_4 mux_9 mux_14 + + l1.N1 l6.N1 l6.N18 l8.N11 mult_36.out[22] - - l3.W15 - mux_99 mux_5 mux_8 mux_30 + + l1.E1 l6.E1 l6.E18 l8.E11 mult_36.out[23] - - l3.N15 - mux_115 mux_21 mux_26 mux_12 + + l1.S1 l6.S1 l6.S18 l8.S11 mult_36.out[24] - - l3.E15 - mux_3 mux_6 mux_24 mux_29 + + l1.W1 l6.W1 l6.W18 l8.W11 mult_36.out[25] - - l3.W18 - mux_32 mux_37 mux_42 mux_47 + + l1.N2 l6.N2 l6.N19 l8.N12 mult_36.out[26] - - l3.N18 - mux_48 mux_53 mux_43 mux_46 + + l1.E2 l6.E2 l6.E19 l8.E12 mult_36.out[27] - - l3.E18 - mux_64 mux_38 mux_41 mux_63 + + l1.S2 l6.S2 l6.S19 l8.S12 mult_36.out[28] - - l3.W21 - mux_96 mux_57 mux_62 + + l1.W2 l6.W2 l6.W19 l8.W12 mult_36.out[29] - - l3.N21 - mux_112 mux_58 mux_61 + + l1.N3 l6.N3 l6.N20 l8.N13 mult_36.out[30] - - l3.E21 - mux_33 mux_36 mux_74 mux_79 + + l1.E3 l6.E3 l6.E20 l8.E13 mult_36.out[31] - - l4.W0 - mux_65 mux_70 mux_40 mux_95 + + l1.S3 l6.S3 l6.S20 l8.S13 mult_36.out[32] - - l4.N0 - mux_81 mux_86 mux_91 mux_44 + + l1.W3 l6.W3 l6.W20 l8.W13 mult_36.out[33] - - l4.E0 - mux_97 mux_56 mux_94 + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - - l4.W4 - mux_34 mux_68 mux_73 mux_111 + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - - l4.N4 - mux_50 mux_84 mux_107 mux_77 + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - - l4.E4 - mux_66 mux_69 mux_72 mux_127 + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - - l4.W8 - mux_98 mux_88 mux_93 + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - - l4.N8 - mux_114 mux_89 mux_92 + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - - l4.E8 - mux_35 mux_100 mux_105 mux_110 + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - - l4.N12 - mux_83 mux_117 mux_122 mux_108 + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - - l4.E12 - mux_99 mux_102 mux_120 mux_125 + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - - l8.W0 - mux_0 mux_5 mux_10 mux_15 + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - - l8.N0 - mux_16 mux_21 mux_11 mux_14 + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - - l8.E0 - mux_32 mux_6 mux_9 mux_31 + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - - l8.W8 - mux_64 mux_25 mux_30 + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - - l8.N8 - mux_80 mux_26 mux_29 + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - - l8.E8 - mux_1 mux_4 mux_42 mux_47 + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - - l1.W9 - l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l2.N3 l6.N8 l8.N1 l12.N2 mult_36.out[18] mult_36.out[34] - - l1.N9 - l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l2.E3 l6.E8 l8.E1 l12.E2 mult_36.out[19] mult_36.out[35] - - l1.E9 - l1.W9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l2.S3 l6.S8 l8.S1 l12.S2 mult_36.out[20] - - l1.W10 - l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l2.W3 l6.W8 l8.W1 l12.W2 mult_36.out[21] - - l1.N10 - l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l2.N4 l6.N9 l8.N2 l12.N3 mult_36.out[22] - - l1.E10 - l1.W10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l2.E4 l6.E9 l8.E2 l12.E3 mult_36.out[23] - - l1.W11 - l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l2.S4 l6.S9 l8.S2 l12.S3 mult_36.out[24] - - l1.N11 - l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l2.W4 l6.W9 l8.W2 l12.W3 mult_36.out[25] - - l1.E11 - l1.W11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l2.N5 l6.N10 l8.N3 l12.N4 mult_36.out[26] - - l1.W12 - l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l2.E5 l6.E10 l8.E3 l12.E4 mult_36.out[27] - - l1.N12 - l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l2.S5 l6.S10 l8.S3 l12.S4 mult_36.out[28] - - l1.E12 - l1.W12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l2.W5 l6.W10 l8.W3 l12.W4 mult_36.out[29] - - io_bottom_ramL.f2a_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l3.N0 l6.N11 l8.N4 l12.N5 mult_36.out[30] - - io_bottom_ramL.f2a_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.E0 l6.E11 l8.E4 l12.E5 mult_36.out[31] - - io_bottom_ramL.f2a_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + l3.S0 l6.S11 l8.S4 l12.S5 mult_36.out[32] - - io_bottom_ramL.f2a_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + l3.W0 l6.W11 l8.W4 l12.W5 mult_36.out[33] - - io_bottom_ramL.f2a_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - - io_bottom_ramL.f2a_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - - io_bottom_ramL.f2a_i[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - - io_bottom_ramL.f2a_i[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - - io_bottom_ramL.f2a_i[0] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - - io_bottom_ramL.f2a_i[1] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - - io_bottom_ramL.f2a_i[2] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - - io_bottom_ramL.f2a_i[3] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - - io_bottom_ramL.f2a_i[4] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - - io_bottom_ramL.f2a_i[5] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - - io_bottom_ramL.f2a_i[6] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - - io_bottom_ramL.f2a_i[7] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - io_bottom_ramL.f2a_i[0] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - io_bottom_ramL.f2a_i[1] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - io_bottom_ramL.f2a_i[2] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - io_bottom_ramL.f2a_i[3] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - io_bottom_ramL.f2a_i[4] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + l3.N5 l6.N16 l8.N9 l12.N10 mult_36.out[18] mult_36.out[34] - - io_bottom_ramL.f2a_i[5] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + l3.E5 l6.E16 l8.E9 l12.E10 mult_36.out[19] mult_36.out[35] - - io_bottom_ramL.f2a_i[6] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + l3.S5 l6.S16 l8.S9 l12.S10 mult_36.out[20] - - io_bottom_ramL.f2a_i[7] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + l3.W5 l6.W16 l8.W9 l12.W10 mult_36.out[21] - - io_bottom_ramL.f2a_i[0] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + l1.N0 l3.N0 l6.N5 l6.N16 mult_36.out[18] mult_36.out[34] - - io_bottom_ramL.f2a_i[1] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + l1.E0 l3.E0 l6.E5 l6.E16 mult_36.out[19] mult_36.out[35] - - io_bottom_ramL.f2a_i[2] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + l1.S0 l3.S0 l6.S5 l6.S16 mult_36.out[20] - - io_bottom_ramL.f2a_i[3] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + l1.W0 l3.W0 l6.W5 l6.W16 mult_36.out[21] - - io_bottom_ramL.f2a_i[4] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + l1.N1 l3.N1 l6.N6 l6.N17 mult_36.out[22] - - io_bottom_ramL.f2a_i[5] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + l1.E1 l3.E1 l6.E6 l6.E17 mult_36.out[23] - - io_bottom_ramL.f2a_i[6] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + l1.S1 l3.S1 l6.S6 l6.S17 mult_36.out[24] - - io_bottom_ramL.f2a_i[7] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + l1.W1 l3.W1 l6.W6 l6.W17 mult_36.out[25] - - io_bottom_ramL.f2a_i[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + l1.N2 l3.N2 l6.N7 l6.N18 mult_36.out[26] - - io_bottom_ramL.f2a_i[1] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 + + l1.E2 l3.E2 l6.E7 l6.E18 mult_36.out[27] - - io_bottom_ramL.f2a_i[2] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + l1.S2 l3.S2 l6.S7 l6.S18 mult_36.out[28] - - io_bottom_ramL.f2a_i[3] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + l1.W2 l3.W2 l6.W7 l6.W18 mult_36.out[29] - - io_bottom_ramL.f2a_i[4] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + l1.N3 l3.N3 l6.N8 l6.N19 mult_36.out[30] - - io_bottom_ramL.f2a_i[5] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 + + l1.E3 l3.E3 l6.E8 l6.E19 mult_36.out[31] - - io_bottom_ramL.f2a_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + l1.S3 l3.S3 l6.S8 l6.S19 mult_36.out[32] - - io_bottom_ramL.f2a_i[7] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + l1.W3 l3.W3 l6.W8 l6.W19 mult_36.out[33] - - io_bottom_ramL.f2a_i[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - io_bottom_ramL.f2a_i[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - io_bottom_ramL.f2a_i[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - io_bottom_ramL.f2a_i[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - io_bottom_ramL.f2a_i[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + + + mult_36.a[9] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - io_bottom_ramL.f2a_i[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 + + mult_36.a[15] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - io_bottom_ramL.f2a_i[6] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + mult_36.b[12] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - io_bottom_ramL.f2a_i[7] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + mult_36.a[9] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - io_bottom_ramL.f2a_i[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + mult_36.a[15] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - io_bottom_ramL.f2a_i[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 + + mult_36.b[12] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - io_bottom_ramL.f2a_i[2] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + mult_36.a[9] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - io_bottom_ramL.f2a_i[3] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + mult_36.a[15] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - io_bottom_ramL.f2a_i[4] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + mult_36.a[10] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - io_bottom_ramL.f2a_i[5] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 + + mult_36.a[16] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - io_bottom_ramL.f2a_i[6] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + mult_36.b[13] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - io_bottom_ramL.f2a_i[7] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + mult_36.a[10] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - io_bottom_ramL.f2a_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + mult_36.a[16] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - io_bottom_ramL.f2a_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 + + mult_36.b[13] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - io_bottom_ramL.f2a_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + mult_36.a[10] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - io_bottom_ramL.f2a_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + mult_36.a[16] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - io_bottom_ramL.lclk[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + mult_36.a[11] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - io_bottom_ramL.lreset[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + mult_36.a[17] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - io_bottom_ramL.lclk[8] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + mult_36.b[14] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - io_bottom_ramL.lreset[8] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + mult_36.a[11] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - io_bottom_ramL.lclk[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + mult_36.a[17] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - io_bottom_ramL.lreset[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + mult_36.b[14] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - io_bottom_ramL.lclk[9] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + mult_36.a[11] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - io_bottom_ramL.lreset[9] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + mult_36.a[17] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - io_bottom_ramL.lclk[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + mult_36.a[12] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - io_bottom_ramL.lreset[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + mult_36.b[9] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - io_bottom_ramL.lclk[10] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + mult_36.b[15] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - io_bottom_ramL.lreset[10] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + mult_36.a[12] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - io_bottom_ramL.lclk[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + mult_36.b[9] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - io_bottom_ramL.lreset[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + mult_36.b[15] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - io_bottom_ramL.lclk[11] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + mult_36.a[12] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - io_bottom_ramL.lreset[11] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + mult_36.b[9] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - io_bottom_ramL.lclk[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + mult_36.a[13] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - io_bottom_ramL.lreset[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + mult_36.b[10] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - io_bottom_ramL.lclk[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + mult_36.b[16] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - io_bottom_ramL.lreset[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 + + mult_36.a[13] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - io_bottom_ramL.lclk[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + mult_36.b[10] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - io_bottom_ramL.lreset[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + mult_36.b[16] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - io_bottom_ramL.lclk[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + mult_36.a[13] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - io_bottom_ramL.lreset[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + mult_36.b[10] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - io_bottom_ramL.lclk[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + mult_36.a[14] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - io_bottom_ramL.lreset[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + mult_36.b[11] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - io_bottom_ramL.lclk[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + mult_36.b[17] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - io_bottom_ramL.lreset[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 + + mult_36.a[14] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - io_bottom_ramL.lclk[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + mult_36.b[11] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - io_bottom_ramL.lreset[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + mult_36.b[17] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - io_bottom_ramL.lclk[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + mult_36.a[14] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - io_bottom_ramL.lreset[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + mult_36.b[11] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - l1.W2 l2.W1 l4.W3 + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - l1.W3 l3.W5 l8.W7 + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - l1.W4 l3.W8 l8.W15 + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - l1.N5 l1.N6 l3.N11 + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - l1.N7 l2.N3 l4.N7 + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - l1.N8 l3.N14 l8.N7 + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - l1.N9 l3.N17 l8.N15 + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - l1.E10 l1.E11 l3.E20 + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - l1.E12 l2.E5 l4.E11 + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - l1.E0 l3.E23 l8.E7 + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - l1.E1 l3.E2 l8.E15 + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - l1.S2 l1.S3 l3.S5 + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - l1.S4 l2.S1 l4.S15 + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - l1.S5 l3.S8 l8.S7 + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - l1.S6 l3.S11 l8.S15 + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - l1.W7 l1.W8 l3.W14 + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - l1.W9 l2.W3 l4.W3 + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - l1.W10 l3.W17 l8.W7 + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - l1.W11 l3.W20 l8.W15 + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - l1.N12 l1.N0 l3.N23 + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - l1.N1 l2.N5 l4.N7 + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - l1.N2 l3.N2 l8.N7 + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - l1.N3 l3.N5 l8.N15 + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - l1.E4 l1.E5 l3.E8 + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - l1.E6 l2.E1 l4.E11 + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - l1.E7 l3.E11 l8.E7 + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - l1.E8 l3.E14 l8.E15 + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - l1.S9 l1.S10 l3.S17 + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - l1.S11 l2.S3 l4.S15 + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - l1.S12 l3.S20 l8.S7 + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - l1.S0 l3.S23 l8.S15 + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - l1.W1 l1.W2 l3.W2 + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - l1.W3 l2.W5 l4.W3 + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - l1.W4 l3.W5 l8.W7 + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - l1.W5 l3.W8 l8.W15 + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - l1.N6 l1.N7 l3.N11 + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - l1.N8 l2.N1 l4.N7 + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - l1.N9 l3.N14 l8.N7 + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - l1.N10 l3.N17 l8.N15 + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - l1.E11 l1.E12 l3.E20 + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - l1.E0 l2.E3 l4.E11 + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - l1.E1 l3.E23 l8.E7 + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - l1.E2 l3.E2 l8.E15 + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - l1.S3 l1.S4 l3.S5 + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - l1.S5 l2.S5 l4.S15 + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - l1.S6 l3.S8 l8.S7 + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - l1.S7 l3.S11 l8.S15 + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - l1.W8 l1.W9 l3.W14 + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - l1.W10 l2.W1 l4.W3 + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - l1.W11 l3.W17 l8.W7 + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - l1.W12 l3.W20 l8.W15 + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - l1.N0 l1.N1 l3.N23 + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - l1.N2 l2.N3 l4.N7 + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - l1.N3 l3.N2 l8.N7 + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - l1.N4 l3.N5 l8.N15 + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - l1.E5 l1.E6 l3.E8 + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - l1.E7 l2.E5 l4.E11 + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - l1.E8 l3.E11 l8.E7 + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - l1.E9 l3.E14 l8.E15 + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - l1.S10 l1.S11 l3.S17 + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - l1.S12 l2.S1 l4.S15 + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - l1.S0 l3.S20 l8.S7 + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - l1.S1 l3.S23 l8.S15 + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - l1.W2 l1.W3 l3.W2 + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - l1.W4 l2.W3 l4.W3 + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - l1.W5 l3.W5 l8.W7 + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 - - - l1.N9 l2.N5 l4.N7 - - - l1.N10 l3.N14 l8.N7 - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 - - - l1.E1 l2.E1 l4.E11 - - - l1.E2 l3.E23 l8.E7 - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 - - - l1.S6 l2.S3 l4.S15 - - - l1.S7 l3.S8 l8.S7 - - - l1.S8 l3.S11 l8.S15 - - - l1.W9 l1.W10 l3.W14 - - - l1.W11 l2.W5 l4.W3 - - - l1.W12 l3.W17 l8.W7 - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 - - - l1.N3 l2.N1 l4.N7 - - - l1.N4 l3.N2 l8.N7 - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 - - - l1.E8 l2.E3 l4.E11 - - - l1.E9 l3.E11 l8.E7 + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.E10 l3.E14 l8.E15 - - - l1.S11 l1.S12 l3.S17 - - - l1.S0 l2.S5 l4.S15 - - - l1.S1 l3.S20 l8.S7 - - - l1.S2 l3.S23 l8.S15 - - - l1.W3 l1.W4 l3.W2 - - - l1.W5 l2.W1 l4.W3 - - - l1.W6 l3.W5 l8.W7 - - - l1.W7 l3.W8 l8.W15 - - - l1.N8 l1.N9 l3.N11 - - - l1.N10 l2.N3 l4.N7 - - - l1.N11 l3.N14 l8.N7 - - - l1.N12 l3.N17 l8.N15 - - - l1.E0 l1.E1 l3.E20 - - - l1.E2 l2.E5 l4.E11 - - - l1.E3 l3.E23 l8.E7 - - - l1.E4 l3.E2 l8.E15 - - - l1.S5 l1.S6 l3.S5 - - - l1.S7 l2.S1 l4.S15 - - - l1.S8 l3.S8 l8.S7 - - - l1.S9 l3.S11 l8.S15 - - - l1.W10 l1.W11 l3.W14 + + + + + + + + + + + + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] - - l1.W12 l2.W3 l4.W3 + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] - - l1.W0 l3.W17 l8.W7 + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] - - l1.W1 l3.W20 l8.W15 + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] - - l1.N2 l1.N3 l3.N23 + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] - - l1.N4 l2.N5 l4.N7 + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] - - l1.N5 l3.N2 l8.N7 + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] - - l1.N6 l3.N5 l8.N15 + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] - - l1.E7 l1.E8 l3.E8 + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] - - l1.E9 l2.E1 l4.E11 + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] - - l1.E10 l3.E11 l8.E7 + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] - - l1.E11 l3.E14 l8.E15 + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] - - l1.S12 l1.S0 l3.S17 + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] - - l1.S1 l2.S3 l4.S15 + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] - - l1.S2 l3.S20 l8.S7 + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] - - l1.S3 l3.S23 l8.S15 + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 mult_36.out[0] mult_36.out[16] - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 mult_36.out[1] mult_36.out[17] - l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 mult_36.out[2] - l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 mult_36.out[3] - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 + l1.N1 l6.N1 l6.N18 l8.N11 mult_36.out[4] - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 l1.N2 + l1.E1 l6.E1 l6.E18 l8.E11 mult_36.out[5] - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 l1.S4 + l1.S1 l6.S1 l6.S18 l8.S11 mult_36.out[6] - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 l1.N9 + l1.W1 l6.W1 l6.W18 l8.W11 mult_36.out[7] - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 + l1.N2 l6.N2 l6.N19 l8.N12 mult_36.out[8] - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 + l1.E2 l6.E2 l6.E19 l8.E12 mult_36.out[9] - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 + l1.S2 l6.S2 l6.S19 l8.S12 mult_36.out[10] - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 + l1.W2 l6.W2 l6.W19 l8.W12 mult_36.out[11] - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 + l1.N3 l6.N3 l6.N20 l8.N13 mult_36.out[12] - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 l1.E5 + l1.E3 l6.E3 l6.E20 l8.E13 mult_36.out[13] - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 l1.S4 + l1.S3 l6.S3 l6.S20 l8.S13 mult_36.out[14] - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 l1.N0 + l1.W3 l6.W3 l6.W20 l8.W13 mult_36.out[15] - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 l1.E0 + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 l1.N10 + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 l1.W6 + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 l1.S8 + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 + l2.N3 l6.N8 l8.N1 l12.N2 mult_36.out[0] mult_36.out[16] - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 + l2.E3 l6.E8 l8.E1 l12.E2 mult_36.out[1] mult_36.out[17] - l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 + l2.S3 l6.S8 l8.S1 l12.S2 mult_36.out[2] - l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 + l2.W3 l6.W8 l8.W1 l12.W2 mult_36.out[3] - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 + l2.N4 l6.N9 l8.N2 l12.N3 mult_36.out[4] - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 l1.S6 + l2.E4 l6.E9 l8.E2 l12.E3 mult_36.out[5] - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 l1.E0 + l2.S4 l6.S9 l8.S2 l12.S3 mult_36.out[6] - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 mult_36.out[7] - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 + l2.N5 l6.N10 l8.N3 l12.N4 mult_36.out[8] - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 + l2.E5 l6.E10 l8.E3 l12.E4 mult_36.out[9] - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 + l2.S5 l6.S10 l8.S3 l12.S4 mult_36.out[10] - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 + l2.W5 l6.W10 l8.W3 l12.W4 mult_36.out[11] - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 + l3.N0 l6.N11 l8.N4 l12.N5 mult_36.out[12] - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 l1.E2 + l3.E0 l6.E11 l8.E4 l12.E5 mult_36.out[13] - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 l1.W3 + l3.S0 l6.S11 l8.S4 l12.S5 mult_36.out[14] - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 mult_36.out[15] - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 l1.W12 + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 l1.W4 + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 l1.N10 + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 - - - - - l1.W0 - mux_0 mux_5 mux_10 mux_15 - - - l1.N0 - mux_16 mux_21 mux_11 mux_14 - - - l1.E0 - mux_32 mux_6 mux_9 mux_31 - - - l1.S0 - mux_48 mux_22 mux_27 mux_13 - - - l1.W1 - mux_64 mux_7 mux_25 mux_30 - - - l1.N1 - mux_80 mux_23 mux_26 mux_29 - - - l1.E1 - mux_1 mux_4 mux_42 mux_47 - - - l1.S1 - mux_17 mux_20 mux_43 mux_46 - - - l1.W2 - mux_33 mux_38 mux_8 mux_63 - - - l1.N2 - mux_49 mux_54 mux_59 mux_12 - - - l1.E2 - mux_65 mux_39 mux_24 mux_62 - - - l1.S2 - mux_81 mux_55 mux_58 mux_28 - - - l1.W3 - mux_2 mux_36 mux_41 mux_79 - - - l1.N3 - mux_18 mux_52 mux_75 mux_45 - - - l1.E3 - mux_34 mux_37 mux_40 mux_95 - - - l1.S3 - mux_50 mux_53 mux_91 mux_44 - - - l1.W4 - mux_66 mux_71 mux_56 mux_61 + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - l1.N4 - mux_82 mux_87 mux_57 mux_60 - - - l1.E4 - mux_3 mux_68 mux_73 mux_78 - - - l1.S4 - mux_19 mux_84 mux_74 mux_77 - - - l1.W5 - mux_35 mux_69 mux_72 mux_94 - - - l1.N5 - mux_51 mux_85 mux_90 mux_76 - - - l1.E5 - mux_67 mux_70 mux_88 mux_93 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - l1.S5 - mux_83 mux_86 mux_89 mux_92 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - l1.W6 - mux_96 mux_101 mux_106 mux_111 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - l1.N6 - mux_112 mux_117 mux_107 mux_110 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - l1.E6 - mux_0 mux_102 mux_105 mux_127 + + l3.N5 l6.N16 l8.N9 l12.N10 mult_36.out[0] mult_36.out[16] - - l1.S6 - mux_16 mux_118 mux_123 mux_109 + + l3.E5 l6.E16 l8.E9 l12.E10 mult_36.out[1] mult_36.out[17] - - l1.W7 - mux_32 mux_103 mux_121 mux_126 + + l3.S5 l6.S16 l8.S9 l12.S10 mult_36.out[2] - - l1.N7 - mux_48 mux_119 mux_122 mux_125 + + l3.W5 l6.W16 l8.W9 l12.W10 mult_36.out[3] - - l1.E7 - mux_97 mux_100 mux_10 mux_15 + + l1.N0 l3.N0 l6.N5 l6.N16 mult_36.out[0] mult_36.out[16] - - l1.S7 - mux_113 mux_116 mux_11 mux_14 - - - l1.W8 - mux_1 mux_6 mux_104 mux_31 - - - l1.N8 - mux_17 mux_22 mux_27 mux_108 - - - l1.E8 - mux_33 mux_7 mux_120 mux_30 - - - l1.S8 - mux_49 mux_23 mux_26 mux_124 - - - l2.W0 - mux_98 mux_4 mux_9 mux_47 - - - l2.N0 - mux_114 mux_20 mux_43 mux_13 + + l1.E0 l3.E0 l6.E5 l6.E16 mult_36.out[1] mult_36.out[17] - - l2.E0 - mux_2 mux_5 mux_8 mux_63 + + l1.S0 l3.S0 l6.S5 l6.S16 mult_36.out[2] - - l2.S0 - mux_18 mux_21 mux_59 mux_12 + + l1.W0 l3.W0 l6.W5 l6.W16 mult_36.out[3] - - l2.W2 - mux_34 mux_39 mux_24 mux_29 + + l1.N1 l3.N1 l6.N6 l6.N17 mult_36.out[4] - - l2.N2 - mux_50 mux_55 mux_25 mux_28 + + l1.E1 l3.E1 l6.E6 l6.E17 mult_36.out[5] - - l2.E2 - mux_99 mux_36 mux_41 mux_46 + + l1.S1 l3.S1 l6.S6 l6.S17 mult_36.out[6] - - l2.S2 - mux_115 mux_52 mux_42 mux_45 + + l1.W1 l3.W1 l6.W6 l6.W17 mult_36.out[7] - - l2.W4 - mux_3 mux_37 mux_40 mux_62 + + l1.N2 l3.N2 l6.N7 l6.N18 mult_36.out[8] - - l2.N4 - mux_19 mux_53 mux_58 mux_44 + + l1.E2 l3.E2 l6.E7 l6.E18 mult_36.out[9] - - l2.E4 - mux_35 mux_38 mux_56 mux_61 + + l1.S2 l3.S2 l6.S7 l6.S18 mult_36.out[10] - - l2.S4 - mux_51 mux_54 mux_57 mux_60 + + l1.W2 l3.W2 l6.W7 l6.W18 mult_36.out[11] - - l3.W0 - mux_64 mux_69 mux_74 mux_79 + + l1.N3 l3.N3 l6.N8 l6.N19 mult_36.out[12] - - l3.N0 - mux_80 mux_85 mux_75 mux_78 + + l1.E3 l3.E3 l6.E8 l6.E19 mult_36.out[13] - - l3.E0 - mux_96 mux_70 mux_73 mux_95 + + l1.S3 l3.S3 l6.S8 l6.S19 mult_36.out[14] - - l3.S0 - mux_112 mux_86 mux_91 mux_77 + + l1.W3 l3.W3 l6.W8 l6.W19 mult_36.out[15] - - l3.W3 - mux_0 mux_71 mux_89 mux_94 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - l3.N3 - mux_16 mux_87 mux_90 mux_93 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - l3.E3 - mux_65 mux_68 mux_106 mux_111 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - l3.S3 - mux_81 mux_84 mux_107 mux_110 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - l3.W6 - mux_97 mux_102 mux_72 mux_127 + + + + mult_36.a[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - l3.N6 - mux_113 mux_118 mux_123 mux_76 + + mult_36.a[6] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - l3.E6 - mux_1 mux_103 mux_88 mux_126 + + mult_36.b[3] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - l3.S6 - mux_17 mux_119 mux_122 mux_92 + + mult_36.a[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - l3.W9 - mux_66 mux_100 mux_105 mux_15 + + mult_36.a[6] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - l3.N9 - mux_82 mux_116 mux_11 mux_109 + + mult_36.b[3] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - l3.E9 - mux_98 mux_101 mux_104 mux_31 + + mult_36.a[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - l3.S9 - mux_114 mux_117 mux_27 mux_108 + + mult_36.a[6] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - l3.W12 - mux_2 mux_7 mux_120 mux_125 + + mult_36.a[1] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - l3.N12 - mux_18 mux_23 mux_121 mux_124 + + mult_36.a[7] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - l3.E12 - mux_67 mux_4 mux_9 mux_14 + + mult_36.b[4] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - l3.S12 - mux_83 mux_20 mux_10 mux_13 + + mult_36.a[1] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - l3.W15 - mux_99 mux_5 mux_8 mux_30 + + mult_36.a[7] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - l3.N15 - mux_115 mux_21 mux_26 mux_12 + + mult_36.b[4] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - l3.E15 - mux_3 mux_6 mux_24 mux_29 + + mult_36.a[1] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - l3.S15 - mux_19 mux_22 mux_25 mux_28 + + mult_36.a[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - l3.W18 - mux_32 mux_37 mux_42 mux_47 + + mult_36.a[2] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - l3.N18 - mux_48 mux_53 mux_43 mux_46 + + mult_36.a[8] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - l3.E18 - mux_64 mux_38 mux_41 mux_63 + + mult_36.b[5] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - l3.S18 - mux_80 mux_54 mux_59 mux_45 + + mult_36.a[2] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - l3.W21 - mux_96 mux_39 mux_57 mux_62 + + mult_36.a[8] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - l3.N21 - mux_112 mux_55 mux_58 mux_61 + + mult_36.b[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - l3.E21 - mux_33 mux_36 mux_74 mux_79 + + mult_36.a[2] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - l3.S21 - mux_49 mux_52 mux_75 mux_78 + + mult_36.a[8] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - l4.W0 - mux_65 mux_70 mux_40 mux_95 + + mult_36.a[3] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - l4.N0 - mux_81 mux_86 mux_91 mux_44 + + mult_36.b[0] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - l4.E0 - mux_97 mux_71 mux_56 mux_94 + + mult_36.b[6] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - l4.S0 - mux_113 mux_87 mux_90 mux_60 + + mult_36.a[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - l4.W4 - mux_34 mux_68 mux_73 mux_111 + + mult_36.b[0] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - l4.N4 - mux_50 mux_84 mux_107 mux_77 + + mult_36.b[6] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - l4.E4 - mux_66 mux_69 mux_72 mux_127 + + mult_36.a[3] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - l4.S4 - mux_82 mux_85 mux_123 mux_76 + + mult_36.b[0] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - l4.W8 - mux_98 mux_103 mux_88 mux_93 + + mult_36.a[4] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - l4.N8 - mux_114 mux_119 mux_89 mux_92 + + mult_36.b[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - l4.E8 - mux_35 mux_100 mux_105 mux_110 + + mult_36.b[7] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - l4.S8 - mux_51 mux_116 mux_106 mux_109 + + mult_36.a[4] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + mult_36.b[1] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - l4.N12 - mux_83 mux_117 mux_122 mux_108 + + mult_36.b[7] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - l4.E12 - mux_99 mux_102 mux_120 mux_125 + + mult_36.a[4] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - l4.S12 - mux_115 mux_118 mux_121 mux_124 + + mult_36.b[1] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - l8.W0 - mux_0 mux_5 mux_10 mux_15 + + mult_36.a[5] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - l8.N0 - mux_16 mux_21 mux_11 mux_14 + + mult_36.b[2] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - l8.E0 - mux_32 mux_6 mux_9 mux_31 + + mult_36.b[8] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - l8.S0 - mux_48 mux_22 mux_27 mux_13 + + mult_36.a[5] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - l8.W8 - mux_64 mux_7 mux_25 mux_30 + + mult_36.b[2] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - l8.N8 - mux_80 mux_23 mux_26 mux_29 + + mult_36.b[8] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - l8.E8 - mux_1 mux_4 mux_42 mux_47 + + mult_36.a[5] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - l8.S8 - mux_17 mux_20 mux_43 mux_46 + + mult_36.b[2] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 dsp.q_o[8] + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - l1.W2 l2.W1 l4.W3 dsp.q_o[0] + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - l1.W3 l3.W5 l8.W7 dsp.q_o[16] + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - l1.W4 l3.W8 l8.W15 + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - l1.N5 l1.N6 l3.N11 dsp.q_o[9] + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - l1.N7 l2.N3 l4.N7 dsp.q_o[1] + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - l1.N8 l3.N14 l8.N7 dsp.q_o[17] + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - l1.N9 l3.N17 l8.N15 + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - l1.E10 l1.E11 l3.E20 dsp.q_o[10] + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - l1.E12 l2.E5 l4.E11 dsp.q_o[2] + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - l1.E0 l3.E23 l8.E7 dsp.q_o[18] + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - l1.E1 l3.E2 l8.E15 + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - l1.S2 l1.S3 l3.S5 dsp.q_o[11] + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - l1.S4 l2.S1 l4.S15 dsp.q_o[3] + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - l1.S5 l3.S8 l8.S7 dsp.q_o[19] + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - l1.S6 l3.S11 l8.S15 + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - l1.W7 l1.W8 l3.W14 dsp.q_o[12] + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - l1.W9 l2.W3 l4.W3 dsp.q_o[4] + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - l1.W10 l3.W17 l8.W7 dsp.q_o[20] + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - l1.W11 l3.W20 l8.W15 + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - l1.N12 l1.N0 l3.N23 dsp.q_o[13] + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - l1.N1 l2.N5 l4.N7 dsp.q_o[5] + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - l1.N2 l3.N2 l8.N7 dsp.q_o[21] + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - l1.N3 l3.N5 l8.N15 + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - l1.E4 l1.E5 l3.E8 dsp.q_o[14] + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - l1.E6 l2.E1 l4.E11 dsp.q_o[6] + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - l1.E7 l3.E11 l8.E7 dsp.q_o[22] + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - l1.E8 l3.E14 l8.E15 + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - l1.S9 l1.S10 l3.S17 dsp.q_o[15] + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - l1.S11 l2.S3 l4.S15 dsp.q_o[7] + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - l1.S12 l3.S20 l8.S7 dsp.q_o[23] + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - l1.S0 l3.S23 l8.S15 + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - l1.W1 l1.W2 l3.W2 dsp.q_o[8] + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - l1.W3 l2.W5 l4.W3 dsp.q_o[0] + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - l1.W4 l3.W5 l8.W7 dsp.q_o[16] + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - l1.W5 l3.W8 l8.W15 + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - l1.N6 l1.N7 l3.N11 dsp.q_o[9] + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - l1.N8 l2.N1 l4.N7 dsp.q_o[1] + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - l1.N9 l3.N14 l8.N7 dsp.q_o[17] + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - l1.N10 l3.N17 l8.N15 + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - l1.E11 l1.E12 l3.E20 dsp.q_o[10] + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - l1.E0 l2.E3 l4.E11 dsp.q_o[2] + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - l1.E1 l3.E23 l8.E7 dsp.q_o[18] + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - l1.E2 l3.E2 l8.E15 + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - l1.S3 l1.S4 l3.S5 dsp.q_o[11] + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - l1.S5 l2.S5 l4.S15 dsp.q_o[3] + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - l1.S6 l3.S8 l8.S7 dsp.q_o[19] + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - l1.S7 l3.S11 l8.S15 + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - l1.W8 l1.W9 l3.W14 dsp.q_o[12] + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - l1.W10 l2.W1 l4.W3 dsp.q_o[4] + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - l1.W11 l3.W17 l8.W7 dsp.q_o[20] + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - l1.W12 l3.W20 l8.W15 + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - l1.N0 l1.N1 l3.N23 dsp.q_o[13] + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - l1.N2 l2.N3 l4.N7 dsp.q_o[5] + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - l1.N3 l3.N2 l8.N7 dsp.q_o[21] + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - l1.N4 l3.N5 l8.N15 + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - l1.E5 l1.E6 l3.E8 dsp.q_o[14] + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - l1.E7 l2.E5 l4.E11 dsp.q_o[6] + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - l1.E8 l3.E11 l8.E7 dsp.q_o[22] + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - l1.E9 l3.E14 l8.E15 + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - l1.S10 l1.S11 l3.S17 dsp.q_o[15] + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - l1.S12 l2.S1 l4.S15 dsp.q_o[7] + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - l1.S0 l3.S20 l8.S7 dsp.q_o[23] + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - l1.S1 l3.S23 l8.S15 + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - l1.W2 l1.W3 l3.W2 dsp.q_o[8] + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - l1.W4 l2.W3 l4.W3 dsp.q_o[0] + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - l1.W5 l3.W5 l8.W7 dsp.q_o[16] + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 dsp.q_o[9] - - - l1.N9 l2.N5 l4.N7 dsp.q_o[1] - - - l1.N10 l3.N14 l8.N7 dsp.q_o[17] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 dsp.q_o[10] - - - l1.E1 l2.E1 l4.E11 dsp.q_o[2] - - - l1.E2 l3.E23 l8.E7 dsp.q_o[18] - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 dsp.q_o[11] - - - l1.S6 l2.S3 l4.S15 dsp.q_o[3] - - - l1.S7 l3.S8 l8.S7 dsp.q_o[19] - - - l1.S8 l3.S11 l8.S15 - - - l1.W9 l1.W10 l3.W14 dsp.q_o[12] - - - l1.W11 l2.W5 l4.W3 dsp.q_o[4] - - - l1.W12 l3.W17 l8.W7 dsp.q_o[20] - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 dsp.q_o[13] - - - l1.N3 l2.N1 l4.N7 dsp.q_o[5] - - - l1.N4 l3.N2 l8.N7 dsp.q_o[21] - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 dsp.q_o[14] - - - l1.E8 l2.E3 l4.E11 dsp.q_o[6] - - - l1.E9 l3.E11 l8.E7 dsp.q_o[22] - - - l1.E10 l3.E14 l8.E15 - - - l1.S11 l1.S12 l3.S17 dsp.q_o[15] - - - l1.S0 l2.S5 l4.S15 dsp.q_o[7] - - - l1.S1 l3.S20 l8.S7 dsp.q_o[23] - - - l1.S2 l3.S23 l8.S15 - - - l1.W3 l1.W4 l3.W2 dsp.q_o[8] + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.W5 l2.W1 l4.W3 dsp.q_o[0] - - - l1.W6 l3.W5 l8.W7 dsp.q_o[16] - - - l1.W7 l3.W8 l8.W15 - - - l1.N8 l1.N9 l3.N11 dsp.q_o[9] - - - l1.N10 l2.N3 l4.N7 dsp.q_o[1] - - - l1.N11 l3.N14 l8.N7 dsp.q_o[17] - - - l1.N12 l3.N17 l8.N15 - - - l1.E0 l1.E1 l3.E20 dsp.q_o[10] - - - l1.E2 l2.E5 l4.E11 dsp.q_o[2] - - - l1.E3 l3.E23 l8.E7 dsp.q_o[18] - - - l1.E4 l3.E2 l8.E15 - - - l1.S5 l1.S6 l3.S5 dsp.q_o[11] - - - l1.S7 l2.S1 l4.S15 dsp.q_o[3] - - - l1.S8 l3.S8 l8.S7 dsp.q_o[19] - - - l1.S9 l3.S11 l8.S15 - - - l1.W10 l1.W11 l3.W14 dsp.q_o[12] + + + + + + + + + + + + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] - - l1.W12 l2.W3 l4.W3 dsp.q_o[4] + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] - - l1.W0 l3.W17 l8.W7 dsp.q_o[20] + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] - - l1.W1 l3.W20 l8.W15 + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] - - l1.N2 l1.N3 l3.N23 dsp.q_o[13] + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] - - l1.N4 l2.N5 l4.N7 dsp.q_o[5] + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] - - l1.N5 l3.N2 l8.N7 dsp.q_o[21] + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] - - l1.N6 l3.N5 l8.N15 + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] - - l1.E7 l1.E8 l3.E8 dsp.q_o[14] + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] - - l1.E9 l2.E1 l4.E11 dsp.q_o[6] + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] - - l1.E10 l3.E11 l8.E7 dsp.q_o[22] + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] - - l1.E11 l3.E14 l8.E15 + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] - - l1.S12 l1.S0 l3.S17 dsp.q_o[15] + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] - - l1.S1 l2.S3 l4.S15 dsp.q_o[7] + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] - - l1.S2 l3.S20 l8.S7 dsp.q_o[23] + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] - - l1.S3 l3.S23 l8.S15 + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 dsp.q_o[0] OG_0 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[54] - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 dsp.q_o[8] + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[55] - l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 dsp.q_o[16] + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[56] - l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 dsp.q_o[1] + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[57] - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 dsp.q_o[9] + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[58] - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 dsp.q_o[17] OG_2 l1.N2 + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[59] - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 dsp.q_o[2] OG_2 l1.S4 + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[60] - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 dsp.q_o[10] OG_3 l1.N9 + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[61] - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 dsp.q_o[18] OG_4 + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[62] - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 dsp.q_o[3] + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[63] - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 dsp.q_o[11] + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[54] - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 dsp.q_o[19] + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[55] - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 dsp.q_o[4] + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[56] - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 dsp.q_o[12] OG_6 l1.E5 + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[57] - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 dsp.q_o[20] OG_6 l1.S4 + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[58] - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 dsp.q_o[5] OG_7 l1.N0 + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[59] - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 dsp.q_o[13] OG_0 + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 dsp.q_o[21] + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 dsp.q_o[6] + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 dsp.q_o[14] + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 dsp.q_o[22] + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 dsp.q_o[7] OG_2 l1.E0 + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 dsp.q_o[15] OG_2 l1.N10 + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 dsp.q_o[23] OG_3 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 dsp.q_o[0] OG_4 + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 dsp.q_o[8] + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 dsp.q_o[16] + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 dsp.q_o[1] + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 dsp.q_o[9] + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 dsp.q_o[17] OG_6 l1.W6 + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 dsp.q_o[2] OG_6 l1.S8 + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 dsp.q_o[10] OG_7 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 dsp.q_o[18] OG_0 + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[54] - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 dsp.q_o[3] + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[55] - l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 dsp.q_o[11] + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[56] - l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 dsp.q_o[19] + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[57] - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 dsp.q_o[4] + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[58] - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 dsp.q_o[12] OG_2 l1.S6 + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[59] - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 dsp.q_o[20] OG_2 l1.E0 + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[60] - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 dsp.q_o[5] OG_3 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[61] - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 dsp.q_o[13] OG_4 + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[62] - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 dsp.q_o[21] + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[63] - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 dsp.q_o[6] + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[54] - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 dsp.q_o[14] + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[55] - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 dsp.q_o[22] + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[56] - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 dsp.q_o[7] OG_6 l1.E2 + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[57] - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 dsp.q_o[15] OG_6 l1.W3 + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[58] - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 dsp.q_o[23] OG_7 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[59] - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 dsp.q_o[0] OG_0 + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 dsp.q_o[8] + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 dsp.q_o[16] + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 dsp.q_o[1] + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 dsp.q_o[9] + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 dsp.q_o[17] OG_2 l1.W12 + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 dsp.q_o[2] OG_2 l1.W4 + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 dsp.q_o[10] OG_3 l1.N10 + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 dsp.q_o[18] OG_4 + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 dsp.q_o[3] + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 dsp.q_o[11] + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 dsp.q_o[19] + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - dsp.q_o[17] dsp.q_o[0] dsp.q_o[8] dsp.q_o[9] + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - dsp.q_o[17] dsp.q_o[0] dsp.q_o[1] dsp.q_o[8] + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - dsp.q_o[16] dsp.q_o[0] dsp.q_o[1] dsp.q_o[9] + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[54] - - dsp.q_o[16] dsp.q_o[1] dsp.q_o[8] dsp.q_o[9] + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[55] - - dsp.q_o[19] dsp.q_o[2] dsp.q_o[10] dsp.q_o[11] + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[56] - - dsp.q_o[19] dsp.q_o[2] dsp.q_o[3] dsp.q_o[10] + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[57] - - dsp.q_o[18] dsp.q_o[2] dsp.q_o[3] dsp.q_o[11] + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[54] - - dsp.q_o[18] dsp.q_o[3] dsp.q_o[10] dsp.q_o[11] + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[55] - - dsp.q_o[21] dsp.q_o[4] dsp.q_o[12] dsp.q_o[13] + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[56] - - dsp.q_o[21] dsp.q_o[4] dsp.q_o[5] dsp.q_o[12] + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[57] - - dsp.q_o[20] dsp.q_o[4] dsp.q_o[5] dsp.q_o[13] + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[58] - - dsp.q_o[20] dsp.q_o[5] dsp.q_o[12] dsp.q_o[13] + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[59] - - dsp.q_o[23] dsp.q_o[6] dsp.q_o[14] dsp.q_o[15] + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[60] - - dsp.q_o[23] dsp.q_o[6] dsp.q_o[7] dsp.q_o[14] + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[61] - - dsp.q_o[22] dsp.q_o[6] dsp.q_o[7] dsp.q_o[15] + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[62] - - dsp.q_o[22] dsp.q_o[7] dsp.q_o[14] dsp.q_o[15] + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[63] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[54] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[55] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[56] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[57] - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[58] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[59] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - l1.W0 - mux_0 mux_5 mux_10 mux_15 + + memory.we1[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + memory.data[54] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + memory.data[60] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + memory.data[50] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + memory.data[56] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + memory.data[62] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + memory.data[52] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + memory.data[58] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + memory.we2[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + memory.data[55] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + memory.data[61] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + memory.data[51] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + memory.data[57] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + memory.data[63] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + memory.data[53] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + memory.data[59] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + memory.data[50] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + memory.data[56] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + memory.data[62] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + memory.data[52] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + memory.data[58] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + memory.we1[0] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + memory.data[54] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + memory.data[60] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + memory.data[51] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + memory.data[57] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + memory.data[63] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + memory.data[53] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + memory.data[59] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + memory.we2[0] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + memory.data[55] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + memory.data[61] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + memory.data[52] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + memory.data[58] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + memory.we1[0] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + memory.data[54] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + memory.data[60] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + memory.data[50] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - + + memory.data[56] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + memory.data[62] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + memory.data[53] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + memory.data[59] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + memory.we2[0] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + memory.data[55] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + memory.data[61] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + memory.data[51] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + memory.data[57] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + memory.data[63] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + l1.N0 - mux_16 mux_21 mux_11 mux_14 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + l1.E0 - mux_32 mux_6 mux_9 mux_31 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + l1.S0 - mux_48 mux_22 mux_27 mux_13 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - - l1.W1 - mux_64 mux_7 mux_25 mux_30 + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - - l1.N1 - mux_80 mux_23 mux_26 mux_29 + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - - l1.E1 - mux_1 mux_4 mux_42 mux_47 + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - - l1.S1 - mux_17 mux_20 mux_43 mux_46 + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - - l1.W2 - mux_33 mux_38 mux_8 mux_63 + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - - l1.N2 - mux_49 mux_54 mux_59 mux_12 + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - - l1.E2 - mux_65 mux_39 mux_24 mux_62 + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - - l1.S2 - mux_81 mux_55 mux_58 mux_28 + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - - l1.W3 - mux_2 mux_36 mux_41 mux_79 + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - - l1.N3 - mux_18 mux_52 mux_75 mux_45 + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - - l1.E3 - mux_34 mux_37 mux_40 mux_95 + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - - l1.S3 - mux_50 mux_53 mux_91 mux_44 + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - + l1.W4 - mux_66 mux_71 mux_56 mux_61 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - - l1.N4 - mux_82 mux_87 mux_57 mux_60 + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - - l1.E4 - mux_3 mux_68 mux_73 mux_78 + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - - l1.S4 - mux_19 mux_84 mux_74 mux_77 + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - - l1.W5 - mux_35 mux_69 mux_72 mux_94 + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - - l1.N5 - mux_51 mux_85 mux_90 mux_76 + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - - l1.E5 - mux_67 mux_70 mux_88 mux_93 + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - l1.S5 - mux_83 mux_86 mux_89 mux_92 + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - - l1.W6 - mux_96 mux_101 mux_106 mux_111 + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - - l1.N6 - mux_112 mux_117 mux_107 mux_110 + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - - l1.E6 - mux_0 mux_102 mux_105 mux_127 + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - - l1.S6 - mux_16 mux_118 mux_123 mux_109 + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - - l1.W7 - mux_32 mux_103 mux_121 mux_126 + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.N7 - mux_48 mux_119 mux_122 mux_125 + + + + + + + + + + + + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] - - l1.E7 - mux_97 mux_100 mux_10 mux_15 + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] - - l1.S7 - mux_113 mux_116 mux_11 mux_14 + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] - - l1.W8 - mux_1 mux_6 mux_104 mux_31 + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] - - l1.N8 - mux_17 mux_22 mux_27 mux_108 + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] - - l1.E8 - mux_33 mux_7 mux_120 mux_30 + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] - - l1.S8 - mux_49 mux_23 mux_26 mux_124 + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] - - l2.W0 - mux_98 mux_4 mux_9 mux_47 + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] - - l2.N0 - mux_114 mux_20 mux_43 mux_13 + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] - - l2.E0 - mux_2 mux_5 mux_8 mux_63 + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] - - l2.S0 - mux_18 mux_21 mux_59 mux_12 + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] - - l2.W2 - mux_34 mux_39 mux_24 mux_29 + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] - - l2.N2 - mux_50 mux_55 mux_25 mux_28 + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] - - l2.E2 - mux_99 mux_36 mux_41 mux_46 + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] - - l2.S2 - mux_115 mux_52 mux_42 mux_45 + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] - - l2.W4 - mux_3 mux_37 mux_40 mux_62 + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] - - l2.N4 - mux_19 mux_53 mux_58 mux_44 + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[44] - - l2.E4 - mux_35 mux_38 mux_56 mux_61 + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[45] - - l2.S4 - mux_51 mux_54 mux_57 mux_60 + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[46] - - l3.W0 - mux_64 mux_69 mux_74 mux_79 + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[47] - - l3.N0 - mux_80 mux_85 mux_75 mux_78 + + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[48] - - l3.E0 - mux_96 mux_70 mux_73 mux_95 + + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[49] - - l3.S0 - mux_112 mux_86 mux_91 mux_77 + + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[50] - - l3.W3 - mux_0 mux_71 mux_89 mux_94 + + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[51] - - l3.N3 - mux_16 mux_87 mux_90 mux_93 + + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[52] - - l3.E3 - mux_65 mux_68 mux_106 mux_111 + + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[53] - - l3.S3 - mux_81 mux_84 mux_107 mux_110 + + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[44] - - l3.W6 - mux_97 mux_102 mux_72 mux_127 + + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[45] - - l3.N6 - mux_113 mux_118 mux_123 mux_76 + + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[46] - - l3.E6 - mux_1 mux_103 mux_88 mux_126 + + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[47] - - l3.S6 - mux_17 mux_119 mux_122 mux_92 + + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[48] - - l3.W9 - mux_66 mux_100 mux_105 mux_15 + + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[49] - - l3.N9 - mux_82 mux_116 mux_11 mux_109 + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - - l3.E9 - mux_98 mux_101 mux_104 mux_31 + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - - l3.S9 - mux_114 mux_117 mux_27 mux_108 + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - - l3.W12 - mux_2 mux_7 mux_120 mux_125 + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - - l3.N12 - mux_18 mux_23 mux_121 mux_124 + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - - l3.E12 - mux_67 mux_4 mux_9 mux_14 + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - - l3.S12 - mux_83 mux_20 mux_10 mux_13 + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - - l3.W15 - mux_99 mux_5 mux_8 mux_30 + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - - l3.N15 - mux_115 mux_21 mux_26 mux_12 + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - - l3.E15 - mux_3 mux_6 mux_24 mux_29 + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - - l3.S15 - mux_19 mux_22 mux_25 mux_28 + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - - l3.W18 - mux_32 mux_37 mux_42 mux_47 + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - - l3.N18 - mux_48 mux_53 mux_43 mux_46 + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - - l3.E18 - mux_64 mux_38 mux_41 mux_63 + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - - l3.S18 - mux_80 mux_54 mux_59 mux_45 + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - - l3.W21 - mux_96 mux_39 mux_57 mux_62 + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - - l3.N21 - mux_112 mux_55 mux_58 mux_61 + + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[44] - - l3.E21 - mux_33 mux_36 mux_74 mux_79 + + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[45] - - l3.S21 - mux_49 mux_52 mux_75 mux_78 + + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[46] - - l4.W0 - mux_65 mux_70 mux_40 mux_95 + + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[47] - - l4.N0 - mux_81 mux_86 mux_91 mux_44 + + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[48] - - l4.E0 - mux_97 mux_71 mux_56 mux_94 + + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[49] - - l4.S0 - mux_113 mux_87 mux_90 mux_60 + + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[50] - - l4.W4 - mux_34 mux_68 mux_73 mux_111 + + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[51] - - l4.N4 - mux_50 mux_84 mux_107 mux_77 + + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[52] - - l4.E4 - mux_66 mux_69 mux_72 mux_127 + + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[53] - - l4.S4 - mux_82 mux_85 mux_123 mux_76 + + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[44] - - l4.W8 - mux_98 mux_103 mux_88 mux_93 + + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[45] - - l4.N8 - mux_114 mux_119 mux_89 mux_92 + + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[46] - - l4.E8 - mux_35 mux_100 mux_105 mux_110 + + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[47] - - l4.S8 - mux_51 mux_116 mux_106 mux_109 + + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[48] - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[49] - - l4.N12 - mux_83 mux_117 mux_122 mux_108 + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - - l4.E12 - mux_99 mux_102 mux_120 mux_125 + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - - l4.S12 - mux_115 mux_118 mux_121 mux_124 + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - - l8.W0 - mux_0 mux_5 mux_10 mux_15 + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - - l8.N0 - mux_16 mux_21 mux_11 mux_14 + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - - l8.E0 - mux_32 mux_6 mux_9 mux_31 + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - - l8.S0 - mux_48 mux_22 mux_27 mux_13 + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - - l8.W8 - mux_64 mux_7 mux_25 mux_30 + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - - l8.N8 - mux_80 mux_23 mux_26 mux_29 + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - - l8.E8 - mux_1 mux_4 mux_42 mux_47 + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - - l8.S8 - mux_17 mux_20 mux_43 mux_46 + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - l1.W9 - l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - l1.N9 - l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - l1.E9 - l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - l1.S9 - l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - l1.W10 - l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[44] - - l1.N10 - l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[45] - - l1.E10 - l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[46] - - l1.S10 - l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[47] - - l1.W11 - l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[44] - - l1.N11 - l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[45] - - l1.E11 - l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[46] - - l1.S11 - l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[47] - - l1.W12 - l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[48] - - l1.N12 - l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[49] - - l1.E12 - l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[50] - - l1.S12 - l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[51] - - dsp.a[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[52] - - dsp.a[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[53] - - dsp.a[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[44] - - dsp.a[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[45] - - dsp.a[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[46] - - dsp.a[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[47] - - dsp.a[6] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[48] - - dsp.a[7] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[49] - - dsp.a[8] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - dsp.a[9] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - dsp.a[10] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - dsp.a[11] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - dsp.b[0] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + + memory.addr1[12] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - dsp.b[1] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + memory.data[40] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - dsp.b[2] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + memory.data[46] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - dsp.b[3] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + memory.addr1[14] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - dsp.b[4] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + memory.data[42] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - dsp.b[5] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + memory.data[48] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - dsp.b[6] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + memory.addr2[13] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - dsp.b[7] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + memory.data[44] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - dsp.b[8] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + memory.addr1[13] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - dsp.b[9] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + memory.data[41] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - dsp.lclk[0] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + memory.data[47] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - dsp.lreset[0] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + memory.addr2[12] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - dsp.a[24] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + memory.data[43] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - dsp.a[25] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + memory.data[49] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - dsp.a[26] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + memory.addr2[14] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - dsp.a[27] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + memory.data[45] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - dsp.a[28] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + memory.addr1[14] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - dsp.a[29] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + memory.data[42] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - dsp.a[30] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + memory.data[48] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - dsp.a[31] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + memory.addr2[13] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - dsp.a[32] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + memory.data[44] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - dsp.a[33] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + memory.addr1[12] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - dsp.a[34] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + memory.data[40] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - dsp.a[35] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + memory.data[46] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - dsp.b[20] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + memory.addr2[12] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - dsp.b[21] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + memory.data[43] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - dsp.b[22] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + memory.data[49] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - dsp.b[23] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + memory.addr2[14] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - dsp.b[24] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + memory.data[45] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - dsp.b[25] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + memory.addr1[13] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - dsp.b[26] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + memory.data[41] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - dsp.b[27] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + memory.data[47] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - dsp.b[28] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + memory.addr2[13] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - dsp.b[29] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + memory.data[44] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - dsp.a[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + memory.addr1[12] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - dsp.a[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + memory.data[40] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - dsp.a[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + memory.data[46] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - dsp.a[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + memory.addr1[14] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - dsp.a[4] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + memory.data[42] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - dsp.a[5] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + memory.data[48] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - dsp.a[6] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + memory.addr2[14] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - dsp.a[7] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + memory.data[45] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - dsp.a[8] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + memory.addr1[13] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - dsp.a[9] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + memory.data[41] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - dsp.a[10] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + memory.data[47] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - dsp.a[11] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + memory.addr2[12] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - dsp.b[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + memory.data[43] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - dsp.b[1] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + memory.data[49] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 dsp.q_o[32] + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - l1.W2 l2.W1 l4.W3 dsp.q_o[24] + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - l1.W3 l3.W5 l8.W7 dsp.q_o[40] + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - l1.W4 l3.W8 l8.W15 + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - l1.N5 l1.N6 l3.N11 dsp.q_o[33] + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - l1.N7 l2.N3 l4.N7 dsp.q_o[25] + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - l1.N8 l3.N14 l8.N7 dsp.q_o[41] + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - l1.N9 l3.N17 l8.N15 + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - l1.E10 l1.E11 l3.E20 dsp.q_o[34] + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - l1.E12 l2.E5 l4.E11 dsp.q_o[26] + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - l1.E0 l3.E23 l8.E7 dsp.q_o[42] + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - l1.E1 l3.E2 l8.E15 + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - l1.S2 l1.S3 l3.S5 dsp.q_o[35] + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - l1.S4 l2.S1 l4.S15 dsp.q_o[27] + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - l1.S5 l3.S8 l8.S7 dsp.q_o[43] + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - l1.S6 l3.S11 l8.S15 + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - l1.W7 l1.W8 l3.W14 dsp.q_o[36] + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - l1.W9 l2.W3 l4.W3 dsp.q_o[28] + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - l1.W10 l3.W17 l8.W7 dsp.q_o[24] + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - l1.W11 l3.W20 l8.W15 + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - l1.N12 l1.N0 l3.N23 dsp.q_o[37] + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - l1.N1 l2.N5 l4.N7 dsp.q_o[29] + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - l1.N2 l3.N2 l8.N7 dsp.q_o[25] + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - l1.N3 l3.N5 l8.N15 + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - l1.E4 l1.E5 l3.E8 dsp.q_o[38] + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - l1.E6 l2.E1 l4.E11 dsp.q_o[30] + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - l1.E7 l3.E11 l8.E7 dsp.q_o[26] + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - l1.E8 l3.E14 l8.E15 + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - l1.S9 l1.S10 l3.S17 dsp.q_o[39] + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - l1.S11 l2.S3 l4.S15 dsp.q_o[31] + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - l1.S12 l3.S20 l8.S7 dsp.q_o[27] + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - l1.S0 l3.S23 l8.S15 + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - l1.W1 l1.W2 l3.W2 dsp.q_o[32] + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - l1.W3 l2.W5 l4.W3 dsp.q_o[24] + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - l1.W4 l3.W5 l8.W7 dsp.q_o[40] + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - l1.W5 l3.W8 l8.W15 - - - l1.N6 l1.N7 l3.N11 dsp.q_o[33] - - - l1.N8 l2.N1 l4.N7 dsp.q_o[25] - - - l1.N9 l3.N14 l8.N7 dsp.q_o[41] - - - l1.N10 l3.N17 l8.N15 - - - l1.E11 l1.E12 l3.E20 dsp.q_o[34] - - - l1.E0 l2.E3 l4.E11 dsp.q_o[26] - - - l1.E1 l3.E23 l8.E7 dsp.q_o[42] - - - l1.E2 l3.E2 l8.E15 - - - l1.S3 l1.S4 l3.S5 dsp.q_o[35] - - - l1.S5 l2.S5 l4.S15 dsp.q_o[27] - - - l1.S6 l3.S8 l8.S7 dsp.q_o[43] - - - l1.S7 l3.S11 l8.S15 - - - l1.W8 l1.W9 l3.W14 dsp.q_o[36] - - - l1.W10 l2.W1 l4.W3 dsp.q_o[28] - - - l1.W11 l3.W17 l8.W7 dsp.q_o[24] - - - l1.W12 l3.W20 l8.W15 - - - l1.N0 l1.N1 l3.N23 dsp.q_o[37] - - - l1.N2 l2.N3 l4.N7 dsp.q_o[29] - - - l1.N3 l3.N2 l8.N7 dsp.q_o[25] - - - l1.N4 l3.N5 l8.N15 - - - l1.E5 l1.E6 l3.E8 dsp.q_o[38] - - - l1.E7 l2.E5 l4.E11 dsp.q_o[30] - - - l1.E8 l3.E11 l8.E7 dsp.q_o[26] - - - l1.E9 l3.E14 l8.E15 - - - l1.S10 l1.S11 l3.S17 dsp.q_o[39] - - - l1.S12 l2.S1 l4.S15 dsp.q_o[31] - - - l1.S0 l3.S20 l8.S7 dsp.q_o[27] - - - l1.S1 l3.S23 l8.S15 - - - l1.W2 l1.W3 l3.W2 dsp.q_o[32] - - - l1.W4 l2.W3 l4.W3 dsp.q_o[24] - - - l1.W5 l3.W5 l8.W7 dsp.q_o[40] - - - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 dsp.q_o[33] - - - l1.N9 l2.N5 l4.N7 dsp.q_o[25] - - - l1.N10 l3.N14 l8.N7 dsp.q_o[41] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 dsp.q_o[34] - - - l1.E1 l2.E1 l4.E11 dsp.q_o[26] - - - l1.E2 l3.E23 l8.E7 dsp.q_o[42] - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 dsp.q_o[35] - - - l1.S6 l2.S3 l4.S15 dsp.q_o[27] - - - l1.S7 l3.S8 l8.S7 dsp.q_o[43] - - - l1.S8 l3.S11 l8.S15 + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - - l1.W9 l1.W10 l3.W14 dsp.q_o[36] + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - - l1.W11 l2.W5 l4.W3 dsp.q_o[28] + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - - l1.W12 l3.W17 l8.W7 dsp.q_o[24] + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - - l1.W0 l3.W20 l8.W15 + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - - l1.N1 l1.N2 l3.N23 dsp.q_o[37] + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - - l1.N3 l2.N1 l4.N7 dsp.q_o[29] + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - - l1.N4 l3.N2 l8.N7 dsp.q_o[25] + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - - l1.N5 l3.N5 l8.N15 + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - - l1.E6 l1.E7 l3.E8 dsp.q_o[38] + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - - l1.E8 l2.E3 l4.E11 dsp.q_o[30] + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - - l1.E9 l3.E11 l8.E7 dsp.q_o[26] + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - - l1.E10 l3.E14 l8.E15 + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - - l1.S11 l1.S12 l3.S17 dsp.q_o[39] + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - - l1.S0 l2.S5 l4.S15 dsp.q_o[31] + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - - l1.S1 l3.S20 l8.S7 dsp.q_o[27] + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - - l1.S2 l3.S23 l8.S15 + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - - l1.W3 l1.W4 l3.W2 dsp.q_o[32] + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - - l1.W5 l2.W1 l4.W3 dsp.q_o[24] + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - - l1.W6 l3.W5 l8.W7 dsp.q_o[40] + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - - l1.W7 l3.W8 l8.W15 + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - - l1.N8 l1.N9 l3.N11 dsp.q_o[33] + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - - l1.N10 l2.N3 l4.N7 dsp.q_o[25] + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - - l1.N11 l3.N14 l8.N7 dsp.q_o[41] + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - - l1.N12 l3.N17 l8.N15 + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - - l1.E0 l1.E1 l3.E20 dsp.q_o[34] + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - - l1.E2 l2.E5 l4.E11 dsp.q_o[26] + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - l1.E3 l3.E23 l8.E7 dsp.q_o[42] + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - - l1.E4 l3.E2 l8.E15 + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - - l1.S5 l1.S6 l3.S5 dsp.q_o[35] + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - - l1.S7 l2.S1 l4.S15 dsp.q_o[27] + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - - l1.S8 l3.S8 l8.S7 dsp.q_o[43] + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - - l1.S9 l3.S11 l8.S15 + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.W10 l1.W11 l3.W14 dsp.q_o[36] + + + + + + + + + + + + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] - - l1.W12 l2.W3 l4.W3 dsp.q_o[28] + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] - - l1.W0 l3.W17 l8.W7 dsp.q_o[24] + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] - - l1.W1 l3.W20 l8.W15 + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] - - l1.N2 l1.N3 l3.N23 dsp.q_o[37] + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] - - l1.N4 l2.N5 l4.N7 dsp.q_o[29] + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] - - l1.N5 l3.N2 l8.N7 dsp.q_o[25] + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] - - l1.N6 l3.N5 l8.N15 + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] - - l1.E7 l1.E8 l3.E8 dsp.q_o[38] + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] - - l1.E9 l2.E1 l4.E11 dsp.q_o[30] + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] - - l1.E10 l3.E11 l8.E7 dsp.q_o[26] + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] - - l1.E11 l3.E14 l8.E15 + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] - - l1.S12 l1.S0 l3.S17 dsp.q_o[39] + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] - - l1.S1 l2.S3 l4.S15 dsp.q_o[31] + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] - - l1.S2 l3.S20 l8.S7 dsp.q_o[27] + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] - - l1.S3 l3.S23 l8.S15 + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 dsp.q_o[24] OG_0 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[33] - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 dsp.q_o[32] + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[34] - l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 dsp.q_o[40] + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[35] - l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 dsp.q_o[25] + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[36] - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 dsp.q_o[33] + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[37] - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 dsp.q_o[41] OG_2 l1.N2 + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[38] - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 dsp.q_o[26] OG_2 l1.S4 + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[39] - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 dsp.q_o[34] OG_3 l1.N9 + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[40] - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 dsp.q_o[42] OG_4 + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[41] - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 dsp.q_o[27] + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[42] - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 dsp.q_o[35] + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[43] - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 dsp.q_o[43] + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[33] - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 dsp.q_o[28] + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[34] - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 dsp.q_o[36] OG_6 l1.E5 + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[35] - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 dsp.q_o[24] OG_6 l1.S4 + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[36] - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 dsp.q_o[29] OG_7 l1.N0 + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[37] - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 dsp.q_o[37] OG_0 + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 dsp.q_o[25] + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 dsp.q_o[30] + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 dsp.q_o[38] + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 dsp.q_o[26] + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 dsp.q_o[31] OG_2 l1.E0 + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 dsp.q_o[39] OG_2 l1.N10 + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 dsp.q_o[27] OG_3 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 dsp.q_o[24] OG_4 + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 dsp.q_o[32] + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 dsp.q_o[40] + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 dsp.q_o[25] + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 dsp.q_o[33] + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 dsp.q_o[41] OG_6 l1.W6 + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 dsp.q_o[26] OG_6 l1.S8 + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 dsp.q_o[34] OG_7 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 dsp.q_o[42] OG_0 + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[33] - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 dsp.q_o[27] + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[34] - l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 dsp.q_o[35] + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[35] - l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 dsp.q_o[43] + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[36] - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 dsp.q_o[28] + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[37] - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 dsp.q_o[36] OG_2 l1.S6 + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[38] - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 dsp.q_o[24] OG_2 l1.E0 + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[39] - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 dsp.q_o[29] OG_3 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[40] - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 dsp.q_o[37] OG_4 + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[41] - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 dsp.q_o[25] + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[42] - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 dsp.q_o[30] + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[43] - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 dsp.q_o[38] + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[33] - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 dsp.q_o[26] + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[34] - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 dsp.q_o[31] OG_6 l1.E2 + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[35] - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 dsp.q_o[39] OG_6 l1.W3 + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[36] - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 dsp.q_o[27] OG_7 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[37] - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 dsp.q_o[24] OG_0 + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 dsp.q_o[32] + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 dsp.q_o[40] + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 dsp.q_o[25] + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 dsp.q_o[33] + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 dsp.q_o[41] OG_2 l1.W12 + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 dsp.q_o[26] OG_2 l1.W4 + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 dsp.q_o[34] OG_3 l1.N10 + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 dsp.q_o[42] OG_4 + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 dsp.q_o[27] + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 dsp.q_o[35] + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 dsp.q_o[43] - - - dsp.q_o[41] dsp.q_o[24] dsp.q_o[32] dsp.q_o[33] - - - dsp.q_o[41] dsp.q_o[24] dsp.q_o[25] dsp.q_o[32] - - - dsp.q_o[40] dsp.q_o[24] dsp.q_o[25] dsp.q_o[33] - - - dsp.q_o[40] dsp.q_o[25] dsp.q_o[32] dsp.q_o[33] - - - dsp.q_o[43] dsp.q_o[26] dsp.q_o[34] dsp.q_o[35] - - - dsp.q_o[43] dsp.q_o[26] dsp.q_o[27] dsp.q_o[34] - - - dsp.q_o[42] dsp.q_o[26] dsp.q_o[27] dsp.q_o[35] - - - dsp.q_o[42] dsp.q_o[27] dsp.q_o[34] dsp.q_o[35] - - - dsp.q_o[25] dsp.q_o[28] dsp.q_o[36] dsp.q_o[37] - - - dsp.q_o[25] dsp.q_o[28] dsp.q_o[29] dsp.q_o[36] - - - dsp.q_o[24] dsp.q_o[28] dsp.q_o[29] dsp.q_o[37] - - - dsp.q_o[24] dsp.q_o[29] dsp.q_o[36] dsp.q_o[37] - - - dsp.q_o[27] dsp.q_o[30] dsp.q_o[38] dsp.q_o[39] - - - dsp.q_o[27] dsp.q_o[30] dsp.q_o[31] dsp.q_o[38] - - - dsp.q_o[26] dsp.q_o[30] dsp.q_o[31] dsp.q_o[39] - - - dsp.q_o[26] dsp.q_o[31] dsp.q_o[38] dsp.q_o[39] - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - - - l1.W0 - mux_0 mux_5 mux_10 mux_15 - - - l1.N0 - mux_16 mux_21 mux_11 mux_14 - - - l1.E0 - mux_32 mux_6 mux_9 mux_31 - - - l1.S0 - mux_48 mux_22 mux_27 mux_13 - - - l1.W1 - mux_64 mux_7 mux_25 mux_30 - - - l1.N1 - mux_80 mux_23 mux_26 mux_29 - - - l1.E1 - mux_1 mux_4 mux_42 mux_47 - - - l1.S1 - mux_17 mux_20 mux_43 mux_46 - - - l1.W2 - mux_33 mux_38 mux_8 mux_63 - - - l1.N2 - mux_49 mux_54 mux_59 mux_12 - - - l1.E2 - mux_65 mux_39 mux_24 mux_62 - - - l1.S2 - mux_81 mux_55 mux_58 mux_28 - - - l1.W3 - mux_2 mux_36 mux_41 mux_79 - - - l1.N3 - mux_18 mux_52 mux_75 mux_45 - - - l1.E3 - mux_34 mux_37 mux_40 mux_95 - - - l1.S3 - mux_50 mux_53 mux_91 mux_44 - - - l1.W4 - mux_66 mux_71 mux_56 mux_61 - - - l1.N4 - mux_82 mux_87 mux_57 mux_60 - - - l1.E4 - mux_3 mux_68 mux_73 mux_78 - - - l1.S4 - mux_19 mux_84 mux_74 mux_77 - - - l1.W5 - mux_35 mux_69 mux_72 mux_94 + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - l1.N5 - mux_51 mux_85 mux_90 mux_76 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - l1.E5 - mux_67 mux_70 mux_88 mux_93 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - l1.S5 - mux_83 mux_86 mux_89 mux_92 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - l1.W6 - mux_96 mux_101 mux_106 mux_111 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - l1.N6 - mux_112 mux_117 mux_107 mux_110 + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[33] - - l1.E6 - mux_0 mux_102 mux_105 mux_127 + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[34] - - l1.S6 - mux_16 mux_118 mux_123 mux_109 + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[35] - - l1.W7 - mux_32 mux_103 mux_121 mux_126 + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[36] - - l1.N7 - mux_48 mux_119 mux_122 mux_125 + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[33] - - l1.E7 - mux_97 mux_100 mux_10 mux_15 + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[34] - - l1.S7 - mux_113 mux_116 mux_11 mux_14 + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[35] - - l1.W8 - mux_1 mux_6 mux_104 mux_31 + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[36] - - l1.N8 - mux_17 mux_22 mux_27 mux_108 + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[37] - - l1.E8 - mux_33 mux_7 mux_120 mux_30 + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[38] - - l1.S8 - mux_49 mux_23 mux_26 mux_124 + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[39] - - l2.W0 - mux_98 mux_4 mux_9 mux_47 - - - l2.N0 - mux_114 mux_20 mux_43 mux_13 - - - l2.E0 - mux_2 mux_5 mux_8 mux_63 - - - l2.S0 - mux_18 mux_21 mux_59 mux_12 - - - l2.W2 - mux_34 mux_39 mux_24 mux_29 - - - l2.N2 - mux_50 mux_55 mux_25 mux_28 - - - l2.E2 - mux_99 mux_36 mux_41 mux_46 - - - l2.S2 - mux_115 mux_52 mux_42 mux_45 - - - l2.W4 - mux_3 mux_37 mux_40 mux_62 - - - l2.N4 - mux_19 mux_53 mux_58 mux_44 - - - l2.E4 - mux_35 mux_38 mux_56 mux_61 - - - l2.S4 - mux_51 mux_54 mux_57 mux_60 - - - l3.W0 - mux_64 mux_69 mux_74 mux_79 - - - l3.N0 - mux_80 mux_85 mux_75 mux_78 - - - l3.E0 - mux_96 mux_70 mux_73 mux_95 - - - l3.S0 - mux_112 mux_86 mux_91 mux_77 - - - l3.W3 - mux_0 mux_71 mux_89 mux_94 - - - l3.N3 - mux_16 mux_87 mux_90 mux_93 - - - l3.E3 - mux_65 mux_68 mux_106 mux_111 - - - l3.S3 - mux_81 mux_84 mux_107 mux_110 - - - l3.W6 - mux_97 mux_102 mux_72 mux_127 - - - l3.N6 - mux_113 mux_118 mux_123 mux_76 - - - l3.E6 - mux_1 mux_103 mux_88 mux_126 - - - l3.S6 - mux_17 mux_119 mux_122 mux_92 - - - l3.W9 - mux_66 mux_100 mux_105 mux_15 - - - l3.N9 - mux_82 mux_116 mux_11 mux_109 - - - l3.E9 - mux_98 mux_101 mux_104 mux_31 - - - l3.S9 - mux_114 mux_117 mux_27 mux_108 - - - l3.W12 - mux_2 mux_7 mux_120 mux_125 - - - l3.N12 - mux_18 mux_23 mux_121 mux_124 - - - l3.E12 - mux_67 mux_4 mux_9 mux_14 - - - l3.S12 - mux_83 mux_20 mux_10 mux_13 - - - l3.W15 - mux_99 mux_5 mux_8 mux_30 - - - l3.N15 - mux_115 mux_21 mux_26 mux_12 - - - l3.E15 - mux_3 mux_6 mux_24 mux_29 - - - l3.S15 - mux_19 mux_22 mux_25 mux_28 - - - l3.W18 - mux_32 mux_37 mux_42 mux_47 - - - l3.N18 - mux_48 mux_53 mux_43 mux_46 - - - l3.E18 - mux_64 mux_38 mux_41 mux_63 - - - l3.S18 - mux_80 mux_54 mux_59 mux_45 - - - l3.W21 - mux_96 mux_39 mux_57 mux_62 - - - l3.N21 - mux_112 mux_55 mux_58 mux_61 - - - l3.E21 - mux_33 mux_36 mux_74 mux_79 - - - l3.S21 - mux_49 mux_52 mux_75 mux_78 - - - l4.W0 - mux_65 mux_70 mux_40 mux_95 + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[40] - - l4.N0 - mux_81 mux_86 mux_91 mux_44 + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[41] - - l4.E0 - mux_97 mux_71 mux_56 mux_94 + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[42] - - l4.S0 - mux_113 mux_87 mux_90 mux_60 + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[43] - - l4.W4 - mux_34 mux_68 mux_73 mux_111 + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[33] - - l4.N4 - mux_50 mux_84 mux_107 mux_77 + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[34] - - l4.E4 - mux_66 mux_69 mux_72 mux_127 + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[35] - - l4.S4 - mux_82 mux_85 mux_123 mux_76 + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[36] - - l4.W8 - mux_98 mux_103 mux_88 mux_93 + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[37] - - l4.N8 - mux_114 mux_119 mux_89 mux_92 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - l4.E8 - mux_35 mux_100 mux_105 mux_110 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - l4.S8 - mux_51 mux_116 mux_106 mux_109 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - l4.N12 - mux_83 mux_117 mux_122 mux_108 - - - l4.E12 - mux_99 mux_102 mux_120 mux_125 - - - l4.S12 - mux_115 mux_118 mux_121 mux_124 - - - l8.W0 - mux_0 mux_5 mux_10 mux_15 - - - l8.N0 - mux_16 mux_21 mux_11 mux_14 - - - l8.E0 - mux_32 mux_6 mux_9 mux_31 - - - l8.S0 - mux_48 mux_22 mux_27 mux_13 - - - l8.W8 - mux_64 mux_7 mux_25 mux_30 - - - l8.N8 - mux_80 mux_23 mux_26 mux_29 - - - l8.E8 - mux_1 mux_4 mux_42 mux_47 - - - l8.S8 - mux_17 mux_20 mux_43 mux_46 - - - l1.W9 - l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.N9 - l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.E9 - l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.S9 - l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.W10 - l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.N10 - l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.E10 - l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.S10 - l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.W11 - l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.N11 - l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.E11 - l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.S11 - l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.W12 - l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.N12 - l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.E12 - l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.S12 - l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - dsp.a[36] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - dsp.a[37] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 - - - dsp.a[38] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - dsp.a[39] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - dsp.a[40] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - dsp.a[41] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - dsp.a[42] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - dsp.a[43] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - dsp.a[44] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 - - - dsp.a[45] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 - - - dsp.a[46] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 - - - dsp.a[47] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 - - - dsp.b[30] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + + memory.addr1[9] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - dsp.b[31] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + memory.data[30] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - dsp.b[32] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + memory.data[36] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - dsp.b[33] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + memory.addr1[11] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - dsp.b[34] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + memory.data[32] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - dsp.b[35] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + memory.data[38] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - dsp.b[36] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + memory.addr2[10] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - dsp.b[37] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + memory.data[34] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - dsp.b[38] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + memory.addr1[10] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - dsp.b[39] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + memory.data[31] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - dsp.a[12] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + memory.data[37] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - dsp.a[13] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + memory.addr2[9] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - dsp.a[14] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + memory.data[33] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - dsp.a[15] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + memory.data[39] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - dsp.a[16] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + memory.addr2[11] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - dsp.a[17] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + memory.data[35] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - dsp.a[18] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + memory.addr1[11] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - dsp.a[19] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + memory.data[32] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - dsp.a[20] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + memory.data[38] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - dsp.a[21] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + memory.addr2[10] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - dsp.a[22] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + memory.data[34] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - dsp.a[23] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + memory.addr1[9] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - dsp.b[10] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + memory.data[30] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - dsp.b[11] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + memory.data[36] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - dsp.b[12] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + memory.addr2[9] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - dsp.b[13] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + memory.data[33] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - dsp.b[14] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + memory.data[39] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - dsp.b[15] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + memory.addr2[11] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - dsp.b[16] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + memory.data[35] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - dsp.b[17] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + memory.addr1[10] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - dsp.b[18] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + memory.data[31] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - dsp.b[19] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + memory.data[37] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - dsp.a[36] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + memory.addr2[10] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - dsp.a[37] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + memory.data[34] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - dsp.a[38] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + memory.addr1[9] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - dsp.a[39] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + memory.data[30] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - dsp.a[40] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + memory.data[36] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - dsp.a[41] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + memory.addr1[11] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - dsp.a[42] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + memory.data[32] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - dsp.a[43] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + memory.data[38] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - dsp.a[44] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + memory.addr2[11] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - dsp.a[45] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + memory.data[35] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - dsp.a[46] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + memory.addr1[10] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - dsp.a[47] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + memory.data[31] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - dsp.b[30] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + memory.data[37] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - dsp.b[31] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + memory.addr2[9] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - dsp.b[32] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + memory.data[33] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - dsp.b[33] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + memory.data[39] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 ram9k.q_o[8] + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - l1.W2 l2.W1 l4.W3 ram9k.q_o[0] + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - l1.W3 l3.W5 l8.W7 ram9k.q_o[16] + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - l1.W4 l3.W8 l8.W15 + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - l1.N5 l1.N6 l3.N11 ram9k.q_o[9] + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - l1.N7 l2.N3 l4.N7 ram9k.q_o[1] + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - l1.N8 l3.N14 l8.N7 ram9k.q_o[17] + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - l1.N9 l3.N17 l8.N15 + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - l1.E10 l1.E11 l3.E20 ram9k.q_o[10] + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - l1.E12 l2.E5 l4.E11 ram9k.q_o[2] + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - l1.E0 l3.E23 l8.E7 ram9k.q_o[18] + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - l1.E1 l3.E2 l8.E15 + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - l1.S2 l1.S3 l3.S5 ram9k.q_o[11] + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - l1.S4 l2.S1 l4.S15 ram9k.q_o[3] + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - l1.S5 l3.S8 l8.S7 ram9k.q_o[19] + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - l1.S6 l3.S11 l8.S15 + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - l1.W7 l1.W8 l3.W14 ram9k.q_o[12] + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - l1.W9 l2.W3 l4.W3 ram9k.q_o[4] + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - l1.W10 l3.W17 l8.W7 ram9k.q_o[20] + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - l1.W11 l3.W20 l8.W15 + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - l1.N12 l1.N0 l3.N23 ram9k.q_o[13] + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - l1.N1 l2.N5 l4.N7 ram9k.q_o[5] + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - l1.N2 l3.N2 l8.N7 ram9k.q_o[21] + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - l1.N3 l3.N5 l8.N15 + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - l1.E4 l1.E5 l3.E8 ram9k.q_o[14] + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - l1.E6 l2.E1 l4.E11 ram9k.q_o[6] + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - l1.E7 l3.E11 l8.E7 ram9k.q_o[22] + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - l1.E8 l3.E14 l8.E15 + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - l1.S9 l1.S10 l3.S17 ram9k.q_o[15] + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - l1.S11 l2.S3 l4.S15 ram9k.q_o[7] + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - l1.S12 l3.S20 l8.S7 ram9k.q_o[23] + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - l1.S0 l3.S23 l8.S15 + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - l1.W1 l1.W2 l3.W2 ram9k.q_o[8] + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - l1.W3 l2.W5 l4.W3 ram9k.q_o[0] + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - l1.W4 l3.W5 l8.W7 ram9k.q_o[16] + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - l1.W5 l3.W8 l8.W15 + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - l1.N6 l1.N7 l3.N11 ram9k.q_o[9] + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - l1.N8 l2.N1 l4.N7 ram9k.q_o[1] + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - l1.N9 l3.N14 l8.N7 ram9k.q_o[17] + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - l1.N10 l3.N17 l8.N15 + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - l1.E11 l1.E12 l3.E20 ram9k.q_o[10] + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - l1.E0 l2.E3 l4.E11 ram9k.q_o[2] + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - l1.E1 l3.E23 l8.E7 ram9k.q_o[18] + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - l1.E2 l3.E2 l8.E15 + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - l1.S3 l1.S4 l3.S5 ram9k.q_o[11] + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - l1.S5 l2.S5 l4.S15 ram9k.q_o[3] + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - l1.S6 l3.S8 l8.S7 ram9k.q_o[19] + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - l1.S7 l3.S11 l8.S15 + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - l1.W8 l1.W9 l3.W14 ram9k.q_o[12] + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - l1.W10 l2.W1 l4.W3 ram9k.q_o[4] + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - l1.W11 l3.W17 l8.W7 ram9k.q_o[20] + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - l1.W12 l3.W20 l8.W15 + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - l1.N0 l1.N1 l3.N23 ram9k.q_o[13] + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - l1.N2 l2.N3 l4.N7 ram9k.q_o[5] + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - l1.N3 l3.N2 l8.N7 ram9k.q_o[21] + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - l1.N4 l3.N5 l8.N15 + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - l1.E5 l1.E6 l3.E8 ram9k.q_o[14] + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - l1.E7 l2.E5 l4.E11 ram9k.q_o[6] + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - l1.E8 l3.E11 l8.E7 ram9k.q_o[22] + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - l1.E9 l3.E14 l8.E15 + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - l1.S10 l1.S11 l3.S17 ram9k.q_o[15] + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - l1.S12 l2.S1 l4.S15 ram9k.q_o[7] + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - l1.S0 l3.S20 l8.S7 ram9k.q_o[23] + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - l1.S1 l3.S23 l8.S15 + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - l1.W2 l1.W3 l3.W2 ram9k.q_o[8] + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - l1.W4 l2.W3 l4.W3 ram9k.q_o[0] + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - l1.W5 l3.W5 l8.W7 ram9k.q_o[16] + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 ram9k.q_o[9] - - - l1.N9 l2.N5 l4.N7 ram9k.q_o[1] - - - l1.N10 l3.N14 l8.N7 ram9k.q_o[17] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 ram9k.q_o[10] - - - l1.E1 l2.E1 l4.E11 ram9k.q_o[2] - - - l1.E2 l3.E23 l8.E7 ram9k.q_o[18] - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 ram9k.q_o[11] - - - l1.S6 l2.S3 l4.S15 ram9k.q_o[3] - - - l1.S7 l3.S8 l8.S7 ram9k.q_o[19] - - - l1.S8 l3.S11 l8.S15 - - - l1.W9 l1.W10 l3.W14 ram9k.q_o[12] - - - l1.W11 l2.W5 l4.W3 ram9k.q_o[4] - - - l1.W12 l3.W17 l8.W7 ram9k.q_o[20] - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 ram9k.q_o[13] - - - l1.N3 l2.N1 l4.N7 ram9k.q_o[5] - - - l1.N4 l3.N2 l8.N7 ram9k.q_o[21] - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 ram9k.q_o[14] - - - l1.E8 l2.E3 l4.E11 ram9k.q_o[6] - - - l1.E9 l3.E11 l8.E7 ram9k.q_o[22] - - - l1.E10 l3.E14 l8.E15 + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.S11 l1.S12 l3.S17 ram9k.q_o[15] - - - l1.S0 l2.S5 l4.S15 ram9k.q_o[7] - - - l1.S1 l3.S20 l8.S7 ram9k.q_o[23] - - - l1.S2 l3.S23 l8.S15 - - - l1.W3 l1.W4 l3.W2 ram9k.q_o[8] - - - l1.W5 l2.W1 l4.W3 ram9k.q_o[0] - - - l1.W6 l3.W5 l8.W7 ram9k.q_o[16] - - - l1.W7 l3.W8 l8.W15 - - - l1.N8 l1.N9 l3.N11 ram9k.q_o[9] - - - l1.N10 l2.N3 l4.N7 ram9k.q_o[1] - - - l1.N11 l3.N14 l8.N7 ram9k.q_o[17] - - - l1.N12 l3.N17 l8.N15 - - - l1.E0 l1.E1 l3.E20 ram9k.q_o[10] - - - l1.E2 l2.E5 l4.E11 ram9k.q_o[2] - - - l1.E3 l3.E23 l8.E7 ram9k.q_o[18] - - - l1.E4 l3.E2 l8.E15 - - - l1.S5 l1.S6 l3.S5 ram9k.q_o[11] - - - l1.S7 l2.S1 l4.S15 ram9k.q_o[3] - - - l1.S8 l3.S8 l8.S7 ram9k.q_o[19] - - - l1.S9 l3.S11 l8.S15 - - - l1.W10 l1.W11 l3.W14 ram9k.q_o[12] + + + + + + + + + + + + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] - - l1.W12 l2.W3 l4.W3 ram9k.q_o[4] + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] - - l1.W0 l3.W17 l8.W7 ram9k.q_o[20] + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] - - l1.W1 l3.W20 l8.W15 + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] - - l1.N2 l1.N3 l3.N23 ram9k.q_o[13] + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] - - l1.N4 l2.N5 l4.N7 ram9k.q_o[5] + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] - - l1.N5 l3.N2 l8.N7 ram9k.q_o[21] + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] - - l1.N6 l3.N5 l8.N15 + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] - - l1.E7 l1.E8 l3.E8 ram9k.q_o[14] + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] - - l1.E9 l2.E1 l4.E11 ram9k.q_o[6] + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] - - l1.E10 l3.E11 l8.E7 ram9k.q_o[22] + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] - - l1.E11 l3.E14 l8.E15 + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] - - l1.S12 l1.S0 l3.S17 ram9k.q_o[15] + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] - - l1.S1 l2.S3 l4.S15 ram9k.q_o[7] + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] - - l1.S2 l3.S20 l8.S7 ram9k.q_o[23] + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] - - l1.S3 l3.S23 l8.S15 + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 ram9k.q_o[0] OG_0 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[22] - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 ram9k.q_o[8] + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[23] - l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 ram9k.q_o[16] + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[24] - l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 ram9k.q_o[1] + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[25] - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 ram9k.q_o[9] + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[26] - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 ram9k.q_o[17] OG_2 l1.N2 + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[27] - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 ram9k.q_o[2] OG_2 l1.S4 + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[28] - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 ram9k.q_o[10] OG_3 l1.N9 + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[29] - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 ram9k.q_o[18] OG_4 + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[30] - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 ram9k.q_o[3] + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[31] - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 ram9k.q_o[11] + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[32] - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 ram9k.q_o[19] + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[22] - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 ram9k.q_o[4] + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[23] - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 ram9k.q_o[12] OG_6 l1.E5 + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[24] - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 ram9k.q_o[20] OG_6 l1.S4 + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[25] - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 ram9k.q_o[5] OG_7 l1.N0 + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[26] - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 ram9k.q_o[13] OG_0 + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 ram9k.q_o[21] + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 ram9k.q_o[6] + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 ram9k.q_o[14] + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 ram9k.q_o[22] + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 ram9k.q_o[7] OG_2 l1.E0 + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 ram9k.q_o[15] OG_2 l1.N10 + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 ram9k.q_o[23] OG_3 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 ram9k.q_o[0] OG_4 + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 ram9k.q_o[8] + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 ram9k.q_o[16] + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 ram9k.q_o[1] + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 ram9k.q_o[9] + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 ram9k.q_o[17] OG_6 l1.W6 + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 ram9k.q_o[2] OG_6 l1.S8 + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 ram9k.q_o[10] OG_7 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 ram9k.q_o[18] OG_0 + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[22] - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 ram9k.q_o[3] + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[23] - l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 ram9k.q_o[11] + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[24] - l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 ram9k.q_o[19] + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[25] - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 ram9k.q_o[4] + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[26] - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 ram9k.q_o[12] OG_2 l1.S6 + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[27] - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 ram9k.q_o[20] OG_2 l1.E0 + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[28] - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 ram9k.q_o[5] OG_3 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[29] - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 ram9k.q_o[13] OG_4 + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[30] - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 ram9k.q_o[21] + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[31] - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 ram9k.q_o[6] + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[32] - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 ram9k.q_o[14] + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[22] - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 ram9k.q_o[22] + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[23] - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 ram9k.q_o[7] OG_6 l1.E2 + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[24] - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 ram9k.q_o[15] OG_6 l1.W3 + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[25] - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 ram9k.q_o[23] OG_7 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[26] - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 ram9k.q_o[0] OG_0 + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 ram9k.q_o[8] + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 ram9k.q_o[16] + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 ram9k.q_o[1] + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 ram9k.q_o[9] + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 ram9k.q_o[17] OG_2 l1.W12 + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 ram9k.q_o[2] OG_2 l1.W4 + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 ram9k.q_o[10] OG_3 l1.N10 + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 ram9k.q_o[18] OG_4 + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 ram9k.q_o[3] + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 ram9k.q_o[11] + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 ram9k.q_o[19] + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - ram9k.q_o[17] ram9k.q_o[0] ram9k.q_o[8] ram9k.q_o[9] + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - ram9k.q_o[17] ram9k.q_o[0] ram9k.q_o[1] ram9k.q_o[8] + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - ram9k.q_o[16] ram9k.q_o[0] ram9k.q_o[1] ram9k.q_o[9] + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - ram9k.q_o[16] ram9k.q_o[1] ram9k.q_o[8] ram9k.q_o[9] + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[22] - - ram9k.q_o[19] ram9k.q_o[2] ram9k.q_o[10] ram9k.q_o[11] + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[23] - - ram9k.q_o[19] ram9k.q_o[2] ram9k.q_o[3] ram9k.q_o[10] + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[24] - - ram9k.q_o[18] ram9k.q_o[2] ram9k.q_o[3] ram9k.q_o[11] + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[25] - - ram9k.q_o[18] ram9k.q_o[3] ram9k.q_o[10] ram9k.q_o[11] + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[22] - - ram9k.q_o[21] ram9k.q_o[4] ram9k.q_o[12] ram9k.q_o[13] + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[23] - - ram9k.q_o[21] ram9k.q_o[4] ram9k.q_o[5] ram9k.q_o[12] + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[24] - - ram9k.q_o[20] ram9k.q_o[4] ram9k.q_o[5] ram9k.q_o[13] + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[25] - - ram9k.q_o[20] ram9k.q_o[5] ram9k.q_o[12] ram9k.q_o[13] + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[26] - - ram9k.q_o[23] ram9k.q_o[6] ram9k.q_o[14] ram9k.q_o[15] + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[27] - - ram9k.q_o[23] ram9k.q_o[6] ram9k.q_o[7] ram9k.q_o[14] + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[28] - - ram9k.q_o[22] ram9k.q_o[6] ram9k.q_o[7] ram9k.q_o[15] + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[29] - - ram9k.q_o[22] ram9k.q_o[7] ram9k.q_o[14] ram9k.q_o[15] + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[30] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[31] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[32] - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[22] - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[23] - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[24] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[25] - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[26] - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - l1.W0 - mux_0 mux_5 mux_10 mux_15 + + memory.addr1[6] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + memory.data[20] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + memory.data[26] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + memory.addr1[8] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + memory.data[22] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + memory.data[28] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + memory.addr2[7] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + memory.data[24] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + memory.addr1[7] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + memory.data[21] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + memory.data[27] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + memory.addr2[6] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + memory.data[23] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + memory.data[29] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + memory.addr2[8] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + memory.data[25] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + memory.addr1[8] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + memory.data[22] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + memory.data[28] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + memory.addr2[7] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + memory.data[24] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + memory.addr1[6] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + memory.data[20] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + memory.data[26] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + memory.addr2[6] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + memory.data[23] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + memory.data[29] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + memory.addr2[8] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + memory.data[25] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + memory.addr1[7] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + memory.data[21] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + memory.data[27] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + memory.addr2[7] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - + + memory.data[24] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + memory.addr1[6] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + memory.data[20] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + memory.data[26] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + memory.addr1[8] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + memory.data[22] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + memory.data[28] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + memory.addr2[8] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + memory.data[25] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + memory.addr1[7] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + memory.data[21] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + memory.data[27] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + memory.addr2[6] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + memory.data[23] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + memory.data[29] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + l1.N0 - mux_16 mux_21 mux_11 mux_14 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - + l1.E0 - mux_32 mux_6 mux_9 mux_31 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - + l1.S0 - mux_48 mux_22 mux_27 mux_13 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - - l1.W1 - mux_64 mux_7 mux_25 mux_30 + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - - l1.N1 - mux_80 mux_23 mux_26 mux_29 + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - - l1.E1 - mux_1 mux_4 mux_42 mux_47 + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - - l1.S1 - mux_17 mux_20 mux_43 mux_46 + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - - l1.W2 - mux_33 mux_38 mux_8 mux_63 + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - - l1.N2 - mux_49 mux_54 mux_59 mux_12 + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - - l1.E2 - mux_65 mux_39 mux_24 mux_62 + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - - l1.S2 - mux_81 mux_55 mux_58 mux_28 + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - - l1.W3 - mux_2 mux_36 mux_41 mux_79 + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - - l1.N3 - mux_18 mux_52 mux_75 mux_45 + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - - l1.E3 - mux_34 mux_37 mux_40 mux_95 + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - - l1.S3 - mux_50 mux_53 mux_91 mux_44 + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - + l1.W4 - mux_66 mux_71 mux_56 mux_61 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - - l1.N4 - mux_82 mux_87 mux_57 mux_60 + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - - l1.E4 - mux_3 mux_68 mux_73 mux_78 + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - - l1.S4 - mux_19 mux_84 mux_74 mux_77 + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - - l1.W5 - mux_35 mux_69 mux_72 mux_94 + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - - l1.N5 - mux_51 mux_85 mux_90 mux_76 + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - - l1.E5 - mux_67 mux_70 mux_88 mux_93 + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - l1.S5 - mux_83 mux_86 mux_89 mux_92 + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - - l1.W6 - mux_96 mux_101 mux_106 mux_111 + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - - l1.N6 - mux_112 mux_117 mux_107 mux_110 + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - - l1.E6 - mux_0 mux_102 mux_105 mux_127 + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - - l1.S6 - mux_16 mux_118 mux_123 mux_109 + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - - l1.W7 - mux_32 mux_103 mux_121 mux_126 + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.N7 - mux_48 mux_119 mux_122 mux_125 + + + + + + + + + + + + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] - - l1.E7 - mux_97 mux_100 mux_10 mux_15 + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] - - l1.S7 - mux_113 mux_116 mux_11 mux_14 + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] - - l1.W8 - mux_1 mux_6 mux_104 mux_31 + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] - - l1.N8 - mux_17 mux_22 mux_27 mux_108 + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] - - l1.E8 - mux_33 mux_7 mux_120 mux_30 + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] - - l1.S8 - mux_49 mux_23 mux_26 mux_124 + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] - - l2.W0 - mux_98 mux_4 mux_9 mux_47 + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] - - l2.N0 - mux_114 mux_20 mux_43 mux_13 + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] - - l2.E0 - mux_2 mux_5 mux_8 mux_63 + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] - - l2.S0 - mux_18 mux_21 mux_59 mux_12 + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] - - l2.W2 - mux_34 mux_39 mux_24 mux_29 + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] - - l2.N2 - mux_50 mux_55 mux_25 mux_28 + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] - - l2.E2 - mux_99 mux_36 mux_41 mux_46 + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] - - l2.S2 - mux_115 mux_52 mux_42 mux_45 + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] - - l2.W4 - mux_3 mux_37 mux_40 mux_62 + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] - - l2.N4 - mux_19 mux_53 mux_58 mux_44 + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[11] - - l2.E4 - mux_35 mux_38 mux_56 mux_61 + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[12] - - l2.S4 - mux_51 mux_54 mux_57 mux_60 + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[13] - - l3.W0 - mux_64 mux_69 mux_74 mux_79 + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[14] - - l3.N0 - mux_80 mux_85 mux_75 mux_78 + + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[15] - - l3.E0 - mux_96 mux_70 mux_73 mux_95 + + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[16] - - l3.S0 - mux_112 mux_86 mux_91 mux_77 + + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[17] - - l3.W3 - mux_0 mux_71 mux_89 mux_94 + + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[18] - - l3.N3 - mux_16 mux_87 mux_90 mux_93 + + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[19] - - l3.E3 - mux_65 mux_68 mux_106 mux_111 + + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[20] - - l3.S3 - mux_81 mux_84 mux_107 mux_110 + + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[21] - - l3.W6 - mux_97 mux_102 mux_72 mux_127 + + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[11] + + + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[12] - - l3.N6 - mux_113 mux_118 mux_123 mux_76 + + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[13] - - l3.E6 - mux_1 mux_103 mux_88 mux_126 + + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[14] - - l3.S6 - mux_17 mux_119 mux_122 mux_92 + + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[15] - - l3.W9 - mux_66 mux_100 mux_105 mux_15 + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - - l3.N9 - mux_82 mux_116 mux_11 mux_109 + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - - l3.E9 - mux_98 mux_101 mux_104 mux_31 + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - - l3.S9 - mux_114 mux_117 mux_27 mux_108 + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - - l3.W12 - mux_2 mux_7 mux_120 mux_125 + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - - l3.N12 - mux_18 mux_23 mux_121 mux_124 + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - - l3.E12 - mux_67 mux_4 mux_9 mux_14 + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - - l3.S12 - mux_83 mux_20 mux_10 mux_13 + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - - l3.W15 - mux_99 mux_5 mux_8 mux_30 + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - - l3.N15 - mux_115 mux_21 mux_26 mux_12 + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - - l3.E15 - mux_3 mux_6 mux_24 mux_29 + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - - l3.S15 - mux_19 mux_22 mux_25 mux_28 + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - - l3.W18 - mux_32 mux_37 mux_42 mux_47 + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - - l3.N18 - mux_48 mux_53 mux_43 mux_46 + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - - l3.E18 - mux_64 mux_38 mux_41 mux_63 + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - - l3.S18 - mux_80 mux_54 mux_59 mux_45 + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - - l3.W21 - mux_96 mux_39 mux_57 mux_62 + + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[11] - - l3.N21 - mux_112 mux_55 mux_58 mux_61 + + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[12] - - l3.E21 - mux_33 mux_36 mux_74 mux_79 + + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[13] - - l3.S21 - mux_49 mux_52 mux_75 mux_78 + + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[14] - - l4.W0 - mux_65 mux_70 mux_40 mux_95 + + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[15] - - l4.N0 - mux_81 mux_86 mux_91 mux_44 + + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[16] - - l4.E0 - mux_97 mux_71 mux_56 mux_94 + + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[17] - - l4.S0 - mux_113 mux_87 mux_90 mux_60 + + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[18] - - l4.W4 - mux_34 mux_68 mux_73 mux_111 + + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[19] - - l4.N4 - mux_50 mux_84 mux_107 mux_77 + + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[20] - - l4.E4 - mux_66 mux_69 mux_72 mux_127 + + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[21] - - l4.S4 - mux_82 mux_85 mux_123 mux_76 + + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[11] - - l4.W8 - mux_98 mux_103 mux_88 mux_93 + + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[12] - - l4.N8 - mux_114 mux_119 mux_89 mux_92 + + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[13] - - l4.E8 - mux_35 mux_100 mux_105 mux_110 + + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[14] - - l4.S8 - mux_51 mux_116 mux_106 mux_109 + + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[15] - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - - l4.N12 - mux_83 mux_117 mux_122 mux_108 + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - - l4.E12 - mux_99 mux_102 mux_120 mux_125 + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - - l4.S12 - mux_115 mux_118 mux_121 mux_124 + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - - l8.W0 - mux_0 mux_5 mux_10 mux_15 + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - - l8.N0 - mux_16 mux_21 mux_11 mux_14 + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - - l8.E0 - mux_32 mux_6 mux_9 mux_31 + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - - l8.S0 - mux_48 mux_22 mux_27 mux_13 + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - - l8.W8 - mux_64 mux_7 mux_25 mux_30 + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - - l8.N8 - mux_80 mux_23 mux_26 mux_29 + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - - l8.E8 - mux_1 mux_4 mux_42 mux_47 + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - - l8.S8 - mux_17 mux_20 mux_43 mux_46 + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - l1.W9 - l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - l1.N9 - l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - l1.E9 - l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - l1.S9 - l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - l1.W10 - l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[11] - - l1.N10 - l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[12] - - l1.E10 - l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[13] - - l1.S10 - l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[14] - - l1.W11 - l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[11] - - l1.N11 - l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[12] - - l1.E11 - l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[13] - - l1.S11 - l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[14] - - l1.W12 - l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[15] - - l1.N12 - l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[16] - - l1.E12 - l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[17] - - l1.S12 - l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[18] - - ram9k.raddr_i[0] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[19] - - ram9k.raddr_i[1] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[20] - - ram9k.raddr_i[2] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[21] - - ram9k.raddr_i[3] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[11] - - ram9k.raddr_i[4] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[12] - - ram9k.raddr_i[5] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[13] - - ram9k.waddr_i[0] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[14] - - ram9k.waddr_i[1] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[15] - - ram9k.waddr_i[2] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - ram9k.waddr_i[3] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - ram9k.waddr_i[4] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - ram9k.waddr_i[5] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - ram9k.data_i[0] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + + + memory.addr1[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - ram9k.data_i[1] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + memory.data[10] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - ram9k.data_i[2] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + memory.data[16] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - ram9k.data_i[3] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + memory.addr1[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - ram9k.data_i[4] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + memory.data[12] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - ram9k.data_i[5] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + memory.data[18] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - ram9k.data_i[6] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + memory.addr2[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - ram9k.data_i[7] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + memory.data[14] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - ram9k.data_i[8] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + memory.addr1[4] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - ram9k.data_i[18] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + memory.data[11] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - ram9k.data_i[19] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + memory.data[17] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - ram9k.data_i[20] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + memory.addr2[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - ram9k.data_i[21] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + memory.data[13] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - ram9k.data_i[22] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + memory.data[19] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - ram9k.data_i[23] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + memory.addr2[5] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - ram9k.data_i[24] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + memory.data[15] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - ram9k.data_i[25] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + memory.addr1[5] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - ram9k.data_i[26] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + memory.data[12] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - ram9k.bwen_ni[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + memory.data[18] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - ram9k.bwen_ni[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + memory.addr2[4] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - ram9k.bwen_ni[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + memory.data[14] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - ram9k.bwen_ni[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + memory.addr1[3] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - ram9k.bwen_ni[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + memory.data[10] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - ram9k.bwen_ni[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + memory.data[16] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - ram9k.bwen_ni[6] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + memory.addr2[3] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - ram9k.bwen_ni[7] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + memory.data[13] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - ram9k.bwen_ni[8] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + memory.data[19] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - ram9k.bwen_ni[18] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + memory.addr2[5] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - ram9k.bwen_ni[19] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + memory.data[15] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - ram9k.bwen_ni[20] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + memory.addr1[4] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - ram9k.bwen_ni[21] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + memory.data[11] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - ram9k.bwen_ni[22] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + memory.data[17] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - ram9k.bwen_ni[23] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + memory.addr2[4] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - ram9k.bwen_ni[24] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + memory.data[14] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - ram9k.bwen_ni[25] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + memory.addr1[3] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - ram9k.bwen_ni[26] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + memory.data[10] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - ram9k.lclk[0] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + memory.data[16] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - ram9k.lreset[0] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + memory.addr1[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - ram9k.raddr_i[0] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + memory.data[12] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - ram9k.raddr_i[1] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + memory.data[18] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - ram9k.raddr_i[2] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + memory.addr2[5] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - ram9k.raddr_i[3] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + memory.data[15] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - ram9k.raddr_i[4] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + memory.addr1[4] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - ram9k.raddr_i[5] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + memory.data[11] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - ram9k.waddr_i[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + memory.data[17] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - ram9k.waddr_i[1] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + memory.addr2[3] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - ram9k.waddr_i[2] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + memory.data[13] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - ram9k.waddr_i[3] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + memory.data[19] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - - - - - - - - - - - l1.W0 l1.W1 l3.W2 ram9k.q_o[32] + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - l1.W2 l2.W1 l4.W3 ram9k.q_o[24] + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - l1.W3 l3.W5 l8.W7 ram9k.q_o[28] + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - l1.W4 l3.W8 l8.W15 + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - l1.N5 l1.N6 l3.N11 ram9k.q_o[33] + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - l1.N7 l2.N3 l4.N7 ram9k.q_o[25] + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - l1.N8 l3.N14 l8.N7 ram9k.q_o[29] + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - l1.N9 l3.N17 l8.N15 + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - l1.E10 l1.E11 l3.E20 ram9k.q_o[34] + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - l1.E12 l2.E5 l4.E11 ram9k.q_o[26] + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - l1.E0 l3.E23 l8.E7 ram9k.q_o[30] + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - l1.E1 l3.E2 l8.E15 + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - l1.S2 l1.S3 l3.S5 ram9k.q_o[35] + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - l1.S4 l2.S1 l4.S15 ram9k.q_o[27] + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - l1.S5 l3.S8 l8.S7 ram9k.q_o[31] + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - l1.S6 l3.S11 l8.S15 + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - l1.W7 l1.W8 l3.W14 ram9k.q_o[24] + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - l1.W9 l2.W3 l4.W3 ram9k.q_o[28] + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - l1.W10 l3.W17 l8.W7 ram9k.q_o[32] + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - l1.W11 l3.W20 l8.W15 + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - l1.N12 l1.N0 l3.N23 ram9k.q_o[25] + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - l1.N1 l2.N5 l4.N7 ram9k.q_o[29] + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - l1.N2 l3.N2 l8.N7 ram9k.q_o[33] + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - l1.N3 l3.N5 l8.N15 + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - l1.E4 l1.E5 l3.E8 ram9k.q_o[26] + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - l1.E6 l2.E1 l4.E11 ram9k.q_o[30] + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - l1.E7 l3.E11 l8.E7 ram9k.q_o[34] + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - l1.E8 l3.E14 l8.E15 + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - l1.S9 l1.S10 l3.S17 ram9k.q_o[27] + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - l1.S11 l2.S3 l4.S15 ram9k.q_o[31] + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - l1.S12 l3.S20 l8.S7 ram9k.q_o[35] + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - l1.S0 l3.S23 l8.S15 + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - l1.W1 l1.W2 l3.W2 ram9k.q_o[32] + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - l1.W3 l2.W5 l4.W3 ram9k.q_o[24] + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - l1.W4 l3.W5 l8.W7 ram9k.q_o[28] + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - l1.W5 l3.W8 l8.W15 + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - l1.N6 l1.N7 l3.N11 ram9k.q_o[33] + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - l1.N8 l2.N1 l4.N7 ram9k.q_o[25] + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - l1.N9 l3.N14 l8.N7 ram9k.q_o[29] + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - l1.N10 l3.N17 l8.N15 + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - l1.E11 l1.E12 l3.E20 ram9k.q_o[34] + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - l1.E0 l2.E3 l4.E11 ram9k.q_o[26] + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - l1.E1 l3.E23 l8.E7 ram9k.q_o[30] + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - l1.E2 l3.E2 l8.E15 + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - l1.S3 l1.S4 l3.S5 ram9k.q_o[35] + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - l1.S5 l2.S5 l4.S15 ram9k.q_o[27] + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - l1.S6 l3.S8 l8.S7 ram9k.q_o[31] + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - l1.S7 l3.S11 l8.S15 + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - l1.W8 l1.W9 l3.W14 ram9k.q_o[24] + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - l1.W10 l2.W1 l4.W3 ram9k.q_o[28] + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - l1.W11 l3.W17 l8.W7 ram9k.q_o[32] + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - l1.W12 l3.W20 l8.W15 + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - l1.N0 l1.N1 l3.N23 ram9k.q_o[25] + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - l1.N2 l2.N3 l4.N7 ram9k.q_o[29] - - - l1.N3 l3.N2 l8.N7 ram9k.q_o[33] - - - l1.N4 l3.N5 l8.N15 - - - l1.E5 l1.E6 l3.E8 ram9k.q_o[26] - - - l1.E7 l2.E5 l4.E11 ram9k.q_o[30] - - - l1.E8 l3.E11 l8.E7 ram9k.q_o[34] - - - l1.E9 l3.E14 l8.E15 - - - l1.S10 l1.S11 l3.S17 ram9k.q_o[27] - - - l1.S12 l2.S1 l4.S15 ram9k.q_o[31] - - - l1.S0 l3.S20 l8.S7 ram9k.q_o[35] - - - l1.S1 l3.S23 l8.S15 - - - l1.W2 l1.W3 l3.W2 ram9k.q_o[32] - - - l1.W4 l2.W3 l4.W3 ram9k.q_o[24] - - - l1.W5 l3.W5 l8.W7 ram9k.q_o[28] - - - l1.W6 l3.W8 l8.W15 - - - l1.N7 l1.N8 l3.N11 ram9k.q_o[33] - - - l1.N9 l2.N5 l4.N7 ram9k.q_o[25] - - - l1.N10 l3.N14 l8.N7 ram9k.q_o[29] - - - l1.N11 l3.N17 l8.N15 - - - l1.E12 l1.E0 l3.E20 ram9k.q_o[34] - - - l1.E1 l2.E1 l4.E11 ram9k.q_o[26] - - - l1.E2 l3.E23 l8.E7 ram9k.q_o[30] - - - l1.E3 l3.E2 l8.E15 - - - l1.S4 l1.S5 l3.S5 ram9k.q_o[35] - - - l1.S6 l2.S3 l4.S15 ram9k.q_o[27] - - - l1.S7 l3.S8 l8.S7 ram9k.q_o[31] - - - l1.S8 l3.S11 l8.S15 - - - l1.W9 l1.W10 l3.W14 ram9k.q_o[24] - - - l1.W11 l2.W5 l4.W3 ram9k.q_o[28] - - - l1.W12 l3.W17 l8.W7 ram9k.q_o[32] - - - l1.W0 l3.W20 l8.W15 - - - l1.N1 l1.N2 l3.N23 ram9k.q_o[25] - - - l1.N3 l2.N1 l4.N7 ram9k.q_o[29] - - - l1.N4 l3.N2 l8.N7 ram9k.q_o[33] - - - l1.N5 l3.N5 l8.N15 - - - l1.E6 l1.E7 l3.E8 ram9k.q_o[26] - - - l1.E8 l2.E3 l4.E11 ram9k.q_o[30] - - - l1.E9 l3.E11 l8.E7 ram9k.q_o[34] - - - l1.E10 l3.E14 l8.E15 - - - l1.S11 l1.S12 l3.S17 ram9k.q_o[27] - - - l1.S0 l2.S5 l4.S15 ram9k.q_o[31] - - - l1.S1 l3.S20 l8.S7 ram9k.q_o[35] - - - l1.S2 l3.S23 l8.S15 - - - l1.W3 l1.W4 l3.W2 ram9k.q_o[32] - - - l1.W5 l2.W1 l4.W3 ram9k.q_o[24] + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - - l1.W6 l3.W5 l8.W7 ram9k.q_o[28] + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - - l1.W7 l3.W8 l8.W15 + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - - l1.N8 l1.N9 l3.N11 ram9k.q_o[33] + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - - l1.N10 l2.N3 l4.N7 ram9k.q_o[25] + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - - l1.N11 l3.N14 l8.N7 ram9k.q_o[29] + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - - l1.N12 l3.N17 l8.N15 + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - - l1.E0 l1.E1 l3.E20 ram9k.q_o[34] + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - - l1.E2 l2.E5 l4.E11 ram9k.q_o[26] + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - l1.E3 l3.E23 l8.E7 ram9k.q_o[30] + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - - l1.E4 l3.E2 l8.E15 + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - - l1.S5 l1.S6 l3.S5 ram9k.q_o[35] + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - - l1.S7 l2.S1 l4.S15 ram9k.q_o[27] + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - - l1.S8 l3.S8 l8.S7 ram9k.q_o[31] + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - - l1.S9 l3.S11 l8.S15 + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - l1.W10 l1.W11 l3.W14 ram9k.q_o[24] + + + + + + + + + + + + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] - - l1.W12 l2.W3 l4.W3 ram9k.q_o[28] + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] - - l1.W0 l3.W17 l8.W7 ram9k.q_o[32] + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] - - l1.W1 l3.W20 l8.W15 + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] - - l1.N2 l1.N3 l3.N23 ram9k.q_o[25] + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] - - l1.N4 l2.N5 l4.N7 ram9k.q_o[29] + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] - - l1.N5 l3.N2 l8.N7 ram9k.q_o[33] + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] - - l1.N6 l3.N5 l8.N15 + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] - - l1.E7 l1.E8 l3.E8 ram9k.q_o[26] + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] - - l1.E9 l2.E1 l4.E11 ram9k.q_o[30] + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] - - l1.E10 l3.E11 l8.E7 ram9k.q_o[34] + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] - - l1.E11 l3.E14 l8.E15 + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] - - l1.S12 l1.S0 l3.S17 ram9k.q_o[27] + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] - - l1.S1 l2.S3 l4.S15 ram9k.q_o[31] + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] - - l1.S2 l3.S20 l8.S7 ram9k.q_o[35] + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] - - l1.S3 l3.S23 l8.S15 + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] - l1.W6 l1.E12 l1.W5 l2.W3 l3.W11 l4.W7 ram9k.q_o[24] OG_0 + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[0] - l1.E12 l1.N5 l1.E11 l2.E5 l3.E23 l4.E15 ram9k.q_o[32] + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[1] - l1.E5 l1.S11 l1.N4 l3.E8 l3.S17 l4.E3 ram9k.q_o[28] + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[2] - l1.W11 l1.N4 l1.S10 l3.W20 l3.N8 l4.W11 ram9k.q_o[25] + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[3] - l1.E4 l1.S10 l1.E3 l3.E5 l3.S14 l4.E15 ram9k.q_o[33] + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[4] - l1.W10 l1.S3 l2.W1 l3.W17 l3.S5 ram9k.q_o[29] OG_2 l1.N2 + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[5] - l1.W3 l1.N9 l2.W3 l3.W2 l3.N11 ram9k.q_o[26] OG_2 l1.S4 + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[6] - l1.E9 l1.S2 l2.E5 l3.E14 l4.E7 ram9k.q_o[34] OG_3 l1.N9 + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[7] - l1.E2 l1.W8 l1.W1 l2.E1 l3.E23 l4.E11 ram9k.q_o[30] OG_4 + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[8] - l1.W8 l1.S1 l1.E7 l2.W3 l3.W11 l4.W3 ram9k.q_o[27] + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[9] - l1.W1 l1.N7 l1.N0 l3.W20 l3.N5 l4.W7 ram9k.q_o[35] + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[10] - l1.E7 l1.S0 l1.S6 l3.E8 l3.S20 l4.E15 ram9k.q_o[31] + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[0] - l1.W0 l1.N6 l1.E12 l3.W17 l3.N2 l4.W3 ram9k.q_o[28] + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[1] - l1.E6 l1.N12 l2.E5 l3.E5 l3.N17 ram9k.q_o[24] OG_6 l1.E5 + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[2] - l1.E12 l1.S5 l2.E1 l3.E14 l3.S23 ram9k.q_o[32] OG_6 l1.S4 + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[3] - l1.W5 l1.N11 l2.W3 l3.W2 l4.W11 ram9k.q_o[29] OG_7 l1.N0 + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[4] - l1.W11 l1.E4 l1.W10 l2.W5 l3.W11 l4.W15 ram9k.q_o[25] OG_0 + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 - l1.W4 l1.N10 l1.E3 l2.W1 l3.W23 l4.W7 ram9k.q_o[33] + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 - l1.E10 l1.N3 l1.N9 l3.E8 l3.N17 l4.E11 ram9k.q_o[30] + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 - l1.E3 l1.N9 l1.S2 l3.E20 l3.N8 l4.E3 ram9k.q_o[26] + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 - l1.E9 l1.N2 l1.E8 l3.E5 l3.N14 l4.E7 ram9k.q_o[34] + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 - l1.E2 l1.S8 l2.E3 l3.E17 l3.S5 ram9k.q_o[31] OG_2 l1.E0 + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 - l1.W8 l1.S1 l2.W5 l3.W2 l3.S11 ram9k.q_o[27] OG_2 l1.N10 + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 - l1.W1 l1.S7 l2.W1 l3.W14 l4.W15 ram9k.q_o[35] OG_3 l1.W12 + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 - l1.E7 l1.W0 l1.W6 l2.E3 l3.E23 l4.E3 ram9k.q_o[24] OG_4 + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 - l1.E0 l1.S6 l1.E12 l2.E5 l3.E11 l4.E11 ram9k.q_o[32] + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 - l1.W6 l1.S12 l1.N5 l3.W20 l3.S5 l4.W15 ram9k.q_o[28] + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 - l1.W12 l1.S5 l1.S11 l3.W8 l3.S20 l4.W7 ram9k.q_o[25] + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 - l1.W5 l1.S11 l1.E4 l3.W17 l3.S2 l4.W11 ram9k.q_o[33] + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 - l1.W11 l1.N4 l2.W1 l3.W5 l3.N17 ram9k.q_o[29] OG_6 l1.W6 + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 - l1.E4 l1.N10 l2.E3 l3.E14 l3.N23 ram9k.q_o[26] OG_6 l1.S8 + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 - l1.E10 l1.N3 l2.E5 l3.E2 l4.E3 ram9k.q_o[34] OG_7 l1.E2 + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 - l1.W3 l1.E9 l1.W2 l2.W1 l3.W11 l4.W7 ram9k.q_o[30] OG_0 + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[0] - l1.E9 l1.N2 l1.E8 l2.E3 l3.E23 l4.E15 ram9k.q_o[27] + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[1] - l1.E2 l1.S8 l1.N1 l3.E8 l3.S17 l4.E3 ram9k.q_o[35] + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[2] - l1.W8 l1.N1 l1.S7 l3.W20 l3.N8 l4.W11 ram9k.q_o[31] + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[3] - l1.E1 l1.S7 l1.E0 l3.E5 l3.S14 l4.E15 ram9k.q_o[28] + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[4] - l1.W7 l1.S0 l2.W5 l3.W17 l3.S5 ram9k.q_o[24] OG_2 l1.S6 + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[5] - l1.W0 l1.N6 l2.W1 l3.W2 l3.N11 ram9k.q_o[32] OG_2 l1.E0 + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[6] - l1.E6 l1.S12 l2.E3 l3.E14 l4.E7 ram9k.q_o[29] OG_3 l1.W11 + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[7] - l1.E12 l1.W5 l1.W11 l2.E5 l3.E23 l4.E11 ram9k.q_o[25] OG_4 + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[8] - l1.W5 l1.S11 l1.E4 l2.W1 l3.W11 l4.W3 ram9k.q_o[33] + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[9] - l1.W11 l1.N4 l1.N10 l3.W20 l3.N5 l4.W7 ram9k.q_o[30] + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[10] - l1.E4 l1.S10 l1.S3 l3.E8 l3.S20 l4.E15 ram9k.q_o[26] + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[0] - l1.W10 l1.N3 l1.E9 l3.W17 l3.N2 l4.W3 ram9k.q_o[34] + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[1] - l1.E3 l1.N9 l2.E3 l3.E5 l3.N17 ram9k.q_o[31] OG_6 l1.E2 + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[2] - l1.E9 l1.S2 l2.E5 l3.E14 l3.S23 ram9k.q_o[27] OG_6 l1.W3 + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[3] - l1.W2 l1.N8 l2.W1 l3.W2 l4.W11 ram9k.q_o[35] OG_7 l1.W0 + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[4] - l1.W8 l1.E1 l1.W7 l2.W3 l3.W11 l4.W15 ram9k.q_o[24] OG_0 + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 - l1.W1 l1.N7 l1.E0 l2.W5 l3.W23 l4.W7 ram9k.q_o[32] + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 - l1.E7 l1.N0 l1.N6 l3.E8 l3.N17 l4.E11 ram9k.q_o[28] + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 - l1.E0 l1.N6 l1.S12 l3.E20 l3.N8 l4.E3 ram9k.q_o[25] + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 - l1.E6 l1.N12 l1.E5 l3.E5 l3.N14 l4.E7 ram9k.q_o[33] + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 - l1.E12 l1.S5 l2.E1 l3.E17 l3.S5 ram9k.q_o[29] OG_2 l1.W12 + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 - l1.W5 l1.S11 l2.W3 l3.W2 l3.S11 ram9k.q_o[26] OG_2 l1.W4 + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 - l1.W11 l1.S4 l2.W5 l3.W14 l4.W15 ram9k.q_o[34] OG_3 l1.N10 + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 - l1.E4 l1.W10 l1.W3 l2.E1 l3.E23 l4.E3 ram9k.q_o[30] OG_4 + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 - l1.E10 l1.S3 l1.E9 l2.E3 l3.E11 l4.E11 ram9k.q_o[27] + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 - l1.W3 l1.S9 l1.N2 l3.W20 l3.S5 l4.W15 ram9k.q_o[35] + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 - l1.W9 l1.S2 l1.S8 l3.W8 l3.S20 l4.W7 ram9k.q_o[31] - - - ram9k.q_o[29] ram9k.q_o[24] ram9k.q_o[32] ram9k.q_o[33] - - - ram9k.q_o[29] ram9k.q_o[24] ram9k.q_o[25] ram9k.q_o[32] - - - ram9k.q_o[28] ram9k.q_o[24] ram9k.q_o[25] ram9k.q_o[33] - - - ram9k.q_o[28] ram9k.q_o[25] ram9k.q_o[32] ram9k.q_o[33] - - - ram9k.q_o[31] ram9k.q_o[26] ram9k.q_o[34] ram9k.q_o[35] - - - ram9k.q_o[31] ram9k.q_o[26] ram9k.q_o[27] ram9k.q_o[34] - - - ram9k.q_o[30] ram9k.q_o[26] ram9k.q_o[27] ram9k.q_o[35] - - - ram9k.q_o[30] ram9k.q_o[27] ram9k.q_o[34] ram9k.q_o[35] - - - ram9k.q_o[33] ram9k.q_o[28] ram9k.q_o[24] ram9k.q_o[25] - - - ram9k.q_o[33] ram9k.q_o[28] ram9k.q_o[29] ram9k.q_o[24] - - - ram9k.q_o[32] ram9k.q_o[28] ram9k.q_o[29] ram9k.q_o[25] - - - ram9k.q_o[32] ram9k.q_o[29] ram9k.q_o[24] ram9k.q_o[25] - - - ram9k.q_o[35] ram9k.q_o[30] ram9k.q_o[26] ram9k.q_o[27] - - - ram9k.q_o[35] ram9k.q_o[30] ram9k.q_o[31] ram9k.q_o[26] - - - ram9k.q_o[34] ram9k.q_o[30] ram9k.q_o[31] ram9k.q_o[27] - - - ram9k.q_o[34] ram9k.q_o[31] ram9k.q_o[26] ram9k.q_o[27] - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_1 OG_1ST_5 OG_1ST_11 OG_1ST_15 - - - OG_1ST_0 OG_1ST_4 OG_1ST_10 OG_1ST_14 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_3 OG_1ST_7 OG_1ST_9 OG_1ST_13 - - - OG_1ST_2 OG_1ST_6 OG_1ST_8 OG_1ST_12 - - - - - l1.W0 - mux_0 mux_5 mux_10 mux_15 - - - l1.N0 - mux_16 mux_21 mux_11 mux_14 - - - l1.E0 - mux_32 mux_6 mux_9 mux_31 - - - l1.S0 - mux_48 mux_22 mux_27 mux_13 + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 - - l1.W1 - mux_64 mux_7 mux_25 mux_30 - - - l1.N1 - mux_80 mux_23 mux_26 mux_29 - - - l1.E1 - mux_1 mux_4 mux_42 mux_47 - - - l1.S1 - mux_17 mux_20 mux_43 mux_46 + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 - - l1.W2 - mux_33 mux_38 mux_8 mux_63 + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 - - l1.N2 - mux_49 mux_54 mux_59 mux_12 + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 - - l1.E2 - mux_65 mux_39 mux_24 mux_62 + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 - - l1.S2 - mux_81 mux_55 mux_58 mux_28 + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[0] - - l1.W3 - mux_2 mux_36 mux_41 mux_79 + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[1] - - l1.N3 - mux_18 mux_52 mux_75 mux_45 + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[2] - - l1.E3 - mux_34 mux_37 mux_40 mux_95 + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[3] - - l1.S3 - mux_50 mux_53 mux_91 mux_44 + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[0] - - l1.W4 - mux_66 mux_71 mux_56 mux_61 + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[1] - - l1.N4 - mux_82 mux_87 mux_57 mux_60 + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[2] - - l1.E4 - mux_3 mux_68 mux_73 mux_78 + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[3] - - l1.S4 - mux_19 mux_84 mux_74 mux_77 + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[4] - - l1.W5 - mux_35 mux_69 mux_72 mux_94 + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[5] - - l1.N5 - mux_51 mux_85 mux_90 mux_76 + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[6] - - l1.E5 - mux_67 mux_70 mux_88 mux_93 + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[7] - - l1.S5 - mux_83 mux_86 mux_89 mux_92 + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[8] - - l1.W6 - mux_96 mux_101 mux_106 mux_111 + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[9] - - l1.N6 - mux_112 mux_117 mux_107 mux_110 + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[10] - - l1.E6 - mux_0 mux_102 mux_105 mux_127 + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[0] - - l1.S6 - mux_16 mux_118 mux_123 mux_109 + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[1] - - l1.W7 - mux_32 mux_103 mux_121 mux_126 + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[2] - - l1.N7 - mux_48 mux_119 mux_122 mux_125 + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[3] - - l1.E7 - mux_97 mux_100 mux_10 mux_15 + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[4] - - l1.S7 - mux_113 mux_116 mux_11 mux_14 + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 - - l1.W8 - mux_1 mux_6 mux_104 mux_31 + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 - - l1.N8 - mux_17 mux_22 mux_27 mux_108 + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 - - l1.E8 - mux_33 mux_7 mux_120 mux_30 + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 - - l1.S8 - mux_49 mux_23 mux_26 mux_124 + + + + memory.addr1[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 - - l2.W0 - mux_98 mux_4 mux_9 mux_47 + + memory.data[0] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 - - l2.N0 - mux_114 mux_20 mux_43 mux_13 + + memory.data[6] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 - - l2.E0 - mux_2 mux_5 mux_8 mux_63 + + memory.addr1[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 - - l2.S0 - mux_18 mux_21 mux_59 mux_12 + + memory.data[2] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 - - l2.W2 - mux_34 mux_39 mux_24 mux_29 + + memory.data[8] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 - - l2.N2 - mux_50 mux_55 mux_25 mux_28 + + memory.addr2[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 - - l2.E2 - mux_99 mux_36 mux_41 mux_46 + + memory.data[4] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 - - l2.S2 - mux_115 mux_52 mux_42 mux_45 + + memory.addr1[1] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 - - l2.W4 - mux_3 mux_37 mux_40 mux_62 + + memory.data[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 - - l2.N4 - mux_19 mux_53 mux_58 mux_44 + + memory.data[7] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 - - l2.E4 - mux_35 mux_38 mux_56 mux_61 + + memory.addr2[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 - - l2.S4 - mux_51 mux_54 mux_57 mux_60 + + memory.data[3] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 - - l3.W0 - mux_64 mux_69 mux_74 mux_79 + + memory.data[9] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 - - l3.N0 - mux_80 mux_85 mux_75 mux_78 + + memory.addr2[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 - - l3.E0 - mux_96 mux_70 mux_73 mux_95 + + memory.data[5] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 - - l3.S0 - mux_112 mux_86 mux_91 mux_77 + + memory.addr1[2] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 - - l3.W3 - mux_0 mux_71 mux_89 mux_94 + + memory.data[2] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 - - l3.N3 - mux_16 mux_87 mux_90 mux_93 + + memory.data[8] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 - - l3.E3 - mux_65 mux_68 mux_106 mux_111 + + memory.addr2[1] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 - - l3.S3 - mux_81 mux_84 mux_107 mux_110 + + memory.data[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 - - l3.W6 - mux_97 mux_102 mux_72 mux_127 + + memory.addr1[0] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 - - l3.N6 - mux_113 mux_118 mux_123 mux_76 + + memory.data[0] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 - - l3.E6 - mux_1 mux_103 mux_88 mux_126 + + memory.data[6] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 - - l3.S6 - mux_17 mux_119 mux_122 mux_92 + + memory.addr2[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 - - l3.W9 - mux_66 mux_100 mux_105 mux_15 + + memory.data[3] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 - - l3.N9 - mux_82 mux_116 mux_11 mux_109 + + memory.data[9] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 - - l3.E9 - mux_98 mux_101 mux_104 mux_31 + + memory.addr2[2] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 - - l3.S9 - mux_114 mux_117 mux_27 mux_108 + + memory.data[5] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 - - l3.W12 - mux_2 mux_7 mux_120 mux_125 + + memory.addr1[1] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 - - l3.N12 - mux_18 mux_23 mux_121 mux_124 + + memory.data[1] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 - - l3.E12 - mux_67 mux_4 mux_9 mux_14 + + memory.data[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 - - l3.S12 - mux_83 mux_20 mux_10 mux_13 + + memory.addr2[1] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 - - l3.W15 - mux_99 mux_5 mux_8 mux_30 + + memory.data[4] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 - - l3.N15 - mux_115 mux_21 mux_26 mux_12 + + memory.addr1[0] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 - - l3.E15 - mux_3 mux_6 mux_24 mux_29 + + memory.data[0] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 - - l3.S15 - mux_19 mux_22 mux_25 mux_28 + + memory.data[6] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 - - l3.W18 - mux_32 mux_37 mux_42 mux_47 + + memory.addr1[2] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 - - l3.N18 - mux_48 mux_53 mux_43 mux_46 + + memory.data[2] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 - - l3.E18 - mux_64 mux_38 mux_41 mux_63 + + memory.data[8] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 - - l3.S18 - mux_80 mux_54 mux_59 mux_45 + + memory.addr2[2] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 - - l3.W21 - mux_96 mux_39 mux_57 mux_62 + + memory.data[5] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 - - l3.N21 - mux_112 mux_55 mux_58 mux_61 + + memory.addr1[1] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 - - l3.E21 - mux_33 mux_36 mux_74 mux_79 + + memory.data[1] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 - - l3.S21 - mux_49 mux_52 mux_75 mux_78 + + memory.data[7] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 - - l4.W0 - mux_65 mux_70 mux_40 mux_95 + + memory.addr2[0] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 - - l4.N0 - mux_81 mux_86 mux_91 mux_44 + + memory.data[3] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 - - l4.E0 - mux_97 mux_71 mux_56 mux_94 + + memory.data[9] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 - - l4.S0 - mux_113 mux_87 mux_90 mux_60 + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 - - l4.W4 - mux_34 mux_68 mux_73 mux_111 + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 - - l4.N4 - mux_50 mux_84 mux_107 mux_77 + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 - - l4.E4 - mux_66 mux_69 mux_72 mux_127 + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 - - l4.S4 - mux_82 mux_85 mux_123 mux_76 + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 - - l4.W8 - mux_98 mux_103 mux_88 mux_93 + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 - - l4.N8 - mux_114 mux_119 mux_89 mux_92 + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 - - l4.E8 - mux_35 mux_100 mux_105 mux_110 + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 - - l4.S8 - mux_51 mux_116 mux_106 mux_109 + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 - - l4.W12 - mux_67 mux_101 mux_104 mux_126 + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 - - l4.N12 - mux_83 mux_117 mux_122 mux_108 + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 - - l4.E12 - mux_99 mux_102 mux_120 mux_125 + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 - - l4.S12 - mux_115 mux_118 mux_121 mux_124 + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 - - l8.W0 - mux_0 mux_5 mux_10 mux_15 + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 - + l8.N0 - mux_16 mux_21 mux_11 mux_14 - - - l8.E0 - mux_32 mux_6 mux_9 mux_31 - - - l8.S0 - mux_48 mux_22 mux_27 mux_13 - - - l8.W8 - mux_64 mux_7 mux_25 mux_30 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 - + l8.N8 - mux_80 mux_23 mux_26 mux_29 - - - l8.E8 - mux_1 mux_4 mux_42 mux_47 - - - l8.S8 - mux_17 mux_20 mux_43 mux_46 - - - l1.W9 - l1.N9 l1.E9 l1.S9 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.N9 - l1.W9 l1.E9 l1.S9 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.E9 - l1.W9 l1.N9 l1.S9 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.S9 - l1.W9 l1.N9 l1.E9 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.W10 - l1.N10 l1.E10 l1.S10 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.N10 - l1.W10 l1.E10 l1.S10 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.E10 - l1.W10 l1.N10 l1.S10 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.S10 - l1.W10 l1.N10 l1.E10 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.W11 - l1.N11 l1.E11 l1.S11 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - l1.N11 - l1.W11 l1.E11 l1.S11 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.E11 - l1.W11 l1.N11 l1.S11 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.S11 - l1.W11 l1.N11 l1.E11 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.W12 - l1.N12 l1.E12 l1.S12 OG_1ST_0 OG_1ST_4 OG_1ST_8 - - - l1.N12 - l1.W12 l1.E12 l1.S12 OG_1ST_1 OG_1ST_5 OG_1ST_9 - - - l1.E12 - l1.W12 l1.N12 l1.S12 OG_1ST_2 OG_1ST_6 OG_1ST_10 - - - l1.S12 - l1.W12 l1.N12 l1.E12 OG_1ST_3 OG_1ST_7 OG_1ST_11 - - - ram9k.raddr_i[6] - mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W7 - - - ram9k.raddr_i[7] - mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N7 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 - - ram9k.raddr_i[8] - mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E7 - - - ram9k.raddr_i[9] - mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S7 - - - ram9k.raddr_i[10] - mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W15 - - - ram9k.waddr_i[6] - mux-0 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N15 - - - ram9k.waddr_i[7] - mux-12 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E15 - - - ram9k.waddr_i[8] - mux-24 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S15 - - - ram9k.waddr_i[9] - mux-36 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W7 + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 - - ram9k.waddr_i[10] - mux-48 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N7 + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 - - ram9k.data_i[27] - mux-0 mux-1 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E7 + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 - - ram9k.data_i[28] - mux-12 mux-13 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S7 + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 - - ram9k.data_i[29] - mux-24 mux-25 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W15 + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 - - ram9k.data_i[30] - mux-36 mux-37 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N15 + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 - - ram9k.data_i[31] - mux-48 mux-49 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E15 + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 - - ram9k.data_i[32] - mux-0 mux-1 mux-2 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.S15 + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 - - ram9k.data_i[33] - mux-12 mux-13 mux-14 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.W7 + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 - - ram9k.data_i[34] - mux-24 mux-25 mux-26 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.N7 + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 - - ram9k.data_i[35] - mux-36 mux-37 mux-38 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.E7 + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 - - ram9k.data_i[9] - mux-48 mux-49 mux-50 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.S7 + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 - - ram9k.data_i[10] - mux-0 mux-1 mux-2 mux-3 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.W15 + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 - - ram9k.data_i[11] - mux-12 mux-13 mux-14 mux-15 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.N15 + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 - - ram9k.data_i[12] - mux-24 mux-25 mux-26 mux-27 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.E15 + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 - - ram9k.data_i[13] - mux-36 mux-37 mux-38 mux-39 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.S15 + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 - - ram9k.data_i[14] - mux-48 mux-49 mux-50 mux-51 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.W7 + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 - - ram9k.data_i[15] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-6 mux-7 mux-8 mux-9 mux-10 mux-11 l8.N7 + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 - - ram9k.data_i[16] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 l8.E7 + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 - - ram9k.data_i[17] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-30 mux-31 mux-32 mux-33 mux-34 mux-35 l8.S7 + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 - - ram9k.bwen_ni[27] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 l8.W15 + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 - - ram9k.bwen_ni[28] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-54 mux-55 mux-56 mux-57 mux-58 mux-59 l8.N15 + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 - - ram9k.bwen_ni[29] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-7 mux-8 mux-9 mux-10 mux-11 l8.E15 + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 - - ram9k.bwen_ni[30] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-19 mux-20 mux-21 mux-22 mux-23 l8.S15 + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 - - ram9k.bwen_ni[31] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-31 mux-32 mux-33 mux-34 mux-35 l8.W7 + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 - - ram9k.bwen_ni[32] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-43 mux-44 mux-45 mux-46 mux-47 l8.N7 + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 - - ram9k.bwen_ni[33] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-55 mux-56 mux-57 mux-58 mux-59 l8.E7 + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 - - ram9k.bwen_ni[34] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-8 mux-9 mux-10 mux-11 l8.S7 + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 - - ram9k.bwen_ni[35] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-20 mux-21 mux-22 mux-23 l8.W15 + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 - - ram9k.bwen_ni[9] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-32 mux-33 mux-34 mux-35 l8.N15 + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 - - ram9k.bwen_ni[10] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-44 mux-45 mux-46 mux-47 l8.E15 + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 - - ram9k.bwen_ni[11] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-56 mux-57 mux-58 mux-59 l8.S15 + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 - - ram9k.bwen_ni[12] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-9 mux-10 mux-11 l8.W7 + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 - - ram9k.bwen_ni[13] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-21 mux-22 mux-23 l8.N7 + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 - - ram9k.bwen_ni[14] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-33 mux-34 mux-35 l8.E7 + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 - - ram9k.bwen_ni[15] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-45 mux-46 mux-47 l8.S7 + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 - - ram9k.bwen_ni[16] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-57 mux-58 mux-59 l8.W15 + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 - - ram9k.bwen_ni[17] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-10 mux-11 l8.N15 + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 - - ram9k.wen_ni[0] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-22 mux-23 l8.E15 + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 - - ram9k.ren_ni[0] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-34 mux-35 l8.S15 + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 - - ram9k.raddr_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-46 mux-47 l8.W7 + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 - - ram9k.raddr_i[7] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-58 mux-59 l8.N7 + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 - - ram9k.raddr_i[8] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-11 l8.E7 + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 - - ram9k.raddr_i[9] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-23 l8.S7 + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 - - ram9k.raddr_i[10] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-35 l8.W15 + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 - - ram9k.waddr_i[6] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-47 l8.N15 + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 - - ram9k.waddr_i[7] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-59 l8.E15 + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 - - ram9k.waddr_i[8] - mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 mux-8 mux-9 mux-10 l8.S15 + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 - - ram9k.waddr_i[9] - mux-12 mux-13 mux-14 mux-15 mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 l8.W7 + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 - - ram9k.waddr_i[10] - mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 mux-32 mux-33 mux-34 l8.N7 + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 - - ram9k.data_i[27] - mux-36 mux-37 mux-38 mux-39 mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 l8.E7 + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 - - ram9k.data_i[28] - mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 mux-56 mux-57 mux-58 l8.S7 + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 - - - - + + + + + - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 27319b206a2899733f0cbb1f6d44cb3bfa1533ac Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 18 Jan 2025 10:40:56 +0800 Subject: [PATCH 426/453] Create config.txt --- .../strong_vib/config/config.txt | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/config.txt new file mode 100644 index 00000000000..ab137e3b7da --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/config.txt @@ -0,0 +1,27 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif + +# Path to directory of architectures to use +archs_dir=arch/VIB + +# Add circuits to list to sweep +circuit_list_add=tseng.blif + +# Add architectures to list to sweep +arch_list_add=vib_test_arch.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +script_params=-starting_stage vpr --route_chan_width 138 --max_router_iterations 400 --device ultimate From 364ac60e9ce6b37401961c8b7349b9b20f4ad7f1 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 18 Jan 2025 10:42:55 +0800 Subject: [PATCH 427/453] Create golden_results.txt --- .../vtr_reg_strong/strong_vib/config/golden_results.txt | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/golden_results.txt new file mode 100644 index 00000000000..a512510d787 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +vib_test_arch.xml tseng.blif common 5.38 vpr 65.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 135 52 0 0 success unkown release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-49-generic x86_64 2025-01-16T17:23:42 yuanqiwang-virtual-machine /home/yuanqiwang/Wang/vtr/vtr-patch-1-old/vtr-verilog-to-routing-patch-1/vtr_flow/tasks 67284 52 122 1483 1605 1 1099 309 20 14 280 -1 ultimate 27.7 MiB 0.28 7177 63993 16752 32956 14285 65.7 MiB 0.35 0.01 3.57193 -517.324 -3.57193 3.57193 1.08 0.000907145 0.000734596 0.0683261 0.0559363 -1 9148 14 1.31729e+07 7.27569e+06 2.24313e+06 8011.19 0.60 0.126578 0.108805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 From 2f8191d97d22c7a9ac7eced2257041813ffe8b9e Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Sat, 18 Jan 2025 10:44:05 +0800 Subject: [PATCH 428/453] Update task_list.txt --- vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 35a4b13bb34..e3d721ea146 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -94,3 +94,4 @@ regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router regression_tests/vtr_reg_strong/strong_routing_constraints +regression_tests/vtr_reg_strong/strong_vib From d273cb22be5ac72ec7b1a8fa7bdbfe1a203aa0eb Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 11 Feb 2025 14:19:27 +0800 Subject: [PATCH 429/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index 29012ccfb94..9438cd48f97 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -1,24 +1,24 @@ .. _VIB: -VIB +VIB Architecture ============ -The VIB architecture adds modeling support for double-level MUX topology and bent wires. +The VIB architecture adds modeling support for double-level MUX topology and bent wires. Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. .. figure:: ../Images/VIB.png :align: center :height: 300 - VIB architecture. The connections between the inputs and outputs of the LB and the routing wires are all implemented within the VIB. + Figure 1. VIB architecture. The connections between the inputs and outputs of the LB and the routing wires are all implemented within the VIB. .. figure:: ../Images/double-level.png :align: center - Double-level MUX topology. + Figure 2. Double-level MUX topology. .. figure:: ../Images/bent_wires.png :align: center - Presentation for bent wires. + Figure 3. Presentation for bent wires. FPGA Architecture File Modification (.xml) -------------------------- From 27bdc8c599d30052823a986b2d3418932ab9a547 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 11 Feb 2025 14:27:40 +0800 Subject: [PATCH 430/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index 9438cd48f97..7ff34b9c579 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -2,7 +2,7 @@ VIB Architecture ============ -The VIB architecture adds modeling support for double-level MUX topology and bent wires. Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. +The VIB architecture adds modeling support for double-level MUX topology and bent wires. Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. Figure 2 shows an example of the detailed interconnect architecture in VIB. The CLB input muxes and the driving muxes of wire segments can share the same fanins. A routing path of a net with two sinks is presented red in the Figure. .. figure:: ../Images/VIB.png :align: center From 1eab1b3bf32ab8e658076f8c6f2532abe4fb13e3 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 11 Feb 2025 14:33:50 +0800 Subject: [PATCH 431/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index 7ff34b9c579..b10e0d4484b 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -2,7 +2,9 @@ VIB Architecture ============ -The VIB architecture adds modeling support for double-level MUX topology and bent wires. Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. Figure 2 shows an example of the detailed interconnect architecture in VIB. The CLB input muxes and the driving muxes of wire segments can share the same fanins. A routing path of a net with two sinks is presented red in the Figure. +The VIB architecture adds modeling support for double-level MUX topology and bent wires. In past, switch blocks have only one level of routing mutliplexers, whose inputs are driven by outputs of programmable blocks and routing tracks. + +Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. Figure 2 shows an example of the detailed interconnect architecture in VIB. The CLB input muxes and the driving muxes of wire segments can share the same fanins. A routing path of a net with two sinks is presented red in the Figure. .. figure:: ../Images/VIB.png :align: center From 395d1529ebbef18e781ce08bdf69980e4a449c82 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 11 Feb 2025 14:35:33 +0800 Subject: [PATCH 432/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index b10e0d4484b..c4a475495c9 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -2,7 +2,7 @@ VIB Architecture ============ -The VIB architecture adds modeling support for double-level MUX topology and bent wires. In past, switch blocks have only one level of routing mutliplexers, whose inputs are driven by outputs of programmable blocks and routing tracks. +The VIB architecture adds modeling support for double-level MUX topology and bent wires. In past, switch blocks have only one level of routing MUXes, whose inputs are driven by outputs of programmable blocks and routing tracks. Now outputs of programmable blocks can shape the first level of routing MUXes, while the inputs of second level involves the outputs of first level and other routing tracks. This can reduce the number and input sizes of routing MUXes. Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. Figure 2 shows an example of the detailed interconnect architecture in VIB. The CLB input muxes and the driving muxes of wire segments can share the same fanins. A routing path of a net with two sinks is presented red in the Figure. From 1f7a84538142e86de3a6aa0a90b86dabb039ad59 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 11 Feb 2025 14:51:02 +0800 Subject: [PATCH 433/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index c4a475495c9..5b9035312e7 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -16,6 +16,8 @@ Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is c :align: center Figure 2. Double-level MUX topology. + +Figure 3 shows the modeling for bent wires. A bent L-length wire is modeled as two segments in CHANX and CHANY respectively connected by a delayless switch. The orange and red arrows represent conterclockwise and clockwise bent wires respectively. .. figure:: ../Images/bent_wires.png :align: center From 1d161b5d60d3d0fa263f26b6bc67877a603440df Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 11 Feb 2025 14:54:40 +0800 Subject: [PATCH 434/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index 5b9035312e7..87d297a5542 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -17,7 +17,7 @@ Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is c Figure 2. Double-level MUX topology. -Figure 3 shows the modeling for bent wires. A bent L-length wire is modeled as two segments in CHANX and CHANY respectively connected by a delayless switch. The orange and red arrows represent conterclockwise and clockwise bent wires respectively. +Figure 3 shows the modeling for bent wires. A bent L-length wire is modeled as two segments in CHANX and CHANY respectively connected by a delayless switch. The orange and red arrows represent conterclockwise and clockwise bent wires respectively. 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z@IJnYQZGH8$lrX20oX;^HsiCTgj$u=GyCKOUZRq4i7F=*b`cIyi6yRk4`3J7+XY_cnL(52Pdgr8lAFD>)B%c@1oD1CCb`?09XNuApN#`vws__H zwHYXYEd+TDe|V8s<^sb&NlU=%y(%XSIHaFBRoOF_HQ*|4~IgV-vsFU$LB^-1z(A{8~HvaT`84`AfM5}eY(nYzWmdgR|kEaIA zS3t$ak7he#+H;qsTEw6qwY0Kx1PG`=k=?GsOl$ZSM64V;#%F(D$$b~KzQIm~?--m9 z-5zI15tArKa1Xe}2joe3gBAl>d~Vk7hzb`yyDo9WJmTtm>p1hZ7qGmS^;NzT5@Ymo zlW#9*C$n?0fI2Lr=nJEAmmPfXIK|>;OW26MCQ^iNn>;g%vj4dNz_`Vw#TQj8I-5d~ zkdQcE}spO(_QazkAm8*?VN#q~F%6>=0K;K`IQ8}RAMkQEF>fq4B z<1i^1UEAnZW}_B?FaT6`c>*)kT<^An519QEKQb^8O!Wwr(-35d{o}EtQe(Q{T_?;8 zWCVJa0L;wVuhM2tSyLndz3p>5`Sb-G)TKq2DCVCVP}3~HF`wv+1h>4f1LI6`-8jfUO+|~sthBqj$wDi7H5t|aQX{q3A@IDP#54-^C z=LSBMC&NmcGLKEmMNVq=Ys+QpX?y<(2H_4m2|7~uDb{b81OO^Nym>D!Yp=|68Bl)^ z%t7VIGlH)DcQ|Jysyne%Ol!?A(b7mnWZdt=_s81`tpI!j#7x~G10bJpbIQE%FE96q zHd{dB!%0_tJWW1?)AQVfZv8#U#@C8SCnsbF*JJ8^-*#PtJwO?O;D&H03yAfczPN)0 zcPF=; Date: Tue, 11 Feb 2025 15:26:08 +0800 Subject: [PATCH 439/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index 87d297a5542..665aa7b6559 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -65,6 +65,8 @@ The content within the ```` tag consists of a group of ```` tags. :req_param pbtype_name: The name of the block type (e.g. clb, memory) that this VIB connects to. + + .. note:: A block (e.g. clb, dsp) is connected to the VIB on its top-right side, so the input and output pins of the block should be on the top or right side. :req_param vib_seg_group: The number of the segment types in this VIB. @@ -124,6 +126,16 @@ The ``content`` of ```` tag consists of a ```` tag :req_param content: The details of each MUX. + +The ``content`` of ```` tag consists of many ```` tags. + +.. arch:tag:: content + +:req_param name: + Name of the MUX. + + :req_param content: + A ```` tag to describe what pins and wires connect to this MUX. For example: @@ -145,6 +157,16 @@ The ```` tag in ```` describes nodes that connects to the MUX. ``clb. :req_param content: The details of each MUX. + +The ``content`` of ```` tag consists of many ```` tags. + +.. arch:tag:: content + +:req_param name: + Name of the MUX. + + :req_param content: + A ```` tag to describe where this MUX connect to and a ```` tag to describe what pins and wires connect to this MUX. For example: From 2e9d87d15a2a8e8d35d051b2d217914ecd016218 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Tue, 11 Feb 2025 15:27:59 +0800 Subject: [PATCH 440/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index 665aa7b6559..ccde48bfb90 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -131,7 +131,7 @@ The ``content`` of ```` tag consists of many ```` tags. .. arch:tag:: content -:req_param name: + :req_param name: Name of the MUX. :req_param content: @@ -162,7 +162,7 @@ The ``content`` of ```` tag consists of many ```` tags. .. arch:tag:: content -:req_param name: + :req_param name: Name of the MUX. :req_param content: From d1d210ed3dda55269f2da7780667d1575228af21 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Wed, 12 Feb 2025 11:51:12 +0800 Subject: [PATCH 441/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index ccde48bfb90..95565bdc338 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -197,3 +197,19 @@ Content inside this tag specifies VIB grid layout to describe different VIBs app :req_param content: The content should contain a set of grid location tags. For grid location tags of vib_layout see :ref:`fpga_architecture_description`; ref:`grid_expressions` + +For example: + +.. code-block:: xml + + + + + + + ... + + + +In this VIB grid layout, ``perimeter``, ``fill``, ``col`` and so on are tags in original ```` tag to describe positions of each type of VIB block. The attibute ``type`` should correspond to the ``name`` of a ```` tag in ````. +Besides, the ``pbtype_name`` of corresponding ```` must be the same as the physical block type at this position. In this example, IO blocks are located on the perimeter of the layout. Memory blocks are on column 5 and CLBs are on the rest positions. The ``vib_io``, ``vib_clb`` and ``vib_memory`` are different types of vib blocks corresponding to IO, CLB and memory blocks respectively. From 5ba8a0e3cf3136e54654b3f40d9bc15a716aeda9 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Wed, 12 Feb 2025 11:51:45 +0800 Subject: [PATCH 442/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index 95565bdc338..b1e2696ca22 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -212,4 +212,6 @@ For example: In this VIB grid layout, ``perimeter``, ``fill``, ``col`` and so on are tags in original ```` tag to describe positions of each type of VIB block. The attibute ``type`` should correspond to the ``name`` of a ```` tag in ````. -Besides, the ``pbtype_name`` of corresponding ```` must be the same as the physical block type at this position. In this example, IO blocks are located on the perimeter of the layout. Memory blocks are on column 5 and CLBs are on the rest positions. The ``vib_io``, ``vib_clb`` and ``vib_memory`` are different types of vib blocks corresponding to IO, CLB and memory blocks respectively. +Besides, the ``pbtype_name`` of corresponding ```` must be the same as the physical block type at this position. + +In this example, IO blocks are located on the perimeter of the layout. Memory blocks are on column 5 and CLBs are on the rest positions. The ``vib_io``, ``vib_clb`` and ``vib_memory`` are different types of vib blocks corresponding to IO, CLB and memory blocks respectively. From 4341b2b3bfc56fb2114ead116658286a5e210be6 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Wed, 12 Feb 2025 13:18:26 +0800 Subject: [PATCH 443/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 51 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 44 insertions(+), 7 deletions(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index b1e2696ca22..fa3eac1c042 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -143,15 +143,15 @@ For example: - clb.O[0] clb.O[8] clb.O[12:16] + clb.O[0] clb.O[1:3] clb.O[4] - L1.E2 L1.W2 L1.S8 L1.N8 + L1.E1 L1.S1 L2.E0 ... -The ```` tag in ```` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.E2`` means the track ``2`` in the ``East`` direction of ``L1`` segment. +The ```` tag in ```` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.E1`` means the track ``1`` in the ``East`` direction of ``L1`` segment. .. arch:tag:: content @@ -175,16 +175,53 @@ For example: clb.I[0] - clb.O[0] clb.O[8] f_mux_0 + clb.O[4] f_mux_0 f_mux_1 - L1.S1 - L1.E1 L1.W1 f_mux_0 f_mux_1 + L1.E1 + L1.S2 f_mux_0 f_mux_1 ... -The ```` tag describes the node this MUX connects to. ``clb.I[*]`` means input pin(s); ``L1.S1`` means the track ``1`` in the ``South`` direction of ``L1`` segment. The ```` tag in ```` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.E2`` means the track ``2`` in the ``East`` direction of ``L1`` segment. ``f_mux_0`` means the name of the specific first stage MUX. +The ```` tag describes the node this MUX connects to. ``clb.I[*]`` means input pin(s); ``L1.E1`` means the track ``1`` in the ``East`` direction of ``L1`` segment. The ```` tag in ```` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.S2`` means the track ``2`` in the ``South`` direction of ``L1`` segment. ``f_mux_0`` means the name of the specific first stage MUX. + +Here is a complete example of the ```` tag: + +.. code-block:: xml + + + + + + + + clb.O[0] clb.O[1:3] clb.O[4] + + + L1.E1 L1.S1 L2.E0 + + + + + clb.I[0] + clb.O[4] f_mux_0 f_mux_1 + + + L1.E1 + L1.S2 f_mux_0 f_mux_1 + + + + + +Its corresponding detailed architecture is shown in Figure 4. + +.. figure:: ../Images/example.png + :align: center + :height: 300 + + Figure 4. The corresponding detaied architecture of the example. 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zQd%1S(cj9FH2Y|zYr_4}t0m`y(d1l7>jLk)Z!>+a#;hNJ)3Sl=&w9N|E&<^Mf zE-*Y%rkm58c$#YC2@`>~yrjevVBg~u@tPYL>xQcnP;XvGr|)+Uyb(SrjsoqL>5eai z7nAGjC)IC?$$5A`FL=_3?KhhzK!hWwVjGcT zh@Tw$$>#NJAm>$0wf$?%tJ1croOz^MUp&}po4&!dYh|TmJp)oH-;=MRR6L}(T*!z| znKE5m^)dR2bB~zvp7GgR@Nr`&=O^{dWu+zVZSN$#aJW%FinaS|-w7kM_4F_AnG%By zqC-}W**;k3lzMs(Q`#%?p;e5Bv7>ux(T)%2ZefNZwhzhT=Tt7cq&${;fH{ydS=rVY zHncLAY)mMHU7dW;S;k8g*^f0EJrP_tWHf z6B)y7*WNX{G<@KTW(uvX#Ak~)5LS|Mah8AX{c&xir-N5)s@`=?gjfC*N`q$mT*Um< zPTo~%6pH-l`LV){(*rs0w~yJ~3C8&k#a2J~;tffRgFW)PC)C*(8Vo-F`jnO${m_(D z9Bo?76#uIzlH!lh7)JceBDn0oXD-x;6A$m|X=qZbXIdlWNyjEZ?sWd9eY^~-gNK$= zx7v;Jw_?N+cBxl4=wIX9?&CS|s_FB!2~{eoWfA412Nh#NamM73*gewtJH0u~gF z)R65(8@TwI^8F}Ljt>m8CfrNSX!>8gUH9#mdN{oMCv~pcPX`oAXM?~1LJ6q;|DXTA(KA+n*5AcVacC&oBUBNF4RuCMM>Sg+d-MMQN;)C3 literal 0 HcmV?d00001 From 8fcd273bc116ee994d9f3c7d3568ec72be72f5d7 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Wed, 12 Feb 2025 13:19:36 +0800 Subject: [PATCH 445/453] Rename example.png to vib_example.png --- doc/src/Images/{example.png => vib_example.png} | Bin 1 file changed, 0 insertions(+), 0 deletions(-) rename doc/src/Images/{example.png => vib_example.png} (100%) diff --git a/doc/src/Images/example.png b/doc/src/Images/vib_example.png similarity index 100% rename from doc/src/Images/example.png rename to doc/src/Images/vib_example.png From 0468c2994ed8f9377f854743819d95b026dbdc78 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Wed, 12 Feb 2025 13:20:07 +0800 Subject: [PATCH 446/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index fa3eac1c042..e3375b0a444 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -217,7 +217,7 @@ Here is a complete example of the ```` tag: Its corresponding detailed architecture is shown in Figure 4. -.. figure:: ../Images/example.png +.. figure:: ../Images/vib_example.png :align: center :height: 300 From 8c40b19d20ff0344521de0a66a1abba372ea4c75 Mon Sep 17 00:00:00 2001 From: Wang Yuanqi <101231450+Wang-Yuanqi-source@users.noreply.github.com> Date: Wed, 12 Feb 2025 13:20:52 +0800 Subject: [PATCH 447/453] Update VIB.rst --- doc/src/vpr/VIB.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst index e3375b0a444..b48675ab174 100644 --- a/doc/src/vpr/VIB.rst +++ b/doc/src/vpr/VIB.rst @@ -219,7 +219,7 @@ Its corresponding detailed architecture is shown in Figure 4. .. figure:: ../Images/vib_example.png :align: center - :height: 300 + :height: 600 Figure 4. The corresponding detaied architecture of the example. From cab1db1f5b917ba33f2a755759e1308756fc6051 Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Thu, 24 Apr 2025 12:03:47 -0400 Subject: [PATCH 448/453] Update OpenFPGA (#2983) * [vpr][ap] remove redundant print_pb * Fix styling regressions * Add reset_bimap helper method to AtomPBBimap * Remove copying empty bimap from global context to cluster legalizer * Refactor is_atom_blk_in_pb function to get two t_pb* arguments * Fix minor styling issues * [vpr][pack] reomve redundant function calls * [vpr][place] fix estimated_wl var name * [APPack] Updated How APPack Adheres to Given Placement The original implementation of APPack was focused on reconstructing a given flat placement. This can cause issues if the given flat placement disagrees with the decisions of the packer. Instead, updated APPack so that it treats the flat placement as a hint to help guide how it performs clustering. Added the following new features: - APPack computes the location of clusters based on the centroid of the molecules packed within. - APPack attenuates the gain terms of candidates based on their distance from the cluster. - APPack drops candidates which are too far from the cluster being created. Remove adding molecules near to the position of the cluster. This had similar affects to unrelated clustering and should be investigated separately later. With these changes to APPack, the AP flow now improves WL of circuits by 1-3% at the expense of up to 15% runtime compared to the default VPR flow. * make format * [vpr][route] remove redundant functions from rr_graph2 * make format * [vpr][route] remove redundant functions from rr_graph2 * [libs][rr_graph] change rr_node_indices value type to RRNodeId * fix formatting issues * make format * [AP][GlobalPlacement] Improved Partial Legalizer Legality Updated the partial legalizer to now take into account block types when spreading blocks. This will create windows around overfilled bins that is aware of which block types are overfilled and how large the window needs to be to accomodate them. It also takes these block types into account when spreading to only allow blocks to spread into sub-windows that they can exist in. This improves quality but was detremental to performance, so some performance improvements were needed. To improve the performance of the partial legalizer, I split the problem into groups of models which must be spread together. This allows us to create tighter windows and can make some parts of the legalizer more efficient. Create a model grouper class which forms the model pack patterns into a graph and find disconnected sub-graphs to form the model groups. Also improved the window generation by pre-clustering the overfilled bins before creating the windows. This sped up the window generation code since less windows overlap. * [vpr][rr_graph] fix comment * [AP][Solver] Supporting Unfixed Blocks When no fixed blocks are provided by the user, the AP flow can still work. Currently, in the first iteration, the solver will put all blocks at 0,0 and use the legalized solution in the next iteration as fixed points. Instead of (0,0), it makes more sense to put the blocks in the center of the device. Also added a guess to the solver to help CG converge faster each iteration. Added a regression test to ensure that not describing the fixed blocks is supported. * [vpr] rename arch_opin_between_dice_switch to arch_inter_die_switch since it is used for both 3d CB and 3d SB * [arch] fix 3d sb arch delay * [arch] add ipin_cblock switch * make format * Update clang-format version to 18 This is the version that is installed by default on Ubuntu 24.04 which we currently run CI and testing on. * Fix formatting to be compliant with clang-format-18 * [APPack] Flat-Placement Informed Unrelated Clustering Used flat placement information provided by APPack to try and select better unrelated candidates. This searches for candidates as close to the flat placement position of the cluster. There are two parameters that control how this is performed: 1) max_unrelated_tile_distance decides how far the algorithm will search for unrelated candidates. The algorithm will check for candidates in the same tile as the cluster, and then will search farther and farther out 2) max_unrelated_clustering_attempts decides how many failing attempts the cluster will try unrelated clustering. This matches the option of the same name in the candidate selector class; but this was made separate since likely it will be different for APPack. * apply comments * make format * [vpr][rr_graph] remove flat router parameter from vpr_create_device * [vpr][stats] add print_resource_usage * [vpr][base] moove calculate_device_util to stats * [vpr][pack] include required lib * add print_device_util to stats * [vpr][base] print resource usage and device util only if clb netlist is valid * [vpr][base] remove unused param * [vpr][base] remove var from doxygen comment * [vpr][base] check whether instnace exists in netlist * apply comments * make format * [vpr][place] add skip anneal option * [vpr][place] pass skip_anneal to placer * [vpr][place] update constraint doc * [vpr][place] minor update to the doc * [vtr][script] add run dir to parse script * [script] remove get_latest_run_dir_number out of util * [script] use run dir name instead of only accepting the run dir num * [script] rename to set_global_run_dir * make format-py * fix formatting issue * [script] fix when run dir is not found * make format-py * fix python lint * add NestedNetlistRouter and custom thread pool * fix formatting issues * [script] add class methods * fix python lint * fix pylint * [place] fix the bug to skip anneal when analytic placer is enabled * [place] rename skip_anneal to quench_only * [place] add doc for place_quench_only * [AP][GlobalPlacment] Added Bound2Bound Solver The Bound2Bound net model is a method to solve for the linear HPWL objective by iteratively solving a quadratic objective function. This method does obtain a better quality post-global placement flat placement; at the expense of being more computationally expensive. Found that this solver also has numerical stability issues. This may cause the CG solver to never converge which will hit the iteration limit of 2 * the number of moveable blocks. This makes this algorithm quadratic with the number of blocks in the netlist. To resolve this, set a custom iteration limit. This seems to work well on our benchmarks but may need to be revisited in the future. * [AP][GlobalPlacement] Updated B2B Solver According to Feedback * [vpr][place] rename get_initial_move_lim to get_place_inner_loop_num_move * fix a typo * Bump libs/EXTERNAL/libcatch2 from `914aeec` to `76f70b1` Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `914aeec` to `76f70b1`. - [Release notes](https://github.com/catchorg/Catch2/releases) - [Commits](https://github.com/catchorg/Catch2/compare/914aeecfe23b1e16af6ea675a4fb5dbd5a5b8d0a...76f70b1403dbc0781216f49e20e45b71f7eccdd8) --- updated-dependencies: - dependency-name: libs/EXTERNAL/libcatch2 dependency-version: 76f70b1403dbc0781216f49e20e45b71f7eccdd8 dependency-type: direct:production ... Signed-off-by: dependabot[bot] * fix a few typos * added a doxygen comments * use VTR_LOGV_ERROR instead of is statements * doxygen comment for load_rr_edge_overrides() * make format * only override edge delay and not electrical stuff * [script] apply comments * [script] rename get_latest_run_dir to get_active_run_dir * [AP] Tuned the AP Flow The AP flow has many tunable knobs which trade-off quality and run time. Went through each of the knobs to find a good combination. Updates to the partial legalizer: - Reversed the order that unplaced large blocks are inserted into partitions. - Increased the bin cluster gap from 1 to 2 On the largest VTR benchmarks, this decreased the number of overfilled bins after legalization by 15% and the average overfill of each of those bins by 40%. On Titan, the number of overfilled bins decreased by 32% and the average overfill decreased by 2.5%. Updates to the analytical solver and global placer: - Allowed the B2B solver to stop early if it seems to be converging. - Changed the anchor weights from a linearized term to a quadratic term. - Decreased the distance epsilon from 0.5 to 0.01. - Increased the max number of B2B solver iterations from 6 to 24 - Decreased the CG iteration cap from 200 to 150. - The global placer saves the best legalized placement it has seen and returns it as its final result. On the largest VTR benchmarks, this decreased the post GP HPWL by 22% and decreased the GP run time by 17%. On Titan, the post GP HPWL decreased by 25%, and the GP run time decreased by 19%. Updates to APPack: - Decreased the max candidate distance from 0.5 (W + H) to 0.1 (W + H) for logical blocks. - Decreased the max candidate distance for all other blocks to 0.35 (W + H) - Lowered the attenuation distance threshold from 2.0 to 1.75. - Decreased the attenuation value at the distance threshold to 0.35. - Increased the max unrelated clustering distance from 1 to 5. - Increased the max number of unrelated clustering attempts from 2 to 10. - Turned off all APPack optimization for RAM blocks. On the largest VTR benchmarks, this decreased the wirelength by 2% over the un-tuned AP flow, with a 2.8% decreased pack time. On Titan, the post FL wirelength decreased by 6% and the post routing wirelength decreased by 2.6%, with a 0.7% decrease in pack time. Updates to initial placement: - Fixed oversight with how the centroid was being calculated. - Increased the range limit when searching for nearby locations when the location a cluster wants is take from 15 to 60. This further improved the post routing wirelength of Titan to 4.4% better than the un-tuned AP flow. I found that there are a lot of issues with the initial placement which may be blocking a large amount of gains. Will be investigating the initial placement code soon. * [Prepacker] Moved the Prepacker Out of Try Pack The AP flow makes its own prepacker which it uses throughout. However, a full legalizer in the AP flow (APPack) uses the try_pack method which creates its own prepacker. This creates two independent prepacker objects when only one is needed. Move the construction of the prepacker object into vpr_api and have it get passed into the try_pack function. * [script] afix the bug with get_next_run_dir * python lint * [vpr][place] update get_place_inner_loop_num_move comment * [vpr][place] prrint number of moves per temp after getting the number * make format * add a unit test for reading edge override file * Add edge_id() method to find an edge that connects given src and sink nodes * replace for loop with edge_id() method that return an edge connecting given src/sink nodes * add doxygen comment for edge_id() method * verify overridden edge attribute in the unit test * move operator==() and hash function of t_rr_switch_inf to physical_types.cpp * add test_read_rr_edge_override.txt * make format * add InsertNewlineAtEOF: true to .clang-format * make format to add new line at EOF * init value of false for load_flat_placement * [Pack][Timing] Abstracted How Timing is Used in the Packer Timing was intermixed into the packer. It appears as though the code originally was designed to recalculate the timing information every so often in the packer, but the idea was abandoned. This left timing code in disperse locations around the Packer and the timing was being recomputed every time clustering was restarted which was unecessary. Collecting all of the timing information from the Packer into a single object called PreClusterTimingManager which abstracts all of the timing info in the Packer. The ultimate goal is to bring this Manager class into the AP flow to be used together with the Global Placer. By sharing this manager class, the AP flow may be able to update the timing info with flat placement information to make the timing more accurate. * [AP][Timing] Added Basic Net Weighting Added basic timing awareness to the AP flow by weighting nets in the AP solver by their criticality (the max criticality of all edges through that net). This makes the solver try to minimize the length of nets that are more critical more than nets that are less critical (according to the pre-clustering timing analyzer). Added a command-line option to tradeoff between timing and wirelength in the AP flow. * [AP][Test] Added Titan Nightly Test of WL-Driven AP Flow * enum class for graph type * use std::vector for clb_to_clb_directs * doxygen comment for t_unified_to_parallel_seg_index * doxygen comment for get_parallel_segs() * replace t_seg_details* with std::vector * get_seg_track_counts() returns std::vector + doxygen comment * move local var declarations from beginning of alloc_and_load_seg_details to where they are used * pass t_chan_width by reference * remove get_ordered_seg_track_counts() * remove t_mux, t_pin_spec, and t_mux_size_distribution structs * add docs for vtr::thread_pool * add is_root_location to grid * remove unnecessary calls to clear() * [AP][InitialPlacement] Improved Initial Placement Found that the Initial Placer stage of the AP flow (after APPack, but before Detailed Placement) was not working as expected. The intention was that clusters would be placed at their centroid location accordin to the flat placement, and if that site was illegal or taken it would take a nearby point instead (falling back on the original initial placer if nothing can be found). To achieve this, I was using a method called find_centroid_neighbor which I thought would return the nearest legal location to the given location. This was not correct. This method just creates a bounding-box and tries to find a random point in that box around the given point. This was causing our AP flow to move clusters WAY farther than they wanted, which moved them into places other clusters wanted to go. This was also not exhaustive, so it was often falling back on the original approach which was putting clusters in practically random locations. All of this was causing the post-FL placement from the AP flow to actually have worse quality than the default AP flow! To resolve this, I wrote the actual method I was intending. It performs a BFS-style search from the src location to all legal locations and returns the closest one. By doing this BFS on the compressed grid, I found that this is actually quite efficient. With these changes, I found that the quality of the post-FL placement more than doubled and the average atom displacement from the GP solution decrease dramatically. * move t_seg_details, t_chan_seg_details, and t_chan_details to rr_types.h * fix compilation error in test_connection router and the warning in rr_graph2.cpp * move t_sblock_pattern to rr_types.h * make format * [vpr][place] remove get_net_wirelength_from_layer_bb_ from netcosthandler class * [vpr][place] make get_net_wirelength_from_layer_bb_ static function and update its parameters * [vpr][place] use appropiate wirelength est function * make format * [test] add strong 3d * fix signal 6 in stratix 10 arch strong test * apply PR comments * add the requested comments * update file_formats.rst * add --read_rr_edge_override to command_line_usage.rst * remove duplicate text in command_line_usage.rst * [vpr][place] apply review comments * make format * make format * [vpr][tileable] add include * remove unused function linear_regression_vector() * add write_channel_occupancy_to_file() * write channel coordinate and occupancy percentage to file * make columns aligns in channel utilization files * update submodule * make format * [libs][arch] return -1 if valid index is not found * make format * [libs][arch] comment unused vars * refactor the code to use the same code for both x and y channels * [libs][pugiutil] delete pointer * [libs][pugiutil] format issue * fix format * [libs][archfpga] comment parse_pin_name * [libs][encrypt] break the line to read file * [vpr][base] call setupvipinf if vib_infs is not empty * [libs][encrypt] initialize plaintext only if file is open * [libs][encrypt] use rdbuf to read a file to avoid gcc-13 warning * [libs][decrypt] rading a file in safe way to prevent gcc13 warning * [vpr][vib_grid] fix type name if type is nullptr * [vpr][tileable] resize if segment inf size is not zero * [vpr][tileable] use empty method instead of checking size * [vpr][tileable] set the size when defining the vector (gcc warning) * fix format * Add Github action to close stale issues The added workflow will close up to 30 old issues every day. Issues that have been inactive for more than a year will be first marked as stale, and if they remain stale after 15 days they will be automatically closed. * Add documentation for automatic issue closure * [test] fix strong constraint * [lib][arch] check num_interconnect is bigger than zero * [vpr][route] add a condition to not increment delta_seg if the segment is on the edge * [vpr][route] fix max seg idx * fix formatting * Change some internal packer APIs to not use C-style arrays This commit changes some functions that used C-style arrays to use std::vector instead. Previously we used the .data() method of std::vectors to pass a pointer to these functions. * pass by reference and typo * Clean up prepacker This commit changes two functions in the prepacker to get the specific element of the array they work with and not the entire array. * Change vector variable name to be more inline with the current style * remove scratch vectors from Move context * NetCostHandler is the owner of all bb-related data * remove PlacerMoveContext * define MoveGenerator::first_rlim * use #pragma once in move generator header files * make format * fix typo * get_bb_from_scratch_() accepts use_ts as its argument * [libs][librrgraph] update echo file of rr graph * [test][strong] update golden result * [test] update strong tileable golden result * explain what RR edge override feature is useful for * [test][tileable] update golden results * add comment for MoveGenerator::first_rlim * [STA] Updated SDF File Generation to Include Min Delays The SDF file generated by the post-implementation netlist writer was only using the max delays of timing connections in the timing graph. In the SDF file, it set all values of the rising and falling triples to the max delay. When using this SDF file for external timing analysis, the minimum timing (hold) paths were incorrect. Updated the netlist writer to work with triples instead of bare delays. This allows (minimum, typical, maximum) delays to be passed through the different functions and be printed cleanly. For standard delay signals in the circuit (not setup / hold times) Tatum provides the minimum delays. These are now being printed in the SDF file and the minimum timing paths are being found correctly in the external timing analyzer. Cleaned up some parts of the netlist printing code as well. 1) netlist_writer.cpp declared many functions in the global scope which may cause conflicts at link time in VTR. Put all of these methods in anonymous namespace to prevent this. 2) The code was casting the delays from seconds to picoseconds in strange places. This was tricky to work with since these are both stored as doubles. Changed all of the code to only work with delays in seconds, and only cast to picoseconds when printing. 3) General cleanup of the header file and the include files. * [STA] Updated How Un-Initialized Delay Triples are Handled Thank you to Fred Tombs for pointing out this issue! * [AP][InitialPlacement] Created Isolated AP Flow The old Initial Placer used in the AP flow was constructed within the initial placer of the non-AP flow. This forced the AP flow to try to place blocks one at a time with minimum displacement. This is non-ideal since blocks that were placed earlier were being getting first picks at locations, which may displace a future cluster which may be a better fit for that location. Separated out the AP initial placement code. For AP, initial placement is done in passes. The first pass will try to place clusters exactly at the tile that the centroid of all atoms within the cluster want to be placed (according to the global placement). Any clusters that could not be placed are reserved for the next pass. The second pass will allow clusters to be placed within 1 tile of their centroid. All subsequent passes will allow cluster to be placed exponentially farther from their centroid. The initial placement terminates when all clusters have been placed or if the max displacement is the size of the entire device. The clusters are sorted based on the size of the macro that contains them and the variance of the placement of the atoms within the macro. This allows large macro blocks with low variance to be placed first. * add doxygen comment for X_coord, Y_coord, and layer_coord * remove X_coord and Y_coord from feasibe_region_move_generator * add comment explaining ts and permanent data members * make format * [AP] General Fixed/Unfixed Blocks Cleanup Fixed a couple of small known issues around the AP flow related to how we handle fixed blocks. Offset the fixed block locations by 0.5 such that they are no longer on the edge. Previously, fixed blocks were placed at the root location of tiles. This was a problem since atoms would want to be generally close to the fixed block and may be biased to the bottom/left tiles to the fixed-block tile. This does not handle large tiles, but will help in general. If no fixed blocks are provided, the AP solver will always produce the trivial solution (all blocks placed on top of one another anywhere on the device). We were wasting time running bound2bound to solve this and the solution was probably being put on the bottom-left corner (0,0) which is not ideal. Instead of running bound2bound during the first iteration in this case, just placed all blocks in the center of the device. This greatly speeds up the first iteration when no fixed blocks are provided. * Remove atom_net global context mutation from packer * [vpr][tileable_rr_graph] fix rr_switch usage --------- Signed-off-by: dependabot[bot] Co-authored-by: Amir Poolad Co-authored-by: Amir Poolad <54797949+AmirhosseinPoolad@users.noreply.github.com> Co-authored-by: AlexandreSinger Co-authored-by: AlexandreSinger <49374526+AlexandreSinger@users.noreply.github.com> Co-authored-by: vaughnbetz Co-authored-by: Soheil Shahrouz <80951211+soheilshahrouz@users.noreply.github.com> Co-authored-by: Duck Deux Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Co-authored-by: soheilshahrouz --- .clang-format | 9 +- .github/scripts/install_dependencies.sh | 2 +- .github/workflows/nightly_test.yml | 6 +- .github/workflows/nightly_test_manual.yml | 106 + .github/workflows/stale.yml | 31 + .github/workflows/test.yml | 3 +- .gitmodules | 4 +- .gitpod.Dockerfile | 1 + CHANGELOG.md | 58 + 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vpr/src/pack/verify_flat_placement.cpp | 100 + vpr/src/pack/verify_flat_placement.h | 37 + vpr/src/place/RL_agent_util.cpp | 47 +- vpr/src/place/RL_agent_util.h | 4 + vpr/src/place/analytic_placer.cpp | 53 +- vpr/src/place/analytic_placer.h | 13 +- vpr/src/place/annealer.cpp | 52 +- vpr/src/place/annealer.h | 10 +- vpr/src/place/compressed_grid.cpp | 4 +- vpr/src/place/compressed_grid.h | 65 +- vpr/src/place/cut_spreader.cpp | 43 +- vpr/src/place/cut_spreader.h | 4 +- .../PlacementDelayModelCreator.cpp | 80 + .../delay_model/PlacementDelayModelCreator.h | 30 + .../compute_delta_delays_utils.cpp | 966 ++++++++ .../delay_model/compute_delta_delays_utils.h | 56 + .../place/delay_model/delta_delay_model.cpp | 136 ++ vpr/src/place/delay_model/delta_delay_model.h | 47 + .../delay_model/override_delay_model.cpp | 282 +++ .../place/delay_model/override_delay_model.h | 112 + .../place/delay_model/place_delay_model.cpp | 78 + vpr/src/place/delay_model/place_delay_model.h | 76 + .../place/delay_model/simple_delay_model.cpp | 132 ++ .../place/delay_model/simple_delay_model.h | 39 + vpr/src/place/grid_tile_lookup.cpp | 9 +- vpr/src/place/grid_tile_lookup.h | 148 +- vpr/src/place/initial_noc_placement.cpp | 11 +- vpr/src/place/initial_noc_placment.h | 2 + vpr/src/place/initial_placement.cpp | 834 ++++++- vpr/src/place/initial_placement.h | 12 +- .../centroid_move_generator.cpp | 18 +- .../move_generators/centroid_move_generator.h | 12 +- .../critical_uniform_move_generator.cpp | 16 +- .../critical_uniform_move_generator.h | 11 +- .../feasible_region_move_generator.cpp | 60 +- .../feasible_region_move_generator.h | 13 +- .../move_generators/manual_move_generator.cpp | 14 +- .../move_generators/manual_move_generator.h | 21 +- .../move_generators/median_move_generator.cpp | 77 +- .../move_generators/median_move_generator.h | 22 +- .../place/move_generators/move_generator.cpp | 9 +- .../place/move_generators/move_generator.h | 55 +- .../simpleRL_move_generator.cpp | 46 +- .../move_generators/simpleRL_move_generator.h | 81 +- .../move_generators/static_move_generator.cpp | 21 +- .../move_generators/static_move_generator.h | 14 +- .../uniform_move_generator.cpp | 9 +- .../move_generators/uniform_move_generator.h | 10 +- .../weighted_centroid_move_generator.cpp | 5 +- .../weighted_centroid_move_generator.h | 9 +- .../weighted_median_move_generator.cpp | 69 +- .../weighted_median_move_generator.h | 18 +- vpr/src/place/move_transactions.cpp | 4 +- vpr/src/place/move_transactions.h | 13 +- vpr/src/place/move_utils.cpp | 293 +-- vpr/src/place/move_utils.h | 94 +- vpr/src/place/net_cost_handler.cpp | 576 ++--- vpr/src/place/net_cost_handler.h | 330 +-- vpr/src/place/noc_place_utils.cpp | 58 +- vpr/src/place/noc_place_utils.h | 14 +- vpr/src/place/place.cpp | 124 +- vpr/src/place/place.h | 3 + vpr/src/place/place_checkpoint.cpp | 4 + vpr/src/place/place_constraints.cpp | 8 +- vpr/src/place/place_constraints.h | 4 - vpr/src/place/place_delay_model.cpp | 469 ---- vpr/src/place/place_delay_model.h | 275 --- vpr/src/place/place_macro.cpp | 167 +- vpr/src/place/place_macro.h | 32 +- vpr/src/place/place_util.cpp | 52 +- vpr/src/place/place_util.h | 19 +- vpr/src/place/placement_log_printer.cpp | 28 +- vpr/src/place/placement_log_printer.h | 4 +- vpr/src/place/placer.cpp | 465 ++-- vpr/src/place/placer.h | 16 +- vpr/src/place/placer_breakpoint.cpp | 8 +- vpr/src/place/placer_breakpoint.h | 15 +- vpr/src/place/placer_state.cpp | 30 +- vpr/src/place/placer_state.h | 49 +- vpr/src/place/timing/PlacerCriticalities.cpp | 117 + vpr/src/place/timing/PlacerCriticalities.h | 214 ++ vpr/src/place/timing/PlacerSetupSlacks.cpp | 81 + vpr/src/place/timing/PlacerSetupSlacks.h | 128 + vpr/src/place/timing/PlacerTimingCosts.cpp | 126 + vpr/src/place/timing/PlacerTimingCosts.h | 242 ++ .../{ => timing}/place_timing_update.cpp | 16 +- .../place/{ => timing}/place_timing_update.h | 14 +- vpr/src/place/timing_place.cpp | 270 --- vpr/src/place/timing_place.h | 647 ------ vpr/src/place/timing_place_lookup.cpp | 1319 ----------- vpr/src/place/timing_place_lookup.h | 18 - vpr/src/place/verify_placement.cpp | 13 +- vpr/src/place/verify_placement.h | 4 +- vpr/src/power/power.cpp | 18 +- vpr/src/power/power_components.h | 2 +- vpr/src/route/DecompNetlistRouter.tpp | 14 +- vpr/src/route/NestedNetlistRouter.h | 134 ++ vpr/src/route/NestedNetlistRouter.tpp | 141 ++ vpr/src/route/ParallelNetlistRouter.tpp | 2 +- vpr/src/route/annotate_routing.cpp | 6 +- vpr/src/route/annotate_routing.h | 4 +- vpr/src/route/build_switchblocks.cpp | 47 +- vpr/src/route/build_switchblocks.h | 6 +- vpr/src/route/cb_metrics.cpp | 11 +- vpr/src/route/channel_stats.cpp | 2 +- vpr/src/route/check_route.cpp | 116 +- vpr/src/route/clock_connection_builders.cpp | 6 +- vpr/src/route/clock_network_builders.cpp | 2 +- vpr/src/route/clock_network_builders.h | 3 +- vpr/src/route/connection_router.cpp | 24 +- vpr/src/route/connection_router.h | 2 +- vpr/src/route/connection_router_interface.h | 9 +- vpr/src/route/d_ary_heap.h | 2 +- vpr/src/route/d_ary_heap.tpp | 4 +- vpr/src/route/edge_groups.cpp | 10 +- vpr/src/route/netlist_routers.h | 19 +- vpr/src/route/overuse_report.cpp | 64 +- vpr/src/route/overuse_report.h | 6 +- vpr/src/route/partition_tree.cpp | 22 +- vpr/src/route/partition_tree.h | 8 +- vpr/src/route/route.cpp | 23 +- vpr/src/route/route_budgets.cpp | 6 +- vpr/src/route/route_common.cpp | 20 +- vpr/src/route/route_profiling.cpp | 4 +- vpr/src/route/route_utilization.cpp | 2 +- vpr/src/route/route_utils.cpp | 17 +- vpr/src/route/route_utils.h | 8 +- vpr/src/route/router_delay_profiling.cpp | 20 +- vpr/src/route/router_lookahead_cost_map.cpp | 10 +- .../route/router_lookahead_extended_map.cpp | 12 +- vpr/src/route/router_lookahead_map.cpp | 38 +- vpr/src/route/router_lookahead_map_utils.cpp | 31 +- vpr/src/route/router_lookahead_sampling.cpp | 12 +- vpr/src/route/rr_graph.cpp | 368 ++- vpr/src/route/rr_graph.h | 6 +- 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vpr/src/server/telegramparser.h | 4 +- vpr/src/server/zlibutils.h | 44 +- vpr/src/tileable_rr_graph/chan_node_details.h | 2 +- .../device_grid_annotation.cpp | 8 +- .../openfpga_rr_graph_utils.cpp | 4 +- .../rr_graph_builder_utils.cpp | 34 +- .../rr_graph_builder_utils.h | 4 +- .../tileable_rr_graph/rr_graph_view_util.cpp | 6 +- vpr/src/tileable_rr_graph/rr_gsb.cpp | 81 +- vpr/src/tileable_rr_graph/rr_gsb.h | 1 + .../tileable_chan_details_builder.cpp | 144 +- .../tileable_rr_graph_builder.cpp | 19 +- .../tileable_rr_graph_edge_builder.cpp | 36 +- .../tileable_rr_graph_gsb.cpp | 222 +- .../tileable_rr_graph/tileable_rr_graph_gsb.h | 4 +- .../tileable_rr_graph_node_builder.cpp | 47 +- vpr/src/timing/NetPinTimingInvalidator.h | 4 +- vpr/src/timing/PostClusterDelayCalculator.tpp | 6 +- vpr/src/timing/PreClusterDelayCalculator.h | 2 +- .../timing/PreClusterTimingGraphResolver.cpp | 2 +- vpr/src/timing/PreClusterTimingManager.cpp | 296 +++ vpr/src/timing/PreClusterTimingManager.h | 119 + vpr/src/timing/VprTimingGraphResolver.cpp | 22 +- vpr/src/timing/concrete_timing_info.h | 4 +- vpr/src/timing/read_sdc.cpp | 8 +- vpr/src/timing/slack_evaluation.cpp | 6 +- vpr/src/timing/timing_graph_builder.cpp | 80 +- vpr/src/timing/timing_graph_builder.h | 8 +- vpr/src/timing/timing_util.cpp | 18 +- vpr/src/util/vpr_utils.cpp | 127 +- vpr/src/util/vpr_utils.h | 50 +- vpr/test/test_ap_netlist.cpp | 29 +- vpr/test/test_ap_partial_placement.cpp | 15 +- vpr/test/test_ap_primitive_vector.cpp | 56 +- vpr/test/test_bfs_routing.cpp | 2 +- vpr/test/test_clustered_netlist.cpp | 2 +- vpr/test/test_compressed_grid.cpp | 16 +- vpr/test/test_connection_router.cpp | 17 +- vpr/test/test_edge_groups.cpp | 10 +- vpr/test/test_flat_placement_types.cpp | 49 + vpr/test/test_interchange_device.cpp | 2 +- vpr/test/test_interchange_netlist.cpp | 2 +- vpr/test/test_noc_place_utils.cpp | 2 +- vpr/test/test_noc_storage.cpp | 2 +- vpr/test/test_noc_traffic_flows.cpp | 2 +- vpr/test/test_odd_even_routing.cpp | 5 +- vpr/test/test_post_verilog.cpp | 2 +- vpr/test/test_read_rr_edge_override.txt | 9 + .../test_read_xml_noc_traffic_flows_file.cpp | 2 +- vpr/test/test_server_convertutils.cpp | 4 +- vpr/test/test_server_taskresolver.cpp | 6 +- vpr/test/test_server_telegrambuffer.cpp | 16 +- vpr/test/test_server_telegramoptions.cpp | 2 +- vpr/test/test_server_telegramparser.cpp | 15 +- vpr/test/test_server_zlibutils.cpp | 8 +- vpr/test/test_setup_noc.cpp | 2 +- vpr/test/test_vpr.cpp | 163 +- vpr/test/test_vpr_constraints.cpp | 29 +- vpr/test/test_xy_routing.cpp | 2 +- vpr/valgrind.supp | 800 +++++++ ...cN10LB_mem20K_complexDSP_customSB_22nm.xml | 43 + .../3d_SB_inter_die_stratixiv_arch.timing.xml | 13 +- vtr_flow/arch/titan/stratixiv_arch.timing.xml | 338 +++ .../benchmarks/system_verilog/f4pga/README.md | 12 +- .../flattened_button_controller.sv | 241 ++ .../system_verilog/f4pga/make_sv_flattened.py | 71 + .../flattened_pulse_width_led.sv | 52 + .../f4pga/timer/flattened_timer.sv | 230 ++ vtr_flow/misc/yosys/synthesis.tcl | 37 +- .../parse/parse_config/common/vpr.place.txt | 1 + .../parse/parse_config/timing/vpr.place.txt | 1 + .../qor_config/qor_ap_fixed_chan_width.txt | 21 +- vtr_flow/scripts/arch_gen/arch_gen.py | 4 +- .../scripts/benchtracker/flask_cors/six.py | 3 +- vtr_flow/scripts/benchtracker/populate_db.py | 2 + vtr_flow/scripts/blif_splicer.py | 8 +- vtr_flow/scripts/download_noc_mlp.py | 8 +- vtr_flow/scripts/download_titan.py | 5 +- vtr_flow/scripts/python_libs/vtr/__init__.py | 5 +- .../scripts/python_libs/vtr/abc/__init__.py | 1 + vtr_flow/scripts/python_libs/vtr/abc/abc.py | 38 +- .../scripts/python_libs/vtr/ace/__init__.py | 1 + vtr_flow/scripts/python_libs/vtr/ace/ace.py | 2 + vtr_flow/scripts/python_libs/vtr/flow.py | 14 +- vtr_flow/scripts/python_libs/vtr/log_parse.py | 3 +- .../scripts/python_libs/vtr/odin/__init__.py | 1 + vtr_flow/scripts/python_libs/vtr/odin/odin.py | 1 + .../python_libs/vtr/parmys/__init__.py | 1 + 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AllowShortLoopsOnASingleLine: false AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None -AlwaysBreakBeforeMultilineStrings: true +AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: true BinPackArguments: true BinPackParameters: false @@ -34,7 +34,7 @@ BraceWrapping: SplitEmptyFunction: false SplitEmptyRecord: true SplitEmptyNamespace: true -BreakBeforeBinaryOperators: All +BreakBeforeBinaryOperators: NonAssignment BreakBeforeBraces: Custom BreakBeforeInheritanceComma: false BreakBeforeTernaryOperators: true @@ -68,10 +68,11 @@ IncludeIsMainRegex: '([-_](test|unittest))?$' IndentCaseLabels: true IndentWidth: 4 IndentWrappedFunctionNames: false -IndentPPDirectives: AfterHash +IndentPPDirectives: None +InsertNewlineAtEOF: true JavaScriptQuotes: Leave JavaScriptWrapImports: true -KeepEmptyLinesAtTheStartOfBlocks: false +KeepEmptyLinesAtTheStartOfBlocks: true MacroBlockBegin: '' MacroBlockEnd: '' MaxEmptyLinesToKeep: 1 diff --git a/.github/scripts/install_dependencies.sh b/.github/scripts/install_dependencies.sh index b5f5388f685..61ad671d30b 100755 --- a/.github/scripts/install_dependencies.sh +++ b/.github/scripts/install_dependencies.sh @@ -55,7 +55,7 @@ sudo apt install -y \ clang-16 \ clang-17 \ clang-18 \ - clang-format-14 \ + clang-format-18 \ libtbb-dev \ openssl diff --git a/.github/workflows/nightly_test.yml b/.github/workflows/nightly_test.yml index a57c502e0d3..a6782293b5d 100644 --- a/.github/workflows/nightly_test.yml +++ b/.github/workflows/nightly_test.yml @@ -22,8 +22,6 @@ on: # - '**.md' # - '**.rst' workflow_dispatch: - schedule: - - cron: '0 0 * * *' # daily # We want to cancel previous runs for a given PR or branch / ref if another CI # run is requested. @@ -65,9 +63,9 @@ jobs: - {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"} - {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"} - {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"} - # - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42) + - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""} - {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""} - - {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=OFF", extra_pkgs: ""} + - {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""} env: DEBIAN_FRONTEND: "noninteractive" diff --git a/.github/workflows/nightly_test_manual.yml b/.github/workflows/nightly_test_manual.yml new file mode 100644 index 00000000000..f98f412eb8c --- /dev/null +++ b/.github/workflows/nightly_test_manual.yml @@ -0,0 +1,106 @@ +name: NightlyTestManual + +# This workflow can only be dispatched. +on: + workflow_dispatch: + + # Automatically runs every Sunday 5 AM UTC. + # Results should be ready ~15 hours later (Sunday 8 PM UTC), on time for Monday mornings. + schedule: + - cron: '0 5 * * 0' + +# We want to cancel previous runs for a given PR or branch / ref if another CI +# run is requested. +# See: https://docs.github.com/en/actions/using-jobs/using-concurrency +concurrency: + group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }} + cancel-in-progress: true + +env: + # default compiler for all non-compatibility tests + MATRIX_EVAL: "CC=gcc-13 && CXX=g++-13" + +jobs: + Run-tests: + # Prevents from running on forks where no custom runners are available + if: ${{ github.repository_owner == 'verilog-to-routing' }} + + name: 'Nightly Tests Manual Run' + # This workflow is expected to take around 19 hours. Giving it 24 hours + # before timing out. + timeout-minutes: 1440 + runs-on: [self-hosted, Linux, X64, SAVI] + + steps: + # Clean previous runs of this workflow. + - name: 'Cleanup build folder' + run: | + rm -rf ./* || true + rm -rf ./.??* || true + + # Checkout the VTR repo. + - uses: actions/checkout@v4 + with: + submodules: 'true' + + # Get the extra benchmarks + - name: 'Get Extra Benchmarks' + run: | + make get_titan_benchmarks + make get_ispd_benchmarks + ./dev/upgrade_vtr_archs.sh + make get_symbiflow_benchmarks + + # Build VTR using the default build options. + - name: 'Build VTR' + run: | + make -j12 + make env + source .venv/bin/activate + pip install -r requirements.txt + + # Run all of the nightly tests. + # TODO: We could expose more parallelism if we had one task list which ran + # all of these. + - name: 'Run Nightly Test 1' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test1 + + - name: 'Run Nightly Test 2' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test2 + + - name: 'Run Nightly Test 3' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test3 + + + - name: 'Run Nightly Test 4' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test4 + + - name: 'Run Nightly Test 5' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test5 + + - name: 'Run Nightly Test 6' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test6 + + - name: 'Run Nightly Test 7' + if: success() || failure() + run: | + source .venv/bin/activate + ./run_reg_test.py -j12 vtr_reg_nightly_test7 diff --git a/.github/workflows/stale.yml b/.github/workflows/stale.yml new file mode 100644 index 00000000000..5f6e9fd9088 --- /dev/null +++ b/.github/workflows/stale.yml @@ -0,0 +1,31 @@ +name: 'Close Stale Issues' +on: + schedule: + # Run everyday at 1 PM UTC + - cron: '0 13 * * *' + +jobs: + stale: + runs-on: ubuntu-latest + steps: + - uses: actions/stale@v9 + with: + # The message to be shown for stale issues + stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.' + close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.' + # If you want to exempt an issue from being marked stale/deleted, label it as 'no-stale' + exempt-issue-labels: 'no-stale' + days-before-issue-stale: 365 + days-before-issue-close: 15 + # Start from the oldest issues + ascending: true + + # The configuration below can be used to allow the same behaviour with PRs. + # Since we currently don't want to close old PRs, it is commented out but + # left here in case we change our mind. + + # stale-pr-message: 'This PR has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you are still working on this PR, please add a comment.' + # close-pr-message: 'This PR has been marked stale for 15 days and has been automatically closed.' + # exempt-pr-labels: 'no-stale' + # days-before-pr-stale: 365 + # days-before-pr-close: 15 \ No newline at end of file diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index b6c665ff3ed..5977e1221ba 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -89,6 +89,8 @@ jobs: with: python-version: 3.10.10 - uses: actions/checkout@v4 + with: + submodules: 'true' - name: Install dependencies run: ./.github/scripts/install_dependencies.sh @@ -439,7 +441,6 @@ jobs: - { name: 'GCC 11 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-11 && CXX=g++-11', } - { name: 'GCC 12 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-12 && CXX=g++-12', } - { name: 'GCC 14 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-14 && CXX=g++-14', } - - { name: 'Clang 15 (Ubuntu Noble - 24.04)', eval: 'CC=clang-15 && CXX=clang++-15', } - { name: 'Clang 16 (Ubuntu Noble - 24.04)', eval: 'CC=clang-16 && CXX=clang++-16', } - { name: 'Clang 17 (Ubuntu Noble - 24.04)', eval: 'CC=clang-17 && CXX=clang++-17', } - { name: 'Clang 18 (Ubuntu Noble - 24.04)', eval: 'CC=clang-18 && CXX=clang++-18', } diff --git a/.gitmodules b/.gitmodules index d8738f84253..8a35f2bff8c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,8 @@ [submodule "libs/EXTERNAL/libcatch2"] path = libs/EXTERNAL/libcatch2 url = https://github.com/catchorg/Catch2.git + +# fork where in branch v1.0.0_no_complication_warnings there are compilation warnings fixes for upstream tag v1.0.0 of sockpp [submodule "libs/EXTERNAL/sockpp"] path = libs/EXTERNAL/sockpp - url = https://github.com/w0lek/sockpp.git # fork where in branch v1.0.0_no_complication_warnings there are compilation warnings fixes for upstream tag v1.0.0 of sockpp + url = https://github.com/w0lek/sockpp.git diff --git a/.gitpod.Dockerfile b/.gitpod.Dockerfile index b738f995a69..bb6524f7f53 100644 --- a/.gitpod.Dockerfile +++ b/.gitpod.Dockerfile @@ -30,6 +30,7 @@ RUN apt-get update \ python-lxml \ qt5-default \ wget \ + default-jre \ && apt-get clean \ && rm -rf /var/lib/apt/lists/* diff --git a/CHANGELOG.md b/CHANGELOG.md index ba313c7720d..d86dda1c83d 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -47,6 +47,64 @@ _The following are changes which have been implemented in the VTR master branch ### Removed + +## v9.0.0 - 2024-12-23 + +### Added + * Support for Advanced Architectures: + * 3D FPGA and RAD architectures. + * Architectures with hard Networks-on-Chip (NoCs). + * Distinct horizontal and vertical channel widths and types. + * Diagonal routing wires and other complex wire shapes (L-shaped, T-shaped, ....). + + * New Benchmark Suites: + * Koios: A deep-learning-focused benchmark suite with various design sizes. + * Hermes: Benchmarks utilizing hard NoCs. + * TitanNew: Large benchmarks targeting the Stratix 10 architecture. + + * Commercial FPGAs Architecture Captures: + * Intel’s Stratix 10 FPGA architecture. + * AMD’s 7-series FPGA architecture. + + * Parmys Logic Synthesis Flow: + * Better Verilog language coverage + * More efficient hard block mapping + + * VPR Graphics Visualizations: + * New interface for improved usability and underlying graphics rewritten using EZGL/GTK to allow more UI widgets. + * Algorithm breakpoint visualizations for placement and routing algorithm debugging. + * User-guided (manual) placement optimization features. + * Enabled a live connection for client graphical application to VTR engines through sockets (server mode). + * Interactive timing path analysis (IPA) client using server mode. + + * Performance Enhancements: + * Parallel router for faster inter-cluster routing or flat routing. + + * Re-clustering API to modify packing decisions during the flow. + * Support for floorplanning and placement constraints. + * Unified intra- and inter-cluster (flat) routing. + * Comprehensive web-based VTR utilities and API documentation. + +### Changed + * The default values of many command line options (e.g. inner_num is 0.5 instead of 1.0) + * Changes to placement engine + * Smart centroid initial placement algorithm. + * Multiple smart placement directed moves. + * Reinforcement learning-based placement algorithm. + * Changes to routing engine + * Faster lookahead creation. + * More accurate lookahead for large blocks. + * More efficient heap and pruning strategies. + * max `pres_fac` capped to avoid possible numeric issues. + + +### Fixed + * Many algorithmic and coding bugs are fixed in this release + +### Removed + * Breadth-first (non-timing-driven) router. + * Non-linear congestion placement cost. + ## v8.0.0 - 2020-03-24 ### Added diff --git a/CMakeLists.txt b/CMakeLists.txt index 3ef16e0bcfc..653c3f17173 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -61,10 +61,10 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF) # Allow the user to enable building Yosys option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON) -option(YOSYS_F4PGA_PLUGINS "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF) +option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF) -set(VTR_VERSION_MAJOR 8) -set(VTR_VERSION_MINOR 1) +set(VTR_VERSION_MAJOR 9) +set(VTR_VERSION_MINOR 0) set(VTR_VERSION_PATCH 0) set(VTR_VERSION_PRERELEASE "dev") @@ -94,9 +94,9 @@ add_definitions("-DVTR_ASSERT_LEVEL=${VTR_ASSERT_LEVEL}") include(CheckCXXCompilerFlag) # -# We require c++17 support +# We require c++20 support # -set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) set(CMAKE_CXX_EXTENSIONS OFF) #No compiler specific extensions @@ -161,7 +161,7 @@ else() "-Wcast-align" #Warn if a cast causes memory alignment changes "-Wshadow" #Warn if local variable shadows another variable "-Wformat=2" #Sanity checks for printf-like formatting - "-Wno-format-nonliteral" # But don't worry about non-literal formtting (i.e. run-time printf format strings) + "-Wno-format-nonliteral" # But don't worry about non-literal formatting (i.e. run-time printf format strings) "-Wlogical-op" #Checks for logical op when bit-wise expected "-Wmissing-declarations" #Warn if a global function is defined with no declaration "-Wmissing-include-dirs" #Warn if a user include directory is missing @@ -179,10 +179,10 @@ else() "-Wduplicated-cond" #Warn about identical conditions in if-else chains "-Wduplicated-branches" #Warn when different branches of an if-else chain are equivalent "-Wnull-dereference" #Warn about null pointer dereference execution paths - "-Wuninitialized" #Warn about unitialized values + "-Wuninitialized" #Warn about uninitialized values "-Winit-self" #Warn about self-initialization "-Wcatch-value=3" #Warn when catch statements don't catch by reference - "-Wextra-semi" #Warn about redudnant semicolons + "-Wextra-semi" #Warn about redundant semicolons "-Wimplicit-fallthrough=3" #Warn about case fallthroughs, but allow 'fallthrough' comments to suppress warnings #GCC-like optional #"-Wsuggest-final-types" #Suggest where 'final' would help if specified on a type methods @@ -454,7 +454,7 @@ if(${WITH_ODIN}) endif() # handle cmake params to compile Yosys SystemVerilog/UHDM plugins -if(${YOSYS_F4PGA_PLUGINS}) +if(${SYNLIG_SYSTEMVERILOG}) # avoid compiling plugins in case the Parmys frontend is not active if(NOT ${WITH_PARMYS}) message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.") diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index f5030302bf9..2ebfababd8d 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -77,7 +77,7 @@ This information helps us to quickly reproduce (and hopefully fix) the issue: Tell us what version of VTR you are using (e.g. the output of `vpr --version`), which Operating System and compiler you are using, or any other relevant information about where or how you are building/running VTR. -Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker. +Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker. Issues that do not have any activity for a year will be automatically marked as stale and will be closed after 15 days of being marked as stale. If you know how to fix the issue, or already have it coded-up, please also consider [submitting the fix](#submitting-code-to-vtr). This is likely the fastest way to get bugs fixed! diff --git a/Dockerfile b/Dockerfile index 71f5129301a..2b36ac5c5e5 100644 --- a/Dockerfile +++ b/Dockerfile @@ -15,6 +15,7 @@ RUN apt-get update -qq \ && apt-get -y install --no-install-recommends \ wget \ ninja-build \ + default-jre \ libeigen3-dev \ libtbb-dev \ python3-pip \ diff --git a/Makefile b/Makefile index 06d2df4c158..109288f0344 100644 --- a/Makefile +++ b/Makefile @@ -48,14 +48,14 @@ ifeq ($(VERBOSE),1) override CMAKE_PARAMS := -DVTR_ENABLE_VERBOSE=on ${CMAKE_PARAMS} endif -# -s : Suppresss makefile output (e.g. entering/leaving directories) +# -s : Suppresses makefile output (e.g. entering/leaving directories) # --output-sync target : For parallel compilation ensure output for each target is synchronized (make version >= 4.0) MAKEFLAGS := -s SOURCE_DIR := $(PWD) BUILD_DIR ?= build -#Check for the cmake exectuable +#Check for the cmake executable CMAKE := $(shell command -v cmake 2> /dev/null) #Show test log on failures with 'make test' diff --git a/README.developers.md b/README.developers.md index 709a256c58c..866f8ca1dac 100644 --- a/README.developers.md +++ b/README.developers.md @@ -301,10 +301,13 @@ For the very large runs, you can submit your runs on a large cluster. A template a Slurm-managed cluster can be found under vtr_flow/tasks/slurm/ ## Continuous integration (CI) + +### Automatic (Github runner) CI tests + For the following tests, you can use remote servers instead of running them locally. Once the changes are pushed into the remote repository, or a PR is created, the [Test Workflow](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/.github/workflows/test.yml) will be triggered. Many tests are included in the workflow, including: -* [vtr_reg_nightly_test1-N](#vtr_reg_nightly_test1-N) +* [vtr_reg_nightly_test1-N](#vtr_reg_nightly_test1-n) * [vtr_reg_strong](#vtr_reg_strong) * [vtr_reg_basic](#vtr_reg_basic) * odin_reg_strong @@ -312,6 +315,15 @@ will be triggered. Many tests are included in the workflow, including: instructions on how to gather QoR results of CI runs can be found [here](#example-extracting-qor-data-from-ci-runs). +### Manual Nightly Tests + +You can use remote servers to run the [vtr_reg_nightly_test1-7](#vtr_reg_nightly_test1-n) tests. These tests are triggered manually by going to the GitHub Actions menu, selecting the NightlyTestManual workflow and selecting run workflow on the branch you want to test. Once you do that, the [Nightly Test Manual Workflow](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/.github/workflows/nightly_test_manual.yml) will be triggered. This run will take approximately 15 hours to complete and will cancel all other workflow runs for the same branch. + +Select GitHub Actions menu +
+Select the NightlyTestManual workflow +Run the Workflow + #### Re-run CI Tests In the case that you want to re-run the CI tests, due to certain issues such as infrastructure failure, go to the "Action" tab and find your workflow under Test Workflow. @@ -637,6 +649,10 @@ They can be used for FPGA architecture exploration for DL and also for tuning CA A typical approach to evaluating an algorithm change would be to run `koios_medium` (or `koios_medium_no_hb`) tasks from the nightly regression test (vtr_reg_nightly_test4), the `koios_large` (or `koios_large_no_hb`) and the `koios_proxy` (or `koios_proxy_no_hb`) tasks from the weekly regression test (vtr_reg_weekly). The nightly test contains smaller benchmarks, whereas the large designs are in the weekly regression test. To measure QoR for the entire benchmark suite, both nightly and weekly tests should be run and the results should be concatenated. +As 3 of the `koios_large` circuits require special settings due to having long DSP chains, they are split in separate tasks as follows: + * `bwave_like.float.large.v` and `bwave_like.fixed.large.v` are in `vtr_reg_weekly/koios_bwave_large` task + * `dla_like.large.v` is in `vtr_reg_weekly/koios_dla_large` task + For evaluating an algorithm change in the Odin frontend, run `koios_medium` (or `koios_medium_no_hb`) tasks from the nightly regression test (vtr_reg_nightly_test4_odin) and the `koios_large_odin` (or `koios_large_no_hb_odin`) tasks from the weekly regression test (vtr_reg_weekly). The `koios_medium`, `koios_large`, and `koios_proxy` regression tasks run these benchmarks with complex_dsp functionality enabled, whereas `koios_medium_no_hb`, `koios_large_no_hb` and `koios_proxy_no_hb` regression tasks run these benchmarks without complex_dsp functionality. Normally, only the `koios_medium`, `koios_large`, and `koios_proxy` tasks should be enough for QoR. @@ -651,6 +667,8 @@ The following table provides details on available Koios settings in VTR flow: | Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_nightly_test4_odin/koios_medium | Odin | | | Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_nightly_test4_odin/koios_medium_no_hb | Odin | | | Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_large | Parmys | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_dla_large | Parmys | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_bwave_large | Parmys | | | Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_large_no_hb | Parmys | | | Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_large_odin | Odin | | | Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_large_no_hb_odin | Odin | | @@ -661,7 +679,15 @@ The following table provides details on available Koios settings in VTR flow: For more information refer to the [Koios benchmark home page](vtr_flow/benchmarks/verilog/koios/README.md). -The following steps show a sequence of commands to run the `koios` tasks on the Koios benchmarks: +To make running all the koios benchmarks easier, especially with thos circuits scattered between different tasks, there is an overall task list that runs all the 40 circuits of Koios as follows (this will run all the circuits with complex DSP functionality enabled. If you want to disable the complex DSP, edit the file to point to the `koios_*_no_hb` tasks): + +```shell +$ ../scripts/run_vtr_task.py -l koios_task_list.txt + +#Several hours later... they complete +# + +If you want to run a subset of the koios benchmarks or run them without hard DSP blocks, you can run lower-level 'koios' tasks as follows: ```shell #From the VTR root @@ -681,17 +707,6 @@ $ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv_no_hb & #Several hours later... they complete -#Parse the results -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly_test4/koios_medium -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_large -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_proxy -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv - -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_large_no_hb -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_proxy_no_hb -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv_no_hb - #The run directory should now contain a summary parse_results.txt file $ head -5 vtr_reg_nightly_test4/koios_medium//parse_results.txt arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time diff --git a/cmake/modules/AutoClangFormat.cmake b/cmake/modules/AutoClangFormat.cmake index e4f6c3cb8a4..fb5e78d9f55 100644 --- a/cmake/modules/AutoClangFormat.cmake +++ b/cmake/modules/AutoClangFormat.cmake @@ -21,11 +21,11 @@ add_custom_target(format-cpp-files COMMAND find ${DIRS_TO_FORMAT_CPP} ${FIND_TO_FORMAT_CPP}) # -# Use clang-format-14 for code format +# Use clang-format for code format # add_custom_target(format-cpp COMMAND find ${DIRS_TO_FORMAT_CPP} ${FIND_TO_FORMAT_CPP} | - xargs -P ${CPU_COUNT} clang-format-14 -style=file -i) + xargs -P ${CPU_COUNT} clang-format-18 -style=file -i) # # Use simple python script for fixing C like boxed comments diff --git a/dev/pylint_check.py b/dev/pylint_check.py index 96e78a2393d..4d2b9bba7c6 100755 --- a/dev/pylint_check.py +++ b/dev/pylint_check.py @@ -132,7 +132,7 @@ def expand_paths(): """Build a list of all python files to process by going through 'paths_to_lint'""" paths = [] - for (path, is_recursive) in paths_to_lint: + for path, is_recursive in paths_to_lint: # Make sure all hard-coded paths point to .py files if path.is_file(): if path.suffix.lower() != ".py": diff --git a/dev/submit_slurm.py b/dev/submit_slurm.py index fe6ef4b9ab5..f372f787e45 100755 --- a/dev/submit_slurm.py +++ b/dev/submit_slurm.py @@ -188,7 +188,7 @@ def get_resource_estimates(filepath): mem_bytes = float(match.groupdict()["mem_bytes"]) time_minutes = time_sec / 60 - mem_mb = mem_bytes / (1024 ** 2) + mem_mb = mem_bytes / (1024**2) return time_minutes, mem_mb diff --git a/dev/vtr_gdb_pretty_printers.py b/dev/vtr_gdb_pretty_printers.py index 86e2e14074d..3f4b7a951b3 100644 --- a/dev/vtr_gdb_pretty_printers.py +++ b/dev/vtr_gdb_pretty_printers.py @@ -7,8 +7,10 @@ https://docs.verilogtorouting.org/en/latest/dev/developing#vtr-pretty-printers """ + import re + # VTR related class VtrStrongIdPrinter: def __init__(self, val, typename="vtr::StrongId"): diff --git a/doc/_doxygen/vpr.dox b/doc/_doxygen/vpr.dox index 5d2933b5295..79e58955469 100644 --- a/doc/_doxygen/vpr.dox +++ b/doc/_doxygen/vpr.dox @@ -6,7 +6,7 @@ EXTRACT_ALL = YES EXTRACT_PRIVATE = YES EXTRACT_STATIC = YES WARN_IF_UNDOCUMENTED = NO -INPUT = ../../vpr +INPUT = ../../vpr ../../libs/libarchfpga/ RECURSIVE = YES GENERATE_HTML = NO GENERATE_LATEX = NO diff --git a/doc/src/api/vpr/mapping.rst b/doc/src/api/vpr/mapping.rst index ef573d0e973..f46436e1897 100644 --- a/doc/src/api/vpr/mapping.rst +++ b/doc/src/api/vpr/mapping.rst @@ -1,7 +1,7 @@ =============== Netlist mapping =============== -As shown in the previous section, there are multiple levels of abstraction (multiple netlists) in VPR which are the ClusteredNetlist and the AtomNetlist. To fully use these netlists, we provide some functions to map between them. +As shown in the previous section, there are multiple levels of abstraction (multiple netlists) in VPR which are the ClusteredNetlist and the AtomNetlist. To fully use these netlists, we provide some functions to map between them. In this section, we will state how to map between the atom and clustered netlists. @@ -16,11 +16,11 @@ To get the block Id of a cluster in the ClusteredNetlist from the block Id of on .. code-block:: cpp - ClusterBlockId clb_index = g_vpr_ctx.atom().lookup.atom_clb(atom_blk_id); + ClusterBlockId clb_index = g_vpr_ctx.atom().lookup().atom_clb(atom_blk_id); * Using re_cluster_util.h helper functions - + .. code-block:: cpp ClusterBlockId clb_index = atom_to_cluster(atom_blk_id); @@ -53,7 +53,7 @@ To get the net Id in the ClusteredNetlist from its Id in the AtomNetlist, use At .. code-block:: cpp - ClusterNetId clb_net = g_vpr_ctx.atom().lookup.clb_net(atom_net); + ClusterNetId clb_net = g_vpr_ctx.atom().lookup().clb_net(atom_net); Cluster net Id to Atom net Id @@ -62,4 +62,4 @@ To get the net Id in the AtomNetlist from its Id in the ClusteredNetlist, use At .. code-block:: cpp - ClusterNetId atom_net = g_vpr_ctx.atom().lookup.atom_net(clb_net); + ClusterNetId atom_net = g_vpr_ctx.atom().lookup().atom_net(clb_net); diff --git a/doc/src/api/vtrutil/index.rst b/doc/src/api/vtrutil/index.rst index 6d44b381a2a..84dc4ede829 100644 --- a/doc/src/api/vtrutil/index.rst +++ b/doc/src/api/vtrutil/index.rst @@ -11,4 +11,5 @@ VTRUTIL API container_utils logging geometry + parallel other diff --git a/doc/src/api/vtrutil/parallel.rst b/doc/src/api/vtrutil/parallel.rst new file mode 100644 index 00000000000..a8f9b9bbfa0 --- /dev/null +++ b/doc/src/api/vtrutil/parallel.rst @@ -0,0 +1,13 @@ +===== +Parallel +===== + +vtr_thread_pool +------------- +.. doxygenfile:: vtr_thread_pool.h + :project: vtr + :sections: briefdescription detaileddescription func innernamespace enum + +.. doxygenclass:: vtr::thread_pool + :project: vtr + :members: diff --git a/doc/src/arch/reference.rst b/doc/src/arch/reference.rst index b8fccc6579a..681a6607818 100644 --- a/doc/src/arch/reference.rst +++ b/doc/src/arch/reference.rst @@ -849,7 +849,7 @@ Each tile type is specified with the ```` tag withing the ```` tag. Tile ~~~~ -.. arch:tag:: +.. arch:tag:: A tile refers to a placeable element within an FPGA architecture and describes its physical compositions on the grid. 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external plugins to the Parmys front-end. + Compiling the VTR flow with the ``-DSynlig_SystemVerilog=ON`` flag is required to build and install Synlig SystemVerilog and UHDM plugins. + Using this compile flag, the `Synlig_SystemVerilog `_ repository is cloned and installed in the ``$VTR_ROOT/build/bin`` directory and then will be compiled and added as external tool to the Parmys front-end. Basic Usage ----------- diff --git a/doc/src/quickstart/index.rst b/doc/src/quickstart/index.rst index 0621ae0cd81..242079bef99 100644 --- a/doc/src/quickstart/index.rst +++ b/doc/src/quickstart/index.rst @@ -24,12 +24,18 @@ If you cloned the repository, you will need to set up the git submodules (if you > git submodule init > git submodule update -VTR requires several system packages and Python packages to build and run the flow. You can install the required system packages using the following command (this works on Ubuntu 18.04, 20.04 and 22.04, but you may require different packages on other Linux distributions). Our CI testing is on Ubuntu 22.04, so that is the best tested platform and recommended for development. +VTR requires several system packages and Python packages to build and run the flow. Ubuntu users can install the required system packages using the following command (this works on Ubuntu 18.04, 20.04, 22.04 and 24.04, but you may require different packages on other Linux distributions). Our CI testing is on Ubuntu 24.04, so that is the best tested platform and recommended for development. .. code-block:: bash > ./install_apt_packages.sh +Fedora and RHEL users may use the following command to install the required system packages. + +.. code-block:: bash + + > ./install_dnf_packages.sh + Then, to install the required Python packages (optionally within a new Python virtual environment): .. code-block:: bash diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index c33d4352fef..f21ee85f1eb 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -89,6 +89,8 @@ VPR runs all stages of (pack, place, route, and analysis) if none of :option:`-- as such, the :option:`--pack` and :option:`--place` options should not be set when this option is set. This flow requires that the device has a fixed size and some of the primitive blocks are fixed somewhere on the device grid. + .. seealso:: See :ref:`analytical_placement_options` for the options for this flow. + .. seealso:: See :ref:`Fixed FPGA Grid Layout ` and :option:`--device` for how to fix the device size. .. seealso:: See :ref:`VPR Placement Constraints ` for how to fix primitive blocks in a design to the device grid. @@ -377,7 +379,15 @@ Use the options below to override this default naming behaviour. .. seealso:: :ref:`Routing Resource XML File `. -.. option:: --read_vpr_constraints ::...: +.. option:: --read_rr_edge_override + + Reads a file that overrides the intrinsic delay of specific edges in RR graph. + + This option should be used with both :option:`--read_rr_graph` and :option:`--write_rr_graph`. When used this way, + VPR reads the RR graph, updates the delays of selected edges using :option:`--read_rr_edge_override`, + and writes the updated RR graph. The modified RR graph can then be used in later VPR runs. + +.. option:: --read_vpr_constraints Reads the :ref:`VPR constraints ` that the flow must respect from the specified XML file. @@ -408,6 +418,50 @@ Use the options below to override this default naming behaviour. Prefix for output files +.. option:: --read_flat_place + + Reads a file containing the locations of each atom on the FPGA. + This is used by the packer to better cluster atoms together. + + The flat placement file (which often ends in ``.fplace``) is a text file + where each line describes the location of an atom. Each line in the flat + placement file should have the following syntax: + + .. code-block:: none + + + + For example: + + .. code-block:: none + + n523 6 8 0 0 3 + n522 6 8 0 0 5 + n520 6 8 0 0 2 + n518 6 8 0 0 16 + + The position of the atom on the FPGA is given by 3 floating point values + (``x``, ``y``, ``layer``). We allow for the positions of atom to be not + quite legal (ok to be off-grid) since this flat placement will be fed into + the packer and placer, which will snap the positions to grid locations. By + allowing for off-grid positions, the packer can better trade-off where to + move atom blocks if they cannot be placed at the given position. + For 2D FPGA architectures, the ``layer`` should be 0. + + The ``sub_tile`` is a clustered placement construct: which cluster-level + location at a given (x, y, layer) should these atoms go at (relevant when + multiple clusters can be stacked there). A sub-tile of -1 may be used when + the sub-tile of an atom is unkown (allowing the packing algorithm to choose + any sub-tile at the given (x, y, layer) location). + + The ``site_idx`` is an optional index into a linearized list of primitive + locations within a cluster-level block which may be used as a hint to + reconstruct clusters. + + .. warning:: + + This interface is currently experimental and under active development. + .. option:: --write_flat_place Writes the post-placement locations of each atom into a flat placement file. @@ -611,7 +665,7 @@ For people not working on CAD, you can probably leave all the options to their d .. note:: - If a pin utilization target is unspecified it defaults to 1.0 (i.e. 100% utilization). + If some pin utilizations are specified, ``auto`` mode is turned off and the utilization target for any unspecified pin types defaults to 1.0 (i.e. 100% utilization). For example: @@ -830,55 +884,9 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe **Default:** ``0.0`` -.. _dusty_sa_options: -Setting any of the following 5 options selects :ref:`Dusty's annealing schedule ` . - -.. option:: --alpha_min - - The minimum (starting) update factor (alpha) used. - Ranges between 0 and alpha_max. - - **Default:** ``0.2`` - -.. option:: --alpha_max - - The maximum (stopping) update factor (alpha) used after which simulated annealing will complete. - Ranges between alpha_min and 1. - - **Default:** ``0.9`` - -.. option:: --alpha_decay - - The rate at which alpha will approach 1: alpha(n) = 1 - (1 - alpha(n-1)) * alpha_decay - Ranges between 0 and 1. - - **Default:** ``0.7`` - -.. option:: --anneal_success_min - - The minimum success ratio after which the temperature will reset to maintain the target success ratio. - Ranges between 0 and anneal_success_target. - - **Default:** ``0.1`` - -.. option:: --anneal_success_target - - The temperature after each reset is selected to keep this target success ratio. - Ranges between anneal_success_target and 1. - - **Default:** ``0.25`` - -.. option:: --place_cost_exp - - Wiring cost is divided by the average channel width over a net's bounding box - taken to this exponent. Only impacts devices with different channel widths in - different directions or regions. - - **Default:** ``1`` - .. option:: --RL_agent_placement {on | off} - Uses a Reinforcement Learning (RL) agent in choosing the appropiate move type in placement. + Uses a Reinforcement Learning (RL) agent in choosing the appropriate move type in placement. It activates the RL agent placement instead of using a fixed probability for each move type. **Default:** ``on`` @@ -907,7 +915,7 @@ Setting any of the following 5 options selects :ref:`Dusty's annealing schedule Controls how quickly the agent's memory decays. Values between [0., 1.] specify the fraction of weight in the exponentially weighted reward average applied to moves - which occured greater than moves_per_temp moves ago. Values < 0 cause the + which occurred greater than moves_per_temp moves ago. Values < 0 cause the unweighted reward sample average to be used (all samples are weighted equally) **Default:** ``0.05`` @@ -926,6 +934,15 @@ Setting any of the following 5 options selects :ref:`Dusty's annealing schedule **Default:** ``move_block_type`` +.. option:: --place_quench_only {on | off} + + If this option is set to ``on``, the placement will skip the annealing phase and only perform the placement quench. + This option is useful when the the quality of initial placement is good enough and there is no need to perform the + annealing phase. + + **Default:** ``off`` + + .. option:: --placer_debug_block .. note:: This option is likely only of interest to developers debugging the placement algorithm @@ -1023,7 +1040,7 @@ The following options are only valid when the placement engine is in timing-driv .. option:: --place_delay_model_reducer {min, max, median, arithmean, geomean} - When calculating delta delays for the placment delay model how are multiple values combined? + When calculating delta delays for the placement delay model how are multiple values combined? **Default:** ``min`` @@ -1056,7 +1073,7 @@ The following options are only valid when the placement engine is in timing-driv .. option:: --place_tsu_abs_margin - Specifies an absolute offest added to cell setup times used by the placer. + Specifies an absolute offset added to cell setup times used by the placer. This effectively controls whether the placer should try to achieve extra margin on setup paths. For example a value of 500e-12 corresponds to requesting an extra 500ps of setup margin. @@ -1064,7 +1081,7 @@ The following options are only valid when the placement engine is in timing-driv .. option:: --post_place_timing_report - Name of the post-placement timing report file to generate (not generated if unspecfied). + Name of the post-placement timing report file to generate (not generated if unspecified). .. _noc_placement_options: @@ -1163,6 +1180,114 @@ The following options are only used when FPGA device and netlist contain a NoC r **Default:** ``vpr_noc_placement_output.txt`` + +.. _analytical_placement_options: + +Analytical Placement Options +^^^^^^^^^^^^^^^ +Instead of Packing atoms into clusters and placing the clusters into valid tile +sites on the FPGA, Analytical Placement uses analytical techniques to place atoms +on the FPGA device by relaxing the constraints on where they can be placed. This +atom-level placement is then legalized into a clustered placement and passed into +the router in VPR. + +Analytical Placement is generally split into three stages: + +* Global Placement: Uses analytical techniques to place atoms on the FPGA grid. + +* Full Legalization: Legalizes a flat (atom) placement into legal clusters placed on the FPGA grid. + +* Detailed Placement: While keeping the clusters legal, performs optimizations on the clustered placement. + +.. warning:: + + Analytical Placement is experimental and under active development. + +.. option:: --ap_analytical_solver {qp-hybrid | lp-b2b} + + Controls which Analytical Solver the Global Placer will use in the AP Flow. + The Analytical Solver solves for a placement which optimizes some objective + function, ignorant of the FPGA legality constraints. This provides a "lower- + bound" solution. The Global Placer will legalize this solution and feed it + back to the analytical solver to make its solution more legal. + + * ``qp-hybrid`` Solves for a placement that minimizes the quadratic HPWL of + the flat placement using a hybrid clique/star net model (as described in + FastPlace :cite:`Viswanathan2005_FastPlace`). + Uses the legalized solution as anchor-points to pull the solution to a + more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`). + + * ``lp-b2b`` Solves for a placement that minimizes the linear HPWL of the + flat placement using the Bound2Bound net model (as described in Kraftwerk2 :cite:`Spindler2008_Kraftwerk2`). + Uses the legalized solution as anchor-points to pull the solution to a + more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`). + + **Default:** ``lp-b2b`` + +.. option:: --ap_partial_legalizer {bipartitioning | flow-based} + + Controls which Partial Legalizer the Global Placer will use in the AP Flow. + The Partial Legalizer legalizes a placement generated by an Analytical Solver. + It is used within the Global Placer to guide the solver to a more legal + solution. + + * ``bipartitioning`` Creates minimum windows around over-dense regions of + the device bi-partitions the atoms in these windows such that the region + is no longer over-dense and the atoms are in tiles that they can be placed + into. + + * ``flow-based`` Flows atoms from regions that are overfilled to regions that + are underfilled. + + **Default:** ``bipartitioning`` + +.. option:: --ap_full_legalizer {naive | appack} + + Controls which Full Legalizer to use in the AP Flow. + + * ``naive`` Use a Naive Full Legalizer which will try to create clusters exactly where their atoms are placed. + + * ``appack`` Use APPack, which takes the Packer in VPR and uses the flat atom placement to create better clusters. + + **Default:** ``appack`` + +.. option:: --ap_detailed_placer {none | annealer} + + Controls which Detailed Placer to use in the AP Flow. + + * ``none`` Do not use any Detailed Placer. + + * ``annealer`` Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer. + + **Default:** ``annealer`` + +.. option:: --ap_timing_tradeoff + + Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow. + + A value of 0.0 makes the AP flow focus completely on wirelength minimization, + while a value of 1.0 makes the AP flow focus completely on timing optimization. + + **Default:** ``0.5`` + +.. option:: --ap_verbosity + + Controls the verbosity of the AP flow output. + Larger values produce more detailed output, which may be useful for + debugging the algorithms in the AP flow. + + * ``1 <= verbosity < 10`` Print standard, stage-level messages. This will + print messages at the GP, FL, or DP level. + + * ``10 <= verbosity < 20`` Print more detailed messages of what is happening + within stages. For example, show high-level information on the legalization + iterations within the Global Placer. + + * ``20 <= verbosity`` Print very detailed messages on intra-stage algorithms. + + **Default:** ``1`` + + .. _router_options: Router Options @@ -1179,7 +1304,7 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout This means that during the routing stage, all nets, both intra- and inter-cluster, are routed directly from one primitive pin to another primitive pin. This increases routing time but can improve routing quality by re-arranging LUT inputs and exposing additional optimization opportunities in architectures with local intra-cluster routing that is not a full crossbar. - **Default:** ``OFF` + **Default:** ``off`` .. option:: --max_router_iterations diff --git a/doc/src/vpr/file_formats.rst b/doc/src/vpr/file_formats.rst index dc76e2ff5ea..32fbb0dfc93 100644 --- a/doc/src/vpr/file_formats.rst +++ b/doc/src/vpr/file_formats.rst @@ -1100,6 +1100,28 @@ To aid in handling large graphs, rr_graph files can also be :ref:`saved in - + @@ -78,7 +78,10 @@ An ```` tag is used to add an atom that must be constrained to the par :req_param name_pattern: The name of the atom. -The ``name_pattern`` can be the exact name of the atom from the input atom netlist that was passed to VPR. It can also be a regular expression, in which case VPR will add all atoms from the netlist which have a portion of their name matching the regular expression to the partition. For example, if a module contains primitives named in the pattern of "alu[0]", "alu[1]", and "alu[2]", the regular expression "alu*" would add all of the primitives from that module. +The ``name_pattern`` can either be the exact name of an atom from the input atom netlist passed to VPR, or a regular expression pattern matching one or more atom names. VPR first searches the netlist for an exact match. If no exact match is found, it then assumes that the given name is a regex pattern and searches for atoms whose names match the pattern. + +For example, to add all atoms ``alu[0]``, ``alu[1]``, and ``alu[2]`` to the partition ``Part0``, the user can use ``alu.*`` as the ``name_pattern`` in the ```` tag. + Region ^^^^^^ @@ -124,12 +127,3 @@ It is strongly recommended that different partitions do not overlap. The packing blocks and the number of physical blocks in a region to decide pack atoms inside a partition more aggressively when there are not enough resources in a partition. Overlapping partitions causes some physical blocks to be counted in more than one partition. - - - - - - - - - diff --git a/doc/src/vtr/run_vtr_flow.rst b/doc/src/vtr/run_vtr_flow.rst index 97782ec7a77..f61bdf3226e 100644 --- a/doc/src/vtr/run_vtr_flow.rst +++ b/doc/src/vtr/run_vtr_flow.rst @@ -73,15 +73,15 @@ The parser for these runs is considered the Yosys conventional Verilog/SystemVer .. code-block:: bash - # Using the Yosys-SystemVerilog plugin if installed, otherwise the Yosys conventional Verilog parser + # Using the Synlig System_Verilog tool if installed, otherwise the Yosys conventional Verilog parser ./run_vtr_flow -parser system-verilog # Using the Surelog plugin if installed, otherwise failure on the unsupported file type ./run_vtr_flow -parser surelog Running the default VTR flow using the Parmys standalone front-end. -The Yosys HDL parser is considered as Yosys-SystemVerilog plugin (i.e., ``read_systemverilog``) and Yosys UHDM plugin (i.e., ``read_uhdm``), respectively. -Utilizing Yosys plugins requires passing the ``-DYOSYS_F4PGA_PLUGINS=ON`` compile flag to build and install the plugins for the Parmys front-end. +The Synlig HDL parser supports the (i.e., ``read_systemverilog``) and (i.e., ``read_uhdm``) commands. It utilizes Surelog for SystemVerilog 2017 processing and Yosys for synthesis. +Enable Synlig tool with the ``-DSYNLIG_SYSTEMVERILOG=ON`` compile flag for the Parmys front-end. .. code-block:: bash diff --git a/doc/src/z_references.bib b/doc/src/z_references.bib index 8822890713d..fc064f2c433 100644 --- a/doc/src/z_references.bib +++ b/doc/src/z_references.bib @@ -436,3 +436,46 @@ @inproceedings{kosar2024parallel booktitle={The 23rd International Conference on Field-Programmable Technology}, year={2024} } + +@ARTICLE{Viswanathan2005_FastPlace, + author={Viswanathan, N. and Chu, C.C.-N.}, + journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + title={{FastPlace}: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model}, + year={2005}, + volume={24}, + number={5}, + month=may, + pages={722-733}, + keywords={Clustering algorithms;Partitioning algorithms;Algorithm design and analysis;Integrated circuit interconnections;Large-scale systems;Minimization;Delay;Simulated annealing;Iterative algorithms;Acceleration;Analytical placement;computer-aided design;net models;standard cell placement}, + doi={10.1109/TCAD.2005.846365} +} + +@article{Kim2013_SimPL, + author = {Kim, Myung-Chul and Lee, Dong-Jin and Markov, Igor L.}, + journal = {Commun. ACM}, + title = {{SimPL}: an algorithm for placing {VLSI} circuits}, + year = {2013}, + issue_date = {June 2013}, + publisher = {Association for Computing Machinery}, + address = {New York, NY, USA}, + volume = {56}, + number = {6}, + issn = {0001-0782}, + doi = {10.1145/2461256.2461279}, + month = jun, + pages = {105–113}, + numpages = {9} +} + +@ARTICLE{Spindler2008_Kraftwerk2, + author={Spindler, Peter and Schlichtmann, Ulf and Johannes, Frank M.}, + journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + title={Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model}, + year={2008}, + volume={27}, + number={8}, + month=aug, + pages={1398-1411}, + keywords={Cost function;Central Processing Unit;Runtime;Quality control;Convergence;Computational efficiency;Integrated circuit synthesis;Stochastic processes;Circuit simulation;Bound2Bound;force-directed;half-perimeter wirelength (HPWL);Kraftwerk2;quadratic placement;Kraftwerk2;force-directed;quadratic placement;Bound2Bound;HPWL}, + doi={10.1109/TCAD.2008.925783} +} diff --git a/install_apt_packages.sh b/install_apt_packages.sh index 17d9aa49425..ede554a197c 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -36,6 +36,7 @@ sudo apt-get install -y \ libboost-system-dev \ libboost-python-dev \ libboost-filesystem-dev \ + default-jre \ zlib1g-dev # Required to build the documentation diff --git a/install_dnf_packages.sh b/install_dnf_packages.sh new file mode 100755 index 00000000000..b2a23fb7da5 --- /dev/null +++ b/install_dnf_packages.sh @@ -0,0 +1,52 @@ +sudo dnf upgrade --refresh + +# Base packages to compile and run basic regression tests +sudo dnf install -y \ + make \ + cmake \ + automake \ + gcc \ + gcc-c++ \ + kernel-devel \ + pkg-config \ + bison \ + flex \ + python3-devel \ + tbb-devel +# Required for graphics +sudo dnf install -y \ + gtk3-devel \ + libX11 + +# Required for parmys front-end from https://github.com/YosysHQ/yosys +sudo dnf install -y \ + make \ + automake \ + gcc \ + gcc-c++ \ + kernel-devel \ + clang \ + bison \ + flex \ + readline-devel \ + gawk \ + tcl-devel \ + libffi-devel \ + git \ + graphviz \ + python-xdot \ + pkg-config \ + python3-devel \ + boost-system \ + boost-python3 \ + boost-filesystem \ + zlib-ng-devel + +# Required to build the documentation +sudo dnf install -y \ + python3-sphinx \ + python-sphinx-doc + +# Required to run the analytical placement flow +sudo dnf install -y \ + eigen3-devel \ No newline at end of file diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index a60c48958eb..f70f150fbe2 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -1,4 +1,5 @@ include(ExternalProject) +include(ProcessorCount) #Manually synchronized external libraries add_subdirectory(libpugixml) @@ -9,8 +10,17 @@ add_subdirectory(libsdcparse) add_subdirectory(libblifparse) add_subdirectory(libtatum) add_subdirectory(libcatch2) +#add_subdirectory(synlig) #add_subdirectory(parmys) +#Proc numbers +ProcessorCount(PROCESSOR_COUNT) + +if(PROCESSOR_COUNT EQUAL 0) + # Fallback to 1 if the processor count cannot be determined + set(PROCESSOR_COUNT 1) +endif() + #VPR_USE_SERVER is initialized in the root CMakeLists #compile sockpp only if server mode is enabled if (VPR_USE_SERVER) @@ -27,8 +37,9 @@ endif () # The VTR root CMakeFile initializes the WITH_PARMYS if (${WITH_PARMYS}) - # building Surelog and UHDM in a custom target to avoid any target conflict with VTR targets - if (${YOSYS_F4PGA_PLUGINS}) + + if (${SYNLIG_SYSTEMVERILOG}) + set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog) set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build) set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins) @@ -62,74 +73,90 @@ if (${WITH_PARMYS}) LOG_OUTPUT_ON_FAILURE ON # dependency - DEPENDS yosys + DEPENDS yosys ) - ExternalProject_Add(f4pga-plugins - # root directory for the Yosys-F4PGA-Plugins project - PREFIX "f4pga-plugins" - - GIT_REPOSITORY https://github.com/chipsalliance/yosys-f4pga-plugins.git - GIT_TAG v1.20230808 - GIT_PROGRESS TRUE - GIT_SHALLOW TRUE - - # setting source, build and install directories - SOURCE_DIR "${YOSYS_F4PGA_PLUGINS_SOURCE_DIR}" - BUILD_IN_SOURCE FALSE - INSTALL_DIR "" - - INSTALL_COMMAND "" - CONFIGURE_COMMAND "" - BUILD_COMMAND ${MAKE_PROGRAM} -C ${YOSYS_F4PGA_PLUGINS_SOURCE_DIR} - PATH=${CMAKE_BINARY_DIR}/bin/:$ENV{PATH} - UHDM_INSTALL_DIR=${CMAKE_BINARY_DIR} - BUILD_DIR=${CMAKE_CURRENT_BINARY_DIR}/f4pga-plugins/$(NAME) # NAME will be resolved by yosys-f4pga-plugins Make - YOSYS_PATH=${CMAKE_BINARY_DIR} - install -j${CUSTOM_BUILD_PARALLEL_LEVEL} - - # redirect logs to a logfile - LOG_BUILD ON - LOG_UPDATE ON - LOG_INSTALL ON - LOG_CONFIGURE OFF - LOG_OUTPUT_ON_FAILURE ON + # Synlig integration (manages Surelog and UHDM internally) + + # Synlig integration (manages Surelog and UHDM internally) + set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig) + + # Clone Synlig repository and ensure submodules are synced before building + ExternalProject_Add(synlig + PREFIX "synlig" + + # Clone the Synlig repository + GIT_REPOSITORY https://github.com/chipsalliance/synlig.git + GIT_TAG main + GIT_PROGRESS TRUE + GIT_SHALLOW TRUE + + # Set source and build directories + SOURCE_DIR "${SYNLIG_SOURCE_DIR}" + BUILD_IN_SOURCE FALSE + INSTALL_DIR " " + + # Sync submodules after cloning + + + UPDATE_COMMAND git submodule update --init --recursive third_party/surelog + WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR} + + BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT} + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + + # Pass necessary paths and set environment variables + CMAKE_CACHE_ARGS + "-DCMAKE_BUILD_TYPE:STRING=Release" + "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog" + "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys" + "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}" + "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build" + "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}" + + LOG_BUILD ON + LOG_UPDATE ON + LOG_INSTALL ON + LOG_CONFIGURE OFF + LOG_OUTPUT_ON_FAILURE ON + + # Ensure dependencies like Yosys are built first + DEPENDS yosys # Ensure submodule sync runs before synlig build + ) - # dependency - DEPENDS surelog yosys - ) endif () - endif () -if (${VTR_ENABLE_CAPNPROTO}) - # Override default policy for capnproto (CMake policy version 3.1) - # Enable new IPO variables - set(CMAKE_POLICY_DEFAULT_CMP0069 NEW) - # Enable option overrides via variables - set(CMAKE_POLICY_DEFAULT_CMP0077 NEW) + if (${VTR_ENABLE_CAPNPROTO}) + # Override default policy for capnproto (CMake policy version 3.1) + # Enable new IPO variables + set(CMAKE_POLICY_DEFAULT_CMP0069 NEW) - # Re-enable CXX extensions for capnproto. - set(CMAKE_CXX_EXTENSIONS ON) + # Enable option overrides via variables + set(CMAKE_POLICY_DEFAULT_CMP0077 NEW) - # Disable capnproto tests - set(BUILD_TESTING OFF) + # Re-enable CXX extensions for capnproto. + set(CMAKE_CXX_EXTENSIONS ON) - #Since capnproto is an externally developed library/tool, we suppress all compiler warnings - CHECK_CXX_COMPILER_FLAG("-w" CXX_COMPILER_SUPPORTS_-w) - if (CXX_COMPILER_SUPPORTS_-w) - add_compile_options("-w") - endif () + # Disable capnproto tests + set(BUILD_TESTING OFF) - add_subdirectory(capnproto EXCLUDE_FROM_ALL) + #Since capnproto is an externally developed library/tool, we suppress all compiler warnings + CHECK_CXX_COMPILER_FLAG("-w" CXX_COMPILER_SUPPORTS_-w) + if (CXX_COMPILER_SUPPORTS_-w) + add_compile_options("-w") + endif () - #Some capnproto kj headers (e.g. filesystem.h) generate warnings, treat them as system headers to suppress warnings - #We suppress them here since we include the capnproto sub-tree as is and do not modify its CMakeLists.txts - target_include_directories(kj SYSTEM INTERFACE - $ - $ - ) + add_subdirectory(capnproto EXCLUDE_FROM_ALL) + + #Some capnproto kj headers (e.g. filesystem.h) generate warnings, treat them as system headers to suppress warnings + #We suppress them here since we include the capnproto sub-tree as is and do not modify its CMakeLists.txts + target_include_directories(kj SYSTEM INTERFACE + $ + $ + ) endif () # Some catch2 headers generate warnings, so treat them as system headers to suppress warnings diff --git a/libs/EXTERNAL/libcatch2 b/libs/EXTERNAL/libcatch2 index fa43b77429b..76f70b1403d 160000 --- a/libs/EXTERNAL/libcatch2 +++ b/libs/EXTERNAL/libcatch2 @@ -1 +1 @@ -Subproject commit fa43b77429ba76c462b1898d6cd2f2d7a9416b14 +Subproject commit 76f70b1403dbc0781216f49e20e45b71f7eccdd8 diff --git a/libs/EXTERNAL/libezgl/include/ezgl/point.hpp b/libs/EXTERNAL/libezgl/include/ezgl/point.hpp index ee8d5d17b90..a0d39279f19 100644 --- a/libs/EXTERNAL/libezgl/include/ezgl/point.hpp +++ b/libs/EXTERNAL/libezgl/include/ezgl/point.hpp @@ -36,7 +36,7 @@ class point2d { /** * Create a point at the given x and y position. */ - point2d(double x_coord, double y_coord) : x(x_coord), y(y_coord) + point2d(double x_coord, double y_coord) noexcept : x(x_coord), y(y_coord) { } diff --git a/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp b/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp index 70138eae392..a454e7f107c 100644 --- a/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp +++ b/libs/EXTERNAL/libezgl/include/ezgl/rectangle.hpp @@ -33,7 +33,7 @@ class rectangle { /** * Default constructor: Create a zero-sized rectangle at {0,0}. */ - rectangle() : m_first({0, 0}), m_second({0, 0}) + rectangle() noexcept : m_first({0, 0}), m_second({0, 0}) { } diff --git a/libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp b/libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp index 71f5b7a874e..28340d53885 100644 --- a/libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp +++ b/libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp @@ -161,7 +161,7 @@ template bool operator!=(const StrongId& lhs, const StrongId& rhs); template -bool operator<(const StrongId& lhs, const StrongId& rhs); +bool operator<(const StrongId& lhs, const StrongId& rhs) noexcept; //Class template definition with default template parameters @@ -198,7 +198,7 @@ class StrongId { // after the function name (i.e. <>) friend bool operator== <>(const StrongId& lhs, const StrongId& rhs); friend bool operator!= <>(const StrongId& lhs, const StrongId& rhs); - friend bool operator< <>(const StrongId& lhs, const StrongId& rhs); + friend bool operator< <>(const StrongId& lhs, const StrongId& rhs) noexcept; private: T id_; }; @@ -215,7 +215,7 @@ bool operator!=(const StrongId& lhs, const StrongId -bool operator<(const StrongId& lhs, const StrongId& rhs) { +bool operator<(const StrongId& lhs, const StrongId& rhs) noexcept { return lhs.id_ < rhs.id_; } diff --git a/libs/EXTERNAL/sockpp b/libs/EXTERNAL/sockpp index 5388c4b5659..599f750c8b6 160000 --- a/libs/EXTERNAL/sockpp +++ b/libs/EXTERNAL/sockpp @@ -1 +1 @@ -Subproject commit 5388c4b5659e99a86bc906dd6ac2eef66f1dd51e +Subproject commit 599f750c8b6532950d4bb43b2b756700e41dbae9 diff --git a/libs/libarchfpga/CMakeLists.txt b/libs/libarchfpga/CMakeLists.txt index 65e9096cd37..283ddb55959 100644 --- a/libs/libarchfpga/CMakeLists.txt +++ b/libs/libarchfpga/CMakeLists.txt @@ -26,6 +26,8 @@ target_link_libraries(libarchfpga if(${VTR_ENABLE_CAPNPROTO}) target_link_libraries(libarchfpga libvtrcapnproto) + find_package(ZLIB REQUIRED) + target_link_libraries(libarchfpga ZLIB::ZLIB) target_compile_definitions(libarchfpga PRIVATE VTR_ENABLE_CAPNPROTO) endif() diff --git a/libs/libarchfpga/src/arch_check.cpp b/libs/libarchfpga/src/arch_check.cpp index c8fb00299c4..5360d6e4c02 100644 --- a/libs/libarchfpga/src/arch_check.cpp +++ b/libs/libarchfpga/src/arch_check.cpp @@ -32,7 +32,7 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line) { bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line) { //Outputs should have no combinational sinks for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) { - if (port->combinational_sink_ports.size() != 0) { + if (!port->combinational_sink_ports.empty()) { archfpga_throw(file, line, "Model '%s' output port '%s' can not have combinational sink ports", model->name, port->name); @@ -114,9 +114,9 @@ void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_ti } for (auto pin_map : pin_direct_map) { - auto block_port = get_port_by_pin(logical_block, pin_map.first.pin); + const t_port* block_port = logical_block->get_port_by_pin(pin_map.first.pin); - auto sub_tile_port = get_port_by_pin(sub_tile, pin_map.second.pin); + const t_physical_tile_port* sub_tile_port = sub_tile->get_port_by_pin(pin_map.second.pin); VTR_ASSERT(block_port != nullptr); VTR_ASSERT(sub_tile_port != nullptr); diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 80b21308e9f..f991ebf30ad 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -851,6 +851,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->model = nullptr; mem_pb_type->modes[0].num_interconnect = mem_pb_type->num_ports * num_pb; + VTR_ASSERT(mem_pb_type->modes[0].num_interconnect > 0); mem_pb_type->modes[0].interconnect = new t_interconnect[mem_pb_type->modes[0].num_interconnect]; for (i = 0; i < mem_pb_type->modes[0].num_interconnect; i++) { diff --git a/libs/libarchfpga/src/arch_util.h b/libs/libarchfpga/src/arch_util.h index c39cf77b94f..fb251bffe10 100644 --- a/libs/libarchfpga/src/arch_util.h +++ b/libs/libarchfpga/src/arch_util.h @@ -23,8 +23,8 @@ class InstPort { InstPort() = default; InstPort(const std::string& str); - std::string instance_name() const { return instance_.name; } - std::string port_name() const { return port_.name; } + const std::string& instance_name() const { return instance_.name; } + const std::string& port_name() const { return port_.name; } int instance_low_index() const { return instance_.low_idx; } int instance_high_index() const { return instance_.high_idx; } @@ -40,7 +40,7 @@ class InstPort { private: struct name_index { - std::string name = ""; + std::string name; int low_idx = UNSPECIFIED; int high_idx = UNSPECIFIED; }; diff --git a/libs/libarchfpga/src/cad_types.h b/libs/libarchfpga/src/cad_types.h index 5ab46816b99..af0aac9a994 100644 --- a/libs/libarchfpga/src/cad_types.h +++ b/libs/libarchfpga/src/cad_types.h @@ -104,7 +104,7 @@ struct t_pack_patterns { std::vector> chain_root_pins; // default constructor initializing to an invalid pack pattern - t_pack_patterns() { + t_pack_patterns() noexcept { name = nullptr; index = -1; root_block = nullptr; @@ -126,7 +126,7 @@ struct t_cluster_placement_primitive { t_pb_graph_node* pb_graph_node; bool valid; float base_cost; /* cost independent of current status of packing */ - float incremental_cost; /* cost dependant on current status of packing */ + float incremental_cost; /* cost dependent on current status of packing */ }; #endif diff --git a/libs/libarchfpga/src/device_grid.h b/libs/libarchfpga/src/device_grid.h index 8e1332559ed..c04e3f8dc4e 100644 --- a/libs/libarchfpga/src/device_grid.h +++ b/libs/libarchfpga/src/device_grid.h @@ -19,8 +19,11 @@ struct t_grid_tile { const t_metadata_dict* meta = nullptr; }; -///@brief DeviceGrid represents the FPGA fabric. It is used to get information about different layers and tiles. -// TODO: All of the function that use helper functions of this class should pass the layer_num to the functions, and the default value of layer_num should be deleted eventually. +//TODO: All of the functions that use helper functions of this class should pass the layer_num to the functions, and the default value of layer_num should be deleted eventually. +/** + * @class DeviceGrid + * @brief Represents the FPGA fabric. It is used to get information about different layers and tiles. + */ class DeviceGrid { public: DeviceGrid() = default; @@ -77,6 +80,10 @@ class DeviceGrid { inline int get_height_offset(const t_physical_tile_loc& tile_loc) const { return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].height_offset; } + ///@brief Returns true if the given location is the root location (bottom left corner) of a tile. + inline bool is_root_location(const t_physical_tile_loc& tile_loc) const { + return get_width_offset(tile_loc) == 0 && get_height_offset(tile_loc) == 0; + } ///@brief Returns a rectangle which represents the bounding box of the tile at the given location. inline vtr::Rect get_tile_bb(const t_physical_tile_loc& tile_loc) const { diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 4fb52c415f2..edceeb748fb 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -297,7 +297,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { int num_layers = (int)layout.layers.size(); if (num_layers > 1) { fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n", - arch->switches[seg.arch_opin_between_dice_switch].name.c_str()); + arch->switches[seg.arch_inter_die_switch].name.c_str()); } } } else { //Should be bidir diff --git a/libs/libarchfpga/src/parse_switchblocks.cpp b/libs/libarchfpga/src/parse_switchblocks.cpp index 1e8908713bf..3ef9ec8e155 100644 --- a/libs/libarchfpga/src/parse_switchblocks.cpp +++ b/libs/libarchfpga/src/parse_switchblocks.cpp @@ -4,19 +4,15 @@ * * * A large chunk of this file is dedicated to helping parse the initial switchblock - * specificaiton in the XML arch file, providing error checking, etc. + * specification in the XML arch file, providing error checking, etc. * * Another large chunk of this file is dedicated to parsing the actual formulas * specified by the switch block permutation functions into their numeric counterparts. */ -#include +#include #include -#include #include -#include -#include -#include #include "vtr_assert.h" #include "vtr_util.h" @@ -26,9 +22,7 @@ #include "arch_error.h" -#include "read_xml_util.h" #include "arch_util.h" -#include "arch_types.h" #include "physical_types.h" #include "parse_switchblocks.h" diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 3bdabaee2a7..9b72cb95758 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -71,6 +71,42 @@ bool t_rr_switch_inf::configurable() const { return switch_type_is_configurable(type()); } +bool t_rr_switch_inf::operator==(const t_rr_switch_inf& other) const { + return R == other.R + && Cin == other.Cin + && Cout == other.Cout + && Cinternal == other.Cinternal + && Tdel == other.Tdel + && mux_trans_size == other.mux_trans_size + && buf_size == other.buf_size + && power_buffer_type == other.power_buffer_type + && power_buffer_size == other.power_buffer_size + && intra_tile == other.intra_tile + && type() == other.type(); +} + +std::size_t t_rr_switch_inf::Hasher::operator()(const t_rr_switch_inf& s) const { + std::size_t hash_val = 0; + + auto hash_combine = [&hash_val](auto&& val) { + hash_val ^= std::hash>{}(val) + 0x9e3779b9 + (hash_val << 6) + (hash_val >> 2); + }; + + hash_combine(s.R); + hash_combine(s.Cin); + hash_combine(s.Cout); + hash_combine(s.Cinternal); + hash_combine(s.Tdel); + hash_combine(s.mux_trans_size); + hash_combine(s.buf_size); + hash_combine(static_cast(s.power_buffer_type)); + hash_combine(s.power_buffer_size); + hash_combine(s.intra_tile); + hash_combine(static_cast(s.type())); + + return hash_val; +} + void t_rr_switch_inf::set_type(SwitchType type_val) { type_ = type_val; } @@ -136,6 +172,56 @@ bool t_physical_tile_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } +int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_port) const { + int ipin = OPEN; + int port_base_ipin = 0; + int num_port_pins = OPEN; + int pin_offset = 0; + + bool port_found = false; + for (const t_sub_tile& sub_tile : sub_tiles) { + for (const t_physical_tile_port& port : sub_tile.ports) { + if (port_name == port.name) { + port_found = true; + num_port_pins = port.num_pins; + break; + } + + port_base_ipin += port.num_pins; + } + + if (port_found) { + break; + } + + port_base_ipin = 0; + pin_offset += sub_tile.num_phy_pins; + } + + if (num_port_pins != OPEN) { + VTR_ASSERT(pin_index_in_port < num_port_pins); + + ipin = port_base_ipin + pin_index_in_port + pin_offset; + } + + return ipin; +} + +int t_physical_tile_type::find_pin_class(std::string_view port_name, int pin_index_in_port, e_pin_type pin_type) const { + int iclass = OPEN; + + int ipin = find_pin(port_name, pin_index_in_port); + + if (ipin != OPEN) { + iclass = pin_class[ipin]; + + if (iclass != OPEN) { + VTR_ASSERT(class_inf[iclass].type == pin_type); + } + } + return iclass; +} + /* * t_logical_block_type */ @@ -144,6 +230,28 @@ bool t_logical_block_type::is_empty() const { return name == std::string(EMPTY_BLOCK_NAME); } +const t_port* t_logical_block_type::get_port(std::string_view port_name) const { + for (int i = 0; i < pb_type->num_ports; i++) { + auto port = pb_type->ports[i]; + if (port_name == port.name) { + return &pb_type->ports[port.index]; + } + } + + return nullptr; +} + +const t_port* t_logical_block_type::get_port_by_pin(int pin) const { + for (int i = 0; i < pb_type->num_ports; i++) { + const t_port& port = pb_type->ports[i]; + if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { + return &pb_type->ports[port.index]; + } + } + + return nullptr; +} + /** * t_pb_graph_node */ @@ -220,7 +328,7 @@ std::string t_pb_graph_pin::to_string(const bool full_description) const { return pin_string; } -/** +/* * t_pb_graph_edge */ @@ -253,3 +361,39 @@ bool t_pb_graph_edge::belongs_to_pattern(int pattern_index) const { // return false otherwise return false; } + +/* + * t_sub_tile + */ + +int t_sub_tile::total_num_internal_pins() const { + int num_pins = 0; + + for (t_logical_block_type_ptr eq_site : equivalent_sites) { + num_pins += (int)eq_site->pin_logical_num_to_pb_pin_mapping.size(); + } + + num_pins *= capacity.total(); + + return num_pins; +} + +const t_physical_tile_port* t_sub_tile::get_port(std::string_view port_name) { + for (const t_physical_tile_port& port : ports) { + if (port_name == port.name) { + return &ports[port.index]; + } + } + + return nullptr; +} + +const t_physical_tile_port* t_sub_tile::get_port_by_pin(int pin) const { + for (const t_physical_tile_port& port : ports) { + if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { + return &ports[port.index]; + } + } + + return nullptr; +} diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index a0351076127..19a625db601 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -24,8 +24,7 @@ * Authors: Jason Luu and Kenneth Kent */ -#ifndef PHYSICAL_TYPES_H -#define PHYSICAL_TYPES_H +#pragma once #include #include @@ -97,7 +96,7 @@ enum class e_sb_type; // Metadata value storage. class t_metadata_value { public: - explicit t_metadata_value(vtr::interned_string v) + explicit t_metadata_value(vtr::interned_string v) noexcept : value_(v) {} explicit t_metadata_value(const t_metadata_value& o) noexcept : value_(o.value_) {} @@ -546,10 +545,13 @@ struct t_port_power { bool reverse_scaled; /* Scale by (1-prob) */ }; -//The type of Fc specification +/** + * @enum e_fc_type + * @brief The type of Fc specification + */ enum class e_fc_type { - IN, //The fc specification for an input pin - OUT //The fc specification for an output pin + IN, /**< Fc specification for an input pin. */ + OUT /**< Fc specification for an output pin. */ }; //The value type of the Fc specification @@ -709,12 +711,6 @@ struct t_physical_tile_type { * tile_block_pin_directs_map[logical block index][logical block pin] -> physical tile pin */ std::unordered_map>> tile_block_pin_directs_map; - /* Returns the indices of pins that contain a clock for this physical logic block */ - std::vector get_clock_pins_indices() const; - - // Returns the sub tile location of the physical tile given an input pin - int get_sub_tile_loc_from_pin(int pin_num) const; - // TODO: Remove is_input_type / is_output_type as part of // https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193 @@ -724,8 +720,21 @@ struct t_physical_tile_type { // Does this t_physical_tile_type contain an outpad? bool is_output_type = false; - // Is this t_physical_tile_type an empty type? + public: // Function members + ///@brief Returns the indices of pins that contain a clock for this physical logic block + std::vector get_clock_pins_indices() const; + + ///@brief Returns the sub tile location of the physical tile given an input pin + int get_sub_tile_loc_from_pin(int pin_num) const; + + ///@brief Is this t_physical_tile_type an empty type? bool is_empty() const; + + ///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port + int find_pin(std::string_view port_name, int pin_index_in_port) const; + + ///@brief Returns the pin class associated with the specified pin_index_in_port within the port port_name on type + int find_pin_class(std::string_view port_name, int pin_index_in_port, e_pin_type pin_type) const; }; /* Holds the capacity range of a certain sub_tile block within the parent physical tile type. @@ -801,6 +810,19 @@ struct t_sub_tile { int num_phy_pins = 0; int index = -1; + + public: + int total_num_internal_pins() const; + + /** + * @brief Returns the physical tile port given the port name and the corresponding sub tile + */ + const t_physical_tile_port* get_port(std::string_view port_name); + + /** + * @brief Returns the physical tile port given the pin name and the corresponding sub tile + */ + const t_physical_tile_port* get_port_by_pin(int pin) const; }; /** A logical pin defines the pin index of a logical block type (i.e. a top level PB type) @@ -955,6 +977,17 @@ struct t_logical_block_type { // Is this t_logical_block_type empty? bool is_empty() const; + + public: + /** + * @brief Returns the logical block port given the port name and the corresponding logical block type + */ + const t_port* get_port(std::string_view port_name) const; + + /** + * @brief Returns the logical block port given the pin name and the corresponding logical block type + */ + const t_port* get_port_by_pin(int pin) const; }; /************************************************************************************************* @@ -1253,8 +1286,8 @@ struct t_pin_to_pin_annotation { * flat_site_index : Index of this primitive site within its primitive type within this cluster type. * Values are in [0...total_primitive_count-1], e.g. if there are 10 ALMs per cluster, 2 FFS * and 2 LUTs per ALM, then flat site indices for FFs would run from 0 to 19, and flat site - indices for LUTs would run from 0 to 19. This member is only used by nodes corresponding - to primitive sites. It is used when reconstructing clusters from a flat placement file. + * indices for LUTs would run from 0 to 19. This member is only used by nodes corresponding + * to primitive sites. It is used when reconstructing clusters from a flat placement file. * illegal_modes : vector containing illegal modes that result in conflicts during routing */ class t_pb_graph_node { @@ -1308,7 +1341,7 @@ class t_pb_graph_node { int total_pb_pins; /* only valid for top-level */ - void* temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */ + void* temp_scratch_pad; /* temporary data, useful for keeping track of things when traversing data structure */ int* input_pin_class_size; /* Stores the number of pins that belong to a particular input pin class */ int num_input_pin_class; /* number of input pin classes that this pb_graph_node has */ @@ -1318,7 +1351,6 @@ class t_pb_graph_node { int total_primitive_count; /* total number of this primitive type in the cluster */ int flat_site_index; /* index of this primitive within sites of its type in this cluster */ - /* Interconnect instances for this pb * Only used for power */ @@ -1538,6 +1570,7 @@ enum e_directionality { UNI_DIRECTIONAL, BI_DIRECTIONAL }; + /* X_AXIS: Data that describes an x-directed wire segment (CHANX) * * Y_AXIS: Data that describes an y-directed wire segment (CHANY) * * BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */ @@ -1560,115 +1593,186 @@ enum class SegResType { NUM_RES_TYPES }; -constexpr std::array(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING = {{"GCLK", "GENERAL"}}; //String versions of segment resource types +/// String versions of segment resource types +constexpr std::array(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING{"GCLK", "GENERAL"}; +/// Defines the type of switch block used in FPGA routing. enum e_switch_block_type { + /// If the type is SUBSET, I use a Xilinx-like switch block where track i in one channel always + /// connects to track i in other channels. SUBSET, + + /// If type is WILTON, I use a switch block where track i + /// does not always connect to track i in other channels. + /// See Steve Wilton, PhD Thesis, University of Toronto, 1996. WILTON, + + /// The UNIVERSAL switch block is from Y. W. Chang et al, TODAES, Jan. 1996, pp. 80 - 101. UNIVERSAL, + + /// The FULL switch block type allows for complete connectivity between tracks. FULL, + + /// A CUSTOM switch block has also been added which allows a user to describe custom permutation functions and connection patterns. + /// See comment at top of SRC/route/build_switchblocks.c CUSTOM }; -typedef enum e_switch_block_type t_switch_block_type; + enum e_Fc_type { ABSOLUTE, FRACTIONAL }; -/* Lists all the important information about a certain segment type. Only * - * used if the route_type is DETAILED. [0 .. det_routing_arch.num_segment] * - * name: the name of this segment * - * frequency: ratio of tracks which are of this segment type. * - * length: Length (in clbs) of the segment. * - * arch_wire_switch: Index of the switch type that connects other wires * - * *to* this segment. Note that this index is in relation * - * to the switches from the architecture file, not the * - * expanded list of switches that is built at the end of * - * build_rr_graph. * - * arch_opin_switch: Index of the switch type that connects output pins * - * (OPINs) *to* this segment. Note that this index is in * - * relation to the switches from the architecture file, * - * not the expanded list of switches that is built * - * at the end of build_rr_graph * - * @param arch_wire_switch_dec: Same as arch_wire_switch but used only for * - * decremental tracks if it is specified in the * - * architecture file. If -1, this value was not set in * - * the architecture file and arch_wire_switch should be * - * used for "DEC_DIR" wire segments. * - * @param arch_opin_switch_dec: Same as arch_opin_switch but used only for * - * decremental tracks if it is specified in the * - * architecture file. If -1, this value was not set in * - * the architecture file and arch_opin_switch should be * - * used for "DEC_DIR" wire segments. * - * @param arch_opin_between_dice_switch: Index of the switch type that * - * connects output pins (OPINs) *to* this segment from * - * *another die (layer)*. Note that this index is in * - * relation to the switches from the architecture file, * - * not the expanded list of switches that is built at * - * the end of build_rr_graph * - * * - * frac_cb: The fraction of logic blocks along its length to which this * - * segment can connect. (i.e. internal population). * - * frac_sb: The fraction of the length + 1 switch blocks along the segment * - * to which the segment can connect. Segments that aren't long * - * lines must connect to at least two switch boxes. * - * parallel_axis: Defines what axis the segment is parallel to. See * - * e_parallel_axis comments for more details on the values. * - * Cmetal: Capacitance of a routing track, per unit logic block length. * - * Rmetal: Resistance of a routing track, per unit logic block length. * - * (UDSD by AY) drivers: How do signals driving a routing track connect to * - * the track? * - * seg_index: The index of the segment as stored in the appropriate Segs list* - * Upon loading the architecture, we use this field to keep track * - * the segment's index in the unified segment_inf vector. This is * - * useful when building the rr_graph for different Y & X channels * - * in terms of track distribution and segment type. * - * res_type: Determines the routing network to which the segment belongs. * - * Possible values are: * - * - GENERAL: The segment is part of the general routing * - * resources. * - * - GCLK: The segment is part of the global routing network. * - * For backward compatibility, this attribute is optional. If not * - * specified, the resource type for the segment is considered to * - * be GENERAL. * - * meta: Table storing extra arbitrary metadata attributes. * - * - * - * New added parameters for bend wires: * - * isbend: This segment is bend or not * - * bend: The bend type of the segment, "-"-0, "U"-1, "D"-2 * - * For example: bend pattern <- - U ->; corresponding bend: [0,0,1,0] * - * part_len: Divide the segment into several parts based on bend position. * - * For example: length-5 bend segment: <- - U ->; * - * Corresponding part_len: [3,2] */ +/** + * @brief Lists all the important information about a certain segment type. Only + * used if the route_type is DETAILED. [0 .. det_routing_arch.num_segment] + */ struct t_segment_inf { + /** + * @brief The name of the segment type + */ std::string name; + + /** + * @brief ratio of tracks which are of this segment type. + */ int frequency; + + /** + * @brief Length (in clbs) of the segment. + */ int length; + + /** + * @brief Index of the switch type that connects other wires to this segment. + * Note that this index is in relation to the switches from the architecture file, + * not the expanded list of switches that is built at the end of build_rr_graph. + */ short arch_wire_switch; + + /** + * @brief Index of the switch type that connects output pins to this segment. + * Note that this index is in relation to the switches from the architecture file, + * not the expanded list of switches that is built at the end of build_rr_graph. + */ short arch_opin_switch; + + /** + * @brief Same as arch_wire_switch but used only for decremental tracks if it is + * specified in the architecture file. If -1, this value was not set in the + * architecture file and arch_wire_switch should be used for "DEC_DIR" wire segments. + */ short arch_wire_switch_dec = -1; + + /** + * @brief Same as arch_opin_switch but used only for decremental tracks if + * it is specified in the architecture file. If -1, this value was not set in + * the architecture file and arch_opin_switch should be used for "DEC_DIR" wire segments. + */ short arch_opin_switch_dec = -1; - short arch_opin_between_dice_switch = -1; + + /** + * @brief Index of the switch type that connects output pins (OPINs) to this + * segment from another die (layer). Note that this index is in relation to + * the switches from the architecture file, not the expanded list of switches + * that is built at the end of build_rr_graph. + */ + short arch_inter_die_switch = -1; + + /** + * @brief The fraction of logic blocks along its length to which this segment can connect. + * (i.e. internal population). + */ float frac_cb; + + /** + * @brief The fraction of the length + 1 switch blocks along the segment to which the segment can connect. + * Segments that aren't long lines must connect to at least two switch boxes. + */ float frac_sb; + bool longline; + + /** + * @brief The resistance of a routing track, per unit logic block length. */ float Rmetal; + + /** + * @brief The capacitance of a routing track, per unit logic block length. */ float Cmetal; + enum e_directionality directionality; + + /** + * @brief Defines what axis the segment is parallel to. See e_parallel_axis + * comments for more details on the values. + */ enum e_parallel_axis parallel_axis; + + /** + * @brief A vector of booleans indicating whether the segment can connect to a logic block. + */ std::vector cb; + + /** + * @brief A vector of booleans indicating whether the segment can connect to a switch block. + */ std::vector sb; - bool isbend; + + /** + * @brief This segment is bend or not + */ + bool isbend; + + /** + * @brief The bend type of the segment, "-"-0, "U"-1, "D"-2 + * For example: bend pattern <- - U ->; corresponding bend: [0,0,1,0] + */ std::vector bend; + + /** + * @brief Divide the segment into several parts based on bend position. + * For example: length-5 bend segment: <- - U ->; + * Corresponding part_len: [3,2] + */ std::vector part_len; + + /** + * @brief The index of the segment as stored in the appropriate Segs list. + * Upon loading the architecture, we use this field to keep track of the + * segment's index in the unified segment_inf vector. This is useful when + * building the rr_graph for different Y & X channels in terms of track + * distribution and segment type. + */ int seg_index; + + /** + * @brief Determines the routing network to which the segment belongs. + * Possible values are: + * - GENERAL: The segment is part of the general routing resources. + * - GCLK: The segment is part of the global routing network. + * For backward compatibility, this attribute is optional. If not specified, + * the resource type for the segment is considered to be GENERAL. + */ enum SegResType res_type = SegResType::GENERAL; - //float Cmetal_per_m; /* Wire capacitance (per meter) */ }; inline bool operator==(const t_segment_inf& a, const t_segment_inf& b) { - return a.name == b.name && a.frequency == b.frequency && a.length == b.length && a.arch_wire_switch == b.arch_wire_switch && a.arch_opin_switch == b.arch_opin_switch && a.arch_opin_between_dice_switch == b.arch_opin_between_dice_switch && a.frac_cb == b.frac_cb && a.frac_sb == b.frac_sb && a.longline == b.longline && a.Rmetal == b.Rmetal && a.Cmetal == b.Cmetal && a.directionality == b.directionality && a.parallel_axis == b.parallel_axis && a.cb == b.cb && a.sb == b.sb; + return a.name == b.name + && a.frequency == b.frequency + && a.length == b.length + && a.arch_wire_switch == b.arch_wire_switch + && a.arch_opin_switch == b.arch_opin_switch + && a.arch_inter_die_switch == b.arch_inter_die_switch + && a.frac_cb == b.frac_cb + && a.frac_sb == b.frac_sb + && a.longline == b.longline + && a.Rmetal == b.Rmetal + && a.Cmetal == b.Cmetal + && a.directionality == b.directionality + && a.parallel_axis == b.parallel_axis + && a.cb == b.cb + && a.sb == b.sb; } /*provide hashing for t_segment_inf to enable the use of many std containers. @@ -1840,16 +1944,28 @@ struct t_rr_switch_inf { bool intra_tile = false; public: - //Returns the type of switch + /// Returns the type of switch SwitchType type() const; - //Returns true if this switch type isolates its input and output into - //separate DC-connected subcircuits + /// Returns true if this switch type isolates its input and output into + /// separate DC-connected subcircuits bool buffered() const; - //Returns true if this switch type is configurable + /// Returns true if this switch type is configurable bool configurable() const; + bool operator==(const t_rr_switch_inf& other) const; + + /** + * @brief Functor for computing a hash value for t_rr_switch_inf. + * + * This custom hasher enables the use of t_rr_switch_inf objects as keys + * in unordered containers such as std::unordered_map or std::unordered_set. + */ + struct Hasher { + std::size_t operator()(const t_rr_switch_inf& s) const; + }; + public: void set_type(SwitchType type_val); @@ -1973,7 +2089,7 @@ struct t_switchblock_inf { /* We can also define a region to apply this SB to all locations falls into this region using regular expression in the architecture file*/ t_sb_loc_spec reg_x; t_sb_loc_spec reg_y; - + t_permutation_map permutation_map; /* map holding the permutation functions attributed to this switchblock */ std::vector wireconns; /* list of wire types/groups this SB will connect */ @@ -2062,8 +2178,6 @@ struct t_noc_inf { std::string noc_router_tile_name; }; - - /* Detailed routing architecture */ struct t_arch { /** Stores unique strings used as key and values in tags, @@ -2143,11 +2257,11 @@ struct t_arch { std::vector ipin_cblock_switch_name; std::vector grid_layouts; //Set of potential device layouts - + //the layout that is chosen to be used with command line options //It is used to generate custom SB for a specific locations within the device //If the layout is not specified in the command line options, this variable will be set to "auto" - std::string device_layout; + std::string device_layout; std::vector vib_grid_layouts; @@ -2160,5 +2274,3 @@ struct t_arch { //bool is_vib_arch = false; std::vector vib_infs; }; - -#endif diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 2256f81d66c..2ecc7fbd41c 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -154,7 +154,7 @@ static std::tuple get_pin_index_for_inst(t_physical_til pin_inst_num = (pin_physical_num - pin_offset) % pins_per_inst; } else { int pin_offset = get_sub_tile_inst_physical_pin_num_offset(type, sub_tile, sub_tile_cap); - int pins_per_inst = get_total_num_sub_tile_internal_pins(sub_tile) / sub_tile->capacity.total(); + int pins_per_inst = sub_tile->total_num_internal_pins() / sub_tile->capacity.total(); pin_inst_num = (pin_physical_num - pin_offset) % pins_per_inst; } @@ -225,7 +225,7 @@ static int get_sub_tile_physical_pin_num_offset(t_physical_tile_type_ptr physica if (&tmp_sub_tile == curr_sub_tile) break; else - offset += get_total_num_sub_tile_internal_pins(&tmp_sub_tile); + offset += tmp_sub_tile.total_num_internal_pins(); } return offset; @@ -235,7 +235,7 @@ static int get_sub_tile_inst_physical_pin_num_offset(t_physical_tile_type_ptr ph const t_sub_tile* curr_sub_tile, const int curr_relative_cap) { int offset = get_sub_tile_physical_pin_num_offset(physical_tile, curr_sub_tile); - int sub_tile_inst_num_pins = get_total_num_sub_tile_internal_pins(curr_sub_tile) / curr_sub_tile->capacity.total(); + int sub_tile_inst_num_pins = curr_sub_tile->total_num_internal_pins() / curr_sub_tile->capacity.total(); offset += (curr_relative_cap * sub_tile_inst_num_pins); @@ -563,57 +563,6 @@ int get_max_num_pins(t_logical_block_type_ptr logical_block) { return max_num_pins; } -//Returns the pin class associated with the specified pin_index_in_port within the port port_name on type -int find_pin_class(t_physical_tile_type_ptr type, std::string port_name, int pin_index_in_port, e_pin_type pin_type) { - int iclass = OPEN; - - int ipin = find_pin(type, port_name, pin_index_in_port); - - if (ipin != OPEN) { - iclass = type->pin_class[ipin]; - - if (iclass != OPEN) { - VTR_ASSERT(type->class_inf[iclass].type == pin_type); - } - } - return iclass; -} - -int find_pin(t_physical_tile_type_ptr type, std::string port_name, int pin_index_in_port) { - int ipin = OPEN; - int port_base_ipin = 0; - int num_pins = OPEN; - int pin_offset = 0; - - bool port_found = false; - for (const auto& sub_tile : type->sub_tiles) { - for (const auto& port : sub_tile.ports) { - if (0 == strcmp(port.name, port_name.c_str())) { - port_found = true; - num_pins = port.num_pins; - break; - } - - port_base_ipin += port.num_pins; - } - - if (port_found) { - break; - } - - port_base_ipin = 0; - pin_offset += sub_tile.num_phy_pins; - } - - if (num_pins != OPEN) { - VTR_ASSERT(pin_index_in_port < num_pins); - - ipin = port_base_ipin + pin_index_in_port + pin_offset; - } - - return ipin; -} - std::pair get_capacity_location_from_physical_pin(t_physical_tile_type_ptr physical_tile, int pin) { int pins_to_remove = 0; for (const auto& sub_tile : physical_tile->sub_tiles) { @@ -638,7 +587,7 @@ std::pair get_capacity_location_from_physical_pin(t_physical_tile_type int get_physical_pin_from_capacity_location(t_physical_tile_type_ptr physical_tile, int relative_pin, int capacity_location) { int pins_to_add = 0; - for (auto sub_tile : physical_tile->sub_tiles) { + for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) { auto capacity = sub_tile.capacity; int rel_capacity = capacity_location - capacity.low; int num_inst_pins = sub_tile.num_phy_pins / capacity.total(); @@ -841,52 +790,6 @@ std::vector block_type_class_index_to_pin_names(t_physical_tile_typ return pin_names; } -const t_physical_tile_port* get_port_by_name(t_sub_tile* sub_tile, const char* port_name) { - for (auto port : sub_tile->ports) { - if (0 == strcmp(port.name, port_name)) { - return &sub_tile->ports[port.index]; - } - } - - return nullptr; -} - -const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* port_name) { - auto pb_type = type->pb_type; - - for (int i = 0; i < pb_type->num_ports; i++) { - auto port = pb_type->ports[i]; - if (0 == strcmp(port.name, port_name)) { - return &pb_type->ports[port.index]; - } - } - - return nullptr; -} - -const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin) { - for (auto port : sub_tile->ports) { - if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { - return &sub_tile->ports[port.index]; - } - } - - return nullptr; -} - -const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin) { - auto pb_type = type->pb_type; - - for (int i = 0; i < pb_type->num_ports; i++) { - auto port = pb_type->ports[i]; - if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) { - return &pb_type->ports[port.index]; - } - } - - return nullptr; -} - /* Access information related to pin classes */ /** get information given class physical num **/ @@ -1009,7 +912,7 @@ std::tuple get_sub_tile_from_pin_physical_num(t_physical int pin_offset = total_pin_counts; for (auto& sub_tile : physical_tile->sub_tiles) { - int sub_tile_num_pins = pin_on_tile ? sub_tile.num_phy_pins : get_total_num_sub_tile_internal_pins(&sub_tile); + int sub_tile_num_pins = pin_on_tile ? sub_tile.num_phy_pins : sub_tile.total_num_internal_pins(); total_pin_counts += sub_tile_num_pins; if (physical_num < total_pin_counts) { @@ -1347,15 +1250,6 @@ const t_pb_graph_node* get_pb_graph_node_from_pin_physical_num(t_physical_tile_t return pb_graph_pin->parent_node; } -int get_total_num_sub_tile_internal_pins(const t_sub_tile* sub_tile) { - int num_pins = 0; - for (auto eq_site : sub_tile->equivalent_sites) { - num_pins += (int)eq_site->pin_logical_num_to_pb_pin_mapping.size(); - } - num_pins *= sub_tile->capacity.total(); - return num_pins; -} - int get_tile_pin_max_ptc(t_physical_tile_type_ptr tile, bool is_flat) { if (is_flat) { return tile->num_pins + (int)tile->pin_num_to_pb_pin.size(); @@ -1538,4 +1432,3 @@ std::map get_sink_choking_points(t_physical_tile_type_ptr physical_til return choking_point; } -/* */ diff --git a/libs/libarchfpga/src/physical_types_util.h b/libs/libarchfpga/src/physical_types_util.h index aa7b2617834..a081683faeb 100644 --- a/libs/libarchfpga/src/physical_types_util.h +++ b/libs/libarchfpga/src/physical_types_util.h @@ -1,5 +1,5 @@ -#ifndef PHYSICAL_TYPES_UTIL_H -#define PHYSICAL_TYPES_UTIL_H + +#pragma once #include "physical_types.h" @@ -13,11 +13,11 @@ * functions in this file are the following: * * - physical_tile_type: identifies a placeable tile within * * the device grid. * - * - logical_block_tpye: identifies a clustered block type * + * - logical_block_type: identifies a clustered block type * * within the clb_netlist * * * * All the following utilities are intended to ease the * - * developement to access the above mentioned classes and perform * + * development to access the above mentioned classes and perform * * some required operations with their data. * * * * Please classify such functions in this file * @@ -107,7 +107,7 @@ * * For instance, the following information are required: * - mapping between logical and sub tile pins. - * - mapping between sub tile pins and absoulte physical pin + * - mapping between sub tile pins and absolute physical pin * - capacity instance of the sub tile * * With all the above information we can calculate correctly the connection between the CLK (logical pin) @@ -152,12 +152,12 @@ int get_physical_pin_from_capacity_location(t_physical_tile_type_ptr physical_ti * * Take the above CLOCK TILE example: * - given the CLOCK TILE and the index corresponding to the CLK_1 pin, we want the relative pin - * of one of its sub tiles at a particualr capacity location (i.e. sub tile instance). + * of one of its sub tiles at a particular capacity location (i.e. sub tile instance). * * std::tie(absolute_capacity, relative_pin) = get_capacity_location_from_physical_pin(clock_tile, 3) * * The value returned is (1, 0), where: - * - 1 corresponds to the capacity location (sub tile instance) where the absoulte physical pin index (CLK_1) is connected + * - 1 corresponds to the capacity location (sub tile instance) where the absolute physical pin index (CLK_1) is connected * - 0 corresponds to the relative pin index within the BUFGCTRL sub tile */ std::pair get_capacity_location_from_physical_pin(t_physical_tile_type_ptr physical_tile, int pin); @@ -173,11 +173,6 @@ std::vector block_type_class_index_to_pin_names(t_physical_tile_typ ///@brief Returns the physical tile type matching a given physical tile type name, or nullptr (if not found) t_physical_tile_type_ptr find_tile_type_by_name(const std::string& name, const std::vector& types); -int find_pin_class(t_physical_tile_type_ptr type, std::string port_name, int pin_index_in_port, e_pin_type pin_type); - -///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port -int find_pin(t_physical_tile_type_ptr type, std::string port_name, int pin_index_in_port); - ///@brief Returns the maximum number of pins within a logical block int get_max_num_pins(t_logical_block_type_ptr logical_block); @@ -217,7 +212,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_ t_logical_block_type_ptr logical_block); /** * @brief Returns the physical pin index (within 'physical_tile') corresponding to the - * logical index ('pin' of the first instance of 'logical_block' within the physcial tile. + * logical index ('pin' of the first instance of 'logical_block' within the physical tile. * * This function is called before/during placement, when a sub tile index was not yet assigned. * @@ -228,7 +223,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile, int pin); /** * @brief Returns the physical pin index (within 'physical_tile') corresponding to the - * logical index ('pin' of the first instance of 'logical_block' within the physcial tile. + * logical index ('pin' of the first instance of 'logical_block' within the physical tile. * This function considers if a given offset is in the range of sub tile capacity * * (First pin index at current sub-tile) (The wanted pin index) @@ -286,26 +281,6 @@ int get_sub_tile_physical_pin(int sub_tile_index, */ t_physical_tile_port find_tile_port_by_name(t_physical_tile_type_ptr type, std::string_view port_name); -/** - * @brief Returns the physical tile port given the port name and the corresponding sub tile - */ -const t_physical_tile_port* get_port_by_name(t_sub_tile* sub_tile, const char* port_name); - -/** - * @brief Returns the logical block port given the port name and the corresponding logical block type - */ -const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* port_name); - -/** - * @brief Returns the physical tile port given the pin name and the corresponding sub tile - */ -const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin); - -/** - * @brief Returns the logical block port given the pin name and the corresponding logical block type - */ -const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin); - /************************************ Access to intra-block resources ************************************/ /* Access information related to pin classes */ @@ -336,12 +311,6 @@ inline bool is_class_on_tile(t_physical_tile_type_ptr physical_tile, int class_p /** * @brief Classes are indexed in a way that the number of classes on the same pb_graph_node is continuous - * @param physical_tile - * @param sub_tile - * @param logical_block - * @param sub_tile_relative_cap - * @param pb_graph_node - * @return */ t_class_range get_pb_graph_node_class_physical_range(t_physical_tile_type_ptr physical_tile, const t_sub_tile* sub_tile, @@ -358,15 +327,11 @@ std::vector get_tile_root_classes(t_physical_tile_type_ptr physical_type); /** * Get the number of all classes, on the tile and inside the cluster. - * @param physical_type - * @return */ t_class_range get_flat_tile_primitive_classes(t_physical_tile_type_ptr physical_type); /** **/ int get_tile_class_max_ptc(t_physical_tile_type_ptr tile, bool is_flat); -/* */ - /* Access information related to pins */ /** get information given pin physical number **/ @@ -434,8 +399,6 @@ int get_edge_sw_arch_idx(t_physical_tile_type_ptr physical_tile, const t_pb_graph_node* get_pb_graph_node_from_pin_physical_num(t_physical_tile_type_ptr physical_type, int pin_physical_num); -int get_total_num_sub_tile_internal_pins(const t_sub_tile* sub_tile); - int get_tile_pin_max_ptc(t_physical_tile_type_ptr tile, bool is_flat); int get_tile_num_internal_pin(t_physical_tile_type_ptr tile); @@ -459,11 +422,6 @@ float get_pin_primitive_comb_delay(t_physical_tile_type_ptr physical_type, /** * @brief This function is used during reachability analysis to check whether two classes should be put in the same group - * @param physical_tile - * @param first_class_ptc_num - * @param second_class_ptc_num - * @param is_flat - * @return */ bool classes_in_same_block(t_physical_tile_type_ptr physical_tile, int first_class_ptc_num, @@ -473,15 +431,8 @@ bool classes_in_same_block(t_physical_tile_type_ptr physical_tile, /** * @brief Given the sink group, identify the pins which can reach both sink_ptc_num and at least one of the sinks, * in the grp. - * @param physical_tile - * @param sink_ptc_num - * @param grp * @return Key is the pin number and value is the number of sinks, including sink_ptc_num, in the grp reachable by the pin */ std::map get_sink_choking_points(t_physical_tile_type_ptr physical_tile, int sink_ptc_num, const std::vector& grp); - -/* */ - -#endif diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 8737503da3b..50840cbb948 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -5,28 +5,28 @@ #ifdef VTR_ENABLE_CAPNPROTO -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include - -# include "vtr_assert.h" -# include "vtr_digest.h" -# include "vtr_log.h" -# include "vtr_memory.h" -# include "vtr_util.h" - -# include "arch_check.h" -# include "arch_error.h" -# include "arch_util.h" -# include "arch_types.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vtr_assert.h" +#include "vtr_digest.h" +#include "vtr_log.h" +#include "vtr_memory.h" +#include "vtr_util.h" + +#include "arch_check.h" +#include "arch_error.h" +#include "arch_util.h" +#include "arch_types.h" /* * FPGA Interchange Device frontend @@ -1076,7 +1076,7 @@ struct ArchReader { continue; // Check for duplicates - auto is_duplicate = [name](const t_logical_block_type& l)-> bool { return l.name == name; }; + auto is_duplicate = [name](const t_logical_block_type& l) -> bool { return l.name == name; }; VTR_ASSERT(std::find_if(ltypes_.begin(), ltypes_.end(), is_duplicate) == ltypes_.end()); ltype.name = name; diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.h b/libs/libarchfpga/src/read_fpga_interchange_arch.h index c859f97a002..753b44d3010 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.h +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.h @@ -5,12 +5,12 @@ #ifdef VTR_ENABLE_CAPNPROTO -# include "DeviceResources.capnp.h" -# include "LogicalNetlist.capnp.h" -# include "capnp/serialize.h" -# include "capnp/serialize-packed.h" -# include -# include +#include "DeviceResources.capnp.h" +#include "LogicalNetlist.capnp.h" +#include "capnp/serialize.h" +#include "capnp/serialize-packed.h" +#include +#include #endif // VTR_ENABLE_CAPNPROTO diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 9c6d4de6608..5e6c96fbfa0 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -199,7 +199,7 @@ static void ProcessSubTiles(pugi::xml_node Node, * string interment storage. * @param loc_data Points to the location in the architecture file where the parser is reading. * @param pb_idx Used to assign unique values to index_in_logical_block field in -* t_pb_type for all pb_types under a logical block type. + * t_pb_type for all pb_types under a logical block type. */ static void ProcessPb_Type(pugi::xml_node Parent, t_pb_type* pb_type, @@ -258,7 +258,7 @@ static void ProcessMode(pugi::xml_node Parent, * @brief Processes tags. * * @param strings String internment storage used to store strings used -* as keys and values in tags. + * as keys and values in tags. * @param Parent An XML node pointing to the parent tag whose children * are to be parsed. * @param loc_data Points to the location in the architecture file where the parser is reading. @@ -316,7 +316,6 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); - static t_grid_def ProcessGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); static void ProcessBlockTypeLocs(t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); @@ -380,7 +379,6 @@ static void ProcessPower(pugi::xml_node parent, static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data); - static void ProcessPb_TypePowerEstMethod(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data); static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const pugiutil::loc_data& loc_data); @@ -418,7 +416,7 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vector& PhysicalTileTypes, std::vector& first_stages, const pugiutil::loc_data& loc_data); static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& second_stages, const pugiutil::loc_data& loc_data); // static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector& froms); -void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); +// static void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); /* * @@ -936,7 +934,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, "No port name is present: %s\n", pin_loc_string); } - auto port = get_port_by_name(type, token.data); + auto port = type->get_port(token.data); if (port == nullptr) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Port %s for %s could not be found: %s\n", @@ -1911,10 +1909,9 @@ static void ProcessInterconnect(vtr::string_internment& strings, } mode->interconnect[interconnect_idx].annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, - sizeof(t_pin_to_pin_annotation)); + sizeof(t_pin_to_pin_annotation)); mode->interconnect[interconnect_idx].num_annotations = num_annotations; - int annotation_idx = 0; for (auto annot_child_name : {"delay_constant", "delay_matrix", "C_constant", "C_matrix", "pack_pattern"}) { pugi::xml_node Cur2 = get_first_child(Cur, annot_child_name, loc_data, ReqOpt::OPTIONAL); @@ -1932,7 +1929,7 @@ static void ProcessInterconnect(vtr::string_internment& strings, /* Power */ mode->interconnect[interconnect_idx].interconnect_power = (t_interconnect_power*)vtr::calloc(1, - sizeof(t_interconnect_power)); + sizeof(t_interconnect_power)); mode->interconnect[interconnect_idx].interconnect_power->port_info_initialized = false; /* get next iteration */ @@ -4006,7 +4003,7 @@ static std::vector ProcessSegments(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "'%s' is not a valid mux name.\n", tmp); } - Segs[i].arch_opin_between_dice_switch = switch_idx; + Segs[i].arch_inter_die_switch = switch_idx; } /* Get the wire and opin switches, or mux switch if unidir */ @@ -4016,63 +4013,61 @@ static std::vector ProcessSegments(pugi::xml_node Parent, tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); //check if tag is defined in the architecture, otherwise we should look for and - if(tmp){ + if (tmp) { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "'%s' is not a valid mux name.\n", tmp); + "'%s' is not a valid mux name.\n", tmp); } /* Unidir muxes must have the same switch - * for wire and opin fanin since there is - * really only the mux in unidir. */ + * for wire and opin fanin since there is + * really only the mux in unidir. */ Segs[i].arch_wire_switch = switch_idx; Segs[i].arch_opin_switch = switch_idx; - } - else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file + } else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file SubElem = get_single_child(Node, "mux_inc", loc_data, ReqOpt::OPTIONAL); tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if(!tmp){ + if (!tmp) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); - } else{ + "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); + } else { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "'%s' is not a valid mux name.\n", tmp); + "'%s' is not a valid mux name.\n", tmp); } /* Unidir muxes must have the same switch - * for wire and opin fanin since there is - * really only the mux in unidir. */ + * for wire and opin fanin since there is + * really only the mux in unidir. */ Segs[i].arch_wire_switch = switch_idx; Segs[i].arch_opin_switch = switch_idx; } SubElem = get_single_child(Node, "mux_dec", loc_data, ReqOpt::OPTIONAL); tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); - if(!tmp){ + if (!tmp) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); - } else{ + "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); + } else { /* Match names */ int switch_idx = find_switch_by_name(switches, tmp); if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "'%s' is not a valid mux name.\n", tmp); + "'%s' is not a valid mux name.\n", tmp); } /* Unidir muxes must have the same switch - * for wire and opin fanin since there is - * really only the mux in unidir. */ + * for wire and opin fanin since there is + * really only the mux in unidir. */ Segs[i].arch_wire_switch_dec = switch_idx; Segs[i].arch_opin_switch_dec = switch_idx; } } - } - else { + } else { VTR_ASSERT(BI_DIRECTIONAL == Segs[i].directionality); SubElem = get_single_child(Node, "wire_switch", loc_data); tmp = get_attribute(SubElem, "name", loc_data).value(); @@ -4197,11 +4192,11 @@ static void ProcessBend(pugi::xml_node Node, std::vector& list, std::vector int tmp_len = 1; int sum_len = 0; - for(size_t i_len = 0; i_len < list.size(); i_len++){ + for (size_t i_len = 0; i_len < list.size(); i_len++) { if (list[i_len] == 0) { tmp_len++; } else if (list[i_len] != 0) { - VTR_ASSERT(tmp_len < (int) list.size()+1); + VTR_ASSERT(tmp_len < (int)list.size() + 1); part_len.push_back(tmp_len); sum_len += tmp_len; tmp_len = 1; @@ -4209,16 +4204,16 @@ static void ProcessBend(pugi::xml_node Node, std::vector& list, std::vector } // add the last clip of segment - if (sum_len < (int) list.size()+1) + if (sum_len < (int)list.size() + 1) part_len.push_back(list.size() + 1 - sum_len); } -static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb){ +static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb) { auto startx_attr = get_attribute(SubElem, "startx", loc_data, ReqOpt::OPTIONAL); - auto endx_attr = get_attribute(SubElem, "endx", loc_data, ReqOpt::OPTIONAL); + auto endx_attr = get_attribute(SubElem, "endx", loc_data, ReqOpt::OPTIONAL); auto starty_attr = get_attribute(SubElem, "starty", loc_data, ReqOpt::OPTIONAL); - auto endy_attr = get_attribute(SubElem, "endy", loc_data, ReqOpt::OPTIONAL); + auto endy_attr = get_attribute(SubElem, "endy", loc_data, ReqOpt::OPTIONAL); auto repeatx_attr = get_attribute(SubElem, "repeatx", loc_data, ReqOpt::OPTIONAL); auto repeaty_attr = get_attribute(SubElem, "repeaty", loc_data, ReqOpt::OPTIONAL); @@ -4233,19 +4228,17 @@ static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, co vars.set_var_value("W", grid_width); vars.set_var_value("H", grid_height); - sb.reg_x.start = startx_attr.empty() ? 0 : p.parse_formula(startx_attr.value(), vars); sb.reg_y.start = starty_attr.empty() ? 0 : p.parse_formula(starty_attr.value(), vars); sb.reg_x.end = endx_attr.empty() ? (grid_width - 1) : p.parse_formula(endx_attr.value(), vars); - sb.reg_y.end = endy_attr.empty() ? (grid_height -1) : p.parse_formula(endy_attr.value(), vars); + sb.reg_y.end = endy_attr.empty() ? (grid_height - 1) : p.parse_formula(endy_attr.value(), vars); sb.reg_x.repeat = repeatx_attr.empty() ? 0 : p.parse_formula(repeatx_attr.value(), vars); sb.reg_y.repeat = repeaty_attr.empty() ? 0 : p.parse_formula(repeaty_attr.value(), vars); sb.reg_x.incr = incrx_attr.empty() ? 1 : p.parse_formula(incrx_attr.value(), vars); sb.reg_y.incr = incry_attr.empty() ? 1 : p.parse_formula(incry_attr.value(), vars); - } /* Processes the switchblocklist section from the xml architecture file. @@ -4259,10 +4252,10 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu /* get the number of switchblocks */ int num_switchblocks = count_children(Parent, "switchblock", loc_data); arch->switchblocks.reserve(num_switchblocks); - + int layout_index = -1; - for(layout_index = 0; layout_index < (int) arch->grid_layouts.size(); layout_index++){ - if(arch->grid_layouts.at(layout_index).name == arch->device_layout){ + for (layout_index = 0; layout_index < (int)arch->grid_layouts.size(); layout_index++) { + if (arch->grid_layouts.at(layout_index).name == arch->device_layout) { //found the used layout break; } @@ -4314,8 +4307,8 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu } /* get the switchblock coordinate only if sb.location is set to E_XY_SPECIFIED*/ - if(sb.location == e_sb_location::E_XY_SPECIFIED){ - if (arch->device_layout == "auto"){ + if (sb.location == e_sb_location::E_XY_SPECIFIED) { + if (arch->device_layout == "auto") { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "Specifying SB locations for auto layout devices are not supported yet!\n"); } expect_only_attributes(SubElem, @@ -4326,17 +4319,17 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu int grid_width = arch->grid_layouts.at(layout_index).width; int grid_height = arch->grid_layouts.at(layout_index).height; - + /* Absolute location that this SB must be applied to, -1 if not specified*/ sb.x = get_attribute(SubElem, "x", loc_data, ReqOpt::OPTIONAL).as_int(-1); sb.y = get_attribute(SubElem, "y", loc_data, ReqOpt::OPTIONAL).as_int(-1); //check if the absolute value is within the device grid width and height - if(sb.x >= grid_width || sb.y >= grid_height) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), \ - "Location (%d,%d) is not valid within the grid! grid dimensions are: (%d,%d)\n", sb.x, sb.y, grid_width, grid_height); + if (sb.x >= grid_width || sb.y >= grid_height) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + "Location (%d,%d) is not valid within the grid! grid dimensions are: (%d,%d)\n", sb.x, sb.y, grid_width, grid_height); } - + /* if the the switchblock exact location is not specified and a region is specified within the architecture file, * we have to parse the region specification and apply the SB pattern to all the locations fall into the specified * region based on device width and height. @@ -4344,7 +4337,6 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu if (sb.x == -1 && sb.y == -1) { calculate_custom_SB_locations(loc_data, SubElem, grid_width, grid_height, sb); } - } /* get switchblock permutation functions */ @@ -5134,7 +5126,7 @@ static T* get_type_by_name(std::string_view type_name, std::vector& types) { // // we decrease the mesh size by 1 when calculating the spacing so that the first and last routers of each row or column are positioned on the mesh boundary // /* // * For example: -// * - If we had a mesh size of 3, then using 3 would result in a spacing that would result in one router positions being placed in either the start of the reigion or end of the region. This is because the distance calculation resulted in having 3 spaces between the ends of the region +// * - If we had a mesh size of 3, then using 3 would result in a spacing that would result in one router positions being placed in either the start of the reigion or end of the region. This is because the distance calculation resulted in having 3 spaces between the ends of the region // * // * start end // *** *** *** *** @@ -5268,11 +5260,11 @@ static T* get_type_by_name(std::string_view type_name, std::vector& types) { // } // /* Each router needs a sperate tag in the architecture description -// * to declare it. The number of declarations for each router in the +// * to declare it. The number of declarations for each router in the // * architecture file is updated here. // * // * Additionally, for any given topology, a router can connect to other routers. -// * THe number of connections for each router is also updated here. +// * THe number of connections for each router is also updated here. // * // */ // static void update_router_info_in_arch(int router_id, bool router_updated_as_a_connection, std::map>& routers_in_arch_info) { @@ -5303,7 +5295,7 @@ static T* get_type_by_name(std::string_view type_name, std::vector& types) { // * Verify each router in the noc by checking whether they satisfy the following conditions: // * - The router has only one declaration in the arch file // * - The router has atleast one connection to another router -// * If any of the conditions above are not met, then an error is thrown. +// * If any of the conditions above are not met, then an error is thrown. // */ // static void verify_noc_topology(std::map>& routers_in_arch_info) { // for (auto router_info = routers_in_arch_info.begin(); router_info != routers_in_arch_info.end(); router_info++) { @@ -5336,7 +5328,7 @@ static void ProcessVibArch(pugi::xml_node Parent, std::vectorvib_infs.reserve(num_vibs); Node = get_first_child(Parent, "vib", loc_data); - + for (int i_vib = 0; i_vib < num_vibs; i_vib++) { ProcessVib(Node, PhysicalTileTypes, arch, loc_data); Node = Node.next_sibling(Node.name()); @@ -5356,8 +5348,7 @@ static void ProcessVib(pugi::xml_node Vib_node, std::vectorvib_infs.push_back(vib); } -static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& first_stages, const pugiutil::loc_data& loc_data) { +static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& /*PhysicalTileTypes*/, std::vector& first_stages, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; pugi::xml_node SubElem; //pugi::xml_node Cur; @@ -5500,7 +5485,7 @@ static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& second_stages, const pugiutil::loc_data& loc_data) { +static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& /*PhysicalTileTypes*/, std::vector& second_stages, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; pugi::xml_node SubElem; //pugi::xml_node Cur; @@ -5529,7 +5514,7 @@ static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector all_sub_tile_to_tile_pin_indices; // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { // int sub_tile_capacity = sub_tile.capacity.total(); @@ -5615,14 +5600,14 @@ static void ProcessSecondStage(pugi::xml_node Stage_node, std::vectorvib_grid_layouts.emplace_back(std::move(grid_def)); } - } static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer) { @@ -5818,13 +5801,13 @@ static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi grid_def.grid_type = VibGridDefType::VIB_AUTO; grid_def.name = "auto"; - for (size_t i = 0;i < arch->grid_layouts.size(); i++) { + for (size_t i = 0; i < arch->grid_layouts.size(); i++) { if (arch->grid_layouts[i].name == grid_def.name) { grid_def.aspect_ratio = arch->grid_layouts[i].aspect_ratio; } } //grid_def.aspect_ratio = get_attribute(layout_type_tag, "aspect_ratio", loc_data, ReqOpt::OPTIONAL).as_float(1.); - + } else if (layout_type_tag.name() == std::string("fixed_layout")) { expect_only_attributes(layout_type_tag, {"name"}, loc_data); @@ -6118,4 +6101,3 @@ static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, } } } - diff --git a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp index a9b6091686d..aa415590551 100644 --- a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp @@ -1,3 +1,4 @@ +#include #include "read_xml_arch_file_noc_tag.h" @@ -17,8 +18,8 @@ * @param noc_ref To be filled with NoC router locations and their connectivity. */ static void process_topology(pugi::xml_node topology_tag, - const pugiutil::loc_data& loc_data, - t_noc_inf* noc_ref); + const pugiutil::loc_data& loc_data, + t_noc_inf* noc_ref); /** * @brief Process a tag under a tag. @@ -49,8 +50,8 @@ static void process_router(pugi::xml_node router_tag, * @param noc_ref To be filled with NoC router locations and their connectivity. */ static void process_mesh_topology(pugi::xml_node mesh_topology_tag, - const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref); - + const pugiutil::loc_data& loc_data, + t_noc_inf* noc_ref); /** * Create routers and set their properties so that a mesh grid of routers is created. @@ -59,19 +60,12 @@ static void process_mesh_topology(pugi::xml_node mesh_topology_tag, * @param mesh_topology_tag An XML tag pointing to a tag. * @param loc_data Points to the location in the xml file where the parser is reading. * @param noc_ref To be filled with NoC router locations and their connectivity. - * @param mesh_region_start_x The location the bottom left NoC router on the X-axis. - * @param mesh_region_end_x The location the top right NoC router on the X-axis. - * @param mesh_region_start_y The location the bottom left NoC router on the Y-axis. - * @param mesh_region_end_y The location the top right NoC router on the Y-axis. - * @param mesh_size The number of NoC routers in each row or column. + * @param mesh_region Specifies the number of NoC routers and their locations in a mesh. */ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, - float mesh_region_start_x, float mesh_region_end_x, - float mesh_region_start_y, float mesh_region_end_y, - int mesh_region_start_layer, int mesh_region_end_layer, - int mesh_size); + const t_mesh_region& mesh_region); /** * @brief Verify each router in the noc by checking whether they satisfy the following conditions: @@ -152,7 +146,6 @@ void process_noc_tag(pugi::xml_node noc_tag, const std::vector expected_noc_children_tags = {"mesh", "topology"}; - // identifier that lets us know when we could not properly convert a string conversion value std::string attribute_conversion_failure_string; @@ -233,48 +226,43 @@ static void process_mesh_topology(pugi::xml_node mesh_topology_tag, // verify that only the acceptable attributes were supplied pugiutil::expect_only_attributes(mesh_topology_tag, expected_router_attributes, loc_data); + t_mesh_region mesh_region; + // go through the attributes and store their values - float mesh_region_start_x = pugiutil::get_attribute(mesh_topology_tag, "startx", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); - float mesh_region_end_x = pugiutil::get_attribute(mesh_topology_tag, "endx", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); - float mesh_region_start_y = pugiutil::get_attribute(mesh_topology_tag, "starty", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); - float mesh_region_end_y = pugiutil::get_attribute(mesh_topology_tag, "endy", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.start_x = pugiutil::get_attribute(mesh_topology_tag, "startx", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.end_x = pugiutil::get_attribute(mesh_topology_tag, "endx", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.start_y = pugiutil::get_attribute(mesh_topology_tag, "starty", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.end_y = pugiutil::get_attribute(mesh_topology_tag, "endy", loc_data, pugiutil::REQUIRED).as_float(ATTRIBUTE_CONVERSION_FAILURE); - int mesh_region_start_layer = pugiutil::get_attribute(mesh_topology_tag, "startlayer", loc_data, pugiutil::OPTIONAL).as_int(ATTRIBUTE_CONVERSION_FAILURE); - int mesh_region_end_layer = pugiutil::get_attribute(mesh_topology_tag, "endlayer", loc_data, pugiutil::OPTIONAL).as_int(ATTRIBUTE_CONVERSION_FAILURE); - int mesh_size = pugiutil::get_attribute(mesh_topology_tag, "size", loc_data, pugiutil::REQUIRED).as_int(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.start_layer = pugiutil::get_attribute(mesh_topology_tag, "startlayer", loc_data, pugiutil::OPTIONAL).as_int(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.end_layer = pugiutil::get_attribute(mesh_topology_tag, "endlayer", loc_data, pugiutil::OPTIONAL).as_int(ATTRIBUTE_CONVERSION_FAILURE); + mesh_region.mesh_size = pugiutil::get_attribute(mesh_topology_tag, "size", loc_data, pugiutil::REQUIRED).as_int(ATTRIBUTE_CONVERSION_FAILURE); // verify that the attributes provided were legal - if ((mesh_region_start_x < 0) || (mesh_region_end_x < 0) || (mesh_region_start_y < 0) || (mesh_region_end_y < 0) || (mesh_size < 0)) { + if (mesh_region.start_x < 0 || mesh_region.end_x < 0 || mesh_region.start_y < 0 || mesh_region.end_y < 0 || mesh_region.mesh_size < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), "The parameters for the mesh topology have to be positive values."); } - if (mesh_region_start_layer == ATTRIBUTE_CONVERSION_FAILURE || mesh_region_end_layer == ATTRIBUTE_CONVERSION_FAILURE) { + if (mesh_region.start_layer == ATTRIBUTE_CONVERSION_FAILURE || mesh_region.end_layer == ATTRIBUTE_CONVERSION_FAILURE) { VTR_LOGF_WARN(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), "Optional 'startlayer' and 'endlayer' attributes were not set for the tag. " "The default value of zero is used for both of them.\n"); - mesh_region_start_layer = 0; - mesh_region_end_layer = 0; + mesh_region.start_layer = 0; + mesh_region.end_layer = 0; } // now create the mesh topology for the noc // create routers, make connections and determine positions - generate_noc_mesh(mesh_topology_tag, loc_data, noc_ref, - mesh_region_start_x, mesh_region_end_x, - mesh_region_start_y, mesh_region_end_y, - mesh_region_start_layer, mesh_region_end_layer, - mesh_size); + generate_noc_mesh(mesh_topology_tag, loc_data, noc_ref, mesh_region); } static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, - float mesh_region_start_x, float mesh_region_end_x, - float mesh_region_start_y, float mesh_region_end_y, - int mesh_region_start_layer, int mesh_region_end_layer, - int mesh_size) { + const t_mesh_region& mesh_region) { // check that the mesh size of the router is not 0 - if (mesh_size == 0) { + if (mesh_region.mesh_size == 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), "The NoC mesh size cannot be 0."); } @@ -301,33 +289,32 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, * * THe reasoning for this is to reduce the number of calculated router positions. */ - float vertical_router_separation = (mesh_region_end_y - mesh_region_start_y) / (mesh_size - 1); - float horizontal_router_separation = (mesh_region_end_x - mesh_region_start_x) / (mesh_size - 1); + float vertical_router_separation = (mesh_region.end_y - mesh_region.start_y) / (mesh_region.mesh_size - 1); + float horizontal_router_separation = (mesh_region.end_x - mesh_region.start_x) / (mesh_region.mesh_size - 1); // improper region check - if (vertical_router_separation <= 0 || horizontal_router_separation <= 0 || - mesh_region_end_layer < mesh_region_start_layer) { + if (vertical_router_separation <= 0 || horizontal_router_separation <= 0 || mesh_region.end_layer < mesh_region.start_layer) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), "The NoC region is invalid."); } // create routers and their connections // start with router id 0 (bottom left of the chip) to the maximum router id (top right of the chip) - for (int l = mesh_region_start_layer; l <= mesh_region_end_layer; l++) { - for (int j = 0; j < mesh_size; j++) { - for (int i = 0; i < mesh_size; i++) { + for (int l = mesh_region.start_layer; l <= mesh_region.end_layer; l++) { + for (int j = 0; j < mesh_region.mesh_size; j++) { + for (int i = 0; i < mesh_region.mesh_size; i++) { t_router temp_router; // assign router id - temp_router.id = (mesh_size * mesh_size * (l - mesh_region_start_layer)) + (mesh_size * j) + i; + temp_router.id = (mesh_region.mesh_size * mesh_region.mesh_size * (l - mesh_region.start_layer)) + (mesh_region.mesh_size * j) + i; // calculate router position /* The first and last router of each column or row will be located on the mesh region boundary, * the remaining routers will be placed within the region and seperated from other routers * using the distance calculated previously. */ - temp_router.device_x_position = (i * horizontal_router_separation) + mesh_region_start_x; - temp_router.device_y_position = (j * vertical_router_separation) + mesh_region_start_y; + temp_router.device_x_position = (i * horizontal_router_separation) + mesh_region.start_x; + temp_router.device_y_position = (j * vertical_router_separation) + mesh_region.start_y; temp_router.device_layer_position = l; // assign connections @@ -339,13 +326,13 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, } // check if there is a router to the top - if (j <= mesh_size - 2) { + if (j <= mesh_region.mesh_size - 2) { // add the top router as a connection - temp_router.connection_list.push_back(temp_router.id + mesh_size); + temp_router.connection_list.push_back(temp_router.id + mesh_region.mesh_size); } // check if there is a router to the right - if (i <= mesh_size - 2) { + if (i <= mesh_region.mesh_size - 2) { // add the router located to the right temp_router.connection_list.push_back(temp_router.id + 1); } @@ -353,17 +340,17 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, // check if there is a router below if (j >= 1) { // add the bottom router as a connection - temp_router.connection_list.push_back(temp_router.id - mesh_size); + temp_router.connection_list.push_back(temp_router.id - mesh_region.mesh_size); } // check if there is a router on the layer above - if (l < mesh_region_end_layer) { - temp_router.connection_list.push_back(temp_router.id + (mesh_size * mesh_size)); + if (l < mesh_region.end_layer) { + temp_router.connection_list.push_back(temp_router.id + (mesh_region.mesh_size * mesh_region.mesh_size)); } // check if there is a router on the layer below - if (l > mesh_region_start_layer) { - temp_router.connection_list.push_back(temp_router.id - (mesh_size * mesh_size)); + if (l > mesh_region.start_layer) { + temp_router.connection_list.push_back(temp_router.id - (mesh_region.mesh_size * mesh_region.mesh_size)); } // add the router to the list @@ -377,8 +364,8 @@ static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, * Go through each router in the NoC and store the list of routers that connect to it. */ static void process_topology(pugi::xml_node topology_tag, - const pugiutil::loc_data& loc_data, - t_noc_inf* noc_ref) { + const pugiutil::loc_data& loc_data, + t_noc_inf* noc_ref) { // The topology tag should have no attributes, check that pugiutil::expect_only_attributes(topology_tag, {}, loc_data); @@ -651,8 +638,7 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag, } auto it = std::find_if(noc_ref.router_list.begin(), noc_ref.router_list.end(), [src, dst](const t_router& router) { - return router.id == src && - std::find(router.connection_list.begin(), router.connection_list.end(), dst) != router.connection_list.end(); + return router.id == src && std::find(router.connection_list.begin(), router.connection_list.end(), dst) != router.connection_list.end(); }); if (it == noc_ref.router_list.end()) { @@ -666,14 +652,14 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag, double latency = std::atof(link_latency_override); if (latency <= 0.0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag), - "The override link latency value for link (%d, %d) must be positive:%g." , + "The override link latency value for link (%d, %d) must be positive:%g.", src, dst, latency); } auto [_, success] = noc_ref.link_latency_overrides.insert({{src, dst}, latency}); if (!success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag), - "The latency for link (%d, %d) was overridden once before." , + "The latency for link (%d, %d) was overridden once before.", src, dst); } } @@ -683,14 +669,14 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag, double bandwidth = std::atof(link_latency_override); if (bandwidth <= 0.0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag), - "The override link bandwidth value for link (%d, %d) must be positive:%g." , + "The override link bandwidth value for link (%d, %d) must be positive:%g.", src, dst, bandwidth); } auto [_, success] = noc_ref.link_bandwidth_overrides.insert({{src, dst}, bandwidth}); if (!success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(override_tag), - "The bandwidth for link (%d, %d) was overridden once before." , + "The bandwidth for link (%d, %d) was overridden once before.", src, dst); } } @@ -698,4 +684,4 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag, bad_tag(override_tag, loc_data, noc_overrides_tag, {"router", "link"}); } } -} \ No newline at end of file +} diff --git a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h index 8309d8cdec9..ab5015ecc0e 100644 --- a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h +++ b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.h @@ -17,4 +17,25 @@ void process_noc_tag(pugi::xml_node noc_tag, t_arch* arch, const pugiutil::loc_data& loc_data); +/** + * @brief Describes a mesh topology as specified in the architecture file. + * It is assumed that NoC routers are equally distanced in each axis. + */ +struct t_mesh_region { + /// The location the bottom left NoC router on the X-axis. + float start_x; + /// The location the top right NoC router on the X-axis. + float end_x; + /// The location the bottom left NoC router on the Y-axis. + float start_y; + /// The location the top right NoC router on the Y-axis. + float end_y; + /// The layer from which the mesh start. + int start_layer; + /// The layer at which the mesh ends. + int end_layer; + /// The number of NoC routers in each row or column. + int mesh_size; +}; + #endif //VTR_READ_XML_ARCH_FILE_NOC_TAG_H diff --git a/libs/libarchfpga/src/vib_inf.cpp b/libs/libarchfpga/src/vib_inf.cpp index 4fcebadfebd..105720cc01f 100644 --- a/libs/libarchfpga/src/vib_inf.cpp +++ b/libs/libarchfpga/src/vib_inf.cpp @@ -43,7 +43,7 @@ void VibInf::set_switch_name(const std::string switch_name) { void VibInf::set_seg_groups(const std::vector seg_groups) { VTR_ASSERT(!seg_groups.empty()); seg_groups_.clear(); - for(auto seg_group : seg_groups) { + for (auto seg_group : seg_groups) { seg_groups_.push_back(seg_group); } } @@ -56,7 +56,7 @@ void VibInf::push_seg_group(const t_seg_group seg_group) { void VibInf::set_first_stages(const std::vector first_stages) { VTR_ASSERT(!first_stages.empty()); first_stages_.clear(); - for(auto first_stage : first_stages) { + for (auto first_stage : first_stages) { first_stages_.push_back(first_stage); } } @@ -69,7 +69,7 @@ void VibInf::push_first_stage(const t_first_stage_mux_inf first_stage) { void VibInf::set_second_stages(const std::vector second_stages) { VTR_ASSERT(!second_stages.empty()); second_stages_.clear(); - for(auto second_stage : second_stages) { + for (auto second_stage : second_stages) { second_stages_.push_back(second_stage); } } @@ -79,58 +79,58 @@ void VibInf::push_second_stage(const t_second_stage_mux_inf second_stage) { second_stages_.push_back(second_stage); } -std::string VibInf::get_name() const{ +std::string VibInf::get_name() const { VTR_ASSERT(!name_.empty()); return name_; } -std::string VibInf::get_pbtype_name() const{ +std::string VibInf::get_pbtype_name() const { VTR_ASSERT(!pbtype_name_.empty()); return pbtype_name_; } -int VibInf::get_seg_group_num() const{ +int VibInf::get_seg_group_num() const { VTR_ASSERT(seg_group_num_ >= 0); return seg_group_num_; } -int VibInf::get_switch_idx() const{ +int VibInf::get_switch_idx() const { VTR_ASSERT(switch_idx_ != -1); return switch_idx_; } -std::string VibInf::get_switch_name() const{ +std::string VibInf::get_switch_name() const { VTR_ASSERT(!switch_name_.empty()); return switch_name_; } -std::vector VibInf::get_seg_groups() const{ +std::vector VibInf::get_seg_groups() const { VTR_ASSERT(!seg_groups_.empty()); return seg_groups_; } -std::vector VibInf::get_first_stages() const{ +std::vector VibInf::get_first_stages() const { VTR_ASSERT(!first_stages_.empty()); return first_stages_; } -std::vector VibInf::get_second_stages() const{ +std::vector VibInf::get_second_stages() const { VTR_ASSERT(!second_stages_.empty()); return second_stages_; } -size_t VibInf::medium_mux_index_by_name(const std::string& name) const{ +size_t VibInf::medium_mux_index_by_name(const std::string& name) const { for (size_t i_medium = 0; i_medium < first_stages_.size(); ++i_medium) { if (name == first_stages_[i_medium].mux_name) { return i_medium; } } VTR_LOG_ERROR("No medium mux named %s!", name.c_str()); -} + return size_t(-1); +} VibDeviceGrid::VibDeviceGrid(std::string grid_name, vtr::NdMatrix vib_grid) : name_(std::move(grid_name)) , vib_grid_(std::move(vib_grid)) { - } diff --git a/libs/libarchfpga/src/vib_inf.h b/libs/libarchfpga/src/vib_inf.h index d4766fb7f88..e0232dd4c2f 100644 --- a/libs/libarchfpga/src/vib_inf.h +++ b/libs/libarchfpga/src/vib_inf.h @@ -24,8 +24,6 @@ //#include "physical_types.h" - - /* for vib tag */ enum e_parallel_axis_vib { X, @@ -34,7 +32,7 @@ enum e_parallel_axis_vib { }; struct t_seg_group { - std::string name; + std::string name; e_parallel_axis_vib axis; int seg_index; int track_num; @@ -48,7 +46,7 @@ enum e_multistage_mux_from_or_to_type { struct t_from_or_to_inf { std::string type_name; - e_multistage_mux_from_or_to_type from_type; //from_or_to_type + e_multistage_mux_from_or_to_type from_type; //from_or_to_type int type_index = -1; int phy_pin_index = -1; char seg_dir = ' '; @@ -56,14 +54,14 @@ struct t_from_or_to_inf { }; struct t_first_stage_mux_inf { - std::string mux_name; + std::string mux_name; std::vector> from_tokens; std::vector froms; }; struct t_second_stage_mux_inf : t_first_stage_mux_inf { std::vector to_tokens; - std::vector to; // for io type, port[pin] may map to several sinks + std::vector to; // for io type, port[pin] may map to several sinks }; // struct t_vib_inf { @@ -79,24 +77,24 @@ struct t_second_stage_mux_inf : t_first_stage_mux_inf { /* VibInf is used to reserve the VIB information. * * For example, a VIB is described: * * - - - - - - - L1.E0 L1.E1 - clb.O[0] L1.E2 - - - clb.I[0] MUX0 MUX1 - L1.N0 MUX0 MUX1 - - - - - Its corresponding figure is shown: - + * + * + * + * + * + * + * L1.E0 L1.E1 + * clb.O[0] L1.E2 + * + * + * clb.I[0] MUX0 MUX1 + * L1.N0 MUX0 MUX1 + * + * + * + * + * Its corresponding figure is shown: + * * | L1.N0 * +-----------------|-------+ * L1.E0-----------------|>|\ MUX-1 _| vib0|----------\ @@ -155,13 +153,12 @@ class VibInf { std::vector get_second_stages() const; size_t medium_mux_index_by_name(const std::string& name) const; - private: - std::string name_; /* vib name */ - std::string pbtype_name_; /* pbtype name of vib */ - int seg_group_num_; /* seg group number of vib */ - int switch_idx_; /* vib switch index */ - std::string switch_name_; /* vib switch name */ + std::string name_; /* vib name */ + std::string pbtype_name_; /* pbtype name of vib */ + int seg_group_num_; /* seg group number of vib */ + int switch_idx_; /* vib switch index */ + std::string switch_name_; /* vib switch name */ std::vector seg_groups_; std::vector first_stages_; std::vector second_stages_; @@ -208,7 +205,6 @@ struct t_vib_grid_loc_def { t_vib_grid_loc_spec x; //Horizontal location specification t_vib_grid_loc_spec y; //Veritcal location specification - }; struct t_vib_layer_def { @@ -253,27 +249,26 @@ class VibDeviceGrid { } const VibInf* get_vib(size_t layer, size_t x, size_t y) const { - return vib_grid_[layer][x][y]; + return vib_grid_[layer][x][y]; } size_t num_medium_nodes(size_t layer, size_t x, size_t y) const { - return vib_grid_[layer][x][y]->get_first_stages().size(); + return vib_grid_[layer][x][y]->get_first_stages().size(); } std::string medium_node_name(size_t layer, size_t x, size_t y, size_t medium_index) const { - return vib_grid_[layer][x][y]->get_first_stages()[medium_index].mux_name; + return vib_grid_[layer][x][y]->get_first_stages()[medium_index].mux_name; } std::string vib_pbtype_name(size_t layer, size_t x, size_t y) const { - return vib_grid_[layer][x][y]->get_pbtype_name(); + return vib_grid_[layer][x][y]->get_pbtype_name(); } bool is_empty() const { - return vib_grid_.empty(); + return vib_grid_.empty(); } private: - std::string name_; /** @@ -284,7 +279,6 @@ class VibDeviceGrid { * @note traditional 2-d indexing to be used */ vtr::NdMatrix vib_grid_; //This stores the grid of complex blocks. It is a 3D matrix: [0..num_layers-1][0..grid.width()-1][0..grid_height()-1] - }; #endif diff --git a/libs/libarchfpga/src/write_models_bb.cpp b/libs/libarchfpga/src/write_models_bb.cpp index 24de3938c96..a48c0b1ab9f 100644 --- a/libs/libarchfpga/src/write_models_bb.cpp +++ b/libs/libarchfpga/src/write_models_bb.cpp @@ -116,4 +116,4 @@ void DeclareModel_bb(FILE* Echo, const t_model* model) { // endmodule fprintf(Echo, "endmodule\n\n"); -} \ No newline at end of file +} diff --git a/libs/libarchfpga/test/main.cpp b/libs/libarchfpga/test/main.cpp index 2a2e12d62b2..f5c7e84bcee 100644 --- a/libs/libarchfpga/test/main.cpp +++ b/libs/libarchfpga/test/main.cpp @@ -1,2 +1,2 @@ #define CATCH_CONFIG_MAIN -#include "catch2/catch_test_macros.hpp" \ No newline at end of file +#include "catch2/catch_test_macros.hpp" diff --git a/libs/libarchfpga/test/test_read_xml_arch_file.cpp b/libs/libarchfpga/test/test_read_xml_arch_file.cpp index edc4ad2d065..e6b4b58a3f4 100644 --- a/libs/libarchfpga/test/test_read_xml_arch_file.cpp +++ b/libs/libarchfpga/test/test_read_xml_arch_file.cpp @@ -148,31 +148,32 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { t_noc_inf test_noc; // mesh parameters - float mesh_start_x = 10; - float mesh_start_y = 10; - float mesh_end_x = 5; - float mesh_end_y = 56; - float mesh_size = 0; - int mesh_start_layer = 0; - int mesh_end_layer = 0; + t_mesh_region mesh_region{ + .start_x = 10.0f, + .end_x = 5.0f, + .start_y = 10.0f, + .end_y = 56.0f, + .start_layer = 0, + .end_layer = 0, + .mesh_size = 0}; SECTION("Check the error where a mesh size was illegal.") { - REQUIRE_THROWS_WITH(generate_noc_mesh(test, test_location, &test_noc, mesh_start_x, mesh_end_x, mesh_start_y, mesh_end_y, mesh_start_layer, mesh_end_layer, mesh_size), "The NoC mesh size cannot be 0."); + REQUIRE_THROWS_WITH(generate_noc_mesh(test, test_location, &test_noc, mesh_region), "The NoC mesh size cannot be 0."); } SECTION("Check the error where a mesh region size was invalid.") { - mesh_size = 3; + mesh_region.mesh_size = 3; - REQUIRE_THROWS_WITH(generate_noc_mesh(test, test_location, &test_noc, mesh_start_x, mesh_end_x, mesh_start_y, mesh_end_y, mesh_start_layer, mesh_end_layer, mesh_size), "The NoC region is invalid."); + REQUIRE_THROWS_WITH(generate_noc_mesh(test, test_location, &test_noc, mesh_region), "The NoC region is invalid."); } SECTION("Check the mesh creation for integer precision coordinates.") { // define test parameters - mesh_size = 3; + mesh_region.mesh_size = 3; - mesh_start_x = 0; - mesh_start_y = 0; + mesh_region.start_x = 0; + mesh_region.start_y = 0; - mesh_end_x = 4; - mesh_end_y = 4; + mesh_region.end_x = 4; + mesh_region.end_y = 4; // create the golden results float golden_results_x[9]; @@ -202,10 +203,10 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { golden_results_x[8] = 4; golden_results_y[8] = 4; - generate_noc_mesh(test, test_location, &test_noc, mesh_start_x, mesh_end_x, mesh_start_y, mesh_end_y, mesh_start_layer, mesh_end_layer, mesh_size); + generate_noc_mesh(test, test_location, &test_noc, mesh_region); // go through all the expected routers - for (int expected_router_id = 0; expected_router_id < (mesh_size * mesh_size); expected_router_id++) { + for (int expected_router_id = 0; expected_router_id < (mesh_region.mesh_size * mesh_region.mesh_size); expected_router_id++) { // make sure the router ids match REQUIRE(test_noc.router_list[expected_router_id].id == expected_router_id); @@ -218,13 +219,13 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { } SECTION("Check the mesh creation for double precision coordinates.") { // define test parameters - mesh_size = 3; + mesh_region.mesh_size = 3; - mesh_start_x = 3.5; - mesh_start_y = 5.7; + mesh_region.start_x = 3.5; + mesh_region.start_y = 5.7; - mesh_end_x = 10.8; - mesh_end_y = 6.4; + mesh_region.end_x = 10.8; + mesh_region.end_y = 6.4; // create the golden results float golden_results_x[9]; @@ -254,10 +255,10 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { golden_results_x[8] = 10.8; golden_results_y[8] = 6.4; - generate_noc_mesh(test, test_location, &test_noc, mesh_start_x, mesh_end_x, mesh_start_y, mesh_end_y, mesh_start_layer, mesh_end_layer, mesh_size); + generate_noc_mesh(test, test_location, &test_noc, mesh_region); // go through all the expected routers - for (int expected_router_id = 0; expected_router_id < (mesh_size * mesh_size); expected_router_id++) { + for (int expected_router_id = 0; expected_router_id < (mesh_region.mesh_size * mesh_region.mesh_size); expected_router_id++) { // make sure the router ids match REQUIRE(test_noc.router_list[expected_router_id].id == expected_router_id); @@ -268,4 +269,4 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") { REQUIRE(vtr::isclose(golden_results_y[expected_router_id], test_noc.router_list[expected_router_id].device_y_position)); } } -} \ No newline at end of file +} diff --git a/libs/libdecrypt/test/src/test.cpp b/libs/libdecrypt/test/src/test.cpp index e88b7cc1675..bc95c971409 100644 --- a/libs/libdecrypt/test/src/test.cpp +++ b/libs/libdecrypt/test/src/test.cpp @@ -15,8 +15,12 @@ void createTestXMLFile(const std::string& filePath) { // Function to read the contents of a file into a string std::string readFileToString(const std::string& filePath) { - std::ifstream inFile(filePath); - std::string content((std::istreambuf_iterator(inFile)), std::istreambuf_iterator()); - inFile.close(); - return content; + std::ifstream inFile(filePath, std::ios::binary); + if (!inFile) { + throw std::runtime_error("Unable to open file: " + filePath); + } + + std::ostringstream ss; + ss << inFile.rdbuf(); + return ss.str(); } \ No newline at end of file diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp index 80455f0e9a5..94e8537ad35 100644 --- a/libs/libencrypt/src/encryption.cpp +++ b/libs/libencrypt/src/encryption.cpp @@ -1,3 +1,5 @@ +#include + #include "encryption.h" #ifdef SESSION_KEY_SIZE @@ -202,14 +204,19 @@ bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& file // Read file contents std::ifstream file(filePath, std::ios::binary); + std::string plaintext; if (!file) { std::cerr << "Unable to open file: " << filePath << std::endl; EVP_PKEY_free(publicKey); return false; + } else { + std::ostringstream oss; + oss << file.rdbuf(); + plaintext = oss.str(); + file.close(); } - std::string plaintext((std::istreambuf_iterator(file)), std::istreambuf_iterator()); - file.close(); + // Encrypt session key std::string encryptedSessionKey = encryptSessionKey(sessionKey, publicKey); diff --git a/libs/liblog/src/main.cpp b/libs/liblog/src/main.cpp index 65388256080..646e6c94a56 100644 --- a/libs/liblog/src/main.cpp +++ b/libs/liblog/src/main.cpp @@ -15,4 +15,4 @@ int main() { log_print_info("Test complete\n"); return 0; -} \ No newline at end of file +} diff --git a/libs/libpugiutil/src/pugixml_util.cpp b/libs/libpugiutil/src/pugixml_util.cpp index 6c5e8951cd9..ccd6dd4caec 100644 --- a/libs/libpugiutil/src/pugixml_util.cpp +++ b/libs/libpugiutil/src/pugixml_util.cpp @@ -31,7 +31,7 @@ loc_data load_xml(pugi::xml_document& doc, //Document object to be loaded w + " (line: " + std::to_string(line) + " col: " + std::to_string(col) + ")", filename.c_str(), line); } - delete (final); + delete[] final; return location_data; } else { //auto location_data = loc_data(end_result_fname); diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 2bb43da89cb..6bea36e299c 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -54,10 +54,10 @@ void check_rr_graph(const RRGraphView& rr_graph, const DeviceGrid& grid, const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, - const t_graph_type graph_type, + const e_graph_type graph_type, bool is_flat) { e_route_type route_type = DETAILED; - if (graph_type == GRAPH_GLOBAL) { + if (graph_type == e_graph_type::GLOBAL) { route_type = GLOBAL; } diff --git a/libs/librrgraph/src/base/check_rr_graph.h b/libs/librrgraph/src/base/check_rr_graph.h index 65f7d7c60d1..fc0e37fe62a 100644 --- a/libs/librrgraph/src/base/check_rr_graph.h +++ b/libs/librrgraph/src/base/check_rr_graph.h @@ -11,7 +11,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const DeviceGrid& grid, const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, - const t_graph_type graph_type, + const e_graph_type graph_type, bool is_flat); void check_rr_node(const RRGraphView& rr_graph, diff --git a/libs/librrgraph/src/base/get_parallel_segs.cpp b/libs/librrgraph/src/base/get_parallel_segs.cpp index adc3bce4f64..871a2e500fd 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.cpp +++ b/libs/librrgraph/src/base/get_parallel_segs.cpp @@ -1,7 +1,5 @@ #include "get_parallel_segs.h" -/*Gets t_segment_inf for parallel segments as defined by the user. - *Segments that have BOTH_AXIS attribute value are always included in the returned vector.*/ std::vector get_parallel_segs(const std::vector& segment_inf, t_unified_to_parallel_seg_index& seg_index_map, enum e_parallel_axis parallel_axis, diff --git a/libs/librrgraph/src/base/get_parallel_segs.h b/libs/librrgraph/src/base/get_parallel_segs.h index 70539863dda..f173b3aa15c 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.h +++ b/libs/librrgraph/src/base/get_parallel_segs.h @@ -4,6 +4,18 @@ #include "rr_graph_type.h" #include "physical_types.h" +/** + * @brief Returns segments aligned with a given axis, including BOTH_AXIS segments. + * + * Filters the unified segment list (`segment_inf`) to include only segments matching + * the specified `parallel_axis` or marked as `BOTH_AXIS`. Also populates `seg_index_map` + * to map unified indices to axis-specific ones. + * + * @param segment_inf Unified list of all segments. + * @param seg_index_map Map from unified to axis-specific segment indices. + * @param parallel_axis Axis to filter segments by. + * @return Filtered list of segments for the given axis. + */ std::vector get_parallel_segs(const std::vector& segment_inf, t_unified_to_parallel_seg_index& seg_index_map, enum e_parallel_axis parallel_axis, diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index f07e135b515..07e23cfb449 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -293,7 +293,7 @@ class RRGraphBuilder { /** @brief Reserve the lists of edges to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, - * when adding a large number of edges in order to avoid memory fragements */ + * when adding a large number of edges in order to avoid memory fragments */ inline void reserve_edges(size_t num_edges) { node_storage_.reserve_edges(num_edges); } @@ -318,6 +318,12 @@ class RRGraphBuilder { node_storage_.alloc_and_load_edges(rr_edges_to_create); } + /** @brief Overrides the associated switch for a given edge by + * updating the edge to use the passed in switch. */ + inline void override_edge_switch(RREdgeId edge_id, RRSwitchId switch_id) { + node_storage_.override_edge_switch(edge_id, switch_id); + } + /** @brief set_node_cost_index gets the index of cost data in the list of cost_indexed_data data structure * It contains the routing cost for different nodes in the RRGraph * when used in evaluate different routing paths @@ -361,7 +367,7 @@ class RRGraphBuilder { /** @brief Reserve the lists of nodes, edges, switches etc. to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, * when adding a large number of nodes/edge/switches/segments, - * in order to avoid memory fragements */ + * in order to avoid memory fragments */ inline void reserve_nodes(size_t size) { node_storage_.reserve(size); } diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index e76de6e4e83..124fd81036b 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -539,10 +539,9 @@ void t_rr_graph_storage::partition_edges(const vtr::vector& rr_switches) const { VTR_ASSERT(!node_first_edge_.empty() && remapped_edges_); diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index adc2f507483..39134554718 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -407,13 +407,27 @@ class t_rr_graph_storage { * This method should generally not be used, and instead first_edge and * last_edge should be used. */ - RREdgeId edge_id(const RRNodeId& id, t_edge_size iedge) const { + RREdgeId edge_id(RRNodeId id, t_edge_size iedge) const { RREdgeId first_edge = this->first_edge(id); RREdgeId ret(size_t(first_edge) + iedge); VTR_ASSERT_SAFE(ret < last_edge(id)); return ret; } + /** + * @brief Retrieve the RREdgeId that connects the given source and sink nodes. + * If the given source/sink nodes are not connected, RREdgeId::INVALID() is returned. + */ + RREdgeId edge_id(RRNodeId src, RRNodeId sink) const { + for (RREdgeId outgoing_edge_id : edge_range(src)) { + if (edge_sink_node(outgoing_edge_id) == sink) { + return outgoing_edge_id; + } + } + + return RREdgeId::INVALID(); + } + /** @brief Get the source node for the specified edge. */ RRNodeId edge_src_node(const RREdgeId& edge) const { VTR_ASSERT_DEBUG(edge.is_valid()); @@ -472,7 +486,7 @@ class t_rr_graph_storage { * * The following methods implement an interface that appears to be * equivalent to the interface exposed by std::vector. - * This was done for backwards compability. See t_rr_node for more details. + * This was done for backwards compatibility. See t_rr_node for more details. * * Proxy methods: * @@ -507,8 +521,8 @@ class t_rr_graph_storage { ***************************/ /** @brief - * Makes room in storage for RRNodeId in amoritized O(1) fashion. - * This results in an allocation pattern similiar to what would happen + * Makes room in storage for RRNodeId in amortized O(1) fashion. + * This results in an allocation pattern similar to what would happen * if push_back(x) / emplace_back() were used if underlying storage * was not pre-allocated. */ @@ -643,8 +657,8 @@ class t_rr_graph_storage { void set_node_direction(RRNodeId, Direction new_direction); /** @brief - * Add a side to the node abbributes - * This is the function to use when you just add a new side WITHOUT reseting side attributes + * Add a side to the node attributes + * This is the function to use when you just add a new side WITHOUT resetting side attributes */ void add_node_side(RRNodeId, e_side new_side); @@ -734,9 +748,8 @@ class t_rr_graph_storage { * * init_fan_in does not need to be invoked before this method. */ - size_t count_rr_switches( - const std::vector& arch_switch_inf, - t_arch_switch_fanin& arch_switch_fanins); + size_t count_rr_switches(const std::vector& arch_switch_inf, + t_arch_switch_fanin& arch_switch_fanins); /** @brief Maps arch_switch_inf indicies to rr_switch_inf indicies. * @@ -758,6 +771,10 @@ class t_rr_graph_storage { */ void partition_edges(const vtr::vector& rr_switches); + /** @brief Overrides the associated switch for a given edge by + * updating the edge to use the passed in switch. */ + void override_edge_switch(RREdgeId edge_id, RRSwitchId switch_id); + /** @brief Validate that edge data is partitioned correctly.*/ bool validate_node(RRNodeId node_id, const vtr::vector& rr_switches) const; bool validate(const vtr::vector& rr_switches) const; diff --git a/libs/librrgraph/src/base/rr_graph_type.h b/libs/librrgraph/src/base/rr_graph_type.h index f6c5bc7efb5..05c0cad0818 100644 --- a/libs/librrgraph/src/base/rr_graph_type.h +++ b/libs/librrgraph/src/base/rr_graph_type.h @@ -19,18 +19,32 @@ enum e_route_type { DETAILED }; -enum e_graph_type { - GRAPH_GLOBAL, /* One node per channel with wire capacity > 1 and full connectivity */ - GRAPH_BIDIR, /* Detailed bidirectional graph */ - GRAPH_UNIDIR, /* Detailed unidir graph, untilable */ - /* RESEARCH TODO: Get this option debugged */ - GRAPH_UNIDIR_TILEABLE /* Detail unidir graph with wire groups multiples of 2*L */ +/** + * @enum e_graph_type + * @brief Represents the type of routing resource graph + */ +enum class e_graph_type { + GLOBAL, ///< One node per channel with wire capacity > 1 and full connectivity + BIDIR, ///< Detailed bidirectional routing graph + UNIDIR, ///< Detailed unidirectional routing graph (non-tileable) + UNIDIR_TILEABLE ///< Tileable unidirectional graph with wire groups in multiples of 2 * L (experimental) }; -typedef enum e_graph_type t_graph_type; -/* This map is used to get indices w.r.t segment_inf_x or segment_inf_y based on parallel_axis of a segment, - * from indices w.r.t the **unified** segment vector, segment_inf in devices context which stores all segments - * regardless of their axis. (see get_parallel_segs for more details)*/ +/** + * @typedef t_unified_to_parallel_seg_index + * @brief Maps indices from the unified segment list to axis-specific segment lists. + * + * This map is used to translate indices from the unified segment vector + * (`segment_inf` in the device context, which contains all segments regardless of axis) + * to axis-specific segment vectors (`segment_inf_x` or `segment_inf_y`), based on the + * segment's parallel axis. + * + * Each entry maps a unified segment index to a pair containing: + * - The index in the corresponding axis-specific segment vector + * - The axis of the segment (X or Y) + * + * @see get_parallel_segs for more details. + */ typedef std::unordered_multimap> t_unified_to_parallel_seg_index; #endif \ No newline at end of file diff --git a/libs/librrgraph/src/base/rr_graph_utils.h b/libs/librrgraph/src/base/rr_graph_utils.h index e04fe3ef177..e3f2d3cdfb9 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.h +++ b/libs/librrgraph/src/base/rr_graph_utils.h @@ -21,7 +21,7 @@ struct t_pin_chain_node { int nxt_node_idx = OPEN; t_pin_chain_node() = default; - t_pin_chain_node(int pin_num, int nxt_idx) + t_pin_chain_node(int pin_num, int nxt_idx) noexcept : pin_physical_num(pin_num) , nxt_node_idx(nxt_idx) {} }; diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index 225af722e5b..4d2e478b220 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -41,7 +41,7 @@ std::vector RRGraphView::node_configurable_in_edges(RRNodeId node) con return ret_edges; } for (const RREdgeId& edge : node_in_edges_[node]) { - if (rr_switch_inf_[edge_switch(edge)].configurable()) { + if (rr_switch_inf_[RRSwitchId(edge_switch(edge))].configurable()) { ret_edges.push_back(edge); } } @@ -56,7 +56,7 @@ std::vector RRGraphView::node_non_configurable_in_edges(RRNodeId node) return ret_edges; } for (const RREdgeId& edge : node_in_edges_[node]) { - if (!rr_switch_inf_[edge_switch(edge)].configurable()) { + if (!rr_switch_inf_[RRSwitchId(edge_switch(edge))].configurable()) { ret_edges.push_back(edge); } } diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index f28a5883cbe..f7e6803c98c 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -425,12 +425,13 @@ class RRGraphView { return node_storage_.edge_switch(id, iedge); } - inline RRSwitchId edge_switch(RREdgeId edge) const { - return RRSwitchId(node_storage_.edge_switch(edge)); + /// @brief Returns the associated switch for a given edge. + inline short edge_switch(RREdgeId id) const { + return node_storage_.edge_switch(id); } - /** @brief Get the source node for the iedge'th edge from specified RRNodeId. - * This method should generally not be used, and instead first_edge and - * last_edge should be used.*/ + + /** @brief Return the source node for the specified edge. + */ inline RRNodeId edge_src_node(const RREdgeId edge_id) const { return node_storage_.edge_src_node(edge_id); } diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index b89244bc95d..8d318921593 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -10,6 +10,7 @@ #include #include "vtr_range.h" #include "vtr_ndmatrix.h" +#include "rr_graph_fwd.h" /** * @brief Type of a routing resource node. @@ -66,7 +67,7 @@ typedef uint16_t t_edge_size; /** * @brief An iterator that dereferences to an edge index * - * Used inconjunction with vtr::Range to return ranges of edge indices + * Used in conjunction with vtr::Range to return ranges of edge indices */ class edge_idx_iterator { public: @@ -101,7 +102,7 @@ typedef vtr::Range edge_idx_range; typedef std::vector> t_arch_switch_fanin; /* - * Reistance/Capacitance data for an RR Nodes + * Resistance/Capacitance data for an RR Nodes * * In practice many RR nodes have the same values, so they are fly-weighted * to keep t_rr_node small. Each RR node holds an rc_index which allows @@ -124,6 +125,6 @@ struct t_rr_rc_data { // This is the data type of fast lookups of an rr-node given an (rr_type, layer, x, y, and the side) //[0..num_rr_types-1][0..num_layer-1][0..grid_width-1][0..grid_height-1][0..NUM_2D_SIDES-1][0..max_ptc-1] -typedef std::array, 4>, NUM_RR_TYPES> t_rr_node_indices; +typedef std::array, 4>, NUM_RR_TYPES> t_rr_node_indices; #endif diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 6234e25552e..fb1780e72ce 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -76,7 +76,7 @@ RRNodeId RRSpatialLookup::find_node(int layer, return RRNodeId::INVALID(); } - return RRNodeId(rr_node_indices_[type][layer][node_x][node_y][node_side][ptc]); + return rr_node_indices_[type][layer][node_x][node_y][node_side][ptc]; } std::vector RRSpatialLookup::find_nodes_in_range(int layer, @@ -156,14 +156,14 @@ std::vector RRSpatialLookup::find_nodes(int layer, /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { - if (RRNodeId(node)) { + if (node.is_valid()) { num_nodes++; } } nodes.reserve(num_nodes); for (const auto& node : rr_node_indices_[type][layer][node_x][node_y][side]) { - if (RRNodeId(node)) { + if (node.is_valid()) { nodes.emplace_back(node); } } @@ -273,11 +273,11 @@ void RRSpatialLookup::add_node(RRNodeId node, if (size_t(ptc) >= rr_node_indices_[type][layer][x][y][side].size()) { /* Deposit invalid ids to newly allocated elements while original elements are untouched */ - rr_node_indices_[type][layer][x][y][side].resize(ptc + 1, int(RRNodeId::INVALID())); + rr_node_indices_[type][layer][x][y][side].resize(ptc + 1, RRNodeId::INVALID()); } /* Resize on demand finished; Register the node */ - rr_node_indices_[type][layer][x][y][side][ptc] = int(node); + rr_node_indices_[type][layer][x][y][side][ptc] = node; } bool RRSpatialLookup::remove_node(RRNodeId node, @@ -303,11 +303,11 @@ bool RRSpatialLookup::remove_node(RRNodeId node, if ((size_t)y >= rr_node_indices_[type].dim_size(2)) return false; if (side >= rr_node_indices_[type].dim_size(3)) return false; if ((size_t)ptc >= rr_node_indices_[type][layer][x][y][side].size()) return false; - if (rr_node_indices_[type][layer][x][y][side][ptc] != int(node)) return false; + if (rr_node_indices_[type][layer][x][y][side][ptc] != node) return false; // The node was in the spatial lookup; remove it. -1 corresponds to an invalid node id, // and so is treated as absent in the spatial lookup - rr_node_indices_[type][layer][x][y][side][ptc] = -1; + rr_node_indices_[type][layer][x][y][side][ptc] = RRNodeId::INVALID(); return true; } @@ -354,8 +354,8 @@ void RRSpatialLookup::reorder(const vtr::vector dest_order) for (size_t y = 0; y < grid.dim_size(2); y++) { for (size_t s = 0; s < grid.dim_size(3); s++) { for (auto &node: grid[l][x][y][s]) { - if (node != OPEN) { - node = size_t(dest_order[RRNodeId(node)]); + if (node.is_valid()) { + node = dest_order[node]; } } } diff --git a/libs/librrgraph/src/io/rr_graph_reader.cpp b/libs/librrgraph/src/io/rr_graph_reader.cpp index ec574080dba..0bcd843ae34 100644 --- a/libs/librrgraph/src/io/rr_graph_reader.cpp +++ b/libs/librrgraph/src/io/rr_graph_reader.cpp @@ -19,6 +19,8 @@ #include "rr_graph_uxsdcxx.h" #include +#include +#include #include "vtr_time.h" #include "pugixml.hpp" @@ -29,6 +31,20 @@ # include "mmap_file.h" #endif +/** + * @brief Parses a line from the RR edge delay override file. + * + * @details Expected formats: + * edge_id Tdel + * (source_node_id, sink_node_id) Tdel + * + * @param line The line to parse. + * @param rr_graph The RR graph for edge lookup using source-sink nodes. + * @return A pair containing an RR edge and the overridden Tdel (intrinsic delay). + */ +static std::pair process_rr_edge_override(const std::string& line, + const RRGraphView& rr_graph); + /************************ Subroutine definitions ****************************/ /* loads the given RR_graph file into the appropriate data structures * as specified by read_rr_graph_name. Set up correct routing data @@ -38,6 +54,7 @@ * parameters are a workaround to passing the data structures of DeviceContext. * Needs a solution to reduce the number of parameters passed in.*/ + void load_rr_file(RRGraphBuilder* rr_graph_builder, RRGraphView* rr_graph, const std::vector& physical_tile_types, @@ -46,14 +63,14 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, std::vector* rr_rc_data, const DeviceGrid& grid, const std::vector& arch_switch_inf, - const t_graph_type graph_type, + e_graph_type graph_type, const t_arch* arch, t_chan_width* chan_width, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, int* wire_to_rr_ipin_switch_between_dice, const char* read_rr_graph_name, - std::string* read_rr_graph_filename, + std::string* loaded_rr_graph_filename, bool read_edge_metadata, bool do_check_rr_graph, bool echo_enabled, @@ -74,7 +91,7 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, wire_to_rr_ipin_switch_between_dice, do_check_rr_graph, read_rr_graph_name, - read_rr_graph_filename, + loaded_rr_graph_filename, read_edge_metadata, echo_enabled, echo_file_name, @@ -115,3 +132,79 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, read_rr_graph_name); } } + +static std::pair process_rr_edge_override(const std::string& line, + const RRGraphView& rr_graph) { + std::istringstream iss(line); + char ch; + RREdgeId edge_id; + + if (std::isdigit(line[0])) { + // Line starts with an integer + int first; + iss >> first; + edge_id = (RREdgeId)first; + } else if (line[0] == '(') { + // Line starts with (first, second) + int first, second; + iss >> ch >> first >> ch >> second >> ch; + + RRNodeId src_node_id = RRNodeId(first); + RRNodeId sink_node_id = RRNodeId(second); + + edge_id = rr_graph.rr_nodes().edge_id(src_node_id, sink_node_id); + + VTR_LOGV_ERROR(!edge_id.is_valid(), + "Couldn't find an edge connecting node %d to node %d\n", + src_node_id, + sink_node_id); + + } else { + VTR_LOG_ERROR("Invalid line format: %s\n", line.c_str()); + } + + float overridden_Tdel; + if (!(iss >> overridden_Tdel)) { + VTR_LOG_ERROR("Couldn't parse the overridden delay in this line: %s\n", line.c_str()); + } + + return {edge_id, overridden_Tdel}; +} + +void load_rr_edge_delay_overrides(std::string_view filename, + RRGraphBuilder& rr_graph_builder, + const RRGraphView& rr_graph) { + std::ifstream file(filename.data()); + VTR_LOGV_ERROR(!file, "Failed to open the RR edge override file: %s\n", filename.data()); + + std::unordered_map unique_switch_info; + for (const auto& [rr_sw_idx, sw] : rr_graph.rr_switch().pairs()) { + unique_switch_info.insert({sw, rr_sw_idx}); + } + + std::string line; + + while (std::getline(file, line)) { + if (line[0] == '#') { + continue; // Ignore lines starting with '#' + } + + if (!line.empty()) { + const auto [edge_id, overridden_Tdel] = process_rr_edge_override(line, rr_graph); + RRSwitchId curr_switch_id = (RRSwitchId)rr_graph.edge_switch(edge_id); + t_rr_switch_inf switch_override_info = rr_graph.rr_switch_inf(curr_switch_id); + + switch_override_info.Tdel = overridden_Tdel; + + RRSwitchId new_switch_id; + auto it = unique_switch_info.find(switch_override_info); + if (it == unique_switch_info.end()) { + new_switch_id = rr_graph_builder.add_rr_switch(switch_override_info); + unique_switch_info.insert({switch_override_info, new_switch_id}); + } else { + new_switch_id = it->second; + } + rr_graph_builder.override_edge_switch(edge_id, new_switch_id); + } + } +} \ No newline at end of file diff --git a/libs/librrgraph/src/io/rr_graph_reader.h b/libs/librrgraph/src/io/rr_graph_reader.h index 8549b712bdf..044345ee721 100644 --- a/libs/librrgraph/src/io/rr_graph_reader.h +++ b/libs/librrgraph/src/io/rr_graph_reader.h @@ -21,18 +21,38 @@ void load_rr_file(RRGraphBuilder* rr_graph_builder, std::vector* rr_rc_data, const DeviceGrid& grid, const std::vector& arch_switch_inf, - const t_graph_type graph_type, + e_graph_type graph_type, const t_arch* arch, t_chan_width* chan_width, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, int* wire_to_rr_ipin_switch_between_dice, const char* read_rr_graph_name, - std::string* read_rr_graph_filename, + std::string* loaded_rr_graph_filename, bool read_edge_metadata, bool do_check_rr_graph, bool echo_enabled, const char* echo_file_name, bool is_flat); +/** + * @brief Reads a text file where the intrinsic delay of edges are overridden. + * + * @details This function tries to find a switch with the overridden delay. If such a + * switch exists, the edge will point to it as its corresponding switch. + * Otherwise, a new switch is created so that the edge can point to a valid switch. + * The architecture file allows the user to specify nominal switch delays, but delays + * may vary for the same switch type across the device. To represent switch delays + * more accurately, the user can specify multiple switch types in the architecture file + * and restrict each one to a region or a single location. Alternatively, the user can + * use this file to override edge delays. + * + * @param filename The text file to be ingested by this function. + * @param rr_graph_builder Used to add switches and override switch IDs for edges. + * @param rr_graph Provides read only access to RR graph. + */ +void load_rr_edge_delay_overrides(std::string_view filename, + RRGraphBuilder& rr_graph_builder, + const RRGraphView& rr_graph); + #endif /* RR_GRAPH_READER_H */ diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index cebd33c9aa0..afc5d180c3d 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -270,13 +270,13 @@ struct RrGraphContextTypes : public uxsd::DefaultRrGraphContextTypes { class RrGraphSerializer final : public uxsd::RrGraphBase { public: RrGraphSerializer( - const t_graph_type graph_type, + const e_graph_type graph_type, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, int* wire_to_rr_ipin_switch_between_dice, bool do_check_rr_graph, const char* read_rr_graph_name, - std::string* read_rr_graph_filename, + std::string* loaded_rr_graph_filename, bool read_edge_metadata, bool echo_enabled, const char* echo_file_name, @@ -303,7 +303,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { , rr_graph_(rr_graph) , rr_switch_inf_(rr_switch_inf) , rr_indexed_data_(rr_indexed_data) - , read_rr_graph_filename_(read_rr_graph_filename) + , loaded_rr_graph_filename_(loaded_rr_graph_filename) , rr_rc_data_(rr_rc_data) , graph_type_(graph_type) , base_cost_type_(base_cost_type) @@ -829,7 +829,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { auto node = (*rr_nodes_)[inode]; RRNodeId node_id = node.id(); - if (GRAPH_GLOBAL == graph_type_) { + if (e_graph_type::GLOBAL == graph_type_) { rr_graph_builder_->set_node_cost_index(node_id, RRIndexedDataId(0)); } else if (rr_graph.node_type(node.id()) == CHANX) { int seg_ind_x = find_segment_index_along_axis(segment_id, X_AXIS); @@ -1832,9 +1832,9 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { (*rr_indexed_data_)[RRIndexedDataId(i)].seg_index = seg_index_[RRIndexedDataId(i)]; } - VTR_ASSERT(read_rr_graph_filename_ != nullptr); + VTR_ASSERT(loaded_rr_graph_filename_ != nullptr); VTR_ASSERT(read_rr_graph_name_ != nullptr); - read_rr_graph_filename_->assign(read_rr_graph_name_); + loaded_rr_graph_filename_->assign(read_rr_graph_name_); if (do_check_rr_graph_) { const VibDeviceGrid vib_grid_; @@ -2182,11 +2182,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { vtr::vector* rr_switch_inf_; vtr::vector* rr_indexed_data_; t_rr_node_indices* rr_node_indices_; - std::string* read_rr_graph_filename_; + std::string* loaded_rr_graph_filename_; std::vector* rr_rc_data_; // Constant data for loads and writes. - const t_graph_type graph_type_; + const e_graph_type graph_type_; const enum e_base_cost_type base_cost_type_; const bool do_check_rr_graph_; const char* read_rr_graph_name_; diff --git a/libs/librrgraph/src/io/rr_graph_writer.cpp b/libs/librrgraph/src/io/rr_graph_writer.cpp index d254ae9edb7..291d9ffafa4 100644 --- a/libs/librrgraph/src/io/rr_graph_writer.cpp +++ b/libs/librrgraph/src/io/rr_graph_writer.cpp @@ -21,7 +21,7 @@ /************************ Subroutine definitions ****************************/ -/* This function is used to write the rr_graph into xml format into a a file with name: file_name */ +/* This function is used to write the rr_graph into xml format into a file with name: file_name */ /**FIXME: To make rr_graph_reader independent of vpr_context, the below * parameters are a workaround to passing the data structures of DeviceContext. @@ -42,7 +42,7 @@ void write_rr_graph(RRGraphBuilder* rr_graph_builder, bool is_flat) { RrGraphSerializer reader( - /*graph_type=*/t_graph_type(), + /*graph_type=*/e_graph_type(), /*base_cost_type=*/e_base_cost_type(), /*wire_to_rr_ipin_switch=*/nullptr, /*wire_to_rr_ipin_switch_between_dice=*/nullptr, diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index d94514b1637..3fd98a700aa 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -29,7 +29,7 @@ static float get_delay_normalization_fac(const vtr::vector& rr_indexed_data); -static void calculate_average_switch(const RRGraphView& rr_graph, int inode, double& avg_switch_R, double& avg_switch_T, double& avg_switch_Cinternal, int& num_switches, short& buffered, vtr::vector>& fan_in_list); +static void calculate_average_switch(const RRGraphView& rr_graph, int inode, double& avg_switch_R, double& avg_switch_T, double& avg_switch_Cinternal, int& num_switches, int& num_shorts, short& buffered, vtr::vector>& fan_in_list); static void fixup_rr_indexed_data_T_values(vtr::vector& rr_indexed_data, size_t num_segment); @@ -542,15 +542,18 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, double avg_switch_T = 0; double avg_switch_Cinternal = 0; int num_switches = 0; + int num_shorts = 0; short buffered = UNDEFINED; - calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, buffered, fan_in_list); + calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list); if (num_switches == 0) { - VTR_LOG_WARN("Node: %d with RR_type: %s at Location:%s, had no incoming switches\n", rr_id, - rr_graph.node_type_string(rr_id), node_cords.c_str()); + if (num_shorts == 0) { + VTR_LOG_WARN("Node: %d with RR_type: %s at Location:%s, had no out-going switches\n", rr_id, + rr_graph.node_type_string(rr_id), node_cords.c_str()); + } continue; - } - VTR_ASSERT(num_switches > 0); + } + VTR_ASSERT(num_switches > 0 || num_shorts > 0); num_nodes_of_index[cost_index]++; C_total[cost_index].push_back(rr_graph.node_C(rr_id)); @@ -634,20 +637,24 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, * It is not safe to assume that each node of the same wire type has the same switches with the same * delays, therefore we take their average to take into account the possible differences */ -static void calculate_average_switch(const RRGraphView& rr_graph, int inode, double& avg_switch_R, double& avg_switch_T, double& avg_switch_Cinternal, int& num_switches, short& buffered, vtr::vector>& fan_in_list) { +static void calculate_average_switch(const RRGraphView& rr_graph, int inode, double& avg_switch_R, double& avg_switch_T, double& avg_switch_Cinternal, int& num_switches, int& num_shorts, short& buffered, vtr::vector>& fan_in_list) { auto node = RRNodeId(inode); avg_switch_R = 0; avg_switch_T = 0; avg_switch_Cinternal = 0; num_switches = 0; + num_shorts = 0; buffered = UNDEFINED; for (const auto& edge : fan_in_list[node]) { /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */ if (rr_graph.node_type(node) == CHANX || rr_graph.node_type(node) == CHANY) { int switch_index = rr_graph.rr_nodes().edge_switch(edge); - if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type() == SwitchType::SHORT) continue; + if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).type() == SwitchType::SHORT) { + num_shorts++; + continue; + } avg_switch_R += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).R; avg_switch_T += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Tdel; @@ -739,6 +746,8 @@ static void print_rr_index_info(const vtr::vector #ifndef FILE_NAME -# define FILE_NAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__) +#define FILE_NAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__) #endif /* Enable Debug Messages for libRTLNumber: Un-Comment to Enable Debug Messages: @@ -24,22 +24,22 @@ // #define ENABLE_DEBUG_MESSAGES #ifdef ENABLE_DEBUG_MESSAGES -# define DEBUG_MSG(debugMsg) std::cerr << "DEBUG: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ - << ": " << debugMsg << std::endl +#define DEBUG_MSG(debugMsg) std::cerr << "DEBUG: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ + << ": " << debugMsg << std::endl #else -# define DEBUG_MSG(debugMsg) /* No-Op */ +#define DEBUG_MSG(debugMsg) /* No-Op */ #endif #ifndef WARN_MSG -# define WARN_MSG(warnMSG) std::cerr << "WARNING: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ - << ": " << warnMSG << "!" << std::endl +#define WARN_MSG(warnMSG) std::cerr << "WARNING: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ + << ": " << warnMSG << "!" << std::endl #endif #ifndef ERR_MSG -# define ERR_MSG(errMsg) std::cerr << std::endl \ - << "ERROR: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ - << ": " << errMsg << "!" << std::endl \ - << std::endl +#define ERR_MSG(errMsg) std::cerr << std::endl \ + << "ERROR: " << FILE_NAME << ":" << __LINE__ << " " << __func__ << "()" \ + << ": " << errMsg << "!" << std::endl \ + << std::endl #endif std::string string_of_radix_to_bitstring(std::string orig_string, size_t radix); diff --git a/libs/libvtrutil/src/specrand.cpp b/libs/libvtrutil/src/specrand.cpp index a508eb31ce3..881802b8227 100644 --- a/libs/libvtrutil/src/specrand.cpp +++ b/libs/libvtrutil/src/specrand.cpp @@ -112,7 +112,7 @@ unsigned long SpecRandomNumberGenerator::spec_genrand_int32_() { if (mti >= N) { /* generate N words at one time */ - if (mti == N + 1) /* if init_genrand() has not been called, */ + if (mti == N + 1) /* if init_genrand() has not been called, */ spec_init_genrand_(5489UL); /* a default initial seed is used */ for (size_t kk = 0; kk < N - M; kk++) { diff --git a/libs/libvtrutil/src/specrand.h b/libs/libvtrutil/src/specrand.h index 9a7634e678c..6216a3a341a 100644 --- a/libs/libvtrutil/src/specrand.h +++ b/libs/libvtrutil/src/specrand.h @@ -114,7 +114,6 @@ class SpecRandomNumberGenerator : public vtr::RandomNumberGeneratorInterface { size_t mti = N + 1; /// the array for the state vector unsigned long mt[N]; - }; #endif diff --git a/libs/libvtrutil/src/tl_optional.hpp b/libs/libvtrutil/src/tl_optional.hpp index 294755b69a1..3d5f037c559 100644 --- a/libs/libvtrutil/src/tl_optional.hpp +++ b/libs/libvtrutil/src/tl_optional.hpp @@ -32,78 +32,78 @@ #include #if (defined(_MSC_VER) && _MSC_VER == 1900) -# define TL_OPTIONAL_MSVC2015 +#define TL_OPTIONAL_MSVC2015 #endif #if (defined(__GNUC__) && __GNUC__ == 4 && __GNUC_MINOR__ <= 9 && !defined(__clang__)) -# define TL_OPTIONAL_GCC49 +#define TL_OPTIONAL_GCC49 #endif #if (defined(__GNUC__) && __GNUC__ == 5 && __GNUC_MINOR__ <= 4 && !defined(__clang__)) -# define TL_OPTIONAL_GCC54 +#define TL_OPTIONAL_GCC54 #endif #if (defined(__GNUC__) && __GNUC__ == 5 && __GNUC_MINOR__ <= 5 && !defined(__clang__)) -# define TL_OPTIONAL_GCC55 +#define TL_OPTIONAL_GCC55 #endif #if (defined(__GNUC__) && __GNUC__ == 4 && __GNUC_MINOR__ <= 9 && !defined(__clang__)) // GCC < 5 doesn't support overloading on const&& for member functions -# define TL_OPTIONAL_NO_CONSTRR +#define TL_OPTIONAL_NO_CONSTRR // GCC < 5 doesn't support some standard C++11 type traits -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ - std::has_trivial_copy_constructor::value -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) std::has_trivial_copy_assign::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ + std::has_trivial_copy_constructor::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) std::has_trivial_copy_assign::value // This one will be different for GCC 5.7 if it's ever supported -# define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value // GCC 5 < v < 8 has a bug in is_trivially_copy_constructible which breaks std::vector // for non-copyable types #elif (defined(__GNUC__) && __GNUC__ < 8 && !defined(__clang__)) -# ifndef TL_GCC_LESS_8_TRIVIALLY_COPY_CONSTRUCTIBLE_MUTEX -# define TL_GCC_LESS_8_TRIVIALLY_COPY_CONSTRUCTIBLE_MUTEX +#ifndef TL_GCC_LESS_8_TRIVIALLY_COPY_CONSTRUCTIBLE_MUTEX +#define TL_GCC_LESS_8_TRIVIALLY_COPY_CONSTRUCTIBLE_MUTEX namespace tl { namespace detail { template struct is_trivially_copy_constructible : std::is_trivially_copy_constructible {}; -# ifdef _GLIBCXX_VECTOR +#ifdef _GLIBCXX_VECTOR template struct is_trivially_copy_constructible> : std::is_trivially_copy_constructible {}; -# endif +#endif } // namespace detail } // namespace tl -# endif +#endif -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ - tl::detail::is_trivially_copy_constructible::value -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) \ - std::is_trivially_copy_assignable::value -# define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ + tl::detail::is_trivially_copy_constructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) \ + std::is_trivially_copy_assignable::value +#define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value #else -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ - std::is_trivially_copy_constructible::value -# define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) \ - std::is_trivially_copy_assignable::value -# define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_CONSTRUCTIBLE(T) \ + std::is_trivially_copy_constructible::value +#define TL_OPTIONAL_IS_TRIVIALLY_COPY_ASSIGNABLE(T) \ + std::is_trivially_copy_assignable::value +#define TL_OPTIONAL_IS_TRIVIALLY_DESTRUCTIBLE(T) std::is_trivially_destructible::value #endif #if __cplusplus > 201103L -# define TL_OPTIONAL_CXX14 +#define TL_OPTIONAL_CXX14 #endif // constexpr implies const in C++11, not C++14 #if (__cplusplus == 201103L || defined(TL_OPTIONAL_MSVC2015) || defined(TL_OPTIONAL_GCC49)) -# define TL_OPTIONAL_11_CONSTEXPR +#define TL_OPTIONAL_11_CONSTEXPR #else -# define TL_OPTIONAL_11_CONSTEXPR constexpr +#define TL_OPTIONAL_11_CONSTEXPR constexpr #endif namespace tl { #ifndef TL_MONOSTATE_INPLACE_MUTEX -# define TL_MONOSTATE_INPLACE_MUTEX +#define TL_MONOSTATE_INPLACE_MUTEX /// Used to represent an optional with no data; essentially a bool class monostate {}; @@ -120,7 +120,7 @@ class optional; namespace detail { #ifndef TL_TRAITS_MUTEX -# define TL_TRAITS_MUTEX +#define TL_TRAITS_MUTEX // C++14-style aliases for brevity template using remove_const_t = typename std::remove_const::type; @@ -142,14 +142,14 @@ template struct conjunction : std::conditional, B>::type {}; -# if defined(_LIBCPP_VERSION) && __cplusplus == 201103L -# define TL_TRAITS_LIBCXX_MEM_FN_WORKAROUND -# endif +#if defined(_LIBCPP_VERSION) && __cplusplus == 201103L +#define TL_TRAITS_LIBCXX_MEM_FN_WORKAROUND +#endif // In C++11 mode, there's an issue in libc++'s std::mem_fn // which results in a hard-error when using it in a noexcept expression // in some cases. This is a check to workaround the common failing case. -# ifdef TL_TRAITS_LIBCXX_MEM_FN_WORKAROUND +#ifdef TL_TRAITS_LIBCXX_MEM_FN_WORKAROUND template struct is_pointer_to_non_const_member_func : std::false_type {}; template @@ -171,14 +171,14 @@ template struct is_const_or_const_ref : std::true_type {}; template struct is_const_or_const_ref : std::true_type {}; -# endif +#endif // std::invoke from C++17 // https://stackoverflow.com/questions/38288042/c11-14-invoke-workaround template::value && is_const_or_const_ref::value)>, -# endif +#endif typename = enable_if_t>::value>, int = 0> constexpr auto invoke(Fn&& f, Args&&... args) noexcept( @@ -212,14 +212,14 @@ using invoke_result = invoke_result_impl; template using invoke_result_t = typename invoke_result::type; -# if defined(_MSC_VER) && _MSC_VER <= 1900 +#if defined(_MSC_VER) && _MSC_VER <= 1900 // TODO make a version which works with MSVC 2015 template struct is_swappable : std::true_type {}; template struct is_nothrow_swappable : std::true_type {}; -# else +#else // https://stackoverflow.com/questions/26744589/what-is-a-proper-way-to-implement-is-swappable-to-test-for-the-swappable-concept namespace swap_adl_tests { // if swap ADL finds this then it would call std::swap otherwise (same @@ -276,12 +276,14 @@ struct is_nothrow_swappable bool, is_swappable::value && ((decltype(detail::swap_adl_tests::uses_std(0))::value && detail::swap_adl_tests::is_std_swap_noexcept::value) || (!decltype(detail::swap_adl_tests::uses_std(0))::value && detail::swap_adl_tests::is_adl_swap_noexcept::value))> { }; -# endif +#endif #endif // std::void_t from C++17 template -struct voider { using type = void; }; +struct voider { + using type = void; +}; template using void_t = typename voider::type; @@ -505,8 +507,7 @@ struct optional_copy_assign_base : optional_move_base { return *this; } optional_copy_assign_base& - operator=(optional_copy_assign_base&& rhs) - = default; + operator=(optional_copy_assign_base&& rhs) = default; }; // This class manages conditionally having a trivial move assignment operator @@ -515,7 +516,7 @@ struct optional_copy_assign_base : optional_move_base { // to make do with a non-trivial move assignment operator even if T is trivially // move assignable #ifndef TL_OPTIONAL_GCC49 -template::value&& std::is_trivially_move_constructible::value&& std::is_trivially_move_assignable::value> +template::value && std::is_trivially_move_constructible::value && std::is_trivially_move_assignable::value> struct optional_move_assign_base : optional_copy_assign_base { using optional_copy_assign_base::optional_copy_assign_base; }; @@ -534,12 +535,11 @@ struct optional_move_assign_base : optional_copy_assign_base { optional_move_assign_base(optional_move_assign_base&& rhs) = default; optional_move_assign_base& - operator=(const optional_move_assign_base& rhs) - = default; + operator=(const optional_move_assign_base& rhs) = default; optional_move_assign_base& operator=(optional_move_assign_base&& rhs) noexcept( - std::is_nothrow_move_constructible::value&& std::is_nothrow_move_assignable::value) { + std::is_nothrow_move_constructible::value && std::is_nothrow_move_assignable::value) { this->assign(std::move(rhs)); return *this; } @@ -553,8 +553,7 @@ struct optional_delete_ctor_base { optional_delete_ctor_base(const optional_delete_ctor_base&) = default; optional_delete_ctor_base(optional_delete_ctor_base&&) noexcept = default; optional_delete_ctor_base& - operator=(const optional_delete_ctor_base&) - = default; + operator=(const optional_delete_ctor_base&) = default; optional_delete_ctor_base& operator=(optional_delete_ctor_base&&) noexcept = default; }; @@ -565,8 +564,7 @@ struct optional_delete_ctor_base { optional_delete_ctor_base(const optional_delete_ctor_base&) = default; optional_delete_ctor_base(optional_delete_ctor_base&&) noexcept = delete; optional_delete_ctor_base& - operator=(const optional_delete_ctor_base&) - = default; + operator=(const optional_delete_ctor_base&) = default; optional_delete_ctor_base& operator=(optional_delete_ctor_base&&) noexcept = default; }; @@ -577,8 +575,7 @@ struct optional_delete_ctor_base { optional_delete_ctor_base(const optional_delete_ctor_base&) = delete; optional_delete_ctor_base(optional_delete_ctor_base&&) noexcept = default; optional_delete_ctor_base& - operator=(const optional_delete_ctor_base&) - = default; + operator=(const optional_delete_ctor_base&) = default; optional_delete_ctor_base& operator=(optional_delete_ctor_base&&) noexcept = default; }; @@ -589,8 +586,7 @@ struct optional_delete_ctor_base { optional_delete_ctor_base(const optional_delete_ctor_base&) = delete; optional_delete_ctor_base(optional_delete_ctor_base&&) noexcept = delete; optional_delete_ctor_base& - operator=(const optional_delete_ctor_base&) - = default; + operator=(const optional_delete_ctor_base&) = default; optional_delete_ctor_base& operator=(optional_delete_ctor_base&&) noexcept = default; }; @@ -605,8 +601,7 @@ struct optional_delete_assign_base { optional_delete_assign_base(const optional_delete_assign_base&) = default; optional_delete_assign_base(optional_delete_assign_base&&) noexcept = default; optional_delete_assign_base& - operator=(const optional_delete_assign_base&) - = default; + operator=(const optional_delete_assign_base&) = default; optional_delete_assign_base& operator=(optional_delete_assign_base&&) noexcept = default; }; @@ -617,8 +612,7 @@ struct optional_delete_assign_base { optional_delete_assign_base(const optional_delete_assign_base&) = default; optional_delete_assign_base(optional_delete_assign_base&&) noexcept = default; optional_delete_assign_base& - operator=(const optional_delete_assign_base&) - = default; + operator=(const optional_delete_assign_base&) = default; optional_delete_assign_base& operator=(optional_delete_assign_base&&) noexcept = delete; }; @@ -629,8 +623,7 @@ struct optional_delete_assign_base { optional_delete_assign_base(const optional_delete_assign_base&) = default; optional_delete_assign_base(optional_delete_assign_base&&) noexcept = default; optional_delete_assign_base& - operator=(const optional_delete_assign_base&) - = delete; + operator=(const optional_delete_assign_base&) = delete; optional_delete_assign_base& operator=(optional_delete_assign_base&&) noexcept = default; }; @@ -641,8 +634,7 @@ struct optional_delete_assign_base { optional_delete_assign_base(const optional_delete_assign_base&) = default; optional_delete_assign_base(optional_delete_assign_base&&) noexcept = default; optional_delete_assign_base& - operator=(const optional_delete_assign_base&) - = delete; + operator=(const optional_delete_assign_base&) = delete; optional_delete_assign_base& operator=(optional_delete_assign_base&&) noexcept = delete; }; @@ -719,7 +711,7 @@ class optional : private detail::optional_move_assign_base, : result(nullopt); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr auto and_then(F&& f) const&& { using result = detail::invoke_result_t; @@ -729,7 +721,7 @@ class optional : private detail::optional_move_assign_base, return has_value() ? detail::invoke(std::forward(f), std::move(**this)) : result(nullopt); } -# endif +#endif #else /// Carries out some operation which returns an optional on the stored /// object if there is one. @@ -763,7 +755,7 @@ class optional : private detail::optional_move_assign_base, : result(nullopt); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr detail::invoke_result_t and_then(F&& f) const&& { using result = detail::invoke_result_t; @@ -773,7 +765,7 @@ class optional : private detail::optional_move_assign_base, return has_value() ? detail::invoke(std::forward(f), std::move(**this)) : result(nullopt); } -# endif +#endif #endif #if defined(TL_OPTIONAL_CXX14) && !defined(TL_OPTIONAL_GCC49) && !defined(TL_OPTIONAL_GCC54) && !defined(TL_OPTIONAL_GCC55) @@ -820,14 +812,14 @@ class optional : private detail::optional_move_assign_base, return optional_map_impl(*this, std::forward(f)); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr decltype(optional_map_impl(std::declval(), std::declval())) map(F&& f) const&& { return optional_map_impl(std::move(*this), std::forward(f)); } -# endif +#endif #endif #if defined(TL_OPTIONAL_CXX14) && !defined(TL_OPTIONAL_GCC49) && !defined(TL_OPTIONAL_GCC54) && !defined(TL_OPTIONAL_GCC55) @@ -874,14 +866,14 @@ class optional : private detail::optional_move_assign_base, return optional_map_impl(*this, std::forward(f)); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr decltype(optional_map_impl(std::declval(), std::declval())) transform(F&& f) const&& { return optional_map_impl(std::move(*this), std::forward(f)); } -# endif +#endif #endif /// Calls `f` if the optional is empty @@ -1251,7 +1243,7 @@ class optional : private detail::optional_move_assign_base, /// If one has a value, it is moved to the other and the movee is left /// valueless. void - swap(optional& rhs) noexcept(std::is_nothrow_move_constructible::value&& detail::is_nothrow_swappable::value) { + swap(optional& rhs) noexcept(std::is_nothrow_move_constructible::value && detail::is_nothrow_swappable::value) { using std::swap; if (has_value()) { if (rhs.has_value()) { @@ -1593,7 +1585,7 @@ class optional { : result(nullopt); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr auto and_then(F&& f) const&& { using result = detail::invoke_result_t; @@ -1603,7 +1595,7 @@ class optional { return has_value() ? detail::invoke(std::forward(f), **this) : result(nullopt); } -# endif +#endif #else /// Carries out some operation which returns an optional on the stored /// object if there is one. @@ -1637,7 +1629,7 @@ class optional { : result(nullopt); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr detail::invoke_result_t and_then(F&& f) const&& { using result = detail::invoke_result_t; @@ -1647,7 +1639,7 @@ class optional { return has_value() ? detail::invoke(std::forward(f), **this) : result(nullopt); } -# endif +#endif #endif #if defined(TL_OPTIONAL_CXX14) && !defined(TL_OPTIONAL_GCC49) && !defined(TL_OPTIONAL_GCC54) && !defined(TL_OPTIONAL_GCC55) @@ -1694,14 +1686,14 @@ class optional { return detail::optional_map_impl(*this, std::forward(f)); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr decltype(detail::optional_map_impl(std::declval(), std::declval())) map(F&& f) const&& { return detail::optional_map_impl(std::move(*this), std::forward(f)); } -# endif +#endif #endif #if defined(TL_OPTIONAL_CXX14) && !defined(TL_OPTIONAL_GCC49) && !defined(TL_OPTIONAL_GCC54) && !defined(TL_OPTIONAL_GCC55) @@ -1750,14 +1742,14 @@ class optional { return detail::optional_map_impl(*this, std::forward(f)); } -# ifndef TL_OPTIONAL_NO_CONSTRR +#ifndef TL_OPTIONAL_NO_CONSTRR template constexpr decltype(detail::optional_map_impl(std::declval(), std::declval())) transform(F&& f) const&& { return detail::optional_map_impl(std::move(*this), std::forward(f)); } -# endif +#endif #endif /// Calls `f` if the optional is empty diff --git a/libs/libvtrutil/src/vpr_error.h b/libs/libvtrutil/src/vpr_error.h index 16ba3891b12..19813253625 100644 --- a/libs/libvtrutil/src/vpr_error.h +++ b/libs/libvtrutil/src/vpr_error.h @@ -78,12 +78,12 @@ void vpr_throw_opt(enum e_vpr_error type, const char* psz_func_pretty_name, cons // information, so we prefer to use it if possible #define VPR_THROW_FUNCTION __func__ #ifdef __GNUC__ -# ifdef __GNUC_MINOR__ -# if __GNUC__ >= 2 && __GNUC_MINOR__ > 6 -# undef VPR_THROW_FUNCTION -# define VPR_THROW_FUNCTION __PRETTY_FUNCTION__ -# endif -# endif +#ifdef __GNUC_MINOR__ +#if __GNUC__ >= 2 && __GNUC_MINOR__ > 6 +#undef VPR_THROW_FUNCTION +#define VPR_THROW_FUNCTION __PRETTY_FUNCTION__ +#endif +#endif #endif /* diff --git a/libs/libvtrutil/src/vtr_assert.h b/libs/libvtrutil/src/vtr_assert.h index ba63a4bb573..e17448a0c89 100644 --- a/libs/libvtrutil/src/vtr_assert.h +++ b/libs/libvtrutil/src/vtr_assert.h @@ -29,57 +29,57 @@ // Set a default assertion level if none is specified #ifndef VTR_ASSERT_LEVEL -# define VTR_ASSERT_LEVEL 2 +#define VTR_ASSERT_LEVEL 2 #endif // Enable the assertions based on the specified level #if VTR_ASSERT_LEVEL >= 4 -# define VTR_ASSERT_DEBUG_ENABLED +#define VTR_ASSERT_DEBUG_ENABLED #endif #if VTR_ASSERT_LEVEL >= 3 -# define VTR_ASSERT_SAFE_ENABLED +#define VTR_ASSERT_SAFE_ENABLED #endif #if VTR_ASSERT_LEVEL >= 2 -# define VTR_ASSERT_ENABLED +#define VTR_ASSERT_ENABLED #endif #if VTR_ASSERT_LEVEL >= 1 -# define VTR_ASSERT_OPT_ENABLED +#define VTR_ASSERT_OPT_ENABLED #endif // Define the user assertion macros #ifdef VTR_ASSERT_DEBUG_ENABLED -# define VTR_ASSERT_DEBUG(expr) VTR_ASSERT_IMPL(expr, nullptr) -# define VTR_ASSERT_DEBUG_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) +#define VTR_ASSERT_DEBUG(expr) VTR_ASSERT_IMPL(expr, nullptr) +#define VTR_ASSERT_DEBUG_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) #else -# define VTR_ASSERT_DEBUG(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) -# define VTR_ASSERT_DEBUG_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) +#define VTR_ASSERT_DEBUG(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) +#define VTR_ASSERT_DEBUG_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) #endif #ifdef VTR_ASSERT_SAFE_ENABLED -# define VTR_ASSERT_SAFE(expr) VTR_ASSERT_IMPL(expr, nullptr) -# define VTR_ASSERT_SAFE_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) +#define VTR_ASSERT_SAFE(expr) VTR_ASSERT_IMPL(expr, nullptr) +#define VTR_ASSERT_SAFE_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) #else -# define VTR_ASSERT_SAFE(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) -# define VTR_ASSERT_SAFE_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) +#define VTR_ASSERT_SAFE(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) +#define VTR_ASSERT_SAFE_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) #endif #ifdef VTR_ASSERT_ENABLED -# define VTR_ASSERT(expr) VTR_ASSERT_IMPL(expr, nullptr) -# define VTR_ASSERT_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) +#define VTR_ASSERT(expr) VTR_ASSERT_IMPL(expr, nullptr) +#define VTR_ASSERT_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) #else -# define VTR_ASSERT(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) -# define VTR_ASSERT_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) +#define VTR_ASSERT(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) +#define VTR_ASSERT_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) #endif #ifdef VTR_ASSERT_OPT_ENABLED -# define VTR_ASSERT_OPT(expr) VTR_ASSERT_IMPL(expr, nullptr) -# define VTR_ASSERT_OPT_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) +#define VTR_ASSERT_OPT(expr) VTR_ASSERT_IMPL(expr, nullptr) +#define VTR_ASSERT_OPT_MSG(expr, msg) VTR_ASSERT_IMPL(expr, msg) #else -# define VTR_ASSERT_OPT(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) -# define VTR_ASSERT_OPT_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) +#define VTR_ASSERT_OPT(expr) VTR_ASSERT_IMPL_NOP(expr, nullptr) +#define VTR_ASSERT_OPT_MSG(expr, msg) VTR_ASSERT_IMPL_NOP(expr, msg) #endif /** @@ -124,12 +124,12 @@ */ #define VTR_ASSERT_FUNCTION __func__ #ifdef __GNUC__ -# ifdef __GNUC_MINOR__ -# if __GNUC__ >= 2 && __GNUC_MINOR__ > 6 -# undef VTR_ASSERT_FUNCTION -# define VTR_ASSERT_FUNCTION __PRETTY_FUNCTION__ -# endif -# endif +#ifdef __GNUC_MINOR__ +#if __GNUC__ >= 2 && __GNUC_MINOR__ > 6 +#undef VTR_ASSERT_FUNCTION +#define VTR_ASSERT_FUNCTION __PRETTY_FUNCTION__ +#endif +#endif #endif namespace vtr { diff --git a/libs/libvtrutil/src/vtr_flat_map.h b/libs/libvtrutil/src/vtr_flat_map.h index 2c0b34f8536..bc857159bdb 100644 --- a/libs/libvtrutil/src/vtr_flat_map.h +++ b/libs/libvtrutil/src/vtr_flat_map.h @@ -21,7 +21,7 @@ class flat_map2; * @brief A function to create a flat map * * Helper function to create a flat map from a vector of pairs - * without haveing to explicity specify the key and value types + * without having to explicitly specify the key and value types */ template flat_map make_flat_map(std::vector>&& vec) { @@ -435,7 +435,7 @@ template class flat_map2 : public flat_map { public: ///@brief Constructor - flat_map2() {} + flat_map2() noexcept {} explicit flat_map2(std::vector::value_type>&& values) : flat_map(std::move(values)) {} diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 7cc17c7d74c..d459653b0a1 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -122,7 +122,7 @@ template class Rect { public: //Constructors ///@brief default constructor - Rect(); + Rect() noexcept; ///@brief construct using 4 vertex Rect(T left_val, T bottom_val, T right_val, T top_val); @@ -183,6 +183,9 @@ class Rect { ///@brief Returns true if other is contained within the rectangle (including all edges) bool contains(const Rect& other) const; + ///@brief Returns true if other strictly overlaps this rectangle (two rectangles that only share an edge do not overlap) + bool strictly_overlaps(const Rect& other) const; + /** * @brief Checks whether the rectangle is empty * diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 6485f8337cf..6cc932ae4a9 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -91,7 +91,7 @@ Point& Point::operator-=(const Point& rhs) { * Rect */ template -Rect::Rect() +Rect::Rect() noexcept : Rect(Point(0, 0), Point(0, 0)) { //pass } @@ -192,6 +192,12 @@ bool Rect::contains(const Rect& other) const { && other.ymin() >= ymin() && other.ymax() <= ymax(); } +template +bool Rect::strictly_overlaps(const Rect& other) const { + return xmin() < other.xmax() && xmax() > other.xmin() + && ymax() > other.ymin() && ymin() < other.ymax(); +} + template bool Rect::empty() const { return xmax() <= xmin() || ymax() <= ymin(); diff --git a/libs/libvtrutil/src/vtr_log.h b/libs/libvtrutil/src/vtr_log.h index 3c52e249d9d..d9b340d1214 100644 --- a/libs/libvtrutil/src/vtr_log.h +++ b/libs/libvtrutil/src/vtr_log.h @@ -13,8 +13,10 @@ * * Three types of log message types are defined: * - VTR_LOG : The standard 'info' type log message - * - VTR_LOG_WARN : A warning log message. This represents unusual condition that may indicate an issue but executiom continues - * - VTR_LOG_ERROR : An error log message. This represents a clear issue that should result in stopping the program execution. Please note that using this log message will not actually terminate the program. So a VtrError should be thrown after all the neccessary VTR_LOG_ERROR messages are printed. + * - VTR_LOG_WARN : A warning log message. This represents an unusual condition that may indicate an issue but execution continues + * - VTR_LOG_ERROR : An error log message. This represents a clear issue that should result in stopping the program execution. + * Please note that using this log message will not actually terminate the program. So a VtrError should be thrown + * after all the necessary VTR_LOG_ERROR messages are printed. * * For example: * @@ -27,7 +29,7 @@ * * Each of the three message types also have a VTR_LOGV_* variant, * which will cause the message to be logged if a user-defined condition - * is satisifed. + * is satisfied. * * For example: * @@ -118,11 +120,11 @@ // Debug logging macros #ifdef VTR_ENABLE_DEBUG_LOGGING //Enable -# define VTR_LOG_DEBUG(...) VTR_LOG(__VA_ARGS__) -# define VTR_LOGV_DEBUG(expr, ...) VTR_LOGV(expr, __VA_ARGS__) +#define VTR_LOG_DEBUG(...) VTR_LOG(__VA_ARGS__) +#define VTR_LOGV_DEBUG(expr, ...) VTR_LOGV(expr, __VA_ARGS__) #else //Disable -# define VTR_LOG_DEBUG(...) VTR_LOG_NOP(__VA_ARGS__) -# define VTR_LOGV_DEBUG(expr, ...) VTR_LOGV_NOP(expr, __VA_ARGS__) +#define VTR_LOG_DEBUG(...) VTR_LOG_NOP(__VA_ARGS__) +#define VTR_LOGV_DEBUG(expr, ...) VTR_LOGV_NOP(expr, __VA_ARGS__) #endif namespace vtr { diff --git a/libs/libvtrutil/src/vtr_logic.h b/libs/libvtrutil/src/vtr_logic.h index b43ee49291e..21b08fea22b 100644 --- a/libs/libvtrutil/src/vtr_logic.h +++ b/libs/libvtrutil/src/vtr_logic.h @@ -4,12 +4,12 @@ #define VTR_LOGIC_H #ifdef FALSE -# undef FALSE +#undef FALSE #endif #define FALSE FALSE #ifdef TRUE -# undef TRUE +#undef TRUE #endif #define TRUE TRUE diff --git a/libs/libvtrutil/src/vtr_memory.cpp b/libs/libvtrutil/src/vtr_memory.cpp index 39d6b244b13..4bea9f1c652 100644 --- a/libs/libvtrutil/src/vtr_memory.cpp +++ b/libs/libvtrutil/src/vtr_memory.cpp @@ -10,9 +10,9 @@ #include "vtr_log.h" #ifndef __GLIBC__ -# include +#include #else -# include +#include #endif namespace vtr { @@ -164,7 +164,7 @@ void free_chunk_memory(t_chunk* chunk_info) { while (curr_ptr != nullptr) { /* Must cast pointers to type char*, since the're of type void*, which delete can't * be called on.*/ - delete[]((char*)curr_ptr->data_vptr); /* Free memory "chunk". */ + delete[] ((char*)curr_ptr->data_vptr); /* Free memory "chunk". */ prev_ptr = curr_ptr; curr_ptr = curr_ptr->next; delete (t_linked_vptr*)prev_ptr; /* Free memory used to track "chunk". */ diff --git a/libs/libvtrutil/src/vtr_memory.h b/libs/libvtrutil/src/vtr_memory.h index 72e92ebe8f8..4c9877ec2cc 100644 --- a/libs/libvtrutil/src/vtr_memory.h +++ b/libs/libvtrutil/src/vtr_memory.h @@ -5,8 +5,8 @@ #include #ifdef _WIN32 -# include -# include +#include +#include #endif namespace vtr { diff --git a/libs/libvtrutil/src/vtr_ndmatrix.h b/libs/libvtrutil/src/vtr_ndmatrix.h index b7d6f030d5d..a9a41ff41b4 100644 --- a/libs/libvtrutil/src/vtr_ndmatrix.h +++ b/libs/libvtrutil/src/vtr_ndmatrix.h @@ -387,10 +387,10 @@ class NdMatrix : public NdMatrixBase { // Peel off the first dimension return NdMatrixProxy( - this->dim_sizes_.data() + 1, //Pass the dimension information - this->dim_strides_.data() + 1, //Pass the stride for the next dimension - this->dim_strides_[0] * index, //Advance to index in this dimension - this->data_); //Pass the base pointer + this->dim_sizes_.data() + 1, //Pass the dimension information + this->dim_strides_.data() + 1, //Pass the stride for the next dimension + this->dim_strides_[0] * index, //Advance to index in this dimension + this->data_); //Pass the base pointer } /** @@ -438,4 +438,3 @@ using Matrix = NdMatrix; } // namespace vtr #endif - diff --git a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h index f85ebc72008..0e1001239bc 100644 --- a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h +++ b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h @@ -63,7 +63,7 @@ class NdOffsetMatrixProxy { * dim_stride: The stride of this dimension (i.e. how many element in memory between indicies of this dimension) * start: Pointer to the start of the sub-matrix this proxy represents */ - NdOffsetMatrixProxy(const DimRange* dim_ranges, size_t idim, size_t dim_stride, T* start) + NdOffsetMatrixProxy(const DimRange* dim_ranges, size_t idim, size_t dim_stride, T* start) : dim_ranges_(dim_ranges) , idim_(idim) , dim_stride_(dim_stride) @@ -116,7 +116,7 @@ class NdOffsetMatrixProxy { * - dim_stride: The stride of this dimension (i.e. how many element in memory between indicies of this dimension) * - start: Pointer to the start of the sub-matrix this proxy represents */ - NdOffsetMatrixProxy(const DimRange* dim_ranges, size_t idim, size_t dim_stride, T* start) + NdOffsetMatrixProxy(const DimRange* dim_ranges, size_t idim, size_t dim_stride, T* start) : dim_ranges_(dim_ranges) , idim_(idim) , dim_stride_(dim_stride) diff --git a/libs/libvtrutil/src/vtr_prefix_sum.h b/libs/libvtrutil/src/vtr_prefix_sum.h new file mode 100644 index 00000000000..31635904f1b --- /dev/null +++ b/libs/libvtrutil/src/vtr_prefix_sum.h @@ -0,0 +1,285 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Definition of the Prefix Sum class which enables O(1) time-complexity + * sums over regions of an unchanging grid of values. + */ + +#pragma once + +#include +#include +#include "vtr_assert.h" +#include "vtr_ndmatrix.h" + +namespace vtr { + +/** + * @brief 1D Prefix Sum manager class. + * + * Given an array of values, it may be necessary to find the sum of values + * within a continuous sub-section of the array. If this operation needs to be + * performed many times, this may be expensive in runtime to calculate. + * + * If the array of values does not change, we can create a prefix sum which will + * allow us to get the sum of values in some continuous sub-section of the array + * in O(1) time, instead of O(k) time where k is the number of values in the + * sub-section. + * + * This class has a space complexity of O(l) where l is the length of the array + * of values. + * + * + * Static Array of Values Example (values stored in a vector): + * + * std::vector vals = {...}; + * + * // Build the Prefix Sum + * vtr::PrefixSum1D prefix_sum(vals); + * + * // Compute the sum of the values between index 3 and 7 of the array (inclusive) + * float sum = prefix_sum.get_sum(3, 7); + * + * + * Dynamic Vector of Values Example (values derived at runtime): + * + * // Build the Prefix Sum using a lambda + * vtr::PrefixSum1D prefix_sum(length, [&](size_t x) { + * // This lambda returns the value that would be in the array at index x. + * return static_cast(x * x); + * }); + * + * // Compute the sum of the values between index 0 and 5 of the array (inclusive) + * float sum = prefix_sum.get_sum(0, 5); + */ +template +class PrefixSum1D { + public: + PrefixSum1D() = default; + + /** + * @brief Construct the 1D prefix sum. + * + * This pre-computes the sums of values in the array, making it faster to + * get the sum of sub-regions of the array later. + * + * This constructor has a time complexity of O(length) + * + * @param length + * The length of the array to a make a prefix sum of. + * @param lookup + * A lambda function which will return the value in the array at + * the given x index. This is a lambda to allow a prefix sum to be + * created, even if the values in the array are not stored in a + * vector (may be computed on the spot). + * @param zero + * What is zero for this data type. For most basic data types (like + * int float, etc.) this parameter can be ignored; for more complex + * data classes (like multi-dimensional vectors) this is necessary + * to be passed in. + */ + PrefixSum1D(size_t length, std::function lookup, T zero = T()) + : prefix_sum_(length + 1, zero) { + // The first value in the prefix sum is already initialized to 0. + + // Initialize the prefix sum. The prefix sum at position x is the sum + // of all values in the original array from 0 to x - 1. + for (size_t x = 1; x < length + 1; x++) { + prefix_sum_[x] = prefix_sum_[x - 1] + lookup(x - 1); + } + } + + /** + * @brief Construct the 1D prefix sum from a vector. + */ + PrefixSum1D(std::vector vals, T zero = T()) + : PrefixSum1D( + vals.size(), + [&](size_t x) noexcept { + return vals[x]; + }, + zero) {} + + /** + * @brief Get the sum of all values in the original array of values between + * lower_x and upper_x (inclusive). + * + * Inclusive means that the sum will include the values at lower_x and + * upper_x. + * + * This method has O(1) time complexity. + */ + T get_sum(size_t lower_x, size_t upper_x) const { + // Some safety asserts. + VTR_ASSERT_SAFE_MSG(lower_x <= upper_x, "lower_x is larger than upper_x"); + VTR_ASSERT_SAFE_MSG(lower_x < prefix_sum_.size() - 1, "lower_x out of range"); + VTR_ASSERT_SAFE_MSG(upper_x < prefix_sum_.size() - 1, "upper_x out of range"); + + // The sum of the region lower_x to upper_x inclusive is equal to + // - The sum from 0 to upper_x + // - Minus the sum from 0 to lower_x - 1 + // Note: These are all offset by 1 since the first value is zero. This + // saves us from having to do bound checking. + return prefix_sum_[upper_x + 1] - prefix_sum_[lower_x]; + } + + private: + /** + * @brief The 1D prefix sum of the original array of values. + * + * Index x of the prefix sum contains the sum of all values in the original + * array from 0 to x - 1. The first value in this array is 0. By setting the + * first value in the array to 0, we can avoid bound checking. This data + * structure has the special property that the sum of any sub-array can be + * computed in O(1) time. + */ + std::vector prefix_sum_; +}; + +/** + * @brief 2D Prefix Sum manager class. + * + * Given a 2D grid of values, it may be necessary to find the sum of values + * within some rectangular sub-region of that grid. If this operation needs to + * be performed many times, this may be expensive in runtime to calculate. + * + * If the grid of values does not change, we can create a prefix sum which will + * allow us to get the sum of values in some rectangular sub-region of the + * grid in O(1) time, instead of O(k) time where k is the number of values + * in the region. + * + * This class has a space complexity of O(w * h) where w and h are the width + * and height of the grid of values. + * + * + * Static Matrix of Values Example (values stored in a matrix): + * + * vtr::NdMatrix vals({w, h}); + * + * // ... Initialize vals + * + * // Build the Prefix Sum + * vtr::PrefixSum2D prefix_sum(vals); + * + * // Compute the sum of the rectangular region from (1, 2) to (3, 4) inclusive. + * float sum = prefix_sum.get_sum(1, 2, 3, 4); + * + * + * Dynamic Matrix of Values Example (values derived at runtime): + * + * // Build the Prefix Sum using a lambda + * vtr::PrefixSum2D prefix_sum(w, h, [&](size_t x, size_t y) { + * // This lambda returns the value that would be in the matrix at (x, y) + * return (x + y) / 2.f; + * }); + * + * // Compute the sum of the rectangular region from (0, 4) to (3, 5) inclusive. + * float sum = prefix_sum.get_sum(0, 4, 3, 5); + */ +template +class PrefixSum2D { + public: + PrefixSum2D() = default; + + /** + * @brief Construct the 2D prefix sum. + * + * This pre-computes the sums of values in the grid, making it faster to + * get the sum of sub-regions of the grid later. + * + * This constructor has a time complexity of O(w * h). + * + * @param w + * The width of the grid of values to make a prefix sum over. + * @param h + * The height of the grid of values to make a prefix sum over. + * @param lookup + * A lambda function which will return the value in the grid at the + * given x, y position. This is a lambda to allow a prefix sum to + * be created, even if the values in the grid are not stored in + * a matrix (may be computed at runtime). + * @param zero + * What is zero for this data type. For most basic data types (like + * int, float, etc.) this parameter can be ignored; for more complex + * data classes (like multi-dimensional vectors) this is necessary + * to be passed in. + */ + PrefixSum2D(size_t w, size_t h, std::function lookup, T zero = T()) + : prefix_sum_({w + 1, h + 1}, zero) { + // The first row and first column should already be initialized to zero. + + // Initialize the prefix sum. The prefix sum at position (x, y) is the + // sum of all values in the original matrix in the rectangle from (0, 0) + // to (x - 1, y - 1) inclusive. + for (size_t x = 1; x < w + 1; x++) { + for (size_t y = 1; y < h + 1; y++) { + prefix_sum_[x][y] = prefix_sum_[x - 1][y] + + prefix_sum_[x][y - 1] + + lookup(x - 1, y - 1) + - prefix_sum_[x - 1][y - 1]; + } + } + } + + /** + * @brief Constructs a 2D prefix sum from a 2D grid of values. + */ + PrefixSum2D(const vtr::NdMatrix& vals, T zero = T()) + : PrefixSum2D( + vals.dim_size(0), + vals.dim_size(1), + [&](size_t x, size_t y) { + return vals[x][y]; + }, + zero) {} + + /** + * @brief Get the sum of all values in the original grid of values between + * x = [lower_x, upper_x] and y = [lower_y, upper_y]. + * + * This sum is inclusive, so it also sums the values at (upper_x, upper_y). + * + * This method has O(1) time complexity. + */ + T get_sum(size_t lower_x, size_t lower_y, size_t upper_x, size_t upper_y) const { + // Some safety asserts. + VTR_ASSERT_SAFE_MSG(lower_x <= upper_x, "lower_x is larger than upper_x"); + VTR_ASSERT_SAFE_MSG(lower_y <= upper_y, "lower_y is larger than upper_y"); + VTR_ASSERT_SAFE_MSG(lower_x < prefix_sum_.dim_size(0) - 1, "lower_x out of range"); + VTR_ASSERT_SAFE_MSG(upper_x < prefix_sum_.dim_size(0) - 1, "upper_x out of range"); + VTR_ASSERT_SAFE_MSG(lower_y < prefix_sum_.dim_size(1) - 1, "lower_y out of range"); + VTR_ASSERT_SAFE_MSG(upper_y < prefix_sum_.dim_size(1) - 1, "upper_y out of range"); + + // The sum of the region (lower_x, lower_y) to (upper_x, upper_y) + // inclusive is equal to: + // - The sum of the region (0, 0) to (upper_x, upper_y) + // - Minus the sum of the region (0, 0) to (lower_x - 1, upper_y) + // - Remove the part below the region + // - Minus the sum of the region (0, 0) to (upper_x, lower_y - 1) + // - Remove the part left of the region + // - Plus the sum of the region (0, 0) to (lower_x - 1, lower_y - 1) + // - Add back on the lower-left corner which was subtracted twice. + // Note: all of these are offset by 1 since the first row and column + // are all zeros. This allows us to avoid bounds checking when + // lower_x or lower_y are 0. + return prefix_sum_[upper_x + 1][upper_y + 1] + - prefix_sum_[lower_x][upper_y + 1] + - prefix_sum_[upper_x + 1][lower_y] + + prefix_sum_[lower_x][lower_y]; + } + + private: + /** + * @brief The 2D prefix sum of the original grid of values. + * + * Position (x, y) of the prefix sum contains the sum of all values in the + * rectangle (0, 0) -> (x - 1, y - 1) inclusive. The first row and column + * are all zeros. By setting these to zero, we can avoid bound checking. + * This data structure has the special property that the sum of any + * rectangular region can be computed in O(1) time. + */ + vtr::NdMatrix prefix_sum_; +}; + +} // namespace vtr diff --git a/libs/libvtrutil/src/vtr_random.cpp b/libs/libvtrutil/src/vtr_random.cpp index eb1756702da..6bef9c41198 100644 --- a/libs/libvtrutil/src/vtr_random.cpp +++ b/libs/libvtrutil/src/vtr_random.cpp @@ -23,7 +23,7 @@ int RandomNumberGenerator::irand(int imax) { // state = (state * IA + IC) % IM; random_state_ = random_state_ * IA + IC; // Use overflow to wrap - ival = random_state_ & (IM - 1); // Modulus + ival = random_state_ & (IM - 1); // Modulus ival = (int)((float)ival * (float)(imax + 0.999) / (float)IM); if constexpr (CHECK_RAND_CONSTEXPR) { @@ -42,7 +42,7 @@ int RandomNumberGenerator::irand(int imax) { float RandomNumberGenerator::frand() { random_state_ = random_state_ * IA + IC; /* Use overflow to wrap */ - int ival = random_state_ & (IM - 1); /* Modulus */ + int ival = random_state_ & (IM - 1); /* Modulus */ float fval = (float)ival / (float)IM; if constexpr (CHECK_RAND_CONSTEXPR) { diff --git a/libs/libvtrutil/src/vtr_random.h b/libs/libvtrutil/src/vtr_random.h index 76c8bb37912..15614b7141e 100644 --- a/libs/libvtrutil/src/vtr_random.h +++ b/libs/libvtrutil/src/vtr_random.h @@ -53,7 +53,6 @@ class RandomNumberGenerator : public RandomNumberGeneratorInterface { state_t random_state_ = 0; }; - class RngContainer : public RandomNumberGeneratorInterface { public: RngContainer(const RngContainer&) = delete; @@ -67,7 +66,6 @@ class RngContainer : public RandomNumberGeneratorInterface { inline virtual float frand() override { return rng_->frand(); } private: - std::unique_ptr rng_; #ifdef SPEC_CPU diff --git a/libs/libvtrutil/src/vtr_rusage.cpp b/libs/libvtrutil/src/vtr_rusage.cpp index a3b74c04c86..466e8264172 100644 --- a/libs/libvtrutil/src/vtr_rusage.cpp +++ b/libs/libvtrutil/src/vtr_rusage.cpp @@ -1,8 +1,8 @@ #include "vtr_rusage.h" #ifdef __unix__ -# include -# include +#include +#include #endif namespace vtr { diff --git a/libs/libvtrutil/src/vtr_strong_id.h b/libs/libvtrutil/src/vtr_strong_id.h index 5c738770d57..672dbae1e7e 100644 --- a/libs/libvtrutil/src/vtr_strong_id.h +++ b/libs/libvtrutil/src/vtr_strong_id.h @@ -167,7 +167,7 @@ template constexpr bool operator!=(const StrongId& lhs, const StrongId& rhs); template -constexpr bool operator<(const StrongId& lhs, const StrongId& rhs); +constexpr bool operator<(const StrongId& lhs, const StrongId& rhs) noexcept; template std::ostream& operator<<(std::ostream& out, const StrongId& rhs); @@ -182,11 +182,11 @@ class StrongId { static constexpr StrongId INVALID() noexcept { return StrongId(); } ///@brief Default to the sentinel value - constexpr StrongId() + constexpr StrongId() noexcept : id_(sentinel) {} ///@brief Only allow explicit constructions from a raw Id (no automatic conversions) - explicit constexpr StrongId(T id) + explicit constexpr StrongId(T id) noexcept : id_(id) {} // Allow some explicit conversion to useful types: @@ -216,7 +216,7 @@ class StrongId { ///@brief != operator friend constexpr bool operator!= <>(const StrongId& lhs, const StrongId& rhs); ///@brief < operator - friend constexpr bool operator< <>(const StrongId& lhs, const StrongId& rhs); + friend constexpr bool operator< <>(const StrongId& lhs, const StrongId& rhs) noexcept; /** * @brief to be able to print them out @@ -241,7 +241,7 @@ constexpr bool operator!=(const StrongId& lhs, const StrongId< ///@brief operator < Needed for std::map-like containers template -constexpr bool operator<(const StrongId& lhs, const StrongId& rhs) { +constexpr bool operator<(const StrongId& lhs, const StrongId& rhs) noexcept { return lhs.id_ < rhs.id_; } diff --git a/libs/libvtrutil/src/vtr_strong_id_range.h b/libs/libvtrutil/src/vtr_strong_id_range.h index f22df41f67e..6728f13a174 100644 --- a/libs/libvtrutil/src/vtr_strong_id_range.h +++ b/libs/libvtrutil/src/vtr_strong_id_range.h @@ -46,9 +46,9 @@ class StrongIdIterator { using difference_type = ssize_t; ///@brief Dereference operator (*) - StrongId& operator*() { + StrongId operator*() const { VTR_ASSERT_SAFE(bool(id_)); - return this->id_; + return id_; } ///@brief += operator @@ -75,6 +75,14 @@ class StrongIdIterator { return *this; } + ///@brief Post-increment operator + StrongIdIterator operator++(int) { + VTR_ASSERT_SAFE(bool(id_)); + StrongIdIterator temp = *this; // Create a copy of the current object + ++(*this); // Use the pre-increment operator to increment + return temp; // Return the copy + } + ///@brief Decremment operator StrongIdIterator& operator--() { VTR_ASSERT_SAFE(bool(id_)); diff --git a/libs/libvtrutil/src/vtr_thread_pool.h b/libs/libvtrutil/src/vtr_thread_pool.h new file mode 100644 index 00000000000..dbf2f5ed258 --- /dev/null +++ b/libs/libvtrutil/src/vtr_thread_pool.h @@ -0,0 +1,165 @@ +#pragma once + +/** + * @file vtr_thread_pool.h + * @brief A generic thread pool for parallel task execution + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vtr_log.h" +#include "vtr_time.h" + +namespace vtr { + +/** + * A thread pool for parallel task execution. It is a naive + * implementation which uses a queue for each thread and assigns + * tasks in a round robin fashion. + * + * Example usage: + * + * ``` + * vtr::thread_pool pool(4); // 4 threads + * pool.schedule_work([]{ + * // Task body + * }); + * pool.wait_for_all(); // There's no API to wait for a single task + * ``` + */ +class thread_pool { + private: + /** Thread-local data */ + struct ThreadData { + std::thread thread; + /** Per-thread task queue */ + std::queue> task_queue; + + /** Threads wait on cv for a stop signal or a new task + * queue_mutex is required for condition variable */ + std::mutex queue_mutex; + std::condition_variable cv; + bool stop = false; + }; + + /** Container for thread-local data */ + std::vector> threads; + /** Used for round-robin scheduling */ + std::atomic next_thread{0}; + /** Used for wait_for_all */ + std::atomic active_tasks{0}; + + /** Condition variable for wait_for_all */ + std::mutex completion_mutex; + std::condition_variable completion_cv; + + public: + /** Create a thread pool with \p thread_count threads. */ + thread_pool(size_t thread_count) { + threads.reserve(thread_count); + + for (size_t i = 0; i < thread_count; i++) { + auto thread_data = std::make_unique(); + + thread_data->thread = std::thread([&]() { + ThreadData* td = thread_data.get(); + + while (true) { + std::function task; + + { /* Wait until a task is available or stop signal is received */ + std::unique_lock lock(td->queue_mutex); + + td->cv.wait(lock, [td]() { + return td->stop || !td->task_queue.empty(); + }); + + if (td->stop && td->task_queue.empty()) { + return; + } + + /* Fetch a task from the queue */ + task = std::move(td->task_queue.front()); + td->task_queue.pop(); + } + + vtr::Timer task_timer; + task(); + } + }); + + threads.push_back(std::move(thread_data)); + } + } + + /** Schedule a function to be executed on one of the threads. */ + template + void schedule_work(F&& f) { + active_tasks++; + + /* Round-robin thread assignment */ + size_t thread_idx = (next_thread++) % threads.size(); + auto thread_data = threads[thread_idx].get(); + + auto task = [this, f = std::forward(f)]() { + vtr::Timer task_timer; + + try { + f(); + } catch (const std::exception& e) { + VTR_LOG_ERROR("Thread %zu failed task with error: %s\n", + std::this_thread::get_id(), e.what()); + throw; + } catch (...) { + VTR_LOG_ERROR("Thread %zu failed task with unknown error\n", + std::this_thread::get_id()); + throw; + } + + size_t remaining = --active_tasks; + if (remaining == 0) { + completion_cv.notify_all(); + } + }; + + /* Queue new task */ + { + std::lock_guard lock(thread_data->queue_mutex); + thread_data->task_queue.push(std::move(task)); + } + thread_data->cv.notify_one(); + } + + /** Wait until the work queue is empty. + * Note that functions are allowed to schedule new functions. */ + void wait_for_all() { + std::unique_lock lock(completion_mutex); + completion_cv.wait(lock, [this]() { return active_tasks == 0; }); + } + + ~thread_pool() { + /* Stop all threads */ + for (auto& thread_data : threads) { + { + std::lock_guard lock(thread_data->queue_mutex); + thread_data->stop = true; + } + thread_data->cv.notify_one(); + } + + for (auto& thread_data : threads) { + if (thread_data->thread.joinable()) { + thread_data->thread.join(); + } + } + } +}; + +} // namespace vtr diff --git a/libs/libvtrutil/src/vtr_util.cpp b/libs/libvtrutil/src/vtr_util.cpp index b3eef7379eb..eca51b05e90 100644 --- a/libs/libvtrutil/src/vtr_util.cpp +++ b/libs/libvtrutil/src/vtr_util.cpp @@ -12,7 +12,7 @@ #include "vtr_error.h" #if defined(__unix__) -# include //For getpid() +#include //For getpid() #endif namespace vtr { @@ -396,7 +396,7 @@ char* getline(char*& _lineptr, FILE* _stream) { #if defined(__unix__) nread = getdelim(&_lineptr, &_n, '\n', _stream); #elif defined(_WIN32) -# define __WIN_NLTK "\r\n" +#define __WIN_NLTK "\r\n" nread = getdelim(&_lineptr, &_n, __WIN_NLTK, _stream); #endif diff --git a/libs/libvtrutil/src/vtr_vector.h b/libs/libvtrutil/src/vtr_vector.h index be4e5874e98..921238a77d7 100644 --- a/libs/libvtrutil/src/vtr_vector.h +++ b/libs/libvtrutil/src/vtr_vector.h @@ -180,17 +180,20 @@ class vector : private std::vector { vector::const_iterator iter; bool operator!=(const enumerated_iterator& other) const { return iter != other.iter; } - void operator++() { i = key_type(size_t(i) + 1); iter++; } + void operator++() { + i = key_type(size_t(i) + 1); + iter++; + } std::tuple operator*() { return std::tie(i, *iter); } }; struct enumerated_wrapper { const vector& vec; - auto begin() { return enumerated_iterator{ key_type(0), vec.begin() }; } - auto end() { return enumerated_iterator{ key_type(vec.size()), vec.end() }; } + auto begin() { return enumerated_iterator{key_type(0), vec.begin()}; } + auto end() { return enumerated_iterator{key_type(vec.size()), vec.end()}; } }; - return enumerated_wrapper{ *this }; + return enumerated_wrapper{*this}; } public: diff --git a/libs/libvtrutil/test/test_prefix_sum.cpp b/libs/libvtrutil/test/test_prefix_sum.cpp new file mode 100644 index 00000000000..a907615fd4f --- /dev/null +++ b/libs/libvtrutil/test/test_prefix_sum.cpp @@ -0,0 +1,98 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Test cases for the Prefix Sum class in vtr_util. + */ + +#include "catch2/catch_test_macros.hpp" + +#include "vtr_ndmatrix.h" +#include "vtr_prefix_sum.h" + +using namespace Catch; + +TEST_CASE("PrefixSum1D", "[vtr_prefix_sum/PrefixSum1D]") { + // Construct a 1D array to compute the prefix sum over. + std::vector vals = {1.f, 7.f, 2.f, 2.f, 5.f, 6.f, 1.f, 9.f, 1.f, 3.f}; + + // Construct the Prefix Sum. + vtr::PrefixSum1D prefix_sum(vals); + + // Check that the sum of each length 1 region is the original value. + SECTION("construction") { + for (size_t x = 0; x < vals.size(); x++) { + float sum_val = prefix_sum.get_sum(x, x); + REQUIRE(sum_val == vals[x]); + } + } + + float sum_of_all_vals = 0.f; + for (size_t x = 0; x < vals.size(); x++) { + sum_of_all_vals += vals[x]; + } + + // Check that get_sum is working on some testcases. + SECTION("get_sum") { + REQUIRE(prefix_sum.get_sum(0, vals.size() - 1) == sum_of_all_vals); + REQUIRE(prefix_sum.get_sum(0, 2) == 10.f); + REQUIRE(prefix_sum.get_sum(7, 9) == 13.f); + REQUIRE(prefix_sum.get_sum(2, 5) == 15.f); + } +} + +TEST_CASE("PrefixSum2D", "[vtr_prefix_sum/PrefixSum2D]") { + // Construct a 2D grid to compute the prefix sum over. + vtr::NdMatrix vals({4, 4}); + /* + * [ 1 3 9 2 ] + * [ 2 4 0 8 ] + * [ 3 7 1 3 ] + * [ 5 6 9 2 ] + */ + vals[0][0] = 5.f; + vals[1][0] = 6.f; + vals[2][0] = 9.f; + vals[3][0] = 2.f; + vals[0][1] = 3.f; + vals[1][1] = 7.f; + vals[2][1] = 1.f; + vals[3][1] = 3.f; + vals[0][2] = 2.f; + vals[1][2] = 4.f; + vals[2][2] = 0.f; + vals[3][2] = 8.f; + vals[0][3] = 1.f; + vals[1][3] = 3.f; + vals[2][3] = 9.f; + vals[3][3] = 2.f; + + // Construct the Prefix Sum. + vtr::PrefixSum2D prefix_sum(vals); + + // Check that the sum of each 1x1 region is the original value. + SECTION("construction") { + for (size_t x = 0; x < 4; x++) { + for (size_t y = 0; y < 4; y++) { + float sum_val = prefix_sum.get_sum(x, y, x, y); + REQUIRE(sum_val == vals[x][y]); + } + } + } + + float sum_of_all_vals = 0; + for (size_t x = 0; x < 4; x++) { + for (size_t y = 0; y < 4; y++) { + sum_of_all_vals += vals[x][y]; + } + } + + // Check that get_sum is working on some testcases. + SECTION("get_sum") { + REQUIRE(prefix_sum.get_sum(0, 0, 3, 3) == sum_of_all_vals); + REQUIRE(prefix_sum.get_sum(1, 1, 2, 2) == 12.f); + REQUIRE(prefix_sum.get_sum(0, 0, 3, 0) == 22.f); + REQUIRE(prefix_sum.get_sum(0, 0, 0, 3) == 11.f); + REQUIRE(prefix_sum.get_sum(1, 2, 2, 3) == 16.f); + } +} diff --git a/odin_ii/regression_test/parse_result/parse_result.py b/odin_ii/regression_test/parse_result/parse_result.py index 83373489d22..0e3bb7faefc 100755 --- a/odin_ii/regression_test/parse_result/parse_result.py +++ b/odin_ii/regression_test/parse_result/parse_result.py @@ -567,7 +567,7 @@ def compare_instances(header, toml_dict, tbl_entry, golden_tbl_entry): if len(tbl_entry[header]) != len(golden_tbl_entry[header]): return False - for (value, golden_value) in zip(tbl_entry[header], golden_tbl_entry[header]): + for value, golden_value in zip(tbl_entry[header], golden_tbl_entry[header]): if not compare_values(header, toml_dict, value, golden_value): return False @@ -778,7 +778,12 @@ def main(): arguments = parse_shared_args(sys.argv[2:]) exit( - {"display": display, "parse": parse, "join": join, "compare": compare,}.get( + { + "display": display, + "parse": parse, + "join": join, + "compare": compare, + }.get( command, lambda: "Invalid Command" )(arguments) ) diff --git a/odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py b/odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py index 617316e5541..c0800584a71 100644 --- a/odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py +++ b/odin_ii/regression_test/tools/8_bit_arithmetic_power_output.py @@ -11,12 +11,12 @@ def make_output_vector(power): print("c") next_a = 0 for i in range(0, 512): - value = next_a ** power + value = next_a**power output = f"{value:#0{4}x}" print(output[0:2] + output[-2:]) if i % 2 == 1: next_a += 1 - value = next_a ** power + value = next_a**power output = f"{value:#0{4}x}" print(output[0:2] + output[-2:]) print("0x00") diff --git a/odin_ii/regression_test/tools/asr_vector_maker.py b/odin_ii/regression_test/tools/asr_vector_maker.py index b3477e36f7d..27c5262303e 100644 --- a/odin_ii/regression_test/tools/asr_vector_maker.py +++ b/odin_ii/regression_test/tools/asr_vector_maker.py @@ -67,7 +67,7 @@ def make_input_vector(bits): # One for each value (2^bits) # a rising edge for each line ( * 2) # a line for reset ( + 1) - lines = ((2 ** bits) * 2) + 2 + lines = ((2**bits) * 2) + 2 for i in range(0, lines): if i < (lines - 1): inputs[0].append(value) diff --git a/odin_ii/src/ast/ast_elaborate.h b/odin_ii/src/ast/ast_elaborate.h index cf6beb85607..d93f0c51f6c 100644 --- a/odin_ii/src/ast/ast_elaborate.h +++ b/odin_ii/src/ast/ast_elaborate.h @@ -32,4 +32,4 @@ ast_node_t* find_top_module(ast_t* ast); int simplify_ast_module(ast_node_t** ast_module, sc_hierarchy* local_ref); void create_param_table_for_scope(ast_node_t* module_items, sc_hierarchy* local_ref); -#endif \ No newline at end of file +#endif diff --git a/odin_ii/src/ast/ast_loop_unroll.cpp b/odin_ii/src/ast/ast_loop_unroll.cpp index ff522f56e0c..1b0887c5860 100644 --- a/odin_ii/src/ast/ast_loop_unroll.cpp +++ b/odin_ii/src/ast/ast_loop_unroll.cpp @@ -342,7 +342,6 @@ post_condition_function resolve_binary_operation(ast_node_t* node) { } } - /* * (function: resolve_post_condition) * return a lambda which gives the next value diff --git a/odin_ii/src/ast/ast_util.cpp b/odin_ii/src/ast/ast_util.cpp index f60759b6ae9..cff0a438ca7 100644 --- a/odin_ii/src/ast/ast_util.cpp +++ b/odin_ii/src/ast/ast_util.cpp @@ -113,8 +113,7 @@ void add_top_module_to_ast(ast_t* ast, ast_node_t* to_add) { oassert(ast); if (to_add) { ast->top_modules_count += 1; - ast->top_modules - = (ast_node_t**)vtr::realloc(ast->top_modules, sizeof(ast_node_t*) * ast->top_modules_count); + ast->top_modules = (ast_node_t**)vtr::realloc(ast->top_modules, sizeof(ast_node_t*) * ast->top_modules_count); ast->top_modules[ast->top_modules_count - 1] = to_add; } diff --git a/odin_ii/src/config/read_xml_config_file.cpp b/odin_ii/src/config/read_xml_config_file.cpp index b329dbd461b..124c395337f 100644 --- a/odin_ii/src/config/read_xml_config_file.cpp +++ b/odin_ii/src/config/read_xml_config_file.cpp @@ -321,4 +321,4 @@ void read_optimizations(pugi::xml_node a_node, config_t* config, const pugiutil: } return; -} \ No newline at end of file +} diff --git a/odin_ii/src/core/block_memories.cpp b/odin_ii/src/core/block_memories.cpp index 0b3cad7e3ea..fe0717c953e 100644 --- a/odin_ii/src/core/block_memories.cpp +++ b/odin_ii/src/core/block_memories.cpp @@ -1470,4 +1470,4 @@ static void free_block_memory(block_memory_t* to_free) { vtr::free(to_free->memory_id); vtr::free(to_free); -} \ No newline at end of file +} diff --git a/odin_ii/src/core/odin_memory.h b/odin_ii/src/core/odin_memory.h index f681ba5e50a..2b431c9db3c 100644 --- a/odin_ii/src/core/odin_memory.h +++ b/odin_ii/src/core/odin_memory.h @@ -35,9 +35,9 @@ #include "odin_error.h" #ifndef __GLIBC__ -# include +#include #else -# include +#include #endif namespace odin { @@ -138,4 +138,4 @@ void realloc(T** ptr_ref, S _n_bytes) { } } // namespace odin -#endif //ODIN_MEMORY_H \ No newline at end of file +#endif //ODIN_MEMORY_H diff --git a/odin_ii/src/main.cpp b/odin_ii/src/main.cpp index a0bc57d9cae..458be4ae027 100644 --- a/odin_ii/src/main.cpp +++ b/odin_ii/src/main.cpp @@ -46,4 +46,4 @@ int main(int argc, char** argv) { netlist_t* odin_netlist = start_odin_ii(argc, argv); terminate_odin_ii(odin_netlist); return 0; -} \ No newline at end of file +} diff --git a/odin_ii/src/netlist/netlist_statistic.cpp b/odin_ii/src/netlist/netlist_statistic.cpp index 6a2aeef0061..6d8ce8c5711 100644 --- a/odin_ii/src/netlist/netlist_statistic.cpp +++ b/odin_ii/src/netlist/netlist_statistic.cpp @@ -547,4 +547,4 @@ void compute_statistics(netlist_t* netlist, bool display) { printf("\n"); } } -} \ No newline at end of file +} diff --git a/odin_ii/src/utils/hierarchy_util.cpp b/odin_ii/src/utils/hierarchy_util.cpp index 7e5f9556601..72c78914e3d 100644 --- a/odin_ii/src/utils/hierarchy_util.cpp +++ b/odin_ii/src/utils/hierarchy_util.cpp @@ -332,4 +332,4 @@ ast_node_t* resolve_hierarchical_name_reference_by_upward_search(sc_hierarchy* l } return NULL; -} \ No newline at end of file +} diff --git a/odin_ii/src/utils/hierarchy_util.h b/odin_ii/src/utils/hierarchy_util.h index af38204243c..88148de1bc8 100644 --- a/odin_ii/src/utils/hierarchy_util.h +++ b/odin_ii/src/utils/hierarchy_util.h @@ -62,4 +62,4 @@ sc_hierarchy* copy_sc_hierarchy(sc_hierarchy* to_copy); void free_sc_hierarchy(sc_hierarchy* to_free); ast_node_t* resolve_hierarchical_name_reference(sc_hierarchy* local_ref, char* identifier); -#endif \ No newline at end of file +#endif diff --git a/odin_ii/src/utils/odin_types.h b/odin_ii/src/utils/odin_types.h index 2fa18d01f11..8ff837d1114 100644 --- a/odin_ii/src/utils/odin_types.h +++ b/odin_ii/src/utils/odin_types.h @@ -48,9 +48,9 @@ #define ODIN_SHORT_STRING 1 #ifndef DEBUG_ODIN -# define ODIN_STRING_TYPE ODIN_SHORT_STRING +#define ODIN_STRING_TYPE ODIN_SHORT_STRING #else -# define ODIN_STRING_TYPE ODIN_LONG_STRING +#define ODIN_STRING_TYPE ODIN_LONG_STRING #endif #define ODIN_STD_BITWIDTH (sizeof(long) * 8) diff --git a/odin_ii/src/utils/odin_util.cpp b/odin_ii/src/utils/odin_util.cpp index 2597fcfdb9e..4b605607f4e 100644 --- a/odin_ii/src/utils/odin_util.cpp +++ b/odin_ii/src/utils/odin_util.cpp @@ -43,11 +43,11 @@ // for mkdir #ifdef WIN32 -# include -# define getcwd _getcwd +#include +#define getcwd _getcwd #else -# include -# include +#include +#include #endif long shift_left_value_with_overflow_check(long input_value, long shift_by, loc_t loc) { diff --git a/odin_ii/src/utils/scope_util.cpp b/odin_ii/src/utils/scope_util.cpp index 658533b9f47..2d77fd9276d 100644 --- a/odin_ii/src/utils/scope_util.cpp +++ b/odin_ii/src/utils/scope_util.cpp @@ -80,4 +80,4 @@ void push_scope() { /* update current scope */ current_scope = scope_stack.back(); -} \ No newline at end of file +} diff --git a/parmys/CMakeLists.txt b/parmys/CMakeLists.txt index 1df18065428..f2139930d36 100644 --- a/parmys/CMakeLists.txt +++ b/parmys/CMakeLists.txt @@ -35,6 +35,7 @@ target_link_libraries(parmys ) set_target_properties(parmys PROPERTIES PREFIX "") # Avoid extra 'lib' prefix +set_target_properties(parmys PROPERTIES SUFFIX ".so") # Yosys expects the suffix to be '.so' even on macOS add_custom_target(parmys-plugin ALL DEPENDS parmys diff --git a/requirements.txt b/requirements.txt index e6b107c0625..3498cec63c3 100644 --- a/requirements.txt +++ b/requirements.txt @@ -6,7 +6,7 @@ numpy scipy # Python linter and formatter click==8.0.2 # Our version of black needs an older version of click (https://stackoverflow.com/questions/71673404/importerror-cannot-import-name-unicodefun-from-click) -black==21.4b0 +black==24.3.0 pylint==2.7.4 # Surelog diff --git a/utils/fasm/src/fasm.cpp b/utils/fasm/src/fasm.cpp index 3001bb1ae8a..2785c1149e8 100644 --- a/utils/fasm/src/fasm.cpp +++ b/utils/fasm/src/fasm.cpp @@ -343,9 +343,9 @@ static AtomNetId _find_atom_input_logical_net(const t_pb* atom, const t_pb_route static LogicVec lut_outputs(const t_pb* atom_pb, size_t num_inputs, const t_pb_routes &pb_route) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId block_id = atom_ctx.lookup.pb_atom(atom_pb); - const auto& truth_table = atom_ctx.nlist.block_truth_table(block_id); - auto ports = atom_ctx.nlist.block_input_ports(atom_ctx.lookup.pb_atom(atom_pb)); + AtomBlockId block_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom_pb); + const auto& truth_table = atom_ctx.netlist().block_truth_table(block_id); + auto ports = atom_ctx.netlist().block_input_ports(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom_pb)); const t_pb_graph_node* gnode = atom_pb->pb_graph_node; @@ -384,7 +384,7 @@ static LogicVec lut_outputs(const t_pb* atom_pb, size_t num_inputs, const t_pb_r if(impl_input_net_id) { //If there is a valid net connected in the implementation - AtomNetId logical_net_id = atom_ctx.nlist.port_net(port_id, orig_index); + AtomNetId logical_net_id = atom_ctx.netlist().port_net(port_id, orig_index); VTR_ASSERT(impl_input_net_id == logical_net_id); //Mark the permutation. @@ -537,7 +537,7 @@ static const t_pb_routes &find_pb_route(const t_pb* pb) { void FasmWriterVisitor::check_for_param(const t_pb *atom) { auto& atom_ctx = g_vpr_ctx.atom(); - auto atom_blk_id = atom_ctx.lookup.pb_atom(atom); + auto atom_blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_blk_id == AtomBlockId::INVALID()) { return; } @@ -580,7 +580,7 @@ void FasmWriterVisitor::check_for_param(const t_pb *atom) { auto ¶ms = iter->second; - for(const auto& param : atom_ctx.nlist.block_params(atom_blk_id)) { + for(const auto& param : atom_ctx.netlist().block_params(atom_blk_id)) { auto feature = params.EmitFasmFeature(param.first, param.second); if(!feature.empty()) { @@ -592,12 +592,12 @@ void FasmWriterVisitor::check_for_param(const t_pb *atom) { void FasmWriterVisitor::check_for_lut(const t_pb* atom) { auto& atom_ctx = g_vpr_ctx.atom(); - auto atom_blk_id = atom_ctx.lookup.pb_atom(atom); + auto atom_blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_blk_id == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.nlist.block_model(atom_blk_id); + const t_model* model = atom_ctx.netlist().block_model(atom_blk_id); if (model->name == std::string(MODEL_NAMES)) { VTR_ASSERT(atom->pb_graph_node != nullptr); const auto *lut_definition = find_lut(atom->pb_graph_node); diff --git a/utils/fasm/src/main.cpp b/utils/fasm/src/main.cpp index 2fbee0a79c2..820179c1456 100644 --- a/utils/fasm/src/main.cpp +++ b/utils/fasm/src/main.cpp @@ -41,7 +41,7 @@ static bool write_fasm(bool is_flat) { auto& device_ctx = g_vpr_ctx.device(); auto& atom_ctx = g_vpr_ctx.atom(); - std::string fasm_filename = atom_ctx.nlist.netlist_name() + ".fasm"; + std::string fasm_filename = atom_ctx.netlist().netlist_name() + ".fasm"; vtr::printf("Writing Implementation FASM: %s\n", fasm_filename.c_str()); std::ofstream fasm_os(fasm_filename); fasm::FasmWriterVisitor visitor(&device_ctx.arch->strings, fasm_os, is_flat); diff --git a/utils/route_diag/CMakeLists.txt b/utils/route_diag/CMakeLists.txt index 809785c939a..b6b41592df9 100644 --- a/utils/route_diag/CMakeLists.txt +++ b/utils/route_diag/CMakeLists.txt @@ -8,7 +8,7 @@ target_link_libraries(route_diag libvpr ) -#Supress IPO link warnings if IPO is enabled +#Suppress IPO link warnings if IPO is enabled get_target_property(TEST_ROUTE_DIAG_USES_IPO route_diag INTERPROCEDURAL_OPTIMIZATION) if (TEST_ROUTE_DIAG_USES_IPO) set_property(TARGET route_diag APPEND PROPERTY LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS}) diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index debd89c8bd6..5074d79cc09 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -9,13 +9,10 @@ // Tool can either perform one route between a source (--source_rr_node) and // a sink (--sink_rr_node), or profile a source to all tiles (set // --source_rr_node and "--profile_source true"). -#include -#include -#include + #include #include "vtr_error.h" -#include "vtr_memory.h" #include "vtr_log.h" #include "vtr_time.h" @@ -28,16 +25,13 @@ #include "globals.h" #include "net_delay.h" -#include "RoutingDelayCalculator.h" #include "place_and_route.h" #include "router_delay_profiling.h" #include "route_tree.h" #include "route_common.h" #include "route_net.h" -#include "route_export.h" #include "rr_graph.h" -#include "rr_graph2.h" -#include "timing_place_lookup.h" +#include "compute_delta_delays_utils.h" struct t_route_util_options { /* Router diag tool Options */ @@ -238,36 +232,6 @@ static void profile_source(const Netlist<>& net_list, VTR_LOG("\n"); } -static t_chan_width setup_chan_width(t_router_opts router_opts, - t_chan_width_dist chan_width_dist) { - /*we give plenty of tracks, this increases routability for the */ - /*lookup table generation */ - - t_graph_type graph_directionality; - int width_fac; - - if (router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH) { - auto& device_ctx = g_vpr_ctx.device(); - - auto type = find_most_common_tile_type(device_ctx.grid); - - width_fac = 4 * type->num_pins; - /*this is 2x the value that binary search starts */ - /*this should be enough to allow most pins to */ - /*connect to tracks in the architecture */ - } else { - width_fac = router_opts.fixed_channel_width; - } - - if (router_opts.route_type == GLOBAL) { - graph_directionality = GRAPH_BIDIR; - } else { - graph_directionality = GRAPH_UNIDIR; - } - - return init_chan(width_fac, chan_width_dist, graph_directionality); -} - t_route_util_options read_route_util_options(int argc, const char** argv) { //Explicitly initialize for zero initialization t_route_util_options args = t_route_util_options(); @@ -283,7 +247,7 @@ t_route_util_options read_route_util_options(int argc, const char** argv) { route_diag_grp.add_argument(args.profile_source, "--profile_source") .help( "Profile routes from source to IPINs at all locations." - "This is similiar to the placer delay matrix construction.") + "This is similar to the placer delay matrix construction.") .show_in(argparse::ShowIn::HELP_ONLY); parser.parse_args(argc, argv); @@ -320,20 +284,18 @@ int main(int argc, const char **argv) { bool is_flat = vpr_setup.RouterOpts.flat_routing; - const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : + const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; - t_chan_width chan_width = setup_chan_width( - vpr_setup.RouterOpts, - Arch.Chans); + t_chan_width chan_width = setup_chan_width(vpr_setup.RouterOpts, + Arch.Chans); - alloc_routing_structs( - chan_width, - vpr_setup.RouterOpts, - &vpr_setup.RoutingArch, - vpr_setup.Segments, - Arch.directs, - is_flat); + alloc_routing_structs(chan_width, + vpr_setup.RouterOpts, + &vpr_setup.RoutingArch, + vpr_setup.Segments, + Arch.directs, + is_flat); if(route_options.profile_source) { profile_source(net_list, diff --git a/utils/vqm2blif/test/scripts/test_vqm2blif.sh b/utils/vqm2blif/test/scripts/test_vqm2blif.sh index 98966a9bc45..60c217a99e5 100755 --- a/utils/vqm2blif/test/scripts/test_vqm2blif.sh +++ b/utils/vqm2blif/test/scripts/test_vqm2blif.sh @@ -259,7 +259,7 @@ do done -# we create seperate subshells to process each iteration of the loops above. +# we create separate subshells to process each iteration of the loops above. # So below we check the result of the last shell. if [ $? -eq 1 ]; then diff --git a/vpr/scripts/profile/util.py b/vpr/scripts/profile/util.py index c6a252a3c75..8ac1e2930e5 100644 --- a/vpr/scripts/profile/util.py +++ b/vpr/scripts/profile/util.py @@ -5,6 +5,7 @@ import socket import getpass + # working on the task directory def sort_runs(runs): natural_sort(runs) diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 7ff47a81cf9..542269395c5 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -23,7 +23,7 @@ void generate_setup_timing_stats(const std::string& prefix, print_setup_timing_summary(*timing_ctx.constraints, *timing_info.setup_analyzer(), "Final ", analysis_opts.write_timing_summary); - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); @@ -48,7 +48,7 @@ void generate_hold_timing_stats(const std::string& prefix, print_hold_timing_summary(*timing_ctx.constraints, *timing_info.hold_analyzer(), "Final "); - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index 9b334402114..853f4cb2f02 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -7,9 +7,12 @@ #include "analytical_placement_flow.h" #include +#include "PreClusterTimingManager.h" #include "analytical_solver.h" #include "ap_netlist.h" #include "atom_netlist.h" +#include "cluster_util.h" +#include "detailed_placer.h" #include "full_legalizer.h" #include "gen_ap_netlist_from_atoms.h" #include "global_placer.h" @@ -20,6 +23,7 @@ #include "user_place_constraints.h" #include "vpr_context.h" #include "vpr_types.h" +#include "stats.h" #include "vtr_assert.h" #include "vtr_time.h" @@ -58,18 +62,104 @@ static void print_ap_netlist_stats(const APNetlist& netlist) { VTR_LOG("\n"); } +/** + * @brief Passes the flat placement information to a provided partial placement. + * + * @param flat_placement_info The flat placement information to be read. + * @param ap_netlist The APNetlist that used to iterate over its blocks. + * @param prepacker The Prepacker to get molecule of blocks in the ap_netlist. + * @param p_placement The partial placement to be updated which is assumend + * to be generated on ap_netlist or have the same blocks. + */ +static void convert_flat_to_partial_placement(const FlatPlacementInfo& flat_placement_info, const APNetlist& ap_netlist, const Prepacker& prepacker, PartialPlacement& p_placement) { + for (APBlockId ap_blk_id : ap_netlist.blocks()) { + // Get the molecule that AP block represents + PackMoleculeId mol_id = ap_netlist.block_molecule(ap_blk_id); + const t_pack_molecule& mol = prepacker.get_molecule(mol_id); + // Get location of a valid atom in the molecule and verify that + // all atoms of the molecule share same placement information. + float atom_loc_x, atom_loc_y, atom_loc_layer; + int atom_loc_sub_tile; + bool found_valid_atom = false; + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + float current_loc_x = flat_placement_info.blk_x_pos[atom_blk_id]; + float current_loc_y = flat_placement_info.blk_y_pos[atom_blk_id]; + float current_loc_layer = flat_placement_info.blk_layer[atom_blk_id]; + int current_loc_sub_tile = flat_placement_info.blk_sub_tile[atom_blk_id]; + if (found_valid_atom) { + if (current_loc_x != atom_loc_x || current_loc_y != atom_loc_y || current_loc_layer != atom_loc_layer || current_loc_sub_tile != atom_loc_sub_tile) + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Molecule of ID %zu contains atom %s (ID: %zu) with a location (%g, %g, layer: %g, subtile: %d) " + "that conflicts the location of other atoms in this molecule of (%g, %g, layer: %g, subtile: %d).", + mol_id, g_vpr_ctx.atom().netlist().block_name(atom_blk_id).c_str(), atom_blk_id, + current_loc_x, current_loc_y, current_loc_layer, current_loc_sub_tile, + atom_loc_x, atom_loc_y, atom_loc_layer, atom_loc_sub_tile); + } else { + atom_loc_x = current_loc_x; + atom_loc_y = current_loc_y; + atom_loc_layer = current_loc_layer; + atom_loc_sub_tile = current_loc_sub_tile; + found_valid_atom = true; + } + } + // Ensure that there is a valid atom in the molecule to pass its location. + VTR_ASSERT_MSG(found_valid_atom, "Each molecule must contain at least one valid atom"); + // Pass the placement information + p_placement.block_x_locs[ap_blk_id] = atom_loc_x; + p_placement.block_y_locs[ap_blk_id] = atom_loc_y; + p_placement.block_layer_nums[ap_blk_id] = atom_loc_layer; + p_placement.block_sub_tiles[ap_blk_id] = atom_loc_sub_tile; + } +} + +/** + * @brief If a flat placement is provided, skips the Global Placer and + * converts it to a partial placement. Otherwise, runs the Global Placer. + */ +static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, + const AtomNetlist& atom_nlist, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const DeviceContext& device_ctx) { + if (g_vpr_ctx.atom().flat_placement_info().valid) { + VTR_LOG("Flat Placement is provided in the AP flow, skipping the Global Placement.\n"); + PartialPlacement p_placement(ap_netlist); + convert_flat_to_partial_placement(g_vpr_ctx.atom().flat_placement_info(), + ap_netlist, + prepacker, + p_placement); + return p_placement; + } else { + // Run the Global Placer + std::unique_ptr global_placer = make_global_placer(ap_opts.analytical_solver_type, + ap_opts.partial_legalizer_type, + ap_netlist, + prepacker, + atom_nlist, + device_ctx.grid, + device_ctx.logical_block_types, + device_ctx.physical_tile_types, + pre_cluster_timing_manager, + ap_opts.ap_timing_tradeoff, + ap_opts.log_verbosity); + return global_placer->place(); + } +} + void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { // Start an overall timer for the Analytical Placement flow. vtr::ScopedStartFinishTimer timer("Analytical Placement"); // The global state used/modified by this flow. - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); const DeviceContext& device_ctx = g_vpr_ctx.device(); const UserPlaceConstraints& constraints = g_vpr_ctx.floorplanning().constraints; // Run the prepacker - Prepacker prepacker; - prepacker.init(atom_nlist, device_ctx.logical_block_types); + const Prepacker prepacker(atom_nlist, device_ctx.logical_block_types); // Create the ap netlist from the atom netlist using the result from the // prepacker. @@ -78,10 +168,26 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { constraints); print_ap_netlist_stats(ap_netlist); - // Run the Global Placer - std::unique_ptr global_placer = make_global_placer(e_global_placer::SimPL, - ap_netlist); - PartialPlacement p_placement = global_placer->place(); + // Pre-compute the pre-clustering timing delays. This object will be passed + // into the global placer and the full legalizer to make them timing driven. + PreClusterTimingManager pre_cluster_timing_manager(vpr_setup.PackerOpts.timing_driven, + atom_nlist, + g_vpr_ctx.atom().lookup(), + prepacker, + vpr_setup.PackerOpts.timing_update_type, + *device_ctx.arch, + vpr_setup.RoutingArch, + vpr_setup.PackerOpts.device_layout, + vpr_setup.AnalysisOpts); + + // Run the Global Placer. + const t_ap_opts& ap_opts = vpr_setup.APOpts; + PartialPlacement p_placement = run_global_placer(ap_opts, + atom_nlist, + ap_netlist, + prepacker, + pre_cluster_timing_manager, + device_ctx); // Verify that the partial placement is valid before running the full // legalizer. @@ -93,17 +199,33 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { device_ctx.grid.get_num_layers())); // Run the Full Legalizer. - FullLegalizer full_legalizer(ap_netlist, - vpr_setup, - device_ctx.grid, - device_ctx.arch, - atom_nlist, - prepacker, - device_ctx.logical_block_types, - vpr_setup.PackerRRGraph, - device_ctx.arch->models, - device_ctx.arch->model_library, - vpr_setup.PackerOpts); - full_legalizer.legalize(p_placement); -} + std::unique_ptr full_legalizer = make_full_legalizer(ap_opts.full_legalizer_type, + ap_netlist, + atom_nlist, + prepacker, + pre_cluster_timing_manager, + vpr_setup, + *device_ctx.arch, + device_ctx.grid); + full_legalizer->legalize(p_placement); + + // Print the number of resources in netlist and number of resources available in architecture + float target_device_utilization = vpr_setup.PackerOpts.target_device_utilization; + print_resource_usage(); + // Print the device utilization + print_device_utilization(target_device_utilization); + // Run the Detailed Placer. + std::unique_ptr detailed_placer = make_detailed_placer(ap_opts.detailed_placer_type, + g_vpr_ctx.placement().blk_loc_registry(), + atom_nlist, + g_vpr_ctx.clustering().clb_nlist, + vpr_setup, + *device_ctx.arch); + detailed_placer->optimize_placement(); + + // Clean up some of the global variables that will no longer be used outside + // of this flow. + g_vpr_ctx.mutable_placement().clean_placement_context_post_place(); + g_vpr_ctx.mutable_floorplanning().clean_floorplanning_context_post_place(); +} diff --git a/vpr/src/analytical_place/analytical_placement_flow.h b/vpr/src/analytical_place/analytical_placement_flow.h index 638456177f1..527fe241706 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.h +++ b/vpr/src/analytical_place/analytical_placement_flow.h @@ -16,4 +16,3 @@ struct t_vpr_setup; * @param vpr_setup The setup options provided by the user. */ void run_analytical_placement_flow(t_vpr_setup& vpr_setup); - diff --git a/vpr/src/analytical_place/analytical_solver.cpp b/vpr/src/analytical_place/analytical_solver.cpp index 4c5e0037c7b..22a846d43ea 100644 --- a/vpr/src/analytical_place/analytical_solver.cpp +++ b/vpr/src/analytical_place/analytical_solver.cpp @@ -9,13 +9,20 @@ #include "analytical_solver.h" #include #include +#include #include #include #include +#include "PreClusterTimingManager.h" +#include "atom_netlist.h" +#include "atom_netlist_fwd.h" +#include "device_grid.h" +#include "flat_placement_types.h" #include "partial_placement.h" #include "ap_netlist.h" #include "vpr_error.h" #include "vtr_assert.h" +#include "vtr_time.h" #include "vtr_vector.h" #ifdef EIGEN_INSTALLED @@ -35,18 +42,46 @@ #pragma GCC diagnostic pop #endif // EIGEN_INSTALLED -std::unique_ptr make_analytical_solver(e_analytical_solver solver_type, - const APNetlist& netlist) { +std::unique_ptr make_analytical_solver(e_ap_analytical_solver solver_type, + const APNetlist& netlist, + const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) { // Based on the solver type passed in, build the solver. switch (solver_type) { - case e_analytical_solver::QP_HYBRID: + case e_ap_analytical_solver::QP_Hybrid: #ifdef EIGEN_INSTALLED - return std::make_unique(netlist); + return std::make_unique(netlist, + device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity); #else (void)netlist; + (void)device_grid; + (void)atom_netlist; + (void)pre_cluster_timing_manager; + (void)ap_timing_tradeoff; + (void)log_verbosity; VPR_FATAL_ERROR(VPR_ERROR_AP, "QP Hybrid Solver requires the Eigen library"); break; +#endif // EIGEN_INSTALLED + case e_ap_analytical_solver::LP_B2B: +#ifdef EIGEN_INSTALLED + return std::make_unique(netlist, + device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity); +#else + VPR_FATAL_ERROR(VPR_ERROR_AP, + "LP B2B Solver requires the Eigen library"); + break; #endif // EIGEN_INSTALLED default: VPR_FATAL_ERROR(VPR_ERROR_AP, @@ -56,16 +91,25 @@ std::unique_ptr make_analytical_solver(e_analytical_solver sol return nullptr; } -AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist) - : netlist_(netlist), - blk_id_to_row_id_(netlist.blocks().size(), APRowId::INVALID()), - row_id_to_blk_id_(netlist.blocks().size(), APBlockId::INVALID()) { +AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) + : netlist_(netlist) + , blk_id_to_row_id_(netlist.blocks().size(), APRowId::INVALID()) + , row_id_to_blk_id_(netlist.blocks().size(), APBlockId::INVALID()) + , net_weights_(netlist.nets().size(), 1.0f) + , log_verbosity_(log_verbosity) { // Get the number of moveable blocks in the netlist and create a unique // row ID from [0, num_moveable_blocks) for each moveable block in the // netlist. num_moveable_blocks_ = 0; + num_fixed_blocks_ = 0; size_t current_row_id = 0; for (APBlockId blk_id : netlist.blocks()) { + if (netlist.block_mobility(blk_id) == APBlockMobility::FIXED) + num_fixed_blocks_++; if (netlist.block_mobility(blk_id) != APBlockMobility::MOVEABLE) continue; APRowId new_row_id = APRowId(current_row_id); @@ -74,6 +118,21 @@ AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist) current_row_id++; num_moveable_blocks_++; } + + if (pre_cluster_timing_manager.is_valid()) { + for (APNetId net_id : netlist.nets()) { + // Get the atom net associated with the given AP net. When + // constructing the AP netlist, we happen to set the name of each + // AP net to the same name as the atom net that generated them! + // TODO: Create a proper lookup structure to go from the AP Netlist + // back to the Atom Netlist. + AtomNetId atom_net_id = atom_netlist.find_net(netlist.net_name(net_id)); + VTR_ASSERT(atom_net_id.is_valid()); + float crit = pre_cluster_timing_manager.calc_net_setup_criticality(atom_net_id, atom_netlist); + + net_weights_[net_id] = ap_timing_tradeoff * crit + (1.0f - ap_timing_tradeoff); + } + } } #ifdef EIGEN_INSTALLED @@ -155,10 +214,10 @@ void QPHybridSolver::init_linear_system() { } // Initialize the linear system with zeros. - size_t num_variables = num_moveable_blocks_ + num_star_nodes; - A_sparse = Eigen::SparseMatrix(num_variables, num_variables); - b_x = Eigen::VectorXd::Zero(num_variables); - b_y = Eigen::VectorXd::Zero(num_variables); + num_variables_ = num_moveable_blocks_ + num_star_nodes; + A_sparse = Eigen::SparseMatrix(num_variables_, num_variables_); + b_x = Eigen::VectorXd::Zero(num_variables_); + b_y = Eigen::VectorXd::Zero(num_variables_); // Create a list of triplets that will be used to create the sparse // coefficient matrix. This is the method recommended by Eigen to initialize @@ -169,13 +228,11 @@ void QPHybridSolver::init_linear_system() { std::vector> tripletList; // Reserve enough space for the triplets. This is just to help with // performance. - // This is an over-estimate that assumes that each net connnects to all - // moveable blocks using a star node. // TODO: This can be made more space-efficient by getting the average fanout // of all nets in the APNetlist. Ideally this should be not enough // space, but be within a constant factor. size_t num_nets = netlist_.nets().size(); - tripletList.reserve(num_moveable_blocks_ * num_nets); + tripletList.reserve(num_nets); // Create the connections using a hybrid connection model of the star and // clique connnection models. @@ -183,12 +240,15 @@ void QPHybridSolver::init_linear_system() { for (APNetId net_id : netlist_.nets()) { size_t num_pins = netlist_.net_pins(net_id).size(); VTR_ASSERT_DEBUG(num_pins > 1); + + double net_weight = net_weights_[net_id]; + if (num_pins > star_num_pins_threshold) { // Create a star node and connect each block in the net to the star // node. // Using the weight from FastPlace // TODO: Investigate other weight terms. - double w = static_cast(num_pins) / static_cast(num_pins - 1); + double w = net_weight * static_cast(num_pins) / static_cast(num_pins - 1); size_t star_node_id = num_moveable_blocks_ + star_node_offset; for (APPinId pin_id : netlist_.net_pins(net_id)) { APBlockId blk_id = netlist_.pin_block(pin_id); @@ -202,7 +262,7 @@ void QPHybridSolver::init_linear_system() { // exactly once to every other block in the net. // Using the weight from FastPlace // TODO: Investigate other weight terms. - double w = 1.0 / static_cast(num_pins - 1); + double w = net_weight * 1.0 / static_cast(num_pins - 1); for (size_t ipin_idx = 0; ipin_idx < num_pins; ipin_idx++) { APPinId first_pin_id = netlist_.net_pin(net_id, ipin_idx); APBlockId first_blk_id = netlist_.pin_block(first_pin_id); @@ -238,42 +298,17 @@ void QPHybridSolver::init_linear_system() { A_sparse.setFromTriplets(tripletList.begin(), tripletList.end()); } -/** - * @brief Helper method to update the linear system with anchors to the current - * partial placement. - * - * For each moveable block (with row = i) in the netlist: - * A[i][i] = A[i][i] + coeff_pseudo_anchor; - * b[i] = b[i] + pos[block(i)] * coeff_pseudo_anchor; - * Where coeff_pseudo_anchor grows with each iteration. - * - * This is basically a fast way of adding a connection between all moveable - * blocks in the netlist and their target fixed placement location. - * - * See add_connection_to_system. - * - * @param A_sparse_diff The ceofficient matrix to update. - * @param b_x_diff The x-dimension constant vector to update. - * @param b_y_diff The y-dimension constant vector to update. - * @param p_placement The location the moveable blocks should be anchored - * to. - * @param num_moveable_blocks The number of moveable blocks in the netlist. - * @param row_id_to_blk_id Lookup for the row id from the APBlock Id. - * @param iteration The current iteration of the Global Placer. - */ -static inline void update_linear_system_with_anchors( - Eigen::SparseMatrix &A_sparse_diff, - Eigen::VectorXd &b_x_diff, - Eigen::VectorXd &b_y_diff, - PartialPlacement& p_placement, - size_t num_moveable_blocks, - vtr::vector row_id_to_blk_id, - unsigned iteration) { +void QPHybridSolver::update_linear_system_with_anchors( + Eigen::SparseMatrix& A_sparse_diff, + Eigen::VectorXd& b_x_diff, + Eigen::VectorXd& b_y_diff, + PartialPlacement& p_placement, + unsigned iteration) { // Anchor weights grow exponentially with iteration. - double coeff_pseudo_anchor = 0.01 * std::exp((double)iteration/5); - for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks; row_id_idx++) { + double coeff_pseudo_anchor = anchor_weight_mult_ * std::exp((double)iteration / anchor_weight_exp_fac_); + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { APRowId row_id = APRowId(row_id_idx); - APBlockId blk_id = row_id_to_blk_id[row_id]; + APBlockId blk_id = row_id_to_blk_id_[row_id]; double pseudo_w = coeff_pseudo_anchor; A_sparse_diff.coeffRef(row_id_idx, row_id_idx) += pseudo_w; b_x_diff(row_id_idx) += pseudo_w * p_placement.block_x_locs[blk_id]; @@ -281,7 +316,54 @@ static inline void update_linear_system_with_anchors( } } -void QPHybridSolver::solve(unsigned iteration, PartialPlacement &p_placement) { +void QPHybridSolver::init_guesses(const DeviceGrid& device_grid) { + // If the number of fixed blocks is zero, initialized the guesses to the + // center of the device. + if (num_fixed_blocks_ == 0) { + guess_x = Eigen::VectorXd::Constant(num_variables_, device_grid.width() / 2.0); + guess_y = Eigen::VectorXd::Constant(num_variables_, device_grid.height() / 2.0); + return; + } + + // Compute the centroid of all fixed blocks in the netlist. + t_flat_pl_loc centroid({0.0f, 0.0f, 0.0f}); + unsigned num_blks_summed = 0; + for (APBlockId blk_id : netlist_.blocks()) { + // We only get the centroid of fixed blocks since these are the only + // blocks with positions that we know. + if (netlist_.block_mobility(blk_id) != APBlockMobility::FIXED) + continue; + // Get the flat location of the fixed block. + APFixedBlockLoc fixed_blk_loc = netlist_.block_loc(blk_id); + VTR_ASSERT_SAFE(fixed_blk_loc.x != APFixedBlockLoc::UNFIXED_DIM); + VTR_ASSERT_SAFE(fixed_blk_loc.y != APFixedBlockLoc::UNFIXED_DIM); + VTR_ASSERT_SAFE(fixed_blk_loc.layer_num != APFixedBlockLoc::UNFIXED_DIM); + t_flat_pl_loc flat_blk_loc; + flat_blk_loc.x = fixed_blk_loc.x; + flat_blk_loc.y = fixed_blk_loc.y; + flat_blk_loc.layer = fixed_blk_loc.layer_num; + // Accumulate into the centroid. + centroid += flat_blk_loc; + num_blks_summed++; + } + // Divide the sum by the number of fixed blocks. + VTR_ASSERT_SAFE(num_blks_summed == num_fixed_blocks_); + centroid /= static_cast(num_blks_summed); + + // Set the guesses to the centroid location. + guess_x = Eigen::VectorXd::Constant(num_variables_, centroid.x); + guess_y = Eigen::VectorXd::Constant(num_variables_, centroid.y); +} + +void QPHybridSolver::solve(unsigned iteration, PartialPlacement& p_placement) { + // In the first iteration, if the number of fixed blocks is 0, set the + // placement to be equal to the guess. The solver below will just set the + // solution to the zero vector if we do not set it to the guess directly. + if (iteration == 0 && num_fixed_blocks_ == 0) { + store_solution_into_placement(guess_x, guess_y, p_placement); + return; + } + // Create a temporary linear system which will contain the original linear // system which may be updated to include the anchor points. Eigen::SparseMatrix A_sparse_diff = Eigen::SparseMatrix(A_sparse); @@ -292,30 +374,41 @@ void QPHybridSolver::solve(unsigned iteration, PartialPlacement &p_placement) { // anchor-points (fixed block positions). if (iteration != 0) { update_linear_system_with_anchors(A_sparse_diff, b_x_diff, b_y_diff, - p_placement, num_moveable_blocks_, - row_id_to_blk_id_, iteration); + p_placement, iteration); } // Verify that the constant vectors are valid. - VTR_ASSERT_DEBUG(!b_x_diff.hasNaN() && "b_x has NaN!"); - VTR_ASSERT_DEBUG(!b_y_diff.hasNaN() && "b_y has NaN!"); + VTR_ASSERT_SAFE_MSG(!b_x_diff.hasNaN(), "b_x has NaN!"); + VTR_ASSERT_SAFE_MSG(!b_y_diff.hasNaN(), "b_y has NaN!"); // Set up the ConjugateGradient Solver using the coefficient matrix. // TODO: can change cg.tolerance to increase performance when needed // - This tolerance may need to be a function of the number of nets. // - Instead of normalizing the fixed blocks, the tolerance can be scaled // by the size of the device. - Eigen::ConjugateGradient, Eigen::Lower|Eigen::Upper> cg; + Eigen::ConjugateGradient, Eigen::Lower | Eigen::Upper> cg; cg.compute(A_sparse_diff); VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at compute!"); // Use the solver to solve for x and y using the constant vectors - // TODO: Use solve with guess to make this faster. Use the previous placement - // as a guess. - Eigen::VectorXd x = cg.solve(b_x_diff); + Eigen::VectorXd x = cg.solveWithGuess(b_x_diff, guess_x); + total_num_cg_iters_ += cg.iterations(); VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at solving b_x!"); - Eigen::VectorXd y = cg.solve(b_y_diff); + Eigen::VectorXd y = cg.solveWithGuess(b_y_diff, guess_y); + total_num_cg_iters_ += cg.iterations(); VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at solving b_y!"); // Write the results back into the partial placement object. + store_solution_into_placement(x, y, p_placement); + + // Update the guess. The guess for the next iteration is the solution in + // this iteration. + guess_x = x; + guess_y = y; +} + +void QPHybridSolver::store_solution_into_placement(const Eigen::VectorXd& x_soln, + const Eigen::VectorXd& y_soln, + PartialPlacement& p_placement) { + // NOTE: The first [0, num_moveable_blocks_) rows always represent the // moveable APBlocks. The star nodes always come after and are ignored // in the solution. @@ -324,10 +417,430 @@ void QPHybridSolver::solve(unsigned iteration, PartialPlacement &p_placement) { APBlockId blk_id = row_id_to_blk_id_[row_id]; VTR_ASSERT_DEBUG(blk_id.is_valid()); VTR_ASSERT_DEBUG(netlist_.block_mobility(blk_id) == APBlockMobility::MOVEABLE); - p_placement.block_x_locs[blk_id] = x[row_id_idx]; - p_placement.block_y_locs[blk_id] = y[row_id_idx]; + // Due to the iterative nature of CG, it is possible for the solver to + // overstep 0 and return a negative number by an incredibly small margin. + // Clamp the number to 0 in this case. + // TODO: Should investigate good bounds on this, the bounds below were + // chosen since any difference higher than 1e-9 would concern me. + double x_pos = x_soln[row_id_idx]; + if (x_pos < 0.0) { + VTR_ASSERT_SAFE(std::abs(x_pos) < negative_soln_tolerance_); + x_pos = 0.0; + } + double y_pos = y_soln[row_id_idx]; + if (y_pos < 0.0) { + VTR_ASSERT_SAFE(std::abs(y_pos) < negative_soln_tolerance_); + y_pos = 0.0; + } + p_placement.block_x_locs[blk_id] = x_pos; + p_placement.block_y_locs[blk_id] = y_pos; } } -#endif // EIGEN_INSTALLED +void QPHybridSolver::print_statistics() { + VTR_LOG("QP-Hybrid Solver Statistics:\n"); + VTR_LOG("\tTotal number of CG iterations: %u\n", total_num_cg_iters_); +} + +void B2BSolver::solve(unsigned iteration, PartialPlacement& p_placement) { + // Store an initial placement into the p_placement object as a starting point + // for the B2B solver. + if (iteration == 0) { + // If there are no fixed blocks, running bound2bound will always yield + // the trivial solution (all blocks on top of each other anywhere on the + // device). Skip having to solve for this by just putting all the blocks + // at the center of the device. + // TODO: This can be further improved by using the average compatible + // tile location for each AP block. The center is just an + // approximation. + if (num_fixed_blocks_ == 0) { + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + p_placement.block_x_locs[blk_id] = device_grid_width_ / 2.0; + p_placement.block_y_locs[blk_id] = device_grid_height_ / 2.0; + } + block_x_locs_solved = p_placement.block_x_locs; + block_y_locs_solved = p_placement.block_y_locs; + return; + } + + // In the first iteration, we have no prior information. + // Run the intial placer to get a first guess. + switch (initial_placement_ty_) { + case e_initial_placement_type::LeastDense: + initialize_placement_least_dense(p_placement); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_AP, "Unknown initial placement type"); + } + } else { + // After the first iteration, the prior solved solution will serve as + // the best starting points for the bounds. + + // Save the legalized solution; we need it for the anchors. + block_x_locs_legalized = p_placement.block_x_locs; + block_y_locs_legalized = p_placement.block_y_locs; + + // Store last solved position into p_placement for b2b model + p_placement.block_x_locs = block_x_locs_solved; + p_placement.block_y_locs = block_y_locs_solved; + } + + // Run the B2B solver using p_placement as a starting point. + b2b_solve_loop(iteration, p_placement); + + // Store the solved solutions for the next iteration. + block_x_locs_solved = p_placement.block_x_locs; + block_y_locs_solved = p_placement.block_y_locs; +} + +void B2BSolver::initialize_placement_least_dense(PartialPlacement& p_placement) { + // Find a gap for the blocks such that each block can fit onto the device + // if they were evenly spaced by this gap. + double gap = std::sqrt(device_grid_height_ * device_grid_width_ / static_cast(num_moveable_blocks_)); + + // Assuming this gap, get how many columns/rows of blocks there will be. + size_t cols = std::ceil(device_grid_width_ / gap); + size_t rows = std::ceil(device_grid_height_ / gap); + + // Spread the blocks at these grid coordinates. + for (size_t r = 0; r <= rows; r++) { + for (size_t c = 0; c <= cols; c++) { + size_t i = r * cols + c; + if (i >= num_moveable_blocks_) + break; + APRowId row_id = APRowId(i); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + p_placement.block_x_locs[blk_id] = c * gap; + p_placement.block_y_locs[blk_id] = r * gap; + } + } +} + +void B2BSolver::b2b_solve_loop(unsigned iteration, PartialPlacement& p_placement) { + // Set up the guesses for x and y to help CG converge faster + // A good guess for B2B is the last solved solution. + Eigen::VectorXd x_guess(num_moveable_blocks_); + Eigen::VectorXd y_guess(num_moveable_blocks_); + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + x_guess(row_id_idx) = p_placement.block_x_locs[blk_id]; + y_guess(row_id_idx) = p_placement.block_y_locs[blk_id]; + } + + // Create a timer to keep track of how long each part of the solver take. + vtr::Timer runtime_timer; + + // To solve B2B, we need to do the following: + // 1) Set up the connectivity matrix and constant vectors based on the + // bounds of the current solution (stored in p_placement). + // 2) Solve the system of equations using CG and store the result into + // p_placement. + // 3) Repeat. Note: We need to repeat step 1 and 2 iteratively since + // the bounds are likely to have changed after step 2. + // We stop when it looks like the placement is converging (the change in + // HPWL is sufficiently small for a few iterations). + double prev_hpwl = std::numeric_limits::max(); + double curr_hpwl = prev_hpwl; + unsigned num_convergence = 0; + for (unsigned counter = 0; counter < max_num_bound_updates_; counter++) { + VTR_LOGV(log_verbosity_ >= 10, + "\tPlacement HPWL in b2b loop: %f\n", + p_placement.get_hpwl(netlist_)); + + // Set up the linear system, including anchor points. + float build_linear_system_start_time = runtime_timer.elapsed_sec(); + init_linear_system(p_placement); + if (iteration != 0) + update_linear_system_with_anchors(iteration); + total_time_spent_building_linear_system_ += runtime_timer.elapsed_sec() - build_linear_system_start_time; + VTR_ASSERT_SAFE_MSG(!b_x.hasNaN(), "b_x has NaN!"); + VTR_ASSERT_SAFE_MSG(!b_y.hasNaN(), "b_y has NaN!"); + VTR_ASSERT_SAFE_MSG((b_x.array() >= 0).all(), "b_x has NaN!"); + VTR_ASSERT_SAFE_MSG((b_y.array() >= 0).all(), "b_y has NaN!"); + + // Build the solvers for each dimension. + // Note: Since we have two different connectivity matrices, we need to + // different CG solver objects. + float solve_linear_system_start_time = runtime_timer.elapsed_sec(); + Eigen::VectorXd x, y; + Eigen::ConjugateGradient, Eigen::Lower | Eigen::Upper> cg_x; + Eigen::ConjugateGradient, Eigen::Lower | Eigen::Upper> cg_y; + cg_x.compute(A_sparse_x); + cg_y.compute(A_sparse_y); + VTR_ASSERT_SAFE_MSG(cg_x.info() == Eigen::Success, "Conjugate Gradient failed at compute for A_x!"); + VTR_ASSERT_SAFE_MSG(cg_y.info() == Eigen::Success, "Conjugate Gradient failed at compute for A_y!"); + cg_x.setMaxIterations(max_cg_iterations_); + cg_y.setMaxIterations(max_cg_iterations_); + + // Solve the x dimension. + x = cg_x.solveWithGuess(b_x, x_guess); + total_num_cg_iters_ += cg_x.iterations(); + VTR_LOGV(log_verbosity_ >= 20, "\t\tNum CG-x iter: %zu\n", cg_x.iterations()); + + // Solve the y dimension. + y = cg_y.solveWithGuess(b_y, y_guess); + total_num_cg_iters_ += cg_y.iterations(); + VTR_LOGV(log_verbosity_ >= 20, "\t\tNum CG-y iter: %zu\n", cg_y.iterations()); + + total_time_spent_solving_linear_system_ += runtime_timer.elapsed_sec() - solve_linear_system_start_time; + + // Save the result into the partial placement object. + store_solution_into_placement(x, y, p_placement); + + // If the current HPWL is larger than the previous HPWL (i.e. the HPWL + // got worst since last B2B iter) or the gap between the two solutions + // is small. Increment a counter. + // TODO: Since, in theory, the HPWL could get worst due to numerical + // reasons, should we save the best result? May not be worth it... + curr_hpwl = p_placement.get_hpwl(netlist_); + double target_gap = b2b_convergence_gap_fac_ * curr_hpwl; + if (curr_hpwl > prev_hpwl || std::abs(curr_hpwl - prev_hpwl) < target_gap) + num_convergence++; + // If the HPWL got close enough times, stop. This is to allow the HPWL + // to "bounce", which can happen as it converges. + // This trades-off quality for run time. + if (num_convergence >= target_num_b2b_convergences_) + break; + prev_hpwl = curr_hpwl; + + // Update the guesses with the most recent answer + x_guess = x; + y_guess = y; + } +} + +namespace { +/** + * @brief Struct used to hold the bounding blocks of an AP net. + */ +struct APNetBounds { + /// @brief The leftmost block in the net. + APBlockId min_x_blk; + /// @brief The rightmost block in the net. + APBlockId max_x_blk; + /// @brief The bottom-most block in the net. + APBlockId min_y_blk; + /// @brief The top-most block in the net. + APBlockId max_y_blk; +}; + +} // namespace + +/** + * @brief Helper method to get the unique bounding blocks of a given net. + * + * In the B2B model, we do not want the same block to be the bounds in a given + * dimension. Therefore, if all blocks share the same x location for example, + * different bounds will be chosen for the x dimension. + */ +static inline APNetBounds get_unique_net_bounds(APNetId net_id, + const PartialPlacement& p_placement, + const APNetlist& netlist) { + VTR_ASSERT_SAFE_MSG(netlist.net_pins(net_id).size() != 0, + "Cannot get the bounds of an empty net"); + VTR_ASSERT_SAFE_MSG(netlist.net_pins(net_id).size() >= 2, + "Expect nets to have at least 2 pins"); + + APNetBounds bounds; + double max_x_pos = std::numeric_limits::lowest(); + double min_x_pos = std::numeric_limits::max(); + double max_y_pos = std::numeric_limits::lowest(); + double min_y_pos = std::numeric_limits::max(); + + for (APPinId pin_id : netlist.net_pins(net_id)) { + // Update the bounds based on the position of the block that has this pin. + APBlockId blk_id = netlist.pin_block(pin_id); + double x_pos = p_placement.block_x_locs[blk_id]; + double y_pos = p_placement.block_y_locs[blk_id]; + if (x_pos < min_x_pos) { + min_x_pos = x_pos; + bounds.min_x_blk = blk_id; + } + if (y_pos < min_y_pos) { + min_y_pos = y_pos; + bounds.min_y_blk = blk_id; + } + if (x_pos > max_x_pos) { + max_x_pos = x_pos; + bounds.max_x_blk = blk_id; + } + if (y_pos > max_y_pos) { + max_y_pos = y_pos; + bounds.max_y_blk = blk_id; + } + + // In the case of a tie, we do not want to have the same blocks as bounds. + // If there is a tie for the max position, and the current min bound is + // not this block, take the incoming block. + if (x_pos == max_x_pos && bounds.min_x_blk != blk_id) { + max_x_pos = x_pos; + bounds.max_x_blk = blk_id; + } + if (y_pos == max_y_pos && bounds.min_y_blk != blk_id) { + max_y_pos = y_pos; + bounds.max_y_blk = blk_id; + } + } + + // Ensure the same block is set as the bounds. + // If there is not a bug in the above code, then this could imply that a + // net only connects to a single APBlock, which does not make sense in this + // context. + VTR_ASSERT_SAFE(bounds.min_x_blk != bounds.max_x_blk); + VTR_ASSERT_SAFE(bounds.min_y_blk != bounds.max_y_blk); + + return bounds; +} + +void B2BSolver::add_connection_to_system(APBlockId first_blk_id, + APBlockId second_blk_id, + size_t num_pins, + double net_w, + const vtr::vector& blk_locs, + std::vector>& triplet_list, + Eigen::VectorXd& b) { + // To make the code below simpler, we assume that the first block is always + // moveable. + if (netlist_.block_mobility(first_blk_id) != APBlockMobility::MOVEABLE) { + if (netlist_.block_mobility(second_blk_id) != APBlockMobility::MOVEABLE) { + // If both blocks are fixed, do not connect them. + return; + } + // If the first block is fixed and the second block is moveable, swap them. + std::swap(first_blk_id, second_blk_id); + } + + // Compute the weight of the connection. + // From the Kraftwerk2 paper: + // w = (2 / (P - 1)) * (1 / distance) + // + // epsilon is needed to prevent numerical instability. If two nodes are on top of each other. + // The denominator of weight is zero, which causes infinity term in the matrix. Another way of + // interpreting epsilon is the minimum distance two nodes are considered to be in placement. + double dist = std::max(std::abs(blk_locs[first_blk_id] - blk_locs[second_blk_id]), distance_epsilon_); + double w = net_w * (2.0 / static_cast(num_pins - 1)) * (1.0 / dist); + + // Update the connectivity matrix and the constant vector. + // This is similar to how connections are added for the quadratic formulation. + size_t first_row_id = (size_t)blk_id_to_row_id_[first_blk_id]; + if (netlist_.block_mobility(second_blk_id) == APBlockMobility::MOVEABLE) { + size_t second_row_id = (size_t)blk_id_to_row_id_[second_blk_id]; + triplet_list.emplace_back(first_row_id, first_row_id, w); + triplet_list.emplace_back(second_row_id, second_row_id, w); + triplet_list.emplace_back(first_row_id, second_row_id, -w); + triplet_list.emplace_back(second_row_id, first_row_id, -w); + } else { + triplet_list.emplace_back(first_row_id, first_row_id, w); + b(first_row_id) += w * blk_locs[second_blk_id]; + } +} + +void B2BSolver::init_linear_system(PartialPlacement& p_placement) { + // Reset the linear system + A_sparse_x = Eigen::SparseMatrix(num_moveable_blocks_, num_moveable_blocks_); + A_sparse_y = Eigen::SparseMatrix(num_moveable_blocks_, num_moveable_blocks_); + b_x = Eigen::VectorXd::Zero(num_moveable_blocks_); + b_y = Eigen::VectorXd::Zero(num_moveable_blocks_); + + // Create triplet lists to store the sparse positions to update and reserve + // space for them. + size_t num_nets = netlist_.nets().size(); + std::vector> triplet_list_x; + triplet_list_x.reserve(num_nets); + std::vector> triplet_list_y; + triplet_list_y.reserve(num_nets); + + for (APNetId net_id : netlist_.nets()) { + size_t num_pins = netlist_.net_pins(net_id).size(); + VTR_ASSERT_SAFE_MSG(num_pins > 1, "net must have at least 2 pins"); + + double net_w = net_weights_[net_id]; + + // Find the bounding blocks + APNetBounds net_bounds = get_unique_net_bounds(net_id, p_placement, netlist_); + + // Add an edge from every block to their bounds (ignoring the bounds + // themselves for now). + // FIXME: If one block has multiple pins, it may connect to the bounds + // multiple times. Should investigate the effect of this. + for (APPinId pin_id : netlist_.net_pins(net_id)) { + APBlockId blk_id = netlist_.pin_block(pin_id); + if (blk_id != net_bounds.max_x_blk && blk_id != net_bounds.min_x_blk) { + add_connection_to_system(blk_id, net_bounds.max_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(blk_id, net_bounds.min_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); + } + if (blk_id != net_bounds.max_y_blk && blk_id != net_bounds.min_y_blk) { + add_connection_to_system(blk_id, net_bounds.max_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); + add_connection_to_system(blk_id, net_bounds.min_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); + } + } + + // Connect the bounds to each other. Its just easier to put these here + // instead of in the for loop above. + add_connection_to_system(net_bounds.max_x_blk, net_bounds.min_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(net_bounds.max_y_blk, net_bounds.min_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); + } + + // Build the sparse connectivity matrices from the triplets. + A_sparse_x.setFromTriplets(triplet_list_x.begin(), triplet_list_x.end()); + A_sparse_y.setFromTriplets(triplet_list_y.begin(), triplet_list_y.end()); +} + +// This function adds anchors for legalized solution. Anchors are treated as fixed node, +// each connecting to a movable node. Number of nodes in a anchor net is always 2. +void B2BSolver::update_linear_system_with_anchors(unsigned iteration) { + VTR_ASSERT_SAFE_MSG(iteration != 0, + "no fixed solution to anchor to in the first iteration"); + // Get the anchor weight based on the iteration number. We want the anchor + // weights to get stronger as we get later in global placement. Found that + // an exponential weight term worked well for this. + double coeff_pseudo_anchor = anchor_weight_mult_ * std::exp((double)iteration / anchor_weight_exp_fac_); + + // Add an anchor for each moveable block to its solved position. + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + double pseudo_w_x = coeff_pseudo_anchor * 2.0; + double pseudo_w_y = coeff_pseudo_anchor * 2.0; + A_sparse_x.coeffRef(row_id_idx, row_id_idx) += pseudo_w_x; + A_sparse_y.coeffRef(row_id_idx, row_id_idx) += pseudo_w_y; + b_x(row_id_idx) += pseudo_w_x * block_x_locs_legalized[blk_id]; + b_y(row_id_idx) += pseudo_w_y * block_y_locs_legalized[blk_id]; + } +} + +void B2BSolver::store_solution_into_placement(Eigen::VectorXd& x_soln, + Eigen::VectorXd& y_soln, + PartialPlacement& p_placement) { + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + // Since we are capping the number of iterations, the solver may not + // have enough time to converge on a solution that is on the device. + // We just clamp the solution to zero for now. + // TODO: Should handle this better. If the solution is very negative + // it may indicate a bug. + if (x_soln[row_id_idx] < 0.0) + x_soln[row_id_idx] = 0.0; + if (y_soln[row_id_idx] < 0.0) + y_soln[row_id_idx] = 0.0; + + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + p_placement.block_x_locs[blk_id] = x_soln[row_id_idx]; + p_placement.block_y_locs[blk_id] = y_soln[row_id_idx]; + } +} + +void B2BSolver::print_statistics() { + VTR_LOG("B2B Solver Statistics:\n"); + VTR_LOG("\tTotal number of CG iterations: %u\n", total_num_cg_iters_); + VTR_LOG("\tTotal time spent building linear system: %g seconds\n", + total_time_spent_building_linear_system_); + VTR_LOG("\tTotal time spent solving linear system: %g seconds\n", + total_time_spent_solving_linear_system_); +} + +#endif // EIGEN_INSTALLED diff --git a/vpr/src/analytical_place/analytical_solver.h b/vpr/src/analytical_place/analytical_solver.h index 33397a554d1..2d748e2a493 100644 --- a/vpr/src/analytical_place/analytical_solver.h +++ b/vpr/src/analytical_place/analytical_solver.h @@ -9,7 +9,9 @@ #pragma once #include -#include "ap_netlist_fwd.h" +#include "ap_flow_enums.h" +#include "ap_netlist.h" +#include "device_grid.h" #include "vtr_strong_id.h" #include "vtr_vector.h" @@ -24,20 +26,13 @@ // Pop the GCC diagnostics state back to what it was before. #pragma GCC diagnostic pop -#endif // EIGEN_INSTALLED +#endif // EIGEN_INSTALLED // Forward declarations class PartialPlacement; class APNetlist; - -/** - * @brief Enumeration of all of the solvers currently implemented in VPR. - * - * NOTE: More are coming. - */ -enum class e_analytical_solver { - QP_HYBRID // A solver which optimizes the quadratic HPWL of the design. -}; +class AtomNetlist; +class PreClusterTimingManager; /** * @brief A strong ID for the rows in a matrix used during solving. @@ -58,7 +53,7 @@ typedef vtr::StrongId APRowId; * compare different solvers. */ class AnalyticalSolver { -public: + public: virtual ~AnalyticalSolver() {} /** @@ -67,7 +62,11 @@ class AnalyticalSolver { * Initializes the internal data members of the base class which are useful * for all solvers. */ - AnalyticalSolver(const APNetlist &netlist); + AnalyticalSolver(const APNetlist& netlist, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); /** * @brief Run an iteration of the solver using the given partial placement @@ -87,10 +86,17 @@ class AnalyticalSolver { * @param p_placement A "hint" to a legal solution that the solver should * try and be like. */ - virtual void solve(unsigned iteration, PartialPlacement &p_placement) = 0; + virtual void solve(unsigned iteration, PartialPlacement& p_placement) = 0; -protected: + /** + * @brief Print statistics on the analytical solver. + * + * This is expected to be called after global placement to collect cummulative + * information on how the solver performed. + */ + virtual void print_statistics() = 0; + protected: /// @brief The APNetlist the solver is optimizing over. It is implied that /// the netlist is not being modified during global placement. const APNetlist& netlist_; @@ -99,6 +105,9 @@ class AnalyticalSolver { /// when allocating matrices. size_t num_moveable_blocks_ = 0; + /// @brief The number of fixed blocks in the netlist. + size_t num_fixed_blocks_ = 0; + /// @brief A lookup between a moveable APBlock and its linear ID from /// [0, num_moveable_blocks). Fixed blocks will return an invalid row /// ID. This is useful when knowing which row in the matrix @@ -109,13 +118,27 @@ class AnalyticalSolver { /// APBlock it represents. useful when getting the results from the /// solver. vtr::vector row_id_to_blk_id_; + + /// @brief The base weight of each net in the AP netlist. This weight can + /// be used to make the solver more interested in some nets over + /// others. These weights can be any positive value, but are often + /// between 0 and 1. + vtr::vector net_weights_; + + /// @brief The verbosity of log messages in the Analytical Solver. + int log_verbosity_; }; /** * @brief A factory method which creates an Analytical Solver of the given type. */ -std::unique_ptr make_analytical_solver(e_analytical_solver solver_type, - const APNetlist &netlist); +std::unique_ptr make_analytical_solver(e_ap_analytical_solver solver_type, + const APNetlist& netlist, + const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); // The Eigen library is used to solve matrix equations in the following solvers. // The solver cannot be built if Eigen is not installed. @@ -145,7 +168,7 @@ std::unique_ptr make_analytical_solver(e_analytical_solver sol * https://doi.org/10.1109/TCAD.2005.846365 */ class QPHybridSolver : public AnalyticalSolver { -private: + private: /// @brief The threshold for the number of pins a net will have to use the /// Star or Clique net models. If the number of pins is larger /// than this number, a star node will be created. @@ -156,6 +179,29 @@ class QPHybridSolver : public AnalyticalSolver { /// sparse. static constexpr size_t star_num_pins_threshold = 3; + // The following constants are used to configure the anchor weighting. + // The weights of anchors grow exponentially each iteration by the following + // function: + // anchor_w = anchor_weight_mult_ * e^(iter / anchor_weight_exp_fac_) + // The numbers below were empircally found to work well. + + /// @brief Multiplier for the anchorweight. The smaller this number is, the + /// weaker the anchors will be at the start. + static constexpr double anchor_weight_mult_ = 0.001; + + /// @brief Factor for controlling the growth of the exponential term in the + /// weight factor function. Larger numbers will cause the anchor + /// weights to grow slower. + static constexpr double anchor_weight_exp_fac_ = 5.0; + + /// @brief Due to the iterative nature of Conjugate Gradient method, the + /// solver may overstep 0 to give a slightly negative solution. This + /// is ok, and we can just clamp the position to 0. However, negative + /// values that are too large may be indicative of an issue in the + /// formulation. This value is how negative we tolerate the positions + /// to be. + static constexpr double negative_soln_tolerance_ = 1e-9; + /** * @brief Initializes the linear system of Ax = b_x and Ay = b_y based on * the APNetlist and the fixed APBlock locations. @@ -166,6 +212,51 @@ class QPHybridSolver : public AnalyticalSolver { */ void init_linear_system(); + /** + * @brief Intializes the guesses which will be used in the solver. + * + * The guesses will be used as starting points for the CG solver. The better + * these guesses are, the faster the solver will converge. + */ + void init_guesses(const DeviceGrid& device_grid); + + /** + * @brief Helper method to update the linear system with anchors to the + * current partial placement. + * + * For each moveable block (with row = i) in the netlist: + * A[i][i] = A[i][i] + coeff_pseudo_anchor; + * b[i] = b[i] + pos[block(i)] * coeff_pseudo_anchor; + * Where coeff_pseudo_anchor grows with each iteration. + * + * This is basically a fast way of adding a connection between all moveable + * blocks in the netlist and their target fixed placement location. + * + * See add_connection_to_system. + * + * @param A_sparse_diff The ceofficient matrix to update. + * @param b_x_diff The x-dimension constant vector to update. + * @param b_y_diff The y-dimension constant vector to update. + * @param p_placement The location the moveable blocks should be + * anchored to. + * @param num_moveable_blocks The number of moveable blocks in the netlist. + * @param row_id_to_blk_id Lookup for the row id from the APBlock Id. + * @param iteration The current iteration of the Global Placer. + */ + void update_linear_system_with_anchors(Eigen::SparseMatrix& A_sparse_diff, + Eigen::VectorXd& b_x_diff, + Eigen::VectorXd& b_y_diff, + PartialPlacement& p_placement, + unsigned iteration); + + /** + * @brief Store the x and y solutions in Eigen's vectors into the partial + * placement object. + */ + void store_solution_into_placement(const Eigen::VectorXd& x_soln, + const Eigen::VectorXd& y_soln, + PartialPlacement& p_placement); + // The following variables represent the linear system without any anchor // points. These are filled in the constructor and never modified. // When the anchor-points are taken into consideration, the diagonal of the @@ -181,19 +272,39 @@ class QPHybridSolver : public AnalyticalSolver { Eigen::VectorXd b_x; /// @brief The constant vector in the y dimension for the linear system. Eigen::VectorXd b_y; + /// @brief The number of variables in the solver. This is the sum of the + /// number of moveable blocks in the netlist and the number of star + /// nodes that exist. + size_t num_variables_ = 0; -public: + /// @brief The current guess for the x positions of the blocks. + Eigen::VectorXd guess_x; + /// @brief The current guess for the y positions of the blocks. + Eigen::VectorXd guess_y; + /// @brief The total number of CG iterations this solver has performed so far. + unsigned total_num_cg_iters_ = 0; + + public: /** * @brief Constructor of the QPHybridSolver * * Initializes internal data and constructs the initial linear system. */ - QPHybridSolver(const APNetlist& netlist) : AnalyticalSolver(netlist) { + QPHybridSolver(const APNetlist& netlist, + const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) + : AnalyticalSolver(netlist, atom_netlist, pre_cluster_timing_manager, ap_timing_tradeoff, log_verbosity) { // Initializing the linear system only depends on the netlist and fixed // block locations. Both are provided by the netlist, allowing this to // be initialized in the constructor. init_linear_system(); + + // Initialize the guesses for the first iteration. + init_guesses(device_grid); } /** @@ -216,8 +327,288 @@ class QPHybridSolver : public AnalyticalSolver { * @param p_placement A "guess" solution. The result will be written into * this object. */ - void solve(unsigned iteration, PartialPlacement &p_placement) final; + void solve(unsigned iteration, PartialPlacement& p_placement) final; + + /** + * @brief Print statistics of the solver. + */ + void print_statistics() final; }; -#endif // EIGEN_INSTALLED +/** + * @brief An Analytical Solver which tries to minimize the linear HPWL objective: + * SUM((xmax - xmin) + (ymax - ymin)) over all nets. + * + * This is implemented using the Bound2Bound method, which iteratively sets up a + * linear system of equations (similar to the QP Hybrid approach above) which + * solves a quadratic objective function. For a net model, each block connects + * to the current bounding blocks in the given dimension and the weight of this + * connection is inversly proportional to the distance of the block to the bound. + * After minimizing this system, the bounds are likely to change; so the system + * needs to be reconstructed and solved iteratively. + * + * This technique was proposed in Kraftwerk2, where they proved that the B2B Net + * Model will, in theory, converge on the linear HPWL solution. + * https://doi.org/10.1109/TCAD.2008.925783 + */ +class B2BSolver : public AnalyticalSolver { + private: + /** + * @brief Enumeration for different initial placements that this class can + * perform in the first iteration. + * + * TODO: Investigate other initial placement techniques, the first iteration + * can be very expensive. + */ + enum class e_initial_placement_type { + LeastDense //< Randomly place blocks as a uniform grid over the device. + }; + + /// @brief Which initial placement algorithm to use in the first iteration. + /// In the first iteration, we need some solution to initialize the + /// bounds. Some papers have found that setting it to a random + /// initial placement is the best approach. + static constexpr e_initial_placement_type initial_placement_ty_ = e_initial_placement_type::LeastDense; + + /// @brief Since the weights in the B2B model divide by the distance between + /// blocks and their bounds, that distance may get very very close to + /// 0. This causes the weight matrix to become numerically unstable. + /// We can gaurd against this by clamping the distance to not be smaller + /// than some epsilon. + /// Decreasing this number may lead to more instability, but can yield + /// a higher quality solution. + static constexpr double distance_epsilon_ = 0.01; + + /// @brief The gap between the HPWL of the current solved solution in the + /// B2B loop and the previous solved solution that is considered to + /// be close-enough to be converged (as a fraction of the current + /// solved solution HPWL). + /// Decreasing this number toward zero would cause the B2B solver to run + /// more iterations to try and reduce the HPWL further. + static constexpr double b2b_convergence_gap_fac_ = 0.001; + + /// @brief The number of times the B2B loop should "converge" before stopping + /// the loop. Due to numerical inaccuracies, it is possible for the + /// HPWL to bounce up and down as it converges. Increasing this number + /// will allow more bounces which may get better quality; however + /// more iterations will need to be run. + static constexpr unsigned target_num_b2b_convergences_ = 2; + + /// @brief Max number of bound update / solve iterations. Increasing this + /// number will yield better quality at the expense of runtime. + static constexpr unsigned max_num_bound_updates_ = 24; + + /// @brief Max number of iterations the Conjugate Gradient solver can perform. + /// Due to the weights getting very large in the early iterations of + /// Global Placement, the CG solver may take a very long time to + /// converge; but the solution quality will not change much. By + /// default the max iteration is set to 2 * num_moveable_blocks; + /// which causes the first iteration of B2B to become quadratic in the + /// number of moveable blocks if it cannot converge. Found through + /// experimentation that this can be clamped to a much smaller number + /// to prevent this behaviour and get good runtime. + // TODO: Need to investigate this more to find a good number for this. + // TODO: Should this be a proportion of the design size? + static constexpr unsigned max_cg_iterations_ = 150; + + // The following constants are used to configure the anchor weighting. + // The weights of anchors grow exponentially each iteration by the following + // function: + // anchor_w = anchor_weight_mult_ * e^(iter / anchor_weight_exp_fac_) + // The numbers below were empircally found to work well. + + /// @brief Multiplier for the anchorweight. The smaller this number is, the + /// weaker the anchors will be at the start. + static constexpr double anchor_weight_mult_ = 0.01; + + /// @brief Factor for controlling the growth of the exponential term in the + /// weight factor function. Larger numbers will cause the anchor + /// weights to grow slower. + static constexpr double anchor_weight_exp_fac_ = 5.0; + + public: + B2BSolver(const APNetlist& ap_netlist, + const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) + : AnalyticalSolver(ap_netlist, atom_netlist, pre_cluster_timing_manager, ap_timing_tradeoff, log_verbosity) + , device_grid_width_(device_grid.width()) + , device_grid_height_(device_grid.height()) {} + + /** + * @brief Perform an iteration of the B2B solver, storing the result into + * the partial placement object passed in. + * + * In the first iteration (iteration = 0), the partial placement object will + * be ignored, and a random initial placement will be used to initially + * construct the system of equations. In all other iterations, the previous + * solved solution will be used. + * + * The B2B solver will then iteratively solve the system of equations and + * update the system to achieve a good HPWL solution which is close to the + * linear HPWL solution. Due to numerical issues with this algorithm, we will + * likely not converge on the true minimum HPWL solution, but it should be + * close. + * + * See the base class for more information. + * + * @param iteration + * The current iteration of the Global Placer + * @param p_placement + * A "guess" solution. The result will be written into this object. + * In all iterations other than the first, this solution will be used + * as anchor-points in the system. + */ + void solve(unsigned iteration, PartialPlacement& p_placement) final; + + /** + * @brief Print overall statistics on this solver. + * + * This is expected to be called after all iterations of Global Placement + * has been complete. + */ + void print_statistics() final; + + private: + /** + * @brief Run the B2B outer solving loop. + * + * The placement in p_placement should be initialized with the initial + * positions of the blocks that the B2B algorithm should use to build the + * first system of equations. This placement will be iteratively updated + * with better and better solutions as B2B iterates. + * + * If iteration is 0, no anchor-blocks will be added to the system, otherwise + * the solution in block_locs_legalized will be used as anchor-blocks. + */ + void b2b_solve_loop(unsigned iteration, PartialPlacement& p_placement); + + /** + * @brief Randomly distributes AP blocks using a normal distribution. + */ + void initialize_placement_random_normal(PartialPlacement& p_placement); + + /** + * @brief Randomly distributes AP blocks using a uniform distribution. + */ + void initialize_placement_random_uniform(PartialPlacement& p_placement); + /** + * @brief Randomly distributes AP blocks using as a uniform grid. + */ + void initialize_placement_least_dense(PartialPlacement& p_placement); + + /** + * @brief Add a weighted connection to the linear system between the first + * and second blocks for a single dimension. + * + * This method is used to construct different linear systems for different + * dimensions (x and y). Since the act of adding weighted connections is the + * same regardless of dimension, this method passes in dimension-specific + * information to be updated. + * + * @param first_blk_id + * @param second_blk_id + * @param num_pins + * The number of pins in the hypernet connecting the two blocks. + * @param blk_locs + * The location of all blocks in a given dimension. + * @param triplet_list + * The triplet list which will be used to construct the connectivity + * matrix for this dimension. + * @param b + * The constant vector for this dimension. + */ + void add_connection_to_system(APBlockId first_blk_id, + APBlockId second_blk_id, + size_t num_pins, + double net_w, + const vtr::vector& blk_locs, + std::vector>& triplet_list, + Eigen::VectorXd& b); + + /** + * @brief Initializes the linear system with the given partial placement. + * + * Blocks will be connected to the bounding blocks of their nets using + * weighted connections, with weight inversly proportional to the distance + * between blocks and the bounds. When solved in a quadratic equation this + * approximates a linear equation. + * + * This will set the connectivity matrices (A) and constant vectors (b) to + * be solved by B2B. + */ + void init_linear_system(PartialPlacement& p_placement); + + /** + * @brief Updates the linear system with anchor-blocks from the legalized + * solution. + */ + void update_linear_system_with_anchors(unsigned iteration); + + /** + * @brief Store the x and y solutions in Eigen's vectors into the partial + * placement object. + * + * Note: The x_soln and y_soln may be modified if it is found that the + * solution is imposible (i.e. has negative positions). + */ + void store_solution_into_placement(Eigen::VectorXd& x_soln, + Eigen::VectorXd& y_soln, + PartialPlacement& p_placement); + + // The following are variables used to store the system of equations to be + // solved in the x and y dimensions. The equations are of the form: + // Ax = b + // There are two sets of matrices and vectors since the x and y dimensions + // of the objective are independent and can be solved separately. + // These are updated each iteration of the B2B loop. + + /// @brief The coefficient / connectivity matrix for the x dimension. + Eigen::SparseMatrix A_sparse_x; + /// @brief The coefficient / connectivity matrix for the y dimension. + Eigen::SparseMatrix A_sparse_y; + /// @brief The constant vector in the x dimension. + Eigen::VectorXd b_x; + /// @brief The constant vector in the y dimension. + Eigen::VectorXd b_y; + + // The following is the solution of the previous iteration of this solver. + // They are updated at the end of solve() and are used as the starting point + // for the next call to solve. + vtr::vector block_x_locs_solved; + vtr::vector block_y_locs_solved; + + // The following are the legalized solution coming into the analytical solver + // (other than the first iteration). These are stored to be used as anchor + // blocks during the solver. + vtr::vector block_x_locs_legalized; + vtr::vector block_y_locs_legalized; + + /// @brief The width of the device grid. Used for randomly generating points + /// on the grid. + size_t device_grid_width_; + /// @brief The height of the device grid. Used for randomly generating points + /// on the grid. + size_t device_grid_height_; + + /// @brief The total number of CG iterations that this solver has performed + /// so far. This can be a useful metric for the amount of work the + /// solver performs. + unsigned total_num_cg_iters_ = 0; + + /// @brief The total time spent building the linear systems in the B2B solve + /// loop so far. This includes creating connections between blocks + /// in the connectivity matrix and constant vector as well as adding + /// anchor connections. + float total_time_spent_building_linear_system_ = 0.0f; + + /// @brief The total time spent solving the linear systems in the B2B solve + /// loop so far. This includes creating the CG solver object and + /// actually solving for a solution. + float total_time_spent_solving_linear_system_ = 0.0f; +}; + +#endif // EIGEN_INSTALLED diff --git a/vpr/src/analytical_place/ap_flow_enums.h b/vpr/src/analytical_place/ap_flow_enums.h new file mode 100644 index 00000000000..91c1407059d --- /dev/null +++ b/vpr/src/analytical_place/ap_flow_enums.h @@ -0,0 +1,55 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Enumerations used by the Analytical Placement Flow. + */ + +#pragma once + +/** + * @brief The type of an Analytical Solver. + * + * The Analytical Placement flow may implement different Analytical Solvers as + * part of the Global Placer. This enum can select between these different + * Analytical Solvers. + */ +enum class e_ap_analytical_solver { + QP_Hybrid, ///< Analytical Solver which uses the hybrid net model to optimize the quadratic HPWL objective. + LP_B2B ///< Analytical Solver which uses the B2B net model to optimize the linear HPWL objective. +}; + +/** + * @brief The type of a Partial Legalizer. + * + * The Analytical Placement flow may implement different Partial Legalizer as + * part of the Global Placer. This enum can select between these different + * Partial Legalizers. + */ +enum class e_ap_partial_legalizer { + BiPartitioning, ///< Partial Legalizer which forms minimum windows around dense regions and uses bipartitioning to spread blocks over windows. + FlowBased ///> Partial Legalizer which flows blocks from overfilled bins to underfilled bins. +}; + +/** + * @brief The type of a Full Legalizer. + * + * The Analytical Placement flow may implement different Full Legalizers. This + * enum can select between these different Full Legalizers. + */ +enum class e_ap_full_legalizer { + Naive, ///< The Naive Full Legalizer, which clusters atoms placed in the same tile and tries to place them in that tile according to the flat placement. + APPack, ///< The APPack Full Legalizer, which uses the flat placement to improve the Packer and Placer. + Basic_Min_Disturbance ///< The Basic Min. Disturbance Full Legalizer, which tries to reconstruct a clustered placement that is as close to the incoming flat placement as it can. +}; + +/** + * @brief The type of a Detailed Placer. + * + * The Analytical Placement flow may implement different Detailed Placers. This + * enum can select between these different Detailed Placers. + */ +enum class e_ap_detailed_placer { + Identity, ///< The Identity Detailed Placer, which does not perform any optimizations on the legalized placement. Needed as a placeholder. + Annealer ///< The Annealer Detailed Placer, which runs the annealer found in the Place part of the VPR flow (using the same options as the Placement stage). +}; diff --git a/vpr/src/analytical_place/ap_netlist.cpp b/vpr/src/analytical_place/ap_netlist.cpp index 6ae59e596b4..26c80119b9a 100644 --- a/vpr/src/analytical_place/ap_netlist.cpp +++ b/vpr/src/analytical_place/ap_netlist.cpp @@ -9,13 +9,13 @@ #include #include "netlist_fwd.h" #include "netlist_utils.h" -#include "vpr_types.h" +#include "prepack.h" #include "vtr_assert.h" /* * Blocks */ -const t_pack_molecule* APNetlist::block_molecule(const APBlockId id) const { +PackMoleculeId APNetlist::block_molecule(const APBlockId id) const { VTR_ASSERT_SAFE(valid_block_id(id)); return block_molecules_[id]; @@ -37,11 +37,11 @@ const APFixedBlockLoc& APNetlist::block_loc(const APBlockId id) const { /* * Mutators */ -APBlockId APNetlist::create_block(const std::string& name, const t_pack_molecule* mol) { +APBlockId APNetlist::create_block(const std::string& name, PackMoleculeId molecule_id) { APBlockId blk_id = Netlist::create_block(name); // Initialize the data - block_molecules_.insert(blk_id, mol); + block_molecules_.insert(blk_id, molecule_id); block_mobilities_.insert(blk_id, APBlockMobility::MOVEABLE); block_locs_.insert(blk_id, APFixedBlockLoc()); @@ -49,7 +49,7 @@ APBlockId APNetlist::create_block(const std::string& name, const t_pack_molecule VTR_ASSERT(validate_block_sizes()); // Check post-conditions: values - VTR_ASSERT(block_molecule(blk_id) == mol); + VTR_ASSERT(block_molecule(blk_id) == molecule_id); VTR_ASSERT(block_mobility(blk_id) == APBlockMobility::MOVEABLE); return blk_id; @@ -59,18 +59,18 @@ void APNetlist::set_block_loc(const APBlockId id, const APFixedBlockLoc& loc) { VTR_ASSERT_SAFE(valid_block_id(id)); // Check that the location is fixed; if all dims are unfixed then it is not fixed. - if (loc.x == APFixedBlockLoc::UNFIXED_DIM && - loc.y == APFixedBlockLoc::UNFIXED_DIM && - loc.sub_tile == APFixedBlockLoc::UNFIXED_DIM && - loc.layer_num == APFixedBlockLoc::UNFIXED_DIM) + if (loc.x == APFixedBlockLoc::UNFIXED_DIM + && loc.y == APFixedBlockLoc::UNFIXED_DIM + && loc.sub_tile == APFixedBlockLoc::UNFIXED_DIM + && loc.layer_num == APFixedBlockLoc::UNFIXED_DIM) return; // Ensure that the block is fixed to a single position on the grid (x, y, layer). // sub-tile is allowed to be unfixed. - VTR_ASSERT(loc.x != APFixedBlockLoc::UNFIXED_DIM && - loc.y != APFixedBlockLoc::UNFIXED_DIM && - loc.layer_num != APFixedBlockLoc::UNFIXED_DIM && - "AP: Currently, AP assumes block is locked down to a single position on the device grid."); + VTR_ASSERT(loc.x != APFixedBlockLoc::UNFIXED_DIM + && loc.y != APFixedBlockLoc::UNFIXED_DIM + && loc.layer_num != APFixedBlockLoc::UNFIXED_DIM + && "AP: Currently, AP assumes block is locked down to a single position on the device grid."); block_locs_[id] = loc; block_mobilities_[id] = APBlockMobility::FIXED; @@ -207,4 +207,3 @@ bool APNetlist::validate_net_sizes_impl(size_t /*num_nets*/) const { // No AP-specific net data to check return true; } - diff --git a/vpr/src/analytical_place/ap_netlist.h b/vpr/src/analytical_place/ap_netlist.h index ec64ae38a9b..1bfe8c5e49b 100644 --- a/vpr/src/analytical_place/ap_netlist.h +++ b/vpr/src/analytical_place/ap_netlist.h @@ -23,9 +23,7 @@ #include #include "netlist.h" #include "ap_netlist_fwd.h" - -// Forward declarations -class t_pack_molecule; +#include "prepack.h" /** * @brief Struct to store fixed block location information @@ -37,10 +35,10 @@ class t_pack_molecule; */ struct APFixedBlockLoc { // Value that represents an unfixed dimension. - static constexpr int UNFIXED_DIM = -1; + static constexpr float UNFIXED_DIM = -1; // The dimensions to fix. - int x = UNFIXED_DIM; - int y = UNFIXED_DIM; + float x = UNFIXED_DIM; + float y = UNFIXED_DIM; int layer_num = UNFIXED_DIM; int sub_tile = UNFIXED_DIM; }; @@ -51,8 +49,8 @@ struct APFixedBlockLoc { * block ids. */ enum class APBlockMobility : bool { - MOVEABLE, // The block is not constrained in any dimension. - FIXED // The block is fixed. + MOVEABLE, // The block is not constrained in any dimension. + FIXED // The block is fixed. }; /** @@ -64,7 +62,7 @@ enum class APBlockMobility : bool { * APBlocks. These need not have physical meaning. */ class APNetlist : public Netlist { -public: + public: /** * @brief Constructs a netlist * @@ -72,18 +70,19 @@ class APNetlist : public Netlist { * @param id A unique identifier for the netlist (e.g. a secure digest of * the input file) */ - APNetlist(std::string name = "", std::string id = "") : Netlist(name, id) {} + APNetlist(std::string name = "", std::string id = "") + : Netlist(name, id) {} APNetlist(const APNetlist& rhs) = default; APNetlist& operator=(const APNetlist& rhs) = default; -public: // Public Accessors + public: // Public Accessors /* * Blocks */ /// @brief Returns the molecule that this block represents. - const t_pack_molecule* block_molecule(const APBlockId id) const; + PackMoleculeId block_molecule(const APBlockId id) const; /// @brief Returns the mobility of this block. APBlockMobility block_mobility(const APBlockId id) const; @@ -92,7 +91,7 @@ class APNetlist : public Netlist { /// This method should not be used if the block is moveable. const APFixedBlockLoc& block_loc(const APBlockId id) const; -public: // Public Mutators + public: // Public Mutators /* * Note: all create_*() functions will silently return the appropriate ID * if it has already been created. @@ -104,7 +103,7 @@ class APNetlist : public Netlist { * @param name The unique name of the block * @param mol The molecule the block represents */ - APBlockId create_block(const std::string& name, const t_pack_molecule* mol); + APBlockId create_block(const std::string& name, PackMoleculeId molecule_id); /** * @brief Fixes a block at the given location @@ -143,7 +142,7 @@ class APNetlist : public Netlist { */ APNetId create_net(const std::string& name); -private: // Private Members + private: // Private Members /* * Netlist compression / optimization */ @@ -180,13 +179,12 @@ class APNetlist : public Netlist { bool validate_pin_sizes_impl(size_t num_pins) const override; bool validate_net_sizes_impl(size_t num_nets) const override; -private: // Private Data + private: // Private Data /// @brief Molecule of each block - vtr::vector_map block_molecules_; + vtr::vector_map block_molecules_; /// @brief Type of each block vtr::vector_map block_mobilities_; /// @brief Location of each block (if fixed). /// NOTE: This vector will likely be quite sparse. vtr::vector_map block_locs_; }; - diff --git a/vpr/src/analytical_place/ap_netlist_fwd.h b/vpr/src/analytical_place/ap_netlist_fwd.h index 3fc9e87dea7..ede36cf6a07 100644 --- a/vpr/src/analytical_place/ap_netlist_fwd.h +++ b/vpr/src/analytical_place/ap_netlist_fwd.h @@ -26,7 +26,7 @@ class APNetlist; * @brief A unique identifier for a block in the AP netlist */ class APBlockId : public ParentBlockId { -public: + public: static constexpr APBlockId INVALID() { return APBlockId(); } using ParentBlockId::ParentBlockId; @@ -37,7 +37,7 @@ class APBlockId : public ParentBlockId { * @brief A unique identifier for a net in the AP netlist */ class APNetId : public ParentNetId { -public: + public: static constexpr APNetId INVALID() { return APNetId(); } using ParentNetId::ParentNetId; @@ -48,7 +48,7 @@ class APNetId : public ParentNetId { * @brief A unique identifier for a port in the AP netlist */ class APPortId : public ParentPortId { -public: + public: static constexpr APPortId INVALID() { return APPortId(); } using ParentPortId::ParentPortId; @@ -59,7 +59,7 @@ class APPortId : public ParentPortId { * @brief A unique identifier for a pin in the AP netlist */ class APPinId : public ParentPinId { -public: + public: static constexpr APPinId INVALID() { return APPinId(); } using ParentPinId::ParentPinId; @@ -101,4 +101,3 @@ struct hash { } }; } // namespace std - diff --git a/vpr/src/analytical_place/detailed_placer.cpp b/vpr/src/analytical_place/detailed_placer.cpp new file mode 100644 index 00000000000..75001fe4c42 --- /dev/null +++ b/vpr/src/analytical_place/detailed_placer.cpp @@ -0,0 +1,109 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Implementation of the Detailed Placers. + */ + +#include "detailed_placer.h" +#include +#include "PlacementDelayModelCreator.h" +#include "ap_flow_enums.h" +#include "atom_netlist.h" +#include "clustered_netlist.h" +#include "clustered_netlist_utils.h" +#include "echo_files.h" +#include "flat_placement_types.h" +#include "globals.h" +#include "physical_types.h" +#include "place_and_route.h" +#include "place_delay_model.h" +#include "placer.h" +#include "vpr_error.h" +#include "vpr_types.h" +#include "vpr_utils.h" +#include "vtr_time.h" + +std::unique_ptr make_detailed_placer(e_ap_detailed_placer detailed_placer_type, + const BlkLocRegistry& curr_clustered_placement, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist, + t_vpr_setup& vpr_setup, + const t_arch& arch) { + switch (detailed_placer_type) { + case e_ap_detailed_placer::Identity: + return std::make_unique(); + case e_ap_detailed_placer::Annealer: + return std::make_unique(curr_clustered_placement, + atom_netlist, + clustered_netlist, + vpr_setup, + arch); + default: + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Unrecognized detailed placer type"); + } +} + +AnnealerDetailedPlacer::AnnealerDetailedPlacer(const BlkLocRegistry& curr_clustered_placement, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist, + t_vpr_setup& vpr_setup, + const t_arch& arch) + : DetailedPlacer() + // TODO: These two variables needed to be stored in the class since + // the Placer stores a reference to these objects. These + // should really be initialized and stored into the Placer + // class directly. + , pb_gpin_lookup_(g_vpr_ctx.device().logical_block_types) + , netlist_pin_lookup_(clustered_netlist, atom_netlist, pb_gpin_lookup_) { + // Initialize the place delay model. + // TODO: This initialization is complicated. Should be moved within create_delay_model + // or something. + std::shared_ptr place_delay_model; + if (vpr_setup.PlacerOpts.place_algorithm.is_timing_driven()) { + place_delay_model = PlacementDelayModelCreator::create_delay_model(vpr_setup.PlacerOpts, + vpr_setup.RouterOpts, + (const Netlist<>&)clustered_netlist, + &vpr_setup.RoutingArch, + vpr_setup.Segments, + arch.Chans, + arch.directs, + false /*is_flat*/); + if (isEchoFileEnabled(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)) { + place_delay_model->dump_echo(getEchoFileName(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)); + } + } + + placer_ = std::make_unique((const Netlist<>&)clustered_netlist, + curr_clustered_placement, + vpr_setup.PlacerOpts, + vpr_setup.AnalysisOpts, + vpr_setup.NocOpts, + pb_gpin_lookup_, + netlist_pin_lookup_, + FlatPlacementInfo(), + place_delay_model, + g_vpr_ctx.placement().cube_bb, + false /*is_flat*/, + false /*quiet*/); +} + +void AnnealerDetailedPlacer::optimize_placement() { + // Create a scoped timer for the detailed placer. + vtr::ScopedStartFinishTimer full_legalizer_timer("AP Detailed Placer"); + + // Prevent the annealer from directly modifying the global legal placement. + // It should only modify its own, local placement. + g_vpr_ctx.mutable_placement().lock_loc_vars(); + + // Run the simulated annealer. + placer_->place(); + + // Copy the placement solution into the global placement solution. + placer_->copy_locs_to_global_state(g_vpr_ctx.mutable_placement()); + + // Since the placement was modified, need to resynchronize the pins in the + // clusters. + post_place_sync(); +} diff --git a/vpr/src/analytical_place/detailed_placer.h b/vpr/src/analytical_place/detailed_placer.h new file mode 100644 index 00000000000..46f769a4d22 --- /dev/null +++ b/vpr/src/analytical_place/detailed_placer.h @@ -0,0 +1,108 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Defines the DetailedPlacer class which takes a fully legal clustering + * and placement and optimizes them while remaining legal. + */ + +#pragma once + +#include +#include "ap_flow_enums.h" +#include "clustered_netlist_utils.h" +#include "placer.h" +#include "vpr_utils.h" + +/** + * @brief The detailed placer in an AP flow. + * + * Given a fully legal clustering and clustered placement, will optimize the + * solution while remaining fully legal (able to be used in the rest of the VPR + * flow). + */ +class DetailedPlacer { + public: + virtual ~DetailedPlacer() {} + + DetailedPlacer() = default; + + /** + * @brief Optimize the current legal placement. + */ + virtual void optimize_placement() = 0; +}; + +/** + * @brief A factory method which creates a Detailed Placer of the given type. + */ +std::unique_ptr make_detailed_placer(e_ap_detailed_placer detailed_placer_type, + const BlkLocRegistry& curr_clustered_placement, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist, + t_vpr_setup& vpr_setup, + const t_arch& arch); + +/** + * @brief The Identity Detailed Placer. + * + * This detailed placer does literally nothing to the legal placement. This + * class is used as a placeholder to make the higher-level code easier to work + * with. + */ +class IdentityDetailedPlacer : public DetailedPlacer { + public: + using DetailedPlacer::DetailedPlacer; + + void optimize_placement() final {} +}; + +/** + * @brief The Annealer Detailed Placer. + * + * This Detailed Placer passes the legal solution into the Annealer in the + * VPR flow (uses the legal solution as the initial placement). This performs + * the Simulated Annealing algorithm on the solution at the cluster level to + * try and find a better clustered placement. + * + * This Detailed Placer reuses the options from the Placer stage of VPR for this + * stage. So options passed to the Placer will be used in here. + */ +class AnnealerDetailedPlacer : public DetailedPlacer { + public: + /** + * @brief Construct the Annealer Detailed Placer class. + * + * @param curr_clustered_placement + * The legalized placement solution to pass as the initial placement + * into the annealer. + * @param atom_netlist + * The netlist of atoms in the circuit. + * @param clustered_netlist + * The netlist of clusters created by the Full Legalizer. + * @param vpr_setup + * The setup variables, used to get the params from the user. + * @param arch + * The FPGA architecture to optimize onto. + */ + AnnealerDetailedPlacer(const BlkLocRegistry& curr_clustered_placement, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist, + t_vpr_setup& vpr_setup, + const t_arch& arch); + + /** + * @brief Run the annealer. + */ + void optimize_placement() final; + + private: + /// @brief The placer class, which contains the annealer. + std::unique_ptr placer_; + + /// @brief A lookup between the block pin indices and pb graph pins. + IntraLbPbPinLookup pb_gpin_lookup_; + + /// @brief A lookup between CLB pins and atom pins. + ClusteredPinAtomPinsLookup netlist_pin_lookup_; +}; diff --git a/vpr/src/analytical_place/flat_placement_bins.h b/vpr/src/analytical_place/flat_placement_bins.h new file mode 100644 index 00000000000..e94ed958312 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_bins.h @@ -0,0 +1,196 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Flat Placement Bin Abstraction + * + * This file declares a class which can bin AP Blocks spatially throughout the + * FPGA. + */ + +#pragma once + +#include +#include "ap_netlist.h" +#include "vtr_assert.h" +#include "vtr_geometry.h" +#include "vtr_log.h" +#include "vtr_range.h" +#include "vtr_strong_id.h" +#include "vtr_vector.h" +#include "vtr_vector_map.h" + +// The tag for the flat placement bin. +struct flat_placement_bin_tag {}; + +/** + * @brief A unique ID to a flat placement bin. + */ +typedef vtr::StrongId FlatPlacementBinId; + +/** + * @brief A container of bins which hold AP blocks and take up space on the FPGA. + * + * For flat placement, blocks may be placed anywhere on the FPGA grid. This + * placement is continuous; however, in order to compute quantities like density + * and legality, there needs to be a way to bin blocks together spatially. + * + * This class maintains bins which hold AP blocks and take up a rectangular + * amount of space on the FPGA grid. + * + * This class is only a container; it leaves how the FPGA is split into bins to + * higher level classes. + */ +class FlatPlacementBins { + public: + // Iterator for the flat placement bin IDs + typedef typename vtr::vector_map::const_iterator bin_iterator; + + // Range for the flat placement bin IDs + typedef typename vtr::Range bin_range; + + FlatPlacementBins(const APNetlist& ap_netlist) + : block_bin_(ap_netlist.blocks().size(), FlatPlacementBinId::INVALID()) {} + + /** + * @brief Returns a range of all bins that have been created. + */ + bin_range bins() const { + return vtr::make_range(bin_ids_.begin(), bin_ids_.end()); + } + + /** + * @brief Creates a bin which exists in the given bin_region. + * + * @param bin_region + * The rectangular region of the FPGA device that this bin will + * represent. + */ + inline FlatPlacementBinId create_bin(const vtr::Rect& bin_region) { + FlatPlacementBinId new_bin_id = FlatPlacementBinId(bin_ids_.size()); + bin_ids_.push_back(new_bin_id); + bin_region_.push_back(bin_region); + bin_contained_blocks_.resize(bin_contained_blocks_.size() + 1); + return new_bin_id; + } + + /** + * @brief Add the given block to the given bin. + */ + inline void add_block_to_bin(APBlockId blk_id, FlatPlacementBinId bin_id) { + VTR_ASSERT(blk_id.is_valid()); + VTR_ASSERT(bin_id.is_valid()); + VTR_ASSERT(!block_bin_[blk_id].is_valid()); + bin_contained_blocks_[bin_id].insert(blk_id); + block_bin_[blk_id] = bin_id; + } + + /** + * @brief Remove the given block from the given bin. The bin must contain + * this block. + */ + inline void remove_block_from_bin(APBlockId blk_id, FlatPlacementBinId bin_id) { + VTR_ASSERT(blk_id.is_valid()); + VTR_ASSERT(bin_id.is_valid()); + VTR_ASSERT(block_bin_[blk_id] == bin_id); + bin_contained_blocks_[bin_id].erase(blk_id); + block_bin_[blk_id] = FlatPlacementBinId::INVALID(); + } + + /** + * @brief Get the blocks contained within the given bin. + */ + inline const std::unordered_set& bin_contained_blocks(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_contained_blocks_[bin_id]; + } + + /** + * @brief Get the region of the FPGA that the given bin covers. + */ + inline const vtr::Rect& bin_region(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_region_[bin_id]; + } + + /** + * @brief Get the bin that contains the given AP block. + */ + inline FlatPlacementBinId block_bin(APBlockId blk_id) const { + VTR_ASSERT(blk_id.is_valid()); + return block_bin_[blk_id]; + } + + /** + * @brief Remove all of the AP blocks from the given bin. + */ + inline void remove_all_blocks_from_bin(FlatPlacementBinId bin_id) { + VTR_ASSERT(bin_id.is_valid()); + // Invalidate the block bin lookup for the blocks in the bin. + for (APBlockId blk_id : bin_contained_blocks_[bin_id]) { + block_bin_[blk_id] = FlatPlacementBinId::INVALID(); + } + // Remove all of the blocks from the bin. + bin_contained_blocks_[bin_id].clear(); + } + + /** + * @brief Verify the internal members of this class are consistent. + */ + inline bool verify() const { + // Ensure all bin IDs are valid and consistent. + for (FlatPlacementBinId bin_id : bin_ids_) { + if (!bin_id.is_valid()) { + VTR_LOG("Bin Verify: Invalid bin ID in bins.\n"); + return false; + } + if (bin_ids_.count(bin_id) != 1) { + VTR_LOG("Bin Verify: Found a bin ID not in the bin IDs array.\n"); + return false; + } + if (bin_ids_[bin_id] != bin_id) { + VTR_LOG("Bin Verify: Bin ID found which is not consistent.\n"); + return false; + } + } + + // Ensure the data members of this class are all the correct size. + size_t num_bins = bin_ids_.size(); + if (bin_contained_blocks_.size() != num_bins) { + VTR_LOG("Bin Verify: bin_constained_blocks_ not the correct size.\n"); + return false; + } + if (bin_region_.size() != num_bins) { + VTR_LOG("Bin Verify: bin_region_ not the correct size.\n"); + return false; + } + + // Make sure that the bin_contained_blocks_ and the block_bin_ are + // consistent. + for (FlatPlacementBinId bin_id : bin_ids_) { + for (APBlockId blk_id : bin_contained_blocks_[bin_id]) { + if (block_bin_[blk_id] != bin_id) { + VTR_LOG("Bin Verify: Block is contained within a bin but does not agree.\n"); + return false; + } + } + } + + return true; + } + + private: + /// @brief A vector of the Flat Placement Bin IDs. If any of them are invalid, + /// then that means that the bin has been destroyed. + vtr::vector_map bin_ids_; + + /// @brief The contained AP blocks of each bin. + vtr::vector_map> bin_contained_blocks_; + + /// @brief The bin that contains each AP block. + vtr::vector block_bin_; + + /// @brief The region that each bin represents on the FPGA grid. + // TODO: For 3D FPGAs, this should be a 3D rectangle. + vtr::vector_map> bin_region_; +}; diff --git a/vpr/src/analytical_place/flat_placement_density_manager.cpp b/vpr/src/analytical_place/flat_placement_density_manager.cpp new file mode 100644 index 00000000000..f4c37b191c8 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_density_manager.cpp @@ -0,0 +1,309 @@ +/** + * @file + * @author Alex Singer + * @date February 2025 + * @brief Implementation of the density manager class. + */ + +#include "flat_placement_density_manager.h" +#include +#include "ap_netlist.h" +#include "ap_netlist_fwd.h" +#include "atom_netlist.h" +#include "flat_placement_bins.h" +#include "flat_placement_mass_calculator.h" +#include "partial_placement.h" +#include "physical_types.h" +#include "prepack.h" +#include "vtr_assert.h" +#include "vtr_geometry.h" +#include "vtr_vector.h" +#include "vtr_vector_map.h" + +/** + * @brief Calculates how over-capacity the given utilization vector is. + */ +static PrimitiveVector calc_bin_overfill(const PrimitiveVector& bin_utilization, + const PrimitiveVector& bin_capacity) { + PrimitiveVector overfill = bin_utilization - bin_capacity; + overfill.relu(); + VTR_ASSERT_DEBUG(overfill.is_non_negative()); + return overfill; +} + +/** + * @brief Calculates how under-capacity the given utilization vector is. + */ +static PrimitiveVector calc_bin_underfill(const PrimitiveVector& bin_utilization, + const PrimitiveVector& bin_capacity) { + PrimitiveVector underfill = bin_capacity - bin_utilization; + underfill.relu(); + VTR_ASSERT_DEBUG(underfill.is_non_negative()); + return underfill; +} + +FlatPlacementDensityManager::FlatPlacementDensityManager(const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + int log_verbosity) + : ap_netlist_(ap_netlist) + , bins_(ap_netlist) + , mass_calculator_(ap_netlist, prepacker, atom_netlist, logical_block_types, physical_tile_types, log_verbosity) + , log_verbosity_(log_verbosity) { + // Initialize the bin spatial lookup object. + size_t num_layers, width, height; + std::tie(num_layers, width, height) = device_grid.dim_sizes(); + bin_spatial_lookup_.resize({num_layers, width, height}); + + // Create a bin for each tile. This will create one bin for each root tile + // location. + vtr::vector_map bin_phy_tile_type_idx; + for (size_t layer = 0; layer < num_layers; layer++) { + for (size_t x = 0; x < width; x++) { + for (size_t y = 0; y < height; y++) { + // Only create bins for root tile locations. + auto tile_loc = t_physical_tile_loc(x, y, layer); + int w_offset = device_grid.get_width_offset(tile_loc); + int h_offset = device_grid.get_height_offset(tile_loc); + if (w_offset != 0 || h_offset != 0) { + // If this is not a root tile location, set the spatial bin + // lookup to point to the root tile location's bin. + FlatPlacementBinId root_bin_id = bin_spatial_lookup_[layer][x - w_offset][y - h_offset]; + bin_spatial_lookup_[layer][x][y] = root_bin_id; + continue; + } + + // Create a bin for this tile. + auto tile_type = device_grid.get_physical_type(tile_loc); + int tw = tile_type->width; + int th = tile_type->height; + VTR_ASSERT_SAFE(tw != 0 && th != 0); + vtr::Rect new_bin_region(vtr::Point(x, y), + vtr::Point(x + tw, + y + th)); + FlatPlacementBinId new_bin_id = bins_.create_bin(new_bin_region); + + // Add the bin to the spatial lookup + bin_spatial_lookup_[layer][x][y] = new_bin_id; + + // Store the index of the physical tile type into a map to be + // used to compute the capacity. + bin_phy_tile_type_idx.insert(new_bin_id, tile_type->index); + } + } + } + + // Initialize the bin capacities to the mass capacity of the physical tile + // this bin represents. + bin_capacity_.resize(bins_.bins().size()); + for (FlatPlacementBinId bin_id : bins_.bins()) { + size_t physical_tile_type_index = bin_phy_tile_type_idx[bin_id]; + bin_capacity_[bin_id] = mass_calculator_.get_physical_tile_type_capacity(physical_tile_type_index); + } + + // Initialize the bin utilizations to be zero (there is nothing in the bin + // currently). + bin_utilization_.resize(bins_.bins().size(), PrimitiveVector()); + + // Initialize the bin underfill and overfill. + bin_underfill_.resize(bins_.bins().size()); + bin_overfill_.resize(bins_.bins().size()); + for (FlatPlacementBinId bin_id : bins_.bins()) { + bin_underfill_[bin_id] = calc_bin_underfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + bin_overfill_[bin_id] = calc_bin_overfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + } + + // Note: The overfilled_bins_ are left empty. All bins are empty, therefore + // no bin is overfilled. +} + +FlatPlacementBinId FlatPlacementDensityManager::get_bin(double x, double y, double layer) const { + size_t layer_pos = std::floor(layer); + size_t x_pos = std::floor(x); + size_t y_pos = std::floor(y); + VTR_ASSERT(layer_pos < bin_spatial_lookup_.dim_size(0)); + VTR_ASSERT(x_pos < bin_spatial_lookup_.dim_size(1)); + VTR_ASSERT(y_pos < bin_spatial_lookup_.dim_size(2)); + return bin_spatial_lookup_[layer_pos][x][y]; +} + +void FlatPlacementDensityManager::insert_block_into_bin(APBlockId blk_id, + FlatPlacementBinId bin_id) { + VTR_ASSERT(blk_id.is_valid()); + VTR_ASSERT(bin_id.is_valid()); + // Add the block to the bin. + bins_.add_block_to_bin(blk_id, bin_id); + // Update the bin utilization. + bin_utilization_[bin_id] += mass_calculator_.get_block_mass(blk_id); + // Update the bin overfill and underfill + bin_overfill_[bin_id] = calc_bin_overfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + bin_underfill_[bin_id] = calc_bin_underfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + // Insert the bin into the overfilled bin set if it is overfilled. + if (bin_is_overfilled(bin_id)) + overfilled_bins_.insert(bin_id); +} + +void FlatPlacementDensityManager::remove_block_from_bin(APBlockId blk_id, + FlatPlacementBinId bin_id) { + VTR_ASSERT(blk_id.is_valid()); + VTR_ASSERT(bin_id.is_valid()); + // Remove the block from the bin. + bins_.remove_block_from_bin(blk_id, bin_id); + // Update the bin utilization. + bin_utilization_[bin_id] -= mass_calculator_.get_block_mass(blk_id); + // Update the bin overfill and underfill. + bin_overfill_[bin_id] = calc_bin_overfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + bin_underfill_[bin_id] = calc_bin_underfill(bin_utilization_[bin_id], bin_capacity_[bin_id]); + // Remove from overfilled bins set if it is not overfilled. + if (!bin_is_overfilled(bin_id)) + overfilled_bins_.erase(bin_id); +} + +void FlatPlacementDensityManager::import_placement_into_bins(const PartialPlacement& p_placement) { + // Empty the bins such that all blocks are no longer within the bins. + empty_bins(); + + // Insert each block in the netlist into their bin based on their placement. + // TODO: Maybe import the fixed block locations in the constructor and then + // only import the moveable block locations. + for (APBlockId blk_id : ap_netlist_.blocks()) { + FlatPlacementBinId bin_id = get_bin(p_placement.block_x_locs[blk_id], + p_placement.block_y_locs[blk_id], + p_placement.block_layer_nums[blk_id]); + insert_block_into_bin(blk_id, bin_id); + } +} + +vtr::Point FlatPlacementDensityManager::get_block_location_in_bin(APBlockId blk_id, + const vtr::Rect& bin_region, + const PartialPlacement& p_placement) const { + // A block should not be placed on the edges of the region + // of a bin; however they can be infinitely close to these sides. It is + // arbitrary how close to the edge we place the blocks; opted to place them + // as close as possible. + double epsilon = 0.0001; + double x = std::clamp(p_placement.block_x_locs[blk_id], + bin_region.bottom_left().x() + epsilon, + bin_region.top_right().x() - epsilon); + double y = std::clamp(p_placement.block_y_locs[blk_id], + bin_region.bottom_left().y() + epsilon, + bin_region.top_right().y() - epsilon); + return vtr::Point(x, y); +} + +void FlatPlacementDensityManager::export_placement_from_bins(PartialPlacement& p_placement) const { + // Updates the partial placement with the location of the blocks in the bin + // by moving the blocks to the point with the bin closest to where they + // were originally. + for (APBlockId blk_id : ap_netlist_.blocks()) { + // Only the moveable block locations should be exported. + if (ap_netlist_.block_mobility(blk_id) == APBlockMobility::FIXED) + continue; + // Project the coordinate of the block in the partial placement to the + // closest point in the bin. + FlatPlacementBinId blk_bin_id = bins_.block_bin(blk_id); + VTR_ASSERT_DEBUG(blk_bin_id.is_valid()); + vtr::Point new_blk_pos = get_block_location_in_bin(blk_id, + bins_.bin_region(blk_bin_id), + p_placement); + p_placement.block_x_locs[blk_id] = new_blk_pos.x(); + p_placement.block_y_locs[blk_id] = new_blk_pos.y(); + // NOTE: This code currently does not support 3D FPGAs. + VTR_ASSERT(std::floor(p_placement.block_layer_nums[blk_id]) == 0.0); + } +} + +void FlatPlacementDensityManager::empty_bins() { + // Reset all of the bins and their utilizations. + for (FlatPlacementBinId bin_id : bins_.bins()) { + bins_.remove_all_blocks_from_bin(bin_id); + bin_utilization_[bin_id].clear(); + bin_overfill_[bin_id].clear(); + bin_underfill_[bin_id] = bin_capacity_[bin_id]; + } + // Once all the bins are reset, all bins should be empty; therefore no bins + // are overfilled. + overfilled_bins_.clear(); +} + +bool FlatPlacementDensityManager::verify() const { + // Verify the bins for consistency. + if (!bins_.verify()) { + VTR_LOG("Bins failed to verify.\n"); + return false; + } + // Make sure that every block has a bin. + for (APBlockId blk_id : ap_netlist_.blocks()) { + if (!bins_.block_bin(blk_id).is_valid()) { + VTR_LOG("Bin Verify: Found a block that is not in a bin.\n"); + return false; + } + } + // Make sure that every bin has the correct utilization, supply, and demand. + for (FlatPlacementBinId bin_id : bins_.bins()) { + PrimitiveVector calc_utilization; + for (APBlockId blk_id : bins_.bin_contained_blocks(bin_id)) { + calc_utilization += mass_calculator_.get_block_mass(blk_id); + } + if (bin_utilization_[bin_id] != calc_utilization) { + VTR_LOG("Bin Verify: Found a bin with incorrect utilization.\n"); + return false; + } + PrimitiveVector calc_overfill = bin_utilization_[bin_id] - bin_capacity_[bin_id]; + calc_overfill.relu(); + if (bin_overfill_[bin_id] != calc_overfill) { + VTR_LOG("Bin Verify: Found a bin with incorrect overfill.\n"); + return false; + } + PrimitiveVector calc_underfill = bin_capacity_[bin_id] - bin_utilization_[bin_id]; + calc_underfill.relu(); + if (bin_underfill_[bin_id] != calc_underfill) { + VTR_LOG("Bin Verify: Found a bin with incorrect underfill.\n"); + return false; + } + if (!bin_overfill_[bin_id].is_non_negative()) { + VTR_LOG("Bin Verify: Found a bin with a negative overfill.\n"); + return false; + } + if (!bin_underfill_[bin_id].is_non_negative()) { + VTR_LOG("Bin Verify: Found a bin with a negative underfill.\n"); + return false; + } + if (!bin_capacity_[bin_id].is_non_negative()) { + VTR_LOG("Bin Verify: Found a bin with a negative capacity.\n"); + return false; + } + if (!bin_utilization_[bin_id].is_non_negative()) { + VTR_LOG("Bin Verify: Found a bin with a negative utilization.\n"); + return false; + } + } + // Make sure all overfilled bins are actually overfilled. + // TODO: Need to make sure that all non-overfilled bins are actually not + // overfilled. + for (FlatPlacementBinId bin_id : overfilled_bins_) { + if (bin_overfill_[bin_id].is_zero()) { + VTR_LOG("Bin Verify: Found an overfilled bin that was not overfilled.\n"); + return false; + } + } + // If all above passed, then the bins are valid. + return true; +} + +void FlatPlacementDensityManager::print_bin_grid() const { + size_t width = bin_spatial_lookup_.dim_size(1); + size_t height = bin_spatial_lookup_.dim_size(2); + for (size_t y = 0; y < height; y++) { + for (size_t x = 0; x < width; x++) { + FlatPlacementBinId bin_id = get_bin(x, y, 0.0); + VTR_LOG("%3zu ", + bins_.bin_contained_blocks(bin_id).size()); + } + VTR_LOG("\n"); + } + VTR_LOG("\n"); +} diff --git a/vpr/src/analytical_place/flat_placement_density_manager.h b/vpr/src/analytical_place/flat_placement_density_manager.h new file mode 100644 index 00000000000..ad3977589c1 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_density_manager.h @@ -0,0 +1,273 @@ +/** + * @file + * @author Alex Singer + * @date February 2024 + * @brief Manager class for how density is calculated in the AP flow. + * + * This class decides how the FPGA grid is partitioned into bins and what + * defines a bin that is "overfilled". + */ + +#pragma once + +#include +#include +#include +#include "flat_placement_bins.h" +#include "flat_placement_mass_calculator.h" +#include "vtr_assert.h" +#include "vtr_ndmatrix.h" +#include "vtr_vector.h" + +class APNetlist; +class AtomNetlist; +class DeviceGrid; +class Prepacker; +struct PartialPlacement; +struct t_logical_block_type; +struct t_physical_tile_type; + +/** + * @brief Manager class for computing the density of a flat placement. + * + * Density is a function of mass and volume. Since a flat placement is a + * continuous placement of discrete objects, the space the objects are placed + * over needs to be partitioned into discrete bins. Regions that are too dense + * are called overfilled bins and regions that may hold more (not too dense) + * are called underfilled bins. This class manages the construction of these + * bins and how overfilled / underfilled they are. + * + * Currently, a bin is created for each tile in the FPGA grid (with a unique + * root tile location). For example, a CLB taking up a single tile would be a + * 1x1 bin, while a DSP block taking up multiple tiles may be a 4x1 bin. The + * capacity of each bin is the capacity of the tile it represents (as computed + * by the flat placement mass calculator). When AP blocks are added / removed + * from bins, this class will maintain the current utilization of the bin. Since + * these masses / capacities are repesented by M-dimensional quantities (where + * M is the number of models in the architecture), the overfill and underfill of + * each bin is given as an M-dimensional vector. For example, in an architecture + * of only LUTs and FFs, an overfill of <3, 1> means that a bin has 3 too many + * LUTs and 1 too many FFs. + * + * This class is able to answer questions about the current density of the flat + * placement such as which bins are currently overfilled, what bin is at the + * given location, etc. + * + * TODO: Add an option to this class to change the granularity of the bins. This + * may allow us to trade off quality and runtime. + */ +class FlatPlacementDensityManager { + public: + /** + * @brief Construct the density manager. + * + * @param ap_netlist + * @param prepacker + * @param atom_netlist + * @param device_grid + * @param logical_block_types + * @param physical_tile_types + * @param log_verbosity + */ + FlatPlacementDensityManager(const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + int log_verbosity); + + /** + * @brief Returns a reference to the bins the manager has created. + */ + inline const FlatPlacementBins& flat_placement_bins() const { + return bins_; + } + + /** + * @brief Returns a reference to the mass calculator that the manager class + * is using to detect overfilled / undefilled bins. + */ + inline const FlatPlacementMassCalculator& mass_calculator() const { + return mass_calculator_; + } + + /** + * @brief Returns the bin located at the given (x, y, layer) position. + */ + FlatPlacementBinId get_bin(double x, double y, double layer) const; + + /** + * @brief Returns the size of the placeable region, i.e. the region that + * contains all bins. + */ + inline std::tuple get_overall_placeable_region_size() const { + return std::make_tuple(bin_spatial_lookup_.dim_size(1), // width + bin_spatial_lookup_.dim_size(2), // height + bin_spatial_lookup_.dim_size(0)); // depth + } + + /** + * @brief Insert the given block into the given bin. + * + * As well as updating the bin's contents, also maintains the utilization + * of the bins. + */ + void insert_block_into_bin(APBlockId blk_id, FlatPlacementBinId bin_id); + + /** + * @brief Remove the given block from the given bin. + * + * Like insertion, this maintains the utilization of bins. + */ + void remove_block_from_bin(APBlockId blk_id, FlatPlacementBinId bin_id); + + /** + * @brief Returns the current utilization of the given bin. + * + * This is the sum of the mass of each atoms in the given bin. + */ + inline const PrimitiveVector& get_bin_utilization(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_utilization_[bin_id]; + } + + /** + * @brief Returns the capacity of the given bin. + * + * This is an approximation of the amount of mass that the tile that this + * bin represents can hold. + */ + inline const PrimitiveVector& get_bin_capacity(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_capacity_[bin_id]; + } + + /** + * @brief Returns how overfilled the given bin is. + * + * This cannot be negative. This is how much over the capacity the current + * utilization is. An overfill of 0 implies that the bin is not overfilled. + */ + inline const PrimitiveVector& get_bin_overfill(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_overfill_[bin_id]; + } + + /** + * @brief Returns how underfilled the given bin is. + * + * This cannot be negative. This is how much more mass the given bin can + * hold without going over capactiy. + */ + inline const PrimitiveVector& get_bin_underfill(FlatPlacementBinId bin_id) const { + VTR_ASSERT(bin_id.is_valid()); + return bin_underfill_[bin_id]; + } + + /** + * @brief Returns true of the given bin is overfilled (it contains too much + * mass and is over capacity). + */ + inline bool bin_is_overfilled(FlatPlacementBinId bin_id) const { + // A bin is overfilled if the overfill is non-zero. + return get_bin_overfill(bin_id).is_non_zero(); + } + + /** + * @brief Returns a list of all overfilled bins. + */ + inline const std::unordered_set& get_overfilled_bins() const { + return overfilled_bins_; + } + + /** + * @brief Import the given flat placement into the bins. + * + * This will place AP blocks into the bins that they are placed over. + * + * This will reset the bins before importing the placement. Anything inside + * the bins will be removed. + */ + void import_placement_into_bins(const PartialPlacement& p_placement); + + /** + * @brief Exports the placement of blocks in bins to a flat placement. + * + * This will move each block to the position closest to the original flat + * placement that is still within the bin the block was placed into. + */ + void export_placement_from_bins(PartialPlacement& p_placement) const; + + /** + * @brief Gets the position of the AP block within the bin it contains. + * + * This will return the position of the block that is closest to the position + * in the given flat placement, while still being within the the bin region. + * + * For example, if the block is located within the bin, its position will + * be returned (unmodified). If the block is located to the left of the bin + * (y coordinate is within the bounds of the bin), then this will return + * the point on the left edge of the bin with the same y coordinate as the + * block. + * + * TODO: It may be a good idea to investigate placing blocks at the input + * or output pin locations of the bin. + */ + vtr::Point get_block_location_in_bin(APBlockId blk_id, + const vtr::Rect& bin_region, + const PartialPlacement& p_placement) const; + + /** + * @brief Resets all bins by emptying them. + */ + void empty_bins(); + + /** + * @brief Verifies that the bins were constructed correctly and that the + * utilization, overfill, underfill, and capacity are all correct. + * Returns false if there are any issues. + */ + bool verify() const; + + /** + * @brief Debug printer which prints a simple representation of the bins + * and their capacity to the log file. + */ + void print_bin_grid() const; + + private: + /// @brief The AP netlist of blocks which are filling the bins. + const APNetlist& ap_netlist_; + + /// @brief The bins created by this class. + FlatPlacementBins bins_; + + /// @brief The mass calculator used to compute the mass of the blocks and + /// physical tiles. + FlatPlacementMassCalculator mass_calculator_; + + /// @brief Spatial lookup for an (layer, x, y) position to the bin at that + /// location. + /// + /// Access: [0..grid.num_layers-1][0..grid.width-1][0..grid.height-1] + vtr::NdMatrix bin_spatial_lookup_; + + /// @brief The capacity of each bin. + vtr::vector bin_capacity_; + + /// @brief The utilization of each bin. + vtr::vector bin_utilization_; + + /// @brief The overfill of each bin. + vtr::vector bin_overfill_; + + /// @brief The underfill of each bin. + vtr::vector bin_underfill_; + + /// @brief The set of overfilled bins. + std::unordered_set overfilled_bins_; + + /// @brief The verbosity of log messages in this class. + const int log_verbosity_; +}; diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.cpp b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp new file mode 100644 index 00000000000..c99aaf29339 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.cpp @@ -0,0 +1,278 @@ +/** + * @file + * @author Alex Singer + * @date February 2024 + * @brief Implementation of the mass calculator used in the AP flow. + */ + +#include "flat_placement_mass_calculator.h" +#include +#include "ap_netlist.h" +#include "atom_netlist.h" +#include "globals.h" +#include "logic_types.h" +#include "physical_types.h" +#include "prepack.h" +#include "primitive_vector.h" +#include "vtr_log.h" + +/** + * @brief Get the scalar mass of the given model (primitive type). + * + * A model with a higher mass will take up more space in its bin which may force + * more spreading of that type of primitive. + * + * TODO: This will be made more complicated later. Models may be weighted based + * on some factors. + */ +static float get_model_mass(const t_model* model) { + // Currently, all models have a mass of one. + (void)model; + return 1.f; +} + +// This method is being forward-declared due to the double recursion below. +// Eventually this should be made into a non-recursive algorithm for performance, +// however this is not in a performance critical part of the code. +static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type); + +/** + * @brief Get the amount of primitives this mode can contain. + * + * This is part of a double recursion, since a mode contains primitives which + * themselves have modes. + */ +static PrimitiveVector calc_mode_capacity(const t_mode& mode) { + // Accumulate the capacities of all the pbs in this mode. + PrimitiveVector capacity; + for (int pb_child_idx = 0; pb_child_idx < mode.num_pb_type_children; pb_child_idx++) { + const t_pb_type& pb_type = mode.pb_type_children[pb_child_idx]; + PrimitiveVector pb_capacity = calc_pb_type_capacity(&pb_type); + // A mode may contain multiple pbs of the same type, multiply the + // capacity. + pb_capacity *= pb_type.num_pb; + capacity += pb_capacity; + } + return capacity; +} + +/** + * @brief Get the amount of primitives this pb can contain. + * + * This is the other part of the double recursion. A pb may have multiple modes. + * Modes are made of pbs. + */ +static PrimitiveVector calc_pb_type_capacity(const t_pb_type* pb_type) { + // Since a pb cannot be multiple modes at the same time, we do not + // accumulate the capacities of the mode. Instead we need to "mix" the two + // capacities as if the pb could choose either one. + PrimitiveVector capacity; + // If this is a leaf / primitive, create the base PrimitiveVector capacity. + if (pb_type->num_modes == 0) { + const t_model* model = pb_type->model; + VTR_ASSERT(model != nullptr); + VTR_ASSERT_DEBUG(model->index >= 0); + capacity.add_val_to_dim(get_model_mass(model), model->index); + return capacity; + } + // For now, we simply mix the capacities of modes by taking the max of each + // dimension of the capcities. This provides an upper-bound on the amount of + // primitives this pb can contain. + for (int mode = 0; mode < pb_type->num_modes; mode++) { + PrimitiveVector mode_capacity = calc_mode_capacity(pb_type->modes[mode]); + capacity = PrimitiveVector::max(capacity, mode_capacity); + } + return capacity; +} + +/** + * @brief Calculate the cpacity of the given logical block type. + */ +static PrimitiveVector calc_logical_block_type_capacity(const t_logical_block_type& logical_block_type) { + // If this logical block is empty, it cannot contain any primitives. + if (logical_block_type.is_empty()) + return PrimitiveVector(); + // The primitive capacity of a logical block is the primitive capacity of + // its root pb. + return calc_pb_type_capacity(logical_block_type.pb_type); +} + +/** + * @brief Get the primitive capacity of the given sub_tile. + * + * Sub_tiles may reuse logical blocks between one another, therefore this method + * requires that the capacities of all of the logical blocks have been + * pre-calculated and stored in the given vector. + * + * @param sub_tile The sub_tile to get the capacity of. + * @param logical_block_type_capacities The capacities of all logical block + * types. + */ +static PrimitiveVector calc_sub_tile_capacity(const t_sub_tile& sub_tile, + const std::vector& logical_block_type_capacities) { + // Similar to getting the primitive capacity of the pb, sub_tiles have many + // equivalent sites, but it can only be one of them at a time. Need to "mix" + // the capacities of the different sites this sub_tile may be. + PrimitiveVector capacity; + for (t_logical_block_type_ptr block_type : sub_tile.equivalent_sites) { + const PrimitiveVector& block_capacity = logical_block_type_capacities[block_type->index]; + // Currently, we take the max of each primitive dimension as an upper + // bound on the capacity of the sub_tile. + capacity = PrimitiveVector::max(capacity, block_capacity); + } + return capacity; +} + +/** + * @brief Get the primitive capacity of a tile of the given type. + * + * Tiles may reuse logical blocks between one another, therefore this method + * requires that the capacities of all of the logical blocks have been + * pre-calculated and stored in the given vector. + * + * @param tile_type The tile type to get the capacity of. + * @param logical_block_type_capacities The capacities of all logical block + * types. + */ +static PrimitiveVector calc_physical_tile_type_capacity(const t_physical_tile_type& tile_type, + const std::vector& logical_block_type_capacities) { + // Accumulate the capacities of all the sub_tiles in the given tile type. + PrimitiveVector capacity; + for (const t_sub_tile& sub_tile : tile_type.sub_tiles) { + PrimitiveVector sub_tile_capacity = calc_sub_tile_capacity(sub_tile, logical_block_type_capacities); + // A tile may contain many sub_tiles of the same type. Multiply by the + // number of sub_tiles of this type. + sub_tile_capacity *= sub_tile.capacity.total(); + capacity += sub_tile_capacity; + } + return capacity; +} + +/** + * @brief Get the primitive mass of the given block. + * + * This returns an M-dimensional vector with each entry indicating the mass of + * that primitive type in this block. M is the number of unique models + * (primitive types) in the architecture. + */ +static PrimitiveVector calc_block_mass(APBlockId blk_id, + const APNetlist& netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist) { + PrimitiveVector mass; + PackMoleculeId mol_id = netlist.block_molecule(blk_id); + const t_pack_molecule& mol = prepacker.get_molecule(mol_id); + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { + // See issue #2791, some of the atom_block_ids may be invalid. They can + // safely be ignored. + if (!atom_blk_id.is_valid()) + continue; + const t_model* model = atom_netlist.block_model(atom_blk_id); + VTR_ASSERT_DEBUG(model->index >= 0); + mass.add_val_to_dim(get_model_mass(model), model->index); + } + return mass; +} + +/** + * @brief Debug printing method to print the capacities of all logical blocks + * and physical tile types. + */ +static void print_capacities(const std::vector& logical_block_type_capacities, + const std::vector& physical_tile_type_capacities, + const std::vector& logical_block_types, + const std::vector& physical_tile_types) { + // Get a linear list of all models. + // TODO: I do not like using the global context here, but these models + // should be stable in VTR. If they were stored better, we may be + // able to pass them in. + std::vector all_models; + t_model* curr_model = g_vpr_ctx.device().arch->models; + while (curr_model != nullptr) { + if (curr_model->index >= (int)all_models.size()) + all_models.resize(curr_model->index + 1); + all_models[curr_model->index] = curr_model; + curr_model = curr_model->next; + } + curr_model = g_vpr_ctx.device().arch->model_library; + while (curr_model != nullptr) { + if (curr_model->index >= (int)all_models.size()) + all_models.resize(curr_model->index + 1); + all_models[curr_model->index] = curr_model; + curr_model = curr_model->next; + } + // Print the capacities. + VTR_LOG("Logical Block Type Capacities:\n"); + VTR_LOG("------------------------------\n"); + VTR_LOG("name\t"); + for (t_model* model : all_models) { + VTR_LOG("%s\t", model->name); + } + VTR_LOG("\n"); + for (const t_logical_block_type& block_type : logical_block_types) { + const PrimitiveVector& capacity = logical_block_type_capacities[block_type.index]; + VTR_LOG("%s\t", block_type.name.c_str()); + for (t_model* model : all_models) { + VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); + } + VTR_LOG("\n"); + } + VTR_LOG("\n"); + VTR_LOG("Physical Tile Type Capacities:\n"); + VTR_LOG("------------------------------\n"); + VTR_LOG("name\t"); + for (t_model* model : all_models) { + VTR_LOG("%s\t", model->name); + } + VTR_LOG("\n"); + for (const t_physical_tile_type& tile_type : physical_tile_types) { + const PrimitiveVector& capacity = physical_tile_type_capacities[tile_type.index]; + VTR_LOG("%s\t", tile_type.name.c_str()); + for (t_model* model : all_models) { + VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); + } + VTR_LOG("\n"); + } + VTR_LOG("\n"); + // TODO: Print the masses of each model. +} + +FlatPlacementMassCalculator::FlatPlacementMassCalculator(const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + int log_verbosity) + : physical_tile_type_capacity_(physical_tile_types.size()) + , logical_block_type_capacity_(logical_block_types.size()) + , block_mass_(ap_netlist.blocks().size()) + , log_verbosity_(log_verbosity) { + + // Precompute the capacity of each logical block type. + for (const t_logical_block_type& logical_block_type : logical_block_types) { + logical_block_type_capacity_[logical_block_type.index] = calc_logical_block_type_capacity(logical_block_type); + } + + // Precompute the capacity of each physical tile type. + for (const t_physical_tile_type& physical_tile_type : physical_tile_types) { + physical_tile_type_capacity_[physical_tile_type.index] = calc_physical_tile_type_capacity(physical_tile_type, logical_block_type_capacity_); + } + + // Precompute the mass of each block in the APNetlist + VTR_LOGV(log_verbosity_ >= 10, "Pre-computing the block masses...\n"); + for (APBlockId ap_block_id : ap_netlist.blocks()) { + block_mass_[ap_block_id] = calc_block_mass(ap_block_id, + ap_netlist, + prepacker, + atom_netlist); + } + VTR_LOGV(log_verbosity_ >= 10, "Finished pre-computing the block masses.\n"); + + // Print the precomputed block capacities. This can be helpful for debugging. + if (log_verbosity_ > 1) { + print_capacities(logical_block_type_capacity_, + physical_tile_type_capacity_, + logical_block_types, + physical_tile_types); + } +} diff --git a/vpr/src/analytical_place/flat_placement_mass_calculator.h b/vpr/src/analytical_place/flat_placement_mass_calculator.h new file mode 100644 index 00000000000..286b91dd743 --- /dev/null +++ b/vpr/src/analytical_place/flat_placement_mass_calculator.h @@ -0,0 +1,114 @@ +/** + * @file + * @author Alex Singer + * @date February 2024 + * @brief Mass calculation for AP blocks and logical/physical block/tile types + */ + +#pragma once + +#include +#include "ap_netlist_fwd.h" +#include "primitive_vector.h" +#include "vtr_assert.h" +#include "vtr_vector.h" + +class AtomNetlist; +class Prepacker; +struct t_logical_block_type; +struct t_physical_tile_type; + +/** + * @brief A calculator class which computes the M-dimensional mass of AP blocks + * and the capacity of tiles. + * + * Each atom in the Atom Netlist represents some model which may be implemented + * on the FPGA. The FPGA architecture has M models. Since an AP block may + * represent multiple atoms, its "mass" (the amount of "space" this block takes + * up) must be M-dimensional. For example, a LUT+FF molecule would have a mass + * of <1, 1> if LUTs and FFs were the only models in the architecture; while a + * single LUT would have a mass of <1, 0>. + * + * This class handles how the mass of the AP blocks are calculated. + * + * This class also handles how much capacity each tile in the FGPA has. This + * capacity is an approximation of how much M-dimensional mass that the tile + * can hold. Since tiles may have multiple modes, the actual capacity of the + * tiles change depending on what is in the tile. This class simplifies this + * to assume that the capacity does not change and approximates the theoretical + * mass that the tile should aim to hold. + */ +class FlatPlacementMassCalculator { + public: + /** + * @brief Construct the mass calculator. + * + * @param ap_netlist + * The netlist of AP blocks to compute the mass of. The mass of each + * block is precomputed in the constructor and loaded cheaply later. + * @param prepacker + * The prepacker used to pack atoms into the molecules. The AP netlist + * contains molecules; this class is needed to get information on these + * molecules. + * @param atom_netlist + * The netlist of atoms for the circuit. + * @param logical_block_types + * A list of all logical block types that can be implemented in the + * device. The capacity of each logical block type is precomputed to + * help compute the capacity of physical_tile_types. + * @param physical_tile_types + * A list of all physical_tile_types that exist on the FGPA. The + * capacity of each physical tile is precomputed in the constructor to + * be loaded cheaply later. + * @param log_verbosity + * The verbosity of log messages in the mass calculator. + */ + FlatPlacementMassCalculator(const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + int log_verbosity); + + /** + * @brief Get the M-dimensional capacity of the given physical tile type. + * + * This is an approximation based on the description of the tile in the + * architecture. + */ + inline const PrimitiveVector& get_physical_tile_type_capacity(size_t physical_tile_type_index) const { + VTR_ASSERT(physical_tile_type_index < physical_tile_type_capacity_.size()); + return physical_tile_type_capacity_[physical_tile_type_index]; + } + + /** + * @brief Get the M-dimensional capacity of the given logical block type. + */ + inline const PrimitiveVector& get_logical_block_type_capacity(size_t logical_block_type_index) const { + VTR_ASSERT(logical_block_type_index < logical_block_type_capacity_.size()); + return logical_block_type_capacity_[logical_block_type_index]; + } + + /** + * @brief Get the M-dimensional mass of the given AP block. + */ + inline const PrimitiveVector& get_block_mass(APBlockId blk_id) const { + VTR_ASSERT(blk_id.is_valid()); + return block_mass_[blk_id]; + } + + private: + /// @brief The capacity of each physical tile type, indexed by the index + /// of the physical_tile_type. + std::vector physical_tile_type_capacity_; + + /// @brief The capacity of each logical block type, indexed by the index + /// of the logical block type. + std::vector logical_block_type_capacity_; + + /// @brief The mass of each block in the AP netlist. + vtr::vector block_mass_; + + /// @brief The verbosity of log messages in the mass calculator. + const int log_verbosity_; +}; diff --git a/vpr/src/analytical_place/full_legalizer.cpp b/vpr/src/analytical_place/full_legalizer.cpp index e0850479118..767ac67e3d9 100644 --- a/vpr/src/analytical_place/full_legalizer.cpp +++ b/vpr/src/analytical_place/full_legalizer.cpp @@ -9,25 +9,38 @@ #include "full_legalizer.h" +#include #include +#include +#include #include #include -#include "partial_placement.h" +#include "PreClusterTimingManager.h" #include "ShowSetup.h" +#include "ap_flow_enums.h" #include "ap_netlist_fwd.h" +#include "blk_loc_registry.h" #include "check_netlist.h" #include "cluster_legalizer.h" #include "cluster_util.h" #include "clustered_netlist.h" +#include "device_grid.h" +#include "flat_placement_types.h" #include "globals.h" #include "initial_placement.h" +#include "load_flat_place.h" #include "logic_types.h" +#include "noc_place_utils.h" #include "pack.h" +#include "partial_placement.h" #include "physical_types.h" +#include "place.h" #include "place_and_route.h" #include "place_constraints.h" #include "place_macro.h" +#include "prepack.h" +#include "read_place.h" #include "verify_clustering.h" #include "verify_placement.h" #include "vpr_api.h" @@ -37,10 +50,47 @@ #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_ndmatrix.h" +#include "vtr_random.h" #include "vtr_strong_id.h" #include "vtr_time.h" #include "vtr_vector.h" +std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_legalizer_type, + const APNetlist& ap_netlist, + const AtomNetlist& atom_netlist, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const t_vpr_setup& vpr_setup, + const t_arch& arch, + const DeviceGrid& device_grid) { + switch (full_legalizer_type) { + case e_ap_full_legalizer::Naive: + return std::make_unique(ap_netlist, + atom_netlist, + prepacker, + pre_cluster_timing_manager, + vpr_setup, + arch, + device_grid); + case e_ap_full_legalizer::APPack: + return std::make_unique(ap_netlist, + atom_netlist, + prepacker, + pre_cluster_timing_manager, + vpr_setup, + arch, + device_grid); + case e_ap_full_legalizer::Basic_Min_Disturbance: + VTR_LOG("Basic Minimum Disturbance Full Legalizer selected!\n"); + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Basic Min. Disturbance Full Legalizer has not been implemented yet."); + + default: + VPR_FATAL_ERROR(VPR_ERROR_AP, + "Unrecognized full legalizer type"); + } +} + namespace { /// @brief A unique ID for each root tile on the device. @@ -60,17 +110,16 @@ typedef vtr::StrongId DeviceTileId; * unify the two flows and make it more stable! */ class APClusterPlacer { -private: + private: // Get the macro for the given cluster block. t_pl_macro get_macro(ClusterBlockId clb_blk_id) { - const auto& place_macros = g_vpr_ctx.placement().blk_loc_registry().place_macros(); // Basically stolen from initial_placement.cpp:place_one_block // TODO: Make this a cleaner interface and share the code. - int imacro = place_macros.get_imacro_from_iblk(clb_blk_id); + int imacro = place_macros_.get_imacro_from_iblk(clb_blk_id); // If this block is part of a macro, return it. if (imacro != -1) { - return place_macros[imacro]; + return place_macros_[imacro]; } // If not, create a "fake" macro with a single element. t_pl_macro_member macro_member; @@ -83,39 +132,34 @@ class APClusterPlacer { return pl_macro; } -public: + const PlaceMacros& place_macros_; + + public: /** * @brief Constructor for the APClusterPlacer * * Initializes internal and global state necessary to place clusters on the * FPGA device. */ - APClusterPlacer() { - // FIXME: This was stolen from place/place.cpp - // it used a static method, just taking what I think I will need. + APClusterPlacer(const PlaceMacros& place_macros, + const char* constraints_file) + : place_macros_(place_macros) { + // Initialize the block loc registry. auto& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry(); - const auto& directs = g_vpr_ctx.device().arch->directs; - - init_placement_context(blk_loc_registry, directs); - - // stolen from place/place.cpp:alloc_and_load_try_swap_structs - // FIXME: set cube_bb to false by hand, should be passed in. - g_vpr_ctx.mutable_placement().cube_bb = false; - g_vpr_ctx.mutable_placement().compressed_block_grids = create_compressed_block_grids(); - - // TODO: The next few steps will be basically a direct copy of the initial - // placement code since it does everything we need! It would be nice - // to share the code. - - // Clear the grid locations (stolen from initial_placement) - blk_loc_registry.clear_all_grid_locs(); - - // Deal with the placement constraints. - propagate_place_constraints(blk_loc_registry.place_macros()); + blk_loc_registry.init(); + // Place the fixed blocks and mark them as fixed. mark_fixed_blocks(blk_loc_registry); - alloc_and_load_compressed_cluster_constraints(); + // Read the constraint file and place fixed blocks. + if (strlen(constraints_file) != 0) { + read_constraints(constraints_file, blk_loc_registry); + } + + // Update the block loc registry with the fixed / moveable blocks. + // We can do this here since the fixed blocks will not change beyond + // this point. + blk_loc_registry.alloc_and_load_movable_blocks(); } /** @@ -202,7 +246,8 @@ class APClusterPlacer { * @param primitive_candidate_block_types A list of candidate block types for * the given molecule. */ -static LegalizationClusterId create_new_cluster(t_pack_molecule* seed_molecule, +static LegalizationClusterId create_new_cluster(PackMoleculeId seed_molecule_id, + const Prepacker& prepacker, ClusterLegalizer& cluster_legalizer, const std::map>& primitive_candidate_block_types) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); @@ -212,8 +257,10 @@ static LegalizationClusterId create_new_cluster(t_pack_molecule* seed_molecule, // placed into. // TODO: The original implementation sorted based on balance. Perhaps this // should do the same. - AtomBlockId root_atom = seed_molecule->atom_block_ids[seed_molecule->root]; - const t_model* root_model = atom_ctx.nlist.block_model(root_atom); + VTR_ASSERT(seed_molecule_id.is_valid()); + const t_pack_molecule& seed_molecule = prepacker.get_molecule(seed_molecule_id); + AtomBlockId root_atom = seed_molecule.atom_block_ids[seed_molecule.root]; + const t_model* root_model = atom_ctx.netlist().block_model(root_atom); auto itr = primitive_candidate_block_types.find(root_model); VTR_ASSERT(itr != primitive_candidate_block_types.end()); @@ -224,7 +271,7 @@ static LegalizationClusterId create_new_cluster(t_pack_molecule* seed_molecule, for (int mode = 0; mode < num_modes; mode++) { e_block_pack_status pack_status = e_block_pack_status::BLK_STATUS_UNDEFINED; LegalizationClusterId new_cluster_id; - std::tie(pack_status, new_cluster_id) = cluster_legalizer.start_new_cluster(seed_molecule, type, mode); + std::tie(pack_status, new_cluster_id) = cluster_legalizer.start_new_cluster(seed_molecule_id, type, mode); if (pack_status == e_block_pack_status::BLK_PASSED) return new_cluster_id; } @@ -235,24 +282,20 @@ static LegalizationClusterId create_new_cluster(t_pack_molecule* seed_molecule, return LegalizationClusterId(); } -void FullLegalizer::create_clusters(const PartialPlacement& p_placement) { +void NaiveFullLegalizer::create_clusters(const PartialPlacement& p_placement) { // PACKING: // Initialize the cluster legalizer (Packing) // FIXME: The legalization strategy is currently set to full. Should handle // this better to make it faster. - t_pack_high_fanout_thresholds high_fanout_thresholds(packer_opts_.high_fanout_threshold); + t_pack_high_fanout_thresholds high_fanout_thresholds(vpr_setup_.PackerOpts.high_fanout_threshold); ClusterLegalizer cluster_legalizer(atom_netlist_, prepacker_, - logical_block_types_, - lb_type_rr_graphs_, - user_models_, - library_models_, - packer_opts_.target_external_pin_util, + vpr_setup_.PackerRRGraph, + vpr_setup_.PackerOpts.target_external_pin_util, high_fanout_thresholds, ClusterLegalizationStrategy::FULL, - packer_opts_.enable_pin_feasibility_filter, - packer_opts_.feasible_block_array_size, - packer_opts_.pack_verbosity); + vpr_setup_.PackerOpts.enable_pin_feasibility_filter, + vpr_setup_.PackerOpts.pack_verbosity); // Create clusters for each tile. // Start by giving each root tile a unique ID. size_t grid_width = device_grid_.width(); @@ -290,33 +333,29 @@ void FullLegalizer::create_clusters(const PartialPlacement& p_placement) { for (size_t tile_id_idx = 0; tile_id_idx < num_device_tiles; tile_id_idx++) { DeviceTileId tile_id = DeviceTileId(tile_id_idx); // Create the molecule list - std::list mol_list; + std::list mol_list; for (APBlockId ap_blk_id : blocks_in_tiles[tile_id]) { - // FIXME: The netlist stores a const pointer to mol; but the cluster - // legalizer does not accept this. Need to fix one or the other. - // For now, using const_cast. - t_pack_molecule* mol = const_cast(ap_netlist_.block_molecule(ap_blk_id)); - mol_list.push_back(mol); + mol_list.push_back(ap_netlist_.block_molecule(ap_blk_id)); } // Clustering algorithm: Create clusters one at a time. while (!mol_list.empty()) { // Arbitrarily choose the first molecule as a seed molecule. - t_pack_molecule* seed_mol = mol_list.front(); + PackMoleculeId seed_mol_id = mol_list.front(); mol_list.pop_front(); // Use the seed molecule to create a cluster for this tile. - LegalizationClusterId new_cluster_id = create_new_cluster(seed_mol, cluster_legalizer, primitive_candidate_block_types); + LegalizationClusterId new_cluster_id = create_new_cluster(seed_mol_id, prepacker_, cluster_legalizer, primitive_candidate_block_types); // Insert all molecules that you can into the cluster. // NOTE: If the mol_list was somehow sorted, we can just stop at // first failure! auto it = mol_list.begin(); while (it != mol_list.end()) { - t_pack_molecule* mol = *it; - if (!cluster_legalizer.is_molecule_compatible(mol, new_cluster_id)) { + PackMoleculeId mol_id = *it; + if (!cluster_legalizer.is_molecule_compatible(mol_id, new_cluster_id)) { ++it; continue; } // Try to insert it. If successful, remove from list. - e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(mol, new_cluster_id); + e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(mol_id, new_cluster_id); if (pack_status == e_block_pack_status::BLK_PASSED) { it = mol_list.erase(it); } else { @@ -330,30 +369,31 @@ void FullLegalizer::create_clusters(const PartialPlacement& p_placement) { // Check and output the clustering. std::unordered_set is_clock = alloc_and_load_is_clock(); - check_and_output_clustering(cluster_legalizer, packer_opts_, is_clock, arch_); + check_and_output_clustering(cluster_legalizer, vpr_setup_.PackerOpts, is_clock, &arch_); // Reset the cluster legalizer. This is required to load the packing. cluster_legalizer.reset(); // Regenerate the clustered netlist from the file generated previously. // FIXME: This writing and loading from a file is wasteful. Should generate // the clusters directly from the cluster legalizer. - vpr_load_packing(vpr_setup_, *arch_); - load_cluster_constraints(); + vpr_load_packing(vpr_setup_, arch_); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; // Verify the packing and print some info - check_netlist(packer_opts_.pack_verbosity); + check_netlist(vpr_setup_.PackerOpts.pack_verbosity); writeClusteredNetlistStats(vpr_setup_.FileNameOpts.write_block_usage); print_pb_type_count(clb_nlist); } -void FullLegalizer::place_clusters(const ClusteredNetlist& clb_nlist, - const PartialPlacement& p_placement) { +void NaiveFullLegalizer::place_clusters(const ClusteredNetlist& clb_nlist, + const PlaceMacros& place_macros, + const PartialPlacement& p_placement) { // PLACING: // Create a lookup from the AtomBlockId to the APBlockId vtr::vector atom_to_ap_block(atom_netlist_.blocks().size()); for (APBlockId ap_blk_id : ap_netlist_.blocks()) { - const t_pack_molecule* blk_mol = ap_netlist_.block_molecule(ap_blk_id); - for (AtomBlockId atom_blk_id : blk_mol->atom_block_ids) { + PackMoleculeId blk_mol_id = ap_netlist_.block_molecule(ap_blk_id); + const t_pack_molecule& blk_mol = prepacker_.get_molecule(blk_mol_id); + for (AtomBlockId atom_blk_id : blk_mol.atom_block_ids) { // See issue #2791, some of the atom_block_ids may be invalid. They // can safely be ignored. if (!atom_blk_id.is_valid()) @@ -367,7 +407,7 @@ void FullLegalizer::place_clusters(const ClusteredNetlist& clb_nlist, // Move the clusters to where they want to be first. // TODO: The fixed clusters should probably be moved first for legality // reasons. - APClusterPlacer ap_cluster_placer; + APClusterPlacer ap_cluster_placer(place_macros, vpr_setup_.PlacerOpts.constraints_file.c_str()); std::vector unplaced_clusters; for (ClusterBlockId cluster_blk_id : clb_nlist.blocks()) { // Assume that the cluster will always want to be placed wherever the @@ -408,7 +448,7 @@ void FullLegalizer::place_clusters(const ClusteredNetlist& clb_nlist, // - This may be needed to perform SA. Not needed right now. } -void FullLegalizer::legalize(const PartialPlacement& p_placement) { +void NaiveFullLegalizer::legalize(const PartialPlacement& p_placement) { // Create a scoped timer for the full legalizer vtr::ScopedStartFinishTimer full_legalizer_timer("AP Full Legalizer"); @@ -428,8 +468,17 @@ void FullLegalizer::legalize(const PartialPlacement& p_placement) { // TODO: Eventually should be returned from the create_clusters method. const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + // Initialize the placement context. + g_vpr_ctx.mutable_placement().init_placement_context(vpr_setup_.PlacerOpts, + arch_.directs); + + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; + + // Update the floorplanning context with the macro information. + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_pre_place(place_macros); + // Place the clusters based on where the atoms want to be placed. - place_clusters(clb_nlist, p_placement); + place_clusters(clb_nlist, place_macros, p_placement); // Verify that the placement created by the full legalizer is valid. unsigned num_placement_errors = verify_placement(g_vpr_ctx); @@ -448,3 +497,86 @@ void FullLegalizer::legalize(const PartialPlacement& p_placement) { post_place_sync(); } +void APPack::legalize(const PartialPlacement& p_placement) { + // Create a scoped timer for the full legalizer + vtr::ScopedStartFinishTimer full_legalizer_timer("AP Full Legalizer"); + + // Convert the Partial Placement (APNetlist) to a flat placement (AtomNetlist). + FlatPlacementInfo flat_placement_info(atom_netlist_); + for (APBlockId ap_blk_id : ap_netlist_.blocks()) { + PackMoleculeId mol_id = ap_netlist_.block_molecule(ap_blk_id); + const t_pack_molecule& mol = prepacker_.get_molecule(mol_id); + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + flat_placement_info.blk_x_pos[atom_blk_id] = p_placement.block_x_locs[ap_blk_id]; + flat_placement_info.blk_y_pos[atom_blk_id] = p_placement.block_y_locs[ap_blk_id]; + flat_placement_info.blk_layer[atom_blk_id] = p_placement.block_layer_nums[ap_blk_id]; + flat_placement_info.blk_sub_tile[atom_blk_id] = p_placement.block_sub_tiles[ap_blk_id]; + } + } + + // Run the Packer stage with the flat placement as a hint. + try_pack(vpr_setup_.PackerOpts, + vpr_setup_.AnalysisOpts, + arch_, + vpr_setup_.PackerRRGraph, + prepacker_, + pre_cluster_timing_manager_, + flat_placement_info); + + // The Packer stores the clusters into a .net file. Load the packing file. + // FIXME: This should be removed. Reading from a file is strange. + vpr_load_packing(vpr_setup_, arch_); + + // Setup the global variables for placement. + g_vpr_ctx.mutable_placement().init_placement_context(vpr_setup_.PlacerOpts, arch_.directs); + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_pre_place(*g_vpr_ctx.placement().place_macros); + + // The placement will be stored in the global block loc registry. + BlkLocRegistry& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry(); + + // Create the noc cost handler used in the initial placer. + std::optional noc_cost_handler; + if (vpr_setup_.NocOpts.noc) + noc_cost_handler.emplace(blk_loc_registry.block_locs()); + + // Create the RNG container for the initial placer. + vtr::RngContainer rng(vpr_setup_.PlacerOpts.seed); + + // Run the initial placer on the clusters created by the packer, using the + // flat placement information from the global placer to guide where to place + // the clusters. + initial_placement(vpr_setup_.PlacerOpts, + vpr_setup_.PlacerOpts.constraints_file.c_str(), + vpr_setup_.NocOpts, + blk_loc_registry, + *g_vpr_ctx.placement().place_macros, + noc_cost_handler, + flat_placement_info, + rng); + + // Log some information on how good the reconstruction was. + log_flat_placement_reconstruction_info(flat_placement_info, + blk_loc_registry.block_locs(), + g_vpr_ctx.clustering().atoms_lookup, + g_vpr_ctx.atom().lookup(), + atom_netlist_, + g_vpr_ctx.clustering().clb_nlist); + + // Verify that the placement is valid for the VTR flow. + unsigned num_errors = verify_placement(blk_loc_registry, + *g_vpr_ctx.placement().place_macros, + g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.device().grid, + g_vpr_ctx.floorplanning().cluster_constraints); + if (num_errors != 0) { + VPR_ERROR(VPR_ERROR_AP, + "\nCompleted placement consistency check, %d errors found.\n" + "Aborting program.\n", + num_errors); + } + + // Synchronize the pins in the clusters after placement. + post_place_sync(); +} diff --git a/vpr/src/analytical_place/full_legalizer.h b/vpr/src/analytical_place/full_legalizer.h index e5f72586b28..57baef27fc9 100644 --- a/vpr/src/analytical_place/full_legalizer.h +++ b/vpr/src/analytical_place/full_legalizer.h @@ -9,7 +9,8 @@ #pragma once -#include +#include +#include "ap_flow_enums.h" // Forward declarations class APNetlist; @@ -17,50 +18,37 @@ class AtomNetlist; class ClusteredNetlist; class DeviceGrid; class PartialPlacement; +class PlaceMacros; +class PreClusterTimingManager; class Prepacker; struct t_arch; -struct t_lb_type_rr_node; -struct t_logical_block_type; -struct t_model; -struct t_packer_opts; struct t_vpr_setup; /** * @brief The full legalizer in an AP flow * * Given a valid partial placement (of any level of legality), will produce a - * fully legal clustering and placement for use in the rest of the VTR flow. + * fully legal clustering and clustered placement for use in the rest of the + * VTR flow. */ class FullLegalizer { -public: - /** - * @brief Constructor of the Full Legalizer class. - * - * Brings in all the necessary state here. This is the state needed from the - * AP Context. the Packer Context, and the Placer Context. - */ + public: + virtual ~FullLegalizer() {} + FullLegalizer(const APNetlist& ap_netlist, - t_vpr_setup& vpr_setup, - const DeviceGrid& device_grid, - const t_arch* arch, const AtomNetlist& atom_netlist, const Prepacker& prepacker, - const std::vector& logical_block_types, - std::vector* lb_type_rr_graphs, - const t_model* user_models, - const t_model* library_models, - const t_packer_opts& packer_opts) - : ap_netlist_(ap_netlist), - vpr_setup_(vpr_setup), - device_grid_(device_grid), - arch_(arch), - atom_netlist_(atom_netlist), - prepacker_(prepacker), - logical_block_types_(logical_block_types), - lb_type_rr_graphs_(lb_type_rr_graphs), - user_models_(user_models), - library_models_(library_models), - packer_opts_(packer_opts) {} + const PreClusterTimingManager& pre_cluster_timing_manager, + const t_vpr_setup& vpr_setup, + const t_arch& arch, + const DeviceGrid& device_grid) + : ap_netlist_(ap_netlist) + , atom_netlist_(atom_netlist) + , prepacker_(prepacker) + , pre_cluster_timing_manager_(pre_cluster_timing_manager) + , vpr_setup_(vpr_setup) + , arch_(arch) + , device_grid_(device_grid) {} /** * @brief Perform legalization on the given partial placement solution @@ -69,9 +57,65 @@ class FullLegalizer { * This implies that all blocks are placed on the * device grid and fixed blocks are observed. */ - void legalize(const PartialPlacement& p_placement); + virtual void legalize(const PartialPlacement& p_placement) = 0; + + protected: + /// @brief The AP Netlist to fully legalize the flat placement of. + const APNetlist& ap_netlist_; + + /// @brief The Atom Netlist used to generate the AP Netlist. + const AtomNetlist& atom_netlist_; + + /// @brief The Prepacker used to create molecules from the Atom Netlist. + const Prepacker& prepacker_; + + /// @brief Pre-Clustering timing manager, hold pre-computed delay information + /// at the primitive level prior to packing. + const PreClusterTimingManager& pre_cluster_timing_manager_; -private: + /// @brief The VPR setup options passed into the VPR flow. This must be + /// mutable since some parts of packing modify the options. + const t_vpr_setup& vpr_setup_; + + /// @brief Information on the architecture of the FPGA. + const t_arch& arch_; + + /// @brief The device grid which records where clusters can be placed. + const DeviceGrid& device_grid_; +}; + +/** + * @brief A factory method which creates a Full Legalizer of the given type. + */ +std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_legalizer_type, + const APNetlist& ap_netlist, + const AtomNetlist& atom_netlist, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const t_vpr_setup& vpr_setup, + const t_arch& arch, + const DeviceGrid& device_grid); + +/** + * @brief The Naive Full Legalizer. + * + * This Full Legalizer will try to create clusters exactly where they want to + * according to the Partial Placement. It will grow clusters from atoms that + * are placed in the same tile, then it will try to place the cluster at that + * location. If a location cannot be found, once all other clusters have tried + * to be placed, it will try to find anywhere the cluster will fit and place it + * there. + */ +class NaiveFullLegalizer : public FullLegalizer { + public: + using FullLegalizer::FullLegalizer; + + /** + * @brief Perform naive full legalization. + */ + void legalize(const PartialPlacement& p_placement) final; + + private: /** * @brief Helper method to create the clusters from the given partial * placement. @@ -85,26 +129,35 @@ class FullLegalizer { * placement. */ void place_clusters(const ClusteredNetlist& clb_nlist, + const PlaceMacros& place_macros, const PartialPlacement& p_placement); - - // AP Context Info - const APNetlist& ap_netlist_; - // Overall Setup Info - // FIXME: I do not like bringing all of this in. Perhaps clean up the methods - // that use it. - t_vpr_setup& vpr_setup_; - // Device Context Info - const DeviceGrid& device_grid_; - const t_arch* arch_; - // Packing Context Info - const AtomNetlist& atom_netlist_; - const Prepacker& prepacker_; - const std::vector& logical_block_types_; - std::vector* lb_type_rr_graphs_; - const t_model* user_models_; - const t_model* library_models_; - const t_packer_opts& packer_opts_; - // Placement Context Info - // TODO: Populate this once the placer is cleaned up some. }; +/** + * @brief APPack: A flat-placement-informed Packer Placer. + * + * The idea of APPack is to use the flat-placement information generated by the + * AP Flow to guide the Packer and Placer to a better solution. + * + * In the Packer, the flat-placement can provide more context for the clusters + * to pull in atoms that want to be near the other atoms in the cluster, and + * repell atoms that are far apart. This can potentially make better clusters + * than a Packer that does not know that information. + * + * In the Placer, the flat-placement can help decide where clusters of atoms + * want to be placed. If this placement is then fed into a Simulated Annealing + * based Detailed Placement step, this would enable it to converge on a better + * answer faster. + */ +class APPack : public FullLegalizer { + public: + using FullLegalizer::FullLegalizer; + + /** + * @brief Run APPack. + * + * This will call the Packer and Placer using the options provided by the + * user for these stages in VPR. + */ + void legalize(const PartialPlacement& p_placement) final; +}; diff --git a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp index 34207e88145..75c3361ec3d 100644 --- a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp +++ b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp @@ -16,7 +16,6 @@ #include "prepack.h" #include "region.h" #include "user_place_constraints.h" -#include "vpr_types.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_time.h" @@ -40,10 +39,11 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, // Each net has the exact same name as in the atom netlist for (AtomBlockId atom_blk_id : atom_netlist.blocks()) { // Get the molecule of this block - t_pack_molecule* mol = prepacker.get_atom_molecule(atom_blk_id); + PackMoleculeId molecule_id = prepacker.get_atom_molecule(atom_blk_id); + const t_pack_molecule& mol = prepacker.get_molecule(molecule_id); // Create the AP block (if not already done) - const std::string& first_blk_name = atom_netlist.block_name(mol->atom_block_ids[0]); - APBlockId ap_blk_id = ap_netlist.create_block(first_blk_name, mol); + const std::string& first_blk_name = atom_netlist.block_name(mol.atom_block_ids[0]); + APBlockId ap_blk_id = ap_netlist.create_block(first_blk_name, molecule_id); // Add the ports and pins of this block to the supernode for (AtomPortId atom_port_id : atom_netlist.block_ports(atom_blk_id)) { BitIndex port_width = atom_netlist.port_width(atom_port_id); @@ -68,8 +68,9 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, // Fix the block locations given by the VPR constraints for (APBlockId ap_blk_id : ap_netlist.blocks()) { - const t_pack_molecule* mol = ap_netlist.block_molecule(ap_blk_id); - for (AtomBlockId mol_atom_blk_id : mol->atom_block_ids) { + PackMoleculeId molecule_id = ap_netlist.block_molecule(ap_blk_id); + const t_pack_molecule& mol = prepacker.get_molecule(molecule_id); + for (AtomBlockId mol_atom_blk_id : mol.atom_block_ids) { PartitionId part_id = constraints.get_atom_partition(mol_atom_blk_id); if (!part_id.is_valid()) continue; @@ -88,8 +89,13 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, const vtr::Rect& region_rect = region.get_rect(); VTR_ASSERT(region_rect.xmin() == region_rect.xmax() && "AP: Expect each region to be a single point in x!"); VTR_ASSERT(region_rect.ymin() == region_rect.ymax() && "AP: Expect each region to be a single point in y!"); - int blk_x_loc = region_rect.xmin(); - int blk_y_loc = region_rect.ymin(); + // Here we offset by 0.5 to put the fixed point in the center of the + // tile (assuming the tile is 1x1). + // TODO: Think about what to do when the user fixes blocks to large + // tiles. However, this solution will at least keep the atoms + // away from the edge of tiles. + float blk_x_loc = region_rect.xmin() + 0.5f; + float blk_y_loc = region_rect.ymin() + 0.5f; // Get the layer. VTR_ASSERT(region.get_layer_range().first == region.get_layer_range().second && "AP: Expect each region to be a single point in layer!"); int blk_layer_num = region.get_layer_range().first; @@ -172,4 +178,3 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, return ap_netlist; } - diff --git a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h index f03055a826d..ed5ae7bb0d1 100644 --- a/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h +++ b/vpr/src/analytical_place/gen_ap_netlist_from_atoms.h @@ -27,4 +27,3 @@ class UserPlaceConstraints; APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist, const Prepacker& prepacker, const UserPlaceConstraints& constraints); - diff --git a/vpr/src/analytical_place/global_placer.cpp b/vpr/src/analytical_place/global_placer.cpp index d2fbfe42d11..d9131e85308 100644 --- a/vpr/src/analytical_place/global_placer.cpp +++ b/vpr/src/analytical_place/global_placer.cpp @@ -8,38 +8,156 @@ #include "global_placer.h" #include +#include #include +#include #include "analytical_solver.h" +#include "ap_flow_enums.h" #include "ap_netlist.h" +#include "ap_netlist_fwd.h" +#include "atom_netlist.h" +#include "device_grid.h" +#include "flat_placement_bins.h" +#include "flat_placement_density_manager.h" +#include "globals.h" #include "partial_legalizer.h" #include "partial_placement.h" -#include "vpr_error.h" +#include "physical_types.h" +#include "primitive_vector.h" #include "vtr_log.h" #include "vtr_time.h" -std::unique_ptr make_global_placer(e_global_placer placer_type, - const APNetlist& netlist) { - // Based on the placer type passed in, build the global placer. - switch (placer_type) { - case e_global_placer::SimPL: - return std::make_unique(netlist); - default: - VPR_FATAL_ERROR(VPR_ERROR_AP, - "Unrecognized global placer type"); - - } +std::unique_ptr make_global_placer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) { + return std::make_unique(analytical_solver_type, + partial_legalizer_type, + ap_netlist, + prepacker, + atom_netlist, + device_grid, + logical_block_types, + physical_tile_types, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity); } -SimPLGlobalPlacer::SimPLGlobalPlacer(const APNetlist& netlist) : GlobalPlacer(netlist) { +SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) + : GlobalPlacer(ap_netlist, log_verbosity) { // This can be a long method. Good to time this to see how long it takes to // construct the global placer. vtr::ScopedStartFinishTimer global_placer_building_timer("Constructing Global Placer"); + // Build the solver. - solver_ = make_analytical_solver(e_analytical_solver::QP_HYBRID, - netlist); + VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the solver...\n"); + solver_ = make_analytical_solver(analytical_solver_type, + ap_netlist_, + device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity_); + + // Build the density manager used by the partial legalizer. + VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the density manager...\n"); + density_manager_ = std::make_shared(ap_netlist_, + prepacker, + atom_netlist, + device_grid, + logical_block_types, + physical_tile_types, + log_verbosity_); + // Build the partial legalizer - partial_legalizer_ = make_partial_legalizer(e_partial_legalizer::FLOW_BASED, - netlist); + VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the partial legalizer...\n"); + partial_legalizer_ = make_partial_legalizer(partial_legalizer_type, + ap_netlist_, + density_manager_, + prepacker, + log_verbosity_); +} + +/** + * @brief Helper method to print the statistics on the given partial placement. + */ +static void print_placement_stats(const PartialPlacement& p_placement, + const APNetlist& ap_netlist, + FlatPlacementDensityManager& density_manager) { + // Print the placement HPWL + VTR_LOG("\tPlacement HPWL: %f\n", p_placement.get_hpwl(ap_netlist)); + + // Print density information. Need to reset the density manager to ensure + // the data is valid. + density_manager.import_placement_into_bins(p_placement); + + // Print the number of overfilled bins. + size_t num_overfilled_bins = density_manager.get_overfilled_bins().size(); + VTR_LOG("\tNumber of overfilled bins: %zu\n", num_overfilled_bins); + + // Print the average overfill + float total_overfill = 0.0f; + for (FlatPlacementBinId bin_id : density_manager.get_overfilled_bins()) { + total_overfill += density_manager.get_bin_overfill(bin_id).manhattan_norm(); + } + float avg_overfill = 0.0f; + if (num_overfilled_bins != 0) + avg_overfill = total_overfill / static_cast(num_overfilled_bins); + VTR_LOG("\tAverage overfill magnitude: %f\n", avg_overfill); + + // Print the number of overfilled tiles per type. + const auto& physical_tile_types = g_vpr_ctx.device().physical_tile_types; + const auto& device_grid = g_vpr_ctx.device().grid; + std::vector overfilled_tiles_by_type(physical_tile_types.size(), 0); + for (FlatPlacementBinId bin_id : density_manager.get_overfilled_bins()) { + const auto& bin_region = density_manager.flat_placement_bins().bin_region(bin_id); + auto tile_loc = t_physical_tile_loc((int)bin_region.xmin(), + (int)bin_region.ymin(), + 0); + auto tile_type = device_grid.get_physical_type(tile_loc); + overfilled_tiles_by_type[tile_type->index]++; + } + VTR_LOG("\tOverfilled bins by tile type:\n"); + for (size_t type_idx = 0; type_idx < physical_tile_types.size(); type_idx++) { + VTR_LOG("\t\t%10s: %zu\n", + physical_tile_types[type_idx].name.c_str(), + overfilled_tiles_by_type[type_idx]); + } + + // Count the number of blocks that were placed in a bin which they cannot + // physically be placed into (according to their mass). + unsigned num_misplaced_blocks = 0; + for (FlatPlacementBinId bin_id : density_manager.get_overfilled_bins()) { + for (APBlockId ap_blk_id : density_manager.flat_placement_bins().bin_contained_blocks(bin_id)) { + // Get the blk mass and project it onto the capacity of its bin. + PrimitiveVector blk_mass = density_manager.mass_calculator().get_block_mass(ap_blk_id); + PrimitiveVector projected_mass = blk_mass; + projected_mass.project(density_manager.get_bin_capacity(bin_id)); + // If the projected mass does not match its match, this implies that + // there this block does not belong in this bin. + if (projected_mass != blk_mass) + num_misplaced_blocks++; + } + } + VTR_LOG("\tNumber of blocks in an incompatible bin: %zu\n", num_misplaced_blocks); } /** @@ -94,7 +212,17 @@ PartialPlacement SimPLGlobalPlacer::place() { if (log_verbosity_ >= 1) print_SimPL_status_header(); // Initialialize the partial placement object. - PartialPlacement p_placement(netlist_); + PartialPlacement p_placement(ap_netlist_); + + float total_time_spent_in_solver = 0.0f; + float total_time_spent_in_legalizer = 0.0f; + + // Create a partial placement object to store the best placement found during + // global placement. It is possible for the global placement to hit a minimum + // in the middle of its iterations, this lets us keep that solution. + PartialPlacement best_p_placement(ap_netlist_); + double best_ub_hpwl = std::numeric_limits::max(); + // Run the global placer. for (size_t i = 0; i < max_num_iterations_; i++) { float iter_start_time = runtime_timer.elapsed_sec(); @@ -103,13 +231,16 @@ PartialPlacement SimPLGlobalPlacer::place() { float solver_start_time = runtime_timer.elapsed_sec(); solver_->solve(i, p_placement); float solver_end_time = runtime_timer.elapsed_sec(); - double lb_hpwl = p_placement.get_hpwl(netlist_); + double lb_hpwl = p_placement.get_hpwl(ap_netlist_); // Run the legalizer. float legalizer_start_time = runtime_timer.elapsed_sec(); partial_legalizer_->legalize(p_placement); float legalizer_end_time = runtime_timer.elapsed_sec(); - double ub_hpwl = p_placement.get_hpwl(netlist_); + double ub_hpwl = p_placement.get_hpwl(ap_netlist_); + + total_time_spent_in_solver += solver_end_time - solver_start_time; + total_time_spent_in_legalizer += legalizer_end_time - legalizer_start_time; // Print some stats if (log_verbosity_ >= 1) { @@ -120,15 +251,37 @@ PartialPlacement SimPLGlobalPlacer::place() { iter_end_time - iter_start_time); } + // If this placement is better than the best we have seen, save it. + if (ub_hpwl < best_ub_hpwl) { + best_ub_hpwl = ub_hpwl; + best_p_placement = p_placement; + } + // Exit condition: If the upper-bound and lower-bound HPWLs are // sufficiently close together then stop. double hpwl_relative_gap = (ub_hpwl - lb_hpwl) / ub_hpwl; if (hpwl_relative_gap < target_hpwl_relative_gap_) break; } + + // Print statistics on the solver used. + solver_->print_statistics(); + + // Print statistics on the partial legalizer used. + partial_legalizer_->print_statistics(); + + VTR_LOG("Global Placer Statistics:\n"); + VTR_LOG("\tTime spent in solver: %g seconds\n", total_time_spent_in_solver); + VTR_LOG("\tTime spent in legalizer: %g seconds\n", total_time_spent_in_legalizer); + + // Print some statistics on the final placement. + VTR_LOG("Placement after Global Placement:\n"); + print_placement_stats(best_p_placement, + ap_netlist_, + *density_manager_); + // Return the placement from the final iteration. // TODO: investigate saving the best solution found so far. It should be // cheap to save a copy of the PartialPlacement object. - return p_placement; + return best_p_placement; } - diff --git a/vpr/src/analytical_place/global_placer.h b/vpr/src/analytical_place/global_placer.h index 0628b9b0d50..7772aa302bb 100644 --- a/vpr/src/analytical_place/global_placer.h +++ b/vpr/src/analytical_place/global_placer.h @@ -15,19 +15,17 @@ #pragma once #include +#include "ap_flow_enums.h" +#include "flat_placement_density_manager.h" +#include "partial_legalizer.h" // Forward declarations class APNetlist; class AnalyticalSolver; -class PartialPlacement; class PartialLegalizer; - -/** - * @brief Enumeration of all of the global placers currently implemented in VPR. - */ -enum class e_global_placer { - SimPL // Global placer based on the SimPL paper. -}; +class Prepacker; +class PreClusterTimingManager; +struct PartialPlacement; /** * @brief The Global Placer base class @@ -38,7 +36,7 @@ enum class e_global_placer { * placers. */ class GlobalPlacer { -public: + public: virtual ~GlobalPlacer() {} /** @@ -50,9 +48,9 @@ class GlobalPlacer { * @param log_verbosity The verbosity of log messages in the Global * Placer. */ - GlobalPlacer(const APNetlist& netlist, int log_verbosity = 1) - : netlist_(netlist), - log_verbosity_(log_verbosity) {} + GlobalPlacer(const APNetlist& ap_netlist, int log_verbosity) + : ap_netlist_(ap_netlist) + , log_verbosity_(log_verbosity) {} /** * @brief Perform global placement on the given netlist. @@ -62,10 +60,9 @@ class GlobalPlacer { */ virtual PartialPlacement place() = 0; -protected: - + protected: /// @brief The APNetlist the global placer is placing. - const APNetlist& netlist_; + const APNetlist& ap_netlist_; /// @brief The setting of how verbose the log messages should be in the /// global placer. Anything larger than zero will display per @@ -76,8 +73,17 @@ class GlobalPlacer { /** * @brief A factory method which creates a Global Placer of the given type. */ -std::unique_ptr make_global_placer(e_global_placer placer_type, - const APNetlist& netlist); +std::unique_ptr make_global_placer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); /** * @brief A Global Placer based on the SimPL work for analytical ASIC placement. @@ -106,8 +112,7 @@ std::unique_ptr make_global_placer(e_global_placer placer_type, * approach each other until a good quality, mostly-legal solution is found. */ class SimPLGlobalPlacer : public GlobalPlacer { -private: - + private: /// @brief The maximum number of iterations the global placer can perform. static constexpr size_t max_num_iterations_ = 100; @@ -115,22 +120,35 @@ class SimPLGlobalPlacer : public GlobalPlacer { /// lower-bound placements. The placer will stop if the difference /// between the two bounds, normalized to the upper-bound, is smaller /// than this number. - static constexpr double target_hpwl_relative_gap_ = 0.10; + /// This number was empircally found to work well. + static constexpr double target_hpwl_relative_gap_ = 0.05; /// @brief The solver which generates the lower-bound placement. std::unique_ptr solver_; + /// @brief The denisty manager the partial legalizer will optimize over. + std::shared_ptr density_manager_; + /// @brief The legalizer which generates the upper-bound placement. std::unique_ptr partial_legalizer_; -public: - + public: /** * @brief Constructor for the SimPL Global Placer * * Constructs the solver and partial legalizer. */ - SimPLGlobalPlacer(const APNetlist& netlist); + SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, + const APNetlist& ap_netlist, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const DeviceGrid& device_grid, + const std::vector& logical_block_types, + const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); /** * @brief Run a SimPL-like global placement algorithm @@ -140,4 +158,3 @@ class SimPLGlobalPlacer : public GlobalPlacer { */ PartialPlacement place() final; }; - diff --git a/vpr/src/analytical_place/model_grouper.cpp b/vpr/src/analytical_place/model_grouper.cpp new file mode 100644 index 00000000000..0aca963c96a --- /dev/null +++ b/vpr/src/analytical_place/model_grouper.cpp @@ -0,0 +1,184 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Implementation of a model grouper class which groups models together + * which must be legalized together in a flat placement. + */ + +#include "model_grouper.h" +#include +#include +#include +#include +#include "cad_types.h" +#include "logic_types.h" +#include "prepack.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +/** + * @brief Recursive helper function which gets the models in the given pattern + * block. + * + * @param pattern_block + * The pattern block to get the models of. + * @param models + * A set of the models found so far. + * @param block_visited + * A vector of flags for each pattern block to signify which blocks have + * been visited. + */ +static void get_pattern_models_recurr(t_pack_pattern_block* pattern_block, + std::unordered_set& models, + std::vector& block_visited) { + // If the pattern block is invalid or this block has been visited, return. + if (pattern_block == nullptr || block_visited[pattern_block->block_id]) { + return; + } + + // Mark this block as visited and insert its model into the models vector. + block_visited[pattern_block->block_id] = true; + models.insert(pattern_block->pb_type->model->index); + + // Go through this block's connections and get their pattern models. + t_pack_pattern_connections* connection = pattern_block->connections; + while (connection != nullptr) { + get_pattern_models_recurr(connection->from_block, models, block_visited); + get_pattern_models_recurr(connection->to_block, models, block_visited); + connection = connection->next; + } +} + +/** + * @brief Entry point into the recursive function above. Gets the models in + * the given pack pattern. + */ +static std::unordered_set get_pattern_models(const t_pack_patterns& pack_pattern) { + std::unordered_set models_in_pattern; + + // Initialize the visited flags for each block to false. + std::vector block_visited(pack_pattern.num_blocks, false); + // Begin the recursion with the root block. + get_pattern_models_recurr(pack_pattern.root_block, models_in_pattern, block_visited); + + return models_in_pattern; +} + +ModelGrouper::ModelGrouper(const Prepacker& prepacker, + t_model* user_models, + t_model* library_models, + int log_verbosity) { + /** + * Group the models together based on their pack patterns. If model A and + * model B form a pattern, and model B and model C form a pattern, then + * models A, B, and C are in a group together. + * + * An efficient way to find this is to represent this problem as a graph, + * where each node is a model and each edge is a relationship where a model + * is in a pack pattern with another model. We can then perform BFS to find + * the connected sub-graphs which will be the groups. + */ + + // Get the number of models + // TODO: Clean up the models vectors in VTR. + std::unordered_map model_name; + unsigned num_models = 0; + t_model* model = library_models; + while (model != nullptr) { + model_name[model->index] = model->name; + num_models++; + model = model->next; + } + model = user_models; + while (model != nullptr) { + model_name[model->index] = model->name; + num_models++; + model = model->next; + } + + // Create an adjacency list for the edges. An edge is formed where two + // models share a pack pattern together. + std::vector> adj_list(num_models); + for (const t_pack_patterns& pack_pattern : prepacker.get_all_pack_patterns()) { + // Get the models within this pattern. + auto models_in_pattern = get_pattern_models(pack_pattern); + VTR_ASSERT_SAFE(!models_in_pattern.empty()); + + // Debug print the models within the pattern. + if (log_verbosity >= 20) { + VTR_LOG("Pattern: %s\n\t", pack_pattern.name); + for (int model_idx : models_in_pattern) { + VTR_LOG("%s ", model_name[model_idx]); + } + VTR_LOG("\n"); + } + + // Connect each of the models to the first model in the pattern. Since + // we only care if there exist a path from each model to another, we do + // not need to connect the models in a clique. + int first_model_idx = *models_in_pattern.begin(); + for (int model_idx : models_in_pattern) { + adj_list[model_idx].insert(first_model_idx); + adj_list[first_model_idx].insert(model_idx); + } + } + + // Perform BFS to group the models. + VTR_LOGV(log_verbosity >= 20, + "Finding model groups...\n"); + std::queue node_queue; + model_group_id_.resize(num_models, ModelGroupId::INVALID()); + for (int model_idx = 0; model_idx < (int)num_models; model_idx++) { + // If this model is already in a group, skip it. + if (model_group_id_[model_idx].is_valid()) { + VTR_LOGV(log_verbosity >= 20, + "\t(%d -> %d)\n", model_idx, model_group_id_[model_idx]); + continue; + } + + ModelGroupId group_id = ModelGroupId(group_ids_.size()); + // Put the model in this group and push to the queue. + model_group_id_[model_idx] = group_id; + node_queue.push(model_idx); + + while (!node_queue.empty()) { + // Pop a node from the queue, and explore its neighbors. + int node_model_idx = node_queue.front(); + node_queue.pop(); + for (int neighbor_model_idx : adj_list[node_model_idx]) { + // If this neighbor is already in this group, skip it. + if (model_group_id_[neighbor_model_idx].is_valid()) { + VTR_ASSERT_SAFE(model_group_id_[neighbor_model_idx] == group_id); + continue; + } + // Put the neighbor in this group and push it to the queue. + model_group_id_[neighbor_model_idx] = group_id; + node_queue.push(neighbor_model_idx); + } + } + + VTR_LOGV(log_verbosity >= 20, + "\t(%d -> %d)\n", model_idx, model_group_id_[model_idx]); + group_ids_.push_back(group_id); + } + + // Create a lookup between each group and the models it contains. + groups_.resize(groups().size()); + for (int model_idx = 0; model_idx < (int)num_models; model_idx++) { + groups_[model_group_id_[model_idx]].push_back(model_idx); + } + + // Debug printing for each group. + if (log_verbosity >= 20) { + for (ModelGroupId group_id : groups()) { + const std::vector& group = groups_[group_id]; + VTR_LOG("Group %zu:\n", group_id); + VTR_LOG("\tSize = %zu\n", group.size()); + VTR_LOG("\tContained models:\n"); + for (int model_idx : group) { + VTR_LOG("\t\t%s\n", model_name[model_idx]); + } + } + } +} diff --git a/vpr/src/analytical_place/model_grouper.h b/vpr/src/analytical_place/model_grouper.h new file mode 100644 index 00000000000..d5a9113d6c1 --- /dev/null +++ b/vpr/src/analytical_place/model_grouper.h @@ -0,0 +1,115 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Declaration of a model grouper class which groups together models + * that must be legalized together in a flat placement. + */ + +#pragma once + +#include +#include "vtr_assert.h" +#include "vtr_range.h" +#include "vtr_strong_id.h" +#include "vtr_vector.h" +#include "vtr_vector_map.h" + +// Forward declarations. +class Prepacker; +struct t_model; + +/// @brief Tag for the ModelGroupId +struct model_group_id_tag; + +/// @brief A unique ID of a group of models created by the ModelGrouper class. +typedef vtr::StrongId ModelGroupId; + +/** + * @brief A manager class for grouping together models that must be legalized + * together in a flat placement due to how they form molecules with each + * other. + * + * When performing legalization of a flat placement, it is desirable to split + * the problem into independent legalization problems. We cannot place all of + * the blocks of different model types independently since some blocks are made + * of multiple different types of models. We wish to find the minimum number of + * models that we need to legalize at the same time. + * + * This class groups models together based on the pack patterns that they can + * form in the prepacker. If model A and model B can form a pack pattern, and + * model B and model C can form a pack pattern, then models A, B, and C form a + * group and must be legalized together. + * + * This class also manages what models each group contains and the group of each + * model, where the user can use IDs to get relavent information. + */ +class ModelGrouper { + public: + // Iterator for the model group IDs + typedef typename vtr::vector_map::const_iterator group_iterator; + + // Range for the model group IDs + typedef typename vtr::Range group_range; + + public: + ModelGrouper() = delete; + + /** + * @brief Constructor for the model grouper class. Groups are formed here. + * + * @param prepacker + * The prepacker used to create molecules in the flat placement. This + * provides the pack patterns for forming the groups. + * @param user_models + * Linked list of user-provided models. + * @param library_models + * Linked list of library models. + * @param log_verbosity + * The verbosity of log messages in the grouper class. + */ + ModelGrouper(const Prepacker& prepacker, + t_model* user_models, + t_model* library_models, + int log_verbosity); + + /** + * @brief Returns a list of all valid group IDs. + */ + inline group_range groups() const { + return vtr::make_range(group_ids_.begin(), group_ids_.end()); + } + + /** + * @brief Gets the group ID of the given model. + */ + inline ModelGroupId get_model_group_id(int model_index) const { + VTR_ASSERT_SAFE_MSG(model_index < (int)model_group_id_.size(), + "Model index outside of range for model_group_id_"); + ModelGroupId group_id = model_group_id_[model_index]; + VTR_ASSERT_SAFE_MSG(group_id.is_valid(), + "Model is not in a group"); + return group_id; + } + + /** + * @brief Gets the models in the given group. + */ + inline const std::vector& get_models_in_group(ModelGroupId group_id) const { + VTR_ASSERT_SAFE_MSG(group_id.is_valid(), + "Invalid group id"); + VTR_ASSERT_SAFE_MSG(groups_[group_id].size() != 0, + "Group is empty"); + return groups_[group_id]; + } + + private: + /// @brief List of all group IDs. + vtr::vector_map group_ids_; + + /// @brief A lookup between models and the group ID that contains them. + std::vector model_group_id_; + + /// @brief A lookup between each group ID and the models in that group. + vtr::vector> groups_; +}; diff --git a/vpr/src/analytical_place/partial_legalizer.cpp b/vpr/src/analytical_place/partial_legalizer.cpp index e782c85b073..7021734f8d5 100644 --- a/vpr/src/analytical_place/partial_legalizer.cpp +++ b/vpr/src/analytical_place/partial_legalizer.cpp @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include #include @@ -19,28 +21,43 @@ #include #include #include "ap_netlist.h" -#include "device_grid.h" +#include "flat_placement_bins.h" +#include "flat_placement_density_manager.h" +#include "flat_placement_mass_calculator.h" #include "globals.h" +#include "model_grouper.h" #include "partial_placement.h" #include "physical_types.h" +#include "prepack.h" #include "primitive_vector.h" #include "vpr_context.h" #include "vpr_error.h" -#include "vpr_types.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_log.h" -#include "vtr_ndmatrix.h" +#include "vtr_math.h" +#include "vtr_prefix_sum.h" #include "vtr_strong_id.h" +#include "vtr_time.h" #include "vtr_vector.h" #include "vtr_vector_map.h" -std::unique_ptr make_partial_legalizer(e_partial_legalizer legalizer_type, - const APNetlist& netlist) { +std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer legalizer_type, + const APNetlist& netlist, + std::shared_ptr density_manager, + const Prepacker& prepacker, + int log_verbosity) { // Based on the partial legalizer type passed in, build the partial legalizer. switch (legalizer_type) { - case e_partial_legalizer::FLOW_BASED: - return std::make_unique(netlist); + case e_ap_partial_legalizer::FlowBased: + return std::make_unique(netlist, + density_manager, + log_verbosity); + case e_ap_partial_legalizer::BiPartitioning: + return std::make_unique(netlist, + density_manager, + prepacker, + log_verbosity); default: VPR_FATAL_ERROR(VPR_ERROR_AP, "Unrecognized partial legalizer type"); @@ -49,164 +66,6 @@ std::unique_ptr make_partial_legalizer(e_partial_legalizer leg return nullptr; } -/** - * @brief Get the scalar mass of the given model (primitive type). - * - * A model with a higher mass will take up more space in its bin which may force - * more spreading of that type of primitive. - * - * TODO: This will be made more complicated later. Models may be weighted based - * on some factors. - */ -static inline float get_model_mass(const t_model* model) { - // Currently, all models have a mass of one. - (void)model; - return 1.f; -} - -/** - * @brief Get the primitive mass of the given block. - * - * This returns an M-dimensional vector with each entry indicating the mass of - * that primitive type in this block. M is the number of unique models - * (primitive types) in the architecture. - */ -static inline PrimitiveVector get_primitive_mass(APBlockId blk_id, - const APNetlist& netlist) { - PrimitiveVector mass; - const t_pack_molecule* mol = netlist.block_molecule(blk_id); - for (AtomBlockId atom_blk_id : mol->atom_block_ids) { - // See issue #2791, some of the atom_block_ids may be invalid. They can - // safely be ignored. - if (!atom_blk_id.is_valid()) - continue; - const t_model* model = g_vpr_ctx.atom().nlist.block_model(atom_blk_id); - VTR_ASSERT_DEBUG(model->index >= 0); - mass.add_val_to_dim(get_model_mass(model), model->index); - } - return mass; -} - -// This method is being forward-declared due to the double recursion below. -// Eventually this should be made into a non-recursive algorithm for performance, -// however this is not in a performance critical part of the code. -static PrimitiveVector get_primitive_capacity(const t_pb_type* pb_type); - -/** - * @brief Get the amount of primitives this mode can contain. - * - * This is part of a double recursion, since a mode contains primitives which - * themselves have modes. - */ -static PrimitiveVector get_primitive_capacity(const t_mode& mode) { - // Accumulate the capacities of all the pbs in this mode. - PrimitiveVector capacity; - for (int pb_child_idx = 0; pb_child_idx < mode.num_pb_type_children; pb_child_idx++) { - const t_pb_type& pb_type = mode.pb_type_children[pb_child_idx]; - PrimitiveVector pb_capacity = get_primitive_capacity(&pb_type); - // A mode may contain multiple pbs of the same type, multiply the - // capacity. - pb_capacity *= pb_type.num_pb; - capacity += pb_capacity; - } - return capacity; -} - -/** - * @brief Get the amount of primitives this pb can contain. - * - * This is the other part of the double recursion. A pb may have multiple modes. - * Modes are made of pbs. - */ -static PrimitiveVector get_primitive_capacity(const t_pb_type* pb_type) { - // Since a pb cannot be multiple modes at the same time, we do not - // accumulate the capacities of the mode. Instead we need to "mix" the two - // capacities as if the pb could choose either one. - PrimitiveVector capacity; - // If this is a leaf / primitive, create the base PrimitiveVector capacity. - if (pb_type->num_modes == 0) { - const t_model* model = pb_type->model; - VTR_ASSERT(model != nullptr); - VTR_ASSERT_DEBUG(model->index >= 0); - capacity.add_val_to_dim(get_model_mass(model), model->index); - return capacity; - } - // For now, we simply mix the capacities of modes by taking the max of each - // dimension of the capcities. This provides an upper-bound on the amount of - // primitives this pb can contain. - for (int mode = 0; mode < pb_type->num_modes; mode++) { - PrimitiveVector mode_capacity = get_primitive_capacity(pb_type->modes[mode]); - capacity = PrimitiveVector::max(capacity, mode_capacity); - } - return capacity; -} - -/** - * @brief Helper method to get the primitive capacity of the given logical block - * type. - * - * This is the entry point to the double recursion. - */ -static inline PrimitiveVector get_primitive_capacity(const t_logical_block_type& block_type) { - // If this logical block is empty, it cannot contain any primitives. - if (block_type.is_empty()) - return PrimitiveVector(); - // The primitive capacity of a logical block is the primitive capacity of - // its root pb. - return get_primitive_capacity(block_type.pb_type); -} - -/** - * @brief Get the primitive capacity of the given sub_tile. - * - * Sub_tiles may reuse logical blocks between one another, therefore this method - * requires that the capacities of all of the logical blocks have been - * pre-calculated and stored in the given vector. - * - * @param sub_tile The sub_tile to get the capacity of. - * @param logical_block_type_capacities The capacities of all logical block - * types. - */ -static inline PrimitiveVector get_primitive_capacity(const t_sub_tile& sub_tile, - const std::vector& logical_block_type_capacities) { - // Similar to getting the primitive capacity of the pb, sub_tiles have many - // equivalent sites, but it can only be one of them at a time. Need to "mix" - // the capacities of the different sites this sub_tile may be. - PrimitiveVector capacity; - for (t_logical_block_type_ptr block_type : sub_tile.equivalent_sites) { - const PrimitiveVector& block_capacity = logical_block_type_capacities[block_type->index]; - // Currently, we take the max of each primitive dimension as an upper - // bound on the capacity of the sub_tile. - capacity = PrimitiveVector::max(capacity, block_capacity); - } - return capacity; -} - -/** - * @brief Get the primitive capacity of a tile of the given type. - * - * Tiles may reuse logical blocks between one another, therefore this method - * requires that the capacities of all of the logical blocks have been - * pre-calculated and stored in the given vector. - * - * @param tile_type The tile type to get the capacity of. - * @param logical_block_type_capacities The capacities of all logical block - * types. - */ -static inline PrimitiveVector get_primitive_capacity(const t_physical_tile_type& tile_type, - const std::vector& logical_block_type_capacities) { - // Accumulate the capacities of all the sub_tiles in the given tile type. - PrimitiveVector capacity; - for (const t_sub_tile& sub_tile : tile_type.sub_tiles) { - PrimitiveVector sub_tile_capacity = get_primitive_capacity(sub_tile, logical_block_type_capacities); - // A tile may contain many sub_tiles of the same type. Multiply by the - // number of sub_tiles of this type. - sub_tile_capacity *= sub_tile.capacity.total(); - capacity += sub_tile_capacity; - } - return capacity; -} - /** * @brief Get the number of models in the device architecture. * @@ -228,106 +87,46 @@ static inline size_t get_num_models() { return num_models; } -/** - * @brief Debug printing method to print the capacities of all logical blocks - * and physical tile types. - */ -static inline void print_capacities(const std::vector& logical_block_type_capacities, - const std::vector& physical_tile_type_capacities, - const std::vector& logical_block_types, - const std::vector& physical_tile_types) { - // Get a linear list of all models. - // TODO: Again, the way these models are stored is so annoying. It would be - // nice if they were already vectors! - std::vector all_models; - t_model* curr_model = g_vpr_ctx.device().arch->models; - while (curr_model != nullptr) { - if (curr_model->index >= (int)all_models.size()) - all_models.resize(curr_model->index + 1); - all_models[curr_model->index] = curr_model; - curr_model = curr_model->next; - } - curr_model = g_vpr_ctx.device().arch->model_library; - while (curr_model != nullptr) { - if (curr_model->index >= (int)all_models.size()) - all_models.resize(curr_model->index + 1); - all_models[curr_model->index] = curr_model; - curr_model = curr_model->next; - } - // Print the capacities. - VTR_LOG("Logical Block Type Capacities:\n"); - VTR_LOG("------------------------------\n"); - VTR_LOG("name\t"); - for (t_model* model : all_models) { - VTR_LOG("%s\t", model->name); - } - VTR_LOG("\n"); - for (const t_logical_block_type& block_type : logical_block_types) { - const PrimitiveVector& capacity = logical_block_type_capacities[block_type.index]; - VTR_LOG("%s\t", block_type.name.c_str()); - for (t_model* model : all_models) { - VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); - } - VTR_LOG("\n"); - } - VTR_LOG("\n"); - VTR_LOG("Physical Tile Type Capacities:\n"); - VTR_LOG("------------------------------\n"); - VTR_LOG("name\t"); - for (t_model* model : all_models) { - VTR_LOG("%s\t", model->name); - } - VTR_LOG("\n"); - for (const t_physical_tile_type& tile_type : physical_tile_types) { - const PrimitiveVector& capacity = physical_tile_type_capacities[tile_type.index]; - VTR_LOG("%s\t", tile_type.name.c_str()); - for (t_model* model : all_models) { - VTR_LOG("%.2f\t", capacity.get_dim_val(model->index)); - } - VTR_LOG("\n"); - } - VTR_LOG("\n"); -} - /** * @brief Helper method to get the direct neighbors of the given bin. * * A direct neighbor of a bin is a bin which shares a side with the given bin on * the tile graph. Corners do not count. */ -static std::unordered_set get_direct_neighbors_of_bin( - LegalizerBinId bin_id, - const vtr::vector_map& bins, - const vtr::NdMatrix tile_bin) { - const LegalizerBin& bin = bins[bin_id]; - int bl_x = bin.bounding_box.bottom_left().x(); - int bl_y = bin.bounding_box.bottom_left().y(); - size_t bin_width = bin.bounding_box.width(); - size_t bin_height = bin.bounding_box.height(); +static std::unordered_set get_direct_neighbors_of_bin( + FlatPlacementBinId bin_id, + const FlatPlacementDensityManager& density_manager) { + const vtr::Rect& bin_region = density_manager.flat_placement_bins().bin_region(bin_id); + int bl_x = bin_region.bottom_left().x(); + int bl_y = bin_region.bottom_left().y(); + size_t bin_width = bin_region.width(); + size_t bin_height = bin_region.height(); // This is an unfortunate consequence of using double precision to store // the bounding box. We need to ensure that the bin represents a tile (not // part of a tile). If it did represent part of a tile, this algorithm // would need to change. - VTR_ASSERT_DEBUG(static_cast(bl_x) == bin.bounding_box.bottom_left().x() && - static_cast(bl_y) == bin.bounding_box.bottom_left().y() && - static_cast(bin_width) == bin.bounding_box.width() && - static_cast(bin_height) == bin.bounding_box.height()); + VTR_ASSERT_DEBUG(static_cast(bl_x) == bin_region.bottom_left().x() && static_cast(bl_y) == bin_region.bottom_left().y() && static_cast(bin_width) == bin_region.width() && static_cast(bin_height) == bin_region.height()); + + double placeable_region_width, placeable_region_height, placeable_region_depth; + std::tie(placeable_region_width, placeable_region_height, placeable_region_depth) = density_manager.get_overall_placeable_region_size(); + // Current does not handle 3D FPGAs + VTR_ASSERT(placeable_region_depth == 1.0); // Add the neighbors. - std::unordered_set neighbor_bin_ids; + std::unordered_set neighbor_bin_ids; // Add unique tiles on left and right sides for (size_t ty = bl_y; ty < bl_y + bin_height; ty++) { if (bl_x >= 1) - neighbor_bin_ids.insert(tile_bin[bl_x - 1][ty]); - if (bl_x <= (int)(tile_bin.dim_size(0) - bin_width - 1)) - neighbor_bin_ids.insert(tile_bin[bl_x + bin_width][ty]); + neighbor_bin_ids.insert(density_manager.get_bin(bl_x - 1, ty, 0.0)); + if (bl_x <= (int)(placeable_region_width - bin_width - 1)) + neighbor_bin_ids.insert(density_manager.get_bin(bl_x + bin_width, ty, 0.0)); } // Add unique tiles on the top and bottom for (size_t tx = bl_x; tx < bl_x + bin_width; tx++) { if (bl_y >= 1) - neighbor_bin_ids.insert(tile_bin[tx][bl_y - 1]); - if (bl_y <= (int)(tile_bin.dim_size(1) - bin_height - 1)) - neighbor_bin_ids.insert(tile_bin[tx][bl_y + bin_height]); + neighbor_bin_ids.insert(density_manager.get_bin(tx, bl_y - 1, 0.0)); + if (bl_y <= (int)(placeable_region_height - bin_height - 1)) + neighbor_bin_ids.insert(density_manager.get_bin(tx, bl_y + bin_height, 0.0)); } // A bin cannot be a neighbor with itself. @@ -343,23 +142,26 @@ static inline vtr::Point get_center_of_rect(vtr::Rect rect) { return rect.bottom_left() + vtr::Point(rect.width() / 2.0, rect.height() / 2.0); } -void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, size_t num_models) { +void FlowBasedLegalizer::compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, size_t num_models) { // Make sure that this bin does not already have neighbors. - VTR_ASSERT_DEBUG(bins_[src_bin_id].neighbors.size() == 0); + VTR_ASSERT_DEBUG(bin_neighbors_.size() == 0); // Bins need to be neighbors to every possible molecule type so things can // flow properly. // Perform BFS to find the closest bins of each type. Where closest is in // manhattan distance. + const FlatPlacementBins& flat_placement_bins = density_manager_->flat_placement_bins(); + size_t num_bins = flat_placement_bins.bins().size(); + // Create the queue and insert the source bin into it. - std::queue q; + std::queue q; q.push(src_bin_id); // Create visited flags for each bin. Set the source to visited. - vtr::vector_map bin_visited(bins_.size(), false); + vtr::vector_map bin_visited(num_bins, false); bin_visited[src_bin_id] = true; // Create a distance count for each bin from the src. - vtr::vector_map bin_distance(bins_.size(), 0); + vtr::vector_map bin_distance(num_bins, 0); // Flags to check if a specific model has been found in the given direction. // In this case, direction is the direction of the largest component of the // manhattan distance between the source bin and the target bin. @@ -374,15 +176,16 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz bool all_right_found = false; bool all_models_found_in_all_directions = false; // The center of the source bin. - vtr::Point src_bin_center = get_center_of_rect(bins_[src_bin_id].bounding_box); + const vtr::Rect& src_bin_region = flat_placement_bins.bin_region(src_bin_id); + vtr::Point src_bin_center = get_center_of_rect(src_bin_region); // The result will be stored in this set. - std::unordered_set neighbors; + std::unordered_set neighbors; // Helper method to add a neighbor to the set of neighbors and update the // found flags for a given direction if this bin is new for a given model // type. This method returns true if every model has been found in the given // direction (i.e. dir_found is now all true). - auto add_neighbor_if_new_dir = [&](LegalizerBinId target_bin_id, + auto add_neighbor_if_new_dir = [&](FlatPlacementBinId target_bin_id, std::vector& dir_found) { bool all_found = true; // Go through all possible models @@ -391,7 +194,8 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz if (dir_found[i]) continue; // If this bin has this model in its capacity, we found a neighbor! - if (bins_[target_bin_id].capacity.get_dim_val(i) > 0) { + const PrimitiveVector& target_bin_capacity = density_manager_->get_bin_capacity(target_bin_id); + if (target_bin_capacity.get_dim_val(i) > 0) { dir_found[i] = true; neighbors.insert(target_bin_id); } else { @@ -403,9 +207,9 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz // Perform the BFS from the source node until all nodes have been explored // or all of the models have been found in all directions. - while(!q.empty() && !all_models_found_in_all_directions) { + while (!q.empty() && !all_models_found_in_all_directions) { // Pop the bin from the queue. - LegalizerBinId bin_id = q.front(); + FlatPlacementBinId bin_id = q.front(); q.pop(); // If the distance of this block from the source is too large, do not // explore. @@ -414,14 +218,15 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz continue; // Get the direct neighbors of the bin (neighbors that are directly // touching). - auto direct_neighbors = get_direct_neighbors_of_bin(bin_id, bins_, tile_bin_); - for (LegalizerBinId dir_neighbor_bin_id : direct_neighbors) { + auto direct_neighbors = get_direct_neighbors_of_bin(bin_id, *density_manager_); + for (FlatPlacementBinId dir_neighbor_bin_id : direct_neighbors) { // If this neighbor has been visited, do not do anything. if (bin_visited[dir_neighbor_bin_id]) continue; // Get the signed distance from the src bin to the target bin in the // x and y dimensions. - vtr::Point target_bin_center = get_center_of_rect(bins_[dir_neighbor_bin_id].bounding_box); + const vtr::Rect& dir_neighbor_bin_region = flat_placement_bins.bin_region(dir_neighbor_bin_id); + vtr::Point target_bin_center = get_center_of_rect(dir_neighbor_bin_region); double dx = target_bin_center.x() - src_bin_center.x(); double dy = target_bin_center.y() - src_bin_center.y(); // Is the target bin above the source bin? @@ -451,260 +256,45 @@ void FlowBasedLegalizer::compute_neighbors_of_bin(LegalizerBinId src_bin_id, siz q.push(dir_neighbor_bin_id); } // Check if all of the models have been found in all directions. - all_models_found_in_all_directions = all_up_found && all_down_found && - all_left_found && all_right_found; + all_models_found_in_all_directions = all_up_found && all_down_found && all_left_found && all_right_found; } // Assign the results into the neighbors of the bin. - bins_[src_bin_id].neighbors.assign(neighbors.begin(), neighbors.end()); + bin_neighbors_[src_bin_id].assign(neighbors.begin(), neighbors.end()); } -FlowBasedLegalizer::FlowBasedLegalizer(const APNetlist& netlist) - : PartialLegalizer(netlist), - // TODO: Pass the device grid in. - tile_bin_({g_vpr_ctx.device().grid.width(), g_vpr_ctx.device().grid.height()}) { - const DeviceGrid& grid = g_vpr_ctx.device().grid; - size_t grid_width = grid.width(); - size_t grid_height = grid.height(); - - // Pre-compute the capacities of all logical blocks in the device. - // logical_block_type::index -> PrimitiveVector - std::vector logical_block_type_capacities(g_vpr_ctx.device().logical_block_types.size()); - for (const t_logical_block_type& logical_block_type : g_vpr_ctx.device().logical_block_types) { - logical_block_type_capacities[logical_block_type.index] = get_primitive_capacity(logical_block_type); - } - // Pre-compute the capacities of all physical tile types in the device. - // physical_tile_type::index -> PrimitiveVector - std::vector physical_tile_type_capacities(g_vpr_ctx.device().physical_tile_types.size()); - for (const t_physical_tile_type& physical_tile_type : g_vpr_ctx.device().physical_tile_types) { - physical_tile_type_capacities[physical_tile_type.index] = get_primitive_capacity(physical_tile_type, logical_block_type_capacities); - } - // Print these capacities. Helpful for debugging. - if (log_verbosity_ > 1) { - print_capacities(logical_block_type_capacities, - physical_tile_type_capacities, - g_vpr_ctx.device().logical_block_types, - g_vpr_ctx.device().physical_tile_types); - } - // Create the bins - // This currently creates 1 bin per tile. - for (size_t x = 0; x < grid_width; x++) { - for (size_t y = 0; y < grid_height; y++) { - // Ignoring 3D placement for now. - t_physical_tile_loc tile_loc = {(int)x, (int)y, 0}; - // Is this the root location? Only create bins for roots. - size_t width_offset = grid.get_width_offset(tile_loc); - size_t height_offset = grid.get_height_offset(tile_loc); - if (width_offset != 0 || height_offset != 0) { - // If this is not a root, point the tile_bin_ lookup to the root - // tile location. - tile_bin_[x][y] = tile_bin_[x - width_offset][y - height_offset]; - continue; - } - // Create the bin - LegalizerBinId new_bin_id = LegalizerBinId(bins_.size()); - LegalizerBin new_bin; - // NOTE: The bounding box from the tile does not make sense in this - // context, making my own here based on the tile size and - // position. - t_physical_tile_type_ptr tile_type = grid.get_physical_type(tile_loc); - int width = tile_type->width; - int height = tile_type->height; - new_bin.bounding_box = vtr::Rect(vtr::Point(x, y), - vtr::Point(x + width, - y + height)); - // The capacity of the bin is the capacity of the tile it represents. - new_bin.capacity = physical_tile_type_capacities[tile_type->index]; - bins_.push_back(std::move(new_bin)); - tile_bin_[x][y] = new_bin_id; - } - } +FlowBasedLegalizer::FlowBasedLegalizer(const APNetlist& netlist, + std::shared_ptr density_manager, + int log_verbosity) + : PartialLegalizer(netlist, log_verbosity) + , density_manager_(density_manager) + , bin_neighbors_(density_manager_->flat_placement_bins().bins().size()) { - // Get the number of models in the device. - size_t num_models = get_num_models(); // Connect the bins. - // TODO: Should create a list of bin IDs to make this more efficient. - for (size_t x = 0; x < grid_width; x++) { - for (size_t y = 0; y < grid_height; y++) { - // Ignoring 3D placement for now. Will likely require modification to - // the solver and legalizer. - t_physical_tile_loc tile_loc = {(int)x, (int)y, 0}; - // Is this the root location? - if (grid.get_width_offset(tile_loc) != 0 || - grid.get_height_offset(tile_loc) != 0) { - continue; - } - // Compute the neighbors of this bin. - compute_neighbors_of_bin(tile_bin_[x][y], num_models); - } - } - - // Pre-compute the masses of the APBlocks - VTR_LOGV(log_verbosity_ >= 10, "Pre-computing the block masses...\n"); - for (APBlockId blk_id : netlist.blocks()) { - block_masses_.insert(blk_id, get_primitive_mass(blk_id, netlist)); + size_t num_models = get_num_models(); + for (FlatPlacementBinId bin_id : density_manager_->flat_placement_bins().bins()) { + compute_neighbors_of_bin(bin_id, num_models); } - VTR_LOGV(log_verbosity_ >= 10, "Finished pre-computing the block masses.\n"); - - // Initialize the block_bins. - block_bins_.resize(netlist.blocks().size(), LegalizerBinId::INVALID()); } -bool FlowBasedLegalizer::verify_bins() const { - // Make sure that every block has a bin. - for (APBlockId blk_id : netlist_.blocks()) { - if (!block_bins_[blk_id].is_valid()) { - VTR_LOG("Bin Verify: Found a block that is not in a bin.\n"); - return false; - } - } - // Make sure that every tile has a bin. - const DeviceGrid& device_grid = g_vpr_ctx.device().grid; - if (tile_bin_.dim_size(0) != device_grid.width() || - tile_bin_.dim_size(1) != device_grid.height()) { - VTR_LOG("Bin Verify: Tile-bin lookup does not contain every tile.\n"); - return false; - } - for (size_t x = 0; x < device_grid.width(); x++) { - for (size_t y = 0; y < device_grid.height(); y++) { - if (!tile_bin_[x][y].is_valid()) { - VTR_LOG("Bin Verify: Found a tile with no bin.\n"); - return false; - } - } +bool FlowBasedLegalizer::verify() const { + if (density_manager_->verify() == false) { + VTR_LOG("Flow-Based Legalizer Verify: Density Manager failed verification.\n"); } - // Make sure that every bin has the correct utilization, supply, and demand. - for (const LegalizerBin& bin : bins_) { - PrimitiveVector calc_utilization; - for (APBlockId blk_id : bin.contained_blocks) { - calc_utilization += block_masses_[blk_id]; - } - if (bin.utilization != calc_utilization) { - VTR_LOG("Bin Verify: Found a bin with incorrect utilization.\n"); - return false; - } - PrimitiveVector calc_supply = bin.utilization - bin.capacity; - calc_supply.relu(); - if (bin.supply != calc_supply) { - VTR_LOG("Bin Verify: Found a bin with incorrect supply.\n"); - return false; - } - PrimitiveVector calc_demand = bin.capacity - bin.utilization; - calc_demand.relu(); - if (bin.demand != calc_demand) { - VTR_LOG("Bin Verify: Found a bin with incorrect demand.\n"); - return false; - } - if (!bin.supply.is_non_negative()) { - VTR_LOG("Bin Verify: Found a bin with a negative supply.\n"); - return false; - } - if (!bin.demand.is_non_negative()) { - VTR_LOG("Bin Verify: Found a bin with a negative demand.\n"); - return false; - } - if (!bin.capacity.is_non_negative()) { - VTR_LOG("Bin Verify: Found a bin with a negative capacity.\n"); - return false; - } - if (!bin.utilization.is_non_negative()) { - VTR_LOG("Bin Verify: Found a bin with a negative utilization.\n"); - return false; - } - if (bin.neighbors.size() == 0) { - VTR_LOG("Bin Verify: Found a bin with no neighbors.\n"); - return false; - } - } - // Make sure all overfilled bins are actually overfilled. - // TODO: Need to make sure that all non-overfilled bins are actually not - // overfilled. - for (LegalizerBinId bin_id : overfilled_bins_) { - const LegalizerBin& bin = bins_[bin_id]; - if (bin.supply.is_zero()) { - VTR_LOG("Bin Verify: Found an overfilled bin that was not overfilled.\n"); + // Make sure that the bins are connected correctly. + for (FlatPlacementBinId bin_id : density_manager_->flat_placement_bins().bins()) { + if (bin_neighbors_[bin_id].empty()) { + VTR_LOG("Flow-Based Legalizer Verify: Found a bin with no neighbors.\n"); return false; } + // TODO: Should verify more about the connectivity. Such as every bin + // has a neighbor of each model type and a path exists from every + // bin to every other bin. } // If all above passed, then the bins are valid. return true; } -void FlowBasedLegalizer::reset_bins() { - // Reset all of the bins by removing all of the contained blocks. - for (LegalizerBin& bin : bins_) { - bin.contained_blocks.clear(); - bin.utilization = PrimitiveVector(); - bin.compute_supply(); - bin.compute_demand(); - } - // Reset the reverse lookup of block_bins_ - std::fill(block_bins_.begin(), block_bins_.end(), LegalizerBinId::INVALID()); - // No bin can be overfilled right now. - overfilled_bins_.clear(); -} - -void FlowBasedLegalizer::import_placement_into_bins(const PartialPlacement& p_placement) { - // TODO: Maybe import the fixed block locations in the constructor and - // then only import the moveable block locations. - for (APBlockId blk_id : netlist_.blocks()) { - size_t x_loc = p_placement.block_x_locs[blk_id]; - size_t y_loc = p_placement.block_y_locs[blk_id]; - LegalizerBinId bin_id = get_bin(x_loc, y_loc); - insert_blk_into_bin(blk_id, bin_id); - } -} - -/** - * @brief Get the location of a block assuming that it is placed within the - * given bin. - * - * This function will return the position of the block in the point within the - * bin's bounding box which is closest to the original position of the block - * (the position in p_placement). - */ -static inline vtr::Point get_block_location_in_bin(APBlockId blk_id, - const LegalizerBin& bin, - const PartialPlacement& p_placement) { - // A block cannot be placed on the right or top sides of the bounding box - // of a bin; however they can be infinitely close to these sides. It is - // arbitrary how close to the edge we place the blocks; opted to place them - // as close as possible. - double epsilon = 0.0001; - double x = std::clamp(p_placement.block_x_locs[blk_id], - bin.bounding_box.bottom_left().x(), - bin.bounding_box.top_right().x() - epsilon); - double y = std::clamp(p_placement.block_y_locs[blk_id], - bin.bounding_box.bottom_left().y(), - bin.bounding_box.top_right().y() - epsilon); - return vtr::Point(x, y); -} - -void FlowBasedLegalizer::export_placement_from_bins(PartialPlacement& p_placement) const { - // Updates the partial placement with the location of the blocks in the bin - // by moving the blocks to the point within the bin closest to where they - // were originally. - // TODO: This should be investigated more. This may put blocks onto the edges - // of bins which may not be ideal. - for (APBlockId blk_id : netlist_.blocks()) { - // Only the moveable block locations should be exported. - if (netlist_.block_mobility(blk_id) == APBlockMobility::FIXED) - continue; - // Project the coordinate of the block in the partial placement to the - // closest point in the bin. - LegalizerBinId bin_id = block_bins_[blk_id]; - VTR_ASSERT_DEBUG(bin_id.is_valid()); - const LegalizerBin& bin = bins_[bin_id]; - // Set the position of the block to the closest position in the bin to - // where the block was. - vtr::Point new_blk_pos = get_block_location_in_bin(blk_id, - bin, - p_placement); - p_placement.block_x_locs[blk_id] = new_blk_pos.x(); - p_placement.block_y_locs[blk_id] = new_blk_pos.y(); - } -} - // Helper method to compute the phi term in the durav algorithm. static inline float computeMaxMovement(size_t iter) { return 100 * (iter + 1) * (iter + 1); @@ -719,40 +309,44 @@ static inline float computeMaxMovement(size_t iter) { * * @param src_bin The bin that contains the blocks to move. * @param target_bin The bin to move blocks to. - * @param block_masses A lookup for the masses of all blocks. * @param p_placement The placement of the blocks prior to legalization. * @param netlist The APNetlist for the placement. + * @param density_manager The density manager for this partial legalizer. * * @return A pair of the minimum cost moveable block and its cost. */ static inline std::pair get_min_cost_block_in_bin( - const LegalizerBin& src_bin, - const LegalizerBin& target_bin, - const vtr::vector_map& block_masses, - const PartialPlacement& p_placement, - const APNetlist& netlist) { + FlatPlacementBinId src_bin, + FlatPlacementBinId target_bin, + const PartialPlacement& p_placement, + const APNetlist& netlist, + const FlatPlacementDensityManager& density_manager) { // Get the min cost block and its cost. APBlockId min_cost_block; float min_cost = std::numeric_limits::infinity(); + const FlatPlacementBins& bins = density_manager.flat_placement_bins(); + const FlatPlacementMassCalculator& mass_calculator = density_manager.mass_calculator(); + const std::unordered_set& src_contained_blocks = bins.bin_contained_blocks(src_bin); // FIXME: If these were somehow pre-sorted, this can be made much cheaper. - for (APBlockId blk_id : src_bin.contained_blocks) { + for (APBlockId blk_id : src_contained_blocks) { // If this block is fixed, it has infinite cost to move. if (netlist.block_mobility(blk_id) == APBlockMobility::FIXED) continue; - const PrimitiveVector& block_mass = block_masses[blk_id]; + const PrimitiveVector& block_mass = mass_calculator.get_block_mass(blk_id); // Is this block compatible with the target bin? // If the capacity of the target, projected onto the mass, is less than // the mass, then the block is not compatible. // TODO: We may want to add a cost term based on how much space is // available in the bin? - PrimitiveVector target_capacity = target_bin.capacity; + PrimitiveVector target_capacity = density_manager.get_bin_capacity(target_bin); target_capacity.project(block_mass); if (target_capacity < block_mass) continue; // Compute the quadratic movement (aka cost). - vtr::Point new_block_pos = get_block_location_in_bin(blk_id, - target_bin, - p_placement); + const vtr::Rect& target_bin_region = bins.bin_region(target_bin); + const vtr::Point& new_block_pos = density_manager.get_block_location_in_bin(blk_id, + target_bin_region, + p_placement); double dx = new_block_pos.x() - p_placement.block_x_locs[blk_id]; double dy = new_block_pos.y() - p_placement.block_y_locs[blk_id]; float cost = (dx * dx) + (dy * dy); @@ -777,18 +371,18 @@ static inline std::pair get_min_cost_block_in_bin( * @param psi Algorithm parameter which represents the maximum * cost this function can return. This function will * return inf if the cost is larger than psi. - * @param block_masses A lookup for the masses of all blocks. * @param p_placement The placement of the blocks prior to legalization. * @param netlist The APNetlist for the placement. + * @param density_manager The density manager for this partial legalizer. */ -static inline float compute_cost(const LegalizerBin& src_bin, - const LegalizerBin& target_bin, +static inline float compute_cost(FlatPlacementBinId src_bin, + FlatPlacementBinId target_bin, float psi, - const vtr::vector_map& block_masses, const PartialPlacement& p_placement, - const APNetlist& netlist) { + const APNetlist& netlist, + const FlatPlacementDensityManager& density_manager) { // If the src bin is empty, then there is nothing to move. - if (src_bin.contained_blocks.size() == 0) + if (density_manager.flat_placement_bins().bin_contained_blocks(src_bin).size() == 0) return std::numeric_limits::infinity(); // Get the min cost block in the src bin which is compatible with the target // bin. @@ -796,9 +390,9 @@ static inline float compute_cost(const LegalizerBin& src_bin, float min_cost; std::tie(min_cost_block, min_cost) = get_min_cost_block_in_bin(src_bin, target_bin, - block_masses, p_placement, - netlist); + netlist, + density_manager); // If no block can be moved to the target bin, return. if (std::isinf(min_cost)) return std::numeric_limits::infinity(); @@ -810,59 +404,64 @@ static inline float compute_cost(const LegalizerBin& src_bin, // This weight tries to keep blocks of the same type together. // This term can be found by taking the L1 norm of the projection of the // src bin's utilization on the direction of the mass. - PrimitiveVector weight_vec = src_bin.utilization; - weight_vec.project(block_masses[min_cost_block]); + const FlatPlacementMassCalculator& mass_calculator = density_manager.mass_calculator(); + const PrimitiveVector& min_cost_block_mass = mass_calculator.get_block_mass(min_cost_block); + PrimitiveVector weight_vec = density_manager.get_bin_utilization(src_bin); + weight_vec.project(min_cost_block_mass); float weight = weight_vec.manhattan_norm(); // Return the overall cost which is the quadratic movement times the weight. return weight * min_cost; } -std::vector> FlowBasedLegalizer::get_paths(LegalizerBinId src_bin_id, - const PartialPlacement& p_placement, - float psi) { +std::vector> FlowBasedLegalizer::get_paths( + FlatPlacementBinId src_bin_id, + const PartialPlacement& p_placement, + float psi) { VTR_LOGV(log_verbosity_ >= 20, "\tGetting paths...\n"); + const FlatPlacementBins& flat_placement_bins = density_manager_->flat_placement_bins(); + size_t num_bins = flat_placement_bins.bins().size(); // Create a visited vector. - vtr::vector_map bin_visited(bins_.size(), false); + vtr::vector_map bin_visited(num_bins, false); bin_visited[src_bin_id] = true; // Create a cost array. The cost of a path is equal to the cost of its tail // bin. - vtr::vector_map bin_cost(bins_.size(), 0.f); + vtr::vector_map bin_cost(num_bins, 0.f); // Create a starting path. - std::vector starting_path; + std::vector starting_path; starting_path.push_back(src_bin_id); // Create a FIFO queue. - std::queue> queue; + std::queue> queue; queue.push(std::move(starting_path)); // Create the resulting vector of paths. // TODO: Can we store this more efficiently as a tree? - std::vector> paths; + std::vector> paths; // Perform the BFS to search for direct paths to flow the starting bin's // supply of primitives until it has found sufficient demand. PrimitiveVector demand; - const PrimitiveVector& starting_bin_supply = bins_[src_bin_id].supply; + const PrimitiveVector& starting_bin_supply = get_bin_supply(src_bin_id); while (!queue.empty() && demand < starting_bin_supply) { // Pop the current bin off the queue. - std::vector &p = queue.front(); - LegalizerBinId tail_bin_id = p.back(); + std::vector& p = queue.front(); + FlatPlacementBinId tail_bin_id = p.back(); // Look over its neighbors - for (LegalizerBinId neighbor_bin_id : bins_[tail_bin_id].neighbors) { + for (FlatPlacementBinId neighbor_bin_id : bin_neighbors_[tail_bin_id]) { // If this bin has already been visited, skip it. if (bin_visited[neighbor_bin_id]) continue; // Compute the cost of moving a block from the tail bin to its // neighbor. - float cost = compute_cost(bins_[tail_bin_id], - bins_[neighbor_bin_id], + float cost = compute_cost(tail_bin_id, + neighbor_bin_id, psi, - block_masses_, p_placement, - netlist_); + netlist_, + *density_manager_); // If the cost is infinite, then the path cannot be made to this // neighbor bin. if (std::isinf(cost)) continue; // Else, a path can be made. - std::vector p_copy(p); + std::vector p_copy(p); bin_cost[neighbor_bin_id] = bin_cost[tail_bin_id] + cost; p_copy.push_back(neighbor_bin_id); bin_visited[neighbor_bin_id] = true; @@ -879,7 +478,7 @@ std::vector> FlowBasedLegalizer::get_paths(Legalizer // investigated further... // FIXME: Perhaps we do not check if it is empty, but check if the // demand is sufficiently large... - PrimitiveVector neighbor_demand = bins_[neighbor_bin_id].demand; + PrimitiveVector neighbor_demand = get_bin_demand(neighbor_bin_id); neighbor_demand.project(starting_bin_supply); VTR_ASSERT_DEBUG(neighbor_demand.is_non_negative()); // if (bins_[neighbor_bin_id].contained_blocks.size() == 0) { @@ -900,39 +499,38 @@ std::vector> FlowBasedLegalizer::get_paths(Legalizer // Helpful debug messages. VTR_LOGV(log_verbosity_ >= 20, "\t\tSupply of source bin: %.2f\n", - starting_bin_supply.manhattan_norm()); + starting_bin_supply.manhattan_norm()); VTR_LOGV(log_verbosity_ >= 20, "\t\tDemand of all paths from source: %.2f\n", - starting_bin_supply.manhattan_norm()); + starting_bin_supply.manhattan_norm()); // Sort the paths in increasing order of cost. - std::sort(paths.begin(), paths.end(), [&](const std::vector& a, - const std::vector& b) { + std::sort(paths.begin(), paths.end(), [&](const std::vector& a, const std::vector& b) { return bin_cost[a.back()] < bin_cost[b.back()]; }); return paths; } -void FlowBasedLegalizer::flow_blocks_along_path(const std::vector& path, +void FlowBasedLegalizer::flow_blocks_along_path(const std::vector& path, const PartialPlacement& p_placement, float psi) { // Get the root bin of the path. VTR_ASSERT(!path.empty()); - LegalizerBinId src_bin_id = path[0]; + FlatPlacementBinId src_bin_id = path[0]; // Create a stack and put the src bin on top. - std::stack s; + std::stack s; s.push(src_bin_id); // Insert the bins in the path into the stack in reverse order (so the last // bin in the path is on top of the stack). size_t path_size = path.size(); for (size_t path_idx = 1; path_idx < path_size; path_idx++) { - LegalizerBinId sink_bin_id = path[path_idx]; + FlatPlacementBinId sink_bin_id = path[path_idx]; // Check that the cost of moving a block from the source bin to the sink // bin is non-infinite. According to the paper, this check is needed // since a previous flow on another path may have made this path not // necessary anymore. - float cost = compute_cost(bins_[src_bin_id], bins_[sink_bin_id], psi, - block_masses_, p_placement, netlist_); + float cost = compute_cost(src_bin_id, sink_bin_id, psi, + p_placement, netlist_, *density_manager_); if (std::isinf(cost)) return; src_bin_id = sink_bin_id; @@ -940,7 +538,7 @@ void FlowBasedLegalizer::flow_blocks_along_path(const std::vector p = get_min_cost_block_in_bin(bins_[src_bin_id], - bins_[sink_bin_id], - block_masses_, + std::pair p = get_min_cost_block_in_bin(src_bin_id, + sink_bin_id, p_placement, - netlist_); + netlist_, + *density_manager_); // Move the block from the src bin to the sink bin. - remove_blk_from_bin(p.first, src_bin_id); - insert_blk_into_bin(p.first, sink_bin_id); + density_manager_->remove_block_from_bin(p.first, src_bin_id); + density_manager_->insert_block_into_bin(p.first, sink_bin_id); sink_bin_id = src_bin_id; } @@ -999,38 +597,18 @@ static void print_flow_based_legalizer_status(size_t iteration, fflush(stdout); } -/** - * @brief Debug method to print the current number of blocks contained in each - * bin visually. - * - * This method helps to see how the spreading is working. - */ -static void print_flow_based_bin_grid(const vtr::NdMatrix& tile_bin, - const vtr::vector_map& bins) { - for (size_t y = 0; y < tile_bin.dim_size(1); y++) { - for (size_t x = 0; x < tile_bin.dim_size(0); x++) { - const LegalizerBin& bin = bins[tile_bin[x][y]]; - VTR_LOG("%3zu ", bin.contained_blocks.size()); - } - VTR_LOG("\n"); - } - VTR_LOG("\n"); -} - -void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { +void FlowBasedLegalizer::legalize(PartialPlacement& p_placement) { VTR_LOGV(log_verbosity_ >= 10, "Running Flow-Based Legalizer\n"); - // Reset the bins from the previous iteration and prepare for this iteration. - reset_bins(); // Import the partial placement into bins. - import_placement_into_bins(p_placement); + density_manager_->import_placement_into_bins(p_placement); // Verify that the placement was imported correctly. - VTR_ASSERT_SAFE(verify_bins()); + VTR_ASSERT_SAFE(density_manager_->verify()); // Print the number of blocks in each bin visually before spreading. if (log_verbosity_ >= 15) { VTR_LOG("Bin utilization prior to spreading:\n"); - print_flow_based_bin_grid(tile_bin_, bins_); + density_manager_->print_bin_grid(); } // Print the status header to make printing the status clearer. @@ -1048,7 +626,8 @@ void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { break; } // If there are no overfilled bins, no more work to do. - if (overfilled_bins_.empty()) { + const std::unordered_set& overfilled_bins = density_manager_->get_overfilled_bins(); + if (overfilled_bins.empty()) { VTR_LOGV(log_verbosity_ >= 10, "Flow-Based legalizer has no overfilled tiles. No further spreading needed.\n"); break; @@ -1063,28 +642,28 @@ void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { // NOTE: Although the supply should always be non-negative, we still // take the absolute value in the norm for completeness. // TODO: This is a guess. Should investigate other norms. - std::vector overfilled_bins_vec(overfilled_bins_.begin(), overfilled_bins_.end()); - std::sort(overfilled_bins_vec.begin(), overfilled_bins_vec.end(), [&](LegalizerBinId a, LegalizerBinId b) { - return bins_[a].supply.manhattan_norm() < bins_[b].supply.manhattan_norm(); + std::vector overfilled_bins_vec(overfilled_bins.begin(), overfilled_bins.end()); + std::sort(overfilled_bins_vec.begin(), overfilled_bins_vec.end(), [&](FlatPlacementBinId a, FlatPlacementBinId b) { + return get_bin_supply(a).manhattan_norm() < get_bin_supply(b).manhattan_norm(); }); // Get the paths to flow blocks from the overfilled bins to the under // filled bins and flow the blocks. - for (LegalizerBinId src_bin_id : overfilled_bins_vec) { + for (FlatPlacementBinId src_bin_id : overfilled_bins_vec) { // Get the list of candidate paths based on psi. A path is a list // of LegalizerBins traversed. // NOTE: The paths are sorted by increasing cost within the // getPaths method. - std::vector> paths = get_paths(src_bin_id, - p_placement, - psi); + std::vector> paths = get_paths(src_bin_id, + p_placement, + psi); VTR_LOGV(log_verbosity_ >= 20, "\tNum paths: %zu\n", paths.size()); // For each path, flow the blocks along the path. - for (const std::vector& path : paths) { + for (const std::vector& path : paths) { VTR_LOGV(log_verbosity_ >= 30, "\t\tPath length: %zu\n", path.size()); // If the bin is no longer overfilled, no need to move any more // blocks along the paths. - if (!bin_is_overfilled(src_bin_id)) + if (!density_manager_->bin_is_overfilled(src_bin_id)) break; // Move blocks over the paths. // NOTE: This will only modify the bins. (actual block @@ -1097,10 +676,10 @@ void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { if (log_verbosity_ >= 10) { // TODO: Get the total cell displacement for debugging. print_flow_based_legalizer_status( - flowBasedIter, - overfilled_bins_vec.size(), - bins_[overfilled_bins_vec.back()].supply.manhattan_norm(), - psi); + flowBasedIter, + overfilled_bins_vec.size(), + get_bin_supply(overfilled_bins_vec.back()).manhattan_norm(), + psi); } // Increment the iteration. @@ -1111,15 +690,853 @@ void FlowBasedLegalizer::legalize(PartialPlacement &p_placement) { flowBasedIter + 1); // Verify that the bins are valid before export. - VTR_ASSERT(verify_bins()); + VTR_ASSERT(verify()); // Print the number of blocks in each bin after spreading. if (log_verbosity_ >= 15) { VTR_LOG("Bin utilization after spreading:\n"); - print_flow_based_bin_grid(tile_bin_, bins_); + density_manager_->print_bin_grid(); + } + + // Export the legalized placement to the partial placement. + density_manager_->export_placement_from_bins(p_placement); +} + +PerModelPrefixSum2D::PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, + t_model* user_models, + t_model* library_models, + std::function lookup) { + // Get the number of models in the architecture. + // TODO: We really need to clean up how models are stored in VPR... + t_model* cur = user_models; + int num_models = 0; + while (cur != nullptr) { + num_models++; + cur = cur->next; + } + cur = library_models; + while (cur != nullptr) { + num_models++; + cur = cur->next; + } + + // Get the size that the prefix sums should be. + size_t width, height, layers; + std::tie(width, height, layers) = density_manager.get_overall_placeable_region_size(); + + // Create each of the prefix sums. + model_prefix_sum_.resize(num_models); + for (int model_index = 0; model_index < num_models; model_index++) { + model_prefix_sum_[model_index] = vtr::PrefixSum2D( + width, + height, + [&](size_t x, size_t y) { + return lookup(model_index, x, y); + }); + } +} + +float PerModelPrefixSum2D::get_model_sum(int model_index, + const vtr::Rect& region) const { + VTR_ASSERT_SAFE(model_index < (int)model_prefix_sum_.size() && model_index >= 0); + // Get the sum over the given region. + return model_prefix_sum_[model_index].get_sum(region.xmin(), + region.ymin(), + region.xmax() - 1, + region.ymax() - 1); +} + +PrimitiveVector PerModelPrefixSum2D::get_sum(const std::vector& model_indices, + const vtr::Rect& region) const { + PrimitiveVector res; + for (int model_index : model_indices) { + VTR_ASSERT_SAFE(res.get_dim_val(model_index) == 0.0f); + res.set_dim_val(model_index, get_model_sum(model_index, region)); + } + return res; +} + +BiPartitioningPartialLegalizer::BiPartitioningPartialLegalizer( + const APNetlist& netlist, + std::shared_ptr density_manager, + const Prepacker& prepacker, + int log_verbosity) + : PartialLegalizer(netlist, log_verbosity) + , density_manager_(density_manager) + , model_grouper_(prepacker, + g_vpr_ctx.device().arch->models, + g_vpr_ctx.device().arch->model_library, + log_verbosity) { + // Compute the capacity prefix sum. Capacity is assumed to not change + // between iterations of the partial legalizer. + capacity_prefix_sum_ = PerModelPrefixSum2D( + *density_manager, + g_vpr_ctx.device().arch->models, + g_vpr_ctx.device().arch->model_library, + [&](int model_index, size_t x, size_t y) { + // Get the bin at this grid location. + FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); + // Get the capacity of the bin for this model. + float cap = density_manager_->get_bin_capacity(bin_id).get_dim_val(model_index); + VTR_ASSERT_SAFE(cap >= 0.0f); + // Bins may be large, but the prefix sum assumes a 1x1 grid of + // values. Normalize by the area of the bin to turn this into + // a 1x1 bin equivalent. + const vtr::Rect& bin_region = density_manager_->flat_placement_bins().bin_region(bin_id); + float bin_area = bin_region.width() * bin_region.height(); + VTR_ASSERT_SAFE(!vtr::isclose(bin_area, 0.f)); + return cap / bin_area; + }); + + num_windows_partitioned_ = 0; + num_blocks_partitioned_ = 0; +} + +void BiPartitioningPartialLegalizer::print_statistics() { + VTR_LOG("Bi-Partitioning Partial Legalizer Statistics:\n"); + VTR_LOG("\tTotal number of windows partitioned: %u\n", num_windows_partitioned_); + VTR_LOG("\tTotal number of blocks partitioned: %u\n", num_blocks_partitioned_); +} + +void BiPartitioningPartialLegalizer::legalize(PartialPlacement& p_placement) { + VTR_LOGV(log_verbosity_ >= 10, "Running Bi-Partitioning Legalizer\n"); + + // Prepare the density manager. + density_manager_->import_placement_into_bins(p_placement); + + // Quick return. If there are no overfilled bins, there is nothing to spread. + if (density_manager_->get_overfilled_bins().size() == 0) { + VTR_LOGV(log_verbosity_ >= 10, "No overfilled bins. Nothing to legalize.\n"); + return; + } + + if (log_verbosity_ >= 10) { + size_t num_overfilled_bins = density_manager_->get_overfilled_bins().size(); + VTR_LOG("\tNumber of overfilled blocks before legalization: %zu\n", + num_overfilled_bins); + // FIXME: Make this a method in the density manager class. + float avg_overfill = 0.f; + for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { + avg_overfill += density_manager_->get_bin_overfill(overfilled_bin_id).manhattan_norm(); + } + VTR_LOG("\t\tAverage overfill per overfilled bin: %f\n", + avg_overfill / static_cast(num_overfilled_bins)); + } + + // 1) Identify the groups that need to be spread + std::unordered_set groups_to_spread; + for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { + // Get the overfilled models in this bin. + const PrimitiveVector& overfill = density_manager_->get_bin_overfill(overfilled_bin_id); + std::vector overfilled_models = overfill.get_non_zero_dims(); + // For each model, insert its group into the set. Set will handle dupes. + for (int model_index : overfilled_models) { + groups_to_spread.insert(model_grouper_.get_model_group_id(model_index)); + } + } + + // 2) For each group, identify non-overlapping windows and spread + vtr::Timer runtime_timer; + float window_identification_time = 0.0f; + float window_spreading_time = 0.0f; + for (ModelGroupId group_id : groups_to_spread) { + VTR_LOGV(log_verbosity_ >= 10, "\tSpreading group %zu\n", group_id); + // Identify non-overlapping spreading windows. + float window_identification_start_time = runtime_timer.elapsed_sec(); + auto non_overlapping_windows = identify_non_overlapping_windows(group_id); + window_identification_time += runtime_timer.elapsed_sec() - window_identification_start_time; + VTR_ASSERT(non_overlapping_windows.size() != 0); + + // Spread the blocks over the non-overlapping windows. + float window_spreading_start_time = runtime_timer.elapsed_sec(); + spread_over_windows(non_overlapping_windows, p_placement, group_id); + window_spreading_time += runtime_timer.elapsed_sec() - window_spreading_start_time; + } + + // FIXME: Remove this duplicate code... + if (log_verbosity_ >= 10) { + size_t num_overfilled_bins = density_manager_->get_overfilled_bins().size(); + VTR_LOG("\tNumber of overfilled blocks after legalization: %zu\n", + num_overfilled_bins); + // FIXME: Make this a method in the density manager class. + float avg_overfill = 0.f; + for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { + avg_overfill += density_manager_->get_bin_overfill(overfilled_bin_id).manhattan_norm(); + } + VTR_LOG("\t\tAverage overfill per overfilled bin: %f\n", + avg_overfill / static_cast(num_overfilled_bins)); + VTR_LOG("\tTime spent identifying windows: %g\n", window_identification_time); + VTR_LOG("\tTime spent spreading windows: %g\n", window_spreading_time); } // Export the legalized placement to the partial placement. - export_placement_from_bins(p_placement); + density_manager_->export_placement_from_bins(p_placement); +} + +std::vector BiPartitioningPartialLegalizer::identify_non_overlapping_windows(ModelGroupId group_id) { + + // 1) Cluster the overfilled bins. This will make creating minimum spanning + // windows more efficient. + auto overfilled_bin_clusters = get_overfilled_bin_clusters(group_id); + + // 2) For each of the overfilled bin clusters, create a minimum window such + // that there is enough space in the window for the atoms inside. + auto windows = get_min_windows_around_clusters(overfilled_bin_clusters, group_id); + + // 3) Merge overlapping windows. + merge_overlapping_windows(windows); + + // TODO: Investigate shrinking the windows. + + // 4) Move the blocks out of their bins and into the windows. + move_blocks_into_windows(windows, group_id); + + return windows; +} + +/** + * @brief Helper method to check if the given PrimitiveVector has any values + * in the model dimensions in the given group. + * + * This method assumes the vector is non-negative. If the vector had any negative + * dimensions, it does not make sense to ask if it is in the group or not. + */ +static bool is_vector_in_group(const PrimitiveVector& vec, + ModelGroupId group_id, + const ModelGrouper& model_grouper) { + VTR_ASSERT_SAFE(vec.is_non_negative()); + const std::vector& models_in_group = model_grouper.get_models_in_group(group_id); + for (int model_index : models_in_group) { + float dim_val = vec.get_dim_val(model_index); + if (dim_val != 0.0f) + return true; + } + return false; +} + +/** + * @brief Checks if the overfilled models in the given overfilled bin is in the + * given model group. + * + * This method does not check if the bin could be in the given group (for + * example the capacity), this checks if the overfilled blocks are in the group. + */ +static bool is_overfilled_bin_in_group(FlatPlacementBinId overfilled_bin_id, + ModelGroupId group_id, + const FlatPlacementDensityManager& density_manager, + const ModelGrouper& model_grouper) { + const PrimitiveVector& bin_overfill = density_manager.get_bin_overfill(overfilled_bin_id); + VTR_ASSERT_SAFE(bin_overfill.is_non_zero()); + return is_vector_in_group(bin_overfill, group_id, model_grouper); +} + +/** + * @brief Checks if the given AP block is in the given model group. + * + * An AP block is in a model group if it contains any models in the model group. + */ +static bool is_block_in_group(APBlockId blk_id, + ModelGroupId group_id, + const FlatPlacementDensityManager& density_manager, + const ModelGrouper& model_grouper) { + const PrimitiveVector& blk_mass = density_manager.mass_calculator().get_block_mass(blk_id); + return is_vector_in_group(blk_mass, group_id, model_grouper); } +std::vector BiPartitioningPartialLegalizer::get_overfilled_bin_clusters( + ModelGroupId group_id) { + // Use BFS over the overfilled bins to cluster them. + std::vector overfilled_bin_clusters; + // Maintain the distance from the last overfilled bin + vtr::vector dist(density_manager_->flat_placement_bins().bins().size(), -1); + for (FlatPlacementBinId overfilled_bin_id : density_manager_->get_overfilled_bins()) { + // If this bin is not overfilled with the models in the group, skip. + if (!is_overfilled_bin_in_group(overfilled_bin_id, + group_id, + *density_manager_, + model_grouper_)) { + continue; + } + // If this bin is already in a cluster, skip. + if (dist[overfilled_bin_id] != -1) + continue; + dist[overfilled_bin_id] = 0; + // Collect nearby bins into a vector. + FlatPlacementBinCluster nearby_bins; + nearby_bins.push_back(overfilled_bin_id); + // Create a queue and insert the overfilled bin into it. + std::queue bin_queue; + bin_queue.push(overfilled_bin_id); + while (!bin_queue.empty()) { + // Pop a bin from queue. + FlatPlacementBinId bin_node = bin_queue.front(); + bin_queue.pop(); + // If the node's distance from an overfilled bin is the max gap, + // do not explore its neighbors. + if (dist[bin_node] > max_bin_cluster_gap_) + continue; + // Explore the neighbors of this bin. + for (FlatPlacementBinId neighbor : get_direct_neighbors_of_bin(bin_node, *density_manager_)) { + int neighbor_dist = dist[bin_node] + 1; + // If this neighbor has been explore with a better distance, + // do not explore it. + if (dist[neighbor] != -1 && dist[neighbor] <= neighbor_dist) + continue; + // If the neighbor is an overfilled bin that we care about, add + // it to the list of nearby bins and set its distance to 0. + if (density_manager_->bin_is_overfilled(neighbor) + && is_overfilled_bin_in_group(neighbor, group_id, *density_manager_, model_grouper_)) { + nearby_bins.push_back(neighbor); + dist[neighbor] = 0; + } else { + dist[neighbor] = neighbor_dist; + } + // Enqueue the neighbor. + bin_queue.push(neighbor); + } + } + + // Move the cluster into the vector of overfilled bin clusters. + overfilled_bin_clusters.push_back(std::move(nearby_bins)); + } + + return overfilled_bin_clusters; +} + +/** + * @brief Helper method to decide if the given region's utilization is higher + * than its capacity. + */ +static bool is_region_overfilled(const vtr::Rect& region, + const PerModelPrefixSum2D& capacity_prefix_sum, + const PerModelPrefixSum2D& utilization_prefix_sum, + const std::vector& model_indices) { + // Go through each model in the model group we are interested in. + for (int model_index : model_indices) { + // Get the capacity of this region for this model. + float region_model_capacity = capacity_prefix_sum.get_model_sum(model_index, + region); + // Get the utilization of this region for this model. + float region_model_utilization = utilization_prefix_sum.get_model_sum(model_index, + region); + // If the utilization is higher than the capacity, then this region is + // overfilled. + // TODO: Look into adding some head room to account for rounding. + if (region_model_utilization > region_model_capacity) + return true; + } + + // If the utilization is less than or equal to the capacity for each model + // then this region is not overfilled. + return false; +} + +std::vector BiPartitioningPartialLegalizer::get_min_windows_around_clusters( + const std::vector& overfilled_bin_clusters, + ModelGroupId group_id) { + // TODO: Currently, we greedily grow the region by 1 in all directions until + // the capacity is larger than the utilization. This may not produce + // the minimum window. Should investigate "touching-up" the windows. + // FIXME: It may be a good idea to sort the bins by their overfill here. Then + // we can check for overlap as we go. + + // Get the width, height, and number of layers for the spreading region. + // This is used by the growing part of this routine to prevent the windows + // from outgrowing the device. + size_t width, height, layers; + std::tie(width, height, layers) = density_manager_->get_overall_placeable_region_size(); + + // Precompute a prefix sum for the current utilization of each 1x1 region + // of the device. This needs to be recomputed every time the bins are + // modified, so it is recomputed here. + PerModelPrefixSum2D utilization_prefix_sum( + *density_manager_, + g_vpr_ctx.device().arch->models, + g_vpr_ctx.device().arch->model_library, + [&](int model_index, size_t x, size_t y) { + FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); + // This is computed the same way as the capacity prefix sum above. + const vtr::Rect& bin_region = density_manager_->flat_placement_bins().bin_region(bin_id); + float bin_area = bin_region.width() * bin_region.height(); + float util = density_manager_->get_bin_utilization(bin_id).get_dim_val(model_index); + VTR_ASSERT_SAFE(util >= 0.0f); + return util / bin_area; + }); + + // Create windows for each overfilled bin cluster. + std::vector windows; + for (const std::vector& overfilled_bin_cluster : overfilled_bin_clusters) { + // Create a new window for this cluster of bins. + SpreadingWindow new_window; + + // Set the region of the window to the bounding box of the cluster of bins. + size_t num_bins_in_cluster = overfilled_bin_cluster.size(); + VTR_ASSERT_SAFE(num_bins_in_cluster != 0); + vtr::Rect& region = new_window.region; + region = density_manager_->flat_placement_bins().bin_region(overfilled_bin_cluster[0]); + for (size_t i = 1; i < num_bins_in_cluster; i++) { + region = vtr::bounding_box(region, + density_manager_->flat_placement_bins().bin_region(overfilled_bin_cluster[i])); + } + + // Grow the region until it is just large enough to not overfill + while (true) { + // Grow the region by 1 on all sides. + double new_xmin = std::clamp(region.xmin() - 1.0, 0.0, width); + double new_xmax = std::clamp(region.xmax() + 1.0, 0.0, width); + double new_ymin = std::clamp(region.ymin() - 1.0, 0.0, height); + double new_ymax = std::clamp(region.ymax() + 1.0, 0.0, height); + + // If the region did not grow, exit. This is a maximal bin. + // TODO: Maybe print warning. + if (new_xmin == region.xmin() && new_xmax == region.xmax() && new_ymin == region.ymin() && new_ymax == region.ymax()) { + break; + } + + region.set_xmin(new_xmin); + region.set_xmax(new_xmax); + region.set_ymin(new_ymin); + region.set_ymax(new_ymax); + + // If the region is no longer overfilled, stop growing. + if (!is_region_overfilled(region, capacity_prefix_sum_, utilization_prefix_sum, model_grouper_.get_models_in_group(group_id))) + break; + } + // Insert this window into the list of windows. + windows.emplace_back(std::move(new_window)); + } + + return windows; +} + +void BiPartitioningPartialLegalizer::merge_overlapping_windows( + std::vector& windows) { + // Merge overlapping windows. + // TODO: This is a very basic merging process which will identify the + // minimum region containing both windows; however, after merging it + // is very likely that this window will now be too large. Need to + // investigate shrinking the windows after merging. + // TODO: I am not sure if it is possible, but after merging 2 windows, the + // new window may overlap with another window that has been already + // created. This should not cause issues with the algorithm since one + // of the new windows will just be empty, but it is not ideal. + // FIXME: This loop is O(N^2) with the number of overfilled bins which may + // get expensive as the circuit sizes increase. Should investigate + // spatial sorting structures (like kd-trees) to help keep this fast. + // Another idea is to merge windows early on (before growing them). + std::vector non_overlapping_windows; + size_t num_windows = windows.size(); + // Need to keep track of which windows have been merged or not to prevent + // merging windows multiple times. + std::vector finished_window(num_windows, false); + for (size_t i = 0; i < num_windows; i++) { + // If the window has already been finished (merged), nothing to do. + if (finished_window[i]) + continue; + + // Check for overlaps between this window and the future windows and + // update the region accordingly. + vtr::Rect& region = windows[i].region; + for (size_t j = i + 1; j < num_windows; j++) { + // No need to check windows which have already finished. + if (finished_window[j]) + continue; + // Check for overlap + if (region.strictly_overlaps(windows[j].region)) { + // If overlap, merge with this region and mark the window as + // finished. + // Here, the merged region is the bounding box around the two + // regions. + region = vtr::bounding_box(region, windows[j].region); + finished_window[j] = true; + } + } + + // This is not strictly necessary, but marking this window as finished + // is just a nice, clean thing to do. + finished_window[i] = true; + + // Move this window into the new list of non-overlapping windows. + non_overlapping_windows.emplace_back(std::move(windows[i])); + } + + // Store the results into the input window. + windows = std::move(non_overlapping_windows); +} + +void BiPartitioningPartialLegalizer::move_blocks_into_windows( + std::vector& non_overlapping_windows, + ModelGroupId group_id) { + // Move the blocks from their bins into the windows that should contain them. + // TODO: It may be good for debugging to check if the windows have nothing + // to move. This may indicate a problem (overfilled bins of fixed + // blocks, overlapping windows, etc.). + for (SpreadingWindow& window : non_overlapping_windows) { + // Iterate over all bins that this window covers. + // TODO: This is a bit crude and should somehow be made more robust. + size_t lower_x = window.region.xmin(); + size_t upper_x = window.region.xmax() - 1; + size_t lower_y = window.region.ymin(); + size_t upper_y = window.region.ymax() - 1; + for (size_t x = lower_x; x <= upper_x; x++) { + for (size_t y = lower_y; y <= upper_y; y++) { + // Get all of the movable blocks from the bin. + std::vector moveable_blks; + FlatPlacementBinId bin_id = density_manager_->get_bin(x, y, 0); + const auto& bin_contained_blocks = density_manager_->flat_placement_bins().bin_contained_blocks(bin_id); + moveable_blks.reserve(bin_contained_blocks.size()); + for (APBlockId blk_id : bin_contained_blocks) { + // If this block is not moveable, do not move it. + if (netlist_.block_mobility(blk_id) != APBlockMobility::MOVEABLE) + continue; + // If this block is not in the group, do not move it. + if (!is_block_in_group(blk_id, group_id, *density_manager_, model_grouper_)) + continue; + + moveable_blks.push_back(blk_id); + } + // Remove the moveable blocks from their bins and store into + // the windows. + for (APBlockId blk_id : moveable_blks) { + density_manager_->remove_block_from_bin(blk_id, bin_id); + window.contained_blocks.push_back(blk_id); + } + } + } + } +} + +void BiPartitioningPartialLegalizer::spread_over_windows(std::vector& non_overlapping_windows, + const PartialPlacement& p_placement, + ModelGroupId group_id) { + if (log_verbosity_ >= 10) { + VTR_LOG("\tIdentified %zu non-overlapping spreading windows.\n", + non_overlapping_windows.size()); + + if (log_verbosity_ >= 20) { + for (const SpreadingWindow& window : non_overlapping_windows) { + VTR_LOG("\t\t[(%.1f, %.1f), (%.1f, %.1f)]\n", + window.region.xmin(), window.region.ymin(), + window.region.xmax(), window.region.ymax()); + PrimitiveVector window_capacity = capacity_prefix_sum_.get_sum(model_grouper_.get_models_in_group(group_id), + window.region); + VTR_LOG("\t\t\tCapacity: %f\n", + window_capacity.manhattan_norm()); + VTR_LOG("\t\t\tNumber of contained blocks: %zu\n", + window.contained_blocks.size()); + } + } + } + + // Insert the windows into a queue for spreading. + std::queue window_queue; + for (SpreadingWindow& window : non_overlapping_windows) { + window_queue.push(std::move(window)); + } + + // For each window in the queue: + // 1) If the window is small enough, do not partition further. + // 2) Partition the window + // 3) Partition the blocks into the window partitions + // 4) Insert the new windows into the queue + std::vector finished_windows; + while (!window_queue.empty()) { + // Get a reference to the front of the queue but do not pop it yet. We + // can save time from having to copy the element out since these windows + // contain vectors. + SpreadingWindow& window = window_queue.front(); + + // Check if the window is empty. This can happen when there is odd + // numbers of blocks or when things do not perfectly fit. + if (window.contained_blocks.empty()) { + // If the window does not contain any blocks, pop it from the queue + // and do not put it in finished windows. There is no point + // operating on it further. + window_queue.pop(); + continue; + } + + // 1) Check if the window is small enough (one bin in size). + // TODO: Perhaps we can make this stopping criteria more intelligent. + // Like stopping when we know there is only one bin within the + // window. + double window_area = window.region.width() * window.region.height(); + if (window_area <= 1.0) { + finished_windows.emplace_back(std::move(window)); + window_queue.pop(); + continue; + } + + num_windows_partitioned_++; + num_blocks_partitioned_ += window.contained_blocks.size(); + + // 2) Partition the window. + auto partitioned_window = partition_window(window); + + // 3) Partition the blocks. + partition_blocks_in_window(window, partitioned_window, group_id, p_placement); + + // 4) Enqueue the new windows. + window_queue.push(std::move(partitioned_window.lower_window)); + window_queue.push(std::move(partitioned_window.upper_window)); + + // Pop the top element off the queue. This will invalidate the window + // object. + window_queue.pop(); + } + + if (log_verbosity_ >= 10) { + VTR_LOG("\t%zu finalized windows.\n", + finished_windows.size()); + + if (log_verbosity_ >= 30) { + for (const SpreadingWindow& window : finished_windows) { + VTR_LOG("\t\t[(%.1f, %.1f), (%.1f, %.1f)]\n", + window.region.xmin(), window.region.ymin(), + window.region.xmax(), window.region.ymax()); + PrimitiveVector window_capacity = capacity_prefix_sum_.get_sum(model_grouper_.get_models_in_group(group_id), + window.region); + VTR_LOG("\t\t\tCapacity: %f\n", + window_capacity.manhattan_norm()); + VTR_LOG("\t\t\tNumber of contained blocks: %zu\n", + window.contained_blocks.size()); + } + } + } + + // Move the blocks into the bins. + move_blocks_out_of_windows(finished_windows); + + // Verify that the bins are valid after moving blocks back from windows. + VTR_ASSERT_SAFE(density_manager_->verify()); +} + +PartitionedWindow BiPartitioningPartialLegalizer::partition_window(SpreadingWindow& window) { + PartitionedWindow partitioned_window; + + // Select the partition direction. + // To keep it simple, we partition the direction which would cut the + // region the most. + // TODO: Should explore making the partition line based on the capacity + // of the two partitioned regions. We may want to cut the + // region in half such that the mass of the atoms contained within + // the two future regions is equal. + partitioned_window.partition_dir = e_partition_dir::VERTICAL; + if (window.region.height() > window.region.width()) + partitioned_window.partition_dir = e_partition_dir::HORIZONTAL; + + // To keep it simple, just cut the space in half. + // TODO: Should investigate other cutting techniques. Cutting perfectly + // in half may not be the most efficient technique. + SpreadingWindow& lower_window = partitioned_window.lower_window; + SpreadingWindow& upper_window = partitioned_window.upper_window; + partitioned_window.pivot_pos = 0.f; + if (partitioned_window.partition_dir == e_partition_dir::VERTICAL) { + // Find the x-coordinate of a cut line directly in the middle of the + // region. We floor this to prevent fractional cut lines. + double pivot_x = std::floor((window.region.xmin() + window.region.xmax()) / 2.0); + + // Cut the region at this cut line. + lower_window.region = vtr::Rect(vtr::Point(window.region.xmin(), + window.region.ymin()), + vtr::Point(pivot_x, + window.region.ymax())); + + upper_window.region = vtr::Rect(vtr::Point(pivot_x, + window.region.ymin()), + vtr::Point(window.region.xmax(), + window.region.ymax())); + partitioned_window.pivot_pos = pivot_x; + } else { + VTR_ASSERT(partitioned_window.partition_dir == e_partition_dir::HORIZONTAL); + // Similarly in the y direction, find the non-fractional y coordinate + // to make a horizontal cut. + double pivot_y = std::floor((window.region.ymin() + window.region.ymax()) / 2.0); + + // Then cut the window. + lower_window.region = vtr::Rect(vtr::Point(window.region.xmin(), + window.region.ymin()), + vtr::Point(window.region.xmax(), + pivot_y)); + + upper_window.region = vtr::Rect(vtr::Point(window.region.xmin(), + pivot_y), + vtr::Point(window.region.xmax(), + window.region.ymax())); + partitioned_window.pivot_pos = pivot_y; + } + + return partitioned_window; +} + +void BiPartitioningPartialLegalizer::partition_blocks_in_window( + SpreadingWindow& window, + PartitionedWindow& partitioned_window, + ModelGroupId group_id, + const PartialPlacement& p_placement) { + + SpreadingWindow& lower_window = partitioned_window.lower_window; + SpreadingWindow& upper_window = partitioned_window.upper_window; + + // Get the capacity of each window partition. + const std::vector& model_indices = model_grouper_.get_models_in_group(group_id); + PrimitiveVector lower_window_capacity = capacity_prefix_sum_.get_sum(model_indices, + lower_window.region); + PrimitiveVector upper_window_capacity = capacity_prefix_sum_.get_sum(model_indices, + upper_window.region); + + // Due to the division by the area, we may get numerical underflows / + // overflows which accumulate. If they accumulate in the positive + // direction, it is not a big deal; but in the negative direction it + // will cause problems with the algorithm below. Clamp any negative + // numbers to 0. + lower_window_capacity.relu(); + upper_window_capacity.relu(); + PrimitiveVector lower_window_underfill = lower_window_capacity; + PrimitiveVector upper_window_underfill = upper_window_capacity; + VTR_ASSERT_SAFE(lower_window_underfill.is_non_negative()); + VTR_ASSERT_SAFE(upper_window_underfill.is_non_negative()); + + // FIXME: We need to take into account the current utilization of the + // fixed blocks... We need to take into account that they are there. + // Currently we assume the underfill is the capacity + // Without this, we may overfill blocks which have fixed blocks in + // them. + + // If the lower window has no space, put all of the blocks in the upper window. + // NOTE: We give some room due to numerical overflows from the prefix sum. + if (lower_window_underfill.manhattan_norm() < 0.01f) { + upper_window.contained_blocks = std::move(window.contained_blocks); + return; + } + // If the upper window has no space, put all of the blocks in the lower window. + if (upper_window_underfill.manhattan_norm() < 0.01f) { + lower_window.contained_blocks = std::move(window.contained_blocks); + return; + } + + // Reserve space in each of the windows to make insertion faster. + upper_window.contained_blocks.reserve(window.contained_blocks.size()); + lower_window.contained_blocks.reserve(window.contained_blocks.size()); + + // Sort the blocks and get the pivot index. The pivot index is the index in + // the windows contained block which decides which sub-window the block + // wants to be in. The blocks at indices [0, pivot) want to be in the lower + // window, blocks at indices [pivot, num_blks) want to be in the upper window. + // This want is based on the solved positions of the blocks. + size_t pivot; + if (partitioned_window.partition_dir == e_partition_dir::VERTICAL) { + // Sort the blocks in the window by the x coordinate. + std::sort(window.contained_blocks.begin(), window.contained_blocks.end(), [&](APBlockId a, APBlockId b) { + return p_placement.block_x_locs[a] < p_placement.block_x_locs[b]; + }); + auto upper = std::upper_bound(window.contained_blocks.begin(), + window.contained_blocks.end(), + partitioned_window.pivot_pos, + [&](double value, APBlockId blk_id) { + return value < p_placement.block_x_locs[blk_id]; + }); + pivot = std::distance(window.contained_blocks.begin(), upper); + } else { + VTR_ASSERT(partitioned_window.partition_dir == e_partition_dir::HORIZONTAL); + // Sort the blocks in the window by the y coordinate. + std::sort(window.contained_blocks.begin(), window.contained_blocks.end(), [&](APBlockId a, APBlockId b) { + return p_placement.block_y_locs[a] < p_placement.block_y_locs[b]; + }); + auto upper = std::upper_bound(window.contained_blocks.begin(), + window.contained_blocks.end(), + partitioned_window.pivot_pos, + [&](double value, APBlockId blk_id) { + return value < p_placement.block_y_locs[blk_id]; + }); + pivot = std::distance(window.contained_blocks.begin(), upper); + } + + // Try to place the blocks that want to be in the lower window from lower + // to upper. + std::vector unplaced_blocks; + for (size_t i = 0; i < pivot; i++) { + const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(window.contained_blocks[i]); + VTR_ASSERT_SAFE(lower_window_underfill.is_non_negative()); + // Try to put the blk in the window. + lower_window_underfill -= blk_mass; + if (lower_window_underfill.is_non_negative()) + // If the underfill is not negative, then we can add it to the window. + lower_window.contained_blocks.push_back(window.contained_blocks[i]); + else { + // If the underfill went negative, undo the addition and mark this + // block as unplaced. + lower_window_underfill += blk_mass; + unplaced_blocks.push_back(window.contained_blocks[i]); + } + } + // Try to place the blocks that want to be in the upper window from upper + // to lower. + // NOTE: This needs to be an int in case the pivot is 0. + for (int i = window.contained_blocks.size() - 1; i >= (int)pivot; i--) { + const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(window.contained_blocks[i]); + VTR_ASSERT_SAFE(lower_window_underfill.is_non_negative()); + upper_window_underfill -= blk_mass; + if (upper_window_underfill.is_non_negative()) + upper_window.contained_blocks.push_back(window.contained_blocks[i]); + else { + upper_window_underfill += blk_mass; + unplaced_blocks.push_back(window.contained_blocks[i]); + } + } + + // Handle the unplaced blocks. + // To handle these blocks, we will try to balance the overfill in both + // windows. To do this we sort the unplaced blocks by largest mass to + // smallest mass. Then we place each block in the bin with the highest + // underfill. + // FIXME: Above was the intuition; however, after experimentation, found that + // sorting by smallest mass to largest mass worked better... + // FIXME: I think large blocks (like carry chains) need to be handled special + // early on. If they are put into a partition too late, they may have + // to create overfill! Perhaps the partitions can hold two lists. + std::sort(unplaced_blocks.begin(), + unplaced_blocks.end(), + [&](APBlockId a, APBlockId b) { + const auto& blk_a_mass = density_manager_->mass_calculator().get_block_mass(a); + const auto& blk_b_mass = density_manager_->mass_calculator().get_block_mass(b); + return blk_a_mass.manhattan_norm() < blk_b_mass.manhattan_norm(); + }); + for (APBlockId blk_id : unplaced_blocks) { + // Project the underfill from each window onto the mass. This gives us + // the overfill in the dimensions the mass cares about. + const PrimitiveVector& blk_mass = density_manager_->mass_calculator().get_block_mass(blk_id); + PrimitiveVector projected_lower_window_underfill = lower_window_underfill; + lower_window_underfill.project(blk_mass); + PrimitiveVector projected_upper_window_underfill = upper_window_underfill; + upper_window_underfill.project(blk_mass); + // Put the block in the window with a higher underfill. This tries to + // balance the overfill as much as possible. This works even if the + // overfill becomes negative. + if (projected_lower_window_underfill.manhattan_norm() >= projected_upper_window_underfill.manhattan_norm()) { + lower_window.contained_blocks.push_back(blk_id); + lower_window_underfill -= blk_mass; + } else { + upper_window.contained_blocks.push_back(blk_id); + upper_window_underfill -= blk_mass; + } + } +} + +void BiPartitioningPartialLegalizer::move_blocks_out_of_windows( + std::vector& finished_windows) { + + for (const SpreadingWindow& window : finished_windows) { + // Get the bin at the center of the window. + vtr::Point center = get_center_of_rect(window.region); + FlatPlacementBinId bin_id = density_manager_->get_bin(center.x(), center.y(), 0); + + // Move all blocks in the window into this bin. + for (APBlockId blk_id : window.contained_blocks) { + // Note: The blocks should have been removed from their original + // bins when they were put into the windows. There are asserts + // within the denisty manager class which will verify this. + density_manager_->insert_block_into_bin(blk_id, bin_id); + } + } +} diff --git a/vpr/src/analytical_place/partial_legalizer.h b/vpr/src/analytical_place/partial_legalizer.h index 96171e5fdb5..2eb4e5771da 100644 --- a/vpr/src/analytical_place/partial_legalizer.h +++ b/vpr/src/analytical_place/partial_legalizer.h @@ -13,29 +13,24 @@ #pragma once +#include #include -#include #include #include "ap_netlist_fwd.h" +#include "ap_flow_enums.h" +#include "flat_placement_bins.h" +#include "flat_placement_density_manager.h" +#include "model_grouper.h" #include "primitive_vector.h" -#include "vtr_assert.h" #include "vtr_geometry.h" -#include "vtr_ndmatrix.h" -#include "vtr_strong_id.h" -#include "vtr_vector_map.h" +#include "vtr_prefix_sum.h" +#include "vtr_vector.h" // Forward declarations class APNetlist; +class Prepacker; struct PartialPlacement; -/** - * @brief Enumeration of all of the partial legalizers currently implemented in - * VPR. - */ -enum class e_partial_legalizer { - FLOW_BASED // Multi-commodity flow-based partial legalizer. -}; - /** * @brief The Partial Legalizer base class * @@ -46,7 +41,7 @@ enum class e_partial_legalizer { * compare different solvers. */ class PartialLegalizer { -public: + public: virtual ~PartialLegalizer() {} /** @@ -54,9 +49,9 @@ class PartialLegalizer { * * Currently just copies the parameters into the class as member varaibles. */ - PartialLegalizer(const APNetlist& netlist, int log_verbosity = 1) - : netlist_(netlist), - log_verbosity_(log_verbosity) {} + PartialLegalizer(const APNetlist& netlist, int log_verbosity) + : netlist_(netlist) + , log_verbosity_(log_verbosity) {} /** * @brief Partially legalize the given partial placement. @@ -71,10 +66,17 @@ class PartialLegalizer { * @param p_placement The placement to legalize. Will be filled with the * legalized placement. */ - virtual void legalize(PartialPlacement &p_placement) = 0; + virtual void legalize(PartialPlacement& p_placement) = 0; -protected: + /** + * @brief Print statistics on the Partial Legalizer. + * + * This is expected to be called at the end of Global Placement to provide + * cummulative information on how much work the partial legalizer performed. + */ + virtual void print_statistics() = 0; + protected: /// @brief The APNetlist the legalizer will be legalizing the placement of. /// It is implied that the netlist is not being modified during /// global placement. @@ -89,85 +91,11 @@ class PartialLegalizer { /** * @brief A factory method which creates a Partial Legalizer of the given type. */ -std::unique_ptr make_partial_legalizer(e_partial_legalizer legalizer_type, - const APNetlist& netlist); - -/** - * @brief A strong ID for the bins used in the partial legalizer. - * - * This allows a separation between the legalizers and tiles such that a bin may - * represent multiple tiles. - */ -struct legalizer_bin_tag {}; -typedef vtr::StrongId LegalizerBinId; - -/** - * @brief A bin used to contain blocks in the partial legalizer. - * - * Bins can be thought of as generalized tiles which have a capacity of blocks - * (and their types) and a current utilization of the bin. A bin may represent - * multiple tiles. - * - * The capacity, utilization, supply, and demand of the bin are stored as - * M-dimensional vectors; where M is the number of models (primitives) in the - * device. This allows the bin to quickly know how much of each types of - * primitives it can contain and how much of each type it currently contains. - */ -struct LegalizerBin { - /// @brief The blocks currently contained in this bin. - std::unordered_set contained_blocks; - - /// @brief The maximum mass of each primitive type this bin can contain. - PrimitiveVector capacity; - - /// @brief The current mass of each primitive type this bin contains. - PrimitiveVector utilization; - - /// @brief The current over-utilization of the bin. This is defined as: - /// elementwise_max(utilization - capacity, 0) - PrimitiveVector supply; - - /// @brief The current under-utilization of the bin. This is defined as: - /// elementwise_max(capacity - utilization, 0) - PrimitiveVector demand; - - /// @brief The bounding box of the bin on the device grid. This is the - /// positions on the grid the blocks will exist. - /// - /// For example, if the tile at location (2,3) was turned directly into a - /// bin, the bounding box of that bin would be [(2.0, 3.0), (3.0, 4.0)) - /// Notice the notation here. The left and bottom edges are included in the - /// set. - /// It is implied that blocks cannot be placed on the right or top edges of - /// the bounding box (since then they may be in another bin!). - /// - /// NOTE: This uses a double to match the precision of the positions of - /// APBlocks (which are doubles). The use of a double here also allows - /// bins to represent partial tiles which may be useful. - vtr::Rect bounding_box; - - /// @brief The neighbors of this bin. These are neighboring bins that this - /// bin can flow blocks to. - std::vector neighbors; - - /** - * @brief Helper method to compute the supply of the bin. - */ - void compute_supply() { - supply = utilization - capacity; - supply.relu(); - VTR_ASSERT_DEBUG(supply.is_non_negative()); - } - - /** - * @brief Helper method to compute the demand of the bin. - */ - void compute_demand() { - demand = capacity - utilization; - demand.relu(); - VTR_ASSERT_DEBUG(demand.is_non_negative()); - } -}; +std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer legalizer_type, + const APNetlist& netlist, + std::shared_ptr density_manager, + const Prepacker& prepacker, + int log_verbosity); /** * @brief A multi-commodity flow-based spreading partial legalizer. @@ -183,14 +111,9 @@ struct LegalizerBin { * on their work by generalizing it to any theoretical architecture which can be * expressed in VPR. * https://doi.org/10.1145/3289602.3293896 - * - * - * TODO: Make the bin size a parameter for the legalizer somehow. That way we - * can make 1x1 bins for very accurate legalizers and larger (clamped) for - * less accurate legalizers. */ class FlowBasedLegalizer : public PartialLegalizer { -private: + private: /// @brief The maximum number of iterations the legalizer can take. This /// prevents the legalizer from never converging if there is not /// enough space to flow blocks. @@ -208,99 +131,32 @@ class FlowBasedLegalizer : public PartialLegalizer { /// sufficient neighbors. static constexpr unsigned max_bin_neighbor_dist_ = 4; - /// @brief A vector of all the bins in the legalizer. - vtr::vector_map bins_; - - /// @brief A reverse lookup between every block and the bin they are - /// currently in. - vtr::vector_map block_bins_; - - /// @brief The mass of each APBlock, represented as a primitive vector. - vtr::vector_map block_masses_; - - /// @brief A lookup that gets the bin that represents every tile (and - /// sub-tile). - vtr::NdMatrix tile_bin_; - - /// @brief A set of overfilled bins. Instead of computing this when needed, - /// this list is maintained whenever a block is moved from one bin to - /// another. - std::unordered_set overfilled_bins_; + /// @brief The density manager which manages how the bins are constructed + /// and maintains how overfilled bins are. + std::shared_ptr density_manager_; - /** - * @brief Returns true if the given bin is overfilled. - */ - inline bool bin_is_overfilled(LegalizerBinId bin_id) const { - VTR_ASSERT_DEBUG(bin_id.is_valid()); - VTR_ASSERT_DEBUG(bins_[bin_id].supply.is_non_negative()); - // By definition, a bin is overfilled if its supply is non-zero. - return bins_[bin_id].supply.is_non_zero(); - } + /// @brief The neighbors of each bin. + /// + /// These are the closest bins in each direction for each model type to flow + /// from this bin into. + vtr::vector> bin_neighbors_; /** - * @brief Helper method to insert a block into a bin. - * - * This method maintains all the necessary state of the class and updates - * the bin the block is being inserted into. - * - * This method assumes that the given block is not currently in a bin. + * @brief Get the supply of the given bin. Supply is how much over-capacity + * the bin is. */ - inline void insert_blk_into_bin(APBlockId blk_id, LegalizerBinId bin_id) { - VTR_ASSERT_DEBUG(blk_id.is_valid()); - VTR_ASSERT_DEBUG(bin_id.is_valid()); - // Make sure that this block is not anywhere else. - VTR_ASSERT(block_bins_[blk_id] == LegalizerBinId::INVALID()); - // Insert the block into the bin. - block_bins_[blk_id] = bin_id; - LegalizerBin& bin = bins_[bin_id]; - bin.contained_blocks.insert(blk_id); - // Update the utilization, supply, and demand. - const PrimitiveVector& blk_mass = block_masses_[blk_id]; - bin.utilization += blk_mass; - bin.compute_supply(); - bin.compute_demand(); - // Update the overfilled bins since this bin may have become overfilled. - if (bin_is_overfilled(bin_id)) - overfilled_bins_.insert(bin_id); + inline const PrimitiveVector& get_bin_supply(FlatPlacementBinId bin_id) const { + // Supply is defined as the overfill of the bin. + return density_manager_->get_bin_overfill(bin_id); } /** - * @brief Helper method to remove a block from a bin. - * - * This method maintains all the necessary state of the class and updates - * the bin the block is being removed from. - * - * This method assumes that the given block is currently in the given bin. + * @brief Get the demand of the given bin. Demand is how much under-capacity + * the bin is. */ - inline void remove_blk_from_bin(APBlockId blk_id, LegalizerBinId bin_id) { - VTR_ASSERT_DEBUG(blk_id.is_valid()); - VTR_ASSERT_DEBUG(bin_id.is_valid()); - // Make sure that this block is in this bin. - VTR_ASSERT(block_bins_[blk_id] == bin_id); - LegalizerBin& bin = bins_[bin_id]; - VTR_ASSERT_DEBUG(bin.contained_blocks.count(blk_id) == 1); - // Remove the block from the bin. - block_bins_[blk_id] = LegalizerBinId::INVALID(); - bin.contained_blocks.erase(blk_id); - // Update the utilization, supply, and demand. - const PrimitiveVector& blk_mass = block_masses_[blk_id]; - bin.utilization -= blk_mass; - bin.compute_supply(); - bin.compute_demand(); - // Update the overfilled bins since this bin may no longer be - // overfilled. - if (!bin_is_overfilled(bin_id)) - overfilled_bins_.erase(bin_id); - } - - /** - * @brief Helper method to get the bin at the current device x and y tile - * coordinate. - */ - inline LegalizerBinId get_bin(size_t x, size_t y) const { - VTR_ASSERT_DEBUG(x < tile_bin_.dim_size(0)); - VTR_ASSERT_DEBUG(y < tile_bin_.dim_size(1)); - return tile_bin_[x][y]; + inline const PrimitiveVector& get_bin_demand(FlatPlacementBinId bin_id) const { + // Demand is defined as the underfill of the bin. + return density_manager_->get_bin_underfill(bin_id); } /** @@ -325,7 +181,7 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param src_bin_id The bin to compute the neighbors for. * @param num_models The number of models in the architecture. */ - void compute_neighbors_of_bin(LegalizerBinId src_bin_id, size_t num_models); + void compute_neighbors_of_bin(FlatPlacementBinId src_bin_id, size_t num_models); /** * @brief Debugging method which verifies that all the bins are valid. @@ -336,30 +192,7 @@ class FlowBasedLegalizer : public PartialLegalizer { * - Every bin has the correct utilization, supply, and demand * - The overfilled bins are correct */ - bool verify_bins() const; - - /** - * @brief Resets all of the bins from a previous call to partial legalize. - * - * This removes all of the blocks from the bins. - */ - void reset_bins(); - - /** - * @brief Import the given partial placement into bins. - * - * This is called at the beginning of legalize to prepare the bins with the - * current placement. - */ - void import_placement_into_bins(const PartialPlacement& p_placement); - - /** - * @brief Export the placement found from spreading the bins. - * - * This is called at the end of legalize to write back the result of the - * legalizer. - */ - void export_placement_from_bins(PartialPlacement& p_placement) const; + bool verify() const; /** * @brief Gets paths to flow blocks from the src_bin_id at a maximum cost @@ -371,9 +204,9 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param psi An algorithm parameter that increases over many * iterations. The "max-cost" a path can be. */ - std::vector> get_paths(LegalizerBinId src_bin_id, - const PartialPlacement& p_placement, - float psi); + std::vector> get_paths(FlatPlacementBinId src_bin_id, + const PartialPlacement& p_placement, + float psi); /** * @brief Flows the blocks along the given path. @@ -387,20 +220,21 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param psi An algorithm parameter that increases over many * iterations. The "max-cost" a path can be. */ - void flow_blocks_along_path(const std::vector& path, + void flow_blocks_along_path(const std::vector& path, const PartialPlacement& p_placement, float psi); -public: - + public: /** - * @brief Construcotr for the flow-based legalizer. + * @brief Constructor for the flow-based legalizer. * * Builds all of the bins, computing their capacities based on the device * description. Builds the connectivity of bins. Computes the mass of all * blocks in the netlist. */ - FlowBasedLegalizer(const APNetlist& netlist); + FlowBasedLegalizer(const APNetlist& netlist, + std::shared_ptr density_manager, + int log_verbosity); /** * @brief Performs flow-based spreading on the given partial placement. @@ -408,6 +242,290 @@ class FlowBasedLegalizer : public PartialLegalizer { * @param p_placement The placmeent to legalize. The result of the partial * legalizer will be stored in this object. */ - void legalize(PartialPlacement &p_placement) final; + void legalize(PartialPlacement& p_placement) final; + + void print_statistics() final {} +}; + +/** + * @brief A cluster of flat placement bins. + */ +typedef typename std::vector FlatPlacementBinCluster; + +/** + * @brief Enum for the direction of a partition. + */ +enum class e_partition_dir { + VERTICAL, + HORIZONTAL +}; + +/** + * @brief Spatial window used to spread the blocks contained within. + * + * This window's region is identified and grown until it has enough space to + * accomodate the blocks stored within. This window is then successivly + * partitioned until it is small enough (blocks are not too dense). + */ +struct SpreadingWindow { + /// @brief The blocks contained within this window. + std::vector contained_blocks; + + /// @brief The 2D region of space that this window covers. + vtr::Rect region; +}; + +/** + * @brief Struct to hold the information from partitioning a window. Contains + * the two window partitions and some information about how they were + * generated. + */ +struct PartitionedWindow { + /// @brief The direction of the partition. + e_partition_dir partition_dir; + + /// @brief The position that the parent window was split at. + double pivot_pos; + + /// @brief The lower window. This is the left partition when the direction + /// is vertical, and the bottom partition when the direction is + /// horizontal. + SpreadingWindow lower_window; + + /// @brief The upper window. This is the right partition when the direction + /// is vertical, and the top partition when the direction is + /// horizontal. + SpreadingWindow upper_window; +}; + +/** + * @brief Wrapper class around the prefix sum class which creates a prefix sum + * for each model type and has helper methods for getting the sums over + * regions. + */ +class PerModelPrefixSum2D { + public: + PerModelPrefixSum2D() = default; + + /** + * @brief Construct prefix sums for each of the models in the architecture. + * + * Uses the density manager to get the size of the placeable region. + * + * The lookup is a lambda used to populate the prefix sum. It provides + * the model index, x, and y to be populated. + */ + PerModelPrefixSum2D(const FlatPlacementDensityManager& density_manager, + t_model* user_models, + t_model* library_models, + std::function lookup); + + /** + * @brief Get the sum for a given model over the given region. + */ + float get_model_sum(int model_index, + const vtr::Rect& region) const; + + /** + * @brief Get the multi-dimensional sum over the given model indices over + * the given region. + */ + PrimitiveVector get_sum(const std::vector& model_indices, + const vtr::Rect& region) const; + + private: + /// @brief Per-Model Prefix Sums + std::vector> model_prefix_sum_; }; +/** + * @brief A bi-paritioning spreading full legalizer. + * + * This creates minimum spanning windows around overfilled bins in the device + * such that the capacity of the bins within the window is just higher than the + * current utilization of the bins within the window. These windows are then + * split in both region and contained atoms. This spatially spreads out the + * atoms within each window. This splitting continues until the windows are + * small enough and the atoms are placed. The benefit of this approach is that + * it cuts the problem size for each partition, which can yield improved + * performance when there is a lot of overfill. + * + * This technique is based on the lookahead legalizer in SimPL and the window- + * based legalization found in GPlace3.0. + * SimPL: https://doi.org/10.1145/2461256.2461279 + * GPlace3.0: https://doi.org/10.1145/3233244 + */ +class BiPartitioningPartialLegalizer : public PartialLegalizer { + private: + /// @brief The maximum gap between overfilled bins we can have in a flat + /// placement bin cluster. For example, if this is set to 1, we will + /// allow two overfilled bins to be clustered together if they only + /// have 1 non-overfilled bin of gap between them. + /// The rational behind this is that it allows us to predict that the windows + /// created for each cluster will overlap if they are within some gap distance. + /// Increasing this number too much may cluster bins together too much and + /// create large windows; decreasing this number will put more pressure on + /// the window generation code, which can increase window size and runtime. + /// TODO: Should this be distance instead of number of bins? + static constexpr int max_bin_cluster_gap_ = 2; + + public: + /** + * @brief Constructor for the bi-partitioning partial legalizer. + * + * Uses the provided denisity manager to identify the capacity and + * utilization of regions of the device. + */ + BiPartitioningPartialLegalizer(const APNetlist& netlist, + std::shared_ptr density_manager, + const Prepacker& prepacker, + int log_verbosity); + + /** + * @brief Perform bi-partitioning spreading on the given partial placement. + * + * @param p_placement + * The placement to legalize. The result of the partial legalizer + * will be stored in this object. + */ + void legalize(PartialPlacement& p_placement) final; + + /** + * @brief Print statistics on the BiPartitioning Partial Legalizer. + */ + void print_statistics() final; + + private: + // ======================================================================== + // Identifying spreading windows + // ======================================================================== + + /** + * @brief Identify spreading windows which contain overfilled bins in the + * given model group on the device and do not overlap. + * + * This process is split into 4 stages: + * 1) Overfilled bins are identified and clustered. + * 2) Grow windows around the overfilled bin clusters. These windows + * will grow until there is just enough space to accomodate the blocks + * within the window (capacity of the window is larger than the utilization). + * 3) Merge overlapping windows. + * 4) Move the blocks within these window regions from their bins into + * their windows. This updates the current utilization of bins, making + * spreading easier. + * + * We identify non-overlapping windows for different model groups independtly + * for a few reasons: + * - Each model group, by design, can be spread independent of each other. + * This reduces the problem size by the number of groups. + * - Without model groups, one block placed on the wrong side of the chip + * may create a window the size of the entire chip! This would rip up and + * spread all the blocks in the chip, which is very expensive. + * - This allows us to ignore block models which are already in legal + * positions. + */ + std::vector identify_non_overlapping_windows(ModelGroupId group_id); + + /** + * @brief Identifies clusters of overfilled bins for the given model group. + * + * This locates clusters of overfilled bins which are within a given + * distance from each other. + */ + std::vector get_overfilled_bin_clusters(ModelGroupId group_id); + + /** + * @brief Creates and grows minimum spanning windows around the given + * overfilled bin clusters. + * + * Here, minimum means that the windows are just large enough such that the + * capacity of the bins within the window is larger than the utilization for + * the given model group. + */ + std::vector get_min_windows_around_clusters( + const std::vector& overfilled_bin_clusters, + ModelGroupId group_id); + + /** + * @brief Merges overlapping windows in the given vector of windows. + * + * The resulting merged windows is stored in the given windows object. + */ + void merge_overlapping_windows(std::vector& windows); + + /** + * @brief Moves the blocks out of their bins and into their window. + * + * Only blocks in the given model group will be moved. + */ + void move_blocks_into_windows(std::vector& non_overlapping_windows, + ModelGroupId group_id); + + // ======================================================================== + // Spreading blocks over windows + // ======================================================================== + + /** + * @brief Spread the blocks over each of the given non-overlapping windows. + * + * The partial placement solution from the solver is used to decide which + * window partition to put a block into. The model group this window is + * spreading over can make it more efficient to make decisions. + */ + void spread_over_windows(std::vector& non_overlapping_windows, + const PartialPlacement& p_placement, + ModelGroupId group_id); + + /** + * @brief Partition the given window into two sub-windows. + * + * We return extra information about how the window was created; for example, + * the direction of the partition (vertical / horizontal) and the position + * of the cut. + */ + PartitionedWindow partition_window(SpreadingWindow& window); + + /** + * @brief Partition the blocks in the given window into the partitioned + * windows. + * + * This is kept separate from splitting the physical window region for + * cleanliness. After this point, the window will not have any atoms in + * it. + */ + void partition_blocks_in_window(SpreadingWindow& window, + PartitionedWindow& partitioned_window, + ModelGroupId group_id, + const PartialPlacement& p_placement); + + /** + * @brief Move the blocks out of the given windows and put them back into + * the correct bin according to the window that contains them. + */ + void move_blocks_out_of_windows(std::vector& finished_windows); + + private: + /// @brief The density manager which manages the capacity and utilization + /// of regions of the device. + std::shared_ptr density_manager_; + + /// @brief Grouper object which handles grouping together models which must + /// be spread together. Models are grouped based on the pack patterns + /// that they can form with each other. + ModelGrouper model_grouper_; + + /// @brief The prefix sum for the capacity of the device, as given by the + /// density manager. We will need to get the capacity of 2D regions + /// of the device very often for this partial legalizer. This data + /// structure greatly improves the time complexity of this operation. + /// + /// This is populated in the constructor and not modified. + PerModelPrefixSum2D capacity_prefix_sum_; + + /// @brief The number of times a window was partitioned in the legalizer. + unsigned num_windows_partitioned_ = 0; + + /// @brief The number of times a block was partitioned from one window into + /// another. This includes blocks which get partitioned multiple times. + unsigned num_blocks_partitioned_ = 0; +}; diff --git a/vpr/src/analytical_place/partial_placement.cpp b/vpr/src/analytical_place/partial_placement.cpp index fc80f43b4a7..4e52faecef0 100644 --- a/vpr/src/analytical_place/partial_placement.cpp +++ b/vpr/src/analytical_place/partial_placement.cpp @@ -43,13 +43,9 @@ bool PartialPlacement::verify_locs(const APNetlist& netlist, for (APBlockId blk_id : netlist.blocks()) { double x_pos = block_x_locs[blk_id]; double y_pos = block_y_locs[blk_id]; - if (std::isnan(x_pos) || - x_pos < 0.0 || - x_pos >= grid_width) + if (std::isnan(x_pos) || x_pos < 0.0 || x_pos >= grid_width) return false; - if (std::isnan(y_pos) || - y_pos < 0.0 || - y_pos >= grid_height) + if (std::isnan(y_pos) || y_pos < 0.0 || y_pos >= grid_height) return false; if (netlist.block_mobility(blk_id) == APBlockMobility::FIXED) { const APFixedBlockLoc& fixed_loc = netlist.block_loc(blk_id); @@ -120,4 +116,3 @@ bool PartialPlacement::verify(const APNetlist& netlist, // If all other verify methods passed, then the placement is valid. return true; } - diff --git a/vpr/src/analytical_place/partial_placement.h b/vpr/src/analytical_place/partial_placement.h index e111dd7bd79..bb7406fcd34 100644 --- a/vpr/src/analytical_place/partial_placement.h +++ b/vpr/src/analytical_place/partial_placement.h @@ -71,10 +71,10 @@ struct PartialPlacement { * @param netlist The APNetlist which contains the blocks to be placed. */ PartialPlacement(const APNetlist& netlist) - : block_x_locs(netlist.blocks().size(), -1.0), - block_y_locs(netlist.blocks().size(), -1.0), - block_layer_nums(netlist.blocks().size(), 0.0), - block_sub_tiles(netlist.blocks().size(), 0) { + : block_x_locs(netlist.blocks().size(), -1.0) + , block_y_locs(netlist.blocks().size(), -1.0) + , block_layer_nums(netlist.blocks().size(), 0.0) + , block_sub_tiles(netlist.blocks().size(), 0) { // Note: All blocks are initialized to: // x_loc = -1.0 // y_loc = -1.0 @@ -84,7 +84,7 @@ struct PartialPlacement { for (APBlockId blk_id : netlist.blocks()) { if (netlist.block_mobility(blk_id) != APBlockMobility::FIXED) continue; - const APFixedBlockLoc &loc = netlist.block_loc(blk_id); + const APFixedBlockLoc& loc = netlist.block_loc(blk_id); if (loc.x != -1) block_x_locs[blk_id] = loc.x; if (loc.y != -1) @@ -201,4 +201,3 @@ struct PartialPlacement { size_t grid_height, size_t grid_num_layers) const; }; - diff --git a/vpr/src/analytical_place/primitive_vector.h b/vpr/src/analytical_place/primitive_vector.h index 1dd7c4d5a4b..d76ae8b509d 100644 --- a/vpr/src/analytical_place/primitive_vector.h +++ b/vpr/src/analytical_place/primitive_vector.h @@ -10,8 +10,11 @@ #pragma once +#include #include #include +#include +#include "vtr_log.h" /** * @brief A sparse vector class to store an M-dimensional quantity of primitives @@ -30,7 +33,7 @@ * Primitive Vectors. */ class PrimitiveVector { -private: + private: /// @brief Storage container for the data of this primitive vector. /// /// This is stored as a map since it is assumed that the vector will be @@ -41,16 +44,31 @@ class PrimitiveVector { /// Perhaps we can just waste the space and use a vector. std::unordered_map data_; -public: + public: /** * @brief Add the value to the given dimension. * * This is a common enough feature to use its own setter. */ inline void add_val_to_dim(float val, size_t dim) { - if (data_.count(dim) == 0) - data_[dim] = 0.f; - data_[dim] += val; + auto it = data_.find(dim); + if (it == data_.end()) + data_.insert({dim, val}); + else { + it->second += val; + } + } + + /** + * @brief Subtract the value to the given dimension. + */ + inline void subtract_val_from_dim(float val, size_t dim) { + auto it = data_.find(dim); + if (it == data_.end()) + data_.insert({dim, -1.0f * val}); + else { + it->second -= val; + } } /** @@ -104,19 +122,26 @@ class PrimitiveVector { */ inline PrimitiveVector& operator+=(const PrimitiveVector& rhs) { for (const auto& p : rhs.data_) { - float dim_val = get_dim_val(p.first); - set_dim_val(p.first, dim_val + p.second); + add_val_to_dim(p.second, p.first); } return *this; } + /** + * @brief Element-wise addition of this with rhs. + */ + inline PrimitiveVector operator+(const PrimitiveVector& rhs) const { + PrimitiveVector res = *this; + res += rhs; + return res; + } + /** * @brief Element-wise de-accumulation of rhs into this. */ inline PrimitiveVector& operator-=(const PrimitiveVector& rhs) { for (const auto& p : rhs.data_) { - float dim_val = get_dim_val(p.first); - set_dim_val(p.first, dim_val - p.second); + subtract_val_from_dim(p.second, p.first); } return *this; } @@ -140,6 +165,25 @@ class PrimitiveVector { return *this; } + /** + * @brief Element-wise division with a scalar. + */ + inline PrimitiveVector& operator/=(float rhs) { + for (auto& p : data_) { + p.second /= rhs; + } + return *this; + } + + /** + * @brief Element-wise division with a scalar. + */ + inline PrimitiveVector operator/(float rhs) const { + PrimitiveVector res = *this; + res /= rhs; + return res; + } + /** * @brief Returns true if any dimension of this vector is less than any * dimension of rhs; false otherwise. @@ -168,12 +212,11 @@ class PrimitiveVector { * is positive, it will not change. */ inline void relu() { - for (auto& p : data_) { - // TODO: Should remove the zero elements from the map to improve - // efficiency. - if (p.second < 0.f) - p.second = 0.f; - } + std::erase_if(data_, [](const std::pair& p) { + // Note: we erase the numbers from the map to improve the performance + // of future operations on this vector. + return p.second <= 0.0f; + }); } /** @@ -234,12 +277,36 @@ class PrimitiveVector { inline void project(const PrimitiveVector& dir) { // For each dimension of this vector, if that dimension is zero in dir // set the dimension to zero. + std::erase_if(data_, [&](const std::pair& p) { + return dir.get_dim_val(p.first) == 0.0f; + }); + } + + /** + * @brief Gets the non-zero dimensions of this vector. + */ + inline std::vector get_non_zero_dims() const { + std::vector non_zero_dims; for (auto& p : data_) { - // TODO: Instead of zeroing the dimension, it should be removed - // from the map. - if (dir.get_dim_val(p.first) == 0.f) - p.second = 0.f; + if (p.second != 0.0f) + non_zero_dims.push_back(p.first); + } + return non_zero_dims; + } + + /** + * @brief Returns true if this and other do not share any non-zero dimensions. + */ + inline bool are_dims_disjoint(const PrimitiveVector& other) const { + for (const auto& p : other.data_) { + // If this and other both have a shared dimension, then they are not + // perpendicular. + if (p.second != 0.0f && get_dim_val(p.first) != 0.0f) { + return false; + } } + // If they do not share any dimensions, then they are perpendicular. + return true; } /** @@ -268,5 +335,13 @@ class PrimitiveVector { } return res; } -}; + /** + * @brief Debug printing method. + */ + inline void print() const { + for (const auto& p : data_) { + VTR_LOG("(%zu, %f)\n", p.first, p.second); + } + } +}; diff --git a/vpr/src/base/CheckSetup.cpp b/vpr/src/base/CheckSetup.cpp index e4a5ab8c8e7..923413ac498 100644 --- a/vpr/src/base/CheckSetup.cpp +++ b/vpr/src/base/CheckSetup.cpp @@ -5,8 +5,6 @@ #include "vpr_types.h" #include "vpr_error.h" #include "globals.h" -#include "read_xml_arch_file.h" - static constexpr int DYMANIC_PORT_RANGE_MIN = 49152; static constexpr int DYNAMIC_PORT_RANGE_MAX = 65535; @@ -36,7 +34,6 @@ void CheckSetup(const t_packer_opts& packer_opts, } } - if ((GLOBAL == router_opts.route_type) && (placer_opts.place_algorithm.is_timing_driven())) { /* Works, but very weird. Can't optimize timing well, since you're @@ -58,16 +55,14 @@ void CheckSetup(const t_packer_opts& packer_opts, "A block location file requires that placement is enabled.\n"); } - if (placer_opts.place_algorithm.is_timing_driven() && - placer_opts.place_static_move_prob.size() > NUM_PL_MOVE_TYPES) { + if (placer_opts.place_algorithm.is_timing_driven() && placer_opts.place_static_move_prob.size() > NUM_PL_MOVE_TYPES) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "The number of provided placer move probabilities (%d) should equal or less than the total number of supported moves (%d).\n", placer_opts.place_static_move_prob.size(), NUM_PL_MOVE_TYPES); } - if (!placer_opts.place_algorithm.is_timing_driven() && - placer_opts.place_static_move_prob.size() > NUM_PL_NONTIMING_MOVE_TYPES) { + if (!placer_opts.place_algorithm.is_timing_driven() && placer_opts.place_static_move_prob.size() > NUM_PL_NONTIMING_MOVE_TYPES) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "The number of placer non timing move probabilities (%d) should equal to or less than the total number of supported moves (%d).\n", placer_opts.place_static_move_prob.size(), @@ -87,10 +82,11 @@ void CheckSetup(const t_packer_opts& packer_opts, "Analytical placement should skip packing.\n"); } - // TODO: Should check that read_vpr_constraint_file is non-empty or - // check within analytical placement that the floorplanning has - // some fixed blocks somewhere. Maybe we can live without fixed - // blocks. + // Make sure that the timing tradeoff is valid. + if (ap_opts.ap_timing_tradeoff < 0.0f || ap_opts.ap_timing_tradeoff > 1.0f) { + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "ap_timing_tradeoff expects a value between 0.0 and 1.0"); + } // TODO: Should we enforce that the size of the device is fixed. This // goes with ensuring that some blocks are fixed. @@ -145,9 +141,9 @@ void CheckSetup(const t_packer_opts& packer_opts, if (server_opts.is_server_mode_enabled) { if (server_opts.port_num < DYMANIC_PORT_RANGE_MIN || server_opts.port_num > DYNAMIC_PORT_RANGE_MAX) { - VPR_FATAL_ERROR(VPR_ERROR_OTHER, - "Specified server port number `--port %d` is out of range [%d-%d]. Please specify a port number within that range.\n", - server_opts.port_num, DYMANIC_PORT_RANGE_MIN, DYNAMIC_PORT_RANGE_MAX); + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "Specified server port number `--port %d` is out of range [%d-%d]. Please specify a port number within that range.\n", + server_opts.port_num, DYMANIC_PORT_RANGE_MIN, DYNAMIC_PORT_RANGE_MAX); } } } diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index bc88df43135..5de45ed2bf8 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -9,12 +9,13 @@ #include #include #include -#include #include +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_math.h" #include "vtr_log.h" +#include "stats.h" #include "vpr_types.h" #include "vpr_error.h" @@ -152,7 +153,7 @@ DeviceGrid create_device_grid(const std::string& layout_name, const std::vector< // //We do not support auto layout now // // // VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); - + // } else { // //Use the specified device @@ -606,7 +607,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt // vtr::NdMatrix grid_priorities; // int num_layers = (int)grid_def.layers.size(); // vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); - + // //Track the current priority for each grid location // // Note that we initialize it to the lowest (i.e. most negative) possible value, so // // any user-specified priority will override the default empty grid @@ -1155,59 +1156,6 @@ static void CheckGrid(const DeviceGrid& grid) { } } -float calculate_device_utilization(const DeviceGrid& grid, const std::map& instance_counts) { - //Record the resources of the grid - std::map grid_resources; - for (int layer_num = 0; layer_num < grid.get_num_layers(); ++layer_num) { - for (int x = 0; x < (int)grid.width(); ++x) { - for (int y = 0; y < (int)grid.height(); ++y) { - int width_offset = grid.get_width_offset({x, y, layer_num}); - int height_offset = grid.get_height_offset({x, y, layer_num}); - if (width_offset == 0 && height_offset == 0) { - const auto& type = grid.get_physical_type({x, y, layer_num}); - ++grid_resources[type]; - } - } - } - } - - //Determine the area of grid in tile units - float grid_area = 0.; - for (auto& kv : grid_resources) { - t_physical_tile_type_ptr type = kv.first; - size_t count = kv.second; - - float type_area = type->width * type->height; - - grid_area += type_area * count; - } - - //Determine the area of instances in tile units - float instance_area = 0.; - for (auto& kv : instance_counts) { - if (is_empty_type(kv.first)) { - continue; - } - - t_physical_tile_type_ptr type = pick_physical_type(kv.first); - - size_t count = kv.second; - - float type_area = type->width * type->height; - - //Instances of multi-capaicty blocks take up less space - if (type->capacity != 0) { - type_area /= type->capacity; - } - - instance_area += type_area * count; - } - - float utilization = instance_area / grid_area; - - return utilization; -} - size_t count_grid_tiles(const DeviceGrid& grid) { return grid.get_num_layers() * grid.width() * grid.height(); } diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 53b4cdbf71d..81f97352e33 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -25,14 +25,6 @@ DeviceGrid create_device_grid(const std::string& layout_name, DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); -/** - * @brief Calculate the device utilization - * - * Calculate the device utilization (i.e. fraction of used grid tiles) - * foor the specified grid and resource requirements - */ -float calculate_device_utilization(const DeviceGrid& grid, const std::map& instance_counts); - /** * @brief Returns the effective size of the device * (size of the bounding box of non-empty grid tiles) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 53c6831b676..000e1ba2b59 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -1,6 +1,7 @@ #include #include +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_util.h" #include "vtr_log.h" @@ -24,6 +25,8 @@ #include "ShowSetup.h" static void SetupNetlistOpts(const t_options& Options, t_netlist_opts& NetlistOpts); +static void SetupAPOpts(const t_options& options, + t_ap_opts& apOpts); static void SetupPackerOpts(const t_options& Options, t_packer_opts* PackerOpts); static void SetupPlacerOpts(const t_options& Options, @@ -43,15 +46,14 @@ static void SetupSwitches(const t_arch& Arch, static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysis_opts); static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch); -static void SetupVibInf(const std::vector& PhysicalTileTypes, - const std::vector& Switches, - const std::vector& Segments, +static void SetupVibInf(const std::vector& PhysicalTileTypes, + const std::vector& Switches, + const std::vector& Segments, std::vector& vib_infs); static void ProcessFromOrToTokens(const std::vector Tokens, const std::vector& PhysicalTileTypes, const std::vector segments, std::vector& froms); static void parse_pin_name(const char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); - /** * @brief Identify which switch must be used for *track* to *IPIN* connections based on architecture file specification. * @param Arch Architecture file specification @@ -141,6 +143,7 @@ void SetupVPR(const t_options* options, fileNameOpts->read_vpr_constraints_file = options->read_vpr_constraints_file; fileNameOpts->write_vpr_constraints_file = options->write_vpr_constraints_file; fileNameOpts->write_constraints_file = options->write_constraints_file; + fileNameOpts->read_flat_place_file = options->read_flat_place_file; fileNameOpts->write_flat_place_file = options->write_flat_place_file; fileNameOpts->write_block_usage = options->write_block_usage; @@ -238,10 +241,14 @@ void SetupVPR(const t_options* options, SetupRoutingArch(*arch, routingArch); SetupTiming(*options, timingenabled, timing); SetupPackerOpts(*options, packerOpts); + SetupAPOpts(*options, *apOpts); routingArch->write_rr_graph_filename = options->write_rr_graph_file; routingArch->read_rr_graph_filename = options->read_rr_graph_file; + routingArch->read_rr_edge_override_filename = options->read_rr_edge_override_file; - SetupVibInf(device_ctx.physical_tile_types, arch->switches, arch->Segments, arch->vib_infs); + if (!arch->vib_infs.empty()) { + SetupVibInf(device_ctx.physical_tile_types, arch->switches, arch->Segments, arch->vib_infs); + } for (auto has_global_routing : arch->layer_global_routing) { device_ctx.inter_cluster_prog_routing_resources.emplace_back(has_global_routing); @@ -368,7 +375,7 @@ static void SetupSwitches(const t_arch& Arch, auto& device_ctx = g_vpr_ctx.mutable_device(); int switches_to_copy = (int)arch_switches.size(); - int num_arch_switches = (int)arch_switches.size();; + int num_arch_switches = (int)arch_switches.size(); find_ipin_cblock_switch_index(Arch, RoutingArch->wire_to_arch_ipin_switch, RoutingArch->wire_to_arch_ipin_switch_between_dice); @@ -561,7 +568,24 @@ static void SetupAnnealSched(const t_options& Options, } /** - * @brief Sets up the s_packer_opts structure based on users inputs and + * @brief Sets up the t_ap_opts structure based on users inputs and + * on the architecture specified. + * + * Error checking, such as checking for conflicting params is assumed + * to be done beforehand + */ +void SetupAPOpts(const t_options& options, + t_ap_opts& apOpts) { + apOpts.analytical_solver_type = options.ap_analytical_solver.value(); + apOpts.partial_legalizer_type = options.ap_partial_legalizer.value(); + apOpts.full_legalizer_type = options.ap_full_legalizer.value(); + apOpts.detailed_placer_type = options.ap_detailed_placer.value(); + apOpts.ap_timing_tradeoff = options.ap_timing_tradeoff.value(); + apOpts.log_verbosity = options.ap_verbosity.value(); +} + +/** + * @brief Sets up the t_packer_opts structure based on users inputs and * on the architecture specified. * * Error checking, such as checking for conflicting params is assumed @@ -578,7 +602,7 @@ void SetupPackerOpts(const t_options& Options, } //TODO: document? - PackerOpts->global_clocks = true; /* DEFAULT */ + PackerOpts->global_clocks = true; /* DEFAULT */ PackerOpts->allow_unrelated_clustering = Options.allow_unrelated_clustering; PackerOpts->connection_driven = Options.connection_driven_clustering; @@ -597,10 +621,6 @@ void SetupPackerOpts(const t_options& Options, PackerOpts->feasible_block_array_size = Options.pack_feasible_block_array_size; PackerOpts->use_attraction_groups = Options.use_attraction_groups; - //TODO: document? - PackerOpts->inter_cluster_net_delay = 1.0; /* DEFAULT */ - PackerOpts->auto_compute_inter_cluster_net_delay = true; - PackerOpts->device_layout = Options.device_layout; PackerOpts->timing_update_type = Options.timing_update_type; @@ -699,6 +719,7 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts) PlacerOpts->place_constraint_subtile = Options.place_constraint_subtile; PlacerOpts->floorplan_num_horizontal_partitions = Options.floorplan_num_horizontal_partitions; PlacerOpts->floorplan_num_vertical_partitions = Options.floorplan_num_vertical_partitions; + PlacerOpts->place_quench_only = Options.place_quench_only; PlacerOpts->seed = Options.Seed; @@ -773,8 +794,6 @@ static void SetupNocOpts(const t_options& Options, t_noc_opts* NocOpts) { } NocOpts->noc_sat_routing_log_search_progress = Options.noc_sat_routing_log_search_progress; NocOpts->noc_placement_file_name = Options.noc_placement_file_name; - - } static void SetupServerOpts(const t_options& Options, t_server_opts* ServerOpts) { @@ -1017,9 +1036,9 @@ static void do_reachability_analysis(t_physical_tile_type* physical_tile, } } -static void SetupVibInf(const std::vector& PhysicalTileTypes, - const std::vector& switches, - const std::vector& Segments, +static void SetupVibInf(const std::vector& PhysicalTileTypes, + const std::vector& switches, + const std::vector& Segments, std::vector& vib_infs) { VTR_ASSERT(!vib_infs.empty()); for (auto& vib_inf : vib_infs) { @@ -1063,10 +1082,9 @@ static void SetupVibInf(const std::vector& PhysicalTileTyp auto from_tokens = second_stage.from_tokens; for (const auto& from_token : from_tokens) { ProcessFromOrToTokens(from_token, PhysicalTileTypes, Segments, second_stage.froms); - } + } } vib_inf.set_second_stages(second_stages); - } } @@ -1080,8 +1098,7 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s from_inf.type_name = token[0]; from_inf.from_type = MUX; froms.push_back(from_inf); - } - else if (token.size() == 2) { + } else if (token.size() == 2) { std::string from_type_name = token[0]; e_multistage_mux_from_or_to_type from_type; for (int i_phy_type = 0; i_phy_type < (int)PhysicalTileTypes.size(); i_phy_type++) { @@ -1094,7 +1111,7 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s pb_type_name = new char[strlen(Token_char)]; port_name = new char[strlen(Token_char)]; parse_pin_name(Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); - + std::vector all_sub_tile_to_tile_pin_indices; for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { int sub_tile_capacity = sub_tile.capacity.total(); @@ -1114,7 +1131,7 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s } for (int pin_num = start; pin_num <= end; ++pin_num) { VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); - for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { + for (int capacity = 0; capacity < sub_tile_capacity; ++capacity) { int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; all_sub_tile_to_tile_pin_indices.push_back(physical_pin_index); @@ -1140,14 +1157,14 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s from_inf.phy_pin_index = all_sub_tile_to_tile_pin_indices[i]; froms.push_back(from_inf); } - + // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { // //int sub_tile_index = sub_tile.index; // int sub_tile_capacity = sub_tile.capacity.total(); // int i_port = 0; // for (; i_port < (int)sub_tile.ports.size(); ++i_port) { - + // if (!strcmp(sub_tile.ports[i_port].name, port_name)) { // if (start_pin_index == end_pin_index && start_pin_index < 0) { // start_pin_index = 0; @@ -1177,7 +1194,6 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s // } // } // } - } } for (int i_seg_type = 0; i_seg_type < (int)segments.size(); i_seg_type++) { @@ -1197,14 +1213,13 @@ static void ProcessFromOrToTokens(const std::vector Tokens, const s from_inf.seg_index = seg_index; froms.push_back(from_inf); } - + break; } } VTR_ASSERT(from_type == PB || from_type == SEGMENT); - - } - else { + + } else { std::string msg = vtr::string_fmt("Failed to parse vib mux from information '%s'", Token.c_str()); VTR_LOGF_ERROR(__FILE__, __LINE__, msg.c_str()); } @@ -1225,9 +1240,8 @@ static void parse_pin_name(const char* src_string, int* start_pin_index, int* en /* Format "pb_type_name.port_name" */ *start_pin_index = *end_pin_index = -1; - strcpy(source_string, src_string); - + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { if (source_string[ichar] == '.') source_string[ichar] = ' '; @@ -1269,7 +1283,7 @@ static void parse_pin_name(const char* src_string, int* start_pin_index, int* en "The end_pin_index and start_pin_index can be the same.\n", src_string); exit(1); - } + } } if (*end_pin_index < 0 || *start_pin_index < 0) { VTR_LOG_ERROR( diff --git a/vpr/src/base/SetupVibGrid.cpp b/vpr/src/base/SetupVibGrid.cpp index 98bd676f058..7a16df722cd 100644 --- a/vpr/src/base/SetupVibGrid.cpp +++ b/vpr/src/base/SetupVibGrid.cpp @@ -35,7 +35,7 @@ VibDeviceGrid create_vib_device_grid(std::string layout_name, const std::vector< //We do not support auto layout now // VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); - + } else { //Use the specified device @@ -78,7 +78,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ vtr::NdMatrix grid_priorities; int num_layers = (int)grid_def.layers.size(); vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); - + //Track the current priority for each grid location // Note that we initialize it to the lowest (i.e. most negative) possible value, so // any user-specified priority will override the default empty grid @@ -200,7 +200,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ //The minimum increment is the block dimension //VTR_ASSERT(type->width > 0); - if (incrx < 1/*size_t(type->width)*/) { + if (incrx < 1 /*size_t(type->width)*/) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incrx for block type '%s' must be at least" " block width (%d) to avoid overlapping instances (was %s = %d)", @@ -208,7 +208,7 @@ static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_ } //VTR_ASSERT(type->height > 0); - if (incry < 1/*size_t(type->height)*/) { + if (incry < 1 /*size_t(type->height)*/) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incry for block type '%s' must be at least" " block height (%d) to avoid overlapping instances (was %s = %d)", @@ -336,13 +336,14 @@ static void set_vib_grid_block_type(int priority, // //We arbitrarily decide to take the 'last applied' wins approach, and warn the user //about the potential ambiguity + std::string type_name = (type == nullptr) ? "nullptr" : type->get_name(); VTR_LOG_WARN( "Ambiguous block type specification at grid location (%zu,%zu)." " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." " The last specification will apply.\n", x_root, y_root, max_priority_type_loc.type->get_name().c_str(), max_priority_type_loc.x, max_priority_type_loc.y, - priority, type->get_name().c_str()); + priority, type_name.c_str()); } //Mark all the grid tiles 'covered' by this block with the appropriate type @@ -361,7 +362,7 @@ static void set_vib_grid_block_type(int priority, if (grid_tile != nullptr //&& grid_tile.type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE - ) { + ) { //We are overriding a non-empty block, we need to be careful //to ensure we remove any blocks which will be invalidated when we //overwrite part of their locations diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index b89c21ca4e2..f21200e97ee 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -1,17 +1,15 @@ -#include -#include - -#include "vtr_assert.h" -#include "vtr_log.h" -#include "vpr_types.h" -#include "vpr_error.h" +#include "ShowSetup.h" +#include "ap_flow_enums.h" #include "globals.h" -#include "echo_files.h" -#include "read_options.h" -#include "read_xml_arch_file.h" -#include "ShowSetup.h" +#include "physical_types_util.h" +#include "vpr_error.h" +#include "vpr_types.h" +#include "vtr_assert.h" +#include "vtr_log.h" +#include +#include /******** Function Prototypes ********/ static void ShowPackerOpts(const t_packer_opts& PackerOpts); @@ -254,6 +252,9 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) { VTR_LOG("RouterOpts.router_algorithm: "); switch (RouterOpts.router_algorithm) { + case NESTED: + VTR_LOG("NESTED\n"); + break; case PARALLEL: VTR_LOG("PARALLEL\n"); break; @@ -597,8 +598,59 @@ static void ShowPlacerOpts(const t_placer_opts& PlacerOpts) { } static void ShowAnalyticalPlacerOpts(const t_ap_opts& APOpts) { - (void)APOpts; - // Currently nothing to show, but will happen eventually. + VTR_LOG("AnalyticalPlacerOpts.analytical_solver_type: "); + switch (APOpts.analytical_solver_type) { + case e_ap_analytical_solver::QP_Hybrid: + VTR_LOG("qp-hybrid\n"); + break; + case e_ap_analytical_solver::LP_B2B: + VTR_LOG("lp-b2b\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown analytical_solver_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.partial_legalizer_type: "); + switch (APOpts.partial_legalizer_type) { + case e_ap_partial_legalizer::BiPartitioning: + VTR_LOG("bipartitioning\n"); + break; + case e_ap_partial_legalizer::FlowBased: + VTR_LOG("flow-based\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown partial_legalizer_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.full_legalizer_type: "); + switch (APOpts.full_legalizer_type) { + case e_ap_full_legalizer::Naive: + VTR_LOG("naive\n"); + break; + case e_ap_full_legalizer::APPack: + VTR_LOG("appack\n"); + break; + case e_ap_full_legalizer::Basic_Min_Disturbance: + VTR_LOG("basic-min-disturbance\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown full_legalizer_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.detailed_placer_type: "); + switch (APOpts.detailed_placer_type) { + case e_ap_detailed_placer::Identity: + VTR_LOG("none\n"); + break; + case e_ap_detailed_placer::Annealer: + VTR_LOG("annealer\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown detailed_placer_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.ap_timing_tradeoff: %f\n", APOpts.ap_timing_tradeoff); + VTR_LOG("AnalyticalPlacerOpts.log_verbosity: %d\n", APOpts.log_verbosity); } static void ShowNetlistOpts(const t_netlist_opts& NetlistOpts) { @@ -706,7 +758,6 @@ static void ShowPackerOpts(const t_packer_opts& PackerOpts) { } VTR_LOG("PackerOpts.connection_driven: %s", (PackerOpts.connection_driven ? "true\n" : "false\n")); VTR_LOG("PackerOpts.global_clocks: %s", (PackerOpts.global_clocks ? "true\n" : "false\n")); - VTR_LOG("PackerOpts.inter_cluster_net_delay: %f\n", PackerOpts.inter_cluster_net_delay); VTR_LOG("PackerOpts.timing_driven: %s", (PackerOpts.timing_driven ? "true\n" : "false\n")); VTR_LOG("PackerOpts.target_external_pin_util: %s", vtr::join(PackerOpts.target_external_pin_util, " ").c_str()); VTR_LOG("\n"); diff --git a/vpr/src/base/atom_lookup.cpp b/vpr/src/base/atom_lookup.cpp index eb597ff8abd..c487e5e6549 100644 --- a/vpr/src/base/atom_lookup.cpp +++ b/vpr/src/base/atom_lookup.cpp @@ -4,51 +4,6 @@ #include "vtr_optional.h" #include "atom_lookup.h" -/* - * PB - */ -const t_pb* AtomLookup::atom_pb(const AtomBlockId blk_id) const { - auto iter = atom_to_pb_.find(blk_id); - if (iter == atom_to_pb_.end()) { - //Not found - return nullptr; - } - return iter->second; -} - -AtomBlockId AtomLookup::pb_atom(const t_pb* pb) const { - auto iter = atom_to_pb_.find(pb); - if (iter == atom_to_pb_.inverse_end()) { - //Not found - return AtomBlockId::INVALID(); - } - return iter->second; -} - -const t_pb_graph_node* AtomLookup::atom_pb_graph_node(const AtomBlockId blk_id) const { - const t_pb* pb = atom_pb(blk_id); - if (pb) { - //Found - return pb->pb_graph_node; - } - return nullptr; -} - -void AtomLookup::set_atom_pb(const AtomBlockId blk_id, const t_pb* pb) { - //If either of blk_id or pb are not valid, - //remove any mapping - - if (!blk_id && pb) { - //Remove - atom_to_pb_.erase(pb); - } else if (blk_id && !pb) { - //Remove - atom_to_pb_.erase(blk_id); - } else if (blk_id && pb) { - //If both are valid store the mapping - atom_to_pb_.update(blk_id, pb); - } -} /* * PB Pins @@ -112,8 +67,8 @@ void AtomLookup::add_atom_clb_net(const AtomNetId atom_net, const ClusterNetId c clb_net_to_atom_net_[clb_net] = atom_net; } -void AtomLookup::remove_clb_net(const ClusterNetId clb_net){ - if(!clb_net_to_atom_net_.count(clb_net)) +void AtomLookup::remove_clb_net(const ClusterNetId clb_net) { + if (!clb_net_to_atom_net_.count(clb_net)) return; auto atom_net = clb_net_to_atom_net_[clb_net]; @@ -124,11 +79,11 @@ void AtomLookup::remove_clb_net(const ClusterNetId clb_net){ /* Remove mapping for given atom net */ void AtomLookup::remove_atom_net(const AtomNetId atom_net) { - if(!atom_net_to_clb_nets_.count(atom_net)) + if (!atom_net_to_clb_nets_.count(atom_net)) return; auto cluster_nets = atom_net_to_clb_nets_[atom_net]; - for(auto c: cluster_nets){ + for (auto c : cluster_nets) { clb_net_to_atom_net_.erase(c); } atom_net_to_clb_nets_.erase(atom_net); diff --git a/vpr/src/base/atom_lookup.h b/vpr/src/base/atom_lookup.h index fdf17cddd46..8a218fae207 100644 --- a/vpr/src/base/atom_lookup.h +++ b/vpr/src/base/atom_lookup.h @@ -14,6 +14,7 @@ #include "tatum/TimingGraphFwd.hpp" #include "vtr_optional.h" +#include "atom_pb_bimap.h" /** * @brief The AtomLookup class describes the mapping between components in the AtomNetlist @@ -31,23 +32,45 @@ class AtomLookup { */ /** - * @brief Returns the leaf pb associated with the atom blk_id - * @note this is the lowest level pb which corresponds directly to the atom block + * @brief Sets the atom to pb bimap access lock to value. + * If set to true, access to the bimap is prohibited and will result in failing assertions. + * + * @param value Value to set to lock to */ - const t_pb* atom_pb(const AtomBlockId blk_id) const; - - ///@brief Returns the atom block id associated with pb - AtomBlockId pb_atom(const t_pb* pb) const; - - ///@brief Conveneince wrapper around atom_pb to access the associated graph node - const t_pb_graph_node* atom_pb_graph_node(const AtomBlockId blk_id) const; + inline void set_atom_pb_bimap_lock(bool value) { + VTR_ASSERT_SAFE_MSG(lock_atom_pb_bimap_ != value, "Double locking or unlocking the atom pb bimap lock"); + lock_atom_pb_bimap_ = value; + } + + /// @brief Gets the current atom to pb bimap lock value. + inline bool atom_pb_bimap_islocked() const { return lock_atom_pb_bimap_; } + + // All accesses, mutable or immutable, to the atom to pb bimap + // will result in failing assertions if the lock is set to true. + // This is done to make sure there is only a single source of + // data in places that are supposed to use a local data structure + // instead of the global context. + + /// @brief Returns a mutable reference to the atom to pb bimap, provided that access to it is unlocked. It will result in a crash otherwise. + /// @return Mutable reference to the atom pb bimap. + inline AtomPBBimap& mutable_atom_pb_bimap() { + VTR_ASSERT(!lock_atom_pb_bimap_); + return atom_to_pb_bimap_; + } + + /// @brief Returns an immutable reference to the atom to pb bimap, provided that access to it is unlocked. It will result in a crash otherwise. + /// @return Immutable reference to the atom pb bimap. + inline const AtomPBBimap& atom_pb_bimap() const { + VTR_ASSERT(!lock_atom_pb_bimap_); + return atom_to_pb_bimap_; + } /** - * @brief Sets the bidirectional mapping between an atom and pb - * - * If either blk_id or pb are not valid any, existing mapping is removed + * @brief Set atom to pb bimap + * + * @param atom_to_pb Reference to AtomPBBimab to be copied from */ - void set_atom_pb(const AtomBlockId blk_id, const t_pb* pb); + void set_atom_to_pb_bimap(const AtomPBBimap& atom_to_pb) { atom_to_pb_bimap_ = atom_to_pb; } /* * PB Pins @@ -112,7 +135,12 @@ class AtomLookup { private: //Types private: - vtr::bimap atom_to_pb_; + /** + * @brief Allows or disallows access to the AtomPBBimap data. + * Useful to make sure global context is not accessed in places you don't want it to. + */ + bool lock_atom_pb_bimap_ = false; + AtomPBBimap atom_to_pb_bimap_; vtr::vector_map atom_pin_to_pb_graph_pin_; diff --git a/vpr/src/base/blk_loc_registry.cpp b/vpr/src/base/blk_loc_registry.cpp index 70f809cdcd9..2e5b1f2c5bb 100644 --- a/vpr/src/base/blk_loc_registry.cpp +++ b/vpr/src/base/blk_loc_registry.cpp @@ -1,18 +1,66 @@ #include "blk_loc_registry.h" +#include "device_grid.h" #include "move_transactions.h" #include "globals.h" +#include "physical_types_util.h" +#include "vpr_context.h" +#include "vpr_utils.h" BlkLocRegistry::BlkLocRegistry() : expected_transaction_(e_expected_transaction::APPLY) {} +void BlkLocRegistry::init() { + const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + auto& block_locs = mutable_block_locs(); + auto& grid_blocks = mutable_grid_blocks(); + + /* Initialize the lookup of CLB block positions */ + block_locs.clear(); + block_locs.resize(clb_nlist.blocks().size()); + + /* Initialize the reverse lookup of CLB block positions */ + grid_blocks.init_grid_blocks(device_grid); + + /* Initialize the grid blocks to empty. + * Initialize all the blocks to unplaced. + */ + clear_all_grid_locs(); +} + +void BlkLocRegistry::alloc_and_load_movable_blocks() { + const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + const auto& logical_block_types = g_vpr_ctx.device().logical_block_types; + const auto& all_block_locs = block_locs(); + auto& movable_blocks = mutable_movable_blocks(); + auto& movable_blocks_per_type = mutable_movable_blocks_per_type(); + + // TODO: Are these clears necessary? + movable_blocks.clear(); + movable_blocks_per_type.clear(); + + movable_blocks_per_type.resize(logical_block_types.size()); + + // Iterate over all clustered blocks and store block ids of movable ones. + for (ClusterBlockId blk_id : clb_nlist.blocks()) { + const t_block_loc& loc = all_block_locs[blk_id]; + if (!loc.is_fixed) { + movable_blocks.push_back(blk_id); + + const t_logical_block_type_ptr block_type = clb_nlist.block_type(blk_id); + movable_blocks_per_type[block_type->index].push_back(blk_id); + } + } +} + const vtr::vector_map& BlkLocRegistry::block_locs() const { - return block_locs_; + return block_locs_; } vtr::vector_map& BlkLocRegistry::mutable_block_locs() { - return block_locs_; + return block_locs_; } const GridBlock& BlkLocRegistry::grid_blocks() const { @@ -44,14 +92,6 @@ int BlkLocRegistry::net_pin_to_tile_pin_index(const ClusterNetId net_id, int net return this->tile_pin_index(pin_id); } -const PlaceMacros& BlkLocRegistry::place_macros() const { - return place_macros_; -} - -PlaceMacros& BlkLocRegistry::mutable_place_macros() { - return place_macros_; -} - void BlkLocRegistry::set_block_location(ClusterBlockId blk_id, const t_pl_loc& location) { const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -201,9 +241,9 @@ void BlkLocRegistry::apply_move_blocks(const t_pl_blocks_to_be_moved& blocks_aff block_locs_[blk].loc = new_loc; // get physical tile type of the old location - t_physical_tile_type_ptr old_type = device_ctx.grid.get_physical_type({old_loc.x,old_loc.y,old_loc.layer}); + t_physical_tile_type_ptr old_type = device_ctx.grid.get_physical_type({old_loc.x, old_loc.y, old_loc.layer}); // get physical tile type of the new location - t_physical_tile_type_ptr new_type = device_ctx.grid.get_physical_type({new_loc.x,new_loc.y, new_loc.layer}); + t_physical_tile_type_ptr new_type = device_ctx.grid.get_physical_type({new_loc.x, new_loc.y, new_loc.layer}); // if physical tile type of old location does not equal physical tile type of new location, sync the new physical pins if (old_type != new_type) { diff --git a/vpr/src/base/blk_loc_registry.h b/vpr/src/base/blk_loc_registry.h index 9d3704f2c1c..145e15867c6 100644 --- a/vpr/src/base/blk_loc_registry.h +++ b/vpr/src/base/blk_loc_registry.h @@ -1,11 +1,10 @@ -#ifndef VTR_BLK_LOC_REGISTRY_H -#define VTR_BLK_LOC_REGISTRY_H + +#pragma once #include "clustered_netlist_fwd.h" #include "vtr_vector_map.h" #include "vpr_types.h" #include "grid_block.h" -#include "place_macro.h" struct t_block_loc; struct t_pl_blocks_to_be_moved; @@ -27,6 +26,15 @@ class BlkLocRegistry { BlkLocRegistry(BlkLocRegistry&&) = delete; BlkLocRegistry& operator=(BlkLocRegistry&&) = delete; + /// @brief Initialize the block loc registry's internal data. Must be called + /// before any other method is called. + void init(); + + /// @brief Iterates over all of the placed blocks and stores block IDs of + /// moveable ones. Must be called after the fixed blocks have been + /// marked and before using the movable_blocks. + void alloc_and_load_movable_blocks(); + private: ///@brief Clustered block placement locations vtr::vector_map block_locs_; @@ -37,14 +45,13 @@ class BlkLocRegistry { ///@brief Clustered pin placement mapping with physical pin vtr::vector_map physical_pins_; - /** - * @brief Contains information about placement macros. - * A placement macro is a set of clustered blocks that must be placed - * in a way that is compliant with relative locations specified by the macro. - */ - PlaceMacros place_macros_; + /// @brief Stores ClusterBlockId of all movable clustered blocks + /// (blocks that are not locked down to a single location) + std::vector movable_blocks_; public: + ///@brief Stores ClusterBlockId of all movable clustered blocks of each block type + std::vector> movable_blocks_per_type_; const vtr::vector_map& block_locs() const; vtr::vector_map& mutable_block_locs(); @@ -60,11 +67,19 @@ class BlkLocRegistry { ///@brief Returns the physical pin of the tile, related to the given ClusterNedId, and the net pin index. int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) const; - ///@brief Returns a constant reference to placement macros. - const PlaceMacros& place_macros() const; + /// @brief Returns a constant reference to the vector of ClusterBlockIds of all movable clustered blocks. + const std::vector& movable_blocks() const { return movable_blocks_; } + + /// @brief Returns a mutable reference to the vector of ClusterBlockIds of all movable clustered blocks. + std::vector& mutable_movable_blocks() { return movable_blocks_; } - ///@brief Returns a mutable reference to placement macros. - PlaceMacros& mutable_place_macros(); + /// @brief Returns a constant reference to a vector of vectors, where each inner vector contains ClusterBlockIds + /// of movable clustered blocks for a specific block type + const std::vector>& movable_blocks_per_type() const { return movable_blocks_per_type_; } + + /// @brief Returns a mutable reference to a vector of vectors, where each inner vector contains ClusterBlockIds + /// of movable clustered blocks for a specific block type. + std::vector>& mutable_movable_blocks_per_type() { return movable_blocks_per_type_; } /** * @brief Performs error checking to see if location is legal for block type, @@ -149,5 +164,3 @@ class BlkLocRegistry { e_expected_transaction expected_transaction_; }; - -#endif //VTR_BLK_LOC_REGISTRY_H diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index cd800003a5f..a80e3d7d76c 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -7,6 +7,7 @@ #include #include +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -16,7 +17,6 @@ #include "hash.h" #include "vpr_utils.h" #include "check_netlist.h" -#include "read_xml_arch_file.h" #define ERROR_THRESHOLD 100 diff --git a/vpr/src/base/clustered_netlist.cpp b/vpr/src/base/clustered_netlist.cpp index 180b60e35bd..2f2fce860a4 100644 --- a/vpr/src/base/clustered_netlist.cpp +++ b/vpr/src/base/clustered_netlist.cpp @@ -1,7 +1,7 @@ #include "clustered_netlist.h" - +#include "globals.h" +#include "physical_types_util.h" #include "vtr_assert.h" -#include "vpr_error.h" #include @@ -171,7 +171,7 @@ ClusterNetId ClusteredNetlist::create_net(const std::string& name) { void ClusteredNetlist::remove_block_impl(const ClusterBlockId blk_id) { //Remove & invalidate pointers - free_pb(block_pbs_[blk_id]); + free_pb(block_pbs_[blk_id], g_vpr_ctx.mutable_atom().mutable_lookup().mutable_atom_pb_bimap()); delete block_pbs_[blk_id]; block_pbs_.insert(blk_id, NULL); block_types_.insert(blk_id, NULL); diff --git a/vpr/src/base/clustered_netlist_utils.cpp b/vpr/src/base/clustered_netlist_utils.cpp index 8fbdff8b658..798c03ca250 100644 --- a/vpr/src/base/clustered_netlist_utils.cpp +++ b/vpr/src/base/clustered_netlist_utils.cpp @@ -45,8 +45,8 @@ void ClusterAtomsLookup::init_lookup() { cluster_atoms.resize(cluster_ctx.clb_nlist.blocks().size()); - for (auto atom_blk_id : atom_ctx.nlist.blocks()) { - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(atom_blk_id); + for (auto atom_blk_id : atom_ctx.netlist().blocks()) { + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(atom_blk_id); /* if this data structure is being built alongside the clustered netlist */ /* e.g. when ingesting and legalizing a flat placement solution, some atoms */ diff --git a/vpr/src/base/flat_placement_types.h b/vpr/src/base/flat_placement_types.h new file mode 100644 index 00000000000..6ece9b2d318 --- /dev/null +++ b/vpr/src/base/flat_placement_types.h @@ -0,0 +1,141 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Declaration of flat placement types used throughout VPR. + */ + +#pragma once + +#include "atom_netlist.h" +#include "vtr_assert.h" +#include "vtr_vector.h" + +/** + * @brief A structure representing a flat placement location on the device. + * + * This is related to the t_pl_loc type; however this uses floating point + * coordinates, allowing for blocks to be placed in illegal positions. + */ +struct t_flat_pl_loc { + float x; /**< The x-coordinate of the location. */ + float y; /**< The y-coordinate of the location. */ + float layer; /**< The layer of the location. */ + + /** + * @brief Adds the coordinates of another t_flat_pl_loc to this one. + * + * @param other The other t_flat_pl_loc whose coordinates are to be added. + * @return A reference to this t_flat_pl_loc after addition. + */ + t_flat_pl_loc& operator+=(const t_flat_pl_loc& other) { + x += other.x; + y += other.y; + layer += other.layer; + return *this; + } + + /** + * @brief Subtracts the coordinates of another t_flat_pl_loc to this one. + */ + t_flat_pl_loc& operator-=(const t_flat_pl_loc& other) { + x -= other.x; + y -= other.y; + layer -= other.layer; + return *this; + } + + /** + * @brief Divides the coordinates of this t_flat_pl_loc by a divisor. + * + * @param divisor The value by which to divide the coordinates. + * @return A reference to this t_flat_pl_loc after division. + */ + t_flat_pl_loc& operator/=(float divisor) { + x /= divisor; + y /= divisor; + layer /= divisor; + return *this; + } +}; + +/** + * @brief Flat placement storage class. + * + * This stores placement information for each atom in the netlist. It contains + * any information that may be used by the packer to better create clusters. + */ +class FlatPlacementInfo { + public: + /// @brief Identifier for an undefined position. + static constexpr float UNDEFINED_POS = -1.f; + /// @brief Identifier for an undefined sub tile. + static constexpr int UNDEFINED_SUB_TILE = -1; + /// @brief Identifier for an undefined site idx. + static constexpr int UNDEFINED_SITE_IDX = -1; + + // The following three floating point numbers describe the flat position of + // an atom block. These are floats instead of integers to allow for flat + // placements which are not quite legal (ok to be off-grid). This allows + // the flat placement to encode information about where atom blocks would + // want to go if they cannot be placed at the grid position they are at. + // (for example, a block placed at (0.9, 0.9) wants to be at tile (0, 0), + // but if thats not possible it would prefer (1, 1) over anything else. + + /// @brief The x-positions of each atom block. Is UNDEFINED_POS if undefined. + vtr::vector blk_x_pos; + /// @brief The y-positions of each atom block. Is UNDEFINED_POS if undefined. + vtr::vector blk_y_pos; + /// @brief The layer of each atom block. Is UNDEFINED_POS if undefined. + vtr::vector blk_layer; + + /// @brief The sub tile location of each atom block. Is UNDEFINED_SUB_TILE + /// if undefined. + vtr::vector blk_sub_tile; + /// @brief The flat site idx of each atom block. This is an optional index + /// into a linearized list of primitive locations within a cluster- + /// level block. Is UNDEFINED_SITE_IDX if undefined. + vtr::vector blk_site_idx; + + /// @brief A flag to signify if this object has been constructed with data + /// or not. This makes it easier to detect if a flat placement exists + /// or not. Is true when a placement has been loaded into this + /// object, false otherwise. + bool valid; + + /** + * @brief Get the flat placement location of the given atom block. + */ + inline t_flat_pl_loc get_pos(AtomBlockId blk_id) const { + VTR_ASSERT_SAFE_MSG(blk_id.is_valid(), "Block ID is invalid"); + VTR_ASSERT_SAFE_MSG(valid, "FlatPlacementInfo not initialized"); + return {blk_x_pos[blk_id], blk_y_pos[blk_id], blk_layer[blk_id]}; + } + + /** + * @brief Default constructor of this class. + * + * Initializes the data structure to invalid so it can be easily checked to + * be uninitialized. + */ + FlatPlacementInfo() + : valid(false) {} + + /** + * @brief Constructs the flat placement with undefined positions for each + * atom block in the atom netlist. + * + * The valid flag is set to true here, since this structure is now + * initialized with data and can be used. + * + * @param atom_netlist + * The netlist of atom blocks in the circuit. + */ + FlatPlacementInfo(const AtomNetlist& atom_netlist) + : blk_x_pos(atom_netlist.blocks().size(), UNDEFINED_POS) + , blk_y_pos(atom_netlist.blocks().size(), UNDEFINED_POS) + , blk_layer(atom_netlist.blocks().size(), UNDEFINED_POS) + , blk_sub_tile(atom_netlist.blocks().size(), UNDEFINED_SUB_TILE) + , blk_site_idx(atom_netlist.blocks().size(), UNDEFINED_SITE_IDX) + , valid(true) {} +}; diff --git a/vpr/src/base/flat_placement_utils.h b/vpr/src/base/flat_placement_utils.h new file mode 100644 index 00000000000..eef37489585 --- /dev/null +++ b/vpr/src/base/flat_placement_utils.h @@ -0,0 +1,20 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Utility methods for working with flat placements. + */ + +#pragma once + +#include +#include "flat_placement_types.h" + +/** + * @brief Returns the manhattan distance (L1 distance) between two flat + * placement locations. + */ +inline float get_manhattan_distance(const t_flat_pl_loc& loc_a, + const t_flat_pl_loc& loc_b) { + return std::abs(loc_a.x - loc_b.x) + std::abs(loc_a.y - loc_b.y) + std::abs(loc_a.layer - loc_b.layer); +} diff --git a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h index d12118cb066..6a835bf5a64 100644 --- a/vpr/src/base/gen/vpr_constraints_uxsdcxx.h +++ b/vpr/src/base/gen/vpr_constraints_uxsdcxx.h @@ -122,9 +122,9 @@ typedef const uint64_t __attribute__((aligned(1))) triehash_uu64; static_assert(alignof(triehash_uu32) == 1, "Unaligned 32-bit access not found."); static_assert(alignof(triehash_uu64) == 1, "Unaligned 64-bit access not found."); #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -# define onechar(c, s, l) (((uint64_t)(c)) << (s)) +#define onechar(c, s, l) (((uint64_t)(c)) << (s)) #else -# define onechar(c, s, l) (((uint64_t)(c)) << (l - 8 - s)) +#define onechar(c, s, l) (((uint64_t)(c)) << (l - 8 - s)) #endif /* Tokens for attribute and node names. */ @@ -1207,7 +1207,7 @@ inline void attr_error(std::bitset astate, const char* const* lookup, const s } inline void get_line_number(const char* filename, std::ptrdiff_t target_offset, int* line, int* col) { - std::unique_ptr f(fopen(filename, "rb"), fclose); + std::unique_ptr f(fopen(filename, "rb"), fclose); if (!f) { throw std::runtime_error(std::string("Failed to open file") + filename); diff --git a/vpr/src/base/grid_block.cpp b/vpr/src/base/grid_block.cpp index 9053830473e..4a6e35b0aba 100644 --- a/vpr/src/base/grid_block.cpp +++ b/vpr/src/base/grid_block.cpp @@ -1,7 +1,28 @@ #include "grid_block.h" +#include "device_grid.h" #include "globals.h" +#include "physical_types.h" + +void GridBlock::init_grid_blocks(const DeviceGrid& device_grid) { + size_t grid_width = device_grid.width(); + size_t grid_height = device_grid.height(); + size_t num_layers = device_grid.get_num_layers(); + + /* Structure should have the same dimensions as the grid. */ + grid_blocks_.resize({num_layers, grid_width, grid_height}); + + for (size_t layer_num = 0; layer_num < num_layers; layer_num++) { + for (size_t x = 0; x < grid_width; x++) { + for (size_t y = 0; y < grid_height; y++) { + const t_physical_tile_loc tile_loc({(int)x, (int)y, (int)layer_num}); + auto type = device_grid.get_physical_type(tile_loc); + initialized_grid_block_at_location(tile_loc, type->capacity); + } + } + } +} void GridBlock::zero_initialize() { auto& device_ctx = g_vpr_ctx.device(); @@ -55,5 +76,3 @@ int GridBlock::decrement_usage(const t_physical_tile_loc& loc) { return updated_usage; } - - diff --git a/vpr/src/base/grid_block.h b/vpr/src/base/grid_block.h index 12e934f0af9..d66cbc9fa26 100644 --- a/vpr/src/base/grid_block.h +++ b/vpr/src/base/grid_block.h @@ -38,6 +38,14 @@ class GridBlock { grid_blocks_.resize({layers, width, height}); } + /** + * @brief Initialize `grid_blocks`, the inverse structure of `block_locs`. + * + * The container at each grid block location should have a length equal to the + * subtile capacity of that block. Unused subtiles would be marked ClusterBlockId::INVALID(). + */ + void init_grid_blocks(const DeviceGrid& device_grid); + inline void initialized_grid_block_at_location(const t_physical_tile_loc& loc, int num_sub_tiles) { grid_blocks_[loc.layer_num][loc.x][loc.y].blocks.resize(num_sub_tiles, ClusterBlockId::INVALID()); } diff --git a/vpr/src/base/load_flat_place.cpp b/vpr/src/base/load_flat_place.cpp index f34d1f94680..14de1c6da1f 100644 --- a/vpr/src/base/load_flat_place.cpp +++ b/vpr/src/base/load_flat_place.cpp @@ -8,11 +8,40 @@ #include "load_flat_place.h" +#include +#include #include +#include "atom_lookup.h" +#include "atom_netlist.h" #include "clustered_netlist.h" +#include "flat_placement_types.h" #include "globals.h" #include "vpr_context.h" +#include "vpr_error.h" #include "vpr_types.h" +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_vector_map.h" +#include "vtr_version.h" + +/** + * @brief Prints the header for the flat placement file. This includes helpful + * information on how to read the file and when it was generated. + * + * @param fp + * File pointer to the file the cluster is printed to. + */ +static void print_flat_placement_file_header(FILE* fp) { + fprintf(fp, "# Flat Placement File\n"); + fprintf(fp, "# Auto-generated by VPR %s\n", + vtr::VERSION); + fprintf(fp, "# Created: %s\n", + vtr::BUILD_TIMESTAMP); + fprintf(fp, "#\n"); + fprintf(fp, "# This file prints the following information for each atom in the netlist:\n"); + fprintf(fp, "# # \n"); + fprintf(fp, "\n"); +} /** * @brief Prints flat placement file entries for the atoms in one placed @@ -30,7 +59,7 @@ */ static void print_flat_cluster(FILE* fp, ClusterBlockId blk_id, - const vtr::vector_map &block_locs, + const vtr::vector_map& block_locs, const vtr::vector>& atoms_lookup) { // Atom context used to get the atom_pb for each atom in the cluster. // NOTE: This is only used for getting the flat site index. @@ -42,12 +71,13 @@ static void print_flat_cluster(FILE* fp, // Print a line for each atom. for (AtomBlockId atom : atoms_lookup[blk_id]) { // Get the atom pb graph node. - t_pb_graph_node* atom_pbgn = atom_ctx.lookup.atom_pb(atom)->pb_graph_node; + t_pb_graph_node* atom_pbgn = atom_ctx.lookup().atom_pb_bimap().atom_pb(atom)->pb_graph_node; // Print the flat placement information for this atom. - fprintf(fp, "%s %d %d %d %d #%zu %s\n", - atom_ctx.nlist.block_name(atom).c_str(), - blk_loc.x, blk_loc.y, blk_loc.sub_tile, + fprintf(fp, "%s %d %d %d %d %d #%zu %s\n", + atom_ctx.netlist().block_name(atom).c_str(), + blk_loc.x, blk_loc.y, blk_loc.layer, + blk_loc.sub_tile, atom_pbgn->flat_site_index, static_cast(blk_id), atom_pbgn->pb_type->name); @@ -56,7 +86,7 @@ static void print_flat_cluster(FILE* fp, void write_flat_placement(const char* flat_place_file_path, const ClusteredNetlist& cluster_netlist, - const vtr::vector_map &block_locs, + const vtr::vector_map& block_locs, const vtr::vector>& atoms_lookup) { // Writes the flat placement to the given flat_place_file_path. @@ -67,6 +97,9 @@ void write_flat_placement(const char* flat_place_file_path, // Create a file in write mode for the flat placement. FILE* fp = fopen(flat_place_file_path, "w"); + // Add a header to the flat placement file. + print_flat_placement_file_header(fp); + // For each cluster, write out the atoms in the cluster at this cluster's // location. for (ClusterBlockId iblk : cluster_netlist.blocks()) { @@ -77,6 +110,86 @@ void write_flat_placement(const char* flat_place_file_path, fclose(fp); } +FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_path, + const AtomNetlist& atom_netlist) { + // Try to open the file, crash if we cannot open the file. + std::ifstream flat_place_file(read_flat_place_file_path); + if (!flat_place_file.is_open()) { + VPR_ERROR(VPR_ERROR_OTHER, "Unable to open flat placement file: %s\n", + read_flat_place_file_path.c_str()); + } + + // Create a FlatPlacementInfo object to hold the flat placement. + FlatPlacementInfo flat_placement_info(atom_netlist); + + // Read each line of the flat placement file. + unsigned line_num = 0; + std::string line; + while (std::getline(flat_place_file, line)) { + // Split the line into tokens (using spaces, tabs, etc. as delimiters). + std::vector tokens = vtr::split(line); + // Skip empty lines + if (tokens.empty()) + continue; + // Skip lines that are only comments. + if (tokens[0][0] == '#') + continue; + // Skip lines with too few arguments. + // Required arguments: + // - Atom name + // - Atom x-pos + // - Atom y-pos + // - Atom layer + // - Atom sub-tile + if (tokens.size() < 5) { + VTR_LOG_WARN("Flat placement file, line %d has too few arguments. " + "Requires at least: \n", + line_num); + continue; + } + + // Get the atom name, which should be the first argument. + AtomBlockId atom_blk_id = atom_netlist.find_block(tokens[0]); + if (!atom_blk_id.is_valid()) { + VTR_LOG_WARN("Flat placement file, line %d atom name does not match " + "any atoms in the atom netlist.\n", + line_num); + continue; + } + + // Check if this atom already has a flat placement + // Using the x_pos and y_pos as identifiers. + if (flat_placement_info.blk_x_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS + || flat_placement_info.blk_y_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS) { + VTR_LOG_WARN("Flat placement file, line %d, atom %s has multiple " + "placement definitions in the flat placement file.\n", + line_num, atom_netlist.block_name(atom_blk_id).c_str()); + continue; + } + + // Get the (x, y, layer) position of the atom. These functions have + // error checking built in. We parse these as floats to allow for + // reading in more global atom positions. + flat_placement_info.blk_x_pos[atom_blk_id] = vtr::atof(tokens[1]); + flat_placement_info.blk_y_pos[atom_blk_id] = vtr::atof(tokens[2]); + flat_placement_info.blk_layer[atom_blk_id] = vtr::atof(tokens[3]); + + // Parse the sub-tile as an integer. + flat_placement_info.blk_sub_tile[atom_blk_id] = vtr::atoi(tokens[4]); + + // If a site index is given, parse the site index as an integer. + if (tokens.size() >= 6 && tokens[5][0] != '#') + flat_placement_info.blk_site_idx[atom_blk_id] = vtr::atoi(tokens[5]); + + // Ignore any further tokens. + + line_num++; + } + + // Return the flat placement info loaded from the file. + return flat_placement_info; +} + /* ingests and legalizes a flat placement file */ bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { VTR_LOG("load_flat_placement(); when implemented, this function:"); @@ -88,3 +201,121 @@ bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { return false; } +void log_flat_placement_reconstruction_info( + const FlatPlacementInfo& flat_placement_info, + const vtr::vector_map& block_locs, + const vtr::vector>& atoms_lookup, + const AtomLookup& cluster_of_atom_lookup, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist) { + // Go through each cluster and see how many clusters have atoms that + // do not belong (cluster is imperfect). + unsigned num_imperfect_clusters = 0; + for (ClusterBlockId clb_blk_id : clustered_netlist.blocks()) { + // Get the centroid of the cluster + const auto& clb_atoms = atoms_lookup[clb_blk_id]; + float centroid_x = 0.f; + float centroid_y = 0.f; + float centroid_layer = 0.f; + float centroid_sub_tile = 0.f; + for (AtomBlockId atom_blk_id : clb_atoms) { + // TODO: Currently only handle the case when all of the position + // data is provided. This can be extended, + VTR_ASSERT(flat_placement_info.blk_x_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_y_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_layer[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_sub_tile[atom_blk_id] != FlatPlacementInfo::UNDEFINED_SUB_TILE); + + centroid_x += flat_placement_info.blk_x_pos[atom_blk_id]; + centroid_y += flat_placement_info.blk_y_pos[atom_blk_id]; + centroid_layer += flat_placement_info.blk_layer[atom_blk_id]; + centroid_sub_tile += flat_placement_info.blk_sub_tile[atom_blk_id]; + } + centroid_x /= static_cast(clb_atoms.size()); + centroid_y /= static_cast(clb_atoms.size()); + centroid_layer /= static_cast(clb_atoms.size()); + centroid_sub_tile /= static_cast(clb_atoms.size()); + // Check if every atom in the cluster is within 0.5 units of the + // centroid. + for (AtomBlockId atom_blk_id : clb_atoms) { + // If the atom's flat placement more than half a block in any + // direction from the flat placement centroid, then it does not + // want to be in this cluster. + // FIXME: This should take into account large blocks somehow, just + // being 0.5 tiles away may not be sufficient. + if (std::abs(centroid_x - flat_placement_info.blk_x_pos[atom_blk_id]) > 0.5f || std::abs(centroid_y - flat_placement_info.blk_y_pos[atom_blk_id]) > 0.5f || std::abs(centroid_layer - flat_placement_info.blk_layer[atom_blk_id]) > 0.5f || std::abs(centroid_sub_tile - flat_placement_info.blk_sub_tile[atom_blk_id]) > 0.5f) { + num_imperfect_clusters++; + break; + } + } + } + // Go through each atom and compute how much it has displaced and count + // how many have been displaced beyond some threshold. + constexpr float disp_threashold = 0.5f; + float total_disp = 0.f; + float max_disp = 0.f; + unsigned num_atoms_missplaced = 0; + for (AtomBlockId atom_blk_id : atom_netlist.blocks()) { + // TODO: Currently only handle the case when all of the position + // data is provided. This can be extended, + VTR_ASSERT(flat_placement_info.blk_x_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_y_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_layer[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS); + VTR_ASSERT(flat_placement_info.blk_sub_tile[atom_blk_id] != FlatPlacementInfo::UNDEFINED_SUB_TILE); + + // Get the (x, y, layer) position of the block. + int blk_x = flat_placement_info.blk_x_pos[atom_blk_id]; + int blk_y = flat_placement_info.blk_y_pos[atom_blk_id]; + int blk_layer = flat_placement_info.blk_layer[atom_blk_id]; + + // Get the (x, y, layer) position of the cluster that contains this block. + ClusterBlockId atom_clb_id = cluster_of_atom_lookup.atom_clb(atom_blk_id); + const t_block_loc& clb_loc = block_locs[atom_clb_id]; + + // Compute the distance between these two positions. + // FIXME: This will overreport large blocks. This should really be + // the distance outside of the tile you want to be placed in. + float dx = blk_x - clb_loc.loc.x; + float dy = blk_y - clb_loc.loc.y; + float dlayer = blk_layer - clb_loc.loc.layer; + // Using the Manhattan distance (L1 norm) + float dist = std::abs(dx) + std::abs(dy) + std::abs(dlayer); + + // Collect the max displacement. + max_disp = std::max(max_disp, dist); + + // Accumulate into the total displacement. + total_disp += dist; + + // Check if this block has been displaced beyond the threshold. + if (dist >= disp_threashold) { + num_atoms_missplaced++; + } + + // TODO: Make this debug option of higher verbosity. Helpful for + // debugging flat placement reconstruction. + /* + * VTR_LOG("%s %d %d %d %d\n", + * g_vpr_ctx.atom().netlist().block_name(atom_blk_id).c_str(), + * clb_loc.loc.x, + * clb_loc.loc.y, + * clb_loc.loc.layer, + * clb_loc.loc.sub_tile); + */ + } + + // Log the flat placement reconstruction info. + size_t num_atoms = atom_netlist.blocks().size(); + size_t num_clusters = clustered_netlist.blocks().size(); + VTR_LOG("Flat Placement Reconstruction Info:\n"); + VTR_LOG("\tPercent of clusters with reconstruction errors: %f\n", + static_cast(num_imperfect_clusters) / static_cast(num_clusters)); + VTR_LOG("\tTotal displacement of initial placement from flat placement: %f\n", + total_disp); + VTR_LOG("\tAverage atom displacement of initial placement from flat placement: %f\n", + total_disp / static_cast(num_atoms)); + VTR_LOG("\tMax atom displacement of initial placement from flat placement: %f\n", + max_disp); + VTR_LOG("\tPercent of atoms misplaced from the flat placement: %f\n", + static_cast(num_atoms_missplaced) / static_cast(num_atoms)); +} diff --git a/vpr/src/base/load_flat_place.h b/vpr/src/base/load_flat_place.h index c70314bb7fc..3c25780fc57 100644 --- a/vpr/src/base/load_flat_place.h +++ b/vpr/src/base/load_flat_place.h @@ -10,14 +10,19 @@ #pragma once +#include #include #include "vtr_vector_map.h" #include "vtr_vector.h" // Forward declarations class AtomBlockId; +class AtomLookup; +class AtomNetlist; class ClusterBlockId; class ClusteredNetlist; +class FlatPlacementInfo; +class Prepacker; struct t_arch; struct t_block_loc; struct t_vpr_setup; @@ -37,11 +42,48 @@ struct t_vpr_setup; */ void write_flat_placement(const char* flat_place_file_path, const ClusteredNetlist& cluster_netlist, - const vtr::vector_map &block_locs, + const vtr::vector_map& block_locs, const vtr::vector>& atoms_lookup); +/** + * @brief Reads a flat placement file generated from a previous run of VTR or + * externally generated. + * + * @param read_flat_place_file_path + * Path to the file to read the flat placement from. + * @param atom_netlist + * The netlist of atom blocks in the circuit. + */ +FlatPlacementInfo read_flat_placement(const std::string& read_flat_place_file_path, + const AtomNetlist& atom_netlist); + /** * @brief A function that loads and legalizes a flat placement file */ bool load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch); +/** + * @brief Logs information on the quality of the clustering and placement + * reconstruction of the given flat placement. + * + * @param flat_placement_info + * The flat placement to log, + * @param block_locs + * The location of each cluster in the netlist. + * @param atoms_lookup + * A lookup between each cluster and the atoms it contains. + * @param cluster_of_atom_lookup + * A lookup between each atom and the cluster that contains it. + * @param atom_netlist + * The netlist of atoms the flat placement was over. + * @param clustered_netlist + * The clustered netlist that the flat placement was used to + * generate. + */ +void log_flat_placement_reconstruction_info( + const FlatPlacementInfo& flat_placement_info, + const vtr::vector_map& block_locs, + const vtr::vector>& atoms_lookup, + const AtomLookup& cluster_of_atom_lookup, + const AtomNetlist& atom_netlist, + const ClusteredNetlist& clustered_netlist); diff --git a/vpr/src/base/netlist_walker.cpp b/vpr/src/base/netlist_walker.cpp index 270a7b6745a..3411210f3cb 100644 --- a/vpr/src/base/netlist_walker.cpp +++ b/vpr/src/base/netlist_walker.cpp @@ -6,7 +6,7 @@ void NetlistWalker::walk() { auto& atom_ctx = g_vpr_ctx.atom(); auto& cluster_ctx = g_vpr_ctx.clustering(); - visitor_.visit_top(atom_ctx.nlist.netlist_name().c_str()); + visitor_.visit_top(atom_ctx.netlist().netlist_name().c_str()); for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { const auto* pb = cluster_ctx.clb_nlist.block_pb(blk_id); diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index d8efdab5b42..53e79a871d9 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -1,36 +1,3 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "vtr_util.h" -#include "vtr_log.h" -#include "vtr_logic.h" -#include "vtr_version.h" - -#include "vpr_error.h" -#include "vpr_types.h" - -#include "read_blif.h" - -#include "netlist_walker.h" -#include "netlist_writer.h" - -#include "globals.h" -#include "atom_netlist.h" -#include "atom_netlist_utils.h" -#include "logic_vec.h" - /** * @file * @@ -89,17 +56,103 @@ * simulation. */ +#include "netlist_writer.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "atom_netlist.h" +#include "atom_netlist_utils.h" +#include "globals.h" +#include "logic_vec.h" +#include "netlist_walker.h" +#include "read_blif.h" +#include "tatum/TimingGraph.hpp" +#include "tatum/TimingGraphFwd.hpp" +#include "vpr_error.h" +#include "vpr_types.h" +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_logic.h" +#include "vtr_version.h" + /* Enable for extra output while calculating LUT masks */ //#define DEBUG_LUT_MASK +namespace { + // //File local type declarations // +/** + * @brief A triple of delay values (all delays should be in seconds). + * + * For delay values in SDF files, three numbers are specified to describe the + * minimum, typical, and maximum delays along a timing edge. + */ +struct DelayTriple { + DelayTriple() = default; + constexpr DelayTriple(double minimum_sec, double typical_sec, double maximum_sec) + : minimum(minimum_sec) + , typical(typical_sec) + , maximum(maximum_sec) {} + + /// @brief The minimum delay along a timing edge. + double minimum = std::numeric_limits::quiet_NaN(); + /// @brief The typical delay along a timing edge. + double typical = std::numeric_limits::quiet_NaN(); + /// @brief The maximum delay along a timing edge. + double maximum = std::numeric_limits::quiet_NaN(); + + /** + * @brief Returns true if the minimum, typical, and maximum delay values have + * been assigned a number. + * + * These values are defaulted to NaN, so this checks if the values have changed. + */ + inline bool has_value() const { + return !std::isnan(minimum) && !std::isnan(typical) && !std::isnan(maximum); + } + + /** + * @brief Convert the triple into a string. This string will be of the form: + * (minimum:typical:maximum) + * + * This string is expected to be written directly into an SDF file. + * + * Since the delays stored in this struct are implied to be in seconds, this + * print method converts the output into picoseconds. + */ + inline std::string str() const { + VTR_ASSERT_MSG(has_value(), + "Cannot create a non-initialized delay triple string"); + + // Convert the delays to picoseconds for printing. + double minimum_ps = minimum * 1e12; + double typical_ps = typical * 1e12; + double maximum_ps = maximum * 1e12; + + // Create the string. + std::stringstream delay_ss; + delay_ss << '(' << minimum_ps << ':' << typical_ps << ':' << maximum_ps << ')'; + return delay_ss.str(); + } +}; + // This pair cointains the following values: // - double: hold, setup or clock-to-q delays of the port // - string: port name of the associated source clock pin of the sequential port -typedef std::pair sequential_port_delay_pair; +typedef std::pair sequential_port_delay_pair; /*enum class PortType { * IN, @@ -110,8 +163,21 @@ typedef std::pair sequential_port_delay_pair; // // File local function declarations // + +/** + * @brief Get the tco delay triple for the given pb_graph pin. + */ +DelayTriple get_pin_tco_delay_triple(const t_pb_graph_pin& pin); + +/** + * @brief Get the edge delay triple for the given edge, as found in the given + * timing graph. + */ +DelayTriple get_edge_delay_triple(tatum::EdgeId edge_id, + const AnalysisDelayCalculator& delay_calc, + const tatum::TimingGraph& timing_graph); + std::string indent(size_t depth); -double get_delay_ps(double delay_sec); void print_blif_port(std::ostream& os, size_t& unconn_count, const std::string& port_name, const std::vector& nets, int depth); void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::string& port_name, const std::vector& nets, PortType type, int depth, struct t_analysis_opts& opts); @@ -138,7 +204,7 @@ class Arc { int src_ipin, /// port_conns, ///::quiet_NaN(), ///::quiet_NaN(), ///::quiet_NaN()) /// port_conns, /// port_connections_; Type type_; vtr::LogicValue initial_value_; - double tcq_; ///pin_count_in_cluster; - tatum::NodeId tnode_id = atom_ctx.lookup.atom_pin_tnode(pin); + tatum::NodeId tnode_id = atom_ctx.lookup().atom_pin_tnode(pin); auto key = std::make_pair(clb_idx, pb_pin_idx); auto value = std::make_pair(key, tnode_id); @@ -859,11 +892,11 @@ class NetlistWriterVisitor : public NetlistVisitor { void visit_atom_impl(const t_pb* atom) override { auto& atom_ctx = g_vpr_ctx.atom(); - auto atom_pb = atom_ctx.lookup.pb_atom(atom); + auto atom_pb = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_pb == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.nlist.block_model(atom_pb); + const t_model* model = atom_ctx.netlist().block_model(atom_pb); if (model->name == std::string(MODEL_INPUT)) { inputs_.emplace_back(make_io(atom, PortType::INPUT)); @@ -1072,10 +1105,7 @@ class NetlistWriterVisitor : public NetlistVisitor { sdf_os_ << indent(depth + 2) << "(DELAY\n"; sdf_os_ << indent(depth + 3) << "(ABSOLUTE\n"; - double delay = get_delay_ps(driver_tnode, sink_tnode); - - std::stringstream delay_triple; - delay_triple << "(" << delay << ":" << delay << ":" << delay << ")"; + DelayTriple delay_triple = get_src_to_sink_delay_triple(driver_tnode, sink_tnode); sdf_os_ << indent(depth + 4) << "(IOPATH datain dataout " << delay_triple.str() << " " << delay_triple.str() << ")\n"; sdf_os_ << indent(depth + 3) << ")\n"; @@ -1234,9 +1264,9 @@ class NetlistWriterVisitor : public NetlistVisitor { net = make_inst_wire(atom_net_id, src_tnode_id, inst_name, PortType::INPUT, 0, pin_idx); //Record the timing arc - float delay = get_delay_ps(src_tnode_id, sink_tnode_id); + DelayTriple delay_triple = get_src_to_sink_delay_triple(src_tnode_id, sink_tnode_id); - Arc timing_arc("in", pin_idx, "out", 0, delay); + Arc timing_arc("in", pin_idx, "out", 0, delay_triple); timing_arcs.push_back(timing_arc); } @@ -1293,6 +1323,7 @@ class NetlistWriterVisitor : public NetlistVisitor { port_conns["D"] = input_net; double tsu = pb_graph_node->input_pins[0][0].tsu; + DelayTriple tsu_triple(tsu, tsu, tsu); //Output (Q) int output_cluster_pin_idx = pb_graph_node->output_pins[0][0].pin_count_in_cluster; //Unique pin index in cluster @@ -1301,7 +1332,7 @@ class NetlistWriterVisitor : public NetlistVisitor { std::string output_net = make_inst_wire(output_atom_net_id, find_tnode(atom, output_cluster_pin_idx), inst_name, PortType::OUTPUT, 0, 0); port_conns["Q"] = output_net; - double tcq = pb_graph_node->output_pins[0][0].tco_max; + DelayTriple tcq_triple = get_pin_tco_delay_triple(pb_graph_node->output_pins[0][0]); //Clock (control) int control_cluster_pin_idx = pb_graph_node->clock_pins[0][0].pin_count_in_cluster; //Unique pin index in cluster @@ -1315,7 +1346,7 @@ class NetlistWriterVisitor : public NetlistVisitor { LatchInst::Type type = LatchInst::Type::RISING_EDGE; vtr::LogicValue init_value = vtr::LogicValue::FALSE; - return std::make_shared(inst_name, port_conns, type, init_value, tcq, tsu); + return std::make_shared(inst_name, port_conns, type, init_value, tcq_triple, tsu_triple); } /** @@ -1395,7 +1426,8 @@ class NetlistWriterVisitor : public NetlistVisitor { } input_port_conns[port_name].push_back(net); - ports_tsu[port_name] = std::make_pair(pin->tsu, pin->associated_clock_pin->port->name); + DelayTriple delay_triple(pin->tsu, pin->tsu, pin->tsu); + ports_tsu[port_name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); } } @@ -1431,7 +1463,8 @@ class NetlistWriterVisitor : public NetlistVisitor { "Unrecognized input port class '%s' for primitive '%s' (%s)\n", port_class.c_str(), atom->name, pb_type->name); } output_port_conns[port_name].push_back(net); - ports_tcq[port_name] = std::make_pair(pin->tco_max, pin->associated_clock_pin->port->name); + DelayTriple delay_triple = get_pin_tco_delay_triple(*pin); + ports_tcq[port_name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); } } @@ -1487,7 +1520,7 @@ class NetlistWriterVisitor : public NetlistVisitor { params["WIDTH"] = "0"; //Delay matrix[sink_tnode] -> tuple of source_port_name, pin index, delay - std::map>> tnode_delay_matrix; + std::map>> tnode_delay_matrix; //Process the input ports for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { @@ -1511,12 +1544,11 @@ class NetlistWriterVisitor : public NetlistVisitor { //Delays // - //We record the souce sink tnodes and thier delays here + //We record the source sink tnodes and their delays here for (tatum::EdgeId edge : timing_ctx.graph->node_out_edges(src_tnode)) { - double delay = delay_calc_->max_edge_delay(*timing_ctx.graph, edge); - + DelayTriple delay_triple = get_edge_delay_triple(edge, *delay_calc_, *timing_ctx.graph); auto sink_tnode = timing_ctx.graph->edge_sink_node(edge); - tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay); + tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay_triple); } } @@ -1547,8 +1579,8 @@ class NetlistWriterVisitor : public NetlistVisitor { for (auto& data_tuple : tnode_delay_matrix[inode]) { auto src_name = std::get<0>(data_tuple); auto src_ipin = std::get<1>(data_tuple); - auto delay = std::get<2>(data_tuple); - timing_arcs.emplace_back(src_name, src_ipin, port->name, ipin, delay); + auto delay_triple = std::get<2>(data_tuple); + timing_arcs.emplace_back(src_name, src_ipin, port->name, ipin, delay_triple); } } @@ -1583,7 +1615,7 @@ class NetlistWriterVisitor : public NetlistVisitor { params["WIDTH"] = "0"; //Delay matrix[sink_tnode] -> tuple of source_port_name, pin index, delay - std::map>> tnode_delay_matrix; + std::map>> tnode_delay_matrix; //Process the input ports for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { @@ -1614,10 +1646,9 @@ class NetlistWriterVisitor : public NetlistVisitor { // //We record the souce sink tnodes and thier delays here for (tatum::EdgeId edge : timing_ctx.graph->node_out_edges(src_tnode)) { - double delay = delay_calc_->max_edge_delay(*timing_ctx.graph, edge); - + DelayTriple delay_triple = get_edge_delay_triple(edge, *delay_calc_, *timing_ctx.graph); auto sink_tnode = timing_ctx.graph->edge_sink_node(edge); - tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay); + tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay_triple); } } @@ -1687,7 +1718,7 @@ class NetlistWriterVisitor : public NetlistVisitor { std::map ports_tcq; //Delay matrix[sink_tnode] -> tuple of source_port_name, pin index, delay - std::map>> tnode_delay_matrix; + std::map>> tnode_delay_matrix; //Process the input ports for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { @@ -1713,17 +1744,22 @@ class NetlistWriterVisitor : public NetlistVisitor { // //We record the source's sink tnodes and their delays here for (tatum::EdgeId edge : timing_ctx.graph->node_out_edges(src_tnode)) { - double delay = delay_calc_->max_edge_delay(*timing_ctx.graph, edge); - + DelayTriple delay_triple = get_edge_delay_triple(edge, *delay_calc_, *timing_ctx.graph); auto sink_tnode = timing_ctx.graph->edge_sink_node(edge); - tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay); + tnode_delay_matrix[sink_tnode].emplace_back(port->name, ipin, delay_triple); } } input_port_conns[port->name].push_back(net); if (pin->type == PB_PIN_SEQUENTIAL) { - if (!std::isnan(pin->tsu)) ports_tsu[port->name] = std::make_pair(pin->tsu, pin->associated_clock_pin->port->name); - if (!std::isnan(pin->thld)) ports_thld[port->name] = std::make_pair(pin->thld, pin->associated_clock_pin->port->name); + if (!std::isnan(pin->tsu)) { + DelayTriple delay_triple(pin->tsu, pin->tsu, pin->tsu); + ports_tsu[port->name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); + } + if (!std::isnan(pin->thld)) { + DelayTriple delay_triple(pin->thld, pin->thld, pin->thld); + ports_thld[port->name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); + } } } } @@ -1757,7 +1793,10 @@ class NetlistWriterVisitor : public NetlistVisitor { } output_port_conns[port->name].push_back(net); - if (pin->type == PB_PIN_SEQUENTIAL && !std::isnan(pin->tco_max)) ports_tcq[port->name] = std::make_pair(pin->tco_max, pin->associated_clock_pin->port->name); + if (pin->type == PB_PIN_SEQUENTIAL && !std::isnan(pin->tco_max)) { + DelayTriple delay_triple = get_pin_tco_delay_triple(*pin); + ports_tcq[port->name] = std::make_pair(delay_triple, pin->associated_clock_pin->port->name); + } } } @@ -1787,12 +1826,12 @@ class NetlistWriterVisitor : public NetlistVisitor { } auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(atom); - for (auto param : atom_ctx.nlist.block_params(blk_id)) { + AtomBlockId blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); + for (auto param : atom_ctx.netlist().block_params(blk_id)) { params[param.first] = param.second; } - for (auto attr : atom_ctx.nlist.block_attrs(blk_id)) { + for (auto attr : atom_ctx.netlist().block_attrs(blk_id)) { attrs[attr.first] = attr.second; } @@ -1809,8 +1848,8 @@ class NetlistWriterVisitor : public NetlistVisitor { tatum::NodeId find_tnode(const t_pb* atom, int cluster_pin_idx) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(atom); - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(blk_id); + AtomBlockId blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(blk_id); auto key = std::make_pair(clb_index, cluster_pin_idx); auto iter = pin_id_to_tnode_lookup_.find(key); @@ -1840,7 +1879,7 @@ class NetlistWriterVisitor : public NetlistVisitor { const t_pb* atom) { //LUT primitive auto& atom_ctx = g_vpr_ctx.atom(); - const t_model* model = atom_ctx.nlist.block_model(atom_ctx.lookup.pb_atom(atom)); + const t_model* model = atom_ctx.netlist().block_model(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom)); VTR_ASSERT(model->name == std::string(MODEL_NAMES)); #ifdef DEBUG_LUT_MASK @@ -1851,7 +1890,7 @@ class NetlistWriterVisitor : public NetlistVisitor { std::vector permute = determine_lut_permutation(num_inputs, atom); //Retrieve the truth table - const auto& truth_table = atom_ctx.nlist.block_truth_table(atom_ctx.lookup.pb_atom(atom)); + const auto& truth_table = atom_ctx.netlist().block_truth_table(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom)); //Apply the permutation auto permuted_truth_table = permute_truth_table(truth_table, num_inputs, permute); @@ -1896,7 +1935,7 @@ class NetlistWriterVisitor : public NetlistVisitor { // //We walk through the logical inputs to this atom (i.e. in the original truth table/netlist) //and find the corresponding input in the implementation atom (i.e. in the current netlist) - auto ports = atom_ctx.nlist.block_input_ports(atom_ctx.lookup.pb_atom(atom_pb)); + auto ports = atom_ctx.netlist().block_input_ports(atom_ctx.lookup().atom_pb_bimap().pb_atom(atom_pb)); if (ports.size() == 1) { const t_pb_graph_node* gnode = atom_pb->pb_graph_node; VTR_ASSERT(gnode->num_input_ports == 1); @@ -1913,16 +1952,16 @@ class NetlistWriterVisitor : public NetlistVisitor { if (impl_input_net_id) { //If there is a valid net connected in the implementation - AtomNetId logical_net_id = atom_ctx.nlist.port_net(port_id, orig_index); + AtomNetId logical_net_id = atom_ctx.netlist().port_net(port_id, orig_index); // Fatal error should be flagged when the net marked in implementation // does not match the net marked in input netlist if (impl_input_net_id != logical_net_id) { VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER, "Unmatch:\n\tlogical net is '%s' at pin '%lu'\n\timplmented net is '%s' at pin '%s'\n", - atom_ctx.nlist.net_name(logical_net_id).c_str(), + atom_ctx.netlist().net_name(logical_net_id).c_str(), size_t(orig_index), - atom_ctx.nlist.net_name(impl_input_net_id).c_str(), + atom_ctx.netlist().net_name(impl_input_net_id).c_str(), gpin->to_string().c_str()); } @@ -2080,16 +2119,14 @@ class NetlistWriterVisitor : public NetlistVisitor { return name; } - ///@brief Returns the delay in pico-seconds from source_tnode to sink_tnode - double get_delay_ps(tatum::NodeId source_tnode, tatum::NodeId sink_tnode) { + ///@brief Returns the delay triple from source_tnode to sink_tnode + DelayTriple get_src_to_sink_delay_triple(tatum::NodeId source_tnode, tatum::NodeId sink_tnode) { auto& timing_ctx = g_vpr_ctx.timing(); tatum::EdgeId edge = timing_ctx.graph->find_edge(source_tnode, sink_tnode); VTR_ASSERT(edge); - double delay_sec = delay_calc_->max_edge_delay(*timing_ctx.graph, edge); - - return ::get_delay_ps(delay_sec); //Class overload hides file-scope by default + return get_edge_delay_triple(edge, *delay_calc_, *timing_ctx.graph); } private: //Data @@ -2144,11 +2181,11 @@ class MergedNetlistWriterVisitor : public NetlistWriterVisitor { void visit_atom_impl(const t_pb* atom) override { auto& atom_ctx = g_vpr_ctx.atom(); - auto atom_pb = atom_ctx.lookup.pb_atom(atom); + auto atom_pb = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom); if (atom_pb == AtomBlockId::INVALID()) { return; } - const t_model* model = atom_ctx.nlist.block_model(atom_pb); + const t_model* model = atom_ctx.netlist().block_model(atom_pb); if (model->name == std::string(MODEL_INPUT)) { auto merged_io_name = make_io(atom, PortType::INPUT); @@ -2307,50 +2344,33 @@ class MergedNetlistWriterVisitor : public NetlistWriterVisitor { }; // -// Externally Accessible Functions +// File-scope function implementations // -///@brief Main routine for this file. See netlist_writer.h for details. -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { - std::string verilog_filename = basename + "_post_synthesis.v"; - std::string blif_filename = basename + "_post_synthesis.blif"; - std::string sdf_filename = basename + "_post_synthesis.sdf"; - - VTR_LOG("Writing Implementation Netlist: %s\n", verilog_filename.c_str()); - VTR_LOG("Writing Implementation Netlist: %s\n", blif_filename.c_str()); - VTR_LOG("Writing Implementation SDF : %s\n", sdf_filename.c_str()); - - std::ofstream verilog_os(verilog_filename); - std::ofstream blif_os(blif_filename); - std::ofstream sdf_os(sdf_filename); - - NetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts); - - NetlistWalker nl_walker(visitor); - - nl_walker.walk(); +DelayTriple get_pin_tco_delay_triple(const t_pb_graph_pin& pin) { + DelayTriple delay_triple; + delay_triple.minimum = pin.tco_min; + delay_triple.maximum = pin.tco_max; + // Since Tatum does not provide typical delays, set it to be the average + // of min and max. + delay_triple.typical = (pin.tco_min + pin.tco_max) / 2.0; + return delay_triple; } -///@brief Main routine for this file. See netlist_writer.h for details. -void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { - std::string verilog_filename = basename + "_merged_post_implementation.v"; - - VTR_LOG("Writing Implementation Netlist: %s\n", verilog_filename.c_str()); - - std::ofstream verilog_os(verilog_filename); - // Don't write blif and sdf, pass dummy streams - std::ofstream blif_os; - std::ofstream sdf_os; - - MergedNetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts); - - NetlistWalker nl_walker(visitor); - - nl_walker.walk(); +DelayTriple get_edge_delay_triple(tatum::EdgeId edge_id, + const AnalysisDelayCalculator& delay_calc, + const tatum::TimingGraph& timing_graph) { + double min_edge_delay = delay_calc.min_edge_delay(timing_graph, edge_id); + double max_edge_delay = delay_calc.max_edge_delay(timing_graph, edge_id); + + DelayTriple delay_triple; + delay_triple.minimum = min_edge_delay; + delay_triple.maximum = max_edge_delay; + // Since Tatum does not provide typical delays, set it to be the average + // of min and max. + delay_triple.typical = (min_edge_delay + max_edge_delay) / 2.0; + return delay_triple; } -// -// File-scope function implementations -// ///@brief Returns a blank string for indenting the given depth std::string indent(size_t depth) { @@ -2362,11 +2382,6 @@ std::string indent(size_t depth) { return new_indent; } -///@brief Returns the delay in pico-seconds from a floating point delay -double get_delay_ps(double delay_sec) { - return delay_sec * 1e12; //Scale to picoseconds -} - ///@brief Returns the name of a unique unconnected net std::string create_unconn_net(size_t& unconn_count) { //We increment unconn_count by reference so each @@ -2572,3 +2587,48 @@ std::string escape_sdf_identifier(const std::string identifier) { std::string join_identifier(std::string lhs, std::string rhs) { return lhs + '_' + rhs; } + +} // namespace + +// +// Externally Accessible Functions +// + +///@brief Main routine for this file. See netlist_writer.h for details. +void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { + std::string verilog_filename = basename + "_post_synthesis.v"; + std::string blif_filename = basename + "_post_synthesis.blif"; + std::string sdf_filename = basename + "_post_synthesis.sdf"; + + VTR_LOG("Writing Implementation Netlist: %s\n", verilog_filename.c_str()); + VTR_LOG("Writing Implementation Netlist: %s\n", blif_filename.c_str()); + VTR_LOG("Writing Implementation SDF : %s\n", sdf_filename.c_str()); + + std::ofstream verilog_os(verilog_filename); + std::ofstream blif_os(blif_filename); + std::ofstream sdf_os(sdf_filename); + + NetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts); + + NetlistWalker nl_walker(visitor); + + nl_walker.walk(); +} + +///@brief Main routine for this file. See netlist_writer.h for details. +void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts) { + std::string verilog_filename = basename + "_merged_post_implementation.v"; + + VTR_LOG("Writing Merged Implementation Netlist: %s\n", verilog_filename.c_str()); + + std::ofstream verilog_os(verilog_filename); + // Don't write blif and sdf, pass dummy streams + std::ofstream blif_os; + std::ofstream sdf_os; + + MergedNetlistWriterVisitor visitor(verilog_os, blif_os, sdf_os, delay_calc, opts); + + NetlistWalker nl_walker(visitor); + + nl_walker.walk(); +} diff --git a/vpr/src/base/netlist_writer.h b/vpr/src/base/netlist_writer.h index 8a8a19976e1..bb1c0fba202 100644 --- a/vpr/src/base/netlist_writer.h +++ b/vpr/src/base/netlist_writer.h @@ -1,29 +1,29 @@ -#ifndef NETLIST_WRITER_H -#define NETLIST_WRITER_H +#pragma once + #include #include -#include - -#include "vtr_logic.h" - #include "AnalysisDelayCalculator.h" /** * @brief Writes out the post-synthesis implementation netlists in BLIF and Verilog formats, * along with an SDF for delay annotations. * + * Here, post-synthesis implementation netlist is the netlist as it appears after + * routing (i.e. implementation is complete). + * * All written filenames end in {basename}_post_synthesis.{fmt} where {basename} is the * basename argument and {fmt} is the file format (e.g. v, blif, sdf) */ -void netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts); +void netlist_writer(const std::string basename, std::shared_ptr delay_calc, t_analysis_opts opts); /** * @brief Writes out the post implementation netlist in Verilog format. * It has its top module ports merged into multi-bit ones. * + * Here, post-synthesis implementation netlist is the netlist as it appears after + * routing (i.e. implementation is complete). + * * Written filename ends in {basename}_merged_post_implementation.v where {basename} is the * basename argument. */ -void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, struct t_analysis_opts opts); - -#endif +void merged_netlist_writer(const std::string basename, std::shared_ptr delay_calc, t_analysis_opts opts); diff --git a/vpr/src/base/partition_region.cpp b/vpr/src/base/partition_region.cpp index 5014976eec4..068f181b7c2 100644 --- a/vpr/src/base/partition_region.cpp +++ b/vpr/src/base/partition_region.cpp @@ -106,9 +106,9 @@ const PartitionRegion& get_device_partition_region() { VTR_ASSERT_SAFE(device_pr.get_regions().size() == 1); const auto [xmin, ymin, xmax, ymax] = device_pr.get_regions()[0].get_rect().coordinates(); - VTR_ASSERT_SAFE(xmin == 0 && ymin == 0 && xmax == width -1 && ymax == height - 1); + VTR_ASSERT_SAFE(xmin == 0 && ymin == 0 && xmax == width - 1 && ymax == height - 1); const auto [layer_low, layer_high] = device_pr.get_regions()[0].get_layer_range(); VTR_ASSERT_SAFE(layer_low == 0 && layer_high == n_layers - 1); return device_pr; -} \ No newline at end of file +} diff --git a/vpr/src/base/partition_region.h b/vpr/src/base/partition_region.h index 9e46a1a849b..2e9949fceea 100644 --- a/vpr/src/base/partition_region.h +++ b/vpr/src/base/partition_region.h @@ -108,5 +108,4 @@ struct hash { }; } // namespace std - #endif /* PARTITION_REGIONS_H */ diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index 12c4187709e..9fcf2a78ff5 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -1,14 +1,11 @@ -#include #include -#include -#include #include #include #include -#include "vtr_util.h" -#include "vtr_memory.h" +#include "flat_placement_types.h" +#include "place_macro.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -16,7 +13,6 @@ #include "vpr_utils.h" #include "vpr_error.h" #include "globals.h" -#include "atom_netlist.h" #include "place_and_route.h" #include "place.h" #include "read_place.h" @@ -24,25 +20,15 @@ #include "route.h" #include "route_export.h" #include "draw.h" -#include "stats.h" -#include "check_route.h" #include "rr_graph.h" -#include "net_delay.h" -#include "timing_place.h" #include "read_xml_arch_file.h" -#include "echo_files.h" #include "route_common.h" -#include "place_macro.h" -#include "power.h" -#include "place_util.h" #include "RoutingDelayCalculator.h" -#include "timing_info.h" -#include "tatum/echo_writer.hpp" /******************* Subroutines local to this module ************************/ -static int compute_chan_width(int cfactor, t_chan chan_dist, float distance, float separation, t_graph_type graph_directionality); +static int compute_chan_width(int cfactor, t_chan chan_dist, float distance, float separation, e_graph_type graph_directionality); static float comp_width(t_chan* chan, float x, float separation); /************************* Subroutine Definitions ****************************/ @@ -82,8 +68,8 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, int udsd_multiplier; int warnings; - t_graph_type graph_type; - t_graph_type graph_directionality; + e_graph_type graph_type; + e_graph_type graph_directionality; /* We have chosen to pass placer_opts_ref by reference because of its large size. * * However, since the value is mutated later in the function, we declare a * @@ -94,15 +80,15 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, /* Allocate the major routing structures. */ if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - graph_directionality = GRAPH_BIDIR; + graph_type = e_graph_type::GLOBAL; + graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); /* Branch on tileable routing */ if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { - graph_type = GRAPH_UNIDIR_TILEABLE; + graph_type = e_graph_type::UNIDIR_TILEABLE; } - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } VTR_ASSERT(!net_delay.empty()); @@ -193,6 +179,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, det_routing_arch, segment_inf, arch->directs, + FlatPlacementInfo(), // Pass empty flat placement info. /*is_flat=*/false); } success = route(router_net_list, @@ -331,6 +318,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, try_place(placement_net_list, placer_opts, router_opts, analysis_opts, noc_opts, arch->Chans, det_routing_arch, segment_inf, arch->directs, + FlatPlacementInfo(), // Pass empty flat placement info. /*is_flat=*/false); } @@ -419,6 +407,36 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, return (final); } +t_chan_width setup_chan_width(const t_router_opts& router_opts, + t_chan_width_dist chan_width_dist) { + /*we give plenty of tracks, this increases routability for the */ + /*lookup table generation */ + + e_graph_type graph_directionality; + int width_fac; + + if (router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH) { + auto& device_ctx = g_vpr_ctx.device(); + + auto type = find_most_common_tile_type(device_ctx.grid); + + width_fac = 4 * type->num_pins; + /*this is 2x the value that binary search starts */ + /*this should be enough to allow most pins to */ + /*connect to tracks in the architecture */ + } else { + width_fac = router_opts.fixed_channel_width; + } + + if (router_opts.route_type == GLOBAL) { + graph_directionality = e_graph_type::BIDIR; + } else { + graph_directionality = e_graph_type::UNIDIR; + } + + return init_chan(width_fac, chan_width_dist, graph_directionality); +} + /** * @brief Assigns widths to channels (in tracks). * @@ -427,7 +445,9 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, * is used to determine if the channel width should be rounded to an * even number. */ -t_chan_width init_chan(int cfactor, const t_chan_width_dist& chan_width_dist, t_graph_type graph_directionality) { +t_chan_width init_chan(int cfactor, + const t_chan_width_dist& chan_width_dist, + e_graph_type graph_directionality) { auto& device_ctx = g_vpr_ctx.mutable_device(); auto& grid = device_ctx.grid; @@ -499,10 +519,10 @@ t_chan_width init_chan(int cfactor, const t_chan_width_dist& chan_width_dist, t_ * @param separation The distance between two channels in the 0 to 1 coordinate system. * @param graph_directionality The directionality of the graph (unidirectional or bidirectional). */ -static int compute_chan_width(int cfactor, t_chan chan_dist, float distance, float separation, t_graph_type graph_directionality) { +static int compute_chan_width(int cfactor, t_chan chan_dist, float distance, float separation, e_graph_type graph_directionality) { int computed_width; computed_width = (int)floor(cfactor * comp_width(&chan_dist, distance, separation) + 0.5); - if ((GRAPH_BIDIR == graph_directionality) || computed_width % 2 == 0) { + if ((e_graph_type::BIDIR == graph_directionality) || computed_width % 2 == 0) { return computed_width; } else { return computed_width - 1; diff --git a/vpr/src/base/place_and_route.h b/vpr/src/base/place_and_route.h index 6f191c0ff9e..e595a2cdedb 100644 --- a/vpr/src/base/place_and_route.h +++ b/vpr/src/base/place_and_route.h @@ -2,11 +2,9 @@ #define VPR_PLACE_AND_ROUTE_H #define INFINITE -1 -#define NOT_FOUND 0 #define WNEED 1 #define WL 2 -#define PROC_TIME 3 #include "vpr_types.h" #include "timing_info.h" @@ -18,7 +16,6 @@ struct t_fmap_cell { int fc; ///& placement_net_list, const std::shared_ptr& delay_calc, bool is_flat); +t_chan_width setup_chan_width(const t_router_opts& router_opts, + t_chan_width_dist chan_width_dist); + t_chan_width init_chan(int cfactor, const t_chan_width_dist& chan_width_dist, - t_graph_type graph_directionality); + e_graph_type graph_directionality); void post_place_sync(); diff --git a/vpr/src/base/read_interchange_netlist.cpp b/vpr/src/base/read_interchange_netlist.cpp index c29cea8326d..ee59c3a76d2 100644 --- a/vpr/src/base/read_interchange_netlist.cpp +++ b/vpr/src/base/read_interchange_netlist.cpp @@ -13,33 +13,33 @@ #ifdef VTR_ENABLE_CAPNPROTO -# include -# include -# include -# include -# include -# include -# include -# include -# include -# include - -# include "LogicalNetlist.capnp.h" -# include "capnp/serialize.h" -# include "capnp/serialize-packed.h" - -# include "vtr_assert.h" -# include "vtr_hash.h" -# include "vtr_util.h" -# include "vtr_log.h" -# include "vtr_logic.h" -# include "vtr_time.h" -# include "vtr_digest.h" - -# include "vpr_types.h" -# include "vpr_error.h" -# include "globals.h" -# include "arch_types.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "LogicalNetlist.capnp.h" +#include "capnp/serialize.h" +#include "capnp/serialize-packed.h" + +#include "vtr_assert.h" +#include "vtr_hash.h" +#include "vtr_util.h" +#include "vtr_log.h" +#include "vtr_logic.h" +#include "vtr_time.h" +#include "vtr_digest.h" + +#include "vpr_types.h" +#include "vpr_error.h" +#include "globals.h" +#include "arch_types.h" struct NetlistReader { public: diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index 2f0d1ff8716..9c648607cae 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -11,6 +11,7 @@ #include #include +#include "physical_types_util.h" #include "pugixml.hpp" #include "pugixml_loc.hpp" #include "pugixml_util.hpp" @@ -19,7 +20,6 @@ #include "vtr_util.h" #include "vtr_log.h" #include "vtr_digest.h" -#include "vtr_memory.h" #include "vtr_token.h" #include "vpr_types.h" @@ -29,7 +29,6 @@ #include "hash.h" #include "globals.h" #include "atom_netlist.h" -#include "read_xml_util.h" #include "read_netlist.h" #include "pb_type_graph.h" @@ -151,11 +150,11 @@ ClusteredNetlist read_netlist(const char* net_file, //Note that we currently don't require that the atom_netlist_id exists, //to remain compatible with old .net files std::string atom_nl_id = atom_netlist_id.value(); - if (atom_nl_id != atom_ctx.nlist.netlist_id()) { + if (atom_nl_id != atom_ctx.netlist().netlist_id()) { auto msg = vtr::string_fmt( "Netlist was generated from a different atom netlist file" " (loaded atom netlist ID: %s, packed netlist atom netlist ID: %s)", - atom_nl_id.c_str(), atom_ctx.nlist.netlist_id().c_str()); + atom_nl_id.c_str(), atom_ctx.netlist().netlist_id().c_str()); if (verify_file_digests) { vpr_throw(VPR_ERROR_NET_F, netlist_file_name, loc_data.line(top), msg.c_str()); } else { @@ -177,8 +176,8 @@ ClusteredNetlist read_netlist(const char* net_file, /* Parse all CLB blocks and all nets*/ //Reset atom/pb mapping (it is reloaded from the packed netlist file) - for (auto blk_id : atom_ctx.nlist.blocks()) - atom_ctx.lookup.set_atom_pb(blk_id, nullptr); + for (auto blk_id : atom_ctx.netlist().blocks()) + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(blk_id, nullptr); //Count the number of blocks for allocation bcount = pugiutil::count_children(top, "block", loc_data, pugiutil::ReqOpt::OPTIONAL); @@ -194,14 +193,14 @@ ClusteredNetlist read_netlist(const char* net_file, VTR_ASSERT(bcount == i); VTR_ASSERT(clb_nlist.blocks().size() == i); VTR_ASSERT(num_primitives >= 0); - VTR_ASSERT(static_cast(num_primitives) == atom_ctx.nlist.blocks().size()); + VTR_ASSERT(static_cast(num_primitives) == atom_ctx.netlist().blocks().size()); /* Error check */ - for (auto blk_id : atom_ctx.nlist.blocks()) { - if (atom_ctx.lookup.atom_pb(blk_id) == nullptr) { + for (auto blk_id : atom_ctx.netlist().blocks()) { + if (atom_ctx.lookup().atom_pb_bimap().atom_pb(blk_id) == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_NET_F, ".blif file and .net file do not match, .net file missing atom %s.\n", - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str()); } } /* TODO: Add additional check to make sure net connections match */ @@ -217,30 +216,30 @@ ClusteredNetlist read_netlist(const char* net_file, * check_top_IO_matches_IO_blocks(circuit_inputs, circuit_outputs, circuit_clocks, blist, bcount); */ /* load mapping between external nets and all nets */ - for (auto net_id : atom_ctx.nlist.nets()) { - atom_ctx.lookup.remove_atom_net(net_id); + for (auto net_id : atom_ctx.netlist().nets()) { + atom_ctx.mutable_lookup().remove_atom_net(net_id); } //Save the mapping between clb and atom nets for (auto clb_net_id : clb_nlist.nets()) { - AtomNetId net_id = atom_ctx.nlist.find_net(clb_nlist.net_name(clb_net_id)); + AtomNetId net_id = atom_ctx.netlist().find_net(clb_nlist.net_name(clb_net_id)); VTR_ASSERT(net_id); - atom_ctx.lookup.add_atom_clb_net(net_id, clb_net_id); + atom_ctx.mutable_lookup().add_atom_clb_net(net_id, clb_net_id); } // Mark ignored and global atom nets /* We have to make set the following variables after the mapping between cluster nets and atom nets * is created */ - const AtomNetlist atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist atom_nlist = g_vpr_ctx.atom().netlist(); for (auto clb_net : clb_nlist.nets()) { - AtomNetId atom_net = atom_ctx.lookup.atom_net(clb_net); + AtomNetId atom_net = atom_ctx.lookup().atom_net(clb_net); VTR_ASSERT(atom_net != AtomNetId::INVALID()); if (clb_nlist.net_is_global(clb_net)) { - atom_ctx.nlist.set_net_is_global(atom_net, true); + atom_ctx.mutable_netlist().set_net_is_global(atom_net, true); } if (clb_nlist.net_is_ignored(clb_net)) { - atom_ctx.nlist.set_net_is_ignored(atom_net, true); + atom_ctx.mutable_netlist().set_net_is_ignored(atom_net, true); } } @@ -320,7 +319,7 @@ static void processComplexBlock(pugi::xml_node clb_block, } //Parse all pbs and CB internal nets - atom_ctx.lookup.set_atom_pb(AtomBlockId::INVALID(), clb_nlist->block_pb(index)); + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(AtomBlockId::INVALID(), clb_nlist->block_pb(index)); clb_nlist->block_pb(index)->pb_graph_node = clb_nlist->block_type(index)->pb_graph_head; clb_nlist->block_pb(index)->pb_route = alloc_pb_route(clb_nlist->block_pb(index)->pb_graph_node); @@ -466,7 +465,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p if (pb_type->num_modes == 0) { /* A primitive type */ - AtomBlockId blk_id = atom_ctx.nlist.find_block(pb->name); + AtomBlockId blk_id = atom_ctx.netlist().find_block(pb->name); if (!blk_id) { VPR_FATAL_ERROR(VPR_ERROR_NET_F, ".net file and .blif file do not match, encountered unknown primitive %s in .net file.\n", @@ -475,11 +474,11 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p //Update atom netlist mapping VTR_ASSERT(blk_id); - atom_ctx.lookup.set_atom_pb(blk_id, pb); - atom_ctx.lookup.set_atom_clb(blk_id, index); + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(blk_id, pb); + atom_ctx.mutable_lookup().set_atom_clb(blk_id, index); - auto atom_attrs = atom_ctx.nlist.block_attrs(blk_id); - auto atom_params = atom_ctx.nlist.block_params(blk_id); + auto atom_attrs = atom_ctx.netlist().block_attrs(blk_id); + auto atom_params = atom_ctx.netlist().block_params(blk_id); processAttrsParams(attrs, "attribute", atom_attrs, loc_data); processAttrsParams(params, "parameter", atom_params, loc_data); @@ -543,7 +542,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p pb->child_pbs[i][pb_index].name = vtr::strdup(name.value()); /* Parse all pbs and CB internal nets*/ - atom_ctx.lookup.set_atom_pb(AtomBlockId::INVALID(), &pb->child_pbs[i][pb_index]); + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(AtomBlockId::INVALID(), &pb->child_pbs[i][pb_index]); auto mode = child.attribute("mode"); pb->child_pbs[i][pb_index].mode = 0; @@ -565,7 +564,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p } else { /* physical block has no used primitives but it may have used routing */ pb->child_pbs[i][pb_index].name = nullptr; - atom_ctx.lookup.set_atom_pb(AtomBlockId::INVALID(), &pb->child_pbs[i][pb_index]); + atom_ctx.mutable_lookup().mutable_atom_pb_bimap().set_atom_pb(AtomBlockId::INVALID(), &pb->child_pbs[i][pb_index]); auto lookahead1 = pugiutil::get_first_child(child, "outputs", loc_data, pugiutil::OPTIONAL); if (lookahead1) { @@ -705,7 +704,7 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route, if (strcmp(pins[i].c_str(), "open") != 0) { //For connected pins look-up the inter-block net index associated with it - AtomNetId net_id = atom_ctx.nlist.find_net(pins[i].c_str()); + AtomNetId net_id = atom_ctx.netlist().find_net(pins[i].c_str()); if (!net_id) { VPR_FATAL_ERROR(VPR_ERROR_NET_F, ".blif and .net do not match, unknown net %s found in .net file.\n.", @@ -785,7 +784,7 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route, const t_pb_graph_pin* pb_gpin = &pb->pb_graph_node->output_pins[out_port][i]; int rr_node_index = pb_gpin->pin_count_in_cluster; if (strcmp(pins[i].c_str(), "open") != 0) { - AtomNetId net_id = atom_ctx.nlist.find_net(pins[i].c_str()); + AtomNetId net_id = atom_ctx.netlist().find_net(pins[i].c_str()); if (!net_id) { VPR_FATAL_ERROR(VPR_ERROR_NET_F, ".blif and .net do not match, unknown net %s found in .net file.\n", @@ -939,8 +938,8 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { if (pb->pb_route.count(pb_graph_pin->pin_count_in_cluster)) { AtomNetId atom_net_id = pb->pb_route[pb_graph_pin->pin_count_in_cluster].atom_net_id; if (atom_net_id) { - add_net_to_hash(ext_nhash, atom_ctx.nlist.net_name(atom_net_id).c_str(), &ext_ncount); - clb_net_id = clb_nlist.create_net(atom_ctx.nlist.net_name(atom_net_id)); + add_net_to_hash(ext_nhash, atom_ctx.netlist().net_name(atom_net_id).c_str(), &ext_ncount); + clb_net_id = clb_nlist.create_net(atom_ctx.netlist().net_name(atom_net_id)); clb_nlist.create_pin(input_port_id, (BitIndex)k, clb_net_id, PinType::SINK, ipin); } } @@ -958,11 +957,11 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { if (pb->pb_route.count(pb_graph_pin->pin_count_in_cluster)) { AtomNetId atom_net_id = pb->pb_route[pb_graph_pin->pin_count_in_cluster].atom_net_id; if (atom_net_id) { - add_net_to_hash(ext_nhash, atom_ctx.nlist.net_name(atom_net_id).c_str(), &ext_ncount); - clb_net_id = clb_nlist.create_net(atom_ctx.nlist.net_name(atom_net_id)); + add_net_to_hash(ext_nhash, atom_ctx.netlist().net_name(atom_net_id).c_str(), &ext_ncount); + clb_net_id = clb_nlist.create_net(atom_ctx.netlist().net_name(atom_net_id)); - AtomPinId atom_net_driver = atom_ctx.nlist.net_driver(atom_net_id); - bool driver_is_constant = atom_ctx.nlist.pin_is_constant(atom_net_driver); + AtomPinId atom_net_driver = atom_ctx.netlist().net_driver(atom_net_id); + bool driver_is_constant = atom_ctx.netlist().pin_is_constant(atom_net_driver); clb_nlist.create_pin(output_port_id, (BitIndex)k, clb_net_id, PinType::DRIVER, ipin, driver_is_constant); @@ -983,8 +982,8 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { if (pb->pb_route.count(pb_graph_pin->pin_count_in_cluster)) { AtomNetId atom_net_id = pb->pb_route[pb_graph_pin->pin_count_in_cluster].atom_net_id; if (atom_net_id) { - add_net_to_hash(ext_nhash, atom_ctx.nlist.net_name(atom_net_id).c_str(), &ext_ncount); - clb_net_id = clb_nlist.create_net(atom_ctx.nlist.net_name(atom_net_id)); + add_net_to_hash(ext_nhash, atom_ctx.netlist().net_name(atom_net_id).c_str(), &ext_ncount); + clb_net_id = clb_nlist.create_net(atom_ctx.netlist().net_name(atom_net_id)); clb_nlist.create_pin(clock_port_id, (BitIndex)k, clb_net_id, PinType::SINK, ipin); } } @@ -1122,8 +1121,8 @@ static size_t mark_constant_generators_rec(const t_pb* pb, const t_pb_routes& pb if (!pb_route.count(cluster_pin_idx)) continue; if (pb_route[cluster_pin_idx].atom_net_id) { AtomNetId net_id = pb_route[pb->pb_graph_node->output_pins[i][j].pin_count_in_cluster].atom_net_id; - AtomPinId driver_pin_id = atom_ctx.nlist.net_driver(net_id); - VTR_ASSERT(atom_ctx.nlist.pin_is_constant(driver_pin_id)); + AtomPinId driver_pin_id = atom_ctx.netlist().net_driver(net_id); + VTR_ASSERT(atom_ctx.netlist().pin_is_constant(driver_pin_id)); } } } @@ -1180,18 +1179,18 @@ static void load_atom_index_for_pb_pin(t_pb_routes& pb_route, int ipin) { static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { auto& atom_ctx = g_vpr_ctx.atom(); - for (const AtomBlockId blk : atom_ctx.nlist.blocks()) { - const t_pb* pb = atom_ctx.lookup.atom_pb(blk); + for (const AtomBlockId blk : atom_ctx.netlist().blocks()) { + const t_pb* pb = atom_ctx.lookup().atom_pb_bimap().atom_pb(blk); VTR_ASSERT_MSG(pb, "Atom block must have a matching PB"); const t_pb_graph_node* gnode = pb->pb_graph_node; - VTR_ASSERT_MSG(gnode->pb_type->model == atom_ctx.nlist.block_model(blk), + VTR_ASSERT_MSG(gnode->pb_type->model == atom_ctx.netlist().block_model(blk), "Atom block PB must match BLIF model"); for (int iport = 0; iport < gnode->num_input_ports; ++iport) { if (gnode->num_input_pins[iport] <= 0) continue; - const AtomPortId port = atom_ctx.nlist.find_atom_port(blk, gnode->input_pins[iport][0].port->model_port); + const AtomPortId port = atom_ctx.netlist().find_atom_port(blk, gnode->input_pins[iport][0].port->model_port); if (!port) continue; for (int ipin = 0; ipin < gnode->num_input_pins[iport]; ++ipin) { @@ -1205,7 +1204,7 @@ static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { for (int iport = 0; iport < gnode->num_output_ports; ++iport) { if (gnode->num_output_pins[iport] <= 0) continue; - const AtomPortId port = atom_ctx.nlist.find_atom_port(blk, gnode->output_pins[iport][0].port->model_port); + const AtomPortId port = atom_ctx.netlist().find_atom_port(blk, gnode->output_pins[iport][0].port->model_port); if (!port) continue; for (int ipin = 0; ipin < gnode->num_output_pins[iport]; ++ipin) { @@ -1219,7 +1218,7 @@ static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { for (int iport = 0; iport < gnode->num_clock_ports; ++iport) { if (gnode->num_clock_pins[iport] <= 0) continue; - const AtomPortId port = atom_ctx.nlist.find_atom_port(blk, gnode->clock_pins[iport][0].port->model_port); + const AtomPortId port = atom_ctx.netlist().find_atom_port(blk, gnode->clock_pins[iport][0].port->model_port); if (!port) continue; for (int ipin = 0; ipin < gnode->num_clock_pins[iport]; ++ipin) { @@ -1235,9 +1234,9 @@ static void load_atom_pin_mapping(const ClusteredNetlist& clb_nlist) { void set_atom_pin_mapping(const ClusteredNetlist& clb_nlist, const AtomBlockId atom_blk, const AtomPortId atom_port, const t_pb_graph_pin* gpin) { auto& atom_ctx = g_vpr_ctx.mutable_atom(); - VTR_ASSERT(atom_ctx.nlist.port_block(atom_port) == atom_blk); + VTR_ASSERT(atom_ctx.netlist().port_block(atom_port) == atom_blk); - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(atom_blk); + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(atom_blk); VTR_ASSERT(clb_index != ClusterBlockId::INVALID()); const t_pb* clb_pb = clb_nlist.block_pb(clb_index); @@ -1251,17 +1250,17 @@ void set_atom_pin_mapping(const ClusteredNetlist& clb_nlist, const AtomBlockId a return; } - const t_pb* atom_pb = atom_ctx.lookup.atom_pb(atom_blk); + const t_pb* atom_pb = atom_ctx.lookup().atom_pb_bimap().atom_pb(atom_blk); //This finds the index within the atom port to which the current gpin //is mapped. Note that this accounts for any applied pin rotations //(e.g. on LUT inputs) BitIndex atom_pin_bit_index = atom_pb->atom_pin_bit_index(gpin); - AtomPinId atom_pin = atom_ctx.nlist.port_pin(atom_port, atom_pin_bit_index); + AtomPinId atom_pin = atom_ctx.netlist().port_pin(atom_port, atom_pin_bit_index); - VTR_ASSERT(pb_route->atom_net_id == atom_ctx.nlist.pin_net(atom_pin)); + VTR_ASSERT(pb_route->atom_net_id == atom_ctx.netlist().pin_net(atom_pin)); //Save the mapping - atom_ctx.lookup.set_atom_pin_pb_graph_pin(atom_pin, gpin); + atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(atom_pin, gpin); } diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 200b549bfd0..aa6d52eb93e 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -5,9 +5,10 @@ #include "argparse.hpp" +#include "ap_flow_enums.h" #include "vtr_log.h" -#include "vtr_util.h" #include "vtr_path.h" +#include "vtr_util.h" #include using argparse::ConvertedValue; @@ -132,6 +133,151 @@ struct ParseCircuitFormat { return {"auto", "blif", "eblif", "fpga-interchange"}; } }; + +struct ParseAPAnalyticalSolver { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "qp-hybrid") + conv_value.set_value(e_ap_analytical_solver::QP_Hybrid); + else if (str == "lp-b2b") + conv_value.set_value(e_ap_analytical_solver::LP_B2B); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_analytical_solver (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_analytical_solver val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_analytical_solver::QP_Hybrid: + conv_value.set_value("qp-hybrid"); + break; + case e_ap_analytical_solver::LP_B2B: + conv_value.set_value("lp-b2b"); + break; + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"qp-hybrid", "lp-b2b"}; + } +}; + +struct ParseAPPartialLegalizer { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "bipartitioning") + conv_value.set_value(e_ap_partial_legalizer::BiPartitioning); + else if (str == "flow-based") + conv_value.set_value(e_ap_partial_legalizer::FlowBased); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_partial_legalizer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_partial_legalizer val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_partial_legalizer::BiPartitioning: + conv_value.set_value("bipartitioning"); + break; + case e_ap_partial_legalizer::FlowBased: + conv_value.set_value("flow-based"); + break; + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"bipartitioning", "flow-based"}; + } +}; + +struct ParseAPFullLegalizer { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "naive") + conv_value.set_value(e_ap_full_legalizer::Naive); + else if (str == "appack") + conv_value.set_value(e_ap_full_legalizer::APPack); + else if (str == "basic-min-disturbance") + conv_value.set_value(e_ap_full_legalizer::Basic_Min_Disturbance); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_full_legalizer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_full_legalizer val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_full_legalizer::Naive: + conv_value.set_value("naive"); + break; + case e_ap_full_legalizer::APPack: + conv_value.set_value("appack"); + break; + case e_ap_full_legalizer::Basic_Min_Disturbance: + conv_value.set_value("basic-min-disturbance"); + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"naive", "appack", "basic-min-disturbance"}; + } +}; + +struct ParseAPDetailedPlacer { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "none") + conv_value.set_value(e_ap_detailed_placer::Identity); + else if (str == "annealer") + conv_value.set_value(e_ap_detailed_placer::Annealer); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_detailed_placer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_detailed_placer val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_detailed_placer::Identity: + conv_value.set_value("none"); + break; + case e_ap_detailed_placer::Annealer: + conv_value.set_value("annealer"); + break; + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"none", "annealer"}; + } +}; + struct ParseRoutePredictor { ConvertedValue from_str(const std::string& str) { ConvertedValue conv_value; @@ -171,7 +317,9 @@ struct ParseRoutePredictor { struct ParseRouterAlgorithm { ConvertedValue from_str(const std::string& str) { ConvertedValue conv_value; - if (str == "parallel") + if (str == "nested") + conv_value.set_value(NESTED); + else if (str == "parallel") conv_value.set_value(PARALLEL); else if (str == "parallel_decomp") conv_value.set_value(PARALLEL_DECOMP); @@ -187,8 +335,12 @@ struct ParseRouterAlgorithm { ConvertedValue to_str(e_router_algorithm val) { ConvertedValue conv_value; - if (val == PARALLEL) + if (val == NESTED) + conv_value.set_value("nested"); + else if (val == PARALLEL) conv_value.set_value("parallel"); + else if (val == PARALLEL_DECOMP) + conv_value.set_value("parallel_decomp"); else { VTR_ASSERT(val == TIMING_DRIVEN); conv_value.set_value("timing_driven"); @@ -1617,19 +1769,26 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .show_in(argparse::ShowIn::HELP_ONLY); file_grp.add_argument(args.read_rr_graph_file, "--read_rr_graph") - .help( - "The routing resource graph file to load." - " The loaded routing resource graph overrides any routing architecture specified in the architecture file.") + .help("The routing resource graph file to load. " + "The loaded routing resource graph overrides any routing architecture specified in the architecture file.") .metavar("RR_GRAPH_FILE") .show_in(argparse::ShowIn::HELP_ONLY); + file_grp.add_argument(args.read_rr_edge_override_file, "--read_rr_edge_override") + .help("The routing resource edge attributes override file to load. " + "This file overrides edge attributes in the routing resource graph. " + "The user can use the architecture file to specify nominal switch delays, " + "while this file can be used to override the nominal delays to make it more accurate " + "for specific edges.") + .show_in(argparse::ShowIn::HELP_ONLY); + file_grp.add_argument(args.write_rr_graph_file, "--write_rr_graph") - .help("Writes the routing resource graph to the specified file") + .help("Writes the routing resource graph to the specified file.") .metavar("RR_GRAPH_FILE") .show_in(argparse::ShowIn::HELP_ONLY); file_grp.add_argument(args.write_initial_place_file, "--write_initial_place_file") - .help("Writes out the the placement chosen by the initial placement algorithm to the specified file") + .help("Writes out the the placement chosen by the initial placement algorithm to the specified file.") .metavar("INITIAL_PLACE_FILE") .show_in(argparse::ShowIn::HELP_ONLY); @@ -1652,6 +1811,11 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("fix_clusters.out") .show_in(argparse::ShowIn::HELP_ONLY); + file_grp.add_argument(args.read_flat_place_file, "--read_flat_place") + .help( + "Reads VPR's (or reconstructed external) placement solution in flat placement file format; this file lists cluster and intra-cluster placement coordinates for each atom and can be used to reconstruct a clustering and placement solution.") + .show_in(argparse::ShowIn::HELP_ONLY); + file_grp.add_argument(args.write_flat_place_file, "--write_flat_place") .help( "VPR's (or reconstructed external) placement solution in flat placement file format; this file lists cluster and intra-cluster placement coordinates for each atom and can be used to reconstruct a clustering and placement solution.") @@ -1739,6 +1903,56 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("1") .show_in(argparse::ShowIn::HELP_ONLY); + auto& ap_grp = parser.add_argument_group("analytical placement options"); + + ap_grp.add_argument(args.ap_analytical_solver, "--ap_analytical_solver") + .help( + "Controls which Analytical Solver the Global Placer will use in the AP Flow.\n" + " * qp-hybrid: olves for a placement that minimizes the quadratic HPWL of the flat placement using a hybrid clique/star net model.\n" + " * lp-b2b: Solves for a placement that minimizes the linear HPWL of theflat placement using the Bound2Bound net model.") + .default_value("lp-b2b") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_partial_legalizer, "--ap_partial_legalizer") + .help( + "Controls which Partial Legalizer the Global Placer will use in the AP Flow.\n" + " * bipartitioning: Creates minimum windows around over-dense regions of the device bi-partitions the atoms in these windows such that the region is no longer over-dense and the atoms are in tiles that they can be placed into.\n" + " * flow-based: Flows atoms from regions that are overfilled to regions that are underfilled.") + .default_value("bipartitioning") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_full_legalizer, "--ap_full_legalizer") + .help( + "Controls which Full Legalizer to use in the AP Flow.\n" + " * naive: Use a Naive Full Legalizer which will try to create clusters exactly where their atoms are placed.\n" + " * appack: Use APPack, which takes the Packer in VPR and uses the flat atom placement to create better clusters.\n" + " * basic-min-disturbance: Use the Basic Min. Disturbance Full Legalizer which tries to reconstruct a clustered placement that is as close to the incoming flat placement as possible.") + .default_value("appack") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_detailed_placer, "--ap_detailed_placer") + .help( + "Controls which Detailed Placer to use in the AP Flow.\n" + " * none: Do not perform any detailed placement. i.e. the output of the full legalizer will be produced by the AP flow without modification.\n" + " * annealer: Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer.") + .default_value("annealer") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_timing_tradeoff, "--ap_timing_tradeoff") + .help( + "Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow.\n" + "A value of 0.0 makes the AP flow focus completely on wirelength minimization, while a value of 1.0 makes the AP flow focus completely on timing optimization.") + .default_value("0.5") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_verbosity, "--ap_verbosity") + .help( + "Controls how verbose the AP flow's log messages will be. Higher " + "values produce more output (useful for debugging the AP " + "algorithms).") + .default_value("1") + .show_in(argparse::ShowIn::HELP_ONLY); + auto& pack_grp = parser.add_argument_group("packing options"); pack_grp.add_argument(args.connection_driven_clustering, "--connection_driven_clustering") @@ -2043,7 +2257,6 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value({"100"}) .show_in(argparse::ShowIn::HELP_ONLY); - place_grp.add_argument(args.place_high_fanout_net, "--place_high_fanout_net") .help( "Sets the assumed high fanout net during placement. " @@ -2067,7 +2280,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio place_grp.add_argument(args.RL_agent_placement, "--RL_agent_placement") .help( - "Uses a Reinforcement Learning (RL) agent in choosing the appropiate move type in placement." + "Uses a Reinforcement Learning (RL) agent in choosing the appropriate move type in placement." "It activates the RL agent placement instead of using fixed probability for each move type.") .default_value("on") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2082,7 +2295,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio place_grp.add_argument(args.place_checkpointing, "--place_checkpointing") .help( "Enable Placement checkpoints. This means saving the placement and restore it if it's better than later placements." - "Only effective if agnet's 2nd state is activated.") + "Only effective if agent's 2nd state is activated.") .default_value("on") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2096,7 +2309,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio place_grp.add_argument(args.place_agent_gamma, "--place_agent_gamma") .help( "Controls how quickly the agent's memory decays. " - "Values between [0., 1.] specify the fraction of weight in the exponentially weighted reward average applied to moves which occured greater than moves_per_temp moves ago." + "Values between [0., 1.] specify the fraction of weight in the exponentially weighted reward average applied to moves which occurred greater than moves_per_temp moves ago." "Values < 0 cause the unweighted reward sample average to be used (all samples are weighted equally)") .default_value("0.05") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2159,13 +2372,12 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); - /* - * place_grp.add_argument(args.place_timing_cost_func, "--place_timing_cost_func") - * .help( - * "which timing cost function to use") - * .default_value("0") - * .show_in(argparse::ShowIn::HELP_ONLY); - */ + place_grp.add_argument(args.place_quench_only, "--place_quench_only") + .help( + "Skip the placement annealing phase and go straight to the placement quench.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + place_grp.add_argument(args.place_agent_algorithm, "--place_agent_algorithm") .help("Controls which placement RL agent is used") .default_value("softmax") @@ -2219,13 +2431,13 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .show_in(argparse::ShowIn::HELP_ONLY); place_timing_grp.add_argument(args.inner_loop_recompute_divider, "--inner_loop_recompute_divider") - .help("Controls how many timing analysies are perform per temperature during placement") + .help("Controls how many timing analyses are performed per temperature during placement") .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); place_timing_grp.add_argument(args.quench_recompute_divider, "--quench_recompute_divider") .help( - "Controls how many timing analysies are perform during the final placement quench (t=0)." + "Controls how many timing analyses are performed during the final placement quench (t=0)." " If unspecified, uses the value from --inner_loop_recompute_divider") .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2295,7 +2507,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .show_in(argparse::ShowIn::HELP_ONLY); place_timing_grp.add_argument(args.post_place_timing_report_file, "--post_place_timing_report") - .help("Name of the post-placement timing report file (not generated if unspecfied)") + .help("Name of the post-placement timing report file (not generated if unspecified)") .default_value("") .show_in(argparse::ShowIn::HELP_ONLY); @@ -2405,9 +2617,10 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio "Specifies the router algorithm to use.\n" " * timing driven: focuses on routability and circuit speed [default]\n" " * parallel: timing_driven with nets in different regions of the chip routed in parallel\n" - " * parallel_decomp: timing_driven with additional parallelism obtained by decomposing high-fanout nets, possibly reducing quality\n") + " * parallel_decomp: timing_driven with additional parallelism obtained by decomposing high-fanout nets, possibly reducing quality\n" + " * nested: parallel with parallelized path search\n") .default_value("timing_driven") - .choices({"parallel", "parallel_decomp", "timing_driven"}) + .choices({"nested", "parallel", "parallel_decomp", "timing_driven"}) .show_in(argparse::ShowIn::HELP_ONLY); route_grp.add_argument(args.min_incremental_reroute_fanout, "--min_incremental_reroute_fanout") @@ -2460,23 +2673,22 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio route_grp.add_argument(args.router_opt_choke_points, "--router_opt_choke_points") .help( "" - "Some FPGA architectures with limited fan-out options within a cluster (e.g. fracturable LUTs with shared pins) do" - " not converge well in routing unless these fan-out choke points are discovered and optimized for during net routing." + "Some FPGA architectures with limited fan-out options within a cluster (e.g. fracturable LUTs with shared pins) do" + " not converge well in routing unless these fan-out choke points are discovered and optimized for during net routing." " This option helps router convergence for such architectures.") .default_value("on") .show_in(argparse::ShowIn::HELP_ONLY); - route_grp.add_argument(args.route_verbosity, "--route_verbosity") .help("Controls the verbosity of routing's output. Higher values produce more output (useful for debugging routing problems)") .default_value("1") .show_in(argparse::ShowIn::HELP_ONLY); route_grp.add_argument(args.custom_3d_sb_fanin_fanout, "--custom_3d_sb_fanin_fanout") - .help( - "Specifies the number of tracks that can drive a 3D switch block connection" - "and the number of tracks that can be driven by a 3D switch block connection") - .default_value("1") - .show_in(argparse::ShowIn::HELP_ONLY); + .help( + "Specifies the number of tracks that can drive a 3D switch block connection" + "and the number of tracks that can be driven by a 3D switch block connection") + .default_value("1") + .show_in(argparse::ShowIn::HELP_ONLY); auto& route_timing_grp = parser.add_argument_group("timing-driven routing options"); @@ -2893,13 +3105,13 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("0.25") .show_in(argparse::ShowIn::HELP_ONLY); - noc_grp.add_argument(args.noc_centroid_weight, "--noc_centroid_weight") + noc_grp.add_argument(args.noc_centroid_weight, "--noc_centroid_weight") .help( "Sets the minimum fraction of swaps attempted by the placer that are NoC blocks." "This value is an integer ranging from 0-100. 0 means NoC blocks will be moved at the same rate as other blocks. 100 means all swaps attempted by the placer are NoC router blocks.") .default_value("0") .show_in(argparse::ShowIn::HELP_ONLY); - + noc_grp.add_argument(args.noc_swap_percentage, "--noc_swap_percentage") .help( "Sets the minimum fraction of swaps attempted by the placer that are NoC blocks. " @@ -2952,7 +3164,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio server_grp.add_argument(args.is_server_mode_enabled, "--server") .help("Run in server mode." - "Accept client application connection and respond to requests." ) + "Accept client application connection and respond to requests.") .action(argparse::Action::STORE_TRUE) .default_value("off"); @@ -3157,7 +3369,7 @@ void set_conditional_defaults(t_options& args) { bool verify_args(const t_options& args) { /* - * Check for conflicting paramaters or dependencies where one parameter set requires another parameter to be included + * Check for conflicting parameters or dependencies where one parameter set requires another parameter to be included */ if (args.read_rr_graph_file.provenance() == Provenance::SPECIFIED && args.RouteChanWidth.provenance() != Provenance::SPECIFIED) { diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 2a9a5a1ce00..42ce1f5c359 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -4,6 +4,7 @@ #include "vpr_types.h" #include "constant_nets.h" +#include "ap_flow_enums.h" #include "argparse_value.hpp" #include "argparse.hpp" @@ -28,11 +29,13 @@ struct t_options { argparse::ArgValue constraints_file; argparse::ArgValue write_rr_graph_file; argparse::ArgValue read_rr_graph_file; + argparse::ArgValue read_rr_edge_override_file; argparse::ArgValue write_initial_place_file; argparse::ArgValue read_initial_place_file; argparse::ArgValue read_vpr_constraints_file; argparse::ArgValue write_vpr_constraints_file; argparse::ArgValue write_constraints_file; + argparse::ArgValue read_flat_place_file; argparse::ArgValue write_flat_place_file; argparse::ArgValue write_placement_delay_lookup; @@ -94,6 +97,14 @@ struct t_options { argparse::ArgValue sweep_constant_primary_outputs; argparse::ArgValue netlist_verbosity; + /* Analytical Placement options */ + argparse::ArgValue ap_analytical_solver; + argparse::ArgValue ap_partial_legalizer; + argparse::ArgValue ap_full_legalizer; + argparse::ArgValue ap_detailed_placer; + argparse::ArgValue ap_verbosity; + argparse::ArgValue ap_timing_tradeoff; + /* Clustering options */ argparse::ArgValue connection_driven_clustering; argparse::ArgValue allow_unrelated_clustering; @@ -148,6 +159,7 @@ struct t_options { argparse::ArgValue place_constraint_subtile; argparse::ArgValue floorplan_num_horizontal_partitions; argparse::ArgValue floorplan_num_vertical_partitions; + argparse::ArgValue place_quench_only; argparse::ArgValue placer_debug_block; argparse::ArgValue placer_debug_net; diff --git a/vpr/src/base/read_place.cpp b/vpr/src/base/read_place.cpp index 5813a780a26..5b07ef33f28 100644 --- a/vpr/src/base/read_place.cpp +++ b/vpr/src/base/read_place.cpp @@ -97,7 +97,7 @@ static void read_place_header(std::ifstream& placement_file, std::streampos file_pos = placement_file.tellg(); while (std::getline(placement_file, line) && (!seen_netlist_id || !seen_grid_dimensions)) { //Parse line-by-line - ++lineno; + ++lineno; std::vector tokens = vtr::split(line); @@ -107,9 +107,7 @@ static void read_place_header(std::ifstream& placement_file, } else if (tokens[0][0] == '#') { continue; //Skip commented lines - } else if (tokens.size() == 4 && - tokens[0] == "Netlist_File:" && - tokens[2] == "Netlist_ID:") { + } else if (tokens.size() == 4 && tokens[0] == "Netlist_File:" && tokens[2] == "Netlist_ID:") { //Check that the netlist used to generate this placement matches the one loaded // //NOTE: this is an optional check which causes no errors if this line is missing. @@ -142,12 +140,12 @@ static void read_place_header(std::ifstream& placement_file, seen_netlist_id = true; - } else if (tokens.size() == 7 && - tokens[0] == "Array" && - tokens[1] == "size:" && - tokens[3] == "x" && - tokens[5] == "logic" && - tokens[6] == "blocks") { + } else if (tokens.size() == 7 + && tokens[0] == "Array" + && tokens[1] == "size:" + && tokens[3] == "x" + && tokens[5] == "logic" + && tokens[6] == "blocks") { //Load the device grid dimensions size_t place_file_width = vtr::atou(tokens[2]); @@ -184,8 +182,8 @@ static void read_place_header(std::ifstream& placement_file, "--verify_file_digests command line option is off."); } - if ((tokens.size() == 4 || (tokens.size() > 4 && tokens[4][0] == '#')) || - (tokens.size() == 5 || (tokens.size() > 5 && tokens[5][0] == '#'))) { + if ((tokens.size() == 4 || (tokens.size() > 4 && tokens[4][0] == '#')) + || (tokens.size() == 5 || (tokens.size() > 5 && tokens[5][0] == '#'))) { placement_file.seekg(file_pos); break; } @@ -236,8 +234,8 @@ static std::string read_place_body(std::ifstream& placement_file, } else if (tokens[0][0] == '#') { continue; //Skip commented lines - } else if ((tokens.size() == 4 || (tokens.size() > 4 && tokens[4][0] == '#')) || - (tokens.size() == 5 || (tokens.size() > 5 && tokens[5][0] == '#'))) { + } else if ((tokens.size() == 4 || (tokens.size() > 4 && tokens[4][0] == '#')) + || (tokens.size() == 5 || (tokens.size() > 5 && tokens[5][0] == '#'))) { //Load the block location // // If the place file corresponds to a 3D architecture, it should contain 5 tokens of actual data, with an optional 6th (commented) token indicating VPR's internal block number. @@ -275,22 +273,22 @@ static std::string read_place_body(std::ifstream& placement_file, //If block name is not found in cluster netlist check if it is in atom netlist if (blk_id == ClusterBlockId::INVALID()) { - AtomBlockId atom_blk_id = atom_ctx.nlist.find_block(block_name); + AtomBlockId atom_blk_id = atom_ctx.netlist().find_block(block_name); if (atom_blk_id == AtomBlockId::INVALID()) { VTR_LOG_WARN("Block %s has an invalid name and it is going to be skipped.\n", c_block_name); continue; } else { - blk_id = atom_ctx.lookup.atom_clb(atom_blk_id); //getting the ClusterBlockId of the cluster that the atom is in + blk_id = atom_ctx.lookup().atom_clb(atom_blk_id); //getting the ClusterBlockId of the cluster that the atom is in } } //Check if block is listed multiple times with conflicting locations in constraints file if (seen_blocks[blk_id] > 0) { - if (block_x != block_locs[blk_id].loc.x || - block_y != block_locs[blk_id].loc.y || - sub_tile_index != block_locs[blk_id].loc.sub_tile || - block_layer != block_locs[blk_id].loc.layer) { + if (block_x != block_locs[blk_id].loc.x + || block_y != block_locs[blk_id].loc.y + || sub_tile_index != block_locs[blk_id].loc.sub_tile + || block_layer != block_locs[blk_id].loc.layer) { std::string cluster_name = cluster_ctx.clb_nlist.block_name(blk_id); VPR_THROW(VPR_ERROR_PLACE, "The location of cluster %s (#%d) is specified %d times in the constraints file with conflicting locations. \n" @@ -310,8 +308,8 @@ static std::string read_place_body(std::ifstream& placement_file, const t_pl_loc& constraint_loc = block_locs[blk_id].loc; if (loc != constraint_loc) { VPR_THROW(VPR_ERROR_PLACE, - "The new location assigned to cluster #%d is (%d,%d,%d,%d), which is inconsistent with the location specified in the constraint file (%d,%d,%d,%d).", - blk_id, loc.x, loc.y, loc.layer, loc.sub_tile, constraint_loc.x, constraint_loc.y, constraint_loc.layer, constraint_loc.sub_tile); + "The new location assigned to cluster #%d is (%d,%d,%d,%d), which is inconsistent with the location specified in the constraint file (%d,%d,%d,%d).", + blk_id, loc.x, loc.y, loc.layer, loc.sub_tile, constraint_loc.x, constraint_loc.y, constraint_loc.layer, constraint_loc.sub_tile); } } blk_loc_registry.set_block_location(blk_id, loc); diff --git a/vpr/src/base/read_place.h b/vpr/src/base/read_place.h index 088f17dd546..9fa6eee6328 100644 --- a/vpr/src/base/read_place.h +++ b/vpr/src/base/read_place.h @@ -5,7 +5,6 @@ #include - class PlacerState; class ClusterBlockId; struct t_block_loc; diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index b88a7d76949..ead89961aa1 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -21,30 +21,23 @@ #include #include -#include "atom_netlist.h" -#include "atom_netlist_utils.h" -#include "rr_graph.h" +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_digest.h" #include "vtr_util.h" -#include "tatum/echo_writer.hpp" #include "vtr_log.h" #include "check_route.h" #include "route_common.h" #include "vpr_types.h" #include "globals.h" -#include "vpr_api.h" #include "read_place.h" #include "vpr_types.h" #include "vpr_utils.h" #include "vpr_error.h" -#include "place_and_route.h" -#include "timing_place.h" -#include "route_export.h" -#include "echo_files.h" #include "route_common.h" #include "route_tree.h" #include "read_route.h" +#include "d_ary_heap.h" #include "old_traceback.h" @@ -104,7 +97,7 @@ bool read_route(const char* route_file, const t_router_opts& router_opts, bool v /*Allocate necessary routing structures*/ alloc_and_load_rr_node_route_structs(); - const Netlist<>& router_net_list = (flat_router) ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& router_net_list = (flat_router) ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; init_route_structs(router_net_list, router_opts.bb_factor, router_opts.has_choke_point, @@ -212,7 +205,6 @@ static void process_nets(const Netlist<>& net_list, std::ifstream& fp, ClusterNe process_nodes(net_list, fp, inet, filename, lineno); } input_tokens.clear(); - return; } static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterNetId inet, const char* filename, int& lineno) { diff --git a/vpr/src/base/region.cpp b/vpr/src/base/region.cpp index 7cc6280626b..ff4040e8ff7 100644 --- a/vpr/src/base/region.cpp +++ b/vpr/src/base/region.cpp @@ -44,8 +44,7 @@ void Region::set_sub_tile(int sub_tile) { bool Region::empty() const { const auto [layer_low, layer_high] = layer_range_; - return (rect_.xmax() < rect_.xmin() || rect_.ymax() < rect_.ymin() || - layer_high < layer_low); + return (rect_.xmax() < rect_.xmin() || rect_.ymax() < rect_.ymin() || layer_high < layer_low); } bool Region::is_loc_in_reg(t_pl_loc loc) const { @@ -83,7 +82,7 @@ Region intersection(const Region& r1, const Region& r2) { auto [r2_layer_low, r2_layer_high] = r2.get_layer_range(); auto [intersect_layer_begin, intersect_layer_end] = std::make_pair(std::max(r1_layer_low, r2_layer_low), - std::min(r1_layer_high, r2_layer_high)); + std::min(r1_layer_high, r2_layer_high)); // check that the give layer range start from a lower layer and end at a higher or the same layer // negative layer means that the given Region object is an empty region diff --git a/vpr/src/base/region.h b/vpr/src/base/region.h index 18a179af19a..08959f1bdc6 100644 --- a/vpr/src/base/region.h +++ b/vpr/src/base/region.h @@ -77,9 +77,7 @@ class Region { bool is_loc_in_reg(t_pl_loc loc) const; bool operator==(const Region& reg) const { - return (reg.rect_ == rect_ && - reg.layer_range_ == layer_range_ && - reg.get_sub_tile() == sub_tile_); + return (reg.rect_ == rect_ && reg.layer_range_ == layer_range_ && reg.get_sub_tile() == sub_tile_); } private: @@ -99,7 +97,7 @@ class Region { */ std::pair layer_range_; - int sub_tile_; ///< users will optionally select a subtile + int sub_tile_; ///< users will optionally select a subtile }; /** diff --git a/vpr/src/base/setup_noc.cpp b/vpr/src/base/setup_noc.cpp index ff05687c414..75313969312 100644 --- a/vpr/src/base/setup_noc.cpp +++ b/vpr/src/base/setup_noc.cpp @@ -38,7 +38,7 @@ void setup_noc(const t_arch& arch) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "The Provided NoC topology information in the architecture file " "uses less number of routers than what is available in the FPGA device."); - } else if (noc_router_tiles.empty()) { // case where no physical router tiles were found + } else if (noc_router_tiles.empty()) { // case where no physical router tiles were found VPR_FATAL_ERROR(VPR_ERROR_OTHER, "No physical NoC routers were found on the FPGA device. " "Either the provided name for the physical router tile was incorrect or the FPGA device has no routers."); @@ -169,7 +169,7 @@ void create_noc_routers(const t_noc_inf& noc_info, error_case_physical_router_index_1 = closest_physical_router; error_case_physical_router_index_2 = curr_physical_router_index; - // case where the current logical router is closest to the physical router tile + // case where the current logical router is closest to the physical router tile } else if (curr_calculated_distance < shortest_distance) { // update the shortest distance and then the closest router shortest_distance = curr_calculated_distance; diff --git a/vpr/src/base/setup_noc.h b/vpr/src/base/setup_noc.h index 4052ec4d940..9b728e0f0ab 100644 --- a/vpr/src/base/setup_noc.h +++ b/vpr/src/base/setup_noc.h @@ -39,7 +39,7 @@ // a data structure to store the position information of a noc router in the FPGA device struct t_noc_router_tile_position { - t_noc_router_tile_position(int x, int y, int layer_num, float centroid_x, float centroid_y) + t_noc_router_tile_position(int x, int y, int layer_num, float centroid_x, float centroid_y) noexcept : grid_width_position(x) , grid_height_position(y) , layer_position(layer_num) @@ -131,4 +131,4 @@ void create_noc_routers(const t_noc_inf& noc_info, */ void create_noc_links(const t_noc_inf& noc_info, NocStorage* noc_model); -#endif \ No newline at end of file +#endif diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp index bda53d16a56..774235bf2cc 100644 --- a/vpr/src/base/stats.cpp +++ b/vpr/src/base/stats.cpp @@ -1,6 +1,12 @@ -#include + +#include "stats.h" + #include +#include +#include +#include +#include "physical_types_util.h" #include "route_tree.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -14,34 +20,45 @@ #include "rr_graph_area.h" #include "segment_stats.h" #include "channel_stats.h" -#include "stats.h" -#include "net_delay.h" -#include "read_xml_arch_file.h" -#include "echo_files.h" - -#include "timing_info.h" -#include "RoutingDelayCalculator.h" - -#include "timing_util.h" -#include "tatum/TimingReporter.hpp" /********************** Subroutines local to this module *********************/ +/** + * @brief Loads the two arrays passed in with the total occupancy at each of the + * channel segments in the FPGA. + */ static void load_channel_occupancies(const Netlist<>& net_list, vtr::Matrix& chanx_occ, vtr::Matrix& chany_occ); +/** + * @brief Writes channel occupancy data to a file. + * + * Each row contains: + * - (x, y) coordinate + * - Occupancy count + * - Occupancy percentage (occupancy / capacity) + * - Channel capacity + * + * @param filename Output file path. + * @param occupancy Matrix of occupancy counts. + * @param capacity_list List of channel capacities (per y for chanx, per x for chany). + */ +static void write_channel_occupancy_table(const std::string_view filename, + const vtr::Matrix& occupancy, + const std::vector& capacity_list); + +/** + * @brief Figures out maximum, minimum and average number of bends + * and net length in the routing. + */ static void length_and_bends_stats(const Netlist<>& net_list, bool is_flat); +///@brief Determines how many tracks are used in each channel. static void get_channel_occupancy_stats(const Netlist<>& net_list, bool /***/); /************************* Subroutine definitions ****************************/ -/** - * @brief Prints out various statistics about the current routing. - * - * Both a routing and an rr_graph must exist when you call this routine. - */ void routing_stats(const Netlist<>& net_list, bool full_stats, enum e_route_type route_type, @@ -113,10 +130,6 @@ void routing_stats(const Netlist<>& net_list, } } -/** - * @brief Figures out maximum, minimum and average number of bends - * and net length in the routing. - */ void length_and_bends_stats(const Netlist<>& net_list, bool is_flat) { int max_bends = 0; int total_bends = 0; @@ -176,9 +189,8 @@ void length_and_bends_stats(const Netlist<>& net_list, bool is_flat) { VTR_LOG("Total number of nets absorbed: %d\n", num_absorbed_nets); } -///@brief Determines how many tracks are used in each channel. static void get_channel_occupancy_stats(const Netlist<>& net_list, bool /***/) { - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); auto chanx_occ = vtr::Matrix({{ device_ctx.grid.width(), //[0 .. device_ctx.grid.width() - 1] (length of x channel) @@ -191,8 +203,12 @@ static void get_channel_occupancy_stats(const Netlist<>& net_list, bool /***/) { device_ctx.grid.height() //[0 .. device_ctx.grid.height() - 1] (length of y channel) }}, 0); + load_channel_occupancies(net_list, chanx_occ, chany_occ); + write_channel_occupancy_table("chanx_occupancy.txt", chanx_occ, device_ctx.chan_width.x_list); + write_channel_occupancy_table("chany_occupancy.txt", chany_occ, device_ctx.chan_width.y_list); + VTR_LOG("\n"); VTR_LOG("X - Directed channels: j max occ ave occ capacity\n"); VTR_LOG(" ---- ------- ------- --------\n"); @@ -233,16 +249,50 @@ static void get_channel_occupancy_stats(const Netlist<>& net_list, bool /***/) { VTR_LOG("\n"); } -/** - * @brief Loads the two arrays passed in with the total occupancy at each of the - * channel segments in the FPGA. - */ +static void write_channel_occupancy_table(const std::string_view filename, + const vtr::Matrix& occupancy, + const std::vector& capacity_list) { + constexpr int w_coord = 6; + constexpr int w_value = 12; + constexpr int w_percent = 12; + + std::ofstream file(filename.data()); + if (!file.is_open()) { + VTR_LOG_WARN("Failed to open %s for writing.\n", filename.data()); + return; + } + + file << std::setw(w_coord) << "x" + << std::setw(w_coord) << "y" + << std::setw(w_value) << "occupancy" + << std::setw(w_percent) << "%" + << std::setw(w_value) << "capacity" + << "\n"; + + for (size_t y = 0; y < occupancy.dim_size(1); ++y) { + int capacity = capacity_list[y]; + for (size_t x = 0; x < occupancy.dim_size(0); ++x) { + int occ = occupancy[x][y]; + float percent = capacity > 0 ? static_cast(occ) / capacity * 100.0f : 0.0f; + + file << std::setw(w_coord) << x + << std::setw(w_coord) << y + << std::setw(w_value) << occ + << std::setw(w_percent) << std::fixed << std::setprecision(3) << percent + << std::setw(w_value) << capacity + << "\n"; + } + } + + file.close(); +} + static void load_channel_occupancies(const Netlist<>& net_list, vtr::Matrix& chanx_occ, vtr::Matrix& chany_occ) { - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - auto& route_ctx = g_vpr_ctx.routing(); + const auto& route_ctx = g_vpr_ctx.routing(); /* First set the occupancy of everything to zero. */ chanx_occ.fill(0); @@ -258,7 +308,7 @@ static void load_channel_occupancies(const Netlist<>& net_list, if (!tree) continue; - for (auto& rt_node : tree.value().all_nodes()) { + for (const RouteTreeNode& rt_node : tree.value().all_nodes()) { RRNodeId inode = rt_node.inode; t_rr_type rr_type = rr_graph.node_type(inode); @@ -284,11 +334,9 @@ void get_num_bends_and_length(ParentNetId inet, int* bends_ptr, int* len_ptr, in auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - int bends, length, segments; - - bends = 0; - length = 0; - segments = 0; + int bends = 0; + int length = 0; + int segments = 0; const vtr::optional& tree = route_ctx.route_trees[inet]; if (!tree) { @@ -344,7 +392,7 @@ void print_wirelen_prob_dist(bool is_flat) { norm_fac = 0.; for (auto net_id : cluster_ctx.clb_nlist.nets()) { - auto par_net_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net_id, is_flat); + auto par_net_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net_id, is_flat); if (!cluster_ctx.clb_nlist.net_is_ignored(net_id) && cluster_ctx.clb_nlist.net_sinks(net_id).size() != 0) { get_num_bends_and_length(par_net_id, &bends, &length, &segments, &is_absorbed); @@ -446,13 +494,137 @@ int count_netlist_clocks() { std::set clock_names; //Loop through each clock pin and record the names in clock_names - for (auto blk_id : atom_ctx.nlist.blocks()) { - for (auto pin_id : atom_ctx.nlist.block_clock_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); - clock_names.insert(atom_ctx.nlist.net_name(net_id)); + for (auto blk_id : atom_ctx.netlist().blocks()) { + for (auto pin_id : atom_ctx.netlist().block_clock_pins(blk_id)) { + auto net_id = atom_ctx.netlist().pin_net(pin_id); + clock_names.insert(atom_ctx.netlist().net_name(net_id)); } } //Since std::set does not include duplicates, the number of clocks is the size of the set return static_cast(clock_names.size()); } + +float calculate_device_utilization(const DeviceGrid& grid, const std::map& instance_counts) { + //Record the resources of the grid + std::map grid_resources; + for (int layer_num = 0; layer_num < grid.get_num_layers(); ++layer_num) { + for (int x = 0; x < (int)grid.width(); ++x) { + for (int y = 0; y < (int)grid.height(); ++y) { + int width_offset = grid.get_width_offset({x, y, layer_num}); + int height_offset = grid.get_height_offset({x, y, layer_num}); + if (width_offset == 0 && height_offset == 0) { + const auto& type = grid.get_physical_type({x, y, layer_num}); + ++grid_resources[type]; + } + } + } + } + + //Determine the area of grid in tile units + float grid_area = 0.; + for (auto& kv : grid_resources) { + t_physical_tile_type_ptr type = kv.first; + size_t count = kv.second; + + float type_area = type->width * type->height; + + grid_area += type_area * count; + } + + //Determine the area of instances in tile units + float instance_area = 0.; + for (auto& kv : instance_counts) { + if (is_empty_type(kv.first)) { + continue; + } + + t_physical_tile_type_ptr type = pick_physical_type(kv.first); + + size_t count = kv.second; + + float type_area = type->width * type->height; + + //Instances of multi-capaicty blocks take up less space + if (type->capacity != 0) { + type_area /= type->capacity; + } + + instance_area += type_area * count; + } + + float utilization = instance_area / grid_area; + + return utilization; +} + +void print_resource_usage() { + auto& device_ctx = g_vpr_ctx.device(); + const auto& clb_netlist = g_vpr_ctx.clustering().clb_nlist; + std::map num_type_instances; + for (auto blk_id : clb_netlist.blocks()) { + num_type_instances[clb_netlist.block_type(blk_id)]++; + } + + VTR_LOG("\n"); + VTR_LOG("Resource usage...\n"); + for (const auto& type : device_ctx.logical_block_types) { + if (is_empty_type(&type)) continue; + size_t num_instances = num_type_instances.count(&type) > 0 ? num_type_instances.at(&type) : 0; + VTR_LOG("\tNetlist\n\t\t%d\tblocks of type: %s\n", + num_instances, type.name.c_str()); + + VTR_LOG("\tArchitecture\n"); + for (const auto equivalent_tile : type.equivalent_tiles) { + //get the number of equivalent tile across all layers + num_instances = device_ctx.grid.num_instances(equivalent_tile, -1); + + VTR_LOG("\t\t%d\tblocks of type: %s\n", + num_instances, equivalent_tile->name.c_str()); + } + } + VTR_LOG("\n"); +} + +void print_device_utilization(const float target_device_utilization) { + auto& device_ctx = g_vpr_ctx.device(); + const auto& clb_netlist = g_vpr_ctx.clustering().clb_nlist; + std::map num_type_instances; + for (auto blk_id : clb_netlist.blocks()) { + num_type_instances[clb_netlist.block_type(blk_id)]++; + } + + float device_utilization = calculate_device_utilization(device_ctx.grid, num_type_instances); + VTR_LOG("Device Utilization: %.2f (target %.2f)\n", device_utilization, target_device_utilization); + for (const auto& type : device_ctx.physical_tile_types) { + if (is_empty_type(&type)) { + continue; + } + + if (device_ctx.grid.num_instances(&type, -1) != 0) { + VTR_LOG("\tPhysical Tile %s:\n", type.name.c_str()); + + auto equivalent_sites = get_equivalent_sites_set(&type); + + for (auto logical_block : equivalent_sites) { + float util = 0.; + size_t num_inst = device_ctx.grid.num_instances(&type, -1); + if (num_inst != 0) { + size_t num_netlist_instances = num_type_instances.count(logical_block) > 0 ? num_type_instances.at(logical_block) : 0; + util = float(num_netlist_instances) / num_inst; + } + VTR_LOG("\tBlock Utilization: %.2f Logical Block: %s\n", util, logical_block->name.c_str()); + } + } + } + VTR_LOG("\n"); + + if (!device_ctx.grid.limiting_resources().empty()) { + std::vector limiting_block_names; + for (auto blk_type : device_ctx.grid.limiting_resources()) { + limiting_block_names.emplace_back(blk_type->name); + } + VTR_LOG("FPGA size limited by block type(s): %s\n", vtr::join(limiting_block_names, " ").c_str()); + VTR_LOG("\n"); + } +} diff --git a/vpr/src/base/stats.h b/vpr/src/base/stats.h index d02cae8f9a0..5f9e50e0700 100644 --- a/vpr/src/base/stats.h +++ b/vpr/src/base/stats.h @@ -3,7 +3,13 @@ #include #include #include "vpr_types.h" +#include "netlist.h" +/** + * @brief Prints out various statistics about the current routing. + * + * Both a routing and an rr_graph must exist when you call this routine. + */ void routing_stats(const Netlist<>& net_list, bool full_stats, enum e_route_type route_type, @@ -24,28 +30,20 @@ void get_num_bends_and_length(ParentNetId inet, int* bends, int* length, int* se int count_netlist_clocks(); /** - * @brief template functions must be defined in header, or explicitely - * instantiated in definition file (defeats the point of template) + * @brief Calculate the device utilization + * + * Calculate the device utilization (i.e. fraction of used grid tiles) + * for the specified grid and resource requirements + */ +float calculate_device_utilization(const DeviceGrid& grid, const std::map& instance_counts); + +/** + * @brief Prints the number of resources in the netlist and the number of available resources in the architecture. + */ +void print_resource_usage(); + +/** + * @brief Prints the device utilization + * @param target_device_utilization The target device utilization set by the user */ -template -double linear_regression_vector(const std::vector& vals, size_t start_x = 0) { - // returns slope; index is x, val is y - size_t n{vals.size() - start_x}; - - double x_avg{0}, y_avg{0}; - for (size_t x = start_x; x < vals.size(); ++x) { - x_avg += x; - y_avg += vals[x]; - } - x_avg /= (double)n; - y_avg /= (double)n; - - double numerator = 0, denominator = 0; - for (size_t x = start_x; x < vals.size(); ++x) { - numerator += (x - x_avg) * (vals[x] - y_avg); - denominator += (x - x_avg) * (x - x_avg); - } - - if (denominator == 0) return std::numeric_limits::max(); - return numerator / denominator; -} +void print_device_utilization(const float target_device_utilization); diff --git a/vpr/src/base/user_route_constraints.cpp b/vpr/src/base/user_route_constraints.cpp index 67cabe6b20e..b6d3f1b0384 100644 --- a/vpr/src/base/user_route_constraints.cpp +++ b/vpr/src/base/user_route_constraints.cpp @@ -72,4 +72,4 @@ const std::string UserRouteConstraints::get_routing_network_name_by_net_name(std int UserRouteConstraints::get_num_route_constraints(void) const { return route_constraints_.size(); -} \ No newline at end of file +} diff --git a/vpr/src/base/user_route_constraints.h b/vpr/src/base/user_route_constraints.h index ec925d7887d..62ba08cda1d 100644 --- a/vpr/src/base/user_route_constraints.h +++ b/vpr/src/base/user_route_constraints.h @@ -153,4 +153,4 @@ class UserRouteConstraints { */ std::unordered_map route_constraints_; }; -#endif /* USER_ROUTE_CONSTRAINTS_H */ \ No newline at end of file +#endif /* USER_ROUTE_CONSTRAINTS_H */ diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 1560b03e90f..6b2acb57dcf 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -14,12 +14,17 @@ #include #include #include +#include +#include +#include "PreClusterTimingManager.h" +#include "flat_placement_types.h" #include "cluster_util.h" +#include "physical_types.h" +#include "place_macro.h" #include "verify_placement.h" #include "vpr_context.h" #include "vtr_assert.h" -#include "vtr_math.h" #include "vtr_log.h" #include "vtr_version.h" #include "vtr_time.h" @@ -30,7 +35,6 @@ #include "atom_netlist.h" #include "read_netlist.h" #include "check_netlist.h" -#include "read_blif.h" #include "draw.h" #include "place_and_route.h" #include "pack.h" @@ -67,7 +71,6 @@ #include "atom_netlist_utils.h" #include "output_clustering.h" #include "vpr_constraints_reader.h" -#include "place_constraints.h" #include "place_util.h" #include "timing_fail_error.h" #include "analytical_placement_flow.h" @@ -93,9 +96,9 @@ #include "load_flat_place.h" #ifdef VPR_USE_TBB -# define TBB_PREVIEW_GLOBAL_CONTROL 1 /* Needed for compatibility with old TBB versions */ -# include -# include +#define TBB_PREVIEW_GLOBAL_CONTROL 1 /* Needed for compatibility with old TBB versions */ +#include +#include #endif #ifndef NO_SERVER @@ -109,12 +112,6 @@ static void free_complex_block_types(); static void free_device(const t_det_routing_arch& routing_arch); static void free_circuit(); -static void get_intercluster_switch_fanin_estimates(const t_vpr_setup& vpr_setup, - const t_arch& arch, - const int wire_segment_length, - int* opin_switch_fanin, - int* wire_switch_fanin, - int* ipin_switch_fanin); /* Local subroutines end */ ///@brief Display general VPR information @@ -320,13 +317,13 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a /* Read blif file and sweep unused components */ auto& atom_ctx = g_vpr_ctx.mutable_atom(); - atom_ctx.nlist = read_and_process_circuit(options->circuit_format, *vpr_setup, *arch); + atom_ctx.mutable_netlist() = read_and_process_circuit(options->circuit_format, *vpr_setup, *arch); if (vpr_setup->PowerOpts.do_power) { //Load the net activity file for power estimation vtr::ScopedStartFinishTimer t("Load Activity File"); auto& power_ctx = g_vpr_ctx.mutable_power(); - power_ctx.atom_net_power = read_activity(atom_ctx.nlist, vpr_setup->FileNameOpts.ActFile.c_str()); + power_ctx.atom_net_power = read_activity(atom_ctx.netlist(), vpr_setup->FileNameOpts.ActFile.c_str()); } //Initialize timing graph and constraints @@ -334,17 +331,17 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a auto& timing_ctx = g_vpr_ctx.mutable_timing(); { vtr::ScopedStartFinishTimer t("Build Timing Graph"); - timing_ctx.graph = TimingGraphBuilder(atom_ctx.nlist, atom_ctx.lookup).timing_graph(options->allow_dangling_combinational_nodes); + timing_ctx.graph = TimingGraphBuilder(atom_ctx.netlist(), atom_ctx.mutable_lookup()).timing_graph(options->allow_dangling_combinational_nodes); VTR_LOG(" Timing Graph Nodes: %zu\n", timing_ctx.graph->nodes().size()); VTR_LOG(" Timing Graph Edges: %zu\n", timing_ctx.graph->edges().size()); VTR_LOG(" Timing Graph Levels: %zu\n", timing_ctx.graph->levels().size()); } { - print_netlist_clock_info(atom_ctx.nlist); + print_netlist_clock_info(atom_ctx.netlist()); } { vtr::ScopedStartFinishTimer t("Load Timing Constraints"); - timing_ctx.constraints = read_sdc(vpr_setup->Timing, atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph); + timing_ctx.constraints = read_sdc(vpr_setup->Timing, atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph); } { set_terminate_if_timing_fails(options->terminate_if_timing_fails); @@ -389,9 +386,16 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { } } - // For the time being, we decided to create the flat graph after placement is done. Thus, the is_flat parameter for this function - //, since it is called before routing, should be false. - vpr_create_device(vpr_setup, arch, false); + vpr_create_device(vpr_setup, arch); + // If packing is not skipped, cluster netlist contain valid information, so + // we can print the resource usage and device utilization + if (vpr_setup.PackerOpts.doPacking != STAGE_SKIP) { + float target_device_utilization = vpr_setup.PackerOpts.target_device_utilization; + // Print the number of resources in netlist and number of resources available in architecture + print_resource_usage(); + // Print the device utilization + print_device_utilization(target_device_utilization); + } // TODO: Placer still assumes that cluster net list is used - graphics can not work with flat routing yet vpr_init_graphics(vpr_setup, arch, false); @@ -409,8 +413,23 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { { // Analytical Place if (vpr_setup.APOpts.doAP == STAGE_DO) { + // Passing flat placement input if provided and not loaded yet. + if (!vpr_setup.FileNameOpts.read_flat_place_file.empty() && !g_vpr_ctx.atom().flat_placement_info().valid) { + g_vpr_ctx.mutable_atom().mutable_flat_placement_info() = read_flat_placement(vpr_setup.FileNameOpts.read_flat_place_file, + g_vpr_ctx.atom().netlist()); + } + // TODO: Make this return a bool if the placement was successful or not. run_analytical_placement_flow(vpr_setup); + + // Write out a flat placement file at the end of Analytical Placement + // flow if the option is specified. + if (!vpr_setup.FileNameOpts.write_flat_place_file.empty()) { + write_flat_placement(vpr_setup.FileNameOpts.write_flat_place_file.c_str(), + g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.placement().block_locs(), + g_vpr_ctx.clustering().atoms_lookup); + } } // Print the placement generated by AP to a .place file. auto& filename_opts = vpr_setup.FileNameOpts; @@ -424,7 +443,7 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { } bool is_flat = vpr_setup.RouterOpts.flat_routing; - const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; RouteStatus route_status; { //Route route_status = vpr_route_flow(router_net_list, vpr_setup, arch, is_flat); @@ -439,7 +458,7 @@ bool vpr_flow(t_vpr_setup& vpr_setup, t_arch& arch) { return route_status.success(); } -void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_flat) { +void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& arch) { vtr::ScopedStartFinishTimer timer("Create Device"); vpr_create_device_grid(vpr_setup, arch); @@ -448,7 +467,9 @@ void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& arch, bool is_flat) vpr_setup_noc(vpr_setup, arch); if (vpr_setup.PlacerOpts.place_chan_width != NO_FIXED_CHANNEL_WIDTH) { - vpr_create_rr_graph(vpr_setup, arch, vpr_setup.PlacerOpts.place_chan_width, is_flat); + // The RR graph built by this function should contain only the intra-cluster resources. + // If the flat router is used, additional resources are added when routing begins. + vpr_create_rr_graph(vpr_setup, arch, vpr_setup.PlacerOpts.place_chan_width, false); } } @@ -491,59 +512,6 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { */ size_t num_grid_tiles = count_grid_tiles(device_ctx.grid); VTR_LOG("FPGA sized to %zu x %zu: %zu grid tiles (%s)\n", device_ctx.grid.width(), device_ctx.grid.height(), num_grid_tiles, device_ctx.grid.name().c_str()); - - VTR_LOG("\n"); - VTR_LOG("Resource usage...\n"); - for (const auto& type : device_ctx.logical_block_types) { - if (is_empty_type(&type)) continue; - - VTR_LOG("\tNetlist\n\t\t%d\tblocks of type: %s\n", - num_type_instances[&type], type.name.c_str()); - - VTR_LOG("\tArchitecture\n"); - for (const auto equivalent_tile : type.equivalent_tiles) { - auto num_instances = 0; - //get the number of equivalent tile across all layers - num_instances = (int)device_ctx.grid.num_instances(equivalent_tile, -1); - - VTR_LOG("\t\t%d\tblocks of type: %s\n", - num_instances, equivalent_tile->name.c_str()); - } - } - VTR_LOG("\n"); - - float device_utilization = calculate_device_utilization(device_ctx.grid, num_type_instances); - VTR_LOG("Device Utilization: %.2f (target %.2f)\n", device_utilization, target_device_utilization); - for (const auto& type : device_ctx.physical_tile_types) { - if (is_empty_type(&type)) { - continue; - } - - if (device_ctx.grid.num_instances(&type, -1) != 0) { - VTR_LOG("\tPhysical Tile %s:\n", type.name.c_str()); - - auto equivalent_sites = get_equivalent_sites_set(&type); - - for (auto logical_block : equivalent_sites) { - float util = 0.; - size_t num_inst = device_ctx.grid.num_instances(&type, -1); - if (num_inst != 0) { - util = float(num_type_instances[logical_block]) / num_inst; - } - VTR_LOG("\tBlock Utilization: %.2f Logical Block: %s\n", util, logical_block->name.c_str()); - } - } - } - VTR_LOG("\n"); - - if (!device_ctx.grid.limiting_resources().empty()) { - std::vector limiting_block_names; - for (auto blk_type : device_ctx.grid.limiting_resources()) { - limiting_block_names.emplace_back(blk_type->name); - } - VTR_LOG("FPGA size limited by block type(s): %s\n", vtr::join(limiting_block_names, " ").c_str()); - VTR_LOG("\n"); - } } void vpr_setup_clock_networks(t_vpr_setup& vpr_setup, const t_arch& Arch) { @@ -644,60 +612,39 @@ bool vpr_pack_flow(t_vpr_setup& vpr_setup, const t_arch& arch) { bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) { vtr::ScopedStartFinishTimer timer("Packing"); - /* If needed, estimate inter-cluster delay. Assume the average routing hop goes out of - * a block through an opin switch to a length-4 wire, then through a wire switch to another - * length-4 wire, then through a wire-to-ipin-switch into another block. */ - int wire_segment_length = 4; - - float inter_cluster_delay = UNDEFINED; - if (vpr_setup.PackerOpts.timing_driven - && vpr_setup.PackerOpts.auto_compute_inter_cluster_net_delay) { - /* We want to determine a reasonable fan-in to the opin, wire, and ipin switches, based - * on which the intercluster delays can be estimated. The fan-in of a switch influences its - * delay. - * - * The fan-in of the switch depends on the architecture (unidirectional/bidirectional), as - * well as Fc_in/out and Fs */ - int opin_switch_fanin, wire_switch_fanin, ipin_switch_fanin; - get_intercluster_switch_fanin_estimates(vpr_setup, arch, wire_segment_length, &opin_switch_fanin, - &wire_switch_fanin, &ipin_switch_fanin); - - float Tdel_opin_switch, R_opin_switch, Cout_opin_switch; - float opin_switch_del = get_arch_switch_info(arch.Segments[0].arch_opin_switch, opin_switch_fanin, - Tdel_opin_switch, R_opin_switch, Cout_opin_switch); - - float Tdel_wire_switch, R_wire_switch, Cout_wire_switch; - float wire_switch_del = get_arch_switch_info(arch.Segments[0].arch_wire_switch, wire_switch_fanin, - Tdel_wire_switch, R_wire_switch, Cout_wire_switch); - - float Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch; - float wtoi_switch_del = get_arch_switch_info(vpr_setup.RoutingArch.wire_to_arch_ipin_switch, ipin_switch_fanin, - Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch); - - float Rmetal = arch.Segments[0].Rmetal; - float Cmetal = arch.Segments[0].Cmetal; - - /* The delay of a wire with its driving switch is the switch delay plus the - * product of the equivalent resistance and capacitance experienced by the wire. */ - - float first_wire_seg_delay = opin_switch_del - + (R_opin_switch + Rmetal * (float)wire_segment_length / 2) - * (Cout_opin_switch + Cmetal * (float)wire_segment_length); - float second_wire_seg_delay = wire_switch_del - + (R_wire_switch + Rmetal * (float)wire_segment_length / 2) - * (Cout_wire_switch + Cmetal * (float)wire_segment_length); - inter_cluster_delay = 4 - * (first_wire_seg_delay + second_wire_seg_delay - + wtoi_switch_del); /* multiply by 4 to get a more conservative estimate */ + // Read in the flat placement if a flat placement file is provided and it + // has not been loaded already. + if (!vpr_setup.FileNameOpts.read_flat_place_file.empty() && !g_vpr_ctx.atom().flat_placement_info().valid) { + g_vpr_ctx.mutable_atom().mutable_flat_placement_info() = read_flat_placement(vpr_setup.FileNameOpts.read_flat_place_file, + g_vpr_ctx.atom().netlist()); } - return try_pack(&vpr_setup.PackerOpts, &vpr_setup.AnalysisOpts, - &arch, vpr_setup.user_models, - vpr_setup.library_models, inter_cluster_delay, - vpr_setup.PackerRRGraph); + // Run the prepacker, packing the atoms into molecules. + // The Prepacker object performs prepacking and stores the pack molecules. + // As long as the molecules are used, this object must persist. + const Prepacker prepacker(g_vpr_ctx.atom().netlist(), + g_vpr_ctx.device().logical_block_types); + + // Setup pre-clustering timing analysis + PreClusterTimingManager pre_cluster_timing_manager(vpr_setup.PackerOpts.timing_driven, + g_vpr_ctx.atom().netlist(), + g_vpr_ctx.atom().lookup(), + prepacker, + vpr_setup.PackerOpts.timing_update_type, + arch, + vpr_setup.RoutingArch, + vpr_setup.PackerOpts.device_layout, + vpr_setup.AnalysisOpts); + + return try_pack(vpr_setup.PackerOpts, vpr_setup.AnalysisOpts, + arch, + vpr_setup.PackerRRGraph, + prepacker, + pre_cluster_timing_manager, + g_vpr_ctx.atom().flat_placement_info()); } -void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch) { +void vpr_load_packing(const t_vpr_setup& vpr_setup, const t_arch& arch) { vtr::ScopedStartFinishTimer timer("Load packing"); VTR_ASSERT_MSG(!vpr_setup.FileNameOpts.NetFile.empty(), @@ -718,8 +665,8 @@ void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch) { /* Load the mapping between clusters and their atoms */ init_clb_atoms_lookup(cluster_ctx.atoms_lookup, atom_ctx, cluster_ctx.clb_nlist); - process_constant_nets(g_vpr_ctx.mutable_atom().nlist, - atom_ctx.lookup, + process_constant_nets(g_vpr_ctx.mutable_atom().mutable_netlist(), + atom_ctx.lookup(), cluster_ctx.clb_nlist, vpr_setup.constant_net_method, vpr_setup.PackerOpts.pack_verbosity); @@ -729,8 +676,9 @@ void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch) { report_packing_pin_usage(ofs, g_vpr_ctx); } - // Load cluster_constraints data structure. - load_cluster_constraints(); + // Ater the clustered netlist has been loaded, update the floorplanning + // constraints with the new information. + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_post_pack(); /* Sanity check the resulting netlist */ check_netlist(vpr_setup.PackerOpts.pack_verbosity); @@ -789,7 +737,9 @@ bool vpr_load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { return true; } -bool vpr_place_flow(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch) { +bool vpr_place_flow(const Netlist<>& net_list, + t_vpr_setup& vpr_setup, + const t_arch& arch) { VTR_LOG("\n"); const auto& placer_opts = vpr_setup.PlacerOpts; const auto& filename_opts = vpr_setup.FileNameOpts; @@ -804,7 +754,7 @@ bool vpr_place_flow(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_a VTR_ASSERT(placer_opts.doPlacement == STAGE_LOAD); //Load a previous placement - vpr_load_placement(vpr_setup, arch); + vpr_load_placement(vpr_setup, arch.directs); } post_place_sync(); @@ -829,7 +779,9 @@ bool vpr_place_flow(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_a return true; } -void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch) { +void vpr_place(const Netlist<>& net_list, + t_vpr_setup& vpr_setup, + const t_arch& arch) { bool is_flat = false; if (vpr_setup.PlacerOpts.place_algorithm.is_timing_driven()) { // Prime lookahead cache to avoid adding lookahead computation cost to @@ -844,6 +796,13 @@ void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& is_flat); } + // Read in the flat placement if a flat placement file is provided and it + // has not been loaded already. + if (!vpr_setup.FileNameOpts.read_flat_place_file.empty() && !g_vpr_ctx.atom().flat_placement_info().valid) { + g_vpr_ctx.mutable_atom().mutable_flat_placement_info() = read_flat_placement(vpr_setup.FileNameOpts.read_flat_place_file, + g_vpr_ctx.atom().netlist()); + } + try_place(net_list, vpr_setup.PlacerOpts, vpr_setup.RouterOpts, @@ -853,6 +812,7 @@ void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& &vpr_setup.RoutingArch, vpr_setup.Segments, arch.directs, + g_vpr_ctx.atom().flat_placement_info(), is_flat); auto& filename_opts = vpr_setup.FileNameOpts; @@ -866,7 +826,8 @@ void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& block_locs); } -void vpr_load_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { +void vpr_load_placement(t_vpr_setup& vpr_setup, + const std::vector directs) { vtr::ScopedStartFinishTimer timer("Load Placement"); const auto& device_ctx = g_vpr_ctx.device(); @@ -874,8 +835,15 @@ void vpr_load_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { auto& blk_loc_registry = place_ctx.mutable_blk_loc_registry(); const auto& filename_opts = vpr_setup.FileNameOpts; - //Initialize placement data structures, which will be filled when loading placement - init_placement_context(blk_loc_registry, arch.directs); + //Initialize the block location registry, which will be filled when loading placement + blk_loc_registry.init(); + + // Alloc and load the placement macros. + place_ctx.place_macros = std::make_unique(directs, + device_ctx.physical_tile_types, + g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.atom().netlist(), + g_vpr_ctx.atom().lookup()); //Load an existing placement from a file place_ctx.placement_id = read_place(filename_opts.NetFile.c_str(), filename_opts.PlaceFile.c_str(), @@ -927,7 +895,7 @@ RouteStatus vpr_route_flow(const Netlist<>& net_list, std::shared_ptr routing_delay_calc = nullptr; if (vpr_setup.Timing.timing_analysis_enabled) { auto& atom_ctx = g_vpr_ctx.atom(); - routing_delay_calc = std::make_shared(atom_ctx.nlist, atom_ctx.lookup, net_delay, is_flat); + routing_delay_calc = std::make_shared(atom_ctx.netlist(), atom_ctx.lookup(), net_delay, is_flat); timing_info = make_setup_hold_timing_info(routing_delay_calc, router_opts.timing_update_type); #ifndef NO_SERVER if (g_vpr_ctx.server().gate_io.is_running()) { @@ -1118,7 +1086,7 @@ RouteStatus vpr_load_routing(t_vpr_setup& vpr_setup, //Load the routing from a file bool is_legal = read_route(filename_opts.RouteFile.c_str(), vpr_setup.RouterOpts, filename_opts.verify_file_digests, is_flat); - const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& router_net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; if (vpr_setup.Timing.timing_analysis_enabled) { //Update timing info load_net_delay_from_routing(router_net_list, @@ -1135,17 +1103,18 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi auto det_routing_arch = &vpr_setup.RoutingArch; auto& router_opts = vpr_setup.RouterOpts; - t_graph_type graph_type; - t_graph_type graph_directionality; + e_graph_type graph_type; + e_graph_type graph_directionality; if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - graph_directionality = GRAPH_BIDIR; + graph_type = e_graph_type::GLOBAL; + graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - if ((UNI_DIRECTIONAL == det_routing_arch->directionality) && (true == det_routing_arch->tileable)) { - graph_type = GRAPH_UNIDIR_TILEABLE; + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = e_graph_type::UNIDIR_TILEABLE; } + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } t_chan_width chan_width = init_chan(chan_width_fac, arch.Chans, graph_directionality); @@ -1199,100 +1168,6 @@ void vpr_close_graphics(const t_vpr_setup& /*vpr_setup*/) { free_draw_structs(); } -/** - * Since the parameters of a switch may change as a function of its fanin, - * to get an estimation of inter-cluster delays we need a reasonable estimation - * of the fan-ins of switches that connect clusters together. These switches are - * 1) opin to wire switch - * 2) wire to wire switch - * 3) wire to ipin switch - * We can estimate the fan-in of these switches based on the Fc_in/Fc_out of - * a logic block, and the switch block Fs value - */ -static void get_intercluster_switch_fanin_estimates(const t_vpr_setup& vpr_setup, - const t_arch& arch, - const int wire_segment_length, - int* opin_switch_fanin, - int* wire_switch_fanin, - int* ipin_switch_fanin) { - e_directionality directionality; - int Fs; - float Fc_in, Fc_out; - int W = 100; //W is unknown pre-packing, so *if* we need W here, we will assume a value of 100 - - directionality = vpr_setup.RoutingArch.directionality; - Fs = vpr_setup.RoutingArch.Fs; - Fc_in = 0, Fc_out = 0; - - //Build a dummy 10x10 device to determine the 'best' block type to use - auto grid = create_device_grid(vpr_setup.device_layout, arch.grid_layouts, 10, 10); - - auto type = find_most_common_tile_type(grid); - /* get Fc_in/out for most common block (e.g. logic blocks) */ - VTR_ASSERT(!type->fc_specs.empty()); - - //Estimate the maximum Fc_in/Fc_out - - for (const t_fc_specification& fc_spec : type->fc_specs) { - float Fc = fc_spec.fc_value; - - if (fc_spec.fc_value_type == e_fc_value_type::ABSOLUTE) { - //Convert to estimated fractional - Fc /= W; - } - VTR_ASSERT_MSG(Fc >= 0 && Fc <= 1., "Fc should be fractional"); - - for (int ipin : fc_spec.pins) { - e_pin_type pin_type = get_pin_type_from_pin_physical_num(type, ipin); - - if (pin_type == DRIVER) { - Fc_out = std::max(Fc, Fc_out); - } else { - VTR_ASSERT(pin_type == RECEIVER); - Fc_in = std::max(Fc, Fc_in); - } - } - } - - /* Estimates of switch fan-in are done as follows: - * 1) opin to wire switch: - * 2 CLBs connect to a channel, each with #opins/4 pins. Each pin has Fc_out*W - * switches, and then we assume the switches are distributed evenly over the W wires. - * In the unidirectional case, all these switches are then crammed down to W/wire_segment_length wires. - * - * Unidirectional: 2 * #opins_per_side * Fc_out * wire_segment_length - * Bidirectional: 2 * #opins_per_side * Fc_out - * - * 2) wire to wire switch - * A wire segment in a switchblock connects to Fs other wires. Assuming these connections are evenly - * distributed, each target wire receives Fs connections as well. In the unidirectional case, - * source wires can only connect to W/wire_segment_length wires. - * - * Unidirectional: Fs * wire_segment_length - * Bidirectional: Fs - * - * 3) wire to ipin switch - * An input pin of a CLB simply receives Fc_in connections. - * - * Unidirectional: Fc_in - * Bidirectional: Fc_in - */ - - /* Fan-in to opin/ipin/wire switches depends on whether the architecture is unidirectional/bidirectional */ - (*opin_switch_fanin) = 2 * type->num_drivers / 4 * Fc_out; - (*wire_switch_fanin) = Fs; - (*ipin_switch_fanin) = Fc_in; - if (directionality == UNI_DIRECTIONAL) { - /* adjustments to opin-to-wire and wire-to-wire switch fan-ins */ - (*opin_switch_fanin) *= wire_segment_length; - (*wire_switch_fanin) *= wire_segment_length; - } else if (directionality == BI_DIRECTIONAL) { - /* no adjustments need to be made here */ - } else { - VPR_FATAL_ERROR(VPR_ERROR_PACK, "Unrecognized directionality: %d\n", (int)directionality); - } -} - ///@brief Free architecture data structures void free_device(const t_det_routing_arch& /*routing_arch*/) { auto& device_ctx = g_vpr_ctx.mutable_device(); @@ -1328,8 +1203,8 @@ void free_circuit() { static void free_atoms() { auto& atom_ctx = g_vpr_ctx.mutable_atom(); - atom_ctx.nlist = AtomNetlist(); - atom_ctx.lookup = AtomLookup(); + atom_ctx.mutable_netlist() = AtomNetlist(); + atom_ctx.mutable_lookup() = AtomLookup(); } static void free_placement() { @@ -1505,12 +1380,12 @@ bool vpr_analysis_flow(const Netlist<>& net_list, if (is_flat) { sync_netlists_to_routing_flat(); } else { - sync_netlists_to_routing(net_list, - g_vpr_ctx.device(), - g_vpr_ctx.mutable_atom(), - g_vpr_ctx.mutable_clustering(), - g_vpr_ctx.placement(), - vpr_setup.PackerOpts.pack_verbosity > 2); + sync_netlists_to_routing(net_list, + g_vpr_ctx.device(), + g_vpr_ctx.mutable_atom(), + g_vpr_ctx.mutable_clustering(), + g_vpr_ctx.placement(), + vpr_setup.PackerOpts.pack_verbosity > 2); } } else { VTR_LOG_WARN("Sychronization between packing and routing results is not applied due to users select to skip it\n"); @@ -1518,8 +1393,8 @@ bool vpr_analysis_flow(const Netlist<>& net_list, std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing"; write_packing_results_to_xml(vpr_setup.PackerOpts.global_clocks, - Arch.architecture_id, - post_routing_packing_output_file_name.c_str()); + Arch.architecture_id, + post_routing_packing_output_file_name.c_str()); } else { VTR_LOG_WARN("Synchronization between packing and routing results is not applied due to illegal circuit implementation\n"); } @@ -1565,7 +1440,7 @@ void vpr_analysis(const Netlist<>& net_list, load_net_delay_from_routing(net_list, net_delay); //Do final timing analysis - auto analysis_delay_calc = std::make_shared(atom_ctx.nlist, atom_ctx.lookup, net_delay, vpr_setup.RouterOpts.flat_routing); + auto analysis_delay_calc = std::make_shared(atom_ctx.netlist(), atom_ctx.lookup(), net_delay, vpr_setup.RouterOpts.flat_routing); auto timing_info = make_setup_hold_timing_info(analysis_delay_calc, vpr_setup.AnalysisOpts.timing_update_type); timing_info->update(); @@ -1584,13 +1459,13 @@ void vpr_analysis(const Netlist<>& net_list, //Write the post-synthesis netlist if (vpr_setup.AnalysisOpts.gen_post_synthesis_netlist) { - netlist_writer(atom_ctx.nlist.netlist_name(), analysis_delay_calc, + netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, vpr_setup.AnalysisOpts); } //Write the post-implementation merged netlist if (vpr_setup.AnalysisOpts.gen_post_implementation_merged_netlist) { - merged_netlist_writer(atom_ctx.nlist.netlist_name(), analysis_delay_calc, vpr_setup.AnalysisOpts); + merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, vpr_setup.AnalysisOpts); } //Do power analysis diff --git a/vpr/src/base/vpr_api.h b/vpr/src/base/vpr_api.h index 93cf2d12cc1..7eda169ba5e 100644 --- a/vpr/src/base/vpr_api.h +++ b/vpr/src/base/vpr_api.h @@ -63,7 +63,7 @@ bool vpr_pack_flow(t_vpr_setup& vpr_setup, const t_arch& arch); bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch); ///@brief Loads a previous packing -void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch); +void vpr_load_packing(const t_vpr_setup& vpr_setup, const t_arch& arch); ///@brief Reconstructs a packing and placement solution from a flat placement file bool vpr_load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch); @@ -71,13 +71,18 @@ bool vpr_load_flat_placement(t_vpr_setup& vpr_setup, const t_arch& arch); /* Placement */ ///@brief Perform, load or skip the placement stage -bool vpr_place_flow(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch); +bool vpr_place_flow(const Netlist<>& net_list, + t_vpr_setup& vpr_setup, + const t_arch& arch); ///@brief Perform placement -void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch); +void vpr_place(const Netlist<>& net_list, + t_vpr_setup& vpr_setup, + const t_arch& arch); ///@brief Loads a previous placement -void vpr_load_placement(t_vpr_setup& vpr_setup, const t_arch& arch); +void vpr_load_placement(t_vpr_setup& vpr_setup, + const std::vector directs); /* Routing */ @@ -133,7 +138,7 @@ void vpr_analysis(const Netlist<>& net_list, /* Device creating */ ///@brief Create the device (grid + rr graph) -void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& Arch, bool is_flat); +void vpr_create_device(t_vpr_setup& vpr_setup, const t_arch& Arch); ///@brief Create the device grid void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch); diff --git a/vpr/src/base/vpr_constraints_serializer.h b/vpr/src/base/vpr_constraints_serializer.h index 9cfd47829c2..409a7702661 100644 --- a/vpr/src/base/vpr_constraints_serializer.h +++ b/vpr/src/base/vpr_constraints_serializer.h @@ -129,7 +129,7 @@ class VprConstraintsSerializer final : public uxsd::VprConstraintsBase +#include "compressed_grid.h" +#include "globals.h" +#include "physical_types.h" +#include "place_constraints.h" +#include "place_macro.h" +#include "vpr_types.h" +#include "vtr_memory.h" + +/** + * @brief determine the type of the bounding box used by the placer to predict + * the wirelength. + * + * @param place_bb_mode The bounding box mode passed by the CLI + * @param rr_graph The routing resource graph + */ +static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, + const RRGraphView& rr_graph); + +void FloorplanningContext::update_floorplanning_context_post_pack() { + // Initialize the cluster_constraints using the constraints loaded from the + // user and clustering generated from packing. + load_cluster_constraints(); +} + +void FloorplanningContext::update_floorplanning_context_pre_place(const PlaceMacros& place_macros) { + // Go through cluster blocks to calculate the tightest placement + // floorplan constraint for each constrained block. + propagate_place_constraints(place_macros); + + // Compute and store compressed floorplanning constraints. + alloc_and_load_compressed_cluster_constraints(); +} + +void FloorplanningContext::clean_floorplanning_context_post_place() { + // The cluster constraints are loaded in propagate_place_constraints and are + // not used outside of placement. + vtr::release_memory(cluster_constraints); + + // The compressed cluster constraints are loaded in alloc_and_load_compressed + // cluster_constraints and are not used outside of placement. + vtr::release_memory(compressed_cluster_constraints); +} + +void PlacementContext::init_placement_context(const t_placer_opts& placer_opts, + const std::vector& directs) { + const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const ClusteringContext& cluster_ctx = g_vpr_ctx.clustering(); + const DeviceContext& device_ctx = g_vpr_ctx.device(); + + cube_bb = is_cube_bb(placer_opts.place_bounding_box_mode, device_ctx.rr_graph); + + compressed_block_grids = create_compressed_block_grids(); + + // Alloc and load the placement macros. + place_macros = std::make_unique(directs, + device_ctx.physical_tile_types, + cluster_ctx.clb_nlist, + atom_ctx.netlist(), + atom_ctx.lookup()); +} + +static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, + const RRGraphView& rr_graph) { + bool cube_bb; + const int number_layers = g_vpr_ctx.device().grid.get_num_layers(); + + if (place_bb_mode == e_place_bounding_box_mode::AUTO_BB) { + // If the auto_bb is used, we analyze the RR graph to see whether is there any inter-layer connection that is not + // originated from OPIN. If there is any, cube BB is chosen, otherwise, per-layer bb is chosen. + if (number_layers > 1 && inter_layer_connections_limited_to_opin(rr_graph)) { + cube_bb = false; + } else { + cube_bb = true; + } + } else if (place_bb_mode == e_place_bounding_box_mode::CUBE_BB) { + // The user has specifically asked for CUBE_BB + cube_bb = true; + } else { + // The user has specifically asked for PER_LAYER_BB + VTR_ASSERT_SAFE(place_bb_mode == e_place_bounding_box_mode::PER_LAYER_BB); + cube_bb = false; + } + + return cube_bb; +} + +void PlacementContext::clean_placement_context_post_place() { + // The compressed block grids are currently only used during placement. + vtr::release_memory(compressed_block_grids); +} diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 1472aa054af..dcab8832f53 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -5,19 +5,20 @@ #include #include -#include "prepack.h" +#include "flat_placement_types.h" +#include "physical_types.h" +#include "place_macro.h" +#include "user_place_constraints.h" +#include "user_route_constraints.h" #include "vpr_types.h" -#include "vtr_ndmatrix.h" #include "vtr_optional.h" #include "vtr_vector.h" #include "vtr_vector_map.h" #include "atom_netlist.h" #include "clustered_netlist.h" #include "rr_graph_view.h" -#include "rr_graph_storage.h" #include "rr_graph_builder.h" #include "rr_node.h" -#include "rr_rc_data.h" #include "tatum/TimingGraph.hpp" #include "tatum/TimingConstraints.hpp" #include "power.h" @@ -27,10 +28,7 @@ #include "clock_connection_builders.h" #include "route_tree.h" #include "router_lookahead.h" -#include "place_macro.h" #include "compressed_grid.h" -#include "metadata_storage.h" -#include "vpr_constraints.h" #include "noc_storage.h" #include "noc_traffic_flows.h" #include "noc_routing.h" @@ -69,16 +67,50 @@ struct Context { * * This should contain only data structures related to user specified netlist * being implemented by VPR onto the target device. + * + * This class provides two categories of getter functions that give mutable or + * immutable reference to the global state. If you need read-only access, use + * the normal getter functions and if you need write access to the context use + * the mutable functions. */ struct AtomContext : public Context { /******************************************************************** * Atom Netlist ********************************************************************/ + private: /// @brief Atom netlist - AtomNetlist nlist; - + AtomNetlist nlist_; /// @brief Mappings to/from the Atom Netlist to physically described .blif models - AtomLookup lookup; + AtomLookup lookup_; + /// @brief Placement information on each atom known (from a file or another + /// algorithm) before packing and the cluster-level placement. + FlatPlacementInfo flat_placement_info_; + + public: + /** + * @brief Immutable reference to the AtomNetlist + */ + inline const AtomNetlist& netlist() const { return nlist_; } + /** + * @brief Mutable reference to the AtomNetlist + */ + inline AtomNetlist& mutable_netlist() { return nlist_; } + /** + * @brief Immutable reference to the AtomLookup + */ + inline const AtomLookup& lookup() const { return lookup_; } + /** + * @brief Mutable reference to the AtomLookup + */ + inline AtomLookup& mutable_lookup() { return lookup_; } + /** + * @brief Immutable reference to the FlatPlacementInfo + */ + inline const FlatPlacementInfo& flat_placement_info() const { return flat_placement_info_; } + /** + * @brief Mutable reference to the FlatPlacementInfo + */ + inline FlatPlacementInfo& mutable_flat_placement_info() { return flat_placement_info_; } }; /** @@ -246,12 +278,15 @@ struct DeviceContext : public Context { ********************************************************************/ t_clock_arch* clock_arch; - /** - * @brief Name of rrgraph file read (if any). - * - * Used to determine when reading rrgraph if file is already loaded. - */ - std::string read_rr_graph_filename; + /// @brief Name of rrgraph file read (if any). + /// Used to determine if the specified rr-graph file is already loaded, + /// so we can avoid redundant reading of the rr-graph + std::string loaded_rr_graph_filename; + + /// @brief Name of rrgraph edge override file read (if any). + /// Used to determine if the specified rr-graph edge override file is already loaded, + /// so we can avoid redundant reading of the rr-graph + std::string loaded_rr_edge_override_filename; /******************************************************************* * Place Related @@ -344,15 +379,62 @@ struct PlacementContext : public Context { BlkLocRegistry blk_loc_registry_; public: + /** + * @brief Initialize the variables stored within the placement context. This + * must be called before performing placement, but must be called + * after the clusters are loaded. + * + * @param placer_opts + * The options passed into the placer. + * @param directs + * A list of the direct connections in the architecture. + */ + void init_placement_context(const t_placer_opts& placer_opts, + const std::vector& directs); - const vtr::vector_map& block_locs() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.block_locs(); } - vtr::vector_map& mutable_block_locs() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_block_locs(); } - const GridBlock& grid_blocks() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.grid_blocks(); } - GridBlock& mutable_grid_blocks() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_grid_blocks(); } - vtr::vector_map& mutable_physical_pins() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_physical_pins(); } - const vtr::vector_map& physical_pins() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.physical_pins(); } - BlkLocRegistry& mutable_blk_loc_registry() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_; } - const BlkLocRegistry& blk_loc_registry() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_; } + /** + * @brief Clean variables from the placement context which are not used + * outside of placement. + * + * There are some variables that are stored in the placement context and are + * only used in placement; while there are some that are used outside of + * placement. This method frees up the memory of the variables used only + * within placement. + */ + void clean_placement_context_post_place(); + + const vtr::vector_map& block_locs() const { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.block_locs(); + } + vtr::vector_map& mutable_block_locs() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.mutable_block_locs(); + } + const GridBlock& grid_blocks() const { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.grid_blocks(); + } + GridBlock& mutable_grid_blocks() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.mutable_grid_blocks(); + } + vtr::vector_map& mutable_physical_pins() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.mutable_physical_pins(); + } + const vtr::vector_map& physical_pins() const { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_.physical_pins(); + } + BlkLocRegistry& mutable_blk_loc_registry() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_; + } + const BlkLocRegistry& blk_loc_registry() const { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + return blk_loc_registry_; + } /** * @brief Makes blk_loc_registry_ inaccessible through the getter methods. @@ -361,7 +443,10 @@ struct PlacementContext : public Context { * guarantee that the placement stage code does not access block location variables * stored in the global state. */ - void lock_loc_vars() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); loc_vars_are_accessible_ = false; } + void lock_loc_vars() { + VTR_ASSERT_SAFE(loc_vars_are_accessible_); + loc_vars_are_accessible_ = false; + } /** * @brief Makes blk_loc_registry_ accessible through the getter methods. @@ -369,13 +454,20 @@ struct PlacementContext : public Context { * This method should be called at the end of the placement stage to * make the block location information accessible for subsequent stages. */ - void unlock_loc_vars() { VTR_ASSERT_SAFE(!loc_vars_are_accessible_); loc_vars_are_accessible_ = true; } - - ///@brief Stores ClusterBlockId of all movable clustered blocks (blocks that are not locked down to a single location) - std::vector movable_blocks; + void unlock_loc_vars() { + VTR_ASSERT_SAFE(!loc_vars_are_accessible_); + loc_vars_are_accessible_ = true; + } - ///@brief Stores ClusterBlockId of all movable clustered of each block type - std::vector> movable_blocks_per_type; + /** + * @brief Collection of all the placement macros in the netlist. A placement + * macro is a set of clustered blocks that must be placed in a way + * that is compliant with relative locations specified by the macro. + * Macros are used during placement and are not modified after they + * are created. + * This is created at the start of placement. + */ + std::unique_ptr place_macros; /** * @brief Compressed grid space for each block type @@ -472,7 +564,7 @@ struct RoutingContext : public Context { * @brief User specified routing constraints */ UserRouteConstraints constraints; - + /** Is flat routing enabled? */ bool is_flat; }; @@ -484,6 +576,42 @@ struct RoutingContext : public Context { * to certain regions on the chip. */ struct FloorplanningContext : public Context { + /** + * @brief Update the floorplanning constraints after a clustering has been + * created. + * + * After clustering, the constraints of contained atoms are used to compute + * the constraints of clusters. + * + * This must be called before using the cluster_constraints. + */ + void update_floorplanning_context_post_pack(); + + /** + * @brief Update the floorplanning constraints before placement. + * + * Placement groups clusters together into macros which must be placed + * together. This imposes more constraints onto the clusters which needs to + * be updated. + * + * This must be called before placement, but after the placement context is + * initialized. + * + * @param place_macros + * Macros of clusters which must be placed together. Initialized in the + * placement context. + */ + void update_floorplanning_context_pre_place(const PlaceMacros& place_macros); + + /** + * @brief Clean the floorplanning constraints after placement. + * + * After placement, many of the variables in this class will no longer be + * used (since the placement is no longer changing, the constraints are no + * longer needed). This method will free up the memory used by this class. + */ + void clean_floorplanning_context_post_place(); + /** * @brief Stores groups of constrained atoms, areas where the atoms are constrained to * @@ -524,8 +652,6 @@ struct FloorplanningContext : public Context { * */ std::vector> compressed_cluster_constraints; - - std::vector overfull_partition_regions; }; /** @@ -553,7 +679,7 @@ struct NocContext : public Context { * * Contains all of the traffic flows that describe which pairs of logical routers are * communicating and also some metrics and constraints on the data transfer between the two routers. - * + * * * This is created from a user supplied .flows file. */ diff --git a/vpr/src/base/vpr_signal_handler.cpp b/vpr/src/base/vpr_signal_handler.cpp index 66cb879ff79..9be73206bd1 100644 --- a/vpr/src/base/vpr_signal_handler.cpp +++ b/vpr/src/base/vpr_signal_handler.cpp @@ -21,7 +21,7 @@ #include #ifdef VPR_USE_SIGACTION -# include +#include #endif void vpr_signal_handler(int signal); diff --git a/vpr/src/base/vpr_tatum_error.cpp b/vpr/src/base/vpr_tatum_error.cpp index ea106def804..ed75818444c 100644 --- a/vpr/src/base/vpr_tatum_error.cpp +++ b/vpr/src/base/vpr_tatum_error.cpp @@ -16,19 +16,19 @@ std::string format_tatum_error(const tatum::Error& error) { } if (error.node) { - AtomPinId pin = atom_ctx.lookup.tnode_atom_pin(error.node); + AtomPinId pin = atom_ctx.lookup().tnode_atom_pin(error.node); if (pin) { - msg += "Netlist Pin: '" + atom_ctx.nlist.pin_name(pin) + "', "; + msg += "Netlist Pin: '" + atom_ctx.netlist().pin_name(pin) + "', "; - const t_pb_graph_pin* gpin = atom_ctx.lookup.atom_pin_pb_graph_pin(pin); + const t_pb_graph_pin* gpin = atom_ctx.lookup().atom_pin_pb_graph_pin(pin); if (gpin) { msg += "Graph node pin: '" + gpin->to_string() + "', "; } - AtomBlockId blk = atom_ctx.nlist.pin_block(pin); + AtomBlockId blk = atom_ctx.netlist().pin_block(pin); if (blk) { - msg += "Netlist Block: '" + atom_ctx.nlist.block_name(blk) + "', "; - ClusterBlockId clb_idx = atom_ctx.lookup.atom_clb(blk); + msg += "Netlist Block: '" + atom_ctx.netlist().block_name(blk) + "', "; + ClusterBlockId clb_idx = atom_ctx.lookup().atom_clb(blk); if (clb_idx) { const t_pb* pb = cluster_ctx.clb_nlist.block_pb(clb_idx); if (pb) { @@ -49,18 +49,18 @@ std::string format_tatum_error(const tatum::Error& error) { tatum::NodeId src_node = timing_ctx.graph->edge_src_node(error.edge); tatum::NodeId sink_node = timing_ctx.graph->edge_sink_node(error.edge); - AtomPinId src_pin = atom_ctx.lookup.tnode_atom_pin(src_node); - AtomPinId sink_pin = atom_ctx.lookup.tnode_atom_pin(sink_node); + AtomPinId src_pin = atom_ctx.lookup().tnode_atom_pin(src_node); + AtomPinId sink_pin = atom_ctx.lookup().tnode_atom_pin(sink_node); if (src_pin && sink_pin) { msg += "Between netlist pins "; - msg += "'" + atom_ctx.nlist.pin_name(src_pin) + "' -> '" + atom_ctx.nlist.pin_name(sink_pin) + "'"; + msg += "'" + atom_ctx.netlist().pin_name(src_pin) + "' -> '" + atom_ctx.netlist().pin_name(sink_pin) + "'"; - AtomNetId src_net = atom_ctx.nlist.pin_net(src_pin); - AtomNetId sink_net = atom_ctx.nlist.pin_net(sink_pin); + AtomNetId src_net = atom_ctx.netlist().pin_net(src_pin); + AtomNetId sink_net = atom_ctx.netlist().pin_net(sink_pin); if (src_net && src_net == sink_net) { - msg += " via net '" + atom_ctx.nlist.net_name(src_net) + "'"; + msg += " via net '" + atom_ctx.netlist().net_name(src_net) + "'"; } msg += ", "; diff --git a/vpr/src/base/vpr_types.cpp b/vpr/src/base/vpr_types.cpp index f1401bd5f51..22a644a2d07 100644 --- a/vpr/src/base/vpr_types.cpp +++ b/vpr/src/base/vpr_types.cpp @@ -1,4 +1,5 @@ #include +#include #include "vpr_types.h" #include "globals.h" @@ -451,4 +452,3 @@ BitIndex t_pb::atom_pin_bit_index(const t_pb_graph_pin* gpin) const { void t_pb::set_atom_pin_bit_index(const t_pb_graph_pin* gpin, BitIndex atom_pin_bit_idx) { pin_rotations_[gpin] = atom_pin_bit_idx; } - diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 3a19b6fb06c..44d12cedf36 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -29,6 +29,7 @@ #include #include #include +#include "ap_flow_enums.h" #include "arch_types.h" #include "atom_netlist_fwd.h" #include "clustered_netlist_fwd.h" @@ -92,15 +93,6 @@ constexpr bool VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR = true; constexpr bool VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR = false; #endif -#define MAX_SHORT 32767 - -/* Values large enough to be way out of range for any data, but small enough - * to allow a small number to be added to them without going out of range. */ -#define HUGE_POSITIVE_FLOAT 1.e30 - -/* Used to avoid floating-point errors when comparing values close to 0 */ -#define EPSILON 1.e-15 - /* * Files */ @@ -113,7 +105,7 @@ constexpr bool VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR = false; #define NOT_VALID (-10000) /* Marks gains that aren't valid */ /* Ensure no gain can ever be this negative! */ #ifndef UNDEFINED -# define UNDEFINED (-1) +#define UNDEFINED (-1) #endif ///@brief Router lookahead types. @@ -251,10 +243,8 @@ class t_pack_high_fanout_thresholds { /* these are defined later, but need to declare here because it is used */ class t_rr_node; -class t_pack_molecule; struct t_pb_stats; struct t_pb_route; -struct t_chain_info; typedef vtr::flat_map2 t_pb_routes; @@ -366,74 +356,6 @@ struct t_pb_route { const t_pb_graph_pin* pb_graph_pin = nullptr; ///block_id - * chain_info : if this is a molecule representing a chained pack pattern, this data structure will - * hold the data shared between all molecules forming a chain together. - * num_blocks : maximum number of atom blocks that can fit in this molecule - * root : index of the pack_pattern->root_block in the atom_blocks_ids. root_block_id = atom_block_ids[root] - * base_gain : intrinsic "goodness" score for molecule independent of rest of netlist - * next : next molecule in the linked list - */ -class t_pack_molecule { - public: - /* general molecule info */ - float base_gain; - enum e_pack_pattern_molecule_type type; - - /* large molecules info */ - t_pack_patterns* pack_pattern; - int root; - int num_blocks; - std::vector atom_block_ids; - std::shared_ptr chain_info; - - t_pack_molecule* next; - // a molecule is chain is it is a forced pack and its pack pattern is chain - bool is_chain() const { return type == MOLECULE_FORCED_PACK && pack_pattern->is_chain; } -}; - -/** - * @brief Holds information to be shared between molecules that represent the same chained pack pattern. - * - * For example, molecules that are representing a long carry chain that spans multiple logic blocks. - * - * Data members: - * is_long_chain : is this a long that is divided on multiple clusters (divided on multiple molecules). - * chain_id : is used to access the chain_root_pins vector in the t_pack_patterns of the molecule. To get - * the starting point of this chain in the cluster. This id is useful when we have multiple - * (architectural) carry chains in a logic block, for example. It lets us see which of the chains - * is being used for this long (netlist) chain, so we continue to use that chain in the packing - * of other molecules of this long chain. - * first_packed_molecule : first molecule to be packed out of the molecules forming this chain. This is the molecule - * setting the value of the chain_id. - */ -struct t_chain_info { - bool is_long_chain = false; - int chain_id = -1; - t_pack_molecule* first_packed_molecule = nullptr; -}; - /****************************************************************** * Timing data types *******************************************************************/ @@ -755,6 +677,7 @@ struct t_file_name_opts { std::string read_vpr_constraints_file; std::string write_vpr_constraints_file; std::string write_constraints_file; + std::string read_flat_place_file; std::string write_flat_place_file; std::string write_block_usage; bool verify_file_digests; @@ -794,9 +717,7 @@ struct t_packer_opts { enum e_cluster_seed cluster_seed_type; float alpha; float beta; - float inter_cluster_net_delay; float target_device_utilization; - bool auto_compute_inter_cluster_net_delay; e_unrelated_clustering allow_unrelated_clustering; bool connection_driven; int pack_verbosity; @@ -813,7 +734,7 @@ struct t_packer_opts { bool use_attraction_groups; int pack_num_moves; std::string pack_move_type; - bool load_flat_placement; + bool load_flat_placement = false; }; /** @@ -991,11 +912,6 @@ enum class e_move_type; * @param timing_tradeoff * When in CRITICALITY_TIMING_PLACE mode, what is the * tradeoff between timing and wiring costs. - * @param place_cost_exp - * Wiring cost is divided by the average channel width over - * a net's bounding box taken to this exponent. - * Only impacts devices with different channel widths in - * different directions or regions. (Default: 1) * @param place_chan_width * The channel width assumed if only one placement is performed. * @param pad_loc_type @@ -1043,7 +959,7 @@ enum class e_move_type; struct t_placer_opts { t_place_algorithm place_algorithm; t_place_algorithm place_quench_algorithm; - t_annealing_sched anneal_sched; /// switchblocks; /* Xifan Tang: subtype of switch blocks. @@ -1429,151 +1345,40 @@ struct t_det_routing_arch { bool concat_pass_wire; short global_route_switch; + + /// Index of a zero delay switch (used to connect things that should have no delay). short delayless_switch; + + /// Keeps track of the type of architecture switch that connects wires to ipins int wire_to_arch_ipin_switch; + + /// Keeps track of the type of architecture switch that connects + /// wires from another die to ipins in different die int wire_to_arch_ipin_switch_between_dice = -1; + + /// keeps track of the type of RR graph switch + /// that connects wires to ipins in the RR graph int wire_to_rr_ipin_switch; + + /// keeps track of the type of RR graph switch that connects wires + /// from another die to ipins in different die in the RR graph int wire_to_rr_ipin_switch_between_dice = -1; + + /// Resistance (in Ohms) of a minimum width nmos transistor. + /// Used only in the FPGA area model. float R_minW_nmos; + + /// Resistance (in Ohms) of a minimum width pmos transistor. float R_minW_pmos; + /// File to read the RR graph from (overrides architecture) std::string read_rr_graph_filename; + /// File to write the RR graph to after generation std::string write_rr_graph_filename; + /// File to read the RR graph edge attribute overrides. + std::string read_rr_edge_override_filename; }; -/** - * @brief Lists detailed information about segmentation. [0 .. W-1]. - * - * @param length length of segment. - * @param start index at which a segment starts in channel 0. - * @param longline true if this segment spans the entire channel. - * @param sb [0..length]: true for every channel intersection, relative to the - * segment start, at which there is a switch box. - * @param cb [0..length-1]: true for every logic block along the segment at - * which there is a connection box. - * @param arch_wire_switch Index of the switch type that connects other wires - * *to* this segment. Note that this index is in relation - * to the switches from the architecture file, not the - * expanded list of switches that is built at the end of - * build_rr_graph. - * @param arch_opin_switch Index of the switch type that connects output pins - * (OPINs) *to* this segment. Note that this index is in - * relation to the switches from the architecture file, - * not the expanded list of switches that is is built - * at the end of build_rr_graph - * @param arch_opin_between_dice_switch Index of the switch type that connects output - * pins (OPINs) *to* this segment from *another dice*. - * Note that this index is in relation to the switches from - * the architecture file, not the expanded list of switches that is built - * at the end of build_rr_graph - * @param Cmetal Capacitance of a routing track, per unit logic block length. - * @param Rmetal Resistance of a routing track, per unit logic block length. - * @param direction The direction of a routing track. - * @param index index of the segment type used for this track. - * Note that this index will store the index of the segment - * relative to its **parallel** segment types, not all segments - * as stored in device_ctx. Look in rr_graph.cpp: build_rr_graph - * for details but here is an example: say our segment_inf_vec in - * device_ctx is as follows: [seg_a_x, seg_b_x, seg_a_y, seg_b_y] - * when building the rr_graph, static segment_inf_vectors will be - * created for each direction, thus you will have the following - * 2 vectors: X_vec =[seg_a_x,seg_b_x] and Y_vec = [seg_a_y,seg_b_y]. - * As a result, e.g. seg_b_y::index == 1 (index in Y_vec) - * and != 3 (index in device_ctx segment_inf_vec). - * @param abs_index index is relative to the segment_inf vec as stored in device_ctx. - * Note that the above vector is **unifies** both x-parallel and - * y-parallel segments and is loaded up originally in read_xml_arch_file.cpp - * - * @param type_name_ptr pointer to name of the segment type this track belongs - * to. points to the appropriate name in s_segment_inf - */ -struct t_seg_details { - int length = 0; - int start = 0; - bool longline = false; - std::unique_ptr sb; - std::unique_ptr cb; - short arch_wire_switch = 0; - short arch_opin_switch = 0; - short arch_opin_between_dice_switch = 0; - float Rmetal = 0; - float Cmetal = 0; - bool twisted = false; - enum Direction direction = Direction::NONE; - int group_start = 0; - int group_size = 0; - int seg_start = 0; - int seg_end = 0; - int index = 0; - int abs_index = 0; - float Cmetal_per_m = 0; ///length) - , seg_detail_(init_seg_details) {} - - public: - int length() const { return length_; } - int seg_start() const { return seg_start_; } - int seg_end() const { return seg_end_; } - - int start() const { return seg_detail_->start; } - bool longline() const { return seg_detail_->longline; } - - int group_start() const { return seg_detail_->group_start; } - int group_size() const { return seg_detail_->group_size; } - - bool cb(int pos) const { return seg_detail_->cb[pos]; } - bool sb(int pos) const { return seg_detail_->sb[pos]; } - - float Rmetal() const { return seg_detail_->Rmetal; } - float Cmetal() const { return seg_detail_->Cmetal; } - float Cmetal_per_m() const { return seg_detail_->Cmetal_per_m; } - - short arch_wire_switch() const { return seg_detail_->arch_wire_switch; } - short arch_opin_switch() const { return seg_detail_->arch_opin_switch; } - short arch_opin_between_dice_switch() const { return seg_detail_->arch_opin_between_dice_switch; } - - Direction direction() const { return seg_detail_->direction; } - - int index() const { return seg_detail_->index; } - int abs_index() const { return seg_detail_->abs_index; } - - const vtr::string_view type_name() const { - return vtr::string_view( - seg_detail_->type_name.data(), - seg_detail_->type_name.size()); - } - - public: //Modifiers - void set_length(int new_len) { length_ = new_len; } - void set_seg_start(int new_start) { seg_start_ = new_start; } - void set_seg_end(int new_end) { seg_end_ = new_end; } - - private: - //The only unique information about a channel segment is it's start/end - //and length. All other information is shared across segment types, - //so we use a flyweight to the t_seg_details which defines that info. - // - //To preserve the illusion of uniqueness we wrap all t_seg_details members - //so it appears transparent -- client code of this class doesn't need to - //know about t_seg_details. - int length_ = -1; - int seg_start_ = -1; - int seg_end_ = -1; - const t_seg_details* seg_detail_ = nullptr; -}; - -/* Defines a 3-D array of t_chan_seg_details data structures (one per-each horizontal and vertical channel) - * once allocated in rr_graph2.cpp, is can be accessed like: [0..grid.width()][0..grid.height()][0..num_tracks-1] - */ -typedef vtr::NdMatrix t_chan_details; - constexpr bool is_pin(e_rr_type type) { return (type == IPIN || type == OPIN); } constexpr bool is_chan(e_rr_type type) { return (type == CHANX || type == CHANY); } constexpr bool is_src_sink(e_rr_type type) { return (type == SOURCE || type == SINK); } @@ -1659,7 +1464,7 @@ typedef t_routing_status t_atom_net_routing_status; /** Edge between two RRNodes */ struct t_node_edge { - t_node_edge(RRNodeId fnode, RRNodeId tnode) + t_node_edge(RRNodeId fnode, RRNodeId tnode) noexcept : from_node(fnode) , to_node(tnode) {} @@ -1672,10 +1477,18 @@ struct t_node_edge { } }; -///@brief Non-configurably connected nodes and edges in the RR graph +/** + * @brief Groups of non-configurably connected nodes and edges in the RR graph. + * @note Each group is represented by a node set and an edge set, stored at the same index. + * + * For example, in an architecture with L-shaped wires formed by an x- and y-directed segment + * connected by an electrical short, each L-shaped wire corresponds to a new group. The group's + * index provides access to its node set (containing two RRNodeIds) and edge set (containing two + * directed edge in opposite directions). + */ struct t_non_configurable_rr_sets { - std::set> node_sets; - std::set> edge_sets; + std::vector> node_sets; + std::vector> edge_sets; }; ///@brief Power estimation options @@ -1687,11 +1500,11 @@ struct t_power_opts { * @param max= Maximum channel width between x_max and y_max. * @param x_min= Minimum channel width of horizontal channels. Initialized when init_chan() is invoked in rr_graph2.cpp * @param y_min= Same as above but for vertical channels. - * @param x_max= Maximum channel width of horiozntal channels. Initialized when init_chan() is invoked in rr_graph2.cpp + * @param x_max= Maximum channel width of horizontal channels. Initialized when init_chan() is invoked in rr_graph2.cpp * @param y_max= Same as above but for vertical channels. * @param x_list= Stores the channel width of all horizontal channels and thus goes from [0..grid.height()] * (imagine a 2D Cartesian grid with horizontal lines starting at every grid point on a line parallel to the y-axis) - * @param y_list= Stores the channel width of all verical channels and thus goes from [0..grid.width()] + * @param y_list= Stores the channel width of all vertical channels and thus goes from [0..grid.width()] * (imagine a 2D Cartesian grid with vertical lines starting at every grid point on a line parallel to the x-axis) */ diff --git a/vpr/src/draw/buttons.cpp b/vpr/src/draw/buttons.cpp index ae48bdbc7b9..db64d45c5de 100644 --- a/vpr/src/draw/buttons.cpp +++ b/vpr/src/draw/buttons.cpp @@ -10,16 +10,16 @@ * Last updated: Aug 2019 */ -# include "draw_global.h" -# include "draw.h" -# include "draw_toggle_functions.h" -# include "buttons.h" -# include "intra_logic_block.h" -# include "clustered_netlist.h" +#include "draw_global.h" +#include "draw.h" +#include "draw_toggle_functions.h" +#include "buttons.h" +#include "intra_logic_block.h" +#include "clustered_netlist.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" //location of spin buttons, combo boxes, and labels on grid gint box_width = 1; diff --git a/vpr/src/draw/buttons.h b/vpr/src/draw/buttons.h index 853ad4cb50b..ce7d2910130 100644 --- a/vpr/src/draw/buttons.h +++ b/vpr/src/draw/buttons.h @@ -3,11 +3,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" void delete_button(const char* button_name); GtkWidget* find_button(const char* button_name); diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 46bdd750ca9..5dc0c09523e 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -55,20 +55,20 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" -# include "draw_rr.h" +#if defined(X11) && !defined(__MINGW32__) +#include +#endif + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" +#include "draw_rr.h" /****************************** Define Macros *******************************/ -# define DEFAULT_RR_NODE_COLOR ezgl::BLACK -# define OLD_BLK_LOC_COLOR blk_GOLD -# define NEW_BLK_LOC_COLOR blk_GREEN +#define DEFAULT_RR_NODE_COLOR ezgl::BLACK +#define OLD_BLK_LOC_COLOR blk_GOLD +#define NEW_BLK_LOC_COLOR blk_GREEN //#define TIME_DRAWSCREEN /* Enable if want to track runtime for drawscreen() */ void act_on_key_press(ezgl::application* /*app*/, GdkEventKey* /*event*/, char* key_name); @@ -569,7 +569,7 @@ void init_draw_coords(float clb_width, const BlkLocRegistry& blk_loc_registry) { draw_state->draw_rr_node[inode].node_highlighted = false; } } - draw_coords->tile_width = clb_width; + draw_coords->set_tile_width(clb_width); draw_coords->pin_size = 0.3; for (const auto& type : device_ctx.physical_tile_types) { auto num_pins = type.num_pins; @@ -795,9 +795,9 @@ void act_on_mouse_move(ezgl::application* app, GdkEventButton* /* event */, doub ezgl::point2d atom_pin_draw_coord(AtomPinId pin) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId blk = atom_ctx.nlist.pin_block(pin); - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(blk); - const t_pb_graph_node* pg_gnode = atom_ctx.lookup.atom_pb_graph_node(blk); + AtomBlockId blk = atom_ctx.netlist().pin_block(pin); + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(blk); + const t_pb_graph_node* pg_gnode = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(blk); t_draw_coords* draw_coords = get_draw_coords_vars(); ezgl::rectangle pb_bbox = draw_coords->get_absolute_pb_bbox(clb_index, @@ -1326,7 +1326,7 @@ static void run_graphics_commands(const std::string& commands) { ezgl::point2d tnode_draw_coord(tatum::NodeId node) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomPinId pin = atom_ctx.lookup.tnode_atom_pin(node); + AtomPinId pin = atom_ctx.lookup().tnode_atom_pin(node); return atom_pin_draw_coord(pin); } @@ -1422,7 +1422,7 @@ size_t get_max_fanout() { max_fanout = std::max(max_fanout, clb_nlist.net_sinks(net_id).size()); auto& atom_ctx = g_vpr_ctx.atom(); - auto& atom_nlist = atom_ctx.nlist; + auto& atom_nlist = atom_ctx.netlist(); size_t max_fanout2 = 0; for (AtomNetId net_id : atom_nlist.nets()) max_fanout2 = std::max(max_fanout2, atom_nlist.net_sinks(net_id).size()); diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h index 355b2891931..adfb6fd47be 100644 --- a/vpr/src/draw/draw.h +++ b/vpr/src/draw/draw.h @@ -26,16 +26,16 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" -# include "vtr_ndoffsetmatrix.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" +#include "vtr_ndoffsetmatrix.h" extern ezgl::application::settings settings; extern ezgl::application application; diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 482fbf178e3..2981dd308aa 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -7,9 +7,9 @@ #include #include +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_ndoffsetmatrix.h" -#include "vtr_log.h" #include "vtr_color_map.h" #include "vpr_utils.h" @@ -22,7 +22,6 @@ #include "draw_rr_edges.h" #include "draw_basic.h" #include "draw_triangle.h" -#include "read_xml_arch_file.h" #include "draw_global.h" #include "move_utils.h" #include "route_export.h" @@ -32,19 +31,19 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /****************************** Define Macros *******************************/ -# define DEFAULT_RR_NODE_COLOR ezgl::BLACK -# define OLD_BLK_LOC_COLOR blk_GOLD -# define NEW_BLK_LOC_COLOR blk_GREEN +#define DEFAULT_RR_NODE_COLOR ezgl::BLACK +#define OLD_BLK_LOC_COLOR blk_GOLD +#define NEW_BLK_LOC_COLOR blk_GREEN constexpr float EMPTY_BLOCK_LIGHTEN_FACTOR = 0.20; @@ -239,7 +238,7 @@ void drawnets(ezgl::renderer* g) { ClusterBlockId b2 = cluster_ctx.clb_nlist.pin_block(pin_id); //the layer of the pin block (net sinks) - sink_block_layer_num =block_locs[b2].loc.layer; + sink_block_layer_num = block_locs[b2].loc.layer; t_draw_layer_display element_visibility = get_element_visibility_and_transparency(driver_block_layer_num, sink_block_layer_num); @@ -384,7 +383,7 @@ void draw_routing_costs(ezgl::renderer* g) { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.routing(); g->set_line_width(0); - + VTR_ASSERT(!route_ctx.rr_node_route_inf.empty()); float min_cost = std::numeric_limits::infinity(); @@ -777,7 +776,9 @@ void draw_placement_macros(ezgl::renderer* g) { t_draw_coords* draw_coords = get_draw_coords_vars(); const auto& block_locs = draw_state->get_graphics_blk_loc_registry_ref().block_locs(); - const auto& place_macros = draw_state->get_graphics_blk_loc_registry_ref().place_macros(); + + VTR_ASSERT(g_vpr_ctx.placement().place_macros); + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; for (const t_pl_macro& pl_macro : place_macros.macros()) { @@ -1086,7 +1087,7 @@ void draw_crit_path(ezgl::renderer* g) { /** * @brief Draw critical path elements. - * + * * This function draws critical path elements based on the provided timing paths * and indexes map. It is primarily used in server mode, where items are drawn upon request. */ @@ -1094,19 +1095,19 @@ void draw_crit_path_elements(const std::vector& paths, const t_draw_state* draw_state = get_draw_state_vars(); const ezgl::color contour_color{0, 0, 0, 40}; - auto draw_flyline_timing_edge_helper_fn = [](ezgl::renderer* renderer, const ezgl::color& color, ezgl::line_dash line_style, int line_width, float delay, - const tatum::NodeId& prev_node, const tatum::NodeId& node, bool skip_draw_delays=false) { + auto draw_flyline_timing_edge_helper_fn = [](ezgl::renderer* renderer, const ezgl::color& color, ezgl::line_dash line_style, int line_width, float delay, + const tatum::NodeId& prev_node, const tatum::NodeId& node, bool skip_draw_delays = false) { renderer->set_color(color); renderer->set_line_dash(line_style); renderer->set_line_width(line_width); draw_flyline_timing_edge(tnode_draw_coord(prev_node), - tnode_draw_coord(node), delay, renderer, skip_draw_delays); + tnode_draw_coord(node), delay, renderer, skip_draw_delays); renderer->set_line_dash(ezgl::line_dash::none); - renderer->set_line_width(0); + renderer->set_line_width(0); }; - for (const auto& [path_index, element_indexes]: indexes) { + for (const auto& [path_index, element_indexes] : indexes) { if (path_index < paths.size()) { const tatum::TimingPath& path = paths[path_index]; @@ -1116,7 +1117,7 @@ void draw_crit_path_elements(const std::vector& paths, const int element_counter = 0; for (const tatum::TimingPathElem& elem : path.data_arrival_path().elements()) { bool draw_current_element = element_indexes.empty() || element_indexes.find(element_counter) != element_indexes.end(); - + // draw element tatum::NodeId node = elem.node(); float arr_time = elem.tag().time(); @@ -1131,9 +1132,9 @@ void draw_crit_path_elements(const std::vector& paths, const float delay = arr_time - prev_arr_time; if ((draw_state->show_crit_path == DRAW_CRIT_PATH_FLYLINES) || (draw_state->show_crit_path == DRAW_CRIT_PATH_FLYLINES_DELAYS)) { if (draw_current_element) { - draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::none, /*line_width*/4, delay, prev_node, node); + draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::none, /*line_width*/ 4, delay, prev_node, node); } else if (draw_crit_path_contour) { - draw_flyline_timing_edge_helper_fn(g, contour_color, ezgl::line_dash::none, /*line_width*/1, delay, prev_node, node, /*skip_draw_delays*/true); + draw_flyline_timing_edge_helper_fn(g, contour_color, ezgl::line_dash::none, /*line_width*/ 1, delay, prev_node, node, /*skip_draw_delays*/ true); } } else { VTR_ASSERT(draw_state->show_crit_path != DRAW_NO_CRIT_PATH); @@ -1142,13 +1143,13 @@ void draw_crit_path_elements(const std::vector& paths, const //Draw the routed version of the timing edge draw_routed_timing_edge_connection(prev_node, node, color, g); - draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/3, delay, prev_node, node); + draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/ 3, delay, prev_node, node); } else if (draw_crit_path_contour) { - draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/3, delay, prev_node, node, /*skip_draw_delays*/true); + draw_flyline_timing_edge_helper_fn(g, color, ezgl::line_dash::asymmetric_5_3, /*line_width*/ 3, delay, prev_node, node, /*skip_draw_delays*/ true); } } } - + prev_node = node; prev_arr_time = arr_time; // end draw element @@ -1164,9 +1165,9 @@ int get_timing_path_node_layer_num(tatum::NodeId node) { const auto& block_locs = draw_state->get_graphics_blk_loc_registry_ref().block_locs(); const auto& atom_ctx = g_vpr_ctx.atom(); - AtomPinId atom_pin = atom_ctx.lookup.tnode_atom_pin(node); - AtomBlockId atom_block = atom_ctx.nlist.pin_block(atom_pin); - ClusterBlockId clb_block = atom_ctx.lookup.atom_clb(atom_block); + AtomPinId atom_pin = atom_ctx.lookup().tnode_atom_pin(node); + AtomBlockId atom_block = atom_ctx.netlist().pin_block(atom_pin); + ClusterBlockId clb_block = atom_ctx.lookup().atom_clb(atom_block); return block_locs[clb_block].loc.layer; } @@ -1184,7 +1185,7 @@ bool is_flyline_valid_to_draw(int src_layer, int sink_layer) { } //Draws critical path shown as flylines. -void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g, bool skip_draw_delays/*=false*/) { +void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g, bool skip_draw_delays /*=false*/) { g->draw_line(start, end); draw_triangle_along_line(g, start, end, 0.95, 40 * DEFAULT_ARROW_SIZE); draw_triangle_along_line(g, start, end, 0.05, 40 * DEFAULT_ARROW_SIZE); @@ -1193,7 +1194,7 @@ void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr == DRAW_CRIT_PATH_FLYLINES_DELAYS || get_draw_state_vars()->show_crit_path == DRAW_CRIT_PATH_ROUTING_DELAYS) - && !skip_draw_delays; + && !skip_draw_delays; if (draw_delays) { //Determine the strict bounding box based on the lines start/end float min_x = std::min(start.x, end.x); @@ -1264,8 +1265,8 @@ void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, auto& cluster_ctx = g_vpr_ctx.clustering(); auto& timing_ctx = g_vpr_ctx.timing(); - AtomPinId atom_src_pin = atom_ctx.lookup.tnode_atom_pin(src_tnode); - AtomPinId atom_sink_pin = atom_ctx.lookup.tnode_atom_pin(sink_tnode); + AtomPinId atom_src_pin = atom_ctx.lookup().tnode_atom_pin(src_tnode); + AtomPinId atom_sink_pin = atom_ctx.lookup().tnode_atom_pin(sink_tnode); std::vector points; points.push_back(atom_pin_draw_coord(atom_src_pin)); @@ -1283,16 +1284,16 @@ void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, //TODO: most of this code is highly similar to code in PostClusterDelayCalculator, refactor // into a common method for walking the clustered netlist, this would also (potentially) // allow us to grab the component delays - AtomBlockId atom_src_block = atom_ctx.nlist.pin_block(atom_src_pin); - AtomBlockId atom_sink_block = atom_ctx.nlist.pin_block(atom_sink_pin); + AtomBlockId atom_src_block = atom_ctx.netlist().pin_block(atom_src_pin); + AtomBlockId atom_sink_block = atom_ctx.netlist().pin_block(atom_sink_pin); - ClusterBlockId clb_src_block = atom_ctx.lookup.atom_clb(atom_src_block); + ClusterBlockId clb_src_block = atom_ctx.lookup().atom_clb(atom_src_block); VTR_ASSERT(clb_src_block != ClusterBlockId::INVALID()); - ClusterBlockId clb_sink_block = atom_ctx.lookup.atom_clb( + ClusterBlockId clb_sink_block = atom_ctx.lookup().atom_clb( atom_sink_block); VTR_ASSERT(clb_sink_block != ClusterBlockId::INVALID()); - const t_pb_graph_pin* sink_gpin = atom_ctx.lookup.atom_pin_pb_graph_pin( + const t_pb_graph_pin* sink_gpin = atom_ctx.lookup().atom_pin_pb_graph_pin( atom_sink_pin); VTR_ASSERT(sink_gpin); diff --git a/vpr/src/draw/draw_basic.h b/vpr/src/draw/draw_basic.h index d939b43b8ec..65d42836948 100644 --- a/vpr/src/draw/draw_basic.h +++ b/vpr/src/draw/draw_basic.h @@ -34,11 +34,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" /* Draws the blocks placed on the proper clbs. Occupied blocks are darker colours * * while empty ones are lighter colours and have a dashed border. * @@ -130,7 +130,7 @@ void draw_crit_path_elements(const std::vector& paths, const bool is_flyline_valid_to_draw(int src_layer, int sink_layer); /* Draws critical path shown as flylines. Takes in start and end coordinates, time delay, & renderer.*/ -void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g, bool skip_draw_delays=false); +void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g, bool skip_draw_delays = false); /* Collects all the drawing locations associated with the timing edge between start and end. * Only traces interconnect edges in detail, and treats all others as flylines. diff --git a/vpr/src/draw/draw_color.h b/vpr/src/draw/draw_color.h index f9258dadbef..4dcc5e5dbe8 100644 --- a/vpr/src/draw/draw_color.h +++ b/vpr/src/draw/draw_color.h @@ -10,9 +10,9 @@ #ifndef NO_GRAPHICS -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" static constexpr ezgl::color blk_BISQUE(0xFF, 0xE4, 0xC4); static constexpr ezgl::color blk_LIGHTGREY(0xD3, 0xD3, 0xD3); diff --git a/vpr/src/draw/draw_debug.cpp b/vpr/src/draw/draw_debug.cpp index aeee39b1501..89566863c5e 100644 --- a/vpr/src/draw/draw_debug.cpp +++ b/vpr/src/draw/draw_debug.cpp @@ -46,16 +46,16 @@ void draw_debug_window() { GtkWidget* mainGrid = gtk_grid_new(); gtk_widget_set_margin_top(mainGrid, 30); gtk_widget_set_margin_bottom(mainGrid, 30); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(mainGrid, 30); -# else +#else gtk_widget_set_margin_left(mainGrid, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(mainGrid, 20); -# else +#else gtk_widget_set_margin_right(mainGrid, 20); -# endif +#endif //create all labels GtkWidget* placerOpts = gtk_label_new(NULL); @@ -71,39 +71,39 @@ void draw_debug_window() { gtk_widget_set_margin_top(bplist, 30); GtkWidget* movesLabel = gtk_label_new("Number of moves to proceed"); gtk_widget_set_halign(movesLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(movesLabel, 8); -# else +#else gtk_widget_set_margin_right(movesLabel, 8); -# endif +#endif GtkWidget* tempsLabel = gtk_label_new("Temperatures to proceed:"); gtk_widget_set_halign(tempsLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(tempsLabel, 8); -# else +#else gtk_widget_set_margin_right(tempsLabel, 8); -# endif +#endif GtkWidget* blockLabel = gtk_label_new("Stop at from_block"); gtk_widget_set_halign(blockLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(blockLabel, 8); -# else +#else gtk_widget_set_margin_right(blockLabel, 8); -# endif +#endif GtkWidget* iterLabel = gtk_label_new("Stop at router iteration"); gtk_widget_set_halign(iterLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(iterLabel, 8); -# else +#else gtk_widget_set_margin_right(iterLabel, 8); -# endif +#endif GtkWidget* netLabel = gtk_label_new("Stop at route_net_id"); gtk_widget_set_halign(netLabel, GTK_ALIGN_END); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(netLabel, 8); -# else +#else gtk_widget_set_margin_right(netLabel, 8); -# endif +#endif GtkWidget* star = gtk_label_new("*for handling multiple breakpoints at once using an expression can be more accurate"); gtk_widget_set_margin_top(star, 15); @@ -111,51 +111,51 @@ void draw_debug_window() { GtkWidget* setM = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setM, GTK_ALIGN_START); gtk_widget_set_margin_bottom(setM, 10); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setM, 10); -# else +#else gtk_widget_set_margin_left(setM, 10); -# endif +#endif GtkWidget* setT = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setT, GTK_ALIGN_START); gtk_widget_set_margin_bottom(setT, 10); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setT, 10); -# else +#else gtk_widget_set_margin_left(setT, 10); -# endif +#endif GtkWidget* setB = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setB, GTK_ALIGN_START); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setB, 10); -# else +#else gtk_widget_set_margin_left(setB, 10); -# endif +#endif GtkWidget* setI = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setI, GTK_ALIGN_START); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setI, 10); -# else +#else gtk_widget_set_margin_left(setI, 10); -# endif +#endif GtkWidget* setN = gtk_button_new_with_label("Set"); gtk_widget_set_halign(setN, GTK_ALIGN_START); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(setN, 10); -# else +#else gtk_widget_set_margin_left(setN, 10); -# endif +#endif GtkWidget* advanced = gtk_button_new_with_label("Advanced"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(advanced, 60); -# else +#else gtk_widget_set_margin_left(advanced, 60); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(advanced, 10); -# else +#else gtk_widget_set_margin_right(advanced, 10); -# endif +#endif gtk_widget_set_margin_top(advanced, 20); //create all entries @@ -273,39 +273,39 @@ void advanced_button_callback() { gtk_widget_set_halign(expander, GTK_ALIGN_START); //set margins -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(instructions, 30); -# else +#else gtk_widget_set_margin_left(instructions, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(instructions, 30); -# else +#else gtk_widget_set_margin_right(instructions, 30); -# endif +#endif gtk_widget_set_margin_top(instructions, 30); gtk_widget_set_margin_bottom(instructions, 30); gtk_widget_set_margin_bottom(expression_here, 5); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(entry, 30); -# else +#else gtk_widget_set_margin_left(entry, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(set, 30); -# else +#else gtk_widget_set_margin_right(set, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(set, 40); -# else +#else gtk_widget_set_margin_left(set, 40); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(expander, 10); -# else +#else gtk_widget_set_margin_left(expander, 10); -# endif +#endif gtk_widget_set_margin_top(expander, 20); //grid settings @@ -350,11 +350,11 @@ void refresh_bpList() { if (draw_state->list_of_breakpoints[i].active) gtk_toggle_button_set_active((GtkToggleButton*)checkbox, TRUE); gtk_grid_attach((GtkGrid*)draw_debug_glob_vars.bpGrid, checkbox, 1, i, 1, 1); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(checkbox, 290 - draw_debug_glob_vars.bp_labels[i].size()); -# else +#else gtk_widget_set_margin_left(checkbox, 290 - draw_debug_glob_vars.bp_labels[i].size()); -# endif +#endif gtk_widget_set_halign(checkbox, GTK_ALIGN_END); gtk_widget_set_valign(checkbox, GTK_ALIGN_CENTER); @@ -368,11 +368,11 @@ void refresh_bpList() { gtk_grid_attach((GtkGrid*)draw_debug_glob_vars.bpGrid, deleteButton, 2, i, 1, 1); gtk_widget_set_halign(deleteButton, GTK_ALIGN_END); gtk_widget_set_valign(deleteButton, GTK_ALIGN_CENTER); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(deleteButton, 10); -# else +#else gtk_widget_set_margin_left(deleteButton, 10); -# endif +#endif gtk_widget_show_all(draw_debug_glob_vars.bpGrid); } @@ -393,11 +393,11 @@ void add_to_bpList(std::string bpDescription) { gtk_widget_set_name(checkbox, c.c_str()); gtk_toggle_button_set_active((GtkToggleButton*)checkbox, TRUE); gtk_grid_attach((GtkGrid*)draw_debug_glob_vars.bpGrid, checkbox, 1, draw_debug_glob_vars.bpList_row, 1, 1); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(checkbox, 290 - bpDescription.size()); -# else +#else gtk_widget_set_margin_left(checkbox, 290 - bpDescription.size()); -# endif +#endif gtk_widget_set_halign(checkbox, GTK_ALIGN_END); gtk_widget_set_valign(checkbox, GTK_ALIGN_CENTER); @@ -411,11 +411,11 @@ void add_to_bpList(std::string bpDescription) { gtk_grid_attach((GtkGrid*)draw_debug_glob_vars.bpGrid, deleteButton, 2, draw_debug_glob_vars.bpList_row, 1, 1); gtk_widget_set_halign(deleteButton, GTK_ALIGN_END); gtk_widget_set_valign(deleteButton, GTK_ALIGN_CENTER); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(deleteButton, 10); -# else +#else gtk_widget_set_margin_left(deleteButton, 10); -# endif +#endif gtk_widget_show_all(draw_debug_glob_vars.bpGrid); } @@ -539,16 +539,16 @@ void invalid_breakpoint_entry_window(std::string error) { //label settings GtkWidget* label = gtk_label_new(error.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(label, 30); -# else +#else gtk_widget_set_margin_left(label, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(label, 30); -# else +#else gtk_widget_set_margin_right(label, 30); -# endif +#endif gtk_widget_set_margin_top(label, 30); gtk_widget_set_margin_bottom(label, 30); gtk_grid_attach((GtkGrid*)grid, label, 0, 0, 1, 1); @@ -556,16 +556,16 @@ void invalid_breakpoint_entry_window(std::string error) { //button settings GtkWidget* button = gtk_button_new_with_label("OK"); gtk_widget_set_margin_bottom(button, 30); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(button, 30); -# else +#else gtk_widget_set_margin_right(button, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(button, 30); -# else +#else gtk_widget_set_margin_left(button, 30); -# endif +#endif gtk_grid_attach((GtkGrid*)grid, button, 0, 1, 1, 1); g_signal_connect(button, "clicked", G_CALLBACK(ok_close_window), window); @@ -586,47 +586,47 @@ void breakpoint_info_window(std::string bpDescription, BreakpointState draw_brea //label settings GtkWidget* label = gtk_label_new(bpDescription.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(label, 30); -# else +#else gtk_widget_set_margin_left(label, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(label, 30); -# else +#else gtk_widget_set_margin_right(label, 30); -# endif +#endif gtk_widget_set_margin_top(label, 30); gtk_widget_set_margin_bottom(label, 30); gtk_grid_attach((GtkGrid*)grid, label, 0, 0, 1, 1); GtkWidget* curr_info = gtk_label_new(NULL); gtk_label_set_markup((GtkLabel*)curr_info, "Current Information"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(curr_info, 30); -# else +#else gtk_widget_set_margin_left(curr_info, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(curr_info, 30); -# else +#else gtk_widget_set_margin_right(curr_info, 30); -# endif +#endif gtk_widget_set_margin_bottom(curr_info, 15); gtk_grid_attach((GtkGrid*)grid, curr_info, 0, 1, 1, 1); //info grid GtkWidget* info_grid = gtk_grid_new(); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(info_grid, 30); -# else +#else gtk_widget_set_margin_left(info_grid, 30); -# endif -# if GTK_CHECK_VERSION(3, 12, 0) +#endif +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_end(info_grid, 30); -# else +#else gtk_widget_set_margin_right(info_grid, 30); -# endif +#endif gtk_widget_set_margin_bottom(info_grid, 20); //images @@ -634,67 +634,67 @@ void breakpoint_info_window(std::string bpDescription, BreakpointState draw_brea GtkWidget* t = gtk_image_new_from_file("src/draw/t.png"); GtkWidget* r = gtk_image_new_from_file("src/draw/r.png"); GtkWidget* n = gtk_image_new_from_file("src/draw/n.png"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(n, 18); -# else +#else gtk_widget_set_margin_left(n, 18); -# endif +#endif GtkWidget* i = gtk_image_new_from_file("src/draw/i.png"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(i, 16); -# else +#else gtk_widget_set_margin_left(i, 16); -# endif +#endif GtkWidget* b = gtk_image_new_from_file("src/draw/b.png"); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(b, 18); -# else +#else gtk_widget_set_margin_left(b, 18); -# endif +#endif //info grid labels std::string move_num = "move_num: " + std::to_string(draw_breakpoint_state.move_num); GtkWidget* move_info = gtk_label_new(move_num.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(move_info, 5); -# else +#else gtk_widget_set_margin_left(move_info, 5); -# endif +#endif gtk_widget_set_halign(move_info, GTK_ALIGN_START); std::string temp_count = "temp_count: " + std::to_string(draw_breakpoint_state.temp_count); GtkWidget* temp_info = gtk_label_new(temp_count.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(temp_info, 5); -# else +#else gtk_widget_set_margin_left(temp_info, 5); -# endif +#endif gtk_widget_set_halign(temp_info, GTK_ALIGN_START); std::string in_blocks_affected = "in_blocks_affected: " + std::to_string(get_bp_state_globals()->get_glob_breakpoint_state()->block_affected); GtkWidget* ba_info = gtk_label_new(in_blocks_affected.c_str()); gtk_widget_set_halign(ba_info, GTK_ALIGN_START); std::string block_id = "from_block: " + std::to_string(draw_breakpoint_state.from_block); GtkWidget* block_info = gtk_label_new(block_id.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(block_info, 5); -# else +#else gtk_widget_set_margin_left(block_info, 5); -# endif +#endif gtk_widget_set_halign(block_info, GTK_ALIGN_START); std::string router_iter = "router_iter: " + std::to_string(draw_breakpoint_state.router_iter); GtkWidget* ri_info = gtk_label_new(router_iter.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(ri_info, 5); -# else +#else gtk_widget_set_margin_left(ri_info, 5); -# endif +#endif gtk_widget_set_halign(ri_info, GTK_ALIGN_START); std::string net_id = "rouet_net_id: " + std::to_string(draw_breakpoint_state.route_net_id); GtkWidget* net_info = gtk_label_new(net_id.c_str()); -# if GTK_CHECK_VERSION(3, 12, 0) +#if GTK_CHECK_VERSION(3, 12, 0) gtk_widget_set_margin_start(net_info, 5); -# else +#else gtk_widget_set_margin_left(net_info, 5); -# endif +#endif gtk_widget_set_halign(net_info, GTK_ALIGN_START); //attach to grid diff --git a/vpr/src/draw/draw_debug.h b/vpr/src/draw/draw_debug.h index c88f146cdb8..f79d7740d7b 100644 --- a/vpr/src/draw/draw_debug.h +++ b/vpr/src/draw/draw_debug.h @@ -9,19 +9,19 @@ #ifndef NO_GRAPHICS -# include "breakpoint.h" -# include "draw_global.h" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "breakpoint.h" +#include "draw_global.h" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" -# include -# include -# include -# include -# include -# include -# include -# include +#include +#include +#include +#include +#include +#include +#include +#include /** debugger functions **/ void draw_debug_window(); diff --git a/vpr/src/draw/draw_floorplanning.cpp b/vpr/src/draw/draw_floorplanning.cpp index 9e56cfda5ac..e22c6446f7a 100644 --- a/vpr/src/draw/draw_floorplanning.cpp +++ b/vpr/src/draw/draw_floorplanning.cpp @@ -18,13 +18,16 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif -static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* current_pb, - const t_pb* pb_to_draw, const ezgl::rectangle& parent_bbox, - const t_logical_block_type_ptr type, ezgl::color color, +static void draw_internal_pb(const ClusterBlockId clb_index, + t_pb* current_pb, + const t_pb* pb_to_draw, + const ezgl::rectangle& parent_bbox, + const t_logical_block_type_ptr type, + ezgl::color color, ezgl::renderer* g); const std::vector kelly_max_contrast_colors_no_black = { @@ -52,8 +55,8 @@ const std::vector kelly_max_contrast_colors_no_black = { ezgl::color(43, 61, 38) //olive green }; -# define DEFAULT_HIGHLIGHT_ALPHA 30 -# define CLICKED_HIGHLIGHT_ALPHA 100 +#define DEFAULT_HIGHLIGHT_ALPHA 30 +#define CLICKED_HIGHLIGHT_ALPHA 100 //Keeps track of how translucent each partition should be drawn on screen. static std::vector highlight_alpha; @@ -149,10 +152,10 @@ void draw_constrained_atoms(ezgl::renderer* g) { auto atoms = constraints.get_part_atoms((PartitionId)partitionID); for (const AtomBlockId atom_id : atoms) { - if (atom_ctx.lookup.atom_pb(atom_id) != nullptr) { - const t_pb* pb = atom_ctx.lookup.atom_pb(atom_id); + if (atom_ctx.lookup().atom_pb_bimap().atom_pb(atom_id) != nullptr) { + const t_pb* pb = atom_ctx.lookup().atom_pb_bimap().atom_pb(atom_id); auto color = kelly_max_contrast_colors_no_black[partitionID % (kelly_max_contrast_colors_no_black.size())]; - ClusterBlockId clb_index = atom_ctx.lookup.atom_clb(atom_id); + ClusterBlockId clb_index = atom_ctx.lookup().atom_clb(atom_id); auto type = cluster_ctx.clb_nlist.block_type(clb_index); draw_internal_pb(clb_index, cluster_ctx.clb_nlist.block_pb(clb_index), pb, ezgl::rectangle({0, 0}, 0, 0), type, color, g); @@ -167,7 +170,8 @@ static void draw_internal_pb(const ClusterBlockId clb_index, const t_pb* pb_to_draw, const ezgl::rectangle& parent_bbox, const t_logical_block_type_ptr type, - ezgl::color color, ezgl::renderer* g) { + ezgl::color color, + ezgl::renderer* g) { t_draw_coords* draw_coords = get_draw_coords_vars(); t_draw_state* draw_state = get_draw_state_vars(); @@ -306,7 +310,7 @@ static GtkTreeModel* create_and_fill_model() { -1); for (AtomBlockId const_atom : atoms) { - std::string atom_name = (atom_ctx.lookup.atom_pb(const_atom))->name; + std::string atom_name = (atom_ctx.lookup().atom_pb_bimap().atom_pb(const_atom))->name; gtk_tree_store_append(store, &child_iter, &iter); gtk_tree_store_set(store, &child_iter, COL_NAME, atom_name.c_str(), diff --git a/vpr/src/draw/draw_floorplanning.h b/vpr/src/draw/draw_floorplanning.h index f45b398e4d8..feae6ec127c 100644 --- a/vpr/src/draw/draw_floorplanning.h +++ b/vpr/src/draw/draw_floorplanning.h @@ -6,11 +6,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" ///@brief Iterates through all partitions described in the constraints file and highlights their respective partitions void highlight_all_regions(ezgl::renderer* g); diff --git a/vpr/src/draw/draw_global.cpp b/vpr/src/draw/draw_global.cpp index 391b659bbcf..9fc5e0b5834 100644 --- a/vpr/src/draw/draw_global.cpp +++ b/vpr/src/draw/draw_global.cpp @@ -12,8 +12,8 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" -# include "draw_types.h" +#include "draw_global.h" +#include "draw_types.h" /*************************** Variables Definition ***************************/ diff --git a/vpr/src/draw/draw_global.h b/vpr/src/draw/draw_global.h index f1eec3967f5..e53b628cc73 100644 --- a/vpr/src/draw/draw_global.h +++ b/vpr/src/draw/draw_global.h @@ -15,13 +15,13 @@ #ifndef NO_GRAPHICS -# include "draw_types.h" +#include "draw_types.h" constexpr float DEFAULT_ARROW_SIZE = 0.3; // a very small area, in (screen pixels)^2 // used for level of detail culling -# define MIN_VISIBLE_AREA 3.0 +#define MIN_VISIBLE_AREA 3.0 t_draw_coords* get_draw_coords_vars(); diff --git a/vpr/src/draw/draw_mux.cpp b/vpr/src/draw/draw_mux.cpp index e83fde50296..7d03e2f468b 100644 --- a/vpr/src/draw/draw_mux.cpp +++ b/vpr/src/draw/draw_mux.cpp @@ -14,9 +14,9 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif //#define TIME_DRAWSCREEN /* Enable if want to track runtime for drawscreen() */ diff --git a/vpr/src/draw/draw_mux.h b/vpr/src/draw/draw_mux.h index dbfcf2b4d30..cb62427f339 100644 --- a/vpr/src/draw/draw_mux.h +++ b/vpr/src/draw/draw_mux.h @@ -31,11 +31,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" /** * @brief Draws a mux with width = height * 0.4 and scale (slope of the muxes sides) = 0.6, labelled with its size. diff --git a/vpr/src/draw/draw_noc.cpp b/vpr/src/draw/draw_noc.cpp index d112cb7cae5..a988d7b4d65 100644 --- a/vpr/src/draw/draw_noc.cpp +++ b/vpr/src/draw/draw_noc.cpp @@ -1,12 +1,12 @@ #ifndef NO_GRAPHICS -# include "draw_noc.h" -# include "globals.h" -# include "noc_storage.h" -# include "vpr_error.h" -# include "vtr_math.h" -# include "draw_basic.h" +#include "draw_basic.h" +#include "draw_noc.h" +#include "globals.h" +#include "noc_storage.h" +#include "physical_types_util.h" +#include "vtr_math.h" void draw_noc(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); @@ -475,4 +475,4 @@ void shift_noc_link(noc_link_draw_coords& link_coords, NocLinkShift link_shift_d } } -#endif \ No newline at end of file +#endif diff --git a/vpr/src/draw/draw_noc.h b/vpr/src/draw/draw_noc.h index f3de82a3e3b..e24ae6b1db2 100644 --- a/vpr/src/draw/draw_noc.h +++ b/vpr/src/draw/draw_noc.h @@ -29,7 +29,7 @@ #ifndef NO_GRAPHICS -# include "draw.h" +#include "draw.h" // defines the area of the marker that represents connection points between links // area is equivalent to the %x of the area of the router @@ -243,4 +243,4 @@ void shift_noc_link(noc_link_draw_coords& link_coords, NocLinkShift link_shift_d #endif -#endif \ No newline at end of file +#endif diff --git a/vpr/src/draw/draw_rr.cpp b/vpr/src/draw/draw_rr.cpp index 62534bb0cc3..a47c76d3032 100644 --- a/vpr/src/draw/draw_rr.cpp +++ b/vpr/src/draw/draw_rr.cpp @@ -28,12 +28,12 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif /****************************** Define Macros *******************************/ -# define DEFAULT_RR_NODE_COLOR ezgl::BLACK +#define DEFAULT_RR_NODE_COLOR ezgl::BLACK //The arrow head position for turning/straight-thru connections in a switch box constexpr float SB_EDGE_TURN_ARROW_POSITION = 0.2; diff --git a/vpr/src/draw/draw_rr.h b/vpr/src/draw/draw_rr.h index 7ed40ffd61b..9c19f6bc951 100644 --- a/vpr/src/draw/draw_rr.h +++ b/vpr/src/draw/draw_rr.h @@ -32,20 +32,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /* Draws the routing resources that exist in the FPGA, if the user wants * * them drawn. */ diff --git a/vpr/src/draw/draw_rr_edges.cpp b/vpr/src/draw/draw_rr_edges.cpp index 0815be661a6..793487d04ab 100644 --- a/vpr/src/draw/draw_rr_edges.cpp +++ b/vpr/src/draw/draw_rr_edges.cpp @@ -1,20 +1,17 @@ /*draw_rr_edges.cpp contains all functions that draw lines between RR nodes.*/ #include +#include "physical_types_util.h" #include "vtr_assert.h" -#include "vtr_color_map.h" #include "vpr_utils.h" #include "vpr_error.h" #include "globals.h" -#include "draw_color.h" -#include "draw.h" #include "draw_rr.h" #include "draw_rr_edges.h" #include "draw_triangle.h" #include "draw_searchbar.h" -#include "read_xml_arch_file.h" #include "draw_global.h" #include "draw_basic.h" @@ -22,9 +19,9 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); @@ -184,7 +181,7 @@ void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, short switch + draw_coords->get_tile_width(); x2 = to_chan.left(); - } /* The following then is executed when from_xlow == to_xlow */ + } /* The following then is executed when from_xlow == to_xlow */ else if (to_xhigh > from_xhigh) { /* Draw from right edge of one to other */ x1 = from_chan.right(); x2 = draw_coords->tile_x[from_xhigh + 1]; diff --git a/vpr/src/draw/draw_rr_edges.h b/vpr/src/draw/draw_rr_edges.h index 9068b31b4fe..8ea7a383dcb 100644 --- a/vpr/src/draw/draw_rr_edges.h +++ b/vpr/src/draw/draw_rr_edges.h @@ -32,20 +32,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g); void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, short switch_type, ezgl::renderer* g); diff --git a/vpr/src/draw/draw_searchbar.cpp b/vpr/src/draw/draw_searchbar.cpp index a90583f42ce..270435fe04f 100644 --- a/vpr/src/draw/draw_searchbar.cpp +++ b/vpr/src/draw/draw_searchbar.cpp @@ -1,18 +1,16 @@ /*draw_searchbar.cpp contains all functions related to searchbar actions.*/ #include -#include #include "netlist_fwd.h" +#include "physical_types_util.h" #include "vpr_utils.h" #include "globals.h" -#include "draw_color.h" #include "draw.h" #include "draw_rr.h" #include "draw_basic.h" #include "draw_searchbar.h" -#include "read_xml_arch_file.h" #include "draw_global.h" #include "intra_logic_block.h" @@ -20,13 +18,13 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif /****************************** Define Macros *******************************/ -# define DEFAULT_RR_NODE_COLOR ezgl::BLACK +#define DEFAULT_RR_NODE_COLOR ezgl::BLACK /* This function computes and returns the boundary coordinates of a channel * wire segment. This can be used for drawing a wire or determining if a @@ -144,7 +142,7 @@ void highlight_nets(char* message, RRNodeId hit_node, bool is_flat) { t_draw_state* draw_state = get_draw_state_vars(); for (auto net_id : cluster_ctx.clb_nlist.nets()) { - ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net_id, is_flat); + ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net_id, is_flat); if (!route_ctx.route_trees[parent_id]) continue; diff --git a/vpr/src/draw/draw_searchbar.h b/vpr/src/draw/draw_searchbar.h index e4dade9bb58..25a135be153 100644 --- a/vpr/src/draw/draw_searchbar.h +++ b/vpr/src/draw/draw_searchbar.h @@ -33,20 +33,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /* This function computes and returns the boundary coordinates of a channel * wire segment. This can be used for drawing a wire or determining if a diff --git a/vpr/src/draw/draw_toggle_functions.cpp b/vpr/src/draw/draw_toggle_functions.cpp index 968808c2906..ddd518cf4a5 100644 --- a/vpr/src/draw/draw_toggle_functions.cpp +++ b/vpr/src/draw/draw_toggle_functions.cpp @@ -18,9 +18,9 @@ //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif //The arrow head position for turning/straight-thru connections in a switch box constexpr float SB_EDGE_TURN_ARROW_POSITION = 0.2; diff --git a/vpr/src/draw/draw_toggle_functions.h b/vpr/src/draw/draw_toggle_functions.h index 7b8330396b7..e6c9114900e 100644 --- a/vpr/src/draw/draw_toggle_functions.h +++ b/vpr/src/draw/draw_toggle_functions.h @@ -38,20 +38,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" - -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "draw_global.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" + +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /* Callback function for main.ui created toggle_nets button in ui_setup.cpp. Controls whether or not nets are visualized. * Toggles value of draw_state->show_nets.*/ diff --git a/vpr/src/draw/draw_triangle.cpp b/vpr/src/draw/draw_triangle.cpp index 82b5bd45376..83ccd1af7f1 100644 --- a/vpr/src/draw/draw_triangle.cpp +++ b/vpr/src/draw/draw_triangle.cpp @@ -7,14 +7,13 @@ #include "draw_triangle.h" #include "draw_global.h" - #ifndef NO_GRAPHICS //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif /** * Retrieves the current zoom level based on the visible world and screen dimensions. diff --git a/vpr/src/draw/draw_triangle.h b/vpr/src/draw/draw_triangle.h index 0ddf12218ec..9c0116f0c5a 100644 --- a/vpr/src/draw/draw_triangle.h +++ b/vpr/src/draw/draw_triangle.h @@ -33,20 +33,20 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" -# include "search_bar.h" -# include "draw_debug.h" -# include "manual_moves.h" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" +#include "search_bar.h" +#include "draw_debug.h" +#include "manual_moves.h" -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" -# include "buttons.h" +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" +#include "buttons.h" /** * Retrieves the current zoom level based on the visible world and screen dimensions. diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index b3909c5fd7c..03940843648 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -1,12 +1,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" -# include "draw_types.h" -# include "draw_toggle_functions.h" -# include "globals.h" -# include "vpr_utils.h" -# include "draw.h" -# include +#include "draw.h" +#include "draw_global.h" +#include "draw_types.h" +#include "globals.h" +#include "physical_types_util.h" +#include "vpr_utils.h" /******************************************* * begin t_draw_state function definitions * diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index 1f6689e63f4..8d96ceaf732 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -20,20 +20,20 @@ #ifndef NO_GRAPHICS -# include -# include -# include "clustered_netlist.h" -# include "timing_info_fwd.h" -# include "vtr_util.h" -# include "vpr_types.h" -# include "vtr_color_map.h" -# include "vtr_vector.h" -# include "breakpoint.h" -# include "manual_moves.h" - -# include "ezgl/point.hpp" -# include "ezgl/rectangle.hpp" -# include "ezgl/color.hpp" +#include +#include +#include "clustered_netlist.h" +#include "timing_info_fwd.h" +#include "vtr_util.h" +#include "vpr_types.h" +#include "vtr_color_map.h" +#include "vtr_vector.h" +#include "breakpoint.h" +#include "manual_moves.h" + +#include "ezgl/point.hpp" +#include "ezgl/rectangle.hpp" +#include "ezgl/color.hpp" enum e_draw_crit_path { DRAW_NO_CRIT_PATH, @@ -410,6 +410,11 @@ struct t_draw_coords { ///@brief constructor t_draw_coords(); + ///@brief Sets the tile width + inline void set_tile_width(float new_tile_width) { + tile_width = new_tile_width; + } + ///@brief returns tile width float get_tile_width(); diff --git a/vpr/src/draw/gtkcomboboxhelper.cpp b/vpr/src/draw/gtkcomboboxhelper.cpp index 6da464289ca..4892fb0afc3 100644 --- a/vpr/src/draw/gtkcomboboxhelper.cpp +++ b/vpr/src/draw/gtkcomboboxhelper.cpp @@ -58,4 +58,4 @@ gint get_item_index_by_text(gpointer combo_box, const gchar* target_item) { return result_index; } -#endif // NO_GRAPHICS \ No newline at end of file +#endif // NO_GRAPHICS diff --git a/vpr/src/draw/hsl.cpp b/vpr/src/draw/hsl.cpp index b5f8403e724..4a909e77252 100644 --- a/vpr/src/draw/hsl.cpp +++ b/vpr/src/draw/hsl.cpp @@ -1,8 +1,8 @@ #ifndef NO_GRAPHICS -# include +#include -# include "hsl.h" +#include "hsl.h" float hue2rgb(float v1, float v2, float vH); diff --git a/vpr/src/draw/hsl.h b/vpr/src/draw/hsl.h index e7d6d4508d2..589266bc6e4 100644 --- a/vpr/src/draw/hsl.h +++ b/vpr/src/draw/hsl.h @@ -9,7 +9,7 @@ #ifndef NO_GRAPHICS -# include "ezgl/color.hpp" +#include "ezgl/color.hpp" struct hsl { double h; // hue a fraction between 0 and 1 diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index c1ee67c7590..375eee6f151 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -20,21 +20,21 @@ #ifndef NO_GRAPHICS -# include -# include -# include - -# include "vtr_assert.h" -# include "vtr_memory.h" - -# include "intra_logic_block.h" -# include "globals.h" -# include "atom_netlist.h" -# include "vpr_utils.h" -# include "draw_global.h" -# include "draw.h" -# include "draw_triangle.h" -# include "draw_color.h" +#include +#include +#include + +#include "vtr_assert.h" +#include "vtr_memory.h" + +#include "intra_logic_block.h" +#include "globals.h" +#include "atom_netlist.h" +#include "vpr_utils.h" +#include "draw_global.h" +#include "draw.h" +#include "draw_triangle.h" +#include "draw_color.h" /************************* Subroutines local to this file. *******************************/ @@ -45,12 +45,12 @@ std::vector collect_pb_atoms(const t_pb* pb); void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms); t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const ezgl::point2d& local_pt, int max_depth); -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezgl::rectangle& parent_bbox, const t_logical_block_type_ptr type, ezgl::renderer* g); void draw_atoms_fanin_fanout_flylines(const std::vector& atoms, ezgl::renderer* g); void draw_selected_pb_flylines(ezgl::renderer* g); void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_pin, ezgl::renderer* g); -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ /************************* Subroutine definitions begin *********************************/ @@ -141,7 +141,7 @@ void draw_internal_init_blk() { //draw_state->max_sub_blk_lvl -= 1; } -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS void draw_internal_draw_subblk(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); if (!draw_state->show_blk_internal) { @@ -192,7 +192,7 @@ void draw_internal_draw_subblk(ezgl::renderer* g) { //(inputs: blue, outputs: red, internal: orange) draw_selected_pb_flylines(g); } -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ /* This function traverses through the pb_graph of a certain physical block type and * finds the maximum sub-block levels for that type. @@ -326,7 +326,7 @@ draw_internal_calc_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node *blk_height = child_height; } -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS /* Helper subroutine to draw all sub-blocks. This function traverses through the pb_graph * which a netlist block can map to, and draws each sub-block inside its parent block. With * each click on the "Blk Internal" button, a new level is shown. @@ -471,7 +471,7 @@ void draw_selected_pb_flylines(ezgl::renderer* g) { void draw_atoms_fanin_fanout_flylines(const std::vector& atoms, ezgl::renderer* g) { std::set atoms_set(atoms.begin(), atoms.end()); - auto& atom_nl = g_vpr_ctx.atom().nlist; + auto& atom_nl = g_vpr_ctx.atom().netlist(); g->set_line_dash(ezgl::line_dash::none); g->set_line_width(2); @@ -517,7 +517,7 @@ void draw_atoms_fanin_fanout_flylines(const std::vector& atoms, ezg } } } -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ std::vector collect_pb_atoms(const t_pb* pb) { std::vector atoms; @@ -530,13 +530,13 @@ void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms) { if (pb->is_primitive()) { //Base case - AtomBlockId blk = atom_ctx.lookup.pb_atom(pb); + AtomBlockId blk = atom_ctx.lookup().atom_pb_bimap().pb_atom(pb); if (blk) { atoms.push_back(blk); } } else { //Recurse - VTR_ASSERT_DEBUG(atom_ctx.lookup.pb_atom(pb) == AtomBlockId::INVALID()); + VTR_ASSERT_DEBUG(atom_ctx.lookup().atom_pb_bimap().pb_atom(pb) == AtomBlockId::INVALID()); for (int itype = 0; itype < pb->get_num_child_types(); ++itype) { for (int ichild = 0; ichild < pb->get_num_children_of_type(itype); ++ichild) { @@ -546,7 +546,7 @@ void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms) { } } -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS void draw_logical_connections(ezgl::renderer* g) { const t_selected_sub_block_info& sel_subblk_info = get_selected_sub_block_info(); t_draw_state* draw_state = get_draw_state_vars(); @@ -560,14 +560,14 @@ void draw_logical_connections(ezgl::renderer* g) { int transparency_factor; // iterate over all the atom nets - for (auto net_id : atom_ctx.nlist.nets()) { - if ((int)atom_ctx.nlist.net_pins(net_id).size() - 1 > draw_state->draw_net_max_fanout) { + for (auto net_id : atom_ctx.netlist().nets()) { + if ((int)atom_ctx.netlist().net_pins(net_id).size() - 1 > draw_state->draw_net_max_fanout) { continue; } - AtomPinId driver_pin_id = atom_ctx.nlist.net_driver(net_id); - AtomBlockId src_blk_id = atom_ctx.nlist.pin_block(driver_pin_id); - ClusterBlockId src_clb = atom_ctx.lookup.atom_clb(src_blk_id); + AtomPinId driver_pin_id = atom_ctx.netlist().net_driver(net_id); + AtomBlockId src_blk_id = atom_ctx.netlist().pin_block(driver_pin_id); + ClusterBlockId src_clb = atom_ctx.lookup().atom_clb(src_blk_id); int src_layer_num = block_locs[src_clb].loc.layer; //To only show primitive nets that are connected to currently active layers on the screen @@ -575,15 +575,15 @@ void draw_logical_connections(ezgl::renderer* g) { continue; /* Don't Draw */ } - const t_pb_graph_node* src_pb_gnode = atom_ctx.lookup.atom_pb_graph_node(src_blk_id); + const t_pb_graph_node* src_pb_gnode = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(src_blk_id); bool src_is_selected = sel_subblk_info.is_in_selected_subtree(src_pb_gnode, src_clb); bool src_is_src_of_selected = sel_subblk_info.is_source_of_selected(src_pb_gnode, src_clb); // iterate over the sinks - for (auto sink_pin_id : atom_ctx.nlist.net_sinks(net_id)) { - AtomBlockId sink_blk_id = atom_ctx.nlist.pin_block(sink_pin_id); - const t_pb_graph_node* sink_pb_gnode = atom_ctx.lookup.atom_pb_graph_node(sink_blk_id); - ClusterBlockId sink_clb = atom_ctx.lookup.atom_clb(sink_blk_id); + for (auto sink_pin_id : atom_ctx.netlist().net_sinks(net_id)) { + AtomBlockId sink_blk_id = atom_ctx.netlist().pin_block(sink_pin_id); + const t_pb_graph_node* sink_pb_gnode = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(sink_blk_id); + ClusterBlockId sink_clb = atom_ctx.lookup().atom_clb(sink_blk_id); int sink_layer_num = block_locs[sink_clb].loc.layer; t_draw_layer_display element_visibility = get_element_visibility_and_transparency(src_layer_num, sink_layer_num); @@ -610,7 +610,7 @@ void draw_logical_connections(ezgl::renderer* g) { } } } -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ /** * Helper function for draw_one_logical_connection(...). @@ -627,21 +627,21 @@ void draw_logical_connections(ezgl::renderer* g) { void find_pin_index_at_model_scope(const AtomPinId pin_id, const AtomBlockId blk_id, int* pin_index, int* total_pins) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id); - const t_model_ports* model_port = atom_ctx.nlist.port_model(port_id); + AtomPortId port_id = atom_ctx.netlist().pin_port(pin_id); + const t_model_ports* model_port = atom_ctx.netlist().port_model(port_id); //Total up the port widths // Note that we do this on the model since the atom netlist doesn't include unused ports int pin_cnt = 0; *pin_index = -1; //initialize - const t_model* model = atom_ctx.nlist.block_model(blk_id); + const t_model* model = atom_ctx.netlist().block_model(blk_id); for (const t_model_ports* port : {model->inputs, model->outputs}) { while (port) { if (port == model_port) { //This is the port the pin is associated with, record it's index //Get the pin index in the port - int atom_port_index = atom_ctx.nlist.pin_port_bit(pin_id); + int atom_port_index = atom_ctx.netlist().pin_port_bit(pin_id); //The index of this pin in the model is the pins counted so-far //(i.e. across previous ports) plus the index in the port @@ -660,7 +660,7 @@ void find_pin_index_at_model_scope(const AtomPinId pin_id, const AtomBlockId blk *total_pins = pin_cnt; } -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS /** * Draws ONE logical connection from src_pin in src_lblk to sink_pin in sink_lblk. * The *_abs_bbox parameters are for mild optimization, as the absolute bbox can be calculated @@ -674,7 +674,7 @@ void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_p g->draw_line(src_point, sink_point); const auto& atom_ctx = g_vpr_ctx.atom(); - if (atom_ctx.lookup.atom_clb(atom_ctx.nlist.pin_block(src_pin)) == atom_ctx.lookup.atom_clb(atom_ctx.nlist.pin_block(sink_pin))) { + if (atom_ctx.lookup().atom_clb(atom_ctx.netlist().pin_block(src_pin)) == atom_ctx.lookup().atom_clb(atom_ctx.netlist().pin_block(sink_pin))) { // if they are in the same clb, put one arrow in the center float center_x = (src_point.x + sink_point.x) / 2; float center_y = (src_point.y + sink_point.y) / 2; @@ -689,7 +689,7 @@ void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_p draw_triangle_along_line(g, src_point, sink_point, 0.95); } } -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ int highlight_sub_block(const ezgl::point2d& point_in_clb, ClusterBlockId clb_index, t_pb* pb) { t_draw_state* draw_state = get_draw_state_vars(); @@ -805,32 +805,32 @@ void t_selected_sub_block_info::set(t_pb* new_selected_sub_block, const ClusterB if (has_selection()) { add_all_children(selected_pb, containing_block_index, in_selected_subtree); - for (auto blk_id : atom_ctx.nlist.blocks()) { - const ClusterBlockId clb = atom_ctx.lookup.atom_clb(blk_id); - const t_pb_graph_node* pb_graph_node = atom_ctx.lookup.atom_pb_graph_node(blk_id); + for (auto blk_id : atom_ctx.netlist().blocks()) { + const ClusterBlockId clb = atom_ctx.lookup().atom_clb(blk_id); + const t_pb_graph_node* pb_graph_node = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(blk_id); // find the atom block that corrisponds to this pb. if (is_in_selected_subtree(pb_graph_node, clb)) { //Collect the sources of all nets driving this node - for (auto pin_id : atom_ctx.nlist.block_input_pins(blk_id)) { - AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id); - AtomPinId driver_pin_id = atom_ctx.nlist.net_driver(net_id); + for (auto pin_id : atom_ctx.netlist().block_input_pins(blk_id)) { + AtomNetId net_id = atom_ctx.netlist().pin_net(pin_id); + AtomPinId driver_pin_id = atom_ctx.netlist().net_driver(net_id); - AtomBlockId src_blk = atom_ctx.nlist.pin_block(driver_pin_id); + AtomBlockId src_blk = atom_ctx.netlist().pin_block(driver_pin_id); - const ClusterBlockId src_clb = atom_ctx.lookup.atom_clb(src_blk); - const t_pb_graph_node* src_pb_graph_node = atom_ctx.lookup.atom_pb_graph_node(src_blk); + const ClusterBlockId src_clb = atom_ctx.lookup().atom_clb(src_blk); + const t_pb_graph_node* src_pb_graph_node = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(src_blk); sources.insert(gnode_clb_pair(src_pb_graph_node, src_clb)); } //Collect the sinks of all nets driven by this node - for (auto pin_id : atom_ctx.nlist.block_output_pins(blk_id)) { - AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id); - for (auto sink_pin_id : atom_ctx.nlist.net_sinks(net_id)) { - AtomBlockId sink_blk = atom_ctx.nlist.pin_block(sink_pin_id); + for (auto pin_id : atom_ctx.netlist().block_output_pins(blk_id)) { + AtomNetId net_id = atom_ctx.netlist().pin_net(pin_id); + for (auto sink_pin_id : atom_ctx.netlist().net_sinks(net_id)) { + AtomBlockId sink_blk = atom_ctx.netlist().pin_block(sink_pin_id); - const ClusterBlockId sink_clb = atom_ctx.lookup.atom_clb(sink_blk); - const t_pb_graph_node* sink_pb_graph_node = atom_ctx.lookup.atom_pb_graph_node(sink_blk); + const ClusterBlockId sink_clb = atom_ctx.lookup().atom_clb(sink_blk); + const t_pb_graph_node* sink_pb_graph_node = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(sink_blk); sinks.insert(gnode_clb_pair(sink_pb_graph_node, sink_clb)); } @@ -881,8 +881,8 @@ t_selected_sub_block_info::clb_pin_tuple::clb_pin_tuple(ClusterBlockId clb_index t_selected_sub_block_info::clb_pin_tuple::clb_pin_tuple(const AtomPinId atom_pin) { auto& atom_ctx = g_vpr_ctx.atom(); - clb_index = atom_ctx.lookup.atom_clb(atom_ctx.nlist.pin_block(atom_pin)); - pb_gnode = atom_ctx.lookup.atom_pb_graph_node(atom_ctx.nlist.pin_block(atom_pin)); + clb_index = atom_ctx.lookup().atom_clb(atom_ctx.netlist().pin_block(atom_pin)); + pb_gnode = atom_ctx.lookup().atom_pb_bimap().atom_pb_graph_node(atom_ctx.netlist().pin_block(atom_pin)); } bool t_selected_sub_block_info::clb_pin_tuple::operator==(const clb_pin_tuple& rhs) const { @@ -905,7 +905,7 @@ bool t_selected_sub_block_info::gnode_clb_pair::operator==(const gnode_clb_pair& /** * @brief Recursively looks through pb graph to find block w. given name - * + * * @param name name of block being searched for * @param pb current node to be examined * @return t_pb* t_pb ptr of block w. name "name". Returns nullptr if nothing found diff --git a/vpr/src/draw/intra_logic_block.h b/vpr/src/draw/intra_logic_block.h index 320a3c9f406..7ad0bf9bba5 100644 --- a/vpr/src/draw/intra_logic_block.h +++ b/vpr/src/draw/intra_logic_block.h @@ -20,17 +20,17 @@ #ifndef NO_GRAPHICS -# include "vpr_types.h" -# include "draw_types.h" -# include "atom_netlist_fwd.h" -# include +#include "vpr_types.h" +#include "draw_types.h" +#include "atom_netlist_fwd.h" +#include -# include "ezgl/point.hpp" +#include "ezgl/point.hpp" -# ifndef NO_GRAPHICS -# include "ezgl/graphics.hpp" -# include "ezgl/application.hpp" -# endif /* NO_GRAPHICS */ +#ifndef NO_GRAPHICS +#include "ezgl/graphics.hpp" +#include "ezgl/application.hpp" +#endif /* NO_GRAPHICS */ struct t_selected_sub_block_info { struct clb_pin_tuple { @@ -112,9 +112,9 @@ void draw_internal_init_blk(); /* Top-level drawing routine for internal sub-blocks. The function traverses through all * grid tiles and calls helper function to draw inside each block. */ -# ifndef NO_GRAPHICS +#ifndef NO_GRAPHICS void draw_internal_draw_subblk(ezgl::renderer* g); -# endif /* NO_GRAPHICS */ +#endif /* NO_GRAPHICS */ /* Determines which part of a block to highlight, and stores it, * so that the other subblock drawing functions will obey it. diff --git a/vpr/src/draw/manual_moves.cpp b/vpr/src/draw/manual_moves.cpp index 6a98d6ee419..972b2a36bd7 100644 --- a/vpr/src/draw/manual_moves.cpp +++ b/vpr/src/draw/manual_moves.cpp @@ -17,6 +17,7 @@ #include "draw.h" #include "draw_searchbar.h" #include "buttons.h" +#include "physical_types_util.h" #ifndef NO_GRAPHICS diff --git a/vpr/src/draw/manual_moves.h b/vpr/src/draw/manual_moves.h index 45739549c85..e5c152275d4 100644 --- a/vpr/src/draw/manual_moves.h +++ b/vpr/src/draw/manual_moves.h @@ -13,17 +13,17 @@ /** This file contains all functions for manual moves **/ #ifndef NO_GRAPHICS -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "manual_move_generator.h" - -# include "move_utils.h" -# include -# include -# include -# include -# include -# include +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "manual_move_generator.h" + +#include "move_utils.h" +#include +#include +#include +#include +#include +#include /** * @brief ManualMovesInfo struct diff --git a/vpr/src/draw/save_graphics.cpp b/vpr/src/draw/save_graphics.cpp index 84b1599f30f..657c6626b42 100644 --- a/vpr/src/draw/save_graphics.cpp +++ b/vpr/src/draw/save_graphics.cpp @@ -1,14 +1,10 @@ #ifndef NO_GRAPHICS -# include -# include - -# include "globals.h" -# include "draw.h" -# include "draw_global.h" -# include "save_graphics.h" -# include "vtr_path.h" -# include "search_bar.h" +#include + +#include "draw.h" +#include "save_graphics.h" +#include "search_bar.h" extern ezgl::rectangle initial_world; diff --git a/vpr/src/draw/save_graphics.h b/vpr/src/draw/save_graphics.h index 0ea5b183de0..f9a6ec2fbb1 100644 --- a/vpr/src/draw/save_graphics.h +++ b/vpr/src/draw/save_graphics.h @@ -9,11 +9,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" void save_graphics(std::string extension, std::string file_name); void save_graphics_dialog_box(GtkWidget* /*widget*/, ezgl::application* /*app*/); diff --git a/vpr/src/draw/search_bar.cpp b/vpr/src/draw/search_bar.cpp index ada698cf136..9a93be2274d 100644 --- a/vpr/src/draw/search_bar.cpp +++ b/vpr/src/draw/search_bar.cpp @@ -15,42 +15,42 @@ #include "physical_types.h" #ifndef NO_GRAPHICS -# include -# include - -# include "vtr_assert.h" -# include "vtr_ndoffsetmatrix.h" -# include "vtr_memory.h" -# include "vtr_log.h" -# include "vtr_color_map.h" - -# include "vpr_utils.h" -# include "vpr_error.h" - -# include "globals.h" -# include "draw_color.h" -# include "draw.h" -# include "draw_basic.h" -# include "draw_rr.h" -# include "draw_searchbar.h" -# include "read_xml_arch_file.h" -# include "draw_global.h" -# include "intra_logic_block.h" -# include "atom_netlist.h" -# include "tatum/report/TimingPathCollector.hpp" -# include "hsl.h" -# include "route_export.h" -# include "search_bar.h" +#include +#include + +#include "vtr_assert.h" +#include "vtr_ndoffsetmatrix.h" +#include "vtr_memory.h" +#include "vtr_log.h" +#include "vtr_color_map.h" + +#include "vpr_utils.h" +#include "vpr_error.h" + +#include "globals.h" +#include "draw_color.h" +#include "draw.h" +#include "draw_basic.h" +#include "draw_rr.h" +#include "draw_searchbar.h" +#include "read_xml_arch_file.h" +#include "draw_global.h" +#include "intra_logic_block.h" +#include "atom_netlist.h" +#include "tatum/report/TimingPathCollector.hpp" +#include "hsl.h" +#include "route_export.h" +#include "search_bar.h" //To process key presses we need the X11 keysym definitions, //which are unavailable when building with MINGW -# if defined(X11) && !defined(__MINGW32__) -# include -# endif +#if defined(X11) && !defined(__MINGW32__) +#include +#endif -# include "rr_graph.h" -# include "route_utilization.h" -# include "place_macro.h" +#include "rr_graph.h" +#include "route_utilization.h" +#include "place_macro.h" extern std::string rr_highlight_message; @@ -112,9 +112,9 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { std::string block_name; ss >> block_name; - AtomBlockId atom_blk_id = atom_ctx.nlist.find_block(block_name); + AtomBlockId atom_blk_id = atom_ctx.netlist().find_block(block_name); if (atom_blk_id != AtomBlockId::INVALID()) { - ClusterBlockId cluster_block_id = atom_ctx.lookup.atom_clb(atom_blk_id); + ClusterBlockId cluster_block_id = atom_ctx.lookup().atom_clb(atom_blk_id); if (!highlight_atom_block(atom_blk_id, cluster_block_id, app)) { highlight_cluster_block(cluster_block_id); } @@ -151,15 +151,15 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { //So we only need to search this one std::string net_name; ss >> net_name; - AtomNetId atom_net_id = atom_ctx.nlist.find_net(net_name); + AtomNetId atom_net_id = atom_ctx.netlist().find_net(net_name); if (atom_net_id == AtomNetId::INVALID()) { warning_dialog_box("Invalid Net Name"); return; //name not exist } - const auto clb_nets = atom_ctx.lookup.clb_nets(atom_net_id); - for(auto clb_net_id: clb_nets.value()){ + const auto clb_nets = atom_ctx.lookup().clb_nets(atom_net_id); + for (auto clb_net_id : clb_nets.value()) { highlight_nets(clb_net_id); } } @@ -319,7 +319,7 @@ bool highlight_atom_block(AtomBlockId atom_blk, ClusterBlockId cl_blk, ezgl::app t_pb* pb = cl_ctx.clb_nlist.block_pb(cl_blk); //Getting the pb* for the atom block - auto atom_block_pb = find_atom_block_in_pb(atom_ctx.nlist.block_name(atom_blk), pb); + auto atom_block_pb = find_atom_block_in_pb(atom_ctx.netlist().block_name(atom_blk), pb); if (!atom_block_pb) return false; //If no block found, returning false //Ensuring that block is drawn at current zoom lvl, returning false if not diff --git a/vpr/src/draw/search_bar.h b/vpr/src/draw/search_bar.h index 8108bfa8c4a..5aafd49435d 100644 --- a/vpr/src/draw/search_bar.h +++ b/vpr/src/draw/search_bar.h @@ -12,12 +12,12 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" -# include "draw_color.h" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" +#include "draw_color.h" void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app); bool highlight_rr_nodes(RRNodeId hit_node); @@ -53,4 +53,4 @@ GdkEvent simulate_keypress(char key, GdkWindow* window); std::string get_search_type(ezgl::application* app); #endif /* NO_GRAPHICS */ -#endif /* SEARCH_BAR_H */ \ No newline at end of file +#endif /* SEARCH_BAR_H */ diff --git a/vpr/src/draw/ui_setup.cpp b/vpr/src/draw/ui_setup.cpp index 61e05c9be3e..d62d8210e63 100644 --- a/vpr/src/draw/ui_setup.cpp +++ b/vpr/src/draw/ui_setup.cpp @@ -4,24 +4,24 @@ * @author Sebastian Lievano * @date July 4th, 2022 * @brief Manages setup for main.ui created buttons - * + * * This file contains the various setup functions for all of the ui functions. * As of June 2022, gtk ui items are to be created through Glade/main.ui file (see Docs) * Each function here initializes a different set of ui buttons, connecting their callback functions */ -# include "draw_global.h" -# include "draw.h" -# include "draw_toggle_functions.h" -# include "buttons.h" -# include "intra_logic_block.h" -# include "clustered_netlist.h" -# include "ui_setup.h" -# include "save_graphics.h" - -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "draw_global.h" +#include "draw.h" +#include "draw_toggle_functions.h" +#include "buttons.h" +#include "intra_logic_block.h" +#include "clustered_netlist.h" +#include "ui_setup.h" +#include "save_graphics.h" + +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" void basic_button_setup(ezgl::application* app) { //button to enter window_mode, created in main.ui GtkButton* window = (GtkButton*)app->get_object("Window"); @@ -45,7 +45,7 @@ void basic_button_setup(ezgl::application* app) { /* * @brief sets up net related buttons and connects their signals - * + * * Sets up the toggle nets combo box, net alpha spin button, and max fanout * spin button which are created in main.ui file. Found in Net Settings dropdown * @param app ezgl::application ptr @@ -70,11 +70,11 @@ void net_button_setup(ezgl::application* app) { /* * @brief sets up block related buttons, connects their signals - * + * * Connects signals and sets init. values for blk internals spin button, * blk pin util combo box,placement macros combo box, and noc combo bx created in * main.ui. Found in Block Settings dropdown - * @param app + * @param app */ void block_button_setup(ezgl::application* app) { t_draw_state* draw_state = get_draw_state_vars(); @@ -105,10 +105,10 @@ void block_button_setup(ezgl::application* app) { /** * @brief configures and connects signals/functions for routing buttons - * + * * Connects signals/sets default values for toggleRRButton, ToggleCongestion, - * ToggleCongestionCost, ToggleRoutingBBox, RoutingExpansionCost, ToggleRoutingUtil - * buttons. + * ToggleCongestionCost, ToggleRoutingBBox, RoutingExpansionCost, ToggleRoutingUtil + * buttons. */ void routing_button_setup(ezgl::application* app) { auto& route_ctx = g_vpr_ctx.routing(); @@ -216,7 +216,7 @@ void search_setup(ezgl::application* app) { /* * @brief connects critical path button to its cbk fn - * + * * @param app ezgl application */ void crit_path_button_setup(ezgl::application* app) { @@ -242,7 +242,7 @@ void hide_crit_path_routing(ezgl::application* app, bool hide) { } /* * @brief Hides the widget with the given name - * + * * @param widgetName string of widget name in main.ui * @param app ezgl app */ @@ -261,7 +261,7 @@ void show_widget(std::string widgetName, ezgl::application* app) { /** * @brief loads atom and cluster lvl names into gtk list store item used for completion - * + * * @param app ezgl application used for ui */ void load_block_names(ezgl::application* app) { @@ -276,17 +276,17 @@ void load_block_names(ezgl::application* app) { 0, (cluster_ctx.clb_nlist.block_name(id)).c_str(), -1); i++; } - for (AtomBlockId id : atom_ctx.nlist.blocks()) { + for (AtomBlockId id : atom_ctx.netlist().blocks()) { gtk_list_store_append(blockStorage, &iter); gtk_list_store_set(blockStorage, &iter, - 0, (atom_ctx.nlist.block_name(id)).c_str(), -1); + 0, (atom_ctx.netlist().block_name(id)).c_str(), -1); i++; } } /* * @brief loads atom net names into gtk list store item used for completion - * + * * @param app ezgl application used for ui */ void load_net_names(ezgl::application* app) { @@ -295,10 +295,10 @@ void load_net_names(ezgl::application* app) { GtkTreeIter iter; //Loading net names int i = 0; - for (AtomNetId id : atom_ctx.nlist.nets()) { + for (AtomNetId id : atom_ctx.netlist().nets()) { gtk_list_store_append(netStorage, &iter); gtk_list_store_set(netStorage, &iter, - 0, (atom_ctx.nlist.net_name(id)).c_str(), -1); + 0, (atom_ctx.netlist().net_name(id)).c_str(), -1); i++; } } diff --git a/vpr/src/draw/ui_setup.h b/vpr/src/draw/ui_setup.h index 40f2045ed91..3b543adb493 100644 --- a/vpr/src/draw/ui_setup.h +++ b/vpr/src/draw/ui_setup.h @@ -14,11 +14,11 @@ #ifndef NO_GRAPHICS -# include "draw_global.h" +#include "draw_global.h" -# include "ezgl/point.hpp" -# include "ezgl/application.hpp" -# include "ezgl/graphics.hpp" +#include "ezgl/point.hpp" +#include "ezgl/application.hpp" +#include "ezgl/graphics.hpp" /** * @brief configures basic buttons @@ -101,4 +101,4 @@ void show_widget(std::string widgetName, ezgl::application* app); #endif /* NO_GRAPHICS */ -#endif /* UISETUP_H */ \ No newline at end of file +#endif /* UISETUP_H */ diff --git a/vpr/src/noc/bfs_routing.cpp b/vpr/src/noc/bfs_routing.cpp index a72ec6b29e4..ef7d5c00d0e 100644 --- a/vpr/src/noc/bfs_routing.cpp +++ b/vpr/src/noc/bfs_routing.cpp @@ -129,4 +129,4 @@ void BFSRouting::generate_route(NocRouterId start_router_id, // now get the parent of the router we moved to curr_intermediate_router_parent_link = router_parent_link.find(curr_intermediate_router); } -} \ No newline at end of file +} diff --git a/vpr/src/noc/bfs_routing.h b/vpr/src/noc/bfs_routing.h index ca28a8ca3fd..7d881bed8b1 100644 --- a/vpr/src/noc/bfs_routing.h +++ b/vpr/src/noc/bfs_routing.h @@ -87,4 +87,4 @@ class BFSRouting : public NocRouting { const std::unordered_map& router_parent_link); }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/channel_dependency_graph.cpp b/vpr/src/noc/channel_dependency_graph.cpp index 31bd4052485..f85de80c0ac 100644 --- a/vpr/src/noc/channel_dependency_graph.cpp +++ b/vpr/src/noc/channel_dependency_graph.cpp @@ -125,4 +125,4 @@ bool ChannelDependencyGraph::has_cycles() { // if no vertex in the graph points to at least one of its ancestors, the graph does not have any cycles return false; -} \ No newline at end of file +} diff --git a/vpr/src/noc/negative_first_routing.cpp b/vpr/src/noc/negative_first_routing.cpp index e45df009122..30098587dff 100644 --- a/vpr/src/noc/negative_first_routing.cpp +++ b/vpr/src/noc/negative_first_routing.cpp @@ -74,9 +74,9 @@ const std::vector& NegativeFirstRouting::get_legal_ bool NegativeFirstRouting::is_turn_legal(const std::array, 3>& noc_routers, const NocStorage& noc_model) const { - const auto[x1, y1, z1] = noc_routers[0].get().get_router_physical_location(); - const auto[x2, y2, z2] = noc_routers[1].get().get_router_physical_location(); - const auto[x3, y3, z3] = noc_routers[2].get().get_router_physical_location(); + const auto [x1, y1, z1] = noc_routers[0].get().get_router_physical_location(); + const auto [x2, y2, z2] = noc_routers[1].get().get_router_physical_location(); + const auto [x3, y3, z3] = noc_routers[2].get().get_router_physical_location(); // check if the given routers can be traversed one after another VTR_ASSERT(vtr::exactly_k_conditions(2, x1 == x2, y1 == y2, z1 == z2)); @@ -89,8 +89,7 @@ bool NegativeFirstRouting::is_turn_legal(const std::array x1 && y3 < y2) || (y2 > y1 && x3 < x2) || (z2 > z1 && x3 < x2) || - (x2 > x1 && z3 < z2) || (z2 > z1 && y3 < y2) || (y2 > y1 && z3 < z2)) { + if ((x2 > x1 && y3 < y2) || (y2 > y1 && x3 < x2) || (z2 > z1 && x3 < x2) || (x2 > x1 && z3 < z2) || (z2 > z1 && y3 < y2) || (y2 > y1 && z3 < z2)) { return false; } } else { diff --git a/vpr/src/noc/noc_data_types.h b/vpr/src/noc/noc_data_types.h index 6317db4ae09..85752445245 100644 --- a/vpr/src/noc/noc_data_types.h +++ b/vpr/src/noc/noc_data_types.h @@ -28,4 +28,4 @@ typedef vtr::StrongId NocTrafficFlowId; struct noc_group_id_tag; typedef vtr::StrongId NocGroupId; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/noc_link.cpp b/vpr/src/noc/noc_link.cpp index f272023dbfc..8175964dc21 100644 --- a/vpr/src/noc/noc_link.cpp +++ b/vpr/src/noc/noc_link.cpp @@ -1,13 +1,12 @@ #include "noc_link.h" // constructor -NocLink::NocLink(NocLinkId link_id, NocRouterId source, NocRouterId sink, - double bw, double lat) +NocLink::NocLink(NocLinkId link_id, NocRouterId source, NocRouterId sink, double bw, double lat) : id(link_id) , source_router(source) , sink_router(sink) , bandwidth(bw) - , latency(lat) { } + , latency(lat) {} // getters NocRouterId NocLink::get_source_router() const { @@ -46,4 +45,3 @@ NocLinkId NocLink::get_link_id() const { NocLink::operator NocLinkId() const { return get_link_id(); } - diff --git a/vpr/src/noc/noc_link.h b/vpr/src/noc/noc_link.h index 3f56e763726..ba7ba01fbba 100644 --- a/vpr/src/noc/noc_link.h +++ b/vpr/src/noc/noc_link.h @@ -50,11 +50,10 @@ class NocLink { NocRouterId sink_router; /*!< The router which uses this link as an incoming edge*/ double bandwidth; /*!< Represents the maximum bits per second that can be transmitted over the link without causing congestion*/ - double latency; /*!< The zero-load latency of this link in seconds.*/ + double latency; /*!< The zero-load latency of this link in seconds.*/ public: - NocLink(NocLinkId link_id, NocRouterId source_router, NocRouterId sink_router, - double bw, double lat); + NocLink(NocLinkId link_id, NocRouterId source_router, NocRouterId sink_router, double bw, double lat); // getters @@ -122,4 +121,4 @@ class NocLink { operator NocLinkId() const; }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/noc_router.cpp b/vpr/src/noc/noc_router.cpp index 4af296c02ef..d2b18ec6b40 100644 --- a/vpr/src/noc/noc_router.cpp +++ b/vpr/src/noc/noc_router.cpp @@ -2,13 +2,15 @@ // constructor NocRouter::NocRouter(int id, - int grid_position_x, int grid_position_y, int layer_position, + int grid_position_x, + int grid_position_y, + int layer_position, double latency) : router_user_id(id) , router_grid_position_x(grid_position_x) , router_grid_position_y(grid_position_y) , router_layer_position(layer_position) - , router_latency(latency){ + , router_latency(latency) { // initialize variables router_block_ref = ClusterBlockId(0); } @@ -45,4 +47,4 @@ ClusterBlockId NocRouter::get_router_block_ref() const { // setters void NocRouter::set_router_block_ref(ClusterBlockId router_block_ref_id) { router_block_ref = router_block_ref_id; -} \ No newline at end of file +} diff --git a/vpr/src/noc/noc_router.h b/vpr/src/noc/noc_router.h index 968ff5206b7..e7a2b04ab0e 100644 --- a/vpr/src/noc/noc_router.h +++ b/vpr/src/noc/noc_router.h @@ -62,7 +62,9 @@ class NocRouter { public: NocRouter(int id, - int grid_position_x, int grid_position_y, int layer_position, + int grid_position_x, + int grid_position_y, + int layer_position, double latency); // getters @@ -117,4 +119,4 @@ class NocRouter { void set_router_block_ref(ClusterBlockId router_block_ref_id); }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/noc_routing_algorithm_creator.cpp b/vpr/src/noc/noc_routing_algorithm_creator.cpp index e52be823ae3..15cbbf5bbfb 100644 --- a/vpr/src/noc/noc_routing_algorithm_creator.cpp +++ b/vpr/src/noc/noc_routing_algorithm_creator.cpp @@ -8,7 +8,6 @@ #include "odd_even_routing.h" #include "vpr_error.h" - std::unique_ptr NocRoutingAlgorithmCreator::create_routing_algorithm(const std::string& routing_algorithm_name, const NocStorage& noc_model) { std::unique_ptr noc_routing_algorithm; @@ -30,4 +29,4 @@ std::unique_ptr NocRoutingAlgorithmCreator::create_routing_algorithm } return noc_routing_algorithm; -} \ No newline at end of file +} diff --git a/vpr/src/noc/noc_routing_algorithm_creator.h b/vpr/src/noc/noc_routing_algorithm_creator.h index 8cb9b777949..4c33d13f590 100644 --- a/vpr/src/noc/noc_routing_algorithm_creator.h +++ b/vpr/src/noc/noc_routing_algorithm_creator.h @@ -8,9 +8,10 @@ * * Overview * ======== - * There are a number of different available NoC routing algorithms. This class is a factory object for the NocRouting abstract class. This class constructs - * the appropriate routing algorithm based on the user specification in the - * command line. The user identifies a + * There are a number of different available NoC routing algorithms. + * This class is a factory object for the NocRouting abstract class. + * This class constructs the appropriate routing algorithm based on + * the user specification in the command line. The user identifies a * specific routing algorithm in the command line by providing a string * (which is the name of routing algorithm). * Then the corresponding routing algorithm is created here based on the diff --git a/vpr/src/noc/noc_storage.cpp b/vpr/src/noc/noc_storage.cpp index 58e79d46b03..4cf62e8b173 100644 --- a/vpr/src/noc/noc_storage.cpp +++ b/vpr/src/noc/noc_storage.cpp @@ -3,7 +3,6 @@ #include "vtr_assert.h" #include "vpr_error.h" - #include NocStorage::NocStorage() { @@ -106,7 +105,9 @@ bool NocStorage::is_noc_3d() const { // setters for the NoC void NocStorage::add_router(int id, - int grid_position_x, int grid_position_y, int layer_position, + int grid_position_x, + int grid_position_y, + int layer_position, double latency) { VTR_ASSERT_MSG(!built_noc, "NoC already built, cannot modify further."); @@ -183,9 +184,9 @@ bool NocStorage::remove_link(NocRouterId src_router_id, NocRouterId sink_router_ if (it == source_router_outgoing_links.end()) { VTR_LOG_WARN("No link could be found among outgoing links of source router with id(%d) " - "that that connects to the sink router with id (%d).\n", - (size_t)src_router_id, - (size_t)sink_router_id); + "that that connects to the sink router with id (%d).\n", + (size_t)src_router_id, + (size_t)sink_router_id); } source_router_outgoing_links.erase(it, source_router_outgoing_links.end()); @@ -196,9 +197,9 @@ bool NocStorage::remove_link(NocRouterId src_router_id, NocRouterId sink_router_ if (it == sink_router_incoming_links.end()) { VTR_LOG_WARN("No link could be found among incoming links of sink router with id(%d) " - "that that connects to the source router with id (%d).\n", - (size_t)sink_router_id, - (size_t)src_router_id); + "that that connects to the source router with id (%d).\n", + (size_t)sink_router_id, + (size_t)src_router_id); } sink_router_incoming_links.erase(it, sink_router_incoming_links.end()); @@ -256,6 +257,7 @@ void NocStorage::clear_noc() { link_storage.clear(); router_outgoing_links_list.clear(); router_incoming_links_list.clear(); + router_id_conversion_table.clear(); grid_location_to_router_id.clear(); built_noc = false; diff --git a/vpr/src/noc/noc_storage.h b/vpr/src/noc/noc_storage.h index 89dcf87bbac..deabfd27853 100644 --- a/vpr/src/noc/noc_storage.h +++ b/vpr/src/noc/noc_storage.h @@ -317,10 +317,9 @@ class NocStorage { * requested NoC links * @return A const */ - template class Container, typename... Ts> + template class Container, typename... Ts> const std::vector>& get_noc_links(const Container& noc_link_ids) const; - /** * @brief Given source and sink router identifiers, this function * finds a link connecting these routers and returns its identifier. @@ -385,7 +384,9 @@ class NocStorage { * when it is routed through this router. */ void add_router(int id, - int grid_position_x, int grid_position_y, int layer_position, + int grid_position_x, + int grid_position_y, + int layer_position, double latency); /** @@ -560,8 +561,7 @@ class NocStorage { void echo_noc(char* file_name) const; }; - -template class Container, typename... Ts> +template class Container, typename... Ts> const std::vector>& NocStorage::get_noc_links(const Container& noc_link_ids) const { returnable_noc_link_const_refs_.clear(); @@ -574,4 +574,3 @@ const std::vector>& NocStorage::get_noc_li } #endif - diff --git a/vpr/src/noc/noc_traffic_flows.cpp b/vpr/src/noc/noc_traffic_flows.cpp index 310eacd2f16..b0d7cfe1b46 100644 --- a/vpr/src/noc/noc_traffic_flows.cpp +++ b/vpr/src/noc/noc_traffic_flows.cpp @@ -49,7 +49,6 @@ const vtr::vector& NocTrafficFlows::get_al return noc_traffic_flows; } - // setters for the traffic flows void NocTrafficFlows::create_noc_traffic_flow(const std::string& source_router_module_name, @@ -189,4 +188,3 @@ void NocTrafficFlows::echo_noc_traffic_flows(char* file_name) { vtr::fclose(fp); } - diff --git a/vpr/src/noc/noc_traffic_flows.h b/vpr/src/noc/noc_traffic_flows.h index 53aa62709a3..a05a2e37696 100644 --- a/vpr/src/noc/noc_traffic_flows.h +++ b/vpr/src/noc/noc_traffic_flows.h @@ -68,7 +68,13 @@ struct t_noc_traffic_flow { int traffic_flow_priority; /** Constructor initializes all variables*/ - t_noc_traffic_flow(std::string source_router_name, std::string sink_router_name, ClusterBlockId source_router_id, ClusterBlockId sink_router_id, double flow_bandwidth, double max_flow_latency, int flow_priority) + t_noc_traffic_flow(std::string source_router_name, + std::string sink_router_name, + ClusterBlockId source_router_id, + ClusterBlockId sink_router_id, + double flow_bandwidth, + double max_flow_latency, + int flow_priority) noexcept : source_router_module_name(std::move(source_router_name)) , sink_router_module_name(std::move(sink_router_name)) , source_router_cluster_id(source_router_id) @@ -295,7 +301,6 @@ class NocTrafficFlows { */ void echo_noc_traffic_flows(char* file_name); - /** * @brief Defines the latency constraint of a traffic flow * when not provided by the user. @@ -310,4 +315,4 @@ class NocTrafficFlows { static constexpr double DEFAULT_MAX_TRAFFIC_FLOW_LATENCY = 1.; }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/north_last_routing.cpp b/vpr/src/noc/north_last_routing.cpp index fd3c1183201..82b1bd4b7f5 100644 --- a/vpr/src/noc/north_last_routing.cpp +++ b/vpr/src/noc/north_last_routing.cpp @@ -72,7 +72,6 @@ bool NorthLastRouting::is_turn_legal(const std::array z1 && x3 < x2) || (z2 > z1 && x3 > x2) || (z2 > z1 && y3 < y2) || - (y2 > y1 && z3 < z2) || (y2 > y1 && x3 < x2) || (y2 > y1 && x3 > x2)) { + if ((z2 > z1 && x3 < x2) || (z2 > z1 && x3 > x2) || (z2 > z1 && y3 < y2) || (y2 > y1 && z3 < z2) || (y2 > y1 && x3 < x2) || (y2 > y1 && x3 > x2)) { return false; } } else { @@ -90,6 +88,5 @@ bool NorthLastRouting::is_turn_legal(const std::array& OddEvenRouting::get_legal_direct if (noc_model.is_noc_3d()) { determine_legal_directions_3d(compressed_src_loc, compressed_curr_loc, compressed_dst_loc, prev_dir); - } else { // 2D NoC + } else { // 2D NoC determine_legal_directions_2d(compressed_src_loc, compressed_curr_loc, compressed_dst_loc, prev_dir); } @@ -120,7 +120,6 @@ bool OddEvenRouting::is_turn_legal(const std::array z1 && y3 < y2) || (z2 < z1 && y3 < y2)) { @@ -131,7 +130,7 @@ bool OddEvenRouting::is_turn_legal(const std::array 0) { diff --git a/vpr/src/noc/odd_even_routing.h b/vpr/src/noc/odd_even_routing.h index ce84c74c264..da61c5f3e9b 100644 --- a/vpr/src/noc/odd_even_routing.h +++ b/vpr/src/noc/odd_even_routing.h @@ -25,7 +25,6 @@ class OddEvenRouting : public TurnModelRouting { ~OddEvenRouting() override; private: - const std::vector& get_legal_directions(NocRouterId src_router_id, NocRouterId curr_router_id, NocRouterId dst_router_id, diff --git a/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp b/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp index 3f12c02ed2d..6b3df6c7ad9 100644 --- a/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp +++ b/vpr/src/noc/read_xml_noc_traffic_flows_file.cpp @@ -1,5 +1,6 @@ #include "read_xml_noc_traffic_flows_file.h" +#include "physical_types_util.h" void read_xml_noc_traffic_flows_file(const char* noc_flows_file) { // start by checking that the provided file is a ".flows" file @@ -274,7 +275,7 @@ bool check_that_all_router_blocks_have_an_associated_traffic_flow(NocContext& no /* * Go through the router subtiles and get the router logical block types the subtiles support. Then determine how many of each router logical block types there are in the clustered netlist. The accumulated sum of all these clusters is the total number of router blocks in the design. */ - for (const auto & noc_router_subtile : *noc_router_subtiles) { + for (const auto& noc_router_subtile : *noc_router_subtiles) { for (auto router_logical_block : noc_router_subtile.equivalent_sites) { // get the number of logical blocks in the design of the current logical block type number_of_router_blocks_in_design += clustered_netlist_stats.num_blocks_type[router_logical_block->index]; @@ -316,4 +317,4 @@ std::vector get_cluster_blocks_compatible_with_noc_router_tiles( } return cluster_blocks_compatible_with_noc_router_tiles; -} \ No newline at end of file +} diff --git a/vpr/src/noc/read_xml_noc_traffic_flows_file.h b/vpr/src/noc/read_xml_noc_traffic_flows_file.h index 2d8b348ad71..b53a0e432be 100644 --- a/vpr/src/noc/read_xml_noc_traffic_flows_file.h +++ b/vpr/src/noc/read_xml_noc_traffic_flows_file.h @@ -257,4 +257,4 @@ bool check_that_all_router_blocks_have_an_associated_traffic_flow(NocContext& no */ std::vector get_cluster_blocks_compatible_with_noc_router_tiles(const ClusteringContext& cluster_ctx, t_physical_tile_type_ptr noc_router_tile_type); -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/sat_routing.cpp b/vpr/src/noc/sat_routing.cpp index 354620c6cfa..0ccf1426720 100644 --- a/vpr/src/noc/sat_routing.cpp +++ b/vpr/src/noc/sat_routing.cpp @@ -1,6 +1,5 @@ #ifdef ENABLE_NOC_SAT_ROUTING - #include "sat_routing.h" #include "turn_model_routing.h" @@ -22,7 +21,6 @@ namespace orsat = operations_research::sat; */ typedef std::unordered_map, orsat::BoolVar> t_flow_link_var_map; - /** * @brief Creates a boolean variable for each (traffic flow, link) pair. * It also create integer variables for latency-constrained traffic flows. @@ -38,7 +36,7 @@ typedef std::unordered_map, orsat::BoolVa */ static void create_flow_link_vars(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars); + std::map& latency_overrun_vars); /** * @brief Translates a latency constraint for a traffic flow to the maximum number @@ -84,7 +82,7 @@ static std::vector get_flow_link_vars(const t_flow_link_var_map& */ static void constrain_latency_overrun_vars(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars); + std::map& latency_overrun_vars); /** * @brief Forbids specific turns that traffic flows can take. @@ -118,7 +116,7 @@ static void forbid_illegal_turns(t_flow_link_var_map& flow_link_vars, * @param bandwidth_resolution Specifies the resolution by which bandwidth * values are quantized. */ -static void create_congested_link_vars(vtr::vector& congested_link_vars, +static void create_congested_link_vars(vtr::vector& congested_link_vars, t_flow_link_var_map& flow_link_vars, orsat::CpModelBuilder& cp_model, int bandwidth_resolution); @@ -172,8 +170,8 @@ static void add_continuity_constraints(t_flow_link_var_map& flow_link_vars, */ static orsat::LinearExpr create_objective(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars, - vtr::vector& congested_link_vars, + std::map& latency_overrun_vars, + vtr::vector& congested_link_vars, int bandwidth_resolution, int latency_overrun_weight, int congestion_weight, @@ -211,7 +209,6 @@ static vtr::vector> convert_vars_to_rou */ static std::vector sort_noc_links_in_chain_order(const std::vector& links); - static std::vector get_flow_link_vars(const t_flow_link_var_map& map, const std::vector& traffic_flow_ids, const std::vector& noc_link_ids) { @@ -233,7 +230,7 @@ static void forbid_illegal_turns(t_flow_link_var_map& flow_link_vars, const auto& noc_ctx = g_vpr_ctx.noc(); const auto& traffic_flow_storage = noc_ctx.noc_traffic_flows_storage; - auto noc_routing_alg = dynamic_cast (noc_ctx.noc_flows_router.get()); + auto noc_routing_alg = dynamic_cast(noc_ctx.noc_flows_router.get()); // ensure that the routing algorithm is a turn model algorithm VTR_ASSERT(noc_routing_alg != nullptr); @@ -256,7 +253,7 @@ static vtr::vector quantize_traffic_flow_bandwidths(int b //TODO: support heterogeneous bandwidth const auto& noc_links = noc_ctx.noc_model.get_noc_links(); const double link_bandwidth = noc_links.front().get_bandwidth(); - auto it = std::adjacent_find(noc_links.begin(), noc_links.end(), [](const NocLink& a, const NocLink& b){ + auto it = std::adjacent_find(noc_links.begin(), noc_links.end(), [](const NocLink& a, const NocLink& b) { return a.get_bandwidth() != b.get_bandwidth(); }); @@ -281,10 +278,10 @@ static vtr::vector quantize_traffic_flow_bandwidths(int b rescaled_traffic_flow_bandwidths[traffic_flow_id] = rescaled_bandwidth; } - return rescaled_traffic_flow_bandwidths; + return rescaled_traffic_flow_bandwidths; } -static void create_congested_link_vars(vtr::vector& congested_link_vars, +static void create_congested_link_vars(vtr::vector& congested_link_vars, t_flow_link_var_map& flow_link_vars, orsat::CpModelBuilder& cp_model, int bandwidth_resolution) { @@ -351,7 +348,6 @@ static void add_continuity_constraints(t_flow_link_var_map& flow_link_vars, continue; } - // for each intermediate router, at most one incoming link can be activated to route this traffic flow const auto& incoming_links = noc_ctx.noc_model.get_noc_router_incoming_links(noc_router_id); auto incoming_vars = get_flow_link_vars(flow_link_vars, {traffic_flow_id}, incoming_links); @@ -386,8 +382,8 @@ static std::vector sort_noc_links_in_chain_order(const std::vector src_map; - std::unordered_map is_dst; + std::unordered_map src_map; + std::unordered_map is_dst; for (const auto l : links) { NocRouterId src_router_id = noc_model.get_single_noc_link(l).get_source_router(); NocRouterId dst_router_id = noc_model.get_single_noc_link(l).get_sink_router(); @@ -426,8 +422,7 @@ static vtr::vector> convert_vars_to_rou const auto& noc_ctx = g_vpr_ctx.noc(); const auto& traffic_flow_storage = noc_ctx.noc_traffic_flows_storage; - VTR_ASSERT(response.status() == orsat::CpSolverStatus::FEASIBLE || - response.status() == orsat::CpSolverStatus::OPTIMAL); + VTR_ASSERT(response.status() == orsat::CpSolverStatus::FEASIBLE || response.status() == orsat::CpSolverStatus::OPTIMAL); vtr::vector> routes; routes.resize(traffic_flow_storage.get_number_of_traffic_flows()); @@ -449,7 +444,7 @@ static vtr::vector> convert_vars_to_rou static void create_flow_link_vars(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars) { + std::map& latency_overrun_vars) { const auto& noc_ctx = g_vpr_ctx.noc(); const auto& noc_model = noc_ctx.noc_model; const auto& traffic_flow_storage = noc_ctx.noc_traffic_flows_storage; @@ -467,12 +462,14 @@ static void create_flow_link_vars(orsat::CpModelBuilder& cp_model, size_t max_n_cols = std::max_element(compressed_noc_grid.compressed_to_grid_x.begin(), compressed_noc_grid.compressed_to_grid_x.end(), [](const std::vector& a, const std::vector& b) { return a.size() < b.size(); - })->size(); + }) + ->size(); size_t max_n_rows = std::max_element(compressed_noc_grid.compressed_to_grid_y.begin(), compressed_noc_grid.compressed_to_grid_y.end(), [](const std::vector& a, const std::vector& b) { return a.size() < b.size(); - })->size(); + }) + ->size(); /* For specifying the domain, assume that the longest traffic flow route starts from * one corner and terminates at the opposite corner. Assuming minimal routing, such a @@ -523,7 +520,7 @@ static int comp_max_number_of_traversed_links(NocTrafficFlowId traffic_flow_id) } auto link_it = std::find_if(noc_links.begin(), noc_links.end(), [noc_link_latency](const NocLink& l) { - return (noc_link_latency != l.get_latency()); + return (noc_link_latency != l.get_latency()); }); if (link_it != noc_links.end()) { @@ -544,7 +541,7 @@ static int comp_max_number_of_traversed_links(NocTrafficFlowId traffic_flow_id) static void constrain_latency_overrun_vars(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars) { + std::map& latency_overrun_vars) { const auto& noc_ctx = g_vpr_ctx.noc(); const auto& noc_model = noc_ctx.noc_model; @@ -569,8 +566,8 @@ static void constrain_latency_overrun_vars(orsat::CpModelBuilder& cp_model, static orsat::LinearExpr create_objective(orsat::CpModelBuilder& cp_model, t_flow_link_var_map& flow_link_vars, - std::map& latency_overrun_vars, - vtr::vector& congested_link_vars, + std::map& latency_overrun_vars, + vtr::vector& congested_link_vars, int bandwidth_resolution, int latency_overrun_weight, int congestion_weight, @@ -603,7 +600,6 @@ static orsat::LinearExpr create_objective(orsat::CpModelBuilder& cp_model, agg_bw_expr = 0; } - orsat::LinearExpr congested_link_sum = orsat::LinearExpr::Sum(congested_link_vars); congested_link_sum *= congestion_weight; @@ -611,7 +607,6 @@ static orsat::LinearExpr create_objective(orsat::CpModelBuilder& cp_model, return objective; } - vtr::vector> noc_sat_route(bool minimize_aggregate_bandwidth, const t_noc_opts& noc_opts, int seed) { @@ -666,8 +661,7 @@ vtr::vector> noc_sat_route(bool minimiz orsat::CpSolverResponse response = orsat::SolveCpModel(cp_model.Build(), &model); - if (response.status() == orsat::CpSolverStatus::FEASIBLE || - response.status() == orsat::CpSolverStatus::OPTIMAL) { + if (response.status() == orsat::CpSolverStatus::FEASIBLE || response.status() == orsat::CpSolverStatus::OPTIMAL) { auto routes = convert_vars_to_routes(flow_link_vars, response); return routes; } @@ -676,4 +670,4 @@ vtr::vector> noc_sat_route(bool minimiz return {}; } -#endif //ENABLE_NOC_SAT_ROUTING \ No newline at end of file +#endif //ENABLE_NOC_SAT_ROUTING diff --git a/vpr/src/noc/sat_routing.h b/vpr/src/noc/sat_routing.h index 945b5a0aabe..60f9a900fb0 100644 --- a/vpr/src/noc/sat_routing.h +++ b/vpr/src/noc/sat_routing.h @@ -66,6 +66,5 @@ struct hash> { }; } // namespace std - #endif -#endif \ No newline at end of file +#endif diff --git a/vpr/src/noc/turn_model_routing.cpp b/vpr/src/noc/turn_model_routing.cpp index d9b169a0896..398af104844 100644 --- a/vpr/src/noc/turn_model_routing.cpp +++ b/vpr/src/noc/turn_model_routing.cpp @@ -78,12 +78,12 @@ void TurnModelRouting::route_flow(NocRouterId src_router_id, flow_route.push_back(next_link); prev_dir = next_step_direction; } else { - VPR_FATAL_ERROR(VPR_ERROR_OTHER, "No route could be found from starting router with ID:'%d' " + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "No route could be found from starting router with ID:'%d' " "and the destination router with ID:'%d' using the XY-Routing algorithm.", src_router.get_router_user_id(), dst_router.get_router_user_id()); } - } } @@ -200,7 +200,7 @@ uint32_t TurnModelRouting::murmur3_32(const std::vector& key, uint32_t // A swap is *not* necessary here because the preceding loop already // places the low bytes in the low places according to whatever endianness // we use. Swaps only apply when the memory is copied in a chunk. -// h ^= murmur_32_scramble(0); + // h ^= murmur_32_scramble(0); /* Finalize. */ h ^= key.size() * 4; h ^= h >> 16; @@ -325,7 +325,6 @@ TurnModelRouting::Direction TurnModelRouting::select_next_direction(const std::v int hash_val_remainder = hash_val % manhattan_dist; - TurnModelRouting::Direction selected_direction = TurnModelRouting::Direction::INVALID; if (hash_val_remainder < delta_x) { diff --git a/vpr/src/noc/turn_model_routing.h b/vpr/src/noc/turn_model_routing.h index ce061a56eed..7263c3d813d 100644 --- a/vpr/src/noc/turn_model_routing.h +++ b/vpr/src/noc/turn_model_routing.h @@ -122,14 +122,14 @@ class TurnModelRouting : public NocRouting { * choose to travel. */ enum class Direction { - WEST, /*!< Moving towards the negative X-axis*/ - EAST, /*!< Moving towards the positive X-axis*/ - NORTH, /*!< Moving towards the positive Y-axis*/ - SOUTH, /*!< Moving towards the negative Y-axis*/ - UP, /*!< Moving towards the positive Z-axis*/ - DOWN, /*!< Moving towards the negative Z-axis*/ + WEST, /*!< Moving towards the negative X-axis*/ + EAST, /*!< Moving towards the positive X-axis*/ + NORTH, /*!< Moving towards the positive Y-axis*/ + SOUTH, /*!< Moving towards the negative Y-axis*/ + UP, /*!< Moving towards the positive Z-axis*/ + DOWN, /*!< Moving towards the negative Z-axis*/ N_DIRECTIONS, - INVALID /*!< Invalid direction*/ + INVALID /*!< Invalid direction*/ }; /** @@ -209,7 +209,6 @@ class TurnModelRouting : public NocRouting { std::unordered_set& visited_routers, const NocStorage& noc_model); - /** * @brief Computes MurmurHash3 for an array of 32-bit words initialized * with seed. As discussed in the comment at the top of this file, @@ -274,7 +273,6 @@ class TurnModelRouting : public NocRouting { private: std::vector inputs_to_murmur3_hasher{4}; - }; #endif //VTR_TURN_MODEL_ROUTING_H diff --git a/vpr/src/noc/west_first_routing.cpp b/vpr/src/noc/west_first_routing.cpp index 95853c7e0c0..c47bfbf1456 100644 --- a/vpr/src/noc/west_first_routing.cpp +++ b/vpr/src/noc/west_first_routing.cpp @@ -48,10 +48,10 @@ const std::vector& WestFirstRouting::get_legal_dire returned_legal_direction.push_back(TurnModelRouting::Direction::DOWN); } } - } else { // 2D NoC + } else { // 2D NoC if (dst_router_pos.x < curr_router_pos.x) { returned_legal_direction.push_back(TurnModelRouting::Direction::WEST); - } else { // to the east or the same column + } else { // to the east or the same column if (dst_router_pos.x > curr_router_pos.x) { // not the same column returned_legal_direction.push_back(TurnModelRouting::Direction::EAST); } @@ -82,13 +82,11 @@ bool WestFirstRouting::is_turn_legal(const std::array z1 && x3 < x2) || (z2 < z1 && x3 < x2) || (z2 > z1 && y3 < y2) || - (z2 < z1 && y3 < y2) || (y2 > y1 && x3 < x2) || (x2 > x1 && y3 > y2)) { + if ((z2 > z1 && x3 < x2) || (z2 < z1 && x3 < x2) || (z2 > z1 && y3 < y2) || (z2 < z1 && y3 < y2) || (y2 > y1 && x3 < x2) || (x2 > x1 && y3 > y2)) { return false; } - } else { // 2D NoC + } else { // 2D NoC /* In the west-first routing algorithm, once the traffic flow * moved in a vertical direction, it is no longer allowed to move * towards west. Therefore, if the first link was travelling in a @@ -99,6 +97,5 @@ bool WestFirstRouting::is_turn_legal(const std::array& XYRouting::get_legal_directions( * the current router has the same x-coordinate as the * destination. Then we start moving along the y-axis. * Finally, we move along the z-axis. - */ + */ if (dst_router_pos.x > curr_router_pos.x) { return east_direction; @@ -82,4 +82,4 @@ bool XYRouting::is_turn_legal(const std::array east_direction{TurnModelRouting::Direction::EAST}; - const std::vector west_direction {TurnModelRouting::Direction::WEST}; - const std::vector north_direction {TurnModelRouting::Direction::NORTH}; - const std::vector south_direction {TurnModelRouting::Direction::SOUTH}; - const std::vector up_direction {TurnModelRouting::Direction::UP}; - const std::vector down_direction {TurnModelRouting::Direction::DOWN}; - const std::vector no_direction {}; - + const std::vector west_direction{TurnModelRouting::Direction::WEST}; + const std::vector north_direction{TurnModelRouting::Direction::NORTH}; + const std::vector south_direction{TurnModelRouting::Direction::SOUTH}; + const std::vector up_direction{TurnModelRouting::Direction::UP}; + const std::vector down_direction{TurnModelRouting::Direction::DOWN}; + const std::vector no_direction{}; }; -#endif \ No newline at end of file +#endif diff --git a/vpr/src/pack/appack_context.h b/vpr/src/pack/appack_context.h new file mode 100644 index 00000000000..0461f26b320 --- /dev/null +++ b/vpr/src/pack/appack_context.h @@ -0,0 +1,160 @@ +/** + * @file + * @author Alex Siner + * @date March 2025 + * @brief Declaration of the APPack Context object which stores all the + * information used to configure APPack in the packer. + */ + +#pragma once + +#include +#include +#include "device_grid.h" +#include "flat_placement_types.h" +#include "physical_types.h" +#include "vpr_context.h" +#include "vpr_utils.h" + +/** + * @brief Configuration options for APPack. + * + * APPack is an upgrade to the AAPack algorithm which uses an atom-level placement + * to inform the packer into creating better clusters. These options configure + * how APPack interprets the flat placement information. + */ +struct t_appack_options { + // Constructor for the appack options. + t_appack_options(const FlatPlacementInfo& flat_placement_info, + const DeviceGrid& device_grid) { + // If the flat placement info is valid, we want to use APPack. + // TODO: Should probably check that all the information is valid here. + use_appack = flat_placement_info.valid; + + // Set the max candidate distance as being some fraction of the longest + // distance on the device (from the bottom corner to the top corner). + // We also use an offset for the minimum this distance can be to prevent + // small devices from finding candidates. + float max_candidate_distance_scale = 0.1f; + float max_candidate_distance_offset = 15.0f; + // Longest L1 distance on the device. + float longest_distance = device_grid.width() + device_grid.height(); + max_candidate_distance = std::max(max_candidate_distance_scale * longest_distance, + max_candidate_distance_offset); + + // Infer the logical block type in the architecture. This will be used + // for the max candidate distance optimization to use a more aggressive + // distance. + t_logical_block_type_ptr logic_block_type = infer_logic_block_type(device_grid); + if (logic_block_type != nullptr) + logic_block_type_index = logic_block_type->index; + } + + // Whether to use APPack or not. + // This is initialized in the constructor based on if the flat placement + // info is valid or not. + bool use_appack = false; + + // =========== Cluster location ======================================== // + // What is the location of the cluster being created relative to the + // molecules being packed into it. + enum class e_cl_loc_ty { + CENTROID, /**< The location of the cluster is the centroid of the molecules which have been packed into it. */ + SEED /**< The location of the cluster is the location of the first molecule packed into it. */ + }; + static constexpr e_cl_loc_ty cluster_location_ty = e_cl_loc_ty::CENTROID; + + // =========== Candidate gain attenuation ============================== // + // These terms are used to update the gain of a given candidate based on + // its distance (d) relative to the location of the cluster being constructed. + // gain_new = attenuation * gain_original + // We use the following gain attenuation function: + // attenuation = { 1 - (quad_fac * d)^2 if d < dist_th + // { 1 / sqrt(d - sqrt_offset) if d >= dist_th + // The numbers below were empirically found to work well. + + // Distance threshold which decides when to use quadratic decay or inverted + // sqrt decay. If the distance is less than this threshold, quadratic decay + // is used. Inverted sqrt is used otherwise. + static constexpr float dist_th = 1.75f; + // Attenuation value at the threshold. + static constexpr float attenuation_th = 0.35f; + + // Using the distance threshold and the attenuation value at that point, we + // can compute the other two terms. This is to keep the attenuation function + // smooth. + // Horizontal offset to the inverted sqrt decay. + static constexpr float sqrt_offset = dist_th - ((1.0f / attenuation_th) * (1.0f / attenuation_th)); + // Squared scaling factor for the quadratic decay term. + static constexpr float quad_fac_sqr = (1.0f - attenuation_th) / (dist_th * dist_th); + + // =========== Candidate selection distance ============================ // + // When selecting candidates, what distance from the cluster will we + // consider? Any candidate beyond this distance will not be proposed. + // This is set in the constructor. + // TODO: It may be a good idea to have max different distances for different + // types of molecules / clusters. For example, CLBs vs DSPs + float max_candidate_distance = std::numeric_limits::max(); + + // A scaling applied to the max candidate distance of all clusters that are + // not logic blocks. + static constexpr float max_candidate_distance_non_lb_scale = 3.5f; + + // TODO: This should be an option similar to the target pin utilization + // so we can specify the max distance per block type! + int logic_block_type_index = -1; + + // =========== Unrelated clustering ==================================== // + // After searching for candidates by connectivity and timing, the user may + // turn on unrelated clustering, which will allow molecules which are + // unrelated to the cluster being created to be attempted to be packed in. + // APPack uses flat placement information to decide which unrelated + // molecules to try. + + // APPack will search for unrelated molecules in the tile which contains + // the flat location of the cluster. It will then look farther out, tile + // by tile. This parameter is the maximum distance from the cluster's tile + // that APPack will search. Setting this to 0 would only allow APPack to + // search within the cluster's tile. Setting this to a higher number would + // allow APPack to search farther away; but may bring in molecules which + // do not "want" to be in the cluster. + static constexpr float max_unrelated_tile_distance = 5.0f; + + // Unrelated clustering occurs after all other candidate selection methods + // have failed. This parameter sets how many time we will attempt unrelated + // clustering between failures of unrelated clustering. If this is set to + // 1, and unrelated clustering failed for a cluster, it will not be attempted + // again for that cluster (note: if it succeeds, the number of attempts get + // reset). + // NOTE: A similar option exists in the candidate selector class. This was + // duplicated since it is very likely that APPack would need a + // different value for this option than the non-APPack flow. + static constexpr int max_unrelated_clustering_attempts = 10; + + // TODO: Investigate adding flat placement info to seed selection. +}; + +/** + * @brief State relating to APPack. + * + * This class is intended to contain information on using flat placement + * information in packing. + */ +struct APPackContext : public Context { + /** + * @brief Constructor for the APPack context. + */ + APPackContext(const FlatPlacementInfo& fplace_info, const DeviceGrid& device_grid) + : appack_options(fplace_info, device_grid) + , flat_placement_info(fplace_info) {} + + /** + * @brief Options used to configure APPack. + */ + t_appack_options appack_options; + + /** + * @brief The flat placement information passed into APPack. + */ + const FlatPlacementInfo& flat_placement_info; +}; diff --git a/vpr/src/pack/atom_pb_bimap.cpp b/vpr/src/pack/atom_pb_bimap.cpp new file mode 100644 index 00000000000..df837cfea6b --- /dev/null +++ b/vpr/src/pack/atom_pb_bimap.cpp @@ -0,0 +1,65 @@ +/** + * @file + * @author Amir Poolad + * @date March 2025 + * @brief The code for the AtomPBBimap class. + * + * This file implements the various functions of the AtomPBBimap class. + */ + +#include "atom_pb_bimap.h" +#include "atom_netlist.h" + +AtomPBBimap::AtomPBBimap(const vtr::bimap& atom_to_pb) { + atom_to_pb_ = atom_to_pb; +} + +const t_pb* AtomPBBimap::atom_pb(const AtomBlockId blk_id) const { + auto iter = atom_to_pb_.find(blk_id); + if (iter == atom_to_pb_.end()) { + //Not found + return nullptr; + } + return iter->second; +} + +AtomBlockId AtomPBBimap::pb_atom(const t_pb* pb) const { + auto iter = atom_to_pb_.find(pb); + if (iter == atom_to_pb_.inverse_end()) { + //Not found + return AtomBlockId::INVALID(); + } + return iter->second; +} + +const t_pb_graph_node* AtomPBBimap::atom_pb_graph_node(const AtomBlockId blk_id) const { + const t_pb* pb = atom_pb(blk_id); + if (pb) { + //Found + return pb->pb_graph_node; + } + return nullptr; +} + +void AtomPBBimap::set_atom_pb(const AtomBlockId blk_id, const t_pb* pb) { + //If either of blk_id or pb are not valid, + //remove any mapping + if (!blk_id && pb) { + //Remove + atom_to_pb_.erase(pb); + } else if (blk_id && !pb) { + //Remove + atom_to_pb_.erase(blk_id); + } else if (blk_id && pb) { + //If both are valid store the mapping + atom_to_pb_.update(blk_id, pb); + } +} + +void AtomPBBimap::reset_bimap() { + atom_to_pb_.clear(); +} + +bool AtomPBBimap::is_empty() const { + return atom_to_pb_.empty(); +} diff --git a/vpr/src/pack/atom_pb_bimap.h b/vpr/src/pack/atom_pb_bimap.h new file mode 100644 index 00000000000..d8623543910 --- /dev/null +++ b/vpr/src/pack/atom_pb_bimap.h @@ -0,0 +1,58 @@ +/** + * @file + * @author Amir Poolad + * @date March 2025 + * @brief The declaration of the AtomPBBimap class. + * + * This file declares a class called AtomPBBimap that + * contains a two way mapping between AtomBlockIds and pb types. + */ + +#pragma once + +#include "vpr_types.h" + +// Forward declaration +class t_pb_graph_node; + +/** + * @brief Class that holds a bimap between atoms and pb types. + * This means that you can get a pb from an atom and the + * other way around. + * + * Used in the global AtomLookup context and in ClusterLegalizer + */ +class AtomPBBimap { + public: + AtomPBBimap() = default; + AtomPBBimap(const vtr::bimap& atom_to_pb); + + /** + * @brief Returns the leaf pb associated with the atom blk_id + * @note this is the lowest level pb which corresponds directly to the atom block + */ + const t_pb* atom_pb(const AtomBlockId blk_id) const; + + ///@brief Returns the atom block id associated with pb + AtomBlockId pb_atom(const t_pb* pb) const; + + ///@brief Conveneince wrapper around atom_pb to access the associated graph node + const t_pb_graph_node* atom_pb_graph_node(const AtomBlockId blk_id) const; + + /** + * @brief Sets the bidirectional mapping between an atom and pb + * + * If either blk_id or pb are not valid any, existing mapping is removed + */ + void set_atom_pb(const AtomBlockId blk_id, const t_pb* pb); + + /// @brief Sets the pb for all blocks in the netlist to nullptr. + void reset_bimap(); + + /// @brief Returns if the bimap is empty + bool is_empty() const; + + private: + /// @brief Two way map between AtomBlockIds and t_pb + vtr::bimap atom_to_pb_; +}; diff --git a/vpr/src/pack/attraction_groups.cpp b/vpr/src/pack/attraction_groups.cpp index 8d151c6c6aa..caba76fecb9 100644 --- a/vpr/src/pack/attraction_groups.cpp +++ b/vpr/src/pack/attraction_groups.cpp @@ -7,7 +7,7 @@ AttractionInfo::AttractionInfo(bool attraction_groups_on) { int num_parts = floorplanning_ctx.constraints.get_num_partitions(); //Initialize every atom to have no attraction group id - int num_atoms = atom_ctx.nlist.blocks().size(); + int num_atoms = atom_ctx.netlist().blocks().size(); atom_attraction_group.resize(num_atoms); fill(atom_attraction_group.begin(), atom_attraction_group.end(), AttractGroupId::INVALID()); @@ -33,7 +33,7 @@ AttractionInfo::AttractionInfo(bool attraction_groups_on) { } } -void AttractionInfo::create_att_groups_for_overfull_regions() { +void AttractionInfo::create_att_groups_for_overfull_regions(const std::vector& overfull_partition_regions) { const auto& floorplanning_ctx = g_vpr_ctx.floorplanning(); auto& atom_ctx = g_vpr_ctx.atom(); int num_parts = floorplanning_ctx.constraints.get_num_partitions(); @@ -43,13 +43,11 @@ void AttractionInfo::create_att_groups_for_overfull_regions() { attraction_groups.clear(); //Initialize every atom to have no attraction group id - int num_atoms = atom_ctx.nlist.blocks().size(); + int num_atoms = atom_ctx.netlist().blocks().size(); atom_attraction_group.resize(num_atoms); fill(atom_attraction_group.begin(), atom_attraction_group.end(), AttractGroupId::INVALID()); - const std::vector& overfull_prs = floorplanning_ctx.overfull_partition_regions; - /* * Create an attraction group for each partition that overlaps with at least one overfull partition */ @@ -58,7 +56,7 @@ void AttractionInfo::create_att_groups_for_overfull_regions() { const Partition& part = floorplanning_ctx.constraints.get_partition(partid); - for (const PartitionRegion& overfull_pr : overfull_prs) { + for (const PartitionRegion& overfull_pr : overfull_partition_regions) { PartitionRegion intersect_pr = intersection(part.get_part_region(), overfull_pr); if (!intersect_pr.empty()) { AttractionGroup group_info; @@ -87,7 +85,7 @@ void AttractionInfo::create_att_groups_for_all_regions() { attraction_groups.clear(); //Initialize every atom to have no attraction group id - int num_atoms = atom_ctx.nlist.blocks().size(); + int num_atoms = atom_ctx.netlist().blocks().size(); atom_attraction_group.resize(num_atoms); fill(atom_attraction_group.begin(), atom_attraction_group.end(), AttractGroupId::INVALID()); diff --git a/vpr/src/pack/attraction_groups.h b/vpr/src/pack/attraction_groups.h index ae2409cf772..d0d79c721b6 100644 --- a/vpr/src/pack/attraction_groups.h +++ b/vpr/src/pack/attraction_groups.h @@ -12,6 +12,9 @@ #include "vtr_vector.h" #include "atom_netlist_fwd.h" +// Forward declarations +class PartitionRegion; + /** * @file * @brief This file defines the AttractionInfo class, which is used to store atoms in attraction groups, which are @@ -53,7 +56,7 @@ class AttractionInfo { * Create attraction groups for the partitions that contain overfull regions (i.e. * The region has more blocks of a certain type assigned to than are actually available). */ - void create_att_groups_for_overfull_regions(); + void create_att_groups_for_overfull_regions(const std::vector& overfull_partition_regions); /* * Create attraction groups for all partitions. diff --git a/vpr/src/pack/cluster_feasibility_filter.cpp b/vpr/src/pack/cluster_feasibility_filter.cpp index c8ecb987f00..dec597aa41e 100644 --- a/vpr/src/pack/cluster_feasibility_filter.cpp +++ b/vpr/src/pack/cluster_feasibility_filter.cpp @@ -333,16 +333,14 @@ static void expand_pb_graph_node_and_load_output_to_input_connections(t_pb_graph reference_pin->list_of_connectable_input_pin_ptrs[depth][i] = temp[i]; reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primitive_input_pins[depth] - - 1] - = current_pb_graph_pin; + - 1] = current_pb_graph_pin; } else { reference_pin->list_of_connectable_input_pin_ptrs[depth] = new t_pb_graph_pin*[reference_pin->num_connectable_primitive_input_pins[depth]]; } reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primitive_input_pins[depth] - - 1] - = current_pb_graph_pin; + - 1] = current_pb_graph_pin; } } } diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index 399b0e271cc..282b0fe8d1c 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -17,6 +17,7 @@ #include #include "atom_lookup.h" #include "atom_netlist.h" +#include "cad_types.h" #include "cluster_placement.h" #include "cluster_router.h" #include "globals.h" @@ -37,43 +38,6 @@ #include "vtr_vector.h" #include "vtr_vector_map.h" -/** - * @brief Counts the total number of logic models that the architecture can - * implement. - * - * @param user_models A linked list of logic models. - * @return The total number of models in the linked list - */ -static size_t count_models(const t_model* user_models) { - if (user_models == nullptr) - return 0; - - size_t n_models = 0; - const t_model* cur_model = user_models; - while (cur_model != nullptr) { - n_models++; - cur_model = cur_model->next; - } - - return n_models; -} - -/* - * @brief Gets the max cluster size that any logical block can have. - * - * This is the maximum number of primitives any cluster can contain. - */ -static size_t calc_max_cluster_size(const std::vector& logical_block_types) { - size_t max_cluster_size = 0; - for (const t_logical_block_type& blk_type : logical_block_types) { - if (is_empty_type(&blk_type)) - continue; - int cur_cluster_size = get_max_primitives_in_pb_type(blk_type.pb_type); - max_cluster_size = std::max(max_cluster_size, cur_cluster_size); - } - return max_cluster_size; -} - /* * @brief Allocates the stats stored within the pb of a cluster. * @@ -97,24 +61,24 @@ static void alloc_and_load_pb_stats(t_pb* pb) { * @brief Check the atom blocks of a cluster pb. Used in the verify method. */ /* TODO: May want to check that all atom blocks are actually reached */ -static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set& blocks_checked) { +static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set& blocks_checked, const AtomPBBimap& atom_pb_lookup) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); const t_pb_type* pb_type = pb->pb_graph_node->pb_type; if (pb_type->num_modes == 0) { /* primitive */ - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(pb); + AtomBlockId blk_id = atom_pb_lookup.pb_atom(pb); if (blk_id) { if (blocks_checked.count(blk_id)) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "pb %s contains atom block %s but atom block is already contained in another pb.\n", - pb->name, atom_ctx.nlist.block_name(blk_id).c_str()); + pb->name, atom_ctx.netlist().block_name(blk_id).c_str()); } blocks_checked.insert(blk_id); - if (pb != atom_ctx.lookup.atom_pb(blk_id)) { + if (pb != atom_pb_lookup.atom_pb(blk_id)) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "pb %s contains atom block %s but atom block does not link to pb.\n", - pb->name, atom_ctx.nlist.block_name(blk_id).c_str()); + pb->name, atom_ctx.netlist().block_name(blk_id).c_str()); } } } else { @@ -125,7 +89,7 @@ static void check_cluster_atom_blocks(t_pb* pb, std::unordered_set& if (pb->child_pbs[i] != nullptr) { if (pb->child_pbs[i][j].name != nullptr) { has_child = true; - check_cluster_atom_blocks(&pb->child_pbs[i][j], blocks_checked); + check_cluster_atom_blocks(&pb->child_pbs[i][j], blocks_checked, atom_pb_lookup); } } } @@ -199,8 +163,8 @@ static bool check_cluster_floorplanning(AtomBlockId atom_blk_id, // the Cluster's new PartitionRegion. if (cluster_pr.empty()) { VTR_LOGV(log_verbosity > 3, - "\t\t\t Intersect: Atom block %d has floorplanning constraints\n", - atom_blk_id); + "\t\t\t Intersect: Atom block %d has floorplanning constraints\n", + atom_blk_id); cluster_pr = atom_pr; cluster_pr_needs_update = true; return true; @@ -214,8 +178,8 @@ static bool check_cluster_floorplanning(AtomBlockId atom_blk_id, // Cluster due to floorplanning constraints. if (cluster_pr.empty()) { VTR_LOGV(log_verbosity > 3, - "\t\t\t Intersect: Atom block %d failed floorplanning check for cluster\n", - atom_blk_id); + "\t\t\t Intersect: Atom block %d failed floorplanning check for cluster\n", + atom_blk_id); cluster_pr_needs_update = false; return false; } @@ -290,22 +254,24 @@ static bool check_cluster_noc_group(AtomBlockId atom_blk_id, * outside the cluster) and returns the status of the placement accordingly. */ static enum e_block_pack_status check_chain_root_placement_feasibility(const t_pb_graph_node* pb_graph_node, - const t_pack_molecule* molecule, - const AtomBlockId blk_id) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const t_chain_info& prepack_chain_info, + const t_clustering_chain_info& clustering_chain_info, + t_pack_patterns* mol_pack_patterns, + const AtomBlockId blk_id) { + const AtomNetlist& atom_netlist = g_vpr_ctx.atom().netlist(); enum e_block_pack_status block_pack_status = e_block_pack_status::BLK_PASSED; - bool is_long_chain = molecule->chain_info->is_long_chain; + bool is_long_chain = prepack_chain_info.is_long_chain; - const auto& chain_root_pins = molecule->pack_pattern->chain_root_pins; + const auto& chain_root_pins = mol_pack_patterns->chain_root_pins; t_model_ports* root_port = chain_root_pins[0][0]->port->model_port; AtomNetId chain_net_id; - auto port_id = atom_ctx.nlist.find_atom_port(blk_id, root_port); + auto port_id = atom_netlist.find_atom_port(blk_id, root_port); if (port_id) { - chain_net_id = atom_ctx.nlist.port_net(port_id, chain_root_pins[0][0]->pin_number); + chain_net_id = atom_netlist.port_net(port_id, chain_root_pins[0][0]->pin_number); } // if this block is part of a long chain or it is driven by a cluster @@ -315,7 +281,7 @@ static enum e_block_pack_status check_chain_root_placement_feasibility(const t_p // driven by a global gnd or vdd. Therefore even if this is not a long chain // but its input pin is driven by a net, the placement legality is checked. if (is_long_chain || chain_net_id) { - auto chain_id = molecule->chain_info->chain_id; + auto chain_id = clustering_chain_info.chain_id; // if this chain has a chain id assigned to it (implies is_long_chain too) if (chain_id != -1) { // the chosen primitive should be a valid starting point for the chain @@ -390,8 +356,8 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ //driving the output net //Get the ports from each primitive - auto blk_port_id = atom_ctx.nlist.find_atom_port(blk_id, port); - auto sib_port_id = atom_ctx.nlist.find_atom_port(sibling_blk_id, port); + auto blk_port_id = atom_ctx.netlist().find_atom_port(blk_id, port); + auto sib_port_id = atom_ctx.netlist().find_atom_port(sibling_blk_id, port); //Check that all nets (including unconnected nets) match for (int ipin = 0; ipin < port->size; ++ipin) { @@ -404,10 +370,10 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ //Note that if the port did not exist, the net is left //as invalid/disconneced if (blk_port_id) { - blk_net_id = atom_ctx.nlist.port_net(blk_port_id, ipin); + blk_net_id = atom_ctx.netlist().port_net(blk_port_id, ipin); } if (sib_port_id) { - sib_net_id = atom_ctx.nlist.port_net(sib_port_id, ipin); + sib_net_id = atom_ctx.netlist().port_net(sib_port_id, ipin); } //The sibling and block must have the same (possibly disconnected) @@ -426,14 +392,12 @@ static bool primitive_memory_sibling_feasible(const AtomBlockId blk_id, const t_ /* * @brief Check if the given atom is feasible in the given pb. */ -static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - +static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb, const AtomPBBimap& atom_to_pb) { const t_pb_type* cur_pb_type = cur_pb->pb_graph_node->pb_type; VTR_ASSERT(cur_pb_type->num_modes == 0); /* primitive */ - AtomBlockId cur_pb_blk_id = atom_ctx.lookup.pb_atom(cur_pb); + AtomBlockId cur_pb_blk_id = atom_to_pb.pb_atom(cur_pb); if (cur_pb_blk_id && cur_pb_blk_id != blk_id) { /* This pb already has a different logical block */ return false; @@ -444,7 +408,8 @@ static bool primitive_feasible(const AtomBlockId blk_id, t_pb* cur_pb) { * - all siblings must share all nets, including open nets, with the exception of data nets */ /* find sibling if one exists */ - AtomBlockId sibling_memory_blk_id = find_memory_sibling(cur_pb); + const t_pb* sibling_memory_pb = find_memory_sibling(cur_pb); + AtomBlockId sibling_memory_blk_id = atom_to_pb.pb_atom(sibling_memory_pb); if (sibling_memory_blk_id) { //There is a sibling, see if the current block is feasible with it @@ -467,17 +432,15 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, const AtomBlockId blk_id, t_pb* cb, t_pb** parent, - const int max_models, - const int max_cluster_size, const LegalizationClusterId cluster_id, vtr::vector_map& atom_cluster, - const t_intra_cluster_placement_stats* cluster_placement_stats_ptr, - const t_pack_molecule* molecule, + const PackMoleculeId molecule_id, t_lb_router_data* router_data, int verbosity, - const int feasible_block_array_size) { + const Prepacker& prepacker, + const vtr::vector_map& clustering_chain_info, + AtomPBBimap& atom_to_pb) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); - AtomContext& mutable_atom_ctx = g_vpr_ctx.mutable_atom(); VTR_ASSERT_SAFE(cb != nullptr); e_block_pack_status block_pack_status = e_block_pack_status::BLK_PASSED; @@ -487,10 +450,11 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, if (pb_graph_node->parent_pb_graph_node != cb->pb_graph_node) { t_pb* my_parent = nullptr; block_pack_status = try_place_atom_block_rec(pb_graph_node->parent_pb_graph_node, blk_id, cb, - &my_parent, max_models, max_cluster_size, cluster_id, + &my_parent, cluster_id, atom_cluster, - cluster_placement_stats_ptr, molecule, router_data, - verbosity, feasible_block_array_size); + molecule_id, router_data, + verbosity, + prepacker, clustering_chain_info, atom_to_pb); parent_pb = my_parent; } else { parent_pb = cb; @@ -500,7 +464,7 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, VTR_ASSERT(parent_pb != nullptr); if (parent_pb->child_pbs == nullptr) { VTR_ASSERT(parent_pb->name == nullptr); - parent_pb->name = vtr::strdup(atom_ctx.nlist.block_name(blk_id).c_str()); + parent_pb->name = vtr::strdup(atom_ctx.netlist().block_name(blk_id).c_str()); parent_pb->mode = pb_graph_node->pb_type->parent_mode->index; set_reset_pb_modes(router_data, parent_pb, true); const t_mode* mode = &parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode]; @@ -548,12 +512,12 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, bool is_primitive = (pb_type->num_modes == 0); if (is_primitive) { - VTR_ASSERT(!atom_ctx.lookup.pb_atom(pb) - && atom_ctx.lookup.atom_pb(blk_id) == nullptr + VTR_ASSERT(!atom_to_pb.pb_atom(pb) + && atom_to_pb.atom_pb(blk_id) == nullptr && atom_cluster[blk_id] == LegalizationClusterId::INVALID()); /* try pack to location */ VTR_ASSERT(pb->name == nullptr); - pb->name = vtr::strdup(atom_ctx.nlist.block_name(blk_id).c_str()); + pb->name = vtr::strdup(atom_ctx.netlist().block_name(blk_id).c_str()); //Update the atom netlist mappings atom_cluster[blk_id] = cluster_id; @@ -562,27 +526,34 @@ try_place_atom_block_rec(const t_pb_graph_node* pb_graph_node, // TODO: It would be a good idea to remove the use of this global // variables to prevent external users from modifying this by // mistake. - mutable_atom_ctx.lookup.set_atom_pb(blk_id, pb); + atom_to_pb.set_atom_pb(blk_id, pb); - add_atom_as_target(router_data, blk_id); - if (!primitive_feasible(blk_id, pb)) { + add_atom_as_target(router_data, blk_id, atom_to_pb); + if (!primitive_feasible(blk_id, pb, atom_to_pb)) { /* failed location feasibility check, revert pack */ block_pack_status = e_block_pack_status::BLK_FAILED_FEASIBLE; } // if this block passed and is part of a chained molecule - if (block_pack_status == e_block_pack_status::BLK_PASSED && molecule->is_chain()) { - auto molecule_root_block = molecule->atom_block_ids[molecule->root]; + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + if (block_pack_status == e_block_pack_status::BLK_PASSED && molecule.is_chain()) { + auto molecule_root_block = molecule.atom_block_ids[molecule.root]; // if this is the root block of the chain molecule check its placmeent feasibility if (blk_id == molecule_root_block) { - block_pack_status = check_chain_root_placement_feasibility(pb_graph_node, molecule, blk_id); + VTR_ASSERT(molecule.chain_id.is_valid()); + const t_chain_info& prepack_chain_info = prepacker.get_molecule_chain_info(molecule.chain_id); + block_pack_status = check_chain_root_placement_feasibility(pb_graph_node, + prepack_chain_info, + clustering_chain_info[molecule.chain_id], + molecule.pack_pattern, + blk_id); } } VTR_LOGV(verbosity > 4 && block_pack_status == e_block_pack_status::BLK_PASSED, "\t\t\tPlaced atom '%s' (%s) at %s\n", - atom_ctx.nlist.block_name(blk_id).c_str(), - atom_ctx.nlist.block_model(blk_id)->name, + atom_ctx.netlist().block_name(blk_id).c_str(), + atom_ctx.netlist().block_model(blk_id)->name, pb->hierarchical_type_name().c_str()); } @@ -628,13 +599,13 @@ static void reset_lookahead_pins_used(t_pb* cur_pb) { * @brief Checks if the sinks of the given net are reachable from the driver * pb gpin. */ -static int net_sinks_reachable_in_cluster(const t_pb_graph_pin* driver_pb_gpin, const int depth, const AtomNetId net_id) { +static int net_sinks_reachable_in_cluster(const t_pb_graph_pin* driver_pb_gpin, const int depth, const AtomNetId net_id, const AtomPBBimap& atom_to_pb) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); //Record the sink pb graph pins we are looking for std::unordered_set sink_pb_gpins; - for (const AtomPinId pin_id : atom_ctx.nlist.net_sinks(net_id)) { - const t_pb_graph_pin* sink_pb_gpin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id); + for (const AtomPinId pin_id : atom_ctx.netlist().net_sinks(net_id)) { + const t_pb_graph_pin* sink_pb_gpin = find_pb_graph_pin(atom_ctx.netlist(), atom_to_pb, pin_id); VTR_ASSERT(sink_pb_gpin); sink_pb_gpins.insert(sink_pb_gpin); @@ -647,7 +618,7 @@ static int net_sinks_reachable_in_cluster(const t_pb_graph_pin* driver_pb_gpin, if (sink_pb_gpins.count(reachable_pb_gpin)) { ++num_reachable_sinks; - if (num_reachable_sinks == atom_ctx.nlist.net_sinks(net_id).size()) { + if (num_reachable_sinks == atom_ctx.netlist().net_sinks(net_id).size()) { return true; } } @@ -660,20 +631,20 @@ static int net_sinks_reachable_in_cluster(const t_pb_graph_pin* driver_pb_gpin, * @brief Returns the pb_graph_pin of the atom pin defined by the driver_pin_id in the driver_pb */ static t_pb_graph_pin* get_driver_pb_graph_pin(const t_pb* driver_pb, const AtomPinId driver_pin_id) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const AtomNetlist& atom_netlist = g_vpr_ctx.atom().netlist(); const auto driver_pb_type = driver_pb->pb_graph_node->pb_type; int output_port = 0; // find the port of the pin driving the net as well as the port model - auto driver_port_id = atom_ctx.nlist.pin_port(driver_pin_id); - auto driver_model_port = atom_ctx.nlist.port_model(driver_port_id); + auto driver_port_id = atom_netlist.pin_port(driver_pin_id); + auto driver_model_port = atom_netlist.port_model(driver_port_id); // find the port id of the port containing the driving pin in the driver_pb_type for (int i = 0; i < driver_pb_type->num_ports; i++) { auto& prim_port = driver_pb_type->ports[i]; if (prim_port.type == OUT_PORT) { if (prim_port.model_port == driver_model_port) { // get the output pb_graph_pin driving this input net - return &(driver_pb->pb_graph_node->output_pins[output_port][atom_ctx.nlist.pin_port_bit(driver_pin_id)]); + return &(driver_pb->pb_graph_node->output_pins[output_port][atom_netlist.pin_port_bit(driver_pin_id)]); } output_port++; } @@ -694,7 +665,8 @@ static t_pb_graph_pin* get_driver_pb_graph_pin(const t_pb* driver_pb, const Atom static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* pb_graph_pin, const t_pb* primitive_pb, const AtomNetId net_id, - const vtr::vector_map& atom_cluster) { + const vtr::vector_map& atom_cluster, + const AtomPBBimap& atom_to_pb) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); // starting from the parent pb of the input primitive go up in the hierarchy till the root block @@ -703,17 +675,17 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p const auto pin_class = pb_graph_pin->parent_pin_class[depth]; VTR_ASSERT(pin_class != OPEN); - const auto driver_blk_id = atom_ctx.nlist.net_driver_block(net_id); + const auto driver_blk_id = atom_ctx.netlist().net_driver_block(net_id); // if this primitive pin is an input pin if (pb_graph_pin->port->type == IN_PORT) { /* find location of net driver if exist in clb, NULL otherwise */ // find the driver of the input net connected to the pin being studied - const auto driver_pin_id = atom_ctx.nlist.net_driver(net_id); + const auto driver_pin_id = atom_ctx.netlist().net_driver(net_id); // find the id of the atom occupying the input primitive_pb - const auto prim_blk_id = atom_ctx.lookup.pb_atom(primitive_pb); + const auto prim_blk_id = atom_to_pb.pb_atom(primitive_pb); // find the pb block occupied by the driving atom - const auto driver_pb = atom_ctx.lookup.atom_pb(driver_blk_id); + const auto driver_pb = atom_to_pb.atom_pb(driver_blk_id); // pb_graph_pin driving net_id in the driver pb block t_pb_graph_pin* output_pb_graph_pin = nullptr; // if the driver block is in the same clb as the input primitive block @@ -761,7 +733,7 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p */ bool net_exits_cluster = true; - int num_net_sinks = static_cast(atom_ctx.nlist.net_sinks(net_id).size()); + int num_net_sinks = static_cast(atom_ctx.netlist().net_sinks(net_id).size()); if (pb_graph_pin->num_connectable_primitive_input_pins[depth] >= num_net_sinks) { //It is possible the net is completely absorbed in the cluster, @@ -785,8 +757,8 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p //Check if all the net sinks are, in fact, inside this cluster bool all_sinks_in_cur_cluster = true; LegalizationClusterId driver_cluster = atom_cluster[driver_blk_id]; - for (auto pin_id : atom_ctx.nlist.net_sinks(net_id)) { - auto sink_blk_id = atom_ctx.nlist.pin_block(pin_id); + for (auto pin_id : atom_ctx.netlist().net_sinks(net_id)) { + auto sink_blk_id = atom_ctx.netlist().pin_block(pin_id); if (atom_cluster[sink_blk_id] != driver_cluster) { all_sinks_in_cur_cluster = false; break; @@ -801,7 +773,7 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p //the net does not exit the cluster /* TODO: I should cache the absorbed outputs, once net is absorbed, * net is forever absorbed, no point in rechecking every time */ - if (net_sinks_reachable_in_cluster(pb_graph_pin, depth, net_id)) { + if (net_sinks_reachable_in_cluster(pb_graph_pin, depth, net_id, atom_to_pb)) { //All the sinks are reachable inside the cluster net_exits_cluster = false; } @@ -816,23 +788,23 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p } } - /* * @brief Determine if pins of speculatively packed pb are legal */ static void compute_and_mark_lookahead_pins_used(const AtomBlockId blk_id, - const vtr::vector_map& atom_cluster) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); + const vtr::vector_map& atom_cluster, + const AtomPBBimap& atom_to_pb) { + const AtomNetlist& atom_netlist = g_vpr_ctx.atom().netlist(); - const t_pb* cur_pb = atom_ctx.lookup.atom_pb(blk_id); + const t_pb* cur_pb = atom_to_pb.atom_pb(blk_id); VTR_ASSERT(cur_pb != nullptr); /* Walk through inputs, outputs, and clocks marking pins off of the same class */ - for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); + for (auto pin_id : atom_netlist.block_pins(blk_id)) { + auto net_id = atom_netlist.pin_net(pin_id); - const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id); - compute_and_mark_lookahead_pins_used_for_pin(pb_graph_pin, cur_pb, net_id, atom_cluster); + const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_netlist, atom_to_pb, pin_id); + compute_and_mark_lookahead_pins_used_for_pin(pb_graph_pin, cur_pb, net_id, atom_cluster, atom_to_pb); } } @@ -843,9 +815,8 @@ static void compute_and_mark_lookahead_pins_used(const AtomBlockId blk_id, * number of pb_graph pins. Can use hash tables or make incremental if becomes an issue. */ static void try_update_lookahead_pins_used(t_pb* cur_pb, - const vtr::vector_map& atom_cluster) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - + const vtr::vector_map& atom_cluster, + const AtomPBBimap& atom_to_pb) { // run recursively till a leaf (primitive) pb block is reached const t_pb_type* pb_type = cur_pb->pb_graph_node->pb_type; if (pb_type->num_modes > 0 && cur_pb->name != nullptr) { @@ -853,7 +824,7 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, for (int i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; i++) { if (cur_pb->child_pbs[i] != nullptr) { for (int j = 0; j < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; j++) { - try_update_lookahead_pins_used(&cur_pb->child_pbs[i][j], atom_cluster); + try_update_lookahead_pins_used(&cur_pb->child_pbs[i][j], atom_cluster, atom_to_pb); } } } @@ -861,9 +832,9 @@ static void try_update_lookahead_pins_used(t_pb* cur_pb, } else { // find if this child (primitive) pb block has an atom mapped to it, // if yes compute and mark lookahead pins used for that pb block - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(cur_pb); + AtomBlockId blk_id = atom_to_pb.pb_atom(cur_pb); if (pb_type->blif_model != nullptr && blk_id) { - compute_and_mark_lookahead_pins_used(blk_id, atom_cluster); + compute_and_mark_lookahead_pins_used(blk_id, atom_cluster, atom_to_pb); } } } @@ -932,26 +903,31 @@ static bool check_lookahead_pins_used(t_pb* cur_pb, t_ext_pin_util max_external_ return true; } -/** - * @brief This function takes a chain molecule, and the pb_graph_node that is - * chosen for packing the molecule's root block. Using the given - * root_primitive, this function will identify which chain id this - * molecule is being mapped to and will update the chain id value inside - * the chain info data structure of this molecule. - */ -static void update_molecule_chain_info(t_pack_molecule* chain_molecule, const t_pb_graph_node* root_primitive) { - VTR_ASSERT(chain_molecule->chain_info->chain_id == -1 && chain_molecule->chain_info->is_long_chain); +void ClusterLegalizer::update_clustering_chain_info(PackMoleculeId chain_molecule_id, + const t_pb_graph_node* root_primitive) { + // Get the molecule + VTR_ASSERT(chain_molecule_id.is_valid()); + const t_pack_molecule& chain_molecule = prepacker_.get_molecule(chain_molecule_id); + + // Get the ID of the chain it is a part of + MoleculeChainId chain_id = chain_molecule.chain_id; + VTR_ASSERT(chain_id.is_valid()); - auto chain_root_pins = chain_molecule->pack_pattern->chain_root_pins; + // Get the prepacking and clustering information on this chain. + const t_chain_info& prepack_chain_info = prepacker_.get_molecule_chain_info(chain_id); + t_clustering_chain_info& clustering_chain_info = clustering_chain_info_[chain_id]; + VTR_ASSERT(clustering_chain_info.chain_id == -1 && prepack_chain_info.is_long_chain); + // Update the clustering chain information. // long chains should only be placed at the beginning of the chain // Since for long chains the molecule size is already equal to the // total number of adders in the cluster. Therefore, it should // always be placed at the very first adder in this cluster. + auto chain_root_pins = chain_molecule.pack_pattern->chain_root_pins; for (size_t chainId = 0; chainId < chain_root_pins.size(); chainId++) { if (chain_root_pins[chainId][0]->parent_node == root_primitive) { - chain_molecule->chain_info->chain_id = chainId; - chain_molecule->chain_info->first_packed_molecule = chain_molecule; + clustering_chain_info.chain_id = chainId; + clustering_chain_info.first_packed_molecule = chain_molecule_id; return; } } @@ -959,28 +935,27 @@ static void update_molecule_chain_info(t_pack_molecule* chain_molecule, const t_ VTR_ASSERT(false); } -/* - * @brief Reset molecule information created while trying to cluster it. - * - * This code only resets information that has to do with long chains. - * - * TODO: This information should not be stored in the molecule, but should be - * stored in the ClusterLegalizer class instead. - * - * TODO: This code may be removable. Tried turning it off and found no test - * failures or QoR degredations. Should be investigated in more detail. - */ -static void reset_molecule_info(t_pack_molecule* mol) { +void ClusterLegalizer::reset_molecule_info(PackMoleculeId mol_id) { + VTR_ASSERT(mol_id.is_valid()); + // when invalidating a molecule check if it's a chain molecule // that is part of a long chain. If so, check if this molecule // has modified the chain_id value based on the stale packing // then reset the chain id and the first packed molecule pointer // this is packing is being reset - if (mol->is_chain() - && mol->chain_info->is_long_chain - && mol->chain_info->first_packed_molecule == mol) { - mol->chain_info->first_packed_molecule = nullptr; - mol->chain_info->chain_id = -1; + const t_pack_molecule& mol = prepacker_.get_molecule(mol_id); + if (!mol.is_chain()) + return; + + VTR_ASSERT(mol.chain_id.is_valid()); + const t_chain_info& prepack_chain_info = prepacker_.get_molecule_chain_info(mol.chain_id); + if (!prepack_chain_info.is_long_chain) + return; + + t_clustering_chain_info& clustering_chain_info = clustering_chain_info_[mol.chain_id]; + if (clustering_chain_info.first_packed_molecule == mol_id) { + clustering_chain_info.first_packed_molecule = PackMoleculeId::INVALID(); + clustering_chain_info.chain_id = -1; } } @@ -989,16 +964,14 @@ static void reset_molecule_info(t_pack_molecule* mol) { */ static void revert_place_atom_block(const AtomBlockId blk_id, t_lb_router_data* router_data, - vtr::vector_map& atom_cluster) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - AtomContext& mutable_atom_ctx = g_vpr_ctx.mutable_atom(); - + vtr::vector_map& atom_cluster, + AtomPBBimap& atom_to_pb) { //We cast away const here since we may free the pb, and it is //being removed from the active mapping. // //In general most code works fine accessing cosnt t_pb*, - //which is why we store them as such in atom_ctx.lookup - t_pb* pb = const_cast(atom_ctx.lookup.atom_pb(blk_id)); + //which is why we store them as such in atom_ctx.lookup() + t_pb* pb = const_cast(atom_to_pb.atom_pb(blk_id)); if (pb != nullptr) { /* When freeing molecules, the current block might already have been freed by a prior revert @@ -1006,7 +979,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id, */ t_pb* next = pb->parent_pb; - free_pb(pb); + free_pb(pb, atom_to_pb); pb = next; while (pb != nullptr) { @@ -1022,7 +995,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id, /* If the code gets here, then that means that placing the initial seed molecule * failed, don't free the actual complex block itself as the seed needs to find * another placement */ - free_pb(pb); + free_pb(pb, atom_to_pb); } } pb = next; @@ -1031,7 +1004,7 @@ static void revert_place_atom_block(const AtomBlockId blk_id, //Update the atom netlist mapping atom_cluster[blk_id] = LegalizationClusterId::INVALID(); - mutable_atom_ctx.lookup.set_atom_pb(blk_id, nullptr); + atom_to_pb.set_atom_pb(blk_id, nullptr); } /* @@ -1139,14 +1112,14 @@ static bool cleanup_pb(t_pb* pb) { return can_free; } -e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecule, +e_block_pack_status ClusterLegalizer::try_pack_molecule(PackMoleculeId molecule_id, LegalizationCluster& cluster, LegalizationClusterId cluster_id, const t_ext_pin_util& max_external_pin_util) { // Try to pack the molecule into a cluster with this pb type. // Safety debugs. - VTR_ASSERT_DEBUG(molecule != nullptr); + VTR_ASSERT_DEBUG(molecule_id.is_valid()); VTR_ASSERT_DEBUG(cluster.pb != nullptr); VTR_ASSERT_DEBUG(cluster.type != nullptr); @@ -1159,15 +1132,19 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul // - Checking if the atom can be placed in the cluster for floorplanning // constraints. const FloorplanningContext& floorplanning_ctx = g_vpr_ctx.floorplanning(); + + // Get the molecule object. + const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); + if (log_verbosity_ > 3) { - AtomBlockId root_atom = molecule->atom_block_ids[molecule->root]; + AtomBlockId root_atom = molecule.atom_block_ids[molecule.root]; VTR_LOG("\t\tTry pack molecule: '%s' (%s)", - atom_ctx.nlist.block_name(root_atom).c_str(), - atom_ctx.nlist.block_model(root_atom)->name); - VTR_LOGV(molecule->pack_pattern, + atom_ctx.netlist().block_name(root_atom).c_str(), + atom_ctx.netlist().block_model(root_atom)->name); + VTR_LOGV(molecule.pack_pattern, " molecule_type %s molecule_size %zu", - molecule->pack_pattern->name, - molecule->atom_block_ids.size()); + molecule.pack_pattern->name, + molecule.atom_block_ids.size()); VTR_LOG("\n"); } @@ -1176,7 +1153,7 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul // molecules to be placed in this cluster. To avoid possibly creating cluster level // blocks that have incompatible placement constraints or form very long placement // macros that limit placement flexibility. - if (cluster.placement_stats->has_long_chain && molecule->is_chain() && molecule->chain_info->is_long_chain) { + if (cluster.placement_stats->has_long_chain && molecule.is_chain() && prepacker_.get_molecule_chain_info(molecule.chain_id).is_long_chain) { VTR_LOGV(log_verbosity_ > 4, "\t\t\tFAILED Placement Feasibility Filter: Only one long chain per cluster is allowed\n"); return e_block_pack_status::BLK_FAILED_FEASIBLE; } @@ -1187,40 +1164,39 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul PartitionRegion new_cluster_pr = cluster.pr; // TODO: This can be made more efficient by pre-computing the intersection // of all the atoms' PRs in the molecule. - int molecule_size = get_array_size_of_molecule(molecule); - for (int i_mol = 0; i_mol < molecule_size; i_mol++) { + for (AtomBlockId atom_blk_id : molecule.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + // Try to intersect with atom PartitionRegion if atom exists - AtomBlockId atom_blk_id = molecule->atom_block_ids[i_mol]; - if (atom_blk_id) { - bool cluster_pr_needs_update = false; - bool block_pack_floorplan_status = check_cluster_floorplanning(atom_blk_id, - new_cluster_pr, - floorplanning_ctx.constraints, - log_verbosity_, - cluster_pr_needs_update); - if (!block_pack_floorplan_status) { - return e_block_pack_status::BLK_FAILED_FLOORPLANNING; - } + bool cluster_pr_needs_update = false; + bool block_pack_floorplan_status = check_cluster_floorplanning(atom_blk_id, + new_cluster_pr, + floorplanning_ctx.constraints, + log_verbosity_, + cluster_pr_needs_update); + if (!block_pack_floorplan_status) { + return e_block_pack_status::BLK_FAILED_FLOORPLANNING; + } - if (cluster_pr_needs_update) { - cluster_pr_update_check = true; - } + if (cluster_pr_needs_update) { + cluster_pr_update_check = true; } } // Check if all atoms in the molecule can be added to the cluster without // NoC group conflicts NocGroupId new_cluster_noc_grp_id = cluster.noc_grp_id; - for (int i_mol = 0; i_mol < molecule_size; i_mol++) { - AtomBlockId atom_blk_id = molecule->atom_block_ids[i_mol]; - if (atom_blk_id) { - bool block_pack_noc_grp_status = check_cluster_noc_group(atom_blk_id, - new_cluster_noc_grp_id, - atom_noc_grp_id_, - log_verbosity_); - if (!block_pack_noc_grp_status) { - return e_block_pack_status::BLK_FAILED_NOC_GROUP; - } + for (AtomBlockId atom_blk_id : molecule.atom_block_ids) { + if (!atom_blk_id.is_valid()) + continue; + + bool block_pack_noc_grp_status = check_cluster_noc_group(atom_blk_id, + new_cluster_noc_grp_id, + atom_noc_grp_id_, + log_verbosity_); + if (!block_pack_noc_grp_status) { + return e_block_pack_status::BLK_FAILED_NOC_GROUP; } } @@ -1228,19 +1204,20 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul e_block_pack_status block_pack_status = e_block_pack_status::BLK_STATUS_UNDEFINED; while (block_pack_status != e_block_pack_status::BLK_PASSED) { if (!get_next_primitive_list(cluster.placement_stats, - molecule, - primitives_list.data())) { + molecule_id, + primitives_list, + prepacker_)) { VTR_LOGV(log_verbosity_ > 3, "\t\tFAILED No candidate primitives available\n"); block_pack_status = e_block_pack_status::BLK_FAILED_FEASIBLE; break; /* no more candidate primitives available, this molecule will not pack, return fail */ } block_pack_status = e_block_pack_status::BLK_PASSED; - int failed_location = 0; - for (int i_mol = 0; i_mol < molecule_size && block_pack_status == e_block_pack_status::BLK_PASSED; i_mol++) { - VTR_ASSERT((primitives_list[i_mol] == nullptr) == (!molecule->atom_block_ids[i_mol])); + size_t failed_location = 0; + for (size_t i_mol = 0; i_mol < molecule.atom_block_ids.size() && block_pack_status == e_block_pack_status::BLK_PASSED; i_mol++) { + VTR_ASSERT((primitives_list[i_mol] == nullptr) == (!molecule.atom_block_ids[i_mol])); failed_location = i_mol + 1; - AtomBlockId atom_blk_id = molecule->atom_block_ids[i_mol]; + AtomBlockId atom_blk_id = molecule.atom_block_ids[i_mol]; if (!atom_blk_id.is_valid()) continue; // NOTE: This parent variable is only used in the recursion of this @@ -1250,21 +1227,20 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul atom_blk_id, cluster.pb, &parent, - num_models_, - max_cluster_size_, cluster_id, atom_cluster_, - cluster.placement_stats, - molecule, + molecule_id, cluster.router_data, log_verbosity_, - feasible_block_array_size_); + prepacker_, + clustering_chain_info_, + mutable_atom_pb_lookup()); } if (enable_pin_feasibility_filter_ && block_pack_status == e_block_pack_status::BLK_PASSED) { // Check if pin usage is feasible for the current packing assignment reset_lookahead_pins_used(cluster.pb); - try_update_lookahead_pins_used(cluster.pb, atom_cluster_); + try_update_lookahead_pins_used(cluster.pb, atom_cluster_, atom_pb_lookup()); if (!check_lookahead_pins_used(cluster.pb, max_external_pin_util)) { VTR_LOGV(log_verbosity_ > 4, "\t\t\tFAILED Pin Feasibility Filter\n"); block_pack_status = e_block_pack_status::BLK_FAILED_FEASIBLE; @@ -1322,14 +1298,14 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul * TODO: SW Engineering note - may want to update cluster stats here too instead of doing it outside */ VTR_ASSERT(block_pack_status == e_block_pack_status::BLK_PASSED); - if (molecule->is_chain()) { + if (molecule.is_chain()) { /* Chained molecules often take up lots of area and are important, * if a chain is packed in, want to rename logic block to match chain name */ - AtomBlockId chain_root_blk_id = molecule->atom_block_ids[molecule->pack_pattern->root_block->block_id]; - t_pb* cur_pb = atom_ctx.lookup.atom_pb(chain_root_blk_id)->parent_pb; + AtomBlockId chain_root_blk_id = molecule.atom_block_ids[molecule.pack_pattern->root_block->block_id]; + t_pb* cur_pb = atom_pb_lookup().atom_pb(chain_root_blk_id)->parent_pb; while (cur_pb != nullptr) { free(cur_pb->name); - cur_pb->name = vtr::strdup(atom_ctx.nlist.block_name(chain_root_blk_id).c_str()); + cur_pb->name = vtr::strdup(atom_ctx.netlist().block_name(chain_root_blk_id).c_str()); cur_pb = cur_pb->parent_pb; } // if this molecule is part of a chain, mark the cluster as having a long chain @@ -1337,10 +1313,13 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul // If so, update the chain id for this chain of molecules to make sure all // molecules will be packed to the same chain id and can reach each other using // the chain direct links between clusters - if (molecule->chain_info->is_long_chain) { + VTR_ASSERT(molecule.chain_id.is_valid()); + const t_chain_info& prepack_chain_info = prepacker_.get_molecule_chain_info(molecule.chain_id); + if (prepack_chain_info.is_long_chain) { cluster.placement_stats->has_long_chain = true; - if (molecule->chain_info->chain_id == -1) { - update_molecule_chain_info(molecule, primitives_list[molecule->root]); + const t_clustering_chain_info& clustering_chain_info = clustering_chain_info_[molecule.chain_id]; + if (clustering_chain_info.chain_id == -1) { + update_clustering_chain_info(molecule_id, primitives_list[molecule.root]); } } } @@ -1356,10 +1335,10 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul cluster.noc_grp_id = new_cluster_noc_grp_id; // Insert the molecule into the cluster for bookkeeping. - cluster.molecules.push_back(molecule); + cluster.molecules.push_back(molecule_id); - for (int i = 0; i < molecule_size; i++) { - AtomBlockId atom_blk_id = molecule->atom_block_ids[i]; + for (size_t i = 0; i < molecule.atom_block_ids.size(); i++) { + AtomBlockId atom_blk_id = molecule.atom_block_ids[i]; if (!atom_blk_id.is_valid()) continue; @@ -1368,7 +1347,7 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul atom_cluster_[atom_blk_id] = cluster_id; // Update the num child blocks in pb - const t_pb* atom_pb = atom_ctx.lookup.atom_pb(atom_blk_id); + const t_pb* atom_pb = atom_pb_lookup().atom_pb(atom_blk_id); VTR_ASSERT_SAFE(atom_pb != nullptr); t_pb* cur_pb = atom_pb->parent_pb; while (cur_pb != nullptr) { @@ -1384,19 +1363,19 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul if (block_pack_status != e_block_pack_status::BLK_PASSED) { /* Pack unsuccessful, undo inserting molecule into cluster */ - for (int i = 0; i < failed_location; i++) { - AtomBlockId atom_blk_id = molecule->atom_block_ids[i]; + for (size_t i = 0; i < failed_location; i++) { + AtomBlockId atom_blk_id = molecule.atom_block_ids[i]; if (atom_blk_id) { - remove_atom_from_target(cluster.router_data, atom_blk_id); + remove_atom_from_target(cluster.router_data, atom_blk_id, atom_pb_lookup()); } } - for (int i = 0; i < failed_location; i++) { - AtomBlockId atom_blk_id = molecule->atom_block_ids[i]; + for (size_t i = 0; i < failed_location; i++) { + AtomBlockId atom_blk_id = molecule.atom_block_ids[i]; if (atom_blk_id) { - revert_place_atom_block(atom_blk_id, cluster.router_data, atom_cluster_); + revert_place_atom_block(atom_blk_id, cluster.router_data, atom_cluster_, mutable_atom_pb_lookup()); } } - reset_molecule_info(molecule); + reset_molecule_info(molecule_id); /* Packing failed, but a part of the pb tree is still allocated and pbs have their modes set. * Before trying to pack next molecule the unused pbs need to be freed and, the most important, @@ -1415,20 +1394,19 @@ e_block_pack_status ClusterLegalizer::try_pack_molecule(t_pack_molecule* molecul } std::tuple -ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, +ClusterLegalizer::start_new_cluster(PackMoleculeId molecule_id, t_logical_block_type_ptr cluster_type, int cluster_mode) { // Safety asserts to ensure the API is being called with valid arguments. - VTR_ASSERT_DEBUG(molecule != nullptr); + VTR_ASSERT_DEBUG(molecule_id.is_valid()); VTR_ASSERT_DEBUG(cluster_type != nullptr); VTR_ASSERT_DEBUG(cluster_mode < cluster_type->pb_graph_head->pb_type->num_modes); // Ensure that the molecule has not already been placed. - VTR_ASSERT_SAFE(molecule_cluster_.find(molecule) == molecule_cluster_.end() || - !molecule_cluster_[molecule].is_valid()); + VTR_ASSERT_SAFE(!molecule_cluster_[molecule_id].is_valid()); // Safety asserts to ensure that the API was initialized properly. VTR_ASSERT_DEBUG(lb_type_rr_graphs_ != nullptr); - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); // Create the physical block for this cluster based on the type. t_pb* cluster_pb = new t_pb; @@ -1458,7 +1436,7 @@ ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, // (meaning all cluster pins are allowed to be used). const t_ext_pin_util FULL_EXTERNAL_PIN_UTIL(1., 1.); LegalizationClusterId new_cluster_id = LegalizationClusterId(legalization_cluster_ids_.size()); - e_block_pack_status pack_status = try_pack_molecule(molecule, + e_block_pack_status pack_status = try_pack_molecule(molecule_id, new_cluster, new_cluster_id, FULL_EXTERNAL_PIN_UTIL); @@ -1466,7 +1444,8 @@ ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, if (pack_status == e_block_pack_status::BLK_PASSED) { // Give the new cluster pb a name. The current convention is to name the // cluster after the root atom of the first molecule packed into it. - AtomBlockId root_atom = molecule->atom_block_ids[molecule->root]; + const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); + AtomBlockId root_atom = molecule.atom_block_ids[molecule.root]; const std::string& root_atom_name = atom_nlist.block_name(root_atom); if (new_cluster.pb->name != nullptr) free(new_cluster.pb->name); @@ -1475,10 +1454,10 @@ ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, legalization_cluster_ids_.push_back(new_cluster_id); legalization_clusters_.push_back(std::move(new_cluster)); // Update the molecule to cluster map. - molecule_cluster_[molecule] = new_cluster_id; + molecule_cluster_[molecule_id] = new_cluster_id; } else { // Delete the new_cluster. - free_pb(new_cluster.pb); + free_pb(new_cluster.pb, mutable_atom_pb_lookup()); delete new_cluster.pb; free_router_data(new_cluster.router_data); free_cluster_placement_stats(new_cluster.placement_stats); @@ -1488,32 +1467,31 @@ ClusterLegalizer::start_new_cluster(t_pack_molecule* molecule, return {pack_status, new_cluster_id}; } -e_block_pack_status ClusterLegalizer::add_mol_to_cluster(t_pack_molecule* molecule, +e_block_pack_status ClusterLegalizer::add_mol_to_cluster(PackMoleculeId molecule_id, LegalizationClusterId cluster_id) { // Safety asserts to make sure the inputs are valid. VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); VTR_ASSERT(legalization_cluster_ids_[cluster_id].is_valid() && "Cannot add to a destroyed cluster"); // Ensure that the molecule has not already been placed. - VTR_ASSERT(molecule_cluster_.find(molecule) == molecule_cluster_.end() || - !molecule_cluster_[molecule].is_valid()); + VTR_ASSERT(!molecule_cluster_[molecule_id].is_valid()); // Safety asserts to ensure that the API was initialized properly. VTR_ASSERT_DEBUG(lb_type_rr_graphs_ != nullptr); // Get the cluster. LegalizationCluster& cluster = legalization_clusters_[cluster_id]; VTR_ASSERT(cluster.router_data != nullptr && cluster.placement_stats != nullptr - && "Cannot add molecule to cleaned cluster!"); + && "Cannot add molecule to cleaned cluster!"); // Set the target_external_pin_util. t_ext_pin_util target_ext_pin_util = target_external_pin_util_.get_pin_util(cluster.type->name); // Try to pack the molecule into the cluster. - e_block_pack_status pack_status = try_pack_molecule(molecule, + e_block_pack_status pack_status = try_pack_molecule(molecule_id, cluster, cluster_id, target_ext_pin_util); // If the packing was successful, set the molecules' cluster to this one. if (pack_status == e_block_pack_status::BLK_PASSED) - molecule_cluster_[molecule] = cluster_id; + molecule_cluster_[molecule_id] = cluster_id; return pack_status; } @@ -1525,24 +1503,23 @@ void ClusterLegalizer::destroy_cluster(LegalizationClusterId cluster_id) { // Get the cluster. LegalizationCluster& cluster = legalization_clusters_[cluster_id]; // Remove all molecules from the cluster. - for (t_pack_molecule* mol : cluster.molecules) { - VTR_ASSERT_SAFE(molecule_cluster_.find(mol) != molecule_cluster_.end() && - molecule_cluster_[mol] == cluster_id); - molecule_cluster_[mol] = LegalizationClusterId::INVALID(); + for (PackMoleculeId mol_id : cluster.molecules) { + VTR_ASSERT_SAFE(molecule_cluster_[mol_id] == cluster_id); + molecule_cluster_[mol_id] = LegalizationClusterId::INVALID(); // Revert the placement of all blocks in the molecule. - int molecule_size = get_array_size_of_molecule(mol); - for (int i = 0; i < molecule_size; i++) { - AtomBlockId atom_blk_id = mol->atom_block_ids[i]; + const t_pack_molecule& mol = prepacker_.get_molecule(mol_id); + for (AtomBlockId atom_blk_id : mol.atom_block_ids) { if (atom_blk_id) { - revert_place_atom_block(atom_blk_id, cluster.router_data, atom_cluster_); + revert_place_atom_block(atom_blk_id, cluster.router_data, atom_cluster_, mutable_atom_pb_lookup()); } } - reset_molecule_info(mol); + reset_molecule_info(mol_id); + molecule_cluster_[mol_id] = LegalizationClusterId::INVALID(); } cluster.molecules.clear(); // Free the rest of the cluster data. // Casting things to nullptr for safety just in case someone is trying to use it. - free_pb(cluster.pb); + free_pb(cluster.pb, mutable_atom_pb_lookup()); delete cluster.pb; cluster.pb = nullptr; free_router_data(cluster.router_data); @@ -1563,10 +1540,11 @@ void ClusterLegalizer::compress() { legalization_cluster_ids_ = clean_and_reorder_ids(cluster_id_map); legalization_clusters_ = clean_and_reorder_values(legalization_clusters_, cluster_id_map); // Update the reverse lookups. - for (auto& it : molecule_cluster_) { - if (!it.second.is_valid()) + for (PackMoleculeId mol_id : prepacker_.molecules()) { + LegalizationClusterId old_cluster_id = molecule_cluster_[mol_id]; + if (!old_cluster_id.is_valid()) continue; - molecule_cluster_[it.first] = cluster_id_map[it.second]; + molecule_cluster_[mol_id] = cluster_id_map[old_cluster_id]; } for (size_t i = 0; i < atom_cluster_.size(); i++) { AtomBlockId atom_blk_id = AtomBlockId(i); @@ -1587,7 +1565,7 @@ void ClusterLegalizer::clean_cluster(LegalizationClusterId cluster_id) { // Get the cluster. LegalizationCluster& cluster = legalization_clusters_[cluster_id]; VTR_ASSERT(cluster.router_data != nullptr && cluster.placement_stats != nullptr - && "Should not clean an already cleaned cluster!"); + && "Should not clean an already cleaned cluster!"); // Free the pb stats. free_pb_stats_recursive(cluster.pb); // Load the pb_route so we can free the cluster router data. @@ -1618,16 +1596,13 @@ bool ClusterLegalizer::check_cluster_legality(LegalizationClusterId cluster_id) ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, const Prepacker& prepacker, - const std::vector& logical_block_types, std::vector* lb_type_rr_graphs, - const t_model* user_models, - const t_model* library_models, const std::vector& target_external_pin_util_str, const t_pack_high_fanout_thresholds& high_fanout_thresholds, ClusterLegalizationStrategy cluster_legalization_strategy, bool enable_pin_feasibility_filter, - int feasible_block_array_size, - int log_verbosity) : prepacker_(prepacker) { + int log_verbosity) + : prepacker_(prepacker) { // Verify that the inputs are valid. VTR_ASSERT_SAFE(lb_type_rr_graphs != nullptr); @@ -1635,18 +1610,16 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, // NOTE: Be careful with this constructor, it may throw a VPR_FATAL_ERROR. target_external_pin_util_ = t_ext_pin_util_targets(target_external_pin_util_str); + // Resize the molecule_cluster lookup to make the accesses much cheaper. + molecule_cluster_.resize(prepacker_.molecules().size(), LegalizationClusterId::INVALID()); // Resize the atom_cluster lookup to make the accesses much cheaper. atom_cluster_.resize(atom_netlist.blocks().size(), LegalizationClusterId::INVALID()); + // Default the clustering chain info for each chain. + clustering_chain_info_.resize(prepacker_.get_num_molecule_chains()); // Pre-compute the max size of any molecule. max_molecule_size_ = prepacker.get_max_molecule_size(); - // Calculate the max cluster size - // - Limit maximum number of elements for each cluster to MAX_SHORT - max_cluster_size_ = calc_max_cluster_size(logical_block_types); - VTR_ASSERT(max_cluster_size_ < MAX_SHORT); // Get a reference to the rr graphs. lb_type_rr_graphs_ = lb_type_rr_graphs; - // Get the number of models in the architecture. - num_models_ = count_models(user_models) + count_models(library_models); // Find all NoC router atoms. std::vector noc_atoms = find_noc_router_atoms(atom_netlist); update_noc_reachability_partitions(noc_atoms, @@ -1656,8 +1629,9 @@ ClusterLegalizer::ClusterLegalizer(const AtomNetlist& atom_netlist, // Copy the options passed by the user cluster_legalization_strategy_ = cluster_legalization_strategy; enable_pin_feasibility_filter_ = enable_pin_feasibility_filter; - feasible_block_array_size_ = feasible_block_array_size; log_verbosity_ = log_verbosity; + VTR_ASSERT(g_vpr_ctx.atom().lookup().atom_pb_bimap().is_empty()); + atom_pb_lookup_ = AtomPBBimap(); } void ClusterLegalizer::reset() { @@ -1667,9 +1641,8 @@ void ClusterLegalizer::reset() { continue; destroy_cluster(cluster_id); } + mutable_atom_pb_lookup().reset_bimap(); compress(); - // Reset the molecule_cluster map - molecule_cluster_.clear(); } void ClusterLegalizer::verify() { @@ -1683,25 +1656,25 @@ void ClusterLegalizer::verify() { /* * Check that each atom block connects to one physical primitive and that the primitive links up to the parent clb */ - for (auto blk_id : atom_ctx.nlist.blocks()) { + for (auto blk_id : atom_ctx.netlist().blocks()) { //Each atom should be part of a pb - const t_pb* atom_pb = atom_ctx.lookup.atom_pb(blk_id); + const t_pb* atom_pb = atom_pb_lookup().atom_pb(blk_id); if (!atom_pb) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom block %s is not mapped to a pb\n", - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str()); } //Check the reverse mapping is consistent - if (atom_ctx.lookup.pb_atom(atom_pb) != blk_id) { + if (atom_pb_lookup().pb_atom(atom_pb) != blk_id) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "pb %s does not contain atom block %s but atom block %s maps to pb.\n", atom_pb->name, - atom_ctx.nlist.block_name(blk_id).c_str(), - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str(), + atom_ctx.netlist().block_name(blk_id).c_str()); } - VTR_ASSERT(atom_ctx.nlist.block_name(blk_id) == atom_pb->name); + VTR_ASSERT(atom_ctx.netlist().block_name(blk_id) == atom_pb->name); const t_pb* cur_pb = atom_pb; while (cur_pb->parent_pb) { @@ -1713,7 +1686,7 @@ void ClusterLegalizer::verify() { if (cluster_id == LegalizationClusterId::INVALID()) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom %s is not mapped to a CLB\n", - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str()); } if (cur_pb != get_cluster_pb(cluster_id)) { @@ -1727,22 +1700,21 @@ void ClusterLegalizer::verify() { for (LegalizationClusterId cluster_id : clusters()) { if (!cluster_id.is_valid()) continue; - check_cluster_atom_blocks(get_cluster_pb(cluster_id), - atoms_checked); + check_cluster_atom_blocks(get_cluster_pb(cluster_id), atoms_checked, atom_pb_lookup()); } - for (auto blk_id : atom_ctx.nlist.blocks()) { + for (auto blk_id : atom_ctx.netlist().blocks()) { if (!atoms_checked.count(blk_id)) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom block %s not found in any cluster.\n", - atom_ctx.nlist.block_name(blk_id).c_str()); + atom_ctx.netlist().block_name(blk_id).c_str()); } } } -bool ClusterLegalizer::is_molecule_compatible(t_pack_molecule* molecule, +bool ClusterLegalizer::is_molecule_compatible(PackMoleculeId molecule_id, LegalizationClusterId cluster_id) const { - VTR_ASSERT_SAFE(molecule != nullptr); + VTR_ASSERT_SAFE(molecule_id.is_valid()); VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); // Go through each atom in the molecule and check if there exists a free // primitive for that atom block. @@ -1753,7 +1725,8 @@ bool ClusterLegalizer::is_molecule_compatible(t_pack_molecule* molecule, // would be more robust, but checking individual atoms is faster. const LegalizationCluster& cluster = legalization_clusters_[cluster_id]; - for (AtomBlockId atom_blk_id : molecule->atom_block_ids) { + const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); + for (AtomBlockId atom_blk_id : molecule.atom_block_ids) { // FIXME: Why is it possible that molecules contain invalid block IDs? // This should be fixed! if (!atom_blk_id.is_valid()) @@ -1773,8 +1746,7 @@ bool ClusterLegalizer::is_molecule_compatible(t_pack_molecule* molecule, return true; } -size_t ClusterLegalizer::get_num_cluster_inputs_available( - LegalizationClusterId cluster_id) const { +size_t ClusterLegalizer::get_num_cluster_inputs_available(LegalizationClusterId cluster_id) const { VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); const LegalizationCluster& cluster = legalization_clusters_[cluster_id]; @@ -1807,4 +1779,3 @@ ClusterLegalizer::~ClusterLegalizer() { destroy_cluster(cluster_id); } } - diff --git a/vpr/src/pack/cluster_legalizer.h b/vpr/src/pack/cluster_legalizer.h index ef3ec64f7b2..67bc00a95ec 100644 --- a/vpr/src/pack/cluster_legalizer.h +++ b/vpr/src/pack/cluster_legalizer.h @@ -12,17 +12,19 @@ #pragma once -#include #include #include "atom_netlist_fwd.h" #include "noc_data_types.h" #include "partition_region.h" +#include "prepack.h" #include "vpr_types.h" #include "vtr_range.h" #include "vtr_strong_id.h" #include "vtr_vector.h" #include "vtr_vector_map.h" +#include "atom_pb_bimap.h" +// Forward declarations class Prepacker; class t_intra_cluster_placement_stats; class t_pb_graph_node; @@ -34,23 +36,49 @@ struct t_lb_router_data; struct legalization_cluster_id_tag; typedef vtr::StrongId LegalizationClusterId; +/** + * @brief Holds information to be shared between molecules that represent the + * same chained pack pattern, specifically for packing. + * + * For example, molecules that are representing a long carry chain that spans + * multiple logic blocks. + * + * This is holding clustering-specific information on the chains. General + * information on chains is found in the t_chain_info type. + */ +struct t_clustering_chain_info { + /// @brief An ID into the chain_root_pins vector in the t_pack_patterns of + /// the molecule. + /// + /// Used to get the starting point of this chain in the cluster. This ID is + /// useful when we have multiple (architectural) carry chains in a logic + /// block, for example. It lets us see which of the chains is being used for + /// this long (netlist) chain, so we continue to use that chain in the + /// packing of other molecules of this long chain. + int chain_id = -1; + + /// @brief First molecule to be packed out of the molecules forming this + /// chain. This is the molecule setting the value of the chain_id. + PackMoleculeId first_packed_molecule; +}; + /// @brief The different legalization strategies the cluster legalizer can perform. /// /// Allows the user of the API to select how thorough the legalizer should be /// when adding molecules into clusters. enum class ClusterLegalizationStrategy { - FULL, // Run the full legalizer (including intra-lb routing) - SKIP_INTRA_LB_ROUTE // Do all legality checks except intra-lb routing + FULL, // Run the full legalizer (including intra-lb routing) + SKIP_INTRA_LB_ROUTE // Do all legality checks except intra-lb routing }; /// @brief The status of the cluster legalization. enum class e_block_pack_status { - BLK_PASSED, // Passed legalization. - BLK_FAILED_FEASIBLE, // Failed due to block not feasibly being able to go in the cluster. - BLK_FAILED_ROUTE, // Failed due to intra-lb routing failure. - BLK_FAILED_FLOORPLANNING, // Failed due to not being compatible with the cluster's current PartitionRegion. - BLK_FAILED_NOC_GROUP, // Failed due to not being compatible with the cluster's NoC group. - BLK_STATUS_UNDEFINED // Undefined status. Something went wrong. + BLK_PASSED, // Passed legalization. + BLK_FAILED_FEASIBLE, // Failed due to block not feasibly being able to go in the cluster. + BLK_FAILED_ROUTE, // Failed due to intra-lb routing failure. + BLK_FAILED_FLOORPLANNING, // Failed due to not being compatible with the cluster's current PartitionRegion. + BLK_FAILED_NOC_GROUP, // Failed due to not being compatible with the cluster's NoC group. + BLK_STATUS_UNDEFINED // Undefined status. Something went wrong. }; /* @@ -62,7 +90,7 @@ struct LegalizationCluster { /// @brief A list of the molecules in the cluster. By design, a cluster will /// only contain molecules which have been previously legalized into /// the cluster using a legalization strategy. - std::vector molecules; + std::vector molecules; /// @brief The logical block of this cluster. /// TODO: We should be more careful with how this is allocated. Instead of @@ -164,15 +192,14 @@ struct LegalizationCluster { * // new_cluster_id now contains a fully legalized cluster. */ class ClusterLegalizer { -public: + public: // Iterator for the legalization cluster IDs typedef typename vtr::vector_map::const_iterator cluster_iterator; // Range for the legalization cluster IDs typedef typename vtr::Range cluster_range; -private: - + private: /* * @brief Helper method that tries to pack the given molecule into a cluster. * @@ -186,13 +213,29 @@ class ClusterLegalizer { * @param max_external_pin_util The max external pin utilization for a * cluster of this type. */ - e_block_pack_status try_pack_molecule(t_pack_molecule* molecule, + e_block_pack_status try_pack_molecule(PackMoleculeId molecule_id, LegalizationCluster& cluster, LegalizationClusterId cluster_id, const t_ext_pin_util& max_external_pin_util); -public: + /** + * @brief This function takes a chain molecule, and the pb_graph_node that is + * chosen for packing the molecule's root block. Using the given + * root_primitive, this function will identify which chain id this + * molecule is being mapped to and will update the chain id value inside + * the chain info data structure of this molecule. + */ + void update_clustering_chain_info(PackMoleculeId chain_molecule_id, + const t_pb_graph_node* root_primitive); + /* + * @brief Reset molecule information created while trying to cluster it. + * + * This code only resets information that has to do with long chains. + */ + void reset_molecule_info(PackMoleculeId mol_id); + + public: // Explicitly deleted default constructor. Need to use other constructor to // initialize state correctly. ClusterLegalizer() = delete; @@ -202,57 +245,39 @@ class ClusterLegalizer { * * Allocates internal state. * - * @param atom_netlist The complete atom netlist. Used to allocate - * internal structures to the correct size. - * @param prepacker The prepacker object used to prepack the atoms - * into molecules. A reference to this object is - * stored internally to be used to lookup the - * molecules of atoms. - * @param logical_block_types Used to allocate internal objects. Used to - * get the max number of primitives in any block - * type. - * @param lb_type_rr_graphs The routing resource graph internal to the - * different cluster types. A reference is stored - * in the class to be used to allocate and load - * the router data. - * @param user_models A linked list of the user models. Used to allocate - * an internal structure. - * @param library_models A linked list of the library models. Used to - * allocate an internal structure. - * @param target_external_pin_util_str A string used to initialize the - * target external pin utilization of - * each cluster type. - * @param high_fanout_thresholds An object that stores the thresholds for - * a net to be considered high fanout for - * different block types. - * @param cluster_legalization_strategy The legalization strategy to be - * used when creating clusters and - * adding molecules to clusters. - * Controls the checks that are performed. - * @param enable_pin_feasibility_filter A flag to turn on/off the check for - * pin usage feasibility. - * @param feasible_block_array_size The largest number of feasible blocks - * that can be stored in a cluster. Used - * to allocate an internal structure. - * @param log_verbosity Controls how verbose the log messages will - * be within this class. - * - * TODO: A lot of these arguments are only used to allocate C-style arrays - * since the original author was avoiding dynamic allocations. It may - * be more space efficient (and cleaner) to make these dynamic arrays - * and not pass these arguments in. + * @param atom_netlist + * The complete atom netlist. Used to allocate internal structures + * to the correct size. + * @param prepacker + * The prepacker object used to prepack the atoms into molecules. + * A reference to this object is stored internally to be used to + * lookup the molecules of atoms. + * @param lb_type_rr_graphs + * The routing resource graph internal to the different cluster + * types. A reference is stored in the class to be used to allocate + * and load the router data. + * @param target_external_pin_util_str + * A string used to initialize the target external pin utilization + * of each cluster type. + * @param high_fanout_thresholds + * An object that stores the thresholds for a net to be considered + * high fanout for different block types. + * @param cluster_legalization_strategy + * The legalization strategy to be used when creating clusters and + * adding molecules to clusters. Controls the checks that are + * performed. + * @param enable_pin_feasibility_filter + * A flag to turn on/off the check for pin usage feasibility. + * @param log_verbosity + * Controls how verbose the log messages will be within this class. */ ClusterLegalizer(const AtomNetlist& atom_netlist, const Prepacker& prepacker, - const std::vector& logical_block_types, std::vector* lb_type_rr_graphs, - const t_model* user_models, - const t_model* library_models, const std::vector& target_external_pin_util_str, const t_pack_high_fanout_thresholds& high_fanout_thresholds, ClusterLegalizationStrategy cluster_legalization_strategy, bool enable_pin_feasibility_filter, - int feasible_block_array_size, int log_verbosity); // This class allocates and deallocates memory within. This class should not @@ -272,7 +297,7 @@ class ClusterLegalizer { * status will return the reason and the ID would be invalid. */ std::tuple - start_new_cluster(t_pack_molecule* molecule, + start_new_cluster(PackMoleculeId molecule_id, t_logical_block_type_ptr cluster_type, int cluster_mode); @@ -292,7 +317,7 @@ class ClusterLegalizer { * @return The status of the pack (if the addition was successful and * if not why). */ - e_block_pack_status add_mol_to_cluster(t_pack_molecule* molecule, + e_block_pack_status add_mol_to_cluster(PackMoleculeId molecule_id, LegalizationClusterId cluster_id); /* @@ -396,7 +421,7 @@ class ClusterLegalizer { * go in a cluster. By calling it you can save runtime for impossible cases * vs. calling the full checks. */ - bool is_molecule_compatible(t_pack_molecule* molecule, + bool is_molecule_compatible(PackMoleculeId molecule_id, LegalizationClusterId cluster_id) const; /// @brief Gets the top-level pb of the given cluster. @@ -421,6 +446,13 @@ class ClusterLegalizer { return cluster.pr; } + /// @brief Gets the molecules currently packed within the given cluster. + inline const std::vector& get_cluster_molecules(LegalizationClusterId cluster_id) const { + VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); + const LegalizationCluster& cluster = legalization_clusters_[cluster_id]; + return cluster.molecules; + } + /// @brief Gets the current number of molecules in the cluster. inline size_t get_num_molecules_in_cluster(LegalizationClusterId cluster_id) const { VTR_ASSERT_SAFE(cluster_id.is_valid() && (size_t)cluster_id < legalization_clusters_.size()); @@ -446,17 +478,11 @@ class ClusterLegalizer { /// @brief Returns true if the given molecule has been packed into a /// cluster, false otherwise. - inline bool is_mol_clustered(t_pack_molecule* mol) const { - VTR_ASSERT_SAFE(mol != nullptr); + inline bool is_mol_clustered(PackMoleculeId mol_id) const { + VTR_ASSERT_SAFE(mol_id.is_valid()); // Check if the molecule has been assigned a cluster. It has not been - // assigned a cluster if it does not have an entry in the map or if the - // ID of the cluster it is assigned to is invalid. - const auto iter = molecule_cluster_.find(mol); - if (iter == molecule_cluster_.end()) - return false; - if (!iter->second.is_valid()) - return false; - return true; + // assigned a cluster if it is assigned to a valid cluster. + return molecule_cluster_[mol_id].is_valid(); } /// @brief Returns a reference to the target_external_pin_util object. This @@ -465,14 +491,6 @@ class ClusterLegalizer { return target_external_pin_util_; } - /// @bried Gets the max size a cluster could physically be. - /// - /// This is the maximum number of primitives any cluster could ever have - /// in the architecture. - inline size_t get_max_cluster_size() const { - return max_cluster_size_; - } - /* * @brief Set the legalization strategy of the cluster legalizer. * @@ -503,16 +521,22 @@ class ClusterLegalizer { log_verbosity_ = verbosity; } + inline const AtomPBBimap& atom_pb_lookup() const { return atom_pb_lookup_; } + inline AtomPBBimap& mutable_atom_pb_lookup() { return atom_pb_lookup_; } + /// @brief Destructor of the class. Frees allocated data. ~ClusterLegalizer(); -private: + private: /// @brief A vector of the legalization cluster IDs. If any of them are /// invalid, then that means that the cluster has been destroyed. vtr::vector_map legalization_cluster_ids_; /// @brief Lookup table for which cluster each molecule is in. - std::unordered_map molecule_cluster_; + vtr::vector_map molecule_cluster_; + + /// @brief Clustering chain information for each of the chains in the prepacker. + vtr::vector_map clustering_chain_info_; /// @brief List of all legalization clusters. vtr::vector_map legalization_clusters_; @@ -537,20 +561,12 @@ class ClusterLegalizer { /// expensive to calculate from the prepacker. size_t max_molecule_size_; - /// @brief The max number of primitives a cluster could physically have. - /// This is used to allocate dynamic arrays. - size_t max_cluster_size_; - /// @brief A vector of routing resource nodes within each logical block type /// [0 .. num_logical_block_types-1] /// TODO: This really should not be a pointer to a vector... I think this is /// meant to be a vector of vectors... std::vector* lb_type_rr_graphs_ = nullptr; - /// @brief The total number of models (user + library) in the architecture. - /// Used to allocate space in dynamic data structures. - size_t num_models_; - /// @brief The current legalization strategy of the cluster legalizer. ClusterLegalizationStrategy cluster_legalization_strategy_; @@ -564,11 +580,6 @@ class ClusterLegalizer { /// option of the same name. bool enable_pin_feasibility_filter_; - /// @brief The max size of the priority queue for candidates that pass the - /// early filter legality test but not the more detailed routing - /// filter. This matches the packer option of the same name. - int feasible_block_array_size_; - /// @brief Used to set the verbosity of log messages in the legalizer. Used /// for debugging. When log_verbosity > 3, the legalizer will print /// messages when a molecule is successful during legalization. When @@ -580,5 +591,8 @@ class ClusterLegalizer { /// @brief The prepacker object that stores the molecules which will be /// legalized into clusters. const Prepacker& prepacker_; -}; + /// @brief A two way map between AtomBlockIds and pb types. This is a copy + /// of the AtomPBBimap in the global context's AtomLookup + AtomPBBimap atom_pb_lookup_; +}; diff --git a/vpr/src/pack/cluster_placement.cpp b/vpr/src/pack/cluster_placement.cpp index 917545cd3ba..297212c4ff1 100644 --- a/vpr/src/pack/cluster_placement.cpp +++ b/vpr/src/pack/cluster_placement.cpp @@ -20,6 +20,7 @@ #include "cluster_placement.h" #include "hash.h" #include "physical_types.h" +#include "prepack.h" #include "vpr_types.h" #include "vpr_utils.h" #include "vtr_assert.h" @@ -43,14 +44,16 @@ static void update_primitive_cost_or_status(t_intra_cluster_placement_stats* clu bool valid); static float try_place_molecule(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, + PackMoleculeId molecule_id, t_pb_graph_node* root, - t_pb_graph_node** primitives_list); + std::vector& primitives_list, + const Prepacker& prepacker); static bool expand_forced_pack_molecule_placement(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, + PackMoleculeId molecule_id, const t_pack_pattern_block* pack_pattern_block, - t_pb_graph_node** primitives_list, + std::vector& primitives_list, + const Prepacker& prepacker, float* cost); static t_pb_graph_pin* expand_pack_molecule_pin_edge(int pattern_id, @@ -147,14 +150,14 @@ void t_intra_cluster_placement_stats::free_primitives() { } t_intra_cluster_placement_stats* alloc_and_load_cluster_placement_stats(t_logical_block_type_ptr cluster_type, - int cluster_mode) { + int cluster_mode) { t_intra_cluster_placement_stats* cluster_placement_stats = new t_intra_cluster_placement_stats; *cluster_placement_stats = t_intra_cluster_placement_stats(); // TODO: This initialization may be able to be made more efficient. // The reset and setting the mode can be done while loading the placement // stats. if (!is_empty_type(cluster_type)) { - cluster_placement_stats->curr_molecule = nullptr; + cluster_placement_stats->curr_molecule = PackMoleculeId::INVALID(); load_cluster_placement_stats_for_pb_graph_node(cluster_placement_stats, cluster_type->pb_graph_head); } @@ -173,19 +176,19 @@ void free_cluster_placement_stats(t_intra_cluster_placement_stats* cluster_place } bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, - t_pb_graph_node** primitives_list, + PackMoleculeId molecule_id, + std::vector& primitives_list, + const Prepacker& prepacker, int force_site) { std::unordered_multimap::iterator best; - int i; float cost, lowest_cost; int best_pb_type_index = -1; - if (cluster_placement_stats->curr_molecule != molecule) { + if (cluster_placement_stats->curr_molecule != molecule_id) { /* New block, requeue tried primitives and in-flight primitives */ cluster_placement_stats->flush_intermediate_queues(); - cluster_placement_stats->curr_molecule = molecule; + cluster_placement_stats->curr_molecule = molecule_id; } else { /* Hack! Same failed molecule may re-enter if upper stream functions suck, * I'm going to make the molecule selector more intelligent. @@ -207,13 +210,14 @@ bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_ // Intialize variables bool found_best = false; - lowest_cost = HUGE_POSITIVE_FLOAT; + lowest_cost = std::numeric_limits::max(); // Iterate over each primitive block type in the current cluster_placement_stats - for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { + for (int i = 0; i < cluster_placement_stats->num_pb_types; i++) { if (!cluster_placement_stats->valid_primitives[i].empty()) { t_cluster_placement_primitive* cur_cluster_placement_primitive = cluster_placement_stats->valid_primitives[i].begin()->second; - if (primitive_type_feasible(molecule->atom_block_ids[molecule->root], cur_cluster_placement_primitive->pb_graph_node->pb_type)) { + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + if (primitive_type_feasible(molecule.atom_block_ids[molecule.root], cur_cluster_placement_primitive->pb_graph_node->pb_type)) { // Iterate over the unordered_multimap of the valid primitives of a specific pb primitive type for (auto it = cluster_placement_stats->valid_primitives[i].begin(); it != cluster_placement_stats->valid_primitives[i].end(); /*loop increment is done inside the loop*/) { //Lazily remove invalid primitives @@ -233,10 +237,11 @@ bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_ } if (force_site == it->second->pb_graph_node->flat_site_index) { cost = try_place_molecule(cluster_placement_stats, - molecule, + molecule_id, it->second->pb_graph_node, - primitives_list); - if (cost < HUGE_POSITIVE_FLOAT) { + primitives_list, + prepacker); + if (cost < std::numeric_limits::max()) { cluster_placement_stats->move_primitive_to_inflight(i, it); return true; } else { @@ -250,9 +255,10 @@ bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_ /* try place molecule at root location cur */ cost = try_place_molecule(cluster_placement_stats, - molecule, + molecule_id, it->second->pb_graph_node, - primitives_list); + primitives_list, + prepacker); // if the cost is lower than the best, or is equal to the best but this // primitive is more available in the cluster mark it as the best primitive @@ -275,15 +281,17 @@ bool get_next_primitive_list(t_intra_cluster_placement_stats* cluster_placement_ if (!found_best) { /* failed to find a placement */ - for (i = 0; i < molecule->num_blocks; i++) { + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + for (size_t i = 0; i < molecule.atom_block_ids.size(); i++) { primitives_list[i] = nullptr; } } else { /* populate primitive list with best */ cost = try_place_molecule(cluster_placement_stats, - molecule, + molecule_id, best->second->pb_graph_node, - primitives_list); + primitives_list, + prepacker); VTR_ASSERT(cost == lowest_cost); /* take out best node and put it in flight */ @@ -313,7 +321,7 @@ static void reset_cluster_placement_stats(t_intra_cluster_placement_stats* clust primitive.second->valid = true; } } - cluster_placement_stats->curr_molecule = nullptr; + cluster_placement_stats->curr_molecule = PackMoleculeId::INVALID(); cluster_placement_stats->has_long_chain = false; } @@ -444,20 +452,18 @@ static void update_primitive_cost_or_status(t_intra_cluster_placement_stats* clu const t_pb_graph_node* pb_graph_node, const float incremental_cost, const bool valid) { - int i, j, k; - t_cluster_placement_primitive* placement_primitive; if (pb_graph_node->is_primitive()) { /* is primitive */ - placement_primitive = cluster_placement_stats->get_pb_graph_node_placement_primitive(pb_graph_node); + t_cluster_placement_primitive* placement_primitive = cluster_placement_stats->get_pb_graph_node_placement_primitive(pb_graph_node); if (valid) { placement_primitive->incremental_cost += incremental_cost; } else { placement_primitive->valid = false; } } else { - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; k++) { + for (int i = 0; i < pb_graph_node->pb_type->num_modes; i++) { + for (int j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { + for (int k = 0; k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; k++) { update_primitive_cost_or_status(cluster_placement_stats, &pb_graph_node->child_pb_graph_nodes[i][j][k], incremental_cost, valid); @@ -471,38 +477,40 @@ static void update_primitive_cost_or_status(t_intra_cluster_placement_stats* clu * Try place molecule at root location, populate primitives list with locations of placement if successful */ static float try_place_molecule(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, + PackMoleculeId molecule_id, t_pb_graph_node* root, - t_pb_graph_node** primitives_list) { - int list_size, i; - float cost = HUGE_POSITIVE_FLOAT; - list_size = get_array_size_of_molecule(molecule); + std::vector& primitives_list, + const Prepacker& prepacker) { + float cost = std::numeric_limits::max(); + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + size_t list_size = molecule.atom_block_ids.size(); - if (primitive_type_feasible(molecule->atom_block_ids[molecule->root], + if (primitive_type_feasible(molecule.atom_block_ids[molecule.root], root->pb_type)) { t_cluster_placement_primitive* root_placement_primitive = cluster_placement_stats->get_pb_graph_node_placement_primitive(root); if (root_placement_primitive->valid) { - for (i = 0; i < list_size; i++) { + for (size_t i = 0; i < list_size; i++) { primitives_list[i] = nullptr; } cost = root_placement_primitive->base_cost + root_placement_primitive->incremental_cost; - primitives_list[molecule->root] = root; - if (molecule->type == MOLECULE_FORCED_PACK) { + primitives_list[molecule.root] = root; + if (molecule.type == e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK) { if (!expand_forced_pack_molecule_placement(cluster_placement_stats, - molecule, - molecule->pack_pattern->root_block, + molecule_id, + molecule.pack_pattern->root_block, primitives_list, + prepacker, &cost)) { - return HUGE_POSITIVE_FLOAT; + return std::numeric_limits::max(); } } - for (i = 0; i < list_size; i++) { - VTR_ASSERT((primitives_list[i] == nullptr) == (!molecule->atom_block_ids[i])); - for (int j = 0; j < list_size; j++) { + for (size_t i = 0; i < list_size; i++) { + VTR_ASSERT((primitives_list[i] == nullptr) == (!molecule.atom_block_ids[i])); + for (size_t j = 0; j < list_size; j++) { if (i != j) { if (primitives_list[i] != nullptr && primitives_list[i] == primitives_list[j]) { - return HUGE_POSITIVE_FLOAT; + return std::numeric_limits::max(); } } } @@ -517,9 +525,10 @@ static float try_place_molecule(t_intra_cluster_placement_stats* cluster_placeme * Assumes molecule and pack pattern connections have fan-out 1 */ static bool expand_forced_pack_molecule_placement(t_intra_cluster_placement_stats* cluster_placement_stats, - const t_pack_molecule* molecule, + PackMoleculeId molecule_id, const t_pack_pattern_block* pack_pattern_block, - t_pb_graph_node** primitives_list, + std::vector& primitives_list, + const Prepacker& prepacker, float* cost) { t_pb_graph_node* pb_graph_node = primitives_list[pack_pattern_block->block_id]; t_pb_graph_node* next_primitive; @@ -534,7 +543,8 @@ static bool expand_forced_pack_molecule_placement(t_intra_cluster_placement_stat } else { next_block = cur->from_block; } - if (primitives_list[next_block->block_id] == nullptr && molecule->atom_block_ids[next_block->block_id]) { + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + if (primitives_list[next_block->block_id] == nullptr && molecule.atom_block_ids[next_block->block_id]) { /* first time visiting location */ /* find next primitive based on pattern connections, expand next primitive if not visited */ @@ -563,12 +573,12 @@ static bool expand_forced_pack_molecule_placement(t_intra_cluster_placement_stat if (next_pin != nullptr) { next_primitive = next_pin->parent_node; /* Check for legality of placement, if legal, expand from legal placement, if not, return false */ - if (molecule->atom_block_ids[next_block->block_id] && primitives_list[next_block->block_id] == nullptr) { + if (molecule.atom_block_ids[next_block->block_id] && primitives_list[next_block->block_id] == nullptr) { t_cluster_placement_primitive* next_placement_primitive = cluster_placement_stats->get_pb_graph_node_placement_primitive(next_primitive); - if (next_placement_primitive->valid && primitive_type_feasible(molecule->atom_block_ids[next_block->block_id], next_primitive->pb_type)) { + if (next_placement_primitive->valid && primitive_type_feasible(molecule.atom_block_ids[next_block->block_id], next_primitive->pb_type)) { primitives_list[next_block->block_id] = next_primitive; *cost += next_placement_primitive->base_cost + next_placement_primitive->incremental_cost; - if (!expand_forced_pack_molecule_placement(cluster_placement_stats, molecule, next_block, primitives_list, cost)) { + if (!expand_forced_pack_molecule_placement(cluster_placement_stats, molecule_id, next_block, primitives_list, prepacker, cost)) { return false; } } else { @@ -685,15 +695,6 @@ static t_pb_graph_pin* expand_pack_molecule_pin_edge(const int pattern_id, return dest_pin; } -/* Determine max index + 1 of molecule */ -int get_array_size_of_molecule(const t_pack_molecule* molecule) { - if (molecule->type == MOLECULE_FORCED_PACK) { - return molecule->pack_pattern->num_blocks; - } else { - return molecule->num_blocks; - } -} - /* Given atom block, determines if a free primitive exists for it */ bool exists_free_primitive_for_atom_block(t_intra_cluster_placement_stats* cluster_placement_stats, const AtomBlockId blk_id) { diff --git a/vpr/src/pack/cluster_placement.h b/vpr/src/pack/cluster_placement.h index f3d840457ca..2f3e438b0fd 100644 --- a/vpr/src/pack/cluster_placement.h +++ b/vpr/src/pack/cluster_placement.h @@ -9,7 +9,10 @@ #include #include #include "physical_types.h" -#include "vpr_types.h" +#include "prepack.h" + +// Forward declarations +class AtomBlockId; /** * @brief Stats keeper for placement within the cluster during packing @@ -18,9 +21,9 @@ */ class t_intra_cluster_placement_stats { public: - int num_pb_types; ///& primitives_list, + const Prepacker& prepacker, int force_site = -1); /** @@ -173,11 +177,6 @@ bool get_next_primitive_list( void commit_primitive(t_intra_cluster_placement_stats* cluster_placement_stats, const t_pb_graph_node* primitive); -/** - * @brief Determine max index + 1 of molecule - */ -int get_array_size_of_molecule(const t_pack_molecule* molecule); - /** * @brief Given atom block, determines if a free primitive exists for it, */ diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 1f10e556ad1..92d4b183dc5 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -34,6 +34,7 @@ #include "pb_type_graph.h" #include "lb_type_rr_graph.h" #include "cluster_router.h" +#include "atom_pb_bimap.h" /* #define PRINT_INTRA_LB_ROUTE */ @@ -74,10 +75,10 @@ class reservable_pq : public std::priority_queue { ******************************************************************************************/ static void free_lb_net_rt(t_lb_trace* lb_trace); static void free_lb_trace(t_lb_trace* lb_trace); -static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id); -static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id); +static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id, const AtomPBBimap& atom_to_pb); +static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id, const AtomPBBimap& atom_to_pb); -static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data); +static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data, const AtomPBBimap& atom_to_pb); static void commit_remove_rt(t_lb_trace* rt, t_lb_router_data* router_data, e_commit_remove op, std::unordered_map* mode_map, t_mode_selection_status* mode_status); static bool is_skip_route_net(t_lb_trace* rt, t_lb_router_data* router_data); @@ -248,17 +249,17 @@ static bool check_edge_for_route_conflicts(std::unordered_map& atoms_added = *router_data->atoms_added; if (atoms_added.count(blk_id) > 0) { - VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom %s added twice to router\n", atom_ctx.nlist.block_name(blk_id).c_str()); + VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom %s added twice to router\n", atom_ctx.netlist().block_name(blk_id).c_str()); } - pb = atom_ctx.lookup.atom_pb(blk_id); + pb = atom_to_pb.atom_pb(blk_id); VTR_ASSERT(pb); @@ -266,20 +267,20 @@ void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id) set_reset_pb_modes(router_data, pb, true); - for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) { - add_pin_to_rt_terminals(router_data, pin_id); + for (auto pin_id : atom_ctx.netlist().block_pins(blk_id)) { + add_pin_to_rt_terminals(router_data, pin_id, atom_to_pb); } - fix_duplicate_equivalent_pins(router_data); + fix_duplicate_equivalent_pins(router_data, atom_to_pb); } /* Remove pins of netlist atom from current routing drivers/targets */ -void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id) { +void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id, const AtomPBBimap& atom_to_pb) { auto& atom_ctx = g_vpr_ctx.atom(); std::map& atoms_added = *router_data->atoms_added; - const t_pb* pb = atom_ctx.lookup.atom_pb(blk_id); + const t_pb* pb = atom_to_pb.atom_pb(blk_id); if (atoms_added.count(blk_id) == 0) { return; @@ -287,8 +288,8 @@ void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId bl set_reset_pb_modes(router_data, pb, false); - for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) { - remove_pin_from_rt_terminals(router_data, pin_id); + for (auto pin_id : atom_ctx.netlist().block_pins(blk_id)) { + remove_pin_from_rt_terminals(router_data, pin_id, atom_to_pb); } atoms_added.erase(blk_id); @@ -356,7 +357,7 @@ static bool try_expand_nodes(t_lb_router_data* router_data, if (verbosity > 3) { //Print detailed debug info - auto& atom_nlist = g_vpr_ctx.atom().nlist; + auto& atom_nlist = g_vpr_ctx.atom().netlist(); AtomNetId net_id = lb_net->atom_net_id; AtomPinId driver_pin = lb_net->atom_pins[0]; AtomPinId sink_pin = lb_net->atom_pins[itarget]; @@ -507,7 +508,7 @@ bool try_intra_lb_route(t_lb_router_data* router_data, --inet; auto& atom_ctx = g_vpr_ctx.atom(); VTR_LOGV(verbosity > 3, "Net '%s' is impossible to route within proposed %s cluster\n", - atom_ctx.nlist.net_name(lb_nets[inet].atom_net_id).c_str(), router_data->lb_type->name.c_str()); + atom_ctx.netlist().net_name(lb_nets[inet].atom_net_id).c_str(), router_data->lb_type->name.c_str()); is_routed = false; } router_data->pres_con_fac *= router_data->params.pres_fac_mult; @@ -625,7 +626,7 @@ static void free_lb_trace(t_lb_trace* lb_trace) { /* Given a pin of a net, assign route tree terminals for it * Assumes that pin is not already assigned */ -static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id) { +static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id, const AtomPBBimap& atom_to_pb) { std::vector& lb_nets = *router_data->intra_lb_nets; std::vector& lb_type_graph = *router_data->lb_type_graph; t_logical_block_type_ptr lb_type = router_data->lb_type; @@ -633,11 +634,11 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin unsigned int ipos; auto& atom_ctx = g_vpr_ctx.atom(); - const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id); + const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.netlist(), atom_to_pb, pin_id); VTR_ASSERT(pb_graph_pin); - AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id); - AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id); + AtomPortId port_id = atom_ctx.netlist().pin_port(pin_id); + AtomNetId net_id = atom_ctx.netlist().pin_net(pin_id); if (!net_id) { //No net connected to this pin, so nothing to route @@ -675,7 +676,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin int source_terminal = get_lb_type_rr_graph_ext_source_index(lb_type); lb_nets[ipos].terminals.push_back(source_terminal); - AtomPinId net_driver_pin_id = atom_ctx.nlist.net_driver(net_id); + AtomPinId net_driver_pin_id = atom_ctx.netlist().net_driver(net_id); lb_nets[ipos].atom_pins.push_back(net_driver_pin_id); VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source"); @@ -683,11 +684,11 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size()); - if (atom_ctx.nlist.port_type(port_id) == PortType::OUTPUT) { + if (atom_ctx.netlist().port_type(port_id) == PortType::OUTPUT) { //The current pin is the net driver, overwrite the default driver at index 0 VTR_ASSERT_MSG(lb_nets[ipos].terminals[0] == get_lb_type_rr_graph_ext_source_index(lb_type), "Default driver must be external source"); - VTR_ASSERT(atom_ctx.nlist.pin_type(pin_id) == PinType::DRIVER); + VTR_ASSERT(atom_ctx.netlist().pin_type(pin_id) == PinType::DRIVER); //Override the default since this is the driver, and it is within the cluster lb_nets[ipos].terminals[0] = pb_graph_pin->pin_count_in_cluster; @@ -696,7 +697,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source"); int sink_terminal = OPEN; - if (lb_nets[ipos].terminals.size() < atom_ctx.nlist.net_pins(net_id).size()) { + if (lb_nets[ipos].terminals.size() < atom_ctx.netlist().net_pins(net_id).size()) { //Not all of the pins are within the cluster if (lb_nets[ipos].terminals.size() == 1) { //Only the source has been specified so far, must add cluster-external sink @@ -724,9 +725,9 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin } } else { //This is an input to a primitive - VTR_ASSERT(atom_ctx.nlist.port_type(port_id) == PortType::INPUT - || atom_ctx.nlist.port_type(port_id) == PortType::CLOCK); - VTR_ASSERT(atom_ctx.nlist.pin_type(pin_id) == PinType::SINK); + VTR_ASSERT(atom_ctx.netlist().port_type(port_id) == PortType::INPUT + || atom_ctx.netlist().port_type(port_id) == PortType::CLOCK); + VTR_ASSERT(atom_ctx.netlist().pin_type(pin_id) == PinType::SINK); //Get the rr node index associated with the pin int pin_index = pb_graph_pin->pin_count_in_cluster; @@ -738,7 +739,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin int sink_index = lb_type_graph[pin_index].outedges[0][0].node_index; VTR_ASSERT(lb_type_graph[sink_index].type == LB_SINK); - if (lb_nets[ipos].terminals.size() == atom_ctx.nlist.net_pins(net_id).size() && lb_nets[ipos].terminals[1] == get_lb_type_rr_graph_ext_sink_index(lb_type)) { + if (lb_nets[ipos].terminals.size() == atom_ctx.netlist().net_pins(net_id).size() && lb_nets[ipos].terminals[1] == get_lb_type_rr_graph_ext_sink_index(lb_type)) { /* If all sinks of net are all contained in the logic block, then the net does * not need to route out of the logic block, so can replace the external sink * with this last sink terminal */ @@ -753,7 +754,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size()); int num_lb_terminals = lb_nets[ipos].terminals.size(); - VTR_ASSERT(num_lb_terminals <= (int)atom_ctx.nlist.net_pins(net_id).size()); + VTR_ASSERT(num_lb_terminals <= (int)atom_ctx.netlist().net_pins(net_id).size()); VTR_ASSERT(num_lb_terminals >= 0); #ifdef VTR_ASSERT_SAFE_ENABLED @@ -767,7 +768,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin //Net driver VTR_ASSERT_SAFE_MSG(lb_type_graph[inode].type == LB_SOURCE, "Driver must be a source RR node"); VTR_ASSERT_SAFE_MSG(atom_pin, "Driver have an associated atom pin"); - VTR_ASSERT_SAFE_MSG(atom_ctx.nlist.pin_type(atom_pin) == PinType::DRIVER, "Source RR must be associated with a driver pin in atom netlist"); + VTR_ASSERT_SAFE_MSG(atom_ctx.netlist().pin_type(atom_pin) == PinType::DRIVER, "Source RR must be associated with a driver pin in atom netlist"); if (inode == get_lb_type_rr_graph_ext_source_index(lb_type)) { ++num_extern_sources; } @@ -781,7 +782,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin ++num_extern_sinks; } else { VTR_ASSERT_SAFE_MSG(atom_pin, "Intra-cluster sink must have an associated atom pin"); - VTR_ASSERT_SAFE_MSG(atom_ctx.nlist.pin_type(atom_pin) == PinType::SINK, "Intra-cluster Sink RR must be associated with a sink pin in atom netlist"); + VTR_ASSERT_SAFE_MSG(atom_ctx.netlist().pin_type(atom_pin) == PinType::SINK, "Intra-cluster Sink RR must be associated with a sink pin in atom netlist"); } } } @@ -792,7 +793,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin /* Given a pin of a net, remove route tree terminals from it */ -static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id) { +static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id, const AtomPBBimap& atom_to_pb) { std::vector& lb_nets = *router_data->intra_lb_nets; std::vector& lb_type_graph = *router_data->lb_type_graph; t_logical_block_type_ptr lb_type = router_data->lb_type; @@ -800,10 +801,10 @@ static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const At unsigned int ipos; auto& atom_ctx = g_vpr_ctx.atom(); - const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id); + const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.netlist(), atom_to_pb, pin_id); - AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id); - AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id); + AtomPortId port_id = atom_ctx.netlist().pin_port(pin_id); + AtomNetId net_id = atom_ctx.netlist().pin_net(pin_id); if (!net_id) { /* This is not a valid net */ @@ -824,7 +825,7 @@ static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const At VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size()); - auto port_type = atom_ctx.nlist.port_type(port_id); + auto port_type = atom_ctx.netlist().port_type(port_id); if (port_type == PortType::OUTPUT) { /* Net driver pin takes 0th position in terminals */ int sink_terminal; @@ -917,7 +918,7 @@ static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const At //To work around this, we fix all but one of these duplicate connections to route to specific pins, //(instead of the common sink). This ensures a legal routing is produced and that the duplicate pins //are not 'missing' in the clustered netlist. -static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data) { +static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data, const AtomPBBimap& atom_to_pb) { auto& atom_ctx = g_vpr_ctx.atom(); std::vector& lb_type_graph = *router_data->lb_type_graph; @@ -943,7 +944,7 @@ static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data) { AtomPinId atom_pin = lb_nets[ilb_net].atom_pins[iterm]; VTR_ASSERT(atom_pin); - const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin); + const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.netlist(), atom_to_pb, atom_pin); VTR_ASSERT(pb_graph_pin); if (pb_graph_pin->port->equivalent == PortEquivalence::NONE) continue; //Only need to remap equivalent ports @@ -955,7 +956,7 @@ static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data) { "Found duplicate nets connected to logically equivalent pins. " "Remapping intra lb net %d (atom net %zu '%s') from common sink " "pb_route %d to fixed pin pb_route %d\n", - ilb_net, size_t(lb_nets[ilb_net].atom_net_id), atom_ctx.nlist.net_name(lb_nets[ilb_net].atom_net_id).c_str(), + ilb_net, size_t(lb_nets[ilb_net].atom_net_id), atom_ctx.netlist().net_name(lb_nets[ilb_net].atom_net_id).c_str(), kv.first, pin_index); VTR_ASSERT(lb_type_graph[pin_index].type == LB_INTERMEDIATE); @@ -1290,7 +1291,7 @@ static void print_route(FILE* fp, t_lb_router_data* router_data) { for (unsigned int inet = 0; inet < lb_nets.size(); inet++) { AtomNetId net_id = lb_nets[inet].atom_net_id; - fprintf(fp, "net %s num targets %d \n", atom_ctx.nlist.net_name(net_id).c_str(), (int)lb_nets[inet].terminals.size()); + fprintf(fp, "net %s num targets %d \n", atom_ctx.netlist().net_name(net_id).c_str(), (int)lb_nets[inet].terminals.size()); fprintf(fp, "\tS"); print_trace(fp, lb_nets[inet].rt_tree, router_data); fprintf(fp, "\n\n"); @@ -1486,7 +1487,7 @@ static std::string describe_congested_rr_nodes(const std::vector& congested for (auto itr = range.first; itr != range.second; ++itr) { AtomNetId net = itr->second; description += vtr::string_fmt("\tNet: %s\n", - atom_ctx.nlist.net_name(net).c_str()); + atom_ctx.netlist().net_name(net).c_str()); } } diff --git a/vpr/src/pack/cluster_router.h b/vpr/src/pack/cluster_router.h index 4f88f1c0b6a..0b40f84c627 100644 --- a/vpr/src/pack/cluster_router.h +++ b/vpr/src/pack/cluster_router.h @@ -16,8 +16,8 @@ void free_router_data(t_lb_router_data* router_data); void free_intra_lb_nets(std::vector* intra_lb_nets); /* Routing Functions */ -void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id); -void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id); +void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id, const AtomPBBimap& atom_to_pb); +void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id, const AtomPBBimap& atom_to_pb); void set_reset_pb_modes(t_lb_router_data* router_data, const t_pb* pb, const bool set); bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_selection_status* mode_status); void reset_intra_lb_route(t_lb_router_data* router_data); diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index 736bde0ef59..dd307168a36 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -2,17 +2,13 @@ #include #include -#include "PreClusterTimingGraphResolver.h" -#include "PreClusterDelayCalculator.h" #include "atom_netlist.h" #include "attraction_groups.h" #include "cluster_legalizer.h" #include "clustered_netlist.h" -#include "concrete_timing_info.h" +#include "globals.h" #include "output_clustering.h" #include "prepack.h" -#include "tatum/TimingReporter.hpp" -#include "tatum/echo_writer.hpp" #include "vpr_context.h" /*Print the contents of each cluster to an echo file*/ @@ -33,7 +29,7 @@ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legali cluster_atoms.insert({cluster_id, std::vector()}); } - for (auto atom_blk_id : atom_ctx.nlist.blocks()) { + for (auto atom_blk_id : atom_ctx.netlist().blocks()) { LegalizationClusterId cluster_id = cluster_legalizer.get_atom_cluster(atom_blk_id); cluster_atoms[cluster_id].push_back(atom_blk_id); @@ -48,7 +44,7 @@ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legali for (auto j = 0; j < num_atoms; j++) { AtomBlockId atom_id = cluster_atom.second[j]; - fprintf(fp, "\t %s \n", atom_ctx.nlist.block_name(atom_id).c_str()); + fprintf(fp, "\t %s \n", atom_ctx.netlist().block_name(atom_id).c_str()); } } @@ -67,58 +63,6 @@ static void echo_clusters(char* filename, const ClusterLegalizer& cluster_legali fclose(fp); } -void calc_init_packing_timing(const t_packer_opts& packer_opts, - const t_analysis_opts& analysis_opts, - const Prepacker& prepacker, - std::shared_ptr& clustering_delay_calc, - std::shared_ptr& timing_info, - vtr::vector& atom_criticality) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - - /* - * Initialize the timing analyzer - */ - clustering_delay_calc = std::make_shared(atom_ctx.nlist, atom_ctx.lookup, packer_opts.inter_cluster_net_delay, prepacker); - timing_info = make_setup_timing_info(clustering_delay_calc, packer_opts.timing_update_type); - - //Calculate the initial timing - timing_info->update(); - - if (isEchoFileEnabled(E_ECHO_PRE_PACKING_TIMING_GRAPH)) { - auto& timing_ctx = g_vpr_ctx.timing(); - tatum::write_echo(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH), - *timing_ctx.graph, *timing_ctx.constraints, *clustering_delay_calc, timing_info->analyzer()); - - tatum::NodeId debug_tnode = id_or_pin_name_to_tnode(analysis_opts.echo_dot_timing_graph_node); - write_setup_timing_graph_dot(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH) + std::string(".dot"), - *timing_info, debug_tnode); - } - - { - auto& timing_ctx = g_vpr_ctx.timing(); - PreClusterTimingGraphResolver resolver(atom_ctx.nlist, - atom_ctx.lookup, *timing_ctx.graph, *clustering_delay_calc); - resolver.set_detail_level(analysis_opts.timing_report_detail); - - tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, - *timing_ctx.constraints); - - timing_reporter.report_timing_setup( - "pre_pack.report_timing.setup.rpt", - *timing_info->setup_analyzer(), - analysis_opts.timing_report_npaths); - } - - //Calculate true criticalities of each block - for (AtomBlockId blk : atom_ctx.nlist.blocks()) { - for (AtomPinId in_pin : atom_ctx.nlist.block_input_pins(blk)) { - //Max criticality over incoming nets - float crit = timing_info->setup_pin_criticality(in_pin); - atom_criticality[blk] = std::max(atom_criticality[blk], crit); - } - } -} - void check_and_output_clustering(ClusterLegalizer& cluster_legalizer, const t_packer_opts& packer_opts, const std::unordered_set& is_clock, @@ -163,8 +107,7 @@ void print_pack_status(int tot_num_molecules, int num_clusters_created = cluster_legalizer.clusters().size(); - if (mols_since_last_print >= int_molecule_increment || - num_molecules_processed == tot_num_molecules) { + if (mols_since_last_print >= int_molecule_increment || num_molecules_processed == tot_num_molecules) { VTR_LOG( "%6d/%-6d %3d%% " "%26d " @@ -210,7 +153,7 @@ void rebuild_attraction_groups(AttractionInfo& attraction_groups, std::map> identify_primitive_candidate_block_types() { std::map> model_candidates; - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); const DeviceContext& device_ctx = g_vpr_ctx.device(); std::set unique_models; @@ -452,13 +395,12 @@ void init_clb_atoms_lookup(vtr::vector& clustering_delay_calc, - std::shared_ptr& timing_info, - vtr::vector& atom_criticality); - /* * @brief Check clustering legality and output it. */ diff --git a/vpr/src/pack/constraints_report.cpp b/vpr/src/pack/constraints_report.cpp index 4d6b9a87e57..2c25cb5f8af 100644 --- a/vpr/src/pack/constraints_report.cpp +++ b/vpr/src/pack/constraints_report.cpp @@ -1,16 +1,12 @@ #include "constraints_report.h" #include "cluster_legalizer.h" -#include "globals.h" #include "grid_tile_lookup.h" -bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_legalizer) { +bool floorplan_constraints_regions_overfull(std::vector& overfull_partition_regions, + const ClusterLegalizer& cluster_legalizer, + const std::vector& logical_block_types) { GridTileLookup grid_tiles; - auto& floorplanning_ctx = g_vpr_ctx.mutable_floorplanning(); - auto& device_ctx = g_vpr_ctx.device(); - - const std::vector& block_types = device_ctx.logical_block_types; - // keep record of how many blocks of each type are assigned to each PartitionRegion std::unordered_map> pr_count_info; @@ -22,7 +18,7 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega t_logical_block_type_ptr bt = cluster_legalizer.get_cluster_type(cluster_id); auto got = pr_count_info.find(pr); if (got == pr_count_info.end()) { - std::vector block_type_counts(block_types.size(), 0); + std::vector block_type_counts(logical_block_types.size(), 0); block_type_counts[bt->index]++; pr_count_info.insert({pr, block_type_counts}); } else { @@ -35,7 +31,7 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega for (const auto& [pr, block_type_counts] : pr_count_info) { const std::vector& regions = pr.get_regions(); - for (const t_logical_block_type& block_type : block_types) { + for (const t_logical_block_type& block_type : logical_block_types) { int num_assigned_blocks = block_type_counts[block_type.index]; int num_tiles = std::accumulate(regions.begin(), regions.end(), 0, [&grid_tiles, &block_type](int acc, const Region& reg) -> int { return acc + grid_tiles.region_tile_count(reg, &block_type); @@ -43,10 +39,11 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega if (num_assigned_blocks > num_tiles) { floorplan_regions_overfull = true; - floorplanning_ctx.overfull_partition_regions.push_back(pr); - VTR_LOG("\n\nA partition including the following regions has been assigned %d blocks of type %s, " - "but only has %d tiles of that type\n", - num_assigned_blocks, block_type.name.c_str(), num_tiles); + overfull_partition_regions.push_back(pr); + VTR_LOG( + "\n\nA partition including the following regions has been assigned %d blocks of type %s, " + "but only has %d tiles of that type\n", + num_assigned_blocks, block_type.name.c_str(), num_tiles); for (const Region& reg : regions) { const vtr::Rect& rect = reg.get_rect(); const auto [layer_low, layer_high] = reg.get_layer_range(); @@ -55,7 +52,6 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega rect.xmax(), rect.ymax(), layer_high, reg.get_sub_tile()); } - } } } diff --git a/vpr/src/pack/constraints_report.h b/vpr/src/pack/constraints_report.h index c10d1183238..779f629ba69 100644 --- a/vpr/src/pack/constraints_report.h +++ b/vpr/src/pack/constraints_report.h @@ -2,10 +2,13 @@ * floorplan regions have been packed with too many clusters. */ -#ifndef VPR_SRC_PACK_CONSTRAINTS_REPORT_H_ -#define VPR_SRC_PACK_CONSTRAINTS_REPORT_H_ +#pragma once + +#include class ClusterLegalizer; +class PartitionRegion; +struct t_logical_block_type; /** * @brief Check if any constraint partition regions are overfull, @@ -23,8 +26,10 @@ class ClusterLegalizer; * VPR can still work if these assumptions do not hold true, but for tight overlapping * partitions, the placement engine may fail to find a legal placement. * + * Adds the overfilled partition regions to the overfull_partition_regions vector. + * * @return True if there is at least one overfull partition. */ -bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_legalizer); - -#endif /* VPR_SRC_PACK_CONSTRAINTS_REPORT_H_ */ +bool floorplan_constraints_regions_overfull(std::vector& overfull_partition_regions, + const ClusterLegalizer& cluster_legalizer, + const std::vector& logical_block_types); diff --git a/vpr/src/pack/greedy_candidate_selector.cpp b/vpr/src/pack/greedy_candidate_selector.cpp index 1b74a44aa66..b202035ec59 100644 --- a/vpr/src/pack/greedy_candidate_selector.cpp +++ b/vpr/src/pack/greedy_candidate_selector.cpp @@ -7,16 +7,24 @@ #include "greedy_candidate_selector.h" #include +#include +#include +#include +#include "PreClusterTimingManager.h" +#include "appack_context.h" +#include "flat_placement_types.h" +#include "flat_placement_utils.h" #include "atom_netlist.h" #include "attraction_groups.h" #include "cluster_legalizer.h" #include "cluster_placement.h" -#include "globals.h" +#include "greedy_clusterer.h" #include "prepack.h" #include "timing_info.h" -#include "vpr_context.h" #include "vpr_types.h" #include "vtr_assert.h" +#include "vtr_ndmatrix.h" +#include "vtr_vector.h" /* * @brief Get gain of packing molecule into current cluster. @@ -28,12 +36,14 @@ * * TODO: Confirm that this comment is correct. */ -static float get_molecule_gain(t_pack_molecule* molecule, +static float get_molecule_gain(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, AttractGroupId cluster_attraction_group_id, AttractionInfo& attraction_groups, int num_molecule_failures, - const AtomNetlist& atom_netlist); + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const APPackContext& appack_ctx); /* * @brief Remove blk from list of feasible blocks sorted according to gain. @@ -42,94 +52,177 @@ static float get_molecule_gain(t_pack_molecule* molecule, * has been found to be illegal, we don't repeatedly consider it. */ static void remove_molecule_from_pb_stats_candidates( - t_pack_molecule* molecule, - ClusterGainStats& cluster_gain_stats); + PackMoleculeId molecule_id, + ClusterGainStats& cluster_gain_stats); /* * @brief Add blk to list of feasible blocks sorted according to gain. */ static void add_molecule_to_pb_stats_candidates( - t_pack_molecule* molecule, - ClusterGainStats& cluster_gain_stats, - int max_queue_size, - AttractionInfo& attraction_groups, - const AtomNetlist& atom_netlist); + PackMoleculeId molecule_id, + ClusterGainStats& cluster_gain_stats, + t_logical_block_type_ptr cluster_type, + int max_queue_size, + AttractionInfo& attraction_groups, + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const APPackContext& appack_ctx); + +/** + * @brief Get the flat placement position of the given molecule. + */ +static t_flat_pl_loc get_molecule_pos(PackMoleculeId molecule_id, + const Prepacker& prepacker, + const APPackContext& appack_ctx) { + VTR_ASSERT_SAFE_MSG(appack_ctx.appack_options.use_appack, "APPack is not enabled"); + VTR_ASSERT_SAFE_MSG(molecule_id.is_valid(), "Molecule ID is invalid"); + AtomBlockId root_blk_id = prepacker.get_molecule_root_atom(molecule_id); + return appack_ctx.flat_placement_info.get_pos(root_blk_id); +} GreedyCandidateSelector::GreedyCandidateSelector( - const AtomNetlist& atom_netlist, - const Prepacker& prepacker, - const t_packer_opts& packer_opts, - bool allow_unrelated_clustering, - const t_molecule_stats& max_molecule_stats, - const std::map>& primitive_candidate_block_types, - const t_pack_high_fanout_thresholds& high_fanout_thresholds, - const std::unordered_set& is_clock, - const std::unordered_set& is_global, - const std::unordered_set& net_output_feeds_driving_block_input, - const SetupTimingInfo& timing_info, - int log_verbosity) - : atom_netlist_(atom_netlist), - packer_opts_(packer_opts), - allow_unrelated_clustering_(allow_unrelated_clustering), - log_verbosity_(log_verbosity), - primitive_candidate_block_types_(primitive_candidate_block_types), - high_fanout_thresholds_(high_fanout_thresholds), - is_clock_(is_clock), - is_global_(is_global), - net_output_feeds_driving_block_input_(net_output_feeds_driving_block_input), - timing_info_(timing_info) { - // Initialize the list of molecules to pack, the clustering data, and the - // net info. - - // Initialize unrelated clustering data. + const AtomNetlist& atom_netlist, + const Prepacker& prepacker, + const t_packer_opts& packer_opts, + bool allow_unrelated_clustering, + const t_molecule_stats& max_molecule_stats, + const std::map>& primitive_candidate_block_types, + const t_pack_high_fanout_thresholds& high_fanout_thresholds, + const std::unordered_set& is_clock, + const std::unordered_set& is_global, + const std::unordered_set& net_output_feeds_driving_block_input, + const PreClusterTimingManager& pre_cluster_timing_manager, + const APPackContext& appack_ctx, + int log_verbosity) + : atom_netlist_(atom_netlist) + , prepacker_(prepacker) + , packer_opts_(packer_opts) + , allow_unrelated_clustering_(allow_unrelated_clustering) + , log_verbosity_(log_verbosity) + , primitive_candidate_block_types_(primitive_candidate_block_types) + , high_fanout_thresholds_(high_fanout_thresholds) + , is_clock_(is_clock) + , is_global_(is_global) + , net_output_feeds_driving_block_input_(net_output_feeds_driving_block_input) + , pre_cluster_timing_manager_(pre_cluster_timing_manager) + , appack_ctx_(appack_ctx) + , rng_(0) { + + // Initialize unrelated clustering data if unrelated clustering is enabled. if (allow_unrelated_clustering_) { + initialize_unrelated_clustering_data(max_molecule_stats); + } + + /* TODO: This is memory inefficient, fix if causes problems */ + /* Store stats on nets used by packed block, useful for determining transitively connected blocks + * (eg. [A1, A2, ..]->[B1, B2, ..]->C implies cluster [A1, A2, ...] and C have a weak link) */ + clb_inter_blk_nets_.resize(atom_netlist.blocks().size()); +} + +void GreedyCandidateSelector::initialize_unrelated_clustering_data(const t_molecule_stats& max_molecule_stats) { + // Create a sorted list of molecules, sorted on decreasing molecule base + // gain. (Highest gain). + std::vector molecules_vector; + molecules_vector.assign(prepacker_.molecules().begin(), prepacker_.molecules().end()); + std::stable_sort(molecules_vector.begin(), + molecules_vector.end(), + [&](PackMoleculeId a_id, PackMoleculeId b_id) { + const t_pack_molecule& a = prepacker_.get_molecule(a_id); + const t_pack_molecule& b = prepacker_.get_molecule(b_id); + + return a.base_gain > b.base_gain; + }); + + if (appack_ctx_.appack_options.use_appack) { + /** + * For APPack, we build a spatial data structure where for each 1x1 grid + * position on the FPGA, we maintain lists of molecule candidates. + * The lists are in order of number of used external pins by the molecule. + * Within each list, the molecules are sorted by their base gain. + */ + // Get the max x, y, and layer from the flat placement. + t_flat_pl_loc max_loc({0.0f, 0.0f, 0.0f}); + for (PackMoleculeId mol_id : molecules_vector) { + t_flat_pl_loc mol_pos = get_molecule_pos(mol_id, prepacker_, appack_ctx_); + max_loc.x = std::max(max_loc.x, mol_pos.x); + max_loc.y = std::max(max_loc.y, mol_pos.y); + max_loc.layer = std::max(max_loc.layer, mol_pos.layer); + } + + VTR_ASSERT_MSG(max_loc.layer == 0, + "APPack unrelated clustering does not support 3D " + "FPGAs yet"); + + // Initialize the data structure with empty arrays with enough space + // for each molecule. + size_t flat_grid_width = max_loc.x + 1; + size_t flat_grid_height = max_loc.y + 1; + appack_unrelated_clustering_data_ = + vtr::NdMatrix>, 2>({flat_grid_width, + flat_grid_height}); + for (size_t x = 0; x < flat_grid_width; x++) { + for (size_t y = 0; y < flat_grid_height; y++) { + // Resize to the maximum number of used external pins. This is + // to ensure that every molecule below can be inserted into a + // valid list based on their number of external pins. + appack_unrelated_clustering_data_[x][y].resize(max_molecule_stats.num_used_ext_pins + 1); + } + } + + // Fill the grid with molecule information. + // Note: These molecules are sorted based on their base gain. They are + // inserted in such a way that the highest gain molecules appear + // first in the lists below. + for (PackMoleculeId mol_id : molecules_vector) { + t_flat_pl_loc mol_pos = get_molecule_pos(mol_id, prepacker_, appack_ctx_); + + //Figure out how many external inputs are used by this molecule + t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_); + int ext_inps = molecule_stats.num_used_ext_inputs; + + //Insert the molecule into the unclustered lists by number of external inputs + auto& tile_uc_data = appack_unrelated_clustering_data_[mol_pos.x][mol_pos.y]; + tile_uc_data[ext_inps].push_back(mol_id); + } + } else { + // When not performing APPack, allocate and load a similar data structure + // without spatial information. + /* alloc and load list of molecules to pack */ unrelated_clustering_data_.resize(max_molecule_stats.num_used_ext_inputs + 1); - // Create a sorted list of molecules, sorted on decreasing molecule base - // gain. (Highest gain). - std::vector molecules_vector = prepacker.get_molecules_vector(); - std::stable_sort(molecules_vector.begin(), - molecules_vector.end(), - [](t_pack_molecule* a, t_pack_molecule* b) { - return a->base_gain > b->base_gain; - }); - // Push back the each molecule into the unrelated clustering data vector // for their external inputs. This creates individual sorted lists of // molecules for each number of used external inputs. - for (t_pack_molecule* mol : molecules_vector) { + for (PackMoleculeId mol_id : molecules_vector) { //Figure out how many external inputs are used by this molecule - t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol, atom_netlist); + t_molecule_stats molecule_stats = prepacker_.calc_molecule_stats(mol_id, atom_netlist_); int ext_inps = molecule_stats.num_used_ext_inputs; //Insert the molecule into the unclustered lists by number of external inputs - unrelated_clustering_data_[ext_inps].push_back(mol); + unrelated_clustering_data_[ext_inps].push_back(mol_id); } } - - /* TODO: This is memory inefficient, fix if causes problems */ - /* Store stats on nets used by packed block, useful for determining transitively connected blocks - * (eg. [A1, A2, ..]->[B1, B2, ..]->C implies cluster [A1, A2, ...] and C have a weak link) */ - clb_inter_blk_nets_.resize(atom_netlist.blocks().size()); } GreedyCandidateSelector::~GreedyCandidateSelector() { } ClusterGainStats GreedyCandidateSelector::create_cluster_gain_stats( - t_pack_molecule* cluster_seed_mol, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + PackMoleculeId cluster_seed_mol_id, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { // Initialize the cluster gain stats. ClusterGainStats cluster_gain_stats; + cluster_gain_stats.seed_molecule_id = cluster_seed_mol_id; cluster_gain_stats.num_feasible_blocks = NOT_VALID; + cluster_gain_stats.has_done_connectivity_and_timing = false; // TODO: The reason this is being resized and not reserved is due to legacy // code which should be updated. cluster_gain_stats.feasible_blocks.resize(packer_opts_.feasible_block_array_size); for (int i = 0; i < packer_opts_.feasible_block_array_size; i++) - cluster_gain_stats.feasible_blocks[i] = nullptr; + cluster_gain_stats.feasible_blocks[i] = PackMoleculeId::INVALID(); cluster_gain_stats.tie_break_high_fanout_net = AtomNetId::INVALID(); cluster_gain_stats.explore_transitive_fanout = true; @@ -138,21 +231,41 @@ ClusterGainStats GreedyCandidateSelector::create_cluster_gain_stats( // TODO: We may want to update the cluster gain stats different, knowing // that this candidate was the seed molecule. update_cluster_gain_stats_candidate_success(cluster_gain_stats, - cluster_seed_mol, + cluster_seed_mol_id, cluster_id, cluster_legalizer, attraction_groups); + // If a flat placement is provided, set the centroid to be the location of + // the seed molecule. + if (appack_ctx_.appack_options.use_appack) { + t_flat_pl_loc seed_mol_pos = get_molecule_pos(cluster_seed_mol_id, + prepacker_, + appack_ctx_); + cluster_gain_stats.flat_cluster_position = seed_mol_pos; + cluster_gain_stats.mol_pos_sum = seed_mol_pos; + } + + // Mark if this cluster is a memory block. We detect this by checking if the + // class type of the seed primitive pb is a memory class. + // This is used by APPack to turn off certain optimizations which interfere + // with RAM packing. + const auto& seed_mol = prepacker_.get_molecule(cluster_seed_mol_id); + AtomBlockId seed_atom = seed_mol.atom_block_ids[seed_mol.root]; + const auto seed_pb = cluster_legalizer.atom_pb_lookup().atom_pb(seed_atom); + cluster_gain_stats.is_memory = seed_pb->pb_graph_node->pb_type->class_type == MEMORY_CLASS; + // Return the cluster gain stats. return cluster_gain_stats; } void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( - ClusterGainStats& cluster_gain_stats, - t_pack_molecule* successful_mol, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + ClusterGainStats& cluster_gain_stats, + PackMoleculeId successful_mol_id, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { + VTR_ASSERT(successful_mol_id.is_valid()); // TODO: If this threshold lookup gets expensive, move outside. int high_fanout_net_threshold = high_fanout_thresholds_.get_threshold(cluster_legalizer.get_cluster_type(cluster_id)->name); @@ -162,9 +275,8 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( // pins, and clock structures, in order to reflect the new content of the // cluster. Also keeps track of which attraction group the cluster belongs // to. - int molecule_size = get_array_size_of_molecule(successful_mol); - for (int iblock = 0; iblock < molecule_size; iblock++) { - AtomBlockId blk_id = successful_mol->atom_block_ids[iblock]; + const t_pack_molecule& successful_mol = prepacker_.get_molecule(successful_mol_id); + for (AtomBlockId blk_id : successful_mol.atom_block_ids) { if (!blk_id) { continue; } @@ -174,6 +286,7 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( /* reset list of feasible blocks */ cluster_gain_stats.num_feasible_blocks = NOT_VALID; + cluster_gain_stats.has_done_connectivity_and_timing = false; /* TODO: Allow clusters to have more than one attraction group. */ if (atom_grp_id.is_valid()) cluster_gain_stats.attraction_grp_id = atom_grp_id; @@ -224,26 +337,47 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( e_net_relation_to_clustered_block::INPUT); } + // TODO: For flat placement reconstruction, should we mark the molecules + // in the same tile as the seed of this cluster? + update_total_gain(cluster_gain_stats, attraction_groups); } // if this molecule came from the transitive fanout candidates remove it - cluster_gain_stats.transitive_fanout_candidates.erase(successful_mol->atom_block_ids[successful_mol->root]); + cluster_gain_stats.transitive_fanout_candidates.erase(successful_mol.atom_block_ids[successful_mol.root]); cluster_gain_stats.explore_transitive_fanout = true; // Whenever a new molecule has been clustered, reset the number of // unrelated clustering attempts. num_unrelated_clustering_attempts_ = 0; + + // If using APPack, update the position of the cluster based on the addition + // of this molecule. + if (appack_ctx_.appack_options.use_appack) { + t_flat_pl_loc successful_mol_pos = get_molecule_pos(successful_mol_id, + prepacker_, + appack_ctx_); + // Accumulate the molecules position into the position sum. + cluster_gain_stats.mol_pos_sum += successful_mol_pos; + + if (appack_ctx_.appack_options.cluster_location_ty == t_appack_options::e_cl_loc_ty::CENTROID) { + // If the cluster's position is defined as the centroid of the + // positions of the mols it contains, compute the new centroid. + cluster_gain_stats.flat_cluster_position = cluster_gain_stats.mol_pos_sum; + size_t num_mols_in_cluster = cluster_legalizer.get_num_molecules_in_cluster(cluster_id); + cluster_gain_stats.flat_cluster_position /= static_cast(num_mols_in_cluster); + } + } } void GreedyCandidateSelector::mark_and_update_partial_gain( - ClusterGainStats& cluster_gain_stats, - AtomNetId net_id, - e_gain_update gain_flag, - AtomBlockId clustered_blk_id, - const ClusterLegalizer& cluster_legalizer, - int high_fanout_net_threshold, - e_net_relation_to_clustered_block net_relation_to_clustered_block) { + ClusterGainStats& cluster_gain_stats, + AtomNetId net_id, + e_gain_update gain_flag, + AtomBlockId clustered_blk_id, + const ClusterLegalizer& cluster_legalizer, + int high_fanout_net_threshold, + e_net_relation_to_clustered_block net_relation_to_clustered_block) { if (int(atom_netlist_.net_sinks(net_id).size()) > high_fanout_net_threshold) { /* Optimization: It can be too runtime costly for marking all sinks for @@ -310,17 +444,13 @@ void GreedyCandidateSelector::mark_and_update_partial_gain( cluster_gain_stats.num_pins_of_net_in_pb[net_id]++; } -/* - * @brief Determine if atom block is in pb. - * - * TODO: This would make more sense in the cluster legalizer class. +/** + * @brief Determine if pb is a child of cluster_pb. */ -static bool is_atom_blk_in_pb(const AtomBlockId blk_id, const t_pb* pb) { - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - - const t_pb* cur_pb = atom_ctx.lookup.atom_pb(blk_id); +static bool is_pb_in_cluster_pb(const t_pb* pb, const t_pb* cluster_pb) { + const t_pb* cur_pb = pb; while (cur_pb) { - if (cur_pb == pb) { + if (cur_pb == cluster_pb) { return true; } cur_pb = cur_pb->parent_pb; @@ -329,20 +459,15 @@ static bool is_atom_blk_in_pb(const AtomBlockId blk_id, const t_pb* pb) { } void GreedyCandidateSelector::update_connection_gain_values( - ClusterGainStats& cluster_gain_stats, - AtomNetId net_id, - AtomBlockId clustered_blk_id, - const ClusterLegalizer& cluster_legalizer, - e_net_relation_to_clustered_block net_relation_to_clustered_block) { + ClusterGainStats& cluster_gain_stats, + AtomNetId net_id, + AtomBlockId clustered_blk_id, + const ClusterLegalizer& cluster_legalizer, + e_net_relation_to_clustered_block net_relation_to_clustered_block) { /*This function is called when the connection_gain values on the net net_id *require updating. */ - // Atom Context used to lookup the atom pb. - // TODO: Should investigate this. Using the atom pb in this class is very - // strange. - const AtomContext& atom_ctx = g_vpr_ctx.atom(); - int num_internal_connections, num_open_connections, num_stuck_connections; num_internal_connections = num_open_connections = num_stuck_connections = 0; @@ -351,8 +476,12 @@ void GreedyCandidateSelector::update_connection_gain_values( /* may wish to speed things up by ignoring clock nets since they are high fanout */ for (AtomPinId pin_id : atom_netlist_.net_pins(net_id)) { AtomBlockId blk_id = atom_netlist_.pin_block(pin_id); - if (cluster_legalizer.get_atom_cluster(blk_id) == legalization_cluster_id - && is_atom_blk_in_pb(blk_id, atom_ctx.lookup.atom_pb(clustered_blk_id))) { + // TODO: Should investigate this. Using the atom pb bimap through is_atom_blk_in_cluster_block + // in this class is very strange + const t_pb* pin_block_pb = cluster_legalizer.atom_pb_lookup().atom_pb(blk_id); + const t_pb* cluster_pb = cluster_legalizer.atom_pb_lookup().atom_pb(clustered_blk_id); + + if (cluster_legalizer.get_atom_cluster(blk_id) == legalization_cluster_id && is_pb_in_cluster_pb(pin_block_pb, cluster_pb)) { num_internal_connections++; } else if (!cluster_legalizer.is_atom_clustered(blk_id)) { num_open_connections++; @@ -402,10 +531,10 @@ void GreedyCandidateSelector::update_connection_gain_values( } void GreedyCandidateSelector::update_timing_gain_values( - ClusterGainStats& cluster_gain_stats, - AtomNetId net_id, - const ClusterLegalizer& cluster_legalizer, - e_net_relation_to_clustered_block net_relation_to_clustered_block) { + ClusterGainStats& cluster_gain_stats, + AtomNetId net_id, + const ClusterLegalizer& cluster_legalizer, + e_net_relation_to_clustered_block net_relation_to_clustered_block) { /*This function is called when the timing_gain values on the atom net *net_id requires updating. */ @@ -416,12 +545,15 @@ void GreedyCandidateSelector::update_timing_gain_values( if (net_output_feeds_driving_block_input_.count(net_id) != 0) pins = atom_netlist_.net_sinks(net_id); + // Get the setup timing info used to compute timing gain terms. + const SetupTimingInfo& timing_info = pre_cluster_timing_manager_.get_timing_info(); + if (net_relation_to_clustered_block == e_net_relation_to_clustered_block::OUTPUT && !is_global_.count(net_id)) { for (AtomPinId pin_id : pins) { AtomBlockId blk_id = atom_netlist_.pin_block(pin_id); if (!cluster_legalizer.is_atom_clustered(blk_id)) { - double timing_gain = timing_info_.setup_pin_criticality(pin_id); + double timing_gain = timing_info.setup_pin_criticality(pin_id); if (cluster_gain_stats.timing_gain.count(blk_id) == 0) { cluster_gain_stats.timing_gain[blk_id] = 0; @@ -441,7 +573,7 @@ void GreedyCandidateSelector::update_timing_gain_values( if (!cluster_legalizer.is_atom_clustered(new_blk_id)) { for (AtomPinId pin_id : atom_netlist_.net_sinks(net_id)) { - double timing_gain = timing_info_.setup_pin_criticality(pin_id); + double timing_gain = timing_info.setup_pin_criticality(pin_id); if (cluster_gain_stats.timing_gain.count(new_blk_id) == 0) { cluster_gain_stats.timing_gain[new_blk_id] = 0; @@ -466,6 +598,9 @@ void GreedyCandidateSelector::update_total_gain(ClusterGainStats& cluster_gain_s if (cluster_gain_stats.sharing_gain.count(blk_id) == 0) { cluster_gain_stats.sharing_gain[blk_id] = 0; } + if (cluster_gain_stats.timing_gain.count(blk_id) == 0) { + cluster_gain_stats.timing_gain[blk_id] = 0; + } AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); if (atom_grp_id != AttractGroupId::INVALID() && atom_grp_id == cluster_att_grp_id) { @@ -486,39 +621,40 @@ void GreedyCandidateSelector::update_total_gain(ClusterGainStats& cluster_gain_s if (packer_opts_.connection_driven) { /*try to absorb as many connections as possible*/ cluster_gain_stats.gain[blk_id] = ((1 - packer_opts_.beta) - * (float)cluster_gain_stats.sharing_gain[blk_id] - + packer_opts_.beta * (float)cluster_gain_stats.connection_gain[blk_id]) - / (num_used_pins); + * (float)cluster_gain_stats.sharing_gain[blk_id] + + packer_opts_.beta * (float)cluster_gain_stats.connection_gain[blk_id]) + / (num_used_pins); } else { cluster_gain_stats.gain[blk_id] = ((float)cluster_gain_stats.sharing_gain[blk_id]) - / (num_used_pins); + / (num_used_pins); } /* Add in timing driven cost into cost function */ if (packer_opts_.timing_driven) { cluster_gain_stats.gain[blk_id] = packer_opts_.alpha - * cluster_gain_stats.timing_gain[blk_id] - + (1.0 - packer_opts_.alpha) * (float)cluster_gain_stats.gain[blk_id]; + * cluster_gain_stats.timing_gain[blk_id] + + (1.0 - packer_opts_.alpha) * (float)cluster_gain_stats.gain[blk_id]; } } } -void GreedyCandidateSelector::update_cluster_gain_stats_candidate_failed(ClusterGainStats& cluster_gain_stats, - t_pack_molecule* failed_mol) { - auto got = cluster_gain_stats.atom_failures.find(failed_mol->atom_block_ids[0]); - if (got == cluster_gain_stats.atom_failures.end()) { - cluster_gain_stats.atom_failures.insert({failed_mol->atom_block_ids[0], 1}); +void GreedyCandidateSelector::update_cluster_gain_stats_candidate_failed( + ClusterGainStats& cluster_gain_stats, + PackMoleculeId failed_mol_id) { + VTR_ASSERT(failed_mol_id.is_valid()); + auto got = cluster_gain_stats.mol_failures.find(failed_mol_id); + if (got == cluster_gain_stats.mol_failures.end()) { + cluster_gain_stats.mol_failures.insert({failed_mol_id, 1}); } else { got->second++; } } -t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - const Prepacker& prepacker, - AttractionInfo& attraction_groups) { +PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { /* Finds the block with the greatest gain that satisfies the * input, clock and capacity constraints of a cluster that are * passed in. If no suitable block is found it returns nullptr. @@ -546,11 +682,12 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( // 1. Find unpacked molecules based on criticality and strong connectedness (connected by low fanout nets) with current cluster if (cluster_gain_stats.num_feasible_blocks == NOT_VALID) { + cluster_gain_stats.num_feasible_blocks = 0; add_cluster_molecule_candidates_by_connectivity_and_timing(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); + cluster_gain_stats.has_done_connectivity_and_timing = true; } if (packer_opts_.prioritize_transitive_connectivity) { @@ -558,7 +695,6 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } @@ -567,7 +703,6 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } @@ -576,7 +711,6 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } @@ -585,7 +719,6 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } @@ -595,13 +728,13 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( if (cluster_gain_stats.num_feasible_blocks == 0) { add_cluster_molecule_candidates_by_attraction_group(cluster_gain_stats, cluster_id, - prepacker, cluster_legalizer, attraction_groups); } + /* Grab highest gain molecule */ // If this was a vector, this would just be a pop_back. - t_pack_molecule* best_molecule = nullptr; + PackMoleculeId best_molecule = PackMoleculeId::INVALID(); if (cluster_gain_stats.num_feasible_blocks > 0) { cluster_gain_stats.num_feasible_blocks--; int index = cluster_gain_stats.num_feasible_blocks; @@ -611,16 +744,24 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( // If we are allowing unrelated clustering and no molecule has been found, // get unrelated candidate for cluster. - if (allow_unrelated_clustering_ && best_molecule == nullptr) { - if (num_unrelated_clustering_attempts_ < max_unrelated_clustering_attempts_) { - best_molecule = get_unrelated_candidate_for_cluster(cluster_id, - cluster_legalizer); - num_unrelated_clustering_attempts_++; - VTR_LOGV(best_molecule && log_verbosity_ > 2, - "\tFound unrelated molecule to cluster\n"); + if (allow_unrelated_clustering_ && best_molecule == PackMoleculeId::INVALID()) { + const t_appack_options& appack_options = appack_ctx_.appack_options; + if (appack_options.use_appack) { + if (num_unrelated_clustering_attempts_ < appack_options.max_unrelated_clustering_attempts) { + best_molecule = get_unrelated_candidate_for_cluster_appack(cluster_gain_stats, + cluster_id, + cluster_legalizer); + num_unrelated_clustering_attempts_++; + } } else { - num_unrelated_clustering_attempts_ = 0; + if (num_unrelated_clustering_attempts_ < max_unrelated_clustering_attempts_) { + best_molecule = get_unrelated_candidate_for_cluster(cluster_id, + cluster_legalizer); + num_unrelated_clustering_attempts_++; + } } + VTR_LOGV(best_molecule && log_verbosity_ > 2, + "\tFound unrelated molecule to cluster\n"); } else { VTR_LOGV(!best_molecule && log_verbosity_ > 2, "\tNo related molecule found and unrelated clustering disabled\n"); @@ -630,68 +771,65 @@ t_pack_molecule* GreedyCandidateSelector::get_next_candidate_for_cluster( } void GreedyCandidateSelector::add_cluster_molecule_candidates_by_connectivity_and_timing( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { - VTR_ASSERT(cluster_gain_stats.num_feasible_blocks == NOT_VALID); - - cluster_gain_stats.num_feasible_blocks = 0; + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { cluster_gain_stats.explore_transitive_fanout = true; /* If no legal molecules found, enable exploration of molecules two hops away */ for (AtomBlockId blk_id : cluster_gain_stats.marked_blocks) { // Get the molecule that contains this block. - t_pack_molecule* molecule = prepacker.get_atom_molecule(blk_id); + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(blk_id); // Add the molecule as a candidate if the molecule is not clustered and // is compatible with this cluster (using simple checks). - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), packer_opts_.feasible_block_array_size, attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); } } } void GreedyCandidateSelector::add_cluster_molecule_candidates_by_transitive_connectivity( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { //TODO: For now, only done by fan-out; should also consider fan-in cluster_gain_stats.explore_transitive_fanout = false; /* First time finding transitive fanout candidates therefore alloc and load them */ load_transitive_fanout_candidates(cluster_gain_stats, legalization_cluster_id, - prepacker, cluster_legalizer); /* Only consider candidates that pass a very simple legality check */ for (const auto& transitive_candidate : cluster_gain_stats.transitive_fanout_candidates) { - t_pack_molecule* molecule = transitive_candidate.second; - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + PackMoleculeId molecule_id = transitive_candidate.second; + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_TRANSITIVE_EXPLORE), attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); } } } void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_connectivity( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { /* Because the packer ignores high fanout nets when marking what blocks * to consider, use one of the ignored high fanout net to fill up lightly * related blocks */ @@ -706,15 +844,17 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn AtomBlockId blk_id = atom_netlist_.pin_block(pin_id); - t_pack_molecule* molecule = prepacker.get_atom_molecule(blk_id); - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(blk_id); + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_HIGH_FANOUT_EXPLORE), attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); count++; } } @@ -722,11 +862,10 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn } void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_group( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups) { auto cluster_type = cluster_legalizer.get_cluster_type(legalization_cluster_id); /* @@ -766,42 +905,38 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou if (num_available_atoms < attraction_group_num_atoms_threshold_) { for (AtomBlockId atom_id : available_atoms) { //Only consider molecules that are unpacked and of the correct type - t_pack_molecule* molecule = prepacker.get_atom_molecule(atom_id); - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(atom_id); + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), packer_opts_.feasible_block_array_size, attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); } } return; } - int min = 0; - int max = num_available_atoms - 1; - for (int j = 0; j < attraction_group_num_atoms_threshold_; j++) { - // FIXME: This is a non-deterministic random number generator and it is - // overkill to what this needs to be. Should use vtr::irand which - // would be faster. - std::random_device rd; - std::mt19937 gen(rd()); - std::uniform_int_distribution<> distr(min, max); - int selected_atom = distr(gen); + //Get a random atom between 0 and the number of available atoms - 1 + int selected_atom = rng_.irand(num_available_atoms - 1); AtomBlockId blk_id = available_atoms[selected_atom]; //Only consider molecules that are unpacked and of the correct type - t_pack_molecule* molecule = prepacker.get_atom_molecule(blk_id); - if (!cluster_legalizer.is_mol_clustered(molecule) && - cluster_legalizer.is_molecule_compatible(molecule, legalization_cluster_id)) { - add_molecule_to_pb_stats_candidates(molecule, + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(blk_id); + if (!cluster_legalizer.is_mol_clustered(molecule_id) && cluster_legalizer.is_molecule_compatible(molecule_id, legalization_cluster_id)) { + add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, + cluster_legalizer.get_cluster_type(legalization_cluster_id), packer_opts_.feasible_block_array_size, attraction_groups, - atom_netlist_); + prepacker_, + atom_netlist_, + appack_ctx_); } } } @@ -809,11 +944,40 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou /* * @brief Add blk to list of feasible blocks sorted according to gain. */ -static void add_molecule_to_pb_stats_candidates(t_pack_molecule* molecule, +static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, + t_logical_block_type_ptr cluster_type, int max_queue_size, AttractionInfo& attraction_groups, - const AtomNetlist& atom_netlist) { + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const APPackContext& appack_ctx) { + + // If using APPack, before adding this molecule to the candidates, check to + // see if the molecule is too far away from the position of the cluster. + // If so, do not add it to the list of candidates. + if (appack_ctx.appack_options.use_appack) { + // If this cluster is a memory block, do not drop candidates based on + // distance. Was found to create too many RAM blocks. + if (!cluster_gain_stats.is_memory) { + // Get the max dist for this block type. + float max_dist = appack_ctx.appack_options.max_candidate_distance; + // If this cluster is anything but a logic block type, then scale + // up the max distance. + if (cluster_type->index != appack_ctx.appack_options.logic_block_type_index) + max_dist *= appack_ctx.appack_options.max_candidate_distance_non_lb_scale; + + // If the distance from the cluster to the candidate is too large, + // do not add this molecule to the list of candidates. + const t_flat_pl_loc mol_loc = get_molecule_pos(molecule_id, + prepacker, + appack_ctx); + float dist = get_manhattan_distance(mol_loc, cluster_gain_stats.flat_cluster_position); + if (dist > max_dist) + return; + } + } + int num_molecule_failures = 0; AttractGroupId cluster_att_grp = cluster_gain_stats.attraction_grp_id; @@ -823,55 +987,56 @@ static void add_molecule_to_pb_stats_candidates(t_pack_molecule* molecule, * more molecules helps to achieve this purpose. */ if (attraction_groups.num_attraction_groups() > 0) { - auto got = cluster_gain_stats.atom_failures.find(molecule->atom_block_ids[0]); - if (got == cluster_gain_stats.atom_failures.end()) { + VTR_ASSERT(molecule_id.is_valid()); + auto got = cluster_gain_stats.mol_failures.find(molecule_id); + if (got == cluster_gain_stats.mol_failures.end()) { num_molecule_failures = 0; } else { num_molecule_failures = got->second; } if (num_molecule_failures > 0) { - remove_molecule_from_pb_stats_candidates(molecule, cluster_gain_stats); + remove_molecule_from_pb_stats_candidates(molecule_id, cluster_gain_stats); return; } } for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule) { + if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { return; // already in queue, do nothing } } if (cluster_gain_stats.num_feasible_blocks >= max_queue_size - 1) { /* maximum size for array, remove smallest gain element and sort */ - if (get_molecule_gain(molecule, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist) > get_molecule_gain(cluster_gain_stats.feasible_blocks[0], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist)) { + if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(cluster_gain_stats.feasible_blocks[0], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { /* single loop insertion sort */ int j; for (j = 0; j < cluster_gain_stats.num_feasible_blocks - 1; j++) { - if (get_molecule_gain(molecule, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist) <= get_molecule_gain(cluster_gain_stats.feasible_blocks[j + 1], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist)) { - cluster_gain_stats.feasible_blocks[j] = molecule; + if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) <= get_molecule_gain(cluster_gain_stats.feasible_blocks[j + 1], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { + cluster_gain_stats.feasible_blocks[j] = molecule_id; break; } else { cluster_gain_stats.feasible_blocks[j] = cluster_gain_stats.feasible_blocks[j + 1]; } } if (j == cluster_gain_stats.num_feasible_blocks - 1) { - cluster_gain_stats.feasible_blocks[j] = molecule; + cluster_gain_stats.feasible_blocks[j] = molecule_id; } } } else { /* Expand array and single loop insertion sort */ int j; for (j = cluster_gain_stats.num_feasible_blocks - 1; j >= 0; j--) { - if (get_molecule_gain(cluster_gain_stats.feasible_blocks[j], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist) > get_molecule_gain(molecule, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, atom_netlist)) { + if (get_molecule_gain(cluster_gain_stats.feasible_blocks[j], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { cluster_gain_stats.feasible_blocks[j + 1] = cluster_gain_stats.feasible_blocks[j]; } else { - cluster_gain_stats.feasible_blocks[j + 1] = molecule; + cluster_gain_stats.feasible_blocks[j + 1] = molecule_id; break; } } if (j < 0) { - cluster_gain_stats.feasible_blocks[0] = molecule; + cluster_gain_stats.feasible_blocks[0] = molecule_id; } cluster_gain_stats.num_feasible_blocks++; } @@ -883,14 +1048,14 @@ static void add_molecule_to_pb_stats_candidates(t_pack_molecule* molecule, * Useful for removing blocks that are repeatedly failing. If a block * has been found to be illegal, we don't repeatedly consider it. */ -static void remove_molecule_from_pb_stats_candidates(t_pack_molecule* molecule, +static void remove_molecule_from_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats) { int molecule_index; bool found_molecule = false; //find the molecule index for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule) { + if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { found_molecule = true; molecule_index = i; } @@ -916,68 +1081,97 @@ static void remove_molecule_from_pb_stats_candidates(t_pack_molecule* molecule, * + molecule_base_gain*some_factor * - introduced_input_nets_of_unrelated_blocks_pulled_in_by_molecule*some_other_factor */ -static float get_molecule_gain(t_pack_molecule* molecule, +static float get_molecule_gain(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, AttractGroupId cluster_attraction_group_id, AttractionInfo& attraction_groups, int num_molecule_failures, - const AtomNetlist& atom_netlist) { + const Prepacker& prepacker, + const AtomNetlist& atom_netlist, + const APPackContext& appack_ctx) { + VTR_ASSERT(molecule_id.is_valid()); + const t_pack_molecule& molecule = prepacker.get_molecule(molecule_id); + float gain = 0; constexpr float attraction_group_penalty = 0.1; int num_introduced_inputs_of_indirectly_related_block = 0; - for (int i = 0; i < get_array_size_of_molecule(molecule); i++) { - AtomBlockId blk_id = molecule->atom_block_ids[i]; - if (blk_id) { - if (cluster_gain_stats.gain.count(blk_id) > 0) { - gain += cluster_gain_stats.gain[blk_id]; - } else { - /* This block has no connection with current cluster, penalize molecule for having this block - */ - for (auto pin_id : atom_netlist.block_input_pins(blk_id)) { - auto net_id = atom_netlist.pin_net(pin_id); - VTR_ASSERT(net_id); - - auto driver_pin_id = atom_netlist.net_driver(net_id); - VTR_ASSERT(driver_pin_id); - - auto driver_blk_id = atom_netlist.pin_block(driver_pin_id); - - num_introduced_inputs_of_indirectly_related_block++; - for (int iblk = 0; iblk < get_array_size_of_molecule(molecule); iblk++) { - if (molecule->atom_block_ids[iblk] && driver_blk_id == molecule->atom_block_ids[iblk]) { - //valid block which is driver (and hence not an input) - num_introduced_inputs_of_indirectly_related_block--; - break; - } + for (AtomBlockId blk_id : molecule.atom_block_ids) { + if (!blk_id.is_valid()) + continue; + + if (cluster_gain_stats.gain.count(blk_id) > 0) { + gain += cluster_gain_stats.gain[blk_id]; + } else { + /* This block has no connection with current cluster, penalize molecule for having this block + */ + for (auto pin_id : atom_netlist.block_input_pins(blk_id)) { + auto net_id = atom_netlist.pin_net(pin_id); + VTR_ASSERT(net_id); + + auto driver_pin_id = atom_netlist.net_driver(net_id); + VTR_ASSERT(driver_pin_id); + + auto driver_blk_id = atom_netlist.pin_block(driver_pin_id); + + num_introduced_inputs_of_indirectly_related_block++; + for (AtomBlockId blk_id_2 : molecule.atom_block_ids) { + if (blk_id_2.is_valid() && driver_blk_id == blk_id_2) { + //valid block which is driver (and hence not an input) + num_introduced_inputs_of_indirectly_related_block--; + break; } } } - AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); - if (atom_grp_id == cluster_attraction_group_id && cluster_attraction_group_id != AttractGroupId::INVALID()) { - float att_grp_gain = attraction_groups.get_attraction_group_gain(atom_grp_id); - gain += att_grp_gain; - } else if (cluster_attraction_group_id != AttractGroupId::INVALID() && atom_grp_id != cluster_attraction_group_id) { - gain -= attraction_group_penalty; - } + } + AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); + if (atom_grp_id == cluster_attraction_group_id && cluster_attraction_group_id != AttractGroupId::INVALID()) { + float att_grp_gain = attraction_groups.get_attraction_group_gain(atom_grp_id); + gain += att_grp_gain; + } else if (cluster_attraction_group_id != AttractGroupId::INVALID() && atom_grp_id != cluster_attraction_group_id) { + gain -= attraction_group_penalty; } } - gain += molecule->base_gain * 0.0001; /* Use base gain as tie breaker TODO: need to sweep this value and perhaps normalize */ + gain += molecule.base_gain * 0.0001; /* Use base gain as tie breaker TODO: need to sweep this value and perhaps normalize */ gain -= num_introduced_inputs_of_indirectly_related_block * (0.001); if (num_molecule_failures > 0 && attraction_groups.num_attraction_groups() > 0) { gain -= 0.1 * num_molecule_failures; } + // If using APPack, attenuate the gain. + // NOTE: We do not perform gain attenuation if the current cluster is a memory. + // It was found that attenuation caused RAMs to have issues packing. + // FIXME: What to do when the gain is negative? Should we divide by the attenuation? + // Also what happens when we try to merge in atoms from the flat placement + // which are not connected to anything inside the cluster? + const t_appack_options& appack_options = appack_ctx.appack_options; + if (appack_options.use_appack && gain > 0.f && !cluster_gain_stats.is_memory) { + // Get the position of the molecule + t_flat_pl_loc target_loc = get_molecule_pos(molecule_id, prepacker, appack_ctx); + + // Compute the gain attenuatation term. + float dist = get_manhattan_distance(cluster_gain_stats.flat_cluster_position, target_loc); + float gain_mult = 1.0f; + if (dist < appack_options.dist_th) { + gain_mult = 1.0f - (appack_options.quad_fac_sqr * dist * dist); + } else { + gain_mult = 1.0f / std::sqrt(dist - appack_options.sqrt_offset); + } + VTR_ASSERT_SAFE(gain_mult >= 0.0f && gain_mult <= 1.0f); + + // Update the gain. + gain *= gain_mult; + } + return gain; } void GreedyCandidateSelector::load_transitive_fanout_candidates( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer) { // iterate over all the nets that have pins in this cluster for (AtomNetId net_id : cluster_gain_stats.marked_nets) { // only consider small nets to constrain runtime @@ -1011,18 +1205,19 @@ void GreedyCandidateSelector::load_transitive_fanout_candidates( } else { cluster_gain_stats.gain[blk_id] += 0.001; } - t_pack_molecule* molecule = prepacker.get_atom_molecule(blk_id); - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(molecule)); - transitive_fanout_candidates.insert({molecule->atom_block_ids[molecule->root], molecule}); + PackMoleculeId molecule_id = prepacker_.get_atom_molecule(blk_id); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(molecule_id)); + const t_pack_molecule& molecule = prepacker_.get_molecule(molecule_id); + transitive_fanout_candidates.insert({molecule.atom_block_ids[molecule.root], molecule_id}); } } } } } -t_pack_molecule* GreedyCandidateSelector::get_unrelated_candidate_for_cluster( - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer) { +PackMoleculeId GreedyCandidateSelector::get_unrelated_candidate_for_cluster( + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer) { // Necessary data structures are only allocated in unrelated clustering is // on. VTR_ASSERT(allow_unrelated_clustering_); @@ -1039,31 +1234,140 @@ t_pack_molecule* GreedyCandidateSelector::get_unrelated_candidate_for_cluster( for (int ext_inps = inputs_avail; ext_inps >= 0; ext_inps--) { // Get the molecule by the number of external inputs. - t_pack_molecule* molecule = nullptr; - for (t_pack_molecule* mol : unrelated_clustering_data_[ext_inps]) { + PackMoleculeId molecule = PackMoleculeId::INVALID(); + for (PackMoleculeId mol_id : unrelated_clustering_data_[ext_inps]) { /* TODO: Get better candidate atom block in future, eg. return most timing critical or some other smarter metric */ - if (!cluster_legalizer.is_mol_clustered(mol)) { + if (!cluster_legalizer.is_mol_clustered(mol_id)) { /* TODO: I should be using a better filtering check especially when I'm * dealing with multiple clock/multiple global reset signals where the clock/reset * packed in matters, need to do later when I have the circuits to check my work */ - if (cluster_legalizer.is_molecule_compatible(mol, cluster_id)) { - molecule = mol; + if (cluster_legalizer.is_molecule_compatible(mol_id, cluster_id)) { + molecule = mol_id; break; } } } // If a molecule could be found, return it. - if (molecule != nullptr) + if (molecule.is_valid()) return molecule; } // If no molecule could be found, return nullptr. - return nullptr; + return PackMoleculeId::INVALID(); +} + +PackMoleculeId GreedyCandidateSelector::get_unrelated_candidate_for_cluster_appack( + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer) { + + /** + * For APPack, we want to find a close candidate with the highest number + * of available inputs which could be packed into the given cluster. + * We will search for candidates in a BFS manner, where we will search in + * the same 1x1 grid location of the cluster for a compatible candidate, and + * will then search out if none can be found. + * + * Here, a molecule is compatible if: + * - It has not been clustered already + * - The number of inputs it has available is less than or equal to the + * number of inputs available in the cluster. + * - It has not tried to be packed in this cluster before. + * - It is compatible with the cluster. + */ + + VTR_ASSERT_MSG(allow_unrelated_clustering_, + "Cannot get unrelated candidates when unrelated clustering " + "is disabled"); + + VTR_ASSERT_MSG(appack_ctx_.appack_options.use_appack, + "APPack is disabled, cannot get unrelated clusters using " + "flat placement information"); + + // The cluster will likely have more inputs available than a single molecule + // would have available (clusters have more pins). Clamp the inputs available + // to the max number of inputs a molecule could have. + size_t inputs_avail = cluster_legalizer.get_num_cluster_inputs_available(cluster_id); + VTR_ASSERT_SAFE(!appack_unrelated_clustering_data_.empty()); + size_t max_molecule_inputs_avail = appack_unrelated_clustering_data_[0][0].size() - 1; + if (inputs_avail >= max_molecule_inputs_avail) { + inputs_avail = max_molecule_inputs_avail; + } + + // Create a queue of locations to search and a map of visited grid locations. + std::queue search_queue; + vtr::NdMatrix visited({appack_unrelated_clustering_data_.dim_size(0), + appack_unrelated_clustering_data_.dim_size(1)}, + false); + // Push the position of the cluster to the queue. + search_queue.push(cluster_gain_stats.flat_cluster_position); + + while (!search_queue.empty()) { + // Pop a position to search from the queue. + const t_flat_pl_loc& node_loc = search_queue.front(); + VTR_ASSERT_SAFE(node_loc.layer == 0); + + // If this position is too far from the source, skip it. + float dist = get_manhattan_distance(node_loc, cluster_gain_stats.flat_cluster_position); + if (dist > 1) { + search_queue.pop(); + continue; + } + + // If this position has been visited, skip it. + if (visited[node_loc.x][node_loc.y]) { + search_queue.pop(); + continue; + } + visited[node_loc.x][node_loc.y] = true; + + // Explore this position from highest number of inputs available to lowest. + const auto& uc_data = appack_unrelated_clustering_data_[node_loc.x][node_loc.y]; + VTR_ASSERT_SAFE(inputs_avail < uc_data.size()); + for (int ext_inps = inputs_avail; ext_inps >= 0; ext_inps--) { + // Get the molecule by the number of external inputs. + for (PackMoleculeId mol_id : uc_data[ext_inps]) { + // If this molecule has been clustered, skip it. + if (cluster_legalizer.is_mol_clustered(mol_id)) + continue; + // If this molecule has tried to be packed before and failed + // do not try it. This also means that this molecule may be + // related to this cluster in some way. + if (cluster_gain_stats.mol_failures.find(mol_id) != cluster_gain_stats.mol_failures.end()) + continue; + // If this molecule is not compatible with the current cluster + // skip it. + if (!cluster_legalizer.is_molecule_compatible(mol_id, cluster_id)) + continue; + // Return this molecule as the unrelated candidate. + return mol_id; + } + } + + // Push the neighbors of the position to the queue. + // Note: Here, we are using the manhattan distance, so we do not push + // the diagonals. We also want to try the direct neighbors first + // since they should be closer. + if (node_loc.x >= 1.0f) + search_queue.push({node_loc.x - 1, node_loc.y, node_loc.layer}); + if (node_loc.x <= visited.dim_size(0) - 2) + search_queue.push({node_loc.x + 1, node_loc.y, node_loc.layer}); + if (node_loc.y >= 1.0f) + search_queue.push({node_loc.x, node_loc.y - 1, node_loc.layer}); + if (node_loc.y <= visited.dim_size(1) - 2) + search_queue.push({node_loc.x, node_loc.y + 1, node_loc.layer}); + + // Pop the position off the queue. + search_queue.pop(); + } + + // No molecule could be found. Return an invalid ID. + return PackMoleculeId::INVALID(); } void GreedyCandidateSelector::update_candidate_selector_finalize_cluster( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId cluster_id) { + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id) { // store info that will be used later in packing. for (const AtomNetId mnet_id : cluster_gain_stats.marked_nets) { int external_terminals = atom_netlist_.net_pins(mnet_id).size() - cluster_gain_stats.num_pins_of_net_in_pb[mnet_id]; @@ -1078,4 +1382,3 @@ void GreedyCandidateSelector::update_candidate_selector_finalize_cluster( } } } - diff --git a/vpr/src/pack/greedy_candidate_selector.h b/vpr/src/pack/greedy_candidate_selector.h index 881e41a4224..2b3eb23a1f5 100644 --- a/vpr/src/pack/greedy_candidate_selector.h +++ b/vpr/src/pack/greedy_candidate_selector.h @@ -12,18 +12,23 @@ #include #include #include +#include "flat_placement_types.h" #include "attraction_groups.h" #include "cluster_legalizer.h" +#include "greedy_clusterer.h" #include "physical_types.h" +#include "prepack.h" +#include "vtr_ndmatrix.h" #include "vtr_vector.h" +#include "vtr_random.h" // Forward declarations class AtomNetlist; class AttractionInfo; +class FlatPlacementInfo; +class PreClusterTimingManager; class Prepacker; -class SetupTimingInfo; class t_pack_high_fanout_thresholds; -class t_pack_molecule; struct t_model; struct t_molecule_stats; struct t_packer_opts; @@ -36,6 +41,14 @@ struct t_packer_opts; * into the given cluster. */ struct ClusterGainStats { + /// @brief The seed molecule used to create this cluster. + PackMoleculeId seed_molecule_id = PackMoleculeId::INVALID(); + + /// @brief Has this cluster tried to get candidates by connectivity and + /// timing yet. This helps ensure that we only do that once per + /// cluster candidate proposal. + bool has_done_connectivity_and_timing = false; + /// @brief Attraction (inverse of cost) function. std::unordered_map gain; @@ -49,12 +62,12 @@ struct ClusterGainStats { /// consideration. std::unordered_map sharing_gain; - /// @brief Stores the number of times atoms have failed to be packed into - /// the cluster. + /// @brief Stores the number of times molecules have failed to be packed + /// into the cluster. /// - /// key: root block id of the molecule, value: number of times the molecule - /// has failed to be packed into the cluster. - std::unordered_map atom_failures; + /// key: molecule id, value: number of times the molecule has failed to be + /// packed into the cluster. + std::unordered_map mol_failures; /// @brief List of nets with the num_pins_of_net_in_pb and gain entries /// altered (i.e. have some gain-related connection to the current @@ -73,7 +86,7 @@ struct ClusterGainStats { /// @brief Holding transitive fanout candidates key: root block id of the /// molecule, value: pointer to the molecule. // TODO: This should be an unordered map, unless stability is desired. - std::map transitive_fanout_candidates; + std::map transitive_fanout_candidates; /// @brief How many pins of each atom net are contained in the currently open pb? std::unordered_map num_pins_of_net_in_pb; @@ -87,8 +100,31 @@ struct ClusterGainStats { /// /// Sorted in ascending gain order so that the last cluster_ctx.blocks is /// the most desirable (this makes it easy to pop blocks off the list. - std::vector feasible_blocks; + std::vector feasible_blocks; int num_feasible_blocks; + + /// @brief The flat placement location of this cluster. + /// + /// This is some function of the positions of the molecules which have been + /// packed into this cluster. How this position is computed is decided by + /// the appack_options passed into the candidate selector class. + /// + /// This is only set and used when APPack is used. + t_flat_pl_loc flat_cluster_position; + + /// @brief The sum of the positions of all molecules in this cluster. + /// + /// This sum can be useful for quickly computing the centroid of this + /// cluster. This sum is updated whenever a molecule is successfully added + /// to the cluster. + /// + /// This is only set and used when APPack is used. + t_flat_pl_loc mol_pos_sum; + + /// @brief Flag to indicate if this cluster is a memory or not. This is + /// set when the stats are created based on the primitive pb type + /// of the seed. + bool is_memory = false; }; /** @@ -111,7 +147,7 @@ struct ClusterGainStats { * ClusterGainStats cluster_gain_stats = candidate_selector.create_cluster_gain_stats(...); * * // Select a candidate to pack into the cluster using the gain stats. - * t_pack_molecule* candidate_mol = candidate_selector.get_next_candidate_for_cluster(cluster_gain_stats, ...); + * PackMoleculeId candidate_mol = candidate_selector.get_next_candidate_for_cluster(cluster_gain_stats, ...); * * // ... (Try to pack the candidate into the cluster) * @@ -129,7 +165,7 @@ struct ClusterGainStats { * candidate_selector.update_candidate_selector_finalize_cluster(cluster_gain_stats, ...); */ class GreedyCandidateSelector { -private: + private: /// @brief How many unrelated candidates can be proposed and not clustered /// in a row. So if an unrelated candidate is successfully clustered, /// the counter is reset. @@ -150,7 +186,7 @@ class GreedyCandidateSelector { /// atoms in the group, or a randomly selected number of them. static constexpr int attraction_group_num_atoms_threshold_ = 500; -public: + public: ~GreedyCandidateSelector(); /** @@ -189,9 +225,13 @@ class GreedyCandidateSelector { * The set of nets whose output feeds the block that drives * itself. This may cause double-counting in the gain * calculations and needs special handling. - * @param timing_info - * Setup timing info for this Atom Netlist. Used to incorporate - * timing / criticality into the gain calculation. + * @param pre_cluster_timing_manager + * Timing manager that holds the information on timing of + * different connections in the circuit. Used for computing + * the timing gain terms. + * @param appack_ctx + * The APPack context which contains options for the flat + * placement guided packing. * @param log_verbosity * The verbosity of log messages in the candidate selector. */ @@ -205,7 +245,8 @@ class GreedyCandidateSelector { const std::unordered_set& is_clock, const std::unordered_set& is_global, const std::unordered_set& net_output_feeds_driving_block_input, - const SetupTimingInfo& timing_info, + const PreClusterTimingManager& pre_cluster_timing_manager, + const APPackContext& appack_ctx, int log_verbosity); /** @@ -229,10 +270,10 @@ class GreedyCandidateSelector { * other. */ ClusterGainStats create_cluster_gain_stats( - t_pack_molecule* cluster_seed_mol, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + PackMoleculeId cluster_seed_mol_id, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Update the cluster gain stats given that the successful_mol was @@ -254,11 +295,11 @@ class GreedyCandidateSelector { * other. */ void update_cluster_gain_stats_candidate_success( - ClusterGainStats& cluster_gain_stats, - t_pack_molecule* successful_mol, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + PackMoleculeId successful_mol_id, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Update the cluster gain stats given that the failed_mol was not @@ -273,8 +314,8 @@ class GreedyCandidateSelector { * The molecule that failed to pack into the cluster. */ void update_cluster_gain_stats_candidate_failed( - ClusterGainStats& cluster_gain_stats, - t_pack_molecule* failed_mol); + ClusterGainStats& cluster_gain_stats, + PackMoleculeId failed_mol_id); /** * @brief Given the cluster_gain_stats, select the next candidate molecule @@ -289,19 +330,15 @@ class GreedyCandidateSelector { * The legalization cluster id for the cluster. * @param cluster_legalizer * The legalizer used to create the cluster. - * @param prepacker - * The prepacker used to generate pack-pattern molecules of the - * atoms in the netlist. * @param attraction_groups * Groups of primitives that have extra attraction to each * other. */ - t_pack_molecule* get_next_candidate_for_cluster( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer, - const Prepacker& prepacker, - AttractionInfo& attraction_groups); + PackMoleculeId get_next_candidate_for_cluster( + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Finalize the creation of a cluster. @@ -319,10 +356,27 @@ class GreedyCandidateSelector { * The legalization cluster id of the cluster to finalize. */ void update_candidate_selector_finalize_cluster( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId cluster_id); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id); + + private: + // ===================================================================== // + // Initializing Data Structures + // ===================================================================== // + + /** + * @brief Initialize data structures used for unrelated clustering. + * + * This must be called before using the get_unrelated_candidate methods. + * + * @param max_molecule_stats + * The maximum molecule statistics over all molecules in the design. + * This is used to allocate the data-structures used for unrelated + * clustering. + */ + void initialize_unrelated_clustering_data( + const t_molecule_stats& max_molecule_stats); -private: // ===================================================================== // // Cluster Gain Stats Updating // ===================================================================== // @@ -332,8 +386,8 @@ class GreedyCandidateSelector { * updated when a block is marked. */ enum class e_gain_update : bool { - GAIN, // Update the gains of affected blocks. - NO_GAIN // Do not update the gains of affected blocks. + GAIN, // Update the gains of affected blocks. + NO_GAIN // Do not update the gains of affected blocks. }; /** @@ -341,8 +395,8 @@ class GreedyCandidateSelector { * updating the connection gain values. */ enum class e_net_relation_to_clustered_block : bool { - INPUT, // This is an input net. - OUTPUT // This is an output net. + INPUT, // This is an input net. + OUTPUT // This is an output net. }; /** @@ -392,11 +446,10 @@ class GreedyCandidateSelector { * the list of feasible blocks. */ void add_cluster_molecule_candidates_by_connectivity_and_timing( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Score unclustered atoms that are two hops away from current @@ -411,32 +464,29 @@ class GreedyCandidateSelector { * This is used when adding molecule candidates by transistive connectivity. */ void load_transitive_fanout_candidates( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer); /* * @brief Add molecules based on transitive connections (eg. 2 hops away) * with current cluster. */ void add_cluster_molecule_candidates_by_transitive_connectivity( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /* * @brief Add molecules based on weak connectedness (connected by high * fanout nets) with current cluster. */ void add_cluster_molecule_candidates_by_highfanout_connectivity( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /* * @brief If the current cluster being packed has an attraction group @@ -450,19 +500,31 @@ class GreedyCandidateSelector { * candidates will vary each time you call this function. */ void add_cluster_molecule_candidates_by_attraction_group( - ClusterGainStats& cluster_gain_stats, - LegalizationClusterId legalization_cluster_id, - const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer, - AttractionInfo& attraction_groups); + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId legalization_cluster_id, + const ClusterLegalizer& cluster_legalizer, + AttractionInfo& attraction_groups); /** * @brief Finds a molecule to propose which is unrelated but may be good to * cluster. */ - t_pack_molecule* get_unrelated_candidate_for_cluster( - LegalizationClusterId cluster_id, - const ClusterLegalizer& cluster_legalizer); + PackMoleculeId get_unrelated_candidate_for_cluster( + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer); + + /** + * @brief Finds a molecule to propose which is unrelated to the current + * cluster but may be good to pack. + * + * This uses flat placement information to choose a good candidate. + * + * This returns an invalid molecule ID if a candidate cannot be found. + */ + PackMoleculeId get_unrelated_candidate_for_cluster_appack( + ClusterGainStats& cluster_gain_stats, + LegalizationClusterId cluster_id, + const ClusterLegalizer& cluster_legalizer); // ===================================================================== // // Internal Variables @@ -471,6 +533,9 @@ class GreedyCandidateSelector { /// @brief The atom netlist to cluster over. const AtomNetlist& atom_netlist_; + /// @brief The prepacker used to pack atoms into molecule pack patterns. + const Prepacker& prepacker_; + /// @brief The packer options used to configure the clusterer. const t_packer_opts& packer_opts_; @@ -501,8 +566,9 @@ class GreedyCandidateSelector { /// drive them. const std::unordered_set& net_output_feeds_driving_block_input_; - /// @brief Setup timing info used to help select critical candidates to pack. - const SetupTimingInfo& timing_info_; + /// @brief The pre-clustering timing manager which holds the timing information + /// of the primitive netlist. + const PreClusterTimingManager& pre_cluster_timing_manager_; /// @brief Inter-block nets within a finalized cluster. Used for finding /// transitive candidates. @@ -511,10 +577,30 @@ class GreedyCandidateSelector { /// @brief Data pre-computed to help select unrelated molecules. This is a /// list of list of molecules sorted by their gain, where the first /// dimension is the number of external outputs of the molecule. - std::vector> unrelated_clustering_data_; + std::vector> unrelated_clustering_data_; + + /// @brief Data pre-computed to help select unrelated molecules when APPack + /// is being used. This is the same data as unrelated_clustering_data_, + /// but it is spatially distributed over the device. + /// For each grid location on the device (x, y), this provides a list of + /// molecules sorted by their gain, where the first dimension is the number + /// of external outputs of the molecule. + /// When APPack is not used, this will be uninitialized. + /// [0..flat_grid_width][0..flat_grid_height][0..max_num_used_ext_pins] + /// Here, flat_grid width/height is the maximum x and y positions given in + /// the flat placement. + vtr::NdMatrix>, 2> appack_unrelated_clustering_data_; + + /// @brief The APPack state which contains the options used to configure + /// APPack and the flat placement. + const APPackContext& appack_ctx_; /// @brief A count on the number of unrelated clustering attempts which /// have been performed. int num_unrelated_clustering_attempts_ = 0; -}; + /// @brief Random number generator used by the clusterer. Currently this + /// is used only when selecting atoms from attraction groups, but + /// could be used for other purposes in the future. + vtr::RngContainer rng_; +}; diff --git a/vpr/src/pack/greedy_clusterer.cpp b/vpr/src/pack/greedy_clusterer.cpp index dd2c9fb4551..7673005af93 100644 --- a/vpr/src/pack/greedy_clusterer.cpp +++ b/vpr/src/pack/greedy_clusterer.cpp @@ -41,15 +41,14 @@ #include #include #include +#include "appack_context.h" #include "SetupGrid.h" #include "atom_netlist.h" #include "attraction_groups.h" #include "cluster_legalizer.h" #include "cluster_util.h" -#include "constraints_report.h" #include "greedy_candidate_selector.h" #include "greedy_seed_selector.h" -#include "pack_types.h" #include "physical_types.h" #include "prepack.h" #include "vpr_context.h" @@ -79,23 +78,26 @@ GreedyClusterer::GreedyClusterer(const t_packer_opts& packer_opts, const t_arch& arch, const t_pack_high_fanout_thresholds& high_fanout_thresholds, const std::unordered_set& is_clock, - const std::unordered_set& is_global) - : packer_opts_(packer_opts), - analysis_opts_(analysis_opts), - atom_netlist_(atom_netlist), - arch_(arch), - high_fanout_thresholds_(high_fanout_thresholds), - is_clock_(is_clock), - is_global_(is_global), - primitive_candidate_block_types_(identify_primitive_candidate_block_types()), - log_verbosity_(packer_opts.pack_verbosity), - net_output_feeds_driving_block_input_(identify_net_output_feeds_driving_block_input(atom_netlist)) { - + const std::unordered_set& is_global, + const PreClusterTimingManager& pre_cluster_timing_manager, + const APPackContext& appack_ctx) + : packer_opts_(packer_opts) + , analysis_opts_(analysis_opts) + , atom_netlist_(atom_netlist) + , arch_(arch) + , high_fanout_thresholds_(high_fanout_thresholds) + , is_clock_(is_clock) + , is_global_(is_global) + , pre_cluster_timing_manager_(pre_cluster_timing_manager) + , appack_ctx_(appack_ctx) + , primitive_candidate_block_types_(identify_primitive_candidate_block_types()) + , log_verbosity_(packer_opts.pack_verbosity) + , net_output_feeds_driving_block_input_(identify_net_output_feeds_driving_block_input(atom_netlist)) { } std::map GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, - Prepacker& prepacker, + const Prepacker& prepacker, bool allow_unrelated_clustering, bool balance_block_type_utilization, AttractionInfo& attraction_groups, @@ -111,19 +113,7 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, // The clustering stats holds information used for logging the progress // of the clustering to the user. t_cluster_progress_stats clustering_stats; - clustering_stats.num_molecules = prepacker.get_num_molecules(); - - // TODO: Create a ClusteringTimingManager class. - // This code relies on the prepacker, once the prepacker is moved to - // the constructor, this code can also move to the constructor. - std::shared_ptr clustering_delay_calc; - std::shared_ptr timing_info; - // Default criticalities set to zero (e.g. if not timing driven) - vtr::vector atom_criticality(atom_netlist_.blocks().size(), 0.f); - if (packer_opts_.timing_driven) { - calc_init_packing_timing(packer_opts_, analysis_opts_, prepacker, - clustering_delay_calc, timing_info, atom_criticality); - } + clustering_stats.num_molecules = prepacker.molecules().size(); // Calculate the max molecule stats, which is used for gain calculation. const t_molecule_stats max_molecule_stats = prepacker.calc_max_molecule_stats(atom_netlist_); @@ -140,7 +130,8 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, is_clock_, is_global_, net_output_feeds_driving_block_input_, - *timing_info, + pre_cluster_timing_manager_, + appack_ctx_, log_verbosity_); // Create the greedy seed selector. @@ -148,11 +139,11 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, prepacker, packer_opts_.cluster_seed_type, max_molecule_stats, - atom_criticality); + pre_cluster_timing_manager_); // Pick the first seed molecule. - t_pack_molecule* seed_mol = seed_selector.get_next_seed(prepacker, - cluster_legalizer); + PackMoleculeId seed_mol_id = seed_selector.get_next_seed(prepacker, + cluster_legalizer); /**************************************************************** * Clustering @@ -162,9 +153,9 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, // Continue clustering as long as a valid seed is returned from the seed // selector. - while (seed_mol != nullptr) { + while (seed_mol_id.is_valid()) { // Check to ensure that this molecule is unclustered. - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_mol)); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_mol_id)); // The basic algorithm: // 1) Try to put all the molecules in that you can without doing the @@ -175,34 +166,34 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, // Try to grow a cluster from the seed molecule without doing intra-lb // route for each molecule (i.e. just use faster but not fully // conservative legality checks). - LegalizationClusterId new_cluster_id = try_grow_cluster(seed_mol, - candidate_selector, - ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, - cluster_legalizer, - prepacker, - balance_block_type_utilization, - attraction_groups, - num_used_type_instances, - mutable_device_ctx); + LegalizationClusterId new_cluster_id = try_grow_cluster(seed_mol_id, + candidate_selector, + ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, + cluster_legalizer, + prepacker, + balance_block_type_utilization, + attraction_groups, + num_used_type_instances, + mutable_device_ctx); if (!new_cluster_id.is_valid()) { // If the previous strategy failed, try to grow the cluster again, // but this time perform full legalization for each molecule added // to the cluster. - new_cluster_id = try_grow_cluster(seed_mol, - candidate_selector, - ClusterLegalizationStrategy::FULL, - cluster_legalizer, - prepacker, - balance_block_type_utilization, - attraction_groups, - num_used_type_instances, - mutable_device_ctx); + new_cluster_id = try_grow_cluster(seed_mol_id, + candidate_selector, + ClusterLegalizationStrategy::FULL, + cluster_legalizer, + prepacker, + balance_block_type_utilization, + attraction_groups, + num_used_type_instances, + mutable_device_ctx); } // Ensure that the seed was packed successfully. VTR_ASSERT(new_cluster_id.is_valid()); - VTR_ASSERT(cluster_legalizer.is_mol_clustered(seed_mol)); + VTR_ASSERT(cluster_legalizer.is_mol_clustered(seed_mol_id)); // Update the clustering progress stats. size_t num_molecules_in_cluster = cluster_legalizer.get_num_molecules_in_cluster(new_cluster_id); @@ -220,8 +211,8 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, cluster_legalizer); // Pick new seed. - seed_mol = seed_selector.get_next_seed(prepacker, - cluster_legalizer); + seed_mol_id = seed_selector.get_next_seed(prepacker, + cluster_legalizer); } // If this architecture has LE physical block, report its usage. @@ -230,44 +221,43 @@ GreedyClusterer::do_clustering(ClusterLegalizer& cluster_legalizer, return num_used_type_instances; } -LegalizationClusterId GreedyClusterer::try_grow_cluster( - t_pack_molecule* seed_mol, - GreedyCandidateSelector& candidate_selector, - ClusterLegalizationStrategy strategy, - ClusterLegalizer& cluster_legalizer, - Prepacker& prepacker, - bool balance_block_type_utilization, - AttractionInfo& attraction_groups, - std::map& num_used_type_instances, - DeviceContext& mutable_device_ctx) { +LegalizationClusterId GreedyClusterer::try_grow_cluster(PackMoleculeId seed_mol_id, + GreedyCandidateSelector& candidate_selector, + ClusterLegalizationStrategy strategy, + ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker, + bool balance_block_type_utilization, + AttractionInfo& attraction_groups, + std::map& num_used_type_instances, + DeviceContext& mutable_device_ctx) { // Check to ensure that this molecule is unclustered. - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_mol)); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_mol_id)); // Set the legalization strategy of the cluster legalizer. cluster_legalizer.set_legalization_strategy(strategy); // Use the seed to start a new cluster. - LegalizationClusterId legalization_cluster_id = start_new_cluster(seed_mol, + LegalizationClusterId legalization_cluster_id = start_new_cluster(seed_mol_id, cluster_legalizer, + prepacker, balance_block_type_utilization, num_used_type_instances, mutable_device_ctx); // Create the cluster gain stats. This updates the gains in the candidate // selector due to a new molecule being clustered. - ClusterGainStats cluster_gain_stats = candidate_selector.create_cluster_gain_stats(seed_mol, + ClusterGainStats cluster_gain_stats = candidate_selector.create_cluster_gain_stats(seed_mol_id, legalization_cluster_id, cluster_legalizer, attraction_groups); // Select the first candidate molecule to try to add to this cluster. - t_pack_molecule* candidate_mol = candidate_selector.get_next_candidate_for_cluster( - cluster_gain_stats, - legalization_cluster_id, - cluster_legalizer, - prepacker, - attraction_groups); + PackMoleculeId candidate_mol_id = candidate_selector.get_next_candidate_for_cluster( + cluster_gain_stats, + legalization_cluster_id, + cluster_legalizer, + attraction_groups); /* * When attraction groups are created, the purpose is to pack more densely by adding more molecules @@ -286,11 +276,12 @@ LegalizationClusterId GreedyClusterer::try_grow_cluster( // 1) No candidate molecule is proposed. // 2) The same candidate was proposed multiple times. int num_repeated_molecules = 0; - while (candidate_mol != nullptr && num_repeated_molecules < max_num_repeated_molecules) { + while (candidate_mol_id.is_valid() && num_repeated_molecules < max_num_repeated_molecules) { // Try to cluster the candidate molecule into the cluster. - bool success = try_add_candidate_mol_to_cluster(candidate_mol, + bool success = try_add_candidate_mol_to_cluster(candidate_mol_id, legalization_cluster_id, - cluster_legalizer); + cluster_legalizer, + prepacker); // If the candidate molecule was clustered successfully, update // the cluster stats. @@ -298,7 +289,7 @@ LegalizationClusterId GreedyClusterer::try_grow_cluster( // If the last candidate was clustered successfully, update the // gains in the candidate selector. candidate_selector.update_cluster_gain_stats_candidate_success(cluster_gain_stats, - candidate_mol, + candidate_mol_id, legalization_cluster_id, cluster_legalizer, attraction_groups); @@ -306,22 +297,21 @@ LegalizationClusterId GreedyClusterer::try_grow_cluster( // If the last candidate was not clustered successfully, update the // gains in the candidate selector accordingly. candidate_selector.update_cluster_gain_stats_candidate_failed(cluster_gain_stats, - candidate_mol); + candidate_mol_id); } // Get the next candidate molecule. - t_pack_molecule* prev_candidate_mol = candidate_mol; - candidate_mol = candidate_selector.get_next_candidate_for_cluster( - cluster_gain_stats, - legalization_cluster_id, - cluster_legalizer, - prepacker, - attraction_groups); + PackMoleculeId prev_candidate_mol_id = candidate_mol_id; + candidate_mol_id = candidate_selector.get_next_candidate_for_cluster( + cluster_gain_stats, + legalization_cluster_id, + cluster_legalizer, + attraction_groups); // If the next candidate molecule is the same as the previous // candidate molecule, increment the number of repeated // molecules counter. - if (candidate_mol == prev_candidate_mol) + if (candidate_mol_id == prev_candidate_mol_id) num_repeated_molecules++; } @@ -363,14 +353,18 @@ LegalizationClusterId GreedyClusterer::try_grow_cluster( } LegalizationClusterId GreedyClusterer::start_new_cluster( - t_pack_molecule* seed_mol, - ClusterLegalizer& cluster_legalizer, - bool balance_block_type_utilization, - std::map& num_used_type_instances, - DeviceContext& mutable_device_ctx) { + PackMoleculeId seed_mol_id, + ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker, + bool balance_block_type_utilization, + std::map& num_used_type_instances, + DeviceContext& mutable_device_ctx) { + + VTR_ASSERT(seed_mol_id.is_valid()); + const t_pack_molecule& seed_mol = prepacker.get_molecule(seed_mol_id); /* Allocate a dummy initial cluster and load a atom block as a seed and check if it is legal */ - AtomBlockId root_atom = seed_mol->atom_block_ids[seed_mol->root]; + AtomBlockId root_atom = seed_mol.atom_block_ids[seed_mol.root]; const std::string& root_atom_name = atom_netlist_.block_name(root_atom); const t_model* root_model = atom_netlist_.block_model(root_atom); @@ -402,8 +396,8 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( if (log_verbosity_ > 2) { VTR_LOG("\tSeed: '%s' (%s)", root_atom_name.c_str(), root_model->name); - VTR_LOGV(seed_mol->pack_pattern, " molecule_type %s molecule_size %zu", - seed_mol->pack_pattern->name, seed_mol->atom_block_ids.size()); + VTR_LOGV(seed_mol.pack_pattern, " molecule_type %s molecule_size %zu", + seed_mol.pack_pattern->name, seed_mol.atom_block_ids.size()); VTR_LOG("\n"); } @@ -415,7 +409,7 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( //Try packing into each mode e_block_pack_status pack_result = e_block_pack_status::BLK_STATUS_UNDEFINED; for (int j = 0; j < type->pb_graph_head->pb_type->num_modes && !success; j++) { - std::tie(pack_result, new_cluster_id) = cluster_legalizer.start_new_cluster(seed_mol, type, j); + std::tie(pack_result, new_cluster_id) = cluster_legalizer.start_new_cluster(seed_mol_id, type, j); success = (pack_result == e_block_pack_status::BLK_PASSED); } @@ -431,11 +425,11 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( if (!success) { //Explored all candidates - if (seed_mol->type == MOLECULE_FORCED_PACK) { + if (seed_mol.type == e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK) { VPR_FATAL_ERROR(VPR_ERROR_PACK, "Can not find any logic block that can implement molecule.\n" "\tPattern %s %s\n", - seed_mol->pack_pattern->name, + seed_mol.pack_pattern->name, root_atom_name.c_str()); } else { VPR_FATAL_ERROR(VPR_ERROR_PACK, @@ -478,15 +472,16 @@ LegalizationClusterId GreedyClusterer::start_new_cluster( return new_cluster_id; } -bool GreedyClusterer::try_add_candidate_mol_to_cluster(t_pack_molecule* candidate_mol, +bool GreedyClusterer::try_add_candidate_mol_to_cluster(PackMoleculeId candidate_mol_id, LegalizationClusterId legalization_cluster_id, - ClusterLegalizer& cluster_legalizer) { - VTR_ASSERT(candidate_mol != nullptr); - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(candidate_mol)); + ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker) { + VTR_ASSERT(candidate_mol_id.is_valid()); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(candidate_mol_id)); VTR_ASSERT(legalization_cluster_id.is_valid()); - e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(candidate_mol, - legalization_cluster_id); + e_block_pack_status pack_status = cluster_legalizer.add_mol_to_cluster(candidate_mol_id, + legalization_cluster_id); // Print helpful debugging log messages. if (log_verbosity_ > 2) { @@ -511,14 +506,15 @@ bool GreedyClusterer::try_add_candidate_mol_to_cluster(t_pack_molecule* candidat break; } // Get the block name and model name - AtomBlockId blk_id = candidate_mol->atom_block_ids[candidate_mol->root]; + const t_pack_molecule& candidate_mol = prepacker.get_molecule(candidate_mol_id); + AtomBlockId blk_id = candidate_mol.atom_block_ids[candidate_mol.root]; VTR_ASSERT(blk_id.is_valid()); std::string blk_name = atom_netlist_.block_name(blk_id); const t_model* blk_model = atom_netlist_.block_model(blk_id); VTR_LOG("'%s' (%s)", blk_name.c_str(), blk_model->name); - VTR_LOGV(candidate_mol->pack_pattern, " molecule %s molecule_size %zu", - candidate_mol->pack_pattern->name, - candidate_mol->atom_block_ids.size()); + VTR_LOGV(candidate_mol.pack_pattern, " molecule %s molecule_size %zu", + candidate_mol.pack_pattern->name, + candidate_mol.atom_block_ids.size()); VTR_LOG("\n"); fflush(stdout); } @@ -565,4 +561,3 @@ void GreedyClusterer::report_le_physical_block_usage(const ClusterLegalizer& clu print_le_count(num_logic_le, num_reg_le, num_logic_and_reg_le, le_pb_type); } } - diff --git a/vpr/src/pack/greedy_clusterer.h b/vpr/src/pack/greedy_clusterer.h index eb1dff3afdf..4c805ffa594 100644 --- a/vpr/src/pack/greedy_clusterer.h +++ b/vpr/src/pack/greedy_clusterer.h @@ -13,17 +13,17 @@ #include #include "cluster_legalizer.h" #include "physical_types.h" +#include "prepack.h" // Forward declarations +class APPackContext; class AtomNetId; class AtomNetlist; class AttractionInfo; class DeviceContext; class GreedyCandidateSelector; -class Prepacker; -class SetupTimingInfo; +class PreClusterTimingManager; class t_pack_high_fanout_thresholds; -class t_pack_molecule; struct t_analysis_opts; struct t_clustering_data; struct t_packer_opts; @@ -42,7 +42,7 @@ struct t_packer_opts; * internal molecules, and to the outputs of the clusters. */ class GreedyClusterer { -public: + public: /** * @brief Constructor of the Greedy Clusterer class. * @@ -76,6 +76,14 @@ class GreedyClusterer { * The set of global nets in the Atom Netlist. These will be * routed on special dedicated networks, and hence are less * relavent to locality / attraction. + * @param pre_cluster_timing_manager + * Timing manager class which holds the timing information of + * the primitive netlist. Used by the seed selector to select + * critical seeds and the candidate selector to select + * timing critical candidates. + * @param appack_ctx + * The APPack state. This contains the options used to + * configure APPack and the flat placement. */ GreedyClusterer(const t_packer_opts& packer_opts, const t_analysis_opts& analysis_opts, @@ -83,7 +91,9 @@ class GreedyClusterer { const t_arch& arch, const t_pack_high_fanout_thresholds& high_fanout_thresholds, const std::unordered_set& is_clock, - const std::unordered_set& is_global); + const std::unordered_set& is_global, + const PreClusterTimingManager& pre_cluster_timing_manager, + const APPackContext& appack_ctx); /** * @brief Performs clustering on the pack molecules formed by the prepacker. @@ -125,13 +135,13 @@ class GreedyClusterer { */ std::map do_clustering(ClusterLegalizer& cluster_legalizer, - Prepacker& prepacker, + const Prepacker& prepacker, bool allow_unrelated_clustering, bool balance_block_type_utilization, AttractionInfo& attraction_groups, DeviceContext& mutable_device_ctx); -private: + private: /** * @brief Given a seed molecule and a legalization strategy, tries to grow * a cluster greedily, starting with the provided seed and adding @@ -148,11 +158,11 @@ class GreedyClusterer { * legalizer for each molecule added. This cannot fail (assuming the seed * can exist in a cluster), so it will always return a valid cluster ID. */ - LegalizationClusterId try_grow_cluster(t_pack_molecule* seed_mol, + LegalizationClusterId try_grow_cluster(PackMoleculeId seed_mol_id, GreedyCandidateSelector& candidate_selector, ClusterLegalizationStrategy strategy, ClusterLegalizer& cluster_legalizer, - Prepacker& prepacker, + const Prepacker& prepacker, bool balance_block_type_utilization, AttractionInfo& attraction_groups, std::map& num_used_type_instances, @@ -172,8 +182,9 @@ class GreedyClusterer { * device grid if it find thats more clusters of specific logical block * types have been created than the device can support. */ - LegalizationClusterId start_new_cluster(t_pack_molecule* seed_mol, + LegalizationClusterId start_new_cluster(PackMoleculeId seed_mol_id, ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker, bool balance_block_type_utilization, std::map& num_used_type_instances, DeviceContext& mutable_device_ctx); @@ -183,9 +194,10 @@ class GreedyClusterer { * Returns true if the molecule was clustered successfully, false * otherwise. */ - bool try_add_candidate_mol_to_cluster(t_pack_molecule* candidate_mol, + bool try_add_candidate_mol_to_cluster(PackMoleculeId candidate_mol_id, LegalizationClusterId legalization_cluster_id, - ClusterLegalizer& cluster_legalizer); + ClusterLegalizer& cluster_legalizer, + const Prepacker& prepacker); /** * @brief Log the physical block usage of the logic element in the @@ -227,6 +239,13 @@ class GreedyClusterer { /// @brief A set of atom nets which are considered as global nets. const std::unordered_set& is_global_; + /// @brief Timing manager class which holds the primitive-level timing information. + const PreClusterTimingManager& pre_cluster_timing_manager_; + + /// @brief The APPack state. This is used by the candidate selector to try + /// and propose better candidates based on a flat placement. + const APPackContext& appack_ctx_; + /// @brief Pre-computed logical block types for each model in the architecture. const std::map> primitive_candidate_block_types_; @@ -246,4 +265,3 @@ class GreedyClusterer { /// is an input, so this should take care of all multiple connections. const std::unordered_set net_output_feeds_driving_block_input_; }; - diff --git a/vpr/src/pack/greedy_seed_selector.cpp b/vpr/src/pack/greedy_seed_selector.cpp index 24a57930f71..c9d1b9397c5 100644 --- a/vpr/src/pack/greedy_seed_selector.cpp +++ b/vpr/src/pack/greedy_seed_selector.cpp @@ -8,14 +8,21 @@ #include "greedy_seed_selector.h" #include +#include +#include "PreClusterTimingManager.h" +#include "flat_placement_types.h" #include "atom_netlist.h" #include "cluster_legalizer.h" +#include "device_grid.h" #include "echo_files.h" +#include "globals.h" +#include "greedy_clusterer.h" #include "prepack.h" #include "vpr_error.h" #include "vpr_types.h" #include "vtr_assert.h" #include "vtr_math.h" +#include "vtr_ndmatrix.h" #include "vtr_vector.h" /** @@ -40,22 +47,20 @@ static inline float get_seed_gain(AtomBlockId blk_id, // Intuition: molecules that use more inputs can be difficult to legally // pack into partially full clusters. Use them as seeds // instead. - case e_cluster_seed::MAX_INPUTS: - { - const t_pack_molecule* blk_mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol, atom_netlist); + case e_cluster_seed::MAX_INPUTS: { + PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); return molecule_stats.num_used_ext_inputs; } // By blended gain (criticality and inputs used). - case e_cluster_seed::BLEND: - { + case e_cluster_seed::BLEND: { // Score seed gain of each block as a weighted sum of timing // criticality, number of tightly coupled blocks connected to // it, and number of external inputs. float seed_blend_fac = 0.5f; - const t_pack_molecule* blk_mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol, atom_netlist); + PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); VTR_ASSERT(max_molecule_stats.num_used_ext_inputs > 0); float used_ext_input_pin_ratio = vtr::safe_ratio(molecule_stats.num_used_ext_inputs, max_molecule_stats.num_used_ext_inputs); @@ -67,25 +72,22 @@ static inline float get_seed_gain(AtomBlockId blk_id, // By pins per molecule (i.e. available pins on primitives, not pins in use). // Intuition (a weak one): primitive types with more pins might be // harder to pack. - case e_cluster_seed::MAX_PINS: - { - const t_pack_molecule* blk_mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol, atom_netlist); + case e_cluster_seed::MAX_PINS: { + PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); return molecule_stats.num_pins; } // By input pins per molecule (i.e. available pins on primitives, not pins in use). // Intuition (a weak one): primitive types with more input pins might be // harder to pack. - case e_cluster_seed::MAX_INPUT_PINS: - { - const t_pack_molecule* blk_mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol, atom_netlist); + case e_cluster_seed::MAX_INPUT_PINS: { + PackMoleculeId blk_mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(blk_mol_id, atom_netlist); return molecule_stats.num_input_pins; } - case e_cluster_seed::BLEND2: - { - const t_pack_molecule* mol = prepacker.get_atom_molecule(blk_id); - const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol, atom_netlist); + case e_cluster_seed::BLEND2: { + PackMoleculeId mol_id = prepacker.get_atom_molecule(blk_id); + const t_molecule_stats molecule_stats = prepacker.calc_molecule_stats(mol_id, atom_netlist); float pin_ratio = vtr::safe_ratio(molecule_stats.num_pins, max_molecule_stats.num_pins); float input_pin_ratio = vtr::safe_ratio(molecule_stats.num_input_pins, max_molecule_stats.num_input_pins); @@ -166,10 +168,21 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, const Prepacker& prepacker, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, - const vtr::vector& atom_criticality) - : seed_atoms_(atom_netlist.blocks().begin(), atom_netlist.blocks().end()) { + const PreClusterTimingManager& pre_cluster_timing_manager) + : seed_atoms_(atom_netlist.blocks().begin(), atom_netlist.blocks().end()) { // Seed atoms list is initialized with all atoms in the atom netlist. + // Pre-compute the criticality of each atom + // Default criticalities set to zero (e.g. if not timing driven) + vtr::vector atom_criticality(atom_netlist.blocks().size(), 0.0f); + if (pre_cluster_timing_manager.is_valid()) { + // If the timing manager is valid (meaning the packing is timing driven) + // compute the criticality of each atom. + for (AtomBlockId atom_blk_id : atom_netlist.blocks()) { + atom_criticality[atom_blk_id] = pre_cluster_timing_manager.calc_atom_setup_criticality(atom_blk_id, atom_netlist); + } + } + // Maintain a lookup table of the seed gain for each atom. This will be // used to sort the seed atoms. // Initially all gains are zero. @@ -210,8 +223,8 @@ GreedySeedSelector::GreedySeedSelector(const AtomNetlist& atom_netlist, seed_index_ = 0; } -t_pack_molecule* GreedySeedSelector::get_next_seed(const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer) { +PackMoleculeId GreedySeedSelector::get_next_seed(const Prepacker& prepacker, + const ClusterLegalizer& cluster_legalizer) { while (seed_index_ < seed_atoms_.size()) { // Get the current seed atom at the seed index and increment the // seed index. @@ -227,14 +240,13 @@ t_pack_molecule* GreedySeedSelector::get_next_seed(const Prepacker& prepacker, // Get the molecule that contains this atom and return it as the // next seed. - t_pack_molecule* seed_molecule = prepacker.get_atom_molecule(seed_blk_id); - VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_molecule)); - return seed_molecule; + PackMoleculeId seed_molecule_id = prepacker.get_atom_molecule(seed_blk_id); + VTR_ASSERT(!cluster_legalizer.is_mol_clustered(seed_molecule_id)); + return seed_molecule_id; } // If the previous loop does not return a molecule, it implies that all // atoms have been clustered or have already been proposed as a seed. // Return nullptr to signify that there are no further seeds. - return nullptr; + return PackMoleculeId::INVALID(); } - diff --git a/vpr/src/pack/greedy_seed_selector.h b/vpr/src/pack/greedy_seed_selector.h index f6eee80da4b..5f152f65236 100644 --- a/vpr/src/pack/greedy_seed_selector.h +++ b/vpr/src/pack/greedy_seed_selector.h @@ -8,12 +8,13 @@ #pragma once +#include "prepack.h" #include "vpr_types.h" // Forward declarations class AtomNetlist; class ClusterLegalizer; -class Prepacker; +class PreClusterTimingManager; struct t_molecule_stats; /** @@ -27,7 +28,7 @@ struct t_molecule_stats; * or has already been clustered. */ class GreedySeedSelector { -public: + public: /** * @brief Constructor of the Greedy Seed Selector class. Pre-computes the * gains of each molecule internally to make getting seeds later very @@ -44,18 +45,19 @@ class GreedySeedSelector { * @param max_molecule_stats * The maximum stats over all molecules. Used for normalizing * terms in the gain. - * @param atom_criticality - * The timing criticality of each atom. + * @param pre_cluster_timing_manager + * Timing manager class for the primitive netlist. Used to + * compute the criticalities of seeds. */ GreedySeedSelector(const AtomNetlist& atom_netlist, const Prepacker& prepacker, const e_cluster_seed seed_type, const t_molecule_stats& max_molecule_stats, - const vtr::vector& atom_criticality); + const PreClusterTimingManager& pre_cluster_timing_manager); /** * @brief Propose a new seed molecule to start a new cluster with. If no - * unclustered molecules exist, will return nullptr. + * unclustered molecules exist, will return an invalid ID. * * This method will never return a molecule which has already been clustered * (according to the cluster legalizer) and will never propose a molecule @@ -71,14 +73,13 @@ class GreedySeedSelector { * clusters. This is used to check if a molecule has already * been clustered or not. */ - t_pack_molecule* get_next_seed(const Prepacker& prepacker, - const ClusterLegalizer& cluster_legalizer); + PackMoleculeId get_next_seed(const Prepacker& prepacker, + const ClusterLegalizer& cluster_legalizer); // TODO: Maybe create an update_seed_gains method to update the seed atoms // list using current clustering information. -private: - + private: /// @brief The index of the next seed to propose in the seed_atoms vector. /// This is set to 0 in the constructor and incremented as more seeds /// are proposed. @@ -94,4 +95,3 @@ class GreedySeedSelector { // used. std::vector seed_atoms_; }; - diff --git a/vpr/src/pack/noc_aware_cluster_util.cpp b/vpr/src/pack/noc_aware_cluster_util.cpp index d807e5aa187..aba034992f2 100644 --- a/vpr/src/pack/noc_aware_cluster_util.cpp +++ b/vpr/src/pack/noc_aware_cluster_util.cpp @@ -70,7 +70,7 @@ void update_noc_reachability_partitions(const std::vector& noc_atom atom_noc_grp_id[current_atom] = noc_grp_id; - for(auto pin : atom_netlist.block_pins(current_atom)) { + for (auto pin : atom_netlist.block_pins(current_atom)) { AtomNetId net_id = atom_netlist.pin_net(pin); size_t net_fanout = atom_netlist.net_sinks(net_id).size(); @@ -91,9 +91,7 @@ void update_noc_reachability_partitions(const std::vector& noc_atom atom_visited[sink_atom_id] = true; } } - } } - } } diff --git a/vpr/src/pack/noc_aware_cluster_util.h b/vpr/src/pack/noc_aware_cluster_util.h index 6f930a21944..a414d147bcf 100644 --- a/vpr/src/pack/noc_aware_cluster_util.h +++ b/vpr/src/pack/noc_aware_cluster_util.h @@ -32,7 +32,6 @@ class t_pack_high_fanout_thresholds; */ std::vector find_noc_router_atoms(const AtomNetlist& atom_netlist); - /** * @brief Runs BFS starting from NoC routers to find all connected * components that include a NoC router. Each connected component diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index 83949655b2b..60a371aee46 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -12,6 +12,7 @@ #include "cluster_legalizer.h" #include "clustered_netlist.h" #include "physical_types.h" +#include "physical_types_util.h" #include "prepack.h" #include "vpr_context.h" #include "vtr_assert.h" @@ -29,7 +30,6 @@ #include "vpr_utils.h" #include "pack.h" - static void print_clustering_stats_header(); static void print_clustering_stats(std::string_view block_name, int num_block_type, float num_inputs_clocks, float num_outputs); @@ -84,7 +84,6 @@ static void count_stats_from_legalizer(const ClusterLegalizer& cluster_legalizer } num_clb_types[logical_block->index]++; } - } static void count_stats_from_netlist(std::unordered_map& nets_absorbed, @@ -112,7 +111,7 @@ static void count_stats_from_netlist(std::unordered_map& nets_a } else { ClusterNetId clb_net_id = clb_nlist.block_net(blk_id, ipin); if (clb_net_id != ClusterNetId::INVALID()) { - AtomNetId net_id = atom_ctx.lookup.atom_net(clb_net_id); + AtomNetId net_id = atom_ctx.lookup().atom_net(clb_net_id); VTR_ASSERT(net_id); nets_absorbed[net_id] = false; @@ -132,7 +131,7 @@ static void count_stats_from_netlist(std::unordered_map& nets_a * internal connections are printed out. */ static void print_stats(const ClusterLegalizer* cluster_legalizer_ptr, bool from_legalizer) { const DeviceContext& device_ctx = g_vpr_ctx.device(); - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); int* num_clb_types = new int[device_ctx.logical_block_types.size()]; int* num_clb_inputs_used = new int[device_ctx.logical_block_types.size()]; @@ -208,10 +207,10 @@ static void print_clustering_stats(std::string_view block_name, int num_block_ty } static const char* clustering_xml_net_text(AtomNetId net_id) { - /* This routine prints out the atom_ctx.nlist net name (or open). - * net_num is the index of the atom_ctx.nlist net to be printed + /* This routine prints out the atom_ctx.netlist() net name (or open). + * net_num is the index of the atom_ctx.netlist() net to be printed */ - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); if (!net_id) { return "open"; @@ -431,18 +430,18 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty block_node.append_attribute("mode") = mode->name; } else { const auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId atom_blk = atom_ctx.nlist.find_block(pb->name); + AtomBlockId atom_blk = atom_ctx.netlist().find_block(pb->name); VTR_ASSERT(atom_blk); pugi::xml_node attrs_node = block_node.append_child("attributes"); - for (const auto& attr : atom_ctx.nlist.block_attrs(atom_blk)) { + for (const auto& attr : atom_ctx.netlist().block_attrs(atom_blk)) { pugi::xml_node attr_node = attrs_node.append_child("attribute"); attr_node.append_attribute("name") = attr.first.c_str(); attr_node.text().set(attr.second.c_str()); } pugi::xml_node params_node = block_node.append_child("parameters"); - for (const auto& param : atom_ctx.nlist.block_params(atom_blk)) { + for (const auto& param : atom_ctx.netlist().block_params(atom_blk)) { pugi::xml_node param_node = params_node.append_child("parameter"); param_node.append_attribute("name") = param.first.c_str(); param_node.text().set(param.second.c_str()); @@ -480,10 +479,10 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty //This is a primitive with equivalent inputs auto& atom_ctx = g_vpr_ctx.atom(); - AtomBlockId atom_blk = atom_ctx.nlist.find_block(pb->name); + AtomBlockId atom_blk = atom_ctx.netlist().find_block(pb->name); VTR_ASSERT(atom_blk); - AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_type->ports[i].model_port); + AtomPortId atom_port = atom_ctx.netlist().find_atom_port(atom_blk, pb_type->ports[i].model_port); if (atom_port) { //Port exists (some LUTs may have no input and hence no port in the atom netlist) @@ -503,10 +502,10 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty //This physical pin is in use, find the original pin in the atom netlist AtomPinId orig_pin; - for (AtomPinId atom_pin : atom_ctx.nlist.port_pins(atom_port)) { + for (AtomPinId atom_pin : atom_ctx.netlist().port_pins(atom_port)) { if (recorded_pins.count(atom_pin)) continue; //Don't add pins twice - AtomNetId atom_pin_net = atom_ctx.nlist.pin_net(atom_pin); + AtomNetId atom_pin_net = atom_ctx.netlist().pin_net(atom_pin); if (atom_pin_net == atom_net) { recorded_pins.insert(atom_pin); @@ -517,7 +516,7 @@ static void clustering_xml_block(pugi::xml_node& parent_node, t_logical_block_ty VTR_ASSERT(orig_pin); //The physical pin j, maps to a pin in the atom netlist - pin_map_list.push_back(vtr::string_fmt("%d", atom_ctx.nlist.pin_port_bit(orig_pin))); + pin_map_list.push_back(vtr::string_fmt("%d", atom_ctx.netlist().pin_port_bit(orig_pin))); } else { //The physical pin is disconnected pin_map_list.push_back("open"); @@ -643,7 +642,7 @@ static void clustering_xml_blocks_from_netlist(pugi::xml_node& block_node, * the cluster, in essentially a graph based format. */ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_clocks, const std::unordered_set& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering, bool from_legalizer) { const DeviceContext& device_ctx = g_vpr_ctx.device(); - const AtomNetlist& atom_nlist = g_vpr_ctx.atom().nlist; + const AtomNetlist& atom_nlist = g_vpr_ctx.atom().netlist(); IntraLbPbPinLookup pb_graph_pin_lookup_from_index_by_type(device_ctx.logical_block_types); @@ -722,7 +721,7 @@ void output_clustering(ClusterLegalizer* cluster_legalizer_ptr, bool global_cloc * but remove all the requirements on input data structures that * have to be built with other APIs * - * As such, this function is expected to be a standard API + * As such, this function is expected to be a standard API * which can be called anytime and anywhere after packing is finished. ********************************************************************/ void write_packing_results_to_xml(const bool& global_clocks, diff --git a/vpr/src/pack/pack.cpp b/vpr/src/pack/pack.cpp index e9ba3f7f7e3..ec96e7c4d7c 100644 --- a/vpr/src/pack/pack.cpp +++ b/vpr/src/pack/pack.cpp @@ -1,14 +1,21 @@ -#include +#include "pack.h" + +#include +#include "PreClusterTimingManager.h" #include "SetupGrid.h" +#include "appack_context.h" #include "attraction_groups.h" #include "cluster_legalizer.h" #include "cluster_util.h" #include "constraints_report.h" +#include "flat_placement_types.h" #include "globals.h" #include "greedy_clusterer.h" -#include "pack.h" +#include "partition_region.h" #include "prepack.h" +#include "stats.h" +#include "verify_flat_placement.h" #include "vpr_context.h" #include "vpr_error.h" #include "vpr_types.h" @@ -20,13 +27,13 @@ static bool try_size_device_grid(const t_arch& arch, float target_device_utilization, const std::string& device_layout_name); -bool try_pack(t_packer_opts* packer_opts, - const t_analysis_opts* analysis_opts, - const t_arch* arch, - const t_model* user_models, - const t_model* library_models, - float interc_delay, - std::vector* lb_type_rr_graphs) { +bool try_pack(const t_packer_opts& packer_opts, + const t_analysis_opts& analysis_opts, + const t_arch& arch, + std::vector* lb_type_rr_graphs, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const FlatPlacementInfo& flat_placement_info) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); const DeviceContext& device_ctx = g_vpr_ctx.device(); // The clusterer modifies the device context by increasing the size of the @@ -34,15 +41,15 @@ bool try_pack(t_packer_opts* packer_opts, DeviceContext& mutable_device_ctx = g_vpr_ctx.mutable_device(); std::unordered_set is_clock, is_global; - VTR_LOG("Begin packing '%s'.\n", packer_opts->circuit_file_name.c_str()); + VTR_LOG("Begin packing '%s'.\n", packer_opts.circuit_file_name.c_str()); is_clock = alloc_and_load_is_clock(); is_global.insert(is_clock.begin(), is_clock.end()); size_t num_p_inputs = 0; size_t num_p_outputs = 0; - for (auto blk_id : atom_ctx.nlist.blocks()) { - auto type = atom_ctx.nlist.block_type(blk_id); + for (auto blk_id : atom_ctx.netlist().blocks()) { + auto type = atom_ctx.netlist().block_type(blk_id); if (type == AtomBlockType::INPAD) { ++num_p_inputs; } else if (type == AtomBlockType::OUTPAD) { @@ -53,74 +60,85 @@ bool try_pack(t_packer_opts* packer_opts, VTR_LOG("\n"); VTR_LOG("After removing unused inputs...\n"); VTR_LOG("\ttotal blocks: %zu, total nets: %zu, total inputs: %zu, total outputs: %zu\n", - atom_ctx.nlist.blocks().size(), atom_ctx.nlist.nets().size(), num_p_inputs, num_p_outputs); - - // Run the prepacker, packing the atoms into molecules. - // The Prepacker object performs prepacking and stores the pack molecules. - // As long as the molecules are used, this object must persist. - VTR_LOG("Begin prepacking.\n"); - Prepacker prepacker; - prepacker.init(atom_ctx.nlist, device_ctx.logical_block_types); + atom_ctx.netlist().blocks().size(), atom_ctx.netlist().nets().size(), num_p_inputs, num_p_outputs); /* We keep attraction groups off in the first iteration, and * only turn on in later iterations if some floorplan regions turn out to be overfull. */ AttractionInfo attraction_groups(false); - VTR_LOG("%d attraction groups were created during prepacking.\n", attraction_groups.num_attraction_groups()); - VTR_LOG("Finish prepacking.\n"); - if (packer_opts->auto_compute_inter_cluster_net_delay) { - packer_opts->inter_cluster_net_delay = interc_delay; - VTR_LOG("Using inter-cluster delay: %g\n", packer_opts->inter_cluster_net_delay); + // We keep track of the overfilled partition regions from all pack iterations in + // this vector. This is so that if the first iteration fails due to overfilled + // partition regions, and it fails again, we can carry over the previous failed + // partition regions to the current iteration. + std::vector overfull_partition_regions; + + // Verify that the Flat Placement is valid for packing. + if (flat_placement_info.valid) { + unsigned num_errors = verify_flat_placement_for_packing(flat_placement_info, + atom_ctx.netlist(), + prepacker); + if (num_errors == 0) { + VTR_LOG("Completed flat placement consistency check successfully.\n"); + } else { + // TODO: In the future, we can just erase the flat placement and + // continue. It depends on what we want to happen if the + // flat placement is not valid. + VPR_ERROR(VPR_ERROR_PACK, + "%u errors found while performing flat placement " + "consistency check. Aborting program.\n", + num_errors); + } } // During clustering, a block is related to un-clustered primitives with nets. // This relation has three types: low fanout, high fanout, and transitive // high_fanout_thresholds stores the threshold for nets to a block type to // be considered high fanout. - t_pack_high_fanout_thresholds high_fanout_thresholds(packer_opts->high_fanout_threshold); + t_pack_high_fanout_thresholds high_fanout_thresholds(packer_opts.high_fanout_threshold); bool allow_unrelated_clustering = false; - if (packer_opts->allow_unrelated_clustering == e_unrelated_clustering::ON) { + if (packer_opts.allow_unrelated_clustering == e_unrelated_clustering::ON) { allow_unrelated_clustering = true; - } else if (packer_opts->allow_unrelated_clustering == e_unrelated_clustering::OFF) { + } else if (packer_opts.allow_unrelated_clustering == e_unrelated_clustering::OFF) { allow_unrelated_clustering = false; } bool balance_block_type_util = false; - if (packer_opts->balance_block_type_utilization == e_balance_block_type_util::ON) { + if (packer_opts.balance_block_type_utilization == e_balance_block_type_util::ON) { balance_block_type_util = true; - } else if (packer_opts->balance_block_type_utilization == e_balance_block_type_util::OFF) { + } else if (packer_opts.balance_block_type_utilization == e_balance_block_type_util::OFF) { balance_block_type_util = false; } int pack_iteration = 1; - // Initialize the cluster legalizer. - ClusterLegalizer cluster_legalizer(atom_ctx.nlist, + ClusterLegalizer cluster_legalizer(atom_ctx.netlist(), prepacker, - device_ctx.logical_block_types, lb_type_rr_graphs, - user_models, - library_models, - packer_opts->target_external_pin_util, + packer_opts.target_external_pin_util, high_fanout_thresholds, ClusterLegalizationStrategy::SKIP_INTRA_LB_ROUTE, - packer_opts->enable_pin_feasibility_filter, - packer_opts->feasible_block_array_size, - packer_opts->pack_verbosity); - + packer_opts.enable_pin_feasibility_filter, + packer_opts.pack_verbosity); VTR_LOG("Packing with pin utilization targets: %s\n", cluster_legalizer.get_target_external_pin_util().to_string().c_str()); VTR_LOG("Packing with high fanout thresholds: %s\n", high_fanout_thresholds.to_string().c_str()); + // Construct the APPack Context. + APPackContext appack_ctx(flat_placement_info, device_ctx.grid); + // Initialize the greedy clusterer. - GreedyClusterer clusterer(*packer_opts, - *analysis_opts, - atom_ctx.nlist, - *arch, + GreedyClusterer clusterer(packer_opts, + analysis_opts, + atom_ctx.netlist(), + arch, high_fanout_thresholds, is_clock, - is_global); + is_global, + pre_cluster_timing_manager, + appack_ctx); + + g_vpr_ctx.mutable_atom().mutable_lookup().set_atom_pb_bimap_lock(true); while (true) { //Cluster the netlist @@ -135,13 +153,16 @@ bool try_pack(t_packer_opts* packer_opts, mutable_device_ctx); //Try to size/find a device - bool fits_on_device = try_size_device_grid(*arch, num_used_type_instances, packer_opts->target_device_utilization, packer_opts->device_layout); + bool fits_on_device = try_size_device_grid(arch, num_used_type_instances, packer_opts.target_device_utilization, packer_opts.device_layout); /* We use this bool to determine the cause for the clustering not being dense enough. If the clustering * is not dense enough and there are floorplan constraints, it is presumed that the constraints are the cause * of the floorplan not fitting, so attraction groups are turned on for later iterations. */ - bool floorplan_regions_overfull = floorplan_constraints_regions_overfull(cluster_legalizer); + bool floorplan_regions_overfull = floorplan_constraints_regions_overfull(overfull_partition_regions, + cluster_legalizer, + device_ctx.logical_block_types); + bool floorplan_not_fitting = (floorplan_regions_overfull || g_vpr_ctx.floorplanning().constraints.get_num_partitions() > 0); if (fits_on_device && !floorplan_regions_overfull) { @@ -150,11 +171,11 @@ bool try_pack(t_packer_opts* packer_opts, //1st pack attempt was unsuccessful (i.e. not dense enough) and we have control of unrelated clustering // //Turn it on to increase packing density - if (packer_opts->allow_unrelated_clustering == e_unrelated_clustering::AUTO) { + if (packer_opts.allow_unrelated_clustering == e_unrelated_clustering::AUTO) { VTR_ASSERT(allow_unrelated_clustering == false); allow_unrelated_clustering = true; } - if (packer_opts->balance_block_type_utilization == e_balance_block_type_util::AUTO) { + if (packer_opts.balance_block_type_utilization == e_balance_block_type_util::AUTO) { VTR_ASSERT(balance_block_type_util == false); balance_block_type_util = true; } @@ -173,13 +194,13 @@ bool try_pack(t_packer_opts* packer_opts, */ } else if (pack_iteration == 1 && floorplan_not_fitting) { VTR_LOG("Floorplan regions are overfull: trying to pack again using cluster attraction groups. \n"); - attraction_groups.create_att_groups_for_overfull_regions(); + attraction_groups.create_att_groups_for_overfull_regions(overfull_partition_regions); attraction_groups.set_att_group_pulls(1); } else if (pack_iteration >= 2 && pack_iteration < 5 && floorplan_not_fitting) { if (pack_iteration == 2) { VTR_LOG("Floorplan regions are overfull: trying to pack again with more attraction groups exploration. \n"); - attraction_groups.create_att_groups_for_overfull_regions(); + attraction_groups.create_att_groups_for_overfull_regions(overfull_partition_regions); VTR_LOG("Pack iteration is %d\n", pack_iteration); } else if (pack_iteration == 3) { attraction_groups.create_att_groups_for_all_regions(); @@ -229,20 +250,11 @@ bool try_pack(t_packer_opts* packer_opts, VPR_FATAL_ERROR(VPR_ERROR_OTHER, "Failed to find device which satisfies resource requirements required: %s (available %s)", resource_reqs.c_str(), resource_avail.c_str()); } - //Reset clustering for re-packing - for (auto blk : g_vpr_ctx.atom().nlist.blocks()) { - g_vpr_ctx.mutable_atom().lookup.set_atom_clb(blk, ClusterBlockId::INVALID()); - g_vpr_ctx.mutable_atom().lookup.set_atom_pb(blk, nullptr); - } - for (auto net : g_vpr_ctx.atom().nlist.nets()) { - g_vpr_ctx.mutable_atom().lookup.remove_atom_net(net); - } + //Reset floorplanning constraints for re-packing g_vpr_ctx.mutable_floorplanning().cluster_constraints.clear(); - //attraction_groups.reset_attraction_groups(); // Reset the cluster legalizer for re-clustering. cluster_legalizer.reset(); - ++pack_iteration; } @@ -260,9 +272,10 @@ bool try_pack(t_packer_opts* packer_opts, * } */ /******************** End **************************/ - + g_vpr_ctx.mutable_atom().mutable_lookup().set_atom_pb_bimap_lock(false); + g_vpr_ctx.mutable_atom().mutable_lookup().set_atom_to_pb_bimap(cluster_legalizer.atom_pb_lookup()); //check clustering and output it - check_and_output_clustering(cluster_legalizer, *packer_opts, is_clock, arch); + check_and_output_clustering(cluster_legalizer, packer_opts, is_clock, &arch); VTR_LOG("\n"); VTR_LOG("Netlist conversion complete.\n"); @@ -271,24 +284,6 @@ bool try_pack(t_packer_opts* packer_opts, return true; } -float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch) { - /* Fetches delay, resistance and output capacitance of the architecture switch at switch_index. - * Returns the total delay through the switch. Used to calculate inter-cluster net delay. */ - - /* The intrinsic delay may depend on fanin to the switch. If the delay map of a - * switch from the architecture file has multiple (#inputs, delay) entries, we - * interpolate/extrapolate to get the delay at 'switch_fanin'. */ - auto& device_ctx = g_vpr_ctx.device(); - - Tdel_switch = device_ctx.arch_switch_inf[switch_index].Tdel(switch_fanin); - R_switch = device_ctx.arch_switch_inf[switch_index].R; - Cout_switch = device_ctx.arch_switch_inf[switch_index].Cout; - - /* The delay through a loaded switch is its intrinsic (unloaded) - * delay plus the product of its resistance and output capacitance. */ - return Tdel_switch + R_switch * Cout_switch; -} - std::unordered_set alloc_and_load_is_clock() { /* Looks through all the atom blocks to find and mark all the clocks, by setting * the corresponding entry by adding the clock to is_clock. @@ -299,9 +294,9 @@ std::unordered_set alloc_and_load_is_clock() { /* Want to identify all the clock nets. */ auto& atom_ctx = g_vpr_ctx.atom(); - for (auto blk_id : atom_ctx.nlist.blocks()) { - for (auto pin_id : atom_ctx.nlist.block_clock_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); + for (auto blk_id : atom_ctx.netlist().blocks()) { + for (auto pin_id : atom_ctx.netlist().block_clock_pins(blk_id)) { + auto net_id = atom_ctx.netlist().pin_net(pin_id); if (!is_clock.count(net_id)) { is_clock.insert(net_id); } @@ -358,4 +353,3 @@ static bool try_size_device_grid(const t_arch& arch, return fits_on_device; } - diff --git a/vpr/src/pack/pack.h b/vpr/src/pack/pack.h index 842feb0aacd..64189ea4ee9 100644 --- a/vpr/src/pack/pack.h +++ b/vpr/src/pack/pack.h @@ -5,21 +5,43 @@ #include class AtomNetId; +class FlatPlacementInfo; +class PreClusterTimingManager; +class Prepacker; struct t_analysis_opts; struct t_arch; struct t_lb_type_rr_node; -struct t_model; struct t_packer_opts; -bool try_pack(t_packer_opts* packer_opts, - const t_analysis_opts* analysis_opts, - const t_arch* arch, - const t_model* user_models, - const t_model* library_models, - float interc_delay, - std::vector* lb_type_rr_graphs); - -float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch); +/** + * @brief Try to pack the atom netlist into legal clusters on the given + * architecture. Will return true if successful, false otherwise. + * + * @param packer_opts + * Options passed by the user to configure the packing algorithm. + * @param analysis_opts + * Options passed by the user to configure how analysis is + * performed in the packer. + * @param arch + * The architecture to create clusters for. + * @param lb_type_rr_graphs + * @param prepacker + * The prepacker used to form atoms into molecules prior to packing. + * @param pre_cluster_timing_manager + * Manager object to store the pre-computed timing delay calculations. + * Used to inform the packer of timing critical paths. + * @param flat_placement_info + * Flat (primitive-level) placement information that may be + * provided by the user as a hint for packing. Will be invalid if + * there is no flat placement information provided. + */ +bool try_pack(const t_packer_opts& packer_opts, + const t_analysis_opts& analysis_opts, + const t_arch& arch, + std::vector* lb_type_rr_graphs, + const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, + const FlatPlacementInfo& flat_placement_info); std::unordered_set alloc_and_load_is_clock(); diff --git a/vpr/src/pack/pack_types.h b/vpr/src/pack/pack_types.h index 44fa9107966..8ebaf22b26b 100644 --- a/vpr/src/pack/pack_types.h +++ b/vpr/src/pack/pack_types.h @@ -69,7 +69,7 @@ struct t_lb_type_rr_node { t_pb_graph_pin* pb_graph_pin; /* pb_graph_pin associated with this lb_rr_node if exists, NULL otherwise */ float intrinsic_cost; /* cost of this node */ - t_lb_type_rr_node() { + t_lb_type_rr_node() noexcept { capacity = 0; num_modes = 0; num_fanout = nullptr; @@ -130,7 +130,7 @@ struct t_intra_lb_net { std::vector fixed_terminals; /* Marks a terminal as having a fixed target (i.e. a pin not a sink) */ t_lb_trace* rt_tree; /* Route tree head */ - t_intra_lb_net() { + t_intra_lb_net() noexcept { atom_net_id = AtomNetId::INVALID(); rt_tree = nullptr; } diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 0c6745b85e2..02784e4321a 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -394,7 +394,6 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node, load_power_structures); } - // update the total number of primitives of that type if (pb_graph_node->is_primitive()) { int total_count = 1; @@ -1498,7 +1497,7 @@ static bool realloc_and_load_pb_graph_pin_ptrs_at_var(const int line_num, if (prev_num_pins > 0) { std::vector temp(*pb_graph_pins, *pb_graph_pins + prev_num_pins); - delete[] * pb_graph_pins; + delete[] *pb_graph_pins; *pb_graph_pins = new t_pb_graph_pin*[*num_pins]; for (i = 0; i < prev_num_pins; i++) (*pb_graph_pins)[i] = temp[i]; @@ -1946,18 +1945,18 @@ const t_pb_graph_edge* get_edge_between_pins(const t_pb_graph_pin* driver_pin, c /* Date:June 8th, 2024 * Author: Kate Thurmer * Purpose: This subroutine computes the index of a pb graph node at its - level of the pb hierarchy; it is computed by the parent and - passed to each child of each child pb type. When the child is - a primitive, the computed indes is its flat site index. - For example, if there are 10 ALMs, each with 2 FFs and 2 LUTs, - then the ALM at index N, when calling this function for - its FF child at index M, would compute the child's index as: - N*(FFs per ALM) + M - e.g. for FF[1] in ALM[5], this returns - 5*(2 FFS per ALM) + 1 = 11 + * level of the pb hierarchy; it is computed by the parent and + * passed to each child of each child pb type. When the child is + * a primitive, the computed indes is its flat site index. + * For example, if there are 10 ALMs, each with 2 FFs and 2 LUTs, + * then the ALM at index N, when calling this function for + * its FF child at index M, would compute the child's index as: + * N*(FFs per ALM) + M + * e.g. for FF[1] in ALM[5], this returns + * 5*(2 FFS per ALM) + 1 = 11 */ static int compute_flat_index_for_child_node(int num_children_of_type, int parent_flat_index, int child_index) { - return parent_flat_index*num_children_of_type + child_index; + return parent_flat_index * num_children_of_type + child_index; } diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.cpp b/vpr/src/pack/post_routing_pb_pin_fixup.cpp index 78084d56df3..d217f07a83d 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.cpp +++ b/vpr/src/pack/post_routing_pb_pin_fixup.cpp @@ -1,15 +1,14 @@ /******************************************************************** - * This file includes functions to fix up the pb pin mapping results + * This file includes functions to fix up the pb pin mapping results * after routing optimization *******************************************************************/ /* Headers from vtrutil library */ +#include "physical_types_util.h" #include "vtr_time.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vpr_error.h" #include "vpr_utils.h" -#include "rr_graph2.h" #include "annotate_routing.h" @@ -19,7 +18,7 @@ #include "globals.h" /******************************************************************** - * Give a given pin index, find the side where this pin is located + * Give a given pin index, find the side where this pin is located * on the physical tile * Note: * - Need to check if the pin_width_offset and pin_height_offset @@ -41,7 +40,7 @@ static std::vector find_physical_tile_pin_side(t_physical_tile_type_ptr /******************************************************************** * Fix up the pb pin mapping results for a given clustered block - * 1. For each input/output pin of a clustered pb, + * 1. For each input/output pin of a clustered pb, * - find a corresponding node in RRGraph object * - find the net id for the node in routing context * - find the net id for the node in clustering context @@ -66,15 +65,15 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li /* Narrow down side search for grids * The wanted side depends on the location of the grid. - * In particular for perimeter grid, + * In particular for perimeter grid, * ------------------------------------------------------- * Grid location | IPIN side * ------------------------------------------------------- - * TOP | BOTTOM + * TOP | BOTTOM * ------------------------------------------------------- - * RIGHT | LEFT + * RIGHT | LEFT * ------------------------------------------------------- - * BOTTOM | TOP + * BOTTOM | TOP * ------------------------------------------------------- * LEFT | RIGHT * ------------------------------------------------------- @@ -173,7 +172,7 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li * In general, there is only one valid rr_node among all the sides. * However, we have an exception in the Stratix-IV arch modeling, * where a pb_pin may exist in two different sides but - * router will only map to 1 rr_node + * router will only map to 1 rr_node * Therefore, it is better to compare the routing nets * for all the sides and pick * - The unique valid net id (others should be all invalid) @@ -247,7 +246,7 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li } /******************************************************************** - * Find an unused pb_route from the other pins in this port + * Find an unused pb_route from the other pins in this port * The pb_route should be remapped to an invalid net, becoming unused * at post routing stage. * @@ -272,7 +271,7 @@ static int find_target_pb_route_from_equivalent_pins(const AtomContext& atom_ctx } /* Limitation: bypass output pins now - * TODO: This is due to the 'instance' equivalence port + * TODO: This is due to the 'instance' equivalence port * where outputs may be swapped. This definitely requires re-run of packing * It can not be solved by swapping routing traces now */ @@ -317,7 +316,7 @@ static int find_target_pb_route_from_equivalent_pins(const AtomContext& atom_ctx VTR_LOGV(verbose, "Found %lu candidates to remap net '%s' at clustered block '%s' pin '%s'\n", pb_route_indices.size(), - atom_ctx.nlist.net_name(target_net).c_str(), + atom_ctx.netlist().net_name(target_net).c_str(), clustering_ctx.clb_nlist.block_pb(blk_id)->name, source_pb_graph_pin->to_string().c_str()); @@ -367,7 +366,7 @@ static const t_pb_graph_pin* find_unused_pb_graph_pin_in_the_same_port(const t_p VTR_LOG("\tUnused\n"); } else { VTR_LOG("\tmapped to net '%s'\n", - g_vpr_ctx.atom().nlist.net_name(pb_routes.at(cand_pb_route_id).atom_net_id).c_str()); + g_vpr_ctx.atom().netlist().net_name(pb_routes.at(cand_pb_route_id).atom_net_id).c_str()); } } @@ -410,7 +409,7 @@ static t_pb_graph_pin* find_used_sink_pb_pin(t_pb_graph_pin* driver_pb_pin, /******************************************************************** * Try to find the atom pin that is mapped to the sink pb_graph_pin - * which can be traced back through the pb routing tree + * which can be traced back through the pb routing tree * * Note: * - This function assumes only 1 sink node to be found @@ -419,13 +418,13 @@ static t_pb_graph_pin* find_used_sink_pb_pin(t_pb_graph_pin* driver_pb_pin, * * Top-level pb_type * +---------------------------- - * | +------------------------ + * | +------------------------ * | | Primitive pb_type * | | +------------------ * | | | - * driver +---+---->| sink pb_pin <------> atom_pin + * driver +---+---->| sink pb_pin <------> atom_pin * pb_route | - * + * *******************************************************************/ static AtomPinId find_mapped_atom_pin(const AtomContext& atom_ctx, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup, @@ -451,9 +450,9 @@ static AtomPinId find_mapped_atom_pin(const AtomContext& atom_ctx, const t_pb_graph_pin* sink_pb_pin = intra_lb_pb_pin_lookup.pb_gpin(logical_type->index, sink_pb_route_id); const t_pb* leaf_pb = pb->find_pb(sink_pb_pin->parent_node); - const AtomPortId& atom_port = atom_ctx.nlist.find_atom_port(atom_ctx.lookup.pb_atom(leaf_pb), sink_pb_pin->port->model_port); + const AtomPortId& atom_port = atom_ctx.netlist().find_atom_port(atom_ctx.lookup().atom_pb_bimap().pb_atom(leaf_pb), sink_pb_pin->port->model_port); BitIndex atom_pin_bit_index = leaf_pb->atom_pin_bit_index(sink_pb_pin); - AtomPinId mapped_atom_pin = atom_ctx.nlist.port_pin(atom_port, atom_pin_bit_index); + AtomPinId mapped_atom_pin = atom_ctx.netlist().port_pin(atom_port, atom_pin_bit_index); return mapped_atom_pin; } @@ -462,20 +461,20 @@ static AtomPinId find_mapped_atom_pin(const AtomContext& atom_ctx, * Cache the mapping from atom pin to pb_graph pin for remapped nets * in current routing traces * - * Note: + * Note: * - The pb_route_id is the routing trace id for top-level pins ONLY! * - This is only applicable to the following case: * * Top-level pb_type * +---------------------------- - * | +------------------------ + * | +------------------------ * | | Primitive pb_type * | | +------------------ * | | | * driver +---+---->| sink * | * - * + * * Anything violates the assumption will be NOT be cached!!! *******************************************************************/ static std::map> cache_atom_pin_to_pb_pin_mapping(const AtomContext& atom_ctx, @@ -522,7 +521,7 @@ static std::map> cache_atom_pin /* Sometimes the routing traces is not what we target, skip caching */ if (orig_mapped_atom_pin) { - atom_pin_to_pb_pin_mapping[pb_route_id] = std::make_pair(orig_mapped_atom_pin, atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)); + atom_pin_to_pb_pin_mapping[pb_route_id] = std::make_pair(orig_mapped_atom_pin, atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)); } } @@ -530,7 +529,7 @@ static std::map> cache_atom_pin } /******************************************************************** - * Spot the original pb_graph_pin that is mapped + * Spot the original pb_graph_pin that is mapped * to a given net from the other equivalent pins in this port *******************************************************************/ static const t_pb_graph_pin* find_mapped_equivalent_pb_pin_by_net(t_pb* pb, @@ -577,7 +576,7 @@ static void rec_remove_downstream_pb_routes(t_pb_routes& curr_pb_routes, /******************************************************************** * Update routing traces for regular nets of a logical block - * This function should NOT + * This function should NOT * - create a routing traces but use the new routing traces * from the inputs * - modify any routing traces for global nets, @@ -603,7 +602,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom } /* Limitation: bypass output pins now - * TODO: This is due to the 'instance' equivalence port + * TODO: This is due to the 'instance' equivalence port * where outputs may be swapped. This definitely requires re-run of packing * It can not be solved by swapping routing traces now */ @@ -626,7 +625,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom VTR_ASSERT_SAFE(remapped_result != clustering_ctx.post_routing_clb_pin_nets[blk_id].end()); /* Cache the remapped net id */ - AtomNetId remapped_net = atom_ctx.lookup.atom_net(remapped_result->second); + AtomNetId remapped_net = atom_ctx.lookup().atom_net(remapped_result->second); /* Skip those pins become unmapped after remapping */ if (!remapped_net) { @@ -648,15 +647,15 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom VTR_LOGV(verbose, "Remapping routing trace for net '%s'\n", - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Spot the routing trace - * Two conditions could happen: + * Two conditions could happen: * - There is already a routing trace for this pin: * we just rename the net id * - There is no routed path for this pin: * we have to find a routing trace which is used by another pin - * in the same port (every pin in this port should be logic equivalent) + * in the same port (every pin in this port should be logic equivalent) * Rename the net id and pb_graph_node pins */ int pb_route_id = find_target_pb_route_from_equivalent_pins(atom_ctx, @@ -688,7 +687,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom /* Check if the sink pb_pins are accessible from the driver pb_pin * - If not accessible, remove the associated sink pin_pins - * - We will add the only accessible pin if and only if + * - We will add the only accessible pin if and only if * the driver pb_pin has only 1 fan-out according to the pb_graph * * Note: @@ -698,14 +697,14 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom * * Top-level pb_type * +---------------------------- - * | +------------------------ + * | +------------------------ * | | Primitive pb_type * | | +------------------ * | | | * driver +---+---->| sink * | * - * + * * Anything violates the assumption will be errored out! */ new_pb_route.sink_pb_pin_ids.clear(); @@ -741,7 +740,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom for (const int& sink_pb_route : new_pb_route.sink_pb_pin_ids) { if (0 == new_pb_routes.count(sink_pb_route)) { /* A new sink pb_pin requires a new pb_route to be added - * This could lead to a chain effect to add new pb_routes + * This could lead to a chain effect to add new pb_routes * We keep adding the pb_pin until we reach a primitive pb_type * All the sink pb_pin of the pb_route to be added * must meet the following requirements @@ -779,14 +778,14 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom "Add a new trace '%d' linked to pin '%s' for net '%s'.\n", new_sink_pb_route_id, new_sink_pb_pin_to_add->to_string().c_str(), - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Update the pins to add for next round */ new_driver_pb_pin = new_sink_pb_pin_to_add->pin_count_in_cluster; new_sink_pb_pin_to_add = next_sink_pb_pin_to_add; } /* The chain effect will lead to a remapping to atom net pins - * Fix the atom net lookup + * Fix the atom net lookup */ VTR_ASSERT(1 == pb->pb_route.at(pb_route_id).sink_pb_pin_ids.size()); const AtomPinId& orig_mapped_atom_pin = previous_atom_pin_to_pb_pin_mapping.at(pb_route_id).first; @@ -795,17 +794,17 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom VTR_LOGV(verbose, "Redirect atom pin '%lu' mapping from '%s' to '%s' for net '%s'.\n", size_t(orig_mapped_atom_pin), - atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)->to_string().c_str(), + atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)->to_string().c_str(), new_sink_pb_pin_to_add->to_string().c_str(), - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Update the pin binding in atom netlist fast look-up */ - atom_ctx.lookup.set_atom_pin_pb_graph_pin(orig_mapped_atom_pin, new_sink_pb_pin_to_add); - VTR_ASSERT(new_sink_pb_pin_to_add == atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)); + atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(orig_mapped_atom_pin, new_sink_pb_pin_to_add); + VTR_ASSERT(new_sink_pb_pin_to_add == atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)); /* Update the pin rotation map */ t_pb* atom_pb = pb->find_mutable_pb(new_sink_pb_pin_to_add->parent_node); - atom_pb->set_atom_pin_bit_index(new_sink_pb_pin_to_add, atom_ctx.nlist.pin_port_bit(orig_mapped_atom_pin)); + atom_pb->set_atom_pin_bit_index(new_sink_pb_pin_to_add, atom_ctx.netlist().pin_port_bit(orig_mapped_atom_pin)); } else { new_pb_routes[sink_pb_route].driver_pb_pin_id = pb_graph_pin->pin_count_in_cluster; @@ -829,7 +828,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom } /* Since this routing trace was mapped to another net, - * we have to spot the original pb_graph_pin that is mapped + * we have to spot the original pb_graph_pin that is mapped * to this net (from the other equivalent pins in this port) * Then we can find out the atom pin that is linked to the remapped net */ @@ -841,17 +840,17 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom VTR_LOGV(verbose, "Redirect atom pin '%lu' mapping from '%s' to '%s' for net '%s'.\n", size_t(orig_mapped_atom_pin), - atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)->to_string().c_str(), + atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)->to_string().c_str(), next_pb_pin->to_string().c_str(), - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Update the pin binding in atom netlist fast look-up */ - atom_ctx.lookup.set_atom_pin_pb_graph_pin(orig_mapped_atom_pin, next_pb_pin); - VTR_ASSERT(next_pb_pin == atom_ctx.lookup.atom_pin_pb_graph_pin(orig_mapped_atom_pin)); + atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(orig_mapped_atom_pin, next_pb_pin); + VTR_ASSERT(next_pb_pin == atom_ctx.lookup().atom_pin_pb_graph_pin(orig_mapped_atom_pin)); /* Update the pin rotation map */ t_pb* atom_pb = pb->find_mutable_pb(next_pb_pin->parent_node); - atom_pb->set_atom_pin_bit_index(next_pb_pin, atom_ctx.nlist.pin_port_bit(orig_mapped_atom_pin)); + atom_pb->set_atom_pin_bit_index(next_pb_pin, atom_ctx.netlist().pin_port_bit(orig_mapped_atom_pin)); } } } @@ -861,7 +860,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom "Remap clustered block '%s' routing trace[%d] to net '%s'\n", clustering_ctx.clb_nlist.block_pb(blk_id)->name, pb_graph_pin->pin_count_in_cluster, - atom_ctx.nlist.net_name(remapped_net).c_str()); + atom_ctx.netlist().net_name(remapped_net).c_str()); /* Update fixup counter */ num_fixup++; @@ -870,7 +869,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom /******************************************************************** * Update routing traces for global nets of a logical block - * This function should NOT + * This function should NOT * - create a routing traces but use the new routing traces * from the inputs * - modify any routing traces for non-global nets, @@ -891,7 +890,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const const t_pb_graph_pin* pb_graph_pin = get_pb_graph_node_pin_from_block_pin(blk_id, pb_type_pin); /* Limitation: bypass output pins now - * TODO: This is due to the 'instance' equivalence port + * TODO: This is due to the 'instance' equivalence port * where outputs may be swapped. This definitely requires re-run of packing * It can not be solved by swapping routing traces now */ @@ -913,7 +912,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const continue; } - AtomNetId global_atom_net_id = atom_ctx.lookup.atom_net(global_net_id); + AtomNetId global_atom_net_id = atom_ctx.lookup().atom_net(global_net_id); auto remapped_result = clustering_ctx.post_routing_clb_pin_nets.at(blk_id).find(pb_graph_pin->pin_count_in_cluster); @@ -928,7 +927,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const VTR_LOGV(verbose, "Remapping clustered block '%s' global net '%s' to unused pin as %s\r", clustering_ctx.clb_nlist.block_pb(blk_id)->name, - atom_ctx.nlist.net_name(global_atom_net_id).c_str(), + atom_ctx.netlist().net_name(global_atom_net_id).c_str(), pb_graph_pin->to_string().c_str()); const t_pb_graph_pin* unused_pb_graph_pin = find_unused_pb_graph_pin_in_the_same_port(pb_graph_pin, new_pb_routes, global_atom_net_id); @@ -959,7 +958,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const VTR_LOGV(verbose, "Remap clustered block '%s' global net '%s' to pin '%s'\n", clustering_ctx.clb_nlist.block_pb(blk_id)->name, - atom_ctx.nlist.net_name(global_atom_net_id).c_str(), + atom_ctx.netlist().net_name(global_atom_net_id).c_str(), unused_pb_graph_pin->to_string().c_str()); /* Update fixup counter */ @@ -972,7 +971,7 @@ static void update_cluster_global_routing_traces_with_post_routing_results(const * This function will directly update the nets of routing traces * stored in the clustered block by considering the post-routing results * - * Note: + * Note: * - This function should be called AFTER the function * update_cluster_pin_with_post_routing_results() *******************************************************************/ @@ -1033,8 +1032,8 @@ void sync_netlists_to_routing(const Netlist<>& net_list, /* Create net-to-rr_node mapping */ vtr::vector rr_node_nets = annotate_rr_node_nets(clustering_ctx, - device_ctx, - verbose); + device_ctx, + verbose); IntraLbPbPinLookup intra_lb_pb_pin_lookup(device_ctx.logical_block_types); diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 9cda9de0360..05912f70b12 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -27,6 +27,7 @@ #include "vpr_utils.h" #include "vtr_assert.h" #include "vtr_range.h" +#include "vtr_time.h" #include "vtr_util.h" #include "vtr_vector.h" @@ -39,13 +40,6 @@ static void free_list_of_pack_patterns(std::vector& list_of_pac static void free_pack_pattern(t_pack_patterns* pack_pattern); -static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_pack_patterns, - vtr::vector& expected_lowest_cost_pb_gnode, - const int num_packing_patterns, - std::multimap& atom_molecules, - const AtomNetlist& atom_nlist, - const std::vector& logical_block_types); - static void discover_pattern_names_in_pb_graph_node(t_pb_graph_node* pb_graph_node, std::unordered_map& pattern_names); @@ -53,20 +47,18 @@ static void forward_infer_pattern(t_pb_graph_pin* pb_graph_pin); static void backward_infer_pattern(t_pb_graph_pin* pb_graph_pin); -static std::vector alloc_and_init_pattern_list_from_hash(std::unordered_map pattern_names); +static std::vector alloc_and_init_pattern_list_from_hash(const std::unordered_map& pattern_names); static t_pb_graph_edge* find_expansion_edge_of_pattern(const int pattern_index, const t_pb_graph_node* pb_graph_node); static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansion_edge, - t_pack_patterns* list_of_packing_patterns, - const int curr_pattern_index, + t_pack_patterns& packing_pattern, int* L_num_blocks, const bool make_root_of_chain); static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansion_edge, - t_pack_patterns* list_of_packing_patterns, - const int curr_pattern_index, + t_pack_patterns& packing_pattern, t_pb_graph_pin* destination_pin, t_pack_pattern_block* destination_block, int* L_num_blocks); @@ -75,21 +67,15 @@ static int compare_pack_pattern(const t_pack_patterns* pattern_a, const t_pack_p static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_pattern_block** pattern_block_list); -static t_pack_molecule* try_create_molecule(t_pack_patterns* list_of_pack_patterns, - const int pack_pattern_index, - AtomBlockId blk_id, - std::multimap& atom_molecules, - const AtomNetlist& atom_nlist); - -static bool try_expand_molecule(t_pack_molecule* molecule, +static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, - const std::multimap& atom_molecules, + const std::multimap& atom_molecules, const AtomNetlist& atom_nlist); static void print_pack_molecules(const char* fname, - const t_pack_patterns* list_of_pack_patterns, + const std::vector& list_of_pack_patterns, const int num_pack_patterns, - const t_pack_molecule* list_of_molecules, + const vtr::vector_map& pack_molecules, const AtomNetlist& atom_nlist); static t_pb_graph_node* get_expected_lowest_cost_primitive_for_atom_block(const AtomBlockId blk_id, @@ -99,7 +85,7 @@ static t_pb_graph_node* get_expected_lowest_cost_primitive_for_atom_block_in_pb_ static AtomBlockId find_new_root_atom_for_chain(const AtomBlockId blk_id, const t_pack_patterns* list_of_pack_patterns, - const std::multimap& atom_molecules, + const std::multimap& atom_molecules, const AtomNetlist& atom_nlist); static std::vector find_end_of_path(t_pb_graph_pin* input_pin, int pattern_index); @@ -114,8 +100,10 @@ static void update_chain_root_pins(t_pack_patterns* chain_pattern, static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector& connected_primitive_pins); static void init_molecule_chain_info(const AtomBlockId blk_id, - t_pack_molecule* molecule, - const std::multimap& atom_molecules, + t_pack_molecule& molecule, + const vtr::vector_map& pack_molecules, + const std::multimap& atom_molecules, + vtr::vector& chain_info, const AtomNetlist& atom_nlist); static AtomBlockId get_sink_block(const AtomBlockId block_id, @@ -146,7 +134,6 @@ static void print_chain_starting_points(t_pack_patterns* chain_pattern); */ static std::vector alloc_and_load_pack_patterns(const std::vector& logical_block_types) { int L_num_blocks; - std::vector list_of_packing_patterns; t_pb_graph_edge* expansion_edge; /* alloc and initialize array of packing patterns based on architecture complex blocks */ @@ -155,7 +142,7 @@ static std::vector alloc_and_load_pack_patterns(const std::vect discover_pattern_names_in_pb_graph_node(type.pb_graph_head, pattern_names); } - list_of_packing_patterns = alloc_and_init_pattern_list_from_hash(pattern_names); + std::vector packing_patterns = alloc_and_init_pattern_list_from_hash(pattern_names); /* load packing patterns by traversing the edges to find edges belonging to pattern */ for (size_t i = 0; i < pattern_names.size(); i++) { @@ -167,30 +154,30 @@ static std::vector alloc_and_load_pack_patterns(const std::vect } L_num_blocks = 0; - list_of_packing_patterns[i].base_cost = 0; + packing_patterns[i].base_cost = 0; // use the found expansion edge to build the pack pattern backward_expand_pack_pattern_from_edge(expansion_edge, - list_of_packing_patterns.data(), i, nullptr, nullptr, &L_num_blocks); - list_of_packing_patterns[i].num_blocks = L_num_blocks; + packing_patterns[i], nullptr, nullptr, &L_num_blocks); + packing_patterns[i].num_blocks = L_num_blocks; /* Default settings: A section of a netlist must match all blocks in a pack * pattern before it can be made a molecule except for carry-chains. * For carry-chains, since carry-chains are typically quite flexible in terms * of size, it is optional whether or not an atom in a netlist matches any * particular block inside the chain */ - list_of_packing_patterns[i].is_block_optional = new bool[L_num_blocks]; + packing_patterns[i].is_block_optional = new bool[L_num_blocks]; for (int k = 0; k < L_num_blocks; k++) { - list_of_packing_patterns[i].is_block_optional[k] = false; - if (list_of_packing_patterns[i].is_chain && list_of_packing_patterns[i].root_block->block_id != k) { - list_of_packing_patterns[i].is_block_optional[k] = true; + packing_patterns[i].is_block_optional[k] = false; + if (packing_patterns[i].is_chain && packing_patterns[i].root_block->block_id != k) { + packing_patterns[i].is_block_optional[k] = true; } } // if this is a chain pattern (extends between complex blocks), check if there // are multiple equivalent chains with different starting and ending points - if (list_of_packing_patterns[i].is_chain) { - find_all_equivalent_chains(&list_of_packing_patterns[i], type.pb_graph_head); - print_chain_starting_points(&list_of_packing_patterns[i]); + if (packing_patterns[i].is_chain) { + find_all_equivalent_chains(&packing_patterns[i], type.pb_graph_head); + print_chain_starting_points(&packing_patterns[i]); } // if pack pattern i is found to belong to current block type, go to next pack pattern @@ -200,12 +187,12 @@ static std::vector alloc_and_load_pack_patterns(const std::vect //Sanity check, every pattern should have a root block for (size_t i = 0; i < pattern_names.size(); ++i) { - if (list_of_packing_patterns[i].root_block == nullptr) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find root block for pack pattern %s", list_of_packing_patterns[i].name); + if (packing_patterns[i].root_block == nullptr) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find root block for pack pattern %s", packing_patterns[i].name); } } - return list_of_packing_patterns; + return packing_patterns; } /** @@ -356,7 +343,7 @@ static void backward_infer_pattern(t_pb_graph_pin* pb_graph_pin) { * Allocates memory for models and loads the name of the packing pattern * so that it can be identified and loaded with more complete information later */ -static std::vector alloc_and_init_pattern_list_from_hash(std::unordered_map pattern_names) { +static std::vector alloc_and_init_pattern_list_from_hash(const std::unordered_map& pattern_names) { std::vector nlist(pattern_names.size()); for (const auto& curr_pattern : pattern_names) { @@ -478,8 +465,7 @@ static t_pb_graph_edge* find_expansion_edge_of_pattern(const int pattern_index, * future multi-fanout support easier) so this function will not update connections */ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansion_edge, - t_pack_patterns* list_of_packing_patterns, - const int curr_pattern_index, + t_pack_patterns& packing_pattern, int* L_num_blocks, bool make_root_of_chain) { int i, j, k; @@ -487,6 +473,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi bool found; /* Error checking, ensure only one fan-out for each pattern net */ t_pack_pattern_block* destination_block = nullptr; t_pb_graph_node* destination_pb_graph_node = nullptr; + int curr_pattern_index = packing_pattern.index; found = expansion_edge->infer_pattern; // if the pack pattern shouldn't be inferred check if the expansion @@ -521,7 +508,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi // 2) assign an id to this pattern block, 3) increment the number of found blocks belonging to this // pattern and 4) expand all its edges to find the other primitives that belong to this pattern destination_block = new t_pack_pattern_block(); - list_of_packing_patterns[curr_pattern_index].base_cost += compute_primitive_base_cost(destination_pb_graph_node); + packing_pattern.base_cost += compute_primitive_base_cost(destination_pb_graph_node); destination_block->block_id = *L_num_blocks; (*L_num_blocks)++; destination_pb_graph_node->temp_scratch_pad = (void*)destination_block; @@ -533,8 +520,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi for (ipin = 0; ipin < destination_pb_graph_node->num_input_pins[iport]; ipin++) { for (iedge = 0; iedge < destination_pb_graph_node->input_pins[iport][ipin].num_input_edges; iedge++) { backward_expand_pack_pattern_from_edge(destination_pb_graph_node->input_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, &destination_pb_graph_node->input_pins[iport][ipin], destination_block, L_num_blocks); } @@ -546,8 +532,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi for (ipin = 0; ipin < destination_pb_graph_node->num_output_pins[iport]; ipin++) { for (iedge = 0; iedge < destination_pb_graph_node->output_pins[iport][ipin].num_output_edges; iedge++) { forward_expand_pack_pattern_from_edge(destination_pb_graph_node->output_pins[iport][ipin].output_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, L_num_blocks, false); + packing_pattern, L_num_blocks, false); } } } @@ -557,8 +542,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi for (ipin = 0; ipin < destination_pb_graph_node->num_clock_pins[iport]; ipin++) { for (iedge = 0; iedge < destination_pb_graph_node->clock_pins[iport][ipin].num_input_edges; iedge++) { backward_expand_pack_pattern_from_edge(destination_pb_graph_node->clock_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, &destination_pb_graph_node->clock_pins[iport][ipin], destination_block, L_num_blocks); } @@ -570,8 +554,8 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi if (((t_pack_pattern_block*)destination_pb_graph_node->temp_scratch_pad)->pattern_index == curr_pattern_index) { // if this pb_graph_node is known to be the root of the chain, update the root block and root pin if (make_root_of_chain == true) { - list_of_packing_patterns[curr_pattern_index].chain_root_pins = {{expansion_edge->output_pins[i]}}; - list_of_packing_patterns[curr_pattern_index].root_block = destination_block; + packing_pattern.chain_root_pins = {{expansion_edge->output_pins[i]}}; + packing_pattern.root_block = destination_block; } } @@ -581,8 +565,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi for (j = 0; j < expansion_edge->output_pins[i]->num_output_edges; j++) { if (expansion_edge->output_pins[i]->output_edges[j]->infer_pattern == true) { forward_expand_pack_pattern_from_edge(expansion_edge->output_pins[i]->output_edges[j], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, L_num_blocks, make_root_of_chain); } else { @@ -597,12 +580,11 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi expansion_edge->output_pins[i]->parent_node->placement_index, expansion_edge->output_pins[i]->port->name, expansion_edge->output_pins[i]->pin_number, - list_of_packing_patterns[curr_pattern_index].name); + packing_pattern.name); } found = true; forward_expand_pack_pattern_from_edge(expansion_edge->output_pins[i]->output_edges[j], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, L_num_blocks, make_root_of_chain); } @@ -620,8 +602,7 @@ static void forward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansi * destination blocks */ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expansion_edge, - t_pack_patterns* list_of_packing_patterns, - const int curr_pattern_index, + t_pack_patterns& packing_pattern, t_pb_graph_pin* destination_pin, t_pack_pattern_block* destination_block, int* L_num_blocks) { @@ -631,6 +612,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans t_pack_pattern_block* source_block = nullptr; t_pb_graph_node* source_pb_graph_node = nullptr; t_pack_pattern_connections* pack_pattern_connection = nullptr; + int curr_pattern_index = packing_pattern.index; found = expansion_edge->infer_pattern; // if the pack pattern shouldn't be inferred check if the expansion @@ -664,13 +646,13 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans source_block = new t_pack_pattern_block(); source_block->block_id = *L_num_blocks; (*L_num_blocks)++; - list_of_packing_patterns[curr_pattern_index].base_cost += compute_primitive_base_cost(source_pb_graph_node); + packing_pattern.base_cost += compute_primitive_base_cost(source_pb_graph_node); source_pb_graph_node->temp_scratch_pad = (void*)source_block; source_block->pattern_index = curr_pattern_index; source_block->pb_type = source_pb_graph_node->pb_type; - if (list_of_packing_patterns[curr_pattern_index].root_block == nullptr) { - list_of_packing_patterns[curr_pattern_index].root_block = source_block; + if (packing_pattern.root_block == nullptr) { + packing_pattern.root_block = source_block; } // explore the inputs of this primitive @@ -678,8 +660,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans for (ipin = 0; ipin < source_pb_graph_node->num_input_pins[iport]; ipin++) { for (iedge = 0; iedge < source_pb_graph_node->input_pins[iport][ipin].num_input_edges; iedge++) { backward_expand_pack_pattern_from_edge(source_pb_graph_node->input_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, &source_pb_graph_node->input_pins[iport][ipin], source_block, L_num_blocks); @@ -692,8 +673,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans for (ipin = 0; ipin < source_pb_graph_node->num_output_pins[iport]; ipin++) { for (iedge = 0; iedge < source_pb_graph_node->output_pins[iport][ipin].num_output_edges; iedge++) { forward_expand_pack_pattern_from_edge(source_pb_graph_node->output_pins[iport][ipin].output_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, L_num_blocks, false); } @@ -705,8 +685,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans for (ipin = 0; ipin < source_pb_graph_node->num_clock_pins[iport]; ipin++) { for (iedge = 0; iedge < source_pb_graph_node->clock_pins[iport][ipin].num_input_edges; iedge++) { backward_expand_pack_pattern_from_edge(source_pb_graph_node->clock_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, &source_pb_graph_node->clock_pins[iport][ipin], source_block, L_num_blocks); @@ -749,11 +728,10 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans if (expansion_edge->input_pins[i]->parent_node->pb_type->parent_mode == nullptr) { // This pack pattern extends to CLB (root pb block) input pin, // thus it extends across multiple logic blocks, treat as a chain - list_of_packing_patterns[curr_pattern_index].is_chain = true; + packing_pattern.is_chain = true; // since this input pin has not driving nets, expand in the forward direction instead forward_expand_pack_pattern_from_edge(expansion_edge, - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, L_num_blocks, true); } @@ -764,8 +742,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans // if pattern should be inferred for this edge continue the expansion backwards if (expansion_edge->input_pins[i]->input_edges[j]->infer_pattern == true) { backward_expand_pack_pattern_from_edge(expansion_edge->input_pins[i]->input_edges[j], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, destination_pin, destination_block, L_num_blocks); @@ -778,8 +755,7 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans /* Check assumption that each forced net has only one fan-out */ found = true; backward_expand_pack_pattern_from_edge(expansion_edge->input_pins[i]->input_edges[j], - list_of_packing_patterns, - curr_pattern_index, + packing_pattern, destination_pin, destination_block, L_num_blocks); @@ -799,29 +775,18 @@ static void backward_expand_pack_pattern_from_edge(const t_pb_graph_edge* expans * 3. Chained molecules are molecules that follow a carry-chain style pattern, * ie. a single linear chain that can be split across multiple complex blocks */ -static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_pack_patterns, - vtr::vector& expected_lowest_cost_pb_gnode, - const int num_packing_patterns, - std::multimap& atom_molecules, - const AtomNetlist& atom_nlist, - const std::vector& logical_block_types) { - int i, j, best_pattern; - t_pack_molecule* list_of_molecules_head; - t_pack_molecule* cur_molecule; - bool* is_used; - - is_used = new bool[num_packing_patterns]; - for (i = 0; i < num_packing_patterns; i++) - is_used[i] = false; - - cur_molecule = list_of_molecules_head = nullptr; +void Prepacker::alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, + const AtomNetlist& atom_nlist, + const std::vector& logical_block_types) { + std::vector is_used(list_of_pack_patterns.size(), false); /* Find forced pack patterns * Simplifying assumptions: Each atom can map to at most one molecule, * use first-fit mapping based on priority of pattern * TODO: Need to investigate better mapping strategies than first-fit */ - for (i = 0; i < num_packing_patterns; i++) { + size_t num_packing_patterns = list_of_pack_patterns.size(); + for (size_t i = 0; i < num_packing_patterns; i++) { /* Skip pack patterns for modes that are disabled for packing, * Ensure no resources in unpackable modes will be mapped during pre-packing stage */ @@ -830,8 +795,8 @@ static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_p continue; } - best_pattern = 0; - for (j = 1; j < num_packing_patterns; j++) { + size_t best_pattern = 0; + for (size_t j = 1; j < num_packing_patterns; j++) { if (is_used[best_pattern]) { best_pattern = j; } else if (is_used[j] == false && compare_pack_pattern(&list_of_pack_patterns[j], &list_of_pack_patterns[best_pattern]) == 1) { @@ -845,34 +810,38 @@ static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_p for (auto blk_iter = blocks.begin(); blk_iter != blocks.end(); ++blk_iter) { auto blk_id = *blk_iter; - cur_molecule = try_create_molecule(list_of_pack_patterns, best_pattern, blk_id, atom_molecules, atom_nlist); - if (cur_molecule != nullptr) { - cur_molecule->next = list_of_molecules_head; - /* In the event of multiple molecules with the same atom block pattern, - * bias to use the molecule with less costly physical resources first */ - /* TODO: Need to normalize magical number 100 */ - cur_molecule->base_gain = cur_molecule->num_blocks - (cur_molecule->pack_pattern->base_cost / 100); - list_of_molecules_head = cur_molecule; - - //Note: atom_molecules is an (ordered) multimap so the last molecule - // inserted for a given blk_id will be the last valid element - // in the equal_range - auto rng = atom_molecules.equal_range(blk_id); //The range of molecules matching this block - bool range_empty = (rng.first == rng.second); - bool cur_was_last_inserted = false; - if (!range_empty) { - auto last_valid_iter = --rng.second; //Iterator to last element (only valid if range is not empty) - cur_was_last_inserted = (last_valid_iter->second == cur_molecule); - } - if (range_empty || !cur_was_last_inserted) { - /* molecule did not cover current atom (possibly because molecule created is - * part of a long chain that extends past multiple logic blocks), try again */ - --blk_iter; - } + PackMoleculeId cur_molecule_id = try_create_molecule(best_pattern, + blk_id, + atom_molecules_multimap, + atom_nlist); + + // If the molecule could not be created, move to the next block. + if (!cur_molecule_id.is_valid()) + continue; + + /* In the event of multiple molecules with the same atom block pattern, + * bias to use the molecule with less costly physical resources first */ + /* TODO: Need to normalize magical number 100 */ + t_pack_molecule& cur_molecule = pack_molecules_[cur_molecule_id]; + cur_molecule.base_gain = cur_molecule.atom_block_ids.size() - (cur_molecule.pack_pattern->base_cost / 100); + + //Note: atom_molecules is an (ordered) multimap so the last molecule + // inserted for a given blk_id will be the last valid element + // in the equal_range + auto rng = atom_molecules_multimap.equal_range(blk_id); //The range of molecules matching this block + bool range_empty = (rng.first == rng.second); + bool cur_was_last_inserted = false; + if (!range_empty) { + auto last_valid_iter = --rng.second; //Iterator to last element (only valid if range is not empty) + cur_was_last_inserted = (last_valid_iter->second == cur_molecule_id); + } + if (range_empty || !cur_was_last_inserted) { + /* molecule did not cover current atom (possibly because molecule created is + * part of a long chain that extends past multiple logic blocks), try again */ + --blk_iter; } } } - delete[] is_used; /* List all atom blocks as a molecule for blocks that do not belong to any molecules. * This allows the packer to be consistent as it now packs molecules only instead of atoms and molecules @@ -883,14 +852,6 @@ static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_p for (auto blk_id : atom_nlist.blocks()) { t_pb_graph_node* best = get_expected_lowest_cost_primitive_for_atom_block(blk_id, logical_block_types); if (!best) { - /* Free the molecules in the linked list to avoid memory leakage */ - cur_molecule = list_of_molecules_head; - while (cur_molecule) { - t_pack_molecule* molecule_to_free = cur_molecule; - cur_molecule = cur_molecule->next; - delete molecule_to_free; - } - VPR_FATAL_ERROR(VPR_ERROR_PACK, "Failed to find any location to pack primitive of type '%s' in architecture", atom_nlist.block_model(blk_id)->name); } @@ -899,33 +860,32 @@ static t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_p expected_lowest_cost_pb_gnode[blk_id] = best; - auto rng = atom_molecules.equal_range(blk_id); + auto rng = atom_molecules_multimap.equal_range(blk_id); bool rng_empty = (rng.first == rng.second); if (rng_empty) { - cur_molecule = new t_pack_molecule; - cur_molecule->type = MOLECULE_SINGLE_ATOM; - cur_molecule->num_blocks = 1; - cur_molecule->root = 0; - cur_molecule->pack_pattern = nullptr; + PackMoleculeId new_molecule_id = PackMoleculeId(pack_molecules_.size()); + t_pack_molecule new_molecule; + new_molecule.type = e_pack_pattern_molecule_type::MOLECULE_SINGLE_ATOM; + new_molecule.root = 0; + new_molecule.pack_pattern = nullptr; - cur_molecule->atom_block_ids = {blk_id}; + new_molecule.atom_block_ids = {blk_id}; - cur_molecule->next = list_of_molecules_head; - cur_molecule->base_gain = 1; - list_of_molecules_head = cur_molecule; + new_molecule.base_gain = 1; + new_molecule.chain_id = MoleculeChainId::INVALID(); - atom_molecules.insert({blk_id, cur_molecule}); + atom_molecules_multimap.insert({blk_id, new_molecule_id}); + pack_molecules_.push_back(std::move(new_molecule)); + pack_molecule_ids_.push_back(new_molecule_id); } } if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS)) { print_pack_molecules(getEchoFileName(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS), list_of_pack_patterns, num_packing_patterns, - list_of_molecules_head, + pack_molecules_, atom_nlist); } - - return list_of_molecules_head; } static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_pattern_block** pattern_block_list) { @@ -959,59 +919,59 @@ static void free_pack_pattern_block(t_pack_pattern_block* pattern_block, t_pack_ * * Side Effect: If successful, link atom to molecule */ -static t_pack_molecule* try_create_molecule(t_pack_patterns* list_of_pack_patterns, - const int pack_pattern_index, - AtomBlockId blk_id, - std::multimap& atom_molecules, - const AtomNetlist& atom_nlist) { - t_pack_molecule* molecule; - +PackMoleculeId Prepacker::try_create_molecule(const int pack_pattern_index, + AtomBlockId blk_id, + std::multimap& atom_molecules_multimap, + const AtomNetlist& atom_nlist) { auto pack_pattern = &list_of_pack_patterns[pack_pattern_index]; // Check pack pattern validity if (pack_pattern == nullptr || pack_pattern->num_blocks == 0 || pack_pattern->root_block == nullptr) { - return nullptr; + return PackMoleculeId::INVALID(); } // If a chain pattern extends beyond a single logic block, we must find // the furthest blk_id up the chain that is not mapped to a molecule yet. if (pack_pattern->is_chain) { - blk_id = find_new_root_atom_for_chain(blk_id, pack_pattern, atom_molecules, atom_nlist); - if (!blk_id) return nullptr; + blk_id = find_new_root_atom_for_chain(blk_id, pack_pattern, atom_molecules_multimap, atom_nlist); + if (!blk_id) return PackMoleculeId::INVALID(); } - molecule = new t_pack_molecule; - molecule->type = MOLECULE_FORCED_PACK; - molecule->pack_pattern = pack_pattern; - molecule->atom_block_ids = std::vector(pack_pattern->num_blocks); //Initializes invalid - molecule->num_blocks = pack_pattern->num_blocks; - molecule->root = pack_pattern->root_block->block_id; + PackMoleculeId new_molecule_id = PackMoleculeId(pack_molecules_.size()); + t_pack_molecule molecule; + molecule.base_gain = 0.f; + molecule.type = e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK; + molecule.pack_pattern = pack_pattern; + molecule.atom_block_ids = std::vector(pack_pattern->num_blocks); //Initializes invalid + molecule.root = pack_pattern->root_block->block_id; + molecule.chain_id = MoleculeChainId::INVALID(); - if (try_expand_molecule(molecule, blk_id, atom_molecules, atom_nlist)) { - // Success! commit molecule + if (!try_expand_molecule(molecule, blk_id, atom_molecules_multimap, atom_nlist)) { + // Failed to create molecule + return PackMoleculeId::INVALID(); + } - // update chain info for chain molecules - if (molecule->pack_pattern->is_chain) { - init_molecule_chain_info(blk_id, molecule, atom_molecules, atom_nlist); - } + // Success! commit molecule - // update the atom_molcules with the atoms that are mapped to this molecule - for (int i = 0; i < molecule->pack_pattern->num_blocks; i++) { - auto blk_id2 = molecule->atom_block_ids[i]; - if (!blk_id2) { - VTR_ASSERT(molecule->pack_pattern->is_block_optional[i]); - continue; - } + // update chain info for chain molecules + if (molecule.pack_pattern->is_chain) { + init_molecule_chain_info(blk_id, molecule, pack_molecules_, atom_molecules_multimap, chain_info_, atom_nlist); + } - atom_molecules.insert({blk_id2, molecule}); + // update the atom_molcules with the atoms that are mapped to this molecule + for (int i = 0; i < molecule.pack_pattern->num_blocks; i++) { + auto blk_id2 = molecule.atom_block_ids[i]; + if (!blk_id2) { + VTR_ASSERT(molecule.pack_pattern->is_block_optional[i]); + continue; } - } else { - // Failed to create molecule - delete molecule; - return nullptr; + + atom_molecules_multimap.insert({blk_id2, new_molecule_id}); } - return molecule; + pack_molecules_.push_back(std::move(molecule)); + pack_molecule_ids_.push_back(new_molecule_id); + return new_molecule_id; } /** @@ -1027,15 +987,15 @@ static t_pack_molecule* try_create_molecule(t_pack_patterns* list_of_pack_patter * atom_molecules : map of atom block ids that are assigned a molecule and a pointer to this molecule * blk_id : chosen to be the root of this molecule and the code is expanding from */ -static bool try_expand_molecule(t_pack_molecule* molecule, +static bool try_expand_molecule(t_pack_molecule& molecule, const AtomBlockId blk_id, - const std::multimap& atom_molecules, + const std::multimap& atom_molecules, const AtomNetlist& atom_nlist) { // root block of the pack pattern, which is the starting point of this pattern - const auto pattern_root_block = molecule->pack_pattern->root_block; + const auto pattern_root_block = molecule.pack_pattern->root_block; // bool array indicating whether a position in a pack pattern is optional or should // be filled with an atom for legality - const auto is_block_optional = molecule->pack_pattern->is_block_optional; + const auto is_block_optional = molecule.pack_pattern->is_block_optional; // create a queue of pattern block and atom block id suggested for this block std::queue> pattern_block_queue; @@ -1054,7 +1014,7 @@ static bool try_expand_molecule(t_pack_molecule* molecule, pattern_block_queue.pop(); // get the atom block id of the atom occupying this primitive position in this molecule - auto molecule_atom_block_id = molecule->atom_block_ids[pattern_block->block_id]; + auto molecule_atom_block_id = molecule.atom_block_ids[pattern_block->block_id]; // if this primitive position in this molecule is already visited and // matches block in the atom netlist go to the next node in the queue @@ -1078,7 +1038,7 @@ static bool try_expand_molecule(t_pack_molecule* molecule, } // set this node in the molecule as visited - molecule->atom_block_ids[pattern_block->block_id] = block_id; + molecule.atom_block_ids[pattern_block->block_id] = block_id; // starting from the first connections, add all the connections of this block to the queue auto block_connection = pattern_block->connections; @@ -1178,13 +1138,12 @@ static AtomBlockId get_driving_block(const AtomBlockId block_id, } static void print_pack_molecules(const char* fname, - const t_pack_patterns* list_of_pack_patterns, + const std::vector& list_of_pack_patterns, const int num_pack_patterns, - const t_pack_molecule* list_of_molecules, + const vtr::vector_map& pack_molecules, const AtomNetlist& atom_nlist) { int i; FILE* fp; - const t_pack_molecule* list_of_molecules_current; fp = std::fopen(fname, "w"); fprintf(fp, "# of pack patterns %d\n", num_pack_patterns); @@ -1198,24 +1157,23 @@ static void print_pack_molecules(const char* fname, list_of_pack_patterns[i].root_block->pb_type->name); } - list_of_molecules_current = list_of_molecules; - while (list_of_molecules_current != nullptr) { - if (list_of_molecules_current->type == MOLECULE_SINGLE_ATOM) { + for (const t_pack_molecule& molecule : pack_molecules) { + if (molecule.type == e_pack_pattern_molecule_type::MOLECULE_SINGLE_ATOM) { fprintf(fp, "\nmolecule type: atom\n"); fprintf(fp, "\tpattern index %d: atom block %s\n", i, - atom_nlist.block_name(list_of_molecules_current->atom_block_ids[0]).c_str()); - } else if (list_of_molecules_current->type == MOLECULE_FORCED_PACK) { + atom_nlist.block_name(molecule.atom_block_ids[0]).c_str()); + } else if (molecule.type == e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK) { fprintf(fp, "\nmolecule type: %s\n", - list_of_molecules_current->pack_pattern->name); - for (i = 0; i < list_of_molecules_current->pack_pattern->num_blocks; + molecule.pack_pattern->name); + for (i = 0; i < molecule.pack_pattern->num_blocks; i++) { - if (!list_of_molecules_current->atom_block_ids[i]) { + if (!molecule.atom_block_ids[i]) { fprintf(fp, "\tpattern index %d: empty \n", i); } else { fprintf(fp, "\tpattern index %d: atom block %s", i, - atom_nlist.block_name(list_of_molecules_current->atom_block_ids[i]).c_str()); - if (list_of_molecules_current->pack_pattern->root_block->block_id == i) { + atom_nlist.block_name(molecule.atom_block_ids[i]).c_str()); + if (molecule.pack_pattern->root_block->block_id == i) { fprintf(fp, " root node\n"); } else { fprintf(fp, "\n"); @@ -1225,7 +1183,6 @@ static void print_pack_molecules(const char* fname, } else { VTR_ASSERT(0); } - list_of_molecules_current = list_of_molecules_current->next; } fclose(fp); @@ -1332,7 +1289,7 @@ static int compare_pack_pattern(const t_pack_patterns* pattern_a, const t_pack_p */ static AtomBlockId find_new_root_atom_for_chain(const AtomBlockId blk_id, const t_pack_patterns* list_of_pack_patterns, - const std::multimap& atom_molecules, + const std::multimap& atom_molecules, const AtomNetlist& atom_nlist) { AtomBlockId new_root_blk_id; t_pb_graph_pin* root_ipin; @@ -1630,14 +1587,16 @@ static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input * and so on. */ static void init_molecule_chain_info(const AtomBlockId blk_id, - t_pack_molecule* molecule, - const std::multimap &atom_molecules, + t_pack_molecule& molecule, + const vtr::vector_map& pack_molecules, + const std::multimap& atom_molecules, + vtr::vector& chain_info, const AtomNetlist& atom_nlist) { // the input molecule to this function should have a pack // pattern assigned to it and the input block should be valid - VTR_ASSERT(molecule->pack_pattern && blk_id); + VTR_ASSERT(molecule.pack_pattern && blk_id); - auto root_ipin = molecule->pack_pattern->chain_root_pins[0][0]; + auto root_ipin = molecule.pack_pattern->chain_root_pins[0][0]; auto model_pin = root_ipin->port->model_port; auto pin_bit = root_ipin->pin_number; @@ -1652,18 +1611,23 @@ static void init_molecule_chain_info(const AtomBlockId blk_id, // if either there is no driver to the block input pin or // if the driver is not part of a molecule if (!driver_atom_id || itr == atom_molecules.end()) { - // allocate chain info - molecule->chain_info = std::make_shared(); - // this is not the first molecule to be created for this chain + MoleculeChainId new_chain_id = MoleculeChainId(chain_info.size()); + t_chain_info new_chain_info; + new_chain_info.is_long_chain = false; + chain_info.push_back(std::move(new_chain_info)); + molecule.chain_id = new_chain_id; } else { + // this is not the first molecule to be created for this chain // molecule driving blk_id - auto prev_molecule = itr->second; + PackMoleculeId prev_molecule_id = itr->second; + VTR_ASSERT(prev_molecule_id.is_valid()); + const t_pack_molecule& prev_molecule = pack_molecules[prev_molecule_id]; // molecule should have chain_info associated with it - VTR_ASSERT(prev_molecule && prev_molecule->chain_info); + VTR_ASSERT(prev_molecule.chain_id.is_valid()); // this molecule is now known to belong to a long chain - prev_molecule->chain_info->is_long_chain = true; - // this new molecule should share the same chain_info - molecule->chain_info = prev_molecule->chain_info; + chain_info[prev_molecule.chain_id].is_long_chain = true; + // this new molecule should share the same chain + molecule.chain_id = prev_molecule.chain_id; } } @@ -1689,55 +1653,44 @@ static void print_chain_starting_points(t_pack_patterns* chain_pattern) { VTR_LOG("\n"); } -/** - * This function frees the linked list of pack molecules. - */ -static void free_pack_molecules(t_pack_molecule* list_of_pack_molecules) { - t_pack_molecule* cur_pack_molecule = list_of_pack_molecules; - while (cur_pack_molecule != nullptr) { - cur_pack_molecule = list_of_pack_molecules->next; - delete list_of_pack_molecules; - list_of_pack_molecules = cur_pack_molecule; - } -} - -void Prepacker::init(const AtomNetlist& atom_nlist, const std::vector& logical_block_types) { - VTR_ASSERT(list_of_pack_molecules == nullptr && "Prepacker cannot be initialized twice."); +Prepacker::Prepacker(const AtomNetlist& atom_nlist, + const std::vector& logical_block_types) { + vtr::ScopedStartFinishTimer prepacker_timer("Prepacker"); // Allocate the pack patterns from the logical block types. list_of_pack_patterns = alloc_and_load_pack_patterns(logical_block_types); // Use the pack patterns to allocate and load the pack molecules. - std::multimap atom_molecules_multimap; + std::multimap atom_molecules_multimap; expected_lowest_cost_pb_gnode.resize(atom_nlist.blocks().size(), nullptr); - list_of_pack_molecules = alloc_and_load_pack_molecules(list_of_pack_patterns.data(), - expected_lowest_cost_pb_gnode, - list_of_pack_patterns.size(), - atom_molecules_multimap, - atom_nlist, - logical_block_types); + alloc_and_load_pack_molecules(atom_molecules_multimap, + atom_nlist, + logical_block_types); // The multimap is a legacy thing. Since blocks can be part of multiple pack // patterns, during prepacking a block may be contained within multiple // molecules. However, by the end of prepacking, molecules should be // combined such that each block is contained in one and only one molecule. - atom_molecules.resize(atom_nlist.blocks().size(), nullptr); + atom_molecule_.resize(atom_nlist.blocks().size(), PackMoleculeId::INVALID()); for (AtomBlockId blk_id : atom_nlist.blocks()) { // Every atom block should be packed into a single molecule (no more // or less). VTR_ASSERT(atom_molecules_multimap.count(blk_id) == 1); - atom_molecules[blk_id] = atom_molecules_multimap.find(blk_id)->second; + atom_molecule_[blk_id] = atom_molecules_multimap.find(blk_id)->second; } } // TODO: Since this is constant per molecule, it may make sense to precompute // this information and store it in the prepacker class. This may be // expensive to calculate for large molecules. -t_molecule_stats Prepacker::calc_molecule_stats(const t_pack_molecule* molecule, +t_molecule_stats Prepacker::calc_molecule_stats(PackMoleculeId molecule_id, const AtomNetlist& atom_nlist) const { + VTR_ASSERT(molecule_id.is_valid()); t_molecule_stats molecule_stats; + const t_pack_molecule& molecule = pack_molecules_[molecule_id]; + //Calculate the number of available pins on primitives within the molecule - for (auto blk : molecule->atom_block_ids) { + for (auto blk : molecule.atom_block_ids) { if (!blk) continue; ++molecule_stats.num_blocks; //Record number of valid blocks in molecule @@ -1755,8 +1708,8 @@ t_molecule_stats Prepacker::calc_molecule_stats(const t_pack_molecule* molecule, molecule_stats.num_pins = molecule_stats.num_input_pins + molecule_stats.num_output_pins; //Calculate the number of externally used pins - std::set molecule_atoms(molecule->atom_block_ids.begin(), molecule->atom_block_ids.end()); - for (auto blk : molecule->atom_block_ids) { + std::set molecule_atoms(molecule.atom_block_ids.begin(), molecule.atom_block_ids.end()); + for (auto blk : molecule.atom_block_ids) { if (!blk) continue; for (auto pin : atom_nlist.block_pins(blk)) { @@ -1803,11 +1756,9 @@ t_molecule_stats Prepacker::calc_molecule_stats(const t_pack_molecule* molecule, t_molecule_stats Prepacker::calc_max_molecule_stats(const AtomNetlist& atom_nlist) const { t_molecule_stats max_molecules_stats; - t_pack_molecule* molecule_head = list_of_pack_molecules; - for (auto cur_molecule = molecule_head; cur_molecule != nullptr; cur_molecule = cur_molecule->next) { + for (PackMoleculeId molecule_id : molecules()) { //Calculate per-molecule statistics - (void)atom_nlist; - t_molecule_stats cur_molecule_stats = calc_molecule_stats(cur_molecule, atom_nlist); + t_molecule_stats cur_molecule_stats = calc_molecule_stats(molecule_id, atom_nlist); //Record the maximums (member-wise) over all molecules max_molecules_stats.num_blocks = std::max(max_molecules_stats.num_blocks, cur_molecule_stats.num_blocks); @@ -1824,15 +1775,8 @@ t_molecule_stats Prepacker::calc_max_molecule_stats(const AtomNetlist& atom_nlis return max_molecules_stats; } -void Prepacker::reset() { +Prepacker::~Prepacker() { // When the prepacker is reset (or destroyed), clean up the internal data // members. free_list_of_pack_patterns(list_of_pack_patterns); - free_pack_molecules(list_of_pack_molecules); - // Reset everything to default state. - list_of_pack_patterns.clear(); - list_of_pack_molecules = nullptr; - atom_molecules.clear(); - expected_lowest_cost_pb_gnode.clear(); } - diff --git a/vpr/src/pack/prepack.h b/vpr/src/pack/prepack.h index 810c79bd19c..5222046ddb6 100644 --- a/vpr/src/pack/prepack.h +++ b/vpr/src/pack/prepack.h @@ -7,19 +7,111 @@ * 2) Carry-chains */ -#ifndef PREPACK_H -#define PREPACK_H +#pragma once #include -#include "vpr_types.h" +#include "atom_netlist_fwd.h" +#include "cad_types.h" #include "vtr_assert.h" +#include "vtr_range.h" +#include "vtr_strong_id.h" #include "vtr_vector.h" +#include "vtr_vector_map.h" -class AtomNetlist; -class AtomBlockId; -struct t_molecule_stats; +// Forward declarations +class t_pack_molecule; struct t_logical_block_type; +// A unique ID used to identify a molecule generated by the prepacker. +struct pack_molecule_id_tag; +typedef vtr::StrongId PackMoleculeId; + +// A unique ID used to identify a chain of molecules generated by the prepacker. +struct molecule_chain_id_tag; +typedef vtr::StrongId MoleculeChainId; + +/** + * @brief Holds general information to be shared between molecules that + * represent the same chained pack pattern. + * + * For example, molecules that are representing a long carry chain that spans + * multiple logic blocks. + */ +struct t_chain_info { + /// @brief Is this a long chain that is divided on multiple clusters + /// (divided on multiple molecules). + bool is_long_chain = false; +}; + +/** + * @brief Describes the molecule pack pattern type. + */ +enum class e_pack_pattern_molecule_type : bool { + MOLECULE_SINGLE_ATOM, ///root_block in the atom_blocks_ids. + /// root_block_id = atom_block_ids[root] + int root; + + /// @brief [0..num_blocks-1] IDs of atom blocks that implements this molecule, + /// indexed by t_pack_pattern_block->block_id. + /// + /// This vector may contain invalid atom block ids (when the molecule does + /// not completely fill the pattern). + std::vector atom_block_ids; + + /// @brief The unique ID of the chain this molecule is a part of if is_chain. + /// If this molecule is not part of a chain, this would be invalid. + /// + /// Multiple molecules may point to the same chain. + MoleculeChainId chain_id; + + // ========================================================================= + // Class methods + // ========================================================================= + + // A molecule is a chain if it is a forced pack and its pack pattern is a chain + inline bool is_chain() const { + return type == e_pack_pattern_molecule_type::MOLECULE_FORCED_PACK && pack_pattern->is_chain; + } +}; + /** * @brief Statistics on a molecule. * @@ -69,7 +161,7 @@ struct t_molecule_stats { * // Initialize device and atom netlist * // ... * Prepacker prepacker; - * prepacker.init(atom_ctx.nlist, device_ctx.logical_block_types); + * prepacker.init(atom_ctx.netlist(), device_ctx.logical_block_types); * // ... * // Use the prepacked molecules. * // ... @@ -78,17 +170,23 @@ struct t_molecule_stats { * */ class Prepacker { -public: - // The constructor is default, the init method performs prepacking. - Prepacker() = default; + public: + // Iterator for the pack molecule IDs + typedef typename vtr::vector_map::const_iterator molecule_iterator; + + // Range for the pack molecule IDs + typedef typename vtr::Range molecule_range; // This class maintains pointers to internal data structures, and as such // should not be copied or moved (prevents unsafe accesses). Prepacker(const Prepacker&) = delete; Prepacker& operator=(const Prepacker&) = delete; + // Destructor of the class. + ~Prepacker(); + /** - * @brief Performs prepacking. + * @brief Construtor. Performs prepacking. * * Initializes the prepacker by performing prepacking and allocating the * necessary data strucutres. @@ -96,19 +194,28 @@ class Prepacker { * @param atom_nlist The atom netlist to prepack. * @param logical_block_types A list of the logical block types on the device. */ - void init(const AtomNetlist& atom_nlist, const std::vector &logical_block_types); + Prepacker(const AtomNetlist& atom_nlist, + const std::vector& logical_block_types); + + /** + * @brief A range of all prepacked molecules. Every atom should exist in one + * of these molecules. + */ + inline molecule_range molecules() const { + return vtr::make_range(pack_molecule_ids_.begin(), pack_molecule_ids_.end()); + } /** * @brief Get the cluster molecule containing the given atom block. * * @param blk_id The atom block to get the molecule of. */ - inline t_pack_molecule* get_atom_molecule(AtomBlockId blk_id) const { + inline PackMoleculeId get_atom_molecule(AtomBlockId blk_id) const { // Safety debug to ensure the blk is valid and has a molecule entry. - VTR_ASSERT_SAFE(blk_id.is_valid() && (size_t)blk_id < atom_molecules.size()); + VTR_ASSERT_SAFE(blk_id.is_valid() && (size_t)blk_id < atom_molecule_.size()); // Safety debug to ensure the molecule is valid - VTR_ASSERT_DEBUG(atom_molecules[blk_id] != nullptr); - return atom_molecules[blk_id]; + VTR_ASSERT_DEBUG(atom_molecule_[blk_id].is_valid()); + return atom_molecule_[blk_id]; } /** @@ -125,34 +232,10 @@ class Prepacker { return expected_lowest_cost_pb_gnode[blk_id]; } - /** - * @brief Returns the total number of molecules in the prepacker. - */ - inline size_t get_num_molecules() const { - size_t num_molecules = 0; - t_pack_molecule* molecule_head = list_of_pack_molecules; - for (auto cur_molecule = molecule_head; cur_molecule != nullptr; cur_molecule = cur_molecule->next) { - ++num_molecules; - } - return num_molecules; - } - - /** - * @brief Returns all of the molecules as a vector. - */ - inline std::vector get_molecules_vector() const { - std::vector molecules; - t_pack_molecule* molecule_head = list_of_pack_molecules; - for (auto cur_molecule = molecule_head; cur_molecule != nullptr; cur_molecule = cur_molecule->next) { - molecules.push_back(cur_molecule); - } - return molecules; - } - /* * @brief Calculates molecule statistics for a single molecule. */ - t_molecule_stats calc_molecule_stats(const t_pack_molecule* molecule, + t_molecule_stats calc_molecule_stats(PackMoleculeId molecule_id, const AtomNetlist& atom_netlist) const; /** @@ -165,37 +248,93 @@ class Prepacker { */ inline size_t get_max_molecule_size() const { size_t max_molecule_size = 1; - t_pack_molecule* molecule_head = list_of_pack_molecules; - for (auto cur_molecule = molecule_head; cur_molecule != nullptr; cur_molecule = cur_molecule->next) { - max_molecule_size = std::max(max_molecule_size, cur_molecule->num_blocks); + for (const t_pack_molecule& molecule : pack_molecules_) { + max_molecule_size = std::max(max_molecule_size, molecule.atom_block_ids.size()); } return max_molecule_size; } /** - * @brief Resets the prepacker object. Clearing all state. - * - * This resets the prepacker, allowing it to prepack again and also freeing - * any state. + * @brief Get information about the molecule associated with the given ID. + */ + inline const t_pack_molecule& get_molecule(PackMoleculeId molecule_id) const { + VTR_ASSERT(molecule_id.is_valid()); + return pack_molecules_[molecule_id]; + } + + /** + * @brief Get the root atom of this molecule. + */ + inline AtomBlockId get_molecule_root_atom(PackMoleculeId molecule_id) const { + VTR_ASSERT_SAFE_MSG(molecule_id.is_valid(), "Invalid molecule ID"); + const t_pack_molecule& mol = get_molecule(molecule_id); + return mol.atom_block_ids[mol.root]; + } + + /** + * @brief Get information about the chain associated with the given ID. + */ + inline const t_chain_info& get_molecule_chain_info(MoleculeChainId chain_id) const { + VTR_ASSERT(chain_id.is_valid()); + return chain_info_[chain_id]; + } + + /** + * @brief Get the number of unique molecule chains from the prepacker. */ - void reset(); + inline size_t get_num_molecule_chains() const { + return chain_info_.size(); + } - /// @brief Destructor of the prepacker class. Calls the reset method. - ~Prepacker() { reset(); } + /** + * @brief Get a list of all the pack patterns in the architecture. + */ + inline const std::vector& get_all_pack_patterns() const { + return list_of_pack_patterns; + } -private: + private: /** - * @brief A linked list of all the packing molecules that are loaded in - * prepacking stage. + * Pre-pack atoms in netlist to molecules + * 1. Single atoms are by definition a molecule. + * 2. Forced pack molecules are groupings of atoms that matches a t_pack_pattern definition. + * 3. Chained molecules are molecules that follow a carry-chain style pattern, + * ie. a single linear chain that can be split across multiple complex blocks + */ + void alloc_and_load_pack_molecules(std::multimap& atom_molecules_multimap, + const AtomNetlist& atom_nlist, + const std::vector& logical_block_types); + + /** + * Given a pattern and an atom block to serve as the root block, determine if + * the candidate atom block serving as the root node matches the pattern. + * If yes, return the molecule with this atom block as the root, if not, return NULL * - * All of the molecules in the prepacker are allocated into this linked list - * and must be freed eventually. + * Limitations: Currently assumes that forced pack nets must be single-fanout as + * this covers all the reasonable architectures we wanted. More complicated + * structures should probably be handled either downstream (general packing) + * or upstream (in tech mapping). + * If this limitation is too constraining, code is designed so that this limitation can be removed * - * TODO: Should use a vtr::vector instead of a linked list for storage. Then - * instead of pointers, IDs can be used to manipulate the molecules - * which would be safer. + * Side Effect: If successful, link atom to molecule + */ + PackMoleculeId try_create_molecule(const int pack_pattern_index, + AtomBlockId blk_id, + std::multimap& atom_molecules_multimap, + const AtomNetlist& atom_nlist); + + private: + /** + * @brief Collection of all molecule IDs. If an entry in this map is invalid + * it means that the molecule should be destroyed. + */ + vtr::vector_map pack_molecule_ids_; + + /** + * @brief Lookup between each molecule ID and the information associated with + * that molecule. */ - t_pack_molecule* list_of_pack_molecules = nullptr; + vtr::vector_map pack_molecules_; /** * @brief The molecules associated with each atom block. @@ -203,7 +342,7 @@ class Prepacker { * This vector is loaded in the init method and cleared in the reset method. * The pointers in this vector are shared with list_of_pack_molecules. */ - vtr::vector atom_molecules; + vtr::vector atom_molecule_; /// @brief A vector of the expected lowest cost physical block graph node. vtr::vector expected_lowest_cost_pb_gnode; @@ -212,6 +351,10 @@ class Prepacker { /// molecules keep pointers to this vector, so this needs to remain /// for the lifetime of the molecules. std::vector list_of_pack_patterns; -}; -#endif + /** + * @brief Lookup between each chain ID and the information associated with + * that chain. + */ + vtr::vector chain_info_; +}; diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.cpp b/vpr/src/pack/sync_netlists_to_routing_flat.cpp index 8aa54bb7f1a..0e6be438300 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.cpp +++ b/vpr/src/pack/sync_netlists_to_routing_flat.cpp @@ -1,23 +1,19 @@ /** -* @file sync_netlists_to_routing_flat.cpp -* -* @brief Implementation for \see sync_netlists_to_routing_flat(). -*/ + * @file sync_netlists_to_routing_flat.cpp + * + * @brief Implementation for \see sync_netlists_to_routing_flat(). + */ #include "clustered_netlist_fwd.h" -#include "clustered_netlist_utils.h" #include "logic_types.h" #include "netlist_fwd.h" #include "physical_types.h" +#include "physical_types_util.h" #include "vtr_time.h" #include "vtr_assert.h" -#include "vtr_log.h" -#include "annotate_routing.h" #include "globals.h" -#include "vpr_error.h" #include "vpr_utils.h" -#include "rr_graph2.h" #include "sync_netlists_to_routing_flat.h" @@ -44,20 +40,19 @@ static void sync_clustered_netlist_to_routing(void); * (i.e. the primitive has equivalent input pins and flat routing used a different pin) */ static void fixup_atom_pb_graph_pin_mapping(void); - /* Function definitions */ /** Is the clock net found in the routing results? * (If not, clock_modeling is probably ideal and we should preserve clock routing while rebuilding.) */ -inline bool is_clock_net_routed(void){ +inline bool is_clock_net_routed(void) { auto& atom_ctx = g_vpr_ctx.atom(); auto& route_ctx = g_vpr_ctx.routing(); - for(auto net_id: atom_ctx.nlist.nets()){ + for (auto net_id : atom_ctx.netlist().nets()) { auto& tree = route_ctx.route_trees[net_id]; - if(!tree) + if (!tree) continue; - if(route_ctx.is_clock_net[net_id]) /* Clock net has routing */ + if (route_ctx.is_clock_net[net_id]) /* Clock net has routing */ return true; } @@ -65,7 +60,7 @@ inline bool is_clock_net_routed(void){ } /** Get the ClusterBlockId for a given RRNodeId. */ -inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode){ +inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode) { auto& device_ctx = g_vpr_ctx.device(); auto& place_ctx = g_vpr_ctx.placement(); auto& rr_graph = device_ctx.rr_graph; @@ -85,38 +80,36 @@ inline ClusterBlockId get_cluster_block_from_rr_node(RRNodeId inode){ int width_offset = device_ctx.grid.get_width_offset(node_phy_tile_loc); int height_offset = device_ctx.grid.get_height_offset(node_phy_tile_loc); - ClusterBlockId clb = place_ctx.grid_blocks().block_at_location({ - rr_graph.node_xlow(inode) - width_offset, - rr_graph.node_ylow(inode) - height_offset, - subtile, - rr_graph.node_layer(inode) - }); + ClusterBlockId clb = place_ctx.grid_blocks().block_at_location({rr_graph.node_xlow(inode) - width_offset, + rr_graph.node_ylow(inode) - height_offset, + subtile, + rr_graph.node_layer(inode)}); return clb; } -static void get_intra_cluster_connections(const RouteTree& tree, std::vector>& out_connections){ +static void get_intra_cluster_connections(const RouteTree& tree, std::vector>& out_connections) { auto& rr_graph = g_vpr_ctx.device().rr_graph; - for(auto& node: tree.all_nodes()){ + for (auto& node : tree.all_nodes()) { const auto& parent = node.parent(); - if(!parent) /* Root */ + if (!parent) /* Root */ continue; /* Find the case where both nodes are IPIN/OPINs and on the same block */ auto type = rr_graph.node_type(node.inode); auto parent_type = rr_graph.node_type(parent->inode); - if((type == IPIN || type == OPIN) && (parent_type == IPIN || parent_type == OPIN)){ + if ((type == IPIN || type == OPIN) && (parent_type == IPIN || parent_type == OPIN)) { auto clb = get_cluster_block_from_rr_node(node.inode); auto parent_clb = get_cluster_block_from_rr_node(parent->inode); - if(clb == parent_clb) + if (clb == parent_clb) out_connections.push_back({parent->inode, node.inode}); } } } -static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_pb_graph_pin* sink_pin, AtomNetId net_id, t_pb* out_pb){ +static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_pb_graph_pin* sink_pin, AtomNetId net_id, t_pb* out_pb) { std::unordered_set visited; std::deque queue; std::unordered_map prev; @@ -126,31 +119,31 @@ static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_p queue.push_back(source_pin); prev[source_pin] = NULL; - while(!queue.empty()){ + while (!queue.empty()) { const t_pb_graph_pin* cur_pin = queue.front(); queue.pop_front(); - if(visited.count(cur_pin)) + if (visited.count(cur_pin)) continue; visited.insert(cur_pin); /* Backtrack and return */ - if(cur_pin == sink_pin){ + if (cur_pin == sink_pin) { break; } - for(auto& edge: cur_pin->output_edges){ + for (auto& edge : cur_pin->output_edges) { VTR_ASSERT(edge->num_output_pins == 1); queue.push_back(edge->output_pins[0]); prev[edge->output_pins[0]] = cur_pin; } } - + VTR_ASSERT_MSG(visited.count(sink_pin), "Couldn't find sink pin"); /* Collect path: we need to build pb_routes from source to sink */ std::vector path; const t_pb_graph_pin* cur_pin = sink_pin; - while(cur_pin != source_pin){ + while (cur_pin != source_pin) { path.push_back(cur_pin); cur_pin = prev[cur_pin]; } @@ -158,25 +151,24 @@ static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_p /* Output the path into out_pb, starting from source. This is where the pb_route is updated */ int prev_pin_id = -1; - for(auto it = path.rbegin(); it != path.rend(); ++it){ + for (auto it = path.rbegin(); it != path.rend(); ++it) { cur_pin = *it; int cur_pin_id = cur_pin->pin_count_in_cluster; t_pb_route* cur_pb_route; - if(out_pb_routes.count(cur_pin_id)) + if (out_pb_routes.count(cur_pin_id)) cur_pb_route = &out_pb_routes[cur_pin_id]; else { t_pb_route pb_route = { net_id, -1, {}, - cur_pin - }; + cur_pin}; out_pb_routes.insert(std::make_pair<>(cur_pin_id, pb_route)); cur_pb_route = &out_pb_routes[cur_pin_id]; } - if(prev_pin_id != -1){ + if (prev_pin_id != -1) { t_pb_route& prev_pb_route = out_pb_routes[prev_pin_id]; prev_pb_route.sink_pb_pin_ids.push_back(cur_pin_id); cur_pb_route->driver_pb_pin_id = prev_pb_route.pb_graph_pin->pin_count_in_cluster; @@ -186,7 +178,7 @@ static void route_intra_cluster_conn(const t_pb_graph_pin* source_pin, const t_p } } -static void sync_pb_routes_to_routing(void){ +static void sync_pb_routes_to_routing(void) { auto& device_ctx = g_vpr_ctx.device(); auto& atom_ctx = g_vpr_ctx.atom(); auto& cluster_ctx = g_vpr_ctx.mutable_clustering(); @@ -202,20 +194,20 @@ static void sync_pb_routes_to_routing(void){ * Otherwise we won't have data to rebuild them */ std::vector pins_to_erase; auto& pb_routes = cluster_ctx.clb_nlist.block_pb(clb_blk_id)->pb_route; - for(auto& [pin, pb_route]: pb_routes){ - if(clock_net_is_routed || !route_ctx.is_clock_net[pb_route.atom_net_id]) + for (auto& [pin, pb_route] : pb_routes) { + if (clock_net_is_routed || !route_ctx.is_clock_net[pb_route.atom_net_id]) pins_to_erase.push_back(pin); } - for(int pin: pins_to_erase){ + for (int pin : pins_to_erase) { pb_routes.erase(pin); } } /* Go through each route tree and rebuild the pb_routes */ - for(ParentNetId net_id: atom_ctx.nlist.nets()){ + for (ParentNetId net_id : atom_ctx.netlist().nets()) { auto& tree = route_ctx.route_trees[net_id]; - if(!tree) + if (!tree) continue; /* No routing at this ParentNetId */ /* Get all intrablock connections */ @@ -223,26 +215,24 @@ static void sync_pb_routes_to_routing(void){ get_intra_cluster_connections(tree.value(), conns_to_restore); /* Restore the connections */ - for(auto [source_inode, sink_inode]: conns_to_restore){ + for (auto [source_inode, sink_inode] : conns_to_restore) { ClusterBlockId clb = get_cluster_block_from_rr_node(source_inode); - auto physical_tile = device_ctx.grid.get_physical_type({ - rr_graph.node_xlow(source_inode), - rr_graph.node_ylow(source_inode), - rr_graph.node_layer(source_inode) - }); + auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(source_inode), + rr_graph.node_ylow(source_inode), + rr_graph.node_layer(source_inode)}); int source_pin = rr_graph.node_pin_num(source_inode); int sink_pin = rr_graph.node_pin_num(sink_inode); /* Look up pb graph pins from pb type if pin is not on tile, look up from block otherwise */ - const t_pb_graph_pin* source_pb_graph_pin, *sink_pb_graph_pin; - if(is_pin_on_tile(physical_tile, sink_pin)){ + const t_pb_graph_pin *source_pb_graph_pin, *sink_pb_graph_pin; + if (is_pin_on_tile(physical_tile, sink_pin)) { sink_pb_graph_pin = get_pb_graph_node_pin_from_block_pin(clb, sink_pin); - }else{ + } else { sink_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_tile, sink_pin); } - if(is_pin_on_tile(physical_tile, source_pin)){ + if (is_pin_on_tile(physical_tile, source_pin)) { source_pb_graph_pin = get_pb_graph_node_pin_from_block_pin(clb, source_pin); - }else{ + } else { source_pb_graph_pin = get_pb_pin_from_pin_physical_num(physical_tile, source_pin); } @@ -255,20 +245,20 @@ static void sync_pb_routes_to_routing(void){ } /** Rebuild the ClusterNetId <-> AtomNetId lookup after compressing the ClusterNetlist. - * Needs the old ClusterNetIds in atom_ctx.lookup. Won't work after calling compress() twice, + * Needs the old ClusterNetIds in atom_ctx.lookup(). Won't work after calling compress() twice, * since we won't have access to the old IDs in the IdRemapper anywhere. */ -inline void rebuild_atom_nets_lookup(ClusteredNetlist::IdRemapper& remapped){ +inline void rebuild_atom_nets_lookup(ClusteredNetlist::IdRemapper& remapped) { auto& atom_ctx = g_vpr_ctx.mutable_atom(); - auto& atom_lookup = atom_ctx.lookup; + auto& atom_lookup = atom_ctx.mutable_lookup(); - for(auto parent_net_id: atom_ctx.nlist.nets()){ + for (auto parent_net_id : atom_ctx.netlist().nets()) { auto atom_net_id = convert_to_atom_net_id(parent_net_id); auto old_clb_nets_opt = atom_lookup.clb_nets(atom_net_id); - if(!old_clb_nets_opt) + if (!old_clb_nets_opt) continue; std::vector old_clb_nets = old_clb_nets_opt.value(); atom_lookup.remove_atom_net(atom_net_id); - for(auto old_clb_net: old_clb_nets){ + for (auto old_clb_net : old_clb_nets) { ClusterNetId new_clb_net = remapped.new_net_id(old_clb_net); atom_lookup.add_atom_clb_net(atom_net_id, new_clb_net); } @@ -276,7 +266,7 @@ inline void rebuild_atom_nets_lookup(ClusteredNetlist::IdRemapper& remapped){ } /** Regenerate clustered netlist nets from routing results */ -static void sync_clustered_netlist_to_routing(void){ +static void sync_clustered_netlist_to_routing(void) { auto& cluster_ctx = g_vpr_ctx.mutable_clustering(); auto& place_ctx = g_vpr_ctx.mutable_placement(); auto& route_ctx = g_vpr_ctx.routing(); @@ -284,7 +274,7 @@ static void sync_clustered_netlist_to_routing(void){ auto& device_ctx = g_vpr_ctx.device(); auto& rr_graph = device_ctx.rr_graph; auto& atom_ctx = g_vpr_ctx.mutable_atom(); - auto& atom_lookup = atom_ctx.lookup; + auto& atom_lookup = atom_ctx.lookup(); bool clock_net_is_routed = is_clock_net_routed(); @@ -295,25 +285,25 @@ static void sync_clustered_netlist_to_routing(void){ std::vector pins_to_remove; std::vector ports_to_remove; - for(auto net_id: clb_netlist.nets()){ + for (auto net_id : clb_netlist.nets()) { auto atom_net_id = atom_lookup.atom_net(net_id); - if(!clock_net_is_routed && route_ctx.is_clock_net[atom_net_id]) + if (!clock_net_is_routed && route_ctx.is_clock_net[atom_net_id]) continue; nets_to_remove.push_back(net_id); } - for(auto pin_id: clb_netlist.pins()){ + for (auto pin_id : clb_netlist.pins()) { ClusterNetId clb_net_id = clb_netlist.pin_net(pin_id); auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if(!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) + if (!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) continue; pins_to_remove.push_back(pin_id); } - for(auto port_id: clb_netlist.ports()){ + for (auto port_id : clb_netlist.ports()) { ClusterNetId clb_net_id = clb_netlist.port_net(port_id, 0); auto atom_net_id = atom_lookup.atom_net(clb_net_id); - if(!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) + if (!clock_net_is_routed && atom_net_id && route_ctx.is_clock_net[atom_net_id]) continue; ports_to_remove.push_back(port_id); @@ -321,14 +311,14 @@ static void sync_clustered_netlist_to_routing(void){ /* ClusteredNetlist's iterators rely on internal lookups, so we mark for removal * while iterating, then remove in bulk */ - for(auto net_id: nets_to_remove){ + for (auto net_id : nets_to_remove) { clb_netlist.remove_net(net_id); - atom_lookup.remove_clb_net(net_id); + atom_ctx.mutable_lookup().remove_clb_net(net_id); } - for(auto pin_id: pins_to_remove){ + for (auto pin_id : pins_to_remove) { clb_netlist.remove_pin(pin_id); } - for(auto port_id: ports_to_remove){ + for (auto port_id : ports_to_remove) { clb_netlist.remove_port(port_id); } @@ -338,51 +328,49 @@ static void sync_clustered_netlist_to_routing(void){ /* 3. Walk each routing in the atom netlist. If a node is on the tile, add a ClusterPinId for it. * Add the associated net and port too if they don't exist */ - for(auto parent_net_id: atom_ctx.nlist.nets()){ + for (auto parent_net_id : atom_ctx.netlist().nets()) { auto& tree = route_ctx.route_trees[parent_net_id]; AtomNetId atom_net_id = convert_to_atom_net_id(parent_net_id); ClusterNetId clb_net_id; int clb_nets_so_far = 0; - for(auto& rt_node: tree->all_nodes()){ + for (auto& rt_node : tree->all_nodes()) { auto node_type = rr_graph.node_type(rt_node.inode); - if(node_type != IPIN && node_type != OPIN) + if (node_type != IPIN && node_type != OPIN) continue; - auto physical_tile = device_ctx.grid.get_physical_type({ - rr_graph.node_xlow(rt_node.inode), - rr_graph.node_ylow(rt_node.inode), - rr_graph.node_layer(rt_node.inode) - }); + auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rt_node.inode), + rr_graph.node_ylow(rt_node.inode), + rr_graph.node_layer(rt_node.inode)}); int pin_index = rr_graph.node_pin_num(rt_node.inode); ClusterBlockId clb = get_cluster_block_from_rr_node(rt_node.inode); - if(!is_pin_on_tile(physical_tile, pin_index)) + if (!is_pin_on_tile(physical_tile, pin_index)) continue; /* OPIN on the tile: create a new clb_net_id and add all ports & pins into here * Due to how the route tree is traversed, all nodes until the next OPIN on the tile will * be under this OPIN, so this is valid (we don't need to get the branch explicitly) */ - if(node_type == OPIN){ + if (node_type == OPIN) { std::string net_name; - net_name = atom_ctx.nlist.net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); + net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far); clb_net_id = clb_netlist.create_net(net_name); - atom_lookup.add_atom_clb_net(atom_net_id, clb_net_id); + atom_ctx.mutable_lookup().add_atom_clb_net(atom_net_id, clb_net_id); clb_nets_so_far++; } t_pb_graph_pin* pb_graph_pin = get_pb_graph_node_pin_from_block_pin(clb, pin_index); ClusterPortId port_id = clb_netlist.find_port(clb, pb_graph_pin->port->name); - if(!port_id){ + if (!port_id) { PortType port_type; - if(pb_graph_pin->port->is_clock) + if (pb_graph_pin->port->is_clock) port_type = PortType::CLOCK; - else if(pb_graph_pin->port->type == IN_PORT) + else if (pb_graph_pin->port->type == IN_PORT) port_type = PortType::INPUT; - else if(pb_graph_pin->port->type == OUT_PORT) + else if (pb_graph_pin->port->type == OUT_PORT) port_type = PortType::OUTPUT; else VTR_ASSERT_MSG(false, "Unsupported port type"); @@ -402,40 +390,40 @@ static void sync_clustered_netlist_to_routing(void){ auto& blk_loc_registry = place_ctx.mutable_blk_loc_registry(); auto& physical_pins = place_ctx.mutable_physical_pins(); physical_pins.clear(); - for(auto clb: clb_netlist.blocks()){ + for (auto clb : clb_netlist.blocks()) { blk_loc_registry.place_sync_external_block_connections(clb); } } -static void fixup_atom_pb_graph_pin_mapping(void){ +static void fixup_atom_pb_graph_pin_mapping(void) { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& atom_ctx = g_vpr_ctx.mutable_atom(); - for(ClusterBlockId clb: cluster_ctx.clb_nlist.blocks()){ + for (ClusterBlockId clb : cluster_ctx.clb_nlist.blocks()) { /* Collect all innermost pb routes */ std::vector sink_pb_route_ids; t_pb* clb_pb = cluster_ctx.clb_nlist.block_pb(clb); - for(auto [pb_route_id, pb_route]: clb_pb->pb_route){ - if(pb_route.sink_pb_pin_ids.empty()) + for (auto [pb_route_id, pb_route] : clb_pb->pb_route) { + if (pb_route.sink_pb_pin_ids.empty()) sink_pb_route_ids.push_back(pb_route_id); } - for(int sink_pb_route_id: sink_pb_route_ids){ + for (int sink_pb_route_id : sink_pb_route_ids) { t_pb_route& pb_route = clb_pb->pb_route.at(sink_pb_route_id); const t_pb_graph_pin* atom_pbg_pin = pb_route.pb_graph_pin; t_pb* atom_pb = clb_pb->find_mutable_pb(atom_pbg_pin->parent_node); - AtomBlockId atb = atom_ctx.lookup.pb_atom(atom_pb); - if(!atb) + AtomBlockId atb = atom_ctx.lookup().atom_pb_bimap().pb_atom(atom_pb); + if (!atb) continue; /* Find atom port from pbg pin's model port */ - AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atb, atom_pbg_pin->port->model_port); - for(AtomPinId atom_pin: atom_ctx.nlist.port_pins(atom_port)){ + AtomPortId atom_port = atom_ctx.netlist().find_atom_port(atb, atom_pbg_pin->port->model_port); + for (AtomPinId atom_pin : atom_ctx.netlist().port_pins(atom_port)) { /* Match net IDs from pb_route and atom netlist and connect in lookup */ - if(pb_route.atom_net_id == atom_ctx.nlist.pin_net(atom_pin)){ - atom_ctx.lookup.set_atom_pin_pb_graph_pin(atom_pin, atom_pbg_pin); - atom_pb->set_atom_pin_bit_index(atom_pbg_pin, atom_ctx.nlist.pin_port_bit(atom_pin)); + if (pb_route.atom_net_id == atom_ctx.netlist().pin_net(atom_pin)) { + atom_ctx.mutable_lookup().set_atom_pin_pb_graph_pin(atom_pin, atom_pbg_pin); + atom_pb->set_atom_pin_bit_index(atom_pbg_pin, atom_ctx.netlist().pin_port_bit(atom_pin)); } } } diff --git a/vpr/src/pack/sync_netlists_to_routing_flat.h b/vpr/src/pack/sync_netlists_to_routing_flat.h index 9403eb1c2a9..0c1bc7d77d3 100644 --- a/vpr/src/pack/sync_netlists_to_routing_flat.h +++ b/vpr/src/pack/sync_netlists_to_routing_flat.h @@ -1,6 +1,6 @@ #include "netlist.h" - /******************************************************************** +/******************************************************************** * Top-level function to synchronize packing results to routing results. * Flat routing invalidates the ClusteredNetlist since nets may be routed * inside or outside a block and changes virtually all intrablock routing. diff --git a/vpr/src/pack/verify_clustering.cpp b/vpr/src/pack/verify_clustering.cpp index a833ce473d6..ec08e10a40b 100644 --- a/vpr/src/pack/verify_clustering.cpp +++ b/vpr/src/pack/verify_clustering.cpp @@ -107,7 +107,7 @@ static bool is_atom_pb_in_cluster_pb(AtomBlockId atom_blk_id, const AtomLookup& atom_lookup, const ClusteredNetlist& clb_nlist) { // Get the pbs - const t_pb* atom_pb = atom_lookup.atom_pb(atom_blk_id); + const t_pb* atom_pb = atom_lookup.atom_pb_bimap().atom_pb(atom_blk_id); const t_pb* cluster_pb = clb_nlist.block_pb(clb_blk_id); // For the atom pb to be a part of the cluster pb, the atom pb must be a // descendent of the cluster pb (the cluster pb is the ancestor to all atom @@ -179,7 +179,7 @@ static unsigned check_clustering_pb_consistency(const ClusteredNetlist& clb_nlis ClusterBlockId atom_clb_blk_id = atom_lookup.atom_clb(atom_blk_id); if (!atom_clb_blk_id.is_valid()) continue; - const t_pb* atom_pb = atom_lookup.atom_pb(atom_blk_id); + const t_pb* atom_pb = atom_lookup.atom_pb_bimap().atom_pb(atom_blk_id); // Make sure the atom's pb exists if (atom_pb == nullptr) { VTR_LOG_ERROR( @@ -188,7 +188,7 @@ static unsigned check_clustering_pb_consistency(const ClusteredNetlist& clb_nlis num_errors++; } else { // Sanity check: atom_pb == pb_atom - if (atom_lookup.pb_atom(atom_pb) != atom_blk_id) { + if (atom_lookup.atom_pb_bimap().pb_atom(atom_pb) != atom_blk_id) { VTR_LOG_ERROR( "Atom block %zu in cluster block %zu has a pb which " "belongs to another atom.\n", @@ -243,10 +243,10 @@ static unsigned check_clustering_pb_consistency(const ClusteredNetlist& clb_nlis * @return The number of errors in the clustering floorplanning. */ static unsigned check_clustering_floorplanning_consistency( - const ClusteredNetlist& clb_nlist, - const vtr::vector>& clb_atoms, - const vtr::vector& cluster_constraints, - const UserPlaceConstraints& constraints) { + const ClusteredNetlist& clb_nlist, + const vtr::vector>& clb_atoms, + const vtr::vector& cluster_constraints, + const UserPlaceConstraints& constraints) { unsigned num_errors = 0; // Check that each cluster has a constraint. if (cluster_constraints.size() != clb_nlist.blocks().size()) { @@ -435,10 +435,9 @@ unsigned verify_clustering(const ClusteredNetlist& clb_nlist, unsigned verify_clustering(const VprContext& ctx) { // Verify the clustering within the given context. return verify_clustering(ctx.clustering().clb_nlist, - ctx.atom().nlist, - ctx.atom().lookup, + ctx.atom().netlist(), + ctx.atom().lookup(), ctx.clustering().atoms_lookup, ctx.floorplanning().cluster_constraints, ctx.floorplanning().constraints); } - diff --git a/vpr/src/pack/verify_clustering.h b/vpr/src/pack/verify_clustering.h index f9ae0d95ed2..f13de9a6d48 100644 --- a/vpr/src/pack/verify_clustering.h +++ b/vpr/src/pack/verify_clustering.h @@ -82,4 +82,3 @@ unsigned verify_clustering(const ClusteredNetlist& clb_nlist, * log messages for each error found. */ unsigned verify_clustering(const VprContext& ctx); - diff --git a/vpr/src/pack/verify_flat_placement.cpp b/vpr/src/pack/verify_flat_placement.cpp new file mode 100644 index 00000000000..76a893d66a6 --- /dev/null +++ b/vpr/src/pack/verify_flat_placement.cpp @@ -0,0 +1,100 @@ + +#include "verify_flat_placement.h" +#include "flat_placement_types.h" +#include "atom_netlist.h" +#include "atom_netlist_fwd.h" +#include "prepack.h" +#include "vpr_types.h" +#include "vtr_log.h" + +unsigned verify_flat_placement_for_packing(const FlatPlacementInfo& flat_placement_info, + const AtomNetlist& atom_netlist, + const Prepacker& prepacker) { + unsigned num_errors = 0; + + // Quick check to ensure that the flat placement info has the correct size + // for each piece of information. + if (flat_placement_info.blk_x_pos.size() != atom_netlist.blocks().size() + || flat_placement_info.blk_y_pos.size() != atom_netlist.blocks().size() + || flat_placement_info.blk_layer.size() != atom_netlist.blocks().size() + || flat_placement_info.blk_sub_tile.size() != atom_netlist.blocks().size() + || flat_placement_info.blk_site_idx.size() != atom_netlist.blocks().size()) { + VTR_LOG_ERROR( + "The number of blocks in the flat placement does not match the " + "number of blocks in the atom netlist.\n"); + num_errors++; + // Return here since this error can cause issues below. + return num_errors; + } + + // 1. Verify that every atom has an (x, y, layer) position on the device. + // + // TODO: In the future, we may be able to allow some blocks to have + // undefined positions. + for (AtomBlockId blk_id : atom_netlist.blocks()) { + if (flat_placement_info.blk_x_pos[blk_id] == FlatPlacementInfo::UNDEFINED_POS + || flat_placement_info.blk_y_pos[blk_id] == FlatPlacementInfo::UNDEFINED_POS + || flat_placement_info.blk_layer[blk_id] == FlatPlacementInfo::UNDEFINED_POS) { + VTR_LOG_ERROR( + "Atom block %s has an undefined position in the flat placement.\n", + atom_netlist.block_name(blk_id).c_str()); + num_errors++; + } + } + + // 2. Verify that every atom block has non-negative position values. + // + // Since the device may not be sized yet, we cannot check if the positions + // are within the bounds of the device, but if any position value is + // negative (and is not undefined) we know that it is invalid. + for (AtomBlockId blk_id : atom_netlist.blocks()) { + float blk_x_pos = flat_placement_info.blk_x_pos[blk_id]; + float blk_y_pos = flat_placement_info.blk_y_pos[blk_id]; + float blk_layer = flat_placement_info.blk_layer[blk_id]; + int blk_sub_tile = flat_placement_info.blk_sub_tile[blk_id]; + int blk_site_idx = flat_placement_info.blk_site_idx[blk_id]; + if ((blk_x_pos < 0.f && blk_x_pos != FlatPlacementInfo::UNDEFINED_POS) + || (blk_y_pos < 0.f && blk_y_pos != FlatPlacementInfo::UNDEFINED_POS) + || (blk_layer < 0.f && blk_layer != FlatPlacementInfo::UNDEFINED_POS) + || (blk_sub_tile < 0 && blk_sub_tile != FlatPlacementInfo::UNDEFINED_SUB_TILE) + || (blk_site_idx < 0 && blk_site_idx != FlatPlacementInfo::UNDEFINED_SITE_IDX)) { + VTR_LOG_ERROR( + "Atom block %s is placed at an invalid position on the FPGA.\n", + atom_netlist.block_name(blk_id).c_str()); + num_errors++; + } + } + + // 3. Verify that every atom in each molecule has the same position. + // + // TODO: In the future, we can support if some of the atoms are undefined, + // but that can be fixed-up before calling this method. + for (PackMoleculeId mol_id : prepacker.molecules()) { + const t_pack_molecule& mol = prepacker.get_molecule(mol_id); + AtomBlockId root_blk_id = mol.atom_block_ids[mol.root]; + float root_pos_x = flat_placement_info.blk_x_pos[root_blk_id]; + float root_pos_y = flat_placement_info.blk_y_pos[root_blk_id]; + float root_layer = flat_placement_info.blk_layer[root_blk_id]; + int root_sub_tile = flat_placement_info.blk_sub_tile[root_blk_id]; + for (AtomBlockId mol_blk_id : mol.atom_block_ids) { + if (!mol_blk_id.is_valid()) + continue; + if (flat_placement_info.blk_x_pos[mol_blk_id] != root_pos_x || flat_placement_info.blk_y_pos[mol_blk_id] != root_pos_y || flat_placement_info.blk_layer[mol_blk_id] != root_layer || flat_placement_info.blk_sub_tile[mol_blk_id] != root_sub_tile) { + VTR_LOG_ERROR( + "Molecule with root atom block %s contains atom block %s " + "which is not at the same position as the root atom " + "block.\n", + atom_netlist.block_name(root_blk_id).c_str(), + atom_netlist.block_name(mol_blk_id).c_str()); + num_errors++; + } + } + } + + // TODO: May want to verify that the layer is all 0 in the case of 2D FPGAs. + + // TODO: Should verify that the fixed block constraints are observed. + // It is ill-formed for a flat placement to disagree with the constraints. + + return num_errors; +} diff --git a/vpr/src/pack/verify_flat_placement.h b/vpr/src/pack/verify_flat_placement.h new file mode 100644 index 00000000000..44bfb47f3fd --- /dev/null +++ b/vpr/src/pack/verify_flat_placement.h @@ -0,0 +1,37 @@ +/** + * @file + * @author Alex Singer + * @date January 2025 + * @brief Independent verify methods to check invariants on the flat + * placement that has been passed into the packer. This checks for + * invalid data so this does not have to be checked during packing. + */ + +#pragma once + +// Forward declarations +class FlatPlacementInfo; +class AtomNetlist; +class Prepacker; + +/** + * @brief Verify the flat placement for use in the packer. + * + * This method will check the following invariants: + * 1. Every atom has a defined x and y position. + * 2. Every atom has non-negative placement information values. + * 3. Every molecule has atoms that have the same placement information. + * + * This method will log error messages for each issue it finds and will return + * a count of the number of errors. + * + * @param flat_placement_info + * The flat placement to verify. + * @param atom_netlist + * The netlist of atoms in the circuits. + * @param prepacker + * The prepacker object used to prepack the atoms into molecules. + */ +unsigned verify_flat_placement_for_packing(const FlatPlacementInfo& flat_placement_info, + const AtomNetlist& atom_netlist, + const Prepacker& prepacker); diff --git a/vpr/src/place/RL_agent_util.cpp b/vpr/src/place/RL_agent_util.cpp index b33e05f077a..54ca3601545 100644 --- a/vpr/src/place/RL_agent_util.cpp +++ b/vpr/src/place/RL_agent_util.cpp @@ -1,8 +1,13 @@ #include "RL_agent_util.h" + +#include "place_macro.h" +#include "simpleRL_move_generator.h" #include "static_move_generator.h" -#include "manual_move_generator.h" +#include "placer_state.h" std::pair, std::unique_ptr> create_move_generators(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, const t_placer_opts& placer_opts, int move_lim, double noc_attraction_weight, @@ -10,7 +15,6 @@ std::pair, std::unique_ptr> create e_reward_function reward_fun = string_to_reward(placer_opts.place_reward_fun); std::pair, std::unique_ptr> move_generators; - if (!placer_opts.RL_agent_placement) { // RL agent is disabled auto move_types = placer_opts.place_static_move_prob; move_types.resize((int)e_move_type::NUMBER_OF_AUTO_MOVES, 0.0f); @@ -22,8 +26,8 @@ std::pair, std::unique_ptr> create move_name.c_str(), placer_opts.place_static_move_prob[move_type]); } - move_generators.first = std::make_unique(placer_state, reward_fun, rng, placer_opts.place_static_move_prob); - move_generators.second = std::make_unique(placer_state, reward_fun, rng, placer_opts.place_static_move_prob); + move_generators.first = std::make_unique(placer_state, place_macros, net_cost_handler, reward_fun, rng, placer_opts.place_static_move_prob); + move_generators.second = std::make_unique(placer_state, place_macros, net_cost_handler, reward_fun, rng, placer_opts.place_static_move_prob); } else { //RL based placement /* For the non timing driven placement: the agent has a single state * * - Available moves are (Uniform / Median / Centroid) * @@ -60,6 +64,13 @@ std::pair, std::unique_ptr> create second_state_avail_moves.push_back(e_move_type::NOC_ATTRACTION_CENTROID); } + std::vector num_movable_blocks_per_type; + std::ranges::transform(placer_state.blk_loc_registry().movable_blocks_per_type(), + std::back_inserter(num_movable_blocks_per_type), + [](const auto& innerVec) noexcept { + return innerVec.size(); + }); + if (placer_opts.place_agent_algorithm == e_agent_algorithm::E_GREEDY) { std::unique_ptr karmed_bandit_agent1, karmed_bandit_agent2; //agent's 1st state @@ -68,16 +79,20 @@ std::pair, std::unique_ptr> create karmed_bandit_agent1 = std::make_unique(first_state_avail_moves, e_agent_space::MOVE_BLOCK_TYPE, placer_opts.place_agent_epsilon, - rng); + rng, + num_movable_blocks_per_type); } else { VTR_LOG("Using simple RL 'Epsilon Greedy agent' for choosing move types\n"); karmed_bandit_agent1 = std::make_unique(first_state_avail_moves, e_agent_space::MOVE_TYPE, placer_opts.place_agent_epsilon, - rng); + rng, + num_movable_blocks_per_type); } karmed_bandit_agent1->set_step(placer_opts.place_agent_gamma, move_lim); move_generators.first = std::make_unique(placer_state, + place_macros, + net_cost_handler, reward_fun, rng, karmed_bandit_agent1, @@ -87,9 +102,12 @@ std::pair, std::unique_ptr> create karmed_bandit_agent2 = std::make_unique(second_state_avail_moves, e_agent_space::MOVE_TYPE, placer_opts.place_agent_epsilon, - rng); + rng, + num_movable_blocks_per_type); karmed_bandit_agent2->set_step(placer_opts.place_agent_gamma, move_lim); move_generators.second = std::make_unique(placer_state, + place_macros, + net_cost_handler, reward_fun, rng, karmed_bandit_agent2, @@ -102,15 +120,19 @@ std::pair, std::unique_ptr> create VTR_LOG("Using simple RL 'Softmax agent' for choosing move and block types\n"); karmed_bandit_agent1 = std::make_unique(first_state_avail_moves, e_agent_space::MOVE_BLOCK_TYPE, - rng); + rng, + num_movable_blocks_per_type); } else { VTR_LOG("Using simple RL 'Softmax agent' for choosing move types\n"); karmed_bandit_agent1 = std::make_unique(first_state_avail_moves, e_agent_space::MOVE_TYPE, - rng); + rng, + num_movable_blocks_per_type); } karmed_bandit_agent1->set_step(placer_opts.place_agent_gamma, move_lim); move_generators.first = std::make_unique(placer_state, + place_macros, + net_cost_handler, reward_fun, rng, karmed_bandit_agent1, @@ -119,9 +141,12 @@ std::pair, std::unique_ptr> create //agent's 2nd state karmed_bandit_agent2 = std::make_unique(second_state_avail_moves, e_agent_space::MOVE_TYPE, - rng); + rng, + num_movable_blocks_per_type); karmed_bandit_agent2->set_step(placer_opts.place_agent_gamma, move_lim); move_generators.second = std::make_unique(placer_state, + place_macros, + net_cost_handler, reward_fun, rng, karmed_bandit_agent2, @@ -149,4 +174,4 @@ MoveGenerator& select_move_generator(std::unique_ptr& move_genera else return *move_generator2; } -} \ No newline at end of file +} diff --git a/vpr/src/place/RL_agent_util.h b/vpr/src/place/RL_agent_util.h index 0ec801e8000..511cd73d0d6 100644 --- a/vpr/src/place/RL_agent_util.h +++ b/vpr/src/place/RL_agent_util.h @@ -3,6 +3,8 @@ #include "move_generator.h" +class PlaceMacros; + //enum represents the available agent states enum class e_agent_state { EARLY_IN_THE_ANNEAL, @@ -27,6 +29,8 @@ enum class e_agent_state { * */ std::pair, std::unique_ptr> create_move_generators(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, const t_placer_opts& placer_opts, int move_lim, double noc_attraction_weight, diff --git a/vpr/src/place/analytic_placer.cpp b/vpr/src/place/analytic_placer.cpp index b4ac4400f0f..a0897af6785 100644 --- a/vpr/src/place/analytic_placer.cpp +++ b/vpr/src/place/analytic_placer.cpp @@ -1,29 +1,30 @@ +#include "place_macro.h" #ifdef ENABLE_ANALYTIC_PLACE -# include "analytic_placer.h" +#include "analytic_placer.h" // The eigen library contains a warning in GCC13 for a null dereference. This // causes the CI build to fail due to the warning. Ignoring the warning for // these include files. Using push to return to the state of GCC diagnostics. #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wnull-dereference" -# include -# include +#include +#include // Pop the GCC diagnostics state back to what it was before. #pragma GCC diagnostic pop -# include -# include -# include +#include +#include +#include -# include "vpr_types.h" -# include "vtr_time.h" -# include "read_place.h" -# include "globals.h" -# include "vtr_log.h" -# include "cut_spreader.h" -# include "vpr_utils.h" -# include "place_util.h" +#include "vpr_types.h" +#include "vtr_time.h" +#include "read_place.h" +#include "globals.h" +#include "vtr_log.h" +#include "cut_spreader.h" +#include "vpr_utils.h" +#include "place_util.h" // Templated struct for constructing and solving matrix equations in analytic placer template @@ -122,8 +123,10 @@ constexpr int HEAP_STALLED_ITERATIONS_STOP = 15; * Placement & device info is accessed via g_vpr_ctx */ -AnalyticPlacer::AnalyticPlacer(BlkLocRegistry& blk_loc_registry) - : blk_loc_registry_ref_(blk_loc_registry) { +AnalyticPlacer::AnalyticPlacer(BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) + : blk_loc_registry_ref_(blk_loc_registry) + , place_macros_(place_macros) { //Eigen::initParallel(); // TODO: PlacerHeapCfg should be externally configured & supplied @@ -297,12 +300,11 @@ void AnalyticPlacer::build_legal_locations() { void AnalyticPlacer::init() { const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; auto& init_block_locs = blk_loc_registry_ref_.block_locs(); - auto& place_macros = blk_loc_registry_ref_.place_macros(); for (auto blk_id : clb_nlist.blocks()) { blk_locs.insert(blk_id, BlockLocation{}); blk_locs[blk_id].loc = init_block_locs[blk_id].loc; // transfer of initial placement - row_num.insert(blk_id, DONT_SOLVE); // no blocks are moved by default, until they are setup in setup_solve_blks() + row_num.insert(blk_id, DONT_SOLVE); // no blocks are moved by default, until they are setup in setup_solve_blks() } // only blocks with connections are considered @@ -319,7 +321,7 @@ void AnalyticPlacer::init() { if (!init_block_locs[blk_id].is_fixed && has_connections(blk_id)) // not fixed and has connections // matrix equation is formulated based on connections, so requires at least one connection - if (place_macros.get_imacro_from_iblk(blk_id) == NO_MACRO || place_macros.macro_head(blk_id) == blk_id) { + if (place_macros_.get_imacro_from_iblk(blk_id) == NO_MACRO || place_macros_.macro_head(blk_id) == blk_id) { // not in macro or head of macro // for macro, only the head (base) block of the macro is a free variable, the location of other macro // blocks can be calculated using offset of the head. They are not free variables in the equation system @@ -379,7 +381,6 @@ int AnalyticPlacer::total_hpwl() { */ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = blk_loc_registry_ref_.place_macros(); int row = 0; solve_blks.clear(); @@ -395,9 +396,9 @@ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { } } // update row_num of macro members - for (auto& macro : blk_loc_registry_ref_.place_macros().macros()) { + for (auto& macro : place_macros_.macros()) { for (auto& member : macro.members) { - row_num[member.blk_index] = row_num[place_macros.macro_head(member.blk_index)]; + row_num[member.blk_index] = row_num[place_macros_.macro_head(member.blk_index)]; } } } @@ -408,7 +409,7 @@ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { * when formulating the matrix equations), an update for members is necessary */ void AnalyticPlacer::update_macros() { - for (auto& macro : blk_loc_registry_ref_.place_macros().macros()) { + for (auto& macro : place_macros_.macros()) { ClusterBlockId head_id = macro.members[0].blk_index; bool mac_can_be_placed = macro_can_be_placed(macro, blk_locs[head_id].loc, true, blk_loc_registry_ref_); @@ -471,8 +472,6 @@ void AnalyticPlacer::stamp_weight_on_matrix(EquationSystem& es, ClusterBlockId var, ClusterBlockId eqn, double weight) { - const auto& place_macros = blk_loc_registry_ref_.place_macros(); - // Return the x or y position of a block auto blk_p = [&](ClusterBlockId blk_id) { return dir ? blk_locs[blk_id].loc.y : blk_locs[blk_id].loc.x; }; @@ -486,8 +485,8 @@ void AnalyticPlacer::stamp_weight_on_matrix(EquationSystem& es, } else { // var is not movable, stamp weight on rhs vector es.add_rhs(eqn_row, -v_pos * weight); } - if (place_macros.get_imacro_from_iblk(var) != NO_MACRO) { // var is part of a macro, stamp on rhs vector - auto& members = place_macros[place_macros.get_imacro_from_iblk(var)].members; + if (place_macros_.get_imacro_from_iblk(var) != NO_MACRO) { // var is part of a macro, stamp on rhs vector + auto& members = place_macros_[place_macros_.get_imacro_from_iblk(var)].members; for (auto& member : members) { // go through macro members to find the right member block if (member.blk_index == var) es.add_rhs(eqn_row, -(dir ? member.offset.y : member.offset.x) * weight); diff --git a/vpr/src/place/analytic_placer.h b/vpr/src/place/analytic_placer.h index b73b3486f57..86e31481858 100644 --- a/vpr/src/place/analytic_placer.h +++ b/vpr/src/place/analytic_placer.h @@ -82,9 +82,10 @@ * https://github.com/YosysHQ/nextpnr */ -# include "vpr_context.h" -# include "timing_place.h" -# include "PlacementDelayCalculator.h" +#include "vpr_context.h" +#include "PlacementDelayCalculator.h" + +class PlaceMacros; /* * @brief Templated struct for constructing and solving matrix equations in analytic placer @@ -99,7 +100,6 @@ extern int DONT_SOLVE; // sentinel for blks not part of a placement macro extern int NO_MACRO; - class AnalyticPlacer { public: /* @@ -107,7 +107,7 @@ class AnalyticPlacer { * To tune these parameters, change directly in constructor */ AnalyticPlacer() = delete; - explicit AnalyticPlacer(BlkLocRegistry& blk_loc_registry); + explicit AnalyticPlacer(BlkLocRegistry& blk_loc_registry, const PlaceMacros& place_macros); /* * @brief main function of analytic placement @@ -168,6 +168,9 @@ class AnalyticPlacer { // reference to the placement location variables BlkLocRegistry& blk_loc_registry_ref_; + // Reference to the placement macros. + const PlaceMacros& place_macros_; + /* * The set of blks of different types to be placed by AnalyticPlacement process, * i.e. the free variable blocks. diff --git a/vpr/src/place/annealer.cpp b/vpr/src/place/annealer.cpp index b18f60b27bd..949dfe5b4c1 100644 --- a/vpr/src/place/annealer.cpp +++ b/vpr/src/place/annealer.cpp @@ -6,6 +6,7 @@ #include "globals.h" #include "draw_global.h" +#include "place_macro.h" #include "vpr_types.h" #include "place_util.h" #include "placer_state.h" @@ -16,6 +17,8 @@ #include "read_place.h" #include "placer_breakpoint.h" #include "RL_agent_util.h" +#include "PlacerSetupSlacks.h" +#include "PlacerCriticalities.h" /**************************************************************************/ /*************** Static Function Declarations *****************************/ @@ -135,7 +138,6 @@ bool t_annealing_state::outer_loop_update(float success_rate, auto& cluster_ctx = g_vpr_ctx.clustering(); float t_exit = 0.005 * costs.cost / cluster_ctx.clb_nlist.nets().size(); - VTR_ASSERT_SAFE(placer_opts.anneal_sched.type == e_sched_type::AUTO_SCHED); // Automatically adjust alpha according to success rate. if (success_rate > 0.96) { @@ -187,6 +189,7 @@ void t_annealing_state::update_crit_exponent(const t_placer_opts& placer_opts) { PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, PlacerState& placer_state, + const PlaceMacros& place_macros, t_placer_costs& costs, NetCostHandler& net_cost_handler, std::optional& noc_cost_handler, @@ -202,6 +205,7 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, int move_lim) : placer_opts_(placer_opts) , placer_state_(placer_state) + , place_macros_(place_macros) , costs_(costs) , net_cost_handler_(net_cost_handler) , noc_cost_handler_(noc_cost_handler) @@ -209,7 +213,7 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, , rng_(rng) , move_generator_1_(std::move(move_generator_1)) , move_generator_2_(std::move(move_generator_2)) - , manual_move_generator_(placer_state, rng) + , manual_move_generator_(placer_state, place_macros, net_cost_handler, rng) , agent_state_(e_agent_state::EARLY_IN_THE_ANNEAL) , delay_model_(delay_model) , criticalities_(criticalities) @@ -219,8 +223,7 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, , move_stats_file_(nullptr, vtr::fclose) , outer_crit_iter_count_(1) , blocks_affected_(placer_state.block_locs().size()) - , quench_started_(false) -{ + , quench_started_(false) { const auto& device_ctx = g_vpr_ctx.device(); float first_crit_exponent; @@ -230,7 +233,9 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, first_crit_exponent = 0.f; } - int first_move_lim = get_initial_move_lim(placer_opts, placer_opts_.anneal_sched); + int first_move_lim = get_place_inner_loop_num_move(placer_opts, placer_opts_.anneal_sched); + + VTR_LOG("Moves per temperature: %d\n", first_move_lim); if (placer_opts.inner_loop_recompute_divider != 0) { inner_recompute_limit_ = static_cast(0.5 + (float)first_move_lim / (float)placer_opts.inner_loop_recompute_divider); @@ -252,10 +257,14 @@ PlacementAnnealer::PlacementAnnealer(const t_placer_opts& placer_opts, tot_iter_ = 0; // Get the first range limiter - placer_state_.mutable_move().first_rlim = (float)std::max(device_ctx.grid.width() - 1, device_ctx.grid.height() - 1); - - annealing_state_ = t_annealing_state(EPSILON, // Set the temperature low to ensure that initial placement quality will be preserved - placer_state_.move().first_rlim, + MoveGenerator::first_rlim = (float)std::max(device_ctx.grid.width() - 1, device_ctx.grid.height() - 1); + + // In automatic schedule we do a number of random moves before starting the main annealer + // to get an estimate for the initial temperature. We set this temperature low + // to ensure that initial placement quality will be preserved + constexpr float pre_annealing_temp = 1.e-15f; + annealing_state_ = t_annealing_state(pre_annealing_temp, + MoveGenerator::first_rlim, first_move_lim, first_crit_exponent); @@ -364,7 +373,6 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, double bb_delta_c = 0; //Change in the bounding box (wiring) cost. double timing_delta_c = 0; //Change in the timing cost (delay * criticality). - /* Allow some fraction of moves to not be restricted by rlim, * in the hopes of better escaping local minima. */ float rlim; @@ -386,12 +394,12 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, if (manual_move_enabled) { #ifndef NO_GRAPHICS create_move_outcome = manual_move_display_and_propose(manual_move_generator_, blocks_affected_, - proposed_action.move_type, rlim, placer_opts_, - criticalities_); + proposed_action.move_type, rlim, + placer_opts_, criticalities_); #endif //NO_GRAPHICS } else if (router_block_move) { // generate a move where two random router blocks are swapped - create_move_outcome = propose_router_swap(blocks_affected_, rlim, blk_loc_registry, rng_); + create_move_outcome = propose_router_swap(blocks_affected_, rlim, blk_loc_registry, place_macros_, rng_); proposed_action.move_type = e_move_type::UNIFORM; } else { //Generate a new move (perturbation) used to explore the space of possible placements @@ -488,7 +496,7 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, criticalities_->disable_update(); setup_slacks_->enable_update(); update_timing_classes(crit_params, timing_info_, criticalities_, - setup_slacks_, pin_timing_invalidator_, placer_state_); + setup_slacks_, pin_timing_invalidator_); /* Get the setup slack analysis cost */ //TODO: calculate a weighted average of the slack cost and wiring cost @@ -553,7 +561,7 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, // Update clb data structures since we kept the move. blk_loc_registry.commit_move_blocks(blocks_affected_); - if (noc_opts_.noc){ + if (noc_opts_.noc) { noc_cost_handler_->commit_noc_costs(); costs_ += noc_delta_c; } @@ -592,7 +600,7 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, // Revert the timing update update_timing_classes(crit_params, timing_info_, criticalities_, - setup_slacks_, pin_timing_invalidator_, placer_state_); + setup_slacks_, pin_timing_invalidator_); VTR_ASSERT_SAFE_MSG( verify_connection_setup_slacks(setup_slacks_, placer_state_), @@ -632,7 +640,6 @@ e_move_result PlacementAnnealer::try_swap_(MoveGenerator& move_generator, stop_placement_and_check_breakpoints(blocks_affected_, move_outcome, delta_c, bb_delta_c, timing_delta_c); #endif - // Clear the data structure containing block move info blocks_affected_.clear_move_blocks(); @@ -646,8 +653,7 @@ void PlacementAnnealer::outer_loop_update_timing_info() { if (placer_opts_.place_algorithm.is_timing_driven()) { /* At each temperature change we update these values to be used * for normalizing the tradeoff between timing and wirelength (bb) */ - if (outer_crit_iter_count_ >= placer_opts_.recompute_crit_iter || - placer_opts_.inner_loop_recompute_divider != 0) { + if (outer_crit_iter_count_ >= placer_opts_.recompute_crit_iter || placer_opts_.inner_loop_recompute_divider != 0) { PlaceCritParams crit_params{annealing_state_.crit_exponent, placer_opts_.place_crit_limit}; @@ -746,9 +752,7 @@ void PlacementAnnealer::placement_inner_loop() { // update the RL agent's state if (!quench_started_) { - if (placer_opts_.place_algorithm.is_timing_driven() && - placer_opts_.place_agent_multistate && - agent_state_ == e_agent_state::EARLY_IN_THE_ANNEAL) { + if (placer_opts_.place_algorithm.is_timing_driven() && placer_opts_.place_agent_multistate && agent_state_ == e_agent_state::EARLY_IN_THE_ANNEAL) { if (annealing_state_.alpha < 0.85 && annealing_state_.alpha > 0.6) { agent_state_ = e_agent_state::LATE_IN_THE_ANNEAL; VTR_LOG("Agent's 2nd state: \n"); @@ -760,7 +764,6 @@ void PlacementAnnealer::placement_inner_loop() { ++annealing_state_.num_temps; } - int PlacementAnnealer::get_total_iteration() const { return tot_iter_; } @@ -842,8 +845,7 @@ void PlacementAnnealer::LOG_MOVE_STATS_PROPOSED() { } } -void PlacementAnnealer::LOG_MOVE_STATS_OUTCOME(double delta_cost, double delta_bb_cost, double delta_td_cost, - const char* outcome, const char* reason) { +void PlacementAnnealer::LOG_MOVE_STATS_OUTCOME(double delta_cost, double delta_bb_cost, double delta_td_cost, const char* outcome, const char* reason) { if (move_stats_file_) { fprintf(move_stats_file_.get(), "%g,%g,%g," diff --git a/vpr/src/place/annealer.h b/vpr/src/place/annealer.h index fd9b0dbd928..66abceea1e3 100644 --- a/vpr/src/place/annealer.h +++ b/vpr/src/place/annealer.h @@ -10,6 +10,7 @@ #include #include +class PlaceMacros; class PlacerState; class t_placer_costs; struct t_placer_opts; @@ -17,6 +18,7 @@ enum class e_agent_state; class NocCostHandler; class NetPinTimingInvalidator; +class PlacerSetupSlacks; /** * These variables keep track of the number of swaps @@ -170,6 +172,7 @@ class PlacementAnnealer { public: PlacementAnnealer(const t_placer_opts& placer_opts, PlacerState& placer_state, + const PlaceMacros& place_macros, t_placer_costs& costs, NetCostHandler& net_cost_handler, std::optional& noc_cost_handler, @@ -230,7 +233,6 @@ class PlacementAnnealer { const MoveAbortionLogger& get_move_abortion_logger() const; private: - /** * @brief Pick some block and moves it to another spot. * @@ -268,6 +270,7 @@ class PlacementAnnealer { private: const t_placer_opts& placer_opts_; PlacerState& placer_state_; + const PlaceMacros& place_macros_; /// Stores different placement cost terms t_placer_costs& costs_; /// Computes bounding box for each cluster net @@ -327,8 +330,7 @@ class PlacementAnnealer { void LOG_MOVE_STATS_HEADER(); void LOG_MOVE_STATS_PROPOSED(); - void LOG_MOVE_STATS_OUTCOME(double delta_cost, double delta_bb_cost, double delta_td_cost, - const char* outcome, const char* reason); + void LOG_MOVE_STATS_OUTCOME(double delta_cost, double delta_bb_cost, double delta_td_cost, const char* outcome, const char* reason); /** * @brief Defines the RL agent's reward function factor constant. This factor controls the weight of bb cost @@ -336,4 +338,4 @@ class PlacementAnnealer { * -1*(1.5-REWARD_BB_TIMING_RELATIVE_WEIGHT)*timing_cost + (1+REWARD_BB_TIMING_RELATIVE_WEIGHT)*bb_cost) */ static constexpr float REWARD_BB_TIMING_RELATIVE_WEIGHT = 0.4; -}; \ No newline at end of file +}; diff --git a/vpr/src/place/compressed_grid.cpp b/vpr/src/place/compressed_grid.cpp index 33fa04cbfc1..ce081acb16f 100644 --- a/vpr/src/place/compressed_grid.cpp +++ b/vpr/src/place/compressed_grid.cpp @@ -3,6 +3,7 @@ #include "arch_util.h" #include "globals.h" +#include "physical_types_util.h" #include "vtr_time.h" /** @@ -17,7 +18,6 @@ static t_compressed_block_grid create_compressed_block_grid(const std::vector>>& locations, int num_layers); - std::vector create_compressed_block_grids() { /* Measure how long it takes to allocate and initialize compressed grid. * The measured execution time is printed when this object goes out of scope @@ -43,7 +43,7 @@ std::vector create_compressed_block_grids() { int width_offset = grid.get_width_offset({x, y, layer_num}); int height_offset = grid.get_height_offset(t_physical_tile_loc(x, y, layer_num)); - if (width_offset == 0 && height_offset == 0) { // the bottom left corner of a tile + if (width_offset == 0 && height_offset == 0) { // the bottom left corner of a tile const auto& type = grid.get_physical_type({x, y, layer_num}); auto equivalent_sites = get_equivalent_sites_set(type); diff --git a/vpr/src/place/compressed_grid.h b/vpr/src/place/compressed_grid.h index c9030a39376..6f9575fb670 100644 --- a/vpr/src/place/compressed_grid.h +++ b/vpr/src/place/compressed_grid.h @@ -1,8 +1,10 @@ #ifndef VPR_COMPRESSED_GRID_H #define VPR_COMPRESSED_GRID_H +#include #include "physical_types.h" +#include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_flat_map.h" @@ -60,18 +62,22 @@ struct t_compressed_block_grid { * * This function takes a physical tile location in the grid and converts it to the corresponding * compressed location. The conversion approximates by rounding up to the nearest valid compressed location. + * If all the compressed locations are less than the grid location, the function will return the last compressed location. * * @param grid_loc The physical tile location in the grid. * @return The corresponding compressed location with the same layer number. */ inline t_physical_tile_loc grid_loc_to_compressed_loc_approx_round_up(t_physical_tile_loc grid_loc) const { auto find_compressed_index = [](const std::vector& compressed, int value) -> int { - auto itr = std::upper_bound(compressed.begin(), compressed.end(), value); - if (itr == compressed.begin()) - return 0; - if (itr == compressed.end() || *(itr - 1) == value) - return (int)std::distance(compressed.begin(), itr - 1); - return (int)std::distance(compressed.begin(), itr); + // Get the first element that is not less than the value + auto itr = std::lower_bound(compressed.begin(), compressed.end(), value); + if (itr == compressed.end()) { + // If all the compressed locations are less than the grid location, return the last compressed location + return compressed.size() - 1; + } else { + // Return the index of the first element that is not less than the value + return std::distance(compressed.begin(), itr); + } }; int layer_num = grid_loc.layer_num; @@ -86,17 +92,22 @@ struct t_compressed_block_grid { * * This function takes a physical tile location in the grid and converts it to the corresponding * compressed location. The conversion approximates by rounding down to the nearest valid compressed location. + * If all the compressed locations are bigger than the grid location, the function will return the first compressed location. * * @param grid_loc The physical tile location in the grid. * @return The corresponding compressed location with the same layer number. */ inline t_physical_tile_loc grid_loc_to_compressed_loc_approx_round_down(t_physical_tile_loc grid_loc) const { auto find_compressed_index = [](const std::vector& compressed, int value) -> int { - auto itr = std::lower_bound(compressed.begin(), compressed.end(), value); - if (itr == compressed.end()) { - return (int)std::distance(compressed.begin(), itr - 1); + // Get the first element that is strictly bigger than the value + auto itr = std::upper_bound(compressed.begin(), compressed.end(), value); + if (itr == compressed.begin()) { + // If all the compressed locations are bigger than the grid location, return the first compressed location + return 0; + } else { + // Return the index of the first element that is less than or equal to the value + return std::distance(compressed.begin(), itr - 1); } - return (int)std::distance(compressed.begin(), itr); }; int layer_num = grid_loc.layer_num; @@ -111,31 +122,29 @@ struct t_compressed_block_grid { * * Useful when the point is of a different block type from coords. * - * @param point represents a coordinate in one dimension of the point - * @param coords represents vector of coordinate values of a single type only - * - * Hence, the exact point coordinate will not be found in coords if they are of different block types. In this case the function will return - * the nearest compressed location to point by rounding it down + * @param grid_loc non-compressed physical tile location in the grid + * @return Nearest x and y compressed locations in the grid (in the same layer) */ inline t_physical_tile_loc grid_loc_to_compressed_loc_approx(t_physical_tile_loc grid_loc) const { auto find_closest_compressed_point = [](int loc, const std::vector& compressed_grid_dim) -> int { + VTR_ASSERT_DEBUG(compressed_grid_dim.size() > 0); + + // Find the first element not less than loc auto itr = std::lower_bound(compressed_grid_dim.begin(), compressed_grid_dim.end(), loc); - int cx; - if (itr < compressed_grid_dim.end() - 1) { - int dist_prev = abs(loc - *itr); - int dist_next = abs(loc - *(itr+1)); - if (dist_prev < dist_next) { - cx = std::distance(compressed_grid_dim.begin(), itr); - } else { - cx = std::distance(compressed_grid_dim.begin(), itr + 1); - } + + if (itr == compressed_grid_dim.begin()) { + // If all the compressed locations are bigger that or equal to loc, return the first compressed location + return 0; } else if (itr == compressed_grid_dim.end()) { - cx = std::distance(compressed_grid_dim.begin(), itr - 1); + // If all the compressed locations are less than loc, return the last compressed location + return compressed_grid_dim.size() - 1; } else { - cx = std::distance(compressed_grid_dim.begin(), itr); + // Find the nearest compressed location. + int dist_prev = loc - *(itr - 1); + int dist_next = *itr - loc; + VTR_ASSERT_DEBUG(dist_prev >= 0 && dist_next >= 0); + return (dist_prev <= dist_next) ? (std::distance(compressed_grid_dim.begin(), itr - 1)) : (std::distance(compressed_grid_dim.begin(), itr)); } - - return cx; }; const int layer_num = grid_loc.layer_num; diff --git a/vpr/src/place/cut_spreader.cpp b/vpr/src/place/cut_spreader.cpp index c9c969b1abd..9dfe17f83c6 100644 --- a/vpr/src/place/cut_spreader.cpp +++ b/vpr/src/place/cut_spreader.cpp @@ -1,18 +1,19 @@ +#include "place_macro.h" #ifdef ENABLE_ANALYTIC_PLACE -# include "cut_spreader.h" -# include -# include -# include -# include +#include "cut_spreader.h" +#include +#include +#include +#include -# include "analytic_placer.h" -# include "vpr_types.h" -# include "vtr_time.h" -# include "globals.h" -# include "vtr_log.h" -# include "place_util.h" -# include "grid_block.h" +#include "analytic_placer.h" +#include "vpr_types.h" +#include "vtr_time.h" +#include "globals.h" +#include "vtr_log.h" +#include "place_util.h" +#include "grid_block.h" // sentinel for base case in CutSpreader (i.e. only 1 block left in region) constexpr std::pair BASE_CASE = {-2, -2}; @@ -112,7 +113,7 @@ void CutSpreader::cutSpread() { // setup CutSpreader data structures using information from AnalyticPlacer void CutSpreader::init() { const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; size_t max_x = g_vpr_ctx.device().grid.width(); size_t max_y = g_vpr_ctx.device().grid.height(); @@ -407,7 +408,7 @@ void CutSpreader::expand_regions() { std::pair CutSpreader::cut_region(SpreaderRegion& r, bool dir) { const DeviceContext& device_ctx = g_vpr_ctx.device(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; // TODO: CutSpreader is not compatible with 3D FPGA VTR_ASSERT(device_ctx.grid.get_num_layers() == 1); @@ -619,7 +620,7 @@ int CutSpreader::initial_source_cut(SpreaderRegion& r, bool dir, int& clearance_l, int& clearance_r) { - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; // pivot is the midpoint of cut_blks in terms of total block size (counting macro members) // this ensures the initial partitions have similar number of blocks @@ -672,7 +673,7 @@ int CutSpreader::initial_target_cut(SpreaderRegion& r, int& right_blks_n, int& left_tiles_n, int& right_tiles_n) { - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; // To achieve smallest difference in utilization, first move all tiles to right partition left_blks_n = 0, right_blks_n = 0; @@ -808,7 +809,7 @@ void CutSpreader::linear_spread_subarea(std::vector& cut_blks, void CutSpreader::strict_legalize() { auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; const auto& block_locs = ap->blk_loc_registry_ref_.block_locs(); - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; int max_x = g_vpr_ctx.device().grid.width(); int max_y = g_vpr_ctx.device().grid.height(); @@ -1035,14 +1036,14 @@ bool CutSpreader::try_place_blk(ClusterBlockId blk, std::priority_queue>& remaining) { const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; // iteration at current radius has exceeded exploration limit, and a candidate sub_tile (best_subtile) is found // then blk is placed in best_subtile if (exceeds_explore_limit && best_subtile != t_pl_loc{}) { // find the logic block bound to (placed on) best_subtile ClusterBlockId bound_blk = grid_blocks.block_at_location(best_subtile); - if (bound_blk) { // if best_subtile has a logic block + if (bound_blk) { // if best_subtile has a logic block unbind_tile(best_subtile); // clear bound_block and best_subtile's placement info remaining.emplace(1, bound_blk); // put bound_blk back into remaining blocks to place } @@ -1051,7 +1052,7 @@ bool CutSpreader::try_place_blk(ClusterBlockId blk, } // if exploration limit is not met or a candidate sub_tile is not found yet - for (auto sub_t : subtiles_at_location[nx][ny]) { // for each available sub_tile at random location + for (auto sub_t : subtiles_at_location[nx][ny]) { // for each available sub_tile at random location ClusterBlockId bound_blk = grid_blocks.block_at_location(sub_t); // logic blk at [nx, ny] if (bound_blk == ClusterBlockId::INVALID() || ripup_radius_met @@ -1112,7 +1113,7 @@ bool CutSpreader::try_place_macro(ClusterBlockId blk, int nx, int ny, std::priority_queue>& remaining) { - const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); + const auto& place_macros = ap->place_macros_; const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; diff --git a/vpr/src/place/cut_spreader.h b/vpr/src/place/cut_spreader.h index 472cd9cc722..5be5f0ed79d 100644 --- a/vpr/src/place/cut_spreader.h +++ b/vpr/src/place/cut_spreader.h @@ -107,8 +107,8 @@ * https://github.com/YosysHQ/nextpnr * */ -# include "vpr_context.h" -# include +#include "vpr_context.h" +#include // declaration of used types; class AnalyticPlacer; diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp new file mode 100644 index 00000000000..e58cb4b9539 --- /dev/null +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.cpp @@ -0,0 +1,80 @@ + + +#include "PlacementDelayModelCreator.h" + +#include "place_delay_model.h" +#include "simple_delay_model.h" +#include "delta_delay_model.h" +#include "override_delay_model.h" + +#include "vtr_time.h" +#include "physical_types.h" +#include "place_and_route.h" + +static int get_longest_segment_length(std::vector& segment_inf) { + int length = 0; + + for (const t_segment_inf& seg_info : segment_inf) { + if (seg_info.length > length) { + length = seg_info.length; + } + } + + return length; +} + +std::unique_ptr +PlacementDelayModelCreator::create_delay_model(const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + const Netlist<>& net_list, + t_det_routing_arch* det_routing_arch, + std::vector& segment_inf, + t_chan_width_dist chan_width_dist, + const std::vector& directs, + bool is_flat) { + vtr::ScopedStartFinishTimer timer("Computing placement delta delay look-up"); + + t_chan_width chan_width = setup_chan_width(router_opts, chan_width_dist); + + alloc_routing_structs(chan_width, router_opts, det_routing_arch, segment_inf, directs, is_flat); + + const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, + router_opts.lookahead_type, + router_opts.write_router_lookahead, + router_opts.read_router_lookahead, + segment_inf, + is_flat); + + RouterDelayProfiler route_profiler(net_list, router_lookahead, is_flat); + + int longest_length = get_longest_segment_length(segment_inf); + + // now setup and compute the actual arrays + std::unique_ptr place_delay_model; + float min_cross_layer_delay = get_min_cross_layer_delay(); + + if (placer_opts.delay_model_type == PlaceDelayModelType::SIMPLE) { + place_delay_model = std::make_unique(); + } else if (placer_opts.delay_model_type == PlaceDelayModelType::DELTA) { + place_delay_model = std::make_unique(min_cross_layer_delay, is_flat); + } else if (placer_opts.delay_model_type == PlaceDelayModelType::DELTA_OVERRIDE) { + place_delay_model = std::make_unique(min_cross_layer_delay, is_flat); + } else { + VTR_ASSERT_MSG(false, "Invalid placer delay model"); + } + + if (placer_opts.read_placement_delay_lookup.empty()) { + place_delay_model->compute(route_profiler, placer_opts, router_opts, longest_length); + } else { + place_delay_model->read(placer_opts.read_placement_delay_lookup); + } + + if (!placer_opts.write_placement_delay_lookup.empty()) { + place_delay_model->write(placer_opts.write_placement_delay_lookup); + } + + // free all data structures that are no longer needed + free_routing_structs(); + + return place_delay_model; +} diff --git a/vpr/src/place/delay_model/PlacementDelayModelCreator.h b/vpr/src/place/delay_model/PlacementDelayModelCreator.h new file mode 100644 index 00000000000..c92b67d4854 --- /dev/null +++ b/vpr/src/place/delay_model/PlacementDelayModelCreator.h @@ -0,0 +1,30 @@ + +#pragma once + +#include +#include + +#include "netlist.h" + +class PlaceDelayModel; +struct t_placer_opts; +struct t_router_opts; +struct t_det_routing_arch; +struct t_segment_inf; +struct t_chan_width_dist; +struct t_direct_inf; + +class PlacementDelayModelCreator { + public: + // nothing to do in the constructor + PlacementDelayModelCreator() = delete; + + static std::unique_ptr create_delay_model(const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + const Netlist<>& net_list, + t_det_routing_arch* det_routing_arch, + std::vector& segment_inf, + t_chan_width_dist chan_width_dist, + const std::vector& directs, + bool is_flat); +}; diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp new file mode 100644 index 00000000000..bb1232d2778 --- /dev/null +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp @@ -0,0 +1,966 @@ + +#include "compute_delta_delays_utils.h" + +#include "vtr_time.h" +#include "vtr_math.h" +#include "physical_types.h" +#include "globals.h" +#include "router_delay_profiling.h" + +/// Indicates the delta delay value has not been calculated +static constexpr float UNINITIALIZED_DELTA = -1; +/// Indicates delta delay from/to an EMPTY block +static constexpr float EMPTY_DELTA = -2; +/// Indicates there is no valid delta delay +static constexpr float IMPOSSIBLE_DELTA = std::numeric_limits::infinity(); + +static vtr::NdMatrix compute_delta_delays(RouterDelayProfiler& route_profiler, + const t_placer_opts& palcer_opts, + const t_router_opts& router_opts, + bool measure_directconnect, + size_t longest_length, + bool is_flat); + +static void fix_empty_coordinates(vtr::NdMatrix& delta_delays); + +static void fill_impossible_coordinates(vtr::NdMatrix& delta_delays); + +static bool verify_delta_delays(const vtr::NdMatrix& delta_delays); + +static void generic_compute_matrix_iterative_astar(RouterDelayProfiler& route_profiler, + vtr::Matrix>& matrix, + int from_layer_num, + int to_layer_num, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types, + bool /*is_flat*/); + +static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& route_profiler, + vtr::Matrix>& matrix, + int from_layer_num, + int to_layer_num, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types, + bool is_flat); + +/** + * @brief Routes between a source and sink location to calculate the delay. + * + * This function computes the delay of a routed connection between a source and sink node + * specified by their coordinates and layers. It iterates over the best driver and sink pin + * classes to find a valid routing path and calculates the delay if a path exists. + * + * @param route_profiler Reference to the `RouterDelayProfiler` responsible for calculating routing delays. + * @param source_x The x-coordinate of the source location. + * @param source_y The y-coordinate of the source location. + * @param source_layer The layer index of the source node. + * @param sink_x The x-coordinate of the sink location. + * @param sink_y The y-coordinate of the sink location. + * @param sink_layer The layer index of the sink node. + * @param router_opts Routing options used for delay calculation. + * @param measure_directconnect If `true`, includes direct connect delays; otherwise, skips direct connections. + * + * @return The calculated routing delay. If routing fails, it returns `IMPOSSIBLE_DELTA`. + */ +static float route_connection_delay(RouterDelayProfiler& route_profiler, + int source_x, + int source_y, + int source_layer, + int sink_x, + int sink_y, + int sink_layer, + const t_router_opts& router_opts, + bool measure_directconnect); + +/** + * @brief Computes a reduced value from a vector of delay values using the specified reduction method. + * + * @param delays A reference to a vector of delay values. This vector may be modified + * (e.g., sorted) depending on the reducer used. + * @param reducer The reduction method to be applied. + * + * @return The reduced delay value. If the input vector is empty, the function + * returns `IMPOSSIBLE_DELTA`. + * + * @throws VPR_FATAL_ERROR if the reducer is unrecognized. + */ +static float delay_reduce(std::vector& delays, e_reducer reducer); + +/** + * @brief Adds a delay value to a 2D matrix of delay vectors. + * + * Updates the delay vector at position (`delta_x`, `delta_y`) in the matrix. + * If the element contains only `EMPTY_DELTA`, it is replaced with the new delay; + * otherwise, the delay is appended to the vector. + * + * @param matrix A 2D matrix of delay vectors. + * @param delta_x The x-index in the matrix. + * @param delta_y The y-index in the matrix. + * @param delay The delay value to add. + */ +static void add_delay_to_matrix(vtr::Matrix>& matrix, + int delta_x, + int delta_y, + float delay); + +/** + * @brief Computes the average delay for a routing span. + * + * This function calculates the average placement delay for a routing span starting from a + * given layer and spanning a region defined by delta x and delta y. It iteratively searches + * for valid delay values within an expanding neighborhood (starting from a distance of 1) + * around the specified delta offsets and layer, until valid values are found or + * the maximum search distance (`max_distance`) is reached. + * + * @param matrix A 4D matrix of delay values indexed by `[from_layer][to_layer][delta_x][delta_y]`. + * @param from_layer The starting layer index of the routing span. + * @param to_tile_loc A structure holding the delta offsets (`x` and `y`) and the target layer index (`layer_num`). + * @param max_distance The maximum neighborhood distance to search for valid delay values. + * + * @return The average of valid delay values within the search range. If no valid delays + * are found up to the maximum distance, the function returns `IMPOSSIBLE_DELTA`. + * + * @note The function performs a Manhattan-distance-based neighborhood search around the target location. + */ +static float find_neighboring_average(vtr::NdMatrix& matrix, + int from_layer, + t_physical_tile_loc to_tile_loc, + int max_distance); + +/***************************************************************************************/ + +static vtr::NdMatrix compute_delta_delays(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + bool measure_directconnect, + size_t longest_length, + bool is_flat) { + + const auto& device_ctx = g_vpr_ctx.device(); + const auto& grid = device_ctx.grid; + + const size_t num_layers = grid.get_num_layers(); + const size_t device_width = grid.width(); + const size_t device_height = grid.height(); + + /* To avoid edge effects we place the source at least 'longest_length' away + * from the device edge and route from there for all possible delta values < dimension + */ + + // +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + // + | | + + // + A | B | C + + // + | | + + // +-----------------\-----------------------.---------------+ + // + | | + + // + | | + + // + | | + + // + | | + + // + D | E | F + + // + | | + + // + | | + + // + | | + + // + | | + + // +-----------------*-----------------------/---------------+ + // + | | + + // + G | H | I + + // + | | + + // +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + // + // * = (low_x, low_y) + // . = (high_x, high_y) + // / = (high_x, low_y) + // \ = (low_x, high_y) + // + = device edge + const size_t mid_x = vtr::nint(device_width / 2); + const size_t mid_y = vtr::nint(device_height / 2); + const size_t low_x = std::min(longest_length, mid_x); + const size_t low_y = std::min(longest_length, mid_y); + const size_t high_x = (longest_length <= device_width) ? std::max(device_width - longest_length, mid_x) : mid_x; + const size_t high_y = (longest_length <= device_height) ? std::max(device_width - longest_length, mid_y) : mid_y; + + vtr::NdMatrix delta_delays({num_layers, num_layers, device_width, device_height}); + + std::set allowed_types; + if (!placer_opts.allowed_tiles_for_delay_model.empty()) { + std::vector allowed_types_vector = vtr::split(placer_opts.allowed_tiles_for_delay_model, ","); + allowed_types = std::set(allowed_types_vector.begin(), allowed_types_vector.end()); + } + + for (int from_layer_num = 0; from_layer_num < (int)num_layers; from_layer_num++) { + for (int to_layer_num = 0; to_layer_num < (int)num_layers; to_layer_num++) { + vtr::NdMatrix, 2> sampled_delta_delays({device_width, device_height}); + + // Find the lowest y location on the left edge with a non-empty block + int y = 0; + int x = 0; + t_physical_tile_type_ptr src_type = nullptr; + for (x = 0; x < (int)device_width; ++x) { + for (y = 0; y < (int)device_height; ++y) { + t_physical_tile_type_ptr type = grid.get_physical_type({x, y, from_layer_num}); + + if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + // check if the tile type is among the allowed types + if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { + continue; + } + src_type = type; + break; + } + } + if (src_type != nullptr) { + break; + } + } + VTR_ASSERT(src_type != nullptr); + + auto generic_compute_matrix = (placer_opts.place_delta_delay_matrix_calculation_method == e_place_delta_delay_algorithm::ASTAR_ROUTE) ? generic_compute_matrix_iterative_astar : generic_compute_matrix_dijkstra_expansion; + +#ifdef VERBOSE + VTR_LOG("Computing from lower left edge (%d,%d):\n", x, y); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + x, y, + x, y, + device_width - 1, device_height - 1, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + // Find the lowest x location on the bottom edge with a non-empty block + src_type = nullptr; + for (y = 0; y < (int)device_height; ++y) { + for (x = 0; x < (int)device_width; ++x) { + t_physical_tile_type_ptr type = grid.get_physical_type({x, y, from_layer_num}); + + if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + // check if the tile type is among the allowed types + if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { + continue; + } + src_type = type; + break; + } + } + if (src_type) { + break; + } + } + VTR_ASSERT(src_type != nullptr); +#ifdef VERBOSE + VTR_LOG("Computing from left bottom edge (%d,%d):\n", x, y); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + x, y, + x, y, + device_width - 1, device_height - 1, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + //Since the other delta delay values may have suffered from edge effects, + //we recalculate deltas within regions B, C, E, F +#ifdef VERBOSE + VTR_LOG("Computing from low/low:\n"); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + low_x, low_y, + low_x, low_y, + device_width - 1, device_height - 1, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + //Since the other delta delay values may have suffered from edge effects, + //we recalculate deltas within regions D, E, G, H +#ifdef VERBOSE + VTR_LOG("Computing from high/high:\n"); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + high_x, high_y, + 0, 0, + high_x, high_y, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + //Since the other delta delay values may have suffered from edge effects, + //we recalculate deltas within regions A, B, D, E +#ifdef VERBOSE + VTR_LOG("Computing from high/low:\n"); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + high_x, low_y, + 0, low_y, + high_x, device_height - 1, + router_opts, + measure_directconnect, allowed_types, + is_flat); + + //Since the other delta delay values may have suffered from edge effects, + //we recalculate deltas within regions E, F, H, I +#ifdef VERBOSE + VTR_LOG("Computing from low/high:\n"); +#endif + generic_compute_matrix(route_profiler, sampled_delta_delays, + from_layer_num, to_layer_num, + low_x, high_y, + low_x, 0, + device_width - 1, high_y, + router_opts, + measure_directconnect, allowed_types, + is_flat); + for (size_t dx = 0; dx < sampled_delta_delays.dim_size(0); ++dx) { + for (size_t dy = 0; dy < sampled_delta_delays.dim_size(1); ++dy) { + delta_delays[from_layer_num][to_layer_num][dx][dy] = delay_reduce(sampled_delta_delays[dx][dy], placer_opts.delay_model_reducer); + } + } + } + } + + return delta_delays; +} + +static void fix_empty_coordinates(vtr::NdMatrix& delta_delays) { + // Set any empty delta's to the average of its neighbours + // + // Empty coordinates may occur if the sampling location happens to not have + // a connection at that location. However, a more thorough sampling likely + // would return a result, so we fill in the empty holes with a small + // neighbour average. + constexpr int kMaxAverageDistance = 2; + for (int from_layer = 0; from_layer < (int)delta_delays.dim_size(0); ++from_layer) { + for (int to_layer = 0; to_layer < (int)delta_delays.dim_size(1); ++to_layer) { + for (int delta_x = 0; delta_x < (int)delta_delays.dim_size(2); ++delta_x) { + for (int delta_y = 0; delta_y < (int)delta_delays.dim_size(3); ++delta_y) { + if (delta_delays[from_layer][to_layer][delta_x][delta_y] == EMPTY_DELTA) { + delta_delays[from_layer][to_layer][delta_x][delta_y] = find_neighboring_average(delta_delays, + from_layer, + {delta_x, delta_y, to_layer}, + kMaxAverageDistance); + } + } + } + } + } +} + +static void fill_impossible_coordinates(vtr::NdMatrix& delta_delays) { + // Set any impossible delta's to the average of its neighbours + // + // Impossible coordinates may occur if an IPIN cannot be reached from the + // sampling OPIN. This might occur if the IPIN or OPIN used for sampling + // is specialized, and therefore cannot be reached via the by the pins + // sampled. Leaving this value in the delay matrix will result in invalid + // slacks if the delay matrix uses this value. + // + // A max average distance of 5 is used to provide increased effort in + // filling these gaps. It is more important to have a poor predication, + // than an invalid value and causing a slack assertion. + constexpr int kMaxAverageDistance = 5; + for (int from_layer_num = 0; from_layer_num < (int)delta_delays.dim_size(0); ++from_layer_num) { + for (int to_layer_num = 0; to_layer_num < (int)delta_delays.dim_size(1); ++to_layer_num) { + for (int delta_x = 0; delta_x < (int)delta_delays.dim_size(2); ++delta_x) { + for (int delta_y = 0; delta_y < (int)delta_delays.dim_size(3); ++delta_y) { + if (delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] == IMPOSSIBLE_DELTA) { + delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] = find_neighboring_average( + delta_delays, from_layer_num, {delta_x, delta_y, to_layer_num}, kMaxAverageDistance); + } + } + } + } + } +} + +static bool verify_delta_delays(const vtr::NdMatrix& delta_delays) { + const auto& device_ctx = g_vpr_ctx.device(); + const auto& grid = device_ctx.grid; + + for (int from_layer_num = 0; from_layer_num < grid.get_num_layers(); ++from_layer_num) { + for (int to_layer_num = 0; to_layer_num < grid.get_num_layers(); ++to_layer_num) { + for (size_t x = 0; x < grid.width(); ++x) { + for (size_t y = 0; y < grid.height(); ++y) { + float delta_delay = delta_delays[from_layer_num][to_layer_num][x][y]; + + if (delta_delay < 0.) { + VPR_ERROR(VPR_ERROR_PLACE, + "Found invalid negative delay %g for delta [%d,%d,%d,%d]", + delta_delay, from_layer_num, to_layer_num, x, y); + } + } + } + } + } + + return true; +} + +static void generic_compute_matrix_iterative_astar(RouterDelayProfiler& route_profiler, + vtr::Matrix>& matrix, + int from_layer_num, + int to_layer_num, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types, + bool /*is_flat*/) { + const auto& device_ctx = g_vpr_ctx.device(); + + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + const int delta_x = abs(sink_x - source_x); + const int delta_y = abs(sink_y - source_y); + + t_physical_tile_type_ptr src_type = device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num}); + t_physical_tile_type_ptr sink_type = device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num}); + + bool src_or_target_empty = (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE + || sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE); + + bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); + + if (src_or_target_empty || !is_allowed_type) { + if (matrix[delta_x][delta_y].empty()) { + // Only set empty target if we don't already have a valid delta delay + matrix[delta_x][delta_y].push_back(EMPTY_DELTA); +#ifdef VERBOSE + VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", + "EMPTY", + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + } + } else { + // Valid start/end + float delay = route_connection_delay(route_profiler, + source_x, + source_y, + from_layer_num, + sink_x, + sink_y, + to_layer_num, + router_opts, + measure_directconnect); + +#ifdef VERBOSE + VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", + delay, + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + if (matrix[delta_x][delta_y].size() == 1 && matrix[delta_x][delta_y][0] == EMPTY_DELTA) { + // Overwrite empty delta + matrix[delta_x][delta_y][0] = delay; + } else { + // Collect delta + matrix[delta_x][delta_y].push_back(delay); + } + } + } + } +} + +static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*route_profiler*/, + vtr::Matrix>& matrix, + int from_layer_num, + int to_layer_num, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types, + bool is_flat) { + const auto& device_ctx = g_vpr_ctx.device(); + + t_physical_tile_type_ptr src_type = device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num}); + bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); + if (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE || !is_allowed_type) { + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + + if (matrix[delta_x][delta_y].empty()) { + //Only set empty target if we don't already have a valid delta delay + matrix[delta_x][delta_y].push_back(EMPTY_DELTA); +#ifdef VERBOSE + VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", + "EMPTY", + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + } + } + } + + return; + } + + vtr::Matrix found_matrix({matrix.dim_size(0), matrix.dim_size(1)}, false); + + auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); + for (int driver_ptc : best_driver_ptcs) { + VTR_ASSERT(driver_ptc != OPEN); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, SOURCE, driver_ptc); + + VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); + auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts, is_flat); + + bool path_to_all_sinks = true; + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + + if (found_matrix[delta_x][delta_y]) { + continue; + } + + t_physical_tile_type_ptr sink_type = device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num}); + if (sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + if (matrix[delta_x][delta_y].empty()) { + // Only set empty target if we don't already have a valid delta delay + matrix[delta_x][delta_y].push_back(EMPTY_DELTA); +#ifdef VERBOSE + VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", + "EMPTY", + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + found_matrix[delta_x][delta_y] = true; + } + } else { + bool found_a_sink = false; + auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); + for (int sink_ptc : best_sink_ptcs) { + VTR_ASSERT(sink_ptc != OPEN); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, SINK, sink_ptc); + + if (sink_rr_node == RRNodeId::INVALID()) + continue; + + if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { + // Skip if we shouldn't measure direct connects and a direct connect exists + continue; + } + + if (std::isnan(delays[sink_rr_node])) { + // This sink was not found + continue; + } + +#ifdef VERBOSE + VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", + delays[size_t(sink_rr_node)], + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + found_matrix[delta_x][delta_y] = true; + + add_delay_to_matrix(matrix, delta_x, delta_y, delays[sink_rr_node]); + + found_a_sink = true; + break; + } + + if (!found_a_sink) { + path_to_all_sinks = false; + } + } + } + } + + if (path_to_all_sinks) { + break; + } + } + + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + if (!found_matrix[delta_x][delta_y]) { + add_delay_to_matrix(matrix, delta_x, delta_y, IMPOSSIBLE_DELTA); + VTR_LOG_WARN("Unable to route between blocks at (%d,%d,%d) and (%d,%d,%d) to characterize delay (setting to %g)\n", + source_x, + source_y, + from_layer_num, + sink_x, + sink_y, + to_layer_num, + IMPOSSIBLE_DELTA); + } + } + } +} + +static float route_connection_delay(RouterDelayProfiler& route_profiler, + int source_x, + int source_y, + int source_layer, + int sink_x, + int sink_y, + int sink_layer, + const t_router_opts& router_opts, + bool measure_directconnect) { + //Routes between the source and sink locations and calculates the delay + + // set to known value for debug purposes + float net_delay_value = IMPOSSIBLE_DELTA; + + const auto& device_ctx = g_vpr_ctx.device(); + + bool successfully_routed = false; + + // Get the rr nodes to route between + auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, source_layer})); + auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, sink_layer})); + + for (int driver_ptc : best_driver_ptcs) { + VTR_ASSERT(driver_ptc != OPEN); + RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, SOURCE, driver_ptc); + + VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); + + for (int sink_ptc : best_sink_ptcs) { + VTR_ASSERT(sink_ptc != OPEN); + RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(sink_layer, sink_x, sink_y, SINK, sink_ptc); + + if (sink_rr_node == RRNodeId::INVALID()) + continue; + + if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { + // Skip if we shouldn't measure direct connects and a direct connect exists + continue; + } + + successfully_routed = route_profiler.calculate_delay(source_rr_node, + sink_rr_node, + router_opts, + &net_delay_value); + + if (successfully_routed) break; + } + if (successfully_routed) break; + } + + if (!successfully_routed) { + VTR_LOG_WARN("Unable to route between blocks at (%d,%d,%d) and (%d,%d,%d) to characterize delay (setting to %g)\n", + source_x, source_y, source_layer, sink_x, sink_y, sink_layer, net_delay_value); + } + + return net_delay_value; +} + +static float delay_reduce(std::vector& delays, e_reducer reducer) { + if (delays.empty()) { + return IMPOSSIBLE_DELTA; + } + + if (delays.size() == 1) { + return delays[0]; + } + + VTR_ASSERT(delays.size() > 1); + + float delay; + + if (reducer == e_reducer::MIN) { + auto itr = std::min_element(delays.begin(), delays.end()); + delay = *itr; + } else if (reducer == e_reducer::MAX) { + auto itr = std::max_element(delays.begin(), delays.end()); + delay = *itr; + } else if (reducer == e_reducer::MEDIAN) { + std::stable_sort(delays.begin(), delays.end()); + delay = vtr::median(delays.begin(), delays.end()); + } else if (reducer == e_reducer::ARITHMEAN) { + delay = vtr::arithmean(delays.begin(), delays.end()); + } else if (reducer == e_reducer::GEOMEAN) { + delay = vtr::geomean(delays.begin(), delays.end()); + } else { + VPR_FATAL_ERROR(VPR_ERROR_PLACE, "Unrecognized delta delay reducer"); + } + + return delay; +} + +static void add_delay_to_matrix(vtr::Matrix>& matrix, + int delta_x, + int delta_y, + float delay) { + if (matrix[delta_x][delta_y].size() == 1 && matrix[delta_x][delta_y][0] == EMPTY_DELTA) { + // Overwrite empty delta + matrix[delta_x][delta_y][0] = delay; + } else { + // Collect delta + matrix[delta_x][delta_y].push_back(delay); + } +} + +static float find_neighboring_average(vtr::NdMatrix& matrix, + int from_layer, + t_physical_tile_loc to_tile_loc, + int max_distance) { + float sum = 0.f; + int num_samples = 0; + const int endx = matrix.end_index(2); + const int endy = matrix.end_index(3); + + const int x = to_tile_loc.x; + const int y = to_tile_loc.y; + const int to_layer = to_tile_loc.layer_num; + + for (int distance = 1; distance <= max_distance; ++distance) { + for (int delx = x - distance; delx <= x + distance; delx++) { + for (int dely = y - distance; dely <= y + distance; dely++) { + // Check distance constraint + if (abs(delx - x) + abs(dely - y) > distance) { + continue; + } + + //check out of bounds + if (delx < 0 || dely < 0 || delx >= endx || dely >= endy || (delx == x && dely == y)) { + continue; + } + + if (matrix[from_layer][to_layer][delx][dely] == EMPTY_DELTA || matrix[from_layer][to_layer][delx][dely] == IMPOSSIBLE_DELTA) { + continue; + } + + sum += matrix[from_layer][to_layer][delx][dely]; + num_samples++; + } + } + + if (num_samples != 0) { + return sum / (float)num_samples; + } + } + + return IMPOSSIBLE_DELTA; +} + +/***************************************************************************************/ + +vtr::NdMatrix compute_delta_delay_model(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + bool measure_directconnect, + int longest_length, + bool is_flat) { + vtr::ScopedStartFinishTimer timer("Computing delta delays"); + vtr::NdMatrix delta_delays = compute_delta_delays(route_profiler, + placer_opts, + router_opts, + measure_directconnect, + longest_length, + is_flat); + + const size_t num_elements = delta_delays.size(); + + // set uninitialized elements to infinity + for (size_t i = 0; i < num_elements; i++) { + if (delta_delays.get(i) == UNINITIALIZED_DELTA) { + delta_delays.get(i) = IMPOSSIBLE_DELTA; + } + } + + fix_empty_coordinates(delta_delays); + + fill_impossible_coordinates(delta_delays); + + verify_delta_delays(delta_delays); + + return delta_delays; +} + +//Finds a src_rr and sink_rr appropriate for measuring the delay of the current direct specification +bool find_direct_connect_sample_locations(const t_direct_inf* direct, + t_physical_tile_type_ptr from_type, + int from_pin, + int from_pin_class, + t_physical_tile_type_ptr to_type, + int to_pin, + int to_pin_class, + RRNodeId& out_src_node, + RRNodeId& out_sink_node) { + VTR_ASSERT(from_type != nullptr); + VTR_ASSERT(to_type != nullptr); + + auto& device_ctx = g_vpr_ctx.device(); + auto& grid = device_ctx.grid; + const auto& node_lookup = device_ctx.rr_graph.node_lookup(); + + //Search the grid for an instance of from/to blocks which satisfy this direct connect offsets, + //and which has the appropriate pins + int from_x = -1; + int from_y = -1; + int from_sub_tile = -1; + int to_x = 0, to_y = 0, to_sub_tile = 0; + bool found = false; + int found_layer_num = -1; + //TODO: Function *FOR NOW* assumes that from/to blocks are at same die and have a same layer nums + for (int layer_num = 0; layer_num < grid.get_num_layers() && !found; ++layer_num) { + for (int x = 0; x < (int)grid.width() && !found; ++x) { + to_x = x + direct->x_offset; + if (to_x < 0 || to_x >= (int)grid.width()) continue; + + for (int y = 0; y < (int)grid.height() && !found; ++y) { + if (grid.get_physical_type({x, y, layer_num}) != from_type) continue; + + //Check that the from pin exists at this from location + //(with multi-width/height blocks pins may not exist at all locations) + bool from_pin_found = false; + if (direct->from_side != NUM_2D_SIDES) { + RRNodeId from_pin_rr = node_lookup.find_node(layer_num, x, y, OPIN, from_pin, direct->from_side); + from_pin_found = from_pin_rr.is_valid(); + } else { + from_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, x, y, OPIN, from_pin).empty()); + } + if (!from_pin_found) continue; + + to_y = y + direct->y_offset; + + if (to_y < 0 || to_y >= (int)grid.height()) continue; + if (grid.get_physical_type({to_x, to_y, layer_num}) != to_type) continue; + + //Check that the from pin exists at this from location + //(with multi-width/height blocks pins may not exist at all locations) + bool to_pin_found = false; + if (direct->to_side != NUM_2D_SIDES) { + RRNodeId to_pin_rr = node_lookup.find_node(layer_num, to_x, to_y, IPIN, to_pin, direct->to_side); + to_pin_found = (to_pin_rr != RRNodeId::INVALID()); + } else { + to_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, to_x, to_y, IPIN, to_pin).empty()); + } + if (!to_pin_found) continue; + + for (int sub_tile_num = 0; sub_tile_num < from_type->capacity; ++sub_tile_num) { + to_sub_tile = sub_tile_num + direct->sub_tile_offset; + + if (to_sub_tile < 0 || to_sub_tile >= to_type->capacity) continue; + + found = true; + found_layer_num = layer_num; + from_x = x; + from_y = y; + from_sub_tile = sub_tile_num; + + break; + } + } + } + } + + if (!found) { + return false; + } + + //Now have a legal instance of this direct connect + VTR_ASSERT(grid.get_physical_type({from_x, from_y, found_layer_num}) == from_type); + VTR_ASSERT(from_sub_tile < from_type->capacity); + + VTR_ASSERT(grid.get_physical_type({to_x, to_y, found_layer_num}) == to_type); + VTR_ASSERT(to_sub_tile < to_type->capacity); + + VTR_ASSERT(from_x + direct->x_offset == to_x); + VTR_ASSERT(from_y + direct->y_offset == to_y); + VTR_ASSERT(from_sub_tile + direct->sub_tile_offset == to_sub_tile); + + // Find a source/sink RR node associated with the pins of the direct + { + RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, SOURCE, from_pin_class); + VTR_ASSERT(src_rr_candidate); + out_src_node = src_rr_candidate; + } + + { + RRNodeId sink_rr_candidate = node_lookup.find_node(found_layer_num, to_x, to_y, SINK, to_pin_class); + VTR_ASSERT(sink_rr_candidate); + out_sink_node = sink_rr_candidate; + } + + return true; +} + +std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type) { + std::vector best_classes; + + //Record any non-zero Fc pins + // + //Note that we track non-zero Fc pins, since certain Fc overrides + //may apply to only a subset of wire types. This ensures we record + //which pins can potentially connect to global routing. + std::unordered_set non_zero_fc_pins; + for (const t_fc_specification& fc_spec : type->fc_specs) { + if (fc_spec.fc_value == 0) continue; + + non_zero_fc_pins.insert(fc_spec.pins.begin(), fc_spec.pins.end()); + } + + // Collect all classes of matching type which connect to general routing + for (int i = 0; i < (int)type->class_inf.size(); i++) { + if (type->class_inf[i].type == pintype) { + //Check whether all pins in this class are ignored or have zero fc + bool any_pins_connect_to_general_routing = false; + for (int ipin = 0; ipin < type->class_inf[i].num_pins; ++ipin) { + int pin = type->class_inf[i].pinlist[ipin]; + //If the pin isn't ignored, and has a non-zero Fc to some general + //routing the class is suitable for delay profiling + if (!type->is_ignored_pin[pin] && non_zero_fc_pins.count(pin)) { + any_pins_connect_to_general_routing = true; + break; + } + } + + // Skip if the pin class doesn't connect to general routing + if (!any_pins_connect_to_general_routing) continue; + + // Record candidate class + best_classes.push_back(i); + } + } + + // Sort classes so the largest pin class is first + auto cmp_class = [&](int lhs, int rhs) { + return type->class_inf[lhs].num_pins > type->class_inf[rhs].num_pins; + }; + + std::stable_sort(best_classes.begin(), best_classes.end(), cmp_class); + + return best_classes; +} diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.h b/vpr/src/place/delay_model/compute_delta_delays_utils.h new file mode 100644 index 00000000000..d51c41cf18f --- /dev/null +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.h @@ -0,0 +1,56 @@ + +#pragma once + +#include "vtr_ndmatrix.h" +#include "physical_types.h" +#include "rr_graph_fwd.h" + +struct t_placer_opts; +struct t_router_opts; +class RouterDelayProfiler; + +vtr::NdMatrix compute_delta_delay_model(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + bool measure_directconnect, + int longest_length, + bool is_flat); + +bool find_direct_connect_sample_locations(const t_direct_inf* direct, + t_physical_tile_type_ptr from_type, + int from_pin, + int from_pin_class, + t_physical_tile_type_ptr to_type, + int to_pin, + int to_pin_class, + RRNodeId& out_src_node, + RRNodeId& out_sink_node); + +/** + * @brief Identifies the best pin classes for delay calculation based on pin count and connectivity. + * + * This function selects pin classes of a specified type (`pintype`) from a physical tile type (`type`) + * that are suitable for delay calculations. It prioritizes pin classes with the largest number of pins + * that connect to general routing, ensuring commonly used pins are chosen for delay profiling. + * + * @param pintype The type of pins to filter. + * @param type Pointer to the physical tile type containing pin and class information. + * + * @return A vector of indices representing the selected pin classes. The classes are sorted + * in descending order based on the number of pins they contain. + * + * @details + * - A pin class is eligible if its type matches `pintype` and it contains at least one pin + * that connects to general routing (non-zero Fc). + * - Non-zero Fc pins are determined by inspecting the tile's `fc_specs`. + * - Classes are sorted so that the class with the largest number of pins appears first. + * If multiple classes have the same pin count, their order depends on their initial appearance + * in the architecture file. + * + * @note + * - Pins explicitly marked as ignored in `type->is_ignored_pin` are excluded. + * - The function ensures stability in sorting, preserving the input order for classes + * with the same number of pins. + */ + +std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type); diff --git a/vpr/src/place/delay_model/delta_delay_model.cpp b/vpr/src/place/delay_model/delta_delay_model.cpp new file mode 100644 index 00000000000..508787b6d69 --- /dev/null +++ b/vpr/src/place/delay_model/delta_delay_model.cpp @@ -0,0 +1,136 @@ + +#include "delta_delay_model.h" + +#include "compute_delta_delays_utils.h" + +#ifdef VTR_ENABLE_CAPNPROTO +#include "capnp/serialize.h" +#include "place_delay_model.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" +#endif // VTR_ENABLE_CAPNPROTO + +void DeltaDelayModel::compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) { + delays_ = compute_delta_delay_model(route_profiler, + placer_opts, + router_opts, + /*measure_directconnect=*/true, + longest_length, + is_flat_); +} + +float DeltaDelayModel::delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const { + int delta_x = std::abs(from_loc.x - to_loc.x); + int delta_y = std::abs(from_loc.y - to_loc.y); + + return delays_[from_loc.layer_num][to_loc.layer_num][delta_x][delta_y]; +} + +void DeltaDelayModel::dump_echo(std::string filepath) const { + FILE* f = vtr::fopen(filepath.c_str(), "w"); + fprintf(f, " "); + for (size_t from_layer_num = 0; from_layer_num < delays_.dim_size(0); ++from_layer_num) { + for (size_t to_layer_num = 0; to_layer_num < delays_.dim_size(1); ++to_layer_num) { + fprintf(f, " %9zu", from_layer_num); + fprintf(f, "\n"); + for (size_t dx = 0; dx < delays_.dim_size(2); ++dx) { + fprintf(f, " %9zu", dx); + } + fprintf(f, "\n"); + for (size_t dy = 0; dy < delays_.dim_size(3); ++dy) { + fprintf(f, "%9zu", dy); + for (size_t dx = 0; dx < delays_.dim_size(2); ++dx) { + fprintf(f, " %9.2e", delays_[from_layer_num][to_layer_num][dx][dy]); + } + fprintf(f, "\n"); + } + } + } + vtr::fclose(f); +} + +void DeltaDelayModel::read(const std::string& file) { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "OverrideDelayModel::read is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + + // MmapFile object creates an mmap of the specified path, and will munmap + // when the object leaves scope. + MmapFile f(file); + + /* Increase reader limit to 1G words to allow for large files. */ + ::capnp::ReaderOptions opts = default_large_capnp_opts(); + + // FlatArrayMessageReader is used to read the message from the data array + // provided by MmapFile. + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); + + // When reading capnproto files the Reader object to use is named + // ::Reader. + // + // Initially this object is an empty VprDeltaDelayModel. + VprDeltaDelayModel::Reader model; + + // The reader.getRoot performs a cast from the generic capnproto to fit + // with the specified schema. + // + // Note that capnproto does not validate that the incoming data matches the + // schema. If this property is required, some form of check would be + // required. + model = reader.getRoot(); + + auto toFloat = [](float* out, const VprFloatEntry::Reader& in) -> void { + *out = in.getValue(); + }; + + // ToNdMatrix is a generic function for converting a Matrix capnproto + // to a vtr::NdMatrix. + // + // The user must supply the matrix dimension (2 in this case), the source + // capnproto type (VprFloatEntry), + // target C++ type (flat), and a function to convert from the source capnproto + // type to the target C++ type (ToFloat). + // + // The second argument should be of type Matrix::Reader where X is the + // capnproto element type. + ToNdMatrix<4, VprFloatEntry, float>(&delays_, model.getDelays(), toFloat); +#endif +} + +void DeltaDelayModel::write(const std::string& file) const { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "DeltaDelayModel::write is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + + // MallocMessageBuilder object is the generate capnproto message builder, + // using malloc for buffer allocation. + ::capnp::MallocMessageBuilder builder; + + // initRoot returns a X::Builder object that can be used to set the + // fields in the message. + auto model = builder.initRoot(); + + auto fromFloat = [](VprFloatEntry::Builder* out, const float& in) -> void { + out->setValue(in); + }; + + // FromNdMatrix is a generic function for converting a vtr::NdMatrix to a + // Matrix message. It is the mirror function of ToNdMatrix described in + // read above. + auto delay_values = model.getDelays(); + FromNdMatrix<4, VprFloatEntry, float>(&delay_values, delays_, fromFloat); + + // writeMessageToFile writes message to the specified file. + writeMessageToFile(file, &builder); +#endif +} diff --git a/vpr/src/place/delay_model/delta_delay_model.h b/vpr/src/place/delay_model/delta_delay_model.h new file mode 100644 index 00000000000..a4c548210ae --- /dev/null +++ b/vpr/src/place/delay_model/delta_delay_model.h @@ -0,0 +1,47 @@ + +#pragma once + +#include "place_delay_model.h" + +/** + * @class DeltaDelayModel + * + * @brief A simple delay model based on the distance (delta) between block locations. + */ +class DeltaDelayModel : public PlaceDelayModel { + public: + DeltaDelayModel(float min_cross_layer_delay, + bool is_flat) + : cross_layer_delay_(min_cross_layer_delay) + , is_flat_(is_flat) {} + + DeltaDelayModel(float min_cross_layer_delay, + vtr::NdMatrix delta_delays, + bool is_flat) + : delays_(std::move(delta_delays)) + , cross_layer_delay_(min_cross_layer_delay) + , is_flat_(is_flat) {} + + void compute(RouterDelayProfiler& router, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) override; + + float delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const override; + + void dump_echo(std::string filepath) const override; + + void read(const std::string& file) override; + void write(const std::string& file) const override; + + const vtr::NdMatrix& delays() const { + return delays_; + } + + private: + vtr::NdMatrix delays_; // [0..num_layers-1][0..max_dx][0..max_dy] + float cross_layer_delay_; + + /// Indicates whether the router is a two-stage or run-flat + bool is_flat_; +}; diff --git a/vpr/src/place/delay_model/override_delay_model.cpp b/vpr/src/place/delay_model/override_delay_model.cpp new file mode 100644 index 00000000000..a3d99c73c9d --- /dev/null +++ b/vpr/src/place/delay_model/override_delay_model.cpp @@ -0,0 +1,282 @@ + +#include "override_delay_model.h" + +#include "compute_delta_delays_utils.h" +#include "physical_types_util.h" + +#ifdef VTR_ENABLE_CAPNPROTO +#include "capnp/serialize.h" +#include "place_delay_model.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" +#endif // VTR_ENABLE_CAPNPROTO + +void OverrideDelayModel::compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) { + auto delays = compute_delta_delay_model(route_profiler, + placer_opts, + router_opts, + /*measure_directconnect=*/false, + longest_length, + is_flat_); + + base_delay_model_ = std::make_unique(cross_layer_delay_, delays, false); + + compute_override_delay_model_(route_profiler, router_opts); +} + +void OverrideDelayModel::compute_override_delay_model_(RouterDelayProfiler& route_profiler, + const t_router_opts& router_opts) { + const auto& device_ctx = g_vpr_ctx.device(); + t_router_opts router_opts2 = router_opts; + router_opts2.astar_fac = 0.f; + router_opts2.astar_offset = 0.f; + + // Look at all the direct connections that exist, and add overrides to delay model + for (int idirect = 0; idirect < (int)device_ctx.arch->directs.size(); ++idirect) { + const t_direct_inf* direct = &device_ctx.arch->directs[idirect]; + + InstPort from_port = parse_inst_port(direct->from_pin); + InstPort to_port = parse_inst_port(direct->to_pin); + + t_physical_tile_type_ptr from_type = find_tile_type_by_name(from_port.instance_name(), device_ctx.physical_tile_types); + t_physical_tile_type_ptr to_type = find_tile_type_by_name(to_port.instance_name(), device_ctx.physical_tile_types); + + int num_conns = from_port.port_high_index() - from_port.port_low_index() + 1; + VTR_ASSERT_MSG(num_conns == to_port.port_high_index() - to_port.port_low_index() + 1, "Directs must have the same size to/from"); + + //We now walk through all the connections associated with the current direct specification, measure + //their delay and specify that value as an override in the delay model. + // + //Note that we need to check every connection in the direct to cover the case where the pins are not + //equivalent. + // + //However, if the from/to ports are equivalent we could end up sampling the same RR SOURCE/SINK + //paths multiple times (wasting CPU time) -- we avoid this by recording the sampled paths in + //sampled_rr_pairs and skipping them if they occur multiple times. + int missing_instances = 0; + int missing_paths = 0; + std::set> sampled_rr_pairs; + for (int iconn = 0; iconn < num_conns; ++iconn) { + //Find the associated pins + int from_pin = from_type->find_pin(from_port.port_name(), from_port.port_low_index() + iconn); + int to_pin = to_type->find_pin(to_port.port_name(), to_port.port_low_index() + iconn); + + VTR_ASSERT(from_pin != OPEN); + VTR_ASSERT(to_pin != OPEN); + + int from_pin_class = from_type->find_pin_class(from_port.port_name(), from_port.port_low_index() + iconn, DRIVER); + VTR_ASSERT(from_pin_class != OPEN); + + int to_pin_class = to_type->find_pin_class(to_port.port_name(), to_port.port_low_index() + iconn, RECEIVER); + VTR_ASSERT(to_pin_class != OPEN); + + bool found_sample_points; + RRNodeId src_rr, sink_rr; + found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, src_rr, sink_rr); + + if (!found_sample_points) { + ++missing_instances; + continue; + } + + //If some of the source/sink ports are logically equivalent we may have already + //sampled the associated source/sink pair and don't need to do so again + if (sampled_rr_pairs.count({src_rr, sink_rr})) continue; + + float direct_connect_delay = std::numeric_limits::quiet_NaN(); + bool found_routing_path = route_profiler.calculate_delay(src_rr, sink_rr, router_opts2, &direct_connect_delay); + + if (found_routing_path) { + set_delay_override(from_type->index, from_pin_class, to_type->index, to_pin_class, direct->x_offset, direct->y_offset, direct_connect_delay); + } else { + ++missing_paths; + } + + //Record that we've sampled this pair of source and sink nodes + sampled_rr_pairs.insert({src_rr, sink_rr}); + } + + VTR_LOGV_WARN(missing_instances > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no instances of this direct found)\n", missing_instances, direct->name.c_str()); + VTR_LOGV_WARN(missing_paths > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no routing path found)\n", missing_paths, direct->name.c_str()); + } +} + +const DeltaDelayModel* OverrideDelayModel::base_delay_model() const { + return base_delay_model_.get(); +} + +float OverrideDelayModel::delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const { + // First check to if there is an override delay value + const auto& device_ctx = g_vpr_ctx.device(); + const auto& grid = device_ctx.grid; + + t_physical_tile_type_ptr from_type_ptr = grid.get_physical_type(from_loc); + t_physical_tile_type_ptr to_type_ptr = grid.get_physical_type(to_loc); + + t_override override_key; + override_key.from_type = from_type_ptr->index; + override_key.from_class = from_type_ptr->pin_class[from_pin]; + override_key.to_type = to_type_ptr->index; + override_key.to_class = to_type_ptr->pin_class[to_pin]; + + //Delay overrides may be different for +/- delta so do not use + //an absolute delta for the look-up + override_key.delta_x = to_loc.x - from_loc.x; + override_key.delta_y = to_loc.y - from_loc.y; + + float delay_val = std::numeric_limits::quiet_NaN(); + auto override_iter = delay_overrides_.find(override_key); + if (override_iter != delay_overrides_.end()) { + //Found an override + delay_val = override_iter->second; + } else { + //Fall back to the base delay model if no override was found + delay_val = base_delay_model_->delay(from_loc, from_pin, to_loc, to_pin); + } + + return delay_val; +} + +void OverrideDelayModel::set_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y, float delay_val) { + t_override override_key; + override_key.from_type = from_type; + override_key.from_class = from_class; + override_key.to_type = to_type; + override_key.to_class = to_class; + override_key.delta_x = delta_x; + override_key.delta_y = delta_y; + + auto res = delay_overrides_.insert(std::make_pair(override_key, delay_val)); + if (!res.second) { //Key already exists + res.first->second = delay_val; //Overwrite existing delay + } +} + +void OverrideDelayModel::dump_echo(std::string filepath) const { + base_delay_model_->dump_echo(filepath); + + FILE* f = vtr::fopen(filepath.c_str(), "a"); + + fprintf(f, "\n"); + fprintf(f, "# Delay Overrides\n"); + auto& device_ctx = g_vpr_ctx.device(); + for (auto kv : delay_overrides_) { + auto override_key = kv.first; + float delay_val = kv.second; + fprintf(f, "from_type: %s to_type: %s from_pin_class: %d to_pin_class: %d delta_x: %d delta_y: %d -> delay: %g\n", + device_ctx.physical_tile_types[override_key.from_type].name.c_str(), + device_ctx.physical_tile_types[override_key.to_type].name.c_str(), + override_key.from_class, + override_key.to_class, + override_key.delta_x, + override_key.delta_y, + delay_val); + } + + vtr::fclose(f); +} + +float OverrideDelayModel::get_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y) const { + t_override key; + key.from_type = from_type; + key.from_class = from_class; + key.to_type = to_type; + key.to_class = to_class; + key.delta_x = delta_x; + key.delta_y = delta_y; + + auto iter = delay_overrides_.find(key); + if (iter == delay_overrides_.end()) { + VPR_THROW(VPR_ERROR_PLACE, "Key not found."); + } + return iter->second; +} + +void OverrideDelayModel::set_base_delay_model(std::unique_ptr base_delay_model_obj) { + base_delay_model_ = std::move(base_delay_model_obj); +} + +void OverrideDelayModel::read(const std::string& file) { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "OverrideDelayModel::read is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + MmapFile f(file); + + /* Increase reader limit to 1G words to allow for large files. */ + ::capnp::ReaderOptions opts = default_large_capnp_opts(); + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); + + auto toFloat = [](float* out, const VprFloatEntry::Reader& in) -> void { + *out = in.getValue(); + }; + + vtr::NdMatrix delays; + auto model = reader.getRoot(); + ToNdMatrix<4, VprFloatEntry, float>(&delays, model.getDelays(), toFloat); + + base_delay_model_ = std::make_unique(cross_layer_delay_, delays, is_flat_); + + // Reading non-scalar capnproto fields is roughly equivalent to using + // a std::vector of the field type. Actual type is capnp::List::Reader. + auto overrides = model.getDelayOverrides(); + std::vector> overrides_arr(overrides.size()); + for (size_t i = 0; i < overrides.size(); ++i) { + const auto& elem = overrides[i]; + overrides_arr[i].first.from_type = elem.getFromType(); + overrides_arr[i].first.to_type = elem.getToType(); + overrides_arr[i].first.from_class = elem.getFromClass(); + overrides_arr[i].first.to_class = elem.getToClass(); + overrides_arr[i].first.delta_x = elem.getDeltaX(); + overrides_arr[i].first.delta_y = elem.getDeltaY(); + + overrides_arr[i].second = elem.getDelay(); + } + + delay_overrides_ = vtr::make_flat_map2(std::move(overrides_arr)); +#endif +} + +void OverrideDelayModel::write(const std::string& file) const { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "OverrideDelayModel::write is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + ::capnp::MallocMessageBuilder builder; + auto model = builder.initRoot(); + + auto fromFloat = [](VprFloatEntry::Builder* out, const float& in) -> void { + out->setValue(in); + }; + + auto delays = model.getDelays(); + FromNdMatrix<4, VprFloatEntry, float>(&delays, base_delay_model_->delays(), fromFloat); + + // Non-scalar capnproto fields should be first initialized with + // init(count), and then accessed from the returned + // std::vector-like Builder object (specifically capnp::List::Builder). + auto overrides = model.initDelayOverrides(delay_overrides_.size()); + auto dst_iter = overrides.begin(); + for (const auto& src : delay_overrides_) { + auto elem = *dst_iter++; + elem.setFromType(src.first.from_type); + elem.setToType(src.first.to_type); + elem.setFromClass(src.first.from_class); + elem.setToClass(src.first.to_class); + elem.setDeltaX(src.first.delta_x); + elem.setDeltaY(src.first.delta_y); + + elem.setDelay(src.second); + } + + writeMessageToFile(file, &builder); +#endif +} diff --git a/vpr/src/place/delay_model/override_delay_model.h b/vpr/src/place/delay_model/override_delay_model.h new file mode 100644 index 00000000000..e7d71c72318 --- /dev/null +++ b/vpr/src/place/delay_model/override_delay_model.h @@ -0,0 +1,112 @@ + +#pragma once + +#include "place_delay_model.h" +#include "delta_delay_model.h" + +class OverrideDelayModel : public PlaceDelayModel { + public: + OverrideDelayModel(float min_cross_layer_delay, + bool is_flat) + : cross_layer_delay_(min_cross_layer_delay) + , is_flat_(is_flat) {} + + void compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) override; + + /** + * @brief returns delay from the specified (x,y) to the specified (x,y) with both endpoints on layer_num and the + * specified from and to pins + */ + float delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const override; + + void dump_echo(std::string filepath) const override; + + void read(const std::string& file) override; + void write(const std::string& file) const override; + + public: //Mutators + void set_base_delay_model(std::unique_ptr base_delay_model); + const DeltaDelayModel* base_delay_model() const; + float get_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y) const; + void set_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y, float delay); + + private: + std::unique_ptr base_delay_model_; + /// Minimum delay of cross-layer connections + float cross_layer_delay_; + + /// Indicates whether the router is a two-stage or run-flat + bool is_flat_; + + void compute_override_delay_model_(RouterDelayProfiler& router, + const t_router_opts& router_opts); + + /** + * @brief Structure that allows delays to be queried from the delay model. + * + * Delay is calculated given the origin physical tile, the origin + * pin, the destination physical tile, and the destination pin. + * This structure encapsulates all these information. + * + * @param from_type, to_type + * Physical tile index (for easy array access) + * @param from_class, to_class + * The class that the pins belongs to. + * @param to_x, to_y + * The horizontal and vertical displacement + * between two physical tiles. + */ + struct t_override { + short from_type; + short to_type; + short from_class; + short to_class; + short delta_x; + short delta_y; + + /** + * @brief Comparison operator designed for performance. + * + * Operator< is important since t_override serves as the key into the + * map structure delay_overrides_. A default comparison operator would + * not be inlined by the compiler. + * + * A combination of ALWAYS_INLINE attribute and std::lexicographical_compare + * is required for operator< to be inlined by compiler. Proper inlining of + * the function reduces place time by around 5%. + * + * For more information: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1225 + */ + friend ALWAYS_INLINE bool operator<(const t_override& lhs, const t_override& rhs) { + const short* left = reinterpret_cast(&lhs); + const short* right = reinterpret_cast(&rhs); + constexpr size_t NUM_T_OVERRIDE_MEMBERS = sizeof(t_override) / sizeof(short); + return std::lexicographical_compare(left, left + NUM_T_OVERRIDE_MEMBERS, right, right + NUM_T_OVERRIDE_MEMBERS); + } + }; + + /** + * @brief Map data structure that returns delay values according to + * specific delay model queries. + * + * Delay model queries are provided by the t_override structure, which + * encapsulates the information regarding the origin and the destination. + */ + vtr::flat_map2 delay_overrides_; + + /** + * operator< treats memory layout of t_override as an array of short. + * This requires all members of t_override are shorts and there is no + * padding between members of t_override. + */ + static_assert(sizeof(t_override) == sizeof(t_override::from_type) + sizeof(t_override::to_type) + sizeof(t_override::from_class) + sizeof(t_override::to_class) + sizeof(t_override::delta_x) + sizeof(t_override::delta_y), "Expect t_override to have a memory layout equivalent to an array of short (no padding)"); + static_assert(sizeof(t_override::from_type) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::to_type) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::from_class) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::to_class) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::delta_x) == sizeof(short), "Expect all t_override data members to be shorts"); + static_assert(sizeof(t_override::delta_y) == sizeof(short), "Expect all t_override data members to be shorts"); +}; diff --git a/vpr/src/place/delay_model/place_delay_model.cpp b/vpr/src/place/delay_model/place_delay_model.cpp new file mode 100644 index 00000000000..6ff7ad3a0cf --- /dev/null +++ b/vpr/src/place/delay_model/place_delay_model.cpp @@ -0,0 +1,78 @@ +/** + * @file place_delay_model.cpp + * @brief This file implements all the class methods and individual + * routines related to the placer delay model. + */ + +#include "place_delay_model.h" + +#include "globals.h" +#include "physical_types_util.h" +#include "placer_state.h" +#include "vpr_error.h" + +/** + * @brief Returns the delay of one point to point connection. + * + * Only estimate delay for signals routed through the inter-block routing network. + * TODO: Do how should we compute the delay for globals. "Global signals are assumed to have zero delay." + */ +float comp_td_single_connection_delay(const PlaceDelayModel* delay_model, + const vtr::vector_map& block_locs, + ClusterNetId net_id, + int ipin) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + + float delay_source_to_sink = 0.; + + if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { + ClusterPinId source_pin = cluster_ctx.clb_nlist.net_driver(net_id); + ClusterPinId sink_pin = cluster_ctx.clb_nlist.net_pin(net_id, ipin); + + ClusterBlockId source_block = cluster_ctx.clb_nlist.pin_block(source_pin); + ClusterBlockId sink_block = cluster_ctx.clb_nlist.pin_block(sink_pin); + + int source_block_ipin = cluster_ctx.clb_nlist.pin_logical_index(source_pin); + int sink_block_ipin = cluster_ctx.clb_nlist.pin_logical_index(sink_pin); + + t_pl_loc source_block_loc = block_locs[source_block].loc; + t_pl_loc sink_block_loc = block_locs[sink_block].loc; + + /** + * This heuristic only considers delta_x and delta_y, a much better + * heuristic would be to to create a more comprehensive lookup table. + * + * In particular this approach does not accurately capture the effect + * of fast carry-chain connections. + */ + delay_source_to_sink = delay_model->delay({source_block_loc.x, source_block_loc.y, source_block_loc.layer}, source_block_ipin, + {sink_block_loc.x, sink_block_loc.y, sink_block_loc.layer}, sink_block_ipin); + if (delay_source_to_sink < 0) { + VPR_ERROR(VPR_ERROR_PLACE, + "in comp_td_single_connection_delay: Bad delay_source_to_sink value %g from %s (at %d,%d,%d) to %s (at %d,%d,%d)\n" + "in comp_td_single_connection_delay: Delay is less than 0\n", + block_type_pin_index_to_name(physical_tile_type(source_block_loc), source_block_ipin, false).c_str(), + source_block_loc.x, source_block_loc.y, source_block_loc.layer, + block_type_pin_index_to_name(physical_tile_type(sink_block_loc), sink_block_ipin, false).c_str(), + sink_block_loc.x, sink_block_loc.y, sink_block_loc.layer, + delay_source_to_sink); + } + } + + return (delay_source_to_sink); +} + +///@brief Recompute all point to point delays, updating `connection_delay` matrix. +void comp_td_connection_delays(const PlaceDelayModel* delay_model, + PlacerState& placer_state) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + auto& p_timing_ctx = placer_state.mutable_timing(); + auto& block_locs = placer_state.block_locs(); + auto& connection_delay = p_timing_ctx.connection_delay; + + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { + for (size_t ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net_id).size(); ++ipin) { + connection_delay[net_id][ipin] = comp_td_single_connection_delay(delay_model, block_locs, net_id, ipin); + } + } +} diff --git a/vpr/src/place/delay_model/place_delay_model.h b/vpr/src/place/delay_model/place_delay_model.h new file mode 100644 index 00000000000..ba22125d712 --- /dev/null +++ b/vpr/src/place/delay_model/place_delay_model.h @@ -0,0 +1,76 @@ +/** + * @file place_delay_model.h + * @brief This file contains all the class and function declarations related to + * the placer delay model. For implementations, see place_delay_model.cpp. + */ + +#pragma once + +#include "vtr_ndmatrix.h" +#include "vtr_flat_map.h" +#include "vpr_types.h" +#include "router_delay_profiling.h" + +#ifndef __has_attribute +#define __has_attribute(x) 0 // Compatibility with non-clang compilers. +#endif + +#if defined(COMPILER_GCC) && defined(NDEBUG) +#define ALWAYS_INLINE inline __attribute__((__always_inline__)) +#elif defined(COMPILER_MSVC) && defined(NDEBUG) +#define ALWAYS_INLINE __forceinline +#elif __has_attribute(always_inline) +#define ALWAYS_INLINE __attribute__((always_inline)) // clang +#else +#define ALWAYS_INLINE inline +#endif + +///@brief Forward declarations. +class PlaceDelayModel; +class PlacerState; + +///@brief Returns the delay of one point to point connection. +float comp_td_single_connection_delay(const PlaceDelayModel* delay_model, + const vtr::vector_map& block_locs, + ClusterNetId net_id, + int ipin); + +///@brief Recompute all point to point delays, updating `connection_delay` matrix. +void comp_td_connection_delays(const PlaceDelayModel* delay_model, + PlacerState& placer_state); + +///@brief Abstract interface to a placement delay model. +class PlaceDelayModel { + public: + virtual ~PlaceDelayModel() = default; + + ///@brief Computes place delay model. + virtual void compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) = 0; + + /** + * @brief Returns the delay estimate between the specified block pins. + * + * Either compute or read methods must be invoked before invoking delay. + */ + virtual float delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const = 0; + + ///@brief Dumps the delay model to an echo file. + virtual void dump_echo(std::string filename) const = 0; + + /** + * @brief Write place delay model to specified file. + * + * May be unimplemented, in which case method should throw an exception. + */ + virtual void write(const std::string& file) const = 0; + + /** + * @brief Read place delay model from specified file. + * + * May be unimplemented, in which case method should throw an exception. + */ + virtual void read(const std::string& file) = 0; +}; diff --git a/vpr/src/place/delay_model/simple_delay_model.cpp b/vpr/src/place/delay_model/simple_delay_model.cpp new file mode 100644 index 00000000000..04d94b0fbac --- /dev/null +++ b/vpr/src/place/delay_model/simple_delay_model.cpp @@ -0,0 +1,132 @@ + +#include "simple_delay_model.h" + +#ifdef VTR_ENABLE_CAPNPROTO +#include "capnp/serialize.h" +#include "place_delay_model.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" +#endif // VTR_ENABLE_CAPNPROTO + +void SimpleDelayModel::compute(RouterDelayProfiler& route_profiler, + const t_placer_opts& /*placer_opts*/, + const t_router_opts& /*router_opts*/, + int /*longest_length*/) { + const auto& grid = g_vpr_ctx.device().grid; + const size_t num_physical_tile_types = g_vpr_ctx.device().physical_tile_types.size(); + const size_t num_layers = grid.get_num_layers(); + + // Initializing the delay matrix to [num_physical_types][num_layers][num_layers][width][height] + // The second index related to the layer that the source location is on and the third index is for the sink layer + delays_ = vtr::NdMatrix({num_physical_tile_types, + num_layers, + num_layers, + grid.width(), + grid.height()}); + + for (size_t physical_tile_type_idx = 0; physical_tile_type_idx < num_physical_tile_types; ++physical_tile_type_idx) { + for (size_t from_layer = 0; from_layer < num_layers; ++from_layer) { + for (size_t to_layer = 0; to_layer < num_layers; ++to_layer) { + for (size_t dx = 0; dx < grid.width(); ++dx) { + for (size_t dy = 0; dy < grid.height(); ++dy) { + float min_delay = route_profiler.get_min_delay(physical_tile_type_idx, + from_layer, + to_layer, + dx, + dy); + delays_[physical_tile_type_idx][from_layer][to_layer][dx][dy] = min_delay; + } + } + } + } + } +} + +float SimpleDelayModel::delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const { + int delta_x = std::abs(from_loc.x - to_loc.x); + int delta_y = std::abs(from_loc.y - to_loc.y); + + int from_tile_idx = g_vpr_ctx.device().grid.get_physical_type(from_loc)->index; + return delays_[from_tile_idx][from_loc.layer_num][to_loc.layer_num][delta_x][delta_y]; +} + +void SimpleDelayModel::read(const std::string& file) { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "SimpleDelayModel::read is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + // MmapFile object creates an mmap of the specified path, and will munmap + // when the object leaves scope. + MmapFile f(file); + + /* Increase reader limit to 1G words to allow for large files. */ + ::capnp::ReaderOptions opts = default_large_capnp_opts(); + + // FlatArrayMessageReader is used to read the message from the data array + // provided by MmapFile. + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); + + // When reading capnproto files the Reader object to use is named + // ::Reader. + // + // Initially this object is an empty VprDeltaDelayModel. + VprDeltaDelayModel::Reader model; + + // The reader.getRoot performs a cast from the generic capnproto to fit + // with the specified schema. + // + // Note that capnproto does not validate that the incoming data matches the + // schema. If this property is required, some form of check would be + // required. + model = reader.getRoot(); + + auto toFloat = [](float* out, const VprFloatEntry::Reader& in) -> void { + *out = in.getValue(); + }; + + // ToNdMatrix is a generic function for converting a Matrix capnproto + // to a vtr::NdMatrix. + // + // The user must supply the matrix dimension (5 in this case), the source + // capnproto type (VprFloatEntry), + // target C++ type (flat), and a function to convert from the source capnproto + // type to the target C++ type (ToFloat). + // + // The second argument should be of type Matrix::Reader where X is the + // capnproto element type. + ToNdMatrix<5, VprFloatEntry, float>(&delays_, model.getDelays(), toFloat); +#endif +} + +void SimpleDelayModel::write(const std::string& file) const { +#ifndef VTR_ENABLE_CAPNPROTO + (void)file; + VPR_THROW(VPR_ERROR_PLACE, + "SimpleDelayModel::write is disabled because VTR_ENABLE_CAPNPROTO=OFF. " + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable."); +#else + // MallocMessageBuilder object generates capnproto message builder, + // using malloc for buffer allocation. + ::capnp::MallocMessageBuilder builder; + + // initRoot returns a X::Builder object that can be used to set the + // fields in the message. + auto model = builder.initRoot(); + + auto fromFloat = [](VprFloatEntry::Builder* out, const float& in) -> void { + out->setValue(in); + }; + + // FromNdMatrix is a generic function for converting a vtr::NdMatrix to a + // Matrix message. It is the mirror function of ToNdMatrix described in + // read above. + auto delay_values = model.getDelays(); + FromNdMatrix<5, VprFloatEntry, float>(&delay_values, delays_, fromFloat); + + // writeMessageToFile writes message to the specified file. + writeMessageToFile(file, &builder); +#endif +} diff --git a/vpr/src/place/delay_model/simple_delay_model.h b/vpr/src/place/delay_model/simple_delay_model.h new file mode 100644 index 00000000000..0a7ace6aece --- /dev/null +++ b/vpr/src/place/delay_model/simple_delay_model.h @@ -0,0 +1,39 @@ + +#pragma once + +#include "place_delay_model.h" + +/** + * @class SimpleDelayModel + * @brief A simple delay model based on the information stored in router lookahead + * This is in contrast to other placement delay models that get the cost of getting from one location to another by running the router + */ +class SimpleDelayModel : public PlaceDelayModel { + public: + SimpleDelayModel() {} + + /// @brief Use the information in the router lookahead to fill the delay matrix instead of running the router + void compute(RouterDelayProfiler& router, + const t_placer_opts& placer_opts, + const t_router_opts& router_opts, + int longest_length) override; + + float delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const override; + + void dump_echo(std::string /*filepath*/) const override {} + + void read(const std::string& /*file*/) override; + void write(const std::string& /*file*/) const override; + + private: + /** + * @brief The matrix to store the minimum delay between different points on different layers. + * + *The matrix used to store delay information is a 5D matrix. This data structure stores the minimum delay for each tile type on each layer to other layers + *for each dx and dy. We decided to separate the delay for each physical type on each die to accommodate cases where the connectivity of a physical type differs + *on each layer. Additionally, instead of using d_layer, we distinguish between the destination layer to handle scenarios where connectivity between layers + *is not uniform. For example, if the number of inter-layer connections between layer 1 and 2 differs from the number of connections between layer 0 and 1. + *One might argue that this variability could also occur for dx and dy. However, we are operating under the assumption that the FPGA fabric architecture is regular. + */ + vtr::NdMatrix delays_; // [0..num_physical_type-1][0..num_layers-1][0..num_layers-1][0..max_dx][0..max_dy] +}; diff --git a/vpr/src/place/grid_tile_lookup.cpp b/vpr/src/place/grid_tile_lookup.cpp index d2236fdbc8a..45aad729647 100644 --- a/vpr/src/place/grid_tile_lookup.cpp +++ b/vpr/src/place/grid_tile_lookup.cpp @@ -1,12 +1,11 @@ #include "grid_tile_lookup.h" +#include "physical_types_util.h" -GridTileLookup::GridTileLookup() { +GridTileLookup::GridTileLookup() + : max_placement_locations(g_vpr_ctx.device().logical_block_types.size()) { const auto& device_ctx = g_vpr_ctx.device(); const int num_layers = device_ctx.grid.get_num_layers(); - //Will store the max number of tile locations for each logical block type - max_placement_locations.resize(device_ctx.logical_block_types.size()); - for (const auto& type : device_ctx.logical_block_types) { vtr::NdMatrix type_count({static_cast(num_layers), device_ctx.grid.width(), device_ctx.grid.height()}); fill_type_matrix(&type, type_count); @@ -85,7 +84,7 @@ int GridTileLookup::region_tile_count(const Region& reg, t_logical_block_type_pt 0, n_layers - 1); Region intersect_reg = intersection(reg, grid_reg); -// VTR_ASSERT(intersect_coord.layer_num == layer_num); + // VTR_ASSERT(intersect_coord.layer_num == layer_num); const auto [xmin, ymin, xmax, ymax] = intersect_reg.get_rect().coordinates(); const auto [layer_low, layer_high] = intersect_reg.get_layer_range(); diff --git a/vpr/src/place/grid_tile_lookup.h b/vpr/src/place/grid_tile_lookup.h index 66d9d372db3..b155bf99410 100644 --- a/vpr/src/place/grid_tile_lookup.h +++ b/vpr/src/place/grid_tile_lookup.h @@ -5,86 +5,86 @@ #include "globals.h" /** -* @class GridTileLookup -* @brief This class is used to store a grid for each logical block type that stores the cumulative number of subtiles -* for that type available at each location in the grid. -* -* The cumulative number of subtiles is the subtiles at the location plus the subtiles available at the grid locations -* above and to the right of the locations. Having these grids allows for O(1) lookups about the number of subtiles -* available for a given type of block in a rectangular region. -* This lookup class is used during initial placement when sorting blocks by the size of their floorplan constraint regions. -*/ + * @class GridTileLookup + * @brief This class is used to store a grid for each logical block type that stores the cumulative number of subtiles + * for that type available at each location in the grid. + * + * The cumulative number of subtiles is the subtiles at the location plus the subtiles available at the grid locations + * above and to the right of the locations. Having these grids allows for O(1) lookups about the number of subtiles + * available for a given type of block in a rectangular region. + * This lookup class is used during initial placement when sorting blocks by the size of their floorplan constraint regions. + */ class GridTileLookup { - public: - /** - * @brief Constructs a new GridTileLookup object. - * - * Creates a grid for each logical type and fills it with the cumulative number - * of subtiles of that type. - */ - GridTileLookup(); + public: + /** + * @brief Constructs a new GridTileLookup object. + * + * Creates a grid for each logical type and fills it with the cumulative number + * of subtiles of that type. + */ + GridTileLookup(); - /** - * @brief Returns the number of subtiles available in the specified region for the given block type. - * - * This routine uses pre-computed values from the grids for each block type to get the number of grid tiles - * covered by a region. - * For a region with no subtiles specified, the number of grid tiles can be calculated by adding - * and subtracting four values from within/at the edge of the region. - * The region with subtile case is taken care of by a helper routine, region_with_subtile_count(). - * - * @param reg The region to be queried. - * @param block_type The type of logical block. - * @return int The number of available subtiles. - */ - int region_tile_count(const Region& reg, t_logical_block_type_ptr block_type) const; + /** + * @brief Returns the number of subtiles available in the specified region for the given block type. + * + * This routine uses pre-computed values from the grids for each block type to get the number of grid tiles + * covered by a region. + * For a region with no subtiles specified, the number of grid tiles can be calculated by adding + * and subtracting four values from within/at the edge of the region. + * The region with subtile case is taken care of by a helper routine, region_with_subtile_count(). + * + * @param reg The region to be queried. + * @param block_type The type of logical block. + * @return int The number of available subtiles. + */ + int region_tile_count(const Region& reg, t_logical_block_type_ptr block_type) const; - /** - * @brief Returns the number of subtiles that can be placed in the specified region for the given block type. - * - * This routine is for the subtile specified case; an O(region_size) scan needs to be done to check whether each grid - * location in the region is compatible for the block at the subtile specified. - * - * @param reg The region to be queried. - * @param block_type The type of logical block. - * @return int The number of subtiles with placement. - */ - int region_with_subtile_count(const Region& reg, t_logical_block_type_ptr block_type) const; + /** + * @brief Returns the number of subtiles that can be placed in the specified region for the given block type. + * + * This routine is for the subtile specified case; an O(region_size) scan needs to be done to check whether each grid + * location in the region is compatible for the block at the subtile specified. + * + * @param reg The region to be queried. + * @param block_type The type of logical block. + * @return int The number of subtiles with placement. + */ + int region_with_subtile_count(const Region& reg, t_logical_block_type_ptr block_type) const; - /** - * @brief Returns the total number of tiles available for the specified block type. - * - * @param block_type The type of logical block. - * @return int The total number of available tiles. - */ - int total_type_tiles(t_logical_block_type_ptr block_type) const; + /** + * @brief Returns the total number of tiles available for the specified block type. + * + * @param block_type The type of logical block. + * @return int The total number of available tiles. + */ + int total_type_tiles(t_logical_block_type_ptr block_type) const; - private: - /** - * @brief Fills the type matrix with cumulative subtiles count for the given block type. - * - * @param block_type The type of logical block. - * @param type_count The matrix to be filled with cumulative subtiles count. - */ - void fill_type_matrix(t_logical_block_type_ptr block_type, vtr::NdMatrix& type_count); + private: + /** + * @brief Fills the type matrix with cumulative subtiles count for the given block type. + * + * @param block_type The type of logical block. + * @param type_count The matrix to be filled with cumulative subtiles count. + */ + void fill_type_matrix(t_logical_block_type_ptr block_type, vtr::NdMatrix& type_count); - /** - * @brief Stores the cumulative total of subtiles available at each (x, y) location in each layer - * for all block types. - * - * Therefore, the length of the vector will be the number of logical block types. To access the cumulative - * number of subtiles at a location in a specific layer, you would use block_type_matrices[iblock_type][layer][x][y]. - * This would give the number of placement locations that are at, or above (larger y) and to the right of the given [x,y] for - * the given block type in the given layer. - */ - std::vector> block_type_matrices; + /** + * @brief Stores the cumulative total of subtiles available at each (x, y) location in each layer + * for all block types. + * + * Therefore, the length of the vector will be the number of logical block types. To access the cumulative + * number of subtiles at a location in a specific layer, you would use block_type_matrices[iblock_type][layer][x][y]. + * This would give the number of placement locations that are at, or above (larger y) and to the right of the given [x,y] for + * the given block type in the given layer. + */ + std::vector> block_type_matrices; - /** - * @brief Stores the total number of placement locations (i.e. compatible subtiles) for each block type. - * - * To access the max_placement locations for a particular block type, use max_placement_locations[block_type->index] - */ - std::vector max_placement_locations; + /** + * @brief Stores the total number of placement locations (i.e. compatible subtiles) for each block type. + * + * To access the max_placement locations for a particular block type, use max_placement_locations[block_type->index] + */ + std::vector max_placement_locations; }; -#endif /* VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ */ \ No newline at end of file +#endif /* VPR_SRC_PLACE_GRID_TILE_LOOKUP_H_ */ diff --git a/vpr/src/place/initial_noc_placement.cpp b/vpr/src/place/initial_noc_placement.cpp index df1352c98ec..2c97ee4f788 100644 --- a/vpr/src/place/initial_noc_placement.cpp +++ b/vpr/src/place/initial_noc_placement.cpp @@ -1,6 +1,7 @@ #include "initial_noc_placment.h" +#include "place_macro.h" #include "vpr_types.h" #include "initial_placement.h" #include "noc_place_utils.h" @@ -66,6 +67,7 @@ static void place_noc_routers_randomly(std::vector& unfixed_rout */ static void noc_routers_anneal(const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng); @@ -210,6 +212,7 @@ static void place_noc_routers_randomly(std::vector& unfixed_rout static void noc_routers_anneal(const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng) { auto& noc_ctx = g_vpr_ctx.noc(); @@ -276,6 +279,7 @@ static void noc_routers_anneal(const t_noc_opts& noc_opts, e_create_move create_move_outcome = propose_router_swap(blocks_affected, r_lim_decayed, blk_loc_registry, + place_macros, rng); if (create_move_outcome != e_create_move::ABORT) { @@ -311,9 +315,10 @@ static void noc_routers_anneal(const t_noc_opts& noc_opts, void initial_noc_placement(const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng) { - vtr::ScopedStartFinishTimer timer("Initial NoC Placement"); + vtr::ScopedStartFinishTimer timer("Initial NoC Placement"); auto& noc_ctx = g_vpr_ctx.noc(); const auto& block_locs = blk_loc_registry.block_locs(); @@ -343,7 +348,7 @@ void initial_noc_placement(const t_noc_opts& noc_opts, noc_cost_handler.initial_noc_routing({}); // Run the simulated annealing optimizer for NoC routers - noc_routers_anneal(noc_opts, blk_loc_registry, noc_cost_handler, rng); + noc_routers_anneal(noc_opts, blk_loc_registry, place_macros, noc_cost_handler, rng); // check if there is any cycles bool has_cycle = noc_cost_handler.noc_routing_has_cycle(); @@ -352,4 +357,4 @@ void initial_noc_placement(const t_noc_opts& noc_opts, "At least one cycle was found in NoC channel dependency graph. This may cause a deadlock " "when packets wait on each other in a cycle.\n"); } -} \ No newline at end of file +} diff --git a/vpr/src/place/initial_noc_placment.h b/vpr/src/place/initial_noc_placment.h index 79b062909dd..1e62164b549 100644 --- a/vpr/src/place/initial_noc_placment.h +++ b/vpr/src/place/initial_noc_placment.h @@ -5,6 +5,7 @@ struct t_noc_opts; struct t_placer_opts; class BlkLocRegistry; +class PlaceMacros; class NocCostHandler; namespace vtr { @@ -22,6 +23,7 @@ class RngContainer; */ void initial_noc_placement(const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, NocCostHandler& noc_cost_handler, vtr::RngContainer& rng); diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index e6c8f8e09db..aac91e0fd65 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -1,4 +1,11 @@ -#include "vtr_memory.h" +#include "clustered_netlist.h" +#include "flat_placement_types.h" +#include "atom_netlist_fwd.h" +#include "physical_types_util.h" +#include "place_macro.h" +#include "vtr_assert.h" +#include "vtr_geometry.h" +#include "vtr_ndmatrix.h" #include "vtr_random.h" #include "vtr_time.h" #include "vpr_types.h" @@ -13,10 +20,14 @@ #include "move_utils.h" #include "region.h" #include "noc_place_utils.h" +#include "vtr_vector.h" +#include #include +#include +#include #include - +#include #ifdef VERBOSE void print_clb_placement(const char* fname); @@ -31,6 +42,10 @@ static constexpr int SORT_WEIGHT_PER_FAILED_BLOCK = 10; // The amount of weight that will be added to each tile which is outside the floorplanning constraints static constexpr int SORT_WEIGHT_PER_TILES_OUTSIDE_OF_PR = 100; +// The range limit to be used when searching for a neighbor in the centroid placement. +// The neighbor location should be within the defined range to the calculated centroid location. +static constexpr int CENTROID_NEIGHBOR_SEARCH_RLIM = 15; + /** * @brief Control routine for placing a macro. * First iteration of place_marco performs the following steps to place a macro: @@ -38,10 +53,10 @@ static constexpr int SORT_WEIGHT_PER_TILES_OUTSIDE_OF_PR = 100; * 2) try_place_macro_randomly : if no smart location found in the centroid placement, the function tries * to place it randomly for the max number of tries. * 3) try_place_macro_exhaustively : if neither placement algorithms work, the function will find a location - * for the macro by exhaustively searching all available locations. + * for the macro by exhaustively searching all available locations. * If first iteration failed, next iteration calls dense placement for specific block types. - * - * @param macros_max_num_tries Max number of tries for initial placement before switching to exhaustive placement. + * + * @param macros_max_num_tries Max number of tries for initial placement before switching to exhaustive placement. * @param pl_macro The macro to be placed. * @param pad_loc_type Used to check whether an io block needs to be marked as fixed. * @param blk_types_empty_locs_in_grid First location (lowest y) and number of remaining blocks in each column for the blk_id type. @@ -49,7 +64,7 @@ static constexpr int SORT_WEIGHT_PER_TILES_OUTSIDE_OF_PR = 100; * @param blk_loc_registry Placement block location information. To be filled with the location * where pl_macro is placed. * @param rng A random number generator. - * + * * @return true if macro was placed, false if not. */ static bool place_macro(int macros_max_num_tries, @@ -58,6 +73,7 @@ static bool place_macro(int macros_max_num_tries, std::vector* blk_types_empty_locs_in_grid, vtr::vector& block_scores, BlkLocRegistry& blk_loc_registry, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); /* @@ -85,7 +101,7 @@ static int get_y_loc_based_on_macro_direction(t_grid_empty_locs_block_type first * * @param loc The first available location that can place the macro blocks. * @param pl_macro The macro to be placed. - * @param blk_types_empty_locs_in_grid first location (lowest y) and number of remaining blocks in each column for the blk_id type + * @param blk_types_empty_locs_in_grid first location (lowest y) and number of remaining blocks in each column for the blk_id type * * @return index to a column of blk_types_empty_locs_in_grid that can accommodate pl_macro and location of first available location returned by reference */ @@ -97,8 +113,8 @@ static int get_blk_type_first_loc(t_pl_loc& loc, const t_pl_macro& pl_macro, std * @param blk_type_column_index Index to a column in blk_types_empty_locs_in_grid that placed pl_macro in itself. * @param block_type Logical block type of the macro blocks. * @param pl_macro The macro to be placed. - * @param blk_types_empty_locs_in_grid first location (lowest y) and number of remaining blocks in each column for the blk_id type - * + * @param blk_types_empty_locs_in_grid first location (lowest y) and number of remaining blocks in each column for the blk_id type + * */ static void update_blk_type_first_loc(int blk_type_column_index, t_logical_block_type_ptr block_type, @@ -106,10 +122,10 @@ static void update_blk_type_first_loc(int blk_type_column_index, std::vector* blk_types_empty_locs_in_grid); /** - * @brief Initializes empty locations of the grid with a specific block type into vector for dense initial placement + * @brief Initializes empty locations of the grid with a specific block type into vector for dense initial placement * * @param block_type_index block type index that failed in previous initial placement iterations - * + * * @return first location (lowest y) and number of remaining blocks in each column for the block_type_index */ static std::vector init_blk_types_empty_locations(int block_type_index); @@ -129,19 +145,38 @@ static inline void fix_IO_block_types(const t_pl_macro& pl_macro, vtr::vector_map& block_locs); /** - * @brief Determine whether a specific macro can be placed in a specific location. - * + * @brief Determine whether a specific macro can be placed in a specific location. + * * @param loc The location at which the macro head member is placed. * @param pr The PartitionRegion of the macro head member - represents its floorplanning constraints, is the size of * the whole chip if the macro is not constrained. * @param block_type Logical block type of the macro head member. - * + * * @return True if the location is legal for the macro head member, false otherwise. */ static bool is_loc_legal(const t_pl_loc& loc, const PartitionRegion& pr, t_logical_block_type_ptr block_type); +/** + * @brief Helper function to choose a subtile in specified location if the type is compatible and an available one exists. + * + * @param centroid The centroid location at which the subtile will be selected using its x, y, and layer. + * @param block_type Logical block type we would like to place here. + * @param block_loc_registry Information on where other blocks have been placed. + * @param pr The PartitionRegion of the block we are trying to place - represents its floorplanning constraints; + * it is the size of the whole chip if the block is not constrained. + * @param rng A random number generator to select a subtile from the available and compatible ones. + * + * @return True if the location is on the chip, legal, and at least one available subtile is found at that location; + * false otherwise. + */ +static bool find_subtile_in_location(t_pl_loc& centroid, + t_logical_block_type_ptr block_type, + const BlkLocRegistry& blk_loc_registry, + const PartitionRegion& pr, + vtr::RngContainer& rng); + /** * @brief Calculates a centroid location for a block based on its placed connections. * @@ -170,6 +205,7 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, static bool find_centroid_neighbor(t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, + int r_lim, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng); @@ -194,12 +230,13 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, e_pad_loc_type pad_loc_type, vtr::vector& block_scores, BlkLocRegistry& blk_loc_registry, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); /** - * @brief Looks for a valid placement location for macro in second iteration, tries to place as many macros as possible in one column - * and avoids fragmenting the available locations in one column. - * + * @brief Looks for a valid placement location for macro in second iteration, tries to place as many macros as possible in one column + * and avoids fragmenting the available locations in one column. + * * @param pl_macro The macro to be placed. * @param pr The PartitionRegion of the macro - represents its floorplanning constraints, is the size of the whole chip if the macro is not * constrained. @@ -220,7 +257,7 @@ static bool try_dense_placement(const t_pl_macro& pl_macro, /** * @brief Tries for MAX_INIT_PLACE_ATTEMPTS times to place all blocks considering their floorplanning constraints and the device size - * + * * @param pad_loc_type Used to check whether an io block needs to be marked as fixed. * @param constraints_file Used to read block locations if any constraints is available. * @param blk_loc_registry Placement block location information. To be filled with the location @@ -232,24 +269,21 @@ static void place_all_blocks(const t_placer_opts& placer_opts, e_pad_loc_type pad_loc_type, const char* constraints_file, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); /** * @brief If any blocks remain unplaced after all initial placement iterations, this routine * throws an error indicating that initial placement can not be done with the current device size or - * floorplanning constraints. - */ -static void check_initial_placement_legality(const vtr::vector_map& block_locs); - -/** - * @brief Fills movable_blocks in global PlacementContext + * floorplanning constraints. */ -static void alloc_and_load_movable_blocks(const vtr::vector_map& block_locs); +static void check_initial_placement_legality(const BlkLocRegistry& blk_loc_registry); -static void check_initial_placement_legality(const vtr::vector_map& block_locs) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_ctx = g_vpr_ctx.placement(); - auto& device_ctx = g_vpr_ctx.device(); +static void check_initial_placement_legality(const BlkLocRegistry& blk_loc_registry) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& device_ctx = g_vpr_ctx.device(); + const auto& block_locs = blk_loc_registry.block_locs(); int unplaced_blocks = 0; @@ -271,14 +305,14 @@ static void check_initial_placement_legality(const vtr::vector_mapindex]; + const auto& type = device_ctx.grid.get_physical_type({centroid.x, centroid.y, centroid.layer}); + const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(type->index); + + //filter out the occupied subtiles + const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); + std::vector available_sub_tiles; + available_sub_tiles.reserve(compatible_sub_tiles.size()); + for (int sub_tile : compatible_sub_tiles) { + t_pl_loc pos = {centroid.x, centroid.y, sub_tile, centroid.layer}; + if (!grid_blocks.block_at_location(pos)) { + available_sub_tiles.push_back(sub_tile); + } + } + + if (!available_sub_tiles.empty()) { + centroid.sub_tile = available_sub_tiles[rng.irand((int)available_sub_tiles.size() - 1)]; + return true; + } + } + + return false; +} + static bool find_centroid_neighbor(t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, + int rlim, const BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; @@ -348,7 +416,7 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, //range limit (rlim) set a limit for the neighbor search in the centroid placement //the neighbor location should be within the defined range to calculated centroid location - int first_rlim = 15; + int first_rlim = rlim; auto search_range = get_compressed_grid_target_search_range(compressed_block_grid, compressed_centroid_loc[centroid_loc_layer_num], @@ -483,19 +551,299 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, return connected_blocks_to_update; } +// TODO: Should this return the unplaced_blocks_to_update_their_score? +static t_flat_pl_loc find_centroid_loc_from_flat_placement(const t_pl_macro& pl_macro, + const FlatPlacementInfo& flat_placement_info) { + // Use the flat placement to compute the centroid of the given macro. + // TODO: Instead of averaging, maybe use MODE (most frequently placed location). + float acc_weight = 0.f; + t_flat_pl_loc centroid({0.0f, 0.0f, 0.0f}); + for (const t_pl_macro_member& member : pl_macro.members) { + const auto& cluster_atoms = g_vpr_ctx.clustering().atoms_lookup[member.blk_index]; + for (AtomBlockId atom_blk_id : cluster_atoms) { + // TODO: We can get away with using less information. + VTR_ASSERT(flat_placement_info.blk_x_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS && flat_placement_info.blk_y_pos[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS && flat_placement_info.blk_layer[atom_blk_id] != FlatPlacementInfo::UNDEFINED_POS && flat_placement_info.blk_sub_tile[atom_blk_id] != FlatPlacementInfo::UNDEFINED_SUB_TILE); + + // Accumulate the x, y, layer, and sub_tile for each atom in each + // member of the macro. Remove the offset so the centroid would be + // where the head macro should be placed to put the members in the + // correct place. + t_flat_pl_loc cluster_offset({(float)member.offset.x, + (float)member.offset.y, + (float)member.offset.layer}); + centroid += flat_placement_info.get_pos(atom_blk_id); + centroid -= cluster_offset; + acc_weight++; + } + } + if (acc_weight > 0.f) { + centroid /= acc_weight; + } + return centroid; +} + +/** + * @brief Returns the L1 distance a cluster at the given flat location would + * need to move to be within the bounds of a tile at the given tile loc. + */ +static inline float get_dist_to_tile(const t_flat_pl_loc& src_flat_loc, + const t_physical_tile_loc& tile_loc, + const DeviceGrid& device_grid) { + // Get the bounds of the tile. + // Note: The get_tile_bb function will not work in this case since it + // subtracts 1 from the width and height. + auto tile_type = device_grid.get_physical_type(tile_loc); + float tile_xmin = tile_loc.x - device_grid.get_width_offset(tile_loc); + float tile_xmax = tile_xmin + tile_type->width; + float tile_ymin = tile_loc.y - device_grid.get_height_offset(tile_loc); + float tile_ymax = tile_ymin + tile_type->height; + + // Get the closest point in the bounding box (including the edges) to + // the src_flat_loc. To do this, we project the point in L1 space. + float proj_x = std::clamp(src_flat_loc.x, tile_xmin, tile_xmax); + float proj_y = std::clamp(src_flat_loc.y, tile_ymin, tile_ymax); + + // Then compute the L1 distance from the src_flat_loc to the projected + // position. This will be the minimum distance this point needs to move. + float dx = std::abs(proj_x - src_flat_loc.x); + float dy = std::abs(proj_y - src_flat_loc.y); + return dx + dy; +} + +/** + * @brief Returns the first available sub_tile (both compatible with the given + * compressed grid and is empty according the the blk_loc_registry) in + * the tile at the given grid_loc. Returns OPEN if no such sub_tile exists. + */ +static inline int get_first_available_sub_tile_at_grid_loc(const t_physical_tile_loc& grid_loc, + const BlkLocRegistry& blk_loc_registry, + const DeviceGrid& device_grid, + const t_compressed_block_grid& compressed_block_grid) { + + // Get the compatible sub-tiles from the compressed grid for this physical + // tile type. + const t_physical_tile_type_ptr phy_type = device_grid.get_physical_type(grid_loc); + const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(phy_type->index); + + // Return the first empty sub-tile from this list. + for (int sub_tile : compatible_sub_tiles) { + if (blk_loc_registry.grid_blocks().is_sub_tile_empty(grid_loc, sub_tile)) { + return sub_tile; + } + } + + // If one cannot be found, return OPEN. + return OPEN; +} + +/** + * @brief Find the nearest compatible location for the given macro as close to + * the src_flat_loc as possible. + * + * This method uses a BFS to find the closest legal location for the macro. + * + * @param src_flat_loc + * The start location of the BFS. This is given as a flat placement to + * allow the search to trade-off different location options. For example, + * if src_loc was (1.6, 1.5), this tells the search that the cluster + * would prefer to be at tile (1, 1), but if it cannot go there and + * it had to go to one of the neighbors, it would prefer to be on the + * right. + * @param block_type + * The logical block type of the macro. + * @param macro + * The macro to place in the location. + * @param blk_loc_registry + * + * @return Returns the closest legal location found. All of the dimensions will + * be OPEN if a locations could not be found. + */ +static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat_loc, + float max_displacement_threshold, + t_logical_block_type_ptr block_type, + const t_pl_macro& pl_macro, + const BlkLocRegistry& blk_loc_registry) { + // This method performs a BFS over the compressed grid. This avoids searching + // locations which obviously cannot implement this macro. + const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + const int num_layers = device_grid.get_num_layers(); + // This method does not support 3D FPGAs yet. The search performed will only + // traverse the same layer as the src_loc. + VTR_ASSERT(num_layers == 1); + constexpr int layer = 0; + + // Get the closest (approximately) compressed location to the src location. + // This does not need to be perfect (in fact I do not think it is), but the + // closer it is, the faster the BFS will find the best solution. + t_physical_tile_loc src_grid_loc(src_flat_loc.x, src_flat_loc.y, src_flat_loc.layer); + const t_physical_tile_loc compressed_src_loc = compressed_block_grid.grid_loc_to_compressed_loc_approx(src_grid_loc); + + // Weighted-BFS search the compressed grid for an empty compatible subtile. + size_t num_rows = compressed_block_grid.get_num_rows(layer); + size_t num_cols = compressed_block_grid.get_num_columns(layer); + vtr::NdMatrix visited({num_cols, num_rows}, false); + float best_dist = std::numeric_limits::max(); + t_pl_loc best_loc(OPEN, OPEN, OPEN, OPEN); + + std::queue loc_queue; + loc_queue.push(compressed_src_loc); + while (!loc_queue.empty()) { + // Pop the top element off the queue. + t_physical_tile_loc loc = loc_queue.front(); + loc_queue.pop(); + + // If this location has already been visited, skip it. + if (visited[loc.x][loc.y]) + continue; + visited[loc.x][loc.y] = true; + + // Get the minimum distance the cluster would need to move (relative to + // its global placement solution) to be within the tile at the given + // location. + // Note: In compressed space, distances are not what they appear. We are + // using the true grid positions to get the truly closest loc. + auto grid_loc = compressed_block_grid.compressed_loc_to_grid_loc(loc); + float grid_dist = get_dist_to_tile(src_flat_loc, grid_loc, device_grid); + // If this distance is worst than the best we have seen. + // NOTE: This prune is always safe (i.e. it will never remove a better + // solution) since this is a spatial graph and our objective is + // positional distance. The un-visitied neighbors of a node should + // have a higher distance than the current node. + if (grid_dist >= best_dist) + continue; + + // If this distance is beyond the max_displacement_threshold, drop this + // location. + if (grid_dist > max_displacement_threshold) + continue; + + // In order to ensure our BFS finds the closest compatible location, we + // traverse compressed grid locations which may not actually be valid + // (i.e. no tile exists there). This is fine, we just need to check for + // them to ensure we never try to put a cluster there. + bool is_valid_compressed_loc = false; + const auto& compressed_col_blk_map = compressed_block_grid.get_column_block_map(loc.x, layer); + if (compressed_col_blk_map.count(loc.y) != 0) + is_valid_compressed_loc = true; + + // If this distance is better than the best we have seen so far, try + // to see if this is a better solution. + if (is_valid_compressed_loc) { + // Get a sub-tile at this location if it is available. + int new_sub_tile = get_first_available_sub_tile_at_grid_loc(grid_loc, + blk_loc_registry, + device_grid, + compressed_block_grid); + if (new_sub_tile != OPEN) { + // If a sub-tile is available, set this to be the first sub-tile + // available and check if this site is legal for this macro. + // Note: We are using the fully legality check here to check for + // floorplanning constraints and compatibility for all + // members of the macro. This prevents some macros being + // placed where they obviously cannot be implemented. + // Note: The check_all_legality flag is poorly named. false means + // that it WILL check all legality... + t_pl_loc new_loc = t_pl_loc(grid_loc.x, grid_loc.y, new_sub_tile, grid_loc.layer_num); + bool site_legal_for_macro = macro_can_be_placed(pl_macro, + new_loc, + false /*check_all_legality*/, + blk_loc_registry); + if (site_legal_for_macro) { + // Update the best solition. + // Note: We need to keep searching since the compressed grid + // may present a location which is closer in compressed + // space earlier than a location which is closer in + // grid space. + best_dist = grid_dist; + best_loc = new_loc; + } + } + } + + // Push the neighbors (in the compressed grid) onto the queue. + // This will push the neighbors left, right, above, and below the current + // location. Some of these locations may not exist or may have already + // been visited. The code above checks for these cases to prevent extra + // work and invalid lookups. This must be done this way to ensure that + // the closest location can be found efficiently. + if (loc.x > 0) { + t_physical_tile_loc new_comp_loc = t_physical_tile_loc(loc.x - 1, + loc.y, + loc.layer_num); + loc_queue.push(new_comp_loc); + } + if (loc.x < (int)num_cols - 1) { + t_physical_tile_loc new_comp_loc = t_physical_tile_loc(loc.x + 1, + loc.y, + loc.layer_num); + loc_queue.push(new_comp_loc); + } + if (loc.y > 0) { + t_physical_tile_loc new_comp_loc = t_physical_tile_loc(loc.x, + loc.y - 1, + loc.layer_num); + loc_queue.push(new_comp_loc); + } + if (loc.y < (int)num_rows - 1) { + t_physical_tile_loc new_comp_loc = t_physical_tile_loc(loc.x, + loc.y + 1, + loc.layer_num); + loc_queue.push(new_comp_loc); + } + } + + return best_loc; +} + static bool try_centroid_placement(const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, vtr::vector& block_scores, BlkLocRegistry& blk_loc_registry, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { auto& block_locs = blk_loc_registry.mutable_block_locs(); t_pl_loc centroid_loc(OPEN, OPEN, OPEN, OPEN); std::vector unplaced_blocks_to_update_their_score; - unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry); + bool found_legal_subtile = false; + + int rlim = CENTROID_NEIGHBOR_SEARCH_RLIM; + if (!flat_placement_info.valid) { + // If a flat placement is not provided, use the centroid of connected + // blocks which have already been placed. + unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry); + found_legal_subtile = find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng); + } else { + // If a flat placement is provided, use the flat placement to get the + // centroid location of the macro. + t_flat_pl_loc centroid_flat_loc = find_centroid_loc_from_flat_placement(pl_macro, flat_placement_info); + // Then find the nearest legal location to this centroid for this macro. + centroid_loc = find_nearest_compatible_loc(centroid_flat_loc, + static_cast(rlim), + block_type, + pl_macro, + blk_loc_registry); + // FIXME: After this point, if the find_nearest_compatible_loc function + // could not find a valid location, then nothing should be able to. + // Also the location it returns will be on the chip and in the PR + // by construction. Could save time by skipping those checks if + // needed. + if (centroid_loc.x == OPEN) { + // If we cannot find a nearest block, fall back on the original + // find_centroid_loc function. + // FIXME: We should really just skip this block and come back + // to it later. We do not want it taking space from + // someone else! + unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry); + found_legal_subtile = find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng); + } else { + found_legal_subtile = true; + } + } //no suggestion was available for this block type if (!is_loc_on_chip({centroid_loc.x, centroid_loc.y, centroid_loc.layer})) { @@ -504,9 +852,8 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, //centroid suggestion was either occupied or does not match block type //try to find a near location that meet these requirements - bool neighbor_legal_loc = false; - if (!is_loc_legal(centroid_loc, pr, block_type)) { - neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, blk_loc_registry, rng); + if (!found_legal_subtile) { + bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, rlim, blk_loc_registry, rng); if (!neighbor_legal_loc) { //no neighbor candidate found return false; } @@ -518,15 +865,6 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, } auto& device_ctx = g_vpr_ctx.device(); - //choose the location's subtile if the centroid location is legal. - //if the location is found within the "find_centroid_neighbor", it already has a subtile - //we don't need to find one again - if (!neighbor_legal_loc) { - const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; - const auto& type = device_ctx.grid.get_physical_type({centroid_loc.x, centroid_loc.y, centroid_loc.layer}); - const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(type->index); - centroid_loc.sub_tile = compatible_sub_tiles[rng.irand((int)compatible_sub_tiles.size() - 1)]; - } int width_offset = device_ctx.grid.get_width_offset({centroid_loc.x, centroid_loc.y, centroid_loc.layer}); int height_offset = device_ctx.grid.get_height_offset({centroid_loc.x, centroid_loc.y, centroid_loc.layer}); VTR_ASSERT(width_offset == 0); @@ -562,7 +900,8 @@ static int get_y_loc_based_on_macro_direction(t_grid_empty_locs_block_type first static void update_blk_type_first_loc(int blk_type_column_index, t_logical_block_type_ptr block_type, - const t_pl_macro& pl_macro, std::vector* blk_types_empty_locs_in_grid) { + const t_pl_macro& pl_macro, + std::vector* blk_types_empty_locs_in_grid) { //check if dense placement could place macro successfully if (blk_type_column_index == -1 || blk_types_empty_locs_in_grid->size() <= (size_t)abs(blk_type_column_index)) { return; @@ -703,7 +1042,6 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, blk_loc_registry, rng); - if (!legal) { //No valid position found return false; @@ -894,6 +1232,7 @@ static bool place_macro(int macros_max_num_tries, std::vector* blk_types_empty_locs_in_grid, vtr::vector& block_scores, BlkLocRegistry& blk_loc_registry, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { const auto& block_locs = blk_loc_registry.block_locs(); ClusterBlockId blk_id = pl_macro.members[0].blk_index; @@ -928,7 +1267,7 @@ static bool place_macro(int macros_max_num_tries, if (!macro_placed) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry centroid placement\n"); - macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, rng); + macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); } VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tMacro is placed: %d\n", macro_placed); // If macro is not placed yet, try to place the macro randomly for the max number of random tries @@ -953,7 +1292,8 @@ static bool place_macro(int macros_max_num_tries, static vtr::vector assign_block_scores(const PlaceMacros& place_macros) { const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& floorplan_ctx = g_vpr_ctx.floorplanning();; + const auto& floorplan_ctx = g_vpr_ctx.floorplanning(); + ; t_block_score score; @@ -993,16 +1333,16 @@ static vtr::vector assign_block_scores(const Plac return block_scores; } - static void place_all_blocks(const t_placer_opts& placer_opts, vtr::vector& block_scores, enum e_pad_loc_type pad_loc_type, const char* constraints_file, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); - const auto& place_macros = blk_loc_registry.place_macros(); auto blocks = cluster_ctx.clb_nlist.blocks(); int number_of_unplaced_blks_in_curr_itr; @@ -1059,7 +1399,14 @@ static void place_all_blocks(const t_placer_opts& placer_opts, blocks_placed_since_heap_update++; - bool block_placed = place_one_block(blk_id, pad_loc_type, &blk_types_empty_locs_in_grid[blk_id_type->index], &block_scores, blk_loc_registry, rng); + bool block_placed = place_one_block(blk_id, + pad_loc_type, + &blk_types_empty_locs_in_grid[blk_id_type->index], + &block_scores, + blk_loc_registry, + place_macros, + flat_placement_info, + rng); //update heap based on update_heap_freq calculated above if (blocks_placed_since_heap_update % (update_heap_freq) == 0) { @@ -1095,117 +1442,386 @@ static void place_all_blocks(const t_placer_opts& placer_opts, } } +/** + * @brief Gets or creates a macro for the given blk_id. + * + * If the block belongs to a macro, this method will return that macro object. + * Note: This code should not create a copy of that macro object. + * + * If the block does not belong to a macro, it will create a "fake" macro that + * only contains the given block. + */ +static inline t_pl_macro get_or_create_macro(ClusterBlockId blk_id, + const PlaceMacros& place_macros) { + // Lookup to see if the block is part of a macro + int imacro = place_macros.get_imacro_from_iblk(blk_id); + + // If the block belongs to a macro, just return it. + if (imacro != -1) { + VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tBelongs to a macro %d\n", imacro); + return place_macros[imacro]; + } + + // If it does not belong to a macro, create a macro with the one block and then pass to the placement routines + // This is done so that the initial placement flow can be the same whether the block belongs to a macro or not + t_pl_macro_member macro_member; + macro_member.blk_index = blk_id; + macro_member.offset = t_pl_offset(0, 0, 0, 0); + t_pl_macro pl_macro; + pl_macro.members.push_back(macro_member); + return pl_macro; +} + bool place_one_block(const ClusterBlockId blk_id, enum e_pad_loc_type pad_loc_type, std::vector* blk_types_empty_locs_in_grid, vtr::vector* block_scores, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { const auto& block_locs = blk_loc_registry.block_locs(); - const auto& place_macros = blk_loc_registry.place_macros(); //Check if block has already been placed if (is_block_placed(blk_id, block_locs)) { return true; } - bool placed_macro = false; + // If this cluster block is contained within a macro, return it. If not + // create a "fake" macro which only contains this block. + t_pl_macro pl_macro = get_or_create_macro(blk_id, place_macros); - //Lookup to see if the block is part of a macro - int imacro = place_macros.get_imacro_from_iblk(blk_id); + // Try to place this macro. + bool placed_macro = place_macro(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, pl_macro, pad_loc_type, blk_types_empty_locs_in_grid, *block_scores, blk_loc_registry, flat_placement_info, rng); - if (imacro != -1) { //If the block belongs to a macro, pass that macro to the placement routines - VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tBelongs to a macro %d\n", imacro); - const t_pl_macro& pl_macro = place_macros[imacro]; - placed_macro = place_macro(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, pl_macro, pad_loc_type, blk_types_empty_locs_in_grid, *block_scores, blk_loc_registry, rng); - } else { - //If it does not belong to a macro, create a macro with the one block and then pass to the placement routines - //This is done so that the initial placement flow can be the same whether the block belongs to a macro or not - t_pl_macro_member macro_member; - macro_member.blk_index = blk_id; - macro_member.offset = t_pl_offset(0, 0, 0, 0); - t_pl_macro pl_macro; - pl_macro.members.push_back(macro_member); - placed_macro = place_macro(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, pl_macro, pad_loc_type, blk_types_empty_locs_in_grid, *block_scores, blk_loc_registry, rng); + // Return the status of the macro placement. + return placed_macro; +} + +static inline float get_flat_variance(const t_pl_macro& macro, + const FlatPlacementInfo& flat_placement_info) { + + // Find the flat centroid location of this macro. Then find the grid location + // that this would be. + t_flat_pl_loc centroid_flat_loc = find_centroid_loc_from_flat_placement(macro, flat_placement_info); + t_physical_tile_loc centroid_grid_loc(centroid_flat_loc.x, + centroid_flat_loc.y, + centroid_flat_loc.layer); + + // Compute the variance. + float num_atoms = 0; + float variance = 0.0f; + for (const t_pl_macro_member& member : macro.members) { + const auto& cluster_atoms = g_vpr_ctx.clustering().atoms_lookup[member.blk_index]; + for (AtomBlockId atom_blk_id : cluster_atoms) { + // Get the atom position, offset by the member offset. This translates + // all atoms to be as if they are in the head position of the macro. + t_flat_pl_loc atom_pos = flat_placement_info.get_pos(atom_blk_id); + t_flat_pl_loc cluster_offset({(float)member.offset.x, + (float)member.offset.y, + (float)member.offset.layer}); + atom_pos -= cluster_offset; + + // Get the amount this atom needs to be displaced in order to be + // within the same tile as the centroid. + float dist = get_dist_to_tile(atom_pos, centroid_grid_loc, g_vpr_ctx.device().grid); + + // Accumulate the variance. + variance += (dist * dist); + num_atoms++; + } + } + if (num_atoms > 0.f) { + variance /= num_atoms; } + return variance; +} - return placed_macro; +/** + * @brief Print the status header for the AP initial placer. + */ +static void print_ap_initial_placer_header() { + VTR_LOG("---- ---------- ---------- -------------\n"); + VTR_LOG("Pass Max Displ. Num Blocks Num Blocks \n"); + VTR_LOG(" Threshold Placed Left Unplaced\n"); + VTR_LOG("---- ---------- ---------- -------------\n"); } -static void alloc_and_load_movable_blocks(const vtr::vector_map& block_locs) { - auto& place_ctx = g_vpr_ctx.mutable_placement(); - const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& device_ctx = g_vpr_ctx.device(); +/** + * @brief Print the status of the current iteration (pass) of the AP initial + * placer. + */ +static void print_ap_initial_placer_status(unsigned iteration, + float max_displacement_threshold, + size_t num_placed, + size_t num_unplaced) { + // Iteration + VTR_LOG("%4u", iteration); - place_ctx.movable_blocks.clear(); - place_ctx.movable_blocks_per_type.clear(); + // Max displacement threshold + VTR_LOG(" %10g", max_displacement_threshold); - size_t n_logical_blocks = device_ctx.logical_block_types.size(); - place_ctx.movable_blocks_per_type.resize(n_logical_blocks); + // Num placed + VTR_LOG(" %10zu", num_placed); - // iterate over all clustered blocks and store block ids of movable ones - for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { - const auto& loc = block_locs[blk_id]; - if (!loc.is_fixed) { - place_ctx.movable_blocks.push_back(blk_id); + // Num unplaced + VTR_LOG(" %13zu", num_unplaced); + + VTR_LOG("\n"); + + fflush(stdout); +} + +/** + * @brief Places all blocks in the clustered netlist as close to the global + * placement produced by the AP flow. + * + * This function will place clusters in passes. In the first pass, it will try + * to place clusters exactly where their global placement is (according to the + * atoms contained in the cluster). In the second pass, all unplaced clusters + * will try to be placed within 1 tile of where they wanted to be placed. + * Subsequent passes will then try to place clusters at exponentially farther + * distances. + * + * The clusters are sorted based on how many clusters are in the macro that + * contains this cluster and the standard deviation of the placement of atoms + * within the cluster. Large macros with low standard deviation will be placed + * first. + */ +static inline void place_all_blocks_ap(enum e_pad_loc_type pad_loc_type, + BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info) { + const ClusteredNetlist& cluster_netlist = g_vpr_ctx.clustering().clb_nlist; + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + + // Create a list of clusters to place. + std::vector clusters_to_place; + clusters_to_place.reserve(cluster_netlist.blocks().size()); + for (ClusterBlockId blk_id : cluster_netlist.blocks()) { + if (!is_block_placed(blk_id, blk_loc_registry.block_locs())) { + clusters_to_place.push_back(blk_id); + } + } + + // Get the max macro size. This is used for scoring macros. + size_t max_macro_size = 1; + for (const t_pl_macro& macro : place_macros.macros()) { + max_macro_size = std::max(max_macro_size, macro.members.size()); + } + + // Sort the list of clusters to place based on some criteria. The clusters + // earlier in the list will get first dibs on where to be placed. + constexpr float macro_size_weight = 1.0f; + constexpr float std_dev_weight = 4.0f; + vtr::vector cluster_score(cluster_netlist.blocks().size(), 0.0f); + for (ClusterBlockId blk_id : cluster_netlist.blocks()) { + // Compute the standard deviation of the positions of all atoms in the + // given macro. This is a measure of how much the atoms "want" to be + // at the centroid location. + t_pl_macro pl_macro = get_or_create_macro(blk_id, place_macros); + float variance = get_flat_variance(pl_macro, flat_placement_info); + float std_dev = std::sqrt(variance); + // Normalize the standard deviation to be a number between 0 and 1. + float normalized_std_dev = std_dev / (std_dev + 1.0f); + + // Get the "size" of the macro. This is the number of members that are + // within the macro, where we consider clusters which are not part of + // macros as having 0 size. Macros tend to be harder to place. + float macro_size = pl_macro.members.size(); + if (place_macros.get_imacro_from_iblk(blk_id) == -1) + macro_size = 0.0f; + // Normalize the macro size to be a number between 0 and 1. + float normalized_macro_size = macro_size / static_cast(max_macro_size); + + // Compute the cost. Clusters wth a higher cost will be placed first. + // Cost is proportional to macro size since larger macros are more + // challenging to place and should be placed earlier if possible. + // Cost is inversly proportional to standard deviation, since clusters + // that contain atoms that all want to be within the same cluster + // should be placed first. + cluster_score[blk_id] = (macro_size_weight * normalized_macro_size) + + (std_dev_weight * (1.0f - normalized_std_dev)); + } + std::stable_sort(clusters_to_place.begin(), clusters_to_place.end(), [&](ClusterBlockId lhs, ClusterBlockId rhs) { + // Sort list such that higher score clusters are placed first. + return cluster_score[lhs] > cluster_score[rhs]; + }); + + // Compute the max L1 distance on the device. If we cannot find a location + // to place a cluster within this distance, then no legal location exists. + float max_distance_on_device = device_grid.width() + device_grid.height(); + + // Print some logging information and the status header. + VTR_LOG("Number of blocks to be placed: %zu\n", clusters_to_place.size()); + VTR_LOG("Max distance on device: %g\n", max_distance_on_device); + print_ap_initial_placer_header(); + + // Iteratively search for legal locations to place blocks. With each + // iteration, we search farther and father away from the global placement + // solution. The idea is to place blocks where they want first, then if they + // cannot be placed we let other blocks try to be placed where they want + // before trying to place the blocks elsewhere. + // + // A list to keep track of the blocks which were unplaced in this iteration. + std::vector unplaced_blocks; + unplaced_blocks.reserve(clusters_to_place.size()); + // The max displacement threshold for the search. We will not search farther + // than this distance when searching for legal location. + // Note: Distance here is the amount we would need to displace the block + // from its global placement solution to be put in the target tile. + float max_displacement_threshold = 0.0f; + float prev_max_displacement_threshold = -1.0f; + size_t iter = 0; + // We stop searching when the previous max_displacement threshold was larger + // than the maximum distance on the device. This implies that the entire device + // was searched. + while (prev_max_displacement_threshold < max_distance_on_device) { + // Early exit. If there is nothing to place in this iteration, just break. + if (clusters_to_place.size() == 0) + break; + + // Try to place each cluster in their cost order. + for (ClusterBlockId blk_to_place : clusters_to_place) { + // If this block is part of a macro, another member of that macro + // may have placed it already. Just skip in that case. + if (is_block_placed(blk_to_place, blk_loc_registry.block_locs())) { + continue; + } - const t_logical_block_type_ptr block_type = cluster_ctx.clb_nlist.block_type(blk_id); - place_ctx.movable_blocks_per_type[block_type->index].push_back(blk_id); + // Get the macro that contains this block, or create a temporary + // macro that only contains this block. + t_pl_macro pl_macro = get_or_create_macro(blk_to_place, place_macros); + + // Get the flat centroid location of the macro. + t_flat_pl_loc centroid_flat_loc = find_centroid_loc_from_flat_placement(pl_macro, flat_placement_info); + + // Find a legal, open site closest to the flat cenetroid location + // (within the displacement threshold). + auto block_type = cluster_netlist.block_type(blk_to_place); + t_pl_loc centroid_loc = find_nearest_compatible_loc(centroid_flat_loc, + max_displacement_threshold, + block_type, + pl_macro, + blk_loc_registry); + + // If a location could not be found, add to list of unplaced blocks + // and skip. + if (centroid_loc.x == OPEN) { + unplaced_blocks.push_back(blk_to_place); + continue; + } + + // The find_nearest_compatible_loc function above should only return + // a location which can legally accomodate the macro (if it found a + // location). Double check these to be safe. + VTR_ASSERT_SAFE(!blk_loc_registry.grid_blocks().block_at_location(centroid_loc)); + VTR_ASSERT_SAFE(macro_can_be_placed(pl_macro, centroid_loc, false, blk_loc_registry)); + + // Place the macro + for (const t_pl_macro_member& pl_macro_member : pl_macro.members) { + t_pl_loc member_pos = centroid_loc + pl_macro_member.offset; + ClusterBlockId iblk = pl_macro_member.blk_index; + blk_loc_registry.set_block_location(iblk, member_pos); + } + + // Finally, if the user asked for random pad locations and this is + // an IO block, lock down the macro at this location so the placer + // can't move it. + // TODO: This is not technically "random" since the AP flow is + // choosing good places to put IO blocks based on the GP stage + // of the flow. This should be investigated to see if a more + // random distribution of IO pads are necessary. + fix_IO_block_types(pl_macro, centroid_loc, pad_loc_type, blk_loc_registry.mutable_block_locs()); } + + // Print the status of this iteration for debugging. + print_ap_initial_placer_status(iter, + max_displacement_threshold, + clusters_to_place.size() - unplaced_blocks.size(), + unplaced_blocks.size()); + + // The clusters to place in the next iteration is the unplaced clusters + // from this iteration. Swap these two vectors and clear the unplaced + // blocks to be filled next iteration. + clusters_to_place.swap(unplaced_blocks); + unplaced_blocks.clear(); + + // Update the max displacement threshold. + // We exponentially increase the threshold. We first begin by trying + // to place all the clusters exactly where they want, then we increase + // the threshold from there. The idea is we spend more iterations with + // low displacement values, then rapidly increase it to get a solution + // sooner. + prev_max_displacement_threshold = max_displacement_threshold; + if (max_displacement_threshold == 0.0f) { + max_displacement_threshold = 1.0f; + } else { + max_displacement_threshold *= 2.0f; + } + + // Increase the iteration for status printing. + iter++; } + + // Check if anything has not been placed, if so just crash for now. + // TODO: Should fall back on the original initial placer. Unless there is a + // bug in the code above, it could be that it is challenging to place + // for this circuit. + VTR_ASSERT(clusters_to_place.size() == 0); } void initial_placement(const t_placer_opts& placer_opts, const char* constraints_file, const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, std::optional& noc_cost_handler, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng) { vtr::ScopedStartFinishTimer timer("Initial Placement"); - auto& block_locs = blk_loc_registry.mutable_block_locs(); - const auto& place_macros = blk_loc_registry.place_macros(); - /* Initialize the grid blocks to empty. - * Initialize all the blocks to unplaced. - */ - blk_loc_registry.clear_all_grid_locs(); - - /* Go through cluster blocks to calculate the tightest placement - * floorplan constraint for each constrained block - */ - propagate_place_constraints(place_macros); + // Initialize the block loc registry. + blk_loc_registry.init(); /*Mark the blocks that have already been locked to one spot via floorplan constraints * as fixed, so they do not get moved during initial placement or later during the simulated annealing stage of placement*/ mark_fixed_blocks(blk_loc_registry); - // Compute and store compressed floorplanning constraints - alloc_and_load_compressed_cluster_constraints(); - // read the constraint file and place fixed blocks if (strlen(constraints_file) != 0) { read_constraints(constraints_file, blk_loc_registry); } - if(!placer_opts.read_initial_place_file.empty()) { + if (!placer_opts.read_initial_place_file.empty()) { const auto& grid = g_vpr_ctx.device().grid; read_place(nullptr, placer_opts.read_initial_place_file.c_str(), blk_loc_registry, false, grid); } else { if (noc_opts.noc) { // NoC routers are placed before other blocks - initial_noc_placement(noc_opts, blk_loc_registry, noc_cost_handler.value(), rng); + initial_noc_placement(noc_opts, blk_loc_registry, place_macros, noc_cost_handler.value(), rng); propagate_place_constraints(place_macros); } - //Assign scores to blocks and placement macros according to how difficult they are to place - vtr::vector block_scores = assign_block_scores(place_macros); - //Place all blocks - place_all_blocks(placer_opts, block_scores, placer_opts.pad_loc_type, constraints_file, blk_loc_registry, rng); + if (flat_placement_info.valid) { + place_all_blocks_ap(placer_opts.pad_loc_type, + blk_loc_registry, + place_macros, + flat_placement_info); + } else { + //Assign scores to blocks and placement macros according to how difficult they are to place + vtr::vector block_scores = assign_block_scores(place_macros); + + place_all_blocks(placer_opts, block_scores, placer_opts.pad_loc_type, + constraints_file, blk_loc_registry, place_macros, + flat_placement_info, rng); + } } - alloc_and_load_movable_blocks(block_locs); + // Update the movable blocks vectors in the block loc registry. + blk_loc_registry.alloc_and_load_movable_blocks(); // ensure all blocks are placed and that NoC routing has no cycles - check_initial_placement_legality(block_locs); + check_initial_placement_legality(blk_loc_registry); } diff --git a/vpr/src/place/initial_placement.h b/vpr/src/place/initial_placement.h index f2078a3e720..b668ce92075 100644 --- a/vpr/src/place/initial_placement.h +++ b/vpr/src/place/initial_placement.h @@ -11,7 +11,12 @@ class NocCostHandler; #include "vpr_types.h" #include "vtr_vector_map.h" +// Forward declarations class BlkLocRegistry; +class FlatPlacementInfo; +namespace vtr { +class RngContainer; +} // namespace vtr /* The maximum number of tries when trying to place a macro at a * random location before trying exhaustive placement - find the first @@ -74,7 +79,6 @@ bool try_place_macro_randomly(const t_pl_macro& pl_macro, BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng); - /** * @brief Looks for a valid placement location for macro exhaustively once the maximum number of random locations have been tried. * @@ -143,7 +147,9 @@ void initial_placement(const t_placer_opts& placer_opts, const char* constraints_file, const t_noc_opts& noc_opts, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, std::optional& noc_cost_handler, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); /** @@ -164,8 +170,8 @@ bool place_one_block(const ClusterBlockId blk_id, std::vector* blk_types_empty_locs_in_grid, vtr::vector* block_scores, BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, + const FlatPlacementInfo& flat_placement_info, vtr::RngContainer& rng); - - #endif diff --git a/vpr/src/place/move_generators/centroid_move_generator.cpp b/vpr/src/place/move_generators/centroid_move_generator.cpp index 45ba9121719..68850ac6b98 100644 --- a/vpr/src/place/move_generators/centroid_move_generator.cpp +++ b/vpr/src/place/move_generators/centroid_move_generator.cpp @@ -1,4 +1,6 @@ #include "centroid_move_generator.h" +#include "physical_types_util.h" +#include "place_macro.h" #include "vpr_types.h" #include "globals.h" #include "place_constraints.h" @@ -8,19 +10,23 @@ #include CentroidMoveGenerator::CentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) , weighted_(false) , noc_attraction_weight_(0.0f) , noc_attraction_enabled_(false) {} CentroidMoveGenerator::CentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, float noc_attraction_weight, size_t high_fanout_net) - : MoveGenerator(placer_state, reward_function, rng) + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) , noc_attraction_weight_(noc_attraction_weight) , noc_attraction_enabled_(true) { VTR_ASSERT(noc_attraction_weight > 0.0 && noc_attraction_weight <= 1.0); @@ -37,13 +43,13 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block const auto& block_locs = placer_state.block_locs(); const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& place_move_ctx = placer_state.move(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); // Find a movable block based on blk_type ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/false, + /*placer_criticalities=*/nullptr, /*net_from=*/nullptr, /*pin_from=*/nullptr, placer_state, @@ -66,7 +72,7 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block VTR_ASSERT(is_tile_compatible(grid_from_type, cluster_from_type)); t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, + first_rlim, placer_opts.place_dm_rlim}; t_pl_loc to; @@ -82,7 +88,7 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -308,4 +314,4 @@ t_pl_loc CentroidMoveGenerator::calculate_centroid_loc_(ClusterBlockId b_from, centroid.layer = (int)std::round(acc_layer / acc_weight); return centroid; -} \ No newline at end of file +} diff --git a/vpr/src/place/move_generators/centroid_move_generator.h b/vpr/src/place/move_generators/centroid_move_generator.h index 17d5ec82924..f818b03f8fb 100644 --- a/vpr/src/place/move_generators/centroid_move_generator.h +++ b/vpr/src/place/move_generators/centroid_move_generator.h @@ -1,8 +1,9 @@ -#ifndef VPR_CENTROID_MOVE_GEN_H -#define VPR_CENTROID_MOVE_GEN_H +#pragma once #include "move_generator.h" +class PlaceMacros; + /** * @file * @author M. Elgammal @@ -30,6 +31,8 @@ class CentroidMoveGenerator : public MoveGenerator { * of the RL agent. */ CentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -49,12 +52,13 @@ class CentroidMoveGenerator : public MoveGenerator { * ignored when forming NoC groups. */ CentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, float noc_attraction_weight, size_t high_fanout_net); - /** * Returns all NoC routers that are in the NoC group with a given ID. * @param noc_grp_id The NoC group ID whose NoC routers are requested. @@ -128,5 +132,3 @@ class CentroidMoveGenerator : public MoveGenerator { */ void initialize_noc_groups(size_t high_fanout_net); }; - -#endif diff --git a/vpr/src/place/move_generators/critical_uniform_move_generator.cpp b/vpr/src/place/move_generators/critical_uniform_move_generator.cpp index 7a1d39ed308..0a641c30043 100644 --- a/vpr/src/place/move_generators/critical_uniform_move_generator.cpp +++ b/vpr/src/place/move_generators/critical_uniform_move_generator.cpp @@ -1,20 +1,26 @@ + #include "critical_uniform_move_generator.h" + #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" CriticalUniformMoveGenerator::CriticalUniformMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move CriticalUniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, float rlim, const t_placer_opts& placer_opts, - const PlacerCriticalities* /*criticalities*/) { - auto& cluster_ctx = g_vpr_ctx.clustering(); + const PlacerCriticalities* criticalities) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& placer_state = placer_state_.get(); const auto& block_locs = placer_state.block_locs(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); @@ -25,6 +31,7 @@ e_create_move CriticalUniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/true, + criticalities, &net_from, &pin_from, placer_state, @@ -48,7 +55,7 @@ e_create_move CriticalUniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -57,4 +64,3 @@ e_create_move CriticalUniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved return create_move; } - diff --git a/vpr/src/place/move_generators/critical_uniform_move_generator.h b/vpr/src/place/move_generators/critical_uniform_move_generator.h index dd4e5391474..7b8e316e867 100644 --- a/vpr/src/place/move_generators/critical_uniform_move_generator.h +++ b/vpr/src/place/move_generators/critical_uniform_move_generator.h @@ -1,7 +1,8 @@ -#ifndef VPR_CRITICAL_UNIFORM_MOVE_GEN_H -#define VPR_CRITICAL_UNIFORM_MOVE_GEN_H +#pragma once + #include "move_generator.h" -#include "timing_place.h" + +class PlaceMacros; /** * @file @@ -18,6 +19,8 @@ class CriticalUniformMoveGenerator : public MoveGenerator { public: CriticalUniformMoveGenerator() = delete; CriticalUniformMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -28,5 +31,3 @@ class CriticalUniformMoveGenerator : public MoveGenerator { const t_placer_opts& /*placer_opts*/, const PlacerCriticalities* /*criticalities*/) override; }; - -#endif diff --git a/vpr/src/place/move_generators/feasible_region_move_generator.cpp b/vpr/src/place/move_generators/feasible_region_move_generator.cpp index 75210dafd43..bb8de8522e5 100644 --- a/vpr/src/place/move_generators/feasible_region_move_generator.cpp +++ b/vpr/src/place/move_generators/feasible_region_move_generator.cpp @@ -1,7 +1,9 @@ #include "feasible_region_move_generator.h" #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" @@ -9,9 +11,11 @@ #include FeasibleRegionMoveGenerator::FeasibleRegionMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, @@ -20,7 +24,6 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& const PlacerCriticalities* criticalities) { const auto& cluster_ctx = g_vpr_ctx.clustering(); auto& placer_state = placer_state_.get(); - auto& place_move_ctx = placer_state.mutable_move(); const auto& block_locs = placer_state.block_locs(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); @@ -30,6 +33,7 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/true, + criticalities, &net_from, &pin_from, placer_state, @@ -44,18 +48,22 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& //from block data t_pl_loc from = block_locs[b_from].loc; - auto cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); - auto grid_from_type = g_vpr_ctx.device().grid.get_physical_type({from.x, from.y, from.layer}); + t_logical_block_type_ptr cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); + t_physical_tile_type_ptr grid_from_type = g_vpr_ctx.device().grid.get_physical_type({from.x, from.y, from.layer}); VTR_ASSERT(is_tile_compatible(grid_from_type, cluster_from_type)); /* Calculate the feasible region */ t_pl_loc to; // Currently, we don't change the layer for this move to.layer = from.layer; - int max_x, min_x, max_y, min_y; - place_move_ctx.X_coord.clear(); - place_move_ctx.Y_coord.clear(); + int max_x = std::numeric_limits::min(); + int min_x = std::numeric_limits::max(); + int max_y = std::numeric_limits::min(); + int min_y = std::numeric_limits::max(); + + bool found = false; + //For critical input nodes, calculate the x & y min-max values for (ClusterPinId pin_id : cluster_ctx.clb_nlist.block_input_pins(b_from)) { ClusterNetId net_id = cluster_ctx.clb_nlist.pin_net(pin_id); @@ -65,28 +73,25 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& int ipin = cluster_ctx.clb_nlist.pin_net_index(pin_id); if (criticalities->criticality(net_id, ipin) > placer_opts.place_crit_limit) { ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id); - place_move_ctx.X_coord.push_back(block_locs[bnum].loc.x); - place_move_ctx.Y_coord.push_back(block_locs[bnum].loc.y); + const t_pl_loc& loc = block_locs[bnum].loc; + min_x = std::min(min_x, loc.x); + max_x = std::max(max_x, loc.x); + min_y = std::min(min_y, loc.y); + max_y = std::max(max_y, loc.y); + found = true; } } - if (!place_move_ctx.X_coord.empty()) { - max_x = *(std::max_element(place_move_ctx.X_coord.begin(), place_move_ctx.X_coord.end())); - min_x = *(std::min_element(place_move_ctx.X_coord.begin(), place_move_ctx.X_coord.end())); - max_y = *(std::max_element(place_move_ctx.Y_coord.begin(), place_move_ctx.Y_coord.end())); - min_y = *(std::min_element(place_move_ctx.Y_coord.begin(), place_move_ctx.Y_coord.end())); - } else { - max_x = from.x; - min_x = from.x; - max_y = from.y; - min_y = from.y; + + if (!found) { + min_x = max_x = from.x; + min_y = max_y = from.y; } //Get the most critical output of the node - int xt, yt; ClusterBlockId b_output = cluster_ctx.clb_nlist.net_pin_block(net_from, pin_from); t_pl_loc output_loc = block_locs[b_output].loc; - xt = output_loc.x; - yt = output_loc.y; + int xt = output_loc.x; + int yt = output_loc.y; /** * @brief determine the feasible region @@ -124,14 +129,13 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& VTR_ASSERT(FR_coords.ymin <= FR_coords.ymax); t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, + first_rlim, placer_opts.place_dm_rlim}; // Try to find a legal location inside the feasible region if (!find_to_loc_median(cluster_from_type, from, &FR_coords, to, b_from, blk_loc_registry, rng_)) { - /** If there is no legal location in the feasible region, calculate the center of the FR and try to find a legal location - * in a range around this center. - */ + /* If there is no legal location in the feasible region, calculate the center of the FR and try to find a legal location + * in a range around this center. */ t_pl_loc center; center.x = (FR_coords.xmin + FR_coords.xmax) / 2; center.y = (FR_coords.ymin + FR_coords.ymax) / 2; @@ -141,7 +145,7 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -149,4 +153,4 @@ e_create_move FeasibleRegionMoveGenerator::propose_move(t_pl_blocks_to_be_moved& } return create_move; -} \ No newline at end of file +} diff --git a/vpr/src/place/move_generators/feasible_region_move_generator.h b/vpr/src/place/move_generators/feasible_region_move_generator.h index 702f8bdd26c..72e58b17753 100644 --- a/vpr/src/place/move_generators/feasible_region_move_generator.h +++ b/vpr/src/place/move_generators/feasible_region_move_generator.h @@ -1,10 +1,11 @@ -#ifndef VPR_FEASIBLE_REGION_MOVE_GEN_H -#define VPR_FEASIBLE_REGION_MOVE_GEN_H +#pragma once + #include "move_generator.h" -#include "timing_place.h" + +class PlaceMacros; /** - * @brief Feasible Reion (FR) move genrator + * @brief Feasible Region (FR) move generator * * This move was originally defined by Chen et al . in "Simultaneous timing-driven placement and duplication", FPGA 2005 * @@ -22,6 +23,8 @@ class FeasibleRegionMoveGenerator : public MoveGenerator { public: FeasibleRegionMoveGenerator() = delete; FeasibleRegionMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -32,5 +35,3 @@ class FeasibleRegionMoveGenerator : public MoveGenerator { const t_placer_opts& placer_opts, const PlacerCriticalities* criticalities) override; }; - -#endif diff --git a/vpr/src/place/move_generators/manual_move_generator.cpp b/vpr/src/place/move_generators/manual_move_generator.cpp index f320d9ef1ea..cebbe8e8dd6 100644 --- a/vpr/src/place/move_generators/manual_move_generator.cpp +++ b/vpr/src/place/move_generators/manual_move_generator.cpp @@ -12,14 +12,19 @@ #include "manual_move_generator.h" #include "manual_moves.h" +#include "physical_types_util.h" +#include "place_macro.h" #include "placer_state.h" #ifndef NO_GRAPHICS -# include "draw.h" +#include "draw.h" #endif //NO_GRAPHICS -ManualMoveGenerator::ManualMoveGenerator(PlacerState& placer_state, vtr::RngContainer& rng) - : MoveGenerator(placer_state, e_reward_function::UNDEFINED_REWARD, rng) {} +ManualMoveGenerator::ManualMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, + vtr::RngContainer& rng) + : MoveGenerator(placer_state, place_macros, net_cost_handler, e_reward_function::UNDEFINED_REWARD, rng) {} //Manual Move Generator function e_create_move ManualMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, @@ -66,7 +71,6 @@ e_create_move ManualMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); return create_move; } - diff --git a/vpr/src/place/move_generators/manual_move_generator.h b/vpr/src/place/move_generators/manual_move_generator.h index 12c71dc0ce9..417ecb9d514 100644 --- a/vpr/src/place/move_generators/manual_move_generator.h +++ b/vpr/src/place/move_generators/manual_move_generator.h @@ -5,19 +5,11 @@ * @brief Contains the ManualMoveGenerator class. */ -#ifndef VPR_MANUAL_MOVE_GEN_H -#define VPR_MANUAL_MOVE_GEN_H +#pragma once #include "move_generator.h" -#include "median_move_generator.h" -#include "weighted_median_move_generator.h" -#include "weighted_centroid_move_generator.h" -#include "feasible_region_move_generator.h" -#include "uniform_move_generator.h" -#include "critical_uniform_move_generator.h" -#include "centroid_move_generator.h" -#include "simpleRL_move_generator.h" -#include + +class PlaceMacros; /** * @brief Manual Moves Generator, inherits from MoveGenerator class. @@ -27,7 +19,10 @@ class ManualMoveGenerator : public MoveGenerator { public: ManualMoveGenerator() = delete; - ManualMoveGenerator(PlacerState& placer_state, vtr::RngContainer& rng); + ManualMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, + vtr::RngContainer& rng); //Evaluates if move is successful and legal or unable to do. e_create_move propose_move(t_pl_blocks_to_be_moved& blocks_affected, @@ -36,5 +31,3 @@ class ManualMoveGenerator : public MoveGenerator { const t_placer_opts& /*placer_opts*/, const PlacerCriticalities* /*criticalities*/) override; }; - -#endif /*VPR_MANUAL_MOVE_GEN_H */ diff --git a/vpr/src/place/move_generators/median_move_generator.cpp b/vpr/src/place/move_generators/median_move_generator.cpp index 2e982ac6425..f3652d97789 100644 --- a/vpr/src/place/move_generators/median_move_generator.cpp +++ b/vpr/src/place/move_generators/median_move_generator.cpp @@ -1,16 +1,21 @@ #include "median_move_generator.h" #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" +#include "net_cost_handler.h" #include MedianMoveGenerator::MedianMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, @@ -20,7 +25,6 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); auto& placer_state = placer_state_.get(); - auto& place_move_ctx = placer_state.mutable_move(); const auto& block_locs = placer_state.block_locs(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); @@ -28,6 +32,7 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/false, + /*placer_criticalities=*/nullptr, /*net_from=*/nullptr, /*pin_from=*/nullptr, placer_state, @@ -42,7 +47,6 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ const int num_layers = device_ctx.grid.get_num_layers(); - t_pl_loc from = block_locs[b_from].loc; int from_layer = from.layer; auto cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); @@ -57,9 +61,9 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ //clear the vectors that saves X & Y coords //reused to save allocation time - place_move_ctx.X_coord.clear(); - place_move_ctx.Y_coord.clear(); - place_move_ctx.layer_coord.clear(); + X_coord.clear(); + Y_coord.clear(); + layer_coord.clear(); std::vector layer_blk_cnt(num_layers, 0); //true if the net is a feedback from the block to itself @@ -86,10 +90,10 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ t_bb union_bb; const bool cube_bb = g_vpr_ctx.placement().cube_bb; if (!cube_bb) { - union_bb = union_2d_bb(place_move_ctx.layer_bb_coords[net_id]); + union_bb = net_cost_handler_.union_2d_bb(net_id); } - const auto& net_bb_coords = cube_bb ? place_move_ctx.bb_coords[net_id] : union_bb; + const auto& net_bb_coords = cube_bb ? net_cost_handler_.bb_coords(net_id) : union_bb; t_physical_tile_loc old_pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); t_physical_tile_loc new_pin_loc; @@ -112,7 +116,7 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ } else { new_pin_loc.layer_num = net_bb_coords.layer_min; } - + // If the moving block is on the border of the bounding box, we cannot get // the bounding box incrementally. In that case, bounding box should be calculated // from scratch. @@ -123,36 +127,36 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ } } //push the calculated coordinates into X,Y coord vectors - place_move_ctx.X_coord.push_back(coords.xmin); - place_move_ctx.X_coord.push_back(coords.xmax); - place_move_ctx.Y_coord.push_back(coords.ymin); - place_move_ctx.Y_coord.push_back(coords.ymax); - place_move_ctx.layer_coord.push_back(coords.layer_min); - place_move_ctx.layer_coord.push_back(coords.layer_max); + X_coord.push_back(coords.xmin); + X_coord.push_back(coords.xmax); + Y_coord.push_back(coords.ymin); + Y_coord.push_back(coords.ymax); + layer_coord.push_back(coords.layer_min); + layer_coord.push_back(coords.layer_max); } - if ((place_move_ctx.X_coord.empty()) || (place_move_ctx.Y_coord.empty()) || (place_move_ctx.layer_coord.empty())) { + if ((X_coord.empty()) || (Y_coord.empty()) || (layer_coord.empty())) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tMove aborted - X_coord or y_coord or layer_coord are empty\n"); return e_create_move::ABORT; } //calculate the median region - std::stable_sort(place_move_ctx.X_coord.begin(), place_move_ctx.X_coord.end()); - std::stable_sort(place_move_ctx.Y_coord.begin(), place_move_ctx.Y_coord.end()); - std::stable_sort(place_move_ctx.layer_coord.begin(), place_move_ctx.layer_coord.end()); + std::stable_sort(X_coord.begin(), X_coord.end()); + std::stable_sort(Y_coord.begin(), Y_coord.end()); + std::stable_sort(layer_coord.begin(), layer_coord.end()); - limit_coords.xmin = place_move_ctx.X_coord[((place_move_ctx.X_coord.size() - 1) / 2)]; - limit_coords.xmax = place_move_ctx.X_coord[((place_move_ctx.X_coord.size() - 1) / 2) + 1]; + limit_coords.xmin = X_coord[((X_coord.size() - 1) / 2)]; + limit_coords.xmax = X_coord[((X_coord.size() - 1) / 2) + 1]; - limit_coords.ymin = place_move_ctx.Y_coord[((place_move_ctx.Y_coord.size() - 1) / 2)]; - limit_coords.ymax = place_move_ctx.Y_coord[((place_move_ctx.Y_coord.size() - 1) / 2) + 1]; + limit_coords.ymin = Y_coord[((Y_coord.size() - 1) / 2)]; + limit_coords.ymax = Y_coord[((Y_coord.size() - 1) / 2) + 1]; - limit_coords.layer_min = place_move_ctx.layer_coord[((place_move_ctx.layer_coord.size() - 1) / 2)]; - limit_coords.layer_max = place_move_ctx.layer_coord[((place_move_ctx.layer_coord.size() - 1) / 2) + 1]; + limit_coords.layer_min = layer_coord[((layer_coord.size() - 1) / 2)]; + limit_coords.layer_max = layer_coord[((layer_coord.size() - 1) / 2) + 1]; //arrange the different range limiters t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, + first_rlim, placer_opts.place_dm_rlim}; //find a location in a range around the center of median region @@ -165,7 +169,7 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -269,27 +273,24 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, t_physical_tile_loc old_pin_loc, t_physical_tile_loc new_pin_loc) { //TODO: account for multiple physical pin instances per logical pin - const auto& place_move_ctx = placer_state_.get().move(); - t_bb union_bb_edge; t_bb union_bb; const bool cube_bb = g_vpr_ctx.placement().cube_bb; /* Calculating per-layer bounding box is more time-consuming compared to cube bounding box. To speed up - * this move, the bounding box used for this move is of the type cube bounding box even if the per-layer - * bounding box is used by placement SA engine. - * If per-layer bounding box is used, we take a union of bounding boxes on each layer to make a cube bounding box. - * For example, the xmax of this cube bounding box is determined by the maximum x coordinate across all blocks on all layers. - */ + * this move, the bounding box used for this move is of the type cube bounding box even if the per-layer + * bounding box is used by placement SA engine. + * If per-layer bounding box is used, we take a union of bounding boxes on each layer to make a cube bounding box. + * For example, the xmax of this cube bounding box is determined by the maximum x coordinate across all blocks on all layers. + */ if (!cube_bb) { - std::tie(union_bb_edge, union_bb) = union_2d_bb_incr(place_move_ctx.layer_bb_num_on_edges[net_id], - place_move_ctx.layer_bb_coords[net_id]); + std::tie(union_bb_edge, union_bb) = net_cost_handler_.union_2d_bb_incr(net_id); } /* In this move, we use a 3D bounding box. Thus, if per-layer BB is used by placer, we need to take a union of BBs and use that for the rest of * operations in this move */ - const t_bb& curr_bb_edge = cube_bb ? place_move_ctx.bb_num_on_edges[net_id] : union_bb_edge; - const t_bb& curr_bb_coord = cube_bb ? place_move_ctx.bb_coords[net_id] : union_bb; + const t_bb& curr_bb_edge = cube_bb ? net_cost_handler_.bb_num_on_edges(net_id) : union_bb_edge; + const t_bb& curr_bb_coord = cube_bb ? net_cost_handler_.bb_coords(net_id) : union_bb; /* Check if I can update the bounding box incrementally. */ diff --git a/vpr/src/place/move_generators/median_move_generator.h b/vpr/src/place/move_generators/median_move_generator.h index 516fcfb573d..62326cbe145 100644 --- a/vpr/src/place/move_generators/median_move_generator.h +++ b/vpr/src/place/move_generators/median_move_generator.h @@ -1,7 +1,9 @@ -#ifndef VPR_MEDIAN_MOVE_GEN_H -#define VPR_MEDIAN_MOVE_GEN_H +#pragma once + #include "move_generator.h" +class PlaceMacros; + /** * @brief Median move generator * @@ -19,6 +21,8 @@ class MedianMoveGenerator : public MoveGenerator { public: MedianMoveGenerator() = delete; MedianMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -41,11 +45,11 @@ class MedianMoveGenerator : public MoveGenerator { * can be used. Essentially, I am assuming the pins always lie on the outside of the bounding box. * The x and y coordinates are the pin's x and y coordinates. IO blocks are considered to be * one cell in for simplicity. */ - bool get_bb_incrementally(ClusterNetId net_id, t_bb& bb_coord_new, + bool get_bb_incrementally(ClusterNetId net_id, + t_bb& bb_coord_new, t_physical_tile_loc old_pin_loc, t_physical_tile_loc new_pin_loc); - /** * @brief Finds the bounding box of a net and stores its coordinates in the bb_coord_new data structure. * @@ -60,6 +64,12 @@ class MedianMoveGenerator : public MoveGenerator { t_bb& bb_coord_new, ClusterBlockId moving_block_id, bool& skip_net); -}; -#endif + private: + /// Stores x positions to find the median + std::vector X_coord; + /// Stores y positions to find the median + std::vector Y_coord; + /// Stores layer positions to find the median + std::vector layer_coord; +}; diff --git a/vpr/src/place/move_generators/move_generator.cpp b/vpr/src/place/move_generators/move_generator.cpp index fd22e8d8b34..9aa3a527a34 100644 --- a/vpr/src/place/move_generators/move_generator.cpp +++ b/vpr/src/place/move_generators/move_generator.cpp @@ -3,6 +3,8 @@ #include "vpr_error.h" +float MoveGenerator::first_rlim; + void MoveGenerator::calculate_reward_and_process_outcome(const MoveOutcomeStats& move_outcome_stats, double delta_c, float timing_bb_factor) { @@ -34,7 +36,6 @@ void MoveGenerator::calculate_reward_and_process_outcome(const MoveOutcomeStats& process_outcome(-1 * delta_c, reward_func_); break; - case e_reward_function::NON_PENALIZING_BASIC: case e_reward_function::RUNTIME_AWARE: if (delta_c < 0) { @@ -51,7 +52,7 @@ void MoveGenerator::calculate_reward_and_process_outcome(const MoveOutcomeStats& } } -void MoveTypeStat::print_placement_move_types_stats() const { +void MoveTypeStat::print_placement_move_types_stats(const std::vector>& movable_blocks_per_type) const { VTR_LOG("\n\nPlacement perturbation distribution by block and move type: \n"); VTR_LOG( @@ -71,9 +72,9 @@ void MoveTypeStat::print_placement_move_types_stats() const { int num_of_avail_moves = blk_type_moves.size() / device_ctx.logical_block_types.size(); //Print placement information for each block type - for (const auto& itype : device_ctx.logical_block_types) { + for (const t_logical_block_type& itype : device_ctx.logical_block_types) { //Skip non-existing block types in the netlist - if (itype.index == 0 || movable_blocks_per_type(itype).empty()) { + if (itype.index == 0 || movable_blocks_per_type[itype.index].empty()) { continue; } diff --git a/vpr/src/place/move_generators/move_generator.h b/vpr/src/place/move_generators/move_generator.h index e39493e16c6..4f9ed137247 100644 --- a/vpr/src/place/move_generators/move_generator.h +++ b/vpr/src/place/move_generators/move_generator.h @@ -1,13 +1,15 @@ -#ifndef VPR_MOVE_GENERATOR_H -#define VPR_MOVE_GENERATOR_H +#pragma once #include "vpr_types.h" #include "move_utils.h" -#include "timing_place.h" +#include "PlacerCriticalities.h" +#include #include +class PlaceMacros; class PlacerState; +class NetCostHandler; struct MoveOutcomeStats { float delta_cost_norm = std::numeric_limits::quiet_NaN(); @@ -35,9 +37,13 @@ struct MoveTypeStat { vtr::NdMatrix rejected_moves; /** - * @brief Prints placement perturbation distribution by block and move type. + * @brief Prints statistics on the distribution of placement perturbations, + * categorized by block type and move type. + * @param movable_blocks_per_type A vector of vectors, where each inner vector contains ClusterBlockIds of + * all movable blocks belonging to a specific logical type. The outer vector + * is indexed by the logical type index. */ - void print_placement_move_types_stats() const; + void print_placement_move_types_stats(const std::vector>& movable_blocks_per_type) const; inline void incr_blk_type_moves(const t_propose_action& proposed_action) { if (proposed_action.logical_blk_type_index != -1) { //if the agent proposed the block type, then collect the block type stat @@ -65,11 +71,11 @@ struct MoveTypeStat { * @brief enum represents the different reward functions */ enum class e_reward_function { - BASIC, ///@ directly uses the change of the annealing cost function - NON_PENALIZING_BASIC, ///@ same as basic reward function but with 0 reward if it's a hill-climbing one - RUNTIME_AWARE, ///@ same as NON_PENALIZING_BASIC but with normalizing with the runtime factor of each move type - WL_BIASED_RUNTIME_AWARE, ///@ same as RUNTIME_AWARE but more biased to WL cost (the factor of the bias is REWARD_BB_TIMING_RELATIVE_WEIGHT) - UNDEFINED_REWARD ///@ Used for manual moves + BASIC, ///@ directly uses the change of the annealing cost function + NON_PENALIZING_BASIC, ///@ same as basic reward function but with 0 reward if it's a hill-climbing one + RUNTIME_AWARE, ///@ same as NON_PENALIZING_BASIC but with normalizing with the runtime factor of each move type + WL_BIASED_RUNTIME_AWARE, ///@ same as RUNTIME_AWARE but more biased to WL cost (the factor of the bias is REWARD_BB_TIMING_RELATIVE_WEIGHT) + UNDEFINED_REWARD ///@ Used for manual moves }; e_reward_function string_to_reward(const std::string& st); @@ -81,19 +87,26 @@ e_reward_function string_to_reward(const std::string& st); */ class MoveGenerator { public: - /** * @brief Initializes some protected member variables that are used * by inheriting classes. * * @param placer_state A mutable reference to the placement state which will * be stored in this object. + * @param place_macros An immutable reference to the placement macros which + * will be stored in this object. * @param reward_function Specifies the reward function to update q-tables * of the RL agent. * @param rng A random number generator to be used for block and location selection. */ - MoveGenerator(PlacerState& placer_state, e_reward_function reward_function, vtr::RngContainer& rng) + MoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, + e_reward_function reward_function, + vtr::RngContainer& rng) : placer_state_(placer_state) + , place_macros_(place_macros) + , net_cost_handler_(net_cost_handler) , reward_func_(reward_function) , rng_(rng) {} @@ -124,7 +137,7 @@ class MoveGenerator { const PlacerCriticalities* criticalities) = 0; /** - * @brief Recieves feedback about the outcome of the previously proposed move + * @brief Receives feedback about the outcome of the previously proposed move * * This function is very useful for RL agent to get the feedback to the agent * @@ -146,10 +159,22 @@ class MoveGenerator { double delta_c, float timing_bb_factor); + public: + /** + * @brief Initial move range limit for clustered blocks. + * + * @details + * Used by multiple move generators to track annealing progress and adjust behavior. + * Several move generators compare the current range limit with its initial value to + * see if the annealing is in its early or late iterations. + * Since no specific move generators owns this variable, it's been made static. + */ + static float first_rlim; + protected: std::reference_wrapper placer_state_; + const PlaceMacros& place_macros_; + const NetCostHandler& net_cost_handler_; e_reward_function reward_func_; vtr::RngContainer& rng_; }; - -#endif diff --git a/vpr/src/place/move_generators/simpleRL_move_generator.cpp b/vpr/src/place/move_generators/simpleRL_move_generator.cpp index f0ab253c680..12e56704a81 100644 --- a/vpr/src/place/move_generators/simpleRL_move_generator.cpp +++ b/vpr/src/place/move_generators/simpleRL_move_generator.cpp @@ -9,7 +9,6 @@ #include #include - /* File-scope routines */ //a scaled and clipped exponential function static float scaled_clipped_exp(float x) { return std::exp(std::min(1000 * x, float(3.0))); } @@ -37,11 +36,14 @@ void SimpleRLMoveGenerator::process_outcome(double reward, e_reward_function rew * K-Armed bandit agent implementation * * * * */ -KArmedBanditAgent::KArmedBanditAgent(std::vector available_moves, e_agent_space agent_space, vtr::RngContainer& rng) +KArmedBanditAgent::KArmedBanditAgent(std::vector available_moves, + e_agent_space agent_space, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type) : available_moves_(std::move(available_moves)) , propose_blk_type_(agent_space == e_agent_space::MOVE_BLOCK_TYPE) , rng_(rng) { - std::vector available_logical_block_types = get_available_logical_blk_types_(); + std::vector available_logical_block_types = get_available_logical_blk_types_(num_movable_blocks_per_type); num_available_types_ = available_logical_block_types.size(); size_t num_available_moves = available_moves_.size(); @@ -89,7 +91,7 @@ int KArmedBanditAgent::action_to_blk_type_(const size_t action_idx) { } } -std::vector KArmedBanditAgent::get_available_logical_blk_types_() { +std::vector KArmedBanditAgent::get_available_logical_blk_types_(const std::vector& num_movable_blocks_per_type) { const auto& device_ctx = g_vpr_ctx.device(); std::vector available_blk_types; @@ -99,9 +101,9 @@ std::vector KArmedBanditAgent::get_available_logical_blk_types_() { continue; } - const auto& blk_per_type = movable_blocks_per_type(logical_blk_type); + int num_blk_per_type = num_movable_blocks_per_type[logical_blk_type.index]; - if (!blk_per_type.empty()) { + if (num_blk_per_type > 0) { available_blk_types.push_back(logical_blk_type.index); } } @@ -192,8 +194,12 @@ int KArmedBanditAgent::agent_to_phy_blk_type(const int idx) { * E-greedy agent implementation * * * * */ -EpsilonGreedyAgent::EpsilonGreedyAgent(std::vector available_moves, e_agent_space agent_space, float epsilon, vtr::RngContainer& rng) - : KArmedBanditAgent(std::move(available_moves), agent_space, rng) { +EpsilonGreedyAgent::EpsilonGreedyAgent(std::vector available_moves, + e_agent_space agent_space, + float epsilon, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type) + : KArmedBanditAgent(std::move(available_moves), agent_space, rng, num_movable_blocks_per_type) { set_epsilon(epsilon); init_q_scores_(); } @@ -267,16 +273,19 @@ void EpsilonGreedyAgent::set_epsilon_action_prob() { * Softmax agent implementation * * * * */ -SoftmaxAgent::SoftmaxAgent(std::vector available_moves, e_agent_space agent_space, vtr::RngContainer& rng) - : KArmedBanditAgent(std::move(available_moves), agent_space, rng) { - init_q_scores_(); +SoftmaxAgent::SoftmaxAgent(std::vector available_moves, + e_agent_space agent_space, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type) + : KArmedBanditAgent(std::move(available_moves), agent_space, rng, num_movable_blocks_per_type) { + init_q_scores_(num_movable_blocks_per_type); } SoftmaxAgent::~SoftmaxAgent() { if (agent_info_file_) vtr::fclose(agent_info_file_); } -void SoftmaxAgent::init_q_scores_() { +void SoftmaxAgent::init_q_scores_(const std::vector& num_movable_blocks_per_type) { q_ = std::vector(num_available_actions_, 0.); exp_q_ = std::vector(num_available_actions_, 0.); num_action_chosen_ = std::vector(num_available_actions_, 0); @@ -297,7 +306,7 @@ void SoftmaxAgent::init_q_scores_() { * it will use the block ratio to calculate action probability for each q_table entry. */ if (propose_blk_type_) { - set_block_ratio_(); + set_block_ratio_(num_movable_blocks_per_type); } set_action_prob_(); } @@ -320,11 +329,8 @@ t_propose_action SoftmaxAgent::propose_action() { return proposed_action; } -void SoftmaxAgent::set_block_ratio_() { - const auto& place_ctx = g_vpr_ctx.placement(); - size_t num_movable_total_blocks = place_ctx.movable_blocks.size(); - - num_movable_total_blocks = std::max(num_movable_total_blocks, 1); +void SoftmaxAgent::set_block_ratio_(const std::vector& num_movable_blocks_per_type) { + size_t num_movable_total_blocks = std::max(1, std::accumulate(num_movable_blocks_per_type.begin(), num_movable_blocks_per_type.end(), 0)); // allocate enough space for available block types in the netlist block_type_ratio_.resize(num_available_types_); @@ -336,7 +342,7 @@ void SoftmaxAgent::set_block_ratio_() { for (size_t itype = 0; itype < num_available_types_; itype++) { t_logical_block_type blk_type; blk_type.index = agent_to_phy_blk_type(itype); - auto num_blocks = movable_blocks_per_type(blk_type).size(); + int num_blocks = num_movable_blocks_per_type[blk_type.index]; block_type_ratio_[itype] = (float)num_blocks / num_movable_total_blocks; block_type_ratio_[itype] /= available_moves_.size(); } @@ -377,4 +383,4 @@ void SoftmaxAgent::set_action_prob_() { accum += action_prob_[i]; cumm_action_prob_[i] = accum; } -} \ No newline at end of file +} diff --git a/vpr/src/place/move_generators/simpleRL_move_generator.h b/vpr/src/place/move_generators/simpleRL_move_generator.h index eacf736e79b..a3df9f01ac2 100644 --- a/vpr/src/place/move_generators/simpleRL_move_generator.h +++ b/vpr/src/place/move_generators/simpleRL_move_generator.h @@ -1,5 +1,5 @@ -#ifndef VPR_SIMPLERL_MOVE_GEN_H -#define VPR_SIMPLERL_MOVE_GEN_H +#pragma once + #include "move_generator.h" #include "median_move_generator.h" #include "weighted_median_move_generator.h" @@ -9,12 +9,17 @@ #include "critical_uniform_move_generator.h" #include "centroid_move_generator.h" +class PlaceMacros; + /** * @brief KArmedBanditAgent is the base class for RL agents that target the k-armed bandit problems */ class KArmedBanditAgent { public: - KArmedBanditAgent(std::vector available_moves, e_agent_space agent_space, vtr::RngContainer& rng); + KArmedBanditAgent(std::vector available_moves, + e_agent_space agent_space, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type); virtual ~KArmedBanditAgent() = default; /** @@ -84,14 +89,14 @@ class KArmedBanditAgent { inline int agent_to_phy_blk_type(int idx); protected: - float exp_alpha_ = -1; //Step size for q_ updates (< 0 implies use incremental average) - std::vector available_moves_; //All available moves from which the agent can choose - size_t num_available_types_; //Number of block types that exist in the netlist. Agent may not choose the block type. - size_t num_available_actions_; //Total number of available actions - bool propose_blk_type_ = false; //Check if agent should propose both move and block type or only move type - std::vector num_action_chosen_; //Number of times each arm has been pulled (n) - std::vector q_; //Estimated value of each arm (Q) - size_t last_action_; //type of the last action (move type) proposed + float exp_alpha_ = -1; //Step size for q_ updates (< 0 implies use incremental average) + std::vector available_moves_; //All available moves from which the agent can choose + size_t num_available_types_; //Number of block types that exist in the netlist. Agent may not choose the block type. + size_t num_available_actions_; //Total number of available actions + bool propose_blk_type_ = false; //Check if agent should propose both move and block type or only move type + std::vector num_action_chosen_; //Number of times each arm has been pulled (n) + std::vector q_; //Estimated value of each arm (Q) + size_t last_action_; //type of the last action (move type) proposed /* Ratios of the average runtime to calculate each move type */ /* These ratios are useful for different reward functions * * The vector is calculated by averaging many runs on different circuits */ @@ -103,11 +108,13 @@ class KArmedBanditAgent { private: /** * @brief Iterates over all logical block types and check whether they exist in the - * netlist. Then, returns the logical block type indices found in the netlist. - * + * netlist. Then, returns the logical block type indices found in the netlist. + * @param movable_blocks_per_type A vector of vectors, where each inner vector contains ClusterBlockIds of + * all movable blocks belonging to a specific logical type. The outer vector + * is indexed by the logical type index. * @return A vector containing all logical block type indices that exist in the netlist. */ - static std::vector get_available_logical_blk_types_(); + static std::vector get_available_logical_blk_types_(const std::vector& num_movable_blocks_per_type); private: std::vector action_logical_blk_type_; @@ -122,7 +129,11 @@ class KArmedBanditAgent { */ class EpsilonGreedyAgent : public KArmedBanditAgent { public: - EpsilonGreedyAgent(std::vector available_moves, e_agent_space agent_space, float epsilon, vtr::RngContainer& rng); + EpsilonGreedyAgent(std::vector available_moves, + e_agent_space agent_space, + float epsilon, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type); ~EpsilonGreedyAgent() override; t_propose_action propose_action() override; //Returns the type of the next action as well as the block type the agent wishes to perform @@ -161,7 +172,10 @@ class EpsilonGreedyAgent : public KArmedBanditAgent { */ class SoftmaxAgent : public KArmedBanditAgent { public: - SoftmaxAgent(std::vector available_moves, e_agent_space agent_space, vtr::RngContainer& rng); + SoftmaxAgent(std::vector available_moves, + e_agent_space agent_space, + vtr::RngContainer& rng, + const std::vector& num_movable_blocks_per_type); ~SoftmaxAgent() override; t_propose_action propose_action() override; //Returns the type of the next action as well as the block type the agent wishes to perform @@ -169,13 +183,19 @@ class SoftmaxAgent : public KArmedBanditAgent { private: /** * @brief Initialize agent's Q-table and internal variable to zero (RL-agent learns everything throughout the placement run and has no prior knowledge) + * @param movable_blocks_per_type A vector of vectors, where each inner vector contains ClusterBlockIds of + * all movable blocks belonging to a specific logical type. The outer vector + * is indexed by the logical type index. */ - void init_q_scores_(); + void init_q_scores_(const std::vector& num_movable_blocks_per_type); /** * @brief Calculate the fraction of total netlist blocks for each agent block type and will be used by the "set_action_prob" function. + * @param movable_blocks_per_type A vector of vectors, where each inner vector contains ClusterBlockIds of + * all movable blocks belonging to a specific logical type. The outer vector + * is indexed by the logical type index. */ - void set_block_ratio_(); + void set_block_ratio_(const std::vector& num_movable_blocks_per_type); /** * @brief Set action probability for all available actions. @@ -211,12 +231,12 @@ class SimpleRLMoveGenerator : public MoveGenerator { * * @param agent std::unique_ptr to the agent. Only EpsilonGreedyAgent and SoftmaxAgent types are accepted * by the constructor. If other types are passed, a compile error would be thrown. - * - * @param is_multi_layer A boolean value to indicate whether the placement is multi-layer or not */ template::value || std::is_same::value>::type> explicit SimpleRLMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, std::unique_ptr& agent, @@ -236,30 +256,31 @@ class SimpleRLMoveGenerator : public MoveGenerator { template SimpleRLMoveGenerator::SimpleRLMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, std::unique_ptr& agent, float noc_attraction_weight, size_t high_fanout_thresh) - : MoveGenerator(placer_state, reward_function, rng) { + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) { if (noc_attraction_weight > 0.0f) { all_moves.resize((int)e_move_type::NUMBER_OF_AUTO_MOVES); } else { all_moves.resize((int)e_move_type::NUMBER_OF_AUTO_MOVES - 1); } - all_moves[e_move_type::UNIFORM] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::MEDIAN] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::CENTROID] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::W_CENTROID] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::W_MEDIAN] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::CRIT_UNIFORM] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::FEASIBLE_REGION] = std::make_unique(placer_state, reward_function, rng); + all_moves[e_move_type::UNIFORM] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::MEDIAN] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::W_CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::W_MEDIAN] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::CRIT_UNIFORM] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::FEASIBLE_REGION] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); if (noc_attraction_weight > 0.0f) { - all_moves[e_move_type::NOC_ATTRACTION_CENTROID] = std::make_unique(placer_state, reward_function, rng, + all_moves[e_move_type::NOC_ATTRACTION_CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng, noc_attraction_weight, high_fanout_thresh); } karmed_bandit_agent = std::move(agent); } -#endif diff --git a/vpr/src/place/move_generators/static_move_generator.cpp b/vpr/src/place/move_generators/static_move_generator.cpp index 6a3de5b4a2a..bbe9248682c 100644 --- a/vpr/src/place/move_generators/static_move_generator.cpp +++ b/vpr/src/place/move_generators/static_move_generator.cpp @@ -2,6 +2,7 @@ #include "static_move_generator.h" #include "median_move_generator.h" +#include "place_macro.h" #include "weighted_median_move_generator.h" #include "weighted_centroid_move_generator.h" #include "feasible_region_move_generator.h" @@ -13,19 +14,21 @@ #include "vtr_assert.h" StaticMoveGenerator::StaticMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, const vtr::vector& move_probs) - : MoveGenerator(placer_state, reward_function, rng) { + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) { all_moves.resize((int)e_move_type::NUMBER_OF_AUTO_MOVES); - all_moves[e_move_type::UNIFORM] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::MEDIAN] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::CENTROID] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::W_CENTROID] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::W_MEDIAN] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::CRIT_UNIFORM] = std::make_unique(placer_state, reward_function, rng); - all_moves[e_move_type::FEASIBLE_REGION] = std::make_unique(placer_state, reward_function, rng); + all_moves[e_move_type::UNIFORM] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::MEDIAN] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::W_CENTROID] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::W_MEDIAN] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::CRIT_UNIFORM] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); + all_moves[e_move_type::FEASIBLE_REGION] = std::make_unique(placer_state, place_macros_, net_cost_handler_, reward_function, rng); initialize_move_prob(move_probs); } @@ -34,7 +37,7 @@ void StaticMoveGenerator::initialize_move_prob(const vtr::vector> all_moves; // list of pointers to the different available move type generators - vtr::vector cumm_move_probs; // accumulative probabilities for different move types - float total_prob; // sum of the input probabilities from the use + vtr::vector> all_moves; // list of pointers to the different available move type generators + vtr::vector cumm_move_probs; // accumulative probabilities for different move types + float total_prob; // sum of the input probabilities from the use void initialize_move_prob(const vtr::vector& move_probs); public: StaticMoveGenerator() = delete; StaticMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng, const vtr::vector& move_probs); @@ -29,4 +32,3 @@ class StaticMoveGenerator : public MoveGenerator { const t_placer_opts& placer_opts, const PlacerCriticalities* criticalities) override; }; -#endif diff --git a/vpr/src/place/move_generators/uniform_move_generator.cpp b/vpr/src/place/move_generators/uniform_move_generator.cpp index 6c6e283ba94..ebfebca5652 100644 --- a/vpr/src/place/move_generators/uniform_move_generator.cpp +++ b/vpr/src/place/move_generators/uniform_move_generator.cpp @@ -1,14 +1,18 @@ #include "uniform_move_generator.h" #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" UniformMoveGenerator::UniformMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move UniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, @@ -24,6 +28,7 @@ e_create_move UniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/false, + /*placer_criticalities=*/nullptr, /*net_from=*/nullptr, /*pin_from=*/nullptr, placer_state, @@ -60,7 +65,7 @@ e_create_move UniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks VTR_LOG("\n"); #endif - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { diff --git a/vpr/src/place/move_generators/uniform_move_generator.h b/vpr/src/place/move_generators/uniform_move_generator.h index 02414c3140e..f91ff71635b 100644 --- a/vpr/src/place/move_generators/uniform_move_generator.h +++ b/vpr/src/place/move_generators/uniform_move_generator.h @@ -1,7 +1,9 @@ -#ifndef VPR_UNIFORM_MOVE_GEN_H -#define VPR_UNIFORM_MOVE_GEN_H +#pragma once + #include "move_generator.h" +class PlaceMacros; + /** * @brief The classic VPR move generator * @@ -12,6 +14,8 @@ class UniformMoveGenerator : public MoveGenerator { public: UniformMoveGenerator() = delete; UniformMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -22,5 +26,3 @@ class UniformMoveGenerator : public MoveGenerator { const t_placer_opts& /*placer_opts*/, const PlacerCriticalities* /*criticalities*/) override; }; - -#endif diff --git a/vpr/src/place/move_generators/weighted_centroid_move_generator.cpp b/vpr/src/place/move_generators/weighted_centroid_move_generator.cpp index a2b99cb1d86..489d5f0ceb4 100644 --- a/vpr/src/place/move_generators/weighted_centroid_move_generator.cpp +++ b/vpr/src/place/move_generators/weighted_centroid_move_generator.cpp @@ -1,8 +1,11 @@ #include "weighted_centroid_move_generator.h" +#include "place_macro.h" WeightedCentroidMoveGenerator::WeightedCentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : CentroidMoveGenerator(placer_state, reward_function, rng) { + : CentroidMoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) { weighted_ = true; } diff --git a/vpr/src/place/move_generators/weighted_centroid_move_generator.h b/vpr/src/place/move_generators/weighted_centroid_move_generator.h index 9a13ebabf08..8d07a0e6118 100644 --- a/vpr/src/place/move_generators/weighted_centroid_move_generator.h +++ b/vpr/src/place/move_generators/weighted_centroid_move_generator.h @@ -1,8 +1,9 @@ -#ifndef VPR_WEIGHTED_CENTROID_MOVE_GEN_H -#define VPR_WEIGHTED_CENTROID_MOVE_GEN_H +#pragma once #include "centroid_move_generator.h" +class PlaceMacros; + /** * @brief Weighted Centroid move generator * @@ -18,8 +19,8 @@ class WeightedCentroidMoveGenerator : public CentroidMoveGenerator { public: WeightedCentroidMoveGenerator() = delete; WeightedCentroidMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); }; - -#endif diff --git a/vpr/src/place/move_generators/weighted_median_move_generator.cpp b/vpr/src/place/move_generators/weighted_median_move_generator.cpp index b391509f5c3..9588e899fa6 100644 --- a/vpr/src/place/move_generators/weighted_median_move_generator.cpp +++ b/vpr/src/place/move_generators/weighted_median_move_generator.cpp @@ -1,7 +1,9 @@ #include "weighted_median_move_generator.h" #include "globals.h" +#include "physical_types_util.h" #include "place_constraints.h" +#include "place_macro.h" #include "placer_state.h" #include "move_utils.h" @@ -11,9 +13,11 @@ #define CRIT_MULT_FOR_W_MEDIAN 10 WeightedMedianMoveGenerator::WeightedMedianMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} + : MoveGenerator(placer_state, place_macros, net_cost_handler, reward_function, rng) {} e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, @@ -23,13 +27,13 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& const auto& cluster_ctx = g_vpr_ctx.clustering(); auto& placer_state = placer_state_.get(); const auto& block_locs = placer_state.block_locs(); - auto& place_move_ctx = placer_state.mutable_move(); const auto& blk_loc_registry = placer_state.blk_loc_registry(); //Find a movable block based on blk_type ClusterBlockId b_from = propose_block_to_move(placer_opts, proposed_action.logical_blk_type_index, /*highly_crit_block=*/false, + /*placer_criticalities=*/nullptr, /*net_from=*/nullptr, /*pin_from=*/nullptr, placer_state, @@ -57,9 +61,9 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& //clear the vectors that saves X & Y coords //reused to save allocation time - place_move_ctx.X_coord.clear(); - place_move_ctx.Y_coord.clear(); - place_move_ctx.layer_coord.clear(); + X_coord.clear(); + Y_coord.clear(); + layer_coord.clear(); std::vector layer_blk_cnt(num_layers, 0); //iterate over block pins @@ -87,50 +91,50 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& // We need to insert the calculated edges in the X,Y vectors multiple times based on the criticality of the pin that caused each of them. // As all the criticalities are [0,1], we map it to [0,CRIT_MULT_FOR_W_MEDIAN] inserts in the vectors for each edge // by multiplying each edge's criticality by CRIT_MULT_FOR_W_MEDIAN - place_move_ctx.X_coord.insert(place_move_ctx.X_coord.end(), ceil(coords.xmin.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.xmin.edge); - place_move_ctx.X_coord.insert(place_move_ctx.X_coord.end(), ceil(coords.xmax.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.xmax.edge); - place_move_ctx.Y_coord.insert(place_move_ctx.Y_coord.end(), ceil(coords.ymin.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.ymin.edge); - place_move_ctx.Y_coord.insert(place_move_ctx.Y_coord.end(), ceil(coords.ymax.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.ymax.edge); - place_move_ctx.layer_coord.insert(place_move_ctx.layer_coord.end(), ceil(coords.layer_min.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.layer_min.edge); - place_move_ctx.layer_coord.insert(place_move_ctx.layer_coord.end(), ceil(coords.layer_max.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.layer_max.edge); + X_coord.insert(X_coord.end(), ceil(coords.xmin.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.xmin.edge); + X_coord.insert(X_coord.end(), ceil(coords.xmax.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.xmax.edge); + Y_coord.insert(Y_coord.end(), ceil(coords.ymin.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.ymin.edge); + Y_coord.insert(Y_coord.end(), ceil(coords.ymax.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.ymax.edge); + layer_coord.insert(layer_coord.end(), ceil(coords.layer_min.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.layer_min.edge); + layer_coord.insert(layer_coord.end(), ceil(coords.layer_max.criticality * CRIT_MULT_FOR_W_MEDIAN), coords.layer_max.edge); } - if ((place_move_ctx.X_coord.empty()) || (place_move_ctx.Y_coord.empty()) || (place_move_ctx.layer_coord.empty())) { + if ((X_coord.empty()) || (Y_coord.empty()) || (layer_coord.empty())) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tMove aborted - X_coord or y_coord or layer_coord are empty\n"); return e_create_move::ABORT; } //calculate the weighted median region - std::stable_sort(place_move_ctx.X_coord.begin(), place_move_ctx.X_coord.end()); - std::stable_sort(place_move_ctx.Y_coord.begin(), place_move_ctx.Y_coord.end()); - std::stable_sort(place_move_ctx.layer_coord.begin(), place_move_ctx.layer_coord.end()); + std::stable_sort(X_coord.begin(), X_coord.end()); + std::stable_sort(Y_coord.begin(), Y_coord.end()); + std::stable_sort(layer_coord.begin(), layer_coord.end()); - if (place_move_ctx.X_coord.size() == 1) { - limit_coords.xmin = place_move_ctx.X_coord[0]; + if (X_coord.size() == 1) { + limit_coords.xmin = X_coord[0]; limit_coords.xmax = limit_coords.xmin; } else { - limit_coords.xmin = place_move_ctx.X_coord[((place_move_ctx.X_coord.size() - 1) / 2)]; - limit_coords.xmax = place_move_ctx.X_coord[((place_move_ctx.X_coord.size() - 1) / 2) + 1]; + limit_coords.xmin = X_coord[((X_coord.size() - 1) / 2)]; + limit_coords.xmax = X_coord[((X_coord.size() - 1) / 2) + 1]; } - if (place_move_ctx.Y_coord.size() == 1) { - limit_coords.ymin = place_move_ctx.Y_coord[0]; + if (Y_coord.size() == 1) { + limit_coords.ymin = Y_coord[0]; limit_coords.ymax = limit_coords.ymin; } else { - limit_coords.ymin = place_move_ctx.Y_coord[((place_move_ctx.Y_coord.size() - 1) / 2)]; - limit_coords.ymax = place_move_ctx.Y_coord[((place_move_ctx.Y_coord.size() - 1) / 2) + 1]; + limit_coords.ymin = Y_coord[((Y_coord.size() - 1) / 2)]; + limit_coords.ymax = Y_coord[((Y_coord.size() - 1) / 2) + 1]; } - if (place_move_ctx.layer_coord.size() == 1) { - limit_coords.layer_min = place_move_ctx.layer_coord[0]; + if (layer_coord.size() == 1) { + limit_coords.layer_min = layer_coord[0]; limit_coords.layer_max = limit_coords.layer_min; } else { - limit_coords.layer_min = place_move_ctx.layer_coord[((place_move_ctx.layer_coord.size() - 1) / 2)]; - limit_coords.layer_max = place_move_ctx.layer_coord[((place_move_ctx.layer_coord.size() - 1) / 2) + 1]; + limit_coords.layer_min = layer_coord[((layer_coord.size() - 1) / 2)]; + limit_coords.layer_max = layer_coord[((layer_coord.size() - 1) / 2) + 1]; } t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, + first_rlim, placer_opts.place_dm_rlim}; t_pl_loc w_median_point; @@ -142,7 +146,7 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros_); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -153,9 +157,9 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& } bool WeightedMedianMoveGenerator::get_bb_cost_for_net_excluding_block(ClusterNetId net_id, - ClusterPinId moving_pin_id, - const PlacerCriticalities* criticalities, - t_bb_cost* coords) { + ClusterPinId moving_pin_id, + const PlacerCriticalities* criticalities, + t_bb_cost* coords) { const auto& blk_loc_registry = placer_state_.get().blk_loc_registry(); const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -253,4 +257,3 @@ bool WeightedMedianMoveGenerator::get_bb_cost_for_net_excluding_block(ClusterNet return skip_net; } - diff --git a/vpr/src/place/move_generators/weighted_median_move_generator.h b/vpr/src/place/move_generators/weighted_median_move_generator.h index a6041f13e87..6cdaf72588f 100644 --- a/vpr/src/place/move_generators/weighted_median_move_generator.h +++ b/vpr/src/place/move_generators/weighted_median_move_generator.h @@ -1,8 +1,8 @@ -#ifndef VPR_WEIGHTED_MEDIAN_MOVE_GEN_H -#define VPR_WEIGHTED_MEDIAN_MOVE_GEN_H +#pragma once #include "move_generator.h" -#include "timing_place.h" + +class PlaceMacros; /** * @brief The weighted median move generator @@ -17,6 +17,8 @@ class WeightedMedianMoveGenerator : public MoveGenerator { public: WeightedMedianMoveGenerator() = delete; WeightedMedianMoveGenerator(PlacerState& placer_state, + const PlaceMacros& place_macros, + const NetCostHandler& net_cost_handler, e_reward_function reward_function, vtr::RngContainer& rng); @@ -42,6 +44,12 @@ class WeightedMedianMoveGenerator : public MoveGenerator { ClusterPinId moving_pin_id, const PlacerCriticalities* criticalities, t_bb_cost* coords); -}; -#endif + private: + /// Stores x positions to find the median + std::vector X_coord; + /// Stores y positions to find the median + std::vector Y_coord; + /// Stores layer positions to find the median + std::vector layer_coord; +}; diff --git a/vpr/src/place/move_transactions.cpp b/vpr/src/place/move_transactions.cpp index d51e0236cbf..b64117848cb 100644 --- a/vpr/src/place/move_transactions.cpp +++ b/vpr/src/place/move_transactions.cpp @@ -5,8 +5,8 @@ #include "grid_block.h" #include "vtr_assert.h" -t_pl_blocks_to_be_moved::t_pl_blocks_to_be_moved(size_t max_blocks){ - moved_blocks.reserve(max_blocks); +t_pl_blocks_to_be_moved::t_pl_blocks_to_be_moved(size_t max_blocks) { + moved_blocks.reserve(max_blocks); } size_t t_pl_blocks_to_be_moved::get_size_and_increment() { diff --git a/vpr/src/place/move_transactions.h b/vpr/src/place/move_transactions.h index 6670a012bb0..ce1095c365d 100644 --- a/vpr/src/place/move_transactions.h +++ b/vpr/src/place/move_transactions.h @@ -62,14 +62,14 @@ struct t_pl_blocks_to_be_moved { t_pl_blocks_to_be_moved(t_pl_blocks_to_be_moved&&) = delete; /** - * @brief This function increments the size of the moved_blocks vector and return the index - * of the newly added last elements. - */ + * @brief This function increments the size of the moved_blocks vector and return the index + * of the newly added last elements. + */ size_t get_size_and_increment(); /** - * @brief This function clears all data structures of this struct. - */ + * @brief This function clears all data structures of this struct. + */ void clear_move_blocks(); /** @@ -81,11 +81,10 @@ struct t_pl_blocks_to_be_moved { */ bool driven_by_moved_block(const ClusterNetId net) const; - e_block_move_result record_block_move(ClusterBlockId blk, t_pl_loc to, const BlkLocRegistry& blk_loc_registry); - + std::set determine_locations_emptied_by_move(); std::vector moved_blocks; diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index b5efb699fc7..f3cc457d0bb 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -3,6 +3,8 @@ #include "move_transactions.h" #include "globals.h" +#include "physical_types_util.h" +#include "place_macro.h" #include "vtr_random.h" #include "draw_debug.h" @@ -10,6 +12,7 @@ #include "place_constraints.h" #include "placer_state.h" +#include "PlacerCriticalities.h" //f_placer_breakpoint_reached is used to stop the placer when a breakpoint is reached. // When this flag is true, it stops the placer after the current perturbation. Thus, when a breakpoint is reached, this flag is set to true. @@ -28,10 +31,11 @@ void set_placer_breakpoint_reached(bool flag) { e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, - const BlkLocRegistry& blk_loc_registry) { + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); - e_block_move_result outcome = find_affected_blocks(blocks_affected, b_from, to, blk_loc_registry); + e_block_move_result outcome = find_affected_blocks(blocks_affected, b_from, to, blk_loc_registry, place_macros); if (outcome == e_block_move_result::INVERT) { //Try inverting the swap direction @@ -44,7 +48,7 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, } else { t_pl_loc from = block_locs[b_from].loc; - outcome = find_affected_blocks(blocks_affected, b_to, from, blk_loc_registry); + outcome = find_affected_blocks(blocks_affected, b_to, from, blk_loc_registry, place_macros); if (outcome == e_block_move_result::INVERT) { blocks_affected.move_abortion_logger.log_move_abort("inverted move recursion"); @@ -64,14 +68,14 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, - const BlkLocRegistry& blk_loc_registry) { + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { /* Finds and set ups the affected_blocks array. * Returns abort_swap. */ VTR_ASSERT_SAFE(b_from); const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); - const auto& place_macros = blk_loc_registry.place_macros(); e_block_move_result outcome = e_block_move_result::VALID; @@ -85,7 +89,7 @@ e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affecte t_pl_offset swap_offset = to - from; int imember_from = 0; - outcome = record_macro_swaps(blocks_affected, imacro_from, imember_from, swap_offset, blk_loc_registry); + outcome = record_macro_swaps(blocks_affected, imacro_from, imember_from, swap_offset, blk_loc_registry, place_macros); VTR_ASSERT_SAFE(outcome != e_block_move_result::VALID || imember_from == int(place_macros[imacro_from].members.size())); @@ -142,14 +146,13 @@ e_block_move_result record_single_block_swap(t_pl_blocks_to_be_moved& blocks_aff return e_block_move_result::ABORT; } - // Sets up the blocks moved outcome = blocks_affected.record_block_move(b_from, to, blk_loc_registry); if (outcome != e_block_move_result::VALID) { return outcome; } - + t_pl_loc from = block_locs[b_from].loc; outcome = blocks_affected.record_block_move(b_to, from, blk_loc_registry); @@ -165,8 +168,8 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro_from, int& imember_from, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { - const auto& place_macros = blk_loc_registry.place_macros(); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); @@ -199,11 +202,11 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, //To block is a macro if (imacro_from == imacro_to) { - outcome = record_macro_self_swaps(blocks_affected, imacro_from, swap_offset, blk_loc_registry); + outcome = record_macro_self_swaps(blocks_affected, imacro_from, swap_offset, blk_loc_registry, place_macros); imember_from = place_macros[imacro_from].members.size(); break; //record_macro_self_swaps() handles this case completely, so we don't need to continue the loop } else { - outcome = record_macro_macro_swaps(blocks_affected, imacro_from, imember_from, imacro_to, b_to, swap_offset, blk_loc_registry); + outcome = record_macro_macro_swaps(blocks_affected, imacro_from, imember_from, imacro_to, b_to, swap_offset, blk_loc_registry, place_macros); if (outcome == e_block_move_result::INVERT_VALID) { break; //The move was inverted and successfully proposed, don't need to continue the loop } @@ -227,7 +230,8 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff const int imacro_to, ClusterBlockId blk_to, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& pl_macros) { //Adds the macro imacro_to to the set of affected block caused by swapping 'blk_to' to its //new position. // @@ -235,7 +239,6 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff //The position in the from macro ('imacro_from') is specified by 'imember_from', and the relevant //macro fro the to block is 'imacro_to'. - const auto& pl_macros = blk_loc_registry.place_macros().macros(); const auto& block_locs = blk_loc_registry.block_locs(); //At the moment, we only support blk_to being the first element of the 'to' macro. @@ -245,7 +248,7 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff //allows these blocks to swap) if (pl_macros[imacro_to].members[0].blk_index != blk_to) { int imember_to = 0; - auto outcome = record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry); + auto outcome = record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry, pl_macros); if (outcome == e_block_move_result::INVERT) { blocks_affected.move_abortion_logger.log_move_abort("invert recursion2"); outcome = e_block_move_result::ABORT; @@ -314,7 +317,7 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff // //Swap the remainder of the 'to' macro to locations after the 'from' macro. //Note that we are swapping in the opposite direction so the swap offsets are inverted. - return record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry); + return record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry, pl_macros); } return e_block_move_result::VALID; @@ -330,8 +333,8 @@ e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, std::vector& displaced_blocks, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { - const auto& place_macros = blk_loc_registry.place_macros(); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); @@ -364,8 +367,8 @@ e_block_move_result identify_macro_self_swap_affected_macros(std::vector& m const int imacro, t_pl_offset swap_offset, const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, MoveAbortionLogger& move_abortion_logger) { - const auto& place_macros = blk_loc_registry.place_macros(); const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); @@ -390,7 +393,7 @@ e_block_move_result identify_macro_self_swap_affected_macros(std::vector& m auto itr = std::find(macros.begin(), macros.end(), imacro_to); if (itr == macros.end()) { macros.push_back(imacro_to); - outcome = identify_macro_self_swap_affected_macros(macros, imacro_to, swap_offset, blk_loc_registry, move_abortion_logger); + outcome = identify_macro_self_swap_affected_macros(macros, imacro_to, swap_offset, blk_loc_registry, place_macros, move_abortion_logger); } } } @@ -400,15 +403,14 @@ e_block_move_result identify_macro_self_swap_affected_macros(std::vector& m e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { - const auto& place_macros = blk_loc_registry.place_macros(); - + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros) { //Reset any partial move blocks_affected.clear_move_blocks(); //Collect the macros affected std::vector affected_macros; - auto outcome = identify_macro_self_swap_affected_macros(affected_macros, imacro, swap_offset, blk_loc_registry, blocks_affected.move_abortion_logger); + auto outcome = identify_macro_self_swap_affected_macros(affected_macros, imacro, swap_offset, blk_loc_registry, place_macros, blocks_affected.move_abortion_logger); if (outcome != e_block_move_result::VALID) { return outcome; @@ -421,7 +423,7 @@ e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affe //Move all the affected macros by the offset for (int imacro_affected : affected_macros) { - outcome = record_macro_move(blocks_affected, displaced_blocks, imacro_affected, swap_offset, blk_loc_registry); + outcome = record_macro_move(blocks_affected, displaced_blocks, imacro_affected, swap_offset, blk_loc_registry, place_macros); if (outcome != e_block_move_result::VALID) { return outcome; @@ -470,7 +472,6 @@ bool is_legal_swap_to_location(ClusterBlockId blk, const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); - if (to.x < 0 || to.x >= int(device_ctx.grid.width()) || to.y < 0 || to.y >= int(device_ctx.grid.height()) || to.layer < 0 @@ -547,30 +548,25 @@ void enable_placer_debug(const t_placer_opts& placer_opts, ClusterBlockId propose_block_to_move(const t_placer_opts& placer_opts, int& logical_blk_type_index, bool highly_crit_block, + const PlacerCriticalities* placer_criticalities, ClusterNetId* net_from, int* pin_from, const PlacerState& placer_state, vtr::RngContainer& rng) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& blk_loc_registry = placer_state.blk_loc_registry(); + ClusterBlockId b_from = ClusterBlockId::INVALID(); - auto& cluster_ctx = g_vpr_ctx.clustering(); - if (logical_blk_type_index == -1) { //If the block type is unspecified, choose any random block to be swapped with another random block - if (highly_crit_block) { - b_from = pick_from_highly_critical_block(*net_from, *pin_from, placer_state, rng); - } else { - b_from = pick_from_block(rng); - } + if (highly_crit_block) { + b_from = pick_from_highly_critical_block(*net_from, *pin_from, logical_blk_type_index, placer_state, *placer_criticalities, rng); + } else { + b_from = pick_from_block(logical_blk_type_index, rng, blk_loc_registry); + } - //if a movable block found, set the block type - if (b_from) { - logical_blk_type_index = cluster_ctx.clb_nlist.block_type(b_from)->index; - } - } else { //If the block type is specified, choose a random block with blk_type to be swapped with another random block - if (highly_crit_block) { - b_from = pick_from_highly_critical_block(*net_from, *pin_from, logical_blk_type_index, placer_state, rng); - } else { - b_from = pick_from_block(logical_blk_type_index, rng); - } + //if a movable block found, set the block type + if (b_from) { + logical_blk_type_index = cluster_ctx.clb_nlist.block_type(b_from)->index; } if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { @@ -580,110 +576,54 @@ ClusterBlockId propose_block_to_move(const t_placer_opts& placer_opts, return b_from; } -const std::vector& movable_blocks_per_type(const t_logical_block_type& blk_type) { - const auto& place_ctx = g_vpr_ctx.placement(); - - // the vector is returned as const reference to avoid unnecessary copies, - // especially that returned vectors may be very large as they contain - // all clustered blocks with a specific block type - return place_ctx.movable_blocks_per_type[blk_type.index]; -} - -ClusterBlockId pick_from_block(vtr::RngContainer& rng) { - auto& place_ctx = g_vpr_ctx.placement(); - - // get the number of movable clustered blocks - const size_t n_movable_blocks = place_ctx.movable_blocks.size(); - - if (n_movable_blocks > 0) { - //Pick a movable block at random and return it - auto b_from = ClusterBlockId(rng.irand((int)n_movable_blocks - 1)); - return b_from; - } else { - //No movable blocks found - return ClusterBlockId::INVALID(); - } -} - -ClusterBlockId pick_from_block(const int logical_blk_type_index, vtr::RngContainer& rng) { - auto& place_ctx = g_vpr_ctx.placement(); - - const auto& movable_blocks_of_type = place_ctx.movable_blocks_per_type[logical_blk_type_index]; - - if (movable_blocks_of_type.empty()) { - return ClusterBlockId::INVALID(); - } - - auto b_from = ClusterBlockId(movable_blocks_of_type[rng.irand((int)movable_blocks_of_type.size() - 1)]); - - return b_from; -} - -//Pick a random highly critical block to be swapped with another random block. -//If none is found return ClusterBlockId::INVALID() -ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, - int& pin_from, - const PlacerState& placer_state, - vtr::RngContainer& rng) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state.move(); - auto& block_locs = placer_state.block_locs(); - - //Initialize critical net and pin to be invalid - net_from = ClusterNetId::INVALID(); - pin_from = -1; +ClusterBlockId pick_from_block(const int logical_blk_type_index, + vtr::RngContainer& rng, + const BlkLocRegistry& blk_loc_registry) { + // if logical block type is specified, pick the 'from' block from blocks of that type; + // otherwise, select it randomly from all blocks + const auto& movable_blocks = (logical_blk_type_index < 0) ? blk_loc_registry.movable_blocks() : blk_loc_registry.movable_blocks_per_type()[logical_blk_type_index]; - //check if any critical block is available - if (place_move_ctx.highly_crit_pins.empty()) { + if (movable_blocks.empty()) { return ClusterBlockId::INVALID(); } - //pick a random highly critical pin and find the nets driver block - std::pair crit_pin = place_move_ctx.highly_crit_pins[rng.irand(place_move_ctx.highly_crit_pins.size() - 1)]; - ClusterBlockId b_from = cluster_ctx.clb_nlist.net_driver_block(crit_pin.first); - - if (block_locs[b_from].is_fixed) { - return ClusterBlockId::INVALID(); //Block is fixed, cannot move - } + ClusterBlockId b_from = movable_blocks[rng.irand((int)movable_blocks.size() - 1)]; - net_from = crit_pin.first; - pin_from = crit_pin.second; return b_from; - - //Unreachable statement - return ClusterBlockId::INVALID(); } -//Pick a random highly critical block with a specified block type to be swapped with another random block. -//If none is found return ClusterBlockId::INVALID() ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, int& pin_from, const int logical_blk_type_index, const PlacerState& placer_state, + const PlacerCriticalities& placer_criticalities, vtr::RngContainer& rng) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state.move(); - auto& block_locs = placer_state.block_locs(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& block_locs = placer_state.block_locs(); //Initialize critical net and pin to be invalid net_from = ClusterNetId::INVALID(); pin_from = -1; + const auto& highly_crit_pins = placer_criticalities.get_highly_critical_pins(); + //check if any critical block is available - if (place_move_ctx.highly_crit_pins.empty()) { + if (highly_crit_pins.empty()) { return ClusterBlockId::INVALID(); } //pick a random highly critical pin and find the nets driver block - std::pair crit_pin = place_move_ctx.highly_crit_pins[rng.irand(place_move_ctx.highly_crit_pins.size() - 1)]; + std::pair crit_pin = highly_crit_pins[rng.irand(highly_crit_pins.size() - 1)]; ClusterBlockId b_from = cluster_ctx.clb_nlist.net_driver_block(crit_pin.first); - //Check if picked block type matches with the blk_type specified, and it is not fixed - //blk_type from propose move doesn't account for the EMPTY type auto b_from_type = cluster_ctx.clb_nlist.block_type(b_from); - if (b_from_type->index == logical_blk_type_index) { + + // check if the type of the picked block matches with the specified block type + // when a block type is specified, i.e. when logical_blk_type_index >= 0 + if (b_from_type->index == logical_blk_type_index || logical_blk_type_index < 0) { + // ensure that the selected block is not fixed if (block_locs[b_from].is_fixed) { - return ClusterBlockId::INVALID(); //Block is fixed, cannot move + return ClusterBlockId::INVALID(); // a fixed block can't be moved } net_from = crit_pin.first; @@ -692,7 +632,6 @@ ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, } //No critical block with 'blk_type' found - //Unreachable statement return ClusterBlockId::INVALID(); } @@ -707,7 +646,7 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, // //Note that the range limit (rlim) is applied in a logical sense (i.e. 'compressed' grid space consisting //of the same block types, and not the physical grid space). This means, for example, that columns of 'rare' - //blocks (e.g. DSPs/RAMs) which are physically far appart but logically adjacent will be swappable even + //blocks (e.g. DSPs/RAMs) which are physically far apart but logically adjacent will be swappable even //at an rlim fo 1. // //This ensures that such blocks don't get locked down too early during placement (as would be the @@ -1252,7 +1191,7 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, const auto [layer_low, layer_high] = compressed_intersect_reg.get_layer_range(); VTR_ASSERT(layer_low == layer_num && layer_high == layer_num); - delta_cx = intersect_rect.xmax() - intersect_rect.xmin(); + delta_cx = intersect_rect.xmax() - intersect_rect.xmin(); std::tie(search_range.xmin, search_range.ymin, search_range.xmax, search_range.ymax) = intersect_rect.coordinates(); search_range.layer_min = layer_low; @@ -1324,111 +1263,3 @@ int get_random_layer(t_logical_block_type_ptr logical_block, vtr::RngContainer& return layer_num; } - -t_bb union_2d_bb(const std::vector& bb_vec) { - t_bb merged_bb; - - // Not all 2d_bbs are valid. Thus, if one of the coordinates in the 2D_bb is not valid (equal to OPEN), - // we need to skip it. - for (const auto& layer_bb : bb_vec) { - if (layer_bb.xmin == OPEN) { - VTR_ASSERT_SAFE(layer_bb.xmax == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymin == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymax == OPEN); - VTR_ASSERT_SAFE(layer_bb.layer_num == OPEN); - continue; - } - if (merged_bb.xmin == OPEN || layer_bb.xmin < merged_bb.xmin) { - merged_bb.xmin = layer_bb.xmin; - } - if (merged_bb.xmax == OPEN || layer_bb.xmax > merged_bb.xmax) { - merged_bb.xmax = layer_bb.xmax; - } - if (merged_bb.ymin == OPEN || layer_bb.ymin < merged_bb.ymin) { - merged_bb.ymin = layer_bb.ymin; - } - if (merged_bb.ymax == OPEN || layer_bb.ymax > merged_bb.ymax) { - merged_bb.ymax = layer_bb.ymax; - } - if (merged_bb.layer_min == OPEN || layer_bb.layer_num < merged_bb.layer_min) { - merged_bb.layer_min = layer_bb.layer_num; - } - if (merged_bb.layer_max == OPEN || layer_bb.layer_num > merged_bb.layer_max) { - merged_bb.layer_max = layer_bb.layer_num; - } - } - - return merged_bb; -} - -std::pair union_2d_bb_incr(const std::vector& num_edge_vec, - const std::vector& bb_vec) { - t_bb merged_num_edge; - t_bb merged_bb; - - for (const auto& layer_bb : bb_vec) { - if (layer_bb.xmin == OPEN) { - VTR_ASSERT_SAFE(layer_bb.xmax == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymin == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymax == OPEN); - VTR_ASSERT_SAFE(layer_bb.layer_num == OPEN); - continue; - } - if (merged_bb.xmin == OPEN || layer_bb.xmin <= merged_bb.xmin) { - if (layer_bb.xmin == merged_bb.xmin) { - VTR_ASSERT_SAFE(merged_num_edge.xmin != OPEN); - merged_num_edge.xmin += num_edge_vec[layer_bb.layer_num].xmin; - } else { - merged_num_edge.xmin = num_edge_vec[layer_bb.layer_num].xmin; - } - merged_bb.xmin = layer_bb.xmin; - } - if (merged_bb.xmax == OPEN || layer_bb.xmax >= merged_bb.xmax) { - if (layer_bb.xmax == merged_bb.xmax) { - VTR_ASSERT_SAFE(merged_num_edge.xmax != OPEN); - merged_num_edge.xmax += num_edge_vec[layer_bb.layer_num].xmax; - } else { - merged_num_edge.xmax = num_edge_vec[layer_bb.layer_num].xmax; - } - merged_bb.xmax = layer_bb.xmax; - } - if (merged_bb.ymin == OPEN || layer_bb.ymin <= merged_bb.ymin) { - if (layer_bb.ymin == merged_bb.ymin) { - VTR_ASSERT_SAFE(merged_num_edge.ymin != OPEN); - merged_num_edge.ymin += num_edge_vec[layer_bb.layer_num].ymin; - } else { - merged_num_edge.ymin = num_edge_vec[layer_bb.layer_num].ymin; - } - merged_bb.ymin = layer_bb.ymin; - } - if (merged_bb.ymax == OPEN || layer_bb.ymax >= merged_bb.ymax) { - if (layer_bb.ymax == merged_bb.ymax) { - VTR_ASSERT_SAFE(merged_num_edge.ymax != OPEN); - merged_num_edge.ymax += num_edge_vec[layer_bb.layer_num].ymax; - } else { - merged_num_edge.ymax = num_edge_vec[layer_bb.layer_num].ymax; - } - merged_bb.ymax = layer_bb.ymax; - } - if (merged_bb.layer_min == OPEN || layer_bb.layer_num <= merged_bb.layer_min) { - if (layer_bb.layer_num == merged_bb.layer_min) { - VTR_ASSERT_SAFE(merged_num_edge.layer_min != OPEN); - merged_num_edge.layer_min += num_edge_vec[layer_bb.layer_num].layer_num; - } else { - merged_num_edge.layer_min = num_edge_vec[layer_bb.layer_num].layer_num; - } - merged_bb.layer_min = layer_bb.layer_num; - } - if (merged_bb.layer_max == OPEN || layer_bb.layer_num >= merged_bb.layer_max) { - if (layer_bb.layer_num == merged_bb.layer_max) { - VTR_ASSERT_SAFE(merged_num_edge.layer_max != OPEN); - merged_num_edge.layer_max += num_edge_vec[layer_bb.layer_num].layer_num; - } else { - merged_num_edge.layer_max = num_edge_vec[layer_bb.layer_num].layer_num; - } - merged_bb.layer_max = layer_bb.layer_num; - } - } - - return std::make_pair(merged_num_edge, merged_bb); -} diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index de3d771e7ae..5552c36e8e9 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -1,5 +1,5 @@ -#ifndef VPR_MOVE_UTILS_H -#define VPR_MOVE_UTILS_H + +#pragma once #include "vpr_types.h" #include "move_transactions.h" @@ -7,6 +7,8 @@ class PlacerState; class BlkLocRegistry; +class PlaceMacros; +class PlacerCriticalities; namespace vtr { class RngContainer; } @@ -97,7 +99,8 @@ struct t_range_limiters { e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); /** * @brief Find the blocks that will be affected by a move of b_from to to_loc @@ -110,7 +113,8 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); e_block_move_result record_single_block_swap(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, @@ -121,7 +125,8 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro_from, int& imember_from, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro_from, @@ -129,24 +134,28 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff const int imacro_to, ClusterBlockId blk_to, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& pl_macros); e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, std::vector& displaced_blocks, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); e_block_move_result identify_macro_self_swap_affected_macros(std::vector& macros, const int imacro, t_pl_offset swap_offset, const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, MoveAbortionLogger& move_abortion_logger); e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros); /** * @brief Check whether the "to" location is legal for the given "blk" @@ -171,55 +180,46 @@ bool is_legal_swap_to_location(ClusterBlockId blk, ClusterBlockId propose_block_to_move(const t_placer_opts& placer_opts, int& logical_blk_type_index, bool highly_crit_block, + const PlacerCriticalities* placer_criticalities, ClusterNetId* net_from, int* pin_from, const PlacerState& placer_state, vtr::RngContainer& rng); -/** - * Returns all movable clustered blocks with a specified logical block type. - * @param blk_type Specifies the logical block block type. - * @return A const reference to a vector containing all movable blocks with the specified logical block type. - */ -const std::vector& movable_blocks_per_type(const t_logical_block_type& blk_type); - -/** - * @brief Select a random block to be swapped with another block - * - * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found - */ -ClusterBlockId pick_from_block(vtr::RngContainer& rng); - /** * @brief Find a block with a specific block type to be swapped with another block * - * @param logical_blk_type_index: the agent type of the moving block. + * @param logical_blk_type_index The logical type of the moving block. If a negative value is passed, + * the block is selected randomly from all movable blocks and not from a specific type. + * @param rng A random number generator used to select a random block. + * @param blk_loc_registry Contains movable blocks and movable blocks per type. * * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found */ -ClusterBlockId pick_from_block(int logical_blk_type_index, vtr::RngContainer& rng); - -/** - * @brief Select a random highly critical block to be swapped with another block - * - * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found - */ -ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, - int& pin_from, - const PlacerState& placer_state, - vtr::RngContainer& rng); +ClusterBlockId pick_from_block(int logical_blk_type_index, + vtr::RngContainer& rng, + const BlkLocRegistry& blk_loc_registry); /** - * @brief Find a block with a specific block type to be swapped with another block + * @brief Find a highly critical block with a specific block type to be swapped with another block. * - * @param logical_blk_type_index: the agent type of the moving block. + * @param net_from The clustered net id of the critical connection of the selected block by this function. + * To be filled by this function. + * @param pin_from The pin id of the critical connection of the selected block by this function. + * To be filled by this function. + * @param logical_blk_type_index The logical type of the moving block. If a negative value is passed, + * the block is selected randomly from all movable blocks and not from a specific type. + * @param placer_state Used to access the current placement's info, e.g. block locations and if they are fixed. + * @param placer_criticalities Holds the clustered netlist connection criticalities. + * @param rng A random number generator used to select a random highly critical block. * - * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found + * @return BlockId of the selected block, ClusterBlockId::INVALID() if no block with specified block type found. */ ClusterBlockId pick_from_highly_critical_block(ClusterNetId& net_from, int& pin_from, int logical_blk_type_index, const PlacerState& placer_state, + const PlacerCriticalities& placer_criticalities, vtr::RngContainer& rng); bool find_to_loc_uniform(t_logical_block_type_ptr type, @@ -433,24 +433,6 @@ int find_free_layer(t_logical_block_type_ptr logical_block, int get_random_layer(t_logical_block_type_ptr logical_block, vtr::RngContainer& rng); -/** - * @brief Iterate over all layers and get the maximum x and y over that layers that have a valid value. set the layer min and max - * based on the layers that have a valid BB. - * @param tbb_vec - * @return 3D bounding box - */ -t_bb union_2d_bb(const std::vector& tbb_vec); - -/** - * @brief Iterate over all layers and get the maximum x and y over that layers that have a valid value. Create the "num_edge" in a similar way. This data structure - * stores how many blocks are on each edge of the BB. set the layer min and max based on the layers that have a valid BB. - * @param num_edge_vec - * @param bb_vec - * @return num_edge, 3D bb - */ -std::pair union_2d_bb_incr(const std::vector& num_edge_vec, - const std::vector& bb_vec); - /** * @brief If the block ID passed to the placer_debug_net parameter of the command line is equal to blk_id, or if any of the nets * connected to the block share the same ID as the net ID passed to the placer_debug_net parameter of the command line, @@ -461,5 +443,3 @@ std::pair union_2d_bb_incr(const std::vector& num_edge_vec, */ void enable_placer_debug(const t_placer_opts& placer_opts, ClusterBlockId blk_id); - -#endif diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index ac049995347..0a48466c644 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -33,7 +33,8 @@ #include "place_timing_update.h" #include "vtr_math.h" #include "vtr_ndmatrix.h" -#include "vtr_ndoffsetmatrix.h" +#include "PlacerCriticalities.h" +#include "vtr_prefix_sum.h" #include @@ -68,8 +69,6 @@ static void update_bb_pin_sink_count(const t_physical_tile_loc& pin_old_loc, vtr::NdMatrixProxy bb_pin_sink_count_new, bool is_output_pin); - - /** * @brief When BB is being updated incrementally, the pin is moving to a new layer, and the BB is of the type "per-layer, * use this function to update the BB on the new layer. @@ -85,14 +84,6 @@ static void add_block_to_bb(const t_physical_tile_loc& new_pin_loc, t_2D_bb& bb_edge_new, t_2D_bb& bb_coord_new); -/** - * @brief Given the 3D BB, calculate the wire-length estimate of the net - * @param net_id ID of the net which wirelength estimate is requested - * @param bb Bounding box of the net - * @return Wirelength estimate of the net - */ -static double get_net_wirelength_estimate(ClusterNetId net_id, const t_bb& bb); - /** * @brief To get the wirelength cost/est, BB perimeter is multiplied by a factor to approximately correct for the half-perimeter * bounding box wirelength's underestimate of wiring for nets with fanout greater than 2. @@ -102,7 +93,6 @@ static double wirelength_crossing_count(size_t fanout); /******************************* End of Function definitions ************************************/ - NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, PlacerState& placer_state, bool cube_bb) @@ -118,7 +108,9 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, if (cube_bb_) { ts_bb_edge_new_.resize(num_nets, t_bb()); ts_bb_coord_new_.resize(num_nets, t_bb()); - comp_bb_cost_functor_ = std::bind(&NetCostHandler::comp_cube_bb_cost_, this, std::placeholders::_1); + bb_coords_.resize(num_nets, t_bb()); + bb_num_on_edges_.resize(num_nets, t_bb()); + comp_bb_cost_functor_ = std::bind(&NetCostHandler::comp_cube_bb_cost_, this, std::placeholders::_1); update_bb_functor_ = std::bind(&NetCostHandler::update_bb_, this, std::placeholders::_1, std::placeholders::_2, std::placeholders::_3, std::placeholders::_4); get_net_bb_cost_functor_ = std::bind(&NetCostHandler::get_net_cube_bb_cost_, this, std::placeholders::_1, /*use_ts=*/true); @@ -126,7 +118,9 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, } else { layer_ts_bb_edge_new_.resize(num_nets, std::vector(num_layers, t_2D_bb())); layer_ts_bb_coord_new_.resize(num_nets, std::vector(num_layers, t_2D_bb())); - comp_bb_cost_functor_ = std::bind(&NetCostHandler::comp_per_layer_bb_cost_, this, std::placeholders::_1); + layer_bb_num_on_edges_.resize(num_nets, std::vector(num_layers, t_2D_bb())); + layer_bb_coords_.resize(num_nets, std::vector(num_layers, t_2D_bb())); + comp_bb_cost_functor_ = std::bind(&NetCostHandler::comp_per_layer_bb_cost_, this, std::placeholders::_1); update_bb_functor_ = std::bind(&NetCostHandler::update_layer_bb_, this, std::placeholders::_1, std::placeholders::_2, std::placeholders::_3, std::placeholders::_4); get_net_bb_cost_functor_ = std::bind(&NetCostHandler::get_net_per_layer_bb_cost_, this, std::placeholders::_1, /*use_ts=*/true); @@ -135,6 +129,7 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, /* This initializes the whole matrix to OPEN which is an invalid value*/ ts_layer_sink_pin_count_.resize({num_nets, size_t(num_layers)}, OPEN); + num_sink_pin_layer_.resize({num_nets, size_t(num_layers)}, OPEN); ts_nets_to_update_.resize(num_nets, ClusterNetId::INVALID()); @@ -153,8 +148,8 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_() { const auto& device_ctx = g_vpr_ctx.device(); - const int grid_height = (int)device_ctx.grid.height(); - const int grid_width = (int)device_ctx.grid.width(); + const size_t grid_height = device_ctx.grid.height(); + const size_t grid_width = device_ctx.grid.width(); /* These arrays contain accumulative channel width between channel zero and * the channel specified by the given index. The accumulated channel width @@ -164,38 +159,29 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_() { * acc_chan?_width_[high] - acc_chan?_width_[low - 1] * This returns the total number of tracks between channels 'low' and 'high', * including tracks in these channels. - * - * Channel -1 doesn't exist, so we can say it has zero tracks. We need to be able - * to access these arrays with index -1 to handle cases where the lower channel is 0. */ - acc_chanx_width_ = vtr::NdOffsetMatrix({{{-1, grid_height}}}); - acc_chany_width_ = vtr::NdOffsetMatrix({{{-1, grid_width}}}); - - // initialize the first element (index -1) with zero - acc_chanx_width_[-1] = 0; - for (int y = 0; y < grid_height; y++) { - acc_chanx_width_[y] = acc_chanx_width_[y - 1] + device_ctx.chan_width.x_list[y]; + acc_chanx_width_ = vtr::PrefixSum1D(grid_height, [&](size_t y) noexcept { + int chan_x_width = device_ctx.chan_width.x_list[y]; /* If the number of tracks in a channel is zero, two consecutive elements take the same * value. This can lead to a division by zero in get_chanxy_cost_fac_(). To avoid this * potential issue, we assume that the channel width is at least 1. */ - if (acc_chanx_width_[y] == acc_chanx_width_[y - 1]) { - acc_chanx_width_[y]++; - } - } + if (chan_x_width == 0) + return 1; - // initialize the first element (index -1) with zero - acc_chany_width_[-1] = 0; - for (int x = 0; x < grid_width; x++) { - acc_chany_width_[x] = acc_chany_width_[x - 1] + device_ctx.chan_width.y_list[x]; + return chan_x_width; + }); + acc_chany_width_ = vtr::PrefixSum1D(grid_width, [&](size_t x) noexcept { + int chan_y_width = device_ctx.chan_width.y_list[x]; // to avoid a division by zero - if (acc_chany_width_[x] == acc_chany_width_[x - 1]) { - acc_chany_width_[x]++; - } - } - + if (chan_y_width == 0) + return 1; + + return chan_y_width; + }); + if (is_multi_layer_) { alloc_and_load_for_fast_vertical_cost_update_(); } @@ -204,13 +190,11 @@ void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_() { void NetCostHandler::alloc_and_load_for_fast_vertical_cost_update_() { const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - + const size_t grid_height = device_ctx.grid.height(); const size_t grid_width = device_ctx.grid.width(); - acc_tile_num_inter_die_conn_ = vtr::NdMatrix({grid_width, grid_height}, 0); - - vtr::NdMatrix tile_num_inter_die_conn({grid_width, grid_height}, 0.); + vtr::NdMatrix tile_num_inter_die_conn({grid_width, grid_height}, 0.); /* * Step 1: iterate over the rr-graph, recording how many edges go between layers at each (x,y) location @@ -249,53 +233,34 @@ void NetCostHandler::alloc_and_load_for_fast_vertical_cost_update_() { int num_layers = device_ctx.grid.get_num_layers(); for (size_t x = 0; x < device_ctx.grid.width(); x++) { for (size_t y = 0; y < device_ctx.grid.height(); y++) { - tile_num_inter_die_conn[x][y] /= (num_layers-1); + tile_num_inter_die_conn[x][y] /= (num_layers - 1); } } // Step 2: Calculate prefix sum of the inter-die connectivity up to and including the channel at (x, y). - acc_tile_num_inter_die_conn_[0][0] = tile_num_inter_die_conn[0][0]; - // Initialize the first row and column - for (size_t x = 1; x < device_ctx.grid.width(); x++) { - acc_tile_num_inter_die_conn_[x][0] = acc_tile_num_inter_die_conn_[x-1][0] + - tile_num_inter_die_conn[x][0]; - } - - for (size_t y = 1; y < device_ctx.grid.height(); y++) { - acc_tile_num_inter_die_conn_[0][y] = acc_tile_num_inter_die_conn_[0][y-1] + - tile_num_inter_die_conn[0][y]; - } - - for (size_t x_high = 1; x_high < device_ctx.grid.width(); x_high++) { - for (size_t y_high = 1; y_high < device_ctx.grid.height(); y_high++) { - acc_tile_num_inter_die_conn_[x_high][y_high] = acc_tile_num_inter_die_conn_[x_high-1][y_high] + - acc_tile_num_inter_die_conn_[x_high][y_high-1] + - tile_num_inter_die_conn[x_high][y_high] - - acc_tile_num_inter_die_conn_[x_high-1][y_high-1]; - } - } + acc_tile_num_inter_die_conn_ = vtr::PrefixSum2D(grid_width, + grid_height, + [&](size_t x, size_t y) { + return (int)tile_num_inter_die_conn[x][y]; + }); } -double NetCostHandler::comp_bb_cost(e_cost_methods method) { +std::pair NetCostHandler::comp_bb_cost(e_cost_methods method) { return comp_bb_cost_functor_(method); } -double NetCostHandler::comp_cube_bb_cost_(e_cost_methods method) { +std::pair NetCostHandler::comp_cube_bb_cost_(e_cost_methods method) { const auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state_.mutable_move(); double cost = 0; double expected_wirelength = 0.0; - for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ - if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ + if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ /* Small nets don't use incremental updating on their bounding boxes, * * so they can use a fast bounding box calculator. */ if (cluster_ctx.clb_nlist.net_sinks(net_id).size() >= SMALL_NET && method == e_cost_methods::NORMAL) { - get_bb_from_scratch_(net_id, - place_move_ctx.bb_coords[net_id], - place_move_ctx.bb_num_on_edges[net_id], - place_move_ctx.num_sink_pin_layer[size_t(net_id)]); + get_bb_from_scratch_(net_id, /*use_ts=*/false); } else { get_non_updatable_cube_bb_(net_id, /*use_ts=*/false); } @@ -303,36 +268,29 @@ double NetCostHandler::comp_cube_bb_cost_(e_cost_methods method) { net_cost_[net_id] = get_net_cube_bb_cost_(net_id, /*use_ts=*/false); cost += net_cost_[net_id]; if (method == e_cost_methods::CHECK) { - expected_wirelength += get_net_wirelength_estimate(net_id, place_move_ctx.bb_coords[net_id]); + expected_wirelength += get_net_wirelength_estimate_(net_id); } } } - if (method == e_cost_methods::CHECK) { - VTR_LOG("\n"); - VTR_LOG("BB estimate of min-dist (placement) wire length: %.0f\n", - expected_wirelength); - } - - return cost; + return {cost, expected_wirelength}; } -double NetCostHandler::comp_per_layer_bb_cost_(e_cost_methods method) { +std::pair NetCostHandler::comp_per_layer_bb_cost_(e_cost_methods method) { const auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state_.mutable_move(); double cost = 0; double expected_wirelength = 0.0; - for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ - if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ + if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ /* Small nets don't use incremental updating on their bounding boxes, * * so they can use a fast bounding box calculator. */ if (cluster_ctx.clb_nlist.net_sinks(net_id).size() >= SMALL_NET && method == e_cost_methods::NORMAL) { get_layer_bb_from_scratch_(net_id, - place_move_ctx.layer_bb_num_on_edges[net_id], - place_move_ctx.layer_bb_coords[net_id], - place_move_ctx.num_sink_pin_layer[size_t(net_id)]); + layer_bb_num_on_edges_[net_id], + layer_bb_coords_[net_id], + num_sink_pin_layer_[size_t(net_id)]); } else { get_non_updatable_per_layer_bb_(net_id, /*use_ts=*/false); } @@ -345,13 +303,7 @@ double NetCostHandler::comp_per_layer_bb_cost_(e_cost_methods method) { } } - if (method == e_cost_methods::CHECK) { - VTR_LOG("\n"); - VTR_LOG("BB estimate of min-dist (placement) wire length: %.0f\n", - expected_wirelength); - } - - return cost; + return {cost, expected_wirelength}; } void NetCostHandler::update_net_bb_(const ClusterNetId net, @@ -532,12 +484,11 @@ void NetCostHandler::get_non_updatable_cube_bb_(ClusterNetId net_id, bool use_ts const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); const auto& blk_loc_registry = placer_state_.blk_loc_registry(); - auto& move_ctx = placer_state_.mutable_move(); // the bounding box coordinates that is going to be updated by this function - t_bb& bb_coord_new = use_ts ? ts_bb_coord_new_[net_id] : move_ctx.bb_coords[net_id]; + t_bb& bb_coord_new = use_ts ? ts_bb_coord_new_[net_id] : bb_coords_[net_id]; // the number of sink pins of "net_id" on each layer - vtr::NdMatrixProxy num_sink_pin_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : move_ctx.num_sink_pin_layer[size_t(net_id)]; + vtr::NdMatrixProxy num_sink_pin_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : num_sink_pin_layer_[size_t(net_id)]; // get the source pin's location ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); @@ -585,10 +536,9 @@ void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool u const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& blk_loc_registry = placer_state_.blk_loc_registry(); - auto& move_ctx = placer_state_.mutable_move(); - std::vector& bb_coord_new = use_ts ? layer_ts_bb_coord_new_[net_id] : move_ctx.layer_bb_coords[net_id]; - vtr::NdMatrixProxy num_sink_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : move_ctx.num_sink_pin_layer[size_t(net_id)]; + std::vector& bb_coord_new = use_ts ? layer_ts_bb_coord_new_[net_id] : layer_bb_coords_[net_id]; + vtr::NdMatrixProxy num_sink_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : num_sink_pin_layer_[size_t(net_id)]; const int num_layers = device_ctx.grid.get_num_layers(); VTR_ASSERT_DEBUG(bb_coord_new.size() == (size_t)num_layers); @@ -627,8 +577,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, //TODO: account for multiple physical pin instances per logical pin const t_bb *curr_bb_edge, *curr_bb_coord; - auto& device_ctx = g_vpr_ctx.device(); - auto& place_move_ctx = placer_state_.move(); + const auto& device_ctx = g_vpr_ctx.device(); const int num_layers = device_ctx.grid.get_num_layers(); @@ -645,12 +594,12 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, return; } - vtr::NdMatrixProxy curr_num_sink_pin_layer = (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) ? place_move_ctx.num_sink_pin_layer[size_t(net_id)] : num_sink_pin_layer_new; + vtr::NdMatrixProxy curr_num_sink_pin_layer = (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) ? num_sink_pin_layer_[size_t(net_id)] : num_sink_pin_layer_new; if (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) { /* The net had NOT been updated before, could use the old values */ - curr_bb_edge = &place_move_ctx.bb_num_on_edges[net_id]; - curr_bb_coord = &place_move_ctx.bb_coords[net_id]; + curr_bb_edge = &bb_num_on_edges_[net_id]; + curr_bb_coord = &bb_coords_[net_id]; bb_update_status_[net_id] = NetUpdateState::UPDATED_ONCE; } else { /* The net had been updated before, must use the new values */ @@ -666,7 +615,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_old_loc.x == curr_bb_coord->xmax) { /* Old position at xmax. */ if (curr_bb_edge->xmax == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -698,7 +647,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_old_loc.x == curr_bb_coord->xmin) { /* Old position at xmin. */ if (curr_bb_edge->xmin == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -739,7 +688,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_old_loc.y == curr_bb_coord->ymax) { /* Old position at ymax. */ if (curr_bb_edge->ymax == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -771,7 +720,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_old_loc.y == curr_bb_coord->ymin) { /* Old position at ymin. */ if (curr_bb_edge->ymin == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -821,7 +770,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, if (pin_new_loc.layer_num < pin_old_loc.layer_num) { if (pin_old_loc.layer_num == curr_bb_coord->layer_max) { if (curr_bb_edge->layer_max == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -847,7 +796,7 @@ void NetCostHandler::update_bb_(ClusterNetId net_id, } else if (pin_new_loc.layer_num > pin_old_loc.layer_num) { if (pin_old_loc.layer_num == curr_bb_coord->layer_min) { if (curr_bb_edge->layer_min == 1) { - get_bb_from_scratch_(net_id, bb_coord_new, bb_edge_new, num_sink_pin_layer_new); + get_bb_from_scratch_(net_id, /*use_ts=*/true); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -893,8 +842,6 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, t_physical_tile_loc pin_old_loc, t_physical_tile_loc pin_new_loc, bool is_output_pin) { - auto& place_move_ctx = placer_state_.move(); - std::vector& bb_edge_new = layer_ts_bb_edge_new_[net_id]; std::vector& bb_coord_new = layer_ts_bb_coord_new_[net_id]; vtr::NdMatrixProxy bb_pin_sink_count_new = ts_layer_sink_pin_count_[size_t(net_id)]; @@ -905,13 +852,13 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, return; } - const vtr::NdMatrixProxy curr_layer_pin_sink_count = (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) ? place_move_ctx.num_sink_pin_layer[size_t(net_id)] : bb_pin_sink_count_new; + const vtr::NdMatrixProxy curr_layer_pin_sink_count = (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) ? num_sink_pin_layer_[size_t(net_id)] : bb_pin_sink_count_new; const std::vector*curr_bb_edge, *curr_bb_coord; if (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) { /* The net had NOT been updated before, could use the old values */ - curr_bb_edge = &place_move_ctx.layer_bb_num_on_edges[net_id]; - curr_bb_coord = &place_move_ctx.layer_bb_coords[net_id]; + curr_bb_edge = &layer_bb_num_on_edges_[net_id]; + curr_bb_coord = &layer_bb_coords_[net_id]; bb_update_status_[net_id] = NetUpdateState::UPDATED_ONCE; } else { /* The net had been updated before, must use the new values */ @@ -960,13 +907,13 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, } inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, - const t_physical_tile_loc& pin_old_loc, - const t_physical_tile_loc& pin_new_loc, - const std::vector& curr_bb_edge, - const std::vector& curr_bb_coord, - vtr::NdMatrixProxy bb_pin_sink_count_new, - std::vector& bb_edge_new, - std::vector& bb_coord_new) { + const t_physical_tile_loc& pin_old_loc, + const t_physical_tile_loc& pin_new_loc, + const std::vector& curr_bb_edge, + const std::vector& curr_bb_coord, + vtr::NdMatrixProxy bb_pin_sink_count_new, + std::vector& bb_edge_new, + std::vector& bb_coord_new) { int x_old = pin_old_loc.x; int x_new = pin_new_loc.x; @@ -979,13 +926,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, if (x_new < x_old) { if (x_old == curr_bb_coord[layer_num].xmax) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[layer_num].xmax, - curr_bb_coord[layer_num].xmax, - bb_edge_new[layer_num].xmax, - bb_coord_new[layer_num].xmax); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[layer_num].xmax, + curr_bb_coord[layer_num].xmax, + bb_edge_new[layer_num].xmax, + bb_coord_new[layer_num].xmax); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1002,13 +949,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, } else if (x_new > x_old) { if (x_old == curr_bb_coord[layer_num].xmin) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[layer_num].xmin, - curr_bb_coord[layer_num].xmin, - bb_edge_new[layer_num].xmin, - bb_coord_new[layer_num].xmin); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[layer_num].xmin, + curr_bb_coord[layer_num].xmin, + bb_edge_new[layer_num].xmin, + bb_coord_new[layer_num].xmin); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1026,13 +973,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, if (y_new < y_old) { if (y_old == curr_bb_coord[layer_num].ymax) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[layer_num].ymax, - curr_bb_coord[layer_num].ymax, - bb_edge_new[layer_num].ymax, - bb_coord_new[layer_num].ymax); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[layer_num].ymax, + curr_bb_coord[layer_num].ymax, + bb_edge_new[layer_num].ymax, + bb_coord_new[layer_num].ymax); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1049,13 +996,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, } else if (y_new > y_old) { if (y_old == curr_bb_coord[layer_num].ymin) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[layer_num].ymin, - curr_bb_coord[layer_num].ymin, - bb_edge_new[layer_num].ymin, - bb_coord_new[layer_num].ymin); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[layer_num].ymin, + curr_bb_coord[layer_num].ymin, + bb_edge_new[layer_num].ymin, + bb_coord_new[layer_num].ymin); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1072,13 +1019,13 @@ inline void NetCostHandler::update_bb_same_layer_(ClusterNetId net_id, } inline void NetCostHandler::update_bb_layer_changed_(ClusterNetId net_id, - const t_physical_tile_loc& pin_old_loc, - const t_physical_tile_loc& pin_new_loc, - const std::vector& curr_bb_edge, - const std::vector& curr_bb_coord, - vtr::NdMatrixProxy bb_pin_sink_count_new, - std::vector& bb_edge_new, - std::vector& bb_coord_new) { + const t_physical_tile_loc& pin_old_loc, + const t_physical_tile_loc& pin_new_loc, + const std::vector& curr_bb_edge, + const std::vector& curr_bb_coord, + vtr::NdMatrixProxy bb_pin_sink_count_new, + std::vector& bb_edge_new, + std::vector& bb_coord_new) { int x_old = pin_old_loc.x; int y_old = pin_old_loc.y; @@ -1088,31 +1035,31 @@ inline void NetCostHandler::update_bb_layer_changed_(ClusterNetId net_id, VTR_ASSERT_SAFE(old_layer_num != new_layer_num); /* - This funcitn is called when BB per layer is used and when the moving block is moving from one layer to another. - Thus, we need to update bounding box on both "from" and "to" layer. Here, we update the bounding box on "from" or - "old_layer". Then, "add_block_to_bb" is called to update the bounding box on the new layer. - */ + * This funcitn is called when BB per layer is used and when the moving block is moving from one layer to another. + * Thus, we need to update bounding box on both "from" and "to" layer. Here, we update the bounding box on "from" or + * "old_layer". Then, "add_block_to_bb" is called to update the bounding box on the new layer. + */ if (x_old == curr_bb_coord[old_layer_num].xmax) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[old_layer_num].xmax, - curr_bb_coord[old_layer_num].xmax, - bb_edge_new[old_layer_num].xmax, - bb_coord_new[old_layer_num].xmax); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[old_layer_num].xmax, + curr_bb_coord[old_layer_num].xmax, + bb_edge_new[old_layer_num].xmax, + bb_coord_new[old_layer_num].xmax); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } } else if (x_old == curr_bb_coord[old_layer_num].xmin) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[old_layer_num].xmin, - curr_bb_coord[old_layer_num].xmin, - bb_edge_new[old_layer_num].xmin, - bb_coord_new[old_layer_num].xmin); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[old_layer_num].xmin, + curr_bb_coord[old_layer_num].xmin, + bb_edge_new[old_layer_num].xmin, + bb_coord_new[old_layer_num].xmin); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1120,25 +1067,25 @@ inline void NetCostHandler::update_bb_layer_changed_(ClusterNetId net_id, if (y_old == curr_bb_coord[old_layer_num].ymax) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[old_layer_num].ymax, - curr_bb_coord[old_layer_num].ymax, - bb_edge_new[old_layer_num].ymax, - bb_coord_new[old_layer_num].ymax); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[old_layer_num].ymax, + curr_bb_coord[old_layer_num].ymax, + bb_edge_new[old_layer_num].ymax, + bb_coord_new[old_layer_num].ymax); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } } else if (y_old == curr_bb_coord[old_layer_num].ymin) { update_bb_edge_(net_id, - bb_edge_new, - bb_coord_new, - bb_pin_sink_count_new, - curr_bb_edge[old_layer_num].ymin, - curr_bb_coord[old_layer_num].ymin, - bb_edge_new[old_layer_num].ymin, - bb_coord_new[old_layer_num].ymin); + bb_edge_new, + bb_coord_new, + bb_pin_sink_count_new, + curr_bb_edge[old_layer_num].ymin, + curr_bb_coord[old_layer_num].ymin, + bb_edge_new[old_layer_num].ymin, + bb_coord_new[old_layer_num].ymin); if (bb_update_status_[net_id] == NetUpdateState::GOT_FROM_SCRATCH) { return; } @@ -1167,18 +1114,18 @@ static void update_bb_pin_sink_count(const t_physical_tile_loc& pin_old_loc, } inline void NetCostHandler::update_bb_edge_(ClusterNetId net_id, - std::vector& bb_edge_new, - std::vector& bb_coord_new, - vtr::NdMatrixProxy bb_layer_pin_sink_count, - const int& old_num_block_on_edge, - const int& old_edge_coord, - int& new_num_block_on_edge, - int& new_edge_coord) { + std::vector& bb_edge_new, + std::vector& bb_coord_new, + vtr::NdMatrixProxy bb_layer_pin_sink_count, + const int& old_num_block_on_edge, + const int& old_edge_coord, + int& new_num_block_on_edge, + int& new_edge_coord) { if (old_num_block_on_edge == 1) { get_layer_bb_from_scratch_(net_id, - bb_edge_new, - bb_coord_new, - bb_layer_pin_sink_count); + bb_edge_new, + bb_coord_new, + bb_layer_pin_sink_count); bb_update_status_[net_id] = NetUpdateState::GOT_FROM_SCRATCH; return; } else { @@ -1196,10 +1143,10 @@ static void add_block_to_bb(const t_physical_tile_loc& new_pin_loc, int y_new = new_pin_loc.y; /* - This function is called to only update the bounding box on the new layer from a block - moving to this layer from another layer. Thus, we only need to assess the effect of this - new block on the edges. - */ + * This function is called to only update the bounding box on the new layer from a block + * moving to this layer from another layer. Thus, we only need to assess the effect of this + * new block on the edges. + */ if (x_new > bb_coord_old.xmax) { bb_edge_new.xmax = 1; @@ -1230,15 +1177,16 @@ static void add_block_to_bb(const t_physical_tile_loc& new_pin_loc, } } -void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, - t_bb& coords, - t_bb& num_on_edges, - vtr::NdMatrixProxy num_sink_pin_layer) { +void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, bool use_ts) { const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); const auto& grid = device_ctx.grid; const auto& blk_loc_registry = placer_state_.blk_loc_registry(); + t_bb& coords = use_ts ? ts_bb_coord_new_[net_id] : bb_coords_[net_id]; + t_bb& num_on_edges = use_ts ? ts_bb_edge_new_[net_id] : bb_num_on_edges_[net_id]; + vtr::NdMatrixProxy num_sink_pin_layer = use_ts ? ts_layer_sink_pin_count_[(size_t)net_id] : num_sink_pin_layer_[(size_t)net_id]; + // get the source pin's location ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); t_physical_tile_loc source_pin_loc = blk_loc_registry.get_coordinate_of_pin(source_pin_id); @@ -1382,12 +1330,11 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, } } - double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { // Finds the cost due to one net by looking at its coordinate bounding box. auto& cluster_ctx = g_vpr_ctx.clustering(); - const t_bb& bb = use_ts ? ts_bb_coord_new_[net_id] : placer_state_.move().bb_coords[net_id]; + const t_bb& bb = use_ts ? ts_bb_coord_new_[net_id] : bb_coords_[net_id]; const double crossing = wirelength_crossing_count(cluster_ctx.clb_nlist.net_pins(net_id).size()); @@ -1417,20 +1364,15 @@ double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { return ncost; } - -double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use_ts) { - const auto& move_ctx = placer_state_.move(); - +double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id, bool use_ts) { // Per-layer bounding box of the net - const std::vector& bb = use_ts ? layer_ts_bb_coord_new_[net_id] : move_ctx.layer_bb_coords[net_id]; - const vtr::NdMatrixProxy layer_pin_sink_count = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : move_ctx.num_sink_pin_layer[size_t(net_id)]; + const std::vector& bb = use_ts ? layer_ts_bb_coord_new_[net_id] : layer_bb_coords_[net_id]; + const vtr::NdMatrixProxy layer_pin_sink_count = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : num_sink_pin_layer_[size_t(net_id)]; // Finds the cost due to one net by looking at its coordinate bounding box double ncost = 0.; int num_layers = g_vpr_ctx.device().grid.get_num_layers(); - - for (int layer_num = 0; layer_num < num_layers; layer_num++) { VTR_ASSERT(layer_pin_sink_count[layer_num] != OPEN); if (layer_pin_sink_count[layer_num] == 0) { @@ -1454,7 +1396,7 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use * chan?_place_cost_fac_ objects can handle -1 indices internally. */ - const auto[chanx_cost_fac, chany_cost_fac] = get_chanxy_cost_fac_(bb[layer_num]); + const auto [chanx_cost_fac, chany_cost_fac] = get_chanxy_cost_fac_(bb[layer_num]); ncost += (bb[layer_num].xmax - bb[layer_num].xmin + 1) * chanx_cost_fac; ncost += (bb[layer_num].ymax - bb[layer_num].ymin + 1) * chany_cost_fac; ncost *= crossing; @@ -1463,7 +1405,8 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use return ncost; } -static double get_net_wirelength_estimate(ClusterNetId net_id, const t_bb& bb) { +double NetCostHandler::get_net_wirelength_estimate_(ClusterNetId net_id) const { + const t_bb& bb = bb_coords_[net_id]; auto& cluster_ctx = g_vpr_ctx.clustering(); double crossing = wirelength_crossing_count(cluster_ctx.clb_nlist.net_pins(net_id).size()); @@ -1482,23 +1425,26 @@ static double get_net_wirelength_estimate(ClusterNetId net_id, const t_bb& bb) { return ncost; } -double NetCostHandler::get_net_wirelength_from_layer_bb_(ClusterNetId net_id) { +double NetCostHandler::get_net_wirelength_from_layer_bb_(ClusterNetId net_id) const { /* WMF: Finds the estimate of wirelength due to one net by looking at * * its coordinate bounding box. */ - const auto& move_ctx = placer_state_.move(); - const std::vector& bb = move_ctx.layer_bb_coords[net_id]; - const auto& layer_pin_sink_count = move_ctx.num_sink_pin_layer[size_t(net_id)]; + const std::vector& bb = layer_bb_coords_[net_id]; + const vtr::NdMatrixProxy net_layer_pin_sink_count = num_sink_pin_layer_[size_t(net_id)]; double ncost = 0.; - const int num_layers = g_vpr_ctx.device().grid.get_num_layers(); + VTR_ASSERT_SAFE(static_cast(bb.size()) == g_vpr_ctx.device().grid.get_num_layers()); - for (int layer_num = 0; layer_num < num_layers; layer_num++) { - VTR_ASSERT_SAFE(layer_pin_sink_count[layer_num] != OPEN); - if (layer_pin_sink_count[layer_num] == 0) { + for (size_t layer_num = 0; layer_num < bb.size(); layer_num++) { + VTR_ASSERT_SAFE(net_layer_pin_sink_count[layer_num] != OPEN); + if (net_layer_pin_sink_count[layer_num] == 0) { continue; } - double crossing = wirelength_crossing_count(layer_pin_sink_count[layer_num] + 1); + + // The reason we add 1 to the number of sink pins is because when per-layer bounding box is used, + // we want to get the estimated wirelength of the given layer assuming that the source pin is + // also on that layer + double crossing = wirelength_crossing_count(net_layer_pin_sink_count[layer_num] + 1); /* Could insert a check for xmin == xmax. In that case, assume * * connection will be made with no bends and hence no x-cost. * @@ -1515,23 +1461,11 @@ double NetCostHandler::get_net_wirelength_from_layer_bb_(ClusterNetId net_id) { } float NetCostHandler::get_chanz_cost_factor_(const t_bb& bb) { - int num_inter_dir_conn; - - if (bb.xmin == 0 && bb.ymin == 0) { - num_inter_dir_conn = acc_tile_num_inter_die_conn_[bb.xmax][bb.ymax]; - } else if (bb.xmin == 0) { - num_inter_dir_conn = acc_tile_num_inter_die_conn_[bb.xmax][bb.ymax] - - acc_tile_num_inter_die_conn_[bb.xmax][bb.ymin-1]; - } else if (bb.ymin == 0) { - num_inter_dir_conn = acc_tile_num_inter_die_conn_[bb.xmax][bb.ymax] - - acc_tile_num_inter_die_conn_[bb.xmin-1][bb.ymax]; - } else { - num_inter_dir_conn = acc_tile_num_inter_die_conn_[bb.xmax][bb.ymax] - - acc_tile_num_inter_die_conn_[bb.xmin-1][bb.ymax] - - acc_tile_num_inter_die_conn_[bb.xmax][bb.ymin-1] + - acc_tile_num_inter_die_conn_[bb.xmin-1][bb.ymin-1]; - } - + int num_inter_dir_conn = acc_tile_num_inter_die_conn_.get_sum(bb.xmin, + bb.ymin, + bb.xmax, + bb.ymax); + float z_cost_factor; if (num_inter_dir_conn == 0) { return 1.0f; @@ -1541,7 +1475,6 @@ float NetCostHandler::get_chanz_cost_factor_(const t_bb& bb) { } return z_cost_factor; - } double NetCostHandler::recompute_bb_cost_() { @@ -1549,8 +1482,8 @@ double NetCostHandler::recompute_bb_cost_() { auto& cluster_ctx = g_vpr_ctx.clustering(); - for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ - if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ + for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { /* for each net ... */ + if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ /* Bounding boxes don't have to be recomputed; they're correct. */ cost += net_cost_[net_id]; } @@ -1571,7 +1504,7 @@ static double wirelength_crossing_count(size_t fanout) { } void NetCostHandler::set_bb_delta_cost_(double& bb_delta_c) { - for (const ClusterNetId ts_net: ts_nets_to_update_) { + for (const ClusterNetId ts_net : ts_nets_to_update_) { ClusterNetId net_id = ts_net; proposed_net_cost_[net_id] = get_net_bb_cost_functor_(net_id); @@ -1621,7 +1554,6 @@ void NetCostHandler::find_affected_nets_and_update_costs(const PlaceDelayModel* void NetCostHandler::update_move_nets() { /* update net cost functions and reset flags. */ auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_move_ctx = placer_state_.mutable_move(); for (const ClusterNetId ts_net : ts_nets_to_update_) { ClusterNetId net_id = ts_net; @@ -1629,7 +1561,7 @@ void NetCostHandler::update_move_nets() { set_ts_bb_coord_(net_id); for (int layer_num = 0; layer_num < g_vpr_ctx.device().grid.get_num_layers(); layer_num++) { - place_move_ctx.num_sink_pin_layer[size_t(net_id)][layer_num] = ts_layer_sink_pin_count_[size_t(net_id)][layer_num]; + num_sink_pin_layer_[size_t(net_id)][layer_num] = ts_layer_sink_pin_count_[size_t(net_id)][layer_num]; } if (cluster_ctx.clb_nlist.net_sinks(net_id).size() >= SMALL_NET) { @@ -1682,20 +1614,146 @@ void NetCostHandler::recompute_costs_from_scratch(const PlaceDelayModel* delay_m } } +double NetCostHandler::get_total_wirelength_estimate() const { + const auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + + double estimated_wirelength = 0.0; + for (ClusterNetId net_id : clb_nlist.nets()) { /* for each net ... */ + if (!clb_nlist.net_is_ignored(net_id)) { /* Do only if not ignored. */ + if (cube_bb_) { + estimated_wirelength += get_net_wirelength_estimate_(net_id); + } else { + estimated_wirelength += get_net_wirelength_from_layer_bb_(net_id); + } + } + } + + return estimated_wirelength; +} + void NetCostHandler::set_ts_bb_coord_(const ClusterNetId net_id) { - auto& place_move_ctx = placer_state_.mutable_move(); if (cube_bb_) { - place_move_ctx.bb_coords[net_id] = ts_bb_coord_new_[net_id]; + bb_coords_[net_id] = ts_bb_coord_new_[net_id]; } else { - place_move_ctx.layer_bb_coords[net_id] = layer_ts_bb_coord_new_[net_id]; + layer_bb_coords_[net_id] = layer_ts_bb_coord_new_[net_id]; } } void NetCostHandler::set_ts_edge_(const ClusterNetId net_id) { - auto& place_move_ctx = placer_state_.mutable_move(); if (cube_bb_) { - place_move_ctx.bb_num_on_edges[net_id] = ts_bb_edge_new_[net_id]; + bb_num_on_edges_[net_id] = ts_bb_edge_new_[net_id]; } else { - place_move_ctx.layer_bb_num_on_edges[net_id] = layer_ts_bb_edge_new_[net_id]; + layer_bb_num_on_edges_[net_id] = layer_ts_bb_edge_new_[net_id]; + } +} + +t_bb NetCostHandler::union_2d_bb(ClusterNetId net_id) const { + t_bb merged_bb; + const std::vector& bb_vec = layer_bb_coords_[net_id]; + + // Not all 2d_bbs are valid. Thus, if one of the coordinates in the 2D_bb is not valid (equal to OPEN), + // we need to skip it. + for (const t_2D_bb& layer_bb : bb_vec) { + if (layer_bb.xmin == OPEN) { + VTR_ASSERT_DEBUG(layer_bb.xmax == OPEN); + VTR_ASSERT_DEBUG(layer_bb.ymin == OPEN); + VTR_ASSERT_DEBUG(layer_bb.ymax == OPEN); + VTR_ASSERT_DEBUG(layer_bb.layer_num == OPEN); + continue; + } + if (merged_bb.xmin == OPEN || layer_bb.xmin < merged_bb.xmin) { + merged_bb.xmin = layer_bb.xmin; + } + if (merged_bb.xmax == OPEN || layer_bb.xmax > merged_bb.xmax) { + merged_bb.xmax = layer_bb.xmax; + } + if (merged_bb.ymin == OPEN || layer_bb.ymin < merged_bb.ymin) { + merged_bb.ymin = layer_bb.ymin; + } + if (merged_bb.ymax == OPEN || layer_bb.ymax > merged_bb.ymax) { + merged_bb.ymax = layer_bb.ymax; + } + if (merged_bb.layer_min == OPEN || layer_bb.layer_num < merged_bb.layer_min) { + merged_bb.layer_min = layer_bb.layer_num; + } + if (merged_bb.layer_max == OPEN || layer_bb.layer_num > merged_bb.layer_max) { + merged_bb.layer_max = layer_bb.layer_num; + } } + + return merged_bb; +} + +std::pair NetCostHandler::union_2d_bb_incr(ClusterNetId net_id) const { + t_bb merged_num_edge; + t_bb merged_bb; + + const std::vector& num_edge_vec = layer_bb_num_on_edges_[net_id]; + const std::vector& bb_vec = layer_bb_coords_[net_id]; + + for (const t_2D_bb& layer_bb : bb_vec) { + if (layer_bb.xmin == OPEN) { + VTR_ASSERT_SAFE(layer_bb.xmax == OPEN); + VTR_ASSERT_SAFE(layer_bb.ymin == OPEN); + VTR_ASSERT_SAFE(layer_bb.ymax == OPEN); + VTR_ASSERT_SAFE(layer_bb.layer_num == OPEN); + continue; + } + if (merged_bb.xmin == OPEN || layer_bb.xmin <= merged_bb.xmin) { + if (layer_bb.xmin == merged_bb.xmin) { + VTR_ASSERT_SAFE(merged_num_edge.xmin != OPEN); + merged_num_edge.xmin += num_edge_vec[layer_bb.layer_num].xmin; + } else { + merged_num_edge.xmin = num_edge_vec[layer_bb.layer_num].xmin; + } + merged_bb.xmin = layer_bb.xmin; + } + if (merged_bb.xmax == OPEN || layer_bb.xmax >= merged_bb.xmax) { + if (layer_bb.xmax == merged_bb.xmax) { + VTR_ASSERT_SAFE(merged_num_edge.xmax != OPEN); + merged_num_edge.xmax += num_edge_vec[layer_bb.layer_num].xmax; + } else { + merged_num_edge.xmax = num_edge_vec[layer_bb.layer_num].xmax; + } + merged_bb.xmax = layer_bb.xmax; + } + if (merged_bb.ymin == OPEN || layer_bb.ymin <= merged_bb.ymin) { + if (layer_bb.ymin == merged_bb.ymin) { + VTR_ASSERT_SAFE(merged_num_edge.ymin != OPEN); + merged_num_edge.ymin += num_edge_vec[layer_bb.layer_num].ymin; + } else { + merged_num_edge.ymin = num_edge_vec[layer_bb.layer_num].ymin; + } + merged_bb.ymin = layer_bb.ymin; + } + if (merged_bb.ymax == OPEN || layer_bb.ymax >= merged_bb.ymax) { + if (layer_bb.ymax == merged_bb.ymax) { + VTR_ASSERT_SAFE(merged_num_edge.ymax != OPEN); + merged_num_edge.ymax += num_edge_vec[layer_bb.layer_num].ymax; + } else { + merged_num_edge.ymax = num_edge_vec[layer_bb.layer_num].ymax; + } + merged_bb.ymax = layer_bb.ymax; + } + if (merged_bb.layer_min == OPEN || layer_bb.layer_num <= merged_bb.layer_min) { + if (layer_bb.layer_num == merged_bb.layer_min) { + VTR_ASSERT_SAFE(merged_num_edge.layer_min != OPEN); + merged_num_edge.layer_min += num_edge_vec[layer_bb.layer_num].layer_num; + } else { + merged_num_edge.layer_min = num_edge_vec[layer_bb.layer_num].layer_num; + } + merged_bb.layer_min = layer_bb.layer_num; + } + if (merged_bb.layer_max == OPEN || layer_bb.layer_num >= merged_bb.layer_max) { + if (layer_bb.layer_num == merged_bb.layer_max) { + VTR_ASSERT_SAFE(merged_num_edge.layer_max != OPEN); + merged_num_edge.layer_max += num_edge_vec[layer_bb.layer_num].layer_num; + } else { + merged_num_edge.layer_max = num_edge_vec[layer_bb.layer_num].layer_num; + } + merged_bb.layer_max = layer_bb.layer_num; + } + } + + return std::make_pair(merged_num_edge, merged_bb); } diff --git a/vpr/src/place/net_cost_handler.h b/vpr/src/place/net_cost_handler.h index 2b8e59af88f..ee60d5ed348 100644 --- a/vpr/src/place/net_cost_handler.h +++ b/vpr/src/place/net_cost_handler.h @@ -7,14 +7,14 @@ #pragma once #include "place_delay_model.h" -#include "timing_place.h" #include "move_transactions.h" #include "place_util.h" -#include "vtr_ndoffsetmatrix.h" +#include "vtr_prefix_sum.h" #include class PlacerState; +class PlacerCriticalities; /** * @brief The method used to calculate placement cost @@ -29,7 +29,6 @@ enum class e_cost_methods { CHECK }; - class NetCostHandler { public: NetCostHandler() = delete; @@ -59,33 +58,35 @@ class NetCostHandler { * non_updateable_bb routine, to provide a cost which can be * used to check the correctness of the other routine. * @param method The method used to calculate placement cost. - * @return The bounding box cost of the placement. - */ - double comp_bb_cost(e_cost_methods method); - - /** - * @brief Find all the nets and pins affected by this swap and update costs. - * - * Find all the nets affected by this swap and update the bounding box (wiring) - * costs. This cost function doesn't depend on the timing info. - * - * Find all the connections affected by this swap and update the timing cost. - * For a connection to be affected, it not only needs to be on or driven by - * a block, but it also needs to have its delay changed. Otherwise, it will - * not be added to the affected_pins structure. - * - * For more, see update_td_delta_costs(). - * - * The timing costs are calculated by getting the new connection delays, - * multiplied by the connection criticalities returned by the timing - * analyzer. These timing costs are stored in the proposed_* data structures. - * - * The change in the bounding box cost is stored in `bb_delta_c`. - * The change in the timing cost is stored in `timing_delta_c`. - * ts_nets_to_update is also extended with the latest net. - * - * @return The number of affected nets. - */ + * @return (bounding box cost of the placement, estimated wirelength) + * + * @note The returned estimated wirelength is valid only when method == CHECK + */ + std::pair comp_bb_cost(e_cost_methods method); + + /** + * @brief Find all the nets and pins affected by this swap and update costs. + * + * Find all the nets affected by this swap and update the bounding box (wiring) + * costs. This cost function doesn't depend on the timing info. + * + * Find all the connections affected by this swap and update the timing cost. + * For a connection to be affected, it not only needs to be on or driven by + * a block, but it also needs to have its delay changed. Otherwise, it will + * not be added to the affected_pins structure. + * + * For more, see update_td_delta_costs(). + * + * The timing costs are calculated by getting the new connection delays, + * multiplied by the connection criticalities returned by the timing + * analyzer. These timing costs are stored in the proposed_* data structures. + * + * The change in the bounding box cost is stored in `bb_delta_c`. + * The change in the timing cost is stored in `timing_delta_c`. + * ts_nets_to_update is also extended with the latest net. + * + * @return The number of affected nets. + */ void find_affected_nets_and_update_costs(const PlaceDelayModel* delay_model, const PlacerCriticalities* criticalities, t_pl_blocks_to_be_moved& blocks_affected, @@ -120,6 +121,11 @@ class NetCostHandler { const PlacerCriticalities* criticalities, t_placer_costs& costs); + /** + * @brief Get the total wirelength estimate of all nets. + */ + double get_total_wirelength_estimate() const; + private: ///@brief Specifies whether the bounding box is computed using cube method or per-layer method. bool cube_bb_; @@ -130,7 +136,7 @@ class NetCostHandler { ///@brief Contains some parameter that determine how the placement cost is computed. const t_placer_opts& placer_opts_; ///@brief Points to the proper method for computing the bounding box cost from scratch. - std::function comp_bb_cost_functor_; + std::function(e_cost_methods method)> comp_bb_cost_functor_; ///@brief Points to the proper method for updating the bounding box of a net. std::function update_bb_functor_; ///@brief Points to the proper method for getting the bounding box cost of a net @@ -148,12 +154,20 @@ class NetCostHandler { }; /** - * @brief The wire length estimation is based on the bounding box of the net. In the case of the 2D architecture, - * we use a 3D BB with the z-dimension (layer) set to 1. In the case of 3D architecture, there 2 types of bounding box: - * 3D and per-layer. The type is determined at the beginning of the placement and stored in the placement context. - * If the bonding box is of the type 3D, ts_bb_coord_new and ts_bb_edge_new are used. Otherwise, layer_ts_bb_edge_new and - * layer_ts_bb_coord_new are used. + * @brief The wire length estimation is based on the bounding box of the net. + * + * For 2D architectures, we use a 3D bounding box with the layer (z) set to 1. + * For 3D architectures, we support two types: full 3D and per-layer bounding boxes. + * The type is set at the start of placement and stored in the placement context. + * + * If using full 3D, `ts_bb_coord_new_` and `ts_bb_edge_new_` are used. + * If using per-layer, `layer_ts_bb_coord_new_` and `layer_ts_bb_edge_new_` are used. + * + * Temporary `ts_*` data members store the bounding box updates for nets affected by a move. + * If the move is accepted, these updates are copied to the permanent data members that store + * bounding box information for all nets. */ + /* [0...cluster_ctx.clb_nlist.nets().size()-1] -> 3D bounding box*/ vtr::vector ts_bb_coord_new_, ts_bb_edge_new_; /* [0...cluster_ctx.clb_nlist.nets().size()-1][0...num_layers-1] -> 2D bonding box on a layer*/ @@ -163,6 +177,20 @@ class NetCostHandler { /* [0...num_affected_nets] -> net_id of the affected nets */ std::vector ts_nets_to_update_; + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each of a net's bounding box (to allow efficient updates) + vtr::vector bb_num_on_edges_; + + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the bounding box coordinates of a net's bounding box + vtr::vector bb_coords_; + + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each of a net's bounding box (to allow efficient updates) + vtr::vector> layer_bb_num_on_edges_; + + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the bounding box coordinates of a net's bounding box + vtr::vector> layer_bb_coords_; + + // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each layer () + vtr::Matrix num_sink_pin_layer_; /** * @brief In each of these vectors, there is one entry per cluster level net: @@ -195,8 +223,8 @@ class NetCostHandler { * number of tracks in that direction; for other cost functions they * will never be used. */ - vtr::NdOffsetMatrix acc_chanx_width_; // [-1...device_ctx.grid.width()-1] - vtr::NdOffsetMatrix acc_chany_width_; // [-1...device_ctx.grid.height()-1] + vtr::PrefixSum1D acc_chanx_width_; // [0..device_ctx.grid.width()-1] + vtr::PrefixSum1D acc_chany_width_; // [0..device_ctx.grid.height()-1] /** * @brief The matrix below is used to calculate a chanz_place_cost_fac based on the average channel width in @@ -206,31 +234,30 @@ class NetCostHandler { * (x=0,y=0) to (x,y). Given this, we can compute the average number of inter-die connections over a (xlow,ylow) to (xhigh,yhigh) * region in O(1) (by adding and subtracting 4 entries) */ - vtr::NdMatrix acc_tile_num_inter_die_conn_; // [0..grid_width-1][0..grid_height-1] - + vtr::PrefixSum2D acc_tile_num_inter_die_conn_; // [0..grid_width-1][0..grid_height-1] private: /** - * @brief Update the bounding box (3D) of the net connected to blk_pin. The old and new locations of the pin are - * stored in pl_moved_block. The updated bounding box will be stored in ts data structures. Do not update the net - * cost here since it should only be updated once per net, not once per pin. - */ + * @brief Update the bounding box (3D) of the net connected to blk_pin. The old and new locations of the pin are + * stored in pl_moved_block. The updated bounding box will be stored in ts data structures. Do not update the net + * cost here since it should only be updated once per net, not once per pin. + */ void update_net_bb_(const ClusterNetId net, const ClusterBlockId blk, const ClusterPinId blk_pin, const t_pl_moved_block& pl_moved_block); /** - * @brief Call suitable function based on the bounding box type to update the bounding box of the net connected to pin_id. Also, - * call the function to update timing information if the placement algorithm is timing-driven. - * @param delay_model Timing delay model used by placer - * @param criticalities Connections timing criticalities - * @param pin_id Pin ID of the moving pin - * @param moving_blk_inf Data structure that holds information, e.g., old location and new location, about all moving blocks - * @param affected_pins Netlist pins which are affected, in terms placement cost, by the proposed move. - * @param timing_delta_c Timing cost change based on the proposed move - * @param is_src_moving Is the moving pin the source of a net. - */ + * @brief Call suitable function based on the bounding box type to update the bounding box of the net connected to pin_id. Also, + * call the function to update timing information if the placement algorithm is timing-driven. + * @param delay_model Timing delay model used by placer + * @param criticalities Connections timing criticalities + * @param pin_id Pin ID of the moving pin + * @param moving_blk_inf Data structure that holds information, e.g., old location and new location, about all moving blocks + * @param affected_pins Netlist pins which are affected, in terms placement cost, by the proposed move. + * @param timing_delta_c Timing cost change based on the proposed move + * @param is_src_moving Is the moving pin the source of a net. + */ void update_net_info_on_pin_move_(const PlaceDelayModel* delay_model, const PlacerCriticalities* criticalities, const ClusterPinId pin_id, @@ -240,10 +267,10 @@ class NetCostHandler { bool is_src_moving); /** - * @brief Calculates and returns the total bb (wirelength) cost change that would result from moving the blocks - * indicated in the blocks_affected data structure. - * @param bb_delta_c Cost difference after and before moving the block - */ + * @brief Calculates and returns the total bb (wirelength) cost change that would result from moving the blocks + * indicated in the blocks_affected data structure. + * @param bb_delta_c Cost difference after and before moving the block + */ void set_bb_delta_cost_(double& bb_delta_c); /** @@ -253,18 +280,16 @@ class NetCostHandler { * @details This is only useful for the cost function that takes the length of the net bounding box in each * dimension divided by the average number of tracks in that direction. For other cost functions, you don't * have to bother calling this routine; when using the cost function described above, however, you must always - * call this routine before you do any placement cost determination. The place_cost_exp factor specifies to - * what power the width of the channel should be taken -- larger numbers make narrower channels more expensive. + * call this routine before you do any placement cost determination. */ void alloc_and_load_chan_w_factors_for_place_cost_(); /** - * @brief Allocates and loads acc_tile_num_inter_die_conn_ which contains the accumulative number of inter-die - * conntections. - * - * @details This is only useful for multi-die FPGAs. The place_cost_exp factor specifies to - * what power the average number of inter-die connections should be take -- larger numbers make narrower channels more expensive. - */ + * @brief Allocates and loads acc_tile_num_inter_die_conn_ which contains the accumulative number of inter-die + * conntections. + * + * @details This is only useful for multi-die FPGAs. + */ void alloc_and_load_for_fast_vertical_cost_update_(); /** @@ -325,14 +350,9 @@ class NetCostHandler { * It updates both the coordinate and number of pins on each edge information. It should only be called when the bounding box * information is not valid. * @param net_id ID of the net which the moving pin belongs to - * @param coords Bounding box coordinates of the net. It is calculated in this function - * @param num_on_edges Net's number of blocks on the edges of the bounding box. It is calculated in this function. - * @param num_sink_pin_layer Net's number of sinks on each layer, calculated in this function. + * @param use_ts Specifies whether the `ts` bounding box is updated or the actual one. */ - void get_bb_from_scratch_(ClusterNetId net_id, - t_bb& coords, - t_bb& num_on_edges, - vtr::NdMatrixProxy num_sink_pin_layer); + void get_bb_from_scratch_(ClusterNetId net_id, bool use_ts); /** * @brief Calculate the per-layer BB of a large net from scratch and update coord, edge, and num_sink_pin_layer data structures. @@ -413,8 +433,8 @@ class NetCostHandler { int& new_edge_coord); /** - * @brief This function is called in update_layer_bb to update the net's bounding box incrementally if - * the pin under consideration change layer. + * @brief This function is called in update_layer_bb to update the net's bounding box incrementally if + * the pin under consideration change layer. * @param net_id ID of the net which the moving pin belongs to * @param pin_old_loc Old location of the moving pin * @param pin_new_loc New location of the moving pin @@ -445,70 +465,66 @@ class NetCostHandler { * @param bb_edge_new The new bb edge calculated by this function * @param bb_coord_new The new bb calculated by this function */ - inline void update_bb_same_layer_(ClusterNetId net_id, - const t_physical_tile_loc& pin_old_loc, - const t_physical_tile_loc& pin_new_loc, - const std::vector& curr_bb_edge, - const std::vector& curr_bb_coord, - vtr::NdMatrixProxy bb_pin_sink_count_new, - std::vector& bb_edge_new, - std::vector& bb_coord_new); - - /** - * @brief Computes the bounding box from scratch using 2D bounding boxes (per-layer mode) - * @param method The method used to calculate placement cost. Specifies whether the cost is - * computed from scratch or incrementally. - * @return Computed bounding box cost. - */ - double comp_per_layer_bb_cost_(e_cost_methods method); - - /** - * @brief Computes the bounding box from scratch using 3D bounding boxes (cube mode) - * @param method The method used to calculate placement cost. Specifies whether the cost is - * computed from scratch or incrementally. - * @return Computed bounding box cost. - */ - double comp_cube_bb_cost_(e_cost_methods method); - - /** - * @brief if "net" is not already stored as an affected net, add it in ts_nets_to_update. - * @param net ID of a net affected by a move - */ - void record_affected_net_(const ClusterNetId net); - - /** - * @brief To mitigate round-off errors, every once in a while, the costs of nets are summed up from scratch. - * This functions is called to do that for bb cost. It doesn't calculate the BBs from scratch, it would only add the costs again. - * @return Total bb (wirelength) cost for the placement - */ - double recompute_bb_cost_(); - - /** - * @brief Given the 3D BB, calculate the wire-length cost of the net - * @param net_id ID of the net which cost is requested. - * @param use_ts Specifies if the bounding box is retrieved from ts data structures - * or move context. - * @return Wirelength cost of the net - */ - double get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts); - - /** - * @brief Given the per-layer BB, calculate the wire-length cost of the net on each layer - * and return the sum of the costs - * @param net_id ID of the net which cost is requested. Currently unused - * @param use_ts Specifies whether the 'ts` bounding box is used to compute the - * cost or the one stored in placer_state_ - * @return Wirelength cost of the net - */ - double get_net_per_layer_bb_cost_(ClusterNetId net_id, bool use_ts); + inline void update_bb_same_layer_(ClusterNetId net_id, + const t_physical_tile_loc& pin_old_loc, + const t_physical_tile_loc& pin_new_loc, + const std::vector& curr_bb_edge, + const std::vector& curr_bb_coord, + vtr::NdMatrixProxy bb_pin_sink_count_new, + std::vector& bb_edge_new, + std::vector& bb_coord_new); /** - * @brief Given the per-layer BB, calculate the wire-length estimate of the net on each layer - * and return the sum of the lengths - * @param net_id ID of the net which wirelength estimate is requested - * @return Wirelength estimate of the net + * @brief Computes the bounding box from scratch using 2D bounding boxes (per-layer mode) + * @param method The method used to calculate placement cost. Specifies whether the cost is + * computed from scratch or incrementally. + * @return (bounding box cost of the placement, estimated wirelength) + * + * @note The returned estimated wirelength is valid only when method == CHECK + */ + std::pair comp_per_layer_bb_cost_(e_cost_methods method); + + /** + * @brief Computes the bounding box from scratch using 3D bounding boxes (cube mode) + * @param method The method used to calculate placement cost. Specifies whether the cost is + * computed from scratch or incrementally. + * @return (bounding box cost of the placement, estimated wirelength) + * + * @note The returned estimated wirelength is valid only when method == CHECK + */ + std::pair comp_cube_bb_cost_(e_cost_methods method); + + /** + * @brief if "net" is not already stored as an affected net, add it in ts_nets_to_update. + * @param net ID of a net affected by a move + */ + void record_affected_net_(const ClusterNetId net); + + /** + * @brief To mitigate round-off errors, every once in a while, the costs of nets are summed up from scratch. + * This functions is called to do that for bb cost. It doesn't calculate the BBs from scratch, it would only add the costs again. + * @return Total bb (wirelength) cost for the placement + */ + double recompute_bb_cost_(); + + /** + * @brief Given the 3D BB, calculate the wire-length cost of the net + * @param net_id ID of the net which cost is requested. + * @param use_ts Specifies if the bounding box is retrieved from ts data structures + * or move context. + * @return Wirelength cost of the net */ - double get_net_wirelength_from_layer_bb_(ClusterNetId net_id); + double get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts); + + /** + * @brief Given the per-layer BB, calculate the wire-length cost of the net on each layer + * and return the sum of the costs + * @param net_id ID of the net which cost is requested. Currently unused + * @param use_ts Specifies whether the 'ts` bounding box is used to compute the + * cost or the one stored in placer_state_ + * @return Wirelength cost of the net + */ + double get_net_per_layer_bb_cost_(ClusterNetId net_id, bool use_ts); /** * @brief Computes the inverse of average channel width for horizontal and @@ -522,10 +538,10 @@ class NetCostHandler { */ template std::pair get_chanxy_cost_fac_(const BBT& bb) { - const int total_chanx_width = acc_chanx_width_[bb.ymax] - acc_chanx_width_[bb.ymin - 1]; + const int total_chanx_width = acc_chanx_width_.get_sum(bb.ymin, bb.ymax); const double inverse_average_chanx_width = (bb.ymax - bb.ymin + 1.0) / total_chanx_width; - const int total_chany_width = acc_chany_width_[bb.xmax] - acc_chany_width_[bb.xmin - 1]; + const int total_chany_width = acc_chany_width_.get_sum(bb.xmin, bb.xmax); const double inverse_average_chany_width = (bb.xmax - bb.xmin + 1.0) / total_chany_width; return {inverse_average_chanx_width, inverse_average_chany_width}; @@ -541,6 +557,42 @@ class NetCostHandler { * @param bb Bounding box of the net which chanz cost factor is to be calculated * @return ChanZ cost factor */ - float get_chanz_cost_factor_(const t_bb& bb); + float get_chanz_cost_factor_(const t_bb& bb); + + /** + * @brief Given the 3D BB, calculate the wire-length estimate of the net + * @param net_id ID of the net which wirelength estimate is requested + * @param bb Bounding box of the net + * @return Wirelength estimate of the net + */ + double get_net_wirelength_estimate_(ClusterNetId net_id) const; + + /** + * @brief Given the per-layer BB, calculate the wire-length estimate of the net on each layer + * and return the sum of the lengths + * @param bb Per-layer BB of the net + * @param net_layer_pin_sink_count Number of sink pins on each layer for the net + * @return Wirelength estimate of the net + */ + double get_net_wirelength_from_layer_bb_(ClusterNetId net_id) const; + + // Bounding-box getters + public: + inline const t_bb& bb_num_on_edges(ClusterNetId net_id) const { return bb_num_on_edges_[net_id]; } + inline const t_bb& bb_coords(ClusterNetId net_id) const { return bb_coords_[net_id]; } + + /** + * @brief Iterate over all layers and get the maximum x and y over that layers that have a valid value. set the layer min and max + * based on the layers that have a valid BB. + * @return 3D bounding box + */ + t_bb union_2d_bb(ClusterNetId net_id) const; + + /** + * @brief Iterate over all layers and get the maximum x and y over that layers that have a valid value. Create the "num_edge" in a similar way. This data structure + * stores how many blocks are on each edge of the BB. set the layer min and max based on the layers that have a valid BB. + * @return num_edge, 3D bb + */ + std::pair union_2d_bb_incr(ClusterNetId net_id) const; }; diff --git a/vpr/src/place/noc_place_utils.cpp b/vpr/src/place/noc_place_utils.cpp index 9f5fbb6045d..569408bb354 100644 --- a/vpr/src/place/noc_place_utils.cpp +++ b/vpr/src/place/noc_place_utils.cpp @@ -2,6 +2,8 @@ #include "noc_place_utils.h" #include "globals.h" +#include "physical_types_util.h" +#include "place_macro.h" #include "vtr_log.h" #include "vtr_assert.h" #include "vtr_random.h" @@ -20,7 +22,6 @@ #include #include - /** * @brief Randomly select a movable NoC router cluster blocks * @@ -79,8 +80,8 @@ void NocCostHandler::initial_noc_routing(const vtr::vector calculate_traffic_flow_latency_cost(const std::vector< noc_router_latency_component = noc_router_latency * num_of_routers_in_traffic_flow; } - // calculate the total traffic flow latency double latency = noc_router_latency_component + noc_link_latency_component; @@ -686,10 +686,10 @@ double NocCostHandler::get_link_congestion_cost(const NocLink& link) const { void normalize_noc_cost_weighting_factor(t_noc_opts& noc_opts) { // calculate the sum of all weighting factors - double weighting_factor_sum = noc_opts.noc_latency_weighting + - noc_opts.noc_latency_constraints_weighting + - noc_opts.noc_congestion_weighting + - noc_opts.noc_aggregate_bandwidth_weighting; + double weighting_factor_sum = noc_opts.noc_latency_weighting + + noc_opts.noc_latency_constraints_weighting + + noc_opts.noc_congestion_weighting + + noc_opts.noc_aggregate_bandwidth_weighting; // Normalize weighting factor so they add up to 1 noc_opts.noc_aggregate_bandwidth_weighting /= weighting_factor_sum; @@ -871,6 +871,7 @@ static bool select_random_router_cluster(ClusterBlockId& b_from, e_create_move propose_router_swap(t_pl_blocks_to_be_moved& blocks_affected, float rlim, const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, vtr::RngContainer& rng) { // block ID for the randomly selected router cluster ClusterBlockId b_from; @@ -898,7 +899,7 @@ e_create_move propose_router_swap(t_pl_blocks_to_be_moved& blocks_affected, return e_create_move::ABORT; } - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); + e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry, place_macros); //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap if (!floorplan_legal(blocks_affected)) { @@ -1000,26 +1001,25 @@ void NocCostHandler::print_noc_costs(std::string_view header, const t_placer_costs& costs, const t_noc_opts& noc_opts) const { VTR_LOG("%s. " - "cost: %g, " - "aggregate_bandwidth_cost: %g, " - "latency_cost: %g, " - "n_met_latency_constraints: %d, " - "latency_overrun_cost: %g, " - "congestion_cost: %g, " - "accum_congested_ratio: %g, " - "n_congested_links: %d \n", - header.data(), - calculate_noc_cost(costs.noc_cost_terms, costs.noc_cost_norm_factors, noc_opts), - costs.noc_cost_terms.aggregate_bandwidth, - costs.noc_cost_terms.latency, - get_number_of_traffic_flows_with_latency_cons_met(), - costs.noc_cost_terms.latency_overrun, - costs.noc_cost_terms.congestion, - get_total_congestion_bandwidth_ratio(), - get_number_of_congested_noc_links()); + "cost: %g, " + "aggregate_bandwidth_cost: %g, " + "latency_cost: %g, " + "n_met_latency_constraints: %d, " + "latency_overrun_cost: %g, " + "congestion_cost: %g, " + "accum_congested_ratio: %g, " + "n_congested_links: %d \n", + header.data(), + calculate_noc_cost(costs.noc_cost_terms, costs.noc_cost_norm_factors, noc_opts), + costs.noc_cost_terms.aggregate_bandwidth, + costs.noc_cost_terms.latency, + get_number_of_traffic_flows_with_latency_cons_met(), + costs.noc_cost_terms.latency_overrun, + costs.noc_cost_terms.congestion, + get_total_congestion_bandwidth_ratio(), + get_number_of_congested_noc_links()); } - static std::vector find_affected_links_by_flow_reroute(std::vector& prev_links, std::vector& curr_links) { // Sort both link containers diff --git a/vpr/src/place/noc_place_utils.h b/vpr/src/place/noc_place_utils.h index 0224ef78af8..a71963b8f10 100644 --- a/vpr/src/place/noc_place_utils.h +++ b/vpr/src/place/noc_place_utils.h @@ -5,6 +5,8 @@ #include "move_utils.h" #include "place_util.h" +class PlaceMacros; + /** * @class NocCostHandler is responsible for computing NoC-related costs terms. * @@ -192,7 +194,7 @@ class NocCostHandler { * * @param costs Contains the normalization factors which need to be updated */ - static void update_noc_normalization_factors(t_placer_costs& costs) ; + static void update_noc_normalization_factors(t_placer_costs& costs); /** * @brief Calculates the aggregate bandwidth of each traffic flow in the NoC @@ -443,7 +445,6 @@ class NocCostHandler { NocRouting& noc_flows_router, std::unordered_set& updated_traffic_flows); - /** * @brief Removes the route of a traffic flow and updates the links to indicate * that the traffic flow does not use them. And then finds @@ -486,7 +487,6 @@ class NocCostHandler { */ static constexpr double MAX_INV_NOC_LATENCY_COST = 1.e12; - /** * @brief Represents the minimum link bandwidth over-utilization for that link to be considered congested. * @details If a link is overloaded by less than 0.1% of the link bandwidth capacity, @@ -626,8 +626,6 @@ double calculate_noc_cost(const NocCostTerms& cost_terms, const NocCostTerms& norm_factors, const t_noc_opts& noc_opts); - - /* Below are functions related to the feature that forces to the placer to swap router blocks for a certain percentage of the total number of swaps */ /** @@ -662,6 +660,7 @@ bool check_for_router_swap(int user_supplied_noc_router_swap_percentage, e_create_move propose_router_swap(t_pl_blocks_to_be_moved& blocks_affected, float rlim, const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, vtr::RngContainer& rng); /** @@ -683,8 +682,6 @@ e_create_move propose_router_swap(t_pl_blocks_to_be_moved& blocks_affected, void write_noc_placement_file(const std::string& file_name, const vtr::vector_map& block_locs); - - /** * @brief Check if the channel dependency graph created from the given traffic flow routes * has any cycles. @@ -708,5 +705,4 @@ bool noc_routing_has_cycle(const vtr::vector - +#include + +#include "flat_placement_types.h" +#include "initial_placement.h" +#include "load_flat_place.h" +#include "noc_place_utils.h" +#include "pack.h" +#include "vpr_context.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_time.h" @@ -10,17 +17,9 @@ #include "globals.h" #include "place.h" #include "annealer.h" -#include "read_xml_arch_file.h" #include "echo_files.h" -#include "histogram.h" -#include "place_delay_model.h" -#include "move_utils.h" -#include "buttons.h" - -#include "VprTimingGraphResolver.h" -#include "tatum/TimingReporter.hpp" +#include "PlacementDelayModelCreator.h" -#include "RL_agent_util.h" #include "placer.h" /********************* Static subroutines local to place.c *******************/ @@ -28,15 +27,6 @@ void print_clb_placement(const char* fname); #endif -/** - * @brief determine the type of the bounding box used by the placer to predict the wirelength - * - * @param place_bb_mode The bounding box mode passed by the CLI - * @param rr_graph The routing resource graph - */ -static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, - const RRGraphView& rr_graph); - /*****************************************************************************/ void try_place(const Netlist<>& net_list, const t_placer_opts& placer_opts, @@ -47,6 +37,7 @@ void try_place(const Netlist<>& net_list, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, const std::vector& directs, + const FlatPlacementInfo& flat_placement_info, bool is_flat) { /* Currently, the functions that require is_flat as their parameter and are called during placement should @@ -58,6 +49,33 @@ void try_place(const Netlist<>& net_list, const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& atom_ctx = g_vpr_ctx.atom(); + // Initialize the variables in the placement context. + g_vpr_ctx.mutable_placement().init_placement_context(placer_opts, directs); + + // Update the floorplanning constraints with the macro information from the + // placement context. + g_vpr_ctx.mutable_floorplanning().update_floorplanning_context_pre_place(*g_vpr_ctx.placement().place_macros); + + const bool cube_bb = g_vpr_ctx.placement().cube_bb; + + VTR_LOG("\n"); + VTR_LOG("Bounding box mode is %s\n", (cube_bb ? "Cube" : "Per-layer")); + VTR_LOG("\n"); + + /* To make sure the importance of NoC-related cost terms compared to + * BB and timing cost is determine only through NoC placement weighting factor, + * we normalize NoC-related cost weighting factors so that they add up to 1. + * With this normalization, NoC-related cost weighting factors only determine + * the relative importance of NoC cost terms with respect to each other, while + * the importance of total NoC cost to conventional placement cost is determined + * by NoC placement weighting factor. + * FIXME: This should not be modifying the NoC Opts here, this normalization + * should occur when these Opts are loaded in. + */ + if (noc_opts.noc) { + normalize_noc_cost_weighting_factor(const_cast(noc_opts)); + } + /* Placement delay model is independent of the placement and can be shared across * multiple placers if we are performing parallel annealing. * So, it is created and initialized once. */ @@ -65,35 +83,25 @@ void try_place(const Netlist<>& net_list, if (placer_opts.place_algorithm.is_timing_driven()) { /*do this before the initial placement to avoid messing up the initial placement */ - place_delay_model = alloc_lookups_and_delay_model(net_list, - chan_width_dist, - placer_opts, - router_opts, - det_routing_arch, - segment_inf, - directs, - is_flat); + place_delay_model = PlacementDelayModelCreator::create_delay_model(placer_opts, + router_opts, + net_list, + det_routing_arch, + segment_inf, + chan_width_dist, + directs, + is_flat); if (isEchoFileEnabled(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)) { place_delay_model->dump_echo(getEchoFileName(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)); } } - g_vpr_ctx.mutable_placement().cube_bb = is_cube_bb(placer_opts.place_bounding_box_mode, device_ctx.rr_graph); - const bool cube_bb = g_vpr_ctx.placement().cube_bb; - - VTR_LOG("\n"); - VTR_LOG("Bounding box mode is %s\n", (cube_bb ? "Cube" : "Per-layer")); - VTR_LOG("\n"); - - auto& place_ctx = g_vpr_ctx.mutable_placement(); - /* Make the global instance of BlkLocRegistry inaccessible through the getter methods of the * placement context. This is done to make sure that the placement stage only accesses its * own local instances of BlkLocRegistry. */ - place_ctx.lock_loc_vars(); - place_ctx.compressed_block_grids = create_compressed_block_grids(); + g_vpr_ctx.mutable_placement().lock_loc_vars(); /* Start measuring placement time. The measured execution time will be printed * when this object goes out of scope at the end of this function. @@ -103,45 +111,24 @@ void try_place(const Netlist<>& net_list, // Enables fast look-up pb graph pins from block pin indices IntraLbPbPinLookup pb_gpin_lookup(device_ctx.logical_block_types); // Enables fast look-up of atom pins connect to CLB pins - ClusteredPinAtomPinsLookup netlist_pin_lookup(cluster_ctx.clb_nlist, atom_ctx.nlist, pb_gpin_lookup); + ClusteredPinAtomPinsLookup netlist_pin_lookup(cluster_ctx.clb_nlist, atom_ctx.netlist(), pb_gpin_lookup); - Placer placer(net_list, placer_opts, analysis_opts, noc_opts, pb_gpin_lookup, netlist_pin_lookup, - directs, place_delay_model, cube_bb, is_flat, /*quiet=*/false); + Placer placer(net_list, {}, placer_opts, analysis_opts, noc_opts, pb_gpin_lookup, netlist_pin_lookup, + flat_placement_info, place_delay_model, cube_bb, is_flat, /*quiet=*/false); placer.place(); - vtr::release_memory(place_ctx.compressed_block_grids); - /* The placer object has its own copy of block locations and doesn't update * the global context directly. We need to copy its internal data structures * to the global placement context before it goes out of scope. */ - placer.copy_locs_to_global_state(place_ctx); -} - -static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, - const RRGraphView& rr_graph) { - bool cube_bb; - const int number_layers = g_vpr_ctx.device().grid.get_num_layers(); - - if (place_bb_mode == e_place_bounding_box_mode::AUTO_BB) { - // If the auto_bb is used, we analyze the RR graph to see whether is there any inter-layer connection that is not - // originated from OPIN. If there is any, cube BB is chosen, otherwise, per-layer bb is chosen. - if (number_layers > 1 && inter_layer_connections_limited_to_opin(rr_graph)) { - cube_bb = false; - } else { - cube_bb = true; - } - } else if (place_bb_mode == e_place_bounding_box_mode::CUBE_BB) { - // The user has specifically asked for CUBE_BB - cube_bb = true; - } else { - // The user has specifically asked for PER_LAYER_BB - VTR_ASSERT_SAFE(place_bb_mode == e_place_bounding_box_mode::PER_LAYER_BB); - cube_bb = false; - } + placer.copy_locs_to_global_state(g_vpr_ctx.mutable_placement()); - return cube_bb; + // Clean the variables in the placement context. This will deallocate memory + // used by variables which were allocated in the placement context and are + // never used outside of placement. + g_vpr_ctx.mutable_placement().clean_placement_context_post_place(); + g_vpr_ctx.mutable_floorplanning().clean_floorplanning_context_post_place(); } #ifdef VERBOSE @@ -173,4 +160,3 @@ static void update_screen_debug() { update_screen(ScreenUpdatePriority::MAJOR, "DEBUG", PLACEMENT, nullptr); } #endif - diff --git a/vpr/src/place/place.h b/vpr/src/place/place.h index e4a0172ba4e..c7c3d9f8758 100644 --- a/vpr/src/place/place.h +++ b/vpr/src/place/place.h @@ -3,6 +3,8 @@ #include "vpr_types.h" +class FlatPlacementInfo; + void try_place(const Netlist<>& net_list, const t_placer_opts& placer_opts, const t_router_opts& router_opts, @@ -12,4 +14,5 @@ void try_place(const Netlist<>& net_list, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, const std::vector& directs, + const FlatPlacementInfo& flat_placement_info, bool is_flat); diff --git a/vpr/src/place/place_checkpoint.cpp b/vpr/src/place/place_checkpoint.cpp index 60b009d85ae..a6e2858e577 100644 --- a/vpr/src/place/place_checkpoint.cpp +++ b/vpr/src/place/place_checkpoint.cpp @@ -1,7 +1,11 @@ + #include "place_checkpoint.h" + #include "noc_place_utils.h" #include "placer_state.h" #include "grid_block.h" +#include "PlacerCriticalities.h" +#include "PlacerSetupSlacks.h" float t_placement_checkpoint::get_cp_cpd() const { return cpd_; } diff --git a/vpr/src/place/place_constraints.cpp b/vpr/src/place/place_constraints.cpp index 2fee09e9d7b..ef867ce5b1a 100644 --- a/vpr/src/place/place_constraints.cpp +++ b/vpr/src/place/place_constraints.cpp @@ -10,6 +10,7 @@ #include "globals.h" #include "place_constraints.h" +#include "physical_types_util.h" #include "place_util.h" #include "vpr_context.h" @@ -117,7 +118,6 @@ PartitionRegion update_macro_member_pr(const PartitionRegion& head_pr, macro_pr.add_to_part_region(modified_reg); } - //intersect to ensure the macro pr does not go outside of grid dimensions macro_pr = intersection(macro_pr, grid_pr); @@ -282,8 +282,6 @@ void alloc_and_load_compressed_cluster_constraints() { // Get the compressed grid for NoC const auto& compressed_grid = place_ctx.compressed_block_grids[block_type->index]; - - for (const Region& region : pr.get_regions()) { const auto [layer_low, layer_high] = region.get_layer_range(); const vtr::Rect& rect = region.get_rect(); @@ -310,14 +308,12 @@ void alloc_and_load_compressed_cluster_constraints() { } } - for (int l = 0 ; l < n_layers; l++) { + for (int l = 0; l < n_layers; l++) { if (floorplanning_ctx.compressed_cluster_constraints[l][blk_id].empty()) { floorplanning_ctx.compressed_cluster_constraints[l][blk_id].add_to_part_region(Region{}); } } - } - } /* diff --git a/vpr/src/place/place_constraints.h b/vpr/src/place/place_constraints.h index 9e045178e77..77952144795 100644 --- a/vpr/src/place/place_constraints.h +++ b/vpr/src/place/place_constraints.h @@ -34,7 +34,6 @@ bool is_cluster_constrained(ClusterBlockId blk_id); */ bool cluster_floorplanning_legal(ClusterBlockId blk_id, const t_pl_loc& loc); - /** * @brief Check whether any member of the macro has floorplan constraints. * @@ -107,7 +106,6 @@ inline bool floorplan_legal(const t_pl_blocks_to_be_moved& blocks_affected) { return true; } - /** * @brief Load cluster_constraints if the pack stage of VPR is skipped. * @@ -185,7 +183,6 @@ int get_part_reg_size(const PartitionRegion& pr, t_logical_block_type_ptr block_type, const GridTileLookup& grid_tiles); - /** * @brief Return the floorplan score that will be used for sorting blocks during initial placement. * @@ -205,5 +202,4 @@ double get_floorplan_score(ClusterBlockId blk_id, t_logical_block_type_ptr block_type, const GridTileLookup& grid_tiles); - #endif /* VPR_SRC_PLACE_PLACE_CONSTRAINTS_H_ */ diff --git a/vpr/src/place/place_delay_model.cpp b/vpr/src/place/place_delay_model.cpp deleted file mode 100644 index 4cbf5be1b6a..00000000000 --- a/vpr/src/place/place_delay_model.cpp +++ /dev/null @@ -1,469 +0,0 @@ -/** - * @file place_delay_model.cpp - * @brief This file implements all the class methods and individual - * routines related to the placer delay model. - */ - -#include -#include "place_delay_model.h" -#include "globals.h" -#include "router_lookahead_map.h" -#include "rr_graph2.h" - -#include "timing_place_lookup.h" -#include "placer_state.h" - -#include "vtr_log.h" -#include "vtr_math.h" -#include "vpr_error.h" - -#ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "place_delay_model.capnp.h" -# include "ndmatrix_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" -#endif /* VTR_ENABLE_CAPNPROTO */ - -///@brief DeltaDelayModel methods. -float DeltaDelayModel::delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const { - int delta_x = std::abs(from_loc.x - to_loc.x); - int delta_y = std::abs(from_loc.y - to_loc.y); - - return delays_[from_loc.layer_num][to_loc.layer_num][delta_x][delta_y]; -} - -void DeltaDelayModel::dump_echo(std::string filepath) const { - FILE* f = vtr::fopen(filepath.c_str(), "w"); - fprintf(f, " "); - for (size_t from_layer_num = 0; from_layer_num < delays_.dim_size(0); ++from_layer_num) { - for (size_t to_layer_num = 0; to_layer_num < delays_.dim_size(1); ++to_layer_num) { - fprintf(f, " %9zu", from_layer_num); - fprintf(f, "\n"); - for (size_t dx = 0; dx < delays_.dim_size(2); ++dx) { - fprintf(f, " %9zu", dx); - } - fprintf(f, "\n"); - for (size_t dy = 0; dy < delays_.dim_size(3); ++dy) { - fprintf(f, "%9zu", dy); - for (size_t dx = 0; dx < delays_.dim_size(2); ++dx) { - fprintf(f, " %9.2e", delays_[from_layer_num][to_layer_num][dx][dy]); - } - fprintf(f, "\n"); - } - } - } - vtr::fclose(f); -} - -const DeltaDelayModel* OverrideDelayModel::base_delay_model() const { - return base_delay_model_.get(); -} - -///@brief OverrideDelayModel methods. -float OverrideDelayModel::delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const { - //First check to if there is an override delay value - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - - t_physical_tile_type_ptr from_type_ptr = grid.get_physical_type(from_loc); - t_physical_tile_type_ptr to_type_ptr = grid.get_physical_type(to_loc); - - t_override override_key; - override_key.from_type = from_type_ptr->index; - override_key.from_class = from_type_ptr->pin_class[from_pin]; - override_key.to_type = to_type_ptr->index; - override_key.to_class = to_type_ptr->pin_class[to_pin]; - - //Delay overrides may be different for +/- delta so do not use - //an absolute delta for the look-up - override_key.delta_x = to_loc.x - from_loc.x; - override_key.delta_y = to_loc.y - from_loc.y; - - float delay_val = std::numeric_limits::quiet_NaN(); - auto override_iter = delay_overrides_.find(override_key); - if (override_iter != delay_overrides_.end()) { - //Found an override - delay_val = override_iter->second; - } else { - //Fall back to the base delay model if no override was found - delay_val = base_delay_model_->delay(from_loc, from_pin, to_loc, to_pin); - } - - return delay_val; -} - -void OverrideDelayModel::set_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y, float delay_val) { - t_override override_key; - override_key.from_type = from_type; - override_key.from_class = from_class; - override_key.to_type = to_type; - override_key.to_class = to_class; - override_key.delta_x = delta_x; - override_key.delta_y = delta_y; - - auto res = delay_overrides_.insert(std::make_pair(override_key, delay_val)); - if (!res.second) { //Key already exists - res.first->second = delay_val; //Overwrite existing delay - } -} - -void OverrideDelayModel::dump_echo(std::string filepath) const { - base_delay_model_->dump_echo(filepath); - - FILE* f = vtr::fopen(filepath.c_str(), "a"); - - fprintf(f, "\n"); - fprintf(f, "# Delay Overrides\n"); - auto& device_ctx = g_vpr_ctx.device(); - for (auto kv : delay_overrides_) { - auto override_key = kv.first; - float delay_val = kv.second; - fprintf(f, "from_type: %s to_type: %s from_pin_class: %d to_pin_class: %d delta_x: %d delta_y: %d -> delay: %g\n", - device_ctx.physical_tile_types[override_key.from_type].name.c_str(), - device_ctx.physical_tile_types[override_key.to_type].name.c_str(), - override_key.from_class, - override_key.to_class, - override_key.delta_x, - override_key.delta_y, - delay_val); - } - - vtr::fclose(f); -} - -float OverrideDelayModel::get_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y) const { - t_override key; - key.from_type = from_type; - key.from_class = from_class; - key.to_type = to_type; - key.to_class = to_class; - key.delta_x = delta_x; - key.delta_y = delta_y; - - auto iter = delay_overrides_.find(key); - if (iter == delay_overrides_.end()) { - VPR_THROW(VPR_ERROR_PLACE, "Key not found."); - } - return iter->second; -} - -void OverrideDelayModel::set_base_delay_model(std::unique_ptr base_delay_model_obj) { - base_delay_model_ = std::move(base_delay_model_obj); -} - -float SimpleDelayModel::delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const { - int delta_x = std::abs(from_loc.x - to_loc.x); - int delta_y = std::abs(from_loc.y - to_loc.y); - - int from_tile_idx = g_vpr_ctx.device().grid.get_physical_type(from_loc)->index; - return delays_[from_tile_idx][from_loc.layer_num][to_loc.layer_num][delta_x][delta_y]; -} - -/** - * When writing capnp targetted serialization, always allow compilation when - * VTR_ENABLE_CAPNPROTO=OFF. Generally this means throwing an exception instead. - */ -#ifndef VTR_ENABLE_CAPNPROTO - -# define DISABLE_ERROR \ - "is disable because VTR_ENABLE_CAPNPROTO=OFF." \ - "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable." - -void SimpleDelayModel::read(const std::string& /*file*/) { - VPR_THROW(VPR_ERROR_PLACE, "SimpleDelayModel::read " DISABLE_ERROR); -} - -void SimpleDelayModel::write(const std::string& /*file*/) const { - VPR_THROW(VPR_ERROR_PLACE, "SimpleDelayModel::write " DISABLE_ERROR); -} - -void DeltaDelayModel::read(const std::string& /*file*/) { - VPR_THROW(VPR_ERROR_PLACE, "DeltaDelayModel::read " DISABLE_ERROR); -} - -void DeltaDelayModel::write(const std::string& /*file*/) const { - VPR_THROW(VPR_ERROR_PLACE, "DeltaDelayModel::write " DISABLE_ERROR); -} - -void OverrideDelayModel::read(const std::string& /*file*/) { - VPR_THROW(VPR_ERROR_PLACE, "OverrideDelayModel::read " DISABLE_ERROR); -} - -void OverrideDelayModel::write(const std::string& /*file*/) const { - VPR_THROW(VPR_ERROR_PLACE, "OverrideDelayModel::write " DISABLE_ERROR); -} - -#else /* VTR_ENABLE_CAPNPROTO */ - -static void ToFloat(float* out, const VprFloatEntry::Reader& in) { - // Getting a scalar field is always "get()". - *out = in.getValue(); -} - -static void FromFloat(VprFloatEntry::Builder* out, const float& in) { - // Setting a scalar field is always "set(value)". - out->setValue(in); -} - -void SimpleDelayModel::read(const std::string& file) { - // MmapFile object creates an mmap of the specified path, and will munmap - // when the object leaves scope. - MmapFile f(file); - - /* Increase reader limit to 1G words to allow for large files. */ - ::capnp::ReaderOptions opts = default_large_capnp_opts(); - - // FlatArrayMessageReader is used to read the message from the data array - // provided by MmapFile. - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); - - // When reading capnproto files the Reader object to use is named - // ::Reader. - // - // Initially this object is an empty VprDeltaDelayModel. - VprDeltaDelayModel::Reader model; - - // The reader.getRoot performs a cast from the generic capnproto to fit - // with the specified schema. - // - // Note that capnproto does not validate that the incoming data matches the - // schema. If this property is required, some form of check would be - // required. - model = reader.getRoot(); - - // ToNdMatrix is a generic function for converting a Matrix capnproto - // to a vtr::NdMatrix. - // - // The user must supply the matrix dimension (5 in this case), the source - // capnproto type (VprFloatEntry), - // target C++ type (flat), and a function to convert from the source capnproto - // type to the target C++ type (ToFloat). - // - // The second argument should be of type Matrix::Reader where X is the - // capnproto element type. - ToNdMatrix<5, VprFloatEntry, float>(&delays_, model.getDelays(), ToFloat); -} - -void SimpleDelayModel::write(const std::string& file) const { - // MallocMessageBuilder object generates capnproto message builder, - // using malloc for buffer allocation. - ::capnp::MallocMessageBuilder builder; - - // initRoot returns a X::Builder object that can be used to set the - // fields in the message. - auto model = builder.initRoot(); - - // FromNdMatrix is a generic function for converting a vtr::NdMatrix to a - // Matrix message. It is the mirror function of ToNdMatrix described in - // read above. - auto delay_values = model.getDelays(); - FromNdMatrix<5, VprFloatEntry, float>(&delay_values, delays_, FromFloat); - - // writeMessageToFile writes message to the specified file. - writeMessageToFile(file, &builder); -} - -void DeltaDelayModel::read(const std::string& file) { - // MmapFile object creates an mmap of the specified path, and will munmap - // when the object leaves scope. - MmapFile f(file); - - /* Increase reader limit to 1G words to allow for large files. */ - ::capnp::ReaderOptions opts = default_large_capnp_opts(); - - // FlatArrayMessageReader is used to read the message from the data array - // provided by MmapFile. - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); - - // When reading capnproto files the Reader object to use is named - // ::Reader. - // - // Initially this object is an empty VprDeltaDelayModel. - VprDeltaDelayModel::Reader model; - - // The reader.getRoot performs a cast from the generic capnproto to fit - // with the specified schema. - // - // Note that capnproto does not validate that the incoming data matches the - // schema. If this property is required, some form of check would be - // required. - model = reader.getRoot(); - - // ToNdMatrix is a generic function for converting a Matrix capnproto - // to a vtr::NdMatrix. - // - // The use must supply the matrix dimension (2 in this case), the source - // capnproto type (VprFloatEntry), - // target C++ type (flat), and a function to convert from the source capnproto - // type to the target C++ type (ToFloat). - // - // The second argument should be of type Matrix::Reader where X is the - // capnproto element type. - ToNdMatrix<4, VprFloatEntry, float>(&delays_, model.getDelays(), ToFloat); -} - -void DeltaDelayModel::write(const std::string& file) const { - // MallocMessageBuilder object is the generate capnproto message builder, - // using malloc for buffer allocation. - ::capnp::MallocMessageBuilder builder; - - // initRoot returns a X::Builder object that can be used to set the - // fields in the message. - auto model = builder.initRoot(); - - // FromNdMatrix is a generic function for converting a vtr::NdMatrix to a - // Matrix message. It is the mirror function of ToNdMatrix described in - // read above. - auto delay_values = model.getDelays(); - FromNdMatrix<4, VprFloatEntry, float>(&delay_values, delays_, FromFloat); - - // writeMessageToFile writes message to the specified file. - writeMessageToFile(file, &builder); -} - -void OverrideDelayModel::read(const std::string& file) { - MmapFile f(file); - - /* Increase reader limit to 1G words to allow for large files. */ - ::capnp::ReaderOptions opts = default_large_capnp_opts(); - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); - - vtr::NdMatrix delays; - auto model = reader.getRoot(); - ToNdMatrix<4, VprFloatEntry, float>(&delays, model.getDelays(), ToFloat); - - base_delay_model_ = std::make_unique(cross_layer_delay_, delays, is_flat_); - - // Reading non-scalar capnproto fields is roughly equivilant to using - // a std::vector of the field type. Actual type is capnp::List::Reader. - auto overrides = model.getDelayOverrides(); - std::vector > overrides_arr(overrides.size()); - for (size_t i = 0; i < overrides.size(); ++i) { - const auto& elem = overrides[i]; - overrides_arr[i].first.from_type = elem.getFromType(); - overrides_arr[i].first.to_type = elem.getToType(); - overrides_arr[i].first.from_class = elem.getFromClass(); - overrides_arr[i].first.to_class = elem.getToClass(); - overrides_arr[i].first.delta_x = elem.getDeltaX(); - overrides_arr[i].first.delta_y = elem.getDeltaY(); - - overrides_arr[i].second = elem.getDelay(); - } - - delay_overrides_ = vtr::make_flat_map2(std::move(overrides_arr)); -} - -void OverrideDelayModel::write(const std::string& file) const { - ::capnp::MallocMessageBuilder builder; - auto model = builder.initRoot(); - - auto delays = model.getDelays(); - FromNdMatrix<4, VprFloatEntry, float>(&delays, base_delay_model_->delays(), FromFloat); - - // Non-scalar capnproto fields should be first initialized with - // init(count), and then accessed from the returned - // std::vector-like Builder object (specifically capnp::List::Builder). - auto overrides = model.initDelayOverrides(delay_overrides_.size()); - auto dst_iter = overrides.begin(); - for (const auto& src : delay_overrides_) { - auto elem = *dst_iter++; - elem.setFromType(src.first.from_type); - elem.setToType(src.first.to_type); - elem.setFromClass(src.first.from_class); - elem.setToClass(src.first.to_class); - elem.setDeltaX(src.first.delta_x); - elem.setDeltaY(src.first.delta_y); - - elem.setDelay(src.second); - } - - writeMessageToFile(file, &builder); -} - -#endif - -///@brief Initialize the placer delay model. -std::unique_ptr alloc_lookups_and_delay_model(const Netlist<>& net_list, - t_chan_width_dist chan_width_dist, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, - std::vector& segment_inf, - const std::vector& directs, - bool is_flat) { - return compute_place_delay_model(placer_opts, - router_opts, - net_list, - det_routing_arch, - segment_inf, - chan_width_dist, - directs, - is_flat); -} - -/** - * @brief Returns the delay of one point to point connection. - * - * Only estimate delay for signals routed through the inter-block routing network. - * TODO: Do how should we compute the delay for globals. "Global signals are assumed to have zero delay." - */ -float comp_td_single_connection_delay(const PlaceDelayModel* delay_model, - const vtr::vector_map& block_locs, - ClusterNetId net_id, - int ipin) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - - float delay_source_to_sink = 0.; - - if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) { - ClusterPinId source_pin = cluster_ctx.clb_nlist.net_driver(net_id); - ClusterPinId sink_pin = cluster_ctx.clb_nlist.net_pin(net_id, ipin); - - ClusterBlockId source_block = cluster_ctx.clb_nlist.pin_block(source_pin); - ClusterBlockId sink_block = cluster_ctx.clb_nlist.pin_block(sink_pin); - - int source_block_ipin = cluster_ctx.clb_nlist.pin_logical_index(source_pin); - int sink_block_ipin = cluster_ctx.clb_nlist.pin_logical_index(sink_pin); - - t_pl_loc source_block_loc = block_locs[source_block].loc; - t_pl_loc sink_block_loc = block_locs[sink_block].loc; - - /** - * This heuristic only considers delta_x and delta_y, a much better - * heuristic would be to to create a more comprehensive lookup table. - * - * In particular this approach does not accurately capture the effect - * of fast carry-chain connections. - */ - delay_source_to_sink = delay_model->delay({source_block_loc.x, source_block_loc.y, source_block_loc.layer}, source_block_ipin, - {sink_block_loc.x, sink_block_loc.y, sink_block_loc.layer}, sink_block_ipin); - if (delay_source_to_sink < 0) { - VPR_ERROR(VPR_ERROR_PLACE, - "in comp_td_single_connection_delay: Bad delay_source_to_sink value %g from %s (at %d,%d,%d) to %s (at %d,%d,%d)\n" - "in comp_td_single_connection_delay: Delay is less than 0\n", - block_type_pin_index_to_name(physical_tile_type(source_block_loc), source_block_ipin, false).c_str(), - source_block_loc.x, source_block_loc.y, source_block_loc.layer, - block_type_pin_index_to_name(physical_tile_type(sink_block_loc), sink_block_ipin, false).c_str(), - sink_block_loc.x, sink_block_loc.y, sink_block_loc.layer, - delay_source_to_sink); - } - } - - return (delay_source_to_sink); -} - -///@brief Recompute all point to point delays, updating `connection_delay` matrix. -void comp_td_connection_delays(const PlaceDelayModel* delay_model, - PlacerState& placer_state) { - const auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& p_timing_ctx = placer_state.mutable_timing(); - auto& block_locs = placer_state.block_locs(); - auto& connection_delay = p_timing_ctx.connection_delay; - - for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) { - for (size_t ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net_id).size(); ++ipin) { - connection_delay[net_id][ipin] = comp_td_single_connection_delay(delay_model, block_locs, net_id, ipin); - } - } -} diff --git a/vpr/src/place/place_delay_model.h b/vpr/src/place/place_delay_model.h deleted file mode 100644 index d9df7a18e90..00000000000 --- a/vpr/src/place/place_delay_model.h +++ /dev/null @@ -1,275 +0,0 @@ -/** - * @file place_delay_model.h - * @brief This file contains all the class and function declarations related to - * the placer delay model. For implementations, see place_delay_model.cpp. - */ - -#pragma once -#include "vtr_ndmatrix.h" -#include "vtr_flat_map.h" -#include "vpr_types.h" -#include "router_delay_profiling.h" - -#ifndef __has_attribute -# define __has_attribute(x) 0 // Compatibility with non-clang compilers. -#endif - -#if defined(COMPILER_GCC) && defined(NDEBUG) -# define ALWAYS_INLINE inline __attribute__((__always_inline__)) -#elif defined(COMPILER_MSVC) && defined(NDEBUG) -# define ALWAYS_INLINE __forceinline -#elif __has_attribute(always_inline) -# define ALWAYS_INLINE __attribute__((always_inline)) // clang -#else -# define ALWAYS_INLINE inline -#endif - -///@brief Forward declarations. -class PlaceDelayModel; -class PlacerState; - -///@brief Initialize the placer delay model. -std::unique_ptr alloc_lookups_and_delay_model(const Netlist<>& net_list, - t_chan_width_dist chan_width_dist, - const t_placer_opts& place_opts, - const t_router_opts& router_opts, - t_det_routing_arch* det_routing_arch, - std::vector& segment_inf, - const std::vector& directs, - bool is_flat); - -///@brief Returns the delay of one point to point connection. -float comp_td_single_connection_delay(const PlaceDelayModel* delay_model, - const vtr::vector_map& block_locs, - ClusterNetId net_id, - int ipin); - -///@brief Recompute all point to point delays, updating `connection_delay` matrix. -void comp_td_connection_delays(const PlaceDelayModel* delay_model, - PlacerState& placer_state); - -///@brief Abstract interface to a placement delay model. -class PlaceDelayModel { - public: - virtual ~PlaceDelayModel() = default; - - ///@brief Computes place delay model. - virtual void compute( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) - = 0; - - /** - * @brief Returns the delay estimate between the specified block pins. - * - * Either compute or read methods must be invoked before invoking delay. - */ - virtual float delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const = 0; - - ///@brief Dumps the delay model to an echo file. - virtual void dump_echo(std::string filename) const = 0; - - /** - * @brief Write place delay model to specified file. - * - * May be unimplemented, in which case method should throw an exception. - */ - virtual void write(const std::string& file) const = 0; - - /** - * @brief Read place delay model from specified file. - * - * May be unimplemented, in which case method should throw an exception. - */ - virtual void read(const std::string& file) = 0; -}; - -///@brief A simple delay model based on the distance (delta) between block locations. -class DeltaDelayModel : public PlaceDelayModel { - public: - DeltaDelayModel(float min_cross_layer_delay, - bool is_flat) - : cross_layer_delay_(min_cross_layer_delay) - , is_flat_(is_flat) {} - DeltaDelayModel(float min_cross_layer_delay, - vtr::NdMatrix delta_delays, - bool is_flat) - : delays_(std::move(delta_delays)) - , cross_layer_delay_(min_cross_layer_delay) - , is_flat_(is_flat) {} - - void compute( - RouterDelayProfiler& router, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) override; - float delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const override; - void dump_echo(std::string filepath) const override; - - void read(const std::string& file) override; - void write(const std::string& file) const override; - const vtr::NdMatrix& delays() const { - return delays_; - } - - private: - vtr::NdMatrix delays_; // [0..num_layers-1][0..max_dx][0..max_dy] - float cross_layer_delay_; - /** - * @brief Indicates whether the router is a two-stage or run-flat - */ - bool is_flat_; -}; - -class OverrideDelayModel : public PlaceDelayModel { - public: - OverrideDelayModel(float min_cross_layer_delay, - bool is_flat) - : cross_layer_delay_(min_cross_layer_delay) - , is_flat_(is_flat) {} - void compute( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) override; - // returns delay from the specified (x,y) to the specified (x,y) with both endpoints on layer_num and the - // specified from and to pins - float delay(const t_physical_tile_loc& from_loc, int from_pin, const t_physical_tile_loc& to_loc, int to_pin) const override; - void dump_echo(std::string filepath) const override; - - void read(const std::string& file) override; - void write(const std::string& file) const override; - - public: //Mutators - void set_base_delay_model(std::unique_ptr base_delay_model); - const DeltaDelayModel* base_delay_model() const; - float get_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y) const; - void set_delay_override(int from_type, int from_class, int to_type, int to_class, int delta_x, int delta_y, float delay); - - private: - std::unique_ptr base_delay_model_; - /** - * @brief Minimum delay of cross-layer connections - */ - float cross_layer_delay_; - /** - * @brief Indicates whether the router is a two-stage or run-flat - */ - bool is_flat_; - - void compute_override_delay_model(RouterDelayProfiler& router, - const t_router_opts& router_opts); - - /** - * @brief Structure that allows delays to be queried from the delay model. - * - * Delay is calculated given the origin physical tile, the origin - * pin, the destination physical tile, and the destination pin. - * This structure encapsulates all these information. - * - * @param from_type, to_type - * Physical tile index (for easy array access) - * @param from_class, to_class - * The class that the pins belongs to. - * @param to_x, to_y - * The horizontal and vertical displacement - * between two physical tiles. - */ - struct t_override { - short from_type; - short to_type; - short from_class; - short to_class; - short delta_x; - short delta_y; - - /** - * @brief Comparison operator designed for performance. - * - * Operator< is important since t_override serves as the key into the - * map structure delay_overrides_. A default comparison operator would - * not be inlined by the compiler. - * - * A combination of ALWAYS_INLINE attribute and std::lexicographical_compare - * is required for operator< to be inlined by compiler. Proper inlining of - * the function reduces place time by around 5%. - * - * For more information: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1225 - */ - friend ALWAYS_INLINE bool operator<(const t_override& lhs, const t_override& rhs) { - const short* left = reinterpret_cast(&lhs); - const short* right = reinterpret_cast(&rhs); - constexpr size_t NUM_T_OVERRIDE_MEMBERS = sizeof(t_override) / sizeof(short); - return std::lexicographical_compare(left, left + NUM_T_OVERRIDE_MEMBERS, right, right + NUM_T_OVERRIDE_MEMBERS); - } - }; - - /** - * @brief Map data structure that returns delay values according to - * specific delay model queries. - * - * Delay model queries are provided by the t_override structure, which - * encapsulates the information regarding the origin and the destination. - */ - vtr::flat_map2 delay_overrides_; - - /** - * operator< treats memory layout of t_override as an array of short. - * This requires all members of t_override are shorts and there is no - * padding between members of t_override. - */ - static_assert(sizeof(t_override) == sizeof(t_override::from_type) + sizeof(t_override::to_type) + sizeof(t_override::from_class) + sizeof(t_override::to_class) + sizeof(t_override::delta_x) + sizeof(t_override::delta_y), "Expect t_override to have a memory layout equivalent to an array of short (no padding)"); - static_assert(sizeof(t_override::from_type) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::to_type) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::from_class) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::to_class) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::delta_x) == sizeof(short), "Expect all t_override data members to be shorts"); - static_assert(sizeof(t_override::delta_y) == sizeof(short), "Expect all t_override data members to be shorts"); -}; - -///@brief A simple delay model based on the information stored in router lookahead -/// This is in contrast to other placement delay models that get the cost of getting from one location to another by running the router -class SimpleDelayModel : public PlaceDelayModel { - public: - SimpleDelayModel() {} - - /** - * @brief Initializes the `delays_` data structure. This involves retrieving the corresponding delays for each entry from - * the router lookahead and storing the minimum among them. - * - * @param router The router used to retrieve information from the router lookahead. - * @param placer_opts Placment parameters. - * @param router_opts Routing parameters. - * @param longest_length The length of the longest routing track. - */ - void compute( - RouterDelayProfiler& router, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) override; - float delay(const t_physical_tile_loc& from_loc, int /*from_pin*/, const t_physical_tile_loc& to_loc, int /*to_pin*/) const override; - void dump_echo(std::string /*filepath*/) const override {} - - void read(const std::string& /*file*/) override; - void write(const std::string& /*file*/) const override; - /** - @brief Returns a reference to the array containing the placement delay matrix. - */ - const vtr::NdMatrix& delays() const { - return delays_; - } - - private: - /** - * @brief The matrix to store the minimum delay between different points on different layers. - * - *The matrix used to store delay information is a 5D matrix. This data structure stores the minimum delay for each tile type on each layer to other layers - *for each dx and dy. We decided to separate the delay for each physical type on each die to accommodate cases where the connectivity of a physical type differs - *on each layer. Additionally, instead of using d_layer, we distinguish between the destination layer to handle scenarios where connectivity between layers - *is not uniform. For example, if the number of inter-layer connections between layer 1 and 2 differs from the number of connections between layer 0 and 1. - *One might argue that this variability could also occur for dx and dy. However, we are operating under the assumption that the FPGA fabric architecture is regular. - */ - vtr::NdMatrix delays_; // [0..num_physical_type-1][0..num_layers-1][0..num_layers-1][0..max_dx][0..max_dy] -}; diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index 3568405290c..4a8ccb62666 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -7,13 +7,16 @@ #include #include +#include "atom_lookup.h" +#include "atom_netlist.h" +#include "clustered_netlist.h" +#include "physical_types_util.h" #include "vtr_assert.h" #include "vtr_util.h" #include "vpr_utils.h" #include "vpr_types.h" #include "vpr_error.h" #include "physical_types.h" -#include "globals.h" #include "echo_files.h" /** @@ -21,14 +24,17 @@ * @param clb_net The unique id of a cluster net. * @return True if the net is constant; otherwise false. */ -static bool is_constant_clb_net(ClusterNetId clb_net); +static bool is_constant_clb_net(ClusterNetId clb_net, + const AtomLookup& atom_lookup, + const AtomNetlist& atom_nlist); /** * @brief Performs a sanity check on macros by making sure that * each block appears in at most one macro. * @param macros All placement macros in the netlist. */ -static void validate_macros(const std::vector& macros); +static void validate_macros(const std::vector& macros, + const ClusteredNetlist& clb_nlist); /** * @brief Tries to combine two placement macros. @@ -62,6 +68,7 @@ static void mark_direct_of_ports(int idirect, int line, std::vector>& idirect_from_blk_pin, std::vector>& direct_type_from_blk_pin, + const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin); /** @@ -79,13 +86,18 @@ static void mark_direct_of_pins(int start_pin_index, int direct_type, int line, std::string_view src_string, + const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin); const std::vector& PlaceMacros::macros() const { return pl_macros_; } -void PlaceMacros::alloc_and_load_placement_macros(const std::vector& directs) { +PlaceMacros::PlaceMacros(const std::vector& directs, + const std::vector& physical_tile_types, + const ClusteredNetlist& clb_nlist, + const AtomNetlist& atom_nlist, + const AtomLookup& atom_lookup) { /* Allocates allocates and loads placement macros and returns * the total number of macros in 2 steps. * 1) Allocate temporary data structure for maximum possible @@ -96,16 +108,17 @@ void PlaceMacros::alloc_and_load_placement_macros(const std::vector pl_macro_idirect(cluster_ctx.clb_nlist.blocks().size()); - std::vector pl_macro_num_members(cluster_ctx.clb_nlist.blocks().size()); + std::vector pl_macro_idirect(num_clusters); + std::vector pl_macro_num_members(num_clusters); /* For pl_macro_member_blk_num, Allocate for the first dimension only at first. Allocate for the second dimension * when I know the size. Otherwise, the array is going to be of size cluster_ctx.clb_nlist.blocks().size()^2 */ - std::vector> pl_macro_member_blk_num(cluster_ctx.clb_nlist.blocks().size()); + std::vector> pl_macro_member_blk_num(num_clusters); - alloc_and_load_idirect_from_blk_pin_(directs); + alloc_and_load_idirect_from_blk_pin_(directs, physical_tile_types); /* Compute required size: * Go through all the pins with possible direct connections in @@ -114,7 +127,9 @@ void PlaceMacros::alloc_and_load_placement_macros(const std::vector& pl_macro_idirect, +int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, + const AtomNetlist& atom_nlist, + const AtomLookup& atom_lookup, + std::vector& pl_macro_idirect, std::vector& pl_macro_num_members, std::vector>& pl_macro_member_blk_num) { /* Compute required size: * @@ -161,8 +182,7 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, * as the number macros) and also the length of each macro * * Head - blocks with to_pin OPEN and from_pin connected * * Tail - blocks with to_pin connected and from_pin OPEN */ - const auto& cluster_ctx = g_vpr_ctx.clustering(); - std::vector pl_macro_member_blk_num_of_this_blk(cluster_ctx.clb_nlist.blocks().size()); + std::vector pl_macro_member_blk_num_of_this_blk(clb_nlist.blocks().size()); // Hash table holding the unique cluster ids and the macro id it belongs to std::unordered_map clusters_macro; @@ -170,15 +190,15 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, // counts the total number of macros int num_macro = 0; - for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { - t_logical_block_type_ptr logical_block = cluster_ctx.clb_nlist.block_type(blk_id); + for (ClusterBlockId blk_id : clb_nlist.blocks()) { + t_logical_block_type_ptr logical_block = clb_nlist.block_type(blk_id); t_physical_tile_type_ptr physical_tile = pick_physical_type(logical_block); - int num_blk_pins = cluster_ctx.clb_nlist.block_type(blk_id)->pb_type->num_pins; + int num_blk_pins = clb_nlist.block_type(blk_id)->pb_type->num_pins; for (int to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) { int to_physical_pin = get_physical_pin(physical_tile, logical_block, to_iblk_pin); - ClusterNetId to_net_id = cluster_ctx.clb_nlist.block_net(blk_id, to_iblk_pin); + ClusterNetId to_net_id = clb_nlist.block_net(blk_id, to_iblk_pin); int to_idirect = idirect_from_blk_pin_[physical_tile->index][to_physical_pin]; int to_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][to_physical_pin]; @@ -191,12 +211,12 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, // Note that the restriction that constant nets are not driven from another direct ensures that // blocks in the middle of a chain with internal constant signals are not detected as potential // head blocks. - if (to_src_or_sink == SINK && to_idirect != OPEN && - (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id) && !net_is_driven_by_direct_(to_net_id)))) { + if (to_src_or_sink == SINK && to_idirect != OPEN + && (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id, atom_lookup, atom_nlist) && !net_is_driven_by_direct_(to_net_id, clb_nlist)))) { for (int from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); - ClusterNetId from_net_id = cluster_ctx.clb_nlist.block_net(blk_id, from_iblk_pin); + ClusterNetId from_net_id = clb_nlist.block_net(blk_id, from_iblk_pin); int from_idirect = idirect_from_blk_pin_[physical_tile->index][from_physical_pin]; int from_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][from_physical_pin]; @@ -224,13 +244,13 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, ClusterNetId curr_net_id = next_net_id; // Assume that carry chains only has 1 sink - direct connection - VTR_ASSERT(cluster_ctx.clb_nlist.net_sinks(curr_net_id).size() == 1); - next_blk_id = cluster_ctx.clb_nlist.net_pin_block(curr_net_id, 1); + VTR_ASSERT(clb_nlist.net_sinks(curr_net_id).size() == 1); + next_blk_id = clb_nlist.net_pin_block(curr_net_id, 1); // Assume that the from_iblk_pin index is the same for the next block VTR_ASSERT(idirect_from_blk_pin_[physical_tile->index][from_physical_pin] == from_idirect && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == SOURCE); - next_net_id = cluster_ctx.clb_nlist.block_net(next_blk_id, from_iblk_pin); + next_net_id = clb_nlist.block_net(next_blk_id, from_iblk_pin); // Mark down this block as a member of the macro int imember = pl_macro_num_members[num_macro]; @@ -274,10 +294,10 @@ int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, num_macro++; } // Do nothing if the from_pins does not have same possible direct connection. - } // Finish going through all the pins for from_pins. - } // Do nothing if the to_pins does not have same possible direct connection. - } // Finish going through all the pins for to_pins. - } // Finish going through all blocks. + } // Finish going through all the pins for from_pins. + } // Do nothing if the to_pins does not have same possible direct connection. + } // Finish going through all the pins for to_pins. + } // Finish going through all blocks. // Now, all the data is readily stored in the temporary data structures. return num_macro; @@ -395,13 +415,12 @@ int PlaceMacros::get_imacro_from_iblk(ClusterBlockId iblk) const { return imacro; } -void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector& directs) { - const auto& device_ctx = g_vpr_ctx.device(); - +void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector& directs, + const std::vector& physical_tile_types) { // Allocate and initialize the values to OPEN (-1). - idirect_from_blk_pin_.resize(device_ctx.physical_tile_types.size()); - direct_type_from_blk_pin_.resize(device_ctx.physical_tile_types.size()); - for (const t_physical_tile_type& type : device_ctx.physical_tile_types) { + idirect_from_blk_pin_.resize(physical_tile_types.size()); + direct_type_from_blk_pin_.resize(physical_tile_types.size()); + for (const t_physical_tile_type& type : physical_tile_types) { if (is_empty_type(&type)) { continue; } @@ -433,6 +452,7 @@ void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector>& idirect_from_blk_pin, std::vector>& direct_type_from_blk_pin, + const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin) { /* Go through all the ports in all the blocks to find the port that has the same * * name as port_name and belongs to the block type that has the name pb_type_name. * @@ -462,11 +484,9 @@ static void mark_direct_of_ports(int idirect, * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * * Otherwise, mark down all the pins in that port. */ - auto& device_ctx = g_vpr_ctx.device(); - // Go through all the block types - for (int itype = 1; itype < (int)device_ctx.physical_tile_types.size(); itype++) { - auto& physical_tile = device_ctx.physical_tile_types[itype]; + for (int itype = 1; itype < (int)physical_tile_types.size(); itype++) { + auto& physical_tile = physical_tile_types[itype]; // Find blocks with the same pb_type_name if (pb_type_name == physical_tile.name) { int num_sub_tiles = physical_tile.sub_tiles.size(); @@ -493,18 +513,20 @@ static void mark_direct_of_ports(int idirect, mark_direct_of_pins(start_pin_index, end_pin_index, itype, isub_tile, iport, idirect_from_blk_pin, idirect, direct_type_from_blk_pin, direct_type, line, src_string, + physical_tile_types, port_pin_to_block_pin); } else { mark_direct_of_pins(0, num_port_pins - 1, itype, isub_tile, iport, idirect_from_blk_pin, idirect, direct_type_from_blk_pin, direct_type, line, src_string, + physical_tile_types, port_pin_to_block_pin); } } // Do nothing if port_name does not match - } // Finish going through all the ports - } // Finish going through all the subtiles - } // Do nothing if pb_type_name does not match - } // Finish going through all the blocks + } // Finish going through all the ports + } // Finish going through all the subtiles + } // Do nothing if pb_type_name does not match + } // Finish going through all the blocks } static void mark_direct_of_pins(int start_pin_index, @@ -518,16 +540,15 @@ static void mark_direct_of_pins(int start_pin_index, int direct_type, int line, std::string_view src_string, + const std::vector& physical_tile_types, const PortPinToBlockPinConverter& port_pin_to_block_pin) { - const auto& device_ctx = g_vpr_ctx.device(); - // Mark pins with indices from start_pin_index to end_pin_index, inclusive for (int iport_pin = start_pin_index; iport_pin <= end_pin_index; iport_pin++) { int iblk_pin = port_pin_to_block_pin.get_blk_pin_from_port_pin(itype, isub_tile, iport, iport_pin); // iterate through all segment connections and check if all Fc's are 0 bool all_fcs_0 = true; - for (const auto& fc_spec : device_ctx.physical_tile_types[itype].fc_specs) { + for (const auto& fc_spec : physical_tile_types[itype].fc_specs) { for (int ipin : fc_spec.pins) { if (iblk_pin == ipin && fc_spec.fc_value > 0) { all_fcs_0 = false; @@ -554,13 +575,12 @@ static void mark_direct_of_pins(int start_pin_index, } /* Allocates and loads imacro_from_iblk array. */ -void PlaceMacros::alloc_and_load_imacro_from_iblk_(const std::vector& macros) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - - imacro_from_iblk_.resize(cluster_ctx.clb_nlist.blocks().size()); +void PlaceMacros::alloc_and_load_imacro_from_iblk_(const std::vector& macros, + const ClusteredNetlist& clb_nlist) { + imacro_from_iblk_.resize(clb_nlist.blocks().size()); /* Allocate and initialize the values to OPEN (-1). */ - for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { + for (auto blk_id : clb_nlist.blocks()) { imacro_from_iblk_.insert(blk_id, OPEN); } @@ -573,11 +593,12 @@ void PlaceMacros::alloc_and_load_imacro_from_iblk_(const std::vector } } -void PlaceMacros::write_place_macros_(std::string filename, const std::vector& macros) { +void PlaceMacros::write_place_macros_(std::string filename, + const std::vector& macros, + const std::vector& physical_tile_types, + const ClusteredNetlist& clb_nlist) { FILE* f = vtr::fopen(filename.c_str(), "w"); - auto& cluster_ctx = g_vpr_ctx.clustering(); - fprintf(f, "#Identified Placement macros\n"); fprintf(f, "Num_Macros: %zu\n", macros.size()); for (size_t imacro = 0; imacro < macros.size(); ++imacro) { @@ -588,7 +609,7 @@ void PlaceMacros::write_place_macros_(std::string filename, const std::vectormembers[imember]; fprintf(f, "Block_Id: %zu (%s), x_offset: %d, y_offset: %d, z_offset: %d\n", size_t(macro_memb->blk_index), - cluster_ctx.clb_nlist.block_name(macro_memb->blk_index).c_str(), + clb_nlist.block_name(macro_memb->blk_index).c_str(), macro_memb->offset.x, macro_memb->offset.y, macro_memb->offset.sub_tile); @@ -601,8 +622,7 @@ void PlaceMacros::write_place_macros_(std::string filename, const std::vector& macros) { +static void validate_macros(const std::vector& macros, + const ClusteredNetlist& clb_nlist) { //Perform sanity checks on macros - const auto& cluster_ctx = g_vpr_ctx.clustering(); //Verify that blocks only appear in a single macro std::multimap block_to_macro; @@ -667,13 +685,13 @@ static void validate_macros(const std::vector& macros) { } } - for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { + for (ClusterBlockId blk_id : clb_nlist.blocks()) { auto range = block_to_macro.equal_range(blk_id); int blk_macro_cnt = std::distance(range.first, range.second); if (blk_macro_cnt > 1) { std::stringstream msg; - msg << "Block #" << size_t(blk_id) << " '" << cluster_ctx.clb_nlist.block_name(blk_id) << "'" + msg << "Block #" << size_t(blk_id) << " '" << clb_nlist.block_name(blk_id) << "'" << " appears in " << blk_macro_cnt << " placement macros (should appear in at most one). Related Macros:\n"; for (auto iter = range.first; iter != range.second; ++iter) { @@ -685,4 +703,3 @@ static void validate_macros(const std::vector& macros) { } } } - diff --git a/vpr/src/place/place_macro.h b/vpr/src/place/place_macro.h index ed6a2fc82c5..0b5988c7c61 100644 --- a/vpr/src/place/place_macro.h +++ b/vpr/src/place/place_macro.h @@ -125,6 +125,9 @@ #include "physical_types.h" #include "vpr_types.h" +class AtomLookup; +class AtomNetlist; + /** * @struct t_pl_macro_member * @brief The placement macro structure. @@ -143,8 +146,6 @@ struct t_pl_macro { class PlaceMacros { public: - PlaceMacros() = default; - /** * @brief Allocates and loads the placement macros. * @details The following steps are taken in this methodL @@ -162,7 +163,11 @@ class PlaceMacros { * carry_in's is connected to the netlist which has only 1 SINK. * @param directs */ - void alloc_and_load_placement_macros(const std::vector& directs); + PlaceMacros(const std::vector& directs, + const std::vector& physical_tile_types, + const ClusteredNetlist& clb_nlist, + const AtomNetlist& atom_nlist, + const AtomLookup& atom_lookup); /** * @brief Returns the placement macro index to which the given block belongs. @@ -194,7 +199,6 @@ class PlaceMacros { const t_pl_macro& operator[](int idx) const; private: - /** * @brief This array allow us to quickly find pins that could be in a direct connection. * @details Values stored is the index of the possible direct connection as specified in the arch file, @@ -222,15 +226,23 @@ class PlaceMacros { std::vector pl_macros_; private: - int find_all_the_macro_(std::vector& pl_macro_idirect, + int find_all_the_macro_(const ClusteredNetlist& clb_nlist, + const AtomNetlist& atom_nlist, + const AtomLookup& atom_lookup, + std::vector& pl_macro_idirect, std::vector& pl_macro_num_members, std::vector>& pl_macro_member_blk_num); - void alloc_and_load_imacro_from_iblk_(const std::vector& macros); + void alloc_and_load_imacro_from_iblk_(const std::vector& macros, + const ClusteredNetlist& clb_nlist); - void write_place_macros_(std::string filename, const std::vector& macros); + void write_place_macros_(std::string filename, + const std::vector& macros, + const std::vector& physical_tile_types, + const ClusteredNetlist& clb_nlist); - bool net_is_driven_by_direct_(ClusterNetId clb_net); + bool net_is_driven_by_direct_(ClusterNetId clb_net, + const ClusteredNetlist& clb_nlist); /** * @brief Allocates and loads idirect_from_blk_pin and direct_type_from_blk_pin arrays. @@ -246,8 +258,10 @@ class PlaceMacros { * the arch file, OPEN (-1) is stored for pins that could not be part of a direct * chain connection. * @param directs Contains information about all direct connections in the architecture. + * @param physical_tile_types A list of the physical tile types on the device. */ - void alloc_and_load_idirect_from_blk_pin_(const std::vector& directs); + void alloc_and_load_idirect_from_blk_pin_(const std::vector& directs, + const std::vector& physical_tile_types); }; #endif diff --git a/vpr/src/place/place_util.cpp b/vpr/src/place/place_util.cpp index e3f3d9da567..1ac0899fbdf 100644 --- a/vpr/src/place/place_util.cpp +++ b/vpr/src/place/place_util.cpp @@ -6,55 +6,10 @@ #include "place_util.h" #include "globals.h" -#include "draw_global.h" +#include "physical_types_util.h" #include "place_constraints.h" #include "noc_place_utils.h" -/** - * @brief Initialize `grid_blocks`, the inverse structure of `block_locs`. - * - * The container at each grid block location should have a length equal to the - * subtile capacity of that block. Unused subtile would be marked ClusterBlockId::INVALID(). - */ -static GridBlock init_grid_blocks(); - -void init_placement_context(BlkLocRegistry& blk_loc_registry, - const std::vector& directs) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - - auto& block_locs = blk_loc_registry.mutable_block_locs(); - auto& grid_blocks = blk_loc_registry.mutable_grid_blocks(); - auto& place_macros = blk_loc_registry.mutable_place_macros(); - - /* Initialize the lookup of CLB block positions */ - block_locs.clear(); - block_locs.resize(cluster_ctx.clb_nlist.blocks().size()); - - /* Initialize the reverse lookup of CLB block positions */ - grid_blocks = init_grid_blocks(); - - place_macros.alloc_and_load_placement_macros(directs); -} - -static GridBlock init_grid_blocks() { - auto& device_ctx = g_vpr_ctx.device(); - int num_layers = device_ctx.grid.get_num_layers(); - - /* Structure should have the same dimensions as the grid. */ - auto grid_blocks = GridBlock(device_ctx.grid.width(), device_ctx.grid.height(), num_layers); - - for (int layer_num = 0; layer_num < num_layers; ++layer_num) { - for (int x = 0; x < (int)device_ctx.grid.width(); ++x) { - for (int y = 0; y < (int)device_ctx.grid.height(); ++y) { - auto type = device_ctx.grid.get_physical_type({x, y, layer_num}); - grid_blocks.initialized_grid_block_at_location({x, y, layer_num}, type->capacity); - } - } - } - - return grid_blocks; -} - void t_placer_costs::update_norm_factors() { if (place_algorithm.is_timing_driven()) { bb_cost_norm = 1 / bb_cost; @@ -95,7 +50,7 @@ t_placer_costs& t_placer_costs::operator+=(const NocCostTerms& noc_delta_cost) { return *this; } -int get_initial_move_lim(const t_placer_opts& placer_opts, const t_annealing_sched& annealing_sched) { +int get_place_inner_loop_num_move(const t_placer_opts& placer_opts, const t_annealing_sched& annealing_sched) { const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -113,8 +68,6 @@ int get_initial_move_lim(const t_placer_opts& placer_opts, const t_annealing_sch /* Avoid having a non-positive move_lim */ move_lim = std::max(move_lim, 1); - VTR_LOG("Moves per temperature: %d\n", move_lim); - return move_lim; } @@ -165,7 +118,6 @@ double get_std_dev(int n, double sum_x_squared, double av_x) { return (std_dev > 0.) ? sqrt(std_dev) : 0.; } - void alloc_and_load_legal_placement_locations(std::vector>>& legal_pos) { auto& device_ctx = g_vpr_ctx.device(); diff --git a/vpr/src/place/place_util.h b/vpr/src/place/place_util.h index 2a816e01350..14cf44455c6 100644 --- a/vpr/src/place/place_util.h +++ b/vpr/src/place/place_util.h @@ -25,6 +25,8 @@ constexpr double PL_INCREMENTAL_COST_TOLERANCE = .01; class t_placer_costs; class BlkLocRegistry; +struct t_pl_macro; + /** * @brief Data structure that stores different cost terms for NoC placement. * This data structure can also be used to store normalization and weighting @@ -195,19 +197,8 @@ class t_placer_statistics { }; /** - * @brief Initialize the placer's block-grid dual direction mapping. - * - * Forward direction - block to grid: place_ctx.block_locs. - * Reverse direction - grid to block: place_ctx.grid_blocks. - * Allocates and load placement macros. - * - * Initialize both of them to empty states. - */ -void init_placement_context(BlkLocRegistry& blk_loc_registry, - const std::vector& directs); - -/** - * @brief Get the initial limit for inner loop block move attempt limit. + * @brief Get the number of moves attempted by the annealer's inner + * loop in each outer loop iteration. * * There are two ways to scale the move limit. * e_place_effort_scaling::CIRCUIT @@ -220,7 +211,7 @@ void init_placement_context(BlkLocRegistry& blk_loc_registry, * (device_size >> num_blocks), the search space is larger, so the second method * performs more moves to ensure better optimization. */ -int get_initial_move_lim(const t_placer_opts& placer_opts, const t_annealing_sched& annealing_sched); +int get_place_inner_loop_num_move(const t_placer_opts& placer_opts, const t_annealing_sched& annealing_sched); /** * @brief Returns the standard deviation of data set x. diff --git a/vpr/src/place/placement_log_printer.cpp b/vpr/src/place/placement_log_printer.cpp index a4eafb3b30f..1ce8c239dc7 100644 --- a/vpr/src/place/placement_log_printer.cpp +++ b/vpr/src/place/placement_log_printer.cpp @@ -1,6 +1,7 @@ #include "placement_log_printer.h" +#include "place_macro.h" #include "vtr_log.h" #include "annealer.h" #include "place_util.h" @@ -92,10 +93,10 @@ void PlacementLogPrinter::print_place_status(float elapsed_sec) const { VTR_LOG("\n"); fflush(stdout); - sprintf(msg_.data(), "Cost: %g BB Cost %g TD Cost %g Temperature: %g", - costs.cost, costs.bb_cost, costs.timing_cost, annealing_state.t); + sprintf(msg_.data(), "Cost: %g BB Cost %g TD Cost %g Temperature: %g", + costs.cost, costs.bb_cost, costs.timing_cost, annealing_state.t); - update_screen(ScreenUpdatePriority::MINOR, msg_.data(), PLACEMENT, timing_info); + update_screen(ScreenUpdatePriority::MINOR, msg_.data(), PLACEMENT, timing_info); } void PlacementLogPrinter::print_resources_utilization() const { @@ -176,7 +177,10 @@ void PlacementLogPrinter::print_initial_placement_stats() const { std::shared_ptr timing_info = placer_.timing_info_; VTR_LOG("Initial placement cost: %g bb_cost: %g td_cost: %g\n", - costs.cost, costs.bb_cost, costs.timing_cost); + costs.cost, costs.bb_cost, costs.timing_cost); + + double wirelength = placer_.net_cost_handler_.get_total_wirelength_estimate(); + VTR_LOG("Initial placement BB estimate of wirelength: %g\n", wirelength); if (placer_.noc_opts_.noc) { VTR_ASSERT(placer_.noc_cost_handler_.has_value()); @@ -196,13 +200,14 @@ void PlacementLogPrinter::print_initial_placement_stats() const { } const BlkLocRegistry& blk_loc_registry = placer_.placer_state_.blk_loc_registry(); + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; size_t num_macro_members = 0; - for (const t_pl_macro& macro : blk_loc_registry.place_macros().macros()) { + for (const t_pl_macro& macro : place_macros.macros()) { num_macro_members += macro.members.size(); } VTR_LOG("Placement contains %zu placement macros involving %zu blocks (average macro size %f)\n", - blk_loc_registry.place_macros().macros().size(), num_macro_members, - float(num_macro_members) / blk_loc_registry.place_macros().macros().size()); + place_macros.macros().size(), num_macro_members, + float(num_macro_members) / place_macros.macros().size()); VTR_LOG("\n"); sprintf(msg_.data(), @@ -231,6 +236,10 @@ void PlacementLogPrinter::print_post_placement_stats() const { VTR_LOG("Swaps called: %d\n", swap_stats.num_ts_called); placer_.annealer_->get_move_abortion_logger().report_aborted_moves(); + VTR_LOG("\n"); + double estimated_wirelength = placer_.net_cost_handler_.get_total_wirelength_estimate(); + VTR_LOG("BB estimate of min-dist (placement) wire length: %.0f\n", estimated_wirelength); + if (placer_.placer_opts_.place_algorithm.is_timing_driven()) { //Final timing estimate VTR_ASSERT(placer_.timing_info_); @@ -279,7 +288,7 @@ void PlacementLogPrinter::print_post_placement_stats() const { print_resources_utilization(); print_placement_swaps_stats(); - move_type_stats.print_placement_move_types_stats(); + move_type_stats.print_placement_move_types_stats(placer_.placer_state_.blk_loc_registry().movable_blocks_per_type()); if (placer_.noc_opts_.noc) { write_noc_placement_file(placer_.noc_opts_.noc_placement_file_name, @@ -306,7 +315,7 @@ void generate_post_place_timing_reports(const t_placer_opts& placer_opts, const auto& timing_ctx = g_vpr_ctx.timing(); const auto& atom_ctx = g_vpr_ctx.atom(); - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); @@ -317,4 +326,3 @@ void generate_post_place_timing_reports(const t_placer_opts& placer_opts, placer_opts.post_place_timing_report_file, *timing_info.setup_analyzer(), analysis_opts.timing_report_npaths); } - diff --git a/vpr/src/place/placement_log_printer.h b/vpr/src/place/placement_log_printer.h index d538c20d895..e349fbe051f 100644 --- a/vpr/src/place/placement_log_printer.h +++ b/vpr/src/place/placement_log_printer.h @@ -2,7 +2,7 @@ * @file placement_log_printer.h * @brief Declares the PlacementLogPrinter class and associated utilities for logging * and reporting placement-related statistics and timing analysis results. - + * * ### Integration: * The PlacementLogPrinter class integrates with the Placer class to provide information about * the placement process for debugging, optimization, and analysis purposes. @@ -61,6 +61,8 @@ class PlacementLogPrinter { void print_initial_placement_stats() const; /// Prints final placement metrics and generates timing reports. void print_post_placement_stats() const; + /// Returns a bool to indicate whether the instance is in quiet mode. + bool quiet() const { return quiet_; } private: /** diff --git a/vpr/src/place/placer.cpp b/vpr/src/place/placer.cpp index 37b48f11d0d..d850fb0144b 100644 --- a/vpr/src/place/placer.cpp +++ b/vpr/src/place/placer.cpp @@ -1,13 +1,19 @@ #include "placer.h" +#include +#include #include +#include "flat_placement_types.h" +#include "blk_loc_registry.h" +#include "place_macro.h" #include "vtr_time.h" #include "draw.h" #include "read_place.h" #include "analytic_placer.h" #include "initial_placement.h" +#include "load_flat_place.h" #include "concrete_timing_info.h" #include "verify_placement.h" #include "place_timing_update.h" @@ -17,12 +23,13 @@ #include "tatum/echo_writer.hpp" Placer::Placer(const Netlist<>& net_list, + std::optional> init_place, const t_placer_opts& placer_opts, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, const IntraLbPbPinLookup& pb_gpin_lookup, const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - const std::vector& directs, + const FlatPlacementInfo& flat_placement_info, std::shared_ptr place_delay_model, bool cube_bb, bool is_flat, @@ -33,42 +40,55 @@ Placer::Placer(const Netlist<>& net_list, , pb_gpin_lookup_(pb_gpin_lookup) , netlist_pin_lookup_(netlist_pin_lookup) , costs_(placer_opts.place_algorithm, noc_opts.noc) - , placer_state_(placer_opts.place_algorithm.is_timing_driven(), cube_bb) + , placer_state_(placer_opts.place_algorithm.is_timing_driven()) , rng_(placer_opts.seed) , net_cost_handler_(placer_opts, placer_state_, cube_bb) , place_delay_model_(std::move(place_delay_model)) , log_printer_(*this, quiet) + , quench_only_(placer_opts.place_quench_only) , is_flat_(is_flat) { const auto& cluster_ctx = g_vpr_ctx.clustering(); pre_place_timing_stats_ = g_vpr_ctx.timing().stats; - init_placement_context(placer_state_.mutable_blk_loc_registry(), directs); + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; // create a NoC cost handler if NoC optimization is enabled if (noc_opts.noc) { noc_cost_handler_.emplace(placer_state_.block_locs()); } - /* To make sure the importance of NoC-related cost terms compared to - * BB and timing cost is determine only through NoC placement weighting factor, - * we normalize NoC-related cost weighting factors so that they add up to 1. - * With this normalization, NoC-related cost weighting factors only determine - * the relative importance of NoC cost terms with respect to each other, while - * the importance of total NoC cost to conventional placement cost is determined - * by NoC placement weighting factor. - */ - if (noc_opts.noc) { - normalize_noc_cost_weighting_factor(const_cast(noc_opts)); - } - + // Initialize the placement for the Simulated Annealer. BlkLocRegistry& blk_loc_registry = placer_state_.mutable_blk_loc_registry(); - initial_placement(placer_opts, placer_opts.constraints_file.c_str(), - noc_opts, blk_loc_registry, noc_cost_handler_, rng_); + if (init_place.has_value()) { + // If an initial placement has been provided, use that. + blk_loc_registry = *init_place; + } else { + // If an initial placement has not been provided, run the initial placer. + initial_placement(placer_opts, placer_opts.constraints_file.c_str(), + noc_opts, blk_loc_registry, place_macros, noc_cost_handler_, + flat_placement_info, rng_); + + // After initial placement, if a flat placement is being reconstructed, + // print flat placement reconstruction info. + if (flat_placement_info.valid) { + log_flat_placement_reconstruction_info(flat_placement_info, + blk_loc_registry.block_locs(), + g_vpr_ctx.clustering().atoms_lookup, + g_vpr_ctx.atom().lookup(), + g_vpr_ctx.atom().netlist(), + g_vpr_ctx.clustering().clb_nlist); + } + } const int move_lim = (int)(placer_opts.anneal_sched.inner_num * pow(net_list.blocks().size(), 1.3333)); //create the move generator based on the chosen placement strategy - auto [move_generator, move_generator2] = create_move_generators(placer_state_, placer_opts, move_lim, noc_opts.noc_centroid_weight, rng_); + auto [move_generator, move_generator2] = create_move_generators(placer_state_, + place_macros, + net_cost_handler_, + placer_opts, move_lim, + noc_opts.noc_centroid_weight, + rng_); if (!placer_opts.write_initial_place_file.empty()) { print_place(nullptr, nullptr, placer_opts.write_initial_place_file.c_str(), placer_state_.block_locs()); @@ -82,251 +102,250 @@ Placer::Placer(const Netlist<>& net_list, * Most of anneal is disabled later by setting initial temperature to 0 and only further optimizes in quench */ if (placer_opts.enable_analytic_placer) { - AnalyticPlacer{blk_loc_registry}.ap_place(); + AnalyticPlacer{blk_loc_registry, place_macros}.ap_place(); } #endif /* ENABLE_ANALYTIC_PLACE */ // Update physical pin values - for (const ClusterBlockId block_id : cluster_ctx.clb_nlist.blocks()) { - blk_loc_registry.place_sync_external_block_connections(block_id); - } + for (const ClusterBlockId block_id : cluster_ctx.clb_nlist.blocks()) { + blk_loc_registry.place_sync_external_block_connections(block_id); + } - if (!quiet) { + if (!quiet) { #ifndef NO_GRAPHICS - if (noc_cost_handler_.has_value()) { - get_draw_state_vars()->set_noc_link_bandwidth_usages_ref(noc_cost_handler_->get_link_bandwidth_usages()); - } + if (noc_cost_handler_.has_value()) { + get_draw_state_vars()->set_noc_link_bandwidth_usages_ref(noc_cost_handler_->get_link_bandwidth_usages()); + } #endif - // width_fac gives the width of the widest channel - const int width_fac = placer_opts.place_chan_width; - init_draw_coords((float)width_fac, placer_state_.blk_loc_registry()); - } - - // Gets initial cost and loads bounding boxes. - costs_.bb_cost = net_cost_handler_.comp_bb_cost(e_cost_methods::NORMAL); - costs_.bb_cost_norm = 1 / costs_.bb_cost; - - if (placer_opts.place_algorithm.is_timing_driven()) { - alloc_and_init_timing_objects_(net_list, analysis_opts); - } else { - VTR_ASSERT(placer_opts.place_algorithm == e_place_algorithm::BOUNDING_BOX_PLACE); - // Timing cost and normalization factors are not used - constexpr double INVALID_COST = std::numeric_limits::quiet_NaN(); - costs_.timing_cost = INVALID_COST; - costs_.timing_cost_norm = INVALID_COST; - } - - if (noc_opts.noc) { - VTR_ASSERT(noc_cost_handler_.has_value()); - - // get the costs associated with the NoC - costs_.noc_cost_terms.aggregate_bandwidth = noc_cost_handler_->comp_noc_aggregate_bandwidth_cost(); - std::tie(costs_.noc_cost_terms.latency, costs_.noc_cost_terms.latency_overrun) = noc_cost_handler_->comp_noc_latency_cost(); - costs_.noc_cost_terms.congestion = noc_cost_handler_->comp_noc_congestion_cost(); - - // initialize all the noc normalization factors - noc_cost_handler_->update_noc_normalization_factors(costs_); - } - - // set the starting total placement cost - costs_.cost = costs_.get_total_cost(placer_opts, noc_opts); - - // Sanity check that initial placement is legal - check_place_(); - - log_printer_.print_initial_placement_stats(); - - annealer_ = std::make_unique(placer_opts_, placer_state_, costs_, net_cost_handler_, noc_cost_handler_, - noc_opts_, rng_, std::move(move_generator), std::move(move_generator2), place_delay_model_.get(), - placer_criticalities_.get(), placer_setup_slacks_.get(), timing_info_.get(), pin_timing_invalidator_.get(), - move_lim); + // width_fac gives the width of the widest channel + const int width_fac = placer_opts.place_chan_width; + init_draw_coords((float)width_fac, placer_state_.blk_loc_registry()); + } + + // Gets initial cost and loads bounding boxes. + costs_.bb_cost = net_cost_handler_.comp_bb_cost(e_cost_methods::NORMAL).first; + costs_.bb_cost_norm = 1 / costs_.bb_cost; + + if (placer_opts.place_algorithm.is_timing_driven()) { + alloc_and_init_timing_objects_(net_list, analysis_opts); + } else { + VTR_ASSERT(placer_opts.place_algorithm == e_place_algorithm::BOUNDING_BOX_PLACE); + // Timing cost and normalization factors are not used + constexpr double INVALID_COST = std::numeric_limits::quiet_NaN(); + costs_.timing_cost = INVALID_COST; + costs_.timing_cost_norm = INVALID_COST; + } + + if (noc_opts.noc) { + VTR_ASSERT(noc_cost_handler_.has_value()); + + // get the costs associated with the NoC + costs_.noc_cost_terms.aggregate_bandwidth = noc_cost_handler_->comp_noc_aggregate_bandwidth_cost(); + std::tie(costs_.noc_cost_terms.latency, costs_.noc_cost_terms.latency_overrun) = noc_cost_handler_->comp_noc_latency_cost(); + costs_.noc_cost_terms.congestion = noc_cost_handler_->comp_noc_congestion_cost(); + + // initialize all the noc normalization factors + noc_cost_handler_->update_noc_normalization_factors(costs_); + } + + // set the starting total placement cost + costs_.cost = costs_.get_total_cost(placer_opts, noc_opts); + + // Sanity check that initial placement is legal + check_place_(); + + log_printer_.print_initial_placement_stats(); + + annealer_ = std::make_unique(placer_opts_, placer_state_, place_macros, costs_, net_cost_handler_, noc_cost_handler_, + noc_opts_, rng_, std::move(move_generator), std::move(move_generator2), place_delay_model_.get(), + placer_criticalities_.get(), placer_setup_slacks_.get(), timing_info_.get(), pin_timing_invalidator_.get(), + move_lim); } void Placer::alloc_and_init_timing_objects_(const Netlist<>& net_list, const t_analysis_opts& analysis_opts) { - const auto& atom_ctx = g_vpr_ctx.atom(); - const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& timing_ctx = g_vpr_ctx.timing(); - const auto& p_timing_ctx = placer_state_.timing(); + const auto& atom_ctx = g_vpr_ctx.atom(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& timing_ctx = g_vpr_ctx.timing(); + const auto& p_timing_ctx = placer_state_.timing(); - // Update the point-to-point delays from the initial placement - comp_td_connection_delays(place_delay_model_.get(), placer_state_); + // Update the point-to-point delays from the initial placement + comp_td_connection_delays(place_delay_model_.get(), placer_state_); - // Initialize timing analysis - placement_delay_calc_ = std::make_shared(atom_ctx.nlist, - atom_ctx.lookup, - p_timing_ctx.connection_delay, - is_flat_); - placement_delay_calc_->set_tsu_margin_relative(placer_opts_.tsu_rel_margin); - placement_delay_calc_->set_tsu_margin_absolute(placer_opts_.tsu_abs_margin); + // Initialize timing analysis + placement_delay_calc_ = std::make_shared(atom_ctx.netlist(), + atom_ctx.lookup(), + p_timing_ctx.connection_delay, + is_flat_); + placement_delay_calc_->set_tsu_margin_relative(placer_opts_.tsu_rel_margin); + placement_delay_calc_->set_tsu_margin_absolute(placer_opts_.tsu_abs_margin); - timing_info_ = make_setup_timing_info(placement_delay_calc_, placer_opts_.timing_update_type); + timing_info_ = make_setup_timing_info(placement_delay_calc_, placer_opts_.timing_update_type); - placer_setup_slacks_ = std::make_unique(cluster_ctx.clb_nlist, - netlist_pin_lookup_, - timing_info_); + placer_setup_slacks_ = std::make_unique(cluster_ctx.clb_nlist, + netlist_pin_lookup_, + timing_info_); - placer_criticalities_ = std::make_unique(cluster_ctx.clb_nlist, - netlist_pin_lookup_, - timing_info_); + placer_criticalities_ = std::make_unique(cluster_ctx.clb_nlist, + netlist_pin_lookup_, + timing_info_); - pin_timing_invalidator_ = make_net_pin_timing_invalidator(placer_opts_.timing_update_type, - net_list, - netlist_pin_lookup_, - atom_ctx.nlist, - atom_ctx.lookup, - timing_info_, - is_flat_); + pin_timing_invalidator_ = make_net_pin_timing_invalidator(placer_opts_.timing_update_type, + net_list, + netlist_pin_lookup_, + atom_ctx.netlist(), + atom_ctx.lookup(), + timing_info_, + is_flat_); - // First time compute timing and costs, compute from scratch - PlaceCritParams crit_params; - crit_params.crit_exponent = placer_opts_.td_place_exp_first; - crit_params.crit_limit = placer_opts_.place_crit_limit; + // First time compute timing and costs, compute from scratch + PlaceCritParams crit_params; + crit_params.crit_exponent = placer_opts_.td_place_exp_first; + crit_params.crit_limit = placer_opts_.place_crit_limit; - initialize_timing_info(crit_params, place_delay_model_.get(), placer_criticalities_.get(), - placer_setup_slacks_.get(), pin_timing_invalidator_.get(), - timing_info_.get(), &costs_, placer_state_); + initialize_timing_info(crit_params, place_delay_model_.get(), placer_criticalities_.get(), + placer_setup_slacks_.get(), pin_timing_invalidator_.get(), + timing_info_.get(), &costs_, placer_state_); - critical_path_ = timing_info_->least_slack_critical_path(); + critical_path_ = timing_info_->least_slack_critical_path(); - // Write out the initial timing echo file - if (isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH)) { - tatum::write_echo(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH), - *timing_ctx.graph, *timing_ctx.constraints, - *placement_delay_calc_, timing_info_->analyzer()); + // Write out the initial timing echo file + if (isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH)) { + tatum::write_echo(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH), + *timing_ctx.graph, *timing_ctx.constraints, + *placement_delay_calc_, timing_info_->analyzer()); - tatum::NodeId debug_tnode = id_or_pin_name_to_tnode(analysis_opts.echo_dot_timing_graph_node); + tatum::NodeId debug_tnode = id_or_pin_name_to_tnode(analysis_opts.echo_dot_timing_graph_node); - write_setup_timing_graph_dot(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH) + std::string(".dot"), - *timing_info_, debug_tnode); - } + write_setup_timing_graph_dot(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH) + std::string(".dot"), + *timing_info_, debug_tnode); + } - costs_.timing_cost_norm = 1 / costs_.timing_cost; + costs_.timing_cost_norm = 1 / costs_.timing_cost; } void Placer::check_place_() { - const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const DeviceGrid& device_grid = g_vpr_ctx.device().grid; - const auto& cluster_constraints = g_vpr_ctx.floorplanning().cluster_constraints; - - int error = 0; - - // Verify the placement invariants independent to the placement flow. - error += verify_placement(placer_state_.blk_loc_registry(), - clb_nlist, - device_grid, - cluster_constraints); - - error += check_placement_costs_(); - - if (noc_opts_.noc) { - // check the NoC costs during placement if the user is using the NoC supported flow - error += noc_cost_handler_->check_noc_placement_costs(costs_, PL_INCREMENTAL_COST_TOLERANCE, noc_opts_); - // make sure NoC routing configuration does not create any cycles in CDG - error += (int)noc_cost_handler_->noc_routing_has_cycle(); - } - - if (error == 0) { - VTR_LOG("\n"); - VTR_LOG("Completed placement consistency check successfully.\n"); - - } else { - VPR_ERROR(VPR_ERROR_PLACE, - "\nCompleted placement consistency check, %d errors found.\n" - "Aborting program.\n", - error); - } + const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + const DeviceGrid& device_grid = g_vpr_ctx.device().grid; + const auto& cluster_constraints = g_vpr_ctx.floorplanning().cluster_constraints; + const PlaceMacros& place_macros = *g_vpr_ctx.placement().place_macros; + + int error = 0; + + // Verify the placement invariants independent to the placement flow. + error += verify_placement(placer_state_.blk_loc_registry(), + place_macros, + clb_nlist, + device_grid, + cluster_constraints); + + error += check_placement_costs_(); + + if (noc_opts_.noc) { + // check the NoC costs during placement if the user is using the NoC supported flow + error += noc_cost_handler_->check_noc_placement_costs(costs_, PL_INCREMENTAL_COST_TOLERANCE, noc_opts_); + // make sure NoC routing configuration does not create any cycles in CDG + error += (int)noc_cost_handler_->noc_routing_has_cycle(); + } + + if (error == 0) { + VTR_LOGV(!log_printer_.quiet(), + "\nCompleted placement consistency check successfully.\n"); + + } else { + VPR_ERROR(VPR_ERROR_PLACE, + "\nCompleted placement consistency check, %d errors found.\n" + "Aborting program.\n", + error); + } } int Placer::check_placement_costs_() { - int error = 0; - double timing_cost_check; - - double bb_cost_check = net_cost_handler_.comp_bb_cost(e_cost_methods::CHECK); - - if (fabs(bb_cost_check - costs_.bb_cost) > costs_.bb_cost * PL_INCREMENTAL_COST_TOLERANCE) { - VTR_LOG_ERROR( - "bb_cost_check: %g and bb_cost: %g differ in check_place.\n", - bb_cost_check, costs_.bb_cost); - error++; - } - - if (placer_opts_.place_algorithm.is_timing_driven()) { - comp_td_costs(place_delay_model_.get(), *placer_criticalities_, placer_state_, &timing_cost_check); - //VTR_LOG("timing_cost recomputed from scratch: %g\n", timing_cost_check); - if (fabs(timing_cost_check - costs_.timing_cost) > costs_.timing_cost * PL_INCREMENTAL_COST_TOLERANCE) { - VTR_LOG_ERROR( - "timing_cost_check: %g and timing_cost: %g differ in check_place.\n", - timing_cost_check, costs_.timing_cost); - error++; - } - } - return error; -} + int error = 0; + double timing_cost_check; -void Placer::place() { - const auto& timing_ctx = g_vpr_ctx.timing(); - const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto [bb_cost_check, expected_wirelength] = net_cost_handler_.comp_bb_cost(e_cost_methods::CHECK); + if (fabs(bb_cost_check - costs_.bb_cost) > costs_.bb_cost * PL_INCREMENTAL_COST_TOLERANCE) { + VTR_LOG_ERROR( + "bb_cost_check: %g and bb_cost: %g differ in check_place.\n", + bb_cost_check, costs_.bb_cost); + error++; + } + + if (placer_opts_.place_algorithm.is_timing_driven()) { + comp_td_costs(place_delay_model_.get(), *placer_criticalities_, placer_state_, &timing_cost_check); + if (fabs(timing_cost_check - costs_.timing_cost) > costs_.timing_cost * PL_INCREMENTAL_COST_TOLERANCE) { + VTR_LOG_ERROR( + "timing_cost_check: %g and timing_cost: %g differ in check_place.\n", + timing_cost_check, costs_.timing_cost); + error++; + } + } + return error; +} - bool skip_anneal = false; +void Placer::place() { + const auto& timing_ctx = g_vpr_ctx.timing(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + bool analytic_place_enabled = false; #ifdef ENABLE_ANALYTIC_PLACE - // Cluster-level analytic placer: when enabled, skip most of the annealing and go straight to quench - if (placer_opts_.enable_analytic_placer) { - skip_anneal = true; - } + // Cluster-level analytic placer: when enabled, skip most of the annealing and go straight to quench + if (placer_opts_.enable_analytic_placer) { + analytic_place_enabled = true; + } #endif - if (!skip_anneal) { - // Table header - log_printer_.print_place_status_header(); + if (!analytic_place_enabled && !quench_only_) { + // Table header + log_printer_.print_place_status_header(); - // Outer loop of the simulated annealing begins - do { - vtr::Timer temperature_timer; + // Outer loop of the simulated annealing begins + do { + vtr::Timer temperature_timer; - annealer_->outer_loop_update_timing_info(); + annealer_->outer_loop_update_timing_info(); - if (placer_opts_.place_algorithm.is_timing_driven()) { - critical_path_ = timing_info_->least_slack_critical_path(); + if (placer_opts_.place_algorithm.is_timing_driven()) { + critical_path_ = timing_info_->least_slack_critical_path(); - // see if we should save the current placement solution as a checkpoint - if (placer_opts_.place_checkpointing && annealer_->get_agent_state() == e_agent_state::LATE_IN_THE_ANNEAL) { - save_placement_checkpoint_if_needed(placer_state_.mutable_block_locs(), - placement_checkpoint_, - timing_info_, costs_, critical_path_.delay()); - } - } + // see if we should save the current placement solution as a checkpoint + if (placer_opts_.place_checkpointing && annealer_->get_agent_state() == e_agent_state::LATE_IN_THE_ANNEAL) { + save_placement_checkpoint_if_needed(placer_state_.mutable_block_locs(), + placement_checkpoint_, + timing_info_, costs_, critical_path_.delay()); + } + } - // do a complete inner loop iteration - annealer_->placement_inner_loop(); + // do a complete inner loop iteration + annealer_->placement_inner_loop(); - log_printer_.print_place_status(temperature_timer.elapsed_sec()); + log_printer_.print_place_status(temperature_timer.elapsed_sec()); - // Outer loop of the simulated annealing ends - } while (annealer_->outer_loop_update_state()); - } //skip_anneal ends + // Outer loop of the simulated annealing ends + } while (annealer_->outer_loop_update_state()); + } //skip_anneal ends // Start Quench annealer_->start_quench(); pre_quench_timing_stats_ = timing_ctx.stats; { // Quench - vtr::ScopedFinishTimer temperature_timer("Placement Quench"); + vtr::ScopedFinishTimer temperature_timer("Placement Quench"); - annealer_->outer_loop_update_timing_info(); + annealer_->outer_loop_update_timing_info(); - /* Run inner loop again with temperature = 0 so as to accept only swaps - * which reduce the cost of the placement */ - annealer_->placement_inner_loop(); + /* Run inner loop again with temperature = 0 so as to accept only swaps + * which reduce the cost of the placement */ + annealer_->placement_inner_loop(); - if (placer_opts_.place_quench_algorithm.is_timing_driven()) { - critical_path_ = timing_info_->least_slack_critical_path(); - } + if (placer_opts_.place_quench_algorithm.is_timing_driven()) { + critical_path_ = timing_info_->least_slack_critical_path(); + } - log_printer_.print_place_status(temperature_timer.elapsed_sec()); + log_printer_.print_place_status(temperature_timer.elapsed_sec()); } post_quench_timing_stats_ = timing_ctx.stats; @@ -337,34 +356,34 @@ void Placer::place() { crit_params.crit_limit = placer_opts_.place_crit_limit; if (placer_opts_.place_algorithm.is_timing_driven()) { - perform_full_timing_update(crit_params, place_delay_model_.get(), placer_criticalities_.get(), - placer_setup_slacks_.get(), pin_timing_invalidator_.get(), - timing_info_.get(), &costs_, placer_state_); + perform_full_timing_update(crit_params, place_delay_model_.get(), placer_criticalities_.get(), + placer_setup_slacks_.get(), pin_timing_invalidator_.get(), + timing_info_.get(), &costs_, placer_state_); - critical_path_ = timing_info_->least_slack_critical_path(); + critical_path_ = timing_info_->least_slack_critical_path(); - VTR_LOG("post-quench CPD = %g (ns) \n", - 1e9 * critical_path_.delay()); + VTR_LOGV(!log_printer_.quiet(), + "post-quench CPD = %g (ns) \n", 1e9 * critical_path_.delay()); } // See if our latest checkpoint is better than the current placement solution if (placer_opts_.place_checkpointing) { - restore_best_placement(placer_state_, - placement_checkpoint_, timing_info_, costs_, - placer_criticalities_, placer_setup_slacks_, place_delay_model_, - pin_timing_invalidator_, crit_params, noc_cost_handler_); + restore_best_placement(placer_state_, + placement_checkpoint_, timing_info_, costs_, + placer_criticalities_, placer_setup_slacks_, place_delay_model_, + pin_timing_invalidator_, crit_params, noc_cost_handler_); } if (placer_opts_.placement_saves_per_temperature >= 1) { - std::string filename = vtr::string_fmt("placement_%03d_%03d.place", - annealing_state.num_temps + 1, 0); - VTR_LOG("Saving final placement to file: %s\n", filename.c_str()); - print_place(nullptr, nullptr, filename.c_str(), placer_state_.mutable_block_locs()); + std::string filename = vtr::string_fmt("placement_%03d_%03d.place", + annealing_state.num_temps + 1, 0); + VTR_LOGV(!log_printer_.quiet(), "Saving final placement to file: %s\n", filename.c_str()); + print_place(nullptr, nullptr, filename.c_str(), placer_state_.mutable_block_locs()); } // Update physical pin values for (const ClusterBlockId block_id : cluster_ctx.clb_nlist.blocks()) { - placer_state_.mutable_blk_loc_registry().place_sync_external_block_connections(block_id); + placer_state_.mutable_blk_loc_registry().place_sync_external_block_connections(block_id); } check_place_(); diff --git a/vpr/src/place/placer.h b/vpr/src/place/placer.h index 99c00d7e8e5..61a8301818c 100644 --- a/vpr/src/place/placer.h +++ b/vpr/src/place/placer.h @@ -17,31 +17,37 @@ #pragma once +#include #include #include -#include "timing_place.h" +#include "annealer.h" #include "place_checkpoint.h" #include "PlacementDelayCalculator.h" #include "placer_state.h" #include "noc_place_utils.h" #include "net_cost_handler.h" #include "placement_log_printer.h" +#include "PlacerSetupSlacks.h" +#include "PlacerCriticalities.h" +#include "NetPinTimingInvalidator.h" -class PlacementAnnealer; -namespace vtr{ +class BlkLocRegistry; +class FlatPlacementInfo; +namespace vtr { class ScopedStartFinishTimer; } class Placer { public: Placer(const Netlist<>& net_list, + std::optional> init_place, const t_placer_opts& placer_opts, const t_analysis_opts& analysis_opts, const t_noc_opts& noc_opts, const IntraLbPbPinLookup& pb_gpin_lookup, const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - const std::vector& directs, + const FlatPlacementInfo& flat_placement_info, std::shared_ptr place_delay_model, bool cube_bb, bool is_flat, @@ -91,6 +97,8 @@ class Placer { std::shared_ptr place_delay_model_; /// Prints logs during placement const PlacementLogPrinter log_printer_; + /// Indicates if the placement quench phase should be skipped. + const bool quench_only_; /// Indicates if flat routing resource graph and delay model is used. It should be false. const bool is_flat_; diff --git a/vpr/src/place/placer_breakpoint.cpp b/vpr/src/place/placer_breakpoint.cpp index a31a0add053..d71430f2090 100644 --- a/vpr/src/place/placer_breakpoint.cpp +++ b/vpr/src/place/placer_breakpoint.cpp @@ -1,6 +1,5 @@ #include "placer_breakpoint.h" - //map of the available move types and their corresponding type number std::map available_move_types = { {0, "Uniform"}}; @@ -17,8 +16,11 @@ void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected) { } } -void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, e_move_result move_outcome, - double delta_c, double bb_delta_c, double timing_delta_c) { +void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, + e_move_result move_outcome, + double delta_c, + double bb_delta_c, + double timing_delta_c) { t_draw_state* draw_state = get_draw_state_vars(); BreakpointState* bp_state = get_bp_state_globals()->get_glob_breakpoint_state(); diff --git a/vpr/src/place/placer_breakpoint.h b/vpr/src/place/placer_breakpoint.h index 510b7071e0d..159e9c40b38 100644 --- a/vpr/src/place/placer_breakpoint.h +++ b/vpr/src/place/placer_breakpoint.h @@ -1,5 +1,5 @@ -#ifndef PLACER_BREAKPOINT_H -#define PLACER_BREAKPOINT_H + +#pragma once #include "globals.h" #include "vpr_types.h" @@ -7,13 +7,12 @@ #include "breakpoint.h" #include "draw.h" - //transforms the vector moved_blocks to a vector of ints and adds it in glob_breakpoint_state void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected); //checks the breakpoint and see whether one of them was reached and pause place,emt accordingly -void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, e_move_result move_outcome, - double delta_c, double bb_delta_c, double timing_delta_c); - - -#endif +void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, + e_move_result move_outcome, + double delta_c, + double bb_delta_c, + double timing_delta_c); diff --git a/vpr/src/place/placer_state.cpp b/vpr/src/place/placer_state.cpp index 998c097b4ca..c0bba0052be 100644 --- a/vpr/src/place/placer_state.cpp +++ b/vpr/src/place/placer_state.cpp @@ -4,29 +4,6 @@ #include "globals.h" #include "move_transactions.h" -PlacerMoveContext::PlacerMoveContext(bool cube_bb) { - const auto& device_ctx = g_vpr_ctx.device(); - const auto& cluster_ctx = g_vpr_ctx.clustering(); - - const size_t num_nets = cluster_ctx.clb_nlist.nets().size(); - - const int num_layers = device_ctx.grid.get_num_layers(); - - if (cube_bb) { - bb_coords.resize(num_nets, t_bb()); - bb_num_on_edges.resize(num_nets, t_bb()); - } else { - layer_bb_num_on_edges.resize(num_nets, std::vector(num_layers, t_2D_bb())); - layer_bb_coords.resize(num_nets, std::vector(num_layers, t_2D_bb())); - } - - num_sink_pin_layer.resize({num_nets, size_t(num_layers)}); - for (size_t flat_idx = 0; flat_idx < num_sink_pin_layer.size(); flat_idx++) { - int& elem = num_sink_pin_layer.get(flat_idx); - elem = OPEN; - } -} - PlacerTimingContext::PlacerTimingContext(bool placement_is_timing_driven) { const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -85,7 +62,6 @@ void PlacerTimingContext::revert_td_cost(const t_pl_blocks_to_be_moved& blocks_a auto& cluster_ctx = g_vpr_ctx.clustering(); auto& clb_nlist = cluster_ctx.clb_nlist; - for (ClusterPinId pin : blocks_affected.affected_pins) { ClusterNetId net = clb_nlist.pin_net(pin); int ipin = clb_nlist.pin_net_index(pin); @@ -95,7 +71,5 @@ void PlacerTimingContext::revert_td_cost(const t_pl_blocks_to_be_moved& blocks_a #endif } -PlacerState::PlacerState(bool placement_is_timing_driven, bool cube_bb) - : timing_(placement_is_timing_driven) - , move_(cube_bb) {} - +PlacerState::PlacerState(bool placement_is_timing_driven) + : timing_(placement_is_timing_driven) {} diff --git a/vpr/src/place/placer_state.h b/vpr/src/place/placer_state.h index 8f3b966a56d..10592ebcfca 100644 --- a/vpr/src/place/placer_state.h +++ b/vpr/src/place/placer_state.h @@ -12,7 +12,7 @@ #include "vpr_context.h" #include "vpr_net_pins_matrix.h" #include "vpr_types.h" -#include "timing_place.h" +#include "PlacerTimingCosts.h" /** * @brief State relating to the timing driven data. @@ -111,47 +111,6 @@ struct PlacerRuntimeContext : public Context { float f_update_td_costs_total_elapsed_sec; }; -/** - * @brief Placement Move generators data - */ -struct PlacerMoveContext : public Context { - public: - PlacerMoveContext() = delete; - explicit PlacerMoveContext(bool cube_bb); - - public: - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each of a net's bounding box (to allow efficient updates) - vtr::vector bb_num_on_edges; - - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the bounding box coordinates of a net's bounding box - vtr::vector bb_coords; - - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each of a net's bounding box (to allow efficient updates) - vtr::vector> layer_bb_num_on_edges; - - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the bounding box coordinates of a net's bounding box - vtr::vector> layer_bb_coords; - - // [0..cluster_ctx.clb_nlist.nets().size()-1]. Store the number of blocks on each layer () - vtr::Matrix num_sink_pin_layer; - - // The first range limit calculated by the annealer - float first_rlim; - - // Scratch vectors that are used by different directed moves for temporary calculations - // These vectors will grow up with the net size as it is mostly used to save coords of the net pins or net bb edges - // Given that placement moves involve operations on each coordinate independently, we chose to - // utilize a Struct of Arrays (SoA) rather than an Array of Struct (AoS). - std::vector X_coord; - std::vector Y_coord; - std::vector layer_coord; - - // Container to save the highly critical pins (higher than a timing criticality limit set by commandline option) - std::vector> highly_crit_pins; -}; - - - /** * @brief This object encapsulates VPR placer's state. * @@ -167,7 +126,7 @@ struct PlacerMoveContext : public Context { */ class PlacerState : public Context { public: - PlacerState(bool placement_is_timing_driven, bool cube_bb); + PlacerState(bool placement_is_timing_driven); public: inline const PlacerTimingContext& timing() const { return timing_; } @@ -176,9 +135,6 @@ class PlacerState : public Context { inline const PlacerRuntimeContext& runtime() const { return runtime_; } inline PlacerRuntimeContext& mutable_runtime() { return runtime_; } - inline const PlacerMoveContext& move() const { return move_; } - inline PlacerMoveContext& mutable_move() { return move_; } - inline const vtr::vector_map& block_locs() const { return blk_loc_registry_.block_locs(); } inline vtr::vector_map& mutable_block_locs() { return blk_loc_registry_.mutable_block_locs(); } @@ -194,7 +150,6 @@ class PlacerState : public Context { private: PlacerTimingContext timing_; PlacerRuntimeContext runtime_; - PlacerMoveContext move_; /** * @brief Contains: 1) The location where each clustered block is placed at. diff --git a/vpr/src/place/timing/PlacerCriticalities.cpp b/vpr/src/place/timing/PlacerCriticalities.cpp new file mode 100644 index 00000000000..4cbf1ec66ec --- /dev/null +++ b/vpr/src/place/timing/PlacerCriticalities.cpp @@ -0,0 +1,117 @@ + +#include "PlacerCriticalities.h" + +#include "timing_info.h" +#include "timing_util.h" + +PlacerCriticalities::PlacerCriticalities(const ClusteredNetlist& clb_nlist, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info) + : clb_nlist_(clb_nlist) + , pin_lookup_(netlist_pin_lookup) + , timing_info_(std::move(timing_info)) + , timing_place_crit_(make_net_pins_matrix(clb_nlist_, std::numeric_limits::quiet_NaN())) { +} + +void PlacerCriticalities::update_criticalities(const PlaceCritParams& crit_params) { + // If update is not enabled, exit the routine. + if (!update_enabled) { + // re-computation is required on the next iteration + recompute_required = true; + return; + } + + // Determine what pins need updating + if (!recompute_required && crit_params.crit_exponent == last_crit_exponent_) { + incr_update_criticalities(); + } else { + recompute_criticalities(); + + // Record new criticality exponent + last_crit_exponent_ = crit_params.crit_exponent; + } + + /* Performs a 1-to-1 mapping from criticality to timing_place_crit_. + * For every pin on every net (or, equivalently, for every tedge ending + * in that pin), timing_place_crit_ = criticality^(criticality exponent) */ + + // Update the affected pins + for (ClusterPinId clb_pin : cluster_pins_with_modified_criticality_) { + ClusterNetId clb_net = clb_nlist_.pin_net(clb_pin); + int pin_index_in_net = clb_nlist_.pin_net_index(clb_pin); + + float clb_pin_crit = calculate_clb_net_pin_criticality(*timing_info_, pin_lookup_, ParentPinId(size_t(clb_pin)), /*is_flat=*/false); + float new_crit = pow(clb_pin_crit, crit_params.crit_exponent); + + /* Update the highly critical pins container + * + * If the old criticality < limit and the new criticality > limit --> add this pin to the highly critical pins + * If the old criticality > limit and the new criticality < limit --> remove this pin from the highly critical pins + */ + if (!first_time_update_criticality) { + if (new_crit > crit_params.crit_limit && timing_place_crit_[clb_net][pin_index_in_net] < crit_params.crit_limit) { + highly_crit_pins.emplace_back(clb_net, pin_index_in_net); + } else if (new_crit < crit_params.crit_limit && timing_place_crit_[clb_net][pin_index_in_net] > crit_params.crit_limit) { + highly_crit_pins.erase(std::remove(highly_crit_pins.begin(), highly_crit_pins.end(), std::make_pair(clb_net, pin_index_in_net)), + highly_crit_pins.end()); + } + } else { + if (new_crit > crit_params.crit_limit) { + highly_crit_pins.emplace_back(clb_net, pin_index_in_net); + } + } + + /* The placer likes a great deal of contrast between criticalities. + * Since path criticality varies much more than timing, we "sharpen" timing + * criticality by taking it to some power, crit_exponent (between 1 and 8 by default). */ + timing_place_crit_[clb_net][pin_index_in_net] = new_crit; + } + + /* Criticalities updated. In sync with timing info. + * Can be incrementally updated on the next iteration */ + recompute_required = false; + + first_time_update_criticality = false; +} + +void PlacerCriticalities::set_recompute_required() { + recompute_required = true; +} + +void PlacerCriticalities::incr_update_criticalities() { + cluster_pins_with_modified_criticality_.clear(); + + for (AtomPinId atom_pin : timing_info_->pins_with_modified_setup_criticality()) { + ClusterPinId clb_pin = pin_lookup_.connected_clb_pin(atom_pin); + + /* Some atom pins correspond to connections which are completely + * contained within a cluster, and hence have no corresponding + * clustered pin. */ + if (!clb_pin) continue; + + cluster_pins_with_modified_criticality_.insert(clb_pin); + } +} + +void PlacerCriticalities::recompute_criticalities() { + cluster_pins_with_modified_criticality_.clear(); + + // Non-incremental: all sink pins need updating + for (ClusterNetId net_id : clb_nlist_.nets()) { + for (ClusterPinId pin_id : clb_nlist_.net_sinks(net_id)) { + cluster_pins_with_modified_criticality_.insert(pin_id); + } + } +} + +///@brief Override the criticality of a particular connection. +void PlacerCriticalities::set_criticality(ClusterNetId net_id, int ipin, float crit_val) { + VTR_ASSERT_SAFE_MSG(ipin > 0, "The pin should not be a driver pin (ipin != 0)"); + VTR_ASSERT_SAFE_MSG(ipin < int(clb_nlist_.net_pins(net_id).size()), "The pin index in net should be smaller than fanout"); + + timing_place_crit_[net_id][ipin] = crit_val; +} + +PlacerCriticalities::pin_range PlacerCriticalities::pins_with_modified_criticality() const { + return vtr::make_range(cluster_pins_with_modified_criticality_); +} diff --git a/vpr/src/place/timing/PlacerCriticalities.h b/vpr/src/place/timing/PlacerCriticalities.h new file mode 100644 index 00000000000..5ad0ef80735 --- /dev/null +++ b/vpr/src/place/timing/PlacerCriticalities.h @@ -0,0 +1,214 @@ + +#pragma once + +#include "vtr_vec_id_set.h" +#include "timing_info_fwd.h" +#include "clustered_netlist_utils.h" +#include "place_delay_model.h" +#include "vpr_net_pins_matrix.h" + +/** + * @brief Saves the placement criticality parameters + * + * crit_exponent: The criticality exponent used to sharpen the criticalities + * crit_limit: The limit to consider a pin as timing critical + */ +struct PlaceCritParams { + float crit_exponent; + float crit_limit; +}; + +/** + * @brief PlacerCriticalities returns the clustered netlist connection criticalities + * used by the placer ('sharpened' by a criticality exponent). + * + * Usage + * ===== + * This class also serves to map atom netlist level criticalites (i.e. on AtomPinIds) + * to the clustered netlist (i.e. ClusterPinIds) used during placement. + * + * Criticalities are updated by update_criticalities(), given that `update_enabled` is + * set to true. It will update criticalities based on the atom netlist connection + * criticalities provided by the passed in SetupTimingInfo. + * + * This process can be done incrementally, based on the modified connections/AtomPinIds + * returned by SetupTimingInfo. However, the set returned only reflects the connections + * changed by the last call to the timing info update (update_setup() method of SetupTimingInfo). + * + * Therefore, if SetupTimingInfo is updated twice in a row without criticalities + * getting updated after the first update of SetupTimingInfo (PlacerCriticalities::update_enabled = false), + * the returned set of modified connections/AtomPinIds by SetupTimingInfo after its second update does not + * account for all the connections that have been modified. + * To address this issue, whenever update_criticalities() is called with flag update_enabled = false, + * we don't update criticalities and set flag recompute_required to true to remember that criticalities + * need to be recomputed from scratch in the first call to update_criticalities() with update_enabled = true. + * + * This class also maps/transforms the modified atom connections/pins returned by the + * timing info into modified clustered netlist connections/pins after calling + * update_criticalities(). The interface then enables users to iterate over this range + * via pins_with_modified_criticalities(). This is useful for incrementally re-calculating + * the timing costs. + * + * The criticalities of individual connections can then be queried by calling the + * criticality() member function. + * + * Implementation + * ============== + * To support incremental re-calculation, the class saves the last criticality exponent + * passed to PlacerCriticalities::update_criticalites(). If the next update uses the same + * exponent, criticalities can be incrementally updated. Otherwise, they must be re-calculated + * from scratch, since a change in exponent changes *all* criticalities. + * + * Calculating criticalities: + * All the raw setup slack values across a single clock domain are gathered + * and rated from the best to the worst in terms of criticalities. In order + * to calculate criticalities, all the slack values need to be non-negative. + * Hence, if the worst slack is negative, all the slack values are shifted + * by the value of the worst slack so that the value is at least 0. If the + * worst slack is positive, then no shift happens. + * + * The best (shifted) slack (the most positive one) will have a criticality of 0. + * The worst (shifted) slack value will have a criticality of 1. + * + * Criticalities are used to calculated timing costs for each connection. + * The formula is cost = delay * criticality. + * + * For a more detailed description on how criticalities are calculated, see + * calc_relaxed_criticality() in `timing_util.cpp`. + */ +class PlacerCriticalities { + public: //Types + typedef vtr::vec_id_set::iterator pin_iterator; + typedef vtr::vec_id_set::iterator net_iterator; + + typedef vtr::Range pin_range; + typedef vtr::Range net_range; + + public: //Lifetime + /** + * @brief Allocates space for the timing_place_crit_ data structure. + * @param clb_nlist Used to lookup and iterate clustered netlist connections. + * @param netlist_pin_lookup Used to lookup Atom/Clustered pins connected to a Clustered/Atom pin. + * @param timing_info Holds setup timing info. + * + * @note timing_info may be shared by multiple objects with different lifetimes. + * To ensure timing_info is destroyed only after all its user object are destructed, + * each user object should hold a shared_ptr to it. + */ + PlacerCriticalities(const ClusteredNetlist& clb_nlist, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info); + + PlacerCriticalities(const PlacerCriticalities&) = delete; + PlacerCriticalities& operator=(const PlacerCriticalities&) = delete; + + public: //Accessors + ///@brief Returns the criticality of the specified connection. + float criticality(ClusterNetId net, int ipin) const { return timing_place_crit_[net][ipin]; } + + /** + * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) which + * were modified by the last call to PlacerCriticalities::update_criticalities(). + */ + pin_range pins_with_modified_criticality() const; + + /// @brief Returns a constant reference to highly critical pins + const std::vector>& get_highly_critical_pins() const { return highly_crit_pins; } + + public: //Modifiers + /** + * @brief Updates criticalities based on the atom netlist criticalities + * provided by timing_info and the provided criticality_exponent. + * + * Should consistently call this method after the most recent timing analysis to + * keep the criticalities stored in this class in sync with the timing analyzer. + * If out of sync, then the criticalities cannot be incrementally updated on + * during the next timing analysis iteration. + * + * If the criticalities are not updated immediately after each time we call + * timing_info->update(), then timing_info->pins_with_modified_setup_criticality() + * cannot accurately account for all the pins that need to be updated. In this case, + * `recompute_required` would be true, and we update all criticalities from scratch. + * If the criticality exponent has changed, we also need to update from scratch. + */ + void update_criticalities(const PlaceCritParams& crit_params); + + ///@bried Enable the recompute_required flag to enforce from scratch update. + void set_recompute_required(); + + /** + * @brief Collect all the sink pins in the netlist and prepare them update. + * + * For the incremental version, see PlacerCriticalities::incr_update_criticalities(). + */ + void recompute_criticalities(); + + ///@brief Override the criticality of a particular connection. + void set_criticality(ClusterNetId net, int ipin, float crit_val); + + ///@brief Set `update_enabled` to true. + void enable_update() { update_enabled = true; } + + ///@brief Set `update_enabled` to true. + void disable_update() { update_enabled = false; } + + private: //Data + ///@brief The clb netlist in the placement context. + const ClusteredNetlist& clb_nlist_; + + ///@brief The lookup table that maps atom pins to clb pins. + const ClusteredPinAtomPinsLookup& pin_lookup_; + + ///@brief A pointer to the setup timing analyzer + std::shared_ptr timing_info_; + + /** + * @brief The matrix that stores criticality value for each connection. + * + * Index range: [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1] + */ + ClbNetPinsMatrix timing_place_crit_; + + /** + * The criticality exponent when update_criticalites() was last called + * (used to detect if incremental update can be used). + */ + float last_crit_exponent_ = std::numeric_limits::quiet_NaN(); + + ///@brief Set of pins with criticalities modified by last call to update_criticalities(). + vtr::vec_id_set cluster_pins_with_modified_criticality_; + + /** + * @brief Collect the cluster pins which need to be updated based on the latest timing + * analysis so that incremental updates to criticalities can be performed. + * + * Note we use the set of pins reported by the *timing_info* as having modified + * criticality, rather than those marked as modified by the timing analyzer. + * + * Since timing_info uses shifted/relaxed criticality (which depends on max required + * time and worst case slacks), additional nodes may be modified when updating the + * atom pin criticalities. + */ + void incr_update_criticalities(); + + ///@brief Flag that turns on/off the update_criticalities() routine. + bool update_enabled = true; + + /** + * @brief Flag that checks if criticalities need to be recomputed for all connections. + * + * Used by the method update_criticalities(). They incremental update is not possible + * if this method wasn't called updated after the previous timing info update. + */ + bool recompute_required = true; + + /** + * @brief if this is first time to call update_criticality + * + * This can be used for incremental criticality update and also incrementally update the highly critical pins + */ + bool first_time_update_criticality = true; + + /// @brief Saves the highly critical pins (higher than a timing criticality limit set by commandline option) + std::vector> highly_crit_pins; +}; diff --git a/vpr/src/place/timing/PlacerSetupSlacks.cpp b/vpr/src/place/timing/PlacerSetupSlacks.cpp new file mode 100644 index 00000000000..ac8f74d2d7e --- /dev/null +++ b/vpr/src/place/timing/PlacerSetupSlacks.cpp @@ -0,0 +1,81 @@ + +#include "PlacerSetupSlacks.h" + +#include "timing_util.h" +#include "timing_info.h" + +PlacerSetupSlacks::PlacerSetupSlacks(const ClusteredNetlist& clb_nlist, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info) + : clb_nlist_(clb_nlist) + , pin_lookup_(netlist_pin_lookup) + , timing_info_(std::move(timing_info)) + , timing_place_setup_slacks_(make_net_pins_matrix(clb_nlist_, std::numeric_limits::quiet_NaN())) { +} + +void PlacerSetupSlacks::update_setup_slacks() { + // If update is not enabled, exit the routine. + if (!update_enabled) { + // re-computation is required on the next iteration + recompute_required = true; + return; + } + + // Determine what pins need updating + if (!recompute_required) { + incr_update_setup_slacks(); + } else { + recompute_setup_slacks(); + } + + // Update the affected pins + for (ClusterPinId clb_pin : cluster_pins_with_modified_setup_slack_) { + ClusterNetId clb_net = clb_nlist_.pin_net(clb_pin); + int pin_index_in_net = clb_nlist_.pin_net_index(clb_pin); + + float clb_pin_setup_slack = calculate_clb_net_pin_setup_slack(*timing_info_, pin_lookup_, clb_pin); + + timing_place_setup_slacks_[clb_net][pin_index_in_net] = clb_pin_setup_slack; + } + + /* Setup slacks updated. In sync with timing info. + * Can be incrementally updated on the next iteration. */ + recompute_required = false; +} + +void PlacerSetupSlacks::incr_update_setup_slacks() { + cluster_pins_with_modified_setup_slack_.clear(); + + for (AtomPinId atom_pin : timing_info_->pins_with_modified_setup_slack()) { + ClusterPinId clb_pin = pin_lookup_.connected_clb_pin(atom_pin); + + //Some atom pins correspond to connections which are completely + //contained within a cluster, and hence have no corresponding + //clustered pin. + if (!clb_pin) continue; + + cluster_pins_with_modified_setup_slack_.insert(clb_pin); + } +} + +void PlacerSetupSlacks::recompute_setup_slacks() { + cluster_pins_with_modified_setup_slack_.clear(); + + // Non-incremental: all sink pins need updating + for (ClusterNetId net_id : clb_nlist_.nets()) { + for (ClusterPinId pin_id : clb_nlist_.net_sinks(net_id)) { + cluster_pins_with_modified_setup_slack_.insert(pin_id); + } + } +} + +void PlacerSetupSlacks::set_setup_slack(ClusterNetId net_id, int ipin, float slack_val) { + VTR_ASSERT_SAFE_MSG(ipin > 0, "The pin should not be a driver pin (ipin != 0)"); + VTR_ASSERT_SAFE_MSG(ipin < int(clb_nlist_.net_pins(net_id).size()), "The pin index in net should be smaller than fanout"); + + timing_place_setup_slacks_[net_id][ipin] = slack_val; +} + +PlacerSetupSlacks::pin_range PlacerSetupSlacks::pins_with_modified_setup_slack() const { + return vtr::make_range(cluster_pins_with_modified_setup_slack_); +} diff --git a/vpr/src/place/timing/PlacerSetupSlacks.h b/vpr/src/place/timing/PlacerSetupSlacks.h new file mode 100644 index 00000000000..521d83809ca --- /dev/null +++ b/vpr/src/place/timing/PlacerSetupSlacks.h @@ -0,0 +1,128 @@ + +#pragma once + +#include "vtr_vec_id_set.h" +#include "timing_info_fwd.h" +#include "clustered_netlist_utils.h" +#include "place_delay_model.h" +#include "vpr_net_pins_matrix.h" + +/** + * @brief PlacerSetupSlacks returns the RAW setup slacks of clustered netlist connection. + * + * Usage + * ===== + * This class mirrors PlacerCriticalities by both its methods and its members. The only + * difference is that this class deals with RAW setup slacks returned by SetupTimingInfo + * rather than criticalities. See the documentation on PlacerCriticalities for more. + * + * RAW setup slacks are unlike criticalities. Their values are not confined between + * 0 and 1. Their values can be either positive or negative. + * + * This class also provides iterating over the clustered netlist connections/pins that + * have modified setup slacks by the last call to update_setup_slacks(). However, this + * utility is mainly used for incrementally committing the setup slack values into the + * structure `connection_setup_slack` used by many placer routines. + */ +class PlacerSetupSlacks { + public: //Types + typedef vtr::vec_id_set::iterator pin_iterator; + typedef vtr::vec_id_set::iterator net_iterator; + + typedef vtr::Range pin_range; + typedef vtr::Range net_range; + + public: //Lifetime + ///@brief Allocates space for the timing_place_setup_slacks_ data structure. + PlacerSetupSlacks(const ClusteredNetlist& clb_nlist, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info); + + PlacerSetupSlacks(const PlacerSetupSlacks& clb_nlist) = delete; + PlacerSetupSlacks& operator=(const PlacerSetupSlacks& clb_nlist) = delete; + + public: //Accessors + ///@brief Returns the setup slack of the specified connection. + float setup_slack(ClusterNetId net, int ipin) const { return timing_place_setup_slacks_[net][ipin]; } + + /** + * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) + * which were modified by the last call to PlacerSetupSlacks::update_setup_slacks(). + */ + pin_range pins_with_modified_setup_slack() const; + + public: //Modifiers + /** + * @brief Updates setup slacks based on the atom netlist setup slacks provided + * by timing_info_. + * + * @note This function updates the setup slacks in the timing_place_setup_slacks_ + * data structure. + * + * Should consistently call this method after the most recent timing analysis to + * keep the setup slacks stored in this class in sync with the timing analyzer. + * If out of sync, then the setup slacks cannot be incrementally updated during + * the next timing analysis iteration. + * + * If the setup slacks are not updated immediately after each time we cal + * timing_info->update(), then timing_info->pins_with_modified_setup_slack() + * cannot accurately account for all the pins that need to be updated. + * In this case, `recompute_required` would be true, and we update all setup slacks + * from scratch. + */ + void update_setup_slacks(); + + ///@bried Enable the recompute_required flag to enforce from scratch update. + void set_recompute_required() { recompute_required = true; } + + ///@brief Override the setup slack of a particular connection. + void set_setup_slack(ClusterNetId net, int ipin, float slack_val); + + ///@brief Set `update_enabled` to true. + void enable_update() { update_enabled = true; } + + ///@brief Set `update_enabled` to true. + void disable_update() { update_enabled = false; } + + private: //Data + const ClusteredNetlist& clb_nlist_; + const ClusteredPinAtomPinsLookup& pin_lookup_; + std::shared_ptr timing_info_; + + /** + * @brief The matrix that stores raw setup slack values for each connection. + * + * Index range: [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1] + */ + ClbNetPinsMatrix timing_place_setup_slacks_; + + ///@brief Set of pins with raw setup slacks modified by last call to update_setup_slacks() + vtr::vec_id_set cluster_pins_with_modified_setup_slack_; + + /** + * @brief Collect the cluster pins which need to be updated based on the latest timing + * analysis so that incremental updates to setup slacks can be performed. + * + * Note we use the set of pins reported by the *timing_info* as having modified + * setup slacks, rather than those marked as modified by the timing analyzer. + */ + void incr_update_setup_slacks(); + + /** + * @brief Collect all the sink pins in the netlist and prepare them update. + * + * For the incremental version, see PlacerSetupSlacks::incr_update_setup_slacks(). + */ + void recompute_setup_slacks(); + + ///@brief Flag that turns on/off the update_setup_slacks() routine. + bool update_enabled = true; + + /** + * @brief Flag that checks if setup slacks need to be recomputed for all connections. + * + * Used by the method update_setup_slacks(). They incremental update is not possible + * if this method wasn't called updated after the previous timing info update. + */ + bool recompute_required = true; +}; diff --git a/vpr/src/place/timing/PlacerTimingCosts.cpp b/vpr/src/place/timing/PlacerTimingCosts.cpp new file mode 100644 index 00000000000..483111a14e6 --- /dev/null +++ b/vpr/src/place/timing/PlacerTimingCosts.cpp @@ -0,0 +1,126 @@ + +#include "PlacerTimingCosts.h" + +PlacerTimingCosts::PlacerTimingCosts(const ClusteredNetlist& nlist) { + auto nets = nlist.nets(); + + net_start_indices_.resize(nets.size()); + + // Walk through the netlist to determine how many connections there are. + size_t iconn = 0; + for (ClusterNetId net : nets) { + // The placer always skips 'ignored' nets, so they don't affect timing + // costs, so we also skip them here + if (nlist.net_is_ignored(net)) { + net_start_indices_[net] = OPEN; + continue; + } + + // Save the starting index of the current net's connections. + // We use a -1 offset, since sinks indexed from [1..num_net_pins-1] + // (there is no timing cost associated with net drivers) + net_start_indices_[net] = iconn - 1; + + // Reserve space for all this net's connections + iconn += nlist.net_sinks(net).size(); + } + + const size_t num_connections = iconn; + + // Determine how many binary tree levels we need to have a leaf for each connection cost + size_t ilevel = 0; + while (num_nodes_in_level(ilevel) < num_connections) { + ++ilevel; + } + num_levels_ = ilevel + 1; + + size_t num_leaves = num_nodes_in_level(ilevel); + size_t num_nodes_in_previous_level = num_nodes_in_level(ilevel - 1); + + VTR_ASSERT_MSG(num_leaves >= num_connections, "Need at least as many leaves as connections"); + VTR_ASSERT_MSG(num_connections == 0 || num_nodes_in_previous_level < num_connections, + "Level before should have fewer nodes than connections (to ensure using the smallest binary tree)"); + + // We don't need to store all possible leaves if we have fewer connections (i.e. bottom-right of tree is empty) + size_t last_level_unused_nodes = num_nodes_in_level(ilevel) - num_connections; + size_t num_nodes = num_nodes_up_to_level(ilevel) - last_level_unused_nodes; + + // Reserve space for connection costs and intermediate node values + connection_costs_ = std::vector(num_nodes, std::numeric_limits::quiet_NaN()); + + // The net start indices we calculated earlier didn't account for intermediate binary tree nodes + // Shift the start indices after the intermediate nodes + size_t num_intermediate_nodes = num_nodes_up_to_level(ilevel - 1); + for (ClusterNetId net : nets) { + if (nlist.net_is_ignored(net)) continue; + + net_start_indices_[net] = net_start_indices_[net] + num_intermediate_nodes; + } +} + +double PlacerTimingCosts::total_cost_recurr(size_t inode) { + // Prune out-of-tree + if (inode > connection_costs_.size() - 1) { + return 0.; + } + + //Valid pre-calculated intermediate result or valid leaf + if (!std::isnan(connection_costs_[inode])) { + return connection_costs_[inode]; + } + + //Recompute recursively + double node_cost = total_cost_recurr(left_child(inode)) + + total_cost_recurr(right_child(inode)); + + //Save intermediate cost at this node + connection_costs_[inode] = node_cost; + + return node_cost; +} + +double PlacerTimingCosts::total_cost_from_scratch(size_t inode) const { + // Prune out-of-tree + if (inode > connection_costs_.size() - 1) { + return 0.; + } + + //Recompute recursively + double node_cost = total_cost_from_scratch(left_child(inode)) + + total_cost_from_scratch(right_child(inode)); + + return node_cost; +} + +void PlacerTimingCosts::invalidate(const double* invalidated_cost) { + //Check pointer within range of internal storage + VTR_ASSERT_SAFE_MSG( + invalidated_cost >= &connection_costs_[0], + "Connection cost pointer should be after start of internal storage"); + + VTR_ASSERT_SAFE_MSG( + invalidated_cost <= &connection_costs_[connection_costs_.size() - 1], + "Connection cost pointer should be before end of internal storage"); + + size_t icost = invalidated_cost - &connection_costs_[0]; + + VTR_ASSERT_SAFE(icost >= num_nodes_up_to_level(num_levels_ - 2)); + + //Invalidate parent intermediate costs up to root or first + //already-invalidated parent + size_t iparent = parent(icost); + + while (!std::isnan(connection_costs_[iparent])) { + //Invalidate + connection_costs_[iparent] = std::numeric_limits::quiet_NaN(); + + if (iparent == 0) { + break; //At root + } else { + //Next parent + iparent = parent(iparent); + } + } + + VTR_ASSERT_SAFE_MSG(std::isnan(connection_costs_[0]), "Invalidating any connection should have invalidated the root"); +} diff --git a/vpr/src/place/timing/PlacerTimingCosts.h b/vpr/src/place/timing/PlacerTimingCosts.h new file mode 100644 index 00000000000..5e1415581c3 --- /dev/null +++ b/vpr/src/place/timing/PlacerTimingCosts.h @@ -0,0 +1,242 @@ + +#pragma once +#include "vtr_vec_id_set.h" +#include "timing_info_fwd.h" +#include "clustered_netlist_utils.h" +#include "place_delay_model.h" +#include "vpr_net_pins_matrix.h" + +/** + * @brief PlacerTimingCosts mimics a 2D array of connection timing costs running from: + * [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1]. + * + * It can be used similar to: + * + * PlacerTimingCosts connection_timing_costs(cluster_ctx.clb_nlist); //Construct + * + * //... + * + * //Modify a connection cost + * connection_timing_costs[net_id][ipin] = new_cost; + * + * //Potentially other modifications... + * + * //Calculate the updated timing cost, of all connections, + * //incrementally based on modifications + * float total_timing_cost = connection_timing_costs.total_cost(); + * + * However behind the scenes PlacerTimingCosts tracks when connection costs are modified, + * and efficiently re-calculates the total timing cost incrementally based on the connections + * which have had their cost modified. + * + * Implementation + * ============== + * Internally, PlacerTimingCosts stores all connection costs in a flat array in the last part + * of connection_costs_. To mimic 2d-array like access PlacerTimingCosts also uses two proxy + * classes which allow indexing in the net and pin dimensions (NetProxy and ConnectionProxy + * respectively). + * + * The first part of connection_costs_ stores intermediate sums of the connection costs for + * efficient incremental re-calculation. More concretely, connection_costs_ stores a binary + * tree, where leaves correspond to individual connection costs and intermediate nodes the + * partial sums of the connection costs. (The binary tree is stored implicitly in the + * connection_costs_ vector, using Eytzinger's/BFS layout.) By summing the entire binary + * tree we calculate the total timing cost over all connections. + * + * Using a binary tree allows us to efficiently re-calculate the timing costs when only a subset + * of connections are changed. This is done by 'invalidating' intermediate nodes (from leaves up + * to the root) which have ancestors (leaves) with modified connection costs. When the + * total_cost() method is called, it recursively walks the binary tree to re-calculate the cost. + * Only invalidated nodes are traversed, with valid nodes just returning their previously + * calculated (and unchanged) value. + * + * For a circuit with 'K' connections, of which 'k' have changed (typically k << K), this can + * be done in O(k log K) time. + * + * It is important to note that due to limited floating point precision, floating point + * arithmetic has an order dependence (due to round-off). Using a binary tree to total + * the timing connection costs allows us to incrementally update the total timing cost while + * maintaining the *same order of operations* as if it was re-computed from scratch. This + * ensures we *always* get consistent results regardless of what/when connections are changed. + * + * Proxy Classes + * ============= + * NetProxy is returned by PlacerTimingCost's operator[], and stores a pointer to the start of + * internal storage of that net's connection costs. + * + * ConnectionProxy is returned by NetProxy's operator[], and holds a reference to a particular + * element of the internal storage pertaining to a specific connection's cost. ConnectionProxy + * supports assignment, allowing clients to modify the connection cost. It also detects if the + * assigned value differs from the previous value and if so, calls PlacerTimingCosts's + * invalidate() method on that connection cost. + * + * PlacerTimingCosts's invalidate() method marks the cost element's ancestors as invalid (NaN) + * so they will be re-calculated by PlacerTimingCosts' total_cost() method. + */ +class PlacerTimingCosts { + public: + PlacerTimingCosts() = default; + + PlacerTimingCosts(const ClusteredNetlist& nlist); + + /** + * @brief Proxy class representing a connection cost. + * + * Supports modification of connection cost while detecting + * changes and reporting them up to PlacerTimingCosts. + */ + class ConnectionProxy { + public: + ConnectionProxy(PlacerTimingCosts* timing_costs, double& connection_cost) + : timing_costs_(timing_costs) + , connection_cost_(connection_cost) {} + + ///@brief Allow clients to modify the connection cost via assignment. + ConnectionProxy& operator=(double new_cost) { + if (new_cost != connection_cost_) { + //If connection cost changed, update it, and mark it + //as invalidated + connection_cost_ = new_cost; + timing_costs_->invalidate(&connection_cost_); + } + return *this; + } + + /** + * @brief Support getting the current connection cost as a double. + * + * Useful for client code operating on the cost values (e.g. difference between costs). + */ + operator double() const { + return connection_cost_; + } + + private: + PlacerTimingCosts* timing_costs_; + double& connection_cost_; + }; + + /** + * @brief Proxy class representing the connection costs of a net. + * + * Supports indexing by pin index to retrieve the ConnectionProxy for that pin/connection. + */ + class NetProxy { + public: + NetProxy(PlacerTimingCosts* timing_costs, double* net_sink_costs) + : timing_costs_(timing_costs) + , net_sink_costs_(net_sink_costs) {} + + ///@brief Indexes into the specific net pin/connection. + ConnectionProxy operator[](size_t ipin) { + return ConnectionProxy(timing_costs_, net_sink_costs_[ipin]); + } + + const ConnectionProxy operator[](size_t ipin) const { + return ConnectionProxy(timing_costs_, net_sink_costs_[ipin]); + } + + private: + PlacerTimingCosts* timing_costs_; + double* net_sink_costs_; + }; + + ///@brief Indexes into the specific net. + NetProxy operator[](ClusterNetId net_id) { + VTR_ASSERT_SAFE(net_start_indices_[net_id] >= 0); + + double* net_connection_costs = &connection_costs_[net_start_indices_[net_id]]; + return NetProxy(this, net_connection_costs); + } + + NetProxy operator[](ClusterNetId net_id) const { + VTR_ASSERT_SAFE(net_start_indices_[net_id] >= 0); + + const double* net_connection_costs = &connection_costs_[net_start_indices_[net_id]]; + return NetProxy(const_cast(this), const_cast(net_connection_costs)); + } + + void clear() { + connection_costs_.clear(); + net_start_indices_.clear(); + } + + void swap(PlacerTimingCosts& other) { + std::swap(connection_costs_, other.connection_costs_); + std::swap(net_start_indices_, other.net_start_indices_); + std::swap(num_levels_, other.num_levels_); + } + + /** + * @brief Calculates the total cost of all connections efficiently + * in the face of modified connection costs. + */ + double total_cost() { + float cost = total_cost_recurr(0); //Root + + VTR_ASSERT_DEBUG_MSG(cost == total_cost_from_scratch(0), + "Expected incremental and from-scratch costs to be consistent"); + + return cost; + } + + private: + ///@brief Recursively calculate and update the timing cost rooted at inode. + double total_cost_recurr(size_t inode); + + double total_cost_from_scratch(size_t inode) const; + + ///@brief Friend-ed so it can call invalidate(). + friend ConnectionProxy; + + void invalidate(const double* invalidated_cost); + + static size_t left_child(size_t i) { + return 2 * i + 1; + } + + static size_t right_child(size_t i) { + return 2 * i + 2; + } + + static size_t parent(size_t i) { + return (i - 1) / 2; + } + + /** + * @brief Returns the number of nodes in ilevel'th level. + * + * If ilevel is negative, return 0, since the root shouldn't + * be counted as a leaf node candidate. + */ + static size_t num_nodes_in_level(int ilevel) { + return ilevel < 0 ? 0 : (2 << (ilevel)); + } + + ///@brief Returns the total number of nodes in levels [0..ilevel] (inclusive). + static size_t num_nodes_up_to_level(int ilevel) { + return (2 << (ilevel + 1)) - 1; + } + + private: + /** + * @brief Vector storing the implicit binary tree of connection costs. + * + * The actual connections are stored at the end of the vector + * (last level of the binary tree). The earlier portions of + * the tree are the intermediate nodes. + * + * The methods left_child()/right_child()/parent() can be used + * to traverse the tree by indices into this vector. + */ + std::vector connection_costs_; + + /** + * @brief Vector storing the indices of the first connection + * for each net in the netlist, used for indexing by net. + */ + vtr::vector net_start_indices_; + + ///@brief Number of levels in the binary tree. + size_t num_levels_ = 0; +}; diff --git a/vpr/src/place/place_timing_update.cpp b/vpr/src/place/timing/place_timing_update.cpp similarity index 98% rename from vpr/src/place/place_timing_update.cpp rename to vpr/src/place/timing/place_timing_update.cpp index c9c53b88f90..e038af00860 100644 --- a/vpr/src/place/place_timing_update.cpp +++ b/vpr/src/place/timing/place_timing_update.cpp @@ -3,10 +3,14 @@ * @brief Defines the routines declared in place_timing_update.h. */ -#include "vtr_time.h" - #include "place_timing_update.h" + +#include "NetPinTimingInvalidator.h" +#include "PlacerCriticalities.h" +#include "PlacerSetupSlacks.h" #include "placer_state.h" +#include "place_util.h" +#include "vtr_time.h" /* Routines local to place_timing_update.cpp */ static double comp_td_connection_cost(const PlaceDelayModel* delay_model, @@ -94,8 +98,7 @@ void perform_full_timing_update(const PlaceCritParams& crit_params, timing_info, criticalities, setup_slacks, - pin_timing_invalidator, - placer_state); + pin_timing_invalidator); /* Update the timing cost with new connection criticalities. */ update_timing_cost(delay_model, @@ -136,13 +139,12 @@ void update_timing_classes(const PlaceCritParams& crit_params, SetupTimingInfo* timing_info, PlacerCriticalities* criticalities, PlacerSetupSlacks* setup_slacks, - NetPinTimingInvalidator* pin_timing_invalidator, - PlacerState& placer_state) { + NetPinTimingInvalidator* pin_timing_invalidator) { /* Run STA to update slacks and adjusted/relaxed criticalities. */ timing_info->update(); /* Update the placer's criticalities (e.g. sharpen with crit_exponent). */ - criticalities->update_criticalities(crit_params, placer_state); + criticalities->update_criticalities(crit_params); /* Update the placer's raw setup slacks. */ setup_slacks->update_setup_slacks(); diff --git a/vpr/src/place/place_timing_update.h b/vpr/src/place/timing/place_timing_update.h similarity index 93% rename from vpr/src/place/place_timing_update.h rename to vpr/src/place/timing/place_timing_update.h index 7944c4a7552..8e7a0dc1f46 100644 --- a/vpr/src/place/place_timing_update.h +++ b/vpr/src/place/timing/place_timing_update.h @@ -4,10 +4,15 @@ */ #pragma once -#include "timing_place.h" -#include "place_util.h" -#include "NetPinTimingInvalidator.h" +class PlacerState; +class PlaceCritParams; +class PlacerCriticalities; +class PlacerSetupSlacks; +class NetPinTimingInvalidator; +class PlaceDelayModel; +class SetupTimingInfo; +struct t_placer_costs; ///@brief Initialize the timing information and structures in the placer. void initialize_timing_info(const PlaceCritParams& crit_params, @@ -34,8 +39,7 @@ void update_timing_classes(const PlaceCritParams& crit_params, SetupTimingInfo* timing_info, PlacerCriticalities* criticalities, PlacerSetupSlacks* setup_slacks, - NetPinTimingInvalidator* pin_timing_invalidator, - PlacerState& placer_state); + NetPinTimingInvalidator* pin_timing_invalidator); ///@brief Updates the timing driven (td) costs. void update_timing_cost(const PlaceDelayModel* delay_model, diff --git a/vpr/src/place/timing_place.cpp b/vpr/src/place/timing_place.cpp deleted file mode 100644 index badd9d1fb61..00000000000 --- a/vpr/src/place/timing_place.cpp +++ /dev/null @@ -1,270 +0,0 @@ -/** - * @file timing_place.cpp - * @brief Stores the method definitions of classes defined in timing_place.h. - */ - -#include - -#include "vtr_util.h" - -#include "vpr_types.h" -#include "vpr_utils.h" -#include "net_delay.h" -#include "timing_place.h" -#include "placer_state.h" - -#include "timing_info.h" - -///@brief Allocates space for the timing_place_crit_ data structure. -PlacerCriticalities::PlacerCriticalities(const ClusteredNetlist& clb_nlist, - const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - std::shared_ptr timing_info) - : clb_nlist_(clb_nlist) - , pin_lookup_(netlist_pin_lookup) - , timing_info_(std::move(timing_info)) - , timing_place_crit_(make_net_pins_matrix(clb_nlist_, std::numeric_limits::quiet_NaN())) { -} - -/** - * @brief Updated the criticalities in the timing_place_crit_ data structure. - * - * If the criticalities are not updated immediately after each time we call - * timing_info->update(), then timing_info->pins_with_modified_setup_criticality() - * cannot accurately account for all the pins that need to be updated. In this case, - * `recompute_required` would be true, and we update all criticalities from scratch. - * - * If the criticality exponent has changed, we also need to update from scratch. - */ -void PlacerCriticalities::update_criticalities(const PlaceCritParams& crit_params, - PlacerState& placer_state) { - /* If update is not enabled, exit the routine. */ - if (!update_enabled) { - /* re-computation is required on the next iteration */ - recompute_required = true; - return; - } - - /* Determine what pins need updating */ - if (!recompute_required && crit_params.crit_exponent == last_crit_exponent_) { - incr_update_criticalities(); - } else { - recompute_criticalities(); - - /* Record new criticality exponent */ - last_crit_exponent_ = crit_params.crit_exponent; - } - - auto& place_move_ctx = placer_state.mutable_move(); - - /* Performs a 1-to-1 mapping from criticality to timing_place_crit_. - * For every pin on every net (or, equivalently, for every tedge ending - * in that pin), timing_place_crit_ = criticality^(criticality exponent) */ - - /* Update the affected pins */ - for (ClusterPinId clb_pin : cluster_pins_with_modified_criticality_) { - ClusterNetId clb_net = clb_nlist_.pin_net(clb_pin); - int pin_index_in_net = clb_nlist_.pin_net_index(clb_pin); - // Routing for placement is not flat (at least for the time being) - float clb_pin_crit = calculate_clb_net_pin_criticality(*timing_info_, pin_lookup_, ParentPinId(size_t(clb_pin)), /*is_flat=*/false); - - float new_crit = pow(clb_pin_crit, crit_params.crit_exponent); - /* - * Update the highly critical pins container - * - * If the old criticality < limit and the new criticality > limit --> add this pin to the highly critical pins - * If the old criticality > limit and the new criticality < limit --> remove this pin from the highly critical pins - */ - if (!first_time_update_criticality) { - if (new_crit > crit_params.crit_limit && timing_place_crit_[clb_net][pin_index_in_net] < crit_params.crit_limit) { - place_move_ctx.highly_crit_pins.emplace_back(clb_net, pin_index_in_net); - } else if (new_crit < crit_params.crit_limit && timing_place_crit_[clb_net][pin_index_in_net] > crit_params.crit_limit) { - place_move_ctx.highly_crit_pins.erase(std::remove(place_move_ctx.highly_crit_pins.begin(), place_move_ctx.highly_crit_pins.end(), std::make_pair(clb_net, pin_index_in_net)), - place_move_ctx.highly_crit_pins.end()); - } - } else { - if (new_crit > crit_params.crit_limit) { - place_move_ctx.highly_crit_pins.emplace_back(clb_net, pin_index_in_net); - } - } - - /* The placer likes a great deal of contrast between criticalities. - * Since path criticality varies much more than timing, we "sharpen" timing - * criticality by taking it to some power, crit_exponent (between 1 and 8 by default). */ - timing_place_crit_[clb_net][pin_index_in_net] = new_crit; - } - - /* Criticalities updated. In sync with timing info. */ - /* Can be incrementally updated on the next iteration */ - recompute_required = false; - - first_time_update_criticality = false; -} - -void PlacerCriticalities::set_recompute_required() { - recompute_required = true; -} - -/** - * @brief Collect the cluster pins which need to be updated based on the latest timing - * analysis so that incremental updates to criticalities can be performed. - * - * Note we use the set of pins reported by the *timing_info* as having modified - * criticality, rather than those marked as modified by the timing analyzer. - * - * Since timing_info uses shifted/relaxed criticality (which depends on max required - * time and worst case slacks), additional nodes may be modified when updating the - * atom pin criticalities. - */ - -void PlacerCriticalities::incr_update_criticalities() { - cluster_pins_with_modified_criticality_.clear(); - - for (AtomPinId atom_pin : timing_info_->pins_with_modified_setup_criticality()) { - ClusterPinId clb_pin = pin_lookup_.connected_clb_pin(atom_pin); - - //Some atom pins correspond to connections which are completely - //contained within a cluster, and hence have no corresponding - //clustered pin. - if (!clb_pin) continue; - - cluster_pins_with_modified_criticality_.insert(clb_pin); - } -} - -/** - * @brief Collect all the sink pins in the netlist and prepare them update. - * - * For the incremental version, see PlacerCriticalities::incr_update_criticalities(). - */ -void PlacerCriticalities::recompute_criticalities() { - cluster_pins_with_modified_criticality_.clear(); - - /* Non-incremental: all sink pins need updating */ - for (ClusterNetId net_id : clb_nlist_.nets()) { - for (ClusterPinId pin_id : clb_nlist_.net_sinks(net_id)) { - cluster_pins_with_modified_criticality_.insert(pin_id); - } - } -} - -///@brief Override the criticality of a particular connection. -void PlacerCriticalities::set_criticality(ClusterNetId net_id, int ipin, float crit_val) { - VTR_ASSERT_SAFE_MSG(ipin > 0, "The pin should not be a driver pin (ipin != 0)"); - VTR_ASSERT_SAFE_MSG(ipin < int(clb_nlist_.net_pins(net_id).size()), "The pin index in net should be smaller than fanout"); - - timing_place_crit_[net_id][ipin] = crit_val; -} - -/** - * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) which - * were modified by the last call to PlacerCriticalities::update_criticalities(). - */ -PlacerCriticalities::pin_range PlacerCriticalities::pins_with_modified_criticality() const { - return vtr::make_range(cluster_pins_with_modified_criticality_); -} - -/**************************************/ - -///@brief Allocates space for the timing_place_setup_slacks_ data structure. -PlacerSetupSlacks::PlacerSetupSlacks(const ClusteredNetlist& clb_nlist, - const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - std::shared_ptr timing_info) - : clb_nlist_(clb_nlist) - , pin_lookup_(netlist_pin_lookup) - , timing_info_(std::move(timing_info)) - , timing_place_setup_slacks_(make_net_pins_matrix(clb_nlist_, std::numeric_limits::quiet_NaN())) { -} - -/** - * @brief Updated the setup slacks in the timing_place_setup_slacks_ data structure. - * - * If the setup slacks are not updated immediately after each time we call - * timing_info->update(), then timing_info->pins_with_modified_setup_slack() - * cannot accurately account for all the pins that need to be updated. - * - * In this case, `recompute_required` would be true, and we update all setup slacks - * from scratch. - */ -void PlacerSetupSlacks::update_setup_slacks() { - /* If update is not enabled, exit the routine. */ - if (!update_enabled) { - /* re-computation is required on the next iteration */ - recompute_required = true; - return; - } - - /* Determine what pins need updating */ - if (!recompute_required) { - incr_update_setup_slacks(); - } else { - recompute_setup_slacks(); - } - - /* Update the affected pins */ - for (ClusterPinId clb_pin : cluster_pins_with_modified_setup_slack_) { - ClusterNetId clb_net = clb_nlist_.pin_net(clb_pin); - int pin_index_in_net = clb_nlist_.pin_net_index(clb_pin); - - float clb_pin_setup_slack = calculate_clb_net_pin_setup_slack(*timing_info_, pin_lookup_, clb_pin); - - timing_place_setup_slacks_[clb_net][pin_index_in_net] = clb_pin_setup_slack; - } - - /* Setup slacks updated. In sync with timing info. */ - /* Can be incrementally updated on the next iteration. */ - recompute_required = false; -} - -/** - * @brief Collect the cluster pins which need to be updated based on the latest timing - * analysis so that incremental updates to setup slacks can be performed. - * - * Note we use the set of pins reported by the *timing_info* as having modified - * setup slacks, rather than those marked as modified by the timing analyzer. - */ -void PlacerSetupSlacks::incr_update_setup_slacks() { - cluster_pins_with_modified_setup_slack_.clear(); - - for (AtomPinId atom_pin : timing_info_->pins_with_modified_setup_slack()) { - ClusterPinId clb_pin = pin_lookup_.connected_clb_pin(atom_pin); - - //Some atom pins correspond to connections which are completely - //contained within a cluster, and hence have no corresponding - //clustered pin. - if (!clb_pin) continue; - - cluster_pins_with_modified_setup_slack_.insert(clb_pin); - } -} - -/** - * @brief Collect all the sink pins in the netlist and prepare them update. - * - * For the incremental version, see PlacerSetupSlacks::incr_update_setup_slacks(). - */ -void PlacerSetupSlacks::recompute_setup_slacks() { - cluster_pins_with_modified_setup_slack_.clear(); - - /* Non-incremental: all sink pins need updating */ - for (ClusterNetId net_id : clb_nlist_.nets()) { - for (ClusterPinId pin_id : clb_nlist_.net_sinks(net_id)) { - cluster_pins_with_modified_setup_slack_.insert(pin_id); - } - } -} - -///@brief Override the setup slack of a particular connection. -void PlacerSetupSlacks::set_setup_slack(ClusterNetId net_id, int ipin, float slack_val) { - VTR_ASSERT_SAFE_MSG(ipin > 0, "The pin should not be a driver pin (ipin != 0)"); - VTR_ASSERT_SAFE_MSG(ipin < int(clb_nlist_.net_pins(net_id).size()), "The pin index in net should be smaller than fanout"); - - timing_place_setup_slacks_[net_id][ipin] = slack_val; -} - -/** - * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) - * which were modified by the last call to PlacerSetupSlacks::update_setup_slacks(). - */ -PlacerSetupSlacks::pin_range PlacerSetupSlacks::pins_with_modified_setup_slack() const { - return vtr::make_range(cluster_pins_with_modified_setup_slack_); -} diff --git a/vpr/src/place/timing_place.h b/vpr/src/place/timing_place.h deleted file mode 100644 index 71e144334ad..00000000000 --- a/vpr/src/place/timing_place.h +++ /dev/null @@ -1,647 +0,0 @@ -/** - * @file timing_place.h - * @brief Interface used by the VPR placer to query information - * from the Tatum timing analyzer. - * - * @class PlacerSetupSlacks - * Queries connection **RAW** setup slacks, which can - * range from negative to positive values. Also maps - * atom pin setup slacks to clb pin setup slacks. - * @class PlacerCriticalities - * Query connection criticalities, which are calculuated - * based on the raw setup slacks and ranges from 0 to 1. - * Also maps atom pin crit. to clb pin crit. - * @class PlacerTimingCosts - * Hierarchical structure used by update_td_costs() to - * maintain the order of addition operation of float values - * (to avoid round-offs) while doing incremental updates. - * - * Calculating criticalities: - * All the raw setup slack values across a single clock domain are gathered - * and rated from the best to the worst in terms of criticalities. In order - * to calculate criticalities, all the slack values need to be non-negative. - * Hence, if the worst slack is negative, all the slack values are shifted - * by the value of the worst slack so that the value is at least 0. If the - * worst slack is positive, then no shift happens. - * - * The best (shifted) slack (the most positive one) will have a criticality of 0. - * The worst (shifted) slack value will have a criticality of 1. - * - * Criticalities are used to calculated timing costs for each connection. - * The formula is cost = delay * criticality. - * - * For a more detailed description on how criticalities are calculated, see - * calc_relaxed_criticality() in `timing_util.cpp`. - */ - -#pragma once -#include "vtr_vec_id_set.h" -#include "timing_info_fwd.h" -#include "clustered_netlist_utils.h" -#include "place_delay_model.h" -#include "vpr_net_pins_matrix.h" - -/** - * @brief Saves the placement criticality parameters - * - * crit_exponent: The criticality exponent used to sharpen the criticalities - * crit_limit: The limit to consider a pin as timing critical - */ -struct PlaceCritParams { - float crit_exponent; - float crit_limit; -}; - -/** - * @brief PlacerCriticalities returns the clustered netlist connection criticalities - * used by the placer ('sharpened' by a criticality exponent). - * - * Usage - * ===== - * This class also serves to map atom netlist level criticalites (i.e. on AtomPinIds) - * to the clustered netlist (i.e. ClusterPinIds) used during placement. - * - * Criticalities are updated by update_criticalities(), given that `update_enabled` is - * set to true. It will update criticalities based on the atom netlist connection - * criticalities provided by the passed in SetupTimingInfo. - * - * This process can be done incrementally, based on the modified connections/AtomPinIds - * returned by SetupTimingInfo. However, the set returned only reflects the connections - * changed by the last call to the timing info update. - * - * Therefore, if SetupTimingInfo is updated twice in succession without criticalities - * getting updated (update_enabled = false), the returned set cannot account for all - * the connections that have been modified. In this case, we flag `recompute_required` - * as false, and we recompute the criticalities for every connection to ensure that - * they are all up to date. Hence, each time update_setup_slacks_and_criticalities() - * is called, we assign `recompute_required` the opposite value of `update_enabled`. - * - * This class also maps/transforms the modified atom connections/pins returned by the - * timing info into modified clustered netlist connections/pins after calling - * update_criticalities(). The interface then enables users to iterate over this range - * via pins_with_modified_criticalities(). This is useful for incrementally re-calculating - * the timing costs. - * - * The criticalities of individual connections can then be queried by calling the - * criticality() member function. - * - * Implementation - * ============== - * To support incremental re-calculation, the class saves the last criticality exponent - * passed to PlacerCriticalities::update_criticalites(). If the next update uses the same - * exponent, criticalities can be incrementally updated. Otherwise, they must be re-calculated - * from scratch, since a change in exponent changes *all* criticalities. - */ -class PlacerCriticalities { - public: //Types - typedef vtr::vec_id_set::iterator pin_iterator; - typedef vtr::vec_id_set::iterator net_iterator; - - typedef vtr::Range pin_range; - typedef vtr::Range net_range; - - public: //Lifetime - PlacerCriticalities(const ClusteredNetlist& clb_nlist, - const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - std::shared_ptr timing_info); - PlacerCriticalities(const PlacerCriticalities&) = delete; - PlacerCriticalities& operator=(const PlacerCriticalities&) = delete; - - public: //Accessors - ///@brief Returns the criticality of the specified connection. - float criticality(ClusterNetId net, int ipin) const { return timing_place_crit_[net][ipin]; } - - /** - * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) which - * were modified by the last call to PlacerCriticalities::update_criticalities(). - */ - pin_range pins_with_modified_criticality() const; - - public: //Modifiers - /** - * @brief Updates criticalities based on the atom netlist criticalitites - * provided by timing_info and the provided criticality_exponent. - * - * Should consistently call this method after the most recent timing analysis to - * keep the criticalities stored in this class in sync with the timing analyzer. - * If out of sync, then the criticalities cannot be incrementally updated on - * during the next timing analysis iteration. - */ - void update_criticalities(const PlaceCritParams& crit_params, - PlacerState& placer_state); - - ///@bried Enable the recompute_required flag to enforce from scratch update. - void set_recompute_required(); - - ///@brief From scratch update. See timing_place.cpp for more. - void recompute_criticalities(); - - ///@brief Override the criticality of a particular connection. - void set_criticality(ClusterNetId net, int ipin, float crit_val); - - ///@brief Set `update_enabled` to true. - void enable_update() { update_enabled = true; } - - ///@brief Set `update_enabled` to true. - void disable_update() { update_enabled = false; } - - private: //Data - ///@brief The clb netlist in the placement context. - const ClusteredNetlist& clb_nlist_; - - ///@brief The lookup table that maps atom pins to clb pins. - const ClusteredPinAtomPinsLookup& pin_lookup_; - - ///@brief A pointer to the setup timing analyzer - std::shared_ptr timing_info_; - - /** - * @brief The matrix that stores criticality value for each connection. - * - * Index range: [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1] - */ - ClbNetPinsMatrix timing_place_crit_; - - /** - * The criticality exponent when update_criticalites() was last called - * (used to detect if incremental update can be used). - */ - float last_crit_exponent_ = std::numeric_limits::quiet_NaN(); - - ///@brief Set of pins with criticaltites modified by last call to update_criticalities(). - vtr::vec_id_set cluster_pins_with_modified_criticality_; - - ///@brief Incremental update. See timing_place.cpp for more. - void incr_update_criticalities(); - - ///@brief Flag that turns on/off the update_criticalities() routine. - bool update_enabled = true; - - /** - * @brief Flag that checks if criticalities need to be recomputed for all connections. - * - * Used by the method update_criticalities(). They incremental update is not possible - * if this method wasn't called updated after the previous timing info update. - */ - bool recompute_required = true; - - /** - * @brief if this is first time to call update_criticality - * - * This can be used for incremental criticality update and also incrementally update the highly critical pins - */ - bool first_time_update_criticality = true; -}; - -/** - * @brief PlacerSetupSlacks returns the RAW setup slacks of clustered netlist connection. - * - * Usage - * ===== - * This class mirrors PlacerCriticalities by both its methods and its members. The only - * difference is that this class deals with RAW setup slacks returned by SetupTimingInfo - * rather than criticalities. See the documentation on PlacerCriticalities for more. - * - * RAW setup slacks are unlike criticalities. Their values are not confined between - * 0 and 1. Their values can be either positive or negative. - * - * This class also provides iterating over the clustered netlist connections/pins that - * have modified setup slacks by the last call to update_setup_slacks(). However, this - * utility is mainly used for incrementally committing the setup slack values into the - * structure `connection_setup_slack` used by many placer routines. - */ -class PlacerSetupSlacks { - public: //Types - typedef vtr::vec_id_set::iterator pin_iterator; - typedef vtr::vec_id_set::iterator net_iterator; - - typedef vtr::Range pin_range; - typedef vtr::Range net_range; - - public: //Lifetime - PlacerSetupSlacks(const ClusteredNetlist& clb_nlist, - const ClusteredPinAtomPinsLookup& netlist_pin_lookup, - std::shared_ptr timing_info); - PlacerSetupSlacks(const PlacerSetupSlacks& clb_nlist) = delete; - PlacerSetupSlacks& operator=(const PlacerSetupSlacks& clb_nlist) = delete; - - public: //Accessors - ///@brief Returns the setup slack of the specified connection. - float setup_slack(ClusterNetId net, int ipin) const { return timing_place_setup_slacks_[net][ipin]; } - - /** - * @brief Returns the range of clustered netlist pins (i.e. ClusterPinIds) - * which were modified by the last call to PlacerSetupSlacks::update_setup_slacks(). - */ - pin_range pins_with_modified_setup_slack() const; - - public: //Modifiers - /** - * @brief Updates setup slacks based on the atom netlist setup slacks provided - * by timing_info_. - * - * Should consistently call this method after the most recent timing analysis to - * keep the setup slacks stored in this class in sync with the timing analyzer. - * If out of sync, then the setup slacks cannot be incrementally updated on - * during the next timing analysis iteration. - */ - void update_setup_slacks(); - - ///@bried Enable the recompute_required flag to enforce from scratch update. - void set_recompute_required() { recompute_required = true; } - - ///@brief Override the setup slack of a particular connection. - void set_setup_slack(ClusterNetId net, int ipin, float slack_val); - - ///@brief Set `update_enabled` to true. - void enable_update() { update_enabled = true; } - - ///@brief Set `update_enabled` to true. - void disable_update() { update_enabled = false; } - - private: //Data - const ClusteredNetlist& clb_nlist_; - const ClusteredPinAtomPinsLookup& pin_lookup_; - std::shared_ptr timing_info_; - - /** - * @brief The matrix that stores raw setup slack values for each connection. - * - * Index range: [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1] - */ - ClbNetPinsMatrix timing_place_setup_slacks_; - - ///@brief Set of pins with raw setup slacks modified by last call to update_setup_slacks() - vtr::vec_id_set cluster_pins_with_modified_setup_slack_; - - ///@brief Incremental update. See timing_place.cpp for more. - void incr_update_setup_slacks(); - - ///@brief Incremental update. See timing_place.cpp for more. - void recompute_setup_slacks(); - - ///@brief Flag that turns on/off the update_setup_slacks() routine. - bool update_enabled = true; - - /** - * @brief Flag that checks if setup slacks need to be recomputed for all connections. - * - * Used by the method update_setup_slacks(). They incremental update is not possible - * if this method wasn't called updated after the previous timing info update. - */ - bool recompute_required = true; -}; - -/** - * @brief PlacerTimingCosts mimics a 2D array of connection timing costs running from: - * [0..cluster_ctx.clb_nlist.nets().size()-1][1..num_pins-1]. - * - * It can be used similar to: - * - * PlacerTimingCosts connection_timing_costs(cluster_ctx.clb_nlist); //Construct - * - * //... - * - * //Modify a connection cost - * connection_timing_costs[net_id][ipin] = new_cost; - * - * //Potentially other modifications... - * - * //Calculate the updated timing cost, of all connections, - * //incrementally based on modifications - * float total_timing_cost = connection_timing_costs.total_cost(); - * - * However behind the scenes PlacerTimingCosts tracks when connection costs are modified, - * and efficiently re-calculates the total timing cost incrementally based on the connections - * which have had their cost modified. - * - * Implementation - * ============== - * Internally, PlacerTimingCosts stores all connection costs in a flat array in the last part - * of connection_costs_. To mimic 2d-array like access PlacerTimingCosts also uses two proxy - * classes which allow indexing in the net and pin dimensions (NetProxy and ConnectionProxy - * respectively). - * - * The first part of connection_costs_ stores intermediate sums of the connection costs for - * efficient incremental re-calculation. More concretely, connection_costs_ stores a binary - * tree, where leaves correspond to individual connection costs and intermediate nodes the - * partial sums of the connection costs. (The binary tree is stored implicitly in the - * connection_costs_ vector, using Eytzinger's/BFS layout.) By summing the entire binary - * tree we calculate the total timing cost over all connections. - * - * Using a binary tree allows us to efficiently re-calculate the timing costs when only a subset - * of connections are changed. This is done by 'invalidating' intermediate nodes (from leaves up - * to the root) which have ancestors (leaves) with modified connection costs. When the - * total_cost() method is called, it recursively walks the binary tree to re-calculate the cost. - * Only invalidated nodes are traversed, with valid nodes just returning their previously - * calculated (and unchanged) value. - * - * For a circuit with 'K' connections, of which 'k' have changed (typically k << K), this can - * be done in O(k log K) time. - * - * It is important to note that due to limited floating point precision, floating point - * arithmetic has an order dependence (due to round-off). Using a binary tree to total - * the timing connection costs allows us to incrementally update the total timing cost while - * maintianing the *same order of operations* as if it was re-computed from scratch. This - * ensures we *always* get consistent results regardless of what/when connections are changed. - * - * Proxy Classes - * ============= - * NetProxy is returned by PlacerTimingCost's operator[], and stores a pointer to the start of - * internal storage of that net's connection costs. - * - * ConnectionProxy is returned by NetProxy's operator[], and holds a reference to a particular - * element of the internal storage pertaining to a specific connection's cost. ConnectionProxy - * supports assignment, allowing clients to modify the connection cost. It also detects if the - * assigned value differs from the previous value and if so, calls PlacerTimingCosts's - * invalidate() method on that connection cost. - * - * PlacerTimingCosts's invalidate() method marks the cost element's ancestors as invalid (NaN) - * so they will be re-calculated by PlacerTimingCosts' total_cost() method. - */ -class PlacerTimingCosts { - public: - PlacerTimingCosts() = default; - - PlacerTimingCosts(const ClusteredNetlist& nlist) { - auto nets = nlist.nets(); - - net_start_indicies_.resize(nets.size()); - - //Walk through the netlist to determine how many connections there are. - size_t iconn = 0; - for (ClusterNetId net : nets) { - //The placer always skips 'ignored' nets, so they don't affect timing - //costs, so we also skip them here - if (nlist.net_is_ignored(net)) { - net_start_indicies_[net] = OPEN; - continue; - } - - //Save the startind index of the current net's connections. - // We use a -1 offset, since sinks indexed from [1..num_net_pins-1] - // (there is no timing cost associated with net drivers) - net_start_indicies_[net] = iconn - 1; - - //Reserve space for all this net's connections - iconn += nlist.net_sinks(net).size(); - } - - size_t num_connections = iconn; - - //Determine how many binary tree levels we need to have a leaf - //for each connection cost - size_t ilevel = 0; - while (num_nodes_in_level(ilevel) < num_connections) { - ++ilevel; - } - num_levels_ = ilevel + 1; - - size_t num_leaves = num_nodes_in_level(ilevel); - size_t num_level_before_leaves = num_nodes_in_level(ilevel - 1); - - VTR_ASSERT_MSG(num_leaves >= num_connections, "Need at least as many leaves as connections"); - VTR_ASSERT_MSG( - num_connections == 0 || num_level_before_leaves < num_connections, - "Level before should have fewer nodes than connections (to ensure using the smallest binary tree)"); - - //We don't need to store all possible leaves if we have fewer connections - //(i.e. bottom-right of tree is empty) - size_t last_level_unused_nodes = num_nodes_in_level(ilevel) - num_connections; - size_t num_nodes = num_nodes_up_to_level(ilevel) - last_level_unused_nodes; - - //Reserve space for connection costs and intermediate node values - connection_costs_ = std::vector(num_nodes, std::numeric_limits::quiet_NaN()); - - //The net start indicies we calculated earlier didn't account for intermediate binary tree nodes - //Shift the start indicies after the intermediate nodes - size_t num_intermediate_nodes = num_nodes_up_to_level(ilevel - 1); - for (ClusterNetId net : nets) { - if (nlist.net_is_ignored(net)) continue; - - net_start_indicies_[net] = net_start_indicies_[net] + num_intermediate_nodes; - } - } - - /** - * @brief Proxy class representing a connection cost. - * - * Supports modification of connection cost while detecting - * changes and reporting them up to PlacerTimingCosts. - */ - class ConnectionProxy { - public: - ConnectionProxy(PlacerTimingCosts* timing_costs, double& connection_cost) - : timing_costs_(timing_costs) - , connection_cost_(connection_cost) {} - - ///@brief Allow clients to modify the connection cost via assignment. - ConnectionProxy& operator=(double new_cost) { - if (new_cost != connection_cost_) { - //If connection cost changed, update it, and mark it - //as invalidated - connection_cost_ = new_cost; - timing_costs_->invalidate(&connection_cost_); - } - return *this; - } - - /** - * @brief Support getting the current connection cost as a double. - * - * Useful for client code operating on the cost values (e.g. difference between costs). - */ - operator double() const { - return connection_cost_; - } - - private: - PlacerTimingCosts* timing_costs_; - double& connection_cost_; - }; - - /** - * @brief Proxy class representing the connection costs of a net. - * - * Supports indexing by pin index to retrieve the ConnectionProxy for that pin/connection. - */ - class NetProxy { - public: - NetProxy(PlacerTimingCosts* timing_costs, double* net_sink_costs) - : timing_costs_(timing_costs) - , net_sink_costs_(net_sink_costs) {} - - ///@brief Indexes into the specific net pin/connection. - ConnectionProxy operator[](size_t ipin) { - return ConnectionProxy(timing_costs_, net_sink_costs_[ipin]); - } - - const ConnectionProxy operator[](size_t ipin) const { - return ConnectionProxy(timing_costs_, net_sink_costs_[ipin]); - } - - private: - PlacerTimingCosts* timing_costs_; - double* net_sink_costs_; - }; - - ///@brief Indexes into the specific net. - NetProxy operator[](ClusterNetId net_id) { - VTR_ASSERT_SAFE(net_start_indicies_[net_id] >= 0); - - double* net_connection_costs = &connection_costs_[net_start_indicies_[net_id]]; - return NetProxy(this, net_connection_costs); - } - - NetProxy operator[](ClusterNetId net_id) const { - VTR_ASSERT_SAFE(net_start_indicies_[net_id] >= 0); - - const double* net_connection_costs = &connection_costs_[net_start_indicies_[net_id]]; - return NetProxy(const_cast(this), const_cast(net_connection_costs)); - } - - void clear() { - connection_costs_.clear(); - net_start_indicies_.clear(); - } - - void swap(PlacerTimingCosts& other) { - std::swap(connection_costs_, other.connection_costs_); - std::swap(net_start_indicies_, other.net_start_indicies_); - std::swap(num_levels_, other.num_levels_); - } - - /** - * @brief Calculates the total cost of all connections efficiently - * in the face of modified connection costs. - */ - double total_cost() { - float cost = total_cost_recurr(0); //Root - - VTR_ASSERT_DEBUG_MSG(cost == total_cost_from_scratch(0), - "Expected incremental and from-scratch costs to be consistent"); - - return cost; - } - - private: - ///@brief Recursively calculate and update the timing cost rooted at inode. - double total_cost_recurr(size_t inode) { - //Prune out-of-tree - if (inode > connection_costs_.size() - 1) { - return 0.; - } - - //Valid pre-calculated intermediate result or valid leaf - if (!std::isnan(connection_costs_[inode])) { - return connection_costs_[inode]; - } - - //Recompute recursively - double node_cost = total_cost_recurr(left_child(inode)) - + total_cost_recurr(right_child(inode)); - - //Save intermedate cost at this node - connection_costs_[inode] = node_cost; - - return node_cost; - } - - double total_cost_from_scratch(size_t inode) const { - //Prune out-of-tree - if (inode > connection_costs_.size() - 1) { - return 0.; - } - - //Recompute recursively - double node_cost = total_cost_from_scratch(left_child(inode)) - + total_cost_from_scratch(right_child(inode)); - - return node_cost; - } - - ///@brief Friend-ed so it can call invalidate(). - friend ConnectionProxy; - - void invalidate(double* invalidated_cost) { - //Check pointer within range of internal storage - VTR_ASSERT_SAFE_MSG( - invalidated_cost >= &connection_costs_[0], - "Connection cost pointer should be after start of internal storage"); - - VTR_ASSERT_SAFE_MSG( - invalidated_cost <= &connection_costs_[connection_costs_.size() - 1], - "Connection cost pointer should be before end of internal storage"); - - size_t icost = invalidated_cost - &connection_costs_[0]; - - VTR_ASSERT_SAFE(icost >= num_nodes_up_to_level(num_levels_ - 2)); - - //Invalidate parent intermediate costs up to root or first - //already-invalidated parent - size_t iparent = parent(icost); - - while (!std::isnan(connection_costs_[iparent])) { - //Invalidate - connection_costs_[iparent] = std::numeric_limits::quiet_NaN(); - - if (iparent == 0) { - break; //At root - } else { - //Next parent - iparent = parent(iparent); - } - } - - VTR_ASSERT_SAFE_MSG(std::isnan(connection_costs_[0]), "Invalidating any connection should have invalidated the root"); - } - - size_t left_child(size_t i) const { - return 2 * i + 1; - } - - size_t right_child(size_t i) const { - return 2 * i + 2; - } - - size_t parent(size_t i) const { - return (i - 1) / 2; - } - - /** - * @brief Returns the number of nodes in ilevel'th level. - * - * If ilevel is negative, return 0, since the root shouldn't - * be counted as a leaf node candidate. - */ - size_t num_nodes_in_level(int ilevel) const { - return ilevel < 0 ? 0 : (2 << (ilevel)); - } - - ///@brief Returns the total number of nodes in levels [0..ilevel] (inclusive). - size_t num_nodes_up_to_level(int ilevel) const { - return (2 << (ilevel + 1)) - 1; - } - - private: - /** - * @brief Vector storing the implicit binary tree of connection costs. - * - * The actual connections are stored at the end of the vector - * (last level of the binary tree). The earlier portions of - * the tree are the intermediate nodes. - * - * The methods left_child()/right_child()/parent() can be used - * to traverse the tree by indicies into this vector. - */ - std::vector connection_costs_; - - /** - * @brief Vector storing the indicies of the first connection - * for each net in the netlist, used for indexing by net. - */ - vtr::vector net_start_indicies_; - - ///@brief Number of levels in the binary tree. - size_t num_levels_ = 0; -}; diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp deleted file mode 100644 index 86dc396e2b8..00000000000 --- a/vpr/src/place/timing_place_lookup.cpp +++ /dev/null @@ -1,1319 +0,0 @@ - -#include -#include - -#include "rr_graph_fwd.h" -#include "vtr_assert.h" -#include "vtr_ndmatrix.h" -#include "vtr_log.h" -#include "vtr_util.h" -#include "vtr_math.h" -#include "vtr_memory.h" -#include "vtr_time.h" -#include "vtr_geometry.h" - -#include "arch_util.h" -#include "vpr_types.h" -#include "globals.h" -#include "place_and_route.h" -#include "route_net.h" -#include "timing_place_lookup.h" -#include "read_xml_arch_file.h" -#include "atom_netlist.h" - -// all functions in profiling:: namespace, which are only activated if PROFILE is defined -#include "route_profiling.h" -#include "router_delay_profiling.h" -#include "place_delay_model.h" - -/*To compute delay between blocks we calculate the delay between */ -/*different nodes in the FPGA. From this procedure we generate - * a lookup table which tells us the delay between different locations in*/ -/*the FPGA */ - -/*the delta arrays are used to contain the best case routing delay */ -/*between different locations on the FPGA. */ - -//#define VERBOSE - -constexpr float UNINITIALIZED_DELTA = -1; //Indicates the delta delay value has not been calculated -constexpr float EMPTY_DELTA = -2; //Indicates delta delay from/to an EMPTY block -constexpr float IMPOSSIBLE_DELTA = std::numeric_limits::infinity(); //Indicates there is no valid delta delay - -struct t_profile_loc { - t_profile_loc(int x, int y, std::vector> delta_values) - : root(x, y) - , deltas(delta_values) {} - - vtr::Point root; - std::vector> deltas; -}; - -struct t_profile_info { - std::vector locations; - - int max_delta_x; - int max_delta_y; -}; - -/*** Function Prototypes *****/ -static t_chan_width setup_chan_width(const t_router_opts& router_opts, - t_chan_width_dist chan_width_dist); - -static float route_connection_delay( - RouterDelayProfiler& route_profiler, - int from_layer_num, - int to_layer_num, - int source_x_loc, - int source_y_loc, - int sink_x_loc, - int sink_y_loc, - const t_router_opts& router_opts, - bool measure_directconnect); - -// Prototype for computing delta delay matrix. -typedef std::function>&, - int, - int, - int, - int, - int, - int, - int, - int, - const t_router_opts&, - bool, - const std::set&, - bool)> - t_compute_delta_delay_matrix; - -static void generic_compute_matrix_iterative_astar( - RouterDelayProfiler& route_profiler, - vtr::Matrix>& matrix, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types, - bool /***/); - -static void generic_compute_matrix_dijkstra_expansion( - RouterDelayProfiler& route_profiler, - vtr::Matrix>& matrix, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types, - bool is_flat); - -static vtr::NdMatrix compute_delta_delays( - RouterDelayProfiler& route_profiler, - const t_placer_opts& palcer_opts, - const t_router_opts& router_opts, - bool measure_directconnect, - size_t longest_length, - bool is_flat); - -float delay_reduce(std::vector& delays, e_reducer reducer); - -static vtr::NdMatrix compute_delta_delay_model( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - bool measure_directconnect, - int longest_length, - bool is_flat); - -/** - * @brief Use the information in the router lookahead to fill the delay matrix instead of running the router - * @param route_profiler - * @return The delay matrix that contain the minimum cost between two locations - */ -static vtr::NdMatrix compute_simple_delay_model(RouterDelayProfiler& route_profiler); - -static bool find_direct_connect_sample_locations(const t_direct_inf* direct, - t_physical_tile_type_ptr from_type, - int from_pin, - int from_pin_class, - t_physical_tile_type_ptr to_type, - int to_pin, - int to_pin_class, - RRNodeId& out_src_node, - RRNodeId& out_sink_node); - -static bool verify_delta_delays(const vtr::NdMatrix& delta_delays); - -static int get_longest_segment_length(std::vector& segment_inf); - -static void fix_empty_coordinates(vtr::NdMatrix& delta_delays); -static void fix_uninitialized_coordinates(vtr::NdMatrix& delta_delays); - -static float find_neighboring_average(vtr::NdMatrix& matrix, - int from_layer, - t_physical_tile_loc to_tile_loc, - int max_distance); - -/******* Globally Accessible Functions **********/ - -std::unique_ptr compute_place_delay_model(const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - const Netlist<>& net_list, - t_det_routing_arch* det_routing_arch, - std::vector& segment_inf, - t_chan_width_dist chan_width_dist, - const std::vector& directs, - bool is_flat) { - vtr::ScopedStartFinishTimer timer("Computing placement delta delay look-up"); - - t_chan_width chan_width = setup_chan_width(router_opts, chan_width_dist); - - alloc_routing_structs(chan_width, router_opts, det_routing_arch, segment_inf, directs, is_flat); - - const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, - router_opts.lookahead_type, - router_opts.write_router_lookahead, - router_opts.read_router_lookahead, - segment_inf, - is_flat); - - RouterDelayProfiler route_profiler(net_list, router_lookahead, is_flat); - - int longest_length = get_longest_segment_length(segment_inf); - - /*now setup and compute the actual arrays */ - std::unique_ptr place_delay_model; - float min_cross_layer_delay = get_min_cross_layer_delay(); - - if (placer_opts.delay_model_type == PlaceDelayModelType::SIMPLE) { - place_delay_model = std::make_unique(); - } else if (placer_opts.delay_model_type == PlaceDelayModelType::DELTA) { - place_delay_model = std::make_unique(min_cross_layer_delay, is_flat); - } else if (placer_opts.delay_model_type == PlaceDelayModelType::DELTA_OVERRIDE) { - place_delay_model = std::make_unique(min_cross_layer_delay, is_flat); - } else { - VTR_ASSERT_MSG(false, "Invalid placer delay model"); - } - - if (placer_opts.read_placement_delay_lookup.empty()) { - place_delay_model->compute(route_profiler, placer_opts, router_opts, longest_length); - } else { - place_delay_model->read(placer_opts.read_placement_delay_lookup); - } - - if (!placer_opts.write_placement_delay_lookup.empty()) { - place_delay_model->write(placer_opts.write_placement_delay_lookup); - } - - /*free all data structures that are no longer needed */ - free_routing_structs(); - - return place_delay_model; -} - -void DeltaDelayModel::compute( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) { - delays_ = compute_delta_delay_model( - route_profiler, - placer_opts, router_opts, /*measure_directconnect=*/true, - longest_length, - is_flat_); -} - -void OverrideDelayModel::compute( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - int longest_length) { - auto delays = compute_delta_delay_model( - route_profiler, - placer_opts, router_opts, /*measure_directconnect=*/false, - longest_length, - is_flat_); - - base_delay_model_ = std::make_unique(cross_layer_delay_, delays, false); - - compute_override_delay_model(route_profiler, router_opts); -} - -void SimpleDelayModel::compute( - RouterDelayProfiler& router, - const t_placer_opts& /*placer_opts*/, - const t_router_opts& /*router_opts*/, - int /*longest_length*/) { - delays_ = compute_simple_delay_model(router); -} - -/******* File Accessible Functions **********/ - -std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type) { - /* - * This function tries to identify the best pin classes to hook up - * for delay calculation. The assumption is that we should pick - * the pin class with the largest number of pins. This makes - * sense, since it ensures we pick commonly used pins, and - * removes order dependence on how the pins are specified - * in the architecture (except in the case were the two largest pin classes - * of a particular pintype have the same number of pins, in which case the - * first pin class is used). - */ - - std::vector best_classes; - - //Record any non-zero Fc pins - // - //Note that we track non-zero Fc pins, since certain Fc overides - //may apply to only a subset of wire types. This ensures we record - //which pins can potentially connect to global routing. - std::unordered_set non_zero_fc_pins; - for (const t_fc_specification& fc_spec : type->fc_specs) { - if (fc_spec.fc_value == 0) continue; - - non_zero_fc_pins.insert(fc_spec.pins.begin(), fc_spec.pins.end()); - } - - //Collect all classes of matching type which connect to general routing - for (int i = 0; i < (int)type->class_inf.size(); i++) { - if (type->class_inf[i].type == pintype) { - //Check whether all pins in this class are ignored or have zero fc - bool any_pins_connect_to_general_routing = false; - for (int ipin = 0; ipin < type->class_inf[i].num_pins; ++ipin) { - int pin = type->class_inf[i].pinlist[ipin]; - //If the pin isn't ignored, and has a non-zero Fc to some general - //routing the class is suitable for delay profiling - if (!type->is_ignored_pin[pin] && non_zero_fc_pins.count(pin)) { - any_pins_connect_to_general_routing = true; - break; - } - } - - if (!any_pins_connect_to_general_routing) continue; //Skip if doesn't connect to general routing - - //Record candidate class - best_classes.push_back(i); - } - } - - //Sort classe so largest pin class is first - auto cmp_class = [&](int lhs, int rhs) { - return type->class_inf[lhs].num_pins > type->class_inf[rhs].num_pins; - }; - - std::stable_sort(best_classes.begin(), best_classes.end(), cmp_class); - - return best_classes; -} - -static int get_longest_segment_length(std::vector& segment_inf) { - int length = 0; - - for (const t_segment_inf &seg_info : segment_inf) { - if (seg_info.length > length) { - length = seg_info.length; - } - } - - return length; -} - -static t_chan_width setup_chan_width(const t_router_opts& router_opts, - t_chan_width_dist chan_width_dist) { - /*we give plenty of tracks, this increases routability for the */ - /*lookup table generation */ - - t_graph_type graph_directionality; - int width_fac; - - if (router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH) { - auto& device_ctx = g_vpr_ctx.device(); - - auto type = find_most_common_tile_type(device_ctx.grid); - - width_fac = 4 * type->num_pins; - /*this is 2x the value that binary search starts */ - /*this should be enough to allow most pins to */ - /*connect to tracks in the architecture */ - } else { - width_fac = router_opts.fixed_channel_width; - } - - if (router_opts.route_type == GLOBAL) { - graph_directionality = GRAPH_BIDIR; - } else { - graph_directionality = GRAPH_UNIDIR; - } - - return init_chan(width_fac, chan_width_dist, graph_directionality); -} - -static float route_connection_delay( - RouterDelayProfiler& route_profiler, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int sink_x, - int sink_y, - const t_router_opts& router_opts, - bool measure_directconnect) { - //Routes between the source and sink locations and calculates the delay - - float net_delay_value = IMPOSSIBLE_DELTA; /*set to known value for debug purposes */ - - auto& device_ctx = g_vpr_ctx.device(); - - bool successfully_routed = false; - - //Get the rr nodes to route between - auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); - auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); - - for (int driver_ptc : best_driver_ptcs) { - VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, SOURCE, driver_ptc); - - VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); - - for (int sink_ptc : best_sink_ptcs) { - VTR_ASSERT(sink_ptc != OPEN); - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, SINK, sink_ptc); - - if (sink_rr_node == RRNodeId::INVALID()) - continue; - - if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { - //Skip if we shouldn't measure direct connects and a direct connect exists - continue; - } - - { - successfully_routed = route_profiler.calculate_delay( - source_rr_node, sink_rr_node, - router_opts, - &net_delay_value); - } - - if (successfully_routed) break; - } - if (successfully_routed) break; - } - - if (!successfully_routed) { - VTR_LOG_WARN("Unable to route between blocks at (%d,%d,%d) and (%d,%d,%d) to characterize delay (setting to %g)\n", - source_x, source_y, from_layer_num, sink_x, sink_y, to_layer_num, net_delay_value); - } - - return (net_delay_value); -} - -static void add_delay_to_matrix( - vtr::Matrix>* matrix, - int delta_x, - int delta_y, - float delay) { - if ((*matrix)[delta_x][delta_y].size() == 1 && (*matrix)[delta_x][delta_y][0] == EMPTY_DELTA) { - //Overwrite empty delta - (*matrix)[delta_x][delta_y][0] = delay; - } else { - //Collect delta - (*matrix)[delta_x][delta_y].push_back(delay); - } -} - -static void generic_compute_matrix_dijkstra_expansion( - RouterDelayProfiler& /*route_profiler*/, - vtr::Matrix>& matrix, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types, - bool is_flat) { - auto& device_ctx = g_vpr_ctx.device(); - - t_physical_tile_type_ptr src_type = device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num}); - bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); - if (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE || !is_allowed_type) { - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - - if (matrix[delta_x][delta_y].empty()) { - //Only set empty target if we don't already have a valid delta delay - matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE - VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", - "EMPTY", - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - } - } - } - - return; - } - - vtr::Matrix found_matrix({matrix.dim_size(0), matrix.dim_size(1)}, false); - - auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); - for (int driver_ptc : best_driver_ptcs) { - VTR_ASSERT(driver_ptc != OPEN); - RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, SOURCE, driver_ptc); - - VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); - auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts, is_flat); - - bool path_to_all_sinks = true; - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - - if (found_matrix[delta_x][delta_y]) { - continue; - } - - t_physical_tile_type_ptr sink_type = device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num}); - if (sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { - if (matrix[delta_x][delta_y].empty()) { - //Only set empty target if we don't already have a valid delta delay - matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE - VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", - "EMPTY", - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - found_matrix[delta_x][delta_y] = true; - } - } else { - bool found_a_sink = false; - auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); - for (int sink_ptc : best_sink_ptcs) { - VTR_ASSERT(sink_ptc != OPEN); - RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, SINK, sink_ptc); - - if (sink_rr_node == RRNodeId::INVALID()) - continue; - - if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { - //Skip if we shouldn't measure direct connects and a direct connect exists - continue; - } - - if (std::isnan(delays[sink_rr_node])) { - // This sink was not found - continue; - } - -#ifdef VERBOSE - VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", - delays[size_t(sink_rr_node)], - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - found_matrix[delta_x][delta_y] = true; - - add_delay_to_matrix(&matrix, delta_x, delta_y, delays[sink_rr_node]); - - found_a_sink = true; - break; - } - - if (!found_a_sink) { - path_to_all_sinks = false; - } - } - } - } - - if (path_to_all_sinks) { - break; - } - } - - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - if (!found_matrix[delta_x][delta_y]) { - add_delay_to_matrix(&matrix, delta_x, delta_y, IMPOSSIBLE_DELTA); - VTR_LOG_WARN("Unable to route between blocks at (%d,%d,%d) and (%d,%d,%d) to characterize delay (setting to %g)\n", - source_x, - source_y, - from_layer_num, - sink_x, - sink_y, - to_layer_num, - IMPOSSIBLE_DELTA); - } - } - } -} - -static void generic_compute_matrix_iterative_astar( - RouterDelayProfiler& route_profiler, - vtr::Matrix>& matrix, - int from_layer_num, - int to_layer_num, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types, - bool /***/) { - //vtr::ScopedStartFinishTimer t(vtr::string_fmt("Profiling from (%d,%d)", source_x, source_y)); - - int delta_x, delta_y; - int sink_x, sink_y; - - auto& device_ctx = g_vpr_ctx.device(); - - for (sink_x = start_x; sink_x <= end_x; sink_x++) { - for (sink_y = start_y; sink_y <= end_y; sink_y++) { - delta_x = abs(sink_x - source_x); - delta_y = abs(sink_y - source_y); - - t_physical_tile_type_ptr src_type = device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num}); - t_physical_tile_type_ptr sink_type = device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num}); - - bool src_or_target_empty = (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE - || sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE); - - bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); - - if (src_or_target_empty || !is_allowed_type) { - if (matrix[delta_x][delta_y].empty()) { - //Only set empty target if we don't already have a valid delta delay - matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE - VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", - "EMPTY", - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - } - } else { - //Valid start/end - - float delay = route_connection_delay(route_profiler, - from_layer_num, - to_layer_num, - source_x, - source_y, - sink_x, - sink_y, - router_opts, - measure_directconnect); - -#ifdef VERBOSE - VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", - delay, - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - if (matrix[delta_x][delta_y].size() == 1 && matrix[delta_x][delta_y][0] == EMPTY_DELTA) { - //Overwrite empty delta - matrix[delta_x][delta_y][0] = delay; - } else { - //Collect delta - matrix[delta_x][delta_y].push_back(delay); - } - } - } - } -} - -static vtr::NdMatrix compute_delta_delays( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - bool measure_directconnect, - size_t longest_length, - bool is_flat) { - //To avoid edge effects we place the source at least 'longest_length' away - //from the device edge - //and route from there for all possible delta values < dimension - - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - - vtr::NdMatrix delta_delays({static_cast(grid.get_num_layers()), static_cast(grid.get_num_layers()), grid.width(), grid.height()}); - - for (int from_layer_num = 0; from_layer_num < grid.get_num_layers(); from_layer_num++) { - for (int to_layer_num = 0; to_layer_num < grid.get_num_layers(); to_layer_num++) { - vtr::NdMatrix, 2> sampled_delta_delays({grid.width(), grid.height()}); - - size_t mid_x = vtr::nint(grid.width() / 2); - size_t mid_y = vtr::nint(grid.height() / 2); - - size_t low_x = std::min(longest_length, mid_x); - size_t low_y = std::min(longest_length, mid_y); - size_t high_x = mid_x; - size_t high_y = mid_y; - if (longest_length <= grid.width()) { - high_x = std::max(grid.width() - longest_length, mid_x); - } - if (longest_length <= grid.height()) { - high_y = std::max(grid.height() - longest_length, mid_y); - } - - std::set allowed_types; - if (!placer_opts.allowed_tiles_for_delay_model.empty()) { - auto allowed_types_vector = vtr::split(placer_opts.allowed_tiles_for_delay_model, ","); - for (const auto& type : allowed_types_vector) { - allowed_types.insert(type); - } - } - - // +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - // + | | + - // + A | B | C + - // + | | + - // +-----------------\-----------------------.---------------+ - // + | | + - // + | | + - // + | | + - // + | | + - // + D | E | F + - // + | | + - // + | | + - // + | | + - // + | | + - // +-----------------*-----------------------/---------------+ - // + | | + - // + G | H | I + - // + | | + - // +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - // - // * = (low_x, low_y) - // . = (high_x, high_y) - // / = (high_x, low_y) - // \ = (low_x, high_y) - // + = device edge - - //Find the lowest y location on the left edge with a non-empty block - int y = 0; - int x = 0; - t_physical_tile_type_ptr src_type = nullptr; - for (x = 0; x < (int)grid.width(); ++x) { - for (y = 0; y < (int)grid.height(); ++y) { - auto type = grid.get_physical_type({x, y, from_layer_num}); - - if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { - if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { - continue; - } - src_type = type; - break; - } - } - if (src_type) { - break; - } - } - VTR_ASSERT(src_type != nullptr); - - t_compute_delta_delay_matrix generic_compute_matrix; - switch (placer_opts.place_delta_delay_matrix_calculation_method) { - case e_place_delta_delay_algorithm::ASTAR_ROUTE: - generic_compute_matrix = generic_compute_matrix_iterative_astar; - break; - case e_place_delta_delay_algorithm::DIJKSTRA_EXPANSION: - generic_compute_matrix = generic_compute_matrix_dijkstra_expansion; - break; - default: - VPR_FATAL_ERROR(VPR_ERROR_PLACE, "Unknown place_delta_delay_matrix_calculation_method %d", placer_opts.place_delta_delay_matrix_calculation_method); - } - -#ifdef VERBOSE - VTR_LOG("Computing from lower left edge (%d,%d):\n", x, y); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - x, y, - x, y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Find the lowest x location on the bottom edge with a non-empty block - src_type = nullptr; - for (y = 0; y < (int)grid.height(); ++y) { - for (x = 0; x < (int)grid.width(); ++x) { - auto type = grid.get_physical_type({x, y, from_layer_num}); - - if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { - if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { - continue; - } - src_type = type; - break; - } - } - if (src_type) { - break; - } - } - VTR_ASSERT(src_type != nullptr); -#ifdef VERBOSE - VTR_LOG("Computing from left bottom edge (%d,%d):\n", x, y); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - x, y, - x, y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Since the other delta delay values may have suffered from edge effects, - //we recalculate deltas within regions B, C, E, F -#ifdef VERBOSE - VTR_LOG("Computing from low/low:\n"); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - low_x, low_y, - low_x, low_y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Since the other delta delay values may have suffered from edge effects, - //we recalculate deltas within regions D, E, G, H -#ifdef VERBOSE - VTR_LOG("Computing from high/high:\n"); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - high_x, high_y, - 0, 0, - high_x, high_y, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Since the other delta delay values may have suffered from edge effects, - //we recalculate deltas within regions A, B, D, E -#ifdef VERBOSE - VTR_LOG("Computing from high/low:\n"); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - high_x, low_y, - 0, low_y, - high_x, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types, - is_flat); - - //Since the other delta delay values may have suffered from edge effects, - //we recalculate deltas within regions E, F, H, I -#ifdef VERBOSE - VTR_LOG("Computing from low/high:\n"); -#endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - from_layer_num, to_layer_num, - low_x, high_y, - low_x, 0, - grid.width() - 1, high_y, - router_opts, - measure_directconnect, allowed_types, - is_flat); - for (size_t dx = 0; dx < sampled_delta_delays.dim_size(0); ++dx) { - for (size_t dy = 0; dy < sampled_delta_delays.dim_size(1); ++dy) { - delta_delays[from_layer_num][to_layer_num][dx][dy] = delay_reduce(sampled_delta_delays[dx][dy], placer_opts.delay_model_reducer); - } - } - } - } - - return delta_delays; -} - -float delay_reduce(std::vector& delays, e_reducer reducer) { - if (delays.empty()) { - return IMPOSSIBLE_DELTA; - } else if (delays.size() == 1) { - return delays[0]; - } - - VTR_ASSERT(delays.size() > 1); - - float delay; - - if (reducer == e_reducer::MIN) { - auto itr = std::min_element(delays.begin(), delays.end()); - delay = *itr; - } else if (reducer == e_reducer::MAX) { - auto itr = std::max_element(delays.begin(), delays.end()); - delay = *itr; - } else if (reducer == e_reducer::MEDIAN) { - std::stable_sort(delays.begin(), delays.end()); - delay = vtr::median(delays.begin(), delays.end()); - } else if (reducer == e_reducer::ARITHMEAN) { - delay = vtr::arithmean(delays.begin(), delays.end()); - } else if (reducer == e_reducer::GEOMEAN) { - delay = vtr::geomean(delays.begin(), delays.end()); - } else { - VPR_FATAL_ERROR(VPR_ERROR_PLACE, "Unrecognized delta delay reducer"); - } - - return delay; -} - -/* We return the average placement estimated delay for a routing spanning (x,y). - * We start with an averaging distance of 1 (i.e. from (x-1,y-1) to (x+1,y+1)) - * and look for legal delay values to average; if some are found we return the - * average and if none are found we increase the distance to average over. - * - * If no legal values are found to average over with a range of max_distance, - * we return IMPOSSIBLE_DELTA. - */ -static float find_neighboring_average( - vtr::NdMatrix& matrix, - int from_layer, - t_physical_tile_loc to_tile_loc, - int max_distance) { - float sum = 0; - int counter = 0; - int endx = matrix.end_index(2); - int endy = matrix.end_index(3); - - int x = to_tile_loc.x; - int y = to_tile_loc.y; - int to_layer = to_tile_loc.layer_num; - - for (int distance = 1; distance <= max_distance; ++distance) { - for (int delx = x - distance; delx <= x + distance; delx++) { - for (int dely = y - distance; dely <= y + distance; dely++) { - // Check distance constraint - if (abs(delx - x) + abs(dely - y) > distance) { - continue; - } - - //check out of bounds - if (delx < 0 || dely < 0 || delx >= endx || dely >= endy || (delx == x && dely == y)) { - continue; - } - - if (matrix[from_layer][to_layer][delx][dely] == EMPTY_DELTA || matrix[from_layer][to_layer][delx][dely] == IMPOSSIBLE_DELTA) { - continue; - } - counter++; - sum += matrix[from_layer][to_layer][delx][dely]; - } - } - if (counter != 0) { - return sum / (float)counter; - } - } - - return IMPOSSIBLE_DELTA; -} - -static void fix_empty_coordinates(vtr::NdMatrix& delta_delays) { - // Set any empty delta's to the average of it's neighbours - // - // Empty coordinates may occur if the sampling location happens to not have - // a connection at that location. However a more through sampling likely - // would return a result, so we fill in the empty holes with a small - // neighbour average. - constexpr int kMaxAverageDistance = 2; - for (int from_layer = 0; from_layer < (int)delta_delays.dim_size(0); ++from_layer) { - for (int to_layer = 0; to_layer < (int)delta_delays.dim_size(1); ++to_layer) { - for (int delta_x = 0; delta_x < (int)delta_delays.dim_size(2); ++delta_x) { - for (int delta_y = 0; delta_y < (int)delta_delays.dim_size(3); ++delta_y) { - if (delta_delays[from_layer][to_layer][delta_x][delta_y] == EMPTY_DELTA) { - delta_delays[from_layer][to_layer][delta_x][delta_y] = - find_neighboring_average(delta_delays, - from_layer, - {delta_x, delta_y, to_layer}, - kMaxAverageDistance); - } - } - } - } - } -} - -static void fix_uninitialized_coordinates(vtr::NdMatrix& delta_delays) { - // Set any empty delta's to the average of it's neighbours - - for (size_t from_layer_num = 0; from_layer_num < delta_delays.dim_size(0); ++from_layer_num) { - for (size_t to_layer_num = 0; to_layer_num < delta_delays.dim_size(1); ++to_layer_num) { - for (size_t delta_x = 0; delta_x < delta_delays.dim_size(2); ++delta_x) { - for (size_t delta_y = 0; delta_y < delta_delays.dim_size(3); ++delta_y) { - if (delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] == UNINITIALIZED_DELTA) { - delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] = IMPOSSIBLE_DELTA; - } - } - } - } - } -} - -static void fill_impossible_coordinates(vtr::NdMatrix& delta_delays) { - // Set any impossible delta's to the average of its neighbours - // - // Impossible coordinates may occur if an IPIN cannot be reached from the - // sampling OPIN. This might occur if the IPIN or OPIN used for sampling - // is specialized, and therefore cannot be reached via the by the pins - // sampled. Leaving this value in the delay matrix will result in invalid - // slacks if the delay matrix uses this value. - // - // A max average distance of 5 is used to provide increased effort in - // filling these gaps. It is more important to have a poor predication, - // than an invalid value and causing a slack assertion. - constexpr int kMaxAverageDistance = 5; - for (int from_layer_num = 0; from_layer_num < (int)delta_delays.dim_size(0); ++from_layer_num) { - for (int to_layer_num = 0; to_layer_num < (int)delta_delays.dim_size(1); ++to_layer_num) { - for (int delta_x = 0; delta_x < (int)delta_delays.dim_size(2); ++delta_x) { - for (int delta_y = 0; delta_y < (int)delta_delays.dim_size(3); ++delta_y) { - if (delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] == IMPOSSIBLE_DELTA) { - delta_delays[from_layer_num][to_layer_num][delta_x][delta_y] = find_neighboring_average( - delta_delays, from_layer_num, {delta_x, delta_y, to_layer_num}, kMaxAverageDistance); - } - } - } - } - } -} - -static vtr::NdMatrix compute_delta_delay_model( - RouterDelayProfiler& route_profiler, - const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - bool measure_directconnect, - int longest_length, - bool is_flat) { - vtr::ScopedStartFinishTimer timer("Computing delta delays"); - vtr::NdMatrix delta_delays = compute_delta_delays(route_profiler, - placer_opts, - router_opts, - measure_directconnect, - longest_length, - is_flat); - - fix_uninitialized_coordinates(delta_delays); - - fix_empty_coordinates(delta_delays); - - fill_impossible_coordinates(delta_delays); - - verify_delta_delays(delta_delays); - - return delta_delays; -} - -static vtr::NdMatrix compute_simple_delay_model(RouterDelayProfiler& route_profiler) { - const auto& grid = g_vpr_ctx.device().grid; - int num_physical_tile_types = static_cast(g_vpr_ctx.device().physical_tile_types.size()); - // Initializing the delay matrix to [num_physical_types][num_layers][num_layers][width][height] - // The second index related to the layer that the source location is on and the third index is for the sink layer - vtr::NdMatrix delta_delays({static_cast(num_physical_tile_types), - static_cast(grid.get_num_layers()), - static_cast(grid.get_num_layers()), - grid.width(), - grid.height()}); - - for (int physical_tile_type_idx = 0; physical_tile_type_idx < num_physical_tile_types; ++physical_tile_type_idx) { - for (int from_layer = 0; from_layer < grid.get_num_layers(); ++from_layer) { - for (int to_layer = 0; to_layer < grid.get_num_layers(); ++to_layer) { - for (int dx = 0; dx < static_cast(grid.width()); ++dx) { - for (int dy = 0; dy < static_cast(grid.height()); ++dy) { - float min_delay = route_profiler.get_min_delay(physical_tile_type_idx, - from_layer, - to_layer, - dx, - dy); - delta_delays[physical_tile_type_idx][from_layer][to_layer][dx][dy] = min_delay; - } - } - } - } - } - - return delta_delays; -} - -//Finds a src_rr and sink_rr appropriate for measuring the delay of the current direct specification -static bool find_direct_connect_sample_locations(const t_direct_inf* direct, - t_physical_tile_type_ptr from_type, - int from_pin, - int from_pin_class, - t_physical_tile_type_ptr to_type, - int to_pin, - int to_pin_class, - RRNodeId& out_src_node, - RRNodeId& out_sink_node) { - VTR_ASSERT(from_type != nullptr); - VTR_ASSERT(to_type != nullptr); - - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - const auto& node_lookup = device_ctx.rr_graph.node_lookup(); - - //Search the grid for an instance of from/to blocks which satisfy this direct connect offsets, - //and which has the appropriate pins - int from_x = -1; - int from_y = -1; - int from_sub_tile = -1; - int to_x = 0, to_y = 0, to_sub_tile = 0; - bool found = false; - int found_layer_num = -1; - //TODO: Function *FOR NOW* assumes that from/to blocks are at same die and have a same layer nums - for (int layer_num = 0; layer_num < grid.get_num_layers() && !found; ++layer_num) { - for (int x = 0; x < (int)grid.width() && !found; ++x) { - to_x = x + direct->x_offset; - if (to_x < 0 || to_x >= (int)grid.width()) continue; - - for (int y = 0; y < (int)grid.height() && !found; ++y) { - if (grid.get_physical_type({x, y, layer_num}) != from_type) continue; - - //Check that the from pin exists at this from location - //(with multi-width/height blocks pins may not exist at all locations) - bool from_pin_found = false; - if (direct->from_side != NUM_2D_SIDES) { - RRNodeId from_pin_rr = node_lookup.find_node(layer_num, x, y, OPIN, from_pin, direct->from_side); - from_pin_found = from_pin_rr.is_valid(); - } else { - from_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, x, y, OPIN, from_pin).empty()); - } - if (!from_pin_found) continue; - - to_y = y + direct->y_offset; - - if (to_y < 0 || to_y >= (int)grid.height()) continue; - if (grid.get_physical_type({to_x, to_y, layer_num}) != to_type) continue; - - //Check that the from pin exists at this from location - //(with multi-width/height blocks pins may not exist at all locations) - bool to_pin_found = false; - if (direct->to_side != NUM_2D_SIDES) { - RRNodeId to_pin_rr = node_lookup.find_node(layer_num, to_x, to_y, IPIN, to_pin, direct->to_side); - to_pin_found = (to_pin_rr != RRNodeId::INVALID()); - } else { - to_pin_found = !(node_lookup.find_nodes_at_all_sides(layer_num, to_x, to_y, IPIN, to_pin).empty()); - } - if (!to_pin_found) continue; - - for (int sub_tile_num = 0; sub_tile_num < from_type->capacity; ++sub_tile_num) { - to_sub_tile = sub_tile_num + direct->sub_tile_offset; - - if (to_sub_tile < 0 || to_sub_tile >= to_type->capacity) continue; - - found = true; - found_layer_num = layer_num; - from_x = x; - from_y = y; - from_sub_tile = sub_tile_num; - - break; - } - } - } - } - - if (!found) { - return false; - } - - //Now have a legal instance of this direct connect - VTR_ASSERT(grid.get_physical_type({from_x, from_y, found_layer_num}) == from_type); - VTR_ASSERT(from_sub_tile < from_type->capacity); - - VTR_ASSERT(grid.get_physical_type({to_x, to_y, found_layer_num}) == to_type); - VTR_ASSERT(to_sub_tile < to_type->capacity); - - VTR_ASSERT(from_x + direct->x_offset == to_x); - VTR_ASSERT(from_y + direct->y_offset == to_y); - VTR_ASSERT(from_sub_tile + direct->sub_tile_offset == to_sub_tile); - - // - //Find a source/sink RR node associated with the pins of the direct - // - - { - RRNodeId src_rr_candidate = node_lookup.find_node(found_layer_num, from_x, from_y, SOURCE, from_pin_class); - VTR_ASSERT(src_rr_candidate); - out_src_node = src_rr_candidate; - } - - { - RRNodeId sink_rr_candidate = node_lookup.find_node(found_layer_num, to_x, to_y, SINK, to_pin_class); - VTR_ASSERT(sink_rr_candidate); - out_sink_node = sink_rr_candidate; - } - - return true; -} - -static bool verify_delta_delays(const vtr::NdMatrix& delta_delays) { - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - - for (int from_layer_num = 0; from_layer_num < grid.get_num_layers(); ++from_layer_num) { - for (int to_layer_num = 0; to_layer_num < grid.get_num_layers(); ++to_layer_num) { - for (size_t x = 0; x < grid.width(); ++x) { - for (size_t y = 0; y < grid.height(); ++y) { - float delta_delay = delta_delays[from_layer_num][to_layer_num][x][y]; - - if (delta_delay < 0.) { - VPR_ERROR(VPR_ERROR_PLACE, - "Found invaild negative delay %g for delta [%d,%d,%d,%d]", - delta_delay, from_layer_num, to_layer_num, x, y); - } - } - } - } - } - - return true; -} - -void OverrideDelayModel::compute_override_delay_model( - RouterDelayProfiler& route_profiler, - const t_router_opts& router_opts) { - t_router_opts router_opts2 = router_opts; - router_opts2.astar_fac = 0.f; - router_opts2.astar_offset = 0.f; - - //Look at all the direct connections that exist, and add overrides to delay model - auto& device_ctx = g_vpr_ctx.device(); - for (int idirect = 0; idirect < (int)device_ctx.arch->directs.size(); ++idirect) { - const t_direct_inf* direct = &device_ctx.arch->directs[idirect]; - - InstPort from_port = parse_inst_port(direct->from_pin); - InstPort to_port = parse_inst_port(direct->to_pin); - - t_physical_tile_type_ptr from_type = find_tile_type_by_name(from_port.instance_name(), device_ctx.physical_tile_types); - t_physical_tile_type_ptr to_type = find_tile_type_by_name(to_port.instance_name(), device_ctx.physical_tile_types); - - int num_conns = from_port.port_high_index() - from_port.port_low_index() + 1; - VTR_ASSERT_MSG(num_conns == to_port.port_high_index() - to_port.port_low_index() + 1, "Directs must have the same size to/from"); - - //We now walk through all the connections associated with the current direct specification, measure - //their delay and specify that value as an override in the delay model. - // - //Note that we need to check every connection in the direct to cover the case where the pins are not - //equivalent. - // - //However, if the from/to ports are equivalent we could end up sampling the same RR SOURCE/SINK - //paths multiple times (wasting CPU time) -- we avoid this by recording the sampled paths in - //sampled_rr_pairs and skipping them if they occur multiple times. - int missing_instances = 0; - int missing_paths = 0; - std::set> sampled_rr_pairs; - for (int iconn = 0; iconn < num_conns; ++iconn) { - //Find the associated pins - int from_pin = find_pin(from_type, from_port.port_name(), from_port.port_low_index() + iconn); - int to_pin = find_pin(to_type, to_port.port_name(), to_port.port_low_index() + iconn); - - VTR_ASSERT(from_pin != OPEN); - VTR_ASSERT(to_pin != OPEN); - - int from_pin_class = find_pin_class(from_type, from_port.port_name(), from_port.port_low_index() + iconn, DRIVER); - VTR_ASSERT(from_pin_class != OPEN); - - int to_pin_class = find_pin_class(to_type, to_port.port_name(), to_port.port_low_index() + iconn, RECEIVER); - VTR_ASSERT(to_pin_class != OPEN); - - bool found_sample_points; - RRNodeId src_rr, sink_rr; - found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, src_rr, sink_rr); - - if (!found_sample_points) { - ++missing_instances; - continue; - } - - //If some of the source/sink ports are logically equivalent we may have already - //sampled the associated source/sink pair and don't need to do so again - if (sampled_rr_pairs.count({src_rr, sink_rr})) continue; - - float direct_connect_delay = std::numeric_limits::quiet_NaN(); - bool found_routing_path = route_profiler.calculate_delay(src_rr, sink_rr, router_opts2, &direct_connect_delay); - - if (found_routing_path) { - set_delay_override(from_type->index, from_pin_class, to_type->index, to_pin_class, direct->x_offset, direct->y_offset, direct_connect_delay); - } else { - ++missing_paths; - } - - //Record that we've sampled this pair of source and sink nodes - sampled_rr_pairs.insert({src_rr, sink_rr}); - } - - VTR_LOGV_WARN(missing_instances > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no instances of this direct found)\n", missing_instances, direct->name.c_str()); - VTR_LOGV_WARN(missing_paths > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no routing path found)\n", missing_paths, direct->name.c_str()); - } -} - -bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node) { - //Returns true if there is a directconnect between the two RR nodes - // - //This is checked by looking for a SOURCE -> OPIN -> IPIN -> SINK path - //which starts at src_rr_node and ends at sink_rr_node - auto& device_ctx = g_vpr_ctx.device(); - const auto& rr_graph = device_ctx.rr_graph; - - VTR_ASSERT(rr_graph.node_type(src_rr_node) == SOURCE && rr_graph.node_type(sink_rr_node) == SINK); - - //TODO: This is a constant depth search, but still may be too slow - for (t_edge_size i_src_edge = 0; i_src_edge < rr_graph.num_edges(src_rr_node); ++i_src_edge) { - RRNodeId opin_rr_node = rr_graph.edge_sink_node(src_rr_node, i_src_edge); - - if (rr_graph.node_type(opin_rr_node) != OPIN) continue; - - for (t_edge_size i_opin_edge = 0; i_opin_edge < rr_graph.num_edges(opin_rr_node); ++i_opin_edge) { - RRNodeId ipin_rr_node = rr_graph.edge_sink_node(opin_rr_node, i_opin_edge); - if (rr_graph.node_type(ipin_rr_node) != IPIN) continue; - - for (t_edge_size i_ipin_edge = 0; i_ipin_edge < rr_graph.num_edges(ipin_rr_node); ++i_ipin_edge) { - if (sink_rr_node == rr_graph.edge_sink_node(ipin_rr_node, i_ipin_edge)) { - return true; - } - } - } - } - return false; -} diff --git a/vpr/src/place/timing_place_lookup.h b/vpr/src/place/timing_place_lookup.h deleted file mode 100644 index fba3f470483..00000000000 --- a/vpr/src/place/timing_place_lookup.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef TIMING_PLACE_LOOKUP_H -#define TIMING_PLACE_LOOKUP_H -#include "place_delay_model.h" - -std::unique_ptr compute_place_delay_model(const t_placer_opts& placer_opts, - const t_router_opts& router_opts, - const Netlist<>& net_list, - t_det_routing_arch* det_routing_arch, - std::vector& segment_inf, - t_chan_width_dist chan_width_dist, - const std::vector& directs, - bool is_flat); - -std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type); - -bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node); - -#endif diff --git a/vpr/src/place/verify_placement.cpp b/vpr/src/place/verify_placement.cpp index 9e9dd6fbcd8..b40b55e1d6c 100644 --- a/vpr/src/place/verify_placement.cpp +++ b/vpr/src/place/verify_placement.cpp @@ -18,6 +18,7 @@ #include "device_grid.h" #include "partition_region.h" #include "physical_types.h" +#include "physical_types_util.h" #include "place_macro.h" #include "vpr_context.h" #include "vpr_types.h" @@ -63,8 +64,7 @@ static unsigned check_block_placement_consistency(const BlkLocRegistry& blk_loc_ // and that it has no valid clusters placed at this location. // TODO: Eventually it should be made impossible to place blocks // at these locations. - if (device_grid.get_width_offset(tile_loc) != 0 || - device_grid.get_height_offset(tile_loc) != 0) { + if (device_grid.get_width_offset(tile_loc) != 0 || device_grid.get_height_offset(tile_loc) != 0) { // Usage must be 0 if (grid_blocks.get_usage(tile_loc) != 0) { VTR_LOG_ERROR( @@ -171,8 +171,8 @@ static unsigned check_block_placement_consistency(const BlkLocRegistry& blk_loc_ * * @return The number of errors in the macro placement. */ -static unsigned check_macro_placement_consistency(const BlkLocRegistry& blk_loc_registry) { - const PlaceMacros& pl_macros = blk_loc_registry.place_macros(); +static unsigned check_macro_placement_consistency(const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& pl_macros) { const auto& block_locs = blk_loc_registry.block_locs(); const auto& grid_blocks = blk_loc_registry.grid_blocks(); @@ -247,6 +247,7 @@ static unsigned check_placement_floorplanning(const BlkLocRegistry& blk_loc_regi } unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, const ClusteredNetlist& clb_nlist, const DeviceGrid& device_grid, const vtr::vector& cluster_constraints) { @@ -264,7 +265,7 @@ unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, // FIXME: Should we be checking the macro consistency at all? Does the // router use the pl_macros? If not this should be removed from this // method and only used when the macro placement is actually used. - num_errors += check_macro_placement_consistency(blk_loc_registry); + num_errors += check_macro_placement_consistency(blk_loc_registry, place_macros); // Check that the floorplanning is observed. num_errors += check_placement_floorplanning(blk_loc_registry, @@ -277,8 +278,8 @@ unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, unsigned verify_placement(const VprContext& ctx) { // Verify the placement within the given context. return verify_placement(ctx.placement().blk_loc_registry(), + *ctx.placement().place_macros, ctx.clustering().clb_nlist, ctx.device().grid, ctx.floorplanning().cluster_constraints); } - diff --git a/vpr/src/place/verify_placement.h b/vpr/src/place/verify_placement.h index 1bee823ea5e..2a3236d3b4c 100644 --- a/vpr/src/place/verify_placement.h +++ b/vpr/src/place/verify_placement.h @@ -22,6 +22,7 @@ class ClusterBlockId; class ClusteredNetlist; class DeviceGrid; class PartitionRegion; +class PlaceMacros; class VprContext; /** @@ -52,6 +53,7 @@ class VprContext; * * @param blk_loc_registry A registry containing the current placement of * the clusters. + * @param place_macros The place macros for the clustered netlist. * @param clb_nlist The clustered netlist being verified. * @param device_grid The device grid being verified over. * @param cluster_constraints The constrained regions that each cluster is @@ -61,6 +63,7 @@ class VprContext; * log messages for each error found. */ unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, + const PlaceMacros& place_macros, const ClusteredNetlist& clb_nlist, const DeviceGrid& device_grid, const vtr::vector& cluster_constraints); @@ -78,4 +81,3 @@ unsigned verify_placement(const BlkLocRegistry& blk_loc_registry, * @param ctx The global VPR context variable found in g_vpr_ctx. */ unsigned verify_placement(const VprContext& ctx); - diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index e899935864a..669133f5a01 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -26,13 +26,12 @@ #include #include #include -#include +#include "physical_types_util.h" #include "vtr_util.h" #include "vtr_path.h" #include "vtr_log.h" #include "vtr_assert.h" -#include "vtr_memory.h" #include "power.h" #include "power_components.h" @@ -44,7 +43,6 @@ #include "physical_types.h" #include "globals.h" -#include "rr_graph.h" #include "vpr_utils.h" /************************* DEFINES **********************************/ @@ -164,9 +162,9 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra } if (pb) { - AtomBlockId blk_id = atom_ctx.lookup.pb_atom(pb); + AtomBlockId blk_id = atom_ctx.lookup().atom_pb_bimap().pb_atom(pb); SRAM_values = alloc_SRAM_values_from_truth_table(LUT_size, - atom_ctx.nlist.block_truth_table(blk_id)); + atom_ctx.netlist().block_truth_table(blk_id)); } else { SRAM_values = alloc_SRAM_values_from_truth_table(LUT_size, AtomNetlist::TruthTable()); } @@ -810,7 +808,7 @@ static void power_usage_routing(t_power_usage* power_usage, /* Populate net indices into rr graph */ for (auto net_id : cluster_ctx.clb_nlist.nets()) { - ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net_id, is_flat); + ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net_id, is_flat); if (!route_ctx.route_trees[parent_id]) continue; for (auto& rt_node : route_ctx.route_trees[parent_id].value().all_nodes()) { @@ -821,7 +819,7 @@ static void power_usage_routing(t_power_usage* power_usage, /* Populate net indices into rr graph */ for (auto net_id : cluster_ctx.clb_nlist.nets()) { - ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net_id, is_flat); + ParentNetId parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net_id, is_flat); if (!route_ctx.route_trees[parent_id]) continue; for (auto& rt_node : route_ctx.route_trees[parent_id].value().all_nodes()) { @@ -923,7 +921,7 @@ static void power_usage_routing(t_power_usage* power_usage, C_wire = wire_length * rr_graph.rr_segments(RRSegmentId(seg_index)).Cmetal; //(double)power_ctx.commonly_used->tile_length); if (node_fan_in == 0) { - continue; // Bypass some nodes with 0 fan-in + continue; // Bypass some nodes with 0 fan-in } VTR_ASSERT(node_power->selected_input < node_fan_in); @@ -1201,8 +1199,8 @@ void power_routing_init(const t_det_routing_arch* routing_arch) { power_ctx.clb_net_power.resize(cluster_ctx.clb_nlist.nets().size()); } for (auto net_id : cluster_ctx.clb_nlist.nets()) { - power_ctx.clb_net_power[net_id].probability = power_ctx.atom_net_power[atom_ctx.lookup.atom_net(net_id)].probability; - power_ctx.clb_net_power[net_id].density = power_ctx.atom_net_power[atom_ctx.lookup.atom_net(net_id)].density; + power_ctx.clb_net_power[net_id].probability = power_ctx.atom_net_power[atom_ctx.lookup().atom_net(net_id)].probability; + power_ctx.clb_net_power[net_id].density = power_ctx.atom_net_power[atom_ctx.lookup().atom_net(net_id)].density; } /* Initialize RR Graph Structures */ diff --git a/vpr/src/power/power_components.h b/vpr/src/power/power_components.h index dd235450603..3faa7b7b641 100644 --- a/vpr/src/power/power_components.h +++ b/vpr/src/power/power_components.h @@ -38,7 +38,7 @@ */ #define POWER_LUT_SLOW #if (!(defined(POWER_LUT_SLOW) || defined(POWER_LUT_FAST))) -# define POWER_LUT_SLOW +#define POWER_LUT_SLOW #endif /************************* ENUMS ************************************/ diff --git a/vpr/src/route/DecompNetlistRouter.tpp b/vpr/src/route/DecompNetlistRouter.tpp index 47de291a14c..228cf428ef6 100644 --- a/vpr/src/route/DecompNetlistRouter.tpp +++ b/vpr/src/route/DecompNetlistRouter.tpp @@ -26,7 +26,7 @@ inline RouteIterResults DecompNetlistRouter::route_netlist(int itry, f /* Organize netlist into a PartitionTree. * Nets in a given level of nodes are guaranteed to not have any overlapping bounding boxes, so they can be routed in parallel. */ - if(!_tree){ + if (!_tree) { _tree = PartitionTree(_net_list); PartitionTreeDebug::log("Iteration " + std::to_string(itry) + ": built partition tree in " + std::to_string(timer.elapsed_sec()) + " s"); } @@ -449,8 +449,8 @@ inline bool is_close_to_cutline(RRNodeId inode, Axis cutline_axis, int cutline_p const auto& rr_graph = device_ctx.rr_graph; vtr::Rect tile_bb = device_ctx.grid.get_tile_bb({rr_graph.node_xlow(inode), - rr_graph.node_ylow(inode), - rr_graph.node_layer(inode)}); + rr_graph.node_ylow(inode), + rr_graph.node_layer(inode)}); /* Cutlines are considered to be at x + 0.5, set a thickness of +1 here by checking for equality */ if (cutline_axis == Axis::X) { @@ -466,8 +466,8 @@ inline bool is_close_to_bb(RRNodeId inode, const t_bb& bb, int thickness) { const auto& rr_graph = device_ctx.rr_graph; vtr::Rect tile_bb = device_ctx.grid.get_tile_bb({rr_graph.node_xlow(inode), - rr_graph.node_ylow(inode), - rr_graph.node_layer(inode)}); + rr_graph.node_ylow(inode), + rr_graph.node_layer(inode)}); int xlow = tile_bb.xmin() - thickness; int ylow = tile_bb.ymin() - thickness; @@ -686,9 +686,9 @@ vtr::dynamic_bitset<> DecompNetlistRouter::get_decomposition_mask_vnet if (inside_bb(tree.root().inode, vnet.clipped_bb)) { /* We have source, no need to sample after reduction in most cases */ bool is_reduced = get_reduction_mask_vnet_with_source(vnet, node.cutline_axis, node.cutline_pos, out); bool source_on_cutline = is_close_to_cutline(tree.root().inode, node.cutline_axis, node.cutline_pos, 1); - if (!is_reduced || source_on_cutline){ + if (!is_reduced || source_on_cutline) { convex_hull_downsample(vnet.net_id, vnet.clipped_bb, out); - } + } } else { int reduced_sides = get_reduction_mask_vnet_no_source(vnet, node.cutline_axis, node.cutline_pos, out); if (reduced_sides < 2) { diff --git a/vpr/src/route/NestedNetlistRouter.h b/vpr/src/route/NestedNetlistRouter.h new file mode 100644 index 00000000000..6870842af8f --- /dev/null +++ b/vpr/src/route/NestedNetlistRouter.h @@ -0,0 +1,134 @@ +#pragma once + +/** @file Nested parallel case for NetlistRouter */ +#include "netlist_routers.h" +#include "vtr_optional.h" +#include "vtr_thread_pool.h" +#include + +/* Add cmd line option for this later */ +constexpr int MAX_THREADS = 4; + +/** Nested parallel impl for NetlistRouter. + * + * Calls a parallel ConnectionRouter for route_net to extract even more parallelism. + * The main reason why this is a different router instead of templating NetlistRouter + * on ConnectionRouter is this router does not use TBB. The scheduling performance is + * worse, but it can wait in individual tasks now (which is not possible with TBB). + * + * Holds enough context members to glue together ConnectionRouter and net routing functions, + * such as \ref route_net. Keeps the members in thread-local storage where needed, + * i.e. ConnectionRouters and RouteIterResults-es. + * See \ref route_net. */ +template +class NestedNetlistRouter : public NetlistRouter { + public: + NestedNetlistRouter( + const Netlist<>& net_list, + const RouterLookahead* router_lookahead, + const t_router_opts& router_opts, + CBRR& connections_inf, + NetPinsMatrix& net_delay, + const ClusteredPinAtomPinsLookup& netlist_pin_lookup, + std::shared_ptr timing_info, + NetPinTimingInvalidator* pin_timing_invalidator, + route_budgets& budgeting_inf, + const RoutingPredictor& routing_predictor, + const vtr::vector>>& choking_spots, + bool is_flat) + : _net_list(net_list) + , _router_lookahead(router_lookahead) + , _router_opts(router_opts) + , _connections_inf(connections_inf) + , _net_delay(net_delay) + , _netlist_pin_lookup(netlist_pin_lookup) + , _timing_info(timing_info) + , _pin_timing_invalidator(pin_timing_invalidator) + , _budgeting_inf(budgeting_inf) + , _routing_predictor(routing_predictor) + , _choking_spots(choking_spots) + , _is_flat(is_flat) + , _thread_pool(MAX_THREADS) {} + ~NestedNetlistRouter() {} + + /** Run a single iteration of netlist routing for this->_net_list. This usually means calling + * \ref route_net for each net, which will handle other global updates. + * \return RouteIterResults for this iteration. */ + RouteIterResults route_netlist(int itry, float pres_fac, float worst_neg_slack); + /** Inform the PartitionTree of the nets with updated bounding boxes */ + void handle_bb_updated_nets(const std::vector& nets); + + /** Set rcv_enabled for each ConnectionRouter this is managing */ + void set_rcv_enabled(bool x); + /** Set timing_info for each ConnectionRouter this is managing */ + void set_timing_info(std::shared_ptr timing_info); + + private: + /** Route all nets in a PartitionTree node and add its children to the task queue. */ + void route_partition_tree_node(PartitionTreeNode& node); + + ConnectionRouter _make_router(const RouterLookahead* router_lookahead, bool is_flat) { + auto& device_ctx = g_vpr_ctx.device(); + auto& route_ctx = g_vpr_ctx.mutable_routing(); + + return ConnectionRouter( + device_ctx.grid, + *router_lookahead, + device_ctx.rr_graph.rr_nodes(), + &device_ctx.rr_graph, + device_ctx.rr_rc_data, + device_ctx.rr_graph.rr_switch(), + route_ctx.rr_node_route_inf, + is_flat); + } + + /* Context fields. Most of them will be forwarded to route_net (see route_net.tpp) */ + const Netlist<>& _net_list; + const RouterLookahead* _router_lookahead; + const t_router_opts& _router_opts; + CBRR& _connections_inf; + NetPinsMatrix& _net_delay; + const ClusteredPinAtomPinsLookup& _netlist_pin_lookup; + std::shared_ptr _timing_info; + NetPinTimingInvalidator* _pin_timing_invalidator; + route_budgets& _budgeting_inf; + const RoutingPredictor& _routing_predictor; + const vtr::vector>>& _choking_spots; + bool _is_flat; + + /** Cached routing parameters for current iteration (inputs to \see route_netlist()) */ + int _itry; + float _pres_fac; + float _worst_neg_slack; + + /** The partition tree. Holds the groups of nets for each partition */ + vtr::optional _tree; + + /** Thread pool for parallel routing. See vtr_thread_pool.h for implementation */ + vtr::thread_pool _thread_pool; + + /* Thread-local storage. + * These are maps because thread::id is a random integer instead of 1, 2, ... */ + std::unordered_map> _routers_th; + std::unordered_map _results_th; + std::mutex _storage_mutex; + + /** Get a thread-local ConnectionRouter. We lock the id->router lookup, but this is + * accessed once per partition so the overhead should be small */ + ConnectionRouter& get_thread_router() { + auto id = std::this_thread::get_id(); + std::lock_guard lock(_storage_mutex); + if (!_routers_th.count(id)) { + _routers_th.emplace(id, _make_router(_router_lookahead, _is_flat)); + } + return _routers_th.at(id); + } + + RouteIterResults& get_thread_results() { + auto id = std::this_thread::get_id(); + std::lock_guard lock(_storage_mutex); + return _results_th[id]; + } +}; + +#include "NestedNetlistRouter.tpp" diff --git a/vpr/src/route/NestedNetlistRouter.tpp b/vpr/src/route/NestedNetlistRouter.tpp new file mode 100644 index 00000000000..333be28ea3b --- /dev/null +++ b/vpr/src/route/NestedNetlistRouter.tpp @@ -0,0 +1,141 @@ +#pragma once + +/** @file Impls for ParallelNetlistRouter */ + +#include +#include "netlist_routers.h" +#include "route_net.h" +#include "vtr_time.h" + +template +inline RouteIterResults NestedNetlistRouter::route_netlist(int itry, float pres_fac, float worst_neg_slack) { + /* Reset results for each thread */ + for (auto& [_, results] : _results_th) { + results = RouteIterResults(); + } + + /* Set the routing parameters: they won't change until the next call and that saves us the trouble of passing them around */ + _itry = itry; + _pres_fac = pres_fac; + _worst_neg_slack = worst_neg_slack; + + /* Organize netlist into a PartitionTree. + * Nets in a given level of nodes are guaranteed to not have any overlapping bounding boxes, so they can be routed in parallel. */ + vtr::Timer timer; + if (!_tree) { + _tree = PartitionTree(_net_list); + PartitionTreeDebug::log("Iteration " + std::to_string(itry) + ": built partition tree in " + std::to_string(timer.elapsed_sec()) + " s"); + } + + /* Push a single route_partition_tree_node task to the thread pool, + * which will recursively schedule the rest of the tree */ + _thread_pool.schedule_work([this]() { + route_partition_tree_node(_tree->root()); + }); + + /* Wait for all tasks in the thread pool to complete */ + _thread_pool.wait_for_all(); + + PartitionTreeDebug::log("Routing all nets took " + std::to_string(timer.elapsed_sec()) + " s"); + + /* Combine results from threads */ + RouteIterResults out; + for (auto& [_, results] : _results_th) { + out.stats.combine(results.stats); + out.rerouted_nets.insert(out.rerouted_nets.end(), results.rerouted_nets.begin(), results.rerouted_nets.end()); + out.bb_updated_nets.insert(out.bb_updated_nets.end(), results.bb_updated_nets.begin(), results.bb_updated_nets.end()); + out.is_routable &= results.is_routable; + } + return out; +} + +template +void NestedNetlistRouter::route_partition_tree_node(PartitionTreeNode& node) { + auto& route_ctx = g_vpr_ctx.mutable_routing(); + + /* node.nets is an unordered set, copy into vector to sort */ + std::vector nets(node.nets.begin(), node.nets.end()); + + /* Sort so net with most sinks is routed first. */ + std::stable_sort(nets.begin(), nets.end(), [&](ParentNetId id1, ParentNetId id2) -> bool { + return _net_list.net_sinks(id1).size() > _net_list.net_sinks(id2).size(); + }); + + vtr::Timer timer; + + /* Route all nets in this node serially */ + for (auto net_id : nets) { + auto& results = get_thread_results(); + auto& router = get_thread_router(); + + auto flags = route_net( + router, + _net_list, + net_id, + _itry, + _pres_fac, + _router_opts, + _connections_inf, + results.stats, + _net_delay, + _netlist_pin_lookup, + _timing_info.get(), + _pin_timing_invalidator, + _budgeting_inf, + _worst_neg_slack, + _routing_predictor, + _choking_spots[net_id], + _is_flat, + route_ctx.route_bb[net_id]); + + if (!flags.success && !flags.retry_with_full_bb) { + /* Disconnected RRG and ConnectionRouter doesn't think growing the BB will work */ + results.is_routable = false; + return; + } + if (flags.retry_with_full_bb) { + /* ConnectionRouter thinks we should grow the BB. Do that and leave this net unrouted for now */ + route_ctx.route_bb[net_id] = full_device_bb(); + results.bb_updated_nets.push_back(net_id); + continue; + } + if (flags.was_rerouted) { + results.rerouted_nets.push_back(net_id); + } + } + + PartitionTreeDebug::log("Node with " + std::to_string(node.nets.size()) + + " nets and " + std::to_string(node.vnets.size()) + + " virtual nets routed in " + std::to_string(timer.elapsed_sec()) + + " s"); + + /* Schedule child nodes as new tasks */ + if (node.left && node.right) { + _thread_pool.schedule_work([this, left = node.left.get()]() { + route_partition_tree_node(*left); + }); + _thread_pool.schedule_work([this, right = node.right.get()]() { + route_partition_tree_node(*right); + }); + } else { + VTR_ASSERT(!node.left && !node.right); // there shouldn't be a node with a single branch + } +} + +template +void NestedNetlistRouter::handle_bb_updated_nets(const std::vector& nets) { + VTR_ASSERT(_tree); + _tree->update_nets(nets); +} + +template +void NestedNetlistRouter::set_rcv_enabled(bool x) { + for (auto& [_, router] : _routers_th) { + router.set_rcv_enabled(x); + } +} + +template +void NestedNetlistRouter::set_timing_info(std::shared_ptr timing_info) { + _timing_info = timing_info; +} diff --git a/vpr/src/route/ParallelNetlistRouter.tpp b/vpr/src/route/ParallelNetlistRouter.tpp index 1268ed6030e..c845be8518d 100644 --- a/vpr/src/route/ParallelNetlistRouter.tpp +++ b/vpr/src/route/ParallelNetlistRouter.tpp @@ -22,7 +22,7 @@ inline RouteIterResults ParallelNetlistRouter::route_netlist(int itry, /* Organize netlist into a PartitionTree. * Nets in a given level of nodes are guaranteed to not have any overlapping bounding boxes, so they can be routed in parallel. */ vtr::Timer timer; - if(!_tree){ + if (!_tree) { _tree = PartitionTree(_net_list); PartitionTreeDebug::log("Iteration " + std::to_string(itry) + ": built partition tree in " + std::to_string(timer.elapsed_sec()) + " s"); } diff --git a/vpr/src/route/annotate_routing.cpp b/vpr/src/route/annotate_routing.cpp index 42b798d4d02..6f20d2e873d 100644 --- a/vpr/src/route/annotate_routing.cpp +++ b/vpr/src/route/annotate_routing.cpp @@ -14,8 +14,8 @@ #include "annotate_routing.h" vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, - const DeviceContext& device_ctx, - const bool& verbose) { + const DeviceContext& device_ctx, + const bool& verbose) { size_t counter = 0; vtr::ScopedStartFinishTimer timer("Annotating rr_node with routed nets"); @@ -35,7 +35,7 @@ vtr::vector annotate_rr_node_nets(const ClusteringContex } auto& tree = get_route_tree_from_cluster_net_id(net_id); - if(!tree) + if (!tree) continue; for (auto& rt_node : tree->all_nodes()) { diff --git a/vpr/src/route/annotate_routing.h b/vpr/src/route/annotate_routing.h index cf548e1e0fe..d12bf313a74 100644 --- a/vpr/src/route/annotate_routing.h +++ b/vpr/src/route/annotate_routing.h @@ -11,7 +11,7 @@ * - Unmapped rr_node will use invalid ids *******************************************************************/ vtr::vector annotate_rr_node_nets(const ClusteringContext& cluster_ctx, - const DeviceContext& device_ctx, - const bool& verbose); + const DeviceContext& device_ctx, + const bool& verbose); #endif diff --git a/vpr/src/route/build_switchblocks.cpp b/vpr/src/route/build_switchblocks.cpp index c203aa001f7..a0dbe35bb1c 100644 --- a/vpr/src/route/build_switchblocks.cpp +++ b/vpr/src/route/build_switchblocks.cpp @@ -141,6 +141,7 @@ #include "physical_types.h" #include "parse_switchblocks.h" #include "vtr_expr_eval.h" +#include "rr_types.h" using vtr::FormulaParser; using vtr::t_formula_data; @@ -431,8 +432,8 @@ t_sb_connection_map* alloc_and_load_switchblock_permutations(const t_chan_detail /******** slow switch block computation method; computes switchblocks at each coordinate ********/ /* iterate over all the switchblocks specified in the architecture */ - for (auto sb: switchblocks) { - + for (auto sb : switchblocks) { + /* verify that switchblock type matches specified directionality -- currently we have to stay consistent */ if (directionality != sb.directionality) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "alloc_and_load_switchblock_connections: Switchblock %s does not match directionality of architecture\n", sb.name.c_str()); @@ -505,10 +506,10 @@ static bool sb_not_here(const DeviceGrid& grid, const std::vector& inter_c } break; case e_sb_location::E_XY_SPECIFIED: - if(match_sb_xy(grid, inter_cluster_rr, x, y, layer, sb)) { + if (match_sb_xy(grid, inter_cluster_rr, x, y, layer, sb)) { sb_not_here = false; } - + break; default: VPR_FATAL_ERROR(VPR_ERROR_ARCH, "sb_not_here: unrecognized location enum: %d\n", sb.location); @@ -564,18 +565,18 @@ static bool match_sb_xy(const DeviceGrid& grid, const std::vector& inter_c if (!is_prog_routing_avail(grid, inter_cluster_rr, layer)) { return false; } - //if one of sb_x and sb_y is defined, we either know the exact location (x,y) or the exact x location (will apply it to all rows) - //or the exact y location (will apply it to all columns) - if(sb.x != -1 || sb.y != -1){ - if(x == sb.x && y == sb.y){ + //if one of sb_x and sb_y is defined, we either know the exact location (x,y) or the exact x location (will apply it to all rows) + //or the exact y location (will apply it to all columns) + if (sb.x != -1 || sb.y != -1) { + if (x == sb.x && y == sb.y) { return true; - } + } - if(x == sb.x && sb.y == -1){ + if (x == sb.x && sb.y == -1) { return true; } - - if(sb.x == -1 && y == sb.y){ + + if (sb.x == -1 && y == sb.y) { return true; } } @@ -585,12 +586,12 @@ static bool match_sb_xy(const DeviceGrid& grid, const std::vector& inter_c //calculate the appropriate region based on the repeatx/repeaty and current location. //This is to determine whether the given location is part of the current SB specified region with regular expression or not //After region calculation, the current SB will apply to this location if: - // 1) the given (x,y) location falls into the calculated region + // 1) the given (x,y) location falls into the calculated region // *AND* // 2) incrx/incry are respected within the region, this means all locations within the calculated region do - // not necessarily crosspond to the current SB. If incrx/incry is equal to 1, then all locations within the - // calculated region are valid. - + // not necessarily crosspond to the current SB. If incrx/incry is equal to 1, then all locations within the + // calculated region are valid. + //calculate the region int x_reg_step = (sb.reg_x.repeat != 0) ? (x - sb.reg_x.start) / sb.reg_x.repeat : sb.reg_x.start; int y_reg_step = (sb.reg_y.repeat != 0) ? (y - sb.reg_y.start) / sb.reg_y.repeat : sb.reg_y.start; @@ -608,23 +609,23 @@ static bool match_sb_xy(const DeviceGrid& grid, const std::vector& inter_c reg_endy = std::min(reg_endy, int(grid.height() - 1)); //check x coordinate - if (x >= reg_startx && x <= reg_endx){ //should fall into the region + if (x >= reg_startx && x <= reg_endx) { //should fall into the region //we also should respect the incrx //if incrx is not equal to 1, all locations within this region are *NOT* valid - if((x + reg_startx) % sb.reg_x.incr == 0){ + if ((x + reg_startx) % sb.reg_x.incr == 0) { //valid x coordinate, check for y value - if(y >= reg_starty && y <= reg_endy){ + if (y >= reg_starty && y <= reg_endy) { //check for incry, similar as incrx - if((y + reg_starty) % sb.reg_y.incr == 0){ + if ((y + reg_starty) % sb.reg_y.incr == 0) { //both x and y are valid return true; } } - } + } } //if reach here, we don't have sb in this location - return false; + return false; } /* Counts the number of wires in each wire type in the specified channel */ @@ -991,7 +992,7 @@ static void compute_wireconn_connections( } else { VTR_ASSERT(from_layer != to_layer); sb_edge.switch_ind = to_chan_details[to_x][to_y][to_wire].arch_wire_switch(); - sb_edge.switch_ind_between_layers = to_chan_details[to_x][to_y][to_wire].arch_opin_between_dice_switch(); + sb_edge.switch_ind_between_layers = to_chan_details[to_x][to_y][to_wire].arch_inter_die_switch(); } VTR_LOGV(verbose, " make_conn: %d -> %d switch=%d\n", sb_edge.from_wire, sb_edge.to_wire, sb_edge.switch_ind); diff --git a/vpr/src/route/build_switchblocks.h b/vpr/src/route/build_switchblocks.h index d9f283dfd4f..917bd16620b 100644 --- a/vpr/src/route/build_switchblocks.h +++ b/vpr/src/route/build_switchblocks.h @@ -7,8 +7,8 @@ #include "physical_types.h" #include "vpr_types.h" #include "device_grid.h" - #include "vtr_random.h" +#include "rr_types.h" /************ Classes, structs, typedefs ************/ @@ -92,9 +92,9 @@ struct t_switchblock_edge { short to_wire_layer; }; -/* Switchblock connections are made as [x][y][from_side][to_side][from_wire_ind]. +/* Switchblock connections are made as [x][y][from_layer][from_side][to_side][from_wire_idx]. * The Switchblock_Lookup class specifies these dimensions. - * Furthermore, a source_wire at a given 5-d coordinate may connect to multiple destination wires so the value + * Furthermore, a source_wire at a given 6-d coordinate may connect to multiple destination wires so the value * of the map is a vector of destination wires. * A matrix specifying connections for all switchblocks in an FPGA would be sparse and possibly very large * so we use an unordered map to take advantage of the sparsity. */ diff --git a/vpr/src/route/cb_metrics.cpp b/vpr/src/route/cb_metrics.cpp index a1fa4294179..6664bd91d41 100644 --- a/vpr/src/route/cb_metrics.cpp +++ b/vpr/src/route/cb_metrics.cpp @@ -19,28 +19,22 @@ #include #include -#include #include #include #include -#include -#include -#include -#include #include #include #include +#include "physical_types_util.h" #include "vtr_random.h" -#include "vtr_assert.h" #include "vtr_log.h" #include "vtr_math.h" #include "vpr_types.h" #include "vpr_error.h" -#include "vpr_utils.h" #include "cb_metrics.h" @@ -170,7 +164,6 @@ void adjust_cb_metric(const e_metric metric, const float target, const float tar get_conn_block_metrics(block_type, pin_to_track_connections, num_segments, segment_inf, pin_type, Fc_array, chan_width_inf, &cb_metrics); - vtr::RngContainer rng(0); /* now run the annealer to adjust the desired metric towards the target value */ bool success = annealer(metric, nodes_per_chan, block_type, pin_type, Fc, num_pin_type_pins, target, @@ -626,7 +619,7 @@ static void get_pin_locations(const t_physical_tile_type_ptr block_type, const e } } /* sort the vector at the current side in increasing order, for good measure */ - std::stable_sort(pin_locations->at(iside).begin(), pin_locations->at(iside).end()); + std::stable_sort(pin_locations->at(iside).begin(), pin_locations->at(iside).end()); } } /* now we have a vector of vectors [0..3][0..num_pins_on_this_side] specifying which pins are on which side */ diff --git a/vpr/src/route/channel_stats.cpp b/vpr/src/route/channel_stats.cpp index 065a6e5b7a0..f95275db9f4 100644 --- a/vpr/src/route/channel_stats.cpp +++ b/vpr/src/route/channel_stats.cpp @@ -36,7 +36,7 @@ void print_channel_stats(bool is_flat) { for (size_t x = 0; x < device_ctx.grid.width() - 1; ++x) { for (size_t y = 0; y < device_ctx.grid.height() - 1; ++y) { float chanx_util = routing_util(chanx_usage[x][y], chanx_avail[x][y]); - float chany_util = routing_util(chanx_usage[x][y], chanx_avail[x][y]); + float chany_util = routing_util(chany_usage[x][y], chany_avail[x][y]); for (float util : {chanx_util, chany_util}) { //Record peak utilization diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index e436018fe52..ab2aad9a281 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -1,20 +1,19 @@ -#include +#include "check_route.h" + +#include "physical_types_util.h" #include "route_common.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_memory.h" #include "vtr_time.h" #include "vpr_types.h" #include "vpr_error.h" #include "globals.h" -#include "route_export.h" -#include "check_route.h" + #include "rr_graph.h" #include "check_rr_graph.h" -#include "read_xml_arch_file.h" #include "route_tree.h" /******************** Subroutines local to this module **********************/ @@ -39,11 +38,32 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_ enum e_route_type route_type, bool is_flat); +/** + * Checks that all non-configurable edges are in a legal configuration. + * @param net_list The netlist whose routing is to be checked. + * @param is_flat True if flat routing is enabled; otherwise false. + */ static void check_all_non_configurable_edges(const Netlist<>& net_list, bool is_flat); + +/** + * @brief Checks that the specified routing is legal with respect to non-configurable edges. + * For routing to be valid, if any non-configurable edge is used, all nodes in the same set + * and the required connecting edges in the set must also be used. + * + * @param net_list A reference to the netlist. + * @param net The net id for which the check is done. + * @param non_configurable_rr_sets Node and edge sets that constitute non-configurable RR sets. + * @param rrnode_set_id Specifies which RR sets each RR node is part of. These indices can be used to + * access elements of node_sets and edge_sets in non_configurable_rr_sets. + * @param is_flat Indicates whether flat routing is enabled. + * @return True if check is done successfully; otherwise false. + */ static bool check_non_configurable_edges(const Netlist<>& net_list, ParentNetId net, const t_non_configurable_rr_sets& non_configurable_rr_sets, + const vtr::vector& rrnode_set_id, bool is_flat); + static void check_net_for_stubs(const Netlist<>& net_list, ParentNetId net, bool is_flat); @@ -65,13 +85,9 @@ void check_route(const Netlist<>& net_list, return; } - int max_pins; - unsigned int ipin; - bool valid, connects; - - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; - auto& route_ctx = g_vpr_ctx.routing(); + const auto& route_ctx = g_vpr_ctx.routing(); const size_t num_switches = rr_graph.num_rr_switches(); @@ -83,7 +99,7 @@ void check_route(const Netlist<>& net_list, * is a successful routing, but I want to double check it here. */ recompute_occupancy_from_scratch(net_list, is_flat); - valid = feasible_routing(); + const bool valid = feasible_routing(); if (valid == false) { VPR_ERROR(VPR_ERROR_ROUTE, "Error in check_route -- routing resources are overused.\n"); @@ -95,7 +111,7 @@ void check_route(const Netlist<>& net_list, is_flat); } - max_pins = 0; + int max_pins = 0; for (auto net_id : net_list.nets()) max_pins = std::max(max_pins, (int)net_list.net_pins(net_id).size()); @@ -129,7 +145,7 @@ void check_route(const Netlist<>& net_list, check_switch(rt_node, num_switches); if (rt_node.parent()) { - connects = check_adjacent(rt_node.parent()->inode, rt_node.inode, is_flat); + bool connects = check_adjacent(rt_node.parent()->inode, rt_node.inode, is_flat); if (!connects) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_route: found non-adjacent segments in traceback while checking net %d:\n" @@ -154,7 +170,7 @@ void check_route(const Netlist<>& net_list, num_sinks, net_list.net_sinks(net_id).size()); } - for (ipin = 0; ipin < net_list.net_pins(net_id).size(); ipin++) { + for (size_t ipin = 0; ipin < net_list.net_pins(net_id).size(); ipin++) { if (pin_done[ipin] == false) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_route: net %zu does not connect to pin %d.\n", size_t(net_id), ipin); @@ -194,7 +210,7 @@ static void check_sink(const Netlist<>& net_list, inode, net_list.net_name(net_id).c_str(), size_t(net_id)); } - VTR_ASSERT(!pin_done[net_pin_index]); /* Should not have found a routed cnnection to it before */ + VTR_ASSERT(!pin_done[net_pin_index]); /* Should not have found a routed connection to it before */ pin_done[net_pin_index] = true; } @@ -464,8 +480,8 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster return true; } else { - VTR_ASSERT(to_type == IPIN); - num_adj += 1; + VTR_ASSERT(to_type == IPIN); + num_adj += 1; } break; @@ -614,43 +630,71 @@ static void check_node_and_range(RRNodeId inode, is_flat); } -//Checks that all non-configurable edges are in a legal configuration -//This check is slow, so it has been moved out of check_route() static void check_all_non_configurable_edges(const Netlist<>& net_list, bool is_flat) { + const auto& rr_graph = g_vpr_ctx.device().rr_graph; + vtr::ScopedStartFinishTimer timer("Checking to ensure non-configurable edges are legal"); - auto non_configurable_rr_sets = identify_non_configurable_rr_sets(); + const t_non_configurable_rr_sets non_configurable_rr_sets = identify_non_configurable_rr_sets(); + + // Specifies which RR set each node is part of. + vtr::vector rrnode_set_ids(rr_graph.num_nodes(), -1); + + const size_t num_non_cfg_rr_sets = non_configurable_rr_sets.node_sets.size(); + + // Populate rrnode_set_ids + for (size_t non_cfg_rr_set_id = 0; non_cfg_rr_set_id < num_non_cfg_rr_sets; non_cfg_rr_set_id++) { + const std::set& node_set = non_configurable_rr_sets.node_sets[non_cfg_rr_set_id]; + for (const RRNodeId node_id : node_set) { + VTR_ASSERT_SAFE(rrnode_set_ids[node_id] == -1); + rrnode_set_ids[node_id] = (int)non_cfg_rr_set_id; + } + } for (auto net_id : net_list.nets()) { check_non_configurable_edges(net_list, net_id, non_configurable_rr_sets, + rrnode_set_ids, is_flat); } } -// Checks that the specified routing is legal with respect to non-configurable edges -// -//For routing to be legal if *any* non-configurable edge is used, so must *all* -//other non-configurable edges in the same set static bool check_non_configurable_edges(const Netlist<>& net_list, ParentNetId net, const t_non_configurable_rr_sets& non_configurable_rr_sets, + const vtr::vector& rrnode_set_id, bool is_flat) { const auto& device_ctx = g_vpr_ctx.device(); - auto& route_ctx = g_vpr_ctx.mutable_routing(); + const auto& route_ctx = g_vpr_ctx.routing(); if (!route_ctx.route_trees[net]) // no routing return true; - // Collect all the edges used by this net's routing + // Collect all the nodes, edges, and non-configurable RR set ids used by this net's routing std::set routing_edges; std::set routing_nodes; - for (auto& rt_node : route_ctx.route_trees[net].value().all_nodes()) { + std::set routing_non_configurable_rr_set_ids; + for (const RouteTreeNode& rt_node : route_ctx.route_trees[net].value().all_nodes()) { routing_nodes.insert(rt_node.inode); if (!rt_node.parent()) continue; t_node_edge edge = {rt_node.parent()->inode, rt_node.inode}; routing_edges.insert(edge); + + if (rrnode_set_id[rt_node.inode] >= 0) { // The node belongs to a non-configurable RR set + routing_non_configurable_rr_set_ids.insert(rrnode_set_id[rt_node.inode]); + } + } + + // Copy used non-configurable RR sets + // This is done to check legality only for used non-configurable RR sets. If a non-configurable RR set + // is not used by a net's routing, it cannot violate the requirements of using that non-configurable RR set. + t_non_configurable_rr_sets used_non_configurable_rr_sets; + used_non_configurable_rr_sets.node_sets.reserve(routing_non_configurable_rr_set_ids.size()); + used_non_configurable_rr_sets.edge_sets.reserve(routing_non_configurable_rr_set_ids.size()); + for (const int set_idx : routing_non_configurable_rr_set_ids) { + used_non_configurable_rr_sets.node_sets.emplace_back(non_configurable_rr_sets.node_sets[set_idx]); + used_non_configurable_rr_sets.edge_sets.emplace_back(non_configurable_rr_sets.edge_sets[set_idx]); } //We need to perform two types of checks: @@ -659,13 +703,13 @@ static bool check_non_configurable_edges(const Netlist<>& net_list, // 2) That all (required) non-configurable edges are used // //We need to check (2) in addition to (1) to ensure that (1) did not pass - //because the nodes 'happend' to be connected together by configurable + //because the nodes 'happened' to be connected together by configurable //routing (to be legal, by definition, they must be connected by //non-configurable routing). - //Check that all nodes in each non-configurable set are full included if any element + //Check that all nodes in each non-configurable set are fully included if any element //within a set is used by the routing - for (const auto& rr_nodes : non_configurable_rr_sets.node_sets) { + for (const auto& rr_nodes : used_non_configurable_rr_sets.node_sets) { //Compute the intersection of the routing and current non-configurable nodes set std::vector intersection; std::set_intersection(routing_nodes.begin(), routing_nodes.end(), @@ -687,7 +731,7 @@ static bool check_non_configurable_edges(const Netlist<>& net_list, routing_nodes.begin(), routing_nodes.end(), std::back_inserter(difference)); - VTR_ASSERT(difference.size() > 0); + VTR_ASSERT(!difference.empty()); std::string msg = vtr::string_fmt( "Illegal routing for net '%s' (#%zu) some " "required non-configurably connected nodes are missing:\n", @@ -704,7 +748,7 @@ static bool check_non_configurable_edges(const Netlist<>& net_list, //Check that any sets of non-configurable RR graph edges are fully included //in the routing, if any of a set's edges are used - for (const auto& rr_edges : non_configurable_rr_sets.edge_sets) { + for (const auto& rr_edges : used_non_configurable_rr_sets.edge_sets) { //Compute the intersection of the routing and current non-configurable edge set std::vector intersection; std::set_intersection(routing_edges.begin(), routing_edges.end(), @@ -717,7 +761,7 @@ static bool check_non_configurable_edges(const Netlist<>& net_list, //Since at least one non-configurable edge is used, to be legal //the full set of non-configurably connected edges must be used. // - //This is somewhat complicted by the fact that non-configurable edges + //This is somewhat complicated by the fact that non-configurable edges //are sometimes bi-directional (e.g. electrical shorts) and so appear //in rr_edges twice (once forward, once backward). Only one of the //paired edges need appear to be correct. @@ -810,9 +854,9 @@ class StubFinder { std::set stub_nodes_; }; -//Cheks for stubs in a net's routing. +//Checks for stubs in a net's routing. // -//Stubs (routing branches which don't connect to SINKs) serve no purpose, and only chew up wiring unecessarily. +//Stubs (routing branches which don't connect to SINKs) serve no purpose, and only chew up wiring unnecessarily. //The only exception are stubs required by non-configurable switches (e.g. shorts). // //We treat any configurable stubs as an error. diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp index d7b0f831e44..5a193a159ad 100644 --- a/vpr/src/route/clock_connection_builders.cpp +++ b/vpr/src/route/clock_connection_builders.cpp @@ -2,11 +2,7 @@ #include "globals.h" #include "arch_util.h" -#include "rr_graph2.h" - -#include "vtr_assert.h" -#include "vtr_log.h" -#include "vtr_error.h" +#include "rr_rc_data.h" #include #include diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp index 40e581a02de..34dccc4ff29 100644 --- a/vpr/src/route/clock_network_builders.cpp +++ b/vpr/src/route/clock_network_builders.cpp @@ -2,9 +2,9 @@ #include "globals.h" +#include "rr_rc_data.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_error.h" void static populate_segment_values(int seg_index, std::string name, diff --git a/vpr/src/route/clock_network_builders.h b/vpr/src/route/clock_network_builders.h index f9983cd85e9..2e73fe211c0 100644 --- a/vpr/src/route/clock_network_builders.h +++ b/vpr/src/route/clock_network_builders.h @@ -113,8 +113,7 @@ class ClockNetwork { t_rr_graph_storage* rr_nodes, RRGraphBuilder& rr_graph_builder, t_rr_edge_info_set* rr_edges_to_create, - int num_segments_x) - = 0; + int num_segments_x) = 0; virtual size_t estimate_additional_nodes(const DeviceGrid& grid) = 0; virtual void map_relative_seg_indices(const t_unified_to_parallel_seg_index& index_map) = 0; }; diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index 8ec7ecc8e2a..664553995a4 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -221,7 +221,7 @@ void ConnectionRouter::timing_driven_route_connection_from_heap(RRNodeId s HeapNode cheapest; while (heap_.try_pop(cheapest)) { // inode with the cheapest total cost in current route tree to be expanded on - const auto& [ new_total_cost, inode ] = cheapest; + const auto& [new_total_cost, inode] = cheapest; update_router_stats(router_stats_, /*is_push=*/false, inode, @@ -303,7 +303,7 @@ vtr::vector ConnectionRouter::timing_driven_find HeapNode cheapest; while (heap_.try_pop(cheapest)) { // inode with the cheapest total cost in current route tree to be expanded on - const auto& [ new_total_cost, inode ] = cheapest; + const auto& [new_total_cost, inode] = cheapest; update_router_stats(router_stats_, /*is_push=*/false, inode, @@ -573,8 +573,7 @@ void ConnectionRouter::timing_driven_add_to_heap(const t_conn_cost_params& // When RCV is enabled, prune based on the RCV-specific total path cost (see // in `compute_node_cost_using_rcv` in `evaluate_timing_driven_node_costs`) // to allow detours to get better QoR. - if ((!rcv_path_manager.is_enabled() && best_back_cost > new_back_cost) || - (rcv_path_manager.is_enabled() && best_total_cost > new_total_cost)) { + if ((!rcv_path_manager.is_enabled() && best_back_cost > new_back_cost) || (rcv_path_manager.is_enabled() && best_total_cost > new_total_cost)) { VTR_LOGV_DEBUG(router_debug_, " Expanding to node %d (%s)\n", to_node, describe_rr_node(device_ctx.rr_graph, device_ctx.grid, @@ -790,12 +789,12 @@ void ConnectionRouter::evaluate_timing_driven_node_costs(RTExploredNode* t //Update total cost float expected_cost = router_lookahead_.get_expected_cost(to->index, target_node, cost_params, to->R_upstream); VTR_LOGV_DEBUG(router_debug_ && !std::isfinite(expected_cost), - " Lookahead from %s (%s) to %s (%s) is non-finite, expected_cost = %f, to->R_upstream = %f\n", - rr_node_arch_name(to->index, is_flat_).c_str(), - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to->index, is_flat_).c_str(), - rr_node_arch_name(target_node, is_flat_).c_str(), - describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(), - expected_cost, to->R_upstream); + " Lookahead from %s (%s) to %s (%s) is non-finite, expected_cost = %f, to->R_upstream = %f\n", + rr_node_arch_name(to->index, is_flat_).c_str(), + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, to->index, is_flat_).c_str(), + rr_node_arch_name(target_node, is_flat_).c_str(), + describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(), + expected_cost, to->R_upstream); total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset); } to->total_cost = total_cost; @@ -876,7 +875,7 @@ void ConnectionRouter::add_route_tree_node_to_heap( describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, inode, is_flat_).c_str()); if (tot_cost > rr_node_route_inf_[inode].path_cost) { - return ; + return; } add_to_mod_list(inode); rr_node_route_inf_[inode].path_cost = tot_cost; @@ -1068,8 +1067,7 @@ static inline void update_router_stats(RouterStats* router_stats, const VibInf* vib; if (!g_vpr_ctx.device().arch->vib_infs.empty()) { vib = g_vpr_ctx.device().vib_grid.get_vib(rr_graph->node_layer(rr_node_id), rr_graph->node_xlow(rr_node_id), rr_graph->node_ylow(rr_node_id)); - } - else { + } else { vib = nullptr; } if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { diff --git a/vpr/src/route/connection_router.h b/vpr/src/route/connection_router.h index cee93384974..0de6d508991 100644 --- a/vpr/src/route/connection_router.h +++ b/vpr/src/route/connection_router.h @@ -51,7 +51,7 @@ class ConnectionRouter : public ConnectionRouterInterface { ~ConnectionRouter() { VTR_LOG("Serial Connection Router is being destroyed. Time spent on path search: %.3f seconds.\n", - std::chrono::duration(path_search_cumulative_time).count()); + std::chrono::duration(path_search_cumulative_time).count()); } // Clear's the modified list. Should be called after reset_path_costs diff --git a/vpr/src/route/connection_router_interface.h b/vpr/src/route/connection_router_interface.h index 62111edc285..96ef278833a 100644 --- a/vpr/src/route/connection_router_interface.h +++ b/vpr/src/route/connection_router_interface.h @@ -59,8 +59,7 @@ class ConnectionRouterInterface { const t_conn_cost_params& cost_params, const t_bb& bounding_box, RouterStats& router_stats, - const ConnectionParameters& conn_params) - = 0; + const ConnectionParameters& conn_params) = 0; /** Finds a path from the route tree rooted at rt_root to sink_node for a * high fanout net. @@ -79,8 +78,7 @@ class ConnectionRouterInterface { const t_bb& bounding_box, const SpatialRouteTreeLookup& spatial_rt_lookup, RouterStats& router_stats, - const ConnectionParameters& conn_params) - = 0; + const ConnectionParameters& conn_params) = 0; // Finds a path from the route tree rooted at rt_root to all sinks // available. @@ -99,8 +97,7 @@ class ConnectionRouterInterface { const t_conn_cost_params& cost_params, const t_bb& bounding_box, RouterStats& router_stats, - const ConnectionParameters& conn_params) - = 0; + const ConnectionParameters& conn_params) = 0; // Sets whether router debug information should be on. virtual void set_router_debug(bool router_debug) = 0; diff --git a/vpr/src/route/d_ary_heap.h b/vpr/src/route/d_ary_heap.h index 5ac59f1eef2..c52cd702d13 100644 --- a/vpr/src/route/d_ary_heap.h +++ b/vpr/src/route/d_ary_heap.h @@ -17,7 +17,7 @@ * to BinaryHeap. This is likely because FourAryHeap has lower tree height, and as we can fit 8 * heap node (each is 8 bytes) on a cache line (commonly 64 bytes on modern architectures), each * heap operation (the comparison among sibling nodes) tends to benefit from the caches. -*/ + */ template class DAryHeap : public HeapInterface { public: diff --git a/vpr/src/route/d_ary_heap.tpp b/vpr/src/route/d_ary_heap.tpp index 565b8bac72b..b1fb0529c86 100644 --- a/vpr/src/route/d_ary_heap.tpp +++ b/vpr/src/route/d_ary_heap.tpp @@ -58,7 +58,7 @@ class customized_d_ary_priority_queue { inline size_t largest_child_index_partial(const size_t first_child, const size_t num_children /*must < `D`*/) { if constexpr (D == 2) { - (void) num_children; + (void)num_children; return first_child; } else { switch (num_children) { @@ -125,7 +125,7 @@ class customized_d_ary_priority_queue { public: explicit customized_d_ary_priority_queue(const Compare& compare = Compare(), - const Container& cont = Container()) + const Container& cont = Container()) : comp_(compare) , heap_(cont) { heap_.resize(1); // FIXME: currently do not support `make_heap` from cont (heap_) diff --git a/vpr/src/route/edge_groups.cpp b/vpr/src/route/edge_groups.cpp index 6b63f7d8823..6ca1e36692a 100644 --- a/vpr/src/route/edge_groups.cpp +++ b/vpr/src/route/edge_groups.cpp @@ -52,14 +52,14 @@ t_non_configurable_rr_sets EdgeGroups::output_sets() { std::set edge_set; std::set node_set(nodes.begin(), nodes.end()); - for (const auto& src : node_set) { - for (const auto& dest : graph_[src].edges) { - edge_set.emplace(t_node_edge(src, dest)); + for (const RRNodeId src : node_set) { + for (const RRNodeId dest : graph_[src].edges) { + edge_set.emplace(src, dest); } } - sets.node_sets.emplace(std::move(node_set)); - sets.edge_sets.emplace(std::move(edge_set)); + sets.node_sets.emplace_back(std::move(node_set)); + sets.edge_sets.emplace_back(std::move(edge_set)); } return sets; diff --git a/vpr/src/route/netlist_routers.h b/vpr/src/route/netlist_routers.h index 1524c2ddb38..d64477f03ad 100644 --- a/vpr/src/route/netlist_routers.h +++ b/vpr/src/route/netlist_routers.h @@ -71,9 +71,10 @@ class NetlistRouter { /* Include the derived classes here to get the HeapType-templated impls */ #include "SerialNetlistRouter.h" +#include "NestedNetlistRouter.h" #ifdef VPR_USE_TBB -# include "ParallelNetlistRouter.h" -# include "DecompNetlistRouter.h" +#include "ParallelNetlistRouter.h" +#include "DecompNetlistRouter.h" #endif template @@ -104,6 +105,20 @@ inline std::unique_ptr make_netlist_router_with_heap( routing_predictor, choking_spots, is_flat); + } else if (router_opts.router_algorithm == e_router_algorithm::NESTED) { + return std::make_unique>( + net_list, + router_lookahead, + router_opts, + connections_inf, + net_delay, + netlist_pin_lookup, + timing_info, + pin_timing_invalidator, + budgeting_inf, + routing_predictor, + choking_spots, + is_flat); } else if (router_opts.router_algorithm == e_router_algorithm::PARALLEL) { #ifdef VPR_USE_TBB return std::make_unique>( diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index cdaa5c00805..618f4edc67b 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -1,6 +1,7 @@ #include "overuse_report.h" #include +#include "physical_types_util.h" #include "vtr_log.h" /** @@ -29,13 +30,28 @@ static void report_congested_nets(const Netlist<>& net_list, static void log_overused_nodes_header(); static void log_single_overused_node_status(int overuse_index, RRNodeId inode); -void print_block_pins_nets(std::ostream& os, - t_physical_tile_type_ptr physical_type, - int layer, - int root_x, - int root_y, - int pin_physical_num, - const std::map>& rr_node_to_net_map); + +/** + * @brief When reporting overused IPIN/OPIN nodes, we also print the nets + * connected to other pins of the same block. This information may help + * the user understand why the node is overused or why other pins are not + * being utilized for routing the net. + * + * @param os The output stream to write the information to. + * @param physical_type The physical type of the block. + * @param layer The layer number of the block. + * @param root_x The x coordinate of the root of the block. + * @param root_y The y coordinate of the root of the block. + * @param pin_physical_num The physical number of the pin. + * @param rr_node_to_net_map A map of RR nodes to the nets that pass through them. + */ +static void print_block_pins_nets(std::ostream& os, + t_physical_tile_type_ptr physical_type, + int layer, + int root_x, + int root_y, + int pin_physical_num, + const std::map>& rr_node_to_net_map); /** * @brief Print out RR node overuse info in the VPR logfile. * @@ -141,7 +157,7 @@ void report_overused_nodes(const Netlist<>& net_list, * info on the nets passing through this overused node */ os << "-----------------------------\n"; //Separation line report_congested_nets(net_list, - g_vpr_ctx.atom().lookup, + g_vpr_ctx.atom().lookup(), os, congested_nets, is_flat, @@ -223,8 +239,7 @@ static void report_overused_ipin_opin(std::ostream& os, const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(grid_layer, grid_x, grid_y); - } - else { + } else { vib = nullptr; } //const t_vib_inf* vib = device_ctx.vib_grid[grid_layer][grid_x][grid_y]; @@ -329,7 +344,7 @@ static void report_congested_nets(const Netlist<>& net_list, os << "Net name = " << net_list.net_name(net_id) << ", "; if (is_flat) { AtomBlockId atom_blk_id = convert_to_atom_block_id(block_id); - os << "Driving block name = " << atom_lookup.atom_pb(atom_blk_id)->name << ", "; + os << "Driving block name = " << atom_lookup.atom_pb_bimap().atom_pb(atom_blk_id)->name << ", "; os << "Driving block type = " << g_vpr_ctx.clustering().clb_nlist.block_type(atom_lookup.atom_clb(atom_blk_id))->name << '\n'; } else { ClusterBlockId clb_blk_id = convert_to_cluster_block_id(block_id); @@ -357,7 +372,7 @@ static void report_congested_nets(const Netlist<>& net_list, << "\n"; if (is_flat) { auto pb_pin = atom_lookup.atom_pin_pb_graph_pin(convert_to_atom_pin_id(sink_id)); - auto pb_net_list = atom_lookup.atom_pb(convert_to_atom_block_id(net_list.pin_block(sink_id))); + auto pb_net_list = atom_lookup.atom_pb_bimap().atom_pb(convert_to_atom_block_id(net_list.pin_block(sink_id))); os << " " << "Pin Logical Num: " << pb_pin->pin_count_in_cluster << " PB Type: " << pb_pin->parent_node->pb_type->name << " Netlist PB: " << pb_net_list->name << " Parent PB Type: " << pb_net_list->parent_pb->pb_graph_node->pb_type->name << "Parent Netlist PB : " << pb_net_list->parent_pb->name << "\n"; os << " " @@ -447,17 +462,18 @@ static void log_single_overused_node_status(int overuse_index, RRNodeId node_id) fflush(stdout); } -void print_block_pins_nets(std::ostream& os, - t_physical_tile_type_ptr physical_type, - int layer, - int root_x, - int root_y, - int pin_physical_num, - const std::map>& rr_node_to_net_map) { +static void print_block_pins_nets(std::ostream& os, + t_physical_tile_type_ptr physical_type, + int layer, + int root_x, + int root_y, + int pin_physical_num, + const std::map>& rr_node_to_net_map) { const auto& rr_graph = g_vpr_ctx.device().rr_graph; t_pin_range pin_num_range; - if (is_pin_on_tile(physical_type, pin_physical_num)) { + bool pin_on_tile = is_pin_on_tile(physical_type, pin_physical_num); + if (pin_on_tile) { pin_num_range.low = 0; pin_num_range.high = physical_type->num_pins - 1; } else { @@ -479,7 +495,13 @@ void print_block_pins_nets(std::ostream& os, for (int pin = pin_num_range.low; pin <= pin_num_range.high; pin++) { t_rr_type rr_type = (get_pin_type_from_pin_physical_num(physical_type, pin) == DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN; RRNodeId node_id = get_pin_rr_node_id(rr_graph.node_lookup(), physical_type, layer, root_x, root_y, pin); - VTR_ASSERT(node_id != RRNodeId::INVALID()); + // When flat router is enabled, RR Node chains collapse into a single node. Thus, when + // looking up the RR Node ID, it may return an invalid node ID. In this case, we skip + // this pin. + if (!pin_on_tile && node_id == RRNodeId::INVALID()) { + continue; + } + VTR_ASSERT(node_id.is_valid()); auto search_result = rr_node_to_net_map.find(node_id); if (rr_type == t_rr_type::OPIN) { os << " OPIN - "; diff --git a/vpr/src/route/overuse_report.h b/vpr/src/route/overuse_report.h index ff48e170cfe..bae9da1d135 100644 --- a/vpr/src/route/overuse_report.h +++ b/vpr/src/route/overuse_report.h @@ -20,7 +20,11 @@ * All the nets passing through an overused RR node are flagged as congested nets. */ -///@brief Print out RR node overuse info in the VPR logfile. +/** + * @brief Print out RR node overuse info in the VPR logfile. + * + * @param max_logged_overused_rr_nodes The maximum number of overused RR nodes to log. + */ void log_overused_nodes_status(int max_logged_overused_rr_nodes); ///@brief Print out RR node overuse info in a post-VPR report file. diff --git a/vpr/src/route/partition_tree.cpp b/vpr/src/route/partition_tree.cpp index ac95a9a5285..38ee7abc2dd 100644 --- a/vpr/src/route/partition_tree.cpp +++ b/vpr/src/route/partition_tree.cpp @@ -34,7 +34,7 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& out->bb = {x1, x2, y1, y2, 0, layer_max}; out->nets = nets; /* Build net to ptree node lookup */ - for(auto net_id: nets){ + for (auto net_id : nets) { _net_to_ptree_node[net_id] = out.get(); } return out; @@ -130,7 +130,7 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& out->bb = {x1, x2, y1, y2, 0, layer_max}; out->nets = nets; /* Build net to ptree node lookup */ - for(auto net_id: nets){ + for (auto net_id : nets) { _net_to_ptree_node[net_id] = out.get(); } } @@ -169,9 +169,9 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& out->right = build_helper(netlist, right_nets, x1, std::floor(best_pos + 1), x2, y2); } - if(out->left) + if (out->left) out->left->parent = out.get(); - if(out->right) + if (out->right) out->right->parent = out.get(); out->bb = {x1, x2, y1, y2, 0, 0}; @@ -180,23 +180,23 @@ std::unique_ptr PartitionTree::build_helper(const Netlist<>& out->cutline_pos = best_pos; /* Build net to ptree node lookup */ - for(auto net_id: my_nets){ + for (auto net_id : my_nets) { _net_to_ptree_node[net_id] = out.get(); } return out; } -inline bool net_in_ptree_node(ParentNetId net_id, const PartitionTreeNode* node){ +inline bool net_in_ptree_node(ParentNetId net_id, const PartitionTreeNode* node) { auto& route_ctx = g_vpr_ctx.routing(); const t_bb& bb = route_ctx.route_bb[net_id]; return bb.xmin >= node->bb.xmin && bb.xmax <= node->bb.xmax && bb.ymin >= node->bb.ymin && bb.ymax <= node->bb.ymax; } void PartitionTree::update_nets(const std::vector& nets) { - for(auto net_id: nets){ + for (auto net_id : nets) { PartitionTreeNode* old_ptree_node = _net_to_ptree_node[net_id]; PartitionTreeNode* new_ptree_node = old_ptree_node; - while(!net_in_ptree_node(net_id, new_ptree_node)) + while (!net_in_ptree_node(net_id, new_ptree_node)) new_ptree_node = new_ptree_node->parent; old_ptree_node->nets.erase(net_id); new_ptree_node->nets.insert(net_id); @@ -208,13 +208,13 @@ void PartitionTree::update_nets(const std::vector& nets) { void PartitionTree::clear_vnets(void) { std::stack stack; stack.push(_root.get()); - while(!stack.empty()){ + while (!stack.empty()) { PartitionTreeNode* node = stack.top(); stack.pop(); node->vnets.clear(); - if(node->left) + if (node->left) stack.push(node->left.get()); - if(node->right) + if (node->right) stack.push(node->right.get()); } } diff --git a/vpr/src/route/partition_tree.h b/vpr/src/route/partition_tree.h index 82b75976b83..6bf68be04b8 100644 --- a/vpr/src/route/partition_tree.h +++ b/vpr/src/route/partition_tree.h @@ -10,7 +10,7 @@ #include #ifdef VPR_USE_TBB -# include +#include #endif /** Self-descriptive */ @@ -87,10 +87,10 @@ class PartitionTree { inline PartitionTreeNode& root(void) { return *_root; } /** Handle nets which had a bounding box update. - * Bounding boxes can only grow, so we should find a new partition tree node for - * these nets by moving them up until they fit in a node's bounds */ + * Bounding boxes can only grow, so we should find a new partition tree node for + * these nets by moving them up until they fit in a node's bounds */ void update_nets(const std::vector& nets); - + /** Delete all virtual nets in the tree. Used for the net decomposing router. * Virtual nets are invalidated between iterations due to changing bounding * boxes. */ diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index 6010e0626ef..098ae85ba5e 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -34,18 +34,18 @@ bool route(const Netlist<>& net_list, VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "No nets to route\n"); } - t_graph_type graph_type; - t_graph_type graph_directionality; + e_graph_type graph_type; + e_graph_type graph_directionality; if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - graph_directionality = GRAPH_BIDIR; + graph_type = e_graph_type::GLOBAL; + graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); /* Branch on tileable routing */ if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { - graph_type = GRAPH_UNIDIR_TILEABLE; + graph_type = e_graph_type::UNIDIR_TILEABLE; } - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } /* Set the channel widths */ @@ -77,7 +77,7 @@ bool route(const Netlist<>& net_list, is_flat); IntraLbPbPinLookup intra_lb_pb_pin_lookup(device_ctx.logical_block_types); - ClusteredPinAtomPinsLookup netlist_pin_lookup(cluster_ctx.clb_nlist, atom_ctx.nlist, intra_lb_pb_pin_lookup); + ClusteredPinAtomPinsLookup netlist_pin_lookup(cluster_ctx.clb_nlist, atom_ctx.netlist(), intra_lb_pb_pin_lookup); auto choking_spots = set_nets_choking_spots(net_list, route_ctx.net_terminal_groups, @@ -204,8 +204,8 @@ bool route(const Netlist<>& net_list, router_opts.timing_update_type, net_list, netlist_pin_lookup, - atom_ctx.nlist, - atom_ctx.lookup, + atom_ctx.netlist(), + atom_ctx.lookup(), timing_info, is_flat); @@ -312,7 +312,7 @@ bool route(const Netlist<>& net_list, float iter_cumm_time = iteration_timer.elapsed_sec(); float iter_elapsed_time = iter_cumm_time - prev_iter_cumm_time; - PartitionTreeDebug::log("Iteration " + std::to_string(itry) + " took " + std::to_string(iter_elapsed_time) + " s"); + PartitionTreeDebug::log("Iteration " + std::to_string(itry) + " took " + std::to_string(iter_elapsed_time) + " s"); //Output progress print_route_status(itry, iter_elapsed_time, pres_fac, num_net_bounding_boxes_updated, iter_results.stats, overuse_info, wirelength_info, timing_info, est_success_iteration); @@ -605,7 +605,6 @@ bool route(const Netlist<>& net_list, print_invalid_routing_info(net_list, is_flat); } } - } if (router_opts.with_timing_analysis) { diff --git a/vpr/src/route/route_budgets.cpp b/vpr/src/route/route_budgets.cpp index 00dd14ae2bc..677450ee034 100644 --- a/vpr/src/route/route_budgets.cpp +++ b/vpr/src/route/route_budgets.cpp @@ -507,7 +507,7 @@ float route_budgets::get_total_path_delay(std::shared_ptrsetup_tags(timing_node, tatum::TagType::DATA_ARRIVAL); auto required_tags = timing_analyzer->setup_tags(timing_node, tatum::TagType::DATA_REQUIRED); @@ -660,7 +660,7 @@ void route_budgets::check_if_budgets_in_bounds() { std::shared_ptr route_budgets::perform_sta(NetPinsMatrix& temp_budgets) { auto& atom_ctx = g_vpr_ctx.atom(); /*Perform static timing analysis to get the delay and path weights for slack allocation*/ - std::shared_ptr routing_delay_calc = std::make_shared(atom_ctx.nlist, atom_ctx.lookup, temp_budgets, is_flat_); + std::shared_ptr routing_delay_calc = std::make_shared(atom_ctx.netlist(), atom_ctx.lookup(), temp_budgets, is_flat_); //TODO: now that we support incremental timing updates, we should avoid re-building the timing analyzer from scratch and try // to calculate this incrementally @@ -950,4 +950,4 @@ void route_budgets::set_should_reroute(ParentNetId net_id, bool value) { if (set) { should_reroute_for_hold[net_id] = value; } -} \ No newline at end of file +} diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 7fd9720e450..3b720c5d76f 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -2,11 +2,16 @@ #include "atom_netlist_utils.h" #include "connection_router_interface.h" +#include "describe_rr_node.h" #include "draw_global.h" -#include "place_and_route.h" #include "route_common.h" +#include "physical_types_util.h" #include "route_export.h" -#include "rr_graph.h" + +#if defined(VPR_USE_TBB) +#include +#include +#endif /* The numbering relation between the channels and clbs is: * * * @@ -533,8 +538,8 @@ load_net_terminal_groups(const RRGraphView& rr_graph, } if (group_num == -1) { - /* TODO: net_terminal_groups cannot be fully RRNodeId - ified, because this code calls libarchfpga which - * I think should not be aware of RRNodeIds. Fixing this requires some refactoring to lift the offending functions + /* TODO: net_terminal_groups cannot be fully RRNodeId - ified, because this code calls libarchfpga which + * I think should not be aware of RRNodeIds. Fixing this requires some refactoring to lift the offending functions * into VPR. */ std::vector new_group = {int(rr_node_num)}; int new_group_num = net_terminal_groups[net_id].size(); @@ -601,12 +606,11 @@ static vtr::vector> load_rr_clb_sources(con static vtr::vector load_is_clock_net(const Netlist<>& net_list, bool is_flat) { - vtr::vector is_clock_net; + vtr::vector is_clock_net(net_list.nets().size()); auto& atom_ctx = g_vpr_ctx.atom(); - std::set clock_nets = find_netlist_physical_clock_nets(atom_ctx.nlist); + std::set clock_nets = find_netlist_physical_clock_nets(atom_ctx.netlist()); - is_clock_net.resize(net_list.nets().size()); for (auto net_id : net_list.nets()) { std::size_t net_id_num = std::size_t(net_id); if (is_flat) { @@ -614,7 +618,7 @@ static vtr::vector load_is_clock_net(const Netlist<>& net_ is_clock_net[net_id] = clock_nets.find(atom_net_id) != clock_nets.end(); } else { ClusterNetId cluster_net_id = ClusterNetId(net_id_num); - is_clock_net[net_id] = clock_nets.find(atom_ctx.lookup.atom_net(cluster_net_id)) != clock_nets.end(); + is_clock_net[net_id] = clock_nets.find(atom_ctx.lookup().atom_net(cluster_net_id)) != clock_nets.end(); } } diff --git a/vpr/src/route/route_profiling.cpp b/vpr/src/route/route_profiling.cpp index b7c88749335..7ae6f7c813e 100644 --- a/vpr/src/route/route_profiling.cpp +++ b/vpr/src/route/route_profiling.cpp @@ -146,7 +146,7 @@ struct Congested_node_types { }; void congestion_analysis() { -# if 0 +#if 0 // each type indexes into array which holds the congestion for that type std::vector congestion_per_type((size_t)NUM_RR_TYPES, 0); // print out specific node information if congestion for type is low enough @@ -183,7 +183,7 @@ void congestion_analysis() { } } return; -# endif +#endif } static clock_t conn_start_time; diff --git a/vpr/src/route/route_utilization.cpp b/vpr/src/route/route_utilization.cpp index 05fc2eda054..66b03751451 100644 --- a/vpr/src/route/route_utilization.cpp +++ b/vpr/src/route/route_utilization.cpp @@ -16,7 +16,7 @@ vtr::Matrix calculate_routing_usage(t_rr_type rr_type, bool is_flat, bool //Collect all the in-use RR nodes std::set rr_nodes; for (auto net : cluster_ctx.clb_nlist.nets()) { - auto parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup, net, is_flat); + auto parent_id = get_cluster_net_parent_id(g_vpr_ctx.atom().lookup(), net, is_flat); if (!route_ctx.route_trees[parent_id]) continue; diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index b398066769f..aab9e952315 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -10,6 +10,7 @@ #include "net_delay.h" #include "netlist_fwd.h" #include "overuse_report.h" +#include "physical_types_util.h" #include "place_and_route.h" #include "route_debug.h" @@ -219,7 +220,7 @@ void generate_route_timing_reports(const t_router_opts& router_opts, auto& atom_ctx = g_vpr_ctx.atom(); const auto& blk_loc_registry = g_vpr_ctx.placement().blk_loc_registry(); - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); @@ -471,14 +472,14 @@ void try_graph(int width_fac, bool is_flat) { auto& device_ctx = g_vpr_ctx.mutable_device(); - t_graph_type graph_type; - t_graph_type graph_directionality; + e_graph_type graph_type; + e_graph_type graph_directionality; if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - graph_directionality = GRAPH_BIDIR; + graph_type = e_graph_type::GLOBAL; + graph_directionality = e_graph_type::BIDIR; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } /* Set the channel widths */ @@ -516,7 +517,7 @@ void update_draw_pres_fac(const float /*new_pres_fac*/) { #ifndef NO_GRAPHICS void update_router_info_and_check_bp(bp_router_type type, int net_id) { t_draw_state* draw_state = get_draw_state_vars(); - if (draw_state->list_of_breakpoints.size() != 0) { + if (!draw_state->list_of_breakpoints.empty()) { if (type == BP_ROUTE_ITER) get_bp_state_globals()->get_glob_breakpoint_state()->router_iter++; else if (type == BP_NET_ID) diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index d129193ee1e..19f14e7cdb2 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -73,12 +73,12 @@ int get_max_pins_per_net(const Netlist<>& net_list); /** Get the RouteTree associated with the ClusterNetId. * Flat routing maps AtomNetIds to RouteTrees instead, so we need to first look up the associated AtomNetId. */ -inline const vtr::optional& get_route_tree_from_cluster_net_id(ClusterNetId net_id){ +inline const vtr::optional& get_route_tree_from_cluster_net_id(ClusterNetId net_id) { auto& route_ctx = g_vpr_ctx.routing(); - if(!route_ctx.is_flat){ + if (!route_ctx.is_flat) { return route_ctx.route_trees[ParentNetId(net_id)]; - }else{ - auto& atom_lookup = g_vpr_ctx.atom().lookup; + } else { + auto& atom_lookup = g_vpr_ctx.atom().lookup(); AtomNetId atom_id = atom_lookup.atom_net(net_id); return route_ctx.route_trees[ParentNetId(atom_id)]; } diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index 1b8c4ab771d..d88b0024517 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -6,7 +6,6 @@ #include "route_tree.h" #include "rr_graph.h" #include "vtr_time.h" -#include "draw.h" RouterDelayProfiler::RouterDelayProfiler(const Netlist<>& net_list, const RouterLookahead* lookahead, @@ -187,10 +186,10 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src RouterStats router_stats; ConnectionParameters conn_params(ParentNetId::INVALID(), OPEN, false, std::unordered_map()); vtr::vector shortest_paths = router.timing_driven_find_all_shortest_paths_from_route_tree(tree.root(), - cost_params, - bounding_box, - router_stats, - conn_params); + cost_params, + bounding_box, + router_stats, + conn_params); VTR_ASSERT(shortest_paths.size() == device_ctx.rr_graph.num_nodes()); for (int isink = 0; isink < (int)device_ctx.rr_graph.num_nodes(); ++isink) { @@ -250,16 +249,17 @@ void alloc_routing_structs(const t_chan_width& chan_width, const std::vector& directs, bool is_flat) { int warnings; - t_graph_type graph_type; + e_graph_type graph_type; auto& device_ctx = g_vpr_ctx.mutable_device(); if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; + graph_type = e_graph_type::GLOBAL; } else { - graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); - if ((UNI_DIRECTIONAL == det_routing_arch->directionality) && (true == det_routing_arch->tileable)) { - graph_type = GRAPH_UNIDIR_TILEABLE; + graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = e_graph_type::UNIDIR_TILEABLE; } } diff --git a/vpr/src/route/router_lookahead_cost_map.cpp b/vpr/src/route/router_lookahead_cost_map.cpp index ec27878b3a1..2f7a8911084 100644 --- a/vpr/src/route/router_lookahead_cost_map.cpp +++ b/vpr/src/route/router_lookahead_cost_map.cpp @@ -6,11 +6,11 @@ #include "vtr_geometry.h" #ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "extended_map_lookahead.capnp.h" -# include "ndmatrix_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" +#include "capnp/serialize.h" +#include "extended_map_lookahead.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" #endif // Lookahead penalties constants diff --git a/vpr/src/route/router_lookahead_extended_map.cpp b/vpr/src/route/router_lookahead_extended_map.cpp index d72f5471130..2f3964b47b5 100644 --- a/vpr/src/route/router_lookahead_extended_map.cpp +++ b/vpr/src/route/router_lookahead_extended_map.cpp @@ -19,15 +19,15 @@ #include "route_debug.h" #ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "extended_map_lookahead.capnp.h" -# include "ndmatrix_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" +#include "capnp/serialize.h" +#include "extended_map_lookahead.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" #endif #if defined(VPR_USE_TBB) -# include +#include #endif /* we're profiling routing cost over many tracks for each wire type, so we'll diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 648b182c9eb..d11f216c8ee 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -24,28 +24,24 @@ #include #include #include "connection_router_interface.h" +#include "physical_types_util.h" #include "vpr_types.h" -#include "vpr_error.h" #include "vpr_utils.h" #include "globals.h" #include "vtr_math.h" -#include "vtr_log.h" #include "vtr_assert.h" #include "vtr_time.h" -#include "vtr_geometry.h" #include "router_lookahead_map.h" #include "router_lookahead_map_utils.h" -#include "rr_graph2.h" #include "rr_graph.h" -#include "route_common.h" #ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "map_lookahead.capnp.h" -# include "ndmatrix_serdes.h" -# include "intra_cluster_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" +#include "capnp/serialize.h" +#include "map_lookahead.capnp.h" +#include "ndmatrix_serdes.h" +#include "intra_cluster_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" #endif /* VTR_ENABLE_CAPNPROTO */ static constexpr int VALID_NEIGHBOR_NUMBER = 3; @@ -207,8 +203,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(current_node), rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node)); - } - else { + } else { vib = nullptr; } //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; @@ -334,7 +329,6 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ //cost to reach them) in src_opin_delays. Once we know what wire types are //reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final //delay to reach the sink. - t_physical_tile_type_ptr from_tile_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(from_node), rr_graph.node_ylow(from_node), from_layer_num}); @@ -348,15 +342,15 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ * the minimum cost among them. In the following for loop, we iterate over each layer and pass it the * routing segments on that layer reachable from the OPIN/SOURCE to segments on that layer. This for loop then calculates and returns * the minimum cost from the given OPIN/SOURCE to the specified SINK considering routing options across all layers. - */ + */ for (int layer_num = 0; layer_num < device_ctx.grid.get_num_layers(); layer_num++) { float this_delay_cost; float this_cong_cost; std::tie(this_delay_cost, this_cong_cost) = util::get_cost_from_src_opin(src_opin_delays[from_layer_num][from_tile_index][from_ptc][layer_num], - delta_x, - delta_y, - to_layer_num, - get_wire_cost_entry); + delta_x, + delta_y, + to_layer_num, + get_wire_cost_entry); expected_delay_cost = std::min(expected_delay_cost, this_delay_cost); expected_cong_cost = std::min(expected_cong_cost, this_cong_cost); } @@ -904,9 +898,9 @@ static void min_opin_distance_cost_map(const util::t_src_opin_delays& src_opin_d // #ifndef VTR_ENABLE_CAPNPROTO -# define DISABLE_ERROR \ - "is disabled because VTR_ENABLE_CAPNPROTO=OFF." \ - "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable." +#define DISABLE_ERROR \ + "is disabled because VTR_ENABLE_CAPNPROTO=OFF." \ + "Re-compile with CMake option VTR_ENABLE_CAPNPROTO=ON to enable." void read_router_lookahead(const std::string& /*file*/) { VPR_THROW(VPR_ERROR_PLACE, "MapLookahead::read_router_lookahead " DISABLE_ERROR); diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index a433ad365a3..c64e97f85c3 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -12,6 +12,7 @@ #include #include "globals.h" +#include "physical_types_util.h" #include "vpr_context.h" #include "vtr_math.h" #include "vtr_time.h" @@ -58,7 +59,6 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, vtr::vector& node_expanded, std::priority_queue& pq); - /** * @brief Computes the adjusted position of an RR graph node. * This function does not modify the position of the given node. @@ -423,8 +423,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(sample_loc.layer_num, sample_loc.x, sample_loc.y); - } - else { + } else { vib = nullptr; } //const t_vib_inf* vib = device_ctx.vib_grid[sample_loc.layer_num][sample_loc.x][sample_loc.y]; @@ -674,7 +673,18 @@ std::pair get_xy_deltas(RRNodeId from_node, RRNodeId to_node) { Direction from_dir = rr_graph.node_direction(from_node); if (is_chan(from_type) && ((to_seg < from_seg_low && from_dir == Direction::INC) || (to_seg > from_seg_high && from_dir == Direction::DEC))) { - delta_seg++; + // If the routing channel starts from the perimeter of the grid, + // and it is heading towards the outside of the grid, we should + // not increment the delta_seg by 1. + int max_seg_index = -1; + if (from_type == CHANX) { + max_seg_index = static_cast(device_ctx.grid.width()) - 1; + } else { + max_seg_index = static_cast(device_ctx.grid.height()) - 1; + } + if (!((from_seg_low == 0 && from_dir == Direction::DEC) || (from_seg_low == max_seg_index && from_dir == Direction::INC))) { + delta_seg++; + } } if (from_type == CHANY) { @@ -792,7 +802,6 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length, //Finally, now that we have a list of sample locations, run a Dijkstra flood from //each sample location to profile the routing network from this type - t_routing_cost_map routing_cost_map({static_cast(device_ctx.grid.get_num_layers()), device_ctx.grid.width(), device_ctx.grid.height()}); if (sample_nodes.empty()) { @@ -1043,8 +1052,7 @@ static void dijkstra_flood_to_wires(int itile, const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(next_node), rr_graph.node_xlow(next_node), rr_graph.node_ylow(next_node)); - } - else { + } else { vib = nullptr; } //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(next_node)][rr_graph.node_xlow(next_node)][rr_graph.node_ylow(next_node)]; @@ -1247,9 +1255,7 @@ static void run_intra_tile_dijkstra(const RRGraphView& rr_graph, node_expanded.resize(rr_graph.num_nodes()); std::fill(node_expanded.begin(), node_expanded.end(), false); - vtr::vector node_seen_cost; - node_seen_cost.resize(rr_graph.num_nodes()); - std::fill(node_seen_cost.begin(), node_seen_cost.end(), -1.); + vtr::vector node_seen_cost(rr_graph.num_nodes(), -1.f); struct t_pq_entry { float delay; @@ -1415,11 +1421,10 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, const VibInf* vib; if (!device_ctx.arch->vib_infs.empty()) { vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(child_node), rr_graph.node_xlow(child_node), rr_graph.node_ylow(child_node)); - } - else { + } else { vib = nullptr; } - + if (!is_inter_cluster_node(physical_type, vib, rr_graph.node_type(child_node), diff --git a/vpr/src/route/router_lookahead_sampling.cpp b/vpr/src/route/router_lookahead_sampling.cpp index c7f2221ff9c..a8ad7dc2f15 100644 --- a/vpr/src/route/router_lookahead_sampling.cpp +++ b/vpr/src/route/router_lookahead_sampling.cpp @@ -60,9 +60,9 @@ static std::vector choose_points(const vtr::Matrix& counts, // sort by distance from center std::stable_sort(points.begin(), points.end(), - [&](const SamplePoint& a, const SamplePoint& b) { - return manhattan_distance(a.location, center) < manhattan_distance(b.location, center); - }); + [&](const SamplePoint& a, const SamplePoint& b) { + return manhattan_distance(a.location, center) < manhattan_distance(b.location, center); + }); return points; } @@ -233,9 +233,9 @@ std::vector find_sample_regions(int num_segments) { // sort regions std::stable_sort(sample_regions.begin(), sample_regions.end(), - [](const SampleRegion& a, const SampleRegion& b) { - return a.order < b.order; - }); + [](const SampleRegion& a, const SampleRegion& b) { + return a.order < b.order; + }); // build an index of sample points on segment type and location std::map, SamplePoint*> sample_point_index; diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 0660c652881..0b38fc692ce 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1,14 +1,14 @@ #include -#include #include -#include #include #include #include +#include "alloc_and_load_rr_indexed_data.h" +#include "physical_types_util.h" +#include "rr_rc_data.h" #include "vtr_assert.h" #include "vtr_util.h" -#include "vtr_memory.h" #include "vtr_math.h" #include "vtr_log.h" #include "vtr_time.h" @@ -21,42 +21,24 @@ #include "rr_graph_utils.h" #include "rr_graph.h" #include "rr_graph_area.h" -#include "rr_graph_utils.h" #include "rr_graph2.h" #include "rr_graph_sbox.h" #include "rr_graph_timing_params.h" -#include "rr_graph_indexed_data.h" #include "check_rr_graph.h" -#include "read_xml_arch_file.h" #include "echo_files.h" -#include "cb_metrics.h" #include "build_switchblocks.h" #include "rr_graph_writer.h" #include "rr_graph_reader.h" -#include "router_lookahead_map.h" #include "rr_graph_clock.h" #include "edge_groups.h" #include "rr_graph_builder.h" #include "tileable_rr_graph_builder.h" #include "rr_types.h" -#include "echo_files.h" //#define VERBOSE //used for getting the exact count of each edge type and printing it to std out. -struct t_mux { - int size; - t_mux* next; -}; - -struct t_mux_size_distribution { - int mux_count; - int max_index; - int* distr; - t_mux_size_distribution* next; -}; - struct t_pin_loc { int pin_index; int width_offset; @@ -65,12 +47,6 @@ struct t_pin_loc { e_side side; }; -struct t_pin_spec { - t_rr_type pin_type; - int pin_ptc; - RRNodeId pin_rr_node_id; -}; - /******************* Variables local to this module. ***********************/ /********************* Subroutines local to this module. *******************/ @@ -108,11 +84,11 @@ bool channel_widths_unchanged(const t_chan_width& current, const t_chan_width& p static vtr::NdMatrix, 5> alloc_and_load_pin_to_track_map(const e_pin_type pin_type, const vtr::Matrix& Fc, const t_physical_tile_type_ptr tile_type, - const std::set type_layer, + const std::set& type_layer, const std::vector& perturb_switch_pattern, const e_directionality directionality, const std::vector& seg_inf, - const int* sets_per_seg_type); + const std::vector& sets_per_seg_type); /** * @brief This routine calculates pin connections to tracks for a specific type and a specific segment based on the Fc value * defined for each pin in the architecture file. This routine is called twice for each combination of block type and segment @@ -146,7 +122,7 @@ static void advance_to_next_block_side(t_physical_tile_type_ptr tile_type, int& static vtr::NdMatrix, 5> alloc_and_load_track_to_pin_lookup(vtr::NdMatrix, 5> pin_to_track_map, const vtr::Matrix& Fc, const t_physical_tile_type_ptr tile_type, - const std::set type_layer, + const std::set& type_layer, const int width, const int height, const int num_pins, @@ -166,7 +142,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_y, const DeviceGrid& grid, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, const int num_seg_types); static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, @@ -186,7 +162,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, bool* Fc_clipped, const t_unified_to_parallel_seg_index& seg_index_map, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, const int num_seg_types, int& edge_count); @@ -200,7 +176,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, RRNodeId from_rr_node, t_rr_edge_info_set& rr_edges_to_create, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs); + const std::vector& clb_to_clb_directs); static std::function alloc_and_load_rr_graph(RRGraphBuilder& rr_graph_builder, t_rr_graph_storage& L_rr_node, @@ -229,7 +205,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder const enum e_directionality directionality, bool* Fc_clipped, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, bool is_global_graph, const enum e_clock_modeling clock_modeling, bool is_flat, @@ -322,7 +298,6 @@ static void alloc_and_load_tile_rr_graph(RRGraphBuilder& rr_graph_builder, static float pattern_fmod(float a, float b); - /** * @brief Loads the tracks_connected_to_pin array with an even distribution of switches across the tracks for each pin. * @@ -375,7 +350,7 @@ static void check_all_tracks_reach_pins(t_logical_block_type_ptr type, static std::vector> alloc_and_load_perturb_ipins(const int L_num_types, const int num_seg_types, - const int* sets_per_seg_type, + const std::vector& sets_per_seg_type, const std::vector>& Fc_in, const std::vector>& Fc_out, const enum e_directionality directionality); @@ -529,7 +504,7 @@ static float get_min_delay_to_chain(t_physical_tile_type_ptr physical_type, int pin_physical_num, int chain_sink_pin); -static std::unordered_set get_chain_pins(std::vector chain); +static std::unordered_set get_chain_pins(const std::vector& chain); static void build_rr_chan(RRGraphBuilder& rr_graph_builder, const int layer, @@ -593,8 +568,7 @@ static void alloc_rr_switch_inf(RRGraphBuilder& rr_graph_builder, t_arch_switch_fanin& arch_switch_fanins, const std::map& arch_sw_map); -static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, - int* num_seg_details = nullptr); +static std::vector alloc_and_load_global_route_seg_details(const int global_route_switch); static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_graph, RRNodeId from_rr, @@ -688,7 +662,7 @@ static float get_delay_directly_connected_pins(t_physical_tile_type_ptr physical static void process_non_config_sets(); -static void build_rr_graph(const t_graph_type graph_type, +static void build_rr_graph(e_graph_type graph_type, const std::vector& types, const DeviceGrid& grid, t_chan_width nodes_per_chan, @@ -711,7 +685,7 @@ static void build_rr_graph(const t_graph_type graph_type, int* Warnings, const int route_verbosity); -static void build_intra_cluster_rr_graph(const t_graph_type graph_type, +static void build_intra_cluster_rr_graph(e_graph_type graph_type, const DeviceGrid& grid, const std::vector& types, const RRGraphView& rr_graph, @@ -728,12 +702,12 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, * @param det_routing_arch Contain the information from architecture file * @param load_rr_graph Indicate whether the RR graph is loaded from a file */ -static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, - bool load_rr_graph); +static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, + bool load_rr_graph); /******************* Subroutine definitions *******************************/ -void create_rr_graph(const t_graph_type graph_type, +void create_rr_graph(e_graph_type graph_type, const std::vector& block_types, const DeviceGrid& grid, const t_chan_width& nodes_per_chan, @@ -759,7 +733,7 @@ void create_rr_graph(const t_graph_type graph_type, } } else { if (load_rr_graph) { - if (device_ctx.read_rr_graph_filename != det_routing_arch->read_rr_graph_filename) { + if (device_ctx.loaded_rr_graph_filename != det_routing_arch->read_rr_graph_filename) { free_rr_graph(); load_rr_file(&mutable_device_ctx.rr_graph_builder, @@ -777,7 +751,7 @@ void create_rr_graph(const t_graph_type graph_type, &det_routing_arch->wire_to_rr_ipin_switch, &det_routing_arch->wire_to_arch_ipin_switch_between_dice, det_routing_arch->read_rr_graph_filename.c_str(), - &det_routing_arch->read_rr_graph_filename, + &mutable_device_ctx.loaded_rr_graph_filename, router_opts.read_rr_edge_metadata, router_opts.do_check_rr_graph, echo_enabled, @@ -791,7 +765,7 @@ void create_rr_graph(const t_graph_type graph_type, } } else { free_rr_graph(); - if (GRAPH_UNIDIR_TILEABLE != graph_type) { + if (e_graph_type::UNIDIR_TILEABLE != graph_type) { build_rr_graph(graph_type, block_types, grid, @@ -833,7 +807,7 @@ void create_rr_graph(const t_graph_type graph_type, directs, &det_routing_arch->wire_to_rr_ipin_switch, det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ - det_routing_arch->perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ + det_routing_arch->perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ det_routing_arch->concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ @@ -841,6 +815,18 @@ void create_rr_graph(const t_graph_type graph_type, Warnings); } } + + // Check if there is an edge override file to read and that it is not already loaded. + if (!det_routing_arch->read_rr_edge_override_filename.empty() + && det_routing_arch->read_rr_edge_override_filename != device_ctx.loaded_rr_edge_override_filename) { + + load_rr_edge_delay_overrides(det_routing_arch->read_rr_edge_override_filename, + mutable_device_ctx.rr_graph_builder, + device_ctx.rr_graph); + + // Remember the loaded filename to avoid reloading it before the RR graph is cleared. + mutable_device_ctx.loaded_rr_edge_override_filename = det_routing_arch->read_rr_edge_override_filename; + } } if (is_flat) { @@ -1045,7 +1031,7 @@ bool channel_widths_unchanged(const t_chan_width& current, const t_chan_width& p return true; //Identical } -static void build_rr_graph(const t_graph_type graph_type, +static void build_rr_graph(e_graph_type graph_type, const std::vector& types, const DeviceGrid& grid, t_chan_width nodes_per_chan, @@ -1073,9 +1059,9 @@ static void build_rr_graph(const t_graph_type graph_type, *Warnings = RR_GRAPH_NO_WARN; /* Decode the graph_type */ - bool is_global_graph = ((GRAPH_GLOBAL == graph_type) ? true : false); - bool use_full_seg_groups = ((GRAPH_UNIDIR_TILEABLE == graph_type) ? true : false); - enum e_directionality directionality = ((GRAPH_BIDIR == graph_type) ? BI_DIRECTIONAL : UNI_DIRECTIONAL); + bool is_global_graph = (e_graph_type::GLOBAL == graph_type); + bool use_full_seg_groups = (e_graph_type::UNIDIR_TILEABLE == graph_type); + enum e_directionality directionality = (e_graph_type::BIDIR == graph_type) ? BI_DIRECTIONAL : UNI_DIRECTIONAL; if (is_global_graph) { directionality = BI_DIRECTIONAL; } @@ -1091,32 +1077,26 @@ static void build_rr_graph(const t_graph_type graph_type, auto& device_ctx = g_vpr_ctx.mutable_device(); const auto& rr_graph = device_ctx.rr_graph; - t_clb_to_clb_directs* clb_to_clb_directs = nullptr; - if (!directs.empty()) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); - } + std::vector clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); /* START SEG_DETAILS */ - size_t num_segments = segment_inf.size(); + const size_t num_segments = segment_inf.size(); device_ctx.rr_graph_builder.reserve_segments(num_segments); for (size_t iseg = 0; iseg < num_segments; ++iseg) { device_ctx.rr_graph_builder.add_rr_segment(segment_inf[iseg]); } - int num_seg_details_x = 0; - int num_seg_details_y = 0; - - t_seg_details* seg_details_x = nullptr; - t_seg_details* seg_details_y = nullptr; - t_unified_to_parallel_seg_index segment_index_map; std::vector segment_inf_x = get_parallel_segs(segment_inf, segment_index_map, X_AXIS); std::vector segment_inf_y = get_parallel_segs(segment_inf, segment_index_map, Y_AXIS); + std::vector seg_details_x; + std::vector seg_details_y; + if (is_global_graph) { /* Sets up a single unit length segment type for global routing. */ - seg_details_x = alloc_and_load_global_route_seg_details(global_route_switch, &num_seg_details_x); - seg_details_y = alloc_and_load_global_route_seg_details(global_route_switch, &num_seg_details_y); + seg_details_x = alloc_and_load_global_route_seg_details(global_route_switch); + seg_details_y = alloc_and_load_global_route_seg_details(global_route_switch); } else { /* Setup segments including distributing tracks and staggering. @@ -1131,13 +1111,11 @@ static void build_rr_graph(const t_graph_type graph_type, /*Get x & y segments separately*/ seg_details_x = alloc_and_load_seg_details(&max_chan_width_x, max_dim, segment_inf_x, - use_full_seg_groups, directionality, - &num_seg_details_x); + use_full_seg_groups, directionality); seg_details_y = alloc_and_load_seg_details(&max_chan_width_y, max_dim, segment_inf_y, - use_full_seg_groups, directionality, - &num_seg_details_y); + use_full_seg_groups, directionality); if (nodes_per_chan.x_max != max_chan_width_x || nodes_per_chan.y_max != max_chan_width_y) { nodes_per_chan.x_max = max_chan_width_x; @@ -1166,8 +1144,7 @@ static void build_rr_graph(const t_graph_type graph_type, t_chan_details chan_details_x; t_chan_details chan_details_y; - alloc_and_load_chan_details(grid, &nodes_per_chan, - num_seg_details_x, num_seg_details_y, + alloc_and_load_chan_details(grid, nodes_per_chan, seg_details_x, seg_details_y, chan_details_x, chan_details_y); @@ -1205,14 +1182,9 @@ static void build_rr_graph(const t_graph_type graph_type, total_sets_x /= 2; total_sets_y /= 2; } - auto sets_per_seg_type_x = get_seg_track_counts(total_sets_x, segment_inf_x, use_full_seg_groups); - auto sets_per_seg_type_y = get_seg_track_counts(total_sets_y, segment_inf_y, use_full_seg_groups); - auto sets_per_seg_type = get_seg_track_counts(total_sets, segment_inf, use_full_seg_groups); - - auto sets_test = get_ordered_seg_track_counts(segment_inf_x, segment_inf_y, segment_inf, sets_per_seg_type_x, sets_per_seg_type_y); - - //VTR_ASSERT_MSG(sets_test==sets_per_seg_type, - // "Not equal combined output after combining segs " ); + std::vector sets_per_seg_type_x = get_seg_track_counts(total_sets_x, segment_inf_x, use_full_seg_groups); + std::vector sets_per_seg_type_y = get_seg_track_counts(total_sets_y, segment_inf_y, use_full_seg_groups); + std::vector sets_per_seg_type = get_seg_track_counts(total_sets, segment_inf, use_full_seg_groups); if (is_global_graph) { //All pins can connect during global routing @@ -1221,19 +1193,19 @@ static void build_rr_graph(const t_graph_type graph_type, Fc_out = std::vector>(types.size(), ones); } else { bool Fc_clipped = false; - Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type.get(), &nodes_per_chan, + Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, &nodes_per_chan, e_fc_type::IN, directionality, &Fc_clipped, is_flat); if (Fc_clipped) { *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; } Fc_clipped = false; - Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type.get(), &nodes_per_chan, + Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, &nodes_per_chan, e_fc_type::OUT, directionality, &Fc_clipped, is_flat); if (Fc_clipped) { *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; } - for (const auto& type : types) { + for (const t_physical_tile_type& type : types) { int i = type.index; /* Skip "EMPTY" */ @@ -1263,7 +1235,7 @@ static void build_rr_graph(const t_graph_type graph_type, } auto perturb_ipins = alloc_and_load_perturb_ipins(types.size(), segment_inf.size(), - sets_per_seg_type.get(), Fc_in, Fc_out, directionality); + sets_per_seg_type, Fc_in, Fc_out, directionality); /* END FC */ /* Alloc node lookups, count nodes, alloc rr nodes */ @@ -1335,10 +1307,10 @@ static void build_rr_graph(const t_graph_type graph_type, /* it looks like we get unbalanced muxing from this switch block code with Fs > 3 */ VTR_ASSERT(Fs == 3); - unidir_sb_pattern = alloc_sblock_pattern_lookup(grid, &nodes_per_chan); + unidir_sb_pattern = alloc_sblock_pattern_lookup(grid, nodes_per_chan); for (size_t i = 0; i < grid.width() - 1; i++) { for (size_t j = 0; j < grid.height() - 1; j++) { - load_sblock_pattern_lookup(i, j, grid, &nodes_per_chan, + load_sblock_pattern_lookup(i, j, grid, nodes_per_chan, chan_details_x, chan_details_y, Fs, sb_type, unidir_sb_pattern); } @@ -1358,7 +1330,7 @@ static void build_rr_graph(const t_graph_type graph_type, */ if (grid.get_num_layers() > 1 && sb_type == CUSTOM) { //keep how many nodes each switchblock requires for each x,y location - auto extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map,custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder); + auto extra_nodes_per_switchblock = get_number_track_to_track_inter_die_conn(sb_conn_map, custom_3d_sb_fanin_fanout, device_ctx.rr_graph_builder); //allocate new nodes in each switchblocks alloc_and_load_inter_die_rr_node_indices(device_ctx.rr_graph_builder, &nodes_per_chan, grid, extra_nodes_per_switchblock, &num_rr_nodes); device_ctx.rr_graph_builder.resize_nodes(num_rr_nodes); @@ -1380,12 +1352,12 @@ static void build_rr_graph(const t_graph_type graph_type, ipin_to_track_map_x[itype] = alloc_and_load_pin_to_track_map(RECEIVER, Fc_in[itype], &types[itype], type_layer, perturb_ipins[itype], directionality, - segment_inf_x, sets_per_seg_type_x.get()); + segment_inf_x, sets_per_seg_type_x); ipin_to_track_map_y[itype] = alloc_and_load_pin_to_track_map(RECEIVER, Fc_in[itype], &types[itype], type_layer, perturb_ipins[itype], directionality, - segment_inf_y, sets_per_seg_type_y.get()); + segment_inf_y, sets_per_seg_type_y); track_to_pin_lookup_x[itype] = alloc_and_load_track_to_pin_lookup(ipin_to_track_map_x[itype], Fc_in[itype], &types[itype], @@ -1422,7 +1394,7 @@ static void build_rr_graph(const t_graph_type graph_type, max_chan_width, segment_inf); opin_to_track_map[itype] = alloc_and_load_pin_to_track_map(DRIVER, Fc_out[itype], &types[itype], type_layer, perturb_opins, directionality, - segment_inf, sets_per_seg_type.get()); + segment_inf, sets_per_seg_type); } } /* END OPIN MAP */ @@ -1469,16 +1441,16 @@ static void build_rr_graph(const t_graph_type graph_type, route_verbosity); // Verify no incremental node allocation. - // AA: Note that in the case of dedicated networks, we are currently underestimating the additional node count due to the clock networks. + // AA: Note that in the case of dedicated networks, we are currently underestimating the additional node count due to the clock networks. /* For now, the node count comparison is being skipped in the presence of clock networks. - * TODO: The node estimation needs to be fixed for dedicated clock networks. */ + * TODO: The node estimation needs to be fixed for dedicated clock networks. */ if (rr_graph.num_nodes() > expected_node_count && clock_modeling != DEDICATED_NETWORK) { VTR_LOG_ERROR("Expected no more than %zu nodes, have %zu nodes\n", expected_node_count, rr_graph.num_nodes()); } /* Update rr_nodes capacities if global routing */ - if (graph_type == GRAPH_GLOBAL) { + if (graph_type == e_graph_type::GLOBAL) { // Using num_rr_nodes here over device_ctx.rr_nodes.size() because // clock_modeling::DEDICATED_NETWORK will append some rr nodes after // the regular graph. @@ -1495,7 +1467,7 @@ static void build_rr_graph(const t_graph_type graph_type, } /*Update rr_nodes ptc_twist_incr number if we are creating tileable graph*/ - if (graph_type == GRAPH_UNIDIR_TILEABLE) { + if (graph_type == e_graph_type::UNIDIR_TILEABLE) { device_ctx.rr_graph_builder.resize_ptc_twist_incr(num_rr_nodes); for (int rr_node_id = 0; rr_node_id < num_rr_nodes; rr_node_id++) { auto node_type = rr_graph.node_type(RRNodeId(rr_node_id)); @@ -1534,7 +1506,7 @@ static void build_rr_graph(const t_graph_type graph_type, device_ctx.chan_width = nodes_per_chan; rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); - + const VibDeviceGrid vib_grid; check_rr_graph(device_ctx.rr_graph, types, @@ -1545,34 +1517,17 @@ static void build_rr_graph(const t_graph_type graph_type, graph_type, is_flat); - /* Free all temp structs */ - delete[] seg_details_x; - delete[] seg_details_y; - - seg_details_x = nullptr; - seg_details_y = nullptr; - if (!chan_details_x.empty() || !chan_details_y.empty()) { - free_chan_details(chan_details_x, chan_details_y); - } - if (sb_conn_map) { free_switchblock_permutations(sb_conn_map); sb_conn_map = nullptr; } - track_to_pin_lookup_x.clear(); - track_to_pin_lookup_y.clear(); - - if (clb_to_clb_directs != nullptr) { - delete[] clb_to_clb_directs; - } - // We are done with building the RR Graph. Thus, we can clear the storages only used // to build the RR Graph device_ctx.rr_graph_builder.clear_temp_storage(); } -static void build_intra_cluster_rr_graph(const t_graph_type graph_type, +static void build_intra_cluster_rr_graph(e_graph_type graph_type, const DeviceGrid& grid, const std::vector& types, const RRGraphView& rr_graph, @@ -1643,12 +1598,12 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, } static int get_delayless_switch_id(t_det_routing_arch* det_routing_arch, - bool load_rr_graph) { + bool load_rr_graph) { const auto& device_ctx = g_vpr_ctx.device(); int delayless_switch = OPEN; if (load_rr_graph) { const auto& rr_switches = device_ctx.rr_graph.rr_switch(); - for (size_t switch_id = 0; switch_id < rr_switches.size(); switch_id++){ + for (size_t switch_id = 0; switch_id < rr_switches.size(); switch_id++) { const auto& rr_switch = rr_switches[RRSwitchId(switch_id)]; if (rr_switch.name.find("delayless") != std::string::npos) { delayless_switch = static_cast(switch_id); @@ -1925,7 +1880,7 @@ void rr_graph_externals(const std::vector& segment_inf, static std::vector> alloc_and_load_perturb_ipins(const int L_num_types, const int num_seg_types, - const int* sets_per_seg_type, + const std::vector& sets_per_seg_type, const std::vector>& Fc_in, const std::vector>& Fc_out, const enum e_directionality directionality) { @@ -1976,33 +1931,27 @@ static std::vector> alloc_and_load_perturb_ipins(const int L_n return result; } -static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, - int* num_seg_details) { - t_seg_details* seg_details = new t_seg_details[1]; - - seg_details->index = 0; - seg_details->abs_index = 0; - seg_details->length = 1; - seg_details->arch_wire_switch = global_route_switch; - seg_details->arch_opin_switch = global_route_switch; - seg_details->longline = false; - seg_details->direction = Direction::BIDIR; - seg_details->Cmetal = 0.0; - seg_details->Rmetal = 0.0; - seg_details->start = 1; - seg_details->cb = std::make_unique(1); - seg_details->cb[0] = true; - seg_details->sb = std::make_unique(2); - seg_details->sb[0] = true; - seg_details->sb[1] = true; - seg_details->group_size = 1; - seg_details->group_start = 0; - seg_details->seg_start = -1; - seg_details->seg_end = -1; - - if (num_seg_details) { - *num_seg_details = 1; - } +static std::vector alloc_and_load_global_route_seg_details(const int global_route_switch) { + std::vector seg_details(1); + + seg_details[0].index = 0; + seg_details[0].abs_index = 0; + seg_details[0].length = 1; + seg_details[0].arch_wire_switch = global_route_switch; + seg_details[0].arch_opin_switch = global_route_switch; + seg_details[0].longline = false; + seg_details[0].direction = Direction::BIDIR; + seg_details[0].Cmetal = 0.0; + seg_details[0].Rmetal = 0.0; + seg_details[0].start = 1; + seg_details[0].cb = std::make_unique(1); + seg_details[0].cb[0] = true; + seg_details[0].sb = std::make_unique(2); + seg_details[0].sb[0] = true; + seg_details[0].sb[1] = true; + seg_details[0].group_size = 1; + seg_details[0].group_start = 0; + return seg_details; } @@ -2010,7 +1959,7 @@ static t_seg_details* alloc_and_load_global_route_seg_details(const int global_r std::vector> alloc_and_load_actual_fc(const std::vector& types, const int max_pins, const std::vector& segment_inf, - const int* sets_per_seg_type, + const std::vector& sets_per_seg_type, const t_chan_width* nodes_per_chan, const e_fc_type fc_type, const enum e_directionality directionality, @@ -2030,7 +1979,7 @@ std::vector> alloc_and_load_actual_fc(const std::vectorx_max % fac) == 0 && (nodes_per_chan->y_max % fac) == 0); - for (const auto& type : types) { //Skip EMPTY + for (const t_physical_tile_type& type : types) { //Skip EMPTY int itype = type.index; for (const t_fc_specification& fc_spec : type.fc_specs) { @@ -2048,7 +1997,7 @@ std::vector> alloc_and_load_actual_fc(const std::vector alloc_and_load_rr_graph(RRGraphBuilder const enum e_directionality directionality, bool* Fc_clipped, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, bool is_global_graph, const enum e_clock_modeling clock_modeling, bool /*is_flat*/, @@ -2173,7 +2122,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder *Fc_clipped = false; /* This function is called to build the general routing graph resoruces. Thus, - the edges are not remapped yet.*/ + * the edges are not remapped yet.*/ bool switches_remapped = false; int num_edges = 0; @@ -2221,7 +2170,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } } - VTR_LOGV(route_verbosity > 1,"SOURCE->OPIN and IPIN->SINK edge count:%d\n", num_edges); + VTR_LOGV(route_verbosity > 1, "SOURCE->OPIN and IPIN->SINK edge count:%d\n", num_edges); num_edges = 0; /* Build opins */ int rr_edges_before_directs = 0; @@ -2258,8 +2207,8 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } } - VTR_LOGV(route_verbosity > 1,"OPIN->CHANX/CHANY edge count before creating direct connections: %d\n", rr_edges_before_directs); - VTR_LOGV(route_verbosity > 1,"OPIN->CHANX/CHANY edge count after creating direct connections: %d\n", num_edges); + VTR_LOGV(route_verbosity > 1, "OPIN->CHANX/CHANY edge count before creating direct connections: %d\n", rr_edges_before_directs); + VTR_LOGV(route_verbosity > 1, "OPIN->CHANX/CHANY edge count after creating direct connections: %d\n", num_edges); num_edges = 0; /* Build channels */ @@ -2269,14 +2218,14 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder vtr::NdMatrix num_of_3d_conns_custom_SB; t_rr_edge_info_set des_3d_rr_edges_to_create; - if(grid.get_num_layers() > 1 && sb_conn_map != nullptr){ - num_of_3d_conns_custom_SB.resize(std::array{grid.width(), grid.height()}, 0); + if (grid.get_num_layers() > 1 && sb_conn_map != nullptr) { + num_of_3d_conns_custom_SB.resize(std::array{grid.width(), grid.height()}, 0); } for (size_t i = 0; i < grid.width() - 1; ++i) { for (size_t j = 0; j < grid.height() - 1; ++j) { for (int layer = 0; layer < grid.get_num_layers(); ++layer) { - auto &device_ctx = g_vpr_ctx.device(); + auto& device_ctx = g_vpr_ctx.device(); /* Skip the current die if architecture file specifies that it doesn't require inter-cluster programmable resource routing */ if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) { continue; @@ -2338,15 +2287,14 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } } - if(grid.get_num_layers() > 1 && sb_conn_map != nullptr){ + if (grid.get_num_layers() > 1 && sb_conn_map != nullptr) { uniquify_edges(des_3d_rr_edges_to_create); alloc_and_load_edges(rr_graph_builder, des_3d_rr_edges_to_create); num_edges += des_3d_rr_edges_to_create.size(); des_3d_rr_edges_to_create.clear(); } - - VTR_LOGV(route_verbosity > 1,"CHAN->CHAN type edge count:%d\n", num_edges); + VTR_LOGV(route_verbosity > 1, "CHAN->CHAN type edge count:%d\n", num_edges); num_edges = 0; std::function update_chan_width = [](t_chan_width*) noexcept {}; @@ -2733,7 +2681,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_y, const DeviceGrid& grid, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, const int num_seg_types) { //Don't connect pins which are not adjacent to channels around the perimeter if ((i == 0 && side != RIGHT) @@ -2796,7 +2744,8 @@ void free_rr_graph() { * allocated, as ALL the chunk allocated data is already free! */ auto& device_ctx = g_vpr_ctx.mutable_device(); - device_ctx.read_rr_graph_filename.clear(); + device_ctx.loaded_rr_graph_filename.clear(); + device_ctx.loaded_rr_edge_override_filename.clear(); device_ctx.rr_graph_builder.clear(); @@ -2959,11 +2908,11 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder, float delay = g_vpr_ctx.device().all_sw_inf.at(sw_idx).Tdel(); bool is_new_sw; std::tie(is_new_sw, sw_idx) = find_create_intra_cluster_sw(rr_graph_builder, - all_sw_inf, - R_minW_nmos, - R_minW_pmos, - switches_remapped, - delay); + all_sw_inf, + R_minW_nmos, + R_minW_pmos, + switches_remapped, + delay); } rr_edges_to_create.emplace_back(parent_pin_node_id, conn_pin_node_id, sw_idx, switches_remapped); } @@ -3170,7 +3119,7 @@ static float get_min_delay_to_chain(t_physical_tile_type_ptr physical_type, return min_delay; } -static std::unordered_set get_chain_pins(std::vector chain) { +static std::unordered_set get_chain_pins(const std::vector& chain) { std::unordered_set chain_pins; for (auto node : chain) { chain_pins.insert(node.pin_physical_num); @@ -3282,10 +3231,10 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, } if (to_seg_details->length() > 0) { get_track_to_tracks(rr_graph_builder, layer, chan_coord, start, track, chan_type, chan_coord, - opposite_chan_type, seg_dimension, max_opposite_chan_width, grid, + opposite_chan_type, seg_dimension, max_opposite_chan_width, grid, Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create, des_3d_rr_edges_to_create, from_seg_details, to_seg_details, opposite_chan_details, - directionality,custom_3d_sb_fanin_fanout,delayless_switch, + directionality, custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map); } } @@ -3302,10 +3251,10 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, } if (to_seg_details->length() > 0) { get_track_to_tracks(rr_graph_builder, layer, chan_coord, start, track, chan_type, chan_coord + 1, - opposite_chan_type, seg_dimension, max_opposite_chan_width, grid, + opposite_chan_type, seg_dimension, max_opposite_chan_width, grid, Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create, des_3d_rr_edges_to_create, from_seg_details, to_seg_details, opposite_chan_details, - directionality,custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map); + directionality, custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map); } } @@ -3334,10 +3283,10 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, } if (to_seg_details->length() > 0) { get_track_to_tracks(rr_graph_builder, layer, chan_coord, start, track, chan_type, target_seg, - chan_type, seg_dimension, max_chan_width, grid, + chan_type, seg_dimension, max_chan_width, grid, Fs_per_side, sblock_pattern, num_of_3d_conns_custom_SB, node, rr_edges_to_create, des_3d_rr_edges_to_create, from_seg_details, to_seg_details, from_chan_details, - directionality,custom_3d_sb_fanin_fanout, delayless_switch, + directionality, custom_3d_sb_fanin_fanout, delayless_switch, switch_block_conn, sb_conn_map); } } @@ -3435,18 +3384,18 @@ void alloc_and_load_edges(RRGraphBuilder& rr_graph_builder, const t_rr_edge_info static vtr::NdMatrix, 5> alloc_and_load_pin_to_track_map(const e_pin_type pin_type, const vtr::Matrix& Fc, const t_physical_tile_type_ptr tile_type, - const std::set type_layer, + const std::set& type_layer, const std::vector& perturb_switch_pattern, const e_directionality directionality, const std::vector& seg_inf, - const int* sets_per_seg_type) { + const std::vector& sets_per_seg_type) { /* allocate 'result' matrix and initialize entries to OPEN. also allocate and intialize matrix which will be * used to index into the correct entries when loading up 'result' */ auto& grid = g_vpr_ctx.device().grid; auto result = vtr::NdMatrix, 5>({ - size_t(tile_type->num_pins), //[0..num_pins-1] - size_t(tile_type->width), //[0..width-1] - size_t(tile_type->height), //[0..height-1] + size_t(tile_type->num_pins), //[0..num_pins-1] + size_t(tile_type->width), //[0..width-1] + size_t(tile_type->height), //[0..height-1] size_t(grid.get_num_layers()), //[0..layer-1] 4, //[0..sides-1] }); @@ -3536,12 +3485,12 @@ static vtr::NdMatrix alloc_and_load_pin_to_seg_type(const e_pin_type pin } auto tracks_connected_to_pin = vtr::NdMatrix({ - size_t(tile_type->num_pins), //[0..num_pins-1] - size_t(tile_type->width), //[0..width-1] - size_t(tile_type->height), //[0..height-1] + size_t(tile_type->num_pins), //[0..num_pins-1] + size_t(tile_type->width), //[0..width-1] + size_t(tile_type->height), //[0..height-1] size_t(grid.get_num_layers()), //[0..layer-1] NUM_2D_SIDES, //[0..NUM_2D_SIDES-1] - size_t(max_Fc) //[0..Fc-1] + size_t(max_Fc) //[0..Fc-1] }, OPEN); //Unconnected @@ -3550,8 +3499,8 @@ static vtr::NdMatrix alloc_and_load_pin_to_seg_type(const e_pin_type pin //Type->num_pins) if a logical pin has multiple specified physical //pinlocations (i.e. appears on multiple sides of the block) auto num_dir = vtr::NdMatrix({ - size_t(tile_type->width), //[0..width-1] - size_t(tile_type->height), //[0..height-1] + size_t(tile_type->width), //[0..width-1] + size_t(tile_type->height), //[0..height-1] size_t(grid.get_num_layers()), //[0..layer-1] NUM_2D_SIDES //[0..NUM_2D_SIDES-1] }, @@ -3565,16 +3514,16 @@ static vtr::NdMatrix alloc_and_load_pin_to_seg_type(const e_pin_type pin auto dir_list = vtr::NdMatrix({ size_t(tile_type->width), //[0..width-1] size_t(tile_type->height), //[0..height-1] - size_t(grid.get_num_layers()), //[0..layer-1] - NUM_2D_SIDES, //[0..NUM_2D_SIDES-1] + size_t(grid.get_num_layers()), //[0..layer-1] + NUM_2D_SIDES, //[0..NUM_2D_SIDES-1] size_t(tile_type->num_pins) * size_t(grid.get_num_layers()) //[0..num_pins * num_layers-1] }, -1); //Defensive coding: Initialize to invalid //Number of currently assigned physical pins auto num_done_per_dir = vtr::NdMatrix({ - size_t(tile_type->width), //[0..width-1] - size_t(tile_type->height), //[0..height-1] + size_t(tile_type->width), //[0..width-1] + size_t(tile_type->height), //[0..height-1] size_t(grid.get_num_layers()), //[0..layer-1] NUM_2D_SIDES //[0..NUM_2D_SIDES-1] }, @@ -4068,7 +4017,7 @@ static void load_perturbed_connection_block_pattern(vtr::NdMatrix& track int layer = pin_locations[i].layer_offset; int pin_Fc = Fc[pin][seg_index]; - int Fc_dense = ( pin_Fc / 2) + 1; + int Fc_dense = (pin_Fc / 2) + 1; int Fc_sparse = pin_Fc - Fc_dense; int Fc_half[2]; @@ -4146,7 +4095,7 @@ static void check_all_tracks_reach_pins(t_logical_block_type_ptr type, static vtr::NdMatrix, 5> alloc_and_load_track_to_pin_lookup(vtr::NdMatrix, 5> pin_to_track_map, const vtr::Matrix& Fc, const t_physical_tile_type_ptr tile_type, - const std::set type_layer, + const std::set& type_layer, const int type_width, const int type_height, const int num_pins, @@ -4235,7 +4184,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, bool* Fc_clipped, const t_unified_to_parallel_seg_index& seg_index_map, const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs, + const std::vector& clb_to_clb_directs, const int num_seg_types, int& rr_edge_count) { /* @@ -4344,21 +4293,18 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * This data structure supplements the the info in the "directs" data structure * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one */ -t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { - t_clb_to_clb_directs* clb_to_clb_directs; - t_physical_tile_type_ptr physical_tile = nullptr; - t_physical_tile_port tile_port; +std::vector alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { auto& device_ctx = g_vpr_ctx.device(); const int num_directs = directs.size(); - clb_to_clb_directs = new t_clb_to_clb_directs[num_directs]; + std::vector clb_to_clb_directs(num_directs); for (int i = 0; i < num_directs; i++) { //clb_to_clb_directs[i].from_clb_type; clb_to_clb_directs[i].from_clb_pin_start_index = 0; clb_to_clb_directs[i].from_clb_pin_end_index = 0; - //clb_to_clb_directs[i]. t_physical_tile_type_ptr to_clb_type; + //clb_to_clb_directs[i].to_clb_type; clb_to_clb_directs[i].to_clb_pin_start_index = 0; clb_to_clb_directs[i].to_clb_pin_end_index = 0; clb_to_clb_directs[i].switch_index = 0; @@ -4367,20 +4313,15 @@ t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, - const t_clb_to_clb_directs* clb_to_clb_directs) { + const std::vector& clb_to_clb_directs) { auto& device_ctx = g_vpr_ctx.device(); t_physical_tile_type_ptr curr_type = device_ctx.grid.get_physical_type({x, y, layer}); @@ -5135,15 +5069,15 @@ static std::pair find_create_intra_cluster_sw(RRGraphBuilder& rr_grap // If this assumption proven to not be accurate, the implementation needs to be changed. VTR_ASSERT(arch_sw.fixed_Tdel()); - t_rr_switch_inf new_rr_switch_inf = create_rr_switch_from_arch_switch(create_internal_arch_sw(delay), - R_minW_nmos, - R_minW_pmos); + t_rr_switch_inf new_rr_switch_inf = create_rr_switch_from_arch_switch(create_internal_arch_sw(delay), + R_minW_nmos, + R_minW_pmos); RRSwitchId rr_switch_id = rr_graph.add_rr_switch(new_rr_switch_inf); /*If the switch found inside the cluster has not seen before and RR graph is not read from a file, - we need to add this switch to switch_fanin_remap data strcutre which is used later to remap switch IDs - from architecture ID to RR graph switch ID. The reason why we don't this when RR graph is read from a file - is that in that case, the switch IDs of edges are alreay RR graph switch IDs. */ + * we need to add this switch to switch_fanin_remap data strcutre which is used later to remap switch IDs + * from architecture ID to RR graph switch ID. The reason why we don't this when RR graph is read from a file + * is that in that case, the switch IDs of edges are alreay RR graph switch IDs. */ auto& switch_fanin_remap = g_vpr_ctx.mutable_device().switch_fanin_remap; switch_fanin_remap.push_back({{UNDEFINED, size_t(rr_switch_id)}}); diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index 0d074f95bb8..b92db8005ea 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -21,7 +21,7 @@ enum { RR_GRAPH_WARN_CHAN_Y_WIDTH_CHANGED = 0x03 }; -void create_rr_graph(const t_graph_type graph_type, +void create_rr_graph(e_graph_type graph_type, const std::vector& block_types, const DeviceGrid& grid, const t_chan_width& nodes_per_chan, @@ -62,12 +62,12 @@ void rr_graph_externals(const std::vector& segment_inf, int wire_to_rr_ipin_switch, enum e_base_cost_type base_cost_type); -t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); +std::vector alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); std::vector> alloc_and_load_actual_fc(const std::vector& types, const int max_pins, const std::vector& segment_inf, - const int* sets_per_seg_type, + const std::vector& sets_per_seg_type, const t_chan_width* nodes_per_chan, const e_fc_type fc_type, const enum e_directionality directionality, diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index cb8b729b05f..81763f8cdb6 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1,9 +1,9 @@ #include +#include "describe_rr_node.h" +#include "physical_types_util.h" #include "vtr_util.h" #include "vtr_assert.h" -#include "vtr_log.h" -#include "vtr_memory.h" #include "vpr_types.h" #include "vpr_error.h" @@ -11,9 +11,7 @@ #include "globals.h" #include "rr_graph_utils.h" #include "rr_graph2.h" -#include "rr_graph.h" #include "rr_graph_sbox.h" -#include "read_xml_arch_file.h" #include "rr_types.h" constexpr short UN_SET = -1; @@ -257,56 +255,35 @@ static bool should_apply_switch_override(int switch_override); /******************** Subroutine definitions *******************************/ -/* This assigns tracks (individually or pairs) to segment types. - * It tries to match requested ratio. If use_full_seg_groups is - * true, then segments are assigned only in multiples of their - * length. This is primarily used for making a tileable unidir - * layout. The effect of using this is that the number of tracks - * requested will not always be met and the result will sometimes - * be over and sometimes under. - * The pattern when using use_full_seg_groups is to keep adding - * one group of the track type that wants the largest number of - * groups of tracks. Each time a group is assigned, the types - * demand is reduced by 1 unit. The process stops when we are - * no longer less than the requested number of tracks. As a final - * step, if we were closer to target before last more, undo it - * and end up with a result that uses fewer tracks than given. */ -std::unique_ptr get_seg_track_counts(const int num_sets, - const std::vector& segment_inf, - const bool use_full_seg_groups) { - std::unique_ptr result; - int imax, freq_sum, assigned, size; - double scale, max, reduce; - - result = std::make_unique(segment_inf.size()); - std::vector demand(segment_inf.size()); - - /* Scale factor so we can divide by any length - * and still use integers */ - scale = 1; - freq_sum = 0; +std::vector get_seg_track_counts(int num_sets, + const std::vector& segment_inf, + bool use_full_seg_groups) { + // Scale factor so we can divide by any length and still use integers + double scale = 1; + int freq_sum = 0; for (size_t i = 0; i < segment_inf.size(); ++i) { scale *= segment_inf[i].length; freq_sum += segment_inf[i].frequency; } - reduce = scale * freq_sum; + const double reduce = scale * freq_sum; - /* Init assignments to 0 and set the demand values */ + // Init assignments to 0 and set the demand values + std::vector result(segment_inf.size(), 0); + std::vector demand(segment_inf.size()); for (size_t i = 0; i < segment_inf.size(); ++i) { - result[i] = 0; demand[i] = scale * num_sets * segment_inf[i].frequency; if (use_full_seg_groups) { demand[i] /= segment_inf[i].length; } } - /* Keep assigning tracks until we use them up */ - assigned = 0; - size = 0; - imax = 0; + // Keep assigning tracks until we use them up + int assigned = 0; + int imax = 0; + int size = 0; while (assigned < num_sets) { - /* Find current maximum demand */ - max = 0; + // Find current maximum demand + double max = 0; for (size_t i = 0; i < segment_inf.size(); ++i) { if (demand[i] > max) { imax = i; @@ -314,19 +291,18 @@ std::unique_ptr get_seg_track_counts(const int num_sets, } } - /* Assign tracks to the type and reduce the types demand */ - size = (use_full_seg_groups ? segment_inf[imax].length : 1); + // Assign tracks to the type and reduce the types demand + size = use_full_seg_groups ? segment_inf[imax].length : 1; demand[imax] -= reduce; result[imax] += size; assigned += size; } - /* Undo last assignment if we were closer to goal without it */ + // Undo last assignment if we were closer to goal without it if ((assigned - num_sets) > (size / 2)) { result[imax] -= size; } - /* This must be freed by caller */ return result; } @@ -345,53 +321,11 @@ int get_parallel_seg_index(const int abs_index, return index; } -/* Returns an array of tracks per segment, with matching indices to segment_inf by combining * - * sets per segment for each direction. This is a helper function to avoid having to refactor * - * alot of the functions inside rr_graph.cpp & rr_graph2.cpp to model different horizontal and vertical * - * channel widths. */ -std::unique_ptr get_ordered_seg_track_counts(const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - const std::vector& segment_inf, - const std::unique_ptr& segment_sets_x, - const std::unique_ptr& segment_sets_y) { - std::unordered_map all_segs_index; - std::unique_ptr ordered_seg_track_counts; - ordered_seg_track_counts = std::make_unique(segment_inf.size()); - - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - all_segs_index.insert(std::make_pair(segment_inf[iseg], iseg)); - } - for (size_t iseg_x = 0; iseg_x < segment_inf_x.size(); ++iseg_x) { - auto seg_in_x_dir = all_segs_index.find(segment_inf_x[iseg_x]); - if (seg_in_x_dir != all_segs_index.end()) { - ordered_seg_track_counts[seg_in_x_dir->second] = segment_sets_x[iseg_x]; - } else { - VTR_ASSERT_MSG(seg_in_x_dir != all_segs_index.end(), - "Segment in the x-direction must be a part of all segments."); - } - } - for (size_t iseg_y = 0; iseg_y < segment_inf_y.size(); ++iseg_y) { - if (segment_inf_y[iseg_y].parallel_axis == BOTH_AXIS) { /*Avoid counting segments in both horizontal and vertical direction twice*/ - continue; - } - auto seg_in_y_dir = all_segs_index.find(segment_inf_y[iseg_y]); - if (seg_in_y_dir != all_segs_index.end()) { - ordered_seg_track_counts[seg_in_y_dir->second] = segment_sets_y[iseg_y]; - } else { - VTR_ASSERT_MSG(seg_in_y_dir != all_segs_index.end(), - "Segment in the x-direction must be a part of all segments."); - } - } - - return ordered_seg_track_counts; -} - -t_seg_details* alloc_and_load_seg_details(int* max_chan_width, - const int max_len, - const std::vector& segment_inf, - const bool use_full_seg_groups, - const enum e_directionality directionality, - int* num_seg_details) { +std::vector alloc_and_load_seg_details(int* max_chan_width, + const int max_len, + const std::vector& segment_inf, + const bool use_full_seg_groups, + const enum e_directionality directionality) { /* Allocates and loads the seg_details data structure. Max_len gives the * * maximum length of a segment (dimension of array). The code below tries * * to: * @@ -401,16 +335,8 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, * (3) stagger the connection and switch boxes on different long lines, * * as they will not be staggered by different segment start points. */ - int cur_track, ntracks, itrack, length, j, index; - int fac, num_sets, tmp; - int arch_wire_switch, arch_opin_switch, arch_wire_switch_dec, arch_opin_switch_dec; - int arch_opin_between_dice_switch; - int group_start, first_track; - std::unique_ptr sets_per_seg_type; - t_seg_details* seg_details = nullptr; - bool longline; - - /* Unidir tracks are assigned in pairs, and bidir tracks individually */ + // Unidir tracks are assigned in pairs, and bidir tracks individually + int fac; if (directionality == BI_DIRECTIONAL) { fac = 1; } else { @@ -422,51 +348,45 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Routing channel width must be divisible by %d (channel width was %d)", fac, *max_chan_width); } - /* Map segment type fractions and groupings to counts of tracks */ - sets_per_seg_type = get_seg_track_counts((*max_chan_width / fac), - segment_inf, use_full_seg_groups); + // Map segment type fractions and groupings to counts of tracks + const std::vector sets_per_seg_type = get_seg_track_counts((*max_chan_width / fac), + segment_inf, use_full_seg_groups); - /* Count the number tracks actually assigned. */ - tmp = 0; - for (size_t i = 0; i < segment_inf.size(); ++i) { - tmp += sets_per_seg_type[i] * fac; - } + // Count the number tracks actually assigned. + int tmp = std::accumulate(sets_per_seg_type.begin(), sets_per_seg_type.end(), 0) * fac; VTR_ASSERT(use_full_seg_groups || (tmp == *max_chan_width)); *max_chan_width = tmp; - seg_details = new t_seg_details[*max_chan_width]; + std::vector seg_details(*max_chan_width); - /* Setup the seg_details data */ - cur_track = 0; + // Setup the seg_details data + int cur_track = 0; for (size_t i = 0; i < segment_inf.size(); ++i) { - first_track = cur_track; + int first_track = cur_track; - num_sets = sets_per_seg_type[i]; - ntracks = fac * num_sets; + const int num_sets = sets_per_seg_type[i]; + const int ntracks = fac * num_sets; if (ntracks < 1) { continue; } /* Avoid divide by 0 if ntracks */ - longline = segment_inf[i].longline; - length = segment_inf[i].length; - if (longline) { - length = max_len; - } - - arch_wire_switch = segment_inf[i].arch_wire_switch; - arch_opin_switch = segment_inf[i].arch_opin_switch; - arch_wire_switch_dec = segment_inf[i].arch_wire_switch_dec; - arch_opin_switch_dec = segment_inf[i].arch_opin_switch_dec; - arch_opin_between_dice_switch = segment_inf[i].arch_opin_between_dice_switch; + const bool longline = segment_inf[i].longline; + const int length = (longline) ? max_len : segment_inf[i].length; + + const int arch_wire_switch = segment_inf[i].arch_wire_switch; + const int arch_opin_switch = segment_inf[i].arch_opin_switch; + const int arch_wire_switch_dec = segment_inf[i].arch_wire_switch_dec; + const int arch_opin_switch_dec = segment_inf[i].arch_opin_switch_dec; + const int arch_inter_die_switch = segment_inf[i].arch_inter_die_switch; VTR_ASSERT((arch_wire_switch == arch_opin_switch && arch_wire_switch_dec == arch_opin_switch_dec) || (directionality != UNI_DIRECTIONAL)); - /* Set up the tracks of same type */ - group_start = 0; - for (itrack = 0; itrack < ntracks; itrack++) { - /* set the name of the segment type this track belongs to */ + // Set up the tracks of same type + int group_start = 0; + for (int itrack = 0; itrack < ntracks; itrack++) { + // set the name of the segment type this track belongs to seg_details[cur_track].type_name = segment_inf[i].name; - /* Remember the start track of the current wire group */ + // Remember the start track of the current wire group if ((itrack / fac) % length == 0 && (itrack % fac) == 0) { group_start = cur_track; } @@ -478,12 +398,10 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, * pin mappings should be aware of this when choosing an * intelligent way of connecting pins and tracks. * cur_track is used as an offset so that extra tracks - * from different segment types are hopefully better - * balanced. */ + * from different segment types are hopefully better balanced. */ seg_details[cur_track].start = (cur_track / fac) % length + 1; - /* These properties are used for vpr_to_phy_track to determine - * * twisting of wires. */ + // These properties are used for vpr_to_phy_track to determine twisting of wires. seg_details[cur_track].group_start = group_start; seg_details[cur_track].group_size = std::min(ntracks + first_track - group_start, length * fac); VTR_ASSERT(0 == seg_details[cur_track].group_size % fac); @@ -491,28 +409,25 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, seg_details[cur_track].group_size = length * fac; } - seg_details[cur_track].seg_start = -1; - seg_details[cur_track].seg_end = -1; - /* Setup the cb and sb patterns. Global route graphs can't depopulate cb and sb * since this is a property of a detailed route. */ seg_details[cur_track].cb = std::make_unique(length); seg_details[cur_track].sb = std::make_unique(length + 1); - for (j = 0; j < length; ++j) { + for (int j = 0; j < length; ++j) { if (seg_details[cur_track].longline) { seg_details[cur_track].cb[j] = true; } else { - /* Use the segment's pattern. */ - index = j % segment_inf[i].cb.size(); + // Use the segment's pattern. + int index = j % segment_inf[i].cb.size(); seg_details[cur_track].cb[j] = segment_inf[i].cb[index]; } } - for (j = 0; j < (length + 1); ++j) { + for (int j = 0; j < (length + 1); ++j) { if (seg_details[cur_track].longline) { seg_details[cur_track].sb[j] = true; } else { /* Use the segment's pattern. */ - index = j % segment_inf[i].sb.size(); + int index = j % segment_inf[i].sb.size(); seg_details[cur_track].sb[j] = segment_inf[i].sb[index]; } } @@ -521,7 +436,7 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, seg_details[cur_track].Cmetal = segment_inf[i].Cmetal; //seg_details[cur_track].Cmetal_per_m = segment_inf[i].Cmetal_per_m; - seg_details[cur_track].arch_opin_between_dice_switch = arch_opin_between_dice_switch; + seg_details[cur_track].arch_inter_die_switch = arch_inter_die_switch; if (BI_DIRECTIONAL == directionality) { seg_details[cur_track].direction = Direction::BIDIR; @@ -530,13 +445,12 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, seg_details[cur_track].direction = (itrack % 2) ? Direction::DEC : Direction::INC; } - //check for directionality to set the wire_switch and opin_switch - //if not specified in the architecture file, we will use a same mux for both directions - if (seg_details[cur_track].direction == Direction::INC || seg_details[cur_track].direction == Direction::BIDIR || arch_wire_switch_dec == -1){ + // check for directionality to set the wire_switch and opin_switch + // if not specified in the architecture file, we will use a same mux for both directions + if (seg_details[cur_track].direction == Direction::INC || seg_details[cur_track].direction == Direction::BIDIR || arch_wire_switch_dec == -1) { seg_details[cur_track].arch_opin_switch = arch_opin_switch; seg_details[cur_track].arch_wire_switch = arch_wire_switch; - } - else { + } else { VTR_ASSERT(seg_details[cur_track].direction == Direction::DEC); seg_details[cur_track].arch_opin_switch = arch_opin_switch_dec; seg_details[cur_track].arch_wire_switch = arch_wire_switch_dec; @@ -549,43 +463,35 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, } } /* End for each segment type. */ - if (num_seg_details) { - *num_seg_details = cur_track; - } + seg_details.resize(cur_track); return seg_details; } /* Allocates and loads the chan_details data structure, a 2D array of * seg_details structures. This array is used to handle unique seg_details * (ie. channel segments) for each horizontal and vertical channel. */ - void alloc_and_load_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, - const int num_seg_details_x, - const int num_seg_details_y, - const t_seg_details* seg_details_x, - const t_seg_details* seg_details_y, + const t_chan_width& nodes_per_chan, + const std::vector& seg_details_x, + const std::vector& seg_details_y, t_chan_details& chan_details_x, t_chan_details& chan_details_y) { - chan_details_x = init_chan_details(grid, nodes_per_chan, - num_seg_details_x, seg_details_x, X_AXIS); - chan_details_y = init_chan_details(grid, nodes_per_chan, - num_seg_details_y, seg_details_y, Y_AXIS); + chan_details_x = init_chan_details(grid, nodes_per_chan, seg_details_x, X_AXIS); + chan_details_y = init_chan_details(grid, nodes_per_chan, seg_details_y, Y_AXIS); /* Adjust segment start/end based on obstructed channels, if any */ - adjust_chan_details(grid, nodes_per_chan, - chan_details_x, chan_details_y); + adjust_chan_details(grid, nodes_per_chan, chan_details_x, chan_details_y); } t_chan_details init_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, - const int num_seg_details, - const t_seg_details* seg_details, + const t_chan_width& nodes_per_chan, + const std::vector& seg_details, const enum e_parallel_axis seg_parallel_axis) { + const int num_seg_details = (int)seg_details.size(); if (seg_parallel_axis == X_AXIS) { - VTR_ASSERT(num_seg_details <= nodes_per_chan->x_max); + VTR_ASSERT(num_seg_details <= nodes_per_chan.x_max); } else if (seg_parallel_axis == Y_AXIS) { - VTR_ASSERT(num_seg_details <= nodes_per_chan->y_max); + VTR_ASSERT(num_seg_details <= nodes_per_chan.y_max); } t_chan_details chan_details({grid.width(), grid.height(), size_t(num_seg_details)}); @@ -611,11 +517,11 @@ t_chan_details init_chan_details(const DeviceGrid& grid, p_seg_details[i].set_seg_end(seg_end); if (seg_parallel_axis == X_AXIS) { - if (i >= nodes_per_chan->x_list[y]) { + if (i >= nodes_per_chan.x_list[y]) { p_seg_details[i].set_length(0); } } else if (seg_parallel_axis == Y_AXIS) { - if (i >= nodes_per_chan->y_list[x]) { + if (i >= nodes_per_chan.y_list[x]) { p_seg_details[i].set_length(0); } } @@ -626,7 +532,7 @@ t_chan_details init_chan_details(const DeviceGrid& grid, } void adjust_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, t_chan_details& chan_details_x, t_chan_details& chan_details_y) { for (size_t y = 0; y <= grid.height() - 2; ++y) { //-2 for no perim channels @@ -657,18 +563,18 @@ void adjust_chan_details(const DeviceGrid& grid, void adjust_seg_details(const int x, const int y, const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, t_chan_details& chan_details, const enum e_parallel_axis seg_parallel_axis) { int seg_index = (seg_parallel_axis == X_AXIS ? x : y); int max_chan_width = 0; if (seg_parallel_axis == X_AXIS) { - max_chan_width = nodes_per_chan->x_max; + max_chan_width = nodes_per_chan.x_max; } else if (seg_parallel_axis == Y_AXIS) { - max_chan_width = nodes_per_chan->y_max; + max_chan_width = nodes_per_chan.y_max; } else { VTR_ASSERT(seg_parallel_axis == BOTH_AXIS); - max_chan_width = nodes_per_chan->max; + max_chan_width = nodes_per_chan.max; } for (int track = 0; track < max_chan_width; ++track) { @@ -702,14 +608,8 @@ void adjust_seg_details(const int x, } } -void free_chan_details(t_chan_details& chan_details_x, - t_chan_details& chan_details_y) { - chan_details_x.clear(); - chan_details_y.clear(); -} - -/* Returns the segment number at which the segment this track lies on * - * started. */ +/* Returns the segment number at which the segment this track lies on + * started. */ int get_seg_start(const t_chan_seg_details* seg_details, const int itrack, const int chan_num, @@ -717,16 +617,14 @@ int get_seg_start(const t_chan_seg_details* seg_details, int seg_start = 0; if (seg_details[itrack].seg_start() >= 0) { seg_start = seg_details[itrack].seg_start(); - } else { seg_start = 1; - if (false == seg_details[itrack].longline()) { + if (!seg_details[itrack].longline()) { int length = seg_details[itrack].length(); int start = seg_details[itrack].start(); - /* Start is guaranteed to be between 1 and length. Hence adding length to * - * the quantity in brackets below guarantees it will be nonnegative. */ - + /* Start is guaranteed to be between 1 and length. Hence, adding length to + * the quantity in brackets below guarantees it will be non-negative. */ VTR_ASSERT(start > 0); VTR_ASSERT(start <= length); @@ -740,6 +638,7 @@ int get_seg_start(const t_chan_seg_details* seg_details, } } } + return seg_start; } @@ -856,7 +755,7 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, continue; } - to_switch = (track_layer == opin_layer) ? seg_details[to_track].arch_wire_switch() : seg_details[to_track].arch_opin_between_dice_switch(); + to_switch = (track_layer == opin_layer) ? seg_details[to_track].arch_wire_switch() : seg_details[to_track].arch_inter_die_switch(); rr_edges_to_create.emplace_back(from_rr_node, to_node, to_switch, false); ++num_conn; @@ -947,11 +846,11 @@ int get_unidir_opin_connections(RRGraphBuilder& rr_graph_builder, } /* Add to the list. */ - auto to_switch = (opin_layer == track_layer) ? seg_details[inc_track].arch_opin_switch() : seg_details[inc_track].arch_opin_between_dice_switch(); + auto to_switch = (opin_layer == track_layer) ? seg_details[inc_track].arch_opin_switch() : seg_details[inc_track].arch_inter_die_switch(); rr_edges_to_create.emplace_back(from_rr_node, inc_inode_index, to_switch, false); ++num_edges; - to_switch = (opin_layer == track_layer) ? seg_details[dec_track].arch_opin_switch() : seg_details[dec_track].arch_opin_between_dice_switch(); + to_switch = (opin_layer == track_layer) ? seg_details[dec_track].arch_opin_switch() : seg_details[dec_track].arch_inter_die_switch(); rr_edges_to_create.emplace_back(from_rr_node, dec_inode_index, to_switch, false); ++num_edges; } @@ -1188,7 +1087,7 @@ static void load_chan_rr_indices(const int max_chan_width, const t_chan_details& chan_details, RRGraphBuilder& rr_graph_builder, int* index) { - auto& device_ctx = g_vpr_ctx.device(); + const auto& device_ctx = g_vpr_ctx.device(); for (int layer = 0; layer < grid.get_num_layers(); layer++) { /* Skip the current die if architecture file specifies that it doesn't require global resource routing */ @@ -1281,17 +1180,17 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m for (int iconn = 0; iconn < (int)conn_vector.size(); ++iconn) { //check if both from_node and to_node exists in the rr-graph //CHANY -> CHANX connection - if(check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, - conn_vector[iconn].from_wire_layer, CHANY, - conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, - CHANX)){ + if (check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, + conn_vector[iconn].from_wire_layer, CHANY, + conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, + CHANX)) { num_of_3d_conn++; } //CHANX -> CHANY connection - if(check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, - conn_vector[iconn].from_wire_layer, CHANX, - conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, - CHANY)){ + if (check_3d_SB_RRnodes(rr_graph_builder, x, y, conn_vector[iconn].from_wire, + conn_vector[iconn].from_wire_layer, CHANX, + conn_vector[iconn].to_wire, conn_vector[iconn].to_wire_layer, + CHANY)) { num_of_3d_conn++; } } @@ -1299,7 +1198,7 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m } } } - extra_nodes_per_switchblocks[x][y] += ((num_of_3d_conn + custom_3d_sb_fanin_fanout - 1)/ custom_3d_sb_fanin_fanout); + extra_nodes_per_switchblocks[x][y] += ((num_of_3d_conn + custom_3d_sb_fanin_fanout - 1) / custom_3d_sb_fanin_fanout); } } } @@ -1364,17 +1263,14 @@ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder, for (int x = 0; x < (int)grid.width(); x++) { for (int y = 0; y < (int)grid.height(); y++) { //Process each block from its root location - if (grid.get_width_offset({x, y, layer}) == 0 && grid.get_height_offset({x, y, layer}) == 0) { - t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, - y, - layer}); + if (grid.is_root_location({x, y, layer})) { + t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); + //Assign indices for SINKs and SOURCEs // Note that SINKS/SOURCES have no side, so we always use side 0 - std::vector class_num_vec; - std::vector pin_num_vec; + std::vector class_num_vec = get_tile_root_classes(physical_type); + std::vector pin_num_vec = get_tile_root_pins(physical_type); - class_num_vec = get_tile_root_classes(physical_type); - pin_num_vec = get_tile_root_pins(physical_type); add_classes_spatial_lookup(rr_graph_builder, physical_type, class_num_vec, @@ -1471,17 +1367,14 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, } } - for (auto pin_num : pin_num_vec) { + for (const int pin_num : pin_num_vec) { bool assigned_to_rr_node = false; - std::vector x_offset; - std::vector y_offset; - std::vector pin_sides; - std::tie(x_offset, y_offset, pin_sides) = get_pin_coordinates(physical_type_ptr, pin_num, wanted_sides); - auto pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); + const auto [x_offset, y_offset, pin_sides] = get_pin_coordinates(physical_type_ptr, pin_num, wanted_sides); + e_pin_type pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); for (int pin_coord_idx = 0; pin_coord_idx < (int)pin_sides.size(); pin_coord_idx++) { int x_tile = root_x + x_offset[pin_coord_idx]; int y_tile = root_y + y_offset[pin_coord_idx]; - auto side = pin_sides[pin_coord_idx]; + e_side side = pin_sides[pin_coord_idx]; if (pin_type == DRIVER) { rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, OPIN, pin_num, side); assigned_to_rr_node = true; @@ -1524,8 +1417,8 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, } } - for (auto class_num : class_num_vec) { - auto class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); + for (const int class_num : class_num_vec) { + e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); e_rr_type node_type = SINK; if (class_type == DRIVER) { node_type = SOURCE; @@ -1546,16 +1439,7 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, } } -/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder - * TODO: these building functions should only talk to a RRGraphBuilder object - * The biggest and fatal issue is - * - the rr_graph2.h is included in the rr_graph_storage.h, - * which is included in the rr_graph_builder.h - * If we include rr_graph_builder.h in rr_graph2.h, this creates a loop - * for C++ compiler to identify data structures, which cannot be solved!!! - * This will block us when putting the RRGraphBuilder object as an input arguement - * of this function - */ +/* As the rr_indices builders modify a local copy of indices, use the local copy in the builder */ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, const t_chan_width* nodes_per_chan, const DeviceGrid& grid, @@ -1594,8 +1478,8 @@ void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_build for (int layer = 0; layer < grid.get_num_layers(); layer++) { for (int x = 0; x < (int)grid.width(); x++) { for (int y = 0; y < (int)grid.height(); y++) { - //Process each block from it's root location - if (grid.get_width_offset({x, y, layer}) == 0 && grid.get_height_offset({x, y, layer}) == 0) { + //Process each block from its root location + if (grid.is_root_location({x, y, layer})) { t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer}); //Assign indices for SINKs and SOURCEs // Note that SINKS/SOURCES have no side, so we always use side 0 @@ -1875,7 +1759,6 @@ int get_track_to_pins(RRGraphBuilder& rr_graph_builder, } /* Check there is a connection and Fc map isn't wrong */ - /*int to_node = get_rr_node_index(L_rr_node_indices, x + width_offset, y + height_offset, IPIN, ipin, side);*/ RRNodeId to_node = rr_graph_builder.node_lookup().find_node(layer_index, x, y, IPIN, ipin, side); int switch_type = (layer_index == layer) ? wire_to_ipin_switch : wire_to_pin_between_dice_switch; if (to_node) { @@ -2100,7 +1983,7 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, if (Direction::INC == from_seg_details[from_track].direction() || BI_DIRECTIONAL == directionality) { num_conn += get_track_to_chan_seg(rr_graph_builder, layer, max_chan_width, from_track, to_chan, to_seg, to_type, from_side_b, to_side, - switch_override,custom_3d_sb_fanin_fanout, delayless_switch, + switch_override, custom_3d_sb_fanin_fanout, delayless_switch, sb_conn_map, num_of_3d_conns_custom_SB, from_rr_node, rr_edges_to_create, des_3d_rr_edges_to_create); } } else { @@ -2671,7 +2554,7 @@ static int vpr_to_phy_track(const int itrack, } t_sblock_pattern alloc_sblock_pattern_lookup(const DeviceGrid& grid, - t_chan_width* nodes_per_chan) { + const t_chan_width& nodes_per_chan) { /* loading up the sblock connection pattern matrix. It's a huge matrix because * for nonquantized W, it's impossible to make simple permutations to figure out * where muxes are and how to connect to them such that their sizes are balanced */ @@ -2686,14 +2569,14 @@ t_sblock_pattern alloc_sblock_pattern_lookup(const DeviceGrid& grid, VTR_ASSERT(grid.width() > 0); VTR_ASSERT(grid.height() > 0); //CHANGE THIS - VTR_ASSERT(nodes_per_chan->max >= 0); + VTR_ASSERT(nodes_per_chan.max >= 0); t_sblock_pattern sblock_pattern({{ grid.width() - 1, grid.height() - 1, 4, //From side 4, //To side - size_t(nodes_per_chan->max), + size_t(nodes_per_chan.max), 4 //to_mux, to_trac, alt_mux, alt_track }}, UN_SET); @@ -2705,7 +2588,7 @@ t_sblock_pattern alloc_sblock_pattern_lookup(const DeviceGrid& grid, void load_sblock_pattern_lookup(const int i, const int j, const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, const int /*Fs*/, @@ -2864,9 +2747,9 @@ void load_sblock_pattern_lookup(const int i, for (int ichan = 0; ichan < get_chan_width((e_side)side_cw, nodes_per_chan); ichan++) { int itrack = ichan; if (side_cw == TOP || side_cw == BOTTOM) { - itrack = ichan % nodes_per_chan->y_list[i]; + itrack = ichan % nodes_per_chan.y_list[i]; } else if (side_cw == RIGHT || side_cw == LEFT) { - itrack = ichan % nodes_per_chan->x_list[j]; + itrack = ichan % nodes_per_chan.x_list[j]; } if (incoming_wire_label[side_cw][itrack] != UN_SET) { @@ -2890,9 +2773,9 @@ void load_sblock_pattern_lookup(const int i, for (int ichan = 0; ichan < get_chan_width((e_side)side_ccw, nodes_per_chan); ichan++) { int itrack = ichan; if (side_ccw == TOP || side_ccw == BOTTOM) { - itrack = ichan % nodes_per_chan->y_list[i]; + itrack = ichan % nodes_per_chan.y_list[i]; } else if (side_ccw == RIGHT || side_ccw == LEFT) { - itrack = ichan % nodes_per_chan->x_list[j]; + itrack = ichan % nodes_per_chan.x_list[j]; } if (incoming_wire_label[side_ccw][itrack] != UN_SET) { @@ -3161,6 +3044,6 @@ static bool should_apply_switch_override(int switch_override) { return false; } -inline int get_chan_width(enum e_side side, const t_chan_width* nodes_per_chan) { - return (side == TOP || side == BOTTOM ? nodes_per_chan->y_max : nodes_per_chan->x_max); +inline int get_chan_width(enum e_side side, const t_chan_width& nodes_per_chan) { + return (side == TOP || side == BOTTOM ? nodes_per_chan.y_max : nodes_per_chan.x_max); } diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h index 348e5633708..71b7004197f 100644 --- a/vpr/src/route/rr_graph2.h +++ b/vpr/src/route/rr_graph2.h @@ -12,13 +12,6 @@ #include "device_grid.h" #include "get_parallel_segs.h" -/******************* Types shared by rr_graph2 functions *********************/ - -/* [0..grid.width()-1][0..grid.width()][0..3 (From side)] \ - * [0..3 (To side)][0...max_chan_width][0..3 (to_mux,to_trac,alt_mux,alt_track)] - * originally initialized to UN_SET until alloc_and_load_sb is called */ -typedef vtr::NdMatrix t_sblock_pattern; - /******************* Subroutines exported by rr_graph2.c *********************/ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder, @@ -63,21 +56,6 @@ bool verify_rr_node_indices(const DeviceGrid& grid, const vtr::vector& rr_indexed_data, const t_rr_graph_storage& rr_nodes, bool is_flat); - -//Returns all x-channel or y-channel wires at the specified location -std::vector get_rr_node_chan_wires_at_location(const t_rr_node_indices& L_rr_node_indices, - t_rr_type rr_type, - int x, - int y); - -//Return the first rr node of the specified type and coordinates -// For non-IPIN/OPIN types 'side' is ignored -int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices, - int x, - int y, - t_rr_type rr_type, - int ptc, - e_side side = NUM_2D_SIDES); /** * @brief goes through 3D custom switch blocks and counts how many connections are crossing dice for each switch block. * @@ -90,46 +68,36 @@ vtr::NdMatrix get_number_track_to_track_inter_die_conn(t_sb_connection_m const int custom_3d_sb_fanin_fanout, RRGraphBuilder& rr_graph_builder); -int find_average_rr_node_index(int device_width, - int device_height, - t_rr_type rr_type, - int ptc, - const t_rr_node_indices& L_rr_node_indices); - -t_seg_details* alloc_and_load_seg_details(int* max_chan_width, - const int max_len, - const std::vector& segment_inf, - const bool use_full_seg_groups, - const enum e_directionality directionality, - int* num_seg_details = nullptr); +std::vector alloc_and_load_seg_details(int* max_chan_width, + const int max_len, + const std::vector& segment_inf, + const bool use_full_seg_groups, + const enum e_directionality directionality); void alloc_and_load_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, - const int num_seg_details_x, - const int num_seg_details_y, - const t_seg_details* seg_details_x, - const t_seg_details* seg_details_y, + const t_chan_width& nodes_per_chan, + const std::vector& seg_details_x, + const std::vector& seg_details_y, t_chan_details& chan_details_x, t_chan_details& chan_details_y); + t_chan_details init_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, - const int num_seg_details, - const t_seg_details* seg_details, + const t_chan_width& nodes_per_chan, + const std::vector& seg_details, const enum e_parallel_axis seg_details_type); + void adjust_chan_details(const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, t_chan_details& chan_details_x, t_chan_details& chan_details_y); + void adjust_seg_details(const int x, const int y, const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, t_chan_details& chan_details, const enum e_parallel_axis seg_details_type); -void free_chan_details(t_chan_details& chan_details_x, - t_chan_details& chan_details_y); - int get_seg_start(const t_chan_seg_details* seg_details, const int itrack, const int chan_num, @@ -223,12 +191,12 @@ int get_track_to_tracks(RRGraphBuilder& rr_graph_builder, t_sb_connection_map* sb_conn_map); t_sblock_pattern alloc_sblock_pattern_lookup(const DeviceGrid& grid, - t_chan_width* nodes_per_chan); + const t_chan_width& nodes_per_chan); void load_sblock_pattern_lookup(const int i, const int j, const DeviceGrid& grid, - const t_chan_width* nodes_per_chan, + const t_chan_width& nodes_per_chan, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, const int Fs, @@ -239,15 +207,28 @@ int get_parallel_seg_index(const int abs, const t_unified_to_parallel_seg_index& index_map, const e_parallel_axis parallel_axis); -std::unique_ptr get_ordered_seg_track_counts(const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - const std::vector& segment_inf, - const std::unique_ptr& segment_sets_x, - const std::unique_ptr& segment_sets_y); - -std::unique_ptr get_seg_track_counts(const int num_sets, - const std::vector& segment_inf, - const bool use_full_seg_groups); +/** + * @brief Assigns routing tracks to each segment type based on their frequencies and lengths. + * + * This function determines how many routing tracks (or sets of tracks) to assign to each + * segment type in order to match the desired frequency distribution specified in + * the segment information. + * + * When @p use_full_seg_groups is true, the function assigns tracks in multiples of the + * segment length, which may result in a total track count that slightly overshoots or + * undershoots the target @p num_sets. The algorithm proceeds by: + * - Calculating the demand for each segment type. + * - Iteratively assigning tracks to the segment type with the highest remaining demand. + * - Optionally undoing the last assignment if it overshoots the target by more than half a group. + * + * @param num_sets Total number of track sets to assign. + * @param segment_inf Vector containing segment type information (frequency, length, etc.). + * @param use_full_seg_groups If true, assign tracks in full segment-length groups. + * @return A vector where each element indicates the number of tracks assigned to the corresponding segment type. + */ +std::vector get_seg_track_counts(int num_sets, + const std::vector& segment_inf, + bool use_full_seg_groups); void dump_seg_details(const t_chan_seg_details* seg_details, int max_chan_width, @@ -270,9 +251,5 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map, int max_chan_width, FILE* fp); -void add_to_rr_node_indices(t_rr_node_indices& rr_node_indices, const t_rr_graph_storage& rr_nodes, int inode); - -void insert_at_ptc_index(std::vector& rr_indices, int ptc, int inode); - -inline int get_chan_width(enum e_side side, const t_chan_width* nodes_per_channel); +inline int get_chan_width(enum e_side side, const t_chan_width& nodes_per_channel); #endif diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp index 75d99f2fde2..06b1c5e512d 100644 --- a/vpr/src/route/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_area.cpp @@ -282,7 +282,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl break; } /* End switch on from_rr_type */ - } /* End for all nodes */ + } /* End for all nodes */ delete[] cblock_counted; delete[] shared_buffer_trans; @@ -480,7 +480,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* break; } /* End switch on from_rr_type */ - } /* End for all nodes */ + } /* End for all nodes */ /* Now add in the input connection block transistors. */ diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_indexed_data.cpp index 115f29b0445..09bad36ad28 100644 --- a/vpr/src/route/rr_graph_indexed_data.cpp +++ b/vpr/src/route/rr_graph_indexed_data.cpp @@ -19,4 +19,4 @@ void load_rr_index_segments(const int num_segment) { index = CHANX_COST_INDEX_START + num_segment + iseg; device_ctx.rr_indexed_data[RRIndexedDataId(index)].seg_index = iseg; } -} \ No newline at end of file +} diff --git a/vpr/src/route/rr_graph_timing_params.cpp b/vpr/src/route/rr_graph_timing_params.cpp index ae316cef2c7..d2c478dffe6 100644 --- a/vpr/src/route/rr_graph_timing_params.cpp +++ b/vpr/src/route/rr_graph_timing_params.cpp @@ -1,14 +1,9 @@ #include -#include "vtr_memory.h" - -#include "vpr_types.h" -#include "vpr_error.h" - #include "globals.h" #include "rr_graph.h" #include "rr_graph_utils.h" -#include "rr_graph2.h" +#include "rr_rc_data.h" #include "rr_graph_timing_params.h" /****************** Subroutine definitions *********************************/ diff --git a/vpr/src/route/rr_types.h b/vpr/src/route/rr_types.h index d75f107d082..8e093faca75 100644 --- a/vpr/src/route/rr_types.h +++ b/vpr/src/route/rr_types.h @@ -22,4 +22,164 @@ typedef std::vector, 5>> t_pin_to_track_lookup; typedef std::vector, 5>> t_track_to_pin_lookup; +/** + * @brief Lists detailed information about wire segments. [0 .. W-1]. + */ +struct t_seg_details { + /** @brief Length (in clbs) of the segment. */ + int length = 0; + + /** @brief Index at which a segment starts in channel 0. */ + int start = 0; + + /** @brief True if this segment spans the entire channel. */ + bool longline = false; + + /** @brief [0..length]: true for every channel intersection, relative to the + * segment start, at which there is a switch box. + */ + std::unique_ptr sb; + + /** @brief [0..length-1]: true for every logic block along the segment at + * which there is a connection box. + */ + std::unique_ptr cb; + + /** @brief Index of the switch type that connects other wires to this segment. + * Note that this index is in relation to the switches from the architecture + * file, not the expanded list of switches that is built at the end of build_rr_graph. + */ + short arch_wire_switch = 0; + + /** @brief Index of the switch type that connects output pins (OPINs) *to* this segment. + * Note that this index is in relation to the switches from the architecture + * file, not the expanded list of switches that is built at the end of build_rr_graph. + */ + short arch_opin_switch = 0; + + /** @brief Index of the switch type that connects output pins (OPINs) *to* this segment + * from *another dice*. Note that this index is in relation to the switches from the + * architecture file, not the expanded list of switches that is built at the end of + * build_rr_graph. + */ + short arch_inter_die_switch = 0; + + /** @brief Resistance of a routing track, per unit logic block length. */ + float Rmetal = 0; + + /** @brief Capacitance of a routing track, per unit logic block length. */ + float Cmetal = 0; + + /** @brief Whether the segment is twisted. */ + bool twisted = false; + + /** @brief Direction of the segment. */ + enum Direction direction = Direction::NONE; + + /** @brief Index of the first logic block in the group. */ + int group_start = 0; + + /** @brief Size of the group. */ + int group_size = 0; + + /** @brief index of the segment type used for this track. + * Note that this index will store the index of the segment + * relative to its **parallel** segment types, not all segments + * as stored in device_ctx. Look in rr_graph.cpp: build_rr_graph + * for details but here is an example: say our segment_inf_vec in + * device_ctx is as follows: [seg_a_x, seg_b_x, seg_a_y, seg_b_y] + * when building the rr_graph, static segment_inf_vectors will be + * created for each direction, thus you will have the following + * 2 vectors: X_vec =[seg_a_x,seg_b_x] and Y_vec = [seg_a_y,seg_b_y]. + * As a result, e.g. seg_b_y::index == 1 (index in Y_vec) + * and != 3 (index in device_ctx segment_inf_vec). + */ + int index = 0; + + /** @brief index is relative to the segment_inf vec as stored in device_ctx. + * Note that the above vector is **unifies** both x-parallel and + * y-parallel segments and is loaded up originally in read_xml_arch_file.cpp + */ + int abs_index = 0; + + /** @brief Used for power */ + float Cmetal_per_m = 0; + + /** @brief Name of the segment type. */ + std::string type_name; +}; + +class t_chan_seg_details { + public: + t_chan_seg_details() = default; + t_chan_seg_details(const t_seg_details* init_seg_details) + : length_(init_seg_details->length) + , seg_detail_(init_seg_details) {} + + public: + int length() const { return length_; } + int seg_start() const { return seg_start_; } + int seg_end() const { return seg_end_; } + + int start() const { return seg_detail_->start; } + bool longline() const { return seg_detail_->longline; } + + int group_start() const { return seg_detail_->group_start; } + int group_size() const { return seg_detail_->group_size; } + + bool cb(int pos) const { return seg_detail_->cb[pos]; } + bool sb(int pos) const { return seg_detail_->sb[pos]; } + + float Rmetal() const { return seg_detail_->Rmetal; } + float Cmetal() const { return seg_detail_->Cmetal; } + float Cmetal_per_m() const { return seg_detail_->Cmetal_per_m; } + + short arch_wire_switch() const { return seg_detail_->arch_wire_switch; } + short arch_opin_switch() const { return seg_detail_->arch_opin_switch; } + short arch_inter_die_switch() const { return seg_detail_->arch_inter_die_switch; } + + Direction direction() const { return seg_detail_->direction; } + + int index() const { return seg_detail_->index; } + int abs_index() const { return seg_detail_->abs_index; } + + const vtr::string_view type_name() const { + return vtr::string_view( + seg_detail_->type_name.data(), + seg_detail_->type_name.size()); + } + + public: //Modifiers + void set_length(int new_len) { length_ = new_len; } + void set_seg_start(int new_start) { seg_start_ = new_start; } + void set_seg_end(int new_end) { seg_end_ = new_end; } + + private: + //The only unique information about a channel segment is it's start/end + //and length. All other information is shared across segment types, + //so we use a flyweight to the t_seg_details which defines that info. + // + //To preserve the illusion of uniqueness we wrap all t_seg_details members + //so it appears transparent -- client code of this class doesn't need to + //know about t_seg_details. + int length_ = -1; + int seg_start_ = -1; + int seg_end_ = -1; + const t_seg_details* seg_detail_ = nullptr; +}; + +/** + * @typedef t_chan_details + * @brief Defines a 3-D array of t_chan_seg_details structures (one for each horizontal and vertical channel). + * + * Once allocated in rr_graph2.cpp, it can be accessed as: + * [0..grid.width()][0..grid.height()][0..num_tracks-1] + */ +typedef vtr::NdMatrix t_chan_details; + +/* [0..grid.width()-1][0..grid.width()][0..3 (From side)] \ + * [0..3 (To side)][0...max_chan_width][0..3 (to_mux,to_trac,alt_mux,alt_track)] + * originally initialized to UN_SET until alloc_and_load_sb is called */ +typedef vtr::NdMatrix t_sblock_pattern; + #endif diff --git a/vpr/src/route/sink_sampling.h b/vpr/src/route/sink_sampling.h index 485bff9b3e5..341a292db7f 100644 --- a/vpr/src/route/sink_sampling.h +++ b/vpr/src/route/sink_sampling.h @@ -159,7 +159,7 @@ inline void convex_hull_downsample(ParentNetId net_id, const t_bb& net_bb, vtr:: for (auto& point : hull) { if (point.isink == 0) /* source */ continue; - if(is_isink_reached.get(point.isink)) + if (is_isink_reached.get(point.isink)) continue; out.set(point.isink, true); } diff --git a/vpr/src/server/bytearray.h b/vpr/src/server/bytearray.h index 2a94927f0cc..566cc83f02d 100644 --- a/vpr/src/server/bytearray.h +++ b/vpr/src/server/bytearray.h @@ -12,9 +12,9 @@ namespace comm { /** * @brief ByteArray is a simple wrapper over std::vector that provides a user-friendly interface for manipulating array data.. -*/ + */ class ByteArray : public std::vector { -public: + public: static const std::size_t DEFAULT_SIZE_HINT = 1024; /** @@ -27,8 +27,7 @@ class ByteArray : public std::vector { * @param data A pointer to the null-terminated C string from which to construct the ByteArray. */ explicit ByteArray(const char* data) - : std::vector(data, data + std::strlen(data)) - {} + : std::vector(data, data + std::strlen(data)) {} /** * @brief Constructs a ByteArray from a raw character array. @@ -41,8 +40,7 @@ class ByteArray : public std::vector { * @param size The size of the raw character array, in bytes. */ ByteArray(const char* data, std::size_t size) - : std::vector(data, data + size) - {} + : std::vector(data, data + size) {} /** * @brief Constructs a byte array with the specified size hint. @@ -66,7 +64,8 @@ class ByteArray : public std::vector { * @param last An iterator to the last element in the range. */ template - ByteArray(Iterator first, Iterator last): std::vector(first, last) {} + ByteArray(Iterator first, Iterator last) + : std::vector(first, last) {} /** * @brief Appends the content of another byte array to the end of this byte array. diff --git a/vpr/src/server/commcmd.h b/vpr/src/server/commcmd.h index 28f3f69f452..54301bad63e 100644 --- a/vpr/src/server/commcmd.h +++ b/vpr/src/server/commcmd.h @@ -6,9 +6,9 @@ namespace comm { enum class CMD : int { - NONE=-1, - GET_PATH_LIST_ID=0, - DRAW_PATH_ID=1 + NONE = -1, + GET_PATH_LIST_ID = 0, + DRAW_PATH_ID = 1 }; } // namespace comm diff --git a/vpr/src/server/convertutils.cpp b/vpr/src/server/convertutils.cpp index f176e7ffee9..6832b23767b 100644 --- a/vpr/src/server/convertutils.cpp +++ b/vpr/src/server/convertutils.cpp @@ -18,7 +18,7 @@ std::optional try_convert_to_int(const std::string& str) { static std::string get_pretty_str_from_double(double value) { std::ostringstream ss; - ss << std::fixed << std::setprecision(2) << value; // Set precision to 2 digit after the decimal point + ss << std::fixed << std::setprecision(2) << value; // Set precision to 2 digit after the decimal point return ss.str(); } @@ -35,10 +35,10 @@ std::string get_pretty_duration_str_from_ms(int64_t duration_ms) { std::string get_pretty_size_str_from_bytes_num(int64_t bytes_num) { std::string result; - if (bytes_num >= 1024*1024*1024) { - result = get_pretty_str_from_double(bytes_num / double(1024*1024*1024)) + "Gb"; - } else if (bytes_num >= 1024*1024) { - result = get_pretty_str_from_double(bytes_num / double(1024*1024)) + "Mb"; + if (bytes_num >= 1024 * 1024 * 1024) { + result = get_pretty_str_from_double(bytes_num / double(1024 * 1024 * 1024)) + "Gb"; + } else if (bytes_num >= 1024 * 1024) { + result = get_pretty_str_from_double(bytes_num / double(1024 * 1024)) + "Mb"; } else if (bytes_num >= 1024) { result = get_pretty_str_from_double(bytes_num / double(1024)) + "Kb"; } else { diff --git a/vpr/src/server/gateio.cpp b/vpr/src/server/gateio.cpp index d40431e7da9..4094fd3e061 100644 --- a/vpr/src/server/gateio.cpp +++ b/vpr/src/server/gateio.cpp @@ -36,7 +36,7 @@ void GateIO::stop() { void GateIO::take_received_tasks(std::vector& tasks) { std::unique_lock lock(m_tasks_mutex); - for (TaskPtr& task: m_received_tasks) { + for (TaskPtr& task : m_received_tasks) { m_logger.queue(LogLevel::Debug, "move task id=", task->job_id(), "for processing"); tasks.push_back(std::move(task)); } @@ -45,7 +45,7 @@ void GateIO::take_received_tasks(std::vector& tasks) { void GateIO::move_tasks_to_send_queue(std::vector& tasks) { std::unique_lock lock(m_tasks_mutex); - for (TaskPtr& task: tasks) { + for (TaskPtr& task : tasks) { m_logger.queue(LogLevel::Debug, "move task id=", task->job_id(), "finished", (task->has_error() ? "with error" : "successfully"), task->error(), "to send queue"); m_send_tasks.push_back(std::move(task)); } @@ -58,7 +58,7 @@ GateIO::ActivityStatus GateIO::check_client_connection(sockpp::tcp6_acceptor& tc sockpp::inet6_address peer; sockpp::tcp6_socket client = tcp_server.accept(&peer); if (client) { - m_logger.queue(LogLevel::Info, "client", client.address().to_string() , "connection accepted"); + m_logger.queue(LogLevel::Info, "client", client.address().to_string(), "connection accepted"); client.set_non_blocking(true); client_opt = std::move(client); @@ -80,12 +80,12 @@ GateIO::ActivityStatus GateIO::handle_sending_data(sockpp::tcp6_socket& client) if (bytes_sent <= task->orig_reponse_bytes_num()) { task->chop_num_sent_bytes_from_response_buffer(bytes_sent); m_logger.queue(LogLevel::Detail, - "sent chunk:", get_pretty_size_str_from_bytes_num(bytes_sent), - "from", get_pretty_size_str_from_bytes_num(task->orig_reponse_bytes_num()), - "left:", get_pretty_size_str_from_bytes_num(task->response_buffer().size())); + "sent chunk:", get_pretty_size_str_from_bytes_num(bytes_sent), + "from", get_pretty_size_str_from_bytes_num(task->orig_reponse_bytes_num()), + "left:", get_pretty_size_str_from_bytes_num(task->response_buffer().size())); status = ActivityStatus::CLIENT_ACTIVITY; } - } catch(...) { + } catch (...) { m_logger.queue(LogLevel::Detail, "error while writing chunk"); status = ActivityStatus::COMMUNICATION_PROBLEM; } @@ -99,7 +99,7 @@ GateIO::ActivityStatus GateIO::handle_sending_data(sockpp::tcp6_socket& client) std::size_t tasks_num_before_removing = m_send_tasks.size(); auto partition_iter = std::partition(m_send_tasks.begin(), m_send_tasks.end(), - [](const TaskPtr& task) { return !task->is_response_fully_sent(); }); + [](const TaskPtr& task) { return !task->is_response_fully_sent(); }); m_send_tasks.erase(partition_iter, m_send_tasks.end()); bool is_removing_took_place = tasks_num_before_removing != m_send_tasks.size(); if (!m_send_tasks.empty() && is_removing_took_place) { @@ -114,7 +114,7 @@ GateIO::ActivityStatus GateIO::handle_receiving_data(sockpp::tcp6_socket& client std::size_t bytes_actually_received{0}; try { bytes_actually_received = client.read_n(&received_message[0], CHUNK_MAX_BYTES_NUM); - } catch(...) { + } catch (...) { m_logger.queue(LogLevel::Error, "fail to receiving"); status = ActivityStatus::COMMUNICATION_PROBLEM; } @@ -132,7 +132,7 @@ GateIO::ActivityStatus GateIO::handle_telegrams(std::vectorbody}; bool is_echo_telegram = false; @@ -150,7 +150,7 @@ GateIO::ActivityStatus GateIO::handle_telegrams(std::vector(job_id_opt.value(), static_cast(cmd_opt.value()), options_opt.value()); const comm::TelegramHeader& header = telegram_frame->header; - m_logger.queue(LogLevel::Info, "received:", header.info(), task->info(/*skipDuration*/true)); + m_logger.queue(LogLevel::Info, "received:", header.info(), task->info(/*skipDuration*/ true)); std::unique_lock lock(m_tasks_mutex); m_received_tasks.push_back(std::move(task)); } else { @@ -176,7 +176,7 @@ GateIO::ActivityStatus GateIO::handle_client_alive_tracker(sockpp::tcp6_socket& m_logger.queue(LogLevel::Detail, "sent", comm::ECHO_TELEGRAM_BODY); client_alive_tracker_ptr->on_echo_sent(); } - } catch(...) { + } catch (...) { m_logger.queue(LogLevel::Debug, "fail to sent", comm::ECHO_TELEGRAM_BODY); status = ActivityStatus::COMMUNICATION_PROBLEM; } @@ -204,8 +204,7 @@ void GateIO::handle_activity_status(ActivityStatus status, std::unique_ptr client_alive_tracker_ptr = - std::make_unique(std::chrono::milliseconds{5000}, std::chrono::milliseconds{20000}); + std::unique_ptr client_alive_tracker_ptr = std::make_unique(std::chrono::milliseconds{5000}, std::chrono::milliseconds{20000}); #else std::unique_ptr client_alive_tracker_ptr; #endif @@ -229,7 +228,7 @@ void GateIO::start_listening() { received_message.resize(CHUNK_MAX_BYTES_NUM); /// comm event loop - while(m_is_running.load()) { + while (m_is_running.load()) { bool is_communication_problem_detected = false; if (!client_opt) { @@ -259,7 +258,7 @@ void GateIO::start_listening() { // forward telegramBuffer errors std::vector telegram_buffer_errors; telegram_buff.take_errors(telegram_buffer_errors); - for (const std::string& error: telegram_buffer_errors) { + for (const std::string& error : telegram_buffer_errors) { m_logger.queue(LogLevel::Info, error); } diff --git a/vpr/src/server/gateio.h b/vpr/src/server/gateio.h index aa9036459c5..ee72d155cb7 100644 --- a/vpr/src/server/gateio.h +++ b/vpr/src/server/gateio.h @@ -37,16 +37,15 @@ namespace server { * and responsiveness of the application. * - GateIO is not started automatically upon creation, you have to use the 'start' method with the port number. * - The socket is initialized in a non-blocking mode to function properly in a multithreaded environment. -*/ -class GateIO -{ + */ +class GateIO { enum class ActivityStatus : int { WAITING_ACTIVITY, CLIENT_ACTIVITY, COMMUNICATION_PROBLEM }; - const std::size_t CHUNK_MAX_BYTES_NUM = 2*1024*1024; // 2Mb + const std::size_t CHUNK_MAX_BYTES_NUM = 2 * 1024 * 1024; // 2Mb /** * @brief Helper class aimed to help detecting a client offline. @@ -58,12 +57,13 @@ class GateIO * and it's time to start accepting new client connections in GateIO. */ class ClientAliveTracker { - public: + public: ClientAliveTracker(const std::chrono::milliseconds& echoIntervalMs, const std::chrono::milliseconds& clientTimeoutMs) - : m_echo_interval_ms(echoIntervalMs), m_client_timeout_ms(clientTimeoutMs) { + : m_echo_interval_ms(echoIntervalMs) + , m_client_timeout_ms(clientTimeoutMs) { reset(); } - ClientAliveTracker()=default; + ClientAliveTracker() = default; void on_client_activity() { m_last_client_activity_time = std::chrono::high_resolution_clock::now(); @@ -76,13 +76,13 @@ class GateIO bool is_time_to_sent_echo() const { return (duration_since_last_client_activity_ms() > m_echo_interval_ms) && (durationSinceLastEchoSentMs() > m_echo_interval_ms); } - bool is_client_timeout() const { return duration_since_last_client_activity_ms() > m_client_timeout_ms; } + bool is_client_timeout() const { return duration_since_last_client_activity_ms() > m_client_timeout_ms; } void reset() { on_client_activity(); } - private: + private: std::chrono::high_resolution_clock::time_point m_last_client_activity_time; std::chrono::high_resolution_clock::time_point m_last_echo_sent_time; std::chrono::milliseconds m_echo_interval_ms; @@ -98,7 +98,7 @@ class GateIO } }; - enum class LogLevel: int { + enum class LogLevel : int { Error, Info, Detail, @@ -106,7 +106,7 @@ class GateIO }; class TLogger { - public: + public: TLogger() { m_log_level = static_cast(LogLevel::Info); } @@ -132,7 +132,7 @@ class GateIO } } - private: + private: std::stringstream m_log_stream; std::mutex m_log_stream_mutex; std::atomic m_log_level; @@ -140,7 +140,7 @@ class GateIO const int LOOP_INTERVAL_MS = 100; -public: + public: /** * @brief Default constructor for GateIO. */ @@ -154,10 +154,10 @@ class GateIO GateIO& operator=(GateIO&&) = delete; /** - * @brief Returns a bool indicating whether or not the port listening process is currently running. - * - * @return True if the port listening process is running, false otherwise. - */ + * @brief Returns a bool indicating whether or not the port listening process is currently running. + * + * @return True if the port listening process is running, false otherwise. + */ bool is_running() const { return m_is_running.load(); } /** @@ -178,7 +178,7 @@ class GateIO * remains empty after the operation. * * @param tasks A reference to a vector containing the tasks to be moved to the send queue. - */ + */ void move_tasks_to_send_queue(std::vector& tasks); /** @@ -187,7 +187,7 @@ class GateIO * @note Must be called from the main thread since it's invoke std::cout. * Calling this method from other threads may result in unexpected behavior. */ - void print_logs(); + void print_logs(); /** * @brief Starts the server on the specified port number. @@ -210,16 +210,16 @@ class GateIO */ void stop(); -private: + private: int m_port_num = -1; std::atomic m_is_running; // is true when started std::thread m_thread; // thread to execute socket IO work - std::mutex m_tasks_mutex; // we used single mutex to guard both vectors m_received_tasks and m_sendTasks + std::mutex m_tasks_mutex; // we used single mutex to guard both vectors m_received_tasks and m_sendTasks std::vector m_received_tasks; // tasks from client (requests) - std::vector m_send_tasks; // tasks to client (responses) + std::vector m_send_tasks; // tasks to client (responses) TLogger m_logger; @@ -240,4 +240,3 @@ class GateIO #endif /* NO_SERVER */ #endif /* GATEIO_H */ - diff --git a/vpr/src/server/pathhelper.cpp b/vpr/src/server/pathhelper.cpp index 9e9d8a7b576..b1f581aa620 100644 --- a/vpr/src/server/pathhelper.cpp +++ b/vpr/src/server/pathhelper.cpp @@ -13,7 +13,7 @@ namespace server { -/** +/** * @brief helper function to collect crit parser metadata. * This data is used on parser side to properly extract arrival path elements from the timing report. */ @@ -29,7 +29,7 @@ static void collect_crit_path_metadata(std::stringstream& ss, const std::vector< } } -/** +/** * @brief Helper function to calculate critical path timing report with specified parameters. */ CritPathsResultPtr calc_critical_path(const std::string& report_type, int crit_path_num, e_timing_report_detail details_level, bool is_flat_routing) { @@ -45,7 +45,7 @@ CritPathsResultPtr calc_critical_path(const std::string& report_type, int crit_p analysis_opts.timing_report_detail = details_level; analysis_opts.timing_report_npaths = crit_path_num; - VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, *routing_delay_calc, is_flat_routing, blk_loc_registry); + VprTimingGraphResolver resolver(atom_ctx.netlist(), atom_ctx.lookup(), *timing_ctx.graph, *routing_delay_calc, is_flat_routing, blk_loc_registry); resolver.set_detail_level(analysis_opts.timing_report_detail); tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints); diff --git a/vpr/src/server/pathhelper.h b/vpr/src/server/pathhelper.h index 8d2244a885a..3de4ba9f4f4 100644 --- a/vpr/src/server/pathhelper.h +++ b/vpr/src/server/pathhelper.h @@ -16,36 +16,36 @@ namespace server { * @brief Structure to retain the calculation result of the critical path. * * It contains the critical path list and the generated report as a string. -*/ + */ struct CritPathsResult { /** - * @brief Checks if the CritPathsResult contains report. - * @return True if contains report, false otherwise. - */ + * @brief Checks if the CritPathsResult contains report. + * @return True if contains report, false otherwise. + */ bool is_valid() const { return !report.empty(); } /** - * @brief Vector containing timing paths. - */ + * @brief Vector containing timing paths. + */ std::vector paths; /** - * @brief String containing the generated report. - */ + * @brief String containing the generated report. + */ std::string report; }; using CritPathsResultPtr = std::shared_ptr; /** -* @brief Calculates the critical path. - -* This function calculates the critical path based on the provided parameters. -* @param type The type of the critical path. Must be either "setup" or "hold". -* @param crit_path_num The max number of critical paths to record. -* @param details_level The level of detail for the timing report. See @ref e_timing_report_detail. -* @param is_flat_routing Indicates whether flat routing should be used. -* @return A `CritPathsResultPtr` which is a pointer to the result of the critical path calculation (see @ref CritPathsResult). -*/ + * @brief Calculates the critical path. + * + * This function calculates the critical path based on the provided parameters. + * @param type The type of the critical path. Must be either "setup" or "hold". + * @param crit_path_num The max number of critical paths to record. + * @param details_level The level of detail for the timing report. See @ref e_timing_report_detail. + * @param is_flat_routing Indicates whether flat routing should be used. + * @return A `CritPathsResultPtr` which is a pointer to the result of the critical path calculation (see @ref CritPathsResult). + */ CritPathsResultPtr calc_critical_path(const std::string& type, int crit_path_num, e_timing_report_detail details_level, bool is_flat_routing); } // namespace server diff --git a/vpr/src/server/serverupdate.cpp b/vpr/src/server/serverupdate.cpp index de45c45936d..075077389ec 100644 --- a/vpr/src/server/serverupdate.cpp +++ b/vpr/src/server/serverupdate.cpp @@ -19,7 +19,7 @@ gboolean update(gpointer data) { std::vector tasks_buff; gate_io.take_received_tasks(tasks_buff); - for (TaskPtr& task: tasks_buff) { + for (TaskPtr& task : tasks_buff) { task_resolver.own_task(std::move(task)); } tasks_buff.clear(); @@ -39,7 +39,7 @@ gboolean update(gpointer data) { } gate_io.print_logs(); } - + // Return TRUE to keep the timer running, or FALSE to stop it return is_running; } diff --git a/vpr/src/server/serverupdate.h b/vpr/src/server/serverupdate.h index f3add9ed269..2235c6910a3 100644 --- a/vpr/src/server/serverupdate.h +++ b/vpr/src/server/serverupdate.h @@ -21,4 +21,3 @@ gboolean update(gpointer); #endif /* NO_SERVER */ #endif /* SERVERUPDATE_H */ - diff --git a/vpr/src/server/task.cpp b/vpr/src/server/task.cpp index f05ada6d835..185c8b81ca5 100644 --- a/vpr/src/server/task.cpp +++ b/vpr/src/server/task.cpp @@ -11,7 +11,9 @@ namespace server { Task::Task(int jobId, comm::CMD cmd, const std::string& options) -: m_job_id(jobId), m_cmd(cmd), m_options(options) { + : m_job_id(jobId) + , m_cmd(cmd) + , m_options(options) { m_creation_time = std::chrono::high_resolution_clock::now(); } @@ -54,7 +56,7 @@ void Task::set_success(std::string&& result) { std::string Task::info(bool skip_duration) const { std::stringstream ss; ss << "task[" - << "id=" << std::to_string(m_job_id) + << "id=" << std::to_string(m_job_id) << ",cmd=" << std::to_string(static_cast(m_cmd)); if (!skip_duration) { ss << ",exists=" << get_pretty_duration_str_from_ms(time_ms_elapsed()); diff --git a/vpr/src/server/task.h b/vpr/src/server/task.h index 3d29e49373f..696e2fb012d 100644 --- a/vpr/src/server/task.h +++ b/vpr/src/server/task.h @@ -19,7 +19,7 @@ namespace server { * It generates a JSON data structure to be sent back to the client as a response. */ class Task { -public: + public: /** * @brief Constructs a new Task object. * @@ -178,7 +178,7 @@ class Task { */ const std::string& options() const { return m_options; } -private: + private: int m_job_id = -1; comm::CMD m_cmd = comm::CMD::NONE; std::string m_options; diff --git a/vpr/src/server/taskresolver.cpp b/vpr/src/server/taskresolver.cpp index 5298521ece0..c9e505c727a 100644 --- a/vpr/src/server/taskresolver.cpp +++ b/vpr/src/server/taskresolver.cpp @@ -14,7 +14,7 @@ namespace server { void TaskResolver::own_task(TaskPtr&& new_task) { // pre-process task before adding, where we could quickly detect failure scenarios - for (const auto& task: m_tasks) { + for (const auto& task : m_tasks) { if (task->cmd() == new_task->cmd()) { if (task->options_match(new_task)) { std::string msg = "similar task is already in execution, reject new " + new_task->info() + " and waiting for old " + task->info() + " execution"; @@ -34,7 +34,7 @@ void TaskResolver::own_task(TaskPtr&& new_task) { } void TaskResolver::take_finished_tasks(std::vector& result) { - for (auto it=m_tasks.begin(); it != m_tasks.end();) { + for (auto it = m_tasks.begin(); it != m_tasks.end();) { TaskPtr& task = *it; if (task->is_finished()) { result.push_back(std::move(task)); @@ -61,21 +61,22 @@ std::optional TaskResolver::try_get_details_level_enum(c bool TaskResolver::update(ezgl::application* app) { bool has_processed_task = false; - for (auto& task: m_tasks) { + for (auto& task : m_tasks) { if (!task->is_finished()) { - switch(task->cmd()) { + switch (task->cmd()) { case comm::CMD::GET_PATH_LIST_ID: { process_get_path_list_task(app, task); has_processed_task = true; break; - } + } case comm::CMD::DRAW_PATH_ID: { process_draw_critical_path_task(app, task); has_processed_task = true; break; } - default: break; - } + default: + break; + } } } diff --git a/vpr/src/server/taskresolver.h b/vpr/src/server/taskresolver.h index eca06bc1b74..ce38348a6b5 100644 --- a/vpr/src/server/taskresolver.h +++ b/vpr/src/server/taskresolver.h @@ -10,7 +10,7 @@ #include namespace ezgl { - class application; +class application; } namespace server { @@ -19,51 +19,51 @@ namespace server { * @brief Resolve server task. * * Process and resolve server task, store result and status for processed task. -*/ + */ class TaskResolver { -public: + public: /** * @brief Default constructor for TaskResolver. */ - TaskResolver()=default; + TaskResolver() = default; - ~TaskResolver()=default; + ~TaskResolver() = default; int tasks_num() const { return m_tasks.size(); } /** - * @brief Takes ownership of a task. - * - * This method takes ownership of a task by moving it into the TaskResolver's internal task queue. - * After calling this method, the task will be owned and managed by the TaskResolver. - * - * @param task The task to take ownership of. After calling this method, the task object will be in a valid but unspecified state. - * - * @note After calling this method, the caller should avoid accessing or modifying the task object. - */ + * @brief Takes ownership of a task. + * + * This method takes ownership of a task by moving it into the TaskResolver's internal task queue. + * After calling this method, the task will be owned and managed by the TaskResolver. + * + * @param task The task to take ownership of. After calling this method, the task object will be in a valid but unspecified state. + * + * @note After calling this method, the caller should avoid accessing or modifying the task object. + */ void own_task(TaskPtr&& task); /** - * @brief Resolve queued tasks. - * - * @param app A pointer to the ezgl::application object representing the application instance. - */ + * @brief Resolve queued tasks. + * + * @param app A pointer to the ezgl::application object representing the application instance. + */ bool update(ezgl::application* app); /** - * @brief Extracts finished tasks from the internal task queue. - * - * This function removes finished tasks from the internal task queue and appends them to the provided vector. - * After this operation, the internal task queue will no longer hold the extracted tasks. - * - * @param tasks A reference to a vector where the finished tasks will be appended. - */ + * @brief Extracts finished tasks from the internal task queue. + * + * This function removes finished tasks from the internal task queue and appends them to the provided vector. + * After this operation, the internal task queue will no longer hold the extracted tasks. + * + * @param tasks A reference to a vector where the finished tasks will be appended. + */ void take_finished_tasks(std::vector& tasks); // helper method used in tests const std::vector& tasks() const { return m_tasks; } -private: + private: std::vector m_tasks; void process_get_path_list_task(ezgl::application*, const TaskPtr&); @@ -77,4 +77,3 @@ class TaskResolver { #endif /* NO_SERVER */ #endif /* TASKRESOLVER_H */ - diff --git a/vpr/src/server/telegrambuffer.cpp b/vpr/src/server/telegrambuffer.cpp index 0aab6af8be1..5e8a79a9a69 100644 --- a/vpr/src/server/telegrambuffer.cpp +++ b/vpr/src/server/telegrambuffer.cpp @@ -55,7 +55,7 @@ void TelegramBuffer::take_telegram_frames(std::vector& r result.push_back(telegram_frame_ptr); } else { - m_errors.push_back("wrong checkSums " + std::to_string(actual_check_sum) +" for " + header.info() + " , drop this chunk"); + m_errors.push_back("wrong checkSums " + std::to_string(actual_check_sum) + " for " + header.info() + " , drop this chunk"); } m_raw_buffer.erase(m_raw_buffer.begin(), m_raw_buffer.begin() + expected_telegram_size); m_header_opt.reset(); diff --git a/vpr/src/server/telegrambuffer.h b/vpr/src/server/telegrambuffer.h index b5822e9a5c6..f7e2abba229 100644 --- a/vpr/src/server/telegrambuffer.h +++ b/vpr/src/server/telegrambuffer.h @@ -17,20 +17,20 @@ namespace comm { * @brief Implements Telegram Buffer as a wrapper over BytesArray * * It aggregates received bytes and assists in extracting telegram frames ( @ref TelegramFrame ) from the raw byte buffer. -*/ -class TelegramBuffer -{ + */ +class TelegramBuffer { inline static const std::size_t DEFAULT_SIZE_HINT = 1024; -public: + public: /** * @brief Constructs a TelegramBuffer object with a specified size hint. * * This constructor initializes a TelegramBuffer object with a specified size hint for the raw buffer. */ - explicit TelegramBuffer(std::size_t size_hint = DEFAULT_SIZE_HINT): m_raw_buffer(size_hint) {} + explicit TelegramBuffer(std::size_t size_hint = DEFAULT_SIZE_HINT) + : m_raw_buffer(size_hint) {} - ~TelegramBuffer()=default; + ~TelegramBuffer() = default; /** * @brief Check if internal byte buffer is empty. @@ -77,7 +77,7 @@ class TelegramBuffer */ const ByteArray& data() const { return m_raw_buffer; } -private: + private: ByteArray m_raw_buffer; std::vector m_errors; std::optional m_header_opt; diff --git a/vpr/src/server/telegramframe.h b/vpr/src/server/telegramframe.h index e2237de3e36..2fc0c312a73 100644 --- a/vpr/src/server/telegramframe.h +++ b/vpr/src/server/telegramframe.h @@ -11,19 +11,19 @@ namespace comm { /** -* @brief Structure representing a TelegramFrame. -* -* A TelegramFrame consists of a TelegramHeader followed by data. -*/ + * @brief Structure representing a TelegramFrame. + * + * A TelegramFrame consists of a TelegramHeader followed by data. + */ struct TelegramFrame { /** - * @brief header The TelegramHeader containing metadata about the telegram message. - */ + * @brief header The TelegramHeader containing metadata about the telegram message. + */ TelegramHeader header; /** - * @brief body The actual data of the telegram message. - */ + * @brief body The actual data of the telegram message. + */ ByteArray body; }; using TelegramFramePtr = std::shared_ptr; diff --git a/vpr/src/server/telegramheader.h b/vpr/src/server/telegramheader.h index ffe95b04ba2..84f1adcac1d 100644 --- a/vpr/src/server/telegramheader.h +++ b/vpr/src/server/telegramheader.h @@ -25,7 +25,7 @@ namespace comm { * @note: The DATA_CHECKSUM field can be used to check the integrity of the telegram body on the client app side. */ class TelegramHeader { -public: + public: static constexpr const char SIGNATURE[] = "IPA"; static constexpr size_t SIGNATURE_SIZE = sizeof(SIGNATURE); static constexpr size_t LENGTH_SIZE = sizeof(uint32_t); @@ -36,7 +36,7 @@ class TelegramHeader { static constexpr size_t CHECKSUM_OFFSET = LENGTH_OFFSET + LENGTH_SIZE; static constexpr size_t COMPRESSORID_OFFSET = CHECKSUM_OFFSET + CHECKSUM_SIZE; - TelegramHeader()=default; + TelegramHeader() = default; /** * @brief Constructs a TelegramHeader object with the specified length, checksum, and optional compressor ID. @@ -56,7 +56,7 @@ class TelegramHeader { */ explicit TelegramHeader(const ByteArray& buffer); - ~TelegramHeader()=default; + ~TelegramHeader() = default; /** * @brief Constructs a TelegramHeader based on the provided body data. @@ -129,7 +129,7 @@ class TelegramHeader { */ std::string info() const; -private: + private: bool m_is_valid = false; ByteArray m_buffer; diff --git a/vpr/src/server/telegramoptions.cpp b/vpr/src/server/telegramoptions.cpp index fef982d1437..86c4803c0d9 100644 --- a/vpr/src/server/telegramoptions.cpp +++ b/vpr/src/server/telegramoptions.cpp @@ -8,11 +8,11 @@ #include namespace server { - + TelegramOptions::TelegramOptions(const std::string& data, const std::vector& expected_keys) { // parse data string std::vector options = vtr::split(data, ";"); - for (const std::string& option_str: options) { + for (const std::string& option_str : options) { std::vector fragments = vtr::split(option_str, ":"); if (fragments.size() == TOTAL_INDEXES_NUM) { std::string name{std::move(fragments[INDEX_NAME])}; @@ -36,14 +36,14 @@ std::map> TelegramOptions::get_map_of_sets(co std::string data_str = get_string(name); if (!data_str.empty()) { std::vector paths = vtr::split(data_str, "|"); - for (const std::string& path: paths) { + for (const std::string& path : paths) { std::vector path_struct = vtr::split(path, "#"); if (path_struct.size() == 2) { std::string path_index_str = path_struct[0]; std::string path_element_indexes_str = path_struct[1]; std::vector path_element_indexes = vtr::split(path_element_indexes_str, ","); std::set elements; - for (const std::string& path_element_index_Str: path_element_indexes) { + for (const std::string& path_element_index_Str : path_element_indexes) { if (std::optional opt_value = try_convert_to_int(path_element_index_Str)) { elements.insert(opt_value.value()); } else { @@ -91,10 +91,10 @@ bool TelegramOptions::get_bool(const std::string& name, bool fail_value) { std::string TelegramOptions::errors_str() const { std::string result; - for (const std::string& error: m_errors) { + for (const std::string& error : m_errors) { result += error + ';'; } - return result; + return result; } bool TelegramOptions::is_data_type_supported(const std::string& type) const { @@ -104,7 +104,7 @@ bool TelegramOptions::is_data_type_supported(const std::string& type) const { bool TelegramOptions::check_keys_presence(const std::vector& keys) { bool result = true; - for (const std::string& key: keys) { + for (const std::string& key : keys) { if (m_options.find(key) == m_options.end()) { m_errors.emplace_back("cannot find required option " + std::string(key)); result = false; diff --git a/vpr/src/server/telegramoptions.h b/vpr/src/server/telegramoptions.h index 41237cdde2e..576973c441f 100644 --- a/vpr/src/server/telegramoptions.h +++ b/vpr/src/server/telegramoptions.h @@ -10,19 +10,19 @@ #include namespace server { - + /** * @brief Option class Parser * * Parse the string of options in the format "TYPE:KEY1:VALUE1;TYPE:KEY2:VALUE2", * for example "int:path_num:11;string:path_type:debug;int:details_level:3;bool:is_flat_routing:0". * It provides a simple interface to check value presence and access them. -*/ + */ class TelegramOptions { -private: + private: enum { - INDEX_TYPE=0, + INDEX_TYPE = 0, INDEX_NAME, INDEX_VALUE, TOTAL_INDEXES_NUM @@ -33,7 +33,7 @@ class TelegramOptions { std::string value; }; -public: + public: /** * @brief Constructs a TelegramOptions object with the provided data and expected keys. * @@ -45,7 +45,7 @@ class TelegramOptions { * @param expected_keys A vector of strings representing the expected keys in the options. */ TelegramOptions(const std::string& data, const std::vector& expected_keys); - ~TelegramOptions()=default; + ~TelegramOptions() = default; /** * @brief Checks if there are any errors present. @@ -115,7 +115,7 @@ class TelegramOptions { */ std::string errors_str() const; -private: + private: std::unordered_map m_options; std::vector m_errors; diff --git a/vpr/src/server/telegramparser.h b/vpr/src/server/telegramparser.h index 23e942f1d9d..633c83484ce 100644 --- a/vpr/src/server/telegramparser.h +++ b/vpr/src/server/telegramparser.h @@ -15,7 +15,7 @@ namespace comm { * from a JSON schema structured as follows: {JOB_ID:num, CMD:enum, OPTIONS:string, DATA:string, STATUS:num}. */ class TelegramParser { -public: + public: /** * @brief Attempts to extract the JOB_ID field from a given message. * @@ -76,7 +76,7 @@ class TelegramParser { */ static std::optional try_extract_field_status(const std::string& message); -private: + private: static std::optional try_extract_json_value_str(const std::string& json_string, const std::string& key); }; diff --git a/vpr/src/server/zlibutils.h b/vpr/src/server/zlibutils.h index a531fe2bcc9..c9ca7cded52 100644 --- a/vpr/src/server/zlibutils.h +++ b/vpr/src/server/zlibutils.h @@ -9,31 +9,31 @@ constexpr const int BYTES_NUM_IN_32KB = 32768; /** -* @brief Compresses the input sequence using zlib. -* -* This function takes a string representing the decompressed data as input -* and compresses it using zlib. If compression is successful, the compressed -* data is returned as an optional string. If compression fails, an empty optional -* is returned. -* -* @param decompressed The input string representing the decompressed data. -* @return An optional string containing the compressed data if compression is successful, -* or an empty optional if compression fails. -*/ + * @brief Compresses the input sequence using zlib. + * + * This function takes a string representing the decompressed data as input + * and compresses it using zlib. If compression is successful, the compressed + * data is returned as an optional string. If compression fails, an empty optional + * is returned. + * + * @param decompressed The input string representing the decompressed data. + * @return An optional string containing the compressed data if compression is successful, + * or an empty optional if compression fails. + */ std::optional try_compress(const std::string& decompressed); /** -* @brief Decompresses the compressed sequence using zlib. -* -* This function takes a string representing the compressed data as input -* and decompresses it using zlib. If decompression is successful, the decompressed -* data is returned as an optional string. If decompression fails, an empty optional -* is returned. -* -* @param compressed The input string representing the compressed data. -* @return An optional string containing the decompressed data if decompression is successful, -* or an empty optional if decompression fails. -*/ + * @brief Decompresses the compressed sequence using zlib. + * + * This function takes a string representing the compressed data as input + * and decompresses it using zlib. If decompression is successful, the decompressed + * data is returned as an optional string. If decompression fails, an empty optional + * is returned. + * + * @param compressed The input string representing the compressed data. + * @return An optional string containing the decompressed data if decompression is successful, + * or an empty optional if decompression fails. + */ std::optional try_decompress(const std::string& compressed); #endif /* NO_SERVER */ diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h index 6768f84ebf0..d0a2793416b 100644 --- a/vpr/src/tileable_rr_graph/chan_node_details.h +++ b/vpr/src/tileable_rr_graph/chan_node_details.h @@ -70,7 +70,7 @@ class ChanNodeDetails { std::vector seg_length_; /* Length of each segment */ std::vector track_start_; /* flag to identify if this is the starting point of the track */ std::vector track_end_; /* flag to identify if this is the ending point of the track */ - std::vector track_bend_start_; /* flag to identify if this is the starting point of the track after bend. 0 means it is not a bend start. Int number means the corresponding bend group */ + std::vector track_bend_start_; /* flag to identify if this is the starting point of the track after bend. 0 means it is not a bend start. Int number means the corresponding bend group */ std::vector track_bend_end_; }; diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp index 66ab365b42a..7b631e799ca 100644 --- a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -18,8 +18,8 @@ void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& perimeter_cb size_t start_x = 1; size_t end_x = grid.width() - 1; if (perimeter_cb) { - start_x = 0; - end_x = grid.width(); + start_x = 0; + end_x = grid.width(); } for (size_t iy = 0; iy < grid.height() - 1; ++iy) { for (size_t ix = start_x; ix < end_x; ++ix) { @@ -29,8 +29,8 @@ void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& perimeter_cb size_t start_y = 1; size_t end_y = grid.height() - 1; if (perimeter_cb) { - start_y = 0; - end_y = grid.height(); + start_y = 0; + end_y = grid.height(); } for (size_t ix = 0; ix < grid.width() - 1; ++ix) { for (size_t iy = start_y; iy < end_y; ++iy) { diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp index a73ff2f15d5..986339d96a9 100644 --- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -74,8 +74,8 @@ std::vector get_rr_graph_driver_switches(const RRGraphView& rr_graph std::vector driver_switches; for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { - if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) { - driver_switches.push_back(rr_graph.edge_switch(edge)); + if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), RRSwitchId(rr_graph.edge_switch(edge)))) { + driver_switches.push_back(RRSwitchId(rr_graph.edge_switch(edge))); } } diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp index 3b9e21bab9b..9bd38254b69 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -44,9 +44,9 @@ int get_grid_pin_class_index(const DeviceGrid& grids, /* Deteremine the side of a io grid */ std::vector determine_io_grid_pin_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate, - const bool& perimeter_cb) { - std::vector pin_sides; + const vtr::Point& grid_coordinate, + const bool& perimeter_cb) { + std::vector pin_sides; /* TOP side IO of FPGA */ if (device_size.y() == grid_coordinate.y()) { /* Such I/O has only bottom side pins */ @@ -64,7 +64,7 @@ std::vector determine_io_grid_pin_side(const vtr::Point& device_ pin_sides.push_back(TOP); pin_sides.push_back(BOTTOM); } - } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ + } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ /* Such I/O has only Top side pins */ pin_sides.push_back(TOP); /* If cbs are allowed around boundary I/Os, add two more sides */ @@ -72,7 +72,7 @@ std::vector determine_io_grid_pin_side(const vtr::Point& device_ pin_sides.push_back(LEFT); pin_sides.push_back(RIGHT); } - } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ + } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ /* Such I/O has only Right side pins */ pin_sides.push_back(RIGHT); /* If cbs are allowed around boundary I/Os, add two more sides */ @@ -89,8 +89,8 @@ std::vector determine_io_grid_pin_side(const vtr::Point& device_ grid_coordinate.x(), grid_coordinate.y(), device_size.x(), device_size.y()); exit(1); - } - return pin_sides; + } + return pin_sides; } /* Deteremine the side of a pin of a grid */ @@ -227,8 +227,8 @@ bool is_chanx_exist(const DeviceGrid& grids, size_t chanx_start = 1; size_t chanx_end = grids.width() - 2; if (perimeter_cb) { - chanx_start = 0; - chanx_end = grids.width() - 1; + chanx_start = 0; + chanx_end = grids.width() - 1; } if ((chanx_start > chanx_coord.x()) || (chanx_coord.x() > chanx_end)) { return false; @@ -273,8 +273,8 @@ bool is_chany_exist(const DeviceGrid& grids, size_t chany_start = 1; size_t chany_end = grids.height() - 2; if (perimeter_cb) { - chany_start = 0; - chany_end = grids.height() - 1; + chany_start = 0; + chany_end = grids.height() - 1; } if (chany_coord.x() > grids.width() - 2) { return false; @@ -311,9 +311,9 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, const bool& through_channel) { size_t start_x = 1; if (perimeter_cb) { - start_x = 0; + start_x = 0; } else { - VTR_ASSERT(0 < chanx_coord.x()); + VTR_ASSERT(0 < chanx_coord.x()); } if (start_x == chanx_coord.x()) { /* This is already the LEFT side of FPGA fabric, @@ -354,7 +354,7 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, VTR_ASSERT(chanx_coord.x() <= grids.width() - 1); size_t end_x = grids.width() - 2; if (perimeter_cb) { - end_x = grids.width() - 1; + end_x = grids.width() - 1; } if (end_x == chanx_coord.x()) { @@ -400,9 +400,9 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, const bool& through_channel) { size_t start_y = 1; if (perimeter_cb) { - start_y = 0; + start_y = 0; } else { - VTR_ASSERT(0 < chany_coord.y()); + VTR_ASSERT(0 < chany_coord.y()); } if (start_y == chany_coord.y()) { /* This is already the BOTTOM side of FPGA fabric, @@ -448,7 +448,7 @@ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, VTR_ASSERT(chany_coord.y() <= grids.height() - 1); size_t end_y = grids.height() - 2; if (perimeter_cb) { - end_y = grids.height() - 1; + end_y = grids.height() - 1; } if (end_y == chany_coord.y()) { diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h index c73ebb8206f..e1869ed4d4a 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -28,8 +28,8 @@ std::vector find_grid_pin_sides(const DeviceGrid& grids, const size_t& pin_id); std::vector determine_io_grid_pin_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate, - const bool& perimeter_cb); + const vtr::Point& grid_coordinate, + const bool& perimeter_cb); std::vector get_grid_side_pins(const DeviceGrid& grids, const size_t& layer, diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp index 9698ac03b45..7816e46134c 100644 --- a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -23,7 +23,7 @@ std::vector find_rr_graph_switches(const RRGraphView& rr_graph, * and update the switch list */ for (auto edge : edges) { - switches.push_back(rr_graph.edge_switch(edge)); + switches.push_back(RRSwitchId(rr_graph.edge_switch(edge))); } return switches; @@ -102,7 +102,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, /* Ensure that (x, y) is a valid location in grids */ if (size_t(x) > device_grid.width() - 1 || size_t(y) > device_grid.height() - 1) { - return indices; + return indices; } /* Ensure we have a valid side */ @@ -112,7 +112,7 @@ std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, t_physical_tile_loc tile_loc(x, y, layer); int width_offset = device_grid.get_width_offset(tile_loc); int height_offset = device_grid.get_height_offset(tile_loc); - + for (int pin = 0; pin < device_grid.get_physical_type(tile_loc)->num_pins; ++pin) { /* Skip those pins have been ignored during rr_graph build-up */ if (true == device_grid.get_physical_type(tile_loc)->is_ignored_pin[pin]) { diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp index 36663b21e2a..58c721a06b1 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -30,7 +30,7 @@ RRGSB::RRGSB() { medium_node_.clear(); for (size_t icb_type = 0; icb_type < 2; icb_type++) { - for (size_t iside = 0; iside < NUM_2D_SIDES; iside++) { + for (size_t iside = 0; iside < NUM_2D_SIDES; iside++) { cb_opin_node_[icb_type][iside].clear(); } } @@ -475,7 +475,7 @@ bool RRGSB::is_medium_node(const RRNodeId& node) const { } return false; } - + bool RRGSB::is_chan_node(const RRNodeId& node) const { std::vector sides = {TOP, RIGHT, BOTTOM, LEFT}; for (e_side side : sides) { @@ -965,7 +965,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ if (CHANX != rr_graph.node_type(src_node) && CHANY != rr_graph.node_type(src_node)) { - continue; + continue; } /* The driver routing channel node can be either an input or an output to the GSB. * Just try to find a qualified one. */ @@ -1008,7 +1008,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, const RRNodeId& src_node = rr_graph.edge_src_node(edge); /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ if (OPIN != rr_graph.node_type(src_node)) { - continue; + continue; } enum e_side cb_opin_side = NUM_2D_SIDES; int cb_opin_index = -1; @@ -1073,45 +1073,44 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { } void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { - for (t_rr_type cb_type : {CHANX, CHANY}) { - size_t icb_type = cb_type == CHANX ? 0 : 1; - std::vector cb_ipin_sides = get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < get_num_ipin_nodes(cb_ipin_side); - ++inode) { - std::vector driver_rr_edges = - get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); - for (const RREdgeId curr_edge : driver_rr_edges) { - RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); - if (OPIN != rr_graph.node_type(cand_node)) { - continue; - } - enum e_side cb_opin_side = NUM_2D_SIDES; - int cb_opin_index = -1; - get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, - cb_opin_index); - if ((-1 == cb_opin_index) || (NUM_2D_SIDES == cb_opin_side)) { - VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); - VTR_LOG("----------------------------------\n"); - VTR_LOG("SRC node:\n"); - VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(cand_node).c_str()); - VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(cand_node)); - VTR_LOG("Fan-out nodes:\n"); - for (const auto& temp_edge : rr_graph.edge_range(cand_node)) { - VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); - } - } - VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); - - if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == - std::find(cb_opin_node_[icb_type][size_t(cb_opin_side)].begin(), cb_opin_node_[icb_type][size_t(cb_opin_side)].end(), cand_node)) { - cb_opin_node_[icb_type][size_t(cb_opin_side)].push_back(cand_node); - } + for (t_rr_type cb_type : {CHANX, CHANY}) { + size_t icb_type = cb_type == CHANX ? 0 : 1; + std::vector cb_ipin_sides = get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < get_num_ipin_nodes(cb_ipin_side); + ++inode) { + std::vector driver_rr_edges = + get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); + for (const RREdgeId curr_edge : driver_rr_edges) { + RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); + if (OPIN != rr_graph.node_type(cand_node)) { + continue; + } + enum e_side cb_opin_side = NUM_2D_SIDES; + int cb_opin_index = -1; + get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, + cb_opin_index); + if ((-1 == cb_opin_index) || (NUM_2D_SIDES == cb_opin_side)) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(cand_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(cand_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(cand_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + } + VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); + + if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == std::find(cb_opin_node_[icb_type][size_t(cb_opin_side)].begin(), cb_opin_node_[icb_type][size_t(cb_opin_side)].end(), cand_node)) { + cb_opin_node_[icb_type][size_t(cb_opin_side)].push_back(cand_node); + } + } + } } - } } - } } /************************************************************************ diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h index 37b2dcc6f9d..30d8e80372b 100644 --- a/vpr/src/tileable_rr_graph/rr_gsb.h +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -232,6 +232,7 @@ class RRGSB { void sort_ipin_node_in_edges(const RRGraphView& rr_graph, const e_side& chan_side, const size_t& ipin_id); + private: /* internal functions */ size_t get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const; diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp index c1334d81d96..084dd9d67d2 100644 --- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -26,18 +26,21 @@ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, const std::vector& segment_inf, const bool& use_full_seg_groups) { - std::vector result; - std::vector demand; - /* Make sure a clean start */ - result.resize(segment_inf.size()); - demand.resize(segment_inf.size()); + + const size_t num_segments = segment_inf.size(); + std::vector result(num_segments); + std::vector demand(num_segments); + + if (segment_inf.empty()) { + return result; + } /* Scale factor so we can divide by any length * and still use integers */ /* Get the sum of frequency */ size_t scale = 1; size_t freq_sum = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + for (size_t iseg = 0; iseg < num_segments; ++iseg) { scale *= segment_inf[iseg].length; freq_sum += segment_inf[iseg].frequency; } @@ -47,7 +50,7 @@ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, /* Get the fraction of each segment type considering the frequency: * num_track_per_seg = chan_width * (freq_of_seg / sum_freq) */ - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + for (size_t iseg = 0; iseg < num_segments; ++iseg) { result[iseg] = 0; demand[iseg] = scale * chan_width * segment_inf[iseg].frequency; if (true == use_full_seg_groups) { @@ -63,7 +66,7 @@ std::vector get_num_tracks_per_seg_type(const size_t& chan_width, while (assigned < chan_width) { /* Find current maximum demand */ double max = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + for (size_t iseg = 0; iseg < num_segments; ++iseg) { if (demand[iseg] > max) { imax = iseg; } @@ -179,9 +182,9 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, /* Add node to ChanNodeDetails */ size_t cur_track = 0; - size_t bend_num = 0; // The index for bend segments + size_t bend_num = 0; // The index for bend segments for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - if (!segment_inf[iseg].isbend){ + if (!segment_inf[iseg].isbend) { /* segment length will be set to maxium segment length if this is a longwire */ size_t seg_len = segment_inf[iseg].length; if (true == segment_inf[iseg].longline) { @@ -208,34 +211,33 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len, seg_start, seg_end); cur_track++; } - } - else{ // bend segment + } else { // bend segment bend_num++; VTR_ASSERT(segment_inf[iseg].isbend); std::vector seg_len = segment_inf[iseg].part_len; std::vector bend = segment_inf[iseg].bend; - VTR_ASSERT(seg_len.size() == 2); // Only support one bend position for a segment. - + VTR_ASSERT(seg_len.size() == 2); // Only support one bend position for a segment. + std::vector num_tracks_bend; /* Each bend part tracks number * - * For example, a length-5 segment with bend pattern: <- - U -> has 20 tracks. * - * Its num_tracks_bend is [20 * 3/5, 20 * 2/5] = [12, 8] */ - for(size_t i = 0; i < seg_len.size(); i++) - num_tracks_bend.push_back(num_tracks[iseg] * seg_len[i] / segment_inf[iseg].length); - + * For example, a length-5 segment with bend pattern: <- - U -> has 20 tracks. * + * Its num_tracks_bend is [20 * 3/5, 20 * 2/5] = [12, 8] */ + for (size_t i = 0; i < seg_len.size(); i++) + num_tracks_bend.push_back(num_tracks[iseg] * seg_len[i] / segment_inf[iseg].length); + VTR_ASSERT(num_tracks_bend[0] + num_tracks_bend[1] == num_tracks[iseg]); for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { bool seg_start = false; bool seg_end = false; - size_t seg_bend_start = 0; // seg_bend_start = 0 means not a bend start. + size_t seg_bend_start = 0; // seg_bend_start = 0 means not a bend start. // seg_bend_start = i (i > 0) means a bend start for bend segment i. size_t seg_bend_end = 0; // The same as seg_bend_start. - // Tracks has same seg_bend_start and seg_bend_end values will be + // Tracks has same seg_bend_start and seg_bend_end values will be // connected by a delayless switch. /* Every first track of a group of Length-N wires, we set a starting point */ if (0 == itrack % segment_inf[iseg].length) { - seg_start = true; + seg_start = true; } /* Number seg_len[0] track of a group of Length-N wires, we set a bend start point */ if (seg_len[0] == int(itrack) % segment_inf[iseg].length) { @@ -260,56 +262,56 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); cur_track++; } - + /*for (size_t itrack = 0; itrack < num_tracks_bend[0]; ++itrack) { - - bool seg_start = false; - bool seg_end = false; - size_t seg_bend_start = 0; - size_t seg_bend_end = 0; - - if (0 == itrack % seg_len[0]) { - seg_start = true; - } - - if ((seg_len[0] - 1 == itrack % seg_len[0]) - || (itrack == num_tracks_bend[0] - 1)) { - seg_end = true; - seg_bend_end = bend_num; - } - int seg_index = segment_inf[iseg].seg_index; - - chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); - cur_track++; - chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); - cur_track++; - - } - for (size_t itrack = 0; itrack < num_tracks_bend[1]; ++itrack) { - - bool seg_start = false; - bool seg_end = false; - size_t seg_bend_start = 0; - size_t seg_bend_end = 0; - - if (0 == itrack % seg_len[1]) { - seg_start = true; - seg_bend_start = bend_num; - } - - if ((seg_len[1] - 1 == itrack % seg_len[1]) - || (itrack == num_tracks_bend[1] - 1)) { - seg_end = true; - } - int seg_index = segment_inf[iseg].seg_index; - - chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); - cur_track++; - - chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); - cur_track++; - - }*/ + * + * bool seg_start = false; + * bool seg_end = false; + * size_t seg_bend_start = 0; + * size_t seg_bend_end = 0; + * + * if (0 == itrack % seg_len[0]) { + * seg_start = true; + * } + * + * if ((seg_len[0] - 1 == itrack % seg_len[0]) + * || (itrack == num_tracks_bend[0] - 1)) { + * seg_end = true; + * seg_bend_end = bend_num; + * } + * int seg_index = segment_inf[iseg].seg_index; + * + * chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + * cur_track++; + * chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + * cur_track++; + * + * } + * for (size_t itrack = 0; itrack < num_tracks_bend[1]; ++itrack) { + * + * bool seg_start = false; + * bool seg_end = false; + * size_t seg_bend_start = 0; + * size_t seg_bend_end = 0; + * + * if (0 == itrack % seg_len[1]) { + * seg_start = true; + * seg_bend_start = bend_num; + * } + * + * if ((seg_len[1] - 1 == itrack % seg_len[1]) + * || (itrack == num_tracks_bend[1] - 1)) { + * seg_end = true; + * } + * int seg_index = segment_inf[iseg].seg_index; + * + * chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); + * cur_track++; + * + * chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); + * cur_track++; + * + * }*/ } } /* Check if all the tracks have been satisified */ diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp index d8ead463d9e..f911c8861d7 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -220,7 +220,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * Should use tileable version so that we have can have full control */ std::vector num_tracks = get_num_tracks_per_seg_type(max_chan_width / 2, segment_inf, false); - int* sets_per_seg_type = (int*)vtr::malloc(sizeof(int) * segment_inf.size()); + std::vector sets_per_seg_type(segment_inf.size()); VTR_ASSERT(num_tracks.size() == segment_inf.size()); for (size_t iseg = 0; iseg < num_tracks.size(); ++iseg) { sets_per_seg_type[iseg] = num_tracks[iseg]; @@ -272,10 +272,7 @@ void build_tileable_unidir_rr_graph(const std::vector& typ * TODO: use tile direct builder ***********************************************************************/ /* Create data structure of direct-connections */ - t_clb_to_clb_directs* clb_to_clb_directs = NULL; - if (!directs.empty()) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); - } + auto clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); std::vector clb2clb_directs; for (size_t idirect = 0; idirect < directs.size(); ++idirect) { /* Sanity checks on rr switch id */ @@ -323,15 +320,5 @@ void build_tileable_unidir_rr_graph(const std::vector& typ /* No clock network support yet; Does not support flatten rr_graph yet */ - check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, vib_grid, device_ctx.chan_width, GRAPH_UNIDIR, false); - - - /************************************************************************ - * Free all temp stucts - ***********************************************************************/ - free(sets_per_seg_type); - - if (nullptr != clb_to_clb_directs) { - free(clb_to_clb_directs); - } + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, vib_grid, device_ctx.chan_width, e_graph_type::UNIDIR_TILEABLE, false); } diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp index d242a0b9bf1..4b32fcab7cf 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -136,8 +136,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, segment_inf_y, perimeter_cb, delayless_switch); - } - else { + } else { build_rr_graph_regular_edges(rr_graph, rr_graph_builder, rr_node_driver_switches, @@ -171,7 +170,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // for (size_t iy = 0; iy < vib_grid.height(); iy++) { // std::map mux_name_map; - + // for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { // mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); // } @@ -179,10 +178,9 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // } // } // } - + // } - - + // size_t num_edges_to_create = 0; // /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ // build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); @@ -212,7 +210,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord, medium_mux_name2medium_index); // build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); - + // rr_graph_builder.build_edges(true); // } // else { @@ -254,7 +252,6 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // device_chan_width, segment_inf_x, segment_inf_y, // layer, gsb_coord, perimeter_cb); - // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -267,7 +264,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // } // num_edges_to_create += edge_count; // //rr_graph_builder.build_edges(true); - + // } // // process right boundary @@ -281,7 +278,6 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // device_chan_width, segment_inf_x, segment_inf_y, // layer, gsb_coord, perimeter_cb); - // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -294,7 +290,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // } // num_edges_to_create += edge_count; // //rr_graph_builder.build_edges(true); - + // } // // process right-top corner @@ -309,7 +305,6 @@ void build_rr_graph_edges(const RRGraphView& rr_graph, // device_chan_width, segment_inf_x, segment_inf_y, // layer, gsb_coord, perimeter_cb); - // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -379,7 +374,7 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, // for (size_t iy = 0; iy < vib_grid.height(); iy++) { // std::map mux_name_map; - + // for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { // mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); // } @@ -413,13 +408,12 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord, perimeter_cb); - t_vib_map vib_map; vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord); build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); - + rr_graph_builder.build_edges(true); - + // else { // /* adapt the track_to_ipin_lookup for the GSB nodes */ // t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ @@ -446,10 +440,10 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, } /* Process boundary */ - + size_t ix, iy; // process top boundary - iy = gsb_range.y() + 1; // == grids.height() - 1 + iy = gsb_range.y() + 1; // == grids.height() - 1 for (ix = 0; ix < gsb_range.x() + 1; ++ix) { vtr::Point actual_coord(ix, iy); vtr::Point gsb_coord(ix, iy - 1); @@ -459,7 +453,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord, perimeter_cb); - t_vib_map vib_map; vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord); //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -472,7 +465,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, } num_edges_to_create += edge_count; //rr_graph_builder.build_edges(true); - } // process right boundary @@ -486,7 +478,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, device_chan_width, segment_inf_x, segment_inf_y, layer, gsb_coord, perimeter_cb); - t_vib_map vib_map; vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord); //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -499,7 +490,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, } num_edges_to_create += edge_count; //rr_graph_builder.build_edges(true); - } // process right-top corner @@ -514,7 +504,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, // device_chan_width, segment_inf_x, segment_inf_y, // layer, gsb_coord, perimeter_cb); - // t_vib_map vib_map; // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); @@ -527,7 +516,6 @@ void build_rr_graph_vib_edges(const RRGraphView& rr_graph, // } // num_edges_to_create += edge_count; rr_graph_builder.build_edges(true); - } void build_rr_graph_regular_edges(const RRGraphView& rr_graph, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp index a0e8494718a..c76320b29c3 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -535,19 +535,19 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, } t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, - RRGraphBuilder& rr_graph_builder, + RRGraphBuilder& rr_graph_builder, const RRGraphView& rr_graph, const std::vector& segment_inf, const size_t& layer, const vtr::Point& gsb_coordinate, const RRSwitchId& delayless_switch, vtr::vector& rr_node_driver_switches) { - + std::vector>>> chan_rr_nodes_all_sides; //[side][bend_num][start/end][node] chan_rr_nodes_all_sides.resize(4); int bend_seg_num = 0; - std::vector bend_seg_type; //bend type: 1: U; 2: D + std::vector bend_seg_type; //bend type: 1: U; 2: D for (size_t iseg = 0; iseg < segment_inf.size(); iseg++) { if (segment_inf[iseg].isbend) { bend_seg_num++; @@ -562,24 +562,24 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, } VTR_ASSERT(bend_seg_num == int(bend_seg_type.size())); for (size_t side = 0; side < 4; ++side) { - std::vector rr_nodes; + std::vector rr_nodes; switch (side) { case TOP: /* TOP = 0 */ /* For the bording, we should take special care */ if (gsb_coordinate.y() == grids.height() - 2) { - + break; } chan_rr_nodes_all_sides[0].resize(bend_seg_num); - for (int i = 0; i < bend_seg_num; i++){ + for (int i = 0; i < bend_seg_num; i++) { chan_rr_nodes_all_sides[0][i].resize(2); //start/end track for bend } - + rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, CHANY); - + for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANY); Direction direction = rr_graph.node_direction(inode); @@ -597,26 +597,25 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(bend_start == 0); chan_rr_nodes_all_sides[0][bend_end - 1][1].push_back(inode); } - } - + break; case RIGHT: /* RIGHT = 1 */ /* For the bording, we should take special care */ if (gsb_coordinate.x() == grids.width() - 2) { - + break; } - + chan_rr_nodes_all_sides[1].resize(bend_seg_num); - for (int i = 0; i < bend_seg_num; i++){ + for (int i = 0; i < bend_seg_num; i++) { chan_rr_nodes_all_sides[1][i].resize(2); //start/end track for bend } - + rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), CHANX); - + for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANX); Direction direction = rr_graph.node_direction(inode); @@ -634,25 +633,24 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(bend_start == 0); chan_rr_nodes_all_sides[1][bend_end - 1][1].push_back(inode); } - } break; case BOTTOM: /* BOTTOM = 2 */ /* For the bording, we should take special care */ if (gsb_coordinate.y() == 0) { - + break; } - + chan_rr_nodes_all_sides[2].resize(bend_seg_num); - for (int i = 0; i < bend_seg_num; i++){ + for (int i = 0; i < bend_seg_num; i++) { chan_rr_nodes_all_sides[2][i].resize(2); //start/end track for bend } - + rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y(), CHANY); - + for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANY); Direction direction = rr_graph.node_direction(inode); @@ -670,25 +668,24 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(bend_end == 0); chan_rr_nodes_all_sides[2][bend_start - 1][0].push_back(inode); } - } break; case LEFT: /* BOTTOM = 2 */ /* For the bording, we should take special care */ if (gsb_coordinate.x() == 0) { - + break; } - + chan_rr_nodes_all_sides[3].resize(bend_seg_num); - for (int i = 0; i < bend_seg_num; i++){ + for (int i = 0; i < bend_seg_num; i++) { chan_rr_nodes_all_sides[3][i].resize(2); //start/end track for bend } - + rr_nodes = find_rr_graph_chan_nodes(rr_graph, layer, gsb_coordinate.x(), gsb_coordinate.y(), CHANX); - + for (auto inode : rr_nodes) { VTR_ASSERT(rr_graph.node_type(inode) == CHANX); Direction direction = rr_graph.node_direction(inode); @@ -706,71 +703,65 @@ t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, VTR_ASSERT(bend_end == 0); chan_rr_nodes_all_sides[3][bend_start - 1][0].push_back(inode); } - } break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid side index!\n"); exit(1); - } } std::map bend_seg_head2bend_seg_end_map; for (size_t ibend_seg = 0; ibend_seg < (size_t)bend_seg_num; ibend_seg++) { - int bend_type = bend_seg_type[ibend_seg]; //bend_type 1:U 2:D + int bend_type = bend_seg_type[ibend_seg]; //bend_type 1:U 2:D VTR_ASSERT(bend_type == 1 || bend_type == 2); - if (bend_type == 1) { //bend type U - for (size_t side = 0; side < 4; side++){ + if (bend_type == 1) { //bend type U + for (size_t side = 0; side < 4; side++) { size_t to_side = (side + 1) % 4; if (chan_rr_nodes_all_sides[side].size() > 0) for (size_t inode = 0; inode < chan_rr_nodes_all_sides[side][ibend_seg][1].size(); inode++) { - + if (chan_rr_nodes_all_sides[to_side].size() > 0) { VTR_ASSERT(chan_rr_nodes_all_sides[side][ibend_seg][1].size() == chan_rr_nodes_all_sides[to_side][ibend_seg][0].size()); bend_seg_head2bend_seg_end_map.emplace(std::make_pair(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode])); rr_node_driver_switches[chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode]] = delayless_switch; - } - else { + } else { rr_graph_builder.set_node_bend_end(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], 0); - } + } } else { if (chan_rr_nodes_all_sides[to_side].size() > 0) { for (size_t inode = 0; inode < chan_rr_nodes_all_sides[to_side][ibend_seg][0].size(); inode++) { - rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); + rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); } } } } - - } - else if (bend_type == 2) { //bend type D - for (size_t side = 0; side < 4; side++){ + + } else if (bend_type == 2) { //bend type D + for (size_t side = 0; side < 4; side++) { size_t to_side = (side + 3) % 4; if (chan_rr_nodes_all_sides[side].size() > 0) for (size_t inode = 0; inode < chan_rr_nodes_all_sides[side][ibend_seg][1].size(); inode++) { - + if (chan_rr_nodes_all_sides[to_side].size() > 0) { VTR_ASSERT(chan_rr_nodes_all_sides[side][ibend_seg][1].size() == chan_rr_nodes_all_sides[to_side][ibend_seg][0].size()); bend_seg_head2bend_seg_end_map.emplace(std::make_pair(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode])); rr_node_driver_switches[chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode]] = delayless_switch; - } - else { + } else { rr_graph_builder.set_node_bend_end(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], 0); - } + } } else { if (chan_rr_nodes_all_sides[to_side].size() > 0) { for (size_t inode = 0; inode < chan_rr_nodes_all_sides[to_side][ibend_seg][0].size(); inode++) { - rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); + rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); } } } } } - } return bend_seg_head2bend_seg_end_map; @@ -961,7 +952,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, OPIN, opin_grid_side[1]); break; case BOTTOM: /* BOTTOM = 2*/ - if (!perimeter_cb && gsb_coordinate.y() == 0) { + if (!perimeter_cb && gsb_coordinate.y() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -990,7 +981,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, OPIN, opin_grid_side[1]); break; case LEFT: /* LEFT = 3 */ - if (!perimeter_cb && gsb_coordinate.x() == 0) { + if (!perimeter_cb && gsb_coordinate.x() == 0) { rr_gsb.clear_one_side(side_manager.get_side()); break; } @@ -1806,7 +1797,7 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, const vtr::Point& gsb_coordinate, const vtr::Point& actual_coordinate) { VTR_ASSERT(rr_gsb.get_x() == gsb_coordinate.x() && rr_gsb.get_y() == gsb_coordinate.y()); - + t_vib_map vib_map; const VibInf* vib = vib_grid.get_vib(layer, actual_coordinate.x(), actual_coordinate.y()); @@ -1821,17 +1812,17 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, for (auto from : froms) { RRNodeId from_node; if (from.from_type == PB) { - + if (from.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type name!\n"); exit(1); } - + for (e_side side : TOTAL_2D_SIDES) { from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); if (from_node.is_valid()) - break; + break; } if (!from_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, @@ -1840,11 +1831,10 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!rr_gsb.is_opin_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Opin node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Opin node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else if (from.from_type == SEGMENT) { + } else if (from.from_type == SEGMENT) { char from_dir = from.seg_dir; //int from_index = from.seg_index; t_segment_inf segment = segment_inf[from.type_index]; @@ -1858,10 +1848,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } VTR_ASSERT(from.seg_index < seg_group.track_num * segment.length); e_side side; - if (from_dir == 'W') side = RIGHT; - else if (from_dir == 'E') side = LEFT; - else if (from_dir == 'N') side = BOTTOM; - else if (from_dir == 'S') side = TOP; + if (from_dir == 'W') + side = RIGHT; + else if (from_dir == 'E') + side = LEFT; + else if (from_dir == 'N') + side = BOTTOM; + else if (from_dir == 'S') + side = TOP; else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong segment from direction!\n"); @@ -1869,14 +1863,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); - if (track_list.size() == 0) continue; + if (track_list.size() == 0) + continue; else { VTR_ASSERT((int)track_list.size() >= (from.seg_index + 1) * 2); size_t seg_id; - if (side == LEFT || side == BOTTOM) { //INC + if (side == LEFT || side == BOTTOM) { //INC seg_id = from.seg_index * 2; - } - else { //DEC + } else { //DEC VTR_ASSERT(side == RIGHT || side == TOP); seg_id = from.seg_index * 2 + 1; } @@ -1887,21 +1881,17 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, "Wire node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - - } - else if (from.from_type == MUX) { + } else if (from.from_type == MUX) { size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); if (!rr_gsb.is_medium_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else { + } else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type!\n"); exit(1); @@ -1918,8 +1908,6 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, to_nodes.push_back(to_node); vib_map.emplace(std::make_pair(from_node, to_nodes)); } - - } } /* Second stages*/ @@ -1927,22 +1915,22 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, for (size_t i_second_stage = 0; i_second_stage < second_stages.size(); i_second_stage++) { std::vector froms = second_stages[i_second_stage].froms; std::vector tos = second_stages[i_second_stage].to; - + std::vector to_nodes; for (auto to : tos) { RRNodeId to_node; if (to.from_type == PB) { - + if (to.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong to type name!\n"); exit(1); } - + for (e_side side : TOTAL_2D_SIDES) { to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), IPIN, to.phy_pin_index, side); if (to_node.is_valid()) - break; + break; } if (!to_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, @@ -1951,11 +1939,10 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!rr_gsb.is_ipin_node(to_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else if (to.from_type == SEGMENT) { + } else if (to.from_type == SEGMENT) { char to_dir = to.seg_dir; //int from_index = from.seg_index; t_segment_inf segment = segment_inf[to.type_index]; @@ -1969,10 +1956,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } VTR_ASSERT(to.seg_index < seg_group.track_num * segment.length); e_side side; - if (to_dir == 'W') side = LEFT; - else if (to_dir == 'E') side = RIGHT; - else if (to_dir == 'N') side = TOP; - else if (to_dir == 'S') side = BOTTOM; + if (to_dir == 'W') + side = LEFT; + else if (to_dir == 'E') + side = RIGHT; + else if (to_dir == 'N') + side = TOP; + else if (to_dir == 'S') + side = BOTTOM; else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong segment from direction!\n"); @@ -1980,15 +1971,15 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); - if (track_list.size() == 0) continue; + if (track_list.size() == 0) + continue; else { //enum e_track_status track_status = determine_track_status_of_gsb VTR_ASSERT((int)track_list.size() >= (to.seg_index + 1) * 2); size_t seg_id; - if (side == LEFT || side == BOTTOM) { //DEC + if (side == LEFT || side == BOTTOM) { //DEC seg_id = to.seg_index * 2 + 1; - } - else { //INC + } else { //INC VTR_ASSERT(side == RIGHT || side == TOP); seg_id = to.seg_index * 2; } @@ -1998,39 +1989,35 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); if (!rr_gsb.is_chan_node(to_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } } - - } - else { + } else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type!\n"); exit(1); } VTR_ASSERT(to_node.is_valid()); - to_nodes.push_back(to_node); + to_nodes.push_back(to_node); } - - std::vector from_nodes; for (auto from : froms) { RRNodeId from_node; if (from.from_type == PB) { - + if (from.type_name != vib->get_pbtype_name()) { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type name!\n"); exit(1); } - + for (e_side side : TOTAL_2D_SIDES) { from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); if (from_node.is_valid()) - break; + break; } if (!from_node.is_valid()) { VTR_LOGF_WARN(__FILE__, __LINE__, @@ -2039,11 +2026,10 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } if (!rr_gsb.is_opin_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else if (from.from_type == SEGMENT) { + } else if (from.from_type == SEGMENT) { char from_dir = from.seg_dir; //int from_index = from.seg_index; t_segment_inf segment = segment_inf[from.type_index]; @@ -2057,10 +2043,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } VTR_ASSERT(from.seg_index < seg_group.track_num * segment.length); e_side side; - if (from_dir == 'W') side = RIGHT; - else if (from_dir == 'E') side = LEFT; - else if (from_dir == 'N') side = BOTTOM; - else if (from_dir == 'S') side = TOP; + if (from_dir == 'W') + side = RIGHT; + else if (from_dir == 'E') + side = LEFT; + else if (from_dir == 'N') + side = BOTTOM; + else if (from_dir == 'S') + side = TOP; else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong segment from direction!\n"); @@ -2068,14 +2058,14 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, } std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); - if (track_list.size() == 0) continue; + if (track_list.size() == 0) + continue; else { VTR_ASSERT((int)track_list.size() >= (from.seg_index + 1) * 2); size_t seg_id; - if (side == LEFT || side == BOTTOM) { //INC + if (side == LEFT || side == BOTTOM) { //INC seg_id = from.seg_index * 2; - } - else { //DEC + } else { //DEC VTR_ASSERT(side == RIGHT || side == TOP); seg_id = from.seg_index * 2 + 1; } @@ -2087,27 +2077,24 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, exit(1); } } - - } - else if (from.from_type == MUX) { + } else if (from.from_type == MUX) { size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); if (!rr_gsb.is_medium_node(from_node)) { VTR_LOGF_ERROR(__FILE__, __LINE__, - "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); exit(1); } - } - else { + } else { VTR_LOGF_ERROR(__FILE__, __LINE__, "Wrong from type!\n"); exit(1); } VTR_ASSERT(from_node.is_valid()); - from_nodes.push_back(from_node); + from_nodes.push_back(from_node); } - + if (to_nodes.size() > 0 && from_nodes.size() > 0) { for (auto from_node : from_nodes) { auto iter = vib_map.begin(); @@ -2116,7 +2103,6 @@ t_vib_map build_vib_map(const RRGraphView& rr_graph, for (auto to_node : to_nodes) { vib_map[from_node].push_back(to_node); } - } } if (iter == vib_map.end()) { diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h index 5e7ca853700..672af21bc0a 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -42,9 +42,9 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, const bool& concat_wire, const bool& wire_opposite_side, const std::vector& segment_inf); - + t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, - RRGraphBuilder& rr_graph_builder, + RRGraphBuilder& rr_graph_builder, const RRGraphView& rr_graph, const std::vector& segment_inf, const size_t& layer, diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 08d80b5936d..5b48ec0f2e6 100644 --- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -20,6 +20,7 @@ #include "tileable_chan_details_builder.h" #include "tileable_rr_graph_node_builder.h" #include "rr_rc_data.h" +#include "physical_types_util.h" /************************************************************************ * Find the number output pins by considering all the grid @@ -89,7 +90,7 @@ static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); for (size_t ix = 0; ix < grids.width(); ++ix) { for (size_t iy = 0; iy < grids.height(); ++iy) { - + const VibInf* vib = vib_grid.get_vib(layer, ix, iy); if (!vib) { VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -223,12 +224,12 @@ static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, size_t start_x = 1; size_t end_x = grids.width() - 1; if (perimeter_cb) { - start_x = 0; - end_x = grids.width(); + start_x = 0; + end_x = grids.width(); } size_t max_seg_length = grids.width() - 2; if (perimeter_cb) { - max_seg_length = grids.width(); + max_seg_length = grids.width(); } for (size_t iy = 0; iy < grids.height() - 1; ++iy) { @@ -300,12 +301,12 @@ static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, size_t start_y = 1; size_t end_y = grids.height() - 1; if (perimeter_cb) { - start_y = 0; - end_y = grids.height(); + start_y = 0; + end_y = grids.height(); } size_t max_seg_length = grids.height() - 2; if (perimeter_cb) { - max_seg_length = grids.height(); + max_seg_length = grids.height(); } for (size_t ix = 0; ix < grids.width() - 1; ++ix) { @@ -389,7 +390,6 @@ static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE, perimeter_cb); num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK, perimeter_cb); - /** * 2. Assign the segments for each routing channel, * To be specific, for each routing track, we assign a routing segment. @@ -519,9 +519,9 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } /* End of loading OPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ @@ -576,9 +576,9 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } /* End of loading IPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - } /* End of width enumeration */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ } /************************************************************************ @@ -713,7 +713,6 @@ static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_build /* RC data */ rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); } - } /************************************************************************ @@ -803,7 +802,7 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); for (size_t iy = 0; iy < grids.height(); ++iy) { for (size_t ix = 0; ix < grids.width(); ++ix) { - + t_physical_tile_loc tile_loc(ix, iy, layer); VTR_ASSERT(vib_grid.vib_pbtype_name(layer, ix, iy) == grids.get_physical_type(tile_loc)->name); vtr::Point grid_coordinate(ix, iy); @@ -815,11 +814,9 @@ static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_rc_data, layer, grid_coordinate, vib_grid); - + } } } - } - //Copy the SOURCE/SINK nodes to all offset positions for blocks with width > 1 and/or height > 1 // This ensures that look-ups on non-root locations will still find the correct SOURCE/SINK @@ -1007,12 +1004,12 @@ static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, size_t start_x = 1; size_t end_x = grids.width() - 1; if (perimeter_cb) { - start_x = 0; - end_x = grids.width(); + start_x = 0; + end_x = grids.width(); } size_t max_seg_length = grids.width() - 2; if (perimeter_cb) { - max_seg_length = grids.width(); + max_seg_length = grids.width(); } /* For X-direction Channel: CHANX */ @@ -1145,12 +1142,12 @@ static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, size_t start_y = 1; size_t end_y = grids.height() - 1; if (perimeter_cb) { - start_y = 0; - end_y = grids.height(); + start_y = 0; + end_y = grids.height(); } size_t max_seg_length = grids.height() - 2; if (perimeter_cb) { - max_seg_length = grids.height(); + max_seg_length = grids.height(); } /* For Y-direction Channel: CHANY */ diff --git a/vpr/src/timing/NetPinTimingInvalidator.h b/vpr/src/timing/NetPinTimingInvalidator.h index c76a075cb74..09badeecc53 100644 --- a/vpr/src/timing/NetPinTimingInvalidator.h +++ b/vpr/src/timing/NetPinTimingInvalidator.h @@ -9,7 +9,7 @@ #include "vtr_vec_id_set.h" #ifdef VPR_USE_TBB -# include +#include #endif /** Make NetPinTimingInvalidator a virtual class since it does nothing for the general case of non-incremental @@ -191,4 +191,4 @@ inline std::unique_ptr make_net_pin_timing_invalidator( return std::make_unique(net_list, clb_atom_pin_lookup, atom_nlist, atom_lookup, timing_info, is_flat); } -} \ No newline at end of file +} diff --git a/vpr/src/timing/PostClusterDelayCalculator.tpp b/vpr/src/timing/PostClusterDelayCalculator.tpp index 9c989cec03f..e112aae06e5 100644 --- a/vpr/src/timing/PostClusterDelayCalculator.tpp +++ b/vpr/src/timing/PostClusterDelayCalculator.tpp @@ -336,9 +336,9 @@ inline tatum::Time PostClusterDelayCalculator::atom_net_delay(const tatum::Timin VTR_ASSERT(src_pin != ParentPinId::INVALID()); VTR_ASSERT(sink_pin != ParentPinId::INVALID()); if (is_flat_) { - AtomNetId atom_src_net = g_vpr_ctx.atom().nlist.pin_net((AtomPinId&)src_pin); - VTR_ASSERT(atom_src_net == g_vpr_ctx.atom().nlist.pin_net((AtomPinId&)sink_pin)); - sink_net_pin_index = g_vpr_ctx.atom().nlist.pin_net_index((AtomPinId&)sink_pin); + AtomNetId atom_src_net = g_vpr_ctx.atom().netlist().pin_net((AtomPinId&)src_pin); + VTR_ASSERT(atom_src_net == g_vpr_ctx.atom().netlist().pin_net((AtomPinId&)sink_pin)); + sink_net_pin_index = g_vpr_ctx.atom().netlist().pin_net_index((AtomPinId&)sink_pin); tatum::Time net_delay = tatum::Time(inter_cluster_delay((ParentNetId&)atom_src_net, 0, sink_net_pin_index)); diff --git a/vpr/src/timing/PreClusterDelayCalculator.h b/vpr/src/timing/PreClusterDelayCalculator.h index a4177fd6126..069aaa13530 100644 --- a/vpr/src/timing/PreClusterDelayCalculator.h +++ b/vpr/src/timing/PreClusterDelayCalculator.h @@ -19,7 +19,7 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { PreClusterDelayCalculator(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, float intercluster_net_delay, - const Prepacker& prepacker) + const Prepacker& prepacker) noexcept : netlist_(netlist) , netlist_lookup_(netlist_lookup) , inter_cluster_net_delay_(intercluster_net_delay) diff --git a/vpr/src/timing/PreClusterTimingGraphResolver.cpp b/vpr/src/timing/PreClusterTimingGraphResolver.cpp index c94d961c84f..d1d8c2d8754 100644 --- a/vpr/src/timing/PreClusterTimingGraphResolver.cpp +++ b/vpr/src/timing/PreClusterTimingGraphResolver.cpp @@ -28,7 +28,7 @@ std::string PreClusterTimingGraphResolver::node_type_name(tatum::NodeId node) co //Annotate primitive grid location, if known auto& atom_ctx = g_vpr_ctx.atom(); auto& block_locs = g_vpr_ctx.placement().block_locs(); - ClusterBlockId cb = atom_ctx.lookup.atom_clb(blk); + ClusterBlockId cb = atom_ctx.lookup().atom_clb(blk); if (cb && block_locs.count(cb)) { int x = block_locs[cb].loc.x; int y = block_locs[cb].loc.y; diff --git a/vpr/src/timing/PreClusterTimingManager.cpp b/vpr/src/timing/PreClusterTimingManager.cpp new file mode 100644 index 00000000000..44407d61522 --- /dev/null +++ b/vpr/src/timing/PreClusterTimingManager.cpp @@ -0,0 +1,296 @@ +/** + * @file + * @author Alex Singer + * @date April 2025 + * @brief Implementation of the pre-cluster timing manager class. + */ + +#include "PreClusterTimingManager.h" +#include +#include +#include "PreClusterDelayCalculator.h" +#include "PreClusterTimingGraphResolver.h" +#include "SetupGrid.h" +#include "atom_lookup.h" +#include "atom_netlist.h" +#include "atom_netlist_fwd.h" +#include "concrete_timing_info.h" +#include "physical_types_util.h" +#include "prepack.h" +#include "tatum/TimingReporter.hpp" +#include "tatum/echo_writer.hpp" +#include "vpr_types.h" +#include "vtr_assert.h" +#include "vtr_time.h" + +/** + * Since the parameters of a switch may change as a function of its fanin, + * to get an estimation of inter-cluster delays we need a reasonable estimation + * of the fan-ins of switches that connect clusters together. These switches are + * 1) opin to wire switch + * 2) wire to wire switch + * 3) wire to ipin switch + * We can estimate the fan-in of these switches based on the Fc_in/Fc_out of + * a logic block, and the switch block Fs value + */ +static void get_intercluster_switch_fanin_estimates(const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout, + const int wire_segment_length, + int* opin_switch_fanin, + int* wire_switch_fanin, + int* ipin_switch_fanin); + +static float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch); + +static float approximate_inter_cluster_delay(const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout); + +PreClusterTimingManager::PreClusterTimingManager(bool timing_driven, + const AtomNetlist& atom_netlist, + const AtomLookup& atom_lookup, + const Prepacker& prepacker, + e_timing_update_type timing_update_type, + const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout, + const t_analysis_opts& analysis_opts) { + + // If the flow is not timing driven, do not initialize any of the timing + // objects and set the valid flag to false. This allows this object to be + // passed through the VPR flow when timing is turned off. + if (!timing_driven) { + is_valid_ = false; + return; + } + is_valid_ = true; + + // Start an overall timer for building the pre-cluster timing info. + vtr::ScopedStartFinishTimer timer("Initializing Pre-Cluster Timing"); + + // Approximate the inter-cluster delay + // FIXME: This can probably be simplified. It can also be improved using + // AP information. + float inter_cluster_net_delay = approximate_inter_cluster_delay(arch, routing_arch, device_layout); + VTR_LOG("Using inter-cluster delay: %g\n", inter_cluster_net_delay); + + // Initialize the timing analyzer + clustering_delay_calc_ = std::make_shared(atom_netlist, + atom_lookup, + inter_cluster_net_delay, + prepacker); + timing_info_ = make_setup_timing_info(clustering_delay_calc_, timing_update_type); + + // Calculate the initial timing + timing_info_->update(); + + // Create the echo file if requested. + if (isEchoFileEnabled(E_ECHO_PRE_PACKING_TIMING_GRAPH)) { + auto& timing_ctx = g_vpr_ctx.timing(); + tatum::write_echo(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH), + *timing_ctx.graph, *timing_ctx.constraints, *clustering_delay_calc_, timing_info_->analyzer()); + + tatum::NodeId debug_tnode = id_or_pin_name_to_tnode(analysis_opts.echo_dot_timing_graph_node); + write_setup_timing_graph_dot(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH) + std::string(".dot"), + *timing_info_, debug_tnode); + } + + // Write a timing report. + { + auto& timing_ctx = g_vpr_ctx.timing(); + PreClusterTimingGraphResolver resolver(atom_netlist, + atom_lookup, + *timing_ctx.graph, + *clustering_delay_calc_); + resolver.set_detail_level(analysis_opts.timing_report_detail); + + tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, + *timing_ctx.constraints); + + timing_reporter.report_timing_setup( + "pre_pack.report_timing.setup.rpt", + *timing_info_->setup_analyzer(), + analysis_opts.timing_report_npaths); + } +} + +static float approximate_inter_cluster_delay(const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout) { + + /* If needed, estimate inter-cluster delay. Assume the average routing hop goes out of + * a block through an opin switch to a length-4 wire, then through a wire switch to another + * length-4 wire, then through a wire-to-ipin-switch into another block. */ + constexpr int wire_segment_length = 4; + + /* We want to determine a reasonable fan-in to the opin, wire, and ipin switches, based + * on which the intercluster delays can be estimated. The fan-in of a switch influences its + * delay. + * + * The fan-in of the switch depends on the architecture (unidirectional/bidirectional), as + * well as Fc_in/out and Fs */ + int opin_switch_fanin, wire_switch_fanin, ipin_switch_fanin; + get_intercluster_switch_fanin_estimates(arch, routing_arch, device_layout, wire_segment_length, &opin_switch_fanin, + &wire_switch_fanin, &ipin_switch_fanin); + + float Tdel_opin_switch, R_opin_switch, Cout_opin_switch; + float opin_switch_del = get_arch_switch_info(arch.Segments[0].arch_opin_switch, opin_switch_fanin, + Tdel_opin_switch, R_opin_switch, Cout_opin_switch); + + float Tdel_wire_switch, R_wire_switch, Cout_wire_switch; + float wire_switch_del = get_arch_switch_info(arch.Segments[0].arch_wire_switch, wire_switch_fanin, + Tdel_wire_switch, R_wire_switch, Cout_wire_switch); + + float Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch; + float wtoi_switch_del = get_arch_switch_info(routing_arch.wire_to_arch_ipin_switch, ipin_switch_fanin, + Tdel_wtoi_switch, R_wtoi_switch, Cout_wtoi_switch); + + float Rmetal = arch.Segments[0].Rmetal; + float Cmetal = arch.Segments[0].Cmetal; + + /* The delay of a wire with its driving switch is the switch delay plus the + * product of the equivalent resistance and capacitance experienced by the wire. */ + + float first_wire_seg_delay = opin_switch_del + + (R_opin_switch + Rmetal * (float)wire_segment_length / 2) + * (Cout_opin_switch + Cmetal * (float)wire_segment_length); + float second_wire_seg_delay = wire_switch_del + + (R_wire_switch + Rmetal * (float)wire_segment_length / 2) + * (Cout_wire_switch + Cmetal * (float)wire_segment_length); + + /* multiply by 4 to get a more conservative estimate */ + return 4 * (first_wire_seg_delay + second_wire_seg_delay + wtoi_switch_del); +} + +static float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch) { + /* Fetches delay, resistance and output capacitance of the architecture switch at switch_index. + * Returns the total delay through the switch. Used to calculate inter-cluster net delay. */ + + /* The intrinsic delay may depend on fanin to the switch. If the delay map of a + * switch from the architecture file has multiple (#inputs, delay) entries, we + * interpolate/extrapolate to get the delay at 'switch_fanin'. */ + auto& device_ctx = g_vpr_ctx.device(); + + Tdel_switch = device_ctx.arch_switch_inf[switch_index].Tdel(switch_fanin); + R_switch = device_ctx.arch_switch_inf[switch_index].R; + Cout_switch = device_ctx.arch_switch_inf[switch_index].Cout; + + /* The delay through a loaded switch is its intrinsic (unloaded) + * delay plus the product of its resistance and output capacitance. */ + return Tdel_switch + R_switch * Cout_switch; +} + +static void get_intercluster_switch_fanin_estimates(const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout, + const int wire_segment_length, + int* opin_switch_fanin, + int* wire_switch_fanin, + int* ipin_switch_fanin) { + // W is unknown pre-packing, so *if* we need W here, we will assume a value of 100 + constexpr int W = 100; + + //Build a dummy 10x10 device to determine the 'best' block type to use + auto grid = create_device_grid(device_layout, arch.grid_layouts, 10, 10); + + auto type = find_most_common_tile_type(grid); + /* get Fc_in/out for most common block (e.g. logic blocks) */ + VTR_ASSERT(!type->fc_specs.empty()); + + //Estimate the maximum Fc_in/Fc_out + float Fc_in = 0.f; + float Fc_out = 0.f; + for (const t_fc_specification& fc_spec : type->fc_specs) { + float Fc = fc_spec.fc_value; + + if (fc_spec.fc_value_type == e_fc_value_type::ABSOLUTE) { + //Convert to estimated fractional + Fc /= W; + } + VTR_ASSERT_MSG(Fc >= 0 && Fc <= 1., "Fc should be fractional"); + + for (int ipin : fc_spec.pins) { + e_pin_type pin_type = get_pin_type_from_pin_physical_num(type, ipin); + + if (pin_type == DRIVER) { + Fc_out = std::max(Fc, Fc_out); + } else { + VTR_ASSERT(pin_type == RECEIVER); + Fc_in = std::max(Fc, Fc_in); + } + } + } + + /* Estimates of switch fan-in are done as follows: + * 1) opin to wire switch: + * 2 CLBs connect to a channel, each with #opins/4 pins. Each pin has Fc_out*W + * switches, and then we assume the switches are distributed evenly over the W wires. + * In the unidirectional case, all these switches are then crammed down to W/wire_segment_length wires. + * + * Unidirectional: 2 * #opins_per_side * Fc_out * wire_segment_length + * Bidirectional: 2 * #opins_per_side * Fc_out + * + * 2) wire to wire switch + * A wire segment in a switchblock connects to Fs other wires. Assuming these connections are evenly + * distributed, each target wire receives Fs connections as well. In the unidirectional case, + * source wires can only connect to W/wire_segment_length wires. + * + * Unidirectional: Fs * wire_segment_length + * Bidirectional: Fs + * + * 3) wire to ipin switch + * An input pin of a CLB simply receives Fc_in connections. + * + * Unidirectional: Fc_in + * Bidirectional: Fc_in + */ + + /* Fan-in to opin/ipin/wire switches depends on whether the architecture is unidirectional/bidirectional */ + (*opin_switch_fanin) = 2.f * type->num_drivers / 4.f * Fc_out; + (*wire_switch_fanin) = routing_arch.Fs; + (*ipin_switch_fanin) = Fc_in; + if (routing_arch.directionality == UNI_DIRECTIONAL) { + /* adjustments to opin-to-wire and wire-to-wire switch fan-ins */ + (*opin_switch_fanin) *= wire_segment_length; + (*wire_switch_fanin) *= wire_segment_length; + } else if (routing_arch.directionality == BI_DIRECTIONAL) { + /* no adjustments need to be made here */ + } else { + VPR_FATAL_ERROR(VPR_ERROR_PACK, "Unrecognized directionality: %d\n", + (int)routing_arch.directionality); + } +} + +float PreClusterTimingManager::calc_atom_setup_criticality(AtomBlockId blk_id, + const AtomNetlist& atom_netlist) const { + VTR_ASSERT_SAFE_MSG(is_valid_, + "PreClusterTimingManager has not been initialized"); + VTR_ASSERT_SAFE_MSG(blk_id.is_valid(), + "Invalid block ID"); + + float crit = 0.0f; + for (AtomPinId in_pin : atom_netlist.block_input_pins(blk_id)) { + // Max criticality over incoming nets + float pin_crit = timing_info_->setup_pin_criticality(in_pin); + crit = std::max(crit, pin_crit); + } + + return crit; +} + +float PreClusterTimingManager::calc_net_setup_criticality(AtomNetId net_id, + const AtomNetlist& atom_netlist) const { + VTR_ASSERT_SAFE_MSG(is_valid_, + "PreClusterTimingManager has not been initialized"); + VTR_ASSERT_SAFE_MSG(net_id.is_valid(), + "Invalid net ID"); + + // We let the criticality of an entire net to be the max criticality of all + // timing edges within the net. Since all timing paths start at the driver, + // this is equivalent to the criticality of the driver pin. + AtomPinId net_driver_pin_id = atom_netlist.net_driver(net_id); + VTR_ASSERT_SAFE_MSG(net_driver_pin_id.is_valid(), + "Net has no driver"); + return timing_info_->setup_pin_criticality(net_driver_pin_id); +} diff --git a/vpr/src/timing/PreClusterTimingManager.h b/vpr/src/timing/PreClusterTimingManager.h new file mode 100644 index 00000000000..0aaed6edea1 --- /dev/null +++ b/vpr/src/timing/PreClusterTimingManager.h @@ -0,0 +1,119 @@ +/** + * @file + * @author Alex Singer + * @date April 2025 + * @brief Manager class for pre-cluster (primitive-level) timing analysis. + */ + +#pragma once + +#include +#include +#include "vpr_types.h" +#include "vtr_assert.h" + +// Forward declarations. +class AtomLookup; +class AtomNetlist; +class PreClusterDelayCalculator; +class Prepacker; +class SetupTimingInfo; + +/** + * @brief Pre-cluster timing manager class. + * + * This class encapsulates the timing computations used prior to clustering. + * This maintains all of the state necessary to perform these timing computations. + */ +class PreClusterTimingManager { + public: + /** + * @brief Constructor for the manager class. + * + * If timing_driven is set to true, this constructor will perform a setup + * timing analysis with a pre-clustered delay model. The delay model uses + * the primitive delays specified in the architecture file and a simple + * estimate of routing (a typical routing delay based on the wire delays + * found in the architecture, and more specific delays for direct connections + * like carry chains whose use we already know from the pre-packing). + * + * @param timing_driven + * Whether this class should compute timing information or not. This + * may seem counter-intuitive, but this class still needs to exist + * even if timing is turned off. This will not initialize anything + * and set the valid flag to false if we are not timing driven. + * @param atom_netlist + * The primitive netlist to perform timing analysis over. + * @param atom_lookup + * A lookup between the primitives and their timing nodes. + * @param prepacker + * The prepacker object used to prepack primitives into molecules. + * @param timing_update_type + * The type of timing update this class should perform. + * @param arch + * The architecture. + * @param routing_arch + * The routing architecture. + * @param analysis opts + * Options for the timing analysis in VPR. + */ + PreClusterTimingManager(bool timing_driven, + const AtomNetlist& atom_netlist, + const AtomLookup& atom_lookup, + const Prepacker& prepacker, + e_timing_update_type timing_update_type, + const t_arch& arch, + const t_det_routing_arch& routing_arch, + const std::string& device_layout, + const t_analysis_opts& analysis_opts); + + /** + * @brief Calculates the setup criticality of the given primitive block. + * + * Currently defined as the maximum criticality over the block inputs. + */ + float calc_atom_setup_criticality(AtomBlockId blk_id, + const AtomNetlist& atom_netlist) const; + + /** + * @brief Calculates the setup criticality of the given net in the primitive + * netlist. + * + * Currently defined as the maximum criticality over all edges in the net + * from the driver pin to the sink pins. This is equivalent to the criticality + * of the driver pin. + */ + float calc_net_setup_criticality(AtomNetId net_id, + const AtomNetlist& atom_netlist) const; + + /** + * @brief Returns whether or not the pre-cluster timing manager was + * initialized (i.e. timing information can be computed). + */ + bool is_valid() const { + return is_valid_; + } + + /** + * @brief Get a reference to the setup timing info. + */ + const SetupTimingInfo& get_timing_info() const { + VTR_ASSERT_SAFE_MSG(is_valid_, + "Timing manager has not been initialized"); + return *timing_info_; + } + + private: + /// @brief A valid flag used to signify if the pre-cluster timing manager + /// class has been initialized or not. For example, if the flow is + /// not timing-driven, then this class will just be a shell which + /// should not have any timing information (but the object exists). + bool is_valid_; + + /// @brief The delay calculator used for computing timing. + std::shared_ptr clustering_delay_calc_; + + /// @brief The setup timing info used for getting the timing of edges + /// in the timing graph. + std::shared_ptr timing_info_; +}; diff --git a/vpr/src/timing/VprTimingGraphResolver.cpp b/vpr/src/timing/VprTimingGraphResolver.cpp index fa5dc1ae960..791615e5585 100644 --- a/vpr/src/timing/VprTimingGraphResolver.cpp +++ b/vpr/src/timing/VprTimingGraphResolver.cpp @@ -34,7 +34,7 @@ std::string VprTimingGraphResolver::node_type_name(tatum::NodeId node) const { //Annotate primitive grid location, if known auto& atom_ctx = g_vpr_ctx.atom(); auto& block_locs = blk_loc_registry_.block_locs(); - ClusterBlockId cb = atom_ctx.lookup.atom_clb(blk); + ClusterBlockId cb = atom_ctx.lookup().atom_clb(blk); if (cb && block_locs.count(cb)) { int x = block_locs[cb].loc.x; int y = block_locs[cb].loc.y; @@ -174,11 +174,11 @@ std::vector VprTimingGraphResolver::interconnect_delay_br tatum::Time sink_clb_delay; if (is_flat_) { - AtomNetId tmp_atom_net = atom_ctx.nlist.pin_net((AtomPinId&)src_pin); - VTR_ASSERT(tmp_atom_net == atom_ctx.nlist.pin_net((AtomPinId&)sink_pin)); + AtomNetId tmp_atom_net = atom_ctx.netlist().pin_net((AtomPinId&)src_pin); + VTR_ASSERT(tmp_atom_net == atom_ctx.netlist().pin_net((AtomPinId&)sink_pin)); - AtomBlockId tmp_atom_src_block = atom_ctx.nlist.pin_block((AtomPinId&)src_pin); - AtomBlockId tmp_atom_sink_block = atom_ctx.nlist.pin_block((AtomPinId&)sink_pin); + AtomBlockId tmp_atom_src_block = atom_ctx.netlist().pin_block((AtomPinId&)src_pin); + AtomBlockId tmp_atom_sink_block = atom_ctx.netlist().pin_block((AtomPinId&)sink_pin); src_blk = (ParentBlockId&)tmp_atom_src_block; sink_blk = (ParentBlockId&)tmp_atom_sink_block; @@ -188,7 +188,7 @@ std::vector VprTimingGraphResolver::interconnect_delay_br driver_clb_delay = tatum::Time(0); sink_clb_delay = tatum::Time(0); - sink_net_pin_index = g_vpr_ctx.atom().nlist.pin_net_index((AtomPinId&)sink_pin); + sink_net_pin_index = g_vpr_ctx.atom().netlist().pin_net_index((AtomPinId&)sink_pin); } else { ClusterNetId tmp_cluster_net = cluster_ctx.clb_nlist.pin_net((ClusterPinId&)src_pin); @@ -218,7 +218,7 @@ std::vector VprTimingGraphResolver::interconnect_delay_br //driver_component.inst_name = cluster_ctx.clb_nlist.block_name(src_blk); driver_component.type_name = "intra '"; if (is_flat_) { - const t_pb* atom_pb = atom_ctx.lookup.atom_pb((AtomBlockId&)src_blk); + const t_pb* atom_pb = atom_ctx.lookup().atom_pb_bimap().atom_pb((AtomBlockId&)src_blk); driver_component.type_name += (std::string(atom_pb->name) + "(" + atom_pb->hierarchical_type_name() + ")"); } else { driver_component.type_name += cluster_ctx.clb_nlist.block_type((ClusterBlockId&)src_blk)->name; @@ -263,7 +263,7 @@ std::vector VprTimingGraphResolver::interconnect_delay_br //sink_component.inst_name = cluster_ctx.clb_nlist.block_name(sink_blk); sink_component.type_name = "intra '"; if (is_flat_) { - sink_component.type_name += atom_ctx.lookup.atom_pb((AtomBlockId&)sink_blk)->name; + sink_component.type_name += atom_ctx.lookup().atom_pb_bimap().atom_pb((AtomBlockId&)sink_blk)->name; } else { sink_component.type_name += cluster_ctx.clb_nlist.block_type((ClusterBlockId&)sink_blk)->name; } @@ -283,8 +283,8 @@ void VprTimingGraphResolver::set_detail_level(e_timing_report_detail report_deta } void VprTimingGraphResolver::get_detailed_interconnect_components(std::vector& components, ParentNetId net_id, ParentPinId sink_pin) const { - /* This routine obtains the interconnect components such as: OPIN, CHANX, CHANY, IPIN which join - * two intra-block clusters in two parts. In part one, we construct the route tree + /* This routine obtains the interconnect components such as: OPIN, CHANX, CHANY, IPIN which join + * two intra-block clusters in two parts. In part one, we construct the route tree * from the traceback and computes its value for R, C, and Tdel. Next, we find the pointer to * the route tree sink which corresponds to the sink_pin. In part two, we call the helper function, * which walks the route tree from the sink to the source. Along the way, we process each node @@ -295,7 +295,7 @@ void VprTimingGraphResolver::get_detailed_interconnect_components(std::vector&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + auto& netlist = is_flat_ ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; int ipin = netlist.pin_net_index(sink_pin); RRNodeId sink_rr_inode = RRNodeId(route_ctx.net_rr_terminals[net_id][ipin]); //obtain the value of the routing resource sink diff --git a/vpr/src/timing/concrete_timing_info.h b/vpr/src/timing/concrete_timing_info.h index ce02e2abe90..d534e597c70 100644 --- a/vpr/src/timing/concrete_timing_info.h +++ b/vpr/src/timing/concrete_timing_info.h @@ -28,7 +28,7 @@ class ConcreteSetupTimingInfo : public SetupTimingInfo { , timing_constraints_(timing_constraints_v) , delay_calc_(delay_calc) , setup_analyzer_(analyzer_v) - , slack_crit_(g_vpr_ctx.atom().nlist, g_vpr_ctx.atom().lookup) { + , slack_crit_(g_vpr_ctx.atom().netlist(), g_vpr_ctx.atom().lookup()) { //pass } @@ -184,7 +184,7 @@ class ConcreteHoldTimingInfo : public HoldTimingInfo { , timing_constraints_(timing_constraints_v) , delay_calc_(delay_calc) , hold_analyzer_(analyzer_v) - , slack_crit_(g_vpr_ctx.atom().nlist, g_vpr_ctx.atom().lookup) { + , slack_crit_(g_vpr_ctx.atom().netlist(), g_vpr_ctx.atom().lookup()) { //pass } diff --git a/vpr/src/timing/read_sdc.cpp b/vpr/src/timing/read_sdc.cpp index 202a3cfe6e0..e8db27b9a28 100644 --- a/vpr/src/timing/read_sdc.cpp +++ b/vpr/src/timing/read_sdc.cpp @@ -1,5 +1,6 @@ #include "read_sdc.h" +#include #include #include "vtr_log.h" @@ -741,13 +742,14 @@ class SdcParseCallback : public sdcparse::Callback { VTR_ASSERT_MSG(capture_clock.period >= 0., "Clock period must be positive"); float constraint = std::numeric_limits::quiet_NaN(); - - if (std::fabs(launch_clock.period - capture_clock.period) < EPSILON && std::fabs(launch_clock.rise_edge - capture_clock.rise_edge) < EPSILON && std::fabs(launch_clock.fall_edge - capture_clock.fall_edge) < EPSILON) { + if (vtr::isclose(launch_clock.period, capture_clock.period) + && vtr::isclose(launch_clock.rise_edge, capture_clock.rise_edge) + && vtr::isclose(launch_clock.fall_edge, capture_clock.fall_edge)) { //The source and sink domains have the same period and edges, the constraint is the common clock period. constraint = launch_clock.period; - } else if (launch_clock.period < EPSILON || capture_clock.period < EPSILON) { + } else if (vtr::isclose(launch_clock.period, 0.0) || vtr::isclose(capture_clock.period, 0.0)) { //If either period is 0, the constraint is 0 constraint = 0.; diff --git a/vpr/src/timing/slack_evaluation.cpp b/vpr/src/timing/slack_evaluation.cpp index 464bc4bc031..7d14d50c201 100644 --- a/vpr/src/timing/slack_evaluation.cpp +++ b/vpr/src/timing/slack_evaluation.cpp @@ -8,9 +8,9 @@ #include "vtr_time.h" #if defined(VPR_USE_TBB) -# include -# include -# include +#include +#include +#include #endif template diff --git a/vpr/src/timing/timing_graph_builder.cpp b/vpr/src/timing/timing_graph_builder.cpp index 49534b9d380..78bbbe63ba2 100644 --- a/vpr/src/timing/timing_graph_builder.cpp +++ b/vpr/src/timing/timing_graph_builder.cpp @@ -7,23 +7,23 @@ * The Timing Graph is a directed acyclic graph (DAG) consisting of nodes and edges: * - Nodes: represent netlist pins (tatum::IPIN, tatum::OPIN) and logical sources/ * sinks like primary inputs/outpus, flip-flops and clock generators (tatum::SOURCE, - * tatum::SINK). + * tatum::SINK). * * Note that tatum::SOURCE/tatum::SINK represent the start/end of * a timing path. As a result tatum::SOURCE's hould never have input edges (except - * perhaps from a tatum::CPIN if it is a sequential source), and tatum::SINKS's + * perhaps from a tatum::CPIN if it is a sequential source), and tatum::SINKS's * should never have output edges. * - * - Edges: represent the timing dependences between nodes in the timing graph. - * These correspond to net connections, combinational paths inside primitives, + * - Edges: represent the timing dependences between nodes in the timing graph. + * These correspond to net connections, combinational paths inside primitives, * clock-to-q, and setup/hold constraints for sequential elements. * - * The timing graph is constructed by first creating timing sub-graphs corresponding to - * each primitive block in the AtomNetlist. Each sub-graph contains the timing graph + * The timing graph is constructed by first creating timing sub-graphs corresponding to + * each primitive block in the AtomNetlist. Each sub-graph contains the timing graph * nodes required to represent the primitive, and all internal timing graph edges (i.e. * those completely contained within the primitive). * - * Next timing graph edges corresponding to nets in the netlist (i.e. connections between + * Next timing graph edges corresponding to nets in the netlist (i.e. connections between * netlist primitives) are created to "stitch" the sub-graph together. This results in a * timing graph corresponding to the netlist. * @@ -31,18 +31,18 @@ * Modelling Primitive Combinational and Sequential Logic as a Timing Graph * ----------------------------------------------------------------------- * - * Consider the architectural primitive block below, which contains two - * sequential elements 'A' and 'B' (controlled by the primitive input + * Consider the architectural primitive block below, which contains two + * sequential elements 'A' and 'B' (controlled by the primitive input * pin 'clk'), and two clouds of combinational logic 'C' and 'D'. * - * The combinational logic 'D' is driven by primtive input 'e' and + * The combinational logic 'D' is driven by primtive input 'e' and * drives primitive output pin 'g'. * * The combinational logic 'C' is driven by the sequential element 'A' and - * primitive input pin 'e'; it then drives the input of the sequential + * primitive input pin 'e'; it then drives the input of the sequential * element 'B'. * - * Sequential element 'A' is driven by primitive input 'f', and sequential + * Sequential element 'A' is driven by primitive input 'f', and sequential * element 'B' drives primitive output pin 'h'. * * +---------------------------------------+ @@ -50,7 +50,7 @@ * | --- | * | / \ | * e --->-----------------+----->| D |-------->|--> g - * | | \ / | + * | | \ / | * | | --- | * | v ^ | * | --- | | @@ -82,9 +82,9 @@ * * which all must be modelled by the timing graph: * - * Modelling combinational logic is simple, and only requires that there is - * a timing graph edge (tedge) between the corresponding timing graph nodes - * (STA only considers the topological structure of the netlist, not it's + * Modelling combinational logic is simple, and only requires that there is + * a timing graph edge (tedge) between the corresponding timing graph nodes + * (STA only considers the topological structure of the netlist, not it's * logic functionality). * * For instance, to model the combinational logic 'D', we use two tnodes as @@ -94,12 +94,12 @@ * --->| IPIN e |------->| OPIN g |---> * +--------+ +--------+ * - * where 'IPIN e' and 'OPIN g' respectively corresponds to the primitive + * where 'IPIN e' and 'OPIN g' respectively corresponds to the primitive * input 'e' and output 'g' and the edge between them the timing dependency * through the combinational logic 'D'. * * - * To model a sequential element like 'B', we use three timing graph + * To model a sequential element like 'B', we use three timing graph * nodes as follows: * * +--------+ +--------+ @@ -113,13 +113,13 @@ * --->| CPIN | * +--------+ * - * Where 'SINK B' represents the data input of sequential element 'B' (e.g. - * Flip-Flop D pin), 'SRC B' the data output (SOURCE) of sequential element - * 'B' (e.g. Flip-Flop Q pin), and 'CPIN' the clock input pin of sequential + * Where 'SINK B' represents the data input of sequential element 'B' (e.g. + * Flip-Flop D pin), 'SRC B' the data output (SOURCE) of sequential element + * 'B' (e.g. Flip-Flop Q pin), and 'CPIN' the clock input pin of sequential * element 'B'. * * - * Following the above transformations, we arrive at the following timing graph + * Following the above transformations, we arrive at the following timing graph * structure, which corresponds to the architectural primitive described above: * * +--------+ +--------+ @@ -145,9 +145,9 @@ * | |------------------------------+ | * --->| CPIN clk | | * | |-----------------------------------------------+ - * +----------+ + * +----------+ * - * Note that we have also used only a single CPIN for both 'A' and 'B' (since + * Note that we have also used only a single CPIN for both 'A' and 'B' (since * they are controlled by the same clock). * * @@ -156,29 +156,29 @@ * ---------------------------------------------------- * * VPR does not directly model the intenals of netlist primitives (e.g. internal - * sequential elements like 'A' or 'B' above). Instead, various attributes are + * sequential elements like 'A' or 'B' above). Instead, various attributes are * tagged on the pins of the primitive which indicate: * - whether a pin is sequential, combinational or a clock - * - whether the pin is combinationally connected to another pin + * - whether the pin is combinationally connected to another pin * within the primitive. - * + * * Mostly there is a one-to-one correspondance between netlist pins and tnodes, * the only exception is for sequential-sequential connections within a primtive * (e.g. the fully internal 'A' to 'B' timing path above). * * As a result we make a distinction between tnodes which are strictly "internal" * to a primitive, and those which are "external" (i.e. connect to tnodes outside - * the primitive). Note that this distinction is just a labelling which is only - * relevant to how VPR tracks the relation between tnodes and netlist pins. It - * has no effect on the timing analysis result (which only depends on the - * structure of the timing graph). Most of VPR doesn't care about the internal + * the primitive). Note that this distinction is just a labelling which is only + * relevant to how VPR tracks the relation between tnodes and netlist pins. It + * has no effect on the timing analysis result (which only depends on the + * structure of the timing graph). Most of VPR doesn't care about the internal * timing paths, as they are typically uneffected by any of VPR's optimization - * choices. Therefore most of VPR only considers "external" tnodes when mapping + * choices. Therefore most of VPR only considers "external" tnodes when mapping * between netlist pins and tnodes. Of course we record both so the parts of VPR * which *do* care about them (e.g. the code here, and in the delay calculator) * can figure out the correct mapping. * - * As a result the timing graph we build (for the primitive example above) is + * As a result the timing graph we build (for the primitive example above) is * described within VPR as: * * +------------+ +------------+ @@ -207,12 +207,12 @@ * | CPIN clk |--------------------------------+ | * --->| | | * | (external) |--------------------------------------------------+ - * +------------+ + * +------------+ * - * Where each pin in the netlist corresponds to an "external" tnode, but the - * sequential netlist pins 'f' and 'h' have additional "internal" tnodes + * Where each pin in the netlist corresponds to an "external" tnode, but the + * sequential netlist pins 'f' and 'h' have additional "internal" tnodes * corresponding to their respective data outputs/inputs within the primitive. - * Also note that combinational pins are makred as both internal and external + * Also note that combinational pins are makred as both internal and external * for convenience (i.e. both map to the same tnode). * */ @@ -371,9 +371,9 @@ void TimingGraphBuilder::add_block_to_timing_graph(const AtomBlockId blk) { * Once all nodes have been created the edges are added between them according * to what was specified in the architecture file models. * - * Note that to minimize the size of the timing graph we only create tnodes and - * edges where they actually exist within the netlist. This means we do not create - * tnodes or tedges to/from pins which are disconnected in the netlist (even if + * Note that to minimize the size of the timing graph we only create tnodes and + * edges where they actually exist within the netlist. This means we do not create + * tnodes or tedges to/from pins which are disconnected in the netlist (even if * they exist in the architecture). * * diff --git a/vpr/src/timing/timing_graph_builder.h b/vpr/src/timing/timing_graph_builder.h index 92de6afdf3d..1f1624eed81 100644 --- a/vpr/src/timing/timing_graph_builder.h +++ b/vpr/src/timing/timing_graph_builder.h @@ -6,14 +6,14 @@ #include "atom_lookup.h" /* - * Class for constructing a Timing Graph (a tatum::TimingGraph, for use with the Tatum - * STA engine) from the provided AtomNetlist. It also updates the provided AtomLookup + * Class for constructing a Timing Graph (a tatum::TimingGraph, for use with the Tatum + * STA engine) from the provided AtomNetlist. It also updates the provided AtomLookup * with the mapping from netlist elements to timing graph nodes. * - * To construct a timing graph initialize this class with the netlist and lookup + * To construct a timing graph initialize this class with the netlist and lookup * (via constructor), and call the timing_graph() method. * - * For details on how the timing graph is constructed from the netlist, see the comments + * For details on how the timing graph is constructed from the netlist, see the comments * in the associated .cpp implementation file. */ class TimingGraphBuilder { diff --git a/vpr/src/timing/timing_util.cpp b/vpr/src/timing/timing_util.cpp index e51fadf5d42..94191667499 100644 --- a/vpr/src/timing/timing_util.cpp +++ b/vpr/src/timing/timing_util.cpp @@ -485,20 +485,20 @@ float find_total_negative_slack_within_clb_blocks(const tatum::HoldTimingAnalyze VTR_ASSERT(origin_node); /*Retrieve the source and sink clb blocks corresponding to these timing nodes*/ - AtomPinId origin_pin = atom_ctx.lookup.tnode_atom_pin(origin_node); - AtomPinId pin = atom_ctx.lookup.tnode_atom_pin(node); + AtomPinId origin_pin = atom_ctx.lookup().tnode_atom_pin(origin_node); + AtomPinId pin = atom_ctx.lookup().tnode_atom_pin(node); VTR_ASSERT(origin_pin); VTR_ASSERT(pin); - AtomBlockId atom_src_block = atom_ctx.nlist.pin_block(origin_pin); - AtomBlockId atom_sink_block = atom_ctx.nlist.pin_block(pin); + AtomBlockId atom_src_block = atom_ctx.netlist().pin_block(origin_pin); + AtomBlockId atom_sink_block = atom_ctx.netlist().pin_block(pin); - ClusterBlockId clb_src_block = atom_ctx.lookup.atom_clb(atom_src_block); + ClusterBlockId clb_src_block = atom_ctx.lookup().atom_clb(atom_src_block); VTR_ASSERT(clb_src_block); - ClusterBlockId clb_sink_block = atom_ctx.lookup.atom_clb(atom_sink_block); + ClusterBlockId clb_sink_block = atom_ctx.lookup().atom_clb(atom_sink_block); VTR_ASSERT(clb_sink_block); - const t_pb_graph_pin* sink_gpin = atom_ctx.lookup.atom_pin_pb_graph_pin(pin); + const t_pb_graph_pin* sink_gpin = atom_ctx.lookup().atom_pin_pb_graph_pin(pin); VTR_ASSERT(sink_gpin); int sink_pb_route_id = sink_gpin->pin_count_in_cluster; @@ -843,13 +843,13 @@ tatum::NodeId id_or_pin_name_to_tnode(const std::string& pin_name_or_tnode) { tatum::NodeId pin_name_to_tnode(const std::string& pin_name) { auto& atom_ctx = g_vpr_ctx.atom(); - AtomPinId pin = atom_ctx.nlist.find_pin(pin_name); + AtomPinId pin = atom_ctx.netlist().find_pin(pin_name); if (!pin) { VPR_THROW(VPR_ERROR_ATOM_NETLIST, "Failed to find pin named '%s'\n", pin_name.c_str()); } - tatum::NodeId tnode = atom_ctx.lookup.atom_pin_tnode(pin); + tatum::NodeId tnode = atom_ctx.lookup().atom_pin_tnode(pin); if (!tnode) { VPR_THROW(VPR_ERROR_TIMING, "Failed to find tnode for pin '%s' (pin: %zu)\n", pin_name.c_str(), size_t(pin)); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 447404067b3..f960f5c8668 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -4,11 +4,10 @@ #include #include "pack_types.h" -#include "prepack.h" +#include "physical_types_util.h" #include "vpr_context.h" #include "vtr_assert.h" #include "vtr_log.h" -#include "vtr_memory.h" #include "vpr_types.h" #include "vpr_error.h" @@ -19,7 +18,6 @@ #include "cluster_placement.h" #include "device_grid.h" #include "user_route_constraints.h" -#include "placer_state.h" #include "grid_block.h" /* This module contains subroutines that are used in several unrelated parts * @@ -214,7 +212,7 @@ AtomPinId find_clb_pin_driver_atom_pin(ClusterBlockId clb, int logical_pin, cons AtomPinId atom_pin = find_atom_pin_for_pb_route_id(clb, pb_pin_id, pb_gpin_lookup); VTR_ASSERT(atom_pin); - VTR_ASSERT_MSG(atom_ctx.nlist.pin_net(atom_pin) == atom_net, "Driver atom pin should drive the same net"); + VTR_ASSERT_MSG(atom_ctx.netlist().pin_net(atom_pin) == atom_net, "Driver atom pin should drive the same net"); return atom_pin; } @@ -244,7 +242,7 @@ std::vector find_clb_pin_sink_atom_pins(ClusterBlockId clb, int logic AtomPinId atom_pin = find_atom_pin_for_pb_route_id(clb, sink_pb_pin, pb_gpin_lookup); VTR_ASSERT(atom_pin); - VTR_ASSERT_MSG(atom_ctx.nlist.pin_net(atom_pin) == atom_net, "Sink atom pins should be driven by the same net"); + VTR_ASSERT_MSG(atom_ctx.netlist().pin_net(atom_pin) == atom_net, "Sink atom pins should be driven by the same net"); sink_atom_pins.push_back(atom_pin); } @@ -300,12 +298,12 @@ static AtomPinId find_atom_pin_for_pb_route_id(ClusterBlockId clb, int pb_route_ //It is a leaf, and hence should map to an atom //Find the associated atom - AtomBlockId atom_block = atom_ctx.lookup.pb_atom(child_pb); + AtomBlockId atom_block = atom_ctx.lookup().atom_pb_bimap().pb_atom(child_pb); VTR_ASSERT(atom_block); //Now find the matching pin by seeing which pin maps to the gpin - for (AtomPinId atom_pin : atom_ctx.nlist.block_pins(atom_block)) { - const t_pb_graph_pin* atom_pin_gpin = atom_ctx.lookup.atom_pin_pb_graph_pin(atom_pin); + for (AtomPinId atom_pin : atom_ctx.netlist().block_pins(atom_block)) { + const t_pb_graph_pin* atom_pin_gpin = atom_ctx.lookup().atom_pin_pb_graph_pin(atom_pin); if (atom_pin_gpin == gpin) { //Match return atom_pin; @@ -413,7 +411,7 @@ t_physical_tile_type_ptr physical_tile_type(t_pl_loc loc) { } t_physical_tile_type_ptr physical_tile_type(AtomBlockId atom_blk) { - auto& atom_look_up = g_vpr_ctx.atom().lookup; + auto& atom_look_up = g_vpr_ctx.atom().lookup(); auto& block_locs = g_vpr_ctx.placement().block_locs(); ClusterBlockId cluster_blk = atom_look_up.atom_clb(atom_blk); @@ -512,12 +510,12 @@ t_class_range get_class_range_for_block(const ClusterBlockId blk_id) { } t_class_range get_class_range_for_block(const AtomBlockId atom_blk) { - auto& atom_look_up = g_vpr_ctx.atom().lookup; + auto& atom_look_up = g_vpr_ctx.atom().lookup(); ClusterBlockId cluster_blk = atom_look_up.atom_clb(atom_blk); auto [physical_tile, sub_tile, sub_tile_cap, logical_block] = get_cluster_blk_physical_spec(cluster_blk); - const t_pb_graph_node* pb_graph_node = atom_look_up.atom_pb_graph_node(atom_blk); + const t_pb_graph_node* pb_graph_node = atom_look_up.atom_pb_bimap().atom_pb_graph_node(atom_blk); VTR_ASSERT(pb_graph_node != nullptr); return get_pb_graph_node_class_physical_range(physical_tile, sub_tile, @@ -569,7 +567,7 @@ t_block_loc get_block_loc(const ParentBlockId& block_id, bool is_flat) { if (is_flat) { AtomBlockId atom_block_id = convert_to_atom_block_id(block_id); - auto& atom_look_up = g_vpr_ctx.atom().lookup; + auto& atom_look_up = g_vpr_ctx.atom().lookup(); cluster_block_id = atom_look_up.atom_clb(atom_block_id); } else { cluster_block_id = convert_to_cluster_block_id(block_id); @@ -706,7 +704,7 @@ InstPort parse_inst_port(const std::string& str) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find block type named %s", inst_port.instance_name().c_str()); } - int num_pins = find_tile_port_by_name(blk_type, inst_port.port_name().c_str()).num_pins; + int num_pins = find_tile_port_by_name(blk_type, inst_port.port_name()).num_pins; if (num_pins == OPEN) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find port %s on block type %s", inst_port.port_name().c_str(), inst_port.instance_name().c_str()); @@ -830,12 +828,12 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t } auto& atom_ctx = g_vpr_ctx.atom(); - if (cur_pb_type->model != atom_ctx.nlist.block_model(blk_id)) { + if (cur_pb_type->model != atom_ctx.netlist().block_model(blk_id)) { //Primitive and atom do not match return false; } - VTR_ASSERT_MSG(atom_ctx.nlist.is_compressed(), "This function assumes a compressed/non-dirty netlist"); + VTR_ASSERT_MSG(atom_ctx.netlist().is_compressed(), "This function assumes a compressed/non-dirty netlist"); //Keep track of how many atom ports were checked. // @@ -851,13 +849,13 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t const t_model_ports* pb_model_port = pb_port->model_port; //Find the matching port on the atom - auto port_id = atom_ctx.nlist.find_atom_port(blk_id, pb_model_port); + auto port_id = atom_ctx.netlist().find_atom_port(blk_id, pb_model_port); if (port_id) { //Port is used by the atom //In compressed form the atom netlist stores only in-use pins, //so we can query the number of required pins directly - int required_atom_pins = atom_ctx.nlist.port_pins(port_id).size(); + int required_atom_pins = atom_ctx.netlist().port_pins(port_id).size(); int available_pb_pins = pb_port->num_pins; @@ -874,7 +872,7 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t //Similarly to pins, only in-use ports are stored in the compressed //atom netlist, so we can figure out how many ports should have been //checked directly - size_t atom_ports = atom_ctx.nlist.block_ports(blk_id).size(); + size_t atom_ports = atom_ctx.netlist().block_ports(blk_id).size(); //See if all the atom ports were checked if (checked_ports != atom_ports) { @@ -889,8 +887,7 @@ bool primitive_type_feasible(const AtomBlockId blk_id, const t_pb_type* cur_pb_t //Returns the sibling atom of a memory slice pb // Note that the pb must be part of a MEMORY_CLASS -AtomBlockId find_memory_sibling(const t_pb* pb) { - auto& atom_ctx = g_vpr_ctx.atom(); +const t_pb* find_memory_sibling(const t_pb* pb) { const t_pb_type* pb_type = pb->pb_graph_node->pb_type; @@ -902,10 +899,10 @@ AtomBlockId find_memory_sibling(const t_pb* pb) { const t_pb* sibling_pb = &memory_class_pb->child_pbs[pb->mode][isibling]; if (sibling_pb->name != nullptr) { - return atom_ctx.lookup.pb_atom(sibling_pb); + return sibling_pb; } } - return AtomBlockId::INVALID(); + return nullptr; } /** @@ -963,11 +960,11 @@ AtomPinId find_atom_pin(ClusterBlockId blk_id, const t_pb_graph_pin* pb_gpin) { AtomPinId atom_pin; //Look through all the pins on this net, looking for the matching pin - for (AtomPinId pin : atom_ctx.nlist.net_pins(atom_net)) { - AtomBlockId blk = atom_ctx.nlist.pin_block(pin); - if (atom_ctx.lookup.atom_clb(blk) == blk_id) { + for (AtomPinId pin : atom_ctx.netlist().net_pins(atom_net)) { + AtomBlockId blk = atom_ctx.netlist().pin_block(pin); + if (atom_ctx.lookup().atom_clb(blk) == blk_id) { //Part of the same CLB - if (atom_ctx.lookup.atom_pin_pb_graph_pin(pin) == pb_gpin) + if (atom_ctx.lookup().atom_pin_pb_graph_pin(pin) == pb_gpin) //The same pin atom_pin = pin; } @@ -978,15 +975,13 @@ AtomPinId find_atom_pin(ClusterBlockId blk_id, const t_pb_graph_pin* pb_gpin) { return atom_pin; } -//Retrieves the pb_graph_pin associated with an AtomPinId -// Currently this function just wraps get_pb_graph_node_pin_from_model_port_pin() -// in a more convenient interface. -const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, const AtomPinId pin_id) { +// Retrieves the pb_graph_pin associated with an AtomPinId +const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomPBBimap& atom_pb_lookup, const AtomPinId pin_id) { VTR_ASSERT(pin_id); //Get the graph node AtomBlockId blk_id = netlist.pin_block(pin_id); - const t_pb_graph_node* pb_gnode = netlist_lookup.atom_pb_graph_node(blk_id); + const t_pb_graph_node* pb_gnode = atom_pb_lookup.atom_pb_graph_node(blk_id); VTR_ASSERT(pb_gnode); //The graph node and pin/block should agree on the model they represent @@ -1254,7 +1249,7 @@ std::vector get_cluster_internal_class_pairs(const AtomLookup& atom_lookup, const auto& cluster_atoms = cluster_ctx.atoms_lookup[cluster_block_id]; for (AtomBlockId atom_blk_id : cluster_atoms) { - auto atom_pb_graph_node = atom_lookup.atom_pb_graph_node(atom_blk_id); + auto atom_pb_graph_node = atom_lookup.atom_pb_bimap().atom_pb_graph_node(atom_blk_id); auto class_range = get_pb_graph_node_class_physical_range(physical_tile, sub_tile, logical_block, @@ -1347,16 +1342,16 @@ int num_ext_inputs_atom_block(AtomBlockId blk_id) { //Record the unique input nets auto& atom_ctx = g_vpr_ctx.atom(); - for (auto pin_id : atom_ctx.nlist.block_input_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); + for (auto pin_id : atom_ctx.netlist().block_input_pins(blk_id)) { + auto net_id = atom_ctx.netlist().pin_net(pin_id); input_nets.insert(net_id); } ext_inps = input_nets.size(); //Look through the output nets for any duplicates of the input nets - for (auto pin_id : atom_ctx.nlist.block_output_pins(blk_id)) { - auto net_id = atom_ctx.nlist.pin_net(pin_id); + for (auto pin_id : atom_ctx.netlist().block_output_pins(blk_id)) { + auto net_id = atom_ctx.netlist().pin_net(pin_id); if (input_nets.count(net_id)) { --ext_inps; } @@ -1367,7 +1362,17 @@ int num_ext_inputs_atom_block(AtomBlockId blk_id) { return (ext_inps); } -void free_pb(t_pb* pb) { +/** + * @brief Free pb and remove its lookup data. + * CLB lookup data is removed from the global context + * and PB to Atom bimap data is removed from atom_pb_bimap + * + * @param pb + * Pointer to t_pb to be freed + * @param atom_pb_bimap + * Reference to the atom to pb bimap to free the data from + */ +void free_pb(t_pb* pb, AtomPBBimap& atom_pb_bimap) { if (pb == nullptr) { return; } @@ -1387,7 +1392,7 @@ void free_pb(t_pb* pb) { for (i = 0; i < pb_type->modes[mode].num_pb_type_children && pb->child_pbs != nullptr; i++) { for (j = 0; j < pb_type->modes[mode].pb_type_children[i].num_pb && pb->child_pbs[i] != nullptr; j++) { if (pb->child_pbs[i][j].name != nullptr || pb->child_pbs[i][j].child_pbs != nullptr) { - free_pb(&pb->child_pbs[i][j]); + free_pb(&pb->child_pbs[i][j], atom_pb_bimap); } } if (pb->child_pbs[i]) { @@ -1405,13 +1410,13 @@ void free_pb(t_pb* pb) { } else { /* Primitive */ auto& atom_ctx = g_vpr_ctx.mutable_atom(); - auto blk_id = atom_ctx.lookup.pb_atom(pb); + auto blk_id = atom_pb_bimap.pb_atom(pb); if (blk_id) { //Update atom netlist mapping - atom_ctx.lookup.set_atom_clb(blk_id, ClusterBlockId::INVALID()); - atom_ctx.lookup.set_atom_pb(blk_id, nullptr); + atom_ctx.mutable_lookup().set_atom_clb(blk_id, ClusterBlockId::INVALID()); + atom_pb_bimap.set_atom_pb(blk_id, nullptr); } - atom_ctx.lookup.set_atom_pb(AtomBlockId::INVALID(), pb); + atom_pb_bimap.set_atom_pb(AtomBlockId::INVALID(), pb); } free_pb_stats(pb); } @@ -1473,7 +1478,8 @@ std::tuple parse_direct_pin_name(std::string std::string source_string{src_string}; // Replace '.' and '[' characters with ' ' - std::replace_if(source_string.begin(), source_string.end(), + std::replace_if( + source_string.begin(), source_string.end(), [](char c) { return c == '.' || c == '[' || c == ':' || c == ']'; }, ' '); @@ -1639,8 +1645,8 @@ int max_pins_per_grid_tile() { } int get_atom_pin_class_num(const AtomPinId atom_pin_id) { - auto& atom_look_up = g_vpr_ctx.atom().lookup; - auto& atom_net_list = g_vpr_ctx.atom().nlist; + auto& atom_look_up = g_vpr_ctx.atom().lookup(); + auto& atom_net_list = g_vpr_ctx.atom().netlist(); auto atom_blk_id = atom_net_list.pin_block(atom_pin_id); auto cluster_block_id = atom_look_up.atom_clb(atom_blk_id); @@ -1859,6 +1865,33 @@ bool node_in_same_physical_tile(RRNodeId node_first, RRNodeId node_second) { } } +bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node) { + const auto& device_ctx = g_vpr_ctx.device(); + const auto& rr_graph = device_ctx.rr_graph; + + VTR_ASSERT(rr_graph.node_type(src_rr_node) == SOURCE && rr_graph.node_type(sink_rr_node) == SINK); + + // A direct connection is defined as a specific path: `SOURCE -> OPIN -> IPIN -> SINK`. + //TODO: This is a constant depth search, but still may be too slow + for (t_edge_size i_src_edge = 0; i_src_edge < rr_graph.num_edges(src_rr_node); ++i_src_edge) { + RRNodeId opin_rr_node = rr_graph.edge_sink_node(src_rr_node, i_src_edge); + + if (rr_graph.node_type(opin_rr_node) != OPIN) continue; + + for (t_edge_size i_opin_edge = 0; i_opin_edge < rr_graph.num_edges(opin_rr_node); ++i_opin_edge) { + RRNodeId ipin_rr_node = rr_graph.edge_sink_node(opin_rr_node, i_opin_edge); + if (rr_graph.node_type(ipin_rr_node) != IPIN) continue; + + for (t_edge_size i_ipin_edge = 0; i_ipin_edge < rr_graph.num_edges(ipin_rr_node); ++i_ipin_edge) { + if (sink_rr_node == rr_graph.edge_sink_node(ipin_rr_node, i_ipin_edge)) { + return true; + } + } + } + } + return false; +} + std::vector get_cluster_netlist_intra_tile_classes_at_loc(int layer, int i, int j, @@ -1866,7 +1899,7 @@ std::vector get_cluster_netlist_intra_tile_classes_at_loc(int layer, std::vector class_num_vec; const auto& place_ctx = g_vpr_ctx.placement(); - const auto& atom_lookup = g_vpr_ctx.atom().lookup; + const auto& atom_lookup = g_vpr_ctx.atom().lookup(); const auto& grid_block = place_ctx.grid_blocks(); class_num_vec.reserve(physical_type->primitive_class_inf.size()); @@ -1988,7 +2021,7 @@ void add_pb_child_to_list(std::list& pb_list, const t_pb* parent_pb void apply_route_constraints(const UserRouteConstraints& route_constraints) { ClusteringContext& mutable_cluster_ctx = g_vpr_ctx.mutable_clustering(); - // Iterate through all the nets + // Iterate through all the nets for (auto net_id : mutable_cluster_ctx.clb_nlist.nets()) { // Get the name of the current net std::string net_name = mutable_cluster_ctx.clb_nlist.net_name(net_id); diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 37047ab7152..aa36ce3f03c 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -1,23 +1,19 @@ #ifndef VPR_UTILS_H #define VPR_UTILS_H -#include -#include - -#include "vpr_types.h" -#include "vtr_vector.h" - -#include "atom_netlist.h" -#include "clustered_netlist.h" -#include "netlist.h" #include "arch_util.h" -#include "physical_types_util.h" +#include "atom_netlist.h" +#include "device_grid.h" #include "rr_graph_utils.h" -#include "vpr_constraints.h" +#include "vpr_types.h" +#include "vtr_vector.h" +#include "atom_pb_bimap.h" +#include +#include +// Forward declaration class DeviceGrid; -class PlacerState; -class Prepacker; +class UserRouteConstraints; const t_model* find_model(const t_model* models, const std::string& name, bool required = true); const t_model_ports* find_model_port(const t_model* model, const std::string& name, bool required = true); @@ -171,6 +167,8 @@ const t_port* find_pb_graph_port(const t_pb_graph_node* pb_gnode, const std::str //Returns the graph pin matching name at pin index const t_pb_graph_pin* find_pb_graph_pin(const t_pb_graph_node* pb_gnode, const std::string& port_name, int index); +const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomPBBimap& atom_pb_lookup, const AtomPinId pin_id); + AtomPinId find_atom_pin(ClusterBlockId blk_id, const t_pb_graph_pin* pb_gpin); //Returns the logical block type which is most common in the device grid @@ -191,7 +189,6 @@ int get_max_depth_of_pb_type(t_pb_type* pb_type); int get_max_nets_in_pb_type(const t_pb_type* pb_type); bool primitive_type_feasible(AtomBlockId blk_id, const t_pb_type* cur_pb_type); t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* model_port, const int model_pin, const t_pb_graph_node* pb_graph_node); -const t_pb_graph_pin* find_pb_graph_pin(const AtomNetlist& netlist, const AtomLookup& netlist_lookup, const AtomPinId pin_id); /// @brief Gets the pb_graph_node pin at the given pin index for the given /// pb_graph_node. t_pb_graph_pin* get_pb_graph_node_pin_from_pb_graph_node(t_pb_graph_node* pb_graph_node, int ipin); @@ -225,12 +222,12 @@ int num_ext_inputs_atom_block(AtomBlockId blk_id); std::tuple parse_direct_pin_name(std::string_view src_string, int line); void free_pb_stats(t_pb* pb); -void free_pb(t_pb* pb); +void free_pb(t_pb* pb, AtomPBBimap& atom_pb_bimap); void print_switch_usage(); void print_usage_by_wire_length(); -AtomBlockId find_memory_sibling(const t_pb* pb); +const t_pb* find_memory_sibling(const t_pb* pb); int get_atom_pin_class_num(const AtomPinId atom_pin_id); @@ -271,9 +268,28 @@ RRNodeId get_class_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, const int j, int class_physical_num); -// Check whether the given nodes are in the same cluster +/// @brief Check whether the given nodes are in the same cluster bool node_in_same_physical_tile(RRNodeId node_first, RRNodeId node_second); +/** + * @brief Checks if a direct connection exists between two RR nodes. + * + * A direct connection is defined as a specific path: `SOURCE -> OPIN -> IPIN -> SINK`. + * + * @param src_rr_node The source RR node (must be of type `SOURCE`). + * @param sink_rr_node The sink RR node (must be of type `SINK`). + * + * @return `true` if a direct connection exists between the source and sink nodes; + * otherwise, `false`. + * + * @details + * - The function performs a depth-limited search starting from the source node, + * traversing through OPIN, IPIN, and finally checking if the path reaches the sink node. + * - Ensures the specified node types are respected (e.g., source node must be of type `SOURCE`). + */ + +bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node); + std::vector get_cluster_netlist_intra_tile_classes_at_loc(int layer, int i, int j, diff --git a/vpr/test/test_ap_netlist.cpp b/vpr/test/test_ap_netlist.cpp index 9dad87819ca..b88528c721e 100644 --- a/vpr/test/test_ap_netlist.cpp +++ b/vpr/test/test_ap_netlist.cpp @@ -11,7 +11,7 @@ #include "catch2/catch_test_macros.hpp" #include "ap_netlist.h" -#include "vpr_types.h" +#include "prepack.h" namespace { @@ -19,18 +19,18 @@ TEST_CASE("test_ap_netlist_data_storage", "[vpr_ap_netlist]") { // Create a test netlist object. APNetlist test_netlist("test_netlist"); // Create a few molecules. - t_pack_molecule mol_a; - t_pack_molecule mol_b; - t_pack_molecule mol_c; + PackMoleculeId mol_a_id; + PackMoleculeId mol_b_id; + PackMoleculeId mol_c_id; // Create blocks for these molecules. - APBlockId block_id_a = test_netlist.create_block("BlockA", &mol_a); - APBlockId block_id_b = test_netlist.create_block("BlockB", &mol_b); - APBlockId block_id_c = test_netlist.create_block("BlockC", &mol_c); + APBlockId block_id_a = test_netlist.create_block("BlockA", mol_a_id); + APBlockId block_id_b = test_netlist.create_block("BlockB", mol_b_id); + APBlockId block_id_c = test_netlist.create_block("BlockC", mol_c_id); SECTION("Test block_molecule returns the correct molecule after creation") { - REQUIRE(test_netlist.block_molecule(block_id_a) == &mol_a); - REQUIRE(test_netlist.block_molecule(block_id_b) == &mol_b); - REQUIRE(test_netlist.block_molecule(block_id_c) == &mol_c); + REQUIRE(test_netlist.block_molecule(block_id_a) == mol_a_id); + REQUIRE(test_netlist.block_molecule(block_id_b) == mol_b_id); + REQUIRE(test_netlist.block_molecule(block_id_c) == mol_c_id); } // Delete block B to reorganize the blocks internally. @@ -42,13 +42,13 @@ TEST_CASE("test_ap_netlist_data_storage", "[vpr_ap_netlist]") { block_id_c = test_netlist.find_block("BlockC"); SECTION("Test block_molecule returns the correct molecule after compression") { - REQUIRE(test_netlist.block_molecule(block_id_a) == &mol_a); - REQUIRE(test_netlist.block_molecule(block_id_c) == &mol_c); + REQUIRE(test_netlist.block_molecule(block_id_a) == mol_a_id); + REQUIRE(test_netlist.block_molecule(block_id_c) == mol_c_id); } // Create a new block, and fix its location. - t_pack_molecule fixed_mol; - APBlockId fixed_block_id = test_netlist.create_block("FixedBlock", &fixed_mol); + PackMoleculeId fixed_mol_id; + APBlockId fixed_block_id = test_netlist.create_block("FixedBlock", fixed_mol_id); APFixedBlockLoc fixed_block_loc; fixed_block_loc.x = 12; fixed_block_loc.y = 42; @@ -74,4 +74,3 @@ TEST_CASE("test_ap_netlist_data_storage", "[vpr_ap_netlist]") { } } // namespace - diff --git a/vpr/test/test_ap_partial_placement.cpp b/vpr/test/test_ap_partial_placement.cpp index c460df48227..29abf5b705b 100644 --- a/vpr/test/test_ap_partial_placement.cpp +++ b/vpr/test/test_ap_partial_placement.cpp @@ -12,7 +12,7 @@ #include "ap_netlist.h" #include "partial_placement.h" -#include "vpr_types.h" +#include "prepack.h" namespace { @@ -20,13 +20,13 @@ TEST_CASE("test_ap_partial_placement_verify", "[vpr_ap]") { // Create a test netlist object. APNetlist test_netlist("test_netlist"); // Create a few molecules. - t_pack_molecule mol_a; - t_pack_molecule mol_b; - t_pack_molecule mol_c; + PackMoleculeId mol_a_id; + PackMoleculeId mol_b_id; + PackMoleculeId mol_c_id; // Create blocks for these molecules. - APBlockId block_id_a = test_netlist.create_block("BlockA", &mol_a); - APBlockId block_id_b = test_netlist.create_block("BlockB", &mol_b); - APBlockId block_id_c = test_netlist.create_block("BlockC", &mol_c); + APBlockId block_id_a = test_netlist.create_block("BlockA", mol_a_id); + APBlockId block_id_b = test_netlist.create_block("BlockB", mol_b_id); + APBlockId block_id_c = test_netlist.create_block("BlockC", mol_c_id); // Fix BlockC. APFixedBlockLoc fixed_block_loc; fixed_block_loc.x = 12; @@ -131,4 +131,3 @@ TEST_CASE("test_ap_partial_placement_verify", "[vpr_ap]") { } } // namespace - diff --git a/vpr/test/test_ap_primitive_vector.cpp b/vpr/test/test_ap_primitive_vector.cpp index e1f114919bb..425f4e20f35 100644 --- a/vpr/test/test_ap_primitive_vector.cpp +++ b/vpr/test/test_ap_primitive_vector.cpp @@ -8,6 +8,7 @@ * PrimitiveVector object are working as expected. */ +#include #include "catch2/catch_test_macros.hpp" #include "primitive_vector.h" @@ -310,7 +311,60 @@ TEST_CASE("test_ap_primitive_vector_verify", "[vpr_ap]") { res = PrimitiveVector::max(vec2, vec1); REQUIRE(res == golden); } + + SECTION("Test more operators and methods") { + PrimitiveVector vec1, vec2; + + // Subtract value from dimension + vec1.set_dim_val(0, 5.f); + vec1.subtract_val_from_dim(3.f, 0); + REQUIRE(vec1.get_dim_val(0) == 2.f); + + // Element-wise addition operator + vec1.clear(); + vec1.set_dim_val(0, 1.f); + vec1.set_dim_val(1, 2.f); + vec2.clear(); + vec2.set_dim_val(0, 3.f); + vec2.set_dim_val(1, 4.f); + PrimitiveVector vec_sum = vec1 + vec2; + REQUIRE(vec_sum.get_dim_val(0) == 4.f); + REQUIRE(vec_sum.get_dim_val(1) == 6.f); + + // Element-wise division operator + vec1.clear(); + vec1.set_dim_val(0, 10.f); + vec1.set_dim_val(1, 20.f); + vec1 /= 2.f; + REQUIRE(vec1.get_dim_val(0) == 5.f); + REQUIRE(vec1.get_dim_val(1) == 10.f); + + // Element-wise division operator (const) + vec1.clear(); + vec1.set_dim_val(0, 10.f); + vec1.set_dim_val(1, 20.f); + PrimitiveVector vec_div = vec1 / 2.f; + REQUIRE(vec_div.get_dim_val(0) == 5.f); + REQUIRE(vec_div.get_dim_val(1) == 10.f); + + // Get non-zero dimensions + vec1.clear(); + vec1.set_dim_val(0, 1.f); + vec1.set_dim_val(2, 3.f); + std::vector non_zero_dims = vec1.get_non_zero_dims(); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 0) != non_zero_dims.end()); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 2) != non_zero_dims.end()); + REQUIRE(std::find(non_zero_dims.begin(), non_zero_dims.end(), 1) == non_zero_dims.end()); + + // Test orthogonal vectors + vec1.clear(); + vec2.clear(); + vec1.set_dim_val(0, 1.f); + vec2.set_dim_val(1, 2.f); + REQUIRE(vec1.are_dims_disjoint(vec2)); + vec2.set_dim_val(0, 3.f); + REQUIRE(!vec1.are_dims_disjoint(vec2)); + } } } // namespace - diff --git a/vpr/test/test_bfs_routing.cpp b/vpr/test/test_bfs_routing.cpp index c0c03a9ad1d..61d98a3c200 100644 --- a/vpr/test/test_bfs_routing.cpp +++ b/vpr/test/test_bfs_routing.cpp @@ -139,4 +139,4 @@ TEST_CASE("test_route_flow", "[vpr_noc_bfs_routing]") { } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_clustered_netlist.cpp b/vpr/test/test_clustered_netlist.cpp index cd0059c173e..bcd42988068 100644 --- a/vpr/test/test_clustered_netlist.cpp +++ b/vpr/test/test_clustered_netlist.cpp @@ -146,4 +146,4 @@ TEST_CASE("test_find_block_with_matching_name", "[vpr_clustered_netlist]") { REQUIRE((size_t)(block_id_from_name.find("router:noc_router_four|flit_out_two[0]~reg0")->second) == (size_t)test_router_id); } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_compressed_grid.cpp b/vpr/test/test_compressed_grid.cpp index 86c2d1f6600..028a1164af9 100644 --- a/vpr/test/test_compressed_grid.cpp +++ b/vpr/test/test_compressed_grid.cpp @@ -12,8 +12,7 @@ namespace { -void set_type_tile_to_empty(const int x, const int y, - vtr::NdMatrix& grid) { +void set_type_tile_to_empty(const int x, const int y, vtr::NdMatrix& grid) { t_physical_tile_type_ptr type = grid[0][x][y].type; const int width_offset = grid[0][x][y].width_offset; const int height_offset = grid[0][x][y].height_offset; @@ -29,12 +28,9 @@ void set_type_tile_to_empty(const int x, const int y, } } } - } -void set_tile_type_at_loc(const int x_anchor, const int y_anchor, - vtr::NdMatrix& grid, - const t_physical_tile_type& tile_type) { +void set_tile_type_at_loc(const int x_anchor, const int y_anchor, vtr::NdMatrix& grid, const t_physical_tile_type& tile_type) { for (int i = x_anchor; i < x_anchor + tile_type.width; i++) { for (int j = y_anchor; j < y_anchor + tile_type.height; j++) { @@ -48,7 +44,6 @@ void set_tile_type_at_loc(const int x_anchor, const int y_anchor, } } - TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { // test device grid name std::string device_grid_name = "test"; @@ -70,7 +65,6 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { auto& logical_block_types = g_vpr_ctx.mutable_device().logical_block_types; logical_block_types.clear(); - t_physical_tile_type empty_tile; empty_tile.name = empty_tile_name; empty_tile.height = 1; @@ -87,7 +81,6 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { empty_tile.sub_tiles.back().index = 0; empty_tile.sub_tiles.back().equivalent_sites.push_back(&EMPTY_LOGICAL_BLOCK_TYPE); - // create an io physical tile and assign its parameters t_physical_tile_type io_tile; io_tile.name = io_tile_name; @@ -130,7 +123,6 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { tall_logical_type.equivalent_tiles.push_back(&tall_tile); logical_block_types.push_back(tall_logical_type); - tall_tile.sub_tiles.back().index = 0; tall_tile.sub_tiles.back().equivalent_sites.push_back(&tall_logical_type); @@ -148,7 +140,6 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { large_tile.sub_tiles.back().index = 0; large_tile.sub_tiles.back().equivalent_sites.push_back(&large_logical_type); - for (int x = 0; x < test_grid_width; x++) { for (int y = 0; y < test_grid_height; y++) { test_grid[0][x][y].type = &io_tile; @@ -330,6 +321,7 @@ TEST_CASE("test_compressed_grid", "[vpr_compressed_grid]") { REQUIRE(grid_loc == t_physical_tile_loc{98, 98, 0}); } + logical_block_types.clear(); } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_connection_router.cpp b/vpr/test/test_connection_router.cpp index a106ad80a80..138e003b04e 100644 --- a/vpr/test/test_connection_router.cpp +++ b/vpr/test/test_connection_router.cpp @@ -8,7 +8,8 @@ #include "globals.h" #include "net_delay.h" #include "place_and_route.h" -#include "timing_place_lookup.h" +#include "connection_router.h" +#include "router_delay_profiling.h" static constexpr const char kArchFile[] = "../../vtr_flow/arch/timing/k6_frac_N10_mem32K_40nm.xml"; static constexpr int kMaxHops = 10; @@ -44,7 +45,7 @@ static float do_one_route(RRNodeId source_node, cost_params.astar_offset = router_opts.astar_offset; cost_params.bend_cost = router_opts.bend_cost; - const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; + const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().netlist() : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist; route_budgets budgeting_inf(net_list, is_flat); RouterStats router_stats; @@ -142,19 +143,18 @@ TEST_CASE("connection_router", "[vpr]") { kArchFile, "wire.eblif", "--route_chan_width", "100"}; - vpr_init(sizeof(argv) / sizeof(argv[0]), argv, - &options, &vpr_setup, &arch); + vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); vpr_create_device_grid(vpr_setup, arch); vpr_setup_clock_networks(vpr_setup, arch); auto det_routing_arch = &vpr_setup.RoutingArch; auto& router_opts = vpr_setup.RouterOpts; - t_graph_type graph_directionality; + e_graph_type graph_directionality; if (router_opts.route_type == GLOBAL) { - graph_directionality = GRAPH_BIDIR; + graph_directionality = e_graph_type::BIDIR; } else { - graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? e_graph_type::BIDIR : e_graph_type::UNIDIR); } auto chan_width = init_chan(vpr_setup.RouterOpts.fixed_channel_width, arch.Chans, graph_directionality); @@ -188,8 +188,7 @@ TEST_CASE("connection_router", "[vpr]") { // Clean up free_routing_structs(); - vpr_free_all(arch, - vpr_setup); + vpr_free_all(arch, vpr_setup); } } // namespace diff --git a/vpr/test/test_edge_groups.cpp b/vpr/test/test_edge_groups.cpp index 80bfea5e133..e8b83741afa 100644 --- a/vpr/test/test_edge_groups.cpp +++ b/vpr/test/test_edge_groups.cpp @@ -19,12 +19,12 @@ TEST_CASE("edge_groups_create_sets", "[vpr]") { // Build chains from the given connected sets int max_node_id = 0; std::vector> edges; - for (auto set : connected_sets) { + for (const auto& set : connected_sets) { int last = *set.cbegin(); std::for_each(std::next(set.cbegin()), set.cend(), [&](int node) { - edges.push_back(std::make_pair(last, node)); + edges.emplace_back(last, node); last = node; max_node_id = std::max(max_node_id, node); }); @@ -36,7 +36,7 @@ TEST_CASE("edge_groups_create_sets", "[vpr]") { // Initialize nodes to [0, 1, ..., max_node_id] std::iota(nodes.begin(), nodes.end(), 0); - // Create a Mersenne Twister psuedo-random number generator with seed 1 + // Create a Mersenne Twister pseudo-random number generator with seed 1 std::mt19937 g(1); // Run the test many times, the PRNG will give differently shuffled inputs @@ -66,12 +66,12 @@ TEST_CASE("edge_groups_create_sets", "[vpr]") { t_non_configurable_rr_sets sets = groups.output_sets(); // Check for the expected sets - for (auto set : connected_sets) { + for (const auto& set : connected_sets) { std::set random_set; for (auto elem : set) { random_set.insert(RRNodeId(random_nodes[elem])); } - REQUIRE(sets.node_sets.find(random_set) != sets.node_sets.end()); + REQUIRE(std::find(sets.node_sets.begin(), sets.node_sets.end(), random_set) != sets.node_sets.end()); } } } diff --git a/vpr/test/test_flat_placement_types.cpp b/vpr/test/test_flat_placement_types.cpp new file mode 100644 index 00000000000..b8daaaf61ea --- /dev/null +++ b/vpr/test/test_flat_placement_types.cpp @@ -0,0 +1,49 @@ +/** + * @file + * @author Alex Singer + * @date March 2025 + * @brief Unit tests for flat placement types + */ + +#include +#include "catch2/catch_test_macros.hpp" +#include "flat_placement_types.h" + +namespace { + +TEST_CASE("test_t_flat_pl_loc", "[vpr_flat_pl_types]") { + SECTION("Test addition operator") { + t_flat_pl_loc loc1{1.0f, 2.0f, 3.0f}; + t_flat_pl_loc loc2{4.0f, 5.0f, 6.0f}; + + loc1 += loc2; + + REQUIRE(loc1.x == Catch::Approx(5.0f)); + REQUIRE(loc1.y == Catch::Approx(7.0f)); + REQUIRE(loc1.layer == Catch::Approx(9.0f)); + } + + SECTION("Test division operator") { + t_flat_pl_loc loc{10.0f, 20.0f, 30.0f}; + + loc /= 2.0f; + + REQUIRE(loc.x == Catch::Approx(5.0f)); + REQUIRE(loc.y == Catch::Approx(10.0f)); + REQUIRE(loc.layer == Catch::Approx(15.0f)); + } + + SECTION("Test addition and division operators combined") { + t_flat_pl_loc loc1{1.0f, 2.0f, 3.0f}; + t_flat_pl_loc loc2{4.0f, 5.0f, 6.0f}; + + loc1 += loc2; + loc1 /= 2.0f; + + REQUIRE(loc1.x == Catch::Approx(2.5f)); + REQUIRE(loc1.y == Catch::Approx(3.5f)); + REQUIRE(loc1.layer == Catch::Approx(4.5f)); + } +} + +} // namespace diff --git a/vpr/test/test_interchange_device.cpp b/vpr/test/test_interchange_device.cpp index 6ab763ec5d8..f344adace1b 100644 --- a/vpr/test/test_interchange_device.cpp +++ b/vpr/test/test_interchange_device.cpp @@ -96,7 +96,7 @@ TEST_CASE("read_interchange_luts", "[vpr]") { for (auto lut_bel : lut_element.lut_bels) { CHECK(lut_bels.find(lut_bel.name) != lut_bels.end()); REQUIRE(lut_bel.output_pin == std::string("O")); - for (const std::string &lut_pin : lut_bel.input_pins) + for (const std::string& lut_pin : lut_bel.input_pins) CHECK(lut_bel_pins.find(lut_pin) != lut_bel_pins.end()); } } diff --git a/vpr/test/test_interchange_netlist.cpp b/vpr/test/test_interchange_netlist.cpp index 2af1b33a96f..ac1fdfb15f9 100644 --- a/vpr/test/test_interchange_netlist.cpp +++ b/vpr/test/test_interchange_netlist.cpp @@ -27,7 +27,7 @@ TEST_CASE("read_interchange_netlist", "[vpr]") { /* Read blif file and sweep unused components */ auto& atom_ctx = g_vpr_ctx.mutable_atom(); - atom_ctx.nlist = read_and_process_circuit(e_circuit_format::FPGA_INTERCHANGE, vpr_setup, arch); + atom_ctx.mutable_netlist() = read_and_process_circuit(e_circuit_format::FPGA_INTERCHANGE, vpr_setup, arch); } } // namespace diff --git a/vpr/test/test_noc_place_utils.cpp b/vpr/test/test_noc_place_utils.cpp index 59e8ca70cf2..515608c1a19 100644 --- a/vpr/test/test_noc_place_utils.cpp +++ b/vpr/test/test_noc_place_utils.cpp @@ -172,7 +172,7 @@ TEST_CASE("test_initial_noc_placement", "[noc_place_utils]") { // route it routing_algorithm->route_flow((NocRouterId)source_hard_router_id, (NocRouterId)sink_hard_routed_id, - (NocTrafficFlowId) traffic_flow_number, + (NocTrafficFlowId)traffic_flow_number, traffic_flow_route, noc_ctx.noc_model); } diff --git a/vpr/test/test_noc_storage.cpp b/vpr/test/test_noc_storage.cpp index 0320fa130dc..225614a43a2 100644 --- a/vpr/test/test_noc_storage.cpp +++ b/vpr/test/test_noc_storage.cpp @@ -457,4 +457,4 @@ TEST_CASE("test_generate_router_key_from_grid_location", "[vpr_noc]") { } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_noc_traffic_flows.cpp b/vpr/test/test_noc_traffic_flows.cpp index 1afd37727e6..ea5806d3261 100644 --- a/vpr/test/test_noc_traffic_flows.cpp +++ b/vpr/test/test_noc_traffic_flows.cpp @@ -133,4 +133,4 @@ TEST_CASE("test_adding_traffic_flows", "[vpr_noc_traffic_flows]") { REQUIRE(traffic_flow_storage.get_traffic_flows_associated_to_router_block(invalid_block).empty()); } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_odd_even_routing.cpp b/vpr/test/test_odd_even_routing.cpp index c0cf9278bee..4f00b7d2663 100644 --- a/vpr/test/test_odd_even_routing.cpp +++ b/vpr/test/test_odd_even_routing.cpp @@ -38,7 +38,6 @@ void compare_routes(const std::vector& golden_path, } } - void check_turn_legality(const vtr::vector>& traffic_flow_routes, const NocStorage& noc_model, const TurnModelRouting& routing_algorithm) { @@ -229,7 +228,7 @@ TEST_CASE("test_route_flow", "[vpr_noc_odd_even_routing]") { SECTION("Test case where multiple traffic flows are routed, and routes are checked for turn legality and deadlock freedom.") { std::random_device device; std::mt19937 rand_num_gen(device()); - std::uniform_int_distribution dist(0, 99); + std::uniform_int_distribution dist(0, 99); NocTrafficFlows traffic_flow_storage; @@ -264,4 +263,4 @@ TEST_CASE("test_route_flow", "[vpr_noc_odd_even_routing]") { } } -} \ No newline at end of file +} // namespace diff --git a/vpr/test/test_post_verilog.cpp b/vpr/test/test_post_verilog.cpp index a8344fa79d4..ca1a250b7d2 100644 --- a/vpr/test/test_post_verilog.cpp +++ b/vpr/test/test_post_verilog.cpp @@ -1,7 +1,7 @@ #include "catch2/catch_test_macros.hpp" #include "vpr_api.h" -#include "timing_place_lookup.h" +#include "router_delay_profiling.h" #include #include diff --git a/vpr/test/test_read_rr_edge_override.txt b/vpr/test/test_read_rr_edge_override.txt new file mode 100644 index 00000000000..05cccc8cbb9 --- /dev/null +++ b/vpr/test/test_read_rr_edge_override.txt @@ -0,0 +1,9 @@ +# edge Tdel +12 5.9e-11 +1586 4.2e-11 +1111 7.1e-11 +1324 9.4e-11 +(645, 127) 7.3e-11 +(591, 347) 7.9e-11 +(544, 45) 8.3e-11 +(37 , 511) 9.5e-11 \ No newline at end of file diff --git a/vpr/test/test_read_xml_noc_traffic_flows_file.cpp b/vpr/test/test_read_xml_noc_traffic_flows_file.cpp index f16a5d9feff..17aedd6bad1 100644 --- a/vpr/test/test_read_xml_noc_traffic_flows_file.cpp +++ b/vpr/test/test_read_xml_noc_traffic_flows_file.cpp @@ -553,4 +553,4 @@ TEST_CASE("test_get_cluster_blocks_compatible_with_noc_router_tiles", "[vpr_noc_ free_clustered_netlist(); } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_server_convertutils.cpp b/vpr/test/test_server_convertutils.cpp index d3f64b81816..2006170de46 100644 --- a/vpr/test/test_server_convertutils.cpp +++ b/vpr/test/test_server_convertutils.cpp @@ -5,8 +5,7 @@ #include "convertutils.h" -TEST_CASE("test_server_convert_utils_to_int", "[vpr]") -{ +TEST_CASE("test_server_convert_utils_to_int", "[vpr]") { REQUIRE(std::optional{-2} == try_convert_to_int("-2")); REQUIRE(std::optional{0} == try_convert_to_int("0")); REQUIRE(std::optional{2} == try_convert_to_int("2")); @@ -18,4 +17,3 @@ TEST_CASE("test_server_convert_utils_to_int", "[vpr]") } #endif /* NO_SERVER */ - diff --git a/vpr/test/test_server_taskresolver.cpp b/vpr/test/test_server_taskresolver.cpp index eda8d5ae82f..20c6a865183 100644 --- a/vpr/test/test_server_taskresolver.cpp +++ b/vpr/test/test_server_taskresolver.cpp @@ -29,7 +29,7 @@ TEST_CASE("test_server_taskresolver_cmdSpamFilter", "[vpr]") { REQUIRE(finished.size() == 4); - for (const auto& task: finished) { + for (const auto& task : finished) { REQUIRE(task->is_finished()); REQUIRE(task->has_error()); REQUIRE(task->job_id() != 1); @@ -60,7 +60,7 @@ TEST_CASE("test_server_taskresolver_cmdOverrideFilter", "[vpr]") { REQUIRE(finished.size() == 2); - for (const server::TaskPtr& task: finished) { + for (const server::TaskPtr& task : finished) { REQUIRE(task->is_finished()); REQUIRE(task->has_error()); REQUIRE(task->job_id() != 3); @@ -112,4 +112,4 @@ TEST_CASE("test_server_taskresolver_cmdSpamAndOverrideOptions", "[vpr]") { REQUIRE(task1->options() == ""); } -#endif /* NO_SERVER */ \ No newline at end of file +#endif /* NO_SERVER */ diff --git a/vpr/test/test_server_telegrambuffer.cpp b/vpr/test/test_server_telegrambuffer.cpp index 6c5c793c3d2..1b20a3c312f 100644 --- a/vpr/test/test_server_telegrambuffer.cpp +++ b/vpr/test/test_server_telegrambuffer.cpp @@ -47,8 +47,7 @@ TEST_CASE("test_server_telegrambuffer_oneOpened", "[vpr]") { REQUIRE(std::string_view{buff.data()} == "111222"); } -TEST_CASE("test_server_telegrambuffer_notFilledTelegramButWithPrependedRubish", "[vpr]") -{ +TEST_CASE("test_server_telegrambuffer_notFilledTelegramButWithPrependedRubish", "[vpr]") { comm::TelegramBuffer tBuff; const comm::ByteArray rubbish{"#@!"}; @@ -65,8 +64,7 @@ TEST_CASE("test_server_telegrambuffer_notFilledTelegramButWithPrependedRubish", REQUIRE(msgHeader.buffer() == tBuff.data()); // the rubbish prefix fragment will be absent here } -TEST_CASE("test_server_telegrambuffer__oneFinishedOneOpened", "[vpr]") -{ +TEST_CASE("test_server_telegrambuffer__oneFinishedOneOpened", "[vpr]") { comm::TelegramBuffer tBuff; const comm::ByteArray msgBody1{"message1"}; @@ -80,7 +78,7 @@ TEST_CASE("test_server_telegrambuffer__oneFinishedOneOpened", "[vpr]") comm::ByteArray t2(msgHeader2.buffer()); t2.append(msgBody2); - t2.resize(t2.size()-2); // drop 2 last elements + t2.resize(t2.size() - 2); // drop 2 last elements tBuff.append(t1); tBuff.append(t2); @@ -94,8 +92,7 @@ TEST_CASE("test_server_telegrambuffer__oneFinishedOneOpened", "[vpr]") REQUIRE(t2 == tBuff.data()); } -TEST_CASE("test_server_telegrambuffer_twoFinished", "[vpr]") -{ +TEST_CASE("test_server_telegrambuffer_twoFinished", "[vpr]") { comm::TelegramBuffer tBuff; const comm::ByteArray msgBody1{"message1"}; @@ -123,8 +120,7 @@ TEST_CASE("test_server_telegrambuffer_twoFinished", "[vpr]") REQUIRE(comm::ByteArray{} == tBuff.data()); } -TEST_CASE("test_server_telegrambuffer_clear", "[vpr]") -{ +TEST_CASE("test_server_telegrambuffer_clear", "[vpr]") { comm::TelegramBuffer tBuff; const comm::ByteArray msgBody1{"message1"}; @@ -148,4 +144,4 @@ TEST_CASE("test_server_telegrambuffer_clear", "[vpr]") REQUIRE(comm::ByteArray{} == tBuff.data()); } -#endif /* NO_SERVER */ \ No newline at end of file +#endif /* NO_SERVER */ diff --git a/vpr/test/test_server_telegramoptions.cpp b/vpr/test/test_server_telegramoptions.cpp index d7b3160a0d1..e49b684bc72 100644 --- a/vpr/test/test_server_telegramoptions.cpp +++ b/vpr/test/test_server_telegramoptions.cpp @@ -27,4 +27,4 @@ TEST_CASE("test_server_telegramoptions_get_wrong_keys", "[vpr]") { REQUIRE(options.get_bool("_is_flat_routing", true) == true); } -#endif /* NO_SERVER */ \ No newline at end of file +#endif /* NO_SERVER */ diff --git a/vpr/test/test_server_telegramparser.cpp b/vpr/test/test_server_telegramparser.cpp index 0d7f0c2276c..a3ac0defa4e 100644 --- a/vpr/test/test_server_telegramparser.cpp +++ b/vpr/test/test_server_telegramparser.cpp @@ -5,8 +5,7 @@ #include "catch2/catch_test_macros.hpp" #include "catch2/matchers/catch_matchers_all.hpp" -TEST_CASE("test_server_telegram_parser_base", "[vpr]") -{ +TEST_CASE("test_server_telegram_parser_base", "[vpr]") { const std::string tdata{R"({"JOB_ID":"7","CMD":"2","OPTIONS":"type1:name1:value1;type2:name2:v a l u e 2;t3:n3:v3","DATA":"some_data...","STATUS":"1"})"}; REQUIRE(std::optional{7} == comm::TelegramParser::try_extract_field_job_id(tdata)); @@ -16,10 +15,9 @@ TEST_CASE("test_server_telegram_parser_base", "[vpr]") REQUIRE(std::optional{1} == comm::TelegramParser::try_extract_field_status(tdata)); } -TEST_CASE("test_server_telegram_parser_invalid_keys", "[vpr]") -{ +TEST_CASE("test_server_telegram_parser_invalid_keys", "[vpr]") { const std::string tBadData{R"({"_JOB_ID":"7","_CMD":"2","_OPTIONS":"type1:name1:value1;type2:name2:v a l u e 2;t3:n3:v3","_DATA":"some_data...","_STATUS":"1"})"}; - + REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_job_id(tBadData)); REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_cmd(tBadData)); REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_options(tBadData)); @@ -27,13 +25,12 @@ TEST_CASE("test_server_telegram_parser_invalid_keys", "[vpr]") REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_status(tBadData)); } -TEST_CASE("test_server_telegram_parser_invalid_types", "[vpr]") -{ +TEST_CASE("test_server_telegram_parser_invalid_types", "[vpr]") { const std::string tBadData{R"({"JOB_ID":"x","CMD":"y","STATUS":"z"})"}; - + REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_job_id(tBadData)); REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_cmd(tBadData)); REQUIRE(std::nullopt == comm::TelegramParser::try_extract_field_status(tBadData)); } -#endif /* NO_SERVER */ \ No newline at end of file +#endif /* NO_SERVER */ diff --git a/vpr/test/test_server_zlibutils.cpp b/vpr/test/test_server_zlibutils.cpp index c8978ab999f..4b5ecf76c30 100644 --- a/vpr/test/test_server_zlibutils.cpp +++ b/vpr/test/test_server_zlibutils.cpp @@ -5,8 +5,7 @@ #include "catch2/catch_test_macros.hpp" #include "catch2/matchers/catch_matchers_all.hpp" -TEST_CASE("test_server_zlib_utils", "[vpr]") -{ +TEST_CASE("test_server_zlib_utils", "[vpr]") { const std::string orig{"This string is going to be compressed now"}; std::optional compressedOpt = try_compress(orig); @@ -20,8 +19,3 @@ TEST_CASE("test_server_zlib_utils", "[vpr]") } #endif /* NO_SERVER */ - - - - - diff --git a/vpr/test/test_setup_noc.cpp b/vpr/test/test_setup_noc.cpp index d1c14c211a8..31dacd0b5d8 100644 --- a/vpr/test/test_setup_noc.cpp +++ b/vpr/test/test_setup_noc.cpp @@ -1249,4 +1249,4 @@ TEST_CASE("test_setup_noc", "[vpr_setup_noc]") { } } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index d96c0389a5d..c05d33e54f9 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -132,7 +132,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); vpr_setup.RouterOpts.read_rr_edge_metadata = true; - vpr_create_device(vpr_setup, arch, false); + vpr_create_device(vpr_setup, arch); const auto& device_ctx = g_vpr_ctx.device(); auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); @@ -195,7 +195,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); vpr_setup.RouterOpts.read_rr_edge_metadata = true; - vpr_create_device(vpr_setup, arch, false); + vpr_create_device(vpr_setup, arch); const auto& device_ctx = g_vpr_ctx.device(); @@ -232,4 +232,163 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { vpr_free_all(arch, vpr_setup); } +TEST_CASE("read_rr_edge_override", "[vpr]") { + + const std::string RR_GRAPH_NAME = "test_read_rr_edge_override"; + const std::string RR_EDGE_OVERRIDE_FILENAME = "test_read_rr_edge_override.txt"; + const std::array file_extensions{".xml", ".bin"}; + + // We test both xml and binary file formats + for (const std::string& file_extension : file_extensions) { + std::string rr_graph_filename = RR_GRAPH_NAME + file_extension; + std::string overridden_rr_graph_filename = RR_GRAPH_NAME + "_overridden" + file_extension; + + RRNodeId src_inode = RRNodeId::INVALID(); + RRNodeId sink_inode = RRNodeId::INVALID(); + short switch_id = -1; + + { // Generate an RR graph and write it out + t_vpr_setup vpr_setup; + t_arch arch; + t_options options; + const char* argv[] = { + "test_vpr", + kArchFile, + "wire.eblif", + "--route_chan_width", + "100"}; + vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_create_device(vpr_setup, arch); + + const auto& device_ctx = g_vpr_ctx.device(); + auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); + const auto& rr_graph = device_ctx.rr_graph; + bool echo_enabled = getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH_INDEXED_DATA); + const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); + + for (const RRNodeId inode : device_ctx.rr_graph.nodes()) { + if ((rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) && rr_graph.num_edges(inode) > 0) { + src_inode = inode; + break; + } + } + + REQUIRE(src_inode.is_valid()); + sink_inode = rr_graph.edge_sink_node(RRNodeId(src_inode), 0); + switch_id = rr_graph.edge_switch(RRNodeId(src_inode), 0); + + write_rr_graph(&mutable_device_ctx.rr_graph_builder, + &mutable_device_ctx.rr_graph, + device_ctx.physical_tile_types, + &mutable_device_ctx.rr_indexed_data, + &mutable_device_ctx.rr_rc_data, + device_ctx.grid, + device_ctx.arch_switch_inf, + device_ctx.arch, + &mutable_device_ctx.chan_width, + rr_graph_filename.c_str(), + echo_enabled, + echo_file_name, + false); + + vpr_free_all(arch, vpr_setup); + } + + REQUIRE(src_inode.is_valid()); + REQUIRE(sink_inode.is_valid()); + REQUIRE(switch_id != -1); + + { // Override edge attributes + t_vpr_setup vpr_setup; + t_arch arch; + t_options options; + const char* argv[] = { + "test_vpr", + kArchFile, + "wire.eblif", + "--route_chan_width", + "100", + "--read_rr_graph", + rr_graph_filename.c_str(), + "--read_rr_edge_override", + RR_EDGE_OVERRIDE_FILENAME.c_str()}; + + vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_create_device(vpr_setup, arch); + + const auto& device_ctx = g_vpr_ctx.device(); + auto& mutable_device_ctx = g_vpr_ctx.mutable_device(); + bool echo_enabled = getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH_INDEXED_DATA); + const char* echo_file_name = getEchoFileName(E_ECHO_RR_GRAPH_INDEXED_DATA); + + write_rr_graph(&mutable_device_ctx.rr_graph_builder, + &mutable_device_ctx.rr_graph, + device_ctx.physical_tile_types, + &mutable_device_ctx.rr_indexed_data, + &mutable_device_ctx.rr_rc_data, + device_ctx.grid, + device_ctx.arch_switch_inf, + device_ctx.arch, + &mutable_device_ctx.chan_width, + overridden_rr_graph_filename.c_str(), + echo_enabled, + echo_file_name, + false); + + vpr_free_all(arch, vpr_setup); + } + + { // Verify overridden values + t_vpr_setup vpr_setup; + t_arch arch; + t_options options; + const char* argv[] = { + "test_vpr", + kArchFile, + "wire.eblif", + "--route_chan_width", + "100", + "--read_rr_graph", + overridden_rr_graph_filename.c_str()}; + + vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_create_device(vpr_setup, arch); + + const auto& device_ctx = g_vpr_ctx.device(); + const auto& rr_graph = device_ctx.rr_graph; + + switch_id = rr_graph.edge_switch((RREdgeId)12); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 5.9e-11f); + + switch_id = rr_graph.edge_switch((RREdgeId)1586); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 4.2e-11f); + + switch_id = rr_graph.edge_switch((RREdgeId)1111); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 7.1e-11f); + + switch_id = rr_graph.edge_switch((RREdgeId)1324); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 9.4e-11f); + + RREdgeId edge_id; + edge_id = rr_graph.rr_nodes().edge_id((RRNodeId)645, (RRNodeId)127); + switch_id = rr_graph.edge_switch(edge_id); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 7.3e-11f); + + edge_id = rr_graph.rr_nodes().edge_id((RRNodeId)591, (RRNodeId)347); + switch_id = rr_graph.edge_switch(edge_id); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 7.9e-11f); + + edge_id = rr_graph.rr_nodes().edge_id((RRNodeId)544, (RRNodeId)45); + switch_id = rr_graph.edge_switch(edge_id); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 8.3e-11f); + + edge_id = rr_graph.rr_nodes().edge_id((RRNodeId)37, (RRNodeId)511); + switch_id = rr_graph.edge_switch(edge_id); + REQUIRE(rr_graph.rr_switch_inf((RRSwitchId)switch_id).Tdel == 9.5e-11f); + + vpr_free_all(arch, vpr_setup); + } + } +} + } // namespace diff --git a/vpr/test/test_vpr_constraints.cpp b/vpr/test/test_vpr_constraints.cpp index d0b95e081e6..9069cc2ba2f 100644 --- a/vpr/test/test_vpr_constraints.cpp +++ b/vpr/test/test_vpr_constraints.cpp @@ -14,18 +14,16 @@ * UserPlaceConstraints, Region, PartitionRegions, and Partition. */ -namespace Catch -{ -template -struct StringMaker> -{ - static std::string convert(vtr::Rect const &value) { +namespace Catch { +template +struct StringMaker> { + static std::string convert(vtr::Rect const& value) { std::ostringstream oss; oss << "Rectangle: (" << value.xmin() << ", " << value.ymin() << ") to (" << value.xmax() << ", " << value.ymax() << ")"; return oss.str(); } }; -} +} // namespace Catch //Test Region class accessors and mutators TEST_CASE("Region", "[vpr]") { @@ -42,7 +40,6 @@ TEST_CASE("Region", "[vpr]") { REQUIRE(r1.get_layer_range() == std::make_pair(10, 11)); REQUIRE(r1.get_sub_tile() == 12); - //checking that default constructor creates an empty rectangle (999, 999,-1,-1) Region def_region; bool is_def_empty = def_region.empty(); @@ -73,7 +70,6 @@ TEST_CASE("PartitionRegion", "[vpr]") { REQUIRE(pr_regions[0].get_sub_tile() == 3); REQUIRE(pr_regions[1].get_sub_tile() == 2); - REQUIRE(pr_regions[0].get_rect() == vtr::Rect(2, 3, 6, 7)); REQUIRE(pr_regions[0].get_layer_range() == std::make_pair(0, 0)); @@ -97,7 +93,6 @@ TEST_CASE("Partition", "[vpr]") { r2 = Region(10, 10, 25, 30, 1, 2); r2.set_sub_tile(0); - PartitionRegion part_reg; part_reg.add_to_part_region(r1); part_reg.add_to_part_region(r2); @@ -200,7 +195,6 @@ TEST_CASE("RegionIntersect", "[vpr]") { REQUIRE(int_reg_2_ml.get_rect() == vtr::Rect(6, 3, 8, 6)); REQUIRE(int_reg_2_ml.get_layer_range() == std::make_pair(0, 2)); - //Test no intersection (rectangles don't overlap, intersect region will be returned empty) const Region int_reg_3 = intersection(region1, region3); REQUIRE(int_reg_3.empty() == TRUE); @@ -209,7 +203,6 @@ TEST_CASE("RegionIntersect", "[vpr]") { const Region int_reg_3_ml = intersection(region1, region2_ml); REQUIRE(int_reg_3_ml.empty() == TRUE); - //Test no intersection (rectangles overlap but different subtiles are specified, intersect region will be returned empty) region1.set_sub_tile(5); region2.set_sub_tile(3); @@ -253,7 +246,6 @@ TEST_CASE("PartRegionIntersect", "[vpr]") { pr1.add_to_part_region(r2); pr2.add_to_part_region(r3); - PartitionRegion int_pr = intersection(pr1, pr2); const std::vector& regions = int_pr.get_regions(); @@ -279,7 +271,6 @@ TEST_CASE("PartRegionIntersectMultiLayer", "[vpr]") { pr1.add_to_part_region(r2); pr2.add_to_part_region(r3); - PartitionRegion int_pr = intersection(pr1, pr2); const std::vector& regions = int_pr.get_regions(); @@ -310,7 +301,7 @@ TEST_CASE("PartRegionIntersect2", "[vpr]") { const std::vector& regions = int_pr.get_regions(); REQUIRE(regions.size() == 1); - REQUIRE(regions[0].get_rect() == vtr::Rect (0, 0, 2, 2)); + REQUIRE(regions[0].get_rect() == vtr::Rect(0, 0, 2, 2)); REQUIRE(regions[0].get_layer_range() == std::make_pair(0, 0)); } @@ -334,7 +325,7 @@ TEST_CASE("PartRegionIntersect2Multilayer", "[vpr]") { const std::vector& regions = int_pr.get_regions(); REQUIRE(regions.size() == 1); - REQUIRE(regions[0].get_rect() == vtr::Rect (0, 0, 2, 2)); + REQUIRE(regions[0].get_rect() == vtr::Rect(0, 0, 2, 2)); REQUIRE(regions[0].get_layer_range() == std::make_pair(1, 1)); } @@ -424,13 +415,12 @@ TEST_CASE("PartRegionIntersect4", "[vpr]") { pr2.add_to_part_region(r3); pr2.add_to_part_region(r4); - PartitionRegion int_pr = intersection(pr1, pr2); const std::vector& regions = int_pr.get_regions(); REQUIRE(regions.size() == 1); REQUIRE(regions[0].get_layer_range() == std::make_pair(0, 0)); - REQUIRE(regions[0].get_rect() == vtr::Rect (1, 2, 3, 4)); + REQUIRE(regions[0].get_rect() == vtr::Rect(1, 2, 3, 4)); REQUIRE(regions[0].get_sub_tile() == 2); } @@ -458,13 +448,12 @@ TEST_CASE("PartRegionIntersect4MultiLayer", "[vpr]") { pr2.add_to_part_region(r3); pr2.add_to_part_region(r4); - PartitionRegion int_pr = intersection(pr1, pr2); const std::vector& regions = int_pr.get_regions(); REQUIRE(regions.size() == 1); REQUIRE(regions[0].get_layer_range() == std::make_pair(1, 1)); - REQUIRE(regions[0].get_rect() == vtr::Rect (1, 2, 3, 4)); + REQUIRE(regions[0].get_rect() == vtr::Rect(1, 2, 3, 4)); REQUIRE(regions[0].get_sub_tile() == 2); } diff --git a/vpr/test/test_xy_routing.cpp b/vpr/test/test_xy_routing.cpp index 8b79960c4c8..b96331cc83a 100644 --- a/vpr/test/test_xy_routing.cpp +++ b/vpr/test/test_xy_routing.cpp @@ -389,4 +389,4 @@ TEST_CASE("test_route_flow when it fails in a non mesh topology.", "[vpr_noc_xy_ REQUIRE_THROWS_WITH(routing_algorithm.route_flow(start_router_id, sink_router_id, traffic_flow_id, found_path, noc_model), "No route could be found from starting router with ID:'3' and the destination router with ID:'1' using the XY-Routing algorithm."); } -} // namespace \ No newline at end of file +} // namespace diff --git a/vpr/valgrind.supp b/vpr/valgrind.supp index fd7781cf70c..3dc4e6058d8 100644 --- a/vpr/valgrind.supp +++ b/vpr/valgrind.supp @@ -766,3 +766,803 @@ ... obj:*libgtk-3* } +#Parmys +{ + + Memcheck:Addr1 + fun:read_history_range + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:strdup + fun:_ZN5Yosys5RTLIL8IdString13get_referenceEPKc + fun:_ZN5Yosys5RTLIL8IdStringC1EPKc + fun:_ZN5Yosys5RTLIL8IdStringaSEPKc + fun:_ZN5Yosys11yosys_setupEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:realloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:realloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:_Znwm + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:realloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:realloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:calloc + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:realloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:realloc + obj:* + obj:* + obj:* + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateNamespace + fun:TclGetNamespaceForQualName + fun:Tcl_FindNamespace + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateObjCommand + fun:Tcl_NRCreateCommand + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateNamespace + fun:TclGetNamespaceForQualName + fun:Tcl_FindNamespace + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateObjCommand + fun:Tcl_NRCreateCommand + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_DictObjPut + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_DStringSetLength + fun:Tcl_ExternalToUtfDString + fun:TclSetupEnv + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_GetThreadData + fun:TclpGetPwUid + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateNamespace + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_NewStringObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_AppendLimitedToObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5Yosys20yosys_tcl_iterp_initEP10Tcl_Interp + fun:_ZN5Yosys20yosys_get_tcl_interpEv +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_AppendLimitedToObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5Yosys20yosys_tcl_iterp_initEP10Tcl_Interp + fun:_ZN5Yosys20yosys_get_tcl_interpEv +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5Yosys20yosys_tcl_iterp_initEP10Tcl_Interp +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_AppendLimitedToObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + fun:Tcl_Realloc + fun:Tcl_DStringAppend + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclSetByteCodeFromAny + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNREvalObjEx + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_NewStringObj + fun:TclCreateProc + fun:Tcl_ProcObjCmd + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5Yosys20yosys_tcl_iterp_initEP10Tcl_Interp + fun:_ZN5Yosys20yosys_get_tcl_interpEv +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + fun:Tcl_CreateObjCommand + fun:Tcl_NRCreateCommand + fun:Tcl_ProcObjCmd + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_EvalEx + fun:Tcl_Eval + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclSetByteCodeFromAny + fun:TclProcCompileProc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNRInterpProc + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:TclpRealloc + fun:Tcl_Realloc + fun:Tcl_DStringSetLength + fun:Tcl_ExternalToUtfDString + fun:TclSetupEnv + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + fun:TclpAlloc + fun:Tcl_Alloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_WriteObj + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx + fun:Tcl_EvalFile + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_NewObj + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: possible + fun:malloc + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_CreateInterp + fun:_ZN5Yosys20yosys_get_tcl_interpEv + fun:main +} +{ + + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:realloc + obj:* + obj:* + obj:* + obj:* + fun:_ZN5Yosys4Pass4callEPNS_5RTLIL6DesignESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISA_EE + fun:_ZN5YosysL13tcl_yosys_cmdEPvP10Tcl_InterpiPPKc + fun:TclInvokeStringCommand + fun:TclNRRunCallbacks + obj:/usr/lib/x86_64-linux-gnu/libtcl8.6.so + fun:Tcl_FSEvalFileEx +} +{ + + Memcheck:Cond + fun:read_history_range + fun:main +} +{ + + Memcheck:Cond + fun:read_history_range + fun:main +} diff --git a/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml b/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml index 8170d72b0e2..3a301bac3dd 100644 --- a/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml +++ b/vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml @@ -744,6 +744,49 @@ --> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/multi_die/stratixiv_3d/3d_SB_inter_die_stratixiv_arch.timing.xml b/vtr_flow/arch/multi_die/stratixiv_3d/3d_SB_inter_die_stratixiv_arch.timing.xml index d671996b6f4..d2dc23f5005 100644 --- a/vtr_flow/arch/multi_die/stratixiv_3d/3d_SB_inter_die_stratixiv_arch.timing.xml +++ b/vtr_flow/arch/multi_die/stratixiv_3d/3d_SB_inter_die_stratixiv_arch.timing.xml @@ -5026,7 +5026,7 @@ - + + + + - - - + - + 1 1 1 1 1 1 1 1 1 - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/README.md b/vtr_flow/benchmarks/system_verilog/f4pga/README.md index 1887a0a2681..2d3e481d3a4 100644 --- a/vtr_flow/benchmarks/system_verilog/f4pga/README.md +++ b/vtr_flow/benchmarks/system_verilog/f4pga/README.md @@ -4,4 +4,14 @@ This folder contains the `button_controller`, `pulse_width_led` and `timer` benc The benchmarks are directly copied to avoid dealing with a significant amount of code by adding the F4PGA repository as a subtree to the VTR repository. The primary purpose of these benchmarks is to utilize them in VTR GitHub CI tests to continuously monitor the functionality of the Yosys SystemVerilog and UHDM plugins. -For more information please see the ['ChipsAlliance/F4PGA'](https://github.com/chipsalliance/f4pga) Github repository. \ No newline at end of file +For more information please see the ['ChipsAlliance/F4PGA'](https://github.com/chipsalliance/f4pga) Github repository. + +## SystemVerilog File Flattening with `make_sv_flattened.py` + +The current SystemVerilog tool, **Synlig**, cannot process multiple files as input (e.g., a top module and its dependencies). To address this limitation, use the script `make_sv_flattened.py` to flatten the files into a single SystemVerilog file. This will convert any design with dependencies into one flattened SystemVerilog file, ensuring compatibility with Synlig. + +### Instructions: +1. Ensure the `make_sv_flattened.py` script is located in the folder where your SystemVerilog files (e.g., the top module and its dependencies) are gathered. +2. Run the `make_sv_flattened.py` script on the gathered files in that folder. +3. The script will output a single flattened SystemVerilog file, ready for use with Synlig. + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv new file mode 100644 index 00000000000..13883b1f424 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv @@ -0,0 +1,241 @@ +// Content from button_controller.sv +`timescale 1ns / 1ps `default_nettype none + +module top ( + input wire logic clk, + btnu, + btnc, + output logic [3:0] anode, + output logic [7:0] segment +); + + + logic sync; + logic syncToDebounce; + logic debounceToOneShot; + logic f1, f2; + logic f3, f4; + logic oneShotToCounter; + logic [7:0] counterToSevenSegment; + logic [7:0] counterToSevenSegment2; + logic oneShotToCounter2; + logic s0, s1; + debounce d0 ( + .clk(clk), + .reset(btnu), + .noisy(syncToDebounce), + .debounced(debounceToOneShot) + ); + + assign oneShotToCounter = f1 && ~f2; + + assign oneShotToCounter2 = f3 && ~f4; + + timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T0 ( + .clk(clk), + .reset(btnu), + .increment(oneShotToCounter), + .rolling_over(s0), + .count(counterToSevenSegment) + ); + + timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T1 ( + .clk(clk), + .reset(btnu), + .increment(oneShotToCounter2), + .rolling_over(s1), + .count(counterToSevenSegment2) + ); + + + display_control DC0 ( + .clk(clk), + .reset(btnu), + .dataIn({counterToSevenSegment2, counterToSevenSegment}), + .digitDisplay(4'b1111), + .digitPoint(4'b0000), + .anode(anode), + .segment(segment) + ); + + always_ff @(posedge clk) begin + + sync <= btnc; + syncToDebounce <= sync; + + f1 <= debounceToOneShot; + f2 <= f1; + + f3 <= syncToDebounce; + f4 <= f3; + end +endmodule + + +// Content from debounce.sv +`timescale 1ns / 1ps `default_nettype none + +module debounce ( + input wire logic clk, + reset, + noisy, + output logic debounced +); + + logic timerDone, clrTimer; + + typedef enum logic [1:0] { + s0, + s1, + s2, + s3, + ERR = 'X + } state_type_e; + state_type_e ns, cs; + + logic [18:0] tA; + + timer #(.MOD_VALUE(500000), .BIT_WIDTH(19)) T0 ( + .clk(clk), + .reset(clrTimer), + .increment(1'b1), + .rolling_over(timerDone), + .count(tA) + ); + + always_comb begin + ns = ERR; + clrTimer = 0; + debounced = 0; + + if (reset) ns = s0; + else + case (cs) + s0: begin + clrTimer = 1'b1; + if (noisy) ns = s1; + else ns = s0; + end + s1: + if (noisy && timerDone) ns = s2; + else if (noisy && ~timerDone) ns = s1; + else ns = s0; + s2: begin + debounced = 1'b1; + clrTimer = 1'b1; + if (noisy) ns = s2; + else ns = s3; + end + s3: begin + debounced = 1'b1; + if (~noisy && timerDone) ns = s0; + else if (~noisy && ~timerDone) ns = s3; + else ns = s2; + end + endcase + end + + always_ff @(posedge clk) cs <= ns; +endmodule + + +// Content from display_control.sv +`default_nettype none + +module display_control ( + input wire logic clk, + input wire logic reset, + input wire logic [15:0] dataIn, + input wire logic [ 3:0] digitDisplay, + input wire logic [ 3:0] digitPoint, + output logic [ 3:0] anode, + output logic [ 7:0] segment +); + + parameter integer COUNT_BITS = 17; + + logic [COUNT_BITS-1:0] count_val; + logic [ 1:0] anode_select; + logic [ 3:0] cur_anode; + logic [ 3:0] cur_data_in; + + always_ff @(posedge clk) begin + if (reset) count_val <= 0; + else count_val <= count_val + 1; + end + + assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + + assign cur_anode = + (anode_select == 2'b00) ? 4'b1110 : + (anode_select == 2'b01) ? 4'b1101 : + (anode_select == 2'b10) ? 4'b1011 : + 4'b0111; + + assign anode = cur_anode | (~digitDisplay); + + assign cur_data_in = + (anode_select == 2'b00) ? dataIn[3:0] : + (anode_select == 2'b01) ? dataIn[7:4] : + (anode_select == 2'b10) ? dataIn[11:8] : + dataIn[15:12] ; + + assign segment[7] = + (anode_select == 2'b00) ? ~digitPoint[0] : + (anode_select == 2'b01) ? ~digitPoint[1] : + (anode_select == 2'b10) ? ~digitPoint[2] : + ~digitPoint[3] ; + + assign segment[6:0] = + (cur_data_in == 0) ? 7'b1000000 : + (cur_data_in == 1) ? 7'b1111001 : + (cur_data_in == 2) ? 7'b0100100 : + (cur_data_in == 3) ? 7'b0110000 : + (cur_data_in == 4) ? 7'b0011001 : + (cur_data_in == 5) ? 7'b0010010 : + (cur_data_in == 6) ? 7'b0000010 : + (cur_data_in == 7) ? 7'b1111000 : + (cur_data_in == 8) ? 7'b0000000 : + (cur_data_in == 9) ? 7'b0010000 : + (cur_data_in == 10) ? 7'b0001000 : + (cur_data_in == 11) ? 7'b0000011 : + (cur_data_in == 12) ? 7'b1000110 : + (cur_data_in == 13) ? 7'b0100001 : + (cur_data_in == 14) ? 7'b0000110 : + 7'b0001110; + + +endmodule + + +// Content from timer.sv +`timescale 1ns / 1ps `default_nettype none + +module timer #( + parameter MOD_VALUE = 1, + parameter BIT_WIDTH = 1 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [BIT_WIDTH-1:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 0; + else if (increment) begin + if (rolling_over) count <= 0; + else count <= count + 1'b1; + end + + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/make_sv_flattened.py b/vtr_flow/benchmarks/system_verilog/f4pga/make_sv_flattened.py new file mode 100644 index 00000000000..930d5fb40a6 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/make_sv_flattened.py @@ -0,0 +1,71 @@ +""" +Module for flattening the SV design files. +""" + +import os +import re + + +def find_verilog_files(): + """Find all Verilog (.sv, .v) files in the current directory.""" + return [f for f in os.listdir(".") if f.endswith((".sv", ".v"))] + + +def identify_top_module(file_list): + """Identify the file containing the top module definition.""" + top_module_regex = re.compile(r"module\s+top\s*\(") + for file in file_list: + with open(file, "r") as f: + for line in f: + if top_module_regex.search(line): + return file + return None + + +def create_flattened_file(top_file, file_list): + """Create a flattened Verilog file with all file contents.""" + current_dir = os.path.basename(os.getcwd()) + output_file_name = f"flattened_{current_dir}.sv" + + with open(output_file_name, "w") as output_file: + if top_file: + # Write the top module first + with open(top_file, "r") as top_module: + output_file.write(f"// Content from {top_file}\n") + output_file.write(top_module.read()) + output_file.write("\n\n") + + # Write the rest of the files + for file in file_list: + if file != top_file: + with open(file, "r") as verilog_file: + output_file.write(f"// Content from {file}\n") + output_file.write(verilog_file.read()) + output_file.write("\n\n") + + print(f"Flattened file created: {output_file_name}") + + +def main(): + """Main function to generate the flattened Verilog file.""" + print("Searching for Verilog files...") + verilog_files = find_verilog_files() + + if not verilog_files: + print("No Verilog files found in the current directory.") + return + + print("Identifying the top module...") + top_file = identify_top_module(verilog_files) + + if top_file: + print(f"Top module found in: {top_file}") + else: + print("No top module found. Files will be combined in arbitrary order.") + + print("Creating flattened file...") + create_flattened_file(top_file, verilog_files) + + +if __name__ == "__main__": + main() diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv new file mode 100644 index 00000000000..74e32cc07fe --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv @@ -0,0 +1,52 @@ +// Content from pulse_led.v +module top ( + input wire clk, + input wire [3:0] sw, + input wire [3:0] btn, + output wire pulse_red, + pulse_blue, + pulse_green +); + wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG; + + assign pulse_wideR = {1'b0, sw[3:1], 10'd0}; + assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0}; + assign pulse_wideB = {btn[1:0], 11'd0}; + + PWM R0 ( + .clk (clk), + .pulse(pulse_red), + .width(pulse_wideR) + ); + PWM B0 ( + .clk (clk), + .pulse(pulse_green), + .width(pulse_wideB) + ); + PWM G0 ( + .clk (clk), + .pulse(pulse_blue), + .width(pulse_wideG) + ); + + +endmodule + + +// Content from PWM.v +module PWM ( + input wire clk, + input wire [13:0] width, + output reg pulse +); + + reg [13:0] counter = 0; + + always @(posedge clk) begin + counter <= counter + 1; + if (counter < width) pulse <= 1'b1; + else pulse <= 1'b0; + end +endmodule + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv b/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv new file mode 100644 index 00000000000..5891e940a15 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv @@ -0,0 +1,230 @@ +// Content from clock.sv +`timescale 1ns / 1ps `default_nettype none + +module top ( + input wire logic clk, + btnc, + sw, + output logic [3:0] anode, + output logic [7:0] segment +); + + logic [15:0] digitData; + + timer TC0 ( + .clk(clk), + .reset(btnc), + .run(sw), + .digit0(digitData[3:0]), + .digit1(digitData[7:4]), + .digit2(digitData[11:8]), + .digit3(digitData[15:12]) + ); + display_control SSC0 ( + .clk(clk), + .reset(btnc), + .dataIn(digitData), + .digitDisplay(4'b1111), + .digitPoint(4'b0100), + .anode(anode), + .segment(segment) + ); +endmodule + + +// Content from modify_count.sv +`default_nettype none + +module modify_count #( + parameter MOD_VALUE = 10 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [3:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 4'b0000; + else if (increment) begin + if (rolling_over) count <= 4'b0000; + else count <= count + 4'b0001; + end + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + +// Content from display_control.sv +`default_nettype none + + +module display_control ( + input wire logic clk, + input wire logic reset, + input wire logic [15:0] dataIn, + input wire logic [ 3:0] digitDisplay, + input wire logic [ 3:0] digitPoint, + output logic [ 3:0] anode, + output logic [ 7:0] segment +); + + parameter integer COUNT_BITS = 17; + + logic [COUNT_BITS-1:0] count_val; + logic [ 1:0] anode_select; + logic [ 3:0] cur_anode; + logic [ 3:0] cur_data_in; + + + always_ff @(posedge clk) begin + if (reset) count_val <= 0; + else count_val <= count_val + 1; + end + + assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + + assign cur_anode = + (anode_select == 2'b00) ? 4'b1110 : + (anode_select == 2'b01) ? 4'b1101 : + (anode_select == 2'b10) ? 4'b1011 : + 4'b0111; + + assign anode = cur_anode | (~digitDisplay); + + assign cur_data_in = + (anode_select == 2'b00) ? dataIn[3:0] : + (anode_select == 2'b01) ? dataIn[7:4] : + (anode_select == 2'b10) ? dataIn[11:8] : + dataIn[15:12] ; + + assign segment[7] = + (anode_select == 2'b00) ? ~digitPoint[0] : + (anode_select == 2'b01) ? ~digitPoint[1] : + (anode_select == 2'b10) ? ~digitPoint[2] : + ~digitPoint[3] ; + + assign segment[6:0] = + (cur_data_in == 0) ? 7'b1000000 : + (cur_data_in == 1) ? 7'b1111001 : + (cur_data_in == 2) ? 7'b0100100 : + (cur_data_in == 3) ? 7'b0110000 : + (cur_data_in == 4) ? 7'b0011001 : + (cur_data_in == 5) ? 7'b0010010 : + (cur_data_in == 6) ? 7'b0000010 : + (cur_data_in == 7) ? 7'b1111000 : + (cur_data_in == 8) ? 7'b0000000 : + (cur_data_in == 9) ? 7'b0010000 : + (cur_data_in == 10) ? 7'b0001000 : + (cur_data_in == 11) ? 7'b0000011 : + (cur_data_in == 12) ? 7'b1000110 : + (cur_data_in == 13) ? 7'b0100001 : + (cur_data_in == 14) ? 7'b0000110 : + 7'b0001110; + + +endmodule + + +// Content from timer.sv +`timescale 1ns / 1ps `default_nettype none + +module timer ( + input wire logic clk, + reset, + run, + output logic [3:0] digit0, + digit1, + digit2, + digit3 +); + + logic inc0, inc1, inc2, inc3, inc4; + + logic [23:0] timerCount; + + modify_count #( + .MOD_VALUE(10) + ) M0 ( + .clk(clk), + .reset(reset), + .increment(inc0), + .rolling_over(inc1), + .count(digit0) + ); + modify_count #( + .MOD_VALUE(10) + ) M1 ( + .clk(clk), + .reset(reset), + .increment(inc1), + .rolling_over(inc2), + .count(digit1) + ); + modify_count #( + .MOD_VALUE(10) + ) M2 ( + .clk(clk), + .reset(reset), + .increment(inc2), + .rolling_over(inc3), + .count(digit2) + ); + modify_count #( + .MOD_VALUE(6) + ) M3 ( + .clk(clk), + .reset(reset), + .increment(inc3), + .rolling_over(inc4), + .count(digit3) + ); + + time_counter #( + .MOD_VALUE(1000000) + ) T0 ( + .clk(clk), + .reset(reset), + .increment(run), + .rolling_over(inc0), + .count(timerCount) + ); +endmodule + + +// Content from time_counter.sv +`timescale 1ns / 1ps `default_nettype none + +module time_counter #( + parameter MOD_VALUE = 1000000 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [23:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 0; + else if (increment) begin + if (rolling_over) count <= 0; + else count <= count + 1'b1; + end + + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 5015d587055..24bae6877cc 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -7,7 +7,15 @@ read_verilog -nomem2reg +/parmys/vtr_primitives.v setattr -mod -set keep_hierarchy 1 single_port_ram setattr -mod -set keep_hierarchy 1 dual_port_ram -puts "Using parmys as partial mapper" +# synlig path error handling +if {[catch {set synlig $::env(synlig_exe_path)} err]} { + puts "Error: $err" + puts "synlig_exe_path is not set" +} else { + set synlig $::env(synlig_exe_path) + puts "Using parmys as partial mapper" +} + # arch file: QQQ # input files: [XXX] @@ -18,15 +26,14 @@ puts "Using parmys as partial mapper" parmys_arch -a QQQ if {$env(PARSER) == "surelog" } { - puts "Using Yosys read_uhdm command" - plugin -i systemverilog - yosys -import - read_uhdm XXX + puts "Using Synlig read_uhdm command" + + exec $synlig -p "read_uhdm XXX" + } elseif {$env(PARSER) == "system-verilog" } { - puts "Using Yosys read_systemverilog command" - plugin -i systemverilog - yosys -import - read_systemverilog XXX + puts "Using Synlig read_systemverilog " + exec $synlig -p "read_systemverilog XXX" + } elseif {$env(PARSER) == "default" } { puts "Using Yosys read_verilog command" read_verilog -sv -nolatches XXX @@ -66,7 +73,14 @@ techmap -map +/parmys/aldffe2dff.v opt -full -parmys -a QQQ -nopass -c CCC YYY +# Separate options for Parmys execution (Verilog or SystemVerilog) +if {$env(PARSER) == "default"} { + # For Verilog, use -nopass for a simpler, faster flow + parmys -a QQQ -nopass -c CCC YYY +} elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} { + # For Synlig SystemVerilog, run additional passes to handle complexity + parmys -a QQQ -c CCC YYY +} opt -full @@ -75,11 +89,10 @@ opt -fast dffunmap opt -fast -noff - #autoname stat hierarchy -check -auto-top -purge_lib -write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ +write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ \ No newline at end of file diff --git a/vtr_flow/parse/parse_config/common/vpr.place.txt b/vtr_flow/parse/parse_config/common/vpr.place.txt index 64da113842b..865a7d2159a 100644 --- a/vtr_flow/parse/parse_config/common/vpr.place.txt +++ b/vtr_flow/parse/parse_config/common/vpr.place.txt @@ -1,4 +1,5 @@ #VPR Place Metrics +initial_placed_wirelength_est;vpr.out;Initial placement BB estimate of wirelength:\s*(\d+) placed_wirelength_est;vpr.out;BB estimate of min-dist \(placement\) wire length: (\d+) #VPR Number of heap operations diff --git a/vtr_flow/parse/parse_config/timing/vpr.place.txt b/vtr_flow/parse/parse_config/timing/vpr.place.txt index ba0dc8a9307..42d3c904cd0 100644 --- a/vtr_flow/parse/parse_config/timing/vpr.place.txt +++ b/vtr_flow/parse/parse_config/timing/vpr.place.txt @@ -1,6 +1,7 @@ %include "../common/vpr.place.txt" #VPR Place Timing Metrics +initial_placed_CPD_est;vpr.out;Initial placement estimated Critical Path Delay \(CPD\): (.*) ns placed_CPD_est;vpr.out;Placement estimated critical path delay \(least slack\): (.*) ns placed_setup_TNS_est;vpr.out;Placement estimated setup Total Negative Slack \(sTNS\): (.*) ns placed_setup_WNS_est;vpr.out;Placement estimated setup Worst Negative Slack \(sWNS\): (.*) ns diff --git a/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt b/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt index a78ab6d191c..db69ba91d66 100644 --- a/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt +++ b/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt @@ -2,14 +2,25 @@ # channel width. vpr_status;output.txt;vpr_status=(.*) -total_wirelength;vpr.out;\s*Total wirelength: (\d+) -# Final critical path delay (least slack): 6.34202 ns, Fmax: 157.678 MHz crit_path_delay;vpr.out;Critical path: (.*) ns +post_gp_hpwl;vpr.out;\s*Placement HPWL: (.*) +post_fl_hpwl;vpr.out;Initial placement BB estimate of wirelength: (.*) +post_dp_hpwl;vpr.out;BB estimate of min-dist \(placement\) wire length: (.*) +total_wirelength;vpr.out;\s*Total wirelength: (\d+) +post_gp_overfilled_bins;vpr.out;\s*Number of overfilled bins: (\d+) +post_gp_avg_overfill;vpr.out;\s*Average overfill magnitude: (.*) +post_gp_num_misplaced_blocks;vpr.out;\s*Number of blocks in an incompatible bin: (\d+) +post_fl_cluster_err;vpr.out;\s*Percent of clusters with reconstruction errors: (.*) +post_fl_atom_err;vpr.out;\s*Percent of atoms misplaced from the flat placement: (.*) +post_fl_total_disp;vpr.out;\s*Total displacement of initial placement from flat placement: (.*) +post_fl_avg_disp;vpr.out;\s*Average atom displacement of initial placement from flat placement: (.*) +post_fl_max_disp;vpr.out;\s*Max atom displacement of initial placement from flat placement: (.*) ap_runtime;vpr.out;Analytical Placement took (.*) seconds -pack_runtime;vpr.out;Packing took (.*) seconds -# TODO: Figure out how to match Placement and not Analytical Placement better. -place_runtime;vpr.out;^(?!.*\bAnalytical\b).*Placement took (.*) seconds +ap_gp_runtime;vpr.out;AP Global Placer took (.*) seconds +ap_fl_runtime;vpr.out;AP Full Legalizer took (.*) seconds +ap_dp_runtime;vpr.out;AP Detailed Placer took (.*) seconds route_runtime;vpr.out;Routing took (.*) seconds total_runtime;vpr.out;The entire flow of VPR took (.*) seconds num_clb;vpr.out;Netlist clb blocks:\s*(\d+) +num_lab;vpr.out;Netlist LAB blocks:\s*(\d+) diff --git a/vtr_flow/scripts/arch_gen/arch_gen.py b/vtr_flow/scripts/arch_gen/arch_gen.py index 2039bf26e06..ef68cde7af5 100755 --- a/vtr_flow/scripts/arch_gen/arch_gen.py +++ b/vtr_flow/scripts/arch_gen/arch_gen.py @@ -172,7 +172,7 @@ def xLUT(LUT_size, num_LUT): def xCLB(k_LUT, N_BLE, I_CLB, I_BLE, fracture_level, num_FF, crossbar_str): - O_LUT = 2 ** fracture_level + O_LUT = 2**fracture_level O_soft = O_LUT O_ble = O_soft O_CLB = N_BLE * O_ble @@ -430,7 +430,7 @@ def xCLB(k_LUT, N_BLE, I_CLB, I_BLE, fracture_level, num_FF, crossbar_str): else: special_stage = False - num_LUT = 2 ** frac_stage + num_LUT = 2**frac_stage LUT_size = k_LUT - frac_stage idx = "[" + str(LUT_size - 1) + ":0]" diff --git a/vtr_flow/scripts/benchtracker/flask_cors/six.py b/vtr_flow/scripts/benchtracker/flask_cors/six.py index c06164c97d0..80c9e7e618d 100644 --- a/vtr_flow/scripts/benchtracker/flask_cors/six.py +++ b/vtr_flow/scripts/benchtracker/flask_cors/six.py @@ -687,7 +687,6 @@ def reraise(tp, value, tb=None): raise value.with_traceback(tb) raise value - else: def exec_(_code_, _globs_=None, _locs_=None): @@ -809,13 +808,13 @@ def wrapper(f): return wrapper - else: wraps = functools.wraps def with_metaclass(meta, *bases): """Create a base class with a metaclass.""" + # This requires a bit of explanation: the basic idea is to make a dummy # metaclass for one level of class instantiation that replaces itself with # the actual metaclass. diff --git a/vtr_flow/scripts/benchtracker/populate_db.py b/vtr_flow/scripts/benchtracker/populate_db.py index 39c898bde1e..358ef190fd7 100755 --- a/vtr_flow/scripts/benchtracker/populate_db.py +++ b/vtr_flow/scripts/benchtracker/populate_db.py @@ -25,6 +25,7 @@ nullval = "-1" type_map = {int: "INT", float: "REAL", str: "TEXT"} + # main program sequence def main(): params = Params() @@ -59,6 +60,7 @@ def update_db(params, db): # check if table for task exists; if not then create it task_table_name = params.task_table_name create_table(params, db, task_table_name) + # load up latest run and parsed date for task def check_last_runs_table(runs): natural_sort(runs) diff --git a/vtr_flow/scripts/blif_splicer.py b/vtr_flow/scripts/blif_splicer.py index dcfb71fc7d1..08058163f65 100755 --- a/vtr_flow/scripts/blif_splicer.py +++ b/vtr_flow/scripts/blif_splicer.py @@ -88,9 +88,11 @@ # and is not 're') with the name of the circuit. sections[sectionNumber] += " ".join( - name + "_" + word - if word != "re" and any(char not in nonNetChars for char in word) - else word + ( + name + "_" + word + if word != "re" and any(char not in nonNetChars for char in word) + else word + ) for word in line.split(" ") ) diff --git a/vtr_flow/scripts/download_noc_mlp.py b/vtr_flow/scripts/download_noc_mlp.py index c483da753df..c541c91c021 100755 --- a/vtr_flow/scripts/download_noc_mlp.py +++ b/vtr_flow/scripts/download_noc_mlp.py @@ -17,6 +17,7 @@ import shutil import errno + class ExtractionError(Exception): """ Raised when extracting the downlaoded file fails @@ -39,8 +40,9 @@ def parse_args(): does nothing (unless --force is specified). """ ) - parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter, - description=description) + parser = argparse.ArgumentParser( + formatter_class=argparse.ArgumentDefaultsHelpFormatter, description=description + ) parser.add_argument( "--vtr_flow_dir", @@ -132,7 +134,7 @@ def extract_to_vtr_flow_dir(args, tar_gz_filename): raise ExtractionError("{} should be a directory".format(directory)) # Create a temporary working directory - tmpdir = tempfile.mkdtemp(suffix="download_NoC_MLP", dir= os.path.abspath(".")) + tmpdir = tempfile.mkdtemp(suffix="download_NoC_MLP", dir=os.path.abspath(".")) try: # Extract the contents of the .tar.gz archive directly into the destination directory with tarfile.open(tar_gz_filename, "r:gz") as tar: diff --git a/vtr_flow/scripts/download_titan.py b/vtr_flow/scripts/download_titan.py index cf025dc38ab..483ba5c04d0 100755 --- a/vtr_flow/scripts/download_titan.py +++ b/vtr_flow/scripts/download_titan.py @@ -41,8 +41,9 @@ def parse_args(): does nothing (unless --force is specified). """ ) - parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter, - description=description) + parser = argparse.ArgumentParser( + formatter_class=argparse.ArgumentDefaultsHelpFormatter, description=description + ) parser.add_argument( "--titan_version", default="2.0.0", help="Titan release version to download" diff --git a/vtr_flow/scripts/python_libs/vtr/__init__.py b/vtr_flow/scripts/python_libs/vtr/__init__.py index 6a0b38d7639..9237e03be89 100644 --- a/vtr_flow/scripts/python_libs/vtr/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/__init__.py @@ -1,6 +1,7 @@ """ __init__ for the VTR python module """ + from .util import ( load_config_lines, CommandRunner, @@ -14,12 +15,12 @@ argparse_use_previous, argparse_str2bool, get_existing_run_dir, - get_latest_run_dir, - get_latest_run_number, + get_active_run_dir, get_next_run_dir, verify_file, pretty_print_table, find_task_dir, + RunDir, ) from .log_parse import ( determine_lut_size, diff --git a/vtr_flow/scripts/python_libs/vtr/abc/__init__.py b/vtr_flow/scripts/python_libs/vtr/abc/__init__.py index 26d376b3420..cdb3a62e69d 100644 --- a/vtr_flow/scripts/python_libs/vtr/abc/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/abc/__init__.py @@ -1,4 +1,5 @@ """ __init__ for abc module """ + from .abc import run, run_lec diff --git a/vtr_flow/scripts/python_libs/vtr/abc/abc.py b/vtr_flow/scripts/python_libs/vtr/abc/abc.py index 0ec3ca5ccef..a49de129d69 100644 --- a/vtr_flow/scripts/python_libs/vtr/abc/abc.py +++ b/vtr_flow/scripts/python_libs/vtr/abc/abc.py @@ -1,6 +1,7 @@ """ Module to run ABC with its various options """ + import shutil from collections import OrderedDict from pathlib import Path @@ -8,6 +9,7 @@ from vtr import paths from vtr.error import InspectError + # pylint: disable=too-many-arguments, too-many-locals def run( architecture_file, @@ -186,24 +188,26 @@ def run( ] ) if abc_script is None - else "; ".join( - [ - "read {pre_abc_blif}".format(pre_abc_blif=pre_abc_blif.name), - "time", - "resyn", - "resyn2", - "if -K {lut_size}".format(lut_size=lut_size), - "time", - "scleanup", - "write_hie {pre_abc_blif} {post_abc_raw_blif}".format( - pre_abc_blif=pre_abc_blif.name, - post_abc_raw_blif=post_abc_raw_blif.name, - ), - "print_stats", - ] + else ( + "; ".join( + [ + "read {pre_abc_blif}".format(pre_abc_blif=pre_abc_blif.name), + "time", + "resyn", + "resyn2", + "if -K {lut_size}".format(lut_size=lut_size), + "time", + "scleanup", + "write_hie {pre_abc_blif} {post_abc_raw_blif}".format( + pre_abc_blif=pre_abc_blif.name, + post_abc_raw_blif=post_abc_raw_blif.name, + ), + "print_stats", + ] + ) + if use_old_abc_script + else abc_script ) - if use_old_abc_script - else abc_script ) cmd = [abc_exec, "-c", abc_script] diff --git a/vtr_flow/scripts/python_libs/vtr/ace/__init__.py b/vtr_flow/scripts/python_libs/vtr/ace/__init__.py index 9666f7710ac..50682d93b35 100644 --- a/vtr_flow/scripts/python_libs/vtr/ace/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/ace/__init__.py @@ -1,4 +1,5 @@ """ init for the ACE module """ + from .ace import run diff --git a/vtr_flow/scripts/python_libs/vtr/ace/ace.py b/vtr_flow/scripts/python_libs/vtr/ace/ace.py index 7c5a274dc7e..a2e6af00fd5 100644 --- a/vtr_flow/scripts/python_libs/vtr/ace/ace.py +++ b/vtr_flow/scripts/python_libs/vtr/ace/ace.py @@ -1,9 +1,11 @@ """ Module to run ACE with its various options """ + from pathlib import Path from vtr import verify_file, CommandRunner, paths + # pylint: disable=too-many-arguments def run( circuit_file, diff --git a/vtr_flow/scripts/python_libs/vtr/flow.py b/vtr_flow/scripts/python_libs/vtr/flow.py index a1f14e2816e..fa0798fcd25 100644 --- a/vtr_flow/scripts/python_libs/vtr/flow.py +++ b/vtr_flow/scripts/python_libs/vtr/flow.py @@ -1,6 +1,7 @@ """ Module to run the VTR flow. This module calls other modules that then access the tools like VPR. """ + import shutil from pathlib import Path from collections import OrderedDict @@ -258,9 +259,9 @@ def run( if should_run_stage(VtrStage.ACE, start_stage, end_stage): vtr.ace.run( next_stage_netlist, - old_netlist=post_odin_netlist - if start_stage == VtrStage.ODIN - else post_yosys_netlist, + old_netlist=( + post_odin_netlist if start_stage == VtrStage.ODIN else post_yosys_netlist + ), output_netlist=post_ace_netlist, output_activity_file=post_ace_activity_file, command_runner=command_runner, @@ -297,8 +298,6 @@ def run( if ( "write_rr_graph" in vpr_args - or "analysis" in vpr_args - or "route" in vpr_args or "write_router_lookahead" in vpr_args or "write_intra_cluster_router_lookahead" in vpr_args ): @@ -399,8 +398,9 @@ def delete_intermediate_files( delete intermediate files """ next_stage_netlist.unlink() - exts = (".xml", ".sdf", ".v") - exts += (".net", ".place", ".route") if not keep_result_files else None + exts = (".xml", ".sdf", ".v", ".sv") + if not keep_result_files: + exts += (".net", ".place", ".route") for file in temp_dir.iterdir(): if file.suffix in exts: diff --git a/vtr_flow/scripts/python_libs/vtr/log_parse.py b/vtr_flow/scripts/python_libs/vtr/log_parse.py index 623c4545e22..69e8d72e7d7 100644 --- a/vtr_flow/scripts/python_libs/vtr/log_parse.py +++ b/vtr_flow/scripts/python_libs/vtr/log_parse.py @@ -1,6 +1,7 @@ """ module that contains functions to inspect various files to determine important values """ + import re from collections import OrderedDict from pathlib import Path @@ -25,7 +26,7 @@ def __init__(self, name, filename, regex_str, default_value=None): self._filename = filename # Look for the specified pattern somewhere in the line, but any characters # can occur before and after it. Detailed in GitHub Issue #2743. - self._regex = re.compile(f'^.*{regex_str}.*$') + self._regex = re.compile(f"^.*{regex_str}.*$") self._default_value = default_value def name(self): diff --git a/vtr_flow/scripts/python_libs/vtr/odin/__init__.py b/vtr_flow/scripts/python_libs/vtr/odin/__init__.py index b55d5c160cd..f1006248346 100644 --- a/vtr_flow/scripts/python_libs/vtr/odin/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/odin/__init__.py @@ -1,4 +1,5 @@ """ init for the ODIN module """ + from .odin import run diff --git a/vtr_flow/scripts/python_libs/vtr/odin/odin.py b/vtr_flow/scripts/python_libs/vtr/odin/odin.py index c4346d115b8..846b743b814 100644 --- a/vtr_flow/scripts/python_libs/vtr/odin/odin.py +++ b/vtr_flow/scripts/python_libs/vtr/odin/odin.py @@ -1,6 +1,7 @@ """ Module to run ODIN II with its various arguments """ + import os import shutil from collections import OrderedDict diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/__init__.py b/vtr_flow/scripts/python_libs/vtr/parmys/__init__.py index 581b8681c71..a8a520b91ed 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/__init__.py @@ -1,5 +1,6 @@ """ init for the YOSYS module """ + from .parmys import run from .parmys import YOSYS_PARSERS diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index cef45626828..c067ee7e7cf 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -1,6 +1,7 @@ """ Module to run Parmys with its various arguments """ + import os import shutil from collections import OrderedDict @@ -232,6 +233,13 @@ def run( odin_config_full_path, ) + # Set the synlig exe script path in the environment variable + # (handle if it is not set or system-verilog OFF) + try: + os.environ["synlig_exe_path"] = str(vtr.paths.synlig_exe_path) + except KeyError: + os.environ["synlig_exe_path"] = "/dummy/path" + # set the parser if parmys_args["parser"] in YOSYS_PARSERS: os.environ["PARSER"] = parmys_args["parser"] diff --git a/vtr_flow/scripts/python_libs/vtr/parse_vtr_flow.py b/vtr_flow/scripts/python_libs/vtr/parse_vtr_flow.py index d500eca0643..e238f2d9bb8 100755 --- a/vtr_flow/scripts/python_libs/vtr/parse_vtr_flow.py +++ b/vtr_flow/scripts/python_libs/vtr/parse_vtr_flow.py @@ -16,7 +16,6 @@ def parse_file_and_update_results(filename, patterns, results): - """ Find filename, and then look through for the matching patterns, updating results """ diff --git a/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py b/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py index d2aac387bcc..0eff7bbb75c 100755 --- a/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py +++ b/vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py @@ -7,6 +7,7 @@ from pathlib import Path from pathlib import PurePath import sys +import os import argparse import textwrap import shutil @@ -18,13 +19,12 @@ from vtr import ( load_list_file, RawDefaultHelpFormatter, - get_latest_run_dir, + get_active_run_dir, load_task_config, find_task_config_file, load_pass_requirements, load_parse_results, parse_vtr_flow, - get_latest_run_number, pretty_print_table, find_task_dir, CommandError, @@ -32,6 +32,7 @@ VtrError, create_jobs, paths, + RunDir, ) # pylint: enable=wrong-import-position @@ -130,7 +131,12 @@ def vtr_command_argparser(prog=None): help="QoR geomeans are not computed by default", ) - parser.add_argument("-run", default=None, type=str, help="") + parser.add_argument( + "-run", + default=None, + type=str, + help="Parse the specified run directory. Defaults to the latest.", + ) parser.add_argument("-revision", default="", help="Revision number") @@ -144,6 +150,8 @@ def vtr_command_main(arg_list, prog=None): """ # Load the arguments args = vtr_command_argparser(prog).parse_args(arg_list) + if args.run is not None: + RunDir.set_user_run_dir_name(args.run) try: task_names = args.task @@ -208,7 +216,7 @@ def parse_task(config, config_jobs, flow_metrics_basename=FIRST_PARSE_FILE, alt_ max_arch_len = len("architecture") max_circuit_len = len("circuit") for job in config_jobs: - work_dir = job.work_dir(get_latest_run_dir(find_task_dir(config, alt_tasks_dir))) + work_dir = job.work_dir(get_active_run_dir(find_task_dir(config, alt_tasks_dir))) job.parse_command()[0] = work_dir # job.second_parse_command()[0] = work_dir job.qor_parse_command()[0] = work_dir @@ -433,7 +441,7 @@ def check_two_files( ) num_qor_failures = 0 # Verify that the first results pass each metric for all cases in the second results - for (arch, circuit, script_params) in second_primary_keys: + for arch, circuit, script_params in second_primary_keys: second_metrics = second_results.metrics(arch, circuit, script_params) first_metrics = first_results.metrics(arch, circuit, script_params) first_fail = True @@ -525,7 +533,7 @@ def calc_geomean(args, configs): first = False lines = summary.readlines() print( - get_latest_run_number(find_task_dir(configs[0], args.alt_tasks_dir)), + os.path.basename(get_active_run_dir(find_task_dir(configs[0], args.alt_tasks_dir))), file=out, end="\t", ) @@ -571,7 +579,7 @@ def find_latest_run_dir(config, alt_tasks_dir=None): """Find the latest run directory for given configuration""" task_dir = find_task_dir(config, alt_tasks_dir) - run_dir = get_latest_run_dir(task_dir) + run_dir = get_active_run_dir(task_dir) if not run_dir: raise InspectError( diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index 2df9317c81c..2ab1e4c31b5 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -22,6 +22,10 @@ yosys_tcl_path = vtr_flow_path / "misc" / "yosys" yosys_script_path = yosys_tcl_path / "synthesis.tcl" +# Synlig paths +synlig_path = root_path / "build" / "bin" / "synlig_install" +synlig_exe_path = synlig_path / "usr" / "local" / "bin" / "synlig" + # PARMYS paths parmys_path = root_path / "parmys" parmys_verify_path = parmys_path / "verify_parmys.sh" diff --git a/vtr_flow/scripts/python_libs/vtr/task.py b/vtr_flow/scripts/python_libs/vtr/task.py index 5af290578f7..3d063d05202 100644 --- a/vtr_flow/scripts/python_libs/vtr/task.py +++ b/vtr_flow/scripts/python_libs/vtr/task.py @@ -1,6 +1,7 @@ """ Module that contains the task functions """ + import itertools from pathlib import Path @@ -15,13 +16,14 @@ load_list_file, load_parse_results, get_existing_run_dir, - get_latest_run_dir, get_next_run_dir, + get_active_run_dir, find_task_dir, load_script_param, paths, ) + # pylint: disable=too-many-instance-attributes, too-many-arguments, too-many-locals, too-few-public-methods class TaskConfig: """ @@ -55,7 +57,7 @@ def __init__( pad_file=None, additional_files=None, additional_files_list_add=None, - circuit_constraint_list_add=None + circuit_constraint_list_add=None, ): self.task_name = task_name self.config_dir = config_dir @@ -82,9 +84,9 @@ def __init__( self.pad_file = pad_file self.additional_files = additional_files self.additional_files_list_add = additional_files_list_add - self.circuit_constraints = parse_circuit_constraint_list(circuit_constraint_list_add, - self.circuits, - self.archs) + self.circuit_constraints = parse_circuit_constraint_list( + circuit_constraint_list_add, self.circuits, self.archs + ) # pylint: enable=too-few-public-methods @@ -306,9 +308,8 @@ def check_include_fields(config_file, key_values): ) ) -def parse_circuit_constraint_list( - circuit_constraint_list, circuits_list, arch_list -) -> dict: + +def parse_circuit_constraint_list(circuit_constraint_list, circuits_list, arch_list) -> dict: """ Parse the circuit constraints passed in via the config file. Circuit constraints are expected to have the following syntax: @@ -343,38 +344,39 @@ def parse_circuit_constraint_list( # Parse the circuit constraint list for circuit_constraint in circuit_constraint_list: # Remove the round brackets. - if circuit_constraint[0] != '(' or circuit_constraint[-1] != ')': - raise VtrError(f"Circuit constraint syntax error: \"{circuit_constraint}\"") + if circuit_constraint[0] != "(" or circuit_constraint[-1] != ")": + raise VtrError(f'Circuit constraint syntax error: "{circuit_constraint}"') circuit_constraint = circuit_constraint[1:-1] # Split the circuit and the constraint - split_constraint_line = circuit_constraint.split(',') + split_constraint_line = circuit_constraint.split(",") if len(split_constraint_line) != 2: - raise VtrError(f"Circuit constraint has too many arguments: \"{circuit_constraint}\"") + raise VtrError(f'Circuit constraint has too many arguments: "{circuit_constraint}"') circuit = split_constraint_line[0].strip() constraint = split_constraint_line[1].strip() # Check that the circuit actually exists. if circuit not in circuits_list: - raise VtrError(f"Cannot constrain circuit \"{circuit}\", circuit has not been added") + raise VtrError(f'Cannot constrain circuit "{circuit}", circuit has not been added') # Parse the constraint split_constraint = constraint.split("=") if len(split_constraint) != 2: - raise VtrError(f"Circuit constraint syntax error: \"{circuit_constraint}\"") + raise VtrError(f'Circuit constraint syntax error: "{circuit_constraint}"') constr_key = split_constraint[0].strip() constr_val = split_constraint[1].strip() # Check that the constr_key is valid. if constr_key not in circuit_constraint_keys: - raise VtrError(f"Invalid constraint \"{constr_key}\" used on circuit \"{circuit}\"") + raise VtrError(f'Invalid constraint "{constr_key}" used on circuit "{circuit}"') # In the case of arch constraints, make sure this arch exists. if constr_key == "arch" and constr_val not in arch_list: - raise VtrError(f"Cannot constrain arch \"{constr_key}\", arch has not been added") + raise VtrError(f'Cannot constrain arch "{constr_key}", arch has not been added') # Make sure this circuit is not already constrained with this constr_arg if res_circuit_constraints[circuit][constr_key] is not None: - raise VtrError(f"Circuit \"{circuit}\" cannot be constrained more than once") + raise VtrError(f'Circuit "{circuit}" cannot be constrained more than once') # Add the constraint for this circuit res_circuit_constraints[circuit][constr_key] = constr_val return res_circuit_constraints + def shorten_task_names(configs, common_task_prefix): """ Shorten the task names of the configs by remove the common task prefix. @@ -407,7 +409,7 @@ def find_longest_task_description(configs): def get_work_dir_addr(arch, circuit, noc_traffic): - """ Get the work directory address under under run_dir """ + """Get the work directory address under under run_dir""" work_dir = None if noc_traffic: work_dir = str(PurePath(arch).joinpath(circuit).joinpath(noc_traffic)) @@ -418,7 +420,7 @@ def get_work_dir_addr(arch, circuit, noc_traffic): def create_second_parse_cmd(config): - """ Create the parse command to run the second time """ + """Create the parse command to run the second time""" second_parse_cmd = None if config.second_parse_file: second_parse_cmd = [ @@ -436,7 +438,7 @@ def create_second_parse_cmd(config): def create_cmd( abs_circuit_filepath, abs_arch_filepath, config, args, circuit, noc_traffic ) -> Tuple: - """ Create the command to run the task """ + """Create the command to run the task""" # Collect any extra script params from the config file cmd = [abs_circuit_filepath, abs_arch_filepath] @@ -583,10 +585,7 @@ def create_jobs(args, configs, after_run=False) -> List[Job]: work_dir = get_work_dir_addr(arch, circuit, noc_traffic) run_dir = ( - str( - Path(get_latest_run_dir(find_task_dir(config, args.alt_tasks_dir))) - / work_dir - ) + str(Path(get_active_run_dir(find_task_dir(config, args.alt_tasks_dir))) / work_dir) if after_run else str( Path(get_next_run_dir(find_task_dir(config, args.alt_tasks_dir))) / work_dir @@ -780,6 +779,7 @@ def ret_expected_vpr_status(arch, circuit, golden_results, script_params=None): return golden_metrics["vpr_status"] + def apply_cmd_line_circuit_constraints(cmd, circuit, config): """ Apply the circuit constraints to the command line. If the circuit is not @@ -798,6 +798,7 @@ def apply_cmd_line_circuit_constraints(cmd, circuit, config): if constrained_route_w is not None: cmd += ["--route_chan_width", constrained_route_w] + def resolve_vtr_source_file(config, filename, base_dir=""): """ Resolves an filename with a base_dir diff --git a/vtr_flow/scripts/python_libs/vtr/util.py b/vtr_flow/scripts/python_libs/vtr/util.py index 61b52ee991b..a80521f07e8 100644 --- a/vtr_flow/scripts/python_libs/vtr/util.py +++ b/vtr_flow/scripts/python_libs/vtr/util.py @@ -22,6 +22,31 @@ from vtr import paths +class RunDir: + """ + A class for representing a run directory. + """ + + # The run directory name passed by set_global_run_dir + # is the run directory name to parse. + # If it is None, the latest run directory will be parsed. + g_run_dir_name = None + + @classmethod + def set_user_run_dir_name(cls, current_run_dir_name): + """ + Set the run directory name passed by the user. + """ + cls.g_run_dir_name = current_run_dir_name + + @classmethod + def get_user_run_dir_name(cls): + """ + Get the run directory name passed by the user. + """ + return cls.g_run_dir_name + + class RawDefaultHelpFormatter( argparse.ArgumentDefaultsHelpFormatter, argparse.RawDescriptionHelpFormatter ): @@ -154,7 +179,7 @@ def run_system_command( # or RR graph files to VPR. PWD environment variable is updated # manually to prevent capnproto from throwing exceptions. modified_environ = os.environ.copy() - modified_environ['PWD'] = str(temp_dir) + modified_environ["PWD"] = str(temp_dir) proc = subprocess.Popen( cmd, @@ -162,7 +187,7 @@ def run_system_command( stderr=stderr, # stderr redirected to stderr universal_newlines=True, # Lines always end in \n cwd=str(temp_dir), # Where to run the command - env=modified_environ + env=modified_environ, ) # Read the output line-by-line and log it @@ -521,16 +546,18 @@ def find_task_dir(config, alt_tasks_dir=None): return str(task_dir) -def get_latest_run_dir(base_dir): +def get_active_run_dir(base_dir): """ - Returns the run directory with the highest run number in base_dir + Returns full path to the active run directory + locatedin base_dir """ - latest_run_number = get_latest_run_number(base_dir) + active_run_dir_name = get_active_run_dir_name(base_dir) - if latest_run_number is None: - return None + run_dir = None + if active_run_dir_name: + run_dir = str(PurePath(base_dir) / active_run_dir_name) - return str(PurePath(base_dir) / run_dir_name(latest_run_number)) + return run_dir def get_existing_run_dir(base_dir: str, run_dir: str) -> str: @@ -549,34 +576,40 @@ def get_next_run_number(base_dir): """ Returns the next available (i.e. non-existing) run number in base_dir """ - latest_run_number = get_latest_run_number(base_dir) - - if latest_run_number is None: - next_run_number = 1 - else: + latest_run_dir_name = get_active_run_dir_name(base_dir) + match = re.match(r"^run(\d{3})$", latest_run_dir_name) + next_run_number = 1 + if match: + latest_run_number = int(match.group(1)) next_run_number = latest_run_number + 1 return next_run_number -def get_latest_run_number(base_dir): +def get_active_run_dir_name(base_dir): """ - Returns the highest run number of all run directories with in base_dir + Returns the active run directory name. If the user has specified + a run directory name, it will be returned. Otherwise, the + highest run number of all run directories within in base_dir + will be returned. """ - run_number = 1 - run_dir = Path(base_dir) / run_dir_name(run_number) + active_run_dir_name = "" + if RunDir.get_user_run_dir_name() is not None: + active_run_dir_name = RunDir.get_user_run_dir_name() + else: + run_number = 1 + run_dir = Path(base_dir) / run_dir_name(run_number) - if not run_dir.exists(): - # No existing run directories - return None + if run_dir.exists(): + while run_dir.exists(): + run_number += 1 + run_dir = Path(base_dir) / run_dir_name(run_number) - while run_dir.exists(): - run_number += 1 - run_dir = Path(base_dir) / run_dir_name(run_number) + # Currently one-past the last existing run dir, + # to get latest existing, subtract one + active_run_dir_name = run_dir_name(run_number - 1) - # Currently one-past the last existing run dir, - # to get latest existing, subtract one - return run_number - 1 + return active_run_dir_name def run_dir_name(run_num): diff --git a/vtr_flow/scripts/python_libs/vtr/vpr/__init__.py b/vtr_flow/scripts/python_libs/vtr/vpr/__init__.py index 895950332ef..823908b93e2 100644 --- a/vtr_flow/scripts/python_libs/vtr/vpr/__init__.py +++ b/vtr_flow/scripts/python_libs/vtr/vpr/__init__.py @@ -1,4 +1,5 @@ """ __init__ for the VPR Module """ + from .vpr import run, run_relax_w, cmp_full_vs_incr_sta, run_second_time diff --git a/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py b/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py index 003adb9f8cb..50278757656 100644 --- a/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py +++ b/vtr_flow/scripts/python_libs/vtr/vpr/vpr.py @@ -1,12 +1,14 @@ """ Module to interact with VPR and its various options """ + from collections import OrderedDict from pathlib import Path from os import environ from vtr import CommandRunner, relax_w, determine_min_w, verify_file, paths from vtr.error import InspectError + # pylint: disable=too-many-arguments,too-many-locals def run_relax_w( architecture, @@ -296,9 +298,9 @@ def run_second_time( if "write_intra_cluster_router_lookahead" in second_run_args: intra_cluster_router_lookahead = second_run_args["write_intra_cluster_router_lookahead"] second_run_args["read_intra_cluster_router_lookahead"] = intra_cluster_router_lookahead - second_run_args[ - "write_intra_cluster_router_lookahead" - ] = "intra_cluster_router_lookahead2.capnp" + second_run_args["write_intra_cluster_router_lookahead"] = ( + "intra_cluster_router_lookahead2.capnp" + ) # run VPR run( diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index 3d584274e3f..70ff3f2ac9b 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -22,6 +22,7 @@ VTR_STAGES = ["odin", "parmys", "abc", "ace", "vpr"] + # pylint: disable=too-few-public-methods class VtrStageArgparseAction(argparse.Action): """ @@ -45,6 +46,7 @@ def __call__(self, parser, namespace, value, option_string=None): # pylint: enable=too-few-public-methods + # pylint: disable=too-many-statements def vtr_command_argparser(prog=None): """ @@ -459,10 +461,10 @@ def format_human_readable_memory(num_kbytes): """format the number of bytes given as a human readable value""" if num_kbytes < 1024: value = "%.2f KiB" % (num_kbytes) - elif num_kbytes < (1024 ** 2): - value = "%.2f MiB" % (num_kbytes / (1024 ** 1)) + elif num_kbytes < (1024**2): + value = "%.2f MiB" % (num_kbytes / (1024**1)) else: - value = "%.2f GiB" % (num_kbytes / (1024 ** 2)) + value = "%.2f GiB" % (num_kbytes / (1024**2)) return value @@ -550,9 +552,11 @@ def vtr_command_main(arg_list, prog=None): vpr_args["read_vpr_constraints"] = Path(vpr_constraint_file_copy).name print( - args.name - if args.name - else Path(args.architecture_file).stem + "/" + Path(args.circuit_file).stem, + ( + args.name + if args.name + else Path(args.architecture_file).stem + "/" + Path(args.circuit_file).stem + ), end="\t\t", ) # Run the flow diff --git a/vtr_flow/scripts/run_vtr_task.py b/vtr_flow/scripts/run_vtr_task.py index 0d9c5013181..ce16f44d518 100755 --- a/vtr_flow/scripts/run_vtr_task.py +++ b/vtr_flow/scripts/run_vtr_task.py @@ -471,9 +471,9 @@ def format_human_readable_time(seconds): def format_human_readable_memory(num_bytes): """format the number of bytes given as a human readable value""" - if num_bytes < 1024 ** 3: - return "%.2f MiB" % (num_bytes / (1024 ** 2)) - return "%.2f GiB" % (num_bytes / (1024 ** 3)) + if num_bytes < 1024**3: + return "%.2f MiB" % (num_bytes / (1024**2)) + return "%.2f GiB" % (num_bytes / (1024**3)) def run_vtr_flow_process(queue, run_dirs, job, script) -> None: diff --git a/vtr_flow/scripts/tuning_runs/control_runs.py b/vtr_flow/scripts/tuning_runs/control_runs.py index 825b3b7609c..c38e2cd7292 100755 --- a/vtr_flow/scripts/tuning_runs/control_runs.py +++ b/vtr_flow/scripts/tuning_runs/control_runs.py @@ -46,9 +46,7 @@ def parse_results(input_path): Parse the output results """ # Find the runXXX directory with the largest XXX - run_dirs = [ - d for d in os.listdir(input_path) if d.startswith("run") and d[3:].isdigit() - ] + run_dirs = [d for d in os.listdir(input_path) if d.startswith("run") and d[3:].isdigit()] if not run_dirs: print("No runXXX directories found in the specified input path.") sys.exit(1) @@ -63,9 +61,9 @@ def parse_results(input_path): sys.exit(1) # Read the parse_results.txt file and write to full_res.csv - with open( - os.path.join(largest_run_path, "parse_results.txt"), "r" - ) as txt_file, open(full_res_csv_path, "w", newline="") as csv_file: + with open(os.path.join(largest_run_path, "parse_results.txt"), "r") as txt_file, open( + full_res_csv_path, "w", newline="" + ) as csv_file: reader = csv.reader(txt_file, delimiter="\t") writer = csv.writer(csv_file) @@ -97,9 +95,7 @@ def parse_results(input_path): print("Generated average seed results") # Generate gmean_res.csv - generate_geomean_res_csv( - os.path.join(largest_run_path, "avg_seed.csv"), largest_run_path - ) + generate_geomean_res_csv(os.path.join(largest_run_path, "avg_seed.csv"), largest_run_path) print("Generated geometric average results over all the circuits") generate_xlsx(largest_run_path) @@ -147,8 +143,7 @@ def parse_script_params(script_params): j = i + key_length while j < len(parts) and not any( - parts[j : j + len(k.split("_"))] == k.split("_") - for k in PARAMS_DICT + parts[j : j + len(k.split("_"))] == k.split("_") for k in PARAMS_DICT ): value_parts.append(parts[j]) j += 1 diff --git a/vtr_flow/tasks/koios_task_list.txt b/vtr_flow/tasks/koios_task_list.txt new file mode 100644 index 00000000000..893a9cdd78b --- /dev/null +++ b/vtr_flow/tasks/koios_task_list.txt @@ -0,0 +1,6 @@ +regression_tests/vtr_reg_nightly_test4/koios_medium +regression_tests/vtr_reg_nightly_test6/koios_other +regression_tests/vtr_reg_weekly/koios_bwave_float_large +regression_tests/vtr_reg_weekly/koios_dla_large +regression_tests/vtr_reg_weekly/koios_large +regression_tests/vtr_reg_weekly/koios_proxy diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt index aab4bc19474..a19aa57c938 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 2.23 vpr 62.52 MiB -1 -1 0.44 18128 3 0.11 -1 -1 33248 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64024 99 130 353 483 1 222 301 13 13 169 clb auto 22.9 MiB 0.06 730 30541 5185 13290 12066 62.5 MiB 0.05 0.00 28 1583 11 3.33e+06 2.25e+06 384474. 2275.00 0.60 - k4_N10_memSize16384_memData64.xml diffeq1.v common 3.94 vpr 66.34 MiB -1 -1 0.54 23352 23 0.30 -1 -1 34272 -1 -1 77 162 0 5 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67928 162 96 1200 1141 1 675 340 13 13 169 clb auto 26.0 MiB 0.18 5120 92848 24971 61178 6699 66.3 MiB 0.19 0.00 52 9701 16 3.33e+06 2.76e+06 671819. 3975.26 1.21 - k4_N10_memSize16384_memData64.xml single_wire.v common 0.68 vpr 60.16 MiB -1 -1 0.06 16212 1 0.03 -1 -1 29556 -1 -1 0 1 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61604 1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 2 3 0 3 0 60.2 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 - k4_N10_memSize16384_memData64.xml single_ff.v common 0.73 vpr 60.14 MiB -1 -1 0.15 16376 1 0.02 -1 -1 29780 -1 -1 1 2 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61580 2 1 3 4 1 3 4 3 3 9 -1 auto 21.3 MiB 0.00 6 9 6 0 3 60.1 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 + k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.71 vpr 62.29 MiB -1 -1 0.45 18372 3 0.09 -1 -1 33140 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63780 99 130 353 483 1 222 301 13 13 169 clb auto 22.7 MiB 0.06 730 30541 5185 13290 12066 62.3 MiB 0.05 0.00 28 1583 11 3.33e+06 2.25e+06 384474. 2275.00 0.18 + k4_N10_memSize16384_memData64.xml diffeq1.v common 3.90 vpr 66.30 MiB -1 -1 0.72 23492 23 0.30 -1 -1 34028 -1 -1 77 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67888 162 96 1200 1141 1 675 340 13 13 169 clb auto 25.9 MiB 0.18 5120 92848 24971 61178 6699 66.3 MiB 0.19 0.00 52 9637 13 3.33e+06 2.76e+06 671819. 3975.26 1.14 + k4_N10_memSize16384_memData64.xml single_wire.v common 2.10 vpr 59.81 MiB -1 -1 0.16 16372 1 0.17 -1 -1 29680 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61244 1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 2 3 0 3 0 59.8 MiB 0.01 0.00 2 1 1 30000 0 1489.46 165.495 0.01 + k4_N10_memSize16384_memData64.xml single_ff.v common 2.13 vpr 59.62 MiB -1 -1 0.15 16244 1 0.17 -1 -1 29552 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61048 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 6 9 6 0 3 59.6 MiB 0.01 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt index 67331c4ebeb..751bc75b90b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.79 vpr 64.14 MiB -1 -1 0.42 18236 3 0.09 -1 -1 33188 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65676 99 130 344 474 1 225 301 13 13 169 clb auto 24.4 MiB 0.09 670 76909 23210 36946 16753 64.1 MiB 0.26 0.00 2.16096 -124.917 -2.16096 2.16096 0.32 0.00129032 0.00122184 0.1026 0.0970333 -1 -1 -1 -1 32 1294 10 6.63067e+06 4.37447e+06 323148. 1912.12 1.31 0.41172 0.377314 11612 59521 -1 1127 11 526 869 34973 10462 1.97404 1.97404 -140.169 -1.97404 -0.343814 -0.101108 396943. 2348.77 0.10 0.05 0.06 -1 -1 0.10 0.0333808 0.0307491 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.81 vpr 64.05 MiB -1 -1 0.41 18040 3 0.09 -1 -1 33320 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65588 99 130 344 474 1 225 301 13 13 169 clb auto 24.3 MiB 0.09 670 76909 23210 36946 16753 64.1 MiB 0.26 0.00 2.16096 -124.917 -2.16096 2.16096 0.31 0.00129523 0.00122583 0.102212 0.0966604 -1 -1 -1 -1 32 1294 10 6.63067e+06 4.37447e+06 323148. 1912.12 1.31 0.406344 0.372511 11612 59521 -1 1127 11 526 869 34973 10462 1.97404 1.97404 -140.169 -1.97404 -0.343814 -0.101108 396943. 2348.77 0.10 0.05 0.06 -1 -1 0.10 0.0333856 0.0307499 - k6_N10_mem32K_40nm.xml diffeq1.v common 11.07 vpr 67.31 MiB -1 -1 0.73 22916 15 0.35 -1 -1 34340 -1 -1 61 162 0 5 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68924 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.9 MiB 0.28 5631 94844 28473 58959 7412 67.3 MiB 0.68 0.01 21.7383 -1576.03 -21.7383 21.7383 0.52 0.00334089 0.00313474 0.301598 0.282973 -1 -1 -1 -1 44 10661 49 1.21132e+07 5.26753e+06 665287. 2598.78 6.02 1.62204 1.48659 20656 131250 -1 8667 20 3482 8436 990185 277410 22.0559 22.0559 -1674.9 -22.0559 0 0 864808. 3378.16 0.21 0.34 0.12 -1 -1 0.21 0.151934 0.140555 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 11.23 vpr 67.06 MiB -1 -1 0.73 23204 15 0.35 -1 -1 34356 -1 -1 61 162 0 5 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68668 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.6 MiB 0.27 5631 94844 28473 58959 7412 67.1 MiB 0.69 0.01 21.7383 -1576.03 -21.7383 21.7383 0.52 0.00336493 0.00315749 0.301999 0.283119 -1 -1 -1 -1 44 10661 49 1.21132e+07 5.26753e+06 665287. 2598.78 6.18 1.63915 1.50303 20656 131250 -1 8667 20 3482 8436 990185 277410 22.0559 22.0559 -1674.9 -22.0559 0 0 864808. 3378.16 0.21 0.34 0.12 -1 -1 0.21 0.151674 0.140243 - k6_N10_mem32K_40nm.xml single_wire.v common 0.71 vpr 61.63 MiB -1 -1 0.15 16380 1 0.02 -1 -1 29720 -1 -1 0 1 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63108 1 1 1 2 0 1 2 3 3 9 -1 auto 23.0 MiB 0.00 2 3 0 3 0 61.6 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0494e-05 7.076e-06 7.8316e-05 5.7044e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00113075 0.00106709 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00105433 0.00102822 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.70 vpr 61.38 MiB -1 -1 0.14 16336 1 0.02 -1 -1 29760 -1 -1 0 1 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 62848 1 1 1 2 0 1 2 3 3 9 -1 auto 22.7 MiB 0.00 2 3 0 3 0 61.4 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0478e-05 7.086e-06 6.5653e-05 4.7198e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00141342 0.00135618 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109338 0.00106763 - k6_N10_mem32K_40nm.xml single_ff.v common 0.72 vpr 61.40 MiB -1 -1 0.12 16364 1 0.02 -1 -1 29716 -1 -1 1 2 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 62872 2 1 3 4 1 3 4 3 3 9 -1 auto 22.8 MiB 0.00 6 9 3 5 1 61.4 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5219e-05 1.1422e-05 0.000111249 8.9402e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00146865 0.00138013 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00114176 0.00110413 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.75 vpr 61.35 MiB -1 -1 0.14 16260 1 0.02 -1 -1 29632 -1 -1 1 2 0 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 62820 2 1 3 4 1 3 4 3 3 9 -1 auto 22.7 MiB 0.00 6 9 3 5 1 61.3 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5145e-05 1.1318e-05 0.000103946 8.1944e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00129416 0.0012252 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00133017 0.00128358 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.47 vpr 63.16 MiB -1 -1 0.44 18236 3 0.17 -1 -1 33188 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 99 130 344 474 1 225 301 13 13 169 clb auto 23.3 MiB 0.09 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128139 0.00121469 0.100824 0.095478 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254103 0.235005 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0312641 0.0288189 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.44 vpr 63.16 MiB -1 -1 0.50 18152 3 0.14 -1 -1 33088 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 99 130 344 474 1 225 301 13 13 169 clb auto 23.2 MiB 0.11 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128481 0.00121739 0.100806 0.0954483 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254201 0.235091 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0311227 0.0286984 + k6_N10_mem32K_40nm.xml diffeq1.v common 9.49 vpr 67.11 MiB -1 -1 0.77 23280 15 0.36 -1 -1 34140 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68724 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.7 MiB 0.29 5596 100404 30167 62963 7274 67.1 MiB 0.72 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332766 0.00312916 0.315543 0.296132 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.42 1.40293 1.28823 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165646 0.152968 + k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 9.36 vpr 66.73 MiB -1 -1 0.76 23068 15 0.37 -1 -1 34060 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68332 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.4 MiB 0.27 5596 100404 30167 62963 7274 66.7 MiB 0.73 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332438 0.00312633 0.31865 0.29876 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.32 1.38842 1.27429 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165924 0.153299 + k6_N10_mem32K_40nm.xml single_wire.v common 2.19 vpr 61.04 MiB -1 -1 0.10 16040 1 0.17 -1 -1 29628 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62508 1 1 1 2 0 1 2 3 3 9 -1 auto 22.4 MiB 0.03 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0106e-05 6.693e-06 6.7577e-05 4.7955e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00184576 0.00171316 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00130358 0.00127692 + k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.14 vpr 61.03 MiB -1 -1 0.18 16180 1 0.17 -1 -1 29612 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62496 1 1 1 2 0 1 2 3 3 9 -1 auto 22.5 MiB 0.01 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 3.4991e-05 2.3839e-05 0.000154694 0.000110075 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.01 0.00205152 0.00184775 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106138 0.00103434 + k6_N10_mem32K_40nm.xml single_ff.v common 2.12 vpr 60.94 MiB -1 -1 0.17 16352 1 0.17 -1 -1 29692 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62400 2 1 3 4 1 3 4 3 3 9 -1 auto 22.4 MiB 0.01 6 9 3 5 1 60.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5239e-05 1.148e-05 9.224e-05 7.1486e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00131631 0.00123081 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011347 0.00109647 + k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.11 vpr 61.02 MiB -1 -1 0.17 16384 1 0.17 -1 -1 29576 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62488 2 1 3 4 1 3 4 3 3 9 -1 auto 22.5 MiB 0.00 6 9 3 5 1 61.0 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.54e-05 1.1599e-05 9.8314e-05 7.6493e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.001247 0.00116724 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00104656 0.00101086 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt index f8224ce61bf..e5e577a6aa0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml mkPktMerge.v common 14.48 vpr 69.41 MiB -1 -1 1.43 25504 2 0.13 -1 -1 33808 -1 -1 43 311 15 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71080 311 156 972 1128 1 953 525 28 28 784 memory auto 28.9 MiB 0.44 9159 207991 76469 122068 9454 69.4 MiB 1.18 0.02 4.10864 -4363.81 -4.10864 4.10864 1.88 0.00581049 0.00492665 0.571738 0.503271 -1 -1 -1 -1 38 14134 13 4.25198e+07 1.05374e+07 1.95643e+06 2495.44 4.44 1.4407 1.2729 61576 387106 -1 13120 12 2507 3155 746004 220560 4.19903 4.19903 -4897.24 -4.19903 -19.5582 -0.360359 2.46901e+06 3149.24 0.67 0.31 0.33 -1 -1 0.67 0.171757 0.154277 + k6_N10_mem32K_40nm.xml mkPktMerge.v common 14.27 vpr 75.54 MiB -1 -1 1.67 25360 2 0.13 -1 -1 33796 -1 -1 43 311 15 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77356 311 156 972 1128 1 953 525 28 28 784 memory auto 28.9 MiB 0.44 8505 220693 82593 126911 11189 69.5 MiB 1.24 0.02 3.82651 -4329.36 -3.82651 3.82651 0.84 0.00554225 0.00490893 0.598549 0.528234 -1 -1 -1 -1 40 13414 12 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 6.02 1.94301 1.71815 62360 400487 -1 12485 12 2406 2992 760238 228941 4.26893 4.26893 -4812.21 -4.26893 -13.8425 -0.321515 2.55406e+06 3257.73 0.09 0.29 0.34 -1 -1 0.09 0.16964 0.153486 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt index 02aded8804a..cbe871a6d70 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.65 vpr 62.39 MiB -1 -1 0.47 18396 3 0.09 -1 -1 33152 -1 -1 71 99 1 0 success v8.0.0-11851-gfde0f8fc1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T14:30:30 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63892 99 130 353 483 1 222 301 13 13 169 clb auto 22.7 MiB 0.06 723 26509 3069 10019 13421 62.4 MiB 0.04 0.00 28 1598 8 3.33e+06 2.25e+06 384474. 2275.00 0.98 +k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.71 vpr 61.64 MiB -1 -1 0.45 18444 3 0.09 -1 -1 32856 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63120 99 130 353 483 1 222 301 13 13 169 clb auto 21.8 MiB 0.06 723 26509 3069 10019 13421 61.6 MiB 0.04 0.00 28 1598 8 3.33e+06 2.25e+06 384474. 2275.00 0.18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt index e28c0960805..1c07cad2e4f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.45 vpr 64.20 MiB -1 -1 0.07 20736 1 0.03 -1 -1 35464 -1 -1 2 6 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65736 6 1 13 14 2 8 9 4 4 16 clb auto 25.8 MiB 0.00 15 27 4 16 7 64.2 MiB 0.00 0.00 0.876768 -3.25729 -0.876768 0.545 0.01 3.3326e-05 2.4624e-05 0.000207932 0.000172543 20 18 16 107788 107788 10441.3 652.579 0.01 0.00186873 0.00161723 742 1670 -1 18 2 7 7 153 93 1.4073 0.545 -4.29789 -1.4073 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00108236 0.00102087 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.49 vpr 64.30 MiB -1 -1 0.09 20608 1 0.04 -1 -1 35572 -1 -1 2 3 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65840 3 -1 23 23 2 3 5 4 4 16 clb auto 26.0 MiB 0.01 2 12 2 3 7 64.3 MiB 0.00 0.00 0.545 -7.62503 -0.545 0.545 0.01 5.8243e-05 5.0672e-05 0.000432079 0.000390226 8 1 1 107788 107788 4888.88 305.555 0.02 0.00256655 0.00231135 622 902 -1 1 1 1 1 9 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00154902 0.00148079 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.91 vpr 62.53 MiB -1 -1 0.10 16916 1 0.05 -1 -1 32024 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 6 1 13 14 2 8 9 4 4 16 clb auto 23.8 MiB 0.01 22 27 6 15 6 62.5 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.8829e-05 2.8382e-05 0.000261465 0.000217889 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00235757 0.00212728 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00170712 0.00164334 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.93 vpr 62.57 MiB -1 -1 0.14 17260 1 0.06 -1 -1 31980 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64076 3 -1 23 23 2 3 5 4 4 16 clb auto 23.8 MiB 0.01 3 12 2 3 7 62.6 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.0445e-05 5.1078e-05 0.000540631 0.00048682 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00313926 0.00293123 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00237872 0.0022794 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt index c5973b977a6..ace8a8d93f0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.56 vpr 64.33 MiB -1 -1 0.07 20736 1 0.04 -1 -1 35300 -1 -1 2 6 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65872 6 1 13 14 2 8 9 4 4 16 clb auto 26.0 MiB 0.00 15 27 4 16 7 64.3 MiB 0.00 0.00 0.876768 -3.25729 -0.876768 0.545 0.01 3.8575e-05 3.0523e-05 0.000220522 0.000177612 20 18 16 107788 107788 10441.3 652.579 0.01 0.00189872 0.00159852 742 1670 -1 18 2 7 7 153 93 1.4073 0.545 -4.29789 -1.4073 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00112306 0.00106033 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.57 vpr 64.14 MiB -1 -1 0.09 20736 1 0.04 -1 -1 35416 -1 -1 1 2 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65680 2 -1 16 16 1 2 3 3 3 9 -1 auto 25.9 MiB 0.01 2 6 3 0 3 64.1 MiB 0.00 0.00 0.545 -3.815 -0.545 0.545 0.00 6.3651e-05 3.6185e-05 0.000421892 0.000363995 2 1 1 53894 53894 1178.84 130.982 0.01 0.00245442 0.00219784 283 309 -1 1 1 1 1 9 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00140976 0.00134385 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.12 vpr 61.70 MiB -1 -1 0.11 16536 1 0.08 -1 -1 31596 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63184 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.7 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.8582e-05 2.7966e-05 0.000277936 0.000219445 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.02 0.00248443 0.00222718 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00178059 0.00171145 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.12 vpr 61.63 MiB -1 -1 0.15 16580 1 0.06 -1 -1 31648 -1 -1 1 2 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63112 2 -1 16 16 1 2 3 3 3 9 -1 auto 23.2 MiB 0.01 3 6 4 0 2 61.6 MiB 0.00 0.00 0.545 -3.815 -0.545 0.545 0.00 4.1349e-05 3.4027e-05 0.000423997 0.000380122 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.00 0.00258339 0.00244324 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00225406 0.00217221 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt index a82f6475eb8..2b26635347b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml bigkey.blif common 5.34 vpr 66.09 MiB -1 -1 -1 -1 3 0.41 -1 -1 38400 -1 -1 53 229 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 67676 229 197 1023 1220 1 510 479 16 16 256 io auto 28.2 MiB 0.25 3590 165303 54609 101546 9148 66.1 MiB 0.56 0.01 2.09742 -520.234 -2.09742 2.09742 0.72 0.00198922 0.0017893 0.194468 0.174387 38 6231 19 1.05632e+07 2.85638e+06 667532. 2607.55 1.61 0.552311 0.501002 25328 137766 -1 5709 10 1328 2368 138222 31100 2.53491 2.53491 -631.681 -2.53491 0 0 843755. 3295.92 0.23 0.09 0.11 -1 -1 0.23 0.0694375 0.0651755 -k6_frac_N10_40nm.xml clma.blif common 5.81 vpr 63.61 MiB -1 -1 -1 -1 7 2.43 -1 -1 43060 -1 -1 77 36 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65132 36 82 542 624 1 390 195 11 11 121 clb auto 25.6 MiB 0.39 2049 40310 15727 18888 5695 63.6 MiB 0.19 0.00 4.12702 -139.772 -4.12702 4.12702 0.35 0.00089595 0.000795753 0.0662268 0.0581277 40 4765 27 4.36541e+06 4.14984e+06 303235. 2506.08 1.27 0.24116 0.212364 11571 60661 -1 3811 17 2179 7425 230352 49600 4.72633 4.72633 -172.493 -4.72633 0 0 379421. 3135.71 0.10 0.10 0.05 -1 -1 0.10 0.0504584 0.0466881 -k6_frac_N10_40nm.xml diffeq.blif common 3.47 vpr 65.28 MiB -1 -1 -1 -1 8 0.38 -1 -1 37780 -1 -1 51 64 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66848 64 39 941 980 1 450 154 10 10 100 clb auto 27.4 MiB 0.49 2676 18694 4142 13457 1095 65.3 MiB 0.17 0.00 4.29927 -776.73 -4.29927 4.29927 0.21 0.00140232 0.00123094 0.0782133 0.0687319 46 4588 16 3.44922e+06 2.74859e+06 276332. 2763.32 1.14 0.400394 0.355124 9816 55112 -1 4229 15 1767 5248 152494 32440 5.1527 5.1527 -909.086 -5.1527 0 0 354105. 3541.05 0.09 0.11 0.05 -1 -1 0.09 0.074353 0.068615 -k6_frac_N10_40nm.xml dsip.blif common 7.16 vpr 67.73 MiB -1 -1 -1 -1 3 0.29 -1 -1 38168 -1 -1 68 229 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 69360 229 197 1135 1332 1 648 494 16 16 256 io auto 29.8 MiB 0.61 4921 178126 59233 109418 9475 67.7 MiB 0.72 0.01 2.05678 -537.964 -2.05678 2.05678 0.70 0.00258579 0.00228238 0.249464 0.221181 36 8990 21 1.05632e+07 3.66479e+06 638738. 2495.07 2.87 0.913578 0.809462 24820 128426 -1 8106 12 2276 5612 323677 69139 2.59846 2.59846 -678.186 -2.59846 0 0 786978. 3074.13 0.24 0.17 0.11 -1 -1 0.24 0.102783 0.0965443 -k6_frac_N10_40nm.xml elliptic.blif common 11.17 vpr 75.88 MiB -1 -1 -1 -1 10 1.31 -1 -1 42108 -1 -1 133 131 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 77704 131 114 2471 2585 1 967 378 14 14 196 clb auto 38.7 MiB 2.04 9202 87802 25510 58148 4144 75.9 MiB 0.81 0.01 6.00251 -3050.7 -6.00251 6.00251 0.50 0.00442638 0.00375412 0.333118 0.286228 64 16031 41 7.76074e+06 7.1679e+06 810706. 4136.26 3.96 1.36942 1.18204 22444 164128 -1 14254 16 4284 17997 698961 120654 7.04139 7.04139 -3672.36 -7.04139 0 0 1.00880e+06 5146.95 0.27 0.37 0.15 -1 -1 0.27 0.21767 0.199157 -k6_frac_N10_40nm.xml frisc.blif common 20.76 vpr 77.35 MiB -1 -1 -1 -1 12 2.02 -1 -1 42412 -1 -1 153 20 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 79204 20 116 2477 2593 1 1097 289 15 15 225 clb auto 40.1 MiB 2.38 13235 56634 14640 37590 4404 77.3 MiB 0.80 0.01 7.08157 -3353.27 -7.08157 7.08157 0.61 0.00557214 0.00505815 0.329992 0.284762 80 22726 42 9.10809e+06 8.24578e+06 1.12687e+06 5008.33 11.88 2.38469 2.06328 28171 234221 -1 19580 15 5661 25029 1100753 177994 8.34828 8.34828 -3982.46 -8.34828 0 0 1.41774e+06 6301.08 0.40 0.47 0.23 -1 -1 0.40 0.24451 0.223131 -k6_frac_N10_40nm.xml s298.blif common 3.93 vpr 65.13 MiB -1 -1 -1 -1 8 0.54 -1 -1 37848 -1 -1 62 4 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66692 4 6 671 677 1 352 72 10 10 100 clb auto 27.2 MiB 0.63 3508 3797 558 3049 190 65.1 MiB 0.09 0.00 4.79301 -39.1818 -4.79301 4.79301 0.21 0.00107169 0.000871246 0.0396977 0.0348858 50 5642 44 3.44922e+06 3.34143e+06 295697. 2956.97 1.34 0.354454 0.310134 10016 58256 -1 5050 17 2138 10782 337740 61219 5.55589 5.55589 -47.4222 -5.55589 0 0 379824. 3798.24 0.09 0.16 0.05 -1 -1 0.09 0.0836831 0.0767868 -k6_frac_N10_40nm.xml s38417.blif common 18.17 vpr 81.67 MiB -1 -1 -1 -1 6 3.18 -1 -1 45752 -1 -1 178 29 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 83628 29 106 3450 3556 1 1206 313 16 16 256 clb auto 44.6 MiB 1.73 9735 73591 18515 47646 7430 81.7 MiB 1.01 0.01 4.1003 -2647.73 -4.1003 4.1003 0.71 0.00572737 0.00502875 0.490793 0.413594 50 16598 31 1.05632e+07 9.59313e+06 843755. 3295.92 8.36 2.66872 2.25339 27116 171776 -1 14184 14 5218 17339 563986 111457 4.90849 4.90849 -3063.34 -4.90849 0 0 1.08660e+06 4244.53 0.30 0.40 0.15 -1 -1 0.30 0.294514 0.26614 -k6_frac_N10_40nm.xml s38584.1.blif common 15.38 vpr 81.98 MiB -1 -1 -1 -1 6 2.31 -1 -1 44476 -1 -1 197 38 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 83944 38 304 3259 3563 1 1569 539 17 17 289 clb auto 45.1 MiB 2.22 10132 186859 56261 111331 19267 82.0 MiB 1.57 0.02 3.66766 -2189.34 -3.66766 3.66766 0.83 0.00720702 0.00587597 0.662359 0.559768 58 18045 29 1.21262e+07 1.06171e+07 1.11519e+06 3858.79 4.91 2.07239 1.77997 32499 230706 -1 16150 15 5235 13970 535313 110316 4.52216 4.52216 -2592.43 -4.52216 0 0 1.41877e+06 4909.24 0.44 0.45 0.21 -1 -1 0.44 0.337035 0.302445 -k6_frac_N10_40nm.xml tseng.blif common 3.22 vpr 63.44 MiB -1 -1 -1 -1 7 0.26 -1 -1 36620 -1 -1 34 52 -1 -1 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64964 52 122 664 786 1 355 208 8 8 64 io clb auto 25.5 MiB 0.48 1722 24848 5456 17914 1478 63.4 MiB 0.15 0.00 3.67867 -543.309 -3.67867 3.67867 0.13 0.00118347 0.00104151 0.0584783 0.0523041 60 3348 21 1.94018e+06 1.8324e+06 209903. 3279.73 1.38 0.400601 0.357549 6596 40562 -1 2925 12 1076 2803 103485 26847 4.47179 4.47179 -637.579 -4.47179 0 0 263485. 4116.95 0.06 0.07 0.04 -1 -1 0.06 0.0496902 0.0465196 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common 6.03 vpr 64.18 MiB -1 -1 -1 -1 3 0.52 -1 -1 34720 -1 -1 53 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65716 229 197 1023 1220 1 510 479 16 16 256 io auto 23.6 MiB 0.35 3641 154065 46430 98015 9620 64.2 MiB 0.72 0.01 2.42373 -577.247 -2.42373 2.42373 0.36 0.00384602 0.00349572 0.296143 0.271678 -1 -1 -1 -1 36 6328 35 1.05632e+07 2.85638e+06 638738. 2495.07 1.93 1.0007 0.917076 24820 128426 -1 5481 8 1306 2376 126862 31374 2.67597 2.67597 -632.008 -2.67597 0 0 786978. 3074.13 0.04 0.15 0.12 -1 -1 0.04 0.11083 0.104176 + k6_frac_N10_40nm.xml clma.blif common 9.71 vpr 61.27 MiB -1 -1 -1 -1 7 3.14 -1 -1 39932 -1 -1 79 36 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62740 36 82 542 624 1 389 197 11 11 121 clb auto 21.7 MiB 0.60 2089 43172 15722 20877 6573 61.3 MiB 0.31 0.01 4.60077 -165.07 -4.60077 4.60077 0.14 0.00147192 0.00133772 0.126064 0.114454 -1 -1 -1 -1 44 4139 30 4.36541e+06 4.25763e+06 327165. 2703.84 3.55 0.883664 0.783925 11931 67129 -1 3316 16 1708 5716 138864 32420 4.83136 4.83136 -175.151 -4.83136 0 0 426099. 3521.48 0.02 0.16 0.06 -1 -1 0.02 0.101559 0.0936106 + k6_frac_N10_40nm.xml diffeq.blif common 4.49 vpr 63.36 MiB -1 -1 -1 -1 8 0.52 -1 -1 34256 -1 -1 52 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 64 39 941 980 1 449 155 10 10 100 clb auto 23.4 MiB 0.76 2832 12635 2438 9282 915 63.4 MiB 0.20 0.01 4.98272 -882.824 -4.98272 4.98272 0.11 0.00295588 0.00259149 0.100311 0.0902062 -1 -1 -1 -1 46 4591 19 3.44922e+06 2.80249e+06 276332. 2763.32 1.60 0.775874 0.679691 9816 55112 -1 4111 18 1656 5042 136520 29654 5.41789 5.41789 -952.235 -5.41789 0 0 354105. 3541.05 0.01 0.17 0.05 -1 -1 0.01 0.125756 0.115657 + k6_frac_N10_40nm.xml dsip.blif common 7.14 vpr 64.52 MiB -1 -1 -1 -1 3 0.40 -1 -1 34652 -1 -1 68 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66068 229 197 1135 1332 1 648 494 16 16 256 io auto 24.8 MiB 0.78 5390 162510 50223 103313 8974 64.5 MiB 1.03 0.02 2.31397 -600.978 -2.31397 2.31397 0.34 0.00602326 0.00554387 0.451127 0.410954 -1 -1 -1 -1 34 9972 32 1.05632e+07 3.66479e+06 613832. 2397.78 2.69 1.43645 1.29189 24564 122629 -1 8332 13 2339 5868 306706 68264 2.51113 2.51113 -669.569 -2.51113 0 0 751777. 2936.63 0.04 0.27 0.11 -1 -1 0.04 0.172623 0.161651 + k6_frac_N10_40nm.xml elliptic.blif common 13.54 vpr 72.58 MiB -1 -1 -1 -1 10 1.77 -1 -1 37472 -1 -1 134 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74324 131 114 2471 2585 1 965 379 14 14 196 clb auto 31.6 MiB 3.12 9493 78526 21300 53244 3982 72.6 MiB 1.13 0.02 6.66989 -3362.18 -6.66989 6.66989 0.25 0.0073855 0.00682539 0.510617 0.432228 -1 -1 -1 -1 64 15463 36 7.76074e+06 7.2218e+06 810706. 4136.26 4.40 2.27 1.95789 22444 164128 -1 13666 16 4234 17970 605416 107406 6.78748 6.78748 -3469.91 -6.78748 0 0 1.00880e+06 5146.95 0.04 0.57 0.15 -1 -1 0.04 0.380082 0.346066 + k6_frac_N10_40nm.xml frisc.blif common 19.09 vpr 73.82 MiB -1 -1 -1 -1 12 2.63 -1 -1 37332 -1 -1 154 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75588 20 116 2477 2593 1 1095 290 15 15 225 clb auto 33.0 MiB 3.90 12890 61666 15631 41457 4578 73.8 MiB 1.29 0.02 8.02167 -3816.55 -8.02167 8.02167 0.29 0.00799854 0.00736702 0.607385 0.536113 -1 -1 -1 -1 74 21484 43 9.10809e+06 8.29968e+06 1.06098e+06 4715.46 6.97 3.19949 2.845 27275 217117 -1 19434 16 5788 25215 1069833 185373 8.27179 8.27179 -4029.23 -8.27179 0 0 1.32822e+06 5903.22 0.06 0.85 0.22 -1 -1 0.06 0.50277 0.462472 + k6_frac_N10_40nm.xml s298.blif common 6.89 vpr 61.61 MiB -1 -1 -1 -1 8 0.90 -1 -1 33640 -1 -1 61 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63092 4 6 671 677 1 350 71 10 10 100 clb auto 22.3 MiB 1.13 3495 3137 432 2529 176 61.6 MiB 0.13 0.00 5.3014 -43.7499 -5.3014 5.3014 0.10 0.00213324 0.00193977 0.0653912 0.0590662 -1 -1 -1 -1 54 5597 27 3.44922e+06 3.28753e+06 316276. 3162.76 2.70 0.969741 0.854177 10312 63908 -1 5157 17 2266 11525 327366 61505 5.48392 5.48392 -46.8399 -5.48392 0 0 411339. 4113.39 0.02 0.24 0.06 -1 -1 0.02 0.132836 0.122294 + k6_frac_N10_40nm.xml s38417.blif common 19.91 vpr 78.25 MiB -1 -1 -1 -1 6 4.38 -1 -1 42652 -1 -1 176 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80128 29 106 3450 3556 1 1190 311 16 16 256 clb auto 37.0 MiB 2.32 8949 65597 16026 43107 6464 78.2 MiB 1.45 0.02 4.50231 -2905.37 -4.50231 4.50231 0.31 0.013459 0.0123921 0.819893 0.68577 -1 -1 -1 -1 46 15732 39 1.05632e+07 9.48534e+06 786978. 3074.13 7.54 3.76391 3.16115 26604 162157 -1 13635 14 5142 17426 519616 106370 4.53102 4.53102 -2987.6 -4.53102 0 0 1.01084e+06 3948.58 0.05 0.64 0.15 -1 -1 0.05 0.491437 0.438055 + k6_frac_N10_40nm.xml s38584.1.blif common 19.73 vpr 78.57 MiB -1 -1 -1 -1 6 3.21 -1 -1 40768 -1 -1 203 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80452 38 304 3259 3563 1 1559 545 17 17 289 clb auto 37.4 MiB 3.40 10446 174095 49766 105233 19096 78.6 MiB 2.06 0.03 4.29015 -2399.8 -4.29015 4.29015 0.36 0.0108513 0.0100424 0.949535 0.807306 -1 -1 -1 -1 58 17767 23 1.21262e+07 1.09405e+07 1.11519e+06 3858.79 6.55 4.0366 3.46133 32499 230706 -1 16008 15 5250 14700 516522 110817 4.81093 4.81093 -2541.32 -4.81093 0 0 1.41877e+06 4909.24 0.08 0.69 0.21 -1 -1 0.08 0.542118 0.483109 + k6_frac_N10_40nm.xml tseng.blif common 4.86 vpr 60.55 MiB -1 -1 -1 -1 7 0.56 -1 -1 34224 -1 -1 33 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62000 52 122 664 786 1 358 207 8 8 64 io clb auto 20.9 MiB 0.71 1908 22239 4478 16280 1481 60.5 MiB 0.19 0.01 4.25559 -597.466 -4.25559 4.25559 0.07 0.00207961 0.0019366 0.0799798 0.0739686 -1 -1 -1 -1 58 3323 26 1.94018e+06 1.7785e+06 203254. 3175.84 1.37 0.640949 0.573504 6532 39661 -1 2850 14 1079 2916 89573 24965 4.64398 4.64398 -644.298 -4.64398 0 0 258247. 4035.11 0.01 0.11 0.03 -1 -1 0.01 0.0836637 0.0773858 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt index 2c1e5143a34..594c4215910 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.48 vpr 64.32 MiB -1 -1 0.08 20608 1 0.04 -1 -1 35284 -1 -1 2 6 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65868 6 1 13 14 2 8 9 4 4 16 clb auto 26.0 MiB 0.00 15 27 4 16 7 64.3 MiB 0.00 0.00 0.876768 -3.25729 -0.876768 0.545 0.01 4.3317e-05 3.4454e-05 0.000280058 0.000232486 20 18 16 107788 107788 10441.3 652.579 0.01 0.00200757 0.00171843 742 1670 -1 18 2 7 7 153 93 1.4073 0.545 -4.29789 -1.4073 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00115658 0.00109103 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.51 vpr 64.29 MiB -1 -1 0.08 20864 1 0.04 -1 -1 35208 -1 -1 2 3 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65828 3 -1 23 23 2 3 5 4 4 16 clb auto 25.9 MiB 0.01 2 12 2 3 7 64.3 MiB 0.00 0.00 0.545 -7.62503 -0.545 0.545 0.01 5.9477e-05 5.1394e-05 0.000445997 0.000401154 8 1 1 107788 107788 4888.88 305.555 0.02 0.00275649 0.00249621 622 902 -1 1 1 1 1 9 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.00 0.00 -1 -1 0.00 0.00158614 0.00151091 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 0.42 vpr 64.03 MiB -1 -1 0.06 20352 1 0.01 -1 -1 33064 -1 -1 1 3 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65568 3 1 5 6 1 4 5 3 3 9 -1 auto 25.8 MiB 0.00 6 12 8 0 4 64.0 MiB 0.00 0.00 0.544641 -0.918653 -0.544641 0.544641 0.00 2.3999e-05 2.0452e-05 0.000114281 9.2013e-05 20 5 1 53894 53894 4880.82 542.314 0.00 0.00099982 0.000925813 379 725 -1 17 1 3 3 68 57 1.45014 1.45014 -1.99566 -1.45014 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000913044 0.000879537 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.77 MiB -1 -1 0.12 16500 1 0.10 -1 -1 31836 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63252 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.8 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.6498e-05 2.6643e-05 0.000260655 0.000218319 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00250948 0.00220504 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00176399 0.00169239 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.09 vpr 61.68 MiB -1 -1 0.15 16776 1 0.07 -1 -1 31648 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63160 3 -1 23 23 2 3 5 4 4 16 clb auto 23.2 MiB 0.01 3 12 2 3 7 61.7 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.5504e-05 5.6164e-05 0.000543565 0.00049453 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00311117 0.00290556 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.01 0.00 -1 -1 0.00 0.00221081 0.00210995 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 10 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 22 1 3 3 79 69 1.8363 1.8363 -2.38182 -1.8363 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt index 33cdd16f53c..248d5d735f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 0.57 vpr 64.32 MiB -1 -1 0.07 20096 1 0.04 -1 -1 35412 -1 -1 2 6 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65864 6 1 13 14 2 8 9 4 4 16 clb auto 25.9 MiB 0.00 15 27 4 16 7 64.3 MiB 0.00 0.00 0.876768 -3.25729 -0.876768 0.545 0.01 3.822e-05 2.8683e-05 0.0002492 0.000209176 20 18 16 107788 107788 10441.3 652.579 0.01 0.0019759 0.00167615 742 1670 -1 18 2 7 7 153 93 1.4073 0.545 -4.29789 -1.4073 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00115121 0.00108599 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 0.57 vpr 64.39 MiB -1 -1 0.09 20480 1 0.04 -1 -1 35548 -1 -1 1 2 0 0 success v8.0.0-9278-g8174f522c9-dirty release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.2.0-37-generic x86_64 2023-12-25T17:01:11 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65932 2 -1 16 16 1 2 3 3 3 9 -1 auto 26.1 MiB 0.01 2 6 3 0 3 64.4 MiB 0.00 0.00 0.545 -3.815 -0.545 0.545 0.00 4.0902e-05 3.4981e-05 0.000354436 0.000323261 2 1 1 53894 53894 1178.84 130.982 0.01 0.00253626 0.00228473 283 309 -1 1 1 1 1 9 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00134392 0.00129235 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.64 MiB -1 -1 0.11 16584 1 0.10 -1 -1 31848 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63124 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.6 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 4.0075e-05 2.932e-05 0.00026592 0.0002219 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00240468 0.00215628 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00168822 0.00161939 + k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.11 vpr 61.76 MiB -1 -1 0.14 16908 1 0.09 -1 -1 31852 -1 -1 1 2 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63240 2 -1 16 16 1 2 3 3 3 9 -1 auto 23.3 MiB 0.01 3 6 4 0 2 61.8 MiB 0.01 0.00 0.545 -3.815 -0.545 0.545 0.01 6.1203e-05 5.2668e-05 0.000507564 0.000460754 -1 -1 -1 -1 2 1 1 53894 53894 1178.84 130.982 0.01 0.00295561 0.00280974 283 309 -1 1 1 1 1 8 6 0.551715 0.551715 -3.84186 -0.551715 0 0 1178.84 130.982 0.00 0.00 0.00 -1 -1 0.00 0.00212103 0.00204508 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt index 039f772d88f..e9d880c30a2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 11.99 vpr 255.45 MiB 0.11 36912 -1 -1 1 0.05 -1 -1 34700 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261584 6 1 13 14 2 8 9 4 4 16 clb auto 101.0 MiB 0.11 13 244.4 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000264546 0.000241337 0.00754986 0.00454282 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136677 0.00891098 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00722654 0.00593545 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 12.96 vpr 261.56 MiB 0.15 45980 -1 -1 1 0.06 -1 -1 34932 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 267836 3 1 25 26 2 8 6 4 4 16 clb auto 106.4 MiB 0.87 17 249.9 MiB 0.03 0 0.571 -8.64803 -0.571 0.557849 0.47 0.000543454 0.000488368 0.00346482 0.00253954 20 19 1 107788 107788 10441.3 652.579 0.67 0.0113116 0.00855232 742 1670 -1 27 1 6 6 63 36 0 0 63 36 6 6 0 0 9 6 0 0 9 9 0 0 6 6 0 0 18 3 0 0 15 6 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.82275 -0.865 0 0 13748.8 859.301 0.01 0.04 0.17 -1 -1 0.01 0.00501901 0.00409753 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 11.88 vpr 254.22 MiB 0.15 35980 -1 -1 1 0 -1 -1 32420 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260320 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000504445 0.000240584 0.00477542 0.00228264 20 15 1 107788 107788 10441.3 652.579 0.64 0.00804976 0.00416003 742 1670 -1 13 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00215701 0.00121245 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 11.88 vpr 254.22 MiB 0.15 35980 -1 -1 1 0 -1 -1 32420 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260320 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000504445 0.000240584 0.00477542 0.00228264 20 27 1 107788 107788 10441.3 652.579 0.64 0.00804976 0.00416003 742 1670 -1 13 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00215701 0.00121245 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc/config/golden_results.txt index dabe58c85d0..9a02931e25d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml bigkey.blif common 5.28 -1 -1 3 0.34 -1 -1 35056 -1 -1 53 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 46028 229 197 1023 1220 1 510 479 16 16 256 io auto 0.21 3413 0.56 0.00 2.1735 -526.299 -2.1735 2.1735 0.39 0.00138821 0.00120378 0.19781 0.168309 40 6116 17 1.05632e+07 2.85638e+06 697968. 2726.44 2.40 0.722292 0.640772 5568 9 1309 2279 135603 31763 2.49868 2.49868 -621.799 -2.49868 0 0 870840. 3401.72 0.16 0.07 0.0510449 0.0478126 -k6_frac_N10_40nm.xml clma.blif common 5.08 -1 -1 7 2.05 -1 -1 39340 -1 -1 77 36 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 32676 36 82 542 624 1 390 195 11 11 121 clb auto 0.35 2039 0.33 0.00 4.11584 -147.948 -4.11584 4.11584 0.15 0.000539492 0.000452693 0.106625 0.0857617 40 4434 24 4.36541e+06 4.14984e+06 303235. 2506.08 1.15 0.303278 0.252285 3724 17 2001 6967 214647 45904 4.75061 4.75061 -182.205 -4.75061 0 0 379421. 3135.71 0.06 0.06 0.0359416 0.0326671 -k6_frac_N10_40nm.xml diffeq.blif common 3.20 -1 -1 8 0.40 -1 -1 34060 -1 -1 51 64 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 34940 64 39 941 980 1 450 154 10 10 100 clb auto 0.42 2664 0.24 0.00 4.29897 -783.884 -4.29897 4.29897 0.12 0.000839617 0.000669735 0.100486 0.0795009 46 5017 28 3.44922e+06 2.74859e+06 276332. 2763.32 1.05 0.326802 0.269909 4217 16 1848 5381 166684 35585 4.95374 4.95374 -932.485 -4.95374 0 0 354105. 3541.05 0.05 0.08 0.0542635 0.0494947 -k6_frac_N10_40nm.xml dsip.blif common 6.16 -1 -1 3 0.30 -1 -1 34940 -1 -1 68 229 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 47348 229 197 1135 1332 1 648 494 16 16 256 io auto 0.53 4829 0.66 0.01 2.11998 -540.899 -2.11998 2.11998 0.39 0.0015698 0.00130015 0.210921 0.176933 36 9346 20 1.05632e+07 3.66479e+06 638738. 2495.07 2.79 0.723593 0.631411 8188 14 2350 5770 322638 68924 2.64997 2.64997 -662.41 -2.64997 0 0 786978. 3074.13 0.15 0.12 0.076965 0.0713829 -k6_frac_N10_40nm.xml elliptic.blif common 10.48 -1 -1 10 1.16 -1 -1 37272 -1 -1 133 131 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 56752 131 114 2471 2585 1 967 378 14 14 196 clb auto 1.84 9009 0.83 0.01 6.26362 -3059.17 -6.26362 6.26362 0.28 0.00212795 0.00173305 0.286733 0.219064 64 15845 47 7.76074e+06 7.1679e+06 810706. 4136.26 4.27 1.22946 1.00099 14220 16 4723 20791 818717 140043 7.05815 7.05815 -3531.55 -7.05815 0 0 1.00880e+06 5146.95 0.16 0.27 0.154401 0.13779 -k6_frac_N10_40nm.xml frisc.blif common 13.84 -1 -1 12 1.91 -1 -1 37256 -1 -1 153 20 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 62524 20 116 2477 2593 1 1097 289 15 15 225 clb auto 2.14 12755 0.94 0.01 6.79269 -3257.02 -6.79269 6.79269 0.34 0.00217438 0.00179657 0.327538 0.24583 76 21374 38 9.10809e+06 8.24578e+06 1.08042e+06 4801.85 6.09 1.27911 1.034 19100 16 5620 24310 1037891 171913 8.29693 8.29693 -3979.77 -8.29693 0 0 1.34805e+06 5991.31 0.22 0.35 0.179872 0.160752 -k6_frac_N10_40nm.xml s298.blif common 3.83 -1 -1 8 0.53 -1 -1 34316 -1 -1 62 4 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 34504 4 6 671 677 1 352 72 10 10 100 clb auto 0.56 3591 0.22 0.00 4.75477 -39.1418 -4.75477 4.75477 0.12 0.000769266 0.000586248 0.09084 0.0707559 52 5575 27 3.44922e+06 3.34143e+06 305142. 3051.42 1.47 0.36114 0.295188 5399 17 2374 11722 416659 74881 5.56322 5.56322 -46.7971 -5.56322 0 0 401807. 4018.07 0.06 0.11 0.0543908 0.049368 -k6_frac_N10_40nm.xml s38417.blif common 12.03 -1 -1 6 2.75 -1 -1 42360 -1 -1 177 29 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 63792 29 106 3450 3556 1 1202 312 16 16 256 clb auto 1.56 8615 1.15 0.01 3.98518 -2557.22 -3.98518 3.98518 0.39 0.00302166 0.00218012 0.456703 0.332458 46 14847 24 1.05632e+07 9.53924e+06 786978. 3074.13 3.52 1.37805 1.08296 13205 15 5027 16599 520957 107073 4.83175 4.83175 -2954.7 -4.83175 0 0 1.01084e+06 3948.58 0.17 0.30 0.238471 0.215337 -k6_frac_N10_40nm.xml s38584.1.blif common 12.46 -1 -1 6 2.08 -1 -1 40804 -1 -1 194 38 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 66920 38 304 3256 3560 1 1587 536 16 16 256 clb auto 1.98 10122 1.65 0.01 3.64177 -2138.5 -3.64177 3.64177 0.40 0.00317473 0.00262755 0.578661 0.434442 58 18006 25 1.05632e+07 1.04554e+07 977637. 3818.90 3.81 1.57474 1.25106 15785 16 5100 13564 505628 106920 4.7203 4.7203 -2481.9 -4.7203 0 0 1.24374e+06 4858.37 0.21 0.26 0.211794 0.191547 -k6_frac_N10_40nm.xml tseng.blif common 2.48 -1 -1 7 0.23 -1 -1 34700 -1 -1 34 52 -1 -1 success v8.0.0-3535-ge4ce792ea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-05-17T19:06:09 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests 31260 52 122 664 786 1 355 208 8 8 64 io clb auto 0.41 1686 0.21 0.00 3.70214 -536.987 -3.70214 3.70214 0.07 0.000641877 0.000544632 0.0739312 0.060713 58 3324 47 1.94018e+06 1.8324e+06 203254. 3175.84 0.73 0.26935 0.22784 2902 11 1075 2671 103928 28289 4.55633 4.55633 -641.099 -4.55633 0 0 258247. 4035.11 0.04 0.07 0.046514 0.0424413 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common 7.20 vpr 66.95 MiB -1 -1 -1 -1 3 0.52 -1 -1 38552 -1 -1 53 229 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68552 229 197 1023 1220 1 510 479 16 16 256 io auto 27.5 MiB 0.24 3857 159684 50415 100566 8703 66.9 MiB 0.65 0.01 2.28488 -572.083 -2.28488 2.28488 0.43 0.00217367 0.00193462 0.259289 0.232202 -1 -1 -1 -1 34 6784 36 1.05632e+07 2.85638e+06 613832. 2397.78 4.05 1.01365 0.918671 24564 122629 -1 5850 11 1312 2352 132518 32277 2.76257 2.76257 -655.553 -2.76257 0 0 751777. 2936.63 0.03 0.09 0.08 -1 -1 0.03 0.069929 0.0656002 + k6_frac_N10_40nm.xml clma.blif common 5.94 vpr 64.80 MiB -1 -1 -1 -1 7 2.23 -1 -1 42980 -1 -1 79 36 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66352 36 82 542 624 1 389 197 11 11 121 clb auto 25.3 MiB 0.48 2127 40880 16866 18710 5304 64.8 MiB 0.32 0.01 4.57111 -169.888 -4.57111 4.57111 0.20 0.00196234 0.001766 0.116536 0.103509 -1 -1 -1 -1 40 4700 26 4.36541e+06 4.25763e+06 303235. 2506.08 1.35 0.43712 0.38801 11571 60661 -1 3777 19 2230 7887 214455 46253 4.82804 4.82804 -186.1 -4.82804 0 0 379421. 3135.71 0.02 0.16 0.07 -1 -1 0.02 0.0896115 0.0822627 + k6_frac_N10_40nm.xml diffeq.blif common 2.92 vpr 66.61 MiB -1 -1 -1 -1 8 0.37 -1 -1 38160 -1 -1 52 64 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68208 64 39 941 980 1 449 155 10 10 100 clb auto 26.8 MiB 0.50 2810 15963 3441 11602 920 66.6 MiB 0.14 0.00 4.99118 -866.838 -4.99118 4.99118 0.09 0.00121728 0.00102812 0.0599001 0.0516492 -1 -1 -1 -1 46 4616 20 3.44922e+06 2.80249e+06 276332. 2763.32 0.93 0.392993 0.343157 9816 55112 -1 4188 15 1800 5546 151236 33167 5.08131 5.08131 -922.585 -5.08131 0 0 354105. 3541.05 0.01 0.11 0.04 -1 -1 0.01 0.0801531 0.0743673 + k6_frac_N10_40nm.xml dsip.blif common 8.04 vpr 68.18 MiB -1 -1 -1 -1 3 0.46 -1 -1 38252 -1 -1 68 229 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69816 229 197 1135 1332 1 648 494 16 16 256 io auto 28.6 MiB 0.85 5312 156654 46092 101923 8639 68.2 MiB 0.99 0.01 2.37422 -599.955 -2.37422 2.37422 0.49 0.00367277 0.00324389 0.347682 0.309361 -1 -1 -1 -1 36 8936 22 1.05632e+07 3.66479e+06 638738. 2495.07 3.13 1.35387 1.20985 24820 128426 -1 8053 12 2277 5560 281512 63324 2.6192 2.6192 -669.375 -2.6192 0 0 786978. 3074.13 0.05 0.25 0.18 -1 -1 0.05 0.157791 0.147117 + k6_frac_N10_40nm.xml elliptic.blif common 11.55 vpr 75.93 MiB -1 -1 -1 -1 10 1.41 -1 -1 42312 -1 -1 134 131 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77748 131 114 2471 2585 1 965 379 14 14 196 clb auto 35.1 MiB 2.51 9456 89494 25858 59393 4243 75.9 MiB 0.77 0.01 6.79623 -3397.75 -6.79623 6.79623 0.20 0.00440022 0.00362715 0.301337 0.256198 -1 -1 -1 -1 66 15578 22 7.76074e+06 7.2218e+06 836700. 4268.88 4.49 1.74713 1.51878 22640 168496 -1 13700 18 4265 18260 614637 108468 7.3276 7.3276 -3617 -7.3276 0 0 1.03533e+06 5282.27 0.04 0.41 0.14 -1 -1 0.04 0.267713 0.242444 + k6_frac_N10_40nm.xml frisc.blif common 16.16 vpr 77.31 MiB -1 -1 -1 -1 12 2.01 -1 -1 42652 -1 -1 154 20 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79164 20 116 2477 2593 1 1095 290 15 15 225 clb auto 36.4 MiB 3.95 13105 58789 14981 39464 4344 77.3 MiB 1.35 0.02 8.00138 -3807.11 -8.00138 8.00138 0.43 0.0081328 0.00719848 0.558575 0.477365 -1 -1 -1 -1 76 21862 33 9.10809e+06 8.29968e+06 1.08042e+06 4801.85 5.74 1.98425 1.72803 27499 221939 -1 19174 16 5769 25045 1026308 173738 8.21541 8.21541 -3991.17 -8.21541 0 0 1.34805e+06 5991.31 0.05 0.46 0.18 -1 -1 0.05 0.251615 0.230637 + k6_frac_N10_40nm.xml s298.blif common 4.60 vpr 65.82 MiB -1 -1 -1 -1 8 0.82 -1 -1 37972 -1 -1 61 4 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67404 4 6 671 677 1 350 71 10 10 100 clb auto 26.5 MiB 1.11 3540 2845 401 2327 117 65.8 MiB 0.12 0.00 5.48084 -44.2852 -5.48084 5.48084 0.16 0.00206735 0.00177304 0.0590776 0.0525925 -1 -1 -1 -1 52 5763 37 3.44922e+06 3.28753e+06 305142. 3051.42 1.18 0.421351 0.369249 10212 61796 -1 5098 18 2211 10437 290027 55717 5.61219 5.61219 -47.3284 -5.61219 0 0 401807. 4018.07 0.01 0.15 0.05 -1 -1 0.01 0.0927923 0.0846279 + k6_frac_N10_40nm.xml s38417.blif common 17.91 vpr 81.74 MiB -1 -1 -1 -1 6 4.10 -1 -1 45508 -1 -1 176 29 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83700 29 106 3450 3556 1 1190 311 16 16 256 clb auto 40.6 MiB 2.62 8975 59279 14510 38832 5937 81.7 MiB 1.37 0.02 4.49038 -2868.52 -4.49038 4.49038 0.48 0.0101802 0.00890923 0.68275 0.55608 -1 -1 -1 -1 48 14949 25 1.05632e+07 9.48534e+06 819368. 3200.65 6.19 3.10939 2.62069 26860 167058 -1 13109 14 4799 16110 475247 99748 4.67678 4.67678 -2975.81 -4.67678 0 0 1.04748e+06 4091.72 0.04 0.38 0.13 -1 -1 0.04 0.295567 0.270634 + k6_frac_N10_40nm.xml s38584.1.blif common 17.99 vpr 82.03 MiB -1 -1 -1 -1 6 3.06 -1 -1 44604 -1 -1 203 38 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83996 38 304 3259 3563 1 1559 545 17 17 289 clb auto 41.0 MiB 3.38 10700 171870 46563 105348 19959 82.0 MiB 2.17 0.02 4.2184 -2435.96 -4.2184 4.2184 0.56 0.0059931 0.00531266 0.863249 0.745275 -1 -1 -1 -1 56 19548 40 1.21262e+07 1.09405e+07 1.07492e+06 3719.43 5.63 3.22677 2.77835 31923 220089 -1 16589 15 5335 14804 532142 114643 4.62993 4.62993 -2587.89 -4.62993 0 0 1.37091e+06 4743.65 0.05 0.41 0.17 -1 -1 0.05 0.315014 0.290558 + k6_frac_N10_40nm.xml tseng.blif common 3.72 vpr 64.95 MiB -1 -1 -1 -1 7 0.30 -1 -1 36976 -1 -1 33 52 -1 -1 success v8.0.0-12164-g463dd1c36-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-20T15:42:53 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66504 52 122 664 786 1 358 207 8 8 64 io clb auto 25.4 MiB 0.60 1979 19791 3963 14597 1231 64.9 MiB 0.21 0.01 4.35959 -604.543 -4.35959 4.35959 0.09 0.00213824 0.00191283 0.0821371 0.0733419 -1 -1 -1 -1 58 3402 44 1.94018e+06 1.7785e+06 203254. 3175.84 1.42 0.631719 0.559346 6532 39661 -1 2996 15 1183 3162 100447 27815 4.60411 4.60411 -641.316 -4.60411 0 0 258247. 4035.11 0.01 0.12 0.05 -1 -1 0.01 0.0870702 0.080662 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt index b9631c0caf9..564cc8c3dc6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.22 vpr 254.93 MiB 0.1 37000 -1 -1 1 0.05 -1 -1 34808 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261052 6 1 13 14 2 8 9 4 4 16 clb auto 100.7 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000263443 0.000240838 0.00748415 0.00450484 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136082 0.00886525 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00739705 0.00603502 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 14.79 vpr 261.44 MiB 0.12 46076 -1 -1 1 0.05 -1 -1 34892 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 267712 3 1 25 26 2 8 6 4 4 16 clb auto 106.3 MiB 1 17 250.0 MiB 0.04 0 0.571 -8.64803 -0.571 0.557849 0.53 0.000560438 0.000505834 0.00360459 0.00262507 20 19 1 107788 107788 10441.3 652.579 0.76 0.0119539 0.00893362 742 1670 -1 27 1 6 6 63 36 0 0 63 36 6 6 0 0 9 6 0 0 9 9 0 0 6 6 0 0 18 3 0 0 15 6 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.82275 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00502268 0.00406987 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.05 vpr 254.23 MiB 0.11 35864 -1 -1 1 0.01 -1 -1 32648 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260328 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000489919 0.000226814 0.00463432 0.00218307 20 15 1 107788 107788 10441.3 652.579 0.64 0.00773058 0.00396899 742 1670 -1 13 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00224126 0.00124363 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.05 vpr 254.23 MiB 0.11 35864 -1 -1 1 0.01 -1 -1 32648 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260328 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000489919 0.000226814 0.00463432 0.00218307 20 27 1 107788 107788 10441.3 652.579 0.64 0.00773058 0.00396899 742 1670 -1 13 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00224126 0.00124363 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/task_list.txt index 5c3e9b08ebb..53cfaf40acf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/task_list.txt @@ -1,5 +1,5 @@ regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket -regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket_odin +regression_tests/vtr_reg_multiclock_odin/func_multiclock/multiclock_mcnc regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative regression_tests/vtr_reg_multiclock_odin/func_multiclock/once regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt index 5c9945e3546..99080e3a8c6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt @@ -1,211 +1,211 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 2.74 vpr 60.62 MiB -1 -1 0.15 17236 2 0.06 -1 -1 31940 -1 -1 2 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62076 9 5 28 33 1 21 16 17 17 289 -1 unnamed_device 22.0 MiB 0.01 135 76 35 40 1 60.6 MiB 0.00 0.00 0.900447 -11.7037 -0.900447 0.900447 0.66 8.645e-05 7.8124e-05 0.000583333 0.000531116 20 236 9 6.55708e+06 24110 394039. 1363.46 0.45 0.00366263 0.00324976 19870 87366 -1 236 7 61 67 5096 1298 0.83871 0.83871 -12.1586 -0.83871 0 0 477104. 1650.88 0.14 0.01 0.08 -1 -1 0.14 0.00258961 0.00232587 13 6 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.94 vpr 60.76 MiB -1 -1 0.14 17160 2 0.06 -1 -1 32004 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62220 11 6 34 40 1 24 19 17 17 289 -1 unnamed_device 22.1 MiB 0.01 55 569 131 359 79 60.8 MiB 0.01 0.00 0.900447 -11.5834 -0.900447 0.900447 0.65 0.00010434 9.5102e-05 0.00271084 0.00247011 26 205 12 6.55708e+06 24110 477104. 1650.88 0.56 0.0146662 0.0123484 21022 109990 -1 188 9 116 121 5329 1929 0.819447 0.819447 -12.7928 -0.819447 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00323617 0.00286903 16 7 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 2.81 vpr 60.62 MiB -1 -1 0.16 17216 3 0.05 -1 -1 31852 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62072 13 7 41 48 1 32 23 17 17 289 -1 unnamed_device 22.0 MiB 0.02 85 567 111 433 23 60.6 MiB 0.01 0.00 1.58811 -16.0101 -1.58811 1.58811 0.66 0.000125009 0.000114627 0.00264833 0.00243277 20 282 10 6.55708e+06 36165 394039. 1363.46 0.45 0.00862391 0.00785706 19870 87366 -1 238 10 108 128 6200 1949 1.50711 1.50711 -17.0526 -1.50711 0 0 477104. 1650.88 0.14 0.01 0.08 -1 -1 0.14 0.00386995 0.00340331 19 9 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.81 vpr 60.71 MiB -1 -1 0.15 17060 3 0.05 -1 -1 31872 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62172 15 8 47 55 1 38 26 17 17 289 -1 unnamed_device 22.0 MiB 0.01 208 862 165 657 40 60.7 MiB 0.01 0.00 1.23151 -19.784 -1.23151 1.23151 0.67 0.000144141 0.000132564 0.00370168 0.00340074 20 451 13 6.55708e+06 36165 394039. 1363.46 0.45 0.00903024 0.00801953 19870 87366 -1 409 8 146 164 9675 2532 1.05785 1.05785 -21.0828 -1.05785 0 0 477104. 1650.88 0.14 0.01 0.08 -1 -1 0.14 0.00383752 0.00340253 23 10 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.01 vpr 60.81 MiB -1 -1 0.12 17156 3 0.05 -1 -1 31920 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62268 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 22.1 MiB 0.05 126 720 180 518 22 60.8 MiB 0.01 0.00 1.70831 -21.3388 -1.70831 1.70831 0.67 0.000172392 0.000158744 0.00325091 0.00300139 26 341 10 6.55708e+06 48220 477104. 1650.88 0.58 0.0213417 0.017943 21022 109990 -1 308 11 131 145 7970 2470 1.58811 1.58811 -22.2734 -1.58811 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00523909 0.004569 25 14 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.13 vpr 61.11 MiB -1 -1 0.14 17116 4 0.05 -1 -1 31968 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62576 19 10 60 70 1 48 33 17 17 289 -1 unnamed_device 22.4 MiB 0.02 138 1593 371 925 297 61.1 MiB 0.02 0.00 1.58811 -24.9956 -1.58811 1.58811 0.66 0.00018571 0.000171683 0.00622386 0.00574361 30 399 18 6.55708e+06 48220 526063. 1820.29 0.66 0.0278424 0.0236006 21886 126133 -1 284 8 179 216 8061 2693 1.50711 1.50711 -23.7908 -1.50711 0 0 666494. 2306.21 0.19 0.01 0.11 -1 -1 0.19 0.00473893 0.0041935 29 13 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 4.03 vpr 60.91 MiB -1 -1 0.16 17260 4 0.06 -1 -1 31804 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62372 21 11 69 80 1 54 37 17 17 289 -1 unnamed_device 22.4 MiB 0.06 171 2965 791 1478 696 60.9 MiB 0.02 0.00 1.74751 -28.6395 -1.74751 1.74751 0.67 0.000207694 0.000192004 0.0107634 0.00994613 22 811 29 6.55708e+06 60275 420624. 1455.45 1.56 0.0517123 0.0436832 20158 92377 -1 540 10 251 342 20280 6103 1.62731 1.62731 -31.7476 -1.62731 0 0 500653. 1732.36 0.15 0.02 0.09 -1 -1 0.15 0.00574609 0.00502617 33 17 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.14 vpr 60.95 MiB -1 -1 0.16 17272 5 0.06 -1 -1 31920 -1 -1 6 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62412 23 12 76 88 1 61 41 17 17 289 -1 unnamed_device 22.4 MiB 0.02 238 4031 1480 1575 976 60.9 MiB 0.03 0.00 2.07857 -33.1668 -2.07857 2.07857 0.71 0.000224038 0.00020653 0.0136882 0.0126411 28 584 15 6.55708e+06 72330 500653. 1732.36 0.63 0.0387169 0.0335188 21310 115450 -1 529 13 230 289 18701 4954 1.7455 1.7455 -33.8966 -1.7455 0 0 612192. 2118.31 0.18 0.02 0.10 -1 -1 0.18 0.00707647 0.00615885 37 19 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.05 vpr 60.94 MiB -1 -1 0.17 17472 5 0.06 -1 -1 31972 -1 -1 6 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62400 25 13 83 96 1 66 44 17 17 289 -1 unnamed_device 22.5 MiB 0.02 377 3894 1439 2026 429 60.9 MiB 0.03 0.00 1.80097 -39.3305 -1.80097 1.80097 0.67 0.000245713 0.000227127 0.0131117 0.0121218 26 788 14 6.55708e+06 72330 477104. 1650.88 0.61 0.0394861 0.0342105 21022 109990 -1 751 16 314 450 35118 8247 1.77504 1.77504 -42.0175 -1.77504 0 0 585099. 2024.56 0.17 0.02 0.10 -1 -1 0.17 0.00872282 0.0075648 40 21 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.30 vpr 61.05 MiB -1 -1 0.12 17516 5 0.06 -1 -1 31788 -1 -1 7 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62520 27 14 91 105 1 70 48 17 17 289 -1 unnamed_device 22.5 MiB 0.02 268 2832 643 1749 440 61.1 MiB 0.02 0.00 1.74751 -36.363 -1.74751 1.74751 0.74 0.000271359 0.000251479 0.00969306 0.00898067 26 762 34 6.55708e+06 84385 477104. 1650.88 0.71 0.0479897 0.0409888 21022 109990 -1 661 16 290 427 42857 13493 1.53665 1.53665 -38.6649 -1.53665 0 0 585099. 2024.56 0.17 0.03 0.10 -1 -1 0.17 0.00953989 0.00824962 42 24 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.13 vpr 61.13 MiB -1 -1 0.16 17524 6 0.06 -1 -1 32148 -1 -1 7 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62600 29 15 95 110 1 74 51 17 17 289 -1 unnamed_device 22.6 MiB 0.04 461 5503 1446 3252 805 61.1 MiB 0.04 0.00 2.47436 -49.4238 -2.47436 2.47436 0.66 0.000279667 0.000258883 0.0172866 0.0160272 26 940 26 6.55708e+06 84385 477104. 1650.88 0.64 0.0530306 0.0459924 21022 109990 -1 852 12 295 406 27209 6503 2.23396 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62628 37 19 127 146 1 99 66 17 17 289 -1 unnamed_device 22.5 MiB 0.03 520 5519 1325 3449 745 61.2 MiB 0.04 0.00 3.12482 -68.231 -3.12482 3.12482 0.66 0.000366828 0.000340613 0.0162433 0.0150584 28 1061 11 6.55708e+06 120550 500653. 1732.36 0.65 0.0541799 0.0472377 21310 115450 -1 962 9 299 403 23764 6046 2.79176 2.79176 -68.6483 -2.79176 0 0 612192. 2118.31 0.18 0.03 0.10 -1 -1 0.18 0.0101929 0.00901767 59 35 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 3.22 vpr 61.16 MiB -1 -1 0.17 17408 8 0.06 -1 -1 32016 -1 -1 11 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62632 41 21 139 160 1 110 73 17 17 289 -1 unnamed_device 22.5 MiB 0.05 468 9497 2136 5919 1442 61.2 MiB 0.06 0.00 3.11516 -75.6589 -3.11516 3.11516 0.65 0.000398342 0.000369999 0.0261698 0.0243142 26 1200 13 6.55708e+06 132605 477104. 1650.88 0.68 0.0685837 0.0604621 21022 109990 -1 1055 11 406 541 31085 8462 2.9023 2.9023 -77.3553 -2.9023 0 0 585099. 2024.56 0.17 0.03 0.10 -1 -1 0.17 0.0106512 0.00938817 67 37 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 4.89 vpr 61.29 MiB -1 -1 0.18 17472 9 0.07 -1 -1 31956 -1 -1 13 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62760 45 23 153 176 1 123 81 17 17 289 -1 unnamed_device 22.5 MiB 0.21 636 10406 4261 6108 37 61.3 MiB 0.06 0.00 3.15236 -84.0115 -3.15236 3.15236 0.66 0.000433887 0.000402031 0.0271458 0.0251881 30 1243 13 6.55708e+06 156715 526063. 1820.29 2.09 0.137701 0.119279 21886 126133 -1 1121 13 401 514 24209 6555 3.0597 3.0597 -84.1453 -3.0597 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0126038 0.0110916 74 41 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 4.96 vpr 61.43 MiB -1 -1 0.19 17552 10 0.07 -1 -1 31968 -1 -1 12 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62904 49 25 166 191 1 129 86 17 17 289 -1 unnamed_device 22.7 MiB 0.09 684 7457 1697 4897 863 61.4 MiB 0.05 0.00 3.70816 -98.1534 -3.70816 3.70816 0.65 0.000469331 0.000436345 0.0199461 0.0185434 28 1493 34 6.55708e+06 144660 500653. 1732.36 2.28 0.135027 0.1168 21310 115450 -1 1272 12 423 577 35128 9092 3.58796 3.58796 -99.0644 -3.58796 0 0 612192. 2118.31 0.18 0.03 0.10 -1 -1 0.18 0.0133462 0.0118212 79 44 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.88 vpr 61.52 MiB -1 -1 0.16 17464 11 0.08 -1 -1 32180 -1 -1 14 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62992 57 29 198 227 1 159 100 17 17 289 -1 unnamed_device 23.0 MiB 0.18 886 14020 4097 8043 1880 61.5 MiB 0.08 0.00 4.12928 -123.627 -4.12928 4.12928 0.66 0.000569495 0.00052983 0.0360377 0.0335206 28 1846 13 6.55708e+06 168770 500653. 1732.36 2.10 0.162815 0.142082 21310 115450 -1 1677 11 546 710 49330 11707 3.87722 3.87722 -125.497 -3.87722 0 0 612192. 2118.31 0.18 0.04 0.10 -1 -1 0.18 0.0155799 0.013858 93 56 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 3.79 vpr 61.71 MiB -1 -1 0.21 17756 13 0.08 -1 -1 32116 -1 -1 16 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63188 65 33 224 257 1 180 114 17 17 289 -1 unnamed_device 23.1 MiB 0.22 826 13362 2721 10353 288 61.7 MiB 0.08 0.00 4.35602 -142.897 -4.35602 4.35602 0.65 0.000640239 0.000596542 0.032983 0.0307208 30 1923 15 6.55708e+06 192880 526063. 1820.29 0.88 0.103373 0.0916773 21886 126133 -1 1661 11 677 907 51084 13514 4.02296 4.02296 -140.256 -4.02296 0 0 666494. 2306.21 0.19 0.04 0.11 -1 -1 0.19 0.0164996 0.0146991 107 62 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 6.46 vpr 62.64 MiB -1 -1 0.26 18136 19 0.10 -1 -1 32292 -1 -1 24 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64144 97 49 340 389 1 266 170 17 17 289 -1 unnamed_device 23.5 MiB 0.21 1319 34480 11756 18994 3730 62.6 MiB 0.17 0.00 7.55025 -291.095 -7.55025 7.55025 0.66 0.000977538 0.000912289 0.0748882 0.0698031 36 2772 30 6.55708e+06 289320 612192. 2118.31 3.26 0.332618 0.296208 22750 144809 -1 2396 20 939 1325 112348 38851 6.97679 6.97679 -283.59 -6.97679 0 0 782063. 2706.10 0.21 0.08 0.13 -1 -1 0.21 0.0382111 0.0340511 161 98 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 5.00 vpr 63.37 MiB -1 -1 0.29 18284 26 0.10 -1 -1 32564 -1 -1 35 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64892 129 65 453 518 1 353 229 17 17 289 -1 unnamed_device 24.3 MiB 0.18 1825 50629 14926 30325 5378 63.4 MiB 0.24 0.00 10.2543 -489.043 -10.2543 10.2543 0.66 0.00132504 0.00123931 0.0996393 0.0931935 36 3634 13 6.55708e+06 421925 612192. 2118.31 1.66 0.352251 0.318118 22750 144809 -1 3317 12 1246 1770 111506 27954 9.31476 9.31476 -453.748 -9.31476 0 0 782063. 2706.10 0.21 0.08 0.13 -1 -1 0.21 0.0355162 0.0321623 213 131 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.56 abc 29.24 MiB -1 -1 0.14 17208 1 0.02 -1 -1 29944 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22848 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.56 abc 29.38 MiB -1 -1 0.11 17212 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23212 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.54 abc 29.30 MiB -1 -1 0.13 17256 1 0.03 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23236 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.59 abc 29.38 MiB -1 -1 0.14 17256 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22880 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.56 abc 29.37 MiB -1 -1 0.15 17124 1 0.02 -1 -1 30076 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23256 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.72 abc 29.29 MiB -1 -1 0.15 17228 1 0.03 -1 -1 29992 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22924 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.57 abc 29.33 MiB -1 -1 0.15 17228 1 0.03 -1 -1 30036 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23016 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.55 abc 29.37 MiB -1 -1 0.14 17056 1 0.02 -1 -1 30076 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23104 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.61 abc 29.31 MiB -1 -1 0.16 17212 1 0.02 -1 -1 30012 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23048 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.50 abc 29.54 MiB -1 -1 0.16 17304 1 0.02 -1 -1 30252 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23076 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.53 abc 29.37 MiB -1 -1 0.15 17292 1 0.02 -1 -1 30072 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23160 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.59 abc 29.30 MiB -1 -1 0.14 17224 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23064 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.57 abc 29.26 MiB -1 -1 0.17 17484 1 0.03 -1 -1 29964 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23044 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.50 abc 29.45 MiB -1 -1 0.14 17468 1 0.02 -1 -1 30152 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23228 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.56 abc 29.38 MiB -1 -1 0.14 17516 1 0.03 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23304 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.61 abc 29.27 MiB -1 -1 0.17 17408 1 0.03 -1 -1 29968 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23272 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.60 abc 29.45 MiB -1 -1 0.16 17440 1 0.03 -1 -1 30152 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23312 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.58 abc 29.36 MiB -1 -1 0.15 17364 1 0.03 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23572 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.62 abc 29.35 MiB -1 -1 0.17 17468 1 0.03 -1 -1 30052 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23328 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.50 abc 29.47 MiB -1 -1 0.12 17572 1 0.03 -1 -1 30176 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23700 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.68 abc 29.56 MiB -1 -1 0.20 17916 1 0.03 -1 -1 30272 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23988 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.48 abc 29.23 MiB -1 -1 0.10 17228 1 0.02 -1 -1 29928 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22800 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.54 abc 29.25 MiB -1 -1 0.14 17220 1 0.02 -1 -1 29952 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22588 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.57 abc 29.28 MiB -1 -1 0.13 17148 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22676 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.54 abc 29.30 MiB -1 -1 0.17 17192 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22740 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.56 abc 29.44 MiB -1 -1 0.15 17124 1 0.02 -1 -1 30148 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22664 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.55 abc 29.33 MiB -1 -1 0.15 17256 1 0.02 -1 -1 30032 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22620 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.56 abc 29.45 MiB -1 -1 0.14 17268 1 0.02 -1 -1 30156 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22640 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.49 abc 29.52 MiB -1 -1 0.07 17312 1 0.02 -1 -1 30232 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22884 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.59 abc 29.30 MiB -1 -1 0.16 17268 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22736 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.49 abc 29.35 MiB -1 -1 0.12 17312 1 0.02 -1 -1 30052 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22704 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.58 abc 29.40 MiB -1 -1 0.16 17208 1 0.02 -1 -1 30104 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22772 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.58 abc 29.38 MiB -1 -1 0.14 17612 1 0.02 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22948 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.47 abc 29.18 MiB -1 -1 0.15 17276 1 0.02 -1 -1 29880 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22728 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.57 abc 29.36 MiB -1 -1 0.14 17456 1 0.03 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22852 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.58 abc 29.39 MiB -1 -1 0.16 17524 1 0.03 -1 -1 30100 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22860 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.54 abc 29.34 MiB -1 -1 0.15 17312 1 0.03 -1 -1 30044 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22936 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.60 abc 29.52 MiB -1 -1 0.16 17260 1 0.02 -1 -1 30228 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23004 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.57 abc 29.36 MiB -1 -1 0.16 17356 1 0.02 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23028 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.63 abc 29.34 MiB -1 -1 0.16 17376 1 0.02 -1 -1 30040 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23240 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.71 abc 29.41 MiB -1 -1 0.18 17680 1 0.03 -1 -1 30120 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23440 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.64 abc 29.86 MiB -1 -1 0.20 17752 1 0.03 -1 -1 30572 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23736 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 3.80 vpr 61.16 MiB -1 -1 0.15 17284 1 0.02 -1 -1 29968 -1 -1 2 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62628 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 22.5 MiB 0.01 43 476 113 309 54 61.2 MiB 0.01 0.00 0.792048 -9.40096 -0.792048 0.792048 0.66 8.7514e-05 7.9344e-05 0.00236896 0.00214809 20 127 14 6.64007e+06 25116 394039. 1363.46 1.51 0.0133243 0.0111289 20530 87850 -1 129 9 85 85 5128 1673 0.901248 0.901248 -10.0628 -0.901248 0 0 477104. 1650.88 0.16 0.01 0.05 -1 -1 0.16 0.00289847 0.00258414 13 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.98 vpr 61.02 MiB -1 -1 0.15 17248 1 0.02 -1 -1 29876 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62480 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 22.4 MiB 0.01 57 869 279 533 57 61.0 MiB 0.01 0.00 0.803048 -11.5224 -0.803048 0.803048 0.66 0.00010455 9.5432e-05 0.00399114 0.0036423 26 182 43 6.64007e+06 25116 477104. 1650.88 0.59 0.0206078 0.0172257 21682 110474 -1 164 18 158 158 7451 2508 0.923248 0.923248 -12.587 -0.923248 0 0 585099. 2024.56 0.21 0.01 0.10 -1 -1 0.21 0.00462477 0.00398154 16 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.00 vpr 61.17 MiB -1 -1 0.13 17144 1 0.02 -1 -1 30000 -1 -1 4 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62640 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 22.5 MiB 0.01 117 1010 285 572 153 61.2 MiB 0.01 0.00 0.825048 -14.462 -0.825048 0.825048 0.66 0.000118471 0.000108009 0.00392714 0.00358242 26 316 12 6.64007e+06 50232 477104. 1650.88 0.58 0.0175211 0.0147768 21682 110474 -1 281 13 146 146 9424 2462 1.05445 1.05445 -17.1111 -1.05445 0 0 585099. 2024.56 0.17 0.01 0.13 -1 -1 0.17 0.00429923 0.00374286 20 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.99 vpr 61.23 MiB -1 -1 0.14 17292 1 0.02 -1 -1 30004 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62700 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 22.5 MiB 0.02 110 1508 446 794 268 61.2 MiB 0.01 0.00 1.18536 -16.9991 -1.18536 1.18536 0.66 0.000140568 0.000128858 0.00601152 0.00552509 26 285 13 6.64007e+06 37674 477104. 1650.88 0.63 0.0217539 0.0185572 21682 110474 -1 258 15 160 160 10027 2964 1.09645 1.09645 -19.1204 -1.09645 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00522504 0.00451674 22 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.12 vpr 61.25 MiB -1 -1 0.14 17264 1 0.02 -1 -1 29992 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62716 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 22.6 MiB 0.02 120 1870 496 982 392 61.2 MiB 0.02 0.00 1.19636 -19.4451 -1.19636 1.19636 0.66 0.000157592 0.000145272 0.00695102 0.00639888 32 282 10 6.64007e+06 50232 554710. 1919.41 0.66 0.0236195 0.0202305 22834 132086 -1 266 11 163 163 7509 2385 0.987248 0.987248 -20.6018 -0.987248 0 0 701300. 2426.64 0.20 0.01 0.14 -1 -1 0.20 0.00477563 0.00418139 25 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.91 vpr 61.45 MiB -1 -1 0.12 17204 1 0.02 -1 -1 30068 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62920 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 23.0 MiB 0.02 130 2165 691 1177 297 61.4 MiB 0.02 0.00 1.20736 -22.2309 -1.20736 1.20736 0.66 0.000174873 0.00016127 0.00782606 0.00722942 30 316 17 6.64007e+06 50232 526063. 1820.29 0.64 0.0282901 0.0242219 22546 126617 -1 254 13 166 166 8480 2498 0.943248 0.943248 -21.1902 -0.943248 0 0 666494. 2306.21 0.19 0.02 0.12 -1 -1 0.19 0.00568189 0.00493208 28 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 3.07 vpr 61.39 MiB -1 -1 0.12 17240 1 0.03 -1 -1 30136 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62868 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 22.9 MiB 0.03 165 2599 732 1310 557 61.4 MiB 0.02 0.00 1.21836 -25.3249 -1.21836 1.21836 0.69 0.000193189 0.000178691 0.00881087 0.00813973 26 421 16 6.64007e+06 62790 477104. 1650.88 0.60 0.0307987 0.0263916 21682 110474 -1 398 14 218 218 16639 4369 1.10745 1.10745 -27.6146 -1.10745 0 0 585099. 2024.56 0.17 0.02 0.10 -1 -1 0.17 0.00642337 0.00555372 31 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.09 vpr 61.24 MiB -1 -1 0.10 17368 1 0.02 -1 -1 30052 -1 -1 5 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62712 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 22.7 MiB 0.03 164 2828 891 1242 695 61.2 MiB 0.02 0.00 1.22936 -27.5958 -1.22936 1.22936 0.66 0.000210126 0.000194466 0.00937181 0.00868417 30 486 22 6.64007e+06 62790 526063. 1820.29 0.67 0.0349793 0.0299751 22546 126617 -1 367 11 239 239 12208 3632 1.12945 1.12945 -28.0041 -1.12945 0 0 666494. 2306.21 0.19 0.02 0.11 -1 -1 0.19 0.00589239 0.00513321 34 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.12 vpr 61.24 MiB -1 -1 0.12 17196 1 0.02 -1 -1 30092 -1 -1 5 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62708 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 22.8 MiB 0.05 222 3193 974 1551 668 61.2 MiB 0.02 0.00 1.24036 -30.5145 -1.24036 1.24036 0.66 0.000206241 0.000189613 0.0101926 0.00944232 32 527 13 6.64007e+06 62790 554710. 1919.41 0.68 0.0366008 0.0318265 22834 132086 -1 447 16 229 229 13941 3724 1.00925 1.00925 -30.3671 -1.00925 0 0 701300. 2426.64 0.20 0.02 0.12 -1 -1 0.20 0.00782296 0.00672908 37 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.22 vpr 61.45 MiB -1 -1 0.14 17216 1 0.02 -1 -1 30064 -1 -1 6 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62920 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 23.0 MiB 0.03 213 3743 1348 1918 477 61.4 MiB 0.03 0.00 1.25136 -33.0163 -1.25136 1.25136 0.72 0.000237901 0.000220345 0.0112493 0.0104016 30 584 22 6.64007e+06 75348 526063. 1820.29 0.68 0.0400304 0.0344975 22546 126617 -1 463 18 358 358 22591 6437 0.934248 0.934248 -31.8611 -0.934248 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0112772 0.00977003 40 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.16 vpr 61.38 MiB -1 -1 0.14 17212 1 0.02 -1 -1 29984 -1 -1 7 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62852 29 15 104 105 1 73 51 17 17 289 -1 unnamed_device 22.8 MiB 0.02 274 4093 1352 1973 768 61.4 MiB 0.03 0.00 1.26236 -36.4784 -1.26236 1.26236 0.66 0.000251147 0.000232594 0.0117031 0.0108389 28 654 15 6.64007e+06 87906 500653. 1732.36 0.72 0.0405765 0.0351595 21970 115934 -1 549 10 281 281 17248 4733 1.04225 1.04225 -36.7874 -1.04225 0 0 612192. 2118.31 0.18 0.02 0.11 -1 -1 0.18 0.00651327 0.00572868 44 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.20 vpr 61.29 MiB -1 -1 0.15 17164 1 0.02 -1 -1 30276 -1 -1 7 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62756 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 22.8 MiB 0.03 288 4848 1950 2799 99 61.3 MiB 0.03 0.00 1.62267 -39.6749 -1.62267 1.62267 0.65 0.000271475 0.000251522 0.0137149 0.0127063 32 617 15 6.64007e+06 87906 554710. 1919.41 0.70 0.0433545 0.037688 22834 132086 -1 575 13 332 332 22282 5973 1.08425 1.08425 -39.233 -1.08425 0 0 701300. 2426.64 0.20 0.02 0.12 -1 -1 0.20 0.0081444 0.00711377 46 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.18 vpr 61.52 MiB -1 -1 0.11 17260 1 0.02 -1 -1 30136 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62992 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 23.0 MiB 0.03 322 6597 2432 2696 1469 61.5 MiB 0.04 0.00 1.63367 -43.7768 -1.63367 1.63367 0.66 0.000292255 0.000270622 0.018541 0.017196 32 754 18 6.64007e+06 87906 554710. 1919.41 0.71 0.0556481 0.0485561 22834 132086 -1 622 14 383 383 25542 6916 1.09525 1.09525 -42.2648 -1.09525 0 0 701300. 2426.64 0.20 0.02 0.12 -1 -1 0.20 0.0090182 0.00784311 49 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 3.22 vpr 61.57 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30072 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63048 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 23.0 MiB 0.04 339 6795 2758 3901 136 61.6 MiB 0.05 0.00 1.66184 -49.3449 -1.66184 1.66184 0.66 0.000328879 0.000305453 0.0186569 0.0173502 30 877 21 6.64007e+06 100464 526063. 1820.29 0.72 0.0534963 0.046625 22546 126617 -1 725 16 455 455 38637 11330 1.11845 1.11845 -47.0517 -1.11845 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0110638 0.00958809 55 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 3.29 vpr 61.68 MiB -1 -1 0.16 17352 1 0.03 -1 -1 30360 -1 -1 8 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63160 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 23.0 MiB 0.04 391 7990 3267 4602 121 61.7 MiB 0.05 0.00 1.67767 -55.9871 -1.67767 1.67767 0.65 0.000358075 0.000332611 0.0210013 0.0195326 30 1076 48 6.64007e+06 100464 526063. 1820.29 0.77 0.0781432 0.0678559 22546 126617 -1 826 17 556 556 45036 11307 1.25945 1.25945 -54.9829 -1.25945 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0125554 0.0108745 61 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 3.36 vpr 61.55 MiB -1 -1 0.17 17408 1 0.02 -1 -1 30468 -1 -1 10 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63024 45 23 160 161 1 114 78 17 17 289 -1 unnamed_device 22.9 MiB 0.03 547 9208 3773 5318 117 61.5 MiB 0.06 0.00 1.69967 -63.665 -1.69967 1.69967 0.66 0.000390372 0.000363778 0.0228801 0.0212812 32 1215 20 6.64007e+06 125580 554710. 1919.41 0.75 0.068449 0.0601539 22834 132086 -1 988 17 576 576 45950 11224 1.17345 1.17345 -60.6848 -1.17345 0 0 701300. 2426.64 0.20 0.04 0.12 -1 -1 0.20 0.0135273 0.0117909 68 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 3.30 vpr 61.69 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30488 -1 -1 10 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63172 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 23.0 MiB 0.04 529 5574 1023 4232 319 61.7 MiB 0.04 0.00 2.07098 -70.8466 -2.07098 2.07098 0.66 0.000421093 0.000392253 0.0140061 0.0130568 30 1206 16 6.64007e+06 125580 526063. 1820.29 0.75 0.0609755 0.053322 22546 126617 -1 1033 12 520 520 32652 8716 1.31245 1.31245 -69.5843 -1.31245 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.011216 0.00987288 73 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 3.41 vpr 62.00 MiB -1 -1 0.13 17528 1 0.02 -1 -1 30020 -1 -1 11 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63488 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 23.3 MiB 0.04 688 14749 3296 10627 826 62.0 MiB 0.08 0.00 2.11498 -86.7749 -2.11498 2.11498 0.68 0.000485921 0.00045307 0.0336544 0.0313608 32 1653 15 6.64007e+06 138138 554710. 1919.41 0.76 0.0862939 0.0768333 22834 132086 -1 1374 14 675 675 48554 12572 1.43265 1.43265 -84.9238 -1.43265 0 0 701300. 2426.64 0.20 0.04 0.12 -1 -1 0.20 0.0143687 0.0126195 85 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 3.52 vpr 62.02 MiB -1 -1 0.16 17364 1 0.03 -1 -1 30016 -1 -1 13 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63508 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 23.4 MiB 0.03 791 18731 4146 13545 1040 62.0 MiB 0.10 0.00 2.50829 -102.158 -2.50829 2.50829 0.66 0.000568801 0.000530582 0.0416036 0.0388114 32 1849 21 6.64007e+06 163254 554710. 1919.41 0.82 0.107446 0.0958091 22834 132086 -1 1541 21 798 798 73275 21259 1.30145 1.30145 -92.1899 -1.30145 0 0 701300. 2426.64 0.20 0.06 0.12 -1 -1 0.20 0.022426 0.0196464 97 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.77 vpr 62.88 MiB -1 -1 0.19 17720 1 0.03 -1 -1 30268 -1 -1 19 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64384 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 24.0 MiB 0.06 1480 31353 9242 19771 2340 62.9 MiB 0.18 0.00 3.38291 -181.53 -3.38291 3.38291 0.66 0.000869775 0.000815118 0.0622449 0.0583122 32 3008 21 6.64007e+06 238602 554710. 1919.41 0.89 0.16522 0.149537 22834 132086 -1 2560 16 1013 1013 92739 21618 1.53945 1.53945 -150.326 -1.53945 0 0 701300. 2426.64 0.21 0.08 0.12 -1 -1 0.21 0.0315009 0.028471 145 2 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 4.23 vpr 63.48 MiB -1 -1 0.21 17928 1 0.03 -1 -1 30708 -1 -1 25 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65000 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 24.3 MiB 0.08 2038 51621 17664 30557 3400 63.5 MiB 0.30 0.01 4.25753 -269.429 -4.25753 4.25753 0.66 0.00121076 0.00113937 0.0979391 0.0921344 32 3930 16 6.64007e+06 313950 554710. 1919.41 1.00 0.232884 0.213016 22834 132086 -1 3494 21 1388 1388 126838 29064 1.83045 1.83045 -210.947 -1.83045 0 0 701300. 2426.64 0.20 0.11 0.12 -1 -1 0.20 0.0468537 0.0421696 193 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 2.77 vpr 60.86 MiB -1 -1 0.08 17284 1 0.02 -1 -1 29916 -1 -1 2 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62324 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 22.2 MiB 0.01 41 456 116 304 36 60.9 MiB 0.01 0.00 0.781048 -9.22036 -0.781048 0.781048 0.66 0.000104203 9.5767e-05 0.00233402 0.00212179 26 126 10 6.65987e+06 25356 477104. 1650.88 0.50 0.00819264 0.00695085 21682 110474 -1 107 6 56 56 2239 782 0.71851 0.71851 -8.88158 -0.71851 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00252282 0.00228879 13 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.90 vpr 61.00 MiB -1 -1 0.15 17288 1 0.02 -1 -1 29916 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62460 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 22.3 MiB 0.01 72 1094 334 508 252 61.0 MiB 0.01 0.00 0.803048 -11.753 -0.803048 0.803048 0.66 0.000105682 9.6175e-05 0.00493217 0.00449786 26 213 10 6.65987e+06 25356 477104. 1650.88 0.57 0.0165703 0.014106 21682 110474 -1 158 11 121 121 5746 1754 0.912248 0.912248 -12.0702 -0.912248 0 0 585099. 2024.56 0.17 0.01 0.10 -1 -1 0.17 0.00360333 0.00316902 16 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 2.99 vpr 61.24 MiB -1 -1 0.17 16984 1 0.02 -1 -1 30068 -1 -1 4 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62708 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 22.5 MiB 0.01 113 670 139 437 94 61.2 MiB 0.01 0.00 0.825048 -14.1032 -0.825048 0.825048 0.66 0.000121874 0.000111722 0.00280615 0.0025762 26 293 16 6.65987e+06 50712 477104. 1650.88 0.59 0.0174431 0.014634 21682 110474 -1 283 18 187 187 18934 4701 1.06545 1.06545 -17.5297 -1.06545 0 0 585099. 2024.56 0.17 0.02 0.10 -1 -1 0.17 0.00532044 0.00456315 20 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.01 vpr 60.85 MiB -1 -1 0.15 17228 1 0.02 -1 -1 30000 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62308 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 22.2 MiB 0.01 111 1508 461 714 333 60.8 MiB 0.01 0.00 1.18536 -17.1757 -1.18536 1.18536 0.66 0.000139613 0.000128169 0.00599238 0.00550345 28 296 13 6.65987e+06 38034 500653. 1732.36 0.61 0.0216038 0.0184157 21970 115934 -1 262 9 136 136 8292 2563 1.08545 1.08545 -18.9312 -1.08545 0 0 612192. 2118.31 0.18 0.01 0.11 -1 -1 0.18 0.00402982 0.00356521 22 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.09 vpr 61.07 MiB -1 -1 0.15 17224 1 0.02 -1 -1 30180 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62540 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 22.6 MiB 0.01 119 1594 461 883 250 61.1 MiB 0.02 0.00 1.19636 -19.4942 -1.19636 1.19636 0.66 0.000159612 0.000146961 0.00596969 0.00549907 32 330 16 6.65987e+06 50712 554710. 1919.41 0.67 0.0240947 0.0205144 22834 132086 -1 281 13 133 133 8022 2338 1.09645 1.09645 -21.4834 -1.09645 0 0 701300. 2426.64 0.20 0.01 0.13 -1 -1 0.20 0.00530799 0.00462174 25 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.09 vpr 61.21 MiB -1 -1 0.15 17180 1 0.02 -1 -1 29948 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62676 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 22.7 MiB 0.01 130 2165 641 1112 412 61.2 MiB 0.02 0.00 1.20736 -22.0911 -1.20736 1.20736 0.66 0.000173899 0.000160531 0.00781201 0.00721594 26 359 15 6.65987e+06 50712 477104. 1650.88 0.64 0.0275906 0.0236264 21682 110474 -1 352 13 197 197 17592 4637 1.21665 1.21665 -25.5322 -1.21665 0 0 585099. 2024.56 0.17 0.02 0.10 -1 -1 0.17 0.00586274 0.00508496 28 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 3.09 vpr 61.23 MiB -1 -1 0.16 17160 1 0.03 -1 -1 30152 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62704 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 22.7 MiB 0.02 146 2599 849 1247 503 61.2 MiB 0.02 0.00 1.21836 -24.7702 -1.21836 1.21836 0.67 0.000193897 0.000178638 0.00884964 0.00818584 28 451 15 6.65987e+06 63390 500653. 1732.36 0.63 0.0309412 0.0265705 21970 115934 -1 403 18 284 284 24774 6503 1.14559 1.14559 -26.5125 -1.14559 0 0 612192. 2118.31 0.18 0.02 0.11 -1 -1 0.18 0.00760464 0.00650486 31 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.13 vpr 61.11 MiB -1 -1 0.16 17228 1 0.02 -1 -1 30068 -1 -1 5 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62572 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 22.6 MiB 0.02 164 2624 822 1205 597 61.1 MiB 0.02 0.00 1.22936 -27.5927 -1.22936 1.22936 0.71 0.000212415 0.00019654 0.00879453 0.00814611 28 553 19 6.65987e+06 63390 500653. 1732.36 0.65 0.0335815 0.0287785 21970 115934 -1 441 15 295 295 28098 7446 1.10745 1.10745 -28.9722 -1.10745 0 0 612192. 2118.31 0.18 0.02 0.11 -1 -1 0.18 0.00725138 0.00626258 34 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.20 vpr 61.31 MiB -1 -1 0.15 17200 1 0.02 -1 -1 30076 -1 -1 5 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62780 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 22.8 MiB 0.02 223 3193 975 1461 757 61.3 MiB 0.03 0.00 1.24036 -30.6298 -1.24036 1.24036 0.67 0.000223378 0.000206877 0.0103334 0.00956946 32 562 14 6.65987e+06 63390 554710. 1919.41 0.72 0.0352523 0.030479 22834 132086 -1 455 15 258 258 14799 4178 1.12945 1.12945 -31.8095 -1.12945 0 0 701300. 2426.64 0.20 0.02 0.12 -1 -1 0.20 0.00753138 0.00650194 37 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.26 vpr 61.30 MiB -1 -1 0.15 17140 1 0.02 -1 -1 30016 -1 -1 6 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62776 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 22.8 MiB 0.02 203 3743 1266 1895 582 61.3 MiB 0.04 0.00 1.25136 -33.0797 -1.25136 1.25136 0.69 0.000180835 0.000163976 0.0114849 0.010514 28 693 32 6.65987e+06 76068 500653. 1732.36 0.76 0.0446686 0.038274 21970 115934 -1 573 17 425 425 38592 10533 1.17465 1.17465 -34.4327 -1.17465 0 0 612192. 2118.31 0.18 0.03 0.11 -1 -1 0.18 0.00877668 0.00758502 40 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.18 vpr 61.19 MiB -1 -1 0.15 17488 1 0.02 -1 -1 30008 -1 -1 7 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62656 29 15 104 105 1 73 51 17 17 289 -1 unnamed_device 22.7 MiB 0.02 264 4093 1437 1752 904 61.2 MiB 0.03 0.00 1.26236 -36.2215 -1.26236 1.26236 0.66 0.000253145 0.000234295 0.011807 0.0109381 32 670 15 6.65987e+06 88746 554710. 1919.41 0.69 0.0396472 0.0343721 22834 132086 -1 581 23 359 359 103468 51390 1.17345 1.17345 -38.6162 -1.17345 0 0 701300. 2426.64 0.20 0.05 0.12 -1 -1 0.20 0.011457 0.00981357 44 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.29 vpr 61.08 MiB -1 -1 0.16 17596 1 0.02 -1 -1 30368 -1 -1 7 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62548 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 22.6 MiB 0.02 288 4848 1943 2811 94 61.1 MiB 0.03 0.00 1.62267 -39.7289 -1.62267 1.62267 0.66 0.000296047 0.000275111 0.0137689 0.012758 32 700 13 6.65987e+06 88746 554710. 1919.41 0.70 0.042975 0.0373677 22834 132086 -1 588 19 363 363 27152 7268 1.05125 1.05125 -39.1147 -1.05125 0 0 701300. 2426.64 0.20 0.03 0.12 -1 -1 0.20 0.0105454 0.00909287 46 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.25 vpr 61.33 MiB -1 -1 0.15 17480 1 0.02 -1 -1 30064 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62800 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 22.7 MiB 0.02 308 6597 2389 2698 1510 61.3 MiB 0.04 0.00 1.63367 -42.5457 -1.63367 1.63367 0.66 0.000296697 0.000275059 0.0184716 0.0171333 32 736 23 6.65987e+06 88746 554710. 1919.41 0.71 0.0510157 0.0445487 22834 132086 -1 635 17 405 405 33264 8740 1.19345 1.19345 -42.9014 -1.19345 0 0 701300. 2426.64 0.20 0.03 0.12 -1 -1 0.20 0.0103838 0.00898409 49 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 3.28 vpr 61.46 MiB -1 -1 0.16 17452 1 0.02 -1 -1 30060 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62932 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 22.9 MiB 0.02 338 6795 2757 3910 128 61.5 MiB 0.04 0.00 1.66184 -49.2226 -1.66184 1.66184 0.66 0.000327462 0.000304172 0.0184939 0.0172006 30 841 20 6.65987e+06 101424 526063. 1820.29 0.70 0.0569636 0.0496511 22546 126617 -1 737 14 426 426 36938 10631 1.14045 1.14045 -47.2201 -1.14045 0 0 666494. 2306.21 0.19 0.03 0.11 -1 -1 0.19 0.0102395 0.00889686 55 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 4.87 vpr 61.34 MiB -1 -1 0.16 17428 1 0.03 -1 -1 30360 -1 -1 8 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62816 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 22.7 MiB 0.03 394 7990 3280 4604 106 61.3 MiB 0.05 0.00 1.67767 -56.0732 -1.67767 1.67767 0.66 0.00035967 0.000334382 0.0209516 0.0194941 32 1087 23 6.65987e+06 101424 554710. 1919.41 2.30 0.105571 0.0908996 22834 132086 -1 908 14 558 558 45347 11907 1.25945 1.25945 -56.4254 -1.25945 0 0 701300. 2426.64 0.20 0.03 0.09 -1 -1 0.20 0.0109338 0.00953004 61 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.15 vpr 61.45 MiB -1 -1 0.16 17632 1 0.02 -1 -1 30336 -1 -1 10 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62924 45 23 160 161 1 114 78 17 17 289 -1 unnamed_device 22.8 MiB 0.03 488 9208 3771 5298 139 61.4 MiB 0.06 0.00 1.69967 -62.9619 -1.69967 1.69967 0.69 0.00039092 0.000363271 0.0226572 0.0210694 36 1124 25 6.65987e+06 126780 612192. 2118.31 2.52 0.126137 0.108853 23410 145293 -1 962 14 514 514 44638 11488 1.23745 1.23745 -61.3906 -1.23745 0 0 782063. 2706.10 0.21 0.04 0.13 -1 -1 0.21 0.0118808 0.0104196 68 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 3.30 vpr 61.90 MiB -1 -1 0.12 17348 1 0.02 -1 -1 30420 -1 -1 10 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63384 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 23.2 MiB 0.06 522 5025 948 3851 226 61.9 MiB 0.04 0.00 2.07098 -69.6207 -2.07098 2.07098 0.66 0.000420978 0.000392155 0.0127708 0.011908 30 1271 23 6.65987e+06 126780 526063. 1820.29 0.79 0.0636972 0.055469 22546 126617 -1 1026 17 511 511 34093 9196 1.56385 1.56385 -74.8887 -1.56385 0 0 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0.03 -1 -1 30016 -1 -1 13 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63244 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 23.2 MiB 0.03 796 12613 2902 8977 734 61.8 MiB 0.08 0.00 2.50829 -102.591 -2.50829 2.50829 0.68 0.000565242 0.000528385 0.0283548 0.0264917 30 1787 26 6.65987e+06 164814 526063. 1820.29 0.84 0.0999576 0.0884406 22546 126617 -1 1473 14 694 694 50016 13024 1.44759 1.44759 -96.299 -1.44759 0 0 666494. 2306.21 0.19 0.04 0.11 -1 -1 0.19 0.0164922 0.0145668 97 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.89 vpr 62.69 MiB -1 -1 0.18 17684 1 0.03 -1 -1 30276 -1 -1 19 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64196 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 23.8 MiB 0.05 1495 31353 9814 19140 2399 62.7 MiB 0.18 0.00 3.38291 -183.11 -3.38291 3.38291 0.65 0.000863126 0.000809109 0.0624506 0.0585064 32 3051 40 6.65987e+06 240882 554710. 1919.41 0.94 0.19035 0.171649 22834 132086 -1 2704 26 1139 1139 155858 42034 1.62545 1.62545 -154.798 -1.62545 0 0 701300. 2426.64 0.20 0.10 0.12 -1 -1 0.20 0.0405798 0.0361239 145 2 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 4.29 vpr 63.19 MiB -1 -1 0.20 17880 1 0.03 -1 -1 30500 -1 -1 25 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64708 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 24.3 MiB 0.08 2040 51621 17960 30273 3388 63.2 MiB 0.30 0.01 4.25753 -270.446 -4.25753 4.25753 0.66 0.00106095 0.0010003 0.0958688 0.0900199 32 4135 45 6.65987e+06 316950 554710. 1919.41 1.09 0.286974 0.260813 22834 132086 -1 3554 15 1373 1373 144561 33087 1.85245 1.85245 -211.327 -1.85245 0 0 701300. 2426.64 0.20 0.10 0.12 -1 -1 0.20 0.0359556 0.0324692 193 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 2.86 vpr 61.84 MiB -1 -1 0.15 17184 1 0.02 -1 -1 29952 -1 -1 1 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63328 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 23.1 MiB 0.02 31 357 99 212 46 61.8 MiB 0.01 0.00 0.723895 -9.81308 -0.723895 0.723895 0.70 8.7282e-05 7.9147e-05 0.00204764 0.00185217 18 109 13 6.95648e+06 14475.7 376052. 1301.22 0.47 0.0126091 0.0106259 22882 88689 -1 106 10 63 63 4495 1485 0.74674 0.74674 -10.4754 -0.74674 0 0 470940. 1629.55 0.13 0.01 0.08 -1 -1 0.13 0.00303795 0.00270532 7 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 3.92 vpr 61.95 MiB -1 -1 0.10 17236 1 0.02 -1 -1 29888 -1 -1 1 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63436 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 23.3 MiB 0.03 45 409 82 317 10 61.9 MiB 0.01 0.00 0.723895 -12.1585 -0.723895 0.723895 0.68 0.000104663 9.5475e-05 0.00223257 0.00203559 22 170 8 6.95648e+06 14475.7 443629. 1535.05 1.56 0.0190578 0.0157985 23458 102101 -1 133 9 59 59 3523 1154 0.723895 0.723895 -13.1609 -0.723895 0 0 531479. 1839.03 0.15 0.01 0.09 -1 -1 0.15 0.00347157 0.00310975 8 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 3.89 vpr 61.98 MiB -1 -1 0.15 17192 1 0.02 -1 -1 30072 -1 -1 2 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63464 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 23.4 MiB 0.03 75 472 115 342 15 62.0 MiB 0.01 0.00 0.905094 -15.1774 -0.905094 0.905094 0.68 0.00012189 0.000111654 0.00233885 0.00214172 20 205 8 6.95648e+06 28951.4 414966. 1435.87 1.38 0.0122566 0.0104883 23170 95770 -1 200 10 84 84 5135 1594 0.87204 0.87204 -16.4471 -0.87204 0 0 503264. 1741.40 0.14 0.01 0.09 -1 -1 0.14 0.00388988 0.00344828 10 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 3.25 vpr 61.77 MiB -1 -1 0.17 17228 1 0.02 -1 -1 30004 -1 -1 2 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63256 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 23.3 MiB 0.03 182 997 285 587 125 61.8 MiB 0.01 0.00 0.852632 -19.1795 -0.852632 0.852632 0.70 0.000138925 0.000127494 0.00432536 0.00398115 24 369 14 6.95648e+06 28951.4 470940. 1629.55 0.59 0.0203047 0.0172057 24034 113901 -1 347 15 149 149 13529 3216 1.10323 1.10323 -22.1823 -1.10323 0 0 586450. 2029.24 0.16 0.02 0.10 -1 -1 0.16 0.005486 0.00477732 11 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 3.06 vpr 61.90 MiB -1 -1 0.15 17124 1 0.02 -1 -1 30020 -1 -1 2 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63384 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 23.3 MiB 0.03 221 616 171 414 31 61.9 MiB 0.01 0.00 0.852632 -23.0752 -0.852632 0.852632 0.68 0.000156976 0.000144516 0.00281936 0.0025914 26 427 11 6.95648e+06 28951.4 503264. 1741.40 0.61 0.0198989 0.016773 24322 120374 -1 413 10 164 164 15751 3684 0.949732 0.949732 -24.7469 -0.949732 0 0 618332. 2139.56 0.17 0.01 0.11 -1 -1 0.17 0.00460572 0.00406062 13 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 4.94 vpr 61.88 MiB -1 -1 0.16 17144 1 0.02 -1 -1 30232 -1 -1 2 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63368 19 10 69 70 1 44 31 17 17 289 -1 unnamed_device 23.4 MiB 0.04 108 2527 936 1406 185 61.9 MiB 0.02 0.00 0.874632 -21.915 -0.874632 0.874632 0.68 0.000174667 0.000161174 0.00982014 0.00906234 34 384 17 6.95648e+06 28951.4 618332. 2139.56 2.35 0.0519176 0.043602 25762 151098 -1 300 23 302 302 18535 6038 1.12523 1.12523 -23.9556 -1.12523 0 0 787024. 2723.27 0.21 0.02 0.13 -1 -1 0.21 0.00849309 0.00723359 14 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 3.60 vpr 61.99 MiB -1 -1 0.15 17012 1 0.02 -1 -1 30176 -1 -1 2 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63476 21 11 76 77 1 49 34 17 17 289 -1 unnamed_device 23.5 MiB 0.04 124 1849 591 958 300 62.0 MiB 0.02 0.00 0.896632 -24.606 -0.896632 0.896632 0.67 0.000192675 0.000178253 0.00710392 0.00656778 34 464 39 6.95648e+06 28951.4 618332. 2139.56 1.07 0.0510483 0.0426537 25762 151098 -1 362 32 415 415 29570 8454 1.10803 1.10803 -26.2823 -1.10803 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.011713 0.00986011 16 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 3.24 vpr 62.27 MiB -1 -1 0.16 17232 1 0.02 -1 -1 30004 -1 -1 3 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63768 23 12 83 84 1 55 38 17 17 289 -1 unnamed_device 23.7 MiB 0.04 149 1424 335 1059 30 62.3 MiB 0.02 0.00 0.879432 -27.154 -0.879432 0.879432 0.68 0.000183203 0.000167598 0.00543142 0.00502988 28 532 47 6.95648e+06 43427 531479. 1839.03 0.73 0.0393068 0.0331151 24610 126494 -1 457 11 280 280 18391 5462 1.06403 1.06403 -32.0123 -1.06403 0 0 648988. 2245.63 0.18 0.02 0.11 -1 -1 0.18 0.00609298 0.00531886 17 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 3.63 vpr 61.99 MiB -1 -1 0.15 17148 1 0.03 -1 -1 29996 -1 -1 3 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63476 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 23.4 MiB 0.04 191 1581 337 1210 34 62.0 MiB 0.02 0.00 0.918632 -30.4288 -0.918632 0.918632 0.68 0.000224111 0.000207562 0.00575802 0.00534334 34 576 15 6.95648e+06 43427 618332. 2139.56 1.06 0.0478747 0.040272 25762 151098 -1 469 13 301 301 25512 7050 1.14103 1.14103 -34.6799 -1.14103 0 0 787024. 2723.27 0.21 0.02 0.13 -1 -1 0.21 0.00708738 0.00617617 19 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 3.31 vpr 62.01 MiB -1 -1 0.15 17284 1 0.02 -1 -1 30108 -1 -1 3 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63496 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 23.5 MiB 0.04 373 2046 513 1237 296 62.0 MiB 0.02 0.00 0.951632 -36.1138 -0.951632 0.951632 0.68 0.000237905 0.000220439 0.00701976 0.00650806 30 806 29 6.95648e+06 43427 556674. 1926.21 0.73 0.0387382 0.0330004 25186 138497 -1 740 15 338 338 31466 6815 1.23953 1.23953 -40.3343 -1.23953 0 0 706193. 2443.58 0.19 0.02 0.12 -1 -1 0.19 0.00817822 0.0071029 20 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 3.71 vpr 62.25 MiB -1 -1 0.16 17448 1 0.02 -1 -1 29992 -1 -1 4 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63740 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 23.6 MiB 0.03 471 3180 797 1969 414 62.2 MiB 0.03 0.00 0.951632 -40.3696 -0.951632 0.951632 0.68 0.000303996 0.000282063 0.0105737 0.00979692 34 943 21 6.95648e+06 57902.7 618332. 2139.56 1.11 0.0601265 0.051146 25762 151098 -1 907 13 383 383 44092 8818 1.17403 1.17403 -47.4039 -1.17403 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.00787889 0.00688785 23 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 3.83 vpr 62.00 MiB -1 -1 0.16 17504 1 0.03 -1 -1 30248 -1 -1 3 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63492 31 16 111 112 1 78 50 17 17 289 -1 unnamed_device 23.4 MiB 0.05 264 3822 1541 2241 40 62.0 MiB 0.03 0.00 1.33396 -40.3826 -1.33396 1.33396 0.68 0.000270886 0.000250971 0.0121153 0.0112397 34 748 29 6.95648e+06 43427 618332. 2139.56 1.17 0.0688746 0.0587304 25762 151098 -1 618 19 437 437 34249 8680 1.21603 1.21603 -44.255 -1.21603 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.0107725 0.00930388 24 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_016bits.v common 5.00 vpr 62.34 MiB -1 -1 0.15 17420 1 0.03 -1 -1 30048 -1 -1 4 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63832 33 17 118 119 1 81 54 17 17 289 -1 unnamed_device 23.7 MiB 0.06 280 4848 1977 2824 47 62.3 MiB 0.04 0.00 1.34496 -43.4863 -1.34496 1.34496 0.68 0.000340372 0.000315622 0.0158838 0.0147285 34 846 37 6.95648e+06 57902.7 618332. 2139.56 2.29 0.112294 0.0951773 25762 151098 -1 606 14 401 401 28162 7406 1.20503 1.20503 -45.4821 -1.20503 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.00922062 0.00805291 25 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_018bits.v common 4.06 vpr 62.36 MiB -1 -1 0.17 17484 1 0.02 -1 -1 30084 -1 -1 4 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63852 37 19 132 133 1 87 60 17 17 289 -1 unnamed_device 23.7 MiB 0.09 310 6963 2911 4006 46 62.4 MiB 0.05 0.00 1.36696 -49.8294 -1.36696 1.36696 0.68 0.000327057 0.000303873 0.0205925 0.0191589 34 994 23 6.95648e+06 57902.7 618332. 2139.56 1.35 0.0863385 0.0744203 25762 151098 -1 765 19 512 512 55670 13459 1.42263 1.42263 -55.9177 -1.42263 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0128797 0.011132 28 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 3.99 vpr 62.29 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30328 -1 -1 4 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63780 41 21 146 147 1 95 66 17 17 289 -1 unnamed_device 23.6 MiB 0.08 348 7115 2951 4114 50 62.3 MiB 0.05 0.00 1.38896 -56.0872 -1.38896 1.38896 0.68 0.000356708 0.000331613 0.0203231 0.018915 34 1081 30 6.95648e+06 57902.7 618332. 2139.56 1.26 0.0931371 0.0803289 25762 151098 -1 859 23 578 578 97985 34449 1.27723 1.27723 -60.4816 -1.27723 0 0 787024. 2723.27 0.21 0.05 0.13 -1 -1 0.21 0.0160421 0.0138688 31 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 4.16 vpr 62.35 MiB -1 -1 0.17 17388 1 0.02 -1 -1 30308 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63960 49 25 174 175 1 119 79 17 17 289 -1 unnamed_device 23.8 MiB 0.09 521 10050 4309 5679 62 62.5 MiB 0.06 0.00 1.43296 -70.1603 -1.43296 1.43296 0.67 0.000421895 0.000392614 0.026221 0.0244102 36 1304 23 6.95648e+06 72378.4 648988. 2245.63 3.05 0.1406 0.121724 26050 158493 -1 1030 17 612 612 59690 13565 1.41353 1.41353 -73.8115 -1.41353 0 0 828058. 2865.25 0.22 0.04 0.14 -1 -1 0.22 0.0149726 0.013118 37 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_028bits.v common 6.65 vpr 62.59 MiB -1 -1 0.17 17464 1 0.03 -1 -1 30112 -1 -1 6 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64088 57 29 202 203 1 142 92 17 17 289 -1 unnamed_device 23.9 MiB 0.07 560 13961 5920 7973 68 62.6 MiB 0.08 0.00 1.47696 -82.5806 -1.47696 1.47696 0.68 0.000486994 0.000453244 0.0343411 0.0319713 44 1567 49 6.95648e+06 86854.1 787024. 2723.27 3.81 0.218821 0.190202 27778 195446 -1 1178 16 789 789 69897 17053 1.71293 1.71293 -93.4275 -1.71293 0 0 997811. 3452.63 0.26 0.05 0.17 -1 -1 0.26 0.0162237 0.0142906 43 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_032bits.v common 6.57 vpr 62.62 MiB -1 -1 0.17 17772 1 0.03 -1 -1 30088 -1 -1 7 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64128 65 33 230 231 1 162 105 17 17 289 -1 unnamed_device 24.1 MiB 0.08 758 16160 6842 9176 142 62.6 MiB 0.09 0.00 1.88129 -97.0955 -1.88129 1.88129 0.67 0.000568281 0.000530239 0.0389098 0.036328 46 1513 18 6.95648e+06 101330 828058. 2865.25 3.65 0.182353 0.160035 28066 200906 -1 1326 20 938 938 82737 18232 1.39433 1.39433 -94.6526 -1.39433 0 0 1.01997e+06 3529.29 0.26 0.06 0.17 -1 -1 0.26 0.0222592 0.0195882 49 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 13.20 vpr 63.59 MiB -1 -1 0.19 17748 1 0.03 -1 -1 30248 -1 -1 10 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65116 97 49 342 343 1 243 156 17 17 289 -1 unnamed_device 24.4 MiB 0.10 1331 30743 8901 19960 1882 63.6 MiB 0.16 0.00 2.41762 -163.869 -2.41762 2.41762 0.68 0.000868882 0.000814468 0.0660178 0.0618779 46 2969 39 6.95648e+06 144757 828058. 2865.25 10.06 0.463365 0.412468 28066 200906 -1 2418 23 1272 1272 164877 46134 1.59703 1.59703 -158.435 -1.59703 0 0 1.01997e+06 3529.29 0.26 0.10 0.17 -1 -1 0.26 0.0374983 0.0335237 73 2 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 8.79 vpr 64.01 MiB -1 -1 0.21 17776 1 0.03 -1 -1 30480 -1 -1 13 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65548 129 65 454 455 1 324 207 17 17 289 -1 unnamed_device 24.9 MiB 0.12 2090 36315 10749 23078 2488 64.0 MiB 0.21 0.01 2.95395 -243.637 -2.95395 2.95395 0.68 0.00119694 0.00112643 0.0741031 0.0697002 60 3530 29 6.95648e+06 188184 1.01997e+06 3529.29 5.38 0.462086 0.415678 30658 258169 -1 3123 16 1299 1299 131280 27013 1.66773 1.66773 -209.901 -1.66773 0 0 1.27783e+06 4421.56 0.32 0.10 0.22 -1 -1 0.32 0.0389481 0.0352944 97 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_004bits.v common 2.86 vpr 61.61 MiB -1 -1 0.14 17324 1 0.02 -1 -1 29988 -1 -1 1 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63092 9 5 34 35 1 17 15 17 17 289 -1 unnamed_device 22.9 MiB 0.01 35 375 107 237 31 61.6 MiB 0.01 0.00 0.712895 -9.56286 -0.712895 0.712895 0.68 8.7064e-05 7.8893e-05 0.00212669 0.0019303 22 122 12 6.99608e+06 14715.7 443629. 1535.05 0.53 0.0122226 0.010287 23458 102101 -1 88 10 56 56 2042 763 0.834592 0.834592 -9.47336 -0.834592 0 0 531479. 1839.03 0.15 0.01 0.09 -1 -1 0.15 0.00302037 0.00268799 7 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_005bits.v common 2.97 vpr 61.53 MiB -1 -1 0.15 17256 1 0.02 -1 -1 29912 -1 -1 1 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63008 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 22.8 MiB 0.01 44 409 92 302 15 61.5 MiB 0.01 0.00 0.837432 -12.9697 -0.837432 0.837432 0.68 0.000104705 9.5595e-05 0.00222083 0.00202997 22 151 9 6.99608e+06 14715.7 443629. 1535.05 0.55 0.0137541 0.0115757 23458 102101 -1 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17332 1 0.02 -1 -1 30148 -1 -1 2 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63032 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 22.8 MiB 0.02 80 745 225 479 41 61.6 MiB 0.01 0.00 0.859432 -18.0958 -0.859432 0.859432 0.68 0.000140434 0.000129114 0.00336029 0.003095 26 226 21 6.99608e+06 29431.4 503264. 1741.40 0.63 0.0207047 0.0174372 24322 120374 -1 219 8 108 108 6712 2063 0.940679 0.940679 -18.5361 -0.940679 0 0 618332. 2139.56 0.17 0.01 0.11 -1 -1 0.17 0.00383384 0.00341969 11 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 3.09 vpr 62.01 MiB -1 -1 0.15 17212 1 0.04 -1 -1 30120 -1 -1 2 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63500 17 9 62 63 1 38 28 17 17 289 -1 unnamed_device 23.5 MiB 0.02 203 658 170 428 60 62.0 MiB 0.01 0.00 0.87204 -21.2308 -0.87204 0.87204 0.68 0.000155534 0.00014286 0.00291886 0.00268597 26 454 14 6.99608e+06 29431.4 503264. 1741.40 0.62 0.0208548 0.01753 24322 120374 -1 397 16 215 215 23320 5491 1.11618 1.11618 -24.5247 -1.11618 0 0 618332. 2139.56 0.17 0.02 0.11 -1 -1 0.17 0.00594626 0.00511258 13 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 5.35 vpr 61.82 MiB -1 -1 0.15 17208 1 0.02 -1 -1 30064 -1 -1 2 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63304 19 10 69 70 1 44 31 17 17 289 -1 unnamed_device 23.3 MiB 0.02 110 2479 792 1104 583 61.8 MiB 0.02 0.00 0.846432 -21.9214 -0.846432 0.846432 0.68 0.000174702 0.000161124 0.00958988 0.00884645 36 343 46 6.99608e+06 29431.4 648988. 2245.63 2.80 0.0627426 0.0522955 26050 158493 -1 255 16 264 264 11899 3964 1.09703 1.09703 -22.5274 -1.09703 0 0 828058. 2865.25 0.22 0.02 0.14 -1 -1 0.22 0.00658358 0.00568186 14 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_010bits.v common 3.63 vpr 61.95 MiB -1 -1 0.15 17104 1 0.02 -1 -1 30080 -1 -1 2 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63436 21 11 76 77 1 49 34 17 17 289 -1 unnamed_device 23.5 MiB 0.02 134 1739 500 978 261 61.9 MiB 0.02 0.00 0.857432 -24.4123 -0.857432 0.857432 0.70 0.00019256 0.000177985 0.00675256 0.00624408 34 406 27 6.99608e+06 29431.4 618332. 2139.56 1.08 0.0469744 0.039314 25762 151098 -1 352 19 335 335 20191 5998 1.16733 1.16733 -25.6028 -1.16733 0 0 787024. 2723.27 0.21 0.02 0.13 -1 -1 0.21 0.00793836 0.0067661 16 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 3.19 vpr 61.93 MiB -1 -1 0.15 17348 1 0.03 -1 -1 30000 -1 -1 3 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63420 23 12 83 84 1 54 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 157 1298 273 992 33 61.9 MiB 0.01 0.00 0.879432 -27.0809 -0.879432 0.879432 0.69 0.000209784 0.000194331 0.00498719 0.00462021 30 505 13 6.99608e+06 44147 556674. 1926.21 0.68 0.0282405 0.0240418 25186 138497 -1 420 17 320 320 22894 6682 1.13198 1.13198 -31.7562 -1.13198 0 0 706193. 2443.58 0.19 0.02 0.12 -1 -1 0.19 0.00791286 0.00680288 17 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 3.19 vpr 61.80 MiB -1 -1 0.14 17248 1 0.02 -1 -1 29996 -1 -1 3 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63280 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 23.3 MiB 0.02 214 1861 414 1414 33 61.8 MiB 0.02 0.00 0.890432 -31.2249 -0.890432 0.890432 0.68 0.000223146 0.000206487 0.00656913 0.00606521 26 594 14 6.99608e+06 44147 503264. 1741.40 0.67 0.0311123 0.0265403 24322 120374 -1 540 14 356 356 28447 7724 1.08798 1.08798 -35.908 -1.08798 0 0 618332. 2139.56 0.17 0.02 0.11 -1 -1 0.17 0.00739638 0.00642002 19 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 3.23 vpr 61.92 MiB -1 -1 0.16 17132 1 0.02 -1 -1 30056 -1 -1 3 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63408 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 23.4 MiB 0.02 395 2354 574 1438 342 61.9 MiB 0.02 0.00 0.912432 -36.6204 -0.912432 0.912432 0.67 0.000244515 0.000221455 0.00801856 0.00743288 30 788 16 6.99608e+06 44147 556674. 1926.21 0.71 0.0349545 0.0299783 25186 138497 -1 710 15 331 331 30405 6379 1.18218 1.18218 -41.7645 -1.18218 0 0 706193. 2443.58 0.19 0.02 0.12 -1 -1 0.19 0.00813372 0.0070695 20 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 3.71 vpr 61.95 MiB -1 -1 0.14 17028 1 0.02 -1 -1 29952 -1 -1 4 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63440 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 23.4 MiB 0.02 470 2571 633 1642 296 62.0 MiB 0.02 0.00 0.923432 -39.2056 -0.923432 0.923432 0.68 0.000250872 0.000232665 0.00822485 0.00762679 34 973 32 6.99608e+06 58862.7 618332. 2139.56 1.13 0.0617908 0.0524284 25762 151098 -1 866 15 496 496 57332 11353 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63560 37 19 132 133 1 87 60 17 17 289 -1 unnamed_device 23.5 MiB 0.03 309 6963 2905 3992 66 62.1 MiB 0.05 0.00 1.33876 -48.9536 -1.33876 1.33876 0.67 0.000328569 0.000305361 0.0205895 0.0191523 36 858 19 6.99608e+06 58862.7 648988. 2245.63 1.26 0.0838954 0.07231 26050 158493 -1 707 14 444 444 42628 10193 1.34133 1.34133 -53.1429 -1.34133 0 0 828058. 2865.25 0.22 0.03 0.14 -1 -1 0.22 0.0102672 0.00892568 28 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 4.04 vpr 62.10 MiB -1 -1 0.16 17520 1 0.02 -1 -1 30328 -1 -1 4 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63588 41 21 146 147 1 94 66 17 17 289 -1 unnamed_device 23.5 MiB 0.03 346 7115 2925 4148 42 62.1 MiB 0.05 0.00 1.34976 -55.318 -1.34976 1.34976 0.68 0.000358867 0.000333622 0.0203294 0.0189181 34 1135 29 6.99608e+06 58862.7 618332. 2139.56 1.34 0.0959932 0.082851 25762 151098 -1 832 15 501 501 54380 12460 1.29733 1.29733 -59.146 -1.29733 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.011617 0.01012 31 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 4.23 vpr 62.14 MiB -1 -1 0.15 17468 1 0.02 -1 -1 30340 -1 -1 5 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63632 45 23 160 161 1 107 73 17 17 289 -1 unnamed_device 23.6 MiB 0.03 396 9041 3748 5233 60 62.1 MiB 0.06 0.00 1.37176 -60.8627 -1.37176 1.37176 0.68 0.000388136 0.000360981 0.0243639 0.0226856 36 1189 23 6.99608e+06 73578.4 648988. 2245.63 1.55 0.101626 0.088275 26050 158493 -1 900 14 588 588 51751 12479 1.26003 1.26003 -64.2225 -1.26003 0 0 828058. 2865.25 0.22 0.04 0.14 -1 -1 0.22 0.0120573 0.0105776 34 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 4.44 vpr 62.25 MiB -1 -1 0.16 17324 1 0.02 -1 -1 30332 -1 -1 5 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63740 49 25 174 175 1 118 79 17 17 289 -1 unnamed_device 23.6 MiB 0.04 446 10050 4202 5799 49 62.2 MiB 0.06 0.00 1.39376 -66.6204 -1.39376 1.39376 0.68 0.00042006 0.000390522 0.0262349 0.0244202 38 1265 21 6.99608e+06 73578.4 678818. 2348.85 1.69 0.108307 0.0943365 26626 170182 -1 974 15 641 641 56777 14042 1.26003 1.26003 -68.4016 -1.26003 0 0 902133. 3121.57 0.23 0.04 0.15 -1 -1 0.23 0.0136353 0.0119655 37 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 6.07 vpr 62.44 MiB -1 -1 0.17 17468 1 0.03 -1 -1 30020 -1 -1 6 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63940 57 29 202 203 1 141 92 17 17 289 -1 unnamed_device 23.7 MiB 0.04 634 13961 5842 8023 96 62.4 MiB 0.08 0.00 1.44876 -81.1127 -1.44876 1.44876 0.67 0.00048998 0.000454837 0.03434 0.031956 36 1508 35 6.99608e+06 88294.1 648988. 2245.63 3.27 0.178122 0.155283 26050 158493 -1 1254 26 824 824 164581 67296 1.21798 1.21798 -79.2356 -1.21798 0 0 828058. 2865.25 0.22 0.08 0.14 -1 -1 0.22 0.0235237 0.0205368 43 2 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 8.40 vpr 62.50 MiB -1 -1 0.17 17500 1 0.03 -1 -1 30004 -1 -1 7 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64000 65 33 230 231 1 162 105 17 17 289 -1 unnamed_device 23.7 MiB 0.04 748 16160 6967 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32092 -1 -1 1 9 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62468 9 5 28 33 1 16 15 17 17 289 -1 unnamed_device 22.4 MiB 0.01 35 357 92 226 39 61.0 MiB 0.01 0.00 0.883748 -9.933 -0.883748 0.883748 0.68 8.4734e-05 7.6497e-05 0.00196888 0.00178132 18 144 17 6.79088e+06 13472 376052. 1301.22 0.45 0.00665622 0.00588373 22222 88205 -1 110 7 44 44 1714 684 0.883748 0.883748 -10.7206 -0.883748 0 0 470940. 1629.55 0.13 0.01 0.08 -1 -1 0.13 0.00263552 0.00238471 8 6 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_005bits.v common 3.15 vpr 61.11 MiB -1 -1 0.15 17188 2 0.05 -1 -1 31992 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62572 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 22.5 MiB 0.01 56 369 83 271 15 61.1 MiB 0.01 0.00 1.02368 -13.1464 -1.02368 1.02368 0.67 0.000104014 9.4812e-05 0.00189463 0.00172822 30 193 10 6.79088e+06 26944 556674. 1926.21 0.65 0.0134574 0.0112841 24526 138013 -1 152 7 57 63 2733 866 1.02368 1.02368 -13.6271 -1.02368 0 0 706193. 2443.58 0.19 0.01 0.12 -1 -1 0.19 0.00305668 0.00274947 10 7 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_006bits.v common 2.91 vpr 61.02 MiB -1 -1 0.10 17192 3 0.05 -1 -1 31792 -1 -1 2 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62488 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 22.4 MiB 0.01 84 562 132 416 14 61.0 MiB 0.01 0.00 1.14898 -15.8855 -1.14898 1.14898 0.67 0.000124296 0.000113845 0.00272442 0.00249969 22 271 8 6.79088e+06 26944 443629. 1535.05 0.53 0.0157781 0.0133199 22798 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62660 19 10 60 70 1 47 31 17 17 289 -1 unnamed_device 22.7 MiB 0.07 125 1183 237 903 43 61.2 MiB 0.01 0.00 1.43883 -25.2844 -1.43883 1.43883 0.67 0.000182863 0.000168735 0.00508335 0.00468617 26 422 10 6.79088e+06 26944 503264. 1741.40 1.28 0.0436852 0.0363998 23662 119890 -1 385 8 159 169 9032 2746 1.38849 1.38849 -27.4637 -1.38849 0 0 618332. 2139.56 0.17 0.01 0.11 -1 -1 0.17 0.00465726 0.00411883 16 13 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_010bits.v common 4.73 vpr 61.26 MiB -1 -1 0.16 17116 4 0.06 -1 -1 31656 -1 -1 3 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62732 21 11 69 80 1 55 35 17 17 289 -1 unnamed_device 22.8 MiB 0.10 146 2315 597 1240 478 61.3 MiB 0.02 0.00 1.81478 -30.6537 -1.81478 1.81478 0.67 0.000233285 0.000212021 0.00979652 0.00898605 30 577 23 6.79088e+06 40416 556674. 1926.21 2.10 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63224 27 14 91 105 1 72 46 17 17 289 -1 unnamed_device 23.2 MiB 0.25 357 5294 1465 2962 867 61.7 MiB 0.05 0.00 2.15497 -46.2823 -2.15497 2.15497 0.67 0.000360865 0.000333566 0.0266747 0.0247208 30 821 13 6.79088e+06 67360 556674. 1926.21 1.51 0.0843095 0.0727651 24526 138013 -1 699 10 243 302 17846 4568 1.89323 1.89323 -44.8083 -1.89323 0 0 706193. 2443.58 0.19 0.02 0.12 -1 -1 0.19 0.0072577 0.00639563 28 24 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_014bits.v common 3.52 vpr 61.38 MiB -1 -1 0.18 17272 6 0.06 -1 -1 32108 -1 -1 4 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62852 29 15 95 110 1 77 48 17 17 289 -1 unnamed_device 22.9 MiB 0.21 360 2310 483 1816 11 61.4 MiB 0.02 0.00 2.44482 -48.4646 -2.44482 2.44482 0.67 0.000280721 0.000260207 0.00834682 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2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63092 37 19 127 146 1 99 62 17 17 289 -1 unnamed_device 23.0 MiB 0.81 464 4820 996 3804 20 61.6 MiB 0.04 0.00 3.16102 -73.9362 -3.16102 3.16102 0.67 0.00036881 0.00034252 0.0156651 0.0145648 30 1094 21 6.79088e+06 80832 556674. 1926.21 1.62 0.0958325 0.0820414 24526 138013 -1 930 12 343 419 31667 7571 2.82088 2.82088 -72.5283 -2.82088 0 0 706193. 2443.58 0.24 0.03 0.12 -1 -1 0.24 0.0106908 0.00940112 38 35 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_020bits.v common 5.50 vpr 61.51 MiB -1 -1 0.19 17548 8 0.06 -1 -1 31928 -1 -1 6 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62984 41 21 139 160 1 108 68 17 17 289 -1 unnamed_device 22.8 MiB 0.35 505 7106 1657 5163 286 61.5 MiB 0.05 0.00 2.83873 -77.6199 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63556 57 29 198 227 1 155 95 17 17 289 -1 unnamed_device 23.6 MiB 0.70 615 10463 2656 6907 900 62.1 MiB 0.06 0.00 4.24968 -125.714 -4.24968 4.24968 0.67 0.000571579 0.000532061 0.0293594 0.0273517 34 1590 48 6.79088e+06 121248 618332. 2139.56 1.34 0.163461 0.14228 25102 150614 -1 1284 13 514 639 38670 10280 4.07404 4.07404 -123.729 -4.07404 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0165509 0.0145999 57 56 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_032bits.v common 6.51 vpr 62.35 MiB -1 -1 0.21 17704 13 0.08 -1 -1 32276 -1 -1 10 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63848 65 33 224 257 1 176 108 17 17 289 -1 unnamed_device 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success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63176 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 22.9 MiB 0.05 213 3965 1588 2336 41 61.7 MiB 0.03 0.00 1.2704 -36.288 -1.2704 1.2704 0.68 0.000237431 0.000219543 0.0125415 0.0115936 34 721 25 6.87369e+06 55895.4 618332. 2139.56 1.10 0.0609137 0.0518256 25762 151098 -1 589 20 464 464 40651 10612 1.19797 1.19797 -38.5769 -1.19797 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.0098341 0.00843389 28 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 5.04 vpr 61.62 MiB -1 -1 0.17 17636 1 0.02 -1 -1 29960 -1 -1 5 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63104 29 15 104 105 1 74 49 17 17 289 -1 unnamed_device 23.2 MiB 0.07 237 4232 1719 2454 59 61.6 MiB 0.03 0.00 1.2814 -39.5262 -1.2814 1.2814 0.69 0.00025177 0.000232586 0.0125905 0.0116432 34 871 25 6.87369e+06 69869.2 618332. 2139.56 2.40 0.079398 0.0672669 25762 151098 -1 667 19 530 530 42842 11447 1.19797 1.19797 -41.7719 -1.19797 0 0 787024. 2723.27 0.21 0.03 0.13 -1 -1 0.21 0.00987761 0.00848143 31 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 4.14 vpr 61.68 MiB -1 -1 0.15 17472 1 0.02 -1 -1 30296 -1 -1 5 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63160 31 16 111 112 1 80 52 17 17 289 -1 unnamed_device 23.2 MiB 0.13 290 5096 2068 2936 92 61.7 MiB 0.04 0.00 1.65273 -43.1089 -1.65273 1.65273 0.68 0.000270835 0.000250663 0.0151058 0.0139874 30 651 17 6.87369e+06 69869.2 556674. 1926.21 1.61 0.0753013 0.06438 25186 138497 -1 555 14 349 349 20738 5613 1.18967 1.18967 -42.4244 -1.18967 0 0 706193. 2443.58 0.19 0.02 0.08 -1 -1 0.19 0.00848612 0.00736887 33 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 3.31 vpr 61.83 MiB -1 -1 0.15 17556 1 0.02 -1 -1 30004 -1 -1 5 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63316 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 23.3 MiB 0.08 305 6087 2501 3496 90 61.8 MiB 0.04 0.00 1.66373 -46.473 -1.66373 1.66373 0.68 0.000289384 0.000268076 0.017735 0.016463 30 704 16 6.87369e+06 69869.2 556674. 1926.21 0.71 0.049865 0.0434789 25186 138497 -1 594 15 396 396 26462 7106 1.10837 1.10837 -44.7628 -1.10837 0 0 706193. 2443.58 0.19 0.03 0.12 -1 -1 0.19 0.00946652 0.00819901 34 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 4.32 vpr 61.81 MiB -1 -1 0.16 17376 1 0.03 -1 -1 30088 -1 -1 5 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63296 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 23.2 MiB 0.07 338 5821 2339 3395 87 61.8 MiB 0.04 0.00 1.68573 -53.1446 -1.68573 1.68573 0.67 0.000331983 0.00030891 0.0168326 0.0156666 30 889 19 6.87369e+06 69869.2 556674. 1926.21 1.73 0.0876477 0.0749122 25186 138497 -1 717 13 426 426 32408 8353 1.25567 1.25567 -53.9391 -1.25567 0 0 706193. 2443.58 0.19 0.03 0.12 -1 -1 0.19 0.00950495 0.00826691 38 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 3.83 vpr 61.99 MiB -1 -1 0.16 17440 1 0.02 -1 -1 30316 -1 -1 6 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63480 41 21 146 147 1 101 68 17 17 289 -1 unnamed_device 23.4 MiB 0.07 382 7382 2999 4271 112 62.0 MiB 0.05 0.00 1.70773 -60.515 -1.70773 1.70773 0.68 0.00036779 0.00034229 0.0202702 0.0188494 34 1055 16 6.87369e+06 83843 618332. 2139.56 1.15 0.0872034 0.0751779 25762 151098 -1 880 13 543 543 61364 17119 1.24467 1.24467 -58.6078 -1.24467 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0103488 0.00905556 42 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 4.02 vpr 62.00 MiB -1 -1 0.17 17468 1 0.02 -1 -1 30320 -1 -1 7 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63492 45 23 160 161 1 115 75 17 17 289 -1 unnamed_device 23.4 MiB 0.11 444 8449 3437 4860 152 62.0 MiB 0.05 0.00 1.72973 -67.7337 -1.72973 1.72973 0.68 0.000392695 0.000364823 0.0219802 0.0204547 34 1370 26 6.87369e+06 97816.9 618332. 2139.56 1.30 0.0832593 0.0724742 25762 151098 -1 1015 13 608 608 51492 13168 1.28867 1.28867 -65.2983 -1.28867 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0111065 0.00972696 47 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 4.01 vpr 62.07 MiB -1 -1 0.17 17528 1 0.02 -1 -1 30404 -1 -1 7 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63560 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 23.5 MiB 0.09 605 10056 2373 7370 313 62.1 MiB 0.07 0.00 2.11206 -78.5497 -2.11206 2.11206 0.67 0.000422072 0.000392985 0.0255691 0.0238238 34 1389 20 6.87369e+06 97816.9 618332. 2139.56 1.18 0.106841 0.0930413 25762 151098 -1 1234 14 660 660 60348 14534 1.34797 1.34797 -75.6162 -1.34797 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0125046 0.010949 50 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 4.05 vpr 62.18 MiB -1 -1 0.15 17476 1 0.02 -1 -1 29948 -1 -1 8 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63672 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 23.6 MiB 0.09 728 10957 2389 8188 380 62.2 MiB 0.07 0.00 2.15606 -94.7378 -2.15606 2.15606 0.68 0.000487876 0.000454841 0.0263095 0.0245419 34 1647 17 6.87369e+06 111791 618332. 2139.56 1.24 0.114196 0.100013 25762 151098 -1 1490 15 722 722 68358 15964 1.40297 1.40297 -91.1627 -1.40297 0 0 787024. 2723.27 0.21 0.05 0.13 -1 -1 0.21 0.0151007 0.0132963 58 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 4.19 vpr 62.34 MiB -1 -1 0.16 17500 1 0.03 -1 -1 29988 -1 -1 9 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63840 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 23.6 MiB 0.09 980 16046 5179 9796 1071 62.3 MiB 0.10 0.00 2.56039 -112.877 -2.56039 2.56039 0.69 0.000564608 0.000527347 0.0374872 0.0350016 34 2030 21 6.87369e+06 125765 618332. 2139.56 1.34 0.147487 0.12985 25762 151098 -1 1789 14 795 795 84552 18473 1.56397 1.56397 -108.864 -1.56397 0 0 787024. 2723.27 0.21 0.05 0.13 -1 -1 0.21 0.016502 0.0145659 66 2 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 4.53 vpr 62.94 MiB -1 -1 0.20 17760 1 0.03 -1 -1 30208 -1 -1 13 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64452 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 24.0 MiB 0.11 1359 29399 8657 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30060 -1 -1 3 11 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62856 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 22.7 MiB 0.03 62 641 164 455 22 61.4 MiB 0.01 0.00 0.817273 -12.6839 -0.817273 0.817273 0.67 0.00010533 9.6259e-05 0.00282302 0.0025714 26 209 13 6.89349e+06 42281.5 503264. 1741.40 1.82 0.0298085 0.0244578 24322 120374 -1 199 9 87 87 5417 1739 0.942573 0.942573 -14.086 -0.942573 0 0 618332. 2139.56 0.22 0.01 0.12 -1 -1 0.22 0.00325929 0.00289589 13 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 3.10 vpr 61.35 MiB -1 -1 0.15 17092 1 0.02 -1 -1 29960 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62820 13 7 48 49 1 33 23 17 17 289 -1 unnamed_device 22.6 MiB 0.04 80 1015 241 576 198 61.3 MiB 0.01 0.00 0.833073 -15.3861 -0.833073 0.833073 0.67 0.000121884 0.000111712 0.00424574 0.00389074 28 312 20 6.89349e+06 42281.5 531479. 1839.03 0.64 0.0193223 0.0163021 24610 126494 -1 244 25 292 292 17449 5462 1.08367 1.08367 -16.6538 -1.08367 0 0 648988. 2245.63 0.18 0.02 0.11 -1 -1 0.18 0.00657205 0.00555051 15 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 3.73 vpr 61.24 MiB -1 -1 0.11 17240 1 0.02 -1 -1 30064 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62712 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 22.6 MiB 0.06 110 1850 727 959 164 61.2 MiB 0.02 0.00 1.2044 -18.413 -1.2044 1.2044 0.68 0.000134194 0.00012004 0.00718063 0.0065967 26 295 32 6.89349e+06 42281.5 503264. 1741.40 1.29 0.0431683 0.0358815 24322 120374 -1 218 12 161 161 7484 2547 0.956373 0.956373 -18.2239 -0.956373 0 0 618332. 2139.56 0.17 0.01 0.11 -1 -1 0.17 0.00457467 0.00398854 17 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 4.58 vpr 61.50 MiB -1 -1 0.15 17304 1 0.02 -1 -1 30032 -1 -1 3 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62972 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 22.8 MiB 0.04 120 2097 836 1147 114 61.5 MiB 0.02 0.00 1.2154 -21.3749 -1.2154 1.2154 0.68 0.000157577 0.0001451 0.00794598 0.00731835 32 320 18 6.89349e+06 42281.5 586450. 2029.24 2.03 0.0483007 0.0402159 25474 144626 -1 237 18 158 158 8304 2719 0.96932 0.96932 -20.6745 -0.96932 0 0 744469. 2576.02 0.20 0.02 0.13 -1 -1 0.20 0.00639046 0.00545052 18 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 3.15 vpr 61.38 MiB -1 -1 0.15 17144 1 0.02 -1 -1 30004 -1 -1 3 19 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62852 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 22.6 MiB 0.04 132 2432 921 1234 277 61.4 MiB 0.02 0.00 1.2264 -24.2382 -1.2264 1.2264 0.70 0.00017559 0.000161937 0.00903211 0.00833549 26 385 13 6.89349e+06 42281.5 503264. 1741.40 0.61 0.028358 0.0243091 24322 120374 -1 326 13 188 188 11131 3367 1.12567 1.12567 -26.3034 -1.12567 0 0 618332. 2139.56 0.17 0.02 0.11 -1 -1 0.17 0.00566447 0.00489787 20 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 4.69 vpr 61.70 MiB -1 -1 0.16 17240 1 0.02 -1 -1 30076 -1 -1 3 21 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63184 21 11 76 77 1 48 35 17 17 289 -1 unnamed_device 23.3 MiB 0.07 144 2657 904 1108 645 61.7 MiB 0.02 0.00 1.2374 -27.0223 -1.2374 1.2374 0.68 0.000193191 0.000178582 0.00958407 0.0088574 32 414 15 6.89349e+06 42281.5 586450. 2029.24 2.12 0.0593495 0.0495628 25474 144626 -1 365 13 200 200 17605 4541 1.14767 1.14767 -29.691 -1.14767 0 0 744469. 2576.02 0.20 0.02 0.13 -1 -1 0.20 0.00609421 0.00526856 22 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 4.62 vpr 61.57 MiB -1 -1 0.14 17292 1 0.02 -1 -1 30000 -1 -1 4 23 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63048 23 12 83 84 1 53 39 17 17 289 -1 unnamed_device 22.9 MiB 0.05 161 3207 1169 1568 470 61.6 MiB 0.02 0.00 1.2484 -30.0849 -1.2484 1.2484 0.70 0.000208728 0.000192972 0.0107645 0.00995636 30 508 23 6.89349e+06 56375.4 556674. 1926.21 2.09 0.0559501 0.0471621 25186 138497 -1 412 16 276 276 21287 5430 1.14287 1.14287 -30.9185 -1.14287 0 0 706193. 2443.58 0.19 0.02 0.13 -1 -1 0.19 0.00749804 0.0064525 24 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 4.31 vpr 61.73 MiB -1 -1 0.15 17184 1 0.02 -1 -1 30012 -1 -1 4 25 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63208 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 23.1 MiB 0.05 194 3066 1220 1817 29 61.7 MiB 0.02 0.00 1.2594 -33.4928 -1.2594 1.2594 0.71 0.000227703 0.000210777 0.0101504 0.00939565 28 566 20 6.89349e+06 56375.4 531479. 1839.03 1.75 0.0702117 0.0590204 24610 126494 -1 508 14 334 334 23293 6293 1.16062 1.16062 -34.8765 -1.16062 0 0 648988. 2245.63 0.18 0.02 0.11 -1 -1 0.18 0.00717823 0.0062033 26 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 5.06 vpr 61.51 MiB -1 -1 0.13 17228 1 0.02 -1 -1 30056 -1 -1 4 27 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62988 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 22.8 MiB 0.05 212 3965 1580 2332 53 61.5 MiB 0.03 0.00 1.2704 -36.2189 -1.2704 1.2704 0.68 0.000237244 0.000219204 0.0124599 0.0115117 36 666 21 6.89349e+06 56375.4 648988. 2245.63 2.45 0.0794831 0.0670493 26050 158493 -1 565 17 407 407 30578 8238 1.18067 1.18067 -37.9109 -1.18067 0 0 828058. 2865.25 0.22 0.03 0.14 -1 -1 0.22 0.00861616 0.00741841 28 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 4.56 vpr 61.76 MiB -1 -1 0.10 17164 1 0.02 -1 -1 29940 -1 -1 5 29 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63240 29 15 104 105 1 74 49 17 17 289 -1 unnamed_device 23.0 MiB 0.06 267 4232 1438 1805 989 61.8 MiB 0.03 0.00 1.2814 -39.3367 -1.2814 1.2814 0.68 0.00025057 0.000231901 0.0125591 0.0116212 32 800 16 6.89349e+06 70469.2 586450. 2029.24 1.95 0.0747419 0.0634269 25474 144626 -1 696 20 474 474 53826 12663 1.07887 1.07887 -41.1685 -1.07887 0 0 744469. 2576.02 0.20 0.03 0.13 -1 -1 0.20 0.0102231 0.00876635 31 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 4.92 vpr 61.71 MiB -1 -1 0.16 17184 1 0.02 -1 -1 30348 -1 -1 5 31 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63196 31 16 111 112 1 80 52 17 17 289 -1 unnamed_device 23.2 MiB 0.08 290 5096 2068 2923 105 61.7 MiB 0.04 0.00 1.65273 -43.2743 -1.65273 1.65273 0.68 0.00026946 0.000249594 0.0148796 0.0137875 32 810 23 6.89349e+06 70469.2 586450. 2029.24 2.27 0.0753431 0.0641536 25474 144626 -1 607 17 388 388 32529 8494 1.21167 1.21167 -43.3168 -1.21167 0 0 744469. 2576.02 0.20 0.03 0.13 -1 -1 0.20 0.00970255 0.00836801 33 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 4.21 vpr 61.70 MiB -1 -1 0.13 17256 1 0.03 -1 -1 30048 -1 -1 5 33 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63176 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 23.2 MiB 0.09 305 6087 2495 3491 101 61.7 MiB 0.04 0.00 1.66373 -47.069 -1.66373 1.66373 0.68 0.000290045 0.000268814 0.0179511 0.0166518 30 713 21 6.89349e+06 70469.2 556674. 1926.21 1.48 0.0734606 0.0630285 25186 138497 -1 602 13 392 392 27294 7261 1.21167 1.21167 -46.7 -1.21167 0 0 706193. 2443.58 0.22 0.03 0.16 -1 -1 0.22 0.00853679 0.00742914 34 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 5.08 vpr 61.67 MiB -1 -1 0.13 17480 1 0.02 -1 -1 30160 -1 -1 5 37 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63148 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 23.2 MiB 0.07 342 5821 2357 3387 77 61.7 MiB 0.04 0.00 1.68573 -54.1107 -1.68573 1.68573 0.68 0.000328562 0.000305394 0.0168304 0.0156577 34 894 16 6.89349e+06 70469.2 618332. 2139.56 2.38 0.0827565 0.0708403 25762 151098 -1 786 12 419 419 34308 8532 1.35897 1.35897 -55.4515 -1.35897 0 0 787024. 2723.27 0.23 0.03 0.13 -1 -1 0.23 0.00896989 0.0078058 38 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 3.98 vpr 61.75 MiB -1 -1 0.15 17444 1 0.02 -1 -1 30440 -1 -1 6 41 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63236 41 21 146 147 1 101 68 17 17 289 -1 unnamed_device 23.1 MiB 0.07 382 7382 2994 4283 105 61.8 MiB 0.05 0.00 1.70773 -60.6787 -1.70773 1.70773 0.67 0.000356003 0.000330603 0.0200354 0.018613 34 1137 29 6.89349e+06 84563 618332. 2139.56 1.25 0.0941227 0.0810155 25762 151098 -1 896 14 497 497 49470 12006 1.27767 1.27767 -59.8203 -1.27767 0 0 787024. 2723.27 0.21 0.03 0.14 -1 -1 0.21 0.0133111 0.0116975 42 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 6.02 vpr 61.94 MiB -1 -1 0.14 17312 1 0.02 -1 -1 30336 -1 -1 7 45 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63424 45 23 160 161 1 115 75 17 17 289 -1 unnamed_device 23.3 MiB 0.09 440 8449 3423 4877 149 61.9 MiB 0.05 0.00 1.72973 -67.5802 -1.72973 1.72973 0.68 0.000388278 0.000360736 0.0217766 0.0202537 40 1047 17 6.89349e+06 98656.9 706193. 2443.58 3.27 0.145235 0.124592 26914 176310 -1 971 14 537 537 52525 12929 1.44227 1.44227 -66.651 -1.44227 0 0 926341. 3205.33 0.24 0.04 0.16 -1 -1 0.24 0.0115703 0.0100724 47 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 4.08 vpr 62.10 MiB -1 -1 0.17 17524 1 0.02 -1 -1 30324 -1 -1 7 49 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63588 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 23.5 MiB 0.08 602 10056 2329 7462 265 62.1 MiB 0.06 0.00 2.11206 -78.5198 -2.11206 2.11206 0.68 0.000430072 0.000400231 0.0253041 0.0235722 34 1406 36 6.89349e+06 98656.9 618332. 2139.56 1.35 0.116771 0.10141 25762 151098 -1 1216 11 566 566 50636 12121 1.24467 1.24467 -73.5762 -1.24467 0 0 787024. 2723.27 0.21 0.03 0.14 -1 -1 0.21 0.0105211 0.00924665 50 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 3.99 vpr 61.96 MiB -1 -1 0.16 17572 1 0.02 -1 -1 30100 -1 -1 8 57 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63452 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 23.4 MiB 0.08 735 7975 1707 6009 259 62.0 MiB 0.06 0.00 2.15606 -94.8271 -2.15606 2.15606 0.68 0.000487556 0.000454494 0.0194204 0.0181076 34 1652 13 6.89349e+06 112751 618332. 2139.56 1.22 0.107832 0.0941081 25762 151098 -1 1422 12 657 657 62311 14519 1.26667 1.26667 -86.3714 -1.26667 0 0 787024. 2723.27 0.21 0.04 0.13 -1 -1 0.21 0.0132587 0.0116877 58 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 4.10 vpr 62.23 MiB -1 -1 0.18 17400 1 0.02 -1 -1 30160 -1 -1 9 65 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63728 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 23.5 MiB 0.08 978 16046 4505 10523 1018 62.2 MiB 0.10 0.00 2.56039 -115.373 -2.56039 2.56039 0.68 0.000566344 0.000527588 0.0374318 0.0349269 34 2012 20 6.89349e+06 126845 618332. 2139.56 1.24 0.146585 0.129049 25762 151098 -1 1824 15 739 739 76313 16556 1.42297 1.42297 -105.171 -1.42297 0 0 787024. 2723.27 0.21 0.05 0.14 -1 -1 0.21 0.0176832 0.0156096 66 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 4.48 vpr 63.08 MiB -1 -1 0.15 17628 1 0.03 -1 -1 30272 -1 -1 13 97 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64592 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 24.1 MiB 0.11 1365 29399 8841 18664 1894 63.1 MiB 0.17 0.00 3.45705 -190.368 -3.45705 3.45705 0.67 0.000863648 0.000809352 0.0613637 0.0575136 34 3239 21 6.89349e+06 183220 618332. 2139.56 1.49 0.233748 0.209831 25762 151098 -1 2600 12 1016 1016 99325 23153 1.77997 1.77997 -168.573 -1.77997 0 0 787024. 2723.27 0.21 0.07 0.15 -1 -1 0.21 0.021962 0.0197184 98 2 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 6.89 vpr 63.66 MiB -1 -1 0.20 18036 1 0.04 -1 -1 30528 -1 -1 17 129 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65184 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 24.7 MiB 0.12 1975 46609 14694 27844 4071 63.7 MiB 0.26 0.01 4.35372 -287.807 -4.35372 4.35372 0.68 0.00121008 0.00113985 0.0921106 0.0866821 36 4420 32 6.89349e+06 239595 648988. 2245.63 3.65 0.429033 0.387492 26050 158493 -1 3675 14 1471 1471 153704 34188 1.98497 1.98497 -234.187 -1.98497 0 0 828058. 2865.25 0.22 0.10 0.14 -1 -1 0.22 0.0341292 0.030824 130 2 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.81 vpr 61.53 MiB -1 -1 0.14 17176 2 0.05 -1 -1 31920 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63004 9 5 28 33 1 17 16 17 17 289 -1 unnamed_device 22.7 MiB 0.01 102 56 22 34 0 61.5 MiB 0.00 0.00 1.25905 -11.4776 -1.25905 1.25905 0.35 8.882e-05 8.0374e-05 0.000503367 0.000460617 -1 -1 -1 -1 20 177 7 6.55708e+06 24110 394039. 1363.46 0.24 0.00338036 0.00301975 19870 87366 -1 145 5 37 42 2127 683 1.13885 1.13885 -10.6853 -1.13885 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00234608 0.00214041 13 6 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.75 vpr 61.79 MiB -1 -1 0.15 17260 2 0.07 -1 -1 31784 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63268 11 6 34 40 1 20 19 17 17 289 -1 unnamed_device 23.1 MiB 0.01 68 419 92 314 13 61.8 MiB 0.01 0.00 1.13885 -12.6274 -1.13885 1.13885 0.36 0.000104018 9.4606e-05 0.00207701 0.00189506 -1 -1 -1 -1 20 166 5 6.55708e+06 24110 394039. 1363.46 0.25 0.00525114 0.0047588 19870 87366 -1 137 4 34 37 1601 538 1.01865 1.01865 -12.5587 -1.01865 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00240353 0.00219298 16 7 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.70 vpr 61.61 MiB -1 -1 0.12 17184 3 0.05 -1 -1 31860 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63088 13 7 41 48 1 27 23 17 17 289 -1 unnamed_device 22.9 MiB 0.01 135 631 147 469 15 61.6 MiB 0.01 0.00 1.37725 -16.6067 -1.37725 1.37725 0.32 0.000129747 0.00011854 0.00286597 0.002624 -1 -1 -1 -1 20 273 10 6.55708e+06 36165 394039. 1363.46 0.25 0.007305 0.00653074 19870 87366 -1 227 7 76 83 3857 1249 1.25705 1.25705 -17.2319 -1.25705 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0033876 0.00303842 19 9 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.80 vpr 61.52 MiB -1 -1 0.13 17272 3 0.04 -1 -1 31840 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62992 15 8 47 55 1 35 27 17 17 289 -1 unnamed_device 23.1 MiB 0.01 246 1107 227 797 83 61.5 MiB 0.01 0.00 1.23151 -21.1845 -1.23151 1.23151 0.32 0.000140574 0.000128754 0.00439077 0.0040239 -1 -1 -1 -1 22 399 8 6.55708e+06 48220 420624. 1455.45 0.33 0.0233791 0.0196844 20158 92377 -1 374 12 138 186 9733 2657 1.23151 1.23151 -21.7797 -1.23151 0 0 500653. 1732.36 0.02 0.01 0.05 -1 -1 0.02 0.00470751 0.00408781 23 10 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.98 vpr 61.69 MiB -1 -1 0.16 17380 3 0.05 -1 -1 32048 -1 -1 6 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63172 17 9 56 65 1 37 32 17 17 289 -1 unnamed_device 23.3 MiB 0.01 141 1132 207 843 82 61.7 MiB 0.01 0.00 1.73785 -23.0011 -1.73785 1.73785 0.32 0.000177397 0.000163282 0.00448382 0.00413693 -1 -1 -1 -1 26 292 10 6.55708e+06 72330 477104. 1650.88 0.34 0.0230579 0.0195262 21022 109990 -1 253 10 116 150 5905 2088 1.73785 1.73785 -22.979 -1.73785 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00488895 0.00427019 26 14 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.00 vpr 61.60 MiB -1 -1 0.17 17588 4 0.08 -1 -1 31936 -1 -1 6 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63080 19 10 60 70 1 46 35 17 17 289 -1 unnamed_device 23.2 MiB 0.02 206 890 192 689 9 61.6 MiB 0.01 0.00 1.83817 -26.8738 -1.83817 1.83817 0.32 0.00018623 0.000172113 0.00345229 0.00318807 -1 -1 -1 -1 24 503 11 6.55708e+06 72330 448715. 1552.65 0.34 0.023586 0.0197806 20734 103517 -1 456 14 189 265 14696 4171 1.79897 1.79897 -29.1306 -1.79897 0 0 554710. 1919.41 0.02 0.02 0.09 -1 -1 0.02 0.00625358 0.00539304 29 13 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.85 vpr 61.68 MiB -1 -1 0.11 17620 4 0.06 -1 -1 31780 -1 -1 7 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63156 21 11 69 80 1 45 39 17 17 289 -1 unnamed_device 23.2 MiB 0.02 234 1425 276 1119 30 61.7 MiB 0.01 0.00 2.00308 -29.8235 -2.00308 2.00308 0.32 0.00021215 0.000195206 0.00517815 0.0047725 -1 -1 -1 -1 20 484 10 6.55708e+06 84385 394039. 1363.46 0.26 0.011519 0.0102836 19870 87366 -1 431 8 137 199 8705 2803 1.8657 1.8657 -30.3926 -1.8657 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00515178 0.00455678 33 17 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.06 vpr 61.65 MiB -1 -1 0.13 17464 5 0.06 -1 -1 32020 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63128 23 12 76 88 1 52 42 17 17 289 -1 unnamed_device 23.1 MiB 0.02 299 2130 460 1580 90 61.6 MiB 0.02 0.00 2.1851 -34.7155 -2.1851 2.1851 0.31 0.000225836 0.000208793 0.00737873 0.0068159 -1 -1 -1 -1 30 557 11 6.55708e+06 84385 526063. 1820.29 0.39 0.0385933 0.032892 21886 126133 -1 477 9 132 177 10121 2634 2.0649 2.0649 -34.6717 -2.0649 0 0 666494. 2306.21 0.03 0.01 0.10 -1 -1 0.03 0.0056861 0.00499978 36 19 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.97 vpr 61.68 MiB -1 -1 0.15 17448 5 0.06 -1 -1 32056 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63164 25 13 83 96 1 61 46 17 17 289 -1 unnamed_device 23.1 MiB 0.03 382 1604 307 1258 39 61.7 MiB 0.02 0.00 2.1433 -40.194 -2.1433 2.1433 0.32 0.0002374 0.000218617 0.00535399 0.0049428 -1 -1 -1 -1 20 750 24 6.55708e+06 96440 394039. 1363.46 0.28 0.0174527 0.0152737 19870 87366 -1 675 11 204 284 17644 4645 2.0231 2.0231 -41.4897 -2.0231 0 0 477104. 1650.88 0.02 0.02 0.08 -1 -1 0.02 0.00708701 0.00625295 39 21 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.98 vpr 61.82 MiB -1 -1 0.12 17548 5 0.06 -1 -1 31808 -1 -1 10 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 27 14 91 105 1 72 51 17 17 289 -1 unnamed_device 23.2 MiB 0.05 487 1931 345 1368 218 61.8 MiB 0.02 0.00 2.31696 -45.6334 -2.31696 2.31696 0.32 0.000303653 0.000273882 0.00640562 0.00591371 -1 -1 -1 -1 26 873 12 6.55708e+06 120550 477104. 1650.88 0.36 0.0365231 0.0313217 21022 109990 -1 816 8 208 332 18433 4780 1.9839 1.9839 -46.0894 -1.9839 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00631768 0.005585 44 24 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.92 vpr 61.82 MiB -1 -1 0.15 17672 6 0.07 -1 -1 32032 -1 -1 10 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 29 15 95 110 1 74 54 17 17 289 -1 unnamed_device 23.2 MiB 0.03 326 1992 324 1638 30 61.8 MiB 0.02 0.00 2.92362 -47.3926 -2.92362 2.92362 0.32 0.000283404 0.000262906 0.00638465 0.00592117 -1 -1 -1 -1 26 681 9 6.55708e+06 120550 477104. 1650.88 0.29 0.0229025 0.019846 21022 109990 -1 645 14 253 412 18759 5604 2.76422 2.76422 -48.0089 -2.76422 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00906397 0.00783781 46 23 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.02 vpr 61.88 MiB -1 -1 0.17 17476 6 0.07 -1 -1 31980 -1 -1 10 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63364 31 16 104 120 1 74 57 17 17 289 -1 unnamed_device 23.2 MiB 0.03 413 2455 496 1792 167 61.9 MiB 0.02 0.00 2.5437 -52.0473 -2.5437 2.5437 0.32 0.000314967 0.000292737 0.00803663 0.00746438 -1 -1 -1 -1 28 797 9 6.55708e+06 120550 500653. 1732.36 0.37 0.0394837 0.0339214 21310 115450 -1 706 7 169 223 12972 3468 2.5437 2.5437 -53.9588 -2.5437 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.0066224 0.00586415 50 27 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.89 vpr 61.88 MiB -1 -1 0.17 17512 7 0.07 -1 -1 32112 -1 -1 10 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63364 33 17 112 129 1 80 60 17 17 289 -1 unnamed_device 23.1 MiB 0.03 455 2400 450 1872 78 61.9 MiB 0.01 0.00 2.77173 -56.4743 -2.77173 2.77173 0.28 0.000151138 0.000138573 0.00382632 0.0035109 -1 -1 -1 -1 22 966 13 6.55708e+06 120550 420624. 1455.45 0.24 0.0223788 0.0192259 20158 92377 -1 820 14 243 337 17062 5047 2.6619 2.6619 -58.7642 -2.6619 0 0 500653. 1732.36 0.02 0.02 0.08 -1 -1 0.02 0.010673 0.0092982 54 30 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.09 vpr 61.96 MiB -1 -1 0.17 17540 7 0.06 -1 -1 31948 -1 -1 13 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63444 37 19 127 146 1 95 69 17 17 289 -1 unnamed_device 23.1 MiB 0.04 580 5286 1128 3575 583 62.0 MiB 0.04 0.00 2.83296 -65.8925 -2.83296 2.83296 0.32 0.000370259 0.000344095 0.0149742 0.013844 -1 -1 -1 -1 28 987 8 6.55708e+06 156715 500653. 1732.36 0.38 0.0517571 0.0451646 21310 115450 -1 947 6 224 327 15796 4347 2.6201 2.6201 -68.3998 -2.6201 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.00692764 0.00618013 63 35 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.16 vpr 61.99 MiB -1 -1 0.15 17432 8 0.07 -1 -1 31996 -1 -1 14 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63480 41 21 139 160 1 106 76 17 17 289 -1 unnamed_device 22.9 MiB 0.04 588 8396 2008 5342 1046 62.0 MiB 0.05 0.00 3.1799 -77.5868 -3.1799 3.1799 0.34 0.000399995 0.000371199 0.0222085 0.0206233 -1 -1 -1 -1 26 1120 12 6.55708e+06 168770 477104. 1650.88 0.38 0.0643844 0.0565876 21022 109990 -1 1022 10 319 425 23447 6363 3.1799 3.1799 -79.2365 -3.1799 0 0 585099. 2024.56 0.03 0.02 0.12 -1 -1 0.03 0.00931512 0.00841851 67 37 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.19 vpr 62.45 MiB -1 -1 0.13 17484 9 0.07 -1 -1 31884 -1 -1 15 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63948 45 23 153 176 1 107 83 17 17 289 -1 unnamed_device 23.1 MiB 0.05 536 7643 1816 4897 930 62.4 MiB 0.05 0.00 4.01419 -88.5998 -4.01419 4.01419 0.32 0.000435711 0.000404292 0.0198098 0.0183771 -1 -1 -1 -1 26 1149 13 6.55708e+06 180825 477104. 1650.88 0.44 0.0661535 0.0580745 21022 109990 -1 1003 13 321 492 25700 7436 3.87922 3.87922 -89.4779 -3.87922 0 0 585099. 2024.56 0.03 0.03 0.10 -1 -1 0.03 0.0114958 0.0102772 73 41 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.19 vpr 62.10 MiB -1 -1 0.13 17776 10 0.07 -1 -1 32012 -1 -1 15 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63588 49 25 166 191 1 117 89 17 17 289 -1 unnamed_device 22.7 MiB 0.04 524 8207 1797 5151 1259 62.1 MiB 0.05 0.00 4.48062 -100.236 -4.48062 4.48062 0.32 0.000471573 0.000438453 0.0210235 0.0195468 -1 -1 -1 -1 26 1157 12 6.55708e+06 180825 477104. 1650.88 0.44 0.070761 0.0623165 21022 109990 -1 1039 10 321 455 24838 7158 4.40948 4.40948 -103.002 -4.40948 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0115319 0.01024 78 44 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.40 vpr 62.41 MiB -1 -1 0.16 17836 11 0.07 -1 -1 32112 -1 -1 20 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 57 29 198 227 1 147 106 17 17 289 -1 unnamed_device 23.0 MiB 0.05 782 8606 1708 6393 505 62.4 MiB 0.06 0.00 4.94665 -134.466 -4.94665 4.94665 0.33 0.000571874 0.000532504 0.0215301 0.0200481 -1 -1 -1 -1 28 1522 13 6.55708e+06 241100 500653. 1732.36 0.43 0.0827513 0.0729032 21310 115450 -1 1371 8 367 517 27034 7537 4.59642 4.59642 -133.949 -4.59642 0 0 612192. 2118.31 0.03 0.03 0.11 -1 -1 0.03 0.0120118 0.0107143 93 56 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.50 vpr 62.60 MiB -1 -1 0.19 17800 13 0.08 -1 -1 32188 -1 -1 20 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 65 33 224 257 1 164 118 17 17 289 -1 unnamed_device 22.9 MiB 0.06 928 17169 4443 10653 2073 62.6 MiB 0.10 0.00 5.28408 -153.681 -5.28408 5.28408 0.36 0.000649312 0.000604542 0.0408491 0.0380181 -1 -1 -1 -1 30 1659 12 6.55708e+06 241100 526063. 1820.29 0.47 0.109688 0.0977858 21886 126133 -1 1555 13 429 584 31745 8729 5.08288 5.08288 -153.594 -5.08288 0 0 666494. 2306.21 0.04 0.03 0.12 -1 -1 0.04 0.016224 0.0145393 107 62 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.63 vpr 63.23 MiB -1 -1 0.20 18112 19 0.10 -1 -1 32232 -1 -1 34 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 97 49 340 389 1 260 180 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1520 22532 5263 15517 1752 63.2 MiB 0.13 0.00 7.62655 -301.388 -7.62655 7.62655 0.29 0.000991752 0.000926486 0.0481233 0.0448481 -1 -1 -1 -1 30 2687 13 6.55708e+06 409870 526063. 1820.29 0.51 0.154423 0.138579 21886 126133 -1 2432 11 662 955 55712 14661 7.28333 7.28333 -297.521 -7.28333 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0249464 0.0224501 165 98 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.24 vpr 63.93 MiB -1 -1 0.28 18296 26 0.13 -1 -1 32396 -1 -1 41 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65464 129 65 453 518 1 334 235 17 17 289 -1 unnamed_device 24.1 MiB 0.10 1951 55259 16458 32932 5869 63.9 MiB 0.28 0.00 10.6369 -487.594 -10.6369 10.6369 0.34 0.00134162 0.00125451 0.10975 0.102432 -1 -1 -1 -1 30 3742 35 6.55708e+06 494255 526063. 1820.29 0.78 0.289369 0.262587 21886 126133 -1 3039 12 909 1148 67590 18881 10.0187 10.0187 -472.64 -10.0187 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0361792 0.0327806 210 131 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.49 abc 29.28 MiB -1 -1 0.10 17348 1 0.02 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.58 abc 29.28 MiB -1 -1 0.12 17328 1 0.03 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23928 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.66 abc 29.27 MiB -1 -1 0.14 17352 1 0.02 -1 -1 29972 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24144 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.66 abc 29.22 MiB -1 -1 0.14 17312 1 0.02 -1 -1 29924 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24024 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.63 abc 29.30 MiB -1 -1 0.14 17436 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.61 abc 29.30 MiB -1 -1 0.15 17384 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24072 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.58 abc 29.34 MiB -1 -1 0.16 17320 1 0.03 -1 -1 30048 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23932 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.55 abc 29.36 MiB -1 -1 0.14 17188 1 0.02 -1 -1 30068 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24076 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.83 abc 29.29 MiB -1 -1 0.16 17156 1 0.02 -1 -1 29992 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23980 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.67 abc 29.23 MiB -1 -1 0.15 17352 1 0.02 -1 -1 29936 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23964 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.64 abc 29.44 MiB -1 -1 0.15 17296 1 0.02 -1 -1 30144 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24080 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.82 abc 29.46 MiB -1 -1 0.16 17372 1 0.02 -1 -1 30164 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24028 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.90 abc 29.28 MiB -1 -1 0.16 17348 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24032 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.13 abc 29.58 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30288 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24004 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.11 abc 29.28 MiB -1 -1 0.15 17584 1 0.03 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24108 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 1.33 abc 29.30 MiB -1 -1 0.15 17496 1 0.04 -1 -1 30004 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24068 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 1.13 abc 29.30 MiB -1 -1 0.16 17684 1 0.02 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24012 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.59 abc 29.43 MiB -1 -1 0.16 17528 1 0.02 -1 -1 30140 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24212 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.61 abc 29.43 MiB -1 -1 0.14 17660 1 0.03 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24056 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.60 abc 29.41 MiB -1 -1 0.12 17788 1 0.03 -1 -1 30116 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24088 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 1.42 abc 29.55 MiB -1 -1 0.21 18072 1 0.03 -1 -1 30256 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24028 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.58 abc 29.32 MiB -1 -1 0.15 17340 1 0.02 -1 -1 30024 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23756 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.56 abc 29.36 MiB -1 -1 0.14 17204 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23848 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.46 abc 29.20 MiB -1 -1 0.08 17420 1 0.02 -1 -1 29904 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23768 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.55 abc 29.36 MiB -1 -1 0.16 17368 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23832 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.50 abc 29.30 MiB -1 -1 0.11 17336 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23792 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.56 abc 29.30 MiB -1 -1 0.14 17268 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23780 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.64 abc 29.29 MiB -1 -1 0.15 17364 1 0.03 -1 -1 29996 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23676 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.77 abc 29.50 MiB -1 -1 0.15 17480 1 0.02 -1 -1 30208 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23908 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.87 abc 29.35 MiB -1 -1 0.13 17308 1 0.03 -1 -1 30056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23860 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.78 abc 29.34 MiB -1 -1 0.15 17316 1 0.02 -1 -1 30044 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23840 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.90 abc 29.28 MiB -1 -1 0.13 17320 1 0.03 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23792 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.55 abc 29.28 MiB -1 -1 0.15 17412 1 0.02 -1 -1 29984 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23760 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.57 abc 29.43 MiB -1 -1 0.14 17428 1 0.02 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23804 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.59 abc 29.38 MiB -1 -1 0.15 17580 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23888 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.59 abc 29.28 MiB -1 -1 0.16 17688 1 0.02 -1 -1 29980 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23704 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.54 abc 29.29 MiB -1 -1 0.14 17696 1 0.02 -1 -1 29988 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23960 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.53 abc 29.36 MiB -1 -1 0.09 17412 1 0.02 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.64 abc 29.38 MiB -1 -1 0.15 17288 1 0.03 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23700 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.68 abc 29.30 MiB -1 -1 0.17 17596 1 0.03 -1 -1 30000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23696 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.67 abc 29.53 MiB -1 -1 0.14 17704 1 0.03 -1 -1 30236 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.81 abc 29.84 MiB -1 -1 0.22 18144 1 0.04 -1 -1 30556 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23768 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.67 vpr 61.95 MiB -1 -1 0.09 17252 1 0.03 -1 -1 30116 -1 -1 3 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63432 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 23.2 MiB 0.01 145 80 29 46 5 61.9 MiB 0.00 0.00 0.83871 -12.0914 -0.83871 0.83871 0.32 8.9493e-05 8.1196e-05 0.000627793 0.000575929 -1 -1 -1 -1 20 218 6 6.64007e+06 37674 394039. 1363.46 0.25 0.00366787 0.00331915 20530 87850 -1 213 8 56 56 3444 969 0.890248 0.890248 -12.2124 -0.890248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0028001 0.00250588 14 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.81 vpr 61.82 MiB -1 -1 0.15 17384 1 0.02 -1 -1 29928 -1 -1 4 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 23.1 MiB 0.01 179 525 133 355 37 61.8 MiB 0.01 0.00 0.803048 -13.1622 -0.803048 0.803048 0.33 0.000104816 9.5546e-05 0.00232117 0.00211796 -1 -1 -1 -1 20 294 8 6.64007e+06 50232 394039. 1363.46 0.25 0.00578063 0.00517738 20530 87850 -1 279 8 74 74 5640 1476 0.923248 0.923248 -15.592 -0.923248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00307315 0.00274174 17 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.86 vpr 61.86 MiB -1 -1 0.14 17352 1 0.02 -1 -1 30052 -1 -1 5 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63344 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 23.5 MiB 0.01 158 889 183 672 34 61.9 MiB 0.01 0.00 0.825048 -14.9551 -0.825048 0.825048 0.32 0.00012299 0.000112599 0.00344711 0.00315992 -1 -1 -1 -1 22 332 15 6.64007e+06 62790 420624. 1455.45 0.31 0.0177773 0.0149893 20818 92861 -1 288 10 103 103 5874 1694 0.934248 0.934248 -16.7505 -0.934248 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.00384738 0.00340089 20 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.89 vpr 61.98 MiB -1 -1 0.15 17472 1 0.02 -1 -1 30136 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63468 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.6 MiB 0.02 130 827 161 522 144 62.0 MiB 0.01 0.00 1.18536 -16.9426 -1.18536 1.18536 0.32 0.000141038 0.000129717 0.00333865 0.00306739 -1 -1 -1 -1 22 336 15 6.64007e+06 50232 420624. 1455.45 0.34 0.0179109 0.0151424 20818 92861 -1 281 7 118 118 7761 2504 1.08545 1.08545 -19.5322 -1.08545 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.0039426 0.00354868 22 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.04 vpr 61.95 MiB -1 -1 0.14 17348 1 0.02 -1 -1 30048 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63440 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.5 MiB 0.02 156 1759 570 827 362 62.0 MiB 0.02 0.00 1.19636 -19.8289 -1.19636 1.19636 0.32 0.000158366 0.000145724 0.00632531 0.00582349 -1 -1 -1 -1 32 266 11 6.64007e+06 62790 554710. 1919.41 0.38 0.0232912 0.0199009 22834 132086 -1 249 10 97 97 4881 1477 0.834048 0.834048 -18.8492 -0.834048 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00447744 0.00392841 25 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.90 vpr 61.86 MiB -1 -1 0.14 17316 1 0.03 -1 -1 30144 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63348 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.4 MiB 0.02 160 1574 392 922 260 61.9 MiB 0.02 0.00 1.20736 -22.28 -1.20736 1.20736 0.31 0.000177199 0.000163665 0.00559114 0.00516294 -1 -1 -1 -1 22 389 20 6.64007e+06 62790 420624. 1455.45 0.33 0.0271204 0.0230692 20818 92861 -1 335 13 170 170 11128 3516 1.05245 1.05245 -23.8346 -1.05245 0 0 500653. 1732.36 0.03 0.02 0.09 -1 -1 0.03 0.00547305 0.00480176 28 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.93 vpr 62.00 MiB -1 -1 0.15 17268 1 0.03 -1 -1 30160 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63488 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 326 2054 512 1388 154 62.0 MiB 0.02 0.00 1.21836 -28.0305 -1.21836 1.21836 0.32 0.000193986 0.000179202 0.0069198 0.00639758 -1 -1 -1 -1 26 550 12 6.64007e+06 75348 477104. 1650.88 0.35 0.0275302 0.0234892 21682 110474 -1 504 11 163 163 10372 2794 1.00925 1.00925 -29.7279 -1.00925 0 0 585099. 2024.56 0.03 0.02 0.10 -1 -1 0.03 0.00561273 0.00490548 31 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.92 vpr 62.17 MiB -1 -1 0.10 17364 1 0.03 -1 -1 30004 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63660 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.5 MiB 0.02 202 2274 577 1358 339 62.2 MiB 0.02 0.00 1.22936 -27.3302 -1.22936 1.22936 0.32 0.000217044 0.000200805 0.00744746 0.00689241 -1 -1 -1 -1 26 516 20 6.64007e+06 87906 477104. 1650.88 0.37 0.03361 0.0286167 21682 110474 -1 423 19 254 254 15495 4842 1.14165 1.14165 -28.5397 -1.14165 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00847906 0.00723997 35 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.03 vpr 62.03 MiB -1 -1 0.13 17356 1 0.02 -1 -1 30120 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63516 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 23.5 MiB 0.02 225 3162 1067 1505 590 62.0 MiB 0.03 0.00 1.24036 -30.3091 -1.24036 1.24036 0.32 0.000223716 0.000206705 0.00935455 0.00864973 -1 -1 -1 -1 28 585 26 6.64007e+06 100464 500653. 1732.36 0.41 0.0378559 0.0324088 21970 115934 -1 409 25 362 362 24657 7379 1.02145 1.02145 -29.5255 -1.02145 0 0 612192. 2118.31 0.04 0.03 0.10 -1 -1 0.04 0.00908575 0.00781132 38 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.07 vpr 62.03 MiB -1 -1 0.15 17336 1 0.02 -1 -1 30088 -1 -1 9 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63520 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 23.5 MiB 0.02 251 4650 1464 2253 933 62.0 MiB 0.03 0.00 1.25136 -32.7881 -1.25136 1.25136 0.32 0.000239703 0.00022173 0.0129775 0.0119987 -1 -1 -1 -1 32 519 22 6.64007e+06 113022 554710. 1919.41 0.41 0.0419733 0.0362927 22834 132086 -1 437 14 276 276 16327 5300 1.03125 1.03125 -33.0873 -1.03125 0 0 701300. 2426.64 0.03 0.02 0.12 -1 -1 0.03 0.00771732 0.00669493 41 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.96 vpr 62.14 MiB -1 -1 0.15 17348 1 0.02 -1 -1 29924 -1 -1 9 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63628 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 23.5 MiB 0.01 462 4409 1391 2113 905 62.1 MiB 0.03 0.00 1.26236 -39.7652 -1.26236 1.26236 0.32 0.000252152 0.000233455 0.012075 0.0111778 -1 -1 -1 -1 26 812 23 6.64007e+06 113022 477104. 1650.88 0.39 0.0429496 0.0370839 21682 110474 -1 713 17 323 323 26583 6736 1.03125 1.03125 -39.6574 -1.03125 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.00919565 0.00794342 44 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.09 vpr 62.16 MiB -1 -1 0.15 17408 1 0.02 -1 -1 30248 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63656 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.5 MiB 0.03 343 4978 1636 2249 1093 62.2 MiB 0.04 0.00 1.62267 -39.5838 -1.62267 1.62267 0.30 0.000273462 0.000253412 0.0135717 0.0125654 -1 -1 -1 -1 30 686 17 6.64007e+06 113022 526063. 1820.29 0.40 0.0434449 0.0377212 22546 126617 -1 539 11 219 219 10604 3260 0.95891 0.95891 -36.3522 -0.95891 0 0 666494. 2306.21 0.03 0.02 0.10 -1 -1 0.03 0.00745402 0.00655316 46 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.01 vpr 62.13 MiB -1 -1 0.08 17640 1 0.02 -1 -1 30132 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63624 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.4 MiB 0.03 352 6329 2210 2989 1130 62.1 MiB 0.04 0.00 1.63367 -42.2226 -1.63367 1.63367 0.32 0.000292013 0.000271082 0.0171275 0.0158779 -1 -1 -1 -1 28 736 12 6.64007e+06 113022 500653. 1732.36 0.42 0.0478919 0.0418393 21970 115934 -1 618 18 335 335 18999 5605 1.21545 1.21545 -44.5486 -1.21545 0 0 612192. 2118.31 0.03 0.03 0.08 -1 -1 0.03 0.0108162 0.00934396 49 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.08 vpr 62.25 MiB -1 -1 0.14 17540 1 0.02 -1 -1 30084 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.5 MiB 0.03 393 6867 2746 3975 146 62.2 MiB 0.05 0.00 1.65567 -49.3018 -1.65567 1.65567 0.32 0.000329974 0.000306635 0.0176624 0.0164096 -1 -1 -1 -1 30 805 15 6.64007e+06 138138 526063. 1820.29 0.41 0.0534439 0.0465752 22546 126617 -1 630 14 325 325 20407 5991 1.07325 1.07325 -45.7613 -1.07325 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0100761 0.0087606 55 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.04 vpr 62.60 MiB -1 -1 0.13 17640 1 0.03 -1 -1 30388 -1 -1 13 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 23.3 MiB 0.02 587 9239 3659 4903 677 62.6 MiB 0.06 0.00 1.67767 -57.8173 -1.67767 1.67767 0.32 0.000360642 0.000335237 0.0220756 0.0205309 -1 -1 -1 -1 30 1014 13 6.64007e+06 163254 526063. 1820.29 0.42 0.0603789 0.0531045 22546 126617 -1 868 10 304 304 26082 6742 1.02025 1.02025 -52.0508 -1.02025 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.00886711 0.00781227 62 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.27 vpr 62.54 MiB -1 -1 0.16 17708 1 0.02 -1 -1 30284 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64044 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 23.2 MiB 0.03 505 10228 3751 5231 1246 62.5 MiB 0.06 0.00 1.69967 -61.6923 -1.69967 1.69967 0.32 0.000396366 0.000369082 0.0236606 0.0219962 -1 -1 -1 -1 32 1098 29 6.64007e+06 175812 554710. 1919.41 0.53 0.0745634 0.0654141 22834 132086 -1 841 14 524 524 35053 10407 1.18565 1.18565 -55.6154 -1.18565 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0118029 0.0103314 68 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.22 vpr 62.62 MiB -1 -1 0.14 17656 1 0.03 -1 -1 30336 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64128 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.3 MiB 0.04 715 8278 1733 6367 178 62.6 MiB 0.06 0.00 2.07098 -71.4065 -2.07098 2.07098 0.32 0.000425886 0.000396892 0.0193216 0.0179715 -1 -1 -1 -1 30 1249 15 6.64007e+06 175812 526063. 1820.29 0.44 0.0656005 0.0577432 22546 126617 -1 1106 11 343 343 25695 6324 1.09525 1.09525 -65.1787 -1.09525 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0113828 0.0101237 73 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.31 vpr 62.69 MiB -1 -1 0.16 17512 1 0.03 -1 -1 30076 -1 -1 18 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64196 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 23.3 MiB 0.04 774 16452 3708 11655 1089 62.7 MiB 0.10 0.00 2.11498 -86.7435 -2.11498 2.11498 0.32 0.000485084 0.000450927 0.0341069 0.0317077 -1 -1 -1 -1 32 1465 18 6.64007e+06 226044 554710. 1919.41 0.49 0.0895901 0.0796678 22834 132086 -1 1213 17 542 542 36079 10159 1.35645 1.35645 -81.4884 -1.35645 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.016593 0.0145733 86 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.38 vpr 62.91 MiB -1 -1 0.18 17672 1 0.03 -1 -1 30064 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.3 MiB 0.05 1165 18135 6420 10093 1622 62.9 MiB 0.11 0.00 2.50829 -108.778 -2.50829 2.50829 0.32 0.0005667 0.000528433 0.0374509 0.0349335 -1 -1 -1 -1 30 1825 43 6.64007e+06 238602 526063. 1820.29 0.51 0.122573 0.10861 22546 126617 -1 1603 14 500 500 39832 9325 1.21425 1.21425 -91.6209 -1.21425 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.016578 0.0146599 97 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.65 vpr 63.45 MiB -1 -1 0.17 17900 1 0.03 -1 -1 30280 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64976 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.9 MiB 0.07 1660 32449 9442 20195 2812 63.5 MiB 0.20 0.00 3.38291 -180.139 -3.38291 3.38291 0.32 0.000868353 0.000813665 0.0603321 0.056479 -1 -1 -1 -1 30 2741 24 6.64007e+06 364182 526063. 1820.29 0.58 0.167976 0.151769 22546 126617 -1 2404 13 827 827 63818 16162 1.39605 1.39605 -140.523 -1.39605 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0236694 0.0212549 145 2 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.96 vpr 63.93 MiB -1 -1 0.19 18156 1 0.03 -1 -1 30516 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.4 MiB 0.11 2246 49637 16069 29592 3976 63.9 MiB 0.33 0.01 4.25753 -269.223 -4.25753 4.25753 0.32 0.00123279 0.00116168 0.0889312 0.0837218 -1 -1 -1 -1 32 3518 14 6.64007e+06 489762 554710. 1919.41 0.66 0.226555 0.20755 22834 132086 -1 3131 12 959 959 74779 19366 1.56805 1.56805 -190.941 -1.56805 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0304292 0.0275916 193 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 1.70 vpr 61.73 MiB -1 -1 0.12 17344 1 0.03 -1 -1 29928 -1 -1 3 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63216 9 5 34 35 1 20 17 17 17 289 -1 unnamed_device 22.9 MiB 0.01 148 80 29 46 5 61.7 MiB 0.00 0.00 0.83871 -11.7447 -0.83871 0.83871 0.32 8.8927e-05 8.028e-05 0.000604437 0.000548194 -1 -1 -1 -1 20 230 8 6.65987e+06 38034 394039. 1363.46 0.25 0.00388017 0.00347642 20530 87850 -1 214 10 61 61 5414 1452 0.83871 0.83871 -11.8866 -0.83871 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0031468 0.00280409 14 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.72 vpr 61.69 MiB -1 -1 0.14 17312 1 0.02 -1 -1 29920 -1 -1 4 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63168 11 6 41 42 1 26 21 17 17 289 -1 unnamed_device 23.0 MiB 0.01 189 525 130 355 40 61.7 MiB 0.01 0.00 0.803048 -13.1363 -0.803048 0.803048 0.32 0.000104272 9.5105e-05 0.00233488 0.00212885 -1 -1 -1 -1 20 304 9 6.65987e+06 50712 394039. 1363.46 0.26 0.00586479 0.00523143 20530 87850 -1 282 10 105 105 8718 2335 0.83871 0.83871 -14.5944 -0.83871 0 0 477104. 1650.88 0.03 0.01 0.08 -1 -1 0.03 0.00378422 0.00342251 17 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.86 vpr 61.82 MiB -1 -1 0.13 17280 1 0.02 -1 -1 29868 -1 -1 5 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 13 7 48 49 1 32 25 17 17 289 -1 unnamed_device 23.4 MiB 0.01 147 1105 244 814 47 61.8 MiB 0.01 0.00 0.830189 -14.844 -0.830189 0.830189 0.33 0.00012577 0.000112704 0.00426613 0.00390409 -1 -1 -1 -1 26 305 15 6.65987e+06 63390 477104. 1650.88 0.34 0.0191538 0.0162467 21682 110474 -1 272 12 128 128 8327 2403 0.950389 0.950389 -16.4625 -0.950389 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00423977 0.00371064 20 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.02 vpr 61.80 MiB -1 -1 0.16 17392 1 0.02 -1 -1 30000 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63288 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.4 MiB 0.01 132 947 214 545 188 61.8 MiB 0.01 0.00 1.20253 -16.9819 -1.20253 1.20253 0.34 0.00014165 0.000130082 0.00397733 0.00363354 -1 -1 -1 -1 32 286 17 6.65987e+06 50712 554710. 1919.41 0.38 0.0203804 0.0172185 22834 132086 -1 207 12 103 103 5880 1787 0.856048 0.856048 -16.2356 -0.856048 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00468142 0.00409653 22 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.96 vpr 61.77 MiB -1 -1 0.14 17420 1 0.02 -1 -1 30048 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63256 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.4 MiB 0.02 169 1039 221 683 135 61.8 MiB 0.01 0.00 1.19636 -19.6785 -1.19636 1.19636 0.34 0.000160216 0.000147534 0.00392966 0.00362469 -1 -1 -1 -1 30 342 14 6.65987e+06 63390 526063. 1820.29 0.37 0.0217562 0.0183847 22546 126617 -1 290 13 143 143 7116 2212 0.823048 0.823048 -19.6378 -0.823048 0 0 666494. 2306.21 0.03 0.01 0.10 -1 -1 0.03 0.00533708 0.00464817 25 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 1.96 vpr 61.78 MiB -1 -1 0.10 17400 1 0.02 -1 -1 30056 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63264 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.3 MiB 0.02 158 1684 407 960 317 61.8 MiB 0.02 0.00 1.20736 -22.0789 -1.20736 1.20736 0.32 0.000176486 0.000162987 0.00597002 0.0055165 -1 -1 -1 -1 30 316 15 6.65987e+06 63390 526063. 1820.29 0.37 0.0258595 0.0220154 22546 126617 -1 281 20 183 183 9032 2990 1.07445 1.07445 -22.6488 -1.07445 0 0 666494. 2306.21 0.05 0.02 0.14 -1 -1 0.05 0.00796327 0.00683749 28 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 1.96 vpr 61.98 MiB -1 -1 0.14 17436 1 0.02 -1 -1 30148 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63472 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.4 MiB 0.02 335 1865 426 1314 125 62.0 MiB 0.02 0.00 1.21836 -28.0156 -1.21836 1.21836 0.32 0.000195988 0.000181389 0.00640653 0.00592412 -1 -1 -1 -1 26 555 11 6.65987e+06 76068 477104. 1650.88 0.35 0.0272629 0.0232932 21682 110474 -1 547 16 214 214 18567 4835 1.08545 1.08545 -31.2059 -1.08545 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00706697 0.00607694 31 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.03 vpr 62.06 MiB -1 -1 0.16 17404 1 0.02 -1 -1 30128 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63552 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.4 MiB 0.02 204 3498 1194 1551 753 62.1 MiB 0.03 0.00 1.22936 -27.6572 -1.22936 1.22936 0.32 0.000212462 0.000196166 0.0109339 0.0101005 -1 -1 -1 -1 30 454 21 6.65987e+06 88746 526063. 1820.29 0.39 0.0363204 0.0312013 22546 126617 -1 361 18 221 221 11264 3655 1.04739 1.04739 -26.9812 -1.04739 0 0 666494. 2306.21 0.03 0.02 0.10 -1 -1 0.03 0.00812448 0.00696129 35 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.99 vpr 61.94 MiB -1 -1 0.15 17252 1 0.02 -1 -1 29996 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63428 25 13 90 91 1 61 46 17 17 289 -1 unnamed_device 23.4 MiB 0.02 266 3244 1063 1597 584 61.9 MiB 0.03 0.00 1.24036 -31.1975 -1.24036 1.24036 0.32 0.000180091 0.000164931 0.00943785 0.00872483 -1 -1 -1 -1 28 564 34 6.65987e+06 101424 500653. 1732.36 0.43 0.046281 0.0393218 21970 115934 -1 503 13 227 227 15114 4347 1.14045 1.14045 -33.3649 -1.14045 0 0 612192. 2118.31 0.03 0.02 0.11 -1 -1 0.03 0.00698344 0.00607333 38 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.09 vpr 62.05 MiB -1 -1 0.15 17416 1 0.02 -1 -1 29976 -1 -1 9 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63544 27 14 97 98 1 67 50 17 17 289 -1 unnamed_device 23.4 MiB 0.02 267 4650 1648 2149 853 62.1 MiB 0.04 0.00 1.25136 -33.284 -1.25136 1.25136 0.32 0.000283328 0.000262351 0.0142241 0.0131692 -1 -1 -1 -1 32 627 21 6.65987e+06 114102 554710. 1919.41 0.42 0.0429261 0.0372136 22834 132086 -1 519 21 333 333 18881 5985 1.12945 1.12945 -35.2713 -1.12945 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0149715 0.0126565 41 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.07 vpr 61.92 MiB -1 -1 0.15 17644 1 0.02 -1 -1 29984 -1 -1 9 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63408 29 15 104 105 1 73 53 17 17 289 -1 unnamed_device 23.3 MiB 0.02 324 3518 788 2107 623 61.9 MiB 0.03 0.00 1.26236 -35.6797 -1.26236 1.26236 0.32 0.000253071 0.000234583 0.00979541 0.0090734 -1 -1 -1 -1 30 698 25 6.65987e+06 114102 526063. 1820.29 0.42 0.0425967 0.0366082 22546 126617 -1 520 15 327 327 17260 5451 1.02039 1.02039 -33.4205 -1.02039 0 0 666494. 2306.21 0.03 0.02 0.08 -1 -1 0.03 0.00850795 0.00740024 44 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.14 vpr 61.97 MiB -1 -1 0.16 17636 1 0.02 -1 -1 30264 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63460 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.3 MiB 0.02 363 4978 1495 2401 1082 62.0 MiB 0.04 0.00 1.62267 -39.2597 -1.62267 1.62267 0.32 0.000271456 0.000251613 0.0137065 0.0126797 -1 -1 -1 -1 28 787 18 6.65987e+06 114102 500653. 1732.36 0.43 0.0450106 0.0390537 21970 115934 -1 646 20 384 384 28172 7864 1.10039 1.10039 -40.1031 -1.10039 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0116488 0.010003 46 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.15 vpr 61.95 MiB -1 -1 0.15 17460 1 0.02 -1 -1 30056 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63440 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.3 MiB 0.02 358 6329 2576 3638 115 62.0 MiB 0.05 0.00 1.63367 -43.0819 -1.63367 1.63367 0.32 0.000297215 0.00027577 0.0173583 0.0161231 -1 -1 -1 -1 30 697 17 6.65987e+06 114102 526063. 1820.29 0.41 0.0506732 0.0443138 22546 126617 -1 563 18 309 309 15903 4551 0.975189 0.975189 -38.2274 -0.975189 0 0 666494. 2306.21 0.03 0.03 0.09 -1 -1 0.03 0.0107508 0.00928908 49 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.29 vpr 62.15 MiB -1 -1 0.17 17580 1 0.02 -1 -1 30004 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63640 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.3 MiB 0.03 395 6867 2582 3609 676 62.1 MiB 0.05 0.00 1.65567 -48.7086 -1.65567 1.65567 0.32 0.000325622 0.000302353 0.0174514 0.0161951 -1 -1 -1 -1 28 927 37 6.65987e+06 139458 500653. 1732.36 0.49 0.0658178 0.0568171 21970 115934 -1 701 14 374 374 29107 8630 1.23745 1.23745 -49.5635 -1.23745 0 0 612192. 2118.31 0.02 0.02 0.07 -1 -1 0.02 0.00594303 0.00527331 55 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.41 vpr 62.28 MiB -1 -1 0.12 17468 1 0.02 -1 -1 30460 -1 -1 13 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63772 41 21 146 147 1 102 75 17 17 289 -1 unnamed_device 23.0 MiB 0.03 491 9081 3707 5187 187 62.3 MiB 0.06 0.00 1.67767 -56.6155 -1.67767 1.67767 0.32 0.00035997 0.000334363 0.0218976 0.020333 -1 -1 -1 -1 30 1037 25 6.65987e+06 164814 526063. 1820.29 0.49 0.0667016 0.0582429 22546 126617 -1 743 15 369 369 22934 6790 1.02419 1.02419 -50.6361 -1.02419 0 0 666494. 2306.21 0.03 0.03 0.10 -1 -1 0.03 0.0117394 0.0102506 62 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 3.61 vpr 62.31 MiB -1 -1 0.11 17580 1 0.02 -1 -1 30308 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 45 23 160 161 1 114 82 17 17 289 -1 unnamed_device 23.1 MiB 0.03 499 10228 3488 4555 2185 62.3 MiB 0.06 0.00 1.69967 -61.5408 -1.69967 1.69967 0.32 0.000393075 0.000365679 0.0237597 0.0221074 -1 -1 -1 -1 30 1113 21 6.65987e+06 177492 526063. 1820.29 1.46 0.127983 0.11047 22546 126617 -1 863 16 593 593 46003 13579 1.18459 1.18459 -55.1595 -1.18459 0 0 666494. 2306.21 0.03 0.04 0.10 -1 -1 0.03 0.0130362 0.0113889 68 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.71 vpr 62.41 MiB -1 -1 0.16 17728 1 0.02 -1 -1 30344 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.1 MiB 0.03 627 5353 1046 4033 274 62.4 MiB 0.04 0.00 2.07098 -70.3136 -2.07098 2.07098 0.32 0.000433307 0.000403645 0.0129451 0.0120394 -1 -1 -1 -1 32 1170 15 6.65987e+06 177492 554710. 1919.41 0.45 0.0588027 0.0514064 22834 132086 -1 1054 17 432 432 30738 8937 1.32345 1.32345 -69.7201 -1.32345 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0145867 0.0127516 73 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.29 vpr 62.52 MiB -1 -1 0.16 17584 1 0.04 -1 -1 30108 -1 -1 18 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64016 57 29 202 203 1 143 104 17 17 289 -1 unnamed_device 23.4 MiB 0.04 750 10596 2249 7776 571 62.5 MiB 0.07 0.00 2.11498 -85.1831 -2.11498 2.11498 0.31 0.000494895 0.000460975 0.0226536 0.02111 -1 -1 -1 -1 32 1479 15 6.65987e+06 228204 554710. 1919.41 0.47 0.0757256 0.0669986 22834 132086 -1 1199 18 520 520 35837 10747 1.36745 1.36745 -82.2692 -1.36745 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0174867 0.0153336 86 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.36 vpr 62.79 MiB -1 -1 0.14 17900 1 0.03 -1 -1 29940 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.2 MiB 0.04 1148 18135 6273 10055 1807 62.8 MiB 0.11 0.00 2.50829 -108.743 -2.50829 2.50829 0.31 0.000567141 0.000528695 0.0376235 0.035098 -1 -1 -1 -1 32 1762 17 6.65987e+06 240882 554710. 1919.41 0.48 0.101169 0.0902369 22834 132086 -1 1641 35 572 572 92037 50076 1.42045 1.42045 -99.1377 -1.42045 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.034255 0.0298774 97 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 2.76 vpr 62.72 MiB -1 -1 0.15 17948 1 0.04 -1 -1 30296 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64224 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.6 MiB 0.05 1644 32449 9393 19839 3217 62.7 MiB 0.19 0.00 3.38291 -180.76 -3.38291 3.38291 0.32 0.000880433 0.000823692 0.0609751 0.0571335 -1 -1 -1 -1 32 2858 35 6.65987e+06 367662 554710. 1919.41 0.66 0.183589 0.165605 22834 132086 -1 2422 21 853 853 74293 19928 1.63645 1.63645 -152.543 -1.63645 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0343826 0.0306978 145 2 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.04 vpr 63.06 MiB -1 -1 0.22 18240 1 0.04 -1 -1 30524 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.1 MiB 0.07 2278 49637 16106 29325 4206 63.1 MiB 0.32 0.01 4.25753 -269.84 -4.25753 4.25753 0.32 0.00119888 0.00112752 0.0868525 0.0816403 -1 -1 -1 -1 32 3524 24 6.65987e+06 494442 554710. 1919.41 0.71 0.239232 0.218193 22834 132086 -1 3207 15 1082 1082 88606 22556 1.61205 1.61205 -194.499 -1.61205 0 0 701300. 2426.64 0.03 0.09 0.13 -1 -1 0.03 0.0362035 0.0327639 193 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 1.77 vpr 62.61 MiB -1 -1 0.15 17432 1 0.02 -1 -1 30000 -1 -1 1 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64112 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 23.9 MiB 0.02 49 141 51 88 2 62.6 MiB 0.00 0.00 0.723895 -9.92304 -0.723895 0.723895 0.26 8.8052e-05 7.9849e-05 0.000999121 0.000908116 -1 -1 -1 -1 20 98 10 6.95648e+06 14475.7 414966. 1435.87 0.30 0.0111389 0.00932378 23170 95770 -1 97 7 39 39 2258 798 0.74674 0.74674 -9.97418 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00275107 0.00248696 7 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 1.90 vpr 62.60 MiB -1 -1 0.14 17416 1 0.02 -1 -1 29904 -1 -1 1 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 24.1 MiB 0.05 62 455 89 352 14 62.6 MiB 0.01 0.00 0.723895 -12.1764 -0.723895 0.723895 0.34 0.000105243 9.602e-05 0.00245462 0.00224036 -1 -1 -1 -1 20 159 11 6.95648e+06 14475.7 414966. 1435.87 0.28 0.006791 0.00608146 23170 95770 -1 135 8 71 71 4591 1516 0.74674 0.74674 -13.0356 -0.74674 0 0 503264. 1741.40 0.02 0.01 0.10 -1 -1 0.02 0.00316305 0.00283131 8 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 1.98 vpr 62.57 MiB -1 -1 0.14 17264 1 0.02 -1 -1 29984 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64076 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 24.1 MiB 0.05 78 532 113 404 15 62.6 MiB 0.01 0.00 0.802432 -14.5369 -0.802432 0.802432 0.35 0.00012283 0.00011251 0.00266091 0.00244373 -1 -1 -1 -1 22 226 14 6.95648e+06 28951.4 443629. 1535.05 0.33 0.0192559 0.0165149 23458 102101 -1 200 12 93 93 4853 1733 1.04203 1.04203 -16.6837 -1.04203 0 0 531479. 1839.03 0.02 0.01 0.10 -1 -1 0.02 0.00425953 0.003729 10 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 1.92 vpr 62.76 MiB -1 -1 0.09 17224 1 0.03 -1 -1 30004 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.3 MiB 0.03 198 745 185 473 87 62.8 MiB 0.01 0.00 0.852632 -19.2076 -0.852632 0.852632 0.34 0.000140716 0.00012916 0.00337215 0.00309938 -1 -1 -1 -1 26 321 13 6.95648e+06 28951.4 503264. 1741.40 0.36 0.0195341 0.0165326 24322 120374 -1 321 11 126 126 8370 2235 1.09223 1.09223 -20.8791 -1.09223 0 0 618332. 2139.56 0.04 0.01 0.12 -1 -1 0.04 0.00464353 0.00415812 11 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.92 MiB -1 -1 0.15 17404 1 0.02 -1 -1 30132 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 24.4 MiB 0.03 223 1078 298 659 121 62.9 MiB 0.01 0.00 0.852632 -21.5769 -0.852632 0.852632 0.33 0.000157576 0.000145183 0.00461473 0.00425641 -1 -1 -1 -1 30 354 9 6.95648e+06 28951.4 556674. 1926.21 0.39 0.0212789 0.0180897 25186 138497 -1 308 12 127 127 6401 1953 0.959892 0.959892 -22.0373 -0.959892 0 0 706193. 2443.58 0.03 0.01 0.11 -1 -1 0.03 0.00509797 0.00446228 13 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 2.35 vpr 62.62 MiB -1 -1 0.16 17360 1 0.02 -1 -1 30072 -1 -1 4 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 24.1 MiB 0.02 137 2113 694 1199 220 62.6 MiB 0.02 0.00 0.852632 -22.0391 -0.852632 0.852632 0.33 0.000175963 0.000162527 0.0077691 0.00716049 -1 -1 -1 -1 34 351 30 6.95648e+06 57902.7 618332. 2139.56 0.63 0.045466 0.0380876 25762 151098 -1 282 21 287 287 12600 4481 1.08603 1.08603 -23.81 -1.08603 0 0 787024. 2723.27 0.05 0.03 0.14 -1 -1 0.05 0.00901771 0.00775726 15 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 2.12 vpr 62.77 MiB -1 -1 0.16 17304 1 0.03 -1 -1 30060 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 21 11 76 77 1 49 36 17 17 289 -1 unnamed_device 24.3 MiB 0.02 347 1157 244 770 143 62.8 MiB 0.01 0.00 0.896632 -29.3782 -0.896632 0.896632 0.34 0.000195865 0.000181237 0.00446093 0.00413933 -1 -1 -1 -1 32 570 14 6.95648e+06 57902.7 586450. 2029.24 0.45 0.0343905 0.0288988 25474 144626 -1 537 14 225 225 20970 4717 0.993732 0.993732 -31.9978 -0.993732 0 0 744469. 2576.02 0.03 0.02 0.10 -1 -1 0.03 0.00662926 0.0057376 17 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 2.48 vpr 62.92 MiB -1 -1 0.16 17280 1 0.02 -1 -1 30048 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64432 23 12 83 84 1 55 39 17 17 289 -1 unnamed_device 24.3 MiB 0.02 176 2481 826 1259 396 62.9 MiB 0.02 0.00 0.896632 -27.0337 -0.896632 0.896632 0.34 0.000210709 0.000195162 0.00860788 0.00797035 -1 -1 -1 -1 34 483 24 6.95648e+06 57902.7 618332. 2139.56 0.67 0.0520092 0.0437792 25762 151098 -1 363 22 394 394 26948 8701 1.04203 1.04203 -28.5778 -1.04203 0 0 787024. 2723.27 0.04 0.03 0.16 -1 -1 0.04 0.00958538 0.00817473 18 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 2.16 vpr 62.77 MiB -1 -1 0.15 17464 1 0.02 -1 -1 30040 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.1 MiB 0.02 224 1468 277 1132 59 62.8 MiB 0.02 0.00 0.918632 -30.5074 -0.918632 0.918632 0.34 0.000235964 0.000218668 0.00528816 0.00487691 -1 -1 -1 -1 28 585 18 6.95648e+06 72378.4 531479. 1839.03 0.42 0.0314017 0.026693 24610 126494 -1 522 14 291 291 16745 5276 1.13003 1.13003 -35.7088 -1.13003 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00737591 0.00639021 20 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 2.17 vpr 62.77 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30064 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 24.1 MiB 0.03 339 2916 911 1507 498 62.8 MiB 0.02 0.00 0.951632 -33.9905 -0.951632 0.951632 0.33 0.000237851 0.000219672 0.0093005 0.00860411 -1 -1 -1 -1 30 672 15 6.95648e+06 72378.4 556674. 1926.21 0.43 0.0359111 0.0309348 25186 138497 -1 538 13 312 312 21190 5519 1.20223 1.20223 -37.9867 -1.20223 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.0076564 0.00668502 21 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 2.25 vpr 62.77 MiB -1 -1 0.16 17140 1 0.02 -1 -1 29948 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 29 15 104 105 1 72 49 17 17 289 -1 unnamed_device 24.1 MiB 0.03 501 2808 751 1668 389 62.8 MiB 0.02 0.00 0.951632 -40.8249 -0.951632 0.951632 0.34 0.000242718 0.000218442 0.00856423 0.00788443 -1 -1 -1 -1 28 933 14 6.95648e+06 72378.4 531479. 1839.03 0.51 0.0366332 0.0315532 24610 126494 -1 839 20 482 482 52768 11792 1.09223 1.09223 -45.6629 -1.09223 0 0 648988. 2245.63 0.03 0.03 0.14 -1 -1 0.03 0.0104657 0.00901245 23 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 2.48 vpr 62.93 MiB -1 -1 0.17 17680 1 0.02 -1 -1 30380 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.2 MiB 0.04 310 4417 1777 2577 63 62.9 MiB 0.03 0.00 1.33396 -40.1371 -1.33396 1.33396 0.33 0.000271468 0.000251395 0.013265 0.0122886 -1 -1 -1 -1 36 703 18 6.95648e+06 72378.4 648988. 2245.63 0.68 0.065333 0.0558986 26050 158493 -1 570 15 424 424 34284 9332 1.09503 1.09503 -39.6024 -1.09503 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64376 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 24.1 MiB 0.07 367 6541 2699 3775 67 62.9 MiB 0.05 0.00 1.36696 -49.1573 -1.36696 1.36696 0.33 0.000329616 0.000306498 0.0189951 0.0176578 -1 -1 -1 -1 32 856 19 6.95648e+06 72378.4 586450. 2029.24 0.49 0.0571506 0.0498642 25474 144626 -1 628 18 477 477 33113 8842 1.22703 1.22703 -50.8059 -1.22703 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0122266 0.0105782 28 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 2.39 vpr 63.03 MiB -1 -1 0.17 17652 1 0.02 -1 -1 30388 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64544 41 21 146 147 1 95 67 17 17 289 -1 unnamed_device 24.0 MiB 0.07 409 6867 2815 3994 58 63.0 MiB 0.05 0.00 1.38896 -56.2399 -1.38896 1.38896 0.33 0.00036088 0.000335508 0.0193484 0.0179993 -1 -1 -1 -1 30 1163 35 6.95648e+06 72378.4 556674. 1926.21 0.60 0.0698336 0.0607412 25186 138497 -1 785 16 563 563 51275 13421 1.44463 1.44463 -60.8139 -1.44463 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0123152 0.0107333 31 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 3.70 vpr 63.18 MiB -1 -1 0.17 17588 1 0.03 -1 -1 30316 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 45 23 160 161 1 108 74 17 17 289 -1 unnamed_device 24.0 MiB 0.08 466 7514 3111 4336 67 63.2 MiB 0.05 0.00 1.41096 -62.5444 -1.41096 1.41096 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 24.0 MiB 0.08 866 16299 6958 9195 146 63.5 MiB 0.10 0.00 1.88129 -97.7109 -1.88129 1.88129 0.34 0.000573807 0.000535131 0.0384883 0.0358947 -1 -1 -1 -1 42 1631 39 6.95648e+06 130281 744469. 2576.02 1.15 0.166265 0.146237 27202 183097 -1 1355 16 747 747 71025 18381 1.44933 1.44933 -95.5906 -1.44933 0 0 949917. 3286.91 0.04 0.05 0.15 -1 -1 0.04 0.0188154 0.0166379 50 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 3.38 vpr 64.11 MiB -1 -1 0.18 17836 1 0.03 -1 -1 30336 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65644 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.3 MiB 0.11 1814 29672 12289 17319 64 64.1 MiB 0.18 0.00 2.41762 -170.667 -2.41762 2.41762 0.33 0.000869886 0.000815239 0.0621123 0.058191 -1 -1 -1 -1 48 2741 23 6.95648e+06 202660 865456. 2994.66 1.22 0.238027 0.213864 28354 207349 -1 2562 20 1103 1103 131768 29384 1.49993 1.49993 -156.421 -1.49993 0 0 1.05005e+06 3633.38 0.04 0.09 0.17 -1 -1 0.04 0.0335475 0.0300032 74 2 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 4.45 vpr 64.69 MiB -1 -1 0.17 18212 1 0.04 -1 -1 30612 -1 -1 19 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66244 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 24.9 MiB 0.13 2229 45933 16115 26949 2869 64.7 MiB 0.29 0.01 2.95395 -241.167 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2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64012 13 7 48 49 1 26 22 17 17 289 -1 unnamed_device 24.0 MiB 0.01 88 442 89 343 10 62.5 MiB 0.02 0.00 0.802432 -14.6238 -0.802432 0.802432 0.33 0.000416283 0.000382138 0.00349914 0.00321787 -1 -1 -1 -1 22 196 8 6.99608e+06 29431.4 443629. 1535.05 0.33 0.0164598 0.0139839 23458 102101 -1 190 12 106 106 6171 2132 0.793379 0.793379 -15.9608 -0.793379 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00429213 0.00376112 10 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 1.96 vpr 62.73 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30052 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.3 MiB 0.01 96 709 205 450 54 62.7 MiB 0.01 0.00 0.859432 -17.7199 -0.859432 0.859432 0.34 0.000140372 0.000128807 0.00323931 0.00297881 -1 -1 -1 -1 26 228 25 6.99608e+06 29431.4 503264. 1741.40 0.37 0.0216731 0.0182166 24322 120374 -1 198 12 131 131 4752 1834 0.927732 0.927732 -17.9149 -0.927732 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00468069 0.0040988 11 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.63 MiB -1 -1 0.15 17184 1 0.02 -1 -1 30084 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64132 17 9 62 63 1 38 28 17 17 289 -1 unnamed_device 24.1 MiB 0.02 260 952 218 609 125 62.6 MiB 0.01 0.00 0.824432 -22.1673 -0.824432 0.824432 0.34 0.000156946 0.000144715 0.00406462 0.00375358 -1 -1 -1 -1 32 430 9 6.99608e+06 29431.4 586450. 2029.24 0.41 0.020757 0.0176249 25474 144626 -1 421 9 116 116 11800 2672 0.87204 0.87204 -23.6355 -0.87204 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00440788 0.00390181 13 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 2.12 vpr 62.43 MiB -1 -1 0.16 17352 1 0.02 -1 -1 30028 -1 -1 4 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63932 19 10 69 70 1 43 33 17 17 289 -1 unnamed_device 23.9 MiB 0.02 137 2477 763 1101 613 62.4 MiB 0.02 0.00 0.846432 -21.9393 -0.846432 0.846432 0.38 0.000171382 0.000154709 0.00923131 0.00850779 -1 -1 -1 -1 28 370 18 6.99608e+06 58862.7 531479. 1839.03 0.39 0.0301008 0.0257969 24610 126494 -1 287 13 210 210 11679 4198 1.18933 1.18933 -23.5118 -1.18933 0 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-1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64144 23 12 83 84 1 54 39 17 17 289 -1 unnamed_device 24.1 MiB 0.02 174 2481 746 1270 465 62.6 MiB 0.02 0.00 0.879432 -26.6557 -0.879432 0.879432 0.33 0.00021024 0.000194311 0.00857848 0.00793516 -1 -1 -1 -1 32 441 18 6.99608e+06 58862.7 586450. 2029.24 0.46 0.0332947 0.0284674 25474 144626 -1 372 12 266 266 17399 5603 0.993732 0.993732 -28.012 -0.993732 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00635172 0.00551661 18 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 2.13 vpr 62.57 MiB -1 -1 0.16 17196 1 0.02 -1 -1 30032 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 23.9 MiB 0.03 255 1618 324 1252 42 62.6 MiB 0.02 0.00 0.890432 -31.1278 -0.890432 0.890432 0.34 0.000224588 0.000208394 0.00581343 0.00537445 -1 -1 -1 -1 30 526 13 6.99608e+06 73578.4 556674. 1926.21 0.42 0.0313334 0.0268842 25186 138497 -1 496 10 236 236 16715 4353 0.99734 0.99734 -33.2379 -0.99734 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00608414 0.00533822 20 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 2.17 vpr 62.79 MiB -1 -1 0.16 17396 1 0.02 -1 -1 29940 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 27 14 97 98 1 66 46 17 17 289 -1 unnamed_device 24.2 MiB 0.02 266 2916 905 1615 396 62.8 MiB 0.02 0.00 0.912432 -33.5679 -0.912432 0.912432 0.34 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0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0099582 0.00858435 23 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_015bits.v common 2.27 vpr 62.73 MiB -1 -1 0.14 17584 1 0.02 -1 -1 30304 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64232 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.0 MiB 0.03 331 4514 1860 2555 99 62.7 MiB 0.03 0.00 1.29476 -39.8517 -1.29476 1.29476 0.33 0.000271418 0.000251586 0.0135538 0.0125405 -1 -1 -1 -1 30 845 48 6.99608e+06 73578.4 556674. 1926.21 0.52 0.0569387 0.0488876 25186 138497 -1 616 19 462 462 34517 8954 1.11703 1.11703 -42.4939 -1.11703 0 0 706193. 2443.58 0.03 0.03 0.12 -1 -1 0.03 0.0108951 0.00939784 24 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 2.18 vpr 62.88 MiB -1 -1 0.09 17568 1 0.02 -1 -1 30068 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64384 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 24.1 MiB 0.03 328 4735 1886 2806 43 62.9 MiB 0.04 0.00 1.31676 -42.6858 -1.31676 1.31676 0.33 0.000291739 0.000270454 0.0141016 0.0130776 -1 -1 -1 -1 30 805 33 6.99608e+06 73578.4 556674. 1926.21 0.49 0.053817 0.046524 25186 138497 -1 641 16 399 399 31520 8272 1.15003 1.15003 -44.2826 -1.15003 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0101561 0.00881561 25 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_018bits.v common 2.07 vpr 62.99 MiB -1 -1 0.13 17664 1 0.03 -1 -1 30056 -1 -1 5 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 24.3 MiB 0.03 364 6541 2695 3784 62 63.0 MiB 0.02 0.00 1.33876 -49.2921 -1.33876 1.33876 0.26 0.000154524 0.000136787 0.00893174 0.00815638 -1 -1 -1 -1 32 939 42 6.99608e+06 73578.4 586450. 2029.24 0.51 0.05855 0.049823 25474 144626 -1 693 12 368 368 26349 7167 1.17203 1.17203 -49.9105 -1.17203 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.00929189 0.00813969 28 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 2.35 vpr 62.70 MiB -1 -1 0.16 17492 1 0.02 -1 -1 30308 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64208 41 21 146 147 1 94 67 17 17 289 -1 unnamed_device 23.7 MiB 0.03 407 6867 2751 4056 60 62.7 MiB 0.05 0.00 1.34976 -54.4321 -1.34976 1.34976 0.33 0.000360265 0.000334878 0.0193038 0.0179451 -1 -1 -1 -1 32 961 35 6.99608e+06 73578.4 586450. 2029.24 0.57 0.0697677 0.0606438 25474 144626 -1 756 15 428 428 30944 8363 1.24903 1.24903 -58.4693 -1.24903 0 0 744469. 2576.02 0.04 0.03 0.12 -1 -1 0.04 0.0117671 0.0102516 31 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 2.27 vpr 62.82 MiB -1 -1 0.16 17528 1 0.03 -1 -1 30348 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64332 45 23 160 161 1 107 74 17 17 289 -1 unnamed_device 23.7 MiB 0.04 530 7514 3084 4380 50 62.8 MiB 0.05 0.00 1.37176 -61.8029 -1.37176 1.37176 0.33 0.000390883 0.000363367 0.0200903 0.0186905 -1 -1 -1 -1 30 1126 15 6.99608e+06 88294.1 556674. 1926.21 0.48 0.0628619 0.0552343 25186 138497 -1 855 18 558 558 40666 10320 1.16968 1.16968 -63.7857 -1.16968 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.014469 0.0126338 34 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 2.94 vpr 63.00 MiB -1 -1 0.14 17580 1 0.02 -1 -1 30244 -1 -1 8 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64512 49 25 174 175 1 118 82 17 17 289 -1 unnamed_device 23.8 MiB 0.04 521 10228 4171 5954 103 63.0 MiB 0.07 0.00 1.39376 -67.8066 -1.39376 1.39376 0.33 0.000422838 0.000393319 0.0255703 0.0237972 -1 -1 -1 -1 34 1390 34 6.99608e+06 117725 618332. 2139.56 1.09 0.117769 0.102435 25762 151098 -1 986 29 736 736 98243 38158 1.36333 1.36333 -70.765 -1.36333 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0224734 0.0194537 38 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 3.07 vpr 63.10 MiB -1 -1 0.16 17624 1 0.03 -1 -1 30008 -1 -1 9 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 57 29 202 203 1 141 95 17 17 289 -1 unnamed_device 23.7 MiB 0.05 724 11543 4737 6716 90 63.1 MiB 0.07 0.00 1.44876 -82.7694 -1.44876 1.44876 0.34 0.000487581 0.000453293 0.0278211 0.0258836 -1 -1 -1 -1 38 1462 37 6.99608e+06 132441 678818. 2348.85 1.07 0.136751 0.119606 26626 170182 -1 1129 17 624 624 44907 12336 1.24188 1.24188 -80.687 -1.24188 0 0 902133. 3121.57 0.03 0.04 0.14 -1 -1 0.03 0.0169488 0.0148993 44 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 3.01 vpr 63.09 MiB -1 -1 0.10 17544 1 0.03 -1 -1 30048 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 23.7 MiB 0.05 873 16299 6945 9215 139 63.1 MiB 0.10 0.00 1.85309 -97.7499 -1.85309 1.85309 0.34 0.000588436 0.000549662 0.0383991 0.0358314 -1 -1 -1 -1 40 1590 25 6.99608e+06 132441 706193. 2443.58 1.10 0.154029 0.135738 26914 176310 -1 1430 16 781 781 64746 16342 1.32403 1.32403 -95.1334 -1.32403 0 0 926341. 3205.33 0.04 0.05 0.14 -1 -1 0.04 0.0186641 0.0164658 50 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 3.65 vpr 63.71 MiB -1 -1 0.17 17844 1 0.03 -1 -1 30352 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65236 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.0 MiB 0.08 1811 29672 12269 17337 66 63.7 MiB 0.18 0.00 2.38942 -170.114 -2.38942 2.38942 0.33 0.000881923 0.00082713 0.0624841 0.0585536 -1 -1 -1 -1 44 2886 50 6.99608e+06 206020 787024. 2723.27 1.45 0.277812 0.249067 27778 195446 -1 2550 19 1048 1048 107084 28330 1.70033 1.70033 -166.464 -1.70033 0 0 997811. 3452.63 0.04 0.08 0.16 -1 -1 0.04 0.032219 0.0288443 74 2 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_064bits.v common 4.33 vpr 64.00 MiB -1 -1 0.22 18124 1 0.04 -1 -1 30668 -1 -1 19 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65536 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 24.8 MiB 0.09 2249 45933 16327 26970 2636 64.0 MiB 0.27 0.01 2.92575 -237.867 -2.92575 2.92575 0.33 0.00120023 0.00112835 0.0902407 0.0848321 -1 -1 -1 -1 48 3564 45 6.99608e+06 279598 865456. 2994.66 1.93 0.385981 0.349472 28354 207349 -1 3147 13 1131 1131 98551 21708 1.67588 1.67588 -208.648 -1.67588 0 0 1.05005e+06 3633.38 0.04 0.09 0.17 -1 -1 0.04 0.0333912 0.0303126 98 2 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_004bits.v common 1.87 vpr 61.76 MiB -1 -1 0.13 17292 2 0.06 -1 -1 31964 -1 -1 1 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63244 9 5 28 33 1 16 15 17 17 289 -1 unnamed_device 23.0 MiB 0.01 54 141 47 92 2 61.8 MiB 0.00 0.00 0.883748 -10.0813 -0.883748 0.883748 0.33 8.5414e-05 7.7314e-05 0.000966256 0.000875122 -1 -1 -1 -1 20 116 6 6.79088e+06 13472 414966. 1435.87 0.29 0.0100954 0.00839297 22510 95286 -1 96 7 35 35 1420 501 0.883748 0.883748 -9.8435 -0.883748 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00269658 0.00243975 8 6 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_005bits.v common 1.90 vpr 61.89 MiB -1 -1 0.14 17340 2 0.07 -1 -1 31884 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63376 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 23.2 MiB 0.01 78 394 86 293 15 61.9 MiB 0.01 0.00 1.02368 -13.4328 -1.02368 1.02368 0.36 0.000106267 9.6689e-05 0.00206803 0.0018958 -1 -1 -1 -1 22 194 10 6.79088e+06 26944 443629. 1535.05 0.32 0.0137002 0.0115006 22798 101617 -1 190 9 83 96 4150 1453 1.02368 1.02368 -14.6764 -1.02368 0 0 531479. 1839.03 0.03 0.01 0.09 -1 -1 0.03 0.00336983 0.00298904 10 7 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_006bits.v common 1.81 vpr 61.99 MiB -1 -1 0.15 17184 3 0.06 -1 -1 31848 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 23.3 MiB 0.01 103 562 132 416 14 62.0 MiB 0.01 0.00 1.14898 -15.8855 -1.14898 1.14898 0.33 5.793e-05 5.1492e-05 0.00140278 0.00125839 -1 -1 -1 -1 22 254 12 6.79088e+06 26944 443629. 1535.05 0.33 0.0182156 0.0151027 22798 101617 -1 234 12 97 105 6113 2065 1.14898 1.14898 -17.5434 -1.14898 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00432033 0.00378435 11 9 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_007bits.v common 2.04 vpr 62.02 MiB -1 -1 0.15 17292 3 0.05 -1 -1 31872 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63512 15 8 47 55 1 35 25 17 17 289 -1 unnamed_device 23.6 MiB 0.04 109 1285 395 736 154 62.0 MiB 0.01 0.00 1.27433 -19.2894 -1.27433 1.27433 0.34 0.000142197 0.0001303 0.00559248 0.00513681 -1 -1 -1 -1 26 347 17 6.79088e+06 26944 503264. 1741.40 0.37 0.0227498 0.0192919 23662 119890 -1 248 14 147 157 5953 2292 1.27433 1.27433 -20.5245 -1.27433 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00522063 0.00452381 13 10 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_008bits.v common 2.16 vpr 61.95 MiB -1 -1 0.16 17260 3 0.06 -1 -1 31924 -1 -1 4 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63432 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 23.5 MiB 0.06 297 1272 281 862 129 61.9 MiB 0.02 0.00 1.56413 -26.212 -1.56413 1.56413 0.34 0.000175567 0.00016209 0.00553938 0.00510909 -1 -1 -1 -1 26 505 11 6.79088e+06 53888 503264. 1741.40 0.36 0.0254124 0.0215936 23662 119890 -1 454 9 113 140 9091 2260 1.31353 1.31353 -26.0895 -1.31353 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00473594 0.00420527 17 14 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_009bits.v common 2.16 vpr 61.99 MiB -1 -1 0.15 17304 4 0.06 -1 -1 31992 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 19 10 60 70 1 46 32 17 17 289 -1 unnamed_device 23.5 MiB 0.07 157 2582 733 1373 476 62.0 MiB 0.02 0.00 1.65028 -26.9205 -1.65028 1.65028 0.34 0.000185515 0.000170984 0.0102122 0.00942314 -1 -1 -1 -1 28 440 24 6.79088e+06 40416 531479. 1839.03 0.40 0.0336774 0.0287458 23950 126010 -1 341 14 189 208 10515 3869 1.68943 1.68943 -27.6328 -1.68943 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00634766 0.00548015 17 13 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_010bits.v common 2.09 vpr 62.10 MiB -1 -1 0.16 17224 4 0.06 -1 -1 31688 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63592 21 11 69 80 1 54 36 17 17 289 -1 unnamed_device 23.6 MiB 0.06 276 1275 269 996 10 62.1 MiB 0.01 0.00 1.56413 -30.7636 -1.56413 1.56413 0.33 0.000211308 0.000195146 0.00522765 0.00483659 -1 -1 -1 -1 22 697 22 6.79088e+06 53888 443629. 1535.05 0.40 0.0360258 0.0302982 22798 101617 -1 574 14 232 281 20802 5741 1.51379 1.51379 -32.6549 -1.51379 0 0 531479. 1839.03 0.02 0.02 0.09 -1 -1 0.02 0.00716795 0.00620991 21 17 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_011bits.v common 1.98 vpr 62.01 MiB -1 -1 0.17 17236 5 0.06 -1 -1 31940 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63496 23 12 76 88 1 60 39 17 17 289 -1 unnamed_device 23.5 MiB 0.06 263 1359 262 1083 14 62.0 MiB 0.02 0.00 1.90432 -34.8738 -1.90432 1.90432 0.33 0.000227626 0.0002106 0.00540807 0.00501505 -1 -1 -1 -1 26 598 16 6.79088e+06 53888 503264. 1741.40 0.38 0.0309708 0.026345 23662 119890 -1 529 13 222 264 13917 4200 1.85054 1.85054 -36.679 -1.85054 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00719778 0.00628971 23 19 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_012bits.v common 2.14 vpr 62.08 MiB -1 -1 0.16 17296 5 0.06 -1 -1 32124 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63568 25 13 83 96 1 65 42 17 17 289 -1 unnamed_device 23.5 MiB 0.10 302 2634 595 2020 19 62.1 MiB 0.02 0.00 1.85398 -39.4801 -1.85398 1.85398 0.33 0.000241404 0.000222109 0.00947024 0.00873055 -1 -1 -1 -1 26 756 25 6.79088e+06 53888 503264. 1741.40 0.42 0.0400931 0.0343115 23662 119890 -1 611 16 260 323 16466 4828 1.76444 1.76444 -40.3833 -1.76444 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00875305 0.00755852 24 21 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_013bits.v common 2.20 vpr 62.27 MiB -1 -1 0.16 17516 5 0.06 -1 -1 31696 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63764 27 14 91 105 1 70 46 17 17 289 -1 unnamed_device 23.7 MiB 0.08 305 1686 354 1296 36 62.3 MiB 0.02 0.00 2.15497 -44.1132 -2.15497 2.15497 0.33 0.00032784 0.000303874 0.00737664 0.00683614 -1 -1 -1 -1 30 642 13 6.79088e+06 67360 556674. 1926.21 0.41 0.0366048 0.0314193 24526 138013 -1 572 14 257 360 19230 5544 1.89323 1.89323 -42.6809 -1.89323 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0153646 0.0131766 28 24 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_014bits.v common 2.32 vpr 62.30 MiB -1 -1 0.17 17720 6 0.06 -1 -1 32036 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63792 29 15 95 110 1 77 49 17 17 289 -1 unnamed_device 23.7 MiB 0.07 324 3342 734 2532 76 62.3 MiB 0.03 0.00 2.42352 -48.7848 -2.42352 2.42352 0.34 0.000283292 0.000262432 0.0115124 0.0106785 -1 -1 -1 -1 26 904 32 6.79088e+06 67360 503264. 1741.40 0.48 0.0553618 0.0473417 23662 119890 -1 757 13 322 384 23522 6789 2.15502 2.15502 -49.648 -2.15502 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00885209 0.00771765 29 23 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_015bits.v common 2.30 vpr 62.27 MiB -1 -1 0.17 17660 6 0.06 -1 -1 32064 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63764 31 16 104 120 1 81 52 17 17 289 -1 unnamed_device 23.5 MiB 0.08 317 3641 1047 1889 705 62.3 MiB 0.03 0.00 2.28032 -49.0709 -2.28032 2.28032 0.33 0.000311764 0.00028965 0.0128153 0.0118974 -1 -1 -1 -1 26 896 44 6.79088e+06 67360 503264. 1741.40 0.47 0.0611187 0.0522955 23662 119890 -1 675 11 298 344 27538 10777 2.15502 2.15502 -50.3725 -2.15502 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00864617 0.00757546 31 27 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_016bits.v common 2.48 vpr 62.32 MiB -1 -1 0.18 17592 7 0.06 -1 -1 32008 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63820 33 17 112 129 1 84 56 17 17 289 -1 unnamed_device 23.6 MiB 0.08 457 2945 706 2143 96 62.3 MiB 0.03 0.00 2.65628 -60.2407 -2.65628 2.65628 0.33 0.000333352 0.000308992 0.0102584 0.00951554 -1 -1 -1 -1 26 985 18 6.79088e+06 80832 503264. 1741.40 0.46 0.0482989 0.0416039 23662 119890 -1 884 27 360 465 59842 33846 2.35534 2.35534 -59.3742 -2.35534 0 0 618332. 2139.56 0.03 0.05 0.10 -1 -1 0.03 0.0169438 0.0145148 33 30 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_018bits.v common 2.73 vpr 62.16 MiB -1 -1 0.17 17536 7 0.06 -1 -1 31940 -1 -1 8 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63652 37 19 127 146 1 96 64 17 17 289 -1 unnamed_device 23.3 MiB 0.17 372 3620 797 2457 366 62.2 MiB 0.03 0.00 2.98184 -67.3807 -2.98184 2.98184 0.33 0.000368639 0.000342637 0.0117319 0.0108909 -1 -1 -1 -1 30 826 19 6.79088e+06 107776 556674. 1926.21 0.44 0.0543666 0.0470508 24526 138013 -1 708 9 322 399 17487 5742 2.85654 2.85654 -65.312 -2.85654 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00897272 0.00794271 39 35 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_020bits.v common 2.51 vpr 62.41 MiB -1 -1 0.18 17712 8 0.09 -1 -1 31984 -1 -1 9 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63912 41 21 139 160 1 106 71 17 17 289 -1 unnamed_device 23.3 MiB 0.12 468 7517 1635 5720 162 62.4 MiB 0.05 0.00 2.82083 -73.4935 -2.82083 2.82083 0.33 0.000396816 0.000367611 0.0218575 0.0202429 -1 -1 -1 -1 28 1210 23 6.79088e+06 121248 531479. 1839.03 0.51 0.0709664 0.0619985 23950 126010 -1 993 14 403 544 32469 9290 2.64519 2.64519 -75.7719 -2.64519 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0126456 0.0111096 41 37 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_022bits.v common 2.55 vpr 62.49 MiB -1 -1 0.18 17636 9 0.07 -1 -1 31924 -1 -1 9 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 45 23 153 176 1 119 77 17 17 289 -1 unnamed_device 23.3 MiB 0.15 477 7086 2063 3975 1048 62.5 MiB 0.05 0.00 3.57268 -91.263 -3.57268 3.57268 0.36 0.000445506 0.0004138 0.0204716 0.0190194 -1 -1 -1 -1 32 1120 12 6.79088e+06 121248 586450. 2029.24 0.47 0.0666694 0.0586499 24814 144142 -1 908 9 364 474 24629 7210 3.27175 3.27175 -87.1614 -3.27175 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0105039 0.00938562 45 41 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_024bits.v common 2.58 vpr 62.59 MiB -1 -1 0.17 17684 10 0.08 -1 -1 31972 -1 -1 10 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64088 49 25 166 191 1 129 84 17 17 289 -1 unnamed_device 23.3 MiB 0.19 888 10149 2418 6579 1152 62.6 MiB 0.06 0.00 3.52584 -103.921 -3.52584 3.52584 0.33 0.000474217 0.000440445 0.028013 0.0260292 -1 -1 -1 -1 26 1697 15 6.79088e+06 134720 503264. 1741.40 0.43 0.0796154 0.0704286 23662 119890 -1 1585 14 501 640 47109 11368 3.40054 3.40054 -105.083 -3.40054 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.014678 0.0129495 49 44 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_028bits.v common 2.81 vpr 62.74 MiB -1 -1 0.20 17628 11 0.08 -1 -1 32024 -1 -1 12 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64244 57 29 198 227 1 154 98 17 17 289 -1 unnamed_device 23.3 MiB 0.23 831 11348 3274 6773 1301 62.7 MiB 0.07 0.00 4.16358 -130.313 -4.16358 4.16358 0.33 0.000571622 0.000532297 0.0308967 0.0287436 -1 -1 -1 -1 26 1812 27 6.79088e+06 161664 503264. 1741.40 0.54 0.104091 0.0917454 23662 119890 -1 1543 14 611 793 48973 13212 3.94874 3.94874 -129.41 -3.94874 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.0176699 0.0155753 57 56 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_032bits.v common 2.86 vpr 62.93 MiB -1 -1 0.20 17752 13 0.07 -1 -1 32144 -1 -1 11 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64436 65 33 224 257 1 172 109 17 17 289 -1 unnamed_device 23.4 MiB 0.21 818 8689 1747 6820 122 62.9 MiB 0.06 0.00 4.75448 -151.053 -4.75448 4.75448 0.33 0.000651059 0.000607364 0.0238685 0.0222369 -1 -1 -1 -1 30 1902 27 6.79088e+06 148192 556674. 1926.21 0.57 0.106315 0.0936834 24526 138013 -1 1542 15 621 853 49087 13080 4.45354 4.45354 -150.197 -4.45354 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0208553 0.018485 67 62 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_048bits.v common 3.47 vpr 63.47 MiB -1 -1 0.26 18060 19 0.10 -1 -1 32316 -1 -1 20 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64996 97 49 340 389 1 268 166 17 17 289 -1 unnamed_device 23.8 MiB 0.35 1595 32542 9530 19534 3478 63.5 MiB 0.17 0.00 6.87725 -295.573 -6.87725 6.87725 0.33 0.000987348 0.000922056 0.0729955 0.0681292 -1 -1 -1 -1 32 3045 22 6.79088e+06 269440 586450. 2029.24 0.63 0.194659 0.175474 24814 144142 -1 2743 18 968 1302 86378 21246 6.58745 6.58745 -293.066 -6.58745 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0363793 0.0325585 103 98 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_064bits.v common 4.24 vpr 64.23 MiB -1 -1 0.16 18356 26 0.11 -1 -1 32464 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65776 129 65 453 518 1 344 218 17 17 289 -1 unnamed_device 24.5 MiB 0.57 1971 49998 15091 29566 5341 64.2 MiB 0.25 0.00 10.4784 -507.086 -10.4784 10.4784 0.33 0.00132893 0.00124528 0.106245 0.0993901 -1 -1 -1 -1 40 3524 26 6.79088e+06 323328 706193. 2443.58 1.34 0.392274 0.354177 26254 175826 -1 3188 13 1107 1495 97622 26410 9.85193 9.85193 -491.088 -9.85193 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0540559 0.0490496 131 131 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_004bits.v common 1.82 vpr 62.44 MiB -1 -1 0.10 17380 1 0.02 -1 -1 30064 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.6 MiB 0.04 79 296 89 204 3 62.4 MiB 0.01 0.00 0.789073 -10.6008 -0.789073 0.789073 0.34 8.7674e-05 7.9525e-05 0.00159518 0.00144518 -1 -1 -1 -1 20 151 10 6.87369e+06 27947.7 414966. 1435.87 0.28 0.00519648 0.00462685 23170 95770 -1 130 9 79 79 4463 1413 0.789073 0.789073 -11.1729 -0.789073 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00359292 0.00318991 10 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 1.97 vpr 62.37 MiB -1 -1 0.08 17400 1 0.02 -1 -1 29904 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63864 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 23.6 MiB 0.04 163 695 168 481 46 62.4 MiB 0.01 0.00 0.811073 -14.7125 -0.811073 0.811073 0.40 9.2581e-05 8.1117e-05 0.00258582 0.00229127 -1 -1 -1 -1 20 310 13 6.87369e+06 41921.5 414966. 1435.87 0.31 0.00683924 0.00597313 23170 95770 -1 289 11 141 141 13137 3115 1.05067 1.05067 -17.0701 -1.05067 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00365303 0.00321754 13 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 2.34 vpr 62.30 MiB -1 -1 0.13 17340 1 0.03 -1 -1 29940 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63796 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 23.8 MiB 0.06 100 806 191 526 89 62.3 MiB 0.01 0.00 0.833073 -15.3512 -0.833073 0.833073 0.34 0.000122088 0.000111989 0.00334155 0.00306422 -1 -1 -1 -1 36 229 22 6.87369e+06 55895.4 648988. 2245.63 0.63 0.0342161 0.0282667 26050 158493 -1 180 17 218 218 8477 3065 0.958373 0.958373 -15.1722 -0.958373 0 0 828058. 2865.25 0.05 0.03 0.11 -1 -1 0.05 0.00917581 0.00770806 15 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 2.03 vpr 62.57 MiB -1 -1 0.14 17352 1 0.02 -1 -1 29992 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64072 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 24.2 MiB 0.05 134 1128 368 603 157 62.6 MiB 0.01 0.00 1.2044 -18.5156 -1.2044 1.2044 0.35 0.000154596 0.000139466 0.00453151 0.00408993 -1 -1 -1 -1 26 307 17 6.87369e+06 41921.5 503264. 1741.40 0.35 0.021363 0.0179662 24322 120374 -1 267 14 146 146 6496 2236 0.989373 0.989373 -20.3361 -0.989373 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00517942 0.0045165 16 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 1.99 vpr 62.28 MiB -1 -1 0.08 17312 1 0.02 -1 -1 29984 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63776 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.8 MiB 0.05 146 1877 632 931 314 62.3 MiB 0.02 0.00 1.2154 -21.3035 -1.2154 1.2154 0.34 0.000157735 0.000145122 0.00722208 0.00664584 -1 -1 -1 -1 26 297 13 6.87369e+06 41921.5 503264. 1741.40 0.37 0.0248125 0.0212051 24322 120374 -1 273 13 150 150 7334 2479 1.00037 1.00037 -22.2134 -1.00037 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00528613 0.0045942 19 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 2.16 vpr 62.50 MiB -1 -1 0.14 17120 1 0.02 -1 -1 30024 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63996 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 24.1 MiB 0.07 160 2332 796 1082 454 62.5 MiB 0.02 0.00 1.2264 -24.1787 -1.2264 1.2264 0.34 0.000175241 0.000161634 0.008706 0.00803815 -1 -1 -1 -1 32 327 12 6.87369e+06 41921.5 586450. 2029.24 0.41 0.0280777 0.0241535 25474 144626 -1 286 11 164 164 7398 2391 1.01137 1.01137 -24.7636 -1.01137 0 0 744469. 2576.02 0.04 0.01 0.12 -1 -1 0.04 0.00504681 0.00448936 20 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 2.07 vpr 62.51 MiB -1 -1 0.15 17260 1 0.02 -1 -1 30120 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.0 MiB 0.07 175 2101 728 1079 294 62.5 MiB 0.02 0.00 1.2374 -27.2124 -1.2374 1.2374 0.34 0.000193984 0.000179478 0.00761103 0.00704442 -1 -1 -1 -1 30 382 13 6.87369e+06 55895.4 556674. 1926.21 0.41 0.0291491 0.0249416 25186 138497 -1 293 13 196 196 9565 2925 1.01137 1.01137 -26.4753 -1.01137 0 0 706193. 2443.58 0.03 0.01 0.08 -1 -1 0.03 0.00399551 0.00355068 22 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_011bits.v common 2.24 vpr 62.55 MiB -1 -1 0.15 17412 1 0.02 -1 -1 30040 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 24.0 MiB 0.05 194 2488 794 1203 491 62.6 MiB 0.02 0.00 1.2484 -30.0694 -1.2484 1.2484 0.33 0.000210963 0.000194687 0.00835745 0.00773003 -1 -1 -1 -1 32 434 17 6.87369e+06 69869.2 586450. 2029.24 0.45 0.0313966 0.026865 25474 144626 -1 373 20 274 274 18397 5227 1.13667 1.13667 -31.3415 -1.13667 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0135594 0.0114399 24 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_012bits.v common 2.22 vpr 62.56 MiB -1 -1 0.16 17376 1 0.02 -1 -1 30204 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64060 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.0 MiB 0.06 241 3493 1152 1593 748 62.6 MiB 0.03 0.00 1.2594 -33.5756 -1.2594 1.2594 0.34 0.00022384 0.000206819 0.0111138 0.0102745 -1 -1 -1 -1 32 501 21 6.87369e+06 69869.2 586450. 2029.24 0.43 0.0379716 0.0326576 25474 144626 -1 425 8 199 199 11182 3603 0.989373 0.989373 -33.3362 -0.989373 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00518953 0.00458893 26 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 2.80 vpr 62.49 MiB -1 -1 0.15 17308 1 0.02 -1 -1 30232 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.9 MiB 0.06 240 2998 1051 1663 284 62.5 MiB 0.03 0.00 1.2773 -35.5756 -1.2773 1.2773 0.33 0.000246381 0.00022827 0.00947207 0.00876673 -1 -1 -1 -1 30 618 21 6.87369e+06 69869.2 556674. 1926.21 1.12 0.0733815 0.0616699 25186 138497 -1 480 17 350 350 21752 6218 1.04437 1.04437 -34.6874 -1.04437 0 0 706193. 2443.58 0.03 0.02 0.09 -1 -1 0.03 0.00875841 0.00753696 28 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.19 vpr 62.53 MiB -1 -1 0.16 17388 1 0.02 -1 -1 30104 -1 -1 7 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 23.9 MiB 0.07 310 4093 1402 1938 753 62.5 MiB 0.03 0.00 1.2814 -39.7439 -1.2814 1.2814 0.33 0.000252751 0.00023371 0.0117669 0.0108889 -1 -1 -1 -1 28 763 21 6.87369e+06 97816.9 531479. 1839.03 0.43 0.041926 0.0362437 24610 126494 -1 614 12 343 343 23714 6541 1.12567 1.12567 -40.5186 -1.12567 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.00730899 0.00637495 31 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 2.29 vpr 62.38 MiB -1 -1 0.15 17576 1 0.02 -1 -1 30264 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63880 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.7 MiB 0.08 337 6389 2578 2834 977 62.4 MiB 0.05 0.00 1.65963 -43.635 -1.65963 1.65963 0.34 0.000271225 0.000250996 0.0184151 0.0170486 -1 -1 -1 -1 32 726 25 6.87369e+06 83843 586450. 2029.24 0.47 0.0547587 0.0475343 25474 144626 -1 583 15 400 400 26645 7674 1.12567 1.12567 -42.064 -1.12567 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.00894667 0.007769 32 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 2.23 vpr 62.55 MiB -1 -1 0.16 17600 1 0.02 -1 -1 30052 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64056 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.9 MiB 0.08 354 5727 2338 3295 94 62.6 MiB 0.04 0.00 1.66373 -46.576 -1.66373 1.66373 0.33 0.00029115 0.000269841 0.0164547 0.0152586 -1 -1 -1 -1 30 765 19 6.87369e+06 83843 556674. 1926.21 0.43 0.0498673 0.043428 25186 138497 -1 646 22 430 430 29960 8573 1.22267 1.22267 -46.6259 -1.22267 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0125804 0.0108044 35 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 2.21 vpr 62.46 MiB -1 -1 0.15 17420 1 0.02 -1 -1 30192 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 23.7 MiB 0.08 390 6188 2490 3601 97 62.5 MiB 0.04 0.00 1.68573 -53.5906 -1.68573 1.68573 0.33 0.000329317 0.000306042 0.0173699 0.0161432 -1 -1 -1 -1 30 851 16 6.87369e+06 97816.9 556674. 1926.21 0.44 0.0537216 0.0467985 25186 138497 -1 693 11 381 381 25789 7299 1.13037 1.13037 -51.5244 -1.13037 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0086009 0.00751161 38 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 2.36 vpr 62.71 MiB -1 -1 0.15 17564 1 0.02 -1 -1 30288 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64220 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.7 MiB 0.08 447 8134 3300 4657 177 62.7 MiB 0.06 0.00 1.70773 -60.3017 -1.70773 1.70773 0.33 0.00036247 0.000336699 0.0215112 0.0200033 -1 -1 -1 -1 32 937 23 6.87369e+06 111791 586450. 2029.24 0.50 0.0651527 0.0569837 25474 144626 -1 774 21 527 527 36101 10508 1.18067 1.18067 -56.9294 -1.18067 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0145839 0.0125579 42 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 2.78 vpr 62.66 MiB -1 -1 0.17 17644 1 0.03 -1 -1 30472 -1 -1 10 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 23.6 MiB 0.11 503 9208 3768 5283 157 62.7 MiB 0.06 0.00 1.72973 -67.8771 -1.72973 1.72973 0.33 0.000386869 0.00035906 0.02257 0.0209781 -1 -1 -1 -1 36 1109 22 6.87369e+06 139738 648988. 2245.63 0.82 0.0992719 0.0860563 26050 158493 -1 898 22 643 643 58388 16256 1.24467 1.24467 -62.8028 -1.24467 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0165817 0.0143669 47 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 2.34 vpr 62.91 MiB -1 -1 0.17 17604 1 0.02 -1 -1 30380 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.7 MiB 0.09 607 6023 1283 4464 276 62.9 MiB 0.05 0.00 2.11206 -76.1943 -2.11206 2.11206 0.33 0.000426528 0.000396958 0.0153869 0.0143251 -1 -1 -1 -1 32 1299 16 6.87369e+06 125765 586450. 2029.24 0.48 0.0620614 0.0543264 25474 144626 -1 1097 14 609 609 45524 12761 1.34167 1.34167 -75.6214 -1.34167 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0127044 0.0111413 51 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 2.41 vpr 62.80 MiB -1 -1 0.17 17660 1 0.03 -1 -1 30076 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.5 MiB 0.09 789 12307 2769 8813 725 62.8 MiB 0.08 0.00 2.15606 -94.5222 -2.15606 2.15606 0.33 0.000492644 0.000458135 0.0286183 0.0266446 -1 -1 -1 -1 32 1559 17 6.87369e+06 153712 586450. 2029.24 0.53 0.0833133 0.0738776 25474 144626 -1 1393 18 688 688 59523 16512 1.49997 1.49997 -95.1329 -1.49997 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0173005 0.0151701 58 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 2.57 vpr 63.14 MiB -1 -1 0.17 17576 1 0.03 -1 -1 30072 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.11 981 17205 4139 12245 821 63.1 MiB 0.11 0.00 2.56039 -112.802 -2.56039 2.56039 0.34 0.0005709 0.000533122 0.0389788 0.0363756 -1 -1 -1 -1 32 1799 22 6.87369e+06 167686 586450. 2029.24 0.56 0.106634 0.0949936 25474 144626 -1 1617 15 720 720 63562 16203 1.47797 1.47797 -105.078 -1.47797 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0173981 0.0153283 67 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 2.89 vpr 63.28 MiB -1 -1 0.15 17828 1 0.03 -1 -1 30264 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 24.0 MiB 0.12 1584 31076 9475 18689 2912 63.3 MiB 0.19 0.00 3.45705 -193.743 -3.45705 3.45705 0.34 0.0008684 0.000814632 0.0625391 0.0585774 -1 -1 -1 -1 32 3068 37 6.87369e+06 251529 586450. 2029.24 0.78 0.189406 0.170897 25474 144626 -1 2611 15 1093 1093 100501 26292 1.79097 1.79097 -171.802 -1.79097 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0264197 0.0236566 99 2 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 3.73 vpr 64.25 MiB -1 -1 0.22 18156 1 0.04 -1 -1 30548 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65796 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.5 MiB 0.14 1992 52618 19565 29996 3057 64.3 MiB 0.34 0.01 4.35372 -280.144 -4.35372 4.35372 0.36 0.00122296 0.00115029 0.100997 0.0950032 -1 -1 -1 -1 34 3707 21 6.87369e+06 335372 618332. 2139.56 1.28 0.350781 0.318364 25762 151098 -1 3199 18 1360 1360 119854 30025 1.75637 1.75637 -212.671 -1.75637 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.04213 0.0380291 131 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_004bits.v common 1.95 vpr 62.20 MiB -1 -1 0.14 17356 1 0.02 -1 -1 29912 -1 -1 2 9 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63688 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.6 MiB 0.05 64 316 84 203 29 62.2 MiB 0.01 0.00 0.789073 -10.2315 -0.789073 0.789073 0.37 6.7432e-05 5.9105e-05 0.0014023 0.00123038 -1 -1 -1 -1 20 131 13 6.89349e+06 28187.7 414966. 1435.87 0.30 0.005288 0.00462994 23170 95770 -1 112 9 43 43 1879 665 0.79102 0.79102 -9.88956 -0.79102 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00293029 0.00260954 10 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 1.92 vpr 62.25 MiB -1 -1 0.16 17372 1 0.02 -1 -1 29916 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63744 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 23.5 MiB 0.03 158 587 141 409 37 62.2 MiB 0.01 0.00 0.834592 -14.4431 -0.834592 0.834592 0.34 0.000109323 9.9479e-05 0.00278401 0.00252793 -1 -1 -1 -1 22 303 8 6.89349e+06 42281.5 443629. 1535.05 0.32 0.0144953 0.0122181 23458 102101 -1 278 9 87 87 6583 1789 0.914373 0.914373 -16.0104 -0.914373 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00331916 0.00294637 13 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 2.05 vpr 62.27 MiB -1 -1 0.15 17272 1 0.02 -1 -1 30048 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63760 13 7 48 49 1 33 24 17 17 289 -1 unnamed_device 23.6 MiB 0.05 133 1044 310 591 143 62.3 MiB 0.01 0.00 0.833073 -15.9272 -0.833073 0.833073 0.34 0.000124785 0.000114174 0.00422947 0.00386489 -1 -1 -1 -1 26 290 13 6.89349e+06 56375.4 503264. 1741.40 0.36 0.0182724 0.0154763 24322 120374 -1 221 12 125 125 5631 2000 0.94932 0.94932 -16.2556 -0.94932 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.0041284 0.00360823 15 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 2.07 vpr 62.25 MiB -1 -1 0.09 17396 1 0.03 -1 -1 30132 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 23.8 MiB 0.04 133 1204 333 631 240 62.2 MiB 0.01 0.00 1.2044 -18.4031 -1.2044 1.2044 0.34 0.000139573 0.000128145 0.0049121 0.00451093 -1 -1 -1 -1 32 295 12 6.89349e+06 42281.5 586450. 2029.24 0.41 0.0205912 0.0174698 25474 144626 -1 203 14 129 129 5391 1760 0.853073 0.853073 -17.6358 -0.853073 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00488954 0.00422668 16 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 1.99 vpr 62.19 MiB -1 -1 0.15 17216 1 0.02 -1 -1 29988 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63680 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.7 MiB 0.05 147 1877 621 864 392 62.2 MiB 0.02 0.00 1.2154 -21.3086 -1.2154 1.2154 0.33 0.000157194 0.000144466 0.00719049 0.006617 -1 -1 -1 -1 26 326 10 6.89349e+06 42281.5 503264. 1741.40 0.36 0.0239307 0.0204765 24322 120374 -1 297 13 172 172 9130 2854 1.11467 1.11467 -23.1377 -1.11467 0 0 618332. 2139.56 0.03 0.01 0.08 -1 -1 0.03 0.00521984 0.00452385 19 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 2.15 vpr 62.36 MiB -1 -1 0.15 17412 1 0.02 -1 -1 30144 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63856 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 23.9 MiB 0.04 160 2382 879 1128 375 62.4 MiB 0.02 0.00 1.2264 -24.2382 -1.2264 1.2264 0.35 0.000196203 0.000178208 0.0083255 0.00754874 -1 -1 -1 -1 26 391 28 6.89349e+06 42281.5 503264. 1741.40 0.41 0.0303822 0.0257506 24322 120374 -1 301 12 172 172 9169 2958 0.88802 0.88802 -24.0325 -0.88802 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.0054245 0.00471594 20 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.13 vpr 62.29 MiB -1 -1 0.16 17316 1 0.02 -1 -1 30208 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63788 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 23.8 MiB 0.05 178 2101 697 1026 378 62.3 MiB 0.03 0.00 1.2374 -27.3972 -1.2374 1.2374 0.34 0.000272143 0.000242871 0.014502 0.0134048 -1 -1 -1 -1 26 398 15 6.89349e+06 56375.4 503264. 1741.40 0.41 0.0366146 0.031747 24322 120374 -1 357 12 211 211 13104 3962 1.00232 1.00232 -27.9123 -1.00232 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00586481 0.00508309 22 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 2.14 vpr 62.36 MiB -1 -1 0.15 17312 1 0.02 -1 -1 30020 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63856 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 23.9 MiB 0.05 194 2488 804 1234 450 62.4 MiB 0.02 0.00 1.2484 -29.9141 -1.2484 1.2484 0.34 0.000209881 0.00019386 0.00831107 0.00768353 -1 -1 -1 -1 32 419 16 6.89349e+06 70469.2 586450. 2029.24 0.44 0.0369654 0.0314569 25474 144626 -1 365 14 187 187 12612 3522 1.15867 1.15867 -31.3059 -1.15867 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00694411 0.00599348 24 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 2.17 vpr 62.26 MiB -1 -1 0.16 17436 1 0.02 -1 -1 30088 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63756 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 23.7 MiB 0.05 217 3493 1104 1725 664 62.3 MiB 0.05 0.00 1.2594 -32.5677 -1.2594 1.2594 0.34 0.000304479 0.000281407 0.0209988 0.0194009 -1 -1 -1 -1 32 482 20 6.89349e+06 70469.2 586450. 2029.24 0.43 0.0482192 0.0420835 25474 144626 -1 389 12 280 280 15448 4965 1.02237 1.02237 -32.661 -1.02237 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00656711 0.00568522 26 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 2.48 vpr 62.37 MiB -1 -1 0.16 17368 1 0.02 -1 -1 30088 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63868 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.8 MiB 0.05 241 2998 936 1427 635 62.4 MiB 0.03 0.00 1.2704 -35.731 -1.2704 1.2704 0.34 0.000238318 0.000220139 0.00954251 0.00882072 -1 -1 -1 -1 36 554 23 6.89349e+06 70469.2 648988. 2245.63 0.68 0.0569241 0.0482567 26050 158493 -1 470 11 304 304 20930 6434 1.17597 1.17597 -35.5601 -1.17597 0 0 828058. 2865.25 0.03 0.02 0.15 -1 -1 0.03 0.00655121 0.00571957 28 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 2.30 vpr 62.49 MiB -1 -1 0.15 17252 1 0.03 -1 -1 30068 -1 -1 7 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63988 29 15 104 105 1 74 51 17 17 289 -1 unnamed_device 23.8 MiB 0.06 311 4093 1430 1919 744 62.5 MiB 0.03 0.00 1.2814 -39.6 -1.2814 1.2814 0.34 0.00025249 0.000233658 0.0117448 0.0108621 -1 -1 -1 -1 32 651 22 6.89349e+06 98656.9 586450. 2029.24 0.45 0.0440558 0.0379748 25474 144626 -1 546 15 298 298 20497 5584 0.96032 0.96032 -37.5765 -0.96032 0 0 744469. 2576.02 0.03 0.02 0.13 -1 -1 0.03 0.00837419 0.00725538 31 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.23 vpr 62.42 MiB -1 -1 0.16 17588 1 0.02 -1 -1 30232 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63916 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.7 MiB 0.07 342 6191 2383 2979 829 62.4 MiB 0.04 0.00 1.65273 -42.5434 -1.65273 1.65273 0.35 0.000272263 0.000252147 0.0177761 0.0164574 -1 -1 -1 -1 28 782 16 6.89349e+06 84563 531479. 1839.03 0.47 0.050838 0.0446254 24610 126494 -1 632 16 412 412 30562 8836 1.09932 1.09932 -43.4614 -1.09932 0 0 648988. 2245.63 0.03 0.03 0.11 -1 -1 0.03 0.00917276 0.00791503 32 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 2.23 vpr 62.59 MiB -1 -1 0.16 17496 1 0.02 -1 -1 30196 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.9 MiB 0.07 355 5727 2349 2359 1019 62.6 MiB 0.04 0.00 1.66373 -46.554 -1.66373 1.66373 0.34 0.00029317 0.000271463 0.0164277 0.0152439 -1 -1 -1 -1 30 761 18 6.89349e+06 84563 556674. 1926.21 0.43 0.0452337 0.0395422 25186 138497 -1 615 14 322 322 20560 5635 1.13667 1.13667 -43.9673 -1.13667 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00900274 0.00782068 35 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 2.26 vpr 62.61 MiB -1 -1 0.15 17668 1 0.02 -1 -1 30096 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64116 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 24.0 MiB 0.07 391 6563 2630 3842 91 62.6 MiB 0.05 0.00 1.68573 -53.2796 -1.68573 1.68573 0.33 0.000328745 0.0003059 0.0180114 0.01674 -1 -1 -1 -1 30 836 17 6.89349e+06 98656.9 556674. 1926.21 0.44 0.0548421 0.0477938 25186 138497 -1 695 15 451 451 29891 8374 1.03337 1.03337 -49.3183 -1.03337 0 0 706193. 2443.58 0.03 0.03 0.13 -1 -1 0.03 0.0118554 0.0102459 38 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.36 vpr 62.61 MiB -1 -1 0.15 17628 1 0.02 -1 -1 30352 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.6 MiB 0.06 444 7702 3109 4434 159 62.6 MiB 0.05 0.00 1.70773 -59.9521 -1.70773 1.70773 0.33 0.000367369 0.000341624 0.0204269 0.0189835 -1 -1 -1 -1 32 990 21 6.89349e+06 112751 586450. 2029.24 0.51 0.0631649 0.0551747 25474 144626 -1 819 18 512 512 38144 10646 1.11467 1.11467 -55.3744 -1.11467 0 0 744469. 2576.02 0.06 0.04 0.12 -1 -1 0.06 0.0153282 0.0133693 42 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.91 vpr 62.58 MiB -1 -1 0.17 17744 1 0.02 -1 -1 30460 -1 -1 10 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 45 23 160 161 1 115 78 17 17 289 -1 unnamed_device 23.5 MiB 0.10 525 9208 3753 5295 160 62.6 MiB 0.06 0.00 1.72973 -67.5033 -1.72973 1.72973 0.34 0.000392949 0.000365341 0.0227959 0.0211971 -1 -1 -1 -1 38 1007 50 6.89349e+06 140938 678818. 2348.85 0.90 0.1159 0.10007 26626 170182 -1 870 15 498 498 29786 8882 1.34722 1.34722 -61.6964 -1.34722 0 0 902133. 3121.57 0.04 0.03 0.15 -1 -1 0.04 0.0128133 0.0111561 47 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 2.37 vpr 62.61 MiB -1 -1 0.16 17696 1 0.02 -1 -1 30324 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64116 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.5 MiB 0.08 661 9623 2236 7262 125 62.6 MiB 0.07 0.00 2.11206 -77.8242 -2.11206 2.11206 0.33 0.000423349 0.000394636 0.0238414 0.0221996 -1 -1 -1 -1 32 1386 20 6.89349e+06 126845 586450. 2029.24 0.50 0.0733721 0.0645323 25474 144626 -1 1142 15 563 563 48813 12563 1.46697 1.46697 -78.8793 -1.46697 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0131862 0.0115318 51 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 2.40 vpr 63.05 MiB -1 -1 0.14 17632 1 0.02 -1 -1 30148 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64564 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.6 MiB 0.08 791 11419 2578 8125 716 63.1 MiB 0.07 0.00 2.15606 -94.8463 -2.15606 2.15606 0.33 0.000485905 0.00045224 0.0262913 0.0244792 -1 -1 -1 -1 32 1495 15 6.89349e+06 155032 586450. 2029.24 0.50 0.0789967 0.0700395 25474 144626 -1 1370 17 655 655 52543 14035 1.33262 1.33262 -89.2547 -1.33262 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0163034 0.0142892 58 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.53 vpr 63.12 MiB -1 -1 0.17 17808 1 0.03 -1 -1 30108 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.09 986 17205 3974 12341 890 63.1 MiB 0.11 0.00 2.56039 -113.021 -2.56039 2.56039 0.33 0.000575876 0.000537719 0.0387672 0.0362165 -1 -1 -1 -1 30 1859 34 6.89349e+06 169126 556674. 1926.21 0.57 0.116327 0.103243 25186 138497 -1 1589 16 746 746 58837 14814 1.31532 1.31532 -101.149 -1.31532 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0180394 0.0158572 67 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.95 vpr 63.42 MiB -1 -1 0.17 17756 1 0.03 -1 -1 30288 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1569 31076 8349 20038 2689 63.4 MiB 0.19 0.00 3.45705 -193.838 -3.45705 3.45705 0.33 0.000873253 0.000818313 0.0625323 0.0585782 -1 -1 -1 -1 32 3055 34 6.89349e+06 253689 586450. 2029.24 0.75 0.184089 0.166063 25474 144626 -1 2514 15 1003 1003 86721 22065 1.69397 1.69397 -165.636 -1.69397 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0259565 0.0232087 99 2 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 3.51 vpr 63.59 MiB -1 -1 0.17 17944 1 0.03 -1 -1 30596 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.4 MiB 0.15 2051 53273 20114 30300 2859 63.6 MiB 0.35 0.01 4.35372 -281.486 -4.35372 4.35372 0.33 0.00119747 0.00112577 0.101104 0.0950117 -1 -1 -1 -1 34 3564 19 6.89349e+06 338252 618332. 2139.56 1.07 0.340154 0.308577 25762 151098 -1 3156 13 1279 1279 97169 24263 1.63107 1.63107 -202.647 -1.63107 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0325631 0.0294317 131 2 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt index 8e03af2eb66..8d0853d10c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -1,1025 +1,1025 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 6.67 vpr 63.87 MiB -1 -1 0.38 21968 14 0.32 -1 -1 36964 -1 -1 27 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65528 32 32 292 324 1 216 94 17 17 289 -1 unnamed_device 25.2 MiB 0.48 1429 10318 2408 6874 1036 64.0 MiB 0.08 0.00 7.55004 -148.529 -7.55004 7.55004 0.89 0.000355121 0.000289641 0.0192998 0.0157331 -1 -1 -1 -1 30 3702 21 6.55708e+06 361650 526063. 1820.29 1.65 0.103989 0.0904622 21886 126133 -1 3032 18 1348 4431 211919 49585 6.6027 6.6027 -144.169 -6.6027 0 0 666494. 2306.21 0.28 0.08 0.11 -1 -1 0.28 0.0235718 0.0212618 199 198 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 5.98 vpr 63.45 MiB -1 -1 0.27 21368 12 0.25 -1 -1 36280 -1 -1 28 27 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64972 27 32 229 261 1 178 87 17 17 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64772 30 32 216 248 1 168 86 17 17 289 -1 unnamed_device 24.8 MiB 0.52 975 6890 1484 5091 315 63.3 MiB 0.05 0.00 7.2876 -142.231 -7.2876 7.2876 1.10 0.000226144 0.000179001 0.0105934 0.00869922 -1 -1 -1 -1 28 2669 16 6.55708e+06 289320 500653. 1732.36 1.81 0.0706326 0.0616944 21310 115450 -1 2344 20 978 2637 155411 35551 6.35264 6.35264 -138.448 -6.35264 0 0 612192. 2118.31 0.29 0.06 0.11 -1 -1 0.29 0.0188124 0.0168309 132 128 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 7.22 vpr 63.11 MiB -1 -1 0.25 21300 12 0.22 -1 -1 36160 -1 -1 22 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64624 32 32 236 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65652 32 32 301 333 1 230 97 17 17 289 -1 unnamed_device 25.3 MiB 0.52 1403 9865 2364 6534 967 64.1 MiB 0.08 0.00 7.61832 -157.97 -7.61832 7.61832 0.99 0.000327782 0.000258845 0.0189479 0.0155529 -1 -1 -1 -1 34 4162 40 6.55708e+06 397815 585099. 2024.56 3.52 0.164137 0.141129 22462 138074 -1 3561 16 1531 5053 312901 69003 7.03204 7.03204 -158.379 -7.03204 0 0 742403. 2568.87 0.31 0.12 0.13 -1 -1 0.31 0.0327397 0.030075 209 207 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_017.v common 7.55 vpr 63.92 MiB -1 -1 0.53 22016 14 0.32 -1 -1 36528 -1 -1 29 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65452 32 32 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65552 32 32 354 285 1 202 96 17 17 289 -1 unnamed_device 25.2 MiB 0.35 1021 13017 3203 8186 1628 64.0 MiB 0.11 0.00 5.56529 -159.911 -5.56529 5.56529 0.99 0.000262042 0.000209334 0.0174063 0.0141423 -1 -1 -1 -1 32 2485 24 6.64007e+06 401856 554710. 1919.41 1.14 0.0768703 0.0652357 22834 132086 -1 2178 21 1579 2366 153039 36543 4.64968 4.64968 -151.131 -4.64968 0 0 701300. 2426.64 0.34 0.06 0.14 -1 -1 0.34 0.0160783 0.0141966 154 50 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 4.99 vpr 64.14 MiB -1 -1 0.20 21392 1 0.04 -1 -1 33844 -1 -1 25 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65676 30 32 363 293 1 196 87 17 17 289 -1 unnamed_device 25.3 MiB 0.36 1071 13527 3636 8473 1418 64.1 MiB 0.10 0.00 4.97921 -144.408 -4.97921 4.97921 0.97 0.000238803 0.000193386 0.0186601 0.015077 -1 -1 -1 -1 32 2399 23 6.64007e+06 313950 554710. 1919.41 1.01 0.0633653 0.0530196 22834 132086 -1 2149 20 1658 2519 162674 39380 4.22689 4.22689 -145.337 -4.22689 0 0 701300. 2426.64 0.32 0.07 0.14 -1 -1 0.32 0.0201902 0.0180317 141 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 6.17 vpr 63.65 MiB -1 -1 0.20 21440 1 0.04 -1 -1 33860 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65176 32 32 299 247 1 188 87 17 17 289 -1 unnamed_device 25.0 MiB 0.37 1084 15639 4927 8621 2091 63.6 MiB 0.13 0.00 4.35433 -126.133 -4.35433 4.35433 1.59 0.000353368 0.000291955 0.0217877 0.0179552 -1 -1 -1 -1 32 2438 19 6.64007e+06 288834 554710. 1919.41 1.25 0.0699429 0.0595596 22834 132086 -1 2059 19 1091 1550 105201 24017 3.66183 3.66183 -123.368 -3.66183 0 0 701300. 2426.64 0.32 0.05 0.13 -1 -1 0.32 0.0145392 0.0129226 126 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 5.32 vpr 63.88 MiB -1 -1 0.22 21504 1 0.06 -1 -1 33624 -1 -1 27 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65412 29 32 308 248 1 169 88 17 17 289 -1 unnamed_device 25.2 MiB 0.14 931 15103 4868 7954 2281 63.9 MiB 0.11 0.00 4.52953 -121.776 -4.52953 4.52953 1.05 0.00019656 0.000155738 0.0174707 0.0140635 -1 -1 -1 -1 32 2287 23 6.64007e+06 339066 554710. 1919.41 1.16 0.0700707 0.0594773 22834 132086 -1 1914 23 1465 2740 192952 43744 3.67063 3.67063 -116.076 -3.67063 0 0 701300. 2426.64 0.39 0.08 0.16 -1 -1 0.39 0.0184129 0.0163026 126 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 4.89 vpr 64.08 MiB -1 -1 0.22 21580 1 0.06 -1 -1 33800 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 336 268 1 174 87 17 17 289 -1 unnamed_device 25.2 MiB 0.16 1007 10071 2662 6608 801 64.1 MiB 0.08 0.00 4.57112 -132.997 -4.57112 4.57112 0.92 0.000203708 0.000161888 0.0128959 0.0104931 -1 -1 -1 -1 32 2498 20 6.64007e+06 288834 554710. 1919.41 0.96 0.053404 0.0450429 22834 132086 -1 2122 21 1503 2874 185659 42276 3.64943 3.64943 -130.19 -3.64943 0 0 701300. 2426.64 0.30 0.07 0.14 -1 -1 0.30 0.0166273 0.0146895 130 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 5.30 vpr 64.21 MiB -1 -1 0.27 21392 1 0.06 -1 -1 33776 -1 -1 34 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65748 32 32 366 295 1 189 98 17 17 289 -1 unnamed_device 25.4 MiB 0.21 1017 13373 3190 9207 976 64.2 MiB 0.11 0.00 3.5011 -120.17 -3.5011 3.5011 0.99 0.000318473 0.00026043 0.0171614 0.0139947 -1 -1 -1 -1 28 2759 36 6.64007e+06 426972 500653. 1732.36 1.31 0.0862329 0.0726462 21970 115934 -1 2279 18 1387 2237 156657 37609 2.89817 2.89817 -120.057 -2.89817 0 0 612192. 2118.31 0.28 0.06 0.11 -1 -1 0.28 0.0162124 0.0141661 142 58 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 4.61 vpr 63.41 MiB -1 -1 0.20 21408 1 0.05 -1 -1 34356 -1 -1 19 27 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64928 27 32 259 221 1 130 78 17 17 289 -1 unnamed_device 24.9 MiB 0.14 699 11034 3536 5995 1503 63.4 MiB 0.07 0.00 3.75638 -102.609 -3.75638 3.75638 0.94 0.000156739 0.000123123 0.0131456 0.0106723 -1 -1 -1 -1 32 1595 18 6.64007e+06 238602 554710. 1919.41 0.87 0.0417151 0.0348347 22834 132086 -1 1412 20 879 1541 105739 24721 3.09756 3.09756 -96.0776 -3.09756 0 0 701300. 2426.64 0.31 0.04 0.13 -1 -1 0.31 0.0115122 0.0101614 93 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 5.62 vpr 63.45 MiB -1 -1 0.18 21640 1 0.03 -1 -1 33768 -1 -1 31 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64968 31 32 271 219 1 162 94 17 17 289 -1 unnamed_device 24.7 MiB 0.21 827 11383 2423 8400 560 63.4 MiB 0.08 0.00 3.48559 -101.391 -3.48559 3.48559 1.10 0.000211519 0.000168259 0.0119728 0.00969488 -1 -1 -1 -1 28 2163 36 6.64007e+06 389298 500653. 1732.36 1.29 0.0670566 0.0567176 21970 115934 -1 1858 21 1080 1973 129274 30214 2.87017 2.87017 -99.5446 -2.87017 0 0 612192. 2118.31 0.30 0.05 0.15 -1 -1 0.30 0.0147154 0.0129521 115 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 5.57 vpr 63.82 MiB -1 -1 0.22 21488 1 0.04 -1 -1 34160 -1 -1 20 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65352 31 32 317 271 1 167 83 17 17 289 -1 unnamed_device 25.0 MiB 0.40 888 14123 4595 7521 2007 63.8 MiB 0.09 0.00 3.62422 -120.034 -3.62422 3.62422 1.08 0.000187515 0.000146379 0.0174094 0.0140366 -1 -1 -1 -1 32 1992 19 6.64007e+06 251160 554710. 1919.41 1.10 0.0554197 0.0466476 22834 132086 -1 1743 19 1121 1661 106825 24557 2.99817 2.99817 -113.252 -2.99817 0 0 701300. 2426.64 0.41 0.06 0.16 -1 -1 0.41 0.0187606 0.016777 111 64 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 5.16 vpr 63.52 MiB -1 -1 0.33 21600 1 0.04 -1 -1 33748 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65040 32 32 298 248 1 156 81 17 17 289 -1 unnamed_device 25.0 MiB 0.24 874 11631 3631 6742 1258 63.5 MiB 0.10 0.00 3.92955 -127.77 -3.92955 3.92955 0.95 0.000189701 0.000150054 0.01562 0.0126926 -1 -1 -1 -1 32 1957 19 6.64007e+06 213486 554710. 1919.41 1.03 0.0525554 0.0441712 22834 132086 -1 1753 19 1044 1681 109300 25609 2.90177 2.90177 -115.584 -2.90177 0 0 701300. 2426.64 0.34 0.06 0.13 -1 -1 0.34 0.0152293 0.0134552 112 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 5.31 vpr 63.82 MiB -1 -1 0.33 21556 1 0.04 -1 -1 33372 -1 -1 17 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65352 30 32 303 262 1 139 79 17 17 289 -1 unnamed_device 24.9 MiB 0.18 728 11571 3255 7389 927 63.8 MiB 0.08 0.00 4.13115 -112.218 -4.13115 4.13115 0.99 0.00019662 0.000157478 0.0166224 0.0136254 -1 -1 -1 -1 28 1735 19 6.64007e+06 213486 500653. 1732.36 1.07 0.0606006 0.0517093 21970 115934 -1 1482 19 805 1293 87516 20285 2.86597 2.86597 -102.428 -2.86597 0 0 612192. 2118.31 0.39 0.05 0.14 -1 -1 0.39 0.0153816 0.0137322 98 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 5.44 vpr 63.54 MiB -1 -1 0.26 21364 1 0.05 -1 -1 33692 -1 -1 18 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65064 32 32 276 237 1 166 82 17 17 289 -1 unnamed_device 25.0 MiB 0.43 793 12008 4621 6063 1324 63.5 MiB 0.09 0.00 3.82041 -120.517 -3.82041 3.82041 1.09 0.000206546 0.00016439 0.0165982 0.0136384 -1 -1 -1 -1 32 2253 40 6.64007e+06 226044 554710. 1919.41 1.09 0.0618556 0.0518993 22834 132086 -1 1803 21 1195 1619 115534 26931 3.04337 3.04337 -115.258 -3.04337 0 0 701300. 2426.64 0.31 0.05 0.16 -1 -1 0.31 0.0126872 0.0111863 109 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 5.32 vpr 64.04 MiB -1 -1 0.21 21500 1 0.05 -1 -1 33892 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65576 32 32 344 272 1 202 88 17 17 289 -1 unnamed_device 25.3 MiB 0.39 1104 18028 6323 9464 2241 64.0 MiB 0.14 0.00 4.4826 -145.148 -4.4826 4.4826 0.94 0.000209899 0.000165632 0.0218027 0.0175323 -1 -1 -1 -1 32 2419 20 6.64007e+06 301392 554710. 1919.41 0.97 0.0592191 0.0492291 22834 132086 -1 2198 21 1658 2485 165389 37416 3.29783 3.29783 -129.319 -3.29783 0 0 701300. 2426.64 0.30 0.06 0.12 -1 -1 0.30 0.0171025 0.0151608 139 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 5.28 vpr 64.12 MiB -1 -1 0.25 21504 1 0.06 -1 -1 33764 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65656 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 25.1 MiB 0.20 965 15215 3853 10047 1315 64.1 MiB 0.13 0.00 4.76344 -140.281 -4.76344 4.76344 0.96 0.000216134 0.000170764 0.0181941 0.0146872 -1 -1 -1 -1 28 2304 23 6.64007e+06 389298 500653. 1732.36 0.97 0.0576001 0.047902 21970 115934 -1 2045 22 1662 2823 167404 40668 3.88183 3.88183 -136.686 -3.88183 0 0 612192. 2118.31 0.31 0.08 0.12 -1 -1 0.31 0.0224895 0.0200196 134 61 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 4.69 vpr 63.23 MiB -1 -1 0.19 21300 1 0.04 -1 -1 33776 -1 -1 21 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64752 29 32 248 215 1 137 82 17 17 289 -1 unnamed_device 24.7 MiB 0.16 748 11118 2695 7379 1044 63.2 MiB 0.07 0.00 3.28519 -93.7186 -3.28519 3.28519 1.02 0.000177763 0.000143001 0.0123985 0.0100246 -1 -1 -1 -1 28 1645 23 6.64007e+06 263718 500653. 1732.36 0.88 0.044401 0.0373413 21970 115934 -1 1486 16 782 1301 86789 20385 2.71577 2.71577 -91.5176 -2.71577 0 0 612192. 2118.31 0.27 0.04 0.11 -1 -1 0.27 0.01224 0.0110447 98 27 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 5.02 vpr 63.95 MiB -1 -1 0.22 21472 1 0.05 -1 -1 33820 -1 -1 22 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65488 32 32 370 297 1 183 86 17 17 289 -1 unnamed_device 25.2 MiB 0.26 1002 9914 2245 7192 477 64.0 MiB 0.09 0.00 4.06227 -126.501 -4.06227 4.06227 1.04 0.000339478 0.000280459 0.0150671 0.0122767 -1 -1 -1 -1 32 2466 22 6.64007e+06 276276 554710. 1919.41 1.00 0.0625471 0.0525543 22834 132086 -1 2152 20 1479 2608 179323 41071 3.09436 3.09436 -120.061 -3.09436 0 0 701300. 2426.64 0.32 0.06 0.13 -1 -1 0.32 0.0175048 0.0154791 133 58 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 5.42 vpr 64.18 MiB -1 -1 0.19 21340 1 0.05 -1 -1 33692 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65720 32 32 338 269 1 196 87 17 17 289 -1 unnamed_device 25.2 MiB 0.36 1138 14679 4370 8457 1852 64.2 MiB 0.11 0.00 4.43584 -143.418 -4.43584 4.43584 1.02 0.000208117 0.000164792 0.0181344 0.0146421 -1 -1 -1 -1 30 2626 19 6.64007e+06 288834 526063. 1820.29 0.98 0.0603549 0.0505747 22546 126617 -1 2242 21 1375 2016 134012 29343 3.26883 3.26883 -128.611 -3.26883 0 0 666494. 2306.21 0.36 0.07 0.17 -1 -1 0.36 0.0224568 0.0201398 138 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 5.32 vpr 63.82 MiB -1 -1 0.30 21340 1 0.05 -1 -1 33492 -1 -1 29 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65352 32 32 323 276 1 153 93 17 17 289 -1 unnamed_device 25.0 MiB 0.26 793 7443 1484 5603 356 63.8 MiB 0.06 0.00 2.85064 -101.719 -2.85064 2.85064 1.07 0.000198513 0.000156054 0.00909122 0.00743855 -1 -1 -1 -1 30 1881 18 6.64007e+06 364182 526063. 1820.29 0.90 0.0436512 0.0367 22546 126617 -1 1524 20 1018 1637 84819 20502 2.06951 2.06951 -94.0823 -2.06951 0 0 666494. 2306.21 0.33 0.05 0.13 -1 -1 0.33 0.0163235 0.0143174 110 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 4.87 vpr 63.29 MiB -1 -1 0.22 21284 1 0.05 -1 -1 33884 -1 -1 15 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64812 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 24.7 MiB 0.09 601 7249 1675 5111 463 63.3 MiB 0.05 0.00 2.38033 -78.5571 -2.38033 2.38033 1.07 0.000226234 0.000187174 0.00846696 0.00685607 -1 -1 -1 -1 28 1432 21 6.64007e+06 188370 500653. 1732.36 0.93 0.041199 0.0342952 21970 115934 -1 1285 21 703 1012 85737 19690 2.04611 2.04611 -83.9383 -2.04611 0 0 612192. 2118.31 0.32 0.07 0.11 -1 -1 0.32 0.0196938 0.0172901 81 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 4.90 vpr 63.76 MiB -1 -1 0.20 21368 1 0.04 -1 -1 34160 -1 -1 20 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65288 31 32 291 243 1 171 83 17 17 289 -1 unnamed_device 25.2 MiB 0.32 927 14123 4588 7430 2105 63.8 MiB 0.11 0.00 4.95484 -148.86 -4.95484 4.95484 0.99 0.000188824 0.000149089 0.0186224 0.0151145 -1 -1 -1 -1 30 2054 21 6.64007e+06 251160 526063. 1820.29 0.95 0.0564355 0.0468617 22546 126617 -1 1848 20 956 1399 83300 19321 3.50023 3.50023 -130.959 -3.50023 0 0 666494. 2306.21 0.31 0.04 0.12 -1 -1 0.31 0.0130819 0.0114957 128 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 4.97 vpr 63.84 MiB -1 -1 0.20 21504 1 0.04 -1 -1 33988 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65368 32 32 342 271 1 179 95 17 17 289 -1 unnamed_device 24.9 MiB 0.14 927 7007 1409 5318 280 63.8 MiB 0.07 0.00 4.20815 -131.502 -4.20815 4.20815 1.01 0.00023098 0.000185719 0.00998554 0.00820313 -1 -1 -1 -1 30 2145 21 6.64007e+06 389298 526063. 1820.29 1.14 0.0561432 0.0479782 22546 126617 -1 1871 22 1181 1998 116468 26613 3.49343 3.49343 -124.596 -3.49343 0 0 666494. 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64908 32 32 285 227 1 165 85 17 17 289 -1 unnamed_device 24.9 MiB 0.13 995 9571 2665 6351 555 63.4 MiB 0.08 0.00 4.78226 -126.055 -4.78226 4.78226 0.96 0.000205893 0.000165719 0.0121023 0.00991669 -1 -1 -1 -1 28 2148 21 6.64007e+06 263718 500653. 1732.36 1.00 0.0515538 0.0439022 21970 115934 -1 1974 21 1150 2159 136149 31256 3.72363 3.72363 -120.986 -3.72363 0 0 612192. 2118.31 0.31 0.06 0.12 -1 -1 0.31 0.0155218 0.0138177 118 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 4.81 vpr 63.03 MiB -1 -1 0.19 21208 1 0.06 -1 -1 33524 -1 -1 14 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64540 32 32 173 169 1 116 78 17 17 289 -1 unnamed_device 24.6 MiB 0.08 542 9374 3354 4039 1981 63.0 MiB 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64932 32 32 284 241 1 145 80 17 17 289 -1 unnamed_device 24.7 MiB 0.12 785 11260 3393 5970 1897 63.4 MiB 0.07 0.00 3.03896 -100.907 -3.03896 3.03896 0.94 0.000176898 0.00013967 0.0136204 0.0110501 -1 -1 -1 -1 32 1803 19 6.64007e+06 200928 554710. 1919.41 0.91 0.0451775 0.0379823 22834 132086 -1 1509 18 768 1281 82415 19190 2.69497 2.69497 -101.097 -2.69497 0 0 701300. 2426.64 0.32 0.04 0.12 -1 -1 0.32 0.0127569 0.0112808 101 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 5.06 vpr 63.28 MiB -1 -1 0.32 21604 1 0.04 -1 -1 33544 -1 -1 23 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64800 30 32 262 227 1 135 85 17 17 289 -1 unnamed_device 24.8 MiB 0.12 760 10873 2730 7151 992 63.3 MiB 0.07 0.00 3.24119 -98.8846 -3.24119 3.24119 0.98 0.000228736 0.000184866 0.0130461 0.0105578 -1 -1 -1 -1 32 1618 23 6.64007e+06 288834 554710. 1919.41 0.95 0.0475561 0.0394843 22834 132086 -1 1566 17 817 1243 85514 19258 2.68277 2.68277 -96.8564 -2.68277 0 0 701300. 2426.64 0.48 0.07 0.14 -1 -1 0.48 0.0185708 0.0165051 97 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 4.97 vpr 63.43 MiB -1 -1 0.20 21612 1 0.04 -1 -1 33908 -1 -1 23 28 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64956 28 32 260 223 1 140 83 17 17 289 -1 unnamed_device 24.8 MiB 0.19 598 14123 3741 8412 1970 63.4 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 367 282 1 201 102 17 17 289 -1 unnamed_device 25.4 MiB 0.24 1108 10812 2420 7290 1102 64.3 MiB 0.10 0.00 4.35696 -124.357 -4.35696 4.35696 1.12 0.000281467 0.000232586 0.0135953 0.01126 -1 -1 -1 -1 26 3426 39 6.64007e+06 477204 477104. 1650.88 2.25 0.0816647 0.0694832 21682 110474 -1 2530 19 1336 2472 192577 43808 3.82982 3.82982 -127.968 -3.82982 0 0 585099. 2024.56 0.30 0.07 0.12 -1 -1 0.30 0.0175832 0.0156085 151 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 5.44 vpr 64.26 MiB -1 -1 0.24 21768 1 0.04 -1 -1 34128 -1 -1 37 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65716 31 32 352 285 1 184 94 17 17 289 -1 unnamed_device 25.3 MiB 0.24 1006 12661 3249 8412 1000 64.2 MiB 0.16 0.01 4.68524 -135.636 -4.68524 4.68524 1.03 0.000722622 0.000625663 0.0250127 0.0210209 -1 -1 -1 -1 32 2355 20 6.64007e+06 389298 554710. 1919.41 1.21 0.0832415 0.0717902 22834 132086 -1 2083 21 944 1573 101119 23699 3.58023 3.58023 -126.148 -3.58023 0 0 701300. 2426.64 0.32 0.05 0.15 -1 -1 0.32 0.0158948 0.0139738 135 55 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 5.56 vpr 63.61 MiB -1 -1 0.26 21404 1 0.03 -1 -1 33824 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65132 32 32 291 242 1 179 87 17 17 289 -1 unnamed_device 25.0 MiB 0.53 1073 14679 4707 8091 1881 63.6 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65572 32 32 349 284 1 183 97 17 17 289 -1 unnamed_device 25.2 MiB 0.25 884 8755 1783 6202 770 64.0 MiB 0.07 0.00 3.97129 -116.286 -3.97129 3.97129 0.94 0.000211094 0.000165612 0.0106346 0.00864227 -1 -1 -1 -1 30 2199 23 6.64007e+06 414414 526063. 1820.29 1.19 0.0625556 0.0533276 22546 126617 -1 1729 19 894 1557 79184 20282 3.00716 3.00716 -105.065 -3.00716 0 0 666494. 2306.21 0.30 0.04 0.12 -1 -1 0.30 0.0143951 0.0127001 131 53 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 5.18 vpr 63.77 MiB -1 -1 0.25 21256 1 0.05 -1 -1 33536 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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33904 -1 -1 29 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65020 32 32 306 248 1 166 93 17 17 289 -1 unnamed_device 24.9 MiB 0.14 831 7023 1481 5311 231 63.5 MiB 0.06 0.00 4.19967 -120.534 -4.19967 4.19967 0.89 0.000188041 0.000148682 0.00905889 0.00752255 -1 -1 -1 -1 30 2034 22 6.64007e+06 364182 526063. 1820.29 0.94 0.0439327 0.0370242 22546 126617 -1 1614 21 1040 1872 100357 23807 3.57043 3.57043 -112.869 -3.57043 0 0 666494. 2306.21 0.29 0.04 0.12 -1 -1 0.29 0.0137281 0.0120905 122 24 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 5.40 vpr 64.20 MiB -1 -1 0.19 21432 1 0.04 -1 -1 33776 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 319 257 1 198 88 17 17 289 -1 unnamed_device 25.2 MiB 0.45 1052 7888 1681 5591 616 64.2 MiB 0.08 0.00 5.2222 -143.082 -5.2222 5.2222 1.09 0.000318555 0.000263924 0.013931 0.0116803 -1 -1 -1 -1 28 2639 22 6.64007e+06 301392 500653. 1732.36 1.08 0.0632308 0.0538295 21970 115934 -1 2239 17 1340 1967 134731 31386 3.71362 3.71362 -131.242 -3.71362 0 0 612192. 2118.31 0.31 0.06 0.12 -1 -1 0.31 0.0160942 0.0142582 133 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 5.29 vpr 64.23 MiB -1 -1 0.22 21816 1 0.06 -1 -1 33676 -1 -1 25 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65776 31 32 373 299 1 202 88 17 17 289 -1 unnamed_device 25.4 MiB 0.39 1063 10423 2679 6644 1100 64.2 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65540 32 32 387 293 1 234 93 17 17 289 -1 unnamed_device 25.6 MiB 0.40 1389 17943 5716 10178 2049 64.0 MiB 0.17 0.00 5.4603 -164.178 -5.4603 5.4603 1.18 0.000282336 0.000220511 0.0250041 0.0204041 -1 -1 -1 -1 28 3504 25 6.64007e+06 364182 500653. 1732.36 1.52 0.0959882 0.0817493 21970 115934 -1 2796 23 2045 3229 234229 51765 4.64188 4.64188 -157.599 -4.64188 0 0 612192. 2118.31 0.27 0.08 0.11 -1 -1 0.27 0.0202234 0.0178275 169 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 5.19 vpr 63.91 MiB -1 -1 0.28 21560 1 0.04 -1 -1 33716 -1 -1 32 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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21180 1 0.05 -1 -1 33872 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65108 32 32 231 199 1 140 87 17 17 289 -1 unnamed_device 25.0 MiB 0.14 820 12375 3515 6889 1971 63.6 MiB 0.08 0.00 3.58247 -102.606 -3.58247 3.58247 0.97 0.000159828 0.000126602 0.0121084 0.00973774 -1 -1 -1 -1 26 1980 30 6.64007e+06 288834 477104. 1650.88 1.06 0.051103 0.0428844 21682 110474 -1 1821 19 887 1524 111639 25164 2.89497 2.89497 -103.885 -2.89497 0 0 585099. 2024.56 0.27 0.05 0.10 -1 -1 0.27 0.0120726 0.0105132 100 3 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 5.05 vpr 64.29 MiB -1 -1 0.23 21640 1 0.04 -1 -1 33820 -1 -1 34 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65836 32 32 349 273 1 191 98 17 17 289 -1 unnamed_device 25.5 MiB 0.20 1051 10223 2392 7301 530 64.3 MiB 0.10 0.00 5.62381 -137.312 -5.62381 5.62381 1.04 0.000244483 0.000192777 0.013702 0.011257 -1 -1 -1 -1 32 2518 24 6.64007e+06 426972 554710. 1919.41 1.12 0.0618896 0.0527029 22834 132086 -1 2171 22 1308 2453 164918 36700 4.71868 4.71868 -136.031 -4.71868 0 0 701300. 2426.64 0.32 0.06 0.13 -1 -1 0.32 0.0164181 0.0144813 139 29 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 4.59 vpr 63.52 MiB -1 -1 0.17 21200 1 0.05 -1 -1 33872 -1 -1 20 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65048 32 32 247 207 1 147 84 17 17 289 -1 unnamed_device 25.0 MiB 0.12 692 7404 1537 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65416 32 32 353 285 1 181 92 17 17 289 -1 unnamed_device 25.2 MiB 0.19 1028 16652 5035 9308 2309 63.9 MiB 0.14 0.00 4.7434 -142.045 -4.7434 4.7434 0.97 0.000229766 0.00018499 0.0243846 0.0198378 -1 -1 -1 -1 32 2433 20 6.64007e+06 351624 554710. 1919.41 1.00 0.06708 0.0561858 22834 132086 -1 2181 18 1038 1785 133597 29133 3.69062 3.69062 -131.911 -3.69062 0 0 701300. 2426.64 0.33 0.05 0.13 -1 -1 0.33 0.0149977 0.0132236 133 51 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 5.50 vpr 63.62 MiB -1 -1 0.21 21616 1 0.05 -1 -1 33724 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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21492 1 0.04 -1 -1 34116 -1 -1 18 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65384 30 32 317 269 1 152 80 17 17 289 -1 unnamed_device 25.1 MiB 0.18 685 9712 2247 6957 508 63.9 MiB 0.08 0.00 3.90078 -114.184 -3.90078 3.90078 0.96 0.000194964 0.000153905 0.0128951 0.0104153 -1 -1 -1 -1 28 1963 19 6.64007e+06 226044 500653. 1732.36 0.97 0.0472529 0.0394904 21970 115934 -1 1789 22 1400 2435 194018 45480 2.98097 2.98097 -109.97 -2.98097 0 0 612192. 2118.31 0.28 0.07 0.12 -1 -1 0.28 0.0167959 0.0148587 109 63 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 5.24 vpr 64.14 MiB -1 -1 0.33 21572 1 0.06 -1 -1 33652 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65104 30 32 272 232 1 147 81 17 17 289 -1 unnamed_device 24.9 MiB 0.16 720 9706 2873 5961 872 63.6 MiB 0.07 0.00 3.87875 -113.748 -3.87875 3.87875 0.91 0.00018793 0.000151889 0.0114303 0.00926962 -1 -1 -1 -1 26 1992 21 6.64007e+06 238602 477104. 1650.88 1.06 0.049573 0.0421375 21682 110474 -1 1698 18 953 1613 112771 26555 2.90297 2.90297 -105.777 -2.90297 0 0 585099. 2024.56 0.26 0.05 0.12 -1 -1 0.26 0.0129574 0.0114093 104 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 5.81 vpr 64.20 MiB -1 -1 0.22 21484 1 0.05 -1 -1 34016 -1 -1 23 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65700 29 32 378 310 1 177 92 17 17 289 -1 unnamed_device 25.4 MiB 0.23 991 14168 3722 8736 1710 64.2 MiB 0.10 0.00 4.90164 -138.394 -4.90164 4.90164 0.95 0.000240485 0.000190466 0.0175885 0.0141857 -1 -1 -1 -1 26 2358 19 6.64007e+06 389298 477104. 1650.88 0.87 0.0554864 0.0462143 21682 110474 -1 2059 21 1193 1929 132387 29914 3.62843 3.62843 -127.623 -3.62843 0 0 585099. 2024.56 0.25 0.05 0.11 -1 -1 0.25 0.0161528 0.0141862 132 85 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 4.70 vpr 63.33 MiB -1 -1 0.25 21144 1 0.05 -1 -1 33904 -1 -1 15 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64848 32 32 243 205 1 139 79 17 17 289 -1 unnamed_device 24.9 MiB 0.11 698 12416 3955 6725 1736 63.3 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65008 31 32 245 205 1 150 84 17 17 289 -1 unnamed_device 24.9 MiB 0.20 781 9417 2297 6451 669 63.5 MiB 0.07 0.00 3.81035 -109.522 -3.81035 3.81035 0.99 0.000163905 0.000129827 0.0101809 0.00828012 -1 -1 -1 -1 32 1805 21 6.64007e+06 263718 554710. 1919.41 1.21 0.072009 0.0621269 22834 132086 -1 1623 22 1006 1686 116113 26730 2.91397 2.91397 -103.946 -2.91397 0 0 701300. 2426.64 0.30 0.04 0.13 -1 -1 0.30 0.0115767 0.0101536 106 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 5.45 vpr 64.18 MiB -1 -1 0.23 21704 1 0.05 -1 -1 34084 -1 -1 26 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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0.04 -1 -1 34048 -1 -1 21 27 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64872 27 32 255 219 1 132 80 17 17 289 -1 unnamed_device 24.8 MiB 0.11 565 12120 3265 7503 1352 63.4 MiB 0.07 0.00 3.49724 -93.0073 -3.49724 3.49724 1.03 0.000169753 0.000135028 0.0143122 0.0115101 -1 -1 -1 -1 28 1552 21 6.64007e+06 263718 500653. 1732.36 0.90 0.0472616 0.0391207 21970 115934 -1 1349 20 1009 1487 99406 23958 2.83997 2.83997 -92.1671 -2.83997 0 0 612192. 2118.31 0.29 0.04 0.12 -1 -1 0.29 0.0120089 0.0104757 97 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 6.88 vpr 64.02 MiB -1 -1 0.23 21820 1 0.04 -1 -1 33960 -1 -1 26 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65560 32 32 421 327 1 232 90 17 17 289 -1 unnamed_device 25.5 MiB 0.40 1324 16572 5072 8808 2692 64.0 MiB 0.18 0.00 4.42635 -141.521 -4.42635 4.42635 1.59 0.00121267 0.00107701 0.0369494 0.0309745 -1 -1 -1 -1 32 3259 35 6.64007e+06 326508 554710. 1919.41 1.59 0.136479 0.117122 22834 132086 -1 2737 20 1821 3112 227397 48414 4.03623 4.03623 -137.329 -4.03623 0 0 701300. 2426.64 0.29 0.07 0.23 -1 -1 0.29 0.0169385 0.0148813 170 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 5.45 vpr 63.98 MiB -1 -1 0.23 21860 1 0.05 -1 -1 34032 -1 -1 23 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65512 31 32 365 296 1 193 86 17 17 289 -1 unnamed_device 25.2 MiB 0.47 1050 12371 3182 7852 1337 64.0 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65424 30 32 325 268 1 171 93 17 17 289 -1 unnamed_device 25.0 MiB 0.22 1000 10173 2480 6565 1128 63.9 MiB 0.12 0.00 3.68089 -112.079 -3.68089 3.68089 1.02 0.000444252 0.000360705 0.0216755 0.0182489 -1 -1 -1 -1 32 2189 21 6.64007e+06 389298 554710. 1919.41 1.11 0.0855121 0.0731107 22834 132086 -1 1934 21 992 1861 125297 27515 2.93217 2.93217 -104.52 -2.93217 0 0 701300. 2426.64 0.41 0.07 0.17 -1 -1 0.41 0.0232143 0.0207969 124 51 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 5.60 vpr 64.41 MiB -1 -1 0.27 21612 1 0.04 -1 -1 33768 -1 -1 25 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65960 32 32 350 275 1 214 89 17 17 289 -1 unnamed_device 25.5 MiB 0.43 1181 8207 1889 5862 456 64.4 MiB 0.09 0.00 5.21333 -162.921 -5.21333 5.21333 1.03 0.000226497 0.000177397 0.0119918 0.00982629 -1 -1 -1 -1 32 2916 22 6.64007e+06 313950 554710. 1919.41 1.32 0.0706068 0.0607564 22834 132086 -1 2540 21 1769 2749 219470 47322 4.11269 4.11269 -146.472 -4.11269 0 0 701300. 2426.64 0.31 0.07 0.12 -1 -1 0.31 0.0180291 0.0158781 148 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 5.98 vpr 64.14 MiB -1 -1 0.24 21904 1 0.05 -1 -1 33800 -1 -1 36 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 386 307 1 195 100 17 17 289 -1 unnamed_device 25.3 MiB 0.25 1091 17268 5141 9536 2591 64.1 MiB 0.13 0.00 4.75546 -148.32 -4.75546 4.75546 0.98 0.000234527 0.000184907 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0.05 -1 -1 33752 -1 -1 37 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65512 31 32 326 261 1 177 100 17 17 289 -1 unnamed_device 25.0 MiB 0.15 1008 6132 1183 4581 368 64.0 MiB 0.06 0.00 4.78944 -127.311 -4.78944 4.78944 0.95 0.000208465 0.000165707 0.00769296 0.00640021 -1 -1 -1 -1 26 2494 22 6.64007e+06 464646 477104. 1650.88 1.17 0.0580782 0.050279 21682 110474 -1 2169 20 1399 2498 165534 38412 3.93603 3.93603 -128.563 -3.93603 0 0 585099. 2024.56 0.35 0.06 0.11 -1 -1 0.35 0.0154133 0.0136646 129 33 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 5.34 vpr 63.46 MiB -1 -1 0.22 21368 1 0.04 -1 -1 33864 -1 -1 22 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64988 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.7 MiB 0.35 764 14303 4579 7529 2195 63.5 MiB 0.10 0.00 4.38281 -116.371 -4.38281 4.38281 1.05 0.000167696 0.000132554 0.0160852 0.0129068 -1 -1 -1 -1 28 2083 19 6.64007e+06 276276 500653. 1732.36 1.20 0.071621 0.0616544 21970 115934 -1 1681 20 1101 1443 96185 22508 3.23483 3.23483 -107.841 -3.23483 0 0 612192. 2118.31 0.26 0.04 0.12 -1 -1 0.26 0.0117702 0.0103844 109 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 5.19 vpr 63.41 MiB -1 -1 0.29 21540 1 0.05 -1 -1 34048 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64936 32 32 278 238 1 149 81 17 17 289 -1 unnamed_device 24.8 MiB 0.17 868 10406 2691 6847 868 63.4 MiB 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65736 31 32 396 325 1 183 95 17 17 289 -1 unnamed_device 25.4 MiB 0.32 974 12839 3425 8126 1288 64.2 MiB 0.10 0.00 4.34696 -135.951 -4.34696 4.34696 1.06 0.000228512 0.00018017 0.0161538 0.0130422 -1 -1 -1 -1 32 2188 19 6.64007e+06 401856 554710. 1919.41 0.95 0.0580896 0.0484063 22834 132086 -1 1958 21 1309 1812 123981 28855 3.33103 3.33103 -127.587 -3.33103 0 0 701300. 2426.64 0.35 0.05 0.13 -1 -1 0.35 0.0177756 0.0157005 138 91 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 5.16 vpr 63.85 MiB -1 -1 0.20 21480 1 0.04 -1 -1 33688 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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0.04 -1 -1 34104 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 393 312 1 213 88 17 17 289 -1 unnamed_device 25.2 MiB 0.43 846 9643 2135 6651 857 64.2 MiB 0.10 0.00 5.52409 -167.953 -5.52409 5.52409 1.02 0.000238583 0.000188463 0.0151312 0.0123654 -1 -1 -1 -1 34 2787 38 6.64007e+06 301392 585099. 2024.56 2.18 0.118619 0.100601 23122 138558 -1 1936 24 1573 2308 150807 38792 4.46809 4.46809 -156.232 -4.46809 0 0 742403. 2568.87 0.30 0.06 0.13 -1 -1 0.30 0.0185594 0.0162769 154 65 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 5.01 vpr 63.35 MiB -1 -1 0.27 21184 1 0.05 -1 -1 33660 -1 -1 18 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64872 31 32 229 197 1 138 81 17 17 289 -1 unnamed_device 24.9 MiB 0.18 599 7956 1801 5879 276 63.4 MiB 0.06 0.00 3.65226 -97.6941 -3.65226 3.65226 0.97 0.000190565 0.000150085 0.00942531 0.00774206 -1 -1 -1 -1 32 1638 19 6.64007e+06 226044 554710. 1919.41 0.96 0.0388896 0.0328137 22834 132086 -1 1460 18 787 1272 92647 21532 2.73697 2.73697 -94.3223 -2.73697 0 0 701300. 2426.64 0.36 0.04 0.14 -1 -1 0.36 0.0118549 0.0104435 96 4 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 5.43 vpr 64.33 MiB -1 -1 0.24 21600 1 0.04 -1 -1 33936 -1 -1 34 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 412 334 1 190 98 17 17 289 -1 unnamed_device 25.3 MiB 0.22 954 8873 1826 6622 425 64.3 MiB 0.08 0.00 4.24713 -140.193 -4.24713 4.24713 1.05 0.00023769 0.000187586 0.0117671 0.00955573 -1 -1 -1 -1 28 2572 31 6.64007e+06 426972 500653. 1732.36 1.22 0.0680236 0.0576681 21970 115934 -1 2175 22 1537 2339 173372 39376 3.93503 3.93503 -141.075 -3.93503 0 0 612192. 2118.31 0.36 0.08 0.15 -1 -1 0.36 0.0222961 0.0195268 145 90 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 5.14 vpr 63.83 MiB -1 -1 0.22 21560 1 0.04 -1 -1 33952 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65360 32 32 376 318 1 155 81 17 17 289 -1 unnamed_device 25.0 MiB 0.33 874 12856 4533 6666 1657 63.8 MiB 0.09 0.00 3.54047 -123.335 -3.54047 3.54047 1.01 0.000213253 0.000167159 0.0183628 0.0147903 -1 -1 -1 -1 32 1825 21 6.64007e+06 213486 554710. 1919.41 0.96 0.0594558 0.0495771 22834 132086 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65132 30 32 224 207 1 137 80 17 17 289 -1 unnamed_device 25.1 MiB 0.26 724 10744 2740 6987 1017 63.6 MiB 0.06 0.00 3.31307 -103.05 -3.31307 3.31307 1.04 0.000147902 0.000116257 0.0110141 0.00883102 -1 -1 -1 -1 32 1572 19 6.64007e+06 226044 554710. 1919.41 0.97 0.0409312 0.0340667 22834 132086 -1 1483 13 658 840 62111 14307 2.32491 2.32491 -94.088 -2.32491 0 0 701300. 2426.64 0.34 0.03 0.14 -1 -1 0.34 0.00919577 0.00818263 87 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 4.91 vpr 63.53 MiB -1 -1 0.33 21556 1 0.04 -1 -1 33684 -1 -1 16 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65052 30 32 286 239 1 134 78 17 17 289 -1 unnamed_device 24.8 MiB 0.11 653 10370 2942 6125 1303 63.5 MiB 0.07 0.00 4.12598 -117.274 -4.12598 4.12598 0.99 0.000203431 0.000163226 0.0139423 0.0113538 -1 -1 -1 -1 26 1686 20 6.64007e+06 200928 477104. 1650.88 0.98 0.0549514 0.0463637 21682 110474 -1 1476 18 837 1320 110296 24299 2.92297 2.92297 -108.566 -2.92297 0 0 585099. 2024.56 0.25 0.04 0.11 -1 -1 0.25 0.012556 0.0111293 92 34 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 5.01 vpr 62.90 MiB -1 -1 0.24 21556 1 0.03 -1 -1 33696 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64408 32 32 296 247 1 157 85 17 17 289 -1 unnamed_device 24.4 MiB 0.12 882 10687 2740 7287 660 62.9 MiB 0.08 0.00 3.50309 -113.66 -3.50309 3.50309 1.06 0.000193155 0.000153084 0.0131685 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1 0.06 -1 -1 34132 -1 -1 35 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65764 31 32 409 331 1 191 98 17 17 289 -1 unnamed_device 25.3 MiB 0.24 961 9998 2423 6940 635 64.2 MiB 0.09 0.00 4.49598 -142.588 -4.49598 4.49598 0.95 0.000241488 0.000191424 0.0138518 0.0113675 -1 -1 -1 -1 32 2313 19 6.64007e+06 439530 554710. 1919.41 0.95 0.0547129 0.0455445 22834 132086 -1 1958 17 1274 1962 116698 27985 3.33083 3.33083 -125.991 -3.33083 0 0 701300. 2426.64 0.34 0.05 0.16 -1 -1 0.34 0.0161459 0.0142364 143 90 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 5.29 vpr 64.05 MiB -1 -1 0.23 21492 1 0.06 -1 -1 33880 -1 -1 30 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 32 32 354 285 1 202 94 17 17 289 -1 unnamed_device 25.2 MiB 0.57 1143 17347 5477 9563 2307 64.1 MiB 0.14 0.00 5.20258 -155.488 -5.20258 5.20258 0.96 0.000274734 0.000221509 0.0207637 0.0168695 -1 -1 -1 -1 28 2696 21 6.65987e+06 380340 500653. 1732.36 1.00 0.0626627 0.0526058 21970 115934 -1 2338 20 1526 2351 162828 36705 4.16677 4.16677 -147.593 -4.16677 0 0 612192. 2118.31 0.31 0.06 0.11 -1 -1 0.31 0.0170185 0.0151521 152 50 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 5.43 vpr 64.19 MiB -1 -1 0.27 21612 1 0.06 -1 -1 33908 -1 -1 24 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65728 30 32 363 293 1 196 86 17 17 289 -1 unnamed_device 25.3 MiB 0.41 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554710. 1919.41 1.14 0.0744293 0.0627948 22834 132086 -1 2143 21 1316 1863 128998 30148 3.48731 3.48731 -116.645 -3.48731 0 0 701300. 2426.64 0.30 0.05 0.13 -1 -1 0.30 0.0139163 0.0123224 126 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 5.42 vpr 63.67 MiB -1 -1 0.26 21548 1 0.04 -1 -1 33992 -1 -1 27 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65196 29 32 308 248 1 169 88 17 17 289 -1 unnamed_device 25.0 MiB 0.21 937 15298 4951 7764 2583 63.7 MiB 0.12 0.00 4.29337 -115.569 -4.29337 4.29337 1.03 0.00019685 0.000155796 0.020236 0.016536 -1 -1 -1 -1 32 2306 30 6.65987e+06 342306 554710. 1919.41 1.05 0.066181 0.0558676 22834 132086 -1 1985 25 1504 2799 219919 50220 3.42411 3.42411 -111.097 -3.42411 0 0 701300. 2426.64 0.42 0.07 0.13 -1 -1 0.42 0.0157669 0.0138077 126 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 5.57 vpr 63.96 MiB -1 -1 0.20 21524 1 0.05 -1 -1 33920 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65496 32 32 336 268 1 174 87 17 17 289 -1 unnamed_device 25.3 MiB 0.21 1058 13911 3755 8078 2078 64.0 MiB 0.13 0.00 4.32255 -126.417 -4.32255 4.32255 1.04 0.000210081 0.000166405 0.0204754 0.0167115 -1 -1 -1 -1 32 2541 47 6.65987e+06 291594 554710. 1919.41 1.40 0.0922247 0.0790323 22834 132086 -1 2322 23 1597 3125 272365 58938 3.64831 3.64831 -124.147 -3.64831 0 0 701300. 2426.64 0.35 0.09 0.13 -1 -1 0.35 0.0212871 0.018745 130 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 5.47 vpr 63.91 MiB -1 -1 0.31 21560 1 0.04 -1 -1 34076 -1 -1 33 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65444 32 32 366 295 1 189 97 17 17 289 -1 unnamed_device 25.0 MiB 0.33 858 7201 1481 5496 224 63.9 MiB 0.08 0.00 3.30984 -111.675 -3.30984 3.30984 1.06 0.000223118 0.000177228 0.0107146 0.0089289 -1 -1 -1 -1 28 2339 24 6.65987e+06 418374 500653. 1732.36 1.22 0.0591409 0.0501912 21970 115934 -1 2009 20 1311 2041 126370 33362 3.01731 3.01731 -111.009 -3.01731 0 0 612192. 2118.31 0.28 0.06 0.12 -1 -1 0.28 0.0174678 0.0151561 141 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 4.87 vpr 63.41 MiB -1 -1 0.21 21468 1 0.04 -1 -1 34072 -1 -1 18 27 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64932 27 32 259 221 1 130 77 17 17 289 -1 unnamed_device 24.8 MiB 0.16 601 11976 3191 7496 1289 63.4 MiB 0.09 0.00 3.61795 -96.0414 -3.61795 3.61795 1.09 0.000190844 0.000151325 0.0183522 0.0149355 -1 -1 -1 -1 28 1542 20 6.65987e+06 228204 500653. 1732.36 0.96 0.0564805 0.0476777 21970 115934 -1 1408 20 793 1327 101908 22870 2.80071 2.80071 -94.1372 -2.80071 0 0 612192. 2118.31 0.31 0.05 0.12 -1 -1 0.31 0.014874 0.0130699 94 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 5.12 vpr 63.51 MiB -1 -1 0.21 21384 1 0.04 -1 -1 33700 -1 -1 31 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65032 31 32 271 219 1 162 94 17 17 289 -1 unnamed_device 24.9 MiB 0.19 811 9892 2186 7284 422 63.5 MiB 0.07 0.00 3.36433 -96.8901 -3.36433 3.36433 0.94 0.000201284 0.000160345 0.0108992 0.00878783 -1 -1 -1 -1 28 2347 24 6.65987e+06 393018 500653. 1732.36 1.38 0.057181 0.0486882 21970 115934 -1 1905 19 1011 1801 131698 30370 2.71485 2.71485 -95.6397 -2.71485 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.0128759 0.0113856 115 4 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 5.30 vpr 63.75 MiB -1 -1 0.35 21472 1 0.05 -1 -1 33836 -1 -1 19 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65276 31 32 317 271 1 169 82 17 17 289 -1 unnamed_device 24.9 MiB 0.29 927 8804 2219 5962 623 63.7 MiB 0.07 0.00 3.4209 -115.766 -3.4209 3.4209 1.00 0.000214778 0.000172015 0.0123141 0.0100703 -1 -1 -1 -1 30 1946 21 6.65987e+06 240882 526063. 1820.29 1.00 0.0534342 0.0450337 22546 126617 -1 1679 22 876 1290 75993 17565 2.91031 2.91031 -109.66 -2.91031 0 0 666494. 2306.21 0.36 0.05 0.18 -1 -1 0.36 0.0170021 0.0147864 112 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 4.97 vpr 63.37 MiB -1 -1 0.19 21528 1 0.04 -1 -1 33820 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64892 32 32 298 248 1 156 81 17 17 289 -1 unnamed_device 24.9 MiB 0.42 719 10056 2390 7132 534 63.4 MiB 0.08 0.00 3.74029 -120.95 -3.74029 3.74029 0.94 0.000201688 0.000160176 0.0136315 0.0110771 -1 -1 -1 -1 28 2074 23 6.65987e+06 215526 500653. 1732.36 1.08 0.0640771 0.0541029 21970 115934 -1 1782 18 1142 1764 119209 29314 2.82871 2.82871 -113.841 -2.82871 0 0 612192. 2118.31 0.33 0.07 0.11 -1 -1 0.33 0.0185251 0.0165222 113 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 5.28 vpr 63.60 MiB -1 -1 0.32 21348 1 0.03 -1 -1 34136 -1 -1 17 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65124 30 32 303 262 1 139 79 17 17 289 -1 unnamed_device 24.9 MiB 0.37 575 5994 1238 4012 744 63.6 MiB 0.05 0.00 4.00989 -106.137 -4.00989 4.00989 1.03 0.00023233 0.000188038 0.00914136 0.00751987 -1 -1 -1 -1 32 1593 22 6.65987e+06 215526 554710. 1919.41 0.99 0.0500588 0.0421829 22834 132086 -1 1313 15 696 1067 62289 16243 2.70271 2.70271 -97.1718 -2.70271 0 0 701300. 2426.64 0.34 0.04 0.14 -1 -1 0.34 0.0128956 0.0114825 98 63 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 5.60 vpr 63.57 MiB -1 -1 0.20 21680 1 0.05 -1 -1 33864 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65092 32 32 276 237 1 166 81 17 17 289 -1 unnamed_device 25.0 MiB 0.33 795 6381 1346 4871 164 63.6 MiB 0.06 0.00 3.75729 -117.97 -3.75729 3.75729 1.01 0.000187526 0.000147758 0.00908277 0.00752482 -1 -1 -1 -1 28 2308 31 6.65987e+06 215526 500653. 1732.36 1.45 0.0735359 0.064043 21970 115934 -1 1893 16 1083 1444 121416 28692 2.92331 2.92331 -107.84 -2.92331 0 0 612192. 2118.31 0.31 0.05 0.21 -1 -1 0.31 0.0120498 0.0107571 106 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 5.64 vpr 64.14 MiB -1 -1 0.21 21512 1 0.05 -1 -1 33976 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 344 272 1 202 88 17 17 289 -1 unnamed_device 25.2 MiB 0.50 1032 9253 2342 6405 506 64.1 MiB 0.09 0.00 4.35378 -139.852 -4.35378 4.35378 0.98 0.000223018 0.000177097 0.0139518 0.0115179 -1 -1 -1 -1 32 2591 17 6.65987e+06 304272 554710. 1919.41 1.18 0.0658643 0.0565817 22834 132086 -1 2306 24 1781 2644 208357 48038 3.49111 3.49111 -130.916 -3.49111 0 0 701300. 2426.64 0.43 0.08 0.15 -1 -1 0.43 0.0206307 0.0181532 139 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 5.19 vpr 64.05 MiB -1 -1 0.21 21536 1 0.04 -1 -1 34092 -1 -1 30 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 32 32 363 295 1 181 94 17 17 289 -1 unnamed_device 25.2 MiB 0.28 904 11170 2626 8078 466 64.1 MiB 0.09 0.00 4.4708 -131.273 -4.4708 4.4708 1.04 0.000219459 0.000173615 0.014438 0.0117766 -1 -1 -1 -1 28 2436 21 6.65987e+06 380340 500653. 1732.36 1.11 0.0637349 0.0540783 21970 115934 -1 2247 23 1751 2879 209966 48329 3.76071 3.76071 -132.119 -3.76071 0 0 612192. 2118.31 0.28 0.08 0.12 -1 -1 0.28 0.019816 0.0175394 133 61 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 5.40 vpr 63.37 MiB -1 -1 0.27 21100 1 0.03 -1 -1 33528 -1 -1 21 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64888 29 32 248 215 1 137 82 17 17 289 -1 unnamed_device 24.8 MiB 0.37 775 11118 2644 7385 1089 63.4 MiB 0.07 0.00 3.16393 -91.7211 -3.16393 3.16393 1.00 0.000181808 0.000145431 0.012512 0.0101952 -1 -1 -1 -1 26 1874 19 6.65987e+06 266238 477104. 1650.88 1.04 0.0572575 0.0491675 21682 110474 -1 1569 19 924 1516 104371 25434 2.84691 2.84691 -93.5767 -2.84691 0 0 585099. 2024.56 0.29 0.05 0.11 -1 -1 0.29 0.0145335 0.012816 98 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 5.78 vpr 63.87 MiB -1 -1 0.24 21272 1 0.04 -1 -1 34148 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65404 32 32 370 297 1 183 85 17 17 289 -1 unnamed_device 25.1 MiB 0.59 1049 12733 3859 6982 1892 63.9 MiB 0.11 0.00 4.04739 -126.772 -4.04739 4.04739 1.05 0.000236508 0.000188286 0.0200991 0.0164663 -1 -1 -1 -1 32 2511 22 6.65987e+06 266238 554710. 1919.41 1.43 0.0852414 0.0732998 22834 132086 -1 2238 23 1445 2718 191051 43605 3.35377 3.35377 -121.168 -3.35377 0 0 701300. 2426.64 0.33 0.07 0.13 -1 -1 0.33 0.0198299 0.0174322 132 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 5.50 vpr 63.91 MiB -1 -1 0.21 21504 1 0.04 -1 -1 33684 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65448 32 32 338 269 1 196 85 17 17 289 -1 unnamed_device 25.1 MiB 0.40 1072 15523 5016 8339 2168 63.9 MiB 0.12 0.00 4.31458 -139.763 -4.31458 4.31458 0.91 0.000213337 0.000169806 0.0220797 0.01809 -1 -1 -1 -1 28 2915 21 6.65987e+06 266238 500653. 1732.36 1.25 0.0794588 0.0684275 21970 115934 -1 2316 19 1401 1989 160493 35788 3.26677 3.26677 -127.853 -3.26677 0 0 612192. 2118.31 0.33 0.07 0.15 -1 -1 0.33 0.0193526 0.0173998 137 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 5.20 vpr 63.85 MiB -1 -1 0.22 21428 1 0.04 -1 -1 33612 -1 -1 29 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65380 32 32 323 276 1 153 93 17 17 289 -1 unnamed_device 25.0 MiB 0.28 861 11433 2956 7633 844 63.8 MiB 0.08 0.00 2.85064 -102.994 -2.85064 2.85064 0.93 0.000233087 0.000188016 0.0140473 0.0114104 -1 -1 -1 -1 26 2153 22 6.65987e+06 367662 477104. 1650.88 1.11 0.0647541 0.0554807 21682 110474 -1 1816 19 977 1497 110865 25449 2.14751 2.14751 -97.7734 -2.14751 0 0 585099. 2024.56 0.32 0.05 0.13 -1 -1 0.32 0.0170404 0.0151823 110 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 4.52 vpr 63.00 MiB -1 -1 0.19 21216 1 0.04 -1 -1 33620 -1 -1 15 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64512 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 24.4 MiB 0.11 640 7086 1644 4840 602 63.0 MiB 0.04 0.00 2.24807 -77.7472 -2.24807 2.24807 0.90 0.000146079 0.000114661 0.00814634 0.0066777 -1 -1 -1 -1 32 1491 20 6.65987e+06 190170 554710. 1919.41 0.90 0.0334735 0.0280832 22834 132086 -1 1296 14 579 811 59607 14185 1.89185 1.89185 -79.7993 -1.89185 0 0 701300. 2426.64 0.38 0.05 0.14 -1 -1 0.38 0.0137347 0.0123977 81 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 5.64 vpr 63.55 MiB -1 -1 0.19 21416 1 0.04 -1 -1 33956 -1 -1 19 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65080 31 32 291 243 1 171 82 17 17 289 -1 unnamed_device 25.0 MiB 0.74 819 13254 3680 8313 1261 63.6 MiB 0.09 0.00 4.81074 -140.485 -4.81074 4.81074 0.98 0.000182772 0.000143938 0.0156644 0.0126589 -1 -1 -1 -1 28 2127 22 6.65987e+06 240882 500653. 1732.36 0.98 0.0553489 0.0466088 21970 115934 -1 1797 18 1099 1584 108008 26189 3.47917 3.47917 -126.534 -3.47917 0 0 612192. 2118.31 0.41 0.06 0.14 -1 -1 0.41 0.0166378 0.0149701 127 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 5.75 vpr 63.93 MiB -1 -1 0.19 21608 1 0.04 -1 -1 33928 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65468 32 32 342 271 1 179 95 17 17 289 -1 unnamed_device 25.1 MiB 0.32 945 6791 1317 5158 316 63.9 MiB 0.07 0.00 4.14893 -130.493 -4.14893 4.14893 1.03 0.000229934 0.000183929 0.0102179 0.00839391 -1 -1 -1 -1 30 2169 21 6.65987e+06 393018 526063. 1820.29 0.99 0.0537387 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65056 32 32 285 227 1 165 85 17 17 289 -1 unnamed_device 25.0 MiB 0.26 1008 10873 2978 7123 772 63.5 MiB 0.08 0.00 4.661 -123.259 -4.661 4.661 1.08 0.000200696 0.000161014 0.0134188 0.0110138 -1 -1 -1 -1 28 2311 31 6.65987e+06 266238 500653. 1732.36 1.01 0.0547584 0.0463224 21970 115934 -1 2059 21 1264 2355 164435 38396 3.79397 3.79397 -121.606 -3.79397 0 0 612192. 2118.31 0.27 0.05 0.11 -1 -1 0.27 0.0142969 0.0126592 118 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 4.86 vpr 62.88 MiB -1 -1 0.17 21108 1 0.04 -1 -1 33504 -1 -1 14 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64384 32 32 173 169 1 116 78 17 17 289 -1 unnamed_device 24.4 MiB 0.10 415 10370 2863 4808 2699 62.9 MiB 0.05 0.00 2.54569 -72.1104 -2.54569 2.54569 1.01 0.000130829 0.000101365 0.0105454 0.00855625 -1 -1 -1 -1 30 1192 29 6.65987e+06 177492 526063. 1820.29 0.97 0.0395417 0.0332815 22546 126617 -1 819 15 404 445 27960 7884 1.81985 1.81985 -66.7912 -1.81985 0 0 666494. 2306.21 0.30 0.03 0.12 -1 -1 0.30 0.00871213 0.00788207 79 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 5.21 vpr 63.51 MiB -1 -1 0.19 21476 1 0.03 -1 -1 33812 -1 -1 30 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65036 32 32 300 245 1 165 94 17 17 289 -1 unnamed_device 24.9 MiB 0.18 867 9679 2178 7022 479 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0.0486652 22546 126617 -1 1950 19 961 1748 104695 23724 2.60951 2.60951 -101.656 -2.60951 0 0 666494. 2306.21 0.30 0.05 0.14 -1 -1 0.30 0.0144722 0.0127854 128 3 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 5.09 vpr 63.92 MiB -1 -1 0.21 21484 1 0.03 -1 -1 33864 -1 -1 26 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65456 32 32 338 277 1 179 90 17 17 289 -1 unnamed_device 24.8 MiB 0.29 1026 15366 4954 8031 2381 63.9 MiB 0.14 0.00 4.40163 -128.768 -4.40163 4.40163 1.03 0.000263784 0.000190982 0.0218191 0.017596 -1 -1 -1 -1 28 2536 22 6.65987e+06 329628 500653. 1732.36 1.17 0.0701533 0.0586005 21970 115934 -1 2239 29 1748 3059 300303 101990 3.99999 3.99999 -130.531 -3.99999 0 0 612192. 2118.31 0.28 0.10 0.12 -1 -1 0.28 0.0213118 0.0184515 125 50 -1 -1 -1 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64932 30 32 262 227 1 135 85 17 17 289 -1 unnamed_device 24.7 MiB 0.14 765 12733 3276 8152 1305 63.4 MiB 0.07 0.00 2.99867 -95.3722 -2.99867 2.99867 1.04 0.00016599 0.00013095 0.013425 0.0108516 -1 -1 -1 -1 32 1733 17 6.65987e+06 291594 554710. 1919.41 1.01 0.045989 0.0387781 22834 132086 -1 1567 19 957 1467 111882 25763 2.66145 2.66145 -94.3977 -2.66145 0 0 701300. 2426.64 0.30 0.05 0.14 -1 -1 0.30 0.0130256 0.0115622 97 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 4.70 vpr 63.15 MiB -1 -1 0.22 21624 1 0.04 -1 -1 33856 -1 -1 23 28 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64668 28 32 260 223 1 140 83 17 17 289 -1 unnamed_device 24.5 MiB 0.15 635 14123 3811 8579 1733 63.2 MiB 0.09 0.00 3.31478 -92.4847 -3.31478 3.31478 0.99 0.00018014 0.000143849 0.0166834 0.0135061 -1 -1 -1 -1 28 1810 27 6.65987e+06 291594 500653. 1732.36 0.92 0.0506914 0.0419816 21970 115934 -1 1551 19 950 1652 120534 27810 2.73271 2.73271 -92.4594 -2.73271 0 0 612192. 2118.31 0.31 0.07 0.11 -1 -1 0.31 0.0181138 0.0159989 98 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_032.v common 4.86 vpr 63.42 MiB -1 -1 0.30 21160 1 0.04 -1 -1 33892 -1 -1 19 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64940 32 32 253 210 1 154 83 17 17 289 -1 unnamed_device 24.7 MiB 0.17 727 6383 1361 4583 439 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65392 32 32 391 311 1 192 100 17 17 289 -1 unnamed_device 25.0 MiB 0.34 918 16804 4626 9521 2657 63.9 MiB 0.14 0.00 3.76954 -123.355 -3.76954 3.76954 1.19 0.000353965 0.000284297 0.0242504 0.0197085 -1 -1 -1 -1 26 2803 43 6.65987e+06 456408 477104. 1650.88 1.57 0.103704 0.0874397 21682 110474 -1 2202 22 1787 2772 200753 48070 3.09111 3.09111 -121.86 -3.09111 0 0 585099. 2024.56 0.32 0.07 0.12 -1 -1 0.32 0.0184838 0.0162755 146 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 5.42 vpr 62.53 MiB -1 -1 0.20 21396 1 0.04 -1 -1 33556 -1 -1 17 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64032 31 32 279 237 1 161 80 17 17 289 -1 unnamed_device 24.1 MiB 0.63 795 7304 1575 5379 350 62.5 MiB 0.06 0.00 4.09732 -119.878 -4.09732 4.09732 1.02 0.000176779 0.000139104 0.00970252 0.00795085 -1 -1 -1 -1 28 2295 28 6.65987e+06 215526 500653. 1732.36 1.18 0.050986 0.0435131 21970 115934 -1 1888 21 1171 1638 142248 31897 2.88337 2.88337 -109.949 -2.88337 0 0 612192. 2118.31 0.26 0.05 0.11 -1 -1 0.26 0.0131063 0.0115533 109 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 5.20 vpr 63.11 MiB -1 -1 0.22 21396 1 0.04 -1 -1 33880 -1 -1 24 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64624 31 32 370 297 1 186 87 17 17 289 -1 unnamed_device 24.2 MiB 0.42 944 8727 2152 5844 731 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65252 32 32 291 242 1 179 86 17 17 289 -1 unnamed_device 25.1 MiB 0.29 922 8780 2172 6205 403 63.7 MiB 0.07 0.00 4.1266 -111.615 -4.1266 4.1266 1.05 0.000186119 0.000147103 0.0106879 0.0087129 -1 -1 -1 -1 26 2735 26 6.65987e+06 278916 477104. 1650.88 1.78 0.0605723 0.0514452 21682 110474 -1 2172 23 1525 2279 180283 42061 3.61865 3.61865 -116.354 -3.61865 0 0 585099. 2024.56 0.29 0.08 0.11 -1 -1 0.29 0.0218666 0.0195236 118 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 5.94 vpr 64.18 MiB -1 -1 0.25 21800 1 0.06 -1 -1 34148 -1 -1 38 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65720 32 32 457 356 1 223 102 17 17 289 -1 unnamed_device 25.8 MiB 0.46 1225 11764 2792 7889 1083 64.2 MiB 0.11 0.00 4.86514 -158.575 -4.86514 4.86514 1.22 0.000285867 0.000229446 0.0163593 0.0133778 -1 -1 -1 -1 28 3027 30 6.65987e+06 481764 500653. 1732.36 1.36 0.0918822 0.078505 21970 115934 -1 2643 23 1724 2712 187683 42451 3.79291 3.79291 -146.352 -3.79291 0 0 612192. 2118.31 0.29 0.08 0.12 -1 -1 0.29 0.0240298 0.0213049 172 87 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 4.83 vpr 63.30 MiB -1 -1 0.30 21576 1 0.03 -1 -1 33508 -1 -1 21 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64816 31 32 261 225 1 142 84 17 17 289 -1 unnamed_device 24.7 MiB 0.27 792 5391 1113 3866 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 353 287 1 198 86 17 17 289 -1 unnamed_device 25.1 MiB 0.45 1090 7835 1660 5643 532 64.0 MiB 0.08 0.00 4.46734 -132.214 -4.46734 4.46734 1.02 0.000205159 0.000162705 0.0134293 0.0109819 -1 -1 -1 -1 32 2503 28 6.65987e+06 278916 554710. 1919.41 1.03 0.0651839 0.0554538 22834 132086 -1 2254 16 1127 1532 112414 26836 3.20591 3.20591 -119.029 -3.20591 0 0 701300. 2426.64 0.32 0.05 0.18 -1 -1 0.32 0.0148755 0.0131789 136 55 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 6.32 vpr 63.97 MiB -1 -1 0.22 21632 1 0.04 -1 -1 33812 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 32 32 361 291 1 185 95 17 17 289 -1 unnamed_device 25.1 MiB 0.63 1025 8951 2023 6429 499 64.0 MiB 0.08 0.00 3.78594 -122.94 -3.78594 3.78594 1.09 0.000231515 0.000185545 0.0124475 0.010335 -1 -1 -1 -1 26 2851 30 6.65987e+06 393018 477104. 1650.88 1.84 0.0906537 0.077767 21682 110474 -1 2246 22 1338 2263 183303 40174 3.11131 3.11131 -122.127 -3.11131 0 0 585099. 2024.56 0.26 0.06 0.11 -1 -1 0.26 0.0167684 0.014701 132 55 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 5.55 vpr 64.07 MiB -1 -1 0.37 21548 1 0.06 -1 -1 33916 -1 -1 36 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65604 32 32 382 305 1 192 100 17 17 289 -1 unnamed_device 25.2 MiB 0.49 1095 17268 5091 9567 2610 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65568 32 32 387 315 1 189 85 17 17 289 -1 unnamed_device 25.2 MiB 0.35 901 8269 1876 5929 464 64.0 MiB 0.08 0.00 3.98149 -123.442 -3.98149 3.98149 0.95 0.000220892 0.000174602 0.0127458 0.0104703 -1 -1 -1 -1 32 2648 25 6.65987e+06 266238 554710. 1919.41 1.09 0.065438 0.0555498 22834 132086 -1 2151 21 1523 2669 176931 42791 3.46425 3.46425 -121.172 -3.46425 0 0 701300. 2426.64 0.32 0.06 0.14 -1 -1 0.32 0.0182481 0.0160657 135 77 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 4.96 vpr 63.25 MiB -1 -1 0.19 21124 1 0.04 -1 -1 33752 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65500 29 32 355 287 1 198 85 17 17 289 -1 unnamed_device 25.1 MiB 0.38 1014 15523 4859 8256 2408 64.0 MiB 0.12 0.00 4.24664 -124.159 -4.24664 4.24664 1.19 0.000216157 0.000172503 0.0207212 0.0168393 -1 -1 -1 -1 32 2519 21 6.65987e+06 304272 554710. 1919.41 0.96 0.0610155 0.051077 22834 132086 -1 2110 26 1456 2226 166870 38789 3.18497 3.18497 -112.254 -3.18497 0 0 701300. 2426.64 0.46 0.11 0.13 -1 -1 0.46 0.0333136 0.0293483 138 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 5.90 vpr 63.97 MiB -1 -1 0.21 21492 1 0.04 -1 -1 33852 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 32 32 358 289 1 175 88 17 17 289 -1 unnamed_device 25.2 MiB 0.30 813 6133 1250 4669 214 64.0 MiB 0.06 0.00 4.31499 -129.627 -4.31499 4.31499 1.23 0.000269975 0.000223102 0.0112372 0.00940652 -1 -1 -1 -1 30 1973 21 6.65987e+06 304272 526063. 1820.29 1.33 0.0794649 0.0682408 22546 126617 -1 1695 21 1155 1730 101267 23759 3.45917 3.45917 -120.941 -3.45917 0 0 666494. 2306.21 0.30 0.04 0.12 -1 -1 0.30 0.0154706 0.0136382 130 54 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 5.96 vpr 63.91 MiB -1 -1 0.20 21496 1 0.03 -1 -1 34036 -1 -1 27 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65440 32 32 353 285 1 181 91 17 17 289 -1 unnamed_device 25.1 MiB 0.33 1032 14575 3712 8961 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64932 28 32 277 229 1 155 95 17 17 289 -1 unnamed_device 24.9 MiB 0.25 923 12623 3487 7239 1897 63.4 MiB 0.14 0.00 4.05815 -100.085 -4.05815 4.05815 1.17 0.000282317 0.000225409 0.0206415 0.0168795 -1 -1 -1 -1 26 2151 41 6.65987e+06 443730 477104. 1650.88 1.29 0.0900948 0.0773508 21682 110474 -1 1846 35 1346 2687 324830 124278 3.61745 3.61745 -101.557 -3.61745 0 0 585099. 2024.56 0.25 0.16 0.14 -1 -1 0.25 0.0285601 0.0246591 115 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 5.76 vpr 63.70 MiB -1 -1 0.22 21504 1 0.04 -1 -1 34148 -1 -1 17 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 32 32 387 309 1 190 101 17 17 289 -1 unnamed_device 25.1 MiB 0.35 1091 6681 1303 5078 300 64.1 MiB 0.07 0.00 4.26912 -136.659 -4.26912 4.26912 1.04 0.000233561 0.000185446 0.00919908 0.00760708 -1 -1 -1 -1 28 2817 25 6.65987e+06 469086 500653. 1732.36 1.51 0.0738565 0.0639349 21970 115934 -1 2390 24 1458 2683 207005 46217 3.57931 3.57931 -129.096 -3.57931 0 0 612192. 2118.31 0.37 0.10 0.13 -1 -1 0.37 0.0306445 0.0276156 140 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 5.28 vpr 63.36 MiB -1 -1 0.21 21540 1 0.05 -1 -1 33636 -1 -1 19 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65696 32 32 365 294 1 185 84 17 17 289 -1 unnamed_device 25.4 MiB 0.31 1063 15273 4695 8692 1886 64.2 MiB 0.13 0.00 4.80469 -139.024 -4.80469 4.80469 1.04 0.000241712 0.000191897 0.0245582 0.0201745 -1 -1 -1 -1 32 2629 23 6.65987e+06 253560 554710. 1919.41 1.07 0.0781199 0.0653028 22834 132086 -1 2268 18 1507 2677 195261 43968 3.62631 3.62631 -130.943 -3.62631 0 0 701300. 2426.64 0.31 0.08 0.13 -1 -1 0.31 0.0215693 0.0191503 133 57 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 5.77 vpr 64.05 MiB -1 -1 0.22 21480 1 0.04 -1 -1 33976 -1 -1 29 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 29 32 378 310 1 177 90 17 17 289 -1 unnamed_device 25.2 MiB 0.43 958 9738 2610 6016 1112 64.1 MiB 0.09 0.00 4.45269 -125.734 -4.45269 4.45269 1.03 0.00030591 0.000251282 0.0162077 0.013419 -1 -1 -1 -1 32 2235 18 6.65987e+06 367662 554710. 1919.41 1.00 0.0615563 0.0516706 22834 132086 -1 1952 21 1256 2061 148316 34812 3.04431 3.04431 -110.646 -3.04431 0 0 701300. 2426.64 0.35 0.05 0.14 -1 -1 0.35 0.0163134 0.0143483 131 85 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 4.55 vpr 63.14 MiB -1 -1 0.17 21216 1 0.04 -1 -1 34124 -1 -1 15 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64656 32 32 243 205 1 139 79 17 17 289 -1 unnamed_device 24.7 MiB 0.18 690 12416 3929 6813 1674 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64780 31 32 245 205 1 150 84 17 17 289 -1 unnamed_device 24.6 MiB 0.16 780 8136 2089 5541 506 63.3 MiB 0.06 0.00 3.80235 -109.245 -3.80235 3.80235 1.02 0.000168167 0.000133684 0.0106798 0.00881916 -1 -1 -1 -1 26 2013 29 6.65987e+06 266238 477104. 1650.88 1.03 0.0468666 0.0398 21682 110474 -1 1810 21 1146 1877 153537 34871 3.03417 3.03417 -108.934 -3.03417 0 0 585099. 2024.56 0.33 0.07 0.18 -1 -1 0.33 0.0175115 0.0155868 106 4 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 5.34 vpr 64.10 MiB -1 -1 0.19 21588 1 0.05 -1 -1 34080 -1 -1 25 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65644 32 32 421 327 1 232 90 17 17 289 -1 unnamed_device 25.8 MiB 0.49 1325 16572 5545 8395 2632 64.1 MiB 0.18 0.00 4.13297 -134.503 -4.13297 4.13297 1.11 0.000357775 0.000294214 0.0364056 0.0306597 -1 -1 -1 -1 28 3732 33 6.65987e+06 329628 500653. 1732.36 1.82 0.10995 0.093406 21970 115934 -1 2910 22 2032 3461 269192 58352 3.78985 3.78985 -132.845 -3.78985 0 0 612192. 2118.31 0.27 0.09 0.13 -1 -1 0.27 0.0233614 0.0209297 170 65 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 6.05 vpr 64.05 MiB -1 -1 0.32 21756 1 0.04 -1 -1 34088 -1 -1 21 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 31 32 365 296 1 193 84 17 17 289 -1 unnamed_device 25.2 MiB 1.20 1078 12528 3903 6326 2299 64.1 MiB 0.10 0.00 5.17417 -148.706 -5.17417 5.17417 0.91 0.000224964 0.000178374 0.0185415 0.0150606 -1 -1 -1 -1 32 2682 40 6.65987e+06 266238 554710. 1919.41 1.14 0.0709059 0.0594337 22834 132086 -1 2210 21 1701 2586 216602 47829 4.53217 4.53217 -149.34 -4.53217 0 0 701300. 2426.64 0.32 0.08 0.14 -1 -1 0.32 0.0204275 0.0182516 150 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 6.17 vpr 63.77 MiB -1 -1 0.20 21532 1 0.04 -1 -1 33784 -1 -1 19 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65296 32 32 331 280 1 175 83 17 17 289 -1 unnamed_device 24.9 MiB 1.22 898 12323 4450 5685 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65624 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 25.4 MiB 0.34 1081 14713 4410 8000 2303 64.1 MiB 0.12 0.00 4.85897 -149.763 -4.85897 4.85897 1.12 0.000225065 0.000169391 0.0201529 0.0163419 -1 -1 -1 -1 32 3051 39 6.65987e+06 304272 554710. 1919.41 1.44 0.102627 0.0878269 22834 132086 -1 2442 22 1985 3010 225131 52194 4.07205 4.07205 -141.281 -4.07205 0 0 701300. 2426.64 0.30 0.07 0.13 -1 -1 0.30 0.0177122 0.0156745 147 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 5.61 vpr 63.86 MiB -1 -1 0.29 21768 1 0.05 -1 -1 33724 -1 -1 34 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65388 32 32 386 307 1 195 98 17 17 289 -1 unnamed_device 25.0 MiB 0.51 1057 18773 5404 10789 2580 63.9 MiB 0.15 0.00 4.57498 -141.429 -4.57498 4.57498 1.03 0.000226159 0.000177933 0.0231806 0.0188536 -1 -1 -1 -1 26 2887 23 6.65987e+06 431052 477104. 1650.88 1.21 0.0784627 0.0667168 21682 110474 -1 2397 18 1290 2019 146660 33279 3.71257 3.71257 -132.431 -3.71257 0 0 585099. 2024.56 0.29 0.05 0.11 -1 -1 0.29 0.0157803 0.0140274 143 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 4.95 vpr 63.14 MiB -1 -1 0.19 21484 1 0.04 -1 -1 34080 -1 -1 17 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64656 29 32 269 229 1 130 78 17 17 289 -1 unnamed_device 24.5 MiB 0.21 522 12528 3273 8240 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64744 32 32 278 238 1 149 80 17 17 289 -1 unnamed_device 24.6 MiB 0.24 840 12980 3474 8543 963 63.2 MiB 0.08 0.00 3.73708 -117.005 -3.73708 3.73708 0.97 0.000183186 0.000144283 0.015428 0.0124593 -1 -1 -1 -1 32 2020 18 6.65987e+06 202848 554710. 1919.41 0.99 0.0467346 0.039004 22834 132086 -1 1831 23 1462 2541 202733 45407 2.67845 2.67845 -105.711 -2.67845 0 0 701300. 2426.64 0.29 0.07 0.13 -1 -1 0.29 0.0149316 0.0131229 109 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 5.12 vpr 63.92 MiB -1 -1 0.27 21696 1 0.06 -1 -1 34000 -1 -1 35 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65456 31 32 373 300 1 181 98 17 17 289 -1 unnamed_device 25.1 MiB 0.33 932 18098 5272 9901 2925 63.9 MiB 0.13 0.00 4.00372 -119.439 -4.00372 4.00372 0.94 0.000219055 0.000172289 0.0205669 0.0163462 -1 -1 -1 -1 32 2122 19 6.65987e+06 443730 554710. 1919.41 1.07 0.0637094 0.0524413 22834 132086 -1 1876 20 1378 2071 131991 31106 2.96231 2.96231 -109.45 -2.96231 0 0 701300. 2426.64 0.32 0.05 0.13 -1 -1 0.32 0.016983 0.0148614 135 64 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 4.72 vpr 63.38 MiB -1 -1 0.22 21532 1 0.03 -1 -1 33676 -1 -1 19 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64900 31 32 265 230 1 164 82 17 17 289 -1 unnamed_device 24.8 MiB 0.30 729 5422 1011 4209 202 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65004 32 32 290 244 1 175 83 17 17 289 -1 unnamed_device 24.8 MiB 0.25 794 6203 1260 4522 421 63.5 MiB 0.06 0.00 4.22769 -129.19 -4.22769 4.22769 0.92 0.000192981 0.000153689 0.00893566 0.00737135 -1 -1 -1 -1 28 2478 30 6.65987e+06 240882 500653. 1732.36 1.24 0.0567572 0.0485113 21970 115934 -1 2072 18 1317 1923 149105 37380 3.16031 3.16031 -121.312 -3.16031 0 0 612192. 2118.31 0.39 0.11 0.12 -1 -1 0.39 0.0301283 0.0271604 115 34 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 4.92 vpr 63.86 MiB -1 -1 0.21 21492 1 0.04 -1 -1 33976 -1 -1 22 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65392 32 32 318 257 1 194 86 17 17 289 -1 unnamed_device 24.8 MiB 0.29 982 13505 4715 6575 2215 63.9 MiB 0.10 0.00 4.5425 -135.474 -4.5425 4.5425 0.90 0.000197258 0.000155465 0.0170356 0.0137727 -1 -1 -1 -1 32 2569 24 6.65987e+06 278916 554710. 1919.41 1.01 0.0549614 0.0459936 22834 132086 -1 2078 23 1533 2145 153331 36456 3.62971 3.62971 -124.599 -3.62971 0 0 701300. 2426.64 0.31 0.06 0.13 -1 -1 0.31 0.0183407 0.0162854 130 30 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 5.39 vpr 63.73 MiB -1 -1 0.27 21476 1 0.04 -1 -1 33900 -1 -1 28 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65264 29 32 324 268 1 168 89 17 17 289 -1 unnamed_device 24.8 MiB 0.58 892 10583 2559 7230 794 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65444 32 32 376 318 1 156 80 17 17 289 -1 unnamed_device 25.0 MiB 0.29 838 12464 4352 6338 1774 63.9 MiB 0.10 0.00 3.54047 -123.895 -3.54047 3.54047 1.06 0.000225521 0.000178436 0.0214698 0.0175208 -1 -1 -1 -1 30 1878 23 6.65987e+06 202848 526063. 1820.29 1.03 0.0666966 0.0558 22546 126617 -1 1542 22 1226 1790 98805 26832 2.87877 2.87877 -118.928 -2.87877 0 0 666494. 2306.21 0.28 0.05 0.12 -1 -1 0.28 0.0151246 0.013228 115 96 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 7.34 vpr 63.93 MiB -1 -1 0.24 21640 1 0.06 -1 -1 34008 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65464 32 32 360 293 1 179 95 17 17 289 -1 unnamed_device 25.1 MiB 0.47 983 16079 4676 8844 2559 63.9 MiB 0.24 0.00 4.19332 -128.664 -4.19332 4.19332 1.63 0.000605014 0.000519415 0.0551051 0.047835 -1 -1 -1 -1 32 2255 22 6.65987e+06 393018 554710. 1919.41 1.58 0.123022 0.106452 22834 132086 -1 1913 18 945 1398 91740 22097 3.08831 3.08831 -113.899 -3.08831 0 0 701300. 2426.64 0.30 0.04 0.14 -1 -1 0.30 0.0144483 0.0127817 130 60 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 7.26 vpr 63.84 MiB -1 -1 0.20 21860 1 0.04 -1 -1 34160 -1 -1 25 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65368 32 32 396 299 1 236 89 17 17 289 -1 unnamed_device 25.3 MiB 0.53 1359 11969 3395 7471 1103 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v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64772 25 32 216 194 1 122 84 17 17 289 -1 unnamed_device 24.8 MiB 0.13 451 9966 3308 4450 2208 63.3 MiB 0.05 0.00 3.08755 -72.8894 -3.08755 3.08755 1.13 0.000148394 0.000117353 0.0106207 0.0086907 -1 -1 -1 -1 30 1266 42 6.65987e+06 342306 526063. 1820.29 1.21 0.0578386 0.0493399 22546 126617 -1 972 64 992 2005 378014 232494 3.12459 3.12459 -67.2426 -3.12459 0 0 666494. 2306.21 0.34 0.15 0.13 -1 -1 0.34 0.024016 0.0204472 89 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 5.78 vpr 63.94 MiB -1 -1 0.22 21484 1 0.04 -1 -1 33800 -1 -1 20 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66132 32 32 361 291 1 178 81 17 17 289 -1 unnamed_device 25.8 MiB 2.21 705 10581 4329 5826 426 64.6 MiB 0.07 0.00 3.235 -113.751 -3.235 3.235 1.07 0.000216793 0.000171308 0.0160907 0.0131381 -1 -1 -1 -1 46 2538 36 6.95648e+06 246087 828058. 2865.25 4.67 0.124548 0.10578 28066 200906 -1 1762 22 1596 2486 209871 53513 3.04467 3.04467 -116.161 -3.04467 0 0 1.01997e+06 3529.29 0.39 0.07 0.19 -1 -1 0.39 0.0178396 0.0158144 75 55 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_050.v common 17.69 vpr 64.84 MiB -1 -1 0.25 21476 1 0.03 -1 -1 33904 -1 -1 26 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66392 32 32 382 305 1 184 90 17 17 289 -1 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66108 32 32 387 315 1 183 77 17 17 289 -1 unnamed_device 25.9 MiB 1.70 875 12791 5461 6994 336 64.6 MiB 0.08 0.00 4.05245 -131.841 -4.05245 4.05245 0.92 0.000217618 0.000171367 0.0210095 0.0169789 -1 -1 -1 -1 40 2776 26 6.95648e+06 188184 706193. 2443.58 18.76 0.221147 0.187227 26914 176310 -1 2529 21 1721 2851 323085 71230 4.21512 4.21512 -142.266 -4.21512 0 0 926341. 3205.33 0.36 0.09 0.17 -1 -1 0.36 0.0194288 0.0173179 76 77 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_055.v common 12.67 vpr 63.85 MiB -1 -1 0.18 21260 1 0.04 -1 -1 33728 -1 -1 18 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65384 32 32 251 219 1 136 82 17 17 289 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on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65996 32 32 269 231 1 166 75 17 17 289 -1 unnamed_device 25.6 MiB 2.48 634 12083 4617 6209 1257 64.4 MiB 0.07 0.00 4.05037 -119.139 -4.05037 4.05037 0.96 0.000176467 0.00013924 0.0158701 0.0128694 -1 -1 -1 -1 40 2183 25 6.95648e+06 159232 706193. 2443.58 10.91 0.141175 0.119154 26914 176310 -1 1650 19 1252 1581 138724 32508 3.42592 3.42592 -119.97 -3.42592 0 0 926341. 3205.33 0.38 0.05 0.18 -1 -1 0.38 0.0131789 0.0117197 68 29 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_090.v common 7.33 vpr 64.03 MiB -1 -1 0.20 21200 1 0.04 -1 -1 34100 -1 -1 14 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65568 31 32 245 205 1 145 77 17 17 289 -1 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66264 31 32 373 300 1 174 87 17 17 289 -1 unnamed_device 25.9 MiB 1.28 760 14295 5473 6487 2335 64.7 MiB 0.09 0.00 3.48773 -117.233 -3.48773 3.48773 0.99 0.000248787 0.000200985 0.0201411 0.0162263 -1 -1 -1 -1 38 2353 27 6.95648e+06 347416 678818. 2348.85 2.59 0.0987226 0.0821954 26626 170182 -1 1741 20 1636 2188 161214 36056 3.39887 3.39887 -120.309 -3.39887 0 0 902133. 3121.57 0.40 0.07 0.16 -1 -1 0.40 0.0211996 0.0189943 79 64 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_110.v common 9.89 vpr 64.54 MiB -1 -1 0.23 21448 1 0.04 -1 -1 33604 -1 -1 12 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66084 31 32 265 230 1 159 75 17 17 289 -1 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GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65756 30 32 286 239 1 137 73 17 17 289 -1 unnamed_device 25.7 MiB 2.72 541 7673 3127 4256 290 64.2 MiB 0.04 0.00 3.61654 -109.463 -3.61654 3.61654 0.99 0.000176144 0.000138463 0.01098 0.00894104 -1 -1 -1 -1 36 1999 40 6.95648e+06 159232 648988. 2245.63 3.45 0.0792419 0.0661642 26050 158493 -1 1573 27 1433 2096 285043 86529 3.15927 3.15927 -115.804 -3.15927 0 0 828058. 2865.25 0.31 0.08 0.15 -1 -1 0.31 0.0147408 0.0128056 55 34 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 8.40 vpr 64.14 MiB -1 -1 0.19 21568 1 0.04 -1 -1 33512 -1 -1 10 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 296 247 1 152 74 17 17 289 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 354 285 1 206 79 17 17 289 -1 unnamed_device 25.7 MiB 2.31 851 13599 5123 6301 2175 64.6 MiB 0.09 0.00 5.05471 -146.645 -5.05471 5.05471 1.03 0.000224334 0.000178624 0.0197154 0.0159003 -1 -1 -1 -1 40 2973 50 6.99608e+06 220735 706193. 2443.58 4.02 0.110297 0.0925107 26914 176310 -1 2391 21 1860 2633 243329 56741 4.97901 4.97901 -158.616 -4.97901 0 0 926341. 3205.33 0.36 0.07 0.17 -1 -1 0.36 0.0159987 0.0141671 88 50 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_002.v common 7.61 vpr 64.58 MiB -1 -1 0.22 21520 1 0.05 -1 -1 33684 -1 -1 18 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66128 30 32 363 293 1 224 80 17 17 289 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 370 297 1 222 80 17 17 289 -1 unnamed_device 25.8 MiB 2.25 1140 12464 4408 6591 1465 64.5 MiB 0.09 0.00 3.78769 -130.542 -3.78769 3.78769 0.93 0.000229561 0.000181976 0.019761 0.0160942 -1 -1 -1 -1 42 3336 48 6.99608e+06 235451 744469. 2576.02 2.77 0.106145 0.0888427 27202 183097 -1 2553 23 2137 3282 294346 60400 3.53451 3.53451 -137.204 -3.53451 0 0 949917. 3286.91 0.36 0.09 0.17 -1 -1 0.36 0.0205908 0.0182084 96 58 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_017.v common 8.80 vpr 64.45 MiB -1 -1 0.17 21604 1 0.04 -1 -1 33496 -1 -1 15 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65992 32 32 338 269 1 198 79 17 17 289 -1 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GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65984 32 32 341 285 1 214 79 17 17 289 -1 unnamed_device 25.5 MiB 1.04 872 9036 3191 4723 1122 64.4 MiB 0.06 0.00 3.89113 -140.293 -3.89113 3.89113 0.87 0.000201335 0.00015834 0.0146925 0.0122 -1 -1 -1 -1 44 3087 35 6.99608e+06 220735 787024. 2723.27 3.33 0.0883414 0.0739486 27778 195446 -1 2004 20 1867 2519 222462 45910 3.68341 3.68341 -137.359 -3.68341 0 0 997811. 3452.63 0.36 0.06 0.20 -1 -1 0.36 0.0131524 0.0115286 93 65 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_057.v common 8.74 vpr 65.02 MiB -1 -1 0.20 21804 1 0.04 -1 -1 34108 -1 -1 16 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66580 32 32 387 293 1 226 80 17 17 289 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66132 32 32 350 275 1 202 78 17 17 289 -1 unnamed_device 25.6 MiB 1.38 829 10204 4200 5555 449 64.6 MiB 0.06 0.00 4.50341 -148.643 -4.50341 4.50341 0.91 0.000205857 0.000161727 0.0150649 0.0122181 -1 -1 -1 -1 48 2835 33 6.99608e+06 206020 865456. 2994.66 19.69 0.169073 0.142889 28354 207349 -1 2230 20 1749 2578 220453 49752 4.10901 4.10901 -145.953 -4.10901 0 0 1.05005e+06 3633.38 0.50 0.06 0.19 -1 -1 0.50 0.0160984 0.0143082 86 34 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_077.v common 8.03 vpr 64.67 MiB -1 -1 0.21 21440 1 0.03 -1 -1 34032 -1 -1 17 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 385 308 1 237 81 17 17 289 -1 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66012 32 32 349 286 1 207 79 17 17 289 -1 unnamed_device 25.5 MiB 1.50 1045 14275 6069 7825 381 64.5 MiB 0.09 0.00 3.51899 -121.288 -3.51899 3.51899 0.88 0.000231565 0.000188562 0.0196182 0.0158497 -1 -1 -1 -1 38 2528 20 6.99608e+06 220735 678818. 2348.85 2.37 0.0847683 0.0709587 26626 170182 -1 2176 20 1461 1984 153571 32028 3.28376 3.28376 -123.98 -3.28376 0 0 902133. 3121.57 0.33 0.05 0.15 -1 -1 0.33 0.0141429 0.012478 91 57 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml mult_112.v common 9.05 vpr 64.88 MiB -1 -1 0.22 21784 1 0.03 -1 -1 33892 -1 -1 20 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66440 31 32 396 325 1 254 83 17 17 289 -1 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65288 31 32 291 243 1 178 82 17 17 289 -1 unnamed_device 25.1 MiB 4.81 940 10406 3145 6506 755 63.8 MiB 0.08 0.00 5.00887 -149.776 -5.00887 5.00887 0.86 0.00017477 0.000138479 0.0117171 0.00940101 -1 -1 -1 -1 30 2234 22 6.87369e+06 265503 556674. 1926.21 0.89 0.0415066 0.0342714 25186 138497 -1 1813 18 871 1255 70103 17136 3.44261 3.44261 -132.101 -3.44261 0 0 706193. 2443.58 0.27 0.03 0.12 -1 -1 0.27 0.01055 0.00924348 116 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 5.59 vpr 64.50 MiB -1 -1 0.17 21616 1 0.03 -1 -1 34020 -1 -1 35 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 25.6 MiB 1.32 1070 16515 4276 10581 1658 64.5 MiB 0.11 0.00 4.18253 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64804 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 24.7 MiB 0.87 415 9836 3792 4975 1069 63.3 MiB 0.04 0.00 2.58823 -76.4648 -2.58823 2.58823 0.87 0.000125104 9.7628e-05 0.00884574 0.00709388 -1 -1 -1 -1 34 1145 25 6.87369e+06 167686 618332. 2139.56 1.32 0.0430803 0.0355142 25762 151098 -1 885 16 568 649 42105 11703 1.91852 1.91852 -73.9266 -1.91852 0 0 787024. 2723.27 0.31 0.02 0.14 -1 -1 0.31 0.00643702 0.00563631 65 3 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 5.43 vpr 63.78 MiB -1 -1 0.17 21612 1 0.03 -1 -1 34048 -1 -1 30 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65312 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 25.1 MiB 1.40 1004 15430 3940 9856 1634 63.8 MiB 0.10 0.00 4.64012 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66044 31 32 383 305 1 212 90 17 17 289 -1 unnamed_device 25.8 MiB 5.58 920 11145 2994 7135 1016 64.5 MiB 0.10 0.00 5.24874 -155.932 -5.24874 5.24874 0.86 0.00022297 0.000174611 0.0140711 0.011303 -1 -1 -1 -1 34 2724 30 6.87369e+06 377294 618332. 2139.56 1.58 0.07622 0.0624516 25762 151098 -1 2074 21 1789 2709 186218 47251 4.63715 4.63715 -156.683 -4.63715 0 0 787024. 2723.27 0.31 0.06 0.13 -1 -1 0.31 0.0148903 0.0129278 152 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 8.04 vpr 64.29 MiB -1 -1 0.18 21348 1 0.03 -1 -1 33760 -1 -1 25 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65832 31 32 352 285 1 186 88 17 17 289 -1 unnamed_device 25.4 MiB 3.70 890 9058 2302 6004 752 64.3 MiB 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65896 31 32 337 267 1 207 86 17 17 289 -1 unnamed_device 25.5 MiB 3.84 1158 13127 3358 8192 1577 64.4 MiB 0.10 0.00 4.80948 -147.413 -4.80948 4.80948 0.87 0.000204709 0.000158017 0.0158426 0.0124126 -1 -1 -1 -1 30 3059 23 6.87369e+06 321398 556674. 1926.21 0.98 0.0516685 0.0423348 25186 138497 -1 2479 20 1353 2038 146343 31929 3.92376 3.92376 -138.461 -3.92376 0 0 706193. 2443.58 0.27 0.05 0.12 -1 -1 0.27 0.0125177 0.0108805 140 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_046.v common 6.85 vpr 64.09 MiB -1 -1 0.18 21568 1 0.04 -1 -1 34064 -1 -1 32 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65632 32 32 349 284 1 183 96 17 17 289 -1 unnamed_device 25.3 MiB 2.56 1064 11703 2949 7949 805 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66252 32 32 431 332 1 239 89 17 17 289 -1 unnamed_device 25.7 MiB 7.23 1345 13553 3739 8295 1519 64.7 MiB 0.11 0.00 5.88501 -174.993 -5.88501 5.88501 0.86 0.000245323 0.00019343 0.0187615 0.015055 -1 -1 -1 -1 36 3244 24 6.87369e+06 349346 648988. 2245.63 2.31 0.0880204 0.0724885 26050 158493 -1 2821 22 2283 3476 317566 69187 4.6476 4.6476 -163.711 -4.6476 0 0 828058. 2865.25 0.31 0.08 0.14 -1 -1 0.31 0.0167235 0.0144216 171 65 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 8.17 vpr 64.32 MiB -1 -1 0.21 21516 1 0.03 -1 -1 34060 -1 -1 35 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 25.5 MiB 3.96 991 19023 5843 10714 2466 64.3 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65660 31 32 319 272 1 176 80 17 17 289 -1 unnamed_device 25.4 MiB 3.59 852 9712 2603 6178 931 64.1 MiB 0.07 0.00 3.7214 -119.25 -3.7214 3.7214 0.86 0.000183259 0.000144617 0.0122168 0.00983741 -1 -1 -1 -1 34 2440 41 6.87369e+06 237555 618332. 2139.56 1.60 0.0696976 0.0571619 25762 151098 -1 1987 23 1447 2180 181291 41758 3.2835 3.2835 -120.806 -3.2835 0 0 787024. 2723.27 0.30 0.06 0.14 -1 -1 0.30 0.0142525 0.0123797 114 64 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_071.v common 7.19 vpr 64.22 MiB -1 -1 0.19 21500 1 0.03 -1 -1 33836 -1 -1 34 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65760 30 32 329 273 1 167 96 17 17 289 -1 unnamed_device 25.4 MiB 3.11 924 12798 3409 8384 1005 64.2 MiB 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65560 31 32 293 230 1 175 94 17 17 289 -1 unnamed_device 25.3 MiB 1.36 1012 10744 2561 7474 709 64.0 MiB 0.08 0.00 4.55512 -132.128 -4.55512 4.55512 0.89 0.000186951 0.00014754 0.0111891 0.00879744 -1 -1 -1 -1 30 2480 24 6.87369e+06 433189 556674. 1926.21 1.04 0.0428633 0.0353869 25186 138497 -1 2052 22 1079 2002 143467 30775 3.3592 3.3592 -119.088 -3.3592 0 0 706193. 2443.58 0.28 0.05 0.14 -1 -1 0.28 0.0152971 0.0133835 129 4 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 10.53 vpr 64.43 MiB -1 -1 0.19 21692 1 0.03 -1 -1 33520 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65980 32 32 350 275 1 214 87 17 17 289 -1 unnamed_device 25.5 MiB 4.85 991 16023 4565 8930 2528 64.4 MiB 0.12 0.00 4.82048 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65196 27 32 255 219 1 139 80 17 17 289 -1 unnamed_device 25.2 MiB 1.36 647 12980 4064 8068 848 63.7 MiB 0.07 0.00 3.48275 -97.807 -3.48275 3.48275 0.87 0.000162659 0.000121533 0.0131598 0.0103956 -1 -1 -1 -1 34 1699 22 6.87369e+06 293451 618332. 2139.56 1.35 0.0546758 0.0444766 25762 151098 -1 1429 20 1057 1601 114649 26035 2.72966 2.72966 -93.4311 -2.72966 0 0 787024. 2723.27 0.31 0.04 0.13 -1 -1 0.31 0.00939077 0.00809281 96 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 10.49 vpr 64.57 MiB -1 -1 0.20 21792 1 0.03 -1 -1 33988 -1 -1 24 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66120 32 32 421 327 1 233 88 17 17 289 -1 unnamed_device 25.8 MiB 5.43 1306 7108 1644 4961 503 64.6 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65860 31 32 373 294 1 197 97 17 17 289 -1 unnamed_device 25.7 MiB 2.53 994 11641 2686 8324 631 64.3 MiB 0.09 0.00 4.45728 -128.707 -4.45728 4.45728 0.86 0.000227679 0.00018129 0.0138821 0.0112255 -1 -1 -1 -1 26 2822 32 6.87369e+06 475111 503264. 1741.40 1.09 0.056187 0.0464994 24322 120374 -1 2420 24 1643 2677 211161 49524 4.10046 4.10046 -136.732 -4.10046 0 0 618332. 2139.56 0.24 0.06 0.11 -1 -1 0.24 0.0155306 0.0133668 149 50 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_101.v common 7.02 vpr 64.16 MiB -1 -1 0.20 21500 1 0.03 -1 -1 34140 -1 -1 31 30 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65700 30 32 325 268 1 172 93 17 17 289 -1 unnamed_device 25.4 MiB 2.68 790 16473 4651 9095 2727 64.2 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 310 266 1 175 81 17 17 289 -1 unnamed_device 25.4 MiB 2.69 963 14081 4182 8130 1769 64.1 MiB 0.09 0.00 3.97822 -122.829 -3.97822 3.97822 0.89 0.000188158 0.000146273 0.0169303 0.0134773 -1 -1 -1 -1 34 2188 24 6.87369e+06 237555 618332. 2139.56 1.48 0.0683485 0.0558112 25762 151098 -1 1967 18 1248 1705 141947 30974 3.3007 3.3007 -124.41 -3.3007 0 0 787024. 2723.27 0.31 0.04 0.13 -1 -1 0.31 0.0107915 0.0093941 112 58 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 6.51 vpr 64.37 MiB -1 -1 0.19 21512 1 0.03 -1 -1 33732 -1 -1 39 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65912 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 25.5 MiB 2.06 880 19380 5710 10605 3065 64.4 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65600 31 32 265 230 1 169 80 17 17 289 -1 unnamed_device 25.3 MiB 3.90 763 6616 1499 4719 398 64.1 MiB 0.05 0.00 3.6942 -114.024 -3.6942 3.6942 0.89 0.000163157 0.00012855 0.00835915 0.00689354 -1 -1 -1 -1 34 2136 24 6.87369e+06 237555 618332. 2139.56 1.48 0.0552961 0.0457836 25762 151098 -1 1636 20 1101 1571 107353 27112 3.19991 3.19991 -110.054 -3.19991 0 0 787024. 2723.27 0.32 0.04 0.14 -1 -1 0.32 0.0102804 0.00894007 105 34 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 8.31 vpr 64.49 MiB -1 -1 0.20 21412 1 0.03 -1 -1 33884 -1 -1 31 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 349 286 1 177 95 17 17 289 -1 unnamed_device 25.4 MiB 3.80 991 15431 4685 8411 2335 64.5 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65548 32 32 318 257 1 197 86 17 17 289 -1 unnamed_device 25.4 MiB 4.36 1100 9914 2382 6266 1266 64.0 MiB 0.07 0.00 4.82651 -140.217 -4.82651 4.82651 0.87 0.000191462 0.000151394 0.0116126 0.00936138 -1 -1 -1 -1 34 2714 26 6.87369e+06 307425 618332. 2139.56 1.60 0.0657325 0.0541548 25762 151098 -1 2273 23 1641 2291 162066 37556 4.02506 4.02506 -136.33 -4.02506 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0129756 0.0111949 132 30 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 7.46 vpr 64.21 MiB -1 -1 0.19 21508 1 0.03 -1 -1 33928 -1 -1 29 29 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65756 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 25.5 MiB 3.40 896 9336 2254 6420 662 64.2 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65920 32 32 376 318 1 168 80 17 17 289 -1 unnamed_device 25.6 MiB 5.53 879 12808 3950 7474 1384 64.4 MiB 0.09 0.00 3.59615 -129.411 -3.59615 3.59615 0.86 0.000208218 0.000161966 0.0174581 0.0138737 -1 -1 -1 -1 34 2239 23 6.87369e+06 223581 618332. 2139.56 1.44 0.072401 0.0589299 25762 151098 -1 1862 21 1602 2312 183384 40198 2.87886 2.87886 -123.177 -2.87886 0 0 787024. 2723.27 0.30 0.06 0.13 -1 -1 0.30 0.0134128 0.0115365 114 96 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 7.83 vpr 64.27 MiB -1 -1 0.20 21420 1 0.03 -1 -1 33892 -1 -1 32 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 360 293 1 182 96 17 17 289 -1 unnamed_device 25.3 MiB 3.71 1029 16083 4329 9310 2444 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65832 30 32 363 293 1 229 88 17 17 289 -1 unnamed_device 25.4 MiB 2.64 1124 13738 3850 8296 1592 64.3 MiB 0.11 0.00 4.83304 -147.244 -4.83304 4.83304 0.89 0.000206477 0.000163244 0.016513 0.0131582 -1 -1 -1 -1 34 2963 23 6.89349e+06 366440 618332. 2139.56 1.69 0.0724681 0.059149 25762 151098 -1 2412 24 2103 3099 213515 50520 4.35719 4.35719 -147.275 -4.35719 0 0 787024. 2723.27 0.30 0.06 0.13 -1 -1 0.30 0.0146084 0.0125248 158 63 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_003.v common 7.49 vpr 63.85 MiB -1 -1 0.17 21364 1 0.03 -1 -1 33896 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65380 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 25.3 MiB 2.76 986 10315 2668 7087 560 63.8 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2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65496 32 32 338 269 1 205 86 17 17 289 -1 unnamed_device 25.2 MiB 2.72 1059 14450 4622 7260 2568 64.0 MiB 0.10 0.00 4.13204 -133.409 -4.13204 4.13204 0.86 0.000207884 0.000163843 0.0176867 0.0141329 -1 -1 -1 -1 34 2659 50 6.89349e+06 310065 618332. 2139.56 1.95 0.087335 0.0716111 25762 151098 -1 2275 19 1487 2177 187547 40425 3.10146 3.10146 -121.303 -3.10146 0 0 787024. 2723.27 0.29 0.05 0.13 -1 -1 0.29 0.0119671 0.0103802 142 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 8.10 vpr 63.51 MiB -1 -1 0.20 21580 1 0.03 -1 -1 33508 -1 -1 21 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65036 32 32 323 276 1 215 85 17 17 289 -1 unnamed_device 24.8 MiB 3.11 1220 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65216 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 25.1 MiB 1.09 988 16079 4364 9917 1798 63.7 MiB 0.12 0.00 3.39295 -107.482 -3.39295 3.39295 0.95 0.000186774 0.000147218 0.0155786 0.012451 -1 -1 -1 -1 28 2520 24 6.89349e+06 436909 531479. 1839.03 1.02 0.0495745 0.040932 24610 126494 -1 2310 22 1455 2525 183042 43297 2.94641 2.94641 -112.319 -2.94641 0 0 648988. 2245.63 0.26 0.05 0.11 -1 -1 0.26 0.0121503 0.0104621 130 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 8.50 vpr 64.37 MiB -1 -1 0.22 21404 1 0.03 -1 -1 33868 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 338 277 1 215 87 17 17 289 -1 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GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65248 31 32 279 237 1 167 81 17 17 289 -1 unnamed_device 25.1 MiB 2.32 891 12681 4633 6140 1908 63.7 MiB 0.08 0.00 4.00748 -121.286 -4.00748 4.00748 0.88 0.000167801 0.00013189 0.0136682 0.0109159 -1 -1 -1 -1 34 2241 20 6.89349e+06 253689 618332. 2139.56 1.70 0.0604483 0.0494803 25762 151098 -1 1909 20 958 1482 148975 31008 3.08205 3.08205 -114.277 -3.08205 0 0 787024. 2723.27 0.31 0.05 0.14 -1 -1 0.31 0.0109286 0.00945882 109 34 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 8.63 vpr 64.05 MiB -1 -1 0.20 21568 1 0.03 -1 -1 34192 -1 -1 25 31 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 31 32 370 297 1 235 88 17 17 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Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65176 32 32 291 230 1 175 90 17 17 289 -1 unnamed_device 25.1 MiB 1.19 980 8934 2029 6214 691 63.6 MiB 0.08 0.00 4.26729 -129.015 -4.26729 4.26729 0.88 0.000186274 0.00014782 0.0105544 0.00863692 -1 -1 -1 -1 32 2710 19 6.89349e+06 366440 586450. 2029.24 0.95 0.039582 0.032944 25474 144626 -1 2224 21 1333 2551 219755 47788 3.5072 3.5072 -124.725 -3.5072 0 0 744469. 2576.02 0.29 0.06 0.14 -1 -1 0.29 0.0115817 0.00996786 123 3 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 8.25 vpr 64.01 MiB -1 -1 0.20 21420 1 0.03 -1 -1 33776 -1 -1 23 32 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65548 32 32 353 287 1 220 87 17 17 289 -1 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critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 3.42 vpr 62.79 MiB -1 -1 0.38 18688 14 0.25 -1 -1 32944 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64300 32 32 277 309 1 202 103 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1547 9502 2152 6495 855 62.8 MiB 0.09 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64488 32 32 302 334 1 214 106 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1672 9856 2131 7054 671 63.0 MiB 0.11 0.00 8.06277 -168.566 -8.06277 8.06277 0.32 0.00100468 0.000929012 0.0474751 0.0438051 -1 -1 -1 -1 32 3848 27 6.55708e+06 506310 554710. 1919.41 0.76 0.185353 0.162891 22174 131602 -1 3263 16 1310 4212 205623 50945 7.27044 7.27044 -162.359 -7.27044 0 0 701300. 2426.64 0.04 0.09 0.11 -1 -1 0.04 0.0385923 0.0343556 217 208 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 3.24 vpr 62.84 MiB -1 -1 0.39 18616 13 0.24 -1 -1 32908 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 32 32 292 324 1 214 105 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1522 10479 2742 6826 911 62.8 MiB 0.11 0.00 8.0037 -160.293 -8.0037 8.0037 0.32 0.000938065 0.000869644 0.0437923 0.0405003 -1 -1 -1 -1 30 3477 18 6.55708e+06 494255 526063. 1820.29 0.74 0.158732 0.139622 21886 126133 -1 2963 16 1237 4638 205817 50427 6.61036 6.61036 -146.138 -6.61036 0 0 666494. 2306.21 0.03 0.09 0.12 -1 -1 0.03 0.0341773 0.0301008 207 198 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 2.76 vpr 62.60 MiB -1 -1 0.28 17976 12 0.19 -1 -1 32644 -1 -1 38 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 27 32 229 261 1 167 97 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1076 6757 1422 4783 552 62.6 MiB 0.06 0.00 7.57737 -131.413 -7.57737 7.57737 0.35 0.000740353 0.000687695 0.0254221 0.0235468 -1 -1 -1 -1 30 2249 15 6.55708e+06 458090 526063. 1820.29 0.51 0.107135 0.0937171 21886 126133 -1 1995 16 754 2397 101760 26051 6.58844 6.58844 -121.637 -6.58844 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0301412 0.0274345 162 150 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 3.27 vpr 62.58 MiB -1 -1 0.30 18408 12 0.19 -1 -1 32680 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64080 31 32 229 261 1 172 96 17 17 289 -1 unnamed_device 23.3 MiB 0.11 1185 7761 1749 4997 1015 62.6 MiB 0.07 0.00 6.59345 -131.227 -6.59345 6.59345 0.32 0.000740267 0.000683218 0.0287775 0.0266122 -1 -1 -1 -1 26 3514 29 6.55708e+06 397815 477104. 1650.88 0.94 0.134112 0.117297 21022 109990 -1 2674 30 1375 5142 317498 101013 5.83766 5.83766 -127.871 -5.83766 0 0 585099. 2024.56 0.03 0.13 0.09 -1 -1 0.03 0.0413928 0.0359352 148 138 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 3.39 vpr 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64212 32 32 250 282 1 185 101 17 17 289 -1 unnamed_device 23.5 MiB 0.13 1310 8561 1766 6158 637 62.7 MiB 0.08 0.00 7.32681 -164.785 -7.32681 7.32681 0.32 0.000806421 0.000748231 0.032678 0.0302492 -1 -1 -1 -1 22 3707 41 6.55708e+06 446035 420624. 1455.45 0.96 0.159714 0.139055 20158 92377 -1 3144 22 1536 4703 302925 83797 7.11044 7.11044 -169.479 -7.11044 0 0 500653. 1732.36 0.02 0.12 0.08 -1 -1 0.02 0.0377263 0.0330363 169 156 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 3.04 vpr 62.66 MiB -1 -1 0.32 18360 12 0.18 -1 -1 32500 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 30 32 216 248 1 156 96 17 17 289 -1 unnamed_device 23.5 MiB 0.10 1085 13455 3502 7863 2090 62.7 MiB 0.11 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 32 32 154 186 1 117 91 17 17 289 -1 unnamed_device 23.0 MiB 0.06 804 12127 3272 7580 1275 62.4 MiB 0.08 0.00 4.197 -96.967 -4.197 4.197 0.31 0.000509299 0.000472577 0.0323362 0.0300116 -1 -1 -1 -1 26 1624 14 6.55708e+06 325485 477104. 1650.88 0.54 0.0861366 0.0759918 21022 109990 -1 1429 12 453 1098 55059 14583 3.85168 3.85168 -96.2848 -3.85168 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0142867 0.0125614 83 60 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_026.v common 2.98 vpr 62.74 MiB -1 -1 0.23 18368 15 0.23 -1 -1 32684 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 32 32 254 286 1 185 105 17 17 289 -1 unnamed_device 23.5 MiB 0.10 1357 8750 1852 5899 999 62.7 MiB 0.08 0.00 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64384 30 32 213 245 1 156 93 17 17 289 -1 unnamed_device 23.3 MiB 0.08 1055 6813 1438 4810 565 62.9 MiB 0.06 0.00 6.26019 -134.121 -6.26019 6.26019 0.31 0.00068437 0.000634858 0.0248044 0.0229674 -1 -1 -1 -1 30 2151 16 6.55708e+06 373705 526063. 1820.29 0.56 0.102637 0.0897125 21886 126133 -1 1944 16 673 2039 82756 21710 5.59726 5.59726 -126.076 -5.59726 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0238631 0.0209819 135 125 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_031.v common 2.76 vpr 62.54 MiB -1 -1 0.27 18100 11 0.19 -1 -1 32736 -1 -1 38 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 28 32 227 259 1 163 98 17 17 289 -1 unnamed_device 23.3 MiB 0.09 1081 10223 2473 6798 952 62.5 MiB 0.09 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64224 31 32 276 308 1 208 108 17 17 289 -1 unnamed_device 23.6 MiB 0.13 1520 8332 1703 5917 712 62.7 MiB 0.09 0.00 7.94503 -161.931 -7.94503 7.94503 0.32 0.000907456 0.000836347 0.0336936 0.031227 -1 -1 -1 -1 26 4333 40 6.55708e+06 542475 477104. 1650.88 1.02 0.173665 0.151349 21022 109990 -1 3482 17 1358 4203 231179 55264 7.22664 7.22664 -160.684 -7.22664 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0333933 0.0294144 200 185 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_041.v common 3.27 vpr 62.66 MiB -1 -1 0.39 18500 13 0.25 -1 -1 32904 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64160 31 32 269 301 1 187 100 17 17 289 -1 unnamed_device 23.6 MiB 0.12 1368 6596 1290 4863 443 62.7 MiB 0.07 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 31 32 284 316 1 196 104 17 17 289 -1 unnamed_device 23.7 MiB 0.14 1353 8400 1833 5671 896 62.8 MiB 0.08 0.00 8.00359 -155.245 -8.00359 8.00359 0.31 0.000908757 0.000841742 0.0358726 0.0331558 -1 -1 -1 -1 24 3710 27 6.55708e+06 494255 448715. 1552.65 1.43 0.161372 0.140867 20734 103517 -1 3127 19 1328 4863 261396 62929 7.33356 7.33356 -160.506 -7.33356 0 0 554710. 1919.41 0.02 0.10 0.09 -1 -1 0.02 0.0370573 0.032434 201 193 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_046.v common 3.51 vpr 62.97 MiB -1 -1 0.36 18516 12 0.23 -1 -1 32672 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64484 32 32 303 335 1 212 104 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1559 7424 1464 5587 373 63.0 MiB 0.08 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65464 32 32 351 383 1 255 115 17 17 289 -1 unnamed_device 24.2 MiB 0.16 1912 10996 2333 7725 938 63.9 MiB 0.12 0.00 9.61395 -186.411 -9.61395 9.61395 0.32 0.0011181 0.00103394 0.0489481 0.0452034 -1 -1 -1 -1 30 4514 22 6.55708e+06 614805 526063. 1820.29 0.99 0.19515 0.17157 21886 126133 -1 3814 18 1702 6171 283766 68025 8.38947 8.38947 -178.746 -8.38947 0 0 666494. 2306.21 0.03 0.11 0.10 -1 -1 0.03 0.0451658 0.0398477 263 257 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_061.v common 3.50 vpr 63.46 MiB -1 -1 0.27 18540 13 0.31 -1 -1 32704 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64988 32 32 297 329 1 211 102 17 17 289 -1 unnamed_device 23.7 MiB 0.14 1494 7004 1387 5016 601 63.5 MiB 0.08 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 30 32 228 260 1 158 97 17 17 289 -1 unnamed_device 23.4 MiB 0.09 1101 6979 1478 4733 768 62.5 MiB 0.06 0.00 7.33897 -151.074 -7.33897 7.33897 0.32 0.000743562 0.000688744 0.0262544 0.0243127 -1 -1 -1 -1 28 2502 19 6.55708e+06 421925 500653. 1732.36 0.53 0.114578 0.100017 21310 115450 -1 2128 14 720 2386 111841 28645 6.59044 6.59044 -145.015 -6.59044 0 0 612192. 2118.31 0.04 0.08 0.12 -1 -1 0.04 0.0296621 0.0262135 152 140 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_066.v common 3.19 vpr 62.88 MiB -1 -1 0.40 18500 12 0.27 -1 -1 33148 -1 -1 41 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64392 29 32 275 307 1 195 102 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1359 6290 1245 4520 525 62.9 MiB 0.07 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 29 32 262 294 1 197 101 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1268 9501 2060 6462 979 62.7 MiB 0.09 0.00 7.09867 -136.55 -7.09867 7.09867 0.32 0.000888396 0.000824305 0.0394313 0.0365356 -1 -1 -1 -1 28 3329 23 6.55708e+06 482200 500653. 1732.36 0.81 0.153343 0.134375 21310 115450 -1 2580 16 1111 3693 174673 45072 6.17838 6.17838 -129.615 -6.17838 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.031461 0.0277134 187 177 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_086.v common 2.70 vpr 62.45 MiB -1 -1 0.30 18100 13 0.16 -1 -1 32568 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63952 32 32 222 254 1 166 98 17 17 289 -1 unnamed_device 23.2 MiB 0.09 1204 5273 829 4270 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64220 31 32 244 276 1 183 99 17 17 289 -1 unnamed_device 23.5 MiB 0.10 1234 5343 953 4107 283 62.7 MiB 0.06 0.00 7.43715 -158.003 -7.43715 7.43715 0.32 0.000792845 0.000735142 0.0216441 0.0200635 -1 -1 -1 -1 28 3024 19 6.55708e+06 433980 500653. 1732.36 0.69 0.116315 0.10146 21310 115450 -1 2710 15 1091 3540 165817 43066 6.44632 6.44632 -152.105 -6.44632 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0262288 0.023126 164 153 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_091.v common 3.79 vpr 62.85 MiB -1 -1 0.37 18668 12 0.29 -1 -1 32728 -1 -1 44 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 32 32 300 332 1 220 108 17 17 289 -1 unnamed_device 23.6 MiB 0.12 1579 8332 1506 5759 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63892 27 32 219 251 1 154 95 17 17 289 -1 unnamed_device 23.1 MiB 0.08 1050 6359 1311 4459 589 62.4 MiB 0.06 0.00 6.77412 -124.861 -6.77412 6.77412 0.32 0.000713459 0.000661731 0.0237722 0.0219985 -1 -1 -1 -1 26 2518 28 6.55708e+06 433980 477104. 1650.88 0.64 0.117944 0.102417 21022 109990 -1 2290 18 974 3227 154423 38178 5.86158 5.86158 -120.568 -5.86158 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0275303 0.0241178 147 140 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_096.v common 4.52 vpr 63.91 MiB -1 -1 0.42 19032 13 0.44 -1 -1 32772 -1 -1 54 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65444 32 32 380 412 1 268 118 17 17 289 -1 unnamed_device 24.4 MiB 0.25 1943 11678 2402 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63888 32 32 235 267 1 175 100 17 17 289 -1 unnamed_device 23.1 MiB 0.09 1209 8452 1924 5669 859 62.4 MiB 0.08 0.00 7.00455 -144.749 -7.00455 7.00455 0.31 0.000733587 0.000678251 0.02952 0.0272855 -1 -1 -1 -1 30 2684 30 6.55708e+06 433980 526063. 1820.29 0.61 0.127043 0.110742 21886 126133 -1 2234 16 921 2754 114752 30025 6.07044 6.07044 -136.126 -6.07044 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0260629 0.022921 156 141 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_106.v common 3.36 vpr 62.86 MiB -1 -1 0.35 18372 13 0.31 -1 -1 32832 -1 -1 43 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64368 31 32 294 326 1 209 106 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1483 8106 1671 5747 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64396 31 32 225 257 1 161 101 17 17 289 -1 unnamed_device 23.1 MiB 0.09 1212 6916 1486 4812 618 62.9 MiB 0.06 0.00 7.22863 -147.66 -7.22863 7.22863 0.32 0.00069335 0.000652807 0.0238351 0.022098 -1 -1 -1 -1 28 2636 14 6.55708e+06 458090 500653. 1732.36 0.62 0.103974 0.0910087 21310 115450 -1 2360 14 823 2439 123719 30628 6.45858 6.45858 -142.003 -6.45858 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0230327 0.0203696 147 134 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_111.v common 3.33 vpr 63.38 MiB -1 -1 0.35 18436 12 0.20 -1 -1 32828 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64904 32 32 288 320 1 207 102 17 17 289 -1 unnamed_device 23.7 MiB 0.13 1453 7242 1384 5338 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 32 32 285 317 1 211 104 17 17 289 -1 unnamed_device 23.6 MiB 0.14 1523 12304 3016 8156 1132 62.7 MiB 0.12 0.00 8.0432 -171.219 -8.0432 8.0432 0.31 0.000924381 0.000858307 0.0502871 0.0466214 -1 -1 -1 -1 26 4101 25 6.55708e+06 482200 477104. 1650.88 1.03 0.169712 0.149072 21022 109990 -1 3342 18 1458 4644 236912 56442 6.94704 6.94704 -162.816 -6.94704 0 0 585099. 2024.56 0.03 0.09 0.11 -1 -1 0.03 0.0358245 0.0314794 203 191 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_116.v common 3.23 vpr 62.64 MiB -1 -1 0.34 18344 11 0.19 -1 -1 33160 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64140 29 32 243 275 1 177 97 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1302 7201 1461 5220 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64020 32 32 238 270 1 177 101 17 17 289 -1 unnamed_device 23.5 MiB 0.09 1218 9501 2083 6458 960 62.5 MiB 0.08 0.00 7.91043 -170.443 -7.91043 7.91043 0.32 0.000758064 0.000703417 0.0336526 0.0311554 -1 -1 -1 -1 26 2922 26 6.55708e+06 446035 477104. 1650.88 0.67 0.133295 0.11664 21022 109990 -1 2523 22 1300 4049 241032 73323 6.78444 6.78444 -160.626 -6.78444 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0332941 0.0290198 163 144 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_121.v common 3.25 vpr 62.82 MiB -1 -1 0.38 18620 12 0.22 -1 -1 32676 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64328 32 32 269 301 1 187 99 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1308 9675 2304 6571 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 32 32 264 296 1 189 102 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1292 11050 2366 7675 1009 62.8 MiB 0.10 0.00 7.4882 -160.311 -7.4882 7.4882 0.32 0.000852834 0.000791169 0.0431371 0.0399693 -1 -1 -1 -1 32 2688 19 6.55708e+06 458090 554710. 1919.41 0.53 0.143565 0.126182 22174 131602 -1 2548 15 967 2908 141203 35435 6.62964 6.62964 -153.549 -6.62964 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0282648 0.0249116 183 170 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_126.v common 2.43 vpr 62.57 MiB -1 -1 0.27 17920 9 0.15 -1 -1 32444 -1 -1 32 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 25 32 183 215 1 133 89 17 17 289 -1 unnamed_device 22.9 MiB 0.07 884 9791 2362 5778 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64504 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 23.9 MiB 0.21 1149 17066 4987 10364 1715 63.0 MiB 0.18 0.00 4.95721 -143.504 -4.95721 4.95721 0.32 0.000710438 0.000660775 0.0614398 0.0570745 -1 -1 -1 -1 32 2427 21 6.64007e+06 376740 554710. 1919.41 0.57 0.145575 0.129108 22834 132086 -1 2154 19 1350 2068 152921 33916 3.93949 3.93949 -135.593 -3.93949 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0272536 0.0238064 147 63 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.68 vpr 62.80 MiB -1 -1 0.23 18488 1 0.03 -1 -1 30312 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 299 247 1 188 95 17 17 289 -1 unnamed_device 23.6 MiB 0.21 995 8519 1888 6283 348 62.8 MiB 0.09 0.00 4.69952 -119.793 -4.69952 4.69952 0.32 0.000629047 0.000585652 0.0270416 0.0251595 -1 -1 -1 -1 26 2703 22 6.64007e+06 389298 477104. 1650.88 0.59 0.103803 0.0908653 21682 110474 -1 2071 19 1134 1713 100741 25334 3.82002 3.82002 -121.448 -3.82002 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0245892 0.021454 129 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.64 vpr 62.60 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30340 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 23.5 MiB 0.07 1008 16445 5394 8747 2304 62.6 MiB 0.16 0.00 4.53207 -121.894 -4.53207 4.53207 0.31 0.000634108 0.000588823 0.0522809 0.04853 -1 -1 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0.09 -1 -1 0.03 0.0306004 0.0266689 134 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.73 vpr 62.80 MiB -1 -1 0.25 18556 1 0.03 -1 -1 30344 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64308 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1006 15768 4339 8895 2534 62.8 MiB 0.15 0.00 3.38256 -114.774 -3.38256 3.38256 0.32 0.000724938 0.000673003 0.0497796 0.04616 -1 -1 -1 -1 32 2303 19 6.64007e+06 489762 554710. 1919.41 0.56 0.133213 0.117724 22834 132086 -1 1827 17 1074 1725 91804 23651 3.05137 3.05137 -112.229 -3.05137 0 0 701300. 2426.64 0.03 0.06 0.10 -1 -1 0.03 0.0301609 0.0264063 145 58 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.43 vpr 63.12 MiB -1 -1 0.23 18080 1 0.03 -1 -1 30572 -1 -1 21 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64636 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 23.5 MiB 0.08 751 11948 4103 6020 1825 63.1 MiB 0.10 0.00 3.76738 -102.601 -3.76738 3.76738 0.32 0.000553592 0.000515184 0.0404029 0.0376175 -1 -1 -1 -1 28 1527 20 6.64007e+06 263718 500653. 1732.36 0.48 0.10499 0.0926546 21970 115934 -1 1471 20 917 1568 101266 24667 2.74477 2.74477 -95.077 -2.74477 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0224191 0.0194903 97 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.59 vpr 62.68 MiB -1 -1 0.24 17844 1 0.03 -1 -1 30220 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64188 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 23.6 MiB 0.06 965 15848 4431 8849 2568 62.7 MiB 0.14 0.00 3.47227 -101.06 -3.47227 3.47227 0.35 0.000595573 0.000554221 0.0440162 0.0408999 -1 -1 -1 -1 32 1850 22 6.64007e+06 439530 554710. 1919.41 0.50 0.116127 0.102699 22834 132086 -1 1654 15 788 1468 75522 19037 2.60777 2.60777 -91.3107 -2.60777 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.019078 0.0167327 123 4 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.86 vpr 62.68 MiB -1 -1 0.24 18476 1 0.03 -1 -1 30096 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 31 32 317 271 1 168 87 17 17 289 -1 unnamed_device 23.5 MiB 0.16 906 5655 1194 4208 253 62.7 MiB 0.07 0.00 3.60222 -117.559 -3.60222 3.60222 0.32 0.000639636 0.000594878 0.0209485 0.0195041 -1 -1 -1 -1 28 2705 33 6.64007e+06 301392 500653. 1732.36 0.81 0.108644 0.0943614 21970 115934 -1 2030 20 1272 1882 135466 32452 3.48643 3.48643 -121.992 -3.48643 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0250351 0.0217808 117 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.55 vpr 62.54 MiB -1 -1 0.23 18256 1 0.03 -1 -1 30068 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64036 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 23.5 MiB 0.13 936 12323 3600 6804 1919 62.5 MiB 0.12 0.00 3.85841 -126.873 -3.85841 3.85841 0.32 0.000619093 0.000576413 0.0446968 0.0416188 -1 -1 -1 -1 32 1786 19 6.64007e+06 238602 554710. 1919.41 0.52 0.11678 0.103252 22834 132086 -1 1612 19 841 1348 82679 19678 2.65457 2.65457 -110.251 -2.65457 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0229212 0.0201044 115 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.54 vpr 62.74 MiB -1 -1 0.25 18388 1 0.03 -1 -1 30384 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.6 MiB 0.12 895 11106 3427 6381 1298 62.7 MiB 0.11 0.00 3.83641 -113.668 -3.83641 3.83641 0.32 0.00061658 0.000573067 0.0411971 0.0383264 -1 -1 -1 -1 32 1647 21 6.64007e+06 238602 554710. 1919.41 0.50 0.113563 0.100095 22834 132086 -1 1460 17 663 1021 62497 14760 2.80297 2.80297 -100.224 -2.80297 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0216856 0.0189302 101 63 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.69 vpr 62.66 MiB -1 -1 0.23 18084 1 0.03 -1 -1 30100 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 23.6 MiB 0.23 914 15063 5013 7393 2657 62.7 MiB 0.14 0.00 3.80941 -119.793 -3.80941 3.80941 0.32 0.000593224 0.000551677 0.0487755 0.0453526 -1 -1 -1 -1 30 2022 22 6.64007e+06 288834 526063. 1820.29 0.52 0.12086 0.107095 22546 126617 -1 1661 17 830 1209 74992 17561 2.80297 2.80297 -107.181 -2.80297 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0208561 0.0182301 111 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 2.65 vpr 62.78 MiB -1 -1 0.13 18376 1 0.03 -1 -1 30344 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64284 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 23.8 MiB 0.21 1145 10803 2724 7364 715 62.8 MiB 0.12 0.00 4.40284 -140.386 -4.40284 4.40284 0.32 0.000709355 0.000659531 0.0383752 0.035603 -1 -1 -1 -1 30 2401 22 6.64007e+06 364182 526063. 1820.29 0.58 0.122776 0.107981 22546 126617 -1 2127 21 1359 2094 110426 27165 3.25703 3.25703 -124.202 -3.25703 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0291253 0.0254331 147 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.80 vpr 63.43 MiB -1 -1 0.16 18368 1 0.03 -1 -1 30268 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.13 989 17873 5923 8850 3100 63.4 MiB 0.17 0.00 4.77444 -137.586 -4.77444 4.77444 0.32 0.000712912 0.000662078 0.0594743 0.0552107 -1 -1 -1 -1 28 2617 24 6.64007e+06 426972 500653. 1732.36 0.75 0.150152 0.13295 21970 115934 -1 2048 20 1394 2351 145782 36264 4.26142 4.26142 -132.668 -4.26142 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.028755 0.0251025 139 61 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.41 vpr 62.78 MiB -1 -1 0.22 18068 1 0.03 -1 -1 30400 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 23.2 MiB 0.08 694 9234 2301 6256 677 62.8 MiB 0.08 0.00 3.09179 -89.0655 -3.09179 3.09179 0.32 0.000541072 0.000503614 0.0294454 0.0273744 -1 -1 -1 -1 28 1661 20 6.64007e+06 288834 500653. 1732.36 0.48 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 32 32 323 276 1 153 98 17 17 289 -1 unnamed_device 23.6 MiB 0.09 912 16523 5279 8659 2585 62.8 MiB 0.15 0.00 2.85064 -102.219 -2.85064 2.85064 0.31 0.000652995 0.000606818 0.0503687 0.0467251 -1 -1 -1 -1 32 1754 21 6.64007e+06 426972 554710. 1919.41 0.54 0.125923 0.111248 22834 132086 -1 1560 18 1067 1888 103791 25844 1.91191 1.91191 -89.0293 -1.91191 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0239531 0.0208594 115 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 2.31 vpr 62.77 MiB -1 -1 0.21 18116 1 0.03 -1 -1 30064 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 30 32 222 206 1 117 79 17 17 289 -1 unnamed_device 23.6 MiB 0.06 532 9543 2250 6629 664 62.8 MiB 0.07 0.00 2.4343 -77.8363 -2.4343 2.4343 0.31 0.000498159 0.00046299 0.0295526 0.0274642 -1 -1 -1 -1 28 1401 21 6.64007e+06 213486 500653. 1732.36 0.51 0.087921 0.0771578 21970 115934 -1 1137 19 688 980 63827 17614 1.86811 1.86811 -77.6028 -1.86811 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0187935 0.0163088 85 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 2.70 vpr 62.58 MiB -1 -1 0.24 18244 1 0.03 -1 -1 30440 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 31 32 291 243 1 171 88 17 17 289 -1 unnamed_device 23.5 MiB 0.24 847 10423 2562 6326 1535 62.6 MiB 0.10 0.00 5.02597 -142.893 -5.02597 5.02597 0.32 0.000610921 0.000568644 0.0349955 0.0325792 -1 -1 -1 -1 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0.03 0.03006 0.0262474 140 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 2.91 vpr 62.91 MiB -1 -1 0.26 18548 1 0.03 -1 -1 30292 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 23.8 MiB 0.23 1260 17591 5360 9925 2306 62.9 MiB 0.19 0.00 4.72719 -143.457 -4.72719 4.72719 0.35 0.000740177 0.000688771 0.0632155 0.0586458 -1 -1 -1 -1 32 2623 20 6.64007e+06 389298 554710. 1919.41 0.56 0.148536 0.131775 22834 132086 -1 2332 17 1286 2056 118473 28953 3.90649 3.90649 -129.764 -3.90649 0 0 701300. 2426.64 0.03 0.06 0.09 -1 -1 0.03 0.0257533 0.0225868 151 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.44 vpr 62.62 MiB -1 -1 0.21 18080 1 0.03 -1 -1 30528 -1 -1 20 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64124 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 23.2 MiB 0.09 426 10536 3993 4440 2103 62.6 MiB 0.07 0.00 2.50053 -67.6186 -2.50053 2.50053 0.32 0.000436929 0.000400303 0.0290515 0.0268679 -1 -1 -1 -1 32 1026 22 6.64007e+06 251160 554710. 1919.41 0.51 0.0817182 0.0716779 22834 132086 -1 874 18 548 811 45228 13433 1.97731 1.97731 -65.3841 -1.97731 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0152356 0.0132622 81 30 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 2.53 vpr 62.68 MiB -1 -1 0.22 17864 1 0.03 -1 -1 30276 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 32 32 285 227 1 165 89 17 17 289 -1 unnamed_device 23.6 MiB 0.07 962 6821 1380 5168 273 62.7 MiB 0.08 0.00 4.45587 -122.025 -4.45587 4.45587 0.32 0.000632837 0.000579639 0.0236586 0.0219696 -1 -1 -1 -1 32 2155 19 6.64007e+06 313950 554710. 1919.41 0.55 0.0955033 0.0835082 22834 132086 -1 1903 22 1221 2303 145599 33656 3.56023 3.56023 -116.407 -3.56023 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0269469 0.0234776 125 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.40 vpr 62.68 MiB -1 -1 0.20 17616 1 0.02 -1 -1 30032 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64184 32 32 173 169 1 116 81 17 17 289 -1 unnamed_device 23.4 MiB 0.05 506 11281 3424 5287 2570 62.7 MiB 0.07 0.00 2.72793 -76.1863 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62.79 MiB -1 -1 0.24 18376 1 0.03 -1 -1 30248 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 32 32 338 277 1 179 99 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1102 15147 4066 9723 1358 62.8 MiB 0.15 0.00 4.9076 -137.928 -4.9076 4.9076 0.32 0.000693713 0.000642192 0.0478832 0.0443651 -1 -1 -1 -1 30 2217 21 6.64007e+06 439530 526063. 1820.29 0.53 0.127985 0.112974 22546 126617 -1 1976 19 975 1710 85252 20817 3.73962 3.73962 -125.26 -3.73962 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0265032 0.0231786 133 50 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.44 vpr 63.14 MiB -1 -1 0.22 18024 1 0.03 -1 -1 30044 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 284 241 1 145 85 17 17 289 -1 unnamed_device 23.3 MiB 0.07 891 9943 2356 6701 886 63.1 MiB 0.10 0.00 3.06979 -104.718 -3.06979 3.06979 0.31 0.000603833 0.000560397 0.0349301 0.0324289 -1 -1 -1 -1 32 1751 17 6.64007e+06 263718 554710. 1919.41 0.49 0.1021 0.0898442 22834 132086 -1 1528 20 825 1366 74902 18215 2.59557 2.59557 -98.7069 -2.59557 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0250366 0.0217718 107 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 2.20 vpr 62.54 MiB -1 -1 0.22 18104 1 0.03 -1 -1 30208 -1 -1 28 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64044 30 32 262 227 1 135 90 17 17 289 -1 unnamed_device 23.2 MiB 0.04 680 8733 1889 6137 707 62.5 MiB 0.08 0.00 3.24119 -95.6654 -3.24119 3.24119 0.24 0.000566872 0.000527984 0.0264591 0.0246154 -1 -1 -1 -1 32 1467 24 6.64007e+06 351624 554710. 1919.41 0.50 0.0951258 0.0831051 22834 132086 -1 1268 15 541 823 48367 12287 2.78097 2.78097 -89.3799 -2.78097 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0180998 0.0158592 100 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 2.42 vpr 62.76 MiB -1 -1 0.23 18080 1 0.03 -1 -1 30176 -1 -1 27 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64264 28 32 260 223 1 140 87 17 17 289 -1 unnamed_device 23.4 MiB 0.07 639 10263 2494 7193 576 62.8 MiB 0.09 0.00 3.42827 -93.8875 -3.42827 3.42827 0.32 0.00043274 0.000391438 0.0289215 0.0266058 -1 -1 -1 -1 32 1562 21 6.64007e+06 339066 554710. 1919.41 0.47 0.0861484 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fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.40 vpr 62.91 MiB -1 -1 0.18 17992 1 0.03 -1 -1 30284 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64420 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 23.9 MiB 0.07 762 8199 1685 6175 339 62.9 MiB 0.08 0.00 3.50227 -101.986 -3.50227 3.50227 0.32 0.000585689 0.000544952 0.0239081 0.0222302 -1 -1 -1 -1 26 1895 22 6.64007e+06 414414 477104. 1650.88 0.55 0.0985801 0.0861158 21682 110474 -1 1634 19 992 1839 102453 25790 2.84297 2.84297 -101.016 -2.84297 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0222234 0.0193272 111 30 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.55 vpr 63.14 MiB -1 -1 0.23 18392 1 0.03 -1 -1 30376 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 23.6 MiB 0.13 926 8579 2243 5615 721 63.1 MiB 0.09 0.00 3.38029 -105.574 -3.38029 3.38029 0.32 0.000606378 0.000563299 0.0269435 0.0250583 -1 -1 -1 -1 32 1817 16 6.64007e+06 389298 554710. 1919.41 0.52 0.0856407 0.0752452 22834 132086 -1 1610 20 846 1287 80837 19336 2.46117 2.46117 -95.63 -2.46117 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0238605 0.0207606 112 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 2.62 vpr 63.50 MiB -1 -1 0.18 18424 1 0.03 -1 -1 30488 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 367 282 1 201 106 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1231 12606 3242 8430 934 63.5 MiB 0.13 0.00 4.47716 -125.986 -4.47716 4.47716 0.34 0.000742465 0.000690503 0.040033 0.0371622 -1 -1 -1 -1 30 2392 22 6.64007e+06 527436 526063. 1820.29 0.57 0.121338 0.107295 22546 126617 -1 2206 21 1094 2094 127085 27888 3.60143 3.60143 -119.17 -3.60143 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0305183 0.026678 158 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 2.79 vpr 63.49 MiB -1 -1 0.25 18340 1 0.04 -1 -1 30180 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65012 32 32 391 311 1 192 105 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1118 12208 2919 8273 1016 63.5 MiB 0.17 0.00 3.91238 -131.369 -3.91238 3.91238 0.32 0.000761885 0.000699352 0.055694 0.0515452 -1 -1 -1 -1 28 2461 21 6.64007e+06 514878 500653. 1732.36 0.57 0.144934 0.12814 21970 115934 -1 2208 19 1586 2620 148161 36739 2.95517 2.95517 -121.08 -2.95517 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0289413 0.0253146 150 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.72 vpr 62.75 MiB -1 -1 0.22 18372 1 0.03 -1 -1 30040 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 23.6 MiB 0.18 947 12938 4038 6585 2315 62.7 MiB 0.13 0.00 4.39563 -129.442 -4.39563 4.39563 0.31 0.000592796 0.000550729 0.0448114 0.0415629 -1 -1 -1 -1 28 2146 18 6.64007e+06 288834 500653. 1732.36 0.64 0.112874 0.0997387 21970 115934 -1 1870 18 1048 1494 96179 23713 3.25683 3.25683 -117.68 -3.25683 0 0 612192. 2118.31 0.03 0.06 0.10 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 31 32 377 302 1 234 99 17 17 289 -1 unnamed_device 24.2 MiB 0.36 1443 12183 2916 8073 1194 63.1 MiB 0.15 0.00 5.78896 -175.168 -5.78896 5.78896 0.34 0.000730371 0.000678859 0.042079 0.0390942 -1 -1 -1 -1 28 3186 22 6.64007e+06 452088 500653. 1732.36 0.59 0.124257 0.109624 21970 115934 -1 2704 21 1544 2373 159211 37709 4.84135 4.84135 -166.082 -4.84135 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0305437 0.0267185 178 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.98 vpr 62.88 MiB -1 -1 0.25 18228 1 0.03 -1 -1 30372 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 23.8 MiB 0.31 1234 12191 3319 7524 1348 62.9 MiB 0.14 0.00 5.10379 -154.62 -5.10379 5.10379 0.32 0.000745353 0.000692519 0.0442067 0.0410231 -1 -1 -1 -1 30 2528 23 6.64007e+06 401856 526063. 1820.29 0.56 0.134313 0.118402 22546 126617 -1 2128 20 1112 1738 94826 23161 4.27288 4.27288 -144.151 -4.27288 0 0 666494. 2306.21 0.04 0.08 0.11 -1 -1 0.04 0.0377662 0.0337785 167 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.73 vpr 62.80 MiB -1 -1 0.26 18420 1 0.03 -1 -1 30316 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 31 32 352 285 1 184 100 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1115 12860 3466 8442 952 62.8 MiB 0.13 0.00 4.70003 -136.748 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23971 3.50942 3.50942 -116.943 -3.50942 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0231839 0.0203345 125 27 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.03 vpr 63.46 MiB -1 -1 0.27 18732 1 0.03 -1 -1 30432 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 457 356 1 223 107 17 17 289 -1 unnamed_device 24.6 MiB 0.16 1312 16552 4366 10580 1606 63.5 MiB 0.18 0.00 5.1085 -163.706 -5.1085 5.1085 0.32 0.000866276 0.000805627 0.0599784 0.0556569 -1 -1 -1 -1 26 3108 25 6.64007e+06 539994 477104. 1650.88 0.74 0.169209 0.149122 21682 110474 -1 2610 21 1586 2418 149034 35187 4.18489 4.18489 -152.922 -4.18489 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0364613 0.0317981 176 87 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.51 vpr 62.67 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30204 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 23.4 MiB 0.08 705 8213 2081 5243 889 62.7 MiB 0.08 0.00 3.75024 -98.8591 -3.75024 3.75024 0.32 0.0005679 0.000526595 0.0263248 0.0244408 -1 -1 -1 -1 32 1549 22 6.64007e+06 288834 554710. 1919.41 0.53 0.100546 0.0878178 22834 132086 -1 1406 19 899 1604 92734 23078 2.74057 2.74057 -95.4429 -2.74057 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0216482 0.0188058 104 28 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 2.78 vpr 62.98 MiB -1 -1 0.25 18292 1 0.03 -1 -1 30248 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 24.0 MiB 0.22 1232 11863 3185 7621 1057 63.0 MiB 0.13 0.00 5.0773 -152.378 -5.0773 5.0773 0.32 0.000685702 0.000638075 0.0388617 0.0361442 -1 -1 -1 -1 30 2607 19 6.64007e+06 426972 526063. 1820.29 0.54 0.117632 0.103629 22546 126617 -1 2248 21 1248 1852 100468 23985 3.96729 3.96729 -135.475 -3.96729 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0289625 0.0253341 149 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.99 vpr 62.95 MiB -1 -1 0.17 18472 1 0.03 -1 -1 30352 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64456 32 32 349 284 1 183 102 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1221 11764 2967 7709 1088 62.9 MiB 0.12 0.00 3.95307 -117.525 -3.95307 3.95307 0.32 0.000696024 0.000644408 0.0366916 0.0340243 -1 -1 -1 -1 22 3240 30 6.64007e+06 477204 420624. 1455.45 0.98 0.131608 0.11527 20818 92861 -1 2548 19 1326 2488 176484 42475 3.19957 3.19957 -118.379 -3.19957 0 0 500653. 1732.36 0.02 0.07 0.08 -1 -1 0.02 0.0262585 0.0229142 137 53 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 2.58 vpr 62.59 MiB -1 -1 0.23 17800 1 0.03 -1 -1 30212 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64096 32 32 291 230 1 168 91 17 17 289 -1 unnamed_device 23.5 MiB 0.07 900 13147 4476 6141 2530 62.6 MiB 0.13 0.00 4.20356 -122.292 -4.20356 4.20356 0.31 0.000620913 0.00057678 0.0422596 0.0392478 -1 -1 -1 -1 32 2124 24 6.64007e+06 339066 554710. 1919.41 0.57 0.118883 0.104795 22834 132086 -1 1774 20 1016 2010 121136 29266 3.34003 3.34003 -110.91 -3.34003 0 0 701300. 2426.64 0.03 0.06 0.12 -1 -1 0.03 0.0252076 0.0219955 127 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.84 vpr 63.38 MiB -1 -1 0.23 18376 1 0.03 -1 -1 30420 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64904 32 32 353 287 1 198 94 17 17 289 -1 unnamed_device 23.8 MiB 0.24 1217 9679 2220 6521 938 63.4 MiB 0.12 0.00 4.87535 -142.566 -4.87535 4.87535 0.32 0.00070198 0.000652914 0.0343575 0.0319558 -1 -1 -1 -1 28 2610 19 6.64007e+06 376740 500653. 1732.36 0.55 0.115739 0.101618 21970 115934 -1 2275 19 1225 1679 117927 28569 3.29983 3.29983 -124.736 -3.29983 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0264037 0.0231204 142 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 2.88 vpr 62.88 MiB -1 -1 0.24 18384 1 0.03 -1 -1 30292 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 32 32 361 291 1 185 103 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1032 10466 2519 7358 589 62.9 MiB 0.11 0.00 3.87166 -121.484 -3.87166 3.87166 0.33 0.000728678 0.00067732 0.03387 0.0314019 -1 -1 -1 -1 26 2492 21 6.64007e+06 489762 477104. 1650.88 0.70 0.123703 0.108661 21682 110474 -1 2122 22 1168 2158 142549 33751 3.01017 3.01017 -112.725 -3.01017 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0306578 0.0267168 139 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.92 vpr 63.10 MiB -1 -1 0.26 18372 1 0.03 -1 -1 30420 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 23.9 MiB 0.13 1185 14744 3959 8963 1822 63.1 MiB 0.15 0.00 4.29207 -132.639 -4.29207 4.29207 0.32 0.000732956 0.000680596 0.0468908 0.0434674 -1 -1 -1 -1 28 2570 18 6.64007e+06 502320 500653. 1732.36 0.59 0.13304 0.117512 21970 115934 -1 2290 20 1435 2358 148680 35355 3.36377 3.36377 -121.085 -3.36377 0 0 612192. 2118.31 0.03 0.10 0.14 -1 -1 0.03 0.0322143 0.0281537 149 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 2.45 vpr 62.71 MiB -1 -1 0.14 18284 1 0.03 -1 -1 30308 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64216 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 23.6 MiB 0.07 1023 10540 2564 7150 826 62.7 MiB 0.10 0.00 4.27093 -125.084 -4.27093 4.27093 0.30 0.000635854 0.000590624 0.0312502 0.0290072 -1 -1 -1 -1 32 2034 20 6.64007e+06 452088 554710. 1919.41 0.53 0.105906 0.0929137 22834 132086 -1 1819 20 1043 1996 118484 27523 3.47223 3.47223 -116.792 -3.47223 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0255077 0.0222584 127 24 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.67 vpr 62.80 MiB -1 -1 0.14 18480 1 0.03 -1 -1 30144 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 319 257 1 198 93 17 17 289 -1 unnamed_device 23.8 MiB 0.21 1094 10173 2429 6748 996 62.8 MiB 0.11 0.00 5.10621 -136.906 -5.10621 5.10621 0.32 0.000655901 0.000609938 0.0340695 0.0316782 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0.08 0.10 -1 -1 0.03 0.0299494 0.0260903 152 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.73 vpr 62.93 MiB -1 -1 0.19 18476 1 0.03 -1 -1 30188 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 32 32 387 315 1 189 89 17 17 289 -1 unnamed_device 23.8 MiB 0.15 1136 14147 4526 7649 1972 62.9 MiB 0.16 0.00 4.38816 -135.074 -4.38816 4.38816 0.32 0.000743004 0.000687682 0.0564022 0.052172 -1 -1 -1 -1 30 2565 21 6.64007e+06 313950 526063. 1820.29 0.59 0.145234 0.128316 22546 126617 -1 2247 16 1212 2170 142450 32357 3.63163 3.63163 -128.953 -3.63163 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0246587 0.0216156 141 77 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.63 vpr 63.07 MiB -1 -1 0.22 18120 1 0.03 -1 -1 30300 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 251 219 1 140 94 17 17 289 -1 unnamed_device 23.3 MiB 0.08 923 15643 4702 9042 1899 63.1 MiB 0.13 0.00 3.5543 -104.7 -3.5543 3.5543 0.32 0.00055848 0.000519887 0.0433436 0.0403444 -1 -1 -1 -1 28 1834 21 6.64007e+06 376740 500653. 1732.36 0.56 0.108027 0.0957526 21970 115934 -1 1668 22 937 1393 89639 21079 2.65657 2.65657 -97.5617 -2.65657 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.0239942 0.0208508 101 23 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.67 vpr 63.50 MiB -1 -1 0.16 18272 1 0.03 -1 -1 30040 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65020 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 23.9 MiB 0.19 1003 17023 5521 9148 2354 63.5 MiB 0.17 0.00 4.05053 -136.563 -4.05053 4.05053 0.32 0.000667134 0.000619094 0.0589093 0.0547082 -1 -1 -1 -1 32 2363 20 6.64007e+06 339066 554710. 1919.41 0.56 0.140709 0.125069 22834 132086 -1 2016 20 1250 1804 125844 29633 3.39003 3.39003 -130.188 -3.39003 0 0 701300. 2426.64 0.03 0.07 0.09 -1 -1 0.03 0.02694 0.0234839 133 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.84 vpr 62.91 MiB -1 -1 0.26 18464 1 0.03 -1 -1 30344 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 387 293 1 234 99 17 17 289 -1 unnamed_device 24.0 MiB 0.21 1435 16059 4481 10134 1444 62.9 MiB 0.17 0.00 5.58406 -162.308 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27017 2.85617 2.85617 -116.634 -2.85617 0 0 701300. 2426.64 0.03 0.07 0.10 -1 -1 0.03 0.0294348 0.0256088 141 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.47 vpr 62.55 MiB -1 -1 0.24 18040 1 0.03 -1 -1 30292 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 23.5 MiB 0.05 787 15647 4513 8348 2786 62.6 MiB 0.13 0.00 3.51327 -106.246 -3.51327 3.51327 0.32 0.000603837 0.000561213 0.0453604 0.0421794 -1 -1 -1 -1 32 1767 19 6.64007e+06 414414 554710. 1919.41 0.51 0.113315 0.100197 22834 132086 -1 1434 19 732 1177 64731 16326 2.73257 2.73257 -98.3112 -2.73257 0 0 701300. 2426.64 0.03 0.04 0.12 -1 -1 0.03 0.0169393 0.0148555 111 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.53 vpr 63.23 MiB -1 -1 0.26 18632 1 0.03 -1 -1 30244 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64744 32 32 431 332 1 235 97 17 17 289 -1 unnamed_device 24.4 MiB 0.31 1370 17635 5043 10114 2478 63.2 MiB 0.21 0.00 6.37067 -183.955 -6.37067 6.37067 0.32 0.000827281 0.000769095 0.0686146 0.0637394 -1 -1 -1 -1 26 3739 28 6.64007e+06 414414 477104. 1650.88 1.06 0.183963 0.163024 21682 110474 -1 2914 23 2106 3156 231468 52338 5.05174 5.05174 -171.67 -5.05174 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0364787 0.031749 177 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.78 vpr 62.80 MiB -1 -1 0.24 18536 1 0.03 -1 -1 30456 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1059 19142 5710 10959 2473 62.8 MiB 0.17 0.00 4.53287 -137.071 -4.53287 4.53287 0.35 0.000694142 0.000645825 0.0585836 0.0543714 -1 -1 -1 -1 32 2159 21 6.64007e+06 477204 554710. 1919.41 0.56 0.141425 0.1254 22834 132086 -1 1899 16 1017 1621 90851 21605 3.65443 3.65443 -127.571 -3.65443 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0232201 0.0203952 136 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.57 vpr 62.96 MiB -1 -1 0.21 17880 1 0.05 -1 -1 30276 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 231 199 1 140 93 17 17 289 -1 unnamed_device 23.4 MiB 0.06 697 14793 4064 8312 2417 63.0 MiB 0.12 0.00 3.58247 -96.388 -3.58247 3.58247 0.34 0.000536007 0.000498696 0.0399856 0.0372164 -1 -1 -1 -1 30 1597 22 6.64007e+06 364182 526063. 1820.29 0.51 0.104438 0.0921129 22546 126617 -1 1300 17 603 1018 57376 14793 2.68557 2.68557 -89.2135 -2.68557 0 0 666494. 2306.21 0.03 0.05 0.09 -1 -1 0.03 0.0188683 0.0164977 103 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.72 vpr 63.45 MiB -1 -1 0.13 18472 1 0.03 -1 -1 30204 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1247 19624 5520 11864 2240 63.4 MiB 0.19 0.00 5.68826 -140.03 -5.68826 5.68826 0.39 0.000705253 0.000655769 0.0593179 0.0551102 -1 -1 -1 -1 32 2366 18 6.64007e+06 502320 554710. 1919.41 0.54 0.139797 0.12415 22834 132086 -1 2129 14 824 1693 109078 25009 4.42708 4.42708 -129.323 -4.42708 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.021665 0.0190537 147 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.60 vpr 62.49 MiB -1 -1 0.22 17892 1 0.03 -1 -1 30152 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63992 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 23.2 MiB 0.07 838 15831 5106 8362 2363 62.5 MiB 0.13 0.00 3.5273 -107.609 -3.5273 3.5273 0.34 0.000557504 0.000519197 0.0480485 0.0446917 -1 -1 -1 -1 28 1874 20 6.64007e+06 288834 500653. 1732.36 0.55 0.114684 0.101665 21970 115934 -1 1689 20 1084 1860 116033 27873 2.77177 2.77177 -103.603 -2.77177 0 0 612192. 2118.31 0.03 0.06 0.11 -1 -1 0.03 0.0221893 0.0192968 107 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.88 vpr 62.60 MiB -1 -1 0.26 18212 1 0.02 -1 -1 30088 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 23.5 MiB 0.11 893 14252 4195 7695 2362 62.6 MiB 0.12 0.00 4.06561 -110.624 -4.06561 4.06561 0.32 0.000598189 0.000554889 0.0387015 0.0359501 -1 -1 -1 -1 28 2003 16 6.64007e+06 477204 500653. 1732.36 0.52 0.105135 0.0927138 21970 115934 -1 1666 21 1086 2090 130293 30391 2.82057 2.82057 -103.094 -2.82057 0 0 612192. 2118.31 0.03 0.07 0.13 -1 -1 0.03 0.0242583 0.0209963 110 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 2.80 vpr 62.91 MiB -1 -1 0.23 18388 1 0.03 -1 -1 30260 -1 -1 32 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64424 29 32 355 287 1 198 93 17 17 289 -1 unnamed_device 23.9 MiB 0.21 964 10173 2395 7060 718 62.9 MiB 0.11 0.00 4.65946 -131.109 -4.65946 4.65946 0.31 0.000693587 0.000645337 0.0360007 0.0334599 -1 -1 -1 -1 28 2771 28 6.64007e+06 401856 500653. 1732.36 0.68 0.125412 0.10974 21970 115934 -1 2174 20 1456 2237 139279 35165 3.62642 3.62642 -121.356 -3.62642 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0276567 0.0241107 146 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 2.60 vpr 62.84 MiB -1 -1 0.17 18284 1 0.03 -1 -1 30432 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64348 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 23.8 MiB 0.11 925 11719 2758 8119 842 62.8 MiB 0.12 0.00 4.42033 -138.276 -4.42033 4.42033 0.32 0.00071589 0.000664168 0.0433359 0.0402562 -1 -1 -1 -1 32 2161 23 6.64007e+06 339066 554710. 1919.41 0.57 0.129395 0.113987 22834 132086 -1 1727 20 1284 1944 114196 28932 3.78702 3.78702 -131.455 -3.78702 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0279344 0.02439 135 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.92 vpr 62.80 MiB -1 -1 0.21 18364 1 0.03 -1 -1 30232 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1091 11798 3080 7487 1231 62.8 MiB 0.13 0.00 4.78258 -142.686 -4.78258 4.78258 0.32 0.000714923 0.00066408 0.0396764 0.0368336 -1 -1 -1 -1 32 2192 17 6.64007e+06 426972 554710. 1919.41 0.80 0.12021 0.105957 22834 132086 -1 2011 16 897 1626 93283 22441 3.62362 3.62362 -128.218 -3.62362 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0237017 0.020821 136 51 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.70 vpr 62.63 MiB -1 -1 0.23 18024 1 0.03 -1 -1 30240 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64136 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 23.5 MiB 0.22 888 6701 1459 4931 311 62.6 MiB 0.08 0.00 4.75515 -130.083 -4.75515 4.75515 0.32 0.00061059 0.000568906 0.023214 0.021603 -1 -1 -1 -1 32 1842 19 6.64007e+06 276276 554710. 1919.41 0.51 0.0918828 0.0803618 22834 132086 -1 1618 15 639 896 58501 14060 3.29883 3.29883 -115.297 -3.29883 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0190421 0.0167372 107 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 3.10 vpr 63.02 MiB -1 -1 0.24 18248 1 0.03 -1 -1 30368 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 31 32 319 272 1 169 88 17 17 289 -1 unnamed_device 23.9 MiB 0.18 793 16078 4554 9333 2191 63.0 MiB 0.15 0.00 4.00036 -122.569 -4.00036 4.00036 0.35 0.000662037 0.000616691 0.0553256 0.0514457 -1 -1 -1 -1 26 2534 43 6.64007e+06 313950 477104. 1650.88 0.88 0.155968 0.137486 21682 110474 -1 1828 21 1216 1787 118458 32053 3.24903 3.24903 -118.128 -3.24903 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0261712 0.0227742 117 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.80 vpr 63.27 MiB -1 -1 0.23 18488 1 0.03 -1 -1 30384 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64788 30 32 329 273 1 166 98 17 17 289 -1 unnamed_device 23.5 MiB 0.10 943 16973 4825 9365 2783 63.3 MiB 0.16 0.00 3.65867 -98.2101 -3.65867 3.65867 0.36 0.000510479 0.000470115 0.0491293 0.0452299 -1 -1 -1 -1 26 2242 21 6.64007e+06 452088 477104. 1650.88 0.67 0.122474 0.109111 21682 110474 -1 1867 18 917 1784 103434 25819 2.77377 2.77377 -96.2306 -2.77377 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0239279 0.0208916 128 57 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.56 vpr 62.76 MiB -1 -1 0.22 18036 1 0.03 -1 -1 30368 -1 -1 39 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 28 32 277 229 1 155 99 17 17 289 -1 unnamed_device 23.6 MiB 0.07 826 16971 4935 9183 2853 62.8 MiB 0.13 0.00 4.21293 -101.023 -4.21293 4.21293 0.33 0.000596135 0.000555002 0.0460918 0.0427488 -1 -1 -1 -1 28 1907 22 6.64007e+06 489762 500653. 1732.36 0.56 0.117192 0.10326 21970 115934 -1 1601 16 895 1627 90491 22777 3.47223 3.47223 -98.8073 -3.47223 0 0 612192. 2118.31 0.02 0.05 0.07 -1 -1 0.02 0.0195628 0.0171324 122 27 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 2.69 vpr 62.73 MiB -1 -1 0.24 18280 1 0.03 -1 -1 30360 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64232 30 32 317 269 1 152 84 17 17 289 -1 unnamed_device 23.6 MiB 0.13 892 13809 4602 7006 2201 62.7 MiB 0.14 0.00 3.90078 -115.622 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64380 32 32 385 308 1 182 101 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1057 12556 3111 8883 562 62.9 MiB 0.13 0.00 4.57304 -141.272 -4.57304 4.57304 0.31 0.000744694 0.000690509 0.0434462 0.0401677 -1 -1 -1 -1 32 2404 16 6.64007e+06 464646 554710. 1919.41 0.58 0.125349 0.110487 22834 132086 -1 2052 22 1123 2086 137496 32021 3.42483 3.42483 -130.344 -3.42483 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.029294 0.0260026 143 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 3.17 vpr 63.51 MiB -1 -1 0.26 18504 1 0.03 -1 -1 30284 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 387 309 1 190 107 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1171 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 23.8 MiB 0.19 1123 13148 3656 8360 1132 62.8 MiB 0.13 0.00 5.23915 -149.423 -5.23915 5.23915 0.31 0.000682659 0.00063482 0.0427424 0.0397167 -1 -1 -1 -1 32 2371 21 6.64007e+06 439530 554710. 1919.41 0.54 0.123323 0.108794 22834 132086 -1 2007 20 1118 1785 91779 24235 4.30908 4.30908 -140.1 -4.30908 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0272733 0.0238268 151 47 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 2.71 vpr 62.93 MiB -1 -1 0.16 18440 1 0.03 -1 -1 30492 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64440 30 32 377 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 23.9 MiB 0.20 1044 14235 4068 7633 2534 63.0 MiB 0.16 0.00 4.71503 -140.381 -4.71503 4.71503 0.32 0.000736638 0.000684303 0.0542958 0.0503407 -1 -1 -1 -1 32 2187 20 6.64007e+06 439530 554710. 1919.41 0.64 0.16213 0.14341 22834 132086 -1 1906 20 1054 1793 106697 26383 3.63163 3.63163 -128.238 -3.63163 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0285345 0.0249014 135 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 2.91 vpr 62.84 MiB -1 -1 0.16 18280 1 0.03 -1 -1 30280 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 23.8 MiB 0.15 1159 10979 2643 7096 1240 62.8 MiB 0.13 0.00 4.8332 -152.333 -4.8332 4.8332 0.31 0.000764668 0.000709401 0.0465756 0.0431972 -1 -1 -1 -1 32 2514 24 6.64007e+06 313950 554710. 1919.41 0.63 0.140961 0.124202 22834 132086 -1 2265 22 1721 2851 169988 41091 3.69343 3.69343 -141.542 -3.69343 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0324477 0.0282823 155 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 2.86 vpr 62.62 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30408 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64128 32 32 269 231 1 170 89 17 17 289 -1 unnamed_device 23.6 MiB 0.19 1035 13157 3525 7788 1844 62.6 MiB 0.12 0.00 4.01361 -116.472 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 32 32 349 260 1 204 107 17 17 289 -1 unnamed_device 23.8 MiB 0.08 1267 17817 5114 10804 1899 63.5 MiB 0.17 0.00 5.50127 -148.27 -5.50127 5.50127 0.32 0.000728707 0.000677247 0.0534885 0.0496414 -1 -1 -1 -1 26 3165 21 6.64007e+06 539994 477104. 1650.88 0.75 0.150128 0.133373 21682 110474 -1 2620 21 1637 3007 196047 46131 4.58248 4.58248 -146.607 -4.58248 0 0 585099. 2024.56 0.03 0.09 0.09 -1 -1 0.03 0.0303632 0.0265432 162 3 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 2.47 vpr 63.33 MiB -1 -1 0.16 18544 1 0.03 -1 -1 30320 -1 -1 35 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 30 32 316 264 1 162 97 17 17 289 -1 unnamed_device 23.6 MiB 0.11 960 10531 2688 6948 895 63.3 MiB 0.10 0.00 3.53527 -104.629 -3.53527 3.53527 0.31 0.000642209 0.000597715 0.0327903 0.0304946 -1 -1 -1 -1 32 2029 21 6.64007e+06 439530 554710. 1919.41 0.53 0.108188 0.0949357 22834 132086 -1 1762 19 983 1688 92821 22824 2.84297 2.84297 -99.6625 -2.84297 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0302453 0.0267024 124 52 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 2.41 vpr 62.96 MiB -1 -1 0.21 18040 1 0.04 -1 -1 30284 -1 -1 25 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64472 27 32 255 219 1 132 84 17 17 289 -1 unnamed_device 23.4 MiB 0.06 787 11430 3535 6029 1866 63.0 MiB 0.09 0.00 3.4653 -96.8105 -3.4653 3.4653 0.31 0.000547949 0.000510433 0.0361061 0.0336224 -1 -1 -1 -1 26 1657 21 6.64007e+06 313950 477104. 1650.88 0.51 0.100455 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 331 280 1 174 87 17 17 289 -1 unnamed_device 23.5 MiB 0.29 989 13335 4742 6776 1817 62.7 MiB 0.13 0.00 4.37915 -137.641 -4.37915 4.37915 0.32 0.000658109 0.000611873 0.048245 0.0448417 -1 -1 -1 -1 32 1903 19 6.64007e+06 288834 554710. 1919.41 0.52 0.124693 0.110299 22834 132086 -1 1693 13 628 883 56758 13715 3.17522 3.17522 -121.439 -3.17522 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0196211 0.017333 130 65 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.90 vpr 63.40 MiB -1 -1 0.24 18384 1 0.03 -1 -1 30344 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1105 13092 3416 8740 936 63.4 MiB 0.13 0.00 5.28888 -136.917 -5.28888 5.28888 0.32 0.000682744 0.000636151 0.0406021 0.0377399 -1 -1 -1 -1 26 2483 21 6.64007e+06 452088 477104. 1650.88 0.57 0.121401 0.10708 21682 110474 -1 2105 18 1009 1726 98465 23986 3.85982 3.85982 -125.513 -3.85982 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0247052 0.0216352 133 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.03 vpr 63.57 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30372 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 31 32 373 294 1 196 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1122 12321 3316 8274 731 63.6 MiB 0.13 0.00 4.92332 -128.094 -4.92332 4.92332 0.34 0.00073579 0.000681292 0.0411424 0.0381693 -1 -1 -1 -1 26 2511 21 6.64007e+06 477204 477104. 1650.88 0.52 0.127987 0.112686 21682 110474 -1 2210 19 1199 1943 114142 28132 3.83382 3.83382 -125.259 -3.83382 0 0 585099. 2024.56 0.03 0.07 0.08 -1 -1 0.03 0.0283169 0.0247367 151 50 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 2.79 vpr 63.06 MiB -1 -1 0.21 18440 1 0.03 -1 -1 30380 -1 -1 36 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 30 32 325 268 1 171 98 17 17 289 -1 unnamed_device 23.9 MiB 0.12 937 16973 5746 8109 3118 63.1 MiB 0.15 0.00 3.65167 -103.348 -3.65167 3.65167 0.31 0.000656815 0.000608992 0.0517459 0.048035 -1 -1 -1 -1 30 2391 26 6.64007e+06 452088 526063. 1820.29 0.71 0.136006 0.120034 22546 126617 -1 1842 21 1098 2007 113299 28167 2.97317 2.97317 -100.808 -2.97317 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 23.8 MiB 0.13 1118 16856 4639 9867 2350 63.5 MiB 0.19 0.00 4.29207 -131.028 -4.29207 4.29207 0.31 0.000745147 0.000691805 0.0590137 0.0547729 -1 -1 -1 -1 28 2771 25 6.64007e+06 527436 500653. 1732.36 0.64 0.152811 0.135193 21970 115934 -1 2232 22 1473 2458 171773 41912 3.24756 3.24756 -122.119 -3.24756 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0326766 0.0284409 151 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.35 vpr 62.91 MiB -1 -1 0.23 18128 1 0.02 -1 -1 30284 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 23.4 MiB 0.06 778 14184 4385 8482 1317 62.9 MiB 0.12 0.00 4.07075 -112.667 -4.07075 4.07075 0.32 0.000580699 0.000540923 0.0493007 0.0459016 -1 -1 -1 -1 28 1504 20 6.64007e+06 238602 500653. 1732.36 0.47 0.116766 0.103529 21970 115934 -1 1377 18 774 1155 75021 18193 2.75077 2.75077 -97.232 -2.75077 0 0 612192. 2118.31 0.03 0.05 0.07 -1 -1 0.03 0.020975 0.0182859 93 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.71 vpr 62.80 MiB -1 -1 0.24 18332 1 0.03 -1 -1 30448 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 310 266 1 176 89 17 17 289 -1 unnamed_device 23.7 MiB 0.18 1008 13949 3776 8315 1858 62.8 MiB 0.13 0.00 4.57978 -129.405 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 31 32 373 300 1 181 103 17 17 289 -1 unnamed_device 24.2 MiB 0.12 994 11671 2882 8064 725 63.2 MiB 0.12 0.00 4.09378 -121.668 -4.09378 4.09378 0.32 0.000726427 0.000674778 0.0377137 0.034953 -1 -1 -1 -1 26 2376 23 6.64007e+06 502320 477104. 1650.88 0.55 0.125439 0.109976 21682 110474 -1 1958 22 1532 2565 145610 36094 3.06217 3.06217 -117.244 -3.06217 0 0 585099. 2024.56 0.05 0.08 0.10 -1 -1 0.05 0.0315397 0.0275332 141 64 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.73 vpr 62.66 MiB -1 -1 0.23 18040 1 0.03 -1 -1 30328 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 23.7 MiB 0.16 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64152 32 32 290 244 1 177 90 17 17 289 -1 unnamed_device 23.5 MiB 0.19 925 8532 1785 6264 483 62.6 MiB 0.09 0.00 4.36984 -131.165 -4.36984 4.36984 0.31 0.00061324 0.000570288 0.0280339 0.026075 -1 -1 -1 -1 28 2708 24 6.64007e+06 326508 500653. 1732.36 0.64 0.104096 0.0910882 21970 115934 -1 1954 20 1359 2003 122646 30886 3.38923 3.38923 -122.625 -3.38923 0 0 612192. 2118.31 0.02 0.04 0.07 -1 -1 0.02 0.0135228 0.0119375 124 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.77 vpr 62.77 MiB -1 -1 0.23 18380 1 0.03 -1 -1 30208 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 32 32 318 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 412 334 1 190 101 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1132 12791 3491 8287 1013 63.7 MiB 0.15 0.00 4.42516 -144.482 -4.42516 4.42516 0.32 0.000777421 0.000722358 0.0449905 0.0417837 -1 -1 -1 -1 32 2175 23 6.64007e+06 464646 554710. 1919.41 0.56 0.138643 0.121972 22834 132086 -1 1928 20 1161 1813 106830 26306 3.76183 3.76183 -135.978 -3.76183 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0308308 0.0269198 146 90 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.52 vpr 62.92 MiB -1 -1 0.16 18316 1 0.03 -1 -1 30184 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 32 32 376 318 1 155 82 17 17 289 -1 unnamed_device 23.7 MiB 0.14 961 14678 5153 7870 1655 62.9 MiB 0.15 0.00 3.5251 -126.262 -3.5251 3.5251 0.32 0.000716805 0.000665017 0.061699 0.0573065 -1 -1 -1 -1 32 1789 17 6.64007e+06 226044 554710. 1919.41 0.53 0.141368 0.125423 22834 132086 -1 1636 19 1061 1511 101615 23343 2.65957 2.65957 -115.251 -2.65957 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0272319 0.0237407 116 96 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.68 vpr 63.50 MiB -1 -1 0.15 18392 1 0.03 -1 -1 30252 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 23.8 MiB 0.14 1040 16059 4498 9094 2467 63.5 MiB 0.16 0.00 4.08563 -122.248 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2.45 vpr 62.72 MiB -1 -1 0.23 18136 1 0.03 -1 -1 30324 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 23.3 MiB 0.06 689 6731 1618 4756 357 62.7 MiB 0.08 0.00 4.09512 -115.35 -4.09512 4.09512 0.32 0.000599086 0.000557828 0.0252094 0.023468 -1 -1 -1 -1 30 1441 21 6.64007e+06 238602 526063. 1820.29 0.50 0.0996073 0.0873472 22546 126617 -1 1294 18 678 1174 70897 17025 2.86577 2.86577 -104.274 -2.86577 0 0 666494. 2306.21 0.03 0.05 0.11 -1 -1 0.03 0.0219962 0.0192113 95 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 2.63 vpr 62.67 MiB -1 -1 0.22 18180 1 0.03 -1 -1 30216 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64172 32 32 296 247 1 157 90 17 17 289 -1 unnamed_device 23.6 MiB 0.08 942 12552 3467 7974 1111 62.7 MiB 0.12 0.00 3.49427 -115.718 -3.49427 3.49427 0.32 0.000632151 0.000578248 0.041451 0.0384616 -1 -1 -1 -1 32 2080 20 6.64007e+06 326508 554710. 1919.41 0.62 0.114609 0.101229 22834 132086 -1 1868 22 1056 2009 127408 29897 2.69957 2.69957 -109.166 -2.69957 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0268929 0.0233414 119 34 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.61 vpr 62.79 MiB -1 -1 0.22 18028 1 0.03 -1 -1 30192 -1 -1 31 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64296 25 32 216 194 1 122 88 17 17 289 -1 unnamed_device 23.3 MiB 0.06 601 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 30 32 363 293 1 196 92 17 17 289 -1 unnamed_device 23.7 MiB 0.09 1161 17066 4950 10267 1849 63.4 MiB 0.18 0.00 4.92316 -142.534 -4.92316 4.92316 0.32 0.000711495 0.000661377 0.0607483 0.05633 -1 -1 -1 -1 32 2317 19 6.65987e+06 380340 554710. 1919.41 0.56 0.14224 0.126171 22834 132086 -1 2201 20 1285 1969 141789 31778 3.96643 3.96643 -135.327 -3.96643 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0286017 0.0250073 147 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.92 vpr 62.58 MiB -1 -1 0.23 18252 1 0.03 -1 -1 30424 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 32 32 299 247 1 188 95 17 17 289 -1 unnamed_device 23.4 MiB 0.10 1005 7223 1515 5389 319 62.6 MiB 0.08 0.00 4.5072 -115.093 -4.5072 4.5072 0.32 0.000638459 0.000593954 0.023343 0.021723 -1 -1 -1 -1 26 2482 19 6.65987e+06 393018 477104. 1650.88 0.57 0.096452 0.084355 21682 110474 -1 2175 22 1225 1807 128173 38231 3.65077 3.65077 -115.591 -3.65077 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0283391 0.0248207 129 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.43 vpr 63.12 MiB -1 -1 0.17 18364 1 0.04 -1 -1 30272 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 29 32 308 248 1 169 92 17 17 289 -1 unnamed_device 23.3 MiB 0.04 1008 16445 5063 9076 2306 63.1 MiB 0.16 0.00 4.28955 -115.789 -4.28955 4.28955 0.31 0.000630792 0.000586242 0.0527628 0.0490015 -1 -1 -1 -1 32 2107 21 6.65987e+06 393018 554710. 1919.41 0.54 0.127475 0.112807 22834 132086 -1 1923 24 1162 2468 162514 37920 3.42191 3.42191 -111.417 -3.42191 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0300343 0.0260368 132 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.88 vpr 62.64 MiB -1 -1 0.23 18404 1 0.03 -1 -1 30412 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64144 32 32 336 268 1 174 92 17 17 289 -1 unnamed_device 23.6 MiB 0.06 926 17066 4722 10092 2252 62.6 MiB 0.18 0.00 4.32246 -124.084 -4.32246 4.32246 0.31 0.000682381 0.000633432 0.0584903 0.0542653 -1 -1 -1 -1 28 2659 35 6.65987e+06 354984 500653. 1732.36 0.85 0.156528 0.138194 21970 115934 -1 1952 22 1359 2592 155691 39529 3.65631 3.65631 -123.935 -3.65631 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0292856 0.0255564 134 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.51 vpr 62.75 MiB -1 -1 0.15 18452 1 0.03 -1 -1 30268 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64252 32 32 366 295 1 189 103 17 17 289 -1 unnamed_device 23.6 MiB 0.08 1006 10707 2558 7056 1093 62.7 MiB 0.11 0.00 3.2981 -110.874 -3.2981 3.2981 0.32 0.000715102 0.000664192 0.0344872 0.0320276 -1 -1 -1 -1 32 2059 17 6.65987e+06 494442 554710. 1919.41 0.52 0.114776 0.10094 22834 132086 -1 1766 16 1009 1653 81293 21469 2.93011 2.93011 -107.664 -2.93011 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0244838 0.0214969 145 58 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 2.33 vpr 62.35 MiB -1 -1 0.16 18212 1 0.03 -1 -1 30572 -1 -1 21 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63844 27 32 259 221 1 130 80 17 17 289 -1 unnamed_device 23.0 MiB 0.05 662 8508 2183 5532 793 62.3 MiB 0.08 0.00 3.64612 -97.2036 -3.64612 3.64612 0.32 0.000556352 0.000518731 0.02948 0.0274761 -1 -1 -1 -1 26 1488 20 6.65987e+06 266238 477104. 1650.88 0.46 0.0948889 0.0832974 21682 110474 -1 1285 19 839 1443 84061 21350 2.55211 2.55211 -89.8292 -2.55211 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0217986 0.0189775 97 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 2.55 vpr 62.41 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30072 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63904 31 32 271 219 1 162 98 17 17 289 -1 unnamed_device 23.4 MiB 0.05 879 17198 5694 8745 2759 62.4 MiB 0.14 0.00 3.28184 -95.5565 -3.28184 3.28184 0.36 0.000595736 0.000552841 0.0478346 0.044364 -1 -1 -1 -1 32 2096 17 6.65987e+06 443730 554710. 1919.41 0.52 0.110623 0.0981322 22834 132086 -1 1775 20 943 1802 114464 28225 2.55445 2.55445 -90.648 -2.55445 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0241442 0.0210605 123 4 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 2.40 vpr 62.57 MiB -1 -1 0.15 18384 1 0.03 -1 -1 30052 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 31 32 317 271 1 168 87 17 17 289 -1 unnamed_device 23.4 MiB 0.09 925 6807 1453 4944 410 62.6 MiB 0.08 0.00 3.3699 -114.313 -3.3699 3.3699 0.32 0.000493922 0.000454414 0.024486 0.0227415 -1 -1 -1 -1 28 2084 19 6.65987e+06 304272 500653. 1732.36 0.51 0.0981972 0.0857413 21970 115934 -1 1840 15 921 1353 95741 23607 2.83031 2.83031 -109.983 -2.83031 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0207326 0.0181803 117 64 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 2.56 vpr 62.51 MiB -1 -1 0.22 18156 1 0.03 -1 -1 30016 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 32 32 298 248 1 156 83 17 17 289 -1 unnamed_device 23.4 MiB 0.09 817 6383 1432 4490 461 62.5 MiB 0.08 0.00 3.76232 -120.722 -3.76232 3.76232 0.32 0.000636848 0.000593635 0.024309 0.0226498 -1 -1 -1 -1 26 2054 21 6.65987e+06 240882 477104. 1650.88 0.54 0.0984567 0.0861078 21682 110474 -1 1799 19 1068 1672 105244 26336 2.74751 2.74751 -112.355 -2.74751 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.024046 0.0210051 115 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 2.55 vpr 62.52 MiB -1 -1 0.20 18352 1 0.03 -1 -1 30424 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 30 32 303 262 1 139 81 17 17 289 -1 unnamed_device 23.4 MiB 0.12 855 11106 3144 6574 1388 62.5 MiB 0.10 0.00 3.77152 -110.328 -3.77152 3.77152 0.34 0.000678385 0.000627002 0.0360956 0.0334026 -1 -1 -1 -1 32 1610 20 6.65987e+06 240882 554710. 1919.41 0.50 0.106565 0.093619 22834 132086 -1 1486 18 705 1168 66043 16527 2.64251 2.64251 -96.0214 -2.64251 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0227846 0.019903 101 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.74 vpr 62.46 MiB -1 -1 0.23 18072 1 0.03 -1 -1 30144 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63964 32 32 276 237 1 167 87 17 17 289 -1 unnamed_device 23.4 MiB 0.09 923 15063 4954 7940 2169 62.5 MiB 0.14 0.00 3.60095 -114.988 -3.60095 3.60095 0.32 0.000589529 0.000548359 0.048608 0.0452215 -1 -1 -1 -1 28 2245 30 6.65987e+06 291594 500653. 1732.36 0.75 0.136128 0.120028 21970 115934 -1 1857 21 1021 1396 110915 26979 3.05825 3.05825 -111.367 -3.05825 0 0 612192. 2118.31 0.03 0.06 0.10 -1 -1 0.03 0.024645 0.0214555 111 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 2.79 vpr 62.86 MiB -1 -1 0.24 18380 1 0.08 -1 -1 30308 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 32 32 344 272 1 202 93 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1172 12063 3279 7731 1053 62.9 MiB 0.16 0.00 4.32078 -139.492 -4.32078 4.32078 0.33 0.000703373 0.000645846 0.0505267 0.04694 -1 -1 -1 -1 32 2466 23 6.65987e+06 367662 554710. 1919.41 0.56 0.135329 0.119646 22834 132086 -1 2158 23 1534 2364 144012 35379 3.01857 3.01857 -118.122 -3.01857 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0312134 0.027204 147 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.74 vpr 62.80 MiB -1 -1 0.24 18376 1 0.03 -1 -1 30196 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64308 32 32 363 295 1 181 98 17 17 289 -1 unnamed_device 23.8 MiB 0.10 971 17873 5392 9032 3449 62.8 MiB 0.19 0.00 4.50383 -130.941 -4.50383 4.50383 0.33 0.000717123 0.000666062 0.0669834 0.0620637 -1 -1 -1 -1 32 2088 18 6.65987e+06 431052 554710. 1919.41 0.57 0.148521 0.131949 22834 132086 -1 1825 20 1420 2352 139941 35041 3.57251 3.57251 -121.811 -3.57251 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0286098 0.0250144 139 61 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 2.47 vpr 62.38 MiB -1 -1 0.22 18052 1 0.03 -1 -1 30508 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63872 29 32 248 215 1 137 84 17 17 289 -1 unnamed_device 23.3 MiB 0.10 694 9600 2464 6430 706 62.4 MiB 0.08 0.00 2.92253 -85.631 -2.92253 2.92253 0.32 0.000543549 0.000506216 0.0305384 0.0284177 -1 -1 -1 -1 26 1711 20 6.65987e+06 291594 477104. 1650.88 0.48 0.0942953 0.0827929 21682 110474 -1 1601 22 1045 1797 119370 29179 2.51431 2.51431 -87.2887 -2.51431 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0234018 0.0202863 103 27 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 2.88 vpr 63.29 MiB -1 -1 0.27 18480 1 0.03 -1 -1 30296 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 32 32 370 297 1 183 91 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1152 16003 4822 9403 1778 63.3 MiB 0.16 0.00 4.09572 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64080 31 32 291 243 1 171 88 17 17 289 -1 unnamed_device 23.4 MiB 0.20 786 13738 3441 7180 3117 62.6 MiB 0.12 0.00 4.80308 -136.113 -4.80308 4.80308 0.31 0.000610132 0.000568245 0.0452547 0.0421109 -1 -1 -1 -1 32 2211 46 6.65987e+06 316950 554710. 1919.41 0.80 0.142447 0.124997 22834 132086 -1 1576 21 899 1285 88683 23465 3.84671 3.84671 -129.866 -3.84671 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0258407 0.0225526 127 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 3.39 vpr 63.26 MiB -1 -1 0.23 18456 1 0.03 -1 -1 30396 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 32 32 342 271 1 179 101 17 17 289 -1 unnamed_device 23.6 MiB 0.07 1092 18196 6057 9791 2348 63.3 MiB 0.17 0.00 4.25196 -133.154 -4.25196 4.25196 0.31 0.000696776 0.000647631 0.0565156 0.0524726 -1 -1 -1 -1 28 2596 21 6.65987e+06 469086 500653. 1732.36 0.78 0.140877 0.125047 21970 115934 -1 2180 20 1359 2318 167321 39385 3.69683 3.69683 -128.953 -3.69683 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0280309 0.0245652 140 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 3.33 vpr 62.74 MiB -1 -1 0.25 18336 1 0.03 -1 -1 30284 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64248 32 32 372 300 1 207 95 17 17 289 -1 unnamed_device 23.9 MiB 0.10 1229 17591 4978 10084 2529 62.7 MiB 0.19 0.00 4.43635 -136.819 -4.43635 4.43635 0.31 0.000723595 0.000672722 0.061937 0.0574339 -1 -1 -1 -1 32 2470 18 6.65987e+06 393018 554710. 1919.41 0.54 0.143942 0.127773 22834 132086 -1 2229 19 1285 1974 116123 28589 3.51771 3.51771 -123.874 -3.51771 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0285167 0.0249981 151 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.43 vpr 62.46 MiB -1 -1 0.14 18020 1 0.02 -1 -1 30524 -1 -1 20 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63960 26 32 190 182 1 108 78 17 17 289 -1 unnamed_device 23.1 MiB 0.07 431 10536 3837 3941 2758 62.5 MiB 0.07 0.00 2.35224 -64.6209 -2.35224 2.35224 0.32 0.000426133 0.000395077 0.0283186 0.0262801 -1 -1 -1 -1 28 1419 31 6.65987e+06 253560 500653. 1732.36 0.63 0.086015 0.075317 21970 115934 -1 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 32 32 300 245 1 165 95 17 17 289 -1 unnamed_device 23.5 MiB 0.09 898 10247 2366 7380 501 62.6 MiB 0.10 0.00 4.32789 -118.536 -4.32789 4.32789 0.32 0.000639255 0.000594623 0.0326551 0.0303542 -1 -1 -1 -1 26 2424 21 6.65987e+06 393018 477104. 1650.88 0.66 0.109099 0.0958696 21682 110474 -1 1959 20 1096 1916 134943 33891 3.50931 3.50931 -114.521 -3.50931 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0257508 0.0224904 126 24 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.57 vpr 62.66 MiB -1 -1 0.18 17776 1 0.03 -1 -1 30360 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 32 32 297 233 1 177 103 17 17 289 -1 unnamed_device 23.7 MiB 0.06 986 15527 4364 9095 2068 62.7 MiB 0.15 0.00 3.58941 -102.662 -3.58941 3.58941 0.32 0.00064423 0.000597693 0.0438764 0.0407061 -1 -1 -1 -1 32 2052 20 6.65987e+06 494442 554710. 1919.41 0.53 0.118788 0.104869 22834 132086 -1 1757 21 995 1984 121842 28850 2.78377 2.78377 -93.9889 -2.78377 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0253086 0.0224502 136 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 3.09 vpr 63.31 MiB -1 -1 0.15 18280 1 0.03 -1 -1 30412 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 338 277 1 179 99 17 17 289 -1 unnamed_device 23.7 MiB 0.08 1132 18339 5277 10722 2340 63.3 MiB 0.17 0.00 4.42603 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63936 32 32 253 210 1 154 85 17 17 289 -1 unnamed_device 23.4 MiB 0.07 733 14035 5318 6638 2079 62.4 MiB 0.12 0.00 3.67009 -108.082 -3.67009 3.67009 0.32 0.000572926 0.000532536 0.0451769 0.0419649 -1 -1 -1 -1 32 1862 31 6.65987e+06 266238 554710. 1919.41 0.57 0.122063 0.107575 22834 132086 -1 1508 20 909 1486 90599 23830 2.64951 2.64951 -100.091 -2.64951 0 0 701300. 2426.64 0.04 0.06 0.10 -1 -1 0.04 0.0273808 0.0243873 116 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 2.57 vpr 62.43 MiB -1 -1 0.24 18192 1 0.03 -1 -1 30544 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63928 31 32 271 231 1 148 96 17 17 289 -1 unnamed_device 23.3 MiB 0.06 765 8199 1674 6237 288 62.4 MiB 0.08 0.00 3.38101 -98.7431 -3.38101 3.38101 0.32 0.000579578 0.000540067 0.0238147 0.0221697 -1 -1 -1 -1 26 1967 21 6.65987e+06 418374 477104. 1650.88 0.55 0.0977505 0.0853359 21682 110474 -1 1633 20 906 1519 84512 22222 2.82071 2.82071 -102.673 -2.82071 0 0 585099. 2024.56 0.04 0.06 0.10 -1 -1 0.04 0.0264682 0.0233523 111 30 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.70 vpr 62.84 MiB -1 -1 0.23 18384 1 0.03 -1 -1 30436 -1 -1 31 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 29 32 291 250 1 153 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 919 13961 3585 8809 1567 62.8 MiB 0.12 0.00 3.21564 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 2.53 vpr 62.52 MiB -1 -1 0.22 18272 1 0.03 -1 -1 30232 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 31 32 279 237 1 161 86 17 17 289 -1 unnamed_device 23.4 MiB 0.09 916 12938 4123 6955 1860 62.5 MiB 0.12 0.00 4.11632 -122.804 -4.11632 4.11632 0.32 0.000592092 0.000550918 0.0429113 0.0399086 -1 -1 -1 -1 32 1802 19 6.65987e+06 291594 554710. 1919.41 0.50 0.112424 0.099407 22834 132086 -1 1621 21 899 1293 89858 21635 2.75411 2.75411 -103.631 -2.75411 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0251542 0.0219007 114 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.66 vpr 62.81 MiB -1 -1 0.25 18388 1 0.03 -1 -1 30428 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64316 31 32 370 297 1 186 92 17 17 289 -1 unnamed_device 23.7 MiB 0.10 962 14375 4628 7389 2358 62.8 MiB 0.15 0.00 4.01529 -116.343 -4.01529 4.01529 0.31 0.000715968 0.000664875 0.0525152 0.0487842 -1 -1 -1 -1 32 2097 20 6.65987e+06 367662 554710. 1919.41 0.55 0.136711 0.120978 22834 132086 -1 1740 19 953 1608 91219 23548 2.83077 2.83077 -103.661 -2.83077 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0283605 0.0250845 145 61 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.65 vpr 62.97 MiB -1 -1 0.26 18260 1 0.03 -1 -1 30408 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64480 31 32 377 302 1 234 99 17 17 289 -1 unnamed_device 24.1 MiB 0.07 1386 11043 2787 7293 963 63.0 MiB 0.13 0.00 5.91489 -170.972 -5.91489 5.91489 0.32 0.000736886 0.000685819 0.0385686 0.0358586 -1 -1 -1 -1 32 2873 20 6.65987e+06 456408 554710. 1919.41 0.57 0.124678 0.109747 22834 132086 -1 2486 19 1319 1924 126550 30073 4.39548 4.39548 -152.161 -4.39548 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0287112 0.0251583 178 64 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 3.22 vpr 63.42 MiB -1 -1 0.26 18348 1 0.03 -1 -1 30388 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 31 32 383 305 1 209 95 17 17 289 -1 unnamed_device 23.9 MiB 0.62 1238 16511 4791 9794 1926 63.4 MiB 0.18 0.00 4.89912 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63956 31 32 261 225 1 142 86 17 17 289 -1 unnamed_device 23.4 MiB 0.09 737 9536 2387 5857 1292 62.5 MiB 0.09 0.00 3.48098 -96.6191 -3.48098 3.48098 0.32 0.000575726 0.000535589 0.0306291 0.0284653 -1 -1 -1 -1 30 1612 20 6.65987e+06 291594 526063. 1820.29 0.52 0.0958834 0.0841792 22546 126617 -1 1405 22 877 1491 83669 20744 2.47931 2.47931 -90.4761 -2.47931 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0247778 0.0215726 104 28 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 3.00 vpr 62.80 MiB -1 -1 0.26 18284 1 0.03 -1 -1 30132 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64304 31 32 337 267 1 204 97 17 17 289 -1 unnamed_device 23.8 MiB 0.08 1249 13195 3658 8262 1275 62.8 MiB 0.14 0.00 4.79192 -144.824 -4.79192 4.79192 0.34 0.000683955 0.000635929 0.0433617 0.0402853 -1 -1 -1 -1 24 3134 28 6.65987e+06 431052 448715. 1552.65 0.88 0.138378 0.12188 21394 104001 -1 2453 22 1503 2172 141924 34169 4.03451 4.03451 -135.006 -4.03451 0 0 554710. 1919.41 0.02 0.07 0.11 -1 -1 0.02 0.0296631 0.0258945 149 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.75 vpr 62.68 MiB -1 -1 0.24 18408 1 0.03 -1 -1 30420 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 349 284 1 183 102 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1155 13906 3407 9168 1331 62.7 MiB 0.13 0.00 3.8576 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1165 2183 127461 31331 3.47345 3.47345 -112.519 -3.47345 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0280871 0.0244558 127 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 2.78 vpr 62.70 MiB -1 -1 0.25 18404 1 0.03 -1 -1 30280 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64204 32 32 353 287 1 198 94 17 17 289 -1 unnamed_device 23.6 MiB 0.17 1224 8827 1935 6242 650 62.7 MiB 0.11 0.00 4.61566 -135.209 -4.61566 4.61566 0.31 0.000712229 0.000661663 0.0318336 0.0295804 -1 -1 -1 -1 30 2511 23 6.65987e+06 380340 526063. 1820.29 0.53 0.117116 0.102706 22546 126617 -1 2136 19 928 1310 71774 17944 3.20951 3.20951 -118.608 -3.20951 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0274664 0.0240917 142 55 -1 -1 -1 -1 + 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64280 32 32 382 305 1 192 104 17 17 289 -1 unnamed_device 23.7 MiB 0.12 1186 14744 3810 9393 1541 62.8 MiB 0.15 0.00 4.08875 -126.488 -4.08875 4.08875 0.32 0.000742546 0.000689999 0.0475827 0.0441969 -1 -1 -1 -1 26 2813 24 6.65987e+06 507120 477104. 1650.88 0.66 0.141553 0.124844 21682 110474 -1 2375 21 1537 2519 161666 39095 3.04491 3.04491 -117.668 -3.04491 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0308635 0.0269302 149 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 2.60 vpr 62.52 MiB -1 -1 0.22 17992 1 0.03 -1 -1 30320 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 32 32 306 248 1 166 100 17 17 289 -1 unnamed_device 23.4 MiB 0.09 1036 11932 2960 7977 995 62.5 MiB 0.11 0.00 3.95041 -117.901 -3.95041 3.95041 0.32 0.000629355 0.000583689 0.0352423 0.0326696 -1 -1 -1 -1 32 2001 21 6.65987e+06 456408 554710. 1919.41 0.54 0.112167 0.0985244 22834 132086 -1 1850 20 1003 1814 115866 27374 3.08765 3.08765 -108.602 -3.08765 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0250013 0.0219994 127 24 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.52 vpr 63.28 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30132 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64800 32 32 319 257 1 198 93 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1087 10383 2461 6851 1071 63.3 MiB 0.12 0.00 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64188 32 32 341 285 1 189 91 17 17 289 -1 unnamed_device 23.7 MiB 0.08 996 17023 5758 8918 2347 62.7 MiB 0.17 0.00 3.96847 -134.773 -3.96847 3.96847 0.32 0.000673933 0.000625952 0.0586522 0.0544351 -1 -1 -1 -1 28 2722 23 6.65987e+06 342306 500653. 1732.36 0.70 0.142328 0.126048 21970 115934 -1 2070 19 1306 1855 127035 31021 3.38897 3.38897 -128.298 -3.38897 0 0 612192. 2118.31 0.03 0.07 0.10 -1 -1 0.03 0.0258283 0.0225418 133 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.77 vpr 62.88 MiB -1 -1 0.24 18520 1 0.03 -1 -1 30352 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64392 32 32 387 293 1 234 99 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1433 14463 4059 9245 1159 62.9 MiB 0.16 0.00 5.18108 -151.87 -5.18108 5.18108 0.32 0.000764555 0.000710159 0.0512314 0.0475868 -1 -1 -1 -1 32 3076 23 6.65987e+06 443730 554710. 1919.41 0.58 0.144273 0.127505 22834 132086 -1 2769 21 1634 2613 161131 38979 4.04551 4.04551 -142.419 -4.04551 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.032354 0.0283413 174 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 2.52 vpr 62.75 MiB -1 -1 0.24 18392 1 0.03 -1 -1 30380 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64256 32 32 340 270 1 181 102 17 17 289 -1 unnamed_device 23.7 MiB 0.08 1064 9622 2158 6803 661 62.8 MiB 0.10 0.00 4.25077 -131.82 -4.25077 4.25077 0.32 0.000689443 0.000641753 0.030528 0.0283813 -1 -1 -1 -1 26 2445 19 6.65987e+06 481764 477104. 1650.88 0.54 0.111197 0.0976738 21682 110474 -1 2100 20 1180 2009 122888 30587 2.98991 2.98991 -119.17 -2.98991 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0282445 0.0247036 141 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 2.97 vpr 62.47 MiB -1 -1 0.22 18020 1 0.02 -1 -1 30388 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 30 32 278 235 1 148 95 17 17 289 -1 unnamed_device 23.4 MiB 0.06 873 7655 1741 5556 358 62.5 MiB 0.08 0.00 3.46801 -106.861 -3.46801 3.46801 0.29 0.000592529 0.000551119 0.0230086 0.0213939 -1 -1 -1 -1 26 1985 22 6.65987e+06 418374 477104. 1650.88 1.09 0.101588 0.0889863 21682 110474 -1 1566 19 872 1628 93100 23067 2.89891 2.89891 -101.232 -2.89891 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0227936 0.0198726 111 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 3.74 vpr 63.60 MiB -1 -1 0.27 18632 1 0.03 -1 -1 30348 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 32 32 431 332 1 235 97 17 17 289 -1 unnamed_device 24.1 MiB 0.16 1373 17857 5541 9729 2587 63.6 MiB 0.21 0.00 6.00689 -175.284 -6.00689 6.00689 0.32 0.000829838 0.000770463 0.0699701 0.065028 -1 -1 -1 -1 26 3848 37 6.65987e+06 418374 477104. 1650.88 1.45 0.197086 0.174141 21682 110474 -1 3002 21 1997 2930 217962 52054 5.28897 5.28897 -171.079 -5.28897 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0353896 0.0309506 177 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 2.72 vpr 62.68 MiB -1 -1 0.23 18428 1 0.03 -1 -1 30384 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 336 268 1 174 102 17 17 289 -1 unnamed_device 23.7 MiB 0.11 1017 19142 6169 10401 2572 62.7 MiB 0.18 0.00 4.49092 -134.922 -4.49092 4.49092 0.32 0.000688964 0.000639258 0.058669 0.0542224 -1 -1 -1 -1 32 2057 20 6.65987e+06 481764 554710. 1919.41 0.55 0.138961 0.123175 22834 132086 -1 1855 18 1006 1647 91104 22583 3.46031 3.46031 -122.488 -3.46031 0 0 701300. 2426.64 0.05 0.07 0.08 -1 -1 0.05 0.027125 0.0239429 136 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 2.42 vpr 62.38 MiB -1 -1 0.20 17912 1 0.05 -1 -1 30352 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63880 32 32 231 199 1 140 93 17 17 289 -1 unnamed_device 23.1 MiB 0.06 757 14793 4373 7837 2583 62.4 MiB 0.13 0.00 3.29469 -92.947 -3.29469 3.29469 0.32 0.000538264 0.000501659 0.0461663 0.0429533 -1 -1 -1 -1 30 1671 23 6.65987e+06 367662 526063. 1820.29 0.50 0.111364 0.098657 22546 126617 -1 1389 20 700 1220 66685 16954 2.41305 2.41305 -85.9205 -2.41305 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.021408 0.0186665 103 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 2.75 vpr 63.34 MiB -1 -1 0.23 18472 1 0.04 -1 -1 30316 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 32 32 349 273 1 191 104 17 17 289 -1 unnamed_device 23.7 MiB 0.10 1150 19624 5000 12637 1987 63.3 MiB 0.19 0.00 5.1064 -126.138 -5.1064 5.1064 0.32 0.000704936 0.000655185 0.059793 0.055533 -1 -1 -1 -1 28 2459 23 6.65987e+06 507120 500653. 1732.36 0.57 0.147213 0.130679 21970 115934 -1 2168 22 1287 2791 166610 39959 3.96919 3.96919 -118.971 -3.96919 0 0 612192. 2118.31 0.03 0.08 0.12 -1 -1 0.03 0.0303989 0.0264907 147 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 2.52 vpr 63.21 MiB -1 -1 0.22 17964 1 0.03 -1 -1 30112 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 32 32 247 207 1 147 87 17 17 289 -1 unnamed_device 23.4 MiB 0.06 872 15831 4931 8734 2166 63.2 MiB 0.14 0.00 3.5083 -107.383 -3.5083 3.5083 0.32 0.000561581 0.00052297 0.050766 0.0471046 -1 -1 -1 -1 32 1802 23 6.65987e+06 291594 554710. 1919.41 0.51 0.118787 0.105164 22834 132086 -1 1692 22 1001 1708 115538 28004 2.61951 2.61951 -100.831 -2.61951 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0241798 0.0210207 107 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 2.78 vpr 62.54 MiB -1 -1 0.24 18124 1 0.03 -1 -1 30336 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 30 32 278 235 1 147 100 17 17 289 -1 unnamed_device 23.4 MiB 0.11 879 14252 3836 8169 2247 62.5 MiB 0.12 0.00 4.01069 -108.355 -4.01069 4.01069 0.34 0.000599354 0.000550843 0.0387901 0.0359731 -1 -1 -1 -1 26 2025 24 6.65987e+06 481764 477104. 1650.88 0.69 0.11377 0.100057 21682 110474 -1 1739 19 906 1763 110431 27178 2.97191 2.97191 -105.651 -2.97191 0 0 585099. 2024.56 0.03 0.06 0.07 -1 -1 0.03 0.0225145 0.0196321 110 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 3.39 vpr 63.42 MiB -1 -1 0.25 18252 1 0.03 -1 -1 30480 -1 -1 32 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 29 32 355 287 1 198 93 17 17 289 -1 unnamed_device 23.7 MiB 0.10 935 10383 2371 7436 576 63.4 MiB 0.12 0.00 4.5774 -127.327 -4.5774 4.5774 0.32 0.000695523 0.000647079 0.0369925 0.0343684 -1 -1 -1 -1 26 3076 43 6.65987e+06 405696 477104. 1650.88 1.04 0.149016 0.130089 21682 110474 -1 2152 21 1391 2137 138462 37475 3.39717 3.39717 -116.441 -3.39717 0 0 585099. 2024.56 0.04 0.09 0.10 -1 -1 0.04 0.0365452 0.031807 146 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 2.56 vpr 62.78 MiB -1 -1 0.24 18248 1 0.03 -1 -1 30348 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64288 32 32 358 289 1 175 91 17 17 289 -1 unnamed_device 23.8 MiB 0.09 929 8251 1789 6085 377 62.8 MiB 0.10 0.00 4.29907 -134.356 -4.29907 4.29907 0.32 0.000692743 0.000642667 0.0308125 0.0285985 -1 -1 -1 -1 32 2220 22 6.65987e+06 342306 554710. 1919.41 0.56 0.116133 0.101656 22834 132086 -1 1882 22 1411 2117 134488 33129 3.89817 3.89817 -131.246 -3.89817 0 0 701300. 2426.64 0.03 0.07 0.08 -1 -1 0.03 0.0309356 0.0270608 135 54 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.62 vpr 63.35 MiB -1 -1 0.23 18572 1 0.04 -1 -1 30276 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 353 285 1 181 98 17 17 289 -1 unnamed_device 23.7 MiB 0.11 1075 15173 3870 9435 1868 63.3 MiB 0.15 0.00 4.58626 -136.867 -4.58626 4.58626 0.32 0.000705923 0.000655882 0.0503308 0.046744 -1 -1 -1 -1 32 2211 20 6.65987e+06 431052 554710. 1919.41 0.55 0.132979 0.11753 22834 132086 -1 1968 17 847 1531 91027 22240 3.35191 3.35191 -122.638 -3.35191 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0253636 0.0223258 136 51 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.47 vpr 63.35 MiB -1 -1 0.25 18168 1 0.04 -1 -1 30140 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 32 32 276 237 1 160 86 17 17 289 -1 unnamed_device 23.7 MiB 0.10 901 6701 1571 4713 417 63.4 MiB 0.08 0.00 4.569 -127.264 -4.569 4.569 0.32 0.000598546 0.000556821 0.0231644 0.0215639 -1 -1 -1 -1 26 2033 20 6.65987e+06 278916 477104. 1650.88 0.48 0.0923268 0.0807068 21682 110474 -1 1721 21 882 1189 70078 18621 3.26691 3.26691 -112.036 -3.26691 0 0 585099. 2024.56 0.02 0.03 0.06 -1 -1 0.02 0.0140382 0.0124423 107 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.64 vpr 62.48 MiB -1 -1 0.20 18340 1 0.03 -1 -1 30296 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63980 31 32 319 272 1 169 88 17 17 289 -1 unnamed_device 23.6 MiB 0.09 802 16273 4920 8724 2629 62.5 MiB 0.15 0.00 3.75784 -117.415 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/home/elgamma8/research/release/vtr-verilog-to-routing 64396 31 32 293 230 1 175 100 17 17 289 -1 unnamed_device 23.7 MiB 0.06 1091 10540 2548 6838 1154 62.9 MiB 0.11 0.00 4.26866 -122.654 -4.26866 4.26866 0.29 0.000634407 0.000589944 0.031125 0.0289309 -1 -1 -1 -1 28 2517 21 6.65987e+06 469086 500653. 1732.36 0.62 0.10807 0.0950411 21970 115934 -1 2180 23 1405 2540 172113 40649 3.40705 3.40705 -114.855 -3.40705 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0283837 0.0247165 134 4 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 3.53 vpr 62.97 MiB -1 -1 0.23 18332 1 0.07 -1 -1 30300 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64484 32 32 350 275 1 209 94 17 17 289 -1 unnamed_device 24.2 MiB 0.12 1246 10957 2695 7343 919 63.0 MiB 0.14 0.00 4.99112 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64176 30 32 375 299 1 187 89 17 17 289 -1 unnamed_device 23.6 MiB 0.13 1064 12365 3291 6967 2107 62.7 MiB 0.13 0.00 4.67895 -138.029 -4.67895 4.67895 0.31 0.000725007 0.000674131 0.0480908 0.0447495 -1 -1 -1 -1 28 2343 23 6.65987e+06 342306 500653. 1732.36 0.62 0.136452 0.120796 21970 115934 -1 1980 22 1486 2399 145841 36399 3.50937 3.50937 -127.985 -3.50937 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0317457 0.027759 147 63 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 2.65 vpr 63.50 MiB -1 -1 0.23 18316 1 0.03 -1 -1 30344 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 32 32 340 270 1 200 94 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1145 13939 3986 8000 1953 63.5 MiB 0.15 0.00 5.09463 -149.184 -5.09463 5.09463 0.29 0.000696151 0.000641679 0.0475882 0.0442297 -1 -1 -1 -1 30 2536 25 6.65987e+06 380340 526063. 1820.29 0.55 0.133121 0.117514 22546 126617 -1 2135 21 1195 1902 103374 25035 3.52651 3.52651 -127.669 -3.52651 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0288516 0.0252219 145 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 3.16 vpr 62.95 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30256 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64464 31 32 340 275 1 196 98 17 17 289 -1 unnamed_device 23.9 MiB 0.18 1110 13148 3427 8545 1176 63.0 MiB 0.13 0.00 5.06667 -144.178 -5.06667 5.06667 0.32 0.000692547 0.00064179 0.0430229 0.0399631 -1 -1 -1 -1 34 2291 34 6.65987e+06 443730 585099. 2024.56 0.95 0.190217 0.165664 23122 138558 -1 2068 20 1254 2153 127671 32495 3.93437 3.93437 -132.32 -3.93437 0 0 742403. 2568.87 0.03 0.07 0.11 -1 -1 0.03 0.0277139 0.0242435 151 47 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 3.18 vpr 63.29 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30392 -1 -1 38 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64808 30 32 377 310 1 177 100 17 17 289 -1 unnamed_device 23.6 MiB 0.48 1101 17500 4849 10565 2086 63.3 MiB 0.18 0.00 4.57218 -136.411 -4.57218 4.57218 0.32 0.000708472 0.000656727 0.0563314 0.0522355 -1 -1 -1 -1 32 2218 20 6.65987e+06 481764 554710. 1919.41 0.57 0.140582 0.124466 22834 132086 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 32 32 243 205 1 139 83 17 17 289 -1 unnamed_device 23.1 MiB 0.10 885 6923 1715 4767 441 62.3 MiB 0.07 0.00 3.77952 -113.03 -3.77952 3.77952 0.32 0.000553392 0.000515609 0.0230724 0.0214826 -1 -1 -1 -1 26 1838 17 6.65987e+06 240882 477104. 1650.88 0.52 0.0857542 0.0752007 21682 110474 -1 1658 19 797 1244 78852 19566 2.69545 2.69545 -103.315 -2.69545 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0288758 0.0251878 99 3 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 2.84 vpr 62.77 MiB -1 -1 0.25 18268 1 0.04 -1 -1 30308 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 32 32 373 302 1 176 99 17 17 289 -1 unnamed_device 23.7 MiB 0.14 1014 14691 4446 7278 2967 62.8 MiB 0.14 0.00 4.39152 -132.525 -4.39152 4.39152 0.32 0.000727586 0.00067249 0.0500078 0.046285 -1 -1 -1 -1 32 2332 30 6.65987e+06 443730 554710. 1919.41 0.69 0.146265 0.128769 22834 132086 -1 1872 23 1191 1892 138049 33056 3.67671 3.67671 -122.883 -3.67671 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0328304 0.0289108 135 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 2.92 vpr 62.82 MiB -1 -1 0.27 18284 1 0.04 -1 -1 30228 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64324 32 32 397 314 1 196 89 17 17 289 -1 unnamed_device 23.9 MiB 0.24 1125 9989 2357 6341 1291 62.8 MiB 0.12 0.00 4.65798 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 356 289 1 202 101 17 17 289 -1 unnamed_device 23.9 MiB 0.18 1270 17021 5150 9608 2263 63.3 MiB 0.16 0.00 5.06049 -146.913 -5.06049 5.06049 0.32 0.000326262 0.000301131 0.0486664 0.0450209 -1 -1 -1 -1 26 2988 41 6.65987e+06 469086 477104. 1650.88 0.74 0.159099 0.140044 21682 110474 -1 2434 19 1509 2359 161130 37560 4.17677 4.17677 -139.903 -4.17677 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0275016 0.0240929 157 56 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 3.13 vpr 63.51 MiB -1 -1 0.16 18148 1 0.03 -1 -1 30108 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 32 32 331 280 1 175 87 17 17 289 -1 unnamed_device 23.4 MiB 0.40 1020 11991 3560 6392 2039 63.2 MiB 0.15 0.00 4.25169 -136.039 -4.25169 4.25169 0.32 0.000864673 0.000803635 0.0533516 0.0496012 -1 -1 -1 -1 32 2019 16 6.65987e+06 291594 554710. 1919.41 0.53 0.127172 0.112926 22834 132086 -1 1798 18 782 1100 71252 17324 3.25897 3.25897 -123.619 -3.25897 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0245208 0.0215202 131 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 2.95 vpr 62.66 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30324 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 32 32 326 263 1 176 100 17 17 289 -1 unnamed_device 23.7 MiB 0.09 1117 12164 3459 7844 861 62.7 MiB 0.12 0.00 4.92174 -128.183 -4.92174 4.92174 0.31 0.00066283 0.000615913 0.0374864 0.0347847 -1 -1 -1 -1 26 2516 22 6.65987e+06 456408 477104. 1650.88 0.54 0.119342 0.104951 21682 110474 -1 2181 18 1043 1793 114022 27754 3.30585 3.30585 -116.367 -3.30585 0 0 585099. 2024.56 0.03 0.06 0.09 -1 -1 0.03 0.0251273 0.0220676 133 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 3.01 vpr 63.32 MiB -1 -1 0.20 18484 1 0.04 -1 -1 30424 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 31 32 373 294 1 196 101 17 17 289 -1 unnamed_device 23.8 MiB 0.09 1058 9971 2285 7156 530 63.3 MiB 0.12 0.00 4.48315 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 2.80 vpr 63.50 MiB -1 -1 0.25 18400 1 0.03 -1 -1 30040 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 386 307 1 195 106 17 17 289 -1 unnamed_device 24.0 MiB 0.11 1068 16856 4579 8928 3349 63.5 MiB 0.14 0.00 4.17081 -125.313 -4.17081 4.17081 0.32 0.000746376 0.000693057 0.0533797 0.0495831 -1 -1 -1 -1 32 2577 35 6.65987e+06 532476 554710. 1919.41 0.67 0.159111 0.140204 22834 132086 -1 2028 24 1434 2300 146117 37601 2.97097 2.97097 -114.135 -2.97097 0 0 701300. 2426.64 0.03 0.09 0.11 -1 -1 0.03 0.034841 0.0304283 151 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.34 vpr 62.36 MiB -1 -1 0.11 18144 1 0.03 -1 -1 30284 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63860 29 32 269 229 1 129 80 17 17 289 -1 unnamed_device 23.4 MiB 0.05 783 14184 4630 8014 1540 62.4 MiB 0.12 0.00 4.07075 -112.394 -4.07075 4.07075 0.32 0.000576339 0.000535755 0.0495872 0.0461609 -1 -1 -1 -1 32 1449 20 6.65987e+06 240882 554710. 1919.41 0.49 0.116661 0.103432 22834 132086 -1 1346 20 716 1069 69828 16923 2.81477 2.81477 -95.7948 -2.81477 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0229956 0.0200317 93 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 2.80 vpr 62.46 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30332 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63964 32 32 310 266 1 175 89 17 17 289 -1 unnamed_device 23.3 MiB 0.08 1007 13949 3952 8258 1739 62.5 MiB 0.12 0.00 4.24766 -126.418 -4.24766 4.24766 0.32 0.000481589 0.000443594 0.0432888 0.0401085 -1 -1 -1 -1 32 1793 18 6.65987e+06 316950 554710. 1919.41 0.52 0.11537 0.101824 22834 132086 -1 1672 14 756 1020 62601 15811 3.06877 3.06877 -112.763 -3.06877 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0198489 0.017478 122 58 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 3.17 vpr 63.25 MiB -1 -1 0.14 18252 1 0.03 -1 -1 30304 -1 -1 42 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 31 32 326 261 1 177 105 17 17 289 -1 unnamed_device 23.7 MiB 0.08 926 12208 3208 7327 1673 63.2 MiB 0.12 0.00 4.58372 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 31 32 265 230 1 163 88 17 17 289 -1 unnamed_device 23.3 MiB 0.07 930 10228 2669 6535 1024 62.5 MiB 0.10 0.00 3.8161 -117.091 -3.8161 3.8161 0.32 0.000591034 0.000543686 0.0323042 0.0300571 -1 -1 -1 -1 32 1836 21 6.65987e+06 316950 554710. 1919.41 0.49 0.100283 0.0881994 22834 132086 -1 1638 17 808 1220 76603 18529 2.93457 2.93457 -107.171 -2.93457 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0213134 0.0187932 115 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 2.63 vpr 62.65 MiB -1 -1 0.23 18412 1 0.03 -1 -1 30008 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64156 32 32 349 286 1 171 101 17 17 289 -1 unnamed_device 23.6 MiB 0.11 1077 18196 4934 11069 2193 62.7 MiB 0.16 0.00 3.54324 -109.963 -3.54324 3.54324 0.32 0.000538895 0.000495325 0.0514617 0.0475687 -1 -1 -1 -1 32 2182 22 6.65987e+06 469086 554710. 1919.41 0.56 0.134851 0.118993 22834 132086 -1 1852 21 982 1748 107334 25210 2.76771 2.76771 -104.243 -2.76771 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0290857 0.025433 131 57 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 2.95 vpr 63.34 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30416 -1 -1 36 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 31 32 396 325 1 183 99 17 17 289 -1 unnamed_device 23.6 MiB 0.43 972 13779 3191 9639 949 63.3 MiB 0.14 0.00 3.95996 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 29 32 324 268 1 168 97 17 17 289 -1 unnamed_device 23.5 MiB 0.11 1042 6535 1424 4454 657 62.8 MiB 0.07 0.00 4.20872 -115.808 -4.20872 4.20872 0.31 0.000653114 0.000605773 0.021466 0.0199964 -1 -1 -1 -1 30 1967 16 6.65987e+06 456408 526063. 1820.29 0.50 0.0934942 0.0815178 22546 126617 -1 1808 19 714 1267 68406 16641 2.71491 2.71491 -97.6025 -2.71491 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0257432 0.0225677 129 55 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.87 vpr 63.45 MiB -1 -1 0.23 18276 1 0.03 -1 -1 30480 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 393 312 1 213 94 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1136 17773 5438 9801 2534 63.4 MiB 0.19 0.00 5.18709 -160.79 -5.18709 5.18709 0.32 0.000751899 0.000698984 0.0661306 0.0614276 -1 -1 -1 -1 32 2400 22 6.65987e+06 380340 554710. 1919.41 0.61 0.167742 0.148709 22834 132086 -1 2213 22 1428 1987 125431 30881 3.96237 3.96237 -142.636 -3.96237 0 0 701300. 2426.64 0.04 0.10 0.11 -1 -1 0.04 0.0400136 0.0353947 159 65 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.46 vpr 62.59 MiB -1 -1 0.23 17952 1 0.03 -1 -1 30084 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 31 32 229 197 1 138 84 17 17 289 -1 unnamed_device 23.3 MiB 0.07 877 10515 2651 6990 874 62.6 MiB 0.10 0.00 3.28101 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1104 1594 96411 24003 3.39911 3.39911 -128.845 -3.39911 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0296925 0.0260202 146 90 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 2.64 vpr 62.69 MiB -1 -1 0.24 18448 1 0.03 -1 -1 30108 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 32 32 376 318 1 156 82 17 17 289 -1 unnamed_device 23.7 MiB 0.11 914 11474 3086 6952 1436 62.7 MiB 0.13 0.00 3.54227 -124.771 -3.54227 3.54227 0.32 0.000718606 0.000667277 0.049602 0.046095 -1 -1 -1 -1 32 1720 17 6.65987e+06 228204 554710. 1919.41 0.53 0.129159 0.114224 22834 132086 -1 1578 21 1236 1858 105693 26868 2.87077 2.87077 -119.337 -2.87077 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0294216 0.0256661 117 96 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.69 vpr 63.28 MiB -1 -1 0.15 18304 1 0.03 -1 -1 30320 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 32 32 360 293 1 179 99 17 17 289 -1 unnamed_device 23.6 MiB 0.09 987 16059 4384 8773 2902 63.3 MiB 0.15 0.00 3.84552 -115.819 -3.84552 3.84552 0.33 0.000588113 0.000522126 0.0529609 0.0491666 -1 -1 -1 -1 32 2087 20 6.65987e+06 443730 554710. 1919.41 0.55 0.136764 0.121046 22834 132086 -1 1731 18 919 1426 73695 19390 2.62331 2.62331 -97.5338 -2.62331 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0269736 0.023685 134 60 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.78 vpr 63.52 MiB -1 -1 0.15 18496 1 0.03 -1 -1 30488 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65040 32 32 396 299 1 236 98 17 17 289 -1 unnamed_device 23.9 MiB 0.16 1229 18773 5439 9701 3633 63.5 MiB 0.18 0.00 6.00689 -176.035 -6.00689 6.00689 0.34 0.000348158 0.00032017 0.0661284 0.0613889 -1 -1 -1 -1 36 2968 23 6.65987e+06 431052 612192. 2118.31 1.43 0.227075 0.199663 23410 145293 -1 2288 21 1763 2474 164498 42055 4.85537 4.85537 -153.246 -4.85537 0 0 782063. 2706.10 0.04 0.07 0.11 -1 -1 0.04 0.0231769 0.0207501 177 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.52 vpr 62.36 MiB -1 -1 0.16 18020 1 0.03 -1 -1 30244 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63860 30 32 224 207 1 138 84 17 17 289 -1 unnamed_device 23.1 MiB 0.06 852 12894 3845 7396 1653 62.4 MiB 0.10 0.00 3.23481 -100.258 -3.23481 3.23481 0.34 0.000510384 0.000474865 0.0371748 0.0345906 -1 -1 -1 -1 26 1611 17 6.65987e+06 278916 477104. 1650.88 0.51 0.0938904 0.0829793 21682 110474 -1 1486 21 811 1082 72254 17229 2.47811 2.47811 -92.0662 -2.47811 0 0 585099. 2024.56 0.03 0.05 0.09 -1 -1 0.03 0.0207099 0.0179707 92 34 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.53 vpr 62.52 MiB -1 -1 0.22 18088 1 0.03 -1 -1 30344 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64024 30 32 286 239 1 134 81 17 17 289 -1 unnamed_device 23.4 MiB 0.13 726 6206 1469 4338 399 62.5 MiB 0.07 0.00 3.83543 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64356 31 32 409 331 1 191 105 17 17 289 -1 unnamed_device 23.9 MiB 0.11 987 19124 5334 10330 3460 62.8 MiB 0.19 0.00 3.91658 -124.769 -3.91658 3.91658 0.32 0.000756341 0.000701237 0.0615584 0.0570229 -1 -1 -1 -1 32 2113 20 6.65987e+06 532476 554710. 1919.41 0.60 0.154524 0.136607 22834 132086 -1 1837 19 1226 1995 117145 29196 2.79751 2.79751 -109.839 -2.79751 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0292829 0.0256389 148 90 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_001.v common 11.61 vpr 64.05 MiB -1 -1 0.24 18320 1 0.03 -1 -1 30228 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65588 32 32 354 285 1 191 88 17 17 289 -1 unnamed_device 24.5 MiB 1.20 903 15298 5538 7704 2056 64.1 MiB 0.13 0.00 5.15265 -149.781 -5.15265 5.15265 0.35 0.000701928 0.000652099 0.0579569 0.0538537 -1 -1 -1 -1 40 2487 22 6.95648e+06 347416 706193. 2443.58 8.24 0.381864 0.330066 26914 176310 -1 2069 20 1681 2521 193589 46028 4.70236 4.70236 -152.72 -4.70236 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0283789 0.0248703 85 50 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 6.23 vpr 63.55 MiB -1 -1 0.25 18552 1 0.03 -1 -1 30328 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 30 32 363 293 1 187 80 17 17 289 -1 unnamed_device 24.5 MiB 1.72 822 9540 3866 5233 441 63.5 MiB 0.10 0.00 4.21658 -127.866 -4.21658 4.21658 0.35 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0 902133. 3121.57 0.04 0.07 0.14 -1 -1 0.04 0.0271238 0.023716 74 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_004.v common 4.01 vpr 64.01 MiB -1 -1 0.24 18400 1 0.03 -1 -1 30284 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65548 29 32 308 248 1 162 84 17 17 289 -1 unnamed_device 24.3 MiB 0.21 713 12894 4756 6364 1774 64.0 MiB 0.11 0.00 3.96328 -113.694 -3.96328 3.96328 0.33 0.000637533 0.000592304 0.046852 0.043548 -1 -1 -1 -1 36 2424 31 6.95648e+06 332941 648988. 2245.63 1.85 0.192789 0.167961 26050 158493 -1 1795 24 1592 2700 214858 50665 4.07691 4.07691 -125.389 -4.07691 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0184205 0.016334 73 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 4.13 vpr 63.91 MiB -1 -1 0.24 18416 1 0.03 -1 -1 30432 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 32 32 336 268 1 167 85 17 17 289 -1 unnamed_device 24.2 MiB 0.30 799 12919 4266 6230 2423 63.9 MiB 0.14 0.00 3.92082 -123.639 -3.92082 3.92082 0.33 0.000689843 0.000640891 0.0579711 0.053704 -1 -1 -1 -1 40 2419 26 6.95648e+06 303989 706193. 2443.58 1.73 0.195597 0.171434 26914 176310 -1 1974 23 1432 2633 220972 49560 4.01942 4.01942 -133.562 -4.01942 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0306242 0.026712 76 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 4.55 vpr 63.35 MiB -1 -1 0.25 18324 1 0.03 -1 -1 30296 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 366 295 1 182 89 17 17 289 -1 unnamed_device 24.5 MiB 0.40 1004 13949 3867 8912 1170 63.3 MiB 0.13 0.00 3.1127 -117.428 -3.1127 3.1127 0.33 0.000898578 0.000838343 0.0537559 0.0498994 -1 -1 -1 -1 34 2773 40 6.95648e+06 361892 618332. 2139.56 2.07 0.217268 0.189412 25762 151098 -1 2255 18 1337 2010 155622 35041 3.22637 3.22637 -127.705 -3.22637 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0266073 0.0233266 81 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 6.63 vpr 63.88 MiB -1 -1 0.23 18196 1 0.03 -1 -1 30616 -1 -1 14 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65412 27 32 259 221 1 124 73 17 17 289 -1 unnamed_device 24.3 MiB 2.35 446 7825 3025 3749 1051 63.9 MiB 0.07 0.00 3.35433 -89.8611 -3.35433 3.35433 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65348 32 32 298 248 1 150 75 17 17 289 -1 unnamed_device 24.4 MiB 0.82 631 10503 4334 5853 316 63.8 MiB 0.10 0.00 3.30308 -115.551 -3.30308 3.30308 0.33 0.0006312 0.000584843 0.0439573 0.0408989 -1 -1 -1 -1 42 1721 25 6.95648e+06 159232 744469. 2576.02 1.03 0.17109 0.149045 27202 183097 -1 1354 19 1057 1489 99641 25380 3.14782 3.14782 -113.598 -3.14782 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0240878 0.0210586 60 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_011.v common 4.30 vpr 63.69 MiB -1 -1 0.24 18432 1 0.03 -1 -1 30336 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65216 30 32 303 262 1 135 75 17 17 289 -1 unnamed_device 24.3 MiB 0.89 501 7975 2162 4189 1624 63.7 MiB 0.07 0.00 3.32418 -98.7921 -3.32418 3.32418 0.33 0.000626842 0.000583299 0.033361 0.031035 -1 -1 -1 -1 42 1361 50 6.95648e+06 188184 744469. 2576.02 1.38 0.180268 0.155588 27202 183097 -1 1018 21 1057 1561 93379 26253 2.99162 2.99162 -104.394 -2.99162 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0261378 0.022782 54 63 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 4.57 vpr 63.32 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30204 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 276 237 1 161 77 17 17 289 -1 unnamed_device 24.3 MiB 1.18 717 11487 4799 6349 339 63.3 MiB 0.05 0.00 3.36853 -108.171 -3.36853 3.36853 0.32 0.000263884 0.000242125 0.0203308 0.0187078 -1 -1 -1 -1 42 2258 41 6.95648e+06 188184 744469. 2576.02 1.40 0.152874 0.131337 27202 183097 -1 1691 23 1303 1654 162426 40261 3.05107 3.05107 -115.385 -3.05107 0 0 949917. 3286.91 0.04 0.07 0.14 -1 -1 0.04 0.0263999 0.0229264 61 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_013.v common 11.03 vpr 63.34 MiB -1 -1 0.25 18344 1 0.03 -1 -1 30272 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 32 32 344 272 1 194 81 17 17 289 -1 unnamed_device 24.4 MiB 1.33 963 14256 6124 7652 480 63.3 MiB 0.13 0.00 4.10048 -133.291 -4.10048 4.10048 0.33 0.000688322 0.000638252 0.0586569 0.0544325 -1 -1 -1 -1 52 2682 48 6.95648e+06 246087 926341. 3205.33 7.55 0.399651 0.344428 29218 227130 -1 2046 22 1527 2342 196802 44603 3.49922 3.49922 -129.355 -3.49922 0 0 1.14541e+06 3963.36 0.05 0.09 0.18 -1 -1 0.05 0.0310755 0.02722 80 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_014.v common 11.11 vpr 63.53 MiB -1 -1 0.14 18364 1 0.03 -1 -1 30292 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 32 32 363 295 1 174 89 17 17 289 -1 unnamed_device 24.5 MiB 0.37 807 13751 4140 6609 3002 63.5 MiB 0.12 0.00 4.30188 -129.441 -4.30188 4.30188 0.34 0.000722024 0.000670873 0.0521037 0.0484003 -1 -1 -1 -1 42 2744 33 6.95648e+06 361892 744469. 2576.02 8.61 0.359569 0.310163 27202 183097 -1 1947 24 1856 2848 247962 58594 4.34321 4.34321 -142.631 -4.34321 0 0 949917. 3286.91 0.04 0.10 0.15 -1 -1 0.04 0.0323478 0.0281415 78 61 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_015.v common 4.18 vpr 63.60 MiB -1 -1 0.22 18040 1 0.03 -1 -1 30504 -1 -1 18 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 29 32 248 215 1 132 79 17 17 289 -1 unnamed_device 24.2 MiB 0.43 542 11064 3839 5079 2146 63.6 MiB 0.10 0.00 2.93656 -85.9547 -2.93656 2.93656 0.33 0.000543369 0.000504995 0.0449064 0.0417544 -1 -1 -1 -1 38 1739 25 6.95648e+06 260562 678818. 2348.85 1.60 0.163141 0.142452 26626 170182 -1 1156 20 930 1476 86830 22287 2.86467 2.86467 -90.2809 -2.86467 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0219637 0.0191139 55 27 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 9.89 vpr 64.18 MiB -1 -1 0.25 18480 1 0.03 -1 -1 30292 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65720 32 32 370 297 1 178 81 17 17 289 -1 unnamed_device 24.6 MiB 0.55 1116 11456 4128 5618 1710 64.2 MiB 0.11 0.00 3.1427 -121.494 -3.1427 3.1427 0.33 0.000717433 0.000666227 0.0497802 0.0462674 -1 -1 -1 -1 38 2695 25 6.95648e+06 246087 678818. 2348.85 7.13 0.321783 0.277821 26626 170182 -1 2317 20 1511 2426 195538 40467 3.13107 3.13107 -128.649 -3.13107 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.029045 0.0253744 77 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 5.39 vpr 64.05 MiB -1 -1 0.23 18332 1 0.03 -1 -1 30084 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65592 32 32 338 269 1 190 81 17 17 289 -1 unnamed_device 24.2 MiB 1.49 1015 13031 4708 5937 2386 64.1 MiB 0.12 0.00 3.87402 -125.064 -3.87402 3.87402 0.34 0.000692755 0.000644535 0.0542598 0.0504807 -1 -1 -1 -1 36 2757 49 6.95648e+06 246087 648988. 2245.63 1.76 0.226187 0.197378 26050 158493 -1 2291 25 1915 2601 250174 70472 3.35447 3.35447 -133.03 -3.35447 0 0 828058. 2865.25 0.03 0.11 0.13 -1 -1 0.03 0.0331884 0.0289165 78 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_018.v common 3.96 vpr 63.38 MiB -1 -1 0.24 18420 1 0.03 -1 -1 30336 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 32 32 323 276 1 148 87 17 17 289 -1 unnamed_device 24.3 MiB 0.59 786 10071 3578 4718 1775 63.4 MiB 0.09 0.00 2.31531 -95.0474 -2.31531 2.31531 0.34 0.000651323 0.000604716 0.0365085 0.0338373 -1 -1 -1 -1 40 1891 23 6.95648e+06 332941 706193. 2443.58 1.30 0.171573 0.148913 26914 176310 -1 1667 24 1362 2073 174745 41485 2.52138 2.52138 -102.073 -2.52138 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0295211 0.02561 65 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_019.v common 3.21 vpr 63.24 MiB -1 -1 0.21 18132 1 0.03 -1 -1 30076 -1 -1 11 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 30 32 222 206 1 114 73 17 17 289 -1 unnamed_device 23.7 MiB 0.15 430 7217 2897 3955 365 63.2 MiB 0.06 0.00 2.19546 -77.9644 -2.19546 2.19546 0.34 0.000496364 0.000461914 0.0252717 0.023525 -1 -1 -1 -1 38 1129 22 6.95648e+06 159232 678818. 2348.85 1.10 0.125104 0.108162 26626 170182 -1 802 21 683 938 55231 15482 2.06418 2.06418 -79.525 -2.06418 0 0 902133. 3121.57 0.04 0.05 0.14 -1 -1 0.04 0.0206062 0.0179189 44 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_020.v common 4.62 vpr 63.34 MiB -1 -1 0.24 18252 1 0.03 -1 -1 30452 -1 -1 14 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 31 32 291 243 1 166 77 17 17 289 -1 unnamed_device 24.2 MiB 1.53 1007 11976 3355 7225 1396 63.3 MiB 0.10 0.00 4.40603 -142.381 -4.40603 4.40603 0.33 0.000608611 0.000566303 0.0470857 0.043836 -1 -1 -1 -1 34 2380 24 6.95648e+06 202660 618332. 2139.56 1.06 0.169043 0.147544 25762 151098 -1 2003 20 1207 1675 119064 27189 3.98032 3.98032 -146.92 -3.98032 0 0 787024. 2723.27 0.03 0.06 0.12 -1 -1 0.03 0.0247293 0.0215758 68 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 4.70 vpr 63.46 MiB -1 -1 0.26 18472 1 0.03 -1 -1 30432 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 342 271 1 172 91 17 17 289 -1 unnamed_device 24.5 MiB 0.23 777 13351 4773 6428 2150 63.5 MiB 0.11 0.00 3.69009 -122.34 -3.69009 3.69009 0.33 0.000688999 0.000639455 0.047794 0.0443687 -1 -1 -1 -1 40 2451 40 6.95648e+06 390843 706193. 2443.58 2.28 0.208193 0.181318 26914 176310 -1 1989 23 1600 2424 223141 68263 3.89406 3.89406 -135.843 -3.89406 0 0 926341. 3205.33 0.04 0.12 0.15 -1 -1 0.04 0.0334966 0.029147 79 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_022.v common 4.94 vpr 63.62 MiB -1 -1 0.25 18268 1 0.03 -1 -1 30280 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65148 32 32 372 300 1 200 80 17 17 289 -1 unnamed_device 24.6 MiB 1.09 929 10228 2968 5474 1786 63.6 MiB 0.10 0.00 4.43786 -126.086 -4.43786 4.43786 0.33 0.000725922 0.000674137 0.0459557 0.042749 -1 -1 -1 -1 52 2444 39 6.95648e+06 231611 926341. 3205.33 1.71 0.211794 0.184632 29218 227130 -1 1697 21 1603 2467 172559 43849 3.84822 3.84822 -125.024 -3.84822 0 0 1.14541e+06 3963.36 0.04 0.08 0.18 -1 -1 0.04 0.0302014 0.0263891 82 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_023.v common 2.81 vpr 63.27 MiB -1 -1 0.22 18188 1 0.02 -1 -1 30624 -1 -1 14 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 26 32 190 182 1 104 72 17 17 289 -1 unnamed_device 23.9 MiB 0.33 469 6926 2796 3691 439 63.3 MiB 0.05 0.00 2.27636 -67.9936 -2.27636 2.27636 0.35 0.000429337 0.000398799 0.0215449 0.020025 -1 -1 -1 -1 32 1196 21 6.95648e+06 202660 586450. 2029.24 0.59 0.0725739 0.0635235 25474 144626 -1 953 24 615 774 90885 31923 2.28603 2.28603 -73.7824 -2.28603 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0199648 0.017303 43 30 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_024.v common 8.18 vpr 63.14 MiB -1 -1 0.15 17796 1 0.03 -1 -1 30324 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 285 227 1 159 81 17 17 289 -1 unnamed_device 24.1 MiB 0.45 719 9531 2772 5216 1543 63.1 MiB 0.09 0.00 4.35141 -115.734 -4.35141 4.35141 0.34 0.00062324 0.000578477 0.03622 0.0336562 -1 -1 -1 -1 42 2136 41 6.95648e+06 246087 744469. 2576.02 5.73 0.308778 0.265688 27202 183097 -1 1474 23 1312 2219 179928 44050 4.15656 4.15656 -120.492 -4.15656 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0278794 0.0242966 66 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 2.64 vpr 63.15 MiB -1 -1 0.11 17612 1 0.03 -1 -1 29988 -1 -1 10 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 23.8 MiB 0.10 456 10459 4198 5595 666 63.1 MiB 0.07 0.00 2.13126 -69.3153 -2.13126 2.13126 0.31 0.00042468 0.000394535 0.0302253 0.0280834 -1 -1 -1 -1 36 1204 23 6.95648e+06 144757 648988. 2245.63 0.91 0.11542 0.100517 26050 158493 -1 915 21 632 749 65534 16835 2.05118 2.05118 -75.2428 -2.05118 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0176879 0.0153969 43 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_026.v common 3.91 vpr 63.34 MiB -1 -1 0.23 18124 1 0.03 -1 -1 30152 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 32 32 300 245 1 159 83 17 17 289 -1 unnamed_device 24.2 MiB 0.46 705 11063 3344 5374 2345 63.3 MiB 0.09 0.00 4.42909 -119.059 -4.42909 4.42909 0.34 0.000632235 0.000588523 0.0414738 0.0385764 -1 -1 -1 -1 42 1926 27 6.95648e+06 275038 744469. 2576.02 1.35 0.176041 0.153466 27202 183097 -1 1512 20 1112 1881 126839 32424 3.69636 3.69636 -116.75 -3.69636 0 0 949917. 3286.91 0.04 0.07 0.15 -1 -1 0.04 0.0258126 0.0225697 67 24 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_027.v common 3.35 vpr 63.43 MiB -1 -1 0.22 17828 1 0.03 -1 -1 30316 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 24.2 MiB 0.18 1111 14983 4654 8769 1560 63.4 MiB 0.12 0.00 2.9965 -108.481 -2.9965 2.9965 0.33 0.000637683 0.000592435 0.0491689 0.0456907 -1 -1 -1 -1 36 2380 21 6.95648e+06 390843 648988. 2245.63 1.14 0.174104 0.152271 26050 158493 -1 2077 22 1257 1942 162231 34962 3.00062 3.00062 -113.678 -3.00062 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0273556 0.0238501 77 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_028.v common 4.13 vpr 64.05 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30268 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65592 32 32 338 277 1 172 87 17 17 289 -1 unnamed_device 24.3 MiB 0.61 815 11991 3979 6088 1924 64.1 MiB 0.06 0.00 4.25013 -125.291 -4.25013 4.25013 0.25 0.00030205 0.000277272 0.0210826 0.0194187 -1 -1 -1 -1 44 2504 50 6.95648e+06 332941 787024. 2723.27 1.53 0.179622 0.15507 27778 195446 -1 1851 23 1415 2385 195085 45432 4.07246 4.07246 -131.405 -4.07246 0 0 997811. 3452.63 0.06 0.10 0.16 -1 -1 0.06 0.0384545 0.0340278 74 50 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_029.v common 3.59 vpr 63.65 MiB -1 -1 0.18 18148 1 0.03 -1 -1 30076 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65176 32 32 284 241 1 139 79 17 17 289 -1 unnamed_device 24.3 MiB 0.44 636 11740 4501 5598 1641 63.6 MiB 0.10 0.00 2.8872 -98.3416 -2.8872 2.8872 0.33 0.000600815 0.000558186 0.0439891 0.0409118 -1 -1 -1 -1 36 2014 26 6.95648e+06 217135 648988. 2245.63 1.18 0.166398 0.144912 26050 158493 -1 1620 23 1058 1616 135085 32903 3.47502 3.47502 -113.126 -3.47502 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0266523 0.0231135 57 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_030.v common 3.40 vpr 63.58 MiB -1 -1 0.14 18124 1 0.03 -1 -1 30096 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65108 30 32 262 227 1 134 84 17 17 289 -1 unnamed_device 24.0 MiB 0.24 598 12894 4167 6970 1757 63.6 MiB 0.10 0.00 3.17414 -94.0877 -3.17414 3.17414 0.34 0.000573241 0.00052658 0.0418466 0.0387546 -1 -1 -1 -1 38 1729 50 6.95648e+06 318465 678818. 2348.85 1.28 0.180547 0.156592 26626 170182 -1 1167 20 965 1502 93858 23736 2.85952 2.85952 -93.9328 -2.85952 0 0 902133. 3121.57 0.04 0.06 0.14 -1 -1 0.04 0.0228669 0.0198687 60 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_031.v common 3.67 vpr 63.50 MiB -1 -1 0.17 18060 1 0.03 -1 -1 30096 -1 -1 21 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65028 28 32 260 223 1 135 81 17 17 289 -1 unnamed_device 23.9 MiB 0.20 526 9881 3467 4910 1504 63.5 MiB 0.08 0.00 2.9041 -89.8524 -2.9041 2.9041 0.35 0.000561846 0.000519378 0.0338285 0.0314291 -1 -1 -1 -1 44 1510 25 6.95648e+06 303989 787024. 2723.27 1.54 0.153363 0.133271 27778 195446 -1 1252 20 976 1638 120916 31896 3.14012 3.14012 -100.347 -3.14012 0 0 997811. 3452.63 0.04 0.06 0.16 -1 -1 0.04 0.0226749 0.0197469 60 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_032.v common 3.36 vpr 63.54 MiB -1 -1 0.20 17740 1 0.02 -1 -1 30304 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 23.9 MiB 0.12 872 7412 1986 4690 736 63.5 MiB 0.07 0.00 3.33963 -114.641 -3.33963 3.33963 0.34 0.000569591 0.000529726 0.0281963 0.026277 -1 -1 -1 -1 36 2003 21 6.95648e+06 188184 648988. 2245.63 1.37 0.144816 0.125617 26050 158493 -1 1836 21 1303 1920 176626 40606 3.03682 3.03682 -116.712 -3.03682 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0242923 0.0211886 59 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_033.v common 3.55 vpr 63.59 MiB -1 -1 0.23 18256 1 0.03 -1 -1 30228 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65120 31 32 271 231 1 143 88 17 17 289 -1 unnamed_device 24.3 MiB 0.20 648 8278 1868 6118 292 63.6 MiB 0.08 0.00 3.26818 -103.77 -3.26818 3.26818 0.34 0.000593505 0.000551506 0.0271878 0.0252563 -1 -1 -1 -1 38 2153 30 6.95648e+06 361892 678818. 2348.85 1.39 0.152159 0.131517 26626 170182 -1 1564 20 1067 1757 135431 31600 3.25942 3.25942 -106.518 -3.25942 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65800 32 32 367 282 1 193 97 17 17 289 -1 unnamed_device 24.6 MiB 0.36 911 15193 4522 7149 3522 64.3 MiB 0.12 0.00 4.10963 -121.284 -4.10963 4.10963 0.35 0.000733576 0.00068136 0.0533783 0.0495534 -1 -1 -1 -1 46 2654 40 6.95648e+06 477698 828058. 2865.25 1.98 0.238984 0.209506 28066 200906 -1 2029 21 1409 2479 179633 42774 3.83601 3.83601 -125.609 -3.83601 0 0 1.01997e+06 3529.29 0.04 0.08 0.14 -1 -1 0.04 0.0318055 0.0278818 91 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_036.v common 4.86 vpr 63.55 MiB -1 -1 0.24 18284 1 0.03 -1 -1 30264 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 349 284 1 175 90 17 17 289 -1 unnamed_device 24.2 MiB 0.44 1076 13557 4204 7841 1512 63.4 MiB 0.12 0.00 3.1047 -113.61 -3.1047 3.1047 0.34 0.000697786 0.000646852 0.0494433 0.0459023 -1 -1 -1 -1 40 2543 44 6.95648e+06 376368 706193. 2443.58 1.74 0.218193 0.190007 26914 176310 -1 2184 21 1482 2483 204735 44012 3.10107 3.10107 -117.005 -3.10107 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0301622 0.026338 78 53 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_047.v common 4.11 vpr 63.94 MiB -1 -1 0.22 17896 1 0.03 -1 -1 30096 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65476 32 32 291 230 1 161 83 17 17 289 -1 unnamed_device 24.3 MiB 0.30 727 11963 4343 5980 1640 63.9 MiB 0.11 0.00 4.01417 -117.763 -4.01417 4.01417 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65688 32 32 382 305 1 184 93 17 17 289 -1 unnamed_device 24.5 MiB 0.29 1111 12693 3643 7264 1786 64.1 MiB 0.12 0.00 3.72599 -128.052 -3.72599 3.72599 0.33 0.000745259 0.000691766 0.0478964 0.0445264 -1 -1 -1 -1 38 2710 39 6.95648e+06 419795 678818. 2348.85 1.56 0.214278 0.18655 26626 170182 -1 2296 18 1570 2524 191579 41155 3.34267 3.34267 -126.01 -3.34267 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0273508 0.0239439 87 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_051.v common 3.83 vpr 63.89 MiB -1 -1 0.23 18064 1 0.03 -1 -1 30284 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65424 32 32 306 248 1 160 86 17 17 289 -1 unnamed_device 24.2 MiB 0.41 714 10859 2768 5884 2207 63.9 MiB 0.09 0.00 4.21985 -115.841 -4.21985 4.21985 0.33 0.00064033 0.000594103 0.0392175 0.0364135 -1 -1 -1 -1 42 2281 32 6.95648e+06 318465 744469. 2576.02 1.40 0.175454 0.152417 27202 183097 -1 1639 21 1114 1829 140230 35033 4.10836 4.10836 -123.57 -4.10836 0 0 949917. 3286.91 0.04 0.07 0.15 -1 -1 0.04 0.0269904 0.0236075 70 24 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_052.v common 5.19 vpr 63.96 MiB -1 -1 0.16 18348 1 0.03 -1 -1 30124 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65500 32 32 319 257 1 191 80 17 17 289 -1 unnamed_device 24.2 MiB 0.86 1059 13152 4245 6889 2018 64.0 MiB 0.12 0.00 4.15748 -130.263 -4.15748 4.15748 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/home/elgamma8/research/release/vtr-verilog-to-routing 65452 32 32 341 285 1 183 79 17 17 289 -1 unnamed_device 24.2 MiB 0.89 876 11740 4893 6611 236 63.9 MiB 0.11 0.00 3.1615 -120.209 -3.1615 3.1615 0.33 0.000675863 0.000627489 0.0490628 0.0456216 -1 -1 -1 -1 42 2500 26 6.95648e+06 217135 744469. 2576.02 1.50 0.18957 0.165472 27202 183097 -1 2089 22 1764 2523 256092 54542 3.40957 3.40957 -131.031 -3.40957 0 0 949917. 3286.91 0.04 0.09 0.15 -1 -1 0.04 0.0290865 0.0252833 73 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_057.v common 6.03 vpr 64.38 MiB -1 -1 0.26 18368 1 0.03 -1 -1 30288 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65928 32 32 387 293 1 226 83 17 17 289 -1 unnamed_device 24.8 MiB 0.86 1199 13043 4951 6384 1708 64.4 MiB 0.14 0.00 4.83158 -154.41 -4.83158 4.83158 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66024 32 32 431 332 1 227 82 17 17 289 -1 unnamed_device 24.8 MiB 1.43 1077 13076 5478 7292 306 64.5 MiB 0.14 0.00 5.30235 -160.109 -5.30235 5.30235 0.33 0.000839666 0.00078032 0.064804 0.0602835 -1 -1 -1 -1 46 3075 31 6.95648e+06 260562 828058. 2865.25 1.52 0.244686 0.214294 28066 200906 -1 2516 23 2235 3373 300793 65578 4.88325 4.88325 -159.437 -4.88325 0 0 1.01997e+06 3529.29 0.04 0.11 0.16 -1 -1 0.04 0.0373225 0.0326244 95 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 4.87 vpr 63.32 MiB -1 -1 0.15 18504 1 0.03 -1 -1 30536 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 32 32 336 268 1 169 89 17 17 289 -1 unnamed_device 24.4 MiB 0.98 769 14543 4279 7650 2614 63.3 MiB 0.13 0.00 4.37605 -128.976 -4.37605 4.37605 0.33 0.00068609 0.000637719 0.0529336 0.0491554 -1 -1 -1 -1 36 2640 45 6.95648e+06 361892 648988. 2245.63 1.95 0.220043 0.191748 26050 158493 -1 1899 19 1368 2103 168161 39340 4.52236 4.52236 -147.419 -4.52236 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0268261 0.0234869 75 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_062.v common 3.23 vpr 63.44 MiB -1 -1 0.21 17720 1 0.03 -1 -1 30332 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64964 32 32 231 199 1 136 81 17 17 289 -1 unnamed_device 23.9 MiB 0.17 862 10581 3669 5472 1440 63.4 MiB 0.08 0.00 2.966 -103.091 -2.966 2.966 0.33 0.000535623 0.000498652 0.0341868 0.0318378 -1 -1 -1 -1 34 2090 46 6.95648e+06 246087 618332. 2139.56 1.15 0.159354 0.137994 25762 151098 -1 1817 19 973 1591 134001 28878 2.85037 2.85037 -106.975 -2.85037 0 0 787024. 2723.27 0.03 0.06 0.12 -1 -1 0.03 0.0206185 0.0179498 55 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_063.v common 9.87 vpr 63.93 MiB -1 -1 0.25 18488 1 0.03 -1 -1 30120 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65464 32 32 349 273 1 184 95 17 17 289 -1 unnamed_device 24.1 MiB 0.34 1079 15647 5481 7915 2251 63.9 MiB 0.14 0.00 4.80547 -133.695 -4.80547 4.80547 0.34 0.000706749 0.000655878 0.0539142 0.0500534 -1 -1 -1 -1 36 3258 49 6.95648e+06 448746 648988. 2245.63 7.26 0.323114 0.280424 26050 158493 -1 2539 33 2032 3613 445607 138907 4.93896 4.93896 -147.631 -4.93896 0 0 828058. 2865.25 0.03 0.17 0.13 -1 -1 0.03 0.0442362 0.0384999 85 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_064.v common 2.85 vpr 63.78 MiB -1 -1 0.22 17988 1 0.03 -1 -1 30204 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65308 32 32 247 207 1 142 80 17 17 289 -1 unnamed_device 24.2 MiB 0.24 726 11088 4552 6360 176 63.8 MiB 0.09 0.00 2.9793 -102.962 -2.9793 2.9793 0.33 0.000555866 0.000516817 0.0383305 0.035649 -1 -1 -1 -1 32 2182 43 6.95648e+06 231611 586450. 2029.24 0.75 0.122287 0.107128 25474 144626 -1 1659 22 1307 1969 160538 36320 3.10097 3.10097 -116.017 -3.10097 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0134192 0.0118545 58 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_065.v common 4.25 vpr 63.77 MiB -1 -1 0.22 18148 1 0.03 -1 -1 30204 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 30 32 278 235 1 141 87 17 17 289 -1 unnamed_device 24.3 MiB 0.57 775 12567 4624 6004 1939 63.8 MiB 0.10 0.00 3.23198 -106.153 -3.23198 3.23198 0.35 0.000590718 0.000549282 0.0409618 0.0381017 -1 -1 -1 -1 36 1945 49 6.95648e+06 361892 648988. 2245.63 1.58 0.19865 0.172724 26050 158493 -1 1651 24 1219 1928 159003 35682 3.51472 3.51472 -122.539 -3.51472 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0269613 0.0233639 64 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 5.16 vpr 63.41 MiB -1 -1 0.25 18380 1 0.03 -1 -1 30368 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 29 32 355 287 1 191 80 17 17 289 -1 unnamed_device 24.5 MiB 1.05 862 13840 5371 6156 2313 63.4 MiB 0.13 0.00 3.49789 -109.385 -3.49789 3.49789 0.33 0.000692113 0.000642977 0.05874 0.0545889 -1 -1 -1 -1 42 2967 32 6.95648e+06 275038 744469. 2576.02 1.93 0.213693 0.18699 27202 183097 -1 2258 20 1883 2806 223583 51789 3.35977 3.35977 -120.027 -3.35977 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0279475 0.0244354 81 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_067.v common 3.65 vpr 63.48 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30320 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 358 289 1 171 83 17 17 289 -1 unnamed_device 24.5 MiB 0.52 803 13763 3951 8222 1590 63.5 MiB 0.13 0.00 4.16158 -131.727 -4.16158 4.16158 0.33 0.000704942 0.00065495 0.0566393 0.0526354 -1 -1 -1 -1 36 2250 32 6.95648e+06 275038 648988. 2245.63 1.05 0.205864 0.179723 26050 158493 -1 1841 23 1629 2363 177966 42287 4.23702 4.23702 -141.59 -4.23702 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.031816 0.0277356 74 54 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_068.v common 4.55 vpr 63.49 MiB -1 -1 0.26 18396 1 0.03 -1 -1 30200 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65012 32 32 353 285 1 175 84 17 17 289 -1 unnamed_device 24.5 MiB 0.59 796 11064 4038 5325 1701 63.5 MiB 0.10 0.00 4.14068 -130.872 -4.14068 4.14068 0.33 0.000702369 0.000652314 0.0451848 0.0419956 -1 -1 -1 -1 42 2677 27 6.95648e+06 289514 744469. 2576.02 1.44 0.192639 0.167021 27202 183097 -1 2130 23 1519 2391 190633 45446 4.10536 4.10536 -140.291 -4.10536 0 0 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 31 32 319 272 1 165 78 17 17 289 -1 unnamed_device 24.2 MiB 1.36 768 11366 3602 6339 1425 63.4 MiB 0.10 0.00 3.45953 -112.445 -3.45953 3.45953 0.33 0.000648061 0.000602589 0.0466726 0.0434327 -1 -1 -1 -1 40 2406 47 6.95648e+06 217135 706193. 2443.58 6.67 0.308184 0.265354 26914 176310 -1 1941 30 1706 2536 269805 79255 3.50087 3.50087 -130.33 -3.50087 0 0 926341. 3205.33 0.04 0.12 0.14 -1 -1 0.04 0.0358129 0.0310119 66 64 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_071.v common 3.25 vpr 63.91 MiB -1 -1 0.27 18412 1 0.03 -1 -1 30368 -1 -1 29 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65672 32 32 350 275 1 201 81 17 17 289 -1 unnamed_device 24.5 MiB 1.27 1129 13906 5547 6652 1707 64.1 MiB 0.15 0.00 4.25269 -145.404 -4.25269 4.25269 0.33 0.00070617 0.000655642 0.0622307 0.0578098 -1 -1 -1 -1 46 2914 38 6.95648e+06 246087 828058. 2865.25 1.96 0.211017 0.18524 28066 200906 -1 2416 22 1670 2541 234855 47792 4.12906 4.12906 -150.919 -4.12906 0 0 1.01997e+06 3529.29 0.04 0.09 0.16 -1 -1 0.04 0.0305654 0.0267071 83 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_077.v common 4.62 vpr 63.66 MiB -1 -1 0.15 18396 1 0.03 -1 -1 30276 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65184 32 32 385 308 1 176 91 17 17 289 -1 unnamed_device 24.6 MiB 0.98 819 15595 5661 7312 2622 63.7 MiB 0.14 0.00 4.05218 -132.756 -4.05218 4.05218 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/home/elgamma8/research/release/vtr-verilog-to-routing 65128 32 32 340 270 1 193 82 17 17 289 -1 unnamed_device 24.7 MiB 1.18 893 10762 4413 5950 399 63.6 MiB 0.10 0.00 4.53151 -135.826 -4.53151 4.53151 0.34 0.000687293 0.000638631 0.0444127 0.041307 -1 -1 -1 -1 44 2872 50 6.95648e+06 260562 787024. 2723.27 2.17 0.218431 0.190231 27778 195446 -1 2052 21 1735 2824 235601 56350 4.03512 4.03512 -138.699 -4.03512 0 0 997811. 3452.63 0.04 0.09 0.16 -1 -1 0.04 0.0293526 0.0257142 80 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_082.v common 4.77 vpr 64.19 MiB -1 -1 0.26 18356 1 0.03 -1 -1 30112 -1 -1 16 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 31 32 340 275 1 188 79 17 17 289 -1 unnamed_device 24.6 MiB 1.18 809 10557 4353 5772 432 64.2 MiB 0.10 0.00 5.4697 -148.249 -5.4697 5.4697 0.34 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0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64972 29 32 378 310 1 170 86 17 17 289 -1 unnamed_device 24.4 MiB 0.65 761 11048 4050 5112 1886 63.4 MiB 0.10 0.00 3.45953 -109.092 -3.45953 3.45953 0.33 0.00071549 0.000663573 0.0445526 0.0413859 -1 -1 -1 -1 36 2656 42 6.95648e+06 361892 648988. 2245.63 2.06 0.211083 0.183304 26050 158493 -1 2025 23 1711 2675 260514 63101 3.36572 3.36572 -118.625 -3.36572 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0319609 0.0278008 78 85 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_086.v common 3.67 vpr 63.50 MiB -1 -1 0.21 17852 1 0.03 -1 -1 30432 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 243 205 1 140 76 17 17 289 -1 unnamed_device 23.9 MiB 0.62 631 7916 2533 3644 1739 63.5 MiB 0.07 0.00 3.37543 -105.078 -3.37543 3.37543 0.34 0.000557086 0.000517598 0.0302229 0.0281436 -1 -1 -1 -1 36 1928 35 6.95648e+06 173708 648988. 2245.63 1.08 0.134647 0.116993 26050 158493 -1 1572 21 1088 1579 130575 31333 2.97567 2.97567 -108.699 -2.97567 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0238637 0.0206275 55 3 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_087.v common 6.31 vpr 64.27 MiB -1 -1 0.24 18476 1 0.03 -1 -1 30208 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65816 32 32 373 302 1 170 91 17 17 289 -1 unnamed_device 24.6 MiB 2.58 966 14983 5125 7592 2266 64.3 MiB 0.13 0.00 4.09512 -134.157 -4.09512 4.09512 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64992 31 32 245 205 1 144 79 17 17 289 -1 unnamed_device 23.9 MiB 0.21 813 9543 2639 6153 751 63.5 MiB 0.08 0.00 3.28943 -107.171 -3.28943 3.28943 0.33 0.000552058 0.000513941 0.0332108 0.0309347 -1 -1 -1 -1 30 2091 23 6.95648e+06 231611 556674. 1926.21 0.75 0.101378 0.0892292 25186 138497 -1 1788 22 1361 2041 160912 34813 2.97572 2.97572 -111.872 -2.97572 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0241773 0.0210133 59 4 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_091.v common 4.99 vpr 64.19 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30480 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65732 32 32 348 274 1 203 82 17 17 289 -1 unnamed_device 24.6 MiB 1.05 911 13788 5176 6984 1628 64.2 MiB 0.13 0.00 4.12648 -135.504 -4.12648 4.12648 0.33 0.000699074 0.000649372 0.0567967 0.0528143 -1 -1 -1 -1 42 2629 45 6.95648e+06 260562 744469. 2576.02 1.88 0.220087 0.192147 27202 183097 -1 1945 23 2032 2844 200495 50646 3.92702 3.92702 -143.111 -3.92702 0 0 949917. 3286.91 0.03 0.05 0.11 -1 -1 0.03 0.0177332 0.0156956 82 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_092.v common 5.22 vpr 64.19 MiB -1 -1 0.15 18440 1 0.03 -1 -1 30296 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 356 289 1 195 87 17 17 289 -1 unnamed_device 24.6 MiB 0.74 1160 14487 4690 8180 1617 64.2 MiB 0.13 0.00 4.82888 -148.206 -4.82888 4.82888 0.33 0.000712138 0.000661648 0.0557283 0.0517813 -1 -1 -1 -1 34 3080 48 6.95648e+06 332941 618332. 2139.56 2.48 0.235318 0.205766 25762 151098 -1 2599 30 2158 3120 284278 71454 4.92206 4.92206 -162.846 -4.92206 0 0 787024. 2723.27 0.03 0.12 0.12 -1 -1 0.03 0.0391423 0.0339394 84 56 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_093.v common 3.98 vpr 63.39 MiB -1 -1 0.24 18200 1 0.03 -1 -1 30160 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64912 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 24.4 MiB 0.22 1004 12903 4488 6360 2055 63.4 MiB 0.12 0.00 4.68117 -141.413 -4.68117 4.68117 0.33 0.000720343 0.00066916 0.0469684 0.0436423 -1 -1 -1 -1 46 2499 25 6.95648e+06 419795 828058. 2865.25 1.60 0.19455 0.170056 28066 200906 -1 2004 22 1773 2931 237482 50990 4.37331 4.37331 -138.259 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-1 19 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 27 32 255 219 1 128 78 17 17 289 -1 unnamed_device 24.0 MiB 0.22 722 7050 2096 4338 616 63.5 MiB 0.06 0.00 2.9635 -93.8648 -2.9635 2.9635 0.33 0.000545241 0.00050719 0.0250802 0.0233661 -1 -1 -1 -1 30 1680 25 6.95648e+06 275038 556674. 1926.21 0.56 0.0935952 0.0816389 25186 138497 -1 1383 22 1105 1543 104085 23514 2.95552 2.95552 -103.065 -2.95552 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0237341 0.0205911 59 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_096.v common 5.41 vpr 64.35 MiB -1 -1 0.26 18844 1 0.03 -1 -1 30304 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65892 32 32 421 327 1 224 82 17 17 289 -1 unnamed_device 24.7 MiB 0.89 1281 15390 5999 6748 2643 64.3 MiB 0.16 0.00 3.89055 -132.538 -3.89055 3.89055 0.33 0.000813615 0.000756466 0.0730744 0.0678737 -1 -1 -1 -1 42 3669 39 6.95648e+06 260562 744469. 2576.02 2.12 0.258872 0.226973 27202 183097 -1 3041 54 3734 6186 866572 315736 4.00842 4.00842 -141.9 -4.00842 0 0 949917. 3286.91 0.04 0.33 0.15 -1 -1 0.04 0.0739409 0.0637852 93 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_097.v common 7.93 vpr 63.49 MiB -1 -1 0.21 18296 1 0.04 -1 -1 30416 -1 -1 17 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65016 31 32 365 296 1 191 80 17 17 289 -1 unnamed_device 24.5 MiB 3.68 1050 11776 4191 5452 2133 63.5 MiB 0.12 0.00 5.15055 -152.017 -5.15055 5.15055 0.35 0.000718301 0.000667584 0.0516793 0.0480382 -1 -1 -1 -1 38 2588 31 6.95648e+06 246087 678818. 2348.85 1.94 0.206918 0.180683 26626 170182 -1 2229 25 1746 2589 260957 73631 4.60096 4.60096 -155.355 -4.60096 0 0 902133. 3121.57 0.04 0.12 0.14 -1 -1 0.04 0.035326 0.030777 81 64 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_098.v common 6.94 vpr 63.92 MiB -1 -1 0.17 18372 1 0.03 -1 -1 30488 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65456 32 32 331 280 1 171 77 17 17 289 -1 unnamed_device 24.2 MiB 3.06 846 8879 3445 4513 921 63.9 MiB 0.09 0.00 3.71344 -127.299 -3.71344 3.71344 0.33 0.000662152 0.000616044 0.0396078 0.0367971 -1 -1 -1 -1 34 2721 49 6.95648e+06 188184 618332. 2139.56 1.88 0.20583 0.178674 25762 151098 -1 2098 21 1594 2255 229437 53251 3.98836 3.98836 -149.148 -3.98836 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0275507 0.0240338 69 65 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_099.v common 4.40 vpr 63.30 MiB -1 -1 0.24 18352 1 0.03 -1 -1 30464 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 326 263 1 169 91 17 17 289 -1 unnamed_device 24.2 MiB 0.19 870 13759 5668 7640 451 63.3 MiB 0.12 0.00 4.15778 -125.912 -4.15778 4.15778 0.33 0.000671759 0.00062482 0.0479104 0.0444404 -1 -1 -1 -1 38 2577 27 6.95648e+06 390843 678818. 2348.85 2.16 0.187441 0.163621 26626 170182 -1 1942 23 1477 2327 174711 43122 4.19391 4.19391 -133.252 -4.19391 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0297229 0.0258967 78 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_100.v common 4.48 vpr 63.51 MiB -1 -1 0.13 18436 1 0.03 -1 -1 30584 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65032 31 32 373 294 1 188 89 17 17 289 -1 unnamed_device 24.5 MiB 0.47 873 14543 4744 7116 2683 63.5 MiB 0.13 0.00 4.28865 -123.708 -4.28865 4.28865 0.33 0.000725918 0.000673454 0.0562397 0.05222 -1 -1 -1 -1 36 2840 47 6.95648e+06 376368 648988. 2245.63 1.95 0.231301 0.201645 26050 158493 -1 2024 22 1600 2407 161278 40379 4.11982 4.11982 -132.03 -4.11982 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0319741 0.0279464 86 50 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_101.v common 4.86 vpr 63.29 MiB -1 -1 0.23 18392 1 0.03 -1 -1 30376 -1 -1 26 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 30 32 325 268 1 165 88 17 17 289 -1 unnamed_device 24.2 MiB 0.47 772 13153 5458 7079 616 63.3 MiB 0.11 0.00 3.0694 -97.4086 -3.0694 3.0694 0.33 0.000653895 0.000606982 0.0467319 0.0433975 -1 -1 -1 -1 40 2419 50 6.95648e+06 376368 706193. 2443.58 2.36 0.206789 0.179782 26914 176310 -1 1811 25 1374 2302 189877 47043 3.14317 3.14317 -106.853 -3.14317 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0309509 0.0268435 73 51 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_102.v common 5.54 vpr 64.13 MiB -1 -1 0.23 18252 1 0.03 -1 -1 30276 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65668 32 32 350 275 1 209 82 17 17 289 -1 unnamed_device 24.5 MiB 0.97 990 11296 4658 6209 429 64.1 MiB 0.11 0.00 4.17918 -138.94 -4.17918 4.17918 0.33 0.000701844 0.000651419 0.0471705 0.0438467 -1 -1 -1 -1 56 2616 30 6.95648e+06 260562 973134. 3367.25 2.33 0.203793 0.178063 29794 239141 -1 2154 22 1945 2922 305600 70699 3.94732 3.94732 -136.513 -3.94732 0 0 1.19926e+06 4149.71 0.05 0.11 0.19 -1 -1 0.05 0.0317994 0.0278462 87 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 4.21 vpr 63.58 MiB -1 -1 0.26 18312 1 0.03 -1 -1 30104 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65108 32 32 386 307 1 187 93 17 17 289 -1 unnamed_device 24.5 MiB 0.41 1037 8913 3105 4740 1068 63.6 MiB 0.08 0.00 3.51453 -125.823 -3.51453 3.51453 0.33 0.000744025 0.000689753 0.0342182 0.0318076 -1 -1 -1 -1 34 2812 26 6.95648e+06 419795 618332. 2139.56 1.61 0.190691 0.165539 25762 151098 -1 2314 20 1644 2351 206052 44179 3.21107 3.21107 -131.121 -3.21107 0 0 787024. 2723.27 0.03 0.09 0.12 -1 -1 0.03 0.0303118 0.026521 89 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_104.v common 5.39 vpr 63.66 MiB -1 -1 0.23 18188 1 0.03 -1 -1 30236 -1 -1 14 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65192 29 32 269 229 1 131 75 17 17 289 -1 unnamed_device 24.0 MiB 2.38 503 8765 3597 4670 498 63.7 MiB 0.07 0.00 3.77092 -99.7617 -3.77092 3.77092 0.34 0.000572882 0.00053298 0.0340432 0.0316733 -1 -1 -1 -1 36 1465 44 6.95648e+06 202660 648988. 2245.63 1.01 0.166036 0.14345 26050 158493 -1 1156 28 1151 1593 112172 28468 3.00497 3.00497 -101.661 -3.00497 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0297575 0.0257352 55 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_105.v common 7.27 vpr 63.48 MiB -1 -1 0.23 18364 1 0.03 -1 -1 30324 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 310 266 1 169 78 17 17 289 -1 unnamed_device 24.3 MiB 0.79 819 11864 4595 6100 1169 63.5 MiB 0.10 0.00 3.1157 -110.455 -3.1157 3.1157 0.33 0.000617386 0.000572641 0.0470302 0.0437382 -1 -1 -1 -1 38 2084 30 6.95648e+06 202660 678818. 2348.85 4.41 0.281604 0.242479 26626 170182 -1 1651 21 1499 1900 148274 33656 3.11207 3.11207 -115.72 -3.11207 0 0 902133. 3121.57 0.03 0.07 0.14 -1 -1 0.03 0.0261644 0.0227736 66 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_106.v common 13.24 vpr 63.42 MiB -1 -1 0.25 18348 1 0.08 -1 -1 30416 -1 -1 31 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 31 32 326 261 1 170 94 17 17 289 -1 unnamed_device 24.2 MiB 0.29 807 17347 5453 8954 2940 63.4 MiB 0.14 0.00 3.99218 -119.823 -3.99218 3.99218 0.33 0.000669928 0.000620402 0.0570896 0.0529137 -1 -1 -1 -1 38 2796 47 6.95648e+06 448746 678818. 2348.85 10.76 0.37726 0.326276 26626 170182 -1 2010 24 1596 2698 256761 68889 4.44846 4.44846 -129.239 -4.44846 0 0 902133. 3121.57 0.03 0.10 0.14 -1 -1 0.03 0.031009 0.0270206 80 33 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_107.v common 4.22 vpr 63.23 MiB -1 -1 0.25 17992 1 0.03 -1 -1 30348 -1 -1 16 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 29 32 262 224 1 162 77 17 17 289 -1 unnamed_device 24.2 MiB 0.73 751 10183 4226 5557 400 63.2 MiB 0.09 0.00 4.02427 -114.705 -4.02427 4.02427 0.34 0.000562056 0.000522712 0.0372432 0.0346484 -1 -1 -1 -1 36 2194 39 6.95648e+06 231611 648988. 2245.63 1.48 0.169094 0.146733 26050 158493 -1 1759 20 1128 1442 125538 30209 3.91432 3.91432 -123.418 -3.91432 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.022937 0.0199794 66 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_108.v common 4.19 vpr 63.57 MiB -1 -1 0.20 18176 1 0.03 -1 -1 30004 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 32 32 278 238 1 144 76 17 17 289 -1 unnamed_device 24.2 MiB 0.99 681 10636 4393 6016 227 63.6 MiB 0.10 0.00 3.83566 -112.084 -3.83566 3.83566 0.33 0.000597626 0.000555977 0.0419891 0.0390707 -1 -1 -1 -1 40 1767 23 6.95648e+06 173708 706193. 2443.58 1.10 0.159787 0.139126 26914 176310 -1 1559 22 1276 1977 179411 40906 3.25122 3.25122 -115.603 -3.25122 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65324 31 32 265 230 1 159 77 17 17 289 -1 unnamed_device 24.3 MiB 1.45 950 11650 3937 6122 1591 63.8 MiB 0.10 0.00 3.38663 -109.663 -3.38663 3.38663 0.33 0.000568518 0.000528957 0.0431381 0.040133 -1 -1 -1 -1 34 2390 49 6.95648e+06 202660 618332. 2139.56 2.03 0.185926 0.161626 25762 151098 -1 2037 21 1191 1753 178422 38700 3.51307 3.51307 -126.052 -3.51307 0 0 787024. 2723.27 0.03 0.07 0.13 -1 -1 0.03 0.0243167 0.0212093 61 34 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_111.v common 4.51 vpr 63.45 MiB -1 -1 0.24 18408 1 0.03 -1 -1 30004 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 318 257 1 190 80 17 17 289 -1 unnamed_device 24.3 MiB 0.76 833 12292 3904 6196 2192 63.5 MiB 0.11 0.00 4.24288 -124.746 -4.24288 4.24288 0.33 0.000654747 0.00060808 0.0492224 0.0457578 -1 -1 -1 -1 40 2755 42 6.95648e+06 231611 706193. 2443.58 2.25 0.20883 0.182198 26914 176310 -1 1933 21 1493 2038 146228 37477 4.53772 4.53772 -141.377 -4.53772 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.028074 0.024611 76 30 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_116.v common 3.93 vpr 63.96 MiB -1 -1 0.22 18400 1 0.03 -1 -1 30096 -1 -1 25 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65184 25 32 216 194 1 119 82 17 17 289 -1 unnamed_device 24.3 MiB 0.17 476 12186 4413 5265 2508 63.7 MiB 0.08 0.00 3.29759 -75.7686 -3.29759 3.29759 0.33 0.000479342 0.000443744 0.0344437 0.0319592 -1 -1 -1 -1 36 1639 41 6.95648e+06 361892 648988. 2245.63 1.21 0.144471 0.125015 26050 158493 -1 1187 21 863 1360 103903 26463 3.13012 3.13012 -84.3189 -3.13012 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0200072 0.0173432 55 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_127.v common 13.58 vpr 63.39 MiB -1 -1 0.23 18344 1 0.03 -1 -1 30268 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 376 307 1 179 78 17 17 289 -1 unnamed_device 24.4 MiB 0.69 806 10370 3831 4684 1855 63.4 MiB 0.10 0.00 3.9218 -122.886 -3.9218 3.9218 0.34 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-1 -1 18 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 27 32 259 221 1 152 77 17 17 289 -1 unnamed_device 23.8 MiB 0.34 572 10835 3549 5392 1894 63.5 MiB 0.09 0.00 3.41253 -95.9445 -3.41253 3.41253 0.33 0.000550141 0.000512325 0.038635 0.0359856 -1 -1 -1 -1 40 1445 25 6.99608e+06 264882 706193. 2443.58 1.11 0.149802 0.130204 26914 176310 -1 1146 23 1101 1637 114171 28235 3.23432 3.23432 -101.208 -3.23432 0 0 926341. 3205.33 0.04 0.06 0.14 -1 -1 0.04 0.0246258 0.0213493 65 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_008.v common 3.99 vpr 63.69 MiB -1 -1 0.22 17916 1 0.03 -1 -1 30120 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65220 31 32 271 219 1 157 90 17 17 289 -1 unnamed_device 24.4 MiB 0.17 727 10140 3383 5019 1738 63.7 MiB 0.08 0.00 2.73675 -88.7663 -2.73675 2.73675 0.33 0.000595211 0.00055369 0.0323175 0.030008 -1 -1 -1 -1 38 2221 27 6.99608e+06 397324 678818. 2348.85 1.89 0.157817 0.136976 26626 170182 -1 1662 18 1028 1750 116894 29647 3.01977 3.01977 -98.9875 -3.01977 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0219675 0.0191938 69 4 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_009.v common 4.50 vpr 63.79 MiB -1 -1 0.25 18444 1 0.03 -1 -1 30152 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65320 31 32 317 271 1 204 81 17 17 289 -1 unnamed_device 24.0 MiB 0.38 980 13556 5192 6525 1839 63.8 MiB 0.12 0.00 3.3916 -120.616 -3.3916 3.3916 0.33 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65092 32 32 276 237 1 165 78 17 17 289 -1 unnamed_device 23.9 MiB 0.38 879 10204 2698 5461 2045 63.6 MiB 0.09 0.00 3.35769 -110.064 -3.35769 3.35769 0.33 0.000592848 0.000552053 0.0387 0.0360475 -1 -1 -1 -1 38 2132 28 6.99608e+06 206020 678818. 2348.85 0.97 0.160199 0.139218 26626 170182 -1 1867 22 1244 1659 127512 28292 2.95567 2.95567 -112.42 -2.95567 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0255903 0.0222615 65 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 11.21 vpr 64.02 MiB -1 -1 0.23 18352 1 0.03 -1 -1 30428 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65556 32 32 344 272 1 201 82 17 17 289 -1 unnamed_device 24.4 MiB 0.42 989 13788 5751 7551 486 64.0 MiB 0.13 0.00 3.85182 -127.119 -3.85182 3.85182 0.33 0.000695996 0.000645706 0.056467 0.0525052 -1 -1 -1 -1 40 2714 27 6.99608e+06 264882 706193. 2443.58 8.55 0.342056 0.295528 26914 176310 -1 2180 20 1618 2438 198461 44961 3.37586 3.37586 -121.862 -3.37586 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0280737 0.0245708 85 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_014.v common 4.89 vpr 63.34 MiB -1 -1 0.23 18476 1 0.03 -1 -1 30296 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 32 32 363 295 1 228 85 17 17 289 -1 unnamed_device 24.3 MiB 0.49 1022 13849 4401 6534 2914 63.3 MiB 0.13 0.00 4.71142 -142.574 -4.71142 4.71142 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/home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 323 276 1 210 81 17 17 289 -1 unnamed_device 24.7 MiB 0.42 1112 13206 4762 6252 2192 64.2 MiB 0.12 0.00 2.94164 -116.816 -2.94164 2.94164 0.33 0.000653202 0.000607503 0.0515789 0.0479923 -1 -1 -1 -1 38 2627 37 6.99608e+06 250167 678818. 2348.85 2.14 0.19862 0.173499 26626 170182 -1 2110 21 1395 1843 145157 31738 2.96141 2.96141 -120.522 -2.96141 0 0 902133. 3121.57 0.04 0.07 0.15 -1 -1 0.04 0.0270508 0.0236021 83 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_019.v common 4.12 vpr 63.28 MiB -1 -1 0.22 18208 1 0.02 -1 -1 30056 -1 -1 14 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 30 32 222 206 1 135 76 17 17 289 -1 unnamed_device 24.1 MiB 0.27 523 9676 3992 5183 501 63.3 MiB 0.07 0.00 2.34646 -82.0889 -2.34646 2.34646 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65552 32 32 372 300 1 225 84 17 17 289 -1 unnamed_device 24.3 MiB 0.42 1287 11430 3124 6919 1387 64.0 MiB 0.12 0.00 4.28762 -137.056 -4.28762 4.28762 0.34 0.000725791 0.000674218 0.0481271 0.0447389 -1 -1 -1 -1 36 3638 47 6.99608e+06 294314 648988. 2245.63 2.54 0.226737 0.197277 26050 158493 -1 2909 22 2179 3181 270199 57321 4.16172 4.16172 -146.771 -4.16172 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0312828 0.0273115 97 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_023.v common 2.73 vpr 63.21 MiB -1 -1 0.19 18128 1 0.03 -1 -1 30684 -1 -1 16 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 26 32 190 182 1 123 74 17 17 289 -1 unnamed_device 23.7 MiB 0.24 509 11389 4872 5794 723 63.2 MiB 0.08 0.00 2.5304 -71.4335 -2.5304 2.5304 0.36 0.000430528 0.000399577 0.0334196 0.0310487 -1 -1 -1 -1 32 1512 40 6.99608e+06 235451 586450. 2029.24 0.67 0.0982233 0.0860666 25474 144626 -1 1053 19 675 830 60421 15815 2.32772 2.32772 -75.6559 -2.32772 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0167778 0.014619 51 30 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_024.v common 10.38 vpr 63.32 MiB -1 -1 0.13 17988 1 0.03 -1 -1 30404 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 285 227 1 160 81 17 17 289 -1 unnamed_device 24.0 MiB 0.46 809 9531 2907 4788 1836 63.3 MiB 0.08 0.00 4.23145 -111.771 -4.23145 4.23145 0.34 0.000616405 0.000573415 0.0358425 0.0333522 -1 -1 -1 -1 42 2262 42 6.99608e+06 250167 744469. 2576.02 7.98 0.31279 0.269362 27202 183097 -1 1628 23 1395 2382 183546 47317 3.75671 3.75671 -123.108 -3.75671 0 0 949917. 3286.91 0.04 0.08 0.14 -1 -1 0.04 0.0277763 0.0241395 66 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_025.v common 2.85 vpr 62.96 MiB -1 -1 0.21 17552 1 0.02 -1 -1 30000 -1 -1 10 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 173 169 1 111 74 17 17 289 -1 unnamed_device 23.6 MiB 0.11 432 8289 2731 4140 1418 63.0 MiB 0.06 0.00 2.03911 -66.1576 -2.03911 2.03911 0.34 0.00043102 0.000399846 0.0244169 0.0226669 -1 -1 -1 -1 34 1237 26 6.99608e+06 147157 618332. 2139.56 0.86 0.114623 0.0995893 25762 151098 -1 1004 18 606 753 61569 17014 1.93402 1.93402 -73.9607 -1.93402 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 297 233 1 170 91 17 17 289 -1 unnamed_device 24.0 MiB 0.17 933 10087 2140 7381 566 63.1 MiB 0.09 0.00 2.84195 -100.69 -2.84195 2.84195 0.34 0.000645685 0.000599204 0.0341485 0.0317824 -1 -1 -1 -1 36 2408 26 6.99608e+06 397324 648988. 2245.63 1.49 0.170187 0.148059 26050 158493 -1 1956 25 1433 2511 172697 38909 3.03892 3.03892 -108.258 -3.03892 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0302885 0.0263341 77 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_028.v common 4.63 vpr 63.82 MiB -1 -1 0.23 18284 1 0.03 -1 -1 30280 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 338 277 1 204 83 17 17 289 -1 unnamed_device 24.3 MiB 0.52 923 8003 1947 5085 971 63.8 MiB 0.09 0.00 4.17173 -123.211 -4.17173 4.17173 0.36 0.000695055 0.000646514 0.0331131 0.0308269 -1 -1 -1 -1 46 2562 33 6.99608e+06 279598 828058. 2865.25 1.99 0.189042 0.16453 28066 200906 -1 1783 21 1525 2326 154442 36408 3.79266 3.79266 -121.653 -3.79266 0 0 1.01997e+06 3529.29 0.04 0.07 0.16 -1 -1 0.04 0.0283844 0.0247975 86 50 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_029.v common 3.94 vpr 63.37 MiB -1 -1 0.23 18112 1 0.03 -1 -1 30208 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64892 32 32 284 241 1 168 78 17 17 289 -1 unnamed_device 24.1 MiB 0.70 870 11200 3386 5818 1996 63.4 MiB 0.10 0.00 3.16334 -110.479 -3.16334 3.16334 0.35 0.000610997 0.00056735 0.043289 0.0402908 -1 -1 -1 -1 34 2372 25 6.99608e+06 206020 618332. 2139.56 1.18 0.16887 0.147246 25762 151098 -1 1876 20 1333 1908 143533 32529 3.00782 3.00782 -119.005 -3.00782 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0242376 0.0211286 68 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_030.v common 3.73 vpr 63.51 MiB -1 -1 0.23 18100 1 0.03 -1 -1 30148 -1 -1 16 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 30 32 262 227 1 160 78 17 17 289 -1 unnamed_device 23.9 MiB 0.25 863 7216 1781 5114 321 63.5 MiB 0.07 0.00 3.77123 -111.817 -3.77123 3.77123 0.33 0.000564297 0.000525618 0.0265931 0.0247595 -1 -1 -1 -1 34 2210 47 6.99608e+06 235451 618332. 2139.56 1.44 0.1607 0.138405 25762 151098 -1 1918 20 1240 1920 164311 36185 3.63166 3.63166 -117.226 -3.63166 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0228113 0.0198785 65 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_031.v common 4.12 vpr 63.31 MiB -1 -1 0.24 18092 1 0.03 -1 -1 30088 -1 -1 20 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64832 28 32 260 223 1 152 80 17 17 289 -1 unnamed_device 23.7 MiB 0.28 611 12808 5071 5723 2014 63.3 MiB 0.10 0.00 3.4808 -106.362 -3.4808 3.4808 0.33 0.00055397 0.000515379 0.0431477 0.0400832 -1 -1 -1 -1 42 2077 35 6.99608e+06 294314 744469. 2576.02 1.76 0.166583 0.14464 27202 183097 -1 1523 23 1079 1820 147840 36523 3.50036 3.50036 -112.715 -3.50036 0 0 949917. 3286.91 0.04 0.07 0.17 -1 -1 0.04 0.025129 0.0218287 71 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_032.v common 3.51 vpr 63.40 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30284 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 253 210 1 149 77 17 17 289 -1 unnamed_device 23.9 MiB 0.21 869 10835 2990 6954 891 63.4 MiB 0.09 0.00 3.30043 -111.689 -3.30043 3.30043 0.33 0.000571124 0.000531379 0.0397191 0.036997 -1 -1 -1 -1 38 1933 22 6.99608e+06 191304 678818. 2348.85 1.28 0.154408 0.134664 26626 170182 -1 1681 20 1206 1902 143421 30990 3.03062 3.03062 -114.764 -3.03062 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0227464 0.0198249 59 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_033.v common 3.57 vpr 63.41 MiB -1 -1 0.14 18096 1 0.03 -1 -1 30152 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64932 31 32 271 231 1 164 78 17 17 289 -1 unnamed_device 23.8 MiB 0.32 848 11200 4155 5330 1715 63.4 MiB 0.10 0.00 3.30638 -108.083 -3.30638 3.30638 0.33 0.000594049 0.000553686 0.041933 0.0390598 -1 -1 -1 -1 36 2468 47 6.99608e+06 220735 648988. 2245.63 1.38 0.18323 0.159726 26050 158493 -1 1921 22 1298 1864 154372 34321 3.07012 3.07012 -110.48 -3.07012 0 0 828058. 2865.25 0.06 0.08 0.11 -1 -1 0.06 0.0273368 0.02388 65 30 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_034.v common 3.43 vpr 63.68 MiB -1 -1 0.24 18268 1 0.03 -1 -1 30436 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65208 29 32 291 250 1 177 80 17 17 289 -1 unnamed_device 24.1 MiB 0.41 894 13840 5313 6055 2472 63.7 MiB 0.11 0.00 2.84515 -98.5413 -2.84515 2.84515 0.33 0.000596794 0.000555651 0.0503236 0.0468031 -1 -1 -1 -1 32 2473 34 6.99608e+06 279598 586450. 2029.24 1.01 0.134807 0.118765 25474 144626 -1 2001 19 1322 1717 133560 29772 2.71322 2.71322 -107.002 -2.71322 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0306834 0.0265408 77 54 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_035.v common 4.30 vpr 64.22 MiB -1 -1 0.13 18472 1 0.03 -1 -1 30424 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65764 32 32 367 282 1 214 86 17 17 289 -1 unnamed_device 24.6 MiB 0.33 1071 15773 6281 8017 1475 64.2 MiB 0.15 0.00 4.08568 -124.656 -4.08568 4.08568 0.33 0.000745003 0.000692275 0.0644112 0.0598632 -1 -1 -1 -1 40 2932 31 6.99608e+06 323745 706193. 2443.58 1.79 0.223533 0.196102 26914 176310 -1 2492 23 1688 2754 246406 62644 4.27126 4.27126 -132.221 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/home/elgamma8/research/release/vtr-verilog-to-routing 65556 31 32 370 297 1 227 86 17 17 289 -1 unnamed_device 24.4 MiB 0.43 1217 14072 4085 8314 1673 64.0 MiB 0.07 0.00 3.60415 -128.157 -3.60415 3.60415 0.25 0.000323073 0.000297377 0.0260474 0.0240278 -1 -1 -1 -1 40 2752 44 6.99608e+06 338461 706193. 2443.58 1.49 0.192261 0.16592 26914 176310 -1 2485 21 1636 2359 186290 40291 3.67861 3.67861 -135.017 -3.67861 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0300731 0.0262642 99 61 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_039.v common 4.59 vpr 63.48 MiB -1 -1 0.28 18352 1 0.03 -1 -1 30284 -1 -1 22 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65008 31 32 377 302 1 235 85 17 17 289 -1 unnamed_device 24.4 MiB 0.41 1068 13477 4250 6738 2489 63.5 MiB 0.13 0.00 5.0573 -155.975 -5.0573 5.0573 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/home/elgamma8/research/release/vtr-verilog-to-routing 65492 32 32 353 287 1 209 82 17 17 289 -1 unnamed_device 24.4 MiB 0.46 1220 8092 1924 5321 847 64.0 MiB 0.09 0.00 3.85238 -122.663 -3.85238 3.85238 0.34 0.000716879 0.000666652 0.0349023 0.0324524 -1 -1 -1 -1 36 2897 23 6.99608e+06 264882 648988. 2245.63 1.53 0.182246 0.158709 26050 158493 -1 2508 21 1547 2144 170292 36759 3.35806 3.35806 -125.954 -3.35806 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0295558 0.0258317 90 55 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_049.v common 4.34 vpr 63.87 MiB -1 -1 0.25 18368 1 0.03 -1 -1 30260 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65400 32 32 361 291 1 214 86 17 17 289 -1 unnamed_device 24.3 MiB 0.51 1060 15017 4116 9319 1582 63.9 MiB 0.15 0.00 3.54419 -122.946 -3.54419 3.54419 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/home/elgamma8/research/release/vtr-verilog-to-routing 65140 31 32 373 299 1 223 85 17 17 289 -1 unnamed_device 24.5 MiB 0.43 1149 13663 5356 6563 1744 63.6 MiB 0.14 0.00 4.32027 -135.237 -4.32027 4.32027 0.36 0.000721821 0.000670744 0.056146 0.0521455 -1 -1 -1 -1 40 3112 25 6.99608e+06 323745 706193. 2443.58 1.16 0.145809 0.129022 26914 176310 -1 2617 22 2047 3207 244307 54446 3.98626 3.98626 -135.777 -3.98626 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0310617 0.0270555 100 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_054.v common 4.66 vpr 63.48 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30420 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65008 32 32 387 315 1 239 84 17 17 289 -1 unnamed_device 24.4 MiB 0.53 1208 10332 3432 4948 1952 63.5 MiB 0.11 0.00 4.04752 -134.676 -4.04752 4.04752 0.33 0.000750424 0.000697188 0.0448985 0.0417269 -1 -1 -1 -1 40 3452 41 6.99608e+06 294314 706193. 2443.58 1.78 0.214316 0.186475 26914 176310 -1 2865 20 2129 3202 274718 60596 4.10366 4.10366 -143.201 -4.10366 0 0 926341. 3205.33 0.04 0.12 0.18 -1 -1 0.04 0.038728 0.0339315 104 77 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_055.v common 3.16 vpr 63.21 MiB -1 -1 0.17 18024 1 0.03 -1 -1 30400 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64724 32 32 251 219 1 151 76 17 17 289 -1 unnamed_device 23.7 MiB 0.22 902 5996 1423 4213 360 63.2 MiB 0.07 0.00 3.24518 -106.32 -3.24518 3.24518 0.34 0.00056176 0.00052322 0.0230302 0.0214129 -1 -1 -1 -1 38 2061 22 6.99608e+06 176588 678818. 2348.85 1.09 0.135173 0.116914 26626 170182 -1 1739 19 995 1488 114516 24820 2.76922 2.76922 -103.921 -2.76922 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/home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 353 285 1 210 82 17 17 289 -1 unnamed_device 24.3 MiB 0.53 1034 11652 4187 4869 2596 63.3 MiB 0.12 0.00 4.57817 -141.46 -4.57817 4.57817 0.34 0.000705394 0.000654779 0.0487977 0.0453192 -1 -1 -1 -1 40 2926 29 6.99608e+06 264882 706193. 2443.58 1.94 0.20213 0.1763 26914 176310 -1 2361 20 1727 2500 217768 50608 4.35045 4.35045 -146.549 -4.35045 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0291737 0.0255574 91 51 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_069.v common 4.39 vpr 63.36 MiB -1 -1 0.23 18088 1 0.03 -1 -1 30020 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 32 32 276 237 1 160 78 17 17 289 -1 unnamed_device 24.0 MiB 0.43 717 10536 3258 5329 1949 63.4 MiB 0.09 0.00 3.47185 -106.975 -3.47185 3.47185 0.34 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/home/elgamma8/research/release/vtr-verilog-to-routing 64868 30 32 317 269 1 200 81 17 17 289 -1 unnamed_device 24.1 MiB 0.37 1051 7256 1625 5219 412 63.3 MiB 0.08 0.00 4.19642 -135.689 -4.19642 4.19642 0.33 0.000641856 0.000596751 0.0288339 0.0268375 -1 -1 -1 -1 36 2537 33 6.99608e+06 279598 648988. 2245.63 1.35 0.166224 0.143652 26050 158493 -1 2196 23 1975 2671 215318 47546 3.80181 3.80181 -135.851 -3.80181 0 0 828058. 2865.25 0.03 0.05 0.09 -1 -1 0.03 0.0159451 0.0140711 84 63 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 5.49 vpr 63.22 MiB -1 -1 0.23 18368 1 0.03 -1 -1 30212 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64740 32 32 335 282 1 216 82 17 17 289 -1 unnamed_device 24.2 MiB 0.39 930 12542 4675 5838 2029 63.2 MiB 0.12 0.00 3.0313 -115.382 -3.0313 3.0313 0.33 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30084 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 31 32 340 275 1 195 82 17 17 289 -1 unnamed_device 24.4 MiB 0.61 919 7736 2635 4162 939 63.9 MiB 0.08 0.00 5.0765 -140.835 -5.0765 5.0765 0.34 0.000683595 0.000635788 0.0323016 0.0300513 -1 -1 -1 -1 40 2827 34 6.99608e+06 279598 706193. 2443.58 2.01 0.183624 0.159375 26914 176310 -1 1996 18 1403 2053 154708 36864 4.34151 4.34151 -139.438 -4.34151 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0256852 0.022549 87 47 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_083.v common 4.34 vpr 64.08 MiB -1 -1 0.26 18548 1 0.03 -1 -1 30088 -1 -1 24 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65616 30 32 377 310 1 234 86 17 17 289 -1 unnamed_device 24.3 MiB 0.48 1149 6134 1189 4745 200 64.1 MiB 0.08 0.00 4.12466 -127.491 -4.12466 4.12466 0.34 0.000726629 0.000675798 0.0261685 0.0243289 -1 -1 -1 -1 38 3100 45 6.99608e+06 353176 678818. 2348.85 1.79 0.202351 0.174984 26626 170182 -1 2499 22 2217 3173 237661 53581 3.66761 3.66761 -131.006 -3.66761 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0311754 0.0271766 106 83 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_084.v common 4.50 vpr 63.91 MiB -1 -1 0.26 18392 1 0.03 -1 -1 30268 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65440 32 32 365 294 1 223 83 17 17 289 -1 unnamed_device 24.3 MiB 0.51 1094 12143 4447 5317 2379 63.9 MiB 0.13 0.00 4.71643 -147.438 -4.71643 4.71643 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21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65648 32 32 373 302 1 234 85 17 17 289 -1 unnamed_device 24.4 MiB 0.27 1243 16081 5953 7939 2189 64.1 MiB 0.16 0.00 4.8168 -157 -4.8168 4.8168 0.26 0.000731852 0.000679799 0.0658794 0.0611482 -1 -1 -1 -1 40 2915 24 6.99608e+06 309029 706193. 2443.58 1.51 0.221118 0.194285 26914 176310 -1 2455 21 1930 2730 203339 43779 5.01301 5.01301 -164.294 -5.01301 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.030157 0.026347 99 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_088.v common 5.66 vpr 64.08 MiB -1 -1 0.24 18396 1 0.03 -1 -1 30260 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65616 32 32 397 314 1 249 85 17 17 289 -1 unnamed_device 24.6 MiB 0.46 1158 15523 5731 7092 2700 64.1 MiB 0.15 0.00 4.69632 -158.476 -4.69632 4.69632 0.36 0.000762962 0.000708836 0.0665301 0.0618197 -1 -1 -1 -1 38 3758 42 6.99608e+06 309029 678818. 2348.85 3.07 0.255062 0.223742 26626 170182 -1 2698 21 2446 3392 270440 61960 4.80151 4.80151 -168.488 -4.80151 0 0 902133. 3121.57 0.03 0.06 0.10 -1 -1 0.03 0.0180729 0.0160962 105 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_089.v common 3.97 vpr 63.32 MiB -1 -1 0.23 18196 1 0.04 -1 -1 30352 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64836 32 32 269 231 1 163 78 17 17 289 -1 unnamed_device 23.7 MiB 0.32 733 12528 5239 6931 358 63.3 MiB 0.11 0.00 3.76077 -112.543 -3.76077 3.76077 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-1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65652 32 32 356 289 1 217 82 17 17 289 -1 unnamed_device 24.4 MiB 0.45 1087 8448 3166 4532 750 64.1 MiB 0.09 0.00 4.61807 -140.276 -4.61807 4.61807 0.33 0.000707102 0.000656576 0.0369544 0.034304 -1 -1 -1 -1 34 3563 30 6.99608e+06 264882 618332. 2139.56 1.99 0.187407 0.162638 25762 151098 -1 2617 25 2032 2765 272549 80736 4.66331 4.66331 -154.076 -4.66331 0 0 787024. 2723.27 0.03 0.12 0.12 -1 -1 0.03 0.0348237 0.0303706 91 56 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_093.v common 4.28 vpr 63.95 MiB -1 -1 0.25 18204 1 0.03 -1 -1 30132 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65488 32 32 349 260 1 195 93 17 17 289 -1 unnamed_device 24.4 MiB 0.20 1086 13533 4315 6748 2470 64.0 MiB 0.13 0.00 4.52621 -140.196 -4.52621 4.52621 0.33 0.000723358 0.00066428 0.0494366 0.0457611 -1 -1 -1 -1 38 2778 46 6.99608e+06 426755 678818. 2348.85 1.90 0.22108 0.192512 26626 170182 -1 2295 21 1739 3136 215099 47757 4.5307 4.5307 -144.202 -4.5307 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0300168 0.0261575 90 3 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_094.v common 4.68 vpr 63.35 MiB -1 -1 0.26 18260 1 0.03 -1 -1 30392 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 30 32 316 264 1 192 84 17 17 289 -1 unnamed_device 24.1 MiB 0.46 927 14175 4952 6503 2720 63.3 MiB 0.12 0.00 3.59117 -104.78 -3.59117 3.59117 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65552 31 32 365 296 1 229 84 17 17 289 -1 unnamed_device 24.4 MiB 0.41 1271 10515 2847 5946 1722 64.0 MiB 0.11 0.00 5.41693 -155.818 -5.41693 5.41693 0.34 0.000714768 0.000664242 0.0440555 0.0409587 -1 -1 -1 -1 40 2971 24 6.99608e+06 309029 706193. 2443.58 1.68 0.194532 0.169876 26914 176310 -1 2506 19 1927 2738 217010 45892 4.58734 4.58734 -155.424 -4.58734 0 0 926341. 3205.33 0.03 0.05 0.10 -1 -1 0.03 0.0158808 0.0141898 96 64 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_098.v common 3.88 vpr 63.83 MiB -1 -1 0.25 18352 1 0.03 -1 -1 30360 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65364 32 32 331 280 1 215 82 17 17 289 -1 unnamed_device 24.3 MiB 0.41 1019 12898 5003 5774 2121 63.8 MiB 0.12 0.00 4.02148 -135.181 -4.02148 4.02148 0.34 0.000675106 0.000626565 0.0511943 0.0476231 -1 -1 -1 -1 40 2554 27 6.99608e+06 264882 706193. 2443.58 1.32 0.190559 0.166595 26914 176310 -1 2119 21 1505 2040 162418 36238 3.52995 3.52995 -133.179 -3.52995 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0276916 0.0241046 87 65 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_099.v common 3.90 vpr 64.20 MiB -1 -1 0.12 18384 1 0.03 -1 -1 30420 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65736 32 32 326 263 1 198 81 17 17 289 -1 unnamed_device 24.5 MiB 0.35 947 12506 5206 6883 417 64.2 MiB 0.12 0.00 4.17438 -127.536 -4.17438 4.17438 0.34 0.000670822 0.000624314 0.0505488 0.0470101 -1 -1 -1 -1 40 2648 27 6.99608e+06 250167 706193. 2443.58 1.61 0.192834 0.168737 26914 176310 -1 2105 21 1427 1931 160580 36723 3.62241 3.62241 -127.407 -3.62241 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0276199 0.0241137 80 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_100.v common 4.13 vpr 63.98 MiB -1 -1 0.26 18396 1 0.03 -1 -1 30400 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65516 31 32 373 294 1 217 84 17 17 289 -1 unnamed_device 24.3 MiB 0.41 991 13077 4725 6680 1672 64.0 MiB 0.13 0.00 4.19793 -122.509 -4.19793 4.19793 0.34 0.000731044 0.000678936 0.0555421 0.0516292 -1 -1 -1 -1 40 2836 26 6.99608e+06 309029 706193. 2443.58 1.62 0.214199 0.187745 26914 176310 -1 2141 23 1964 2996 200616 48065 3.88241 3.88241 -125.837 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-1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64928 32 32 350 275 1 209 82 17 17 289 -1 unnamed_device 24.3 MiB 0.40 979 11296 4199 5586 1511 63.4 MiB 0.11 0.00 4.18128 -137.803 -4.18128 4.18128 0.35 0.000700566 0.000651095 0.0474618 0.044136 -1 -1 -1 -1 40 3397 41 6.99608e+06 264882 706193. 2443.58 10.45 0.385824 0.332557 26914 176310 -1 2446 25 2427 3705 324428 72341 4.38436 4.38436 -149.497 -4.38436 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0341054 0.0297049 87 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_103.v common 10.20 vpr 64.19 MiB -1 -1 0.24 18476 1 0.03 -1 -1 30092 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 386 307 1 240 85 17 17 289 -1 unnamed_device 24.5 MiB 0.41 1172 14779 4944 7940 1895 64.2 MiB 0.14 0.00 3.49383 -123.038 -3.49383 3.49383 0.35 0.000744675 0.000690682 0.0623874 0.0579082 -1 -1 -1 -1 38 3062 42 6.99608e+06 309029 678818. 2348.85 7.53 0.401185 0.347255 26626 170182 -1 2503 21 2030 2756 207605 45774 3.22392 3.22392 -130.363 -3.22392 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0313101 0.0274444 101 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.37 vpr 63.54 MiB -1 -1 0.22 18176 1 0.03 -1 -1 30312 -1 -1 17 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 29 32 269 229 1 166 78 17 17 289 -1 unnamed_device 23.9 MiB 0.27 653 11698 4829 5917 952 63.5 MiB 0.10 0.00 3.87612 -110.458 -3.87612 3.87612 0.33 0.000576824 0.00053597 0.0425092 0.0395708 -1 -1 -1 -1 36 1983 34 6.99608e+06 250167 648988. 2245.63 1.06 0.166516 0.144952 26050 158493 -1 1462 21 1445 1913 139306 32789 3.36942 3.36942 -114.909 -3.36942 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0246534 0.0215084 68 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 3.78 vpr 63.19 MiB -1 -1 0.23 18272 1 0.03 -1 -1 30280 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 310 266 1 184 80 17 17 289 -1 unnamed_device 24.0 MiB 0.39 769 12292 3548 6982 1762 63.2 MiB 0.11 0.00 3.56989 -117.422 -3.56989 3.56989 0.34 0.000639731 0.000595039 0.0476767 0.0443352 -1 -1 -1 -1 48 1921 23 6.99608e+06 235451 865456. 2994.66 1.32 0.176243 0.153877 28354 207349 -1 1369 21 1242 1698 118545 29084 3.32086 3.32086 -112.996 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30324 -1 -1 16 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 29 32 262 224 1 162 77 17 17 289 -1 unnamed_device 23.8 MiB 0.36 695 10346 4286 5606 454 63.4 MiB 0.09 0.00 3.75967 -107.452 -3.75967 3.75967 0.33 0.000564484 0.000525149 0.0379166 0.0352817 -1 -1 -1 -1 42 2064 29 6.99608e+06 235451 744469. 2576.02 1.18 0.155295 0.134907 27202 183097 -1 1555 21 1113 1458 123164 29262 3.29971 3.29971 -107.37 -3.29971 0 0 949917. 3286.91 0.04 0.06 0.15 -1 -1 0.04 0.0233802 0.0203302 67 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 3.91 vpr 63.50 MiB -1 -1 0.23 18172 1 0.03 -1 -1 30120 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65024 32 32 278 238 1 178 79 17 17 289 -1 unnamed_device 24.4 MiB 0.31 796 9881 3787 3524 2570 63.5 MiB 0.08 0.00 3.83776 -116.677 -3.83776 3.83776 0.34 0.000602466 0.000560405 0.0375036 0.0348051 -1 -1 -1 -1 40 2236 47 6.99608e+06 220735 706193. 2443.58 1.65 0.18307 0.158721 26914 176310 -1 1723 22 1490 2039 151424 35617 3.27792 3.27792 -122.849 -3.27792 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0262726 0.0228775 70 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 3.86 vpr 64.20 MiB -1 -1 0.16 18264 1 0.03 -1 -1 30352 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65736 31 32 373 300 1 230 86 17 17 289 -1 unnamed_device 24.5 MiB 0.40 1185 13505 4820 6538 2147 64.2 MiB 0.13 0.00 4.07096 -136.622 -4.07096 4.07096 0.34 0.000729681 0.000677527 0.0547725 0.0508854 -1 -1 -1 -1 42 2958 22 6.99608e+06 338461 744469. 2576.02 1.31 0.208461 0.182792 27202 183097 -1 2422 18 1969 2848 217495 47098 3.51536 3.51536 -133.165 -3.51536 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0276423 0.0242731 100 64 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_110.v common 4.04 vpr 63.46 MiB -1 -1 0.24 18104 1 0.03 -1 -1 30292 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64988 31 32 265 230 1 170 78 17 17 289 -1 unnamed_device 23.8 MiB 0.36 907 8876 2820 4643 1413 63.5 MiB 0.08 0.00 3.24748 -103.016 -3.24748 3.24748 0.33 0.00057241 0.000532529 0.032623 0.0303397 -1 -1 -1 -1 36 2282 37 6.99608e+06 220735 648988. 2245.63 1.56 0.159617 0.138207 26050 158493 -1 1955 18 1210 1690 151023 32590 3.12312 3.12312 -115.765 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-1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65700 31 32 396 325 1 257 87 17 17 289 -1 unnamed_device 24.6 MiB 0.44 1349 14103 4011 7972 2120 64.2 MiB 0.14 0.00 4.40154 -151.265 -4.40154 4.40154 0.33 0.000751009 0.00069733 0.0583701 0.0541383 -1 -1 -1 -1 38 3173 30 6.99608e+06 353176 678818. 2348.85 1.58 0.224464 0.196682 26626 170182 -1 2642 24 2358 3345 246804 52357 4.09905 4.09905 -148.278 -4.09905 0 0 902133. 3121.57 0.03 0.10 0.14 -1 -1 0.03 0.034493 0.0300425 111 91 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_113.v common 3.68 vpr 63.35 MiB -1 -1 0.16 18120 1 0.03 -1 -1 30264 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 303 262 1 189 80 17 17 289 -1 unnamed_device 24.2 MiB 0.39 882 11604 4388 5877 1339 63.3 MiB 0.11 0.00 3.12442 -108.534 -3.12442 3.12442 0.33 0.000626026 0.000581342 0.0442632 0.0411357 -1 -1 -1 -1 40 2100 25 6.99608e+06 235451 706193. 2443.58 1.25 0.169644 0.147609 26914 176310 -1 1761 21 1458 2022 155648 35832 3.10012 3.10012 -112.487 -3.10012 0 0 926341. 3205.33 0.04 0.07 0.14 -1 -1 0.04 0.0262352 0.0228162 80 57 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_114.v common 3.73 vpr 63.70 MiB -1 -1 0.13 18116 1 0.02 -1 -1 30224 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 32 32 290 244 1 174 79 17 17 289 -1 unnamed_device 24.1 MiB 0.38 908 12585 5135 6794 656 63.7 MiB 0.11 0.00 3.42763 -113.296 -3.42763 3.42763 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/home/elgamma8/research/release/vtr-verilog-to-routing 64692 31 32 229 197 1 138 78 17 17 289 -1 unnamed_device 23.7 MiB 0.48 649 8378 3363 4684 331 63.2 MiB 0.07 0.00 3.20338 -90.6125 -3.20338 3.20338 0.33 0.000536852 0.000500057 0.0285834 0.0266282 -1 -1 -1 -1 38 1740 26 6.99608e+06 220735 678818. 2348.85 1.36 0.137751 0.119285 26626 170182 -1 1408 23 1078 1745 129004 28747 2.71597 2.71597 -95.6168 -2.71597 0 0 902133. 3121.57 0.03 0.06 0.14 -1 -1 0.03 0.0241496 0.0209859 55 4 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_119.v common 4.78 vpr 64.14 MiB -1 -1 0.26 18268 1 0.03 -1 -1 30284 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65676 32 32 412 334 1 258 87 17 17 289 -1 unnamed_device 24.6 MiB 0.43 1319 11991 3957 5960 2074 64.1 MiB 0.12 0.00 4.93268 -164.708 -4.93268 4.93268 0.33 0.000771802 0.0007156 0.0512591 0.0475308 -1 -1 -1 -1 36 4054 47 6.99608e+06 338461 648988. 2245.63 2.21 0.243207 0.211496 26050 158493 -1 2858 22 2200 2781 251702 57095 5.2633 5.2633 -181.627 -5.2633 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0334506 0.0292332 114 90 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_120.v common 4.24 vpr 64.18 MiB -1 -1 0.15 18404 1 0.03 -1 -1 30156 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65716 32 32 376 318 1 253 86 17 17 289 -1 unnamed_device 24.5 MiB 0.45 1337 12182 2801 8441 940 64.2 MiB 0.12 0.00 4.37262 -158.739 -4.37262 4.37262 0.37 0.000711764 0.00066043 0.0487485 0.0452791 -1 -1 -1 -1 46 2963 26 6.99608e+06 323745 828058. 2865.25 1.71 0.203017 0.17733 28066 200906 -1 2457 21 1963 2529 189545 39868 4.11305 4.11305 -157.703 -4.11305 0 0 1.01997e+06 3529.29 0.04 0.08 0.16 -1 -1 0.04 0.0298197 0.0260554 105 96 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_121.v common 4.40 vpr 63.93 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30296 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65468 32 32 360 293 1 219 83 17 17 289 -1 unnamed_device 24.3 MiB 0.39 1211 12683 3755 7514 1414 63.9 MiB 0.12 0.00 3.36853 -122.175 -3.36853 3.36853 0.34 0.000707294 0.000657276 0.0529326 0.049187 -1 -1 -1 -1 38 2800 43 6.99608e+06 279598 678818. 2348.85 1.88 0.220766 0.19246 26626 170182 -1 2343 24 1786 2393 200580 41794 3.23592 3.23592 -123.11 -3.23592 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0326012 0.0283387 94 60 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_122.v common 12.44 vpr 64.27 MiB -1 -1 0.24 18692 1 0.03 -1 -1 30400 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65812 32 32 396 299 1 231 85 17 17 289 -1 unnamed_device 24.5 MiB 0.32 1108 13105 3671 7584 1850 64.3 MiB 0.14 0.00 5.6322 -158.993 -5.6322 5.6322 0.33 0.000777235 0.000722016 0.0575258 0.0534752 -1 -1 -1 -1 44 3147 38 6.99608e+06 309029 787024. 2723.27 9.94 0.396837 0.342694 27778 195446 -1 2287 34 2017 3107 304138 115013 4.85505 4.85505 -154.503 -4.85505 0 0 997811. 3452.63 0.04 0.15 0.16 -1 -1 0.04 0.0485984 0.0422188 99 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_123.v common 3.20 vpr 63.57 MiB -1 -1 0.17 18072 1 0.03 -1 -1 30108 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65100 30 32 224 207 1 134 75 17 17 289 -1 unnamed_device 24.1 MiB 0.28 577 10029 4242 5446 341 63.6 MiB 0.08 0.00 2.33546 -85.6612 -2.33546 2.33546 0.33 0.000504067 0.000469255 0.0336791 0.0313571 -1 -1 -1 -1 36 1749 31 6.99608e+06 191304 648988. 2245.63 1.08 0.138424 0.120065 26050 158493 -1 1357 21 893 1110 100119 24717 2.39608 2.39608 -90.4929 -2.39608 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0205929 0.0178716 52 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_124.v common 5.20 vpr 63.46 MiB -1 -1 0.12 18016 1 0.03 -1 -1 30352 -1 -1 16 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 30 32 286 239 1 159 78 17 17 289 -1 unnamed_device 24.1 MiB 1.18 829 10868 4869 5663 336 63.5 MiB 0.09 0.00 3.98607 -129.511 -3.98607 3.98607 0.33 0.000597854 0.000554481 0.0409971 0.0380891 -1 -1 -1 -1 36 2107 25 6.99608e+06 235451 648988. 2245.63 2.17 0.233413 0.20137 26050 158493 -1 1748 17 1098 1623 130284 30423 3.71161 3.71161 -136.48 -3.71161 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0214257 0.018737 71 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_125.v common 4.67 vpr 63.82 MiB -1 -1 0.23 18140 1 0.03 -1 -1 30060 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65348 32 32 296 247 1 182 85 17 17 289 -1 unnamed_device 24.2 MiB 0.32 859 13477 5604 7598 275 63.8 MiB 0.12 0.00 3.71535 -130.45 -3.71535 3.71535 0.36 0.000628988 0.00058134 0.0476797 0.0443348 -1 -1 -1 -1 38 2908 46 6.99608e+06 309029 678818. 2348.85 2.29 0.197424 0.171974 26626 170182 -1 2101 23 1401 2302 222408 54792 4.32052 4.32052 -140.632 -4.32052 0 0 902133. 3121.57 0.04 0.09 0.14 -1 -1 0.04 0.0284077 0.0247235 77 34 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_126.v common 3.44 vpr 63.14 MiB -1 -1 0.21 18088 1 0.03 -1 -1 30336 -1 -1 19 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64660 25 32 216 194 1 134 76 17 17 289 -1 unnamed_device 23.8 MiB 0.25 507 10956 4030 4533 2393 63.1 MiB 0.08 0.00 3.37063 -78.72 -3.37063 3.37063 0.33 0.000480281 0.000446164 0.0343935 0.0319653 -1 -1 -1 -1 38 1738 27 6.99608e+06 279598 678818. 2348.85 1.26 0.132985 0.115295 26626 170182 -1 1108 17 744 1072 69349 18454 3.14737 3.14737 -85.6299 -3.14737 0 0 902133. 3121.57 0.03 0.04 0.14 -1 -1 0.03 0.0171683 0.0150118 56 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_127.v common 6.40 vpr 63.52 MiB -1 -1 0.25 18276 1 0.03 -1 -1 30348 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65044 32 32 376 307 1 230 83 17 17 289 -1 unnamed_device 24.4 MiB 0.51 1070 13583 5650 7491 442 63.5 MiB 0.13 0.00 4.04452 -130.09 -4.04452 4.04452 0.34 0.000728734 0.000675996 0.0578889 0.0536675 -1 -1 -1 -1 40 3557 32 6.99608e+06 279598 706193. 2443.58 3.62 0.22235 0.194456 26914 176310 -1 2744 21 2050 3040 252988 64010 4.43451 4.43451 -145.309 -4.43451 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0305214 0.0266633 100 72 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_128.v common 4.47 vpr 63.53 MiB -1 -1 0.26 18432 1 0.03 -1 -1 30404 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 31 32 409 331 1 257 87 17 17 289 -1 unnamed_device 24.6 MiB 0.47 1269 16023 5206 8626 2191 63.5 MiB 0.16 0.00 4.27167 -145.144 -4.27167 4.27167 0.34 0.000768802 0.000713617 0.0673126 0.0624982 -1 -1 -1 -1 38 3325 48 6.99608e+06 353176 678818. 2348.85 1.74 0.259733 0.227383 26626 170182 -1 2713 23 2420 3261 279104 64299 3.9869 3.9869 -150.259 -3.9869 0 0 902133. 3121.57 0.04 0.11 0.14 -1 -1 0.04 0.035037 0.0305796 115 90 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_001.v common 5.45 vpr 63.17 MiB -1 -1 0.37 18628 14 0.27 -1 -1 32696 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 32 32 277 309 1 198 86 17 17 289 -1 unnamed_device 23.9 MiB 1.02 1216 8402 2148 5464 790 63.2 MiB 0.10 0.00 8.60211 -177.555 -8.60211 8.60211 0.33 0.000906651 0.000841051 0.0440023 0.04089 -1 -1 -1 -1 36 3343 23 6.79088e+06 296384 648988. 2245.63 1.66 0.234664 0.204625 25390 158009 -1 2918 20 1215 3530 210135 48583 7.25706 7.25706 -164.252 -7.25706 0 0 828058. 2865.25 0.03 0.09 0.13 -1 -1 0.03 0.0372184 0.0326547 134 183 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_002.v common 4.27 vpr 63.08 MiB -1 -1 0.39 18612 14 0.28 -1 -1 32752 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64592 30 32 272 304 1 201 85 17 17 289 -1 unnamed_device 23.8 MiB 0.54 1069 6595 1508 3894 1193 63.1 MiB 0.08 0.00 7.62679 -156.019 -7.62679 7.62679 0.33 0.000897571 0.000832492 0.0356274 0.0329963 -1 -1 -1 -1 30 3252 22 6.79088e+06 309856 556674. 1926.21 1.19 0.153656 0.134616 24526 138013 -1 2437 15 1240 3174 155047 38736 7.03519 7.03519 -154.218 -7.03519 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 29 32 275 307 1 198 84 17 17 289 -1 unnamed_device 23.8 MiB 0.58 1159 7221 1730 4679 812 63.6 MiB 0.08 0.00 7.12458 -141.442 -7.12458 7.12458 0.33 0.000907899 0.000842156 0.0393057 0.0364311 -1 -1 -1 -1 36 3012 26 6.79088e+06 309856 648988. 2245.63 1.25 0.235956 0.204904 25390 158009 -1 2527 17 1156 3212 170442 40925 6.40858 6.40858 -139.574 -6.40858 0 0 828058. 2865.25 0.03 0.08 0.14 -1 -1 0.03 0.034688 0.0306631 138 190 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_005.v common 4.73 vpr 63.32 MiB -1 -1 0.37 18332 13 0.27 -1 -1 32836 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64224 31 32 235 267 1 193 83 17 17 289 -1 unnamed_device 23.5 MiB 0.49 1267 9443 2350 5394 1699 62.7 MiB 0.09 0.00 7.00394 -146.716 -7.00394 7.00394 0.33 0.00075893 0.000701998 0.0425388 0.039409 -1 -1 -1 -1 38 3104 44 6.79088e+06 269440 678818. 2348.85 1.40 0.217188 0.188472 25966 169698 -1 2511 13 1067 2786 145991 34263 6.13878 6.13878 -139.908 -6.13878 0 0 902133. 3121.57 0.03 0.06 0.13 -1 -1 0.03 0.0236132 0.0210078 109 144 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_010.v common 4.65 vpr 62.76 MiB -1 -1 0.34 18032 13 0.19 -1 -1 32656 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 32 32 250 282 1 179 81 17 17 289 -1 unnamed_device 23.8 MiB 0.50 1090 10931 3367 5780 1784 62.8 MiB 0.11 0.00 7.28577 -164.664 -7.28577 7.28577 0.34 0.000813571 0.000754847 0.0542084 0.0503226 -1 -1 -1 -1 28 3533 41 6.79088e+06 229024 531479. 1839.03 1.91 0.185087 0.16268 23950 126010 -1 2752 19 1252 3064 186322 44716 6.83133 6.83133 -163.201 -6.83133 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0192374 0.0173001 110 156 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_011.v common 3.96 vpr 63.13 MiB -1 -1 0.34 17980 12 0.18 -1 -1 32420 -1 -1 20 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 30 32 216 248 1 158 82 17 17 289 -1 unnamed_device 23.7 MiB 0.64 1013 7736 2109 4154 1473 63.1 MiB 0.07 0.00 7.00052 -148.469 -7.00052 7.00052 0.34 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65432 32 32 303 335 1 223 88 17 17 289 -1 unnamed_device 24.1 MiB 0.93 1381 7108 1510 4813 785 63.9 MiB 0.09 0.00 8.68737 -182.159 -8.68737 8.68737 0.33 0.000971373 0.000899383 0.0395476 0.0366407 -1 -1 -1 -1 32 4290 36 6.79088e+06 323328 586450. 2029.24 1.15 0.190555 0.16651 24814 144142 -1 3144 21 1610 4237 239711 58120 7.62947 7.62947 -174.383 -7.62947 0 0 744469. 2576.02 0.03 0.11 0.12 -1 -1 0.03 0.0443311 0.0389765 154 209 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_015.v common 3.50 vpr 63.13 MiB -1 -1 0.17 18192 11 0.17 -1 -1 32568 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64648 29 32 225 257 1 169 84 17 17 289 -1 unnamed_device 23.7 MiB 0.44 916 10515 3062 5421 2032 63.1 MiB 0.09 0.00 6.53813 -131.787 -6.53813 6.53813 0.34 0.000725706 0.000672408 0.0448337 0.0415415 -1 -1 -1 -1 32 2757 29 6.79088e+06 309856 586450. 2029.24 0.69 0.142599 0.125231 24814 144142 -1 2124 15 1029 2591 137318 34249 5.82544 5.82544 -128.803 -5.82544 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0251747 0.0222641 108 140 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_016.v common 5.08 vpr 63.88 MiB -1 -1 0.38 18624 12 0.27 -1 -1 32832 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65408 32 32 301 333 1 219 91 17 17 289 -1 unnamed_device 24.2 MiB 0.77 1438 8863 2011 6147 705 63.9 MiB 0.10 0.00 7.59173 -165.075 -7.59173 7.59173 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 30 32 175 207 1 132 76 17 17 289 -1 unnamed_device 23.3 MiB 0.29 730 7916 1923 5695 298 62.7 MiB 0.04 0.00 4.80476 -119.7 -4.80476 4.80476 0.26 0.000256369 0.000236382 0.0143765 0.0132661 -1 -1 -1 -1 30 2018 34 6.79088e+06 188608 556674. 1926.21 0.77 0.095688 0.0827056 24526 138013 -1 1498 16 687 1592 79762 20616 4.17477 4.17477 -114.477 -4.17477 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0198998 0.0174803 65 87 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_020.v common 4.36 vpr 63.16 MiB -1 -1 0.33 17996 13 0.18 -1 -1 32604 -1 -1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 238 270 1 178 83 17 17 289 -1 unnamed_device 23.8 MiB 0.65 1148 12143 3041 7670 1432 63.3 MiB 0.11 0.00 6.34459 -146.944 -6.34459 6.34459 0.33 0.000750706 0.000694298 0.0538223 0.0498043 -1 -1 -1 -1 38 2647 17 6.79088e+06 255968 678818. 2348.85 1.33 0.2063 0.18023 25966 169698 -1 2328 17 947 2403 123447 29193 5.48874 5.48874 -138.211 -5.48874 0 0 902133. 3121.57 0.04 0.07 0.11 -1 -1 0.04 0.0286228 0.0252657 107 144 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_030.v common 5.13 vpr 63.04 MiB -1 -1 0.31 18240 11 0.15 -1 -1 32708 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 30 32 213 245 1 165 83 17 17 289 -1 unnamed_device 23.7 MiB 0.61 974 10343 3278 5049 2016 63.0 MiB 0.09 0.00 6.09388 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/home/elgamma8/research/release/vtr-verilog-to-routing 64524 29 32 220 252 1 166 80 17 17 289 -1 unnamed_device 23.6 MiB 0.45 940 6788 1590 4069 1129 63.0 MiB 0.07 0.00 5.87088 -123.319 -5.87088 5.87088 0.33 0.000727256 0.000674214 0.0314234 0.0291543 -1 -1 -1 -1 32 2784 27 6.79088e+06 255968 586450. 2029.24 0.81 0.125126 0.109442 24814 144142 -1 2184 23 928 2818 218996 73994 5.15963 5.15963 -121.159 -5.15963 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0346152 0.0304083 103 135 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_035.v common 6.98 vpr 63.85 MiB -1 -1 0.40 19044 13 0.29 -1 -1 32872 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65384 32 32 315 347 1 230 88 17 17 289 -1 unnamed_device 24.1 MiB 0.96 1348 13153 3284 8043 1826 63.9 MiB 0.15 0.00 8.14776 -167.632 -8.14776 8.14776 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64600 31 32 307 339 1 222 88 17 17 289 -1 unnamed_device 24.1 MiB 1.21 1407 7498 1735 4811 952 63.1 MiB 0.09 0.00 7.34976 -154.275 -7.34976 7.34976 0.34 0.000981071 0.000910313 0.0420093 0.0389437 -1 -1 -1 -1 40 3418 20 6.79088e+06 336800 706193. 2443.58 1.73 0.246794 0.215022 26254 175826 -1 3093 18 1523 4851 283645 64150 6.47011 6.47011 -145.98 -6.47011 0 0 926341. 3205.33 0.04 0.10 0.14 -1 -1 0.04 0.0386713 0.0341337 147 216 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_039.v common 4.12 vpr 63.12 MiB -1 -1 0.29 18700 14 0.33 -1 -1 32668 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 293 325 1 209 86 17 17 289 -1 unnamed_device 24.1 MiB 0.66 1309 5189 1008 3816 365 63.1 MiB 0.07 0.00 8.47715 -171.11 -8.47715 8.47715 0.33 0.000951617 0.000883008 0.0299557 0.0278273 -1 -1 -1 -1 32 3922 37 6.79088e+06 309856 586450. 2029.24 1.02 0.169292 0.147146 24814 144142 -1 2985 16 1354 3764 205238 49818 7.35086 7.35086 -163.299 -7.35086 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.035856 0.0317914 145 202 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_040.v common 7.66 vpr 63.05 MiB -1 -1 0.41 18940 13 0.26 -1 -1 32728 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 31 32 276 308 1 213 90 17 17 289 -1 unnamed_device 23.9 MiB 0.91 1374 8733 1936 6161 636 63.0 MiB 0.10 0.00 8.23594 -169.125 -8.23594 8.23594 0.34 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65196 32 32 271 303 1 213 86 17 17 289 -1 unnamed_device 23.9 MiB 0.48 1392 6323 1417 4337 569 63.7 MiB 0.08 0.00 7.43607 -167.439 -7.43607 7.43607 0.34 0.000883475 0.000818429 0.0332858 0.0308115 -1 -1 -1 -1 32 3852 24 6.79088e+06 296384 586450. 2029.24 1.13 0.154314 0.134981 24814 144142 -1 3039 31 1428 4021 302952 101633 6.58083 6.58083 -166.434 -6.58083 0 0 744469. 2576.02 0.03 0.09 0.08 -1 -1 0.03 0.0285554 0.0252491 137 177 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_059.v common 3.59 vpr 62.98 MiB -1 -1 0.29 18232 11 0.21 -1 -1 32800 -1 -1 20 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 30 32 235 267 1 168 80 17 17 289 -1 unnamed_device 23.6 MiB 0.93 1017 9368 2381 5580 1407 63.2 MiB 0.09 0.00 7.37863 -147.299 -7.37863 7.37863 0.33 0.000762423 0.00070602 0.0447211 0.0414357 -1 -1 -1 -1 30 2602 19 6.79088e+06 242496 556674. 1926.21 0.82 0.135703 0.11964 24526 138013 -1 2239 15 965 2628 129907 31874 6.45553 6.45553 -140.988 -6.45553 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0261016 0.0231301 106 147 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_074.v common 5.26 vpr 63.01 MiB -1 -1 0.36 18368 12 0.25 -1 -1 32488 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65428 32 32 318 350 1 235 87 17 17 289 -1 unnamed_device 24.1 MiB 0.56 1568 4887 902 3684 301 63.9 MiB 0.07 0.00 9.02019 -190.009 -9.02019 9.02019 0.34 0.00104181 0.000961409 0.0318736 0.0295113 -1 -1 -1 -1 36 4105 46 6.79088e+06 309856 648988. 2245.63 2.61 0.292466 0.253271 25390 158009 -1 3306 18 1498 4099 235444 53438 7.68756 7.68756 -176.02 -7.68756 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0414283 0.0365895 161 224 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_118.v common 3.77 vpr 63.05 MiB -1 -1 0.29 17912 12 0.16 -1 -1 32496 -1 -1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64564 31 32 222 254 1 182 83 17 17 289 -1 unnamed_device 23.6 MiB 0.49 1069 9983 2406 6498 1079 63.1 MiB 0.09 0.00 6.74398 -150.531 -6.74398 6.74398 0.33 0.000713695 0.000661577 0.0425082 0.0394239 -1 -1 -1 -1 38 2477 16 6.79088e+06 269440 678818. 2348.85 1.06 0.169114 0.147666 25966 169698 -1 2099 19 1023 2452 121285 30063 5.80973 5.80973 -140.663 -5.80973 0 0 902133. 3121.57 0.03 0.07 0.14 -1 -1 0.03 0.0287622 0.0252832 105 131 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_119.v common 5.67 vpr 63.24 MiB -1 -1 0.41 18960 13 0.27 -1 -1 32740 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 32 32 282 314 1 205 88 17 17 289 -1 unnamed_device 24.2 MiB 0.68 1353 7498 1790 4732 976 63.2 MiB 0.09 0.00 7.75713 -161.394 -7.75713 7.75713 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 32 32 350 382 1 253 93 17 17 289 -1 unnamed_device 24.4 MiB 0.80 1534 15843 4073 9876 1894 64.2 MiB 0.20 0.00 9.26624 -195.349 -9.26624 9.26624 0.33 0.00114344 0.00105332 0.0911082 0.0837944 -1 -1 -1 -1 36 4424 47 6.79088e+06 390688 648988. 2245.63 2.27 0.375645 0.327516 25390 158009 -1 3688 20 2137 6480 362108 83352 8.22795 8.22795 -186.796 -8.22795 0 0 828058. 2865.25 0.03 0.13 0.13 -1 -1 0.03 0.050897 0.0448721 188 256 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_123.v common 3.06 vpr 62.77 MiB -1 -1 0.29 17780 10 0.10 -1 -1 32524 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64272 30 32 174 206 1 132 75 17 17 289 -1 unnamed_device 23.2 MiB 0.33 648 7817 1916 5610 291 62.8 MiB 0.07 0.00 5.06221 -116.743 -5.06221 5.06221 0.33 0.000563723 0.000524027 0.0299828 0.0278843 -1 -1 -1 -1 32 2039 40 6.79088e+06 175136 586450. 2029.24 0.68 0.114078 0.0994672 24814 144142 -1 1601 16 716 1708 100263 26208 4.63261 4.63261 -119.111 -4.63261 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0195277 0.0171444 66 86 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_124.v common 3.60 vpr 62.99 MiB -1 -1 0.33 18044 13 0.25 -1 -1 32752 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 30 32 228 260 1 177 80 17 17 289 -1 unnamed_device 23.5 MiB 0.41 977 10744 3187 5417 2140 63.0 MiB 0.10 0.00 7.96187 -158.87 -7.96187 7.96187 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 32 32 300 332 1 225 89 17 17 289 -1 unnamed_device 24.1 MiB 0.37 1417 10979 2888 6604 1487 63.8 MiB 0.12 0.00 7.28043 -165.449 -7.28043 7.28043 0.33 0.000948654 0.000879079 0.0577509 0.0533375 -1 -1 -1 -1 32 4329 46 6.79088e+06 336800 586450. 2029.24 1.37 0.214521 0.187812 24814 144142 -1 3568 20 1714 4669 291667 67052 6.45537 6.45537 -165.272 -6.45537 0 0 744469. 2576.02 0.03 0.11 0.12 -1 -1 0.03 0.0397058 0.0352465 149 206 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_128.v common 4.87 vpr 63.24 MiB -1 -1 0.42 18912 13 0.31 -1 -1 32660 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 31 32 290 322 1 212 86 17 17 289 -1 unnamed_device 24.2 MiB 0.69 1276 4622 899 3442 281 63.2 MiB 0.06 0.00 8.4013 -172.333 -8.4013 8.4013 0.34 0.000957164 0.000887561 0.0274008 0.0254206 -1 -1 -1 -1 34 3859 32 6.79088e+06 309856 618332. 2139.56 1.54 0.247346 0.214205 25102 150614 -1 3160 20 1508 4342 240659 56587 7.44571 7.44571 -165.463 -7.44571 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0400711 0.0351655 150 199 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_001.v common 4.66 vpr 63.26 MiB -1 -1 0.25 18400 1 0.03 -1 -1 30288 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 32 32 354 285 1 207 95 17 17 289 -1 unnamed_device 24.3 MiB 2.00 1147 13487 3979 8243 1265 63.3 MiB 0.14 0.00 5.50182 -164.026 -5.50182 5.50182 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65260 29 32 308 248 1 172 90 17 17 289 -1 unnamed_device 24.1 MiB 0.86 892 10140 2486 6760 894 63.7 MiB 0.11 0.00 4.60038 -123.753 -4.60038 4.60038 0.33 0.000633932 0.000589803 0.0345913 0.0320554 -1 -1 -1 -1 32 2149 25 6.87369e+06 405241 586450. 2029.24 0.58 0.111836 0.0978729 25474 144626 -1 1602 29 1438 2570 137658 37022 3.4118 3.4118 -110.106 -3.4118 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0330296 0.0285014 124 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_005.v common 4.32 vpr 63.72 MiB -1 -1 0.24 18380 1 0.04 -1 -1 30476 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65248 32 32 336 268 1 181 91 17 17 289 -1 unnamed_device 24.0 MiB 1.54 976 16411 4511 9390 2510 63.7 MiB 0.15 0.00 4.59502 -132.541 -4.59502 4.59502 0.32 0.000701689 0.000651586 0.0483871 0.0448305 -1 -1 -1 -1 32 2485 25 6.87369e+06 377294 586450. 2029.24 0.64 0.133884 0.117944 25474 144626 -1 1977 21 1412 2809 153940 39270 3.7944 3.7944 -130.207 -3.7944 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0280558 0.024416 132 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_006.v common 3.84 vpr 63.56 MiB -1 -1 0.26 18328 1 0.03 -1 -1 30288 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65088 32 32 366 295 1 189 96 17 17 289 -1 unnamed_device 24.6 MiB 1.24 1097 10170 2509 6996 665 63.6 MiB 0.11 0.00 3.40153 -118.348 -3.40153 3.40153 0.34 0.000718937 0.00066798 0.0357972 0.0332493 -1 -1 -1 -1 28 2662 22 6.87369e+06 447163 531479. 1839.03 0.56 0.122325 0.107375 24610 126494 -1 2380 23 1512 2419 162698 39915 3.07761 3.07761 -124.592 -3.07761 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0315109 0.0273292 138 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_007.v common 4.43 vpr 63.20 MiB -1 -1 0.23 18008 1 0.03 -1 -1 30656 -1 -1 20 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64716 27 32 259 221 1 141 79 17 17 289 -1 unnamed_device 23.6 MiB 1.99 786 12585 3639 7320 1626 63.2 MiB 0.11 0.00 3.84098 -106.539 -3.84098 3.84098 0.33 0.000553599 0.000515588 0.0428643 0.0399218 -1 -1 -1 -1 30 1555 20 6.87369e+06 279477 556674. 1926.21 0.52 0.107252 0.0947091 25186 138497 -1 1281 20 867 1509 82468 20053 2.68236 2.68236 -96.0091 -2.68236 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 317 271 1 175 83 17 17 289 -1 unnamed_device 24.0 MiB 1.95 910 8723 2060 6322 341 63.1 MiB 0.09 0.00 3.31917 -111.486 -3.31917 3.31917 0.34 0.00063441 0.000590038 0.0329474 0.0306471 -1 -1 -1 -1 32 2150 19 6.87369e+06 279477 586450. 2029.24 0.58 0.106092 0.093061 25474 144626 -1 1748 20 1043 1565 98545 24803 2.91151 2.91151 -112.578 -2.91151 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0244429 0.0212104 110 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_010.v common 6.12 vpr 63.35 MiB -1 -1 0.22 18120 1 0.03 -1 -1 30076 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 32 32 298 248 1 162 81 17 17 289 -1 unnamed_device 23.6 MiB 3.62 974 4631 910 3488 233 63.4 MiB 0.06 0.00 3.98344 -131.884 -3.98344 3.98344 0.33 0.000626678 0.000583326 0.0185195 0.0172494 -1 -1 -1 -1 30 2081 18 6.87369e+06 237555 556674. 1926.21 0.54 0.0883308 0.0768845 25186 138497 -1 1827 21 1179 2019 124096 30001 2.82686 2.82686 -118.966 -2.82686 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0253455 0.0219646 107 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_011.v common 5.19 vpr 63.25 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30308 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 30 32 303 262 1 148 80 17 17 289 -1 unnamed_device 23.6 MiB 2.64 812 9368 2251 6434 683 63.2 MiB 0.10 0.00 3.87398 -114.403 -3.87398 3.87398 0.33 0.000612514 0.000569112 0.0353925 0.0329109 -1 -1 -1 -1 26 1876 20 6.87369e+06 251529 503264. 1741.40 0.61 0.106442 0.0934101 24322 120374 -1 1676 21 1167 1874 125726 31327 3.02256 3.02256 -110.18 -3.02256 0 0 618332. 2139.56 0.03 0.04 0.11 -1 -1 0.03 0.0147437 0.0129497 99 63 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_012.v common 5.15 vpr 63.40 MiB -1 -1 0.24 18128 1 0.03 -1 -1 30064 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 23.8 MiB 2.09 828 9338 2215 6345 778 63.4 MiB 0.09 0.00 3.67066 -113.699 -3.67066 3.67066 0.34 0.000590743 0.000549309 0.0329731 0.0306745 -1 -1 -1 -1 28 2764 43 6.87369e+06 251529 531479. 1839.03 1.09 0.127315 0.111059 24610 126494 -1 1961 20 1277 1700 137309 35657 3.08581 3.08581 -116.238 -3.08581 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 23.9 MiB 2.12 926 9599 2091 6833 675 63.1 MiB 0.11 0.00 4.83358 -141.45 -4.83358 4.83358 0.33 0.000713803 0.000663884 0.0340711 0.0316564 -1 -1 -1 -1 30 2718 27 6.87369e+06 433189 556674. 1926.21 0.65 0.123589 0.10815 25186 138497 -1 1936 20 1247 1954 117467 30151 4.17226 4.17226 -144.094 -4.17226 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.014747 0.0130134 133 61 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_015.v common 4.22 vpr 63.17 MiB -1 -1 0.23 18132 1 0.03 -1 -1 30400 -1 -1 21 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 29 32 248 215 1 142 82 17 17 289 -1 unnamed_device 23.9 MiB 1.70 711 8982 2096 6475 411 63.2 MiB 0.08 0.00 3.07868 -92.9683 -3.07868 3.07868 0.33 0.000544701 0.000507131 0.0291861 0.0271418 -1 -1 -1 -1 30 1671 24 6.87369e+06 293451 556674. 1926.21 0.54 0.09513 0.0832085 25186 138497 -1 1338 20 791 1267 69154 17413 2.61566 2.61566 -91.2171 -2.61566 0 0 706193. 2443.58 0.04 0.06 0.11 -1 -1 0.04 0.0269583 0.0234237 94 27 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 5.24 vpr 63.32 MiB -1 -1 0.24 18324 1 0.03 -1 -1 30280 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 24.0 MiB 1.91 1084 8668 1982 6147 539 63.3 MiB 0.10 0.00 3.90567 -127.707 -3.90567 3.90567 0.34 0.000723408 0.000672104 0.0345784 0.0321445 -1 -1 -1 -1 26 3264 40 6.87369e+06 335372 503264. 1741.40 1.11 0.146809 0.128202 24322 120374 -1 2399 26 1846 3235 222891 55287 3.67301 3.67301 -130.22 -3.67301 0 0 618332. 2139.56 0.03 0.10 0.10 -1 -1 0.03 0.0345238 0.0298759 135 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 5.98 vpr 63.31 MiB -1 -1 0.14 18332 1 0.03 -1 -1 30080 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 338 269 1 204 87 17 17 289 -1 unnamed_device 24.0 MiB 3.16 1041 6615 1468 4357 790 63.3 MiB 0.09 0.00 4.18227 -133.396 -4.18227 4.18227 0.34 0.000705916 0.000657167 0.0262471 0.0244203 -1 -1 -1 -1 30 2762 25 6.87369e+06 321398 556674. 1926.21 0.64 0.11193 0.0976763 25186 138497 -1 1904 18 1127 1583 94947 23325 3.4571 3.4571 -119.55 -3.4571 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0250568 0.0218957 136 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 4.85 vpr 63.07 MiB -1 -1 0.17 18456 1 0.03 -1 -1 30260 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 323 276 1 156 93 17 17 289 -1 unnamed_device 23.9 MiB 2.21 961 14583 4168 8594 1821 63.1 MiB 0.13 0.00 2.88754 -107.489 -2.88754 2.88754 0.34 0.000653129 0.000606854 0.0473539 0.0439444 -1 -1 -1 -1 26 2202 23 6.87369e+06 405241 503264. 1741.40 0.71 0.126735 0.111657 24322 120374 -1 1966 21 1193 2019 142695 34226 2.22712 2.22712 -101.935 -2.22712 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0260927 0.0225956 110 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 3.10 vpr 63.05 MiB -1 -1 0.16 18180 1 0.03 -1 -1 30184 -1 -1 15 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 23.7 MiB 0.66 689 12139 3691 7050 1398 63.0 MiB 0.09 0.00 2.38778 -83.5564 -2.38778 2.38778 0.34 0.000495747 0.000461876 0.038516 0.0358607 -1 -1 -1 -1 32 1442 23 6.87369e+06 209608 586450. 2029.24 0.50 0.0985935 0.0870204 25474 144626 -1 1219 18 585 811 57943 14080 2.01382 2.01382 -84.6315 -2.01382 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0179977 0.0155952 71 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 5.39 vpr 63.12 MiB -1 -1 0.24 18340 1 0.03 -1 -1 30384 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 291 243 1 178 84 17 17 289 -1 unnamed_device 24.1 MiB 2.65 926 13626 5074 6419 2133 63.1 MiB 0.14 0.00 4.99433 -147.969 -4.99433 4.99433 0.33 0.00061624 0.000572644 0.0477352 0.04437 -1 -1 -1 -1 32 2269 22 6.87369e+06 293451 586450. 2029.24 0.61 0.120075 0.105959 25474 144626 -1 1823 19 1094 1607 107959 26850 3.64821 3.64821 -133.065 -3.64821 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0229829 0.0199895 114 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 3.77 vpr 63.66 MiB -1 -1 0.24 18488 1 0.03 -1 -1 30524 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65192 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 23.9 MiB 0.98 1087 13779 3849 8710 1220 63.7 MiB 0.14 0.00 4.23509 -137.221 -4.23509 4.23509 0.41 0.000700481 0.000649025 0.0450399 0.041707 -1 -1 -1 -1 32 2379 21 6.87369e+06 489084 586450. 2029.24 0.59 0.126272 0.11115 25474 144626 -1 1994 21 1330 2152 132705 31355 3.6621 3.6621 -128.504 -3.6621 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0278376 0.0241709 137 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_022.v common 4.99 vpr 63.32 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30268 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64836 32 32 372 300 1 206 87 17 17 289 -1 unnamed_device 24.2 MiB 2.22 1217 10647 2492 7086 1069 63.3 MiB 0.12 0.00 4.31025 -134.205 -4.31025 4.31025 0.33 0.000725524 0.000675176 0.0426199 0.0396102 -1 -1 -1 -1 32 2810 25 6.87369e+06 321398 586450. 2029.24 0.63 0.131393 0.11554 25474 144626 -1 2136 16 1278 2034 131099 31365 3.74246 3.74246 -129.143 -3.74246 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0238439 0.020874 138 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 4.12 vpr 62.94 MiB -1 -1 0.22 18228 1 0.02 -1 -1 30548 -1 -1 17 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64448 26 32 190 182 1 108 75 17 17 289 -1 unnamed_device 23.6 MiB 1.58 480 8133 3281 4323 529 62.9 MiB 0.06 0.00 2.38158 -69.4238 -2.38158 2.38158 0.34 0.00047137 0.000434655 0.0191877 0.0175956 -1 -1 -1 -1 28 1220 24 6.87369e+06 237555 531479. 1839.03 0.52 0.0720773 0.0625468 24610 126494 -1 1036 17 707 988 65067 17945 2.18312 2.18312 -75.9258 -2.18312 0 0 648988. 2245.63 0.03 0.04 0.10 -1 -1 0.03 0.014802 0.0128753 67 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 3.76 vpr 63.39 MiB -1 -1 0.22 17868 1 0.03 -1 -1 30344 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 285 227 1 169 87 17 17 289 -1 unnamed_device 23.8 MiB 1.15 1002 13719 4614 6837 2268 63.4 MiB 0.14 0.00 4.57022 -130.066 -4.57022 4.57022 0.33 0.00061934 0.000575759 0.0461905 0.0429273 -1 -1 -1 -1 30 2201 25 6.87369e+06 321398 556674. 1926.21 0.60 0.122115 0.10779 25186 138497 -1 1821 21 1157 2162 119285 29514 3.7041 3.7041 -123.476 -3.7041 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0254677 0.0220817 119 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 2.97 vpr 63.02 MiB -1 -1 0.12 17552 1 0.02 -1 -1 30008 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 23.8 MiB 0.62 529 9036 3698 5030 308 63.0 MiB 0.07 0.00 2.64533 -79.7813 -2.64533 2.64533 0.34 0.000423617 0.000392859 0.0254041 0.0235785 -1 -1 -1 -1 28 1296 30 6.87369e+06 167686 531479. 1839.03 0.56 0.0819974 0.0717561 24610 126494 -1 1030 14 522 612 45566 12360 2.19737 2.19737 -79.5748 -2.19737 0 0 648988. 2245.63 0.03 0.05 0.10 -1 -1 0.03 0.0206278 0.0179992 65 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 3.58 vpr 63.64 MiB -1 -1 0.23 18288 1 0.03 -1 -1 30140 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65172 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 24.0 MiB 0.98 1049 16069 4575 9607 1887 63.6 MiB 0.15 0.00 4.58208 -129.699 -4.58208 4.58208 0.33 0.000638368 0.000594438 0.0502991 0.046754 -1 -1 -1 -1 26 2413 24 6.87369e+06 419215 503264. 1741.40 0.61 0.127158 0.112378 24322 120374 -1 2176 20 1211 1947 151498 35401 3.8557 3.8557 -129.062 -3.8557 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0251252 0.0218207 120 24 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 3.62 vpr 63.05 MiB -1 -1 0.23 17932 1 0.03 -1 -1 30524 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 24.0 MiB 0.87 1082 17591 5231 9950 2410 63.0 MiB 0.16 0.00 3.50229 -113.775 -3.50229 3.50229 0.33 0.000639768 0.000594765 0.0541889 0.0503085 -1 -1 -1 -1 26 2515 20 6.87369e+06 433189 503264. 1741.40 0.72 0.128188 0.113567 24322 120374 -1 2222 18 1165 2078 132215 32194 3.07956 3.07956 -114.993 -3.07956 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 284 241 1 148 82 17 17 289 -1 unnamed_device 23.7 MiB 0.94 856 12720 4032 6930 1758 63.3 MiB 0.12 0.00 3.07458 -105.313 -3.07458 3.07458 0.33 0.000608 0.000559447 0.0450373 0.0417759 -1 -1 -1 -1 32 1770 20 6.87369e+06 251529 586450. 2029.24 0.53 0.114315 0.100881 25474 144626 -1 1498 21 757 1288 84508 20239 2.64866 2.64866 -104.259 -2.64866 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0130009 0.0114168 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.53 vpr 63.14 MiB -1 -1 0.14 18236 1 0.03 -1 -1 30272 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 30 32 262 227 1 138 87 17 17 289 -1 unnamed_device 23.6 MiB 1.11 850 14103 4319 8139 1645 63.1 MiB 0.12 0.00 3.14772 -102.363 -3.14772 3.14772 0.33 0.00056828 0.000529209 0.0435607 0.0405281 -1 -1 -1 -1 32 1755 31 6.87369e+06 349346 586450. 2029.24 0.57 0.118019 0.103831 25474 144626 -1 1498 19 881 1432 93880 22924 2.79396 2.79396 -97.0612 -2.79396 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0210251 0.018223 97 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 3.40 vpr 63.08 MiB -1 -1 0.16 18000 1 0.02 -1 -1 30160 -1 -1 24 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64596 28 32 260 223 1 140 84 17 17 289 -1 unnamed_device 23.5 MiB 0.98 762 14175 5132 6824 2219 63.1 MiB 0.12 0.00 3.46791 -98.5079 -3.46791 3.46791 0.34 0.000563734 0.000522844 0.045193 0.0418736 -1 -1 -1 -1 32 1793 20 6.87369e+06 335372 586450. 2029.24 0.55 0.110531 0.0973165 25474 144626 -1 1515 22 1016 1832 127699 30852 2.85696 2.85696 -98.0028 -2.85696 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.023617 0.0204119 98 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_032.v common 3.74 vpr 63.33 MiB -1 -1 0.16 17904 1 0.03 -1 -1 30268 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64848 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 23.7 MiB 1.29 755 8448 1958 6116 374 63.3 MiB 0.09 0.00 3.92118 -117.55 -3.92118 3.92118 0.33 0.000566959 0.000528139 0.0291684 0.0271468 -1 -1 -1 -1 28 2136 22 6.87369e+06 251529 531479. 1839.03 0.64 0.0969963 0.0849626 24610 126494 -1 1789 21 1303 2060 129617 33406 3.24686 3.24686 -120.536 -3.24686 0 0 648988. 2245.63 0.03 0.07 0.11 -1 -1 0.03 0.0233859 0.0202504 101 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_033.v common 3.22 vpr 63.34 MiB -1 -1 0.21 18088 1 0.03 -1 -1 30404 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 31 32 271 231 1 149 89 17 17 289 -1 unnamed_device 23.7 MiB 0.85 947 11771 3021 7217 1533 63.3 MiB 0.11 0.00 3.40475 -107.115 -3.40475 3.40475 0.34 0.000611176 0.000561225 0.0377071 0.0349827 -1 -1 -1 -1 32 2054 22 6.87369e+06 363320 586450. 2029.24 0.56 0.10753 0.0944819 25474 144626 -1 1803 18 928 1643 117337 27902 2.95826 2.95826 -108.892 -2.95826 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0114211 0.0100919 102 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 4.89 vpr 63.20 MiB -1 -1 0.17 18508 1 0.03 -1 -1 30520 -1 -1 25 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64712 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 23.6 MiB 2.42 855 9536 2217 6358 961 63.2 MiB 0.09 0.00 3.08002 -99.9202 -3.08002 3.08002 0.34 0.000605347 0.000562439 0.0322847 0.0300207 -1 -1 -1 -1 32 1836 20 6.87369e+06 349346 586450. 2029.24 0.54 0.101683 0.0890847 25474 144626 -1 1618 17 896 1401 87699 22004 2.36147 2.36147 -96.2223 -2.36147 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0208019 0.0180997 105 54 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_035.v common 5.60 vpr 63.82 MiB -1 -1 0.22 18412 1 0.04 -1 -1 30340 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 367 282 1 201 104 17 17 289 -1 unnamed_device 24.2 MiB 2.99 1201 11572 2628 7875 1069 63.8 MiB 0.12 0.00 4.28409 -125.895 -4.28409 4.28409 0.33 0.000745621 0.000691639 0.0376247 0.0349383 -1 -1 -1 -1 32 2850 21 6.87369e+06 558954 586450. 2029.24 0.60 0.123608 0.108597 25474 144626 -1 2283 22 1202 2387 140467 34356 3.5931 3.5931 -122.354 -3.5931 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0309075 0.0268465 156 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_036.v common 5.65 vpr 63.77 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30256 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 32 32 391 311 1 194 104 17 17 289 -1 unnamed_device 24.1 MiB 2.85 1115 17428 4398 11199 1831 63.8 MiB 0.18 0.00 4.01296 -135.521 -4.01296 4.01296 0.33 0.000766942 0.000704452 0.0562864 0.0519881 -1 -1 -1 -1 32 2421 26 6.87369e+06 558954 586450. 2029.24 0.61 0.150049 0.132322 25474 144626 -1 2065 20 1509 2448 142727 34833 3.01616 3.01616 -125.596 -3.01616 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.029391 0.0255786 149 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 4.36 vpr 63.29 MiB -1 -1 0.22 18292 1 0.13 -1 -1 30024 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 23.6 MiB 1.83 846 9881 2610 5928 1343 63.3 MiB 0.10 0.00 4.09163 -121.619 -4.09163 4.09163 0.33 0.000593945 0.000552927 0.0353443 0.0329006 -1 -1 -1 -1 32 1941 25 6.87369e+06 251529 586450. 2029.24 0.56 0.108321 0.0951512 25474 144626 -1 1646 21 1100 1628 113634 27943 2.96331 2.96331 -109.173 -2.96331 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0136148 0.011982 105 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_038.v common 5.10 vpr 63.34 MiB -1 -1 0.20 18388 1 0.03 -1 -1 30396 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 31 32 370 297 1 187 89 17 17 289 -1 unnamed_device 24.3 MiB 2.43 1023 15533 5566 7049 2918 63.3 MiB 0.16 0.00 3.72294 -120.106 -3.72294 3.72294 0.33 0.000718031 0.000666124 0.0592263 0.0550182 -1 -1 -1 -1 30 2608 22 6.87369e+06 363320 556674. 1926.21 0.67 0.14449 0.127836 25186 138497 -1 2002 16 1255 2178 123141 30081 3.01531 3.01531 -116.913 -3.01531 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0236042 0.0206111 136 61 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_039.v common 6.30 vpr 63.29 MiB -1 -1 0.23 18360 1 0.03 -1 -1 30336 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 31 32 377 302 1 237 92 17 17 289 -1 unnamed_device 24.3 MiB 3.21 1226 11477 3074 7440 963 63.3 MiB 0.14 0.00 5.94301 -174.677 -5.94301 5.94301 0.33 0.000740882 0.00068947 0.0435873 0.0404978 -1 -1 -1 -1 32 3381 27 6.87369e+06 405241 586450. 2029.24 0.86 0.135821 0.119293 25474 144626 -1 2594 21 2065 3065 259228 59072 4.91379 4.91379 -168.168 -4.91379 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.030074 0.0261518 156 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_040.v common 10.36 vpr 63.25 MiB -1 -1 0.13 18256 1 0.03 -1 -1 30432 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64772 31 32 383 305 1 212 91 17 17 289 -1 unnamed_device 24.2 MiB 3.73 1111 18247 5857 8950 3440 63.3 MiB 0.17 0.00 5.17369 -157.317 -5.17369 5.17369 0.34 0.000735997 0.000683017 0.0685617 0.0636389 -1 -1 -1 -1 32 3441 45 6.87369e+06 391268 586450. 2029.24 4.57 0.366723 0.317795 25474 144626 -1 2256 24 1622 2535 185379 47271 4.9157 4.9157 -166.109 -4.9157 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0333739 0.0289693 151 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 5.01 vpr 63.19 MiB -1 -1 0.19 18320 1 0.03 -1 -1 30352 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 31 32 352 285 1 186 91 17 17 289 -1 unnamed_device 24.0 MiB 2.47 1131 11311 2943 7349 1019 63.2 MiB 0.13 0.00 4.13563 -130.877 -4.13563 4.13563 0.33 0.000699135 0.000649874 0.0415874 0.0386624 -1 -1 -1 -1 32 2600 24 6.87369e+06 391268 586450. 2029.24 0.59 0.128261 0.113076 25474 144626 -1 2128 18 1230 2196 131110 32142 3.01051 3.01051 -116.588 -3.01051 0 0 744469. 2576.02 0.04 0.07 0.13 -1 -1 0.04 0.0280873 0.0248281 132 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 4.67 vpr 63.59 MiB -1 -1 0.14 18176 1 0.04 -1 -1 30420 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65116 32 32 291 242 1 183 86 17 17 289 -1 unnamed_device 24.0 MiB 2.08 1141 9158 2504 6028 626 63.6 MiB 0.10 0.00 4.45965 -121.916 -4.45965 4.45965 0.33 0.00062293 0.000575167 0.0320274 0.0298167 -1 -1 -1 -1 26 2762 22 6.87369e+06 307425 503264. 1741.40 0.76 0.106328 0.0931794 24322 120374 -1 2331 25 1513 2202 176135 41792 4.13656 4.13656 -128.468 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-1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64740 31 32 261 225 1 148 83 17 17 289 -1 unnamed_device 23.7 MiB 1.65 712 6743 1427 4646 670 63.2 MiB 0.07 0.00 3.53695 -102.057 -3.53695 3.53695 0.33 0.000580111 0.000533635 0.0235301 0.0218269 -1 -1 -1 -1 30 1801 19 6.87369e+06 279477 556674. 1926.21 1.25 0.14987 0.128847 25186 138497 -1 1472 24 1139 2012 112446 28814 2.71766 2.71766 -99.2166 -2.71766 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.025589 0.0220302 95 28 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_045.v common 5.49 vpr 63.11 MiB -1 -1 0.21 18396 1 0.03 -1 -1 30176 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 23.9 MiB 2.51 1167 9448 2299 6357 792 63.1 MiB 0.12 0.00 4.84783 -145.415 -4.84783 4.84783 0.33 0.000681899 0.000634009 0.0364431 0.0338906 -1 -1 -1 -1 26 3222 39 6.87369e+06 349346 503264. 1741.40 0.88 0.136534 0.11933 24322 120374 -1 2636 21 1907 2825 215476 51329 4.38896 4.38896 -148.594 -4.38896 0 0 618332. 2139.56 0.03 0.08 0.08 -1 -1 0.03 0.0276589 0.0240477 139 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_046.v common 4.53 vpr 63.29 MiB -1 -1 0.23 18428 1 0.02 -1 -1 30416 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 32 32 349 284 1 183 96 17 17 289 -1 unnamed_device 24.0 MiB 1.74 1161 10170 2713 6697 760 63.3 MiB 0.12 0.00 3.7235 -118.305 -3.7235 3.7235 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 32 32 361 291 1 189 97 17 17 289 -1 unnamed_device 24.1 MiB 2.80 942 18079 4845 10579 2655 63.1 MiB 0.17 0.00 3.80724 -119.205 -3.80724 3.80724 0.33 0.000719091 0.000668366 0.0611155 0.0567946 -1 -1 -1 -1 32 2842 49 6.87369e+06 461137 586450. 2029.24 0.76 0.175295 0.154435 25474 144626 -1 2003 21 1296 2243 161130 40238 3.17181 3.17181 -117.395 -3.17181 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0299406 0.0260509 137 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_050.v common 5.43 vpr 63.39 MiB -1 -1 0.26 18356 1 0.03 -1 -1 30236 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 382 305 1 193 99 17 17 289 -1 unnamed_device 24.3 MiB 2.75 1194 15147 4115 8922 2110 63.4 MiB 0.17 0.00 4.12873 -137.061 -4.12873 4.12873 0.33 0.000747128 0.000694047 0.0516993 0.0480117 -1 -1 -1 -1 30 2637 23 6.87369e+06 489084 556674. 1926.21 0.62 0.140245 0.123846 25186 138497 -1 2186 20 1312 2080 127606 30703 3.18081 3.18081 -123.292 -3.18081 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0284563 0.0247655 145 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 3.96 vpr 63.45 MiB -1 -1 0.26 18084 1 0.03 -1 -1 30416 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64968 32 32 306 248 1 170 97 17 17 289 -1 unnamed_device 24.3 MiB 0.96 1051 16969 4458 10747 1764 63.4 MiB 0.16 0.00 4.25889 -127.121 -4.25889 4.25889 0.33 0.000643879 0.000599022 0.0513577 0.0476883 -1 -1 -1 -1 28 2418 26 6.87369e+06 461137 531479. 1839.03 0.59 0.132297 0.11702 24610 126494 -1 2119 22 1403 2481 165711 40053 4.2163 4.2163 -131.586 -4.2163 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0267192 0.0231603 124 24 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 4.58 vpr 63.15 MiB -1 -1 0.18 18544 1 0.03 -1 -1 30256 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 32 32 319 257 1 203 87 17 17 289 -1 unnamed_device 24.0 MiB 1.82 1159 5847 1196 4159 492 63.1 MiB 0.07 0.00 4.90813 -141.116 -4.90813 4.90813 0.33 0.000655955 0.000610109 0.0221425 0.0206032 -1 -1 -1 -1 30 2614 20 6.87369e+06 321398 556674. 1926.21 0.61 0.0978835 0.0853734 25186 138497 -1 2189 21 1298 1910 108067 26664 3.78346 3.78346 -130.411 -3.78346 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.026572 0.023122 131 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 4.84 vpr 63.18 MiB -1 -1 0.15 18304 1 0.03 -1 -1 30300 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 31 32 373 299 1 204 87 17 17 289 -1 unnamed_device 23.9 MiB 2.11 1104 15639 5017 7583 3039 63.2 MiB 0.17 0.00 4.75448 -143.415 -4.75448 4.75448 0.34 0.000721909 0.000671142 0.0613266 0.0569853 -1 -1 -1 -1 32 2855 22 6.87369e+06 335372 586450. 2029.24 0.69 0.149738 0.132769 25474 144626 -1 2208 19 1430 2340 173817 40610 3.83796 3.83796 -133.557 -3.83796 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.030116 0.0262036 140 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 5.03 vpr 63.30 MiB -1 -1 0.14 18384 1 0.03 -1 -1 30284 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 387 315 1 194 86 17 17 289 -1 unnamed_device 24.2 MiB 2.41 1107 13883 4421 7374 2088 63.3 MiB 0.15 0.00 4.4264 -134.375 -4.4264 4.4264 0.34 0.00074745 0.000694485 0.0572042 0.0531062 -1 -1 -1 -1 32 2766 23 6.87369e+06 307425 586450. 2029.24 0.63 0.14684 0.129797 25474 144626 -1 2283 20 1421 2543 162506 40189 3.63536 3.63536 -132.707 -3.63536 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0293206 0.0255442 134 77 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 3.49 vpr 63.16 MiB -1 -1 0.22 18112 1 0.03 -1 -1 30340 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 251 219 1 141 87 17 17 289 -1 unnamed_device 23.7 MiB 0.88 781 8151 1829 5687 635 63.2 MiB 0.08 0.00 3.42581 -102.974 -3.42581 3.42581 0.41 0.000559902 0.000521562 0.0254085 0.0236473 -1 -1 -1 -1 28 1904 23 6.87369e+06 321398 531479. 1839.03 0.53 0.0929223 0.0810831 24610 126494 -1 1688 22 1081 1762 117647 29623 2.79596 2.79596 -101.105 -2.79596 0 0 648988. 2245.63 0.03 0.06 0.10 -1 -1 0.03 0.0233409 0.0201884 93 23 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 4.41 vpr 63.22 MiB -1 -1 0.25 18552 1 0.03 -1 -1 30108 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 341 285 1 188 84 17 17 289 -1 unnamed_device 24.0 MiB 1.74 910 13260 3607 7806 1847 63.2 MiB 0.14 0.00 3.77904 -129.086 -3.77904 3.77904 0.33 0.000677957 0.000630665 0.0508368 0.047249 -1 -1 -1 -1 32 2421 25 6.87369e+06 279477 586450. 2029.24 0.62 0.133094 0.117462 25474 144626 -1 1923 21 1469 2059 133480 33321 3.30611 3.30611 -126.077 -3.30611 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0269363 0.0233703 120 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 5.27 vpr 63.93 MiB -1 -1 0.25 18328 1 0.03 -1 -1 30320 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 32 32 387 293 1 235 91 17 17 289 -1 unnamed_device 24.2 MiB 2.26 1446 16003 4513 9679 1811 63.9 MiB 0.20 0.00 5.45062 -164.1 -5.45062 5.45062 0.33 0.000765113 0.000710511 0.0625287 0.0580806 -1 -1 -1 -1 28 3827 27 6.87369e+06 377294 531479. 1839.03 0.95 0.162884 0.144247 24610 126494 -1 3174 24 2379 3636 266572 63430 5.026 5.026 -170.437 -5.026 0 0 648988. 2245.63 0.03 0.11 0.11 -1 -1 0.03 0.0356458 0.0310264 163 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_058.v common 5.19 vpr 63.83 MiB -1 -1 0.22 18408 1 0.03 -1 -1 30368 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65364 32 32 340 270 1 185 98 17 17 289 -1 unnamed_device 24.0 MiB 2.64 1118 12923 3108 8715 1100 63.8 MiB 0.14 0.00 4.49891 -142.201 -4.49891 4.49891 0.33 0.000673492 0.000619904 0.0430244 0.0399706 -1 -1 -1 -1 32 2521 22 6.87369e+06 475111 586450. 2029.24 0.58 0.126419 0.1116 25474 144626 -1 2072 19 1267 2113 137525 33579 3.11326 3.11326 -127.341 -3.11326 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0256752 0.0223967 137 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_059.v common 3.23 vpr 63.53 MiB -1 -1 0.24 18052 1 0.03 -1 -1 30460 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 30 32 278 235 1 150 87 17 17 289 -1 unnamed_device 23.8 MiB 0.67 780 11991 2894 8475 622 63.5 MiB 0.11 0.00 3.57685 -110.542 -3.57685 3.57685 0.30 0.00059148 0.000550047 0.0366114 0.0339228 -1 -1 -1 -1 26 2085 23 6.87369e+06 349346 503264. 1741.40 0.76 0.10767 0.0943904 24322 120374 -1 1811 21 1236 2012 147312 38902 3.10156 3.10156 -113.453 -3.10156 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.023601 0.0204161 104 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_060.v common 6.87 vpr 63.43 MiB -1 -1 0.27 18568 1 0.03 -1 -1 30284 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64956 32 32 431 332 1 239 91 17 17 289 -1 unnamed_device 24.5 MiB 4.02 1420 13147 3569 8315 1263 63.4 MiB 0.16 0.00 5.92629 -174.407 -5.92629 5.92629 0.34 0.000833342 0.00077516 0.0564343 0.0524045 -1 -1 -1 -1 32 3147 27 6.87369e+06 377294 586450. 2029.24 0.69 0.163689 0.144051 25474 144626 -1 2602 19 1701 2677 174677 41715 4.7336 4.7336 -161.132 -4.7336 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0308763 0.0269051 166 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_061.v common 5.42 vpr 63.79 MiB -1 -1 0.24 18388 1 0.03 -1 -1 30364 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65316 32 32 336 268 1 182 99 17 17 289 -1 unnamed_device 24.0 MiB 2.76 1022 11043 2817 7461 765 63.8 MiB 0.11 0.00 4.68232 -141.336 -4.68232 4.68232 0.33 0.000696088 0.000647253 0.0357086 0.0331238 -1 -1 -1 -1 32 2244 25 6.87369e+06 489084 586450. 2029.24 0.59 0.120339 0.105641 25474 144626 -1 1837 21 1382 2159 118015 30016 3.5788 3.5788 -126.007 -3.5788 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0276469 0.0240155 135 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_062.v common 4.03 vpr 63.44 MiB -1 -1 0.22 17936 1 0.03 -1 -1 30292 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64960 32 32 231 199 1 142 92 17 17 289 -1 unnamed_device 23.9 MiB 0.76 952 13754 3685 8569 1500 63.4 MiB 0.12 0.00 3.65166 -105.903 -3.65166 3.65166 0.34 0.000538237 0.000500843 0.0381477 0.0354746 -1 -1 -1 -1 28 2055 22 6.87369e+06 391268 531479. 1839.03 0.54 0.102196 0.0900138 24610 126494 -1 1741 19 874 1554 114632 26729 3.03561 3.03561 -105.274 -3.03561 0 0 648988. 2245.63 0.03 0.06 0.08 -1 -1 0.03 0.0203082 0.0175966 96 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 4.89 vpr 63.26 MiB -1 -1 0.23 18412 1 0.03 -1 -1 30272 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 32 32 349 273 1 191 101 17 17 289 -1 unnamed_device 24.0 MiB 2.00 1239 18196 5620 10238 2338 63.3 MiB 0.18 0.00 5.34161 -141.066 -5.34161 5.34161 0.33 0.000710511 0.000657709 0.0583585 0.0538307 -1 -1 -1 -1 30 2783 24 6.87369e+06 517032 556674. 1926.21 0.72 0.154647 0.136888 25186 138497 -1 2319 21 1461 2924 184023 42728 4.22195 4.22195 -135.723 -4.22195 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.0286229 0.0248525 145 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 3.54 vpr 63.56 MiB -1 -1 0.15 17904 1 0.03 -1 -1 30144 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65084 32 32 247 207 1 153 85 17 17 289 -1 unnamed_device 23.9 MiB 1.05 897 15337 5119 7874 2344 63.6 MiB 0.13 0.00 3.56305 -113.438 -3.56305 3.56305 0.33 0.000555907 0.000516935 0.048281 0.0448719 -1 -1 -1 -1 32 2070 20 6.87369e+06 293451 586450. 2029.24 0.56 0.113008 0.100078 25474 144626 -1 1815 21 1262 2238 153889 35786 2.87996 2.87996 -110.843 -2.87996 0 0 744469. 2576.02 0.03 0.07 0.13 -1 -1 0.03 0.0224254 0.0194167 99 3 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 4.50 vpr 63.21 MiB -1 -1 0.24 18168 1 0.03 -1 -1 30436 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 30 32 278 235 1 151 96 17 17 289 -1 unnamed_device 23.6 MiB 2.07 912 16302 4828 9136 2338 63.2 MiB 0.08 0.00 3.98176 -118.667 -3.98176 3.98176 0.26 0.000276471 0.000248271 0.0217191 0.01981 -1 -1 -1 -1 26 2091 22 6.87369e+06 475111 503264. 1741.40 0.50 0.0611662 0.0536977 24322 120374 -1 1886 19 1130 2030 131294 33386 3.10226 3.10226 -114.681 -3.10226 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0221492 0.0191797 109 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 5.18 vpr 63.14 MiB -1 -1 0.26 18392 1 0.03 -1 -1 30332 -1 -1 26 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 29 32 355 287 1 200 87 17 17 289 -1 unnamed_device 23.9 MiB 2.47 1138 9879 2524 6508 847 63.1 MiB 0.11 0.00 4.16737 -125.588 -4.16737 4.16737 0.34 0.00070545 0.000656964 0.038101 0.0354197 -1 -1 -1 -1 26 3080 23 6.87369e+06 363320 503264. 1741.40 0.65 0.124906 0.109698 24322 120374 -1 2586 20 1688 2528 198148 46939 3.83206 3.83206 -130.566 -3.83206 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0271976 0.0236497 136 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_067.v common 4.61 vpr 63.30 MiB -1 -1 0.14 18396 1 0.03 -1 -1 30300 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 358 289 1 183 90 17 17 289 -1 unnamed_device 24.0 MiB 2.07 1034 14763 4115 8879 1769 63.3 MiB 0.15 0.00 4.56255 -145.294 -4.56255 4.56255 0.33 0.000706084 0.000656237 0.0540242 0.050208 -1 -1 -1 -1 32 2336 21 6.87369e+06 363320 586450. 2029.24 0.63 0.138549 0.122618 25474 144626 -1 1904 17 1252 1923 121500 28801 3.85766 3.85766 -135.319 -3.85766 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0134867 0.0119686 132 54 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_068.v common 5.03 vpr 63.16 MiB -1 -1 0.26 18412 1 0.03 -1 -1 30232 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 353 285 1 188 93 17 17 289 -1 unnamed_device 23.9 MiB 2.18 1032 17103 5602 8670 2831 63.2 MiB 0.17 0.00 4.79103 -139.615 -4.79103 4.79103 0.34 0.000696183 0.000646015 0.0590853 0.0548123 -1 -1 -1 -1 32 2900 27 6.87369e+06 405241 586450. 2029.24 0.67 0.149928 0.132477 25474 144626 -1 2176 23 1449 2597 174377 41794 3.66236 3.66236 -128.606 -3.66236 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0307027 0.0267017 134 51 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_069.v common 4.97 vpr 63.34 MiB -1 -1 0.12 18092 1 0.03 -1 -1 30112 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 32 32 276 237 1 165 81 17 17 289 -1 unnamed_device 23.7 MiB 2.62 947 9706 2619 6448 639 63.3 MiB 0.10 0.00 4.51686 -127.927 -4.51686 4.51686 0.34 0.000594314 0.000552804 0.0348864 0.0324832 -1 -1 -1 -1 32 2103 29 6.87369e+06 237555 586450. 2029.24 0.57 0.11248 0.0986961 25474 144626 -1 1866 21 1041 1496 114762 27029 3.13531 3.13531 -117.494 -3.13531 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0134532 0.0118711 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_070.v common 4.98 vpr 63.09 MiB -1 -1 0.25 18468 1 0.03 -1 -1 30400 -1 -1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 31 32 319 272 1 176 83 17 17 289 -1 unnamed_device 24.0 MiB 2.28 815 11963 2932 8103 928 63.1 MiB 0.11 0.00 3.7214 -117.821 -3.7214 3.7214 0.33 0.000642969 0.000598055 0.0446753 0.0415087 -1 -1 -1 -1 32 2447 35 6.87369e+06 279477 586450. 2029.24 0.65 0.132911 0.116764 25474 144626 -1 1648 18 1255 1811 115960 30273 3.13061 3.13061 -113.813 -3.13061 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.023017 0.0200541 110 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_071.v common 4.91 vpr 63.10 MiB -1 -1 0.25 18340 1 0.03 -1 -1 30372 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 30 32 329 273 1 167 96 17 17 289 -1 unnamed_device 23.9 MiB 2.19 1016 17616 5582 9654 2380 63.1 MiB 0.16 0.00 3.48905 -102.473 -3.48905 3.48905 0.34 0.000658679 0.000611852 0.055243 0.0512742 -1 -1 -1 -1 28 2346 23 6.87369e+06 475111 531479. 1839.03 0.56 0.135181 0.119563 24610 126494 -1 2025 22 1317 2333 143046 35830 2.93056 2.93056 -101.97 -2.93056 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0274558 0.0237741 124 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_072.v common 4.74 vpr 63.03 MiB -1 -1 0.23 18160 1 0.03 -1 -1 30408 -1 -1 35 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64544 28 32 277 229 1 156 95 17 17 289 -1 unnamed_device 23.7 MiB 1.62 942 17375 5412 9917 2046 63.0 MiB 0.14 0.00 4.15879 -107.762 -4.15879 4.15879 0.33 0.000596877 0.000555385 0.0497932 0.046256 -1 -1 -1 -1 26 2158 21 6.87369e+06 489084 503264. 1741.40 0.68 0.128929 0.113776 24322 120374 -1 1940 81 3637 6717 511772 117111 3.947 3.947 -114.579 -3.947 0 0 618332. 2139.56 0.03 0.21 0.07 -1 -1 0.03 0.0759938 0.0645077 117 27 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 5.24 vpr 63.37 MiB -1 -1 0.12 18380 1 0.03 -1 -1 30424 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64892 30 32 317 269 1 156 80 17 17 289 -1 unnamed_device 24.0 MiB 2.72 914 13496 4233 7612 1651 63.4 MiB 0.14 0.00 3.85608 -120.401 -3.85608 3.85608 0.34 0.000630011 0.000585172 0.051381 0.0476878 -1 -1 -1 -1 32 2066 24 6.87369e+06 251529 586450. 2029.24 0.61 0.132137 0.116563 25474 144626 -1 1808 22 1276 2281 150695 35758 3.09126 3.09126 -120.425 -3.09126 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0273207 0.0236964 105 63 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 4.59 vpr 63.08 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30072 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64592 32 32 335 282 1 189 84 17 17 289 -1 unnamed_device 23.9 MiB 2.01 1004 6855 1530 4961 364 63.1 MiB 0.08 0.00 3.6946 -124.308 -3.6946 3.6946 0.33 0.000666465 0.000620289 0.0269554 0.0250659 -1 -1 -1 -1 28 2476 23 6.87369e+06 279477 531479. 1839.03 0.58 0.106325 0.0927977 24610 126494 -1 2194 23 1488 2178 170330 42033 3.28611 3.28611 -130.137 -3.28611 0 0 648988. 2245.63 0.03 0.08 0.12 -1 -1 0.03 0.0285581 0.0246782 118 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_075.v common 3.51 vpr 63.07 MiB -1 -1 0.24 17948 1 0.03 -1 -1 30292 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 31 32 293 230 1 175 96 17 17 289 -1 unnamed_device 24.0 MiB 0.92 1091 9075 2015 6280 780 63.1 MiB 0.10 0.00 4.61548 -132.875 -4.61548 4.61548 0.33 0.000631977 0.000587553 0.028804 0.0267387 -1 -1 -1 -1 26 2616 23 6.87369e+06 461137 503264. 1741.40 0.69 0.105235 0.0920603 24322 120374 -1 2293 21 1418 2488 166028 39907 3.8604 3.8604 -130.723 -3.8604 0 0 618332. 2139.56 0.02 0.04 0.07 -1 -1 0.02 0.0137315 0.012053 130 4 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 5.58 vpr 63.24 MiB -1 -1 0.15 18428 1 0.03 -1 -1 30448 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 32 32 350 275 1 214 89 17 17 289 -1 unnamed_device 24.3 MiB 2.94 1200 15731 4693 8579 2459 63.2 MiB 0.17 0.00 4.80258 -153.363 -4.80258 4.80258 0.33 0.000703729 0.0006543 0.0576808 0.053582 -1 -1 -1 -1 32 3003 23 6.87369e+06 349346 586450. 2029.24 0.66 0.14232 0.126023 25474 144626 -1 2526 21 1639 2470 197373 45896 4.12826 4.12826 -146.013 -4.12826 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0284546 0.0247738 142 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 6.24 vpr 63.32 MiB -1 -1 0.26 18460 1 0.03 -1 -1 30252 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64836 32 32 385 308 1 195 101 17 17 289 -1 unnamed_device 24.2 MiB 3.49 1124 13496 3681 8868 947 63.3 MiB 0.15 0.00 5.22228 -150.906 -5.22228 5.22228 0.34 0.000752487 0.000696927 0.0455464 0.0421192 -1 -1 -1 -1 30 2530 21 6.87369e+06 517032 556674. 1926.21 0.66 0.135733 0.119283 25186 138497 -1 2081 21 1252 2234 136986 32950 3.78145 3.78145 -137.672 -3.78145 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0298214 0.0259139 147 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_078.v common 6.11 vpr 63.93 MiB -1 -1 0.26 18560 1 0.03 -1 -1 30276 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65468 32 32 387 309 1 192 105 17 17 289 -1 unnamed_device 24.2 MiB 2.74 987 13690 3687 9358 645 63.9 MiB 0.14 0.00 4.53808 -140.381 -4.53808 4.53808 0.33 0.000749439 0.000696383 0.0438679 0.0405747 -1 -1 -1 -1 40 2022 24 6.87369e+06 572927 706193. 2443.58 1.23 0.19167 0.166443 26914 176310 -1 1886 21 1261 2401 156153 39758 3.6171 3.6171 -127.506 -3.6171 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0300207 0.0261017 148 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 4.70 vpr 63.23 MiB -1 -1 0.23 18128 1 0.03 -1 -1 30216 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64748 30 32 272 232 1 151 80 17 17 289 -1 unnamed_device 23.6 MiB 2.20 813 9024 2370 5899 755 63.2 MiB 0.10 0.00 3.89188 -117.262 -3.89188 3.89188 0.33 0.000584829 0.000544928 0.0324753 0.0302551 -1 -1 -1 -1 32 1912 21 6.87369e+06 251529 586450. 2029.24 0.55 0.100521 0.0882835 25474 144626 -1 1652 20 1057 1880 121709 29083 2.97696 2.97696 -107.258 -2.97696 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226212 0.0196254 99 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 5.57 vpr 63.89 MiB -1 -1 0.14 18284 1 0.02 -1 -1 30372 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65424 30 32 375 299 1 188 85 17 17 289 -1 unnamed_device 24.0 MiB 3.12 1029 9757 2105 6512 1140 63.9 MiB 0.12 0.00 4.57902 -143.928 -4.57902 4.57902 0.33 0.000730298 0.000678703 0.0403111 0.0374677 -1 -1 -1 -1 28 2535 23 6.87369e+06 321398 531479. 1839.03 0.64 0.127412 0.111966 24610 126494 -1 2307 21 1874 2865 205104 49082 3.9547 3.9547 -144.752 -3.9547 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0166106 0.0146556 137 63 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 5.03 vpr 63.10 MiB -1 -1 0.24 18356 1 0.03 -1 -1 30352 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 23.9 MiB 2.02 1137 13355 3696 8021 1638 63.1 MiB 0.15 0.00 5.16481 -152.482 -5.16481 5.16481 0.33 0.00068747 0.000638496 0.0488585 0.0454013 -1 -1 -1 -1 28 3018 30 6.87369e+06 349346 531479. 1839.03 0.86 0.140547 0.123885 24610 126494 -1 2524 24 1875 2946 236442 55729 4.90886 4.90886 -155.241 -4.90886 0 0 648988. 2245.63 0.03 0.09 0.11 -1 -1 0.03 0.0312093 0.027068 136 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 6.14 vpr 63.24 MiB -1 -1 0.24 18392 1 0.03 -1 -1 30196 -1 -1 31 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 31 32 340 275 1 201 94 17 17 289 -1 unnamed_device 24.0 MiB 2.51 1095 17560 6469 8624 2467 63.2 MiB 0.17 0.00 5.28104 -147.847 -5.28104 5.28104 0.33 0.000689075 0.000639545 0.0588762 0.0546834 -1 -1 -1 -1 28 3079 44 6.87369e+06 433189 531479. 1839.03 1.22 0.166584 0.14682 24610 126494 -1 2291 23 1877 3073 206403 52519 4.5206 4.5206 -147.07 -4.5206 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 32 32 365 294 1 187 86 17 17 289 -1 unnamed_device 24.0 MiB 2.29 977 11804 3582 6996 1226 63.3 MiB 0.15 0.00 4.77578 -141.077 -4.77578 4.77578 0.34 0.000721237 0.000668993 0.0471484 0.0438001 -1 -1 -1 -1 30 2619 21 6.87369e+06 307425 556674. 1926.21 0.66 0.132756 0.116983 25186 138497 -1 2066 20 1426 2450 128813 33448 3.90766 3.90766 -135.71 -3.90766 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0277408 0.024151 132 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 5.03 vpr 63.49 MiB -1 -1 0.27 18544 1 0.03 -1 -1 30308 -1 -1 29 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65016 29 32 378 310 1 179 90 17 17 289 -1 unnamed_device 24.2 MiB 2.28 945 16170 4095 11127 948 63.5 MiB 0.16 0.00 4.12999 -122.875 -4.12999 4.12999 0.33 0.000715356 0.000664292 0.0600459 0.055713 -1 -1 -1 -1 32 2398 22 6.87369e+06 405241 586450. 2029.24 0.61 0.145064 0.128358 25474 144626 -1 1959 21 1386 2247 136731 34828 3.12181 3.12181 -115.774 -3.12181 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0291387 0.025244 132 85 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.69 vpr 63.22 MiB -1 -1 0.21 17864 1 0.03 -1 -1 30328 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 243 205 1 149 82 17 17 289 -1 unnamed_device 23.6 MiB 1.07 892 12542 3412 7235 1895 63.2 MiB 0.11 0.00 3.98264 -119.291 -3.98264 3.98264 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65128 32 32 269 231 1 170 82 17 17 289 -1 unnamed_device 23.9 MiB 2.13 994 9694 2678 5995 1021 63.6 MiB 0.10 0.00 4.37292 -124.998 -4.37292 4.37292 0.33 0.00058825 0.000548397 0.0336292 0.0313019 -1 -1 -1 -1 26 2325 22 6.87369e+06 251529 503264. 1741.40 0.62 0.103077 0.090504 24322 120374 -1 2098 22 1212 1576 117648 28606 3.4928 3.4928 -124.305 -3.4928 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0245323 0.0212581 103 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_090.v common 3.70 vpr 63.16 MiB -1 -1 0.23 17880 1 0.03 -1 -1 30368 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64680 31 32 245 205 1 153 84 17 17 289 -1 unnamed_device 23.7 MiB 1.09 879 14358 4211 8419 1728 63.2 MiB 0.13 0.00 3.81898 -115.032 -3.81898 3.81898 0.33 0.000551096 0.000512803 0.0451184 0.0419713 -1 -1 -1 -1 32 1927 21 6.87369e+06 293451 586450. 2029.24 0.58 0.11685 0.103169 25474 144626 -1 1705 21 1147 1895 134417 30219 2.80196 2.80196 -107.148 -2.80196 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226517 0.0196196 100 4 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 5.14 vpr 63.21 MiB -1 -1 0.24 18416 1 0.03 -1 -1 30464 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 32 32 348 274 1 215 88 17 17 289 -1 unnamed_device 24.0 MiB 2.49 1167 13738 4717 6121 2900 63.2 MiB 0.14 0.00 4.82535 -151.45 -4.82535 4.82535 0.34 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65128 30 32 316 264 1 165 96 17 17 289 -1 unnamed_device 24.0 MiB 2.11 882 12798 3427 7781 1590 63.6 MiB 0.12 0.00 3.60295 -105.856 -3.60295 3.60295 0.33 0.000644126 0.000598529 0.0398531 0.0369682 -1 -1 -1 -1 30 1919 24 6.87369e+06 475111 556674. 1926.21 0.60 0.11996 0.10565 25186 138497 -1 1665 19 1031 1845 92885 24170 2.80666 2.80666 -100.682 -2.80666 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0237563 0.0206309 119 52 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_095.v common 3.39 vpr 63.20 MiB -1 -1 0.12 18080 1 0.03 -1 -1 30460 -1 -1 24 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64720 27 32 255 219 1 139 83 17 17 289 -1 unnamed_device 23.6 MiB 0.98 659 7643 1786 5184 673 63.2 MiB 0.07 0.00 3.59463 -97.3218 -3.59463 3.59463 0.34 0.000551197 0.000513497 0.0250754 0.0233186 -1 -1 -1 -1 30 1508 21 6.87369e+06 335372 556674. 1926.21 0.53 0.0893672 0.0779488 25186 138497 -1 1307 22 912 1404 85222 19958 2.71066 2.71066 -92.8097 -2.71066 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0229535 0.0198213 97 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 5.57 vpr 63.50 MiB -1 -1 0.26 18408 1 0.03 -1 -1 30300 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65020 32 32 421 327 1 233 90 17 17 289 -1 unnamed_device 24.5 MiB 2.67 1401 16170 4964 9023 2183 63.5 MiB 0.19 0.00 4.57338 -144.339 -4.57338 4.57338 0.34 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64592 32 32 326 263 1 176 97 17 17 289 -1 unnamed_device 23.9 MiB 1.26 996 18079 6285 9338 2456 63.1 MiB 0.17 0.00 5.05545 -135.157 -5.05545 5.05545 0.34 0.0006787 0.00062261 0.0569607 0.0526736 -1 -1 -1 -1 28 2735 32 6.87369e+06 461137 531479. 1839.03 0.90 0.150988 0.132992 24610 126494 -1 2184 23 1538 2474 186286 44655 3.7844 3.7844 -127.117 -3.7844 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0289064 0.0250237 129 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_100.v common 4.36 vpr 63.26 MiB -1 -1 0.27 18324 1 0.03 -1 -1 30424 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64776 31 32 373 294 1 197 97 17 17 289 -1 unnamed_device 24.2 MiB 1.61 975 8977 1882 6473 622 63.3 MiB 0.10 0.00 4.47518 -127.7 -4.47518 4.47518 0.34 0.000735349 0.000682437 0.0320028 0.0296931 -1 -1 -1 -1 30 2526 22 6.87369e+06 475111 556674. 1926.21 0.65 0.121632 0.106372 25186 138497 -1 1772 20 1161 1988 89442 23941 3.59926 3.59926 -123.864 -3.59926 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0287372 0.0250502 149 50 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_101.v common 4.69 vpr 63.14 MiB -1 -1 0.25 18476 1 0.03 -1 -1 30092 -1 -1 31 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 30 32 325 268 1 172 93 17 17 289 -1 unnamed_device 24.0 MiB 1.89 1016 17523 5783 9680 2060 63.1 MiB 0.16 0.00 3.6935 -107.395 -3.6935 3.6935 0.33 0.000656932 0.000610154 0.0564618 0.0524435 -1 -1 -1 -1 32 2389 47 6.87369e+06 433189 586450. 2029.24 0.66 0.157482 0.138428 25474 144626 -1 2002 22 1287 2224 135136 33535 3.14781 3.14781 -106.636 -3.14781 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0272988 0.0236707 124 51 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_102.v common 6.12 vpr 63.13 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30228 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 24.1 MiB 3.33 1248 13738 4274 7446 2018 63.1 MiB 0.15 0.00 4.85883 -154.737 -4.85883 4.85883 0.33 0.000713451 0.000654801 0.0520909 0.0481021 -1 -1 -1 -1 32 3121 22 6.87369e+06 335372 586450. 2029.24 0.63 0.136198 0.12007 25474 144626 -1 2484 20 1815 2844 200706 47665 4.17706 4.17706 -148.515 -4.17706 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0274458 0.0239019 143 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 5.85 vpr 63.91 MiB -1 -1 0.25 18376 1 0.03 -1 -1 30128 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65444 32 32 386 307 1 196 100 17 17 289 -1 unnamed_device 24.3 MiB 3.01 1086 10308 2517 7280 511 63.9 MiB 0.12 0.00 4.14663 -136.709 -4.14663 4.14663 0.34 0.000747845 0.000694676 0.0358158 0.0332704 -1 -1 -1 -1 28 2852 22 6.87369e+06 503058 531479. 1839.03 0.74 0.128014 0.1121 24610 126494 -1 2345 20 1518 2459 158677 39350 3.26061 3.26061 -128.829 -3.26061 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0293717 0.0255279 148 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 4.20 vpr 63.19 MiB -1 -1 0.22 18280 1 0.03 -1 -1 30284 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 29 32 269 229 1 150 81 17 17 289 -1 unnamed_device 23.5 MiB 1.73 676 13381 4841 5719 2821 63.2 MiB 0.12 0.00 3.95844 -115.993 -3.95844 3.95844 0.33 0.000576391 0.00053603 0.0458306 0.0426133 -1 -1 -1 -1 32 1602 21 6.87369e+06 279477 586450. 2029.24 0.54 0.11245 0.0993597 25474 144626 -1 1303 20 1078 1620 101124 24300 3.02726 3.02726 -105.477 -3.02726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226321 0.0196502 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 4.33 vpr 63.11 MiB -1 -1 0.24 18380 1 0.03 -1 -1 30284 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 32 32 310 266 1 175 84 17 17 289 -1 unnamed_device 24.0 MiB 1.51 1025 15456 4644 9539 1273 63.1 MiB 0.15 0.00 3.98516 -120.978 -3.98516 3.98516 0.33 0.000629119 0.000584837 0.0550716 0.051179 -1 -1 -1 -1 26 2517 27 6.87369e+06 279477 503264. 1741.40 0.77 0.135191 0.119354 24322 120374 -1 2108 22 1426 1967 170507 40619 3.43941 3.43941 -126.369 -3.43941 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0266223 0.0230652 108 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 4.68 vpr 63.76 MiB -1 -1 0.15 18476 1 0.03 -1 -1 30344 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65292 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 24.0 MiB 1.43 987 18428 5110 10243 3075 63.8 MiB 0.17 0.00 4.59612 -128.416 -4.59612 4.59612 0.33 0.00066769 0.000620041 0.0537939 0.049922 -1 -1 -1 -1 26 2846 38 6.87369e+06 544980 503264. 1741.40 1.16 0.153274 0.135079 24322 120374 -1 2300 23 1587 2983 214840 50593 4.066 4.066 -137.302 -4.066 0 0 618332. 2139.56 0.02 0.05 0.07 -1 -1 0.02 0.0152959 0.0134031 135 33 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 4.72 vpr 63.51 MiB -1 -1 0.22 18056 1 0.03 -1 -1 30240 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65032 29 32 262 224 1 168 81 17 17 289 -1 unnamed_device 23.9 MiB 2.21 926 13031 3833 7297 1901 63.5 MiB 0.12 0.00 4.39772 -121.351 -4.39772 4.39772 0.34 0.000564946 0.000526026 0.0438255 0.0407939 -1 -1 -1 -1 26 2366 26 6.87369e+06 279477 503264. 1741.40 0.58 0.115317 0.101479 24322 120374 -1 1950 21 1326 1745 124283 31179 3.5018 3.5018 -119.379 -3.5018 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0230083 0.0198986 103 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 6.22 vpr 63.16 MiB -1 -1 0.23 18184 1 0.03 -1 -1 30060 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 32 32 278 238 1 158 81 17 17 289 -1 unnamed_device 23.5 MiB 3.10 830 13556 5623 7156 777 63.2 MiB 0.12 0.00 3.89598 -121.823 -3.89598 3.89598 0.34 0.000599774 0.000558122 0.0486182 0.0452549 -1 -1 -1 -1 30 2401 40 6.87369e+06 237555 556674. 1926.21 1.16 0.151662 0.13314 25186 138497 -1 1517 22 1110 1832 122846 32031 2.91031 2.91031 -105.79 -2.91031 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0248086 0.0215212 102 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 5.22 vpr 63.86 MiB -1 -1 0.26 18380 1 0.03 -1 -1 30372 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65392 31 32 373 300 1 185 101 17 17 289 -1 unnamed_device 24.3 MiB 2.52 996 8326 1655 6069 602 63.9 MiB 0.09 0.00 3.95528 -124.82 -3.95528 3.95528 0.33 0.00073019 0.000672729 0.028011 0.0259846 -1 -1 -1 -1 30 2187 19 6.87369e+06 531006 556674. 1926.21 0.58 0.110267 0.0962367 25186 138497 -1 1812 19 1272 2135 103364 26073 2.96596 2.96596 -116.595 -2.96596 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0270136 0.0235073 142 64 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 4.45 vpr 63.19 MiB -1 -1 0.23 18184 1 0.03 -1 -1 30328 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 31 32 265 230 1 169 81 17 17 289 -1 unnamed_device 23.5 MiB 1.98 964 7606 1989 5205 412 63.2 MiB 0.08 0.00 3.71466 -116.831 -3.71466 3.71466 0.33 0.00058092 0.000541652 0.026736 0.0248919 -1 -1 -1 -1 30 2104 20 6.87369e+06 251529 556674. 1926.21 0.54 0.0928595 0.0811791 25186 138497 -1 1736 21 950 1365 79050 19847 3.06461 3.06461 -112.199 -3.06461 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0278341 0.0244082 101 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 5.45 vpr 63.81 MiB -1 -1 0.25 18348 1 0.03 -1 -1 29996 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65340 32 32 349 286 1 177 96 17 17 289 -1 unnamed_device 24.1 MiB 2.52 1048 13455 3508 9157 790 63.8 MiB 0.13 0.00 3.8199 -117.926 -3.8199 3.8199 0.34 0.000698483 0.000649166 0.0451115 0.0418957 -1 -1 -1 -1 26 2805 33 6.87369e+06 447163 503264. 1741.40 0.91 0.145167 0.127573 24322 120374 -1 2183 29 1347 2248 170016 40039 3.04151 3.04151 -116.867 -3.04151 0 0 618332. 2139.56 0.03 0.09 0.10 -1 -1 0.03 0.0361119 0.0312691 130 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 5.38 vpr 63.44 MiB -1 -1 0.15 18316 1 0.04 -1 -1 30280 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64960 31 32 396 325 1 185 96 17 17 289 -1 unnamed_device 24.4 MiB 2.88 1015 16959 5374 8849 2736 63.4 MiB 0.17 0.00 3.7606 -128.355 -3.7606 3.7606 0.33 0.000748216 0.000694083 0.0605097 0.0561856 -1 -1 -1 -1 32 2262 24 6.87369e+06 461137 586450. 2029.24 0.59 0.150753 0.133203 25474 144626 -1 1821 20 1416 2136 127559 31716 2.80391 2.80391 -117.048 -2.80391 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0156045 0.0137633 138 91 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 4.70 vpr 63.33 MiB -1 -1 0.24 18292 1 0.03 -1 -1 30324 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 303 262 1 154 81 17 17 289 -1 unnamed_device 24.0 MiB 2.09 926 11806 3071 7035 1700 63.3 MiB 0.11 0.00 3.46595 -111.033 -3.46595 3.46595 0.34 0.000626318 0.000581564 0.0441167 0.0410371 -1 -1 -1 -1 32 1999 19 6.87369e+06 237555 586450. 2029.24 0.56 0.115252 0.101659 25474 144626 -1 1755 16 874 1380 84592 21150 2.99146 2.99146 -110.25 -2.99146 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0205676 0.0179449 99 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 4.69 vpr 63.04 MiB -1 -1 0.23 18180 1 0.03 -1 -1 30264 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 24.0 MiB 1.70 868 9623 2653 6092 878 63.0 MiB 0.10 0.00 4.12463 -125.158 -4.12463 4.12463 0.29 0.000611296 0.000568942 0.0346504 0.0322298 -1 -1 -1 -1 28 2577 24 6.87369e+06 265503 531479. 1839.03 0.64 0.108794 0.0953846 24610 126494 -1 2089 21 1614 2365 175909 43157 3.21861 3.21861 -122.623 -3.21861 0 0 648988. 2245.63 0.03 0.08 0.07 -1 -1 0.03 0.0247676 0.021436 110 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 4.68 vpr 63.23 MiB -1 -1 0.12 18288 1 0.03 -1 -1 30172 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 32 32 318 257 1 196 86 17 17 289 -1 unnamed_device 24.1 MiB 2.03 1052 5567 1101 4155 311 63.2 MiB 0.07 0.00 4.84388 -137.106 -4.84388 4.84388 0.33 0.000657365 0.000611273 0.0214686 0.0199696 -1 -1 -1 -1 26 2782 21 6.87369e+06 307425 503264. 1741.40 0.77 0.101909 0.0887736 24322 120374 -1 2258 23 1745 2467 162233 39815 4.05606 4.05606 -137.797 -4.05606 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0293776 0.0254551 128 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 5.13 vpr 63.11 MiB -1 -1 0.25 18372 1 0.03 -1 -1 30196 -1 -1 29 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 24.0 MiB 2.37 1060 14562 4184 8868 1510 63.1 MiB 0.14 0.00 4.11363 -115.792 -4.11363 4.11363 0.34 0.000654586 0.000608681 0.0494721 0.0459961 -1 -1 -1 -1 30 2285 32 6.87369e+06 405241 556674. 1926.21 0.70 0.138159 0.121704 25186 138497 -1 1890 18 982 1734 104165 24665 3.11651 3.11651 -108.645 -3.11651 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.023576 0.0205441 123 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 6.17 vpr 64.10 MiB -1 -1 0.26 18404 1 0.03 -1 -1 30556 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65640 32 32 393 312 1 215 88 17 17 289 -1 unnamed_device 24.4 MiB 2.82 1203 9838 2479 6641 718 64.1 MiB 0.07 0.00 5.21116 -164.931 -5.21116 5.21116 0.32 0.000342348 0.000315851 0.0195076 0.017971 -1 -1 -1 -1 26 3413 41 6.87369e+06 335372 503264. 1741.40 1.24 0.136273 0.117963 24322 120374 -1 2693 21 2122 3152 243393 57965 4.48486 4.48486 -163.249 -4.48486 0 0 618332. 2139.56 0.03 0.10 0.10 -1 -1 0.03 0.0332255 0.0289183 148 65 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 3.52 vpr 63.05 MiB -1 -1 0.13 17992 1 0.03 -1 -1 30080 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64568 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 23.5 MiB 1.06 844 13556 4454 6953 2149 63.1 MiB 0.11 0.00 3.44201 -103.957 -3.44201 3.44201 0.33 0.000529031 0.000492592 0.0429559 0.0399555 -1 -1 -1 -1 32 1714 22 6.87369e+06 251529 586450. 2029.24 0.52 0.105722 0.0934036 25474 144626 -1 1496 19 749 1215 76767 19027 2.80296 2.80296 -100.579 -2.80296 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0199165 0.0172949 93 4 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 4.64 vpr 64.04 MiB -1 -1 0.26 18464 1 0.03 -1 -1 30180 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65572 32 32 412 334 1 194 99 17 17 289 -1 unnamed_device 24.3 MiB 1.86 1127 14007 4056 9039 912 64.0 MiB 0.15 0.00 4.44135 -147.306 -4.44135 4.44135 0.33 0.000765121 0.0007102 0.0495822 0.0459695 -1 -1 -1 -1 32 2681 24 6.87369e+06 489084 586450. 2029.24 0.63 0.142967 0.125789 25474 144626 -1 2165 21 1488 2138 146818 34899 3.61706 3.61706 -138.505 -3.61706 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0315295 0.0274102 145 90 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 6.55 vpr 63.58 MiB -1 -1 0.24 18480 1 0.03 -1 -1 30084 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65104 32 32 376 318 1 168 82 17 17 289 -1 unnamed_device 24.3 MiB 3.93 818 7914 1986 4991 937 63.6 MiB 0.09 0.00 3.65241 -126.689 -3.65241 3.65241 0.33 0.000716521 0.000665697 0.0339799 0.0315396 -1 -1 -1 -1 32 2064 21 6.87369e+06 251529 586450. 2029.24 0.59 0.116999 0.102344 25474 144626 -1 1733 19 1279 1863 114597 28329 3.23576 3.23576 -126.641 -3.23576 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0262627 0.022804 114 96 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 6.17 vpr 63.64 MiB -1 -1 0.25 18384 1 0.03 -1 -1 30248 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 32 32 360 293 1 182 97 17 17 289 -1 unnamed_device 23.9 MiB 2.69 898 12973 3607 6302 3064 63.6 MiB 0.12 0.00 4.14663 -123.081 -4.14663 4.14663 0.34 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 30 32 286 239 1 151 82 17 17 289 -1 unnamed_device 23.7 MiB 1.04 731 7380 1917 5120 343 63.3 MiB 0.08 0.00 3.87678 -118.42 -3.87678 3.87678 0.33 0.000600531 0.000558766 0.026782 0.0248795 -1 -1 -1 -1 32 1689 23 6.87369e+06 279477 586450. 2029.24 0.55 0.0992538 0.0866565 25474 144626 -1 1447 20 1008 1567 100138 24264 2.91726 2.91726 -109.833 -2.91726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.023328 0.0202272 106 34 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 3.96 vpr 63.45 MiB -1 -1 0.23 18024 1 0.03 -1 -1 30136 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 32 32 354 285 1 223 90 17 17 289 -1 unnamed_device 23.9 MiB 1.53 1144 16773 5687 8252 2834 63.1 MiB 0.17 0.00 5.45687 -159.577 -5.45687 5.45687 0.34 0.000707441 0.000653701 0.061291 0.0568531 -1 -1 -1 -1 34 2960 24 6.89349e+06 366440 618332. 2139.56 1.09 0.207628 0.181784 25762 151098 -1 2314 21 1560 2311 158787 38584 4.32749 4.32749 -146.434 -4.32749 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0285389 0.0248246 147 50 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_002.v common 4.15 vpr 63.02 MiB -1 -1 0.15 18292 1 0.03 -1 -1 30292 -1 -1 27 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64528 30 32 363 293 1 229 89 17 17 289 -1 unnamed_device 23.8 MiB 1.45 1225 15929 4471 9301 2157 63.0 MiB 0.17 0.00 4.93328 -152.269 -4.93328 4.93328 0.33 0.00070826 0.000658533 0.059288 0.0551026 -1 -1 -1 -1 32 2735 20 6.89349e+06 380534 586450. 2029.24 0.63 0.140514 0.124521 25474 144626 -1 2348 22 1808 2627 169139 39727 4.37429 4.37429 -148.001 -4.37429 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0294465 0.0255588 152 63 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_003.v common 3.95 vpr 63.16 MiB -1 -1 0.15 18440 1 0.03 -1 -1 30276 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64680 32 32 299 247 1 190 86 17 17 289 -1 unnamed_device 23.8 MiB 1.46 1082 9347 2400 6379 568 63.2 MiB 0.11 0.00 4.40779 -123.677 -4.40779 4.40779 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/home/elgamma8/research/release/vtr-verilog-to-routing 64608 27 32 259 221 1 159 82 17 17 289 -1 unnamed_device 23.4 MiB 1.06 879 11118 3409 5655 2054 63.1 MiB 0.10 0.00 4.18543 -114.454 -4.18543 4.18543 0.33 0.000554655 0.000516362 0.0367097 0.0341929 -1 -1 -1 -1 32 1862 23 6.89349e+06 324158 586450. 2029.24 0.56 0.103219 0.0906636 25474 144626 -1 1552 19 1103 1617 122140 28845 3.05681 3.05681 -101.377 -3.05681 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.020955 0.0181463 104 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 3.23 vpr 63.25 MiB -1 -1 0.24 17896 1 0.03 -1 -1 30072 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64768 31 32 271 219 1 164 96 17 17 289 -1 unnamed_device 23.7 MiB 0.69 1005 15426 4709 8488 2229 63.2 MiB 0.13 0.00 3.4228 -103.716 -3.4228 3.4228 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/home/elgamma8/research/release/vtr-verilog-to-routing 64692 32 32 276 237 1 171 82 17 17 289 -1 unnamed_device 23.6 MiB 1.10 901 12008 3961 5948 2099 63.2 MiB 0.06 0.00 3.74726 -113.02 -3.74726 3.74726 0.25 0.00026857 0.000246966 0.0193216 0.0178049 -1 -1 -1 -1 32 2217 28 6.89349e+06 253689 586450. 2029.24 0.42 0.0559151 0.0489354 25474 144626 -1 1652 16 887 1232 89434 21858 2.94461 2.94461 -102.907 -2.94461 0 0 744469. 2576.02 0.03 0.05 0.13 -1 -1 0.03 0.0193158 0.016865 103 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_013.v common 4.97 vpr 63.11 MiB -1 -1 0.25 18540 1 0.03 -1 -1 30284 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 344 272 1 209 89 17 17 289 -1 unnamed_device 23.9 MiB 1.57 1074 17909 6040 8736 3133 63.1 MiB 0.19 0.00 4.12632 -131.306 -4.12632 4.12632 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27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 370 297 1 234 91 17 17 289 -1 unnamed_device 24.0 MiB 2.18 1431 13351 3686 8381 1284 63.2 MiB 0.16 0.00 4.1691 -138.277 -4.1691 4.1691 0.34 0.000725196 0.000673597 0.0499479 0.0463746 -1 -1 -1 -1 32 3294 30 6.89349e+06 380534 586450. 2029.24 0.77 0.151269 0.133213 25474 144626 -1 2734 21 1994 3084 228982 52255 3.74455 3.74455 -136.57 -3.74455 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0292561 0.0254045 157 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_017.v common 4.44 vpr 63.09 MiB -1 -1 0.15 18504 1 0.03 -1 -1 30092 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64604 32 32 338 269 1 205 89 17 17 289 -1 unnamed_device 23.9 MiB 1.60 1160 9593 2673 5745 1175 63.1 MiB 0.11 0.00 4.11158 -133.367 -4.11158 4.11158 0.33 0.000685651 0.000637337 0.0352935 0.0328014 -1 -1 -1 -1 34 2547 20 6.89349e+06 352346 618332. 2139.56 0.97 0.173434 0.15089 25762 151098 -1 2202 19 1226 1793 150582 33445 2.96516 2.96516 -117.404 -2.96516 0 0 787024. 2723.27 0.03 0.04 0.09 -1 -1 0.03 0.0144492 0.0127946 138 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 5.42 vpr 62.96 MiB -1 -1 0.14 18316 1 0.03 -1 -1 30408 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 32 32 323 276 1 215 88 17 17 289 -1 unnamed_device 23.8 MiB 1.51 1219 7888 1702 5732 454 63.0 MiB 0.10 0.00 3.59345 -126.377 -3.59345 3.59345 0.34 0.000652743 0.000606899 0.0293208 0.0272933 -1 -1 -1 -1 30 2682 34 6.89349e+06 338252 556674. 1926.21 1.97 0.239653 0.205887 25186 138497 -1 2052 17 1244 1673 101028 24727 2.79796 2.79796 -117.425 -2.79796 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0223332 0.0194694 128 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_019.v common 3.07 vpr 63.13 MiB -1 -1 0.20 18224 1 0.03 -1 -1 30144 -1 -1 16 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 30 32 222 206 1 141 78 17 17 289 -1 unnamed_device 23.7 MiB 0.69 830 12694 4493 6588 1613 63.1 MiB 0.10 0.00 2.70263 -92.4151 -2.70263 2.70263 0.33 0.000497119 0.000462474 0.0395541 0.0367909 -1 -1 -1 -1 26 1667 21 6.89349e+06 225501 503264. 1741.40 0.57 0.098353 0.0869129 24322 120374 -1 1469 15 644 725 56762 13692 2.10807 2.10807 -91.092 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35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 32 32 342 271 1 207 99 17 17 289 -1 unnamed_device 23.9 MiB 1.31 1197 19479 5549 11862 2068 63.1 MiB 0.19 0.00 4.72649 -149.912 -4.72649 4.72649 0.37 0.000706398 0.000656772 0.0619063 0.0575159 -1 -1 -1 -1 34 2608 22 6.89349e+06 493284 618332. 2139.56 1.01 0.197307 0.172912 25762 151098 -1 2194 20 1354 2047 139470 34278 4.03544 4.03544 -144.363 -4.03544 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0275815 0.0240026 150 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_022.v common 4.77 vpr 63.10 MiB -1 -1 0.25 18376 1 0.03 -1 -1 30376 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 32 32 372 300 1 229 89 17 17 289 -1 unnamed_device 23.9 MiB 1.25 1325 9791 2524 6598 669 63.1 MiB 0.13 0.00 4.60648 -139.803 -4.60648 4.60648 0.33 0.000731497 0.000680237 0.0409879 0.0380157 -1 -1 -1 -1 26 3361 41 6.89349e+06 352346 503264. 1741.40 1.33 0.161648 0.141511 24322 120374 -1 2926 25 2536 3825 316091 89851 3.9097 3.9097 -143.697 -3.9097 0 0 618332. 2139.56 0.03 0.12 0.10 -1 -1 0.03 0.0337451 0.0292678 154 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_023.v common 3.15 vpr 63.02 MiB -1 -1 0.21 18180 1 0.02 -1 -1 30560 -1 -1 19 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 26 32 190 182 1 126 77 17 17 289 -1 unnamed_device 23.6 MiB 0.72 539 10346 4260 5337 749 63.0 MiB 0.07 0.00 2.69961 -73.3828 -2.69961 2.69961 0.34 0.000428627 0.000398029 0.0284074 0.0263245 -1 -1 -1 -1 28 1430 47 6.89349e+06 267783 531479. 1839.03 0.60 0.100975 0.0884533 24610 126494 -1 1019 14 577 682 43677 12108 2.11835 2.11835 -70.8739 -2.11835 0 0 648988. 2245.63 0.02 0.02 0.07 -1 -1 0.02 0.0077792 0.00694829 72 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_024.v common 4.58 vpr 63.12 MiB -1 -1 0.23 17996 1 0.03 -1 -1 30308 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 32 32 285 227 1 169 87 17 17 289 -1 unnamed_device 23.6 MiB 0.98 1063 11799 3182 7057 1560 63.1 MiB 0.12 0.00 4.60563 -130.083 -4.60563 4.60563 0.33 0.000618593 0.000574802 0.0400595 0.0372659 -1 -1 -1 -1 32 2381 24 6.89349e+06 324158 586450. 2029.24 1.59 0.232922 0.201157 25474 144626 -1 1999 22 1208 2278 146746 35126 3.61225 3.61225 -118.524 -3.61225 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0317339 0.0274249 119 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_025.v common 3.02 vpr 62.83 MiB -1 -1 0.21 17648 1 0.02 -1 -1 30064 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 23.6 MiB 0.50 458 9356 2990 4431 1935 62.8 MiB 0.06 0.00 2.39862 -72.6001 -2.39862 2.39862 0.33 0.000423472 0.000392915 0.0258794 0.024019 -1 -1 -1 -1 28 1318 45 6.89349e+06 169126 531479. 1839.03 0.63 0.0914474 0.079783 24610 126494 -1 1010 26 617 760 72909 29156 2.06796 2.06796 -77.4474 -2.06796 0 0 648988. 2245.63 0.03 0.06 0.10 -1 -1 0.03 0.0206634 0.0178415 65 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_026.v common 4.11 vpr 63.18 MiB -1 -1 0.24 18204 1 0.03 -1 -1 30152 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 32 32 300 245 1 187 86 17 17 289 -1 unnamed_device 23.8 MiB 1.33 1053 11993 3304 7573 1116 63.2 MiB 0.13 0.00 4.96363 -136.721 -4.96363 4.96363 0.33 0.000634294 0.000590454 0.0424028 0.0394305 -1 -1 -1 -1 26 2626 25 6.89349e+06 310065 503264. 1741.40 0.71 0.126284 0.111236 24322 120374 -1 2255 19 1275 1846 130434 31937 4.03626 4.03626 -132.507 -4.03626 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0237551 0.0206724 121 24 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 4.10 vpr 63.39 MiB -1 -1 0.13 17964 1 0.03 -1 -1 30384 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 23.7 MiB 0.72 1102 17591 5006 10257 2328 63.4 MiB 0.16 0.00 3.451 -111.885 -3.451 3.451 0.33 0.00063647 0.000592222 0.0539327 0.050037 -1 -1 -1 -1 28 2445 37 6.89349e+06 436909 531479. 1839.03 0.74 0.144368 0.127087 24610 126494 -1 2122 22 1263 2289 148196 36337 2.70081 2.70081 -107.98 -2.70081 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0265493 0.0230306 130 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 4.69 vpr 63.19 MiB -1 -1 0.22 18324 1 0.04 -1 -1 30232 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 338 277 1 215 89 17 17 289 -1 unnamed_device 24.0 MiB 1.53 1243 15731 5322 7942 2467 63.2 MiB 0.16 0.00 4.85308 -135.583 -4.85308 4.85308 0.34 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 28 32 260 223 1 163 85 17 17 289 -1 unnamed_device 23.6 MiB 1.23 910 14593 5077 7414 2102 63.1 MiB 0.13 0.00 4.29929 -120.332 -4.29929 4.29929 0.34 0.000557357 0.000518617 0.0461162 0.0428912 -1 -1 -1 -1 32 2100 20 6.89349e+06 352346 586450. 2029.24 0.56 0.111197 0.098241 25474 144626 -1 1696 21 895 1529 95985 22999 3.23235 3.23235 -110.54 -3.23235 0 0 744469. 2576.02 0.03 0.03 0.08 -1 -1 0.03 0.0122668 0.0107644 108 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 3.76 vpr 63.04 MiB -1 -1 0.23 17900 1 0.03 -1 -1 30224 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 253 210 1 156 82 17 17 289 -1 unnamed_device 23.5 MiB 1.06 749 9160 2232 6447 481 63.0 MiB 0.09 0.00 3.86328 -116.366 -3.86328 3.86328 0.33 0.000573773 0.000532341 0.031373 0.0291874 -1 -1 -1 -1 28 2273 28 6.89349e+06 253689 531479. 1839.03 0.68 0.104099 0.0910894 24610 126494 -1 1785 34 1750 3035 275769 99959 2.87716 2.87716 -113.369 -2.87716 0 0 648988. 2245.63 0.03 0.12 0.10 -1 -1 0.03 0.0338085 0.0290584 101 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 3.63 vpr 63.10 MiB -1 -1 0.24 18240 1 0.03 -1 -1 30132 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 31 32 271 231 1 172 84 17 17 289 -1 unnamed_device 23.5 MiB 1.03 896 7770 1848 5501 421 63.1 MiB 0.09 0.00 3.62655 -110.965 -3.62655 3.62655 0.33 0.000583477 0.000543265 0.0267762 0.0249136 -1 -1 -1 -1 26 2417 31 6.89349e+06 295971 503264. 1741.40 0.65 0.104233 0.0908852 24322 120374 -1 1997 26 1435 2066 169243 52516 2.81636 2.81636 -107.029 -2.81636 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0282252 0.024338 105 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 4.52 vpr 63.24 MiB -1 -1 0.24 18424 1 0.03 -1 -1 30452 -1 -1 24 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 29 32 291 250 1 185 85 17 17 289 -1 unnamed_device 23.9 MiB 1.72 987 11989 3361 6675 1953 63.2 MiB 0.11 0.00 3.73533 -108.087 -3.73533 3.73533 0.34 0.000596376 0.000554792 0.0403117 0.0374762 -1 -1 -1 -1 26 2360 26 6.89349e+06 338252 503264. 1741.40 0.89 0.122772 0.107939 24322 120374 -1 2030 21 1210 1703 126678 30193 2.95146 2.95146 -109.609 -2.95146 0 0 618332. 2139.56 0.02 0.04 0.07 -1 -1 0.02 0.0132468 0.0116048 117 54 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_035.v common 5.23 vpr 63.10 MiB -1 -1 0.24 18260 1 0.03 -1 -1 30420 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 32 32 367 282 1 224 92 17 17 289 -1 unnamed_device 23.9 MiB 1.16 1265 10649 3041 6726 882 63.1 MiB 0.13 0.00 4.57545 -131.234 -4.57545 4.57545 0.33 0.000735448 0.000683785 0.0403333 0.0374629 -1 -1 -1 -1 28 3232 44 6.89349e+06 394628 531479. 1839.03 2.16 0.272148 0.23506 24610 126494 -1 2714 22 1537 2644 200999 47427 3.7547 3.7547 -129.761 -3.7547 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0172363 0.0151812 155 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_036.v common 4.75 vpr 63.11 MiB -1 -1 0.25 18380 1 0.03 -1 -1 30400 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64628 32 32 391 311 1 250 93 17 17 289 -1 unnamed_device 24.1 MiB 1.73 1433 15423 4226 9063 2134 63.1 MiB 0.18 0.00 4.56723 -154.163 -4.56723 4.56723 0.33 0.000759097 0.000705105 0.0586858 0.0546043 -1 -1 -1 -1 30 3141 34 6.89349e+06 408721 556674. 1926.21 0.84 0.164331 0.145039 25186 138497 -1 2546 22 2111 2906 187308 44776 3.63025 3.63025 -138.661 -3.63025 0 0 706193. 2443.58 0.03 0.09 0.11 -1 -1 0.03 0.0322373 0.0280504 162 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_037.v common 3.71 vpr 63.12 MiB -1 -1 0.24 18508 1 0.03 -1 -1 30236 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64632 31 32 279 237 1 166 81 17 17 289 -1 unnamed_device 23.6 MiB 1.01 863 12331 3145 7318 1868 63.1 MiB 0.12 0.00 4.00748 -119.789 -4.00748 4.00748 0.34 0.000603096 0.000561509 0.0437123 0.0406478 -1 -1 -1 -1 32 1949 21 6.89349e+06 253689 586450. 2029.24 0.58 0.11396 0.100554 25474 144626 -1 1645 19 873 1326 100623 24502 3.22455 3.22455 -109.63 -3.22455 0 0 744469. 2576.02 0.03 0.06 0.14 -1 -1 0.03 0.0229871 0.0200214 106 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 4.53 vpr 63.14 MiB -1 -1 0.28 18500 1 0.03 -1 -1 30392 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64656 31 32 370 297 1 235 91 17 17 289 -1 unnamed_device 24.2 MiB 1.85 1334 16615 5524 9183 1908 63.1 MiB 0.18 0.00 4.35803 -138.286 -4.35803 4.35803 0.33 0.000727677 0.000676594 0.0611783 0.0568038 -1 -1 -1 -1 32 3139 23 6.89349e+06 394628 586450. 2029.24 0.64 0.148113 0.131113 25474 144626 -1 2593 17 1393 2113 153401 34955 3.66925 3.66925 -132.64 -3.66925 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0137367 0.0121843 154 61 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 4.31 vpr 63.20 MiB -1 -1 0.26 18304 1 0.03 -1 -1 30332 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64720 31 32 377 302 1 241 91 17 17 289 -1 unnamed_device 24.1 MiB 1.60 1343 10699 2924 7083 692 63.2 MiB 0.07 0.00 5.62498 -166.87 -5.62498 5.62498 0.26 0.000327803 0.000302305 0.0189607 0.0174255 -1 -1 -1 -1 34 3178 21 6.89349e+06 394628 618332. 2139.56 0.88 0.100962 0.0873837 25762 151098 -1 2774 21 2014 3034 249717 56521 4.87549 4.87549 -160.742 -4.87549 0 0 787024. 2723.27 0.03 0.09 0.12 -1 -1 0.03 0.0301309 0.0261619 159 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_040.v common 4.99 vpr 63.14 MiB -1 -1 0.26 18304 1 0.03 -1 -1 30548 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 31 32 383 305 1 240 93 17 17 289 -1 unnamed_device 24.1 MiB 2.16 1180 16893 5958 8269 2666 63.1 MiB 0.18 0.00 5.57018 -172.63 -5.57018 5.57018 0.33 0.000739064 0.000686488 0.0616354 0.0572376 -1 -1 -1 -1 32 2992 25 6.89349e+06 422815 586450. 2029.24 0.67 0.153088 0.135511 25474 144626 -1 2271 22 1773 2638 157146 39758 4.86068 4.86068 -161.708 -4.86068 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0314788 0.0273736 163 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_041.v common 4.16 vpr 63.20 MiB -1 -1 0.26 18440 1 0.03 -1 -1 30376 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64720 31 32 352 285 1 223 90 17 17 289 -1 unnamed_device 24.0 MiB 1.25 1293 12150 3370 7532 1248 63.2 MiB 0.14 0.00 4.06478 -128.581 -4.06478 4.06478 0.34 0.000699316 0.000650208 0.0445193 0.0413753 -1 -1 -1 -1 30 2866 44 6.89349e+06 380534 556674. 1926.21 0.76 0.154584 0.135395 25186 138497 -1 2238 19 1372 2024 123195 28998 2.85031 2.85031 -111.874 -2.85031 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.026008 0.0226341 146 55 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_042.v common 3.87 vpr 63.28 MiB -1 -1 0.15 18076 1 0.03 -1 -1 30476 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 32 32 291 242 1 188 86 17 17 289 -1 unnamed_device 23.7 MiB 1.37 1096 9347 2440 6352 555 63.3 MiB 0.10 0.00 4.52484 -122.151 -4.52484 4.52484 0.34 0.000629764 0.000586024 0.0325575 0.0302635 -1 -1 -1 -1 26 2789 28 6.89349e+06 310065 503264. 1741.40 0.59 0.119867 0.104736 24322 120374 -1 2323 23 1271 1766 129816 31818 4.20376 4.20376 -129.093 -4.20376 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0269782 0.0233675 114 27 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_043.v common 5.49 vpr 63.48 MiB -1 -1 0.28 18520 1 0.03 -1 -1 30440 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 457 356 1 296 99 17 17 289 -1 unnamed_device 24.4 MiB 2.27 1650 16971 5334 10464 1173 63.5 MiB 0.21 0.00 5.33145 -171.907 -5.33145 5.33145 0.33 0.000866659 0.000806268 0.0674064 0.0626669 -1 -1 -1 -1 30 4216 33 6.89349e+06 493284 556674. 1926.21 0.96 0.188556 0.166125 25186 138497 -1 3338 24 2618 3983 274830 62997 4.22004 4.22004 -160.102 -4.22004 0 0 706193. 2443.58 0.03 0.11 0.11 -1 -1 0.03 0.038707 0.0334571 198 87 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_044.v common 3.45 vpr 63.15 MiB -1 -1 0.22 18152 1 0.03 -1 -1 30152 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64668 31 32 261 225 1 171 82 17 17 289 -1 unnamed_device 23.6 MiB 0.92 942 13966 3994 8618 1354 63.2 MiB 0.13 0.00 3.7719 -110.938 -3.7719 3.7719 0.34 0.00056775 0.000527039 0.0461714 0.0428804 -1 -1 -1 -1 32 2071 21 6.89349e+06 267783 586450. 2029.24 0.55 0.112744 0.0995375 25474 144626 -1 1805 18 1021 1430 85739 21011 2.97291 2.97291 -107.69 -2.97291 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0206187 0.0179139 101 28 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_045.v common 4.28 vpr 63.04 MiB -1 -1 0.25 18404 1 0.03 -1 -1 30324 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64556 31 32 337 267 1 207 88 17 17 289 -1 unnamed_device 23.9 MiB 1.40 1128 5158 1029 3935 194 63.0 MiB 0.07 0.00 4.79572 -142.454 -4.79572 4.79572 0.33 0.000682908 0.000635379 0.020152 0.018729 -1 -1 -1 -1 30 3093 24 6.89349e+06 352346 556674. 1926.21 0.79 0.10569 0.0919385 25186 138497 -1 2432 21 1436 2183 149532 35823 3.8035 3.8035 -133.873 -3.8035 0 0 706193. 2443.58 0.03 0.10 0.11 -1 -1 0.03 0.0356862 0.030933 139 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_046.v common 4.46 vpr 62.96 MiB -1 -1 0.24 18576 1 0.03 -1 -1 30268 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 349 284 1 222 90 17 17 289 -1 unnamed_device 23.8 MiB 1.47 1260 16572 5549 8089 2934 63.0 MiB 0.18 0.00 4.31681 -131.797 -4.31681 4.31681 0.33 0.000692411 0.000641627 0.0595607 0.0553191 -1 -1 -1 -1 30 3482 26 6.89349e+06 366440 556674. 1926.21 0.88 0.149362 0.132119 25186 138497 -1 2487 19 1298 2160 137638 32282 3.5623 3.5623 -128.005 -3.5623 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0258789 0.0225371 144 53 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_047.v common 3.55 vpr 63.14 MiB -1 -1 0.22 17968 1 0.03 -1 -1 30124 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64660 32 32 291 230 1 175 91 17 17 289 -1 unnamed_device 23.5 MiB 0.86 1024 12535 4004 6635 1896 63.1 MiB 0.12 0.00 4.24939 -127.739 -4.24939 4.24939 0.34 0.000626882 0.000582042 0.0404428 0.0375685 -1 -1 -1 -1 30 2604 24 6.89349e+06 380534 556674. 1926.21 0.80 0.121426 0.106891 25186 138497 -1 2002 21 1172 2290 138411 33291 3.7797 3.7797 -124.432 -3.7797 0 0 706193. 2443.58 0.03 0.04 0.08 -1 -1 0.03 0.0133723 0.0117291 123 3 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 4.77 vpr 63.05 MiB -1 -1 0.28 18268 1 0.03 -1 -1 30436 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64568 32 32 353 287 1 220 90 17 17 289 -1 unnamed_device 23.9 MiB 1.62 1205 14160 4623 7104 2433 63.1 MiB 0.15 0.00 4.53365 -132.672 -4.53365 4.53365 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64464 32 32 340 270 1 204 89 17 17 289 -1 unnamed_device 23.8 MiB 0.94 1210 12365 3326 7764 1275 63.0 MiB 0.08 0.00 5.21531 -154.715 -5.21531 5.21531 0.26 0.000308828 0.000284704 0.0209834 0.0193316 -1 -1 -1 -1 30 2780 24 6.89349e+06 352346 556674. 1926.21 0.47 0.0641112 0.0562922 25186 138497 -1 2260 20 1189 2085 141591 32513 3.706 3.706 -133.226 -3.706 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0265655 0.0231263 137 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_082.v common 4.42 vpr 63.12 MiB -1 -1 0.25 18396 1 0.03 -1 -1 30196 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 31 32 340 275 1 211 90 17 17 289 -1 unnamed_device 23.9 MiB 1.73 1088 9336 2201 6577 558 63.1 MiB 0.11 0.00 5.04444 -145.956 -5.04444 5.04444 0.33 0.000682831 0.000634779 0.0339186 0.0315045 -1 -1 -1 -1 30 3021 26 6.89349e+06 380534 556674. 1926.21 0.72 0.119856 0.104908 25186 138497 -1 2171 23 1498 2362 145453 36505 4.09269 4.09269 -138.021 -4.09269 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0293748 0.0254617 142 47 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 4.58 vpr 63.17 MiB -1 -1 0.14 18380 1 0.03 -1 -1 30344 -1 -1 31 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 30 32 377 310 1 239 93 17 17 289 -1 unnamed_device 24.1 MiB 2.01 1323 12063 3354 7850 859 63.2 MiB 0.14 0.00 4.83716 -144.714 -4.83716 4.83716 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/home/elgamma8/research/release/vtr-verilog-to-routing 64480 32 32 356 289 1 224 90 17 17 289 -1 unnamed_device 23.8 MiB 1.71 1387 15768 4665 9408 1695 63.0 MiB 0.16 0.00 4.93824 -150.865 -4.93824 4.93824 0.33 0.000707307 0.00065752 0.0579457 0.0538599 -1 -1 -1 -1 32 2960 23 6.89349e+06 366440 586450. 2029.24 0.61 0.142278 0.12601 25474 144626 -1 2441 19 1502 2031 146713 34429 4.31335 4.31335 -145.674 -4.31335 0 0 744469. 2576.02 0.03 0.04 0.08 -1 -1 0.03 0.0149205 0.0132196 146 56 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_093.v common 3.84 vpr 62.96 MiB -1 -1 0.24 18176 1 0.03 -1 -1 30164 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64468 32 32 349 260 1 204 100 17 17 289 -1 unnamed_device 23.8 MiB 0.63 1297 14020 4001 8993 1026 63.0 MiB 0.16 0.00 5.06861 -145.864 -5.06861 5.06861 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30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 421 327 1 271 94 17 17 289 -1 unnamed_device 24.2 MiB 1.97 1509 10957 2826 6796 1335 63.3 MiB 0.14 0.00 4.63892 -149.381 -4.63892 4.63892 0.33 0.00080454 0.000748076 0.043944 0.0407989 -1 -1 -1 -1 28 4136 42 6.89349e+06 422815 531479. 1839.03 1.38 0.170393 0.149095 24610 126494 -1 3075 22 2130 3307 228365 66158 4.43289 4.43289 -149.976 -4.43289 0 0 648988. 2245.63 0.03 0.10 0.11 -1 -1 0.03 0.0340225 0.0295636 180 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_097.v common 4.62 vpr 63.55 MiB -1 -1 0.15 18416 1 0.03 -1 -1 30312 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65080 31 32 365 296 1 233 89 17 17 289 -1 unnamed_device 23.8 MiB 1.82 1244 11771 3259 7075 1437 63.6 MiB 0.13 0.00 5.7998 -165.192 -5.7998 5.7998 0.33 0.000716053 0.000665573 0.0448739 0.0416641 -1 -1 -1 -1 32 2788 40 6.89349e+06 366440 586450. 2029.24 0.77 0.149219 0.130667 25474 144626 -1 2412 21 1884 2692 188955 47019 4.67615 4.67615 -156.175 -4.67615 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0298131 0.0259191 151 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_098.v common 4.36 vpr 63.19 MiB -1 -1 0.24 18252 1 0.03 -1 -1 30300 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 32 32 331 280 1 221 87 17 17 289 -1 unnamed_device 24.0 MiB 1.50 1210 16215 5301 8723 2191 63.2 MiB 0.16 0.00 4.58923 -148.326 -4.58923 4.58923 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0 0 648988. 2245.63 0.02 0.04 0.07 -1 -1 0.02 0.013763 0.0121788 131 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_100.v common 4.05 vpr 63.06 MiB -1 -1 0.26 18404 1 0.03 -1 -1 30484 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 31 32 373 294 1 231 91 17 17 289 -1 unnamed_device 23.8 MiB 1.46 1232 10291 2595 7126 570 63.1 MiB 0.13 0.00 4.53972 -131.904 -4.53972 4.53972 0.33 0.000731723 0.000679966 0.0398017 0.0369928 -1 -1 -1 -1 30 2836 17 6.89349e+06 394628 556674. 1926.21 0.57 0.120718 0.106209 25186 138497 -1 2405 21 1646 2522 144904 35098 3.7514 3.7514 -127.877 -3.7514 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0296711 0.0258196 158 50 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_101.v common 4.41 vpr 63.09 MiB -1 -1 0.25 18444 1 0.03 -1 -1 30376 -1 -1 26 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 30 32 325 268 1 210 88 17 17 289 -1 unnamed_device 23.9 MiB 1.46 1228 15493 4762 8305 2426 63.1 MiB 0.16 0.00 4.32549 -122.97 -4.32549 4.32549 0.33 0.000656747 0.000610369 0.0543623 0.0505311 -1 -1 -1 -1 32 2960 24 6.89349e+06 366440 586450. 2029.24 0.62 0.134116 0.118568 25474 144626 -1 2431 20 1284 2055 142826 33487 3.4732 3.4732 -117.819 -3.4732 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.025544 0.0221956 135 51 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_102.v common 4.78 vpr 63.11 MiB -1 -1 0.23 18348 1 0.03 -1 -1 30356 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 350 275 1 215 88 17 17 289 -1 unnamed_device 23.9 MiB 1.99 1263 13738 4130 7532 2076 63.1 MiB 0.15 0.00 4.94548 -156.272 -4.94548 4.94548 0.34 0.000704088 0.000654957 0.0519574 0.0483078 -1 -1 -1 -1 30 3289 25 6.89349e+06 338252 556674. 1926.21 0.72 0.141395 0.124798 25186 138497 -1 2682 20 1660 2612 206101 48392 4.08826 4.08826 -148.158 -4.08826 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.027773 0.0241643 143 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_103.v common 4.90 vpr 63.29 MiB -1 -1 0.26 18364 1 0.03 -1 -1 29992 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 32 32 386 307 1 246 93 17 17 289 -1 unnamed_device 24.2 MiB 2.08 1385 10173 2853 6391 929 63.3 MiB 0.13 0.00 4.14004 -138.199 -4.14004 4.14004 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26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 31 32 326 261 1 204 89 17 17 289 -1 unnamed_device 23.9 MiB 1.17 1108 10583 2739 6769 1075 63.0 MiB 0.12 0.00 5.02183 -139.303 -5.02183 5.02183 0.33 0.000666098 0.000619577 0.0377341 0.0350695 -1 -1 -1 -1 36 2340 22 6.89349e+06 366440 648988. 2245.63 1.15 0.169204 0.14718 26050 158493 -1 2066 18 1163 1883 137081 32533 3.75856 3.75856 -127.625 -3.75856 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0242178 0.0211161 134 33 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_107.v common 4.07 vpr 63.09 MiB -1 -1 0.25 18156 1 0.03 -1 -1 30312 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64600 29 32 262 224 1 168 81 17 17 289 -1 unnamed_device 23.5 MiB 1.30 845 8306 2095 5417 794 63.1 MiB 0.09 0.00 4.25195 -113.857 -4.25195 4.25195 0.33 0.000574 0.000535503 0.0287148 0.0267542 -1 -1 -1 -1 28 2177 33 6.89349e+06 281877 531479. 1839.03 0.68 0.104971 0.0914314 24610 126494 -1 1920 28 1357 1777 186903 65337 3.169 3.169 -109.113 -3.169 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0289744 0.0249371 104 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_108.v common 4.81 vpr 63.11 MiB -1 -1 0.23 18156 1 0.03 -1 -1 30064 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64620 32 32 278 238 1 182 84 17 17 289 -1 unnamed_device 23.5 MiB 1.41 1019 13809 4194 7374 2241 63.1 MiB 0.13 0.00 4.20123 -130.77 -4.20123 4.20123 0.34 0.000595178 0.00055434 0.0468899 0.0436464 -1 -1 -1 -1 28 2671 42 6.89349e+06 281877 531479. 1839.03 0.95 0.140562 0.123393 24610 126494 -1 2173 24 1552 2167 196263 44101 3.30321 3.30321 -128.538 -3.30321 0 0 648988. 2245.63 0.03 0.08 0.11 -1 -1 0.03 0.0270876 0.0233899 109 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 4.58 vpr 63.64 MiB -1 -1 0.26 18424 1 0.03 -1 -1 30380 -1 -1 28 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 31 32 373 300 1 237 91 17 17 289 -1 unnamed_device 23.8 MiB 1.80 1293 14983 4153 9099 1731 63.6 MiB 0.17 0.00 4.61837 -148.41 -4.61837 4.61837 0.33 0.00072392 0.000673027 0.0559176 0.0519563 -1 -1 -1 -1 28 3195 26 6.89349e+06 394628 531479. 1839.03 0.65 0.14627 0.129198 24610 126494 -1 2553 20 1986 2698 186531 44431 3.81965 3.81965 -141.172 -3.81965 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0281923 0.0245186 155 64 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_110.v common 3.60 vpr 63.05 MiB -1 -1 0.23 18092 1 0.03 -1 -1 30472 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64568 31 32 265 230 1 175 82 17 17 289 -1 unnamed_device 23.5 MiB 1.02 883 8804 2413 5751 640 63.1 MiB 0.09 0.00 3.61555 -111.504 -3.61555 3.61555 0.33 0.00057191 0.000532928 0.0300125 0.0279299 -1 -1 -1 -1 30 2116 21 6.89349e+06 267783 556674. 1926.21 0.54 0.0967442 0.0847373 25186 138497 -1 1746 22 1000 1418 88147 21633 2.90311 2.90311 -110.877 -2.90311 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0237371 0.0205404 104 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_111.v common 4.24 vpr 63.06 MiB -1 -1 0.15 18416 1 0.03 -1 -1 30020 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 32 32 349 286 1 221 89 17 17 289 -1 unnamed_device 23.8 MiB 1.50 1245 11969 3140 7616 1213 63.1 MiB 0.13 0.00 4.39413 -130.035 -4.39413 4.39413 0.34 0.000697558 0.00064848 0.0442265 0.0410941 -1 -1 -1 -1 30 2800 29 6.89349e+06 352346 556674. 1926.21 0.70 0.136708 0.120083 25186 138497 -1 2259 17 1056 1557 104303 24463 3.1503 3.1503 -117.968 -3.1503 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0240403 0.021017 142 57 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_112.v common 5.19 vpr 63.09 MiB -1 -1 0.29 18380 1 0.03 -1 -1 30260 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 31 32 396 325 1 259 93 17 17 289 -1 unnamed_device 24.0 MiB 2.12 1311 17313 4833 10070 2410 63.1 MiB 0.19 0.00 4.94622 -159.495 -4.94622 4.94622 0.33 0.000741991 0.000685776 0.0638633 0.0592945 -1 -1 -1 -1 32 3396 38 6.89349e+06 422815 586450. 2029.24 0.81 0.172103 0.15195 25474 144626 -1 2671 23 1970 2785 193766 45890 4.04249 4.04249 -151.176 -4.04249 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0322965 0.0279992 166 91 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_113.v common 4.65 vpr 63.05 MiB -1 -1 0.25 18472 1 0.03 -1 -1 30280 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 32 32 303 262 1 200 85 17 17 289 -1 unnamed_device 23.9 MiB 1.42 1134 7153 1649 5156 348 63.0 MiB 0.09 0.00 3.69791 -119.314 -3.69791 3.69791 0.33 0.000617724 0.000574295 0.0263615 0.0244812 -1 -1 -1 -1 26 3014 50 6.89349e+06 295971 503264. 1741.40 0.74 0.12603 0.109223 24322 120374 -1 2497 19 1652 2257 182227 43841 3.70126 3.70126 -131.815 -3.70126 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0236811 0.0205417 121 57 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 3.82 vpr 63.18 MiB -1 -1 0.22 18576 1 0.03 -1 -1 30256 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64700 32 32 290 244 1 176 83 17 17 289 -1 unnamed_device 23.6 MiB 1.05 898 9983 2681 6247 1055 63.2 MiB 0.12 0.00 4.17923 -126.577 -4.17923 4.17923 0.38 0.000618611 0.000576399 0.0436637 0.0406308 -1 -1 -1 -1 32 2248 27 6.89349e+06 267783 586450. 2029.24 0.63 0.121099 0.106383 25474 144626 -1 1913 21 1176 1778 129091 30495 3.09046 3.09046 -115.484 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-1 28 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64516 29 32 324 268 1 207 89 17 17 289 -1 unnamed_device 23.9 MiB 1.34 1163 13949 4509 7225 2215 63.0 MiB 0.14 0.00 4.06068 -113.604 -4.06068 4.06068 0.36 0.000648988 0.000603481 0.0483598 0.0449987 -1 -1 -1 -1 32 2498 22 6.89349e+06 394628 586450. 2029.24 0.57 0.125864 0.111182 25474 144626 -1 2113 18 1091 1529 102409 24986 3.1726 3.1726 -107.969 -3.1726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0235466 0.0205043 136 55 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 5.04 vpr 63.17 MiB -1 -1 0.26 18540 1 0.03 -1 -1 30420 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64684 32 32 393 312 1 243 90 17 17 289 -1 unnamed_device 24.1 MiB 2.00 1197 8532 1944 6080 508 63.2 MiB 0.11 0.00 5.6615 -176.256 -5.6615 5.6615 0.33 0.000765182 0.000711071 0.034673 0.0322116 -1 -1 -1 -1 32 3572 28 6.89349e+06 366440 586450. 2029.24 0.87 0.132281 0.11584 25474 144626 -1 2640 22 1876 2860 206960 49868 4.38809 4.38809 -163.546 -4.38809 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0314949 0.0273942 161 65 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 3.73 vpr 63.07 MiB -1 -1 0.23 17908 1 0.03 -1 -1 30152 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 31 32 229 197 1 143 81 17 17 289 -1 unnamed_device 23.5 MiB 0.88 858 12156 3731 6704 1721 63.1 MiB 0.11 0.00 3.31865 -102.092 -3.31865 3.31865 0.33 0.000531063 0.000495106 0.0385232 0.0358846 -1 -1 -1 -1 30 1864 18 6.89349e+06 253689 556674. 1926.21 0.52 0.0984705 0.0870618 25186 138497 -1 1477 21 802 1292 78949 19537 2.35985 2.35985 -93.6869 -2.35985 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0215092 0.0186059 93 4 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 4.40 vpr 63.87 MiB -1 -1 0.25 18480 1 0.03 -1 -1 30404 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65400 32 32 412 334 1 269 94 17 17 289 -1 unnamed_device 24.2 MiB 1.70 1511 17773 5393 10213 2167 63.9 MiB 0.19 0.00 5.64972 -177.297 -5.64972 5.64972 0.33 0.000351025 0.000323302 0.0594056 0.0549061 -1 -1 -1 -1 32 3132 28 6.89349e+06 422815 586450. 2029.24 0.51 0.130668 0.115927 25474 144626 -1 2549 18 1654 2142 127890 31978 4.60024 4.60024 -163.543 -4.60024 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0277509 0.0242359 173 90 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 4.89 vpr 63.25 MiB -1 -1 0.15 18432 1 0.03 -1 -1 30176 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 32 32 376 318 1 259 92 17 17 289 -1 unnamed_device 24.2 MiB 1.84 1293 9614 2367 6489 758 63.2 MiB 0.12 0.00 4.89568 -164.328 -4.89568 4.89568 0.33 0.000704531 0.000653159 0.0352242 0.0326131 -1 -1 -1 -1 32 3167 23 6.89349e+06 394628 586450. 2029.24 0.73 0.122092 0.106854 25474 144626 -1 2517 22 2283 2786 179066 44397 4.21384 4.21384 -161.857 -4.21384 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0296871 0.0257565 155 96 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 4.27 vpr 63.02 MiB -1 -1 0.25 18248 1 0.03 -1 -1 30208 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 32 32 360 293 1 226 91 17 17 289 -1 unnamed_device 23.8 MiB 1.40 1307 13759 4403 8202 1154 63.0 MiB 0.17 0.00 4.10168 -130.557 -4.10168 4.10168 0.33 0.000711311 0.00066117 0.0570836 0.0530446 -1 -1 -1 -1 32 2791 48 6.89349e+06 380534 586450. 2029.24 0.71 0.169513 0.148957 25474 144626 -1 2228 17 1439 1975 125236 30124 2.97891 2.97891 -117.401 -2.97891 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0245511 0.0214454 147 60 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 5.73 vpr 63.15 MiB -1 -1 0.14 18740 1 0.03 -1 -1 30328 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64668 32 32 396 299 1 240 92 17 17 289 -1 unnamed_device 24.1 MiB 2.03 1350 12098 3111 7804 1183 63.2 MiB 0.17 0.00 5.93815 -178.759 -5.93815 5.93815 0.34 0.000774961 0.000720753 0.0484735 0.0450489 -1 -1 -1 -1 30 3179 30 6.89349e+06 394628 556674. 1926.21 1.07 0.154751 0.136253 25186 138497 -1 2629 22 1591 2517 184543 45433 4.56655 4.56655 -159.834 -4.56655 0 0 706193. 2443.58 0.03 0.05 0.08 -1 -1 0.03 0.0173111 0.0152944 167 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 3.42 vpr 63.09 MiB -1 -1 0.18 18056 1 0.03 -1 -1 30168 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 30 32 224 207 1 138 79 17 17 289 -1 unnamed_device 23.6 MiB 0.86 744 11064 2972 6586 1506 63.1 MiB 0.09 0.00 3.06986 -93.837 -3.06986 3.06986 0.33 0.00050022 0.000465468 0.0342512 0.0318795 -1 -1 -1 -1 32 1608 21 6.89349e+06 239595 586450. 2029.24 0.51 0.0930254 0.0819585 25474 144626 -1 1362 19 746 975 64274 15732 2.15637 2.15637 -86.663 -2.15637 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0186802 0.0161973 80 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 4.09 vpr 63.19 MiB -1 -1 0.24 18064 1 0.03 -1 -1 30332 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 30 32 286 239 1 176 85 17 17 289 -1 unnamed_device 23.6 MiB 1.17 970 14221 4684 7353 2184 63.2 MiB 0.13 0.00 4.47457 -139.461 -4.47457 4.47457 0.33 0.000598059 0.000556233 0.0476839 0.0443531 -1 -1 -1 -1 32 2088 19 6.89349e+06 324158 586450. 2029.24 0.57 0.116239 0.102831 25474 144626 -1 1798 19 1209 1755 123419 28254 3.20405 3.20405 -123.196 -3.20405 0 0 744469. 2576.02 0.04 0.06 0.14 -1 -1 0.04 0.0213811 0.0188746 120 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 4.64 vpr 63.24 MiB -1 -1 0.14 18164 1 0.04 -1 -1 30036 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 32 32 296 247 1 187 89 17 17 289 -1 unnamed_device 23.9 MiB 1.81 1127 15137 4309 8906 1922 63.2 MiB 0.15 0.00 4.30299 -142.144 -4.30299 4.30299 0.33 0.000624179 0.000580082 0.0500647 0.0464926 -1 -1 -1 -1 32 2632 22 6.89349e+06 352346 586450. 2029.24 0.65 0.124241 0.109743 25474 144626 -1 2086 21 1194 2198 152487 35249 3.2979 3.2979 -129.639 -3.2979 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0252727 0.0218883 119 34 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 3.81 vpr 63.04 MiB -1 -1 0.23 18076 1 0.03 -1 -1 30284 -1 -1 22 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 25 32 216 194 1 138 79 17 17 289 -1 unnamed_device 23.6 MiB 0.97 598 9881 3477 4123 2281 63.0 MiB 0.07 0.00 3.7089 -85.4656 -3.7089 3.7089 0.33 0.000478077 0.000444482 0.0293864 0.0272887 -1 -1 -1 -1 36 1448 42 6.89349e+06 310065 648988. 2245.63 1.04 0.136492 0.117908 26050 158493 -1 1138 18 657 975 59260 15977 2.93981 2.93981 -80.0624 -2.93981 0 0 828058. 2865.25 0.03 0.03 0.09 -1 -1 0.03 0.00980015 0.00865384 88 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 4.99 vpr 63.14 MiB -1 -1 0.15 18352 1 0.03 -1 -1 30352 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64660 32 32 376 307 1 242 90 17 17 289 -1 unnamed_device 24.1 MiB 2.30 1430 16170 4616 9563 1991 63.1 MiB 0.18 0.00 4.51899 -138.857 -4.51899 4.51899 0.33 0.000721273 0.000669662 0.0603201 0.0559474 -1 -1 -1 -1 32 3301 26 6.89349e+06 366440 586450. 2029.24 0.66 0.151815 0.134188 25474 144626 -1 2662 22 1825 2779 185735 42367 3.63286 3.63286 -129.152 -3.63286 0 0 744469. 2576.02 0.03 0.05 0.08 -1 -1 0.03 0.0164302 0.0144632 156 72 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 5.19 vpr 63.29 MiB -1 -1 0.27 18404 1 0.03 -1 -1 30280 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 31 32 409 331 1 264 96 17 17 289 -1 unnamed_device 24.2 MiB 2.08 1431 11703 3152 7474 1077 63.3 MiB 0.14 0.00 4.84775 -156.008 -4.84775 4.84775 0.33 0.000772559 0.000718063 0.0435525 0.0403604 -1 -1 -1 -1 26 3450 37 6.89349e+06 465097 503264. 1741.40 0.87 0.155585 0.13616 24322 120374 -1 3021 21 2266 3099 239025 58139 4.43869 4.43869 -159.514 -4.43869 0 0 618332. 2139.56 0.03 0.09 0.10 -1 -1 0.03 0.0309079 0.0268354 175 90 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt index 14b02df4c6e..2aa73474bd1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 1864.14 vpr 957.58 MiB -1 -1 22.42 331380 27 13.20 -1 -1 142432 -1 -1 5694 641 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 980564 641 128 52026 52154 1 24058 6463 90 90 8100 clb auto 349.0 MiB 173.06 299893 8009738 3248634 4687011 74093 957.6 MiB 90.11 0.74 14.696 -38781.3 -14.696 14.696 78.67 0.0454146 0.0364574 6.41213 5.29191 66 440752 49 2.50222e+08 6.86455e+07 3.39805e+07 4195.12 1395.25 30.8998 26.3648 844532 8713078 -1 405206 17 108336 237098 17288222 3304110 13.1078 13.1078 -35765.6 -13.1078 0 0 4.24114e+07 5235.97 21.75 5.86 5.90 -1 -1 21.75 2.25901 2.0474 41833 14777 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 7.58 vpr 64.93 MiB -1 -1 0.84 29792 11 0.37 -1 -1 37192 -1 -1 47 54 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 66492 54 51 461 512 1 307 152 10 10 100 clb auto 26.7 MiB 0.17 2373 13922 2643 10142 1137 64.9 MiB 0.13 0.00 6.47024 -256.927 -6.47024 6.47024 0.33 0.00042886 0.000357536 0.0688225 0.0500239 54 5335 26 1.91864e+06 566585 279084. 2790.84 3.59 0.401441 0.318793 8874 64549 -1 4508 18 1941 9258 477400 107312 5.64329 5.64329 -238.143 -5.64329 0 0 343682. 3436.82 0.14 0.15 0.08 -1 -1 0.14 0.031029 0.0281091 351 351 -1 -1 -1 -1 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 496.86 vpr 906.63 MiB -1 -1 14.92 221280 1 3.28 -1 -1 149256 -1 -1 5125 641 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 928388 641 128 55563 47815 1 19235 5894 85 85 7225 clb auto 357.9 MiB 53.49 222909 7988444 3311697 4529990 146757 906.6 MiB 158.12 1.29 7.30188 -25593.7 -7.30188 7.30188 59.85 0.0346093 0.0287273 5.37677 4.40327 72 301784 47 2.22196e+08 6.43647e+07 3.24327e+07 4488.96 129.63 18.1686 15.4729 798746 8418143 -1 279076 27 66623 107145 10680598 2015876 5.67328 5.67328 -22253.4 -5.67328 0 0 4.04835e+07 5603.25 23.02 4.40 5.91 -1 -1 23.02 2.21605 1.94489 39986 2048 -1 -1 -1 -1 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 8.87 vpr 65.29 MiB -1 -1 0.79 28728 4 0.20 -1 -1 36472 -1 -1 41 54 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 66852 54 51 503 502 1 302 146 10 10 100 clb auto 27.3 MiB 2.56 2020 13202 2597 9296 1309 65.3 MiB 0.11 0.00 4.8288 -228.616 -4.8288 4.8288 0.37 0.000364269 0.000298402 0.0192023 0.0163646 54 4296 26 1.94278e+06 514878 279084. 2790.84 2.89 0.263514 0.235912 9066 64687 -1 3771 16 1579 6792 333407 78376 3.86988 3.86988 -205.334 -3.86988 0 0 343682. 3436.82 0.12 0.10 0.06 -1 -1 0.12 0.0312726 0.0289765 310 279 -1 -1 -1 -1 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 1397.07 vpr 910.60 MiB -1 -1 14.85 221360 1 3.28 -1 -1 149104 -1 -1 5176 641 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 932456 641 128 55563 47815 1 19575 5945 86 86 7396 clb auto 365.9 MiB 147.36 216449 8026913 3325604 4544181 157128 910.6 MiB 163.05 1.15 7.79808 -26173.5 -7.79808 7.79808 74.45 0.0333148 0.0256067 5.40235 4.3967 64 296093 41 2.34635e+08 6.56264e+07 3.02030e+07 4083.70 918.35 25.6673 21.649 786056 7778811 -1 273121 29 74523 108445 10800591 2118622 5.10857 5.10857 -22338.5 -5.10857 0 0 3.78329e+07 5115.32 18.90 4.37 4.97 -1 -1 18.90 2.1942 1.92409 40262 2048 -1 -1 -1 -1 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 7.20 vpr 65.30 MiB -1 -1 0.75 28880 4 0.23 -1 -1 36456 -1 -1 39 54 0 0 success v8.0.0-10948-g76f6d280f release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-44-generic x86_64 2024-08-02T13:50:03 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 66864 54 51 503 502 1 307 144 10 10 100 clb auto 27.3 MiB 1.64 2063 8438 1287 6455 696 65.3 MiB 0.11 0.04 4.75191 -227.336 -4.75191 4.75191 0.39 0.0381416 0.0380647 0.0525767 0.050608 52 4645 30 1.94854e+06 494442 271502. 2715.02 1.67 0.208403 0.193565 8966 63017 -1 3899 50 1667 6383 746112 263022 3.83606 3.83606 -202.472 -3.83606 0 0 335037. 3350.37 0.15 0.37 0.15 -1 -1 0.15 0.120279 0.114452 305 279 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 346.85 vpr 1.15 GiB -1 -1 34.22 328308 27 15.05 -1 -1 138296 -1 -1 6514 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1202304 641 128 52026 52154 1 22211 7283 96 96 9216 clb auto 299.9 MiB 22.55 298865 9039475 3705368 5259409 74698 1174.1 MiB 99.58 0.80 15.6652 -38327.4 -15.6652 15.6652 30.26 0.094057 0.0773765 12.1503 10.1571 -1 -1 -1 -1 52 436843 31 2.87242e+08 7.85314e+07 3.22264e+07 3496.79 84.03 34.4054 28.6501 876764 7891077 -1 405234 17 92350 208771 15162225 3092956 14.5295 14.5295 -35310.2 -14.5295 0 0 3.95636e+07 4292.92 2.28 8.25 6.87 -1 -1 2.28 3.81485 3.27893 44137 14777 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 4.27 vpr 64.04 MiB -1 -1 0.87 26712 11 0.25 -1 -1 33516 -1 -1 51 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65580 54 51 461 512 1 281 156 11 11 121 clb auto 24.7 MiB 0.16 2356 11469 1919 8714 836 64.0 MiB 0.12 0.00 5.64506 -244.834 -5.64506 5.64506 0.13 0.00146196 0.00133342 0.0458162 0.0422569 -1 -1 -1 -1 48 5066 26 2.09946e+06 614805 317060. 2620.33 1.31 0.36651 0.319953 10252 71876 -1 4625 16 1697 8023 407060 95904 5.13857 5.13857 -230.591 -5.13857 0 0 382250. 3159.09 0.01 0.15 0.06 -1 -1 0.01 0.0499744 0.0448408 351 351 -1 -1 -1 -1 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 399.84 vpr 1.07 GiB -1 -1 21.81 218380 1 3.70 -1 -1 145176 -1 -1 5511 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1117152 641 128 55563 47815 1 19087 6280 89 89 7921 clb auto 300.2 MiB 18.05 230047 8461724 3459022 4875110 127592 1091.0 MiB 204.82 1.70 7.09259 -24894.9 -7.09259 7.09259 27.46 0.0722137 0.0620773 11.1205 9.22983 -1 -1 -1 -1 66 309563 40 2.46893e+08 6.92128e+07 3.31523e+07 4185.37 68.55 29.6499 24.5503 846610 8512169 -1 289933 30 70505 114345 10785585 2091912 4.98188 4.98188 -21717.1 -4.98188 0 0 4.13768e+07 5223.69 2.61 7.93 7.55 -1 -1 2.61 4.60052 3.86111 40340 2050 -1 -1 -1 -1 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.46 vpr 64.67 MiB -1 -1 0.88 25784 4 0.13 -1 -1 33088 -1 -1 47 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66224 54 51 503 502 1 293 152 10 10 100 clb auto 25.4 MiB 1.53 2207 8657 1268 6725 664 64.7 MiB 0.12 0.00 4.72142 -243.243 -4.72142 4.72142 0.10 0.00138683 0.00126889 0.0371909 0.0344533 -1 -1 -1 -1 44 4688 46 1.94278e+06 590226 231289. 2312.89 1.36 0.376354 0.326721 8470 54129 -1 4028 17 1662 7146 368098 92041 3.78868 3.78868 -208.146 -3.78868 0 0 291571. 2915.71 0.01 0.14 0.05 -1 -1 0.01 0.0559049 0.0498459 310 281 -1 -1 -1 -1 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 415.20 vpr 1.04 GiB -1 -1 21.75 218308 1 4.05 -1 -1 145180 -1 -1 5620 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1088640 641 128 55563 47815 1 19638 6389 89 89 7921 clb auto 308.1 MiB 52.99 226704 9072863 3788850 5116203 167810 1063.1 MiB 189.74 1.45 7.32093 -25503.3 -7.32093 7.32093 27.00 0.0695794 0.0596563 11.1854 9.32085 -1 -1 -1 -1 62 301435 41 2.47551e+08 7.12563e+07 3.13221e+07 3954.32 64.63 30.1669 25.0298 822850 7925305 -1 280695 33 74632 110486 9460418 1906659 4.74051 4.74051 -21753 -4.74051 0 0 3.86383e+07 4877.96 2.36 8.35 6.62 -1 -1 2.36 5.11529 4.30965 40780 2050 -1 -1 -1 -1 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.14 vpr 64.61 MiB -1 -1 0.49 25988 4 0.16 -1 -1 33144 -1 -1 50 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66164 54 51 503 502 1 302 155 11 11 121 clb auto 25.5 MiB 0.55 2264 11803 2091 8793 919 64.6 MiB 0.15 0.01 4.6074 -231.734 -4.6074 4.6074 0.13 0.00143538 0.00131584 0.0463156 0.0428406 -1 -1 -1 -1 46 4761 36 2.13871e+06 633900 304223. 2514.24 1.58 0.37716 0.328993 10384 69934 -1 4032 15 1433 6356 300467 73316 3.80829 3.80829 -202.73 -3.80829 0 0 371547. 3070.64 0.01 0.12 0.06 -1 -1 0.01 0.0507242 0.0453634 307 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt index 36a72a857e2..e0e23492818 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt @@ -1,11 +1,11 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_2ripple_N8_22nm.xml Md5Core.v common 967.55 vpr 763.48 MiB -1 -1 21.42 218260 1 3.55 -1 -1 145252 -1 -1 2765 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 781804 641 128 55563 47815 1 18442 3534 63 63 3969 clb auto 281.1 MiB 538.53 193346 3958863 1550116 2317083 91664 724.9 MiB 91.43 0.78 7.15591 -24783.9 -7.15591 7.15591 35.35 0.069551 0.0596698 11.0083 9.1981 -1 -1 -1 -1 100 265108 28 1.26034e+08 4.00259e+07 2.46425e+07 6208.74 216.16 44.9729 37.3415 555724 6871176 -1 241564 19 87044 109997 12783883 2167446 5.78182 5.78182 -22734.5 -5.78182 0 0 3.14324e+07 7919.47 11.63 6.19 5.58 -1 -1 11.63 3.3327 2.85451 20869 2050 -1 -1 -1 -1 - k6_frac_2ripple_N8_22nm.xml cordic.v common 8.95 vpr 64.59 MiB -1 -1 0.89 26192 4 0.16 -1 -1 33384 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66140 54 51 503 502 1 316 136 9 9 81 clb auto 25.8 MiB 3.67 1981 10606 1997 7706 903 64.6 MiB 0.14 0.01 4.17161 -228.336 -4.17161 4.17161 0.15 0.00186072 0.00171427 0.0514286 0.0475525 -1 -1 -1 -1 64 3792 30 1.45065e+06 448746 257695. 3181.41 2.54 0.574843 0.497531 8184 62525 -1 3344 18 1920 7095 335845 82840 3.72075 3.72075 -206.153 -3.72075 0 0 325495. 4018.46 0.07 0.13 0.06 -1 -1 0.07 0.0566057 0.0503365 223 281 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1559.25 vpr 722.84 MiB -1 -1 21.49 218496 1 3.59 -1 -1 145220 -1 -1 2755 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 740192 641 128 55563 47815 1 18420 3524 63 63 3969 clb auto 275.9 MiB 401.16 189162 3756364 1484461 2184211 87692 722.8 MiB 82.41 0.75 6.93106 -24149.1 -6.93106 6.93106 33.22 0.0717932 0.0614288 10.2573 8.56904 -1 -1 -1 -1 96 272845 49 1.26708e+08 4.05424e+07 2.39085e+07 6023.80 957.73 60.3389 49.6676 543820 6559920 -1 240871 21 88185 112391 12448748 2170100 5.42465 5.42465 -22151.3 -5.42465 0 0 2.98904e+07 7530.95 11.16 6.44 5.45 -1 -1 11.16 3.58618 3.05396 20824 2050 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml cordic.v common 4.56 vpr 64.47 MiB -1 -1 0.86 25908 4 0.16 -1 -1 33380 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66020 54 51 503 502 1 317 136 9 9 81 clb auto 25.8 MiB 0.24 1985 6767 1049 5344 374 64.5 MiB 0.10 0.00 4.17356 -220.898 -4.17356 4.17356 0.15 0.00138081 0.00127221 0.0330425 0.0306558 -1 -1 -1 -1 60 3856 40 1.45905e+06 456186 242836. 2997.97 1.76 0.429337 0.371533 7944 58396 -1 3350 17 1679 5954 301000 77818 3.8968 3.8968 -205.243 -3.8968 0 0 304930. 3764.57 0.07 0.12 0.06 -1 -1 0.07 0.0544767 0.0485746 223 281 -1 -1 -1 -1 - k6_frac_N8_22nm.xml Md5Core.v common 1120.51 vpr 806.71 MiB -1 -1 35.59 328120 27 14.77 -1 -1 138400 -1 -1 3317 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 826068 641 128 52026 52154 1 23512 4086 69 69 4761 clb auto 272.8 MiB 754.36 261133 4150890 1586658 2510234 53998 806.7 MiB 66.92 0.57 15.1822 -39318.8 -15.1822 15.1822 40.15 0.0882437 0.0769439 12.042 10.1836 -1 -1 -1 -1 86 398717 44 1.50071e+08 4.46866e+07 2.62257e+07 5508.44 135.32 40.4871 34.0228 609466 7129297 -1 363314 18 111266 235135 19285517 3561010 13.209 13.209 -36299.7 -13.209 0 0 3.28825e+07 6906.63 13.30 9.39 5.66 -1 -1 13.30 4.36645 3.79962 24398 14777 -1 -1 -1 -1 - k6_frac_N8_22nm.xml cordic.v common 5.30 vpr 64.01 MiB -1 -1 0.90 26384 11 0.25 -1 -1 33576 -1 -1 32 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65548 54 51 461 512 1 320 137 9 9 81 clb auto 24.8 MiB 0.23 2288 7197 1051 5690 456 64.0 MiB 0.10 0.00 6.24973 -250.56 -6.24973 6.24973 0.15 0.00144607 0.00132918 0.0370165 0.0342281 -1 -1 -1 -1 68 4737 28 1.41552e+06 431104 273575. 3377.47 2.36 0.459262 0.397505 8204 65576 -1 4227 16 2032 7777 430507 103502 5.511 5.511 -231.556 -5.511 0 0 341260. 4213.08 0.07 0.09 0.04 -1 -1 0.07 0.0317702 0.0289934 248 351 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml Md5Core.v common 1137.63 vpr 796.55 MiB -1 -1 21.77 218484 1 3.71 -1 -1 145332 -1 -1 3347 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 815668 641 128 55563 47815 1 19485 4116 69 69 4761 clb auto 265.0 MiB 674.41 209187 4719112 1762947 2769356 186809 796.6 MiB 133.07 1.12 7.50454 -24350.9 -7.50454 7.50454 41.02 0.0732288 0.0593247 10.5586 8.73373 -1 -1 -1 -1 78 280465 38 1.51752e+08 4.6769e+07 2.40314e+07 5047.55 201.27 45.7702 37.9151 599066 6522637 -1 262949 17 86466 116965 11441653 2162489 4.92975 4.92975 -21271.4 -4.92975 0 0 3.01399e+07 6330.58 12.77 5.93 5.15 -1 -1 12.77 3.01721 2.57504 25690 2050 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml cordic.v common 6.89 vpr 64.07 MiB -1 -1 0.89 25656 4 0.16 -1 -1 33436 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65612 54 51 503 502 1 304 136 9 9 81 clb auto 25.2 MiB 2.05 1922 8163 1239 6107 817 64.1 MiB 0.12 0.01 4.46634 -227.611 -4.46634 4.46634 0.15 0.00138637 0.00127855 0.0380722 0.0352824 -1 -1 -1 -1 58 4010 35 1.43308e+06 433189 237595. 2933.27 2.17 0.473652 0.409252 7864 57025 -1 3504 19 1914 6815 355293 91574 4.00986 4.00986 -203.926 -4.00986 0 0 298762. 3688.42 0.06 0.14 0.06 -1 -1 0.06 0.0573607 0.0506837 231 281 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml Md5Core.v common 725.64 vpr 847.35 MiB -1 -1 21.61 218272 1 3.62 -1 -1 145224 -1 -1 3391 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 867688 641 128 55563 47815 1 19453 4160 70 70 4900 clb auto 257.6 MiB 242.61 229476 4786509 1811673 2839137 135699 847.4 MiB 144.98 1.15 8.45033 -26255.9 -8.45033 8.45033 44.55 0.0706407 0.0605663 9.85709 8.24084 -1 -1 -1 -1 74 309564 47 1.56988e+08 4.77907e+07 2.37944e+07 4855.99 205.74 40.3572 33.4092 603630 6360748 -1 281191 24 82458 102666 12068393 2210419 5.62486 5.62486 -22699.9 -5.62486 0 0 2.96071e+07 6042.26 11.42 6.73 5.01 -1 -1 11.42 3.76274 3.16053 25717 2050 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml cordic.v common 5.09 vpr 64.27 MiB -1 -1 0.90 25612 4 0.16 -1 -1 33360 -1 -1 33 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65812 54 51 503 502 1 307 138 9 9 81 clb auto 25.3 MiB 0.70 2035 12242 2410 8614 1218 64.3 MiB 0.15 0.00 4.64981 -235.444 -4.64981 4.64981 0.15 0.00138199 0.00127842 0.0546169 0.0504723 -1 -1 -1 -1 54 4324 35 1.43728e+06 465097 226270. 2793.45 1.66 0.427278 0.370182 7624 52756 -1 3604 19 1920 6934 318277 82324 3.81736 3.81736 -208.354 -3.81736 0 0 280165. 3458.82 0.06 0.13 0.05 -1 -1 0.06 0.0571091 0.0505347 247 281 -1 -1 -1 -1 + k6_frac_2ripple_N8_22nm.xml Md5Core.v common 541.33 vpr 770.48 MiB -1 -1 21.57 219052 1 3.94 -1 -1 145160 -1 -1 2904 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 788976 641 128 55563 47815 1 17837 3673 65 65 4225 clb auto 278.4 MiB 280.64 186842 4139415 1628153 2426823 84439 770.5 MiB 80.11 0.65 6.85172 -24425.5 -6.85172 6.85172 17.37 0.0707807 0.0606116 10.8556 9.00171 -1 -1 -1 -1 86 266896 42 1.34217e+08 4.20381e+07 2.31978e+07 5490.61 95.85 37.0767 30.5473 551762 6310377 -1 239670 19 85960 107325 12022295 2121435 5.37037 5.37037 -22498.9 -5.37037 0 0 2.90884e+07 6884.83 1.53 5.92 5.28 -1 -1 1.53 3.24584 2.77988 21038 2050 -1 -1 -1 -1 + k6_frac_2ripple_N8_22nm.xml cordic.v common 7.58 vpr 65.10 MiB -1 -1 0.88 26100 4 0.16 -1 -1 33024 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66664 54 51 503 502 1 316 138 9 9 81 clb auto 26.1 MiB 3.78 1956 11174 2060 8307 807 65.1 MiB 0.13 0.00 4.40854 -233.833 -4.40854 4.40854 0.09 0.00139097 0.00128641 0.0504025 0.0467374 -1 -1 -1 -1 56 4041 27 1.45065e+06 477698 231774. 2861.41 1.17 0.353028 0.308187 7704 54090 -1 3517 18 1771 6187 313268 82102 4.02896 4.02896 -216.237 -4.02896 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0573414 0.0511544 225 281 -1 -1 -1 -1 + k6_frac_2uripple_N8_22nm.xml Md5Core.v common 445.49 vpr 768.55 MiB -1 -1 21.93 218372 1 4.17 -1 -1 145216 -1 -1 2904 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 787000 641 128 55563 47815 1 17906 3673 65 65 4225 clb auto 273.5 MiB 187.96 185308 3941126 1565098 2300167 75861 768.6 MiB 89.53 0.80 6.8947 -23916.3 -6.8947 6.8947 17.72 0.0715102 0.0611769 10.6329 8.87437 -1 -1 -1 -1 86 262207 37 1.34928e+08 4.2735e+07 2.31978e+07 5490.61 81.66 34.9922 28.9773 551762 6310377 -1 236506 17 80887 101963 10950479 1939027 5.59715 5.59715 -21989.7 -5.59715 0 0 2.90884e+07 6884.83 1.64 5.62 5.31 -1 -1 1.64 3.04009 2.59505 20989 2050 -1 -1 -1 -1 + k6_frac_2uripple_N8_22nm.xml cordic.v common 5.96 vpr 64.87 MiB -1 -1 0.87 26208 4 0.16 -1 -1 33076 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66424 54 51 503 502 1 318 138 9 9 81 clb auto 25.9 MiB 0.40 1964 10462 1843 7559 1060 64.9 MiB 0.13 0.00 4.28518 -225.617 -4.28518 4.28518 0.09 0.00139646 0.00129195 0.0476616 0.0441834 -1 -1 -1 -1 56 4128 31 1.45905e+06 485618 231774. 2861.41 2.57 0.547183 0.474234 7704 54090 -1 3583 18 1731 6262 331465 85566 3.8968 3.8968 -212.026 -3.8968 0 0 286113. 3532.26 0.01 0.14 0.05 -1 -1 0.01 0.058103 0.0518196 225 281 -1 -1 -1 -1 + k6_frac_N8_22nm.xml Md5Core.v common 523.72 vpr 809.32 MiB -1 -1 35.88 328152 27 14.52 -1 -1 138636 -1 -1 3446 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 828744 641 128 52026 52154 1 22420 4215 70 70 4900 clb auto 269.8 MiB 211.66 265423 4326406 1648229 2614689 63488 809.3 MiB 79.80 0.65 14.952 -39387.3 -14.952 14.952 20.28 0.0925834 0.0810563 12.6496 10.7217 -1 -1 -1 -1 84 394620 43 1.54829e+08 4.64245e+07 2.64571e+07 5399.40 108.95 44.8309 37.5465 624050 7235563 -1 356794 20 108067 230531 16879775 3154299 13.0725 13.0725 -36269.1 -13.0725 0 0 3.34846e+07 6833.59 1.94 9.36 5.72 -1 -1 1.94 4.65498 4.01829 24663 14777 -1 -1 -1 -1 + k6_frac_N8_22nm.xml cordic.v common 4.95 vpr 64.28 MiB -1 -1 0.95 26424 11 0.25 -1 -1 33660 -1 -1 34 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65824 54 51 461 512 1 317 139 9 9 81 clb auto 25.0 MiB 0.23 2204 9473 1828 7093 552 64.3 MiB 0.12 0.00 6.42199 -256.014 -6.42199 6.42199 0.09 0.00144714 0.00133734 0.0443724 0.0410787 -1 -1 -1 -1 62 4693 48 1.41552e+06 458048 249781. 3083.72 1.55 0.41392 0.360399 7884 59488 -1 3923 19 2092 8192 403186 97926 5.39904 5.39904 -231.32 -5.39904 0 0 310465. 3832.90 0.01 0.10 0.04 -1 -1 0.01 0.0365187 0.0331706 252 351 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml Md5Core.v common 968.02 vpr 871.61 MiB -1 -1 22.34 218328 1 3.90 -1 -1 145312 -1 -1 3580 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 892524 641 128 55563 47815 1 19465 4349 71 71 5041 clb auto 262.5 MiB 670.29 210279 5114045 1917429 3043210 153406 871.6 MiB 143.83 0.80 7.61884 -24559.3 -7.61884 7.61884 21.38 0.0719772 0.0594682 10.7407 8.89088 -1 -1 -1 -1 72 286581 46 1.58244e+08 5.00245e+07 2.39867e+07 4758.32 62.14 31.0052 25.5746 615390 6416121 -1 266321 24 92304 125385 12396060 2405052 4.93927 4.93927 -21502.9 -4.93927 0 0 3.00078e+07 5952.75 1.71 7.10 5.50 -1 -1 1.71 3.83741 3.21004 25723 2050 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml cordic.v common 5.83 vpr 64.57 MiB -1 -1 0.88 26136 4 0.16 -1 -1 33044 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66124 54 51 503 502 1 304 138 9 9 81 clb auto 25.3 MiB 2.08 2002 12954 2480 9062 1412 64.6 MiB 0.20 0.01 4.43013 -227.708 -4.43013 4.43013 0.09 0.001451 0.0013363 0.0685664 0.0632597 -1 -1 -1 -1 56 4228 32 1.43308e+06 461137 231774. 2861.41 1.26 0.391145 0.341818 7704 54090 -1 3725 17 1917 7166 373067 93632 3.65072 3.65072 -196.427 -3.65072 0 0 286113. 3532.26 0.01 0.09 0.03 -1 -1 0.01 0.0324143 0.0294926 234 281 -1 -1 -1 -1 + k6_frac_uripple_N8_22nm.xml Md5Core.v common 472.40 vpr 866.96 MiB -1 -1 22.33 218376 1 4.13 -1 -1 145204 -1 -1 3485 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 887772 641 128 55563 47815 1 18425 4254 71 71 5041 clb auto 256.6 MiB 191.79 205408 4896722 1844424 2914068 138230 867.0 MiB 129.30 1.04 8.03131 -25587.9 -8.03131 8.03131 21.08 0.0733517 0.0590529 10.6832 8.73949 -1 -1 -1 -1 64 273108 50 1.5868e+08 4.91153e+07 2.16513e+07 4295.04 61.30 30.7872 25.3336 590190 5755241 -1 250871 18 71120 89065 8566793 1619750 5.5524 5.5524 -21928.1 -5.5524 0 0 2.72404e+07 5403.77 1.82 6.19 4.71 -1 -1 1.82 3.42355 2.88442 25749 2050 -1 -1 -1 -1 + k6_frac_uripple_N8_22nm.xml cordic.v common 4.49 vpr 64.21 MiB -1 -1 0.92 26136 4 0.16 -1 -1 33152 -1 -1 35 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65752 54 51 503 502 1 303 140 9 9 81 clb auto 25.4 MiB 0.68 1940 13934 2921 9841 1172 64.2 MiB 0.17 0.00 4.47128 -234.847 -4.47128 4.47128 0.09 0.00140285 0.00129011 0.0597002 0.0551005 -1 -1 -1 -1 56 3999 30 1.43728e+06 493284 231774. 2861.41 1.11 0.375638 0.327858 7704 54090 -1 3545 17 1758 6326 315468 81095 3.68106 3.68106 -203.624 -3.68106 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0539124 0.0479125 251 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt index f58fc23a7d9..bc4a9702b59 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt @@ -1,31 +1,31 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.76 vpr 64.06 MiB -1 -1 0.45 18428 3 0.09 -1 -1 33228 -1 53036 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65596 99 130 344 474 1 226 298 12 12 144 clb auto 24.8 MiB 0.08 690 66963 18463 34948 13552 64.1 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128301 0.00121619 0.0902368 0.085465 -1 -1 -1 -1 48 1235 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.88 0.373857 0.343183 13382 75762 -1 1211 8 384 646 27249 8414 1.92052 1.92052 -141.203 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.04 0.07 -1 -1 0.11 0.027115 0.0250754 0.01051 0.26 0.08082 0.6592 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 14.27 vpr 67.39 MiB -1 -1 0.71 23632 15 0.35 -1 -1 34492 -1 54792 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69008 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.2 MiB 0.26 5690 95430 30621 57523 7286 67.4 MiB 0.71 0.01 21.0118 -1578.46 -21.0118 21.0118 0.51 0.00329249 0.00309405 0.327743 0.307697 -1 -1 -1 -1 48 13017 37 1.21132e+07 4.08187e+06 756778. 2956.16 7.85 1.49988 1.37661 25228 149258 -1 10215 19 3466 7106 912370 260096 21.8757 21.8757 -1697.9 -21.8757 0 0 968034. 3781.38 0.22 0.33 0.13 -1 -1 0.22 0.146899 0.13583 0.007773 0.3631 0.01709 0.6198 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 401.39 vpr 460.05 MiB -1 -1 83.22 343248 123 58.49 -1 -1 79500 -1 117196 1366 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 471088 114 102 21994 21904 1 11836 1635 50 50 2500 memory auto 154.8 MiB 20.21 157807 1070343 385976 662554 21813 460.0 MiB 25.59 0.21 79.4041 -53458.1 -79.4041 79.4041 19.31 0.0604453 0.0527448 7.45004 6.20215 -1 -1 -1 -1 94 240754 50 1.47946e+08 1.0145e+08 1.55181e+07 6207.23 114.06 27.7995 22.9975 341268 3271592 -1 215929 21 44770 168610 10181079 1913380 79.6681 79.6681 -67309 -79.6681 -34.1184 -0.295467 1.95446e+07 7817.85 7.00 6.34 2.88 -1 -1 7.00 3.52242 3.0254 0.08167 0.4293 0.0115 0.5592 - k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.68 vpr 64.21 MiB -1 -1 0.49 18412 3 0.09 -1 -1 33192 -1 53180 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65752 99 130 344 474 1 226 298 12 12 144 clb auto 25.2 MiB 0.10 819 72933 24290 33841 14802 64.2 MiB 0.24 0.00 1.91347 -122.834 -1.91347 1.91347 0.26 0.00128041 0.00121074 0.0975158 0.0923199 -1 -1 -1 -1 46 1427 13 5.66058e+06 4.21279e+06 378970. 2631.74 1.69 0.37035 0.339938 13238 73581 -1 1364 9 400 647 30525 8792 1.87624 1.87624 -136.601 -1.87624 -1.17589 -0.322548 486261. 3376.82 0.10 0.05 0.07 -1 -1 0.10 0.029177 0.0269441 0.01251 0.2572 0.06872 0.6741 - k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml diffeq1.v common 13.20 vpr 67.45 MiB -1 -1 0.72 23304 15 0.35 -1 -1 34404 -1 54880 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69064 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.2 MiB 0.33 5690 95430 30623 57523 7284 67.4 MiB 0.72 0.01 21.0118 -1578.35 -21.0118 21.0118 0.52 0.00334815 0.00314845 0.334671 0.314364 -1 -1 -1 -1 48 13572 38 1.21132e+07 4.08187e+06 756778. 2956.16 6.63 1.3536 1.2446 25228 149258 -1 10088 17 3403 6982 882550 253315 21.8901 21.8901 -1680.47 -21.8901 0 0 968034. 3781.38 0.22 0.31 0.13 -1 -1 0.22 0.135825 0.125866 0.008049 0.3475 0.01649 0.636 - k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 408.55 vpr 462.37 MiB -1 -1 83.91 346936 123 56.59 -1 -1 79516 -1 117232 1283 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 473464 114 102 21994 21904 1 11396 1552 50 50 2500 memory auto 158.9 MiB 48.19 155931 971608 341857 610635 19116 462.4 MiB 25.21 0.21 80.3837 -53565.2 -80.3837 80.3837 20.66 0.0618498 0.0542286 7.48256 6.24492 -1 -1 -1 -1 96 229667 22 1.47946e+08 9.69764e+07 1.58254e+07 6330.17 92.97 25.1374 20.8491 343768 3324272 -1 208496 21 41726 161181 9376663 1766124 80.5561 80.5561 -67304.6 -80.5561 -13.3147 -0.295467 1.97871e+07 7914.84 6.32 5.96 2.94 -1 -1 6.32 3.48565 2.98525 0.08322 0.4235 0.01132 0.5652 - k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.77 vpr 64.30 MiB -1 -1 0.47 18588 3 0.09 -1 -1 33172 -1 53072 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65844 99 130 344 474 1 226 298 12 12 144 clb auto 25.1 MiB 0.15 699 66963 17966 34693 14304 64.3 MiB 0.23 0.00 1.84343 -124.37 -1.84343 1.84343 0.27 0.00123085 0.00116207 0.0901875 0.0853725 -1 -1 -1 -1 34 1396 8 5.66058e+06 4.21279e+06 307677. 2136.65 1.83 0.530992 0.483083 12584 59343 -1 1233 10 404 639 23079 7765 1.94353 1.94353 -145.674 -1.94353 -0.336499 -0.167028 377431. 2621.05 0.09 0.05 0.05 -1 -1 0.09 0.0313345 0.0289285 0.01001 0.231 0.07204 0.697 - k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 13.25 vpr 67.53 MiB -1 -1 0.72 23416 15 0.35 -1 -1 34272 -1 54808 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69152 162 96 1009 950 1 705 302 16 16 256 mult_36 auto 28.3 MiB 0.84 5916 86322 26942 52489 6891 67.5 MiB 0.65 0.01 21.2591 -1580.87 -21.2591 21.2591 0.54 0.00333899 0.00313775 0.30219 0.283938 -1 -1 -1 -1 48 12788 29 1.21132e+07 4.08187e+06 791884. 3093.30 6.16 1.45115 1.33083 26208 159478 -1 10226 17 3178 6770 896758 257736 22.1828 22.1828 -1735.12 -22.1828 0 0 1.01413e+06 3961.44 0.24 0.32 0.13 -1 -1 0.24 0.137182 0.127174 0.008014 0.3561 0.01656 0.6273 - k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 680.75 vpr 490.74 MiB -1 -1 81.98 346216 123 60.04 -1 -1 79272 -1 117192 1288 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 502520 114 102 21994 21904 1 12045 1557 50 50 2500 memory auto 155.5 MiB 213.60 164488 1011797 361199 628216 22382 490.7 MiB 26.52 0.22 79.4472 -51530.1 -79.4472 79.4472 22.32 0.060741 0.0533068 7.58406 6.36451 -1 -1 -1 -1 96 243545 47 1.47946e+08 9.72458e+07 1.65526e+07 6621.02 194.25 27.7583 23.1223 355864 3561008 -1 217786 21 41299 157335 9832993 1863421 80.3477 80.3477 -63213.1 -80.3477 -9.95257 -0.29436 2.06346e+07 8253.84 6.55 6.06 3.05 -1 -1 6.55 3.47074 2.99437 0.08657 0.4192 0.01142 0.5694 - k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.40 vpr 64.41 MiB -1 -1 0.46 18612 3 0.09 -1 -1 33252 -1 52968 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65952 99 130 344 474 1 226 298 12 12 144 clb auto 25.4 MiB 0.13 692 72933 23276 35223 14434 64.4 MiB 0.24 0.00 1.86464 -118.633 -1.86464 1.86464 0.27 0.00127857 0.00121127 0.0978445 0.0926191 -1 -1 -1 -1 38 1411 12 5.66058e+06 4.21279e+06 334530. 2323.13 1.40 0.417201 0.382648 13012 66834 -1 1212 7 400 636 24860 8313 1.99361 1.99361 -136.339 -1.99361 -0.924755 -0.320482 424691. 2949.24 0.10 0.04 0.06 -1 -1 0.10 0.0250475 0.0232193 0.0114 0.2245 0.06531 0.7102 - k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 10.29 vpr 67.59 MiB -1 -1 0.73 23388 15 0.35 -1 -1 34328 -1 54912 38 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69208 162 96 1009 950 1 706 301 16 16 256 mult_36 auto 28.4 MiB 0.95 5815 73885 21988 46599 5298 67.6 MiB 0.58 0.01 20.9884 -1505.17 -20.9884 20.9884 0.54 0.00334172 0.00313673 0.25816 0.242412 -1 -1 -1 -1 46 13107 32 1.21132e+07 4.02797e+06 761464. 2974.47 3.14 0.910149 0.838444 25952 154797 -1 10036 18 3102 6455 835144 242123 22.1364 22.1364 -1610.51 -22.1364 0 0 979054. 3824.43 0.23 0.31 0.13 -1 -1 0.23 0.142565 0.132103 0.008278 0.3388 0.01582 0.6453 - k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 590.93 vpr 489.86 MiB -1 -1 82.75 346848 123 58.04 -1 -1 79280 -1 117184 1193 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 501620 114 102 21994 21904 1 11319 1462 50 50 2500 memory auto 156.6 MiB 191.22 150803 905508 321541 566075 17892 489.9 MiB 22.88 0.19 78.1077 -50345.2 -78.1077 78.1077 21.98 0.0591849 0.0516876 7.17008 5.99965 -1 -1 -1 -1 92 228120 37 1.47946e+08 9.21257e+07 1.59225e+07 6369.02 133.10 26.7258 22.1743 350868 3451476 -1 203270 20 41572 162541 9562123 1847272 78.237 78.237 -64005.6 -78.237 -38.6467 -0.293253 2.01686e+07 8067.44 6.81 6.03 2.89 -1 -1 6.81 3.4232 2.94021 0.08721 0.4013 0.01147 0.5872 - k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.75 vpr 64.53 MiB -1 -1 0.47 18468 3 0.09 -1 -1 33276 -1 53036 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66076 99 130 344 474 1 224 298 12 12 144 clb auto 25.3 MiB 0.15 684 73928 22492 35269 16167 64.5 MiB 0.25 0.00 1.84564 -120.454 -1.84564 1.84564 0.28 0.00128312 0.00121622 0.099544 0.0942601 -1 -1 -1 -1 32 1444 14 5.66058e+06 4.21279e+06 307825. 2137.67 0.69 0.279002 0.257511 12860 59602 -1 1374 12 375 565 30620 10341 2.02431 2.02431 -141.661 -2.02431 -0.372022 -0.169903 375846. 2610.04 0.09 0.05 0.05 -1 -1 0.09 0.0357317 0.0329107 0.009994 0.2606 0.06791 0.6715 - k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 11.09 vpr 67.76 MiB -1 -1 0.72 23484 15 0.35 -1 -1 34496 -1 54884 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69384 162 96 1009 950 1 712 299 16 16 256 mult_36 auto 28.5 MiB 0.82 5783 78221 22549 49384 6288 67.8 MiB 0.60 0.01 21.2118 -1583.01 -21.2118 21.2118 0.56 0.00335661 0.00314936 0.275732 0.259044 -1 -1 -1 -1 46 13220 42 1.21132e+07 3.92018e+06 791147. 3090.42 4.06 0.996512 0.917657 26792 163197 -1 10183 19 3349 7152 989589 281475 22.2653 22.2653 -1681.46 -22.2653 0 0 1.01637e+06 3970.19 0.23 0.34 0.13 -1 -1 0.23 0.146642 0.135717 0.008056 0.352 0.01624 0.6318 - k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 685.71 vpr 541.36 MiB -1 -1 82.72 346304 123 60.41 -1 -1 79620 -1 117176 1274 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 554352 114 102 21994 21904 1 11815 1543 50 50 2500 memory auto 156.5 MiB 261.00 166633 946215 318795 604305 23115 541.4 MiB 23.62 0.21 80.1279 -54074.7 -80.1279 80.1279 26.36 0.0593802 0.0519284 6.93138 5.84084 -1 -1 -1 -1 94 248407 44 1.47946e+08 9.64913e+07 1.68500e+07 6739.98 149.04 27.7074 23.0826 363732 3705320 -1 218597 20 39669 154060 10430670 2004897 80.2496 80.2496 -66632.5 -80.2496 -14.4798 -0.29436 2.11127e+07 8445.07 6.74 6.02 3.27 -1 -1 6.74 3.35396 2.8887 0.08961 0.4087 0.01166 0.5796 - k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.69 vpr 64.59 MiB -1 -1 0.47 18536 3 0.09 -1 -1 33168 -1 53016 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66140 99 130 344 474 1 224 298 12 12 144 clb auto 25.6 MiB 0.14 723 72933 21131 35508 16294 64.6 MiB 0.24 0.00 1.84896 -122.984 -1.84896 1.84896 0.28 0.00129708 0.00123013 0.0982963 0.0931302 -1 -1 -1 -1 32 1546 9 5.66058e+06 4.21279e+06 307825. 2137.67 1.66 0.461106 0.422085 12860 59602 -1 1430 7 347 561 25878 8702 1.97804 1.97804 -145.694 -1.97804 -0.24122 -0.0950605 375846. 2610.04 0.09 0.04 0.06 -1 -1 0.09 0.0254919 0.0236226 0.01153 0.2343 0.06023 0.7055 - k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 11.76 vpr 68.03 MiB -1 -1 0.73 23656 15 0.35 -1 -1 34312 -1 54840 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69664 162 96 1009 950 1 712 299 16 16 256 mult_36 auto 28.7 MiB 1.03 5783 78221 22554 49384 6283 68.0 MiB 0.61 0.01 21.2118 -1582.92 -21.2118 21.2118 0.59 0.00341236 0.003205 0.281532 0.264594 -1 -1 -1 -1 46 13227 46 1.21132e+07 3.92018e+06 791147. 3090.42 4.29 1.02224 0.94124 26792 163197 -1 10289 19 3183 6723 927239 263450 22.3978 22.3978 -1754.57 -22.3978 0 0 1.01637e+06 3970.19 0.24 0.35 0.13 -1 -1 0.24 0.152499 0.14121 0.008319 0.3396 0.01564 0.6448 - k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 710.23 vpr 546.39 MiB -1 -1 84.01 346708 123 57.00 -1 -1 79472 -1 117204 1175 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 559508 114 102 21994 21904 1 10942 1444 50 50 2500 memory auto 156.6 MiB 247.45 149383 890666 315853 555376 19437 546.4 MiB 24.29 0.22 78.9433 -49861.2 -78.9433 78.9433 26.06 0.0637968 0.0519727 7.43281 6.14665 -1 -1 -1 -1 92 224977 28 1.47946e+08 9.11556e+07 1.65231e+07 6609.23 189.49 27.8764 23.0735 361236 3648468 -1 197674 21 36197 148054 8655924 1696159 79.8587 79.8587 -61942.5 -79.8587 -11.4535 -0.29436 2.08892e+07 8355.67 6.76 5.76 3.02 -1 -1 6.76 3.44382 2.97064 0.08992 0.3929 0.01157 0.5955 - k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.83 vpr 64.24 MiB -1 -1 0.46 18588 3 0.09 -1 -1 33268 -1 53060 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65780 99 130 344 474 1 226 298 12 12 144 clb auto 25.0 MiB 0.14 690 66963 18463 34948 13552 64.2 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128966 0.00122151 0.0906009 0.0857911 -1 -1 -1 -1 48 1219 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.88 0.374327 0.343576 13382 75762 -1 1213 10 380 620 26636 8291 1.92052 1.92052 -132.564 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.05 0.07 -1 -1 0.11 0.031463 0.0290047 0.01061 0.2612 0.08008 0.6587 - k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 13.92 vpr 67.27 MiB -1 -1 0.74 23740 15 0.35 -1 -1 34420 -1 54776 37 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 68880 162 96 1009 950 1 705 300 16 16 256 mult_36 auto 28.1 MiB 0.78 5822 99597 35964 57057 6576 67.3 MiB 0.75 0.01 20.9826 -1581.32 -20.9826 20.9826 0.51 0.00340159 0.00318809 0.352654 0.330998 -1 -1 -1 -1 46 13288 46 1.21132e+07 3.97408e+06 727248. 2840.81 6.84 1.58393 1.45671 24972 144857 -1 10547 19 3468 7301 1024533 298496 22.4428 22.4428 -1807.38 -22.4428 0 0 934704. 3651.19 0.21 0.34 0.12 -1 -1 0.21 0.144733 0.133839 0.00776 0.3586 0.01653 0.6249 - k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 530.63 vpr 452.32 MiB -1 -1 84.49 343012 123 57.56 -1 -1 79496 -1 117260 1312 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 463172 114 102 21994 21904 1 12069 1581 50 50 2500 memory auto 155.7 MiB 153.23 156855 1014241 368235 623960 22046 452.3 MiB 24.95 0.21 79.7937 -51339.3 -79.7937 79.7937 19.16 0.0602961 0.0527292 7.34313 6.15426 -1 -1 -1 -1 96 234956 41 1.47946e+08 9.85393e+07 1.58254e+07 6330.17 110.51 24.5347 20.3374 343768 3324272 -1 213019 20 45703 171940 10043077 1887993 79.5447 79.5447 -64945.1 -79.5447 -27.0382 -0.295467 1.97871e+07 7914.84 6.68 5.96 2.93 -1 -1 6.68 3.33648 2.88206 0.08305 0.4251 0.01164 0.5633 - k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.60 vpr 64.32 MiB -1 -1 0.46 18460 3 0.09 -1 -1 33116 -1 52940 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65868 99 130 344 474 1 226 298 12 12 144 clb auto 25.3 MiB 0.13 819 72933 24290 33841 14802 64.3 MiB 0.24 0.00 1.91347 -122.834 -1.91347 1.91347 0.26 0.00127684 0.00120774 0.0977163 0.092509 -1 -1 -1 -1 46 1423 13 5.66058e+06 4.21279e+06 378970. 2631.74 1.68 0.370142 0.339907 13238 73581 -1 1376 9 406 664 31725 9062 1.87624 1.87624 -136.482 -1.87624 -1.17589 -0.322548 486261. 3376.82 0.10 0.05 0.07 -1 -1 0.10 0.0294731 0.0272283 0.01259 0.2575 0.06826 0.6742 - k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 11.88 vpr 67.57 MiB -1 -1 0.71 23172 15 0.35 -1 -1 34336 -1 55020 38 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69196 162 96 1009 950 1 712 301 16 16 256 mult_36 auto 28.4 MiB 0.90 5650 82957 25249 50207 7501 67.6 MiB 0.63 0.01 21.0836 -1553.51 -21.0836 21.0836 0.52 0.00341845 0.00321054 0.295101 0.277311 -1 -1 -1 -1 52 12449 43 1.21132e+07 4.02797e+06 805949. 3148.24 4.82 1.2104 1.11453 25992 162577 -1 9670 14 3083 6221 808658 230419 22.2502 22.2502 -1680.34 -22.2502 0 0 1.06067e+06 4143.25 0.23 0.28 0.14 -1 -1 0.23 0.11935 0.1109 0.008212 0.3529 0.01664 0.6305 - k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 567.80 vpr 459.82 MiB -1 -1 83.88 346828 123 56.93 -1 -1 79404 -1 117236 1232 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 470852 114 102 21994 21904 1 11410 1501 50 50 2500 memory auto 157.1 MiB 153.85 152566 937811 338282 579692 19837 459.8 MiB 23.16 0.20 79.5093 -52803.3 -79.5093 79.5093 19.01 0.0589847 0.0516048 7.12415 5.9667 -1 -1 -1 -1 94 230017 31 1.47946e+08 9.42277e+07 1.55181e+07 6207.23 151.42 27.1606 22.5407 341268 3271592 -1 206976 21 43395 164909 10164437 1931987 79.3467 79.3467 -64718.7 -79.3467 -7.07382 -0.296573 1.95446e+07 7817.85 6.05 6.03 2.95 -1 -1 6.05 3.41938 2.93997 0.08398 0.4124 0.01155 0.5761 - k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.79 vpr 64.62 MiB -1 -1 0.46 18580 3 0.09 -1 -1 33112 -1 53044 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66176 99 130 344 474 1 224 298 12 12 144 clb auto 25.4 MiB 0.15 678 73928 21255 36531 16142 64.6 MiB 0.25 0.00 1.84343 -119.532 -1.84343 1.84343 0.27 0.00127236 0.00120574 0.0989421 0.0936831 -1 -1 -1 -1 50 1296 14 5.66058e+06 4.21279e+06 406292. 2821.48 1.82 0.448976 0.411503 13526 77840 -1 1195 11 357 532 29874 9121 1.99509 1.99509 -135.514 -1.99509 -0.544742 -0.178238 520805. 3616.70 0.11 0.05 0.07 -1 -1 0.11 0.0334864 0.0308874 0.01027 0.2615 0.07863 0.6599 - k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 10.02 vpr 67.49 MiB -1 -1 0.73 23636 15 0.35 -1 -1 34472 -1 54844 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69108 162 96 1009 950 1 713 299 16 16 256 mult_36 auto 28.3 MiB 0.75 5721 86213 28592 52244 5377 67.5 MiB 0.66 0.01 20.8058 -1501.7 -20.8058 20.8058 0.51 0.00342119 0.00321645 0.305002 0.28669 -1 -1 -1 -1 48 13175 30 1.21132e+07 3.92018e+06 756778. 2956.16 3.01 0.967828 0.892591 25228 149258 -1 10301 18 3425 6878 942155 258318 22.3533 22.3533 -1697.63 -22.3533 0 0 968034. 3781.38 0.22 0.33 0.14 -1 -1 0.22 0.143607 0.132965 0.007929 0.3557 0.01643 0.6279 - k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 625.06 vpr 452.82 MiB -1 -1 84.98 342824 123 57.69 -1 -1 79376 -1 117200 1303 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 463692 114 102 21994 21904 1 11945 1572 50 50 2500 memory auto 156.6 MiB 165.49 160111 988260 342703 624333 21224 452.8 MiB 23.88 0.23 79.9872 -53373.2 -79.9872 79.9872 18.91 0.0587079 0.0512977 7.09493 5.97271 -1 -1 -1 -1 98 240200 31 1.47946e+08 9.80543e+07 1.60641e+07 6425.63 192.41 27.0374 22.491 348768 3430976 -1 216847 21 44681 169424 9942056 1841988 81.5457 81.5457 -64488 -81.5457 -39.6896 -0.29436 2.03677e+07 8147.07 6.25 5.93 3.10 -1 -1 6.25 3.40108 2.93127 0.08479 0.4269 0.01147 0.5616 - k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.82 vpr 64.68 MiB -1 -1 0.48 18524 3 0.09 -1 -1 33252 -1 53000 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66236 99 130 344 474 1 224 298 12 12 144 clb auto 25.7 MiB 0.13 698 72933 20188 36234 16511 64.7 MiB 0.24 0.00 1.84564 -121.191 -1.84564 1.84564 0.26 0.00128124 0.00121391 0.0977819 0.0926146 -1 -1 -1 -1 48 1220 12 5.66058e+06 4.21279e+06 394078. 2736.65 0.84 0.349739 0.321525 13382 75762 -1 1200 11 356 571 27848 8427 1.97152 1.97152 -138.744 -1.97152 -0.366576 -0.220625 503207. 3494.49 0.11 0.05 0.07 -1 -1 0.11 0.0335359 0.030924 0.01177 0.2373 0.07035 0.6923 - k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 12.60 vpr 67.55 MiB -1 -1 0.73 23468 15 0.35 -1 -1 34400 -1 54856 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69172 162 96 1009 950 1 713 299 16 16 256 mult_36 auto 28.4 MiB 0.93 5721 86213 28592 52244 5377 67.6 MiB 0.66 0.01 20.8058 -1501.7 -20.8058 20.8058 0.51 0.00335344 0.00314925 0.303909 0.285307 -1 -1 -1 -1 50 11869 21 1.21132e+07 3.92018e+06 780512. 3048.87 5.52 1.32663 1.21819 25484 153448 -1 10126 17 3362 6747 918313 252436 22.3405 22.3405 -1650.85 -22.3405 0 0 1.00276e+06 3917.05 0.22 0.31 0.13 -1 -1 0.22 0.137518 0.127577 0.008272 0.3466 0.01554 0.6378 - k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 598.55 vpr 491.77 MiB -1 -1 84.05 346908 123 53.64 -1 -1 79372 -1 117228 1201 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 503568 114 102 21994 21904 1 11170 1470 50 50 2500 memory auto 156.4 MiB 166.03 150651 903810 320390 563000 20420 459.0 MiB 22.23 0.19 78.4561 -52150.3 -78.4561 78.4561 18.73 0.058846 0.0512813 7.13124 5.98955 -1 -1 -1 -1 96 226476 38 1.47946e+08 9.25569e+07 1.58254e+07 6330.17 173.31 36.0661 29.773 343768 3324272 -1 204225 21 42293 163966 10269335 1942383 79.7709 79.7709 -64638.4 -79.7709 -5.0051 -0.29436 1.97871e+07 7914.84 6.66 6.08 2.93 -1 -1 6.66 3.42255 2.94526 0.08545 0.4092 0.0116 0.5791 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.41 vpr 66.85 MiB -1 -1 0.34 22268 3 0.10 -1 -1 37000 -1 54240 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68452 99 130 344 474 1 226 298 12 12 144 clb auto 27.2 MiB 0.07 661 69948 21317 34488 14143 66.8 MiB 0.19 0.00 1.84343 -120.716 -1.84343 1.84343 0.15 0.000836305 0.000777868 0.0624432 0.0579886 -1 -1 -1 -1 48 1234 11 5.66058e+06 4.21279e+06 394078. 2736.65 1.13 0.388411 0.354166 13382 75762 -1 1152 12 449 726 34037 10619 1.91136 1.91136 -134.16 -1.91136 -1.28997 -0.320482 503207. 3494.49 0.02 0.04 0.08 -1 -1 0.02 0.0268156 0.0249636 0.01041 0.2485 0.08202 0.6695 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 11.54 vpr 70.42 MiB -1 -1 0.52 27052 15 0.44 -1 -1 37612 -1 56036 39 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72112 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 30.4 MiB 0.30 5587 92394 30880 53838 7676 70.4 MiB 0.63 0.01 21.0975 -1536.06 -21.0975 21.0975 0.31 0.00264219 0.0024523 0.255431 0.237213 -1 -1 -1 -1 54 12491 42 1.21132e+07 4.08187e+06 835850. 3265.04 5.79 1.11973 1.03745 26248 167850 -1 9804 18 3129 6329 829951 256686 22.2714 22.2714 -1674.4 -22.2714 0 0 1.08614e+06 4242.72 0.05 0.30 0.16 -1 -1 0.05 0.123137 0.115878 0.007816 0.3726 0.01778 0.6096 +k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 445.10 vpr 422.13 MiB -1 -1 69.38 368528 123 78.20 -1 -1 82692 -1 118888 1375 114 45 8 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 432260 114 102 21994 21904 1 11802 1644 50 50 2500 memory auto 156.2 MiB 22.97 160790 1049136 374899 655277 18960 422.1 MiB 26.05 0.23 78.4871 -53143.2 -78.4871 78.4871 11.24 0.052813 0.0462077 6.2757 5.24155 -1 -1 -1 -1 94 237421 37 1.47946e+08 1.01935e+08 1.55181e+07 6207.23 158.08 25.6908 21.7243 341268 3271592 -1 217663 19 44811 172250 10215733 1905978 81.238 81.238 -63088.5 -81.238 -14.6885 -0.29436 1.95446e+07 7817.85 1.30 6.17 3.55 -1 -1 1.30 3.3903 2.9824 0.08135 0.4303 0.01138 0.5584 +k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.52 vpr 67.00 MiB -1 -1 0.34 22060 3 0.09 -1 -1 37120 -1 54184 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68612 99 130 344 474 1 226 298 12 12 144 clb auto 27.4 MiB 0.11 716 68953 19729 34143 15081 67.0 MiB 0.20 0.00 1.84343 -118.985 -1.84343 1.84343 0.16 0.000884793 0.00082197 0.0659105 0.0611015 -1 -1 -1 -1 50 1307 17 5.66058e+06 4.21279e+06 406292. 2821.48 1.16 0.290646 0.265392 13526 77840 -1 1223 12 430 705 34827 10711 2.03591 2.03591 -135.117 -2.03591 -0.536858 -0.172926 520805. 3616.70 0.02 0.04 0.08 -1 -1 0.02 0.0279279 0.0259917 0.01127 0.2362 0.07017 0.6936 +k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml diffeq1.v common 11.30 vpr 70.10 MiB -1 -1 0.54 27172 15 0.44 -1 -1 38168 -1 56116 39 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 71784 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 30.1 MiB 0.39 5587 92394 30879 53839 7676 70.1 MiB 0.66 0.01 21.0975 -1536.12 -21.0975 21.0975 0.31 0.00286543 0.00265289 0.276055 0.256826 -1 -1 -1 -1 56 11626 33 1.21132e+07 4.08187e+06 870502. 3400.40 5.32 1.27718 1.18421 26504 172068 -1 9678 21 2911 5904 758117 233537 22.3178 22.3178 -1651.57 -22.3178 0 0 1.11200e+06 4343.75 0.05 0.32 0.17 -1 -1 0.05 0.141995 0.133696 0.008142 0.3626 0.01671 0.6207 +k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 454.81 vpr 426.46 MiB -1 -1 71.31 367564 123 81.62 -1 -1 82248 -1 118536 1291 114 45 8 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 436700 114 102 21994 21904 1 11352 1560 50 50 2500 memory auto 158.3 MiB 61.05 152483 987356 362069 607612 17675 426.5 MiB 26.52 0.22 79.1367 -50547.3 -79.1367 79.1367 11.72 0.0513453 0.0448586 6.66942 5.5865 -1 -1 -1 -1 92 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2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68676 99 130 344 474 1 226 298 12 12 144 clb auto 27.2 MiB 0.15 708 68953 19077 35256 14620 67.1 MiB 0.19 0.00 1.84675 -120.418 -1.84675 1.84675 0.16 0.000896212 0.000833184 0.0639544 0.0592867 -1 -1 -1 -1 32 1546 17 5.66058e+06 4.21279e+06 295695. 2053.44 0.32 0.170676 0.156606 12440 56522 -1 1380 11 395 551 27778 8974 2.00702 2.00702 -146.809 -2.00702 -0.360519 -0.100806 361905. 2513.23 0.02 0.04 0.05 -1 -1 0.02 0.0259164 0.0241103 0.01128 0.2266 0.06022 0.7132 +k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 10.36 vpr 70.66 MiB -1 -1 0.53 27052 15 0.44 -1 -1 37896 -1 56252 38 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72360 162 96 1009 950 1 695 301 16 16 256 mult_36 auto 30.6 MiB 0.96 5610 94045 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VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 423676 114 102 21994 21904 1 11865 1590 50 50 2500 memory auto 157.0 MiB 234.23 159962 1012674 360995 632974 18705 413.7 MiB 28.65 0.24 80.0347 -53799.9 -80.0347 80.0347 11.56 0.0584029 0.048305 6.87553 5.75603 -1 -1 -1 -1 98 236251 50 1.47946e+08 9.90244e+07 1.60641e+07 6425.63 236.89 27.583 23.3765 348768 3430976 -1 213518 19 44437 171946 9945264 1846943 82.1489 82.1489 -66738.4 -82.1489 -32.5879 -0.295467 2.03677e+07 8147.07 1.31 6.03 3.88 -1 -1 1.31 3.45254 3.05529 0.0845 0.427 0.01145 0.5616 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 2.93 vpr 67.35 MiB -1 -1 0.33 22060 3 0.09 -1 -1 36884 -1 54528 68 99 1 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 68968 99 130 344 474 1 224 298 12 12 144 clb auto 27.6 MiB 0.15 687 68953 19356 33866 15731 67.4 MiB 0.19 0.00 1.84343 -121.129 -1.84343 1.84343 0.16 0.00085163 0.000776737 0.0614238 0.0570225 -1 -1 -1 -1 50 1252 13 5.66058e+06 4.21279e+06 406292. 2821.48 0.55 0.231719 0.212206 13526 77840 -1 1181 11 369 581 25228 7706 1.92695 1.92695 -132.699 -1.92695 -0.484167 -0.178238 520805. 3616.70 0.02 0.04 0.08 -1 -1 0.02 0.0260129 0.0241858 0.01196 0.2348 0.06986 0.6954 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 10.78 vpr 70.93 MiB -1 -1 0.50 27244 15 0.44 -1 -1 37616 -1 56252 39 162 0 5 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 72628 162 96 1009 950 1 696 302 16 16 256 mult_36 auto 30.6 MiB 0.82 5628 84298 25487 51591 7220 70.9 MiB 0.61 0.01 20.5614 -1538.13 -20.5614 20.5614 0.31 0.00277962 0.00258393 0.2467 0.229461 -1 -1 -1 -1 48 11900 27 1.21132e+07 4.08187e+06 756778. 2956.16 4.46 1.13654 1.0514 25228 149258 -1 9893 20 3407 7154 882105 254608 22.0311 22.0311 -1692.99 -22.0311 0 0 968034. 3781.38 0.05 0.34 0.14 -1 -1 0.05 0.137752 0.129626 0.008223 0.3385 0.01605 0.6455 +k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 690.94 vpr 425.08 MiB -1 -1 65.25 367856 123 79.72 -1 -1 82696 -1 118676 1206 114 45 8 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 435280 114 102 21994 21904 1 11136 1475 50 50 2500 memory auto 157.9 MiB 235.02 149552 916312 318253 574633 23426 425.1 MiB 26.64 0.23 79.6388 -49613.8 -79.6388 79.6388 11.39 0.057808 0.048017 6.8334 5.67923 -1 -1 -1 -1 96 228699 35 1.47946e+08 9.28264e+07 1.58254e+07 6330.17 187.06 28.054 23.6791 343768 3324272 -1 203782 21 43588 169952 10265906 1938967 79.9409 79.9409 -62955.8 -79.9409 -22.6241 -0.295467 1.97871e+07 7914.84 1.28 6.23 3.62 -1 -1 1.28 3.53958 3.11283 0.08518 0.4086 0.01162 0.5798 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt index cc62481848e..8d6884970eb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt @@ -1,15 +1,15 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 101.34 parmys 236.79 MiB -1 -1 60.71 242472 13 8.21 -1 -1 47864 -1 49620 321 257 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 95300 257 32 5008 5040 1 2969 610 23 23 529 clb auto 50.4 MiB 3.82 20279 215248 66110 139947 9191 93.1 MiB 3.04 0.04 8.70616 -3949.99 -8.70616 8.70616 1.18 0.0125771 0.0113805 1.0992 0.970008 -1 -1 -1 -1 56 34377 21 2.70004e+07 1.73e+07 1.92373e+06 3636.54 8.22 3.45323 3.01988 56706 387443 -1 30578 16 11916 36297 982790 202359 9.34373 9.34373 -4057.11 -9.34373 0 0 2.45466e+06 4640.18 0.60 0.82 0.32 -1 -1 0.60 0.512599 0.462114 0.01666 0.4299 0.03362 0.5365 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 107.46 parmys 306.12 MiB -1 -1 20.79 313468 7 12.29 -1 -1 61008 -1 50612 547 36 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 159172 36 100 6778 6878 1 3152 683 30 30 900 clb auto 67.4 MiB 3.53 43003 265211 75875 171128 18208 113.8 MiB 5.03 0.06 5.7259 -2235.23 -5.7259 5.7259 2.15 0.0185179 0.0154456 1.73258 1.47032 -1 -1 -1 -1 70 65187 20 4.8774e+07 2.948e+07 4.18297e+06 4647.75 38.88 8.89422 7.5224 106732 854442 -1 61867 16 14594 66731 2752238 371387 6.2856 6.2856 -2335.12 -6.2856 0 0 5.26086e+06 5845.40 1.29 1.60 0.70 -1 -1 1.29 0.836319 0.749628 0.02599 0.3676 0.06197 0.5704 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 24.16 vpr 67.42 MiB -1 -1 17.13 32316 4 0.24 -1 -1 34324 -1 55220 50 195 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69040 195 193 1087 1280 1 611 439 15 15 225 io auto 28.5 MiB 0.29 3380 103793 26292 68639 8862 67.4 MiB 0.54 0.01 2.49928 -1085.58 -2.49928 2.49928 0.45 0.00353825 0.00330455 0.231878 0.216292 -1 -1 -1 -1 38 6431 21 1.03862e+07 3.2427e+06 544128. 2418.35 1.99 1.01597 0.930332 21038 109288 -1 5638 14 1680 2547 165707 45554 2.61737 2.61737 -1202.07 -2.61737 -0.383541 -0.179345 690492. 3068.85 0.16 0.17 0.09 -1 -1 0.16 0.118647 0.10973 0.01444 0.3894 0.05366 0.5569 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.90 vpr 64.11 MiB -1 -1 0.46 18576 3 0.09 -1 -1 33260 -1 53084 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65652 99 130 344 474 1 226 298 12 12 144 clb auto 24.9 MiB 0.08 690 66963 18463 34948 13552 64.1 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128062 0.00121358 0.0901314 0.0853406 -1 -1 -1 -1 48 1235 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.89 0.376068 0.345073 13382 75762 -1 1211 8 384 646 27249 8414 1.92052 1.92052 -141.203 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.04 0.07 -1 -1 0.11 0.0270219 0.0250048 0.01051 0.26 0.08082 0.6592 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 10.77 vpr 67.23 MiB -1 -1 0.74 23536 15 0.37 -1 -1 34412 -1 54864 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 68840 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.0 MiB 0.26 5690 95430 30621 57523 7286 67.2 MiB 0.71 0.01 21.0118 -1578.46 -21.0118 21.0118 0.51 0.00332849 0.00313083 0.328391 0.308461 -1 -1 -1 -1 48 13017 37 1.21132e+07 4.08187e+06 756778. 2956.16 4.22 1.0699 0.986615 25228 149258 -1 10215 19 3466 7106 912370 260096 21.8757 21.8757 -1697.9 -21.8757 0 0 968034. 3781.38 0.22 0.33 0.13 -1 -1 0.22 0.149551 0.138422 0.007773 0.3631 0.01709 0.6198 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 11.72 vpr 65.73 MiB -1 -1 0.58 22544 16 0.25 -1 -1 33408 -1 53836 25 66 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 67312 66 96 616 557 1 415 192 16 16 256 mult_36 auto 26.2 MiB 0.24 3582 35584 8711 22727 4146 65.7 MiB 0.31 0.01 17.0763 -933.216 -17.0763 17.0763 0.51 0.00238059 0.00225121 0.161867 0.152888 -1 -1 -1 -1 38 9038 38 1.21132e+07 3.32735e+06 614590. 2400.74 6.60 0.921446 0.844635 23696 123034 -1 7156 21 2451 5027 1039467 341839 18.1068 18.1068 -1021.94 -18.1068 0 0 780512. 3048.87 0.18 0.32 0.11 -1 -1 0.18 0.111255 0.102688 0.007306 0.3288 0.0194 0.6518 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 412.25 vpr 459.94 MiB -1 -1 83.91 345680 123 55.18 -1 -1 79452 -1 117364 1366 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 470976 114 102 21994 21904 1 11836 1635 50 50 2500 memory auto 154.7 MiB 20.14 157807 1070343 385976 662554 21813 459.9 MiB 27.15 0.21 79.4041 -53458.1 -79.4041 79.4041 20.21 0.0604698 0.0528011 7.69778 6.42684 -1 -1 -1 -1 94 240754 50 1.47946e+08 1.0145e+08 1.55181e+07 6207.23 125.92 26.5625 22.0155 341268 3271592 -1 215929 21 44770 168610 10181079 1913380 79.6681 79.6681 -67309 -79.6681 -34.1184 -0.295467 1.95446e+07 7817.85 5.86 5.76 2.89 -1 -1 5.86 3.26586 2.8046 0.08167 0.4293 0.0115 0.5592 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 90.48 vpr 331.86 MiB -1 -1 18.16 125044 5 3.21 -1 -1 56032 -1 73368 460 506 47 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 339828 506 553 3055 3608 1 2790 1566 50 50 2500 memory auto 46.0 MiB 4.79 16153 1137816 548528 407688 181600 331.9 MiB 5.44 0.07 6.67096 -2020.14 -6.67096 6.67096 19.12 0.0225934 0.0204156 2.93437 2.63134 -1 -1 -1 -1 38 23317 18 1.47946e+08 5.05479e+07 6.86584e+06 2746.33 16.87 8.18989 7.41168 251304 1421084 -1 22431 17 3841 4967 1023796 259831 7.09403 7.09403 -2394.32 -7.09403 -1.60806 -0.199574 8.69095e+06 3476.38 2.76 1.13 1.19 -1 -1 2.76 0.934502 0.861192 0.1726 0.1419 0.03943 0.8187 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 21.17 vpr 71.31 MiB -1 -1 1.27 25292 2 0.14 -1 -1 33632 -1 60032 26 311 15 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 73020 311 156 972 1128 1 953 508 28 28 784 memory auto 28.8 MiB 0.46 9244 197030 68488 118013 10529 71.3 MiB 1.14 0.02 4.08264 -4469.06 -4.08264 4.08264 1.88 0.00555662 0.00492709 0.564647 0.499581 -1 -1 -1 -1 36 15359 25 4.25198e+07 9.62124e+06 1.94918e+06 2486.20 9.68 2.58077 2.28028 74338 387760 -1 14127 14 3001 3471 707329 200421 4.39536 4.39536 -4930.06 -4.39536 -23.3965 -0.340786 2.40571e+06 3068.51 0.65 0.37 0.32 -1 -1 0.65 0.203975 0.183729 0.08358 0.1547 0.01721 0.828 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 25.81 vpr 75.85 MiB -1 -1 8.75 54500 7 2.29 -1 -1 39580 -1 59092 155 193 5 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 77668 193 205 2234 2439 1 1177 558 20 20 400 memory auto 35.7 MiB 1.09 9343 230158 76067 129187 24904 75.8 MiB 1.66 0.02 4.77105 -2950.24 -4.77105 4.77105 0.85 0.00679034 0.00613812 0.712263 0.639828 -1 -1 -1 -1 48 16951 19 2.07112e+07 1.10936e+07 1.23055e+06 3076.38 4.06 1.80116 1.60396 40448 245963 -1 14947 15 4199 10676 555153 128354 5.33264 5.33264 -3131.09 -5.33264 -6.85654 -0.29768 1.57502e+06 3937.55 0.37 0.39 0.21 -1 -1 0.37 0.26107 0.236959 0.029 0.2155 0.0258 0.7587 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 59.82 vpr 99.94 MiB -1 -1 7.76 67916 27 4.04 -1 -1 38688 -1 61160 230 385 2 1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 102336 385 394 3906 4237 1 2371 1012 27 27 729 io auto 45.8 MiB 2.74 31818 549436 207916 318095 23425 88.1 MiB 5.14 0.06 13.6891 -13601.7 -13.6891 13.6891 1.80 0.015847 0.01475 2.00047 1.83115 -1 -1 -1 -1 74 52043 45 3.93038e+07 1.38876e+07 3.51708e+06 4824.52 23.64 7.06874 6.48735 88217 717307 -1 45806 15 11143 38956 2327403 423270 13.7426 13.7426 -14238.9 -13.7426 0 0 4.41327e+06 6053.86 1.15 1.18 0.59 -1 -1 1.15 0.620583 0.577856 0.02262 0.455 0.02732 0.5177 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 26.77 vpr 77.02 MiB -1 -1 6.02 45696 8 1.03 -1 -1 37700 -1 60816 132 235 1 6 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 78872 235 305 2600 2761 1 1513 679 19 19 361 io auto 36.9 MiB 2.30 12446 257217 87938 156711 12568 77.0 MiB 2.00 0.03 5.21052 -2695.25 -5.21052 5.21052 0.78 0.00833798 0.00759325 0.784503 0.720451 -1 -1 -1 -1 56 23724 29 1.72706e+07 1.0038e+07 1.27879e+06 3542.35 6.44 2.59347 2.36584 38159 255829 -1 21061 16 6083 16778 1518471 388985 5.74403 5.74403 -2918.04 -5.74403 -0.678968 -0.063748 1.63234e+06 4521.70 0.37 0.64 0.21 -1 -1 0.37 0.322829 0.298228 0.02425 0.4068 0.02614 0.567 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 19.90 vpr 78.46 MiB -1 -1 4.15 47060 21 2.26 -1 -1 40792 -1 45652 149 38 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 80344 38 36 2570 2606 1 1067 223 17 17 289 clb auto 37.6 MiB 1.11 9186 42135 10514 28822 2799 78.5 MiB 0.87 0.01 14.489 -2637.24 -14.489 14.489 0.59 0.00570235 0.00505996 0.410899 0.362544 -1 -1 -1 -1 48 15409 28 1.34605e+07 8.03021e+06 864508. 2991.38 3.30 1.52379 1.3128 28519 171069 -1 13295 15 4245 12043 362530 70167 15.0234 15.0234 -2942.08 -15.0234 0 0 1.10659e+06 3829.03 0.25 0.37 0.14 -1 -1 0.25 0.250361 0.222953 0.006573 0.364 0.03019 0.6058 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5120.01 vpr 1.66 GiB -1 -1 669.92 1429688 64 3238.48 -1 -1 348532 -1 316988 6755 36 159 27 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 1745216 36 356 125423 124208 1 35759 7333 98 98 9604 clb auto 669.3 MiB 69.08 472751 9976873 4211332 5688117 77424 1704.3 MiB 166.62 1.28 62.922 -266875 -62.922 62.922 79.42 0.238495 0.197947 34.8953 29.1342 -1 -1 -1 -1 84 619524 38 5.9175e+08 4.61843e+08 5.50586e+07 5732.88 291.80 112.255 92.7458 1265060 11766760 -1 588054 18 120512 381178 21916553 4319201 63.8888 63.8888 -334021 -63.8888 0 0 6.99411e+07 7282.50 23.74 17.67 10.44 -1 -1 23.74 11.6929 10.0211 0.2761 0.3715 0.01425 0.6143 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 98.48 parmys 238.48 MiB -1 -1 62.65 244200 13 8.25 -1 -1 47788 -1 49624 326 257 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 95576 257 32 5008 5040 1 2954 615 23 23 529 clb auto 50.5 MiB 2.76 20267 220191 65143 146065 8983 93.3 MiB 2.97 0.04 8.82032 -3904.7 -8.82032 8.82032 0.54 0.0109643 0.0098333 1.02884 0.902188 -1 -1 -1 -1 56 33645 24 2.70004e+07 1.75694e+07 1.92373e+06 3636.54 6.22 3.27588 2.85668 56706 387443 -1 30010 16 11550 36095 972511 199422 9.40635 9.40635 -3964.62 -9.40635 0 0 2.45466e+06 4640.18 0.09 0.82 0.33 -1 -1 0.09 0.508209 0.459137 0.01648 0.4272 0.03377 0.5391 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 94.21 parmys 306.69 MiB -1 -1 21.16 314052 7 13.24 -1 -1 60844 -1 50612 549 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 136868 36 100 6778 6878 1 3144 685 30 30 900 clb auto 67.3 MiB 3.50 42466 287395 83633 184471 19291 113.8 MiB 5.19 0.06 5.74861 -2247.23 -5.74861 5.74861 1.03 0.0222208 0.0200972 1.955 1.66503 -1 -1 -1 -1 66 68658 45 4.8774e+07 2.95878e+07 3.99156e+06 4435.07 27.65 7.52931 6.32406 104036 803752 -1 60922 16 14883 67597 2789200 373708 5.76735 5.76735 -2377.78 -5.76735 0 0 4.95347e+06 5503.86 0.20 1.71 0.69 -1 -1 0.20 0.908064 0.803825 0.02605 0.351 0.06511 0.5839 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 24.14 vpr 68.57 MiB -1 -1 17.73 31664 4 0.24 -1 -1 34328 -1 55248 53 195 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70220 195 193 1087 1280 1 610 442 15 15 225 io auto 28.4 MiB 0.31 3111 131716 33861 86359 11496 68.6 MiB 0.67 0.01 2.49928 -1087.72 -2.49928 2.49928 0.23 0.00362287 0.00338275 0.298018 0.277768 -1 -1 -1 -1 40 5849 18 1.03862e+07 3.40438e+06 568276. 2525.67 1.78 1.09849 1.00863 21262 112936 -1 5416 11 1616 2529 155491 45590 2.72859 2.72859 -1209.59 -2.72859 -0.959406 -0.246 712852. 3168.23 0.02 0.09 0.07 -1 -1 0.02 0.0607763 0.057325 0.01365 0.3769 0.05606 0.567 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.23 vpr 63.89 MiB -1 -1 0.49 18176 3 0.10 -1 -1 33044 -1 53092 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65428 99 130 344 474 1 226 298 12 12 144 clb auto 24.1 MiB 0.08 678 66963 19395 33485 14083 63.9 MiB 0.23 0.00 1.86362 -122.41 -1.86362 1.86362 0.14 0.00130445 0.00123497 0.0907109 0.085881 -1 -1 -1 -1 52 1254 11 5.66058e+06 4.21279e+06 419432. 2912.72 0.65 0.338628 0.310581 13810 82561 -1 1175 7 368 599 29659 8862 1.9806 1.9806 -135.825 -1.9806 -0.309826 -0.0782318 551878. 3832.49 0.02 0.04 0.08 -1 -1 0.02 0.0250196 0.0231993 0.01031 0.263 0.08354 0.6535 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 10.16 vpr 68.16 MiB -1 -1 0.74 23332 15 0.35 -1 -1 34092 -1 54824 39 162 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69796 162 96 1009 950 1 709 302 16 16 256 mult_36 auto 28.2 MiB 0.19 5587 92394 30880 53838 7676 68.2 MiB 0.69 0.01 21.0975 -1536.06 -21.0975 21.0975 0.26 0.00337966 0.00317219 0.323022 0.303359 -1 -1 -1 -1 56 11812 30 1.21132e+07 4.08187e+06 870502. 3400.40 4.17 1.16452 1.07293 26504 172068 -1 9609 16 2935 5927 775463 239759 22.3005 22.3005 -1636.88 -22.3005 0 0 1.11200e+06 4343.75 0.04 0.29 0.15 -1 -1 0.04 0.13141 0.122082 0.007854 0.3765 0.01734 0.6061 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 7.88 vpr 65.00 MiB -1 -1 0.61 21868 16 0.27 -1 -1 33428 -1 53744 25 66 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66560 66 96 616 557 1 415 192 16 16 256 mult_36 auto 25.5 MiB 0.17 3625 36690 9459 22826 4405 65.0 MiB 0.32 0.01 17.203 -935.064 -17.203 17.203 0.26 0.00236496 0.0022302 0.166486 0.157037 -1 -1 -1 -1 40 8373 37 1.21132e+07 3.32735e+06 642278. 2508.90 3.53 0.766237 0.703647 23952 127161 -1 7217 17 2534 5167 951988 292757 18.0101 18.0101 -1019.64 -18.0101 0 0 805949. 3148.24 0.02 0.19 0.08 -1 -1 0.02 0.05209 0.0486566 0.007411 0.3353 0.01978 0.6449 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 440.60 vpr 461.59 MiB -1 -1 84.00 349248 123 64.46 -1 -1 78572 -1 117272 1375 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 472672 114 102 21994 21904 1 11802 1644 50 50 2500 memory auto 155.4 MiB 20.55 160790 1049136 374899 655277 18960 461.6 MiB 26.29 0.22 78.4871 -53143.2 -78.4871 78.4871 9.75 0.0621978 0.0545143 7.35439 6.13837 -1 -1 -1 -1 94 240662 29 1.47946e+08 1.01935e+08 1.55181e+07 6207.23 162.29 28.9908 23.8912 341268 3271592 -1 217509 21 44132 167614 9994098 1867129 81.2261 81.2261 -64082.4 -81.2261 -12.841 -0.29436 1.95446e+07 7817.85 0.86 6.13 3.06 -1 -1 0.86 3.42933 2.93557 0.08134 0.4302 0.01139 0.5585 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 70.13 vpr 332.00 MiB -1 -1 18.29 128412 5 3.25 -1 -1 56812 -1 73340 470 506 47 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 339964 506 553 3055 3608 1 2790 1576 50 50 2500 memory auto 45.7 MiB 4.81 15429 1147451 561958 401565 183928 332.0 MiB 5.51 0.07 7.14518 -1819.3 -7.14518 7.14518 9.87 0.0227758 0.020582 2.93349 2.63053 -1 -1 -1 -1 38 22365 17 1.47946e+08 5.10868e+07 6.86584e+06 2746.33 11.85 8.32526 7.54939 251304 1421084 -1 21433 18 3916 5150 995348 263030 7.69019 7.69019 -2049.85 -7.69019 -5.04137 -0.293253 8.69095e+06 3476.38 0.41 1.18 1.23 -1 -1 0.41 0.985049 0.907039 0.1604 0.1419 0.03923 0.8189 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 13.31 vpr 71.36 MiB -1 -1 1.63 25356 2 0.13 -1 -1 33796 -1 60140 29 311 15 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73068 311 156 972 1128 1 953 511 28 28 784 memory auto 29.5 MiB 0.51 9032 192459 70202 112997 9260 71.4 MiB 1.14 0.02 4.00429 -4585.85 -4.00429 4.00429 0.90 0.00569369 0.00505114 0.564395 0.499447 -1 -1 -1 -1 36 14754 13 4.25198e+07 9.78293e+06 1.94918e+06 2486.20 3.93 1.82677 1.61944 74338 387760 -1 13894 15 2784 3327 698932 209763 4.39426 4.39426 -5070.29 -4.39426 -12.8598 -0.360359 2.40571e+06 3068.51 0.10 0.36 0.33 -1 -1 0.10 0.20904 0.188673 0.0833 0.1522 0.01727 0.8306 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 28.03 vpr 76.09 MiB -1 -1 9.24 55960 7 2.30 -1 -1 37416 -1 59040 157 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77920 193 205 2234 2439 1 1179 560 20 20 400 memory auto 35.6 MiB 1.10 9842 228953 80249 124571 24133 76.1 MiB 1.72 0.02 5.08439 -2926.08 -5.08439 5.08439 0.43 0.00685575 0.00620383 0.738776 0.665656 -1 -1 -1 -1 48 17744 33 2.07112e+07 1.12014e+07 1.23055e+06 3076.38 6.37 2.5483 2.26983 40448 245963 -1 15329 16 4566 11562 627458 139494 5.47739 5.47739 -3135.16 -5.47739 -11.584 -0.360359 1.57502e+06 3937.55 0.06 0.44 0.22 -1 -1 0.06 0.280677 0.254763 0.02856 0.2221 0.02552 0.7523 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 63.07 vpr 106.00 MiB -1 -1 7.93 68908 27 4.13 -1 -1 38580 -1 61144 234 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 108548 385 394 3906 4237 1 2373 1016 27 27 729 io auto 46.0 MiB 2.92 31525 572776 227317 322407 23052 88.3 MiB 5.07 0.06 14.4133 -13461.7 -14.4133 14.4133 0.83 0.0160926 0.0150256 1.89286 1.74364 -1 -1 -1 -1 78 51645 44 3.93038e+07 1.41032e+07 3.65949e+06 5019.88 29.17 7.69214 7.06424 90401 760319 -1 44396 14 10279 35511 1944665 349659 14.8103 14.8103 -13960.4 -14.8103 0 0 4.63207e+06 6354.00 0.16 1.07 0.66 -1 -1 0.16 0.591618 0.549921 0.02224 0.4637 0.02666 0.5097 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 25.27 vpr 77.84 MiB -1 -1 6.25 46808 8 0.90 -1 -1 37872 -1 60796 133 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79708 235 305 2600 2761 1 1501 680 19 19 361 io auto 36.8 MiB 2.09 12500 263712 91208 158948 13556 77.8 MiB 1.99 0.03 5.38636 -2731.89 -5.38636 5.38636 0.39 0.00825643 0.00765916 0.774605 0.712384 -1 -1 -1 -1 56 23995 47 1.72706e+07 1.00919e+07 1.27879e+06 3542.35 6.04 2.65451 2.42437 38159 255829 -1 20300 15 5879 16147 1393547 361528 5.87661 5.87661 -3009.11 -5.87661 -1.26427 -0.201639 1.63234e+06 4521.70 0.07 0.66 0.22 -1 -1 0.07 0.333764 0.30935 0.02386 0.4083 0.02598 0.5657 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 19.44 vpr 78.34 MiB -1 -1 4.20 47476 21 2.24 -1 -1 40644 -1 45784 147 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80220 38 36 2570 2606 1 1050 221 17 17 289 clb auto 37.3 MiB 1.10 9478 36239 7889 25786 2564 78.3 MiB 0.76 0.01 14.6977 -2591.44 -14.6977 14.6977 0.30 0.00627054 0.00560905 0.378906 0.335347 -1 -1 -1 -1 46 16543 25 1.34605e+07 7.92242e+06 830882. 2875.03 3.43 1.51759 1.31374 28231 166010 -1 13884 15 4024 11917 367875 68444 15.3347 15.3347 -2866.69 -15.3347 0 0 1.06831e+06 3696.59 0.04 0.39 0.14 -1 -1 0.04 0.261218 0.233045 0.006476 0.3635 0.02972 0.6068 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5304.23 vpr 1.66 GiB -1 -1 692.05 1442556 64 3350.31 -1 -1 347144 -1 317188 6851 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1741944 36 356 125423 124208 1 34881 7429 98 98 9604 clb auto 660.2 MiB 73.61 461903 10223866 4318975 5823833 81058 1701.1 MiB 186.47 1.32 63.3139 -299631 -63.3139 63.3139 39.62 0.235404 0.202231 35.8753 30.2278 -1 -1 -1 -1 80 612389 32 5.9175e+08 4.67016e+08 5.28775e+07 5505.77 350.18 119.658 98.779 1236252 11146124 -1 575490 18 116226 373166 21552241 4233065 64.9427 64.9427 -370561 -64.9427 0 0 6.66202e+07 6936.71 3.07 14.93 8.56 -1 -1 3.07 9.99565 8.64031 0.27 0.3629 0.01392 0.6231 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt index 829c3da90f8..afc7702ee1c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.75 vpr 64.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66040 14 8 926 934 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6815 89.2 MiB 2.28 0.03 7.83344 -342.752 -7.83344 7.83344 0.92 0.0100177 0.00886659 0.857361 0.741308 92 46721 44 1.74617e+07 1.65455e+07 2.37849e+06 5946.23 18.28 3.97352 3.38216 54288 506964 -1 42503 16 14653 63396 2356990 367690 8.12752 8.12752 -355.073 -8.12752 0 0 3.01539e+06 7538.48 0.69 1.19 0.43 -1 -1 0.69 0.511744 0.462774 -k6_frac_N10_40nm.xml des.pre-vpr.blif common 7.12 vpr 62.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64448 256 245 954 1199 0 578 552 18 18 324 io auto 23.8 MiB 0.33 4966 131806 34568 89483 7755 62.9 MiB 0.48 0.01 3.70962 -712.314 -3.70962 nan 0.74 0.00414551 0.00395387 0.186169 0.176197 36 9086 34 1.37969e+07 2.74859e+06 824466. 2544.65 3.31 1.24102 1.16598 31748 166456 -1 8145 16 2076 4578 247499 55677 4.28288 nan -799.816 -4.28288 0 0 1.01518e+06 3133.28 0.26 0.23 0.13 -1 -1 0.26 0.156872 0.14849 -k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 3.87 vpr 64.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 65 64 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65904 64 39 1371 1410 1 542 168 11 11 121 clb auto 25.2 MiB 0.48 3387 16373 2957 12425 991 64.4 MiB 0.23 0.01 5.33717 -1012.06 -5.33717 5.33717 0.22 0.00291587 0.00263997 0.121115 0.109984 46 5978 20 4.36541e+06 3.50311e+06 343362. 2837.71 1.41 0.597762 0.523358 12051 69045 -1 5146 15 1964 5478 158754 33013 5.81148 5.81148 -1104.11 -5.81148 0 0 440296. 3638.81 0.09 0.18 0.06 -1 -1 0.09 0.122268 0.110374 -k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 10.46 vpr 65.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on 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0.356682 -k6_frac_N10_40nm.xml s298.pre-vpr.blif common 4.12 vpr 62.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 4 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63740 4 6 726 732 1 398 73 10 10 100 clb auto 23.2 MiB 0.75 3666 3417 417 2860 140 62.2 MiB 0.11 0.00 6.02354 -48.3456 -6.02354 6.02354 0.18 0.00201694 0.00183365 0.0626085 0.0572741 50 5820 31 3.44922e+06 3.39532e+06 295697. 2956.97 1.63 0.53661 0.462064 10016 58256 -1 5144 15 2315 9199 280618 50632 6.26562 6.26562 -52.0008 -6.26562 0 0 379824. 3798.24 0.08 0.17 0.05 -1 -1 0.08 0.0972111 0.0881692 -k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 15.85 vpr 87.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 249 29 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89280 29 106 4782 4888 1 2019 384 18 18 324 clb auto 44.7 MiB 2.35 13216 107799 27485 70375 9939 87.2 MiB 1.53 0.02 5.18654 -3584.37 -5.18654 5.18654 0.72 0.00820093 0.00716198 0.7235 0.630423 52 21960 50 1.37969e+07 1.34196e+07 1.12378e+06 3468.47 6.68 2.99225 2.56134 35300 236012 -1 19626 15 6767 19136 685005 132226 5.32162 5.32162 -3691.42 -5.32162 0 0 1.48031e+06 4568.86 0.34 0.58 0.19 -1 -1 0.34 0.406682 0.365814 -k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 16.40 vpr 86.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 226 38 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88452 38 304 4422 4726 1 2052 568 18 18 324 clb auto 43.6 MiB 2.25 13975 176893 52423 113746 10724 86.4 MiB 1.91 0.03 4.9343 -2945.33 -4.9343 4.9343 0.73 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-k6_frac_N10_40nm.xml spla.pre-vpr.blif common 16.32 vpr 76.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78668 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.3 MiB 2.69 15884 45628 10574 32142 2912 76.8 MiB 0.90 0.02 5.95671 -204.452 -5.95671 nan 0.66 0.00655055 0.00559031 0.393901 0.343227 74 25546 32 1.21262e+07 1.16411e+07 1.39325e+06 4820.95 7.80 2.00641 1.71174 35379 286977 -1 24647 19 7675 42760 1737904 249467 6.14143 nan -217.643 -6.14143 0 0 1.74421e+06 6035.33 0.38 0.81 0.26 -1 -1 0.38 0.340644 0.303738 -k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 3.98 vpr 65.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 61 52 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66596 52 122 1461 1583 1 474 235 10 10 100 clb auto 26.0 MiB 0.54 2490 35711 8852 25144 1715 65.0 MiB 0.32 0.01 4.73051 -1125.66 -4.73051 4.73051 0.18 0.00299119 0.00271471 0.1633 0.148553 46 4691 25 3.44922e+06 3.28753e+06 276332. 2763.32 1.35 0.707889 0.622607 9816 55112 -1 4036 15 1411 3526 118896 27892 5.08546 5.08546 -1209.63 -5.08546 0 0 354105. 3541.05 0.07 0.15 0.04 -1 -1 0.07 0.117472 0.106373 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 4.59 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65868 14 8 926 934 0 490 100 11 11 121 clb auto 24.6 MiB 0.91 4639 5668 847 4419 402 64.3 MiB 0.16 0.01 4.54815 -31.8355 -4.54815 nan 0.11 0.00249412 0.00221472 0.083083 0.0754962 -1 -1 -1 -1 48 7214 49 4.36541e+06 4.20373e+06 357017. 2950.55 2.04 0.729015 0.623693 12171 71069 -1 6577 19 3324 15359 408061 81134 4.87162 nan -34.7178 -4.87162 0 0 455885. 3767.64 0.01 0.26 0.06 -1 -1 0.01 0.140142 0.125126 + k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 6.95 vpr 65.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 103 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67448 38 3 1113 1116 0 662 144 13 13 169 clb auto 26.3 MiB 1.53 7442 11831 1926 8689 1216 65.9 MiB 0.29 0.01 5.59822 -16.3249 -5.59822 nan 0.16 0.00306728 0.00270237 0.126883 0.113876 -1 -1 -1 -1 64 12841 39 6.52117e+06 5.55108e+06 687872. 4070.25 3.20 0.976549 0.840439 19211 138678 -1 11425 17 4712 23613 728373 121323 5.82519 nan -16.8677 -5.82519 0 0 856291. 5066.81 0.03 0.36 0.11 -1 -1 0.03 0.160453 0.144609 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.91 vpr 64.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65892 9 19 897 916 0 556 110 12 12 144 clb auto 24.8 MiB 1.46 6252 7474 1266 5720 488 64.3 MiB 0.20 0.01 4.74237 -77.8307 -4.74237 nan 0.14 0.00271417 0.00242922 0.0925149 0.0843887 -1 -1 -1 -1 62 10739 47 5.3894e+06 4.41931e+06 554770. 3852.57 2.59 0.760237 0.654515 15940 110000 -1 9728 17 4391 21118 675575 120995 5.20821 nan -84.4166 -5.20821 0 0 687181. 4772.09 0.02 0.31 0.09 -1 -1 0.02 0.1315 0.118528 + k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 6.12 vpr 65.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67388 229 197 1364 1561 1 539 497 16 16 256 io auto 26.1 MiB 0.83 4504 148022 42306 97632 8084 65.8 MiB 0.82 0.01 2.97254 -656.061 -2.97254 2.97254 0.27 0.00439332 0.00408702 0.35847 0.333653 -1 -1 -1 -1 36 7822 26 1.05632e+07 3.82647e+06 638738. 2495.07 2.60 1.40665 1.28851 24820 128426 -1 7098 11 1611 3987 187232 44731 3.15649 3.15649 -738.429 -3.15649 0 0 786978. 3074.13 0.03 0.19 0.08 -1 -1 0.03 0.132772 0.123936 + k6_frac_N10_40nm.xml clma.pre-vpr.blif common 28.51 vpr 89.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 316 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91500 62 82 3672 3754 1 2348 460 20 20 400 clb auto 45.2 MiB 3.83 29602 121160 32274 82250 6636 89.4 MiB 2.46 0.04 7.97523 -360.045 -7.97523 7.97523 0.44 0.0115817 0.00968577 0.858962 0.732885 -1 -1 -1 -1 92 48575 45 1.74617e+07 1.70305e+07 2.37849e+06 5946.23 16.44 4.93267 4.15445 54288 506964 -1 43403 17 15069 65645 2357098 375873 8.16272 8.16272 -366.296 -8.16272 0 0 3.01539e+06 7538.48 0.10 1.28 0.42 -1 -1 0.10 0.57067 0.510695 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 5.68 vpr 62.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 256 245 954 1199 0 578 552 18 18 324 io auto 23.6 MiB 0.23 5523 134069 36344 90454 7271 63.0 MiB 0.66 0.01 3.66288 -710.092 -3.66288 nan 0.35 0.00435575 0.00415707 0.270866 0.258189 -1 -1 -1 -1 36 9376 41 1.37969e+07 2.74859e+06 824466. 2544.65 2.93 1.43298 1.34768 31748 166456 -1 8164 13 2250 4803 238712 56339 4.07339 nan -791.038 -4.07339 0 0 1.01518e+06 3133.28 0.04 0.21 0.14 -1 -1 0.04 0.139599 0.132291 + k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 3.71 vpr 64.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66072 64 39 1371 1410 1 541 167 10 10 100 clb auto 25.0 MiB 0.50 3623 18986 4100 13819 1067 64.5 MiB 0.29 0.01 5.32461 -1004.72 -5.32461 5.32461 0.09 0.00297013 0.00265425 0.142744 0.129291 -1 -1 -1 -1 50 5495 30 3.44922e+06 3.44922e+06 295697. 2956.97 1.53 0.822979 0.71402 10016 58256 -1 4877 17 1881 5375 141590 30815 5.49357 5.49357 -1059.83 -5.49357 0 0 379824. 3798.24 0.01 0.18 0.05 -1 -1 0.01 0.130986 0.117787 + k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 6.57 vpr 65.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66956 229 197 1362 1559 1 570 496 16 16 256 io auto 25.8 MiB 0.92 5066 137836 36889 92766 8181 65.4 MiB 0.78 0.01 2.91431 -671.379 -2.91431 2.91431 0.27 0.00438808 0.00409538 0.327876 0.305574 -1 -1 -1 -1 36 8862 27 1.05632e+07 3.77258e+06 638738. 2495.07 2.96 1.41434 1.29776 24820 128426 -1 7675 13 1986 5211 265646 63312 3.18697 3.18697 -739.19 -3.18697 0 0 786978. 3074.13 0.03 0.23 0.10 -1 -1 0.03 0.155656 0.14507 + k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 12.40 vpr 77.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 171 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79424 131 114 3421 3535 1 1164 416 16 16 256 clb auto 36.2 MiB 3.40 10474 95088 26501 63930 4657 77.6 MiB 1.19 0.02 7.51043 -4391.12 -7.51043 7.51043 0.26 0.00746347 0.00670247 0.527413 0.462699 -1 -1 -1 -1 56 18313 31 1.05632e+07 9.21587e+06 942187. 3680.42 4.59 2.05209 1.78067 28136 192436 -1 15484 16 5183 22017 710369 128360 7.51944 7.51944 -4543.65 -7.51944 0 0 1.20185e+06 4694.72 0.04 0.55 0.15 -1 -1 0.04 0.349204 0.315387 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 24.75 vpr 82.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83992 10 10 2659 2669 0 1401 305 19 19 361 clb auto 39.3 MiB 4.57 26220 51605 13492 36245 1868 82.0 MiB 1.25 0.02 6.59302 -61.9652 -6.59302 nan 0.39 0.00827542 0.00731978 0.484089 0.41329 -1 -1 -1 -1 90 42829 31 1.55754e+07 1.53598e+07 2.09179e+06 5794.43 14.00 3.32602 2.79995 48131 439069 -1 39158 17 9518 58062 2365838 328796 6.83753 nan -64.8858 -6.83753 0 0 2.60973e+06 7229.16 0.08 1.03 0.29 -1 -1 0.08 0.41705 0.373851 + k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 3.76 vpr 63.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64588 8 63 761 824 0 435 134 10 10 100 clb auto 23.7 MiB 0.68 3999 11420 2063 8488 869 63.1 MiB 0.20 0.01 3.77984 -169.82 -3.77984 nan 0.09 0.00233479 0.00210219 0.0905659 0.0824737 -1 -1 -1 -1 58 6565 28 3.44922e+06 3.39532e+06 342720. 3427.20 1.56 0.557203 0.48462 10608 68480 -1 5918 16 2541 10577 323005 63220 4.22288 nan -188.35 -4.22288 0 0 435638. 4356.38 0.01 0.19 0.05 -1 -1 0.01 0.102623 0.0927145 + k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 13.58 vpr 77.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 167 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79220 20 116 3175 3291 1 1338 303 15 15 225 clb auto 36.1 MiB 3.06 14602 62340 15718 42273 4349 77.4 MiB 1.17 0.02 8.56273 -4519.63 -8.56273 8.56273 0.22 0.00757247 0.0068348 0.522644 0.463063 -1 -1 -1 -1 80 24018 43 9.10809e+06 9.0003e+06 1.12687e+06 5008.33 6.06 2.41987 2.10801 28171 234221 -1 21050 15 6703 26493 1041429 176822 9.09101 9.09101 -4756.62 -9.09101 0 0 1.41774e+06 6301.08 0.04 0.63 0.19 -1 -1 0.04 0.342199 0.310175 + k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 4.84 vpr 63.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 14 14 828 842 0 475 99 11 11 121 clb auto 24.1 MiB 0.91 4532 5343 748 4219 376 63.7 MiB 0.15 0.01 4.39029 -57.6027 -4.39029 nan 0.11 0.00227799 0.00202987 0.0718845 0.0655562 -1 -1 -1 -1 52 7728 41 4.36541e+06 3.82647e+06 379421. 3135.71 2.05 0.703343 0.603899 12531 77429 -1 6634 16 3040 13763 383785 71279 4.69105 nan -60.7462 -4.69105 0 0 499620. 4129.09 0.01 0.15 0.04 -1 -1 0.01 0.0814211 0.0751261 + k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 26.16 vpr 82.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 272 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84416 16 40 2839 2879 0 1511 328 19 19 361 clb auto 39.8 MiB 3.52 23598 55698 13292 40268 2138 82.4 MiB 1.28 0.02 6.48626 -238.484 -6.48626 nan 0.44 0.00886302 0.00735171 0.491212 0.417579 -1 -1 -1 -1 82 38584 40 1.55754e+07 1.46592e+07 1.91630e+06 5308.30 16.27 3.50905 2.95866 46331 403357 -1 35281 17 9680 52085 1891572 294823 6.8403 nan -243.508 -6.8403 0 0 2.40187e+06 6653.38 0.08 1.01 0.33 -1 -1 0.08 0.437668 0.392311 + k6_frac_N10_40nm.xml s298.pre-vpr.blif common 3.15 vpr 62.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 4 6 726 732 1 395 74 10 10 100 clb auto 23.4 MiB 0.73 3639 2709 340 2252 117 62.8 MiB 0.10 0.00 6.02711 -48.0055 -6.02711 6.02711 0.09 0.00207648 0.0018638 0.0538424 0.0494959 -1 -1 -1 -1 50 5470 24 3.44922e+06 3.44922e+06 295697. 2956.97 1.28 0.507359 0.443613 10016 58256 -1 4992 17 2195 9283 271197 50082 6.42868 6.42868 -51.2874 -6.42868 0 0 379824. 3798.24 0.01 0.12 0.03 -1 -1 0.01 0.0746748 0.0694149 + k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 13.59 vpr 87.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89136 29 106 4782 4888 1 1993 385 18 18 324 clb auto 44.4 MiB 2.46 13385 89985 21640 60579 7766 87.0 MiB 1.52 0.02 5.22969 -3570.14 -5.22969 5.22969 0.34 0.00938818 0.00831247 0.681949 0.588191 -1 -1 -1 -1 50 21612 42 1.37969e+07 1.34735e+07 1.08879e+06 3360.46 5.45 2.95573 2.52337 34656 222912 -1 19075 14 7130 20879 621675 127526 5.31212 5.31212 -3691.5 -5.31212 0 0 1.40279e+06 4329.61 0.05 0.59 0.17 -1 -1 0.05 0.416139 0.374046 + k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 13.45 vpr 85.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 228 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87964 38 304 4422 4726 1 1994 570 18 18 324 clb auto 43.2 MiB 2.50 13819 172996 49998 111442 11556 85.9 MiB 2.01 0.03 4.76683 -2916.88 -4.76683 4.76683 0.35 0.00939228 0.00841165 0.819185 0.712738 -1 -1 -1 -1 58 23055 36 1.37969e+07 1.22878e+07 1.26150e+06 3893.53 4.75 2.90623 2.51915 36592 261672 -1 20398 14 6469 17425 591858 126037 4.97859 4.97859 -3048.53 -4.97859 0 0 1.60510e+06 4954.00 0.05 0.63 0.21 -1 -1 0.05 0.450883 0.410575 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.73 vpr 65.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66644 41 35 1006 1041 0 604 160 12 12 144 clb auto 25.4 MiB 1.22 6515 13180 2173 9685 1322 65.1 MiB 0.26 0.01 4.58553 -134.055 -4.58553 nan 0.14 0.00299227 0.00267516 0.112623 0.102342 -1 -1 -1 -1 64 10841 30 5.3894e+06 4.5271e+06 575115. 3993.85 2.53 0.863068 0.745904 16224 115365 -1 9534 17 3641 17204 511035 92223 4.88481 nan -140.076 -4.88481 0 0 716128. 4973.11 0.02 0.28 0.09 -1 -1 0.02 0.142307 0.128311 + k6_frac_N10_40nm.xml spla.pre-vpr.blif common 15.03 vpr 76.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78680 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.0 MiB 2.88 16089 42000 9359 30203 2438 76.8 MiB 0.95 0.02 5.95204 -207.143 -5.95204 nan 0.30 0.00775355 0.00661099 0.401796 0.349405 -1 -1 -1 -1 68 27700 45 1.21262e+07 1.16411e+07 1.30851e+06 4527.71 7.55 2.17634 1.8524 34227 265321 -1 23554 19 8023 43603 1540936 228530 6.17174 nan -217.21 -6.17174 0 0 1.61843e+06 5600.10 0.05 0.82 0.21 -1 -1 0.05 0.356964 0.321301 + k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 3.30 vpr 65.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66732 52 122 1461 1583 1 472 237 10 10 100 clb auto 25.8 MiB 0.55 2690 30290 6635 22073 1582 65.2 MiB 0.30 0.01 4.95966 -1122.48 -4.95966 4.95966 0.09 0.00309899 0.0028239 0.143089 0.130468 -1 -1 -1 -1 46 4786 25 3.44922e+06 3.39532e+06 276332. 2763.32 1.07 0.637438 0.562157 9816 55112 -1 4250 13 1489 3922 122560 29939 5.00101 5.00101 -1209.26 -5.00101 0 0 354105. 3541.05 0.01 0.16 0.04 -1 -1 0.01 0.119116 0.108599 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt index 694b1b03602..cc7b62c6a7e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt @@ -1,20 +1,20 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_40nm.xml alu4.pre-vpr.blif common 7.79 vpr 64.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 14 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65584 14 8 926 934 0 517 119 12 12 144 clb auto 24.9 MiB 0.59 4978 9171 1462 7157 552 64.0 MiB 0.27 0.01 4.85854 -36.6925 -4.85854 nan 0.40 0.00229013 0.0019463 0.126381 0.111748 -1 -1 -1 -1 52 6841 26 1.8e+06 1.746e+06 452692. 3143.70 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-1 -1 95 9 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65968 9 19 897 916 0 568 123 12 12 144 clb auto 25.0 MiB 0.57 6616 8358 1251 6625 482 64.4 MiB 0.22 0.01 5.18808 -85.4879 -5.18808 nan 0.39 0.00281312 0.0023275 0.0756863 0.0650474 -1 -1 -1 -1 64 10344 32 1.8e+06 1.71e+06 562980. 3909.58 6.98 1.02613 0.882001 13324 112085 -1 9823 21 5176 24280 1089893 157064 5.18521 nan -85.6966 -5.18521 0 0 705288. 4897.83 0.22 0.47 0.11 -1 -1 0.22 0.162583 0.148293 -k6_N10_40nm.xml bigkey.pre-vpr.blif common 12.60 vpr 65.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 229 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66928 263 197 1372 1603 1 490 554 17 17 289 io auto 26.0 MiB 0.36 4312 159734 46622 103443 9669 65.4 MiB 1.19 0.03 3.07033 -729.814 -3.07033 3.07033 1.14 0.00415099 0.00372162 0.308823 0.273056 -1 -1 -1 -1 34 7551 23 4.05e+06 1.692e+06 688919. 2383.80 5.72 1.29646 1.16606 21366 134962 -1 7110 17 2315 10686 592079 112425 3.1266 3.1266 -779.621 -3.1266 0 0 845950. 2927.16 0.34 0.43 0.19 -1 -1 0.34 0.207796 0.19268 -k6_N10_40nm.xml clma.pre-vpr.blif common 61.67 vpr 99.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 378 62 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 101448 383 82 3674 4077 1 2351 843 22 22 484 clb auto 44.5 MiB 2.29 30234 398843 147564 198233 53046 88.7 MiB 6.67 0.10 8.68878 -384.052 -8.68878 8.68878 2.69 0.0155276 0.0133229 1.26339 1.07925 -1 -1 -1 -1 82 49771 43 7.2e+06 6.804e+06 2.55950e+06 5288.23 35.48 6.79195 5.74354 51036 532374 -1 43646 25 18197 79309 3810614 487367 8.62407 8.62407 -396.956 -8.62407 0 0 3.19792e+06 6607.28 1.25 2.00 0.51 -1 -1 1.25 0.806388 0.742409 -k6_N10_40nm.xml des.pre-vpr.blif common 9.87 vpr 63.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 256 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64664 256 245 954 1199 0 613 602 18 18 324 io auto 24.3 MiB 0.27 4828 140357 37125 96029 7203 63.1 MiB 0.58 0.01 4.31026 -789.244 -4.31026 nan 1.18 0.00268887 0.00247718 0.14833 0.135634 -1 -1 -1 -1 34 7705 26 4.608e+06 1.818e+06 779010. 2404.35 3.68 0.891807 0.829501 24000 152888 -1 7130 18 2525 6134 402061 81348 4.49788 nan -806.729 -4.49788 0 0 956463. 2952.05 0.41 0.38 0.14 -1 -1 0.41 0.171429 0.161993 -k6_N10_40nm.xml diffeq.pre-vpr.blif common 9.77 vpr 64.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 64 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65996 64 39 1371 1410 1 554 198 12 12 144 clb auto 25.4 MiB 0.38 3823 22662 4704 16452 1506 64.4 MiB 0.27 0.01 6.25641 -1164.67 -6.25641 6.25641 0.39 0.00226113 0.00194038 0.0990354 0.0845147 -1 -1 -1 -1 38 5271 25 1.8e+06 1.71e+06 347776. 2415.11 4.33 1.28566 1.11201 10892 69136 -1 4772 22 2865 8580 311452 52776 5.99996 5.99996 -1159.16 -5.99996 0 0 439064. 3049.06 0.16 0.26 0.06 -1 -1 0.16 0.1526 0.138145 -k6_N10_40nm.xml dsip.pre-vpr.blif common 12.42 vpr 65.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 229 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66712 229 197 1370 1567 1 538 523 16 16 256 io auto 25.8 MiB 0.56 4639 156367 46237 102482 7648 65.1 MiB 1.00 0.02 3.20322 -726.151 -3.20322 3.20322 0.86 0.00418747 0.00365041 0.259732 0.22846 -1 -1 -1 -1 34 8368 47 3.528e+06 1.746e+06 604079. 2359.69 5.60 1.32024 1.1892 18880 118149 -1 7459 13 2689 9149 571229 113616 3.28489 3.28489 -779.779 -3.28489 0 0 742044. 2898.61 0.30 0.35 0.11 -1 -1 0.30 0.147385 0.138151 -k6_N10_40nm.xml elliptic.pre-vpr.blif common 39.05 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 235 131 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 78472 131 114 3421 3535 1 1210 480 18 18 324 clb auto 35.7 MiB 1.64 11363 120672 33837 81431 5404 76.6 MiB 2.18 0.04 8.05414 -4631.43 -8.05414 8.05414 1.22 0.00849488 0.00726103 0.692001 0.597428 -1 -1 -1 -1 52 19720 37 4.608e+06 4.23e+06 1.09957e+06 3393.73 16.77 4.25257 3.62962 27876 225772 -1 17122 28 8126 36582 1833716 257901 7.83312 7.83312 -4681.92 -7.83312 0 0 1.44575e+06 4462.18 0.53 1.09 0.27 -1 -1 0.53 0.553107 0.496597 -k6_N10_40nm.xml ex1010.pre-vpr.blif common 41.78 vpr 79.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 299 10 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 81784 10 10 2659 2669 0 1414 319 20 20 400 clb auto 37.5 MiB 2.01 26899 59125 16225 41006 1894 79.9 MiB 1.87 0.03 6.8153 -65.2788 -6.8153 nan 1.86 0.0068608 0.00562071 0.52978 0.455904 -1 -1 -1 -1 90 45378 49 5.832e+06 5.382e+06 2.27845e+06 5696.13 25.05 3.88225 3.29354 44092 472493 -1 41285 21 11495 69687 3807936 447062 6.84579 nan -65.1254 -6.84579 0 0 2.84047e+06 7101.17 1.28 2.16 0.54 -1 -1 1.28 0.780219 0.707484 -k6_N10_40nm.xml ex5p.pre-vpr.blif common 9.00 vpr 62.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 8 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 63808 8 63 761 824 0 451 153 12 12 144 clb auto 23.3 MiB 0.57 4564 13650 2467 10070 1113 62.3 MiB 0.33 0.01 4.36001 -198.144 -4.36001 nan 0.63 0.00250332 0.00205267 0.106769 0.0912641 -1 -1 -1 -1 46 8116 47 1.8e+06 1.476e+06 409728. 2845.33 4.32 0.911486 0.793647 11608 81817 -1 7004 30 4945 21003 896494 141905 4.47246 nan -203.996 -4.47246 0 0 527971. 3666.47 0.17 0.60 0.08 -1 -1 0.17 0.234913 0.213184 -k6_N10_40nm.xml frisc.pre-vpr.blif common 40.55 vpr 75.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 242 20 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 77756 20 116 3175 3291 1 1258 378 18 18 324 clb auto 34.9 MiB 1.71 15482 83704 21369 56709 5626 75.9 MiB 1.70 0.02 10.0612 -5141.26 -10.0612 10.0612 1.16 0.00491127 0.00417088 0.4835 0.410195 -1 -1 -1 -1 64 24533 32 4.608e+06 4.356e+06 1.36711e+06 4219.48 18.07 3.52561 2.98385 30460 277092 -1 22374 28 8629 36312 2096962 284266 10.1175 10.1175 -5118.01 -10.1175 0 0 1.70889e+06 5274.36 1.01 0.98 0.44 -1 -1 1.01 0.438117 0.387003 -k6_N10_40nm.xml misex3.pre-vpr.blif common 7.41 vpr 62.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 86 14 -1 -1 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64336 14 14 828 842 0 506 114 12 12 144 clb auto 23.7 MiB 0.43 4946 8118 1259 6320 539 62.8 MiB 0.19 0.00 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-1 -1 -1 -1 -1 -1 -1 -1 100 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64732 14 14 828 842 0 489 128 12 12 144 clb auto 23.4 MiB 0.39 5175 7856 1075 6307 474 63.2 MiB 0.17 0.01 4.84801 -64.1454 -4.84801 nan 0.13 0.00237316 0.00211186 0.0763038 0.069521 -1 -1 -1 -1 46 7690 36 1.8e+06 1.8e+06 409728. 2845.33 1.90 0.68048 0.582561 11608 81817 -1 6920 20 4140 18396 605767 102501 4.82071 nan -63.1482 -4.82071 0 0 527971. 3666.47 0.02 0.29 0.06 -1 -1 0.02 0.12603 0.112062 + k6_N10_40nm.xml pdc.pre-vpr.blif common 21.86 vpr 80.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 332 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82088 16 40 2839 2879 0 1508 388 21 21 441 clb auto 37.7 MiB 1.17 25399 76744 19217 54467 3060 80.2 MiB 1.51 0.03 6.92036 -251.161 -6.92036 nan 0.47 0.00885769 0.00740089 0.531173 0.448728 -1 -1 -1 -1 72 40612 31 6.498e+06 5.976e+06 2.09950e+06 4760.78 11.04 2.90977 2.44288 43822 429389 -1 36688 22 12583 72460 3185853 429873 7.06044 nan -257.312 -7.06044 0 0 2.62494e+06 5952.24 0.09 1.30 0.27 -1 -1 0.09 0.47556 0.41731 + k6_N10_40nm.xml s298.pre-vpr.blif common 3.96 vpr 61.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62952 4 6 726 732 1 389 94 12 12 144 clb auto 22.2 MiB 0.25 4089 5206 723 4335 148 61.5 MiB 0.09 0.00 7.44269 -59.1085 -7.44269 7.44269 0.10 0.00104361 0.000914441 0.0377587 0.0345446 -1 -1 -1 -1 40 6786 29 1.8e+06 1.512e+06 360446. 2503.10 1.34 0.413858 0.360142 11036 71301 -1 5886 21 3075 15208 517485 86492 7.26292 7.26292 -60.1433 -7.26292 0 0 452692. 3143.70 0.01 0.25 0.06 -1 -1 0.01 0.116222 0.103786 + k6_N10_40nm.xml s38584.1.pre-vpr.blif common 25.20 vpr 84.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 404 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86316 39 304 4677 4982 1 2030 747 23 23 529 clb auto 42.7 MiB 1.01 14904 261623 79531 168959 13133 84.3 MiB 2.43 0.03 5.31651 -3386.99 -5.31651 5.31651 0.57 0.010079 0.00906179 0.841925 0.734315 -1 -1 -1 -1 38 21753 42 7.938e+06 7.272e+06 1.42597e+06 2695.60 6.41 3.52156 3.02715 41046 290405 -1 19677 23 11025 32342 1182586 226448 5.01574 5.01574 -3392.1 -5.01574 0 0 1.79789e+06 3398.65 0.07 0.91 0.22 -1 -1 0.07 0.560332 0.490747 + k6_N10_40nm.xml seq.pre-vpr.blif common 6.68 vpr 63.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65376 41 35 1006 1041 0 592 188 13 13 169 clb auto 24.2 MiB 0.53 7217 15790 2751 11594 1445 63.8 MiB 0.29 0.01 4.98507 -144.608 -4.98507 nan 0.16 0.00308253 0.00273928 0.120489 0.109161 -1 -1 -1 -1 54 11911 44 2.178e+06 2.016e+06 560467. 3316.37 3.24 0.979146 0.844173 14526 113769 -1 10428 30 5280 24638 903866 142828 4.87201 nan -144.017 -4.87201 0 0 730287. 4321.22 0.02 0.46 0.10 -1 -1 0.02 0.199563 0.175824 + k6_N10_40nm.xml spla.pre-vpr.blif common 17.67 vpr 74.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 265 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76688 16 46 2232 2278 0 1137 327 19 19 361 clb auto 33.2 MiB 0.92 17307 56627 13789 39736 3102 74.9 MiB 1.05 0.02 6.63208 -224.84 -6.63208 nan 0.37 0.00697821 0.0058582 0.391341 0.336325 -1 -1 -1 -1 60 30174 42 5.202e+06 4.77e+06 1.43744e+06 3981.82 8.84 2.3335 1.98111 32910 290117 -1 25425 24 9835 57132 2445755 336723 6.52939 nan -226.972 -6.52939 0 0 1.79849e+06 4981.96 0.06 1.13 0.23 -1 -1 0.06 0.404897 0.357661 + k6_N10_40nm.xml tseng.pre-vpr.blif common 3.61 vpr 64.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65656 52 122 1461 1583 1 500 286 13 13 169 clb auto 24.5 MiB 0.22 3158 39808 8713 28658 2437 64.1 MiB 0.20 0.00 6.15771 -1276.75 -6.15771 6.15771 0.12 0.00151949 0.00138677 0.0725931 0.0655934 -1 -1 -1 -1 26 4848 34 2.178e+06 2.016e+06 310759. 1838.81 0.73 0.389324 0.342948 11502 59218 -1 4210 17 2436 6640 243507 54081 5.71256 5.71256 -1266.26 -5.71256 0 0 383419. 2268.75 0.01 0.20 0.05 -1 -1 0.01 0.123184 0.110004 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt index f2ab28c8ba9..9c78b87cb9f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt @@ -1,17 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu -hard_fpu_arch_timing.xml bfly.v common -1 -1 -1 -1 -1 0.16 18224 1 0.05 -1 -1 31068 -1 -1 12 193 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63432 193 64 833 649 1 555 273 30 30 900 block_FPU auto 23.1 MiB 12.87 6972 77268 29980 43623 3665 61.9 MiB 0.64 0.01 2.985 -1452.65 -2.985 2.985 0.00 0.00345903 0.00320898 0.310157 0.288034 9758 17.6137 2596 4.68592 934 1040 481302 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-1 -1 0 129 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63392 129 64 769 585 1 513 197 30 30 900 block_FPU auto 22.9 MiB 12.31 6958 48902 21245 27359 298 61.9 MiB 0.54 0.01 2.985 -1455.98 -2.985 2.985 0.00 0.00319221 0.00294586 0.282301 0.261055 10003 19.5371 2642 5.16016 779 897 439553 99390 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1548.45 -2.985 -21.7856 -0.0851 0.51 -1 -1 61.9 MiB 0.13 0.339114 0.31525 61.9 MiB -1 0.74 4 -hard_fpu_arch_timing.xml fir.v common -1 -1 -1 -1 -1 0.23 18448 1 0.06 -1 -1 31448 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63824 161 32 993 808 1 589 198 32 32 1024 block_FPU auto 23.5 MiB 19.33 8696 52614 20036 29788 2790 62.3 MiB 0.52 0.00 2.985 -1388.15 -2.985 2.985 0.00 0.00236183 0.0021016 0.238946 0.215583 12400 21.0884 3199 5.44048 931 1030 627581 134171 2.063e+06 171916 2.37490e+06 2319.23 4 57140 479124 -1 2.985 2.985 -1481.02 -2.985 -38.21 -0.0851 0.58 -1 -1 62.3 MiB 0.17 0.292004 0.266051 62.3 MiB -1 1.10 5 -hard_fpu_arch_timing.xml mm3.v common -1 -1 -1 -1 -1 0.13 17448 1 0.04 -1 -1 30584 -1 -1 0 193 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 61708 193 32 545 422 1 406 228 22 22 484 block_FPU auto 21.7 MiB 5.89 4776 55212 23773 31167 272 60.3 MiB 0.43 0.00 2.985 -859.622 -2.985 2.985 0.00 0.00227966 0.00213157 0.192562 0.180241 6302 15.5605 1716 4.23704 575 575 247743 57500 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -879.413 -2.985 -11.8289 -0.0851 0.31 -1 -1 60.3 MiB 0.08 0.230754 0.216735 60.3 MiB -1 0.40 3 -hard_fpu_arch_timing.xml ode.v common -1 -1 -1 -1 -1 0.27 18856 1 0.10 -1 -1 34124 -1 -1 139 130 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 65828 130 72 1194 1103 1 572 343 19 19 361 io auto 25.3 MiB 63.68 4565 96343 31862 60407 4074 64.3 MiB 0.65 0.02 2.985 -1406.8 -2.985 2.985 0.00 0.00310122 0.00280178 0.267549 0.240869 6648 11.6427 1747 3.05954 1275 1369 363986 74305 653279 387384 795482. 2203.55 9 19802 160939 -1 2.985 2.985 -1405.3 -2.985 -52.6773 -0.0851 0.23 -1 -1 64.3 MiB 0.15 0.350981 0.317977 64.3 MiB -1 0.27 2 -hard_fpu_arch_timing.xml syn2.v common -1 -1 -1 -1 -1 0.18 17704 1 0.03 -1 -1 30688 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63032 161 128 641 490 1 475 293 30 30 900 block_FPU auto 22.9 MiB 2.22 7841 79997 33960 45061 976 61.6 MiB 0.67 0.01 2.985 -1572.64 -2.985 2.985 0.00 0.00371321 0.00348406 0.319763 0.300473 10437 22.0190 2753 5.80802 792 997 433379 92547 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1589.34 -2.985 -16.4581 -0.0851 0.53 -1 -1 61.6 MiB 0.15 0.385642 0.363691 61.6 MiB -1 0.84 4 -hard_fpu_arch_timing.xml syn7.v common -1 -1 -1 -1 -1 0.42 20548 1 0.08 -1 -1 32460 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 114764 161 128 1921 499 1 1761 309 54 54 2916 block_FPU auto 36.7 MiB 0.90 51330 112017 54453 57290 274 112.1 MiB 3.15 0.04 2.985 -8362.4 -2.985 2.985 0.00 0.0141291 0.0132401 1.6054 1.50698 67889 38.5733 17189 9.76648 4622 7614 5369001 1071099 6.08571e+06 687663 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8813.08 -2.985 -46.2947 -0.0851 1.66 -1 -1 112.1 MiB 1.35 1.95104 1.84046 112.1 MiB -1 3.28 20 - hard_fpu_arch_timing.xml bfly.v common -1 -1 -1 -1 -1 0.16 18224 1 0.05 -1 -1 31068 -1 -1 12 193 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63432 193 64 833 649 1 555 273 30 30 900 block_FPU auto 23.1 MiB 12.87 6972 77268 29980 43623 3665 61.9 MiB 0.64 0.01 2.985 -1452.65 -2.985 2.985 0.00 0.00345903 0.00320898 0.310157 0.288034 9758 17.6137 2596 4.68592 934 1040 481302 105916 1.6779e+06 165039 2.03108e+06 2256.75 7 48532 406344 -1 2.985 2.985 -1496.45 -2.985 -23.8163 -0.0851 0.54 -1 -1 61.9 MiB 0.16 0.388266 0.362244 61.9 MiB -1 0.74 4 - hard_fpu_arch_timing.xml bgm.v common -1 -1 -1 -1 -1 0.29 19040 1 0.06 -1 -1 31632 -1 -1 0 257 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 67800 257 32 1281 693 1 1054 299 38 38 1444 block_FPU auto 26.9 MiB 1.08 18110 101198 46140 54513 545 66.2 MiB 1.42 0.01 2.985 -3229.01 -2.985 2.985 0.00 0.00654702 0.00610351 0.685687 0.639812 25207 23.9383 6546 6.21652 1846 2287 1380850 300883 2.90196e+06 343832 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3437.76 -2.985 -32.8428 -0.0851 0.80 -1 -1 66.2 MiB 0.40 0.828712 0.776824 66.2 MiB -1 1.59 10 - hard_fpu_arch_timing.xml dscg.v common -1 -1 -1 -1 -1 0.18 17724 1 0.05 -1 -1 31092 -1 -1 0 129 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63392 129 64 769 585 1 513 197 30 30 900 block_FPU auto 22.9 MiB 12.31 6958 48902 21245 27359 298 61.9 MiB 0.54 0.01 2.985 -1455.98 -2.985 2.985 0.00 0.00319221 0.00294586 0.282301 0.261055 10003 19.5371 2642 5.16016 779 897 439553 99390 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1548.45 -2.985 -21.7856 -0.0851 0.51 -1 -1 61.9 MiB 0.13 0.339114 0.31525 61.9 MiB -1 0.74 4 - hard_fpu_arch_timing.xml fir.v common -1 -1 -1 -1 -1 0.23 18448 1 0.06 -1 -1 31448 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63824 161 32 993 808 1 589 198 32 32 1024 block_FPU auto 23.5 MiB 19.33 8696 52614 20036 29788 2790 62.3 MiB 0.52 0.00 2.985 -1388.15 -2.985 2.985 0.00 0.00236183 0.0021016 0.238946 0.215583 12400 21.0884 3199 5.44048 931 1030 627581 134171 2.063e+06 171916 2.37490e+06 2319.23 4 57140 479124 -1 2.985 2.985 -1481.02 -2.985 -38.21 -0.0851 0.58 -1 -1 62.3 MiB 0.17 0.292004 0.266051 62.3 MiB -1 1.10 5 - hard_fpu_arch_timing.xml mm3.v common -1 -1 -1 -1 -1 0.13 17448 1 0.04 -1 -1 30584 -1 -1 0 193 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 61708 193 32 545 422 1 406 228 22 22 484 block_FPU auto 21.7 MiB 5.89 4776 55212 23773 31167 272 60.3 MiB 0.43 0.00 2.985 -859.622 -2.985 2.985 0.00 0.00227966 0.00213157 0.192562 0.180241 6302 15.5605 1716 4.23704 575 575 247743 57500 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -879.413 -2.985 -11.8289 -0.0851 0.31 -1 -1 60.3 MiB 0.08 0.230754 0.216735 60.3 MiB -1 0.40 3 - hard_fpu_arch_timing.xml ode.v common -1 -1 -1 -1 -1 0.27 18856 1 0.10 -1 -1 34124 -1 -1 139 130 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 65828 130 72 1194 1103 1 572 343 19 19 361 io auto 25.3 MiB 63.68 4565 96343 31862 60407 4074 64.3 MiB 0.65 0.02 2.985 -1406.8 -2.985 2.985 0.00 0.00310122 0.00280178 0.267549 0.240869 6648 11.6427 1747 3.05954 1275 1369 363986 74305 653279 387384 795482. 2203.55 9 19802 160939 -1 2.985 2.985 -1405.3 -2.985 -52.6773 -0.0851 0.23 -1 -1 64.3 MiB 0.15 0.350981 0.317977 64.3 MiB -1 0.27 2 - hard_fpu_arch_timing.xml syn2.v common -1 -1 -1 -1 -1 0.18 17704 1 0.03 -1 -1 30688 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 63032 161 128 641 490 1 475 293 30 30 900 block_FPU auto 22.9 MiB 2.22 7841 79997 33960 45061 976 61.6 MiB 0.67 0.01 2.985 -1572.64 -2.985 2.985 0.00 0.00371321 0.00348406 0.319763 0.300473 10437 22.0190 2753 5.80802 792 997 433379 92547 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1589.34 -2.985 -16.4581 -0.0851 0.53 -1 -1 61.6 MiB 0.15 0.385642 0.363691 61.6 MiB -1 0.84 4 - hard_fpu_arch_timing.xml syn7.v common -1 -1 -1 -1 -1 0.42 20548 1 0.08 -1 -1 32460 -1 -1 0 161 -1 -1 success v8.0.0-10677-gf2af7ebf0 release IPO VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-11T11:34:37 betzgrp-wintermute.eecg.utoronto.ca /home/shrevena/Documents/vtr/vtr-verilog-to-routing/vtr_flow/tasks 114764 161 128 1921 499 1 1761 309 54 54 2916 block_FPU auto 36.7 MiB 0.90 51330 112017 54453 57290 274 112.1 MiB 3.15 0.04 2.985 -8362.4 -2.985 2.985 0.00 0.0141291 0.0132401 1.6054 1.50698 67889 38.5733 17189 9.76648 4622 7614 5369001 1071099 6.08571e+06 687663 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8813.08 -2.985 -46.2947 -0.0851 1.66 -1 -1 112.1 MiB 1.35 1.95104 1.84046 112.1 MiB -1 3.28 20 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu + hard_fpu_arch_timing.xml bfly.v common 10.66 vpr 62.66 MiB -1 -1 0.29 18880 1 0.04 -1 -1 31060 -1 -1 14 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64160 193 64 833 649 1 555 275 30 30 900 block_FPU auto 22.9 MiB 9.06 7227 73501 28110 42559 2832 62.7 MiB 0.24 0.00 2.985 -1449.57 -2.985 2.985 0.00 0.00129076 0.0012041 0.111382 0.10419 -1 -1 -1 -1 10011 18.0704 2627 4.74188 921 1045 352645 96816 1.6779e+06 169623 2.03108e+06 2256.75 6 48532 406344 -1 2.985 2.985 -1492.92 -2.985 -24.3711 -0.0851 0.33 -1 -1 62.7 MiB 0.08 0.141917 0.133178 62.7 MiB -1 0.09 4 + hard_fpu_arch_timing.xml bgm.v common 4.38 vpr 66.29 MiB -1 -1 0.37 19684 1 0.06 -1 -1 31568 -1 -1 0 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67880 257 32 1281 693 1 1048 299 38 38 1444 block_FPU auto 27.1 MiB 1.15 17732 96203 37615 55516 3072 66.3 MiB 0.97 0.01 2.985 -3196.19 -2.985 2.985 0.00 0.0058053 0.00549326 0.572424 0.541944 -1 -1 -1 -1 24861 23.7450 6446 6.15664 1897 2343 998279 268232 2.90196e+06 343832 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3400.32 -2.985 -32.9279 -0.0851 0.72 -1 -1 66.3 MiB 0.27 0.668829 0.633922 66.3 MiB -1 0.18 10 + hard_fpu_arch_timing.xml dscg.v common 11.83 vpr 63.13 MiB -1 -1 0.27 18916 1 0.05 -1 -1 30476 -1 -1 0 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 129 64 769 585 1 513 197 30 30 900 block_FPU auto 23.0 MiB 9.85 7095 47183 20094 26781 308 63.1 MiB 0.42 0.00 2.985 -1443.24 -2.985 2.985 0.00 0.00302745 0.00284785 0.254581 0.239617 -1 -1 -1 -1 9979 19.4902 2627 5.13086 790 910 348267 96422 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1537.32 -2.985 -21.8648 -0.0851 0.44 -1 -1 63.1 MiB 0.11 0.304162 0.286319 63.1 MiB -1 0.10 4 + hard_fpu_arch_timing.xml fir.v common 19.03 vpr 63.21 MiB -1 -1 0.34 19016 1 0.05 -1 -1 32588 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64724 161 32 993 808 1 587 198 32 32 1024 block_FPU auto 23.3 MiB 16.72 9692 44550 18401 25778 371 63.2 MiB 0.41 0.00 2.985 -1407.96 -2.985 2.985 0.00 0.00297922 0.00277214 0.239029 0.222609 -1 -1 -1 -1 12905 22.0222 3330 5.68259 990 1086 448603 120061 2.063e+06 171916 2.37490e+06 2319.23 5 57140 479124 -1 2.985 2.985 -1491.67 -2.985 -38.4653 -0.0851 0.53 -1 -1 63.2 MiB 0.13 0.291694 0.271864 63.2 MiB -1 0.12 5 + hard_fpu_arch_timing.xml mm3.v common 6.50 vpr 61.19 MiB -1 -1 0.23 18328 1 0.04 -1 -1 30736 -1 -1 0 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62656 193 32 545 422 1 386 228 22 22 484 block_FPU auto 21.8 MiB 4.95 4984 53124 22938 29850 336 61.2 MiB 0.32 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00217515 0.00206622 0.171111 0.1626 -1 -1 -1 -1 6454 16.7636 1714 4.45195 565 565 194103 53991 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.472 -2.985 -13.5705 -0.0851 0.24 -1 -1 61.2 MiB 0.07 0.203477 0.193246 61.2 MiB -1 0.05 3 + hard_fpu_arch_timing.xml ode.v common 53.14 vpr 64.66 MiB -1 -1 0.41 19816 1 0.10 -1 -1 34200 -1 -1 141 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66208 130 72 1194 1103 1 571 345 19 19 361 io auto 24.6 MiB 50.95 5001 98274 32566 61072 4636 64.7 MiB 0.54 0.01 2.985 -1384.17 -2.985 2.985 0.00 0.00308436 0.00282904 0.260751 0.239819 -1 -1 -1 -1 6737 11.8193 1762 3.09123 1249 1362 304558 77526 653279 391968 795482. 2203.55 8 19802 160939 -1 2.985 2.985 -1385.47 -2.985 -52.8417 -0.0851 0.18 -1 -1 64.7 MiB 0.13 0.330036 0.303434 64.7 MiB -1 0.04 2 + hard_fpu_arch_timing.xml syn2.v common 3.85 vpr 62.39 MiB -1 -1 0.16 18524 1 0.04 -1 -1 30832 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63892 161 128 641 490 1 475 293 30 30 900 block_FPU auto 23.1 MiB 1.75 8105 81941 35762 45750 429 62.4 MiB 0.54 0.01 2.985 -1571.9 -2.985 2.985 0.00 0.00342016 0.0032503 0.298242 0.283689 -1 -1 -1 -1 10335 21.8038 2743 5.78692 780 976 327494 85675 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1595.62 -2.985 -16.3392 -0.0851 0.44 -1 -1 62.4 MiB 0.11 0.355509 0.338332 62.4 MiB -1 0.10 4 + hard_fpu_arch_timing.xml syn7.v common 7.45 vpr 112.47 MiB -1 -1 0.45 21564 1 0.08 -1 -1 32500 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 115168 161 128 1921 499 1 1760 309 54 54 2916 block_FPU auto 37.0 MiB 0.62 44624 112017 52264 59181 572 112.5 MiB 2.20 0.02 2.985 -8100.96 -2.985 2.985 0.00 0.0120269 0.0114133 1.31427 1.24716 -1 -1 -1 -1 60108 34.1717 15324 8.71177 4214 6760 3339753 839694 6.08571e+06 687663 6.89978e+06 2366.18 9 161598 1383069 -1 2.985 2.985 -8533.86 -2.985 -46.3798 -0.0851 1.55 -1 -1 112.5 MiB 0.90 1.61708 1.53715 112.5 MiB -1 0.39 20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt index 39285b5f6fd..985745ce71c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt @@ -1,8 +1,8 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - soft_fpu_arch_timing.xml bfly.v common 40.57 yosys 122.16 MiB -1 -1 22.13 125096 23 5.62 -1 -1 41692 -1 -1 1040 193 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 85328 193 64 4025 4089 1 2736 1297 35 35 1225 clb auto 46.0 MiB 0.97 24357 83.3 MiB 3.80 0.05 12.6863 -3133.42 -12.6863 12.6863 0.19 0.00678317 0.00575525 0.583526 0.494286 43509 23481 79464 7440725 993539 2.49624e+06 2.38392e+06 2.83731e+06 2316.17 25 14.5389 14.5389 -3399.68 -14.5389 -30.6915 -0.0851 83.3 MiB 2.29 1.09901 0.94705 83.3 MiB 1.83 - soft_fpu_arch_timing.xml bgm.v common 85.62 yosys 262.74 MiB -1 -1 55.10 269048 18 13.31 -1 -1 50340 -1 -1 1412 257 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 98592 257 32 6050 6082 1 4052 1701 40 40 1600 clb auto 59.8 MiB 1.28 32465 96.3 MiB 5.79 0.04 10.1721 -4834.31 -10.1721 10.1721 0.25 0.00614799 0.00540653 0.86422 0.729823 55833 29024 89852 8145011 1111561 3.30999e+06 3.23663e+06 3.73324e+06 2333.28 24 11.3843 11.3843 -5207.55 -11.3843 -27.431 -0.0851 96.3 MiB 1.71 1.32139 1.13159 96.3 MiB 2.43 - soft_fpu_arch_timing.xml dscg.v common 33.83 yosys 120.67 MiB -1 -1 24.80 123568 25 2.07 -1 -1 41792 -1 -1 565 129 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 71128 129 64 2143 2207 1 1543 758 26 26 676 clb auto 31.6 MiB 0.51 12874 69.5 MiB 1.58 0.02 14.3664 -1690.33 -14.3664 14.3664 0.09 0.00354728 0.00307928 0.273789 0.235084 23119 13167 44172 4130151 562348 1.32031e+06 1.2951e+06 1.53374e+06 2268.84 24 15.799 15.799 -1841.77 -15.799 -8.6998 -0.0851 69.5 MiB 1.27 0.551637 0.482491 69.5 MiB 0.94 - soft_fpu_arch_timing.xml fir.v common 26.03 yosys 107.03 MiB -1 -1 20.01 109600 16 1.08 -1 -1 39144 -1 -1 470 161 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68304 161 32 2031 2063 1 1225 663 24 24 576 clb auto 29.0 MiB 0.34 6818 66.7 MiB 0.96 0.02 8.78105 -1407.83 -8.78105 8.78105 0.07 0.00263578 0.00221588 0.190077 0.16097 11091 6628 16931 1530770 210173 1.10943e+06 1.07733e+06 1.29802e+06 2253.51 29 10.2137 10.2137 -1490.23 -10.2137 -36.4317 -0.0851 66.7 MiB 0.58 0.402875 0.349509 66.7 MiB 0.78 - soft_fpu_arch_timing.xml mm3.v common 16.83 yosys 77.55 MiB -1 -1 14.00 79408 11 0.34 -1 -1 37140 -1 -1 188 193 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 60760 193 32 904 936 1 583 413 21 21 441 io auto 21.3 MiB 0.13 2803 59.3 MiB 0.33 0.01 5.82017 -484.835 -5.82017 5.82017 0.05 0.00130186 0.00114881 0.0741617 0.0644725 4633 2312 4580 414875 58859 827486 430936 981244. 2225.04 18 6.59157 6.59157 -518.556 -6.59157 -6.90646 -0.0851 59.3 MiB 0.16 0.13609 0.120573 59.3 MiB 0.51 - soft_fpu_arch_timing.xml ode.v common 41.23 yosys 125.50 MiB -1 -1 17.72 128508 24 6.58 -1 -1 47476 -1 -1 1376 130 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 95068 130 72 5235 5307 1 3591 1578 40 40 1600 clb auto 55.9 MiB 1.26 35397 92.8 MiB 5.68 0.07 13.7468 -4422.98 -13.7468 13.7468 0.24 0.00918165 0.00803446 0.859672 0.732311 61467 27802 90970 8572516 1132437 3.30999e+06 3.15411e+06 3.73324e+06 2333.28 22 15.1794 15.1794 -4765.97 -15.1794 -53.7766 -0.0851 92.8 MiB 2.72 1.52323 1.31474 92.8 MiB 2.44 - soft_fpu_arch_timing.xml syn2.v common 70.87 yosys 151.36 MiB -1 -1 23.13 154996 23 13.96 -1 -1 51820 -1 -1 2290 161 -1 -1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 131092 161 128 8356 8484 1 6201 2579 50 50 2500 clb auto 82.9 MiB 2.30 63583 126.4 MiB 14.58 0.16 13.437 -6901.96 -13.437 13.437 0.46 0.0187672 0.016783 1.78112 1.47957 112990 51030 168594 15868739 2084984 5.2812e+06 5.24911e+06 5.89298e+06 2357.19 25 14.6283 14.6283 -7454.97 -14.6283 -24.4737 -0.0851 126.4 MiB 5.44 3.18795 2.70077 126.4 MiB 4.09 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + soft_fpu_arch_timing.xml bfly.v common 41.34 parmys 121.35 MiB -1 -1 28.71 124260 23 3.25 -1 -1 39816 -1 -1 1065 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84540 193 64 3908 3972 1 2590 1322 35 35 1225 clb auto 40.9 MiB 0.92 23821 566978 183866 374301 8811 82.6 MiB 3.62 0.05 15.2252 -3632.45 -15.2252 15.2252 0.00 0.00893832 0.00809078 0.765101 0.674928 -1 -1 -1 -1 41554 16.0502 10620 4.10197 16398 55146 3818752 563046 2.49624e+06 2.44122e+06 2.83731e+06 2316.17 20 66042 566079 -1 14.3186 14.3186 -3387.7 -14.3186 -31.8712 -0.0851 0.59 -1 -1 82.6 MiB 1.30 1.1781 1.04452 82.6 MiB -1 0.14 + soft_fpu_arch_timing.xml bgm.v common 91.63 parmys 261.79 MiB -1 -1 68.05 268076 18 8.02 -1 -1 47316 -1 -1 1490 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 98376 257 32 6040 6072 1 3862 1779 41 41 1681 clb auto 52.4 MiB 1.35 32284 896104 308252 576620 11232 96.1 MiB 5.96 0.07 12.7604 -5544.74 -12.7604 12.7604 0.00 0.0121239 0.0108644 1.11649 0.963883 -1 -1 -1 -1 53705 13.9132 13764 3.56580 24580 81256 5307364 800086 3.48649e+06 3.41543e+06 3.92715e+06 2336.20 24 90666 782499 -1 12.0246 12.0246 -5156.11 -12.0246 -31.3502 -0.0851 0.78 -1 -1 96.1 MiB 1.91 1.78217 1.54405 96.1 MiB -1 0.19 + soft_fpu_arch_timing.xml dscg.v common 37.96 parmys 121.48 MiB -1 -1 31.02 124396 24 1.46 -1 -1 38668 -1 -1 602 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72036 129 64 2192 2256 1 1525 795 27 27 729 clb auto 30.2 MiB 0.54 13360 240060 66463 162314 11283 70.3 MiB 1.50 0.02 16.4736 -1891.5 -16.4736 16.4736 0.00 0.00522672 0.00478088 0.373681 0.337968 -1 -1 -1 -1 23389 15.7821 5992 4.04318 10665 36046 2530253 367157 1.43263e+06 1.37991e+06 1.65895e+06 2275.65 21 39258 331839 -1 14.938 14.938 -1781.33 -14.938 -9.29425 -0.0851 0.32 -1 -1 70.3 MiB 0.86 0.642834 0.579879 70.3 MiB -1 0.07 + soft_fpu_arch_timing.xml fir.v common 30.01 parmys 107.04 MiB -1 -1 25.31 109604 16 0.75 -1 -1 35824 -1 -1 480 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69144 161 32 2044 2076 1 1154 673 24 24 576 clb auto 27.8 MiB 0.33 7067 186397 50839 130117 5441 67.5 MiB 1.00 0.02 10.7496 -1623.35 -10.7496 10.7496 0.00 0.00400883 0.00360476 0.266889 0.238205 -1 -1 -1 -1 11039 9.58247 2844 2.46875 5647 15675 1030099 156890 1.10943e+06 1.10026e+06 1.29802e+06 2253.51 23 30996 260004 -1 10.1243 10.1243 -1523.31 -10.1243 -41.6788 -0.0851 0.25 -1 -1 67.5 MiB 0.42 0.454829 0.403412 67.5 MiB -1 0.06 + soft_fpu_arch_timing.xml mm3.v common 19.71 parmys 76.30 MiB -1 -1 17.40 78128 11 0.25 -1 -1 34080 -1 -1 188 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62248 193 32 892 924 1 553 413 21 21 441 io auto 21.0 MiB 0.15 2944 81874 21125 56255 4494 60.8 MiB 0.37 0.01 7.4944 -557.676 -7.4944 7.4944 0.00 0.00203025 0.00187301 0.114304 0.105094 -1 -1 -1 -1 4300 7.78986 1136 2.05797 2073 4078 247328 39648 827486 430936 981244. 2225.04 17 23706 196899 -1 6.6809 6.6809 -514.232 -6.6809 -6.91814 -0.0851 0.19 -1 -1 60.8 MiB 0.13 0.187463 0.170377 60.8 MiB -1 0.04 + soft_fpu_arch_timing.xml ode.v common 40.64 parmys 125.57 MiB -1 -1 23.10 128584 24 4.17 -1 -1 44228 -1 -1 1412 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 94024 130 72 5151 5223 1 3426 1614 40 40 1600 clb auto 48.4 MiB 1.33 35991 777580 261625 505362 10593 91.8 MiB 5.34 0.06 15.9431 -5264.37 -15.9431 15.9431 0.00 0.0117408 0.0100826 1.01252 0.875255 -1 -1 -1 -1 60460 17.6732 15462 4.51973 24242 84687 5987586 871715 3.30999e+06 3.23663e+06 3.73324e+06 2333.28 21 86292 744004 -1 14.8488 14.8488 -4929.15 -14.8488 -50.5031 -0.0851 0.74 -1 -1 91.8 MiB 1.94 1.5713 1.36676 91.8 MiB -1 0.19 + soft_fpu_arch_timing.xml syn2.v common 62.84 parmys 154.08 MiB -1 -1 29.55 157776 24 7.67 -1 -1 48164 -1 -1 2381 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 146376 161 128 8330 8458 1 5909 2670 51 51 2601 clb auto 69.8 MiB 2.37 66146 1576445 571349 976282 28814 142.9 MiB 12.22 0.13 17.1016 -8352.63 -17.1016 17.1016 0.00 0.0199685 0.0180821 1.87397 1.60664 -1 -1 -1 -1 113775 19.4487 28920 4.94359 45588 170928 12281742 1779631 5.50353e+06 5.45769e+06 6.13592e+06 2359.06 21 140346 1220799 -1 15.9299 15.9299 -7817.18 -15.9299 -29.0971 -0.0851 1.30 -1 -1 142.9 MiB 4.07 2.89569 2.48638 142.9 MiB -1 0.35 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt index 6e30998de45..dbe5e369b17 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt @@ -1,235 +1,235 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_14.v common 10.54 vpr 70.70 MiB 0.08 10424 -1 -1 8 0.47 -1 -1 34568 -1 -1 129 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72392 22 19 1764 1664 1 986 174 16 16 256 mult_36 auto 32.5 MiB 0.23 6911 23454 4494 16949 2011 70.7 MiB 0.38 0.01 4.33936 -1301.29 -4.33936 4.33936 0.56 0.00365899 0.00326498 0.195213 0.174646 56 12579 33 6.2557e+06 3.1391e+06 803869. 3140.11 6.06 1.35873 1.18031 23564 190428 -1 11422 16 3998 8028 649808 152476 4.21916 4.21916 -1356.04 -4.21916 0 0 987003. 3855.48 0.24 0.27 0.17 -1 -1 0.24 0.135479 0.1203 966 966 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_15.v common 18.70 vpr 71.25 MiB 0.12 10744 -1 -1 8 0.49 -1 -1 36248 -1 -1 139 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72960 22 19 1918 1801 1 1083 185 16 16 256 clb mult_36 auto 33.3 MiB 0.31 7452 24381 4617 17851 1913 71.2 MiB 0.40 0.01 4.2726 -1449.28 -4.2726 4.2726 0.57 0.00379266 0.0033986 0.199621 0.178244 58 13092 31 6.2557e+06 3.65564e+06 820238. 3204.05 13.97 1.94719 1.68393 24072 200857 -1 11442 15 3878 7716 550889 129867 4.33936 4.33936 -1521.98 -4.33936 0 0 1.02849e+06 4017.54 0.26 0.28 0.18 -1 -1 0.26 0.149226 0.132931 1047 1047 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_16.v common 20.82 vpr 71.85 MiB 0.08 10924 -1 -1 8 0.49 -1 -1 37424 -1 -1 143 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73572 22 19 1976 1859 1 1114 189 17 17 289 clb auto 33.9 MiB 0.32 7264 24037 4291 17788 1958 71.8 MiB 0.41 0.01 4.21916 -1486.51 -4.21916 4.21916 0.63 0.00489752 0.00431003 0.201025 0.178991 50 13894 29 6.55708e+06 3.70386e+06 851065. 2944.86 15.84 1.99817 1.72454 25342 195625 -1 12284 15 4638 9503 717159 167904 4.21916 4.21916 -1550.01 -4.21916 0 0 1.01866e+06 3524.77 0.26 0.29 0.17 -1 -1 0.26 0.142612 0.126662 1086 1086 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_17.v common 9.92 vpr 72.78 MiB 0.12 11700 -1 -1 8 0.62 -1 -1 36784 -1 -1 163 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74524 22 19 2278 2144 1 1240 209 17 17 289 clb auto 35.2 MiB 0.36 8060 29969 5695 21748 2526 72.8 MiB 0.47 0.01 4.45956 -1684.95 -4.45956 4.45956 0.63 0.00463111 0.0041369 0.23625 0.210005 54 15140 22 6.55708e+06 3.94496e+06 896083. 3100.63 4.55 1.53975 1.33532 26206 212621 -1 12577 16 4569 8799 640836 153828 4.21916 4.21916 -1745.34 -4.21916 0 0 1.10294e+06 3816.40 0.28 0.32 0.18 -1 -1 0.28 0.176032 0.155889 1242 1242 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_18.v common 11.28 vpr 73.71 MiB 0.09 11836 -1 -1 8 0.64 -1 -1 37796 -1 -1 168 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75484 22 19 2336 2202 1 1265 214 18 18 324 clb auto 35.8 MiB 0.40 8290 36637 7934 26298 2405 73.7 MiB 0.57 0.01 4.21916 -1744.34 -4.21916 4.21916 0.73 0.00444452 0.00396062 0.286115 0.253518 50 16367 48 7.67456e+06 4.00524e+06 975281. 3010.13 5.32 1.59346 1.38595 28904 225404 -1 13788 16 5109 10482 831833 193930 4.33936 4.33936 -1820.48 -4.33936 0 0 1.16663e+06 3600.72 0.32 0.37 0.20 -1 -1 0.32 0.182922 0.161524 1281 1281 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_19.v common 27.64 vpr 73.89 MiB 0.14 12416 -1 -1 8 0.73 -1 -1 37396 -1 -1 175 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75668 22 19 2488 2337 1 1372 222 18 18 324 clb auto 36.6 MiB 0.40 9596 39140 8295 28140 2705 73.9 MiB 0.68 0.01 4.33936 -1880.13 -4.33936 4.33936 0.80 0.0047139 0.00418558 0.324637 0.286821 54 18562 42 7.67456e+06 4.48562e+06 1.02660e+06 3168.53 21.36 2.68022 2.31611 29872 244976 -1 14749 13 5049 10006 745695 175397 4.33936 4.33936 -1903.22 -4.33936 0 0 1.26286e+06 3897.71 0.32 0.31 0.21 -1 -1 0.32 0.161915 0.144401 1360 1360 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_20.v common 12.23 vpr 74.60 MiB 0.14 12340 -1 -1 8 0.79 -1 -1 37540 -1 -1 182 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76388 22 19 2546 2395 1 1407 229 18 18 324 clb auto 37.3 MiB 0.40 9852 41529 9029 29722 2778 74.6 MiB 0.66 0.01 4.23263 -1906.98 -4.23263 4.23263 0.73 0.00510993 0.00455479 0.311577 0.274832 56 17400 27 7.67456e+06 4.57001e+06 1.05222e+06 3247.61 5.92 1.81762 1.58422 30196 251424 -1 15852 16 5369 10891 854362 201858 4.33936 4.33936 -2002.14 -4.33936 0 0 1.29075e+06 3983.80 0.34 0.40 0.22 -1 -1 0.34 0.201322 0.179277 1399 1399 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_21.v common 16.26 vpr 75.50 MiB 0.15 12828 -1 -1 8 0.89 -1 -1 37744 -1 -1 193 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77308 22 19 2735 2567 1 1516 240 19 19 361 clb auto 38.2 MiB 0.47 11409 38235 7770 28551 1914 75.5 MiB 0.63 0.01 4.57976 -2047.16 -4.57976 4.57976 0.84 0.00577536 0.00518636 0.3054 0.270886 60 19097 20 8.02416e+06 4.70262e+06 1.23460e+06 3419.94 9.34 2.14776 1.86265 34598 305437 -1 17021 13 5592 11571 878461 200428 4.45956 4.45956 -2093.27 -4.45956 0 0 1.54069e+06 4267.84 0.41 0.36 0.27 -1 -1 0.41 0.181661 0.162213 1497 1497 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_22.v common 12.01 vpr 75.86 MiB 0.14 12916 -1 -1 8 0.92 -1 -1 38120 -1 -1 200 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77680 22 19 2793 2625 1 1545 247 19 19 361 clb auto 38.7 MiB 0.43 10819 43591 9468 32068 2055 75.9 MiB 0.69 0.01 4.33936 -2094.5 -4.33936 4.33936 0.83 0.00528357 0.00468913 0.332009 0.293678 58 18949 22 8.02416e+06 4.787e+06 1.20750e+06 3344.89 5.03 1.59876 1.39152 34238 298765 -1 17036 18 6019 12139 929813 221385 4.33936 4.33936 -2185.66 -4.33936 0 0 1.51231e+06 4189.22 0.41 0.44 0.25 -1 -1 0.41 0.233865 0.207296 1536 1536 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_23.v common 12.86 vpr 76.60 MiB 0.11 13404 -1 -1 8 0.92 -1 -1 38712 -1 -1 211 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78440 22 19 2947 2762 1 1644 259 19 19 361 clb auto 39.4 MiB 0.49 11020 43159 9038 31489 2632 76.6 MiB 0.75 0.01 4.2726 -2221.58 -4.2726 4.2726 0.87 0.0059107 0.00523601 0.358623 0.318099 58 19050 20 8.02416e+06 5.3156e+06 1.20750e+06 3344.89 5.62 1.82998 1.60216 34238 298765 -1 17111 13 5734 11444 793982 193134 4.45956 4.45956 -2263.88 -4.45956 0 0 1.51231e+06 4189.22 0.41 0.40 0.26 -1 -1 0.41 0.205585 0.184619 1617 1617 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_24.v common 13.53 vpr 76.93 MiB 0.18 13496 -1 -1 8 0.95 -1 -1 38724 -1 -1 216 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78780 22 19 3005 2820 1 1676 264 19 19 361 clb auto 39.9 MiB 0.51 11788 45102 9582 33144 2376 76.9 MiB 0.77 0.01 4.33936 -2265.94 -4.33936 4.33936 0.89 0.0060117 0.00535217 0.367787 0.325894 58 20359 33 8.02416e+06 5.37588e+06 1.20750e+06 3344.89 5.91 1.94923 1.70406 34238 298765 -1 17938 13 6106 12521 945470 221782 4.33936 4.33936 -2379.04 -4.33936 0 0 1.51231e+06 4189.22 0.42 0.42 0.26 -1 -1 0.42 0.207164 0.185275 1656 1656 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_25.v common 16.78 vpr 79.07 MiB 0.16 13996 -1 -1 8 1.12 -1 -1 40320 -1 -1 231 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80972 22 19 3229 3027 1 1787 279 20 20 400 clb auto 41.1 MiB 0.55 13104 50384 10538 36503 3343 79.1 MiB 0.86 0.01 4.33936 -2497.75 -4.33936 4.33936 1.01 0.00631594 0.00563073 0.407978 0.360229 56 24126 48 1.09209e+07 5.5567e+06 1.31097e+06 3277.42 8.53 2.56516 2.25629 37530 313959 -1 21480 15 7283 15143 1320591 298085 4.33936 4.33936 -2564.15 -4.33936 0 0 1.60880e+06 4022.00 0.42 0.54 0.27 -1 -1 0.42 0.247739 0.220975 1771 1771 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_26.v common 19.25 vpr 79.34 MiB 0.18 14372 -1 -1 8 1.08 -1 -1 40560 -1 -1 237 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81244 22 19 3287 3085 1 1821 285 21 21 441 clb auto 41.4 MiB 0.56 13136 57442 13523 40914 3005 79.3 MiB 0.90 0.01 4.33936 -2504.53 -4.33936 4.33936 1.08 0.00606643 0.00535482 0.414242 0.364529 58 22683 37 1.13066e+07 5.62904e+06 1.48593e+06 3369.47 10.49 2.35823 2.04792 42062 368216 -1 20548 13 6990 14309 1055541 245303 4.21916 4.21916 -2554.32 -4.21916 0 0 1.86135e+06 4220.76 0.51 0.49 0.31 -1 -1 0.51 0.232733 0.208547 1810 1810 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_27.v common 19.01 vpr 79.30 MiB 0.15 14548 -1 -1 8 1.04 -1 -1 39364 -1 -1 251 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81208 22 19 3453 3234 1 1931 300 21 21 441 clb auto 42.4 MiB 0.57 14985 60480 13891 43297 3292 79.3 MiB 0.96 0.02 4.35283 -2683.1 -4.35283 4.35283 1.06 0.006508 0.00577071 0.447304 0.394235 58 26866 32 1.13066e+07 6.1938e+06 1.48593e+06 3369.47 10.12 2.22103 1.93376 42062 368216 -1 23239 14 7816 16183 1303787 291924 4.33936 4.33936 -2773.32 -4.33936 0 0 1.86135e+06 4220.76 0.54 0.60 0.32 -1 -1 0.54 0.286199 0.260459 1903 1903 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_28.v common 21.07 vpr 80.57 MiB 0.14 14696 -1 -1 8 1.34 -1 -1 41092 -1 -1 256 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82504 22 19 3511 3292 1 1964 305 21 21 441 clb auto 42.9 MiB 0.62 13949 56735 12285 41462 2988 80.6 MiB 0.96 0.02 4.33936 -2735.23 -4.33936 4.33936 1.10 0.00704446 0.00619059 0.437073 0.384685 64 23032 20 1.13066e+07 6.25408e+06 1.61476e+06 3661.58 11.73 2.81808 2.45166 43822 404518 -1 20960 15 6761 13901 1029805 236692 4.33936 4.33936 -2868.81 -4.33936 0 0 2.02607e+06 4594.27 0.59 0.55 0.37 -1 -1 0.59 0.291523 0.261599 1942 1942 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_29.v common 43.72 vpr 81.68 MiB 0.11 15144 -1 -1 8 1.20 -1 -1 40048 -1 -1 268 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83640 22 19 3709 3473 1 2078 318 22 22 484 clb mult_36 auto 44.3 MiB 0.60 16039 68673 16015 49006 3652 81.7 MiB 1.06 0.02 4.45956 -2880.87 -4.45956 4.45956 1.15 0.00686048 0.00606524 0.489167 0.431798 58 28453 49 1.25085e+07 6.79474e+06 1.65337e+06 3416.05 34.20 3.77322 3.27923 46570 411141 -1 24738 15 8089 16692 1363351 299594 4.45956 4.45956 -2907.33 -4.45956 0 0 2.07026e+06 4277.39 0.57 0.58 0.34 -1 -1 0.57 0.269084 0.238866 2049 2049 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_30.v common 19.05 vpr 82.44 MiB 0.15 15328 -1 -1 8 1.43 -1 -1 40280 -1 -1 274 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84420 22 19 3767 3531 1 2107 324 22 22 484 clb mult_36 auto 45.1 MiB 0.63 15345 71492 17040 50634 3818 82.4 MiB 1.15 0.02 4.33936 -2892.9 -4.33936 4.33936 1.15 0.00691652 0.00611562 0.518098 0.456256 58 27413 39 1.25085e+07 6.86707e+06 1.65337e+06 3416.05 8.83 2.77404 2.41177 46570 411141 -1 23887 38 8479 18001 1648879 434292 4.21916 4.21916 -3000.49 -4.21916 0 0 2.07026e+06 4277.39 0.57 0.99 0.35 -1 -1 0.57 0.558583 0.489165 2088 2088 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_31.v common 23.10 vpr 85.05 MiB 0.22 15676 -1 -1 8 1.39 -1 -1 41812 -1 -1 288 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87096 22 19 3928 3675 1 2213 338 22 22 484 clb mult_36 auto 45.3 MiB 0.65 16438 72074 17115 51144 3815 82.8 MiB 1.12 0.02 4.45956 -3035.76 -4.45956 4.45956 1.16 0.00842428 0.00738986 0.509085 0.449211 66 26913 16 1.25085e+07 7.03584e+06 1.84972e+06 3821.73 12.87 3.03126 2.63675 48986 463441 -1 24448 13 7560 15563 1140627 256835 4.33936 4.33936 -3082.3 -4.33936 0 0 2.30827e+06 4769.15 0.68 0.58 0.41 -1 -1 0.68 0.287148 0.25805 2176 2176 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_32.v common 41.95 vpr 83.27 MiB 0.21 15936 -1 -1 8 1.45 -1 -1 41916 -1 -1 292 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85272 22 19 3986 3733 1 2248 342 22 22 484 clb mult_36 auto 45.9 MiB 0.69 16132 74432 17571 52958 3903 83.3 MiB 1.25 0.02 4.33936 -3099.4 -4.33936 4.33936 1.20 0.00832441 0.00746229 0.553013 0.486788 56 31857 46 1.25085e+07 7.08406e+06 1.62053e+06 3348.21 31.65 4.71659 4.10469 45606 389969 -1 26896 15 9433 19525 1638672 375328 4.33936 4.33936 -3259.61 -4.33936 0 0 1.98725e+06 4105.89 0.58 0.70 0.31 -1 -1 0.58 0.308955 0.276833 2215 2215 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_33.v common 27.12 vpr 84.87 MiB 0.20 16892 -1 -1 8 1.52 -1 -1 40940 -1 -1 314 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86904 22 19 4329 4059 1 2377 365 23 23 529 clb auto 47.6 MiB 0.71 17638 86363 21629 61030 3704 84.9 MiB 1.40 0.02 4.33936 -3329.38 -4.33936 4.33936 1.33 0.00842929 0.00749515 0.624815 0.549057 56 32553 43 1.29425e+07 7.74527e+06 1.78215e+06 3368.90 15.79 3.43193 2.97782 49650 429369 -1 28679 14 9750 20297 1623196 372067 4.33936 4.33936 -3511.98 -4.33936 0 0 2.18505e+06 4130.54 0.64 0.72 0.38 -1 -1 0.64 0.329797 0.295474 2394 2394 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_34.v common 39.21 vpr 85.64 MiB 0.20 17024 -1 -1 8 1.64 -1 -1 42864 -1 -1 320 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87692 22 19 4387 4117 1 2404 371 23 23 529 clb auto 48.3 MiB 0.69 17853 80291 18434 57983 3874 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100540 22 19 4860 4556 1 2713 407 25 25 625 clb auto 51.0 MiB 0.83 21029 104390 26805 72904 4681 87.5 MiB 1.68 0.02 4.513 -3868.35 -4.513 4.513 1.70 0.00965273 0.008604 0.734399 0.645727 64 35977 33 1.55855e+07 8.63552e+06 2.32897e+06 3726.35 18.72 4.63084 4.04052 62084 585869 -1 31942 15 9860 20631 1603833 349642 4.45956 4.45956 -4006.24 -4.45956 0 0 2.92220e+06 4675.52 0.82 0.72 0.47 -1 -1 0.82 0.357199 0.317705 2704 2704 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_39.v common 24.48 vpr 92.17 MiB 0.23 18476 -1 -1 8 1.83 -1 -1 43728 -1 -1 370 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94384 22 19 5019 4698 1 2814 422 25 25 625 clb auto 51.8 MiB 0.93 21376 107998 26675 75558 5765 90.1 MiB 1.77 0.02 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0.24 19348 -1 -1 8 2.09 -1 -1 44368 -1 -1 397 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97564 22 19 5366 5028 1 2986 450 26 26 676 clb auto 53.8 MiB 0.86 22251 119337 30576 83966 4795 90.3 MiB 1.80 0.02 4.23263 -4198.35 -4.23263 4.23263 1.74 0.0101791 0.00901582 0.76676 0.671252 56 40623 46 1.89118e+07 9.53784e+06 2.31971e+06 3431.53 12.60 4.2101 3.65301 64740 561756 -1 35526 16 11590 24438 1963681 445204 4.45956 4.45956 -4499.81 -4.45956 0 0 2.84390e+06 4206.95 1.08 0.94 0.59 -1 -1 1.08 0.462596 0.415325 2990 2990 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_43.v common 36.63 vpr 106.50 MiB 0.22 19876 -1 -1 8 2.33 -1 -1 44700 -1 -1 404 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 109060 22 19 5524 5169 1 3090 457 26 26 676 clb auto 54.9 MiB 0.90 23398 130623 34411 91228 4984 92.7 MiB 2.06 0.03 4.45956 -4342.14 -4.45956 4.45956 1.83 0.0108931 0.00969226 0.874489 0.767625 60 39582 39 1.89118e+07 9.62222e+06 2.42032e+06 3580.36 21.57 5.52395 4.85172 66764 605600 -1 35437 14 11429 23247 1712213 389393 4.45956 4.45956 -4737.53 -4.45956 0 0 3.01907e+06 4466.08 0.95 0.86 0.52 -1 -1 0.95 0.4245 0.38237 3075 3075 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_44.v common 27.82 vpr 97.39 MiB 0.30 20044 -1 -1 8 2.22 -1 -1 45288 -1 -1 410 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99732 22 19 5582 5227 1 3122 463 26 26 676 clb auto 55.3 MiB 0.91 23363 127553 31863 89801 5889 93.0 MiB 2.05 0.03 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0.37 22404 -1 -1 8 3.18 -1 -1 47348 -1 -1 485 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 132504 22 19 6600 6177 1 3704 540 28 28 784 clb auto 61.2 MiB 1.11 29887 163192 43894 113647 5651 98.5 MiB 2.51 0.03 4.45956 -5273.35 -4.45956 4.45956 2.19 0.0131739 0.0114938 1.01498 0.889057 68 47406 27 2.18512e+07 1.13907e+07 3.12359e+06 3984.17 26.82 7.31251 6.40015 80408 782754 -1 43526 15 12631 27337 1955079 425942 4.45956 4.45956 -5862.66 -4.45956 0 0 3.88747e+06 4958.51 1.25 1.01 0.66 -1 -1 1.25 0.518284 0.464813 3692 3692 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 12.28 vpr 67.25 MiB 0.06 9112 -1 -1 10 0.50 -1 -1 35248 -1 -1 93 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68864 22 19 1149 1049 1 787 138 16 16 256 mult_36 auto 29.3 MiB 0.23 5353 14734 2612 11022 1100 67.2 MiB 0.27 0.01 12.8728 -438.233 -12.8728 12.8728 0.60 0.00301233 0.0027457 0.141779 0.129371 58 10212 29 6.2557e+06 2.70512e+06 820238. 3204.05 8.07 1.40181 1.23568 24072 200857 -1 9272 20 4271 8887 665232 152260 12.1591 12.1591 -509.624 -12.1591 0 0 1.02849e+06 4017.54 0.27 0.28 0.18 -1 -1 0.27 0.129279 0.115798 715 715 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_15.v common 9.05 vpr 67.98 MiB 0.11 9572 -1 -1 11 0.61 -1 -1 36132 -1 -1 106 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69616 22 19 1261 1144 1 879 152 16 16 256 mult_36 auto 30.0 MiB 0.26 6117 19592 3623 14422 1547 68.0 MiB 0.32 0.01 14.5477 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-1 128 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71072 22 19 1507 1373 1 1035 174 16 16 256 mult_36 auto 32.0 MiB 0.28 7464 21029 3707 15454 1868 69.4 MiB 0.36 0.01 14.9867 -537.872 -14.9867 14.9867 0.59 0.00395163 0.00358045 0.179772 0.163435 58 13697 35 6.2557e+06 3.52304e+06 820238. 3204.05 5.18 1.10905 0.982387 24072 200857 -1 12092 18 5182 10900 801705 187365 13.6413 13.6413 -622.575 -13.6413 0 0 1.02849e+06 4017.54 0.26 0.36 0.18 -1 -1 0.26 0.160493 0.144356 961 961 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 9.66 vpr 70.07 MiB 0.10 10332 -1 -1 11 0.71 -1 -1 36144 -1 -1 135 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71748 22 19 1596 1445 1 1100 182 16 16 256 clb mult_36 auto 32.6 MiB 0.28 7815 21297 3392 16393 1512 70.1 MiB 0.38 0.01 14.7981 -567.745 -14.7981 14.7981 0.57 0.00384762 0.00349311 0.187979 0.171004 56 15000 37 6.2557e+06 4.00342e+06 803869. 3140.11 4.70 1.20261 1.06324 23564 190428 -1 13198 19 5867 12427 977161 232477 13.6952 13.6952 -693.57 -13.6952 0 0 987003. 3855.48 0.26 0.43 0.18 -1 -1 0.26 0.177795 0.160712 1013 1013 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 11.89 vpr 70.29 MiB 0.14 10576 -1 -1 11 0.68 -1 -1 36936 -1 -1 137 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71980 22 19 1656 1505 1 1146 184 16 16 256 clb mult_36 auto 32.7 MiB 0.30 8226 19535 3061 14927 1547 70.3 MiB 0.35 0.01 14.4967 -584.138 -14.4967 14.4967 0.57 0.00393457 0.00358032 0.168607 0.15344 58 15564 50 6.2557e+06 4.02754e+06 820238. 3204.05 6.98 1.3782 1.22146 24072 200857 -1 13060 20 5925 12416 924193 221803 13.4156 13.4156 -768.957 -13.4156 0 0 1.02849e+06 4017.54 0.28 0.34 0.19 -1 -1 0.28 0.16696 0.149639 1054 1054 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_21.v common 15.54 vpr 70.82 MiB 0.09 10748 -1 -1 12 0.81 -1 -1 37008 -1 -1 145 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72520 22 19 1754 1586 1 1213 192 17 17 289 clb auto 33.6 MiB 0.30 9436 23971 4257 18177 1537 70.8 MiB 0.45 0.01 15.1206 -613.533 -15.1206 15.1206 0.65 0.00447903 0.00407881 0.226797 0.206229 60 17512 49 6.55708e+06 4.12398e+06 958460. 3316.47 10.01 1.45888 1.29374 27358 235245 -1 14560 18 6447 13271 1064829 240334 14.1746 14.1746 -764.795 -14.1746 0 0 1.19711e+06 4142.24 0.31 0.42 0.20 -1 -1 0.31 0.173969 0.156345 1115 1115 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_22.v common 11.30 vpr 71.59 MiB 0.15 10996 -1 -1 11 0.85 -1 -1 37792 -1 -1 154 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73308 22 19 1827 1659 1 1262 201 17 17 289 clb auto 34.2 MiB 0.33 9095 29013 5239 21338 2436 71.6 MiB 0.47 0.01 14.6828 -638.764 -14.6828 14.6828 0.64 0.00429262 0.00389892 0.233123 0.211587 64 16634 32 6.55708e+06 4.23247e+06 1.01866e+06 3524.77 5.32 1.32124 1.16817 28222 252754 -1 14512 23 6357 13024 1029780 236641 13.8083 13.8083 -765.715 -13.8083 0 0 1.27888e+06 4425.19 0.33 0.57 0.25 -1 -1 0.33 0.267912 0.242576 1169 1169 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_23.v common 15.76 vpr 71.86 MiB 0.14 11232 -1 -1 12 0.87 -1 -1 38128 -1 -1 157 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73580 22 19 1905 1720 1 1323 205 18 18 324 mult_36 auto 34.4 MiB 0.34 9808 34633 7458 24783 2392 71.9 MiB 0.59 0.01 14.9939 -659.479 -14.9939 14.9939 0.75 0.00453045 0.00412462 0.291424 0.264208 58 19445 41 7.67456e+06 4.66464e+06 1.07356e+06 3313.45 9.40 1.57466 1.39573 30840 265148 -1 16122 22 7808 16540 1310721 294165 14.0003 14.0003 -877.662 -14.0003 0 0 1.34501e+06 4151.27 0.37 0.54 0.24 -1 -1 0.37 0.228984 0.204045 1210 1210 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_24.v common 16.84 vpr 72.42 MiB 0.13 11360 -1 -1 12 0.93 -1 -1 36812 -1 -1 163 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74156 22 19 1979 1794 1 1362 211 18 18 324 mult_36 auto 35.0 MiB 0.36 10247 30307 5737 22712 1858 72.4 MiB 0.53 0.01 15.5582 -672.236 -15.5582 15.5582 0.77 0.00485803 0.00441306 0.256813 0.232741 64 18408 28 7.67456e+06 4.73696e+06 1.16663e+06 3600.72 10.39 2.12101 1.87481 32132 291232 -1 16259 20 7082 14613 1290097 280950 14.0222 14.0222 -882.314 -14.0222 0 0 1.46385e+06 4518.05 0.40 0.54 0.27 -1 -1 0.40 0.22467 0.202927 1265 1265 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 15.82 vpr 73.32 MiB 0.17 11668 -1 -1 12 0.98 -1 -1 37456 -1 -1 174 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75084 22 19 2073 1871 1 1415 222 18 18 324 clb mult_36 auto 35.8 MiB 0.36 10262 31759 5655 24329 1775 73.3 MiB 0.54 0.01 15.2851 -698.101 -15.2851 15.2851 0.74 0.00493404 0.00448269 0.2635 0.238323 62 19471 45 7.67456e+06 4.86957e+06 1.13028e+06 3488.51 9.42 2.10207 1.85772 31488 277500 -1 15897 19 7242 15053 992914 233872 13.8751 13.8751 -842.351 -13.8751 0 0 1.39838e+06 4315.99 0.40 0.38 0.24 -1 -1 0.40 0.19889 0.1808 1322 1322 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 17.70 vpr 73.64 MiB 0.16 11832 -1 -1 12 1.09 -1 -1 37448 -1 -1 180 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75408 22 19 2130 1928 1 1466 228 18 18 324 clb mult_36 auto 36.0 MiB 0.39 10652 35724 6736 26248 2740 73.6 MiB 0.62 0.01 15.3608 -721.142 -15.3608 15.3608 0.75 0.00597821 0.00546213 0.299863 0.271939 64 19028 28 7.67456e+06 4.9419e+06 1.16663e+06 3600.72 10.86 2.2653 1.99637 32132 291232 -1 16939 19 7400 15347 1200851 276434 14.0936 14.0936 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77720 22 19 2400 2164 1 1689 248 22 22 484 mult_36 auto 37.7 MiB 0.40 12158 39926 7813 29522 2591 75.0 MiB 0.70 0.01 14.8648 -767.523 -14.8648 14.8648 1.17 0.00572308 0.00520244 0.335179 0.302059 60 23104 32 1.25085e+07 5.95089e+06 1.69059e+06 3492.95 14.33 2.65821 2.35306 47054 420411 -1 20299 21 9082 18938 1454657 337588 13.6423 13.6423 -1032.35 -13.6423 0 0 2.10969e+06 4358.87 0.58 0.59 0.35 -1 -1 0.58 0.261257 0.233815 1537 1537 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_30.v common 21.29 vpr 75.84 MiB 0.13 12620 -1 -1 12 1.25 -1 -1 38124 -1 -1 209 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77656 22 19 2474 2238 1 1711 259 22 22 484 mult_36 auto 38.5 MiB 0.44 12757 40684 7873 30286 2525 75.8 MiB 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2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79624 22 19 2834 2564 1 1962 291 22 22 484 mult_36 auto 40.8 MiB 0.49 13536 57167 12483 41925 2759 77.8 MiB 0.93 0.01 16.4686 -958.47 -16.4686 16.4686 1.19 0.00655799 0.00594363 0.434681 0.391476 56 26290 37 1.25085e+07 6.8532e+06 1.62053e+06 3348.21 9.69 2.424 2.14289 45606 389969 -1 23558 19 10115 20843 1765620 396726 15.2737 15.2737 -1309.09 -15.2737 0 0 1.98725e+06 4105.89 0.55 0.71 0.33 -1 -1 0.55 0.295054 0.264891 1840 1840 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_35.v common 21.81 vpr 78.48 MiB 0.21 14128 -1 -1 13 1.46 -1 -1 40480 -1 -1 248 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80368 22 19 2941 2654 1 2054 299 22 22 484 mult_36 auto 41.8 MiB 0.51 15246 57242 12170 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85196 22 19 3689 3334 1 2572 370 24 24 576 mult_36 auto 46.4 MiB 0.65 18865 83971 19794 59912 4265 83.2 MiB 1.39 0.02 15.5441 -1198.02 -15.5441 15.5441 1.44 0.00874975 0.00795207 0.616877 0.549789 64 34373 50 1.51154e+07 8.57344e+06 2.13454e+06 3705.80 12.90 2.98074 2.63968 57414 536310 -1 30131 18 12902 26588 2258286 492592 14.6142 14.6142 -1654.43 -14.6142 0 0 2.67880e+06 4650.70 0.79 0.87 0.46 -1 -1 0.79 0.358025 0.321617 2415 2415 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_45.v common 32.60 vpr 91.75 MiB 0.28 16060 -1 -1 13 2.25 -1 -1 38912 -1 -1 321 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93956 22 19 3763 3391 1 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9.04176e+06 1.96475e+06 3411.02 50.72 4.39914 3.86705 55114 488114 -1 31826 21 13682 28559 2181283 495303 14.7048 14.7048 -1619.73 -14.7048 0 0 2.46106e+06 4272.68 0.71 0.97 0.39 -1 -1 0.71 0.432828 0.388718 2515 2515 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_47.v common 34.19 vpr 95.70 MiB 0.30 16696 -1 -1 13 2.35 -1 -1 42724 -1 -1 337 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98000 22 19 3983 3594 1 2790 391 24 24 576 clb mult_36 auto 48.3 MiB 0.70 20826 97563 23505 69067 4991 85.4 MiB 1.57 0.02 16.1383 -1250.84 -16.1383 16.1383 1.41 0.00962343 0.00858643 0.672502 0.597474 68 35894 26 1.51154e+07 9.21054e+06 2.25030e+06 3906.77 21.08 4.40596 3.90419 58566 560801 -1 32368 22 13885 29969 2157797 487394 14.8224 14.8224 -1676.6 -14.8224 0 0 2.80126e+06 4863.30 0.78 0.98 0.47 -1 -1 0.78 0.459592 0.412945 2616 2616 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_48.v common 24.05 vpr 87.84 MiB 0.15 16744 -1 -1 13 2.49 -1 -1 38852 -1 -1 341 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89944 22 19 4025 3636 1 2807 395 24 24 576 clb mult_36 auto 49.0 MiB 0.65 20555 85827 18761 62689 4377 85.9 MiB 1.41 0.02 15.9366 -1257.71 -15.9366 15.9366 1.41 0.00929673 0.00841654 0.600275 0.534894 66 36074 31 1.51154e+07 9.25876e+06 2.19797e+06 3815.93 11.41 3.11841 2.75444 57990 550195 -1 32231 18 13521 28658 2093839 472895 14.6727 14.6727 -1673.74 -14.6727 0 0 2.74415e+06 4764.15 0.78 0.72 0.50 -1 -1 0.78 0.332776 0.301428 2639 2639 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_49.v common 37.25 vpr 99.59 MiB 0.28 17008 -1 -1 13 2.57 -1 -1 39368 -1 -1 355 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101976 22 19 4164 3758 1 2908 410 25 25 625 clb auto 49.9 MiB 0.78 24013 87164 19079 63957 4128 86.7 MiB 1.53 0.03 16.6034 -1378.21 -16.6034 16.6034 1.65 0.0113847 0.0102893 0.659189 0.587169 74 38864 29 1.55855e+07 9.82352e+06 2.63203e+06 4211.25 23.48 4.53826 4.00027 65828 666824 -1 36038 21 13775 28917 2595162 541555 15.5436 15.5436 -1942.02 -15.5436 0 0 3.27126e+06 5234.01 0.97 1.01 0.54 -1 -1 0.97 0.381898 0.347421 2741 2741 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_50.v common 27.11 vpr 87.12 MiB 0.21 17160 -1 -1 13 2.59 -1 -1 39248 -1 -1 356 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89212 22 19 4190 3784 1 2926 411 25 25 625 clb auto 49.7 MiB 0.76 22437 93558 20689 67553 5316 86.7 MiB 1.50 0.02 16.4936 -1315.59 -16.4936 16.4936 1.59 0.00547894 0.00498528 0.640403 0.568865 66 39166 37 1.55855e+07 9.83558e+06 2.39749e+06 3835.99 12.82 3.14878 2.7644 62708 601000 -1 34785 23 14166 29888 2365680 520343 15.4749 15.4749 -1830.59 -15.4749 0 0 2.99279e+06 4788.46 0.94 1.16 0.55 -1 -1 0.94 0.542515 0.485758 2748 2748 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_51.v common 25.89 vpr 88.01 MiB 0.30 17380 -1 -1 13 2.75 -1 -1 43640 -1 -1 366 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90120 22 19 4305 3882 1 2980 421 25 25 625 clb auto 50.8 MiB 0.74 22535 99772 22908 71362 5502 87.8 MiB 1.63 0.03 16.3966 -1337.54 -16.3966 16.3966 1.58 0.0106801 0.00931618 0.693838 0.614797 66 38966 35 1.55855e+07 9.95613e+06 2.39749e+06 3835.99 11.41 3.27514 2.88885 62708 601000 -1 34679 18 14178 29765 2227761 499078 15.1266 15.1266 -2035.35 -15.1266 0 0 2.99279e+06 4788.46 0.89 0.97 0.52 -1 -1 0.89 0.436174 0.392121 2826 2826 -1 -1 -1 -1 -k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_52.v common 27.64 vpr 92.35 MiB 0.20 17548 -1 -1 13 2.75 -1 -1 39780 -1 -1 370 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94564 22 19 4363 3940 1 3039 425 25 25 625 clb auto 50.9 MiB 0.79 23857 97842 22331 71351 4160 87.9 MiB 1.71 0.02 16.7981 -1392.86 -16.7981 16.7981 1.62 0.00937252 0.0084418 0.734853 0.652986 70 40949 38 1.55855e+07 1.00044e+07 2.52006e+06 4032.10 12.89 3.29691 2.90817 64580 638411 -1 36845 20 14992 31313 2738027 581899 15.2222 15.2222 -1993.63 -15.2222 0 0 3.16512e+06 5064.19 0.94 1.13 0.54 -1 -1 0.94 0.475349 0.426546 2865 2865 -1 -1 -1 -1 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_14.v common 7.17 vpr 71.81 MiB 0.07 10472 -1 -1 1 0.25 -1 -1 35508 -1 -1 125 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73532 22 19 1974 1653 1 1039 170 16 16 256 mult_36 auto 34.2 MiB 0.37 6283 25550 5428 17285 2837 71.8 MiB 0.45 0.01 4.18011 -1206.26 -4.18011 4.18011 0.57 0.00350846 0.00313293 0.213571 0.191347 44 12375 36 6.32612e+06 3.15375e+06 649498. 2537.10 2.89 0.908391 0.79608 22336 155612 -1 8982 15 3271 4074 387555 98826 4.36136 4.36136 -1211.82 -4.36136 0 0 820238. 3204.05 0.21 0.22 0.14 -1 -1 0.21 0.128601 0.11497 955 708 247 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_15.v common 9.37 vpr 72.36 MiB 0.08 10772 -1 -1 1 0.26 -1 -1 36860 -1 -1 134 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74096 22 19 2144 1789 1 1138 180 16 16 256 clb mult_36 auto 35.1 MiB 0.36 6909 28120 5467 19449 3204 72.4 MiB 0.33 0.01 4.19358 -1335.76 -4.19358 4.19358 0.57 0.0037113 0.00333884 0.133605 0.11961 46 11544 32 6.32612e+06 3.66277e+06 684529. 2673.94 5.06 1.22954 1.06767 22592 160355 -1 9200 15 3275 3934 333576 89258 4.24116 4.24116 -1301.9 -4.24116 0 0 838722. 3276.26 0.23 0.23 0.14 -1 -1 0.23 0.139646 0.124395 1035 769 266 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_16.v common 10.35 vpr 73.17 MiB 0.07 10912 -1 -1 1 0.23 -1 -1 36864 -1 -1 139 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74924 22 19 2218 1846 1 1177 185 16 16 256 clb mult_36 auto 35.7 MiB 0.41 6963 25959 4805 17669 3485 73.2 MiB 0.45 0.01 4.07338 -1365.88 -4.07338 4.07338 0.56 0.00388045 0.00348674 0.208146 0.187017 46 13890 41 6.32612e+06 3.72556e+06 684529. 2673.94 5.69 1.29537 1.13495 22592 160355 -1 10116 19 3779 4592 448481 113412 4.24116 4.24116 -1370.82 -4.24116 0 0 838722. 3276.26 0.23 0.27 0.15 -1 -1 0.23 0.169377 0.15002 1073 788 285 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_17.v common 8.34 vpr 74.82 MiB 0.14 11732 -1 -1 1 0.25 -1 -1 36588 -1 -1 159 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76620 22 19 2536 2130 1 1298 205 17 17 289 clb auto 37.6 MiB 0.46 7620 37049 7684 25247 4118 74.8 MiB 0.62 0.01 4.42051 -1540.01 -4.42051 4.42051 0.65 0.00423609 0.00378899 0.282318 0.252374 46 13764 27 6.64007e+06 3.97672e+06 782063. 2706.10 3.04 1.04231 0.91148 25426 183746 -1 11043 17 4001 4900 453425 123152 4.24116 4.24116 -1541.83 -4.24116 0 0 958460. 3316.47 0.26 0.29 0.16 -1 -1 0.26 0.177466 0.157705 1228 924 304 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_18.v common 8.78 vpr 75.02 MiB 0.10 11952 -1 -1 1 0.31 -1 -1 37072 -1 -1 165 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76816 22 19 2610 2187 1 1336 211 17 17 289 clb auto 37.7 MiB 0.48 8349 34696 7275 23014 4407 75.0 MiB 0.58 0.01 4.13813 -1586.39 -4.13813 4.13813 0.66 0.00439442 0.00392502 0.267351 0.239362 48 14562 33 6.64007e+06 4.05207e+06 816265. 2824.45 3.48 1.13466 0.990693 25714 189529 -1 11938 15 4344 5163 568179 146907 4.36136 4.36136 -1641.57 -4.36136 0 0 986792. 3414.50 0.26 0.33 0.17 -1 -1 0.26 0.173087 0.154333 1266 943 323 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_19.v common 9.22 vpr 76.04 MiB 0.12 12208 -1 -1 1 0.32 -1 -1 36792 -1 -1 174 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77860 22 19 2778 2321 1 1434 221 18 18 324 clb auto 38.8 MiB 0.56 8435 36906 7335 26151 3420 76.0 MiB 0.62 0.01 4.18011 -1706.23 -4.18011 4.18011 0.77 0.00463437 0.00415387 0.27846 0.249498 44 15275 31 7.77114e+06 4.56109e+06 850563. 2625.19 3.39 1.13425 0.990832 28700 205432 -1 11863 18 4157 5289 458211 127186 4.36136 4.36136 -1720.9 -4.36136 0 0 1.07356e+06 3313.45 0.29 0.31 0.17 -1 -1 0.29 0.197713 0.175468 1344 1002 342 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_20.v common 10.57 vpr 76.70 MiB 0.11 12456 -1 -1 1 0.33 -1 -1 36984 -1 -1 178 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78536 22 19 2852 2378 1 1479 225 18 18 324 clb auto 39.2 MiB 0.58 8723 40581 8381 28372 3828 76.7 MiB 0.68 0.01 4.13813 -1771.41 -4.13813 4.13813 0.77 0.00494821 0.00443889 0.30125 0.269261 46 14626 20 7.77114e+06 4.61132e+06 895831. 2764.91 4.55 1.42369 1.24659 29024 211752 -1 12101 15 4346 5256 526214 143468 4.24116 4.24116 -1780.8 -4.24116 0 0 1.09776e+06 3388.15 0.30 0.31 0.19 -1 -1 0.30 0.17954 0.16092 1382 1021 361 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_21.v common 10.05 vpr 77.91 MiB 0.15 12852 -1 -1 1 0.36 -1 -1 37596 -1 -1 190 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79784 22 19 3057 2549 1 1586 237 18 18 324 clb auto 40.7 MiB 0.63 10000 39086 7340 28690 3056 77.9 MiB 0.81 0.01 4.36136 -1893.99 -4.36136 4.36136 0.82 0.005902 0.00531029 0.341896 0.304488 46 17097 24 7.77114e+06 4.76202e+06 895831. 2764.91 3.74 1.26578 1.10779 29024 211752 -1 13601 15 4515 5613 518271 136937 4.36136 4.36136 -1963.24 -4.36136 0 0 1.09776e+06 3388.15 0.29 0.31 0.18 -1 -1 0.29 0.186915 0.166708 1479 1099 380 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_22.v common 13.34 vpr 77.94 MiB 0.11 13080 -1 -1 1 0.25 -1 -1 38084 -1 -1 196 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79812 22 19 3131 2606 1 1626 243 19 19 361 clb auto 40.8 MiB 0.63 10581 47239 9889 33869 3481 77.9 MiB 0.87 0.01 4.48156 -1979.61 -4.48156 4.48156 0.90 0.00552736 0.00497025 0.378449 0.337682 48 18758 47 8.13532e+06 4.83737e+06 1.05176e+06 2913.46 6.65 1.84109 1.60475 32602 246183 -1 15477 18 5270 6461 700019 166552 4.36136 4.36136 -2014.15 -4.36136 0 0 1.27108e+06 3521.00 0.35 0.38 0.21 -1 -1 0.35 0.216509 0.191988 1517 1118 399 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_23.v common 11.22 vpr 79.36 MiB 0.16 13248 -1 -1 1 0.36 -1 -1 37868 -1 -1 206 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81260 22 19 3301 2742 1 1720 254 19 19 361 clb auto 42.2 MiB 0.60 10777 53318 12123 37751 3444 79.4 MiB 0.92 0.01 4.30038 -2073.95 -4.30038 4.30038 0.85 0.00592401 0.00523054 0.407801 0.364218 54 17563 25 8.13532e+06 5.35895e+06 1.15452e+06 3198.10 4.34 1.72645 1.50918 34042 276675 -1 14742 16 4950 6056 567418 143713 4.36136 4.36136 -2093.48 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-1 1 0.30 -1 -1 38104 -1 -1 225 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82628 22 19 3615 3005 1 1878 273 20 20 400 clb auto 43.8 MiB 0.73 12783 60453 13305 42245 4903 80.7 MiB 1.08 0.01 4.29513 -2284.67 -4.29513 4.29513 0.94 0.00615409 0.00550465 0.468509 0.418359 50 22427 38 1.10386e+07 5.59755e+06 1.21483e+06 3037.08 6.84 2.14736 1.8751 36870 282114 -1 18002 16 6329 7668 826615 201907 4.48156 4.48156 -2405 -4.48156 0 0 1.45344e+06 3633.59 0.46 0.44 0.26 -1 -1 0.46 0.240524 0.214471 1749 1293 456 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_26.v common 27.65 vpr 81.20 MiB 0.21 14084 -1 -1 1 0.44 -1 -1 38468 -1 -1 230 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83144 22 19 3689 3062 1 1918 278 20 20 400 clb auto 44.4 MiB 0.67 12259 59233 12310 41511 5412 81.2 MiB 1.01 0.01 4.13813 -2292.86 -4.13813 4.13813 0.97 0.0059514 0.00531072 0.419469 0.371454 46 22560 47 1.10386e+07 5.66034e+06 1.11552e+06 2788.80 19.94 2.92269 2.53164 36070 264401 -1 16932 14 5898 7281 710408 180437 4.36136 4.36136 -2399.27 -4.36136 0 0 1.36764e+06 3419.10 0.38 0.46 0.24 -1 -1 0.38 0.266686 0.241179 1787 1312 475 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_27.v common 38.14 vpr 82.61 MiB 0.14 14440 -1 -1 1 0.47 -1 -1 38408 -1 -1 242 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84596 22 19 3871 3210 1 2023 291 21 21 441 clb auto 45.6 MiB 0.77 12969 62951 13572 44045 5334 82.6 MiB 1.11 0.01 4.36136 -2529.89 -4.36136 4.36136 1.08 0.00661824 0.0059161 0.478655 0.426406 48 24732 39 1.14404e+07 6.20704e+06 1.29409e+06 2934.45 29.79 3.13754 2.72999 40046 303487 -1 19419 15 6942 8722 1093050 248022 4.48156 4.48156 -2651.69 -4.48156 0 0 1.56480e+06 3548.29 0.44 0.48 0.21 -1 -1 0.44 0.242647 0.21615 1879 1385 494 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_28.v common 14.38 vpr 82.73 MiB 0.19 14620 -1 -1 1 0.54 -1 -1 38548 -1 -1 247 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84716 22 19 3945 3267 1 2070 296 21 21 441 clb auto 45.8 MiB 0.77 13605 63400 13597 45154 4649 82.7 MiB 1.18 0.02 4.24116 -2495.55 -4.24116 4.24116 1.09 0.00697535 0.00626872 0.499185 0.445723 52 23436 41 1.14404e+07 6.26983e+06 1.38344e+06 3137.06 5.84 2.26323 1.98047 41366 331634 -1 18697 14 6169 7747 801288 198953 4.36136 4.36136 -2569.18 -4.36136 0 0 1.70223e+06 3859.94 0.46 0.38 0.28 -1 -1 0.46 0.213995 0.190374 1917 1404 513 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_29.v common 18.09 vpr 84.27 MiB 0.15 14936 -1 -1 1 0.52 -1 -1 39648 -1 -1 260 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86288 22 19 4159 3447 1 2186 310 22 22 484 mult_36 auto 47.3 MiB 0.79 14251 75766 16916 53468 5382 84.3 MiB 1.32 0.02 4.30038 -2650.53 -4.30038 4.30038 1.21 0.006988 0.00623253 0.5503 0.488282 48 24770 32 1.26594e+07 6.82908e+06 1.44011e+06 2975.42 9.09 2.32987 2.03802 44390 338934 -1 20456 14 6939 8707 972163 230644 4.48156 4.48156 -2836.1 -4.48156 0 0 1.74100e+06 3597.11 0.51 0.46 0.24 -1 -1 0.51 0.2421 0.216208 2023 1491 532 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_30.v common 21.30 vpr 84.31 MiB 0.19 15188 -1 -1 1 0.53 -1 -1 40780 -1 -1 265 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86336 22 19 4233 3504 1 2225 315 22 22 484 mult_36 auto 47.5 MiB 0.83 14490 83853 20335 56854 6664 84.3 MiB 1.46 0.02 4.24116 -2618.51 -4.24116 4.24116 1.24 0.00714772 0.00637711 0.605622 0.537951 50 25164 32 1.26594e+07 6.89187e+06 1.50222e+06 3103.76 11.74 2.89467 2.5294 44874 350400 -1 20610 14 7194 8993 921636 226843 4.36136 4.36136 -2766.51 -4.36136 0 0 1.79645e+06 3711.66 0.50 0.49 0.28 -1 -1 0.50 0.274395 0.24729 2061 1510 551 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_31.v common 19.45 vpr 85.30 MiB 0.14 15440 -1 -1 1 0.52 -1 -1 40928 -1 -1 276 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87344 22 19 4410 3647 1 2335 326 22 22 484 clb mult_36 auto 48.5 MiB 0.78 16122 77675 17613 54161 5901 85.3 MiB 1.36 0.02 4.36136 -2880.63 -4.36136 4.36136 1.23 0.0075266 0.00673816 0.559591 0.497527 50 27001 29 1.26594e+07 7.03001e+06 1.50222e+06 3103.76 9.88 2.41232 2.1093 44874 350400 -1 22573 15 7610 9869 1093468 253767 4.48156 4.48156 -2966.78 -4.48156 0 0 1.79645e+06 3711.66 0.58 0.52 0.31 -1 -1 0.58 0.262899 0.235664 2148 1578 570 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_32.v common 30.33 vpr 85.77 MiB 0.20 15712 -1 -1 1 0.44 -1 -1 40580 -1 -1 280 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87824 22 19 4484 3704 1 2374 330 22 22 484 clb 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1.65241e+06 3123.66 33.77 3.95648 3.4406 48882 385791 -1 23998 15 7697 10016 1012708 239734 4.48156 4.48156 -3211.65 -4.48156 0 0 1.97533e+06 3734.07 0.57 0.54 0.32 -1 -1 0.57 0.296085 0.263436 2364 1756 608 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_34.v common 16.82 vpr 88.21 MiB 0.18 16652 -1 -1 1 0.72 -1 -1 41604 -1 -1 309 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90328 22 19 4917 4086 1 2542 360 23 23 529 clb auto 51.3 MiB 0.85 16883 87400 19509 61991 5900 88.2 MiB 1.45 0.02 4.2946 -3132.19 -4.2946 4.2946 1.29 0.00788218 0.006887 0.570903 0.502905 48 29983 34 1.31115e+07 7.84042e+06 1.58369e+06 2993.75 6.73 2.19272 1.90211 48354 373213 -1 24232 15 8519 10539 1178068 279978 4.36136 4.36136 -3239.06 -4.36136 0 0 1.91452e+06 3619.14 0.54 0.55 0.30 -1 -1 0.54 0.289307 0.25688 2402 1775 627 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_35.v common 18.89 vpr 88.98 MiB 0.23 17056 -1 -1 1 0.65 -1 -1 41752 -1 -1 320 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91120 22 19 5093 4228 1 2643 371 23 23 529 clb auto 52.3 MiB 0.97 16361 88283 19281 62146 6856 89.0 MiB 1.56 0.02 4.18011 -3243.72 -4.18011 4.18011 1.43 0.0101303 0.009037 0.622098 0.552535 54 27381 34 1.31115e+07 7.97856e+06 1.73850e+06 3286.39 8.20 2.81154 2.4584 50466 419205 -1 22379 15 7580 9662 963966 246031 4.36136 4.36136 -3289.45 -4.36136 0 0 2.13727e+06 4040.20 0.64 0.58 0.34 -1 -1 0.64 0.341484 0.306495 2488 1842 646 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_36.v common 29.16 vpr 89.19 MiB 0.26 17120 -1 -1 1 0.71 -1 -1 41720 -1 -1 324 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91328 22 19 5167 4285 1 2691 375 23 23 529 clb auto 52.7 MiB 0.95 18019 98998 23016 68009 7973 89.2 MiB 1.69 0.02 4.25463 -3294.79 -4.25463 4.25463 1.31 0.00840097 0.00747584 0.671425 0.595096 56 29248 46 1.31115e+07 8.02879e+06 1.78215e+06 3368.90 18.21 4.18849 3.64695 50994 430361 -1 25192 17 8520 10780 1168967 288965 4.24116 4.24116 -3384.13 -4.24116 0 0 2.18505e+06 4130.54 0.60 0.66 0.38 -1 -1 0.60 0.36118 0.320109 2526 1861 665 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_37.v common 26.20 vpr 91.57 MiB 0.23 17756 -1 -1 1 0.69 -1 -1 40880 -1 -1 337 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93768 22 19 5380 4464 1 2808 389 24 24 576 clb mult_36 auto 53.9 MiB 1.06 18769 112490 27337 77347 7806 90.5 MiB 2.04 0.02 4.24116 -3467.58 -4.24116 4.24116 1.46 0.00907631 0.00809949 0.782821 0.686432 50 31438 37 1.52924e+07 8.58805e+06 1.78400e+06 3097.22 14.29 3.93921 3.43732 53074 415989 -1 26089 15 8677 10964 1154625 282675 4.36136 4.36136 -3530.32 -4.36136 0 0 2.13454e+06 3705.80 0.73 0.62 0.36 -1 -1 0.73 0.345649 0.311132 2631 1947 684 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_38.v common 22.31 vpr 91.45 MiB 0.17 17708 -1 -1 1 0.73 -1 -1 42384 -1 -1 343 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93644 22 19 5454 4521 1 2849 395 24 24 576 clb mult_36 auto 55.0 MiB 0.90 19940 116235 27981 79411 8843 91.4 MiB 2.02 0.02 4.36136 -3489.43 -4.36136 4.36136 1.56 0.00865726 0.0076673 0.789594 0.698073 50 33618 45 1.52924e+07 8.66339e+06 1.78400e+06 3097.22 10.80 3.19398 2.7774 53074 415989 -1 27632 15 9105 11562 1231630 291884 4.48156 4.48156 -3625.47 -4.48156 0 0 2.13454e+06 3705.80 0.60 0.62 0.28 -1 -1 0.60 0.337085 0.300387 2669 1966 703 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_39.v common 25.88 vpr 91.90 MiB 0.28 18160 -1 -1 1 0.76 -1 -1 40224 -1 -1 353 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94108 22 19 5629 4662 1 2951 405 25 25 625 clb auto 55.4 MiB 1.14 19953 114177 27339 77982 8856 91.9 MiB 1.99 0.02 4.36136 -3656.12 -4.36136 4.36136 1.69 0.0096819 0.00860995 0.788368 0.696843 50 35626 42 1.57822e+07 8.78897e+06 1.94653e+06 3114.45 13.53 3.34528 2.91404 57408 454416 -1 28298 13 9542 11975 1300975 310972 4.48156 4.48156 -3801.9 -4.48156 0 0 2.32897e+06 3726.35 0.78 0.61 0.33 -1 -1 0.78 0.323378 0.290166 2754 2032 722 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_40.v common 26.67 vpr 92.66 MiB 0.30 18280 -1 -1 1 0.77 -1 -1 42276 -1 -1 358 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94880 22 19 5703 4719 1 2994 410 25 25 625 clb auto 56.3 MiB 1.08 21027 114560 27826 78845 7889 92.7 MiB 2.12 0.02 4.24116 -3663.98 -4.24116 4.24116 1.63 0.00961592 0.0085823 0.754727 0.666265 54 36082 37 1.57822e+07 8.85176e+06 2.04878e+06 3278.05 13.97 3.29258 2.87627 59280 493784 -1 28451 13 8976 11375 1210126 295638 4.60176 4.60176 -3737.01 -4.60176 0 0 2.52006e+06 4032.10 0.74 0.60 0.40 -1 -1 0.74 0.322934 0.288973 2792 2051 741 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_41.v common 20.61 vpr 94.05 MiB 0.26 18812 -1 -1 1 0.79 -1 -1 41700 -1 -1 374 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96312 22 19 5950 4932 1 3111 427 25 25 625 clb auto 57.5 MiB 1.20 20818 125773 30837 85286 9650 94.1 MiB 2.17 0.03 4.42051 -3821.28 -4.42051 4.42051 1.63 0.00988404 0.0088336 0.857002 0.754623 52 33687 24 1.57822e+07 9.44869e+06 1.99531e+06 3192.49 6.87 2.69468 2.36476 58656 480125 -1 27916 13 8776 11804 1123040 278330 4.60176 4.60176 -3900.78 -4.60176 0 0 2.45448e+06 3927.17 0.96 0.67 0.44 -1 -1 0.96 0.380177 0.346074 2913 2153 760 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_42.v common 21.94 vpr 94.25 MiB 0.28 18964 -1 -1 1 0.87 -1 -1 42876 -1 -1 377 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96512 22 19 6024 4989 1 3151 430 25 25 625 clb auto 57.6 MiB 1.16 21903 126946 30063 87199 9684 94.2 MiB 2.26 0.03 4.36136 -3905.46 -4.36136 4.36136 1.66 0.0103375 0.00920788 0.868049 0.767092 54 34451 19 1.57822e+07 9.48637e+06 2.04878e+06 3278.05 8.66 3.34036 2.92748 59280 493784 -1 29343 13 9076 11896 1099829 264107 4.48156 4.48156 -4076.71 -4.48156 0 0 2.52006e+06 4032.10 0.77 0.60 0.42 -1 -1 0.77 0.340296 0.305387 2951 2172 779 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_43.v common 23.19 vpr 95.80 MiB 0.31 19404 -1 -1 1 0.89 -1 -1 43328 -1 -1 389 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98104 22 19 6198 5129 1 3252 442 25 25 625 clb auto 59.1 MiB 1.21 22747 131716 31686 89081 10949 95.8 MiB 2.33 0.03 4.37853 -4053.38 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4.48156 4.48156 -4398.9 -4.48156 0 0 2.70930e+06 4007.84 0.83 0.64 0.45 -1 -1 0.83 0.357413 0.31977 3073 2256 817 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_45.v common 28.04 vpr 96.83 MiB 0.32 19964 -1 -1 1 0.91 -1 -1 43712 -1 -1 407 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99156 22 19 6485 5365 1 3415 461 26 26 676 clb auto 60.4 MiB 1.17 21937 142861 34619 98677 9565 96.8 MiB 2.51 0.03 4.37853 -4161.26 -4.37853 4.37853 1.72 0.0108605 0.00967532 0.949021 0.832038 54 35587 27 1.91291e+07 1.02591e+07 2.26288e+06 3347.46 13.68 3.78755 3.32727 65792 548382 -1 29674 14 9521 12541 1199994 291317 4.60176 4.60176 -4732.88 -4.60176 0 0 2.78165e+06 4114.86 0.80 0.67 0.46 -1 -1 0.80 0.40794 0.367144 3178 2342 836 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_46.v common 50.52 vpr 97.72 MiB 0.22 20072 -1 -1 1 0.91 -1 -1 44016 -1 -1 412 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100068 22 19 6559 5422 1 3449 466 26 26 676 clb auto 60.7 MiB 1.21 23538 148558 36858 101207 10493 97.3 MiB 2.54 0.03 4.36136 -4211.81 -4.36136 4.36136 1.74 0.012603 0.01142 0.948557 0.83767 50 37784 24 1.91291e+07 1.03219e+07 2.15046e+06 3181.16 36.51 5.75007 5.01756 63768 504694 -1 31931 15 10220 12587 1272284 312759 4.48156 4.48156 -4493.44 -4.48156 0 0 2.57128e+06 3803.68 0.75 0.74 0.39 -1 -1 0.75 0.42784 0.384383 3216 2361 855 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_47.v common 23.60 vpr 99.03 MiB 0.22 20368 -1 -1 1 0.93 -1 -1 44564 -1 -1 422 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101408 22 19 6735 5564 1 3561 476 26 26 676 clb auto 62.5 MiB 1.21 24114 145322 35443 99736 10143 99.0 MiB 2.73 0.03 4.36136 -4363.73 -4.36136 4.36136 1.76 0.0129397 0.011653 1.1003 0.97872 52 40909 29 1.91291e+07 1.04475e+07 2.20423e+06 3260.69 8.77 3.41046 3.00851 65116 533202 -1 32715 14 10296 12618 1300621 315598 4.60176 4.60176 -4478.39 -4.60176 0 0 2.70930e+06 4007.84 0.98 0.71 0.46 -1 -1 0.98 0.408648 0.366685 3302 2428 874 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_48.v common 27.73 vpr 100.63 MiB 0.30 20524 -1 -1 1 0.97 -1 -1 44032 -1 -1 428 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103044 22 19 6809 5621 1 3598 482 26 26 676 clb auto 63.0 MiB 1.28 25457 151602 37795 102913 10894 98.7 MiB 2.57 0.03 4.36136 -4421.6 -4.36136 4.36136 1.76 0.0110835 0.0098763 0.963183 0.849135 54 40678 40 1.91291e+07 1.05228e+07 2.26288e+06 3347.46 13.20 4.51534 3.96596 65792 548382 -1 33773 15 10421 12979 1342589 331991 4.48156 4.48156 -4589.32 -4.48156 0 0 2.78165e+06 4114.86 0.79 0.71 0.44 -1 -1 0.79 0.406414 0.361218 3340 2447 893 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_49.v common 28.81 vpr 101.54 MiB 0.32 21104 -1 -1 1 1.05 -1 -1 44376 -1 -1 444 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103976 22 19 7094 5872 1 3718 499 27 27 729 clb auto 64.4 MiB 1.35 27242 166651 41903 114568 10180 100.2 MiB 3.09 0.03 4.48156 -4645.19 -4.48156 4.48156 1.93 0.0137483 0.0124058 1.21856 1.07489 54 44469 28 1.9669e+07 1.11198e+07 2.44988e+06 3360.60 12.93 4.26154 3.72779 70678 594165 -1 36864 15 11534 14523 1551802 366884 4.60176 4.60176 -5029.95 -4.60176 0 0 3.01106e+06 4130.40 0.86 0.80 0.49 -1 -1 0.86 0.436947 0.390212 3481 2569 912 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_50.v common 38.24 vpr 104.04 MiB 0.22 21184 -1 -1 1 0.99 -1 -1 44140 -1 -1 449 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106532 22 19 7168 5929 1 3755 504 27 27 729 clb auto 65.1 MiB 1.38 27900 166919 41558 115070 10291 101.0 MiB 3.07 0.03 4.42058 -4700.51 -4.42058 4.42058 1.95 0.0133138 0.0119708 1.19493 1.0588 54 46623 41 1.9669e+07 1.11825e+07 2.44988e+06 3360.60 22.19 5.22553 4.55891 70678 594165 -1 37253 16 11580 14881 1507663 361077 4.48156 4.48156 -4833.63 -4.48156 0 0 3.01106e+06 4130.40 0.95 0.82 0.47 -1 -1 0.95 0.462516 0.412714 3519 2588 931 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_51.v common 59.87 vpr 106.14 MiB 0.31 21572 -1 -1 1 1.08 -1 -1 44824 -1 -1 460 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 108688 22 19 7344 6071 1 3863 515 27 27 729 clb auto 65.7 MiB 1.37 26191 173807 44357 119669 9781 101.5 MiB 3.15 0.04 4.4148 -4780.65 -4.4148 4.4148 1.97 0.0143687 0.0128847 1.21421 1.07263 54 42070 24 1.9669e+07 1.13207e+07 2.44988e+06 3360.60 43.33 5.82771 5.07827 70678 594165 -1 35404 13 11033 14165 1456223 354857 4.72196 4.72196 -5030.57 -4.72196 0 0 3.01106e+06 4130.40 0.98 0.78 0.49 -1 -1 0.98 0.425101 0.38117 3605 2655 950 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_52.v common 28.61 vpr 106.45 MiB 0.25 21884 -1 -1 1 1.15 -1 -1 45220 -1 -1 465 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 109004 22 19 7418 6128 1 3909 520 27 27 729 clb auto 66.5 MiB 1.34 28280 178170 45981 119497 12692 102.4 MiB 3.22 0.04 4.37853 -4830.08 -4.37853 4.37853 1.95 0.0141499 0.0123272 1.23818 1.08169 54 45707 28 1.9669e+07 1.13835e+07 2.44988e+06 3360.60 12.27 4.30066 3.76467 70678 594165 -1 38034 16 11980 15124 1623681 386703 4.48156 4.48156 -5051.95 -4.48156 0 0 3.01106e+06 4130.40 0.84 0.80 0.46 -1 -1 0.84 0.496756 0.440935 3643 2674 969 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 9.41 vpr 67.30 MiB 0.06 9328 -1 -1 1 0.16 -1 -1 34656 -1 -1 81 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68916 22 19 1246 925 1 736 126 16 16 256 mult_36 auto 29.6 MiB 0.40 4254 18396 4205 11555 2636 67.3 MiB 0.34 0.01 8.36318 -383.367 -8.36318 8.36318 0.56 0.00278544 0.00258491 0.159571 0.146202 38 8861 34 6.32612e+06 2.6012e+06 558663. 2182.28 5.53 1.07474 0.945186 21316 135884 -1 6561 22 4832 5445 582149 154526 7.80999 7.80999 -388.43 -7.80999 0 0 744679. 2908.90 0.19 0.26 0.12 -1 -1 0.19 0.118783 0.105935 591 344 247 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_15.v common 7.62 vpr 67.93 MiB 0.07 9716 -1 -1 1 0.16 -1 -1 35136 -1 -1 86 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69556 22 19 1344 989 1 796 132 16 16 256 mult_36 auto 30.3 MiB 0.37 4680 18892 4302 11939 2651 67.9 MiB 0.37 0.01 8.43996 -390.118 -8.43996 8.43996 0.57 0.00280472 0.00258568 0.168314 0.15441 40 9059 33 6.32612e+06 3.05999e+06 583096. 2277.72 3.69 0.787018 0.698129 21572 140635 -1 7624 21 5398 6282 743093 192604 7.99439 7.99439 -467.887 -7.99439 0 0 763333. 2981.77 0.19 0.28 0.13 -1 -1 0.19 0.117461 0.104846 635 369 266 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_16.v common 22.21 vpr 68.30 MiB 0.07 9588 -1 -1 1 0.20 -1 -1 35172 -1 -1 91 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69944 22 19 1418 1046 1 833 137 16 16 256 mult_36 auto 30.8 MiB 0.46 5124 23788 5451 15273 3064 68.3 MiB 0.47 0.01 8.48338 -427.318 -8.48338 8.48338 0.59 0.00324841 0.00298687 0.205054 0.187831 40 9542 34 6.32612e+06 3.12278e+06 583096. 2277.72 17.80 1.58883 1.40324 21572 140635 -1 7989 24 5937 6919 778879 198407 8.18279 8.18279 -520.319 -8.18279 0 0 763333. 2981.77 0.19 0.33 0.13 -1 -1 0.19 0.146991 0.131238 673 388 285 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_17.v common 11.74 vpr 69.05 MiB 0.12 10252 -1 -1 1 0.22 -1 -1 35376 -1 -1 97 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70708 22 19 1518 1112 1 899 143 16 16 256 mult_36 auto 31.4 MiB 0.43 5605 24761 5724 15848 3189 69.1 MiB 0.50 0.01 9.23404 -471.583 -9.23404 9.23404 0.57 0.00299432 0.00271579 0.215328 0.196431 42 12302 48 6.32612e+06 3.19813e+06 613404. 2396.11 7.17 1.52838 1.35187 21828 146600 -1 8704 23 6699 7694 985071 246811 9.15065 9.15065 -572.903 -9.15065 0 0 784202. 3063.29 0.27 0.40 0.13 -1 -1 0.27 0.157069 0.140898 719 415 304 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_18.v common 14.27 vpr 69.80 MiB 0.10 10300 -1 -1 1 0.23 -1 -1 34916 -1 -1 102 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71472 22 19 1592 1169 1 937 148 16 16 256 mult_36 auto 32.0 MiB 0.48 5411 25954 5761 17040 3153 69.8 MiB 0.50 0.01 9.11384 -492.872 -9.11384 9.11384 0.57 0.00308504 0.00279575 0.215571 0.196214 40 10608 35 6.32612e+06 3.26092e+06 583096. 2277.72 9.65 1.42462 1.25955 21572 140635 -1 9003 23 6783 7936 948207 245104 8.48265 8.48265 -629.25 -8.48265 0 0 763333. 2981.77 0.22 0.37 0.14 -1 -1 0.22 0.155053 0.138515 757 434 323 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 11.00 vpr 70.22 MiB 0.11 10544 -1 -1 1 0.21 -1 -1 35336 -1 -1 107 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71904 22 19 1688 1231 1 998 154 16 16 256 mult_36 auto 32.6 MiB 0.51 5851 22814 4729 13760 4325 70.2 MiB 0.46 0.01 9.12484 -496.487 -9.12484 9.12484 0.56 0.00337278 0.00308981 0.204978 0.187705 46 11198 40 6.32612e+06 3.71971e+06 684529. 2673.94 6.64 1.44049 1.27621 22592 160355 -1 8482 21 5296 6099 654272 170198 8.26205 8.26205 -572.735 -8.26205 0 0 838722. 3276.26 0.21 0.29 0.11 -1 -1 0.21 0.143728 0.128598 799 457 342 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 12.00 vpr 70.56 MiB 0.08 10640 -1 -1 1 0.25 -1 -1 35548 -1 -1 112 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72256 22 19 1762 1288 1 1033 159 16 16 256 mult_36 auto 32.8 MiB 0.48 6825 22089 4646 13915 3528 70.6 MiB 0.47 0.01 9.16401 -519.117 -9.16401 9.16401 0.56 0.00360731 0.00330817 0.190943 0.174072 50 11241 25 6.32612e+06 3.7825e+06 744679. 2908.90 7.42 1.37001 1.20992 23104 171162 -1 9261 21 5709 6587 736555 189282 8.39745 8.39745 -613.624 -8.39745 0 0 891356. 3481.86 0.24 0.34 0.17 -1 -1 0.24 0.158795 0.142393 837 476 361 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_21.v common 10.24 vpr 70.94 MiB 0.09 10924 -1 -1 1 0.23 -1 -1 35780 -1 -1 119 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72640 22 19 1859 1351 1 1097 166 16 16 256 mult_36 auto 33.3 MiB 0.47 6666 26158 5203 16523 4432 70.9 MiB 0.50 0.01 9.03763 -508.506 -9.03763 9.03763 0.56 0.00365336 0.00334877 0.220005 0.200745 48 12141 45 6.32612e+06 3.8704e+06 714410. 2790.66 5.70 1.21186 1.07324 22848 165380 -1 9960 23 6766 7896 953019 239000 8.21605 8.21605 -705.722 -8.21605 0 0 863353. 3372.47 0.22 0.38 0.16 -1 -1 0.22 0.175403 0.156387 880 500 380 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_22.v common 8.72 vpr 71.55 MiB 0.14 11048 -1 -1 1 0.26 -1 -1 35832 -1 -1 123 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73272 22 19 1933 1408 1 1134 170 16 16 256 mult_36 auto 33.8 MiB 0.52 7313 28370 5828 17736 4806 71.6 MiB 0.56 0.01 9.17501 -549.932 -9.17501 9.17501 0.56 0.00368249 0.0033307 0.236244 0.214884 48 12035 28 6.32612e+06 3.92063e+06 714410. 2790.66 3.90 0.984652 0.872973 22848 165380 -1 10062 23 6419 7390 836835 213069 8.51065 8.51065 -667.103 -8.51065 0 0 863353. 3372.47 0.23 0.38 0.16 -1 -1 0.23 0.181923 0.162592 918 519 399 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_23.v common 13.10 vpr 71.78 MiB 0.12 11476 -1 -1 1 0.26 -1 -1 36084 -1 -1 131 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73504 22 19 2031 1472 1 1198 179 18 18 324 mult_36 auto 34.2 MiB 0.61 7550 30419 6455 19369 4595 71.8 MiB 0.62 0.01 9.12001 -583.855 -9.12001 9.12001 0.73 0.00393783 0.00359825 0.259055 0.235968 48 12630 26 7.77114e+06 4.4171e+06 935225. 2886.50 7.41 1.66175 1.4664 29348 218440 -1 10831 21 6820 7945 915173 231648 8.49665 8.49665 -783.026 -8.49665 0 0 1.13028e+06 3488.51 0.31 0.42 0.21 -1 -1 0.31 0.196924 0.173911 962 544 418 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_24.v common 14.69 vpr 72.13 MiB 0.09 11404 -1 -1 1 0.26 -1 -1 36260 -1 -1 136 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73860 22 19 2105 1529 1 1235 184 18 18 324 mult_36 auto 34.9 MiB 0.58 7661 37317 8501 24959 3857 72.1 MiB 0.69 0.01 9.10913 -586.392 -9.10913 9.10913 0.75 0.00385424 0.00348189 0.294439 0.266977 48 13133 26 7.77114e+06 4.47989e+06 935225. 2886.50 8.93 1.94041 1.70952 29348 218440 -1 10908 23 7434 8576 948645 234568 8.58465 8.58465 -791.233 -8.58465 0 0 1.13028e+06 3488.51 0.30 0.42 0.19 -1 -1 0.30 0.198405 0.177356 1000 563 437 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 10.98 vpr 72.92 MiB 0.13 11880 -1 -1 1 0.24 -1 -1 36524 -1 -1 141 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74672 22 19 2201 1591 1 1295 189 18 18 324 mult_36 auto 35.6 MiB 0.65 7882 35419 7795 23110 4514 72.9 MiB 0.75 0.01 9.0476 -626.573 -9.0476 9.0476 0.76 0.00401564 0.00365488 0.307124 0.279188 46 14895 28 7.77114e+06 4.54268e+06 895831. 2764.91 5.23 1.29314 1.14623 29024 211752 -1 11428 21 6952 8164 847241 222680 8.28945 8.28945 -792.599 -8.28945 0 0 1.09776e+06 3388.15 0.29 0.38 0.19 -1 -1 0.29 0.187225 0.167354 1042 586 456 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 14.27 vpr 73.07 MiB 0.16 11928 -1 -1 1 0.33 -1 -1 37424 -1 -1 145 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74820 22 19 2275 1648 1 1331 193 18 18 324 mult_36 auto 35.9 MiB 0.64 8270 37512 8174 25127 4211 73.1 MiB 0.74 0.01 9.15301 -640.754 -9.15301 9.15301 0.75 0.00418134 0.00380681 0.302948 0.275287 48 14431 26 7.77114e+06 4.59291e+06 935225. 2886.50 8.14 1.80477 1.59081 29348 218440 -1 12124 23 9127 10596 1176912 285820 8.54065 8.54065 -814.155 -8.54065 0 0 1.13028e+06 3488.51 0.34 0.52 0.20 -1 -1 0.34 0.226656 0.202872 1080 605 475 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_27.v common 16.96 vpr 73.94 MiB 0.16 12168 -1 -1 1 0.33 -1 -1 36860 -1 -1 153 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75712 22 19 2385 1724 1 1408 202 18 18 324 mult_36 auto 36.6 MiB 0.62 9475 39274 8633 24027 6614 73.9 MiB 0.80 0.01 9.16401 -680.51 -9.16401 9.16401 0.79 0.00432941 0.00393962 0.337033 0.306189 54 16614 36 7.77114e+06 5.08937e+06 1.02660e+06 3168.53 10.75 2.19661 1.93908 30640 245540 -1 13208 20 7860 9445 1117978 264377 8.41125 8.41125 -880.793 -8.41125 0 0 1.26286e+06 3897.71 0.33 0.42 0.21 -1 -1 0.33 0.191053 0.170746 1136 642 494 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_28.v common 11.57 vpr 74.54 MiB 0.18 12280 -1 -1 1 0.26 -1 -1 36736 -1 -1 158 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76324 22 19 2459 1781 1 1444 207 18 18 324 mult_36 auto 37.0 MiB 0.76 8909 41211 9001 25741 6469 74.5 MiB 0.81 0.01 9.14684 -663.352 -9.14684 9.14684 0.79 0.00460207 0.00411187 0.323378 0.293345 46 16563 50 7.77114e+06 5.15216e+06 895831. 2764.91 5.19 1.42025 1.25683 29024 211752 -1 12815 21 8674 9947 1180543 313346 8.80125 8.80125 -858.702 -8.80125 0 0 1.09776e+06 3388.15 0.29 0.48 0.18 -1 -1 0.29 0.209869 0.187449 1174 661 513 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_29.v common 19.37 vpr 74.96 MiB 0.18 12660 -1 -1 1 0.34 -1 -1 37108 -1 -1 165 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76756 22 19 2565 1853 1 1517 215 22 22 484 mult_36 auto 37.6 MiB 0.76 9695 50369 11832 33775 4762 75.0 MiB 1.05 0.01 9.39824 -758.644 -9.39824 9.39824 1.22 0.0048153 0.00437802 0.403953 0.3667 44 19021 30 1.26594e+07 5.63607e+06 1.30964e+06 2705.88 11.40 2.24831 1.98778 43422 318546 -1 14146 23 8551 9980 1131104 280459 8.63965 8.63965 -1048.26 -8.63965 0 0 1.65337e+06 3416.05 0.47 0.53 0.27 -1 -1 0.47 0.25129 0.224571 1226 694 532 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_30.v common 46.46 vpr 75.68 MiB 0.13 12644 -1 -1 1 0.25 -1 -1 37348 -1 -1 170 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77492 22 19 2639 1910 1 1554 220 22 22 484 mult_36 auto 38.2 MiB 0.83 9525 45967 10375 31456 4136 75.7 MiB 0.98 0.01 9.332 -761.848 -9.332 9.332 1.27 0.00495473 0.00451634 0.392015 0.355908 40 18870 42 1.26594e+07 5.69886e+06 1.17677e+06 2431.33 38.65 2.72081 2.40169 41974 287914 -1 15646 19 10618 12587 1630390 401109 8.82305 8.82305 -1060.29 -8.82305 0 0 1.53957e+06 3180.94 0.43 0.56 0.18 -1 -1 0.43 0.20758 0.185629 1264 713 551 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_31.v common 14.59 vpr 75.85 MiB 0.10 12888 -1 -1 1 0.39 -1 -1 37480 -1 -1 177 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77668 22 19 2744 1981 1 1626 227 22 22 484 mult_36 auto 38.5 MiB 0.79 10029 50743 11223 34192 5328 75.8 MiB 1.02 0.01 9.332 -743.867 -9.332 9.332 1.29 0.00285428 0.00261476 0.411716 0.373589 44 19607 46 1.26594e+07 5.78677e+06 1.30964e+06 2705.88 6.46 1.62768 1.44317 43422 318546 -1 14760 21 8812 10635 1193110 306240 8.51565 8.51565 -997.056 -8.51565 0 0 1.65337e+06 3416.05 0.47 0.51 0.28 -1 -1 0.47 0.239315 0.214108 1315 745 570 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_32.v common 20.57 vpr 76.41 MiB 0.20 13016 -1 -1 1 0.37 -1 -1 37008 -1 -1 181 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78240 22 19 2818 2038 1 1662 231 22 22 484 mult_36 auto 39.1 MiB 0.84 10896 62535 16168 40587 5780 76.4 MiB 1.32 0.02 9.51844 -833.689 -9.51844 9.51844 1.17 0.00567558 0.0051011 0.507219 0.459742 46 19729 33 1.26594e+07 5.837e+06 1.37878e+06 2848.72 12.02 2.45886 2.17829 43906 328446 -1 15857 23 10062 11624 1282729 313572 8.31125 8.31125 -1223.57 -8.31125 0 0 1.69059e+06 3492.95 0.48 0.55 0.30 -1 -1 0.48 0.256887 0.228971 1353 764 589 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_33.v common 42.72 vpr 76.81 MiB 0.20 13632 -1 -1 1 0.28 -1 -1 37428 -1 -1 189 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78656 22 19 2923 2109 1 1730 240 22 22 484 mult_36 auto 39.7 MiB 0.84 11006 63565 15479 41766 6320 76.8 MiB 1.25 0.01 10.0899 -813.568 -10.0899 10.0899 1.21 0.00518259 0.00469824 0.489613 0.442392 44 22012 50 1.26594e+07 6.33346e+06 1.30964e+06 2705.88 34.19 2.93242 2.58393 43422 318546 -1 16383 23 12263 14060 1788436 435492 9.31331 9.31331 -1098.11 -9.31331 0 0 1.65337e+06 3416.05 0.48 0.67 0.28 -1 -1 0.48 0.271858 0.242511 1404 796 608 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_34.v common 23.80 vpr 77.41 MiB 0.20 13712 -1 -1 1 0.40 -1 -1 37740 -1 -1 194 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79264 22 19 2997 2166 1 1769 245 22 22 484 mult_36 auto 40.1 MiB 1.12 11467 56929 13204 37063 6662 77.4 MiB 1.16 0.01 9.84947 -801.897 -9.84947 9.84947 1.23 0.00550201 0.00500599 0.449134 0.405926 46 23369 48 1.26594e+07 6.39625e+06 1.37878e+06 2848.72 14.79 2.70665 2.3907 43906 328446 -1 16588 23 11553 13716 1515832 373082 9.23591 9.23591 -1123.07 -9.23591 0 0 1.69059e+06 3492.95 0.48 0.73 0.29 -1 -1 0.48 0.297688 0.267246 1442 815 627 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_35.v common 18.97 vpr 78.42 MiB 0.19 14032 -1 -1 1 0.42 -1 -1 37924 -1 -1 200 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80300 22 19 3101 2236 1 1838 251 22 22 484 mult_36 auto 41.0 MiB 1.06 11980 57994 13001 38956 6037 78.4 MiB 1.22 0.02 10.4246 -898.797 -10.4246 10.4246 1.48 0.0061833 0.00566496 0.467701 0.424377 46 22305 40 1.26594e+07 6.4716e+06 1.37878e+06 2848.72 9.73 1.90829 1.69402 43906 328446 -1 17462 19 9824 11939 1348912 334590 9.59651 9.59651 -1262.04 -9.59651 0 0 1.69059e+06 3492.95 0.46 0.53 0.29 -1 -1 0.46 0.230592 0.206289 1492 846 646 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_36.v common 17.38 vpr 78.79 MiB 0.22 14132 -1 -1 1 0.41 -1 -1 37988 -1 -1 204 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80684 22 19 3175 2293 1 1872 255 22 22 484 mult_36 auto 41.3 MiB 1.17 11366 60855 13639 40637 6579 78.8 MiB 1.21 0.02 10.2398 -852.171 -10.2398 10.2398 1.18 0.00553478 0.00500054 0.457669 0.413833 48 20735 33 1.26594e+07 6.52183e+06 1.44011e+06 2975.42 8.52 2.04069 1.81415 44390 338934 -1 16863 23 10639 12310 1484249 366742 9.42731 9.42731 -1124.46 -9.42731 0 0 1.74100e+06 3597.11 0.48 0.58 0.29 -1 -1 0.48 0.268926 0.2395 1530 865 665 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_37.v common 25.75 vpr 79.31 MiB 0.25 14440 -1 -1 1 0.47 -1 -1 37420 -1 -1 211 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81216 22 19 3280 2364 1 1945 263 24 24 576 mult_36 auto 42.3 MiB 1.15 12736 63413 14509 42506 6398 79.3 MiB 1.40 0.02 10.3609 -909.644 -10.3609 10.3609 1.63 0.00777899 0.00697982 0.548709 0.497288 48 22784 34 1.52924e+07 7.00574e+06 1.71014e+06 2969.00 15.49 2.97976 2.63549 52498 402441 -1 18388 22 10953 12996 1615157 387443 9.53551 9.53551 -1204.08 -9.53551 0 0 2.06880e+06 3591.66 0.62 0.65 0.35 -1 -1 0.62 0.284875 0.25441 1581 897 684 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_38.v common 21.35 vpr 79.64 MiB 0.16 14468 -1 -1 1 0.48 -1 -1 37924 -1 -1 216 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81556 22 19 3354 2421 1 1981 268 24 24 576 mult_36 auto 42.8 MiB 1.30 13069 66719 15235 45868 5616 79.6 MiB 1.39 0.02 9.9525 -910.496 -9.9525 9.9525 1.46 0.00636589 0.00580294 0.514272 0.463865 44 26849 47 1.52924e+07 7.06853e+06 1.55518e+06 2699.97 11.22 2.20563 1.95256 51346 378163 -1 19312 24 12866 15131 1925109 470482 9.60091 9.60091 -1238.65 -9.60091 0 0 1.96475e+06 3411.02 0.55 0.70 0.30 -1 -1 0.55 0.295828 0.263378 1619 916 703 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_39.v common 16.77 vpr 80.21 MiB 0.21 14716 -1 -1 1 0.49 -1 -1 38280 -1 -1 223 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82140 22 19 3457 2490 1 2052 275 24 24 576 mult_36 auto 43.2 MiB 1.22 13656 73501 17416 50143 5942 80.2 MiB 1.62 0.02 10.0727 -966.849 -10.0727 10.0727 1.44 0.00654031 0.00595441 0.621855 0.561075 46 23538 32 1.52924e+07 7.15643e+06 1.63708e+06 2842.15 6.70 1.88873 1.67432 51922 389946 -1 18838 23 10601 12759 1435807 370600 8.95151 8.95151 -1160.49 -8.95151 0 0 2.00908e+06 3487.99 0.57 0.69 0.23 -1 -1 0.57 0.331688 0.297995 1668 946 722 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_40.v common 21.71 vpr 80.70 MiB 0.17 14852 -1 -1 1 0.46 -1 -1 38748 -1 -1 228 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82636 22 19 3531 2547 1 2089 280 24 24 576 mult_36 auto 43.6 MiB 1.40 13045 78055 20225 49115 8715 80.7 MiB 1.53 0.02 9.95249 -1011.72 -9.95249 9.95249 1.45 0.0065844 0.00598886 0.59874 0.538194 46 24015 38 1.52924e+07 7.21922e+06 1.63708e+06 2842.15 11.30 2.16095 1.91139 51922 389946 -1 18582 26 11805 14295 1481227 365944 8.90771 8.90771 -1456.6 -8.90771 0 0 2.00908e+06 3487.99 0.59 0.71 0.29 -1 -1 0.59 0.349879 0.311755 1706 965 741 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_41.v common 22.34 vpr 81.34 MiB 0.25 15324 -1 -1 1 0.59 -1 -1 37992 -1 -1 234 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83292 22 19 3634 2616 1 2155 287 24 24 576 mult_36 auto 44.4 MiB 1.34 13626 81643 18980 54154 8509 81.3 MiB 1.76 0.02 10.2807 -1100.54 -10.2807 10.2807 1.64 0.00589193 0.00531161 0.641657 0.582472 48 24099 30 1.52924e+07 7.69057e+06 1.71014e+06 2969.00 11.28 2.30878 2.05025 52498 402441 -1 19745 21 10698 12698 1556800 373550 9.35911 9.35911 -1273.87 -9.35911 0 0 2.06880e+06 3591.66 0.58 0.64 0.34 -1 -1 0.58 0.296748 0.265201 1755 995 760 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_42.v common 26.53 vpr 81.88 MiB 0.19 15376 -1 -1 1 0.51 -1 -1 38272 -1 -1 239 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83848 22 19 3708 2673 1 2193 292 24 24 576 mult_36 auto 44.8 MiB 1.41 14431 72892 16198 51073 5621 81.9 MiB 1.77 0.02 10.1929 -992.819 -10.1929 10.1929 1.57 0.00635968 0.00581533 0.574831 0.514396 48 25902 39 1.52924e+07 7.75336e+06 1.71014e+06 2969.00 15.17 3.18975 2.81988 52498 402441 -1 20831 21 12944 15314 1869342 457103 9.58971 9.58971 -1252.11 -9.58971 0 0 2.06880e+06 3591.66 0.64 0.79 0.37 -1 -1 0.64 0.333755 0.299406 1793 1014 779 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_43.v common 20.91 vpr 82.54 MiB 0.14 15612 -1 -1 1 0.53 -1 -1 38816 -1 -1 245 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84520 22 19 3810 2741 1 2260 298 24 24 576 mult_36 auto 45.3 MiB 1.35 14165 81888 20044 54601 7243 82.5 MiB 1.81 0.03 10.1328 -1049.12 -10.1328 10.1328 1.56 0.00741441 0.00659365 0.662329 0.59364 46 27674 49 1.52924e+07 7.82871e+06 1.63708e+06 2842.15 9.61 2.43495 2.15978 51922 389946 -1 20484 24 13292 15374 1707658 435292 9.19011 9.19011 -1651.37 -9.19011 0 0 2.00908e+06 3487.99 0.58 0.79 0.29 -1 -1 0.58 0.365312 0.326451 1841 1043 798 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_44.v common 71.92 vpr 82.65 MiB 0.22 15704 -1 -1 1 0.56 -1 -1 38420 -1 -1 250 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84636 22 19 3884 2798 1 2296 303 24 24 576 mult_36 auto 45.4 MiB 1.53 14946 80646 18903 52810 8933 82.7 MiB 1.73 0.02 9.99493 -1033.19 -9.99493 9.99493 1.55 0.00737401 0.00661175 0.630908 0.568308 48 27278 40 1.52924e+07 7.8915e+06 1.71014e+06 2969.00 60.53 4.224 3.7203 52498 402441 -1 22061 23 14612 17263 2051107 497730 9.31511 9.31511 -1517.68 -9.31511 0 0 2.06880e+06 3591.66 0.60 0.83 0.34 -1 -1 0.60 0.353811 0.314744 1879 1062 817 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_45.v common 19.49 vpr 83.04 MiB 0.26 15944 -1 -1 1 0.60 -1 -1 40472 -1 -1 257 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85032 22 19 3989 2869 1 2368 311 24 24 576 mult_36 auto 46.0 MiB 1.40 16964 75074 16987 50636 7451 83.0 MiB 1.59 0.02 10.3131 -1048.02 -10.3131 10.3131 1.52 0.00784933 0.00716328 0.580129 0.52297 48 28860 31 1.52924e+07 8.37541e+06 1.71014e+06 2969.00 8.09 2.10725 1.8649 52498 402441 -1 23894 23 12966 15711 2070445 493094 9.73871 9.73871 -1579.52 -9.73871 0 0 2.06880e+06 3591.66 0.58 0.76 0.37 -1 -1 0.58 0.33325 0.296675 1930 1094 836 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_46.v common 22.02 vpr 83.42 MiB 0.27 16056 -1 -1 1 0.58 -1 -1 40536 -1 -1 261 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85424 22 19 4063 2926 1 2404 315 24 24 576 mult_36 auto 46.3 MiB 1.67 15692 88137 21521 56647 9969 83.4 MiB 1.75 0.02 9.95249 -1107.23 -9.95249 9.95249 1.49 0.00859715 0.00777619 0.658305 0.593526 54 26619 49 1.52924e+07 8.42564e+06 1.87785e+06 3260.16 10.01 2.74176 2.43271 54798 452027 -1 21115 25 12793 15079 1570956 397175 9.08891 9.08891 -1436.28 -9.08891 0 0 2.31032e+06 4010.97 0.65 0.77 0.42 -1 -1 0.65 0.388572 0.345487 1968 1113 855 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_47.v common 24.10 vpr 84.30 MiB 0.26 16620 -1 -1 1 0.44 -1 -1 40800 -1 -1 268 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86324 22 19 4167 2996 1 2473 322 24 24 576 mult_36 auto 47.3 MiB 1.15 15910 88562 20878 57457 10227 84.3 MiB 1.83 0.02 10.0899 -1142.01 -10.0899 10.0899 1.50 0.00778185 0.0070779 0.652391 0.587128 50 27180 34 1.52924e+07 8.51354e+06 1.78400e+06 3097.22 12.92 2.60385 2.30211 53074 415989 -1 22519 23 12297 14952 1649666 414573 9.24691 9.24691 -1519.04 -9.24691 0 0 2.13454e+06 3705.80 0.61 0.78 0.35 -1 -1 0.61 0.379489 0.338212 2018 1144 874 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_48.v common 19.62 vpr 84.32 MiB 0.24 16492 -1 -1 1 0.62 -1 -1 40916 -1 -1 273 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86348 22 19 4241 3053 1 2509 327 24 24 576 mult_36 auto 47.4 MiB 1.38 16487 93785 22388 64524 6873 84.3 MiB 1.86 0.02 10.5535 -1144.3 -10.5535 10.5535 1.46 0.00701064 0.0063265 0.618906 0.556033 48 28818 32 1.52924e+07 8.57633e+06 1.71014e+06 2969.00 8.35 2.29073 2.04076 52498 402441 -1 24059 23 12093 14580 1751508 427964 10.3207 10.3207 -1752.01 -10.3207 0 0 2.06880e+06 3591.66 0.70 0.70 0.33 -1 -1 0.70 0.318799 0.289487 2056 1163 893 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_49.v common 23.58 vpr 84.68 MiB 0.33 16980 -1 -1 1 0.61 -1 -1 41100 -1 -1 279 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86712 22 19 4346 3124 1 2580 334 24 24 576 mult_36 auto 47.9 MiB 1.53 16418 98764 23499 65407 9858 84.7 MiB 2.11 0.02 10.0121 -1103.23 -10.0121 10.0121 1.51 0.00801433 0.0072699 0.739201 0.661626 48 28351 48 1.52924e+07 9.04768e+06 1.71014e+06 2969.00 11.34 2.93392 2.59947 52498 402441 -1 24128 20 15119 18240 2121135 532072 9.54451 9.54451 -1898.86 -9.54451 0 0 2.06880e+06 3591.66 0.62 0.85 0.34 -1 -1 0.62 0.358724 0.321338 2107 1195 912 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_50.v common 21.90 vpr 85.40 MiB 0.17 17136 -1 -1 1 0.64 -1 -1 40976 -1 -1 284 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87452 22 19 4420 3181 1 2615 339 24 24 576 mult_36 auto 48.5 MiB 1.60 17962 88914 19616 60588 8710 85.4 MiB 1.92 0.03 10.2463 -1217.9 -10.2463 10.2463 1.43 0.00802952 0.00727944 0.649197 0.583734 52 30590 30 1.52924e+07 9.11047e+06 1.82869e+06 3174.81 9.79 2.66483 2.36444 54222 439550 -1 24692 22 14714 17386 2038106 506700 9.42751 9.42751 -1884.23 -9.42751 0 0 2.25030e+06 3906.77 0.74 0.91 0.41 -1 -1 0.74 0.403763 0.368433 2145 1214 931 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_51.v common 30.19 vpr 85.87 MiB 0.20 17368 -1 -1 1 0.65 -1 -1 41140 -1 -1 292 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87932 22 19 4524 3251 1 2687 347 24 24 576 mult_36 auto 48.9 MiB 1.71 17584 90479 20112 60343 10024 85.9 MiB 1.88 0.03 10.1323 -1257.51 -10.1323 10.1323 1.41 0.00828558 0.00749981 0.650201 0.58338 54 30742 41 1.52924e+07 9.21094e+06 1.87785e+06 3260.16 17.90 3.45437 3.05274 54798 452027 -1 24323 24 12811 15116 1754918 426147 9.61671 9.61671 -2019.82 -9.61671 0 0 2.31032e+06 4010.97 0.76 0.86 0.38 -1 -1 0.76 0.434004 0.388012 2195 1245 950 19 0 0 -k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_52.v common 24.08 vpr 86.49 MiB 0.29 17524 -1 -1 1 0.59 -1 -1 39328 -1 -1 296 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88564 22 19 4598 3308 1 2721 351 24 24 576 mult_36 auto 49.6 MiB 1.38 17233 94363 21503 64446 8414 86.5 MiB 1.99 0.03 10.4246 -1286.45 -10.4246 10.4246 1.46 0.00842922 0.00765206 0.674663 0.606068 50 29595 50 1.52924e+07 9.26117e+06 1.78400e+06 3097.22 11.90 3.04331 2.69276 53074 415989 -1 24350 23 14468 16947 2000437 496448 9.61971 9.61971 -1721.97 -9.61971 0 0 2.13454e+06 3705.80 0.89 0.81 0.41 -1 -1 0.89 0.393047 0.353185 2233 1264 969 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_14.v common 13.99 vpr 71.68 MiB 0.06 10360 -1 -1 1 0.26 -1 -1 35432 -1 -1 123 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73404 22 19 1974 1653 1 1039 168 16 16 256 mult_36 auto 34.2 MiB 1.71 6084 26559 5485 17904 3170 71.7 MiB 0.45 0.01 4.07137 -1184.46 -4.07137 4.07137 0.56 0.00386419 0.0035194 0.214571 0.193058 40 11804 49 6.34292e+06 3.14339e+06 583096. 2277.72 8.15 1.68742 1.4728 21572 140635 -1 9984 21 4134 4929 581328 151853 4.48156 4.48156 -1220.21 -4.48156 0 0 763333. 2981.77 0.21 0.33 0.14 -1 -1 0.21 0.188958 0.168721 953 708 247 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_15.v common 13.35 vpr 72.60 MiB 0.08 10804 -1 -1 1 0.24 -1 -1 36924 -1 -1 132 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74340 22 19 2144 1789 1 1138 178 16 16 256 clb mult_36 auto 35.2 MiB 1.79 6845 29178 5734 19784 3660 72.6 MiB 0.50 0.01 4.13443 -1312.79 -4.13443 4.13443 0.56 0.00395181 0.00358259 0.243092 0.21955 44 12842 28 6.34292e+06 3.6535e+06 649498. 2537.10 7.35 1.51796 1.33002 22336 155612 -1 9870 14 3634 4364 464801 122306 4.24116 4.24116 -1341.45 -4.24116 0 0 820238. 3204.05 0.22 0.25 0.12 -1 -1 0.22 0.143265 0.129136 1033 769 266 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_16.v common 8.94 vpr 72.88 MiB 0.12 10984 -1 -1 1 0.25 -1 -1 36852 -1 -1 137 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74632 22 19 2218 1846 1 1177 183 16 16 256 clb mult_36 auto 35.6 MiB 2.08 7131 32361 6636 21461 4264 72.9 MiB 0.55 0.01 4.24116 -1381.33 -4.24116 4.24116 0.58 0.00386192 0.00347919 0.254067 0.228151 46 12387 24 6.34292e+06 3.71689e+06 684529. 2673.94 2.56 0.873502 0.767796 22592 160355 -1 9850 14 3563 4257 399452 105344 4.24116 4.24116 -1382.06 -4.24116 0 0 838722. 3276.26 0.21 0.23 0.15 -1 -1 0.21 0.133813 0.119563 1071 788 285 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_17.v common 10.12 vpr 75.05 MiB 0.10 11836 -1 -1 1 0.30 -1 -1 36744 -1 -1 157 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76848 22 19 2536 2130 1 1298 203 17 17 289 clb auto 37.7 MiB 2.30 7990 29407 5457 21306 2644 75.0 MiB 0.50 0.01 4.48156 -1537.29 -4.48156 4.48156 0.64 0.00430613 0.00385143 0.230555 0.20626 46 15105 26 6.65987e+06 3.97045e+06 782063. 2706.10 3.11 1.02124 0.89176 25426 183746 -1 11140 13 4183 5041 445642 117624 4.36136 4.36136 -1531.19 -4.36136 0 0 958460. 3316.47 0.25 0.31 0.16 -1 -1 0.25 0.181249 0.165655 1226 924 304 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_18.v common 10.00 vpr 75.36 MiB 0.12 11868 -1 -1 1 0.31 -1 -1 37216 -1 -1 163 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77172 22 19 2610 2187 1 1336 209 17 17 289 clb auto 37.9 MiB 2.21 8155 36789 7305 26033 3451 75.4 MiB 0.50 0.01 4.05473 -1593.4 -4.05473 4.05473 0.64 0.00204187 0.00181336 0.205703 0.183114 48 15307 35 6.65987e+06 4.04651e+06 816265. 2824.45 3.10 0.995261 0.867823 25714 189529 -1 12228 16 4558 5382 598643 148707 4.24116 4.24116 -1683.87 -4.24116 0 0 986792. 3414.50 0.26 0.30 0.17 -1 -1 0.26 0.169811 0.15093 1264 943 323 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_19.v common 19.99 vpr 76.09 MiB 0.10 12172 -1 -1 1 0.34 -1 -1 36796 -1 -1 172 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77916 22 19 2778 2321 1 1434 219 18 18 324 clb auto 39.2 MiB 2.49 8731 36464 7395 26087 2982 76.1 MiB 0.61 0.01 4.24116 -1720.94 -4.24116 4.24116 0.73 0.00509493 0.00450297 0.279768 0.250014 44 16662 42 7.79418e+06 4.55662e+06 850563. 2625.19 12.37 2.27729 1.98592 28700 205432 -1 12706 14 4544 5587 531680 141034 4.24116 4.24116 -1760.33 -4.24116 0 0 1.07356e+06 3313.45 0.30 0.31 0.18 -1 -1 0.30 0.173921 0.155689 1342 1002 342 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_20.v common 12.38 vpr 76.71 MiB 0.17 12368 -1 -1 1 0.34 -1 -1 36952 -1 -1 176 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78552 22 19 2852 2378 1 1479 223 18 18 324 clb auto 39.8 MiB 2.45 9149 36727 6960 26660 3107 76.7 MiB 0.64 0.01 4.17493 -1790.89 -4.17493 4.17493 0.77 0.00476988 0.00427466 0.281251 0.25121 46 15963 21 7.79418e+06 4.60733e+06 895831. 2764.91 4.53 1.36531 1.18775 29024 211752 -1 13130 14 4664 5572 585274 152661 4.36136 4.36136 -1839.76 -4.36136 0 0 1.09776e+06 3388.15 0.29 0.31 0.18 -1 -1 0.29 0.16464 0.147225 1380 1021 361 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_21.v common 13.46 vpr 77.67 MiB 0.13 12896 -1 -1 1 0.35 -1 -1 38016 -1 -1 188 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79536 22 19 3057 2549 1 1586 235 18 18 324 clb auto 40.8 MiB 2.76 9903 45123 9529 32094 3500 77.7 MiB 0.76 0.01 4.25463 -1905.93 -4.25463 4.25463 0.75 0.00498986 0.0044505 0.338263 0.301731 46 17948 30 7.79418e+06 4.75946e+06 895831. 2764.91 5.01 1.49883 1.31763 29024 211752 -1 13855 14 5092 6144 628537 161536 4.36136 4.36136 -2028.43 -4.36136 0 0 1.09776e+06 3388.15 0.29 0.32 0.17 -1 -1 0.29 0.179308 0.160203 1477 1099 380 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_22.v common 18.07 vpr 78.16 MiB 0.13 12828 -1 -1 1 0.35 -1 -1 37944 -1 -1 194 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80032 22 19 3131 2606 1 1626 241 19 19 361 clb auto 41.4 MiB 2.84 10286 47428 9839 33939 3650 78.2 MiB 0.84 0.01 4.24116 -1964.7 -4.24116 4.24116 0.84 0.00515519 0.00460612 0.374874 0.334519 48 18602 34 8.16184e+06 4.83553e+06 1.05176e+06 2913.46 9.15 2.16239 1.89086 32602 246183 -1 15049 16 5468 6655 767404 181797 4.24116 4.24116 -1987.18 -4.24116 0 0 1.27108e+06 3521.00 0.34 0.37 0.21 -1 -1 0.34 0.197316 0.175297 1515 1118 399 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_23.v common 14.48 vpr 79.21 MiB 0.16 13236 -1 -1 1 0.36 -1 -1 37880 -1 -1 204 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81112 22 19 3301 2742 1 1720 252 19 19 361 clb auto 42.1 MiB 2.94 11043 52722 11417 37077 4228 79.2 MiB 0.96 0.01 4.12096 -2024.58 -4.12096 4.12096 0.84 0.00592097 0.00532352 0.426861 0.380863 50 18333 39 8.16184e+06 5.35831e+06 1.09718e+06 3039.29 5.13 1.91612 1.67794 32962 254619 -1 15633 15 5503 6537 715495 175652 4.36136 4.36136 -2095.67 -4.36136 0 0 1.31179e+06 3633.76 0.43 0.44 0.21 -1 -1 0.43 0.258958 0.236943 1595 1179 418 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_24.v common 17.69 vpr 79.93 MiB 0.18 13436 -1 -1 1 0.38 -1 -1 38112 -1 -1 209 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81848 22 19 3375 2799 1 1765 257 19 19 361 clb auto 42.7 MiB 3.14 10750 45953 8990 33234 3729 79.9 MiB 0.78 0.01 4.17493 -2082.77 -4.17493 4.17493 0.83 0.00572618 0.00512497 0.333878 0.297631 50 19942 42 8.16184e+06 5.4217e+06 1.09718e+06 3039.29 8.20 1.98948 1.74691 32962 254619 -1 15531 18 5893 7110 826640 196272 4.48156 4.48156 -2097.91 -4.48156 0 0 1.31179e+06 3633.76 0.35 0.41 0.23 -1 -1 0.35 0.232604 0.206131 1633 1198 437 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_25.v common 19.32 vpr 80.93 MiB 0.09 13904 -1 -1 1 0.41 -1 -1 38040 -1 -1 223 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82876 22 19 3615 3005 1 1878 271 20 20 400 clb auto 43.8 MiB 3.29 11843 54583 11378 38149 5056 80.9 MiB 0.91 0.01 4.18011 -2275.57 -4.18011 4.18011 0.99 0.0059378 0.00528452 0.392642 0.348871 50 19676 18 1.10667e+07 5.59919e+06 1.21483e+06 3037.08 9.37 2.3373 2.05364 36870 282114 -1 16952 16 6065 7149 736369 184136 4.36136 4.36136 -2393.56 -4.36136 0 0 1.45344e+06 3633.59 0.39 0.38 0.24 -1 -1 0.39 0.221589 0.196726 1747 1293 456 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_26.v common 15.55 vpr 81.50 MiB 0.10 14064 -1 -1 1 0.42 -1 -1 38312 -1 -1 228 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83456 22 19 3689 3062 1 1918 276 20 20 400 clb auto 44.8 MiB 3.39 12415 59544 13159 41333 5052 81.5 MiB 1.03 0.02 4.13813 -2248.17 -4.13813 4.13813 0.94 0.00636596 0.00571336 0.441584 0.393961 48 22522 44 1.10667e+07 5.66258e+06 1.16517e+06 2912.92 5.28 1.89176 1.66089 36470 272802 -1 17889 14 6502 7743 857384 212074 4.36136 4.36136 -2389.08 -4.36136 0 0 1.40818e+06 3520.44 0.42 0.40 0.25 -1 -1 0.42 0.215312 0.194032 1785 1312 475 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_27.v common 22.10 vpr 82.62 MiB 0.14 14320 -1 -1 1 0.43 -1 -1 38328 -1 -1 240 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84604 22 19 3871 3210 1 2023 289 21 21 441 clb auto 45.5 MiB 3.59 13091 69049 15421 48905 4723 82.6 MiB 1.17 0.02 4.25833 -2439.76 -4.25833 4.25833 1.04 0.00662048 0.00586304 0.484025 0.429075 50 22955 23 1.14723e+07 6.21072e+06 1.34972e+06 3060.59 10.90 2.78183 2.45578 40486 313801 -1 19085 17 6693 8122 872684 214863 4.36136 4.36136 -2497.47 -4.36136 0 0 1.61476e+06 3661.58 0.44 0.45 0.25 -1 -1 0.44 0.256917 0.228658 1877 1385 494 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_28.v common 18.55 vpr 83.02 MiB 0.18 14580 -1 -1 1 0.52 -1 -1 38388 -1 -1 245 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85016 22 19 3945 3267 1 2070 294 21 21 441 clb auto 46.1 MiB 3.68 13787 70638 15611 48908 6119 83.0 MiB 1.24 0.02 4.18011 -2457.52 -4.18011 4.18011 1.06 0.0074756 0.006569 0.530694 0.471761 50 23792 26 1.14723e+07 6.27411e+06 1.34972e+06 3060.59 7.01 2.15928 1.89132 40486 313801 -1 19707 15 6833 8556 909227 220592 4.36136 4.36136 -2566.1 -4.36136 0 0 1.61476e+06 3661.58 0.45 0.42 0.25 -1 -1 0.45 0.231815 0.206025 1915 1404 513 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_29.v common 31.29 vpr 84.27 MiB 0.19 15128 -1 -1 1 0.54 -1 -1 39544 -1 -1 258 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86292 22 19 4159 3447 1 2186 308 22 22 484 mult_36 auto 47.4 MiB 3.84 14540 75116 16849 52375 5892 84.3 MiB 1.25 0.02 4.48156 -2570.01 -4.48156 4.48156 1.17 0.00688567 0.00616168 0.52709 0.468722 50 23434 22 1.26954e+07 6.83492e+06 1.50222e+06 3103.76 19.22 3.03941 2.64267 44874 350400 -1 20303 14 6789 8219 816835 204141 4.48156 4.48156 -2692.11 -4.48156 0 0 1.79645e+06 3711.66 0.51 0.43 0.30 -1 -1 0.51 0.249086 0.222942 2021 1491 532 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_30.v common 19.90 vpr 84.84 MiB 0.20 15240 -1 -1 1 0.52 -1 -1 40812 -1 -1 263 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86880 22 19 4233 3504 1 2225 313 22 22 484 mult_36 auto 48.0 MiB 3.96 14345 72529 15646 51039 5844 84.8 MiB 1.22 0.02 4.29513 -2641.58 -4.29513 4.29513 1.15 0.00705696 0.00626798 0.507139 0.45077 48 25057 33 1.26954e+07 6.89831e+06 1.44011e+06 2975.42 7.55 2.3246 2.02616 44390 338934 -1 20617 16 7249 9020 909338 222155 4.48156 4.48156 -2910.31 -4.48156 0 0 1.74100e+06 3597.11 0.56 0.49 0.29 -1 -1 0.56 0.277592 0.247925 2059 1510 551 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_31.v common 26.91 vpr 85.89 MiB 0.17 15576 -1 -1 1 0.57 -1 -1 40948 -1 -1 274 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87948 22 19 4410 3647 1 2335 324 22 22 484 clb mult_36 auto 49.0 MiB 4.10 14627 81500 18211 56732 6557 85.9 MiB 1.36 0.02 4.48156 -2763.28 -4.48156 4.48156 1.17 0.00738142 0.0064759 0.546542 0.485598 54 24724 32 1.26954e+07 7.03777e+06 1.58090e+06 3266.32 13.87 3.49276 3.07371 46322 380746 -1 20211 16 6937 8304 881095 215583 4.48156 4.48156 -2824.86 -4.48156 0 0 1.94386e+06 4016.24 0.75 0.50 0.38 -1 -1 0.75 0.291696 0.260883 2146 1578 570 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_32.v common 18.88 vpr 86.39 MiB 0.21 15748 -1 -1 1 0.57 -1 -1 40676 -1 -1 278 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88460 22 19 4484 3704 1 2374 328 22 22 484 clb mult_36 auto 49.4 MiB 4.21 15540 78298 18108 54278 5912 86.4 MiB 1.37 0.02 4.24116 -2782.8 -4.24116 4.24116 1.18 0.00850778 0.00767123 0.580402 0.51799 48 26921 28 1.26954e+07 7.08848e+06 1.44011e+06 2975.42 6.06 2.09126 1.83654 44390 338934 -1 22311 13 7902 9623 980518 241405 4.48156 4.48156 -2896.93 -4.48156 0 0 1.74100e+06 3597.11 0.50 0.47 0.31 -1 -1 0.50 0.244366 0.218501 2184 1597 589 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_33.v common 20.43 vpr 87.84 MiB 0.18 16488 -1 -1 1 0.61 -1 -1 41520 -1 -1 302 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89948 22 19 4843 4029 1 2501 353 23 23 529 clb auto 51.3 MiB 4.44 17435 87643 19607 61599 6437 87.8 MiB 1.47 0.01 4.24116 -3073.8 -4.24116 4.24116 1.40 0.00437909 0.00392859 0.602393 0.533154 50 29482 39 1.31518e+07 7.78876e+06 1.65241e+06 3123.66 6.51 2.45162 2.13701 48882 385791 -1 24265 14 8069 9691 993548 240146 4.36136 4.36136 -3116.31 -4.36136 0 0 1.97533e+06 3734.07 0.60 0.53 0.37 -1 -1 0.60 0.293733 0.261277 2362 1756 608 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_34.v common 23.61 vpr 88.46 MiB 0.12 16748 -1 -1 1 0.62 -1 -1 41616 -1 -1 308 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90580 22 19 4917 4086 1 2542 359 23 23 529 clb auto 51.8 MiB 4.42 16896 87059 18935 61744 6380 88.5 MiB 1.56 0.02 4.48156 -3114.12 -4.48156 4.48156 1.32 0.00762155 0.00676444 0.636308 0.56748 50 30043 27 1.31518e+07 7.86482e+06 1.65241e+06 3123.66 9.44 2.60169 2.26752 48882 385791 -1 24344 14 8758 10802 1224972 286268 4.60176 4.60176 -3387.39 -4.60176 0 0 1.97533e+06 3734.07 0.56 0.56 0.37 -1 -1 0.56 0.286044 0.255012 2401 1775 627 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_35.v common 42.49 vpr 89.30 MiB 0.25 17244 -1 -1 1 0.65 -1 -1 41768 -1 -1 319 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91440 22 19 5093 4228 1 2643 370 23 23 529 clb auto 52.6 MiB 4.59 18051 89279 20131 63728 5420 89.3 MiB 1.53 0.03 4.37483 -3218.94 -4.37483 4.37483 1.28 0.0115723 0.0106977 0.611601 0.540946 50 30668 35 1.31518e+07 8.00428e+06 1.65241e+06 3123.66 28.07 3.81148 3.33209 48882 385791 -1 25188 17 8575 10282 1105084 272137 4.48156 4.48156 -3354.12 -4.48156 0 0 1.97533e+06 3734.07 0.57 0.64 0.31 -1 -1 0.57 0.36502 0.32385 2487 1842 646 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_36.v common 42.13 vpr 89.86 MiB 0.24 17224 -1 -1 1 0.58 -1 -1 41708 -1 -1 323 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92020 22 19 5167 4285 1 2691 374 23 23 529 clb auto 53.3 MiB 4.79 17780 96011 21980 67780 6251 89.9 MiB 1.63 0.02 4.48156 -3272.89 -4.48156 4.48156 1.27 0.00902501 0.00810883 0.636019 0.564686 50 31361 46 1.31518e+07 8.05499e+06 1.65241e+06 3123.66 27.54 4.02566 3.48344 48882 385791 -1 25174 17 9093 11307 1257811 296331 4.36136 4.36136 -3536.95 -4.36136 0 0 1.97533e+06 3734.07 0.65 0.70 0.32 -1 -1 0.65 0.394101 0.352154 2525 1861 665 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_37.v common 22.69 vpr 91.00 MiB 0.28 17624 -1 -1 1 0.67 -1 -1 40876 -1 -1 336 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93188 22 19 5380 4464 1 2808 388 24 24 576 mult_36 auto 54.4 MiB 4.95 18000 106438 25977 73150 7311 91.0 MiB 1.93 0.02 4.36136 -3470.71 -4.36136 4.36136 1.62 0.00921082 0.00823912 0.767144 0.678016 48 30066 22 1.53347e+07 8.61581e+06 1.71014e+06 2969.00 6.75 2.50437 2.1985 52498 402441 -1 25768 15 8689 10479 1086200 257350 4.60176 4.60176 -3539.87 -4.60176 0 0 2.06880e+06 3591.66 0.59 0.57 0.34 -1 -1 0.59 0.325227 0.290089 2630 1947 684 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_38.v common 29.23 vpr 91.32 MiB 0.27 17876 -1 -1 1 0.76 -1 -1 42228 -1 -1 342 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93512 22 19 5454 4521 1 2849 394 24 24 576 clb mult_36 auto 55.5 MiB 4.99 18144 115834 28131 77060 10643 91.3 MiB 1.97 0.02 4.24116 -3379.88 -4.24116 4.24116 1.45 0.00923439 0.00823115 0.799143 0.708981 50 29652 34 1.53347e+07 8.69188e+06 1.78400e+06 3097.22 13.48 3.83727 3.35876 53074 415989 -1 25288 17 8636 10670 1032084 260041 4.36136 4.36136 -3563.7 -4.36136 0 0 2.13454e+06 3705.80 0.60 0.62 0.34 -1 -1 0.60 0.370192 0.325926 2668 1966 703 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_39.v common 23.74 vpr 92.36 MiB 0.22 18152 -1 -1 1 0.66 -1 -1 40208 -1 -1 352 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94576 22 19 5629 4662 1 2951 404 24 24 576 clb mult_36 auto 56.4 MiB 5.14 21626 118272 28657 79200 10415 92.4 MiB 2.06 0.02 4.48156 -3617.12 -4.48156 4.48156 1.45 0.0096086 0.00860047 0.824292 0.731809 52 37764 38 1.53347e+07 8.81866e+06 1.82869e+06 3174.81 7.59 2.73664 2.40506 54222 439550 -1 29338 14 9216 11739 1241818 290722 4.72196 4.72196 -3919.7 -4.72196 0 0 2.25030e+06 3906.77 0.67 0.65 0.37 -1 -1 0.67 0.353944 0.318368 2753 2032 722 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_40.v common 26.05 vpr 92.76 MiB 0.19 18376 -1 -1 1 0.67 -1 -1 42312 -1 -1 357 22 0 11 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94988 22 19 5703 4719 1 2994 409 25 25 625 clb auto 57.0 MiB 5.29 20955 115701 27338 79764 8599 92.8 MiB 1.92 0.02 4.30038 -3680.46 -4.30038 4.30038 1.49 0.00891788 0.00790718 0.732142 0.646044 52 36068 32 1.58291e+07 8.88205e+06 1.99531e+06 3192.49 9.71 2.88506 2.51628 58656 480125 -1 28247 15 9057 11231 1191506 271016 4.48156 4.48156 -3899.12 -4.48156 0 0 2.45448e+06 3927.17 0.73 0.61 0.38 -1 -1 0.73 0.343601 0.306286 2791 2051 741 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_41.v common 35.27 vpr 101.03 MiB 0.26 18820 -1 -1 1 0.88 -1 -1 41464 -1 -1 373 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103456 22 19 5950 4932 1 3111 426 25 25 625 clb auto 58.4 MiB 5.35 22868 125382 30342 84914 10126 94.5 MiB 2.17 0.03 4.36136 -3900.3 -4.36136 4.36136 1.74 0.010111 0.00896462 0.855855 0.758941 58 35761 44 1.58291e+07 9.48089e+06 2.14341e+06 3429.45 17.71 4.20562 3.67432 61152 534357 -1 30542 13 9396 11438 1360367 304092 4.36136 4.36136 -4147.24 -4.36136 0 0 2.68463e+06 4295.40 0.82 0.64 0.38 -1 -1 0.82 0.334472 0.299137 2912 2153 760 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_42.v common 28.04 vpr 94.77 MiB 0.19 18916 -1 -1 1 0.81 -1 -1 42788 -1 -1 376 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97040 22 19 6024 4989 1 3151 429 25 25 625 clb auto 58.8 MiB 5.61 22338 129789 31817 87521 10451 94.8 MiB 2.26 0.02 4.48156 -3879.56 -4.48156 4.48156 1.62 0.0100564 0.00897238 0.888357 0.786949 52 37600 39 1.58291e+07 9.51893e+06 1.99531e+06 3192.49 10.69 3.58221 3.12509 58656 480125 -1 30047 14 9557 11787 1160075 277147 4.60176 4.60176 -3969.48 -4.60176 0 0 2.45448e+06 3927.17 0.72 0.63 0.28 -1 -1 0.72 0.364161 0.324891 2950 2172 779 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_43.v common 52.56 vpr 95.76 MiB 0.17 19248 -1 -1 1 0.84 -1 -1 43268 -1 -1 388 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98060 22 19 6198 5129 1 3252 441 25 25 625 clb auto 59.7 MiB 5.69 22292 124613 28130 84188 12295 95.8 MiB 2.25 0.03 4.48156 -3906.86 -4.48156 4.48156 1.57 0.0119826 0.0108248 0.915972 0.811748 52 39721 49 1.58291e+07 9.67106e+06 1.99531e+06 3192.49 35.29 5.54653 4.84612 58656 480125 -1 30201 14 9788 12101 1217348 300045 4.48156 4.48156 -4076.88 -4.48156 0 0 2.45448e+06 3927.17 0.72 0.64 0.45 -1 -1 0.72 0.362311 0.324278 3034 2237 798 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_44.v common 38.21 vpr 104.12 MiB 0.23 19452 -1 -1 1 0.85 -1 -1 43464 -1 -1 393 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106616 22 19 6272 5186 1 3297 446 26 26 676 clb auto 60.2 MiB 5.83 21355 129874 31660 89304 8910 96.5 MiB 2.36 0.03 4.29513 -3951.34 -4.29513 4.29513 1.81 0.0122421 0.0106007 0.908054 0.794565 52 38819 39 1.91809e+07 9.73445e+06 2.20423e+06 3260.69 19.62 4.72492 4.12636 65116 533202 -1 29530 15 9717 12154 1180163 283797 4.60176 4.60176 -4317.78 -4.60176 0 0 2.70930e+06 4007.84 0.83 0.68 0.45 -1 -1 0.83 0.396535 0.354423 3072 2256 817 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_45.v common 54.27 vpr 97.45 MiB 0.29 19848 -1 -1 1 0.86 -1 -1 43752 -1 -1 406 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99784 22 19 6485 5365 1 3415 460 26 26 676 clb auto 61.4 MiB 5.72 22624 140685 34814 96882 8989 97.4 MiB 2.38 0.03 4.48156 -4103.24 -4.48156 4.48156 1.75 0.0108887 0.00973389 0.910155 0.806291 50 36300 23 1.91809e+07 1.02953e+07 2.15046e+06 3181.16 35.78 4.8435 4.21885 63768 504694 -1 31167 13 10359 13165 1307358 324247 4.60176 4.60176 -4375.92 -4.60176 0 0 2.57128e+06 3803.68 0.81 0.74 0.42 -1 -1 0.81 0.405213 0.364765 3177 2342 836 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_46.v common 32.21 vpr 97.84 MiB 0.19 20024 -1 -1 1 0.91 -1 -1 43916 -1 -1 411 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100184 22 19 6559 5422 1 3449 465 26 26 676 clb auto 61.9 MiB 6.60 25506 149865 38664 101092 10109 97.8 MiB 2.67 0.03 4.48156 -4212.37 -4.48156 4.48156 1.84 0.01155 0.0100428 0.99278 0.873518 54 41203 26 1.91809e+07 1.03587e+07 2.26288e+06 3347.46 12.00 3.68277 3.22084 65792 548382 -1 34168 15 10921 13370 1528099 357175 4.60176 4.60176 -4476.26 -4.60176 0 0 2.78165e+06 4114.86 0.79 0.72 0.45 -1 -1 0.79 0.406959 0.362956 3215 2361 855 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_47.v common 31.14 vpr 99.51 MiB 0.29 20428 -1 -1 1 0.95 -1 -1 44560 -1 -1 421 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101896 22 19 6735 5564 1 3561 475 26 26 676 clb auto 63.1 MiB 6.24 25310 154191 38459 104957 10775 99.0 MiB 2.64 0.03 4.42058 -4395.65 -4.42058 4.42058 1.77 0.0114443 0.0102196 0.993177 0.874618 54 40333 20 1.91809e+07 1.04854e+07 2.26288e+06 3347.46 11.75 3.82 3.32185 65792 548382 -1 34143 14 10999 13415 1399252 324545 4.48156 4.48156 -4534.97 -4.48156 0 0 2.78165e+06 4114.86 0.84 0.73 0.44 -1 -1 0.84 0.402783 0.361236 3301 2428 874 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_48.v common 31.29 vpr 99.37 MiB 0.17 20476 -1 -1 1 1.03 -1 -1 44148 -1 -1 427 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101756 22 19 6809 5621 1 3598 481 26 26 676 clb auto 63.5 MiB 6.29 25005 160536 40351 110386 9799 99.4 MiB 2.77 0.03 4.48156 -4491.6 -4.48156 4.48156 1.74 0.0111671 0.00995686 1.02469 0.906026 56 38290 31 1.91809e+07 1.05615e+07 2.31971e+06 3431.53 11.86 3.84741 3.37679 66468 563034 -1 34042 15 10589 12939 1484526 349460 4.60176 4.60176 -4789.55 -4.60176 0 0 2.84390e+06 4206.95 0.80 0.72 0.46 -1 -1 0.80 0.40184 0.356501 3339 2447 893 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_49.v common 31.00 vpr 102.99 MiB 0.31 21084 -1 -1 1 0.94 -1 -1 44412 -1 -1 443 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 105464 22 19 7094 5872 1 3718 498 27 27 729 clb auto 65.0 MiB 6.56 24179 152419 37669 105372 9378 101.0 MiB 2.65 0.03 4.19728 -4586.35 -4.19728 4.19728 1.87 0.0111429 0.00990221 0.979898 0.856498 52 42399 36 1.9726e+07 1.11604e+07 2.38665e+06 3273.86 10.51 3.42089 2.98719 69950 577685 -1 33223 16 11342 13977 1432247 338328 4.48156 4.48156 -4941.55 -4.48156 0 0 2.93284e+06 4023.09 0.88 0.90 0.47 -1 -1 0.88 0.524157 0.472249 3480 2569 912 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_50.v common 36.75 vpr 105.16 MiB 0.33 21384 -1 -1 1 1.16 -1 -1 44104 -1 -1 448 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 107684 22 19 7168 5929 1 3755 503 27 27 729 clb auto 65.2 MiB 6.69 28000 166420 40751 114741 10928 101.5 MiB 2.94 0.03 4.48156 -4578.26 -4.48156 4.48156 1.90 0.0129669 0.0115651 1.12572 0.993242 56 43916 39 1.9726e+07 1.12237e+07 2.51142e+06 3445.02 15.40 4.33648 3.78899 71406 610069 -1 38950 16 12222 15384 1884834 440341 4.60176 4.60176 -4998.93 -4.60176 0 0 3.07846e+06 4222.85 0.95 0.92 0.50 -1 -1 0.95 0.483905 0.433524 3518 2588 931 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_51.v common 40.38 vpr 105.87 MiB 0.36 21596 -1 -1 1 1.05 -1 -1 44764 -1 -1 459 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 108412 22 19 7344 6071 1 3863 514 27 27 729 clb auto 66.9 MiB 6.64 28678 169270 42388 115337 11545 102.6 MiB 2.80 0.03 4.41533 -4778.21 -4.41533 4.41533 1.83 0.0117034 0.0103951 1.02012 0.897826 54 46382 43 1.9726e+07 1.13632e+07 2.44988e+06 3360.60 19.23 4.86679 4.23664 70678 594165 -1 38295 15 12029 14450 1626312 380742 4.48156 4.48156 -5141.25 -4.48156 0 0 3.01106e+06 4130.40 1.00 0.82 0.46 -1 -1 1.00 0.446907 0.396647 3604 2655 950 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_52.v common 37.70 vpr 104.27 MiB 0.36 21756 -1 -1 1 1.12 -1 -1 45316 -1 -1 464 22 0 14 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106772 22 19 7418 6128 1 3909 519 27 27 729 clb auto 67.1 MiB 6.88 26143 167239 39832 117509 9898 102.7 MiB 2.94 0.03 4.30031 -4799.25 -4.30031 4.30031 1.86 0.0122554 0.0109024 1.03923 0.915693 54 43532 47 1.9726e+07 1.14266e+07 2.44988e+06 3360.60 16.00 4.83717 4.20334 70678 594165 -1 35636 17 11690 14277 1452572 355720 4.36136 4.36136 -5218.21 -4.36136 0 0 3.01106e+06 4130.40 0.94 0.86 0.53 -1 -1 0.94 0.509977 0.45505 3642 2674 969 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 11.24 vpr 67.37 MiB 0.06 9432 -1 -1 1 0.12 -1 -1 34808 -1 -1 79 22 0 4 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68984 22 19 1246 925 1 736 124 16 16 256 mult_36 auto 29.5 MiB 1.24 4241 18355 4196 11625 2534 67.4 MiB 0.38 0.01 8.07311 -393.21 -8.07311 8.07311 0.57 0.00311988 0.00285625 0.168593 0.154108 38 9033 43 6.34292e+06 2.58556e+06 558663. 2182.28 6.60 0.809765 0.716733 21316 135884 -1 6718 20 5024 5685 595728 162068 8.13448 8.13448 -417.392 -8.13448 0 0 744679. 2908.90 0.19 0.24 0.09 -1 -1 0.19 0.106176 0.0947645 589 344 247 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_15.v common 20.61 vpr 68.05 MiB 0.07 9540 -1 -1 1 0.15 -1 -1 35248 -1 -1 84 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69684 22 19 1344 989 1 796 130 16 16 256 mult_36 auto 30.6 MiB 1.51 4753 18225 3749 10940 3536 68.1 MiB 0.34 0.01 8.46137 -399.963 -8.46137 8.46137 0.59 0.00267077 0.00244665 0.164538 0.150832 40 9325 41 6.34292e+06 3.04495e+06 583096. 2277.72 15.54 1.45096 1.27986 21572 140635 -1 7587 24 6351 7155 819730 219125 8.06128 8.06128 -488.017 -8.06128 0 0 763333. 2981.77 0.20 0.33 0.13 -1 -1 0.20 0.137446 0.122756 633 369 266 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_16.v common 10.49 vpr 68.47 MiB 0.10 9628 -1 -1 1 0.17 -1 -1 35048 -1 -1 89 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70116 22 19 1418 1046 1 833 135 16 16 256 mult_36 auto 30.9 MiB 1.59 4903 22971 5326 13381 4264 68.5 MiB 0.42 0.01 8.1423 -435.818 -8.1423 8.1423 0.58 0.00275106 0.00252177 0.197817 0.181108 44 8716 37 6.34292e+06 3.10834e+06 649498. 2537.10 5.33 1.17548 1.03474 22336 155612 -1 7030 22 4906 5497 598759 157899 7.39308 7.39308 -479.139 -7.39308 0 0 820238. 3204.05 0.21 0.25 0.09 -1 -1 0.21 0.124865 0.111257 671 388 285 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_17.v common 8.65 vpr 69.00 MiB 0.08 10204 -1 -1 1 0.19 -1 -1 35396 -1 -1 95 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70660 22 19 1518 1112 1 899 141 16 16 256 mult_36 auto 31.5 MiB 1.46 5556 17709 3644 11642 2423 69.0 MiB 0.35 0.01 8.90161 -437.56 -8.90161 8.90161 0.55 0.00293275 0.00267956 0.158421 0.144964 46 9741 26 6.34292e+06 3.18441e+06 684529. 2673.94 3.47 0.839932 0.745992 22592 160355 -1 7950 22 5670 6223 725059 195443 8.13305 8.13305 -481.209 -8.13305 0 0 838722. 3276.26 0.21 0.30 0.15 -1 -1 0.21 0.14019 0.125408 717 415 304 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_18.v common 13.78 vpr 69.55 MiB 0.07 10252 -1 -1 1 0.15 -1 -1 34892 -1 -1 100 22 0 5 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71216 22 19 1592 1169 1 937 146 16 16 256 mult_36 auto 31.9 MiB 1.64 5565 22034 5042 13956 3036 69.5 MiB 0.42 0.01 8.87973 -457.467 -8.87973 8.87973 0.62 0.00310544 0.00284191 0.193774 0.177316 42 11318 39 6.34292e+06 3.2478e+06 613404. 2396.11 8.14 1.38438 1.21964 21828 146600 -1 8699 22 6205 6918 797479 216264 8.34213 8.34213 -594.881 -8.34213 0 0 784202. 3063.29 0.25 0.33 0.12 -1 -1 0.25 0.146706 0.131004 755 434 323 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 11.33 vpr 69.94 MiB 0.11 10548 -1 -1 1 0.22 -1 -1 35336 -1 -1 105 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71616 22 19 1688 1231 1 998 152 16 16 256 mult_36 auto 32.5 MiB 1.86 5757 22427 4578 13882 3967 69.9 MiB 0.44 0.01 8.92361 -471.887 -8.92361 8.92361 0.56 0.00324852 0.00295972 0.195619 0.178395 48 9652 27 6.34292e+06 3.70719e+06 714410. 2790.66 5.63 1.35638 1.19582 22848 165380 -1 8651 22 5351 6026 732157 188713 8.18805 8.18805 -546.947 -8.18805 0 0 863353. 3372.47 0.22 0.30 0.10 -1 -1 0.22 0.147667 0.131721 797 457 342 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 12.61 vpr 70.42 MiB 0.13 10708 -1 -1 1 0.22 -1 -1 35620 -1 -1 110 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72112 22 19 1762 1288 1 1033 157 16 16 256 mult_36 auto 32.8 MiB 1.88 5909 26383 5594 16039 4750 70.4 MiB 0.51 0.01 8.83537 -533.405 -8.83537 8.83537 0.56 0.00334843 0.00305355 0.229503 0.208935 46 10553 28 6.34292e+06 3.77058e+06 684529. 2673.94 6.59 1.4927 1.31724 22592 160355 -1 8432 21 5501 6184 629963 165433 8.19799 8.19799 -535.068 -8.19799 0 0 838722. 3276.26 0.21 0.29 0.14 -1 -1 0.21 0.14789 0.13221 835 476 361 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_21.v common 19.27 vpr 71.07 MiB 0.14 11088 -1 -1 1 0.26 -1 -1 35780 -1 -1 117 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72772 22 19 1859 1351 1 1097 164 16 16 256 mult_36 auto 33.3 MiB 2.10 6877 26148 4845 17989 3314 71.1 MiB 0.52 0.01 9.10283 -530.329 -9.10283 9.10283 0.55 0.00350904 0.00319379 0.219292 0.199579 46 12941 28 6.34292e+06 3.85933e+06 684529. 2673.94 12.86 1.68486 1.48673 22592 160355 -1 9640 20 5382 6297 642924 169839 8.50765 8.50765 -651.006 -8.50765 0 0 838722. 3276.26 0.24 0.30 0.14 -1 -1 0.24 0.158102 0.141691 878 500 380 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_22.v common 12.47 vpr 71.47 MiB 0.09 11048 -1 -1 1 0.24 -1 -1 35836 -1 -1 121 22 0 6 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73184 22 19 1933 1408 1 1134 168 16 16 256 mult_36 auto 33.9 MiB 2.14 7422 25170 4911 15658 4601 71.5 MiB 0.48 0.01 9.01458 -573.662 -9.01458 9.01458 0.57 0.00366039 0.00333703 0.217225 0.1982 48 13367 46 6.34292e+06 3.91004e+06 714410. 2790.66 5.95 1.20201 1.06296 22848 165380 -1 10834 24 6813 8030 1002292 248924 8.32694 8.32694 -795.331 -8.32694 0 0 863353. 3372.47 0.22 0.40 0.15 -1 -1 0.22 0.183735 0.163565 916 519 399 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_23.v common 11.86 vpr 72.08 MiB 0.09 11388 -1 -1 1 0.27 -1 -1 36152 -1 -1 129 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73808 22 19 2031 1472 1 1198 177 18 18 324 mult_36 auto 34.6 MiB 2.24 7275 31425 6625 21832 2968 72.1 MiB 0.66 0.01 9.00463 -548.336 -9.00463 9.00463 0.74 0.00390493 0.00356234 0.258931 0.235866 46 14196 45 7.79418e+06 4.40746e+06 895831. 2764.91 4.56 1.12575 0.997804 29024 211752 -1 10934 25 6882 7848 880826 223229 8.43839 8.43839 -703.752 -8.43839 0 0 1.09776e+06 3388.15 0.29 0.39 0.17 -1 -1 0.29 0.19905 0.177408 960 544 418 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_24.v common 12.36 vpr 72.46 MiB 0.09 11464 -1 -1 1 0.25 -1 -1 36348 -1 -1 134 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74196 22 19 2105 1529 1 1235 182 18 18 324 mult_36 auto 35.0 MiB 2.48 7801 30567 6031 22002 2534 72.5 MiB 0.61 0.01 8.93461 -590.946 -8.93461 8.93461 0.74 0.00432734 0.00392692 0.248296 0.225855 44 15786 47 7.79418e+06 4.47085e+06 850563. 2625.19 4.97 1.26592 1.11687 28700 205432 -1 11441 21 7563 8584 1010699 259800 8.45525 8.45525 -751.332 -8.45525 0 0 1.07356e+06 3313.45 0.29 0.41 0.17 -1 -1 0.29 0.184476 0.164299 998 563 437 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 15.88 vpr 73.18 MiB 0.16 11912 -1 -1 1 0.26 -1 -1 36644 -1 -1 139 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74940 22 19 2201 1591 1 1295 187 18 18 324 mult_36 auto 35.6 MiB 2.58 7794 35431 8008 24050 3373 73.2 MiB 0.75 0.01 8.99805 -627.204 -8.99805 8.99805 0.76 0.00409877 0.00373479 0.29492 0.268298 48 14419 25 7.79418e+06 4.53424e+06 935225. 2886.50 7.93 1.6909 1.49346 29348 218440 -1 11847 24 9376 10639 1260323 308837 8.19914 8.19914 -859.595 -8.19914 0 0 1.13028e+06 3488.51 0.31 0.46 0.19 -1 -1 0.31 0.202649 0.180363 1040 586 456 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 15.96 vpr 73.44 MiB 0.16 11904 -1 -1 1 0.27 -1 -1 37360 -1 -1 143 22 0 7 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75200 22 19 2275 1648 1 1331 191 18 18 324 mult_36 auto 36.1 MiB 2.25 8212 29837 6030 19775 4032 73.4 MiB 0.58 0.01 9.02558 -646.811 -9.02558 9.02558 0.75 0.00428548 0.00390516 0.253584 0.230771 46 15122 38 7.79418e+06 4.58495e+06 895831. 2764.91 8.59 1.9133 1.68997 29024 211752 -1 11958 22 7098 8090 861622 220837 8.17599 8.17599 -727.5 -8.17599 0 0 1.09776e+06 3388.15 0.29 0.38 0.19 -1 -1 0.29 0.193184 0.173255 1078 605 475 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_27.v common 17.03 vpr 74.23 MiB 0.11 12160 -1 -1 1 0.30 -1 -1 36788 -1 -1 151 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76008 22 19 2385 1724 1 1408 200 18 18 324 mult_36 auto 36.7 MiB 2.60 8727 36992 8286 24092 4614 74.2 MiB 0.76 0.01 8.93461 -662.978 -8.93461 8.93461 0.76 0.00472339 0.00425073 0.301533 0.274021 48 15283 36 7.79418e+06 5.08238e+06 935225. 2886.50 8.89 2.08068 1.8344 29348 218440 -1 12726 23 9179 10508 1335353 324369 8.28419 8.28419 -946.068 -8.28419 0 0 1.13028e+06 3488.51 0.30 0.49 0.19 -1 -1 0.30 0.205865 0.184459 1134 642 494 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_28.v common 16.72 vpr 74.45 MiB 0.17 12356 -1 -1 1 0.31 -1 -1 36712 -1 -1 156 22 0 8 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76232 22 19 2459 1781 1 1444 205 18 18 324 mult_36 auto 37.1 MiB 2.68 8451 39465 8337 25107 6021 74.4 MiB 0.76 0.01 9.16641 -691.339 -9.16641 9.16641 0.74 0.00462481 0.00422355 0.316536 0.287465 48 14904 25 7.79418e+06 5.14577e+06 935225. 2886.50 8.55 2.04169 1.80553 29348 218440 -1 12614 21 8926 10211 1159620 293360 8.50739 8.50739 -823.07 -8.50739 0 0 1.13028e+06 3488.51 0.30 0.45 0.19 -1 -1 0.30 0.203297 0.181535 1172 661 513 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_29.v common 47.46 vpr 75.10 MiB 0.11 12536 -1 -1 1 0.33 -1 -1 37136 -1 -1 163 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76900 22 19 2565 1853 1 1517 213 22 22 484 mult_36 auto 37.8 MiB 2.97 9736 37678 8527 25986 3165 75.1 MiB 0.75 0.01 8.92046 -697.22 -8.92046 8.92046 1.15 0.00455768 0.00415114 0.297373 0.26977 44 19381 44 1.26954e+07 5.63051e+06 1.30964e+06 2705.88 37.68 2.69823 2.37585 43422 318546 -1 14570 23 9535 10931 1293369 324951 8.36113 8.36113 -893.601 -8.36113 0 0 1.65337e+06 3416.05 0.47 0.54 0.29 -1 -1 0.47 0.243977 0.218617 1224 694 532 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_30.v common 21.61 vpr 75.55 MiB 0.15 12620 -1 -1 1 0.35 -1 -1 37288 -1 -1 168 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77368 22 19 2639 1910 1 1554 218 22 22 484 mult_36 auto 38.7 MiB 2.93 9704 46068 10050 31278 4740 75.6 MiB 0.90 0.01 9.05578 -707.338 -9.05578 9.05578 1.22 0.00505393 0.00458653 0.362219 0.32803 46 18565 36 1.26954e+07 5.6939e+06 1.37878e+06 2848.72 11.65 2.2504 1.98663 43906 328446 -1 14231 21 9207 10549 1182524 287358 8.44828 8.44828 -1021.22 -8.44828 0 0 1.69059e+06 3492.95 0.48 0.49 0.29 -1 -1 0.48 0.22278 0.199444 1262 713 551 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_31.v common 18.40 vpr 76.16 MiB 0.19 12948 -1 -1 1 0.36 -1 -1 37572 -1 -1 175 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77984 22 19 2744 1981 1 1626 225 22 22 484 mult_36 auto 39.1 MiB 3.06 10429 54261 13323 35940 4998 76.2 MiB 1.06 0.01 9.21706 -731.706 -9.21706 9.21706 1.19 0.00506592 0.00460699 0.417543 0.377769 46 19383 40 1.26954e+07 5.78265e+06 1.37878e+06 2848.72 7.99 1.79479 1.59544 43906 328446 -1 15283 22 9077 10419 1338103 316338 8.27705 8.27705 -922.434 -8.27705 0 0 1.69059e+06 3492.95 0.47 0.57 0.28 -1 -1 0.47 0.263815 0.237002 1313 745 570 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_32.v common 22.02 vpr 76.43 MiB 0.11 13016 -1 -1 1 0.39 -1 -1 36920 -1 -1 179 22 0 9 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78268 22 19 2818 2038 1 1662 229 22 22 484 mult_36 auto 39.4 MiB 3.20 10391 57629 14299 38067 5263 76.4 MiB 1.16 0.01 8.90432 -796.741 -8.90432 8.90432 1.23 0.00509439 0.00460665 0.45302 0.409964 50 17124 25 1.26954e+07 5.83336e+06 1.50222e+06 3103.76 11.39 2.40958 2.13136 44874 350400 -1 15076 25 10335 11812 1322909 330631 8.19693 8.19693 -1070.7 -8.19693 0 0 1.79645e+06 3711.66 0.51 0.57 0.25 -1 -1 0.51 0.26958 0.240498 1351 764 589 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_33.v common 16.88 vpr 77.11 MiB 0.21 13780 -1 -1 1 0.39 -1 -1 37408 -1 -1 187 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78956 22 19 2923 2109 1 1730 238 22 22 484 mult_36 auto 40.1 MiB 3.20 10842 55513 13255 35231 7027 77.1 MiB 1.05 0.01 9.95249 -834.822 -9.95249 9.95249 1.18 0.00253764 0.00230185 0.418184 0.377872 46 19712 40 1.26954e+07 6.33079e+06 1.37878e+06 2848.72 6.36 1.65683 1.4737 43906 328446 -1 15703 22 9397 10976 1237626 310640 9.04671 9.04671 -1200.39 -9.04671 0 0 1.69059e+06 3492.95 0.48 0.56 0.28 -1 -1 0.48 0.263107 0.234827 1402 796 608 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_34.v common 18.96 vpr 77.73 MiB 0.20 13840 -1 -1 1 0.39 -1 -1 37884 -1 -1 193 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79600 22 19 2997 2166 1 1769 244 22 22 484 mult_36 auto 40.5 MiB 3.32 11512 55870 12803 38332 4735 77.7 MiB 1.10 0.01 9.71104 -846.569 -9.71104 9.71104 1.18 0.00548715 0.00499123 0.421909 0.382237 44 24353 49 1.26954e+07 6.40685e+06 1.30964e+06 2705.88 8.01 1.83971 1.62943 43422 318546 -1 17171 26 12960 14652 1853547 452272 9.15799 9.15799 -1105.75 -9.15799 0 0 1.65337e+06 3416.05 0.48 0.73 0.27 -1 -1 0.48 0.310143 0.276139 1441 815 627 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_35.v common 23.39 vpr 78.45 MiB 0.21 14108 -1 -1 1 0.41 -1 -1 37808 -1 -1 199 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80332 22 19 3101 2236 1 1838 250 22 22 484 mult_36 auto 41.3 MiB 3.53 11883 59275 13898 40462 4915 78.4 MiB 1.24 0.02 10.0716 -839.08 -10.0716 10.0716 1.19 0.00572678 0.00520149 0.474643 0.430492 46 21331 31 1.26954e+07 6.48292e+06 1.37878e+06 2848.72 12.12 2.66162 2.35294 43906 328446 -1 17287 21 10101 11468 1346054 329306 9.20985 9.20985 -1049.74 -9.20985 0 0 1.69059e+06 3492.95 0.47 0.54 0.27 -1 -1 0.47 0.254172 0.227458 1491 846 646 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_36.v common 25.66 vpr 78.64 MiB 0.13 14164 -1 -1 1 0.42 -1 -1 38088 -1 -1 203 22 0 10 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80532 22 19 3175 2293 1 1872 254 22 22 484 mult_36 auto 41.7 MiB 3.56 11856 67790 16050 43614 8126 78.6 MiB 1.29 0.02 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v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82676 22 19 3531 2547 1 2089 279 24 24 576 mult_36 auto 43.9 MiB 4.04 13649 81358 20240 53084 8034 80.7 MiB 1.55 0.02 9.76447 -1012.02 -9.76447 9.76447 1.44 0.00627344 0.00568308 0.596184 0.538567 46 24498 47 1.53347e+07 7.23391e+06 1.63708e+06 2842.15 10.31 2.32309 2.0508 51922 389946 -1 19547 23 11831 13375 1622364 412860 8.89731 8.89731 -1325.41 -8.89731 0 0 2.00908e+06 3487.99 0.56 0.69 0.34 -1 -1 0.56 0.32088 0.286395 1705 965 741 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_41.v common 23.80 vpr 81.44 MiB 0.24 15120 -1 -1 1 0.63 -1 -1 38080 -1 -1 233 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83396 22 19 3634 2616 1 2155 286 24 24 576 mult_36 auto 44.5 MiB 5.19 13461 71802 17518 48500 5784 81.4 MiB 1.44 0.02 9.84473 -990.415 -9.84473 9.84473 1.49 0.00682155 0.00620547 0.551807 0.496406 46 24068 31 1.53347e+07 7.70597e+06 1.63708e+06 2842.15 9.20 2.20878 1.9572 51922 389946 -1 19383 21 10783 12491 1296656 334801 9.01371 9.01371 -1397.76 -9.01371 0 0 2.00908e+06 3487.99 0.56 0.58 0.31 -1 -1 0.56 0.291691 0.25952 1754 995 760 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_42.v common 26.35 vpr 81.95 MiB 0.23 15460 -1 -1 1 0.54 -1 -1 38248 -1 -1 238 22 0 12 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83920 22 19 3708 2673 1 2193 291 24 24 576 mult_36 auto 45.0 MiB 4.33 13774 73555 16192 46647 10716 82.0 MiB 1.46 0.02 9.6448 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-k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_45.v common 22.00 vpr 83.36 MiB 0.27 16076 -1 -1 1 0.66 -1 -1 40428 -1 -1 256 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85360 22 19 3989 2869 1 2368 310 24 24 576 mult_36 auto 46.3 MiB 4.47 16170 76814 16744 54012 6058 83.4 MiB 1.63 0.02 9.69686 -1053.48 -9.69686 9.69686 1.51 0.00733892 0.00667215 0.584672 0.525516 48 27771 33 1.53347e+07 8.39357e+06 1.71014e+06 2969.00 7.65 2.13518 1.89576 52498 402441 -1 23267 23 14444 16589 2052278 495094 9.46445 9.46445 -1673.39 -9.46445 0 0 2.06880e+06 3591.66 0.60 0.85 0.29 -1 -1 0.60 0.365172 0.325707 1929 1094 836 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_46.v common 23.54 vpr 84.10 MiB 0.26 16096 -1 -1 1 0.61 -1 -1 40696 -1 -1 260 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86116 22 19 4063 2926 1 2404 314 24 24 576 mult_36 auto 47.2 MiB 4.78 15339 80264 18599 54196 7469 84.1 MiB 1.70 0.02 10.1503 -1097.92 -10.1503 10.1503 1.37 0.0080052 0.0071957 0.606251 0.544168 48 26539 34 1.53347e+07 8.44428e+06 1.71014e+06 2969.00 8.51 2.26702 2.00623 52498 402441 -1 22415 22 12869 14913 1883761 456417 9.18285 9.18285 -1669.24 -9.18285 0 0 2.06880e+06 3591.66 0.59 0.79 0.34 -1 -1 0.59 0.345793 0.309364 1967 1113 855 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_47.v common 26.53 vpr 84.31 MiB 0.29 16492 -1 -1 1 0.68 -1 -1 40776 -1 -1 267 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86336 22 19 4167 2996 1 2473 321 24 24 576 mult_36 auto 47.5 MiB 5.05 15911 94749 24093 55772 14884 84.3 MiB 1.98 0.02 9.84328 -1100.98 -9.84328 9.84328 1.68 0.00765987 0.00694488 0.760369 0.680609 52 27975 40 1.53347e+07 8.53303e+06 1.82869e+06 3174.81 10.22 2.77005 2.44505 54222 439550 -1 21924 24 13845 15738 1880408 458130 8.78434 8.78434 -1662.3 -8.78434 0 0 2.25030e+06 3906.77 0.65 0.81 0.38 -1 -1 0.65 0.378633 0.337232 2017 1144 874 19 0 0 -k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_48.v common 25.99 vpr 84.62 MiB 0.29 16564 -1 -1 1 0.63 -1 -1 40944 -1 -1 272 22 0 13 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86648 22 19 4241 3053 1 2509 326 24 24 576 mult_36 auto 47.7 MiB 6.23 15944 93369 22969 60571 9829 84.6 MiB 1.86 0.02 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crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_14.v common 13.36 vpr 70.26 MiB 0.09 10424 -1 -1 8 0.47 -1 -1 34572 -1 -1 167 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76224 22 19 2488 2337 1 1296 281 20 20 400 clb auto 34.2 MiB 0.79 10108 52721 12182 37607 2932 74.4 MiB 0.72 0.01 4.33936 -1893.53 -4.33936 4.33936 0.44 0.00513677 0.00460665 0.29455 0.260628 -1 -1 -1 -1 42 20702 48 1.09209e+07 5.19687e+06 1.00142e+06 2503.56 5.54 1.53183 1.3355 33938 240731 -1 16690 15 5263 11971 845516 215430 4.57976 4.57976 -1989.21 -4.57976 0 0 1.27864e+06 3196.60 0.05 0.37 0.19 -1 -1 0.05 0.185413 0.164913 1360 1360 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_20.v common 20.34 vpr 74.65 MiB 0.15 12440 -1 -1 8 0.72 -1 -1 37452 -1 -1 242 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76440 22 19 2546 2395 1 1327 289 21 21 441 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78972 22 19 3005 2820 1 1580 334 22 22 484 clb auto 36.4 MiB 0.59 12197 69814 16429 49622 3763 77.1 MiB 0.61 0.01 4.39565 -2299.56 -4.39565 4.39565 0.44 0.00315432 0.00282751 0.205453 0.180694 -1 -1 -1 -1 44 23896 48 1.25085e+07 6.21973e+06 1.30964e+06 2705.88 21.51 2.81539 2.41828 42222 317661 -1 20018 14 6355 14283 1038692 270318 4.45956 4.45956 -2489.25 -4.45956 0 0 1.65337e+06 3416.05 0.07 0.44 0.25 -1 -1 0.07 0.215637 0.192196 1656 1656 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_25.v common 33.50 vpr 78.28 MiB 0.10 14148 -1 -1 8 1.00 -1 -1 40376 -1 -1 301 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80160 22 19 3229 3027 1 1681 349 23 23 529 clb auto 37.5 MiB 1.06 12977 75257 18358 53198 3701 78.3 MiB 1.08 0.02 4.20914 -2487.72 -4.20914 4.20914 0.61 0.00633471 0.00564081 0.435315 0.383338 -1 -1 -1 -1 46 25322 26 1.29425e+07 6.40056e+06 1.51613e+06 2866.03 25.87 3.15091 2.706 46482 360645 -1 20392 15 6168 14237 875172 225052 4.33936 4.33936 -2618 -4.33936 0 0 1.85922e+06 3514.59 0.08 0.43 0.28 -1 -1 0.08 0.235902 0.211186 1771 1771 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_pipe_26.v common 31.57 vpr 78.65 MiB 0.19 14376 -1 -1 8 1.08 -1 -1 40752 -1 -1 310 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80536 22 19 3287 3085 1 1716 358 23 23 529 clb auto 37.6 MiB 1.10 13044 77828 19200 55176 3452 78.6 MiB 1.09 0.02 4.33936 -2551.51 -4.33936 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/home/elgamma8/research/release/vtr-verilog-to-routing 121012 22 19 6600 6177 1 3516 701 32 32 1024 clb auto 54.0 MiB 2.25 28670 252773 74309 169713 8751 111.3 MiB 3.47 0.04 4.49301 -5297.83 -4.49301 4.49301 1.27 0.0139262 0.0124467 1.19941 1.0457 -1 -1 -1 -1 48 51786 44 3.00046e+07 1.33315e+07 3.15722e+06 3083.23 66.78 7.45152 6.3921 92896 748174 -1 44132 14 12610 29612 1930272 478078 4.45956 4.45956 -5598.89 -4.45956 0 0 3.82033e+06 3730.79 0.18 0.91 0.58 -1 -1 0.18 0.463107 0.411713 3692 3692 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 10.85 vpr 68.50 MiB 0.10 9364 -1 -1 10 0.49 -1 -1 35168 -1 -1 129 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70148 22 19 1149 1049 1 759 174 16 16 256 mult_36 auto 28.0 MiB 0.39 5184 23939 4710 17099 2130 68.5 MiB 0.33 0.01 13.5198 -443.456 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71320 22 19 1507 1373 1 991 218 18 18 324 clb auto 30.4 MiB 0.53 7362 30348 5713 22491 2144 69.6 MiB 0.43 0.01 14.8725 -555.907 -14.8725 14.8725 0.36 0.00359591 0.00327891 0.185193 0.16836 -1 -1 -1 -1 54 13406 22 7.67456e+06 4.05346e+06 1.02660e+06 3168.53 2.82 0.944802 0.832068 29872 244976 -1 12074 19 4649 10391 624229 159812 13.4966 13.4966 -696.578 -13.4966 0 0 1.26286e+06 3897.71 0.05 0.29 0.19 -1 -1 0.05 0.150286 0.133957 961 961 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 12.51 vpr 70.14 MiB 0.12 10404 -1 -1 11 0.66 -1 -1 36104 -1 -1 183 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71828 22 19 1596 1445 1 1066 230 18 18 324 clb auto 30.6 MiB 0.40 7944 35430 6947 26296 2187 70.1 MiB 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 101752 22 19 4305 3882 1 2862 558 29 29 841 clb auto 45.5 MiB 1.42 22691 158982 41824 110259 6899 91.0 MiB 2.07 0.03 16.6868 -1410.23 -16.6868 16.6868 1.00 0.0098307 0.008898 0.737926 0.654456 -1 -1 -1 -1 54 40794 35 2.24058e+07 1.16077e+07 2.80981e+06 3341.03 61.81 5.74602 5.00323 78400 678428 -1 35834 21 13983 32924 2124657 520135 15.259 15.259 -1939.91 -15.259 0 0 3.45506e+06 4108.28 0.15 0.97 0.53 -1 -1 0.15 0.456186 0.407309 2826 2826 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml fir_nopipe_52.v common 64.09 vpr 97.14 MiB 0.31 17592 -1 -1 13 2.71 -1 -1 39888 -1 -1 507 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 99468 22 19 4363 3940 1 2893 562 29 29 841 clb auto 45.6 MiB 1.45 22976 167458 43444 116381 7633 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77224 22 19 2536 2130 1 1284 256 19 19 361 clb auto 35.5 MiB 0.73 7943 48976 10568 34606 3802 75.4 MiB 0.71 0.01 4.19769 -1575.78 -4.19769 4.19769 0.40 0.00421759 0.00376835 0.28038 0.250024 -1 -1 -1 -1 38 14826 29 8.13532e+06 4.61718e+06 822740. 2279.06 9.82 1.90607 1.64658 30442 202059 -1 11445 15 3911 5068 425584 124345 4.24116 4.24116 -1631.53 -4.24116 0 0 1.09718e+06 3039.29 0.04 0.25 0.16 -1 -1 0.04 0.152868 0.135649 1228 924 304 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_18.v common 11.05 vpr 75.65 MiB 0.13 12000 -1 -1 1 0.28 -1 -1 37152 -1 -1 220 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77468 22 19 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 117908 22 19 7418 6128 1 3906 690 31 31 961 clb auto 60.8 MiB 2.21 31171 274920 76802 183853 14265 110.9 MiB 4.03 0.05 4.48156 -5029.46 -4.48156 4.48156 1.18 0.0129033 0.0115628 1.21606 1.07363 -1 -1 -1 -1 44 50421 42 2.5096e+07 1.35183e+07 2.69324e+06 2802.54 31.82 4.99006 4.31204 86716 660222 -1 41712 15 11398 14424 1540122 390484 4.72196 4.72196 -5077.4 -4.72196 0 0 3.40179e+06 3539.84 0.16 0.77 0.51 -1 -1 0.16 0.433546 0.384238 3643 2674 969 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_14.v common 5.54 vpr 67.75 MiB 0.09 9396 -1 -1 1 0.16 -1 -1 34652 -1 -1 105 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69380 22 19 1246 925 1 729 150 16 16 256 mult_36 auto 28.8 MiB 0.42 4287 20050 4045 13932 2073 67.8 MiB 0.35 0.01 8.44555 -394.864 -8.44555 8.44555 0.28 0.00252268 0.00231193 0.137422 0.125997 -1 -1 -1 -1 36 9045 37 6.32612e+06 2.90259e+06 535569. 2092.07 2.37 0.631072 0.557954 20808 126872 -1 6872 24 5057 6129 675254 196211 7.96139 7.96139 -477.109 -7.96139 0 0 684529. 2673.94 0.03 0.26 0.11 -1 -1 0.03 0.121495 0.108107 591 344 247 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_15.v common 6.19 vpr 68.48 MiB 0.11 9612 -1 -1 1 0.19 -1 -1 35192 -1 -1 112 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70120 22 19 1344 989 1 789 158 16 16 256 mult_36 auto 29.2 MiB 0.41 4918 25778 5718 17517 2543 68.5 MiB 0.48 0.01 8.50055 -422.339 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vpr 69.84 MiB 0.12 10372 -1 -1 1 0.19 -1 -1 35108 -1 -1 134 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71520 22 19 1592 1169 1 928 180 16 16 256 clb mult_36 auto 30.8 MiB 0.54 5466 32184 7384 21670 3130 69.8 MiB 0.62 0.01 9.07695 -498.175 -9.07695 9.07695 0.28 0.00305233 0.00278916 0.206264 0.188236 -1 -1 -1 -1 38 11809 43 6.32612e+06 3.66277e+06 558663. 2182.28 3.10 0.890721 0.7875 21316 135884 -1 8788 23 6839 8006 836324 249518 8.68285 8.68285 -652.045 -8.68285 0 0 744679. 2908.90 0.03 0.32 0.11 -1 -1 0.03 0.143925 0.127913 757 434 323 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 18.37 vpr 70.55 MiB 0.13 10476 -1 -1 1 0.20 -1 -1 35300 -1 -1 141 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72240 22 19 1688 1231 1 988 188 17 17 289 clb auto 31.2 MiB 0.56 6040 29778 6467 18590 4721 70.5 MiB 0.54 0.01 9.14683 -510.28 -9.14683 9.14683 0.32 0.00337204 0.00307949 0.207074 0.188891 -1 -1 -1 -1 40 11750 40 6.64007e+06 4.14668e+06 666494. 2306.21 14.32 1.64128 1.44358 24274 161130 -1 9396 22 6413 7782 829846 236284 8.85905 8.85905 -666.243 -8.85905 0 0 872365. 3018.56 0.03 0.32 0.13 -1 -1 0.03 0.148784 0.132358 799 457 342 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 17.96 vpr 70.89 MiB 0.13 10752 -1 -1 1 0.22 -1 -1 35712 -1 -1 147 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72596 22 19 1762 1288 1 1026 194 17 17 289 clb auto 31.6 MiB 0.58 6727 40025 9604 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74468 22 19 2105 1529 1 1224 223 18 18 324 clb mult_36 auto 33.2 MiB 0.69 7747 44163 10132 30236 3795 72.7 MiB 0.80 0.01 9.18099 -606.294 -9.18099 9.18099 0.36 0.00398144 0.00363267 0.286395 0.26078 -1 -1 -1 -1 44 14619 39 7.77114e+06 4.96965e+06 850563. 2625.19 8.75 1.79914 1.57976 28700 205432 -1 11577 23 7286 8761 953169 268335 8.47065 8.47065 -820.552 -8.47065 0 0 1.07356e+06 3313.45 0.04 0.39 0.16 -1 -1 0.04 0.18896 0.167499 1000 563 437 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 8.60 vpr 73.39 MiB 0.15 12020 -1 -1 1 0.28 -1 -1 36580 -1 -1 182 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75152 22 19 2201 1591 1 1284 230 18 18 324 clb mult_36 auto 33.9 MiB 0.69 7961 49510 11662 33160 4688 73.4 MiB 0.86 0.01 8.98857 -675.612 -8.98857 8.98857 0.36 0.00418069 0.00380642 0.286762 0.259732 -1 -1 -1 -1 46 14105 33 7.77114e+06 5.05756e+06 895831. 2764.91 3.63 1.28515 1.13409 29024 211752 -1 11360 22 7134 8496 846648 235548 8.25405 8.25405 -875.377 -8.25405 0 0 1.09776e+06 3388.15 0.04 0.34 0.17 -1 -1 0.04 0.182138 0.161881 1042 586 456 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 15.03 vpr 73.68 MiB 0.16 11956 -1 -1 1 0.28 -1 -1 37400 -1 -1 189 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75444 22 19 2275 1648 1 1320 237 18 18 324 clb mult_36 auto 34.2 MiB 0.69 8332 51547 11837 33261 6449 73.7 MiB 0.93 0.01 9.20998 -667.689 -9.20998 9.20998 0.36 0.00430745 0.00392566 0.319063 0.289801 -1 -1 -1 -1 44 15572 31 7.77114e+06 5.14546e+06 850563. 2625.19 9.86 1.88471 1.65398 28700 205432 -1 12379 22 7578 9224 954809 269452 8.67185 8.67185 -830.678 -8.67185 0 0 1.07356e+06 3313.45 0.04 0.38 0.16 -1 -1 0.04 0.192164 0.170765 1080 605 475 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_27.v common 17.59 vpr 74.30 MiB 0.16 12248 -1 -1 1 0.30 -1 -1 36696 -1 -1 199 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76088 22 19 2385 1724 1 1395 248 19 19 361 clb auto 34.5 MiB 0.72 8712 55486 13505 36286 5695 74.3 MiB 0.93 0.01 9.14633 -671.93 -9.14633 9.14633 0.40 0.00429562 0.00386782 0.322657 0.292637 -1 -1 -1 -1 40 16572 36 8.13532e+06 5.66704e+06 859013. 2379.54 12.11 2.20879 1.93876 30802 209215 -1 13671 23 9626 11438 1195167 335637 8.64865 8.64865 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77884 22 19 2639 1910 1 1539 271 22 22 484 mult_36 auto 36.2 MiB 0.86 9909 65971 16907 43504 5560 76.1 MiB 1.22 0.02 9.0891 -763.527 -9.0891 9.0891 0.55 0.00494907 0.0044795 0.389735 0.352486 -1 -1 -1 -1 40 19268 27 1.26594e+07 6.33932e+06 1.17677e+06 2431.33 6.46 1.51266 1.33443 41974 287914 -1 15915 25 12141 14260 1611823 432096 8.74585 8.74585 -895.223 -8.74585 0 0 1.53957e+06 3180.94 0.07 0.55 0.23 -1 -1 0.07 0.23933 0.211973 1264 713 551 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_31.v common 28.21 vpr 76.57 MiB 0.18 13024 -1 -1 1 0.34 -1 -1 37476 -1 -1 231 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78408 22 19 2744 1981 1 1609 281 22 22 484 mult_36 auto 36.7 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6.52769e+06 1.12685e+06 2328.21 22.62 2.69708 2.36845 41490 277996 -1 16087 22 12319 14701 1525128 421166 8.84825 8.84825 -1096.2 -8.84825 0 0 1.50222e+06 3103.76 0.06 0.57 0.22 -1 -1 0.06 0.243455 0.216177 1353 764 589 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_33.v common 12.97 vpr 77.75 MiB 0.20 13700 -1 -1 1 0.37 -1 -1 37496 -1 -1 247 22 0 10 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79612 22 19 2923 2109 1 1714 298 22 22 484 mult_36 auto 37.6 MiB 0.89 10805 77908 19804 48941 9163 77.7 MiB 1.33 0.02 10.0946 -829.447 -10.0946 10.0946 0.55 0.00549627 0.00497002 0.446976 0.403289 -1 -1 -1 -1 44 20199 34 1.26594e+07 7.06183e+06 1.30964e+06 2705.88 5.99 1.7989 1.59048 43422 318546 -1 16375 21 10645 12669 1455180 374595 9.65391 9.65391 -1117.92 -9.65391 0 0 1.65337e+06 3416.05 0.07 0.51 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81000 22 19 3175 2293 1 1856 318 22 22 484 clb mult_36 auto 39.0 MiB 1.01 13199 78438 19409 50137 8892 79.1 MiB 1.42 0.02 10.2693 -910.248 -10.2693 10.2693 0.55 0.00593774 0.00534405 0.444722 0.401248 -1 -1 -1 -1 44 25416 43 1.26594e+07 7.31299e+06 1.30964e+06 2705.88 21.94 2.74676 2.40989 43422 318546 -1 19234 24 10254 12494 1584808 397779 9.57071 9.57071 -1208.42 -9.57071 0 0 1.65337e+06 3416.05 0.07 0.59 0.25 -1 -1 0.07 0.276211 0.24504 1530 865 665 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_37.v common 46.16 vpr 79.78 MiB 0.22 14476 -1 -1 1 0.42 -1 -1 37556 -1 -1 277 22 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81692 22 19 3280 2364 1 1927 329 24 24 576 mult_36 auto 39.6 MiB 1.02 12290 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84868 22 19 3708 2673 1 2172 365 24 24 576 mult_36 auto 41.6 MiB 1.22 14462 120241 32438 75438 12365 82.2 MiB 2.17 0.02 9.96967 -1067.82 -9.96967 9.96967 0.65 0.00646698 0.00585808 0.660337 0.594419 -1 -1 -1 -1 52 24462 42 1.52924e+07 8.6701e+06 1.82869e+06 3174.81 13.80 3.56459 3.12873 54222 439550 -1 20698 22 10976 13483 1592120 415353 9.00471 9.00471 -1584.16 -9.00471 0 0 2.25030e+06 3906.77 0.09 0.64 0.35 -1 -1 0.09 0.304663 0.270699 1793 1014 779 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_43.v common 14.31 vpr 82.55 MiB 0.25 15636 -1 -1 1 0.51 -1 -1 38876 -1 -1 321 22 0 12 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84528 22 19 3810 2741 1 2238 374 24 24 576 mult_36 auto 42.1 MiB 1.22 14596 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87024 22 19 4241 3053 1 2487 411 25 25 625 clb auto 44.3 MiB 1.43 16851 128679 33580 81852 13247 85.0 MiB 2.19 0.03 10.4333 -1182.17 -10.4333 10.4333 0.71 0.00727078 0.00656308 0.651011 0.584255 -1 -1 -1 -1 46 30316 49 1.57822e+07 9.63121e+06 1.78602e+06 2857.63 7.65 2.46871 2.17452 56160 425985 -1 23399 19 11576 14177 1412366 389061 9.45851 9.45851 -1530.31 -9.45851 0 0 2.19200e+06 3507.21 0.09 0.61 0.33 -1 -1 0.09 0.307777 0.274473 2056 1163 893 19 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_49.v common 30.41 vpr 85.53 MiB 0.30 17148 -1 -1 1 0.61 -1 -1 41080 -1 -1 367 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87584 22 19 4346 3124 1 2556 422 25 25 625 clb auto 44.7 MiB 1.42 16534 145966 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-1 -1 168 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73836 22 19 1974 1653 1 1034 213 18 18 324 clb auto 32.4 MiB 1.57 6437 36408 8464 25361 2583 72.1 MiB 0.53 0.01 4.17493 -1221.02 -4.17493 4.17493 0.35 0.00353135 0.00317482 0.212 0.190543 -1 -1 -1 -1 38 11873 29 7.79418e+06 3.7139e+06 731621. 2258.09 2.13 0.865345 0.753807 27408 179348 -1 9578 16 3293 4036 387848 110929 4.36136 4.36136 -1291.74 -4.36136 0 0 975281. 3010.13 0.04 0.21 0.14 -1 -1 0.04 0.123114 0.108894 955 708 247 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_15.v common 10.08 vpr 73.14 MiB 0.11 11004 -1 -1 1 0.23 -1 -1 36888 -1 -1 182 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74896 22 19 2144 1789 1 1129 228 18 18 324 clb auto 33.3 MiB 1.78 6855 41292 9386 28690 3216 73.1 MiB 0.59 0.01 4.12096 -1335.05 -4.12096 4.12096 0.35 0.00392815 0.00353498 0.234729 0.21031 -1 -1 -1 -1 36 12852 27 7.79418e+06 4.2874e+06 701445. 2164.95 4.64 1.31645 1.14368 26764 167360 -1 10878 15 3781 4648 441066 132051 4.36136 4.36136 -1397.94 -4.36136 0 0 895831. 2764.91 0.04 0.22 0.13 -1 -1 0.04 0.127815 0.113299 1035 769 266 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_16.v common 11.76 vpr 73.54 MiB 0.12 10880 -1 -1 1 0.25 -1 -1 36860 -1 -1 190 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75308 22 19 2218 1846 1 1177 236 18 18 324 clb auto 34.0 MiB 1.84 7711 49079 11493 33399 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 107268 22 19 6485 5365 1 3397 606 30 30 900 clb auto 56.4 MiB 5.35 22826 236402 66664 157987 11751 102.1 MiB 3.35 0.04 4.30031 -4327.06 -4.30031 4.30031 1.07 0.0103941 0.00921231 1.01692 0.892236 -1 -1 -1 -1 42 39063 32 2.45387e+07 1.21463e+07 2.38040e+06 2644.88 40.63 5.17453 4.4485 79656 579061 -1 32498 17 10688 13571 1349892 354774 4.36136 4.36136 -4464.7 -4.36136 0 0 3.03473e+06 3371.92 0.13 0.72 0.44 -1 -1 0.13 0.414525 0.366798 3178 2342 836 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_pipe_46.v common 79.18 vpr 109.56 MiB 0.31 20060 -1 -1 1 0.90 -1 -1 43976 -1 -1 561 22 0 13 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 112192 22 19 6559 5422 1 3448 615 30 30 900 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0.11 10272 -1 -1 1 0.18 -1 -1 35368 -1 -1 127 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71256 22 19 1518 1112 1 892 173 16 16 256 mult_36 auto 30.3 MiB 0.65 5503 28071 5933 18743 3395 69.6 MiB 0.49 0.01 8.91743 -462.46 -8.91743 8.91743 0.29 0.00295234 0.00270461 0.189539 0.173372 -1 -1 -1 -1 38 11258 42 6.34292e+06 3.59011e+06 558663. 2182.28 5.29 1.1709 1.0309 21316 135884 -1 8513 21 6222 7437 682588 201755 8.48434 8.48434 -576.047 -8.48434 0 0 744679. 2908.90 0.03 0.27 0.11 -1 -1 0.03 0.128485 0.114432 719 415 304 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_18.v common 6.42 vpr 69.94 MiB 0.10 10248 -1 -1 1 0.21 -1 -1 34952 -1 -1 134 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71616 22 19 1592 1169 1 928 180 16 16 256 clb mult_36 auto 30.7 MiB 0.64 5724 31676 7309 20857 3510 69.9 MiB 0.57 0.01 8.93251 -473.848 -8.93251 8.93251 0.28 0.00321904 0.00295322 0.2123 0.193994 -1 -1 -1 -1 40 10073 47 6.34292e+06 3.67885e+06 583096. 2277.72 2.38 0.879715 0.778536 21572 140635 -1 8764 24 5909 7048 709438 207670 8.43039 8.43039 -586.215 -8.43039 0 0 763333. 2981.77 0.03 0.30 0.11 -1 -1 0.03 0.1475 0.13093 757 434 323 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_19.v common 16.88 vpr 70.49 MiB 0.12 10616 -1 -1 1 0.20 -1 -1 35336 -1 -1 141 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72184 22 19 1688 1231 1 988 188 17 17 289 clb auto 31.2 MiB 0.71 6258 37848 9148 22741 5959 70.5 MiB 0.63 0.01 9.05754 -504.418 -9.05754 9.05754 0.31 0.00319327 0.00290678 0.237097 0.216084 -1 -1 -1 -1 44 11257 33 6.65987e+06 4.1636e+06 742403. 2568.87 12.65 1.70433 1.49671 25138 178286 -1 9123 22 5698 6671 729354 204335 8.54048 8.54048 -561.246 -8.54048 0 0 937218. 3242.97 0.04 0.30 0.14 -1 -1 0.04 0.14804 0.131823 799 457 342 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_20.v common 14.65 vpr 70.83 MiB 0.13 10704 -1 -1 1 0.21 -1 -1 35564 -1 -1 147 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72528 22 19 1762 1288 1 1026 194 17 17 289 clb auto 31.6 MiB 0.69 6372 41708 10894 25393 5421 70.8 MiB 0.72 0.01 8.88444 -508.436 -8.88444 8.88444 0.31 0.00339803 0.00310403 0.264787 0.240982 -1 -1 -1 -1 40 12323 50 6.65987e+06 4.23967e+06 666494. 2306.21 10.22 1.61063 1.418 24274 161130 -1 9898 23 7805 9172 952233 263407 8.50239 8.50239 -652.802 -8.50239 0 0 872365. 3018.56 0.03 0.37 0.13 -1 -1 0.03 0.16399 0.145904 837 476 361 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_21.v common 9.41 vpr 71.57 MiB 0.14 11128 -1 -1 1 0.22 -1 -1 35816 -1 -1 153 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73284 22 19 1859 1351 1 1087 200 17 17 289 clb auto 32.1 MiB 0.71 7135 41080 9703 25137 6240 71.6 MiB 0.74 0.01 9.05481 -571.674 -9.05481 9.05481 0.32 0.00355987 0.00325093 0.260262 0.23706 -1 -1 -1 -1 48 12634 30 6.65987e+06 4.31573e+06 816265. 2824.45 4.94 1.51572 1.33563 25714 189529 -1 10421 20 5528 6749 743939 205293 8.25194 8.25194 -695.98 -8.25194 0 0 986792. 3414.50 0.04 0.30 0.15 -1 -1 0.04 0.14708 0.131047 880 500 380 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_22.v common 6.87 vpr 71.99 MiB 0.14 11160 -1 -1 1 0.23 -1 -1 35832 -1 -1 160 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73716 22 19 1933 1408 1 1125 207 17 17 289 clb auto 32.5 MiB 0.72 7164 37539 8536 23747 5256 72.0 MiB 0.67 0.01 8.99572 -564.854 -8.99572 8.99572 0.31 0.00365369 0.00332109 0.239411 0.217447 -1 -1 -1 -1 46 12071 28 6.65987e+06 4.40448e+06 782063. 2706.10 2.34 0.897038 0.793261 25426 183746 -1 9756 23 5544 6782 656975 182769 8.12179 8.12179 -677.438 -8.12179 0 0 958460. 3316.47 0.04 0.33 0.15 -1 -1 0.04 0.181285 0.161567 918 519 399 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_23.v common 12.72 vpr 72.27 MiB 0.14 11396 -1 -1 1 0.24 -1 -1 36052 -1 -1 169 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74008 22 19 2031 1472 1 1187 217 18 18 324 clb mult_36 auto 32.8 MiB 0.78 7269 45136 10448 29894 4794 72.3 MiB 0.84 0.01 8.94717 -568.771 -8.94717 8.94717 0.36 0.00385211 0.00351229 0.273839 0.249158 -1 -1 -1 -1 40 14012 42 7.79418e+06 4.91458e+06 763742. 2357.23 7.80 1.66763 1.46752 27732 185676 -1 11431 21 7670 9036 921671 269036 8.55559 8.55559 -694.235 -8.55559 0 0 999570. 3085.09 0.04 0.36 0.15 -1 -1 0.04 0.166579 0.14786 962 544 418 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_24.v common 10.07 vpr 73.32 MiB 0.15 11604 -1 -1 1 0.26 -1 -1 36112 -1 -1 175 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75084 22 19 2105 1529 1 1224 223 18 18 324 clb mult_36 auto 33.8 MiB 0.82 7856 45515 10622 31014 3879 73.3 MiB 0.82 0.01 8.93681 -595.083 -8.93681 8.93681 0.35 0.00381823 0.00346963 0.275426 0.250002 -1 -1 -1 -1 46 14077 24 7.79418e+06 4.99065e+06 895831. 2764.91 5.04 1.60029 1.40502 29024 211752 -1 11512 22 7514 8893 918553 261407 8.35219 8.35219 -631.356 -8.35219 0 0 1.09776e+06 3388.15 0.04 0.37 0.17 -1 -1 0.04 0.180825 0.160726 1000 563 437 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_25.v common 10.13 vpr 73.51 MiB 0.16 11912 -1 -1 1 0.28 -1 -1 36424 -1 -1 182 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75272 22 19 2201 1591 1 1284 230 18 18 324 clb mult_36 auto 33.8 MiB 0.85 8224 50918 12167 30031 8720 73.5 MiB 0.83 0.01 8.99737 -625.34 -8.99737 8.99737 0.36 0.00397983 0.00362109 0.314202 0.285111 -1 -1 -1 -1 48 14542 36 7.79418e+06 5.0794e+06 935225. 2886.50 4.88 1.31157 1.15852 29348 218440 -1 11961 24 7008 8736 915317 241367 8.56039 8.56039 -704.083 -8.56039 0 0 1.13028e+06 3488.51 0.04 0.40 0.17 -1 -1 0.04 0.204017 0.181375 1042 586 456 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_26.v common 8.53 vpr 73.86 MiB 0.16 11876 -1 -1 1 0.27 -1 -1 37400 -1 -1 189 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75628 22 19 2275 1648 1 1320 237 18 18 324 clb mult_36 auto 34.1 MiB 0.81 8346 50814 11462 34501 4851 73.9 MiB 0.96 0.01 9.09558 -657.157 -9.09558 9.09558 0.36 0.00436876 0.00398285 0.319295 0.290452 -1 -1 -1 -1 44 15339 45 7.79418e+06 5.16814e+06 850563. 2625.19 3.22 1.21177 1.07151 28700 205432 -1 12115 22 7823 9299 982087 267789 8.25188 8.25188 -856.357 -8.25188 0 0 1.07356e+06 3313.45 0.04 0.38 0.16 -1 -1 0.04 0.191349 0.170229 1080 605 475 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_27.v common 15.88 vpr 74.38 MiB 0.17 12296 -1 -1 1 0.32 -1 -1 36844 -1 -1 199 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76168 22 19 2385 1724 1 1395 248 19 19 361 clb auto 34.5 MiB 0.87 8353 59376 14664 39126 5586 74.4 MiB 1.05 0.01 9.03062 -667.978 -9.03062 9.03062 0.40 0.00460919 0.00421162 0.363484 0.330023 -1 -1 -1 -1 42 16704 48 8.16184e+06 5.69092e+06 904410. 2505.29 10.08 2.07236 1.82372 31162 217923 -1 12970 23 9018 10799 1228060 332168 8.43914 8.43914 -824.709 -8.43914 0 0 1.15452e+06 3198.10 0.05 0.46 0.17 -1 -1 0.05 0.21151 0.188231 1136 642 494 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77352 22 19 2565 1853 1 1503 265 22 22 484 mult_36 auto 36.2 MiB 0.97 9808 64015 16460 42593 4962 75.5 MiB 1.13 0.02 9.05375 -732.273 -9.05375 9.05375 0.55 0.00470731 0.00428202 0.384556 0.348512 -1 -1 -1 -1 40 18429 28 1.26954e+07 6.28977e+06 1.17677e+06 2431.33 24.28 2.52808 2.22106 41974 287914 -1 15451 24 9834 11638 1274098 332704 8.80894 8.80894 -983.307 -8.80894 0 0 1.53957e+06 3180.94 0.06 0.49 0.23 -1 -1 0.06 0.230917 0.205166 1226 694 532 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_30.v common 30.96 vpr 76.09 MiB 0.18 12684 -1 -1 1 0.33 -1 -1 37320 -1 -1 221 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77912 22 19 2639 1910 1 1539 271 22 22 484 mult_36 auto 36.4 MiB 0.97 10302 64219 16193 42182 5844 76.1 MiB 1.11 0.02 9.22277 -769.765 -9.22277 9.22277 0.55 0.00470315 0.00427788 0.370428 0.335355 -1 -1 -1 -1 40 19440 32 1.26954e+07 6.36584e+06 1.17677e+06 2431.33 24.43 2.31453 2.03196 41974 287914 -1 16183 23 10677 12986 1545071 400344 8.83708 8.83708 -956.651 -8.83708 0 0 1.53957e+06 3180.94 0.06 0.53 0.23 -1 -1 0.06 0.225759 0.200111 1264 713 551 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_31.v common 36.68 vpr 76.55 MiB 0.19 13056 -1 -1 1 0.34 -1 -1 37400 -1 -1 231 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78384 22 19 2744 1981 1 1609 281 22 22 484 mult_36 auto 36.9 MiB 0.98 10126 69281 17690 45544 6047 76.5 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87468 22 19 4241 3053 1 2487 411 25 25 625 clb auto 44.6 MiB 1.46 17117 127152 34394 82360 10398 85.4 MiB 2.38 0.03 9.74538 -1337.51 -9.74538 9.74538 0.72 0.00741054 0.00670671 0.661797 0.592729 -1 -1 -1 -1 48 30943 45 1.58291e+07 9.67405e+06 1.86575e+06 2985.21 7.70 2.31897 2.0396 56784 439662 -1 24260 24 15548 18942 2246437 579527 9.03454 9.03454 -1610.92 -9.03454 0 0 2.25743e+06 3611.89 0.10 0.80 0.34 -1 -1 0.10 0.366347 0.324821 2056 1163 893 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_49.v common 33.98 vpr 85.96 MiB 0.29 17048 -1 -1 1 0.62 -1 -1 41120 -1 -1 367 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88028 22 19 4346 3124 1 2556 422 25 25 625 clb auto 45.0 MiB 1.54 17917 164950 43977 106885 14088 86.0 MiB 2.98 0.03 9.72864 -1222.9 -9.72864 9.72864 0.72 0.00748269 0.00676769 0.832977 0.745272 -1 -1 -1 -1 48 29936 46 1.58291e+07 1.01968e+07 1.86575e+06 2985.21 22.95 4.21972 3.69785 56784 439662 -1 25226 23 13398 16104 1760306 465428 9.24793 9.24793 -1703.69 -9.24793 0 0 2.25743e+06 3611.89 0.10 0.73 0.35 -1 -1 0.10 0.364782 0.323472 2107 1195 912 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_50.v common 18.62 vpr 86.75 MiB 0.29 17068 -1 -1 1 0.62 -1 -1 41008 -1 -1 373 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88828 22 19 4420 3181 1 2593 428 25 25 625 clb auto 45.7 MiB 1.51 18261 148732 41199 95280 12253 86.7 MiB 2.57 0.03 9.79718 -1289.48 -9.79718 9.79718 0.71 0.00764436 0.00689871 0.720103 0.645993 -1 -1 -1 -1 48 31646 38 1.58291e+07 1.02729e+07 1.86575e+06 2985.21 7.90 2.54634 2.24429 56784 439662 -1 25317 22 14234 17411 1948373 506791 9.01254 9.01254 -2044.95 -9.01254 0 0 2.25743e+06 3611.89 0.10 0.86 0.34 -1 -1 0.10 0.407263 0.362966 2145 1214 931 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_51.v common 18.28 vpr 86.97 MiB 0.30 17412 -1 -1 1 0.66 -1 -1 41160 -1 -1 383 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89060 22 19 4524 3251 1 2660 438 25 25 625 clb auto 46.0 MiB 1.53 18966 148356 39141 96657 12558 87.0 MiB 2.65 0.03 9.8742 -1310.12 -9.8742 9.8742 0.71 0.00878717 0.00798343 0.709788 0.637808 -1 -1 -1 -1 48 32817 33 1.58291e+07 1.03997e+07 1.86575e+06 2985.21 8.24 2.45853 2.17254 56784 439662 -1 26245 22 13943 16929 1864054 492094 9.52339 9.52339 -1741.57 -9.52339 0 0 2.25743e+06 3611.89 0.09 0.51 0.25 -1 -1 0.09 0.217762 0.195363 2195 1245 950 19 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml fir_nopipe_52.v common 18.19 vpr 87.73 MiB 0.30 17516 -1 -1 1 0.64 -1 -1 39364 -1 -1 389 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89836 22 19 4598 3308 1 2699 444 25 25 625 clb auto 46.4 MiB 1.56 16791 164665 43738 102572 18355 87.7 MiB 2.77 0.03 9.57983 -1323.89 -9.57983 9.57983 0.71 0.00892576 0.00791173 0.83102 0.74501 -1 -1 -1 -1 50 26877 25 1.58291e+07 1.04757e+07 1.94653e+06 3114.45 7.18 2.79481 2.46273 57408 454416 -1 23850 23 15192 18227 1836466 484557 8.86851 8.86851 -1778.99 -8.86851 0 0 2.32897e+06 3726.35 0.10 0.81 0.36 -1 -1 0.10 0.4043 0.358163 2233 1264 969 19 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt index 3b5b7fa0f97..5e8d0a1b566 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt @@ -1,391 +1,391 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_2ripple_N8_22nm.xml fir_pipe_14.v common 8.50 vpr 71.57 MiB 0.11 10472 -1 -1 1 0.27 -1 -1 35440 -1 -1 65 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73284 22 19 1974 1653 1 1013 110 16 16 256 mult_36 auto 34.0 MiB 0.69 5272 15101 3393 9968 1740 71.6 MiB 0.37 0.01 4.0831 -1115.98 -4.0831 4.0831 0.58 0.0034759 0.00313328 0.217026 0.195977 64 9828 23 6.59459e+06 2.52492e+06 943753. 3686.54 3.60 0.988199 0.864659 27892 240595 -1 8477 16 3926 4549 486168 112677 4.27196 4.27196 -1212.54 -4.27196 0 0 1.19033e+06 4649.74 0.30 0.24 0.21 -1 -1 0.30 0.136181 0.121699 481 708 247 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_15.v common 9.16 vpr 72.44 MiB 0.06 10800 -1 -1 1 0.24 -1 -1 36992 -1 -1 72 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74180 22 19 2144 1789 1 1110 118 16 16 256 mult_36 auto 34.8 MiB 0.98 6136 19192 4400 11965 2827 72.4 MiB 0.47 0.01 4.07762 -1246.61 -4.07762 4.07762 0.53 0.00377881 0.00340845 0.27241 0.245631 68 11309 29 6.59459e+06 3.02225e+06 1.00038e+06 3907.74 3.77 1.15784 1.01647 28404 252462 -1 9516 17 4344 4959 564949 131023 4.27196 4.27196 -1329.64 -4.27196 0 0 1.24648e+06 4869.04 0.30 0.28 0.24 -1 -1 0.30 0.159052 0.141737 521 769 266 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_16.v common 10.44 vpr 72.95 MiB 0.08 10940 -1 -1 1 0.23 -1 -1 36856 -1 -1 74 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74700 22 19 2218 1846 1 1154 120 16 16 256 mult_36 auto 35.3 MiB 0.88 6159 16935 3952 11063 1920 72.9 MiB 0.44 0.01 4.14666 -1298.68 -4.14666 4.14666 0.59 0.00394912 0.00355481 0.245771 0.221636 64 13073 22 6.59459e+06 3.0512e+06 943753. 3686.54 5.23 1.15014 1.00888 27892 240595 -1 10191 20 4784 5574 648344 144961 4.39726 4.39726 -1411.91 -4.39726 0 0 1.19033e+06 4649.74 0.29 0.30 0.21 -1 -1 0.29 0.170515 0.151369 540 788 285 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_17.v common 28.01 vpr 74.32 MiB 0.10 11684 -1 -1 1 0.28 -1 -1 36576 -1 -1 83 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76104 22 19 2536 2130 1 1256 129 16 16 256 mult_36 auto 36.9 MiB 1.18 6865 15729 3064 11003 1662 74.3 MiB 0.42 0.01 4.27196 -1448.46 -4.27196 4.27196 0.58 0.00465454 0.00412377 0.234476 0.211013 62 14881 44 6.59459e+06 3.18149e+06 916467. 3579.95 22.37 2.23199 1.9324 27384 229598 -1 10624 18 4845 5517 591644 141708 4.27196 4.27196 -1513.48 -4.27196 0 0 1.13630e+06 4438.68 0.26 0.30 0.19 -1 -1 0.26 0.179178 0.159375 617 924 304 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_18.v common 9.57 vpr 74.83 MiB 0.10 11884 -1 -1 1 0.31 -1 -1 37200 -1 -1 86 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76624 22 19 2610 2187 1 1305 132 16 16 256 mult_36 auto 37.5 MiB 0.99 6869 16212 3205 10695 2312 74.8 MiB 0.42 0.01 4.03926 -1468.2 -4.03926 4.03926 0.58 0.00449043 0.00402742 0.234775 0.2109 70 12353 27 6.59459e+06 3.22491e+06 1.02522e+06 4004.78 3.93 1.22954 1.06835 28912 262511 -1 10716 20 5011 5723 704649 159235 4.27196 4.27196 -1543.19 -4.27196 0 0 1.29210e+06 5047.26 0.31 0.34 0.25 -1 -1 0.31 0.199818 0.1773 636 943 323 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_19.v common 10.50 vpr 75.61 MiB 0.11 12332 -1 -1 1 0.23 -1 -1 36868 -1 -1 91 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77428 22 19 2778 2321 1 1401 138 16 16 256 mult_36 auto 38.4 MiB 0.98 7751 20074 4172 13462 2440 75.6 MiB 0.50 0.01 4.20832 -1614.09 -4.20832 4.20832 0.59 0.00455987 0.00407148 0.282142 0.252858 70 14091 32 6.59459e+06 3.69329e+06 1.02522e+06 4004.78 4.69 1.46178 1.27549 28912 262511 -1 11597 19 5221 6080 670296 155538 4.27196 4.27196 -1747.26 -4.27196 0 0 1.29210e+06 5047.26 0.31 0.34 0.25 -1 -1 0.31 0.20489 0.182093 676 1002 342 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_20.v common 11.55 vpr 76.22 MiB 0.14 12328 -1 -1 1 0.36 -1 -1 36916 -1 -1 93 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78052 22 19 2852 2378 1 1441 140 16 16 256 mult_36 auto 39.0 MiB 1.20 7701 24098 5487 15382 3229 76.2 MiB 0.69 0.01 4.14666 -1615.69 -4.14666 4.14666 0.59 0.00482598 0.00432145 0.385718 0.345251 68 15216 40 6.59459e+06 3.72224e+06 1.00038e+06 3907.74 5.20 1.61757 1.41891 28404 252462 -1 12039 17 5419 6476 661435 153008 4.27196 4.27196 -1732.55 -4.27196 0 0 1.24648e+06 4869.04 0.32 0.34 0.23 -1 -1 0.32 0.201544 0.180315 695 1021 361 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_21.v common 13.54 vpr 77.15 MiB 0.15 12796 -1 -1 1 0.34 -1 -1 37844 -1 -1 97 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79000 22 19 3057 2549 1 1544 144 16 16 256 mult_36 auto 40.0 MiB 1.31 9367 24272 5008 16124 3140 77.1 MiB 0.68 0.01 4.39726 -1835.45 -4.39726 4.39726 0.58 0.00532694 0.00478054 0.376655 0.338089 74 16942 47 6.59459e+06 3.78015e+06 1.07073e+06 4182.55 6.89 2.11826 1.85409 29424 273870 -1 13957 14 5924 6833 901877 190814 4.52256 4.52256 -1968.88 -4.52256 0 0 1.33358e+06 5209.30 0.32 0.36 0.25 -1 -1 0.32 0.186047 0.16608 742 1099 380 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_22.v common 12.36 vpr 77.33 MiB 0.11 13000 -1 -1 1 0.38 -1 -1 37952 -1 -1 100 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79184 22 19 3131 2606 1 1587 147 16 16 256 mult_36 auto 40.3 MiB 1.11 8900 25689 5397 16690 3602 77.3 MiB 0.70 0.01 4.27196 -1832.45 -4.27196 4.27196 0.56 0.00564151 0.00505803 0.391706 0.351179 74 16546 36 6.59459e+06 3.82357e+06 1.07073e+06 4182.55 5.80 1.71816 1.50682 29424 273870 -1 13593 21 6218 7124 883830 200504 4.27196 4.27196 -1953.42 -4.27196 0 0 1.33358e+06 5209.30 0.32 0.45 0.24 -1 -1 0.32 0.256768 0.228242 762 1118 399 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_23.v common 14.10 vpr 78.45 MiB 0.13 13308 -1 -1 1 0.37 -1 -1 38060 -1 -1 107 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80332 22 19 3301 2742 1 1685 155 18 18 324 mult_36 auto 41.3 MiB 1.00 9550 28859 6368 19463 3028 78.4 MiB 0.57 0.01 4.27196 -1973.15 -4.27196 4.27196 0.66 0.00634227 0.00573287 0.287066 0.258115 68 18693 46 8.13932e+06 4.3209e+06 1.31159e+06 4048.11 7.26 1.84939 1.62041 36620 334356 -1 14822 18 6572 7617 914655 195234 4.39726 4.39726 -2060.9 -4.39726 0 0 1.63345e+06 5041.52 0.42 0.44 0.31 -1 -1 0.42 0.239853 0.214582 802 1179 418 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_24.v common 12.49 vpr 78.90 MiB 0.14 13444 -1 -1 1 0.29 -1 -1 38112 -1 -1 109 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80796 22 19 3375 2799 1 1732 157 18 18 324 mult_36 auto 41.8 MiB 0.75 10056 25960 5726 17532 2702 78.9 MiB 0.71 0.01 4.27196 -2004.23 -4.27196 4.27196 0.77 0.00625433 0.00566837 0.392726 0.352573 76 17719 30 8.13932e+06 4.34985e+06 1.43297e+06 4422.75 5.70 1.77721 1.56248 38232 369828 -1 14833 17 6600 7437 899992 195667 4.39726 4.39726 -2169.68 -4.39726 0 0 1.77541e+06 5479.65 0.46 0.43 0.33 -1 -1 0.46 0.242617 0.21773 821 1198 437 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_25.v common 13.23 vpr 79.76 MiB 0.14 14020 -1 -1 1 0.37 -1 -1 38096 -1 -1 116 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81676 22 19 3615 3005 1 1836 164 18 18 324 mult_36 auto 42.7 MiB 1.03 10729 33764 7877 22457 3430 79.8 MiB 0.90 0.01 4.39726 -2180.78 -4.39726 4.39726 0.78 0.00623701 0.00557538 0.503163 0.449551 76 19342 24 8.13932e+06 4.45118e+06 1.43297e+06 4422.75 5.58 1.93758 1.70715 38232 369828 -1 16315 17 6932 7862 1003575 222232 4.39726 4.39726 -2258.25 -4.39726 0 0 1.77541e+06 5479.65 0.46 0.52 0.33 -1 -1 0.46 0.27578 0.248193 877 1293 456 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_26.v common 15.22 vpr 80.33 MiB 0.15 14088 -1 -1 1 0.44 -1 -1 38552 -1 -1 118 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82260 22 19 3689 3062 1 1874 166 18 18 324 mult_36 auto 43.3 MiB 1.16 10442 30262 6705 20097 3460 80.3 MiB 0.77 0.01 4.27196 -2184.83 -4.27196 4.27196 0.79 0.00652778 0.00585374 0.404966 0.361867 72 20476 50 8.13932e+06 4.48013e+06 1.37338e+06 4238.83 7.42 2.18124 1.91119 37588 355536 -1 16153 20 7464 8416 998033 217072 4.14666 4.14666 -2311.78 -4.14666 0 0 1.72054e+06 5310.31 0.47 0.50 0.39 -1 -1 0.47 0.292601 0.260921 896 1312 475 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_27.v common 14.26 vpr 81.57 MiB 0.21 14520 -1 -1 1 0.45 -1 -1 38396 -1 -1 126 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83528 22 19 3871 3210 1 1982 175 18 18 324 mult_36 auto 44.4 MiB 1.24 11174 29515 6552 19982 2981 81.6 MiB 0.80 0.01 4.27196 -2274.04 -4.27196 4.27196 0.78 0.00630671 0.00561642 0.439461 0.393044 68 21260 31 8.13932e+06 4.99193e+06 1.31159e+06 4048.11 6.40 2.09377 1.83035 36620 334356 -1 17367 17 7795 9201 990857 222794 4.39726 4.39726 -2515.29 -4.39726 0 0 1.63345e+06 5041.52 0.42 0.49 0.30 -1 -1 0.42 0.282366 0.253531 944 1385 494 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_28.v common 13.93 vpr 81.64 MiB 0.14 14688 -1 -1 1 0.47 -1 -1 38576 -1 -1 128 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83604 22 19 3945 3267 1 2025 177 18 18 324 mult_36 auto 44.7 MiB 1.09 11734 34897 7640 23359 3898 81.6 MiB 0.90 0.01 4.27196 -2285.03 -4.27196 4.27196 0.77 0.00668871 0.00599553 0.483753 0.431257 72 22190 34 8.13932e+06 5.02088e+06 1.37338e+06 4238.83 5.98 2.12639 1.84804 37588 355536 -1 17870 17 7943 9223 1126928 247605 4.39726 4.39726 -2508.33 -4.39726 0 0 1.72054e+06 5310.31 0.45 0.56 0.30 -1 -1 0.45 0.304202 0.272596 962 1404 513 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_29.v common 18.58 vpr 82.79 MiB 0.19 14976 -1 -1 1 0.49 -1 -1 39616 -1 -1 135 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84780 22 19 4159 3447 1 2141 185 22 22 484 mult_36 auto 45.8 MiB 1.44 13174 35953 8427 24187 3339 82.8 MiB 1.04 0.02 4.22237 -2488.49 -4.22237 4.22237 1.18 0.00856951 0.00780558 0.564857 0.507552 72 25377 43 1.32347e+07 5.5182e+06 2.11301e+06 4365.72 8.73 2.57868 2.27583 56918 551676 -1 20346 15 8444 9848 1257155 262005 4.39726 4.39726 -2750.66 -4.39726 0 0 2.64603e+06 5467.00 0.75 0.46 0.50 -1 -1 0.75 0.2482 0.223951 1015 1491 532 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_30.v common 18.97 vpr 84.25 MiB 0.19 15232 -1 -1 1 0.52 -1 -1 40872 -1 -1 137 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86276 22 19 4233 3504 1 2181 187 22 22 484 mult_36 auto 46.4 MiB 1.32 13110 38635 8392 26373 3870 84.3 MiB 1.00 0.01 4.08302 -2563.57 -4.08302 4.08302 1.21 0.00716477 0.00630509 0.530592 0.472881 68 25874 37 1.32347e+07 5.54715e+06 2.01763e+06 4168.66 9.32 2.41307 2.11127 55470 518816 -1 20145 22 8858 10316 1212837 260181 4.14666 4.14666 -2787.95 -4.14666 0 0 2.51205e+06 5190.18 0.65 0.59 0.44 -1 -1 0.65 0.338688 0.299762 1034 1510 551 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_31.v common 18.06 vpr 85.23 MiB 0.23 15608 -1 -1 1 0.54 -1 -1 40796 -1 -1 143 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87276 22 19 4410 3647 1 2284 193 22 22 484 mult_36 auto 47.4 MiB 1.13 14030 46981 10944 31495 4542 85.2 MiB 1.28 0.02 4.39726 -2691.53 -4.39726 4.39726 1.26 0.00865791 0.00769648 0.685382 0.611844 76 25587 29 1.32347e+07 5.63401e+06 2.20457e+06 4554.90 8.03 2.41776 2.11977 57882 574062 -1 21637 17 8701 9904 1360390 269571 4.64786 4.64786 -2958.16 -4.64786 0 0 2.73077e+06 5642.09 0.76 0.63 0.37 -1 -1 0.76 0.339392 0.307222 1077 1578 570 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_32.v common 21.69 vpr 84.51 MiB 0.21 15728 -1 -1 1 0.55 -1 -1 40596 -1 -1 145 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86536 22 19 4484 3704 1 2331 195 22 22 484 mult_36 auto 47.4 MiB 1.32 14336 39180 9212 26344 3624 84.5 MiB 1.07 0.02 4.27196 -2750.64 -4.27196 4.27196 1.30 0.00779802 0.00686165 0.574051 0.513729 74 27846 43 1.32347e+07 5.66296e+06 2.15943e+06 4461.62 11.13 2.7468 2.41532 57402 562966 -1 21950 17 9362 10872 1422997 286951 4.52256 4.52256 -3005.56 -4.52256 0 0 2.68771e+06 5553.12 0.74 0.66 0.53 -1 -1 0.74 0.333597 0.299696 1096 1597 589 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_33.v common 22.52 vpr 86.98 MiB 0.26 16636 -1 -1 1 0.59 -1 -1 41576 -1 -1 157 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89064 22 19 4843 4029 1 2441 208 22 22 484 mult_36 auto 49.7 MiB 1.74 14676 47024 10400 32136 4488 87.0 MiB 1.30 0.02 4.39726 -2845.68 -4.39726 4.39726 1.30 0.00826196 0.00738647 0.697696 0.62331 78 24684 29 1.32347e+07 6.23266e+06 2.25108e+06 4650.99 10.99 3.39692 2.97879 58850 595650 -1 21723 14 8860 10340 1224784 254736 4.39726 4.39726 -3004.01 -4.39726 0 0 2.82299e+06 5832.63 0.74 0.56 0.53 -1 -1 0.74 0.31281 0.283115 1185 1756 608 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_34.v common 23.60 vpr 86.76 MiB 0.29 16752 -1 -1 1 0.62 -1 -1 41480 -1 -1 160 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88844 22 19 4917 4086 1 2486 211 22 22 484 mult_36 auto 50.2 MiB 1.67 14916 46609 10188 31704 4717 86.8 MiB 1.24 0.02 4.27196 -2997.24 -4.27196 4.27196 1.27 0.00858556 0.00770115 0.67088 0.597459 80 25429 32 1.32347e+07 6.27609e+06 2.29262e+06 4736.82 12.34 3.4883 3.04762 59334 607116 -1 22295 17 9208 10622 1372836 273552 4.27196 4.27196 -3123.26 -4.27196 0 0 2.87723e+06 5944.70 0.75 0.61 0.49 -1 -1 0.75 0.336562 0.300767 1205 1775 627 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_35.v common 20.24 vpr 87.50 MiB 0.25 17108 -1 -1 1 0.68 -1 -1 41776 -1 -1 163 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89604 22 19 5093 4228 1 2588 214 22 22 484 mult_36 auto 50.9 MiB 1.67 15536 45583 9917 31556 4110 87.5 MiB 1.27 0.02 4.27196 -3005.45 -4.27196 4.27196 1.31 0.00869664 0.00777674 0.669261 0.594241 76 28352 31 1.32347e+07 6.31951e+06 2.20457e+06 4554.90 9.25 2.8244 2.47362 57882 574062 -1 23607 17 9965 11831 1457758 304984 4.39726 4.39726 -3480.44 -4.39726 0 0 2.73077e+06 5642.09 0.74 0.67 0.43 -1 -1 0.74 0.353488 0.321039 1248 1842 646 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_36.v common 22.73 vpr 87.92 MiB 0.25 17160 -1 -1 1 0.67 -1 -1 41868 -1 -1 165 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90028 22 19 5167 4285 1 2632 216 22 22 484 mult_36 auto 51.4 MiB 1.63 15667 41624 8267 29885 3472 87.9 MiB 1.23 0.02 4.33362 -3152.9 -4.33362 4.33362 1.28 0.00850204 0.00759229 0.636531 0.565249 74 29785 34 1.32347e+07 6.34846e+06 2.15943e+06 4461.62 11.37 3.30946 2.8967 57402 562966 -1 24080 19 10244 12040 1518165 313102 4.52256 4.52256 -3590.71 -4.52256 0 0 2.68771e+06 5553.12 0.75 0.71 0.49 -1 -1 0.75 0.40039 0.357387 1267 1861 665 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_37.v common 23.77 vpr 89.23 MiB 0.26 17788 -1 -1 1 0.66 -1 -1 40800 -1 -1 173 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91368 22 19 5380 4464 1 2743 225 24 24 576 mult_36 auto 52.8 MiB 1.91 17323 51525 11897 34432 5196 89.2 MiB 1.39 0.02 4.28601 -3284.49 -4.28601 4.28601 1.54 0.00857551 0.00763061 0.733055 0.64925 74 30303 40 1.59675e+07 6.86027e+06 2.56259e+06 4448.94 10.91 3.19892 2.80024 67906 667765 -1 25244 18 10317 12089 1522453 322878 4.39726 4.39726 -3731.23 -4.39726 0 0 3.19068e+06 5539.38 0.95 0.75 0.60 -1 -1 0.95 0.40953 0.366886 1321 1947 684 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_38.v common 22.68 vpr 89.94 MiB 0.17 17808 -1 -1 1 0.71 -1 -1 42296 -1 -1 176 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92100 22 19 5454 4521 1 2787 228 24 24 576 mult_36 auto 52.9 MiB 2.02 17173 57996 13827 39781 4388 89.4 MiB 1.61 0.02 4.52256 -3242.13 -4.52256 4.52256 1.46 0.00925643 0.00828699 0.842234 0.748468 74 29865 34 1.59675e+07 6.90369e+06 2.56259e+06 4448.94 9.75 3.22568 2.83864 67906 667765 -1 25656 15 10421 12099 1547300 316808 4.64786 4.64786 -3606.77 -4.64786 0 0 3.19068e+06 5539.38 0.98 0.68 0.62 -1 -1 0.98 0.359616 0.32315 1340 1966 703 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_39.v common 25.20 vpr 90.11 MiB 0.21 18144 -1 -1 1 0.71 -1 -1 40084 -1 -1 180 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92272 22 19 5629 4662 1 2884 232 24 24 576 mult_36 auto 53.8 MiB 2.03 18624 55768 13035 37822 4911 90.1 MiB 1.61 0.02 4.39726 -3391.54 -4.39726 4.39726 1.50 0.0104887 0.00942536 0.862312 0.77126 76 33253 33 1.59675e+07 6.9616e+06 2.61600e+06 4541.67 11.98 3.38951 2.98079 68478 680951 -1 27050 17 10922 12570 1623278 339627 4.52256 4.52256 -3618.17 -4.52256 0 0 3.24203e+06 5628.53 0.93 0.73 0.59 -1 -1 0.93 0.390966 0.349857 1381 2032 722 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_40.v common 106.73 vpr 91.25 MiB 0.15 18340 -1 -1 1 0.75 -1 -1 42292 -1 -1 182 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93440 22 19 5703 4719 1 2932 234 24 24 576 mult_36 auto 54.2 MiB 2.06 17761 53514 12161 36873 4480 90.6 MiB 1.51 0.02 4.3337 -3472.19 -4.3337 4.3337 1.47 0.0105528 0.00951556 0.779612 0.694323 70 33764 46 1.59675e+07 6.99055e+06 2.45377e+06 4260.01 93.93 6.55011 5.67694 66754 640332 -1 27180 18 11294 13295 1660649 350009 4.39726 4.39726 -3935.92 -4.39726 0 0 3.09179e+06 5367.68 0.84 0.73 0.53 -1 -1 0.84 0.400462 0.355338 1400 2051 741 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_41.v common 28.65 vpr 92.59 MiB 0.22 18828 -1 -1 1 0.74 -1 -1 41616 -1 -1 190 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94816 22 19 5950 4932 1 3040 243 24 24 576 mult_36 auto 55.3 MiB 2.19 19478 54819 12176 38018 4625 91.5 MiB 1.41 0.02 4.41131 -3650.22 -4.41131 4.41131 1.44 0.00941679 0.00837831 0.711187 0.628289 80 31276 23 1.59675e+07 7.50235e+06 2.72095e+06 4723.87 15.35 3.98026 3.46891 70206 720185 -1 27478 16 10740 12213 1485213 299160 4.52256 4.52256 -3708.57 -4.52256 0 0 3.41546e+06 5929.62 0.96 0.70 0.62 -1 -1 0.96 0.397874 0.356582 1461 2153 760 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_42.v common 24.36 vpr 92.43 MiB 0.21 19056 -1 -1 1 0.62 -1 -1 42764 -1 -1 193 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94644 22 19 6024 4989 1 3083 246 24 24 576 mult_36 auto 56.0 MiB 2.07 19232 63386 14561 42862 5963 92.0 MiB 1.77 0.02 4.64786 -3641.46 -4.64786 4.64786 1.43 0.0112474 0.010131 0.930823 0.832762 76 33762 25 1.59675e+07 7.54578e+06 2.61600e+06 4541.67 10.82 3.38503 2.97948 68478 680951 -1 28522 16 11374 13382 1767274 362795 4.77316 4.77316 -3938.14 -4.77316 0 0 3.24203e+06 5628.53 0.92 0.78 0.55 -1 -1 0.92 0.417719 0.37574 1480 2172 779 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_43.v common 35.71 vpr 93.63 MiB 0.30 19448 -1 -1 1 0.89 -1 -1 43352 -1 -1 199 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 95880 22 19 6198 5129 1 3182 252 24 24 576 mult_36 auto 56.7 MiB 2.19 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100084 22 19 6735 5564 1 3478 270 24 24 576 mult_36 auto 59.6 MiB 2.33 22209 70030 15451 47782 6797 95.9 MiB 2.09 0.02 4.41516 -4128.21 -4.41516 4.41516 1.47 0.0129228 0.0116882 1.09035 0.970827 84 37671 32 1.59675e+07 8.27472e+06 2.84938e+06 4946.85 19.62 5.16013 4.52241 71930 760447 -1 31070 17 12543 14162 1836210 367421 4.52256 4.52256 -4366.36 -4.52256 0 0 3.60864e+06 6265.01 1.06 0.86 0.55 -1 -1 1.06 0.485985 0.435523 1656 2428 874 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_48.v common 33.45 vpr 97.87 MiB 0.32 20468 -1 -1 1 0.97 -1 -1 44052 -1 -1 218 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100220 22 19 6809 5621 1 3528 272 24 24 576 mult_36 auto 60.2 MiB 2.27 22399 68109 15563 46856 5690 96.2 MiB 1.89 0.02 4.28601 -4165.16 -4.28601 4.28601 1.51 0.0106728 0.00949716 0.930706 0.824444 84 37990 31 1.59675e+07 8.30367e+06 2.84938e+06 4946.85 18.68 4.78227 4.17358 71930 760447 -1 31425 16 12475 14355 1676213 339117 4.64786 4.64786 -4427.09 -4.64786 0 0 3.60864e+06 6265.01 1.05 0.83 0.62 -1 -1 1.05 0.476709 0.428619 1674 2447 893 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_49.v common 30.74 vpr 104.11 MiB 0.26 21080 -1 -1 1 1.14 -1 -1 44408 -1 -1 228 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106608 22 19 7094 5872 1 3643 283 24 24 576 mult_36 auto 61.6 MiB 2.42 22044 72667 16155 50381 6131 97.9 MiB 2.20 0.03 4.16456 -4302.53 -4.16456 4.16456 1.47 0.0132913 0.0117975 1.12979 0.99479 78 36952 26 1.59675e+07 8.84444e+06 2.67122e+06 4637.53 15.11 5.14497 4.49556 69630 706637 -1 31678 15 13251 15339 1784571 373556 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1 1.11 -1 -1 44760 -1 -1 235 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106064 22 19 7344 6071 1 3784 290 24 24 576 mult_36 auto 62.9 MiB 2.61 23160 75092 17160 51061 6871 99.0 MiB 2.23 0.03 4.28601 -4423.35 -4.28601 4.28601 1.55 0.0133859 0.0120886 1.16131 1.03723 80 39279 28 1.59675e+07 8.94577e+06 2.72095e+06 4723.87 20.13 5.30123 4.63659 70206 720185 -1 33312 15 13811 15847 1871805 392568 4.52256 4.52256 -4830.06 -4.52256 0 0 3.41546e+06 5929.62 1.07 0.89 0.58 -1 -1 1.07 0.477973 0.430588 1808 2655 950 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_pipe_52.v common 33.54 vpr 106.84 MiB 0.21 21728 -1 -1 1 0.94 -1 -1 45300 -1 -1 237 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 109400 22 19 7418 6128 1 3829 292 24 24 576 mult_36 auto 63.4 MiB 2.53 24388 75796 17173 51253 7370 99.4 MiB 1.97 0.02 4.39726 -4541.6 -4.39726 4.39726 1.42 0.0121864 0.0108831 0.960739 0.84753 82 40166 40 1.59675e+07 8.97472e+06 2.78508e+06 4835.20 18.23 5.40215 4.7012 70778 734779 -1 34142 16 13821 15840 1861707 392582 4.52256 4.52256 -4916.53 -4.52256 0 0 3.48632e+06 6052.64 0.92 0.89 0.59 -1 -1 0.92 0.502002 0.449718 1827 2674 969 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_14.v common 9.57 vpr 67.63 MiB 0.09 9420 -1 -1 1 0.13 -1 -1 34724 -1 -1 43 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69256 22 19 1246 925 1 719 88 16 16 256 mult_36 auto 29.9 MiB 1.06 3708 12178 3140 7111 1927 67.6 MiB 0.29 0.00 7.85627 -369.053 -7.85627 7.85627 0.56 0.00247974 0.00227123 0.164562 0.151153 56 7704 42 6.59459e+06 2.20645e+06 849745. 3319.32 4.60 0.792333 0.701862 26364 208198 -1 6616 32 8380 9269 1473487 377056 8.18784 8.18784 -442.129 -8.18784 0 0 1.04740e+06 4091.43 0.25 0.51 0.24 -1 -1 0.25 0.174145 0.155285 299 344 247 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_15.v common 8.47 vpr 68.37 MiB 0.10 9592 -1 -1 1 0.16 -1 -1 35180 -1 -1 46 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70012 22 19 1344 989 1 778 92 16 16 256 mult_36 auto 30.5 MiB 0.89 4253 11891 2718 7916 1257 68.4 MiB 0.29 0.00 8.06786 -397.609 -8.06786 8.06786 0.58 0.00265339 0.00243857 0.163296 0.149912 54 9006 35 6.59459e+06 2.64588e+06 829453. 3240.05 3.79 0.796672 0.706837 26108 202796 -1 7077 27 6857 7815 969928 231501 8.88753 8.88753 -500.255 -8.88753 0 0 1.02522e+06 4004.78 0.24 0.35 0.17 -1 -1 0.24 0.148959 0.132915 321 369 266 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_16.v common 9.84 vpr 68.77 MiB 0.11 9752 -1 -1 1 0.17 -1 -1 35168 -1 -1 48 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70424 22 19 1418 1046 1 822 94 16 16 256 mult_36 auto 30.9 MiB 1.08 4528 13087 3331 8118 1638 68.8 MiB 0.34 0.01 7.80064 -415.87 -7.80064 7.80064 0.58 0.00301012 0.00277729 0.190385 0.174644 60 8307 44 6.59459e+06 2.67484e+06 890343. 3477.90 4.96 0.900933 0.799135 27128 224764 -1 7269 23 7299 8032 994162 223606 8.50533 8.50533 -467.681 -8.50533 0 0 1.11577e+06 4358.47 0.27 0.34 0.18 -1 -1 0.27 0.136378 0.121633 340 388 285 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_17.v common 10.49 vpr 69.04 MiB 0.11 10164 -1 -1 1 0.18 -1 -1 35384 -1 -1 52 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70692 22 19 1518 1112 1 879 98 16 16 256 mult_36 auto 31.3 MiB 1.02 4723 16523 4141 9979 2403 69.0 MiB 0.48 0.01 8.49449 -420.557 -8.49449 8.49449 0.66 0.00306434 0.00276878 0.261531 0.239561 56 9780 47 6.59459e+06 2.73274e+06 849745. 3319.32 5.12 1.05673 0.940382 26364 208198 -1 8101 27 9367 10451 1358860 310210 9.29868 9.29868 -518.713 -9.29868 0 0 1.04740e+06 4091.43 0.25 0.45 0.19 -1 -1 0.25 0.168453 0.150261 365 415 304 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_18.v common 11.55 vpr 69.42 MiB 0.08 10380 -1 -1 1 0.19 -1 -1 34960 -1 -1 55 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71088 22 19 1592 1169 1 918 101 16 16 256 mult_36 auto 31.5 MiB 1.29 5255 15846 3816 10145 1885 69.4 MiB 0.43 0.01 8.73075 -474.97 -8.73075 8.73075 0.54 0.00363037 0.00333098 0.234126 0.214278 58 9951 50 6.59459e+06 2.77617e+06 871168. 3403.00 6.13 1.0597 0.940004 26872 219187 -1 8328 26 8188 9162 1100395 244875 8.96668 8.96668 -544.981 -8.96668 0 0 1.09288e+06 4269.05 0.31 0.41 0.20 -1 -1 0.31 0.174447 0.155683 383 434 323 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_19.v common 11.58 vpr 69.89 MiB 0.05 10540 -1 -1 1 0.22 -1 -1 35332 -1 -1 58 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71564 22 19 1688 1231 1 975 105 16 16 256 mult_36 auto 32.2 MiB 1.26 5522 18136 4926 9933 3277 69.9 MiB 0.33 0.00 8.61576 -458.576 -8.61576 8.61576 0.58 0.00158923 0.00144049 0.173046 0.158003 58 11561 41 6.59459e+06 3.21559e+06 871168. 3403.00 6.32 1.01078 0.895587 26872 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10.09 vpr 70.92 MiB 0.13 11064 -1 -1 1 0.22 -1 -1 35788 -1 -1 62 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72620 22 19 1859 1351 1 1072 109 16 16 256 mult_36 auto 33.2 MiB 1.38 6071 17789 4553 10762 2474 70.9 MiB 0.47 0.01 8.64699 -503.256 -8.64699 8.64699 0.57 0.00350866 0.00321066 0.255118 0.233082 70 10334 32 6.59459e+06 3.2735e+06 1.02522e+06 4004.78 4.12 1.1358 1.00634 28912 262511 -1 9048 24 8163 9276 1068033 251456 8.68598 8.68598 -630.827 -8.68598 0 0 1.29210e+06 5047.26 0.33 0.45 0.26 -1 -1 0.33 0.190795 0.170811 445 500 380 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_22.v common 11.76 vpr 71.06 MiB 0.14 11192 -1 -1 1 0.23 -1 -1 35848 -1 -1 66 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72768 22 19 1933 1408 1 1112 113 16 16 256 mult_36 auto 33.5 MiB 1.56 6284 16766 3772 10688 2306 71.1 MiB 0.44 0.01 8.66433 -531.367 -8.66433 8.66433 0.57 0.00358871 0.00327439 0.235653 0.214767 64 12202 40 6.59459e+06 3.3314e+06 943753. 3686.54 5.63 1.18362 1.04832 27892 240595 -1 9937 26 8773 9855 1261410 275837 8.85048 8.85048 -653.969 -8.85048 0 0 1.19033e+06 4649.74 0.29 0.49 0.23 -1 -1 0.29 0.220799 0.198239 464 519 399 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_23.v common 13.12 vpr 71.43 MiB 0.14 11392 -1 -1 1 0.24 -1 -1 36044 -1 -1 68 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73144 22 19 2031 1472 1 1172 116 18 18 324 mult_36 auto 34.0 MiB 1.74 6825 18164 4253 11642 2269 71.4 MiB 0.49 0.01 8.63545 -565.294 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75180 22 19 2385 1724 1 1377 131 18 18 324 mult_36 auto 36.2 MiB 1.78 8472 26027 6274 16532 3221 73.4 MiB 0.69 0.01 8.72365 -592.733 -8.72365 8.72365 0.75 0.00437438 0.00398433 0.368738 0.33545 58 17784 50 8.13932e+06 4.35501e+06 1.14310e+06 3528.09 11.45 1.60024 1.4182 34680 290288 -1 14148 29 14549 16458 2410411 525176 9.27518 9.27518 -913.009 -9.27518 0 0 1.43297e+06 4422.75 0.35 0.73 0.25 -1 -1 0.35 0.258717 0.230231 575 642 494 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_28.v common 13.73 vpr 73.90 MiB 0.18 12284 -1 -1 1 0.33 -1 -1 36780 -1 -1 83 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75676 22 19 2459 1781 1 1418 132 18 18 324 mult_36 auto 36.6 MiB 2.05 8415 20232 4376 13738 2118 73.9 MiB 0.55 0.01 8.74245 -615.172 -8.74245 8.74245 0.76 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v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77420 22 19 2744 1981 1 1589 143 22 22 484 mult_36 auto 38.3 MiB 2.25 10398 27745 6556 18229 2960 75.6 MiB 0.79 0.01 8.84777 -733.653 -8.84777 8.84777 1.21 0.0050278 0.00457911 0.39794 0.361066 60 21030 47 1.32347e+07 4.91023e+06 1.79840e+06 3715.71 62.39 3.13351 2.7603 53054 462096 -1 16299 28 16051 18584 2592891 539995 9.38798 9.38798 -984.877 -9.38798 0 0 2.25108e+06 4650.99 0.59 0.83 0.38 -1 -1 0.59 0.297336 0.264934 665 745 570 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_32.v common 18.89 vpr 75.58 MiB 0.14 12912 -1 -1 1 0.34 -1 -1 36856 -1 -1 96 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77392 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79456 22 19 3175 2293 1 1835 158 22 22 484 mult_36 auto 40.4 MiB 3.51 11333 30475 6946 20367 3162 77.6 MiB 0.87 0.01 9.75629 -817.637 -9.75629 9.75629 1.21 0.00575594 0.00522535 0.444008 0.402507 66 21761 48 1.32347e+07 5.50888e+06 1.96511e+06 4060.15 57.53 4.0587 3.55958 54986 507526 -1 17539 27 16171 18953 2330366 501744 9.95932 9.95932 -1222.31 -9.95932 0 0 2.45963e+06 5081.88 0.66 0.86 0.43 -1 -1 0.66 0.347439 0.310801 773 865 665 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_37.v common 26.60 vpr 78.42 MiB 0.24 14392 -1 -1 1 0.43 -1 -1 37452 -1 -1 111 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80304 22 19 3280 2364 1 1905 163 24 24 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fir_nopipe_45.v common 26.06 vpr 81.98 MiB 0.25 15932 -1 -1 1 0.55 -1 -1 40488 -1 -1 135 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83944 22 19 3989 2869 1 2317 189 24 24 576 mult_36 auto 45.0 MiB 4.61 14618 41381 9719 27735 3927 82.0 MiB 1.20 0.02 9.77027 -1011.74 -9.77027 9.77027 1.47 0.00736802 0.00668993 0.588856 0.531874 72 25523 37 1.59675e+07 7.1022e+06 2.50747e+06 4353.24 11.47 2.51799 2.2285 67330 654343 -1 21225 23 16401 19162 2396371 518493 9.82682 9.82682 -1397.87 -9.82682 0 0 3.14081e+06 5452.80 0.91 0.90 0.55 -1 -1 0.91 0.37998 0.340237 975 1094 836 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_46.v common 29.93 vpr 82.05 MiB 0.14 16060 -1 -1 1 0.54 -1 -1 40688 -1 -1 136 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84020 22 19 4063 2926 1 2354 190 24 24 576 mult_36 auto 44.9 MiB 4.94 16350 37864 7792 26746 3326 82.1 MiB 1.14 0.02 9.83665 -1114.77 -9.83665 9.83665 1.50 0.00740843 0.00663842 0.54478 0.488634 82 25929 47 1.59675e+07 7.11667e+06 2.78508e+06 4835.20 15.04 3.2069 2.82375 70778 734779 -1 22200 23 15637 18321 2342525 476667 9.76082 9.76082 -1542.32 -9.76082 0 0 3.48632e+06 6052.64 0.98 0.78 0.64 -1 -1 0.98 0.322008 0.287989 993 1113 855 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_47.v common 25.24 vpr 82.53 MiB 0.26 16636 -1 -1 1 0.53 -1 -1 40820 -1 -1 141 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84508 22 19 4167 2996 1 2420 195 24 24 576 mult_36 auto 45.3 MiB 4.57 16260 49350 11375 33104 4871 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83.79 MiB 0.16 17144 -1 -1 1 0.67 -1 -1 41040 -1 -1 148 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85796 22 19 4420 3181 1 2563 203 24 24 576 mult_36 auto 47.2 MiB 5.26 17398 44307 10226 29911 4170 83.8 MiB 1.37 0.02 9.9037 -1079.02 -9.9037 9.9037 1.52 0.00831944 0.00739092 0.668411 0.598925 74 29993 39 1.59675e+07 7.68637e+06 2.56259e+06 4448.94 13.19 2.72523 2.40927 67906 667765 -1 25064 27 22957 25885 3706669 745505 9.89712 9.89712 -1512.67 -9.89712 0 0 3.19068e+06 5539.38 0.92 1.25 0.54 -1 -1 0.92 0.468746 0.417267 1082 1214 931 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_51.v common 29.07 vpr 84.34 MiB 0.27 17280 -1 -1 1 0.73 -1 -1 41072 -1 -1 152 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86360 22 19 4524 3251 1 2633 207 24 24 576 mult_36 auto 47.4 MiB 5.06 17274 43047 9353 29279 4415 84.3 MiB 1.13 0.02 9.72425 -1170.65 -9.72425 9.72425 1.50 0.00836409 0.00742991 0.5227 0.466561 76 29407 46 1.59675e+07 7.74428e+06 2.61600e+06 4541.67 13.39 2.72234 2.40206 68478 680951 -1 24555 25 19224 22166 3043731 614947 10.2548 10.2548 -1642.4 -10.2548 0 0 3.24203e+06 5628.53 0.89 1.10 0.55 -1 -1 0.89 0.452964 0.405044 1107 1245 950 19 0 0 -k6_frac_2ripple_N8_22nm.xml fir_nopipe_52.v common 28.26 vpr 84.80 MiB 0.30 17348 -1 -1 1 0.67 -1 -1 39500 -1 -1 155 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86832 22 19 4598 3308 1 2667 210 24 24 576 mult_36 auto 48.0 MiB 5.62 17604 46386 10173 32285 3928 84.8 MiB 1.48 0.02 9.68009 -1080.95 -9.68009 9.68009 1.59 0.00915384 0.0082116 0.70414 0.632133 72 30917 38 1.59675e+07 7.7877e+06 2.50747e+06 4353.24 11.45 2.81989 2.49644 67330 654343 -1 25360 25 21418 25117 3240485 694413 10.206 10.206 -1662.84 -10.206 0 0 3.14081e+06 5452.80 0.89 1.15 0.56 -1 -1 0.89 0.452531 0.404064 1127 1264 969 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_14.v common 9.62 vpr 71.29 MiB 0.11 10476 -1 -1 1 0.25 -1 -1 35508 -1 -1 65 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73000 22 19 1974 1653 1 1013 110 16 16 256 mult_36 auto 33.6 MiB 0.45 5297 17205 4342 10377 2486 71.3 MiB 0.42 0.01 4.14666 -1129.87 -4.14666 4.14666 0.58 0.00339471 0.00305405 0.248201 0.223626 56 11347 43 6.62819e+06 2.54052e+06 849745. 3319.32 4.90 1.11777 0.974098 26364 208198 -1 9317 19 4256 4818 612410 141530 4.39726 4.39726 -1244.22 -4.39726 0 0 1.04740e+06 4091.43 0.25 0.29 0.18 -1 -1 0.25 0.154654 0.137773 481 708 247 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_15.v common 9.84 vpr 72.22 MiB 0.08 10828 -1 -1 1 0.28 -1 -1 36908 -1 -1 72 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73952 22 19 2144 1789 1 1107 118 16 16 256 mult_36 auto 34.4 MiB 0.65 5790 18036 4123 11366 2547 72.2 MiB 0.41 0.00 4.11968 -1267.13 -4.11968 4.11968 0.60 0.00166501 0.00149431 0.220697 0.197374 58 11809 27 6.62819e+06 3.03953e+06 871168. 3403.00 4.87 1.10123 0.960951 26872 219187 -1 9868 19 4677 5264 620916 144337 4.14666 4.14666 -1356.44 -4.14666 0 0 1.09288e+06 4269.05 0.26 0.31 0.20 -1 -1 0.26 0.181583 0.162619 521 769 266 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_16.v common 32.82 vpr 72.61 MiB 0.09 10936 -1 -1 1 0.29 -1 -1 37020 -1 -1 74 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74348 22 19 2218 1846 1 1153 120 16 16 256 mult_36 auto 34.8 MiB 0.65 5931 16640 3652 10868 2120 72.6 MiB 0.41 0.01 4.14666 -1288.47 -4.14666 4.14666 0.57 0.00377805 0.00339693 0.234481 0.211024 60 12726 33 6.62819e+06 3.06896e+06 890343. 3477.90 27.70 2.238 1.94709 27128 224764 -1 10016 27 4853 5474 1043418 337630 4.27196 4.27196 -1404.7 -4.27196 0 0 1.11577e+06 4358.47 0.27 0.46 0.19 -1 -1 0.27 0.218022 0.192869 540 788 285 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_17.v common 30.59 vpr 74.12 MiB 0.14 11752 -1 -1 1 0.27 -1 -1 36588 -1 -1 83 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 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-k6_frac_2uripple_N8_22nm.xml fir_pipe_20.v common 12.79 vpr 75.91 MiB 0.15 12328 -1 -1 1 0.31 -1 -1 37000 -1 -1 93 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77736 22 19 2852 2378 1 1440 140 16 16 256 mult_36 auto 38.6 MiB 0.79 8294 22646 5123 14901 2622 75.9 MiB 0.60 0.01 4.2084 -1649.58 -4.2084 4.2084 0.59 0.00519432 0.00459622 0.330436 0.295579 68 16097 38 6.62819e+06 3.74456e+06 1.00038e+06 3907.74 6.65 1.6338 1.43308 28404 252462 -1 12428 32 5526 6490 1025857 306320 4.39726 4.39726 -1796.73 -4.39726 0 0 1.24648e+06 4869.04 0.32 0.59 0.24 -1 -1 0.32 0.329705 0.29122 695 1021 361 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_21.v common 11.23 vpr 76.87 MiB 0.13 12808 -1 -1 1 0.34 -1 -1 37736 -1 -1 97 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78712 22 19 3057 2549 1 1542 144 16 16 256 mult_36 auto 39.6 MiB 0.88 8673 23895 5161 15228 3506 76.9 MiB 0.64 0.01 4.52256 -1743.09 -4.52256 4.52256 0.59 0.00509947 0.00455544 0.355011 0.31784 74 15361 35 6.62819e+06 3.80343e+06 1.07073e+06 4182.55 5.08 1.69428 1.48117 29424 273870 -1 12772 16 5516 6283 721984 162116 4.39726 4.39726 -1867.34 -4.39726 0 0 1.33358e+06 5209.30 0.37 0.37 0.23 -1 -1 0.37 0.219266 0.196635 742 1099 380 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_22.v common 11.01 vpr 77.04 MiB 0.14 13056 -1 -1 1 0.35 -1 -1 38004 -1 -1 100 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78884 22 19 3131 2606 1 1585 147 16 16 256 mult_36 auto 39.8 MiB 0.80 8566 16401 3002 11439 1960 77.0 MiB 0.46 0.01 4.20292 -1804.73 -4.20292 4.20292 0.58 0.00505943 0.00451654 0.250613 0.224921 70 15569 27 6.62819e+06 3.84757e+06 1.02522e+06 4004.78 5.00 1.57019 1.37496 28912 262511 -1 12915 18 5834 6628 735961 170375 4.27196 4.27196 -1954.66 -4.27196 0 0 1.29210e+06 5047.26 0.31 0.39 0.23 -1 -1 0.31 0.237635 0.212022 762 1118 399 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_23.v common 12.69 vpr 78.08 MiB 0.23 13264 -1 -1 1 0.36 -1 -1 37940 -1 -1 107 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79956 22 19 3301 2742 1 1683 155 18 18 324 mult_36 auto 40.7 MiB 0.77 9538 29691 6508 19815 3368 78.1 MiB 0.78 0.01 4.16456 -1929.44 -4.16456 4.16456 0.77 0.00543034 0.00486181 0.427346 0.382197 74 17207 25 8.18539e+06 4.34658e+06 1.40368e+06 4332.34 5.68 1.81502 1.59881 37912 362744 -1 14522 15 6182 7157 877389 187757 4.39726 4.39726 -2097.58 -4.39726 0 0 1.74764e+06 5393.95 0.44 0.39 0.32 -1 -1 0.44 0.220923 0.197744 802 1179 418 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_24.v common 14.98 vpr 78.37 MiB 0.16 13344 -1 -1 1 0.39 -1 -1 38272 -1 -1 109 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80252 22 19 3375 2799 1 1730 157 18 18 324 mult_36 auto 41.1 MiB 0.72 9993 25960 5685 17809 2466 78.4 MiB 0.69 0.01 4.14666 -1987.87 -4.14666 4.14666 0.78 0.00654875 0.00596535 0.380892 0.340812 66 20196 47 8.18539e+06 4.37601e+06 1.27759e+06 3943.17 8.17 2.00995 1.75922 36296 327148 -1 15425 16 6577 7667 933401 201564 4.27196 4.27196 -2140.03 -4.27196 0 0 1.59950e+06 4936.74 0.40 0.40 0.29 -1 -1 0.40 0.219115 0.195599 821 1198 437 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_25.v common 15.04 vpr 79.46 MiB 0.12 13996 -1 -1 1 0.41 -1 -1 38108 -1 -1 116 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81364 22 19 3615 3005 1 1835 164 18 18 324 mult_36 auto 42.2 MiB 0.80 11154 29284 6310 19654 3320 79.5 MiB 0.80 0.01 4.14666 -2148.01 -4.14666 4.14666 0.79 0.00586019 0.00523374 0.423027 0.375862 74 20993 41 8.18539e+06 4.47902e+06 1.40368e+06 4332.34 7.70 2.07686 1.81166 37912 362744 -1 16756 18 7134 8004 1128968 235536 4.39726 4.39726 -2385.21 -4.39726 0 0 1.74764e+06 5393.95 0.46 0.53 0.37 -1 -1 0.46 0.278899 0.249426 877 1293 456 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_26.v common 13.31 vpr 79.98 MiB 0.19 14172 -1 -1 1 0.42 -1 -1 38464 -1 -1 118 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81896 22 19 3689 3062 1 1872 166 18 18 324 mult_36 auto 42.9 MiB 0.73 10890 31630 7268 20957 3405 80.0 MiB 0.87 0.01 4.27196 -2181.76 -4.27196 4.27196 0.76 0.00606494 0.00540887 0.467527 0.418559 70 19335 31 8.18539e+06 4.50845e+06 1.34436e+06 4149.26 5.95 2.19285 1.93908 37264 347768 -1 16326 14 6732 7802 873866 193746 4.64786 4.64786 -2351.91 -4.64786 0 0 1.69344e+06 5226.66 0.44 0.45 0.31 -1 -1 0.44 0.250603 0.228761 896 1312 475 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_27.v common 14.41 vpr 80.97 MiB 0.24 14340 -1 -1 1 0.46 -1 -1 38332 -1 -1 126 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82916 22 19 3871 3210 1 1979 175 18 18 324 mult_36 auto 43.9 MiB 0.98 11935 36361 8458 24158 3745 81.0 MiB 0.94 0.01 4.27196 -2285.74 -4.27196 4.27196 0.75 0.00613784 0.00547274 0.503502 0.449047 74 21341 43 8.18539e+06 5.02217e+06 1.40368e+06 4332.34 6.40 2.23969 1.95842 37912 362744 -1 17442 28 7329 8264 1322461 328195 4.39726 4.39726 -2440.95 -4.39726 0 0 1.74764e+06 5393.95 0.44 0.76 0.34 -1 -1 0.44 0.424379 0.377177 944 1385 494 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_28.v common 14.60 vpr 81.27 MiB 0.18 14592 -1 -1 1 0.47 -1 -1 38396 -1 -1 128 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83216 22 19 3945 3267 1 2024 177 18 18 324 mult_36 auto 44.3 MiB 0.90 12138 33905 7358 22743 3804 81.3 MiB 0.87 0.01 4.2084 -2321.46 -4.2084 4.2084 0.75 0.00632408 0.00564454 0.466734 0.414007 70 21577 28 8.18539e+06 5.0516e+06 1.34436e+06 4149.26 7.04 2.21927 1.94826 37264 347768 -1 17740 16 7557 8666 1010701 226948 4.39726 4.39726 -2498.89 -4.39726 0 0 1.69344e+06 5226.66 0.44 0.51 0.32 -1 -1 0.44 0.287858 0.262005 962 1404 513 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_29.v common 17.47 vpr 82.56 MiB 0.20 14908 -1 -1 1 0.53 -1 -1 39728 -1 -1 135 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84544 22 19 4159 3447 1 2140 185 22 22 484 mult_36 auto 45.6 MiB 0.82 12922 36479 8016 24715 3748 82.6 MiB 0.96 0.01 4.27196 -2537.11 -4.27196 4.27196 1.19 0.00683899 0.00611129 0.513952 0.458181 72 24568 26 1.33067e+07 5.5506e+06 2.11301e+06 4365.72 7.99 2.21268 1.9378 56918 551676 -1 19622 18 7762 9120 1147231 234160 4.52256 4.52256 -2684.21 -4.52256 0 0 2.64603e+06 5467.00 0.81 0.59 0.50 -1 -1 0.81 0.327241 0.293336 1015 1491 532 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_30.v common 17.71 vpr 82.84 MiB 0.22 15256 -1 -1 1 0.50 -1 -1 40852 -1 -1 137 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84824 22 19 4233 3504 1 2179 187 22 22 484 mult_36 auto 45.8 MiB 1.00 12963 38101 8862 25522 3717 82.8 MiB 1.03 0.01 4.16456 -2491.22 -4.16456 4.16456 1.21 0.00728231 0.00641715 0.549748 0.485614 68 24170 26 1.33067e+07 5.58003e+06 2.01763e+06 4168.66 8.33 2.19929 1.91941 55470 518816 -1 19865 19 8475 9594 1119874 244580 4.27196 4.27196 -2605.99 -4.27196 0 0 2.51205e+06 5190.18 0.79 0.62 0.32 -1 -1 0.79 0.347772 0.311818 1034 1510 551 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_31.v common 19.21 vpr 84.78 MiB 0.19 15500 -1 -1 1 0.53 -1 -1 40888 -1 -1 143 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86816 22 19 4410 3647 1 2283 193 22 22 484 mult_36 auto 46.6 MiB 1.09 13261 42525 9859 28389 4277 84.8 MiB 1.12 0.01 4.20292 -2606.72 -4.20292 4.20292 1.23 0.00792387 0.00715548 0.607786 0.542467 68 26796 45 1.33067e+07 5.66832e+06 2.01763e+06 4168.66 9.59 2.60643 2.28092 55470 518816 -1 20620 18 9122 10596 1262791 274069 4.27196 4.27196 -2850.79 -4.27196 0 0 2.51205e+06 5190.18 0.66 0.58 0.41 -1 -1 0.66 0.313357 0.279844 1077 1578 570 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_32.v common 17.78 vpr 83.86 MiB 0.24 15564 -1 -1 1 0.65 -1 -1 40628 -1 -1 145 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85876 22 19 4484 3704 1 2328 195 22 22 484 mult_36 auto 46.7 MiB 1.10 14086 42570 10140 28365 4065 83.9 MiB 1.19 0.01 4.27196 -2656.53 -4.27196 4.27196 1.26 0.0074867 0.00669018 0.632666 0.566104 76 25174 22 1.33067e+07 5.69776e+06 2.20457e+06 4554.90 7.48 2.3411 2.05657 57882 574062 -1 21201 17 8736 10203 1208112 256654 4.52256 4.52256 -2899.81 -4.52256 0 0 2.73077e+06 5642.09 0.76 0.56 0.47 -1 -1 0.76 0.308971 0.276204 1096 1597 589 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_33.v common 19.59 vpr 86.55 MiB 0.18 16668 -1 -1 1 0.72 -1 -1 41584 -1 -1 157 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88624 22 19 4843 4029 1 2439 208 22 22 484 mult_36 auto 48.9 MiB 0.97 14930 47640 11114 32188 4338 86.5 MiB 1.36 0.02 4.39726 -2986.1 -4.39726 4.39726 1.21 0.00807193 0.00721129 0.720009 0.641175 72 28519 46 1.33067e+07 6.27034e+06 2.11301e+06 4365.72 9.31 2.92459 2.56125 56918 551676 -1 22603 18 8941 10278 1322426 274519 4.52256 4.52256 -3196.98 -4.52256 0 0 2.64603e+06 5467.00 0.69 0.62 0.44 -1 -1 0.69 0.344955 0.307973 1185 1756 608 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_34.v common 19.92 vpr 86.19 MiB 0.21 16844 -1 -1 1 0.66 -1 -1 41520 -1 -1 160 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88260 22 19 4917 4086 1 2483 211 22 22 484 mult_36 auto 49.5 MiB 1.07 15547 44101 10019 30168 3914 86.2 MiB 1.19 0.02 4.52256 -2910.9 -4.52256 4.52256 1.29 0.00850993 0.00765958 0.628457 0.56061 72 28972 45 1.33067e+07 6.31449e+06 2.11301e+06 4365.72 9.40 3.01041 2.65124 56918 551676 -1 23425 15 9029 10536 1317654 275619 4.77316 4.77316 -3227.02 -4.77316 0 0 2.64603e+06 5467.00 0.72 0.59 0.48 -1 -1 0.72 0.310447 0.278067 1205 1775 627 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_35.v common 19.61 vpr 86.97 MiB 0.19 17008 -1 -1 1 0.61 -1 -1 41780 -1 -1 163 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89056 22 19 5093 4228 1 2586 214 22 22 484 mult_36 auto 50.4 MiB 1.15 14368 50056 10737 34290 5029 87.0 MiB 1.36 0.02 4.0831 -3007.04 -4.0831 4.0831 1.30 0.00833478 0.00743564 0.68954 0.611847 70 26841 32 1.33067e+07 6.35863e+06 2.06816e+06 4273.05 8.76 2.96404 2.60102 56434 539830 -1 22266 17 9508 10903 1285918 285062 4.27196 4.27196 -3253.37 -4.27196 0 0 2.60483e+06 5381.88 0.75 0.66 0.47 -1 -1 0.75 0.377564 0.341646 1248 1842 646 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_36.v common 28.12 vpr 87.36 MiB 0.27 17256 -1 -1 1 0.66 -1 -1 42020 -1 -1 165 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89452 22 19 5167 4285 1 2630 216 22 22 484 mult_36 auto 50.8 MiB 1.17 17033 50682 11615 34548 4519 87.4 MiB 1.48 0.02 4.41516 -3107.93 -4.41516 4.41516 1.32 0.0095028 0.00838872 0.767027 0.68235 78 30105 32 1.33067e+07 6.38806e+06 2.25108e+06 4650.99 16.67 3.91497 3.43174 58850 595650 -1 24920 16 9692 11251 1483545 305489 4.52256 4.52256 -3425.17 -4.52256 0 0 2.82299e+06 5832.63 0.79 0.67 0.52 -1 -1 0.79 0.358575 0.322125 1267 1861 665 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_37.v common 22.25 vpr 88.59 MiB 0.24 17688 -1 -1 1 0.71 -1 -1 40812 -1 -1 173 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90716 22 19 5380 4464 1 2739 225 24 24 576 mult_36 auto 52.1 MiB 1.21 16600 56313 12680 38864 4769 88.6 MiB 1.57 0.02 4.39726 -3260.8 -4.39726 4.39726 1.56 0.00877338 0.00782934 0.818708 0.726201 70 30941 28 1.60519e+07 6.90179e+06 2.45377e+06 4260.01 9.63 2.98262 2.61057 66754 640332 -1 25189 16 10124 11953 1441066 304403 4.52256 4.52256 -3510.18 -4.52256 0 0 3.09179e+06 5367.68 0.86 0.69 0.63 -1 -1 0.86 0.381342 0.340062 1321 1947 684 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_38.v common 23.40 vpr 90.68 MiB 0.27 17864 -1 -1 1 0.70 -1 -1 42304 -1 -1 176 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92852 22 19 5454 4521 1 2784 228 24 24 576 mult_36 auto 52.1 MiB 1.20 17686 58692 14006 39560 5126 88.5 MiB 1.63 0.02 4.20237 -3287.95 -4.20237 4.20237 1.47 0.00905596 0.00808648 0.861451 0.765781 80 27661 18 1.60519e+07 6.94594e+06 2.72095e+06 4723.87 11.25 3.6755 3.21596 70206 720185 -1 25044 17 9392 10797 1238597 262408 4.39726 4.39726 -3387.93 -4.39726 0 0 3.41546e+06 5929.62 0.92 0.62 0.58 -1 -1 0.92 0.365106 0.326009 1340 1966 703 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_39.v common 21.01 vpr 92.66 MiB 0.31 18068 -1 -1 1 0.60 -1 -1 40220 -1 -1 180 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94884 22 19 5629 4662 1 2882 232 24 24 576 mult_36 auto 52.9 MiB 1.16 17139 55056 12561 37747 4748 89.5 MiB 1.32 0.01 4.39726 -3372.5 -4.39726 4.39726 1.43 0.00421205 0.00376248 0.673509 0.595022 72 32360 40 1.60519e+07 7.0048e+06 2.50747e+06 4353.24 9.53 3.12732 2.7338 67330 654343 -1 26063 15 10213 11721 1450566 306425 4.52256 4.52256 -3562.16 -4.52256 0 0 3.14081e+06 5452.80 0.88 0.66 0.52 -1 -1 0.88 0.362696 0.325953 1381 2032 722 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_40.v common 23.71 vpr 95.62 MiB 0.17 18332 -1 -1 1 0.64 -1 -1 42224 -1 -1 182 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97920 22 19 5703 4719 1 2929 234 24 24 576 mult_36 auto 53.8 MiB 1.19 17730 54234 12385 37329 4520 90.3 MiB 1.44 0.02 4.27196 -3426.27 -4.27196 4.27196 1.45 0.0096553 0.00863034 0.736039 0.655051 74 32857 35 1.60519e+07 7.03423e+06 2.56259e+06 4448.94 11.86 3.74322 3.27327 67906 667765 -1 27007 17 10660 11973 1577287 328402 4.39726 4.39726 -3639.92 -4.39726 0 0 3.19068e+06 5539.38 0.88 0.72 0.53 -1 -1 0.88 0.399574 0.357659 1400 2051 741 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_41.v common 25.04 vpr 92.39 MiB 0.19 18932 -1 -1 1 0.84 -1 -1 41616 -1 -1 190 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94612 22 19 5950 4932 1 3039 243 24 24 576 mult_36 auto 54.5 MiB 1.28 18494 48755 10232 33831 4692 90.9 MiB 1.31 0.02 4.14666 -3593.15 -4.14666 4.14666 1.49 0.00924519 0.00822018 0.675753 0.598199 78 30524 25 1.60519e+07 7.54795e+06 2.67122e+06 4637.53 12.89 4.04171 3.53277 69630 706637 -1 26409 17 10464 12149 1422734 303195 4.27196 4.27196 -3758.11 -4.27196 0 0 3.35110e+06 5817.88 0.92 0.70 0.57 -1 -1 0.92 0.40952 0.366635 1461 2153 760 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_42.v common 27.13 vpr 92.70 MiB 0.23 18872 -1 -1 1 0.94 -1 -1 42772 -1 -1 193 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94928 22 19 6024 4989 1 3082 246 24 24 576 mult_36 auto 55.2 MiB 1.24 20030 64926 14885 44112 5929 91.5 MiB 1.76 0.02 4.39726 -3645.71 -4.39726 4.39726 1.56 0.00996243 0.008898 0.910422 0.8106 76 36054 42 1.60519e+07 7.5921e+06 2.61600e+06 4541.67 13.78 4.1362 3.61629 68478 680951 -1 29459 18 11439 13299 1697383 348587 4.39726 4.39726 -3948.23 -4.39726 0 0 3.24203e+06 5628.53 1.06 0.83 0.60 -1 -1 1.06 0.459419 0.411692 1480 2172 779 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_43.v common 23.59 vpr 92.35 MiB 0.25 19360 -1 -1 1 1.09 -1 -1 43276 -1 -1 199 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94568 22 19 6198 5129 1 3181 252 24 24 576 mult_36 auto 56.1 MiB 1.30 20168 59082 13911 39065 6106 92.4 MiB 1.54 0.02 4.64786 -3811.84 -4.64786 4.64786 1.45 0.00965356 0.0085898 0.791746 0.702729 74 34701 31 1.60519e+07 7.68039e+06 2.56259e+06 4448.94 10.77 3.6847 3.24442 67906 667765 -1 29515 15 11276 13062 1613817 335267 4.64786 4.64786 -4088.62 -4.64786 0 0 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97556 22 19 6485 5365 1 3338 262 24 24 576 mult_36 auto 57.5 MiB 1.43 21050 68140 15742 46206 6192 93.8 MiB 1.96 0.02 4.3337 -3866.62 -4.3337 4.3337 1.72 0.0110034 0.00985175 1.00708 0.895221 76 37388 40 1.60519e+07 8.20883e+06 2.61600e+06 4541.67 12.17 3.96882 3.48336 68478 680951 -1 29833 26 12212 14243 1891537 439336 4.39726 4.39726 -4071.65 -4.39726 0 0 3.24203e+06 5628.53 0.94 1.11 0.57 -1 -1 0.94 0.649219 0.577456 1593 2342 836 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_46.v common 24.25 vpr 95.32 MiB 0.31 20044 -1 -1 1 1.01 -1 -1 43836 -1 -1 210 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 97604 22 19 6559 5422 1 3380 264 24 24 576 mult_36 auto 57.9 MiB 1.44 20986 65406 14272 45368 5766 94.0 MiB 1.89 0.02 4.41516 -3851.32 -4.41516 4.41516 1.75 0.0104864 0.00925677 0.951179 0.844485 76 35918 33 1.60519e+07 8.23826e+06 2.61600e+06 4541.67 9.96 3.65068 3.18914 68478 680951 -1 30049 16 12176 14229 1658356 357526 4.39726 4.39726 -4137.94 -4.39726 0 0 3.24203e+06 5628.53 0.96 0.81 0.56 -1 -1 0.96 0.45034 0.404231 1613 2361 855 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_47.v common 30.26 vpr 100.97 MiB 0.23 20468 -1 -1 1 0.98 -1 -1 44512 -1 -1 216 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103392 22 19 6735 5564 1 3477 270 24 24 576 mult_36 auto 59.1 MiB 1.55 24055 64798 13570 44576 6652 95.1 MiB 1.71 0.02 4.39726 -4157.74 -4.39726 4.39726 1.78 0.0113045 0.0101147 0.845251 0.755155 86 40233 49 1.60519e+07 8.32656e+06 2.91907e+06 5067.82 15.99 4.313 3.78276 72506 773887 -1 33084 16 12748 14764 2101422 413693 4.64786 4.64786 -4356.52 -4.64786 0 0 3.65856e+06 6351.67 1.02 0.87 0.65 -1 -1 1.02 0.458208 0.411484 1656 2428 874 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_48.v common 35.47 vpr 96.93 MiB 0.32 20664 -1 -1 1 0.95 -1 -1 44236 -1 -1 218 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99252 22 19 6809 5621 1 3526 272 24 24 576 mult_36 auto 59.3 MiB 1.50 22900 73395 16707 49770 6918 95.2 MiB 2.15 0.02 4.39726 -4153.76 -4.39726 4.39726 1.67 0.011406 0.0101958 1.08523 0.969545 80 37824 42 1.60519e+07 8.35599e+06 2.72095e+06 4723.87 20.80 5.22399 4.56195 70206 720185 -1 31870 17 12170 14127 1643072 340205 4.52256 4.52256 -4448.16 -4.52256 0 0 3.41546e+06 5929.62 0.98 0.91 0.60 -1 -1 0.98 0.514534 0.462797 1674 2447 893 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_49.v common 31.44 vpr 97.77 MiB 0.33 21116 -1 -1 1 1.20 -1 -1 44496 -1 -1 228 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100120 22 19 7094 5872 1 3640 283 24 24 576 mult_36 auto 60.8 MiB 1.61 22621 68027 14330 47033 6664 96.8 MiB 1.93 0.02 4.32767 -4362.09 -4.32767 4.32767 1.64 0.0119534 0.0107154 0.980804 0.872047 78 38472 32 1.60519e+07 8.89916e+06 2.67122e+06 4637.53 16.89 5.12848 4.48135 69630 706637 -1 32337 18 12793 14786 1774390 369345 4.39726 4.39726 -4662.48 -4.39726 0 0 3.35110e+06 5817.88 0.96 0.89 0.59 -1 -1 0.96 0.506522 0.451565 1745 2569 912 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_50.v common 42.89 vpr 104.99 MiB 0.34 21260 -1 -1 1 1.07 -1 -1 44300 -1 -1 230 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 107512 22 19 7168 5929 1 3676 285 24 24 576 mult_36 auto 61.3 MiB 1.54 23567 73371 16206 50485 6680 97.6 MiB 2.07 0.02 4.52256 -4404.95 -4.52256 4.52256 1.61 0.0121815 0.0108962 1.01563 0.902893 80 39688 35 1.60519e+07 8.92859e+06 2.72095e+06 4723.87 28.13 5.30125 4.63165 70206 720185 -1 33305 16 12887 14936 1843889 377237 4.64786 4.64786 -4684.92 -4.64786 0 0 3.41546e+06 5929.62 0.97 0.88 0.58 -1 -1 0.97 0.48546 0.433223 1764 2588 931 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_51.v common 35.12 vpr 100.53 MiB 0.29 21748 -1 -1 1 1.16 -1 -1 44852 -1 -1 235 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 102940 22 19 7344 6071 1 3782 290 24 24 576 mult_36 auto 61.8 MiB 1.53 23722 73174 15715 50579 6880 97.9 MiB 2.23 0.02 4.459 -4442.21 -4.459 4.459 1.71 0.0129397 0.0114853 1.13602 1.00367 78 40381 49 1.60519e+07 9.00217e+06 2.67122e+06 4637.53 19.81 5.82881 5.09426 69630 706637 -1 33812 17 13492 15556 1913676 402938 4.39726 4.39726 -4781.62 -4.39726 0 0 3.35110e+06 5817.88 0.99 0.96 0.60 -1 -1 0.99 0.553941 0.498992 1808 2655 950 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_pipe_52.v common 29.93 vpr 103.93 MiB 0.35 21712 -1 -1 1 1.06 -1 -1 45144 -1 -1 237 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 106420 22 19 7418 6128 1 3828 292 24 24 576 mult_36 auto 63.0 MiB 1.65 25005 78700 18301 52935 7464 99.2 MiB 2.24 0.03 4.3337 -4441.83 -4.3337 4.3337 1.62 0.0141833 0.0126136 1.11433 0.987066 82 41723 40 1.60519e+07 9.0316e+06 2.78508e+06 4835.20 14.40 5.09586 4.46474 70778 734779 -1 34399 17 13048 14909 1766649 364634 4.64786 4.64786 -4948.18 -4.64786 0 0 3.48632e+06 6052.64 1.03 0.91 0.62 -1 -1 1.03 0.529155 0.472554 1827 2674 969 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_14.v common 8.30 vpr 67.70 MiB 0.06 9236 -1 -1 1 0.16 -1 -1 34796 -1 -1 43 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69320 22 19 1246 925 1 718 88 16 16 256 mult_36 auto 29.6 MiB 0.40 3890 12373 3373 7466 1534 67.7 MiB 0.29 0.00 7.60941 -361.611 -7.60941 7.60941 0.58 0.00248719 0.00227377 0.168746 0.154814 48 8671 44 6.62819e+06 2.21677e+06 755748. 2952.14 4.19 0.782373 0.696842 25088 180500 -1 6645 23 6937 7779 935577 227413 8.26573 8.26573 -437.931 -8.26573 0 0 916467. 3579.95 0.32 0.34 0.18 -1 -1 0.32 0.131416 0.117582 299 344 247 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_15.v common 7.86 vpr 67.93 MiB 0.10 9568 -1 -1 1 0.16 -1 -1 35164 -1 -1 46 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69560 22 19 1344 989 1 778 92 16 16 256 mult_36 auto 30.1 MiB 0.35 4185 14168 4013 8552 1603 67.9 MiB 0.34 0.00 7.6175 -392.139 -7.6175 7.6175 0.57 0.00268393 0.00245944 0.195077 0.179222 60 7437 28 6.62819e+06 2.65692e+06 890343. 3477.90 3.66 0.798125 0.713421 27128 224764 -1 6562 26 6006 6790 825899 214119 7.65538 7.65538 -446.805 -7.65538 0 0 1.11577e+06 4358.47 0.27 0.34 0.20 -1 -1 0.27 0.146346 0.13072 321 369 266 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_16.v common 7.58 vpr 68.24 MiB 0.11 9564 -1 -1 1 0.17 -1 -1 35172 -1 -1 48 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69880 22 19 1418 1046 1 821 94 16 16 256 mult_36 auto 30.5 MiB 0.39 4487 13513 3432 8383 1698 68.2 MiB 0.33 0.00 7.60494 -393.597 -7.60494 7.60494 0.58 0.0027842 0.00255165 0.187731 0.172143 56 8390 28 6.62819e+06 2.68636e+06 849745. 3319.32 3.33 0.831016 0.737597 26364 208198 -1 7216 25 7078 7963 962371 230897 7.99013 7.99013 -460.438 -7.99013 0 0 1.04740e+06 4091.43 0.25 0.36 0.25 -1 -1 0.25 0.150063 0.134273 340 388 285 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_17.v common 9.38 vpr 68.71 MiB 0.11 10216 -1 -1 1 0.15 -1 -1 35368 -1 -1 52 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70356 22 19 1518 1112 1 879 98 16 16 256 mult_36 auto 31.0 MiB 0.39 4625 16298 4224 8851 3223 68.7 MiB 0.40 0.01 8.32683 -417.873 -8.32683 8.32683 0.58 0.00298677 0.00271368 0.228688 0.209212 58 9112 39 6.62819e+06 2.74522e+06 871168. 3403.00 5.05 0.9919 0.882394 26872 219187 -1 7252 25 7366 7878 922895 225342 9.12512 9.12512 -480.323 -9.12512 0 0 1.09288e+06 4269.05 0.27 0.39 0.19 -1 -1 0.27 0.167818 0.150821 365 415 304 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_18.v common 11.18 vpr 69.09 MiB 0.12 10396 -1 -1 1 0.19 -1 -1 34952 -1 -1 55 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70752 22 19 1592 1169 1 918 101 16 16 256 mult_36 auto 31.2 MiB 0.42 5347 16316 4097 10275 1944 69.1 MiB 0.41 0.01 8.4422 -469.823 -8.4422 8.4422 0.57 0.00307543 0.00281496 0.225945 0.206695 56 10897 47 6.62819e+06 2.78937e+06 849745. 3319.32 6.50 1.05998 0.941705 26364 208198 -1 9026 32 9275 10182 1519161 349464 9.30818 9.30818 -562.145 -9.30818 0 0 1.04740e+06 4091.43 0.25 0.55 0.18 -1 -1 0.25 0.20576 0.183578 383 434 323 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_19.v common 10.03 vpr 69.58 MiB 0.08 10668 -1 -1 1 0.20 -1 -1 35488 -1 -1 58 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71252 22 19 1688 1231 1 976 105 16 16 256 mult_36 auto 31.8 MiB 0.46 5523 17642 4653 10328 2661 69.6 MiB 0.43 0.01 8.2901 -468.025 -8.2901 8.2901 0.57 0.00321502 0.00294453 0.244246 0.223338 58 10958 42 6.62819e+06 3.22951e+06 871168. 3403.00 5.27 1.08965 0.971784 26872 219187 -1 8881 23 8148 9336 1045786 240112 9.19702 9.19702 -670.638 -9.19702 0 0 1.09288e+06 4269.05 0.36 0.44 0.21 -1 -1 0.36 0.170417 0.152624 404 457 342 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_20.v common 9.80 vpr 70.05 MiB 0.08 10652 -1 -1 1 0.22 -1 -1 35588 -1 -1 59 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71732 22 19 1762 1288 1 1014 106 16 16 256 mult_36 auto 32.2 MiB 0.47 5650 16606 4202 10324 2080 70.1 MiB 0.45 0.01 8.4978 -488.18 -8.4978 8.4978 0.57 0.00334718 0.00305518 0.244371 0.222607 56 11507 38 6.62819e+06 3.24423e+06 849745. 3319.32 4.85 1.09951 0.975231 26364 208198 -1 9516 27 10307 11396 1607507 371242 9.22112 9.22112 -579.067 -9.22112 0 0 1.04740e+06 4091.43 0.27 0.59 0.21 -1 -1 0.27 0.202265 0.180619 423 476 361 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_21.v common 10.37 vpr 70.59 MiB 0.13 10924 -1 -1 1 0.23 -1 -1 35984 -1 -1 62 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72284 22 19 1859 1351 1 1072 109 16 16 256 mult_36 auto 32.8 MiB 0.52 6035 17789 4471 10978 2340 70.6 MiB 0.50 0.01 8.38109 -487.093 -8.38109 8.38109 0.58 0.00353177 0.00322401 0.258398 0.235679 60 12117 48 6.62819e+06 3.28838e+06 890343. 3477.90 5.30 1.15998 1.0304 27128 224764 -1 9393 23 8484 9643 1075611 255217 9.04658 9.04658 -638.837 -9.04658 0 0 1.11577e+06 4358.47 0.34 0.43 0.20 -1 -1 0.34 0.187693 0.169332 445 500 380 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_22.v common 9.75 vpr 71.11 MiB 0.15 11060 -1 -1 1 0.23 -1 -1 35992 -1 -1 66 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72816 22 19 1933 1408 1 1111 113 16 16 256 mult_36 auto 33.4 MiB 0.55 6447 14582 3335 9243 2004 71.1 MiB 0.40 0.01 8.38225 -539.049 -8.38225 8.38225 0.52 0.00372084 0.00340025 0.211763 0.193395 66 12032 36 6.62819e+06 3.34724e+06 974584. 3806.97 4.64 1.11576 0.989347 28148 247068 -1 9826 24 8221 9433 1042848 236369 8.80852 8.80852 -690.661 -8.80852 0 0 1.22072e+06 4768.46 0.29 0.44 0.23 -1 -1 0.29 0.195304 0.175492 464 519 399 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_23.v common 12.26 vpr 71.07 MiB 0.15 11404 -1 -1 1 0.25 -1 -1 36004 -1 -1 68 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72780 22 19 2031 1472 1 1174 116 18 18 324 mult_36 auto 33.5 MiB 0.60 6930 17882 4089 11335 2458 71.1 MiB 0.47 0.01 8.41364 -547.214 -8.41364 8.41364 0.75 0.00373301 0.0033942 0.252968 0.230155 60 13146 46 8.18539e+06 3.77267e+06 1.16833e+06 3605.96 6.44 1.26858 1.12367 35004 297736 -1 10629 25 9789 11037 1322884 293485 8.79022 8.79022 -667.882 -8.79022 0 0 1.46313e+06 4515.82 0.37 0.55 0.26 -1 -1 0.37 0.222269 0.199302 486 544 418 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_24.v common 28.06 vpr 71.67 MiB 0.15 11572 -1 -1 1 0.26 -1 -1 36336 -1 -1 71 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73388 22 19 2105 1529 1 1210 119 18 18 324 mult_36 auto 34.0 MiB 0.57 6947 19099 4545 12489 2065 71.7 MiB 0.50 0.01 8.54591 -592.304 -8.54591 8.54591 0.76 0.00387295 0.00353344 0.268825 0.244429 58 13826 37 8.18539e+06 3.81682e+06 1.14310e+06 3528.09 22.14 2.16612 1.90652 34680 290288 -1 11315 25 10013 11336 1455403 323969 9.26762 9.26762 -836.784 -9.26762 0 0 1.43297e+06 4422.75 0.38 0.51 0.26 -1 -1 0.38 0.191148 0.172557 505 563 437 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_25.v common 12.18 vpr 72.28 MiB 0.10 11840 -1 -1 1 0.28 -1 -1 36436 -1 -1 73 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74016 22 19 2201 1591 1 1268 121 18 18 324 mult_36 auto 34.8 MiB 0.59 7634 22247 5441 14246 2560 72.3 MiB 0.59 0.01 8.41835 -567.959 -8.41835 8.41835 0.75 0.00403852 0.00366175 0.317042 0.288294 64 14202 44 8.18539e+06 3.84625e+06 1.23838e+06 3822.15 6.20 1.44631 1.28376 35972 318676 -1 11820 29 12088 13740 1940094 442042 8.68898 8.68898 -781.144 -8.68898 0 0 1.56068e+06 4816.91 0.38 0.65 0.28 -1 -1 0.38 0.246613 0.219596 526 586 456 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_26.v common 11.94 vpr 72.46 MiB 0.10 11936 -1 -1 1 0.28 -1 -1 37420 -1 -1 76 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74204 22 19 2275 1648 1 1306 124 18 18 324 mult_36 auto 35.1 MiB 0.81 7751 20827 4662 13516 2649 72.5 MiB 0.57 0.01 8.56929 -568.623 -8.56929 8.56929 0.77 0.00413781 0.00376541 0.298181 0.271274 60 14701 32 8.18539e+06 3.8904e+06 1.16833e+06 3605.96 5.72 1.33007 1.17753 35004 297736 -1 12032 25 10795 12330 1483067 336752 8.81798 8.81798 -886.816 -8.81798 0 0 1.46313e+06 4515.82 0.37 0.55 0.25 -1 -1 0.37 0.224402 0.199898 546 605 475 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_27.v common 12.20 vpr 73.11 MiB 0.16 12176 -1 -1 1 0.31 -1 -1 36624 -1 -1 82 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74864 22 19 2385 1724 1 1378 131 18 18 324 mult_36 auto 35.7 MiB 0.67 8283 20383 4936 13018 2429 73.1 MiB 0.56 0.01 8.5461 -628.049 -8.5461 8.5461 0.75 0.00441244 0.00400671 0.289094 0.262967 68 14535 41 8.18539e+06 4.37469e+06 1.31159e+06 4048.11 5.93 1.42908 1.26783 36620 334356 -1 12409 26 10631 12441 1427422 320553 8.58227 8.58227 -875.158 -8.58227 0 0 1.63345e+06 5041.52 0.41 0.56 0.28 -1 -1 0.41 0.247584 0.221266 575 642 494 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_28.v common 16.70 vpr 73.46 MiB 0.17 12280 -1 -1 1 0.31 -1 -1 36788 -1 -1 83 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75224 22 19 2459 1781 1 1417 132 18 18 324 mult_36 auto 36.1 MiB 0.64 8787 24252 5813 15988 2451 73.5 MiB 0.63 0.01 8.59036 -640.13 -8.59036 8.59036 0.74 0.00438785 0.00398589 0.335875 0.305032 58 18144 50 8.18539e+06 4.3894e+06 1.14310e+06 3528.09 10.39 1.61231 1.42708 34680 290288 -1 13981 22 13072 15000 1915715 426043 9.02382 9.02382 -822.024 -9.02382 0 0 1.43297e+06 4422.75 0.36 0.64 0.24 -1 -1 0.36 0.241009 0.217144 594 661 513 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_29.v common 17.70 vpr 73.96 MiB 0.18 12728 -1 -1 1 0.32 -1 -1 37292 -1 -1 85 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75732 22 19 2565 1853 1 1485 135 22 22 484 mult_36 auto 36.7 MiB 0.71 9693 25047 5824 16462 2761 74.0 MiB 0.71 0.01 8.56824 -658.817 -8.56824 8.56824 1.22 0.00474006 0.0043231 0.362784 0.329646 64 18425 33 1.33067e+07 4.81483e+06 1.90554e+06 3937.06 9.45 1.53093 1.35853 54502 494576 -1 15063 28 14458 16832 2340289 516030 8.76628 8.76628 -928.497 -8.76628 0 0 2.40101e+06 4960.76 0.62 0.77 0.40 -1 -1 0.62 0.280264 0.250411 619 694 532 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_30.v common 15.00 vpr 74.31 MiB 0.08 12824 -1 -1 1 0.34 -1 -1 37428 -1 -1 89 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76096 22 19 2639 1910 1 1523 139 22 22 484 mult_36 auto 37.1 MiB 0.74 9384 25628 5988 16697 2943 74.3 MiB 0.72 0.01 8.44238 -674.317 -8.44238 8.44238 1.23 0.00474821 0.00431628 0.368392 0.334281 70 15871 29 1.33067e+07 4.87369e+06 2.06816e+06 4273.05 6.97 1.51562 1.34444 56434 539830 -1 14145 24 11726 13596 1807233 398151 9.10687 9.10687 -826.57 -9.10687 0 0 2.60483e+06 5381.88 0.69 0.64 0.44 -1 -1 0.69 0.255512 0.228396 639 713 551 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_31.v common 17.31 vpr 74.87 MiB 0.19 12964 -1 -1 1 0.39 -1 -1 37424 -1 -1 93 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76664 22 19 2744 1981 1 1590 143 22 22 484 mult_36 auto 37.7 MiB 0.74 9784 30356 7187 19530 3639 74.9 MiB 0.86 0.01 8.38567 -675.978 -8.38567 8.38567 1.22 0.00507411 0.00456402 0.440825 0.399147 64 18972 47 1.33067e+07 4.93255e+06 1.90554e+06 3937.06 9.03 1.81872 1.61299 54502 494576 -1 15109 27 13335 15415 2075489 440624 9.05667 9.05667 -930.353 -9.05667 0 0 2.40101e+06 4960.76 0.63 0.71 0.40 -1 -1 0.63 0.28603 0.255035 665 745 570 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_32.v common 59.78 vpr 75.20 MiB 0.13 13060 -1 -1 1 0.42 -1 -1 36820 -1 -1 96 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77008 22 19 2818 2038 1 1627 146 22 22 484 mult_36 auto 37.9 MiB 0.81 9765 27794 6626 18138 3030 75.2 MiB 0.78 0.01 8.43423 -706.833 -8.43423 8.43423 1.24 0.00503391 0.00455887 0.393484 0.356822 68 17281 43 1.33067e+07 4.9767e+06 2.01763e+06 4168.66 51.47 3.45154 3.04118 55470 518816 -1 14549 26 13387 15791 1843918 396984 8.48238 8.48238 -1019.62 -8.48238 0 0 2.51205e+06 5190.18 0.66 0.73 0.35 -1 -1 0.66 0.32025 0.287688 684 764 589 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_33.v common 18.67 vpr 75.77 MiB 0.20 13728 -1 -1 1 0.40 -1 -1 37556 -1 -1 100 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77588 22 19 2923 2109 1 1695 151 22 22 484 mult_36 auto 38.4 MiB 0.73 10394 32632 7799 20384 4449 75.8 MiB 0.93 0.01 9.15948 -780.094 -9.15948 9.15948 1.23 0.00550841 0.00496395 0.466464 0.422627 68 19006 40 1.33067e+07 5.43155e+06 2.01763e+06 4168.66 10.13 1.85464 1.64421 55470 518816 -1 15474 24 12536 14090 1741858 383228 9.73142 9.73142 -1174.71 -9.73142 0 0 2.51205e+06 5190.18 0.66 0.64 0.41 -1 -1 0.66 0.274146 0.24518 710 796 608 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_34.v common 17.07 vpr 76.12 MiB 0.15 13748 -1 -1 1 0.44 -1 -1 37840 -1 -1 101 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77944 22 19 2997 2166 1 1734 152 22 22 484 mult_36 auto 38.9 MiB 1.01 10711 29717 6877 19660 3180 76.1 MiB 0.85 0.01 9.29828 -782.067 -9.29828 9.29828 1.27 0.00537933 0.00488556 0.439577 0.398766 68 19336 39 1.33067e+07 5.44627e+06 2.01763e+06 4168.66 8.09 1.80439 1.59957 55470 518816 -1 15822 25 13222 15017 1923830 410698 9.61867 9.61867 -1083.26 -9.61867 0 0 2.51205e+06 5190.18 0.67 0.74 0.44 -1 -1 0.67 0.31043 0.277578 729 815 627 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_35.v common 18.30 vpr 76.68 MiB 0.23 14092 -1 -1 1 0.43 -1 -1 37608 -1 -1 106 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78520 22 19 3101 2236 1 1801 157 22 22 484 mult_36 auto 39.4 MiB 1.05 11402 28075 6295 18501 3279 76.7 MiB 0.81 0.01 9.47066 -829.471 -9.47066 9.47066 1.22 0.00609179 0.00558557 0.405266 0.367879 70 19800 47 1.33067e+07 5.51985e+06 2.06816e+06 4273.05 9.21 1.86486 1.65176 56434 539830 -1 16867 24 13697 15802 2138431 452706 9.74781 9.74781 -1050.32 -9.74781 0 0 2.60483e+06 5381.88 0.70 0.76 0.44 -1 -1 0.70 0.299055 0.26771 755 846 646 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_36.v common 21.97 vpr 77.04 MiB 0.21 14088 -1 -1 1 0.44 -1 -1 38016 -1 -1 107 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78888 22 19 3175 2293 1 1836 158 22 22 484 mult_36 auto 39.8 MiB 1.13 11170 30902 7166 20385 3351 77.0 MiB 0.94 0.01 9.18378 -834.69 -9.18378 9.18378 1.25 0.00580597 0.00527978 0.477711 0.431692 60 23060 49 1.33067e+07 5.53456e+06 1.79840e+06 3715.71 12.89 2.11193 1.86795 53054 462096 -1 17670 24 14840 17527 2134269 458631 9.53001 9.53001 -1214.3 -9.53001 0 0 2.25108e+06 4650.99 0.61 0.77 0.38 -1 -1 0.61 0.306378 0.273847 773 865 665 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_37.v common 21.82 vpr 77.66 MiB 0.22 14376 -1 -1 1 0.43 -1 -1 37340 -1 -1 111 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79520 22 19 3280 2364 1 1904 163 24 24 576 mult_36 auto 40.5 MiB 1.15 11916 36653 8512 22659 5482 77.7 MiB 1.10 0.01 9.503 -813.596 -9.503 9.503 1.55 0.00616994 0.00541883 0.561311 0.506567 68 21847 36 1.60519e+07 5.98942e+06 2.39371e+06 4155.74 11.44 2.14252 1.89965 65606 615345 -1 17297 31 13826 16479 2281397 551091 9.31947 9.31947 -1215.55 -9.31947 0 0 2.98162e+06 5176.42 0.78 0.89 0.49 -1 -1 0.78 0.378325 0.337347 798 897 684 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_38.v common 19.36 vpr 78.34 MiB 0.28 14508 -1 -1 1 0.44 -1 -1 37968 -1 -1 113 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80220 22 19 3354 2421 1 1941 165 24 24 576 mult_36 auto 41.1 MiB 1.27 13091 35421 8629 23184 3608 78.3 MiB 1.06 0.01 9.56954 -911.791 -9.56954 9.56954 1.50 0.0060493 0.00549289 0.531047 0.479941 70 22176 36 1.60519e+07 6.01886e+06 2.45377e+06 4260.01 8.83 2.08523 1.84725 66754 640332 -1 18678 23 12610 14627 1802919 388775 9.66152 9.66152 -1189.17 -9.66152 0 0 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80760 22 19 3531 2547 1 2046 172 24 24 576 mult_36 auto 41.7 MiB 1.34 13416 38890 9004 25965 3921 78.9 MiB 1.13 0.01 9.43624 -981.01 -9.43624 9.43624 1.43 0.00625586 0.00565441 0.543303 0.489943 70 23523 44 1.60519e+07 6.12186e+06 2.45377e+06 4260.01 11.31 2.23268 1.9759 66754 640332 -1 19563 25 14474 17290 2278221 477004 9.83772 9.83772 -1353.33 -9.83772 0 0 3.09179e+06 5367.68 0.86 0.84 0.51 -1 -1 0.86 0.367156 0.327513 862 965 741 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_41.v common 21.92 vpr 79.35 MiB 0.22 15180 -1 -1 1 0.52 -1 -1 38096 -1 -1 122 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81256 22 19 3634 2616 1 2113 175 24 24 576 mult_36 auto 42.3 MiB 1.31 14260 37339 8299 25744 3296 79.4 MiB 1.14 0.01 9.48942 -936.304 -9.48942 9.48942 1.49 0.00675422 0.00614536 0.558513 0.504178 76 24101 46 1.60519e+07 6.5473e+06 2.61600e+06 4541.67 11.02 2.44748 2.17082 68478 680951 -1 20450 26 13980 16375 2275565 472356 10.0482 10.0482 -1255.71 -10.0482 0 0 3.24203e+06 5628.53 0.92 0.87 0.54 -1 -1 0.92 0.371853 0.332549 886 995 760 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_42.v common 22.42 vpr 80.11 MiB 0.12 15260 -1 -1 1 0.45 -1 -1 38348 -1 -1 125 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82028 22 19 3708 2673 1 2147 178 24 24 576 mult_36 auto 42.9 MiB 1.36 13247 38178 8698 26287 3193 80.1 MiB 1.07 0.01 9.34555 -911.748 -9.34555 9.34555 1.44 0.0064956 0.00588021 0.52583 0.474314 68 24266 46 1.60519e+07 6.59144e+06 2.39371e+06 4155.74 12.11 2.37149 2.09472 65606 615345 -1 19305 25 14215 16917 2027268 431068 9.41247 9.41247 -1370.03 -9.41247 0 0 2.98162e+06 5176.42 0.76 0.76 0.48 -1 -1 0.76 0.345503 0.307881 906 1014 779 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_43.v common 23.50 vpr 80.20 MiB 0.16 15604 -1 -1 1 0.54 -1 -1 38872 -1 -1 129 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82124 22 19 3810 2741 1 2214 182 24 24 576 mult_36 auto 43.1 MiB 1.40 14854 39322 8760 27092 3470 80.2 MiB 1.18 0.01 9.43515 -973.044 -9.43515 9.43515 1.50 0.00665249 0.00603299 0.564376 0.511736 70 26179 39 1.60519e+07 6.6503e+06 2.45377e+06 4260.01 12.41 2.38973 2.11663 66754 640332 -1 21790 27 16236 19013 2690277 570799 10.0622 10.0622 -1353.82 -10.0622 0 0 3.09179e+06 5367.68 0.89 1.00 0.52 -1 -1 0.89 0.406695 0.362835 930 1043 798 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_44.v common 21.15 vpr 80.74 MiB 0.15 15680 -1 -1 1 0.55 -1 -1 38396 -1 -1 132 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82680 22 19 3884 2798 1 2251 185 24 24 576 mult_36 auto 43.6 MiB 1.51 14264 43317 10157 28920 4240 80.7 MiB 1.14 0.01 9.54931 -1049.89 -9.54931 9.54931 1.45 0.00442549 0.0040212 0.566381 0.512217 70 23866 43 1.60519e+07 6.69445e+06 2.45377e+06 4260.01 10.14 2.47136 2.1912 66754 640332 -1 20739 24 16345 18902 2422633 514103 9.94026 9.94026 -1346.73 -9.94026 0 0 3.09179e+06 5367.68 0.84 0.90 0.53 -1 -1 0.84 0.372298 0.33204 949 1062 817 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_45.v common 21.13 vpr 81.10 MiB 0.14 15976 -1 -1 1 0.58 -1 -1 40524 -1 -1 135 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83048 22 19 3989 2869 1 2318 189 24 24 576 mult_36 auto 43.9 MiB 1.45 15002 45717 10664 29972 5081 81.1 MiB 1.34 0.02 9.30374 -1001.57 -9.30374 9.30374 1.52 0.00746911 0.00679006 0.668085 0.604004 74 24106 34 1.60519e+07 7.1346e+06 2.56259e+06 4448.94 9.60 2.47418 2.18875 67906 667765 -1 21115 26 15678 18406 2326491 502931 9.44027 9.44027 -1425.49 -9.44027 0 0 3.19068e+06 5539.38 0.86 0.92 0.59 -1 -1 0.86 0.405328 0.361259 975 1094 836 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_46.v common 24.34 vpr 81.14 MiB 0.24 16108 -1 -1 1 0.56 -1 -1 40476 -1 -1 136 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83088 22 19 4063 2926 1 2357 190 24 24 576 mult_36 auto 44.1 MiB 1.54 15384 39502 8716 27417 3369 81.1 MiB 1.20 0.02 9.25444 -1065.06 -9.25444 9.25444 1.46 0.00819881 0.00737383 0.591398 0.531649 68 28280 44 1.60519e+07 7.14931e+06 2.39371e+06 4155.74 13.33 2.59794 2.29721 65606 615345 -1 22363 25 16582 19483 2454716 510839 9.51877 9.51877 -1579.55 -9.51877 0 0 2.98162e+06 5176.42 0.80 0.77 0.50 -1 -1 0.80 0.295053 0.265261 993 1113 855 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_47.v common 22.95 vpr 81.84 MiB 0.28 16676 -1 -1 1 0.57 -1 -1 40860 -1 -1 141 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83800 22 19 4167 2996 1 2421 195 24 24 576 mult_36 auto 44.9 MiB 1.52 15434 47655 11175 32212 4268 81.8 MiB 1.45 0.02 9.32624 -1067.91 -9.32624 9.32624 1.46 0.00866741 0.00766169 0.705291 0.6329 68 26939 44 1.60519e+07 7.22289e+06 2.39371e+06 4155.74 11.15 2.73486 2.41721 65606 615345 -1 22408 22 17205 20128 2344851 525433 9.69172 9.69172 -1531.77 -9.69172 0 0 2.98162e+06 5176.42 0.89 0.86 0.54 -1 -1 0.89 0.360779 0.3226 1019 1144 874 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_48.v common 26.04 vpr 84.46 MiB 0.28 16560 -1 -1 1 0.62 -1 -1 40944 -1 -1 144 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86488 22 19 4241 3053 1 2459 198 24 24 576 mult_36 auto 45.1 MiB 1.63 16101 43398 9885 28969 4544 82.2 MiB 1.32 0.02 9.15276 -1137.39 -9.15276 9.15276 1.41 0.00812705 0.00725182 0.602704 0.540065 74 28016 46 1.60519e+07 7.26704e+06 2.56259e+06 4448.94 14.11 3.02835 2.67053 67906 667765 -1 23184 26 19200 22279 3097523 635988 10.1736 10.1736 -1421.35 -10.1736 0 0 3.19068e+06 5539.38 0.89 1.12 0.55 -1 -1 0.89 0.441622 0.39392 1038 1163 893 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_49.v common 22.70 vpr 82.50 MiB 0.30 17020 -1 -1 1 0.63 -1 -1 41164 -1 -1 145 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84476 22 19 4346 3124 1 2527 200 24 24 576 mult_36 auto 45.8 MiB 1.58 16303 42248 9563 28218 4467 82.5 MiB 1.25 0.02 9.38798 -1053.9 -9.38798 9.38798 1.45 0.00782229 0.00708899 0.606041 0.545412 76 26459 35 1.60519e+07 7.67775e+06 2.61600e+06 4541.67 10.77 2.5998 2.30202 68478 680951 -1 22900 23 17127 19789 2450260 525170 9.49071 9.49071 -1363.71 -9.49071 0 0 3.24203e+06 5628.53 0.88 0.95 0.57 -1 -1 0.88 0.408657 0.365417 1062 1195 912 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_50.v common 24.93 vpr 84.88 MiB 0.30 16992 -1 -1 1 0.62 -1 -1 40960 -1 -1 148 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86916 22 19 4420 3181 1 2564 203 24 24 576 mult_36 auto 46.2 MiB 1.72 16495 43711 9469 30201 4041 82.7 MiB 1.31 0.02 9.43609 -1064.71 -9.43609 9.43609 1.44 0.0088878 0.00796896 0.634709 0.572282 74 29023 44 1.60519e+07 7.72189e+06 2.56259e+06 4448.94 12.97 2.85564 2.52665 67906 667765 -1 23678 25 18523 22416 2877968 597216 9.48707 9.48707 -1821.24 -9.48707 0 0 3.19068e+06 5539.38 0.86 1.01 0.55 -1 -1 0.86 0.421101 0.376085 1082 1214 931 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_51.v common 23.60 vpr 83.62 MiB 0.31 17388 -1 -1 1 0.50 -1 -1 41132 -1 -1 152 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85628 22 19 4524 3251 1 2634 207 24 24 576 mult_36 auto 46.9 MiB 1.47 16985 41823 9101 28954 3768 83.6 MiB 1.27 0.02 9.734 -1168.67 -9.734 9.734 1.49 0.00828626 0.00752653 0.605156 0.543297 72 29204 35 1.60519e+07 7.78076e+06 2.50747e+06 4353.24 11.88 2.7076 2.39559 67330 654343 -1 24180 25 18625 21935 2835680 592310 9.95301 9.95301 -1799.32 -9.95301 0 0 3.14081e+06 5452.80 0.84 1.10 0.55 -1 -1 0.84 0.463942 0.414065 1107 1245 950 19 0 0 -k6_frac_2uripple_N8_22nm.xml fir_nopipe_52.v common 23.86 vpr 86.70 MiB 0.30 17404 -1 -1 1 0.68 -1 -1 39356 -1 -1 155 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88776 22 19 4598 3308 1 2668 210 24 24 576 mult_36 auto 47.2 MiB 1.76 17259 43266 9678 28409 5179 84.2 MiB 1.25 0.02 9.7565 -1135.89 -9.7565 9.7565 1.46 0.00829854 0.00752642 0.618965 0.557544 72 30374 50 1.60519e+07 7.8249e+06 2.50747e+06 4353.24 11.75 2.94605 2.60428 67330 654343 -1 24994 25 20197 24076 3112218 653789 9.59001 9.59001 -1667.66 -9.59001 0 0 3.14081e+06 5452.80 0.89 1.12 0.53 -1 -1 0.89 0.451547 0.402446 1127 1264 969 19 0 0 -k6_frac_N8_22nm.xml fir_pipe_14.v common 35.06 vpr 70.03 MiB 0.07 10400 -1 -1 8 0.52 -1 -1 34576 -1 -1 79 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71708 22 19 1764 1664 1 1014 124 16 16 256 mult_36 auto 32.0 MiB 0.61 6309 13720 2598 9792 1330 70.0 MiB 0.31 0.01 4.27196 -1341.5 -4.27196 4.27196 0.57 0.00354648 0.00317141 0.178158 0.159799 62 13731 45 6.45408e+06 2.64829e+06 916467. 3579.95 30.10 2.06286 1.78614 26824 229188 -1 9858 17 4242 7313 542219 128340 4.27196 4.27196 -1342.23 -4.27196 0 0 1.13630e+06 4438.68 0.29 0.31 0.20 -1 -1 0.29 0.168254 0.151358 599 966 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_15.v common 9.44 vpr 71.33 MiB 0.12 10904 -1 -1 8 0.42 -1 -1 36132 -1 -1 85 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73044 22 19 1918 1801 1 1104 131 16 16 256 mult_36 auto 32.9 MiB 0.59 6626 16731 3359 11755 1617 71.3 MiB 0.41 0.01 4.52256 -1452.91 -4.52256 4.52256 0.59 0.00446844 0.00396271 0.2364 0.211929 64 12736 29 6.45408e+06 3.12512e+06 943753. 3686.54 4.24 1.25278 1.0975 27332 240185 -1 10846 16 4390 7653 589954 137377 4.39726 4.39726 -1545.05 -4.39726 0 0 1.19033e+06 4649.74 0.30 0.34 0.22 -1 -1 0.30 0.187048 0.169073 651 1047 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_16.v common 9.35 vpr 71.73 MiB 0.10 10872 -1 -1 8 0.52 -1 -1 37432 -1 -1 87 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73448 22 19 1976 1859 1 1141 133 16 16 256 mult_36 auto 33.4 MiB 0.64 7164 16066 3216 11368 1482 71.7 MiB 0.37 0.01 4.28601 -1479.04 -4.28601 4.28601 0.58 0.00387816 0.00346619 0.213837 0.190981 66 14097 31 6.45408e+06 3.15206e+06 974584. 3806.97 4.07 1.22789 1.07012 27588 246658 -1 11314 14 4644 8048 628529 143762 4.39726 4.39726 -1506.32 -4.39726 0 0 1.22072e+06 4768.46 0.30 0.29 0.24 -1 -1 0.30 0.152509 0.136574 679 1086 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_17.v common 10.64 vpr 72.72 MiB 0.19 11888 -1 -1 8 0.54 -1 -1 36740 -1 -1 102 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74464 22 19 2278 2144 1 1269 148 16 16 256 mult_36 auto 34.9 MiB 0.67 8095 16961 3169 12034 1758 72.7 MiB 0.39 0.01 4.27196 -1685.47 -4.27196 4.27196 0.61 0.00431669 0.00384312 0.216345 0.192777 66 15895 38 6.45408e+06 3.35414e+06 974584. 3806.97 4.97 1.40484 1.2203 27588 246658 -1 12871 17 5512 9156 773452 182436 4.14666 4.14666 -1714.79 -4.14666 0 0 1.22072e+06 4768.46 0.29 0.35 0.23 -1 -1 0.29 0.187032 0.166489 768 1242 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_18.v common 10.64 vpr 73.61 MiB 0.13 11900 -1 -1 8 0.64 -1 -1 37788 -1 -1 105 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75380 22 19 2336 2202 1 1299 151 16 16 256 mult_36 auto 35.2 MiB 0.49 8142 19800 3855 14118 1827 73.6 MiB 0.45 0.01 4.27196 -1743.36 -4.27196 4.27196 0.57 0.00455664 0.00406375 0.2538 0.22658 66 16357 31 6.45408e+06 3.39456e+06 974584. 3806.97 5.10 1.41202 1.23044 27588 246658 -1 13041 16 5315 9387 790244 175589 4.27196 4.27196 -1778.91 -4.27196 0 0 1.22072e+06 4768.46 0.29 0.38 0.23 -1 -1 0.29 0.193318 0.172161 794 1281 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_19.v common 24.75 vpr 74.32 MiB 0.14 12416 -1 -1 8 0.68 -1 -1 37468 -1 -1 111 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76104 22 19 2488 2337 1 1399 158 16 16 256 mult_36 auto 36.3 MiB 0.69 9188 20654 3849 14830 1975 74.3 MiB 0.46 0.01 4.52256 -1895.49 -4.52256 4.52256 0.57 0.00473762 0.00422106 0.259355 0.231093 68 18182 48 6.45408e+06 3.87139e+06 1.00038e+06 3907.74 18.65 2.74248 2.3778 27844 252052 -1 14297 34 5758 10179 1038312 262783 4.52256 4.52256 -1955.57 -4.52256 0 0 1.24648e+06 4869.04 0.30 0.58 0.21 -1 -1 0.30 0.341379 0.298117 837 1360 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_20.v common 11.64 vpr 74.53 MiB 0.15 12376 -1 -1 8 0.72 -1 -1 37532 -1 -1 114 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76316 22 19 2546 2395 1 1440 161 16 16 256 mult_36 auto 36.6 MiB 0.76 9425 20700 4100 14535 2065 74.5 MiB 0.49 0.01 4.32767 -1936.05 -4.32767 4.32767 0.60 0.00479328 0.00425549 0.262515 0.233316 70 17071 27 6.45408e+06 3.91181e+06 1.02522e+06 4004.78 5.44 1.50404 1.31263 28352 262101 -1 14775 14 5841 10666 895010 199961 4.39726 4.39726 -1935.26 -4.39726 0 0 1.29210e+06 5047.26 0.33 0.40 0.24 -1 -1 0.33 0.202434 0.182515 867 1399 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_21.v common 13.89 vpr 75.57 MiB 0.08 12880 -1 -1 8 0.83 -1 -1 37748 -1 -1 122 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77380 22 19 2735 2567 1 1547 169 16 16 256 mult_36 auto 37.5 MiB 0.80 10400 22118 4046 16008 2064 75.6 MiB 0.53 0.01 4.52256 -2137.28 -4.52256 4.52256 0.58 0.00516143 0.00458229 0.287244 0.254668 70 19515 48 6.45408e+06 4.01958e+06 1.02522e+06 4004.78 7.48 1.81902 1.57916 28352 262101 -1 15796 16 6443 11250 987187 224359 4.39726 4.39726 -2218.61 -4.39726 0 0 1.29210e+06 5047.26 0.31 0.44 0.24 -1 -1 0.31 0.220885 0.198288 931 1497 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_22.v common 13.34 vpr 75.62 MiB 0.30 13172 -1 -1 8 0.95 -1 -1 38144 -1 -1 126 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77440 22 19 2793 2625 1 1580 173 16 16 256 mult_36 auto 38.0 MiB 0.83 10482 25185 5093 17461 2631 75.6 MiB 0.56 0.01 4.39726 -2104.19 -4.39726 4.39726 0.57 0.00537934 0.0047865 0.308563 0.273921 72 20575 41 6.45408e+06 4.07347e+06 1.04740e+06 4091.43 6.34 1.82921 1.59368 28608 268066 -1 16169 16 6398 11556 979161 224597 4.39726 4.39726 -2198.12 -4.39726 0 0 1.31294e+06 5128.69 0.35 0.45 0.25 -1 -1 0.35 0.226758 0.202105 962 1536 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_23.v common 16.01 vpr 76.38 MiB 0.16 13296 -1 -1 8 0.89 -1 -1 38448 -1 -1 131 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78216 22 19 2947 2762 1 1693 179 18 18 324 mult_36 auto 39.0 MiB 0.93 10552 29411 6189 20863 2359 76.4 MiB 0.70 0.01 4.33362 -2228.91 -4.33362 4.33362 0.66 0.00580614 0.00516197 0.384101 0.340643 68 20948 46 7.94662e+06 4.53683e+06 1.31159e+06 4048.11 8.55 2.05696 1.79391 35852 333792 -1 17072 17 7143 12403 1006005 225429 4.27196 4.27196 -2354.78 -4.27196 0 0 1.63345e+06 5041.52 0.41 0.48 0.29 -1 -1 0.41 0.256808 0.22909 1008 1617 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_24.v common 14.93 vpr 76.59 MiB 0.17 13576 -1 -1 8 1.00 -1 -1 38700 -1 -1 135 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78424 22 19 3005 2820 1 1720 183 18 18 324 mult_36 auto 39.2 MiB 0.91 11450 28728 5932 20637 2159 76.6 MiB 0.66 0.01 4.52256 -2356.78 -4.52256 4.52256 0.75 0.00574229 0.00510157 0.358146 0.317759 72 21726 43 7.94662e+06 4.59072e+06 1.37338e+06 4238.83 7.31 1.99763 1.74589 36820 354972 -1 17934 15 7047 12424 1077888 233656 4.52256 4.52256 -2526.88 -4.52256 0 0 1.72054e+06 5310.31 0.42 0.49 0.31 -1 -1 0.42 0.23615 0.211458 1039 1656 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_25.v common 16.53 vpr 77.66 MiB 0.18 13972 -1 -1 8 1.00 -1 -1 40404 -1 -1 145 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79524 22 19 3229 3027 1 1824 193 18 18 324 mult_36 auto 40.2 MiB 0.96 12352 31385 6347 23011 2027 77.7 MiB 0.71 0.01 4.39726 -2511.96 -4.39726 4.39726 0.75 0.0065231 0.00581076 0.383994 0.340359 70 22936 50 7.94662e+06 4.72544e+06 1.34436e+06 4149.26 8.72 2.23382 1.94605 36496 347204 -1 19370 16 7698 13674 1225432 265565 4.39726 4.39726 -2525.78 -4.39726 0 0 1.69344e+06 5226.66 0.45 0.57 0.25 -1 -1 0.45 0.288571 0.258231 1106 1771 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_26.v common 33.53 vpr 78.91 MiB 0.16 14212 -1 -1 8 1.12 -1 -1 40760 -1 -1 151 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80804 22 19 3287 3085 1 1862 199 18 18 324 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2.29136 2.00107 37144 362180 -1 20914 15 8108 14439 1272992 270691 4.39726 4.39726 -2705.27 -4.39726 0 0 1.74764e+06 5393.95 0.42 0.54 0.30 -1 -1 0.42 0.270946 0.242901 1189 1903 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_28.v common 16.27 vpr 80.38 MiB 0.19 14924 -1 -1 8 1.34 -1 -1 41120 -1 -1 160 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82308 22 19 3511 3292 1 2001 209 18 18 324 mult_36 auto 42.2 MiB 1.16 13533 36169 7851 25670 2648 80.4 MiB 0.81 0.01 4.27196 -2716.32 -4.27196 4.27196 0.77 0.00311184 0.00273883 0.42534 0.377914 76 24958 37 7.94662e+06 5.32352e+06 1.43297e+06 4422.75 7.46 2.14707 1.86573 37464 369264 -1 20464 15 8254 14560 1239406 267344 4.27196 4.27196 -2808.92 -4.27196 0 0 1.77541e+06 5479.65 0.44 0.56 0.31 -1 -1 0.44 0.280802 0.252252 1221 1942 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_29.v common 18.06 vpr 81.39 MiB 0.22 15232 -1 -1 8 1.30 -1 -1 39884 -1 -1 168 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83348 22 19 3709 3473 1 2127 218 22 22 484 mult_36 auto 43.1 MiB 1.13 14602 39518 9141 27857 2520 81.4 MiB 0.88 0.01 4.64786 -2935.24 -4.64786 4.64786 1.18 0.00704858 0.00623722 0.475426 0.419795 72 26438 32 1.29336e+07 5.8273e+06 2.11301e+06 4365.72 7.81 2.31239 2.02149 55718 550791 -1 22616 14 8048 14017 1235710 262139 4.64786 4.64786 -3093.81 -4.64786 0 0 2.64603e+06 5467.00 0.71 0.56 0.43 -1 -1 0.71 0.282288 0.253979 1281 2049 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_30.v common 19.14 vpr 81.88 MiB 0.15 15520 -1 -1 8 1.29 -1 -1 40308 -1 -1 170 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83848 22 19 3767 3531 1 2168 220 22 22 484 mult_36 auto 43.8 MiB 1.21 14136 38674 7872 27997 2805 81.9 MiB 0.88 0.01 4.27196 -2917.4 -4.27196 4.27196 1.12 0.00731678 0.00647748 0.47014 0.414099 70 26124 28 1.29336e+07 5.85424e+06 2.06816e+06 4273.05 8.74 2.28486 1.99526 55234 538945 -1 23007 16 8701 15898 1397998 301821 4.52256 4.52256 -3212.81 -4.52256 0 0 2.60483e+06 5381.88 0.72 0.59 0.43 -1 -1 0.72 0.284851 0.256579 1309 2088 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_31.v common 22.22 vpr 82.26 MiB 0.23 15852 -1 -1 8 1.37 -1 -1 41832 -1 -1 177 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84232 22 19 3928 3675 1 2252 227 22 22 484 mult_36 auto 44.1 MiB 1.26 15955 41055 8830 29506 2719 82.3 MiB 0.91 0.01 4.64786 -3128.05 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87116 22 19 4387 4117 1 2459 249 22 22 484 mult_36 auto 47.0 MiB 1.40 17068 44097 9577 31491 3029 85.1 MiB 1.06 0.02 4.39726 -3405.93 -4.39726 4.39726 1.28 0.00891162 0.00796796 0.552844 0.487065 72 32512 35 1.29336e+07 6.62746e+06 2.11301e+06 4365.72 9.24 2.76456 2.41224 55718 550791 -1 26613 16 9838 17813 1459212 312343 4.39726 4.39726 -3610.82 -4.39726 0 0 2.64603e+06 5467.00 0.72 0.69 0.44 -1 -1 0.72 0.357191 0.320219 1521 2433 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_pipe_35.v common 25.69 vpr 85.73 MiB 0.22 17368 -1 -1 8 1.74 -1 -1 41464 -1 -1 208 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71656 22 19 1596 1445 1 1103 127 16 16 256 mult_36 auto 32.0 MiB 0.46 7348 16715 3403 11508 1804 70.0 MiB 0.39 0.01 14.8867 -546.505 -14.8867 14.8867 0.61 0.00383748 0.00350071 0.219016 0.199495 74 14383 47 6.45408e+06 3.45376e+06 1.07073e+06 4182.55 5.89 1.36261 1.21569 28864 273460 -1 12301 23 6003 11963 1225113 345124 13.7425 13.7425 -634.512 -13.7425 0 0 1.33358e+06 5209.30 0.32 0.48 0.25 -1 -1 0.32 0.195495 0.174987 615 1013 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_nopipe_20.v common 11.43 vpr 70.18 MiB 0.12 10476 -1 -1 11 0.71 -1 -1 37016 -1 -1 86 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71864 22 19 1656 1505 1 1131 133 16 16 256 mult_36 auto 32.3 MiB 0.50 7846 15049 2924 10833 1292 70.2 MiB 0.36 0.01 15.2396 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32313 17 14152 27191 2278999 483397 15.8336 15.8336 -1741.68 -15.8336 0 0 3.48632e+06 6052.64 0.95 0.91 0.59 -1 -1 0.95 0.399336 0.360201 1622 2741 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_nopipe_50.v common 36.12 vpr 86.42 MiB 0.20 17156 -1 -1 13 2.58 -1 -1 39324 -1 -1 212 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88496 22 19 4190 3784 1 2864 267 24 24 576 mult_36 auto 48.0 MiB 1.19 20719 47512 9780 35035 2697 84.8 MiB 1.16 0.02 16.5956 -1264.91 -16.5956 16.5956 1.47 0.0091073 0.00821237 0.577449 0.516343 80 37198 33 1.56141e+07 8.40006e+06 2.72095e+06 4723.87 22.19 4.055 3.58594 68798 719145 -1 32760 21 15413 30452 2837390 559448 15.403 15.403 -1780.07 -15.403 0 0 3.41546e+06 5929.62 0.95 1.10 0.58 -1 -1 0.95 0.474642 0.42666 1618 2748 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_nopipe_51.v common 30.24 vpr 89.34 MiB 0.32 17612 -1 -1 13 2.71 -1 -1 43504 -1 -1 216 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91480 22 19 4305 3882 1 2950 271 24 24 576 mult_36 auto 49.1 MiB 0.93 21440 51079 10257 37415 3407 86.6 MiB 1.27 0.02 16.714 -1309.99 -16.714 16.714 1.64 0.0119022 0.0109917 0.641407 0.572951 84 38763 39 1.56141e+07 8.45395e+06 2.84938e+06 4946.85 15.79 4.22066 3.74218 70522 759407 -1 32428 20 15429 30918 2308593 493125 15.4073 15.4073 -1971.83 -15.4073 0 0 3.60864e+06 6265.01 0.98 1.05 0.61 -1 -1 0.98 0.497871 0.448507 1666 2826 -1 -1 -1 -1 -k6_frac_N8_22nm.xml fir_nopipe_52.v common 152.77 vpr 89.94 MiB 0.33 17640 -1 -1 13 2.82 -1 -1 39776 -1 -1 227 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92096 22 19 4363 3940 1 3005 282 24 24 576 mult_36 auto 49.3 MiB 1.21 21730 54798 11168 40568 3062 87.0 MiB 1.32 0.02 17.192 -1314.04 -17.192 17.192 1.52 0.0101418 0.00918253 0.66549 0.59325 76 43596 50 1.56141e+07 8.60214e+06 2.61600e+06 4541.67 137.76 7.36468 6.43712 67070 679911 -1 35261 20 17755 34183 2873298 612759 15.6501 15.6501 -1976.75 -15.6501 0 0 3.24203e+06 5628.53 0.91 1.24 0.60 -1 -1 0.91 0.56194 0.502549 1697 2865 -1 -1 -1 -1 -k6_frac_ripple_N8_22nm.xml fir_pipe_14.v common 7.16 vpr 70.80 MiB 0.07 10496 -1 -1 1 0.24 -1 -1 35480 -1 -1 81 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72496 22 19 1974 1653 1 1020 126 16 16 256 mult_36 auto 32.8 MiB 0.41 5707 14616 2612 9996 2008 70.8 MiB 0.35 0.01 4.27196 -1191.29 -4.27196 4.27196 0.57 0.00340592 0.00306896 0.179803 0.162328 60 9610 24 6.52434e+06 2.71588e+06 890343. 3477.90 2.78 0.899076 0.784711 27128 224764 -1 8185 17 3699 4190 423433 108714 4.39726 4.39726 -1140.75 -4.39726 0 0 1.11577e+06 4358.47 0.29 0.23 0.19 -1 -1 0.29 0.130495 0.117487 605 708 247 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_15.v common 20.60 vpr 71.64 MiB 0.08 10912 -1 -1 1 0.25 -1 -1 36976 -1 -1 88 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73356 22 19 2144 1789 1 1119 134 16 16 256 mult_36 auto 33.5 MiB 0.42 6078 18944 3753 12931 2260 71.6 MiB 0.44 0.01 4.22492 -1354.66 -4.22492 4.22492 0.67 0.0037036 0.00333617 0.21501 0.193696 52 14873 50 6.52434e+06 3.20969e+06 808720. 3159.06 15.69 1.74398 1.5257 25852 197779 -1 10045 20 4558 5394 572033 144141 4.52256 4.52256 -1396.34 -4.52256 0 0 1.00038e+06 3907.74 0.24 0.29 0.17 -1 -1 0.24 0.162087 0.143071 654 769 266 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_16.v common 8.25 vpr 71.93 MiB 0.11 10952 -1 -1 1 0.26 -1 -1 36912 -1 -1 91 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73652 22 19 2218 1846 1 1161 137 16 16 256 mult_36 auto 33.8 MiB 0.46 6793 19199 3651 12642 2906 71.9 MiB 0.46 0.01 4.29396 -1376.37 -4.29396 4.29396 0.55 0.00392286 0.00353131 0.222154 0.199557 56 12610 23 6.52434e+06 3.25161e+06 849745. 3319.32 3.35 1.08385 0.946389 26364 208198 -1 10765 21 4657 5400 648059 162428 4.52256 4.52256 -1436.25 -4.52256 0 0 1.04740e+06 4091.43 0.27 0.35 0.21 -1 -1 0.27 0.193181 0.170747 683 788 285 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_17.v common 9.50 vpr 73.33 MiB 0.13 11704 -1 -1 1 0.27 -1 -1 36580 -1 -1 103 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75088 22 19 2536 2130 1 1274 149 16 16 256 mult_36 auto 35.3 MiB 0.52 7563 19849 3721 13396 2732 73.3 MiB 0.51 0.01 4.29396 -1555.03 -4.29396 4.29396 0.60 0.00452081 0.00408155 0.252577 0.22717 54 14934 45 6.52434e+06 3.4193e+06 829453. 3240.05 4.40 1.45664 1.27771 26108 202796 -1 11220 19 5009 5929 575456 150599 4.29396 4.29396 -1585.29 -4.29396 0 0 1.02522e+06 4004.78 0.25 0.34 0.17 -1 -1 0.25 0.199787 0.177848 770 924 304 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_18.v common 10.95 vpr 74.29 MiB 0.12 11884 -1 -1 1 0.31 -1 -1 37120 -1 -1 107 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76068 22 19 2610 2187 1 1316 153 16 16 256 mult_36 auto 35.8 MiB 0.55 7580 22648 4139 15538 2971 74.3 MiB 0.55 0.01 4.22437 -1603.12 -4.22437 4.22437 0.58 0.00443525 0.00398183 0.273319 0.245768 56 14991 32 6.52434e+06 3.47519e+06 849745. 3319.32 5.86 1.41031 1.23076 26364 208198 -1 12118 24 5442 6385 763550 186400 5.14906 5.14906 -1681.4 -5.14906 0 0 1.04740e+06 4091.43 0.27 0.41 0.13 -1 -1 0.27 0.230417 0.203033 798 943 323 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_19.v common 10.76 vpr 75.11 MiB 0.17 12184 -1 -1 1 0.33 -1 -1 36724 -1 -1 113 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76916 22 19 2778 2321 1 1410 160 16 16 256 mult_36 auto 36.8 MiB 0.57 8169 22294 4065 14927 3302 75.1 MiB 0.53 0.01 4.2304 -1681.23 -4.2304 4.2304 0.58 0.0045314 0.00405318 0.256982 0.22945 58 14770 47 6.52434e+06 3.95503e+06 871168. 3403.00 5.40 1.56264 1.36024 26872 219187 -1 12035 18 5167 5841 646056 165802 4.29396 4.29396 -1705.82 -4.29396 0 0 1.09288e+06 4269.05 0.26 0.34 0.19 -1 -1 0.26 0.194726 0.171914 846 1002 342 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_20.v common 9.91 vpr 75.12 MiB 0.13 12376 -1 -1 1 0.35 -1 -1 37004 -1 -1 118 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76928 22 19 2852 2378 1 1454 165 16 16 256 mult_36 auto 37.3 MiB 0.56 8808 21861 3843 15034 2984 75.1 MiB 0.55 0.01 4.28986 -1739.48 -4.28986 4.28986 0.61 0.00497001 0.00446513 0.264268 0.23753 60 14824 27 6.52434e+06 4.0249e+06 890343. 3477.90 4.57 1.45122 1.26718 27128 224764 -1 12480 16 5276 6100 595745 151457 4.41926 4.41926 -1762.84 -4.41926 0 0 1.11577e+06 4358.47 0.28 0.34 0.20 -1 -1 0.28 0.194343 0.172377 875 1021 361 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_21.v common 11.49 vpr 76.05 MiB 0.15 12808 -1 -1 1 0.34 -1 -1 37824 -1 -1 122 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77880 22 19 3057 2549 1 1559 169 16 16 256 mult_36 auto 38.3 MiB 0.64 9015 24920 4571 15619 4730 76.1 MiB 0.64 0.01 4.20237 -1905.04 -4.20237 4.20237 0.58 0.00554434 0.00500669 0.309355 0.276796 60 16024 44 6.52434e+06 4.0808e+06 890343. 3477.90 5.69 1.73434 1.51865 27128 224764 -1 13134 16 5600 6594 636756 160290 4.29396 4.29396 -1928.97 -4.29396 0 0 1.11577e+06 4358.47 0.28 0.36 0.19 -1 -1 0.28 0.207694 0.184735 932 1099 380 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_22.v common 12.10 vpr 76.48 MiB 0.10 12960 -1 -1 1 0.35 -1 -1 37920 -1 -1 125 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78316 22 19 3131 2606 1 1599 172 16 16 256 mult_36 auto 38.8 MiB 0.53 9644 27896 4964 18195 4737 76.5 MiB 0.74 0.01 4.09962 -1964.96 -4.09962 4.09962 0.57 0.00549947 0.00489115 0.342589 0.303885 66 17711 35 6.52434e+06 4.12272e+06 974584. 3806.97 6.45 1.71183 1.49596 28148 247068 -1 13707 17 5831 6659 781116 185151 4.29396 4.29396 -1959.31 -4.29396 0 0 1.22072e+06 4768.46 0.31 0.39 0.19 -1 -1 0.31 0.215751 0.191625 961 1118 399 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_23.v common 13.73 vpr 77.29 MiB 0.17 13308 -1 -1 1 0.39 -1 -1 37936 -1 -1 133 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79140 22 19 3301 2742 1 1700 181 18 18 324 mult_36 auto 39.5 MiB 0.72 10087 30330 5799 21301 3230 77.3 MiB 0.74 0.01 4.29396 -2075.2 -4.29396 4.29396 0.77 0.00650178 0.00598133 0.346423 0.313697 60 18320 28 8.04299e+06 4.63052e+06 1.16833e+06 3605.96 7.06 1.72603 1.51148 35004 297736 -1 15010 17 6849 7695 873963 206522 4.29396 4.29396 -2095.97 -4.29396 0 0 1.46313e+06 4515.82 0.40 0.41 0.25 -1 -1 0.40 0.220321 0.195312 1012 1179 418 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_24.v common 13.85 vpr 77.54 MiB 0.13 13392 -1 -1 1 0.41 -1 -1 38108 -1 -1 137 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79396 22 19 3375 2799 1 1743 185 18 18 324 mult_36 auto 39.8 MiB 0.70 10300 29115 5219 20674 3222 77.5 MiB 0.80 0.01 4.22437 -2073.88 -4.22437 4.22437 0.77 0.006131 0.00553331 0.354774 0.317073 58 18565 31 8.04299e+06 4.68641e+06 1.14310e+06 3528.09 7.15 1.79694 1.56807 34680 290288 -1 15595 17 6816 7782 901255 220455 4.29396 4.29396 -2160.36 -4.29396 0 0 1.43297e+06 4422.75 0.36 0.44 0.26 -1 -1 0.36 0.237466 0.211355 1041 1198 437 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_25.v common 13.85 vpr 78.52 MiB 0.13 13888 -1 -1 1 0.40 -1 -1 38236 -1 -1 146 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80404 22 19 3615 3005 1 1847 194 18 18 324 mult_36 auto 40.8 MiB 0.67 10975 29927 5204 21640 3083 78.5 MiB 0.78 0.01 4.29396 -2273.15 -4.29396 4.29396 0.76 0.006101 0.00546094 0.361338 0.323248 58 20078 36 8.04299e+06 4.81218e+06 1.14310e+06 3528.09 7.25 1.94915 1.69787 34680 290288 -1 16168 17 7089 8219 904291 224983 4.41926 4.41926 -2410.63 -4.41926 0 0 1.43297e+06 4422.75 0.36 0.46 0.24 -1 -1 0.36 0.258436 0.230808 1107 1293 456 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_26.v common 14.51 vpr 79.02 MiB 0.09 14076 -1 -1 1 0.34 -1 -1 38412 -1 -1 148 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80916 22 19 3689 3062 1 1888 196 18 18 324 mult_36 auto 41.4 MiB 0.77 10816 33767 6403 23789 3575 79.0 MiB 0.90 0.01 4.09962 -2289.16 -4.09962 4.09962 0.77 0.00666653 0.00592456 0.405095 0.359897 60 19765 47 8.04299e+06 4.84013e+06 1.16833e+06 3605.96 7.57 2.1649 1.88473 35004 297736 -1 15783 16 6853 7919 833754 202360 4.41926 4.41926 -2402.93 -4.41926 0 0 1.46313e+06 4515.82 0.37 0.43 0.25 -1 -1 0.37 0.24325 0.216254 1135 1312 475 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_27.v common 12.41 vpr 80.23 MiB 0.18 14388 -1 -1 1 0.41 -1 -1 38456 -1 -1 156 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82160 22 19 3871 3210 1 1998 205 18 18 324 mult_36 auto 42.4 MiB 0.80 12132 28593 4296 20787 3510 80.2 MiB 0.74 0.01 4.41926 -2393.12 -4.41926 4.41926 0.77 0.006481 0.00579771 0.338432 0.302298 64 20586 19 8.04299e+06 5.34793e+06 1.23838e+06 3822.15 5.24 1.78906 1.56837 35972 318676 -1 17280 19 7116 8295 869286 210992 4.41926 4.41926 -2474.76 -4.41926 0 0 1.56068e+06 4816.91 0.44 0.51 0.30 -1 -1 0.44 0.295813 0.263743 1191 1385 494 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_28.v common 15.94 vpr 80.36 MiB 0.28 14584 -1 -1 1 0.47 -1 -1 38476 -1 -1 160 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82292 22 19 3945 3267 1 2043 209 18 18 324 mult_36 auto 42.6 MiB 0.83 12721 34929 5952 24376 4601 80.4 MiB 0.89 0.01 4.26697 -2429.16 -4.26697 4.26697 0.78 0.00701006 0.00631112 0.406399 0.363637 60 21797 48 8.04299e+06 5.40382e+06 1.16833e+06 3605.96 8.27 2.30836 2.01074 35004 297736 -1 18182 20 8118 9346 1020381 253908 4.41926 4.41926 -2516.38 -4.41926 0 0 1.46313e+06 4515.82 0.38 0.63 0.27 -1 -1 0.38 0.375108 0.337767 1219 1404 513 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_29.v common 17.64 vpr 81.52 MiB 0.12 15092 -1 -1 1 0.48 -1 -1 39648 -1 -1 170 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83480 22 19 4159 3447 1 2157 220 22 22 484 mult_36 auto 43.7 MiB 0.84 13597 41989 8196 30469 3324 81.5 MiB 1.05 0.02 4.16866 -2687.48 -4.16866 4.16866 1.22 0.00719836 0.00646222 0.481623 0.429453 56 27289 30 1.30842e+07 5.93957e+06 1.71605e+06 3545.56 8.95 2.22671 1.94498 51606 428054 -1 21919 20 9434 11001 1516906 343088 4.52256 4.52256 -2855.36 -4.52256 0 0 2.11301e+06 4365.72 0.56 0.39 0.34 -1 -1 0.56 0.187846 0.168815 1283 1491 532 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_30.v common 20.20 vpr 82.89 MiB 0.20 15032 -1 -1 1 0.60 -1 -1 40776 -1 -1 173 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84880 22 19 4233 3504 1 2198 223 22 22 484 mult_36 auto 44.3 MiB 0.85 14316 43487 8493 30718 4276 82.9 MiB 1.12 0.02 4.41926 -2750.54 -4.41926 4.41926 1.22 0.00742763 0.00666077 0.497987 0.444103 58 27441 46 1.30842e+07 5.98149e+06 1.75961e+06 3635.55 10.85 2.43679 2.13088 52570 450426 -1 21701 17 9112 10561 1278143 292476 4.54456 4.54456 -2870.39 -4.54456 0 0 2.20457e+06 4554.90 0.61 0.57 0.36 -1 -1 0.61 0.303403 0.26981 1311 1510 551 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_31.v common 16.67 vpr 83.57 MiB 0.23 15640 -1 -1 1 0.53 -1 -1 41024 -1 -1 179 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85576 22 19 4410 3647 1 2304 229 22 22 484 mult_36 auto 44.9 MiB 0.88 14559 42929 8301 31079 3549 83.6 MiB 1.12 0.02 4.54456 -2849.05 -4.54456 4.54456 1.21 0.00745103 0.00666239 0.502234 0.448841 60 26138 29 1.30842e+07 6.06533e+06 1.79840e+06 3715.71 7.35 2.34135 2.05057 53054 462096 -1 21367 18 8865 10303 1128192 264808 4.54456 4.54456 -2991.12 -4.54456 0 0 2.25108e+06 4650.99 0.62 0.59 0.39 -1 -1 0.62 0.318889 0.285441 1363 1578 570 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_32.v common 20.69 vpr 82.85 MiB 0.19 15572 -1 -1 1 0.54 -1 -1 40572 -1 -1 183 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84836 22 19 4484 3704 1 2346 233 22 22 484 mult_36 auto 45.1 MiB 0.91 14169 51069 10204 36498 4367 82.8 MiB 1.24 0.02 4.35562 -2870.14 -4.35562 4.35562 1.18 0.00727166 0.00648461 0.540705 0.481056 58 28562 42 1.30842e+07 6.12123e+06 1.75961e+06 3635.55 10.86 2.61612 2.28074 52570 450426 -1 21935 18 9198 10981 1225293 282955 4.41926 4.41926 -3046.59 -4.41926 0 0 2.20457e+06 4554.90 0.62 0.59 0.32 -1 -1 0.62 0.310706 0.275736 1393 1597 589 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_33.v common 24.20 vpr 85.52 MiB 0.23 16688 -1 -1 1 0.56 -1 -1 41628 -1 -1 196 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87572 22 19 4843 4029 1 2462 247 22 22 484 mult_36 auto 47.0 MiB 1.13 15624 49783 9117 36437 4229 85.5 MiB 1.21 0.02 4.64786 -3017.99 -4.64786 4.64786 1.24 0.00761602 0.00676614 0.533935 0.474376 60 29459 48 1.30842e+07 6.6989e+06 1.79840e+06 3715.71 14.26 2.84822 2.48391 53054 462096 -1 23118 17 9322 10866 1279018 283870 4.54456 4.54456 -3177.97 -4.54456 0 0 2.25108e+06 4650.99 0.61 0.62 0.46 -1 -1 0.61 0.353908 0.31735 1490 1756 608 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_34.v common 20.31 vpr 84.88 MiB 0.26 16896 -1 -1 1 0.63 -1 -1 41516 -1 -1 199 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86916 22 19 4917 4086 1 2503 250 22 22 484 mult_36 auto 47.4 MiB 0.95 16182 52192 10276 36322 5594 84.9 MiB 1.28 0.02 4.41926 -3092.45 -4.41926 4.41926 1.23 0.00760482 0.00676556 0.564061 0.500769 64 28538 36 1.30842e+07 6.74082e+06 1.90554e+06 3937.06 10.13 3.04467 2.68442 54502 494576 -1 22667 18 8811 10602 1146289 263961 4.54456 4.54456 -3188.99 -4.54456 0 0 2.40101e+06 4960.76 0.65 0.62 0.41 -1 -1 0.65 0.351193 0.312295 1519 1775 627 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_35.v common 21.36 vpr 85.83 MiB 0.32 17128 -1 -1 1 0.63 -1 -1 41764 -1 -1 207 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87888 22 19 5093 4228 1 2606 258 22 22 484 mult_36 auto 48.2 MiB 0.95 15281 55265 10444 39810 5011 85.8 MiB 1.34 0.02 4.16866 -3231.81 -4.16866 4.16866 1.23 0.00806113 0.00717252 0.590696 0.524331 60 28985 37 1.30842e+07 6.85261e+06 1.79840e+06 3715.71 11.05 2.9251 2.55373 53054 462096 -1 22720 20 9865 11925 1244020 294578 4.41926 4.41926 -3325.32 -4.41926 0 0 2.25108e+06 4650.99 0.64 0.69 0.37 -1 -1 0.64 0.399047 0.354548 1572 1842 646 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_36.v common 18.14 vpr 86.34 MiB 0.17 17204 -1 -1 1 0.65 -1 -1 41776 -1 -1 209 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88416 22 19 5167 4285 1 2653 260 22 22 484 mult_36 auto 48.8 MiB 0.98 16606 54145 10648 38527 4970 86.3 MiB 1.36 0.02 4.16866 -3259.63 -4.16866 4.16866 1.19 0.00868234 0.00775776 0.586893 0.521739 64 29957 28 1.30842e+07 6.88056e+06 1.90554e+06 3937.06 8.19 2.67123 2.33119 54502 494576 -1 23683 18 9902 11325 1259385 289004 4.41926 4.41926 -3287.54 -4.41926 0 0 2.40101e+06 4960.76 0.61 0.58 0.39 -1 -1 0.61 0.331583 0.292623 1600 1861 665 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_37.v common 21.09 vpr 88.22 MiB 0.26 17588 -1 -1 1 0.67 -1 -1 40772 -1 -1 218 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90340 22 19 5380 4464 1 2755 270 24 24 576 mult_36 auto 49.9 MiB 1.06 18567 56078 10962 40406 4710 88.2 MiB 1.45 0.02 4.41926 -3517.74 -4.41926 4.41926 1.46 0.011845 0.0108667 0.625669 0.556627 62 34089 42 1.57908e+07 7.40233e+06 2.19658e+06 3813.51 10.12 3.24992 2.85968 63306 560109 -1 25982 17 10013 11925 1290386 299725 4.54456 4.54456 -3709.06 -4.54456 0 0 2.72095e+06 4723.87 0.70 0.60 0.43 -1 -1 0.70 0.335585 0.296844 1662 1947 684 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_38.v common 23.46 vpr 87.28 MiB 0.18 17932 -1 -1 1 0.70 -1 -1 42356 -1 -1 220 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89372 22 19 5454 4521 1 2802 272 24 24 576 mult_36 auto 49.6 MiB 1.08 18582 51370 9929 37950 3491 87.3 MiB 1.41 0.02 4.41926 -3447.93 -4.41926 4.41926 1.47 0.00885871 0.00790343 0.606093 0.53869 64 34209 36 1.57908e+07 7.43028e+06 2.26035e+06 3924.22 12.06 2.88108 2.51729 64454 586630 -1 26870 18 10485 12283 1454697 328137 4.54456 4.54456 -3636.25 -4.54456 0 0 2.84938e+06 4946.85 0.81 0.72 0.48 -1 -1 0.81 0.391969 0.349886 1690 1966 703 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_39.v common 23.62 vpr 88.21 MiB 0.29 18256 -1 -1 1 0.71 -1 -1 40212 -1 -1 228 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90324 22 19 5629 4662 1 2909 280 24 24 576 mult_36 auto 50.9 MiB 1.08 18512 58840 11287 42675 4878 88.2 MiB 1.50 0.02 4.53661 -3591.01 -4.53661 4.53661 1.51 0.0104965 0.0094672 0.651336 0.579977 64 33376 33 1.57908e+07 7.54207e+06 2.26035e+06 3924.22 11.88 3.18095 2.78182 64454 586630 -1 26570 18 10607 12773 1398491 323531 4.52256 4.52256 -3729.32 -4.52256 0 0 2.84938e+06 4946.85 0.82 0.72 0.47 -1 -1 0.82 0.405198 0.361638 1742 2032 722 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_40.v common 24.07 vpr 89.79 MiB 0.34 18348 -1 -1 1 0.68 -1 -1 42284 -1 -1 232 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91944 22 19 5703 4719 1 2951 284 24 24 576 mult_36 auto 51.8 MiB 1.09 19527 61862 12354 44168 5340 89.8 MiB 1.55 0.02 4.51758 -3660.42 -4.51758 4.51758 1.41 0.00911902 0.00811392 0.654527 0.579497 64 35385 33 1.57908e+07 7.59797e+06 2.26035e+06 3924.22 11.97 3.12936 2.74636 64454 586630 -1 27678 18 10750 12796 1471921 331561 4.64786 4.64786 -3839.37 -4.64786 0 0 2.84938e+06 4946.85 0.83 0.79 0.55 -1 -1 0.83 0.438235 0.393209 1771 2051 741 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_41.v common 24.48 vpr 89.66 MiB 0.21 18724 -1 -1 1 0.84 -1 -1 41504 -1 -1 240 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91816 22 19 5950 4932 1 3065 293 24 24 576 mult_36 auto 52.4 MiB 1.12 20313 68333 13912 49003 5418 89.7 MiB 1.76 0.02 4.35562 -3781.12 -4.35562 4.35562 1.49 0.0100927 0.00897853 0.748474 0.663187 64 37437 47 1.57908e+07 8.10576e+06 2.26035e+06 3924.22 12.19 3.44676 2.99524 64454 586630 -1 29393 20 11515 13868 1578948 357275 4.54456 4.54456 -4027.56 -4.54456 0 0 2.84938e+06 4946.85 0.77 0.81 0.47 -1 -1 0.77 0.448202 0.39727 1841 2153 760 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_42.v common 25.47 vpr 92.35 MiB 0.23 18988 -1 -1 1 0.86 -1 -1 42916 -1 -1 242 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94564 22 19 6024 4989 1 3106 295 24 24 576 mult_36 auto 53.2 MiB 1.15 21018 65041 12819 46780 5442 90.3 MiB 1.67 0.02 4.54456 -3823.47 -4.54456 4.54456 1.51 0.0101508 0.00906076 0.715915 0.636736 64 36534 49 1.57908e+07 8.13371e+06 2.26035e+06 3924.22 13.19 3.56747 3.11957 64454 586630 -1 29646 18 11267 13244 1541469 352337 4.66986 4.66986 -3955.02 -4.66986 0 0 2.84938e+06 4946.85 0.75 0.75 0.46 -1 -1 0.75 0.430993 0.383901 1869 2172 779 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_43.v common 25.12 vpr 91.39 MiB 0.31 19256 -1 -1 1 0.89 -1 -1 43264 -1 -1 250 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93588 22 19 6198 5129 1 3209 303 24 24 576 mult_36 auto 54.3 MiB 1.22 22338 66408 13114 47625 5669 91.4 MiB 1.76 0.03 4.47497 -4072.8 -4.47497 4.47497 1.50 0.0104487 0.00936437 0.738522 0.655007 68 37694 34 1.57908e+07 8.2455e+06 2.39371e+06 4155.74 12.43 3.35506 2.92455 65606 615345 -1 30383 15 11489 13385 1484469 334786 4.66986 4.66986 -4189.73 -4.66986 0 0 2.98162e+06 5176.42 1.02 0.78 0.49 -1 -1 1.02 0.421175 0.378984 1921 2237 798 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_44.v common 25.17 vpr 94.43 MiB 0.17 19552 -1 -1 1 0.85 -1 -1 43196 -1 -1 253 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96696 22 19 6272 5186 1 3253 306 24 24 576 mult_36 auto 54.2 MiB 1.23 22629 67256 12828 47647 6781 91.3 MiB 1.75 0.03 4.41926 -4066.4 -4.41926 4.41926 1.56 0.0105256 0.0093916 0.741281 0.658657 70 37350 43 1.57908e+07 8.28742e+06 2.45377e+06 4260.01 12.42 3.6164 3.15387 66754 640332 -1 30782 20 11655 13506 1570135 362351 4.41926 4.41926 -4119.98 -4.41926 0 0 3.09179e+06 5367.68 0.82 0.82 0.51 -1 -1 0.82 0.468682 0.416096 1949 2256 817 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_45.v common 23.85 vpr 92.27 MiB 0.33 20028 -1 -1 1 0.90 -1 -1 43716 -1 -1 262 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 94488 22 19 6485 5365 1 3362 316 24 24 576 mult_36 auto 55.3 MiB 1.26 21577 68041 12652 49574 5815 92.3 MiB 1.82 0.03 4.34967 -4219.28 -4.34967 4.34967 1.55 0.010752 0.00961779 0.738639 0.650742 72 36507 46 1.57908e+07 8.80919e+06 2.50747e+06 4353.24 10.81 3.77641 3.29091 67330 654343 -1 29810 22 11462 13137 1601544 361852 4.39726 4.39726 -4238.31 -4.39726 0 0 3.14081e+06 5452.80 0.85 0.91 0.52 -1 -1 0.85 0.527897 0.467341 2011 2342 836 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_46.v common 26.61 vpr 98.11 MiB 0.34 20028 -1 -1 1 0.87 -1 -1 43880 -1 -1 266 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100468 22 19 6559 5422 1 3404 320 24 24 576 mult_36 auto 55.5 MiB 1.28 24101 72524 13138 53102 6284 92.7 MiB 2.08 0.03 4.66986 -4291.45 -4.66986 4.66986 1.46 0.0119672 0.0107794 0.83727 0.749668 68 40255 40 1.57908e+07 8.86508e+06 2.39371e+06 4155.74 13.34 3.88625 3.40879 65606 615345 -1 32521 18 12015 14089 1546690 340905 4.66986 4.66986 -4364.43 -4.66986 0 0 2.98162e+06 5176.42 0.79 0.84 0.52 -1 -1 0.79 0.471209 0.420824 2040 2361 855 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_47.v common 25.66 vpr 96.38 MiB 0.26 20328 -1 -1 1 0.98 -1 -1 44612 -1 -1 273 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98692 22 19 6735 5564 1 3511 327 24 24 576 mult_36 auto 56.6 MiB 1.32 22785 72391 13683 52096 6612 93.7 MiB 2.12 0.03 4.36967 -4379.74 -4.36967 4.36967 1.44 0.0126992 0.011479 0.885818 0.786761 66 39572 35 1.57908e+07 8.9629e+06 2.33135e+06 4047.49 12.30 3.95827 3.45851 65030 601923 -1 31611 19 12384 14268 1564989 359786 4.54456 4.54456 -4464.94 -4.54456 0 0 2.91907e+06 5067.82 0.82 0.86 0.50 -1 -1 0.82 0.496205 0.441897 2092 2428 874 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_48.v common 27.56 vpr 98.24 MiB 0.39 20536 -1 -1 1 1.04 -1 -1 44100 -1 -1 276 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100596 22 19 6809 5621 1 3555 330 24 24 576 mult_36 auto 57.0 MiB 1.36 23066 80060 16107 55507 8446 94.0 MiB 2.24 0.03 4.29396 -4332.56 -4.29396 4.29396 1.49 0.010321 0.00913554 0.900016 0.796321 70 39582 34 1.57908e+07 9.00482e+06 2.45377e+06 4260.01 13.48 3.67756 3.19309 66754 640332 -1 32506 18 12951 15266 1774464 412111 4.41926 4.41926 -4460.37 -4.41926 0 0 3.09179e+06 5367.68 0.84 0.87 0.54 -1 -1 0.84 0.478592 0.424893 2121 2447 893 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_49.v common 27.16 vpr 97.51 MiB 0.18 21252 -1 -1 1 1.04 -1 -1 44416 -1 -1 287 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99852 22 19 7094 5872 1 3669 342 24 24 576 mult_36 auto 58.0 MiB 1.42 24245 82797 16885 57326 8586 95.1 MiB 2.25 0.03 4.52256 -4714.45 -4.52256 4.52256 1.44 0.0118561 0.0106259 0.900369 0.79678 72 41230 32 1.57908e+07 9.55454e+06 2.50747e+06 4353.24 13.37 3.97004 3.4626 67330 654343 -1 33608 16 12552 14465 1746432 385070 4.64786 4.64786 -4951.91 -4.64786 0 0 3.14081e+06 5452.80 0.85 0.85 0.53 -1 -1 0.85 0.455975 0.406164 2200 2569 912 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_50.v common 26.03 vpr 100.95 MiB 0.21 21304 -1 -1 1 1.04 -1 -1 44288 -1 -1 290 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 103372 22 19 7168 5929 1 3710 345 24 24 576 mult_36 auto 58.4 MiB 1.47 24589 80139 15697 56982 7460 95.4 MiB 2.13 0.03 4.41926 -4634.65 -4.41926 4.41926 1.48 0.0119433 0.010454 0.836358 0.737133 70 40446 44 1.57908e+07 9.59646e+06 2.45377e+06 4260.01 12.09 4.00842 3.47817 66754 640332 -1 34146 18 13413 15667 1907396 427492 4.54456 4.54456 -4822.29 -4.54456 0 0 3.09179e+06 5367.68 0.89 1.01 0.52 -1 -1 0.89 0.535964 0.47839 2229 2588 931 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_51.v common 28.63 vpr 99.47 MiB 0.37 21664 -1 -1 1 1.11 -1 -1 44756 -1 -1 297 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101856 22 19 7344 6071 1 3814 352 24 24 576 mult_36 auto 59.4 MiB 1.64 25956 86050 17957 59580 8513 96.4 MiB 2.35 0.04 4.54456 -4790.18 -4.54456 4.54456 1.49 0.0162424 0.0148599 0.946895 0.838694 72 43615 28 1.57908e+07 9.69428e+06 2.50747e+06 4353.24 13.90 3.95891 3.45177 67330 654343 -1 35657 17 13386 15768 1879694 426603 4.64786 4.64786 -4925.15 -4.64786 0 0 3.14081e+06 5452.80 0.86 0.89 0.52 -1 -1 0.86 0.48718 0.433407 2282 2655 950 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_pipe_52.v common 25.95 vpr 99.39 MiB 0.28 21732 -1 -1 1 1.01 -1 -1 45068 -1 -1 301 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 101776 22 19 7418 6128 1 3859 356 24 24 576 mult_36 auto 60.1 MiB 1.47 27555 81060 16090 57104 7866 99.1 MiB 2.14 0.03 4.54456 -4802.82 -4.54456 4.54456 1.43 0.0120698 0.0107753 0.842413 0.740695 76 44587 45 1.57908e+07 9.75017e+06 2.61600e+06 4541.67 12.08 4.15845 3.61183 68478 680951 -1 37419 17 14263 16730 1964169 440460 4.52256 4.52256 -5062.61 -4.52256 0 0 3.24203e+06 5628.53 0.95 0.95 0.52 -1 -1 0.95 0.502544 0.447268 2310 2674 969 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_14.v common 8.81 vpr 67.31 MiB 0.13 9440 -1 -1 1 0.12 -1 -1 34712 -1 -1 58 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68924 22 19 1246 925 1 732 103 16 16 256 mult_36 auto 28.9 MiB 2.74 3886 14081 3199 8271 2611 67.3 MiB 0.31 0.01 8.43746 -386.648 -8.43746 8.43746 0.59 0.00249884 0.0022961 0.153735 0.141049 44 8107 32 6.52434e+06 2.39448e+06 686998. 2683.59 2.43 0.551985 0.492102 24576 170172 -1 6188 24 5707 6417 667481 172985 7.87084 7.87084 -462.711 -7.87084 0 0 871168. 3403.00 0.21 0.29 0.15 -1 -1 0.21 0.128358 0.11408 421 344 247 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_15.v common 9.80 vpr 67.93 MiB 0.10 9540 -1 -1 1 0.17 -1 -1 35144 -1 -1 61 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69560 22 19 1344 989 1 793 107 16 16 256 mult_36 auto 29.6 MiB 2.03 4415 16299 3732 8915 3652 67.9 MiB 0.37 0.01 8.61109 -402.505 -8.61109 8.61109 0.58 0.00265723 0.00243955 0.189356 0.173645 44 9925 41 6.52434e+06 2.8324e+06 686998. 2683.59 3.88 0.892944 0.7947 24576 170172 -1 7024 25 6220 7095 698142 184212 8.45004 8.45004 -463.679 -8.45004 0 0 871168. 3403.00 0.22 0.34 0.15 -1 -1 0.22 0.155405 0.14074 453 369 266 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_16.v common 11.29 vpr 68.10 MiB 0.10 9672 -1 -1 1 0.19 -1 -1 35136 -1 -1 65 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69736 22 19 1418 1046 1 832 111 16 16 256 mult_36 auto 30.1 MiB 2.96 4724 16869 4045 10706 2118 68.1 MiB 0.44 0.01 8.43651 -410.772 -8.43651 8.43651 0.62 0.0028132 0.00257563 0.200536 0.183658 48 9176 31 6.52434e+06 2.88829e+06 755748. 2952.14 4.31 0.897273 0.796679 25088 180500 -1 7305 24 6692 7397 851322 211567 7.80584 7.80584 -467.143 -7.80584 0 0 916467. 3579.95 0.22 0.34 0.17 -1 -1 0.22 0.143449 0.127696 481 388 285 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_17.v common 10.58 vpr 68.59 MiB 0.10 10212 -1 -1 1 0.15 -1 -1 35340 -1 -1 71 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70240 22 19 1518 1112 1 896 117 16 16 256 mult_36 auto 30.6 MiB 2.67 5238 17563 3887 11404 2272 68.6 MiB 0.46 0.01 9.04171 -433.063 -9.04171 9.04171 0.56 0.00413444 0.00385519 0.205719 0.187964 48 10177 28 6.52434e+06 2.97214e+06 755748. 2952.14 3.95 0.881042 0.782615 25088 180500 -1 8176 22 6890 7606 917926 237751 8.68028 8.68028 -493.626 -8.68028 0 0 916467. 3579.95 0.22 0.32 0.18 -1 -1 0.22 0.135487 0.121653 514 415 304 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_18.v common 13.14 vpr 68.97 MiB 0.12 10304 -1 -1 1 0.21 -1 -1 34948 -1 -1 74 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70628 22 19 1592 1169 1 934 120 16 16 256 mult_36 auto 30.9 MiB 3.32 5243 15755 3475 9888 2392 69.0 MiB 0.39 0.01 9.04775 -490.252 -9.04775 9.04775 0.55 0.00310114 0.00281456 0.183321 0.167683 48 11232 37 6.52434e+06 3.01406e+06 755748. 2952.14 5.98 0.941072 0.833617 25088 180500 -1 8633 23 7736 8750 1034775 249786 8.80158 8.80158 -540.639 -8.80158 0 0 916467. 3579.95 0.23 0.39 0.17 -1 -1 0.23 0.152496 0.136913 542 434 323 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_19.v common 11.51 vpr 69.29 MiB 0.11 10692 -1 -1 1 0.20 -1 -1 35236 -1 -1 79 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70956 22 19 1688 1231 1 994 126 16 16 256 mult_36 auto 31.4 MiB 2.90 5618 18711 3986 11280 3445 69.3 MiB 0.48 0.01 9.18492 -482.658 -9.18492 9.18492 0.58 0.00325551 0.00298378 0.223503 0.20475 52 10842 44 6.52434e+06 3.47993e+06 808720. 3159.06 4.48 1.093 0.971846 25852 197779 -1 8271 22 6752 7535 845938 215127 8.23108 8.23108 -551.85 -8.23108 0 0 1.00038e+06 3907.74 0.25 0.33 0.17 -1 -1 0.25 0.150906 0.134461 573 457 342 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_20.v common 12.15 vpr 69.87 MiB 0.12 10752 -1 -1 1 0.22 -1 -1 35508 -1 -1 81 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71544 22 19 1762 1288 1 1031 128 16 16 256 mult_36 auto 31.8 MiB 3.48 6535 19770 4199 12093 3478 69.9 MiB 0.50 0.01 9.33493 -488.07 -9.33493 9.33493 0.58 0.00393902 0.00361618 0.226774 0.206643 48 12219 33 6.52434e+06 3.50787e+06 755748. 2952.14 4.48 1.04501 0.925176 25088 180500 -1 9898 22 7504 8327 1040791 265119 8.96258 8.96258 -581.233 -8.96258 0 0 916467. 3579.95 0.23 0.39 0.16 -1 -1 0.23 0.156731 0.139761 601 476 361 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_21.v common 12.92 vpr 70.16 MiB 0.14 10972 -1 -1 1 0.23 -1 -1 35944 -1 -1 85 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71844 22 19 1859 1351 1 1093 132 16 16 256 mult_36 auto 32.1 MiB 3.48 6792 15542 2589 10760 2193 70.2 MiB 0.41 0.01 9.32007 -525.351 -9.32007 9.32007 0.61 0.00348662 0.00319064 0.180881 0.165392 52 13770 38 6.52434e+06 3.56377e+06 808720. 3159.06 5.06 1.13318 1.00524 25852 197779 -1 10144 26 8345 9522 1119762 274391 8.76698 8.76698 -629.803 -8.76698 0 0 1.00038e+06 3907.74 0.25 0.48 0.17 -1 -1 0.25 0.200326 0.179147 632 500 380 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_22.v common 12.79 vpr 70.51 MiB 0.09 11036 -1 -1 1 0.25 -1 -1 35780 -1 -1 90 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72200 22 19 1933 1408 1 1131 137 16 16 256 mult_36 auto 32.7 MiB 4.09 7153 18846 3425 12209 3212 70.5 MiB 0.49 0.01 9.31293 -505.408 -9.31293 9.31293 0.60 0.00360585 0.00328582 0.209128 0.190526 56 11937 28 6.52434e+06 3.63364e+06 849745. 3319.32 4.42 1.06006 0.938823 26364 208198 -1 10148 23 7351 8481 910874 235258 8.45968 8.45968 -707.138 -8.45968 0 0 1.04740e+06 4091.43 0.26 0.39 0.18 -1 -1 0.26 0.181491 0.161447 661 519 399 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_23.v common 16.10 vpr 71.06 MiB 0.18 11408 -1 -1 1 0.25 -1 -1 36016 -1 -1 94 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72768 22 19 2031 1472 1 1193 142 18 18 324 mult_36 auto 33.2 MiB 3.90 7470 21602 4449 14485 2668 71.1 MiB 0.53 0.01 9.36191 -552.695 -9.36191 9.36191 0.79 0.00376507 0.00343241 0.238367 0.217452 50 14673 42 8.04299e+06 4.08553e+06 1.03391e+06 3191.07 7.13 1.27319 1.12709 32744 246704 -1 11207 23 8954 10315 1227188 301096 8.80128 8.80128 -805.076 -8.80128 0 0 1.23838e+06 3822.15 0.31 0.48 0.22 -1 -1 0.31 0.19755 0.176261 693 544 418 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_24.v common 15.40 vpr 71.33 MiB 0.11 11492 -1 -1 1 0.23 -1 -1 36264 -1 -1 97 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73040 22 19 2105 1529 1 1232 145 18 18 324 mult_36 auto 33.3 MiB 4.14 7507 21425 4200 14405 2820 71.3 MiB 0.55 0.01 9.44155 -614.321 -9.44155 9.44155 0.78 0.0038934 0.00354525 0.238346 0.21681 50 14797 40 8.04299e+06 4.12745e+06 1.03391e+06 3191.07 6.30 1.24287 1.0989 32744 246704 -1 11508 23 9004 10353 1255675 301759 8.51938 8.51938 -832.526 -8.51938 0 0 1.23838e+06 3822.15 0.31 0.44 0.21 -1 -1 0.31 0.185596 0.165494 721 563 437 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_25.v common 14.99 vpr 71.78 MiB 0.08 11932 -1 -1 1 0.27 -1 -1 36564 -1 -1 101 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73500 22 19 2201 1591 1 1290 149 18 18 324 mult_36 auto 33.9 MiB 3.96 8738 27335 5810 17606 3919 71.8 MiB 0.75 0.01 9.29835 -606.15 -9.29835 9.29835 0.78 0.00474546 0.00429979 0.319794 0.290255 54 16607 42 8.04299e+06 4.18335e+06 1.08842e+06 3359.33 5.60 1.37437 1.21416 33712 268580 -1 12763 24 9307 10561 1197981 287506 8.67428 8.67428 -895.049 -8.67428 0 0 1.34436e+06 4149.26 0.34 0.51 0.24 -1 -1 0.34 0.215604 0.192549 751 586 456 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_26.v common 15.07 vpr 72.17 MiB 0.11 11824 -1 -1 1 0.27 -1 -1 37384 -1 -1 105 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73900 22 19 2275 1648 1 1330 153 18 18 324 mult_36 auto 34.3 MiB 4.64 8508 22239 4415 15566 2258 72.2 MiB 0.62 0.01 9.42265 -590.577 -9.42265 9.42265 0.80 0.00445864 0.00401596 0.257362 0.233603 58 14084 47 8.04299e+06 4.23924e+06 1.14310e+06 3528.09 5.07 1.33825 1.18192 34680 290288 -1 11882 25 8955 10040 1155840 295020 8.75428 8.75428 -771.843 -8.75428 0 0 1.43297e+06 4422.75 0.37 0.49 0.24 -1 -1 0.37 0.224963 0.200306 779 605 475 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_27.v common 15.95 vpr 72.68 MiB 0.12 12180 -1 -1 1 0.31 -1 -1 36636 -1 -1 111 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74420 22 19 2385 1724 1 1404 160 18 18 324 mult_36 auto 34.8 MiB 4.54 8706 29238 6495 17225 5518 72.7 MiB 0.73 0.01 9.5032 -657.318 -9.5032 9.5032 0.82 0.00494662 0.00454829 0.328609 0.29886 54 15872 37 8.04299e+06 4.7191e+06 1.08842e+06 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-k6_frac_ripple_N8_22nm.xml fir_nopipe_29.v common 21.18 vpr 73.47 MiB 0.18 12728 -1 -1 1 0.34 -1 -1 37124 -1 -1 118 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75236 22 19 2565 1853 1 1511 168 22 22 484 mult_36 auto 35.8 MiB 5.07 9474 28874 6138 19875 2861 73.5 MiB 0.84 0.01 9.50133 -723.607 -9.50133 9.50133 1.27 0.00561174 0.0050836 0.359574 0.328413 48 19694 45 1.30842e+07 5.21292e+06 1.52614e+06 3153.19 8.93 1.66619 1.47757 49190 371334 -1 15172 26 14085 16168 2028455 476792 9.32778 9.32778 -1106.44 -9.32778 0 0 1.85176e+06 3825.95 0.50 0.70 0.33 -1 -1 0.50 0.26154 0.232522 881 694 532 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_30.v common 23.43 vpr 73.83 MiB 0.18 12628 -1 -1 1 0.34 -1 -1 37408 -1 -1 123 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75604 22 19 2639 1910 1 1549 173 22 22 484 mult_36 auto 36.1 MiB 5.43 9440 36248 7919 24781 3548 73.8 MiB 0.99 0.01 9.36191 -670.158 -9.36191 9.36191 1.30 0.00494298 0.00448404 0.423993 0.384622 48 20360 50 1.30842e+07 5.28279e+06 1.52614e+06 3153.19 10.37 1.80964 1.60233 49190 371334 -1 15247 24 13469 15202 1910838 455736 8.95958 8.95958 -928.137 -8.95958 0 0 1.85176e+06 3825.95 0.50 0.72 0.32 -1 -1 0.50 0.254704 0.227272 910 713 551 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_31.v common 20.52 vpr 75.10 MiB 0.11 12956 -1 -1 1 0.35 -1 -1 37316 -1 -1 128 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76900 22 19 2744 1981 1 1618 178 22 22 484 mult_36 auto 37.0 MiB 5.38 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-1 16006 25 13662 15590 1847779 424015 8.83758 8.83758 -1053.02 -8.83758 0 0 2.06816e+06 4273.05 0.59 0.75 0.35 -1 -1 0.59 0.284515 0.253659 974 764 589 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_33.v common 20.81 vpr 75.45 MiB 0.19 13676 -1 -1 1 0.29 -1 -1 37356 -1 -1 137 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77256 22 19 2923 2109 1 1726 188 22 22 484 mult_36 auto 37.9 MiB 5.35 10997 40538 8465 27874 4199 75.4 MiB 1.12 0.01 10.2864 -775.869 -10.2864 10.2864 1.27 0.00603775 0.00548455 0.463266 0.419405 52 22517 47 1.30842e+07 5.87443e+06 1.63434e+06 3376.74 8.03 1.96653 1.74365 50638 406276 -1 16574 24 12868 14850 1713334 417624 9.69202 9.69202 -1312.41 -9.69202 0 0 2.01763e+06 4168.66 0.52 0.60 0.36 -1 -1 0.52 0.259428 0.231175 1009 796 608 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_34.v common 23.72 vpr 75.49 MiB 0.15 13668 -1 -1 1 0.46 -1 -1 37768 -1 -1 140 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77304 22 19 2997 2166 1 1764 191 22 22 484 mult_36 auto 38.1 MiB 8.36 11197 34229 7090 23850 3289 75.5 MiB 0.93 0.01 10.179 -781.353 -10.179 10.179 1.24 0.0059064 0.00538226 0.383252 0.348114 54 21293 29 1.30842e+07 5.91636e+06 1.67518e+06 3461.11 7.73 1.7254 1.52965 51122 416746 -1 16721 23 13120 14891 1633684 395631 9.53142 9.53142 -1224.14 -9.53142 0 0 2.06816e+06 4273.05 0.54 0.66 0.38 -1 -1 0.54 0.27638 0.245962 1037 815 627 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_35.v common 23.83 vpr 76.11 MiB 0.25 14040 -1 -1 1 0.49 -1 -1 37616 -1 -1 145 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77940 22 19 3101 2236 1 1831 196 22 22 484 mult_36 auto 38.7 MiB 7.24 12065 39457 7984 27451 4022 76.1 MiB 1.09 0.02 10.526 -851.981 -10.526 10.526 1.24 0.00586591 0.00534859 0.436328 0.396044 56 22258 29 1.30842e+07 5.98623e+06 1.71605e+06 3545.56 8.54 1.85952 1.64959 51606 428054 -1 18193 24 12714 14593 1871341 439910 10.0876 10.0876 -1238.72 -10.0876 0 0 2.11301e+06 4365.72 0.61 0.73 0.36 -1 -1 0.61 0.297247 0.265421 1072 846 646 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_36.v common 24.33 vpr 76.50 MiB 0.20 14132 -1 -1 1 0.44 -1 -1 38020 -1 -1 148 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78332 22 19 3175 2293 1 1871 199 22 22 484 mult_36 auto 39.2 MiB 9.10 12207 40799 8234 28761 3804 76.5 MiB 1.07 0.02 10.1611 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-1 38268 -1 -1 161 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79784 22 19 3457 2490 1 2044 213 24 24 576 mult_36 auto 40.5 MiB 8.89 13552 45933 9854 31922 4157 77.9 MiB 1.23 0.02 10.2548 -903.58 -10.2548 10.2548 1.43 0.0061585 0.00559162 0.50214 0.4543 56 23176 27 1.57908e+07 6.60581e+06 2.03561e+06 3534.04 7.69 2.02374 1.79471 61006 507707 -1 19371 24 12670 14651 1649493 401965 9.71472 9.71472 -1420.41 -9.71472 0 0 2.50747e+06 4353.24 0.70 0.73 0.46 -1 -1 0.70 0.328048 0.292553 1198 946 722 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_40.v common 29.98 vpr 78.39 MiB 0.21 14836 -1 -1 1 0.55 -1 -1 38816 -1 -1 164 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80272 22 19 3531 2547 1 2082 216 24 24 576 mult_36 auto 41.0 MiB 10.45 14377 40977 8198 29796 2983 78.4 MiB 1.20 0.04 10.1711 -960.277 -10.1711 10.1711 1.48 0.0143787 0.0127714 0.458028 0.414102 54 25953 34 1.57908e+07 6.64774e+06 1.98675e+06 3449.22 10.60 2.07487 1.83836 60430 494267 -1 20022 24 14385 16625 1937405 463879 9.81632 9.81632 -1428.6 -9.81632 0 0 2.45377e+06 4260.01 0.64 0.73 0.39 -1 -1 0.64 0.314374 0.279746 1226 965 741 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_41.v common 35.16 vpr 78.74 MiB 0.28 15280 -1 -1 1 0.49 -1 -1 38148 -1 -1 170 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80628 22 19 3634 2616 1 2147 223 24 24 576 mult_36 auto 41.5 MiB 9.41 15712 55655 12202 38909 4544 78.7 MiB 1.47 0.02 10.3763 -978.657 -10.3763 10.3763 1.47 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2.61600e+06 4541.67 0.71 0.81 0.45 -1 -1 0.71 0.329232 0.292614 1289 1014 779 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_43.v common 36.71 vpr 79.58 MiB 0.18 15700 -1 -1 1 0.52 -1 -1 39024 -1 -1 178 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81492 22 19 3810 2741 1 2253 231 24 24 576 mult_36 auto 42.4 MiB 10.00 15931 45543 9198 31101 5244 79.6 MiB 1.19 0.02 10.2488 -1034.23 -10.2488 10.2488 1.39 0.00703787 0.00638807 0.446452 0.40357 58 28790 31 1.57908e+07 7.23937e+06 2.08734e+06 3623.85 17.51 2.14457 1.89576 62154 534210 -1 22784 25 17469 20003 2871017 629000 9.78802 9.78802 -1425.18 -9.78802 0 0 2.61600e+06 4541.67 0.70 0.99 0.44 -1 -1 0.70 0.367709 0.327023 1323 1043 798 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_44.v common 31.84 vpr 79.89 MiB 0.19 15672 -1 -1 1 0.62 -1 -1 38428 -1 -1 181 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81804 22 19 3884 2798 1 2294 234 24 24 576 mult_36 auto 42.5 MiB 11.63 15026 47034 9339 32867 4828 79.9 MiB 1.26 0.02 10.6634 -975.806 -10.6634 10.6634 1.49 0.00718101 0.00652364 0.497842 0.448355 56 25505 43 1.57908e+07 7.28129e+06 2.03561e+06 3534.04 10.72 2.34961 2.07315 61006 507707 -1 21177 24 13604 15932 1830861 450606 10.1266 10.1266 -1497.53 -10.1266 0 0 2.50747e+06 4353.24 0.75 0.86 0.45 -1 -1 0.75 0.39966 0.357524 1351 1062 817 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_45.v common 34.45 vpr 80.38 MiB 0.20 15976 -1 -1 1 0.56 -1 -1 40620 -1 -1 186 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82304 22 19 3989 2869 1 2359 240 24 24 576 mult_36 auto 43.1 MiB 10.86 16504 49410 9364 35589 4457 80.4 MiB 1.34 0.02 10.4128 -1039.57 -10.4128 10.4128 1.47 0.00736411 0.00667934 0.524551 0.472825 58 28065 31 1.57908e+07 7.74716e+06 2.08734e+06 3623.85 14.02 2.31055 2.04279 62154 534210 -1 23178 24 14780 17083 2031719 479355 10.0216 10.0216 -1620.1 -10.0216 0 0 2.61600e+06 4541.67 0.76 0.85 0.46 -1 -1 0.76 0.380055 0.340905 1387 1094 836 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_46.v common 34.08 vpr 80.50 MiB 0.16 16112 -1 -1 1 0.51 -1 -1 40524 -1 -1 189 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82428 22 19 4063 2926 1 2398 243 24 24 576 mult_36 auto 43.3 MiB 12.69 15456 49513 9815 35157 4541 80.5 MiB 1.38 0.02 10.3988 -1055.79 -10.3988 10.3988 1.48 0.00738406 0.00670027 0.527894 0.477333 54 30376 49 1.57908e+07 7.78909e+06 1.98675e+06 3449.22 11.93 2.5705 2.26971 60430 494267 -1 22258 25 14010 16246 1792980 437746 10.0703 10.0703 -1496.13 -10.0703 0 0 2.45377e+06 4260.01 0.71 0.83 0.42 -1 -1 0.71 0.407104 0.363229 1414 1113 855 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_47.v common 31.04 vpr 80.99 MiB 0.29 16436 -1 -1 1 0.50 -1 -1 40912 -1 -1 194 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82936 22 19 4167 2996 1 2466 248 24 24 576 mult_36 auto 43.9 MiB 11.29 16457 49262 9642 34224 5396 81.0 MiB 1.33 0.02 10.2964 -1023.88 -10.2964 10.2964 1.45 0.00767253 0.00696798 0.528201 0.475734 62 27413 41 1.57908e+07 7.85896e+06 2.19658e+06 3813.51 10.15 2.47844 2.18562 63306 560109 -1 22126 24 15880 18201 1967159 487181 9.26852 9.26852 -1515.46 -9.26852 0 0 2.72095e+06 4723.87 0.80 0.85 0.42 -1 -1 0.80 0.382417 0.341094 1449 1144 874 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_48.v common 37.43 vpr 81.34 MiB 0.29 16504 -1 -1 1 0.60 -1 -1 40704 -1 -1 197 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83288 22 19 4241 3053 1 2505 251 24 24 576 mult_36 auto 44.2 MiB 13.09 16971 46920 8877 33152 4891 81.3 MiB 1.26 0.02 10.3426 -1105.68 -10.3426 10.3426 1.41 0.00707168 0.00637172 0.454538 0.408531 58 28357 39 1.57908e+07 7.90088e+06 2.08734e+06 3623.85 14.75 2.52654 2.23221 62154 534210 -1 23109 25 14819 17069 1985321 468184 9.32312 9.32312 -1714.79 -9.32312 0 0 2.61600e+06 4541.67 0.71 0.84 0.45 -1 -1 0.71 0.394003 0.351585 1477 1163 893 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_49.v common 31.77 vpr 81.89 MiB 0.24 16968 -1 -1 1 0.63 -1 -1 41060 -1 -1 204 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83852 22 19 4346 3124 1 2572 259 24 24 576 mult_36 auto 44.8 MiB 12.23 17818 58009 12065 38423 7521 81.9 MiB 1.51 0.02 10.4215 -1066.19 -10.4215 10.4215 1.46 0.0080745 0.00733701 0.604224 0.544123 64 27669 29 1.57908e+07 8.3947e+06 2.26035e+06 3924.22 9.46 2.45546 2.1712 64454 586630 -1 23761 23 15470 17571 1974721 480976 10.0026 10.0026 -1667.25 -10.0026 0 0 2.84938e+06 4946.85 0.77 0.83 0.50 -1 -1 0.77 0.375436 0.332674 1512 1195 912 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_50.v common 38.16 vpr 82.15 MiB 0.29 17100 -1 -1 1 0.66 -1 -1 41020 -1 -1 206 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84120 22 19 4420 3181 1 2611 261 24 24 576 mult_36 auto 44.8 MiB 13.82 18113 59404 12055 41197 6152 82.1 MiB 1.17 0.02 10.7633 -1102.87 -10.7633 10.7633 1.43 0.00500541 0.00457353 0.399298 0.359786 58 30827 50 1.57908e+07 8.42264e+06 2.08734e+06 3623.85 14.62 2.65311 2.33328 62154 534210 -1 25105 24 17430 20166 2474881 582739 9.91802 9.91802 -1434.59 -9.91802 0 0 2.61600e+06 4541.67 0.83 0.99 0.44 -1 -1 0.83 0.413443 0.368887 1541 1214 931 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_51.v common 35.76 vpr 82.72 MiB 0.36 17424 -1 -1 1 0.69 -1 -1 41064 -1 -1 211 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84708 22 19 4524 3251 1 2681 266 24 24 576 mult_36 auto 45.6 MiB 12.68 17903 58406 11821 39335 7250 82.7 MiB 1.54 0.02 10.1189 -1113.35 -10.1189 10.1189 1.47 0.00840097 0.00762828 0.598606 0.537073 66 28650 46 1.57908e+07 8.49251e+06 2.33135e+06 4047.49 12.41 2.79535 2.46899 65030 601923 -1 23838 22 15662 18095 2053216 483046 9.32782 9.32782 -1570.64 -9.32782 0 0 2.91907e+06 5067.82 0.88 0.90 0.53 -1 -1 0.88 0.406862 0.363976 1576 1245 950 19 0 0 -k6_frac_ripple_N8_22nm.xml fir_nopipe_52.v common 38.64 vpr 83.15 MiB 0.31 17420 -1 -1 1 0.66 -1 -1 39328 -1 -1 215 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85148 22 19 4598 3308 1 2718 270 24 24 576 mult_36 auto 46.1 MiB 14.46 18499 60438 12754 41701 5983 83.2 MiB 1.60 0.02 10.3652 -1274.39 -10.3652 10.3652 1.47 0.00856926 0.00761627 0.633263 0.568286 60 30704 47 1.57908e+07 8.54841e+06 2.13333e+06 3703.69 13.56 2.91685 2.57247 62730 548095 -1 24767 24 17273 19354 2179586 520270 9.64242 9.64242 -1770.68 -9.64242 0 0 2.67122e+06 4637.53 0.72 1.11 0.45 -1 -1 0.72 0.496032 0.445053 1605 1264 969 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_14.v common 7.87 vpr 70.55 MiB 0.07 10524 -1 -1 1 0.24 -1 -1 35484 -1 -1 81 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72248 22 19 1974 1653 1 1020 126 16 16 256 mult_36 auto 32.4 MiB 0.34 5566 18081 3979 11568 2534 70.6 MiB 0.43 0.01 4.18656 -1184 -4.18656 4.18656 0.67 0.00356539 0.00320963 0.220467 0.198858 50 12015 26 6.54114e+06 2.7256e+06 787708. 3076.99 3.45 1.01169 0.882887 25344 186282 -1 9252 17 4107 4636 547995 139041 4.41926 4.41926 -1238.23 -4.41926 0 0 943753. 3686.54 0.24 0.26 0.16 -1 -1 0.24 0.141423 0.125975 605 708 247 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_15.v common 8.30 vpr 71.43 MiB 0.11 10904 -1 -1 1 0.26 -1 -1 36900 -1 -1 88 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73144 22 19 2144 1789 1 1120 134 16 16 256 mult_36 auto 33.2 MiB 0.36 6319 20654 4053 14159 2442 71.4 MiB 0.51 0.01 4.29396 -1347.48 -4.29396 4.29396 0.58 0.00372143 0.00335451 0.253783 0.22888 50 12838 32 6.54114e+06 3.22025e+06 787708. 3076.99 3.77 1.17955 1.03156 25344 186282 -1 10194 15 4381 5331 543271 135603 4.41926 4.41926 -1427.22 -4.41926 0 0 943753. 3686.54 0.23 0.24 0.17 -1 -1 0.23 0.128701 0.114324 654 769 266 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_16.v common 8.39 vpr 71.61 MiB 0.10 10948 -1 -1 1 0.28 -1 -1 36840 -1 -1 91 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73332 22 19 2218 1846 1 1162 137 16 16 256 mult_36 auto 33.5 MiB 0.37 6746 20611 4243 13930 2438 71.6 MiB 0.50 0.01 4.27196 -1343.11 -4.27196 4.27196 0.59 0.0032663 0.00291636 0.239428 0.215294 56 12205 20 6.54114e+06 3.26253e+06 849745. 3319.32 3.49 1.14162 1.001 26364 208198 -1 10886 18 4466 5238 632605 153751 4.54456 4.54456 -1414.59 -4.54456 0 0 1.04740e+06 4091.43 0.29 0.30 0.19 -1 -1 0.29 0.15905 0.140984 683 788 285 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_17.v common 9.73 vpr 72.91 MiB 0.08 11792 -1 -1 1 0.32 -1 -1 36508 -1 -1 103 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74660 22 19 2536 2130 1 1275 149 16 16 256 mult_36 auto 34.6 MiB 0.47 7309 25759 5410 16752 3597 72.9 MiB 0.59 0.01 4.22437 -1538.56 -4.22437 4.22437 0.57 0.00421061 0.00376811 0.292735 0.261633 54 15370 50 6.54114e+06 3.43166e+06 829453. 3240.05 4.63 1.49103 1.29857 26108 202796 -1 11251 20 4866 5650 591941 150326 4.41926 4.41926 -1554.25 -4.41926 0 0 1.02522e+06 4004.78 0.27 0.32 0.18 -1 -1 0.27 0.191262 0.168408 770 924 304 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_18.v common 10.30 vpr 73.96 MiB 0.11 11880 -1 -1 1 0.29 -1 -1 37264 -1 -1 107 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75732 22 19 2610 2187 1 1316 153 16 16 256 mult_36 auto 35.4 MiB 0.45 7489 21012 3652 14420 2940 74.0 MiB 0.52 0.01 4.05741 -1594.66 -4.05741 4.05741 0.59 0.00442383 0.00397394 0.261885 0.235686 58 14224 36 6.54114e+06 3.48803e+06 871168. 3403.00 5.23 1.41298 1.23272 26872 219187 -1 11540 19 4929 5820 646042 159250 4.41926 4.41926 -1618.92 -4.41926 0 0 1.09288e+06 4269.05 0.26 0.39 0.19 -1 -1 0.26 0.204211 0.18126 798 943 323 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_19.v common 10.55 vpr 74.75 MiB 0.14 12128 -1 -1 1 0.25 -1 -1 36804 -1 -1 113 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76548 22 19 2778 2321 1 1412 160 16 16 256 mult_36 auto 36.3 MiB 0.47 8590 28804 5795 19118 3891 74.8 MiB 0.72 0.01 4.16866 -1754.96 -4.16866 4.16866 0.60 0.00457112 0.00408692 0.351306 0.314519 60 14551 41 6.54114e+06 3.96859e+06 890343. 3477.90 5.43 1.68264 1.47097 27128 224764 -1 12108 19 5195 6165 612347 148881 4.29396 4.29396 -1780.33 -4.29396 0 0 1.11577e+06 4358.47 0.27 0.35 0.17 -1 -1 0.27 0.205204 0.181382 846 1002 342 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_20.v common 11.37 vpr 74.61 MiB 0.10 12396 -1 -1 1 0.31 -1 -1 37000 -1 -1 118 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76400 22 19 2852 2378 1 1455 165 16 16 256 mult_36 auto 36.7 MiB 0.47 8719 21409 3812 14750 2847 74.6 MiB 0.53 0.01 4.23032 -1751.68 -4.23032 4.23032 0.57 0.00497053 0.00445561 0.253389 0.227057 58 15488 34 6.54114e+06 4.03906e+06 871168. 3403.00 6.21 1.50021 1.30756 26872 219187 -1 12591 16 5346 6342 671911 168571 4.29396 4.29396 -1828.31 -4.29396 0 0 1.09288e+06 4269.05 0.30 0.33 0.19 -1 -1 0.30 0.183129 0.162478 875 1021 361 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_21.v common 11.40 vpr 75.77 MiB 0.14 12892 -1 -1 1 0.38 -1 -1 37876 -1 -1 122 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77592 22 19 3057 2549 1 1560 169 16 16 256 mult_36 auto 37.8 MiB 0.52 9662 28189 5474 18473 4242 75.8 MiB 0.72 0.01 4.27196 -1924.27 -4.27196 4.27196 0.56 0.00527906 0.00471781 0.33261 0.296421 60 16376 39 6.54114e+06 4.09544e+06 890343. 3477.90 5.78 1.68732 1.4696 27128 224764 -1 13229 17 5417 6865 651246 161214 4.52256 4.52256 -1946.8 -4.52256 0 0 1.11577e+06 4358.47 0.29 0.37 0.20 -1 -1 0.29 0.214974 0.191547 932 1099 380 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_22.v common 11.22 vpr 75.77 MiB 0.15 13000 -1 -1 1 0.36 -1 -1 38084 -1 -1 125 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77584 22 19 3131 2606 1 1600 172 16 16 256 mult_36 auto 37.8 MiB 0.50 9746 26940 4762 17615 4563 75.8 MiB 0.74 0.01 4.1051 -1925.37 -4.1051 4.1051 0.60 0.00611816 0.00544144 0.356751 0.319711 64 17025 40 6.54114e+06 4.13772e+06 943753. 3686.54 5.32 1.70879 1.49331 27892 240595 -1 13419 19 5604 6604 696533 174227 4.41926 4.41926 -1888.34 -4.41926 0 0 1.19033e+06 4649.74 0.30 0.40 0.23 -1 -1 0.30 0.237528 0.209958 961 1118 399 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_23.v common 16.07 vpr 76.61 MiB 0.17 13432 -1 -1 1 0.37 -1 -1 37772 -1 -1 133 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78444 22 19 3301 2742 1 1700 181 18 18 324 mult_36 auto 38.7 MiB 0.59 10073 29819 5770 20700 3349 76.6 MiB 0.78 0.01 4.29396 -2072.96 -4.29396 4.29396 0.94 0.00542746 0.00490157 0.375376 0.33652 58 20039 44 8.06603e+06 4.64648e+06 1.14310e+06 3528.09 9.23 1.91764 1.67586 34680 290288 -1 15296 19 6397 7351 896472 206109 4.52256 4.52256 -2107.99 -4.52256 0 0 1.43297e+06 4422.75 0.40 0.44 0.25 -1 -1 0.40 0.240683 0.213451 1012 1179 418 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_24.v common 14.61 vpr 77.01 MiB 0.16 13444 -1 -1 1 0.37 -1 -1 38100 -1 -1 137 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78856 22 19 3375 2799 1 1744 185 18 18 324 mult_36 auto 39.0 MiB 0.53 10242 28589 5033 20765 2791 77.0 MiB 0.77 0.01 4.16866 -2095.84 -4.16866 4.16866 0.89 0.00584888 0.00521185 0.358826 0.320166 56 19239 34 8.06603e+06 4.70285e+06 1.11497e+06 3441.27 8.07 1.89179 1.65394 34036 275796 -1 15430 18 6668 8155 902923 218175 4.66986 4.66986 -2283.29 -4.66986 0 0 1.37338e+06 4238.83 0.34 0.45 0.23 -1 -1 0.34 0.243287 0.216124 1041 1198 437 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_25.v common 12.96 vpr 77.87 MiB 0.14 13944 -1 -1 1 0.45 -1 -1 38164 -1 -1 146 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79740 22 19 3615 3005 1 1848 194 18 18 324 mult_36 auto 39.9 MiB 0.63 11381 30488 5169 21849 3470 77.9 MiB 0.84 0.01 4.29396 -2317.79 -4.29396 4.29396 0.96 0.00648239 0.00577959 0.389275 0.347872 60 19735 24 8.06603e+06 4.8297e+06 1.16833e+06 3605.96 5.76 1.97602 1.73231 35004 297736 -1 15899 18 6600 7758 807688 195562 4.41926 4.41926 -2334.44 -4.41926 0 0 1.46313e+06 4515.82 0.41 0.46 0.27 -1 -1 0.41 0.266483 0.237429 1107 1293 456 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_26.v common 15.61 vpr 78.54 MiB 0.13 14192 -1 -1 1 0.42 -1 -1 38520 -1 -1 148 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80428 22 19 3689 3062 1 1888 196 18 18 324 mult_36 auto 40.5 MiB 0.63 11433 29784 5199 21859 2726 78.5 MiB 0.82 0.02 4.24437 -2303.41 -4.24437 4.24437 0.85 0.00711705 0.00628036 0.378532 0.339296 58 20982 37 8.06603e+06 4.85789e+06 1.14310e+06 3528.09 8.60 2.11816 1.84746 34680 290288 -1 16695 16 7063 8326 925400 221942 4.41926 4.41926 -2385.92 -4.41926 0 0 1.43297e+06 4422.75 0.36 0.47 0.24 -1 -1 0.36 0.260815 0.235816 1135 1312 475 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_27.v common 14.19 vpr 79.47 MiB 0.19 14444 -1 -1 1 0.48 -1 -1 38456 -1 -1 156 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81380 22 19 3871 3210 1 2002 205 18 18 324 mult_36 auto 41.4 MiB 0.56 12765 36445 6420 26320 3705 79.5 MiB 0.96 0.02 4.54456 -2408.49 -4.54456 4.54456 0.82 0.00685927 0.00612775 0.437842 0.392218 64 23264 38 8.06603e+06 5.36665e+06 1.23838e+06 3822.15 6.95 2.19503 1.91755 35972 318676 -1 18200 18 7220 8450 972098 233171 4.52256 4.52256 -2487.12 -4.52256 0 0 1.56068e+06 4816.91 0.48 0.50 0.28 -1 -1 0.48 0.289327 0.259022 1191 1385 494 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_28.v common 14.33 vpr 79.86 MiB 0.11 14480 -1 -1 1 0.47 -1 -1 38392 -1 -1 160 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81780 22 19 3945 3267 1 2045 209 18 18 324 mult_36 auto 41.9 MiB 0.70 12597 35549 6371 25304 3874 79.9 MiB 0.91 0.02 4.26697 -2505.98 -4.26697 4.26697 0.79 0.00592329 0.00528273 0.412317 0.367578 68 21534 29 8.06603e+06 5.42302e+06 1.31159e+06 4048.11 7.05 2.09847 1.8353 36620 334356 -1 17403 19 7212 8305 866718 201384 4.29396 4.29396 -2504.3 -4.29396 0 0 1.63345e+06 5041.52 0.41 0.50 0.28 -1 -1 0.41 0.292126 0.259432 1219 1404 513 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_29.v common 17.90 vpr 80.95 MiB 0.17 14996 -1 -1 1 0.48 -1 -1 39736 -1 -1 170 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82888 22 19 4159 3447 1 2159 220 22 22 484 mult_36 auto 42.9 MiB 0.66 13941 43978 8874 31271 3833 80.9 MiB 1.17 0.02 4.35022 -2631.97 -4.35022 4.35022 1.25 0.00774696 0.00697861 0.556098 0.499879 58 24926 40 1.31202e+07 5.95997e+06 1.75961e+06 3635.55 9.01 2.41905 2.11286 52570 450426 -1 20690 17 8007 9443 1068841 244740 4.54456 4.54456 -2664.53 -4.54456 0 0 2.20457e+06 4554.90 0.59 0.56 0.38 -1 -1 0.59 0.298787 0.265732 1283 1491 532 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_30.v common 17.61 vpr 81.04 MiB 0.31 15108 -1 -1 1 0.50 -1 -1 40796 -1 -1 173 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82984 22 19 4233 3504 1 2198 223 22 22 484 mult_36 auto 43.1 MiB 0.70 14275 43487 8406 30788 4293 81.0 MiB 1.13 0.02 4.29396 -2676.94 -4.29396 4.29396 1.20 0.00692972 0.00618355 0.508408 0.45329 62 26940 39 1.31202e+07 6.00225e+06 1.85176e+06 3825.95 8.47 2.36766 2.06397 53538 472186 -1 20137 19 7963 9293 978277 226339 4.39726 4.39726 -2703.02 -4.39726 0 0 2.29262e+06 4736.82 0.66 0.56 0.41 -1 -1 0.66 0.316801 0.28135 1311 1510 551 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_31.v common 20.11 vpr 82.97 MiB 0.24 15504 -1 -1 1 0.53 -1 -1 41024 -1 -1 179 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84960 22 19 4410 3647 1 2305 229 22 22 484 mult_36 auto 44.0 MiB 0.73 14328 48529 9744 34610 4175 83.0 MiB 1.21 0.02 4.31186 -2776.62 -4.31186 4.31186 1.19 0.00763571 0.00681491 0.544669 0.484896 60 26322 48 1.31202e+07 6.08682e+06 1.79840e+06 3715.71 10.61 2.63139 2.29142 53054 462096 -1 20969 18 8442 9887 1082581 257139 4.39726 4.39726 -2815.55 -4.39726 0 0 2.25108e+06 4650.99 0.71 0.59 0.38 -1 -1 0.71 0.326546 0.291041 1363 1578 570 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_32.v common 15.71 vpr 82.19 MiB 0.19 15580 -1 -1 1 0.53 -1 -1 40672 -1 -1 183 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 84164 22 19 4484 3704 1 2348 233 22 22 484 mult_36 auto 44.2 MiB 0.73 14525 45341 8355 32699 4287 82.2 MiB 1.16 0.02 4.41926 -2881.16 -4.41926 4.41926 1.21 0.00766067 0.00686394 0.513788 0.459417 60 25283 24 1.31202e+07 6.14319e+06 1.79840e+06 3715.71 6.97 2.2262 1.94485 53054 462096 -1 21198 18 8307 9417 1043367 244738 4.41926 4.41926 -2865.53 -4.41926 0 0 2.25108e+06 4650.99 0.61 0.56 0.32 -1 -1 0.61 0.315484 0.280564 1393 1597 589 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_33.v common 18.91 vpr 84.66 MiB 0.22 16620 -1 -1 1 0.59 -1 -1 41660 -1 -1 196 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86688 22 19 4843 4029 1 2463 247 22 22 484 mult_36 auto 46.0 MiB 0.78 15998 49783 9671 35687 4425 84.7 MiB 1.28 0.02 4.54456 -3078.09 -4.54456 4.54456 1.19 0.00747416 0.00663489 0.560167 0.499174 62 30039 29 1.31202e+07 6.72242e+06 1.85176e+06 3825.95 9.26 2.48747 2.16446 53538 472186 -1 22471 18 8965 10546 1092220 257195 4.41926 4.41926 -3312.48 -4.41926 0 0 2.29262e+06 4736.82 0.59 0.58 0.41 -1 -1 0.59 0.352441 0.314917 1490 1756 608 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_34.v common 19.55 vpr 84.04 MiB 0.25 16760 -1 -1 1 0.57 -1 -1 41600 -1 -1 199 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86060 22 19 4917 4086 1 2505 250 22 22 484 mult_36 auto 46.4 MiB 0.77 15240 53766 10631 37846 5289 84.0 MiB 1.33 0.02 4.29396 -3047.21 -4.29396 4.29396 1.18 0.00808591 0.00721489 0.588263 0.523476 60 28229 35 1.31202e+07 6.7647e+06 1.79840e+06 3715.71 9.97 2.63886 2.29656 53054 462096 -1 22321 17 8852 10511 1134513 265850 4.52256 4.52256 -3384.85 -4.52256 0 0 2.25108e+06 4650.99 0.63 0.60 0.40 -1 -1 0.63 0.335676 0.2989 1519 1775 627 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_35.v common 23.64 vpr 85.00 MiB 0.24 17068 -1 -1 1 0.68 -1 -1 41824 -1 -1 207 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87040 22 19 5093 4228 1 2607 258 22 22 484 mult_36 auto 47.3 MiB 0.79 16561 53623 9690 39001 4932 85.0 MiB 1.34 0.02 4.27196 -3266.59 -4.27196 4.27196 1.24 0.00830998 0.0075757 0.581879 0.518075 60 31544 47 1.31202e+07 6.87745e+06 1.79840e+06 3715.71 13.58 3.07471 2.68119 53054 462096 -1 24567 20 9974 11801 1384303 319840 4.64786 4.64786 -3518.09 -4.64786 0 0 2.25108e+06 4650.99 0.64 0.77 0.37 -1 -1 0.64 0.428809 0.381439 1572 1842 646 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_36.v common 17.81 vpr 85.26 MiB 0.14 17200 -1 -1 1 0.65 -1 -1 41692 -1 -1 209 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 87308 22 19 5167 4285 1 2655 260 22 22 484 mult_36 auto 47.4 MiB 0.83 17463 54974 10444 39030 5500 85.3 MiB 1.42 0.02 4.35562 -3241.22 -4.35562 4.35562 1.19 0.00860278 0.00767459 0.617579 0.546968 66 29932 33 1.31202e+07 6.90564e+06 1.96511e+06 4060.15 7.92 2.75677 2.40228 54986 507526 -1 24310 15 9330 10872 1221412 282633 4.41926 4.41926 -3341.91 -4.41926 0 0 2.45963e+06 5081.88 0.65 0.58 0.40 -1 -1 0.65 0.312635 0.278695 1600 1861 665 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_37.v common 27.73 vpr 87.54 MiB 0.26 17768 -1 -1 1 0.54 -1 -1 40916 -1 -1 218 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89640 22 19 5380 4464 1 2756 270 24 24 576 mult_36 auto 48.8 MiB 0.86 18706 56950 10603 41531 4816 87.5 MiB 1.41 0.02 4.35562 -3473.4 -4.35562 4.35562 1.50 0.00838022 0.00746015 0.610354 0.542795 60 36033 48 1.58331e+07 7.42849e+06 2.13333e+06 3703.69 16.72 3.22557 2.81696 62730 548095 -1 27276 19 10671 12691 1595594 352262 4.54456 4.54456 -3667.6 -4.54456 0 0 2.67122e+06 4637.53 0.72 0.73 0.46 -1 -1 0.72 0.392459 0.34775 1662 1947 684 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_38.v common 22.21 vpr 86.79 MiB 0.26 17700 -1 -1 1 0.70 -1 -1 42288 -1 -1 220 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 88868 22 19 5454 4521 1 2804 272 24 24 576 mult_36 auto 49.1 MiB 0.86 18631 58418 11427 42785 4206 86.8 MiB 1.49 0.02 4.29396 -3507.9 -4.29396 4.29396 1.45 0.00871041 0.00776012 0.630769 0.558119 62 35211 42 1.58331e+07 7.45668e+06 2.19658e+06 3813.51 11.05 3.14164 2.73658 63306 560109 -1 26641 17 10663 12453 1388485 323603 4.39726 4.39726 -3646.05 -4.39726 0 0 2.72095e+06 4723.87 0.74 0.69 0.45 -1 -1 0.74 0.371924 0.331025 1690 1966 703 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_39.v common 25.05 vpr 87.38 MiB 0.29 18144 -1 -1 1 0.73 -1 -1 40268 -1 -1 228 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 89472 22 19 5629 4662 1 2910 280 24 24 576 mult_36 auto 49.9 MiB 0.89 20090 64330 13333 46393 4604 87.4 MiB 1.77 0.02 4.55861 -3641.68 -4.55861 4.55861 1.58 0.0105706 0.00923672 0.76296 0.67492 66 38359 44 1.58331e+07 7.56943e+06 2.33135e+06 4047.49 13.56 3.38858 2.95709 65030 601923 -1 28690 16 10858 13238 1585011 358083 4.54456 4.54456 -3858.1 -4.54456 0 0 2.91907e+06 5067.82 0.82 0.68 0.42 -1 -1 0.82 0.309942 0.278263 1742 2032 722 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_40.v common 26.03 vpr 88.15 MiB 0.16 18344 -1 -1 1 0.75 -1 -1 42292 -1 -1 232 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 90268 22 19 5703 4719 1 2952 284 24 24 576 mult_36 auto 50.3 MiB 0.97 18947 59996 11849 42843 5304 87.7 MiB 1.58 0.02 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1 0.89 -1 -1 43280 -1 -1 250 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92720 22 19 6198 5129 1 3209 303 24 24 576 mult_36 auto 52.8 MiB 1.03 22784 60306 10847 44895 4564 90.0 MiB 1.63 0.03 4.66986 -4092.44 -4.66986 4.66986 1.56 0.010458 0.00933727 0.683433 0.609507 68 38832 41 1.58331e+07 8.2755e+06 2.39371e+06 4155.74 15.82 3.42817 2.98344 65606 615345 -1 31135 17 11588 13651 1552306 353970 4.54456 4.54456 -4162.55 -4.54456 0 0 2.98162e+06 5176.42 0.80 0.76 0.49 -1 -1 0.80 0.414118 0.368413 1921 2237 798 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_44.v common 24.51 vpr 90.27 MiB 0.24 19576 -1 -1 1 0.89 -1 -1 43548 -1 -1 253 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 92432 22 19 6272 5186 1 3255 306 24 24 576 mult_36 auto 52.8 MiB 1.02 21212 62106 11016 45638 5452 90.3 MiB 1.89 0.03 4.29396 -3963.31 -4.29396 4.29396 1.50 0.0118959 0.0107204 0.811675 0.728958 66 38086 47 1.58331e+07 8.31778e+06 2.33135e+06 4047.49 12.08 3.96345 3.47157 65030 601923 -1 29668 16 11714 13642 1536421 356784 4.52256 4.52256 -4103.45 -4.52256 0 0 2.91907e+06 5067.82 0.82 0.73 0.50 -1 -1 0.82 0.396822 0.353156 1949 2256 817 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_45.v common 23.95 vpr 93.04 MiB 0.29 19992 -1 -1 1 0.99 -1 -1 43872 -1 -1 262 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 95268 22 19 6485 5365 1 3364 316 24 24 576 mult_36 auto 53.9 MiB 1.06 21665 63741 11956 46622 5163 91.4 MiB 1.69 0.03 4.41926 -4168.43 -4.41926 4.41926 1.43 0.0109101 0.00976255 0.702499 0.622845 64 37095 22 1.58331e+07 8.84063e+06 2.26035e+06 3924.22 11.56 3.25556 2.83432 64454 586630 -1 31001 18 12007 14131 1617183 372391 4.54456 4.54456 -4244.66 -4.54456 0 0 2.84938e+06 4946.85 0.84 0.83 0.47 -1 -1 0.84 0.455739 0.405333 2011 2342 836 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_46.v common 28.82 vpr 94.72 MiB 0.17 20176 -1 -1 1 0.95 -1 -1 44120 -1 -1 266 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96992 22 19 6559 5422 1 3406 320 24 24 576 mult_36 auto 54.3 MiB 1.11 22395 70336 13410 49504 7422 91.7 MiB 1.88 0.03 4.29396 -4167.58 -4.29396 4.29396 1.55 0.0104906 0.00933311 0.751473 0.664137 68 38012 39 1.58331e+07 8.897e+06 2.39371e+06 4155.74 15.77 3.61694 3.13945 65606 615345 -1 30883 18 11581 13686 1504829 345509 4.41926 4.41926 -4245.28 -4.41926 0 0 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v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 99552 22 19 6809 5621 1 3556 330 24 24 576 mult_36 auto 55.5 MiB 1.24 24443 75504 14693 54581 6230 92.9 MiB 2.12 0.03 4.54456 -4333.82 -4.54456 4.54456 1.61 0.0130596 0.0117811 0.89344 0.798428 68 41304 32 1.58331e+07 9.03794e+06 2.39371e+06 4155.74 14.16 4.00794 3.5132 65606 615345 -1 32992 16 12193 14996 1577116 364367 4.66986 4.66986 -4785.3 -4.66986 0 0 2.98162e+06 5176.42 0.83 0.79 0.49 -1 -1 0.83 0.434988 0.387791 2121 2447 893 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_49.v common 25.51 vpr 96.57 MiB 0.23 21104 -1 -1 1 1.09 -1 -1 44384 -1 -1 287 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 98888 22 19 7094 5872 1 3671 342 24 24 576 mult_36 auto 56.6 MiB 1.18 24412 81602 15797 59095 6710 94.3 MiB 2.29 0.03 4.66986 -4735 -4.66986 4.66986 1.59 0.0116342 0.0102507 0.880052 0.775715 76 38504 31 1.58331e+07 9.58898e+06 2.61600e+06 4541.67 11.47 3.75695 3.26879 68478 680951 -1 32830 17 11929 13673 1640992 357972 4.92046 4.92046 -4741.32 -4.92046 0 0 3.24203e+06 5628.53 0.93 0.87 0.55 -1 -1 0.93 0.489288 0.436653 2200 2569 912 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_50.v common 27.54 vpr 98.38 MiB 0.35 21340 -1 -1 1 1.16 -1 -1 44232 -1 -1 290 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 100736 22 19 7168 5929 1 3712 345 24 24 576 mult_36 auto 57.1 MiB 1.25 25160 76512 14255 54563 7694 94.7 MiB 1.93 0.03 4.47552 -4598.48 -4.47552 4.47552 1.61 0.013865 0.0125473 0.804796 0.724721 70 41615 40 1.58331e+07 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2655 950 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_pipe_52.v common 32.37 vpr 102.40 MiB 0.37 21760 -1 -1 1 1.14 -1 -1 45136 -1 -1 301 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 104856 22 19 7418 6128 1 3860 356 24 24 576 mult_36 auto 58.7 MiB 1.26 25970 87365 17770 61046 8549 96.3 MiB 2.54 0.03 4.34967 -4804.09 -4.34967 4.34967 1.60 0.0145542 0.0131418 1.06436 0.932564 72 44233 45 1.58331e+07 9.78629e+06 2.50747e+06 4353.24 17.54 4.64956 4.04739 67330 654343 -1 35405 17 12953 15244 1834273 401238 4.54456 4.54456 -4810.48 -4.54456 0 0 3.14081e+06 5452.80 0.85 0.91 0.53 -1 -1 0.85 0.514887 0.459964 2310 2674 969 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_14.v common 18.72 vpr 66.80 MiB 0.10 9440 -1 -1 1 0.19 -1 -1 34640 -1 -1 58 22 0 4 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68404 22 19 1246 925 1 732 103 16 16 256 mult_36 auto 28.4 MiB 1.17 4023 13117 2985 8070 2062 66.8 MiB 0.34 0.01 8.30942 -383.734 -8.30942 8.30942 0.59 0.00262001 0.00241154 0.150191 0.137092 40 8052 31 6.54114e+06 2.40144e+06 616420. 2407.89 13.83 1.33095 1.17365 23812 153515 -1 6887 25 6377 7252 840667 207113 7.83898 7.83898 -465.002 -7.83898 0 0 808720. 3159.06 0.20 0.35 0.14 -1 -1 0.20 0.139969 0.124794 421 344 247 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_15.v common 8.49 vpr 67.56 MiB 0.07 9596 -1 -1 1 0.18 -1 -1 35084 -1 -1 61 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69180 22 19 1344 989 1 791 107 16 16 256 mult_36 auto 29.3 MiB 0.96 4575 14022 3062 9140 1820 67.6 MiB 0.35 0.01 8.46467 -389.974 -8.46467 8.46467 0.59 0.00303809 0.00280853 0.166695 0.152832 42 9875 50 6.54114e+06 2.83972e+06 649763. 2538.14 3.81 0.88637 0.786788 24068 159480 -1 7244 23 6090 6933 810054 211687 7.95378 7.95378 -494.958 -7.95378 0 0 829453. 3240.05 0.22 0.34 0.14 -1 -1 0.22 0.139388 0.124672 453 369 266 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_16.v common 8.88 vpr 67.79 MiB 0.11 9644 -1 -1 1 0.18 -1 -1 35228 -1 -1 65 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69416 22 19 1418 1046 1 832 111 16 16 256 mult_36 auto 29.5 MiB 1.30 4773 16071 3747 10021 2303 67.8 MiB 0.39 0.01 8.40964 -409.362 -8.40964 8.40964 0.58 0.00292238 0.0026757 0.181568 0.165822 46 9093 31 6.54114e+06 2.89609e+06 723233. 2825.13 3.79 0.816121 0.72172 24832 174915 -1 7344 26 5474 6088 675835 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35032 -1 -1 74 22 0 5 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70372 22 19 1592 1169 1 934 120 16 16 256 mult_36 auto 30.6 MiB 1.48 5562 18410 4023 12076 2311 68.7 MiB 0.50 0.01 9.11545 -462.729 -9.11545 9.11545 0.58 0.00313992 0.00286707 0.219509 0.20039 50 10839 29 6.54114e+06 3.02294e+06 787708. 3076.99 3.65 0.960923 0.851871 25344 186282 -1 8621 24 6644 7427 822442 205516 8.84223 8.84223 -564.118 -8.84223 0 0 943753. 3686.54 0.24 0.34 0.19 -1 -1 0.24 0.155445 0.138298 542 434 323 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_19.v common 9.72 vpr 68.82 MiB 0.11 10560 -1 -1 1 0.27 -1 -1 35344 -1 -1 79 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70468 22 19 1688 1231 1 993 126 16 16 256 mult_36 auto 30.8 MiB 1.32 5905 19656 4339 11653 3664 68.8 MiB 0.49 0.01 9.37523 -468.383 -9.37523 9.37523 0.58 0.00351254 0.00323258 0.232479 0.212033 48 11452 47 6.54114e+06 3.48941e+06 755748. 2952.14 4.24 1.13956 1.0091 25088 180500 -1 8957 23 5555 6342 718459 187069 8.83268 8.83268 -558.947 -8.83268 0 0 916467. 3579.95 0.23 0.33 0.16 -1 -1 0.23 0.163001 0.145746 573 457 342 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_20.v common 10.98 vpr 69.38 MiB 0.09 10784 -1 -1 1 0.23 -1 -1 35528 -1 -1 81 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71044 22 19 1762 1288 1 1031 128 16 16 256 mult_36 auto 31.4 MiB 1.59 6159 20092 4300 10622 5170 69.4 MiB 0.47 0.01 9.0553 -504.795 -9.0553 9.0553 0.58 0.00336194 0.003079 0.223133 0.20372 48 12002 45 6.54114e+06 3.51759e+06 755748. 2952.14 5.14 1.09027 0.964321 25088 180500 -1 9426 26 8013 9013 1087933 263252 8.51952 8.51952 -758.559 -8.51952 0 0 916467. 3579.95 0.27 0.43 0.18 -1 -1 0.27 0.182262 0.162271 601 476 361 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_21.v common 10.02 vpr 69.73 MiB 0.11 10904 -1 -1 1 0.24 -1 -1 35776 -1 -1 85 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71404 22 19 1859 1351 1 1092 132 16 16 256 mult_36 auto 31.6 MiB 1.57 6816 20232 4108 12738 3386 69.7 MiB 0.54 0.01 9.21366 -510.538 -9.21366 9.21366 0.59 0.00370234 0.00339557 0.232676 0.21175 54 12156 29 6.54114e+06 3.57397e+06 829453. 3240.05 4.16 1.10107 0.97694 26108 202796 -1 9502 23 6442 7334 699332 184639 8.23497 8.23497 -611.204 -8.23497 0 0 1.02522e+06 4004.78 0.24 0.34 0.18 -1 -1 0.24 0.17102 0.152253 632 500 380 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_22.v common 11.05 vpr 69.93 MiB 0.14 11016 -1 -1 1 0.26 -1 -1 35912 -1 -1 90 22 0 6 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71604 22 19 1933 1408 1 1130 137 16 16 256 mult_36 auto 31.8 MiB 1.89 6953 18846 3874 11726 3246 69.9 MiB 0.51 0.01 9.25639 -524.337 -9.25639 9.25639 0.60 0.00633064 0.00579152 0.229754 0.209796 54 12678 28 6.54114e+06 3.64444e+06 829453. 3240.05 4.77 1.12815 0.998589 26108 202796 -1 10018 23 7514 8545 880687 221653 8.27422 8.27422 -608.588 -8.27422 0 0 1.02522e+06 4004.78 0.26 0.42 0.19 -1 -1 0.26 0.195465 0.17486 661 519 399 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_23.v common 12.05 vpr 70.30 MiB 0.14 11296 -1 -1 1 0.24 -1 -1 35984 -1 -1 94 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71988 22 19 2031 1472 1 1193 142 18 18 324 mult_36 auto 32.4 MiB 1.88 7735 24562 5200 16532 2830 70.3 MiB 0.65 0.01 9.45758 -535.83 -9.45758 9.45758 0.78 0.00385623 0.00351616 0.276218 0.251396 50 14484 31 8.06603e+06 4.09681e+06 1.03391e+06 3191.07 5.08 1.22106 1.08246 32744 246704 -1 11690 23 7230 8414 1076073 253853 8.46493 8.46493 -695.821 -8.46493 0 0 1.23838e+06 3822.15 0.31 0.47 0.23 -1 -1 0.31 0.198031 0.176796 693 544 418 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_24.v common 15.78 vpr 70.71 MiB 0.17 11480 -1 -1 1 0.22 -1 -1 36208 -1 -1 97 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72404 22 19 2105 1529 1 1230 145 18 18 324 mult_36 auto 32.6 MiB 1.82 7180 26745 5794 17769 3182 70.7 MiB 0.44 0.01 9.12646 -589.17 -9.12646 9.12646 0.72 0.00174114 0.00155803 0.141052 0.12686 46 15589 39 8.06603e+06 4.13909e+06 948677. 2928.01 9.22 1.18426 1.04138 32096 231720 -1 11052 22 7422 8604 958262 236388 8.28608 8.28608 -757.327 -8.28608 0 0 1.16833e+06 3605.96 0.35 0.43 0.17 -1 -1 0.35 0.198698 0.177394 721 563 437 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_25.v common 13.08 vpr 71.23 MiB 0.19 11976 -1 -1 1 0.32 -1 -1 36508 -1 -1 101 22 0 7 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72944 22 19 2201 1591 1 1290 149 18 18 324 mult_36 auto 33.3 MiB 1.80 8299 21425 4201 14721 2503 71.2 MiB 0.63 0.01 9.40561 -605.89 -9.40561 9.40561 0.82 0.0049407 0.00448797 0.265454 0.241336 50 15707 32 8.06603e+06 4.19547e+06 1.03391e+06 3191.07 5.84 1.31782 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fir_nopipe_27.v common 13.18 vpr 72.21 MiB 0.12 12088 -1 -1 1 0.32 -1 -1 36688 -1 -1 111 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73948 22 19 2385 1724 1 1404 160 18 18 324 mult_36 auto 34.4 MiB 1.94 9241 28370 5807 18956 3607 72.2 MiB 0.83 0.01 9.27331 -683.845 -9.27331 9.27331 0.78 0.00442823 0.00404133 0.325043 0.29516 54 17136 39 8.06603e+06 4.73242e+06 1.08842e+06 3359.33 5.64 1.46239 1.29485 33712 268580 -1 13437 24 10877 12354 1477729 344669 8.64193 8.64193 -919.251 -8.64193 0 0 1.34436e+06 4149.26 0.36 0.59 0.22 -1 -1 0.36 0.252438 0.226581 817 642 494 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_28.v common 14.41 vpr 72.31 MiB 0.16 12296 -1 -1 1 0.32 -1 -1 36784 -1 -1 114 22 0 8 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74048 22 19 2459 1781 1 1443 163 18 18 324 mult_36 auto 34.3 MiB 2.32 9764 21523 4098 13503 3922 72.3 MiB 0.62 0.01 9.32934 -687.124 -9.32934 9.32934 0.78 0.00551631 0.00500842 0.259632 0.236424 56 16775 37 8.06603e+06 4.7747e+06 1.11497e+06 3441.27 6.63 1.46602 1.29663 34036 275796 -1 13980 23 9350 10755 1348955 317758 8.77023 8.77023 -898.217 -8.77023 0 0 1.37338e+06 4238.83 0.34 0.53 0.24 -1 -1 0.34 0.233752 0.208772 845 661 513 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_29.v common 16.69 vpr 73.07 MiB 0.19 12476 -1 -1 1 0.36 -1 -1 37116 -1 -1 118 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74828 22 19 2565 1853 1 1511 168 22 22 484 mult_36 auto 35.2 MiB 2.60 9948 31652 6879 21519 3254 73.1 MiB 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0.35 -1 -1 36972 -1 -1 131 22 0 9 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75492 22 19 2818 2038 1 1656 181 22 22 484 mult_36 auto 36.0 MiB 2.74 10985 33396 7014 22006 4376 73.7 MiB 0.94 0.01 9.18872 -729.727 -9.18872 9.18872 1.22 0.00555682 0.00501678 0.391822 0.354063 52 21147 46 1.31202e+07 5.4103e+06 1.63434e+06 3376.74 7.78 1.89748 1.68336 50638 406276 -1 15805 26 12963 14588 1925572 461503 8.66113 8.66113 -888.638 -8.66113 0 0 2.01763e+06 4168.66 0.56 0.76 0.37 -1 -1 0.56 0.298184 0.266224 974 764 589 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_33.v common 18.09 vpr 74.57 MiB 0.18 13792 -1 -1 1 0.37 -1 -1 37332 -1 -1 137 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76356 22 19 2923 2109 1 1725 188 22 22 484 mult_36 auto 36.9 MiB 2.39 11534 41076 8921 25709 6446 74.6 MiB 1.05 0.01 10.2924 -835.387 -10.2924 10.2924 1.27 0.00546535 0.00497593 0.44184 0.40093 54 21231 38 1.31202e+07 5.89087e+06 1.67518e+06 3461.11 8.17 1.90087 1.69027 51122 416746 -1 16854 24 11734 13578 1615248 384384 9.39377 9.39377 -1134.87 -9.39377 0 0 2.06816e+06 4273.05 0.54 0.62 0.34 -1 -1 0.54 0.267121 0.2382 1009 796 608 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_34.v common 21.65 vpr 74.83 MiB 0.21 13772 -1 -1 1 0.38 -1 -1 37876 -1 -1 140 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76624 22 19 2997 2166 1 1764 191 22 22 484 mult_36 auto 37.2 MiB 3.66 12266 39170 8245 26892 4033 74.8 MiB 1.07 0.01 9.97834 -770.817 -9.97834 9.97834 1.21 0.00571216 0.0052044 0.426004 0.386425 56 21922 39 1.31202e+07 5.93316e+06 1.71605e+06 3545.56 10.32 1.86387 1.65418 51606 428054 -1 18215 24 13841 15896 2255928 507616 9.94227 9.94227 -1246.47 -9.94227 0 0 2.11301e+06 4365.72 0.54 0.76 0.35 -1 -1 0.54 0.281343 0.250097 1037 815 627 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_35.v common 19.19 vpr 75.42 MiB 0.15 13984 -1 -1 1 0.39 -1 -1 37592 -1 -1 145 22 0 10 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 77228 22 19 3101 2236 1 1830 196 22 22 484 mult_36 auto 37.6 MiB 3.22 11422 38319 7965 26269 4085 75.4 MiB 1.02 0.01 9.90229 -825.692 -9.90229 9.90229 1.23 0.00568749 0.00517513 0.40807 0.368882 54 21987 30 1.31202e+07 6.00363e+06 1.67518e+06 3461.11 8.36 1.90347 1.6945 51122 416746 -1 17198 23 12943 14962 1754919 421016 9.26291 9.26291 -1135.22 -9.26291 0 0 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78116 22 19 3280 2364 1 1940 204 24 24 576 mult_36 auto 38.6 MiB 3.56 12413 41604 8759 29253 3592 76.3 MiB 1.07 0.02 10.1414 -859.737 -10.1414 10.1414 1.64 0.00602109 0.00548311 0.412304 0.372312 50 25735 44 1.58331e+07 6.49829e+06 1.88759e+06 3277.06 11.57 2.03071 1.79344 58706 454005 -1 18389 25 12459 14636 1793419 425436 9.27766 9.27766 -1319.74 -9.27766 0 0 2.26035e+06 3924.22 0.60 0.75 0.36 -1 -1 0.60 0.334717 0.30042 1135 897 684 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_38.v common 21.64 vpr 76.78 MiB 0.24 14576 -1 -1 1 0.46 -1 -1 37976 -1 -1 157 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78620 22 19 3354 2421 1 1977 209 24 24 576 mult_36 auto 39.0 MiB 4.17 12700 43609 9545 30570 3494 76.8 MiB 1.19 0.02 10.0282 -917.593 -10.0282 10.0282 1.49 0.00602725 0.00545141 0.471712 0.425047 56 21119 26 1.58331e+07 6.56876e+06 2.03561e+06 3534.04 8.64 1.92611 1.70534 61006 507707 -1 18139 27 11695 13188 1690980 410021 9.18442 9.18442 -1340.55 -9.18442 0 0 2.50747e+06 4353.24 0.70 0.76 0.43 -1 -1 0.70 0.348213 0.310179 1164 916 703 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_39.v common 22.11 vpr 77.25 MiB 0.12 14688 -1 -1 1 0.46 -1 -1 38264 -1 -1 161 22 0 11 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79100 22 19 3457 2490 1 2042 213 24 24 576 mult_36 auto 39.5 MiB 3.72 12894 46568 10474 28732 7362 77.2 MiB 1.22 0.02 10.1583 -949.474 -10.1583 10.1583 1.43 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79964 22 19 3708 2673 1 2186 226 24 24 576 mult_36 auto 40.3 MiB 4.74 16104 42194 8322 28032 5840 78.1 MiB 1.14 0.02 10.4136 -1012.01 -10.4136 10.4136 1.46 0.00636253 0.00575312 0.426379 0.385045 62 27815 40 1.58331e+07 7.19026e+06 2.19658e+06 3813.51 14.85 2.26474 2.0088 63306 560109 -1 21638 25 14219 16394 2291368 490734 9.41877 9.41877 -1577.24 -9.41877 0 0 2.72095e+06 4723.87 0.71 0.81 0.46 -1 -1 0.71 0.336207 0.29879 1289 1014 779 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_43.v common 27.74 vpr 78.05 MiB 0.25 15604 -1 -1 1 0.65 -1 -1 38608 -1 -1 178 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79920 22 19 3810 2741 1 2253 231 24 24 576 mult_36 auto 40.4 MiB 4.30 15296 41295 8139 29365 3791 78.0 MiB 1.20 0.02 10.16 -1063.97 -10.16 10.16 1.54 0.0070497 0.00641468 0.455071 0.409328 56 28472 50 1.58331e+07 7.26073e+06 2.03561e+06 3534.04 13.96 2.40374 2.12442 61006 507707 -1 22090 23 15206 17473 2444394 558097 9.42572 9.42572 -1494.13 -9.42572 0 0 2.50747e+06 4353.24 0.67 0.80 0.47 -1 -1 0.67 0.286418 0.257228 1323 1043 798 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_44.v common 24.56 vpr 78.46 MiB 0.26 15644 -1 -1 1 0.65 -1 -1 38452 -1 -1 181 22 0 12 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80348 22 19 3884 2798 1 2294 234 24 24 576 mult_36 auto 40.8 MiB 4.95 15489 47034 9365 34232 3437 78.5 MiB 1.31 0.02 10.121 -975.462 -10.121 10.121 1.62 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success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81580 22 19 4167 2996 1 2465 248 24 24 576 mult_36 auto 42.2 MiB 4.83 16473 59376 11937 40248 7191 79.7 MiB 1.55 0.02 10.4408 -1061.77 -10.4408 10.4408 1.55 0.00789307 0.00718347 0.613169 0.553732 60 26903 48 1.58331e+07 7.88224e+06 2.13333e+06 3703.69 11.83 2.78199 2.45451 62730 548095 -1 21754 23 12304 14126 1550289 380177 9.28402 9.28402 -1464.85 -9.28402 0 0 2.67122e+06 4637.53 0.76 0.75 0.47 -1 -1 0.76 0.374453 0.33403 1449 1144 874 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_48.v common 23.87 vpr 79.73 MiB 0.23 16660 -1 -1 1 0.66 -1 -1 40516 -1 -1 197 22 0 13 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81648 22 19 4241 3053 1 2504 251 24 24 576 mult_36 auto 42.1 MiB 5.61 16474 57994 11394 40219 6381 79.7 MiB 1.47 0.02 10.5013 -1047.39 -10.5013 10.5013 1.43 0.00738982 0.00668981 0.570981 0.514404 64 25175 29 1.58331e+07 7.92452e+06 2.26035e+06 3924.22 8.19 2.34248 2.06535 64454 586630 -1 22200 23 12490 14529 1711643 410861 9.39387 9.39387 -1359.3 -9.39387 0 0 2.84938e+06 4946.85 0.85 0.79 0.56 -1 -1 0.85 0.382435 0.340426 1477 1163 893 19 0 0 -k6_frac_uripple_N8_22nm.xml fir_nopipe_49.v common 27.24 vpr 80.15 MiB 0.31 17092 -1 -1 1 0.64 -1 -1 40920 -1 -1 204 22 0 14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82076 22 19 4346 3124 1 2572 259 24 24 576 mult_36 auto 42.5 MiB 5.24 17944 60484 12294 40037 8153 80.2 MiB 1.62 0.02 10.2711 -1057.18 -10.2711 10.2711 1.51 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14 success v8.0.0-10981-ge72dccf2d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T17:16:23 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 83244 22 19 4598 3308 1 2717 270 24 24 576 mult_36 auto 43.9 MiB 6.37 18189 61310 12677 40484 8149 81.3 MiB 1.72 0.03 10.1072 -1112.57 -10.1072 10.1072 1.50 0.0101785 0.00922809 0.672075 0.603798 58 33606 48 1.58331e+07 8.57421e+06 2.08734e+06 3623.85 22.48 2.99387 2.64132 62154 534210 -1 25197 24 15147 17510 2264940 516528 9.45177 9.45177 -1662.09 -9.45177 0 0 2.61600e+06 4541.67 0.75 0.98 0.38 -1 -1 0.75 0.434057 0.386885 1605 1264 969 19 0 0 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler 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min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_2ripple_N8_22nm.xml fir_pipe_14.v common 16.72 vpr 72.14 MiB 0.07 10524 -1 -1 1 0.22 -1 -1 35652 -1 -1 84 22 0 4 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73868 22 19 1974 1653 1 1008 129 16 16 256 mult_36 auto 32.4 MiB 1.05 5469 18004 3993 12227 1784 72.1 MiB 0.40 0.01 4.14666 -1156.94 -4.14666 4.14666 0.24 0.00342963 0.00309238 0.20424 0.184059 -1 -1 -1 -1 56 11505 39 6.59459e+06 2.79996e+06 849745. 3319.32 12.41 2.02021 1.75562 26364 208198 -1 8946 18 3982 4651 528508 140814 4.27196 4.27196 -1272.08 -4.27196 0 0 1.04740e+06 4091.43 0.04 0.25 0.16 -1 -1 0.04 0.141457 0.12562 484 708 247 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_15.v common 19.14 vpr 72.98 MiB 0.12 11000 -1 -1 1 0.23 -1 -1 36912 -1 -1 91 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74728 22 19 2144 1789 1 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78104 22 19 2778 2321 1 1389 163 16 16 256 mult_36 auto 36.0 MiB 1.36 8349 28643 6138 19307 3198 76.3 MiB 0.67 0.01 4.32767 -1701.92 -4.32767 4.32767 0.29 0.00489133 0.00440702 0.328294 0.294928 -1 -1 -1 -1 64 15175 30 6.59459e+06 4.05519e+06 943753. 3686.54 22.89 2.88759 2.49841 27892 240595 -1 11744 16 4803 5611 621335 143640 4.27196 4.27196 -1714.96 -4.27196 0 0 1.19033e+06 4649.74 0.04 0.31 0.20 -1 -1 0.04 0.186567 0.166709 682 1002 342 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_20.v common 11.70 vpr 76.78 MiB 0.13 12496 -1 -1 1 0.31 -1 -1 37004 -1 -1 120 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78624 22 19 2852 2378 1 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81316 22 19 3375 2799 1 1720 192 18 18 324 mult_36 auto 38.5 MiB 1.64 9997 35031 7324 24280 3427 79.4 MiB 0.78 0.01 4.2263 -2010.98 -4.2263 4.2263 0.37 0.00551458 0.00492416 0.367684 0.328149 -1 -1 -1 -1 60 17113 25 8.13932e+06 4.8565e+06 1.16833e+06 3605.96 13.83 3.1404 2.72282 35004 297736 -1 14817 17 6221 7512 731941 182840 4.27196 4.27196 -2101.85 -4.27196 0 0 1.46313e+06 4515.82 0.06 0.40 0.24 -1 -1 0.06 0.241793 0.217237 826 1198 437 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_25.v common 24.17 vpr 80.90 MiB 0.18 14024 -1 -1 1 0.41 -1 -1 38176 -1 -1 150 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82840 22 19 3615 3005 1 1813 198 18 18 324 mult_36 auto 39.9 MiB 1.74 10048 37638 8260 25340 4038 80.9 MiB 0.85 0.01 4.14666 -2190.25 -4.14666 4.14666 0.37 0.00573555 0.00511089 0.403337 0.358296 -1 -1 -1 -1 66 17382 33 8.13932e+06 4.94335e+06 1.27759e+06 3943.17 17.16 3.41995 2.95671 36296 327148 -1 14915 14 5955 7259 740555 175354 4.27196 4.27196 -2315.28 -4.27196 0 0 1.59950e+06 4936.74 0.06 0.36 0.26 -1 -1 0.06 0.218664 0.195875 891 1293 456 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_26.v common 12.13 vpr 81.18 MiB 0.18 14036 -1 -1 1 0.42 -1 -1 38344 -1 -1 155 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83124 22 19 3689 3062 1 1866 203 18 18 324 mult_36 auto 40.2 MiB 1.83 11664 39539 8297 27644 3598 81.2 MiB 0.94 0.01 4.32822 -2193.84 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86016 22 19 4233 3504 1 2174 229 22 22 484 mult_36 auto 42.6 MiB 2.19 12823 49929 11428 34943 3558 84.0 MiB 1.10 0.02 4.27196 -2525.34 -4.27196 4.27196 0.58 0.0065951 0.00586339 0.503897 0.447818 -1 -1 -1 -1 62 22961 40 1.32347e+07 6.15512e+06 1.85176e+06 3825.95 31.78 3.98361 3.44449 53538 472186 -1 18850 14 7518 9345 917099 214842 4.39726 4.39726 -2598.37 -4.39726 0 0 2.29262e+06 4736.82 0.11 0.45 0.41 -1 -1 0.11 0.262052 0.234969 1041 1510 551 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_pipe_31.v common 41.01 vpr 85.09 MiB 0.21 15580 -1 -1 1 0.52 -1 -1 40960 -1 -1 186 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 87128 22 19 4410 3647 1 2271 236 22 22 484 mult_36 auto 43.6 MiB 2.20 14018 52724 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71228 22 19 1518 1112 1 874 114 16 16 256 mult_36 auto 30.3 MiB 1.44 5245 24402 6450 15009 2943 69.6 MiB 0.54 0.01 8.71055 -438.026 -8.71055 8.71055 0.29 0.00292705 0.00267783 0.270838 0.247842 -1 -1 -1 -1 54 10377 43 6.59459e+06 2.96435e+06 829453. 3240.05 4.94 1.17091 1.04076 26108 202796 -1 8188 26 8292 9448 963929 243570 9.34558 9.34558 -558.37 -9.34558 0 0 1.02522e+06 4004.78 0.04 0.34 0.16 -1 -1 0.04 0.156995 0.139831 366 415 304 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_18.v common 8.03 vpr 69.85 MiB 0.12 10260 -1 -1 1 0.19 -1 -1 34968 -1 -1 71 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71524 22 19 1592 1169 1 911 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3.46168e+06 916467. 3579.95 6.63 1.71576 1.51305 27384 229598 -1 8531 27 8100 9147 1007274 238049 8.54388 8.54388 -576.436 -8.54388 0 0 1.13630e+06 4438.68 0.04 0.36 0.18 -1 -1 0.04 0.178144 0.15859 407 457 342 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_20.v common 19.24 vpr 70.88 MiB 0.13 10668 -1 -1 1 0.21 -1 -1 35540 -1 -1 77 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72576 22 19 1762 1288 1 1008 124 16 16 256 mult_36 auto 31.2 MiB 1.58 5696 19900 4820 12143 2937 70.9 MiB 0.47 0.01 8.72494 -497.85 -8.72494 8.72494 0.29 0.00333636 0.00304322 0.232955 0.21242 -1 -1 -1 -1 62 10220 48 6.59459e+06 3.49063e+06 916467. 3579.95 14.15 1.93836 1.69903 27384 229598 -1 8514 24 7371 8214 846629 211248 8.69588 8.69588 -542.413 -8.69588 0 0 1.13630e+06 4438.68 0.04 0.34 0.19 -1 -1 0.04 0.173473 0.154762 425 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73132 22 19 1933 1408 1 1105 131 16 16 256 mult_36 auto 31.8 MiB 1.69 6613 19387 4426 12555 2406 71.4 MiB 0.49 0.01 8.68371 -576.607 -8.68371 8.68371 0.29 0.00361745 0.00330276 0.231014 0.210384 -1 -1 -1 -1 64 11510 32 6.59459e+06 3.59196e+06 943753. 3686.54 3.57 1.09921 0.971727 27892 240595 -1 9867 25 8936 10054 1161617 270205 8.73628 8.73628 -648.894 -8.73628 0 0 1.19033e+06 4649.74 0.04 0.42 0.20 -1 -1 0.04 0.194085 0.17289 467 519 399 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_23.v common 10.20 vpr 72.12 MiB 0.15 11536 -1 -1 1 0.25 -1 -1 36192 -1 -1 89 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73852 22 19 2031 1472 1 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8.13932e+06 4.10377e+06 1.16833e+06 3605.96 4.12 1.13211 0.999115 35004 297736 -1 10624 23 8524 9667 1084700 263305 8.64568 8.64568 -770.611 -8.64568 0 0 1.46313e+06 4515.82 0.06 0.39 0.24 -1 -1 0.06 0.190269 0.169691 508 563 437 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_25.v common 13.99 vpr 73.21 MiB 0.12 11768 -1 -1 1 0.22 -1 -1 36520 -1 -1 95 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74964 22 19 2201 1591 1 1260 143 18 18 324 mult_36 auto 33.2 MiB 1.76 8194 27745 7100 17403 3242 73.2 MiB 0.69 0.01 8.73499 -572.467 -8.73499 8.73499 0.38 0.0042082 0.00384116 0.33006 0.299895 -1 -1 -1 -1 66 14299 30 8.13932e+06 4.1472e+06 1.27759e+06 3943.17 7.86 1.99307 1.75537 36296 327148 -1 12283 23 11448 12868 1680012 391916 9.04958 9.04958 -692.805 -9.04958 0 0 1.59950e+06 4936.74 0.06 0.52 0.26 -1 -1 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75884 22 19 2385 1724 1 1372 153 18 18 324 mult_36 auto 34.2 MiB 2.02 8777 30419 7799 19239 3381 74.1 MiB 0.75 0.01 8.86475 -625.413 -8.86475 8.86475 0.37 0.00429284 0.00389463 0.34172 0.309996 -1 -1 -1 -1 76 13707 24 8.13932e+06 4.67347e+06 1.43297e+06 4422.75 7.73 2.18313 1.92481 38232 369828 -1 12614 23 9422 10787 1205229 288478 8.68188 8.68188 -858.473 -8.68188 0 0 1.77541e+06 5479.65 0.07 0.45 0.30 -1 -1 0.07 0.220245 0.196444 577 642 494 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_28.v common 12.54 vpr 74.55 MiB 0.17 12360 -1 -1 1 0.31 -1 -1 36800 -1 -1 108 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 76336 22 19 2459 1781 1 1407 157 18 18 324 mult_36 auto 34.7 MiB 2.09 8925 30190 7619 18347 4224 74.5 MiB 0.72 0.01 8.65855 -666.267 -8.65855 8.65855 0.37 0.00438766 0.0039739 0.340069 0.308012 -1 -1 -1 -1 66 15195 32 8.13932e+06 4.73137e+06 1.27759e+06 3943.17 5.83 1.66023 1.46255 36296 327148 -1 13273 22 10080 11530 1391089 314694 9.17008 9.17008 -831.006 -9.17008 0 0 1.59950e+06 4936.74 0.06 0.47 0.26 -1 -1 0.06 0.217458 0.194342 597 661 513 19 0 0 + k6_frac_2ripple_N8_22nm.xml fir_nopipe_29.v common 14.48 vpr 75.21 MiB 0.17 12648 -1 -1 1 0.32 -1 -1 37264 -1 -1 113 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77016 22 19 2565 1853 1 1476 163 22 22 484 mult_36 auto 35.3 MiB 2.43 8788 31313 8132 20016 3165 75.2 MiB 0.75 0.01 8.77133 -653.597 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74616 22 19 2144 1789 1 1096 137 16 16 256 mult_36 auto 32.8 MiB 0.83 6252 23082 5311 14826 2945 72.9 MiB 0.51 0.01 4.27196 -1278.5 -4.27196 4.27196 0.29 0.00368719 0.00331551 0.260562 0.234651 -1 -1 -1 -1 56 12471 39 6.62819e+06 3.31913e+06 849745. 3319.32 4.71 1.38491 1.20834 26364 208198 -1 9905 17 4015 4904 579812 151105 4.39726 4.39726 -1386.98 -4.39726 0 0 1.04740e+06 4091.43 0.04 0.27 0.17 -1 -1 0.04 0.152253 0.13572 530 769 266 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_pipe_16.v common 6.62 vpr 73.04 MiB 0.12 11024 -1 -1 1 0.25 -1 -1 36876 -1 -1 95 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74796 22 19 2218 1846 1 1145 141 16 16 256 mult_36 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78140 22 19 2852 2378 1 1431 167 16 16 256 mult_36 auto 36.0 MiB 1.08 9109 29543 6251 19805 3487 76.3 MiB 0.71 0.01 4.33405 -1719.45 -4.33405 4.33405 0.31 0.00480446 0.00430083 0.339688 0.304336 -1 -1 -1 -1 72 15149 30 6.62819e+06 4.14189e+06 1.04740e+06 4091.43 7.24 2.26964 1.97187 29168 268476 -1 12761 14 4845 5724 641063 148686 4.39726 4.39726 -1772.51 -4.39726 0 0 1.31294e+06 5128.69 0.05 0.29 0.22 -1 -1 0.05 0.172114 0.154045 698 1021 361 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_pipe_21.v common 15.79 vpr 77.49 MiB 0.16 12836 -1 -1 1 0.34 -1 -1 37928 -1 -1 127 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79352 22 19 3057 2549 1 1525 174 16 16 256 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82504 22 19 3615 3005 1 1807 198 18 18 324 mult_36 auto 39.4 MiB 1.38 10242 38214 8215 26103 3896 80.6 MiB 0.86 0.01 4.22665 -2157.26 -4.22665 4.22665 0.42 0.00581616 0.00517666 0.409019 0.363853 -1 -1 -1 -1 62 18218 46 8.18539e+06 4.97935e+06 1.20291e+06 3712.69 15.15 3.33537 2.87876 35328 304176 -1 14927 16 6073 7295 716490 176824 4.27196 4.27196 -2232.43 -4.27196 0 0 1.49010e+06 4599.06 0.06 0.36 0.24 -1 -1 0.06 0.22827 0.202908 891 1293 456 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_pipe_26.v common 17.26 vpr 80.83 MiB 0.18 14164 -1 -1 1 0.42 -1 -1 38460 -1 -1 155 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82772 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k6_frac_2uripple_N8_22nm.xml fir_nopipe_17.v common 22.16 vpr 69.66 MiB 0.12 10296 -1 -1 1 0.19 -1 -1 35392 -1 -1 68 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71332 22 19 1518 1112 1 874 114 16 16 256 mult_36 auto 30.3 MiB 0.63 5196 19710 5445 11819 2446 69.7 MiB 0.47 0.01 8.45239 -453.637 -8.45239 8.45239 0.29 0.00302513 0.00277978 0.229393 0.209995 -1 -1 -1 -1 52 11585 50 6.62819e+06 2.98067e+06 808720. 3159.06 18.20 1.69619 1.49381 25852 197779 -1 8467 26 7939 9134 1049694 260543 9.07812 9.07812 -543.726 -9.07812 0 0 1.00038e+06 3907.74 0.04 0.35 0.16 -1 -1 0.04 0.155655 0.138475 366 415 304 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_nopipe_18.v common 6.76 vpr 69.75 MiB 0.12 10348 -1 -1 1 0.19 -1 -1 34968 -1 -1 71 22 0 5 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 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on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73576 22 19 2031 1472 1 1164 137 18 18 324 mult_36 auto 32.2 MiB 0.79 6746 28730 7542 17338 3850 71.9 MiB 0.68 0.01 8.54591 -533.672 -8.54591 8.54591 0.38 0.0037745 0.00344253 0.325506 0.296594 -1 -1 -1 -1 56 12955 47 8.18539e+06 4.0817e+06 1.11497e+06 3441.27 4.18 1.39605 1.23432 34036 275796 -1 10923 24 9524 10733 1204326 316235 9.44578 9.44578 -667.58 -9.44578 0 0 1.37338e+06 4238.83 0.05 0.44 0.22 -1 -1 0.05 0.197167 0.175668 489 544 418 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_nopipe_24.v common 10.17 vpr 72.61 MiB 0.15 11564 -1 -1 1 0.26 -1 -1 36176 -1 -1 92 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74348 22 19 2105 1529 1 1203 140 18 18 324 mult_36 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475 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_nopipe_27.v common 22.51 vpr 73.62 MiB 0.18 12268 -1 -1 1 0.30 -1 -1 36652 -1 -1 104 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75384 22 19 2385 1724 1 1370 153 18 18 324 mult_36 auto 33.7 MiB 0.88 8092 32055 7887 20603 3565 73.6 MiB 0.73 0.01 8.64809 -651.306 -8.64809 8.64809 0.38 0.00428401 0.00390161 0.353171 0.320778 -1 -1 -1 -1 58 14837 29 8.18539e+06 4.69843e+06 1.14310e+06 3528.09 17.13 2.39591 2.1037 34680 290288 -1 12470 25 10099 11558 1309249 328905 9.16302 9.16302 -843.909 -9.16302 0 0 1.43297e+06 4422.75 0.06 0.49 0.23 -1 -1 0.06 0.233777 0.208169 577 642 494 19 0 0 + k6_frac_2uripple_N8_22nm.xml fir_nopipe_28.v common 14.78 vpr 74.25 MiB 0.17 12316 -1 -1 1 0.32 -1 -1 36856 -1 -1 108 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84256 22 19 4233 3504 1 2196 265 22 22 484 mult_36 auto 40.6 MiB 1.57 14001 52965 10141 38785 4039 82.3 MiB 1.21 0.02 4.18656 -2766.6 -4.18656 4.18656 0.59 0.00689166 0.00615924 0.46357 0.411804 -1 -1 -1 -1 52 25400 33 1.30842e+07 6.5684e+06 1.63434e+06 3376.74 18.23 3.12246 2.69814 50638 406276 -1 20255 18 7377 9042 871750 226668 4.54456 4.54456 -2785.97 -4.54456 0 0 2.01763e+06 4168.66 0.08 0.47 0.31 -1 -1 0.08 0.281012 0.247997 1312 1510 551 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_pipe_31.v common 15.10 vpr 83.01 MiB 0.21 15516 -1 -1 1 0.53 -1 -1 40880 -1 -1 223 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85004 22 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88736 22 19 5093 4228 1 2600 306 22 22 484 mult_36 auto 44.4 MiB 1.76 17113 70346 15205 49642 5499 86.7 MiB 1.64 0.02 4.39726 -3301.07 -4.39726 4.39726 0.61 0.00818413 0.00730255 0.619958 0.550445 -1 -1 -1 -1 58 27385 20 1.30842e+07 7.52337e+06 1.75961e+06 3635.55 5.81 2.71154 2.35254 52570 450426 -1 23967 17 8704 10692 1062475 277561 4.41926 4.41926 -3287.64 -4.41926 0 0 2.20457e+06 4554.90 0.09 0.54 0.35 -1 -1 0.09 0.321183 0.283601 1579 1842 646 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_pipe_36.v common 31.41 vpr 86.95 MiB 0.25 17312 -1 -1 1 0.65 -1 -1 41708 -1 -1 261 22 0 10 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 89032 22 19 5167 4285 1 2654 312 22 22 484 mult_36 auto 44.6 MiB 1.80 17908 66903 12538 49558 4807 86.9 MiB 1.61 0.03 4.32323 -3308.18 -4.32323 4.32323 0.60 0.00860958 0.00769352 0.588541 0.520875 -1 -1 -1 -1 56 31375 42 1.30842e+07 7.60721e+06 1.71605e+06 3545.56 21.96 4.30623 3.71055 51606 428054 -1 25747 16 9282 11133 1163492 307557 4.54456 4.54456 -3414.57 -4.54456 0 0 2.11301e+06 4365.72 0.09 0.57 0.33 -1 -1 0.09 0.322486 0.286254 1601 1861 665 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_pipe_37.v common 30.76 vpr 88.01 MiB 0.26 17764 -1 -1 1 0.67 -1 -1 40792 -1 -1 270 22 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 90120 22 19 5380 4464 1 2753 322 24 24 576 mult_36 auto 45.4 MiB 1.83 17930 72017 15146 51896 4975 88.0 MiB 1.67 0.02 4.39726 -3485.12 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/home/elgamma8/research/release/vtr-verilog-to-routing 73044 22 19 2031 1472 1 1189 159 18 18 324 mult_36 auto 31.5 MiB 4.48 7061 27679 5917 18965 2797 71.3 MiB 0.68 0.01 9.36191 -582.736 -9.36191 9.36191 0.38 0.00371606 0.00338429 0.254265 0.231417 -1 -1 -1 -1 48 12912 27 8.04299e+06 4.32309e+06 991730. 3060.90 2.90 0.953397 0.843166 32420 239176 -1 10546 23 7436 8617 945615 250974 8.93758 8.93758 -717.803 -8.93758 0 0 1.20291e+06 3712.69 0.05 0.36 0.19 -1 -1 0.05 0.176264 0.156554 700 544 418 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_nopipe_24.v common 13.09 vpr 71.78 MiB 0.07 11528 -1 -1 1 0.25 -1 -1 36188 -1 -1 115 22 0 7 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73504 22 19 2105 1529 1 1226 163 18 18 324 mult_36 auto 32.0 MiB 4.85 7614 27308 5726 18896 2686 71.8 MiB 0.74 0.01 9.27241 -589.706 -9.27241 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75116 22 19 2459 1781 1 1435 184 18 18 324 mult_36 auto 33.6 MiB 5.87 9664 34179 7288 22627 4264 73.4 MiB 0.90 0.01 9.47211 -709.303 -9.47211 9.47211 0.37 0.00453022 0.0040763 0.308968 0.280239 -1 -1 -1 -1 52 17978 43 8.04299e+06 5.05447e+06 1.06151e+06 3276.26 5.52 1.52642 1.34525 33388 261900 -1 13899 25 10339 11870 1318603 341192 8.71498 8.71498 -893.429 -8.71498 0 0 1.31159e+06 4048.11 0.05 0.49 0.20 -1 -1 0.05 0.228226 0.20229 856 661 513 19 0 0 + k6_frac_ripple_N8_22nm.xml fir_nopipe_29.v common 19.43 vpr 73.88 MiB 0.17 12676 -1 -1 1 0.32 -1 -1 37268 -1 -1 142 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75656 22 19 2565 1853 1 1504 192 22 22 484 mult_36 auto 33.9 MiB 5.89 9917 38902 8764 24624 5514 73.9 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/home/elgamma8/research/release/vtr-verilog-to-routing 77708 22 19 3057 2549 1 1549 198 17 17 289 clb auto 35.4 MiB 1.03 9250 34182 6503 23460 4219 75.9 MiB 0.75 0.01 4.16866 -1902.33 -4.16866 4.16866 0.33 0.00498017 0.00445532 0.314048 0.279386 -1 -1 -1 -1 52 16499 45 6.89349e+06 4.50416e+06 926341. 3205.33 8.02 2.62694 2.26391 29218 227130 -1 13459 15 4935 6172 588490 160646 4.54456 4.54456 -1954.17 -4.54456 0 0 1.14541e+06 3963.36 0.04 0.30 0.18 -1 -1 0.04 0.181183 0.160647 939 1099 380 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_pipe_22.v common 16.80 vpr 76.08 MiB 0.16 12964 -1 -1 1 0.34 -1 -1 37912 -1 -1 157 22 0 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77908 22 19 3131 2606 1 1600 204 17 17 289 clb auto 35.7 MiB 1.03 10391 36204 6804 25063 4337 76.1 MiB 0.83 0.01 4.29396 -2010.61 -4.29396 4.29396 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81024 22 19 3689 3062 1 1888 233 18 18 324 clb mult_36 auto 37.8 MiB 1.20 12084 41761 7839 29331 4591 79.1 MiB 0.99 0.02 4.41926 -2391.24 -4.41926 4.41926 0.38 0.00615276 0.00550654 0.38751 0.346378 -1 -1 -1 -1 56 19374 25 8.06603e+06 5.37936e+06 1.11497e+06 3441.27 4.53 2.02335 1.75425 34036 275796 -1 16924 17 6149 7462 703147 193689 4.54456 4.54456 -2408.11 -4.54456 0 0 1.37338e+06 4238.83 0.05 0.46 0.26 -1 -1 0.05 0.27169 0.242225 1136 1312 475 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_pipe_27.v common 23.80 vpr 79.91 MiB 0.19 14560 -1 -1 1 0.45 -1 -1 38468 -1 -1 194 22 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81828 22 19 3871 3210 1 1992 243 19 19 361 clb auto 38.6 MiB 1.26 11315 46481 8979 32879 4623 79.9 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Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84424 22 19 4410 3647 1 2297 273 22 22 484 mult_36 auto 40.7 MiB 1.53 15086 56028 10921 40849 4258 82.4 MiB 1.31 0.02 4.39726 -2835.95 -4.39726 4.39726 0.58 0.00723747 0.00646969 0.487651 0.433891 -1 -1 -1 -1 54 28995 49 1.31202e+07 6.70695e+06 1.67518e+06 3461.11 21.06 3.52671 3.04296 51122 416746 -1 21612 13 7756 9275 951243 242088 4.66986 4.66986 -2900.03 -4.66986 0 0 2.06816e+06 4273.05 0.08 0.44 0.32 -1 -1 0.08 0.236748 0.210606 1370 1578 570 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_pipe_32.v common 13.50 vpr 82.77 MiB 0.22 15816 -1 -1 1 0.53 -1 -1 40564 -1 -1 229 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84760 22 19 4484 3704 1 2346 279 22 22 484 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75056 22 19 2565 1853 1 1504 192 22 22 484 mult_36 auto 33.4 MiB 2.66 9980 38902 8510 27060 3332 73.3 MiB 0.94 0.01 9.55956 -734.936 -9.55956 9.55956 0.58 0.00467819 0.00424899 0.341342 0.309318 -1 -1 -1 -1 46 19528 31 1.31202e+07 5.56534e+06 1.45945e+06 3015.39 29.18 2.55349 2.24323 48706 359646 -1 14955 23 9799 11721 1367754 344286 8.92648 8.92648 -1046.74 -8.92648 0 0 1.79840e+06 3715.71 0.08 0.53 0.32 -1 -1 0.08 0.233165 0.207613 891 694 532 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_nopipe_30.v common 40.51 vpr 73.54 MiB 0.18 12696 -1 -1 1 0.26 -1 -1 37316 -1 -1 145 22 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75304 22 19 2639 1910 1 1540 195 22 22 484 mult_36 auto 33.7 MiB 2.84 9425 47655 11240 31065 5350 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4524 3251 1 2671 308 24 24 576 mult_36 auto 41.0 MiB 5.18 18561 77194 16474 53362 7358 82.8 MiB 2.10 0.03 10.2353 -1249.02 -10.2353 10.2353 0.71 0.00813623 0.00736483 0.636713 0.568738 -1 -1 -1 -1 56 31415 47 1.58331e+07 9.10978e+06 2.03561e+06 3534.04 40.83 4.73954 4.14534 61006 507707 -1 25944 24 15278 18150 2062037 537506 9.39491 9.39491 -1834.69 -9.39491 0 0 2.50747e+06 4353.24 0.11 0.90 0.39 -1 -1 0.11 0.419484 0.372632 1594 1245 950 19 0 0 + k6_frac_uripple_N8_22nm.xml fir_nopipe_52.v common 26.53 vpr 89.48 MiB 0.32 17472 -1 -1 1 0.69 -1 -1 39304 -1 -1 258 22 0 14 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91628 22 19 4598 3308 1 2708 313 24 24 576 mult_36 auto 41.2 MiB 5.63 17989 78901 17073 53371 8457 82.8 MiB 2.11 0.03 10.0544 -1205.38 -10.0544 10.0544 0.69 0.00923478 0.00812452 0.667561 0.594533 -1 -1 -1 -1 60 26627 33 1.58331e+07 9.18025e+06 2.13333e+06 3703.69 12.39 3.91661 3.44487 62730 548095 -1 24090 24 13892 16967 1757096 435601 9.21877 9.21877 -1665.44 -9.21877 0 0 2.67122e+06 4637.53 0.12 0.81 0.43 -1 -1 0.12 0.419028 0.37223 1624 1264 969 19 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt index 7754909e7b4..23d74d84fd3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt @@ -1,201 +1,201 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.50 vpr 61.01 MiB 0.01 5816 -1 -1 2 0.05 -1 -1 31892 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62472 11 6 34 40 1 24 19 17 17 289 -1 unnamed_device 22.4 MiB 0.01 72 444 121 288 35 61.0 MiB 0.01 0.00 0.900447 -12.0151 -0.900447 0.900447 0.95 0.000147916 0.000134485 0.00301238 0.00273498 22 213 10 6.55708e+06 24110 420624. 1455.45 0.64 0.0194369 0.0168614 20158 92377 -1 158 12 95 98 5293 1758 0.83871 0.83871 -12.913 -0.83871 0 0 500653. 1732.36 0.17 0.01 0.13 -1 -1 0.17 0.0048254 0.00430326 16 7 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.60 vpr 61.00 MiB 0.02 6064 -1 -1 3 0.06 -1 -1 31956 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62468 13 7 41 48 1 32 23 17 17 289 -1 unnamed_device 22.4 MiB 0.01 91 855 163 648 44 61.0 MiB 0.01 0.00 1.58811 -16.2873 -1.58811 1.58811 0.95 0.000177402 0.000162269 0.00519947 0.00475699 24 295 11 6.55708e+06 36165 448715. 1552.65 0.71 0.0249257 0.0217293 20734 103517 -1 254 10 116 129 6964 2198 1.50711 1.50711 -17.293 -1.50711 0 0 554710. 1919.41 0.18 0.01 0.15 -1 -1 0.18 0.00501074 0.00449096 19 9 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.69 vpr 60.88 MiB 0.01 5880 -1 -1 3 0.06 -1 -1 32376 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62336 15 8 47 55 1 38 26 17 17 289 -1 unnamed_device 22.2 MiB 0.01 99 1014 271 604 139 60.9 MiB 0.01 0.00 1.23151 -17.4525 -1.23151 1.23151 0.96 0.000203904 0.000186784 0.0059962 0.00548251 26 398 20 6.55708e+06 36165 477104. 1650.88 0.77 0.0318265 0.027733 21022 109990 -1 272 8 150 171 7737 2724 1.14085 1.14085 -18.4888 -1.14085 0 0 585099. 2024.56 0.19 0.01 0.16 -1 -1 0.19 0.00489735 0.00439557 23 10 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 4.85 vpr 61.05 MiB 0.01 5884 -1 -1 3 0.07 -1 -1 32092 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62512 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 22.2 MiB 0.06 120 628 136 477 15 61.0 MiB 0.01 0.00 1.70831 -21.0872 -1.70831 1.70831 0.96 0.000251482 0.000230868 0.00407859 0.00374317 28 337 17 6.55708e+06 48220 500653. 1732.36 1.89 0.0668127 0.057696 21310 115450 -1 293 12 147 164 8042 2499 1.58811 1.58811 -21.8318 -1.58811 0 0 612192. 2118.31 0.21 0.02 0.16 -1 -1 0.21 0.00738294 0.00656787 25 14 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.70 vpr 61.07 MiB 0.02 5956 -1 -1 4 0.06 -1 -1 31980 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62532 19 10 60 70 1 48 33 17 17 289 -1 unnamed_device 22.3 MiB 0.02 142 1229 224 959 46 61.1 MiB 0.02 0.00 1.58811 -24.8435 -1.58811 1.58811 0.95 0.000261776 0.000240893 0.00688308 0.00632377 26 425 11 6.55708e+06 48220 477104. 1650.88 0.77 0.0357697 0.0312968 21022 109990 -1 380 16 211 268 12350 3922 1.59011 1.59011 -25.4098 -1.59011 0 0 585099. 2024.56 0.19 0.02 0.16 -1 -1 0.19 0.00945114 0.00833258 29 13 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 5.45 vpr 61.21 MiB 0.03 5844 -1 -1 4 0.06 -1 -1 31764 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62676 21 11 69 80 1 54 37 17 17 289 -1 unnamed_device 22.7 MiB 0.05 255 1379 224 1089 66 61.2 MiB 0.02 0.00 1.74751 -29.3828 -1.74751 1.74751 0.98 0.000301732 0.000278383 0.00759182 0.0070033 26 631 16 6.55708e+06 60275 477104. 1650.88 2.35 0.0681668 0.0593772 21022 109990 -1 573 15 226 325 21349 5594 1.59211 1.59211 -31.6197 -1.59211 0 0 585099. 2024.56 0.19 0.02 0.16 -1 -1 0.19 0.0101978 0.00903499 33 17 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.82 vpr 60.99 MiB 0.01 5896 -1 -1 5 0.04 -1 -1 32356 -1 -1 5 23 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62452 23 12 73 85 1 58 40 17 17 289 -1 unnamed_device 22.3 MiB 0.02 278 3032 1045 1570 417 61.0 MiB 0.03 0.00 2.03736 -35.0243 -2.03736 2.03736 0.99 0.000313724 0.000288155 0.0147363 0.0135526 26 630 14 6.55708e+06 60275 477104. 1650.88 0.80 0.05062 0.044825 21022 109990 -1 591 12 246 332 19803 5342 2.03736 2.03736 -37.4544 -2.03736 0 0 585099. 2024.56 0.20 0.02 0.16 -1 -1 0.20 0.00906154 0.00809068 35 16 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.90 vpr 61.21 MiB 0.01 6096 -1 -1 5 0.06 -1 -1 31996 -1 -1 6 25 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62684 25 13 82 95 1 66 44 17 17 289 -1 unnamed_device 22.5 MiB 0.02 261 1738 345 1379 14 61.2 MiB 0.02 0.00 2.11777 -37.2459 -2.11777 2.11777 0.96 0.000351899 0.000323529 0.00882293 0.00811274 28 700 13 6.55708e+06 72330 500653. 1732.36 0.90 0.0481305 0.0424594 21310 115450 -1 582 11 253 352 21177 5630 1.7847 1.7847 -38.388 -1.7847 0 0 612192. 2118.31 0.20 0.02 0.17 -1 -1 0.20 0.00821106 0.00733367 40 20 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.91 vpr 61.17 MiB 0.03 6144 -1 -1 5 0.06 -1 -1 32156 -1 -1 7 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62636 27 14 91 105 1 70 48 17 17 289 -1 unnamed_device 22.5 MiB 0.02 359 1875 334 1509 32 61.2 MiB 0.02 0.00 1.74751 -38.0286 -1.74751 1.74751 0.95 0.000399123 0.000368654 0.00960368 0.00887756 26 782 16 6.55708e+06 84385 477104. 1650.88 0.88 0.055629 0.0490976 21022 109990 -1 739 13 288 437 26332 6701 1.61564 1.61564 -41.0607 -1.61564 0 0 585099. 2024.56 0.19 0.03 0.16 -1 -1 0.19 0.0114245 0.0101843 42 24 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.89 vpr 61.09 MiB 0.01 6012 -1 -1 6 0.08 -1 -1 31864 -1 -1 7 29 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62560 29 15 95 110 1 74 51 17 17 289 -1 unnamed_device 22.6 MiB 0.04 393 3811 1258 2017 536 61.1 MiB 0.04 0.00 2.47436 -47.7903 -2.47436 2.47436 0.95 0.000410482 0.000378211 0.0175403 0.0161537 26 836 30 6.55708e+06 84385 477104. 1650.88 0.89 0.0766164 0.0677414 21022 109990 -1 781 10 297 399 27292 6696 2.23396 2.23396 -48.1296 -2.23396 0 0 585099. 2024.56 0.20 0.03 0.12 -1 -1 0.20 0.0100811 0.00903196 45 23 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 4.17 vpr 61.22 MiB 0.02 5976 -1 -1 6 0.06 -1 -1 31852 -1 -1 9 31 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62688 31 16 104 120 1 80 56 17 17 289 -1 unnamed_device 22.7 MiB 0.14 318 5620 1687 2850 1083 61.2 MiB 0.04 0.00 2.31696 -46.1298 -2.31696 2.31696 0.95 0.000322878 0.000295631 0.0181944 0.0166554 28 899 16 6.55708e+06 108495 500653. 1732.36 1.00 0.0708566 0.0627012 21310 115450 -1 747 12 319 467 28038 7282 2.07656 2.07656 -46.8018 -2.07656 0 0 612192. 2118.31 0.20 0.03 0.17 -1 -1 0.20 0.0125221 0.0111438 50 27 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.94 vpr 61.47 MiB 0.01 6004 -1 -1 7 0.06 -1 -1 31832 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62948 33 17 108 125 1 86 57 17 17 289 -1 unnamed_device 23.0 MiB 0.03 550 4526 1045 3142 339 61.5 MiB 0.04 0.00 3.16202 -64.7432 -3.16202 3.16202 0.95 0.000463838 0.000428431 0.0203095 0.0187574 30 1080 27 6.55708e+06 84385 526063. 1820.29 0.90 0.08197 0.0728203 21886 126133 -1 971 12 307 433 28025 6683 2.92162 2.92162 -64.2421 -2.92162 0 0 666494. 2306.21 0.22 0.03 0.18 -1 -1 0.22 0.0128013 0.011434 51 26 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 6.02 vpr 61.43 MiB 0.01 5940 -1 -1 7 0.07 -1 -1 32640 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62904 37 19 127 146 1 101 64 17 17 289 -1 unnamed_device 22.7 MiB 0.20 514 6795 1522 4730 543 61.4 MiB 0.06 0.00 3.00462 -67.1078 -3.00462 3.00462 0.96 0.000542022 0.000497119 0.0304047 0.0280285 30 1090 15 6.55708e+06 96440 526063. 1820.29 2.69 0.171612 0.152175 21886 126133 -1 946 13 343 485 26736 6931 2.76422 2.76422 -66.3273 -2.76422 0 0 666494. 2306.21 0.22 0.03 0.18 -1 -1 0.22 0.0157454 0.0141273 59 35 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 4.43 vpr 61.74 MiB 0.02 6248 -1 -1 8 0.07 -1 -1 32048 -1 -1 10 41 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63220 41 21 139 160 1 109 72 17 17 289 -1 unnamed_device 23.1 MiB 0.15 466 7224 1587 4756 881 61.7 MiB 0.06 0.00 3.12482 -72.4463 -3.12482 3.12482 0.94 0.000585941 0.000537805 0.0296336 0.0273828 26 1176 14 6.55708e+06 120550 477104. 1650.88 1.03 0.0959116 0.0860609 21022 109990 -1 992 60 521 751 349760 277715 2.88442 2.88442 -73.8868 -2.88442 0 0 585099. 2024.56 0.20 0.22 0.16 -1 -1 0.20 0.0605657 0.0536567 67 37 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.97 vpr 61.59 MiB 0.03 6236 -1 -1 9 0.07 -1 -1 32300 -1 -1 11 45 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63068 45 23 152 175 1 124 79 17 17 289 -1 unnamed_device 22.9 MiB 0.06 700 10219 3011 5707 1501 61.6 MiB 0.08 0.00 3.23076 -85.7251 -3.23076 3.23076 0.96 0.000636299 0.000587737 0.040168 0.0371027 30 1350 16 6.55708e+06 132605 526063. 1820.29 2.73 0.217915 0.194235 21886 126133 -1 1250 15 429 583 35763 8490 2.9787 2.9787 -84.954 -2.9787 0 0 666494. 2306.21 0.21 0.04 0.18 -1 -1 0.21 0.0202543 0.018224 74 40 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 6.42 vpr 61.94 MiB 0.01 6140 -1 -1 10 0.07 -1 -1 32668 -1 -1 11 49 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63428 49 25 165 190 1 131 85 17 17 289 -1 unnamed_device 23.3 MiB 0.23 510 10687 3828 4882 1977 61.9 MiB 0.08 0.00 3.62716 -93.9579 -3.62716 3.62716 0.95 0.000577829 0.000539911 0.0408866 0.0377321 34 1348 13 6.55708e+06 132605 585099. 2024.56 3.01 0.222018 0.198376 22462 138074 -1 1076 12 464 619 34731 9575 3.50696 3.50696 -93.1779 -3.50696 0 0 742403. 2568.87 0.24 0.04 0.20 -1 -1 0.24 0.0188192 0.0170145 79 43 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.65 vpr 61.80 MiB 0.01 6420 -1 -1 11 0.08 -1 -1 32568 -1 -1 14 57 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63280 57 29 199 228 1 157 100 17 17 289 -1 unnamed_device 23.0 MiB 0.23 782 9380 2186 6081 1113 61.8 MiB 0.07 0.00 4.46034 -123.44 -4.46034 4.46034 0.96 0.000605841 0.000559835 0.0339911 0.0314438 30 1804 48 6.55708e+06 168770 526063. 1820.29 1.19 0.174767 0.156836 21886 126133 -1 1460 13 570 852 45024 11444 3.85934 3.85934 -118.77 -3.85934 0 0 666494. 2306.21 0.22 0.05 0.18 -1 -1 0.22 0.0236573 0.0213575 93 57 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 4.68 vpr 62.28 MiB 0.01 6352 -1 -1 13 0.08 -1 -1 32060 -1 -1 15 65 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63776 65 33 224 257 1 179 113 17 17 289 -1 unnamed_device 23.4 MiB 0.44 1034 16493 4993 9000 2500 62.3 MiB 0.11 0.00 4.49339 -150.828 -4.49339 4.49339 0.96 0.000937882 0.00086809 0.0590234 0.0546171 28 2094 24 6.55708e+06 180825 500653. 1732.36 1.03 0.179539 0.162231 21310 115450 -1 1921 12 695 915 63028 15444 4.26336 4.26336 -151.13 -4.26336 0 0 612192. 2118.31 0.20 0.06 0.16 -1 -1 0.20 0.0249062 0.0225707 107 62 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 7.38 vpr 62.89 MiB 0.02 6432 -1 -1 19 0.11 -1 -1 32496 -1 -1 24 97 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64400 97 49 340 389 1 265 170 17 17 289 -1 unnamed_device 23.9 MiB 0.28 1415 34950 10191 20929 3830 62.9 MiB 0.22 0.00 6.91256 -283.047 -6.91256 6.91256 0.96 0.00143473 0.00132934 0.110179 0.102108 34 2902 25 6.55708e+06 289320 585099. 2024.56 3.54 0.507859 0.460642 22462 138074 -1 2593 11 922 1294 92517 23588 6.61819 6.61819 -278.129 -6.61819 0 0 742403. 2568.87 0.23 0.08 0.20 -1 -1 0.23 0.0358744 0.0328197 160 98 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 12.55 vpr 63.77 MiB 0.03 6688 -1 -1 26 0.11 -1 -1 32544 -1 -1 31 129 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65300 129 65 454 519 1 354 225 17 17 289 -1 unnamed_device 24.3 MiB 0.20 1738 52893 17102 30066 5725 63.8 MiB 0.32 0.00 9.58349 -458.959 -9.58349 9.58349 0.95 0.00192435 0.00178641 0.153331 0.142328 34 3942 23 6.55708e+06 373705 585099. 2024.56 8.61 0.838476 0.764406 22462 138074 -1 3385 12 1244 1747 115011 28796 9.09424 9.09424 -446.392 -9.09424 0 0 742403. 2568.87 0.23 0.10 0.20 -1 -1 0.23 0.0511318 0.0469612 213 132 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.39 abc 29.26 MiB 0.02 6300 -1 -1 1 0.03 -1 -1 29964 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23020 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.38 abc 29.34 MiB 0.03 6396 -1 -1 1 0.02 -1 -1 30044 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23352 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.46 abc 29.38 MiB 0.03 6136 -1 -1 1 0.02 -1 -1 30084 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23228 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.39 abc 29.30 MiB 0.01 6252 -1 -1 1 0.03 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23204 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.40 abc 29.33 MiB 0.01 6264 -1 -1 1 0.03 -1 -1 30036 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23244 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.40 abc 29.36 MiB 0.02 6296 -1 -1 1 0.03 -1 -1 30060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23272 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.40 abc 29.45 MiB 0.03 6332 -1 -1 1 0.02 -1 -1 30156 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23344 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.40 abc 29.30 MiB 0.01 6436 -1 -1 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23364 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.38 abc 29.47 MiB 0.01 6184 -1 -1 1 0.03 -1 -1 30176 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23392 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.41 abc 29.29 MiB 0.01 6316 -1 -1 1 0.02 -1 -1 29996 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23304 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.37 abc 29.25 MiB 0.01 6484 -1 -1 1 0.03 -1 -1 29956 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23404 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.41 abc 29.58 MiB 0.01 6388 -1 -1 1 0.02 -1 -1 30292 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23776 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.38 abc 29.61 MiB 0.01 6344 -1 -1 1 0.03 -1 -1 30324 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23540 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.42 abc 29.65 MiB 0.03 6444 -1 -1 1 0.02 -1 -1 30360 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23832 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.41 abc 29.82 MiB 0.01 6280 -1 -1 1 0.03 -1 -1 30536 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23516 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.40 abc 29.66 MiB 0.01 6356 -1 -1 1 0.02 -1 -1 30376 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23880 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 7 7 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.36 abc 29.73 MiB 0.02 6616 -1 -1 1 0.03 -1 -1 30448 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23668 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 8 8 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.39 abc 29.64 MiB 0.02 6516 -1 -1 1 0.03 -1 -1 30348 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23616 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 9 9 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.47 abc 29.82 MiB 0.03 6716 -1 -1 1 0.03 -1 -1 30532 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23984 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 13 13 0 0 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.45 abc 29.70 MiB 0.02 6940 -1 -1 1 0.04 -1 -1 30412 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 24276 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 17 17 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.39 abc 29.38 MiB 0.03 6260 -1 -1 1 0.02 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22928 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.41 abc 29.36 MiB 0.01 6260 -1 -1 1 0.02 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22928 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.41 abc 29.32 MiB 0.01 6304 -1 -1 1 0.03 -1 -1 30020 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23048 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.35 abc 29.46 MiB 0.01 6256 -1 -1 1 0.02 -1 -1 30172 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23044 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.43 abc 29.31 MiB 0.03 6260 -1 -1 1 0.02 -1 -1 30012 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22900 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.40 abc 29.30 MiB 0.03 6412 -1 -1 1 0.02 -1 -1 30004 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22968 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.40 abc 29.30 MiB 0.02 6284 -1 -1 1 0.02 -1 -1 30008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23068 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.42 abc 29.35 MiB 0.01 6224 -1 -1 1 0.02 -1 -1 30056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22976 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.37 abc 29.36 MiB 0.02 6360 -1 -1 1 0.03 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23120 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.36 abc 29.46 MiB 0.01 6348 -1 -1 1 0.03 -1 -1 30164 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 22964 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.41 abc 29.36 MiB 0.01 6316 -1 -1 1 0.03 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23180 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.36 abc 29.51 MiB 0.01 6396 -1 -1 1 0.02 -1 -1 30216 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23232 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.37 abc 29.62 MiB 0.01 6408 -1 -1 1 0.02 -1 -1 30336 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23256 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.35 abc 29.62 MiB 0.01 6452 -1 -1 1 0.03 -1 -1 30332 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23508 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.43 abc 29.68 MiB 0.02 6344 -1 -1 1 0.02 -1 -1 30388 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23152 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.36 abc 29.77 MiB 0.02 6460 -1 -1 1 0.03 -1 -1 30488 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23392 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 7 7 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.38 abc 29.66 MiB 0.02 6356 -1 -1 1 0.03 -1 -1 30376 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23252 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 8 8 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.39 abc 29.69 MiB 0.01 6520 -1 -1 1 0.03 -1 -1 30404 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23656 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 9 9 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.40 abc 29.68 MiB 0.02 6880 -1 -1 1 0.03 -1 -1 30392 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 23700 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 13 13 0 0 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.41 abc 29.86 MiB 0.02 6776 -1 -1 1 0.04 -1 -1 30572 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 24068 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 17 17 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.63 vpr 61.31 MiB 0.01 6316 -1 -1 1 0.02 -1 -1 30196 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62780 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 22.6 MiB 0.02 63 419 85 325 9 61.3 MiB 0.01 0.00 0.803048 -11.7113 -0.803048 0.803048 1.01 0.000115703 0.000104219 0.00248269 0.00222935 22 232 10 6.64007e+06 25116 420624. 1455.45 0.70 0.0188354 0.0162609 20818 92861 -1 196 8 97 97 4416 1451 0.912248 0.912248 -13.152 -0.912248 0 0 500653. 1732.36 0.17 0.01 0.13 -1 -1 0.17 0.00390172 0.0035265 16 2 7 7 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.58 vpr 61.36 MiB 0.03 6392 -1 -1 1 0.02 -1 -1 30016 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62836 13 7 48 49 1 32 23 17 17 289 -1 unnamed_device 22.7 MiB 0.02 113 727 127 584 16 61.4 MiB 0.01 0.00 0.825048 -14.4294 -0.825048 0.825048 0.99 0.000125571 0.00011309 0.00358775 0.00322947 26 247 6 6.64007e+06 37674 477104. 1650.88 0.67 0.0135043 0.0116866 21682 110474 -1 253 10 96 96 5814 1694 0.825048 0.825048 -15.7267 -0.825048 0 0 585099. 2024.56 0.20 0.01 0.16 -1 -1 0.20 0.00487818 0.00437432 19 2 8 8 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.71 vpr 61.23 MiB 0.01 6108 -1 -1 1 0.02 -1 -1 30120 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62700 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 22.5 MiB 0.02 103 938 201 719 18 61.2 MiB 0.01 0.00 1.18536 -16.7279 -1.18536 1.18536 0.98 0.000194182 0.000177814 0.00531568 0.0048707 26 296 14 6.64007e+06 37674 477104. 1650.88 0.78 0.027702 0.0241689 21682 110474 -1 255 12 171 171 7592 2494 0.954248 0.954248 -18.6358 -0.954248 0 0 585099. 2024.56 0.23 0.02 0.16 -1 -1 0.23 0.00640486 0.00575347 22 2 9 9 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.77 vpr 61.42 MiB 0.01 6304 -1 -1 1 0.03 -1 -1 30016 -1 -1 4 17 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62892 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 22.7 MiB 0.03 174 858 170 673 15 61.4 MiB 0.01 0.00 1.19636 -20.4292 -1.19636 1.19636 0.98 0.000158989 0.000143916 0.00348312 0.00316506 26 351 9 6.64007e+06 50232 477104. 1650.88 0.76 0.0272919 0.0237987 21682 110474 -1 343 15 138 138 7704 2264 0.921248 0.921248 -21.734 -0.921248 0 0 585099. 2024.56 0.22 0.02 0.16 -1 -1 0.22 0.00679754 0.00601394 25 2 10 10 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.84 vpr 61.36 MiB 0.01 6232 -1 -1 1 0.02 -1 -1 30048 -1 -1 4 19 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62836 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 22.8 MiB 0.03 216 1021 207 713 101 61.4 MiB 0.01 0.00 1.20736 -23.977 -1.20736 1.20736 0.99 0.000243033 0.000223112 0.00533354 0.00490576 26 442 13 6.64007e+06 50232 477104. 1650.88 0.85 0.0281258 0.0244045 21682 110474 -1 419 12 187 187 12739 3257 0.987248 0.987248 -25.9698 -0.987248 0 0 585099. 2024.56 0.23 0.02 0.16 -1 -1 0.23 0.00723711 0.0064074 28 2 11 11 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 3.88 vpr 61.54 MiB 0.01 6412 -1 -1 1 0.02 -1 -1 30048 -1 -1 5 21 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63016 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 23.1 MiB 0.03 214 1623 338 1262 23 61.5 MiB 0.02 0.00 1.21836 -25.661 -1.21836 1.21836 0.98 0.000272138 0.000250413 0.00831597 0.00767986 28 467 13 6.64007e+06 62790 500653. 1732.36 0.86 0.038732 0.0339266 21970 115934 -1 429 12 134 134 7869 2282 0.943248 0.943248 -27.0018 -0.943248 0 0 612192. 2118.31 0.21 0.02 0.16 -1 -1 0.21 0.00746885 0.00664669 31 2 12 12 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.67 vpr 61.50 MiB 0.01 6276 -1 -1 1 0.03 -1 -1 30260 -1 -1 5 23 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62980 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 22.8 MiB 0.04 261 1536 299 1189 48 61.5 MiB 0.02 0.00 1.22936 -29.0547 -1.22936 1.22936 0.92 0.000295184 0.000271395 0.00731757 0.00672944 22 568 14 6.64007e+06 62790 420624. 1455.45 0.75 0.0410044 0.0359424 20818 92861 -1 506 11 199 199 13088 3699 1.10745 1.10745 -32.0351 -1.10745 0 0 500653. 1732.36 0.20 0.03 0.13 -1 -1 0.20 0.0151575 0.0133105 34 2 13 13 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.80 vpr 61.47 MiB 0.01 6260 -1 -1 1 0.03 -1 -1 30052 -1 -1 5 25 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62944 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 22.8 MiB 0.03 303 1618 294 1276 48 61.5 MiB 0.02 0.00 1.24036 -31.9481 -1.24036 1.24036 0.96 0.000316354 0.000291154 0.00757555 0.00697705 26 656 12 6.64007e+06 62790 477104. 1650.88 0.81 0.0424619 0.0373186 21682 110474 -1 635 11 267 267 20790 5144 1.10745 1.10745 -34.9991 -1.10745 0 0 585099. 2024.56 0.19 0.02 0.16 -1 -1 0.19 0.00835673 0.00743413 37 2 14 14 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.82 vpr 61.52 MiB 0.01 6324 -1 -1 1 0.02 -1 -1 30064 -1 -1 6 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62996 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 23.1 MiB 0.03 324 2231 466 1582 183 61.5 MiB 0.02 0.00 1.25136 -34.9134 -1.25136 1.25136 0.95 0.000328185 0.000301419 0.0096156 0.00882967 26 657 19 6.64007e+06 75348 477104. 1650.88 0.80 0.0487004 0.0427251 21682 110474 -1 642 12 177 177 12847 3231 1.04225 1.04225 -37.0687 -1.04225 0 0 585099. 2024.56 0.26 0.02 0.14 -1 -1 0.26 0.00776323 0.00696115 40 2 15 15 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 4.01 vpr 61.71 MiB 0.03 6292 -1 -1 1 0.02 -1 -1 30268 -1 -1 6 29 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63196 29 15 104 105 1 73 50 17 17 289 -1 unnamed_device 23.2 MiB 0.03 332 2626 448 2137 41 61.7 MiB 0.03 0.00 1.26236 -36.933 -1.26236 1.26236 0.95 0.000354517 0.000326698 0.0110615 0.0101922 32 715 15 6.64007e+06 75348 554710. 1919.41 0.91 0.0518265 0.0457882 22834 132086 -1 665 9 264 264 19013 4931 0.956248 0.956248 -38.329 -0.956248 0 0 701300. 2426.64 0.25 0.02 0.20 -1 -1 0.25 0.00834853 0.00750376 43 2 16 16 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.85 vpr 61.70 MiB 0.02 6236 -1 -1 1 0.02 -1 -1 30304 -1 -1 7 31 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63184 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 23.2 MiB 0.03 430 4134 883 2967 284 61.7 MiB 0.04 0.00 1.62267 -42.2033 -1.62267 1.62267 0.96 0.000381488 0.000351602 0.0165045 0.0152134 26 840 9 6.64007e+06 87906 477104. 1650.88 0.80 0.0565092 0.0501826 21682 110474 -1 803 16 354 354 25144 6064 1.07325 1.07325 -43.1628 -1.07325 0 0 585099. 2024.56 0.24 0.03 0.16 -1 -1 0.24 0.0129664 0.0115094 46 2 17 17 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.97 vpr 61.71 MiB 0.03 6336 -1 -1 1 0.03 -1 -1 30528 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63192 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 23.2 MiB 0.03 400 5507 1293 3991 223 61.7 MiB 0.05 0.00 1.63367 -44.5064 -1.63367 1.63367 1.06 0.000408945 0.000377519 0.0214126 0.0197253 26 883 13 6.64007e+06 87906 477104. 1650.88 0.84 0.0663624 0.0590511 21682 110474 -1 791 19 389 389 30948 7774 1.06345 1.06345 -44.7308 -1.06345 0 0 585099. 2024.56 0.19 0.04 0.15 -1 -1 0.19 0.0147011 0.0129749 49 2 18 18 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 3.83 vpr 61.86 MiB 0.02 6216 -1 -1 1 0.03 -1 -1 30340 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63344 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 23.3 MiB 0.04 467 4001 820 3044 137 61.9 MiB 0.04 0.00 1.65567 -51.2944 -1.65567 1.65567 0.97 0.000459785 0.000424853 0.015202 0.0140269 26 1042 14 6.64007e+06 100464 477104. 1650.88 0.81 0.0658689 0.0583462 21682 110474 -1 917 13 352 352 28690 6808 1.17145 1.17145 -51.8759 -1.17145 0 0 585099. 2024.56 0.19 0.03 0.16 -1 -1 0.19 0.0124416 0.0110161 55 2 20 20 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 4.02 vpr 61.92 MiB 0.02 6408 -1 -1 1 0.02 -1 -1 30420 -1 -1 8 41 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63404 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 23.3 MiB 0.04 551 4966 1056 3737 173 61.9 MiB 0.05 0.00 1.67767 -59.443 -1.67767 1.67767 0.93 0.000500905 0.000462299 0.0184939 0.0170705 32 1095 12 6.64007e+06 100464 554710. 1919.41 0.94 0.0734061 0.0652999 22834 132086 -1 968 14 416 416 31553 7556 1.07325 1.07325 -55.2431 -1.07325 0 0 701300. 2426.64 0.23 0.04 0.19 -1 -1 0.23 0.0152335 0.0135691 61 2 22 22 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 4.21 vpr 62.12 MiB 0.03 6456 -1 -1 1 0.02 -1 -1 30496 -1 -1 9 45 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63608 45 23 160 161 1 114 77 17 17 289 -1 unnamed_device 23.5 MiB 0.04 584 6760 1544 5011 205 62.1 MiB 0.05 0.00 1.69967 -63.9386 -1.69967 1.69967 1.14 0.000553185 0.0005114 0.0216194 0.0199584 28 1213 14 6.64007e+06 113022 500653. 1732.36 0.91 0.0826337 0.0737112 21970 115934 -1 1091 11 457 457 39339 9371 1.11845 1.11845 -61.1772 -1.11845 0 0 612192. 2118.31 0.20 0.04 0.17 -1 -1 0.20 0.0134772 0.0121033 67 2 24 24 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 4.11 vpr 61.82 MiB 0.02 6576 -1 -1 1 0.02 -1 -1 30284 -1 -1 10 49 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63300 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 23.1 MiB 0.04 754 12711 4339 7261 1111 61.8 MiB 0.09 0.00 2.07098 -75.5183 -2.07098 2.07098 0.97 0.000599035 0.000553004 0.0428346 0.0395009 30 1330 13 6.64007e+06 125580 526063. 1820.29 0.93 0.108506 0.097651 22546 126617 -1 1194 13 486 486 33990 8082 1.18125 1.18125 -69.8231 -1.18125 0 0 666494. 2306.21 0.22 0.04 0.18 -1 -1 0.22 0.0166537 0.0149633 73 2 26 26 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.10 vpr 62.04 MiB 0.01 6400 -1 -1 1 0.03 -1 -1 29960 -1 -1 11 57 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63532 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 23.4 MiB 0.04 781 12973 3128 9205 640 62.0 MiB 0.10 0.00 2.11498 -88.6474 -2.11498 2.11498 0.96 0.000688368 0.000636098 0.0448878 0.0414394 28 1578 16 6.64007e+06 138138 500653. 1732.36 0.93 0.124055 0.111839 21970 115934 -1 1448 16 714 714 62305 14306 1.22525 1.22525 -82.5246 -1.22525 0 0 612192. 2118.31 0.20 0.06 0.17 -1 -1 0.20 0.0225172 0.0202093 85 2 30 30 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 4.48 vpr 62.51 MiB 0.02 6396 -1 -1 1 0.02 -1 -1 30360 -1 -1 13 65 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64008 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 23.7 MiB 0.07 1016 17401 7183 10118 100 62.5 MiB 0.15 0.00 2.50829 -106.175 -2.50829 2.50829 1.04 0.00111944 0.00103172 0.0660215 0.0610914 32 1822 12 6.64007e+06 163254 554710. 1919.41 1.05 0.153471 0.139055 22834 132086 -1 1725 13 707 707 61118 14144 1.31125 1.31125 -94.7939 -1.31125 0 0 701300. 2426.64 0.23 0.06 0.19 -1 -1 0.23 0.0222217 0.0200178 97 2 34 34 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 4.68 vpr 63.29 MiB 0.03 6728 -1 -1 1 0.03 -1 -1 30476 -1 -1 19 97 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64812 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 24.3 MiB 0.06 1599 34969 13035 19621 2313 63.3 MiB 0.24 0.00 3.38291 -183.275 -3.38291 3.38291 0.95 0.000963566 0.000889534 0.0970877 0.0900944 30 2918 27 6.64007e+06 238602 526063. 1820.29 1.24 0.242446 0.220945 22546 126617 -1 2584 20 1013 1013 84748 19026 1.51625 1.51625 -149.177 -1.51625 0 0 666494. 2306.21 0.23 0.09 0.18 -1 -1 0.23 0.0338627 0.030536 145 2 50 50 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 5.00 vpr 63.69 MiB 0.02 6864 -1 -1 1 0.03 -1 -1 30296 -1 -1 25 129 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65216 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 24.6 MiB 0.08 1778 56234 21152 30749 4333 63.7 MiB 0.40 0.01 4.25753 -263.048 -4.25753 4.25753 0.96 0.00166468 0.00155049 0.144367 0.134295 32 3642 14 6.64007e+06 313950 554710. 1919.41 1.24 0.332515 0.305368 22834 132086 -1 3143 13 1268 1268 107582 25490 1.71025 1.71025 -195.441 -1.71025 0 0 701300. 2426.64 0.23 0.11 0.19 -1 -1 0.23 0.0456319 0.0418789 193 2 66 66 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.50 vpr 61.26 MiB 0.01 6352 -1 -1 1 0.03 -1 -1 30152 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62732 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 22.6 MiB 0.01 67 419 80 331 8 61.3 MiB 0.01 0.00 0.803048 -11.78 -0.803048 0.803048 0.96 0.000100883 8.92e-05 0.00277665 0.00250861 22 251 10 6.65987e+06 25356 420624. 1455.45 0.65 0.0192068 0.0166272 20818 92861 -1 198 8 93 93 4666 1476 1.04345 1.04345 -14.1496 -1.04345 0 0 500653. 1732.36 0.18 0.01 0.12 -1 -1 0.18 0.00386653 0.00348934 16 2 7 7 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.35 vpr 61.01 MiB 0.01 6268 -1 -1 1 0.02 -1 -1 30016 -1 -1 3 13 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62476 13 7 48 49 1 32 23 17 17 289 -1 unnamed_device 22.3 MiB 0.01 108 791 160 615 16 61.0 MiB 0.01 0.00 0.825048 -14.3383 -0.825048 0.825048 0.95 0.000169095 0.000154616 0.00465786 0.00425356 20 310 11 6.65987e+06 38034 394039. 1363.46 0.60 0.0103609 0.00931345 20530 87850 -1 273 13 145 145 8632 2391 1.01045 1.01045 -16.4625 -1.01045 0 0 477104. 1650.88 0.16 0.01 0.12 -1 -1 0.16 0.005724 0.00508009 19 2 8 8 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.79 vpr 61.41 MiB 0.02 6244 -1 -1 1 0.02 -1 -1 30088 -1 -1 3 15 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62880 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 22.7 MiB 0.01 103 938 195 725 18 61.4 MiB 0.02 0.00 1.18536 -16.8309 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62996 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 22.8 MiB 0.02 256 1536 305 1173 58 61.5 MiB 0.03 0.00 1.22936 -28.8616 -1.22936 1.22936 0.94 0.000904834 0.000833633 0.00784941 0.00717263 22 582 9 6.65987e+06 63390 420624. 1455.45 0.71 0.0387895 0.0339824 20818 92861 -1 499 15 192 192 11326 3279 1.12945 1.12945 -32.4515 -1.12945 0 0 500653. 1732.36 0.17 0.02 0.13 -1 -1 0.17 0.00865158 0.00766782 34 2 13 13 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.78 vpr 61.39 MiB 0.01 6200 -1 -1 1 0.02 -1 -1 30192 -1 -1 5 25 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62868 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 22.7 MiB 0.02 293 2293 540 1476 277 61.4 MiB 0.02 0.00 1.24036 -31.9104 -1.24036 1.24036 0.96 0.000313177 0.000288035 0.010364 0.00953574 26 636 12 6.65987e+06 63390 477104. 1650.88 0.79 0.0451094 0.039711 21682 110474 -1 608 15 296 296 22531 5808 1.02025 1.02025 -34.0861 -1.02025 0 0 585099. 2024.56 0.20 0.03 0.16 -1 -1 0.20 0.0106445 0.00943593 37 2 14 14 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.83 vpr 61.36 MiB 0.01 6236 -1 -1 1 0.03 -1 -1 30124 -1 -1 6 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62832 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 22.9 MiB 0.02 378 2231 478 1580 173 61.4 MiB 0.02 0.00 1.25136 -36.02 -1.25136 1.25136 0.96 0.000339532 0.000312504 0.0097423 0.00897193 30 668 13 6.65987e+06 76068 526063. 1820.29 0.86 0.0468599 0.0413419 22546 126617 -1 622 11 216 216 15522 3800 0.856048 0.856048 -34.1489 -0.856048 0 0 666494. 2306.21 0.22 0.02 0.18 -1 -1 0.22 0.00895817 0.00799451 40 2 15 15 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 3.68 vpr 61.53 MiB 0.01 6456 -1 -1 1 0.03 -1 -1 30324 -1 -1 6 29 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63004 29 15 104 105 1 73 50 17 17 289 -1 unnamed_device 23.0 MiB 0.02 331 2442 412 1993 37 61.5 MiB 0.03 0.00 1.26236 -36.7774 -1.26236 1.26236 0.96 0.00035608 0.00032823 0.0103726 0.0095505 26 789 11 6.65987e+06 76068 477104. 1650.88 0.76 0.0486244 0.0429782 21682 110474 -1 724 15 378 378 28843 7348 1.06545 1.06545 -39.427 -1.06545 0 0 585099. 2024.56 0.20 0.03 0.16 -1 -1 0.20 0.0118046 0.010488 43 2 16 16 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.78 vpr 61.38 MiB 0.03 6324 -1 -1 1 0.03 -1 -1 30284 -1 -1 7 31 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62848 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 22.9 MiB 0.02 435 3216 703 2283 230 61.4 MiB 0.03 0.00 1.62267 -42.4629 -1.62267 1.62267 0.96 0.000387867 0.000357866 0.0129899 0.0119562 26 863 15 6.65987e+06 88746 477104. 1650.88 0.80 0.0548182 0.0484952 21682 110474 -1 825 14 376 376 28737 7038 1.05019 1.05019 -43.3518 -1.05019 0 0 585099. 2024.56 0.19 0.03 0.16 -1 -1 0.19 0.0118349 0.0105148 46 2 17 17 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.85 vpr 61.43 MiB 0.01 6336 -1 -1 1 0.03 -1 -1 30284 -1 -1 7 33 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62900 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 22.9 MiB 0.02 427 6052 1399 4413 240 61.4 MiB 0.05 0.00 1.63367 -46.0647 -1.63367 1.63367 0.88 0.000406209 0.000374769 0.0236579 0.0218125 26 862 21 6.65987e+06 88746 477104. 1650.88 0.87 0.0742398 0.0660048 21682 110474 -1 837 14 393 393 28781 7241 1.11845 1.11845 -46.125 -1.11845 0 0 585099. 2024.56 0.19 0.03 0.16 -1 -1 0.19 0.0126558 0.0112639 49 2 18 18 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 3.82 vpr 61.51 MiB 0.01 6388 -1 -1 1 0.02 -1 -1 30428 -1 -1 8 37 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62984 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 22.9 MiB 0.03 445 3874 792 2975 107 61.5 MiB 0.04 0.00 1.65567 -51.2172 -1.65567 1.65567 0.95 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/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63592 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 23.4 MiB 0.03 728 12751 3280 8876 595 62.1 MiB 0.09 0.00 2.11498 -85.6644 -2.11498 2.11498 0.97 0.000693276 0.000640716 0.041245 0.0381323 32 1538 17 6.65987e+06 139458 554710. 1919.41 1.01 0.133302 0.120096 22834 132086 -1 1375 14 555 555 43916 11014 1.23625 1.23625 -78.4834 -1.23625 0 0 701300. 2426.64 0.23 0.05 0.19 -1 -1 0.23 0.0202577 0.0181988 85 2 30 30 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 4.19 vpr 62.18 MiB 0.02 6540 -1 -1 1 0.03 -1 -1 30536 -1 -1 13 65 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63676 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 23.3 MiB 0.03 1003 17401 6715 9666 1020 62.2 MiB 0.10 0.00 2.50829 -107.27 -2.50829 2.50829 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49 1 25 22 17 17 289 -1 unnamed_device 23.4 MiB 0.04 58 562 122 423 17 61.9 MiB 0.01 0.00 0.802432 -14.4781 -0.802432 0.802432 1.00 0.000169573 0.000154834 0.00365235 0.00333138 22 206 13 6.95648e+06 28951.4 443629. 1535.05 1.96 0.0318908 0.0275353 23458 102101 -1 189 12 79 79 5519 1756 0.87204 0.87204 -15.9569 -0.87204 0 0 531479. 1839.03 0.17 0.01 0.14 -1 -1 0.17 0.00546236 0.00487674 10 2 8 8 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 3.92 vpr 62.06 MiB 0.01 6240 -1 -1 1 0.02 -1 -1 30112 -1 -1 2 15 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63548 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 23.4 MiB 0.04 82 673 149 507 17 62.1 MiB 0.01 0.00 0.830632 -16.8934 -0.830632 0.830632 1.01 0.000189877 0.000173438 0.00408628 0.00373528 26 255 11 6.95648e+06 28951.4 503264. 1741.40 0.79 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63788 21 11 76 77 1 49 34 17 17 289 -1 unnamed_device 23.7 MiB 0.04 238 914 193 707 14 62.3 MiB 0.01 0.00 0.896632 -26.6731 -0.896632 0.896632 1.01 0.000270266 0.000248424 0.00535576 0.00493972 26 545 15 6.95648e+06 28951.4 503264. 1741.40 2.07 0.074246 0.0639801 24322 120374 -1 481 16 290 290 21220 5201 1.14723 1.14723 -30.8531 -1.14723 0 0 618332. 2139.56 0.20 0.02 0.17 -1 -1 0.20 0.00956601 0.00844827 16 2 12 12 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 6.07 vpr 62.29 MiB 0.03 6216 -1 -1 1 0.03 -1 -1 30016 -1 -1 3 23 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63784 23 12 83 84 1 55 38 17 17 289 -1 unnamed_device 23.8 MiB 0.04 198 1298 273 1012 13 62.3 MiB 0.02 0.00 0.907632 -28.5647 -0.907632 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0.03 0.22 -1 -1 0.24 0.0109102 0.00967308 19 2 14 14 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 4.99 vpr 62.43 MiB 0.02 6340 -1 -1 1 0.03 -1 -1 30156 -1 -1 3 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63924 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 23.9 MiB 0.04 180 3971 1477 2086 408 62.4 MiB 0.04 0.00 0.951632 -32.5735 -0.951632 0.951632 1.00 0.000331553 0.000304909 0.0184768 0.0170144 36 677 34 6.95648e+06 43427 648988. 2245.63 1.69 0.0808537 0.0710269 26050 158493 -1 479 36 638 638 44030 11892 1.21133 1.21133 -34.4716 -1.21133 0 0 828058. 2865.25 0.26 0.05 0.22 -1 -1 0.26 0.0226096 0.0198257 20 2 15 15 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 5.22 vpr 62.30 MiB 0.03 6472 -1 -1 1 0.03 -1 -1 30268 -1 -1 3 29 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63796 29 15 104 105 1 72 47 17 17 289 -1 unnamed_device 23.7 MiB 0.05 227 4331 1745 2561 25 62.3 MiB 0.04 0.00 0.962632 -36.3287 -0.962632 0.962632 1.02 0.00035448 0.000325727 0.0193523 0.0177854 36 789 39 6.95648e+06 43427 648988. 2245.63 1.96 0.102472 0.0898472 26050 158493 -1 644 21 474 474 83491 31666 1.26153 1.26153 -42.9574 -1.26153 0 0 828058. 2865.25 0.25 0.05 0.23 -1 -1 0.25 0.0153445 0.0135655 22 2 16 16 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 6.42 vpr 62.38 MiB 0.01 6456 -1 -1 1 0.03 -1 -1 30276 -1 -1 3 31 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63872 31 16 111 112 1 78 50 17 17 289 -1 unnamed_device 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on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65192 97 49 342 343 1 243 156 17 17 289 -1 unnamed_device 24.7 MiB 0.10 1600 30324 11596 17665 1063 63.7 MiB 0.20 0.00 2.41762 -168.85 -2.41762 2.41762 0.99 0.0012189 0.00113346 0.0914509 0.0849961 52 2765 24 6.95648e+06 144757 926341. 3205.33 5.79 0.458578 0.416464 29218 227130 -1 2519 17 1068 1068 118761 24238 1.49993 1.49993 -156.625 -1.49993 0 0 1.14541e+06 3963.36 0.35 0.10 0.35 -1 -1 0.35 0.0416608 0.0379877 73 2 50 50 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 12.07 vpr 64.49 MiB 0.03 6956 -1 -1 1 0.04 -1 -1 30328 -1 -1 13 129 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66040 129 65 454 455 1 324 207 17 17 289 -1 unnamed_device 25.4 MiB 0.08 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63608 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 23.6 MiB 0.02 340 1441 266 1110 65 62.1 MiB 0.02 0.00 0.901432 -33.1271 -0.901432 0.901432 0.99 0.000312456 0.000287804 0.00724621 0.00668238 34 752 16 6.99608e+06 44147 618332. 2139.56 1.48 0.0691239 0.060081 25762 151098 -1 707 15 318 318 34339 7519 1.17833 1.17833 -38.8894 -1.17833 0 0 787024. 2723.27 0.24 0.03 0.22 -1 -1 0.24 0.010303 0.00911183 19 2 14 14 0 0 -fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 4.92 vpr 62.22 MiB 0.01 6328 -1 -1 1 0.03 -1 -1 30080 -1 -1 3 27 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63716 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 23.7 MiB 0.02 178 3971 1404 1915 652 62.2 MiB 0.04 0.00 0.912432 -32.1713 -0.912432 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62792 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 22.6 MiB 0.01 171 94 40 54 0 61.3 MiB 0.01 0.00 1.02368 -16.6264 -1.02368 1.02368 0.96 0.000150084 0.000136484 0.00132734 0.00125 20 289 7 6.79088e+06 26944 414966. 1435.87 1.90 0.0145334 0.0126342 22510 95286 -1 266 5 64 74 4817 1223 1.02368 1.02368 -16.8849 -1.02368 0 0 503264. 1741.40 0.16 0.01 0.15 -1 -1 0.16 0.00329059 0.00301525 10 7 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_006bits.v common 3.63 vpr 61.30 MiB 0.02 5944 -1 -1 3 0.05 -1 -1 32032 -1 -1 2 13 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62776 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 22.7 MiB 0.01 78 532 122 389 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65484 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 25.0 MiB 0.13 1688 49117 18704 27900 2513 63.9 MiB 0.39 0.01 4.35372 -274.791 -4.35372 4.35372 0.99 0.0016391 0.00152441 0.138557 0.129324 36 3981 28 6.87369e+06 237555 648988. 2245.63 2.31 0.431598 0.395411 26050 158493 -1 3348 17 1626 1626 161860 37131 1.87697 1.87697 -215.085 -1.87697 0 0 828058. 2865.25 0.25 0.13 0.23 -1 -1 0.25 0.0558962 0.051049 130 2 66 66 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 5.09 vpr 61.48 MiB 0.01 6404 -1 -1 1 0.02 -1 -1 30040 -1 -1 2 11 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62960 11 6 41 42 1 27 19 17 17 289 -1 unnamed_device 22.8 MiB 0.04 64 444 102 328 14 61.5 MiB 0.01 0.00 0.850273 -12.9291 -0.850273 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63048 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 22.9 MiB 0.05 144 1041 203 767 71 61.6 MiB 0.01 0.00 1.2326 -21.8949 -1.2326 1.2326 1.00 0.000218316 0.000200418 0.00572431 0.00525213 24 415 18 6.89349e+06 42281.5 470940. 1629.55 2.00 0.0431018 0.0372535 24034 113901 -1 396 8 135 135 15448 4273 1.12264 1.12264 -24.7204 -1.12264 0 0 586450. 2029.24 0.18 0.02 0.16 -1 -1 0.18 0.00519604 0.00465696 18 2 10 10 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 4.81 vpr 61.85 MiB 0.02 6300 -1 -1 1 0.02 -1 -1 30240 -1 -1 3 19 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63332 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 23.1 MiB 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63584 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 23.6 MiB 0.07 389 3541 674 2740 127 62.1 MiB 0.03 0.00 1.70293 -53.0421 -1.70293 1.70293 1.01 0.000461074 0.000425981 0.0145987 0.013486 30 873 17 6.89349e+06 70469.2 556674. 1926.21 2.04 0.11842 0.103829 25186 138497 -1 796 13 362 362 22124 5809 1.12567 1.12567 -52.3224 -1.12567 0 0 706193. 2443.58 0.22 0.03 0.20 -1 -1 0.22 0.0131863 0.0116944 38 2 20 20 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 4.90 vpr 62.24 MiB 0.03 6368 -1 -1 1 0.03 -1 -1 30496 -1 -1 6 41 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63732 41 21 146 147 1 101 68 17 17 289 -1 unnamed_device 23.7 MiB 0.07 518 8624 2120 6023 481 62.2 MiB 0.07 0.00 1.72493 -63.2115 -1.72493 1.72493 1.01 0.000502665 0.00046437 0.032912 0.03043 34 1201 12 6.89349e+06 84563 618332. 2139.56 1.47 0.128077 0.113684 25762 151098 -1 1092 19 486 486 44758 10102 1.05732 1.05732 -60.475 -1.05732 0 0 787024. 2723.27 0.24 0.05 0.22 -1 -1 0.24 0.0191615 0.0169569 42 2 22 22 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 4.89 vpr 62.16 MiB 0.07 6400 -1 -1 1 0.03 -1 -1 30320 -1 -1 6 45 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63656 45 23 160 161 1 115 74 17 17 289 -1 unnamed_device 23.6 MiB 0.07 723 8754 3062 4670 1022 62.2 MiB 0.07 0.00 1.74693 -75.1597 -1.74693 1.74693 1.00 0.000548145 0.000506193 0.0322829 0.0297954 34 1449 13 6.89349e+06 84563 618332. 2139.56 1.51 0.136395 0.121126 25762 151098 -1 1323 17 566 566 61281 12665 1.18067 1.18067 -69.4326 -1.18067 0 0 787024. 2723.27 0.24 0.05 0.22 -1 -1 0.24 0.0192756 0.0171967 47 2 24 24 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 4.97 vpr 62.20 MiB 0.03 6460 -1 -1 1 0.02 -1 -1 30324 -1 -1 7 49 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63696 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 23.6 MiB 0.10 626 7431 1738 5510 183 62.2 MiB 0.07 0.00 2.12926 -77.4465 -2.12926 2.12926 0.99 0.000597739 0.000552859 0.0265395 0.0245343 34 1418 16 6.89349e+06 98656.9 618332. 2139.56 1.51 0.143182 0.1274 25762 151098 -1 1247 15 537 537 47107 10808 1.35887 1.35887 -77.4553 -1.35887 0 0 787024. 2723.27 0.24 0.05 0.22 -1 -1 0.24 0.0186467 0.0166572 50 2 26 26 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 5.16 vpr 62.36 MiB 0.02 6424 -1 -1 1 0.03 -1 -1 30160 -1 -1 8 57 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63852 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 23.8 MiB 0.12 744 15004 6297 8531 176 62.4 MiB 0.11 0.00 2.17326 -95.1695 -2.17326 2.17326 1.00 0.00068394 0.000631618 0.0499335 0.0461505 34 1591 25 6.89349e+06 112751 618332. 2139.56 1.64 0.195702 0.175187 25762 151098 -1 1347 18 763 763 72750 17001 1.27767 1.27767 -84.9346 -1.27767 0 0 787024. 2723.27 0.24 0.06 0.22 -1 -1 0.24 0.0246571 0.0220987 58 2 30 30 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 5.09 vpr 62.41 MiB 0.02 6416 -1 -1 1 0.03 -1 -1 30360 -1 -1 9 65 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63908 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 23.7 MiB 0.09 917 16046 5086 9451 1509 62.4 MiB 0.12 0.00 2.57759 -114.077 -2.57759 2.57759 1.01 0.000794256 0.00073469 0.0524572 0.0485583 34 1955 15 6.89349e+06 126845 618332. 2139.56 1.64 0.207582 0.186274 25762 151098 -1 1772 11 686 686 59886 13353 1.43387 1.43387 -105.391 -1.43387 0 0 787024. 2723.27 0.24 0.05 0.22 -1 -1 0.24 0.0193739 0.0174416 66 2 34 34 0 0 -fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 5.87 vpr 63.18 MiB 0.03 6764 -1 -1 1 0.04 -1 -1 30372 -1 -1 13 97 0 0 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64700 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 24.3 MiB 0.13 1233 31119 11476 17865 1778 63.2 MiB 0.22 0.01 3.47425 -185.498 -3.47425 3.47425 1.01 0.00120524 0.00111939 0.0901849 0.0837306 34 2983 38 6.89349e+06 183220 618332. 2139.56 2.13 0.373536 0.33893 25762 151098 -1 2521 14 1152 1152 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odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 2.26 vpr 61.58 MiB 0.03 6444 -1 -1 2 0.05 -1 -1 31768 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63060 11 6 34 40 1 20 19 17 17 289 -1 unnamed_device 22.9 MiB 0.01 130 394 82 301 11 61.6 MiB 0.01 0.00 1.13885 -14.0146 -1.13885 1.13885 0.32 0.000122715 0.000111905 0.00236611 0.00216193 -1 -1 -1 -1 26 218 5 6.55708e+06 24110 477104. 1650.88 0.84 0.0245212 0.0201793 21022 109990 -1 206 5 43 48 4257 1028 1.13885 1.13885 -14.7223 -1.13885 0 0 585099. 2024.56 0.02 0.01 0.09 -1 -1 0.02 0.00260643 0.00236173 16 7 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.94 vpr 61.66 MiB 0.03 6308 -1 -1 3 0.06 -1 -1 32080 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63136 13 7 41 48 1 27 23 17 17 289 -1 unnamed_device 22.9 MiB 0.01 89 887 227 554 106 61.7 MiB 0.01 0.00 1.37725 -15.4804 -1.37725 1.37725 0.33 0.000148682 0.000136138 0.00420888 0.00384431 -1 -1 -1 -1 20 157 8 6.55708e+06 36165 394039. 1363.46 0.52 0.0125893 0.0108682 19870 87366 -1 153 6 78 88 3997 1739 1.25705 1.25705 -15.7895 -1.25705 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00296234 0.00265101 19 9 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.79 vpr 61.64 MiB 0.02 6372 -1 -1 3 0.05 -1 -1 32476 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63116 15 8 47 55 1 35 27 17 17 289 -1 unnamed_device 23.2 MiB 0.01 130 1227 294 745 188 61.6 MiB 0.04 0.00 1.23151 -17.8131 -1.23151 1.23151 0.31 0.000251661 0.000232432 0.00907333 0.00831964 -1 -1 -1 -1 26 323 11 6.55708e+06 48220 477104. 1650.88 0.33 0.0245422 0.0211268 21022 109990 -1 248 9 79 100 4761 1525 1.13885 1.13885 -18.5343 -1.13885 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.0039751 0.00350554 23 10 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.97 vpr 61.75 MiB 0.02 6292 -1 -1 3 0.06 -1 -1 32132 -1 -1 6 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63236 17 9 56 65 1 37 32 17 17 289 -1 unnamed_device 23.3 MiB 0.02 178 932 169 687 76 61.8 MiB 0.01 0.00 1.77705 -23.0458 -1.77705 1.77705 0.31 0.000174397 0.000161035 0.00373922 0.00346015 -1 -1 -1 -1 20 342 11 6.55708e+06 72330 394039. 1363.46 0.56 0.0159688 0.0137057 19870 87366 -1 328 13 123 161 9114 2904 1.77705 1.77705 -24.539 -1.77705 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00580726 0.00504644 26 14 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.15 vpr 62.00 MiB 0.03 6376 -1 -1 4 0.06 -1 -1 31884 -1 -1 6 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63492 19 10 60 70 1 46 35 17 17 289 -1 unnamed_device 23.6 MiB 0.02 186 1232 224 942 66 62.0 MiB 0.01 0.00 1.83817 -25.6813 -1.83817 1.83817 0.31 0.000184382 0.000170589 0.00452271 0.00419042 -1 -1 -1 -1 20 466 19 6.55708e+06 72330 394039. 1363.46 0.71 0.0279027 0.0235479 19870 87366 -1 393 15 214 298 11674 4307 2.03937 2.03937 -30.3326 -2.03937 0 0 477104. 1650.88 0.02 0.02 0.07 -1 -1 0.02 0.00672168 0.00579046 29 13 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.07 vpr 61.77 MiB 0.03 6324 -1 -1 4 0.06 -1 -1 31936 -1 -1 7 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63256 21 11 69 80 1 46 39 17 17 289 -1 unnamed_device 23.3 MiB 0.02 276 1359 263 1085 11 61.8 MiB 0.01 0.00 1.9859 -31.0743 -1.9859 1.9859 0.31 0.00021121 0.000195409 0.00496748 0.00458686 -1 -1 -1 -1 24 564 17 6.55708e+06 84385 448715. 1552.65 0.61 0.0325681 0.0275036 20734 103517 -1 514 9 133 201 13014 3345 1.7455 1.7455 -31.9552 -1.7455 0 0 554710. 1919.41 0.02 0.01 0.09 -1 -1 0.02 0.00525742 0.00461312 33 17 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.16 vpr 61.84 MiB 0.03 6428 -1 -1 5 0.06 -1 -1 32364 -1 -1 6 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63320 23 12 73 85 1 53 41 17 17 289 -1 unnamed_device 23.3 MiB 0.02 292 1441 261 1160 20 61.8 MiB 0.01 0.00 2.60682 -38.0792 -2.60682 2.60682 0.31 0.000219464 0.000203084 0.00513191 0.00474464 -1 -1 -1 -1 22 602 9 6.55708e+06 72330 420624. 1455.45 0.69 0.0348324 0.0294077 20158 92377 -1 535 10 166 220 13909 3706 2.48662 2.48662 -38.3511 -2.48662 0 0 500653. 1732.36 0.02 0.02 0.08 -1 -1 0.02 0.00585718 0.00513458 34 16 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 2.17 vpr 61.76 MiB 0.03 6308 -1 -1 5 0.06 -1 -1 31864 -1 -1 8 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63240 25 13 82 95 1 61 46 17 17 289 -1 unnamed_device 23.2 MiB 0.03 391 1932 388 1396 148 61.8 MiB 0.02 0.00 2.1851 -40.0296 -2.1851 2.1851 0.31 0.000241424 0.000223353 0.00638335 0.00590312 -1 -1 -1 -1 26 680 12 6.55708e+06 96440 477104. 1650.88 0.69 0.0630077 0.0530182 21022 109990 -1 649 11 188 284 12781 3584 2.1851 2.1851 -42.0607 -2.1851 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00671151 0.00588002 39 20 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.13 vpr 61.99 MiB 0.03 6376 -1 -1 5 0.06 -1 -1 32084 -1 -1 10 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63476 27 14 91 105 1 72 51 17 17 289 -1 unnamed_device 23.3 MiB 0.03 462 2683 577 1816 290 62.0 MiB 0.02 0.00 2.59656 -45.1104 -2.59656 2.59656 0.28 0.000274162 0.00025416 0.00861471 0.00797451 -1 -1 -1 -1 24 752 11 6.55708e+06 120550 448715. 1552.65 0.60 0.0418406 0.0358196 20734 103517 -1 739 14 209 307 17867 4574 2.3837 2.3837 -46.1866 -2.3837 0 0 554710. 1919.41 0.02 0.02 0.09 -1 -1 0.02 0.00866172 0.00751515 44 24 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.93 vpr 62.11 MiB 0.03 6296 -1 -1 6 0.06 -1 -1 31788 -1 -1 10 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63604 29 15 95 110 1 74 54 17 17 289 -1 unnamed_device 23.4 MiB 0.03 397 3318 653 2620 45 62.1 MiB 0.03 0.00 2.92362 -49.6372 -2.92362 2.92362 0.31 0.000285151 0.000264394 0.0100796 0.00934229 -1 -1 -1 -1 26 785 14 6.55708e+06 120550 477104. 1650.88 0.40 0.0406659 0.0350168 21022 109990 -1 694 10 212 341 15952 4689 2.76422 2.76422 -49.2109 -2.76422 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.0071525 0.00625742 46 23 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.29 vpr 61.78 MiB 0.03 6372 -1 -1 6 0.06 -1 -1 31792 -1 -1 10 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63260 31 16 104 120 1 74 57 17 17 289 -1 unnamed_device 23.1 MiB 0.03 388 2673 538 2060 75 61.8 MiB 0.02 0.00 2.4235 -49.7792 -2.4235 2.4235 0.33 0.000314307 0.000291768 0.00868864 0.00806347 -1 -1 -1 -1 26 798 10 6.55708e+06 120550 477104. 1650.88 0.75 0.0693169 0.05865 21022 109990 -1 689 13 250 353 19015 5274 2.1831 2.1831 -49.5094 -2.1831 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00917228 0.00796703 50 27 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.37 vpr 61.91 MiB 0.03 6420 -1 -1 7 0.06 -1 -1 31836 -1 -1 10 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63400 33 17 108 125 1 77 60 17 17 289 -1 unnamed_device 23.2 MiB 0.03 484 3570 643 2715 212 61.9 MiB 0.03 0.00 3.41468 -59.8938 -3.41468 3.41468 0.31 0.000321271 0.000298431 0.0107363 0.00997272 -1 -1 -1 -1 26 947 11 6.55708e+06 120550 477104. 1650.88 0.84 0.079649 0.0676146 21022 109990 -1 849 9 238 356 22359 5793 3.41468 3.41468 -62.6758 -3.41468 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00804668 0.00715803 52 26 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 2.43 vpr 62.03 MiB 0.03 6348 -1 -1 7 0.06 -1 -1 32444 -1 -1 13 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63516 37 19 127 146 1 96 69 17 17 289 -1 unnamed_device 22.9 MiB 0.04 576 5709 1280 3850 579 62.0 MiB 0.04 0.00 2.95316 -65.5347 -2.95316 2.95316 0.31 0.000369839 0.00034352 0.0160103 0.014861 -1 -1 -1 -1 26 1011 13 6.55708e+06 156715 477104. 1650.88 0.88 0.0900938 0.0771875 21022 109990 -1 976 13 305 456 21173 5968 2.8997 2.8997 -67.669 -2.8997 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0107541 0.00938794 63 35 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 1.97 vpr 62.04 MiB 0.03 6324 -1 -1 8 0.07 -1 -1 32080 -1 -1 14 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63524 41 21 139 160 1 106 76 17 17 289 -1 unnamed_device 22.8 MiB 0.05 691 4076 776 3111 189 62.0 MiB 0.03 0.00 2.9395 -74.3337 -2.9395 2.9395 0.31 0.000402257 0.000373288 0.0114107 0.010609 -1 -1 -1 -1 26 1257 13 6.55708e+06 168770 477104. 1650.88 0.38 0.0537184 0.0466845 21022 109990 -1 1170 8 268 383 24156 6017 2.9395 2.9395 -78.3932 -2.9395 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00874971 0.00779802 67 37 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.55 vpr 62.20 MiB 0.03 6348 -1 -1 9 0.08 -1 -1 32332 -1 -1 14 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63696 45 23 152 175 1 114 82 17 17 289 -1 unnamed_device 22.9 MiB 0.05 656 5778 1200 4246 332 62.2 MiB 0.04 0.00 3.50896 -86.4899 -3.50896 3.50896 0.31 0.000435088 0.00040467 0.0154814 0.0143823 -1 -1 -1 -1 26 1263 12 6.55708e+06 168770 477104. 1650.88 0.95 0.113918 0.0981967 21022 109990 -1 1167 13 370 556 29616 8301 3.30776 3.30776 -86.348 -3.30776 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0125489 0.0110314 73 40 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.53 vpr 62.25 MiB 0.03 6328 -1 -1 10 0.06 -1 -1 32632 -1 -1 15 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63740 49 25 165 190 1 123 89 17 17 289 -1 unnamed_device 22.9 MiB 0.05 770 12761 4334 6906 1521 62.2 MiB 0.08 0.00 4.11762 -102.077 -4.11762 4.11762 0.31 0.000469597 0.000436378 0.0316911 0.0294372 -1 -1 -1 -1 26 1420 16 6.55708e+06 180825 477104. 1650.88 0.96 0.113359 0.0994 21022 109990 -1 1279 14 412 589 33508 9008 3.87722 3.87722 -102.053 -3.87722 0 0 585099. 2024.56 0.03 0.03 0.09 -1 -1 0.03 0.0142206 0.0125056 79 43 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.51 vpr 62.38 MiB 0.02 6300 -1 -1 11 0.07 -1 -1 32540 -1 -1 21 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63876 57 29 199 228 1 148 107 17 17 289 -1 unnamed_device 23.1 MiB 0.05 683 9215 2009 6469 737 62.4 MiB 0.06 0.00 5.01553 -132.266 -5.01553 5.01553 0.31 0.000568179 0.000529341 0.0225074 0.0209121 -1 -1 -1 -1 28 1411 13 6.55708e+06 253155 500653. 1732.36 0.87 0.141376 0.12279 21310 115450 -1 1240 9 447 590 31672 10140 4.76548 4.76548 -132.308 -4.76548 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0128546 0.0114383 96 57 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.16 vpr 62.64 MiB 0.03 6340 -1 -1 13 0.08 -1 -1 31956 -1 -1 20 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64148 65 33 224 257 1 164 118 17 17 289 -1 unnamed_device 22.9 MiB 0.06 989 18614 4289 12324 2001 62.6 MiB 0.10 0.00 5.28408 -156.845 -5.28408 5.28408 0.31 0.000640307 0.000596942 0.0431822 0.040187 -1 -1 -1 -1 28 1859 11 6.55708e+06 241100 500653. 1732.36 0.43 0.108776 0.0969116 21310 115450 -1 1667 10 458 639 35378 9665 5.04368 5.04368 -155.125 -5.04368 0 0 612192. 2118.31 0.03 0.04 0.10 -1 -1 0.03 0.0153278 0.0136288 106 62 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.18 vpr 62.82 MiB 0.04 6404 -1 -1 19 0.10 -1 -1 32408 -1 -1 34 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64332 97 49 340 389 1 260 180 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1331 34724 8061 22998 3665 62.8 MiB 0.17 0.00 7.79296 -292.17 -7.79296 7.79296 0.31 0.000989413 0.000924399 0.0705726 0.0658766 -1 -1 -1 -1 28 2799 13 6.55708e+06 409870 500653. 1732.36 1.25 0.295876 0.264001 21310 115450 -1 2447 11 761 1108 56440 16024 7.48193 7.48193 -290.119 -7.48193 0 0 612192. 2118.31 0.03 0.05 0.10 -1 -1 0.03 0.0245827 0.0221141 165 98 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.08 vpr 63.86 MiB 0.03 6696 -1 -1 26 0.12 -1 -1 32676 -1 -1 42 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65388 129 65 454 519 1 343 236 17 17 289 -1 unnamed_device 24.2 MiB 0.12 1865 57827 16105 35644 6078 63.9 MiB 0.28 0.00 10.762 -492.423 -10.762 10.762 0.31 0.00132955 0.00123905 0.109086 0.101946 -1 -1 -1 -1 32 3613 18 6.55708e+06 506310 554710. 1919.41 0.88 0.330173 0.298856 22174 131602 -1 3191 11 997 1345 80150 22909 10.2468 10.2468 -479.947 -10.2468 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0334881 0.0303791 222 132 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.46 abc 29.31 MiB 0.03 6768 -1 -1 1 0.02 -1 -1 30016 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24016 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.40 abc 29.35 MiB 0.03 6568 -1 -1 1 0.02 -1 -1 30056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23972 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.43 abc 29.32 MiB 0.02 6704 -1 -1 1 0.02 -1 -1 30028 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24232 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.44 abc 29.37 MiB 0.03 6724 -1 -1 1 0.02 -1 -1 30076 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23992 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.44 abc 29.43 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30132 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24400 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.36 abc 29.25 MiB 0.01 6568 -1 -1 1 0.02 -1 -1 29948 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24076 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.45 abc 29.25 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 29948 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24104 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.46 abc 29.45 MiB 0.03 6724 -1 -1 1 0.02 -1 -1 30152 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24160 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.46 abc 29.42 MiB 0.02 6732 -1 -1 1 0.02 -1 -1 30128 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23976 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.44 abc 29.38 MiB 0.02 6752 -1 -1 1 0.03 -1 -1 30088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24060 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.42 abc 29.38 MiB 0.03 6720 -1 -1 1 0.02 -1 -1 30080 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24464 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.47 abc 29.64 MiB 0.04 6568 -1 -1 1 0.03 -1 -1 30352 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24000 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.45 abc 29.68 MiB 0.02 6704 -1 -1 1 0.02 -1 -1 30392 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24308 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.43 abc 29.63 MiB 0.02 6708 -1 -1 1 0.03 -1 -1 30340 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23928 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.43 abc 29.68 MiB 0.04 6816 -1 -1 1 0.02 -1 -1 30392 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24268 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.49 abc 29.64 MiB 0.04 6588 -1 -1 1 0.03 -1 -1 30352 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24092 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 7 7 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.47 abc 29.68 MiB 0.03 6716 -1 -1 1 0.02 -1 -1 30392 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24088 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 8 8 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.48 abc 29.60 MiB 0.03 6760 -1 -1 1 0.03 -1 -1 30308 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24136 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 9 9 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.49 abc 29.75 MiB 0.03 6572 -1 -1 1 0.03 -1 -1 30460 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24012 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 13 13 0 0 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.45 abc 29.75 MiB 0.04 6852 -1 -1 1 0.04 -1 -1 30464 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24180 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 17 17 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.46 abc 29.29 MiB 0.02 6708 -1 -1 1 0.02 -1 -1 29988 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23656 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.41 abc 29.41 MiB 0.01 6716 -1 -1 1 0.02 -1 -1 30112 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24148 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 2 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.46 abc 29.51 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30216 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23796 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.43 abc 29.29 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 29996 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23912 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.42 abc 29.36 MiB 0.02 6712 -1 -1 1 0.02 -1 -1 30064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23736 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.43 abc 29.29 MiB 0.03 6616 -1 -1 1 0.02 -1 -1 29992 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23772 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 3 3 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.44 abc 29.33 MiB 0.02 6652 -1 -1 1 0.02 -1 -1 30036 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23820 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.45 abc 29.42 MiB 0.02 6780 -1 -1 1 0.03 -1 -1 30128 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23864 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.47 abc 29.43 MiB 0.02 6708 -1 -1 1 0.03 -1 -1 30136 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23904 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.44 abc 29.49 MiB 0.02 6736 -1 -1 1 0.03 -1 -1 30200 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24060 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 4 4 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.47 abc 29.34 MiB 0.02 6708 -1 -1 1 0.02 -1 -1 30048 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23880 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.46 abc 29.67 MiB 0.02 6716 -1 -1 1 0.02 -1 -1 30384 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23820 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.49 abc 29.54 MiB 0.03 6696 -1 -1 1 0.03 -1 -1 30244 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24196 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 5 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.50 abc 29.68 MiB 0.03 6820 -1 -1 1 0.03 -1 -1 30396 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23788 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.49 abc 29.59 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30304 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23880 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 6 6 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.49 abc 29.71 MiB 0.03 6648 -1 -1 1 0.02 -1 -1 30428 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23816 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 7 7 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.51 abc 29.62 MiB 0.04 6588 -1 -1 1 0.02 -1 -1 30332 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23896 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 8 8 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.49 abc 29.64 MiB 0.03 6708 -1 -1 1 0.03 -1 -1 30348 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23884 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 9 9 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.51 abc 29.68 MiB 0.04 6620 -1 -1 1 0.03 -1 -1 30388 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 23796 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 13 13 0 0 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.57 abc 29.66 MiB 0.04 6816 -1 -1 1 0.03 -1 -1 30372 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 24136 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 17 17 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.88 vpr 61.86 MiB 0.03 6576 -1 -1 1 0.02 -1 -1 30168 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63344 11 6 41 42 1 26 20 17 17 289 -1 unnamed_device 23.1 MiB 0.01 136 263 59 203 1 61.9 MiB 0.01 0.00 0.803048 -13.0336 -0.803048 0.803048 0.31 0.000104173 9.5074e-05 0.00135463 0.00124089 -1 -1 -1 -1 20 227 9 6.64007e+06 37674 394039. 1363.46 0.49 0.00682042 0.00591582 20530 87850 -1 213 13 70 70 3370 1092 1.04345 1.04345 -14.39 -1.04345 0 0 477104. 1650.88 0.02 0.01 0.07 -1 -1 0.02 0.00377977 0.00328557 16 2 7 7 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 2.08 vpr 61.92 MiB 0.03 6604 -1 -1 1 0.02 -1 -1 30132 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63408 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 23.5 MiB 0.01 145 636 105 517 14 61.9 MiB 0.01 0.00 0.825048 -14.6191 -0.825048 0.825048 0.31 0.000122313 0.00011203 0.00266971 0.00244996 -1 -1 -1 -1 22 275 10 6.64007e+06 50232 420624. 1455.45 0.69 0.0223373 0.0186159 20818 92861 -1 235 15 108 108 5032 1552 0.912248 0.912248 -15.1079 -0.912248 0 0 500653. 1732.36 0.02 0.01 0.08 -1 -1 0.02 0.00472477 0.0040916 19 2 8 8 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 1.73 vpr 61.98 MiB 0.03 6804 -1 -1 1 0.02 -1 -1 30132 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63464 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.5 MiB 0.01 227 867 163 655 49 62.0 MiB 0.01 0.00 1.18536 -18.0665 -1.18536 1.18536 0.31 0.000140047 0.000128876 0.00345801 0.00317978 -1 -1 -1 -1 26 350 13 6.64007e+06 50232 477104. 1650.88 0.33 0.0189662 0.0160174 21682 110474 -1 351 10 125 125 6106 1854 0.954248 0.954248 -19.5944 -0.954248 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00412996 0.00363203 22 2 9 9 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.03 vpr 61.89 MiB 0.03 6580 -1 -1 1 0.02 -1 -1 30028 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63380 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.5 MiB 0.02 174 943 169 760 14 61.9 MiB 0.01 0.00 1.19636 -19.914 -1.19636 1.19636 0.31 0.000158116 0.000145773 0.00358447 0.00330728 -1 -1 -1 -1 20 349 19 6.64007e+06 62790 394039. 1363.46 0.65 0.0185526 0.0157803 20530 87850 -1 320 10 155 155 7334 2477 1.07445 1.07445 -22.2008 -1.07445 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00446293 0.00391146 25 2 10 10 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.45 vpr 62.06 MiB 0.03 6640 -1 -1 1 0.02 -1 -1 30024 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63548 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.6 MiB 0.02 223 1134 190 934 10 62.1 MiB 0.01 0.00 1.20736 -23.2962 -1.20736 1.20736 0.31 0.000176833 0.000163455 0.00418602 0.00386617 -1 -1 -1 -1 28 410 12 6.64007e+06 62790 500653. 1732.36 0.99 0.037395 0.0312357 21970 115934 -1 362 11 131 131 7334 2115 0.932248 0.932248 -23.521 -0.932248 0 0 612192. 2118.31 0.03 0.01 0.10 -1 -1 0.03 0.00506579 0.00442078 28 2 11 11 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.04 vpr 62.12 MiB 0.03 6684 -1 -1 1 0.02 -1 -1 30132 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63608 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.5 MiB 0.02 323 1298 247 984 67 62.1 MiB 0.01 0.00 1.21836 -27.8009 -1.21836 1.21836 0.31 0.000202917 0.0001884 0.00461098 0.00426552 -1 -1 -1 -1 20 523 16 6.64007e+06 75348 394039. 1363.46 0.58 0.0203965 0.0174694 20530 87850 -1 509 12 155 155 10820 2929 0.998248 0.998248 -29.6258 -0.998248 0 0 477104. 1650.88 0.02 0.02 0.08 -1 -1 0.02 0.00641472 0.00562137 31 2 12 12 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 1.93 vpr 62.10 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30012 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63592 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.5 MiB 0.02 205 1770 299 1445 26 62.1 MiB 0.02 0.00 1.22936 -26.9843 -1.22936 1.22936 0.31 0.000145679 0.000130774 0.00573339 0.00531444 -1 -1 -1 -1 20 438 14 6.64007e+06 87906 394039. 1363.46 0.50 0.0189757 0.0164845 20530 87850 -1 382 11 177 177 8797 3204 1.11845 1.11845 -29.7081 -1.11845 0 0 477104. 1650.88 0.02 0.02 0.07 -1 -1 0.02 0.00584345 0.00509062 34 2 13 13 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.86 vpr 62.20 MiB 0.03 6616 -1 -1 1 0.02 -1 -1 29976 -1 -1 7 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63696 25 13 90 91 1 61 45 17 17 289 -1 unnamed_device 23.6 MiB 0.02 401 2525 518 1825 182 62.2 MiB 0.02 0.00 1.24036 -33.9356 -1.24036 1.24036 0.31 0.000224977 0.000208196 0.00775309 0.00718717 -1 -1 -1 -1 26 636 13 6.64007e+06 87906 477104. 1650.88 0.35 0.0327664 0.0282301 21682 110474 -1 602 8 158 158 11379 2754 0.889048 0.889048 -33.2549 -0.889048 0 0 585099. 2024.56 0.03 0.01 0.09 -1 -1 0.03 0.00512806 0.00452575 37 2 14 14 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 1.84 vpr 62.09 MiB 0.03 6756 -1 -1 1 0.02 -1 -1 29980 -1 -1 8 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63576 27 14 97 98 1 67 49 17 17 289 -1 unnamed_device 23.4 MiB 0.02 262 2185 359 1806 20 62.1 MiB 0.02 0.00 1.25136 -32.6648 -1.25136 1.25136 0.31 0.000237796 0.00022075 0.00653957 0.00606642 -1 -1 -1 -1 26 537 12 6.64007e+06 100464 477104. 1650.88 0.35 0.0315952 0.0270894 21682 110474 -1 504 18 302 302 16010 5657 0.976248 0.976248 -33.9775 -0.976248 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00896876 0.00771322 40 2 15 15 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 2.36 vpr 62.20 MiB 0.03 6684 -1 -1 1 0.02 -1 -1 30316 -1 -1 8 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63696 29 15 104 105 1 73 52 17 17 289 -1 unnamed_device 23.6 MiB 0.02 394 3059 656 2338 65 62.2 MiB 0.03 0.00 1.26236 -37.9697 -1.26236 1.26236 0.31 0.000254084 0.000235264 0.00875769 0.00811532 -1 -1 -1 -1 26 742 12 6.64007e+06 100464 477104. 1650.88 0.86 0.0511371 0.0435734 21682 110474 -1 657 12 218 218 13114 3793 0.956248 0.956248 -37.9684 -0.956248 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00724257 0.00634647 43 2 16 16 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 1.84 vpr 62.20 MiB 0.03 6604 -1 -1 1 0.02 -1 -1 30312 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63688 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.4 MiB 0.03 368 2838 548 2263 27 62.2 MiB 0.03 0.00 1.62267 -39.2436 -1.62267 1.62267 0.31 0.000272415 0.000252766 0.00798727 0.00740779 -1 -1 -1 -1 26 687 12 6.64007e+06 113022 477104. 1650.88 0.35 0.0363444 0.0313419 21682 110474 -1 634 10 243 243 17614 5237 0.964048 0.964048 -39.834 -0.964048 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00684108 0.00601986 46 2 17 17 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 1.89 vpr 62.15 MiB 0.03 6756 -1 -1 1 0.02 -1 -1 30296 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63640 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.2 MiB 0.03 441 2681 480 2040 161 62.1 MiB 0.03 0.00 1.63367 -43.1429 -1.63367 1.63367 0.31 0.000290913 0.000270625 0.00768241 0.00713958 -1 -1 -1 -1 26 842 14 6.64007e+06 113022 477104. 1650.88 0.38 0.0390819 0.0336684 21682 110474 -1 757 11 300 300 18950 5356 1.20445 1.20445 -46.9048 -1.20445 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00764167 0.00669687 49 2 18 18 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.91 vpr 62.29 MiB 0.03 6832 -1 -1 1 0.02 -1 -1 30464 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63788 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.3 MiB 0.03 388 3603 641 2930 32 62.3 MiB 0.03 0.00 1.65567 -48.0323 -1.65567 1.65567 0.31 0.000336788 0.000314337 0.00967818 0.00901659 -1 -1 -1 -1 26 736 12 6.64007e+06 138138 477104. 1650.88 0.37 0.0439734 0.0379806 21682 110474 -1 650 11 285 285 15076 5113 1.05125 1.05125 -46.6701 -1.05125 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00852096 0.00742981 55 2 20 20 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.50 vpr 62.61 MiB 0.03 6636 -1 -1 1 0.02 -1 -1 30424 -1 -1 12 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 41 21 146 147 1 102 74 17 17 289 -1 unnamed_device 23.4 MiB 0.03 577 4104 822 3220 62 62.6 MiB 0.04 0.00 1.67767 -57.0444 -1.67767 1.67767 0.31 0.000362725 0.000337742 0.0106104 0.00987595 -1 -1 -1 -1 28 1040 17 6.64007e+06 150696 500653. 1732.36 0.95 0.0980832 0.0837458 21970 115934 -1 940 15 382 382 25658 7026 1.10745 1.10745 -54.7506 -1.10745 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0114861 0.00998555 61 2 22 22 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.05 vpr 62.53 MiB 0.04 6804 -1 -1 1 0.02 -1 -1 30312 -1 -1 13 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 45 23 160 161 1 114 81 17 17 289 -1 unnamed_device 23.3 MiB 0.03 761 9356 3852 5449 55 62.5 MiB 0.06 0.00 1.69967 -67.3409 -1.69967 1.69967 0.31 0.000389848 0.000362773 0.021996 0.0204828 -1 -1 -1 -1 28 1269 16 6.64007e+06 163254 500653. 1732.36 0.48 0.0649668 0.0571778 21970 115934 -1 1148 15 446 446 38197 9429 1.09525 1.09525 -62.8914 -1.09525 0 0 612192. 2118.31 0.03 0.03 0.10 -1 -1 0.03 0.0120875 0.0105482 67 2 24 24 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.81 vpr 62.48 MiB 0.02 6692 -1 -1 1 0.02 -1 -1 30456 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63980 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.2 MiB 0.04 813 11593 4672 6864 57 62.5 MiB 0.08 0.00 2.07098 -74.8771 -2.07098 2.07098 0.31 0.000425735 0.000396472 0.0264043 0.0245563 -1 -1 -1 -1 32 1237 11 6.64007e+06 175812 554710. 1919.41 1.18 0.102629 0.0897834 22834 132086 -1 1121 12 325 325 22310 5834 1.08305 1.08305 -65.8737 -1.08305 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0112433 0.00991557 73 2 26 26 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.11 vpr 62.69 MiB 0.03 6640 -1 -1 1 0.03 -1 -1 29968 -1 -1 17 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 57 29 202 203 1 143 103 17 17 289 -1 unnamed_device 23.3 MiB 0.04 935 15045 4530 8759 1756 62.7 MiB 0.09 0.00 2.11498 -89.4948 -2.11498 2.11498 0.31 0.000487016 0.000453823 0.0318696 0.029688 -1 -1 -1 -1 28 1595 16 6.64007e+06 213486 500653. 1732.36 0.46 0.0856085 0.0761532 21970 115934 -1 1379 14 443 443 34247 8513 1.21425 1.21425 -81.6596 -1.21425 0 0 612192. 2118.31 0.03 0.04 0.10 -1 -1 0.03 0.0142171 0.0125697 85 2 30 30 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.22 vpr 62.92 MiB 0.03 6704 -1 -1 1 0.03 -1 -1 30352 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64428 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.3 MiB 0.05 1122 18421 7032 10116 1273 62.9 MiB 0.11 0.00 2.50829 -108.018 -2.50829 2.50829 0.31 0.000566532 0.000528562 0.0381144 0.0355701 -1 -1 -1 -1 32 1704 14 6.64007e+06 238602 554710. 1919.41 0.47 0.0984369 0.0878945 22834 132086 -1 1535 11 465 465 38655 9331 1.18005 1.18005 -90.2429 -1.18005 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0138037 0.0122711 97 2 34 34 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.27 vpr 63.12 MiB 0.04 6704 -1 -1 1 0.03 -1 -1 30360 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64640 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 24.0 MiB 0.05 1707 39295 14344 22265 2686 63.1 MiB 0.23 0.00 3.38291 -181.168 -3.38291 3.38291 0.31 0.000869138 0.000815304 0.0720204 0.0674679 -1 -1 -1 -1 32 2666 14 6.64007e+06 364182 554710. 1919.41 1.40 0.256234 0.230504 22834 132086 -1 2405 18 776 776 67569 16733 1.47225 1.47225 -144.521 -1.47225 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0297577 0.0266197 145 2 50 50 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.83 vpr 63.39 MiB 0.03 6856 -1 -1 1 0.03 -1 -1 30340 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.4 MiB 0.09 2035 55365 19341 31922 4102 63.4 MiB 0.35 0.01 4.25753 -263.271 -4.25753 4.25753 0.31 0.00120102 0.00112888 0.09601 0.0902685 -1 -1 -1 -1 32 3291 15 6.64007e+06 489762 554710. 1919.41 0.63 0.229587 0.210068 22834 132086 -1 2910 19 1014 1014 86802 22344 1.61205 1.61205 -187.768 -1.61205 0 0 701300. 2426.64 0.03 0.10 0.11 -1 -1 0.03 0.0431002 0.038877 193 2 66 66 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 1.86 vpr 61.86 MiB 0.03 6576 -1 -1 1 0.02 -1 -1 30080 -1 -1 3 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63348 11 6 41 42 1 26 20 17 17 289 -1 unnamed_device 23.1 MiB 0.01 122 290 73 215 2 61.9 MiB 0.01 0.00 0.803048 -13.1372 -0.803048 0.803048 0.31 0.000104501 9.5109e-05 0.00144755 0.00132503 -1 -1 -1 -1 20 207 12 6.65987e+06 38034 394039. 1363.46 0.49 0.00728444 0.00630178 20530 87850 -1 188 9 73 73 3633 1144 0.922189 0.922189 -13.6636 -0.922189 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.0031618 0.00280442 16 2 7 7 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 1.64 vpr 61.76 MiB 0.03 6768 -1 -1 1 0.02 -1 -1 30076 -1 -1 4 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63244 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 23.4 MiB 0.01 147 636 105 515 16 61.8 MiB 0.01 0.00 0.825048 -14.6534 -0.825048 0.825048 0.31 0.000122233 0.000112014 0.00268088 0.00245979 -1 -1 -1 -1 20 277 14 6.65987e+06 50712 394039. 1363.46 0.25 0.00752938 0.00664726 20530 87850 -1 231 8 84 84 5397 1657 0.901248 0.901248 -14.9767 -0.901248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00337804 0.00300772 19 2 8 8 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 2.07 vpr 61.85 MiB 0.03 6640 -1 -1 1 0.02 -1 -1 30144 -1 -1 4 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63332 15 8 55 56 1 38 27 17 17 289 -1 unnamed_device 23.4 MiB 0.01 238 867 167 635 65 61.8 MiB 0.01 0.00 1.18536 -19.544 -1.18536 1.18536 0.32 0.000140851 0.000129741 0.00346244 0.0031901 -1 -1 -1 -1 20 420 8 6.65987e+06 50712 394039. 1363.46 0.64 0.0160163 0.0136691 20530 87850 -1 388 9 145 145 9151 2592 0.954248 0.954248 -21.1559 -0.954248 0 0 477104. 1650.88 0.02 0.01 0.09 -1 -1 0.02 0.00395321 0.00349714 22 2 9 9 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 1.96 vpr 61.82 MiB 0.01 6696 -1 -1 1 0.02 -1 -1 30004 -1 -1 5 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63308 17 9 62 63 1 41 31 17 17 289 -1 unnamed_device 23.4 MiB 0.01 172 895 165 716 14 61.8 MiB 0.01 0.00 1.19636 -19.7595 -1.19636 1.19636 0.32 0.000159483 0.000147394 0.00345089 0.00318641 -1 -1 -1 -1 20 361 13 6.65987e+06 63390 394039. 1363.46 0.57 0.0164468 0.0140398 20530 87850 -1 334 13 193 193 9618 3193 0.954248 0.954248 -21.3594 -0.954248 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00525668 0.00456049 25 2 10 10 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 2.36 vpr 62.02 MiB 0.02 6696 -1 -1 1 0.02 -1 -1 30008 -1 -1 5 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63512 19 10 69 70 1 44 34 17 17 289 -1 unnamed_device 23.5 MiB 0.01 220 1189 203 975 11 62.0 MiB 0.01 0.00 1.20736 -23.2065 -1.20736 1.20736 0.32 0.000176161 0.000162967 0.00434767 0.00401623 -1 -1 -1 -1 32 402 14 6.65987e+06 63390 554710. 1919.41 0.91 0.0374954 0.0312611 22834 132086 -1 323 9 92 92 4553 1340 0.757848 0.757848 -21.8538 -0.757848 0 0 701300. 2426.64 0.03 0.01 0.11 -1 -1 0.03 0.00454231 0.0040016 28 2 11 11 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 2.12 vpr 61.91 MiB 0.03 6696 -1 -1 1 0.02 -1 -1 30004 -1 -1 6 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63396 21 11 76 77 1 49 38 17 17 289 -1 unnamed_device 23.3 MiB 0.02 319 1424 271 1064 89 61.9 MiB 0.02 0.00 1.21836 -27.4574 -1.21836 1.21836 0.34 0.000195523 0.000181053 0.00506221 0.00469157 -1 -1 -1 -1 20 564 13 6.65987e+06 76068 394039. 1363.46 0.67 0.0207312 0.0178612 20530 87850 -1 505 7 127 127 8462 2321 0.878048 0.878048 -27.7026 -0.878048 0 0 477104. 1650.88 0.02 0.01 0.08 -1 -1 0.02 0.00445217 0.00395426 31 2 12 12 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 2.28 vpr 62.03 MiB 0.03 6560 -1 -1 1 0.02 -1 -1 30128 -1 -1 7 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63516 23 12 83 84 1 55 42 17 17 289 -1 unnamed_device 23.3 MiB 0.02 230 1554 244 1300 10 62.0 MiB 0.02 0.00 1.22936 -27.3766 -1.22936 1.22936 0.31 0.000212276 0.000196636 0.00515723 0.00478111 -1 -1 -1 -1 28 442 9 6.65987e+06 88746 500653. 1732.36 0.81 0.048974 0.0409901 21970 115934 -1 413 11 185 185 9296 3104 0.900048 0.900048 -28.4777 -0.900048 0 0 612192. 2118.31 0.03 0.02 0.10 -1 -1 0.03 0.00596745 0.00522525 34 2 13 13 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 1.90 vpr 62.18 MiB 0.02 6636 -1 -1 1 0.02 -1 -1 30072 -1 -1 7 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63672 25 13 90 91 1 61 45 17 17 289 -1 unnamed_device 23.5 MiB 0.02 409 3485 835 2303 347 62.2 MiB 0.03 0.00 1.24036 -33.7953 -1.24036 1.24036 0.31 0.000224442 0.000207614 0.0104748 0.0096921 -1 -1 -1 -1 26 637 8 6.65987e+06 88746 477104. 1650.88 0.39 0.0360189 0.031088 21682 110474 -1 624 11 212 212 14386 3643 0.911048 0.911048 -33.6091 -0.911048 0 0 585099. 2024.56 0.03 0.02 0.13 -1 -1 0.03 0.00647834 0.00570097 37 2 14 14 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.35 vpr 61.94 MiB 0.03 6756 -1 -1 1 0.02 -1 -1 30028 -1 -1 8 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63428 27 14 97 98 1 67 49 17 17 289 -1 unnamed_device 23.3 MiB 0.02 262 2185 395 1761 29 61.9 MiB 0.02 0.00 1.25136 -32.6942 -1.25136 1.25136 0.31 0.000238926 0.00022177 0.00659082 0.00611604 -1 -1 -1 -1 26 531 16 6.65987e+06 101424 477104. 1650.88 0.86 0.0704766 0.0570241 21682 110474 -1 471 16 277 277 14113 4827 1.02145 1.02145 -32.5992 -1.02145 0 0 585099. 2024.56 0.03 0.02 0.09 -1 -1 0.03 0.00833727 0.00721634 40 2 15 15 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 1.83 vpr 62.01 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30348 -1 -1 8 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63496 29 15 104 105 1 73 52 17 17 289 -1 unnamed_device 23.4 MiB 0.02 445 2380 471 1861 48 62.0 MiB 0.02 0.00 1.26236 -39.246 -1.26236 1.26236 0.31 0.000254392 0.000235531 0.00697532 0.00646239 -1 -1 -1 -1 26 753 15 6.65987e+06 101424 477104. 1650.88 0.36 0.0348818 0.0300011 21682 110474 -1 714 9 257 257 18102 4810 0.933048 0.933048 -38.8566 -0.933048 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00607428 0.00537385 43 2 16 16 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 2.58 vpr 62.32 MiB 0.03 6700 -1 -1 1 0.02 -1 -1 30404 -1 -1 9 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63812 31 16 111 112 1 79 56 17 17 289 -1 unnamed_device 23.7 MiB 0.02 391 2303 365 1903 35 62.3 MiB 0.02 0.00 1.62267 -39.7198 -1.62267 1.62267 0.31 0.000271803 0.000252259 0.00662073 0.0061278 -1 -1 -1 -1 32 691 13 6.65987e+06 114102 554710. 1919.41 1.05 0.071966 0.0608376 22834 132086 -1 647 11 218 218 14191 3952 0.965248 0.965248 -38.9172 -0.965248 0 0 701300. 2426.64 0.03 0.02 0.11 -1 -1 0.03 0.00743991 0.00653078 46 2 17 17 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 2.61 vpr 62.15 MiB 0.03 6664 -1 -1 1 0.02 -1 -1 30320 -1 -1 9 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63644 33 17 118 119 1 82 59 17 17 289 -1 unnamed_device 23.1 MiB 0.02 437 3023 558 2261 204 62.2 MiB 0.03 0.00 1.63367 -43.0272 -1.63367 1.63367 0.31 0.000276267 0.000255251 0.00858576 0.0079773 -1 -1 -1 -1 32 784 16 6.65987e+06 114102 554710. 1919.41 1.06 0.0805083 0.0682591 22834 132086 -1 696 15 276 276 16973 4776 1.10745 1.10745 -44.1166 -1.10745 0 0 701300. 2426.64 0.03 0.02 0.11 -1 -1 0.03 0.00945995 0.00822878 49 2 18 18 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 1.90 vpr 62.24 MiB 0.02 6660 -1 -1 1 0.02 -1 -1 30292 -1 -1 11 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63732 37 19 132 133 1 90 67 17 17 289 -1 unnamed_device 23.3 MiB 0.03 392 3467 586 2833 48 62.2 MiB 0.03 0.00 1.65567 -48.2349 -1.65567 1.65567 0.31 0.000329593 0.000307324 0.00936662 0.00873063 -1 -1 -1 -1 26 812 15 6.65987e+06 139458 477104. 1650.88 0.40 0.0453993 0.039156 21682 110474 -1 712 12 341 341 19867 6706 1.22645 1.22645 -51.4169 -1.22645 0 0 585099. 2024.56 0.02 0.02 0.09 -1 -1 0.02 0.00903974 0.00790258 55 2 20 20 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 2.62 vpr 62.30 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30312 -1 -1 12 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63800 41 21 146 147 1 102 74 17 17 289 -1 unnamed_device 23.1 MiB 0.03 531 4259 752 3396 111 62.3 MiB 0.04 0.00 1.67767 -55.8836 -1.67767 1.67767 0.31 0.000359195 0.000334602 0.0109398 0.0101848 -1 -1 -1 -1 30 896 10 6.65987e+06 152136 526063. 1820.29 1.07 0.0927812 0.0793515 22546 126617 -1 770 8 209 209 10850 3074 0.997048 0.997048 -50.9669 -0.997048 0 0 666494. 2306.21 0.03 0.02 0.11 -1 -1 0.03 0.00774313 0.0068671 61 2 22 22 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 2.75 vpr 62.52 MiB 0.02 6656 -1 -1 1 0.02 -1 -1 30252 -1 -1 13 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64016 45 23 160 161 1 114 81 17 17 289 -1 unnamed_device 23.2 MiB 0.03 764 9356 3815 5489 52 62.5 MiB 0.06 0.00 1.69967 -67.6805 -1.69967 1.69967 0.31 0.000389167 0.000362172 0.0220569 0.0205187 -1 -1 -1 -1 32 1188 12 6.65987e+06 164814 554710. 1919.41 1.13 0.113328 0.0982649 22834 132086 -1 1103 12 366 366 28680 7324 1.04225 1.04225 -60.952 -1.04225 0 0 701300. 2426.64 0.03 0.03 0.11 -1 -1 0.03 0.0106173 0.00935199 67 2 24 24 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 2.72 vpr 62.35 MiB 0.03 6692 -1 -1 1 0.02 -1 -1 30336 -1 -1 14 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63848 49 25 174 175 1 123 88 17 17 289 -1 unnamed_device 23.4 MiB 0.03 831 11593 4192 5757 1644 62.4 MiB 0.07 0.00 2.07098 -75.8197 -2.07098 2.07098 0.31 0.000422101 0.000393192 0.0262417 0.0244148 -1 -1 -1 -1 28 1333 28 6.65987e+06 177492 500653. 1732.36 1.09 0.124957 0.108589 21970 115934 -1 1219 17 437 437 39278 9751 1.18125 1.18125 -70.3009 -1.18125 0 0 612192. 2118.31 0.03 0.04 0.10 -1 -1 0.03 0.0145468 0.0127462 73 2 26 26 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 2.66 vpr 62.61 MiB 0.04 6704 -1 -1 1 0.03 -1 -1 30100 -1 -1 17 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64108 57 29 202 203 1 143 103 17 17 289 -1 unnamed_device 23.2 MiB 0.04 912 15286 4502 8913 1871 62.6 MiB 0.09 0.00 2.11498 -88.9574 -2.11498 2.11498 0.32 0.000489153 0.000455741 0.0323812 0.0301748 -1 -1 -1 -1 26 1550 18 6.65987e+06 215526 477104. 1650.88 0.98 0.121837 0.107277 21682 110474 -1 1388 13 443 443 31299 8177 1.24725 1.24725 -82.6298 -1.24725 0 0 585099. 2024.56 0.03 0.04 0.09 -1 -1 0.03 0.0137722 0.0122007 85 2 30 30 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 2.98 vpr 62.75 MiB 0.04 6612 -1 -1 1 0.03 -1 -1 30328 -1 -1 19 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64256 65 33 230 231 1 164 117 17 17 289 -1 unnamed_device 23.1 MiB 0.04 1143 18707 7317 10498 892 62.8 MiB 0.11 0.00 2.50829 -107.845 -2.50829 2.50829 0.31 0.000569974 0.000532034 0.0390222 0.0364211 -1 -1 -1 -1 32 1748 14 6.65987e+06 240882 554710. 1919.41 1.25 0.14817 0.130955 22834 132086 -1 1630 14 535 535 40050 9975 1.19105 1.19105 -91.6687 -1.19105 0 0 701300. 2426.64 0.03 0.04 0.11 -1 -1 0.03 0.0164661 0.0145733 97 2 34 34 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.52 vpr 62.78 MiB 0.04 6756 -1 -1 1 0.03 -1 -1 30356 -1 -1 29 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64284 97 49 342 343 1 246 175 17 17 289 -1 unnamed_device 23.7 MiB 0.06 1707 39295 13883 22023 3389 62.8 MiB 0.23 0.00 3.38291 -180.692 -3.38291 3.38291 0.31 0.000869288 0.000814436 0.0720259 0.0674873 -1 -1 -1 -1 30 2761 18 6.65987e+06 367662 526063. 1820.29 1.58 0.265662 0.238826 22546 126617 -1 2375 15 699 699 54381 13247 1.40705 1.40705 -140.081 -1.40705 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0257587 0.0231206 145 2 50 50 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 2.80 vpr 64.12 MiB 0.04 6792 -1 -1 1 0.03 -1 -1 30296 -1 -1 39 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65660 129 65 454 455 1 328 233 17 17 289 -1 unnamed_device 24.4 MiB 0.08 2016 55365 18672 32218 4475 64.1 MiB 0.35 0.01 4.25753 -263.191 -4.25753 4.25753 0.31 0.00119825 0.00112662 0.0958231 0.0900876 -1 -1 -1 -1 32 3312 15 6.65987e+06 494442 554710. 1919.41 0.64 0.229644 0.210151 22834 132086 -1 2958 13 1029 1029 81817 21457 1.61205 1.61205 -189.09 -1.61205 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.032125 0.0291029 193 2 66 66 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 2.28 vpr 62.79 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30164 -1 -1 1 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 24.4 MiB 0.03 62 386 62 311 13 62.8 MiB 0.01 0.00 0.701895 -12.1033 -0.701895 0.701895 0.33 0.000104225 9.5142e-05 0.00210608 0.00192352 -1 -1 -1 -1 22 161 9 6.95648e+06 14475.7 443629. 1535.05 0.83 0.0193973 0.0160855 23458 102101 -1 138 7 55 55 2772 942 0.74674 0.74674 -12.942 -0.74674 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00291234 0.00261908 8 2 7 7 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 2.45 vpr 62.65 MiB 0.03 6560 -1 -1 1 0.02 -1 -1 30100 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64156 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 24.2 MiB 0.03 87 592 130 456 6 62.7 MiB 0.01 0.00 0.802432 -14.5164 -0.802432 0.802432 0.34 0.000127127 0.000116896 0.0028274 0.00258618 -1 -1 -1 -1 26 198 15 6.95648e+06 28951.4 503264. 1741.40 0.92 0.0318139 0.0262425 24322 120374 -1 178 11 63 63 3258 1111 0.74674 0.74674 -15.7863 -0.74674 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00406124 0.00358157 10 2 8 8 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 2.56 vpr 62.70 MiB 0.02 6608 -1 -1 1 0.02 -1 -1 30156 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64208 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.2 MiB 0.03 100 673 142 515 16 62.7 MiB 0.01 0.00 0.830632 -16.9552 -0.830632 0.830632 0.33 0.000138329 0.00012717 0.00304865 0.00280557 -1 -1 -1 -1 30 255 11 6.95648e+06 28951.4 556674. 1926.21 1.05 0.0371939 0.0307114 25186 138497 -1 211 13 123 123 6740 2400 0.955932 0.955932 -18.5062 -0.955932 0 0 706193. 2443.58 0.03 0.01 0.11 -1 -1 0.03 0.00478076 0.00417062 11 2 9 9 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.31 vpr 63.02 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 29992 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 24.5 MiB 0.03 125 952 332 614 6 63.0 MiB 0.01 0.00 0.841632 -19.8878 -0.841632 0.841632 0.33 0.000157373 0.000144688 0.00413175 0.00380665 -1 -1 -1 -1 26 311 22 6.95648e+06 28951.4 503264. 1741.40 0.78 0.0457154 0.0377034 24322 120374 -1 298 20 261 261 14472 4694 0.960732 0.960732 -21.912 -0.960732 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00686066 0.00585132 13 2 10 10 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 2.40 vpr 62.72 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30060 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64228 19 10 69 70 1 44 32 17 17 289 -1 unnamed_device 24.2 MiB 0.02 146 1832 488 1226 118 62.7 MiB 0.02 0.00 0.874632 -22.1583 -0.874632 0.874632 0.33 0.000174979 0.000161424 0.00696673 0.00643382 -1 -1 -1 -1 26 404 21 6.95648e+06 43427 503264. 1741.40 0.87 0.0526737 0.0439072 24322 120374 -1 318 21 284 284 18247 5948 1.29263 1.29263 -24.4314 -1.29263 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00790038 0.00673662 14 2 11 11 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 1.97 vpr 62.73 MiB 0.03 6660 -1 -1 1 0.02 -1 -1 29992 -1 -1 3 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64236 21 11 76 77 1 49 35 17 17 289 -1 unnamed_device 24.1 MiB 0.02 155 2543 828 1282 433 62.7 MiB 0.02 0.00 0.896632 -24.6955 -0.896632 0.896632 0.33 0.000194126 0.000179697 0.0092792 0.00858868 -1 -1 -1 -1 26 462 31 6.95648e+06 43427 503264. 1741.40 0.45 0.0364336 0.0310881 24322 120374 -1 398 19 338 338 26201 10587 0.99734 0.99734 -27.2189 -0.99734 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00791891 0.00675717 16 2 12 12 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 1.92 vpr 62.88 MiB 0.03 6692 -1 -1 1 0.02 -1 -1 30012 -1 -1 3 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 23 12 83 84 1 55 38 17 17 289 -1 unnamed_device 24.3 MiB 0.03 382 1361 315 963 83 62.9 MiB 0.01 0.00 0.907632 -31.8241 -0.907632 0.907632 0.33 0.000209316 0.000193583 0.00519236 0.0048121 -1 -1 -1 -1 28 709 21 6.95648e+06 43427 531479. 1839.03 0.41 0.0315098 0.0268375 24610 126494 -1 672 17 385 385 39114 9217 1.10803 1.10803 -35.7734 -1.10803 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.007843 0.00674308 17 2 13 13 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 2.49 vpr 63.14 MiB 0.03 6760 -1 -1 1 0.02 -1 -1 30096 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 24.5 MiB 0.02 217 1842 400 1425 17 63.1 MiB 0.02 0.00 0.918632 -30.4825 -0.918632 0.918632 0.33 0.000225704 0.000208561 0.00649227 0.00600972 -1 -1 -1 -1 26 646 19 6.95648e+06 57902.7 503264. 1741.40 0.93 0.0509913 0.0429348 24322 120374 -1 504 13 321 321 21249 6537 1.11903 1.11903 -35.2417 -1.11903 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00707951 0.00615094 19 2 14 14 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 2.59 vpr 63.15 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30196 -1 -1 4 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 27 14 97 98 1 66 45 17 17 289 -1 unnamed_device 24.5 MiB 0.03 301 1965 420 1532 13 63.1 MiB 0.02 0.00 0.951632 -34.1049 -0.951632 0.951632 0.33 0.000237918 0.000220458 0.00657517 0.00609508 -1 -1 -1 -1 30 661 16 6.95648e+06 57902.7 556674. 1926.21 1.05 0.0629534 0.0529979 25186 138497 -1 553 14 332 332 23518 6075 1.14103 1.14103 -37.6974 -1.14103 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00772022 0.00670017 20 2 15 15 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 2.77 vpr 62.84 MiB 0.03 6756 -1 -1 1 0.02 -1 -1 30248 -1 -1 4 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 24.2 MiB 0.03 284 3615 1181 1970 464 62.8 MiB 0.03 0.00 0.962632 -36.5249 -0.962632 0.962632 0.33 0.000252111 0.000233608 0.0113814 0.0105342 -1 -1 -1 -1 28 727 17 6.95648e+06 57902.7 531479. 1839.03 1.19 0.079796 0.0676654 24610 126494 -1 620 18 431 431 33772 9630 1.64223 1.64223 -47.0349 -1.64223 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.00956765 0.00827914 22 2 16 16 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 2.54 vpr 62.99 MiB 0.03 6700 -1 -1 1 0.02 -1 -1 30292 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.2 MiB 0.04 453 4708 1459 2518 731 63.0 MiB 0.04 0.00 1.33396 -42.5374 -1.33396 1.33396 0.33 0.00027208 0.00025224 0.0140247 0.0130132 -1 -1 -1 -1 30 913 18 6.95648e+06 72378.4 556674. 1926.21 0.95 0.0723094 0.0618422 25186 138497 -1 790 14 414 414 38456 8768 1.20503 1.20503 -47.857 -1.20503 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.00869876 0.00758825 24 2 17 17 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_016bits.v common 2.15 vpr 62.87 MiB 0.03 6760 -1 -1 1 0.02 -1 -1 30248 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64376 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 23.9 MiB 0.05 377 6607 2742 3791 74 62.9 MiB 0.05 0.00 1.34496 -43.4191 -1.34496 1.34496 0.33 0.000294762 0.000272557 0.0193513 0.0179452 -1 -1 -1 -1 28 913 30 6.95648e+06 72378.4 531479. 1839.03 0.50 0.0577112 0.0502372 24610 126494 -1 715 17 452 452 41946 11009 1.42263 1.42263 -49.4656 -1.42263 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0108026 0.00939751 25 2 18 18 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_018bits.v common 2.33 vpr 63.01 MiB 0.04 6580 -1 -1 1 0.02 -1 -1 30336 -1 -1 5 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64524 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 23.9 MiB 0.07 393 3301 654 2600 47 63.0 MiB 0.03 0.00 1.36696 -49.8334 -1.36696 1.36696 0.33 0.000330266 0.000307361 0.0100521 0.00936704 -1 -1 -1 -1 32 864 42 6.95648e+06 72378.4 586450. 2029.24 0.67 0.0691101 0.0588358 25474 144626 -1 705 15 408 408 32526 9042 1.10173 1.10173 -52.471 -1.10173 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0107581 0.00935112 28 2 20 20 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 3.07 vpr 63.13 MiB 0.03 6580 -1 -1 1 0.03 -1 -1 30388 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 41 21 146 147 1 95 67 17 17 289 -1 unnamed_device 23.9 MiB 0.07 410 7955 3291 4607 57 63.1 MiB 0.05 0.00 1.38896 -55.723 -1.38896 1.38896 0.33 0.000373075 0.000347385 0.022255 0.0206821 -1 -1 -1 -1 30 1115 42 6.95648e+06 72378.4 556674. 1926.21 1.37 0.117238 0.100702 25186 138497 -1 768 18 563 563 47917 12726 1.26003 1.26003 -58.1622 -1.26003 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0132196 0.0114637 31 2 22 22 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 2.81 vpr 63.12 MiB 0.03 6808 -1 -1 1 0.02 -1 -1 30328 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64636 45 23 160 161 1 107 74 17 17 289 -1 unnamed_device 23.9 MiB 0.08 569 10614 2660 7461 493 63.1 MiB 0.07 0.00 1.41096 -65.6384 -1.41096 1.41096 0.33 0.000389385 0.000362412 0.0278189 0.0259072 -1 -1 -1 -1 30 1184 24 6.95648e+06 86854.1 556674. 1926.21 1.10 0.102487 0.0892946 25186 138497 -1 976 14 527 527 35129 9046 1.24423 1.24423 -67.232 -1.24423 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.011989 0.010522 34 2 24 24 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_024bits.v common 2.43 vpr 63.29 MiB 0.01 6560 -1 -1 1 0.02 -1 -1 30380 -1 -1 7 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 49 25 174 175 1 119 81 17 17 289 -1 unnamed_device 24.0 MiB 0.05 854 11106 4608 6456 42 63.3 MiB 0.07 0.00 1.43296 -76.1933 -1.43296 1.43296 0.33 0.00042267 0.000393493 0.0281882 0.0262471 -1 -1 -1 -1 32 1488 18 6.95648e+06 101330 586450. 2029.24 0.71 0.0909348 0.0799055 25474 144626 -1 1358 24 681 681 103355 32923 1.59383 1.59383 -87.2355 -1.59383 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0192398 0.0167411 38 2 26 26 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_028bits.v common 2.72 vpr 63.51 MiB 0.03 6712 -1 -1 1 0.03 -1 -1 30024 -1 -1 8 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 24.1 MiB 0.06 701 13726 3066 10452 208 63.5 MiB 0.08 0.00 1.47696 -80.9741 -1.47696 1.47696 0.33 0.00048541 0.000452475 0.0327471 0.0305043 -1 -1 -1 -1 36 1504 25 6.95648e+06 115805 648988. 2245.63 0.95 0.130404 0.114538 26050 158493 -1 1275 19 669 669 58321 15600 1.45133 1.45133 -89.0754 -1.45133 0 0 828058. 2865.25 0.03 0.05 0.13 -1 -1 0.03 0.0182283 0.0160219 44 2 30 30 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_032bits.v common 3.02 vpr 63.56 MiB 0.04 6608 -1 -1 1 0.03 -1 -1 30416 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65084 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 23.9 MiB 0.08 910 17311 4711 11729 871 63.6 MiB 0.10 0.00 1.88129 -96.5486 -1.88129 1.88129 0.33 0.000568125 0.000530079 0.0404902 0.0378271 -1 -1 -1 -1 38 1716 50 6.95648e+06 130281 678818. 2348.85 1.16 0.17582 0.154761 26626 170182 -1 1485 18 787 787 58967 14897 1.32593 1.32593 -97.9313 -1.32593 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0202252 0.0178317 50 2 34 34 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 6.63 vpr 63.82 MiB 0.03 6616 -1 -1 1 0.03 -1 -1 30440 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.5 MiB 0.10 1640 34012 12509 19150 2353 63.8 MiB 0.19 0.00 2.41762 -166.789 -2.41762 2.41762 0.33 0.000873313 0.000818471 0.0707271 0.0662884 -1 -1 -1 -1 46 2590 14 6.95648e+06 202660 828058. 2865.25 4.53 0.398032 0.354733 28066 200906 -1 2334 18 952 952 79254 17784 1.47173 1.47173 -153.194 -1.47173 0 0 1.01997e+06 3529.29 0.04 0.07 0.16 -1 -1 0.04 0.0305654 0.0274123 74 2 50 50 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 7.79 vpr 64.66 MiB 0.04 6776 -1 -1 1 0.03 -1 -1 30312 -1 -1 19 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66216 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 24.8 MiB 0.13 1977 51013 20101 28701 2211 64.7 MiB 0.29 0.01 2.95395 -231.581 -2.95395 2.95395 0.33 0.00120007 0.00112846 0.0995914 0.093585 -1 -1 -1 -1 56 3124 19 6.95648e+06 275038 973134. 3367.25 5.43 0.673439 0.605837 29794 239141 -1 2776 20 1296 1296 121046 30748 1.89633 1.89633 -213.812 -1.89633 0 0 1.19926e+06 4149.71 0.05 0.11 0.19 -1 -1 0.05 0.0461238 0.0416744 98 2 66 66 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_005bits.v common 2.18 vpr 62.55 MiB 0.03 6700 -1 -1 1 0.02 -1 -1 30104 -1 -1 1 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64052 11 6 41 42 1 19 18 17 17 289 -1 unnamed_device 23.8 MiB 0.01 58 363 61 287 15 62.6 MiB 0.01 0.00 0.688132 -11.6961 -0.688132 0.688132 0.33 0.000103887 9.4676e-05 0.00199438 0.00182048 -1 -1 -1 -1 26 153 8 6.99608e+06 14715.7 503264. 1741.40 0.72 0.0238353 0.0195708 24322 120374 -1 139 8 48 48 2544 859 0.688132 0.688132 -12.6806 -0.688132 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00303976 0.00271809 8 2 7 7 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_006bits.v common 2.24 vpr 62.54 MiB 0.03 6608 -1 -1 1 0.02 -1 -1 29912 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 13 7 48 49 1 26 22 17 17 289 -1 unnamed_device 24.1 MiB 0.01 78 562 126 419 17 62.5 MiB 0.01 0.00 0.802432 -14.4602 -0.802432 0.802432 0.32 0.000121935 0.000111669 0.00267955 0.00245719 -1 -1 -1 -1 26 205 14 6.99608e+06 29431.4 503264. 1741.40 0.76 0.0294451 0.0243692 24322 120374 -1 197 17 97 97 5169 1930 0.916732 0.916732 -16.4331 -0.916732 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00493038 0.00425735 10 2 8 8 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 2.42 vpr 62.64 MiB 0.03 6612 -1 -1 1 0.02 -1 -1 30092 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64140 15 8 55 56 1 31 25 17 17 289 -1 unnamed_device 24.1 MiB 0.01 98 637 131 492 14 62.6 MiB 0.01 0.00 0.813432 -16.8565 -0.813432 0.813432 0.31 6.2692e-05 5.6118e-05 0.0014755 0.00132676 -1 -1 -1 -1 32 226 11 6.99608e+06 29431.4 586450. 2029.24 0.92 0.0278602 0.0229111 25474 144626 -1 180 13 106 106 4615 1703 0.804379 0.804379 -17.6598 -0.804379 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00481667 0.00418904 11 2 9 9 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 1.91 vpr 62.59 MiB 0.04 6560 -1 -1 1 0.02 -1 -1 30016 -1 -1 2 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 17 9 62 63 1 36 28 17 17 289 -1 unnamed_device 24.1 MiB 0.01 114 952 302 601 49 62.6 MiB 0.01 0.00 0.835432 -19.044 -0.835432 0.835432 0.34 0.000156766 0.000144322 0.00408126 0.00375596 -1 -1 -1 -1 28 296 22 6.99608e+06 29431.4 531479. 1839.03 0.38 0.0237415 0.0199754 24610 126494 -1 256 22 277 277 17430 6116 1.04203 1.04203 -20.1441 -1.04203 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.00725829 0.0061685 13 2 10 10 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 2.58 vpr 62.60 MiB 0.03 6716 -1 -1 1 0.02 -1 -1 30012 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64100 19 10 69 70 1 43 32 17 17 289 -1 unnamed_device 24.1 MiB 0.02 140 1832 485 1229 118 62.6 MiB 0.02 0.00 0.846432 -21.7224 -0.846432 0.846432 0.33 0.000173613 0.000160388 0.00696085 0.00643037 -1 -1 -1 -1 32 309 11 6.99608e+06 44147 586450. 2029.24 1.04 0.0505928 0.0421812 25474 144626 -1 264 17 235 235 13568 4536 0.971732 0.971732 -22.3105 -0.971732 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00673143 0.00577916 14 2 11 11 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_010bits.v common 2.41 vpr 62.58 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30008 -1 -1 3 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64084 21 11 76 77 1 48 35 17 17 289 -1 unnamed_device 24.1 MiB 0.02 190 2315 608 1263 444 62.6 MiB 0.02 0.00 0.868432 -25.6922 -0.868432 0.868432 0.33 0.000199171 0.000180565 0.00847415 0.00783455 -1 -1 -1 -1 26 414 17 6.99608e+06 44147 503264. 1741.40 0.90 0.0472016 0.0396651 24322 120374 -1 378 13 199 199 14854 4544 0.993732 0.993732 -27.7763 -0.993732 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.0061308 0.00533051 16 2 12 12 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 2.46 vpr 62.75 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 29984 -1 -1 3 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64260 23 12 83 84 1 54 38 17 17 289 -1 unnamed_device 24.1 MiB 0.02 355 1487 338 1045 104 62.8 MiB 0.02 0.00 0.879432 -29.3885 -0.879432 0.879432 0.34 0.00021161 0.000195534 0.00560054 0.00518581 -1 -1 -1 -1 26 651 22 6.99608e+06 44147 503264. 1741.40 0.94 0.0633592 0.05278 24322 120374 -1 612 16 287 287 21910 5749 0.971732 0.971732 -32.8358 -0.971732 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00751229 0.00646523 17 2 13 13 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 2.45 vpr 62.94 MiB 0.03 6696 -1 -1 1 0.02 -1 -1 30000 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64452 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 24.3 MiB 0.02 215 1842 394 1399 49 62.9 MiB 0.02 0.00 0.901432 -30.3131 -0.901432 0.901432 0.33 0.000281864 0.000257049 0.00829278 0.00764444 -1 -1 -1 -1 26 564 17 6.99608e+06 58862.7 503264. 1741.40 0.93 0.0537918 0.0453251 24322 120374 -1 521 18 365 365 24551 7622 1.14103 1.14103 -36.1835 -1.14103 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.0085692 0.00736037 19 2 14 14 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 2.56 vpr 62.73 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30148 -1 -1 4 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 27 14 97 98 1 66 45 17 17 289 -1 unnamed_device 24.1 MiB 0.02 232 1645 306 1308 31 62.7 MiB 0.02 0.00 0.912432 -32.6875 -0.912432 0.912432 0.33 0.000237403 0.000219852 0.00563039 0.0052098 -1 -1 -1 -1 28 634 16 6.99608e+06 58862.7 531479. 1839.03 0.99 0.0510613 0.0430376 24610 126494 -1 580 15 347 347 22140 6906 1.12098 1.12098 -38.2151 -1.12098 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.00802719 0.00695465 20 2 15 15 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 2.65 vpr 62.88 MiB 0.03 6700 -1 -1 1 0.02 -1 -1 30384 -1 -1 4 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64388 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 24.2 MiB 0.03 373 3702 1135 2001 566 62.9 MiB 0.03 0.00 0.934432 -38.3641 -0.934432 0.934432 0.33 0.000251966 0.000233344 0.0115225 0.0106543 -1 -1 -1 -1 30 767 25 6.99608e+06 58862.7 556674. 1926.21 1.06 0.0735093 0.06237 25186 138497 -1 628 13 341 341 24944 6277 1.08603 1.08603 -40.6345 -1.08603 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00773893 0.00675775 22 2 16 16 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_015bits.v common 2.06 vpr 62.76 MiB 0.03 6584 -1 -1 1 0.02 -1 -1 30324 -1 -1 5 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64268 31 16 111 112 1 78 52 17 17 289 -1 unnamed_device 24.1 MiB 0.03 329 4708 1728 2615 365 62.8 MiB 0.04 0.00 1.30576 -38.8078 -1.30576 1.30576 0.33 0.000270479 0.000250497 0.0140615 0.0130288 -1 -1 -1 -1 28 861 22 6.99608e+06 73578.4 531479. 1839.03 0.43 0.0470125 0.0407944 24610 126494 -1 671 33 467 467 69994 35425 1.31648 1.31648 -46.8964 -1.31648 0 0 648988. 2245.63 0.03 0.05 0.10 -1 -1 0.03 0.0161664 0.0137404 24 2 17 17 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 2.63 vpr 62.89 MiB 0.03 6724 -1 -1 1 0.02 -1 -1 30464 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64400 33 17 118 119 1 81 55 17 17 289 -1 unnamed_device 23.8 MiB 0.03 332 6711 2788 3857 66 62.9 MiB 0.05 0.00 1.31676 -42.5221 -1.31676 1.31676 0.33 0.000290847 0.000269945 0.0196842 0.0182572 -1 -1 -1 -1 30 798 23 6.99608e+06 73578.4 556674. 1926.21 1.02 0.0861479 0.0739404 25186 138497 -1 633 14 378 378 25514 6912 1.12803 1.12803 -44.1937 -1.12803 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00909213 0.00792804 25 2 18 18 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_018bits.v common 2.26 vpr 62.82 MiB 0.03 6640 -1 -1 1 0.02 -1 -1 30308 -1 -1 5 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64324 37 19 132 133 1 87 61 17 17 289 -1 unnamed_device 23.8 MiB 0.03 358 4261 920 3151 190 62.8 MiB 0.03 0.00 1.33876 -48.1967 -1.33876 1.33876 0.33 0.000329896 0.000306815 0.0126606 0.0117764 -1 -1 -1 -1 32 835 17 6.99608e+06 73578.4 586450. 2029.24 0.64 0.056576 0.048753 25474 144626 -1 664 15 333 333 20812 6284 1.12373 1.12373 -51.9237 -1.12373 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0106675 0.00927301 28 2 20 20 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 2.31 vpr 62.79 MiB 0.04 6584 -1 -1 1 0.02 -1 -1 30456 -1 -1 5 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64292 41 21 146 147 1 94 67 17 17 289 -1 unnamed_device 23.8 MiB 0.03 468 7955 3317 4596 42 62.8 MiB 0.05 0.00 1.36076 -55.6855 -1.36076 1.36076 0.33 0.0003604 0.000335335 0.0220989 0.020532 -1 -1 -1 -1 32 929 17 6.99608e+06 73578.4 586450. 2029.24 0.64 0.0715016 0.0623443 25474 144626 -1 758 14 366 366 27217 7456 1.23803 1.23803 -58.6653 -1.23803 0 0 744469. 2576.02 0.03 0.03 0.12 -1 -1 0.03 0.0110418 0.00964779 31 2 22 22 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 2.91 vpr 62.83 MiB 0.02 6708 -1 -1 1 0.02 -1 -1 30332 -1 -1 6 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 45 23 160 161 1 106 74 17 17 289 -1 unnamed_device 23.7 MiB 0.04 574 10149 2496 7579 74 62.8 MiB 0.06 0.00 1.38276 -62.9133 -1.38276 1.38276 0.33 0.000392204 0.000364759 0.0268104 0.0248718 -1 -1 -1 -1 30 1236 38 6.99608e+06 88294.1 556674. 1926.21 1.25 0.124304 0.107554 25186 138497 -1 954 14 520 520 41622 10284 1.19403 1.19403 -64.1778 -1.19403 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.01195 0.0104728 34 2 24 24 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 2.24 vpr 63.00 MiB 0.03 6760 -1 -1 1 0.03 -1 -1 30312 -1 -1 7 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64512 49 25 174 175 1 118 81 17 17 289 -1 unnamed_device 23.7 MiB 0.04 868 11106 3989 6115 1002 63.0 MiB 0.07 0.00 1.40476 -74.1905 -1.40476 1.40476 0.33 0.000424614 0.000394513 0.0281667 0.0262197 -1 -1 -1 -1 30 1519 43 6.99608e+06 103010 556674. 1926.21 0.52 0.0915366 0.080441 25186 138497 -1 1309 16 480 480 43224 9730 1.31503 1.31503 -80.1605 -1.31503 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0139185 0.0122012 38 2 26 26 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 2.66 vpr 63.32 MiB 0.04 6704 -1 -1 1 0.02 -1 -1 30008 -1 -1 8 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 57 29 202 203 1 141 94 17 17 289 -1 unnamed_device 23.9 MiB 0.05 716 13726 3497 10051 178 63.3 MiB 0.08 0.00 1.44876 -81.7332 -1.44876 1.44876 0.33 0.000485892 0.000452708 0.0329705 0.0305998 -1 -1 -1 -1 36 1485 24 6.99608e+06 117725 648988. 2245.63 0.88 0.129849 0.114084 26050 158493 -1 1285 14 597 597 52011 13012 1.30403 1.30403 -83.6263 -1.30403 0 0 828058. 2865.25 0.03 0.04 0.13 -1 -1 0.03 0.0144526 0.0128002 44 2 30 30 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 2.83 vpr 63.25 MiB 0.04 6688 -1 -1 1 0.03 -1 -1 30304 -1 -1 9 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64772 65 33 230 231 1 162 107 17 17 289 -1 unnamed_device 23.7 MiB 0.05 974 17311 5634 10760 917 63.3 MiB 0.11 0.00 1.85309 -98.3079 -1.85309 1.85309 0.33 0.000573006 0.000535177 0.040683 0.0380129 -1 -1 -1 -1 38 1748 34 6.99608e+06 132441 678818. 2348.85 1.01 0.16221 0.143137 26626 170182 -1 1535 17 764 764 60474 14239 1.41203 1.41203 -101.564 -1.41203 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0193024 0.0170044 50 2 34 34 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 4.23 vpr 63.43 MiB 0.02 6560 -1 -1 1 0.03 -1 -1 30436 -1 -1 14 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64952 97 49 342 343 1 243 160 17 17 289 -1 unnamed_device 24.1 MiB 0.08 1658 34012 13319 19214 1479 63.4 MiB 0.19 0.00 2.38942 -166.658 -2.38942 2.38942 0.33 0.000871933 0.000816621 0.0708685 0.0663994 -1 -1 -1 -1 46 2542 21 6.99608e+06 206020 828058. 2865.25 2.20 0.318031 0.284999 28066 200906 -1 2386 18 1000 1000 89813 19714 1.40918 1.40918 -149.495 -1.40918 0 0 1.01997e+06 3529.29 0.04 0.07 0.16 -1 -1 0.04 0.0306471 0.0274583 74 2 50 50 0 0 + fixed_k6_frac_2uripple_N8_22nm.xml adder_064bits.v common 8.68 vpr 64.58 MiB 0.04 6868 -1 -1 1 0.03 -1 -1 30300 -1 -1 19 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66132 129 65 454 455 1 324 213 17 17 289 -1 unnamed_device 24.8 MiB 0.10 1985 51013 19564 29177 2272 64.6 MiB 0.31 0.01 2.92575 -230.422 -2.92575 2.92575 0.33 0.0012048 0.00113356 0.0999523 0.0940212 -1 -1 -1 -1 50 3267 26 6.99608e+06 279598 902133. 3121.57 6.41 0.669769 0.603211 28642 213929 -1 2965 18 1277 1277 117926 28131 1.74903 1.74903 -209.268 -1.74903 0 0 1.08113e+06 3740.92 0.04 0.10 0.17 -1 -1 0.04 0.0421011 0.0380301 98 2 66 66 0 0 + fixed_k6_frac_N8_22nm.xml adder_005bits.v common 1.73 vpr 61.99 MiB 0.03 6368 -1 -1 2 0.06 -1 -1 31820 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63480 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 23.2 MiB 0.01 185 119 39 80 0 62.0 MiB 0.00 0.00 1.02368 -16.2207 -1.02368 1.02368 0.33 0.000105613 9.6137e-05 0.000843747 0.000776845 -1 -1 -1 -1 20 272 6 6.79088e+06 26944 414966. 1435.87 0.27 0.00397713 0.00357669 22510 95286 -1 280 10 79 96 5531 1461 1.02368 1.02368 -16.6343 -1.02368 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00346008 0.00306058 10 7 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_006bits.v common 1.95 vpr 61.93 MiB 0.03 6440 -1 -1 3 0.05 -1 -1 31972 -1 -1 2 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63420 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 23.3 MiB 0.01 99 472 98 353 21 61.9 MiB 0.01 0.00 1.14898 -16.154 -1.14898 1.14898 0.33 0.000125154 0.000114524 0.00243451 0.00224419 -1 -1 -1 -1 20 280 10 6.79088e+06 26944 414966. 1435.87 0.53 0.00956601 0.00830799 22510 95286 -1 223 7 83 87 4348 1454 1.05944 1.05944 -17.1675 -1.05944 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00329137 0.00293956 11 9 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_007bits.v common 2.42 vpr 62.09 MiB 0.03 6444 -1 -1 3 0.05 -1 -1 32544 -1 -1 2 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63584 15 8 47 55 1 35 25 17 17 289 -1 unnamed_device 23.6 MiB 0.04 124 1141 451 677 13 62.1 MiB 0.01 0.00 1.31353 -19.8451 -1.31353 1.31353 0.33 0.000143611 0.000131677 0.00503436 0.0046201 -1 -1 -1 -1 24 275 11 6.79088e+06 26944 470940. 1629.55 0.93 0.0316593 0.0264652 23374 113417 -1 241 10 112 119 5467 1823 1.31353 1.31353 -21.0649 -1.31353 0 0 586450. 2029.24 0.03 0.01 0.09 -1 -1 0.03 0.00422996 0.00371899 13 10 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_008bits.v common 1.92 vpr 62.10 MiB 0.03 6416 -1 -1 3 0.06 -1 -1 32096 -1 -1 4 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63588 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 23.6 MiB 0.06 138 1364 351 850 163 62.1 MiB 0.02 0.00 1.56413 -22.2762 -1.56413 1.56413 0.33 0.000175061 0.00016151 0.00578447 0.00534538 -1 -1 -1 -1 26 380 13 6.79088e+06 53888 503264. 1741.40 0.36 0.0252761 0.0214839 23662 119890 -1 311 10 190 233 11383 4069 1.43883 1.43883 -23.4014 -1.43883 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00506057 0.00444233 17 14 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_009bits.v common 2.42 vpr 62.01 MiB 0.03 6376 -1 -1 4 0.06 -1 -1 32004 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63496 19 10 60 70 1 47 32 17 17 289 -1 unnamed_device 23.5 MiB 0.07 175 1032 216 789 27 62.0 MiB 0.01 0.00 1.65028 -27.4579 -1.65028 1.65028 0.33 0.000184083 0.000169959 0.00440207 0.00406982 -1 -1 -1 -1 26 388 8 6.79088e+06 40416 503264. 1741.40 0.83 0.0431103 0.0358263 23662 119890 -1 349 7 136 152 6381 2191 1.65028 1.65028 -28.9406 -1.65028 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00429807 0.00381194 17 13 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_010bits.v common 2.37 vpr 62.13 MiB 0.01 6416 -1 -1 4 0.06 -1 -1 31812 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63620 21 11 69 80 1 54 36 17 17 289 -1 unnamed_device 23.6 MiB 0.06 191 1452 298 1143 11 62.1 MiB 0.02 0.00 1.56413 -28.6885 -1.56413 1.56413 0.33 0.00021013 0.000194272 0.00585312 0.00542163 -1 -1 -1 -1 22 619 20 6.79088e+06 53888 443629. 1535.05 0.76 0.0405774 0.0341028 22798 101617 -1 442 11 230 273 12308 4104 1.51379 1.51379 -31.026 -1.51379 0 0 531479. 1839.03 0.02 0.02 0.09 -1 -1 0.02 0.006077 0.0053106 21 17 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_011bits.v common 2.02 vpr 62.25 MiB 0.03 6408 -1 -1 5 0.06 -1 -1 32476 -1 -1 4 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63748 23 12 73 85 1 57 39 17 17 289 -1 unnamed_device 23.7 MiB 0.10 324 1293 253 1010 30 62.3 MiB 0.01 0.00 1.90093 -37.0277 -1.90093 1.90093 0.33 0.000220235 0.000203862 0.00496718 0.00460762 -1 -1 -1 -1 26 610 11 6.79088e+06 53888 503264. 1741.40 0.36 0.0280228 0.0238754 23662 119890 -1 587 12 200 237 14071 3800 1.77563 1.77563 -37.5926 -1.77563 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00652735 0.00569607 21 16 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_012bits.v common 2.38 vpr 62.18 MiB 0.03 6372 -1 -1 5 0.06 -1 -1 31816 -1 -1 4 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63676 25 13 82 95 1 64 42 17 17 289 -1 unnamed_device 23.6 MiB 0.07 311 3498 1073 1762 663 62.2 MiB 0.03 0.00 2.11577 -39.2455 -2.11577 2.11577 0.33 0.000240811 0.000222276 0.0125095 0.0115677 -1 -1 -1 -1 26 678 11 6.79088e+06 53888 503264. 1741.40 0.77 0.0617736 0.0525154 23662 119890 -1 630 10 251 327 17898 4910 1.81483 1.81483 -40.2385 -1.81483 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00642909 0.00566045 25 20 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_013bits.v common 2.57 vpr 62.27 MiB 0.03 6368 -1 -1 5 0.06 -1 -1 32264 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63768 27 14 91 105 1 70 46 17 17 289 -1 unnamed_device 23.6 MiB 0.08 366 1440 252 1179 9 62.3 MiB 0.02 0.00 2.15497 -43.2188 -2.15497 2.15497 0.34 0.000272352 0.000251968 0.00569786 0.00529265 -1 -1 -1 -1 26 771 12 6.79088e+06 67360 503264. 1741.40 0.93 0.0585775 0.0494107 23662 119890 -1 724 15 295 415 26147 6829 2.06543 2.06543 -45.476 -2.06543 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00916542 0.00793504 28 24 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_014bits.v common 2.43 vpr 62.08 MiB 0.03 6384 -1 -1 6 0.06 -1 -1 31792 -1 -1 5 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63572 29 15 95 110 1 77 49 17 17 289 -1 unnamed_device 23.4 MiB 0.07 466 2363 475 1762 126 62.1 MiB 0.02 0.00 2.40562 -51.3873 -2.40562 2.40562 0.33 0.000283014 0.00026257 0.008428 0.00782966 -1 -1 -1 -1 26 1006 20 6.79088e+06 67360 503264. 1741.40 0.84 0.0737772 0.0621989 23662 119890 -1 868 15 357 442 37776 9302 2.28027 2.28027 -52.397 -2.28027 0 0 618332. 2139.56 0.03 0.03 0.08 -1 -1 0.03 0.00951784 0.00825793 29 23 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_015bits.v common 2.81 vpr 62.16 MiB 0.03 6416 -1 -1 6 0.06 -1 -1 31760 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63656 31 16 104 120 1 84 53 17 17 289 -1 unnamed_device 23.4 MiB 0.08 547 2231 435 1739 57 62.2 MiB 0.02 0.00 2.69548 -57.02 -2.69548 2.69548 0.33 0.000312731 0.000290207 0.00798741 0.00743841 -1 -1 -1 -1 30 1011 15 6.79088e+06 80832 556674. 1926.21 1.14 0.0619094 0.0525221 24526 138013 -1 888 11 296 383 24823 5960 2.44488 2.44488 -57.0491 -2.44488 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0117276 0.0101176 32 27 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_016bits.v common 2.77 vpr 62.21 MiB 0.03 6380 -1 -1 7 0.06 -1 -1 31840 -1 -1 5 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63704 33 17 108 125 1 84 55 17 17 289 -1 unnamed_device 23.5 MiB 0.14 411 6503 2709 3763 31 62.2 MiB 0.05 0.00 2.69553 -58.1741 -2.69553 2.69553 0.33 0.000323422 0.000300152 0.0211808 0.0196751 -1 -1 -1 -1 28 942 15 6.79088e+06 67360 531479. 1839.03 1.02 0.09488 0.0813611 23950 126010 -1 708 12 321 412 23073 6793 2.69553 2.69553 -57.9994 -2.69553 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.00917799 0.00802688 31 26 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_018bits.v common 2.85 vpr 62.34 MiB 0.04 6408 -1 -1 7 0.06 -1 -1 32380 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63840 37 19 127 146 1 98 63 17 17 289 -1 unnamed_device 23.2 MiB 0.17 476 6063 1544 3786 733 62.3 MiB 0.04 0.00 2.90688 -68.4098 -2.90688 2.90688 0.33 0.000368248 0.000341607 0.0191151 0.0177558 -1 -1 -1 -1 26 1168 18 6.79088e+06 94304 503264. 1741.40 1.07 0.104535 0.0896586 23662 119890 -1 1004 13 384 508 32774 8739 2.90344 2.90344 -73.1338 -2.90344 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.0111271 0.00974877 37 35 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_020bits.v common 3.15 vpr 62.30 MiB 0.04 6368 -1 -1 8 0.07 -1 -1 32016 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63792 41 21 139 160 1 107 70 17 17 289 -1 unnamed_device 23.3 MiB 0.14 570 6982 2815 4045 122 62.3 MiB 0.05 0.00 2.99652 -76.0046 -2.99652 2.99652 0.33 0.000399364 0.000370484 0.0206606 0.0191367 -1 -1 -1 -1 28 1580 50 6.79088e+06 107776 531479. 1839.03 1.37 0.132385 0.113608 23950 126010 -1 1054 10 373 485 28857 7567 2.74592 2.74592 -76.6852 -2.74592 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.010177 0.00900614 41 37 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_022bits.v common 3.10 vpr 62.59 MiB 0.03 6416 -1 -1 9 0.07 -1 -1 32328 -1 -1 8 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 45 23 152 175 1 118 76 17 17 289 -1 unnamed_device 23.4 MiB 0.17 502 8076 3035 4695 346 62.6 MiB 0.06 0.00 3.44738 -89.4365 -3.44738 3.44738 0.33 0.00043407 0.000402995 0.0234092 0.0217395 -1 -1 -1 -1 28 1205 16 6.79088e+06 107776 531479. 1839.03 1.28 0.128429 0.111207 23950 126010 -1 1016 10 411 515 32993 10013 3.14645 3.14645 -88.4177 -3.14645 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.0109613 0.00973903 46 40 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_024bits.v common 3.58 vpr 62.63 MiB 0.03 6464 -1 -1 10 0.09 -1 -1 32664 -1 -1 10 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64136 49 25 165 190 1 131 84 17 17 289 -1 unnamed_device 23.3 MiB 0.18 739 11247 4252 6647 348 62.6 MiB 0.07 0.00 3.86603 -103.96 -3.86603 3.86603 0.33 0.000472102 0.000438272 0.0304073 0.0282308 -1 -1 -1 -1 28 1645 20 6.79088e+06 134720 531479. 1839.03 1.66 0.152184 0.132201 23950 126010 -1 1446 27 611 946 116777 58516 3.66233 3.66233 -105.67 -3.66233 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0235639 0.0205086 51 43 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_028bits.v common 3.24 vpr 62.96 MiB 0.04 6380 -1 -1 11 0.07 -1 -1 32692 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64472 57 29 199 228 1 155 97 17 17 289 -1 unnamed_device 23.4 MiB 0.19 966 15637 5195 8163 2279 63.0 MiB 0.10 0.00 4.19267 -132.823 -4.19267 4.19267 0.33 0.000572989 0.00053382 0.0423166 0.0394322 -1 -1 -1 -1 30 1883 23 6.79088e+06 148192 556674. 1926.21 1.27 0.167367 0.146646 24526 138013 -1 1627 36 587 869 119586 67484 3.95993 3.95993 -132.604 -3.95993 0 0 706193. 2443.58 0.03 0.10 0.11 -1 -1 0.03 0.0362552 0.0315027 58 57 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_032bits.v common 4.55 vpr 62.89 MiB 0.03 6408 -1 -1 13 0.08 -1 -1 32052 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64404 65 33 224 257 1 173 110 17 17 289 -1 unnamed_device 23.3 MiB 0.33 796 9841 2082 7388 371 62.9 MiB 0.07 0.00 4.79019 -155.397 -4.79019 4.79019 0.33 0.000646067 0.000602862 0.0260827 0.0243204 -1 -1 -1 -1 40 1491 20 6.79088e+06 161664 706193. 2443.58 2.47 0.270638 0.235041 26254 175826 -1 1363 13 682 924 48199 14189 4.48925 4.48925 -144.593 -4.48925 0 0 926341. 3205.33 0.04 0.04 0.14 -1 -1 0.04 0.0184905 0.016418 66 62 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_048bits.v common 3.91 vpr 63.67 MiB 0.01 6528 -1 -1 19 0.10 -1 -1 32428 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 97 49 340 389 1 265 164 17 17 289 -1 unnamed_device 23.9 MiB 0.40 1609 33316 10415 19690 3211 63.7 MiB 0.18 0.00 6.98035 -294.114 -6.98035 6.98035 0.33 0.000979692 0.000914831 0.0760896 0.0710834 -1 -1 -1 -1 32 3037 18 6.79088e+06 242496 586450. 2029.24 1.57 0.319846 0.2854 24814 144142 -1 2813 16 988 1426 91867 23129 6.58396 6.58396 -295.091 -6.58396 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0326998 0.0292956 98 98 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_064bits.v common 3.69 vpr 64.08 MiB 0.04 6716 -1 -1 26 0.13 -1 -1 32516 -1 -1 23 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65616 129 65 454 519 1 349 217 17 17 289 -1 unnamed_device 24.3 MiB 0.62 2134 47740 17239 26981 3520 64.1 MiB 0.24 0.00 9.1792 -467.226 -9.1792 9.1792 0.33 0.00132682 0.00124252 0.101532 0.0950444 -1 -1 -1 -1 38 3693 17 6.79088e+06 309856 678818. 2348.85 0.94 0.287394 0.260813 25966 169698 -1 3277 14 1240 1597 98903 25444 8.678 8.678 -451.298 -8.678 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0401425 0.0363529 132 132 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 2.05 vpr 62.20 MiB 0.03 6716 -1 -1 1 0.02 -1 -1 30044 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63692 11 6 41 42 1 27 19 17 17 289 -1 unnamed_device 23.5 MiB 0.04 82 494 104 366 24 62.2 MiB 0.01 0.00 0.811073 -12.9331 -0.811073 0.811073 0.33 0.000109216 0.000100055 0.00239581 0.00218085 -1 -1 -1 -1 22 222 7 6.87369e+06 27947.7 443629. 1535.05 0.59 0.0157082 0.0131251 23458 102101 -1 180 10 122 122 4992 1656 0.936373 0.936373 -14.3779 -0.936373 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00340253 0.00299828 12 2 7 7 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 2.60 vpr 62.32 MiB 0.03 6612 -1 -1 1 0.02 -1 -1 30100 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63812 13 7 48 49 1 33 23 17 17 289 -1 unnamed_device 23.9 MiB 0.04 213 599 129 415 55 62.3 MiB 0.01 0.00 0.833073 -17.625 -0.833073 0.833073 0.33 0.000121975 0.000111736 0.00265288 0.00242771 -1 -1 -1 -1 32 353 12 6.87369e+06 41921.5 586450. 2029.24 1.07 0.0316859 0.0261142 25474 144626 -1 324 9 102 102 10094 2410 0.856592 0.856592 -18.7883 -0.856592 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00351684 0.00310223 15 2 8 8 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 2.19 vpr 62.48 MiB 0.01 6668 -1 -1 1 0.03 -1 -1 30036 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63976 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 24.0 MiB 0.05 187 748 145 594 9 62.5 MiB 0.01 0.00 1.2044 -19.4991 -1.2044 1.2044 0.33 0.000139386 0.000128323 0.00316518 0.00290833 -1 -1 -1 -1 20 408 23 6.87369e+06 41921.5 414966. 1435.87 0.71 0.0194972 0.0163899 23170 95770 -1 392 10 179 179 14036 3970 1.20697 1.20697 -23.1723 -1.20697 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00417982 0.00366155 16 2 9 9 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 1.96 vpr 62.47 MiB 0.03 6612 -1 -1 1 0.02 -1 -1 30000 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63968 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 24.0 MiB 0.05 149 997 208 726 63 62.5 MiB 0.01 0.00 1.2154 -21.2728 -1.2154 1.2154 0.25 7.035e-05 6.3019e-05 0.0019862 0.00178595 -1 -1 -1 -1 22 427 20 6.87369e+06 41921.5 443629. 1535.05 0.49 0.0172433 0.0142862 23458 102101 -1 345 13 233 233 11990 4205 1.12567 1.12567 -24.97 -1.12567 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00514588 0.00445328 19 2 10 10 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 2.67 vpr 62.71 MiB 0.03 6672 -1 -1 1 0.02 -1 -1 29940 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64220 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 24.3 MiB 0.05 147 1332 336 883 113 62.7 MiB 0.01 0.00 1.2264 -23.8065 -1.2264 1.2264 0.33 0.000183123 0.000169976 0.00519838 0.00480106 -1 -1 -1 -1 32 310 19 6.87369e+06 41921.5 586450. 2029.24 1.08 0.0524689 0.0435148 25474 144626 -1 288 16 301 301 14927 5393 1.08167 1.08167 -24.3353 -1.08167 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00651021 0.00559509 20 2 11 11 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 2.49 vpr 62.37 MiB 0.02 6712 -1 -1 1 0.02 -1 -1 29996 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63868 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 23.9 MiB 0.05 216 3399 1062 1618 719 62.4 MiB 0.03 0.00 1.2374 -27.5226 -1.2374 1.2374 0.35 0.000231461 0.000214059 0.0120169 0.0111098 -1 -1 -1 -1 28 433 11 6.87369e+06 55895.4 531479. 1839.03 0.91 0.0543141 0.0459095 24610 126494 -1 386 7 154 154 10219 3021 1.02237 1.02237 -29.2086 -1.02237 0 0 648988. 2245.63 0.03 0.01 0.10 -1 -1 0.03 0.00428849 0.00379636 22 2 12 12 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_011bits.v common 1.99 vpr 62.53 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30008 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64032 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 23.8 MiB 0.04 278 1740 348 1260 132 62.5 MiB 0.02 0.00 1.2484 -30.619 -1.2484 1.2484 0.33 0.000212692 0.000197557 0.00602394 0.00558597 -1 -1 -1 -1 30 492 12 6.87369e+06 69869.2 556674. 1926.21 0.43 0.0283989 0.0242014 25186 138497 -1 475 13 163 163 8919 2552 1.14767 1.14767 -34.0748 -1.14767 0 0 706193. 2443.58 0.03 0.02 0.13 -1 -1 0.03 0.00650489 0.00564162 24 2 13 13 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_012bits.v common 2.43 vpr 62.76 MiB 0.02 6708 -1 -1 1 0.02 -1 -1 30068 -1 -1 5 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64264 25 13 90 91 1 60 43 17 17 289 -1 unnamed_device 24.1 MiB 0.05 302 1693 290 1387 16 62.8 MiB 0.02 0.00 1.2594 -34.117 -1.2594 1.2594 0.33 0.000225641 0.000209301 0.00573914 0.00531382 -1 -1 -1 -1 26 604 12 6.87369e+06 69869.2 503264. 1741.40 0.88 0.0560887 0.0469461 24322 120374 -1 553 16 268 268 21363 5538 1.15867 1.15867 -37.5285 -1.15867 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00777771 0.00668641 26 2 14 14 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 2.39 vpr 62.59 MiB 0.03 6668 -1 -1 1 0.02 -1 -1 29972 -1 -1 5 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64088 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 23.9 MiB 0.05 267 2752 605 2119 28 62.6 MiB 0.02 0.00 1.2704 -35.8231 -1.2704 1.2704 0.33 0.000237779 0.000220202 0.00864896 0.0080164 -1 -1 -1 -1 28 626 14 6.87369e+06 69869.2 531479. 1839.03 0.79 0.0596084 0.0503997 24610 126494 -1 565 16 360 360 19568 6390 1.11467 1.11467 -38.8099 -1.11467 0 0 648988. 2245.63 0.03 0.02 0.11 -1 -1 0.03 0.0081905 0.0070539 28 2 15 15 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 2.65 vpr 62.57 MiB 0.03 6728 -1 -1 1 0.02 -1 -1 30348 -1 -1 6 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 29 15 104 105 1 74 50 17 17 289 -1 unnamed_device 23.9 MiB 0.07 449 4926 1194 3103 629 62.6 MiB 0.04 0.00 1.2814 -41.6008 -1.2814 1.2814 0.34 0.000251491 0.000232904 0.0142724 0.0132062 -1 -1 -1 -1 30 748 14 6.87369e+06 83843 556674. 1926.21 0.98 0.0710628 0.0606964 25186 138497 -1 718 16 331 331 22142 5786 1.14767 1.14767 -43.9267 -1.14767 0 0 706193. 2443.58 0.03 0.02 0.11 -1 -1 0.03 0.00873591 0.00753771 31 2 16 16 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 2.62 vpr 62.69 MiB 0.03 6648 -1 -1 1 0.02 -1 -1 30212 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.9 MiB 0.08 506 3122 687 2071 364 62.7 MiB 0.03 0.00 1.65273 -47.1101 -1.65273 1.65273 0.33 0.000271541 0.000251916 0.00930908 0.00863013 -1 -1 -1 -1 26 972 12 6.87369e+06 83843 503264. 1741.40 0.98 0.0729331 0.0618466 24322 120374 -1 878 14 403 403 35152 8582 1.18967 1.18967 -49.5108 -1.18967 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.00844785 0.00733974 32 2 17 17 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 2.13 vpr 62.65 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30260 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64156 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.7 MiB 0.08 355 7118 2954 4050 114 62.7 MiB 0.05 0.00 1.66373 -46.6834 -1.66373 1.66373 0.33 0.000292639 0.000271267 0.0202721 0.0187953 -1 -1 -1 -1 32 794 17 6.87369e+06 83843 586450. 2029.24 0.47 0.0529502 0.0463374 25474 144626 -1 640 13 379 379 22896 6687 1.20067 1.20067 -45.3375 -1.20067 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00851033 0.00741274 35 2 18 18 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 2.11 vpr 62.69 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30340 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 23.7 MiB 0.08 649 7313 2500 4015 798 62.7 MiB 0.05 0.00 1.68573 -58.9222 -1.68573 1.68573 0.33 0.000329228 0.000305972 0.0201722 0.0187566 -1 -1 -1 -1 30 989 15 6.87369e+06 97816.9 556674. 1926.21 0.43 0.0557943 0.0488353 25186 138497 -1 1001 15 396 396 27469 6892 1.13037 1.13037 -58.2873 -1.13037 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0103837 0.00897525 38 2 20 20 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 2.66 vpr 62.84 MiB 0.04 6776 -1 -1 1 0.02 -1 -1 30348 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.7 MiB 0.08 664 7846 2295 4568 983 62.8 MiB 0.05 0.00 1.70773 -65.3086 -1.70773 1.70773 0.33 0.000360815 0.000335551 0.0206228 0.0191812 -1 -1 -1 -1 26 1218 15 6.87369e+06 111791 503264. 1741.40 0.97 0.0861072 0.07439 24322 120374 -1 1110 16 473 473 35957 8835 1.22267 1.22267 -65.1761 -1.22267 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.0118095 0.010231 42 2 22 22 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 2.38 vpr 62.82 MiB 0.03 6620 -1 -1 1 0.02 -1 -1 30388 -1 -1 9 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64328 45 23 160 161 1 115 77 17 17 289 -1 unnamed_device 23.7 MiB 0.09 747 10020 3319 5209 1492 62.8 MiB 0.06 0.00 1.72973 -72.3274 -1.72973 1.72973 0.33 0.000390613 0.000363431 0.0251295 0.0233677 -1 -1 -1 -1 32 1248 13 6.87369e+06 125765 586450. 2029.24 0.63 0.0724594 0.0637838 25474 144626 -1 1131 17 445 445 37682 8907 1.17437 1.17437 -69.2803 -1.17437 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.013325 0.0115909 47 2 24 24 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 2.75 vpr 63.02 MiB 0.01 6712 -1 -1 1 0.02 -1 -1 30424 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64528 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.8 MiB 0.09 769 9983 2785 6331 867 63.0 MiB 0.07 0.00 2.11206 -79.8727 -2.11206 2.11206 0.33 0.000420086 0.000391143 0.0244999 0.0228072 -1 -1 -1 -1 26 1428 20 6.87369e+06 125765 503264. 1741.40 1.07 0.110999 0.0968084 24322 120374 -1 1344 17 540 540 50274 12230 1.24467 1.24467 -78.2689 -1.24467 0 0 618332. 2139.56 0.03 0.04 0.10 -1 -1 0.03 0.0141755 0.012354 51 2 26 26 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 2.79 vpr 63.39 MiB 0.04 6812 -1 -1 1 0.02 -1 -1 29920 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 24.0 MiB 0.09 986 14527 4652 8514 1361 63.4 MiB 0.09 0.00 2.15606 -99.1531 -2.15606 2.15606 0.33 0.000489951 0.000455425 0.0333882 0.031069 -1 -1 -1 -1 26 1828 21 6.87369e+06 153712 503264. 1741.40 1.06 0.129224 0.113522 24322 120374 -1 1668 18 675 675 67210 15649 1.38567 1.38567 -96.9365 -1.38567 0 0 618332. 2139.56 0.03 0.05 0.10 -1 -1 0.03 0.0170754 0.0149627 58 2 30 30 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 2.49 vpr 63.42 MiB 0.02 6708 -1 -1 1 0.03 -1 -1 30476 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.8 MiB 0.10 1149 15890 6271 9336 283 63.4 MiB 0.10 0.00 2.56039 -116.289 -2.56039 2.56039 0.33 0.000570494 0.000532024 0.0359975 0.0335798 -1 -1 -1 -1 32 1980 19 6.87369e+06 167686 586450. 2029.24 0.70 0.114387 0.101416 25474 144626 -1 1790 14 625 625 55337 13048 1.32437 1.32437 -103.308 -1.32437 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0161927 0.014281 67 2 34 34 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 2.84 vpr 63.51 MiB 0.04 6712 -1 -1 1 0.03 -1 -1 30432 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 24.2 MiB 0.14 1584 34212 11837 19501 2874 63.5 MiB 0.21 0.00 3.45705 -191.416 -3.45705 3.45705 0.33 0.000870741 0.000816649 0.0683671 0.0640663 -1 -1 -1 -1 32 2862 16 6.87369e+06 251529 586450. 2029.24 0.78 0.188371 0.170336 25474 144626 -1 2513 15 1047 1047 89318 22265 1.63267 1.63267 -163.007 -1.63267 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0257721 0.0230934 99 2 50 50 0 0 + fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 4.67 vpr 64.36 MiB 0.04 6876 -1 -1 1 0.03 -1 -1 30368 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65900 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.5 MiB 0.14 2195 52618 20545 30099 1974 64.4 MiB 0.33 0.01 4.35372 -284.635 -4.35372 4.35372 0.33 0.00120258 0.00112994 0.099306 0.093418 -1 -1 -1 -1 32 3987 22 6.87369e+06 335372 586450. 2029.24 2.42 0.482133 0.43529 25474 144626 -1 3398 15 1362 1362 111584 27000 1.71237 1.71237 -212.376 -1.71237 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0357095 0.032221 131 2 66 66 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 2.02 vpr 62.34 MiB 0.03 6708 -1 -1 1 0.02 -1 -1 30056 -1 -1 2 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63832 11 6 41 42 1 27 19 17 17 289 -1 unnamed_device 23.6 MiB 0.04 85 469 97 346 26 62.3 MiB 0.01 0.00 0.850273 -13.1081 -0.850273 0.850273 0.33 0.000104629 9.5431e-05 0.00228532 0.00208162 -1 -1 -1 -1 20 224 19 6.89349e+06 28187.7 414966. 1435.87 0.54 0.00970642 0.00829097 23170 95770 -1 202 12 128 128 7528 2536 1.05067 1.05067 -15.1349 -1.05067 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00366989 0.00319739 12 2 7 7 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 2.11 vpr 62.34 MiB 0.03 6616 -1 -1 1 0.02 -1 -1 29868 -1 -1 3 13 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63836 13 7 48 49 1 33 23 17 17 289 -1 unnamed_device 23.9 MiB 0.04 162 727 181 475 71 62.3 MiB 0.01 0.00 0.872273 -16.5201 -0.872273 0.872273 0.33 0.000121537 0.000111263 0.00311797 0.00284901 -1 -1 -1 -1 22 322 13 6.89349e+06 42281.5 443629. 1535.05 0.61 0.0208679 0.0173929 23458 102101 -1 305 11 116 116 8809 2344 0.96032 0.96032 -18.8019 -0.96032 0 0 531479. 1839.03 0.02 0.01 0.09 -1 -1 0.02 0.00388052 0.00340595 15 2 8 8 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 1.88 vpr 62.41 MiB 0.03 6620 -1 -1 1 0.02 -1 -1 30048 -1 -1 3 15 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63904 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 23.9 MiB 0.04 188 748 144 591 13 62.4 MiB 0.01 0.00 1.2216 -19.9265 -1.2216 1.2216 0.33 0.000139253 0.000128044 0.00321952 0.0029619 -1 -1 -1 -1 26 377 12 6.89349e+06 42281.5 503264. 1741.40 0.36 0.0186159 0.0157025 24322 120374 -1 329 14 197 197 12002 3194 0.881273 0.881273 -20.4462 -0.881273 0 0 618332. 2139.56 0.03 0.01 0.10 -1 -1 0.03 0.00485855 0.00418679 16 2 9 9 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 2.08 vpr 62.23 MiB 0.03 6612 -1 -1 1 0.02 -1 -1 30144 -1 -1 3 17 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63728 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.8 MiB 0.04 152 1041 235 743 63 62.2 MiB 0.01 0.00 1.2326 -21.189 -1.2326 1.2326 0.33 0.000157184 0.000144821 0.00417962 0.00384695 -1 -1 -1 -1 20 343 11 6.89349e+06 42281.5 414966. 1435.87 0.58 0.0159801 0.0137231 23170 95770 -1 288 9 138 138 7110 2605 0.875073 0.875073 -22.7178 -0.875073 0 0 503264. 1741.40 0.02 0.01 0.08 -1 -1 0.02 0.00430274 0.00378195 19 2 10 10 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 2.51 vpr 62.31 MiB 0.02 6644 -1 -1 1 0.02 -1 -1 29980 -1 -1 3 19 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63808 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 23.9 MiB 0.04 214 1182 282 820 80 62.3 MiB 0.01 0.00 1.2436 -24.8042 -1.2436 1.2436 0.33 0.00017517 0.000162061 0.00467232 0.004308 -1 -1 -1 -1 26 421 10 6.89349e+06 42281.5 503264. 1741.40 0.96 0.0457991 0.0380226 24322 120374 -1 376 13 193 193 11232 3145 0.995573 0.995573 -26.0806 -0.995573 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00556774 0.00481207 20 2 11 11 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 2.49 vpr 62.41 MiB 0.03 6616 -1 -1 1 0.02 -1 -1 30076 -1 -1 4 21 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63904 21 11 76 77 1 48 36 17 17 289 -1 unnamed_device 24.0 MiB 0.04 179 3399 1263 1623 513 62.4 MiB 0.03 0.00 1.2546 -27.4421 -1.2546 1.2546 0.33 0.000191961 0.000177522 0.0116707 0.0107938 -1 -1 -1 -1 26 445 9 6.89349e+06 56375.4 503264. 1741.40 0.90 0.0446987 0.0379883 24322 120374 -1 370 13 231 231 16365 4692 1.12087 1.12087 -28.776 -1.12087 0 0 618332. 2139.56 0.03 0.02 0.12 -1 -1 0.03 0.00888603 0.00761606 22 2 12 12 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 2.69 vpr 62.41 MiB 0.03 6704 -1 -1 1 0.02 -1 -1 30052 -1 -1 5 23 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63908 23 12 83 84 1 53 40 17 17 289 -1 unnamed_device 23.9 MiB 0.06 276 1604 327 1182 95 62.4 MiB 0.02 0.00 1.2656 -31.3421 -1.2656 1.2656 0.33 0.00021091 0.000195761 0.00556254 0.00515097 -1 -1 -1 -1 32 513 11 6.89349e+06 70469.2 586450. 2029.24 1.13 0.043551 0.0365875 25474 144626 -1 494 8 166 166 12156 3163 0.89902 0.89902 -31.8409 -0.89902 0 0 744469. 2576.02 0.03 0.01 0.12 -1 -1 0.03 0.00491505 0.00433884 24 2 13 13 0 0 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Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64104 27 14 97 98 1 67 46 17 17 289 -1 unnamed_device 24.0 MiB 0.05 270 2506 503 1985 18 62.6 MiB 0.02 0.00 1.2876 -36.1111 -1.2876 1.2876 0.33 0.000242909 0.000225486 0.0080733 0.00749067 -1 -1 -1 -1 28 602 16 6.89349e+06 70469.2 531479. 1839.03 0.39 0.0346112 0.0297881 24610 126494 -1 545 14 296 296 16842 5312 1.15387 1.15387 -38.9299 -1.15387 0 0 648988. 2245.63 0.03 0.02 0.10 -1 -1 0.03 0.00750924 0.00650717 28 2 15 15 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 2.50 vpr 62.59 MiB 0.04 6692 -1 -1 1 0.02 -1 -1 30464 -1 -1 6 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 29 15 104 105 1 74 50 17 17 289 -1 unnamed_device 23.9 MiB 0.06 433 3454 892 2308 254 62.6 MiB 0.03 0.00 1.2986 -41.2946 -1.2986 1.2986 0.33 0.00025263 0.000234007 0.0102286 0.00945211 -1 -1 -1 -1 26 790 19 6.89349e+06 84563 503264. 1741.40 0.90 0.0691103 0.0585998 24322 120374 -1 761 9 290 290 20549 5463 0.97132 0.97132 -42.1866 -0.97132 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00604144 0.00534577 31 2 16 16 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 2.54 vpr 62.51 MiB 0.03 6712 -1 -1 1 0.02 -1 -1 30392 -1 -1 6 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64008 31 16 111 112 1 80 53 17 17 289 -1 unnamed_device 23.8 MiB 0.07 506 3518 755 2345 418 62.5 MiB 0.03 0.00 1.66993 -47.3509 -1.66993 1.66993 0.30 0.000271833 0.000252145 0.0103953 0.00964078 -1 -1 -1 -1 26 937 10 6.89349e+06 84563 503264. 1741.40 0.94 0.0703325 0.0597716 24322 120374 -1 856 10 288 288 21575 5335 1.06632 1.06632 -47.5744 -1.06632 0 0 618332. 2139.56 0.03 0.02 0.10 -1 -1 0.03 0.00672837 0.00590934 32 2 17 17 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 2.09 vpr 62.57 MiB 0.03 6812 -1 -1 1 0.02 -1 -1 30300 -1 -1 6 33 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64068 33 17 118 119 1 83 56 17 17 289 -1 unnamed_device 23.6 MiB 0.07 355 7118 2968 4031 119 62.6 MiB 0.05 0.00 1.68093 -46.6476 -1.68093 1.68093 0.33 0.000292539 0.000271644 0.02025 0.018783 -1 -1 -1 -1 32 742 16 6.89349e+06 84563 586450. 2029.24 0.44 0.0521433 0.045664 25474 144626 -1 627 13 345 345 22999 6204 1.12567 1.12567 -44.8602 -1.12567 0 0 744469. 2576.02 0.03 0.02 0.12 -1 -1 0.03 0.00839705 0.00729405 35 2 18 18 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 2.71 vpr 62.67 MiB 0.02 6692 -1 -1 1 0.02 -1 -1 30332 -1 -1 7 37 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64172 37 19 132 133 1 89 63 17 17 289 -1 unnamed_device 23.7 MiB 0.07 618 7313 2319 4209 785 62.7 MiB 0.05 0.00 1.70293 -59.1014 -1.70293 1.70293 0.33 0.000330355 0.000307328 0.0203419 0.018847 -1 -1 -1 -1 26 1056 18 6.89349e+06 98656.9 503264. 1741.40 0.96 0.0990559 0.0848204 24322 120374 -1 974 13 338 338 26941 6941 1.00507 1.00507 -56.0319 -1.00507 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.00939027 0.00815172 38 2 20 20 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 2.72 vpr 62.59 MiB 0.01 6612 -1 -1 1 0.02 -1 -1 30332 -1 -1 8 41 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64092 41 21 146 147 1 101 70 17 17 289 -1 unnamed_device 23.6 MiB 0.07 661 7846 2247 4897 702 62.6 MiB 0.05 0.00 1.72493 -65.1086 -1.72493 1.72493 0.33 0.000360281 0.000335234 0.020578 0.0191452 -1 -1 -1 -1 26 1172 14 6.89349e+06 112751 503264. 1741.40 0.96 0.0843787 0.0730066 24322 120374 -1 1083 11 383 383 31932 7864 1.04427 1.04427 -61.1172 -1.04427 0 0 618332. 2139.56 0.03 0.03 0.10 -1 -1 0.03 0.00897434 0.00786025 42 2 22 22 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 2.77 vpr 62.54 MiB 0.04 6692 -1 -1 1 0.02 -1 -1 30456 -1 -1 9 45 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64040 45 23 160 161 1 115 77 17 17 289 -1 unnamed_device 23.4 MiB 0.07 760 10020 3321 5690 1009 62.5 MiB 0.07 0.00 1.74693 -72.6551 -1.74693 1.74693 0.33 0.000391929 0.000364742 0.025148 0.0233979 -1 -1 -1 -1 28 1350 16 6.89349e+06 126845 531479. 1839.03 1.10 0.113977 0.098921 24610 126494 -1 1226 9 414 414 32996 8098 1.28387 1.28387 -71.8955 -1.28387 0 0 648988. 2245.63 0.03 0.03 0.10 -1 -1 0.03 0.00872835 0.00771702 47 2 24 24 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 2.70 vpr 62.80 MiB 0.02 6668 -1 -1 1 0.03 -1 -1 30380 -1 -1 9 49 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 49 25 174 175 1 124 83 17 17 289 -1 unnamed_device 23.9 MiB 0.08 809 9983 2879 5663 1441 62.8 MiB 0.07 0.00 2.12926 -80.2814 -2.12926 2.12926 0.33 0.000421866 0.000392654 0.0245734 0.0228767 -1 -1 -1 -1 30 1352 17 6.89349e+06 126845 556674. 1926.21 0.92 0.111078 0.0966581 25186 138497 -1 1223 10 398 398 27529 6709 1.10827 1.10827 -72.8896 -1.10827 0 0 706193. 2443.58 0.03 0.03 0.11 -1 -1 0.03 0.0100241 0.00886901 51 2 26 26 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 3.26 vpr 62.83 MiB 0.04 6812 -1 -1 1 0.03 -1 -1 30012 -1 -1 11 57 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 57 29 202 203 1 142 97 17 17 289 -1 unnamed_device 23.5 MiB 0.08 997 14527 5181 7993 1353 62.8 MiB 0.09 0.00 2.17326 -99.1204 -2.17326 2.17326 0.33 0.00048722 0.000453359 0.0331513 0.0308519 -1 -1 -1 -1 28 1682 13 6.89349e+06 155032 531479. 1839.03 1.35 0.141383 0.123982 24610 126494 -1 1549 13 587 587 48315 11675 1.14137 1.14137 -86.9212 -1.14137 0 0 648988. 2245.63 0.03 0.04 0.10 -1 -1 0.03 0.0133467 0.0117682 58 2 30 30 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 2.56 vpr 63.10 MiB 0.03 6584 -1 -1 1 0.03 -1 -1 30264 -1 -1 12 65 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 65 33 230 231 1 165 110 17 17 289 -1 unnamed_device 23.6 MiB 0.09 1136 15890 5118 9153 1619 63.1 MiB 0.10 0.00 2.57759 -117.501 -2.57759 2.57759 0.33 0.000568098 0.000530316 0.035727 0.0333474 -1 -1 -1 -1 32 1885 15 6.89349e+06 169126 586450. 2029.24 0.69 0.11053 0.0980873 25474 144626 -1 1735 13 637 637 57371 14126 1.35267 1.35267 -103.967 -1.35267 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0154282 0.013613 67 2 34 34 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 2.90 vpr 63.45 MiB 0.04 6712 -1 -1 1 0.03 -1 -1 30348 -1 -1 18 97 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64972 97 49 342 343 1 247 164 17 17 289 -1 unnamed_device 23.8 MiB 0.11 1589 34212 11441 20008 2763 63.4 MiB 0.21 0.00 3.47425 -191.764 -3.47425 3.47425 0.33 0.000867802 0.000813674 0.0684317 0.0641065 -1 -1 -1 -1 32 2773 23 6.89349e+06 253689 586450. 2029.24 0.85 0.216363 0.194841 25474 144626 -1 2491 16 873 873 69957 17320 1.44532 1.44532 -153.656 -1.44532 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0271503 0.0243172 99 2 50 50 0 0 + fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 3.32 vpr 63.73 MiB 0.02 6736 -1 -1 1 0.03 -1 -1 30372 -1 -1 24 129 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65256 129 65 454 455 1 329 218 17 17 289 -1 unnamed_device 24.4 MiB 0.13 2213 52618 20882 30344 1392 63.7 MiB 0.33 0.01 4.37092 -286.442 -4.37092 4.37092 0.33 0.0012033 0.001131 0.0996157 0.0936493 -1 -1 -1 -1 32 3862 23 6.89349e+06 338252 586450. 2029.24 1.06 0.296664 0.270031 25474 144626 -1 3389 12 1184 1184 101124 24774 1.64837 1.64837 -210.641 -1.64837 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0298483 0.0270215 131 2 66 66 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt index b09eed101d9..0581e25a8ca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -1,1025 +1,1025 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 5.22 vpr 63.83 MiB 0.03 7104 -1 -1 14 0.34 -1 -1 36588 -1 -1 26 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65364 32 32 280 312 1 203 90 17 17 289 -1 unnamed_device 25.0 MiB 0.26 1396 5718 1043 4241 434 63.8 MiB 0.05 0.00 8.33526 -166.471 -8.33526 8.33526 0.85 0.000298132 0.000238364 0.0117609 0.00981176 -1 -1 -1 -1 28 3716 42 6.55708e+06 313430 500653. 1732.36 1.65 0.0689479 0.0577638 21310 115450 -1 3004 21 1526 4795 248684 58174 7.4395 7.4395 -161.842 -7.4395 0 0 612192. 2118.31 0.23 0.07 0.10 -1 -1 0.23 0.0202595 0.017917 186 186 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 6.05 vpr 64.09 MiB 0.02 6952 -1 -1 14 0.37 -1 -1 36552 -1 -1 30 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65624 30 32 277 309 1 214 92 17 17 289 -1 unnamed_device 25.3 MiB 0.48 1292 9821 2314 6313 1194 64.1 MiB 0.07 0.00 7.97266 -161.847 -7.97266 7.97266 0.86 0.000279394 0.000221618 0.0166927 0.0134901 -1 -1 -1 -1 28 4133 49 6.55708e+06 361650 500653. 1732.36 1.94 0.0776588 0.0645059 21310 115450 -1 3143 20 1590 4541 279442 69927 7.1579 7.1579 -156.969 -7.1579 0 0 612192. 2118.31 0.54 0.07 0.11 -1 -1 0.54 0.0181305 0.0160094 189 189 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 7.42 vpr 64.04 MiB 0.02 6880 -1 -1 11 0.26 -1 -1 36548 -1 -1 25 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65572 32 32 274 306 1 208 89 17 17 289 -1 unnamed_device 25.3 MiB 0.40 1387 5633 1032 4013 588 64.0 MiB 0.05 0.00 6.70549 -144.379 -6.70549 6.70549 0.83 0.000279145 0.000222543 0.0107434 0.00891549 -1 -1 -1 -1 38 3367 24 6.55708e+06 301375 638502. 2209.35 3.88 0.124863 0.104095 23326 155178 -1 2938 15 1203 3923 204412 45867 5.90278 5.90278 -137.681 -5.90278 0 0 851065. 2944.86 0.30 0.06 0.12 -1 -1 0.30 0.0163744 0.0147263 180 180 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_004.v common 5.60 vpr 64.01 MiB 0.02 7068 -1 -1 12 0.42 -1 -1 36704 -1 -1 29 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65548 29 32 269 301 1 203 90 17 17 289 -1 unnamed_device 25.2 MiB 0.44 1235 6522 1332 4656 534 64.0 MiB 0.05 0.00 7.67294 -144.969 -7.67294 7.67294 0.83 0.000278308 0.000221884 0.0118876 0.00978677 -1 -1 -1 -1 32 3833 44 6.55708e+06 349595 554710. 1919.41 1.83 0.0860144 0.0720033 22174 131602 -1 3094 42 2072 6957 632362 219498 7.25558 7.25558 -144.225 -7.25558 0 0 701300. 2426.64 0.26 0.15 0.11 -1 -1 0.26 0.0286853 0.0246033 185 184 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_005.v common 5.92 vpr 63.16 MiB 0.02 6896 -1 -1 13 0.40 -1 -1 36720 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64680 32 32 317 349 1 246 95 17 17 289 -1 unnamed_device 24.4 MiB 0.45 1620 8303 2009 5589 705 63.2 MiB 0.07 0.00 7.84931 -165.878 -7.84931 7.84931 0.93 0.000321232 0.00025629 0.0164354 0.0135238 -1 -1 -1 -1 30 4081 45 6.55708e+06 373705 526063. 1820.29 1.84 0.0971766 0.0824286 21886 126133 -1 3417 31 2192 6994 649153 243609 6.9587 6.9587 -160.39 -6.9587 0 0 666494. 2306.21 0.26 0.16 0.11 -1 -1 0.26 0.028572 0.0249935 224 223 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 10.17 vpr 64.12 MiB 0.04 7008 -1 -1 12 0.34 -1 -1 36400 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65660 32 32 299 331 1 224 95 17 17 289 -1 unnamed_device 25.2 MiB 0.75 1415 13055 3582 8009 1464 64.1 MiB 0.09 0.00 7.00015 -146.985 -7.00015 7.00015 0.89 0.00031654 0.000247097 0.0221928 0.0178846 -1 -1 -1 -1 28 4777 41 6.55708e+06 373705 500653. 1732.36 5.70 0.160482 0.132999 21310 115450 -1 3425 17 1556 4990 279641 64342 6.22218 6.22218 -144.978 -6.22218 0 0 612192. 2118.31 0.34 0.07 0.24 -1 -1 0.34 0.0173854 0.0155007 206 205 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 6.18 vpr 63.48 MiB 0.02 6852 -1 -1 12 0.22 -1 -1 36320 -1 -1 27 27 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65000 27 32 210 242 1 165 86 17 17 289 -1 unnamed_device 24.7 MiB 0.44 974 6890 1587 4820 483 63.5 MiB 0.04 0.00 6.94984 -127.162 -6.94984 6.94984 0.84 0.000215012 0.000171308 0.0102381 0.00843267 -1 -1 -1 -1 28 2654 18 6.55708e+06 325485 500653. 1732.36 2.67 0.0775907 0.0646235 21310 115450 -1 2427 19 1010 2929 164353 38329 6.09998 6.09998 -124.429 -6.09998 0 0 612192. 2118.31 0.23 0.05 0.09 -1 -1 0.23 0.0129959 0.0114885 137 131 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 5.01 vpr 63.83 MiB 0.02 7092 -1 -1 11 0.22 -1 -1 36588 -1 -1 28 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65360 31 32 264 296 1 200 91 17 17 289 -1 unnamed_device 24.9 MiB 0.29 1315 7231 1531 4891 809 63.8 MiB 0.05 0.00 6.53897 -136.036 -6.53897 6.53897 0.84 0.000258039 0.000203995 0.0120496 0.00982378 -1 -1 -1 -1 30 3221 27 6.55708e+06 337540 526063. 1820.29 1.56 0.0697046 0.059383 21886 126133 -1 2714 16 1147 3840 187272 43051 5.50098 5.50098 -128.943 -5.50098 0 0 666494. 2306.21 0.28 0.06 0.11 -1 -1 0.28 0.0171813 0.0154819 175 173 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 8.07 vpr 63.88 MiB 0.02 6784 -1 -1 12 0.21 -1 -1 35732 -1 -1 25 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65412 31 32 234 266 1 190 88 17 17 289 -1 unnamed_device 24.9 MiB 0.40 1115 11203 2815 6442 1946 63.9 MiB 0.08 0.00 6.90263 -147 -6.90263 6.90263 0.90 0.000241734 0.000192658 0.0179692 0.0147247 -1 -1 -1 -1 30 2958 44 6.55708e+06 301375 526063. 1820.29 4.07 0.117929 0.098719 21886 126133 -1 2303 12 926 2399 117672 28295 6.17898 6.17898 -142.174 -6.17898 0 0 666494. 2306.21 0.55 0.04 0.13 -1 -1 0.55 0.0117269 0.010674 145 143 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_010.v common 5.40 vpr 63.82 MiB 0.02 6908 -1 -1 13 0.23 -1 -1 36480 -1 -1 25 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65356 32 32 253 285 1 194 89 17 17 289 -1 unnamed_device 25.0 MiB 0.56 1192 15137 4443 8200 2494 63.8 MiB 0.09 0.00 7.39554 -161.911 -7.39554 7.39554 0.89 0.000253042 0.000202028 0.0226291 0.0183277 -1 -1 -1 -1 30 3232 46 6.55708e+06 301375 526063. 1820.29 1.46 0.0802749 0.0670454 21886 126133 -1 2512 16 1069 2908 152436 34980 6.42904 6.42904 -155.481 -6.42904 0 0 666494. 2306.21 0.28 0.06 0.11 -1 -1 0.28 0.0189785 0.017127 162 159 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 6.55 vpr 63.38 MiB 0.02 6884 -1 -1 12 0.20 -1 -1 36556 -1 -1 22 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64900 30 32 217 249 1 169 84 17 17 289 -1 unnamed_device 24.6 MiB 0.45 1009 4842 919 3670 253 63.4 MiB 0.04 0.00 7.00015 -143.218 -7.00015 7.00015 0.87 0.000220011 0.000175717 0.00853566 0.00713455 -1 -1 -1 -1 26 2871 22 6.55708e+06 265210 477104. 1650.88 3.11 0.0900748 0.0760941 21022 109990 -1 2368 17 940 2361 135836 31778 6.06078 6.06078 -139.79 -6.06078 0 0 585099. 2024.56 0.25 0.04 0.09 -1 -1 0.25 0.0130152 0.0115551 132 129 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 7.24 vpr 63.75 MiB 0.02 6944 -1 -1 12 0.17 -1 -1 36084 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65280 32 32 227 259 1 176 85 17 17 289 -1 unnamed_device 24.9 MiB 0.24 1020 12547 3823 6487 2237 63.8 MiB 0.08 0.00 6.61272 -143.64 -6.61272 6.61272 0.84 0.000217803 0.000172726 0.0177674 0.0143939 -1 -1 -1 -1 30 2715 21 6.55708e+06 253155 526063. 1820.29 3.85 0.0933524 0.0779977 21886 126133 -1 2267 16 994 2621 133216 32040 5.61918 5.61918 -136.187 -5.61918 0 0 666494. 2306.21 0.26 0.04 0.11 -1 -1 0.26 0.0127213 0.0114209 138 133 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_013.v common 7.26 vpr 64.27 MiB 0.02 7056 -1 -1 13 0.33 -1 -1 37072 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 306 338 1 236 95 17 17 289 -1 unnamed_device 25.3 MiB 0.48 1509 7439 1652 5093 694 64.3 MiB 0.07 0.00 8.16384 -167.563 -8.16384 8.16384 0.88 0.000320998 0.000255221 0.0154697 0.0127613 -1 -1 -1 -1 32 3500 18 6.55708e+06 373705 554710. 1919.41 3.28 0.142958 0.11998 22174 131602 -1 3114 18 1384 4275 227959 52912 6.8823 6.8823 -154.863 -6.8823 0 0 701300. 2426.64 0.29 0.08 0.12 -1 -1 0.29 0.0228379 0.0205497 212 212 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_014.v common 12.34 vpr 64.51 MiB 0.02 7032 -1 -1 14 0.41 -1 -1 37004 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66060 32 32 302 334 1 235 93 17 17 289 -1 unnamed_device 25.5 MiB 0.52 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65484 32 32 259 291 1 202 91 17 17 289 -1 unnamed_device 25.0 MiB 0.29 1261 6619 1462 4468 689 63.9 MiB 0.05 0.00 7.87238 -161.512 -7.87238 7.87238 0.84 0.000258374 0.00020518 0.0110293 0.00907364 -1 -1 -1 -1 28 3782 22 6.55708e+06 325485 500653. 1732.36 1.41 0.0633755 0.0538763 21310 115450 -1 2987 36 1896 5422 530398 211567 6.74584 6.74584 -155.563 -6.74584 0 0 612192. 2118.31 0.26 0.16 0.10 -1 -1 0.26 0.0270705 0.0234281 167 165 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_115.v common 8.29 vpr 63.89 MiB 0.02 6992 -1 -1 13 0.32 -1 -1 36744 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65420 32 32 277 309 1 220 93 17 17 289 -1 unnamed_device 25.1 MiB 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Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65748 30 32 409 330 1 186 85 17 17 289 -1 unnamed_device 25.2 MiB 0.21 873 12919 4129 6395 2395 64.2 MiB 0.11 0.00 4.45516 -130.844 -4.45516 4.45516 0.89 0.000227213 0.000178692 0.0205306 0.016632 -1 -1 -1 -1 32 2188 21 6.64007e+06 288834 554710. 1919.41 0.97 0.0618261 0.0513815 22834 132086 -1 1899 23 1583 2754 164100 38700 3.84263 3.84263 -133.584 -3.84263 0 0 701300. 2426.64 0.30 0.06 0.13 -1 -1 0.30 0.0166886 0.0145581 142 91 30 30 89 30 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 4.12 vpr 64.32 MiB 0.02 7132 -1 -1 1 0.04 -1 -1 34196 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 387 309 1 186 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-1 26 2361 21 6.64007e+06 301392 477104. 1650.88 0.87 0.0530226 0.0443146 21682 110474 -1 1898 19 1382 2391 133144 31525 3.75363 3.75363 -131.002 -3.75363 0 0 585099. 2024.56 0.25 0.05 0.10 -1 -1 0.25 0.01433 0.0126017 138 34 87 29 29 29 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 4.16 vpr 64.22 MiB 0.02 7096 -1 -1 1 0.04 -1 -1 33828 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65764 32 32 376 288 1 195 86 17 17 289 -1 unnamed_device 25.3 MiB 0.15 849 15017 4515 8552 1950 64.2 MiB 0.13 0.00 4.14936 -139.21 -4.14936 4.14936 0.85 0.000243855 0.00019718 0.0213406 0.0171585 -1 -1 -1 -1 32 2158 19 6.64007e+06 276276 554710. 1919.41 0.93 0.0598378 0.0492011 22834 132086 -1 1883 23 1627 2940 175616 44084 3.50723 3.50723 -131.536 -3.50723 0 0 701300. 2426.64 0.29 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34368 -1 -1 20 27 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65300 27 32 269 226 1 135 79 17 17 289 -1 unnamed_device 24.8 MiB 0.12 536 12754 3285 8720 749 63.8 MiB 0.08 0.00 3.7877 -97.0533 -3.7877 3.7877 0.84 0.000161805 0.000127881 0.0142715 0.0115701 -1 -1 -1 -1 32 1263 20 6.64007e+06 251160 554710. 1919.41 0.99 0.0469307 0.0394295 22834 132086 -1 1040 20 890 1548 89627 21823 2.79977 2.79977 -89.8593 -2.79977 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0122122 0.0107845 97 34 54 27 27 27 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 4.34 vpr 64.30 MiB 0.02 7228 -1 -1 1 0.04 -1 -1 33624 -1 -1 34 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 317 242 1 185 97 17 17 289 -1 unnamed_device 25.4 MiB 0.14 948 16081 4441 8879 2761 64.3 MiB 0.12 0.00 3.49449 -109.504 -3.49449 3.49449 0.90 0.000233602 0.000187103 0.018421 0.0150374 -1 -1 -1 -1 28 2250 21 6.64007e+06 426972 500653. 1732.36 0.96 0.0538166 0.0450278 21970 115934 -1 1978 20 1191 1997 126595 29386 2.65357 2.65357 -104.975 -2.65357 0 0 612192. 2118.31 0.25 0.05 0.10 -1 -1 0.25 0.0139128 0.0120919 140 4 115 31 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 3.91 vpr 63.79 MiB 0.02 7108 -1 -1 1 0.03 -1 -1 34008 -1 -1 17 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65316 31 32 338 292 1 147 80 17 17 289 -1 unnamed_device 24.9 MiB 0.18 706 7820 1805 5417 598 63.8 MiB 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132086 -1 1778 22 1293 2043 128760 29112 2.85677 2.85677 -120.971 -2.85677 0 0 701300. 2426.64 0.31 0.05 0.12 -1 -1 0.31 0.0136456 0.0119649 121 34 64 32 32 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 4.29 vpr 63.91 MiB 0.02 7088 -1 -1 1 0.04 -1 -1 33784 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65448 30 32 325 273 1 151 80 17 17 289 -1 unnamed_device 25.0 MiB 0.18 822 14012 5060 7295 1657 63.9 MiB 0.10 0.00 3.4841 -115.834 -3.4841 3.4841 0.95 0.000216729 0.000174733 0.0187339 0.015216 -1 -1 -1 -1 28 1790 20 6.64007e+06 226044 500653. 1732.36 0.83 0.050825 0.0423282 21970 115934 -1 1551 18 1049 1513 95909 21865 2.76697 2.76697 -110.142 -2.76697 0 0 612192. 2118.31 0.26 0.04 0.10 -1 -1 0.26 0.0127133 0.0111761 110 63 30 30 60 30 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 386 305 1 188 98 17 17 289 -1 unnamed_device 25.3 MiB 0.21 893 19448 6133 10048 3267 64.3 MiB 0.16 0.00 3.56129 -122.026 -3.56129 3.56129 0.97 0.000249057 0.000200043 0.0238154 0.0191416 -1 -1 -1 -1 32 2126 22 6.64007e+06 426972 554710. 1919.41 1.00 0.0679577 0.0566976 22834 132086 -1 1768 20 1395 2386 143294 33441 2.87597 2.87597 -115.245 -2.87597 0 0 701300. 2426.64 0.30 0.05 0.14 -1 -1 0.30 0.0152489 0.0134 145 58 64 32 57 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 4.22 vpr 64.31 MiB 0.02 7232 -1 -1 1 0.04 -1 -1 34120 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66048 32 32 376 288 1 194 99 17 17 289 -1 unnamed_device 25.4 MiB 0.11 956 14691 4376 8904 1411 64.5 MiB 0.11 0.00 4.18856 -140.856 -4.18856 4.18856 0.87 0.000214277 0.000168514 0.0164732 0.0131539 -1 -1 -1 -1 32 2374 20 6.64007e+06 439530 554710. 1919.41 0.99 0.0570988 0.0477004 22834 132086 -1 2007 22 1606 2528 142742 34241 3.66543 3.66543 -137.36 -3.66543 0 0 701300. 2426.64 0.30 0.05 0.12 -1 -1 0.30 0.0163222 0.0143776 153 34 96 32 32 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 5.05 vpr 64.33 MiB 0.02 7024 -1 -1 1 0.04 -1 -1 34052 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 337 253 1 196 101 17 17 289 -1 unnamed_device 25.5 MiB 0.12 1019 8796 1857 6524 415 64.3 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65864 31 32 391 309 1 194 87 17 17 289 -1 unnamed_device 25.4 MiB 0.20 1058 10839 2803 6606 1430 64.3 MiB 0.09 0.00 3.4841 -118.469 -3.4841 3.4841 0.86 0.000221674 0.000175555 0.0145427 0.0117407 -1 -1 -1 -1 28 2547 22 6.64007e+06 301392 500653. 1732.36 0.90 0.0534732 0.0443312 21970 115934 -1 2220 21 1654 2736 175719 41104 3.11837 3.11837 -120.431 -3.11837 0 0 612192. 2118.31 0.27 0.06 0.10 -1 -1 0.27 0.01537 0.0133577 149 64 60 30 62 31 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 4.71 vpr 64.38 MiB 0.03 7248 -1 -1 1 0.05 -1 -1 34308 -1 -1 23 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65924 31 32 455 371 1 193 86 17 17 289 -1 unnamed_device 25.5 MiB 0.40 953 7835 1760 5704 371 64.4 MiB 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65528 31 32 305 250 1 158 81 17 17 289 -1 unnamed_device 25.2 MiB 0.14 655 13731 5030 6417 2284 64.0 MiB 0.09 0.00 3.7665 -117.146 -3.7665 3.7665 0.92 0.000186017 0.00014681 0.0168689 0.0135111 -1 -1 -1 -1 32 1675 22 6.64007e+06 226044 554710. 1919.41 0.92 0.0490117 0.0404927 22834 132086 -1 1426 19 1054 1688 97004 24503 2.74857 2.74857 -108.046 -2.74857 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0123819 0.0108236 116 34 62 31 31 31 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 4.38 vpr 64.52 MiB 0.02 7180 -1 -1 1 0.04 -1 -1 34092 -1 -1 38 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66068 31 32 395 311 1 196 101 17 17 289 -1 unnamed_device 25.7 MiB 0.15 910 7386 1527 5477 382 64.5 MiB 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65660 32 32 312 255 1 166 95 17 17 289 -1 unnamed_device 25.1 MiB 0.12 928 8735 1852 5986 897 64.1 MiB 0.06 0.00 3.50687 -122.364 -3.50687 3.50687 0.85 0.000201805 0.000161795 0.00962113 0.00787879 -1 -1 -1 -1 28 2268 21 6.64007e+06 389298 500653. 1732.36 0.88 0.0413011 0.0342616 21970 115934 -1 1966 19 1238 1976 126734 29630 3.00117 3.00117 -120.372 -3.00117 0 0 612192. 2118.31 0.27 0.04 0.10 -1 -1 0.27 0.0113774 0.00996614 125 34 63 32 32 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 4.25 vpr 64.13 MiB 0.02 7104 -1 -1 1 0.04 -1 -1 33876 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65672 32 32 370 314 1 164 82 17 17 289 -1 unnamed_device 25.4 MiB 0.20 885 10406 2864 6861 681 64.1 MiB 0.09 0.00 3.5031 -121.505 -3.5031 3.5031 0.92 0.000205124 0.000161668 0.0156831 0.012803 -1 -1 -1 -1 26 2176 22 6.64007e+06 226044 477104. 1650.88 0.87 0.0551054 0.0459777 21682 110474 -1 1889 21 1261 2024 140942 31764 3.17337 3.17337 -121.891 -3.17337 0 0 585099. 2024.56 0.26 0.05 0.11 -1 -1 0.26 0.0151839 0.0133115 121 94 0 0 94 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 4.31 vpr 63.74 MiB 0.03 7260 -1 -1 1 0.04 -1 -1 34180 -1 -1 42 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65272 32 32 469 351 1 233 106 17 17 289 -1 unnamed_device 25.0 MiB 0.14 1352 17606 4821 10688 2097 63.7 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65924 32 32 376 288 1 194 102 17 17 289 -1 unnamed_device 25.3 MiB 0.13 1027 16762 4357 10483 1922 64.4 MiB 0.12 0.00 4.27488 -146.847 -4.27488 4.27488 0.86 0.000231769 0.000184248 0.0180869 0.0143812 -1 -1 -1 -1 28 2732 21 6.64007e+06 477204 500653. 1732.36 0.91 0.0577514 0.0476383 21970 115934 -1 2262 19 1618 2382 151152 37456 3.85383 3.85383 -149.152 -3.85383 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.015425 0.0135776 153 34 96 32 32 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 4.05 vpr 64.03 MiB 0.02 6916 -1 -1 1 0.03 -1 -1 34024 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65564 32 32 283 225 1 164 96 17 17 289 -1 unnamed_device 25.1 MiB 0.08 882 11046 2802 6952 1292 64.0 MiB 0.09 0.00 3.5621 -124.172 -3.5621 3.5621 0.96 0.000189392 0.000150366 0.0118212 0.00960726 -1 -1 -1 -1 30 1789 19 6.64007e+06 401856 526063. 1820.29 0.87 0.0428872 0.0358449 22546 126617 -1 1527 18 784 1304 70997 17006 2.46797 2.46797 -107.154 -2.46797 0 0 666494. 2306.21 0.28 0.03 0.11 -1 -1 0.28 0.0111268 0.00982292 124 3 96 32 0 0 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 4.39 vpr 64.39 MiB 0.03 7068 -1 -1 1 0.04 -1 -1 34344 -1 -1 43 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65940 32 32 438 320 1 235 107 17 17 289 -1 unnamed_device 25.8 MiB 0.16 1334 20347 5362 13158 1827 64.4 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65912 32 32 407 319 1 194 86 17 17 289 -1 unnamed_device 25.6 MiB 0.17 937 11048 2797 7564 687 64.4 MiB 0.09 0.00 4.21976 -143.232 -4.21976 4.21976 0.87 0.000224116 0.000176908 0.0162198 0.0132135 -1 -1 -1 -1 32 2064 24 6.64007e+06 276276 554710. 1919.41 1.01 0.0601819 0.0504569 22834 132086 -1 1768 20 1585 2461 150379 34846 3.63243 3.63243 -140.901 -3.63243 0 0 701300. 2426.64 0.29 0.06 0.12 -1 -1 0.29 0.018671 0.0163887 152 65 64 32 64 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 4.35 vpr 64.34 MiB 0.02 7140 -1 -1 1 0.04 -1 -1 34284 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65884 32 32 407 319 1 195 100 17 17 289 -1 unnamed_device 25.6 MiB 0.26 1070 15876 4480 9346 2050 64.3 MiB 0.14 0.00 4.25856 -146.098 -4.25856 4.25856 0.86 0.000234164 0.000186199 0.0192536 0.0154407 -1 -1 -1 -1 32 2599 21 6.64007e+06 452088 554710. 1919.41 0.99 0.0600367 0.0497525 22834 132086 -1 2322 21 1600 2740 173936 39501 3.61523 3.61523 -141.653 -3.61523 0 0 701300. 2426.64 0.29 0.06 0.12 -1 -1 0.29 0.015469 0.0135641 154 65 64 32 64 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 4.36 vpr 64.02 MiB 0.02 6916 -1 -1 1 0.04 -1 -1 34200 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65552 32 32 345 287 1 161 96 17 17 289 -1 unnamed_device 25.0 MiB 0.15 863 8856 1892 6516 448 64.0 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65572 30 32 325 273 1 157 81 17 17 289 -1 unnamed_device 25.3 MiB 0.17 812 12506 4081 6359 2066 64.0 MiB 0.09 0.00 3.5343 -115.469 -3.5343 3.5343 0.87 0.000192273 0.000151488 0.0162237 0.0130458 -1 -1 -1 -1 32 1937 21 6.64007e+06 238602 554710. 1919.41 0.91 0.0503033 0.0412744 22834 132086 -1 1726 23 1277 2198 156154 33320 2.60657 2.60657 -105.956 -2.60657 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0144274 0.0124512 115 63 30 30 60 30 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 4.42 vpr 64.15 MiB 0.02 7072 -1 -1 1 0.04 -1 -1 33980 -1 -1 17 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65692 32 32 361 308 1 158 81 17 17 289 -1 unnamed_device 25.1 MiB 0.21 892 11281 2807 6986 1488 64.2 MiB 0.09 0.00 3.6865 -117.315 -3.6865 3.6865 1.00 0.000231686 0.000166095 0.0162594 0.0131115 -1 -1 -1 -1 30 1814 21 6.64007e+06 213486 526063. 1820.29 0.85 0.0531827 0.0438512 22546 126617 -1 1687 17 815 1359 86402 19223 2.67457 2.67457 -106.696 -2.67457 0 0 666494. 2306.21 0.28 0.04 0.11 -1 -1 0.28 0.0130339 0.0114756 114 91 0 0 91 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 4.41 vpr 64.18 MiB 0.03 7076 -1 -1 1 0.05 -1 -1 34084 -1 -1 37 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65720 31 32 335 251 1 196 100 17 17 289 -1 unnamed_device 25.3 MiB 0.11 1121 19124 6194 10224 2706 64.2 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65588 30 32 296 244 1 156 81 17 17 289 -1 unnamed_device 25.2 MiB 0.15 840 12856 4254 6466 2136 64.1 MiB 0.08 0.00 3.4921 -115.538 -3.4921 3.4921 0.85 0.000177735 0.000140207 0.0148918 0.0119814 -1 -1 -1 -1 32 1934 20 6.64007e+06 238602 554710. 1919.41 0.89 0.0448034 0.037139 22834 132086 -1 1742 21 1067 1755 114510 25571 2.86097 2.86097 -113.552 -2.86097 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.012042 0.0105224 113 34 60 30 30 30 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 4.42 vpr 64.37 MiB 0.02 7184 -1 -1 1 0.04 -1 -1 34140 -1 -1 24 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65916 30 32 383 303 1 191 86 17 17 289 -1 unnamed_device 25.4 MiB 0.23 996 13127 3599 7422 2106 64.4 MiB 0.10 0.00 4.20393 -135.69 -4.20393 4.20393 0.88 0.00027076 0.000224256 0.0185437 0.0151405 -1 -1 -1 -1 26 2442 22 6.64007e+06 301392 477104. 1650.88 1.03 0.0631652 0.0531875 21682 110474 -1 2103 20 1623 2452 154154 35629 3.91003 3.91003 -142.145 -3.91003 0 0 585099. 2024.56 0.25 0.06 0.10 -1 -1 0.25 0.0164675 0.0144506 146 63 60 30 60 30 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 4.63 vpr 64.98 MiB 0.02 7308 -1 -1 1 0.04 -1 -1 34508 -1 -1 41 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66544 32 32 469 381 1 198 105 17 17 289 -1 unnamed_device 25.8 MiB 0.24 1061 10232 2187 7405 640 65.0 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65884 29 32 387 316 1 179 97 17 17 289 -1 unnamed_device 25.4 MiB 0.18 964 18079 5198 10699 2182 64.3 MiB 0.12 0.00 3.5353 -109.347 -3.5353 3.5353 0.89 0.000211216 0.000166725 0.0198423 0.0157529 -1 -1 -1 -1 32 2001 18 6.64007e+06 452088 554710. 1919.41 0.95 0.0622356 0.0517002 22834 132086 -1 1793 18 1207 1991 113093 26929 2.78997 2.78997 -103.83 -2.78997 0 0 701300. 2426.64 0.33 0.05 0.12 -1 -1 0.33 0.0154254 0.013583 136 88 26 26 85 29 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 4.20 vpr 63.82 MiB 0.02 6864 -1 -1 1 0.04 -1 -1 33836 -1 -1 17 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65868 32 32 381 303 1 188 97 17 17 289 -1 unnamed_device 25.3 MiB 0.20 927 16303 4785 8793 2725 64.3 MiB 0.12 0.00 4.16476 -135.871 -4.16476 4.16476 0.86 0.000214425 0.000169547 0.0186242 0.0149077 -1 -1 -1 -1 32 2140 22 6.64007e+06 414414 554710. 1919.41 0.94 0.0578515 0.0477727 22834 132086 -1 1889 20 1256 1910 116840 27528 3.41802 3.41802 -125.912 -3.41802 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0157401 0.0137388 139 59 60 32 58 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 4.32 vpr 64.27 MiB 0.02 7348 -1 -1 1 0.04 -1 -1 34292 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 32 32 406 330 1 190 96 17 17 289 -1 unnamed_device 25.3 MiB 0.14 1051 17397 5163 9750 2484 64.3 MiB 0.13 0.00 4.41596 -136.112 -4.41596 4.41596 0.86 0.000231919 0.000184321 0.0204928 0.016475 -1 -1 -1 -1 26 2810 21 6.64007e+06 401856 477104. 1650.88 1.18 0.0640676 0.0533102 21682 110474 -1 2235 21 1299 2191 157955 34760 3.91883 3.91883 -135.985 -3.91883 0 0 585099. 2024.56 0.25 0.05 0.10 -1 -1 0.25 0.0148661 0.0129345 136 88 28 28 88 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 4.52 vpr 63.97 MiB 0.03 7192 -1 -1 1 0.04 -1 -1 34004 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 32 32 399 285 1 228 101 17 17 289 -1 unnamed_device 25.4 MiB 0.12 1159 10441 2545 7247 649 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65860 31 32 455 371 1 188 85 17 17 289 -1 unnamed_device 25.5 MiB 0.30 983 10501 2625 7195 681 64.3 MiB 0.09 0.00 4.43796 -139.728 -4.43796 4.43796 0.85 0.00023457 0.000184715 0.0160309 0.012969 -1 -1 -1 -1 32 2330 19 6.64007e+06 276276 554710. 1919.41 0.95 0.0563085 0.0465816 22834 132086 -1 2080 19 1285 2105 131522 30636 3.86303 3.86303 -142.801 -3.86303 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.015414 0.0134999 145 124 0 0 124 31 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 4.05 vpr 64.25 MiB 0.02 7148 -1 -1 1 0.03 -1 -1 33796 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65792 32 32 355 304 1 150 80 17 17 289 -1 unnamed_device 25.3 MiB 0.23 851 9540 2516 6274 750 64.2 MiB 0.07 0.00 3.72946 -115.235 -3.72946 3.72946 0.85 0.000199491 0.000156194 0.0128658 0.0103524 -1 -1 -1 -1 32 1856 20 6.64007e+06 200928 554710. 1919.41 0.87 0.0476618 0.0394235 22834 132086 -1 1679 16 644 994 63164 14955 2.68397 2.68397 -105.845 -2.68397 0 0 701300. 2426.64 0.30 0.03 0.12 -1 -1 0.30 0.0125449 0.0111185 109 89 0 0 89 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 4.45 vpr 64.20 MiB 0.02 7168 -1 -1 1 0.04 -1 -1 34168 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65736 32 32 364 282 1 196 97 17 17 289 -1 unnamed_device 25.2 MiB 0.12 1023 18745 6322 9498 2925 64.2 MiB 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66024 32 32 405 318 1 200 104 17 17 289 -1 unnamed_device 25.6 MiB 0.18 988 17184 5218 8807 3159 64.5 MiB 0.13 0.00 3.62559 -123.648 -3.62559 3.62559 0.85 0.000262181 0.000212009 0.0196698 0.0158139 -1 -1 -1 -1 28 2903 40 6.64007e+06 502320 500653. 1732.36 1.21 0.0678937 0.0560273 21970 115934 -1 2226 21 1439 2284 161332 37219 2.89997 2.89997 -117.754 -2.89997 0 0 612192. 2118.31 0.27 0.06 0.11 -1 -1 0.27 0.0155528 0.0135179 157 65 63 32 64 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 4.29 vpr 63.91 MiB 0.02 7172 -1 -1 1 0.04 -1 -1 34184 -1 -1 18 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65420 31 32 308 262 1 147 80 17 17 289 -1 unnamed_device 25.1 MiB 0.19 869 9368 2508 6076 784 63.9 MiB 0.07 0.00 3.34153 -105.882 -3.34153 3.34153 0.86 0.000229262 0.00019097 0.0116431 0.00942741 -1 -1 -1 -1 32 1866 23 6.64007e+06 213486 554710. 1919.41 0.90 0.0443576 0.0368834 22834 132086 -1 1656 18 876 1510 96218 21620 2.68277 2.68277 -105.301 -2.68277 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.01071 0.00932685 106 55 31 31 53 31 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 7.59 vpr 64.20 MiB 0.02 7084 -1 -1 1 0.04 -1 -1 34136 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65740 32 32 383 307 1 184 97 17 17 289 -1 unnamed_device 25.2 MiB 0.18 879 9865 2512 6573 780 64.2 MiB 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 29 32 367 293 1 183 95 17 17 289 -1 unnamed_device 25.3 MiB 0.16 1020 16079 4107 10319 1653 64.3 MiB 0.12 0.00 3.72052 -109.725 -3.72052 3.72052 0.87 0.00022959 0.000175625 0.0188595 0.0150887 -1 -1 -1 -1 32 2087 23 6.64007e+06 426972 554710. 1919.41 0.91 0.0585367 0.048494 22834 132086 -1 1904 18 1088 1735 96314 23271 2.84497 2.84497 -106.604 -2.84497 0 0 701300. 2426.64 0.32 0.04 0.12 -1 -1 0.32 0.0132667 0.0116569 135 62 56 29 58 29 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 4.33 vpr 64.45 MiB 0.02 7376 -1 -1 1 0.04 -1 -1 34168 -1 -1 39 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65992 32 32 469 381 1 200 103 17 17 289 -1 unnamed_device 25.5 MiB 0.26 937 9020 1835 6701 484 64.4 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65932 32 32 401 316 1 196 101 17 17 289 -1 unnamed_device 25.4 MiB 0.18 1060 9736 1961 7168 607 64.4 MiB 0.08 0.00 3.51212 -122.885 -3.51212 3.51212 0.88 0.000222726 0.000175722 0.0125685 0.0102996 -1 -1 -1 -1 26 2722 22 6.64007e+06 464646 477104. 1650.88 1.04 0.0605853 0.0511951 21682 110474 -1 2283 20 1346 1924 137623 31055 2.99937 2.99937 -123.86 -2.99937 0 0 585099. 2024.56 0.26 0.06 0.11 -1 -1 0.26 0.0190909 0.0169345 151 65 61 32 64 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 4.56 vpr 64.48 MiB 0.03 7320 -1 -1 1 0.04 -1 -1 34364 -1 -1 45 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66024 32 32 500 382 1 232 109 17 17 289 -1 unnamed_device 26.0 MiB 0.25 1244 16489 4012 10933 1544 64.5 MiB 0.14 0.00 4.96651 -168.366 -4.96651 4.96651 0.87 0.000288065 0.000229579 0.0224214 0.0182557 -1 -1 -1 -1 26 3331 25 6.64007e+06 565110 477104. 1650.88 1.07 0.0755519 0.0630738 21682 110474 -1 2710 22 2295 3724 240942 54867 4.68148 4.68148 -171.314 -4.68148 0 0 585099. 2024.56 0.26 0.08 0.10 -1 -1 0.26 0.0211128 0.018455 188 96 64 32 96 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 3.92 vpr 63.66 MiB 0.02 6848 -1 -1 1 0.03 -1 -1 33740 -1 -1 15 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65188 30 32 246 229 1 118 77 17 17 289 -1 unnamed_device 24.9 MiB 0.11 483 10509 2545 7262 702 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 432 346 1 193 86 17 17 289 -1 unnamed_device 25.7 MiB 0.20 1064 14828 5337 7470 2021 64.5 MiB 0.12 0.00 4.34676 -140.278 -4.34676 4.34676 0.88 0.000231141 0.000181034 0.0207891 0.0166439 -1 -1 -1 -1 32 2306 25 6.64007e+06 276276 554710. 1919.41 0.95 0.0644728 0.0530903 22834 132086 -1 1995 20 1368 2467 139291 32056 3.42803 3.42803 -133.215 -3.42803 0 0 701300. 2426.64 0.29 0.05 0.13 -1 -1 0.29 0.0162241 0.0141842 149 94 32 32 94 32 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 4.61 vpr 64.40 MiB 0.03 7172 -1 -1 1 0.05 -1 -1 34224 -1 -1 39 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65944 31 32 421 339 1 193 102 17 17 289 -1 unnamed_device 25.6 MiB 0.19 994 11288 2808 7770 710 64.4 MiB 0.09 0.00 3.54427 -117.284 -3.54427 3.54427 0.94 0.000230643 0.000181768 0.0139695 0.0112671 -1 -1 -1 -1 26 2483 22 6.64007e+06 489762 477104. 1650.88 1.12 0.0609049 0.0511219 21682 110474 -1 2174 19 1650 2620 154872 38837 3.11657 3.11657 -120.491 -3.11657 0 0 585099. 2024.56 0.26 0.06 0.10 -1 -1 0.26 0.0167739 0.0147592 148 94 29 29 93 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 4.45 vpr 64.03 MiB 0.02 7248 -1 -1 1 0.05 -1 -1 34496 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65568 32 32 438 350 1 194 98 17 17 289 -1 unnamed_device 25.4 MiB 0.15 984 7523 1506 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0.0142431 0.0124293 141 65 54 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 4.25 vpr 63.87 MiB 0.03 7224 -1 -1 1 0.03 -1 -1 33956 -1 -1 22 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65400 29 32 343 267 1 184 83 17 17 289 -1 unnamed_device 25.0 MiB 0.15 792 11963 2924 7039 2000 63.9 MiB 0.07 0.00 4.3057 -123.39 -4.3057 4.3057 0.86 0.000205469 0.00016254 0.0160257 0.0130239 -1 -1 -1 -1 32 2326 24 6.65987e+06 278916 554710. 1919.41 1.07 0.0542803 0.0450852 22834 132086 -1 1788 22 1543 2752 171817 43958 3.46431 3.46431 -122.506 -3.46431 0 0 701300. 2426.64 0.30 0.06 0.13 -1 -1 0.30 0.0155374 0.0135797 138 34 87 29 29 29 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 4.35 vpr 63.99 MiB 0.03 7124 -1 -1 1 0.04 -1 -1 34212 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 376 288 1 195 84 17 17 289 -1 unnamed_device 25.3 MiB 0.24 1026 15456 4961 8586 1909 64.0 MiB 0.12 0.00 4.14936 -143.085 -4.14936 4.14936 0.86 0.000222356 0.000176445 0.021947 0.0177341 -1 -1 -1 -1 32 2589 20 6.65987e+06 253560 554710. 1919.41 0.97 0.0609418 0.0506463 22834 132086 -1 2222 22 1680 3105 206991 47036 3.69143 3.69143 -143.37 -3.69143 0 0 701300. 2426.64 0.30 0.07 0.12 -1 -1 0.30 0.0172213 0.015149 151 34 96 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 4.49 vpr 64.23 MiB 0.02 7084 -1 -1 1 0.04 -1 -1 33844 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65768 32 32 402 316 1 199 101 17 17 289 -1 unnamed_device 25.4 MiB 0.23 1029 9501 1978 7135 388 64.2 MiB 0.09 0.00 3.43623 -117.882 -3.43623 3.43623 0.92 0.000233029 0.00018302 0.0120644 0.00985763 -1 -1 -1 -1 32 2342 20 6.65987e+06 469086 554710. 1919.41 0.95 0.0528538 0.0443739 22834 132086 -1 1962 18 1126 1792 107710 25832 2.72371 2.72371 -112.034 -2.72371 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0149223 0.013213 154 64 63 32 63 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 4.07 vpr 63.64 MiB 0.02 6904 -1 -1 1 0.03 -1 -1 33952 -1 -1 19 27 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65164 27 32 269 226 1 135 78 17 17 289 -1 unnamed_device 24.9 MiB 0.14 580 13026 4344 6329 2353 63.6 MiB 0.09 0.00 3.7565 -98.351 -3.7565 3.7565 0.97 0.00016047 0.000126685 0.0158445 0.0128417 -1 -1 -1 -1 30 1411 19 6.65987e+06 240882 526063. 1820.29 0.86 0.0445457 0.0369664 22546 126617 -1 1171 19 804 1373 82491 19526 2.70051 2.70051 -92.1985 -2.70051 0 0 666494. 2306.21 0.29 0.03 0.11 -1 -1 0.29 0.0110419 0.00972093 96 34 54 27 27 27 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 4.19 vpr 63.96 MiB 0.02 7032 -1 -1 1 0.03 -1 -1 34040 -1 -1 33 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65492 31 32 317 242 1 185 96 17 17 289 -1 unnamed_device 25.2 MiB 0.30 1016 11265 2888 7039 1338 64.0 MiB 0.09 0.00 3.36201 -108.145 -3.36201 3.36201 0.86 0.000196594 0.000156412 0.0129528 0.0105918 -1 -1 -1 -1 26 2532 27 6.65987e+06 418374 477104. 1650.88 1.00 0.0530519 0.0445537 21682 110474 -1 2233 18 1175 2022 139017 32170 2.74797 2.74797 -107.276 -2.74797 0 0 585099. 2024.56 0.26 0.05 0.10 -1 -1 0.26 0.0129167 0.0114214 139 4 115 31 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 4.06 vpr 64.00 MiB 0.02 7112 -1 -1 1 0.03 -1 -1 33884 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65540 31 32 338 292 1 147 79 17 17 289 -1 unnamed_device 25.3 MiB 0.28 818 11571 4275 5789 1507 64.0 MiB 0.08 0.00 3.08801 -101.656 -3.08801 3.08801 0.86 0.000194887 0.000152233 0.0157148 0.0125822 -1 -1 -1 -1 28 2012 20 6.65987e+06 202848 500653. 1732.36 0.89 0.0503903 0.0416852 21970 115934 -1 1768 19 888 1441 101867 23067 2.77365 2.77365 -102.085 -2.77365 0 0 612192. 2118.31 0.26 0.04 0.11 -1 -1 0.26 0.0132013 0.0115096 105 85 0 0 84 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 5.70 vpr 63.76 MiB 0.02 7048 -1 -1 1 0.04 -1 -1 33868 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65288 32 32 314 256 1 162 80 17 17 289 -1 unnamed_device 24.8 MiB 0.23 642 11432 4032 4649 2751 63.8 MiB 0.07 0.00 3.56921 -118.924 -3.56921 3.56921 0.89 0.000204221 0.000163325 0.0157006 0.0127499 -1 -1 -1 -1 36 2044 28 6.65987e+06 202848 612192. 2118.31 2.19 0.0902007 0.0764587 23410 145293 -1 1461 25 1464 2371 152631 38874 3.06097 3.06097 -111.701 -3.06097 0 0 782063. 2706.10 0.32 0.06 0.13 -1 -1 0.32 0.0154486 0.0133314 121 34 64 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 4.36 vpr 63.83 MiB 0.02 7032 -1 -1 1 0.04 -1 -1 33896 -1 -1 17 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65364 30 32 325 273 1 151 79 17 17 289 -1 unnamed_device 25.0 MiB 0.23 688 7684 1925 5205 554 63.8 MiB 0.07 0.00 3.53806 -112.993 -3.53806 3.53806 0.89 0.000199151 0.000157834 0.0114809 0.00944231 -1 -1 -1 -1 32 1563 20 6.65987e+06 215526 554710. 1919.41 0.91 0.048507 0.0408916 22834 132086 -1 1404 20 939 1333 81887 19635 2.76697 2.76697 -105.554 -2.76697 0 0 701300. 2426.64 0.31 0.04 0.12 -1 -1 0.31 0.0142186 0.0125318 110 63 30 30 60 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 4.12 vpr 64.06 MiB 0.02 7060 -1 -1 1 0.04 -1 -1 33892 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65600 32 32 331 280 1 156 93 17 17 289 -1 unnamed_device 25.3 MiB 0.27 841 11223 2602 8034 587 64.1 MiB 0.08 0.00 3.27957 -108.894 -3.27957 3.27957 0.88 0.000190398 0.000148882 0.0118571 0.00951992 -1 -1 -1 -1 30 2020 22 6.65987e+06 367662 526063. 1820.29 0.88 0.0460649 0.038006 22546 126617 -1 1668 22 1025 1665 104569 24167 2.50305 2.50305 -103.61 -2.50305 0 0 666494. 2306.21 0.28 0.04 0.12 -1 -1 0.28 0.0129487 0.0112801 114 65 25 25 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 4.38 vpr 64.01 MiB 0.02 7108 -1 -1 1 0.04 -1 -1 34084 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65544 32 32 386 305 1 188 96 17 17 289 -1 unnamed_device 25.3 MiB 0.40 1002 18711 5900 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1.03 0.0597878 0.0508458 22834 132086 -1 2106 22 1643 2700 178482 44548 3.66751 3.66751 -139.961 -3.66751 0 0 701300. 2426.64 0.29 0.07 0.12 -1 -1 0.29 0.0203484 0.0177778 156 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 4.27 vpr 63.52 MiB 0.02 6840 -1 -1 1 0.04 -1 -1 34020 -1 -1 18 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65048 29 32 272 228 1 145 79 17 17 289 -1 unnamed_device 24.8 MiB 0.25 686 7177 1709 4538 930 63.5 MiB 0.06 0.00 3.15358 -93.6229 -3.15358 3.15358 0.88 0.000173679 0.000137734 0.0100514 0.00828262 -1 -1 -1 -1 28 1892 19 6.65987e+06 228204 500653. 1732.36 0.87 0.0409682 0.0344969 21970 115934 -1 1647 23 1148 1915 132777 31641 2.65245 2.65245 -95.4509 -2.65245 0 0 612192. 2118.31 0.27 0.06 0.11 -1 -1 0.27 0.0157757 0.0138858 107 29 58 29 24 24 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 4.59 vpr 64.16 MiB 0.02 7272 -1 -1 1 0.04 -1 -1 33708 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65696 32 32 401 315 1 192 84 17 17 289 -1 unnamed_device 25.4 MiB 0.27 1074 13992 4161 7846 1985 64.2 MiB 0.12 0.00 3.5141 -125.301 -3.5141 3.5141 0.88 0.000272516 0.000214316 0.02221 0.0180216 -1 -1 -1 -1 32 2362 21 6.65987e+06 253560 554710. 1919.41 0.97 0.0647798 0.0539167 22834 132086 -1 2100 19 1387 2433 160863 37488 3.00917 3.00917 -120.058 -3.00917 0 0 701300. 2426.64 0.33 0.05 0.12 -1 -1 0.33 0.0164651 0.0145785 146 63 64 32 62 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 5.22 vpr 64.17 MiB 0.02 7252 -1 -1 1 0.04 -1 -1 34176 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65712 32 32 383 303 1 185 98 17 17 289 -1 unnamed_device 25.4 MiB 0.40 934 18323 6450 8556 3317 64.2 MiB 0.11 0.00 3.6343 -123.732 -3.6343 3.6343 0.86 0.000218734 0.000172517 0.0218129 0.0175926 -1 -1 -1 -1 30 2378 28 6.65987e+06 431052 526063. 1820.29 1.45 0.074348 0.0625194 22546 126617 -1 1916 19 1275 1888 125113 28979 2.76277 2.76277 -114.988 -2.76277 0 0 666494. 2306.21 0.28 0.05 0.12 -1 -1 0.28 0.0161028 0.0141349 142 57 64 32 56 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 4.54 vpr 64.10 MiB 0.02 7124 -1 -1 1 0.04 -1 -1 34144 -1 -1 30 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65636 32 32 339 284 1 162 94 17 17 289 -1 unnamed_device 25.3 MiB 0.32 832 15430 4777 8379 2274 64.1 MiB 0.13 0.00 2.83964 -101.659 -2.83964 2.83964 0.86 0.00028625 0.00022412 0.020992 0.0168723 -1 -1 -1 -1 30 1996 22 6.65987e+06 380340 526063. 1820.29 0.95 0.060009 0.0498959 22546 126617 -1 1635 14 802 1184 72625 16499 2.18971 2.18971 -96.9741 -2.18971 0 0 666494. 2306.21 0.29 0.04 0.12 -1 -1 0.29 0.0132388 0.0119215 118 65 29 29 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 3.75 vpr 63.32 MiB 0.02 6928 -1 -1 1 0.03 -1 -1 33756 -1 -1 15 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64836 30 32 226 208 1 119 77 17 17 289 -1 unnamed_device 24.8 MiB 0.10 661 10835 3152 6204 1479 63.3 MiB 0.06 0.00 2.60038 -85.2282 -2.60038 2.60038 0.86 0.000146349 0.000115364 0.0115561 0.00926061 -1 -1 -1 -1 28 1452 20 6.65987e+06 190170 500653. 1732.36 0.80 0.0360421 0.0297892 21970 115934 -1 1272 18 515 793 57249 13039 1.71265 1.71265 -76.7055 -1.71265 0 0 612192. 2118.31 0.25 0.03 0.11 -1 -1 0.25 0.00829805 0.00726069 85 34 24 24 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 4.39 vpr 63.92 MiB 0.02 7144 -1 -1 1 0.05 -1 -1 34172 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65452 31 32 335 280 1 154 79 17 17 289 -1 unnamed_device 25.2 MiB 0.14 862 13768 4646 7227 1895 63.9 MiB 0.09 0.00 3.94338 -122.441 -3.94338 3.94338 0.88 0.00021207 0.000168982 0.018332 0.0148478 -1 -1 -1 -1 32 1822 20 6.65987e+06 202848 554710. 1919.41 0.89 0.0533518 0.0444459 22834 132086 -1 1666 18 875 1353 101459 22409 2.91545 2.91545 -114.226 -2.91545 0 0 701300. 2426.64 0.31 0.04 0.12 -1 -1 0.31 0.0129711 0.0115155 113 64 31 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 4.50 vpr 64.01 MiB 0.02 7076 -1 -1 1 0.05 -1 -1 33524 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65548 32 32 366 283 1 192 98 17 17 289 -1 unnamed_device 25.0 MiB 0.23 1067 12248 3339 7850 1059 64.0 MiB 0.09 0.00 4.06436 -136.288 -4.06436 4.06436 0.88 0.000235554 0.000189371 0.014899 0.0122004 -1 -1 -1 -1 30 2353 19 6.65987e+06 431052 526063. 1820.29 0.92 0.0565076 0.0477459 22546 126617 -1 2038 20 1356 2011 119922 27360 3.22177 3.22177 -126.056 -3.22177 0 0 666494. 2306.21 0.29 0.05 0.11 -1 -1 0.29 0.0157327 0.0139328 145 34 91 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 4.35 vpr 64.25 MiB 0.02 7212 -1 -1 1 0.04 -1 -1 34632 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65796 32 32 460 375 1 196 100 17 17 289 -1 unnamed_device 25.8 MiB 0.33 1107 12164 3260 7320 1584 64.3 MiB 0.10 0.00 3.45103 -121.866 -3.45103 3.45103 0.86 0.00025615 0.000191433 0.0153242 0.0120164 -1 -1 -1 -1 32 2586 24 6.65987e+06 456408 554710. 1919.41 0.93 0.060485 0.0497648 22834 132086 -1 2228 18 1253 1902 113164 26704 3.01545 3.01545 -117.593 -3.01545 0 0 701300. 2426.64 0.29 0.06 0.12 -1 -1 0.29 0.0194744 0.0173037 149 124 0 0 125 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 3.83 vpr 62.89 MiB 0.02 6876 -1 -1 1 0.03 -1 -1 34076 -1 -1 17 26 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64404 26 32 198 186 1 109 75 17 17 289 -1 unnamed_device 24.4 MiB 0.19 410 10345 3142 6004 1199 62.9 MiB 0.04 0.00 2.61938 -68.655 -2.61938 2.61938 0.86 0.000125071 9.7591e-05 0.00937445 0.00750279 -1 -1 -1 -1 30 1071 20 6.65987e+06 215526 526063. 1820.29 0.80 0.0298943 0.0246568 22546 126617 -1 892 17 477 715 39145 10340 1.85405 1.85405 -64.8879 -1.85405 0 0 666494. 2306.21 0.28 0.02 0.11 -1 -1 0.28 0.00774252 0.00681641 77 30 26 26 22 22 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 6.50 vpr 63.80 MiB 0.02 7092 -1 -1 1 0.05 -1 -1 33904 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65332 32 32 333 251 1 187 84 17 17 289 -1 unnamed_device 24.9 MiB 0.23 1115 13443 3576 8165 1702 63.8 MiB 0.11 0.00 4.2335 -135.193 -4.2335 4.2335 1.02 0.00019936 0.000157616 0.0172239 0.0140116 -1 -1 -1 -1 28 2630 26 6.65987e+06 253560 500653. 1732.36 2.84 0.0959019 0.0796908 21970 115934 -1 2272 22 1473 2541 181143 40800 3.73177 3.73177 -136.785 -3.73177 0 0 612192. 2118.31 0.26 0.06 0.10 -1 -1 0.26 0.0151157 0.013274 137 3 122 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 3.78 vpr 63.01 MiB 0.02 6776 -1 -1 1 0.03 -1 -1 33852 -1 -1 13 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64524 32 32 199 182 1 122 77 17 17 289 -1 unnamed_device 24.3 MiB 0.10 594 7901 1809 5857 235 63.0 MiB 0.05 0.00 2.22607 -81.2607 -2.22607 2.22607 0.85 0.000135476 0.000106952 0.00801793 0.00648837 -1 -1 -1 -1 32 1389 15 6.65987e+06 164814 554710. 1919.41 0.84 0.0304616 0.0255145 22834 132086 -1 1233 16 549 735 54361 13016 1.93825 1.93825 -78.4309 -1.93825 0 0 701300. 2426.64 0.29 0.03 0.12 -1 -1 0.29 0.00807441 0.00716267 81 3 53 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 4.63 vpr 64.14 MiB 0.02 7120 -1 -1 1 0.04 -1 -1 34116 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65684 32 32 376 288 1 195 97 17 17 289 -1 unnamed_device 25.4 MiB 0.15 1065 18079 5979 9630 2470 64.1 MiB 0.15 0.00 4.06247 -139.199 -4.06247 4.06247 0.94 0.000237937 0.000191141 0.0228789 0.0186552 -1 -1 -1 -1 32 2367 20 6.65987e+06 418374 554710. 1919.41 1.00 0.0679986 0.0572457 22834 132086 -1 2074 22 1496 2206 146587 33354 3.39397 3.39397 -131.759 -3.39397 0 0 701300. 2426.64 0.28 0.05 0.12 -1 -1 0.28 0.0168664 0.0149314 152 34 96 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 4.16 vpr 64.14 MiB 0.02 6960 -1 -1 1 0.04 -1 -1 34208 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 337 253 1 196 99 17 17 289 -1 unnamed_device 25.2 MiB 0.22 1134 16059 4004 10217 1838 64.1 MiB 0.13 0.00 3.38184 -119.391 -3.38184 3.38184 0.87 0.000220735 0.000175379 0.0179557 0.0144782 -1 -1 -1 -1 30 2478 22 6.65987e+06 443730 526063. 1820.29 0.91 0.0553238 0.0460675 22546 126617 -1 2138 23 1418 2253 152856 33329 2.67931 2.67931 -115.639 -2.67931 0 0 666494. 2306.21 0.28 0.05 0.11 -1 -1 0.28 0.0152187 0.0132582 150 3 124 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 6.06 vpr 64.15 MiB 0.02 7076 -1 -1 1 0.04 -1 -1 33948 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65688 32 32 407 319 1 197 99 17 17 289 -1 unnamed_device 25.6 MiB 0.15 1118 17199 4898 10401 1900 64.1 MiB 0.13 0.00 3.91784 -137.067 -3.91784 3.91784 0.84 0.000233033 0.000185887 0.0198197 0.0158727 -1 -1 -1 -1 30 2570 27 6.65987e+06 443730 526063. 1820.29 2.93 0.106041 0.0868113 22546 126617 -1 2132 19 1575 2660 153360 35523 3.16231 3.16231 -129.907 -3.16231 0 0 666494. 2306.21 0.27 0.05 0.11 -1 -1 0.27 0.0148045 0.0130393 153 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 3.92 vpr 63.66 MiB 0.02 6928 -1 -1 1 0.03 -1 -1 33652 -1 -1 15 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65184 32 32 294 246 1 149 79 17 17 289 -1 unnamed_device 24.8 MiB 0.18 736 8191 2107 5347 737 63.7 MiB 0.06 0.00 2.8895 -100.047 -2.8895 2.8895 0.86 0.000176608 0.000139393 0.010168 0.00825419 -1 -1 -1 -1 28 2097 23 6.65987e+06 190170 500653. 1732.36 0.84 0.0417828 0.0348056 21970 115934 -1 1812 19 1072 1768 132294 30499 2.85491 2.85491 -104.569 -2.85491 0 0 612192. 2118.31 0.26 0.04 0.11 -1 -1 0.26 0.011401 0.0100046 106 34 54 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 4.02 vpr 63.67 MiB 0.02 7024 -1 -1 1 0.04 -1 -1 34040 -1 -1 19 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65200 30 32 296 244 1 154 81 17 17 289 -1 unnamed_device 24.8 MiB 0.15 832 12156 3666 7026 1464 63.7 MiB 0.08 0.00 3.4951 -115.55 -3.4951 3.4951 0.88 0.00017766 0.000139605 0.0145473 0.0117716 -1 -1 -1 -1 32 1812 18 6.65987e+06 240882 554710. 1919.41 0.90 0.0452634 0.0376541 22834 132086 -1 1637 24 948 1418 102648 23106 2.94997 2.94997 -112.088 -2.94997 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0132396 0.0115416 115 34 60 30 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 4.35 vpr 63.80 MiB 0.02 7136 -1 -1 1 0.04 -1 -1 33784 -1 -1 20 28 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65328 28 32 278 232 1 150 80 17 17 289 -1 unnamed_device 25.0 MiB 0.20 593 11776 2929 8189 658 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0.046107 22834 132086 -1 1631 20 1209 1890 125284 30035 2.73971 2.73971 -110.442 -2.73971 0 0 701300. 2426.64 0.30 0.05 0.13 -1 -1 0.30 0.0136135 0.0120325 125 3 96 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 4.43 vpr 63.84 MiB 0.02 7024 -1 -1 1 0.05 -1 -1 34132 -1 -1 31 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65372 31 32 303 249 1 162 94 17 17 289 -1 unnamed_device 24.9 MiB 0.19 735 8614 2125 5723 766 63.8 MiB 0.08 0.00 3.29178 -108.454 -3.29178 3.29178 0.92 0.000219705 0.000167933 0.0124794 0.0104425 -1 -1 -1 -1 28 2096 24 6.65987e+06 393018 500653. 1732.36 0.97 0.0553195 0.0471305 21970 115934 -1 1861 24 1396 2258 163291 38205 2.77565 2.77565 -108.842 -2.77565 0 0 612192. 2118.31 0.27 0.06 0.11 -1 -1 0.27 0.0154836 0.0134816 119 34 61 31 31 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 4.56 vpr 63.98 MiB 0.03 6952 -1 -1 1 0.04 -1 -1 33856 -1 -1 30 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65516 29 32 312 264 1 154 91 17 17 289 -1 unnamed_device 25.0 MiB 0.29 717 8047 1725 5786 536 64.0 MiB 0.07 0.00 2.76744 -86.2128 -2.76744 2.76744 0.92 0.000180985 0.000142457 0.0100526 0.00824251 -1 -1 -1 -1 32 1718 21 6.65987e+06 380340 554710. 1919.41 0.95 0.0456769 0.038576 22834 132086 -1 1480 18 839 1446 82236 20096 1.99625 1.99625 -81.928 -1.99625 0 0 701300. 2426.64 0.34 0.04 0.14 -1 -1 0.34 0.0138296 0.0121381 109 61 29 29 57 29 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_035.v common 6.55 vpr 64.14 MiB 0.03 7068 -1 -1 1 0.04 -1 -1 34152 -1 -1 39 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65684 32 32 423 310 1 229 103 17 17 289 -1 unnamed_device 25.6 MiB 0.38 1246 13117 3185 8526 1406 64.1 MiB 0.13 0.00 4.16036 -141.523 -4.16036 4.16036 0.86 0.000239798 0.000190496 0.0160078 0.0130221 -1 -1 -1 -1 28 3650 28 6.65987e+06 494442 500653. 1732.36 3.08 0.110543 0.0915706 21970 115934 -1 2889 22 2073 3566 281141 62285 3.86363 3.86363 -148.555 -3.86363 0 0 612192. 2118.31 0.26 0.08 0.10 -1 -1 0.26 0.0186994 0.0163891 179 29 128 32 27 27 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_036.v common 4.55 vpr 64.27 MiB 0.03 7160 -1 -1 1 0.04 -1 -1 34264 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65812 32 32 403 317 1 198 99 17 17 289 -1 unnamed_device 25.4 MiB 0.31 1041 9447 2232 6542 673 64.3 MiB 0.08 0.00 3.5061 -122.514 -3.5061 3.5061 0.88 0.000240141 0.000185736 0.0125694 0.010158 -1 -1 -1 -1 32 2288 19 6.65987e+06 443730 554710. 1919.41 0.94 0.0522072 0.0436475 22834 132086 -1 1994 21 1391 2140 124097 29585 2.77297 2.77297 -115.234 -2.77297 0 0 701300. 2426.64 0.30 0.05 0.13 -1 -1 0.30 0.0162666 0.0142913 152 65 62 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_037.v common 4.67 vpr 64.23 MiB 0.02 7172 -1 -1 1 0.04 -1 -1 34524 -1 -1 28 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65768 31 32 353 302 1 156 91 17 17 289 -1 unnamed_device 25.5 MiB 0.35 709 5599 957 4403 239 64.2 MiB 0.05 0.00 3.18838 -103.883 -3.18838 3.18838 0.89 0.000193365 0.000152611 0.0074812 0.00619347 -1 -1 -1 -1 26 2105 38 6.65987e+06 354984 477104. 1650.88 1.09 0.0499822 0.0417201 21682 110474 -1 1745 19 1012 1678 105217 25769 2.55939 2.55939 -102.816 -2.55939 0 0 585099. 2024.56 0.25 0.05 0.12 -1 -1 0.25 0.0146118 0.0129378 113 90 0 0 89 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 4.76 vpr 64.30 MiB 0.02 7324 -1 -1 1 0.06 -1 -1 33916 -1 -1 21 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 391 309 1 194 84 17 17 289 -1 unnamed_device 25.5 MiB 0.29 950 14541 4604 7502 2435 64.3 MiB 0.12 0.00 3.4921 -115.341 -3.4921 3.4921 0.94 0.000218513 0.000172546 0.0215484 0.0175215 -1 -1 -1 -1 32 2284 19 6.65987e+06 266238 554710. 1919.41 0.99 0.0643863 0.0538435 22834 132086 -1 1926 24 1607 2769 175988 39847 2.89577 2.89577 -113.543 -2.89577 0 0 701300. 2426.64 0.33 0.08 0.13 -1 -1 0.33 0.0231932 0.0205581 148 64 60 30 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 4.25 vpr 64.27 MiB 0.02 7372 -1 -1 1 0.04 -1 -1 34192 -1 -1 21 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65808 31 32 455 371 1 193 84 17 17 289 -1 unnamed_device 25.3 MiB 0.37 1075 7953 1851 5455 647 64.3 MiB 0.07 0.00 4.84238 -140.996 -4.84238 4.84238 0.86 0.000237949 0.000187108 0.0129485 0.0105657 -1 -1 -1 -1 30 2514 21 6.65987e+06 266238 526063. 1820.29 0.90 0.0558263 0.0463713 22546 126617 -1 2032 18 1004 1712 93766 22265 3.60671 3.60671 -132.535 -3.60671 0 0 666494. 2306.21 0.27 0.04 0.12 -1 -1 0.27 0.0155553 0.0136789 149 124 0 0 124 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 4.58 vpr 64.20 MiB 0.03 7360 -1 -1 1 0.04 -1 -1 34176 -1 -1 21 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65736 31 32 413 333 1 188 84 17 17 289 -1 unnamed_device 25.4 MiB 0.26 947 10332 2670 7099 563 64.2 MiB 0.09 0.00 4.78027 -132.754 -4.78027 4.78027 0.93 0.00023816 0.000188952 0.0164624 0.0135123 -1 -1 -1 -1 32 2150 18 6.65987e+06 266238 554710. 1919.41 0.90 0.0567469 0.0476182 22834 132086 -1 1930 19 1139 1864 120278 28305 3.69497 3.69497 -130.77 -3.69497 0 0 701300. 2426.64 0.29 0.05 0.15 -1 -1 0.29 0.0150248 0.0132065 143 90 31 31 89 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 4.64 vpr 64.31 MiB 0.03 7156 -1 -1 1 0.06 -1 -1 34028 -1 -1 33 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65852 31 32 391 309 1 193 96 17 17 289 -1 unnamed_device 25.5 MiB 0.30 995 11265 2756 7734 775 64.3 MiB 0.10 0.00 3.36361 -112.108 -3.36361 3.36361 0.86 0.000223451 0.000176788 0.0138665 0.0111909 -1 -1 -1 -1 32 2231 21 6.65987e+06 418374 554710. 1919.41 0.93 0.0535533 0.0445229 22834 132086 -1 2051 22 1429 2522 161477 37406 2.80191 2.80191 -109.124 -2.80191 0 0 701300. 2426.64 0.31 0.06 0.13 -1 -1 0.31 0.0200867 0.0178564 146 64 60 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 4.30 vpr 64.45 MiB 0.03 7084 -1 -1 1 0.04 -1 -1 34348 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66000 32 32 407 319 1 198 99 17 17 289 -1 unnamed_device 25.5 MiB 0.22 1091 9903 2241 6952 710 64.5 MiB 0.09 0.00 3.91784 -134.792 -3.91784 3.91784 0.85 0.000230603 0.000182409 0.0130468 0.0105336 -1 -1 -1 -1 30 2537 27 6.65987e+06 443730 526063. 1820.29 1.06 0.0560136 0.0466339 22546 126617 -1 2201 22 1649 2612 165739 37609 3.29771 3.29771 -131.299 -3.29771 0 0 666494. 2306.21 0.29 0.06 0.11 -1 -1 0.29 0.0162299 0.0141879 154 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 5.61 vpr 64.40 MiB 0.03 7436 -1 -1 1 0.06 -1 -1 33856 -1 -1 40 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65944 32 32 496 380 1 232 104 17 17 289 -1 unnamed_device 26.0 MiB 0.31 1184 18648 4691 11584 2373 64.4 MiB 0.18 0.00 4.06547 -137.623 -4.06547 4.06547 0.94 0.000290764 0.000232192 0.024197 0.0195494 -1 -1 -1 -1 34 2821 22 6.65987e+06 507120 585099. 2024.56 1.67 0.102929 0.0869897 23122 138558 -1 2347 19 1676 2732 179173 42035 3.71977 3.71977 -136.162 -3.71977 0 0 742403. 2568.87 0.31 0.06 0.12 -1 -1 0.31 0.0194582 0.0171595 184 96 62 32 96 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 4.13 vpr 63.97 MiB 0.02 6900 -1 -1 1 0.04 -1 -1 34076 -1 -1 18 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65508 31 32 305 250 1 158 81 17 17 289 -1 unnamed_device 25.0 MiB 0.23 685 11806 2914 7153 1739 64.0 MiB 0.08 0.00 3.55518 -111.493 -3.55518 3.55518 0.87 0.000188 0.000148625 0.0149034 0.0120671 -1 -1 -1 -1 32 1837 21 6.65987e+06 228204 554710. 1919.41 0.93 0.0484108 0.0402551 22834 132086 -1 1559 21 1192 1993 124706 29921 3.10705 3.10705 -109.722 -3.10705 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.0130355 0.0114709 116 34 62 31 31 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 4.90 vpr 63.46 MiB 0.02 7272 -1 -1 1 0.04 -1 -1 33820 -1 -1 36 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64980 31 32 395 311 1 196 99 17 17 289 -1 unnamed_device 24.6 MiB 0.21 975 9675 2183 7040 452 63.5 MiB 0.10 0.00 4.0281 -131.106 -4.0281 4.0281 0.97 0.000240279 0.000188018 0.0149648 0.0123429 -1 -1 -1 -1 26 2958 42 6.65987e+06 456408 477104. 1650.88 1.34 0.0756727 0.0642825 21682 110474 -1 2412 20 1578 2670 189219 43824 3.73577 3.73577 -138.183 -3.73577 0 0 585099. 2024.56 0.25 0.06 0.10 -1 -1 0.25 0.0161226 0.0142303 150 64 62 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 4.71 vpr 64.20 MiB 0.03 7168 -1 -1 1 0.04 -1 -1 34352 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65744 32 32 397 313 1 196 97 17 17 289 -1 unnamed_device 25.4 MiB 0.32 1040 11641 3109 7665 867 64.2 MiB 0.11 0.00 3.62624 -117.445 -3.62624 3.62624 0.97 0.000279853 0.000230454 0.0155215 0.0126195 -1 -1 -1 -1 28 2841 21 6.65987e+06 418374 500653. 1732.36 0.94 0.0555543 0.0462223 21970 115934 -1 2311 25 1614 2976 197433 45925 2.86271 2.86271 -111.815 -2.86271 0 0 612192. 2118.31 0.26 0.08 0.10 -1 -1 0.26 0.022325 0.0196621 148 63 62 32 62 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 4.72 vpr 64.01 MiB 0.02 7056 -1 -1 1 0.03 -1 -1 33972 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65544 32 32 345 257 1 194 84 17 17 289 -1 unnamed_device 25.1 MiB 0.22 853 8685 1897 5601 1187 64.0 MiB 0.07 0.00 4.14936 -138.467 -4.14936 4.14936 0.85 0.000217517 0.000172692 0.0128369 0.0104785 -1 -1 -1 -1 32 2947 27 6.65987e+06 253560 554710. 1919.41 1.52 0.06375 0.0530946 22834 132086 -1 2183 20 1697 3130 202299 50463 4.17937 4.17937 -151.011 -4.17937 0 0 701300. 2426.64 0.29 0.06 0.12 -1 -1 0.29 0.0155497 0.013763 150 3 128 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 4.27 vpr 64.19 MiB 0.03 7320 -1 -1 1 0.03 -1 -1 35408 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65728 32 32 424 343 1 190 98 17 17 289 -1 unnamed_device 25.3 MiB 0.37 1097 11798 3144 7589 1065 64.2 MiB 0.11 0.00 3.29555 -116.715 -3.29555 3.29555 0.84 0.000239341 0.000187499 0.0156126 0.0125119 -1 -1 -1 -1 32 2347 22 6.65987e+06 431052 554710. 1919.41 0.90 0.0552587 0.0456105 22834 132086 -1 2185 19 1263 1818 115545 27756 2.61645 2.61645 -112.838 -2.61645 0 0 701300. 2426.64 0.30 0.05 0.12 -1 -1 0.30 0.0154936 0.0136053 145 96 25 25 96 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 4.28 vpr 64.00 MiB 0.02 7080 -1 -1 1 0.04 -1 -1 33932 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65536 32 32 395 311 1 194 99 17 17 289 -1 unnamed_device 25.2 MiB 0.34 1042 7623 1446 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0.0169885 0.0150001 150 34 96 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 4.69 vpr 63.94 MiB 0.02 7156 -1 -1 1 0.04 -1 -1 34404 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65476 32 32 407 319 1 197 101 17 17 289 -1 unnamed_device 25.4 MiB 0.27 1025 18901 5265 11118 2518 63.9 MiB 0.15 0.00 3.95704 -138.682 -3.95704 3.95704 0.91 0.000237819 0.000186986 0.0238361 0.0191897 -1 -1 -1 -1 32 2290 23 6.65987e+06 469086 554710. 1919.41 1.03 0.0687873 0.0572488 22834 132086 -1 2103 23 1697 2639 176451 40256 3.38671 3.38671 -133.347 -3.38671 0 0 701300. 2426.64 0.31 0.06 0.13 -1 -1 0.31 0.0183719 0.016118 153 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 4.80 vpr 64.04 MiB 0.03 7268 -1 -1 1 0.05 -1 -1 34192 -1 -1 34 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65572 31 32 449 367 1 193 97 17 17 289 -1 unnamed_device 25.4 MiB 0.38 1075 12529 3319 7633 1577 64.0 MiB 0.12 0.00 3.98298 -125.763 -3.98298 3.98298 0.94 0.000263789 0.000205086 0.0207667 0.0169871 -1 -1 -1 -1 28 2875 24 6.65987e+06 431052 500653. 1732.36 1.03 0.0680779 0.0567205 21970 115934 -1 2454 21 1535 2576 174851 40840 3.55825 3.55825 -129.218 -3.55825 0 0 612192. 2118.31 0.26 0.06 0.11 -1 -1 0.26 0.0179787 0.0156959 145 122 0 0 122 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 4.34 vpr 64.15 MiB 0.02 7280 -1 -1 1 0.04 -1 -1 34168 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65688 32 32 432 346 1 195 84 17 17 289 -1 unnamed_device 25.2 MiB 0.28 1088 15822 4733 9518 1571 64.1 MiB 0.12 0.00 4.01118 -127.976 -4.01118 4.01118 0.86 0.000230879 0.000181222 0.0223147 0.0178722 -1 -1 -1 -1 32 2447 24 6.65987e+06 253560 554710. 1919.41 0.96 0.0664386 0.0547738 22834 132086 -1 2163 22 1707 3104 193742 43407 3.17765 3.17765 -121.359 -3.17765 0 0 701300. 2426.64 0.31 0.06 0.11 -1 -1 0.31 0.0172721 0.0150439 149 94 32 32 94 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 4.50 vpr 63.73 MiB 0.02 6868 -1 -1 1 0.04 -1 -1 33984 -1 -1 30 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65264 32 32 312 255 1 166 94 17 17 289 -1 unnamed_device 24.8 MiB 0.20 771 8827 2156 6189 482 63.7 MiB 0.07 0.00 3.35364 -111.63 -3.35364 3.35364 0.93 0.000208378 0.000162646 0.0107347 0.00884616 -1 -1 -1 -1 28 2265 24 6.65987e+06 380340 500653. 1732.36 0.99 0.0512892 0.0436202 21970 115934 -1 1988 24 1408 2241 175119 41581 2.87885 2.87885 -113.156 -2.87885 0 0 612192. 2118.31 0.26 0.08 0.11 -1 -1 0.26 0.0198981 0.017597 124 34 63 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 4.33 vpr 63.97 MiB 0.02 7000 -1 -1 1 0.04 -1 -1 34116 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65508 32 32 370 314 1 164 82 17 17 289 -1 unnamed_device 25.2 MiB 0.32 775 7914 1954 5542 418 64.0 MiB 0.06 0.00 3.38184 -115.147 -3.38184 3.38184 0.86 0.000203243 0.000160444 0.0110477 0.008959 -1 -1 -1 -1 32 1876 23 6.65987e+06 228204 554710. 1919.41 0.90 0.0472121 0.0390771 22834 132086 -1 1751 22 1235 1983 135410 30234 2.53731 2.53731 -107.925 -2.53731 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0157865 0.0138575 121 94 0 0 94 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 4.29 vpr 64.33 MiB 0.03 7156 -1 -1 1 0.04 -1 -1 34196 -1 -1 40 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65876 32 32 469 351 1 233 104 17 17 289 -1 unnamed_device 25.7 MiB 0.18 1358 14500 3674 9480 1346 64.3 MiB 0.14 0.00 4.6627 -160.408 -4.6627 4.6627 0.85 0.00029908 0.000212861 0.0201361 0.0162125 -1 -1 -1 -1 32 2828 20 6.65987e+06 507120 554710. 1919.41 0.98 0.0658264 0.0547301 22834 132086 -1 2592 20 2112 3449 200165 48304 4.13857 4.13857 -159.759 -4.13857 0 0 701300. 2426.64 0.30 0.06 0.11 -1 -1 0.30 0.0183217 0.0161196 187 65 96 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 4.72 vpr 64.27 MiB 0.03 7072 -1 -1 1 0.05 -1 -1 34176 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65812 32 32 368 284 1 194 95 17 17 289 -1 unnamed_device 25.5 MiB 0.31 954 14567 4735 7432 2400 64.3 MiB 0.12 0.00 3.51422 -121.562 -3.51422 3.51422 0.92 0.000224144 0.000176961 0.0190945 0.0155758 -1 -1 -1 -1 32 2355 23 6.65987e+06 393018 554710. 1919.41 1.02 0.0643413 0.0540318 22834 132086 -1 1996 20 1380 2125 138010 32355 2.94216 2.94216 -118.256 -2.94216 0 0 701300. 2426.64 0.30 0.05 0.13 -1 -1 0.30 0.0163025 0.0144465 146 34 92 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 4.08 vpr 64.00 MiB 0.02 6924 -1 -1 1 0.04 -1 -1 33800 -1 -1 30 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65536 30 32 296 244 1 158 92 17 17 289 -1 unnamed_device 24.9 MiB 0.19 839 17066 5534 9253 2279 64.0 MiB 0.11 0.00 3.49012 -114.14 -3.49012 3.49012 0.85 0.000180881 0.000144 0.0168054 0.0134939 -1 -1 -1 -1 32 1786 21 6.65987e+06 380340 554710. 1919.41 0.90 0.0479918 0.0398136 22834 132086 -1 1612 21 982 1572 108138 24890 2.66737 2.66737 -105.642 -2.66737 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.0120459 0.010547 115 34 60 30 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 4.97 vpr 64.62 MiB 0.03 7472 -1 -1 1 0.05 -1 -1 34480 -1 -1 43 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66168 32 32 531 413 1 232 107 17 17 289 -1 unnamed_device 26.1 MiB 0.57 1333 18829 5161 11634 2034 64.6 MiB 0.17 0.00 4.64147 -157.361 -4.64147 4.64147 0.89 0.000289058 0.000225857 0.0250218 0.0197806 -1 -1 -1 -1 30 2844 21 6.65987e+06 545154 526063. 1820.29 0.97 0.0777588 0.0644079 22546 126617 -1 2398 23 2018 3072 157660 37757 4.17037 4.17037 -158 -4.17037 0 0 666494. 2306.21 0.28 0.06 0.12 -1 -1 0.28 0.0214825 0.0188006 186 127 32 32 128 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 4.48 vpr 63.95 MiB 0.02 7200 -1 -1 1 0.04 -1 -1 33812 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65480 32 32 376 288 1 194 100 17 17 289 -1 unnamed_device 25.5 MiB 0.21 1044 16340 4500 10034 1806 63.9 MiB 0.12 0.00 4.15932 -143.209 -4.15932 4.15932 0.94 0.000227382 0.000181584 0.0180974 0.0146392 -1 -1 -1 -1 28 2434 23 6.65987e+06 456408 500653. 1732.36 0.94 0.0595807 0.0496523 21970 115934 -1 2212 21 1724 2576 175138 40284 3.49823 3.49823 -139.756 -3.49823 0 0 612192. 2118.31 0.26 0.06 0.10 -1 -1 0.26 0.0186107 0.016527 151 34 96 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 4.01 vpr 64.04 MiB 0.02 6912 -1 -1 1 0.04 -1 -1 34056 -1 -1 31 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65580 32 32 283 225 1 164 95 17 17 289 -1 unnamed_device 25.0 MiB 0.14 722 13055 3473 8103 1479 64.0 MiB 0.10 0.00 3.50687 -117.927 -3.50687 3.50687 0.87 0.000204996 0.000163902 0.0137235 0.0110272 -1 -1 -1 -1 28 2310 22 6.65987e+06 393018 500653. 1732.36 0.92 0.0475175 0.0395702 21970 115934 -1 1874 19 1249 1926 119722 30066 2.97077 2.97077 -121.563 -2.97077 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.0124692 0.0109595 123 3 96 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 4.84 vpr 64.14 MiB 0.03 7332 -1 -1 1 0.05 -1 -1 34392 -1 -1 41 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 32 32 438 320 1 235 105 17 17 289 -1 unnamed_device 25.5 MiB 0.26 1337 12702 3419 8223 1060 64.1 MiB 0.13 0.00 4.90437 -166.477 -4.90437 4.90437 0.93 0.000364548 0.000302208 0.0187206 0.0154481 -1 -1 -1 -1 30 3005 22 6.65987e+06 519798 526063. 1820.29 1.05 0.0671451 0.0565234 22546 126617 -1 2536 23 1897 3418 212452 47742 4.54303 4.54303 -164.492 -4.54303 0 0 666494. 2306.21 0.30 0.07 0.13 -1 -1 0.30 0.0194344 0.0170516 188 34 128 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 4.48 vpr 63.82 MiB 0.02 6744 -1 -1 1 0.04 -1 -1 33868 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65348 32 32 283 225 1 162 80 17 17 289 -1 unnamed_device 24.9 MiB 0.18 852 11260 3935 5447 1878 63.8 MiB 0.08 0.00 3.4749 -119.679 -3.4749 3.4749 0.95 0.000204384 0.000166857 0.0140302 0.0114205 -1 -1 -1 -1 32 2054 21 6.65987e+06 202848 554710. 1919.41 0.95 0.0482203 0.0405875 22834 132086 -1 1732 24 1316 2108 152415 36089 2.72571 2.72571 -112.904 -2.72571 0 0 701300. 2426.64 0.30 0.06 0.12 -1 -1 0.30 0.0157272 0.0139518 121 3 96 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 3.96 vpr 63.70 MiB 0.02 6972 -1 -1 1 0.04 -1 -1 33556 -1 -1 31 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65224 30 32 296 244 1 157 93 17 17 289 -1 unnamed_device 24.8 MiB 0.18 707 8073 1842 5622 609 63.7 MiB 0.07 0.00 3.47387 -110.471 -3.47387 3.47387 0.87 0.000185366 0.000147346 0.00897922 0.0073044 -1 -1 -1 -1 28 2018 21 6.65987e+06 393018 500653. 1732.36 0.87 0.0398835 0.0332487 21970 115934 -1 1690 19 1134 1899 121372 29545 2.89017 2.89017 -109.84 -2.89017 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.0126448 0.0111171 113 34 60 30 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 4.38 vpr 64.29 MiB 0.03 7304 -1 -1 1 0.04 -1 -1 34060 -1 -1 33 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65828 29 32 393 319 1 182 94 17 17 289 -1 unnamed_device 25.2 MiB 0.36 964 15856 4549 8713 2594 64.3 MiB 0.11 0.00 3.50895 -109.722 -3.50895 3.50895 0.86 0.000215153 0.000170439 0.0186278 0.0149426 -1 -1 -1 -1 30 1987 21 6.65987e+06 418374 526063. 1820.29 0.86 0.0565959 0.0467885 22546 126617 -1 1675 18 1050 1751 89648 21297 2.54417 2.54417 -99.3535 -2.54417 0 0 666494. 2306.21 0.31 0.05 0.12 -1 -1 0.31 0.0162979 0.0143824 133 88 29 29 85 29 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 4.65 vpr 64.19 MiB 0.02 7076 -1 -1 1 0.05 -1 -1 34224 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65732 32 32 407 319 1 194 84 17 17 289 -1 unnamed_device 25.4 MiB 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0.29 0.014387 0.0125029 120 65 32 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 4.31 vpr 63.97 MiB 0.02 7032 -1 -1 1 0.04 -1 -1 34188 -1 -1 17 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 31 32 353 302 1 152 80 17 17 289 -1 unnamed_device 25.3 MiB 0.32 800 12464 4445 5613 2406 64.0 MiB 0.09 0.00 3.46898 -107.215 -3.46898 3.46898 0.89 0.00019997 0.000156691 0.0170875 0.013651 -1 -1 -1 -1 32 1807 19 6.65987e+06 215526 554710. 1919.41 0.91 0.0510589 0.0422033 22834 132086 -1 1612 21 941 1768 104618 25029 2.51805 2.51805 -100.388 -2.51805 0 0 701300. 2426.64 0.31 0.04 0.12 -1 -1 0.31 0.0133321 0.0116015 109 90 0 0 89 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 4.50 vpr 64.06 MiB 0.02 7200 -1 -1 1 0.04 -1 -1 33940 -1 -1 33 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65600 30 32 374 297 1 186 95 17 17 289 -1 unnamed_device 25.0 MiB 0.30 998 10463 2754 7099 610 64.1 MiB 0.09 0.00 3.41496 -111.837 -3.41496 3.41496 0.94 0.000213302 0.000170101 0.0129597 0.0105604 -1 -1 -1 -1 26 2353 22 6.65987e+06 418374 477104. 1650.88 0.96 0.0546171 0.045868 21682 110474 -1 2029 17 1123 1957 131265 30894 2.71545 2.71545 -108.984 -2.71545 0 0 585099. 2024.56 0.26 0.05 0.11 -1 -1 0.26 0.0141206 0.0125491 137 60 60 30 57 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 4.45 vpr 63.79 MiB 0.02 7108 -1 -1 1 0.04 -1 -1 34084 -1 -1 31 28 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65316 28 32 332 260 1 180 91 17 17 289 -1 unnamed_device 24.9 MiB 0.21 995 16207 5283 8775 2149 63.8 MiB 0.13 0.00 4.24344 -123.397 -4.24344 4.24344 0.94 0.000193242 0.000152952 0.0192057 0.015567 -1 -1 -1 -1 28 2452 19 6.65987e+06 393018 500653. 1732.36 0.95 0.0561114 0.0469721 21970 115934 -1 2053 21 1498 2513 164181 38572 3.61111 3.61111 -125.602 -3.61111 0 0 612192. 2118.31 0.27 0.05 0.12 -1 -1 0.27 0.0142277 0.0125585 133 34 84 28 28 28 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 4.05 vpr 63.76 MiB 0.02 6984 -1 -1 1 0.04 -1 -1 33920 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65288 30 32 325 273 1 157 80 17 17 289 -1 unnamed_device 25.1 MiB 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0.014366 0.01275 150 4 124 31 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 4.93 vpr 64.34 MiB 0.03 7188 -1 -1 1 0.04 -1 -1 34348 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 407 319 1 197 98 17 17 289 -1 unnamed_device 25.4 MiB 0.31 1037 13598 4125 8601 872 64.3 MiB 0.12 0.00 4.1263 -141.609 -4.1263 4.1263 0.92 0.000250062 0.000198811 0.0176691 0.0142417 -1 -1 -1 -1 26 2960 37 6.65987e+06 431052 477104. 1650.88 1.25 0.0779238 0.0658367 21682 110474 -1 2249 22 1692 3000 199861 46709 3.59517 3.59517 -140.665 -3.59517 0 0 585099. 2024.56 0.25 0.06 0.11 -1 -1 0.25 0.0178305 0.0156392 153 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 4.68 vpr 64.21 MiB 0.03 7304 -1 -1 1 0.04 -1 -1 33872 -1 -1 34 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65752 32 32 407 319 1 194 98 17 17 289 -1 unnamed_device 25.3 MiB 0.23 1033 10448 2380 7653 415 64.2 MiB 0.10 0.00 4.16458 -142.258 -4.16458 4.16458 0.88 0.000227579 0.000180213 0.0136564 0.0109757 -1 -1 -1 -1 28 2950 23 6.65987e+06 431052 500653. 1732.36 1.23 0.0616907 0.0516743 21970 115934 -1 2366 14 1336 2203 163664 38169 3.67477 3.67477 -147.386 -3.67477 0 0 612192. 2118.31 0.28 0.05 0.11 -1 -1 0.28 0.0135227 0.0121468 151 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 4.29 vpr 63.89 MiB 0.02 7244 -1 -1 1 0.04 -1 -1 33988 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65420 32 32 399 315 1 196 101 17 17 289 -1 unnamed_device 25.3 MiB 0.35 982 9031 1878 6401 752 63.9 MiB 0.08 0.00 3.86706 -126.941 -3.86706 3.86706 0.85 0.000223285 0.00017658 0.0110086 0.00892723 -1 -1 -1 -1 30 2516 24 6.65987e+06 469086 526063. 1820.29 0.97 0.0527037 0.0439763 22546 126617 -1 2125 20 1264 2174 119793 28949 3.29571 3.29571 -124.191 -3.29571 0 0 666494. 2306.21 0.27 0.05 0.12 -1 -1 0.27 0.0151636 0.0133061 148 65 60 30 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 4.55 vpr 63.67 MiB 0.02 7004 -1 -1 1 0.04 -1 -1 34100 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65196 30 32 296 244 1 156 80 17 17 289 -1 unnamed_device 24.8 MiB 0.31 698 7992 1870 5622 500 63.7 MiB 0.06 0.00 3.50927 -110.859 -3.50927 3.50927 0.90 0.000184222 0.00014674 0.010644 0.00873391 -1 -1 -1 -1 32 1861 17 6.65987e+06 228204 554710. 1919.41 0.97 0.0430998 0.0363375 22834 132086 -1 1458 20 905 1434 81381 21081 2.75597 2.75597 -105.004 -2.75597 0 0 701300. 2426.64 0.31 0.04 0.14 -1 -1 0.31 0.0144868 0.0128538 112 34 60 30 30 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 4.17 vpr 64.49 MiB 0.02 7112 -1 -1 1 0.04 -1 -1 34032 -1 -1 22 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66040 30 32 383 303 1 191 84 17 17 289 -1 unnamed_device 25.4 MiB 0.28 985 11796 3468 7405 923 64.5 MiB 0.11 0.00 4.19776 -134.529 -4.19776 4.19776 0.85 0.000230315 0.000182359 0.0172369 0.0139425 -1 -1 -1 -1 32 2009 21 6.65987e+06 278916 554710. 1919.41 0.90 0.0557442 0.0462361 22834 132086 -1 1752 20 1321 1969 105280 25542 3.56043 3.56043 -130.097 -3.56043 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.015448 0.0136244 145 63 60 30 60 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 4.63 vpr 64.05 MiB 0.02 7372 -1 -1 1 0.04 -1 -1 34400 -1 -1 39 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 32 32 469 381 1 198 103 17 17 289 -1 unnamed_device 25.6 MiB 0.24 1052 13117 2855 8842 1420 64.1 MiB 0.10 0.00 3.91498 -132.986 -3.91498 3.91498 0.94 0.000259669 0.00020629 0.0167786 0.013628 -1 -1 -1 -1 32 2453 22 6.65987e+06 494442 554710. 1919.41 0.98 0.0608658 0.0505698 22834 132086 -1 2157 22 1790 2994 187896 45084 3.62605 3.62605 -137.441 -3.62605 0 0 701300. 2426.64 0.30 0.06 0.13 -1 -1 0.30 0.0179191 0.0155926 154 127 0 0 128 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 4.72 vpr 63.97 MiB 0.02 7220 -1 -1 1 0.04 -1 -1 34316 -1 -1 31 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65504 31 32 425 341 1 189 94 17 17 289 -1 unnamed_device 25.4 MiB 0.16 1050 9679 2438 6769 472 64.0 MiB 0.09 0.00 3.91106 -131.382 -3.91106 3.91106 0.88 0.000427902 0.000363857 0.0153748 0.0126998 -1 -1 -1 -1 26 2853 26 6.65987e+06 393018 477104. 1650.88 1.25 0.0637988 0.0536406 21682 110474 -1 2216 22 1545 2682 190227 44085 3.91691 3.91691 -140.392 -3.91691 0 0 585099. 2024.56 0.26 0.06 0.10 -1 -1 0.26 0.0169902 0.0148516 146 94 31 31 93 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 4.57 vpr 64.14 MiB 0.03 7352 -1 -1 1 0.06 -1 -1 34172 -1 -1 30 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65680 30 32 404 328 1 182 92 17 17 289 -1 unnamed_device 25.4 MiB 0.29 992 11063 2679 7283 1101 64.1 MiB 0.09 0.00 3.74723 -113.498 -3.74723 3.74723 0.91 0.00021966 0.000173512 0.0141335 0.0114634 -1 -1 -1 -1 28 2320 21 6.65987e+06 380340 500653. 1732.36 0.88 0.0559482 0.0468534 21970 115934 -1 1911 18 1016 1843 106397 26846 3.08637 3.08637 -110.967 -3.08637 0 0 612192. 2118.31 0.26 0.05 0.11 -1 -1 0.26 0.0158639 0.0140921 136 92 26 26 90 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 4.90 vpr 64.11 MiB 0.02 7132 -1 -1 1 0.05 -1 -1 34024 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65644 32 32 407 319 1 198 85 17 17 289 -1 unnamed_device 25.3 MiB 0.39 1074 13477 4127 7567 1783 64.1 MiB 0.12 0.00 4.06547 -141.302 -4.06547 4.06547 1.00 0.000228597 0.000180904 0.0201545 0.0164508 -1 -1 -1 -1 32 2517 20 6.65987e+06 266238 554710. 1919.41 0.96 0.0598829 0.0497928 22834 132086 -1 2263 21 1834 3159 192050 44920 3.36097 3.36097 -134.209 -3.36097 0 0 701300. 2426.64 0.34 0.07 0.12 -1 -1 0.34 0.0181254 0.0160363 154 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 4.14 vpr 64.09 MiB 0.02 7372 -1 -1 1 0.03 -1 -1 34084 -1 -1 34 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65628 29 32 387 316 1 179 95 17 17 289 -1 unnamed_device 25.1 MiB 0.25 874 10895 2930 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0.0432357 0.0361987 22834 132086 -1 1754 22 1114 1735 125414 29154 2.86777 2.86777 -118.356 -2.86777 0 0 701300. 2426.64 0.29 0.05 0.11 -1 -1 0.29 0.0135667 0.0119384 117 3 96 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 5.04 vpr 63.94 MiB 0.03 7012 -1 -1 1 0.04 -1 -1 33880 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65472 32 32 407 319 1 194 97 17 17 289 -1 unnamed_device 25.5 MiB 0.41 1015 16525 5345 8784 2396 63.9 MiB 0.13 0.00 4.18856 -142.192 -4.18856 4.18856 1.03 0.000234025 0.000184401 0.021043 0.0171308 -1 -1 -1 -1 32 2391 18 6.65987e+06 418374 554710. 1919.41 0.97 0.061095 0.0511326 22834 132086 -1 1935 22 1491 2315 154663 35170 3.56843 3.56843 -134.747 -3.56843 0 0 701300. 2426.64 0.32 0.06 0.14 -1 -1 0.32 0.0188209 0.0165247 150 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 4.26 vpr 64.34 MiB 0.02 7044 -1 -1 1 0.03 -1 -1 34012 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65880 32 32 407 319 1 201 85 17 17 289 -1 unnamed_device 25.4 MiB 0.30 1026 16081 4881 8736 2464 64.3 MiB 0.12 0.00 4.23393 -146.239 -4.23393 4.23393 0.85 0.000227134 0.000178885 0.0222291 0.0178092 -1 -1 -1 -1 32 2423 20 6.65987e+06 266238 554710. 1919.41 0.94 0.0621139 0.0513255 22834 132086 -1 2088 20 1618 2397 158021 36521 3.54323 3.54323 -139.034 -3.54323 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0166336 0.0146456 157 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 4.81 vpr 63.68 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 34116 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65204 32 32 315 267 1 158 93 17 17 289 -1 unnamed_device 24.8 MiB 0.25 688 16683 5557 7719 3407 63.7 MiB 0.10 0.00 3.44878 -105.048 -3.44878 3.44878 0.96 0.000192075 0.000150792 0.0183431 0.0147613 -1 -1 -1 -1 32 2061 28 6.65987e+06 367662 554710. 1919.41 1.10 0.0603129 0.0504057 22834 132086 -1 1604 22 1074 1599 128090 35387 2.74465 2.74465 -99.8729 -2.74465 0 0 701300. 2426.64 0.31 0.05 0.12 -1 -1 0.31 0.0149201 0.013139 111 55 32 32 54 27 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 4.32 vpr 63.91 MiB 0.02 6932 -1 -1 1 0.04 -1 -1 33900 -1 -1 18 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65448 31 32 275 220 1 160 81 17 17 289 -1 unnamed_device 25.1 MiB 0.21 720 9356 2387 5915 1054 63.9 MiB 0.08 0.00 3.4529 -113.153 -3.4529 3.4529 0.88 0.000182473 0.000145676 0.0118602 0.00971275 -1 -1 -1 -1 30 1921 19 6.65987e+06 228204 526063. 1820.29 0.92 0.0444613 0.037458 22546 126617 -1 1653 19 1135 1847 109681 25398 2.89017 2.89017 -110.427 -2.89017 0 0 666494. 2306.21 0.28 0.04 0.12 -1 -1 0.28 0.0128444 0.011367 118 4 93 31 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 6.30 vpr 64.00 MiB 0.02 7244 -1 -1 1 0.04 -1 -1 33892 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65536 32 32 381 303 1 188 96 17 17 289 -1 unnamed_device 25.0 MiB 0.38 913 5790 1032 4561 197 64.0 MiB 0.05 0.00 3.91316 -128.563 -3.91316 3.91316 0.85 0.000214525 0.000169549 0.00777021 0.0064358 -1 -1 -1 -1 26 2646 37 6.65987e+06 405696 477104. 1650.88 3.03 0.0950528 0.0790268 21682 110474 -1 2100 23 1573 2374 154692 36908 3.58831 3.58831 -133.102 -3.58831 0 0 585099. 2024.56 0.25 0.06 0.10 -1 -1 0.25 0.0169989 0.0146948 138 59 60 32 58 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 4.88 vpr 64.11 MiB 0.03 7320 -1 -1 1 0.04 -1 -1 33752 -1 -1 30 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65652 32 32 406 330 1 190 94 17 17 289 -1 unnamed_device 25.3 MiB 0.15 879 9892 2434 7009 449 64.1 MiB 0.10 0.00 4.11224 -123.302 -4.11224 4.11224 0.86 0.000321479 0.000268756 0.0144725 0.0118283 -1 -1 -1 -1 28 2708 31 6.65987e+06 380340 500653. 1732.36 1.43 0.0751404 0.0641647 21970 115934 -1 2190 24 1517 2512 179886 43994 3.75965 3.75965 -131.439 -3.75965 0 0 612192. 2118.31 0.26 0.06 0.11 -1 -1 0.26 0.0187983 0.0164705 134 88 28 28 88 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 4.56 vpr 64.03 MiB 0.03 7284 -1 -1 1 0.05 -1 -1 34032 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65564 32 32 399 285 1 228 99 17 17 289 -1 unnamed_device 25.6 MiB 0.22 1247 19251 5678 10972 2601 64.0 MiB 0.17 0.00 4.78976 -159.687 -4.78976 4.78976 0.86 0.000238781 0.000190561 0.0250133 0.0203764 -1 -1 -1 -1 32 2872 20 6.65987e+06 443730 554710. 1919.41 1.02 0.0727967 0.0613132 22834 132086 -1 2519 21 1954 3285 237082 51906 4.04943 4.04943 -149.419 -4.04943 0 0 701300. 2426.64 0.30 0.07 0.12 -1 -1 0.30 0.0175497 0.0155177 177 3 156 32 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 4.25 vpr 64.29 MiB 0.02 7276 -1 -1 1 0.04 -1 -1 33868 -1 -1 32 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65832 30 32 371 295 1 184 94 17 17 289 -1 unnamed_device 25.3 MiB 0.31 1003 9892 2469 6555 868 64.3 MiB 0.08 0.00 3.59821 -110.073 -3.59821 3.59821 0.85 0.00020839 0.000164853 0.0118818 0.00956624 -1 -1 -1 -1 32 2189 22 6.65987e+06 405696 554710. 1919.41 0.94 0.0497122 0.0414156 22834 132086 -1 1957 22 1356 2177 131501 31199 2.77671 2.77671 -109.109 -2.77671 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0151062 0.0131895 136 59 60 30 56 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 4.36 vpr 63.53 MiB 0.02 6920 -1 -1 1 0.04 -1 -1 34212 -1 -1 20 27 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65056 27 32 269 226 1 143 79 17 17 289 -1 unnamed_device 24.8 MiB 0.12 768 12754 4322 6521 1911 63.5 MiB 0.08 0.00 3.3979 -99.6122 -3.3979 3.3979 0.96 0.00016626 0.000130912 0.0160227 0.013089 -1 -1 -1 -1 32 1486 19 6.65987e+06 253560 554710. 1919.41 0.97 0.0486231 0.0407528 22834 132086 -1 1328 19 850 1272 81588 19169 2.56737 2.56737 -92.6845 -2.56737 0 0 701300. 2426.64 0.31 0.04 0.13 -1 -1 0.31 0.0120134 0.0106387 107 34 54 27 27 27 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 4.41 vpr 64.48 MiB 0.03 7300 -1 -1 1 0.04 -1 -1 34204 -1 -1 40 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66028 32 32 493 378 1 232 104 17 17 289 -1 unnamed_device 26.0 MiB 0.28 1366 15232 4128 9656 1448 64.5 MiB 0.14 0.00 4.15924 -136.806 -4.15924 4.15924 0.85 0.000277765 0.000220544 0.0207731 0.0166701 -1 -1 -1 -1 32 3092 23 6.65987e+06 507120 554710. 1919.41 0.99 0.06996 0.0578366 22834 132086 -1 2778 24 2083 3703 243892 56131 3.46791 3.46791 -136.36 -3.46791 0 0 701300. 2426.64 0.31 0.07 0.12 -1 -1 0.31 0.0200441 0.0173711 184 95 62 31 95 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 4.17 vpr 64.46 MiB 0.02 7448 -1 -1 1 0.04 -1 -1 34200 -1 -1 21 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66012 31 32 455 371 1 189 84 17 17 289 -1 unnamed_device 25.5 MiB 0.24 989 7038 1632 4931 475 64.5 MiB 0.07 0.00 4.3087 -132.62 -4.3087 4.3087 0.84 0.000235578 0.000185919 0.0114304 0.00927209 -1 -1 -1 -1 32 2348 23 6.65987e+06 266238 554710. 1919.41 0.91 0.0526485 0.0432866 22834 132086 -1 2136 20 1285 2053 142990 32843 3.57811 3.57811 -134.798 -3.57811 0 0 701300. 2426.64 0.29 0.05 0.12 -1 -1 0.29 0.0161723 0.0141581 145 124 0 0 124 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 4.48 vpr 63.89 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33896 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65424 32 32 355 304 1 151 80 17 17 289 -1 unnamed_device 24.9 MiB 0.22 741 9196 2428 5976 792 63.9 MiB 0.07 0.00 3.81463 -109.262 -3.81463 3.81463 0.95 0.000220879 0.000177835 0.0138884 0.0114192 -1 -1 -1 -1 32 1801 19 6.65987e+06 202848 554710. 1919.41 0.96 0.0532942 0.0449636 22834 132086 -1 1593 16 667 1046 64001 15581 2.76971 2.76971 -104.892 -2.76971 0 0 701300. 2426.64 0.31 0.04 0.13 -1 -1 0.31 0.0149849 0.013423 109 89 0 0 89 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 4.43 vpr 64.00 MiB 0.02 6912 -1 -1 1 0.04 -1 -1 34040 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65540 32 32 364 282 1 196 96 17 17 289 -1 unnamed_device 25.0 MiB 0.13 1123 15645 4083 9696 1866 64.0 MiB 0.12 0.00 4.2837 -136.384 -4.2837 4.2837 0.96 0.000211771 0.000167069 0.0188431 0.0153039 -1 -1 -1 -1 26 2734 22 6.65987e+06 405696 477104. 1650.88 1.01 0.0583938 0.0487463 21682 110474 -1 2304 21 1435 2192 157562 36356 3.90497 3.90497 -138.663 -3.90497 0 0 585099. 2024.56 0.25 0.05 0.10 -1 -1 0.25 0.0161463 0.0142706 146 34 90 30 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 4.86 vpr 64.05 MiB 0.03 7372 -1 -1 1 0.04 -1 -1 34460 -1 -1 36 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65584 31 32 443 336 1 220 99 17 17 289 -1 unnamed_device 25.6 MiB 0.34 1167 13551 3218 9177 1156 64.0 MiB 0.13 0.00 4.22766 -133.836 -4.22766 4.22766 0.90 0.000263693 0.000210924 0.0194889 0.0159014 -1 -1 -1 -1 32 2393 23 6.65987e+06 456408 554710. 1919.41 1.00 0.0709292 0.0599018 22834 132086 -1 2240 21 1644 2505 148012 35341 3.52031 3.52031 -130.484 -3.52031 0 0 701300. 2426.64 0.34 0.06 0.13 -1 -1 0.34 0.019955 0.0176184 171 64 87 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 6.08 vpr 64.07 MiB 0.02 7212 -1 -1 1 0.04 -1 -1 34212 -1 -1 33 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65604 30 32 373 297 1 186 95 17 17 289 -1 unnamed_device 25.0 MiB 0.30 1070 11111 2802 7426 883 64.1 MiB 0.09 0.00 3.62941 -110.797 -3.62941 3.62941 0.89 0.000216898 0.000171859 0.0133401 0.0108081 -1 -1 -1 -1 22 3059 42 6.65987e+06 418374 420624. 1455.45 2.81 0.0855172 0.0706322 20818 92861 -1 2541 19 1204 2230 204381 44907 3.36171 3.36171 -117.007 -3.36171 0 0 500653. 1732.36 0.23 0.06 0.08 -1 -1 0.23 0.0143945 0.0126119 134 61 58 30 58 30 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 4.28 vpr 64.42 MiB 0.02 7276 -1 -1 1 0.04 -1 -1 34076 -1 -1 42 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65964 32 32 407 319 1 201 106 17 17 289 -1 unnamed_device 25.3 MiB 0.26 1074 12606 3053 8336 1217 64.4 MiB 0.11 0.00 4.0783 -140.694 -4.0783 4.0783 0.85 0.000234095 0.000184681 0.0145852 0.0117767 -1 -1 -1 -1 30 2478 23 6.65987e+06 532476 526063. 1820.29 0.98 0.0550997 0.0457093 22546 126617 -1 2051 21 1402 2299 137271 31767 3.45817 3.45817 -133.145 -3.45817 0 0 666494. 2306.21 0.28 0.05 0.11 -1 -1 0.28 0.0156737 0.0136999 157 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 4.59 vpr 63.81 MiB 0.02 7204 -1 -1 1 0.04 -1 -1 34304 -1 -1 38 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65340 32 32 405 318 1 200 102 17 17 289 -1 unnamed_device 25.3 MiB 0.31 984 6766 1232 5172 362 63.8 MiB 0.07 0.00 3.41884 -115.761 -3.41884 3.41884 0.93 0.000247148 0.000195377 0.00970804 0.00800792 -1 -1 -1 -1 26 2790 23 6.65987e+06 481764 477104. 1650.88 0.94 0.0585829 0.0496962 21682 110474 -1 2277 22 1589 2490 166815 39888 2.87011 2.87011 -115.85 -2.87011 0 0 585099. 2024.56 0.26 0.07 0.10 -1 -1 0.26 0.0227187 0.0202367 155 65 63 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 3.90 vpr 63.59 MiB 0.02 7036 -1 -1 1 0.04 -1 -1 33988 -1 -1 16 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65112 29 32 287 238 1 135 77 17 17 289 -1 unnamed_device 24.8 MiB 0.09 508 12791 3386 7672 1733 63.6 MiB 0.06 0.00 3.7595 -104.085 -3.7595 3.7595 0.84 0.000167729 0.000131427 0.0150113 0.0120138 -1 -1 -1 -1 32 1446 20 6.65987e+06 202848 554710. 1919.41 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111 82 0 0 82 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 5.81 vpr 64.08 MiB 0.03 7044 -1 -1 1 0.04 -1 -1 34024 -1 -1 37 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65620 31 32 365 281 1 196 100 17 17 289 -1 unnamed_device 25.1 MiB 0.24 964 13556 3768 8523 1265 64.1 MiB 0.12 0.00 4.3897 -133.197 -4.3897 4.3897 0.86 0.000230146 0.000184894 0.0159005 0.0130657 -1 -1 -1 -1 28 2998 50 6.65987e+06 469086 500653. 1732.36 2.10 0.0712368 0.05962 21970 115934 -1 2210 24 2070 3451 281681 63736 3.91377 3.91377 -140.951 -3.91377 0 0 612192. 2118.31 0.27 0.10 0.11 -1 -1 0.27 0.024783 0.0221684 150 34 93 31 31 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 4.60 vpr 63.76 MiB 0.02 7180 -1 -1 1 0.06 -1 -1 33988 -1 -1 31 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65292 29 32 297 254 1 150 92 17 17 289 -1 unnamed_device 24.9 MiB 0.27 621 11063 2736 7707 620 63.8 MiB 0.08 0.00 3.58224 -95.8028 -3.58224 3.58224 0.91 0.000171037 0.000133562 0.0112281 0.00901717 -1 -1 -1 -1 26 1813 22 6.65987e+06 393018 477104. 1650.88 1.02 0.0490225 0.0412671 21682 110474 -1 1602 17 840 1268 82834 21231 2.78565 2.78565 -100.012 -2.78565 0 0 585099. 2024.56 0.26 0.04 0.10 -1 -1 0.26 0.0114202 0.0101537 108 56 29 29 52 26 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 4.77 vpr 63.80 MiB 0.02 7028 -1 -1 1 0.05 -1 -1 33896 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65328 32 32 314 256 1 160 80 17 17 289 -1 unnamed_device 24.9 MiB 0.23 823 7992 1920 5681 391 63.8 MiB 0.08 0.00 3.5141 -118.56 -3.5141 3.5141 0.95 0.000212288 0.000163298 0.0115542 0.00939533 -1 -1 -1 -1 32 1965 19 6.65987e+06 202848 554710. 1919.41 1.03 0.045829 0.0384227 22834 132086 -1 1725 18 1124 1875 121897 29067 2.82857 2.82857 -115.262 -2.82857 0 0 701300. 2426.64 0.32 0.05 0.12 -1 -1 0.32 0.0133285 0.0118801 119 34 64 32 32 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 4.35 vpr 64.30 MiB 0.03 7328 -1 -1 1 0.04 -1 -1 34104 -1 -1 36 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65848 31 32 387 307 1 189 99 17 17 289 -1 unnamed_device 25.5 MiB 0.28 997 12411 3191 8197 1023 64.3 MiB 0.09 0.00 3.50507 -117.588 -3.50507 3.50507 0.91 0.000225858 0.000175333 0.0148189 0.0118768 -1 -1 -1 -1 26 2261 19 6.65987e+06 456408 477104. 1650.88 0.88 0.0564569 0.0473976 21682 110474 -1 1929 20 1442 2138 126025 29548 2.78571 2.78571 -115.079 -2.78571 0 0 585099. 2024.56 0.25 0.06 0.10 -1 -1 0.25 0.0180723 0.0160056 142 64 58 31 62 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 4.08 vpr 63.61 MiB 0.02 6968 -1 -1 1 0.04 -1 -1 33824 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65140 31 32 308 262 1 147 79 17 17 289 -1 unnamed_device 24.7 MiB 0.32 889 12754 3806 7303 1645 63.6 MiB 0.08 0.00 3.11304 -101.246 -3.11304 3.11304 0.84 0.000195861 0.000155969 0.0154357 0.0123096 -1 -1 -1 -1 32 1732 19 6.65987e+06 202848 554710. 1919.41 0.88 0.0452196 0.037293 22834 132086 -1 1557 13 635 1065 56669 14489 2.67545 2.67545 -99.9304 -2.67545 0 0 701300. 2426.64 0.29 0.03 0.11 -1 -1 0.29 0.00953536 0.00851094 105 55 31 31 53 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 5.65 vpr 64.28 MiB 0.02 7132 -1 -1 1 0.04 -1 -1 34016 -1 -1 32 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65820 32 32 383 307 1 184 96 17 17 289 -1 unnamed_device 25.3 MiB 0.37 929 17616 5738 7949 3929 64.3 MiB 0.11 0.00 3.3979 -111.1 -3.3979 3.3979 0.87 0.000223965 0.000176453 0.0208594 0.0168011 -1 -1 -1 -1 32 2317 41 6.65987e+06 405696 554710. 1919.41 2.03 0.0852565 0.0710206 22834 132086 -1 1896 18 1239 2139 175466 43245 2.75477 2.75477 -106.462 -2.75477 0 0 701300. 2426.64 0.30 0.06 0.13 -1 -1 0.30 0.0168361 0.0150402 136 65 52 26 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 4.62 vpr 63.93 MiB 0.02 7308 -1 -1 1 0.03 -1 -1 34104 -1 -1 36 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65460 31 32 422 339 1 195 99 17 17 289 -1 unnamed_device 25.4 MiB 0.80 966 17427 4771 10069 2587 63.9 MiB 0.13 0.00 3.7525 -119.295 -3.7525 3.7525 0.85 0.000247417 0.00019615 0.0214676 0.0171495 -1 -1 -1 -1 28 2373 19 6.65987e+06 456408 500653. 1732.36 0.85 0.0599269 0.0493077 21970 115934 -1 2028 19 1642 2395 148618 35956 3.00737 3.00737 -117.232 -3.00737 0 0 612192. 2118.31 0.26 0.05 0.10 -1 -1 0.26 0.016465 0.0142604 148 93 31 31 92 31 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 4.63 vpr 63.84 MiB 0.02 6912 -1 -1 1 0.04 -1 -1 33908 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65376 32 32 333 279 1 160 82 17 17 289 -1 unnamed_device 25.0 MiB 0.29 861 11652 3522 6006 2124 63.8 MiB 0.08 0.00 2.81844 -100.349 -2.81844 2.81844 0.97 0.000198971 0.00015632 0.0156976 0.0127349 -1 -1 -1 -1 32 1853 21 6.65987e+06 228204 554710. 1919.41 1.01 0.0534988 0.0447903 22834 132086 -1 1607 17 1010 1569 98798 22749 2.60745 2.60745 -102.851 -2.60745 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0131704 0.011693 115 61 32 32 60 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 4.22 vpr 63.85 MiB 0.02 7132 -1 -1 1 0.03 -1 -1 33804 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65380 32 32 339 283 1 164 82 17 17 289 -1 unnamed_device 25.1 MiB 0.32 667 7380 1595 4913 872 63.8 MiB 0.05 0.00 3.38184 -112.707 -3.38184 3.38184 0.84 0.000206345 0.000165141 0.00994296 0.00808268 -1 -1 -1 -1 32 2059 26 6.65987e+06 228204 554710. 1919.41 1.01 0.0465543 0.038809 22834 132086 -1 1562 19 1091 1685 116660 29140 2.76171 2.76171 -110.403 -2.76171 0 0 701300. 2426.64 0.29 0.04 0.12 -1 -1 0.29 0.0124826 0.0109317 121 63 32 32 62 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 4.45 vpr 63.78 MiB 0.02 7264 -1 -1 1 0.04 -1 -1 34304 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65308 32 32 407 319 1 198 100 17 17 289 -1 unnamed_device 25.2 MiB 0.26 1042 12164 2979 8000 1185 63.8 MiB 0.10 0.00 4.02524 -139.262 -4.02524 4.02524 0.89 0.000224224 0.000177437 0.0143822 0.011598 -1 -1 -1 -1 28 2574 23 6.65987e+06 456408 500653. 1732.36 0.93 0.0544088 0.0451301 21970 115934 -1 2245 21 1795 2760 183069 42394 3.45191 3.45191 -135.897 -3.45191 0 0 612192. 2118.31 0.26 0.06 0.12 -1 -1 0.26 0.017424 0.0153585 154 65 64 32 64 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 4.23 vpr 64.05 MiB 0.02 7212 -1 -1 1 0.04 -1 -1 34152 -1 -1 32 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 29 32 367 293 1 183 93 17 17 289 -1 unnamed_device 25.1 MiB 0.28 974 17313 5216 9261 2836 64.1 MiB 0.13 0.00 3.57304 -105.909 -3.57304 3.57304 0.87 0.000215211 0.000171489 0.0209218 0.0168287 -1 -1 -1 -1 32 2030 20 6.65987e+06 405696 554710. 1919.41 0.87 0.0572275 0.0471326 22834 132086 -1 1783 15 787 1212 72557 17895 2.73571 2.73571 -101.927 -2.73571 0 0 701300. 2426.64 0.29 0.03 0.11 -1 -1 0.29 0.0132598 0.0118308 133 62 56 29 58 29 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 4.26 vpr 64.08 MiB 0.02 7196 -1 -1 1 0.04 -1 -1 34044 -1 -1 37 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65616 32 32 469 381 1 200 101 17 17 289 -1 unnamed_device 25.6 MiB 0.35 1004 11616 2968 7911 737 64.1 MiB 0.10 0.00 3.97241 -135.454 -3.97241 3.97241 0.86 0.000245837 0.000193262 0.0149478 0.0118908 -1 -1 -1 -1 32 2350 23 6.65987e+06 469086 554710. 1919.41 0.91 0.0575117 0.0473782 22834 132086 -1 2119 18 1433 2346 143697 34733 3.52231 3.52231 -134.27 -3.52231 0 0 701300. 2426.64 0.29 0.05 0.11 -1 -1 0.29 0.0155355 0.0136356 156 127 0 0 128 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 5.70 vpr 63.50 MiB 0.02 6808 -1 -1 1 0.03 -1 -1 33768 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65024 31 32 259 212 1 146 79 17 17 289 -1 unnamed_device 24.7 MiB 0.18 635 8698 2288 5521 889 63.5 MiB 0.07 0.00 2.9397 -95.8867 -2.9397 2.9397 0.87 0.000194796 0.000158562 0.0113121 0.00927696 -1 -1 -1 -1 32 1618 16 6.65987e+06 202848 554710. 1919.41 2.45 0.0849356 0.070936 22834 132086 -1 1428 19 892 1396 78771 21607 2.61571 2.61571 -97.4937 -2.61571 0 0 701300. 2426.64 0.30 0.04 0.12 -1 -1 0.30 0.0115836 0.0102602 105 4 85 31 0 0 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 4.50 vpr 64.24 MiB 0.02 7304 -1 -1 1 0.04 -1 -1 34068 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65784 32 32 418 338 1 190 97 17 17 289 -1 unnamed_device 25.4 MiB 0.22 948 20077 6167 11074 2836 64.2 MiB 0.15 0.00 4.10497 -133.778 -4.10497 4.10497 0.88 0.000237769 0.000187399 0.0253409 0.0202843 -1 -1 -1 -1 32 2138 21 6.65987e+06 418374 554710. 1919.41 0.96 0.0680995 0.0564173 22834 132086 -1 1855 19 1230 1767 113991 26733 3.46417 3.46417 -126.503 -3.46417 0 0 701300. 2426.64 0.29 0.06 0.13 -1 -1 0.29 0.0195772 0.0172145 142 92 28 28 92 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 4.96 vpr 63.83 MiB 0.02 7196 -1 -1 1 0.04 -1 -1 33884 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65364 32 32 376 318 1 156 80 17 17 289 -1 unnamed_device 25.0 MiB 0.24 805 9196 3450 4876 870 63.8 MiB 0.07 0.00 3.54047 -120.422 -3.54047 3.54047 0.91 0.000223891 0.00017629 0.0154269 0.0126552 -1 -1 -1 -1 30 2166 35 6.65987e+06 202848 526063. 1820.29 1.44 0.0876728 0.0760202 22546 126617 -1 1721 17 1153 1677 119370 27737 2.75177 2.75177 -114.486 -2.75177 0 0 666494. 2306.21 0.29 0.06 0.12 -1 -1 0.29 0.0177851 0.0159531 115 96 0 0 96 32 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 4.54 vpr 63.97 MiB 0.02 7188 -1 -1 1 0.05 -1 -1 33996 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65508 32 32 401 316 1 196 99 17 17 289 -1 unnamed_device 25.4 MiB 0.27 1002 18111 5520 9663 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66196 32 32 333 251 1 180 76 17 17 289 -1 unnamed_device 25.9 MiB 1.20 755 9836 4062 5477 297 64.6 MiB 0.06 0.00 4.01986 -136.639 -4.01986 4.01986 0.88 0.000197592 0.000156166 0.0149909 0.012293 -1 -1 -1 -1 42 2992 24 6.95648e+06 173708 744469. 2576.02 2.09 0.0694728 0.0583928 27202 183097 -1 2087 23 1911 2887 275152 61216 4.09781 4.09781 -148.697 -4.09781 0 0 949917. 3286.91 0.36 0.07 0.16 -1 -1 0.36 0.0154741 0.0135685 74 3 122 32 0 0 -fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 4.94 vpr 63.73 MiB 0.02 6652 -1 -1 1 0.04 -1 -1 34112 -1 -1 8 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65256 32 32 199 182 1 119 72 17 17 289 -1 unnamed_device 25.2 MiB 0.30 731 9906 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66316 31 32 455 371 1 185 77 17 17 289 -1 unnamed_device 26.1 MiB 2.35 778 10998 4559 6059 380 64.8 MiB 0.08 0.00 4.63397 -149.774 -4.63397 4.63397 0.90 0.00024371 0.000190966 0.0198411 0.0159577 -1 -1 -1 -1 42 3197 35 6.95648e+06 202660 744469. 2576.02 2.23 0.0831513 0.0680942 27202 183097 -1 2238 23 1687 2592 248478 54871 4.77941 4.77941 -161.64 -4.77941 0 0 949917. 3286.91 0.39 0.07 0.16 -1 -1 0.39 0.018557 0.0161691 78 124 0 0 124 31 -fixed_k6_frac_2ripple_N8_22nm.xml mult_040.v common 8.04 vpr 65.06 MiB 0.03 7216 -1 -1 1 0.04 -1 -1 34216 -1 -1 13 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66624 31 32 413 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66076 31 32 305 250 1 152 74 17 17 289 -1 unnamed_device 25.7 MiB 0.67 589 10304 4334 5652 318 64.5 MiB 0.06 0.00 3.38836 -119.14 -3.38836 3.38836 0.97 0.000184644 0.000145692 0.0143092 0.0116647 -1 -1 -1 -1 36 2300 43 6.95648e+06 159232 648988. 2245.63 2.69 0.0850846 0.0712621 26050 158493 -1 1707 19 1387 1919 175590 41198 3.54282 3.54282 -128.096 -3.54282 0 0 828058. 2865.25 0.31 0.05 0.14 -1 -1 0.31 0.0123226 0.0108318 62 34 62 31 31 31 -fixed_k6_frac_2ripple_N8_22nm.xml mult_045.v common 6.67 vpr 64.86 MiB 0.02 7144 -1 -1 1 0.04 -1 -1 34096 -1 -1 27 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66412 31 32 395 311 1 188 90 17 17 289 -1 unnamed_device 25.9 MiB 0.73 807 13959 3748 8318 1893 64.9 MiB 0.09 0.00 3.90275 -135.486 -3.90275 3.90275 0.98 0.000231152 0.000182294 0.0194515 0.0158095 -1 -1 -1 -1 42 2665 23 6.95648e+06 390843 744469. 2576.02 2.40 0.0885421 0.0735368 27202 183097 -1 2191 20 1849 2845 264362 56154 4.00046 4.00046 -148.359 -4.00046 0 0 949917. 3286.91 0.35 0.07 0.16 -1 -1 0.35 0.0172906 0.0153058 86 64 62 31 62 31 -fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 9.86 vpr 64.84 MiB 0.02 7284 -1 -1 1 0.05 -1 -1 34128 -1 -1 26 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66396 32 32 397 313 1 188 90 17 17 289 -1 unnamed_device 25.9 MiB 0.91 803 11145 4511 6144 490 64.8 MiB 0.08 0.00 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67160 32 32 531 413 1 225 95 17 17 289 -1 unnamed_device 26.7 MiB 1.98 1126 15215 3732 10105 1378 65.6 MiB 0.11 0.00 4.49524 -160.999 -4.49524 4.49524 0.91 0.000277122 0.000218207 0.0227717 0.0183203 -1 -1 -1 -1 50 2881 24 6.95648e+06 448746 902133. 3121.57 16.05 0.189725 0.155869 28642 213929 -1 2578 31 3160 4685 568753 162228 4.90641 4.90641 -174.584 -4.90641 0 0 1.08113e+06 3740.92 0.40 0.14 0.20 -1 -1 0.40 0.0246224 0.021161 103 127 32 32 128 32 -fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 7.26 vpr 64.74 MiB 0.02 7212 -1 -1 1 0.04 -1 -1 33988 -1 -1 28 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66192 30 32 296 244 1 151 83 17 17 289 -1 unnamed_device 25.8 MiB 0.86 581 11423 4387 5607 1429 64.6 MiB 0.06 0.00 3.09676 -109.06 -3.09676 3.09676 0.94 0.00017616 0.000139195 0.0134055 0.0109111 -1 -1 -1 -1 38 2169 24 6.95648e+06 303989 678818. 2348.85 2.72 0.0680768 0.0566394 26626 170182 -1 1705 19 1262 1896 159278 35800 3.29047 3.29047 -118.286 -3.29047 0 0 902133. 3121.57 0.32 0.05 0.14 -1 -1 0.32 0.0117107 0.0103167 65 34 60 30 30 30 -fixed_k6_frac_2ripple_N8_22nm.xml mult_066.v common 7.79 vpr 64.72 MiB 0.03 7360 -1 -1 1 0.05 -1 -1 33964 -1 -1 20 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66420 32 32 366 283 1 215 87 17 17 289 -1 unnamed_device 25.9 MiB 0.61 873 12759 5251 7214 294 64.9 MiB 0.09 0.00 4.03513 -142.757 -4.03513 4.03513 0.92 0.00022868 0.000182409 0.019295 0.0157573 -1 -1 -1 -1 42 3024 42 6.99608e+06 338461 744469. 2576.02 13.02 0.167627 0.140752 27202 183097 -1 2381 21 2303 3171 353724 88771 4.2429 4.2429 -160.748 -4.2429 0 0 949917. 3286.91 0.35 0.09 0.15 -1 -1 0.35 0.0164715 0.0145842 97 34 91 32 32 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_022.v common 7.26 vpr 64.95 MiB 0.02 7336 -1 -1 1 0.04 -1 -1 34640 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66512 32 32 460 375 1 303 86 17 17 289 -1 unnamed_device 26.4 MiB 1.61 1281 15206 5059 7438 2709 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66184 32 32 376 288 1 218 81 17 17 289 -1 unnamed_device 25.8 MiB 1.32 835 12856 4936 6167 1753 64.6 MiB 0.08 0.00 3.83288 -138.607 -3.83288 3.83288 0.89 0.00021599 0.00016998 0.0192495 0.0156266 -1 -1 -1 -1 54 2823 49 6.99608e+06 250167 949917. 3286.91 5.84 0.127506 0.105907 29506 232905 -1 1943 24 2035 2954 239818 56718 4.18862 4.18862 -149.145 -4.18862 0 0 1.17392e+06 4061.99 0.41 0.07 0.21 -1 -1 0.41 0.0161238 0.0141157 95 34 96 32 32 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_027.v common 7.76 vpr 64.61 MiB 0.02 7036 -1 -1 1 0.04 -1 -1 33968 -1 -1 28 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66164 32 32 337 253 1 188 92 17 17 289 -1 unnamed_device 25.6 MiB 0.31 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66620 32 32 403 317 1 252 82 17 17 289 -1 unnamed_device 26.2 MiB 0.98 1127 14500 5161 6829 2510 65.1 MiB 0.11 0.00 3.90969 -144.443 -3.90969 3.90969 0.97 0.00022537 0.000178072 0.0238396 0.0193545 -1 -1 -1 -1 46 3349 32 6.99608e+06 264882 828058. 2865.25 5.45 0.144589 0.119953 28066 200906 -1 2712 21 2653 3652 420598 86614 4.50691 4.50691 -161.912 -4.50691 0 0 1.01997e+06 3529.29 0.40 0.11 0.18 -1 -1 0.40 0.0200355 0.0178052 110 65 62 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_037.v common 8.75 vpr 64.87 MiB 0.04 7184 -1 -1 1 0.05 -1 -1 34224 -1 -1 16 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66428 31 32 353 302 1 224 79 17 17 289 -1 unnamed_device 26.0 MiB 1.11 1061 8867 2259 5908 700 64.9 MiB 0.06 0.00 3.47679 -127.153 -3.47679 3.47679 0.94 0.000198827 0.000156777 0.0132116 0.0108281 -1 -1 -1 -1 40 2485 24 6.99608e+06 235451 706193. 2443.58 4.15 0.0987458 0.0811122 26914 176310 -1 2159 35 1875 1958 356327 152178 3.24576 3.24576 -128.28 -3.24576 0 0 926341. 3205.33 0.35 0.11 0.15 -1 -1 0.35 0.0193278 0.0166574 99 90 0 0 89 31 -fixed_k6_frac_2uripple_N8_22nm.xml mult_038.v common 6.62 vpr 64.75 MiB 0.03 7340 -1 -1 1 0.04 -1 -1 34028 -1 -1 18 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66308 31 32 391 309 1 242 81 17 17 289 -1 unnamed_device 25.7 MiB 0.93 1183 15656 5841 7703 2112 64.8 MiB 0.10 0.00 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66532 32 32 407 319 1 252 81 17 17 289 -1 unnamed_device 26.2 MiB 1.14 1214 6556 2392 3648 516 65.0 MiB 0.06 0.00 3.81945 -147.993 -3.81945 3.81945 0.96 0.000279184 0.000211029 0.0125466 0.0103975 -1 -1 -1 -1 46 2989 29 6.99608e+06 250167 828058. 2865.25 2.37 0.0880295 0.0738868 28066 200906 -1 2519 22 2224 2868 243990 48257 3.93982 3.93982 -158.396 -3.93982 0 0 1.01997e+06 3529.29 0.39 0.07 0.18 -1 -1 0.39 0.0172134 0.0151412 110 65 64 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_043.v common 11.70 vpr 65.39 MiB 0.03 7280 -1 -1 1 0.05 -1 -1 34328 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66964 32 32 496 380 1 313 86 17 17 289 -1 unnamed_device 26.3 MiB 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-fixed_k6_frac_2uripple_N8_22nm.xml mult_046.v common 7.21 vpr 64.75 MiB 0.04 7200 -1 -1 1 0.04 -1 -1 34136 -1 -1 20 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66300 32 32 397 313 1 246 84 17 17 289 -1 unnamed_device 25.9 MiB 1.54 1277 13077 4097 6940 2040 64.7 MiB 0.09 0.00 3.58873 -134.162 -3.58873 3.58873 0.99 0.000229633 0.000180938 0.0194183 0.0157603 -1 -1 -1 -1 42 3408 27 6.99608e+06 294314 744469. 2576.02 2.01 0.0800376 0.066476 27202 183097 -1 2874 20 1975 2784 237357 49435 3.78176 3.78176 -147.68 -3.78176 0 0 949917. 3286.91 0.36 0.08 0.17 -1 -1 0.36 0.0210986 0.0188864 108 63 62 32 62 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_047.v common 7.17 vpr 64.48 MiB 0.02 7164 -1 -1 1 0.04 -1 -1 33912 -1 -1 13 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 345 257 1 187 77 17 17 289 -1 unnamed_device 25.8 MiB 1.04 749 9368 3828 5102 438 64.5 MiB 0.06 0.00 3.60355 -132.937 -3.60355 3.60355 0.93 0.000213125 0.00016731 0.0149499 0.012205 -1 -1 -1 -1 56 2389 27 6.99608e+06 191304 973134. 3367.25 2.49 0.0828029 0.0693947 29794 239141 -1 1739 21 1825 3135 221688 52565 4.10836 4.10836 -144.078 -4.10836 0 0 1.19926e+06 4149.71 0.45 0.09 0.22 -1 -1 0.45 0.0220902 0.0198719 78 3 128 32 0 0 -fixed_k6_frac_2uripple_N8_22nm.xml mult_048.v common 7.58 vpr 64.88 MiB 0.02 7200 -1 -1 1 0.05 -1 -1 35376 -1 -1 19 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66440 32 32 424 343 1 266 83 17 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66340 31 32 449 367 1 290 85 17 17 289 -1 unnamed_device 26.4 MiB 2.11 1393 14035 5565 6766 1704 64.8 MiB 0.10 0.00 4.08308 -143.875 -4.08308 4.08308 0.96 0.000255139 0.000191975 0.0220399 0.0175298 -1 -1 -1 -1 46 3396 24 6.99608e+06 323745 828058. 2865.25 2.11 0.0987222 0.0814817 28066 200906 -1 2897 21 2039 2368 186090 38982 4.05885 4.05885 -147.773 -4.05885 0 0 1.01997e+06 3529.29 0.42 0.07 0.20 -1 -1 0.42 0.0220963 0.0195136 132 122 0 0 122 31 -fixed_k6_frac_2uripple_N8_22nm.xml mult_054.v common 7.29 vpr 64.72 MiB 0.04 7324 -1 -1 1 0.04 -1 -1 34048 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66272 32 32 432 346 1 281 85 17 17 289 -1 unnamed_device 26.1 MiB 1.10 1279 12175 4545 5316 2314 64.7 MiB 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66208 32 32 368 284 1 217 80 17 17 289 -1 unnamed_device 25.8 MiB 0.95 1017 10916 2707 7442 767 64.7 MiB 0.08 0.00 3.32994 -129.578 -3.32994 3.32994 1.03 0.000220964 0.000174747 0.0171409 0.0140139 -1 -1 -1 -1 40 2983 47 6.99608e+06 235451 706193. 2443.58 5.65 0.167246 0.139392 26914 176310 -1 2449 20 2023 2659 257257 52586 3.29722 3.29722 -135.821 -3.29722 0 0 926341. 3205.33 0.36 0.08 0.16 -1 -1 0.36 0.0181497 0.0161526 93 34 92 32 32 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_059.v common 7.62 vpr 64.62 MiB 0.04 7124 -1 -1 1 0.06 -1 -1 33716 -1 -1 24 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66168 30 32 296 244 1 177 86 17 17 289 -1 unnamed_device 25.7 MiB 0.91 690 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-fixed_k6_frac_2uripple_N8_22nm.xml mult_062.v common 9.33 vpr 64.30 MiB 0.03 6768 -1 -1 1 0.04 -1 -1 33912 -1 -1 24 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65848 32 32 283 225 1 158 88 17 17 289 -1 unnamed_device 25.6 MiB 0.34 689 12763 5259 7126 378 64.3 MiB 0.07 0.00 2.98775 -114.562 -2.98775 2.98775 1.06 0.000182842 0.000144177 0.0144186 0.0116779 -1 -1 -1 -1 46 1939 24 6.99608e+06 353176 828058. 2865.25 5.26 0.106654 0.0893777 28066 200906 -1 1527 21 1501 2262 149821 33894 3.01532 3.01532 -116.678 -3.01532 0 0 1.01997e+06 3529.29 0.40 0.05 0.18 -1 -1 0.40 0.0122811 0.0107309 70 3 96 32 0 0 -fixed_k6_frac_2uripple_N8_22nm.xml mult_063.v common 22.35 vpr 65.39 MiB 0.03 7272 -1 -1 1 0.05 -1 -1 34388 -1 -1 18 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66960 32 32 438 320 1 256 82 17 17 289 -1 unnamed_device 26.4 MiB 1.16 1185 13432 5656 7470 306 65.4 MiB 0.10 0.00 4.53729 -162.267 -4.53729 4.53729 1.07 0.000263201 0.000209673 0.0242107 0.019831 -1 -1 -1 -1 50 3497 30 6.99608e+06 264882 902133. 3121.57 17.27 0.194278 0.162778 28642 213929 -1 2557 23 2809 4093 320106 67773 4.92476 4.92476 -175.108 -4.92476 0 0 1.08113e+06 3740.92 0.44 0.09 0.19 -1 -1 0.44 0.022 0.0195436 112 34 128 32 32 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_064.v common 7.14 vpr 63.99 MiB 0.04 6820 -1 -1 1 0.04 -1 -1 33864 -1 -1 10 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65524 32 32 283 225 1 156 74 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66648 32 32 407 319 1 249 82 17 17 289 -1 unnamed_device 26.3 MiB 1.27 1170 5244 1136 3811 297 65.1 MiB 0.05 0.00 4.32144 -158.986 -4.32144 4.32144 1.00 0.000230503 0.000183217 0.0103799 0.00872211 -1 -1 -1 -1 46 3311 42 6.99608e+06 264882 828058. 2865.25 5.78 0.140111 0.117171 28066 200906 -1 2631 25 2845 3941 372150 72492 4.81551 4.81551 -175.677 -4.81551 0 0 1.01997e+06 3529.29 0.42 0.11 0.18 -1 -1 0.42 0.0232085 0.0205383 110 65 64 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_069.v common 7.76 vpr 64.56 MiB 0.04 7028 -1 -1 1 0.05 -1 -1 34096 -1 -1 15 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66112 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66156 30 32 325 273 1 204 77 17 17 289 -1 unnamed_device 25.8 MiB 1.97 887 12139 5086 6651 402 64.6 MiB 0.08 0.00 3.82453 -131.841 -3.82453 3.82453 1.01 0.000190891 0.000150526 0.0165867 0.0133726 -1 -1 -1 -1 38 3002 38 6.99608e+06 220735 678818. 2348.85 2.79 0.0817484 0.0683012 26626 170182 -1 2180 23 2088 2835 240005 53520 4.0456 4.0456 -144.414 -4.0456 0 0 902133. 3121.57 0.35 0.10 0.16 -1 -1 0.35 0.0265658 0.0238164 89 63 30 30 60 30 -fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 8.01 vpr 64.73 MiB 0.02 7076 -1 -1 1 0.04 -1 -1 33840 -1 -1 15 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66284 32 32 361 308 1 241 79 17 17 289 -1 unnamed_device 25.8 MiB 1.46 1045 13430 4937 5959 2534 64.7 MiB 0.09 0.00 3.53869 -131.536 -3.53869 3.53869 0.98 0.000226974 0.000181446 0.021796 0.0177445 -1 -1 -1 -1 42 3258 28 6.99608e+06 220735 744469. 2576.02 2.86 0.122763 0.104468 27202 183097 -1 2507 23 2060 2527 240062 48931 3.41506 3.41506 -131.615 -3.41506 0 0 949917. 3286.91 0.44 0.08 0.18 -1 -1 0.44 0.0197599 0.0175337 105 91 0 0 91 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_075.v common 10.08 vpr 64.36 MiB 0.02 7012 -1 -1 1 0.06 -1 -1 33940 -1 -1 25 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65904 31 32 335 251 1 188 88 17 17 289 -1 unnamed_device 25.5 MiB 0.24 786 15688 6044 7337 2307 64.4 MiB 0.09 0.00 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66020 30 32 296 244 1 179 75 17 17 289 -1 unnamed_device 25.7 MiB 1.04 692 12241 5462 6298 481 64.5 MiB 0.07 0.00 3.58339 -124.571 -3.58339 3.58339 0.96 0.000183567 0.000145119 0.016464 0.0133148 -1 -1 -1 -1 46 2629 41 6.99608e+06 191304 828058. 2865.25 2.93 0.0913011 0.0769988 28066 200906 -1 1796 22 1604 2143 175253 41225 3.70046 3.70046 -130.475 -3.70046 0 0 1.01997e+06 3529.29 0.39 0.06 0.18 -1 -1 0.39 0.0133216 0.0117077 76 34 60 30 30 30 -fixed_k6_frac_2uripple_N8_22nm.xml mult_080.v common 12.51 vpr 64.85 MiB 0.03 7268 -1 -1 1 0.05 -1 -1 34044 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66404 30 32 383 303 1 237 80 17 17 289 -1 unnamed_device 26.1 MiB 2.48 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 407 319 1 252 83 17 17 289 -1 unnamed_device 26.2 MiB 1.18 985 15563 6705 8342 516 65.1 MiB 0.11 0.00 4.37079 -157.14 -4.37079 4.37079 0.96 0.000244224 0.000193967 0.0245303 0.0199559 -1 -1 -1 -1 46 3379 44 6.99608e+06 279598 828058. 2865.25 3.55 0.122301 0.102909 28066 200906 -1 2435 24 2773 3900 345445 73632 4.90351 4.90351 -180.423 -4.90351 0 0 1.01997e+06 3529.29 0.40 0.09 0.19 -1 -1 0.40 0.0193243 0.0170213 111 65 64 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_085.v common 8.24 vpr 64.73 MiB 0.03 7328 -1 -1 1 0.04 -1 -1 33952 -1 -1 20 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66288 29 32 387 316 1 240 81 17 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66712 32 32 407 319 1 252 82 17 17 289 -1 unnamed_device 26.3 MiB 1.08 1239 11118 3581 5407 2130 65.1 MiB 0.08 0.00 3.83715 -144.315 -3.83715 3.83715 0.89 0.00024052 0.00019174 0.0195501 0.0160437 -1 -1 -1 -1 40 3054 44 6.99608e+06 264882 706193. 2443.58 9.37 0.164638 0.135906 26914 176310 -1 2607 23 2389 2887 211349 46103 4.51132 4.51132 -164.932 -4.51132 0 0 926341. 3205.33 0.37 0.07 0.16 -1 -1 0.37 0.0190344 0.0167079 110 65 64 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_116.v common 8.59 vpr 64.79 MiB 0.02 7116 -1 -1 1 0.04 -1 -1 33976 -1 -1 21 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66340 29 32 367 293 1 222 82 17 17 289 -1 unnamed_device 26.0 MiB 1.96 912 9160 3705 5067 388 64.8 MiB 0.06 0.00 3.41124 -117.288 -3.41124 3.41124 0.94 0.000207571 0.00016423 0.0132526 0.0108472 -1 -1 -1 -1 38 3022 46 6.99608e+06 309029 678818. 2348.85 3.30 0.0824746 0.0680641 26626 170182 -1 2437 25 2136 2811 246062 52450 3.51187 3.51187 -127.239 -3.51187 0 0 902133. 3121.57 0.32 0.07 0.15 -1 -1 0.32 0.0176691 0.0154476 101 62 56 29 58 29 -fixed_k6_frac_2uripple_N8_22nm.xml mult_117.v common 18.33 vpr 64.91 MiB 0.02 7344 -1 -1 1 0.04 -1 -1 34152 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66472 32 32 469 381 1 309 86 17 17 289 -1 unnamed_device 26.3 MiB 1.04 1399 13316 4006 7788 1522 64.9 MiB 0.10 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66600 32 32 401 316 1 247 83 17 17 289 -1 unnamed_device 26.2 MiB 1.01 1122 13403 4777 5917 2709 65.0 MiB 0.09 0.00 3.33684 -128.047 -3.33684 3.33684 0.87 0.000224408 0.000178231 0.0197189 0.0161144 -1 -1 -1 -1 40 3281 42 6.99608e+06 279598 706193. 2443.58 11.50 0.162397 0.134694 26914 176310 -1 2604 23 2214 2913 246629 50304 3.47452 3.47452 -138.906 -3.47452 0 0 926341. 3205.33 0.35 0.08 0.16 -1 -1 0.35 0.0187151 0.0164243 106 65 61 32 64 32 -fixed_k6_frac_2uripple_N8_22nm.xml mult_122.v common 20.77 vpr 65.05 MiB 0.03 7364 -1 -1 1 0.05 -1 -1 34460 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66612 32 32 500 382 1 312 86 17 17 289 -1 unnamed_device 26.6 MiB 1.04 1505 15584 4795 8564 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65744 29 32 272 228 1 148 80 17 17 289 -1 unnamed_device 25.4 MiB 2.95 801 11776 3453 6762 1561 64.2 MiB 0.07 0.00 3.43775 -109.554 -3.43775 3.43775 0.89 0.000162292 0.000127804 0.0127527 0.0102608 -1 -1 -1 -1 32 1877 23 6.87369e+06 265503 586450. 2029.24 0.93 0.0418293 0.03461 25474 144626 -1 1647 23 1064 1825 119258 27812 2.99626 2.99626 -112.835 -2.99626 0 0 744469. 2576.02 0.29 0.04 0.13 -1 -1 0.29 0.012181 0.0105405 102 29 58 29 24 24 -fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 9.77 vpr 64.37 MiB 0.02 7148 -1 -1 1 0.05 -1 -1 33800 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65916 32 32 401 315 1 200 85 17 17 289 -1 unnamed_device 25.6 MiB 4.31 1029 14221 5946 7079 1196 64.4 MiB 0.10 0.00 3.65105 -129.633 -3.65105 3.65105 0.87 0.000224714 0.000177642 0.0207869 0.0167666 -1 -1 -1 -1 36 3065 50 6.87369e+06 293451 648988. 2245.63 2.19 0.0958683 0.0786595 26050 158493 -1 2297 19 1926 3226 237152 58676 3.45816 3.45816 -139.806 -3.45816 0 0 828058. 2865.25 0.33 0.07 0.16 -1 -1 0.33 0.0159029 0.0139562 145 63 64 32 62 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 10.02 vpr 64.67 MiB 0.02 7264 -1 -1 1 0.04 -1 -1 34080 -1 -1 38 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 383 303 1 193 102 17 17 289 -1 unnamed_device 26.0 MiB 5.90 1063 17238 4632 10836 1770 64.7 MiB 0.13 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66448 32 32 376 288 1 202 100 17 17 289 -1 unnamed_device 26.0 MiB 1.21 1077 18660 4798 12102 1760 64.9 MiB 0.13 0.00 4.29809 -149.349 -4.29809 4.29809 0.89 0.000215605 0.000168808 0.0198175 0.0159125 -1 -1 -1 -1 32 2995 31 6.87369e+06 503058 586450. 2029.24 1.04 0.0622672 0.0514239 25474 144626 -1 2431 21 1840 2718 195257 46178 3.9299 3.9299 -152.07 -3.9299 0 0 744469. 2576.02 0.29 0.06 0.13 -1 -1 0.29 0.013973 0.0121396 155 34 96 32 32 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 5.72 vpr 64.41 MiB 0.02 7124 -1 -1 1 0.04 -1 -1 34208 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65956 32 32 337 253 1 198 100 17 17 289 -1 unnamed_device 25.7 MiB 1.45 1035 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 403 317 1 200 103 17 17 289 -1 unnamed_device 26.0 MiB 3.98 1053 18419 4965 10740 2714 64.8 MiB 0.13 0.00 3.69025 -132.499 -3.69025 3.69025 0.87 0.000236148 0.000186453 0.0200595 0.0159935 -1 -1 -1 -1 32 2477 24 6.87369e+06 544980 586450. 2029.24 0.98 0.0615048 0.0505014 25474 144626 -1 2015 22 1749 2539 155694 36025 2.98996 2.98996 -128.336 -2.98996 0 0 744469. 2576.02 0.32 0.05 0.14 -1 -1 0.32 0.0156752 0.0135608 154 65 62 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 8.92 vpr 64.12 MiB 0.02 7092 -1 -1 1 0.03 -1 -1 34300 -1 -1 31 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65664 31 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66028 31 32 391 309 1 195 99 17 17 289 -1 unnamed_device 25.7 MiB 3.37 1065 19023 5641 10657 2725 64.5 MiB 0.14 0.00 3.57405 -123.706 -3.57405 3.57405 0.90 0.000242943 0.000183485 0.0209234 0.0164715 -1 -1 -1 -1 34 2347 23 6.87369e+06 503058 618332. 2139.56 1.46 0.0807165 0.0656769 25762 151098 -1 1963 20 1564 2747 169520 40321 2.77566 2.77566 -115.861 -2.77566 0 0 787024. 2723.27 0.31 0.05 0.13 -1 -1 0.31 0.0136101 0.0117076 148 64 60 31 62 31 -fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 6.77 vpr 64.87 MiB 0.03 7196 -1 -1 1 0.04 -1 -1 34300 -1 -1 38 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66424 32 32 407 319 1 202 102 17 17 289 -1 unnamed_device 25.8 MiB 2.45 1155 19618 5472 12434 1712 64.9 MiB 0.15 0.00 4.1996 -146.035 -4.1996 4.1996 0.87 0.000223865 0.000176571 0.0213021 0.0169841 -1 -1 -1 -1 30 2958 23 6.87369e+06 531006 556674. 1926.21 1.06 0.0591899 0.048507 25186 138497 -1 2309 19 1570 2428 163554 36586 3.9064 3.9064 -153.734 -3.9064 0 0 706193. 2443.58 0.30 0.05 0.12 -1 -1 0.30 0.013815 0.01203 156 65 64 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_043.v common 8.61 vpr 65.12 MiB 0.03 7296 -1 -1 1 0.04 -1 -1 34172 -1 -1 42 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66680 32 32 496 380 1 234 106 17 17 289 -1 unnamed_device 26.1 MiB 4.22 1304 13356 3354 8810 1192 65.1 MiB 0.15 0.00 4.3641 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-1 -1 1 0.04 -1 -1 34144 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66124 32 32 397 313 1 198 99 17 17 289 -1 unnamed_device 25.8 MiB 2.66 1125 15147 4465 9540 1142 64.6 MiB 0.12 0.00 3.50375 -124.908 -3.50375 3.50375 0.87 0.000224984 0.000177759 0.017141 0.013773 -1 -1 -1 -1 30 2615 20 6.87369e+06 489084 556674. 1926.21 0.96 0.0533442 0.0438888 25186 138497 -1 2047 22 1534 2693 140187 33757 2.78966 2.78966 -116.866 -2.78966 0 0 706193. 2443.58 0.27 0.05 0.12 -1 -1 0.27 0.0145921 0.0125912 150 63 62 32 62 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_047.v common 7.32 vpr 64.48 MiB 0.02 7024 -1 -1 1 0.03 -1 -1 34096 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66032 32 32 345 257 1 202 85 17 17 289 -1 unnamed_device 25.5 MiB 2.52 962 16825 4488 11549 788 64.5 MiB 0.13 0.00 4.1996 -145.34 -4.1996 4.1996 0.88 0.000206785 0.000163548 0.021257 0.0171171 -1 -1 -1 -1 32 3332 24 6.87369e+06 293451 586450. 2029.24 1.60 0.0694849 0.0574817 25474 144626 -1 2278 21 1867 3241 210798 52491 3.89741 3.89741 -156.479 -3.89741 0 0 744469. 2576.02 0.32 0.06 0.13 -1 -1 0.32 0.0139255 0.0121673 147 3 128 32 0 0 -fixed_k6_frac_ripple_N8_22nm.xml mult_048.v common 9.63 vpr 64.85 MiB 0.03 7312 -1 -1 1 0.04 -1 -1 35468 -1 -1 36 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66404 32 32 424 343 1 195 100 17 17 289 -1 unnamed_device 25.8 MiB 4.91 1065 20980 6969 11401 2610 64.8 MiB 0.18 0.00 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64.57 MiB 0.02 7228 -1 -1 1 0.03 -1 -1 33876 -1 -1 39 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66116 32 32 376 288 1 202 103 17 17 289 -1 unnamed_device 25.7 MiB 1.42 958 13599 3600 8151 1848 64.6 MiB 0.08 0.00 4.3249 -147.82 -4.3249 4.3249 0.86 0.000216082 0.000170272 0.0142184 0.0113278 -1 -1 -1 -1 32 2911 36 6.87369e+06 544980 586450. 2029.24 1.63 0.0726237 0.060214 25474 144626 -1 2230 22 1793 2893 184546 46762 4.02571 4.02571 -159.108 -4.02571 0 0 744469. 2576.02 0.30 0.06 0.13 -1 -1 0.30 0.0155482 0.0134674 156 34 96 32 32 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 10.15 vpr 64.68 MiB 0.02 7180 -1 -1 1 0.05 -1 -1 34132 -1 -1 41 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66236 32 32 407 319 1 202 105 17 17 289 -1 unnamed_device 25.8 MiB 3.72 1138 19865 5157 12797 1911 64.7 MiB 0.15 0.00 4.20633 -143.385 -4.20633 4.20633 0.86 0.000249249 0.000201686 0.0226384 0.0181355 -1 -1 -1 -1 30 2568 24 6.87369e+06 572927 556674. 1926.21 3.16 0.106058 0.0864942 25186 138497 -1 2323 25 1941 3133 245373 54886 3.8924 3.8924 -154.334 -3.8924 0 0 706193. 2443.58 0.27 0.07 0.12 -1 -1 0.27 0.015799 0.0135051 157 65 64 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 9.40 vpr 65.14 MiB 0.03 7500 -1 -1 1 0.04 -1 -1 34216 -1 -1 37 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66700 31 32 449 367 1 195 100 17 17 289 -1 unnamed_device 26.0 MiB 5.09 910 8684 1839 6215 630 65.1 MiB 0.08 0.00 4.22589 -134.122 -4.22589 4.22589 0.88 0.000237887 0.00018619 0.0113147 0.00901135 -1 -1 -1 -1 30 2752 25 6.87369e+06 517032 556674. 1926.21 1.16 0.0547158 0.0450792 25186 138497 -1 2053 20 1379 2449 129700 33281 3.8074 3.8074 -136.498 -3.8074 0 0 706193. 2443.58 0.28 0.05 0.12 -1 -1 0.28 0.0140976 0.0121024 150 122 0 0 122 31 -fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 9.21 vpr 65.26 MiB 0.02 7100 -1 -1 1 0.05 -1 -1 33872 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66824 32 32 432 346 1 200 85 17 17 289 -1 unnamed_device 26.2 MiB 4.45 1073 15709 4453 9637 1619 65.3 MiB 0.12 0.00 4.13359 -143.434 -4.13359 4.13359 0.87 0.00023319 0.000183164 0.0217007 0.0173423 -1 -1 -1 -1 34 2807 23 6.87369e+06 293451 618332. 2139.56 1.56 0.086419 0.0705133 25762 151098 -1 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66724 32 32 469 351 1 236 108 17 17 289 -1 unnamed_device 25.9 MiB 2.85 1417 17327 4454 11447 1426 65.2 MiB 0.15 0.00 4.99284 -170.997 -4.99284 4.99284 0.85 0.000258779 0.000204777 0.0200466 0.0160881 -1 -1 -1 -1 30 3591 25 6.87369e+06 614849 556674. 1926.21 3.42 0.12118 0.100026 25186 138497 -1 2850 21 2202 3809 257801 56093 4.31865 4.31865 -166.494 -4.31865 0 0 706193. 2443.58 0.27 0.07 0.12 -1 -1 0.27 0.017747 0.0153865 189 65 96 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_058.v common 7.67 vpr 64.46 MiB 0.02 7028 -1 -1 1 0.03 -1 -1 34020 -1 -1 35 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66004 32 32 368 284 1 198 99 17 17 289 -1 unnamed_device 25.6 MiB 3.65 1065 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2089 22 6.87369e+06 461137 618332. 2139.56 1.44 0.070595 0.0579194 25762 151098 -1 1735 17 1235 1956 122081 30864 3.04926 3.04926 -122.245 -3.04926 0 0 787024. 2723.27 0.30 0.04 0.13 -1 -1 0.30 0.0105222 0.00916378 123 65 32 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_070.v common 9.85 vpr 64.05 MiB 0.03 7152 -1 -1 1 0.04 -1 -1 34184 -1 -1 18 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65592 31 32 353 302 1 160 81 17 17 289 -1 unnamed_device 25.2 MiB 5.31 853 13381 4420 7135 1826 64.1 MiB 0.09 0.00 3.47075 -119.995 -3.47075 3.47075 0.88 0.000192776 0.000150994 0.0163016 0.0129391 -1 -1 -1 -1 34 2045 22 6.87369e+06 251529 618332. 2139.56 1.43 0.0697653 0.0568018 25762 151098 -1 1733 21 1033 1932 133986 30887 2.70966 2.70966 -113.156 -2.70966 0 0 787024. 2723.27 0.32 0.05 0.13 -1 -1 0.32 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65860 28 32 332 260 1 180 95 17 17 289 -1 unnamed_device 25.4 MiB 2.04 910 12623 3390 8288 945 64.3 MiB 0.09 0.00 4.19891 -126.139 -4.19891 4.19891 0.86 0.000207099 0.000169791 0.0140662 0.0114999 -1 -1 -1 -1 28 2341 25 6.87369e+06 489084 531479. 1839.03 2.84 0.0843971 0.0696707 24610 126494 -1 2006 18 1450 2389 167831 39763 3.7341 3.7341 -130.294 -3.7341 0 0 648988. 2245.63 0.26 0.06 0.11 -1 -1 0.26 0.0149856 0.0131992 139 34 84 28 28 28 -fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 9.82 vpr 63.48 MiB 0.02 7148 -1 -1 1 0.04 -1 -1 33752 -1 -1 18 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66060 30 32 404 328 1 188 94 17 17 289 -1 unnamed_device 25.7 MiB 2.99 935 16921 4888 8942 3091 64.5 MiB 0.15 0.00 3.55591 -115.746 -3.55591 3.55591 0.97 0.000226366 0.00017879 0.0243287 0.0196111 -1 -1 -1 -1 32 2417 27 6.87369e+06 447163 586450. 2029.24 1.45 0.0757108 0.062121 25474 144626 -1 1907 21 1729 2823 182050 44816 2.83496 2.83496 -110.923 -2.83496 0 0 744469. 2576.02 0.29 0.05 0.12 -1 -1 0.29 0.0138646 0.0119459 141 92 26 26 90 30 -fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 11.37 vpr 64.75 MiB 0.03 7200 -1 -1 1 0.04 -1 -1 34252 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66304 32 32 407 319 1 202 85 17 17 289 -1 unnamed_device 25.9 MiB 6.65 1090 14593 4195 9072 1326 64.8 MiB 0.11 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65892 32 32 407 319 1 202 85 17 17 289 -1 unnamed_device 25.5 MiB 5.86 1089 15151 6141 8127 883 64.3 MiB 0.12 0.00 4.2388 -152.365 -4.2388 4.2388 0.87 0.000245556 0.00019339 0.0217641 0.0175302 -1 -1 -1 -1 34 2813 25 6.87369e+06 293451 618332. 2139.56 1.56 0.0870329 0.0714122 25762 151098 -1 2284 21 1936 3204 224975 50146 3.8064 3.8064 -151.466 -3.8064 0 0 787024. 2723.27 0.30 0.06 0.13 -1 -1 0.30 0.014551 0.0125512 147 65 64 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_089.v common 9.35 vpr 64.21 MiB 0.02 6920 -1 -1 1 0.04 -1 -1 34128 -1 -1 30 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65748 32 32 315 267 1 158 94 17 17 289 -1 unnamed_device 25.5 MiB 4.92 885 16708 5068 9384 2256 64.2 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66460 32 32 399 285 1 232 105 17 17 289 -1 unnamed_device 25.6 MiB 1.58 1421 17642 5571 10308 1763 64.9 MiB 0.16 0.00 4.86064 -164.755 -4.86064 4.86064 0.87 0.000263008 0.000213785 0.0204632 0.0165214 -1 -1 -1 -1 28 3916 26 6.87369e+06 572927 531479. 1839.03 1.92 0.0684584 0.0573019 24610 126494 -1 3082 22 2321 3773 334328 70756 4.99175 4.99175 -173.828 -4.99175 0 0 648988. 2245.63 0.25 0.08 0.11 -1 -1 0.25 0.0163948 0.0142184 183 3 156 32 0 0 -fixed_k6_frac_ripple_N8_22nm.xml mult_094.v common 7.72 vpr 64.30 MiB 0.02 7160 -1 -1 1 0.04 -1 -1 34256 -1 -1 32 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65844 30 32 371 295 1 188 94 17 17 289 -1 unnamed_device 25.7 MiB 3.49 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GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66316 32 32 405 318 1 201 106 17 17 289 -1 unnamed_device 25.7 MiB 3.95 1124 19356 5960 11281 2115 64.8 MiB 0.14 0.00 3.52575 -126.289 -3.52575 3.52575 0.95 0.000231539 0.000181695 0.0207286 0.0164649 -1 -1 -1 -1 28 2720 22 6.87369e+06 586901 531479. 1839.03 0.99 0.0592066 0.0484379 24610 126494 -1 2281 23 1865 2999 197983 46445 2.85366 2.85366 -124.307 -2.85366 0 0 648988. 2245.63 0.27 0.06 0.12 -1 -1 0.27 0.0147338 0.0126694 157 65 63 32 64 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 6.55 vpr 63.94 MiB 0.02 7028 -1 -1 1 0.03 -1 -1 33844 -1 -1 19 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65472 29 32 287 238 1 155 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6.87369e+06 209608 618332. 2139.56 1.36 0.0639777 0.0520625 25762 151098 -1 1734 18 961 1429 108243 23610 2.77096 2.77096 -111.679 -2.77096 0 0 787024. 2723.27 0.30 0.04 0.13 -1 -1 0.30 0.010599 0.00915162 101 82 0 0 82 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 7.30 vpr 64.63 MiB 0.02 7164 -1 -1 1 0.04 -1 -1 34024 -1 -1 39 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66180 31 32 365 281 1 197 102 17 17 289 -1 unnamed_device 25.7 MiB 2.30 1129 19618 5686 11712 2220 64.6 MiB 0.16 0.00 4.1955 -141.345 -4.1955 4.1955 0.89 0.000219606 0.00017348 0.0206175 0.0165582 -1 -1 -1 -1 26 3057 24 6.87369e+06 544980 503264. 1741.40 1.82 0.0670987 0.0559839 24322 120374 -1 2634 18 1808 2912 248656 53210 4.1163 4.1163 -154.166 -4.1163 0 0 618332. 2139.56 0.25 0.07 0.11 -1 -1 0.25 0.0127215 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65684 32 32 314 256 1 168 80 17 17 289 -1 unnamed_device 25.4 MiB 4.82 751 9884 2209 6799 876 64.1 MiB 0.07 0.00 3.54365 -123.521 -3.54365 3.54365 0.88 0.000199945 0.00015956 0.0126742 0.0102434 -1 -1 -1 -1 34 2329 25 6.87369e+06 223581 618332. 2139.56 1.54 0.0700718 0.0578442 25762 151098 -1 1833 20 1450 2403 162142 41252 3.33286 3.33286 -129.55 -3.33286 0 0 787024. 2723.27 0.32 0.05 0.15 -1 -1 0.32 0.0131642 0.0115269 114 34 64 32 32 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 7.99 vpr 64.91 MiB 0.02 7356 -1 -1 1 0.04 -1 -1 34352 -1 -1 35 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66080 32 32 339 283 1 166 80 17 17 289 -1 unnamed_device 25.6 MiB 4.20 885 10744 2853 7291 600 64.5 MiB 0.08 0.00 3.52165 -124.831 -3.52165 3.52165 0.89 0.000192461 0.000151372 0.0143825 0.0115919 -1 -1 -1 -1 32 2324 23 6.87369e+06 223581 586450. 2029.24 0.98 0.0508054 0.0421806 25474 144626 -1 1985 22 1341 2306 170125 38936 3.03826 3.03826 -124.192 -3.03826 0 0 744469. 2576.02 0.30 0.06 0.12 -1 -1 0.30 0.0154408 0.013459 112 63 32 32 62 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 7.99 vpr 64.84 MiB 0.02 6996 -1 -1 1 0.04 -1 -1 34212 -1 -1 40 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66400 32 32 407 319 1 202 104 17 17 289 -1 unnamed_device 25.8 MiB 3.82 1034 13768 3498 9086 1184 64.8 MiB 0.11 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65964 32 32 418 338 1 194 101 17 17 289 -1 unnamed_device 25.5 MiB 2.27 980 17961 5545 9859 2557 64.4 MiB 0.13 0.00 4.28709 -142.511 -4.28709 4.28709 0.86 0.000234881 0.000184997 0.0202386 0.0161602 -1 -1 -1 -1 34 2224 22 6.87369e+06 517032 618332. 2139.56 1.46 0.0842825 0.068848 25762 151098 -1 1870 22 1465 2223 131927 31674 3.606 3.606 -133.315 -3.606 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0149753 0.0128466 147 92 28 28 92 32 -fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 10.08 vpr 64.34 MiB 0.02 7016 -1 -1 1 0.04 -1 -1 33820 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65888 32 32 376 318 1 168 80 17 17 289 -1 unnamed_device 25.6 MiB 5.63 956 12808 4156 7121 1531 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65744 30 32 296 244 1 158 80 17 17 289 -1 unnamed_device 25.3 MiB 1.32 761 12120 5037 6663 420 64.2 MiB 0.08 0.00 3.55905 -117.266 -3.55905 3.55905 0.87 0.00017626 0.000139469 0.0142 0.0114757 -1 -1 -1 -1 32 1841 36 6.87369e+06 251529 586450. 2029.24 0.94 0.0492163 0.0407116 25474 144626 -1 1498 22 1417 2088 130027 30932 3.00236 3.00236 -116.529 -3.00236 0 0 744469. 2576.02 0.30 0.05 0.14 -1 -1 0.30 0.0119945 0.0103626 109 34 60 30 30 30 -fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 6.84 vpr 64.06 MiB 0.02 6868 -1 -1 1 0.04 -1 -1 33816 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65596 32 32 314 256 1 168 80 17 17 289 -1 unnamed_device 25.3 MiB 2.23 871 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65880 27 32 269 226 1 164 80 17 17 289 -1 unnamed_device 25.4 MiB 1.90 736 14528 4306 9196 1026 64.3 MiB 0.09 0.00 3.83226 -109.478 -3.83226 3.83226 0.85 0.000168821 0.000132794 0.0152965 0.0122355 -1 -1 -1 -1 30 2004 33 6.89349e+06 295971 556674. 1926.21 0.96 0.047321 0.0388631 25186 138497 -1 1617 20 1157 1681 96912 23589 3.00146 3.00146 -107.805 -3.00146 0 0 706193. 2443.58 0.28 0.04 0.12 -1 -1 0.28 0.0102131 0.00884307 112 34 54 27 27 27 -fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 5.75 vpr 64.38 MiB 0.02 7072 -1 -1 1 0.04 -1 -1 33712 -1 -1 35 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65928 31 32 317 242 1 187 98 17 17 289 -1 unnamed_device 25.5 MiB 1.15 921 14273 4376 7304 2593 64.4 MiB 0.10 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 331 280 1 215 84 17 17 289 -1 unnamed_device 25.5 MiB 2.55 879 15822 5947 6978 2897 64.4 MiB 0.10 0.00 3.8521 -121.987 -3.8521 3.8521 0.89 0.000196412 0.000155369 0.0188877 0.0151892 -1 -1 -1 -1 34 2631 49 6.89349e+06 281877 618332. 2139.56 1.63 0.0749337 0.0615648 25762 151098 -1 1815 17 1150 1285 88992 22042 3.20001 3.20001 -113.739 -3.20001 0 0 787024. 2723.27 0.32 0.04 0.13 -1 -1 0.32 0.0121447 0.0107 135 65 25 25 64 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_013.v common 6.95 vpr 64.32 MiB 0.03 7300 -1 -1 1 0.04 -1 -1 33588 -1 -1 25 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65864 32 32 386 305 1 240 89 17 17 289 -1 unnamed_device 25.5 MiB 1.78 1132 13751 4297 6849 2605 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66144 32 32 383 303 1 236 89 17 17 289 -1 unnamed_device 25.8 MiB 1.69 1195 12959 3577 7748 1634 64.6 MiB 0.11 0.00 3.72345 -132.536 -3.72345 3.72345 0.91 0.000241694 0.000193082 0.0186371 0.0150399 -1 -1 -1 -1 34 2729 22 6.89349e+06 352346 618332. 2139.56 1.49 0.0838167 0.0690827 25762 151098 -1 2362 21 1803 2277 162810 37088 2.94846 2.94846 -122.186 -2.94846 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0142159 0.0123128 160 57 64 32 56 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 7.96 vpr 64.31 MiB 0.02 7200 -1 -1 1 0.03 -1 -1 33964 -1 -1 22 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65852 32 32 339 284 1 224 86 17 17 289 -1 unnamed_device 25.2 MiB 3.05 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65636 32 32 283 225 1 168 80 17 17 289 -1 unnamed_device 25.2 MiB 1.79 856 14700 5411 7261 2028 64.1 MiB 0.10 0.00 3.66161 -130.921 -3.66161 3.66161 0.87 0.000177824 0.000140661 0.0168182 0.0135649 -1 -1 -1 -1 34 2177 21 6.89349e+06 225501 618332. 2139.56 1.52 0.0675572 0.0561074 25762 151098 -1 1897 21 1382 2387 171811 37083 2.92106 2.92106 -127.327 -2.92106 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0116462 0.010097 114 3 96 32 0 0 -fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 6.93 vpr 64.16 MiB 0.02 7136 -1 -1 1 0.04 -1 -1 34188 -1 -1 19 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65696 31 32 303 249 1 191 82 17 17 289 -1 unnamed_device 25.4 MiB 2.19 976 14322 4714 7465 2143 64.2 MiB 0.10 0.00 3.81397 -130.472 -3.81397 3.81397 0.89 0.000185833 0.000146275 0.0165877 0.0133433 -1 -1 -1 -1 34 2278 30 6.89349e+06 267783 618332. 2139.56 1.47 0.0699933 0.0576751 25762 151098 -1 1938 21 1186 1746 114542 27145 2.89006 2.89006 -118.505 -2.89006 0 0 787024. 2723.27 0.30 0.04 0.14 -1 -1 0.30 0.0117794 0.0102476 121 34 61 31 31 31 -fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 7.02 vpr 64.14 MiB 0.02 7108 -1 -1 1 0.03 -1 -1 33872 -1 -1 23 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65676 29 32 312 264 1 201 84 17 17 289 -1 unnamed_device 25.4 MiB 2.44 1053 14724 4750 7690 2284 64.1 MiB 0.10 0.00 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2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65936 31 32 391 309 1 246 89 17 17 289 -1 unnamed_device 25.5 MiB 3.41 1248 13157 3309 8741 1107 64.4 MiB 0.11 0.00 4.45339 -147.016 -4.45339 4.45339 0.89 0.000221631 0.000175109 0.0167085 0.0134795 -1 -1 -1 -1 34 3100 24 6.89349e+06 366440 618332. 2139.56 1.58 0.0825087 0.0681385 25762 151098 -1 2555 19 1713 2442 149720 36465 3.8506 3.8506 -145.517 -3.8506 0 0 787024. 2723.27 0.32 0.05 0.13 -1 -1 0.32 0.0134436 0.0116491 170 64 60 30 62 31 -fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 8.35 vpr 64.84 MiB 0.02 7372 -1 -1 1 0.04 -1 -1 34396 -1 -1 31 31 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66396 31 32 455 371 1 307 94 17 17 289 -1 unnamed_device 25.8 MiB 3.03 1502 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66324 32 32 424 343 1 279 92 17 17 289 -1 unnamed_device 25.7 MiB 2.53 1256 18722 6037 9946 2739 64.8 MiB 0.14 0.00 4.28929 -144.626 -4.28929 4.28929 0.87 0.000236379 0.000186303 0.0236777 0.0189259 -1 -1 -1 -1 34 3110 23 6.89349e+06 394628 618332. 2139.56 1.42 0.0732182 0.0599722 25762 151098 -1 2659 20 1783 2122 143790 34717 3.2992 3.2992 -130.444 -3.2992 0 0 787024. 2723.27 0.30 0.05 0.13 -1 -1 0.30 0.0143469 0.0124184 185 96 25 25 96 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_049.v common 8.26 vpr 64.65 MiB 0.02 7304 -1 -1 1 0.04 -1 -1 33872 -1 -1 27 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66204 32 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66352 31 32 449 367 1 300 94 17 17 289 -1 unnamed_device 25.9 MiB 2.63 1470 18625 5645 10509 2471 64.8 MiB 0.15 0.00 5.04279 -156.823 -5.04279 5.04279 0.87 0.00024531 0.000193161 0.0235858 0.0188101 -1 -1 -1 -1 34 3368 47 6.89349e+06 436909 618332. 2139.56 1.54 0.101234 0.0823807 25762 151098 -1 2690 20 1877 2226 151581 35363 3.93725 3.93725 -140.668 -3.93725 0 0 787024. 2723.27 0.32 0.05 0.14 -1 -1 0.32 0.015561 0.0135352 195 122 0 0 122 31 -fixed_k6_frac_uripple_N8_22nm.xml mult_054.v common 8.42 vpr 64.53 MiB 0.04 7264 -1 -1 1 0.04 -1 -1 34152 -1 -1 27 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66076 32 32 432 346 1 287 91 17 17 289 -1 unnamed_device 25.7 MiB 3.64 1477 9271 2383 5997 891 64.5 MiB 0.09 0.00 4.63225 -158.944 -4.63225 4.63225 0.89 0.000249436 0.000200627 0.0133427 0.0108658 -1 -1 -1 -1 34 3600 35 6.89349e+06 380534 618332. 2139.56 1.65 0.0826916 0.0675099 25762 151098 -1 2976 22 2460 3565 232523 53347 4.18666 4.18666 -156.524 -4.18666 0 0 787024. 2723.27 0.30 0.07 0.13 -1 -1 0.30 0.0156711 0.0134989 190 94 32 32 94 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_055.v common 6.98 vpr 64.24 MiB 0.02 7044 -1 -1 1 0.03 -1 -1 34028 -1 -1 21 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65784 32 32 312 255 1 198 85 17 17 289 -1 unnamed_device 25.5 MiB 2.33 1085 16081 5241 8837 2003 64.2 MiB 0.11 0.00 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v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65936 32 32 407 319 1 264 90 17 17 289 -1 unnamed_device 25.5 MiB 2.93 1381 17577 5400 9797 2380 64.4 MiB 0.15 0.00 5.10907 -172.718 -5.10907 5.10907 0.89 0.000278374 0.000227814 0.0226901 0.0182244 -1 -1 -1 -1 34 3492 23 6.89349e+06 366440 618332. 2139.56 1.78 0.0934945 0.0775943 25762 151098 -1 2788 20 2119 3010 209008 45498 4.43325 4.43325 -167.168 -4.43325 0 0 787024. 2723.27 0.30 0.07 0.13 -1 -1 0.30 0.0167258 0.0145877 177 65 64 32 64 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 8.04 vpr 64.26 MiB 0.02 7372 -1 -1 1 0.04 -1 -1 33920 -1 -1 30 29 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65800 29 32 387 316 1 251 91 17 17 289 -1 unnamed_device 25.6 MiB 3.34 1289 17431 5289 9749 2393 64.3 MiB 0.13 0.00 4.47765 -137.075 -4.47765 4.47765 0.86 0.000211644 0.000167397 0.0205212 0.0164853 -1 -1 -1 -1 34 2899 29 6.89349e+06 422815 618332. 2139.56 1.47 0.0793412 0.0646242 25762 151098 -1 2542 19 1652 2288 151389 34203 3.3997 3.3997 -122.825 -3.3997 0 0 787024. 2723.27 0.31 0.05 0.13 -1 -1 0.31 0.0144247 0.012619 170 88 26 26 85 29 -fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 5.86 vpr 63.96 MiB 0.02 7020 -1 -1 1 0.04 -1 -1 34084 -1 -1 16 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65500 32 32 283 225 1 168 80 17 17 289 -1 unnamed_device 25.1 MiB 1.15 883 14872 4496 9235 1141 64.0 MiB 0.10 0.00 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65336 31 32 275 220 1 164 80 17 17 289 -1 unnamed_device 25.1 MiB 1.46 719 6444 1413 4474 557 63.8 MiB 0.06 0.00 3.59935 -121.473 -3.59935 3.59935 0.90 0.000172294 0.00013625 0.00813888 0.00664648 -1 -1 -1 -1 28 2235 20 6.89349e+06 239595 531479. 1839.03 0.98 0.0380221 0.0316999 24610 126494 -1 1909 20 1424 2243 170016 39128 3.12946 3.12946 -127.906 -3.12946 0 0 648988. 2245.63 0.26 0.05 0.11 -1 -1 0.26 0.0111476 0.00966853 112 4 93 31 0 0 -fixed_k6_frac_uripple_N8_22nm.xml mult_091.v common 7.04 vpr 64.33 MiB 0.02 7076 -1 -1 1 0.04 -1 -1 33796 -1 -1 25 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65872 32 32 381 303 1 240 89 17 17 289 -1 unnamed_device 25.5 MiB 2.20 1298 18107 5148 10871 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qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65312 29 32 367 293 1 231 87 17 17 289 -1 unnamed_device 25.0 MiB 2.57 1165 15639 4840 8583 2216 63.8 MiB 0.12 0.00 3.69045 -118.464 -3.69045 3.69045 0.90 0.000206669 0.000163271 0.0189307 0.0151556 -1 -1 -1 -1 30 2493 21 6.89349e+06 366440 556674. 1926.21 0.94 0.0573164 0.0475628 25186 138497 -1 2048 22 1565 2117 122502 28169 2.97676 2.97676 -113.932 -2.97676 0 0 706193. 2443.58 0.28 0.04 0.12 -1 -1 0.28 0.0135679 0.0117437 157 62 56 29 58 29 -fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 9.16 vpr 64.58 MiB 0.03 7488 -1 -1 1 0.05 -1 -1 34048 -1 -1 29 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66132 32 32 469 381 1 315 93 17 17 289 -1 unnamed_device 25.7 MiB 2.65 1517 16893 4853 9389 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x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66040 32 32 401 316 1 253 89 17 17 289 -1 unnamed_device 25.6 MiB 2.66 1223 15335 4617 8313 2405 64.5 MiB 0.13 0.00 3.74935 -130.887 -3.74935 3.74935 0.87 0.000224967 0.000178303 0.0201438 0.016268 -1 -1 -1 -1 34 2949 22 6.89349e+06 352346 618332. 2139.56 1.68 0.0925099 0.0771385 25762 151098 -1 2455 21 1607 2192 170274 37420 3.1004 3.1004 -127.579 -3.1004 0 0 787024. 2723.27 0.32 0.06 0.13 -1 -1 0.32 0.0156903 0.0135711 170 65 61 32 64 32 -fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 8.12 vpr 63.69 MiB 0.03 7444 -1 -1 1 0.04 -1 -1 34380 -1 -1 33 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65216 32 32 500 382 1 323 97 17 17 289 -1 unnamed_device 24.9 MiB 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0.0532119 0.0438963 25762 151098 -1 1575 16 677 697 55663 12945 2.31406 2.31406 -91.2888 -2.31406 0 0 787024. 2723.27 0.32 0.03 0.13 -1 -1 0.32 0.00820774 0.00718987 93 56 0 0 53 30 -fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 6.65 vpr 62.88 MiB 0.03 6984 -1 -1 1 0.05 -1 -1 33864 -1 -1 21 30 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64392 30 32 296 244 1 181 83 17 17 289 -1 unnamed_device 23.9 MiB 1.95 936 13763 4424 7248 2091 62.9 MiB 0.09 0.00 4.23979 -138.455 -4.23979 4.23979 0.88 0.000176156 0.000139181 0.0152404 0.0122558 -1 -1 -1 -1 34 2069 19 6.89349e+06 295971 618332. 2139.56 1.39 0.0610836 0.0501228 25762 151098 -1 1752 19 1387 2094 145324 33469 3.41345 3.41345 -131.279 -3.41345 0 0 787024. 2723.27 0.32 0.05 0.14 -1 -1 0.32 0.013382 0.0118796 124 34 60 30 30 30 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9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65140 25 32 251 214 1 162 81 17 17 289 -1 unnamed_device 25.1 MiB 1.69 638 13031 3446 7568 2017 63.6 MiB 0.08 0.00 3.8441 -98.0419 -3.8441 3.8441 0.91 0.000148241 0.000116908 0.0124021 0.00993332 -1 -1 -1 -1 34 1735 20 6.89349e+06 338252 618332. 2139.56 1.35 0.0530287 0.0433486 25762 151098 -1 1462 18 873 1225 71875 17963 3.18111 3.18111 -99.3117 -3.18111 0 0 787024. 2723.27 0.32 0.03 0.13 -1 -1 0.32 0.0093407 0.00808074 107 34 50 25 25 25 -fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 8.87 vpr 64.67 MiB 0.03 7260 -1 -1 1 0.06 -1 -1 34164 -1 -1 28 32 0 0 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 66224 32 32 432 346 1 288 92 17 17 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placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64416 32 32 302 334 1 209 106 17 17 289 -1 unnamed_device 23.9 MiB 0.15 1516 10356 2279 7365 712 62.9 MiB 0.11 0.00 8.73986 -179.719 -8.73986 8.73986 0.36 0.000983572 0.000910051 0.044446 0.0411316 -1 -1 -1 -1 28 4246 29 6.55708e+06 506310 500653. 1732.36 0.99 0.181894 0.159405 21310 115450 -1 3245 18 1360 4616 242551 59872 7.65802 7.65802 -173.385 -7.65802 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0374401 0.0328965 216 208 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_015.v common 2.55 vpr 63.25 MiB 0.04 6640 -1 -1 11 0.20 -1 -1 32412 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 29 32 238 270 1 177 97 17 17 289 -1 unnamed_device 23.5 MiB 0.12 1173 9865 2533 6304 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 32 32 383 303 1 185 102 17 17 289 -1 unnamed_device 24.2 MiB 0.10 1120 15810 4601 9118 2091 63.0 MiB 0.16 0.00 3.5171 -123.44 -3.5171 3.5171 0.31 0.000745322 0.000691087 0.0520892 0.0482761 -1 -1 -1 -1 30 2224 21 6.64007e+06 477204 526063. 1820.29 1.40 0.217198 0.188922 22546 126617 -1 1939 16 1189 1826 115145 26469 3.00017 3.00017 -120.351 -3.00017 0 0 666494. 2306.21 0.03 0.08 0.10 -1 -1 0.03 0.0323529 0.0282406 146 57 64 32 56 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 2.45 vpr 62.86 MiB 0.03 6980 -1 -1 1 0.05 -1 -1 30104 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64372 32 32 339 284 1 162 99 17 17 289 -1 unnamed_device 23.8 MiB 0.11 968 16515 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64484 32 32 337 253 1 196 105 17 17 289 -1 unnamed_device 23.8 MiB 0.07 950 11961 2772 8489 700 63.0 MiB 0.13 0.00 3.50507 -117.309 -3.50507 3.50507 0.32 0.000697058 0.000646752 0.0361771 0.0334978 -1 -1 -1 -1 32 2114 18 6.64007e+06 514878 554710. 1919.41 1.46 0.235517 0.20326 22834 132086 -1 1863 23 1437 2509 146808 35996 2.78877 2.78877 -112.501 -2.78877 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.030771 0.0267278 156 3 124 32 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.58 vpr 63.36 MiB 0.05 7112 -1 -1 1 0.03 -1 -1 30600 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64880 32 32 407 319 1 197 104 17 17 289 -1 unnamed_device 24.4 MiB 0.08 1130 17184 5737 8837 2610 63.4 MiB 0.18 0.00 4.23656 -144.814 -4.23656 4.23656 0.31 0.000767369 0.000711388 0.0569018 0.0527002 -1 -1 -1 -1 32 2274 22 6.64007e+06 502320 554710. 1919.41 0.60 0.147862 0.130636 22834 132086 -1 1992 23 1622 2800 148797 36507 3.81983 3.81983 -142.34 -3.81983 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0334645 0.0290941 157 65 64 32 64 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 3.00 vpr 62.83 MiB 0.04 6916 -1 -1 1 0.03 -1 -1 30204 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64336 32 32 294 246 1 149 82 17 17 289 -1 unnamed_device 23.7 MiB 0.07 840 8270 2111 5830 329 62.8 MiB 0.09 0.00 3.06579 -105.423 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64860 31 32 303 249 1 162 101 17 17 289 -1 unnamed_device 23.6 MiB 0.07 862 11146 2592 7979 575 63.3 MiB 0.11 0.00 3.50687 -115.397 -3.50687 3.50687 0.31 0.000633728 0.000589298 0.0320851 0.0298131 -1 -1 -1 -1 26 2499 26 6.64007e+06 477204 477104. 1650.88 1.95 0.183781 0.15873 21682 110474 -1 1865 22 1267 2178 125582 31798 2.91577 2.91577 -114.15 -2.91577 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.0264303 0.0229425 125 34 61 31 31 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 2.52 vpr 62.75 MiB 0.04 7028 -1 -1 1 0.03 -1 -1 30052 -1 -1 37 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64260 29 32 312 264 1 154 98 17 17 289 -1 unnamed_device 23.6 MiB 0.11 922 17198 5894 8996 2308 62.8 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64652 31 32 391 309 1 194 89 17 17 289 -1 unnamed_device 24.2 MiB 0.08 1079 9197 2284 6348 565 63.1 MiB 0.06 0.00 3.55147 -118.528 -3.55147 3.55147 0.24 0.000335013 0.000306723 0.0173535 0.0159879 -1 -1 -1 -1 32 2150 20 6.64007e+06 326508 554710. 1919.41 1.35 0.199218 0.170874 22834 132086 -1 1941 23 1473 2493 142325 34910 2.90497 2.90497 -115.356 -2.90497 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0327757 0.0285415 155 64 60 30 62 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 2.85 vpr 63.93 MiB 0.05 7300 -1 -1 1 0.03 -1 -1 30632 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65460 31 32 455 371 1 192 88 17 17 289 -1 unnamed_device 24.2 MiB 0.29 1002 14908 5470 7356 2082 63.9 MiB 0.17 0.00 4.45513 -137.3 -4.45513 4.45513 0.31 0.000834144 0.000775325 0.066533 0.0618773 -1 -1 -1 -1 32 2284 27 6.64007e+06 313950 554710. 1919.41 0.61 0.170249 0.150289 22834 132086 -1 1941 20 1342 2354 134944 33685 3.86483 3.86483 -138.007 -3.86483 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0326114 0.0283482 154 124 0 0 124 31 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 3.45 vpr 63.17 MiB 0.05 7124 -1 -1 1 0.03 -1 -1 30416 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 31 32 413 333 1 186 88 17 17 289 -1 unnamed_device 24.2 MiB 0.13 1027 11398 2983 7528 887 63.2 MiB 0.13 0.00 4.38913 -134.67 -4.38913 4.38913 0.34 0.000766712 0.000712184 0.0477711 0.0443788 -1 -1 -1 -1 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 32 32 395 311 1 194 106 17 17 289 -1 unnamed_device 24.1 MiB 0.14 1140 12606 3075 8755 776 63.7 MiB 0.14 0.00 3.50687 -121.034 -3.50687 3.50687 0.31 0.000763907 0.000708181 0.0411347 0.0381036 -1 -1 -1 -1 26 2863 33 6.64007e+06 527436 477104. 1650.88 1.46 0.241988 0.209195 21682 110474 -1 2394 20 1602 2796 167314 41417 2.85057 2.85057 -121.098 -2.85057 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0296906 0.0258573 153 61 64 32 60 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.63 vpr 63.01 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30420 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64524 32 32 405 318 1 200 105 17 17 289 -1 unnamed_device 24.0 MiB 0.12 1167 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 432 346 1 195 89 17 17 289 -1 unnamed_device 24.2 MiB 0.11 1141 15731 4718 8920 2093 63.2 MiB 0.17 0.00 4.14856 -139.91 -4.14856 4.14856 0.32 0.000810138 0.000744827 0.0667672 0.06186 -1 -1 -1 -1 32 2582 17 6.64007e+06 313950 554710. 1919.41 0.58 0.155449 0.137753 22834 132086 -1 2286 22 1613 2975 171935 42030 3.41023 3.41023 -130.66 -3.41023 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0341772 0.0297611 155 94 32 32 94 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 3.34 vpr 62.84 MiB 0.04 6808 -1 -1 1 0.03 -1 -1 30652 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64344 32 32 312 255 1 166 100 17 17 289 -1 unnamed_device 23.8 MiB 0.07 978 17964 4790 11291 1883 62.8 MiB 0.16 0.00 3.50687 -123.607 -3.50687 3.50687 0.31 0.000634391 0.000590427 0.0516727 0.0479857 -1 -1 -1 -1 32 2015 21 6.64007e+06 452088 554710. 1919.41 1.42 0.236854 0.20544 22834 132086 -1 1764 19 1043 1706 104857 24083 2.70957 2.70957 -114.861 -2.70957 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0239623 0.0208695 128 34 63 32 32 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 3.34 vpr 62.99 MiB 0.04 6944 -1 -1 1 0.03 -1 -1 30408 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64504 32 32 370 314 1 164 86 17 17 289 -1 unnamed_device 24.0 MiB 0.14 959 13694 3826 7953 1915 63.0 MiB 0.14 0.00 3.5031 -123.294 -3.5031 3.5031 0.31 0.000703797 0.000653041 0.0533381 0.0495388 -1 -1 -1 -1 32 2054 22 6.64007e+06 276276 554710. 1919.41 1.44 0.254834 0.220755 22834 132086 -1 1866 21 1185 1986 135253 31237 2.75177 2.75177 -114.926 -2.75177 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0284481 0.0247206 125 94 0 0 94 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 3.82 vpr 63.67 MiB 0.05 7264 -1 -1 1 0.03 -1 -1 30804 -1 -1 45 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 469 351 1 233 109 17 17 289 -1 unnamed_device 24.7 MiB 0.11 1361 11809 2725 8268 816 63.7 MiB 0.15 0.00 4.90898 -166.187 -4.90898 4.90898 0.31 0.000882608 0.000821324 0.0432573 0.0401574 -1 -1 -1 -1 26 3708 29 6.64007e+06 565110 477104. 1650.88 1.78 0.258756 0.223516 21682 110474 -1 2936 24 2542 4529 290190 66859 5.02189 5.02189 -184.485 -5.02189 0 0 585099. 2024.56 0.03 0.11 0.09 -1 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65336 32 32 406 330 1 190 102 17 17 289 -1 unnamed_device 24.2 MiB 0.10 992 12478 2933 7679 1866 63.8 MiB 0.11 0.00 4.52516 -135.426 -4.52516 4.52516 0.31 0.000756476 0.000701792 0.0423415 0.0392551 -1 -1 -1 -1 32 2451 20 6.64007e+06 477204 554710. 1919.41 1.84 0.267131 0.230443 22834 132086 -1 2005 18 1132 1883 102007 26645 3.80383 3.80383 -135.287 -3.80383 0 0 701300. 2426.64 0.05 0.07 0.13 -1 -1 0.05 0.0322026 0.0285569 147 88 28 28 88 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 2.57 vpr 63.09 MiB 0.03 7060 -1 -1 1 0.03 -1 -1 30500 -1 -1 44 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64608 32 32 399 285 1 228 108 17 17 289 -1 unnamed_device 24.3 MiB 0.07 1325 21182 6964 11671 2547 63.1 MiB 0.22 0.00 4.95022 -163.573 -4.95022 4.95022 0.31 0.000790751 0.000734727 0.0682016 0.0632932 -1 -1 -1 -1 32 2976 22 6.64007e+06 552552 554710. 1919.41 0.61 0.162701 0.144613 22834 132086 -1 2375 21 1636 2775 149856 36568 4.28689 4.28689 -157.468 -4.28689 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0331594 0.0290767 185 3 156 32 0 0 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 3.63 vpr 63.01 MiB 0.03 7056 -1 -1 1 0.03 -1 -1 30692 -1 -1 39 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64520 30 32 371 295 1 184 101 17 17 289 -1 unnamed_device 24.1 MiB 0.11 895 17726 5089 8956 3681 63.0 MiB 0.16 0.00 3.59647 -113.455 -3.59647 3.59647 0.32 0.000721907 0.000670482 0.0566287 0.0524999 -1 -1 -1 -1 28 2294 25 6.64007e+06 489762 500653. 1732.36 1.75 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 32 32 314 256 1 160 84 17 17 289 -1 unnamed_device 23.7 MiB 0.12 754 13077 3934 6633 2510 62.8 MiB 0.13 0.00 3.59624 -121.098 -3.59624 3.59624 0.31 0.000646421 0.000601399 0.0484737 0.0450874 -1 -1 -1 -1 32 2005 24 6.64007e+06 251160 554710. 1919.41 0.61 0.127184 0.112426 22834 132086 -1 1579 21 1361 2245 147119 38033 2.94077 2.94077 -118.328 -2.94077 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0264705 0.0230795 121 34 64 32 32 32 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.41 vpr 63.13 MiB 0.05 7172 -1 -1 1 0.03 -1 -1 30468 -1 -1 41 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 31 32 387 307 1 189 104 17 17 289 -1 unnamed_device 24.2 MiB 0.13 1070 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64328 30 32 296 244 1 137 80 17 17 289 -1 unnamed_device 23.7 MiB 0.06 686 13152 4141 7190 1821 62.8 MiB 0.14 0.00 3.45727 -110.065 -3.45727 3.45727 0.33 0.000612305 0.000569631 0.0564435 0.0523904 -1 -1 -1 -1 30 1478 23 6.64007e+06 226044 526063. 1820.29 1.01 0.197261 0.17187 22546 126617 -1 1314 19 848 1353 76955 18874 2.64537 2.64537 -102.521 -2.64537 0 0 666494. 2306.21 0.03 0.05 0.10 -1 -1 0.03 0.0232706 0.0202247 100 34 60 30 30 30 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 3.11 vpr 62.86 MiB 0.03 6776 -1 -1 1 0.03 -1 -1 30180 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64364 32 32 314 256 1 167 85 17 17 289 -1 unnamed_device 23.7 MiB 0.08 858 10873 2510 6865 1498 62.9 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64504 32 32 438 350 1 194 102 17 17 289 -1 unnamed_device 24.2 MiB 0.07 979 11288 2565 7046 1677 63.0 MiB 0.11 0.00 4.02833 -135.774 -4.02833 4.02833 0.31 0.000825015 0.000758332 0.0423022 0.0391608 -1 -1 -1 -1 30 2738 22 6.65987e+06 481764 526063. 1820.29 2.54 0.245848 0.213121 22546 126617 -1 1963 23 1686 2764 149139 37885 3.32871 3.32871 -131.231 -3.32871 0 0 666494. 2306.21 0.03 0.08 0.10 -1 -1 0.03 0.0359753 0.0313491 154 96 32 32 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 2.51 vpr 62.99 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30780 -1 -1 26 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64396 31 32 353 302 1 156 97 17 17 289 -1 unnamed_device 23.8 MiB 0.11 797 10753 2302 7921 530 62.9 MiB 0.11 0.00 3.28032 -107.646 -3.28032 3.28032 0.31 0.000689833 0.000634337 0.0363116 0.0336729 -1 -1 -1 -1 26 2397 31 6.65987e+06 431052 477104. 1650.88 0.97 0.12993 0.113818 21682 110474 -1 1782 22 1184 1981 146390 37209 2.87265 2.87265 -111.394 -2.87265 0 0 585099. 2024.56 0.03 0.07 0.09 -1 -1 0.03 0.028321 0.0246033 117 90 0 0 89 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 2.52 vpr 62.88 MiB 0.04 7188 -1 -1 1 0.03 -1 -1 30372 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65064 32 32 496 380 1 232 111 17 17 289 -1 unnamed_device 24.6 MiB 0.12 1279 19795 5512 12343 1940 63.5 MiB 0.21 0.00 4.1355 -142.457 -4.1355 4.1355 0.31 0.00091285 0.000844831 0.0714664 0.0662515 -1 -1 -1 -1 28 3135 37 6.65987e+06 595866 500653. 1732.36 1.76 0.32821 0.284568 21970 115934 -1 2553 20 1888 3079 188802 46009 3.50797 3.50797 -140.761 -3.50797 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0367567 0.0321191 190 96 62 32 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.39 vpr 62.62 MiB 0.05 6916 -1 -1 1 0.03 -1 -1 30488 -1 -1 20 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64312 32 32 395 311 1 194 106 17 17 289 -1 unnamed_device 23.8 MiB 0.12 1147 12856 3159 9034 663 62.8 MiB 0.14 0.00 3.5401 -122.035 -3.5401 3.5401 0.31 0.000764599 0.000710168 0.0417941 0.0387737 -1 -1 -1 -1 28 2774 48 6.65987e+06 532476 500653. 1732.36 1.51 0.264529 0.228282 21970 115934 -1 2432 20 1563 2666 179161 43958 2.82857 2.82857 -120.753 -2.82857 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0299698 0.0261885 153 61 64 32 60 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.60 vpr 63.67 MiB 0.04 7124 -1 -1 1 0.03 -1 -1 30452 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64848 32 32 312 255 1 166 100 17 17 289 -1 unnamed_device 23.7 MiB 0.06 948 13092 3333 8859 900 63.3 MiB 0.12 0.00 3.35364 -114.677 -3.35364 3.35364 0.31 0.000641139 0.00059719 0.0388568 0.036055 -1 -1 -1 -1 30 2033 20 6.65987e+06 456408 526063. 1820.29 1.38 0.201509 0.174371 22546 126617 -1 1762 20 1100 1830 102561 24771 2.56705 2.56705 -108.258 -2.56705 0 0 666494. 2306.21 0.03 0.06 0.10 -1 -1 0.03 0.0251041 0.0218944 128 34 63 32 32 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.38 vpr 62.81 MiB 0.04 7024 -1 -1 1 0.03 -1 -1 30456 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64352 32 32 381 303 1 188 103 17 17 289 -1 unnamed_device 24.0 MiB 0.11 1076 14081 3693 8945 1443 62.8 MiB 0.14 0.00 3.93641 -131.645 -3.93641 3.93641 0.31 0.000742196 0.000690054 0.0458873 0.0426023 -1 -1 -1 -1 26 2525 22 6.65987e+06 494442 477104. 1650.88 0.62 0.133849 0.118097 21682 110474 -1 2205 23 1606 2318 148974 36221 3.64751 3.64751 -134.105 -3.64751 0 0 585099. 2024.56 0.03 0.08 0.09 -1 -1 0.03 0.0330027 0.0287536 145 59 60 32 58 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 2.90 vpr 63.58 MiB 0.05 7300 -1 -1 1 0.03 -1 -1 30472 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 32 32 405 318 1 200 108 17 17 289 -1 unnamed_device 24.2 MiB 0.12 1090 19897 6114 10922 2861 63.6 MiB 0.20 0.00 3.47384 -119.153 -3.47384 3.47384 0.32 0.000776576 0.000721115 0.0625927 0.0580912 -1 -1 -1 -1 30 2598 21 6.65987e+06 557832 526063. 1820.29 1.92 0.283759 0.24621 22546 126617 -1 2057 17 1450 2297 149814 35496 2.74451 2.74451 -113.792 -2.74451 0 0 666494. 2306.21 0.03 0.07 0.10 -1 -1 0.03 0.0276725 0.0243033 160 65 63 32 64 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 2.29 vpr 62.52 MiB 0.05 7024 -1 -1 1 0.03 -1 -1 30404 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 31 32 387 307 1 189 104 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1073 15232 3616 10043 1573 63.0 MiB 0.15 0.00 3.5933 -121.502 -3.5933 3.5933 0.32 0.000747396 0.000694772 0.0492652 0.0457064 -1 -1 -1 -1 26 2279 27 6.65987e+06 519798 477104. 1650.88 0.55 0.144125 0.127084 21682 110474 -1 1906 21 1326 2088 126708 30754 2.79857 2.79857 -113.894 -2.79857 0 0 585099. 2024.56 0.02 0.07 0.09 -1 -1 0.02 0.030524 0.0266578 148 64 58 31 62 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 2.28 vpr 62.66 MiB 0.05 6964 -1 -1 1 0.03 -1 -1 30420 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64164 31 32 308 262 1 147 82 17 17 289 -1 unnamed_device 23.4 MiB 0.11 885 12008 3839 6318 1851 62.7 MiB 0.11 0.00 2.84661 -98.4293 -2.84661 2.84661 0.31 0.000631232 0.000580188 0.0443964 0.0411781 -1 -1 -1 -1 32 1706 22 6.65987e+06 240882 554710. 1919.41 0.52 0.118512 0.104417 22834 132086 -1 1554 22 956 1612 90325 22983 2.62945 2.62945 -101.745 -2.62945 0 0 701300. 2426.64 0.03 0.06 0.08 -1 -1 0.03 0.0263038 0.0228571 110 55 31 31 53 31 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 3.32 vpr 63.18 MiB 0.05 7124 -1 -1 1 0.03 -1 -1 30452 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64700 32 32 383 307 1 184 102 17 17 289 -1 unnamed_device 24.3 MiB 0.11 1058 13430 3540 9051 839 63.2 MiB 0.15 0.00 3.5071 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64340 32 32 407 319 1 198 105 17 17 289 -1 unnamed_device 23.9 MiB 0.11 1080 13937 3664 9212 1061 62.8 MiB 0.15 0.00 3.90984 -134.389 -3.90984 3.90984 0.32 0.000774896 0.000718761 0.046587 0.0431798 -1 -1 -1 -1 28 2591 22 6.65987e+06 519798 500653. 1732.36 0.58 0.139162 0.122734 21970 115934 -1 2361 23 2066 3170 201155 50958 3.71431 3.71431 -142.327 -3.71431 0 0 612192. 2118.31 0.03 0.09 0.10 -1 -1 0.03 0.0339076 0.0295498 158 65 64 32 64 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 2.43 vpr 62.95 MiB 0.05 7192 -1 -1 1 0.03 -1 -1 30504 -1 -1 42 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64460 29 32 367 293 1 183 103 17 17 289 -1 unnamed_device 24.0 MiB 0.10 1000 10948 2708 7481 759 62.9 MiB 0.12 0.00 3.44084 -105.052 -3.44084 3.44084 0.31 0.000707491 0.000658083 0.0347288 0.0322952 -1 -1 -1 -1 32 2041 21 6.65987e+06 532476 554710. 1919.41 0.51 0.118473 0.104115 22834 132086 -1 1850 22 1076 1623 88236 23321 2.81351 2.81351 -106.952 -2.81351 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0302869 0.0263862 144 62 56 29 58 29 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 3.38 vpr 63.86 MiB 0.05 7164 -1 -1 1 0.03 -1 -1 30712 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65392 32 32 469 381 1 200 105 17 17 289 -1 unnamed_device 24.3 MiB 0.16 1096 12949 3437 8756 756 63.9 MiB 0.15 0.00 3.95704 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1234 67713 18322 2.47851 2.47851 -94.3327 -2.47851 0 0 701300. 2426.64 0.03 0.05 0.11 -1 -1 0.03 0.0203558 0.017821 109 4 85 31 0 0 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 3.33 vpr 63.71 MiB 0.05 7176 -1 -1 1 0.03 -1 -1 30396 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65240 32 32 418 338 1 190 102 17 17 289 -1 unnamed_device 24.0 MiB 0.09 1066 12716 3370 8608 738 63.7 MiB 0.14 0.00 4.13067 -135.986 -4.13067 4.13067 0.31 0.000785204 0.000729403 0.0456023 0.0421972 -1 -1 -1 -1 26 2687 32 6.65987e+06 481764 477104. 1650.88 1.50 0.224839 0.194903 21682 110474 -1 2099 23 1423 2143 149237 39624 3.57017 3.57017 -136.957 -3.57017 0 0 585099. 2024.56 0.02 0.08 0.09 -1 -1 0.02 0.0345441 0.0301138 149 92 28 28 92 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 3.20 vpr 62.77 MiB 0.03 7040 -1 -1 1 0.03 -1 -1 30244 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64276 32 32 376 318 1 156 82 17 17 289 -1 unnamed_device 23.6 MiB 0.13 926 13254 4558 6661 2035 62.8 MiB 0.13 0.00 3.55944 -125.789 -3.55944 3.55944 0.31 0.000723045 0.000671323 0.0555964 0.051664 -1 -1 -1 -1 32 1849 23 6.65987e+06 228204 554710. 1919.41 1.41 0.231785 0.201204 22834 132086 -1 1667 17 1110 1612 89987 22309 3.08297 3.08297 -125.343 -3.08297 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0249941 0.0218771 117 96 0 0 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 2.55 vpr 62.93 MiB 0.04 7000 -1 -1 1 0.03 -1 -1 30328 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64436 32 32 401 316 1 196 103 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1003 19142 5741 10397 3004 62.9 MiB 0.18 0.00 3.45184 -118.245 -3.45184 3.45184 0.32 0.000773902 0.000719397 0.063688 0.059114 -1 -1 -1 -1 32 2291 21 6.65987e+06 494442 554710. 1919.41 0.57 0.154084 0.136793 22834 132086 -1 1862 20 1350 2010 115617 29443 2.74451 2.74451 -110.58 -2.74451 0 0 701300. 2426.64 0.03 0.07 0.11 -1 -1 0.03 0.0308957 0.0270872 156 65 61 32 64 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 3.04 vpr 63.47 MiB 0.05 7348 -1 -1 1 0.03 -1 -1 30736 -1 -1 47 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64996 32 32 500 382 1 232 111 17 17 289 -1 unnamed_device 24.4 MiB 0.15 1286 15273 3766 9701 1806 63.5 MiB 0.17 0.00 4.72967 -161.298 -4.72967 4.72967 0.31 0.000917339 0.000851608 0.0561514 0.0521487 -1 -1 -1 -1 26 3444 26 6.65987e+06 595866 477104. 1650.88 0.93 0.17674 0.155699 21682 110474 -1 2751 21 2134 3367 219700 52402 4.79157 4.79157 -170.054 -4.79157 0 0 585099. 2024.56 0.03 0.10 0.09 -1 -1 0.03 0.0383862 0.0335311 190 96 64 32 96 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 2.98 vpr 62.69 MiB 0.04 6768 -1 -1 1 0.03 -1 -1 30160 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64192 30 32 246 229 1 118 80 17 17 289 -1 unnamed_device 23.1 MiB 0.08 541 7132 1642 4789 701 62.7 MiB 0.06 0.00 2.58318 -78.5582 -2.58318 2.58318 0.31 0.00052899 0.000492666 0.0236053 0.0219854 -1 -1 -1 -1 28 1428 32 6.65987e+06 228204 500653. 1732.36 1.30 0.153014 0.131237 21970 115934 -1 1128 14 573 813 60927 17486 1.63745 1.63745 -72.3167 -1.63745 0 0 612192. 2118.31 0.03 0.04 0.10 -1 -1 0.03 0.0158565 0.0138448 86 56 0 0 53 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 2.34 vpr 62.70 MiB 0.04 6916 -1 -1 1 0.03 -1 -1 30448 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64204 30 32 296 244 1 137 80 17 17 289 -1 unnamed_device 23.6 MiB 0.11 646 13152 3617 7215 2320 62.7 MiB 0.11 0.00 3.30481 -102.112 -3.30481 3.30481 0.31 0.000613314 0.000570714 0.0492634 0.0458682 -1 -1 -1 -1 32 1416 19 6.65987e+06 228204 554710. 1919.41 0.50 0.11968 0.106111 22834 132086 -1 1271 19 886 1393 71493 19264 2.61931 2.61931 -98.109 -2.61931 0 0 701300. 2426.64 0.03 0.06 0.11 -1 -1 0.03 0.0249757 0.0218013 100 34 60 30 30 30 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 3.36 vpr 62.68 MiB 0.04 7004 -1 -1 1 0.03 -1 -1 29968 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64180 32 32 314 256 1 167 85 17 17 289 -1 unnamed_device 23.7 MiB 0.08 836 10501 2382 7608 511 62.7 MiB 0.12 0.00 3.4859 -120.54 -3.4859 3.4859 0.31 0.000647384 0.000602776 0.0387371 0.0360456 -1 -1 -1 -1 30 2335 26 6.65987e+06 266238 526063. 1820.29 1.53 0.193827 0.168222 22546 126617 -1 1805 21 1249 2212 113029 28883 2.82977 2.82977 -114.788 -2.82977 0 0 666494. 2306.21 0.03 0.07 0.11 -1 -1 0.03 0.0269704 0.0235565 128 34 64 32 32 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 2.50 vpr 62.52 MiB 0.04 7028 -1 -1 1 0.03 -1 -1 30464 -1 -1 38 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64020 25 32 251 214 1 138 95 17 17 289 -1 unnamed_device 23.4 MiB 0.05 608 15647 3933 10514 1200 62.5 MiB 0.12 0.00 3.31961 -85.6713 -3.31961 3.31961 0.31 0.00053389 0.000496806 0.0406082 0.0376997 -1 -1 -1 -1 26 1766 37 6.65987e+06 481764 477104. 1650.88 0.73 0.115752 0.101381 21682 110474 -1 1384 19 913 1343 87909 24454 2.89271 2.89271 -92.8305 -2.89271 0 0 585099. 2024.56 0.02 0.05 0.09 -1 -1 0.02 0.0201672 0.0175079 106 34 50 25 25 25 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 2.60 vpr 62.96 MiB 0.05 7196 -1 -1 1 0.03 -1 -1 30440 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64472 32 32 432 346 1 193 88 17 17 289 -1 unnamed_device 23.9 MiB 0.12 1105 16078 5546 8034 2498 63.0 MiB 0.18 0.00 3.74158 -129.005 -3.74158 3.74158 0.31 0.000801314 0.00074477 0.0691049 0.0642531 -1 -1 -1 -1 32 2457 23 6.65987e+06 304272 554710. 1919.41 0.59 0.16526 0.14669 22834 132086 -1 2140 21 1584 2875 173957 42583 3.17765 3.17765 -125.504 -3.17765 0 0 701300. 2426.64 0.03 0.08 0.11 -1 -1 0.03 0.0328779 0.0286287 153 94 32 32 94 32 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 3.24 vpr 62.98 MiB 0.05 7296 -1 -1 1 0.03 -1 -1 30324 -1 -1 44 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64496 31 32 421 339 1 193 107 17 17 289 -1 unnamed_device 24.2 MiB 0.07 1092 17817 4773 10666 2378 63.0 MiB 0.17 0.00 3.5303 -118.773 -3.5303 3.5303 0.31 0.000784783 0.000729218 0.058218 0.0538467 -1 -1 -1 -1 28 2470 22 6.65987e+06 557832 500653. 1732.36 1.36 0.256565 0.222613 21970 115934 -1 2103 22 1837 2937 176557 43306 2.92871 2.92871 -116.544 -2.92871 0 0 612192. 2118.31 0.03 0.08 0.10 -1 -1 0.03 0.0329991 0.028701 154 94 29 29 93 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_001.v common 9.05 vpr 64.44 MiB 0.05 7264 -1 -1 1 0.03 -1 -1 30504 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65984 32 32 438 350 1 187 93 17 17 289 -1 unnamed_device 24.7 MiB 0.60 1068 16053 5016 9033 2004 64.4 MiB 0.15 0.00 3.77239 -143.21 -3.77239 3.77239 0.33 0.000819121 0.000752752 0.0650966 0.0603673 -1 -1 -1 -1 42 2696 36 6.95648e+06 419795 744469. 2576.02 6.47 0.380974 0.328752 27202 183097 -1 2317 23 2077 3288 264441 53308 3.91596 3.91596 -150.502 -3.91596 0 0 949917. 3286.91 0.04 0.10 0.14 -1 -1 0.04 0.0355501 0.030934 88 96 32 32 96 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 4.39 vpr 63.74 MiB 0.05 7196 -1 -1 1 0.03 -1 -1 30664 -1 -1 15 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65268 30 32 409 330 1 175 77 17 17 289 -1 unnamed_device 24.8 MiB 1.05 835 12954 5477 7070 407 63.7 MiB 0.13 0.00 3.62689 -126.78 -3.62689 3.62689 0.33 0.000766347 0.000712217 0.0631769 0.0587644 -1 -1 -1 -1 38 2711 25 6.95648e+06 217135 678818. 2348.85 1.37 0.214696 0.187849 26626 170182 -1 2106 22 1943 3061 242645 53045 4.32786 4.32786 -151.679 -4.32786 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 29 32 343 267 1 176 78 17 17 289 -1 unnamed_device 24.5 MiB 0.25 1061 10204 3275 5543 1386 63.4 MiB 0.10 0.00 3.62689 -130.249 -3.62689 3.62689 0.33 0.000680633 0.00063309 0.0445894 0.041492 -1 -1 -1 -1 38 2540 28 6.95648e+06 246087 678818. 2348.85 1.10 0.161726 0.141209 26626 170182 -1 2162 24 1970 3085 253782 52395 3.96316 3.96316 -142.395 -3.96316 0 0 902133. 3121.57 0.04 0.09 0.13 -1 -1 0.04 0.0314043 0.0273255 79 34 87 29 29 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 8.03 vpr 64.37 MiB 0.05 6972 -1 -1 1 0.03 -1 -1 30376 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65916 32 32 376 288 1 187 78 17 17 289 -1 unnamed_device 24.8 MiB 0.35 822 11366 4732 6273 361 64.4 MiB 0.12 0.00 3.66789 -136.565 -3.66789 3.66789 0.33 0.000742769 0.000689984 0.0532242 0.0494887 -1 -1 -1 -1 48 2549 24 6.95648e+06 202660 865456. 2994.66 5.76 0.284945 0.24735 28354 207349 -1 2110 21 2098 3593 283256 62966 3.93316 3.93316 -149.175 -3.93316 0 0 1.05005e+06 3633.38 0.04 0.10 0.16 -1 -1 0.04 0.0314303 0.0275526 79 34 96 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_006.v common 5.73 vpr 63.63 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30420 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65160 32 32 402 316 1 191 97 17 17 289 -1 unnamed_device 24.7 MiB 0.18 1077 14305 4216 7787 2302 63.6 MiB 0.12 0.00 3.01863 -119.444 -3.01863 3.01863 0.33 0.000765737 0.000708851 0.0521861 0.0483024 -1 -1 -1 -1 36 2784 41 6.95648e+06 477698 648988. 2245.63 3.67 0.310116 0.26763 26050 158493 -1 2431 19 1558 2270 202731 44402 3.16582 3.16582 -131.286 -3.16582 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0291793 0.0255119 93 64 63 32 63 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_007.v common 5.46 vpr 63.79 MiB 0.04 6936 -1 -1 1 0.03 -1 -1 30592 -1 -1 14 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65324 27 32 269 226 1 128 73 17 17 289 -1 unnamed_device 24.4 MiB 2.29 577 8129 3070 3829 1230 63.8 MiB 0.07 0.00 2.81185 -90.4167 -2.81185 2.81185 0.33 0.000567839 0.000528502 0.0325119 0.0302887 -1 -1 -1 -1 38 1395 35 6.95648e+06 202660 678818. 2348.85 1.37 0.158645 0.137322 26626 170182 -1 1153 18 916 1438 84006 20348 2.83942 2.83942 -96.2616 -2.83942 0 0 902133. 3121.57 0.03 0.05 0.14 -1 -1 0.03 0.0213373 0.0186289 56 34 54 27 27 27 + fixed_k6_frac_2ripple_N8_22nm.xml mult_008.v common 10.13 vpr 63.84 MiB 0.04 7012 -1 -1 1 0.03 -1 -1 30192 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65368 31 32 317 242 1 178 93 17 17 289 -1 unnamed_device 24.9 MiB 0.17 1057 11013 2654 7318 1041 63.8 MiB 0.10 0.00 2.9463 -110.957 -2.9463 2.9463 0.33 0.00067038 0.000621405 0.0371103 0.0345043 -1 -1 -1 -1 40 2428 25 6.95648e+06 434271 706193. 2443.58 8.04 0.307828 0.264922 26914 176310 -1 2119 24 1315 2149 186842 48456 3.20912 3.20912 -122.667 -3.20912 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0301775 0.0262335 85 4 115 31 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_009.v common 4.83 vpr 63.58 MiB 0.05 7020 -1 -1 1 0.03 -1 -1 30152 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65104 31 32 338 292 1 142 75 17 17 289 -1 unnamed_device 24.6 MiB 0.83 586 8449 2574 4566 1309 63.6 MiB 0.08 0.00 2.81185 -97.8774 -2.81185 2.81185 0.33 0.000668743 0.000621811 0.0381379 0.0354913 -1 -1 -1 -1 44 1586 30 6.95648e+06 173708 787024. 2723.27 2.17 0.237151 0.20446 27778 195446 -1 1104 20 825 1227 84252 23016 2.94562 2.94562 -102.672 -2.94562 0 0 997811. 3452.63 0.04 0.06 0.16 -1 -1 0.04 0.0263065 0.0229401 57 85 0 0 84 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_010.v common 4.82 vpr 63.41 MiB 0.05 6848 -1 -1 1 0.03 -1 -1 30272 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 32 32 314 256 1 156 75 17 17 289 -1 unnamed_device 24.3 MiB 0.79 627 9871 4078 5538 255 63.4 MiB 0.10 0.00 2.97205 -115.921 -2.97205 2.97205 0.34 0.000647028 0.0006013 0.0438341 0.0408459 -1 -1 -1 -1 42 1803 27 6.95648e+06 159232 744469. 2576.02 2.15 0.268233 0.23105 27202 183097 -1 1493 23 1574 2212 156517 37213 2.93652 2.93652 -121.97 -2.93652 0 0 949917. 3286.91 0.04 0.07 0.14 -1 -1 0.04 0.0289656 0.0252216 63 34 64 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_011.v common 5.95 vpr 63.62 MiB 0.05 7048 -1 -1 1 0.03 -1 -1 30160 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65152 30 32 325 273 1 146 75 17 17 289 -1 unnamed_device 24.6 MiB 0.86 754 9397 3857 5236 304 63.6 MiB 0.09 0.00 2.95005 -111.061 -2.95005 2.95005 0.33 0.000644862 0.000599321 0.0406386 0.0377981 -1 -1 -1 -1 32 2003 39 6.95648e+06 188184 586450. 2029.24 3.23 0.271513 0.234061 25474 144626 -1 1696 21 1434 2017 171701 37391 3.20012 3.20012 -125.609 -3.20012 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0266087 0.0231499 61 63 30 30 60 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_012.v common 8.43 vpr 63.57 MiB 0.05 6940 -1 -1 1 0.03 -1 -1 30404 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 32 32 331 280 1 150 82 17 17 289 -1 unnamed_device 24.6 MiB 0.52 812 11118 3920 5250 1948 63.6 MiB 0.10 0.00 2.9793 -108.709 -2.9793 2.9793 0.33 0.000663809 0.000617097 0.0433514 0.0403456 -1 -1 -1 -1 34 2568 40 6.95648e+06 260562 618332. 2139.56 6.06 0.321941 0.276426 25762 151098 -1 1997 23 1324 2070 202850 43814 3.33157 3.33157 -128.102 -3.33157 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65344 32 32 407 319 1 192 94 17 17 289 -1 unnamed_device 24.8 MiB 0.60 836 13939 4431 7094 2414 63.8 MiB 0.13 0.00 3.86969 -139.597 -3.86969 3.86969 0.33 0.000781202 0.00072361 0.0540096 0.0501271 -1 -1 -1 -1 48 2382 47 6.95648e+06 434271 865456. 2994.66 2.91 0.339439 0.293708 28354 207349 -1 1936 22 2028 3003 232916 52891 4.27316 4.27316 -150.988 -4.27316 0 0 1.05005e+06 3633.38 0.04 0.05 0.12 -1 -1 0.04 0.0181227 0.0160795 90 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_015.v common 3.53 vpr 63.25 MiB 0.04 6956 -1 -1 1 0.03 -1 -1 30664 -1 -1 14 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64768 29 32 272 228 1 138 75 17 17 289 -1 unnamed_device 24.3 MiB 0.47 566 7975 3221 4328 426 63.2 MiB 0.07 0.00 2.93836 -96.7018 -2.93836 2.93836 0.33 0.000579085 0.000538813 0.0311578 0.0289894 -1 -1 -1 -1 42 1839 31 6.95648e+06 202660 744469. 2576.02 1.21 0.15386 0.133224 27202 183097 -1 1249 21 1035 1597 116659 31176 3.08382 3.08382 -109.335 -3.08382 0 0 949917. 3286.91 0.04 0.06 0.14 -1 -1 0.04 0.0240087 0.0208894 57 29 58 29 24 24 + fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 9.88 vpr 64.35 MiB 0.04 7192 -1 -1 1 0.03 -1 -1 30420 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65896 32 32 401 315 1 186 78 17 17 289 -1 unnamed_device 24.8 MiB 1.16 1051 6718 1470 4903 345 64.4 MiB 0.08 0.00 2.93285 -118.01 -2.93285 2.93285 0.33 0.000766349 0.0007122 0.0337949 0.0314084 -1 -1 -1 -1 40 2582 20 6.95648e+06 202660 706193. 2443.58 6.81 0.326427 0.281084 26914 176310 -1 2318 21 1946 3047 245185 52239 3.19032 3.19032 -129.521 -3.19032 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0315594 0.0275657 79 63 64 32 62 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 8.08 vpr 64.39 MiB 0.04 7100 -1 -1 1 0.03 -1 -1 30292 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 32 32 383 303 1 179 93 17 17 289 -1 unnamed_device 24.9 MiB 1.10 807 7443 1468 5595 380 64.4 MiB 0.08 0.00 3.0804 -116.29 -3.0804 3.0804 0.33 0.000743967 0.00068945 0.0294348 0.0269957 -1 -1 -1 -1 40 2287 38 6.95648e+06 419795 706193. 2443.58 5.09 0.329903 0.283274 26914 176310 -1 1865 24 1671 2241 168965 43042 3.42677 3.42677 -133.373 -3.42677 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0341624 0.0297364 83 57 64 32 56 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_018.v common 6.98 vpr 63.63 MiB 0.04 7088 -1 -1 1 0.03 -1 -1 30068 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65160 32 32 339 284 1 156 85 17 17 289 -1 unnamed_device 24.6 MiB 0.56 700 10687 3483 5569 1635 63.6 MiB 0.09 0.00 2.22111 -90.2873 -2.22111 2.22111 0.33 0.000670523 0.000622423 0.0409654 0.0380687 -1 -1 -1 -1 38 1911 29 6.95648e+06 303989 678818. 2348.85 4.56 0.280097 0.241158 26626 170182 -1 1497 28 1606 2322 200743 56036 2.19418 2.19418 -95.8841 -2.19418 0 0 902133. 3121.57 0.03 0.10 0.14 -1 -1 0.03 0.0347281 0.0300728 69 65 29 29 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_019.v common 3.85 vpr 63.71 MiB 0.04 6752 -1 -1 1 0.03 -1 -1 30184 -1 -1 12 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65240 30 32 226 208 1 116 74 17 17 289 -1 unnamed_device 24.3 MiB 0.14 714 10149 3183 6390 576 63.7 MiB 0.08 0.00 2.21746 -84.2994 -2.21746 2.21746 0.33 0.000510843 0.000475833 0.0346548 0.0322729 -1 -1 -1 -1 38 1456 26 6.95648e+06 173708 678818. 2348.85 1.91 0.186234 0.160283 26626 170182 -1 1292 20 731 961 83650 19590 2.05938 2.05938 -89.0505 -2.05938 0 0 902133. 3121.57 0.03 0.05 0.13 -1 -1 0.03 0.0200003 0.0173963 46 34 24 24 30 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_020.v common 9.11 vpr 63.62 MiB 0.05 7060 -1 -1 1 0.03 -1 -1 30540 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65152 31 32 335 280 1 151 75 17 17 289 -1 unnamed_device 24.6 MiB 0.74 615 9397 3718 5138 541 63.6 MiB 0.09 0.00 2.93905 -108.96 -2.93905 2.93905 0.33 0.000657083 0.000609906 0.0414978 0.0386046 -1 -1 -1 -1 38 2293 48 6.95648e+06 173708 678818. 2348.85 6.66 0.355163 0.305281 26626 170182 -1 1458 20 1336 2012 153236 36799 3.14792 3.14792 -120.423 -3.14792 0 0 902133. 3121.57 0.03 0.04 0.10 -1 -1 0.03 0.0149913 0.0133587 63 64 31 31 62 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 8.10 vpr 64.19 MiB 0.04 6944 -1 -1 1 0.03 -1 -1 30128 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65732 32 32 366 283 1 184 93 17 17 289 -1 unnamed_device 24.5 MiB 0.25 997 17103 6265 8394 2444 64.2 MiB 0.14 0.00 3.69567 -136.934 -3.69567 3.69567 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64736 32 32 294 246 1 146 75 17 17 289 -1 unnamed_device 24.2 MiB 0.62 578 10819 4344 5833 642 63.2 MiB 0.09 0.00 2.9374 -102.673 -2.9374 2.9374 0.33 0.000617179 0.000573951 0.0445039 0.0414198 -1 -1 -1 -1 40 2030 34 6.95648e+06 159232 706193. 2443.58 2.41 0.179381 0.156219 26914 176310 -1 1381 23 1086 1653 119084 31432 3.02602 3.02602 -112.76 -3.02602 0 0 926341. 3205.33 0.04 0.06 0.14 -1 -1 0.04 0.0273198 0.0237438 58 34 54 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_030.v common 7.03 vpr 63.46 MiB 0.04 6980 -1 -1 1 0.03 -1 -1 30284 -1 -1 13 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65264 29 32 312 264 1 148 84 17 17 289 -1 unnamed_device 24.6 MiB 0.31 635 11064 3909 4785 2370 63.7 MiB 0.09 0.00 2.21891 -81.6895 -2.21891 2.21891 0.33 0.000623436 0.000578988 0.039937 0.0370801 -1 -1 -1 -1 40 1902 46 6.95648e+06 332941 706193. 2443.58 5.55 0.317169 0.271688 26914 176310 -1 1570 27 1498 2404 191874 48434 2.31468 2.31468 -91.5414 -2.31468 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0312514 0.0270471 68 61 29 29 57 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_035.v common 5.37 vpr 64.55 MiB 0.05 7212 -1 -1 1 0.03 -1 -1 30488 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66104 32 32 423 310 1 219 101 17 17 289 -1 unnamed_device 24.8 MiB 0.45 1182 15141 4783 8004 2354 64.6 MiB 0.14 0.00 3.79319 -141.215 -3.79319 3.79319 0.33 0.000835201 0.00076864 0.0565569 0.0524524 -1 -1 -1 -1 44 3177 26 6.95648e+06 535600 787024. 2723.27 2.97 0.346037 0.299004 27778 195446 -1 2566 22 2200 3706 303319 62532 3.75956 3.75956 -147.814 -3.75956 0 0 997811. 3452.63 0.04 0.10 0.15 -1 -1 0.04 0.0355552 0.031018 107 29 128 32 27 27 + fixed_k6_frac_2ripple_N8_22nm.xml mult_036.v common 4.96 vpr 64.28 MiB 0.05 7128 -1 -1 1 0.03 -1 -1 30384 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65824 32 32 403 317 1 190 96 17 17 289 -1 unnamed_device 24.7 MiB 0.67 1060 16083 4486 9706 1891 64.3 MiB 0.14 0.00 3.02515 -122.785 -3.02515 3.02515 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31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66100 31 32 455 371 1 184 78 17 17 289 -1 unnamed_device 24.9 MiB 1.50 845 13524 5793 7234 497 64.6 MiB 0.14 0.00 3.79794 -133.542 -3.79794 3.79794 0.33 0.000826826 0.000767866 0.0704672 0.0655095 -1 -1 -1 -1 40 2621 30 6.95648e+06 217135 706193. 2443.58 1.31 0.215857 0.189013 26914 176310 -1 2112 26 2232 3557 295737 79592 4.39226 4.39226 -155.198 -4.39226 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0400289 0.0346379 81 124 0 0 124 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_040.v common 8.74 vpr 63.83 MiB 0.05 7260 -1 -1 1 0.03 -1 -1 30448 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65864 31 32 395 311 1 188 98 17 17 289 -1 unnamed_device 24.8 MiB 0.39 989 16748 5604 8391 2753 64.3 MiB 0.15 0.00 3.79506 -135.536 -3.79506 3.79506 0.33 0.000757519 0.000701627 0.059186 0.0547998 -1 -1 -1 -1 40 2470 25 6.95648e+06 506649 706193. 2443.58 1.23 0.193225 0.169288 26914 176310 -1 2238 31 2339 3708 347876 92384 4.08526 4.08526 -147.457 -4.08526 0 0 926341. 3205.33 0.03 0.09 0.10 -1 -1 0.03 0.0229175 0.0200935 94 64 62 31 62 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 9.83 vpr 64.24 MiB 0.05 7192 -1 -1 1 0.03 -1 -1 30516 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65780 32 32 397 313 1 188 97 17 17 289 -1 unnamed_device 24.8 MiB 0.37 1148 16303 5501 8667 2135 64.2 MiB 0.15 0.00 3.03615 -120.283 -3.03615 3.03615 0.33 0.000762575 0.000706804 0.0585653 0.0542728 -1 -1 -1 -1 40 3009 39 6.95648e+06 477698 706193. 2443.58 7.50 0.334194 0.28839 26914 176310 -1 2538 23 1940 3291 262378 55301 3.13692 3.13692 -127.574 -3.13692 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0336333 0.029197 90 63 62 32 62 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_047.v common 5.99 vpr 64.25 MiB 0.05 7092 -1 -1 1 0.03 -1 -1 30516 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65788 32 32 345 257 1 187 78 17 17 289 -1 unnamed_device 24.6 MiB 0.72 808 11532 4802 6262 468 64.2 MiB 0.11 0.00 3.66789 -136.287 -3.66789 3.66789 0.33 0.000707703 0.000657989 0.0517912 0.0481796 -1 -1 -1 -1 50 2475 27 6.95648e+06 202660 902133. 3121.57 3.27 0.284452 0.246852 28642 213929 -1 2091 25 1980 3343 311147 72023 4.03826 4.03826 -147.211 -4.03826 0 0 1.08113e+06 3740.92 0.04 0.10 0.17 -1 -1 0.04 0.03405 0.0297223 79 3 128 32 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_048.v common 10.76 vpr 63.57 MiB 0.04 7312 -1 -1 1 0.03 -1 -1 30428 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65100 32 32 424 343 1 182 96 17 17 289 -1 unnamed_device 24.7 MiB 1.02 1065 16521 4546 10556 1419 63.6 MiB 0.14 0.00 3.1848 -124.83 -3.1848 3.1848 0.33 0.000785387 0.000728964 0.0617577 0.0572851 -1 -1 -1 -1 38 2687 33 6.95648e+06 463222 678818. 2348.85 7.75 0.368946 0.319487 26626 170182 -1 2320 22 1567 2540 210400 44525 3.66637 3.66637 -135.719 -3.66637 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0336424 0.0293054 87 96 25 25 96 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_049.v common 7.18 vpr 63.57 MiB 0.02 7124 -1 -1 1 0.03 -1 -1 30252 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65092 32 32 395 311 1 186 99 17 17 289 -1 unnamed_device 24.8 MiB 0.50 1083 9903 2382 6922 599 63.6 MiB 0.10 0.00 3.01415 -121.42 -3.01415 3.01415 0.33 0.000772534 0.000710303 0.0358282 0.0332014 -1 -1 -1 -1 44 2470 21 6.95648e+06 506649 787024. 2723.27 4.75 0.297318 0.256316 27778 195446 -1 2151 19 1429 2157 174479 36240 2.78492 2.78492 -121.017 -2.78492 0 0 997811. 3452.63 0.04 0.07 0.15 -1 -1 0.04 0.0288609 0.0252417 90 61 64 32 60 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_050.v common 5.43 vpr 64.67 MiB 0.05 7044 -1 -1 1 0.03 -1 -1 30440 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66224 32 32 405 318 1 192 96 17 17 289 -1 unnamed_device 25.1 MiB 0.39 855 12579 3955 6361 2263 64.7 MiB 0.11 0.00 3.07535 -115.588 -3.07535 3.07535 0.33 0.000772691 0.000715687 0.0472455 0.0437473 -1 -1 -1 -1 52 2408 35 6.95648e+06 463222 926341. 3205.33 3.06 0.300148 0.259567 29218 227130 -1 1649 23 1921 2960 212859 52816 2.98672 2.98672 -119.129 -2.98672 0 0 1.14541e+06 3963.36 0.04 0.09 0.18 -1 -1 0.04 0.0340922 0.0297115 92 65 63 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_051.v common 8.45 vpr 64.41 MiB 0.05 7064 -1 -1 1 0.03 -1 -1 30688 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65956 32 32 376 288 1 186 95 17 17 289 -1 unnamed_device 24.8 MiB 0.51 904 11975 3915 5851 2209 64.4 MiB 0.11 0.00 3.80196 -138.017 -3.80196 3.80196 0.33 0.000744874 0.000691059 0.0437331 0.0405233 -1 -1 -1 -1 54 2450 40 6.95648e+06 448746 949917. 3286.91 5.92 0.36777 0.316519 29506 232905 -1 2084 23 1932 3144 338376 81728 3.85486 3.85486 -141.939 -3.85486 0 0 1.17392e+06 4061.99 0.04 0.11 0.19 -1 -1 0.04 0.0326879 0.0285039 88 34 96 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_052.v common 4.84 vpr 64.45 MiB 0.05 7040 -1 -1 1 0.03 -1 -1 30588 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65992 32 32 407 319 1 189 97 17 17 289 -1 unnamed_device 24.8 MiB 0.63 835 16303 5172 8841 2290 64.4 MiB 0.14 0.00 3.71319 -134.96 -3.71319 3.71319 0.33 0.000775862 0.000713547 0.0593351 0.0549642 -1 -1 -1 -1 38 2726 37 6.95648e+06 477698 678818. 2348.85 2.25 0.230379 0.20089 26626 170182 -1 2109 24 2198 3267 259879 60536 4.32506 4.32506 -159.241 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14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 32 32 432 346 1 187 78 17 17 289 -1 unnamed_device 24.8 MiB 0.54 837 12860 5438 7034 388 64.4 MiB 0.13 0.00 3.61409 -131.006 -3.61409 3.61409 0.33 0.000804261 0.00074721 0.0651314 0.0605464 -1 -1 -1 -1 42 2696 47 6.95648e+06 202660 744469. 2576.02 2.54 0.351541 0.304643 27202 183097 -1 2067 22 1762 3011 226876 51341 3.83296 3.83296 -139.071 -3.83296 0 0 949917. 3286.91 0.04 0.09 0.15 -1 -1 0.04 0.0346853 0.0302318 79 94 32 32 94 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_055.v common 10.65 vpr 63.37 MiB 0.04 6880 -1 -1 1 0.03 -1 -1 30520 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64888 32 32 312 255 1 160 90 17 17 289 -1 unnamed_device 24.5 MiB 0.14 768 14160 5227 6971 1962 63.4 MiB 0.11 0.00 2.94515 -113.956 -2.94515 2.94515 0.33 0.000637754 0.000590834 0.0472694 0.0438506 -1 -1 -1 -1 36 2903 45 6.95648e+06 376368 648988. 2245.63 8.65 0.303775 0.262638 26050 158493 -1 2089 22 1714 2771 272804 63076 3.24022 3.24022 -130.142 -3.24022 0 0 828058. 2865.25 0.03 0.09 0.13 -1 -1 0.03 0.0274157 0.0238458 73 34 63 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_056.v common 7.99 vpr 63.60 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30408 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65124 32 32 370 314 1 158 76 17 17 289 -1 unnamed_device 24.6 MiB 0.62 633 7596 1852 4646 1098 63.6 MiB 0.09 0.00 2.95805 -110.254 -2.95805 2.95805 0.34 0.000721358 0.00067093 0.0362416 0.0337131 -1 -1 -1 -1 50 1624 23 6.95648e+06 173708 902133. 3121.57 5.45 0.315953 0.271561 28642 213929 -1 1343 21 1345 2022 156849 37822 3.07172 3.07172 -118.613 -3.07172 0 0 1.08113e+06 3740.92 0.04 0.07 0.17 -1 -1 0.04 0.0289241 0.0252175 64 94 0 0 94 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_057.v common 18.28 vpr 64.62 MiB 0.04 7296 -1 -1 1 0.03 -1 -1 30848 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66168 32 32 469 351 1 223 98 17 17 289 -1 unnamed_device 25.0 MiB 0.45 1114 17423 6179 8626 2618 64.6 MiB 0.17 0.00 4.52726 -161.049 -4.52726 4.52726 0.33 0.000881204 0.000815262 0.0715494 0.0663738 -1 -1 -1 -1 50 3235 42 6.95648e+06 492173 902133. 3121.57 15.74 0.483072 0.417301 28642 213929 -1 2528 22 2389 3979 344470 76256 4.91551 4.91551 -173.271 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26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65040 32 32 345 287 1 155 90 17 17 289 -1 unnamed_device 24.5 MiB 0.97 694 11949 4515 6462 972 63.5 MiB 0.11 0.00 3.00763 -115.231 -3.00763 3.00763 0.33 0.000695616 0.000640177 0.04302 0.039867 -1 -1 -1 -1 42 2166 27 6.95648e+06 376368 744469. 2576.02 2.56 0.272814 0.234896 27202 183097 -1 1684 20 1439 2147 181429 42594 3.08572 3.08572 -123.618 -3.08572 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0267147 0.0233462 71 65 32 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_070.v common 6.71 vpr 63.63 MiB 0.05 7032 -1 -1 1 0.03 -1 -1 30444 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65156 31 32 353 302 1 146 75 17 17 289 -1 unnamed_device 24.6 MiB 0.93 612 8291 3398 4596 297 63.6 MiB 0.08 0.00 2.91705 -106.629 -2.91705 2.91705 0.33 0.00068008 0.00063168 0.0378053 0.0351459 -1 -1 -1 -1 46 1854 29 6.95648e+06 173708 828058. 2865.25 3.91 0.276337 0.237262 28066 200906 -1 1470 31 1482 2490 232383 80656 3.06512 3.06512 -114.478 -3.06512 0 0 1.01997e+06 3529.29 0.04 0.11 0.16 -1 -1 0.04 0.0377265 0.0326056 61 90 0 0 89 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_071.v common 4.45 vpr 64.16 MiB 0.05 7068 -1 -1 1 0.03 -1 -1 30472 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65704 30 32 374 297 1 178 96 17 17 289 -1 unnamed_device 24.5 MiB 0.40 821 14769 4586 7579 2604 64.2 MiB 0.13 0.00 3.02515 -108.016 -3.02515 3.02515 0.33 0.000722641 0.0006702 0.0511161 0.0473837 -1 -1 -1 -1 46 2030 27 6.95648e+06 492173 828058. 2865.25 2.07 0.267387 0.230902 28066 200906 -1 1721 23 1567 2496 164396 39597 3.13882 3.13882 -114.694 -3.13882 0 0 1.01997e+06 3529.29 0.04 0.08 0.16 -1 -1 0.04 0.0317639 0.0276667 87 60 60 30 57 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_072.v common 4.81 vpr 63.64 MiB 0.04 7108 -1 -1 1 0.03 -1 -1 30380 -1 -1 36 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 28 32 332 260 1 172 96 17 17 289 -1 unnamed_device 24.7 MiB 0.30 750 17397 5782 8505 3110 63.6 MiB 0.13 0.00 3.71919 -117.682 -3.71919 3.71919 0.33 0.000645624 0.000598523 0.0553633 0.0513525 -1 -1 -1 -1 44 2211 25 6.95648e+06 521125 787024. 2723.27 2.53 0.259532 0.224903 27778 195446 -1 1780 22 1725 3075 257842 57336 3.72466 3.72466 -122.473 -3.72466 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65212 32 32 361 308 1 152 76 17 17 289 -1 unnamed_device 24.7 MiB 0.76 616 9196 3757 5077 362 63.7 MiB 0.05 0.00 2.84485 -103.916 -2.84485 2.84485 0.26 0.000304913 0.000279654 0.0197365 0.018182 -1 -1 -1 -1 46 1840 34 6.95648e+06 173708 828058. 2865.25 4.33 0.250391 0.213816 28066 200906 -1 1394 35 1497 2433 166296 41613 2.87532 2.87532 -111.17 -2.87532 0 0 1.01997e+06 3529.29 0.04 0.09 0.16 -1 -1 0.04 0.0433451 0.0374291 62 91 0 0 91 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_075.v common 10.20 vpr 64.43 MiB 0.05 6980 -1 -1 1 0.03 -1 -1 30444 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65980 31 32 335 251 1 188 95 17 17 289 -1 unnamed_device 24.7 MiB 0.13 1144 16511 5176 9723 1612 64.4 MiB 0.15 0.00 3.78219 -141.259 -3.78219 3.78219 0.33 0.0006922 0.000642311 0.0556803 0.051684 -1 -1 -1 -1 44 2822 26 6.95648e+06 463222 787024. 2723.27 8.06 0.304996 0.264291 27778 195446 -1 2340 24 2046 3336 296556 60315 3.98996 3.98996 -154.33 -3.98996 0 0 997811. 3452.63 0.04 0.10 0.16 -1 -1 0.04 0.0322218 0.0281051 92 4 124 31 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_076.v common 6.62 vpr 63.82 MiB 0.05 7100 -1 -1 1 0.03 -1 -1 30572 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65348 32 32 407 319 1 189 94 17 17 289 -1 unnamed_device 24.9 MiB 1.00 864 17134 7233 9262 639 63.8 MiB 0.15 0.00 3.74919 -137.193 -3.74919 3.74919 0.33 0.000780148 0.000717018 0.0650585 0.060269 -1 -1 -1 -1 52 2894 39 6.95648e+06 434271 926341. 3205.33 3.57 0.344887 0.299059 29218 227130 -1 2047 22 1993 3508 286773 66388 3.87496 3.87496 -144.842 -3.87496 0 0 1.14541e+06 3963.36 0.04 0.10 0.18 -1 -1 0.04 0.0329266 0.0287273 89 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_077.v common 5.94 vpr 63.82 MiB 0.05 7240 -1 -1 1 0.03 -1 -1 30488 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65352 32 32 407 319 1 187 93 17 17 289 -1 unnamed_device 24.9 MiB 1.14 894 17313 6821 8964 1528 63.8 MiB 0.16 0.00 3.81339 -139.726 -3.81339 3.81339 0.33 0.000783383 0.000727232 0.0673179 0.0624753 -1 -1 -1 -1 48 2550 23 6.95648e+06 419795 865456. 2994.66 2.79 0.321209 0.279312 28354 207349 -1 2170 24 2069 3371 308547 67749 4.02226 4.02226 -149.506 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/home/elgamma8/research/release/vtr-verilog-to-routing 65908 30 32 383 303 1 183 78 17 17 289 -1 unnamed_device 24.9 MiB 0.34 893 10702 4147 4571 1984 64.4 MiB 0.11 0.00 3.73035 -132.73 -3.73035 3.73035 0.33 0.000734314 0.000682468 0.0501984 0.0466866 -1 -1 -1 -1 34 2877 46 6.95648e+06 231611 618332. 2139.56 4.53 0.360062 0.310152 25762 151098 -1 2294 23 2043 2959 254014 56227 4.50466 4.50466 -154.048 -4.50466 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0329306 0.0287016 79 63 60 30 60 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_081.v common 13.33 vpr 64.45 MiB 0.05 7156 -1 -1 1 0.03 -1 -1 30832 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65992 32 32 469 381 1 190 99 17 17 289 -1 unnamed_device 24.9 MiB 1.08 1057 9675 2493 6229 953 64.4 MiB 0.10 0.00 3.83239 -141.999 -3.83239 3.83239 0.33 0.000852539 0.000791956 0.0391889 0.0364065 -1 -1 -1 -1 40 2810 26 6.95648e+06 506649 706193. 2443.58 10.27 0.400508 0.344736 26914 176310 -1 2406 25 2230 3734 317253 67036 4.36886 4.36886 -157.59 -4.36886 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0391247 0.0338521 92 127 0 0 128 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_082.v common 5.18 vpr 64.53 MiB 0.05 7196 -1 -1 1 0.03 -1 -1 30748 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66080 31 32 425 341 1 182 92 17 17 289 -1 unnamed_device 24.9 MiB 0.56 804 12926 4797 6175 1954 64.5 MiB 0.12 0.00 3.77419 -132.789 -3.77419 3.77419 0.33 0.000781678 0.000724755 0.05182 0.0480111 -1 -1 -1 -1 46 2386 39 6.95648e+06 419795 828058. 2865.25 2.65 0.323566 0.279626 28066 200906 -1 1742 26 2024 3121 217542 56896 3.81746 3.81746 -137.751 -3.81746 0 0 1.01997e+06 3529.29 0.04 0.10 0.16 -1 -1 0.04 0.0375528 0.0326026 87 94 31 31 93 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_083.v common 4.88 vpr 64.39 MiB 0.05 7268 -1 -1 1 0.03 -1 -1 30612 -1 -1 30 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65936 30 32 404 328 1 172 92 17 17 289 -1 unnamed_device 24.8 MiB 0.71 784 11684 3303 6454 1927 64.4 MiB 0.11 0.00 3.06483 -107.982 -3.06483 3.06483 0.33 0.000752562 0.000698047 0.0453498 0.0421498 -1 -1 -1 -1 44 1986 32 6.95648e+06 434271 787024. 2723.27 2.16 0.283655 0.244503 27778 195446 -1 1633 25 1707 2674 178629 42997 2.96332 2.96332 -111.845 -2.96332 0 0 997811. 3452.63 0.04 0.08 0.16 -1 -1 0.04 0.0352125 0.0305304 82 92 26 26 90 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_084.v common 10.29 vpr 63.78 MiB 0.05 7204 -1 -1 1 0.03 -1 -1 30504 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65308 32 32 407 319 1 193 78 17 17 289 -1 unnamed_device 24.8 MiB 0.98 970 13524 4161 8124 1239 63.8 MiB 0.14 0.00 3.70709 -138.158 -3.70709 3.70709 0.33 0.000772866 0.000717363 0.0660303 0.0613345 -1 -1 -1 -1 46 2848 44 6.95648e+06 202660 828058. 2865.25 7.32 0.417886 0.362144 28066 200906 -1 2393 22 2040 3350 304015 62919 4.15746 4.15746 -154.192 -4.15746 0 0 1.01997e+06 3529.29 0.04 0.10 0.16 -1 -1 0.04 0.0335983 0.0293839 81 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_085.v common 7.38 vpr 64.33 MiB 0.05 7252 -1 -1 1 0.03 -1 -1 30344 -1 -1 34 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65872 29 32 387 316 1 171 95 17 17 289 -1 unnamed_device 24.8 MiB 0.53 799 11543 3674 5805 2064 64.3 MiB 0.10 0.00 2.99215 -102.7 -2.99215 2.99215 0.33 0.000728462 0.000674606 0.0415125 0.0384754 -1 -1 -1 -1 36 2491 33 6.95648e+06 492173 648988. 2245.63 4.97 0.305982 0.26271 26050 158493 -1 1739 22 1523 2315 173906 41913 3.37362 3.37362 -114.306 -3.37362 0 0 828058. 2865.25 0.03 0.08 0.13 -1 -1 0.03 0.0308938 0.0268483 85 88 26 26 85 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_086.v common 4.24 vpr 63.20 MiB 0.04 6920 -1 -1 1 0.03 -1 -1 30340 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64720 32 32 283 225 1 154 75 17 17 289 -1 unnamed_device 24.2 MiB 0.73 634 10345 3746 4906 1693 63.2 MiB 0.09 0.00 2.95005 -113.271 -2.95005 2.95005 0.33 0.000610328 0.00056797 0.0421183 0.0392314 -1 -1 -1 -1 42 2214 29 6.95648e+06 159232 744469. 2576.02 1.68 0.170191 0.148201 27202 183097 -1 1662 20 1294 1970 184358 45262 3.02772 3.02772 -120.654 -3.02772 0 0 949917. 3286.91 0.04 0.07 0.14 -1 -1 0.04 0.0245907 0.0215065 62 3 96 32 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_087.v common 12.95 vpr 64.38 MiB 0.05 7152 -1 -1 1 0.03 -1 -1 30488 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65924 32 32 407 319 1 187 91 17 17 289 -1 unnamed_device 24.8 MiB 2.49 995 13555 5305 7140 1110 64.4 MiB 0.13 0.00 3.78519 -140.535 -3.78519 3.78519 0.33 0.000778235 0.000720528 0.054465 0.0504447 -1 -1 -1 -1 42 2784 31 6.95648e+06 390843 744469. 2576.02 8.50 0.33905 0.293573 27202 183097 -1 2234 24 2085 3193 301812 63023 3.92696 3.92696 -150.426 -3.92696 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 32 32 315 267 1 152 86 17 17 289 -1 unnamed_device 24.3 MiB 0.44 767 11804 4844 6750 210 63.4 MiB 0.10 0.00 2.88585 -108.369 -2.88585 2.88585 0.33 0.000636465 0.000591064 0.0419709 0.0389871 -1 -1 -1 -1 38 1971 50 6.95648e+06 318465 678818. 2348.85 1.17 0.169719 0.147796 26626 170182 -1 1602 22 1339 2042 173752 53877 2.95852 2.95852 -112.019 -2.95852 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0268009 0.0233212 68 55 32 32 54 27 + fixed_k6_frac_2ripple_N8_22nm.xml mult_090.v common 3.47 vpr 63.25 MiB 0.05 6788 -1 -1 1 0.03 -1 -1 30440 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64768 31 32 275 220 1 154 75 17 17 289 -1 unnamed_device 24.2 MiB 0.24 876 9081 2616 5597 868 63.2 MiB 0.08 0.00 2.95305 -115.628 -2.95305 2.95305 0.33 0.000593954 0.000553134 0.0364921 0.0340113 -1 -1 -1 -1 38 2026 23 6.95648e+06 173708 678818. 2348.85 1.37 0.159325 0.138822 26626 170182 -1 1817 20 1467 2170 170840 37494 3.10392 3.10392 -126.814 -3.10392 0 0 902133. 3121.57 0.03 0.07 0.13 -1 -1 0.03 0.0240864 0.0210193 65 4 93 31 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_091.v common 4.29 vpr 63.48 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30328 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65000 32 32 381 303 1 180 96 17 17 289 -1 unnamed_device 24.7 MiB 0.63 927 17178 7158 9678 342 63.5 MiB 0.14 0.00 3.69719 -130.339 -3.69719 3.69719 0.33 0.000742262 0.000687479 0.0611967 0.0566815 -1 -1 -1 -1 36 2786 48 6.95648e+06 463222 648988. 2245.63 1.65 0.22788 0.198897 26050 158493 -1 2199 24 1979 2920 237525 53484 3.88776 3.88776 -147.598 -3.88776 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0341537 0.0297461 86 59 60 32 58 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_092.v common 9.53 vpr 63.73 MiB 0.05 7268 -1 -1 1 0.03 -1 -1 30348 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65260 32 32 406 330 1 182 94 17 17 289 -1 unnamed_device 24.8 MiB 0.20 910 13087 4875 6895 1317 63.7 MiB 0.12 0.00 3.72106 -128.856 -3.72106 3.72106 0.33 0.000758331 0.00070384 0.0494498 0.0458613 -1 -1 -1 -1 38 2744 24 6.95648e+06 434271 678818. 2348.85 7.45 0.371848 0.32008 26626 170182 -1 1958 22 1825 2915 213896 51230 4.44216 4.44216 -143.258 -4.44216 0 0 902133. 3121.57 0.04 0.09 0.13 -1 -1 0.04 0.0322575 0.0280913 85 88 28 28 88 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_093.v common 13.35 vpr 64.48 MiB 0.05 7124 -1 -1 1 0.03 -1 -1 30500 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66024 32 32 399 285 1 218 98 17 17 289 -1 unnamed_device 24.8 MiB 0.22 1090 14948 4439 8116 2393 64.5 MiB 0.14 0.00 4.49114 -157.775 -4.49114 4.49114 0.33 0.000792848 0.000736771 0.0556148 0.0516116 -1 -1 -1 -1 44 3655 42 6.95648e+06 492173 787024. 2723.27 11.05 0.401725 0.347723 27778 195446 -1 2734 21 2285 3558 331809 73612 4.63201 4.63201 -168.752 -4.63201 0 0 997811. 3452.63 0.04 0.11 0.16 -1 -1 0.04 0.0339831 0.0298585 105 3 156 32 0 0 + fixed_k6_frac_2ripple_N8_22nm.xml mult_094.v common 3.93 vpr 64.21 MiB 0.05 7200 -1 -1 1 0.03 -1 -1 30516 -1 -1 30 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65756 30 32 371 295 1 176 92 17 17 289 -1 unnamed_device 24.5 MiB 0.42 773 16031 4862 8616 2553 64.2 MiB 0.14 0.00 3.02515 -107.178 -3.02515 3.02515 0.33 0.000712777 0.000661625 0.0580159 0.0538366 -1 -1 -1 -1 40 2544 46 6.95648e+06 434271 706193. 2443.58 1.60 0.205228 0.178834 26914 176310 -1 1819 24 1746 2759 221514 53000 3.75432 3.75432 -120.684 -3.75432 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0327945 0.0285264 84 59 60 30 56 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_095.v common 3.47 vpr 63.25 MiB 0.04 7040 -1 -1 1 0.03 -1 -1 30672 -1 -1 15 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 27 32 269 226 1 135 74 17 17 289 -1 unnamed_device 24.2 MiB 0.29 834 7359 2280 4045 1034 63.2 MiB 0.07 0.00 2.86985 -98.9536 -2.86985 2.86985 0.33 0.000566146 0.000526225 0.0289215 0.0269497 -1 -1 -1 -1 32 1834 21 6.95648e+06 217135 586450. 2029.24 1.39 0.178093 0.153042 25474 144626 -1 1646 20 1127 1555 124124 27156 3.10102 3.10102 -112.718 -3.10102 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226312 0.0196526 60 34 54 27 27 27 + fixed_k6_frac_2ripple_N8_22nm.xml mult_096.v common 15.31 vpr 64.71 MiB 0.05 7320 -1 -1 1 0.03 -1 -1 30672 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66268 32 32 493 378 1 222 99 17 17 289 -1 unnamed_device 25.1 MiB 0.46 1306 14919 4313 9293 1313 64.7 MiB 0.15 0.00 3.80387 -141.931 -3.80387 3.80387 0.33 0.000908108 0.000843874 0.0625778 0.0580792 -1 -1 -1 -1 38 3944 44 6.95648e+06 506649 678818. 2348.85 12.78 0.440725 0.380228 26626 170182 -1 3006 25 2747 4678 399014 81226 4.05526 4.05526 -157.833 -4.05526 0 0 902133. 3121.57 0.03 0.13 0.13 -1 -1 0.03 0.0423983 0.0367877 109 95 62 31 95 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_097.v common 6.45 vpr 64.20 MiB 0.05 7332 -1 -1 1 0.03 -1 -1 30528 -1 -1 15 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65736 31 32 455 371 1 185 78 17 17 289 -1 unnamed_device 25.1 MiB 1.77 760 10204 4107 5326 771 64.2 MiB 0.11 0.00 3.76754 -132.461 -3.76754 3.76754 0.33 0.000830916 0.000772406 0.0542281 0.0504428 -1 -1 -1 -1 62 1887 20 6.95648e+06 217135 1.05005e+06 3633.38 2.72 0.321677 0.276732 30946 263737 -1 1513 22 1619 2464 160407 38798 4.09926 4.09926 -141.868 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32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65828 32 32 364 282 1 188 94 17 17 289 -1 unnamed_device 24.6 MiB 0.16 872 12235 3685 6337 2213 64.3 MiB 0.11 0.00 3.79096 -133.989 -3.79096 3.79096 0.33 0.000736219 0.00067696 0.044285 0.0410864 -1 -1 -1 -1 52 2436 27 6.95648e+06 434271 926341. 3205.33 3.01 0.29903 0.257725 29218 227130 -1 1955 23 1817 2761 224784 50670 3.93796 3.93796 -140.061 -3.93796 0 0 1.14541e+06 3963.36 0.04 0.09 0.18 -1 -1 0.04 0.0322204 0.0281007 88 34 90 30 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_100.v common 4.98 vpr 64.46 MiB 0.05 7296 -1 -1 1 0.03 -1 -1 30600 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66008 31 32 443 336 1 210 97 17 17 289 -1 unnamed_device 24.7 MiB 0.47 1008 10309 3050 5352 1907 64.5 MiB 0.11 0.00 3.78655 -135.19 -3.78655 3.78655 0.33 0.000846979 0.000786053 0.0425116 0.0395538 -1 -1 -1 -1 40 2671 33 6.95648e+06 492173 706193. 2443.58 2.53 0.317865 0.27328 26914 176310 -1 2235 29 2474 3465 283787 75948 4.35786 4.35786 -151.699 -4.35786 0 0 926341. 3205.33 0.04 0.12 0.14 -1 -1 0.04 0.0443633 0.0383883 103 64 87 31 62 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_101.v common 9.71 vpr 63.65 MiB 0.05 7204 -1 -1 1 0.03 -1 -1 30472 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65176 30 32 373 297 1 178 95 17 17 289 -1 unnamed_device 24.6 MiB 0.33 1053 17591 5567 10335 1689 63.6 MiB 0.15 0.00 2.95915 -111.602 -2.95915 2.95915 0.33 0.000718414 0.000667128 0.0611833 0.0567047 -1 -1 -1 -1 40 2583 24 6.95648e+06 477698 706193. 2443.58 7.41 0.324079 0.280739 26914 176310 -1 2311 22 1722 2902 232970 49578 2.98052 2.98052 -118.352 -2.98052 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0303733 0.0264167 86 61 58 30 58 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_102.v common 10.45 vpr 64.38 MiB 0.05 6996 -1 -1 1 0.04 -1 -1 30484 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65924 32 32 407 319 1 193 102 17 17 289 -1 unnamed_device 24.8 MiB 0.37 955 12716 3237 8898 581 64.4 MiB 0.12 0.00 3.77739 -138.851 -3.77739 3.77739 0.33 0.000775412 0.000719774 0.0443718 0.0411573 -1 -1 -1 -1 40 2793 38 6.95648e+06 550076 706193. 2443.58 8.11 0.373362 0.321643 26914 176310 -1 2288 22 1989 2937 263378 58824 4.37036 4.37036 -156.062 -4.37036 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0327769 0.0285741 95 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 9.91 vpr 63.83 MiB 0.04 7144 -1 -1 1 0.03 -1 -1 30588 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65360 32 32 405 318 1 192 99 17 17 289 -1 unnamed_device 24.8 MiB 0.36 994 14463 3282 10605 576 63.8 MiB 0.14 0.00 3.08635 -120.858 -3.08635 3.08635 0.33 0.000776897 0.000719642 0.0545356 0.0505443 -1 -1 -1 -1 38 2560 23 6.95648e+06 506649 678818. 2348.85 7.65 0.384788 0.331479 26626 170182 -1 2177 21 1643 2221 175833 37705 3.16882 3.16882 -130.69 -3.16882 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0320414 0.028007 94 65 63 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_104.v common 6.87 vpr 63.45 MiB 0.04 6976 -1 -1 1 0.03 -1 -1 30496 -1 -1 13 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64972 29 32 287 238 1 135 74 17 17 289 -1 unnamed_device 24.4 MiB 2.31 566 8444 3444 4596 404 63.4 MiB 0.07 0.00 2.81985 -96.9287 -2.81985 2.81985 0.33 0.000597536 0.000555252 0.034631 0.032233 -1 -1 -1 -1 36 1559 30 6.95648e+06 188184 648988. 2245.63 2.74 0.24753 0.211807 26050 158493 -1 1203 22 1078 1370 97012 23866 2.81132 2.81132 -105.046 -2.81132 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0255544 0.0221971 57 34 58 29 29 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_105.v common 5.56 vpr 64.38 MiB 0.05 6912 -1 -1 1 0.03 -1 -1 30244 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65924 32 32 334 290 1 148 76 17 17 289 -1 unnamed_device 24.6 MiB 0.29 701 9036 2643 5274 1119 64.4 MiB 0.08 0.00 2.9635 -104.243 -2.9635 2.9635 0.33 0.000661879 0.000614835 0.0393279 0.0365752 -1 -1 -1 -1 36 1741 27 6.95648e+06 173708 648988. 2245.63 3.45 0.275177 0.236366 26050 158493 -1 1405 21 1158 1558 112962 26210 3.04982 3.04982 -111.965 -3.04982 0 0 828058. 2865.25 0.03 0.06 0.13 -1 -1 0.03 0.0275127 0.0239783 60 82 0 0 82 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_106.v common 9.01 vpr 64.32 MiB 0.04 7124 -1 -1 1 0.03 -1 -1 30424 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65868 31 32 365 281 1 188 98 17 17 289 -1 unnamed_device 24.9 MiB 0.29 1068 17198 4744 11124 1330 64.3 MiB 0.14 0.00 3.78219 -137.213 -3.78219 3.78219 0.33 0.000721609 0.000669659 0.057735 0.0535352 -1 -1 -1 -1 42 2615 25 6.95648e+06 506649 744469. 2576.02 6.77 0.333788 0.289203 27202 183097 -1 2176 22 2043 3023 251062 52225 4.09926 4.09926 -150.342 -4.09926 0 0 949917. 3286.91 0.04 0.09 0.14 -1 -1 0.04 0.0305887 0.0266408 94 34 93 31 31 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_107.v common 5.13 vpr 63.99 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30552 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65528 29 32 297 254 1 141 84 17 17 289 -1 unnamed_device 24.3 MiB 0.41 578 12345 5122 6532 691 64.0 MiB 0.10 0.00 2.86863 -95.8049 -2.86863 2.86863 0.33 0.000603909 0.000561664 0.0427403 0.0397317 -1 -1 -1 -1 48 1549 29 6.95648e+06 332941 865456. 2994.66 2.88 0.225983 0.194731 28354 207349 -1 1315 24 1183 1871 131675 32208 2.85522 2.85522 -101.12 -2.85522 0 0 1.05005e+06 3633.38 0.04 0.07 0.16 -1 -1 0.04 0.0273014 0.0236141 65 56 29 29 52 26 + fixed_k6_frac_2ripple_N8_22nm.xml mult_108.v common 4.18 vpr 63.43 MiB 0.04 6920 -1 -1 1 0.03 -1 -1 30264 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 314 256 1 154 75 17 17 289 -1 unnamed_device 24.5 MiB 0.96 746 10345 4259 5889 197 63.4 MiB 0.10 0.00 2.93285 -115.609 -2.93285 2.93285 0.33 0.000650042 0.000604312 0.0445715 0.0414736 -1 -1 -1 -1 40 1880 20 6.95648e+06 159232 706193. 2443.58 1.40 0.170514 0.148777 26914 176310 -1 1701 24 1523 2134 204150 47477 3.51472 3.51472 -130.674 -3.51472 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.029555 0.0257005 62 34 64 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_109.v common 5.79 vpr 63.75 MiB 0.05 7216 -1 -1 1 0.03 -1 -1 30304 -1 -1 33 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65276 31 32 387 307 1 181 96 17 17 289 -1 unnamed_device 24.8 MiB 0.64 929 15864 4548 9162 2154 63.7 MiB 0.14 0.00 3.07535 -115.416 -3.07535 3.07535 0.33 0.000565143 0.000514805 0.0565728 0.0525191 -1 -1 -1 -1 36 2485 49 6.95648e+06 477698 648988. 2245.63 3.20 0.327486 0.283381 26050 158493 -1 1982 25 2078 2928 235069 55386 3.29232 3.29232 -128.257 -3.29232 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0353141 0.030716 89 64 58 31 62 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_110.v common 5.68 vpr 63.54 MiB 0.05 7104 -1 -1 1 0.03 -1 -1 30296 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 31 32 308 262 1 142 75 17 17 289 -1 unnamed_device 24.3 MiB 1.10 561 9081 3726 4991 364 63.5 MiB 0.08 0.00 2.878 -99.4515 -2.878 2.878 0.33 0.000625323 0.000580577 0.0384881 0.0358352 -1 -1 -1 -1 42 1873 44 6.95648e+06 173708 744469. 2576.02 2.71 0.261568 0.224788 27202 183097 -1 1399 34 1462 2239 198648 67215 2.97097 2.97097 -105.92 -2.97097 0 0 949917. 3286.91 0.04 0.10 0.15 -1 -1 0.04 0.0379742 0.0327631 57 55 31 31 53 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_111.v common 9.50 vpr 63.75 MiB 0.04 7140 -1 -1 1 0.03 -1 -1 30448 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65276 32 32 383 307 1 176 96 17 17 289 -1 unnamed_device 24.6 MiB 0.90 1008 15645 5715 8149 1781 63.7 MiB 0.13 0.00 2.93235 -112.949 -2.93235 2.93235 0.33 0.000736041 0.000680911 0.0553155 0.051248 -1 -1 -1 -1 38 2510 47 6.95648e+06 463222 678818. 2348.85 6.69 0.349571 0.302102 26626 170182 -1 2131 22 1477 2382 175778 38190 2.94132 2.94132 -122.271 -2.94132 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0312975 0.0272747 84 65 52 26 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_112.v common 3.97 vpr 64.48 MiB 0.05 7164 -1 -1 1 0.03 -1 -1 30420 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66032 31 32 422 339 1 187 95 17 17 289 -1 unnamed_device 24.8 MiB 0.95 814 14999 5034 7379 2586 64.5 MiB 0.13 0.00 3.12545 -115.097 -3.12545 3.12545 0.33 0.000787055 0.000728493 0.0575209 0.0531761 -1 -1 -1 -1 40 2613 32 6.95648e+06 463222 706193. 2443.58 1.09 0.196102 0.171338 26914 176310 -1 1926 21 1924 2659 204937 48092 3.45062 3.45062 -126.961 -3.45062 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0322371 0.028142 91 93 31 31 92 31 + fixed_k6_frac_2ripple_N8_22nm.xml mult_113.v common 4.74 vpr 63.47 MiB 0.04 6968 -1 -1 1 0.03 -1 -1 30320 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64996 32 32 333 279 1 154 76 17 17 289 -1 unnamed_device 24.3 MiB 0.43 634 9836 2564 5684 1588 63.5 MiB 0.09 0.00 2.83385 -103.376 -2.83385 2.83385 0.33 0.000658459 0.000612155 0.0427864 0.0398191 -1 -1 -1 -1 44 1831 49 6.95648e+06 173708 787024. 2723.27 2.44 0.279259 0.240577 27778 195446 -1 1296 22 1167 1847 118693 29957 3.27042 3.27042 -108.272 -3.27042 0 0 997811. 3452.63 0.04 0.07 0.15 -1 -1 0.04 0.0282458 0.0245808 62 61 32 32 60 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_114.v common 7.84 vpr 63.64 MiB 0.05 6968 -1 -1 1 0.03 -1 -1 30064 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 32 32 339 283 1 158 76 17 17 289 -1 unnamed_device 24.6 MiB 0.36 653 8716 2249 5094 1373 63.6 MiB 0.04 0.00 2.91085 -109.584 -2.91085 2.91085 0.25 0.000296029 0.000272482 0.0180277 0.0166447 -1 -1 -1 -1 46 1898 26 6.95648e+06 173708 828058. 2865.25 5.83 0.290743 0.24807 28066 200906 -1 1393 27 1458 2287 173544 43666 3.37552 3.37552 -120.828 -3.37552 0 0 1.01997e+06 3529.29 0.04 0.08 0.17 -1 -1 0.04 0.0333938 0.0289533 64 63 32 32 62 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_115.v common 4.98 vpr 63.68 MiB 0.05 7016 -1 -1 1 0.03 -1 -1 30740 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65208 32 32 407 319 1 190 96 17 17 289 -1 unnamed_device 24.8 MiB 0.59 846 15645 5217 8008 2420 63.7 MiB 0.14 0.00 3.76019 -138.157 -3.76019 3.76019 0.33 0.000776097 0.000720992 0.0584194 0.0541845 -1 -1 -1 -1 40 2973 41 6.95648e+06 463222 706193. 2443.58 2.39 0.237572 0.207353 26914 176310 -1 2139 22 2082 3061 234663 54691 4.28096 4.28096 -154.111 -4.28096 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0325639 0.0283912 91 65 64 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_116.v common 3.69 vpr 63.62 MiB 0.05 7200 -1 -1 1 0.03 -1 -1 30484 -1 -1 33 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65144 29 32 367 293 1 175 94 17 17 289 -1 unnamed_device 24.5 MiB 0.48 804 14791 5197 7141 2453 63.6 MiB 0.13 0.00 2.96363 -103.824 -2.96363 2.96363 0.33 0.000717323 0.000666661 0.052836 0.0490004 -1 -1 -1 -1 36 2587 50 6.95648e+06 477698 648988. 2245.63 1.33 0.215037 0.186915 26050 158493 -1 1915 21 1505 2184 169250 39755 3.09182 3.09182 -114.618 -3.09182 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0290436 0.0252849 87 62 56 29 58 29 + fixed_k6_frac_2ripple_N8_22nm.xml mult_117.v common 10.33 vpr 64.57 MiB 0.05 7276 -1 -1 1 0.03 -1 -1 30660 -1 -1 32 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66116 32 32 469 381 1 192 96 17 17 289 -1 unnamed_device 25.1 MiB 1.04 833 14769 5115 7175 2479 64.6 MiB 0.14 0.00 3.83239 -140.013 -3.83239 3.83239 0.33 0.000857044 0.000795576 0.0612803 0.0568805 -1 -1 -1 -1 40 3023 40 6.95648e+06 463222 706193. 2443.58 7.25 0.410817 0.353029 26914 176310 -1 2371 28 2471 3681 337820 82004 4.31396 4.31396 -161.444 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32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65156 32 32 418 338 1 182 93 17 17 289 -1 unnamed_device 24.7 MiB 0.49 1008 14373 5915 8161 297 63.6 MiB 0.12 0.00 3.76639 -134.285 -3.76639 3.76639 0.33 0.000782573 0.000725614 0.0562358 0.0521638 -1 -1 -1 -1 42 2357 30 6.95648e+06 419795 744469. 2576.02 5.40 0.336258 0.290782 27202 183097 -1 2106 20 1769 2470 198773 43978 3.72356 3.72356 -143.045 -3.72356 0 0 949917. 3286.91 0.04 0.08 0.14 -1 -1 0.04 0.0304509 0.0265932 85 92 28 28 92 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_120.v common 7.27 vpr 63.56 MiB 0.04 7128 -1 -1 1 0.03 -1 -1 30148 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65084 32 32 376 318 1 154 75 17 17 289 -1 unnamed_device 24.5 MiB 2.10 788 8607 3571 4894 142 63.6 MiB 0.09 0.00 2.94085 -114.746 -2.94085 2.94085 0.33 0.000713205 0.000662552 0.0414309 0.038531 -1 -1 -1 -1 34 2334 39 6.95648e+06 159232 618332. 2139.56 3.12 0.282429 0.243136 25762 151098 -1 1768 64 3392 4836 664245 272373 3.37362 3.37362 -130.543 -3.37362 0 0 787024. 2723.27 0.03 0.29 0.12 -1 -1 0.03 0.0739877 0.0634063 62 96 0 0 96 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_121.v common 8.27 vpr 64.46 MiB 0.05 7000 -1 -1 1 0.03 -1 -1 30348 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66012 32 32 401 316 1 188 94 17 17 289 -1 unnamed_device 25.0 MiB 0.77 1163 14578 4502 8146 1930 64.5 MiB 0.13 0.00 3.02515 -120.461 -3.02515 3.02515 0.33 0.000763621 0.000708978 0.0550876 0.0510326 -1 -1 -1 -1 38 2720 24 6.95648e+06 434271 678818. 2348.85 5.60 0.350026 0.302466 26626 170182 -1 2254 21 1648 2439 188931 40647 3.28132 3.28132 -131.597 -3.28132 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0314833 0.0274757 89 65 61 32 64 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_122.v common 4.40 vpr 64.71 MiB 0.05 7420 -1 -1 1 0.03 -1 -1 30792 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66268 32 32 500 382 1 222 101 17 17 289 -1 unnamed_device 25.0 MiB 1.00 1172 16081 5219 8297 2565 64.7 MiB 0.16 0.00 4.55644 -167.51 -4.55644 4.55644 0.33 0.000918369 0.000853658 0.0659489 0.0611756 -1 -1 -1 -1 42 3191 26 6.95648e+06 535600 744469. 2576.02 1.40 0.220628 0.193047 27202 183097 -1 2692 24 2813 4296 363308 73326 4.74021 4.74021 -177.029 -4.74021 0 0 949917. 3286.91 0.04 0.12 0.15 -1 -1 0.04 0.0425785 0.0370625 108 96 64 32 96 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_123.v common 3.89 vpr 63.56 MiB 0.04 6924 -1 -1 1 0.03 -1 -1 30152 -1 -1 12 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65084 30 32 246 229 1 115 74 17 17 289 -1 unnamed_device 24.0 MiB 0.31 487 9219 3932 4969 318 63.6 MiB 0.07 0.00 2.20646 -79.82 -2.20646 2.20646 0.33 0.000526981 0.000490756 0.033147 0.0308633 -1 -1 -1 -1 34 1402 21 6.95648e+06 173708 618332. 2139.56 1.80 0.193704 0.166313 25762 151098 -1 1112 20 754 1006 83380 21795 2.10948 2.10948 -84.4848 -2.10948 0 0 787024. 2723.27 0.03 0.05 0.12 -1 -1 0.03 0.021054 0.0182373 45 56 0 0 53 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_124.v common 6.01 vpr 63.31 MiB 0.04 6884 -1 -1 1 0.03 -1 -1 30416 -1 -1 12 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 30 32 296 244 1 141 74 17 17 289 -1 unnamed_device 24.3 MiB 1.22 714 11544 4893 6197 454 63.3 MiB 0.10 0.00 2.83685 -102.626 -2.83685 2.83685 0.33 0.000610989 0.000567908 0.0477614 0.044451 -1 -1 -1 -1 40 1762 24 6.95648e+06 173708 706193. 2443.58 2.95 0.279609 0.240749 26914 176310 -1 1496 21 1107 1674 190010 50002 3.09792 3.09792 -113.332 -3.09792 0 0 926341. 3205.33 0.04 0.08 0.14 -1 -1 0.04 0.0255234 0.0221883 58 34 60 30 30 30 + fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 9.51 vpr 63.36 MiB 0.05 6876 -1 -1 1 0.03 -1 -1 30036 -1 -1 12 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 32 32 314 256 1 161 76 17 17 289 -1 unnamed_device 24.2 MiB 0.16 675 9356 3688 5198 470 63.4 MiB 0.09 0.00 2.98911 -115.235 -2.98911 2.98911 0.33 0.000645409 0.000600029 0.0399621 0.0371964 -1 -1 -1 -1 44 2328 48 6.95648e+06 173708 787024. 2723.27 7.46 0.332472 0.286341 27778 195446 -1 1719 22 1464 2394 196534 47359 3.50852 3.50852 -124.354 -3.50852 0 0 997811. 3452.63 0.04 0.08 0.15 -1 -1 0.04 0.0277999 0.0242654 66 34 64 32 32 32 + fixed_k6_frac_2ripple_N8_22nm.xml mult_126.v common 6.28 vpr 63.65 MiB 0.04 6996 -1 -1 1 0.03 -1 -1 30392 -1 -1 23 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65176 25 32 251 214 1 132 80 17 17 289 -1 unnamed_device 24.4 MiB 0.17 539 11776 4899 6026 851 63.6 MiB 0.11 0.00 3.0295 -88.2249 -3.0295 3.0295 0.33 0.000532627 0.000495578 0.0485384 0.0452027 -1 -1 -1 -1 32 1899 49 6.95648e+06 332941 586450. 2029.24 4.36 0.265617 0.228504 25474 144626 -1 1321 27 1201 1717 130920 30562 2.94452 2.94452 -95.9196 -2.94452 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0266542 0.0229613 61 34 50 25 25 25 + fixed_k6_frac_2ripple_N8_22nm.xml mult_127.v common 4.89 vpr 63.81 MiB 0.05 7120 -1 -1 1 0.03 -1 -1 30548 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65344 32 32 432 346 1 185 78 17 17 289 -1 unnamed_device 24.8 MiB 0.64 818 10868 4497 5970 401 63.8 MiB 0.12 0.00 3.72219 -135.01 -3.72219 3.72219 0.33 0.000804735 0.000747637 0.0553397 0.0514399 -1 -1 -1 -1 44 2570 26 6.95648e+06 202660 787024. 2723.27 2.33 0.297276 0.256946 27778 195446 -1 1944 21 1780 3078 212057 49868 3.97716 3.97716 -145.956 -3.97716 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65356 32 32 438 350 1 287 89 17 17 289 -1 unnamed_device 24.9 MiB 0.36 1233 11375 4637 6444 294 63.8 MiB 0.12 0.00 4.40054 -159.031 -4.40054 4.40054 0.33 0.000808814 0.000751192 0.0495967 0.0460748 -1 -1 -1 -1 42 3320 45 6.99608e+06 367892 744469. 2576.02 8.08 0.40144 0.344773 27202 183097 -1 2539 23 2414 2701 243477 63902 4.71111 4.71111 -173.083 -4.71111 0 0 949917. 3286.91 0.04 0.10 0.14 -1 -1 0.04 0.0359306 0.0313085 126 96 32 32 96 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_002.v common 6.30 vpr 63.62 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30596 -1 -1 25 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65152 30 32 409 330 1 257 87 17 17 289 -1 unnamed_device 24.6 MiB 0.35 1064 13335 4865 6427 2043 63.6 MiB 0.13 0.00 4.36632 -144.157 -4.36632 4.36632 0.34 0.000756055 0.000702402 0.0554984 0.0515527 -1 -1 -1 -1 50 2976 46 6.99608e+06 367892 902133. 3121.57 3.97 0.3417 0.294858 28642 213929 -1 2223 24 2360 3313 277236 67322 4.14654 4.14654 -145.435 -4.14654 0 0 1.08113e+06 3740.92 0.04 0.10 0.17 -1 -1 0.04 0.0346117 0.0301218 114 91 30 30 89 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_003.v common 3.87 vpr 64.24 MiB 0.05 7096 -1 -1 1 0.03 -1 -1 30464 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65784 32 32 387 309 1 241 85 17 17 289 -1 unnamed_device 24.6 MiB 0.50 1235 15523 5650 7863 2010 64.2 MiB 0.15 0.00 3.64599 -137.543 -3.64599 3.64599 0.33 0.000738812 0.000686248 0.0642401 0.0596489 -1 -1 -1 -1 40 3140 38 6.99608e+06 309029 706193. 2443.58 1.39 0.196641 0.172918 26914 176310 -1 2560 23 1930 2360 218707 46060 4.07156 4.07156 -152.256 -4.07156 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0329047 0.0286835 100 65 54 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_004.v common 4.56 vpr 63.96 MiB 0.04 7188 -1 -1 1 0.03 -1 -1 30420 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65500 29 32 343 267 1 201 81 17 17 289 -1 unnamed_device 24.4 MiB 0.38 847 11981 3747 5797 2437 64.0 MiB 0.11 0.00 3.84635 -127.029 -3.84635 3.84635 0.33 0.000686096 0.000637966 0.0493909 0.0459572 -1 -1 -1 -1 48 2100 31 6.99608e+06 294314 865456. 2994.66 2.34 0.265243 0.22956 28354 207349 -1 1595 22 1728 2558 187627 48523 3.83472 3.83472 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-1 -1 30516 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 402 316 1 251 93 17 17 289 -1 unnamed_device 24.6 MiB 0.32 1320 17313 6726 9274 1313 63.7 MiB 0.16 0.00 3.71319 -137.448 -3.71319 3.71319 0.33 0.000778887 0.000723269 0.0660236 0.0612872 -1 -1 -1 -1 40 3233 25 6.99608e+06 426755 706193. 2443.58 1.16 0.194054 0.170793 26914 176310 -1 2612 29 2337 3584 347075 89466 3.65466 3.65466 -141.846 -3.65466 0 0 926341. 3205.33 0.04 0.13 0.14 -1 -1 0.04 0.0404468 0.0350768 114 64 63 32 63 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_007.v common 3.06 vpr 63.43 MiB 0.05 6972 -1 -1 1 0.03 -1 -1 30628 -1 -1 17 27 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 27 32 269 226 1 156 76 17 17 289 -1 unnamed_device 24.4 MiB 0.35 793 10636 4431 5599 606 63.4 MiB 0.09 0.00 3.0735 -101.918 -3.0735 3.0735 0.33 0.000570738 0.00053129 0.039728 0.0369982 -1 -1 -1 -1 36 1866 21 6.99608e+06 250167 648988. 2245.63 0.94 0.126687 0.11096 26050 158493 -1 1715 21 1382 1942 186836 39004 3.21292 3.21292 -113.803 -3.21292 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.02326 0.0201542 68 34 54 27 27 27 + fixed_k6_frac_2uripple_N8_22nm.xml mult_008.v common 8.70 vpr 64.03 MiB 0.02 7064 -1 -1 1 0.03 -1 -1 30204 -1 -1 30 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65564 31 32 317 242 1 178 93 17 17 289 -1 unnamed_device 24.5 MiB 0.15 1053 15633 4964 8757 1912 64.0 MiB 0.13 0.00 2.8156 -108.673 -2.8156 2.8156 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65116 30 32 325 273 1 197 80 17 17 289 -1 unnamed_device 24.6 MiB 0.40 907 10916 3962 5331 1623 63.6 MiB 0.10 0.00 3.56495 -123.942 -3.56495 3.56495 0.33 0.000651363 0.000605652 0.0437044 0.0406188 -1 -1 -1 -1 38 2537 27 6.99608e+06 264882 678818. 2348.85 1.36 0.175213 0.152456 26626 170182 -1 1998 23 2038 2743 238850 68052 3.72141 3.72141 -139.11 -3.72141 0 0 902133. 3121.57 0.03 0.10 0.13 -1 -1 0.03 0.030142 0.0262821 86 63 30 30 60 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_012.v common 7.37 vpr 63.97 MiB 0.04 6988 -1 -1 1 0.03 -1 -1 30464 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65508 32 32 331 280 1 210 82 17 17 289 -1 unnamed_device 24.3 MiB 0.36 1146 9694 2399 6092 1203 64.0 MiB 0.09 0.00 3.0953 -120.741 -3.0953 3.0953 0.33 0.000658633 0.00061218 0.0384871 0.0357874 -1 -1 -1 -1 38 2566 46 6.99608e+06 264882 678818. 2348.85 5.11 0.323446 0.277602 26626 170182 -1 2137 22 1380 1520 128231 27765 3.32967 3.32967 -128.514 -3.32967 0 0 902133. 3121.57 0.03 0.07 0.14 -1 -1 0.03 0.028121 0.024473 85 65 25 25 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 10.33 vpr 64.25 MiB 0.05 7132 -1 -1 1 0.03 -1 -1 30292 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65788 32 32 386 305 1 228 84 17 17 289 -1 unnamed_device 24.6 MiB 0.37 1223 5757 1291 4117 349 64.2 MiB 0.08 0.00 3.67909 -136.815 -3.67909 3.67909 0.33 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20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65808 32 32 401 315 1 244 84 17 17 289 -1 unnamed_device 24.7 MiB 1.24 1279 12711 5262 7205 244 64.3 MiB 0.13 0.00 3.55059 -132.497 -3.55059 3.55059 0.36 0.000770108 0.000715452 0.0560539 0.0520678 -1 -1 -1 -1 46 2879 20 6.99608e+06 294314 828058. 2865.25 2.46 0.273978 0.237341 28066 200906 -1 2421 23 2380 3740 245886 54523 3.60011 3.60011 -143.637 -3.60011 0 0 1.01997e+06 3529.29 0.04 0.10 0.16 -1 -1 0.04 0.0341191 0.0297451 108 63 64 32 62 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_017.v common 4.77 vpr 63.76 MiB 0.02 7160 -1 -1 1 0.03 -1 -1 30316 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65288 32 32 383 303 1 227 84 17 17 289 -1 unnamed_device 24.7 MiB 0.40 1158 9966 2544 6871 551 63.8 MiB 0.11 0.00 3.23714 -123.773 -3.23714 3.23714 0.34 0.000747831 0.000695384 0.0433814 0.0403347 -1 -1 -1 -1 40 2794 37 6.99608e+06 294314 706193. 2443.58 2.49 0.281413 0.24312 26914 176310 -1 2333 24 2014 2580 220082 47588 3.49952 3.49952 -139.157 -3.49952 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.0342117 0.0298083 97 57 64 32 56 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_018.v common 7.84 vpr 63.98 MiB 0.04 6988 -1 -1 1 0.03 -1 -1 30124 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65512 32 32 339 284 1 218 83 17 17 289 -1 unnamed_device 24.3 MiB 0.39 1038 13763 4757 7523 1483 64.0 MiB 0.12 0.00 2.91805 -112.667 -2.91805 2.91805 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65772 32 32 366 283 1 215 97 17 17 289 -1 unnamed_device 24.7 MiB 0.31 958 14971 4356 8257 2358 64.2 MiB 0.13 0.00 4.00213 -141.214 -4.00213 4.00213 0.34 0.000727574 0.000676096 0.0518197 0.0481102 -1 -1 -1 -1 40 2774 47 6.99608e+06 485618 706193. 2443.58 2.09 0.207999 0.182008 26914 176310 -1 2148 21 1903 2841 256990 74288 4.3382 4.3382 -152.268 -4.3382 0 0 926341. 3205.33 0.04 0.10 0.14 -1 -1 0.04 0.0298727 0.026075 103 34 91 32 32 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_022.v common 5.19 vpr 63.86 MiB 0.05 7284 -1 -1 1 0.03 -1 -1 30560 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65396 32 32 460 375 1 304 91 17 17 289 -1 unnamed_device 24.9 MiB 0.47 1465 14983 5290 7359 2334 63.9 MiB 0.16 0.00 4.08533 -143.635 -4.08533 4.08533 0.34 0.000839968 0.000780835 0.0651483 0.0605954 -1 -1 -1 -1 48 3159 24 6.99608e+06 397324 865456. 2994.66 2.67 0.319591 0.276412 28354 207349 -1 2635 18 2010 2295 201415 50295 3.93832 3.93832 -148.233 -3.93832 0 0 1.05005e+06 3633.38 0.04 0.09 0.16 -1 -1 0.04 0.0309936 0.0270963 132 124 0 0 125 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_023.v common 2.82 vpr 63.16 MiB 0.04 6748 -1 -1 1 0.03 -1 -1 30556 -1 -1 16 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 26 32 198 186 1 125 74 17 17 289 -1 unnamed_device 23.7 MiB 0.28 507 10149 4254 5314 581 63.2 MiB 0.10 0.00 2.61785 -73.794 -2.61785 2.61785 0.33 0.00052234 0.000485184 0.0446462 0.041496 -1 -1 -1 -1 36 1335 24 6.99608e+06 235451 648988. 2245.63 0.79 0.116157 0.102295 26050 158493 -1 1082 18 603 752 57594 14524 2.30737 2.30737 -76.2676 -2.30737 0 0 828058. 2865.25 0.03 0.04 0.13 -1 -1 0.03 0.0165843 0.0144907 53 30 26 26 22 22 + fixed_k6_frac_2uripple_N8_22nm.xml mult_024.v common 8.97 vpr 63.15 MiB 0.04 6928 -1 -1 1 0.03 -1 -1 30204 -1 -1 14 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64668 32 32 333 251 1 181 78 17 17 289 -1 unnamed_device 24.3 MiB 0.84 917 12030 4510 6313 1207 63.2 MiB 0.12 0.00 3.49024 -127.709 -3.49024 3.49024 0.33 0.000882113 0.000820402 0.0535002 0.0496594 -1 -1 -1 -1 44 2529 42 6.99608e+06 206020 787024. 2723.27 6.18 0.337561 0.291936 27778 195446 -1 2012 21 1781 2845 248153 51952 3.59331 3.59331 -135.697 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64748 28 32 278 232 1 163 77 17 17 289 -1 unnamed_device 24.1 MiB 0.30 898 11813 3304 7441 1068 63.2 MiB 0.10 0.00 3.56439 -121.03 -3.56439 3.56439 0.33 0.000582792 0.00054258 0.0443042 0.0412529 -1 -1 -1 -1 42 2263 47 6.99608e+06 250167 744469. 2576.02 2.35 0.24824 0.213732 27202 183097 -1 1927 24 1129 1983 181139 37303 3.45416 3.45416 -123.961 -3.45416 0 0 949917. 3286.91 0.04 0.08 0.15 -1 -1 0.04 0.0269335 0.0233457 73 34 56 28 28 28 + fixed_k6_frac_2uripple_N8_22nm.xml mult_032.v common 5.09 vpr 63.59 MiB 0.03 6936 -1 -1 1 0.03 -1 -1 30364 -1 -1 11 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 65256 32 32 407 319 1 252 86 17 17 289 -1 unnamed_device 24.6 MiB 0.51 1090 16907 7321 9114 472 63.7 MiB 0.16 0.00 3.84815 -144.105 -3.84815 3.84815 0.33 0.000782806 0.000727461 0.071641 0.0665573 -1 -1 -1 -1 42 3318 46 6.99608e+06 323745 744469. 2576.02 10.46 0.418148 0.363014 27202 183097 -1 2456 29 2732 3557 313631 77793 4.36892 4.36892 -165.543 -4.36892 0 0 949917. 3286.91 0.04 0.12 0.15 -1 -1 0.04 0.0404369 0.035038 106 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_043.v common 9.40 vpr 64.26 MiB 0.05 7360 -1 -1 1 0.03 -1 -1 30788 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65800 32 32 496 380 1 313 90 17 17 289 -1 unnamed_device 25.2 MiB 0.50 1582 11547 3145 7670 732 64.3 MiB 0.14 0.00 4.28794 -157.671 -4.28794 4.28794 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65728 29 32 393 319 1 240 86 17 17 289 -1 unnamed_device 24.5 MiB 0.40 1231 14828 5539 7167 2122 64.2 MiB 0.14 0.00 3.52589 -122.812 -3.52589 3.52589 0.33 0.00073433 0.000681789 0.0606837 0.0563789 -1 -1 -1 -1 38 3483 25 6.99608e+06 367892 678818. 2348.85 9.08 0.331469 0.287412 26626 170182 -1 2762 20 2184 2966 249408 53951 3.62541 3.62541 -130.616 -3.62541 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0295916 0.0258818 111 88 29 29 85 29 + fixed_k6_frac_2uripple_N8_22nm.xml mult_067.v common 3.73 vpr 64.57 MiB 0.04 7140 -1 -1 1 0.03 -1 -1 30748 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66124 32 32 407 319 1 250 84 17 17 289 -1 unnamed_device 24.9 MiB 0.69 1211 14724 6283 7977 464 64.6 MiB 0.14 0.00 4.47024 -165.899 -4.47024 4.47024 0.33 0.000767102 0.000712252 0.0646944 0.0600997 -1 -1 -1 -1 42 3024 26 6.99608e+06 294314 744469. 2576.02 1.09 0.192098 0.168941 27202 183097 -1 2573 24 2506 3356 266293 59389 5.06801 5.06801 -179.766 -5.06801 0 0 949917. 3286.91 0.04 0.10 0.15 -1 -1 0.04 0.0352599 0.0307328 107 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_068.v common 11.50 vpr 64.34 MiB 0.04 7076 -1 -1 1 0.03 -1 -1 30708 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65880 32 32 407 319 1 249 85 17 17 289 -1 unnamed_device 24.7 MiB 0.65 1172 12919 4604 6148 2167 64.3 MiB 0.13 0.00 4.42939 -158.789 -4.42939 4.42939 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23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65600 30 32 374 297 1 226 85 17 17 289 -1 unnamed_device 24.3 MiB 0.42 990 12733 4591 5781 2361 64.1 MiB 0.11 0.00 3.2948 -115.864 -3.2948 3.2948 0.33 0.000718725 0.000667694 0.0518642 0.0481849 -1 -1 -1 -1 50 2446 24 6.99608e+06 338461 902133. 3121.57 2.62 0.275226 0.238098 28642 213929 -1 1972 24 1918 2622 194283 48559 3.19707 3.19707 -121.425 -3.19707 0 0 1.08113e+06 3740.92 0.04 0.09 0.17 -1 -1 0.04 0.0328931 0.028642 100 60 60 30 57 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_072.v common 3.45 vpr 63.32 MiB 0.05 7124 -1 -1 1 0.04 -1 -1 30496 -1 -1 25 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 28 32 332 260 1 195 85 17 17 289 -1 unnamed_device 24.4 MiB 0.31 1003 6409 2401 3531 477 63.3 MiB 0.07 0.00 3.82205 -126.533 -3.82205 3.82205 0.33 0.00066289 0.000617122 0.0254201 0.0237124 -1 -1 -1 -1 38 2515 23 6.99608e+06 367892 678818. 2348.85 1.22 0.152501 0.132161 26626 170182 -1 2269 28 2236 3241 337187 98313 4.23992 4.23992 -143.46 -4.23992 0 0 902133. 3121.57 0.03 0.13 0.13 -1 -1 0.03 0.0342635 0.0297172 88 34 84 28 28 28 + fixed_k6_frac_2uripple_N8_22nm.xml mult_073.v common 4.81 vpr 63.40 MiB 0.04 6928 -1 -1 1 0.03 -1 -1 30212 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 30 32 325 273 1 204 80 17 17 289 -1 unnamed_device 24.3 MiB 0.39 1052 14012 5462 6811 1739 63.4 MiB 0.12 0.00 3.90653 -137.71 -3.90653 3.90653 0.33 0.000650497 0.000605108 0.0555379 0.0516654 -1 -1 -1 -1 44 2316 24 6.99608e+06 264882 787024. 2723.27 2.41 0.277551 0.240219 27778 195446 -1 2071 44 2896 3928 469909 173674 3.6477 3.6477 -132.698 -3.6477 0 0 997811. 3452.63 0.04 0.19 0.15 -1 -1 0.04 0.0489188 0.0420951 86 63 30 30 60 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_074.v common 4.70 vpr 63.59 MiB 0.05 7036 -1 -1 1 0.03 -1 -1 30320 -1 -1 20 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 32 32 361 308 1 237 84 17 17 289 -1 unnamed_device 24.4 MiB 0.40 1052 13626 4473 6882 2271 63.6 MiB 0.13 0.00 3.46859 -125.68 -3.46859 3.46859 0.33 0.000693365 0.000644071 0.0542717 0.0503975 -1 -1 -1 -1 44 2754 30 6.99608e+06 294314 787024. 2723.27 2.37 0.272055 0.235196 27778 195446 -1 2112 25 1909 2369 196518 45972 3.56566 3.56566 -129.624 -3.56566 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65920 32 32 407 319 1 249 87 17 17 289 -1 unnamed_device 24.7 MiB 0.31 1238 8727 2205 5715 807 64.4 MiB 0.10 0.00 4.31154 -156.569 -4.31154 4.31154 0.33 0.000773857 0.000719495 0.0379417 0.0352146 -1 -1 -1 -1 38 3518 32 6.99608e+06 338461 678818. 2348.85 1.70 0.175096 0.152396 26626 170182 -1 2958 25 2711 3680 352834 74473 4.68111 4.68111 -171.74 -4.68111 0 0 902133. 3121.57 0.03 0.12 0.13 -1 -1 0.03 0.0363705 0.0315752 105 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_077.v common 9.72 vpr 63.94 MiB 0.05 7144 -1 -1 1 0.03 -1 -1 30380 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65476 32 32 407 319 1 248 85 17 17 289 -1 unnamed_device 24.9 MiB 0.40 1289 7711 1655 5862 194 63.9 MiB 0.10 0.00 4.54847 -159.975 -4.54847 4.54847 0.33 0.000776719 0.000721466 0.0349948 0.0325352 -1 -1 -1 -1 46 3139 42 6.99608e+06 309029 828058. 2865.25 7.43 0.26383 0.227743 28066 200906 -1 2534 21 2174 2990 224195 48442 4.42484 4.42484 -162.7 -4.42484 0 0 1.01997e+06 3529.29 0.04 0.09 0.16 -1 -1 0.04 0.0320405 0.0280087 106 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_078.v common 4.02 vpr 63.72 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30380 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65248 32 32 399 315 1 250 86 17 17 289 -1 unnamed_device 24.7 MiB 0.42 1229 15017 6317 8415 285 63.7 MiB 0.15 0.00 3.80163 -136.823 -3.80163 3.80163 0.33 0.000763786 0.0007091 0.063708 0.059041 -1 -1 -1 -1 48 3288 34 6.99608e+06 323745 865456. 2994.66 1.63 0.225777 0.197283 28354 207349 -1 2629 24 2392 3459 274832 60108 3.65631 3.65631 -138.78 -3.65631 0 0 1.05005e+06 3633.38 0.04 0.10 0.16 -1 -1 0.04 0.0349164 0.0304211 104 65 60 30 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_079.v common 8.45 vpr 63.25 MiB 0.04 6940 -1 -1 1 0.03 -1 -1 30408 -1 -1 17 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64764 30 32 296 244 1 177 79 17 17 289 -1 unnamed_device 24.1 MiB 0.32 778 10726 3078 5744 1904 63.2 MiB 0.10 0.00 3.0932 -110.285 -3.0932 3.0932 0.33 0.000609563 0.0005667 0.0407636 0.0378909 -1 -1 -1 -1 38 2358 25 6.99608e+06 250167 678818. 2348.85 6.33 0.27111 0.234205 26626 170182 -1 1969 21 1586 2235 207800 45573 3.25447 3.25447 -123.974 -3.25447 0 0 902133. 3121.57 0.03 0.08 0.14 -1 -1 0.03 0.0254469 0.0221535 73 34 60 30 30 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_080.v common 8.71 vpr 64.29 MiB 0.05 7044 -1 -1 1 0.03 -1 -1 30364 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65836 30 32 383 303 1 235 83 17 17 289 -1 unnamed_device 24.7 MiB 0.38 1198 14303 4504 8197 1602 64.3 MiB 0.14 0.00 4.62177 -156.286 -4.62177 4.62177 0.33 0.00073958 0.000687065 0.0614497 0.0571291 -1 -1 -1 -1 38 3098 34 6.99608e+06 309029 678818. 2348.85 6.34 0.361023 0.311836 26626 170182 -1 2603 19 2214 3134 240633 52283 4.62344 4.62344 -161.886 -4.62344 0 0 902133. 3121.57 0.03 0.09 0.14 -1 -1 0.03 0.0285404 0.0249821 102 63 60 30 60 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_081.v common 5.44 vpr 64.70 MiB 0.05 7348 -1 -1 1 0.03 -1 -1 30836 -1 -1 28 32 0 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27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66140 32 32 493 378 1 313 91 17 17 289 -1 unnamed_device 25.1 MiB 0.42 1492 16411 6100 7697 2614 64.6 MiB 0.18 0.00 4.57134 -160.625 -4.57134 4.57134 0.33 0.000911256 0.00084626 0.0764421 0.0710434 -1 -1 -1 -1 54 3582 33 6.99608e+06 397324 949917. 3286.91 4.50 0.428916 0.370043 29506 232905 -1 2767 24 2560 3729 282156 63406 4.55301 4.55301 -161.557 -4.55301 0 0 1.17392e+06 4061.99 0.04 0.11 0.18 -1 -1 0.04 0.0411328 0.0357344 137 95 62 31 95 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_097.v common 9.80 vpr 63.95 MiB 0.05 7324 -1 -1 1 0.03 -1 -1 30556 -1 -1 27 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65040 30 32 373 297 1 228 85 17 17 289 -1 unnamed_device 24.4 MiB 0.44 1206 13477 4531 6953 1993 63.5 MiB 0.13 0.00 3.74367 -132.253 -3.74367 3.74367 0.33 0.000719791 0.00066916 0.0547673 0.0509122 -1 -1 -1 -1 44 2895 25 6.99608e+06 338461 787024. 2723.27 2.38 0.281536 0.243742 27778 195446 -1 2424 19 1616 2330 170737 36982 3.71286 3.71286 -134.409 -3.71286 0 0 997811. 3452.63 0.04 0.07 0.15 -1 -1 0.04 0.0273469 0.0238845 99 61 58 30 58 30 + fixed_k6_frac_2uripple_N8_22nm.xml mult_102.v common 4.87 vpr 63.64 MiB 0.04 7016 -1 -1 1 0.03 -1 -1 30472 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65164 32 32 407 319 1 252 87 17 17 289 -1 unnamed_device 24.6 MiB 0.32 1123 16023 6720 8873 430 63.6 MiB 0.16 0.00 4.43684 -158.443 -4.43684 4.43684 0.33 0.000787457 0.000732047 0.0679509 0.0630974 -1 -1 -1 -1 50 3055 30 6.99608e+06 338461 902133. 3121.57 2.56 0.312864 0.271781 28642 213929 -1 2505 20 2207 2741 196823 45094 4.32121 4.32121 -161.091 -4.32121 0 0 1.08113e+06 3740.92 0.04 0.08 0.17 -1 -1 0.04 0.0306376 0.0267673 105 65 64 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_103.v common 8.07 vpr 63.64 MiB 0.05 7056 -1 -1 1 0.03 -1 -1 30448 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65168 32 32 405 318 1 253 85 17 17 289 -1 unnamed_device 24.6 MiB 0.39 1415 15337 5616 8436 1285 63.6 MiB 0.14 0.00 3.0955 -123.55 -3.0955 3.0955 0.33 0.00076674 0.000712295 0.0661456 0.0614431 -1 -1 -1 -1 40 2973 25 6.99608e+06 309029 706193. 2443.58 5.72 0.370882 0.318658 26914 176310 -1 2620 23 2150 2820 218958 48809 3.61382 3.61382 -140.947 -3.61382 0 0 926341. 3205.33 0.04 0.09 0.14 -1 -1 0.04 0.033936 0.0295804 107 65 63 32 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 3.63 vpr 63.34 MiB 0.04 6976 -1 -1 1 0.03 -1 -1 30580 -1 -1 17 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 29 32 287 238 1 170 78 17 17 289 -1 unnamed_device 24.2 MiB 0.32 666 8876 3323 4226 1327 63.3 MiB 0.08 0.00 3.1285 -107.074 -3.1285 3.1285 0.33 0.000610837 0.000568394 0.0342537 0.0319048 -1 -1 -1 -1 34 2262 30 6.99608e+06 250167 618332. 2139.56 1.55 0.16008 0.138268 25762 151098 -1 1537 21 1619 2035 155412 38445 3.36877 3.36877 -119.496 -3.36877 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0244987 0.0212967 72 34 58 29 29 29 + fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 6.89 vpr 63.38 MiB 0.04 6968 -1 -1 1 0.03 -1 -1 30096 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 32 32 334 290 1 208 81 17 17 289 -1 unnamed_device 24.3 MiB 0.43 1166 6206 1355 4310 541 63.4 MiB 0.07 0.00 4.11048 -136.015 -4.11048 4.11048 0.33 0.000659925 0.000613867 0.0257308 0.0239495 -1 -1 -1 -1 40 2270 30 6.99608e+06 250167 706193. 2443.58 4.65 0.290196 0.248394 26914 176310 -1 2122 18 1181 1410 111217 24820 3.80255 3.80255 -133.933 -3.80255 0 0 926341. 3205.33 0.04 0.06 0.14 -1 -1 0.04 0.0241211 0.0210959 90 82 0 0 82 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_106.v common 3.73 vpr 64.18 MiB 0.04 7172 -1 -1 1 0.03 -1 -1 30372 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65716 31 32 365 281 1 217 82 17 17 289 -1 unnamed_device 24.5 MiB 0.32 1147 12898 4995 5597 2306 64.2 MiB 0.13 0.00 3.86834 -142 -3.86834 3.86834 0.33 0.000720904 0.000669682 0.0547434 0.0509063 -1 -1 -1 -1 36 3082 32 6.99608e+06 279598 648988. 2245.63 1.53 0.179425 0.157376 26050 158493 -1 2514 23 2327 3090 280116 62616 4.42821 4.42821 -161.244 -4.42821 0 0 828058. 2865.25 0.03 0.10 0.13 -1 -1 0.03 0.0318403 0.0277092 91 34 93 31 31 31 + fixed_k6_frac_2uripple_N8_22nm.xml mult_107.v common 3.26 vpr 63.38 MiB 0.02 7008 -1 -1 1 0.03 -1 -1 30424 -1 -1 19 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 29 32 297 254 1 181 80 17 17 289 -1 unnamed_device 24.2 MiB 0.31 830 9712 4017 5322 373 63.4 MiB 0.08 0.00 3.34864 -106.469 -3.34864 3.34864 0.33 0.000603881 0.000561558 0.0360932 0.0335729 -1 -1 -1 -1 40 1948 31 6.99608e+06 279598 706193. 2443.58 1.18 0.16134 0.13969 26914 176310 -1 1672 20 1255 1552 125286 28838 3.00031 3.00031 -107.625 -3.00031 0 0 926341. 3205.33 0.04 0.06 0.14 -1 -1 0.04 0.0241952 0.0210568 79 56 29 29 52 26 + fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 3.50 vpr 63.43 MiB 0.04 6912 -1 -1 1 0.03 -1 -1 30260 -1 -1 15 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 314 256 1 188 79 17 17 289 -1 unnamed_device 24.2 MiB 0.36 895 9881 4069 5606 206 63.4 MiB 0.09 0.00 3.0973 -120.067 -3.0973 3.0973 0.33 0.000650451 0.00059899 0.040462 0.0376572 -1 -1 -1 -1 40 2218 28 6.99608e+06 220735 706193. 2443.58 1.25 0.172399 0.149807 26914 176310 -1 1932 28 2074 2680 291160 87479 3.45207 3.45207 -131.583 -3.45207 0 0 926341. 3205.33 0.04 0.11 0.14 -1 -1 0.04 0.0330448 0.0286302 75 34 64 32 32 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 8.37 vpr 63.55 MiB 0.05 7192 -1 -1 1 0.03 -1 -1 30488 -1 -1 21 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65076 31 32 387 307 1 238 84 17 17 289 -1 unnamed_device 24.6 MiB 0.38 1114 13626 4545 6760 2321 63.6 MiB 0.13 0.00 3.60415 -130.344 -3.60415 3.60415 0.33 0.000744748 0.000692384 0.0583437 0.0540895 -1 -1 -1 -1 38 3132 24 6.99608e+06 309029 678818. 2348.85 6.02 0.349426 0.301337 26626 170182 -1 2521 25 2729 3732 309316 66755 3.77881 3.77881 -142.753 -3.77881 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66036 32 32 383 307 1 232 85 17 17 289 -1 unnamed_device 24.9 MiB 0.41 1097 14035 5866 7813 356 64.5 MiB 0.13 0.00 3.64125 -130.197 -3.64125 3.64125 0.33 0.000735643 0.000683183 0.0582656 0.0540201 -1 -1 -1 -1 44 2644 37 6.99608e+06 309029 787024. 2723.27 1.21 0.188576 0.16524 27778 195446 -1 2227 21 1685 2220 176554 44126 3.82396 3.82396 -138.43 -3.82396 0 0 997811. 3452.63 0.04 0.08 0.15 -1 -1 0.04 0.030419 0.0265708 102 65 52 26 64 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_112.v common 3.92 vpr 63.90 MiB 0.05 7264 -1 -1 1 0.03 -1 -1 30472 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65436 31 32 422 339 1 272 88 17 17 289 -1 unnamed_device 24.8 MiB 0.42 1424 15103 5056 7808 2239 63.9 MiB 0.15 0.00 4.24588 -151.83 -4.24588 4.24588 0.33 0.000788099 0.000731914 0.0637956 0.0591968 -1 -1 -1 -1 38 3816 42 6.99608e+06 367892 678818. 2348.85 1.54 0.2123 0.185979 26626 170182 -1 2995 20 2675 3652 293854 62663 4.19435 4.19435 -157.692 -4.19435 0 0 902133. 3121.57 0.03 0.10 0.13 -1 -1 0.03 0.0314511 0.0275132 119 93 31 31 92 31 + fixed_k6_frac_2uripple_N8_22nm.xml mult_113.v common 3.59 vpr 64.04 MiB 0.02 7004 -1 -1 1 0.03 -1 -1 30356 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65580 32 32 333 279 1 208 82 17 17 289 -1 unnamed_device 24.4 MiB 0.38 1167 13076 3755 7840 1481 64.0 MiB 0.12 0.00 3.22189 -126.373 -3.22189 3.22189 0.33 0.000671703 0.000618407 0.0512917 0.0475594 -1 -1 -1 -1 38 2940 44 6.99608e+06 264882 678818. 2348.85 1.37 0.173524 0.151669 26626 170182 -1 2358 19 1606 2229 178314 38534 3.34676 3.34676 -129.325 -3.34676 0 0 902133. 3121.57 0.03 0.07 0.13 -1 -1 0.03 0.0253234 0.0221217 85 61 32 32 60 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_114.v common 4.53 vpr 63.43 MiB 0.04 6888 -1 -1 1 0.03 -1 -1 30116 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64952 32 32 339 283 1 211 82 17 17 289 -1 unnamed_device 24.3 MiB 0.36 917 12364 4451 6156 1757 63.4 MiB 0.11 0.00 3.63989 -128.991 -3.63989 3.63989 0.33 0.00067204 0.000624224 0.0490385 0.0456041 -1 -1 -1 -1 42 2577 26 6.99608e+06 264882 744469. 2576.02 2.33 0.265612 0.229418 27202 183097 -1 1974 21 1463 1798 131008 32318 3.79276 3.79276 -142.235 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-1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 29 32 367 293 1 220 84 17 17 289 -1 unnamed_device 24.5 MiB 0.36 1112 11430 4239 5486 1705 63.6 MiB 0.11 0.00 3.04335 -110.206 -3.04335 3.04335 0.33 0.00071264 0.000659741 0.0475405 0.0441043 -1 -1 -1 -1 34 3058 35 6.99608e+06 338461 618332. 2139.56 4.45 0.300304 0.259023 25762 151098 -1 2487 20 1867 2516 191914 44595 3.32957 3.32957 -122.999 -3.32957 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0281985 0.0246124 101 62 56 29 58 29 + fixed_k6_frac_2uripple_N8_22nm.xml mult_117.v common 5.16 vpr 64.54 MiB 0.05 7184 -1 -1 1 0.03 -1 -1 30644 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66088 32 32 469 381 1 309 91 17 17 289 -1 unnamed_device 25.1 MiB 0.50 1451 17635 5731 9015 2889 64.5 MiB 0.18 0.00 4.9146 -172.985 -4.9146 4.9146 0.33 0.00087653 0.000815367 0.0780793 0.0726099 -1 -1 -1 -1 40 4076 36 6.99608e+06 397324 706193. 2443.58 2.78 0.372763 0.323318 26914 176310 -1 3032 23 2765 3245 274464 62366 5.7329 5.7329 -198.714 -5.7329 0 0 926341. 3205.33 0.03 0.07 0.10 -1 -1 0.03 0.0212485 0.0187799 132 127 0 0 128 32 + fixed_k6_frac_2uripple_N8_22nm.xml mult_118.v common 6.87 vpr 63.40 MiB 0.05 6944 -1 -1 1 0.03 -1 -1 30284 -1 -1 12 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 31 32 259 212 1 144 75 17 17 289 -1 unnamed_device 24.0 MiB 0.62 607 9713 4010 5428 275 63.4 MiB 0.08 0.00 2.81885 -98.97 -2.81885 2.81885 0.33 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65208 32 32 274 306 1 198 84 17 17 289 -1 unnamed_device 23.9 MiB 0.62 1234 12711 4362 6553 1796 63.7 MiB 0.13 0.00 6.93533 -144.489 -6.93533 6.93533 0.33 0.000900392 0.000834539 0.0661293 0.0613616 -1 -1 -1 -1 46 2868 32 6.79088e+06 269440 828058. 2865.25 2.76 0.335933 0.290814 27406 200422 -1 2349 17 1287 4024 196793 48150 5.78973 5.78973 -132.886 -5.78973 0 0 1.01997e+06 3529.29 0.04 0.08 0.16 -1 -1 0.04 0.0330675 0.0291265 135 180 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_004.v common 4.17 vpr 63.22 MiB 0.04 6708 -1 -1 12 0.33 -1 -1 32832 -1 -1 23 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65172 31 32 264 296 1 193 86 17 17 289 -1 unnamed_device 23.9 MiB 0.60 1220 9536 2544 6437 555 63.6 MiB 0.10 0.00 6.78954 -136.027 -6.78954 6.78954 0.33 0.000844903 0.000781822 0.0460384 0.0425566 -1 -1 -1 -1 38 3274 32 6.79088e+06 309856 678818. 2348.85 1.50 0.224921 0.194565 25966 169698 -1 2633 17 1198 3613 193992 44793 5.78203 5.78203 -131.142 -5.78203 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0310318 0.0272896 124 173 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_009.v common 5.81 vpr 62.96 MiB 0.04 6700 -1 -1 12 0.17 -1 -1 32412 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65840 32 32 361 393 1 259 92 17 17 289 -1 unnamed_device 24.7 MiB 0.72 1675 9821 2468 6259 1094 64.3 MiB 0.12 0.00 8.49462 -180.844 -8.49462 8.49462 0.33 0.00113116 0.00104754 0.0584007 0.0540699 -1 -1 -1 -1 32 5477 46 6.79088e+06 377216 586450. 2029.24 6.32 0.463813 0.400212 24814 144142 -1 4152 58 4745 16433 1624290 646059 8.00188 8.00188 -180.946 -8.00188 0 0 744469. 2576.02 0.03 0.62 0.12 -1 -1 0.03 0.121806 0.104932 187 267 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_058.v common 10.53 vpr 63.98 MiB 0.04 6704 -1 -1 13 0.29 -1 -1 32716 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 32 32 238 270 1 167 80 17 17 289 -1 unnamed_device 23.8 MiB 0.34 1009 10056 3067 4893 2096 63.3 MiB 0.10 0.00 6.37179 -142.275 -6.37179 6.37179 0.33 0.000734437 0.000680156 0.0458146 0.0424751 -1 -1 -1 -1 30 2840 28 6.79088e+06 215552 556674. 1926.21 2.68 0.234692 0.203008 24526 138013 -1 2125 20 991 2582 119455 29953 5.78618 5.78618 -138.331 -5.78618 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0297151 0.0260505 100 144 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_063.v common 5.58 vpr 63.25 MiB 0.05 6996 -1 -1 12 0.29 -1 -1 32852 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64712 32 32 277 309 1 207 86 17 17 289 -1 unnamed_device 24.2 MiB 0.60 1382 8591 2239 5858 494 63.2 MiB 0.10 0.00 7.91581 -161.259 -7.91581 7.91581 0.33 0.000913371 0.000847226 0.0450635 0.0417541 -1 -1 -1 -1 38 3350 25 6.79088e+06 296384 678818. 2348.85 2.32 0.2926 0.252355 25966 169698 -1 2787 16 1251 3857 189868 44623 7.15279 7.15279 -153.16 -7.15279 0 0 902133. 3121.57 0.03 0.08 0.13 -1 -1 0.03 0.0321713 0.0284014 138 183 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_078.v common 9.96 vpr 63.31 MiB 0.05 6804 -1 -1 13 0.33 -1 -1 33256 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 32 32 277 309 1 203 85 17 17 289 -1 unnamed_device 24.4 MiB 0.81 1340 13849 4059 7638 2152 63.4 MiB 0.14 0.00 7.74106 -161.688 -7.74106 7.74106 0.33 0.000906466 0.00084094 0.0714624 0.0662797 -1 -1 -1 -1 34 3696 38 6.79088e+06 282912 618332. 2139.56 1.21 0.234614 0.20537 25102 150614 -1 2984 20 1482 4209 226980 52735 6.74184 6.74184 -158.649 -6.74184 0 0 787024. 2723.27 0.03 0.09 0.12 -1 -1 0.03 0.037172 0.0325816 135 183 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_116.v common 3.73 vpr 62.84 MiB 0.02 6852 -1 -1 11 0.19 -1 -1 32724 -1 -1 22 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 32 32 235 267 1 174 85 17 17 289 -1 unnamed_device 24.0 MiB 0.42 1119 12361 3329 7454 1578 63.1 MiB 0.11 0.00 7.36852 -166.004 -7.36852 7.36852 0.33 0.000750919 0.000696197 0.0528367 0.0489875 -1 -1 -1 -1 36 2782 17 6.79088e+06 282912 648988. 2245.63 2.17 0.273945 0.237408 25390 158009 -1 2366 14 955 2497 138037 32540 6.58432 6.58432 -158.848 -6.58432 0 0 828058. 2865.25 0.03 0.06 0.12 -1 -1 0.03 0.0242351 0.0214443 107 141 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_121.v common 5.48 vpr 63.56 MiB 0.05 6808 -1 -1 12 0.22 -1 -1 32888 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65088 32 32 265 297 1 192 85 17 17 289 -1 unnamed_device 23.8 MiB 1.07 1078 14593 5070 7208 2315 63.6 MiB 0.15 0.00 7.08202 -153.624 -7.08202 7.08202 0.33 0.000866045 0.000801126 0.0729181 0.0675734 -1 -1 -1 -1 42 2583 22 6.79088e+06 282912 744469. 2576.02 2.28 0.325852 0.282352 26542 182613 -1 2078 15 1025 2965 145160 36401 5.91852 5.91852 -141.174 -5.91852 0 0 949917. 3286.91 0.04 0.07 0.15 -1 -1 0.04 0.0306689 0.0271112 125 171 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_122.v common 5.02 vpr 64.26 MiB 0.05 6984 -1 -1 15 0.47 -1 -1 32836 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65804 32 32 344 376 1 252 91 17 17 289 -1 unnamed_device 24.5 MiB 0.82 1721 10291 2790 6459 1042 64.3 MiB 0.13 0.00 9.60297 -194.922 -9.60297 9.60297 0.33 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64844 30 32 409 330 1 192 86 17 17 289 -1 unnamed_device 24.2 MiB 2.95 1037 12749 4416 6197 2136 63.3 MiB 0.14 0.00 4.18449 -135.92 -4.18449 4.18449 0.33 0.000755725 0.000701569 0.0532811 0.0494806 -1 -1 -1 -1 32 2593 34 6.87369e+06 335372 586450. 2029.24 0.65 0.154987 0.136111 25474 144626 -1 1987 22 1738 2948 159843 42253 3.7121 3.7121 -137.584 -3.7121 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0313519 0.0271426 141 91 30 30 89 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_003.v common 5.86 vpr 63.40 MiB 0.04 7016 -1 -1 1 0.03 -1 -1 30396 -1 -1 36 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 32 32 387 309 1 191 100 17 17 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Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64884 27 32 269 226 1 146 79 17 17 289 -1 unnamed_device 23.7 MiB 1.93 818 12923 4188 6960 1775 63.4 MiB 0.12 0.00 3.47075 -103.849 -3.47075 3.47075 0.33 0.000565726 0.000526652 0.0450654 0.0419682 -1 -1 -1 -1 32 1806 29 6.87369e+06 279477 586450. 2029.24 1.47 0.222765 0.191829 25474 144626 -1 1564 22 1168 2001 119983 28902 2.91296 2.91296 -103.344 -2.91296 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0235488 0.0203495 103 34 54 27 27 27 + fixed_k6_frac_ripple_N8_22nm.xml mult_008.v common 4.45 vpr 63.29 MiB 0.05 7088 -1 -1 1 0.03 -1 -1 30228 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64808 31 32 317 242 1 187 98 17 17 289 -1 unnamed_device 24.3 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 32 32 331 280 1 161 96 17 17 289 -1 unnamed_device 24.0 MiB 1.62 993 13236 3578 8478 1180 63.2 MiB 0.13 0.00 3.48455 -118.435 -3.48455 3.48455 0.33 0.000657594 0.000609717 0.0418718 0.0388044 -1 -1 -1 -1 32 2209 21 6.87369e+06 447163 586450. 2029.24 1.52 0.228799 0.197263 25474 144626 -1 1846 20 1139 1945 130898 31151 2.66236 2.66236 -110.707 -2.66236 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0247864 0.0214565 116 65 25 25 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_013.v common 6.98 vpr 63.43 MiB 0.05 7136 -1 -1 1 0.03 -1 -1 30300 -1 -1 35 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64948 32 32 386 305 1 195 99 17 17 289 -1 unnamed_device 24.3 MiB 4.17 977 19707 6512 10053 3142 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0.04 7144 -1 -1 1 0.03 -1 -1 30520 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64972 32 32 401 315 1 200 86 17 17 289 -1 unnamed_device 24.3 MiB 2.82 1115 15773 4732 9095 1946 63.4 MiB 0.16 0.00 3.52575 -125.388 -3.52575 3.52575 0.33 0.000772531 0.000717559 0.0662559 0.0615514 -1 -1 -1 -1 32 2906 30 6.87369e+06 307425 586450. 2029.24 2.19 0.312394 0.27116 25474 144626 -1 2427 22 2029 3433 234126 57574 3.09026 3.09026 -131.793 -3.09026 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0317234 0.0275455 145 63 64 32 62 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 6.95 vpr 63.33 MiB 0.05 7144 -1 -1 1 0.03 -1 -1 30240 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 383 303 1 193 103 17 17 289 -1 unnamed_device 24.3 MiB 4.17 1033 10225 2381 7241 603 63.3 MiB 0.09 0.00 3.55695 -125.38 -3.55695 3.55695 0.33 0.000527944 0.000479759 0.0252969 0.0231207 -1 -1 -1 -1 30 2330 25 6.87369e+06 544980 556674. 1926.21 0.98 0.116663 0.100789 25186 138497 -1 1916 23 1479 2321 129964 32109 2.88996 2.88996 -119.301 -2.88996 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0315576 0.0273331 148 57 64 32 56 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 5.64 vpr 63.15 MiB 0.04 6840 -1 -1 1 0.03 -1 -1 30132 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 32 32 339 284 1 165 94 17 17 289 -1 unnamed_device 24.2 MiB 2.29 861 16495 5119 8899 2477 63.1 MiB 0.15 0.00 2.97721 -105.51 -2.97721 2.97721 0.33 0.000672635 0.00062511 0.0542118 0.0503248 -1 -1 -1 -1 32 2032 26 6.87369e+06 419215 586450. 2029.24 1.52 0.22393 0.194297 25474 144626 -1 1525 20 1283 2179 122131 32242 2.16112 2.16112 -94.0688 -2.16112 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0255937 0.0221844 118 65 29 29 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 3.20 vpr 63.31 MiB 0.04 6716 -1 -1 1 0.03 -1 -1 30272 -1 -1 15 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64832 30 32 226 208 1 119 77 17 17 289 -1 unnamed_device 23.7 MiB 0.83 708 9042 3454 4658 930 63.3 MiB 0.07 0.00 2.76391 -93.2661 -2.76391 2.76391 0.33 0.00050239 0.000467889 0.0294658 0.0274435 -1 -1 -1 -1 32 1457 18 6.87369e+06 209608 586450. 2029.24 0.68 0.101206 0.0883047 25474 144626 -1 1255 15 579 856 60701 14448 1.84342 1.84342 -82.8045 -1.84342 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0155573 0.0135349 73 34 24 24 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 4.00 vpr 63.68 MiB 0.04 6924 -1 -1 1 0.03 -1 -1 30368 -1 -1 19 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65208 31 32 335 280 1 165 82 17 17 289 -1 unnamed_device 24.0 MiB 1.56 906 13610 3953 7473 2184 63.7 MiB 0.13 0.00 4.23969 -129.95 -4.23969 4.23969 0.34 0.000673921 0.00062764 0.053103 0.0494269 -1 -1 -1 -1 32 2070 22 6.87369e+06 265503 586450. 2029.24 0.57 0.131366 0.116249 25474 144626 -1 1697 15 912 1358 93698 21781 3.1389 3.1389 -120.145 -3.1389 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.02054 0.017889 113 64 31 31 62 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 3.75 vpr 63.82 MiB 0.04 7052 -1 -1 1 0.03 -1 -1 30136 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65352 32 32 366 283 1 197 102 17 17 289 -1 unnamed_device 24.2 MiB 1.07 1119 17952 5305 10368 2279 63.8 MiB 0.16 0.00 4.22105 -144.562 -4.22105 4.22105 0.33 0.000731228 0.000679596 0.0578907 0.0537838 -1 -1 -1 -1 32 2576 22 6.87369e+06 531006 586450. 2029.24 0.81 0.165502 0.145799 25474 144626 -1 2079 21 1588 2325 140087 33143 3.5888 3.5888 -137.535 -3.5888 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0287367 0.024956 151 34 91 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_022.v common 6.10 vpr 63.68 MiB 0.05 7192 -1 -1 1 0.03 -1 -1 30620 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65204 32 32 460 375 1 199 104 17 17 289 -1 unnamed_device 24.6 MiB 2.80 1172 19624 5698 11079 2847 63.7 MiB 0.15 0.00 3.80272 -131.055 -3.80272 3.80272 0.35 0.000381998 0.000351029 0.0474611 0.0436295 -1 -1 -1 -1 28 3282 32 6.87369e+06 558954 531479. 1839.03 1.38 0.160013 0.139393 24610 126494 -1 2623 24 1856 3107 291154 78871 3.855 3.855 -141.694 -3.855 0 0 648988. 2245.63 0.03 0.11 0.10 -1 -1 0.03 0.0364804 0.0313998 154 124 0 0 125 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 4.68 vpr 63.19 MiB 0.04 6700 -1 -1 1 0.02 -1 -1 30708 -1 -1 18 26 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64708 26 32 198 186 1 109 76 17 17 289 -1 unnamed_device 23.7 MiB 1.66 596 9676 3280 4936 1460 63.2 MiB 0.07 0.00 2.74191 -77.6931 -2.74191 2.74191 0.33 0.000442931 0.000412026 0.0281821 0.0262149 -1 -1 -1 -1 32 1249 22 6.87369e+06 251529 586450. 2029.24 1.29 0.154764 0.133132 25474 144626 -1 1132 20 607 999 75312 18294 2.03582 2.03582 -76.1177 -2.03582 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0171715 0.0148634 70 30 26 26 22 22 + fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 4.99 vpr 63.30 MiB 0.04 6932 -1 -1 1 0.03 -1 -1 30112 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 333 251 1 196 87 17 17 289 -1 unnamed_device 24.3 MiB 1.41 1189 15831 5026 8598 2207 63.3 MiB 0.16 0.00 4.1666 -144.095 -4.1666 4.1666 0.33 0.000685072 0.000637317 0.0587906 0.0546903 -1 -1 -1 -1 32 2811 25 6.87369e+06 321398 586450. 2029.24 1.67 0.263581 0.229024 25474 144626 -1 2285 22 1540 2599 177810 42595 3.8734 3.8734 -148.875 -3.8734 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.028838 0.0250352 143 3 122 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 3.53 vpr 63.11 MiB 0.04 6796 -1 -1 1 0.03 -1 -1 30424 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64628 32 32 199 182 1 122 77 17 17 289 -1 unnamed_device 23.7 MiB 0.60 804 11324 4283 5922 1119 63.1 MiB 0.09 0.00 2.37678 -91.0069 -2.37678 2.37678 0.33 0.000467352 0.000434509 0.0338642 0.0314978 -1 -1 -1 -1 30 1526 21 6.87369e+06 181660 556674. 1926.21 1.26 0.142626 0.124141 25186 138497 -1 1276 15 532 689 48402 11520 1.93872 1.93872 -87.9909 -1.93872 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0146748 0.012876 72 3 53 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 5.40 vpr 63.95 MiB 0.05 7080 -1 -1 1 0.03 -1 -1 30516 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65480 32 32 376 288 1 202 101 17 17 289 -1 unnamed_device 24.2 MiB 0.88 969 13261 3427 8940 894 63.9 MiB 0.14 0.00 4.32457 -145.823 -4.32457 4.32457 0.33 0.000742868 0.000691175 0.0440029 0.040873 -1 -1 -1 -1 28 3100 47 6.87369e+06 517032 531479. 1839.03 2.61 0.269503 0.233255 24610 126494 -1 2411 23 2057 3269 242126 62287 4.5109 4.5109 -157.957 -4.5109 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0315161 0.0273367 155 34 96 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 4.00 vpr 63.46 MiB 0.04 7080 -1 -1 1 0.03 -1 -1 30120 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 32 32 337 253 1 198 101 17 17 289 -1 unnamed_device 24.4 MiB 0.92 1115 9736 2184 6547 1005 63.5 MiB 0.11 0.00 3.53495 -124.767 -3.53495 3.53495 0.33 0.000708282 0.000654294 0.0311928 0.0289347 -1 -1 -1 -1 30 2469 22 6.87369e+06 517032 556674. 1926.21 1.28 0.189028 0.163454 25186 138497 -1 2002 21 1395 2409 133701 32486 2.89016 2.89016 -117.09 -2.89016 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0278384 0.0241707 151 3 124 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_028.v common 6.37 vpr 64.21 MiB 0.05 7124 -1 -1 1 0.03 -1 -1 30532 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65752 32 32 407 319 1 202 104 17 17 289 -1 unnamed_device 24.7 MiB 1.13 1055 13036 3588 8403 1045 64.2 MiB 0.14 0.00 4.2809 -144.104 -4.2809 4.2809 0.33 0.00078174 0.000726997 0.0437557 0.0405274 -1 -1 -1 -1 28 3474 41 6.87369e+06 558954 531479. 1839.03 3.28 0.255436 0.22109 24610 126494 -1 2528 22 2162 3811 289506 69194 4.03971 4.03971 -155.286 -4.03971 0 0 648988. 2245.63 0.03 0.10 0.10 -1 -1 0.03 0.0313674 0.0271723 156 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_029.v common 4.15 vpr 63.41 MiB 0.04 6824 -1 -1 1 0.03 -1 -1 30108 -1 -1 16 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64928 32 32 294 246 1 157 80 17 17 289 -1 unnamed_device 24.0 MiB 1.15 754 11948 3802 6412 1734 63.4 MiB 0.11 0.00 3.07332 -107.198 -3.07332 3.07332 0.33 0.000611879 0.000569338 0.0445328 0.0414247 -1 -1 -1 -1 30 1864 23 6.87369e+06 223581 556674. 1926.21 1.25 0.186041 0.161539 25186 138497 -1 1405 19 817 1358 76499 19622 2.60936 2.60936 -106.109 -2.60936 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.022867 0.0198891 104 34 54 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_030.v common 3.52 vpr 63.02 MiB 0.04 6976 -1 -1 1 0.03 -1 -1 30088 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 30 32 296 244 1 160 81 17 17 289 -1 unnamed_device 24.0 MiB 1.13 897 12156 3930 6335 1891 63.0 MiB 0.12 0.00 3.54295 -120.85 -3.54295 3.54295 0.33 0.000612449 0.000569801 0.0444946 0.0413873 -1 -1 -1 -1 32 1986 25 6.87369e+06 265503 586450. 2029.24 0.56 0.119501 0.105273 25474 144626 -1 1615 22 1274 1935 140595 32787 2.83966 2.83966 -116.899 -2.83966 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0256004 0.0221305 109 34 60 30 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_031.v common 4.51 vpr 63.31 MiB 0.05 6888 -1 -1 1 0.03 -1 -1 30252 -1 -1 20 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 28 32 278 232 1 150 80 17 17 289 -1 unnamed_device 23.6 MiB 1.22 721 12808 3405 8634 769 63.3 MiB 0.12 0.00 3.48175 -105.896 -3.48175 3.48175 0.33 0.00058427 0.00054379 0.0457607 0.0426031 -1 -1 -1 -1 32 1911 27 6.87369e+06 279477 586450. 2029.24 1.47 0.196705 0.170264 25474 144626 -1 1576 20 1146 1943 113904 29907 3.02426 3.02426 -108.885 -3.02426 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0226945 0.0194929 104 34 56 28 28 28 + fixed_k6_frac_ripple_N8_22nm.xml mult_032.v common 4.26 vpr 63.03 MiB 0.04 6784 -1 -1 1 0.03 -1 -1 30372 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64544 32 32 283 225 1 168 83 17 17 289 -1 unnamed_device 23.9 MiB 1.55 989 9983 2839 5973 1171 63.0 MiB 0.10 0.00 3.52575 -126.669 -3.52575 3.52575 0.33 0.00061684 0.00057454 0.0357093 0.0332609 -1 -1 -1 -1 32 2281 37 6.87369e+06 265503 586450. 2029.24 0.85 0.141467 0.123329 25474 144626 -1 1904 21 1562 2639 186474 42654 2.76766 2.76766 -121.308 -2.76766 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0248173 0.0215091 115 3 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_033.v common 3.22 vpr 63.66 MiB 0.05 6980 -1 -1 1 0.03 -1 -1 30248 -1 -1 32 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65188 31 32 303 249 1 163 95 17 17 289 -1 unnamed_device 24.0 MiB 0.78 845 15215 4592 7994 2629 63.7 MiB 0.14 0.00 3.50375 -117.395 -3.50375 3.50375 0.33 0.000626809 0.000582838 0.0461669 0.0429028 -1 -1 -1 -1 32 2080 22 6.87369e+06 447163 586450. 2029.24 0.58 0.119837 0.105722 25474 144626 -1 1622 23 1301 2198 133984 33915 2.85066 2.85066 -110.644 -2.85066 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0269005 0.0233078 119 34 61 31 31 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 5.52 vpr 63.15 MiB 0.03 6928 -1 -1 1 0.03 -1 -1 30152 -1 -1 33 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 29 32 312 264 1 154 94 17 17 289 -1 unnamed_device 23.9 MiB 2.36 922 12022 3402 7419 1201 63.1 MiB 0.11 0.00 2.87654 -95.4564 -2.87654 2.87654 0.33 0.000623822 0.000578701 0.0370939 0.034354 -1 -1 -1 -1 32 1829 20 6.87369e+06 461137 586450. 2029.24 1.44 0.215994 0.185864 25474 144626 -1 1603 17 984 1705 94014 23813 2.02952 2.02952 -88.5363 -2.02952 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65556 32 32 403 317 1 200 103 17 17 289 -1 unnamed_device 24.5 MiB 2.69 1161 9984 2299 6887 798 64.0 MiB 0.12 0.00 3.66173 -128.462 -3.66173 3.66173 0.33 0.000770426 0.000715526 0.0351384 0.0325169 -1 -1 -1 -1 28 2693 27 6.87369e+06 544980 531479. 1839.03 1.55 0.243432 0.209689 24610 126494 -1 2360 19 1925 2873 182260 45046 2.99616 2.99616 -129.298 -2.99616 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0280704 0.024391 154 65 62 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_037.v common 6.30 vpr 63.27 MiB 0.05 7076 -1 -1 1 0.03 -1 -1 30508 -1 -1 31 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 31 32 353 302 1 160 94 17 17 289 -1 unnamed_device 24.0 MiB 3.14 911 12661 3506 8208 947 63.3 MiB 0.12 0.00 3.47075 -118.785 -3.47075 3.47075 0.33 0.000679038 0.000629437 0.0422431 0.0391776 -1 -1 -1 -1 28 2101 21 6.87369e+06 433189 531479. 1839.03 1.35 0.218656 0.18868 24610 126494 -1 1923 21 1291 2156 139833 35089 3.06856 3.06856 -119.491 -3.06856 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0268995 0.0232219 116 90 0 0 89 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_038.v common 5.13 vpr 63.39 MiB 0.05 7148 -1 -1 1 0.03 -1 -1 30360 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 31 32 391 309 1 195 86 17 17 289 -1 unnamed_device 24.2 MiB 2.27 1158 14639 5381 7464 1794 63.4 MiB 0.17 0.00 3.53495 -122.885 -3.53495 3.53495 0.33 0.000742938 0.00068998 0.0600531 0.0557636 -1 -1 -1 -1 32 2673 35 6.87369e+06 321398 586450. 2029.24 0.89 0.196215 0.171741 25474 144626 -1 2240 20 1617 2629 179174 42111 3.13256 3.13256 -125.645 -3.13256 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0288827 0.02511 141 64 60 30 62 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_039.v common 7.79 vpr 63.59 MiB 0.05 7320 -1 -1 1 0.03 -1 -1 30488 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65112 31 32 455 371 1 198 86 17 17 289 -1 unnamed_device 24.5 MiB 4.95 1142 15773 5258 8448 2067 63.6 MiB 0.18 0.00 4.89027 -151.644 -4.89027 4.89027 0.33 0.000842905 0.000783698 0.0723096 0.0672411 -1 -1 -1 -1 32 2743 25 6.87369e+06 321398 586450. 2029.24 0.85 0.198848 0.174671 25474 144626 -1 2290 21 1515 2578 168142 40772 3.93805 3.93805 -146.284 -3.93805 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65496 31 32 391 309 1 195 99 17 17 289 -1 unnamed_device 24.3 MiB 2.30 1085 13323 3719 8474 1130 64.0 MiB 0.15 0.00 3.56305 -121.781 -3.56305 3.56305 0.33 0.000750292 0.000695055 0.0469947 0.043466 -1 -1 -1 -1 32 2458 26 6.87369e+06 503058 586450. 2029.24 0.83 0.164638 0.143846 25474 144626 -1 1962 21 1734 3018 163687 41150 2.98326 2.98326 -115.348 -2.98326 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0302449 0.0263189 149 64 60 31 62 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 8.17 vpr 64.33 MiB 0.05 7208 -1 -1 1 0.03 -1 -1 30508 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65876 32 32 407 319 1 202 103 17 17 289 -1 unnamed_device 24.8 MiB 1.74 1175 14322 3573 9808 941 64.3 MiB 0.15 0.00 4.3428 -150.925 -4.3428 4.3428 0.33 0.0007668 0.000712902 0.0478086 0.0443512 -1 -1 -1 -1 26 3596 47 6.87369e+06 544980 503264. 1741.40 4.48 0.334679 0.288774 24322 120374 -1 2764 34 2811 4835 447833 101045 4.5329 4.5329 -163.977 -4.5329 0 0 618332. 2139.56 0.03 0.14 0.10 -1 -1 0.03 0.0446884 0.0385203 156 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_043.v common 5.61 vpr 64.00 MiB 0.05 7292 -1 -1 1 0.03 -1 -1 30764 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65540 32 32 496 380 1 234 106 17 17 289 -1 unnamed_device 25.0 MiB 2.89 1315 14106 3332 9481 1293 64.0 MiB 0.18 0.00 4.3641 -148.76 -4.3641 4.3641 0.33 0.000913768 0.000848271 0.0544141 0.0505209 -1 -1 -1 -1 32 3325 28 6.87369e+06 586901 586450. 2029.24 0.69 0.170009 0.149215 25474 144626 -1 2623 22 2115 3321 198523 50434 4.0397 4.0397 -157.94 -4.0397 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.037404 0.0324118 186 96 62 32 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_044.v common 4.39 vpr 62.99 MiB 0.04 6960 -1 -1 1 0.03 -1 -1 30552 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64500 31 32 305 250 1 164 81 17 17 289 -1 unnamed_device 23.9 MiB 2.07 945 8306 2134 5368 804 63.0 MiB 0.09 0.00 3.51475 -122.042 -3.51475 3.51475 0.33 0.0006264 0.000583386 0.0316576 0.0294713 -1 -1 -1 -1 32 2051 21 6.87369e+06 251529 586450. 2029.24 0.57 0.104635 0.0918106 25474 144626 -1 1786 20 1319 2146 137058 32821 2.95396 2.95396 -122.035 -2.95396 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64876 32 32 397 313 1 198 99 17 17 289 -1 unnamed_device 24.2 MiB 1.72 1312 16515 4792 9681 2042 63.4 MiB 0.18 0.00 3.52701 -124.222 -3.52701 3.52701 0.33 0.000756812 0.000701615 0.0574427 0.053151 -1 -1 -1 -1 30 2985 27 6.87369e+06 489084 556674. 1926.21 0.80 0.151833 0.133736 25186 138497 -1 2612 18 1625 2936 191570 44956 2.88196 2.88196 -120.53 -2.88196 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.0264691 0.023027 150 63 62 32 62 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_047.v common 4.30 vpr 63.34 MiB 0.05 7036 -1 -1 1 0.03 -1 -1 30464 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64864 32 32 345 257 1 202 87 17 17 289 -1 unnamed_device 24.3 MiB 1.76 1031 15447 4347 9193 1907 63.3 MiB 0.17 0.00 4.1996 -144.506 -4.1996 4.1996 0.33 0.000706404 0.000657267 0.0588578 0.0547481 -1 -1 -1 -1 32 2895 23 6.87369e+06 321398 586450. 2029.24 0.66 0.143471 0.127238 25474 144626 -1 2288 23 2010 3668 237373 58414 3.8954 3.8954 -150.851 -3.8954 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0303079 0.0263189 147 3 128 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_048.v common 6.83 vpr 63.51 MiB 0.05 7088 -1 -1 1 0.03 -1 -1 30368 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65036 32 32 424 343 1 195 104 17 17 289 -1 unnamed_device 24.5 MiB 3.47 1164 18648 5381 11612 1655 63.5 MiB 0.18 0.00 3.52575 -126.751 -3.52575 3.52575 0.33 0.000780876 0.000725701 0.0634594 0.0587907 -1 -1 -1 -1 26 2648 39 6.87369e+06 558954 503264. 1741.40 1.44 0.252115 0.219239 24322 120374 -1 2239 22 1531 2600 178956 42448 3.24386 3.24386 -130.882 -3.24386 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0319613 0.027676 150 96 25 25 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_049.v common 6.86 vpr 63.62 MiB 0.05 7152 -1 -1 1 0.03 -1 -1 30368 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65148 32 32 395 311 1 198 103 17 17 289 -1 unnamed_device 24.5 MiB 3.34 1149 18178 5141 10104 2933 63.6 MiB 0.18 0.00 3.65105 -129.099 -3.65105 3.65105 0.33 0.000765584 0.000711031 0.0596975 0.0554178 -1 -1 -1 -1 28 2782 22 6.87369e+06 544980 531479. 1839.03 1.60 0.255503 0.22208 24610 126494 -1 2328 21 1707 3104 208619 51126 3.38476 3.38476 -123.951 -3.38476 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0304756 0.0264434 152 61 64 32 60 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_050.v common 6.72 vpr 64.06 MiB 0.05 7156 -1 -1 1 0.03 -1 -1 30428 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65596 32 32 405 318 1 201 104 17 17 289 -1 unnamed_device 24.5 MiB 2.76 1197 19868 5863 11669 2336 64.1 MiB 0.20 0.00 3.61805 -127.892 -3.61805 3.61805 0.33 0.000769266 0.000714418 0.0653848 0.0605519 -1 -1 -1 -1 28 3033 24 6.87369e+06 558954 531479. 1839.03 1.97 0.277699 0.241262 24610 126494 -1 2594 22 2007 3268 239230 57218 3.27506 3.27506 -132.18 -3.27506 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0318897 0.027649 156 65 63 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 2.89 vpr 64.03 MiB 0.02 7140 -1 -1 1 0.04 -1 -1 30520 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65564 32 32 376 288 1 202 104 17 17 289 -1 unnamed_device 24.3 MiB 0.93 1150 19136 5645 11051 2440 64.0 MiB 0.10 0.00 4.23385 -148.233 -4.23385 4.23385 0.25 0.000325426 0.00029842 0.0272704 0.0250031 -1 -1 -1 -1 32 2791 24 6.87369e+06 558954 586450. 2029.24 0.41 0.0701023 0.0617397 25474 144626 -1 2250 23 1968 3230 221453 52196 3.7891 3.7891 -147.336 -3.7891 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0315215 0.0273298 156 34 96 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_052.v common 6.51 vpr 64.16 MiB 0.05 7244 -1 -1 1 0.03 -1 -1 30784 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65700 32 32 407 319 1 202 105 17 17 289 -1 unnamed_device 24.6 MiB 2.62 1145 20606 5563 13214 1829 64.2 MiB 0.20 0.00 4.1996 -142.893 -4.1996 4.1996 0.33 0.000773114 0.000717867 0.0667821 0.0618703 -1 -1 -1 -1 34 2517 29 6.87369e+06 572927 618332. 2139.56 1.95 0.30449 0.263883 25762 151098 -1 2214 22 1811 2978 183813 46622 3.9067 3.9067 -149.325 -3.9067 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0313269 0.0271562 157 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 7.82 vpr 63.69 MiB 0.05 7392 -1 -1 1 0.03 -1 -1 30528 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65220 31 32 449 367 1 195 100 17 17 289 -1 unnamed_device 24.7 MiB 3.63 1067 17268 4540 10656 2072 63.7 MiB 0.18 0.00 4.21489 -136.932 -4.21489 4.21489 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64820 32 32 370 314 1 166 82 17 17 289 -1 unnamed_device 24.3 MiB 2.68 980 13788 4117 8145 1526 63.3 MiB 0.15 0.00 3.56085 -129.056 -3.56085 3.56085 0.33 0.000703297 0.000652593 0.0566934 0.0526315 -1 -1 -1 -1 30 2359 21 6.87369e+06 251529 556674. 1926.21 1.44 0.219007 0.190404 25186 138497 -1 1930 22 1354 2129 140760 32404 2.88186 2.88186 -125.993 -2.88186 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0291445 0.0252505 113 94 0 0 94 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 5.19 vpr 64.33 MiB 0.05 7288 -1 -1 1 0.03 -1 -1 30756 -1 -1 45 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0.33 0.000715182 0.000666935 0.0354636 0.0329477 -1 -1 -1 -1 32 2542 20 6.87369e+06 489084 586450. 2029.24 1.53 0.209861 0.181299 25474 144626 -1 2038 20 1385 2121 129429 31025 3.05446 3.05446 -125.324 -3.05446 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0279555 0.0243171 150 34 92 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_059.v common 3.96 vpr 63.70 MiB 0.05 6880 -1 -1 1 0.03 -1 -1 30436 -1 -1 31 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65228 30 32 296 244 1 160 93 17 17 289 -1 unnamed_device 24.1 MiB 0.64 720 11853 2709 7510 1634 63.7 MiB 0.10 0.00 3.58505 -114.7 -3.58505 3.58505 0.33 0.000617614 0.000575341 0.0369468 0.0342607 -1 -1 -1 -1 30 2038 29 6.87369e+06 433189 556674. 1926.21 1.56 0.202629 0.174747 25186 138497 -1 1489 21 1124 1783 90984 26180 2.85866 2.85866 -114.937 -2.85866 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65480 32 32 376 288 1 202 104 17 17 289 -1 unnamed_device 24.2 MiB 2.88 1096 19624 5769 11241 2614 63.9 MiB 0.18 0.00 4.2308 -146.72 -4.2308 4.2308 0.33 0.000746072 0.000692515 0.0625144 0.0579168 -1 -1 -1 -1 32 2571 23 6.87369e+06 558954 586450. 2029.24 0.60 0.151855 0.134453 25474 144626 -1 2045 21 1677 2570 158948 39079 3.8456 3.8456 -143.771 -3.8456 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0292746 0.0254061 156 34 96 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_062.v common 4.22 vpr 63.06 MiB 0.04 6872 -1 -1 1 0.03 -1 -1 30288 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64576 32 32 283 225 1 168 98 17 17 289 -1 unnamed_device 23.9 MiB 0.88 899 18098 6040 9605 2453 63.1 MiB 0.15 0.00 3.61805 -127.303 -3.61805 3.61805 0.33 0.000613324 0.000570955 0.0511833 0.0475788 -1 -1 -1 -1 32 2263 22 6.87369e+06 475111 586450. 2029.24 1.52 0.202656 0.176277 25474 144626 -1 1761 21 1383 2192 151668 36597 2.95696 2.95696 -121.662 -2.95696 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0244908 0.0212215 123 3 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 6.60 vpr 64.32 MiB 0.05 7212 -1 -1 1 0.03 -1 -1 30864 -1 -1 45 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65868 32 32 438 320 1 236 109 17 17 289 -1 unnamed_device 24.6 MiB 2.54 1291 20389 5708 11832 2849 64.3 MiB 0.22 0.00 4.94208 -168.29 -4.94208 4.94208 0.33 0.000850867 0.000791664 0.0695921 0.0646805 -1 -1 -1 -1 32 3292 27 6.87369e+06 628823 586450. 2029.24 2.04 0.327614 0.283956 25474 144626 -1 2625 22 2526 4446 310721 73337 4.56925 4.56925 -171.748 -4.56925 0 0 744469. 2576.02 0.03 0.11 0.12 -1 -1 0.03 0.0352502 0.0305223 189 34 128 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 4.15 vpr 63.11 MiB 0.04 6780 -1 -1 1 0.03 -1 -1 30408 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64624 32 32 283 225 1 168 82 17 17 289 -1 unnamed_device 24.0 MiB 1.56 947 13610 4549 7009 2052 63.1 MiB 0.13 0.00 3.54365 -126.361 -3.54365 3.54365 0.33 0.000611131 0.000568901 0.0486451 0.0452949 -1 -1 -1 -1 32 2213 19 6.87369e+06 251529 586450. 2029.24 0.78 0.13438 0.118327 25474 144626 -1 1884 21 1485 2490 174745 40690 2.95696 2.95696 -125.229 -2.95696 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0245192 0.0212342 114 3 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 5.23 vpr 63.18 MiB 0.05 6880 -1 -1 1 0.03 -1 -1 30368 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64696 30 32 296 244 1 162 95 17 17 289 -1 unnamed_device 24.1 MiB 1.94 847 12839 3221 8494 1124 63.2 MiB 0.12 0.00 3.53801 -116.955 -3.53801 3.53801 0.33 0.000621705 0.00057914 0.0385308 0.0358153 -1 -1 -1 -1 26 2367 31 6.87369e+06 461137 503264. 1741.40 1.48 0.188074 0.162548 24322 120374 -1 1900 21 1392 2297 159121 39320 3.08556 3.08556 -121.668 -3.08556 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0246692 0.0213 118 34 60 30 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 6.21 vpr 63.55 MiB 0.05 7276 -1 -1 1 0.03 -1 -1 30404 -1 -1 35 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65080 29 32 393 319 1 184 96 17 17 289 -1 unnamed_device 24.4 MiB 2.83 979 10827 2630 7177 1020 63.6 MiB 0.12 0.00 3.61805 -112.96 -3.61805 3.61805 0.33 0.000739424 0.000687465 0.038744 0.0359292 -1 -1 -1 -1 30 2274 23 6.87369e+06 489084 556674. 1926.21 1.55 0.229251 0.197547 25186 138497 -1 1721 19 1105 1908 90980 24484 2.75066 2.75066 -107.331 -2.75066 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0268335 0.0233232 141 88 29 29 85 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_067.v common 5.75 vpr 63.53 MiB 0.05 7208 -1 -1 1 0.03 -1 -1 30672 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65052 32 32 407 319 1 202 87 17 17 289 -1 unnamed_device 24.3 MiB 2.33 930 7959 1713 5891 355 63.5 MiB 0.11 0.00 4.2388 -145.479 -4.2388 4.2388 0.33 0.000774665 0.000717646 0.0344985 0.0319606 -1 -1 -1 -1 30 2629 23 6.87369e+06 321398 556674. 1926.21 1.57 0.209352 0.180755 25186 138497 -1 1871 18 1718 2679 166549 40728 3.648 3.648 -141.73 -3.648 0 0 706193. 2443.58 0.03 0.09 0.11 -1 -1 0.03 0.0328073 0.0285125 147 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_068.v common 6.64 vpr 64.01 MiB 0.05 7196 -1 -1 1 0.03 -1 -1 30632 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65548 32 32 407 319 1 202 102 17 17 289 -1 unnamed_device 24.2 MiB 3.99 1011 13192 3264 8603 1325 64.0 MiB 0.14 0.00 4.2699 -143.724 -4.2699 4.2699 0.33 0.00077125 0.000716466 0.0452503 0.0419891 -1 -1 -1 -1 30 2526 23 6.87369e+06 531006 556674. 1926.21 0.76 0.136836 0.120435 25186 138497 -1 2010 23 1859 3223 181999 45116 3.6168 3.6168 -139.905 -3.6168 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.0327175 0.0283991 155 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_069.v common 6.15 vpr 63.31 MiB 0.05 6876 -1 -1 1 0.03 -1 -1 30508 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64832 32 32 345 287 1 168 98 17 17 289 -1 unnamed_device 24.3 MiB 2.81 851 13373 3762 8362 1249 63.3 MiB 0.13 0.00 3.52575 -122.419 -3.52575 3.52575 0.33 0.000677114 0.00062979 0.0424472 0.0393624 -1 -1 -1 -1 28 2227 24 6.87369e+06 475111 531479. 1839.03 1.49 0.226038 0.195381 24610 126494 -1 1950 20 1530 2375 156947 39894 3.06826 3.06826 -126.732 -3.06826 0 0 648988. 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65132 30 32 374 297 1 189 97 17 17 289 -1 unnamed_device 24.6 MiB 2.51 1035 12529 3126 8556 847 63.6 MiB 0.13 0.00 3.62905 -119.689 -3.62905 3.62905 0.33 0.000721992 0.00066963 0.0429819 0.0398325 -1 -1 -1 -1 26 2897 29 6.87369e+06 489084 503264. 1741.40 1.60 0.206091 0.178504 24322 120374 -1 2445 19 1503 2481 179127 44386 3.19986 3.19986 -127.798 -3.19986 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.02689 0.0233994 144 60 60 30 57 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_072.v common 4.10 vpr 63.40 MiB 0.05 7120 -1 -1 1 0.03 -1 -1 30368 -1 -1 35 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 28 32 332 260 1 180 95 17 17 289 -1 unnamed_device 24.4 MiB 1.43 952 17807 6266 8549 2992 63.4 MiB 0.17 0.00 4.2699 -127.29 -4.2699 4.2699 0.33 0.000662328 0.000615428 0.0567935 0.0527895 -1 -1 -1 -1 28 2387 24 6.87369e+06 489084 531479. 1839.03 0.78 0.138312 0.122399 24610 126494 -1 2002 19 1529 2511 177079 42805 3.6088 3.6088 -128.236 -3.6088 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0248427 0.0215994 139 34 84 28 28 28 + fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 4.96 vpr 63.31 MiB 0.05 6904 -1 -1 1 0.03 -1 -1 30216 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64832 30 32 325 273 1 161 81 17 17 289 -1 unnamed_device 24.1 MiB 2.52 898 13556 4057 8084 1415 63.3 MiB 0.13 0.00 3.50375 -117.529 -3.50375 3.50375 0.33 0.000649845 0.000604665 0.0520676 0.0484313 -1 -1 -1 -1 32 2221 20 6.87369e+06 265503 586450. 2029.24 0.57 0.12622 0.111731 25474 144626 -1 1795 21 1299 2260 159091 36914 2.82066 2.82066 -114.863 -2.82066 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0259517 0.0224026 110 63 30 30 60 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 5.86 vpr 63.38 MiB 0.05 6912 -1 -1 1 0.03 -1 -1 30336 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 32 32 361 308 1 163 82 17 17 289 -1 unnamed_device 24.1 MiB 3.19 824 8804 2201 5514 1089 63.4 MiB 0.10 0.00 3.47695 -115.33 -3.47695 3.47695 0.35 0.000696267 0.000647352 0.0366908 0.0341135 -1 -1 -1 -1 32 2099 23 6.87369e+06 251529 586450. 2029.24 0.78 0.143621 0.124944 25474 144626 -1 1776 19 1093 1793 115987 28998 2.75366 2.75366 -112.872 -2.75366 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65564 32 32 407 319 1 202 103 17 17 289 -1 unnamed_device 24.2 MiB 3.76 1231 19383 5317 12294 1772 64.0 MiB 0.19 0.00 4.22285 -147.062 -4.22285 4.22285 0.33 0.000778242 0.000721253 0.0651145 0.0602538 -1 -1 -1 -1 32 3199 26 6.87369e+06 544980 586450. 2029.24 1.79 0.297577 0.258264 25474 144626 -1 2441 20 1822 3196 212930 49914 3.6718 3.6718 -147.592 -3.6718 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0294434 0.0255651 156 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 9.80 vpr 64.23 MiB 0.05 7144 -1 -1 1 0.03 -1 -1 30392 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65776 32 32 407 319 1 202 102 17 17 289 -1 unnamed_device 24.7 MiB 3.75 944 19618 5376 10136 4106 64.2 MiB 0.17 0.00 4.27923 -143.211 -4.27923 4.27923 0.33 0.000774509 0.0007197 0.0666149 0.0617933 -1 -1 -1 -1 38 3009 25 6.87369e+06 531006 678818. 2348.85 4.02 0.314785 0.273663 26626 170182 -1 2070 27 1946 3321 223670 64347 4.2823 4.2823 -145.755 -4.2823 0 0 902133. 3121.57 0.03 0.10 0.13 -1 -1 0.03 0.0374599 0.0324198 155 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_078.v common 7.72 vpr 63.89 MiB 0.05 7072 -1 -1 1 0.03 -1 -1 30584 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65428 32 32 399 315 1 198 103 17 17 289 -1 unnamed_device 24.1 MiB 2.62 1101 18901 5395 10733 2773 63.9 MiB 0.21 0.00 4.21489 -141.08 -4.21489 4.21489 0.34 0.000756944 0.000702815 0.0701323 0.0650259 -1 -1 -1 -1 28 3533 26 6.87369e+06 544980 531479. 1839.03 3.09 0.290448 0.252681 24610 126494 -1 2557 21 1759 3006 236786 55479 3.9567 3.9567 -147.253 -3.9567 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0301146 0.0261642 152 65 60 30 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 4.51 vpr 63.10 MiB 0.05 6936 -1 -1 1 0.03 -1 -1 30356 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64612 30 32 296 244 1 160 81 17 17 289 -1 unnamed_device 24.0 MiB 2.16 811 8131 2113 5235 783 63.1 MiB 0.09 0.00 3.50375 -115.041 -3.50375 3.50375 0.33 0.000615393 0.000572913 0.0305644 0.028444 -1 -1 -1 -1 32 2043 19 6.87369e+06 265503 586450. 2029.24 0.57 0.100501 0.0881055 25474 144626 -1 1701 21 1175 1973 126862 31034 2.96496 2.96496 -117.093 -2.96496 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0246417 0.0213432 110 34 60 30 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 6.26 vpr 63.30 MiB 0.05 7148 -1 -1 1 0.03 -1 -1 30376 -1 -1 24 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64824 30 32 383 303 1 192 86 17 17 289 -1 unnamed_device 24.2 MiB 3.02 998 9536 2273 6581 682 63.3 MiB 0.11 0.00 4.25789 -139.005 -4.25789 4.25789 0.33 0.00074191 0.000689601 0.0393657 0.036587 -1 -1 -1 -1 30 2333 22 6.87369e+06 335372 556674. 1926.21 1.39 0.205752 0.178308 25186 138497 -1 1885 21 1596 2515 141236 34135 3.5228 3.5228 -133.425 -3.5228 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0291919 0.0253499 140 63 60 30 60 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 7.45 vpr 64.23 MiB 0.05 7276 -1 -1 1 0.03 -1 -1 30852 -1 -1 43 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65776 32 32 469 381 1 202 107 17 17 289 -1 unnamed_device 24.5 MiB 4.70 1135 19588 6002 11154 2432 64.2 MiB 0.20 0.00 4.29189 -148.036 -4.29189 4.29189 0.33 0.000855811 0.000795502 0.0686583 0.0637435 -1 -1 -1 -1 32 2822 34 6.87369e+06 600875 586450. 2029.24 0.73 0.182253 0.160272 25474 144626 -1 2236 22 1970 3411 223133 54425 3.6088 3.6088 -140.997 -3.6088 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0345331 0.029776 158 127 0 0 128 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 4.92 vpr 64.15 MiB 0.05 7216 -1 -1 1 0.03 -1 -1 30460 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65688 31 32 425 341 1 197 98 17 17 289 -1 unnamed_device 24.6 MiB 1.21 1141 19448 6231 10726 2491 64.1 MiB 0.20 0.00 4.30289 -146.351 -4.30289 4.30289 0.33 0.000781644 0.000725131 0.0711285 0.0659157 -1 -1 -1 -1 32 2686 23 6.87369e+06 489084 586450. 2029.24 1.71 0.299615 0.260246 25474 144626 -1 2052 23 1877 3089 196870 47667 3.5338 3.5338 -136.163 -3.5338 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0337744 0.0293123 150 94 31 31 93 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_083.v common 5.70 vpr 63.40 MiB 0.05 7272 -1 -1 1 0.03 -1 -1 30480 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64924 30 32 404 328 1 188 96 17 17 289 -1 unnamed_device 24.2 MiB 2.01 1065 18054 5358 10040 2656 63.4 MiB 0.18 0.00 3.59605 -119.759 -3.59605 3.59605 0.33 0.00081945 0.000766068 0.0646998 0.0600821 -1 -1 -1 -1 28 2564 22 6.87369e+06 475111 531479. 1839.03 1.77 0.270153 0.234929 24610 126494 -1 2063 19 1593 2688 167070 41776 3.09326 3.09326 -120.307 -3.09326 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.028226 0.0245706 142 92 26 26 90 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 8.39 vpr 63.37 MiB 0.05 7016 -1 -1 1 0.03 -1 -1 30532 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64892 32 32 407 319 1 202 87 17 17 289 -1 unnamed_device 24.2 MiB 4.63 949 16407 6991 7912 1504 63.4 MiB 0.16 0.00 4.2354 -145.24 -4.2354 4.2354 0.33 0.000772793 0.000717614 0.068577 0.063707 -1 -1 -1 -1 34 3451 45 6.87369e+06 321398 618332. 2139.56 1.82 0.246696 0.215458 25762 151098 -1 2227 24 2270 3978 255976 66268 4.3046 4.3046 -154.958 -4.3046 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0339345 0.0293887 147 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 4.41 vpr 63.30 MiB 0.02 7256 -1 -1 1 0.03 -1 -1 30404 -1 -1 36 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 29 32 387 316 1 181 97 17 17 289 -1 unnamed_device 24.2 MiB 1.95 1023 13861 3933 8688 1240 63.3 MiB 0.14 0.00 3.54105 -111.845 -3.54105 3.54105 0.33 0.000741536 0.000681895 0.0479005 0.0443245 -1 -1 -1 -1 26 2429 23 6.87369e+06 503058 503264. 1741.40 0.61 0.134169 0.117894 24322 120374 -1 2203 20 1527 2550 176515 42383 3.15456 3.15456 -118.618 -3.15456 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0281841 0.0244437 138 88 26 26 85 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 3.46 vpr 63.24 MiB 0.04 6860 -1 -1 1 0.03 -1 -1 30432 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 32 32 283 225 1 168 82 17 17 289 -1 unnamed_device 24.1 MiB 0.94 998 12542 3592 7114 1836 63.2 MiB 0.12 0.00 3.53195 -129.235 -3.53195 3.53195 0.33 0.00061261 0.000570281 0.045175 0.0420068 -1 -1 -1 -1 32 2144 29 6.87369e+06 251529 586450. 2029.24 0.80 0.145624 0.127554 25474 144626 -1 1833 21 1429 2173 145252 34704 2.83966 2.83966 -125.078 -2.83966 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.024812 0.0215335 114 3 96 32 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_087.v common 7.24 vpr 63.44 MiB 0.05 7148 -1 -1 1 0.03 -1 -1 30560 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64960 32 32 407 319 1 202 102 17 17 289 -1 unnamed_device 24.5 MiB 4.63 1144 20094 6405 10924 2765 63.4 MiB 0.20 0.00 4.3249 -149.538 -4.3249 4.3249 0.33 0.000774111 0.000719268 0.0678336 0.0628953 -1 -1 -1 -1 32 2698 22 6.87369e+06 531006 586450. 2029.24 0.65 0.159596 0.14127 25474 144626 -1 2153 21 1807 2822 188316 44685 3.7701 3.7701 -144.194 -3.7701 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0307341 0.026714 155 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_088.v common 8.13 vpr 64.19 MiB 0.04 7160 -1 -1 1 0.03 -1 -1 30364 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65732 32 32 407 319 1 202 87 17 17 289 -1 unnamed_device 24.4 MiB 4.07 922 15639 5289 7574 2776 64.2 MiB 0.17 0.00 4.25669 -145.061 -4.25669 4.25669 0.33 0.000769819 0.000714718 0.0652538 0.060608 -1 -1 -1 -1 36 2458 23 6.87369e+06 321398 648988. 2245.63 2.05 0.288458 0.250238 26050 158493 -1 1854 23 1816 2924 196456 49015 3.9064 3.9064 -141.863 -3.9064 0 0 828058. 2865.25 0.03 0.09 0.13 -1 -1 0.03 0.0334663 0.0289911 147 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_089.v common 6.80 vpr 63.20 MiB 0.04 7088 -1 -1 1 0.03 -1 -1 30388 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64716 32 32 315 267 1 158 95 17 17 289 -1 unnamed_device 24.0 MiB 3.39 889 10031 2536 7112 383 63.2 MiB 0.10 0.00 3.48439 -117.289 -3.48439 3.48439 0.33 0.000640293 0.000593722 0.0322523 0.0298511 -1 -1 -1 -1 26 2494 50 6.87369e+06 433189 503264. 1741.40 1.64 0.200857 0.173039 24322 120374 -1 1966 20 1201 2057 156416 39138 3.11686 3.11686 -121.082 -3.11686 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64808 32 32 381 303 1 194 99 17 17 289 -1 unnamed_device 24.3 MiB 2.81 1004 18339 5620 10081 2638 63.3 MiB 0.18 0.00 4.21143 -138.827 -4.21143 4.21143 0.33 0.000741737 0.00068996 0.062068 0.0576067 -1 -1 -1 -1 32 2426 25 6.87369e+06 489084 586450. 2029.24 1.61 0.282514 0.244981 25474 144626 -1 1959 20 1356 2079 141662 34145 3.5578 3.5578 -130.794 -3.5578 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0282301 0.0245219 144 59 60 32 58 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_092.v common 4.76 vpr 63.29 MiB 0.05 7228 -1 -1 1 0.03 -1 -1 30304 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64812 32 32 406 330 1 191 98 17 17 289 -1 unnamed_device 24.1 MiB 1.15 1050 12248 3256 7931 1061 63.3 MiB 0.14 0.00 4.15685 -135.946 -4.15685 4.15685 0.33 0.000763552 0.000709219 0.0441766 0.0409039 -1 -1 -1 -1 32 2666 23 6.87369e+06 475111 586450. 2029.24 1.72 0.268884 0.23177 25474 144626 -1 2174 20 1394 2281 155652 37795 3.62136 3.62136 -135.059 -3.62136 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0292805 0.0254453 142 88 28 28 88 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_093.v common 5.17 vpr 63.54 MiB 0.05 7224 -1 -1 1 0.03 -1 -1 30512 -1 -1 40 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 32 32 399 285 1 232 104 17 17 289 -1 unnamed_device 24.5 MiB 1.03 1271 9620 2298 6733 589 63.5 MiB 0.12 0.00 4.95294 -165.009 -4.95294 4.95294 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42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66068 32 32 493 378 1 233 106 17 17 289 -1 unnamed_device 24.9 MiB 2.49 1329 20856 6846 10957 3053 64.5 MiB 0.25 0.00 4.2988 -145.63 -4.2988 4.2988 0.33 0.000908484 0.000841446 0.0786036 0.0727899 -1 -1 -1 -1 34 3745 25 6.87369e+06 586901 618332. 2139.56 3.37 0.35274 0.305335 25762 151098 -1 2842 22 2418 4406 318963 74864 3.8867 3.8867 -144.829 -3.8867 0 0 787024. 2723.27 0.03 0.11 0.12 -1 -1 0.03 0.0371682 0.0321277 184 95 62 31 95 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_097.v common 6.50 vpr 63.67 MiB 0.05 7332 -1 -1 1 0.03 -1 -1 30600 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65196 31 32 455 371 1 198 86 17 17 289 -1 unnamed_device 24.6 MiB 3.72 969 10292 2693 6968 631 63.7 MiB 0.13 0.00 5.04825 -153.046 -5.04825 5.04825 0.33 0.000827217 0.000769784 0.0476629 0.0443182 -1 -1 -1 -1 32 2736 33 6.87369e+06 321398 586450. 2029.24 0.87 0.187222 0.162903 25474 144626 -1 2049 21 1361 2091 140337 35584 4.10255 4.10255 -146.565 -4.10255 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0331857 0.0287172 144 124 0 0 124 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_098.v common 6.54 vpr 63.22 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30384 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64740 32 32 355 304 1 161 82 17 17 289 -1 unnamed_device 24.0 MiB 3.38 829 11474 3124 7170 1180 63.2 MiB 0.12 0.00 3.7386 -117.206 -3.7386 3.7386 0.33 0.000685433 0.000636355 0.0463019 0.0430183 -1 -1 -1 -1 28 2287 21 6.87369e+06 251529 531479. 1839.03 1.33 0.220296 0.190693 24610 126494 -1 1926 19 1177 1801 142449 34364 2.91816 2.91816 -119.998 -2.91816 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0250793 0.0217538 108 89 0 0 89 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_099.v common 4.87 vpr 63.93 MiB 0.04 7076 -1 -1 1 0.03 -1 -1 30512 -1 -1 34 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65468 32 32 364 282 1 196 98 17 17 289 -1 unnamed_device 24.3 MiB 0.95 1139 19448 6515 10263 2670 63.9 MiB 0.19 0.00 4.23385 -144.907 -4.23385 4.23385 0.33 0.000718442 0.000667695 0.0646027 0.0599307 -1 -1 -1 -1 30 2683 24 6.87369e+06 475111 556674. 1926.21 1.99 0.240566 0.209858 25186 138497 -1 2068 18 1240 1851 106675 25903 3.7591 3.7591 -139.692 -3.7591 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64872 30 32 373 297 1 188 99 17 17 289 -1 unnamed_device 24.3 MiB 1.69 1033 18795 5927 9774 3094 63.4 MiB 0.19 0.00 3.58505 -115.362 -3.58505 3.58505 0.33 0.000722756 0.000671595 0.0616 0.0572047 -1 -1 -1 -1 28 2699 26 6.87369e+06 517032 531479. 1839.03 2.10 0.263132 0.2286 24610 126494 -1 2197 25 1835 3179 208579 51177 3.14156 3.14156 -118.269 -3.14156 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0328167 0.0283615 144 61 58 30 58 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_102.v common 6.58 vpr 64.07 MiB 0.04 7100 -1 -1 1 0.03 -1 -1 30484 -1 -1 46 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65604 32 32 407 319 1 202 110 17 17 289 -1 unnamed_device 24.5 MiB 2.48 1104 21939 6697 12218 3024 64.1 MiB 0.21 0.00 4.26989 -146.214 -4.26989 4.26989 0.33 0.000780945 0.000725395 0.0672548 0.0623564 -1 -1 -1 -1 28 3104 28 6.87369e+06 642796 531479. 1839.03 2.18 0.277559 0.241293 24610 126494 -1 2421 21 2056 3450 244961 58711 4.14 4.14 -149.625 -4.14 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0310418 0.0269398 160 65 64 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 5.36 vpr 63.46 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30516 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64984 32 32 405 318 1 201 106 17 17 289 -1 unnamed_device 24.5 MiB 2.78 1162 18856 5235 12009 1612 63.5 MiB 0.18 0.00 3.52575 -124.656 -3.52575 3.52575 0.33 0.000775346 0.000718795 0.0604867 0.0560114 -1 -1 -1 -1 28 2666 30 6.87369e+06 586901 531479. 1839.03 0.64 0.159673 0.140781 24610 126494 -1 2294 21 1638 2584 168506 39834 3.04356 3.04356 -125.841 -3.04356 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0306125 0.0265386 157 65 63 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 4.13 vpr 63.04 MiB 0.04 7080 -1 -1 1 0.03 -1 -1 30480 -1 -1 20 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 29 32 287 238 1 155 81 17 17 289 -1 unnamed_device 24.0 MiB 1.54 803 12331 3349 7158 1824 63.0 MiB 0.11 0.00 3.53195 -114.094 -3.53195 3.53195 0.33 0.000594501 0.000553827 0.043937 0.0409176 -1 -1 -1 -1 32 1796 25 6.87369e+06 279477 586450. 2029.24 0.75 0.134583 0.118008 25474 144626 -1 1473 20 1118 1664 106970 25049 2.85686 2.85686 -113.062 -2.85686 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0234324 0.0202674 107 34 58 29 29 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 4.94 vpr 63.16 MiB 0.05 7012 -1 -1 1 0.03 -1 -1 30156 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 32 32 334 290 1 154 81 17 17 289 -1 unnamed_device 23.9 MiB 2.39 889 8831 2178 6177 476 63.2 MiB 0.09 0.00 3.7565 -114.859 -3.7565 3.7565 0.35 0.000651672 0.000605737 0.0348874 0.03242 -1 -1 -1 -1 32 1843 20 6.87369e+06 237555 586450. 2029.24 0.75 0.131586 0.114593 25474 144626 -1 1566 21 937 1352 87466 21450 2.92726 2.92726 -110.063 -2.92726 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0259282 0.0224473 102 82 0 0 82 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 4.31 vpr 63.90 MiB 0.05 7120 -1 -1 1 0.03 -1 -1 30416 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65432 31 32 365 281 1 197 102 17 17 289 -1 unnamed_device 24.2 MiB 1.63 1141 17714 5354 10065 2295 63.9 MiB 0.18 0.00 4.28537 -144.975 -4.28537 4.28537 0.33 0.000731564 0.000672837 0.0560893 0.0519217 -1 -1 -1 -1 26 2765 25 6.87369e+06 544980 503264. 1741.40 0.79 0.15216 0.134256 24322 120374 -1 2394 19 1730 2896 192147 49140 4.132 4.132 -151.551 -4.132 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0270606 0.0235739 152 34 93 31 31 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 6.62 vpr 63.02 MiB 0.04 6984 -1 -1 1 0.03 -1 -1 30376 -1 -1 32 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64536 29 32 297 254 1 148 93 17 17 289 -1 unnamed_device 24.0 MiB 3.08 711 17523 7364 8811 1348 63.0 MiB 0.15 0.00 3.48301 -104.839 -3.48301 3.48301 0.33 0.000678214 0.000625626 0.0515323 0.0476674 -1 -1 -1 -1 32 1844 23 6.87369e+06 447163 586450. 2029.24 1.68 0.233039 0.20087 25474 144626 -1 1430 20 1023 1684 109422 28099 2.93196 2.93196 -102.499 -2.93196 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0229676 0.0198241 108 56 29 29 52 26 + fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 6.96 vpr 63.40 MiB 0.04 6776 -1 -1 1 0.03 -1 -1 30224 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64920 32 32 314 256 1 168 82 17 17 289 -1 unnamed_device 24.2 MiB 3.37 907 12186 5086 6820 280 63.4 MiB 0.12 0.00 3.52575 -126.076 -3.52575 3.52575 0.33 0.000649434 0.000604341 0.0461654 0.0429588 -1 -1 -1 -1 36 2041 25 6.87369e+06 251529 648988. 2245.63 1.85 0.23834 0.205904 26050 158493 -1 1676 22 1442 2340 168113 41738 2.92396 2.92396 -119.414 -2.92396 0 0 828058. 2865.25 0.03 0.04 0.09 -1 -1 0.03 0.0144365 0.0126743 114 34 64 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 5.17 vpr 63.38 MiB 0.05 7156 -1 -1 1 0.03 -1 -1 30364 -1 -1 38 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 31 32 387 307 1 193 101 17 17 289 -1 unnamed_device 24.3 MiB 2.39 1125 17726 4908 10315 2503 63.4 MiB 0.18 0.00 3.65725 -124.867 -3.65725 3.65725 0.33 0.000743512 0.000690673 0.0587036 0.0544582 -1 -1 -1 -1 32 2384 23 6.87369e+06 531006 586450. 2029.24 0.81 0.170519 0.149952 25474 144626 -1 1941 22 1596 2436 147466 35647 3.03726 3.03726 -116.56 -3.03726 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0308456 0.0267553 148 64 58 31 62 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 5.99 vpr 63.04 MiB 0.04 6960 -1 -1 1 0.03 -1 -1 30348 -1 -1 17 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64552 31 32 308 262 1 154 80 17 17 289 -1 unnamed_device 23.9 MiB 2.83 883 8336 2238 5700 398 63.0 MiB 0.09 0.00 3.07332 -106.515 -3.07332 3.07332 0.33 0.000623655 0.000580678 0.0321098 0.0298728 -1 -1 -1 -1 26 2205 20 6.87369e+06 237555 503264. 1741.40 1.36 0.194692 0.167731 24322 120374 -1 1778 19 1124 1815 137522 32680 2.99326 2.99326 -121.385 -2.99326 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0229435 0.0198963 103 55 31 31 53 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 5.14 vpr 63.95 MiB 0.04 7136 -1 -1 1 0.03 -1 -1 30476 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65484 32 32 383 307 1 190 101 17 17 289 -1 unnamed_device 24.3 MiB 2.54 1053 18196 4930 10917 2349 63.9 MiB 0.18 0.00 3.63031 -121.705 -3.63031 3.63031 0.33 0.000734279 0.00068219 0.0594197 0.0550985 -1 -1 -1 -1 30 2320 47 6.87369e+06 517032 556674. 1926.21 0.66 0.172678 0.151644 25186 138497 -1 1771 20 975 1633 82292 21490 2.77866 2.77866 -111.157 -2.77866 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0283294 0.0246798 143 65 52 26 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 6.47 vpr 63.70 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30252 -1 -1 39 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65224 31 32 422 339 1 196 102 17 17 289 -1 unnamed_device 24.7 MiB 3.07 1065 19142 5683 10528 2931 63.7 MiB 0.19 0.00 3.61805 -124.185 -3.61805 3.61805 0.33 0.000785502 0.000728936 0.0658729 0.0610449 -1 -1 -1 -1 30 2186 20 6.87369e+06 544980 556674. 1926.21 1.42 0.244531 0.213169 25186 138497 -1 1793 21 1543 2324 131571 32107 2.86186 2.86186 -116.026 -2.86186 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0312002 0.0270359 151 93 31 31 92 31 + fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 5.73 vpr 63.69 MiB 0.05 7088 -1 -1 1 0.03 -1 -1 30356 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65216 32 32 333 279 1 164 82 17 17 289 -1 unnamed_device 24.0 MiB 2.51 798 7024 1571 5156 297 63.7 MiB 0.09 0.00 3.12352 -109.491 -3.12352 3.12352 0.33 0.000661365 0.000614863 0.028191 0.0262299 -1 -1 -1 -1 30 2322 21 6.87369e+06 251529 556674. 1926.21 1.52 0.1809 0.155834 25186 138497 -1 1705 22 1146 1813 110801 27576 2.85996 2.85996 -114.1 -2.85996 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0273634 0.0236873 110 61 32 32 60 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 5.16 vpr 63.17 MiB 0.05 6996 -1 -1 1 0.03 -1 -1 30108 -1 -1 17 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 32 32 339 283 1 166 81 17 17 289 -1 unnamed_device 24.0 MiB 2.74 790 5856 1196 3825 835 63.2 MiB 0.08 0.00 3.50375 -120.315 -3.50375 3.50375 0.33 0.000668234 0.000621218 0.0244303 0.0227368 -1 -1 -1 -1 32 2209 24 6.87369e+06 237555 586450. 2029.24 0.60 0.105262 0.0916136 25474 144626 -1 1787 20 1278 2173 147014 36806 3.08556 3.08556 -123.57 -3.08556 0 0 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v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 29 32 367 293 1 185 95 17 17 289 -1 unnamed_device 24.2 MiB 2.12 929 7223 1505 5248 470 63.2 MiB 0.09 0.00 3.56305 -112.306 -3.56305 3.56305 0.33 0.000709598 0.00066013 0.0259172 0.0240869 -1 -1 -1 -1 32 2450 25 6.87369e+06 475111 586450. 2029.24 1.67 0.236998 0.203241 25474 144626 -1 1723 20 1187 1934 105365 27235 3.04926 3.04926 -112.724 -3.04926 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.027155 0.0235801 141 62 56 29 58 29 + fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 7.31 vpr 63.66 MiB 0.05 7240 -1 -1 1 0.03 -1 -1 30676 -1 -1 41 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65188 32 32 469 381 1 202 105 17 17 289 -1 unnamed_device 24.5 MiB 4.64 1148 19865 5788 12352 1725 63.7 MiB 0.20 0.00 4.2388 -147.714 -4.2388 4.2388 0.33 0.000862195 0.000800938 0.0716368 0.0664075 -1 -1 -1 -1 32 2766 22 6.87369e+06 572927 586450. 2029.24 0.65 0.17168 0.151682 25474 144626 -1 2252 21 1785 2897 183545 43998 3.6481 3.6481 -141.582 -3.6481 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0333568 0.0287883 157 127 0 0 128 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 4.22 vpr 63.21 MiB 0.04 6808 -1 -1 1 0.03 -1 -1 30440 -1 -1 17 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64728 31 32 259 212 1 155 80 17 17 289 -1 unnamed_device 23.6 MiB 1.00 771 11948 3657 6485 1806 63.2 MiB 0.11 0.00 3.09052 -105.03 -3.09052 3.09052 0.33 0.000573463 0.000534012 0.0415517 0.0387278 -1 -1 -1 -1 32 1807 22 6.87369e+06 237555 586450. 2029.24 1.42 0.185585 0.161711 25474 144626 -1 1538 19 976 1534 98343 24653 2.87716 2.87716 -110.55 -2.87716 0 0 744469. 2576.02 0.03 0.05 0.12 -1 -1 0.03 0.0213093 0.0185046 104 4 85 31 0 0 + fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 4.33 vpr 63.55 MiB 0.05 7168 -1 -1 1 0.03 -1 -1 30412 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65076 32 32 418 338 1 194 101 17 17 289 -1 unnamed_device 24.3 MiB 1.55 1202 17256 4935 10275 2046 63.6 MiB 0.17 0.00 4.21805 -142.394 -4.21805 4.21805 0.33 0.000786939 0.000730724 0.0600142 0.0556031 -1 -1 -1 -1 32 2704 27 6.87369e+06 517032 586450. 2029.24 0.86 0.180988 0.158835 25474 144626 -1 2253 21 1613 2321 167558 38682 3.7331 3.7331 -143.417 -3.7331 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0313769 0.0272202 147 92 28 28 92 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 6.76 vpr 63.42 MiB 0.05 7056 -1 -1 1 0.03 -1 -1 30148 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64944 32 32 376 318 1 168 82 17 17 289 -1 unnamed_device 24.3 MiB 3.97 908 7558 1836 5408 314 63.4 MiB 0.09 0.00 3.59615 -125.953 -3.59615 3.59615 0.33 0.000710981 0.000660498 0.0324529 0.030153 -1 -1 -1 -1 32 2031 27 6.87369e+06 251529 586450. 2029.24 0.95 0.153416 0.13275 25474 144626 -1 1719 22 1362 2002 124828 31033 2.89906 2.89906 -123.708 -2.89906 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0294741 0.025474 114 96 0 0 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 5.27 vpr 63.42 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30400 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64940 32 32 401 316 1 199 103 17 17 289 -1 unnamed_device 24.2 MiB 2.59 1047 20106 6225 10936 2945 63.4 MiB 0.19 0.00 3.57101 -124.74 -3.57101 3.57101 0.33 0.000768123 0.000714366 0.0669362 0.0621563 -1 -1 -1 -1 28 2774 30 6.87369e+06 544980 531479. 1839.03 0.74 0.166014 0.14687 24610 126494 -1 2197 22 1770 2827 191011 48782 3.32186 3.32186 -131.581 -3.32186 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.0318332 0.0276685 154 65 61 32 64 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_122.v common 8.06 vpr 64.39 MiB 0.05 7360 -1 -1 1 0.03 -1 -1 30796 -1 -1 47 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 32 32 500 382 1 236 111 17 17 289 -1 unnamed_device 24.7 MiB 4.16 1334 21391 6019 13210 2162 64.4 MiB 0.24 0.00 5.00794 -170.227 -5.00794 5.00794 0.33 0.000916929 0.000851788 0.0768448 0.0711612 -1 -1 -1 -1 34 3011 24 6.87369e+06 656770 618332. 2139.56 1.78 0.31193 0.271113 25762 151098 -1 2498 24 2178 3771 230476 57119 4.72775 4.72775 -176.408 -4.72775 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0407005 0.0352068 190 96 64 32 96 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_123.v common 5.11 vpr 63.17 MiB 0.04 6908 -1 -1 1 0.03 -1 -1 30152 -1 -1 15 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 30 32 246 229 1 118 77 17 17 289 -1 unnamed_device 23.7 MiB 2.05 600 5130 1094 3499 537 63.2 MiB 0.05 0.00 2.80201 -86.4967 -2.80201 2.80201 0.33 0.000526559 0.000490729 0.0181796 0.0169262 -1 -1 -1 -1 32 1340 20 6.87369e+06 209608 586450. 2029.24 1.33 0.160159 0.136701 25474 144626 -1 1125 17 501 729 39368 10821 1.96972 1.96972 -82.7331 -1.96972 0 0 744469. 2576.02 0.03 0.04 0.12 -1 -1 0.03 0.0179094 0.0155243 72 56 0 0 53 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_124.v common 3.83 vpr 63.54 MiB 0.03 7032 -1 -1 1 0.02 -1 -1 30524 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65068 30 32 296 244 1 158 81 17 17 289 -1 unnamed_device 23.9 MiB 0.88 853 13731 4499 7083 2149 63.5 MiB 0.13 0.00 3.55905 -117.205 -3.55905 3.55905 0.33 0.000619692 0.000576772 0.0502622 0.0467755 -1 -1 -1 -1 30 1784 22 6.87369e+06 265503 556674. 1926.21 1.16 0.207443 0.180195 25186 138497 -1 1505 20 1040 1546 87369 21376 3.00236 3.00236 -117.588 -3.00236 0 0 706193. 2443.58 0.04 0.06 0.11 -1 -1 0.04 0.0256121 0.0224304 109 34 60 30 30 30 + fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 5.41 vpr 63.29 MiB 0.04 6908 -1 -1 1 0.03 -1 -1 30116 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64804 32 32 314 256 1 168 82 17 17 289 -1 unnamed_device 24.1 MiB 1.55 813 13610 4570 6521 2519 63.3 MiB 0.14 0.00 3.54365 -123.01 -3.54365 3.54365 0.33 0.00064556 0.000599784 0.0513418 0.0477432 -1 -1 -1 -1 36 2314 26 6.87369e+06 251529 648988. 2245.63 1.95 0.247455 0.214353 26050 158493 -1 1792 25 1631 2926 208357 54408 3.10126 3.10126 -123.47 -3.10126 0 0 828058. 2865.25 0.03 0.09 0.13 -1 -1 0.03 0.0298074 0.0257994 114 34 64 32 32 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_126.v common 3.81 vpr 63.31 MiB 0.05 6860 -1 -1 1 0.03 -1 -1 30488 -1 -1 37 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 25 32 251 214 1 139 94 17 17 289 -1 unnamed_device 23.7 MiB 0.73 757 15004 4162 8299 2543 63.3 MiB 0.12 0.00 3.44875 -92.5459 -3.44875 3.44875 0.33 0.000535278 0.000498443 0.0393721 0.0365858 -1 -1 -1 -1 26 1811 20 6.87369e+06 517032 503264. 1741.40 1.32 0.175615 0.151497 24322 120374 -1 1614 19 1028 1796 118492 29292 3.05256 3.05256 -97.0385 -3.05256 0 0 618332. 2139.56 0.03 0.06 0.10 -1 -1 0.03 0.0197168 0.0170434 105 34 50 25 25 25 + fixed_k6_frac_ripple_N8_22nm.xml mult_127.v common 6.21 vpr 63.57 MiB 0.02 7224 -1 -1 1 0.03 -1 -1 30508 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65096 32 32 432 346 1 200 86 17 17 289 -1 unnamed_device 24.5 MiB 2.83 1089 15584 5798 8091 1695 63.6 MiB 0.18 0.00 4.16249 -143.194 -4.16249 4.16249 0.33 0.000800668 0.000743979 0.0684708 0.0636369 -1 -1 -1 -1 30 2528 23 6.87369e+06 307425 556674. 1926.21 1.47 0.254511 0.22214 25186 138497 -1 1986 21 1753 3227 174348 43308 3.5888 3.5888 -138.86 -3.5888 0 0 706193. 2443.58 0.03 0.08 0.11 -1 -1 0.03 0.0319715 0.0277482 145 94 32 32 94 32 + fixed_k6_frac_ripple_N8_22nm.xml mult_128.v common 5.21 vpr 63.52 MiB 0.05 7172 -1 -1 1 0.03 -1 -1 30328 -1 -1 40 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65044 31 32 421 339 1 195 103 17 17 289 -1 unnamed_device 24.5 MiB 2.41 1002 13358 3288 9107 963 63.5 MiB 0.14 0.00 3.58505 -119.642 -3.58505 3.58505 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65048 32 32 387 309 1 253 94 17 17 289 -1 unnamed_device 24.4 MiB 1.39 1289 15643 4373 9722 1548 63.5 MiB 0.17 0.00 4.10566 -141.292 -4.10566 4.10566 0.33 0.000900432 0.000831399 0.0574687 0.0533419 -1 -1 -1 -1 26 3438 40 6.89349e+06 422815 503264. 1741.40 1.41 0.235827 0.205113 24322 120374 -1 2791 19 1731 2127 162157 38059 3.871 3.871 -144.587 -3.871 0 0 618332. 2139.56 0.03 0.07 0.10 -1 -1 0.03 0.0272732 0.0237211 163 65 54 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_004.v common 4.66 vpr 63.21 MiB 0.05 6992 -1 -1 1 0.03 -1 -1 30604 -1 -1 27 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64560 31 32 317 242 1 187 98 17 17 289 -1 unnamed_device 23.9 MiB 0.79 1086 16523 4545 9530 2448 63.0 MiB 0.15 0.00 3.3697 -112.289 -3.3697 3.3697 0.33 0.000660774 0.000614032 0.0506958 0.0470607 -1 -1 -1 -1 32 2443 21 6.89349e+06 493284 586450. 2029.24 0.78 0.146505 0.128768 25474 144626 -1 2019 19 1143 1954 114229 28334 2.77861 2.77861 -109.807 -2.77861 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0244802 0.0212692 142 4 115 31 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_009.v common 3.97 vpr 63.07 MiB 0.05 7220 -1 -1 1 0.03 -1 -1 30148 -1 -1 25 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64584 31 32 338 292 1 226 88 17 17 289 -1 unnamed_device 23.8 MiB 1.20 1157 14323 4572 7373 2378 63.1 MiB 0.15 0.00 4.06464 -134.474 -4.06464 4.06464 0.33 0.000664123 0.000617403 0.050763 0.047131 -1 -1 -1 -1 32 3057 29 6.89349e+06 352346 586450. 2029.24 0.90 0.156146 0.136589 25474 144626 -1 2346 20 1487 1827 150561 34363 3.3447 3.3447 -127.373 -3.3447 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0253661 0.0219819 135 85 0 0 84 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_010.v common 4.03 vpr 63.19 MiB 0.04 6788 -1 -1 1 0.03 -1 -1 30372 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 314 256 1 193 85 17 17 289 -1 unnamed_device 24.0 MiB 1.38 1003 14035 4618 7503 1914 63.2 MiB 0.14 0.00 3.73335 -131.185 -3.73335 3.73335 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64912 32 32 386 305 1 240 92 17 17 289 -1 unnamed_device 24.3 MiB 0.93 1321 18515 6156 9982 2377 63.4 MiB 0.20 0.00 4.0839 -143.379 -4.0839 4.0839 0.33 0.000756452 0.000703052 0.0701448 0.065168 -1 -1 -1 -1 32 2882 23 6.89349e+06 394628 586450. 2029.24 1.56 0.263566 0.229932 25474 144626 -1 2320 22 1764 2437 159060 37188 3.04555 3.04555 -129.006 -3.04555 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0307837 0.0266916 158 58 64 32 57 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_014.v common 6.08 vpr 63.27 MiB 0.02 7048 -1 -1 1 0.04 -1 -1 30564 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64792 32 32 407 319 1 264 95 17 17 289 -1 unnamed_device 24.1 MiB 1.67 1515 17807 5526 10110 2171 63.3 MiB 0.20 0.00 5.10149 -174.569 -5.10149 5.10149 0.33 0.000782436 0.000727452 0.066614 0.0618444 -1 -1 -1 -1 30 3629 24 6.89349e+06 436909 556674. 1926.21 2.48 0.289196 0.251456 25186 138497 -1 2863 21 2115 2749 198519 44318 4.32705 4.32705 -170.378 -4.32705 0 0 706193. 2443.58 0.03 0.09 0.16 -1 -1 0.03 0.0317348 0.0276811 174 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_015.v common 3.66 vpr 63.43 MiB 0.04 6956 -1 -1 1 0.03 -1 -1 30732 -1 -1 22 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64952 29 32 272 228 1 171 83 17 17 289 -1 unnamed_device 23.7 MiB 1.08 924 12323 4386 5618 2319 63.4 MiB 0.11 0.00 3.63755 -113.774 -3.63755 3.63755 0.33 0.00058211 0.000541802 0.0417248 0.0388655 -1 -1 -1 -1 34 1905 19 6.89349e+06 310065 618332. 2139.56 0.78 0.15071 0.13128 25762 151098 -1 1729 20 1044 1450 88575 22251 3.04066 3.04066 -110.817 -3.04066 0 0 787024. 2723.27 0.03 0.05 0.12 -1 -1 0.03 0.0223184 0.0193403 109 29 58 29 24 24 + fixed_k6_frac_uripple_N8_22nm.xml mult_016.v common 6.48 vpr 63.55 MiB 0.05 7148 -1 -1 1 0.03 -1 -1 30420 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65072 32 32 401 315 1 256 92 17 17 289 -1 unnamed_device 24.4 MiB 2.55 1531 16859 5081 9680 2098 63.5 MiB 0.19 0.00 4.39629 -154.321 -4.39629 4.39629 0.33 0.000772822 0.000715626 0.0653816 0.0605141 -1 -1 -1 -1 28 3515 23 6.89349e+06 394628 531479. 1839.03 1.93 0.270115 0.235025 24610 126494 -1 3014 19 2269 3616 246411 56974 3.545 3.545 -146.114 -3.545 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64580 32 32 339 284 1 224 89 17 17 289 -1 unnamed_device 24.1 MiB 1.50 1258 13157 3692 8051 1414 63.1 MiB 0.14 0.00 3.60335 -129.041 -3.60335 3.60335 0.33 0.000674635 0.000627831 0.0468074 0.043497 -1 -1 -1 -1 30 2881 25 6.89349e+06 352346 556674. 1926.21 1.70 0.234358 0.203026 25186 138497 -1 2182 17 1104 1497 91335 21903 2.66425 2.66425 -116.788 -2.66425 0 0 706193. 2443.58 0.03 0.06 0.13 -1 -1 0.03 0.0230353 0.0201227 137 65 29 29 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_019.v common 3.68 vpr 63.17 MiB 0.04 6828 -1 -1 1 0.03 -1 -1 30192 -1 -1 18 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 30 32 226 208 1 143 80 17 17 289 -1 unnamed_device 23.7 MiB 0.90 838 11776 3393 6972 1411 63.2 MiB 0.09 0.00 3.10286 -101.836 -3.10286 3.10286 0.33 0.00050415 0.000469789 0.0360115 0.0335082 -1 -1 -1 -1 26 1682 19 6.89349e+06 253689 503264. 1741.40 1.05 0.135675 0.117914 24322 120374 -1 1556 18 769 879 68164 16574 2.31947 2.31947 -97.434 -2.31947 0 0 618332. 2139.56 0.03 0.05 0.10 -1 -1 0.03 0.0180737 0.0156881 80 34 24 24 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_020.v common 4.34 vpr 63.24 MiB 0.05 7008 -1 -1 1 0.03 -1 -1 30472 -1 -1 24 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 31 32 335 280 1 217 87 17 17 289 -1 unnamed_device 24.0 MiB 1.66 1174 11223 2879 7192 1152 63.2 MiB 0.12 0.00 4.32035 -143.77 -4.32035 4.32035 0.33 0.000660483 0.000614364 0.0406654 0.0378133 -1 -1 -1 -1 32 2540 22 6.89349e+06 338252 586450. 2029.24 0.81 0.139364 0.121872 25474 144626 -1 2136 18 1187 1646 106119 25575 3.445 3.445 -138.062 -3.445 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0254304 0.0221108 139 64 31 31 62 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_021.v common 4.32 vpr 63.16 MiB 0.04 6976 -1 -1 1 0.03 -1 -1 30256 -1 -1 42 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 32 32 366 283 1 228 106 17 17 289 -1 unnamed_device 24.1 MiB 1.27 1198 19606 5729 9767 4110 63.2 MiB 0.17 0.00 4.66313 -155.697 -4.66313 4.66313 0.33 0.000727903 0.000675351 0.0597099 0.0552916 -1 -1 -1 -1 32 3108 38 6.89349e+06 591941 586450. 2029.24 1.17 0.210355 0.183773 25474 144626 -1 2180 21 1904 2743 175307 45584 4.05824 4.05824 -148.746 -4.05824 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64420 26 32 198 186 1 129 78 17 17 289 -1 unnamed_device 23.5 MiB 0.74 637 12030 3326 7451 1253 62.9 MiB 0.09 0.00 2.88461 -78.8989 -2.88461 2.88461 0.33 0.000440092 0.000409523 0.0332636 0.0309327 -1 -1 -1 -1 24 1634 41 6.89349e+06 281877 470940. 1629.55 1.11 0.150845 0.130427 24034 113901 -1 1317 22 772 957 74343 18260 2.29195 2.29195 -79.8024 -2.29195 0 0 586450. 2029.24 0.03 0.05 0.09 -1 -1 0.03 0.0186709 0.0161636 76 30 26 26 22 22 + fixed_k6_frac_uripple_N8_22nm.xml mult_024.v common 4.70 vpr 63.17 MiB 0.04 6932 -1 -1 1 0.03 -1 -1 30116 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64688 32 32 333 251 1 196 87 17 17 289 -1 unnamed_device 23.9 MiB 1.16 1167 15063 4427 8897 1739 63.2 MiB 0.16 0.00 4.12784 -142.508 -4.12784 4.12784 0.33 0.000685681 0.000637517 0.0559723 0.0519633 -1 -1 -1 -1 32 2813 22 6.89349e+06 324158 586450. 2029.24 1.64 0.233566 0.203102 25474 144626 -1 2117 19 1337 2275 135687 32011 3.58075 3.58075 -138.09 -3.58075 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0254392 0.0221542 143 3 122 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_025.v common 3.28 vpr 62.93 MiB 0.04 6744 -1 -1 1 0.03 -1 -1 30488 -1 -1 13 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 32 32 199 182 1 122 77 17 17 289 -1 unnamed_device 23.5 MiB 0.48 758 9857 3324 5266 1267 62.9 MiB 0.08 0.00 2.24722 -87.4594 -2.24722 2.24722 0.33 0.0004674 0.000434708 0.0296772 0.0276125 -1 -1 -1 -1 30 1512 19 6.89349e+06 183220 556674. 1926.21 1.08 0.134196 0.116634 25186 138497 -1 1235 17 463 698 44396 10589 1.75616 1.75616 -83.6758 -1.75616 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0160881 0.0140619 72 3 53 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_026.v common 4.17 vpr 63.77 MiB 0.05 7028 -1 -1 1 0.03 -1 -1 30608 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65304 32 32 376 288 1 233 91 17 17 289 -1 unnamed_device 24.2 MiB 1.17 1168 13555 3574 8990 991 63.8 MiB 0.15 0.00 4.73011 -159.818 -4.73011 4.73011 0.33 0.000749456 0.000697181 0.051715 0.0480754 -1 -1 -1 -1 32 3172 41 6.89349e+06 380534 586450. 2029.24 1.08 0.194557 0.17019 25474 144626 -1 2214 20 1861 2669 170127 41472 3.89866 3.89866 -151.991 -3.89866 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0284247 0.0247428 158 34 96 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 4.46 vpr 63.38 MiB 0.05 6980 -1 -1 1 0.03 -1 -1 30132 -1 -1 37 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64896 32 32 337 253 1 198 101 17 17 289 -1 unnamed_device 24.4 MiB 0.78 1124 9031 1841 6476 714 63.4 MiB 0.10 0.00 3.4888 -121.478 -3.4888 3.4888 0.33 0.00069141 0.000643026 0.0288 0.026754 -1 -1 -1 -1 26 2703 32 6.89349e+06 521472 503264. 1741.40 1.83 0.210315 0.181529 24322 120374 -1 2329 25 1648 2587 172707 40900 2.78661 2.78661 -120.803 -2.78661 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0319214 0.0276231 151 3 124 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 5.58 vpr 63.46 MiB 0.05 7156 -1 -1 1 0.03 -1 -1 30596 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64980 32 32 407 319 1 264 94 17 17 289 -1 unnamed_device 24.2 MiB 1.96 1502 17773 5551 9919 2303 63.5 MiB 0.20 0.00 4.64215 -161.497 -4.64215 4.64215 0.33 0.000770465 0.000715798 0.0666924 0.0619586 -1 -1 -1 -1 30 3264 28 6.89349e+06 422815 556674. 1926.21 1.64 0.252643 0.220499 25186 138497 -1 2552 19 2024 2797 142241 36192 3.75146 3.75146 -152.492 -3.75146 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0284633 0.0247982 173 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_029.v common 4.01 vpr 63.67 MiB 0.04 6824 -1 -1 1 0.03 -1 -1 30084 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65200 32 32 294 246 1 188 83 17 17 289 -1 unnamed_device 24.3 MiB 1.36 1108 13403 4630 7095 1678 63.7 MiB 0.14 0.00 3.59005 -129.708 -3.59005 3.59005 0.33 0.000617113 0.000574729 0.0480705 0.044737 -1 -1 -1 -1 32 2442 21 6.89349e+06 267783 586450. 2029.24 0.78 0.140603 0.12352 25474 144626 -1 1997 19 1132 1634 114303 26570 2.74266 2.74266 -122.977 -2.74266 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0228836 0.0198641 116 34 54 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_030.v common 4.79 vpr 63.05 MiB 0.04 6980 -1 -1 1 0.03 -1 -1 30136 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64568 30 32 296 244 1 182 83 17 17 289 -1 unnamed_device 24.0 MiB 1.57 1078 12323 3284 7488 1551 63.1 MiB 0.13 0.00 4.27029 -140.501 -4.27029 4.27029 0.33 0.000623398 0.000580978 0.0441116 0.0410269 -1 -1 -1 -1 30 2160 33 6.89349e+06 295971 556674. 1926.21 1.38 0.194503 0.168642 25186 138497 -1 1847 19 1187 1829 102616 25341 3.3695 3.3695 -127.916 -3.3695 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0229967 0.0200005 120 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_031.v common 4.71 vpr 63.27 MiB 0.05 6880 -1 -1 1 0.03 -1 -1 30212 -1 -1 22 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64792 28 32 278 232 1 173 82 17 17 289 -1 unnamed_device 23.9 MiB 1.38 1003 14500 4764 7501 2235 63.3 MiB 0.14 0.00 4.23389 -129.733 -4.23389 4.23389 0.33 0.000582815 0.000542217 0.0495344 0.046131 -1 -1 -1 -1 32 2137 21 6.89349e+06 310065 586450. 2029.24 1.47 0.19217 0.167087 25474 144626 -1 1818 21 1106 1913 131028 30791 3.36645 3.36645 -121.548 -3.36645 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0235656 0.020402 116 34 56 28 28 28 + fixed_k6_frac_uripple_N8_22nm.xml mult_032.v common 4.02 vpr 63.31 MiB 0.05 6884 -1 -1 1 0.03 -1 -1 30284 -1 -1 19 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64828 32 32 283 225 1 168 83 17 17 289 -1 unnamed_device 23.6 MiB 1.31 995 9983 2978 5831 1174 63.3 MiB 0.11 0.00 3.60535 -128.599 -3.60535 3.60535 0.33 0.000608754 0.000566731 0.0364156 0.0339066 -1 -1 -1 -1 32 2253 45 6.89349e+06 267783 586450. 2029.24 0.90 0.160442 0.139464 25474 144626 -1 1932 18 1291 2131 173660 38323 2.91826 2.91826 -127.221 -2.91826 0 0 744469. 2576.02 0.04 0.08 0.12 -1 -1 0.04 0.0241167 0.0211408 115 3 96 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_033.v common 5.97 vpr 63.01 MiB 0.04 6968 -1 -1 1 0.03 -1 -1 30272 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64524 31 32 303 249 1 191 86 17 17 289 -1 unnamed_device 24.0 MiB 1.20 907 14828 6219 7954 655 63.0 MiB 0.15 0.00 3.98415 -131.57 -3.98415 3.98415 0.33 0.000637205 0.000592814 0.051749 0.0481409 -1 -1 -1 -1 28 3090 42 6.89349e+06 324158 531479. 1839.03 2.92 0.255636 0.221463 24610 126494 -1 2151 19 1466 2137 156655 40733 3.14066 3.14066 -126.902 -3.14066 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0235051 0.0204161 121 34 61 31 31 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_034.v common 4.43 vpr 63.15 MiB 0.05 7072 -1 -1 1 0.03 -1 -1 30212 -1 -1 25 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64664 29 32 312 264 1 201 86 17 17 289 -1 unnamed_device 23.9 MiB 1.17 1104 15773 5239 8417 2117 63.1 MiB 0.15 0.00 3.69355 -116.513 -3.69355 3.69355 0.33 0.000624524 0.000580633 0.0540431 0.0501986 -1 -1 -1 -1 28 2477 23 6.89349e+06 352346 531479. 1839.03 1.41 0.220149 0.191174 24610 126494 -1 2134 17 1208 1592 98897 24521 2.92316 2.92316 -114.783 -2.92316 0 0 648988. 2245.63 0.03 0.06 0.10 -1 -1 0.03 0.0213852 0.0185626 130 61 29 29 57 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_035.v common 4.44 vpr 63.41 MiB 0.05 7212 -1 -1 1 0.03 -1 -1 30452 -1 -1 29 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64932 32 32 423 310 1 254 93 17 17 289 -1 unnamed_device 24.4 MiB 1.48 1413 16263 4557 9710 1996 63.4 MiB 0.19 0.00 4.60705 -160.408 -4.60705 4.60705 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26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64692 32 32 368 284 1 225 90 17 17 289 -1 unnamed_device 24.1 MiB 1.17 1065 11748 3163 7762 823 63.2 MiB 0.14 0.00 3.82 -129.667 -3.82 3.82 0.33 0.000728354 0.000677457 0.0449102 0.0417487 -1 -1 -1 -1 34 2622 24 6.89349e+06 366440 618332. 2139.56 0.98 0.187458 0.163164 25762 151098 -1 2082 19 1560 2262 126074 32981 2.88186 2.88186 -122.428 -2.88186 0 0 787024. 2723.27 0.03 0.07 0.12 -1 -1 0.03 0.0269576 0.0234409 151 34 92 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_059.v common 4.18 vpr 62.98 MiB 0.04 7036 -1 -1 1 0.03 -1 -1 30400 -1 -1 34 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64492 30 32 296 244 1 183 96 17 17 289 -1 unnamed_device 23.9 MiB 0.99 1065 10827 2630 7184 1013 63.0 MiB 0.11 0.00 4.28819 -133.732 -4.28819 4.28819 0.33 0.000620962 0.000574826 0.0325883 0.0302153 -1 -1 -1 -1 26 2530 28 6.89349e+06 479191 503264. 1741.40 1.35 0.182638 0.157298 24322 120374 -1 2242 28 1520 2635 216315 62883 3.7564 3.7564 -135.697 -3.7564 0 0 618332. 2139.56 0.03 0.10 0.10 -1 -1 0.03 0.032201 0.0277818 129 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_060.v common 5.68 vpr 64.02 MiB 0.05 7436 -1 -1 1 0.04 -1 -1 30900 -1 -1 39 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65560 32 32 531 413 1 356 103 17 17 289 -1 unnamed_device 25.0 MiB 2.20 1973 21552 6975 11898 2679 64.0 MiB 0.29 0.00 6.49481 -214.549 -6.49481 6.49481 0.33 0.000956296 0.000887927 0.0879429 0.0816438 -1 -1 -1 -1 32 4754 49 6.89349e+06 549660 586450. 2029.24 1.33 0.302547 0.264497 25474 144626 -1 3626 19 2684 3381 245763 60782 5.74388 5.74388 -209.908 -5.74388 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0354734 0.0308974 230 127 32 32 128 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_061.v common 4.80 vpr 63.18 MiB 0.05 7076 -1 -1 1 0.03 -1 -1 30448 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64700 32 32 376 288 1 225 90 17 17 289 -1 unnamed_device 24.1 MiB 1.09 1228 16974 4785 10461 1728 63.2 MiB 0.18 0.00 4.44639 -155.101 -4.44639 4.44639 0.33 0.000747652 0.000695557 0.0652856 0.0606932 -1 -1 -1 -1 30 2788 24 6.89349e+06 366440 556674. 1926.21 1.59 0.240185 0.210238 25186 138497 -1 2313 21 1772 2460 154590 35823 3.9319 3.9319 -147.023 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0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 32 32 438 320 1 267 95 17 17 289 -1 unnamed_device 24.4 MiB 1.56 1501 17807 4939 10901 1967 63.4 MiB 0.23 0.00 5.46259 -184.464 -5.46259 5.46259 0.33 0.000849969 0.000791236 0.0728097 0.0677385 -1 -1 -1 -1 32 3872 46 6.89349e+06 436909 586450. 2029.24 1.16 0.237545 0.208277 25474 144626 -1 2984 23 2248 3385 241015 56567 5.0328 5.0328 -185.031 -5.0328 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0366065 0.0317044 188 34 128 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_064.v common 3.90 vpr 63.39 MiB 0.04 6936 -1 -1 1 0.03 -1 -1 30248 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64912 32 32 283 225 1 168 82 17 17 289 -1 unnamed_device 23.7 MiB 1.31 894 13610 5225 7262 1123 63.4 MiB 0.13 0.00 3.61335 -129.478 -3.61335 3.61335 0.33 0.000616373 0.00057349 0.0489363 0.0455634 -1 -1 -1 -1 32 2299 22 6.89349e+06 253689 586450. 2029.24 0.80 0.142003 0.124912 25474 144626 -1 1818 19 1402 2342 149181 35719 2.92106 2.92106 -124.168 -2.92106 0 0 744469. 2576.02 0.03 0.04 0.09 -1 -1 0.03 0.0127971 0.011263 114 3 96 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_065.v common 4.25 vpr 62.95 MiB 0.04 6912 -1 -1 1 0.03 -1 -1 30112 -1 -1 22 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64456 30 32 296 244 1 185 84 17 17 289 -1 unnamed_device 23.9 MiB 0.78 983 15090 5268 7800 2022 62.9 MiB 0.14 0.00 3.71935 -122.134 -3.71935 3.71935 0.34 0.00061946 0.000576334 0.0528802 0.0492205 -1 -1 -1 -1 32 2249 38 6.89349e+06 310065 586450. 2029.24 1.53 0.220572 0.19161 25474 144626 -1 1759 21 1240 1711 103616 25757 3.17801 3.17801 -120.108 -3.17801 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0247395 0.0214495 118 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_066.v common 5.14 vpr 63.39 MiB 0.04 7176 -1 -1 1 0.03 -1 -1 30320 -1 -1 33 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 29 32 393 319 1 252 94 17 17 289 -1 unnamed_device 24.2 MiB 1.33 1341 18199 5258 10538 2403 63.4 MiB 0.19 0.00 4.13664 -130.224 -4.13664 4.13664 0.33 0.000738038 0.000685287 0.0654014 0.0607404 -1 -1 -1 -1 28 3301 35 6.89349e+06 465097 531479. 1839.03 1.81 0.277343 0.241104 24610 126494 -1 2504 21 1727 2312 165397 39519 3.4561 3.4561 -128.16 -3.4561 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0298808 0.0259522 168 88 29 29 85 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_067.v common 5.48 vpr 63.34 MiB 0.05 7240 -1 -1 1 0.03 -1 -1 30784 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 32 32 407 319 1 264 95 17 17 289 -1 unnamed_device 24.2 MiB 1.82 1221 12407 3290 7924 1193 63.3 MiB 0.14 0.00 5.16911 -173.806 -5.16911 5.16911 0.33 0.000779363 0.000724302 0.0469731 0.0436453 -1 -1 -1 -1 32 3125 20 6.89349e+06 436909 586450. 2029.24 1.72 0.282038 0.243868 25474 144626 -1 2420 23 2196 3091 179353 44427 4.73405 4.73405 -171.972 -4.73405 0 0 744469. 2576.02 0.03 0.09 0.12 -1 -1 0.03 0.0334452 0.0290599 173 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_068.v common 4.95 vpr 63.94 MiB 0.05 7044 -1 -1 1 0.03 -1 -1 30656 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65476 32 32 407 319 1 264 95 17 17 289 -1 unnamed_device 24.2 MiB 1.80 1231 8951 1983 6660 308 63.9 MiB 0.12 0.00 5.05324 -167.397 -5.05324 5.05324 0.35 0.000775867 0.000720909 0.0346246 0.0321574 -1 -1 -1 -1 34 3282 24 6.89349e+06 436909 618332. 2139.56 1.12 0.191107 0.165711 25762 151098 -1 2448 20 2092 2934 200786 47072 4.79705 4.79705 -174.942 -4.79705 0 0 787024. 2723.27 0.03 0.09 0.12 -1 -1 0.03 0.0299895 0.0261215 175 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_069.v common 4.03 vpr 63.32 MiB 0.04 6980 -1 -1 1 0.03 -1 -1 30524 -1 -1 25 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64840 32 32 345 287 1 220 89 17 17 289 -1 unnamed_device 24.3 MiB 1.22 1016 14741 4173 7811 2757 63.3 MiB 0.15 0.00 4.27829 -143.109 -4.27829 4.27829 0.34 0.000678002 0.000630406 0.0526872 0.0489865 -1 -1 -1 -1 32 2726 35 6.89349e+06 352346 586450. 2029.24 0.83 0.168639 0.147749 25474 144626 -1 1899 20 1232 1423 98620 23951 3.3857 3.3857 -129.596 -3.3857 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0263435 0.0228985 136 65 32 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_070.v common 5.11 vpr 63.30 MiB 0.05 7028 -1 -1 1 0.03 -1 -1 30468 -1 -1 26 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 31 32 353 302 1 231 89 17 17 289 -1 unnamed_device 24.2 MiB 1.47 1227 8999 2014 6221 764 63.3 MiB 0.11 0.00 4.43069 -143.689 -4.43069 4.43069 0.33 0.000689588 0.000641809 0.0330719 0.0307387 -1 -1 -1 -1 28 3099 22 6.89349e+06 366440 531479. 1839.03 1.75 0.220305 0.189725 24610 126494 -1 2588 21 1666 2118 145227 36584 3.9119 3.9119 -140.139 -3.9119 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0274964 0.0238227 142 90 0 0 89 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_071.v common 4.96 vpr 63.36 MiB 0.05 7140 -1 -1 1 0.03 -1 -1 30432 -1 -1 31 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64880 30 32 374 297 1 236 93 17 17 289 -1 unnamed_device 24.3 MiB 1.29 1263 17943 5889 9476 2578 63.4 MiB 0.19 0.00 3.98278 -131.19 -3.98278 3.98278 0.33 0.000719207 0.000668391 0.0640912 0.0594873 -1 -1 -1 -1 26 3455 39 6.89349e+06 436909 503264. 1741.40 1.74 0.275059 0.239402 24322 120374 -1 2762 21 1913 2858 208201 47445 3.41131 3.41131 -134.426 -3.41131 0 0 618332. 2139.56 0.03 0.08 0.10 -1 -1 0.03 0.0291052 0.0252606 161 60 60 30 57 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_072.v common 3.73 vpr 63.24 MiB 0.05 7080 -1 -1 1 0.03 -1 -1 30392 -1 -1 27 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 28 32 332 260 1 203 87 17 17 289 -1 unnamed_device 24.0 MiB 0.99 936 12375 3003 7042 2330 63.2 MiB 0.13 0.00 4.59085 -131.386 -4.59085 4.59085 0.33 0.000669455 0.000622708 0.0462473 0.0431111 -1 -1 -1 -1 32 2579 22 6.89349e+06 380534 586450. 2029.24 0.86 0.145096 0.127288 25474 144626 -1 1932 16 1168 1740 102968 26808 4.35596 4.35596 -134.764 -4.35596 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0216679 0.0189282 142 34 84 28 28 28 + fixed_k6_frac_uripple_N8_22nm.xml mult_073.v common 6.88 vpr 63.06 MiB 0.05 7032 -1 -1 1 0.03 -1 -1 30208 -1 -1 24 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64572 30 32 325 273 1 208 86 17 17 289 -1 unnamed_device 23.8 MiB 1.75 1061 14639 6063 7932 644 63.1 MiB 0.15 0.00 4.67543 -143.963 -4.67543 4.67543 0.33 0.000646754 0.000601523 0.0523043 0.0486486 -1 -1 -1 -1 30 3104 46 6.89349e+06 338252 556674. 1926.21 3.18 0.235055 0.204448 25186 138497 -1 2284 21 1485 2041 154074 36200 3.492 3.492 -132 -3.492 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0259833 0.0225035 131 63 30 30 60 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_074.v common 5.67 vpr 63.28 MiB 0.04 6932 -1 -1 1 0.03 -1 -1 30320 -1 -1 26 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64800 32 32 361 308 1 245 90 17 17 289 -1 unnamed_device 24.2 MiB 1.39 1306 14361 4140 7938 2283 63.3 MiB 0.15 0.00 4.25449 -145.014 -4.25449 4.25449 0.33 0.000701879 0.00065219 0.0519651 0.0482643 -1 -1 -1 -1 28 3359 38 6.89349e+06 366440 531479. 1839.03 2.29 0.254873 0.220716 24610 126494 -1 2678 27 1972 2454 207890 58002 3.3777 3.3777 -136.729 -3.3777 0 0 648988. 2245.63 0.03 0.10 0.10 -1 -1 0.03 0.034048 0.029393 144 91 0 0 91 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_075.v common 6.10 vpr 63.39 MiB 0.05 7068 -1 -1 1 0.03 -1 -1 30148 -1 -1 37 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 31 32 335 251 1 197 100 17 17 289 -1 unnamed_device 24.2 MiB 0.88 932 17268 5400 7852 4016 63.4 MiB 0.15 0.00 4.36065 -141.282 -4.36065 4.36065 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64704 32 32 399 315 1 257 93 17 17 289 -1 unnamed_device 24.1 MiB 1.76 1404 17523 6159 8784 2580 63.2 MiB 0.20 0.00 4.56713 -153.013 -4.56713 4.56713 0.33 0.000761838 0.000706965 0.066083 0.0613463 -1 -1 -1 -1 32 3702 24 6.89349e+06 408721 586450. 2029.24 0.94 0.184324 0.162289 25474 144626 -1 2700 21 1764 2529 155980 37292 3.8129 3.8129 -145.514 -3.8129 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0305139 0.0265566 169 65 60 30 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_079.v common 4.25 vpr 63.10 MiB 0.05 6980 -1 -1 1 0.03 -1 -1 30448 -1 -1 21 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64616 30 32 296 244 1 185 83 17 17 289 -1 unnamed_device 24.1 MiB 1.09 999 11963 3206 7400 1357 63.1 MiB 0.12 0.00 4.11194 -131.981 -4.11194 4.11194 0.34 0.000622359 0.000579722 0.0429193 0.039954 -1 -1 -1 -1 30 2219 20 6.89349e+06 295971 556674. 1926.21 1.29 0.194284 0.16852 25186 138497 -1 1868 18 1140 1614 101876 24036 3.12985 3.12985 -120.641 -3.12985 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0221432 0.019271 118 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_080.v common 4.50 vpr 63.24 MiB 0.05 7092 -1 -1 1 0.03 -1 -1 30372 -1 -1 28 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64760 30 32 383 303 1 241 90 17 17 289 -1 unnamed_device 24.1 MiB 1.72 1228 13155 3873 7280 2002 63.2 MiB 0.15 0.00 4.93324 -157.041 -4.93324 4.93324 0.33 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0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0326715 0.0283189 196 127 0 0 128 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_082.v common 5.46 vpr 63.44 MiB 0.02 7272 -1 -1 1 0.03 -1 -1 30772 -1 -1 35 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64964 31 32 425 341 1 280 98 17 17 289 -1 unnamed_device 24.5 MiB 1.69 1433 19898 6263 10776 2859 63.4 MiB 0.21 0.00 5.19789 -171.346 -5.19789 5.19789 0.33 0.00078494 0.000729042 0.0718066 0.0666239 -1 -1 -1 -1 28 3483 21 6.89349e+06 493284 531479. 1839.03 1.93 0.279576 0.243742 24610 126494 -1 2768 19 2123 2590 197715 46849 4.66075 4.66075 -169.956 -4.66075 0 0 648988. 2245.63 0.02 0.05 0.07 -1 -1 0.02 0.0159056 0.0140709 184 94 31 31 93 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 6.21 vpr 63.36 MiB 0.05 7224 -1 -1 1 0.03 -1 -1 30488 -1 -1 33 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64876 30 32 404 328 1 261 95 17 17 289 -1 unnamed_device 24.2 MiB 1.60 1466 16943 5275 9110 2558 63.4 MiB 0.19 0.00 4.58423 -145.605 -4.58423 4.58423 0.34 0.000753953 0.000700732 0.0625049 0.0579699 -1 -1 -1 -1 28 3595 39 6.89349e+06 465097 531479. 1839.03 2.61 0.296221 0.256997 24610 126494 -1 2856 23 2400 3459 235720 55615 3.8522 3.8522 -142.438 -3.8522 0 0 648988. 2245.63 0.03 0.10 0.10 -1 -1 0.03 0.033048 0.0286617 174 92 26 26 90 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_084.v common 5.88 vpr 63.41 MiB 0.05 7072 -1 -1 1 0.03 -1 -1 30592 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 32 32 407 319 1 264 94 17 17 289 -1 unnamed_device 24.3 MiB 1.86 1438 16921 4532 10127 2262 63.4 MiB 0.20 0.00 5.09969 -174.568 -5.09969 5.09969 0.33 0.000769951 0.000714253 0.0638066 0.0591767 -1 -1 -1 -1 26 3901 31 6.89349e+06 422815 503264. 1741.40 2.01 0.263499 0.229188 24322 120374 -1 3079 22 2458 3494 309356 69378 4.58385 4.58385 -176.85 -4.58385 0 0 618332. 2139.56 0.03 0.11 0.10 -1 -1 0.03 0.0326723 0.0283961 174 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 5.01 vpr 63.24 MiB 0.05 7284 -1 -1 1 0.03 -1 -1 30360 -1 -1 34 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64756 29 32 387 316 1 251 95 17 17 289 -1 unnamed_device 24.1 MiB 1.48 1300 13919 3823 7524 2572 63.2 MiB 0.15 0.00 4.50731 -134.302 -4.50731 4.50731 0.34 0.000837393 0.000785725 0.0499097 0.0463459 -1 -1 -1 -1 28 3058 30 6.89349e+06 479191 531479. 1839.03 1.59 0.25121 0.217412 24610 126494 -1 2557 19 1761 2383 146907 36045 3.9319 3.9319 -131.067 -3.9319 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0276474 0.0240476 169 88 26 26 85 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 3.46 vpr 63.39 MiB 0.02 6852 -1 -1 1 0.03 -1 -1 30232 -1 -1 18 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64908 32 32 283 225 1 168 82 17 17 289 -1 unnamed_device 23.7 MiB 0.79 953 15034 4497 9060 1477 63.4 MiB 0.15 0.00 3.60415 -127.643 -3.60415 3.60415 0.33 0.000610265 0.000567997 0.0533095 0.049604 -1 -1 -1 -1 32 2236 44 6.89349e+06 253689 586450. 2029.24 0.89 0.181995 0.158961 25474 144626 -1 1894 20 1208 1986 122611 29252 2.96316 2.96316 -124.924 -2.96316 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0237067 0.020599 114 3 96 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_087.v common 4.83 vpr 63.48 MiB 0.05 7052 -1 -1 1 0.03 -1 -1 30336 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65008 32 32 407 319 1 259 94 17 17 289 -1 unnamed_device 24.3 MiB 1.63 1301 16069 5243 8056 2770 63.5 MiB 0.18 0.00 5.15687 -172.128 -5.15687 5.15687 0.33 0.000791386 0.000735263 0.0613103 0.0569259 -1 -1 -1 -1 34 3362 22 6.89349e+06 422815 618332. 2139.56 1.15 0.219914 0.1925 25762 151098 -1 2671 23 2330 3274 223930 53683 4.50619 4.50619 -169.447 -4.50619 0 0 787024. 2723.27 0.03 0.10 0.12 -1 -1 0.03 0.0341173 0.0296211 172 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_088.v common 5.11 vpr 63.35 MiB 0.05 7044 -1 -1 1 0.03 -1 -1 30520 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64868 32 32 407 319 1 263 94 17 17 289 -1 unnamed_device 24.2 MiB 2.20 1383 17134 5303 9222 2609 63.3 MiB 0.19 0.00 5.10782 -172.27 -5.10782 5.10782 0.33 0.000773712 0.000717737 0.0647863 0.0601172 -1 -1 -1 -1 32 3271 22 6.89349e+06 422815 586450. 2029.24 0.89 0.182116 0.160392 25474 144626 -1 2692 19 2085 2832 175192 41819 4.52939 4.52939 -167.419 -4.52939 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0285049 0.0248437 172 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_089.v common 4.92 vpr 63.04 MiB 0.05 6948 -1 -1 1 0.03 -1 -1 30472 -1 -1 24 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64548 32 32 315 267 1 204 88 17 17 289 -1 unnamed_device 23.9 MiB 1.05 986 9838 2323 6939 576 63.0 MiB 0.10 0.00 3.75491 -121.625 -3.75491 3.75491 0.33 0.000649994 0.000603938 0.0340968 0.0316787 -1 -1 -1 -1 28 2822 25 6.89349e+06 338252 531479. 1839.03 1.99 0.224225 0.192873 24610 126494 -1 2192 21 1376 1671 132502 32852 3.01905 3.01905 -120.319 -3.01905 0 0 648988. 2245.63 0.03 0.07 0.10 -1 -1 0.03 0.0258106 0.0223522 124 55 32 32 54 27 + fixed_k6_frac_uripple_N8_22nm.xml mult_090.v common 4.47 vpr 63.21 MiB 0.05 6924 -1 -1 1 0.03 -1 -1 30396 -1 -1 18 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64724 31 32 275 220 1 164 81 17 17 289 -1 unnamed_device 23.6 MiB 1.07 803 9881 3191 5068 1622 63.2 MiB 0.09 0.00 3.59935 -120.624 -3.59935 3.59935 0.33 0.000605233 0.000564063 0.0355859 0.033138 -1 -1 -1 -1 32 2124 35 6.89349e+06 253689 586450. 2029.24 1.56 0.21792 0.187665 25474 144626 -1 1628 20 1203 1831 121960 30492 3.23576 3.23576 -119.48 -3.23576 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0233256 0.0202238 112 4 93 31 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_091.v common 4.85 vpr 63.33 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30312 -1 -1 28 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64852 32 32 381 303 1 240 92 17 17 289 -1 unnamed_device 24.2 MiB 1.15 1231 13754 4153 8203 1398 63.3 MiB 0.15 0.00 4.56339 -148.311 -4.56339 4.56339 0.33 0.000740831 0.0006887 0.0515433 0.0478362 -1 -1 -1 -1 28 3040 24 6.89349e+06 394628 531479. 1839.03 1.72 0.275416 0.238331 24610 126494 -1 2614 23 1820 2296 164135 40448 4.0873 4.0873 -145.854 -4.0873 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64916 32 32 399 285 1 232 104 17 17 289 -1 unnamed_device 24.2 MiB 0.88 1512 14012 4050 8858 1104 63.4 MiB 0.18 0.00 4.95818 -166.989 -4.95818 4.95818 0.33 0.000796918 0.000738904 0.0477977 0.0443417 -1 -1 -1 -1 32 3643 28 6.89349e+06 563754 586450. 2029.24 1.15 0.199029 0.173637 25474 144626 -1 2795 21 2045 3563 248050 55674 4.52739 4.52739 -164.832 -4.52739 0 0 744469. 2576.02 0.03 0.06 0.08 -1 -1 0.03 0.0174675 0.0154246 183 3 156 32 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_094.v common 5.04 vpr 63.23 MiB 0.05 7136 -1 -1 1 0.03 -1 -1 30472 -1 -1 30 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 32 32 355 304 1 244 89 17 17 289 -1 unnamed_device 24.2 MiB 1.43 1277 9989 2458 6925 606 63.3 MiB 0.11 0.00 4.48385 -143.454 -4.48385 4.48385 0.34 0.000690008 0.000638492 0.0376752 0.0348434 -1 -1 -1 -1 30 2753 21 6.89349e+06 352346 556674. 1926.21 1.44 0.19703 0.170514 25186 138497 -1 2325 18 1389 1653 105535 25688 3.503 3.503 -135.401 -3.503 0 0 706193. 2443.58 0.03 0.06 0.11 -1 -1 0.03 0.0246385 0.0214264 142 89 0 0 89 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_099.v common 5.60 vpr 63.30 MiB 0.04 7060 -1 -1 1 0.03 -1 -1 30340 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca 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/home/elgamma8/research/release/vtr-verilog-to-routing 64932 29 32 287 238 1 178 84 17 17 289 -1 unnamed_device 24.0 MiB 0.92 753 14907 5576 6751 2580 63.4 MiB 0.13 0.00 3.831 -117.329 -3.831 3.831 0.33 0.00060551 0.000563981 0.0513937 0.0478521 -1 -1 -1 -1 32 2165 25 6.89349e+06 324158 586450. 2029.24 0.84 0.151921 0.133256 25474 144626 -1 1559 20 1409 1830 122009 30591 3.06071 3.06071 -112.057 -3.06071 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0231868 0.0200793 115 34 58 29 29 29 + fixed_k6_frac_uripple_N8_22nm.xml mult_105.v common 5.52 vpr 63.20 MiB 0.04 6912 -1 -1 1 0.03 -1 -1 30248 -1 -1 23 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64712 32 32 334 290 1 222 87 17 17 289 -1 unnamed_device 24.0 MiB 1.22 1101 13911 5707 7810 394 63.2 MiB 0.15 0.00 4.70868 -138.961 -4.70868 4.70868 0.33 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64644 32 32 314 256 1 194 85 17 17 289 -1 unnamed_device 23.9 MiB 1.53 1169 12733 4095 6614 2024 63.1 MiB 0.13 0.00 3.8782 -135.142 -3.8782 3.8782 0.34 0.000657222 0.000612326 0.0469677 0.0437456 -1 -1 -1 -1 28 2823 24 6.89349e+06 295971 531479. 1839.03 1.85 0.231118 0.200661 24610 126494 -1 2360 20 1668 2279 200006 44131 3.38931 3.38931 -137.549 -3.38931 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0249365 0.0215969 123 34 64 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 5.67 vpr 63.39 MiB 0.05 7108 -1 -1 1 0.03 -1 -1 30416 -1 -1 29 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64912 31 32 387 307 1 244 92 17 17 289 -1 unnamed_device 24.2 MiB 1.75 1268 16652 5558 8745 2349 63.4 MiB 0.18 0.00 4.36484 -143.839 -4.36484 4.36484 0.33 0.000745649 0.000692421 0.0626172 0.0581734 -1 -1 -1 -1 28 3192 22 6.89349e+06 408721 531479. 1839.03 1.94 0.270943 0.235581 24610 126494 -1 2762 21 2177 2939 216914 52041 3.78855 3.78855 -145.228 -3.78855 0 0 648988. 2245.63 0.03 0.09 0.10 -1 -1 0.03 0.030277 0.0263235 163 64 58 31 62 31 + fixed_k6_frac_uripple_N8_22nm.xml mult_110.v common 3.71 vpr 63.01 MiB 0.05 6956 -1 -1 1 0.03 -1 -1 30348 -1 -1 23 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64524 31 32 308 262 1 197 86 17 17 289 -1 unnamed_device 23.9 MiB 1.12 1033 8024 1908 5498 618 63.0 MiB 0.09 0.00 3.26322 -110.856 -3.26322 3.26322 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0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64532 32 32 333 279 1 216 87 17 17 289 -1 unnamed_device 23.8 MiB 2.09 1217 9879 2720 6405 754 63.0 MiB 0.11 0.00 3.54325 -124.984 -3.54325 3.54325 0.33 0.000660706 0.000614519 0.0362522 0.0337014 -1 -1 -1 -1 30 2687 20 6.89349e+06 324158 556674. 1926.21 1.36 0.188275 0.162908 25186 138497 -1 2129 16 1092 1526 86472 21544 2.8315 2.8315 -116.981 -2.8315 0 0 706193. 2443.58 0.03 0.05 0.11 -1 -1 0.03 0.0217635 0.0189492 133 61 32 32 60 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 4.83 vpr 63.34 MiB 0.04 6896 -1 -1 1 0.03 -1 -1 30120 -1 -1 22 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64856 32 32 339 283 1 218 86 17 17 289 -1 unnamed_device 24.3 MiB 0.86 980 8591 2112 5922 557 63.3 MiB 0.11 0.00 3.8741 -128.661 -3.8741 3.8741 0.33 0.000673254 0.00062665 0.0326141 0.0303366 -1 -1 -1 -1 28 3027 43 6.89349e+06 310065 531479. 1839.03 2.11 0.240563 0.206551 24610 126494 -1 2382 22 1731 2107 166869 42558 3.37841 3.37841 -133.561 -3.37841 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0279856 0.0242131 132 63 32 32 62 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_115.v common 5.50 vpr 63.46 MiB 0.05 7048 -1 -1 1 0.03 -1 -1 30848 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64988 32 32 407 319 1 264 94 17 17 289 -1 unnamed_device 24.3 MiB 1.25 1282 15643 3802 10271 1570 63.5 MiB 0.19 0.00 4.6143 -156.82 -4.6143 4.6143 0.33 0.000778574 0.00072427 0.058865 0.0547005 -1 -1 -1 -1 30 3171 38 6.89349e+06 422815 556674. 1926.21 2.22 0.25593 0.222346 25186 138497 -1 2462 19 1846 2253 127632 31903 4.11336 4.11336 -155.135 -4.11336 0 0 706193. 2443.58 0.03 0.07 0.11 -1 -1 0.03 0.0282964 0.0246222 170 65 64 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_116.v common 3.71 vpr 63.23 MiB 0.02 7196 -1 -1 1 0.03 -1 -1 30668 -1 -1 29 29 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64744 29 32 367 293 1 233 90 17 17 289 -1 unnamed_device 24.1 MiB 1.17 1203 10542 2870 6902 770 63.2 MiB 0.07 0.00 3.69745 -116.178 -3.69745 3.69745 0.25 0.000317735 0.000292613 0.0181715 0.016705 -1 -1 -1 -1 26 3071 25 6.89349e+06 408721 503264. 1741.40 1.06 0.111552 0.0958251 24322 120374 -1 2431 22 1447 1929 143218 33711 3.6346 3.6346 -123.643 -3.6346 0 0 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64796 31 32 259 212 1 155 80 17 17 289 -1 unnamed_device 23.6 MiB 0.82 745 8336 2043 5166 1127 63.3 MiB 0.09 0.00 2.99217 -101.039 -2.99217 2.99217 0.33 0.000574136 0.000534957 0.0295149 0.0274887 -1 -1 -1 -1 32 1906 32 6.89349e+06 239595 586450. 2029.24 0.58 0.106354 0.0929425 25474 144626 -1 1632 21 1057 1694 108711 26729 2.72261 2.72261 -106.292 -2.72261 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.0230958 0.0199982 104 4 85 31 0 0 + fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 4.92 vpr 63.41 MiB 0.05 7168 -1 -1 1 0.03 -1 -1 30340 -1 -1 31 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64936 32 32 418 338 1 273 95 17 17 289 -1 unnamed_device 24.5 MiB 1.64 1217 9599 2333 5862 1404 63.4 MiB 0.12 0.00 5.60308 -177.161 -5.60308 5.60308 0.33 0.000803468 0.000746944 0.037283 0.0345942 -1 -1 -1 -1 34 3214 39 6.89349e+06 436909 618332. 2139.56 1.29 0.211084 0.182635 25762 151098 -1 2321 20 1852 2491 152053 38190 5.20054 5.20054 -174.876 -5.20054 0 0 787024. 2723.27 0.03 0.08 0.12 -1 -1 0.03 0.0301735 0.0262642 178 92 28 28 92 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 5.59 vpr 63.27 MiB 0.04 7000 -1 -1 1 0.03 -1 -1 30132 -1 -1 27 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64784 32 32 376 318 1 259 91 17 17 289 -1 unnamed_device 24.2 MiB 1.80 1321 16615 4991 9246 2378 63.3 MiB 0.18 0.00 5.02744 -166.554 -5.02744 5.02744 0.33 0.000715759 0.000664942 0.0607316 0.0563724 -1 -1 -1 -1 32 3248 26 6.89349e+06 380534 586450. 2029.24 1.87 0.254283 0.220939 25474 144626 -1 2576 20 1850 2349 165532 38600 4.36539 4.36539 -162.705 -4.36539 0 0 744469. 2576.02 0.03 0.08 0.12 -1 -1 0.03 0.0275449 0.0239539 153 96 0 0 96 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 5.63 vpr 63.23 MiB 0.05 7160 -1 -1 1 0.03 -1 -1 30320 -1 -1 30 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64752 32 32 401 316 1 253 94 17 17 289 -1 unnamed_device 24.1 MiB 1.68 1306 19051 6211 10037 2803 63.2 MiB 0.21 0.00 3.73835 -130.804 -3.73835 3.73835 0.33 0.000763021 0.000709152 0.0711454 0.0660209 -1 -1 -1 -1 28 3343 23 6.89349e+06 422815 531479. 1839.03 1.95 0.281782 0.244986 24610 126494 -1 2689 21 1843 2447 192473 46184 3.1084 3.1084 -130.26 -3.1084 0 0 648988. 2245.63 0.03 0.08 0.10 -1 -1 0.03 0.0311229 0.0270762 168 65 61 32 64 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 4.83 vpr 63.66 MiB 0.05 7360 -1 -1 1 0.03 -1 -1 30772 -1 -1 38 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65192 32 32 500 382 1 322 102 17 17 289 -1 unnamed_device 24.8 MiB 1.53 1462 15096 4398 9006 1692 63.7 MiB 0.19 0.00 5.86158 -190.116 -5.86158 5.86158 0.33 0.000919181 0.000854379 0.061316 0.0569405 -1 -1 -1 -1 32 4699 41 6.89349e+06 535566 586450. 2029.24 1.25 0.266879 0.23192 25474 144626 -1 3190 22 2412 2931 198387 48002 5.40169 5.40169 -188.235 -5.40169 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0382229 0.0331721 214 96 64 32 96 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 3.79 vpr 63.16 MiB 0.04 6768 -1 -1 1 0.03 -1 -1 30240 -1 -1 19 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 30 32 246 229 1 160 81 17 17 289 -1 unnamed_device 23.6 MiB 0.90 892 12856 4155 7039 1662 63.2 MiB 0.10 0.00 3.53735 -105.472 -3.53735 3.53735 0.33 0.000533269 0.000496561 0.040837 0.038018 -1 -1 -1 -1 30 1687 20 6.89349e+06 267783 556674. 1926.21 1.08 0.160413 0.138837 25186 138497 -1 1417 14 544 570 40251 9509 2.31396 2.31396 -91.0321 -2.31396 0 0 706193. 2443.58 0.03 0.04 0.11 -1 -1 0.03 0.0156975 0.0136917 88 56 0 0 53 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 3.92 vpr 62.93 MiB 0.05 7080 -1 -1 1 0.03 -1 -1 30492 -1 -1 23 30 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64444 30 32 296 244 1 181 85 17 17 289 -1 unnamed_device 23.8 MiB 1.29 886 13105 4113 6709 2283 62.9 MiB 0.12 0.00 4.28025 -136.671 -4.28025 4.28025 0.33 0.000613731 0.000571122 0.0450939 0.0419413 -1 -1 -1 -1 32 2067 23 6.89349e+06 324158 586450. 2029.24 0.78 0.137946 0.120725 25474 144626 -1 1700 19 1159 1686 109933 26904 3.31165 3.31165 -125.274 -3.31165 0 0 744469. 2576.02 0.03 0.06 0.12 -1 -1 0.03 0.022771 0.0197669 123 34 60 30 30 30 + fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 4.76 vpr 63.23 MiB 0.04 6816 -1 -1 1 0.03 -1 -1 30112 -1 -1 21 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64744 32 32 314 256 1 199 85 17 17 289 -1 unnamed_device 24.0 MiB 1.78 1163 14407 4027 8826 1554 63.2 MiB 0.15 0.00 4.37635 -153.345 -4.37635 4.37635 0.33 0.000649324 0.000604396 0.0520894 0.0484335 -1 -1 -1 -1 32 3043 47 6.89349e+06 295971 586450. 2029.24 1.08 0.17418 0.152423 25474 144626 -1 2472 18 1486 2592 197683 43427 3.7754 3.7754 -146.81 -3.7754 0 0 744469. 2576.02 0.03 0.07 0.12 -1 -1 0.03 0.0230032 0.0200354 126 34 64 32 32 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 4.35 vpr 63.06 MiB 0.05 6988 -1 -1 1 0.03 -1 -1 30404 -1 -1 26 25 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64572 25 32 251 214 1 162 83 17 17 289 -1 unnamed_device 23.6 MiB 0.98 688 11423 2933 7572 918 63.1 MiB 0.10 0.00 3.8262 -99.1533 -3.8262 3.8262 0.33 0.000535906 0.00049956 0.035518 0.0331009 -1 -1 -1 -1 28 2060 38 6.89349e+06 366440 531479. 1839.03 1.52 0.18858 0.162195 24610 126494 -1 1597 20 1045 1416 94744 24504 3.09471 3.09471 -100.32 -3.09471 0 0 648988. 2245.63 0.03 0.05 0.11 -1 -1 0.03 0.0207982 0.0179176 103 34 50 25 25 25 + fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 5.31 vpr 63.52 MiB 0.05 7212 -1 -1 1 0.03 -1 -1 30608 -1 -1 33 32 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65044 32 32 432 346 1 288 97 17 17 289 -1 unnamed_device 24.5 MiB 2.27 1580 18079 5345 10673 2061 63.5 MiB 0.21 0.00 4.63015 -159.985 -4.63015 4.63015 0.33 0.000798293 0.00074155 0.0678044 0.0629363 -1 -1 -1 -1 32 3820 28 6.89349e+06 465097 586450. 2029.24 1.01 0.196504 0.17261 25474 144626 -1 3049 22 2642 3823 268741 61061 3.84746 3.84746 -153.108 -3.84746 0 0 744469. 2576.02 0.03 0.10 0.12 -1 -1 0.03 0.0334057 0.028964 187 94 32 32 94 32 + fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 5.98 vpr 63.41 MiB 0.05 7280 -1 -1 1 0.03 -1 -1 30368 -1 -1 34 31 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64932 31 32 421 339 1 274 97 17 17 289 -1 unnamed_device 24.4 MiB 2.09 1424 7645 1561 5653 431 63.4 MiB 0.10 0.00 4.77128 -155.482 -4.77128 4.77128 0.33 0.000785282 0.00072944 0.0294522 0.0273626 -1 -1 -1 -1 36 3008 22 6.89349e+06 479191 648988. 2245.63 1.97 0.23972 0.206091 26050 158493 -1 2694 17 1684 2423 159887 38092 4.07659 4.07659 -150.939 -4.07659 0 0 828058. 2865.25 0.03 0.07 0.13 -1 -1 0.03 0.0270512 0.0236163 182 94 29 29 93 31 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/golden_results.txt index 1cd9c9c84b1..4e15e0febf8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 598.66 vpr 960.23 MiB 13.68 133976 -1 -1 27 17.69 -1 -1 143016 -1 -1 5856 641 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 983276 641 128 52347 52475 1 24532 6625 91 91 8281 clb auto 357.7 MiB 160.79 318332 960.2 MiB 89.62 0.73 12.6254 -34290.9 -12.6254 12.6254 72.13 0.0592375 0.0517226 8.48988 7.13926 68 455834 31 2.5209e+08 7.05985e+07 3.55803e+07 4296.62 157.20 31.0104 26.6124 421084 16 109170 237403 17951291 3376200 13.6905 13.6905 -36287.5 -13.6905 0 0 4.43124e+07 5351.09 22.01 7.24 3.1936 2.8713 42271 15098 -1 -1 -1 -1 - k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 2.70 vpr 62.27 MiB 0.03 9516 -1 -1 11 0.24 -1 -1 37588 -1 -1 46 54 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 63768 54 51 469 520 1 312 151 10 10 100 clb auto 24.4 MiB 0.10 2353 62.3 MiB 0.07 0.00 5.08149 -205.596 -5.08149 5.08149 0.17 0.000392086 0.000311852 0.015759 0.0132278 50 5234 25 1.91864e+06 554530 264954. 2649.54 1.11 0.148127 0.128494 4614 22 1947 8386 484081 113201 5.49532 5.49532 -235.774 -5.49532 0 0 317040. 3170.40 0.08 0.11 0.03397 0.0308444 359 359 -1 -1 -1 -1 - k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 721.72 vpr 993.43 MiB 13.23 119524 -1 -1 1 4.23 -1 -1 173176 -1 -1 5778 641 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1017272 641 128 63843 53443 1 24926 6547 90 90 8100 clb auto 410.9 MiB 27.41 304069 991.9 MiB 226.58 1.31 7.15186 -24073.5 -7.15186 7.15186 71.60 0.0585901 0.0478535 9.32155 7.68188 84 399830 26 2.53171e+08 7.25663e+07 4.14494e+07 5117.21 284.66 36.1117 30.8063 377918 28 85229 152359 14087442 2558840 6.0606 6.0606 -24169.7 -6.0606 0 0 5.22475e+07 6450.30 26.97 7.77 4.41712 3.91642 43425 3440 12624 36 0 0 - k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 4.43 vpr 62.77 MiB 0.03 9708 -1 -1 4 0.16 -1 -1 37160 -1 -1 42 54 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64280 54 51 517 516 1 303 147 10 10 100 clb auto 24.8 MiB 1.39 2083 62.8 MiB 0.08 0.00 4.02436 -195.095 -4.02436 4.02436 0.17 0.000342444 0.000276702 0.0186213 0.015713 54 4284 26 1.94278e+06 527436 279084. 2790.84 1.66 0.190374 0.164594 3699 14 1415 5494 270401 63439 4.06651 4.06651 -209.119 -4.06651 0 0 343682. 3436.82 0.09 0.07 0.0271413 0.0252567 315 291 60 18 54 18 - k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 601.64 vpr 995.39 MiB 13.26 119624 -1 -1 1 3.96 -1 -1 173248 -1 -1 5777 641 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1019280 641 128 63843 53443 1 24852 6546 90 90 8100 clb auto 418.2 MiB 43.82 300188 995.4 MiB 232.78 1.24 6.78969 -23600.7 -6.78969 6.78969 70.51 0.0553422 0.0482949 9.58768 7.83378 70 420422 50 2.53845e+08 7.32471e+07 3.57218e+07 4410.10 152.16 34.4167 29.3473 391652 15 95578 169458 17599752 3082471 6.14994 6.14994 -24121.7 -6.14994 0 0 4.49017e+07 5543.42 22.47 6.34 2.82915 2.54089 43447 3440 12624 36 0 0 - k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 4.80 vpr 62.46 MiB 0.03 9556 -1 -1 4 0.16 -1 -1 37128 -1 -1 41 54 0 0 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 63956 54 51 517 516 1 301 146 10 10 100 clb auto 24.7 MiB 1.00 2091 62.5 MiB 0.07 0.00 3.49134 -180.988 -3.49134 3.49134 0.17 0.000334437 0.000274835 0.0142493 0.0122451 46 4918 46 1.94854e+06 519798 244280. 2442.80 2.43 0.235119 0.203245 3980 19 1895 7398 407017 96041 3.5254 3.5254 -198.595 -3.5254 0 0 298105. 2981.05 0.08 0.09 0.030901 0.028364 314 291 60 18 54 18 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_N8_gate_boost_0.2V_22nm.xml Md5Core.v common 904.68 vpr 1.14 GiB 18.37 133724 -1 -1 27 15.68 -1 -1 139168 -1 -1 6624 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1194824 641 128 52347 52475 1 22515 7393 97 97 9409 clb auto 310.4 MiB 22.85 298740 9149996 3753498 5333891 62607 1166.8 MiB 96.26 0.74 15.7412 -38591.1 -15.7412 15.7412 30.42 0.089974 0.0781796 12.053 10.084 -1 -1 -1 -1 56 426274 31 2.89231e+08 7.98576e+07 3.46650e+07 3684.24 657.45 60.0816 49.7342 912566 8524037 -1 405147 17 94617 217119 15169611 3148784 13.8543 13.8543 -35439 -13.8543 0 0 4.24521e+07 4511.86 2.43 8.46 7.26 -1 -1 2.43 4.03963 3.48005 44415 15098 -1 -1 -1 -1 + k6_N8_gate_boost_0.2V_22nm.xml cordic.v common 5.25 vpr 64.36 MiB 0.08 9300 -1 -1 11 0.25 -1 -1 32860 -1 -1 54 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65900 54 51 469 520 1 286 159 11 11 121 clb auto 25.2 MiB 0.16 2396 14349 2717 10798 834 64.4 MiB 0.15 0.00 5.78243 -247.508 -5.78243 5.78243 0.13 0.00148725 0.00137134 0.0570149 0.052511 -1 -1 -1 -1 46 5422 28 2.09946e+06 650970 304223. 2514.24 3.13 0.592987 0.51407 10132 69752 -1 4577 18 1669 7724 363406 87385 5.1128 5.1128 -231.102 -5.1128 0 0 371547. 3070.64 0.01 0.15 0.06 -1 -1 0.01 0.0601602 0.0534512 359 359 -1 -1 -1 -1 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 945.24 vpr 1.22 GiB 14.77 119136 -1 -1 1 4.75 -1 -1 169236 -1 -1 6208 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1275364 641 128 63843 53443 1 25019 6977 94 94 8836 clb auto 345.6 MiB 24.23 286843 10336022 4163054 5963355 209613 1245.5 MiB 252.94 1.74 6.91605 -25945.5 -6.91605 6.91605 29.94 0.0859758 0.0710401 13.9672 11.53 -1 -1 -1 -1 66 396883 44 2.78555e+08 7.79671e+07 3.71258e+07 4201.65 555.20 59.0437 48.8196 947360 9542419 -1 370537 18 99136 180208 14815346 2853307 4.59448 4.59448 -22721.2 -4.59448 0 0 4.63522e+07 5245.84 2.74 7.65 8.20 -1 -1 2.74 3.85648 3.30259 44203 3442 12624 36 0 0 + k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 7.69 vpr 65.05 MiB 0.08 9280 -1 -1 4 0.16 -1 -1 33104 -1 -1 51 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66608 54 51 517 516 1 297 156 11 11 121 clb auto 25.7 MiB 1.55 2180 12307 2298 9064 945 65.0 MiB 0.15 0.00 4.53625 -236.732 -4.53625 4.53625 0.13 0.00143278 0.00131459 0.0488556 0.0451651 -1 -1 -1 -1 42 4925 36 2.13115e+06 640458 271555. 2244.25 4.18 0.701293 0.605871 10024 64108 -1 4231 30 2262 11552 672859 177202 3.82788 3.82788 -212.131 -3.82788 0 0 347739. 2873.88 0.01 0.24 0.06 -1 -1 0.01 0.0855185 0.0753713 315 295 60 18 54 18 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml Md5Core.v common 536.95 vpr 1.18 GiB 18.45 119164 -1 -1 1 4.62 -1 -1 169160 -1 -1 6224 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1233924 641 128 63843 53443 1 25134 6993 94 94 8836 clb auto 353.0 MiB 37.25 281948 10233972 4151923 5847650 234399 1205.0 MiB 273.47 1.74 6.79691 -25446.5 -6.79691 6.79691 30.65 0.0837999 0.0722687 14.1256 11.7008 -1 -1 -1 -1 68 391509 39 2.79293e+08 7.8915e+07 3.80124e+07 4301.99 106.46 44.7539 37.1554 956196 9731417 -1 364633 17 102524 185933 15374308 2998695 4.58117 4.58117 -22276.8 -4.58117 0 0 4.73504e+07 5358.81 3.23 8.69 8.17 -1 -1 3.23 4.10562 3.53354 44381 3442 12624 36 0 0 + k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml cordic.v common 5.18 vpr 64.96 MiB 0.09 9316 -1 -1 4 0.16 -1 -1 33216 -1 -1 49 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66520 54 51 517 516 1 302 154 11 11 121 clb auto 25.8 MiB 0.53 2227 11278 1862 8633 783 65.0 MiB 0.14 0.01 4.6946 -234.829 -4.6946 4.6946 0.13 0.00145318 0.00133151 0.0449965 0.0415935 -1 -1 -1 -1 40 4906 30 2.13871e+06 621222 258219. 2134.04 2.74 0.473879 0.41168 9904 61394 -1 4507 16 1551 6485 367369 88315 4.05888 4.05888 -216.164 -4.05888 0 0 338486. 2797.40 0.01 0.14 0.06 -1 -1 0.01 0.054532 0.0488347 316 295 60 18 54 18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/golden_results.txt index fa1e6a13164..04afcf5aa7b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_2ripple_N8_22nm.xml Md5Core.v common 1345.54 vpr 843.61 MiB 19.63 119156 -1 -1 1 4.60 -1 -1 169172 -1 -1 3158 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 863860 641 128 63843 53443 1 23908 3927 67 67 4489 clb auto 333.0 MiB 941.47 238707 4308618 1653800 2561467 93351 843.6 MiB 113.38 1.02 7.62466 -26238.2 -7.62466 7.62466 38.80 0.0900086 0.0781522 12.8973 10.8798 94 348495 43 1.40629e+08 4.5715e+07 2.66495e+07 5936.62 150.85 46.5822 39.074 610042 7319579 -1 311881 17 109690 149750 16562445 2801122 6.6934 6.6934 -24791.4 -6.6934 0 0 3.32742e+07 7412.38 14.55 8.41 6.36 -1 -1 14.55 4.14356 3.60079 23344 3442 12624 36 0 0 -k6_frac_2ripple_N8_22nm.xml cordic.v common 8.48 vpr 64.71 MiB 0.08 9264 -1 -1 4 0.67 -1 -1 32964 -1 -1 30 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66264 54 51 517 516 1 317 135 9 9 81 clb auto 26.0 MiB 3.70 1928 12591 2777 8745 1069 64.7 MiB 0.14 0.00 4.22749 -230.57 -4.22749 4.22749 0.17 0.00141093 0.00129827 0.0575671 0.0532357 58 4528 48 1.45065e+06 434271 237595. 2933.27 1.94 0.466668 0.405335 7864 57025 -1 3678 22 2146 7902 424283 100359 3.88422 3.88422 -214.982 -3.88422 0 0 298762. 3688.42 0.06 0.18 0.07 -1 -1 0.06 0.0681518 0.0603634 223 295 60 18 54 18 -k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1078.50 vpr 824.74 MiB 19.19 119160 -1 -1 1 4.32 -1 -1 169116 -1 -1 3164 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 844532 641 128 63843 53443 1 23903 3933 67 67 4489 clb auto 325.8 MiB 725.52 236753 4379445 1690051 2596186 93208 824.7 MiB 92.80 0.77 7.40731 -25921.7 -7.40731 7.40731 38.55 0.0817046 0.0702754 12.4206 10.4665 94 336057 42 1.41393e+08 4.65612e+07 2.66495e+07 5936.62 125.43 41.24 34.5853 610042 7319579 -1 304945 16 105315 145559 15279873 2577115 6.2474 6.2474 -24272.2 -6.2474 0 0 3.32742e+07 7412.38 12.66 7.72 6.34 -1 -1 12.66 3.82185 3.32566 23332 3442 12624 36 0 0 -k6_frac_2uripple_N8_22nm.xml cordic.v common 4.58 vpr 64.71 MiB 0.10 9248 -1 -1 4 0.67 -1 -1 32908 -1 -1 31 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66260 54 51 517 516 1 322 136 9 9 81 clb auto 26.0 MiB 0.32 1855 10955 2337 7732 886 64.7 MiB 0.12 0.00 4.14249 -227.55 -4.14249 4.14249 0.17 0.00138708 0.00127662 0.049497 0.0457647 60 4035 30 1.45905e+06 456186 242836. 2997.97 1.47 0.347941 0.302314 7944 58396 -1 3327 18 1973 6844 325272 81930 3.74077 3.74077 -210.366 -3.74077 0 0 304930. 3764.57 0.07 0.14 0.07 -1 -1 0.07 0.0558437 0.0496984 227 295 60 18 54 18 -k6_frac_N8_22nm.xml Md5Core.v common 1232.05 vpr 861.79 MiB 18.39 133792 -1 -1 27 15.07 -1 -1 139148 -1 -1 3438 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 882472 641 128 52347 52475 1 23739 4207 70 70 4900 clb auto 279.5 MiB 756.19 255287 4315476 1661008 2584916 69552 855.8 MiB 55.93 0.45 15.3287 -39294.9 -15.3287 15.3287 41.71 0.0836165 0.0720047 11.6572 9.72775 90 377297 35 1.54829e+08 4.63167e+07 2.82429e+07 5763.86 264.70 56.8895 47.4295 638746 7615755 -1 353369 19 110041 232156 17925116 3249677 13.664 13.664 -36226.3 -13.664 0 0 3.48442e+07 7111.06 15.25 10.12 6.75 -1 -1 15.25 4.78713 4.16617 24673 15098 -1 -1 -1 -1 -k6_frac_N8_22nm.xml cordic.v common 6.46 vpr 64.57 MiB 0.07 9144 -1 -1 11 0.71 -1 -1 32832 -1 -1 34 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66120 54 51 469 520 1 309 139 9 9 81 clb auto 25.4 MiB 0.22 2174 8396 1359 6431 606 64.6 MiB 0.10 0.00 6.18892 -253.076 -6.18892 6.18892 0.17 0.00148504 0.00137147 0.0408609 0.0378237 64 4974 36 1.41552e+06 458048 257695. 3181.41 3.49 0.665842 0.574693 8044 62425 -1 4274 16 1979 7908 463358 108363 5.6854 5.6854 -236.355 -5.6854 0 0 325495. 4018.46 0.07 0.16 0.08 -1 -1 0.07 0.0545932 0.0486561 260 359 -1 -1 -1 -1 -k6_frac_ripple_N8_22nm.xml Md5Core.v common 1505.87 vpr 940.51 MiB 18.52 119108 -1 -1 1 4.45 -1 -1 169136 -1 -1 3939 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 963080 641 128 63843 53443 1 22927 4708 75 75 5625 clb auto 305.9 MiB 883.44 247966 5684356 2056083 3381895 246378 940.5 MiB 196.60 1.29 8.34964 -24574.8 -8.34964 8.34964 52.46 0.0937 0.0766502 13.4951 11.1191 80 342149 48 1.79437e+08 5.50405e+07 2.91229e+07 5177.40 271.91 57.9694 48.0698 717126 7920329 -1 325246 23 104183 175560 15728014 2904682 5.77787 5.77787 -21906 -5.77787 0 0 3.65283e+07 6493.92 13.62 8.30 6.56 -1 -1 13.62 4.37971 3.70517 29971 3442 12624 36 0 0 -k6_frac_ripple_N8_22nm.xml cordic.v common 6.28 vpr 64.21 MiB 0.10 9368 -1 -1 4 0.67 -1 -1 32960 -1 -1 32 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65748 54 51 517 516 1 308 137 9 9 81 clb auto 25.5 MiB 1.79 1973 8256 1458 6016 782 64.2 MiB 0.10 0.00 4.53631 -225.368 -4.53631 4.53631 0.17 0.0013957 0.00128956 0.0377693 0.034954 58 4378 29 1.43308e+06 447163 237595. 2933.27 1.75 0.39112 0.338338 7864 57025 -1 3755 20 1946 7125 408241 97925 3.83476 3.83476 -204.238 -3.83476 0 0 298762. 3688.42 0.07 0.16 0.07 -1 -1 0.07 0.0595007 0.0525933 235 295 60 18 54 18 -k6_frac_uripple_N8_22nm.xml Md5Core.v common 982.08 vpr 949.34 MiB 19.21 119216 -1 -1 1 4.29 -1 -1 169148 -1 -1 4035 641 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 972120 641 128 63843 53443 1 23951 4804 76 76 5776 clb auto 298.1 MiB 444.87 279860 5758360 2092735 3370157 295468 949.3 MiB 155.35 1.08 9.03188 -27023.3 -9.03188 9.03188 53.40 0.0797474 0.0683203 12.4205 10.4126 74 366559 30 1.87279e+08 5.68659e+07 2.80207e+07 4851.23 229.52 50.1288 41.5608 710444 7492861 -1 338755 20 85472 118774 11490599 2020589 7.0444 7.0444 -24245.9 -7.0444 0 0 3.48777e+07 6038.39 13.16 7.09 6.21 -1 -1 13.16 4.01472 3.43224 30624 3442 12624 36 0 0 -k6_frac_uripple_N8_22nm.xml cordic.v common 4.79 vpr 64.06 MiB 0.10 9168 -1 -1 4 0.67 -1 -1 33056 -1 -1 34 54 0 0 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65600 54 51 517 516 1 312 139 9 9 81 clb auto 25.4 MiB 0.60 1998 7319 1124 5518 677 64.1 MiB 0.09 0.00 4.76334 -234.438 -4.76334 4.76334 0.17 0.00141492 0.00129496 0.0342431 0.0317551 58 4035 26 1.43728e+06 479191 237595. 2933.27 1.43 0.331668 0.287909 7864 57025 -1 3625 18 1765 6255 317707 78027 3.8948 3.8948 -205.264 -3.8948 0 0 298762. 3688.42 0.06 0.14 0.07 -1 -1 0.06 0.0568345 0.050492 249 295 60 18 54 18 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_2ripple_N8_22nm.xml Md5Core.v common 719.95 vpr 930.50 MiB 18.37 119188 -1 -1 1 4.56 -1 -1 169196 -1 -1 3410 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 952828 641 128 63843 53443 1 23477 4179 70 70 4900 clb auto 332.1 MiB 370.76 235506 4781911 1870571 2798467 112873 865.1 MiB 103.32 0.86 7.52141 -26074.7 -7.52141 7.52141 20.32 0.0816713 0.0703528 12.6522 10.5227 -1 -1 -1 -1 96 327519 29 1.58307e+08 4.93629e+07 2.96071e+07 6042.26 146.59 47.2488 39.3458 672214 8127938 -1 305311 18 111930 152921 15206824 2753649 6.01093 6.01093 -24357.7 -6.01093 0 0 3.70091e+07 7552.87 2.30 7.89 6.99 -1 -1 2.30 4.22181 3.66195 23430 3442 12624 36 0 0 + k6_frac_2ripple_N8_22nm.xml cordic.v common 7.37 vpr 65.34 MiB 0.09 9348 -1 -1 4 0.15 -1 -1 33220 -1 -1 32 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66908 54 51 517 516 1 313 137 9 9 81 clb auto 26.1 MiB 3.87 2057 10727 2058 7633 1036 65.3 MiB 0.13 0.00 4.23609 -233.261 -4.23609 4.23609 0.09 0.00141962 0.00130738 0.0490049 0.0453196 -1 -1 -1 -1 60 4196 22 1.45065e+06 463222 242836. 2997.97 1.84 0.496698 0.430402 7944 58396 -1 3645 17 1759 5910 307112 75726 4.31905 4.31905 -218.777 -4.31905 0 0 304930. 3764.57 0.01 0.13 0.06 -1 -1 0.01 0.0544893 0.0486012 228 295 60 18 54 18 + k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1251.68 vpr 860.31 MiB 18.93 119300 -1 -1 1 4.88 -1 -1 169228 -1 -1 3405 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 880956 641 128 63843 53443 1 23524 4174 70 70 4900 clb auto 324.2 MiB 248.39 239120 4740787 1863060 2780694 97033 860.3 MiB 124.98 1.00 7.3147 -25736.6 -7.3147 7.3147 20.89 0.091958 0.0752357 13.2611 11.0893 -1 -1 -1 -1 82 347465 34 1.59139e+08 5.01078e+07 2.58747e+07 5280.54 778.86 64.8144 53.6614 628122 6995602 -1 313528 19 112390 157276 15412644 2790255 5.6429 5.6429 -24107.4 -5.6429 0 0 3.23196e+07 6595.84 1.82 8.47 5.85 -1 -1 1.82 4.58889 3.93913 23428 3442 12624 36 0 0 + k6_frac_2uripple_N8_22nm.xml cordic.v common 3.44 vpr 65.43 MiB 0.09 9216 -1 -1 4 0.16 -1 -1 33192 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67000 54 51 517 516 1 318 138 9 9 81 clb auto 26.3 MiB 0.36 1922 16158 3946 10822 1390 65.4 MiB 0.18 0.00 4.1935 -227.995 -4.1935 4.1935 0.09 0.0013986 0.00129103 0.0703328 0.065036 -1 -1 -1 -1 56 3937 25 1.45905e+06 485618 231774. 2861.41 1.23 0.383785 0.335697 7704 54090 -1 3462 17 1880 6549 321379 84144 3.8246 3.8246 -211.788 -3.8246 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.0554246 0.0493896 232 295 60 18 54 18 + k6_frac_N8_22nm.xml Md5Core.v common 1278.24 vpr 857.64 MiB 19.62 133848 -1 -1 27 16.10 -1 -1 139176 -1 -1 3560 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 878220 641 128 52347 52475 1 22613 4329 71 71 5041 clb auto 278.2 MiB 210.81 253837 4483111 1724795 2697814 60502 857.6 MiB 66.74 0.54 15.7271 -39246.4 -15.7271 15.7271 20.00 0.0880225 0.0759431 12.0413 10.1053 -1 -1 -1 -1 80 373760 27 1.56446e+08 4.79603e+07 2.60147e+07 5160.63 890.35 63.5702 52.7719 626238 7057181 -1 349344 18 105464 224026 16594796 3174287 13.5919 13.5919 -36084.3 -13.5919 0 0 3.26297e+07 6472.86 1.84 8.74 5.89 -1 -1 1.84 4.37319 3.77951 24995 15098 -1 -1 -1 -1 + k6_frac_N8_22nm.xml cordic.v common 3.34 vpr 64.39 MiB 0.09 9404 -1 -1 11 0.21 -1 -1 33040 -1 -1 33 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65936 54 51 469 520 1 307 138 9 9 81 clb auto 25.3 MiB 0.23 2168 10462 1941 7796 725 64.4 MiB 0.12 0.00 6.49963 -254.17 -6.49963 6.49963 0.09 0.00148553 0.00136363 0.0501404 0.0462173 -1 -1 -1 -1 64 4590 31 1.41552e+06 444576 257695. 3181.41 1.35 0.391024 0.341283 8044 62425 -1 4035 18 1888 7794 404854 99129 5.61742 5.61742 -233.114 -5.61742 0 0 325495. 4018.46 0.01 0.15 0.06 -1 -1 0.01 0.0624396 0.0556903 262 359 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml Md5Core.v common 1236.62 vpr 974.87 MiB 18.63 119092 -1 -1 1 5.40 -1 -1 169112 -1 -1 4156 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 998268 641 128 63843 53443 1 22922 4925 77 77 5929 clb auto 303.2 MiB 860.38 269984 5994337 2194745 3524702 274890 974.9 MiB 179.38 1.17 7.28071 -25362.6 -7.28071 7.28071 24.44 0.0868232 0.070468 12.705 10.4847 -1 -1 -1 -1 74 383007 50 1.88597e+08 5.80724e+07 2.87929e+07 4856.27 92.21 41.4301 34.2283 728640 7699156 -1 360816 23 121596 201798 19887743 3889899 5.17537 5.17537 -23064.7 -5.17537 0 0 3.58422e+07 6045.24 2.14 9.78 6.48 -1 -1 2.14 4.76556 4.03104 30007 3442 12624 36 0 0 + k6_frac_ripple_N8_22nm.xml cordic.v common 5.17 vpr 64.61 MiB 0.09 9384 -1 -1 4 0.16 -1 -1 33188 -1 -1 35 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66160 54 51 517 516 1 306 140 9 9 81 clb auto 25.6 MiB 1.86 2034 15749 3494 10440 1815 64.6 MiB 0.19 0.00 4.60908 -224.227 -4.60908 4.60908 0.09 0.00141288 0.00129939 0.0670027 0.0617908 -1 -1 -1 -1 56 4304 35 1.43308e+06 489084 231774. 2861.41 1.49 0.487985 0.424161 7704 54090 -1 3690 17 1831 6439 331209 84904 3.85365 3.85365 -205.536 -3.85365 0 0 286113. 3532.26 0.01 0.13 0.05 -1 -1 0.01 0.054238 0.0481705 239 295 60 18 54 18 + k6_frac_uripple_N8_22nm.xml Md5Core.v common 1259.85 vpr 1.03 GiB 18.42 119200 -1 -1 1 5.18 -1 -1 169000 -1 -1 4209 641 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1080808 641 128 63843 53443 1 23625 4978 78 78 6084 clb auto 298.6 MiB 267.64 265982 6207934 2313787 3686907 207240 1055.5 MiB 218.86 1.42 8.76338 -26782 -8.76338 8.76338 26.03 0.086622 0.0748437 13.4573 11.3319 -1 -1 -1 -1 58 374194 42 1.94536e+08 5.93179e+07 2.42024e+07 3978.04 672.28 59.587 49.4099 688856 6339671 -1 334274 17 91351 128675 11823089 2309725 6.4004 6.4004 -23909.5 -6.4004 0 0 3.02494e+07 4971.96 1.65 7.05 5.14 -1 -1 1.65 3.73867 3.13107 30395 3442 12624 36 0 0 + k6_frac_uripple_N8_22nm.xml cordic.v common 4.05 vpr 64.43 MiB 0.08 9404 -1 -1 4 0.16 -1 -1 33148 -1 -1 35 54 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65972 54 51 517 516 1 310 140 9 9 81 clb auto 25.4 MiB 0.67 2149 11030 2051 7862 1117 64.4 MiB 0.14 0.00 4.36445 -234.289 -4.36445 4.36445 0.09 0.00141199 0.00129434 0.0496983 0.0458465 -1 -1 -1 -1 56 4579 37 1.43728e+06 493284 231774. 2861.41 1.63 0.469693 0.406996 7704 54090 -1 3879 20 1959 7459 402962 103780 3.73026 3.73026 -208.468 -3.73026 0 0 286113. 3532.26 0.01 0.15 0.05 -1 -1 0.01 0.0602283 0.0532613 256 295 60 18 54 18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt index 7964e15f7be..413802afe0b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt @@ -1,31 +1,31 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.86 vpr 64.10 MiB 0.09 9392 -1 -1 3 0.28 -1 -1 34500 -1 53004 68 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 65640 99 130 363 493 1 258 298 12 12 144 clb auto 25.1 MiB 0.11 959 66963 20877 35036 11050 64.1 MiB 0.25 0.00 2.19547 -220.397 -2.19547 2.19547 0.26 0.000888885 0.000830781 0.083606 0.0788776 -1 -1 -1 -1 44 1703 11 5.66058e+06 4.21279e+06 360780. 2505.42 0.90 0.275088 0.252948 13094 71552 -1 1588 7 435 526 37760 12301 2.62103 2.62103 -239.974 -2.62103 0 0 470765. 3269.20 0.10 0.04 0.07 -1 -1 0.10 0.0257276 0.0238689 0.008006 0.2706 0.07512 0.6543 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 9.49 vpr 67.67 MiB 0.04 9348 -1 -1 15 0.30 -1 -1 34596 -1 54736 39 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69296 162 96 999 932 1 700 302 16 16 256 mult_36 auto 28.2 MiB 0.21 5813 84298 23720 53467 7111 67.7 MiB 0.68 0.01 20.9992 -1841.13 -20.9992 20.9992 0.46 0.00373748 0.0035203 0.323095 0.304438 -1 -1 -1 -1 46 13307 40 1.21132e+07 4.08187e+06 727248. 2840.81 3.84 1.09252 1.01361 24972 144857 -1 10229 22 3566 7249 945644 266838 22.6939 22.6939 -1995.17 -22.6939 0 0 934704. 3651.19 0.21 0.39 0.13 -1 -1 0.21 0.18746 0.174886 0.007576 0.3575 0.01677 0.6257 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 696.57 vpr 553.42 MiB 19.92 218908 -1 -1 127 252.42 -1 -1 94120 -1 131280 2033 114 44 8 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 566700 114 102 29627 29353 1 15945 2301 55 55 3025 clb auto 210.0 MiB 31.31 230514 1642173 595704 1018876 27593 540.5 MiB 48.51 0.39 78.2692 -58089.8 -78.2692 78.2692 24.93 0.086973 0.0768336 10.7593 9.09845 -1 -1 -1 -1 96 342970 28 1.75831e+08 1.3685e+08 1.91810e+07 6340.82 195.12 37.5378 31.1093 414120 4030168 -1 311902 20 61622 243318 13757769 2438696 78.5659 78.5659 -72067.7 -78.5659 -30.242 -0.295467 2.39857e+07 7929.14 7.35 8.59 3.70 -1 -1 7.35 4.77392 4.09434 0.1059 0.4192 0.01061 0.5702 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.66 vpr 64.15 MiB 0.08 9336 -1 -1 3 0.27 -1 -1 34464 -1 53020 68 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 65692 99 130 363 493 1 258 298 12 12 144 clb auto 25.1 MiB 0.10 959 66963 20877 35036 11050 64.2 MiB 0.23 0.00 2.19547 -220.397 -2.19547 2.19547 0.26 0.00129073 0.00122255 0.0905854 0.0857208 -1 -1 -1 -1 44 1703 11 5.66058e+06 4.21279e+06 360780. 2505.42 0.84 0.340653 0.313119 13094 71552 -1 1588 7 435 526 37760 12301 2.62103 2.62103 -239.974 -2.62103 0 0 470765. 3269.20 0.11 0.04 0.07 -1 -1 0.11 0.0252461 0.0233937 0.008984 0.2412 0.06695 0.6919 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml diffeq1.v common 9.88 vpr 67.66 MiB 0.06 9504 -1 -1 15 0.36 -1 -1 34620 -1 54700 39 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69280 162 96 999 932 1 700 302 16 16 256 mult_36 auto 28.3 MiB 0.30 5813 84298 23720 53467 7111 67.7 MiB 0.67 0.01 20.9992 -1841.13 -20.9992 20.9992 0.51 0.00364719 0.0034382 0.315399 0.297153 -1 -1 -1 -1 46 12939 32 1.21132e+07 4.08187e+06 727248. 2840.81 3.83 1.0356 0.96046 24972 144857 -1 10365 21 3566 7284 931163 263037 22.5015 22.5015 -1988.97 -22.5015 0 0 934704. 3651.19 0.21 0.37 0.13 -1 -1 0.21 0.171081 0.159064 0.007926 0.3458 0.01615 0.6381 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 756.18 vpr 600.11 MiB 20.31 219020 -1 -1 127 246.99 -1 -1 94172 -1 131552 1938 114 44 8 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 614516 114 102 29627 29353 1 15590 2206 53 53 2809 clb auto 215.9 MiB 63.87 221505 1566792 581029 965817 19946 520.7 MiB 48.75 0.46 78.7649 -55802 -78.7649 78.7649 23.32 0.0977564 0.0805634 11.7533 9.85012 -1 -1 -1 -1 100 329890 44 1.63647e+08 1.3173e+08 1.82848e+07 6509.36 229.47 52.8122 43.5211 391934 3893229 -1 296717 20 58974 234587 13009606 2288152 78.7037 78.7037 -67475.2 -78.7037 -22.6809 -0.293253 2.30694e+07 8212.69 7.40 8.50 3.68 -1 -1 7.40 4.85419 4.15005 0.1043 0.409 0.01013 0.5808 -k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.47 vpr 64.21 MiB 0.06 9328 -1 -1 3 0.27 -1 -1 34516 -1 52912 67 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 65756 99 130 363 493 1 258 297 12 12 144 clb auto 25.3 MiB 0.09 912 71577 22752 36592 12233 64.2 MiB 0.25 0.00 2.17749 -221.419 -2.17749 2.17749 0.27 0.00128772 0.00121844 0.0973662 0.092124 -1 -1 -1 -1 34 1812 15 5.66058e+06 4.1589e+06 307677. 2136.65 1.55 0.509645 0.466454 12584 59343 -1 1647 10 548 718 46799 16285 2.55443 2.55443 -235.172 -2.55443 0 0 377431. 2621.05 0.09 0.05 0.06 -1 -1 0.09 0.0317434 0.0293207 0.007928 0.2374 0.06937 0.6933 -k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 12.05 vpr 68.07 MiB 0.06 9312 -1 -1 15 0.35 -1 -1 34604 -1 54616 38 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69704 162 96 999 932 1 699 301 16 16 256 mult_36 auto 28.7 MiB 0.28 5611 83965 25982 50757 7226 68.1 MiB 0.70 0.01 20.9967 -1752.4 -20.9967 20.9967 0.56 0.00368208 0.00346882 0.327374 0.307452 -1 -1 -1 -1 46 13011 47 1.21132e+07 4.02797e+06 761464. 2974.47 5.84 1.16752 1.08182 25952 154797 -1 9769 32 3388 7483 1099104 316197 22.1698 22.1698 -1892.97 -22.1698 0 0 979054. 3824.43 0.22 0.47 0.13 -1 -1 0.22 0.238042 0.220618 0.007946 0.3448 0.01646 0.6388 -k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 797.26 vpr 576.95 MiB 19.66 219040 -1 -1 127 244.26 -1 -1 94192 -1 131488 1859 114 44 8 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 590792 114 102 29627 29353 1 15873 2127 53 53 2809 clb auto 211.2 MiB 207.60 222448 1492484 550042 918799 23643 576.9 MiB 40.72 0.33 78.3072 -55670.6 -78.3072 78.3072 24.05 0.0857385 0.0755555 10.3641 8.60779 -1 -1 -1 -1 100 323169 38 1.63647e+08 1.27472e+08 1.91159e+07 6805.25 143.13 34.3369 28.4206 405500 4174239 -1 294891 16 55655 220410 11983026 2178775 79.6382 79.6382 -66134.4 -79.6382 -17.5339 -0.29436 2.40369e+07 8557.10 8.05 8.07 3.74 -1 -1 8.05 4.53198 3.91629 0.1084 0.4017 0.01015 0.5881 -k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.43 vpr 64.35 MiB 0.08 9280 -1 -1 3 0.26 -1 -1 34500 -1 53000 67 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 65892 99 130 363 493 1 258 297 12 12 144 clb auto 25.3 MiB 0.09 912 71577 22752 36592 12233 64.3 MiB 0.25 0.00 2.17749 -221.419 -2.17749 2.17749 0.27 0.00129969 0.00123005 0.0974263 0.0921907 -1 -1 -1 -1 32 1947 38 5.66058e+06 4.1589e+06 295695. 2053.44 1.50 0.475807 0.435965 12440 56522 -1 1697 11 551 747 46498 15792 2.47803 2.47803 -236.591 -2.47803 0 0 361905. 2513.23 0.08 0.06 0.05 -1 -1 0.08 0.0336462 0.0310363 0.009086 0.2044 0.06066 0.7349 -k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml diffeq1.v common 10.08 vpr 67.89 MiB 0.06 9368 -1 -1 15 0.36 -1 -1 34708 -1 54736 38 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69524 162 96 999 932 1 699 301 16 16 256 mult_36 auto 28.5 MiB 0.28 5610 83965 25979 50756 7230 67.9 MiB 0.67 0.01 20.9967 -1752.69 -20.9967 20.9967 0.55 0.00362376 0.00341442 0.318346 0.299793 -1 -1 -1 -1 48 12263 38 1.21132e+07 4.02797e+06 791884. 3093.30 3.91 1.12515 1.04331 26208 159478 -1 9793 21 3197 6813 893738 262077 22.0098 22.0098 -1892.01 -22.0098 0 0 1.01413e+06 3961.44 0.23 0.37 0.14 -1 -1 0.23 0.172385 0.160478 0.008313 0.3353 0.01608 0.6486 -k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 835.73 vpr 605.52 MiB 20.55 218940 -1 -1 127 246.80 -1 -1 94084 -1 131572 1784 114 44 8 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 620056 114 102 29627 29353 1 15339 2052 51 51 2601 clb auto 213.3 MiB 206.13 223335 1422758 511358 886246 25154 537.5 MiB 43.06 0.33 78.4175 -55205.9 -78.4175 78.4175 23.01 0.0899449 0.0795648 10.6024 8.96248 -1 -1 -1 -1 102 313896 24 1.52527e+08 1.2343e+08 1.80757e+07 6949.52 173.09 45.2786 37.4329 380370 3944208 -1 292217 19 55586 222906 12296761 2246282 79.3608 79.3608 -63694 -79.3608 -16.4456 -0.29436 2.25881e+07 8684.41 6.62 7.83 3.47 -1 -1 6.62 4.56129 3.92303 0.107 0.3895 0.009646 0.6009 -k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.60 vpr 64.82 MiB 0.06 9320 -1 -1 3 0.27 -1 -1 34644 -1 52860 67 99 1 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 66372 99 130 363 493 1 263 297 12 12 144 clb auto 25.8 MiB 0.09 901 72567 24766 36583 11218 64.8 MiB 0.26 0.00 2.17749 -223.572 -2.17749 2.17749 0.31 0.00129642 0.00122674 0.0986744 0.0933585 -1 -1 -1 -1 38 1762 11 5.66058e+06 4.1589e+06 347689. 2414.51 1.65 0.348272 0.319946 13432 70334 -1 1528 9 475 592 34104 11793 2.5464 2.5464 -238.385 -2.5464 0 0 440062. 3055.98 0.10 0.05 0.04 -1 -1 0.10 0.0299128 0.0276617 0.00795 0.2306 0.07376 0.6956 -k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 10.06 vpr 68.09 MiB 0.06 9364 -1 -1 15 0.38 -1 -1 34700 -1 54620 36 162 0 5 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 69728 162 96 999 932 1 700 299 16 16 256 mult_36 auto 28.8 MiB 0.24 5618 84215 26483 50655 7077 68.1 MiB 0.67 0.01 20.8745 -1914.57 -20.8745 20.8745 0.57 0.00362065 0.00341374 0.323005 0.304388 -1 -1 -1 -1 52 12761 39 1.21132e+07 3.92018e+06 875283. 3419.07 3.97 1.22658 1.13606 27812 183157 -1 9204 19 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logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc + 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/home/elgamma8/research/release/vtr-verilog-to-routing 554912 114 102 29627 29353 1 15922 2251 54 54 2916 clb auto 210.9 MiB 119.52 222919 1580073 571874 985592 22607 531.1 MiB 48.29 0.39 77.8953 -57999.4 -77.8953 77.8953 11.52 0.0926883 0.0822081 11.0789 9.32318 -1 -1 -1 -1 96 331929 43 1.70873e+08 1.34156e+08 1.84738e+07 6335.34 178.58 39.6952 32.8705 399532 3879924 -1 299844 21 60223 237835 13208126 2353586 78.7014 78.7014 -70108.8 -78.7014 -29.771 -0.29436 2.31021e+07 7922.54 1.11 9.04 3.72 -1 -1 1.11 5.15092 4.42498 0.1048 0.4082 0.01076 0.5811 + k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.05 vpr 65.32 MiB 0.08 9324 -1 -1 3 0.27 -1 -1 34472 -1 52808 69 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66884 99 130 363 493 1 258 299 12 12 144 clb auto 25.6 MiB 0.09 913 66233 21239 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 70232 162 96 999 932 1 692 302 16 16 256 mult_36 auto 28.6 MiB 0.26 5546 83286 26609 49026 7651 68.6 MiB 0.64 0.01 21.0243 -1894.68 -21.0243 21.0243 0.26 0.00355367 0.00335054 0.310396 0.292545 -1 -1 -1 -1 54 11790 34 1.21132e+07 4.08187e+06 835850. 3265.04 6.08 1.44279 1.33344 26248 167850 -1 9592 19 3142 6275 854413 269675 22.0932 22.0932 -1987.22 -22.0932 0 0 1.08614e+06 4242.72 0.04 0.35 0.15 -1 -1 0.04 0.160799 0.149782 0.00805 0.3587 0.01739 0.6239 + k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 719.26 vpr 546.14 MiB 18.47 218876 -1 -1 127 261.95 -1 -1 94060 -1 131520 1971 114 44 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 559248 114 102 29627 29353 1 15847 2239 54 54 2916 clb auto 209.6 MiB 135.16 225408 1598108 582829 992381 22898 530.2 MiB 44.62 0.37 78.1966 -55511.9 -78.1966 78.1966 9.94 0.0937316 0.0830703 10.8349 9.12795 -1 -1 -1 -1 98 325803 29 1.70873e+08 1.33509e+08 1.87532e+07 6431.13 134.61 35.0377 28.9908 405364 4004376 -1 300586 20 59494 234219 12688820 2264650 78.0957 78.0957 -66362.9 -78.0957 -27.2952 -0.295467 2.37782e+07 8154.37 1.22 8.76 3.81 -1 -1 1.22 4.98031 4.28265 0.1071 0.4088 0.01084 0.5803 + k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.21 vpr 65.15 MiB 0.06 9328 -1 -1 3 0.33 -1 -1 34540 -1 52848 69 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66716 99 130 363 493 1 263 299 12 12 144 clb auto 25.4 MiB 0.10 990 67232 22930 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3.69 -1 -1 1.15 4.54132 3.87896 0.1061 0.3948 0.01039 0.5948 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt index e44f94f6fb4..746a413d647 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt @@ -1,15 +1,15 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 1042.27 vpr 681.79 MiB 25.44 379864 -1 -1 22 518.01 -1 -1 154072 -1 116500 2560 257 0 11 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 698152 257 32 32041 31556 1 18655 2860 61 61 3721 clb auto 233.1 MiB 36.39 248784 1971184 693534 1249697 27953 667.6 MiB 67.38 0.57 17.2227 -24536 -17.2227 17.2227 32.23 0.0949015 0.0847155 10.7087 9.08247 -1 -1 -1 -1 82 383775 24 2.18169e+08 1.42327e+08 2.04246e+07 5489.00 212.07 51.8327 42.9917 475364 4274107 -1 368989 20 108548 499678 20761050 3200843 17.2471 17.2471 -24997.9 -17.2471 0 0 2.56329e+07 6888.72 9.50 12.11 3.85 -1 -1 9.50 5.44089 4.71206 0.1728 0.4587 0.02687 0.5144 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 178.53 vpr 135.18 MiB 0.80 62972 -1 -1 18 80.57 -1 -1 65724 -1 50856 547 36 0 0 success f4f46d5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-19T20:09:53 betzgrp-wintermute.eecg.utoronto.ca /home/yanhang1/updated-master 138428 36 100 6600 6700 1 2882 683 30 30 900 clb auto 68.0 MiB 4.70 44999 244169 69488 159892 14789 114.4 MiB 5.78 0.06 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 341240 506 553 3285 3838 1 3021 1578 50 50 2500 memory auto 47.5 MiB 4.88 14975 1131087 537386 412299 181402 333.2 MiB 5.48 0.06 7.31798 -1716.46 -7.31798 7.31798 9.59 0.0233425 0.0202789 2.88885 2.58827 -1 -1 -1 -1 38 21877 13 1.47946e+08 5.11946e+07 6.86584e+06 2746.33 21.59 9.34517 8.46777 251304 1421084 -1 21223 14 3882 5152 957849 258652 7.69928 7.69928 -2017.61 -7.69928 -4.40929 -0.295467 8.69095e+06 3476.38 0.42 0.99 1.24 -1 -1 0.42 0.812677 0.750095 0.16 0.1404 0.03929 0.8203 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 11.90 vpr 71.21 MiB 0.17 16564 -1 -1 2 0.57 -1 -1 33572 -1 60112 29 311 15 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72916 311 156 972 1128 1 953 511 28 28 784 memory auto 28.6 MiB 0.52 8675 196543 71995 115326 9222 71.2 MiB 1.12 0.02 3.94157 -4520.2 -3.94157 3.94157 0.88 0.00450683 0.00400124 0.539697 0.478132 -1 -1 -1 -1 38 14424 15 4.25198e+07 9.78293e+06 2.03942e+06 2601.30 3.08 1.42389 1.26202 75902 416746 -1 13482 13 2485 2939 742342 220707 4.30811 4.30811 -5120.27 -4.30811 -9.59348 -0.340786 2.58559e+06 3297.95 0.11 0.34 0.35 -1 -1 0.11 0.190264 0.171934 0.08518 0.1546 0.01779 0.8276 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 20.15 vpr 76.48 MiB 0.45 30028 -1 -1 7 2.80 -1 -1 37892 -1 59140 166 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78316 193 205 2232 2437 1 1230 569 20 20 400 memory auto 35.7 MiB 1.01 9358 240983 80731 132632 27620 76.5 MiB 1.73 0.02 5.06623 -2804.81 -5.06623 5.06623 0.43 0.00696087 0.00630657 0.736351 0.662847 -1 -1 -1 -1 46 17929 33 2.07112e+07 1.16864e+07 1.18195e+06 2954.88 7.39 2.49645 2.21716 40048 238620 -1 14832 16 4536 11233 579630 132122 5.42812 5.42812 -3017.08 -5.42812 -8.60084 -0.359474 1.52036e+06 3800.91 0.05 0.44 0.21 -1 -1 0.05 0.286104 0.260109 0.02818 0.2078 0.02581 0.7664 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 55.48 vpr 103.80 MiB 0.94 40848 -1 -1 27 5.16 -1 -1 43924 -1 61440 247 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 106292 385 394 3979 4310 1 2366 1029 27 27 729 io auto 47.1 MiB 2.79 31256 577452 220184 332574 24694 90.8 MiB 5.47 0.06 14.223 -11856.8 -14.223 14.223 0.83 0.016611 0.0155207 2.13767 1.96728 -1 -1 -1 -1 78 49772 44 3.93038e+07 1.48038e+07 3.65949e+06 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0.258873 0.02191 0.4692 0.04307 0.4877 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 522.61 abc 94.14 MiB 1.59 38664 -1 -1 20 496.43 -1 -1 96404 -1 46400 231 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86112 38 36 3404 3440 1 1299 305 20 20 400 clb auto 42.7 MiB 1.75 14687 64943 16819 44848 3276 84.1 MiB 1.34 0.02 13.5301 -4881.23 -13.5301 13.5301 0.43 0.00872776 0.00786542 0.616796 0.54249 -1 -1 -1 -1 56 24982 33 2.07112e+07 1.24495e+07 1.41661e+06 3541.53 7.53 2.50686 2.16704 42444 283345 -1 21461 15 5499 21648 703274 121673 14.3477 14.3477 -5041.91 -14.3477 0 0 1.80858e+06 4521.44 0.06 0.57 0.24 -1 -1 0.06 0.350084 0.313149 0.01034 0.3838 0.02922 0.587 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 8023.20 vpr 1.87 GiB 83.23 923700 -1 -1 75 6961.27 -1 -1 447876 -1 340272 7516 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1957912 36 356 135102 133883 1 42070 8094 103 103 10609 clb auto 726.6 MiB 80.63 518483 11055510 4565633 6404934 84943 1912.0 MiB 184.45 1.38 68.3226 -364781 -68.3226 68.3226 42.76 0.254885 0.21869 37.8791 31.4262 -1 -1 -1 -1 82 699404 45 6.46441e+08 5.02852e+08 5.95200e+07 5610.33 254.16 127.752 104.712 1372100 12531702 -1 665004 19 157793 498465 26586492 5156950 69.6527 69.6527 -457878 -69.6527 0 0 7.45804e+07 7029.92 3.45 20.21 11.41 -1 -1 3.45 13.9724 11.9555 0.2965 0.3745 0.01315 0.6123 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc/config/golden_results.txt index 4c1d5cbd7fa..801b3e6f120 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 6.44 vpr 64.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65860 14 8 926 934 0 490 100 11 11 121 clb auto 24.8 MiB 0.91 4540 5436 746 4365 325 64.3 MiB 0.22 0.01 4.4958 -31.528 -4.4958 nan 0.32 0.00518513 0.00476183 0.142243 0.131594 52 7157 39 4.36541e+06 4.20373e+06 379421. 3135.71 3.12 1.54305 1.41039 12531 77429 -1 6624 17 3168 14393 437125 83566 4.8594 nan -34.0978 -4.8594 0 0 499620. 4129.09 0.12 0.35 0.11 -1 -1 0.12 0.217292 0.201716 -k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 10.42 vpr 66.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 103 38 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67776 38 3 1113 1116 0 662 144 13 13 169 clb auto 26.6 MiB 1.57 7370 11454 1699 8583 1172 66.2 MiB 0.36 0.01 5.6032 -16.0295 -5.6032 nan 0.48 0.00608264 0.00556782 0.216301 0.199813 66 12625 26 6.52117e+06 5.55108e+06 710325. 4203.11 5.48 1.80568 1.65233 19379 142405 -1 11924 18 4624 23024 803122 126844 5.75407 nan -16.4608 -5.75407 0 0 879032. 5201.38 0.21 0.49 0.22 -1 -1 0.21 0.268726 0.249892 -k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 8.36 vpr 64.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65900 9 19 897 916 0 556 110 12 12 144 clb auto 24.8 MiB 1.43 6155 6948 1152 5347 449 64.4 MiB 0.19 0.00 4.85584 -79.8781 -4.85584 nan 0.40 0.00184535 0.00164299 0.102414 0.0941394 64 10771 28 5.3894e+06 4.41931e+06 575115. 3993.85 4.15 1.4005 1.27741 16224 115365 -1 9685 19 3941 19896 705511 115372 5.17072 nan -84.2996 -5.17072 0 0 716128. 4973.11 0.16 0.44 0.18 -1 -1 0.16 0.238518 0.221526 -k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 9.13 vpr 65.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67428 229 197 1364 1561 1 539 497 16 16 256 io auto 26.3 MiB 0.80 3888 151956 45040 98819 8097 65.8 MiB 1.02 0.01 3.01736 -656.133 -3.01736 3.01736 0.79 0.00693433 0.00645616 0.560233 0.521561 38 7443 37 1.05632e+07 3.82647e+06 667532. 2607.55 3.90 2.38635 2.22107 25328 137766 -1 6882 14 1605 4348 206877 47610 3.0708 3.0708 -728.475 -3.0708 0 0 843755. 3295.92 0.23 0.33 0.19 -1 -1 0.23 0.246405 0.231441 -k6_frac_N10_40nm.xml clma.pre-vpr.blif common 43.74 vpr 89.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 307 62 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 91560 62 82 3672 3754 1 2344 451 20 20 400 clb auto 45.4 MiB 4.13 29194 126595 33709 86071 6815 89.4 MiB 3.36 0.04 7.83344 -342.752 -7.83344 7.83344 1.33 0.0213741 0.0195703 1.719 1.5557 92 46721 44 1.74617e+07 1.65455e+07 2.37849e+06 5946.23 27.30 8.57955 7.81451 54288 506964 -1 42503 16 14653 63396 2356990 367690 8.12752 8.12752 -355.073 -8.12752 0 0 3.01539e+06 7538.48 0.77 1.55 0.89 -1 -1 0.77 0.838641 0.780724 -k6_frac_N10_40nm.xml des.pre-vpr.blif common 9.42 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64488 256 245 954 1199 0 578 552 18 18 324 io auto 23.8 MiB 0.31 4966 131806 34568 89483 7755 63.0 MiB 0.74 0.01 3.70962 -712.314 -3.70962 nan 1.04 0.00594369 0.00563587 0.363143 0.344074 36 9086 34 1.37969e+07 2.74859e+06 824466. 2544.65 4.56 1.92823 1.82519 31748 166456 -1 8145 16 2076 4578 247499 55677 4.28288 nan -799.816 -4.28288 0 0 1.01518e+06 3133.28 0.29 0.31 0.23 -1 -1 0.29 0.217585 0.206808 -k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 5.00 vpr 64.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 65 64 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66216 64 39 1371 1410 1 542 168 11 11 121 clb auto 25.5 MiB 0.49 3387 16373 2957 12425 991 64.7 MiB 0.34 0.01 5.33717 -1012.06 -5.33717 5.33717 0.32 0.00551817 0.00506527 0.217367 0.199664 46 5978 20 4.36541e+06 3.50311e+06 343362. 2837.71 2.08 1.1317 1.03145 12051 69045 -1 5146 15 1964 5478 158754 33013 5.81148 5.81148 -1104.11 -5.81148 0 0 440296. 3638.81 0.10 0.26 0.10 -1 -1 0.10 0.200354 0.185353 -k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 13.46 vpr 65.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67568 229 197 1362 1559 1 570 496 16 16 256 io auto 26.5 MiB 0.92 4585 165304 49025 107137 9142 66.0 MiB 1.16 0.01 3.10283 -686.218 -3.10283 3.10283 0.79 0.00699037 0.00652345 0.625484 0.582292 34 9041 35 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-1 84 41 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66792 41 35 1006 1041 0 604 160 12 12 144 clb auto 25.8 MiB 1.25 6526 13180 2280 9516 1384 65.2 MiB 0.34 0.01 4.5556 -135.416 -4.5556 nan 0.40 0.00567464 0.00519319 0.194713 0.180099 64 11365 46 5.3894e+06 4.5271e+06 575115. 3993.85 7.24 2.30466 2.10936 16224 115365 -1 10143 18 4137 19881 679868 115960 4.93645 nan -144.738 -4.93645 0 0 716128. 4973.11 0.16 0.46 0.18 -1 -1 0.16 0.25103 0.233257 -k6_frac_N10_40nm.xml spla.pre-vpr.blif common 21.57 vpr 77.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 79132 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.6 MiB 2.77 15884 45628 10574 32142 2912 77.3 MiB 1.36 0.02 5.95671 -204.452 -5.95671 nan 0.91 0.0133587 0.0121199 0.775594 0.707225 74 25546 32 1.21262e+07 1.16411e+07 1.39325e+06 4820.95 11.37 4.19873 3.8273 35379 286977 -1 24647 19 7675 42760 1737904 249467 6.14143 nan -217.643 -6.14143 0 0 1.74421e+06 6035.33 0.44 1.20 0.46 -1 -1 0.44 0.621038 0.575028 -k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 4.92 vpr 65.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 61 52 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66784 52 122 1461 1583 1 474 235 10 10 100 clb auto 26.2 MiB 0.55 2490 35711 8852 25144 1715 65.2 MiB 0.47 0.01 4.73051 -1125.66 -4.73051 4.73051 0.26 0.00536421 0.00491253 0.285644 0.261717 46 4691 25 3.44922e+06 3.28753e+06 276332. 2763.32 2.04 1.3096 1.19377 9816 55112 -1 4036 15 1411 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place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 5.16 vpr 64.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65944 14 8 926 934 0 490 100 11 11 121 clb auto 24.8 MiB 0.89 4639 5668 847 4419 402 64.4 MiB 0.16 0.01 4.54815 -31.8355 -4.54815 nan 0.11 0.00261159 0.00232467 0.0841871 0.076513 -1 -1 -1 -1 48 7214 49 4.36541e+06 4.20373e+06 357017. 2950.55 2.66 0.880153 0.750327 12171 71069 -1 6577 19 3324 15359 408061 81134 4.87162 nan -34.7178 -4.87162 0 0 455885. 3767.64 0.01 0.27 0.06 -1 -1 0.01 0.140373 0.125542 + k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 7.63 vpr 66.33 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/home/elgamma8/research/release/vtr-verilog-to-routing 65932 9 19 897 916 0 556 110 12 12 144 clb auto 24.9 MiB 1.39 6252 7474 1266 5720 488 64.4 MiB 0.21 0.01 4.74237 -77.8307 -4.74237 nan 0.14 0.00279294 0.00250543 0.096856 0.0884436 -1 -1 -1 -1 62 10739 47 5.3894e+06 4.41931e+06 554770. 3852.57 3.46 1.02986 0.886777 15940 110000 -1 9728 17 4391 21118 675575 120995 5.20821 nan -84.4166 -5.20821 0 0 687181. 4772.09 0.02 0.31 0.09 -1 -1 0.02 0.132804 0.119663 + k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 5.33 vpr 65.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67420 229 197 1364 1561 1 539 497 16 16 256 io auto 26.1 MiB 0.79 4504 148022 42306 97632 8084 65.8 MiB 0.82 0.01 2.97254 -656.061 -2.97254 2.97254 0.27 0.00449011 0.00417919 0.35606 0.331144 -1 -1 -1 -1 36 7822 26 1.05632e+07 3.82647e+06 638738. 2495.07 1.79 1.11868 1.02782 24820 128426 -1 7098 11 1611 3987 187232 44731 3.15649 3.15649 -738.429 -3.15649 0 0 786978. 3074.13 0.03 0.20 0.10 -1 -1 0.03 0.13819 0.129003 + k6_frac_N10_40nm.xml clma.pre-vpr.blif common 29.41 vpr 89.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 316 62 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 91496 62 82 3672 3754 1 2348 460 20 20 400 clb auto 45.2 MiB 3.88 29602 121160 32274 82250 6636 89.4 MiB 2.62 0.04 7.97523 -360.045 -7.97523 7.97523 0.44 0.0148917 0.0123882 0.964104 0.824254 -1 -1 -1 -1 92 48575 45 1.74617e+07 1.70305e+07 2.37849e+06 5946.23 17.26 5.37402 4.51033 54288 506964 -1 43403 17 15069 65645 2357098 375873 8.16272 8.16272 -366.296 -8.16272 0 0 3.01539e+06 7538.48 0.10 1.23 0.42 -1 -1 0.10 0.552812 0.496854 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66192 64 39 1371 1410 1 541 167 10 10 100 clb auto 25.1 MiB 0.50 3623 18986 4100 13819 1067 64.6 MiB 0.29 0.01 5.32461 -1004.72 -5.32461 5.32461 0.09 0.00311791 0.00279289 0.147968 0.134197 -1 -1 -1 -1 50 5495 30 3.44922e+06 3.44922e+06 295697. 2956.97 2.48 1.15638 1.00085 10016 58256 -1 4877 17 1881 5375 141590 30815 5.49357 5.49357 -1059.83 -5.49357 0 0 379824. 3798.24 0.01 0.11 0.03 -1 -1 0.01 0.0869823 0.0803709 + k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 7.24 vpr 65.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67020 229 197 1362 1559 1 570 496 16 16 256 io auto 25.9 MiB 0.92 5066 137836 36889 92766 8181 65.4 MiB 0.83 0.01 2.91431 -671.379 -2.91431 2.91431 0.27 0.00448988 0.00419125 0.351186 0.326741 -1 -1 -1 -1 36 8862 27 1.05632e+07 3.77258e+06 638738. 2495.07 3.54 1.6488 1.51079 24820 128426 -1 7675 13 1986 5211 265646 63312 3.18697 3.18697 -739.19 -3.18697 0 0 786978. 3074.13 0.03 0.23 0.10 -1 -1 0.03 0.157841 0.146845 + k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 14.52 vpr 77.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 171 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79436 131 114 3421 3535 1 1164 416 16 16 256 clb auto 36.3 MiB 3.47 10474 95088 26501 63930 4657 77.6 MiB 1.19 0.02 7.51043 -4391.12 -7.51043 7.51043 0.27 0.00762209 0.00685426 0.530205 0.466193 -1 -1 -1 -1 56 18313 31 1.05632e+07 9.21587e+06 942187. 3680.42 6.67 2.5886 2.2427 28136 192436 -1 15484 16 5183 22017 710369 128360 7.51944 7.51944 -4543.65 -7.51944 0 0 1.20185e+06 4694.72 0.04 0.54 0.15 -1 -1 0.04 0.344922 0.311996 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 25.26 vpr 82.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84000 10 10 2659 2669 0 1401 305 19 19 361 clb auto 39.5 MiB 4.53 26220 51605 13492 36245 1868 82.0 MiB 1.24 0.02 6.59302 -61.9652 -6.59302 nan 0.39 0.00787717 0.00693136 0.475136 0.405537 -1 -1 -1 -1 90 42829 31 1.55754e+07 1.53598e+07 2.09179e+06 5794.43 14.64 3.52852 2.9687 48131 439069 -1 39158 17 9518 58062 2365838 328796 6.83753 nan -64.8858 -6.83753 0 0 2.60973e+06 7229.16 0.09 1.12 0.37 -1 -1 0.09 0.426225 0.383395 + k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 4.09 vpr 62.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64476 8 63 761 824 0 435 134 10 10 100 clb auto 23.6 MiB 0.77 3999 11420 2063 8488 869 63.0 MiB 0.21 0.01 3.77984 -169.82 -3.77984 nan 0.09 0.00239284 0.00215421 0.0972723 0.0888313 -1 -1 -1 -1 58 6565 28 3.44922e+06 3.39532e+06 342720. 3427.20 1.79 0.648473 0.563539 10608 68480 -1 5918 16 2541 10577 323005 63220 4.22288 nan -188.35 -4.22288 0 0 435638. 4356.38 0.01 0.19 0.06 -1 -1 0.01 0.105677 0.0956385 + k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 13.26 vpr 77.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 167 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79316 20 116 3175 3291 1 1338 303 15 15 225 clb auto 36.2 MiB 3.13 14602 62340 15718 42273 4349 77.5 MiB 1.19 0.02 8.56273 -4519.63 -8.56273 8.56273 0.23 0.00775606 0.00702614 0.536242 0.475888 -1 -1 -1 -1 80 24018 43 9.10809e+06 9.0003e+06 1.12687e+06 5008.33 5.63 2.43667 2.13078 28171 234221 -1 21050 15 6703 26493 1041429 176822 9.09101 9.09101 -4756.62 -9.09101 0 0 1.41774e+06 6301.08 0.04 0.61 0.19 -1 -1 0.04 0.331662 0.300028 + k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 4.57 vpr 63.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65212 14 14 828 842 0 475 99 11 11 121 clb auto 24.1 MiB 0.92 4532 5343 748 4219 376 63.7 MiB 0.15 0.01 4.39029 -57.6027 -4.39029 nan 0.11 0.00248516 0.00222328 0.0774866 0.0708311 -1 -1 -1 -1 52 7728 41 4.36541e+06 3.82647e+06 379421. 3135.71 2.10 0.733439 0.630441 12531 77429 -1 6634 16 3040 13763 383785 71279 4.69105 nan -60.7462 -4.69105 0 0 499620. 4129.09 0.01 0.22 0.06 -1 -1 0.01 0.11464 0.1034 + k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 21.91 vpr 82.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 272 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84436 16 40 2839 2879 0 1511 328 19 19 361 clb auto 39.8 MiB 3.39 23598 55698 13292 40268 2138 82.5 MiB 1.30 0.02 6.48626 -238.484 -6.48626 nan 0.40 0.00882838 0.00732248 0.497678 0.42275 -1 -1 -1 -1 82 38584 40 1.55754e+07 1.46592e+07 1.91630e+06 5308.30 12.46 3.24821 2.7604 46331 403357 -1 35281 17 9680 52085 1891572 294823 6.8403 nan -243.508 -6.8403 0 0 2.40187e+06 6653.38 0.08 1.01 0.33 -1 -1 0.08 0.437512 0.392895 + k6_frac_N10_40nm.xml s298.pre-vpr.blif common 2.88 vpr 62.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63972 4 6 726 732 1 395 74 10 10 100 clb auto 23.1 MiB 0.73 3639 2709 340 2252 117 62.5 MiB 0.07 0.00 6.02711 -48.0055 -6.02711 6.02711 0.08 0.0010205 0.000898899 0.032602 0.0300701 -1 -1 -1 -1 50 5470 24 3.44922e+06 3.44922e+06 295697. 2956.97 0.91 0.327596 0.288129 10016 58256 -1 4992 17 2195 9283 271197 50082 6.42868 6.42868 -51.2874 -6.42868 0 0 379824. 3798.24 0.01 0.18 0.05 -1 -1 0.01 0.106672 0.0965561 + k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 12.83 vpr 86.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88964 29 106 4782 4888 1 1993 385 18 18 324 clb auto 44.6 MiB 2.49 13385 89985 21640 60579 7766 86.9 MiB 1.53 0.02 5.22969 -3570.14 -5.22969 5.22969 0.35 0.00959865 0.008535 0.694501 0.599971 -1 -1 -1 -1 50 21612 42 1.37969e+07 1.34735e+07 1.08879e+06 3360.46 4.74 2.80262 2.39638 34656 222912 -1 19075 14 7130 20879 621675 127526 5.31212 5.31212 -3691.5 -5.31212 0 0 1.40279e+06 4329.61 0.05 0.58 0.17 -1 -1 0.05 0.405856 0.364092 + k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 15.17 vpr 85.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 228 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 88036 38 304 4422 4726 1 1994 570 18 18 324 clb auto 43.2 MiB 2.53 13819 172996 49998 111442 11556 86.0 MiB 2.00 0.03 4.76683 -2916.88 -4.76683 4.76683 0.34 0.00989457 0.00890887 0.808389 0.705884 -1 -1 -1 -1 58 23055 36 1.37969e+07 1.22878e+07 1.26150e+06 3893.53 6.60 3.80943 3.29187 36592 261672 -1 20398 14 6469 17425 591858 126037 4.97859 4.97859 -3048.53 -4.97859 0 0 1.60510e+06 4954.00 0.05 0.58 0.21 -1 -1 0.05 0.422141 0.383308 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.65 vpr 65.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66668 41 35 1006 1041 0 604 160 12 12 144 clb auto 25.4 MiB 1.19 6515 13180 2173 9685 1322 65.1 MiB 0.24 0.01 4.58553 -134.055 -4.58553 nan 0.14 0.00264486 0.00235005 0.0999925 0.09047 -1 -1 -1 -1 64 10841 30 5.3894e+06 4.5271e+06 575115. 3993.85 2.46 0.814658 0.704026 16224 115365 -1 9534 17 3641 17204 511035 92223 4.88481 nan -140.076 -4.88481 0 0 716128. 4973.11 0.02 0.29 0.09 -1 -1 0.02 0.147344 0.133243 + k6_frac_N10_40nm.xml spla.pre-vpr.blif common 20.41 vpr 77.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 216 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78924 16 46 2232 2278 0 1170 278 17 17 289 clb auto 35.3 MiB 2.70 16089 42000 9359 30203 2438 77.1 MiB 0.81 0.02 5.95204 -207.143 -5.95204 nan 0.30 0.00525519 0.00454263 0.288327 0.254222 -1 -1 -1 -1 68 27700 45 1.21262e+07 1.16411e+07 1.30851e+06 4527.71 13.13 2.97958 2.51831 34227 265321 -1 23554 19 8023 43603 1540936 228530 6.17174 nan -217.21 -6.17174 0 0 1.61843e+06 5600.10 0.05 0.86 0.21 -1 -1 0.05 0.373493 0.33657 + k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 3.28 vpr 65.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66580 52 122 1461 1583 1 472 237 10 10 100 clb auto 25.6 MiB 0.57 2690 30290 6635 22073 1582 65.0 MiB 0.30 0.01 4.95966 -1122.48 -4.95966 4.95966 0.09 0.00301411 0.00273882 0.141986 0.129529 -1 -1 -1 -1 46 4786 25 3.44922e+06 3.39532e+06 276332. 2763.32 1.04 0.627009 0.552567 9816 55112 -1 4250 13 1489 3922 122560 29939 5.00101 5.00101 -1209.26 -5.00101 0 0 354105. 3541.05 0.01 0.16 0.04 -1 -1 0.01 0.116497 0.106123 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt index 1ceb9578fa8..9405554e3bd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt @@ -1,20 +1,20 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_40nm.xml alu4.pre-vpr.blif common 8.55 vpr 64.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 97 14 -1 -1 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65700 14 8 926 934 0 517 119 12 12 144 clb auto 25.0 MiB 0.45 4999 8879 1390 6975 514 64.2 MiB 0.20 0.01 5.06551 -38.2757 -5.06551 nan 0.39 0.00158196 0.0012423 0.0754693 0.0645508 -1 -1 -1 -1 44 7317 35 1.8e+06 1.746e+06 394711. 2741.05 4.48 0.974727 0.839816 11464 79652 -1 6325 25 4240 16737 572059 90972 5.28978 nan -37.6562 -5.28978 0 0 511253. 3550.37 0.18 0.38 0.07 -1 -1 0.18 0.171255 0.155339 -k6_N10_40nm.xml apex2.pre-vpr.blif common 8.76 vpr 65.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 114 38 -1 -1 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67348 39 3 1113 1117 0 676 156 13 13 169 clb auto 26.1 MiB 0.64 7918 14821 2638 10792 1391 65.8 MiB 0.42 0.01 5.90722 -17.5854 -5.90722 nan 0.47 0.00428283 0.00360168 0.158762 0.140089 -1 -1 -1 -1 62 12758 32 2.178e+06 2.052e+06 652532. 3861.14 3.88 0.891905 0.775114 15366 127615 -1 12093 24 6108 26868 1139076 155556 5.87992 nan -17.0763 -5.87992 0 0 801739. 4744.02 0.27 0.51 0.12 -1 -1 0.27 0.197711 0.179939 -k6_N10_40nm.xml apex4.pre-vpr.blif common 7.45 vpr 64.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 95 9 -1 -1 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65620 9 19 897 916 0 568 123 12 12 144 clb auto 24.7 MiB 0.49 6597 8358 1363 6514 481 64.1 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/home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 64460 8 63 761 824 0 451 153 12 12 144 clb auto 24.0 MiB 0.36 4546 14468 2684 10639 1145 62.9 MiB 0.26 0.01 4.52309 -198.681 -4.52309 nan 0.49 0.00118271 0.000925606 0.101229 0.0900942 -1 -1 -1 -1 48 7679 49 1.8e+06 1.476e+06 423548. 2941.31 5.16 1.03606 0.893613 11752 84318 -1 6741 20 4041 16856 693280 109643 4.56024 nan -202.106 -4.56024 0 0 546237. 3793.31 0.18 0.27 0.08 -1 -1 0.18 0.102123 0.0923636 -k6_N10_40nm.xml frisc.pre-vpr.blif common 32.16 vpr 76.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 242 20 -1 -1 success v8.0.0-11160-g9b23a7edd-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 78444 20 116 3175 3291 1 1258 378 18 18 324 clb auto 35.6 MiB 1.06 15200 83704 21342 56824 5538 76.6 MiB 1.48 0.02 10.1942 -5061.1 -10.1942 10.1942 1.08 0.00401498 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-07T07:28:02 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 65816 52 122 1461 1583 1 525 279 13 13 169 clb auto 25.2 MiB 0.34 3205 42185 9478 30169 2538 64.3 MiB 0.30 0.01 5.73017 -1218.51 -5.73017 5.73017 0.48 0.00160768 0.00134372 0.0787468 0.0649553 -1 -1 -1 -1 30 5038 31 2.178e+06 1.89e+06 350324. 2072.92 0.92 0.326072 0.27382 12006 67531 -1 4389 18 2512 6814 252428 49786 5.32906 5.32906 -1222.04 -5.32906 0 0 430798. 2549.10 0.15 0.26 0.06 -1 -1 0.15 0.14434 0.131338 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77376 131 114 3421 3535 1 1197 487 18 18 324 clb auto 34.5 MiB 0.88 12132 123047 34177 83673 5197 75.6 MiB 1.33 0.02 7.4606 -4613.61 -7.4606 7.4606 0.33 0.00799169 0.00683063 0.533887 0.467114 -1 -1 -1 -1 52 19935 35 4.608e+06 4.356e+06 1.09957e+06 3393.73 5.62 2.58917 2.24384 27876 225772 -1 16865 24 7619 33177 1410533 212600 7.58148 7.58148 -4794.49 -7.58148 0 0 1.44575e+06 4462.18 0.05 0.80 0.17 -1 -1 0.05 0.430849 0.380256 + k6_N10_40nm.xml ex1010.pre-vpr.blif common 23.62 vpr 79.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 322 10 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81104 10 10 2659 2669 0 1386 342 20 20 400 clb auto 36.8 MiB 1.37 27552 61287 15872 43555 1860 79.2 MiB 1.33 0.02 7.05556 -66.589 -7.05556 nan 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0.02 6.63208 -224.84 -6.63208 nan 0.38 0.00689474 0.00584076 0.390968 0.336886 -1 -1 -1 -1 60 30174 42 5.202e+06 4.77e+06 1.43744e+06 3981.82 14.90 3.32674 2.80555 32910 290117 -1 25425 24 9835 57132 2445755 336723 6.52939 nan -226.972 -6.52939 0 0 1.79849e+06 4981.96 0.06 1.14 0.23 -1 -1 0.06 0.410205 0.363021 + k6_N10_40nm.xml tseng.pre-vpr.blif common 5.72 vpr 64.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 112 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65796 52 122 1461 1583 1 500 286 13 13 169 clb auto 24.6 MiB 0.31 3158 39808 8713 28658 2437 64.3 MiB 0.35 0.01 6.15771 -1276.75 -6.15771 6.15771 0.16 0.00319459 0.00292205 0.149655 0.136345 -1 -1 -1 -1 26 4848 34 2.178e+06 2.016e+06 310759. 1838.81 2.44 1.14951 1.00345 11502 59218 -1 4210 17 2436 6640 243507 54081 5.71256 5.71256 -1266.26 -5.71256 0 0 383419. 2268.75 0.01 0.20 0.05 -1 -1 0.01 0.124909 0.111658 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_hard_block_arch/config/golden_results.txt index f5251301604..a3f5660315d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_hard_block_arch/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu -hard_fpu_arch_timing.xml bfly.v common 6.14 vpr 62.38 MiB 0.04 7212 -1 -1 1 0.05 -1 -1 31024 -1 -1 0 193 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63872 193 64 833 649 1 353 260 24 24 576 io auto 23.4 MiB 3.45 5270 64093 26913 36818 362 62.4 MiB 0.81 0.01 2.985 -1388.77 -2.985 2.985 0.00 0.00780093 0.00749265 0.620138 0.595835 7269 20.6506 1911 5.42898 502 663 292581 62228 1.06129e+06 103149 1.28794e+06 2236.02 4 31350 258969 -1 2.985 2.985 -1374.24 -2.985 -40.8482 -0.0851 0.57 -1 -1 62.4 MiB 0.17 0.727974 0.700185 62.4 MiB -1 0.45 3 -hard_fpu_arch_timing.xml bgm.v common 7.32 vpr 66.50 MiB 0.09 8960 -1 -1 1 0.06 -1 -1 31548 -1 -1 0 257 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68092 257 32 1281 693 1 861 298 38 38 1444 block_FPU auto 27.5 MiB 1.16 16522 99798 44225 55105 468 66.5 MiB 2.09 0.02 2.985 -3185.75 -2.985 2.985 0.00 0.0163994 0.0158581 1.68623 1.6313 22762 26.4674 5833 6.78256 1476 2064 1080688 230994 2.90196e+06 309448 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3345.27 -2.985 -44.0704 -0.0851 1.36 -1 -1 66.5 MiB 0.55 1.97993 1.91753 66.5 MiB -1 1.25 9 -hard_fpu_arch_timing.xml dscg.v common 9.89 vpr 62.29 MiB 0.05 7196 -1 -1 1 0.06 -1 -1 31120 -1 -1 0 129 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63784 129 64 769 585 1 438 197 30 30 900 block_FPU auto 23.5 MiB 6.56 6049 46610 19774 26513 323 62.3 MiB 0.78 0.01 2.985 -1429.54 -2.985 2.985 0.00 0.00752857 0.00722714 0.624964 0.600088 8579 19.6316 2232 5.10755 679 809 410931 90713 1.6779e+06 137533 2.03108e+06 2256.75 4 48532 406344 -1 2.985 2.985 -1485.8 -2.985 -28.1681 -0.0851 0.84 -1 -1 62.3 MiB 0.19 0.729083 0.700795 62.3 MiB -1 0.73 4 -hard_fpu_arch_timing.xml fir.v common 57.40 vpr 62.87 MiB 0.06 7616 -1 -1 1 0.06 -1 -1 31352 -1 -1 28 161 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64376 161 32 993 808 1 515 225 30 30 900 block_FPU auto 23.7 MiB 53.91 6735 58365 23997 33194 1174 62.9 MiB 0.83 0.01 2.985 -1375.04 -2.985 2.985 0.00 0.00723697 0.00689036 0.632448 0.602154 9598 18.6732 2539 4.93969 850 1033 535877 116345 1.6779e+06 201714 2.03108e+06 2256.75 7 48532 406344 -1 2.985 2.985 -1451.27 -2.985 -40.9671 -0.0851 0.85 -1 -1 62.9 MiB 0.26 0.773667 0.737616 62.9 MiB -1 0.73 4 -hard_fpu_arch_timing.xml mm3.v common 3.90 vpr 60.56 MiB 0.04 6828 -1 -1 1 0.04 -1 -1 30604 -1 -1 0 193 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62012 193 32 545 422 1 289 227 21 21 441 io auto 22.0 MiB 1.92 3480 45207 19008 25799 400 60.6 MiB 0.45 0.01 2.985 -824.702 -2.985 2.985 0.00 0.00499164 0.00480908 0.336809 0.324626 4551 15.8021 1192 4.13889 400 400 194592 43581 809148 68766.3 979092. 2220.16 4 24050 197379 -1 2.985 2.985 -811.598 -2.985 -21.7856 -0.0851 0.43 -1 -1 60.6 MiB 0.11 0.404833 0.390442 60.6 MiB -1 0.34 2 -hard_fpu_arch_timing.xml ode.v common 56.49 vpr 64.68 MiB 0.06 8012 -1 -1 1 0.10 -1 -1 34068 -1 -1 135 130 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66228 130 72 1194 1103 1 573 339 19 19 361 io auto 25.2 MiB 53.93 4794 91276 29206 58307 3763 64.7 MiB 0.80 0.01 2.985 -1385.68 -2.985 2.985 0.00 0.0067648 0.00635986 0.538663 0.506206 6805 11.8969 1780 3.11189 1273 1397 405829 81804 653279 378215 795482. 2203.55 9 19802 160939 -1 2.985 2.985 -1384.18 -2.985 -52.6319 -0.0851 0.36 -1 -1 64.7 MiB 0.24 0.695262 0.654681 64.7 MiB -1 0.27 2 -hard_fpu_arch_timing.xml syn2.v common 5.41 vpr 61.97 MiB 0.06 7400 -1 -1 1 0.04 -1 -1 30732 -1 -1 0 161 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63456 161 128 641 490 1 475 293 30 30 900 block_FPU auto 23.2 MiB 1.84 7788 82913 36084 46392 437 62.0 MiB 0.98 0.01 2.985 -1564.05 -2.985 2.985 0.00 0.00836211 0.00808883 0.729693 0.705711 10286 21.7004 2724 5.74684 792 992 508821 108959 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1586.47 -2.985 -16.4184 -0.0851 0.85 -1 -1 62.0 MiB 0.24 0.860584 0.83302 62.0 MiB -1 0.73 4 -hard_fpu_arch_timing.xml syn7.v common 16.79 vpr 112.52 MiB 0.13 9896 -1 -1 1 0.08 -1 -1 32560 -1 -1 0 161 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 115216 161 128 1921 499 1 1728 310 54 54 2916 block_FPU auto 37.0 MiB 2.60 46119 121878 61470 59985 423 112.5 MiB 5.38 0.04 2.985 -8198.94 -2.985 2.985 0.00 0.0373253 0.0362774 4.41941 4.29869 62568 36.2293 15926 9.22177 4142 7176 4439104 909795 6.08571e+06 722046 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8701.55 -2.985 -33.0188 -0.0851 2.79 -1 -1 112.5 MiB 1.75 5.1621 5.02634 112.5 MiB -1 2.86 21 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time num_fpu + hard_fpu_arch_timing.xml bfly.v common 4.85 vpr 63.30 MiB 0.06 7264 -1 -1 1 0.05 -1 -1 30848 -1 -1 0 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64816 193 64 833 649 1 353 260 24 24 576 io auto 23.2 MiB 3.26 5607 63264 26769 36140 355 63.3 MiB 0.43 0.01 2.985 -1370.5 -2.985 2.985 0.00 0.00322632 0.00304499 0.253266 0.239228 -1 -1 -1 -1 7398 21.0170 1937 5.50284 510 675 229921 59199 1.06129e+06 103149 1.28794e+06 2236.02 4 31350 258969 -1 2.985 2.985 -1377.54 -2.985 -40.8482 -0.0851 0.28 -1 -1 63.3 MiB 0.08 0.301441 0.284814 63.3 MiB -1 0.06 3 + hard_fpu_arch_timing.xml bgm.v common 4.12 vpr 66.32 MiB 0.10 8964 -1 -1 1 0.06 -1 -1 31456 -1 -1 0 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67912 257 32 1281 693 1 861 298 38 38 1444 block_FPU auto 27.2 MiB 1.08 16965 98803 43154 54026 1623 66.3 MiB 0.98 0.01 2.985 -3182.68 -2.985 2.985 0.00 0.00568488 0.00537845 0.58516 0.553989 -1 -1 -1 -1 23078 26.8349 5961 6.93140 1605 2215 922235 248459 2.90196e+06 309448 3.35777e+06 2325.33 6 79768 674274 -1 2.985 2.985 -3356.06 -2.985 -44.0704 -0.0851 0.72 -1 -1 66.3 MiB 0.26 0.693055 0.656725 66.3 MiB -1 0.16 9 + hard_fpu_arch_timing.xml dscg.v common 7.96 vpr 62.73 MiB 0.05 7136 -1 -1 1 0.05 -1 -1 31104 -1 -1 0 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64240 129 64 769 585 1 438 197 30 30 900 block_FPU auto 22.9 MiB 6.25 6253 46037 19417 26312 308 62.7 MiB 0.40 0.00 2.985 -1429.58 -2.985 2.985 0.00 0.0029514 0.00277598 0.244908 0.230423 -1 -1 -1 -1 8636 19.7620 2241 5.12815 682 799 306937 82874 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -1494.72 -2.985 -28.2077 -0.0851 0.44 -1 -1 62.7 MiB 0.10 0.294062 0.276714 62.7 MiB -1 0.10 4 + hard_fpu_arch_timing.xml fir.v common 51.65 vpr 63.12 MiB 0.07 7520 -1 -1 1 0.05 -1 -1 31324 -1 -1 28 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64636 161 32 993 808 1 515 225 30 30 900 block_FPU auto 23.5 MiB 49.72 6935 58365 24143 33008 1214 63.1 MiB 0.46 0.00 2.985 -1371.83 -2.985 2.985 0.00 0.00297047 0.00275784 0.264671 0.246456 -1 -1 -1 -1 9669 18.8113 2558 4.97665 860 1036 384010 103019 1.6779e+06 201714 2.03108e+06 2256.75 6 48532 406344 -1 2.985 2.985 -1450.61 -2.985 -40.9671 -0.0851 0.43 -1 -1 63.1 MiB 0.12 0.322443 0.30033 63.1 MiB -1 0.10 4 + hard_fpu_arch_timing.xml mm3.v common 3.05 vpr 61.30 MiB 0.05 6704 -1 -1 1 0.04 -1 -1 30656 -1 -1 0 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62772 193 32 545 422 1 289 227 21 21 441 io auto 21.6 MiB 1.86 3735 46591 19762 26388 441 61.3 MiB 0.27 0.00 2.985 -824.634 -2.985 2.985 0.00 0.00215884 0.00205042 0.152585 0.145074 -1 -1 -1 -1 4594 15.9514 1212 4.20833 428 428 158702 42530 809148 68766.3 979092. 2220.16 5 24050 197379 -1 2.985 2.985 -813.802 -2.985 -21.7856 -0.0851 0.22 -1 -1 61.3 MiB 0.06 0.187066 0.177642 61.3 MiB -1 0.04 2 + hard_fpu_arch_timing.xml ode.v common 53.80 vpr 65.19 MiB 0.08 7820 -1 -1 1 0.10 -1 -1 33844 -1 -1 141 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66756 130 72 1194 1103 1 571 345 19 19 361 io auto 24.7 MiB 52.04 4959 94647 30568 59629 4450 65.2 MiB 0.52 0.01 2.985 -1386.18 -2.985 2.985 0.00 0.00315775 0.00290682 0.254985 0.234605 -1 -1 -1 -1 6658 11.6807 1749 3.06842 1205 1317 282347 70583 653279 391968 795482. 2203.55 10 19802 160939 -1 2.985 2.985 -1383.62 -2.985 -52.7624 -0.0851 0.18 -1 -1 65.2 MiB 0.14 0.337469 0.310228 65.2 MiB -1 0.04 2 + hard_fpu_arch_timing.xml syn2.v common 3.68 vpr 62.52 MiB 0.06 7168 -1 -1 1 0.04 -1 -1 30800 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64016 161 128 641 490 1 475 293 30 30 900 block_FPU auto 23.1 MiB 1.75 8122 82913 36462 46039 412 62.5 MiB 0.55 0.01 2.985 -1569.74 -2.985 2.985 0.00 0.00410324 0.00391013 0.301248 0.287236 -1 -1 -1 -1 10417 21.9768 2760 5.82278 773 969 358629 94838 1.6779e+06 137533 2.03108e+06 2256.75 6 48532 406344 -1 2.985 2.985 -1593.86 -2.985 -16.4581 -0.0851 0.42 -1 -1 62.5 MiB 0.13 0.364652 0.347661 62.5 MiB -1 0.09 4 + hard_fpu_arch_timing.xml syn7.v common 9.24 vpr 112.29 MiB 0.15 9816 -1 -1 1 0.08 -1 -1 32480 -1 -1 0 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 114988 161 128 1921 499 1 1728 310 54 54 2916 block_FPU auto 36.7 MiB 2.42 46604 125022 60723 63851 448 112.3 MiB 2.55 0.03 2.985 -8233.69 -2.985 2.985 0.00 0.011887 0.0112692 1.44511 1.37115 -1 -1 -1 -1 63797 36.9409 16261 9.41575 4499 7822 3665481 927835 6.08571e+06 722046 6.89978e+06 2366.18 7 161598 1383069 -1 2.985 2.985 -8717.74 -2.985 -33.0585 -0.0851 1.48 -1 -1 112.3 MiB 0.90 1.70466 1.62007 112.3 MiB -1 0.40 21 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt index 940651b7efd..7f926449ba3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt @@ -1,8 +1,8 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - soft_fpu_arch_timing.xml bfly.v common 210.98 vpr 342.67 MiB 4.56 167920 -1 -1 60 101.38 -1 -1 88668 -1 -1 6915 193 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 350896 193 64 24163 24227 1 18280 7172 86 86 7396 clb auto 215.1 MiB 4.38 228607 338.0 MiB 65.70 0.55 37.264 -17207 -37.264 37.264 1.34 0.0392839 0.0347954 4.55714 3.73911 378957 160332 446958 44726667 5530437 1.61728e+07 1.58496e+07 1.77311e+07 2397.39 32 40.8797 40.8797 -18421.3 -40.8797 -52.9827 -0.0851 338.0 MiB 11.74 7.82746 6.47064 338.0 MiB 9.25 - soft_fpu_arch_timing.xml bgm.v common 1155.84 vpr 845.20 MiB 24.67 405584 -1 -1 60 700.25 -1 -1 201356 -1 -1 17932 257 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 865488 257 32 61892 61924 1 47401 18221 136 136 18496 clb auto 524.0 MiB 13.72 615364 823.9 MiB 323.25 2.38 36.8643 -42955.7 -36.8643 36.8643 4.76 0.112517 0.0992696 13.1458 10.8406 999640 415440 1173043 116925879 14611095 4.11556e+07 4.11006e+07 4.47194e+07 2417.79 31 40.3221 40.3221 -46134 -40.3221 -78.8244 -0.0851 823.9 MiB 31.31 22.1047 18.3137 823.9 MiB 25.41 - soft_fpu_arch_timing.xml dscg.v common 196.75 vpr 320.08 MiB 4.33 168696 -1 -1 60 99.00 -1 -1 88224 -1 -1 6472 129 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 327760 129 64 22456 22520 1 16929 6665 83 83 6889 clb auto 202.3 MiB 4.08 204998 312.4 MiB 57.65 0.46 36.2779 -14866.4 -36.2779 36.2779 1.18 0.035477 0.0314625 4.20235 3.44545 345906 140160 401628 40518883 4971695 1.50382e+07 1.48343e+07 1.65016e+07 2395.36 25 39.7359 39.7359 -15878 -39.7359 -46.6351 -0.0851 312.4 MiB 10.09 6.77644 5.59725 312.4 MiB 8.39 - soft_fpu_arch_timing.xml fir.v common 184.82 vpr 324.23 MiB 3.29 149532 -1 -1 60 88.59 -1 -1 84480 -1 -1 6576 161 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 332012 161 32 22750 22782 1 17239 6769 84 84 7056 clb auto 204.3 MiB 4.30 208218 318.1 MiB 56.24 0.50 34.5565 -15161.3 -34.5565 34.5565 1.21 0.0355809 0.0315045 4.10389 3.3815 348929 154532 426175 40951738 5214122 1.54118e+07 1.50726e+07 1.69066e+07 2396.05 29 38.5028 38.5028 -16251.6 -38.5028 -52.5409 -0.0851 318.1 MiB 10.72 7.03873 5.80747 318.1 MiB 8.80 - soft_fpu_arch_timing.xml mm3.v common 108.31 vpr 241.86 MiB 1.44 108788 -1 -1 60 47.09 -1 -1 66008 -1 -1 4729 193 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 247668 193 32 16498 16530 1 12703 4954 71 71 5041 clb auto 151.8 MiB 2.99 145106 237.7 MiB 33.84 0.29 36.43 -10714.8 -36.43 36.43 0.78 0.0274769 0.0218478 2.93832 2.40093 249436 111649 305614 29509234 3745335 1.09126e+07 1.08393e+07 1.20254e+07 2385.52 27 39.0748 39.0748 -11430.1 -39.0748 -29.8922 -0.0851 237.7 MiB 7.49 4.92141 4.05414 237.7 MiB 6.12 - soft_fpu_arch_timing.xml ode.v common 83.78 vpr 206.61 MiB 1.49 110724 -1 -1 60 34.93 -1 -1 64700 -1 -1 4046 130 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 211564 130 72 14280 14352 1 10655 4248 66 66 4356 clb auto 132.0 MiB 2.53 126661 203.3 MiB 25.42 0.23 33.6749 -11373.8 -33.6749 33.6749 0.63 0.0217049 0.0192436 2.43891 2.00506 210198 84432 240099 23319963 2968136 9.38847e+06 9.27387e+06 1.03689e+07 2380.36 27 37.9042 37.9042 -12186.3 -37.9042 -62.8382 -0.0851 203.3 MiB 6.05 4.10709 3.41493 203.3 MiB 5.21 - soft_fpu_arch_timing.xml syn2.v common 241.70 vpr 358.75 MiB 4.26 187176 -1 -1 59 121.03 -1 -1 93136 -1 -1 7281 161 -1 -1 success 9b1abd6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2022-11-27T23:54:07 gh-actions-runner-vtr-auto-spawned24 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 367364 161 128 25307 25435 1 19423 7570 88 88 7744 clb auto 224.9 MiB 4.77 234396 352.9 MiB 73.31 0.60 34.8871 -19280.1 -34.8871 34.8871 1.39 0.0405268 0.0357603 4.95119 4.03621 394777 190635 523094 51317356 6505901 1.69521e+07 1.66885e+07 1.85753e+07 2398.67 40 39.0062 39.0062 -20597.8 -39.0062 -37.8125 -0.0851 352.9 MiB 14.07 9.11454 7.49626 352.9 MiB 9.46 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + soft_fpu_arch_timing.xml bfly.v common 218.61 vpr 359.48 MiB 4.91 167836 -1 -1 59 101.39 -1 -1 87824 -1 -1 7340 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 368112 193 64 24210 24274 1 17856 7597 88 88 7744 clb auto 175.2 MiB 7.13 225319 7621897 3212176 4390908 18813 359.5 MiB 72.98 0.60 42.8236 -19565.7 -42.8236 42.8236 0.01 0.0573859 0.0512591 6.89379 5.84877 -1 -1 -1 -1 368191 20.6235 92948 5.20630 130349 394015 30949248 4051469 1.69521e+07 1.68237e+07 1.85753e+07 2398.67 25 418068 3685924 -1 39.6673 39.6673 -18140.5 -39.6673 -54.7919 -0.0851 3.95 -1 -1 359.5 MiB 11.14 10.3565 8.75089 359.5 MiB -1 1.01 + soft_fpu_arch_timing.xml bgm.v common 1037.62 vpr 914.45 MiB 26.28 405280 -1 -1 60 660.49 -1 -1 203444 -1 -1 18904 257 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 936396 257 32 61976 62008 1 46325 19193 140 140 19600 clb auto 419.4 MiB 22.97 596630 25961245 10613132 15303353 44760 914.4 MiB 244.51 2.09 44.1177 -49389.4 -44.1177 44.1177 0.02 0.135011 0.11835 15.2682 12.6503 -1 -1 -1 -1 964345 20.8183 242567 5.23654 339210 1013781 79857050 10583069 4.36493e+07 4.33284e+07 4.74065e+07 2418.70 31 1058292 9395004 -1 41.0998 41.0998 -45704.6 -41.0998 -98.6648 -0.0851 10.18 -1 -1 914.4 MiB 29.50 25.1448 20.7983 914.4 MiB -1 2.72 + soft_fpu_arch_timing.xml dscg.v common 210.26 vpr 342.20 MiB 4.32 168364 -1 -1 60 101.02 -1 -1 87488 -1 -1 6907 129 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 350408 129 64 22611 22675 1 16729 7100 86 86 7396 clb auto 165.7 MiB 6.79 220446 7100940 2996754 4090499 13687 342.2 MiB 66.64 0.56 43.5901 -17476.1 -43.5901 43.5901 0.01 0.0532765 0.0476953 6.30841 5.34291 -1 -1 -1 -1 358090 21.4092 90377 5.40338 124278 375194 30762916 3990281 1.61728e+07 1.58313e+07 1.77311e+07 2397.39 24 399276 3518724 -1 40.7277 40.7277 -16249.7 -40.7277 -52.6715 -0.0851 3.85 -1 -1 342.2 MiB 10.53 9.49355 8.00671 342.2 MiB -1 0.96 + soft_fpu_arch_timing.xml fir.v common 196.96 vpr 343.11 MiB 3.59 149312 -1 -1 59 90.17 -1 -1 83512 -1 -1 6922 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 351344 161 32 22819 22851 1 16866 7115 86 86 7396 clb auto 166.8 MiB 7.04 199474 6915717 2912308 3989791 13618 343.1 MiB 64.14 0.58 40.5059 -17267.1 -40.5059 40.5059 0.01 0.0584 0.048947 6.37642 5.38999 -1 -1 -1 -1 337722 20.0274 85356 5.06173 145553 416282 30884732 4213664 1.61728e+07 1.58657e+07 1.77311e+07 2397.39 32 399276 3518724 -1 37.6419 37.6419 -16015.1 -37.6419 -59.9389 -0.0851 3.71 -1 -1 343.1 MiB 11.94 10.2688 8.65711 343.1 MiB -1 1.07 + soft_fpu_arch_timing.xml mm3.v common 118.95 vpr 275.90 MiB 2.45 108596 -1 -1 59 45.41 -1 -1 58472 -1 -1 5066 193 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 282524 193 32 16754 16786 1 12491 5291 74 74 5476 clb auto 125.9 MiB 4.96 146469 4475536 1818353 2641694 15489 275.9 MiB 42.98 0.37 41.7388 -12064.6 -41.7388 41.7388 0.00 0.0413345 0.0348399 4.58602 3.90866 -1 -1 -1 -1 245866 19.6882 62306 4.98927 109264 305433 22333496 3068702 1.18822e+07 1.16117e+07 1.30782e+07 2388.28 34 295596 2597004 -1 39.2533 39.2533 -11158.6 -39.2533 -32.4114 -0.0851 2.73 -1 -1 275.9 MiB 8.90 7.59926 6.44593 275.9 MiB -1 0.74 + soft_fpu_arch_timing.xml ode.v common 93.35 vpr 240.33 MiB 2.44 110172 -1 -1 59 33.13 -1 -1 65808 -1 -1 4287 130 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 246100 130 72 14367 14439 1 10374 4489 68 68 4624 clb auto 109.3 MiB 4.08 127157 3557929 1403830 2141831 12268 240.3 MiB 33.73 0.32 40.5533 -13292.3 -40.5533 40.5533 0.00 0.0389352 0.033177 4.01164 3.41586 -1 -1 -1 -1 208721 20.1274 52866 5.09797 78139 230635 17685168 2400784 9.98439e+06 9.82624e+06 1.10168e+07 2382.52 26 249588 2188524 -1 36.7396 36.7396 -12330.1 -36.7396 -66.7867 -0.0851 2.36 -1 -1 240.3 MiB 6.75 6.16378 5.23035 240.3 MiB -1 0.60 + soft_fpu_arch_timing.xml syn2.v common 242.74 vpr 375.87 MiB 4.96 186956 -1 -1 59 118.30 -1 -1 91564 -1 -1 7728 161 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 384888 161 128 25405 25533 1 18921 8017 90 90 8100 clb auto 183.0 MiB 7.71 234549 8028217 3391444 4616392 20381 375.9 MiB 75.43 0.64 42.3604 -22270.1 -42.3604 42.3604 0.01 0.0617653 0.0552171 6.77016 5.75861 -1 -1 -1 -1 385300 20.3658 97359 5.14610 136904 413779 32546376 4303699 1.77497e+07 1.7713e+07 1.94391e+07 2399.89 32 437292 3857004 -1 39.1789 39.1789 -20606.8 -39.1789 -41.0113 -0.0851 4.35 -1 -1 375.9 MiB 12.57 11.1492 9.4112 375.9 MiB -1 1.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt index 239e48d4b20..2054d1011a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 311.8 274 967 36 59 0 2 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1735732 22 252 53001 29054 7 24654 1338 89 66 5874 DSP auto 23.51 252822 67.35 0.34 7.26641 -38060.9 -6.26641 2.79561 72.76 0.0922902 0.0742036 19.4784 15.1106 354720 83977 171255 284760839 58437920 0 0 108076000 18399.1 50 7.93667 2.94925 -43306.7 -6.93667 0 0 48.18 30.2955 24.559 65.43 -stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 215.82 36 1583 10 10 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1495008 3 33 48977 39238 1 25960 1639 54 40 2160 LAB auto 60.22 275660 73.3 0.48 76.888 -77679.7 -75.888 76.888 8.1 0.0956007 0.0692678 14.5078 10.6502 370341 90509 238008 217472654 23545267 0 0 39646500 18354.9 28 71.6492 71.6492 -105914 -70.6492 0 0 28.14 21.4905 16.5041 21.42 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2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1755572 227 309 49176 40422 1 28183 2519 85 63 5355 io auto 77.01 312290 91.24 0.69 195.971 -119913 -194.971 195.971 50.83 0.0991588 0.084565 16.0983 11.5643 406195 106821 335442 213233166 16541048 0 0 98440800 18383 22 188.774 188.774 -136523 -187.774 0 0 25.35 22.7627 17.0347 58.18 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 247.43 36 1332 8 149 2 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1629816 3 33 52402 39411 1 28117 1527 73 54 3942 M9K auto 61.3 324276 56.9 0.43 16.9115 -306564 -15.9115 16.9115 21.92 0.115668 0.0811981 14.2927 9.97478 446671 101291 248928 219409565 29355499 0 0 72633900 18425.6 49 17.5096 17.5096 -329353 -16.5096 0 0 36.21 25.5848 19.3127 40 -stratixiv_arch.timing.xml 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VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1076940 18 17 2291 2142 1 1504 119 16 12 192 LAB M9K auto 4.08 10271 0.96 0.01 4.965 -3328.06 -3.965 3.70554 0.09 0.00544208 0.00414461 0.470524 0.35424 14141 4076 9559 7859416 739818 0 0 3350780 17452 20 5.1517 3.94454 -3676.27 -4.1517 0 0 0.88 0.737841 0.591727 0.41 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 240.41 vpr 1.80 GiB 274 1048 36 59 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1886012 22 252 53001 29054 7 22984 1419 89 66 5874 DSP auto 1200.1 MiB 62.75 248316 1021579 298715 629192 93672 1841.8 MiB 68.63 0.51 7.79847 -44076.4 -6.79847 3.16357 0.04 0.165964 0.147061 22.0804 19.3916 348037 15.1637 76678 3.34080 64297 133419 118695520 34142571 0 0 1.08074e+08 18398.6 17 1714760 18504579 -1 8.25872 3.11653 -42832.7 -7.25872 0 0 39.08 -1 -1 1841.8 MiB 30.91 29.1651 25.7894 1841.8 MiB -1 9.35 + stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 221.39 vpr 1.47 GiB 36 1585 10 10 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1847692 131 314 57881 45152 1 32833 2672 73 54 3942 io auto 1361.0 MiB 91.84 318946 2041412 717468 1272847 51097 1720.0 MiB 112.21 1.13 221.943 -77080.5 -220.943 221.943 0.03 0.22642 0.192763 26.2516 22.5036 431464 13.1709 103995 3.17455 107179 331669 90059672 17820477 0 0 7.26311e+07 18424.9 19 1148308 12423798 -1 191.341 191.341 -83524.8 -190.341 0 0 25.61 -1 -1 1725.7 MiB 33.11 36.9562 31.8075 1720.0 MiB -1 6.07 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 56.10 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1212332 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1061.2 MiB 12.53 72155 253216 50624 190930 11662 1175.4 MiB 10.11 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24.86 21.4146 18.4508 2972.2 MiB -1 30.90 + stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 287.28 vpr 3.37 GiB 1107 725 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3531216 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 1059.1 MiB 60.75 187193 1324022 523278 764997 35747 3448.5 MiB 22.39 0.20 12.7682 -23323.6 -11.7682 6.27217 0.13 0.0592033 0.0490591 7.25586 6.09591 231524 27.1328 38817 4.54905 24809 96129 21440863 3812157 0 0 3.84009e+08 18544.0 14 5987112 65598998 -1 12.9996 6.14541 -26165.8 -11.9996 0 0 128.07 -1 -1 3448.5 MiB 8.23 9.74816 8.27075 3448.5 MiB -1 40.93 + stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 104.00 vpr 1.15 GiB 35 739 0 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1206076 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 1055.9 MiB 57.16 84377 244832 62116 178083 4633 1170.5 MiB 9.34 0.14 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0407227 0.0346923 3.31901 2.66458 119256 18.9777 28323 4.50716 18857 88786 20657004 3728094 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 7.35046 7.35046 -45160 -6.35046 0 0 8.61 -1 -1 1170.5 MiB 7.38 5.40776 4.46635 1170.5 MiB -1 1.72 + stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 25.34 vpr 990.99 MiB 35 78 0 8 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1014772 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 952.6 MiB 5.77 10189 9390 1103 7334 953 991.0 MiB 0.58 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00761951 0.00626889 0.283964 0.242647 14035 9.71280 3656 2.53010 3331 8155 2407464 497474 0 0 3.34790e+06 17437.0 10 54372 558374 -1 5.45077 4.46245 -3957.23 -4.45077 0 0 1.88 -1 -1 991.0 MiB 0.85 0.560139 0.494736 991.0 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt index afdc3a7228c..cd660523188 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt @@ -1,23 +1,23 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 3434.92 136 21492 0 1848 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 9760656 100 36 504627 490068 5 200916 23477 255 189 48195 M9K auto 700.76 -1 1504.23 11.74 8.0573 -1.40572e+06 -8.0 5.6189 177.19 1.11051 0.713981 193.057 125.871 5385844 441201 1322987 933414169 132816309 0 0 8.91222e+08 18492.0 12 9.0 6.19052 -1.94741e+06 -8.20679 0 0 180.15 240.444 164.718 597.95 -stratixiv_arch.timing.xml mes_noc_stratixiv_arch_timing.blif common 5178.68 5 23760 0 800 0 8 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 9098808 3 2 577696 547568 17 345674 24573 193 143 27599 LAB auto 1364.30 -1 2826.61 26.29 11.27 -2.97906e+06 -10.27 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Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5971932 264 588 355537 274786 1 218574 15265 150 111 16650 LAB auto 395.29 -1 2053.18 13.33 866.716 -868475 -865.716 866.716 59.74 0.852057 0.609981 129.74 93.1704 3069575 1205817 3821898 2625594594 200491408 0 0 3.08278e+08 18515.2 43 857.427 857.427 -1.06208e+06 -856.427 0 0 316.47 210.711 159.272 198.99 -stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 3101.89 451 14725 0 260 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5492144 239 212 302755 300220 1 184812 15436 153 113 17289 LAB auto 720.50 -1 1616.14 9.31 10.5604 -686489 -9.56037 10.5604 74.77 0.872497 0.578117 133.503 89.1183 4841206 557658 2081616 1599598820 153094223 0 0 3.20293e+08 18525.8 65 10.8439 10.8439 -962235 -9.84391 0 0 295.90 247.633 179.457 246.21 -stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 2191.28 162 9680 132 600 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5522328 94 68 331744 255478 1 156536 10574 169 125 21125 DSP auto 343.39 -1 889.63 8.09 8.69851 -566131 -7.69851 8.69851 109.08 1.20758 0.935206 125.961 91.4 2616338 369944 775061 1257487865 245527477 0 0 3.91827e+08 18548.0 18 9.26921 9.26921 -849140 -8.26921 0 0 268.77 166.745 126.095 403.77 -stratixiv_arch.timing.xml minres_stratixiv_arch_timing.blif common 2432.68 229 7818 78 1459 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 6819488 129 100 316623 257480 3 183470 9585 225 167 37575 M9K auto 381.42 -1 827.15 4.18 7.64836 -339381 -6.64836 4.9105 204.80 0.749549 0.556493 143.207 105.834 2913341 385664 736714 785197968 116848060 0 0 6.95909e+08 18520.5 15 8.94983 6.16821 -534628 -7.94983 0 0 140.68 181.401 138.116 657.28 -stratixiv_arch.timing.xml stap_qrd_stratixiv_arch_timing.blif common 2706.95 150 15899 75 553 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 4970724 68 82 284051 234177 1 144423 16677 158 117 18486 LAB auto 315.03 -1 1579.67 9.66 6.97142 -374581 -5.97142 6.97142 129.35 0.569765 0.447079 154.643 112.186 2649637 299124 721610 828065173 126669656 0 0 3.42752e+08 18541.2 16 7.53291 7.53291 -591536 -6.53291 0 0 196.94 202.379 151.111 327.94 -stratixiv_arch.timing.xml openCV_stratixiv_arch_timing.blif common 2406.79 208 7145 213 785 40 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5944316 106 102 279132 212552 1 168784 8391 209 155 32395 DSP auto 412.15 -1 692.21 4.57 10.0969 -598047 -9.09688 10.0969 169.15 0.727472 0.55054 116.775 85.9459 3370536 460982 1021226 1164410289 196307724 0 0 6.00287e+08 18530.2 43 10.8759 10.8759 -859659 -9.87586 0 0 300.88 195.6 151.617 643.04 -stratixiv_arch.timing.xml bitonic_mesh_stratixiv_arch_timing.blif common 3396.68 119 7239 85 1664 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 6841728 87 32 233978 190746 1 146198 9107 242 179 43318 M9K auto 559.97 -1 1127.28 6.90 12.1144 -1.51589e+06 -11.1144 12.1144 221.34 1.21887 0.860698 175.663 128.302 4588292 456078 1491126 1548811766 242407085 0 0 8.01751e+08 18508.5 18 12.7209 12.7209 -1.86107e+06 -11.7209 0 0 304.05 240.372 183.004 932.96 -stratixiv_arch.timing.xml segmentation_stratixiv_arch_timing.blif common 1763.17 441 6937 15 481 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 3718544 72 369 178312 137832 1 108345 7874 136 101 13736 M9K auto 185.42 -1 1080.57 6.58 851.19 -389269 -850.19 851.19 54.10 0.501823 0.365842 89.6848 65.6521 1630334 475504 1473018 1179152997 94653229 0 0 2.53781e+08 18475.6 24 837.727 837.727 -515162 -836.727 0 0 172.25 126.618 95.8909 165.68 -stratixiv_arch.timing.xml SLAM_spheric_stratixiv_arch_timing.blif common 884.93 479 5366 37 0 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 2821524 323 156 140638 111354 1 78004 5882 95 70 6650 LAB auto 212.42 -1 396.74 2.66 78.3162 -375071 -77.3162 78.3162 29.78 0.331472 0.280128 50.9109 37.3753 1612271 249303 845612 794012785 90253580 0 0 1.22432e+08 18410.9 20 77.2015 77.2015 -414731 -76.2015 0 0 107.22 71.3949 54.5921 73.43 -stratixiv_arch.timing.xml des90_stratixiv_arch_timing.blif common 1446.48 117 4233 44 860 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 4013740 85 32 138853 110549 1 87969 5254 171 127 21717 M9K auto 282.94 -1 444.78 4.09 11.4477 -770173 -10.4477 11.4477 81.79 0.834987 0.625928 85.2758 63.1207 2230768 283309 861480 732978149 114988063 0 0 4.02762e+08 18545.9 57 12.2596 12.2596 -928196 -11.2596 0 0 239.80 184.596 144.573 274.03 -stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 582.49 77 3123 89 136 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 2813800 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 85.55 -1 117.60 0.94 7.88637 -71260.7 -6.88637 5.1277 63.82 0.276687 0.214216 36.7265 27.9182 749667 110099 187821 250313976 47472949 0 0 2.28642e+08 18462.7 29 8.05602 5.58124 -112257 -7.05602 0 0 57.52 54.3082 43.3457 181.77 -stratixiv_arch.timing.xml sparcT1_core_stratixiv_arch_timing.blif common 791.54 310 4000 1 128 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 2316624 173 137 92814 91975 1 60944 4439 82 61 5002 LAB auto 250.21 -1 292.72 2.97 7.69498 -527081 -6.69498 7.69498 18.58 0.484786 0.335188 47.2008 32.1521 1293421 213067 742140 562420350 57380434 0 0 9.19900e+07 18390.6 34 8.28235 8.28235 -655221 -7.28235 0 0 115.19 81.8934 60.2717 57.04 -stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 563.33 506 3246 76 113 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 2744440 172 334 127090 94090 3 61732 3941 129 96 12384 DSP auto 81.66 -1 117.95 0.82 7.16483 -51326.5 -6.16483 3.19482 60.85 0.192659 0.134604 27.0351 19.0385 580833 129881 199489 173990883 19816534 0 0 2.28642e+08 18462.7 24 7.39025 3.26548 -71146 -6.39025 0 0 30.31 39.7283 29.6661 189.20 -stratixiv_arch.timing.xml cholesky_mc_stratixiv_arch_timing.blif common 822.42 262 4765 59 444 16 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 3139848 111 151 140214 108592 1 66751 5546 125 93 11625 M9K auto 127.78 -1 257.07 1.60 6.64077 -177966 -5.64077 6.64077 58.12 0.325199 0.243045 52.6464 38.4057 1180344 153949 342701 556413254 117858039 0 0 2.14514e+08 18452.8 16 6.97434 6.97434 -288912 -5.97434 0 0 137.35 70.3563 53.4736 154.69 -stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 13033.91 319 61450 240 2535 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 19989968 62 257 1374456 930989 2 679981 64544 317 235 74495 M9K auto 1100.54 -1 8835.77 82.27 10.0391 -1.7189e+06 -9.03907 8.60202 365.26 2.32644 1.66281 526.865 374.58 12211049 1565796 2766063 3167014806 442243815 0 0 1.38708e+09 18619.7 36 10.5916 9.11279 -2.47963e+06 -9.59162 0 0 683.17 734.274 541.813 1479.59 -stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 12379.71 385 32503 0 1331 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 14041524 353 32 1446409 1087537 2 848902 34220 225 167 37575 LAB auto 800.01 -1 8905.24 34.75 8.79365 -825548 -7.79365 8.79365 142.25 1.97467 1.46614 404.675 290.131 10667459 2667357 3983335 3475083060 437778344 0 0 6.95909e+08 18520.5 221 13.7216 13.7216 -1.26214e+06 -12.7216 0 0 1592.57 1348.11 1039.94 533.31 -stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 9437.46 373 16571 116 5040 16 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 18756984 178 195 663067 568001 2 413013 22116 430 319 137170 M9K auto 1116.15 -1 3180.91 12.00 22.8182 -3.14594e+06 -21.8182 7.83218 755.18 1.81031 1.31598 435.301 309.645 17977564 1024239 1942686 3346505372 605233804 0 0 2.57820e+09 18795.7 28 23.0087 9.77401 -5.72551e+06 -22.0087 0 0 898.40 569.516 420.296 2890.28 -stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 9296.08 1891 33629 3 506 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 12985200 815 1076 764693 760412 1423 416439 36029 280 207 57960 io auto 1621.50 -1 5111.77 25.16 15.6661 -3.78262e+06 -14.6661 4.89313 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3240872 111 151 140214 108592 1 66275 5543 125 93 11625 M9K auto 1990.1 MiB 150.70 788106 6330929 2486828 3764499 79602 2999.6 MiB 253.72 2.29 6.96286 -206320 -5.96286 6.96286 0.08 0.604795 0.483861 67.9341 55.4074 1136243 17.1454 244932 3.69592 141963 302339 243323807 67066242 0 0 2.14511e+08 18452.6 16 3364308 36745094 -1 7.39694 7.39694 -298154 -6.39694 0 0 72.92 -1 -1 2999.6 MiB 76.78 90.4375 75.2977 2999.6 MiB -1 19.73 + stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 12532.52 vpr 19.50 GiB 319 61499 240 2535 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 20448160 62 257 1374456 930989 2 664817 64593 317 235 74495 M9K auto 11400.2 MiB 1506.39 10830328 216389546 87578779 128174025 636742 16624.7 MiB 9335.15 60.39 9.32838 -1.81224e+06 -8.32838 8.21814 0.67 3.53075 2.88911 658.938 543.734 11749927 17.6766 2324437 3.49689 1382377 2282905 1372376586 322363776 0 0 1.38707e+09 18619.7 14 21381670 236483135 -1 9.87707 8.61989 -2.31232e+06 -8.87707 0 0 452.96 -1 -1 16912.8 MiB 513.06 803.854 668.88 16624.7 MiB -1 182.00 + stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 11466.83 vpr 14.34 GiB 385 35914 0 1331 0 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 15035956 353 32 1446409 1087537 2 802897 37631 236 175 41300 LAB auto 8407.8 MiB 1414.82 8069197 81976111 30515078 50803021 658012 10893.1 MiB 8936.33 46.36 8.82853 -897986 -7.82853 8.82853 0.36 2.99104 2.55745 469.647 390.463 9365241 11.6644 2162474 2.69335 1742182 2571548 800029867 152528004 0 0 7.64522e+08 18511.4 17 11894042 131060469 -1 10.6871 10.6871 -1.2059e+06 -9.68713 0 0 251.35 -1 -1 12829.2 MiB 343.34 618.45 518.897 10893.1 MiB -1 88.27 + stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 6830.28 vpr 19.49 GiB 373 16678 116 5040 16 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 20438632 178 195 663067 568001 2 406083 22223 430 319 137170 M9K auto 5700.5 MiB 1520.96 15354107 51862695 21830000 29930794 101901 19959.6 MiB 3339.60 16.18 26.6172 -3.23472e+06 -25.6172 8.81163 0.77 2.93237 2.42302 522.353 431.036 16386901 40.3553 3026953 7.45434 917037 1739755 1410990275 326533180 0 0 2.57820e+09 18795.6 12 39390806 435738327 -1 24.6154 10.5061 -5.75347e+06 -23.6154 0 0 796.86 -1 -1 19959.6 MiB 463.24 629.617 524.068 19959.6 MiB -1 347.65 + stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 8297.71 vpr 12.67 GiB 1891 33747 3 506 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 13287316 815 1076 764693 760412 1423 413569 36147 280 207 57960 io auto 6871.8 MiB 2181.98 6321041 78292272 33005860 44758558 527854 11353.1 MiB 4930.46 30.53 17.7516 -4.16163e+06 -16.7516 4.89119 0.50 2.84274 2.25204 405.671 323.281 7527876 18.5260 1630241 4.01199 988164 3143557 705151553 127852079 0 0 1.07374e+09 18525.6 21 16684552 184042692 -1 17.843 5.02145 -4.80984e+06 -16.843 0 0 348.44 -1 -1 11473.0 MiB 340.62 553.004 447.083 11353.1 MiB -1 132.10 + stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6343.70 vpr 11.23 GiB 399 31093 112 1175 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 11773496 85 185 721554 630079 28 405002 32781 220 163 35860 LAB auto 6475.4 MiB 1009.92 5178404 84458444 33598600 50279421 580423 8859.9 MiB 4446.05 26.77 8.14669 -688925 -7.14669 5.20564 0.30 3.77527 2.96208 508.454 405.77 6249071 15.4486 1362456 3.36819 825418 1759906 637573300 144402801 0 0 6.64232e+08 18522.9 14 10351778 113707977 -1 8.89873 5.39961 -915798 -7.89873 0 0 217.81 -1 -1 10398.6 MiB 257.32 623.547 504.372 8859.9 MiB -1 73.73 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt index 923229b832d..92b4e95ed1c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt @@ -1,6 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 26.57 vpr 82.09 MiB -1 -1 4.09 45804 3 0.98 -1 -1 40164 -1 -1 112 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84056 236 305 3195 3007 1 1538 660 19 19 361 io auto 44.6 MiB 1.97 12550 82.1 MiB 2.18 0.03 4.23319 -2592.08 -4.23319 4.23319 0.09 0.00734041 0.00664649 0.800573 0.722627 22506 5369 14230 2808527 640885 1.72706e+07 8.96013e+06 2.90560e+06 8048.76 16 4.88723 4.88723 -2997.25 -4.88723 -6.66982 -0.193384 82.1 MiB 1.04 1.20892 1.10479 82.1 MiB 1.24 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 26.32 vpr 82.26 MiB -1 -1 3.75 46008 3 0.93 -1 -1 40016 -1 -1 120 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84232 236 305 3195 3007 1 1534 668 19 19 361 io auto 45.3 MiB 2.86 12092 82.3 MiB 2.03 0.03 4.31218 -2553.6 -4.31218 4.31218 0.07 0.00696218 0.00631702 0.765105 0.691642 19341 4478 11708 2097942 457216 1.72706e+07 9.39128e+06 2.71656e+06 7525.11 12 4.99952 4.99952 -3010.14 -4.99952 0 0 82.3 MiB 0.83 1.12422 1.027 82.3 MiB 1.15 - k6_frac_N10_mem32K_40nm.xml raygentop.v common 26.02 vpr 77.67 MiB -1 -1 4.82 49248 8 1.50 -1 -1 41880 -1 -1 116 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 79536 235 305 2594 2755 1 1443 663 19 19 361 io auto 39.9 MiB 2.23 11448 77.7 MiB 1.82 0.03 4.41088 -2430.87 -4.41088 4.41088 0.08 0.00649293 0.00576414 0.647429 0.579732 18768 3833 11059 1989583 427191 1.72706e+07 9.1757e+06 2.71663e+06 7525.28 11 5.29026 5.29026 -2756.74 -5.29026 -8.67533 -0.17036 77.7 MiB 0.75 0.955384 0.866802 77.7 MiB 1.18 - k6_N10_mem32K_40nm.xml raygentop.v common 25.03 vpr 76.39 MiB -1 -1 4.72 48856 8 1.50 -1 -1 41792 -1 -1 165 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78228 235 305 2594 2755 1 1461 712 19 19 361 io auto 38.7 MiB 0.95 12269 76.4 MiB 1.85 0.03 4.59709 -2576.68 -4.59709 4.59709 0.09 0.00642268 0.00566871 0.591253 0.53058 18465 7376 21416 6225690 1224003 1.72706e+07 1.18165e+07 2.57233e+06 7125.57 19 4.96959 4.96959 -2849.65 -4.96959 -0.0066982 -0.0066982 76.4 MiB 1.84 0.995979 0.901619 76.4 MiB 1.10 - hard_fpu_arch_timing.xml raygentop.v common 389.64 vpr 322.97 MiB -1 -1 36.07 182560 40 111.52 -1 -1 74952 -1 -1 3776 235 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 330724 235 305 20496 20801 1 8995 4316 68 68 4624 clb auto 158.1 MiB 4.44 176765 323.0 MiB 49.61 0.36 22.409 -30564.1 -22.409 22.409 1.35 0.0561504 0.0436831 6.55008 5.20912 249819 53589 173978 17781644 1967620 9.87441e+06 8.65503e+06 1.89440e+07 4096.88 23 25.1849 25.1849 -37219.3 -25.1849 -0.1702 -0.0851 323.0 MiB 8.47 9.92861 8.04481 323.0 MiB 16.99 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 21.07 vpr 83.23 MiB -1 -1 4.77 42300 3 0.69 -1 -1 37768 -1 -1 119 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85232 236 305 3199 3011 1 1524 667 19 19 361 io auto 42.1 MiB 2.01 12616 262837 90033 158763 14041 83.2 MiB 2.05 0.03 4.49369 -2806.86 -4.49369 4.49369 0.00 0.00966118 0.00895805 0.835281 0.769463 -1 -1 -1 -1 21210 13.9908 5587 3.68536 5140 14335 1484939 342866 1.72706e+07 9.33739e+06 3.48716e+06 9659.72 17 58198 611635 -1 4.74754 4.74754 -2972.19 -4.74754 -0.452504 -0.0215478 0.56 -1 -1 83.2 MiB 0.75 1.24852 1.15404 83.2 MiB -1 0.11 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 22.29 vpr 83.17 MiB -1 -1 4.81 42876 3 0.69 -1 -1 37760 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85164 236 305 3199 3011 1 1520 677 19 19 361 io auto 42.5 MiB 2.79 12380 244299 81189 149577 13533 83.2 MiB 1.87 0.03 4.65817 -2859.2 -4.65817 4.65817 0.00 0.00866299 0.00799175 0.759534 0.696955 -1 -1 -1 -1 18640 12.3280 4948 3.27249 4102 10444 795414 174592 1.72706e+07 9.87633e+06 3.27351e+06 9067.88 17 54883 545335 -1 4.90067 4.90067 -2957.57 -4.90067 0 0 0.53 -1 -1 83.2 MiB 0.52 1.13157 1.04213 83.2 MiB -1 0.11 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 21.25 vpr 78.37 MiB -1 -1 5.87 46604 8 0.98 -1 -1 37824 -1 -1 117 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80252 235 305 2600 2761 1 1433 664 19 19 361 io auto 37.8 MiB 1.95 11898 272794 88380 167366 17048 78.4 MiB 1.97 0.03 5.27944 -2662.29 -5.27944 5.27944 0.00 0.00791855 0.00732648 0.794863 0.732871 -1 -1 -1 -1 18276 12.8163 4830 3.38710 3901 10985 836374 182612 1.72706e+07 9.2296e+06 3.27351e+06 9067.88 11 53999 544685 -1 5.16248 5.16248 -2765.43 -5.16248 -4.72457 -0.168146 0.53 -1 -1 78.4 MiB 0.41 1.06143 0.98183 78.4 MiB -1 0.10 + k6_N10_mem32K_40nm.xml raygentop.v common 19.60 vpr 77.53 MiB -1 -1 6.09 46284 8 0.99 -1 -1 37804 -1 -1 193 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 79388 235 305 2600 2761 1 1403 740 19 19 361 io clb auto 36.9 MiB 1.01 12379 261650 87521 161400 12729 77.5 MiB 1.85 0.03 5.29995 -2784.97 -5.29995 5.29995 0.00 0.0080991 0.00750467 0.669483 0.615668 -1 -1 -1 -1 17144 12.2808 4591 3.28868 6555 20515 2226044 437383 1.72706e+07 1.33255e+07 3.09093e+06 8562.13 21 47590 507115 -1 5.08294 5.08294 -2786.98 -5.08294 -12.7904 -0.246958 0.50 -1 -1 77.5 MiB 0.79 1.07204 0.98586 77.5 MiB -1 0.10 + hard_fpu_arch_timing.xml raygentop.v common 237.56 vpr 393.52 MiB -1 -1 40.57 186152 41 66.23 -1 -1 72764 -1 -1 3955 235 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 402960 235 305 20447 20752 1 8685 4495 70 70 4900 clb auto 132.2 MiB 4.43 172483 4046324 1736449 2271923 37952 393.5 MiB 31.14 0.27 27.318 -38433 -27.318 27.318 0.02 0.0410618 0.0358058 4.84871 4.07471 -1 -1 -1 -1 244983 28.2271 61861 7.12766 48213 160239 16322926 1805170 1.04337e+07 9.0653e+06 2.44008e+07 4979.75 20 487536 5108624 -1 25.2535 25.2535 -40276.6 -25.2535 -0.3404 -0.0851 6.81 -1 -1 393.5 MiB 5.85 6.95088 5.84398 393.5 MiB -1 1.57 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt index dfbbf4d2833..d459ca13114 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k4_n4_v7_bidir.xml dsip.blif common 68.50 vpr 103.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 106276 229 197 1815 2012 1 1190 816 29 29 841 io auto 29.4 MiB 0.37 11620 103.8 MiB 2.16 0.04 6.8651 -1709.92 -6.8651 6.8651 1.11 0.00477376 0.00418939 0.496235 0.436882 15380 5691 17014 6186367 416954 2.187e+07 1.17e+07 -1 -1 13 8.65812 8.65812 -2235.57 -8.65812 0 0 103.8 MiB 1.40 0.704858 0.627073 103.8 MiB 9.22 - k4_n4_v7_bidir.xml elliptic.blif common 106.33 vpr 146.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 996 131 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 150432 131 114 4855 4969 1 2150 1241 34 34 1156 clb auto 49.8 MiB 0.89 31903 146.9 MiB 4.39 0.05 19.6462 -11430.7 -19.6462 19.6462 1.76 0.0110664 0.00959187 0.986311 0.840225 41276 10265 46782 11439440 713310 3.072e+07 2.988e+07 -1 -1 18 23.458 23.458 -14291.4 -23.458 0 0 146.9 MiB 3.13 1.66205 1.43613 146.9 MiB 13.74 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k4_n4_v7_bidir.xml dsip.blif common 25.73 vpr 128.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 443 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 131904 229 197 1815 2012 1 1190 869 29 29 841 io auto 27.9 MiB 0.38 11808 386354 130262 246701 9391 128.8 MiB 2.12 0.03 8.26026 -2002.89 -8.26026 8.26026 0.00 0.00584398 0.00529802 0.564955 0.515177 -1 -1 -1 -1 14837 12.4786 3857 3.24390 5280 18595 4288015 314127 2.187e+07 1.329e+07 -1 -1 12 141714 3348831 -1 10.3649 10.3649 -2489.23 -10.3649 0 0 1.96 -1 -1 128.8 MiB 0.87 0.747411 0.681765 128.8 MiB -1 0.72 + k4_n4_v7_bidir.xml elliptic.blif common 38.86 vpr 178.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 182996 131 114 4855 4969 1 2112 1268 34 34 1156 clb auto 44.7 MiB 0.81 31400 563788 196591 359179 8018 178.7 MiB 4.04 0.04 22.2892 -11723.6 -22.2892 22.2892 0.01 0.0103809 0.00927175 1.12003 0.959229 -1 -1 -1 -1 40056 18.9749 10269 4.86452 9570 44105 8008892 526134 3.072e+07 3.069e+07 -1 -1 19 194754 4643496 -1 27.7541 27.7541 -14616.1 -27.7541 0 0 2.77 -1 -1 178.7 MiB 1.77 1.60391 1.38102 178.7 MiB -1 1.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt index 14bf14c7160..35eb454cdb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 70.22 vpr 81.37 MiB -1 -1 5.14 48880 13 1.49 -1 -1 41348 -1 -1 256 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 83320 235 305 3025 3186 1 2385 803 26 26 676 mult_36 auto 37.3 MiB 0.66 17792 81.4 MiB 2.66 0.04 4.07341 -1915.66 -4.07341 4.07341 0.18 0.00727701 0.00657869 0.640946 0.566051 26395 7994 25461 5630378 1530085 3.88769e+06 1.79395e+06 7.17610e+06 10615.5 16 4.6849 4.6849 -2313.21 -4.6849 -34.8532 -0.36083 81.4 MiB 1.99 1.02377 0.915351 81.4 MiB 9.69 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 27.97 vpr 90.66 MiB -1 -1 6.04 46344 13 0.96 -1 -1 37412 -1 -1 258 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 92832 235 305 3050 3211 1 2409 805 26 26 676 mult_36 auto 35.0 MiB 0.56 18548 318960 106153 197804 15003 90.7 MiB 2.80 0.04 4.63435 -2030.57 -4.63435 4.63435 0.00 0.00954579 0.00885942 0.841339 0.769886 -1 -1 -1 -1 27327 11.3768 12604 5.24729 7556 24511 3145050 770465 3.88769e+06 1.80175e+06 7.17610e+06 10615.5 17 154908 1423382 -1 4.95816 4.95816 -2400.04 -4.95816 -4.91839 -0.302506 2.27 -1 -1 90.7 MiB 1.13 1.2245 1.12379 90.7 MiB -1 0.68 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt index 5261852db4a..b062cee3d4b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 18.21 vpr 75.18 MiB -1 -1 4.72 49096 13 1.40 -1 -1 41408 -1 -1 256 235 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 76984 235 305 3025 3186 1 2385 803 26 26 676 mult_36 auto 37.5 MiB 0.60 17960 75.2 MiB 2.54 0.04 4.07552 -1959 -4.07552 4.07552 0.15 0.00692304 0.00628985 0.617946 0.554056 27960 9568 30531 5163874 1503608 3.88769e+06 1.79395e+06 3.89335e+06 5759.39 21 4.86688 4.86688 -2303.87 -4.86688 -33.7771 -0.30051 75.2 MiB 1.82 1.04903 0.946401 75.2 MiB 4.50 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 13.99 vpr 76.51 MiB -1 -1 6.07 46336 13 0.97 -1 -1 37404 -1 -1 258 235 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78348 235 305 3050 3211 1 2409 805 26 26 676 mult_36 auto 35.1 MiB 0.56 18006 296502 98971 182176 15355 76.5 MiB 2.50 0.04 4.59638 -1990.69 -4.59638 4.59638 0.00 0.00877395 0.00813036 0.734286 0.67238 -1 -1 -1 -1 27613 11.4958 13095 5.45171 8944 28960 2940446 834435 3.88769e+06 1.80175e+06 3.89335e+06 5759.39 15 97004 733416 -1 4.97823 4.97823 -2391.62 -4.97823 -8.61767 -0.284072 1.15 -1 -1 76.5 MiB 0.93 1.05837 0.970896 76.5 MiB -1 0.34 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt index 067a8cc5230..e2eda83b3b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1504.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 2859008 42 35 119888 86875 1 51143 3418 129 96 12384 DSP auto 85.58 583323 119.39 0.71 7.89477 -209772 -7.89477 7.89477 208.83 0.200591 0.17182 32.4665 25.7145 744976 -1 -1 -1 -1 0 0 2.28642e+08 18462.7 33 8.25962 8.25962 -264487 -8.25962 0 0 57.37 50.95 41.9616 169.27 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 966.64 vpr 2.85 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2990436 42 35 119888 86875 1 50848 3434 129 96 12384 DSP auto 1744.6 MiB 111.96 593082 3188765 1210302 1953134 25329 2920.3 MiB 129.15 1.03 7.82707 -223897 -7.82707 7.82707 0.07 0.354575 0.31728 46.7861 40.8662 -1 -1 -1 -1 760648 14.9737 161961 3.18827 105791 178983 117012215 31658104 0 0 2.28639e+08 18462.4 15 3593250 39165143 -1 8.06159 8.06159 -257707 -8.06159 0 0 77.93 -1 -1 2920.3 MiB 38.69 62.4048 54.9606 2920.3 MiB -1 22.61 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt index c1dc0afb50f..ad32242d902 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt @@ -1,41 +1,41 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_n4_v7_bidir.xml alu4.blif common 14.52 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 477 14 -1 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68932 14 8 1536 1544 0 1088 499 24 24 576 clb auto 27.1 MiB 0.35 13713 125113 37636 85702 1775 67.3 MiB 0.82 0.01 14.0421 -101.788 -14.0421 nan 0.88 0.00340676 0.00297335 0.220724 0.194701 28 19990 27 1.452e+07 1.431e+07 -1 -1 8.80 1.43324 1.22449 21174 279108 -1 19228 18 7062 27087 2139856 196285 17.1451 nan -119.753 -17.1451 0 0 -1 -1 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28.1 MiB 0.20 9992 137732 37830 95961 3941 67.7 MiB 0.64 0.01 13.4033 -2671.54 -13.4033 13.4033 0.70 0.00195077 0.00171362 0.173386 0.151149 24 14332 21 1.323e+07 1.245e+07 -1 -1 6.54 1.33161 1.13731 18402 227975 -1 13634 22 6342 21307 1309693 133684 15.9009 15.9009 -3236.59 -15.9009 0 0 -1 -1 0.30 0.48 0.13 -1 -1 0.30 0.194956 0.169766 -k4_n4_v7_bidir.xml dsip.blif common 17.59 vpr 67.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69036 229 197 1815 2012 1 1190 816 29 29 841 io auto 27.7 MiB 0.36 11545 347617 108721 229249 9647 67.4 MiB 1.72 0.02 7.21771 -1868.83 -7.21771 7.21771 1.36 0.00518736 0.00474124 0.503797 0.459535 18 18641 50 2.187e+07 1.17e+07 -1 -1 9.53 1.95931 1.76098 25794 279159 -1 15915 19 6571 20190 1355499 141050 8.71824 8.71824 -2334.27 -8.71824 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2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 120424 10 10 4608 4618 0 3617 1527 41 41 1681 clb auto 48.8 MiB 1.07 44970 713436 251975 459721 1740 117.6 MiB 5.30 0.06 23.5124 -229.462 -23.5124 nan 3.51 0.00978634 0.00856467 0.959665 0.808442 28 68638 30 4.563e+07 4.521e+07 -1 -1 48.39 4.23166 3.50982 61362 838935 -1 63940 21 25222 100656 7392341 708511 28.5457 nan -270.488 -28.5457 0 0 -1 -1 1.24 2.14 0.48 -1 -1 1.24 0.496082 0.429934 -k4_n4_v7_bidir.xml ex5p.blif common 10.49 vpr 63.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 342 8 -1 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65300 8 63 1072 1135 0 906 413 21 21 441 clb auto 24.4 MiB 0.27 11449 84948 23521 59664 1763 63.8 MiB 0.57 0.01 12.8622 -575.489 -12.8622 nan 0.65 0.00267296 0.002391 0.164293 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ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time 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x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71692 38 3 1916 1919 0 1483 667 28 28 784 clb auto 29.5 MiB 0.29 19984 195838 60682 130920 4236 70.0 MiB 1.45 0.02 17.0385 -49.2963 -17.0385 nan 0.49 0.00449691 0.00389108 0.328393 0.287877 -1 -1 -1 -1 28 30181 48 2.028e+07 1.878e+07 -1 -1 17.00 1.80013 1.5249 28758 383844 -1 28376 15 9150 33071 2590424 247096 20.7907 nan -60.2269 -20.7907 0 0 -1 -1 0.07 0.68 0.22 -1 -1 0.07 0.170018 0.15064 + k4_n4_v7_bidir.xml apex4.blif common 9.32 vpr 64.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 434 9 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66272 9 19 1271 1290 0 989 462 23 23 529 clb auto 25.3 MiB 0.38 13918 105777 29780 74317 1680 64.7 MiB 0.80 0.01 13.9047 -226.083 -13.9047 nan 0.32 0.00309616 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75676 256 245 1847 2092 0 1412 985 34 34 1156 io auto 28.8 MiB 0.47 16647 378208 121053 242540 14615 73.9 MiB 1.97 0.03 12.9369 -2198.65 -12.9369 nan 0.75 0.00633861 0.00581167 0.523122 0.480492 -1 -1 -1 -1 18 23173 26 3.072e+07 1.452e+07 -1 -1 5.70 2.0657 1.87447 35364 387024 -1 21989 19 8778 32560 2141080 246703 15.131 nan -2729.2 -15.131 0 0 -1 -1 0.07 0.71 0.23 -1 -1 0.07 0.271271 0.249347 + k4_n4_v7_bidir.xml diffeq.blif common 7.63 vpr 67.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 69484 64 39 1935 1974 1 1077 542 23 23 529 clb auto 28.0 MiB 0.35 10284 139709 36550 99088 4071 67.9 MiB 1.01 0.02 13.3471 -2484.01 -13.3471 13.3471 0.32 0.00419252 0.00369096 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-1 -1 -1 -1 -1 -1 -1 -1 -1 1094 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 123920 20 116 4445 4561 1 2290 1230 36 36 1296 clb auto 44.1 MiB 0.99 38255 580886 202911 367450 10525 120.6 MiB 4.25 0.05 29.223 -16576.9 -29.223 29.223 1.43 0.0105708 0.00897893 0.999254 0.851085 -1 -1 -1 -1 26 40614 39 3.468e+07 3.282e+07 -1 -1 79.50 4.26322 3.57492 104992 763300 -1 37284 18 13336 60167 5347576 900846 28.6821 28.6821 -16996 -28.6821 0 0 -1 -1 0.20 1.82 0.58 -1 -1 0.20 0.421201 0.366517 + k4_n4_v7_l1_bidir.xml misex3.blif common 17.56 vpr 65.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 450 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67284 14 14 1411 1425 0 1056 478 24 24 576 clb auto 26.1 MiB 0.40 13799 121898 36530 83432 1936 65.7 MiB 0.91 0.01 18.1166 -222.755 -18.1166 nan 0.58 0.00323875 0.00286176 0.229781 0.204181 -1 -1 -1 -1 21 15917 38 1.452e+07 1.35e+07 -1 -1 12.60 1.01596 0.869596 39160 271852 -1 13861 19 6925 26912 1892268 324238 17.8372 nan -222.89 -17.8372 0 0 -1 -1 0.06 0.66 0.21 -1 -1 0.06 0.14886 0.130215 + k4_n4_v7_l1_bidir.xml pdc.blif common 418.57 vpr 161.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1606 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 164932 16 40 4591 4631 0 3616 1662 43 43 1849 clb auto 50.4 MiB 1.48 71388 995502 386267 603819 5416 155.6 MiB 7.56 0.07 36.0567 -1232.66 -36.0567 nan 2.15 0.0118231 0.00974149 1.23901 1.02884 -1 -1 -1 -1 34 83956 48 5.043e+07 4.818e+07 -1 -1 394.83 5.32434 4.35296 185730 1416087 -1 74292 16 24740 103095 11970321 1866116 34.9964 nan -1210.26 -34.9964 0 0 -1 -1 0.37 3.72 1.11 -1 -1 0.37 0.501094 0.427155 + k4_n4_v7_l1_bidir.xml s298.blif common 14.97 vpr 70.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 573 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71716 4 6 1942 1948 1 1167 583 26 26 676 clb auto 29.8 MiB 0.37 13721 168529 51547 115716 1266 70.0 MiB 1.27 0.02 26.8992 -206.444 -26.8992 26.8992 0.69 0.00496419 0.00432315 0.361202 0.317423 -1 -1 -1 -1 17 15103 41 1.728e+07 1.719e+07 -1 -1 8.88 1.36971 1.16775 39072 254696 -1 13708 17 7890 40380 2928639 390491 25.7904 25.7904 -205.684 -25.7904 0 0 -1 -1 0.06 0.94 0.21 -1 -1 0.06 0.209805 0.184411 + k4_n4_v7_l1_bidir.xml s38417.blif common 61.66 vpr 189.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1852 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 193636 29 106 7534 7640 1 4623 1987 46 46 2116 clb auto 61.8 MiB 1.63 45682 1150699 423694 711314 15691 189.1 MiB 8.82 0.10 24.016 -14000.6 -24.016 24.016 2.46 0.0169007 0.0139461 1.64128 1.36389 -1 -1 -1 -1 16 41981 27 5.808e+07 5.556e+07 -1 -1 37.78 5.55941 4.54523 118272 756192 -1 39731 15 23886 81328 4350389 861432 23.6137 23.6137 -14728 -23.6137 0 0 -1 -1 0.20 2.01 0.59 -1 -1 0.20 0.647233 0.553971 + k4_n4_v7_l1_bidir.xml s38584.1.blif common 67.22 vpr 183.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1787 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 187696 38 304 7475 7779 1 4320 2129 45 45 2025 clb auto 61.8 MiB 1.45 43799 1343749 517594 801490 24665 183.3 MiB 9.49 0.12 21.0587 -13121.7 -21.0587 21.0587 2.45 0.0167009 0.0137478 1.77708 1.46891 -1 -1 -1 -1 16 39654 47 5.547e+07 5.361e+07 -1 -1 43.54 5.72828 4.70791 113090 722879 -1 37482 13 19902 66283 3641519 680597 20.2436 20.2436 -13770 -20.2436 0 0 -1 -1 0.19 1.67 0.56 -1 -1 0.19 0.58033 0.500952 + k4_n4_v7_l1_bidir.xml seq.blif common 39.62 vpr 69.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 567 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71260 41 35 1791 1826 0 1347 643 26 26 676 clb auto 29.0 MiB 0.45 18608 203145 65187 132320 5638 69.6 MiB 1.44 0.02 18.1385 -520.265 -18.1385 nan 0.69 0.00437225 0.00383137 0.338582 0.298021 -1 -1 -1 -1 24 20201 48 1.728e+07 1.701e+07 -1 -1 33.10 1.88123 1.59699 51072 366016 -1 19098 15 8908 34158 2699342 394310 17.881 nan -530.81 -17.881 0 0 -1 -1 0.08 0.83 0.27 -1 -1 0.08 0.160739 0.141136 + k4_n4_v7_l1_bidir.xml spla.blif common 187.45 vpr 130.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1282 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 133456 16 46 3706 3752 0 2852 1344 38 38 1444 clb auto 43.1 MiB 1.08 48851 705674 261242 438237 6195 129.8 MiB 4.82 0.05 28.2789 -928.469 -28.2789 nan 1.62 0.00923375 0.00767658 0.87033 0.724376 -1 -1 -1 -1 30 55651 36 3.888e+07 3.846e+07 -1 -1 170.35 3.95474 3.27046 133344 1000208 -1 49871 15 17906 78246 6885546 1014380 27.1504 nan -941.372 -27.1504 0 0 -1 -1 0.25 2.27 0.77 -1 -1 0.25 0.36105 0.312454 + k4_n4_v7_l1_bidir.xml tseng.blif common 6.87 vpr 64.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65932 52 122 1483 1605 1 725 466 20 20 400 clb auto 25.0 MiB 0.16 6135 112438 30480 78177 3781 64.4 MiB 0.46 0.01 11.1777 -2780.46 -11.1777 11.1777 0.26 0.00160816 0.00140359 0.112456 0.0992435 -1 -1 -1 -1 14 6150 30 9.72e+06 8.76e+06 -1 -1 4.21 0.681536 0.590913 19872 120996 -1 5573 18 4232 15969 711167 147306 11.3812 11.3812 -3151.62 -11.3812 0 0 -1 -1 0.03 0.34 0.09 -1 -1 0.03 0.138745 0.122462 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt index 9a0185a4a79..bb78a015d23 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml sha.v common 44.03 vpr 73.78 MiB -1 -1 3.12 49440 21 3.46 -1 -1 43232 -1 -1 149 38 -1 -1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 75548 38 36 2570 2606 1 1074 223 15 15 225 clb auto 36.3 MiB 1.63 9037 73.8 MiB 0.90 0.01 11.9791 -2411.35 -11.9791 11.9791 0.03 0.00596368 0.00534087 0.447849 0.394176 -1 12486 10 9.10809e+06 8.03021e+06 2.53713e+06 11276.1 0.39 0.766703 0.68744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml sha.v common 27.28 vpr 73.95 MiB -1 -1 4.23 47424 21 2.24 -1 -1 40536 -1 -1 150 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75720 38 36 2570 2606 1 1074 224 15 15 225 clb auto 33.2 MiB 1.42 8222 34904 7738 25262 1904 73.9 MiB 0.73 0.01 13.816 -2613.59 -13.816 13.816 0.00 0.0060727 0.0053926 0.356833 0.315667 -1 -1 -1 -1 -1 11320 14 9.10809e+06 8.0841e+06 2.53713e+06 11276.1 0.33 0.616726 0.549992 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt index 8308ae3e0d1..fce3205d8f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml bigkey.blif common 11.30 vpr 63.27 MiB -1 -1 -1 -1 3 0.32 -1 -1 34796 -1 -1 53 229 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64792 229 197 1023 1220 1 510 479 16 16 256 io auto 24.4 MiB 0.26 3412 154065 46239 98678 9148 63.3 MiB 0.73 0.01 2.41239 -578.515 -2.41239 2.41239 0.56 0.00388149 0.00363052 0.3504 0.328056 34 6563 36 1.05632e+07 2.85638e+06 613832. 2397.78 7.21 1.89404 1.73907 24564 122629 -1 5999 13 1330 2398 156004 35692 2.69369 2.69369 -639.318 -2.69369 0 0 751777. 2936.63 0.19 0.17 0.10 -1 -1 0.19 0.128614 0.119851 -k6_frac_N10_40nm.xml clma.blif common 7.57 vpr 60.88 MiB -1 -1 -1 -1 7 2.24 -1 -1 39876 -1 -1 77 36 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62344 36 82 542 624 1 389 195 11 11 121 clb auto 22.2 MiB 0.52 2075 39180 14775 18229 6176 60.9 MiB 0.27 0.00 4.56725 -162.762 -4.56725 4.56725 0.22 0.00159549 0.00146528 0.119745 0.110395 40 4742 31 4.36541e+06 4.14984e+06 303235. 2506.08 2.55 0.592576 0.518987 11571 60661 -1 3946 19 2186 7344 217806 45734 4.7836 4.7836 -183.173 -4.7836 0 0 379421. 3135.71 0.08 0.13 0.05 -1 -1 0.08 0.0725952 0.0652714 -k6_frac_N10_40nm.xml diffeq.blif common 4.35 vpr 62.58 MiB -1 -1 -1 -1 8 0.40 -1 -1 34344 -1 -1 52 64 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64080 64 39 941 980 1 449 155 10 10 100 clb auto 23.7 MiB 0.70 2754 14299 2774 10573 952 62.6 MiB 0.19 0.00 5.00123 -878.262 -5.00123 5.00123 0.18 0.00232392 0.00210955 0.0947283 0.0862055 46 4930 28 3.44922e+06 2.80249e+06 276332. 2763.32 1.38 0.487916 0.424969 9816 55112 -1 4472 14 1803 5492 169063 35103 5.16783 5.16783 -930.109 -5.16783 0 0 354105. 3541.05 0.07 0.14 0.04 -1 -1 0.07 0.0907073 0.0819924 -k6_frac_N10_40nm.xml dsip.blif common 7.40 vpr 64.36 MiB -1 -1 -1 -1 3 0.30 -1 -1 34644 -1 -1 68 229 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65904 229 197 1135 1332 1 648 494 16 16 256 io auto 24.9 MiB 0.70 4700 170318 50861 109699 9758 64.4 MiB 0.86 0.01 2.3875 -617.47 -2.3875 2.3875 0.55 0.00411276 0.00382969 0.375801 0.34991 34 9287 43 1.05632e+07 3.66479e+06 613832. 2397.78 2.70 1.24173 1.13943 24564 122629 -1 8151 13 2265 5666 327590 69866 2.60848 2.60848 -674.007 -2.60848 0 0 751777. 2936.63 0.18 0.22 0.10 -1 -1 0.18 0.147267 0.137349 -k6_frac_N10_40nm.xml elliptic.blif common 12.50 vpr 72.55 MiB -1 -1 -1 -1 10 1.33 -1 -1 37408 -1 -1 133 131 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74288 131 114 2471 2585 1 970 378 14 14 196 clb auto 32.0 MiB 2.92 9165 74142 19344 51191 3607 72.5 MiB 0.75 0.02 7.14215 -3414.64 -7.14215 7.14215 0.39 0.00547722 0.00485817 0.331988 0.297156 64 15825 36 7.76074e+06 7.1679e+06 810706. 4136.26 3.87 1.47043 1.28666 22444 164128 -1 14159 17 4519 20253 781043 131442 7.47917 7.47917 -3699.02 -7.47917 0 0 1.00880e+06 5146.95 0.21 0.43 0.13 -1 -1 0.21 0.253091 0.228552 -k6_frac_N10_40nm.xml frisc.blif common 16.27 vpr 74.19 MiB -1 -1 -1 -1 12 2.02 -1 -1 37188 -1 -1 153 20 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75968 20 116 2477 2593 1 1088 289 15 15 225 clb auto 33.3 MiB 3.67 12581 59499 15581 39947 3971 74.2 MiB 0.86 0.01 8.14365 -3747.83 -8.14365 8.14365 0.46 0.00553861 0.00488686 0.382187 0.339626 74 21933 44 9.10809e+06 8.24578e+06 1.06098e+06 4715.46 5.56 1.63058 1.41486 27275 217117 -1 19654 18 5722 25295 1201911 194668 8.26982 8.26982 -3960.51 -8.26982 0 0 1.32822e+06 5903.22 0.28 0.55 0.17 -1 -1 0.28 0.277444 0.249442 -k6_frac_N10_40nm.xml s298.blif common 5.81 vpr 62.13 MiB -1 -1 -1 -1 8 0.57 -1 -1 33988 -1 -1 61 4 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63620 4 6 671 677 1 350 71 10 10 100 clb auto 23.2 MiB 0.91 3493 3283 433 2659 191 62.1 MiB 0.10 0.00 5.33805 -43.3781 -5.33805 5.33805 0.18 0.00193693 0.00174134 0.0562002 0.0515773 52 5783 22 3.44922e+06 3.28753e+06 305142. 3051.42 2.47 0.614574 0.526903 10212 61796 -1 5397 17 2148 10775 376607 64965 5.90507 5.90507 -48.8576 -5.90507 0 0 401807. 4018.07 0.08 0.19 0.05 -1 -1 0.08 0.0945264 0.084902 -k6_frac_N10_40nm.xml s38417.blif common 14.75 vpr 78.14 MiB -1 -1 -1 -1 6 3.01 -1 -1 42440 -1 -1 179 29 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80016 29 106 3450 3556 1 1198 314 16 16 256 clb auto 37.1 MiB 2.04 8989 70670 18144 45519 7007 78.1 MiB 0.96 0.01 4.74073 -2890.12 -4.74073 4.74073 0.54 0.00636901 0.00556012 0.4763 0.414513 48 14980 41 1.05632e+07 9.64703e+06 819368. 3200.65 4.15 2.12828 1.82805 26860 167058 -1 13212 15 5024 17286 529604 104654 4.75139 4.75139 -2966.77 -4.75139 0 0 1.04748e+06 4091.72 0.24 0.42 0.13 -1 -1 0.24 0.302619 0.272356 -k6_frac_N10_40nm.xml s38584.1.blif common 16.03 vpr 78.52 MiB -1 -1 -1 -1 6 2.15 -1 -1 41076 -1 -1 194 38 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80400 38 304 3259 3563 1 1574 536 16 16 256 clb auto 37.8 MiB 3.25 9889 183320 55884 108640 18796 78.5 MiB 1.52 0.02 4.27217 -2394.9 -4.27217 4.27217 0.54 0.00692031 0.00615749 0.646279 0.571663 58 17695 25 1.05632e+07 1.04554e+07 977637. 3818.90 4.53 2.11223 1.84277 28644 201685 -1 15484 13 5074 13582 483608 102794 4.69981 4.69981 -2495.41 -4.69981 0 0 1.24374e+06 4858.37 0.28 0.40 0.16 -1 -1 0.28 0.308951 0.281339 -k6_frac_N10_40nm.xml tseng.blif common 3.98 vpr 60.70 MiB -1 -1 -1 -1 7 0.27 -1 -1 34484 -1 -1 34 52 -1 -1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62156 52 122 664 786 1 355 208 8 8 64 io clb auto 22.0 MiB 0.68 1783 26080 5856 18588 1636 60.7 MiB 0.20 0.00 4.2185 -596.347 -4.2185 4.2185 0.10 0.00193464 0.00178089 0.0920256 0.0848454 58 3398 46 1.94018e+06 1.8324e+06 203254. 3175.84 1.50 0.686589 0.603505 6532 39661 -1 2965 13 1169 3143 108747 29150 4.26194 4.26194 -630.352 -4.26194 0 0 258247. 4035.11 0.05 0.10 0.03 -1 -1 0.05 0.0682836 0.0622434 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common 5.65 vpr 64.37 MiB -1 -1 -1 -1 3 0.37 -1 -1 34760 -1 -1 53 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65912 229 197 1023 1220 1 510 479 16 16 256 io auto 23.7 MiB 0.27 3641 154065 46430 98015 9620 64.4 MiB 0.75 0.01 2.42373 -577.247 -2.42373 2.42373 0.27 0.00402185 0.0037687 0.347336 0.325429 -1 -1 -1 -1 36 6328 35 1.05632e+07 2.85638e+06 638738. 2495.07 2.33 1.3288 1.226 24820 128426 -1 5481 8 1306 2376 126862 31374 2.67597 2.67597 -632.008 -2.67597 0 0 786978. 3074.13 0.03 0.14 0.10 -1 -1 0.03 0.10014 0.0939306 + k6_frac_N10_40nm.xml clma.blif common 7.01 vpr 61.45 MiB -1 -1 -1 -1 7 2.26 -1 -1 40008 -1 -1 79 36 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62928 36 82 542 624 1 389 197 11 11 121 clb auto 22.0 MiB 0.54 2089 43172 15722 20877 6573 61.5 MiB 0.30 0.01 4.60077 -165.07 -4.60077 4.60077 0.11 0.00158856 0.00146661 0.128968 0.119097 -1 -1 -1 -1 44 4139 30 4.36541e+06 4.25763e+06 327165. 2703.84 1.96 0.513339 0.454587 11931 67129 -1 3316 16 1708 5716 138864 32420 4.83136 4.83136 -175.151 -4.83136 0 0 426099. 3521.48 0.01 0.11 0.05 -1 -1 0.01 0.0673334 0.0609583 + k6_frac_N10_40nm.xml diffeq.blif common 4.08 vpr 63.54 MiB -1 -1 -1 -1 8 0.41 -1 -1 34312 -1 -1 52 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65060 64 39 941 980 1 449 155 10 10 100 clb auto 23.5 MiB 0.77 2832 12635 2438 9282 915 63.5 MiB 0.18 0.01 4.98272 -882.824 -4.98272 4.98272 0.09 0.00238086 0.0021534 0.0867068 0.0790903 -1 -1 -1 -1 46 4591 19 3.44922e+06 2.80249e+06 276332. 2763.32 1.21 0.589006 0.512826 9816 55112 -1 4111 18 1656 5042 136520 29654 5.41789 5.41789 -952.235 -5.41789 0 0 354105. 3541.05 0.01 0.16 0.04 -1 -1 0.01 0.110724 0.0994958 + k6_frac_N10_40nm.xml dsip.blif common 7.35 vpr 64.67 MiB -1 -1 -1 -1 3 0.33 -1 -1 34628 -1 -1 68 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66224 229 197 1135 1332 1 648 494 16 16 256 io auto 25.0 MiB 0.72 5390 162510 50223 103313 8974 64.7 MiB 0.91 0.01 2.31397 -600.978 -2.31397 2.31397 0.27 0.00421493 0.00392148 0.372643 0.347093 -1 -1 -1 -1 34 9972 32 1.05632e+07 3.66479e+06 613832. 2397.78 3.30 1.45616 1.33282 24564 122629 -1 8332 13 2339 5868 306706 68264 2.51113 2.51113 -669.569 -2.51113 0 0 751777. 2936.63 0.03 0.23 0.10 -1 -1 0.03 0.152244 0.141942 + k6_frac_N10_40nm.xml elliptic.blif common 11.64 vpr 72.78 MiB -1 -1 -1 -1 10 1.34 -1 -1 37432 -1 -1 134 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74524 131 114 2471 2585 1 965 379 14 14 196 clb auto 31.8 MiB 3.04 9493 78526 21300 53244 3982 72.8 MiB 0.92 0.02 6.66989 -3362.18 -6.66989 6.66989 0.19 0.00621513 0.00561729 0.393073 0.34792 -1 -1 -1 -1 64 15463 36 7.76074e+06 7.2218e+06 810706. 4136.26 3.33 1.63306 1.42706 22444 164128 -1 13666 16 4234 17970 605416 107406 6.78748 6.78748 -3469.91 -6.78748 0 0 1.00880e+06 5146.95 0.03 0.43 0.13 -1 -1 0.03 0.272075 0.245691 + k6_frac_N10_40nm.xml frisc.blif common 13.54 vpr 74.06 MiB -1 -1 -1 -1 12 2.03 -1 -1 37144 -1 -1 154 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75836 20 116 2477 2593 1 1095 290 15 15 225 clb auto 33.2 MiB 3.17 12890 61666 15631 41457 4578 74.1 MiB 0.67 0.01 8.02167 -3816.55 -8.02167 8.02167 0.17 0.00308355 0.00276008 0.244864 0.21648 -1 -1 -1 -1 74 21484 43 9.10809e+06 8.29968e+06 1.06098e+06 4715.46 4.50 1.57616 1.37159 27275 217117 -1 19434 16 5788 25215 1069833 185373 8.27179 8.27179 -4029.23 -8.27179 0 0 1.32822e+06 5903.22 0.04 0.55 0.17 -1 -1 0.04 0.282827 0.255609 + k6_frac_N10_40nm.xml s298.blif common 4.79 vpr 62.54 MiB -1 -1 -1 -1 8 0.58 -1 -1 33952 -1 -1 61 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64036 4 6 671 677 1 350 71 10 10 100 clb auto 23.2 MiB 0.90 3495 3137 432 2529 176 62.5 MiB 0.10 0.00 5.3014 -43.7499 -5.3014 5.3014 0.09 0.00191372 0.00173621 0.0550982 0.0506336 -1 -1 -1 -1 54 5597 27 3.44922e+06 3.28753e+06 316276. 3162.76 1.25 0.504852 0.437208 10312 63908 -1 5157 17 2266 11525 327366 61505 5.48392 5.48392 -46.8399 -5.48392 0 0 411339. 4113.39 0.01 0.18 0.05 -1 -1 0.01 0.0985021 0.0889271 + k6_frac_N10_40nm.xml s38417.blif common 14.29 vpr 78.14 MiB -1 -1 -1 -1 6 3.06 -1 -1 42400 -1 -1 176 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80012 29 106 3450 3556 1 1190 311 16 16 256 clb auto 36.9 MiB 1.87 8949 65597 16026 43107 6464 78.1 MiB 1.20 0.02 4.50231 -2905.37 -4.50231 4.50231 0.27 0.00878799 0.00788817 0.629893 0.548582 -1 -1 -1 -1 46 15732 39 1.05632e+07 9.48534e+06 786978. 3074.13 4.38 2.35028 2.01673 26604 162157 -1 13635 14 5142 17426 519616 106370 4.53102 4.53102 -2987.6 -4.53102 0 0 1.01084e+06 3948.58 0.03 0.46 0.12 -1 -1 0.03 0.329139 0.295823 + k6_frac_N10_40nm.xml s38584.1.blif common 15.85 vpr 78.47 MiB -1 -1 -1 -1 6 2.17 -1 -1 41016 -1 -1 203 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80352 38 304 3259 3563 1 1559 545 17 17 289 clb auto 37.3 MiB 3.11 10446 174095 49766 105233 19096 78.5 MiB 1.70 0.02 4.29015 -2399.8 -4.29015 4.29015 0.30 0.00816298 0.00737727 0.707435 0.623009 -1 -1 -1 -1 58 17767 23 1.21262e+07 1.09405e+07 1.11519e+06 3858.79 4.82 2.79347 2.44034 32499 230706 -1 16008 15 5250 14700 516522 110817 4.81093 4.81093 -2541.32 -4.81093 0 0 1.41877e+06 4909.24 0.05 0.49 0.18 -1 -1 0.05 0.36595 0.331861 + k6_frac_N10_40nm.xml tseng.blif common 3.49 vpr 61.39 MiB -1 -1 -1 -1 7 0.30 -1 -1 34332 -1 -1 33 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62864 52 122 664 786 1 358 207 8 8 64 io clb auto 21.8 MiB 0.69 1908 22239 4478 16280 1481 61.4 MiB 0.19 0.01 4.25559 -597.466 -4.25559 4.25559 0.05 0.00195021 0.00179724 0.0809638 0.0748422 -1 -1 -1 -1 58 3323 26 1.94018e+06 1.7785e+06 203254. 3175.84 1.00 0.508961 0.449326 6532 39661 -1 2850 14 1079 2916 89573 24965 4.64398 4.64398 -644.298 -4.64398 0 0 258247. 4035.11 0.01 0.11 0.03 -1 -1 0.01 0.0730931 0.0666261 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt index e7281d70fba..6a59a733970 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 47.21 vpr 98.92 MiB -1 -1 5.05 65016 8 3.45 -1 -1 44040 -1 -1 251 385 2 1 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 101292 385 362 4531 4417 1 2465 1001 26 26 676 io auto 59.7 MiB 5.71 30896 96.5 MiB 3.76 0.04 8.37958 -9104.32 -8.37958 8.37958 1.98 0.00830834 0.00758752 1.05656 0.959646 90 47787 47 3.69863e+07 1.50194e+07 3.84682e+06 5690.57 18.16 4.21656 3.81172 44385 19 10566 34671 3451960 662494 9.05146 9.05146 -10537 -9.05146 0 0 4.81243e+06 7118.99 1.55 1.22 0.549245 0.511207 - k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 19.74 vpr 79.73 MiB -1 -1 2.63 46860 4 2.10 -1 -1 41524 -1 -1 132 38 0 0 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 81640 38 36 2744 2493 1 1037 206 16 16 256 clb auto 42.8 MiB 2.33 8753 79.7 MiB 0.86 0.01 9.36767 -2501.88 -9.36767 9.36767 0.82 0.00550316 0.00491598 0.40002 0.356102 62 13665 39 1.21132e+07 7.11401e+06 968026. 3781.35 6.03 2.53777 2.22319 12472 21 4184 9814 370969 64997 10.7551 10.7551 -3015.2 -10.7551 0 0 1.20332e+06 4700.46 0.45 0.55 0.435383 0.391894 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 28.60 vpr 68.80 MiB -1 -1 17.23 47568 3 0.87 -1 -1 38244 -1 -1 44 196 1 0 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 70452 196 193 1202 1347 1 614 434 15 15 225 io auto 30.8 MiB 0.96 3011 68.8 MiB 0.68 0.01 2.01184 -980.486 -2.01184 2.01184 0.78 0.00265232 0.00237738 0.259845 0.234269 40 6048 22 1.03862e+07 2.91934e+06 568276. 2525.67 4.59 1.09948 1.00544 5465 12 1709 2607 217962 55517 2.51002 2.51002 -1171.5 -2.51002 0 0 712852. 3168.23 0.29 0.17 0.113728 0.107732 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 39.01 vpr 82.69 MiB -1 -1 4.24 45940 3 1.03 -1 -1 40156 -1 -1 120 236 1 6 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84672 236 305 3195 3007 1 1534 668 19 19 361 io auto 45.6 MiB 3.15 12151 82.7 MiB 2.21 0.03 4.27652 -2642.42 -4.27652 4.27652 1.33 0.00627945 0.00562841 0.771371 0.692542 62 23629 24 1.72706e+07 9.39128e+06 1.42198e+06 3939.00 19.99 3.88206 3.48504 20659 16 6434 17007 3134575 708021 4.9842 4.9842 -3082.5 -4.9842 0 0 1.76637e+06 4892.99 0.79 1.16 0.398852 0.370941 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.88 vpr 105.39 MiB -1 -1 6.79 63484 8 3.06 -1 -1 40704 -1 -1 250 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 107916 385 362 4415 4299 1 2365 1000 26 26 676 io auto 53.4 MiB 8.02 30064 545782 201861 320153 23768 96.5 MiB 5.36 0.06 9.17025 -9814.95 -9.17025 9.17025 0.75 0.0154429 0.0143793 1.79153 1.64504 -1 -1 -1 -1 86 44693 20 3.69863e+07 1.49655e+07 3.69198e+06 5461.52 13.35 6.72204 6.1687 89040 769342 -1 41511 17 9662 32287 1739041 311622 9.36868 9.36868 -10331.7 -9.36868 0 0 4.67059e+06 6909.16 0.16 1.11 0.68 -1 -1 0.16 0.681008 0.635643 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 15.44 vpr 81.45 MiB -1 -1 3.43 44504 3 1.23 -1 -1 39800 -1 -1 141 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83404 38 36 2739 2488 1 1022 215 17 17 289 clb auto 40.5 MiB 1.96 8926 42010 10393 28489 3128 81.4 MiB 0.91 0.01 10.0828 -2706.04 -10.0828 10.0828 0.30 0.00541664 0.00477131 0.391772 0.345384 -1 -1 -1 -1 62 13454 38 1.34605e+07 7.59905e+06 1.10657e+06 3828.96 3.45 1.77757 1.52314 31771 216973 -1 12449 21 4102 9497 328915 58876 10.8931 10.8931 -3012.43 -10.8931 0 0 1.37508e+06 4758.06 0.05 0.40 0.19 -1 -1 0.05 0.289893 0.256286 + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.74 vpr 70.58 MiB -1 -1 17.86 45828 3 0.69 -1 -1 35540 -1 -1 48 196 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72272 196 193 1201 1346 1 606 438 15 15 225 io auto 31.2 MiB 0.83 3130 146694 39708 93961 13025 70.6 MiB 0.73 0.01 2.24601 -1081.12 -2.24601 2.24601 0.23 0.00356204 0.00332113 0.333364 0.31069 -1 -1 -1 -1 36 6058 29 1.03862e+07 3.13491e+06 520410. 2312.93 1.93 1.18409 1.08635 21110 102306 -1 5134 10 1618 2340 136007 39516 2.56471 2.56471 -1177.45 -2.56471 0 0 643451. 2859.78 0.02 0.14 0.09 -1 -1 0.02 0.102579 0.095844 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 22.86 vpr 83.41 MiB -1 -1 4.78 42380 3 0.69 -1 -1 37656 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85412 236 305 3199 3011 1 1520 677 19 19 361 io auto 42.5 MiB 2.99 12761 268067 88565 164726 14776 83.4 MiB 2.03 0.03 4.74988 -2887.79 -4.74988 4.74988 0.39 0.00859777 0.00794312 0.829104 0.763261 -1 -1 -1 -1 62 24213 37 1.72706e+07 9.87633e+06 1.42198e+06 3939.00 7.32 3.04293 2.76861 40483 281719 -1 20603 18 6062 15441 1381198 347776 4.88181 4.88181 -3127.07 -4.88181 0 0 1.76637e+06 4892.99 0.06 0.66 0.24 -1 -1 0.06 0.38505 0.357195 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt index cf79f555b8c..a4f9b24ece9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 641.67 vpr 492.06 MiB -1 -1 62.37 452332 97 114.33 -1 -1 115316 -1 -1 2134 114 45 8 success 897b3a8-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-31T03:36:34 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 503872 114 102 35773 31864 1 16914 2403 56 56 3136 clb auto 343.5 MiB 83.71 223478 368.9 MiB 77.61 0.67 65.1983 -51745.6 -65.1983 65.1983 1.35 0.10571 0.0920455 13.1674 10.7012 -1 321806 23 1.8697e+08 1.4284e+08 2.05038e+07 6538.21 25.53 21.7816 18.0231 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 487.31 vpr 496.91 MiB -1 -1 76.36 452592 97 71.44 -1 -1 112732 -1 -1 2151 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 508836 114 102 35834 31925 1 16897 2420 56 56 3136 clb auto 278.8 MiB 75.84 221426 1805060 662974 1113867 28219 408.5 MiB 56.83 0.51 73.2133 -55671.2 -73.2133 73.2133 0.01 0.0965983 0.0857314 13.1957 10.9836 -1 -1 -1 -1 -1 309163 22 1.8697e+08 1.43756e+08 2.23321e+07 7121.20 10.26 19.311 16.2288 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt index f2b439ff03e..b88815848b4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1315.84 77 3123 89 136 0 0 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 2858228 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 86.66 609879 114.00 0.78 7.31659 -73007.4 -6.31659 6.39652 193.04 0.230423 0.177265 33.2852 25.4119 777696 -1 -1 -1 -1 0 0 2.28642e+08 18462.7 20 7.77193 6.96909 -118197 -6.77193 0 0 50.21 46.7196 37.2174 149.58 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 868.60 vpr 2.85 GiB 77 3136 89 136 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2992704 42 35 119888 86875 1 50816 3438 129 96 12384 DSP auto 1747.1 MiB 107.17 582667 3141815 1177622 1941316 22877 2922.6 MiB 141.55 1.07 8.30634 -81008.6 -7.30634 5.71368 0.07 0.395558 0.333308 50.4231 42.3852 753664 14.8455 159283 3.13753 108681 189329 132420316 35517631 0 0 2.28639e+08 18462.4 18 3593250 39165143 -1 8.74065 6.13717 -112227 -7.74065 0 0 68.73 -1 -1 2922.6 MiB 45.88 68.8436 58.8864 2922.6 MiB -1 22.31 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_other/config/golden_results.txt index 71836073bd1..b1f58c98f8e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_other/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 311.80 274 967 36 59 0 2 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1686764 22 252 53001 29054 7 24654 1338 89 66 5874 DSP auto 23.51 252822 67.35 0.34 7.26641 -38060.9 -6.26641 2.79561 72.76 0.0922902 0.0742036 19.4784 15.1106 354720 83977 171255 284760839 58437920 0 0 1.08076e+08 18399.1 50 7.93667 2.94925 -43306.7 -6.93667 0 0 48.18 30.2955 24.559 65.43 -stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 215.82 36 1583 10 10 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1399980 3 33 48977 39238 1 25960 1639 54 40 2160 LAB auto 60.22 275660 73.30 0.48 76.888 -77679.7 -75.888 76.888 8.10 0.0956007 0.0692678 14.5078 10.6502 370341 90509 238008 217472654 23545267 0 0 3.96465e+07 18354.9 28 71.6492 71.6492 -105914 -70.6492 0 0 28.14 21.4905 16.5041 21.42 -stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 492.02 211 2256 3 210 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1898600 38 173 62892 59064 3 36122 2680 86 64 5504 M9K auto 130.91 654114 131.72 0.80 13.3368 -342543 -12.3368 7.39474 50.51 0.177306 0.126609 25.7151 17.5933 892864 172996 611822 407520129 46601819 0 0 1.01289e+08 18402.8 68 14.1432 7.7062 -394796 -13.1432 0 0 73.84 51.3879 38.3937 62.13 -stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 613.15 574 2805 16 0 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1988108 4 570 66175 54803 2 39637 3395 91 67 6097 io auto 110.71 677805 163.29 1.08 28.2408 -109542 -27.2408 6.93264 72.80 0.187151 0.130173 25.6141 17.899 973037 224900 867383 947842960 143826835 0 0 1.12157e+08 18395.4 25 29.6387 8.19964 -124725 -28.6387 0 0 154.76 37.9372 28.0766 66.17 -stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 1318.55 40 3678 172 1 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 4743240 19 21 171111 96274 1 72623 3891 194 144 27936 DSP auto 76.77 765977 145.09 1.60 5.16314 -128136 -4.16314 3.90969 508.03 0.285112 0.239247 42.3664 34.8257 874132 150455 182899 349628973 70478863 0 0 5.18919e+08 18575.3 13 5.45721 4.48464 -179446 -4.45721 0 0 63.66 54.6347 45.956 400.24 -stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 341.45 536 1972 7 4 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1657868 227 309 49176 40422 1 28183 2519 85 63 5355 io auto 77.01 312290 91.24 0.69 195.971 -119913 -194.971 195.971 50.83 0.0991588 0.084565 16.0983 11.5643 406195 106821 335442 213233166 16541048 0 0 9.84408e+07 18383.0 22 188.774 188.774 -136523 -187.774 0 0 25.35 22.7627 17.0347 58.18 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 247.43 36 1332 8 149 2 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1531868 3 33 52402 39411 1 28117 1527 73 54 3942 M9K auto 61.30 324276 56.90 0.43 16.9115 -306564 -15.9115 16.9115 21.92 0.115668 0.0811981 14.2927 9.97478 446671 101291 248928 219409565 29355499 0 0 7.26339e+07 18425.6 49 17.5096 17.5096 -329353 -16.5096 0 0 36.21 25.5848 19.3127 40.00 -stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 103.86 251 951 1 17 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1118884 55 196 20131 19956 1 8395 1220 44 33 1452 io auto 36.33 120394 17.88 0.13 7.53064 -73100.4 -6.53064 7.53064 5.18 0.0385338 0.0250793 5.54194 3.66441 176474 31041 128473 83605460 6753731 0 0 2.65099e+07 18257.5 28 8.2232 8.2232 -80771.2 -7.2232 0 0 10.41 8.44641 6.09178 14.90 -stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 219.94 255 2095 1 28 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1429560 84 171 36458 36247 3 20591 2379 62 46 2852 LAB auto 73.17 304905 58.87 0.36 12.4545 -84121.6 -11.4545 3.90486 14.28 0.0957957 0.0630812 14.7936 9.65547 399311 62124 215218 133537079 11346973 0 0 5.24521e+07 18391.3 13 13.7366 4.34743 -96722.9 -12.7366 0 0 15.78 19.0668 13.1481 28.90 -stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 423.80 69 2106 10 295 16 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 2030312 36 33 57796 49182 1 20383 2496 105 78 8190 M9K auto 64.78 248417 57.14 0.43 8.87852 -98126.1 -7.87852 8.87852 101.81 0.102251 0.0739036 16.5433 11.9168 401785 70797 206901 253160930 44501707 0 0 1.50986e+08 18435.5 70 8.73181 8.73181 -152440 -7.73181 0 0 59.20 32.5906 25.4858 95.57 -stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 414.48 478 1243 1 300 4 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1930672 202 276 35125 30509 3 21597 2026 106 79 8374 M9K auto 62.32 273262 46.18 0.37 9.02165 -38875.4 -8.02165 2.98256 116.87 0.119629 0.0874896 15.1424 10.6139 427620 69908 196969 259577742 42937167 0 0 1.54360e+08 18433.2 24 9.59492 3.21937 -53394.2 -8.59492 0 0 49.61 22.0979 16.4463 95.83 -stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 221.49 5 335 31 105 0 2 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1529424 3 2 14862 10304 26 7545 478 89 66 5874 DSP auto 32.10 110073 8.69 0.05 5.6799 -31954.6 -4.6799 3.86103 73.08 0.0297436 0.0249301 5.08886 3.80117 162487 18820 40748 49231361 8764921 0 0 1.08076e+08 18399.1 13 5.94858 4.19214 -42746.9 -4.94858 0 0 8.06 6.74261 5.24191 66.24 -stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 453.16 693 1772 25 16 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 2041664 35 658 51416 37539 1 27838 2506 108 80 8640 io auto 58.41 242409 99.55 0.46 37.8217 -58716.9 -36.8217 37.8217 112.56 0.0923575 0.0800076 22.4325 16.6445 339418 92511 294098 299646713 40180048 0 0 1.59377e+08 18446.5 21 38.6529 38.6529 -63587.1 -37.6529 0 0 37.23 29.0352 22.2784 99.48 -stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 370.66 753 1134 5 32 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 2077072 13 740 25173 25306 1 12841 1924 117 87 10179 io auto 43.57 162862 27.12 0.18 9.4498 -29888.4 -8.4498 7.62781 119.49 0.0419754 0.0337119 7.41368 5.12874 203573 33756 127355 88616513 6903805 0 0 1.87947e+08 18464.1 16 10.0597 7.94534 -35332.5 -9.05972 0 0 10.27 10.3001 7.58645 123.59 -stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 254.87 117 2162 0 0 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1586756 79 38 66795 54922 1 35874 2279 62 46 2852 LAB auto 66.38 265514 91.85 0.60 9.73271 -169191 -8.73271 9.73271 14.10 0.109447 0.0754959 15.151 10.2167 353280 150391 325210 185311692 14766611 0 0 5.24521e+07 18391.3 39 10.5988 10.5988 -198966 -9.59881 0 0 26.10 26.0487 19.0873 27.50 -stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 199.98 213 1566 26 4 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1599748 139 74 57121 41054 1 24187 1809 75 56 4200 DSP auto 50.57 166705 40.06 0.27 5.67384 -21057.2 -4.67384 4.83115 17.58 0.089833 0.0688155 14.1813 10.5486 223321 55207 100513 123731930 21668188 0 0 7.74195e+07 18433.2 28 6.01154 5.30578 -34881.6 -5.01154 0 0 20.05 20.8584 16.3292 41.08 -stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 93.73 54 671 0 40 0 1 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1075876 2 52 16673 16662 2 12020 766 38 28 1064 LAB auto 28.79 181169 14.48 0.11 5.49667 -21261.7 -4.49667 4.87568 5.83 0.044069 0.0283665 5.5448 3.63538 246051 57719 179681 173183538 18866158 0 0 1.93821e+07 18216.2 19 6.0422 5.29849 -27330.5 -5.0422 0 0 19.56 8.20931 5.7957 8.71 -stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 310.33 445 2166 19 51 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1713300 131 314 57881 45152 1 32966 2681 73 54 3942 io auto 70.45 321679 104.87 0.89 196.373 -68832.2 -195.373 196.373 21.24 0.227108 0.170335 20.1175 14.878 433232 110664 348056 280252346 23247136 0 0 7.26339e+07 18425.6 39 188.336 188.336 -82847 -187.336 0 0 37.14 33.2841 25.9806 41.01 -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 54.29 42 750 0 0 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1042248 13 29 26295 20086 1 12417 792 39 29 1131 LAB auto 9.43 75218 10.95 0.06 4.87175 -4560.25 -3.87175 2.71822 4.94 0.0168256 0.0134598 2.75581 1.80879 82722 32407 46016 30062452 2507226 0 0 2.05958e+07 18210.3 16 4.98602 2.75435 -5381.95 -3.98602 0 0 3.35 3.89581 2.77576 9.91 -stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 678.97 964 982 19 34 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 2781748 542 422 37277 26038 1 20655 1999 147 109 16023 io auto 41.73 267816 73.62 0.80 7.80246 -38033.5 -6.80246 7.6263 258.47 0.0892357 0.0697083 13.6631 10.2442 362796 92851 202881 211513388 35702086 0 0 2.96650e+08 18514.0 55 8.53312 8.20447 -44732.7 -7.53312 0 0 41.77 24.7555 19.7387 200.64 -stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 799.35 1107 724 0 0 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 3223976 403 704 15490 16194 1 8415 1831 167 124 20708 io auto 37.55 190229 16.71 0.14 11.4027 -21636.9 -10.4027 4.89489 400.55 0.0371088 0.0262547 5.13621 3.50481 233299 26413 105009 64404491 4696027 0 0 3.84012e+08 18544.1 14 11.8994 5.31154 -27542.3 -10.8994 0 0 7.34 6.87555 4.97917 259.42 -stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 89.94 35 730 0 6 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1046032 18 17 16969 16357 1 6291 771 39 29 1131 LAB auto 39.14 82220 9.36 0.08 6.86051 -43809.9 -5.86051 6.86051 4.27 0.0198281 0.0155483 3.08359 2.01596 116615 27639 146882 73829529 5721062 0 0 2.05958e+07 18210.3 43 7.27333 7.27333 -49633.6 -6.27333 0 0 10.96 6.52073 4.82028 9.83 -stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 16.85 35 76 0 8 0 0 success v8.0.0-4099-g0082ba205 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-08-02T02:41:49 betzgrp-wintermute.eecg.utoronto.ca /home/ahmadi55/vtr-verilog-to-routing/vtr_flow 1076940 18 17 2291 2142 1 1504 119 16 12 192 LAB M9K auto 4.08 10271 0.96 0.01 4.965 -3328.06 -3.965 3.70554 0.09 0.00544208 0.00414461 0.470524 0.35424 14141 4076 9559 7859416 739818 0 0 3.35078e+06 17452.0 20 5.1517 3.94454 -3676.27 -4.1517 0 0 0.88 0.737841 0.591727 0.41 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2102508 4 570 66175 54803 2 39221 3376 91 67 6097 io auto 1442.4 MiB 160.90 637050 2737396 996225 1655508 85663 2024.5 MiB 152.59 1.32 31.0835 -120493 -30.0835 7.14678 0.05 0.24893 0.221734 29.4275 24.9184 899667 22.9413 200386 5.10980 182427 712388 314287781 64497091 0 0 1.12154e+08 18394.9 22 1777086 19206576 -1 31.4681 7.0455 -124410 -30.4681 0 0 40.50 -1 -1 2024.5 MiB 89.22 43.711 37.2882 2024.5 MiB -1 9.88 + stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 581.34 vpr 4.71 GiB 40 3697 172 1 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 4942252 19 21 171111 96274 1 69059 3910 194 144 27936 DSP auto 1879.6 MiB 92.06 765653 3945030 1609251 2318045 17734 4826.4 MiB 169.94 1.44 6.56186 -137549 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1271264 55 196 20131 19956 1 8273 1224 44 33 1452 io auto 1086.7 MiB 51.58 121891 590184 190135 382049 18000 1219.4 MiB 16.94 0.19 8.00991 -79285.3 -7.00991 8.00991 0.01 0.0540335 0.042834 5.3265 4.25169 175526 21.2244 41043 4.96288 27288 110050 30231721 5468094 0 0 2.65070e+07 18255.5 16 423692 4510959 -1 8.24194 8.24194 -78833.9 -7.24194 0 0 10.78 -1 -1 1219.4 MiB 10.31 7.96372 6.52567 1219.4 MiB -1 2.08 + stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 249.81 vpr 1.51 GiB 255 2122 1 28 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1578260 84 171 36458 36247 3 20327 2406 62 46 2852 LAB auto 1227.7 MiB 129.65 282856 1613906 577988 956437 79481 1496.5 MiB 49.09 0.46 12.7635 -89890.6 -11.7635 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1767028 3 2 14862 10304 26 7583 476 89 66 5874 DSP auto 1033.8 MiB 53.02 124138 182462 49732 129080 3650 1725.6 MiB 10.85 0.11 5.88079 -31819.8 -4.88079 4.5134 0.03 0.0618536 0.0525314 6.42815 5.46252 179249 23.7196 37106 4.91015 18387 40581 28916864 7312373 0 0 1.08074e+08 18398.6 14 1714760 18504579 -1 6.28555 4.43959 -39032.4 -5.28555 0 0 38.34 -1 -1 1725.6 MiB 8.47 8.90485 7.65703 1725.6 MiB -1 8.94 + stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 303.21 vpr 2.16 GiB 693 1797 25 16 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2264080 35 658 51416 37539 1 27427 2531 108 80 8640 io auto 1279.4 MiB 79.02 241934 2243861 754419 1344439 145003 2211.0 MiB 86.86 0.75 41.8615 -66574.8 -40.8615 41.8615 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2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1740272 139 74 57121 41054 1 24001 1808 75 56 4200 DSP auto 1288.6 MiB 70.43 167389 1300988 426055 839266 35667 1699.5 MiB 55.74 0.51 5.92747 -26440.3 -4.92747 5.12571 0.04 0.163802 0.140085 19.2082 16.3816 226209 9.42655 53807 2.24224 52155 95084 47723189 13084284 0 0 7.74167e+07 18432.5 19 1223026 13250712 -1 6.18889 5.28844 -34182.8 -5.18889 0 0 27.88 -1 -1 1699.5 MiB 17.42 27.0898 23.3547 1699.5 MiB -1 6.41 + stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 102.62 vpr 1.18 GiB 54 665 0 40 0 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1232304 2 52 16673 16662 2 12027 760 37 27 999 LAB auto 1064.5 MiB 40.48 185817 260785 68816 184545 7424 1165.2 MiB 13.22 0.17 6.43593 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36.2469 31.1156 1720.1 MiB -1 6.18 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 56.35 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1213036 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1061.7 MiB 12.38 72155 253216 50624 190930 11662 1175.9 MiB 10.02 0.13 5.18599 -5515.92 -4.18599 2.85104 0.01 0.0366291 0.0316121 2.8417 2.37087 84093 6.76152 20141 1.61944 25550 34715 9357710 1681121 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 5.29142 2.82099 -5638.13 -4.29142 0 0 8.52 -1 -1 1175.9 MiB 3.91 4.51909 3.83081 1175.9 MiB -1 1.49 + stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 335.23 vpr 2.90 GiB 964 1119 19 34 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3043780 542 422 37277 26038 1 20403 2136 147 109 16023 io auto 1148.7 MiB 80.27 272838 1734636 659517 1007756 67363 2972.4 MiB 69.82 0.57 8.43041 -42423.1 -7.43041 8.08995 0.09 0.110892 0.0979927 15.5695 13.2591 363091 17.7986 78522 3.84912 59722 139345 87871064 23006283 0 0 2.96647e+08 18513.8 19 4640960 50771684 -1 8.69484 7.49966 -42054.1 -7.69484 0 0 98.95 -1 -1 2972.4 MiB 25.07 21.2025 18.289 2972.4 MiB -1 29.48 + stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 287.05 vpr 3.37 GiB 1107 725 0 0 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3531316 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 1059.2 MiB 60.68 187193 1324022 523278 764997 35747 3448.6 MiB 22.04 0.19 12.7682 -23323.6 -11.7682 6.27217 0.11 0.058631 0.0487404 7.24478 6.0757 231524 27.1328 38817 4.54905 24809 96129 21440863 3812157 0 0 3.84009e+08 18544.0 14 5987112 65598998 -1 12.9996 6.14541 -26165.8 -11.9996 0 0 128.48 -1 -1 3448.6 MiB 8.30 9.76557 8.27695 3448.6 MiB -1 39.20 + stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 105.89 vpr 1.15 GiB 35 739 0 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1206268 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 1055.9 MiB 58.67 84377 244832 62116 178083 4633 1170.7 MiB 9.36 0.15 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0403174 0.0343915 3.27761 2.60777 119256 18.9777 28323 4.50716 18857 88786 20657004 3728094 0 0 2.05929e+07 18207.7 16 331560 3499109 -1 7.35046 7.35046 -45160 -6.35046 0 0 8.57 -1 -1 1170.7 MiB 7.33 5.31368 4.36758 1170.7 MiB -1 1.64 + stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 24.32 vpr 991.27 MiB 35 78 0 8 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1015056 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 952.9 MiB 5.78 10189 9390 1103 7334 953 991.3 MiB 0.56 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00719423 0.00593688 0.266582 0.228623 14035 9.71280 3656 2.53010 3331 8155 2407464 497474 0 0 3.34790e+06 17437.0 10 54372 558374 -1 5.45077 4.46245 -3957.23 -4.45077 0 0 1.85 -1 -1 991.3 MiB 0.84 0.535245 0.473492 991.3 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_quick_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_quick_qor/config/golden_results.txt index d7048468870..82ffc857817 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_quick_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/titan_quick_qor/config/golden_results.txt @@ -1,23 +1,23 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 3434.92 136 21492 0 1848 0 1 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 9760656 100 36 504627 490068 5 200916 23477 255 189 48195 M9K auto 700.76 -1 1504.23 11.74 8.0573 -1.40572e+06 -8.0573 5.6189 177.19 1.11051 0.713981 193.057 125.871 5385844 441201 1322987 933414169 132816309 0 0 8.91222e+08 18492.0 12 9.20679 6.19052 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sparcT2_core_stratixiv_arch_timing.blif common 3101.89 451 14725 0 260 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5492144 239 212 302755 300220 1 184812 15436 153 113 17289 LAB auto 720.50 -1 1616.14 9.31 10.5604 -686489 -9.56037 10.5604 74.77 0.872497 0.578117 133.503 89.1183 4841206 557658 2081616 1599598820 153094223 0 0 3.20293e+08 18525.8 65 10.8439 10.8439 -962235 -9.84391 0 0 295.90 247.633 179.457 246.21 -stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 2191.28 162 9680 132 600 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 5522328 94 68 331744 255478 1 156536 10574 169 125 21125 DSP auto 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196307724 0 0 6.00287e+08 18530.2 43 10.8759 10.8759 -859659 -9.87586 0 0 300.88 195.6 151.617 643.04 -stratixiv_arch.timing.xml bitonic_mesh_stratixiv_arch_timing.blif common 3396.68 119 7239 85 1664 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks 6841728 87 32 233978 190746 1 146198 9107 242 179 43318 M9K auto 559.97 -1 1127.28 6.90 12.1144 -1.51589e+06 -11.1144 12.1144 221.34 1.21887 0.860698 175.663 128.302 4588292 456078 1491126 1548811766 242407085 0 0 8.01751e+08 18508.5 18 12.7209 12.7209 -1.86107e+06 -11.7209 0 0 304.05 240.372 183.004 932.96 -stratixiv_arch.timing.xml segmentation_stratixiv_arch_timing.blif common 1763.17 441 6937 15 481 0 0 success v8.0.0-4626-g00c7dece9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2021-10-05T20:25:38 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4176.1 MiB 102.09 117.721 99.3918 4176.1 MiB -1 40.63 + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 421.30 vpr 2.85 GiB 77 3136 89 136 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2991324 42 35 119888 86875 1 50816 3438 129 96 12384 DSP auto 1745.7 MiB 108.53 589279 3141815 1167038 1945807 28970 2921.2 MiB 122.40 1.04 7.38717 -81468.3 -6.38717 5.54912 0.07 0.387866 0.32584 48.8479 41.3623 766630 15.1010 160642 3.16430 100455 168766 108374381 28508729 0 0 2.28639e+08 18462.4 15 3593250 39165143 -1 7.60292 5.98464 -114944 -6.60292 0 0 77.84 -1 -1 2921.2 MiB 37.56 65.2582 56.1183 2921.2 MiB -1 19.09 + stratixiv_arch.timing.xml sparcT1_core_stratixiv_arch_timing.blif common 695.98 vpr 2.32 GiB 310 4015 1 128 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2437260 173 137 92814 91975 1 60525 4454 82 61 5002 LAB auto 1682.1 MiB 328.02 905799 3923864 1456413 2412431 55020 2002.6 MiB 208.23 1.73 9.26063 -594496 -8.26063 9.26063 0.04 0.361226 0.287081 41.9149 33.3166 1241316 20.5105 280369 4.63259 192705 660207 193204537 36029492 0 0 9.19872e+07 18390.1 17 1450842 15736794 -1 9.26352 9.26352 -654561 -8.26352 0 0 33.03 -1 -1 2227.7 MiB 64.37 59.3287 48.138 2002.6 MiB -1 7.27 + stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 369.28 vpr 2.83 GiB 506 3280 76 113 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2962964 172 334 127090 94090 3 61320 3975 129 96 12384 DSP auto 1700.4 MiB 92.28 509805 3655075 1361648 2244810 48617 2893.5 MiB 106.78 1.02 7.86325 -61457.1 -6.86325 3.46836 0.06 0.267265 0.217852 32.269 26.2483 592827 9.66870 127681 2.08241 120500 173662 60165583 13187056 0 0 2.28639e+08 18462.4 15 3593250 39165143 -1 7.51746 3.25652 -73809.5 -6.51746 0 0 72.77 -1 -1 2893.5 MiB 24.19 43.7993 36.2426 2893.5 MiB -1 18.65 + stratixiv_arch.timing.xml cholesky_mc_stratixiv_arch_timing.blif common 617.64 vpr 3.09 GiB 262 4762 59 444 16 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3240764 111 151 140214 108592 1 66275 5543 125 93 11625 M9K auto 1990.3 MiB 151.48 788106 6330929 2486828 3764499 79602 2999.8 MiB 232.35 1.87 6.96286 -206320 -5.96286 6.96286 0.07 0.500192 0.409213 65.7757 53.6456 1136243 17.1454 244932 3.69592 141963 302339 243323807 67066242 0 0 2.14511e+08 18452.6 16 3364308 36745094 -1 7.39694 7.39694 -298154 -6.39694 0 0 72.75 -1 -1 2999.8 MiB 72.42 87.4449 72.7019 2999.8 MiB -1 18.74 + stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 12065.34 vpr 19.50 GiB 319 61499 240 2535 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 20448212 62 257 1374456 930989 2 664817 64593 317 235 74495 M9K auto 11400.2 MiB 1468.30 10830328 216389546 87578779 128174025 636742 16624.7 MiB 9036.53 60.52 9.32838 -1.81224e+06 -8.32838 8.21814 0.64 3.49044 2.85081 631.297 518.226 11749927 17.6766 2324437 3.49689 1382377 2282905 1372376586 322363776 0 0 1.38707e+09 18619.7 14 21381670 236483135 -1 9.87707 8.61989 -2.31232e+06 -8.87707 0 0 423.56 -1 -1 16912.8 MiB 478.20 764.49 633.315 16624.7 MiB -1 172.48 + stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 10920.08 vpr 14.34 GiB 385 35914 0 1331 0 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 15035900 353 32 1446409 1087537 2 802897 37631 236 175 41300 LAB auto 8407.9 MiB 1399.69 8069197 81976111 30515078 50803021 658012 10893.4 MiB 8471.96 46.28 8.82853 -897986 -7.82853 8.82853 0.36 2.98543 2.55333 437.471 361.343 9365241 11.6644 2162474 2.69335 1742182 2571548 800029867 152528004 0 0 7.64522e+08 18511.4 17 11894042 131060469 -1 10.6871 10.6871 -1.2059e+06 -9.68713 0 0 248.62 -1 -1 12829.4 MiB 335.71 579.023 482.876 10893.4 MiB -1 83.17 + stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 6630.33 vpr 19.49 GiB 373 16678 116 5040 16 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 20438700 178 195 663067 568001 2 406083 22223 430 319 137170 M9K auto 5700.6 MiB 1488.67 15354107 51862695 21830000 29930794 101901 19959.7 MiB 3209.27 16.23 26.6172 -3.23472e+06 -25.6172 8.81163 0.75 2.90058 2.38659 503.078 413.353 16386901 40.3553 3026953 7.45434 917037 1739755 1410990275 326533180 0 0 2.57820e+09 18795.6 12 39390806 435738327 -1 24.6154 10.5061 -5.75347e+06 -23.6154 0 0 818.19 -1 -1 19959.7 MiB 464.81 608.245 504.614 19959.7 MiB -1 324.73 + stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 8193.12 vpr 12.67 GiB 1891 33747 3 506 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 13287440 815 1076 764693 760412 1423 413569 36147 280 207 57960 io auto 6871.9 MiB 2170.60 6321041 78292272 33005860 44758558 527854 11353.3 MiB 4815.14 29.77 17.7516 -4.16163e+06 -16.7516 4.89119 0.49 2.87248 2.26378 416.975 332.994 7527876 18.5260 1630241 4.01199 988164 3143557 705151553 127852079 0 0 1.07374e+09 18525.6 21 16684552 184042692 -1 17.843 5.02145 -4.80984e+06 -16.843 0 0 356.76 -1 -1 11473.0 MiB 368.46 581.186 470.324 11353.3 MiB -1 125.64 + stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6013.51 vpr 11.23 GiB 399 31093 112 1175 0 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 11773592 85 185 721554 630079 28 405002 32781 220 163 35860 LAB auto 6475.5 MiB 1002.80 5178404 84458444 33598600 50279421 580423 8860.1 MiB 4172.19 24.46 8.14669 -688925 -7.14669 5.20564 0.32 2.89777 2.30021 490.741 391.133 6249071 15.4486 1362456 3.36819 825418 1759906 637573300 144402801 0 0 6.64232e+08 18522.9 14 10351778 113707977 -1 8.89873 5.39961 -915798 -7.89873 0 0 217.47 -1 -1 10398.8 MiB 253.99 604.773 489.305 8860.1 MiB -1 69.95 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph/config/golden_results.txt index 94c339dadc7..2bd7b64568f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph/config/golden_results.txt @@ -1,6 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 15.44 0.32 30784 3 1.53 -1 -1 39924 -1 -1 100 214 0 8 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 72096 214 305 2963 2869 1 1462 627 19 19 361 io auto 1.29 11329 1.92 0.02 4.35337 -2516.86 -4.35337 4.35337 0.06 0.00328107 0.00285296 0.738956 0.625763 20096 -1 -1 -1 -1 1.72706e+07 8.5574e+06 2.90560e+06 8048.76 17 4.76636 4.76636 -2957.47 -4.76636 0 0 0.58 0.953726 0.825808 1.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 15.47 0.42 30800 3 1.31 -1 -1 39976 -1 -1 111 214 0 8 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 70728 214 305 2963 2869 1 1440 638 19 19 361 io auto 2.27 10427 1.32 0.01 4.36814 -2472.84 -4.36814 4.36814 0.05 0.00317149 0.00278315 0.443043 0.379506 17186 -1 -1 -1 -1 1.72706e+07 9.15023e+06 2.71656e+06 7525.11 12 4.72208 4.72208 -2856.74 -4.72208 0 0 0.43 0.616587 0.542339 0.70 - k6_frac_N10_mem32K_40nm.xml raygentop.v common 17.49 0.42 31904 8 1.69 -1 -1 40332 -1 -1 104 214 0 9 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 68708 214 305 2625 2741 1 1440 632 22 22 484 mult_36 auto 2.50 11461 1.44 0.02 4.30553 -2458.71 -4.30553 4.30553 0.09 0.00294167 0.00252875 0.478138 0.403453 18517 -1 -1 -1 -1 2.50602e+07 9.16898e+06 3.71564e+06 7676.94 12 5.02187 5.02187 -2941.43 -5.02187 0 0 0.53 0.630845 0.545873 0.89 - k6_N10_mem32K_40nm.xml raygentop.v common 17.74 0.33 31864 8 1.76 -1 -1 40228 -1 -1 164 214 0 9 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 65808 214 305 2625 2741 1 1482 692 22 22 484 mult_36 auto 0.65 12264 1.70 0.02 4.21675 -2419.09 -4.21675 4.21675 0.14 0.00304558 0.00252583 0.51155 0.423932 18017 -1 -1 -1 -1 2.50602e+07 1.24026e+07 3.52243e+06 7277.74 49 4.898 4.898 -2810.42 -4.898 0 0 2.32 0.867474 0.743958 1.39 - hard_fpu_arch_timing.xml raygentop.v common 159.25 0.60 66344 38 100.76 -1 -1 67464 -1 -1 2217 211 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 229228 211 305 9491 9796 1 6956 2733 53 53 2809 clb auto 1.57 68376 10.58 0.09 21.0864 -5585.28 -21.0864 21.0864 0.42 0.0102485 0.00869648 1.45593 1.02314 106554 -1 -1 -1 -1 5.87942e+06 5.0818e+06 1.13971e+07 4057.33 27 22.8705 22.8705 -6341.42 -22.8705 -0.0851 -0.0851 3.38 2.35962 1.78429 4.77 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 18.10 vpr 84.26 MiB 0.49 31568 -1 -1 3 1.10 -1 -1 40400 -1 -1 119 214 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86280 214 305 2963 2869 1 1465 646 19 19 361 io auto 42.9 MiB 2.38 11473 279746 97784 164344 17618 84.3 MiB 2.03 0.03 4.50048 -2595.18 -4.50048 4.50048 0.00 0.00847397 0.00785036 0.847998 0.78148 -1 -1 -1 -1 19540 13.4666 5175 3.56651 4591 11814 1372016 333143 1.72706e+07 9.58139e+06 2.90560e+06 8048.76 12 52798 501983 -1 4.7575 4.7575 -2835.11 -4.7575 0 0 0.44 -1 -1 84.3 MiB 0.59 1.16192 1.07597 84.3 MiB -1 0.10 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 16.87 vpr 84.21 MiB 0.49 31612 -1 -1 3 1.08 -1 -1 40360 -1 -1 123 214 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86232 214 305 2963 2869 1 1444 650 19 19 361 io auto 43.2 MiB 2.84 11413 231398 76618 140983 13797 84.2 MiB 1.01 0.02 4.67106 -2660.25 -4.67106 4.67106 0.00 0.0042158 0.00385403 0.364929 0.335739 -1 -1 -1 -1 17576 12.2909 4673 3.26783 3635 8404 916352 219992 1.72706e+07 9.79696e+06 2.71656e+06 7525.11 13 49483 447175 -1 4.79628 4.79628 -2823.47 -4.79628 0 0 0.33 -1 -1 84.2 MiB 0.32 0.56686 0.527395 84.2 MiB -1 0.09 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 19.25 vpr 79.38 MiB 0.51 32832 -1 -1 8 1.59 -1 -1 40644 -1 -1 117 214 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 81284 214 305 2625 2741 1 1438 645 22 22 484 mult_36 auto 38.5 MiB 2.62 11780 287500 97684 170577 19239 79.4 MiB 1.98 0.03 4.70477 -2668 -4.70477 4.70477 0.00 0.00775198 0.00716962 0.832076 0.767666 -1 -1 -1 -1 18108 12.7074 4758 3.33895 3393 7424 854677 202496 2.50602e+07 9.8696e+06 3.71564e+06 7676.94 15 65910 614443 -1 4.88861 4.88861 -2835.89 -4.88861 0 0 0.57 -1 -1 79.4 MiB 0.53 1.15898 1.07234 79.4 MiB -1 0.13 + k6_N10_mem32K_40nm.xml raygentop.v common 16.82 vpr 78.59 MiB 0.51 32832 -1 -1 8 1.69 -1 -1 40844 -1 -1 198 214 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80472 214 305 2625 2741 1 1415 726 22 22 484 mult_36 auto 37.4 MiB 1.14 12153 264867 85581 162230 17056 78.6 MiB 1.77 0.02 4.91361 -2793.64 -4.91361 4.91361 0.00 0.00766742 0.0070794 0.656327 0.603669 -1 -1 -1 -1 16547 11.8024 4369 3.11626 6679 17662 2743548 596669 2.50602e+07 1.4235e+07 3.52243e+06 7277.74 26 57210 572443 -1 4.90022 4.90022 -2862.69 -4.90022 0 0 0.55 -1 -1 78.6 MiB 0.94 1.10615 1.01763 78.6 MiB -1 0.12 + hard_fpu_arch_timing.xml raygentop.v common 138.65 vpr 231.80 MiB 0.99 70388 -1 -1 38 69.46 -1 -1 68188 -1 -1 2403 211 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 237368 211 305 9491 9796 1 6660 2919 55 55 3025 clb auto 80.5 MiB 2.31 66631 1817043 654938 1126978 35127 231.8 MiB 13.17 0.11 26.0917 -6594.81 -26.0917 26.0917 0.00 0.0168338 0.0140529 2.38382 2.05463 -1 -1 -1 -1 110311 16.5956 28136 4.23289 74198 194987 16052984 1871492 6.31033e+06 5.50811e+06 1.22764e+07 4058.32 35 255054 2544855 -1 23.6419 23.6419 -6371.61 -23.6419 -0.0851 -0.0851 2.53 -1 -1 231.8 MiB 5.25 4.12195 3.55168 231.8 MiB -1 0.79 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_bidir/config/golden_results.txt index 36fa7bb0a1b..5f9d2a62a25 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_bidir/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - k4_n4_v7_bidir.xml dsip.blif common 27.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 118552 229 197 1815 2012 1 1190 816 29 29 841 io auto 0.33 11648 1.49 0.02 7.41386 -1808.21 -7.41386 7.41386 0.61 0.0021178 0.0016946 0.281919 0.225954 15856 -1 -1 -1 -1 2.187e+07 1.17e+07 -1 -1 20 9.24582 9.24582 -2352.55 -9.24582 0 0 0.83 0.391481 0.321957 5.69 - k4_n4_v7_bidir.xml elliptic.blif common 48.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 996 131 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 169988 131 114 4855 4969 1 2150 1241 34 34 1156 clb auto 0.88 31542 3.21 0.03 21.1193 -11571.9 -21.1193 21.1193 0.90 0.00449081 0.00368456 0.662064 0.449287 40462 -1 -1 -1 -1 3.072e+07 2.988e+07 -1 -1 20 26.9983 26.9983 -14687.8 -26.9983 0 0 1.69 1.0392 0.770433 7.04 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k4_n4_v7_bidir.xml dsip.blif common 24.15 vpr 129.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 443 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 132104 229 197 1815 2012 1 1190 869 29 29 841 io auto 28.1 MiB 0.38 11808 386354 130262 246701 9391 129.0 MiB 1.99 0.02 8.26026 -2002.89 -8.26026 8.26026 0.00 0.00522947 0.00475426 0.50234 0.458325 -1 -1 -1 -1 14837 12.4786 3857 3.24390 5280 18595 4288015 314127 2.187e+07 1.329e+07 -1 -1 12 141714 3348831 -1 10.3649 10.3649 -2489.23 -10.3649 0 0 1.93 -1 -1 129.0 MiB 0.71 0.66274 0.604038 129.0 MiB -1 0.64 + k4_n4_v7_bidir.xml elliptic.blif common 39.80 vpr 178.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1023 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 182672 131 114 4855 4969 1 2112 1268 34 34 1156 clb auto 44.4 MiB 0.83 31400 563788 196591 359179 8018 178.4 MiB 3.77 0.04 22.2892 -11723.6 -22.2892 22.2892 0.00 0.0101629 0.00906485 0.918798 0.79034 -1 -1 -1 -1 40056 18.9749 10269 4.86452 9570 44105 8008892 526134 3.072e+07 3.069e+07 -1 -1 19 194754 4643496 -1 27.7541 27.7541 -14616.1 -27.7541 0 0 2.78 -1 -1 178.4 MiB 1.65 1.38449 1.19731 178.4 MiB -1 0.94 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_complex_switch/config/golden_results.txt index a3bec08d847..ab193c4d4af 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_complex_switch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 29.30 0.39 31692 12 1.62 -1 -1 37060 -1 -1 238 214 0 9 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 91116 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.46 16418 1.91 0.02 3.92422 -1914.18 -3.92422 3.92422 0.10 0.00303059 0.00265402 0.424989 0.354567 24730 -1 -1 -1 -1 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 4.06116 4.06116 -2255.58 -4.06116 0 0 1.44 0.597094 0.511983 5.30 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 24.33 vpr 90.75 MiB 0.51 32872 -1 -1 12 1.55 -1 -1 40880 -1 -1 238 214 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 92924 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 35.0 MiB 0.55 17879 291515 96968 176018 18529 90.7 MiB 2.29 0.03 4.04097 -2026.17 -4.04097 4.04097 0.00 0.00789147 0.00729898 0.68601 0.631189 -1 -1 -1 -1 25655 11.8335 11525 5.31596 7010 22783 3120920 787237 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 154908 1423382 -1 4.23901 4.23901 -2367.29 -4.23901 0 0 2.25 -1 -1 90.7 MiB 0.90 1.00021 0.919765 90.7 MiB -1 0.66 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_error_check/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_error_check/config/golden_results.txt index 7e7ccf79b1f..d6391fd6791 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_error_check/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_error_check/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 12.84 0.38 31704 12 2.23 -1 -1 37112 -1 -1 238 214 0 9 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 74736 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.66 16553 2.42 0.03 3.96803 -1941.86 -3.96803 3.96803 0.09 0.0050075 0.00438498 0.553215 0.461746 25791 -1 -1 -1 -1 3.88769e+06 1.9974e+06 3.89335e+06 5759.39 17 4.2505 4.2505 -2428.8 -4.2505 0 0 1.81 0.756122 0.644202 2.88 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 10.04 vpr 76.59 MiB 0.56 32824 -1 -1 12 1.57 -1 -1 41056 -1 -1 238 214 0 9 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 78432 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 35.0 MiB 0.55 18203 298521 99577 180379 18565 76.6 MiB 2.21 0.03 4.02384 -2044.4 -4.02384 4.02384 0.00 0.0078973 0.00729681 0.668637 0.615335 -1 -1 -1 -1 27105 12.5023 12496 5.76384 9844 29663 3742250 1056449 3.88769e+06 1.9974e+06 3.89335e+06 5759.39 18 97004 733416 -1 4.47172 4.47172 -2442.55 -4.47172 0 0 1.15 -1 -1 76.6 MiB 1.23 1.03037 0.946995 76.6 MiB -1 0.36 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_titan/config/golden_results.txt index 067a8cc5230..d3376c5e4de 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vpr_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1504.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 2859008 42 35 119888 86875 1 51143 3418 129 96 12384 DSP auto 85.58 583323 119.39 0.71 7.89477 -209772 -7.89477 7.89477 208.83 0.200591 0.17182 32.4665 25.7145 744976 -1 -1 -1 -1 0 0 2.28642e+08 18462.7 33 8.25962 8.25962 -264487 -8.25962 0 0 57.37 50.95 41.9616 169.27 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 993.75 vpr 2.85 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2990508 42 35 119888 86875 1 50848 3434 129 96 12384 DSP auto 1744.8 MiB 110.48 593082 3188765 1210302 1953134 25329 2920.4 MiB 131.36 1.01 7.82707 -223897 -7.82707 7.82707 0.07 0.35368 0.316469 47.6901 41.67 -1 -1 -1 -1 760648 14.9737 161961 3.18827 105791 178983 117012215 31658104 0 0 2.28639e+08 18462.4 15 3593250 39165143 -1 8.06159 8.06159 -257707 -8.06159 0 0 77.71 -1 -1 2920.4 MiB 39.46 63.6187 56.0573 2920.4 MiB -1 21.95 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt index 79387b20d65..9d333670603 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt @@ -1,41 +1,41 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_n4_v7_bidir.xml alu4.blif common 14.12 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 477 14 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68808 14 8 1536 1544 0 1088 499 24 24 576 clb auto 26.9 MiB 0.35 13713 125113 37636 85702 1775 67.2 MiB 0.83 0.01 14.0421 -101.788 -14.0421 nan 0.89 0.00337182 0.00294136 0.228232 0.201212 28 19990 27 1.452e+07 1.431e+07 -1 -1 8.35 1.31835 1.12022 21174 279108 -1 19228 18 7062 27087 2139856 196285 17.1451 nan -119.753 -17.1451 0 0 -1 -1 0.37 0.58 0.16 -1 -1 0.37 0.149382 0.130325 -k4_n4_v7_bidir.xml apex2.blif common 20.08 vpr 69.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 598 38 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71168 38 3 1916 1919 0 1508 639 27 27 729 clb auto 29.3 MiB 0.47 20032 176703 52353 120171 4179 69.5 MiB 1.23 0.02 17.5139 -50.2777 -17.5139 nan 1.17 0.00472981 0.00411722 0.317696 0.278113 31 29578 36 1.875e+07 1.794e+07 -1 -1 12.05 1.72453 1.47135 28210 394495 -1 28636 22 10688 37557 3476301 294242 20.8295 nan -58.5593 -20.8295 0 0 -1 -1 0.56 1.01 0.23 -1 -1 0.56 0.253299 0.22082 -k4_n4_v7_bidir.xml apex4.blif common 15.04 vpr 65.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 410 9 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66588 9 19 1271 1290 0 989 438 23 23 529 clb auto 25.5 MiB 0.27 13508 95172 26074 67665 1433 65.0 MiB 0.65 0.01 13.1269 -216.571 -13.1269 nan 0.83 0.00276239 0.0024392 0.1738 0.155352 31 20275 34 1.323e+07 1.23e+07 -1 -1 9.83 1.0323 0.884588 20514 283063 -1 18947 16 6713 24480 2299733 193456 16.0497 nan -259.266 -16.0497 0 0 -1 -1 0.39 0.53 0.16 -1 -1 0.39 0.116433 0.102846 -k4_n4_v7_bidir.xml bigkey.blif common 19.30 vpr 69.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 456 229 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71668 229 197 2152 2349 1 1587 882 29 29 841 io auto 29.8 MiB 0.34 12720 440594 137247 291517 11830 70.0 MiB 2.20 0.02 8.05109 -1841.77 -8.05109 8.05109 1.37 0.00589079 0.00536855 0.626379 0.566795 18 20694 46 2.187e+07 1.368e+07 -1 -1 10.54 2.27299 2.02358 25794 279159 -1 18007 20 8342 23483 1514225 162064 9.13231 9.13231 -2338.69 -9.13231 0 0 -1 -1 0.39 0.61 0.17 -1 -1 0.39 0.250982 0.22507 -k4_n4_v7_bidir.xml clma.blif common 125.73 vpr 199.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2521 62 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 204696 62 82 8460 8542 1 6346 2665 53 53 2809 clb auto 74.6 MiB 2.08 106112 1720282 687942 1019943 12397 191.1 MiB 12.56 0.13 27.7798 -1475.05 -27.7798 27.7798 5.67 0.0212825 0.0174879 2.07784 1.7299 39 139827 30 7.803e+07 7.563e+07 -1 -1 77.34 8.16732 6.70717 121914 1953961 -1 145653 37 50338 174644 40465788 3496071 37.5154 37.5154 -1994.17 -37.5154 0 0 -1 -1 3.29 8.98 1.16 -1 -1 3.29 1.60084 1.35094 -k4_n4_v7_bidir.xml des.blif common 21.96 vpr 73.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 449 256 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75736 256 245 1847 2092 0 1443 950 34 34 1156 io auto 28.6 MiB 0.43 15858 337046 106006 219615 11425 74.0 MiB 1.69 0.02 13.6482 -2283.71 -13.6482 nan 2.03 0.00653534 0.00597695 0.503268 0.461334 18 23829 44 3.072e+07 1.347e+07 -1 -1 11.46 2.34979 2.13492 35364 387024 -1 21475 27 8540 28313 2203704 220439 16.6899 nan -2838.96 -16.6899 0 0 -1 -1 0.56 0.82 0.23 -1 -1 0.56 0.360996 0.330838 -k4_n4_v7_bidir.xml diffeq.blif common 12.81 vpr 67.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 415 64 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69116 64 39 1935 1974 1 1102 518 23 23 529 clb auto 27.8 MiB 0.35 9992 137732 37830 95961 3941 67.5 MiB 0.95 0.01 13.4033 -2671.54 -13.4033 13.4033 0.80 0.00428173 0.00383691 0.312705 0.277181 24 14332 21 1.323e+07 1.245e+07 -1 -1 7.02 1.61062 1.38241 18402 227975 -1 13634 22 6342 21307 1309693 133684 15.9009 15.9009 -3236.59 -15.9009 0 0 -1 -1 0.30 0.50 0.13 -1 -1 0.30 0.20143 0.175765 -k4_n4_v7_bidir.xml dsip.blif common 17.77 vpr 67.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68900 229 197 1815 2012 1 1190 816 29 29 841 io auto 27.5 MiB 0.32 11545 347617 108721 229249 9647 67.3 MiB 1.74 0.02 7.21771 -1868.83 -7.21771 7.21771 1.36 0.00565774 0.00516606 0.524959 0.478887 18 18641 50 2.187e+07 1.17e+07 -1 -1 9.76 2.03171 1.82626 25794 279159 -1 15915 19 6571 20190 1355499 141050 8.71824 8.71824 -2334.27 -8.71824 0 0 -1 -1 0.39 0.53 0.17 -1 -1 0.39 0.218562 0.197453 -k4_n4_v7_bidir.xml elliptic.blif common 55.36 vpr 90.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1000 131 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 93164 131 114 4855 4969 1 2139 1245 34 34 1156 clb auto 44.4 MiB 0.80 31454 550235 189587 353717 6931 90.2 MiB 3.44 0.04 23.2801 -11982.4 -23.2801 23.2801 1.99 0.0102012 0.00912611 0.93124 0.796503 29 50282 41 3.072e+07 3e+07 -1 -1 39.75 4.26668 3.61139 43448 604980 -1 46002 25 13205 58637 9554007 846071 38.8565 38.8565 -19809.8 -38.8565 0 0 -1 -1 0.87 2.29 0.35 -1 -1 0.87 0.550161 0.477667 -k4_n4_v7_bidir.xml ex1010.blif common 70.88 vpr 117.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1507 10 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 120624 10 10 4608 4618 0 3617 1527 41 41 1681 clb auto 49.0 MiB 1.01 44970 713436 251975 459721 1740 117.8 MiB 5.24 0.06 23.5124 -229.462 -23.5124 nan 3.18 0.0097988 0.00855656 0.894426 0.754306 28 68638 30 4.563e+07 4.521e+07 -1 -1 49.13 4.21383 3.49296 61362 838935 -1 63940 21 25222 100656 7392341 708511 28.5457 nan -270.488 -28.5457 0 0 -1 -1 1.32 2.31 0.49 -1 -1 1.32 0.568954 0.493491 -k4_n4_v7_bidir.xml ex5p.blif common 10.49 vpr 63.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 342 8 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65140 8 63 1072 1135 0 906 413 21 21 441 clb auto 24.3 MiB 0.26 11449 84948 23521 59664 1763 63.6 MiB 0.57 0.01 12.8622 -575.489 -12.8622 nan 0.65 0.0025827 0.00230286 0.159252 0.143541 35 17128 25 1.083e+07 1.026e+07 -1 -1 5.53 0.949583 0.821185 18442 269153 -1 17835 36 8694 28272 4470817 400190 22.7431 nan -871.031 -22.7431 0 0 -1 -1 0.35 0.95 0.15 -1 -1 0.35 0.19761 0.170925 -k4_n4_v7_bidir.xml frisc.blif common 42.63 vpr 94.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1051 20 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 96356 20 116 4445 4561 1 2326 1187 35 35 1225 clb auto 43.5 MiB 0.91 37678 522593 180255 332319 10019 91.3 MiB 3.77 0.04 26.7351 -13400.3 -26.7351 26.7351 2.15 0.0120194 0.0108773 1.0849 0.940114 35 54338 28 3.267e+07 3.153e+07 -1 -1 24.33 3.94847 3.3672 50922 772933 -1 56811 45 18725 83358 16216109 1534592 31.802 31.802 -18151.6 -31.802 0 0 -1 -1 1.17 3.76 0.44 -1 -1 1.17 0.873991 0.748271 -k4_n4_v7_bidir.xml misex3.blif common 18.72 vpr 65.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 431 14 -1 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67172 14 14 1411 1425 0 1079 459 23 23 529 clb auto 26.0 MiB 0.34 13374 101292 28145 71403 1744 65.6 MiB 0.68 0.01 13.1746 -165.157 -13.1746 nan 0.79 0.00303589 0.00266696 0.186267 0.165347 29 21582 50 1.323e+07 1.293e+07 -1 -1 13.16 1.49464 1.27631 19986 270173 -1 20352 22 8774 29285 3704651 332778 24.3868 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vpr 63.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 367 8 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65236 8 63 1072 1135 0 898 438 22 22 484 clb auto 24.3 MiB 0.28 11915 106806 31455 73557 1794 63.7 MiB 0.76 0.01 16.2558 -718.217 -16.2558 nan 0.48 0.00266047 0.00239417 0.186827 0.16858 -1 -1 -1 -1 24 13413 30 1.2e+07 1.101e+07 -1 -1 18.57 1.14807 0.989575 36000 257712 -1 11900 15 6787 23733 1853955 288518 16.2529 nan -726.803 -16.2529 0 0 -1 -1 0.05 0.53 0.19 -1 -1 0.05 0.103498 0.0915159 + k4_n4_v7_l1_bidir.xml frisc.blif common 38.93 vpr 121.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1094 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 123968 20 116 4445 4561 1 2290 1230 36 36 1296 clb auto 44.0 MiB 1.00 38255 580886 202911 367450 10525 121.0 MiB 4.07 0.05 29.223 -16576.9 -29.223 29.223 1.13 0.0106484 0.00904003 0.940065 0.801656 -1 -1 -1 -1 26 40614 39 3.468e+07 3.282e+07 -1 -1 24.94 2.98417 2.53653 104992 763300 -1 37284 18 13336 60167 5347576 900846 28.6821 28.6821 -16996 -28.6821 0 0 -1 -1 0.20 1.82 0.58 -1 -1 0.20 0.419427 0.365252 + k4_n4_v7_l1_bidir.xml misex3.blif common 45.92 vpr 66.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 450 14 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67696 14 14 1411 1425 0 1056 478 24 24 576 clb auto 26.5 MiB 0.37 13799 121898 36530 83432 1936 66.1 MiB 0.90 0.01 18.1166 -222.755 -18.1166 nan 0.60 0.00309451 0.00272996 0.216068 0.191921 -1 -1 -1 -1 21 15917 38 1.452e+07 1.35e+07 -1 -1 40.79 1.44479 1.22595 39160 271852 -1 13861 19 6925 26912 1892268 324238 17.8372 nan -222.89 -17.8372 0 0 -1 -1 0.06 0.64 0.20 -1 -1 0.06 0.144778 0.126476 + k4_n4_v7_l1_bidir.xml pdc.blif common 185.86 vpr 161.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1606 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 165376 16 40 4591 4631 0 3616 1662 43 43 1849 clb auto 50.5 MiB 1.46 71388 995502 386267 603819 5416 155.7 MiB 7.79 0.07 36.0567 -1232.66 -36.0567 nan 2.17 0.0114444 0.00941235 1.37422 1.1363 -1 -1 -1 -1 34 83956 48 5.043e+07 4.818e+07 -1 -1 161.61 5.08837 4.17381 185730 1416087 -1 74292 16 24740 103095 11970321 1866116 34.9964 nan -1210.26 -34.9964 0 0 -1 -1 0.37 3.70 1.22 -1 -1 0.37 0.489235 0.420817 + k4_n4_v7_l1_bidir.xml s298.blif common 12.12 vpr 70.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 573 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71732 4 6 1942 1948 1 1167 583 26 26 676 clb auto 29.8 MiB 0.37 13721 168529 51547 115716 1266 70.1 MiB 0.87 0.01 26.8992 -206.444 -26.8992 26.8992 0.51 0.00299887 0.00257425 0.223433 0.19287 -1 -1 -1 -1 17 15103 41 1.728e+07 1.719e+07 -1 -1 6.67 0.869853 0.739775 39072 254696 -1 13708 17 7890 40380 2928639 390491 25.7904 25.7904 -205.684 -25.7904 0 0 -1 -1 0.06 0.93 0.19 -1 -1 0.06 0.19636 0.172164 + k4_n4_v7_l1_bidir.xml s38417.blif common 85.43 vpr 189.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1852 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 194024 29 106 7534 7640 1 4623 1987 46 46 2116 clb auto 62.1 MiB 1.48 45682 1150699 423694 711314 15691 189.5 MiB 8.94 0.10 24.016 -14000.6 -24.016 24.016 2.52 0.0168312 0.0139048 1.65489 1.37293 -1 -1 -1 -1 16 41981 27 5.808e+07 5.556e+07 -1 -1 61.09 6.8711 5.59216 118272 756192 -1 39731 15 23886 81328 4350389 861432 23.6137 23.6137 -14728 -23.6137 0 0 -1 -1 0.21 2.06 0.61 -1 -1 0.21 0.672518 0.576412 + k4_n4_v7_l1_bidir.xml s38584.1.blif common 89.69 vpr 183.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1787 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 187676 38 304 7475 7779 1 4320 2129 45 45 2025 clb auto 61.8 MiB 1.45 43799 1343749 517594 801490 24665 183.3 MiB 9.55 0.12 21.0587 -13121.7 -21.0587 21.0587 2.33 0.0205892 0.0168564 1.8726 1.54631 -1 -1 -1 -1 16 39654 47 5.547e+07 5.361e+07 -1 -1 65.95 7.05965 5.7985 113090 722879 -1 37482 13 19902 66283 3641519 680597 20.2436 20.2436 -13770 -20.2436 0 0 -1 -1 0.19 1.67 0.56 -1 -1 0.19 0.582155 0.503652 + k4_n4_v7_l1_bidir.xml seq.blif common 39.04 vpr 69.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 567 41 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 71060 41 35 1791 1826 0 1347 643 26 26 676 clb auto 28.8 MiB 0.45 18608 203145 65187 132320 5638 69.4 MiB 1.45 0.02 18.1385 -520.265 -18.1385 nan 0.69 0.00440251 0.00379688 0.341235 0.296573 -1 -1 -1 -1 24 20201 48 1.728e+07 1.701e+07 -1 -1 32.66 1.86519 1.57725 51072 366016 -1 19098 15 8908 34158 2699342 394310 17.881 nan -530.81 -17.881 0 0 -1 -1 0.08 0.84 0.27 -1 -1 0.08 0.169259 0.148746 + k4_n4_v7_l1_bidir.xml spla.blif common 55.44 vpr 130.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1282 16 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 133644 16 46 3706 3752 0 2852 1344 38 38 1444 clb auto 43.3 MiB 0.97 48851 705674 261242 438237 6195 130.4 MiB 5.28 0.05 28.2789 -928.469 -28.2789 nan 1.62 0.00915224 0.00762446 0.960488 0.808085 -1 -1 -1 -1 30 55651 36 3.888e+07 3.846e+07 -1 -1 38.42 2.90573 2.41614 133344 1000208 -1 49871 15 17906 78246 6885546 1014380 27.1504 nan -941.372 -27.1504 0 0 -1 -1 0.25 2.26 0.77 -1 -1 0.25 0.363869 0.316143 + k4_n4_v7_l1_bidir.xml tseng.blif common 11.07 vpr 64.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 292 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65992 52 122 1483 1605 1 725 466 20 20 400 clb auto 25.0 MiB 0.25 6135 112438 30480 78177 3781 64.4 MiB 0.73 0.01 11.1777 -2780.46 -11.1777 11.1777 0.38 0.00330812 0.00294725 0.224125 0.201235 -1 -1 -1 -1 14 6150 30 9.72e+06 8.76e+06 -1 -1 7.57 1.13613 0.985613 19872 120996 -1 5573 18 4232 15969 711167 147306 11.3812 11.3812 -3151.62 -11.3812 0 0 -1 -1 0.03 0.33 0.09 -1 -1 0.03 0.136984 0.120602 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_func_formal/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_func_formal/config/golden_results.txt index a64f0a882d0..9878ca23cf5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_func_formal/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_func_formal/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time placement_technique reward uniform_percentage median_percentage wmedian_percentage wcent_percentage fr_percentage critUni_percentage centroid_percentage - k6_frac_N10_40nm.xml sha.v common 2075.74 0.69 36476 20 506.72 -1 -1 95572 -1 -1 208 38 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 75108 38 36 3404 3440 1 1290 282 17 17 289 clb auto 1.64 12508 1.22 0.01 11.3503 -3905.76 -11.3503 11.3503 0.02 0.00324856 0.00264942 0.47841 0.349287 -1 17462 12 1.21262e+07 1.121e+07 3.33009e+06 11522.8 0.29 0.692138 0.542275 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml stereovision3.v common 1.42 0.05 8820 4 0.11 -1 -1 33040 -1 -1 13 11 -1 -1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 25032 23 30 262 304 2 110 66 6 6 36 clb auto 0.09 358 0.09 0.00 2.24318 -154.283 -2.24318 2.0857 0.00 0.000283319 0.000227979 0.0465577 0.036372 -1 397 9 862304 700622 300248. 8340.23 0.02 0.0593364 0.0478995 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml sha.v common 1573.18 abc 94.10 MiB 2.09 38248 -1 -1 20 467.44 -1 -1 96356 -1 -1 207 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82452 38 36 3404 3440 1 1294 281 17 17 289 clb auto 38.8 MiB 2.28 12837 53641 12833 37659 3149 80.5 MiB 1.12 0.02 13.5016 -4515.69 -13.5016 13.5016 0.00 0.00752789 0.00668401 0.495491 0.4378 -1 -1 -1 -1 -1 17934 16 1.21262e+07 1.11561e+07 3.33009e+06 11522.8 0.50 0.863052 0.768227 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml stereovision3.v common 1.63 vpr 58.65 MiB 0.08 9400 -1 -1 4 0.15 -1 -1 33352 -1 -1 13 11 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 60056 23 30 262 304 2 110 66 6 6 36 clb auto 19.5 MiB 0.09 409 2593 543 1856 194 58.6 MiB 0.02 0.00 2.55648 -171.328 -2.55648 2.31607 0.00 0.00037611 0.000333951 0.0105184 0.00953081 -1 -1 -1 -1 -1 426 9 862304 700622 300248. 8340.23 0.02 0.0265046 0.024223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_multiclock_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_multiclock_mcnc/config/golden_results.txt index 76aa77f8ebe..f952fd79e3d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_multiclock_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_multiclock_mcnc/config/golden_results.txt @@ -1,11 +1,11 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml bigkey.blif common 15.50 vpr 63.39 MiB -1 -1 -1 -1 3 0.37 -1 -1 34844 -1 -1 53 229 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64912 229 197 1023 1220 1 510 479 16 16 256 io auto 24.2 MiB 0.27 3412 154065 46239 98678 9148 63.4 MiB 0.95 0.01 2.41239 -578.515 -2.41239 2.41239 0.79 0.00631748 0.00590554 0.537724 0.50284 34 6563 36 1.05632e+07 2.85638e+06 613832. 2397.78 10.54 3.12398 2.91529 24564 122629 -1 5999 13 1330 2398 156004 35692 2.69369 2.69369 -639.318 -2.69369 0 0 751777. 2936.63 0.21 0.25 0.16 -1 -1 0.21 0.197289 0.185691 -k6_frac_N10_40nm.xml clma.blif common 8.18 vpr 60.61 MiB -1 -1 -1 -1 7 2.28 -1 -1 39892 -1 -1 77 36 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62060 36 82 542 624 1 389 195 11 11 121 clb auto 21.8 MiB 0.54 2075 39180 14775 18229 6176 60.6 MiB 0.39 0.01 4.56725 -162.762 -4.56725 4.56725 0.32 0.00290424 0.00269628 0.21446 0.199553 40 4742 31 4.36541e+06 4.14984e+06 303235. 2506.08 2.72 0.896352 0.821286 11571 60661 -1 3946 19 2186 7344 217806 45734 4.7836 4.7836 -183.173 -4.7836 0 0 379421. 3135.71 0.09 0.20 0.08 -1 -1 0.09 0.124637 0.115259 -k6_frac_N10_40nm.xml diffeq.blif common 5.52 vpr 62.28 MiB -1 -1 -1 -1 8 0.40 -1 -1 34272 -1 -1 52 64 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63776 64 39 941 980 1 449 155 10 10 100 clb auto 23.5 MiB 0.73 2754 14299 2774 10573 952 62.3 MiB 0.27 0.01 5.00123 -878.262 -5.00123 5.00123 0.25 0.00444533 0.00408514 0.170524 0.156838 46 4930 28 3.44922e+06 2.80249e+06 276332. 2763.32 2.10 0.960344 0.875051 9816 55112 -1 4472 14 1803 5492 169063 35103 5.16783 5.16783 -930.109 -5.16783 0 0 354105. 3541.05 0.08 0.21 0.08 -1 -1 0.08 0.15494 0.143538 -k6_frac_N10_40nm.xml dsip.blif common 9.71 vpr 64.65 MiB -1 -1 -1 -1 3 0.33 -1 -1 34640 -1 -1 68 229 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66204 229 197 1135 1332 1 648 494 16 16 256 io auto 25.3 MiB 0.73 4700 170318 50861 109699 9758 64.7 MiB 1.18 0.02 2.3875 -617.47 -2.3875 2.3875 0.78 0.00683703 0.00637878 0.619128 0.577611 34 9287 43 1.05632e+07 3.66479e+06 613832. 2397.78 3.93 2.05956 1.91939 24564 122629 -1 8151 13 2265 5666 327590 69866 2.60848 2.60848 -674.007 -2.60848 0 0 751777. 2936.63 0.21 0.32 0.16 -1 -1 0.21 0.222292 0.209372 -k6_frac_N10_40nm.xml elliptic.blif common 15.88 vpr 72.66 MiB -1 -1 -1 -1 10 1.34 -1 -1 37424 -1 -1 133 131 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 74408 131 114 2471 2585 1 970 378 14 14 196 clb auto 32.2 MiB 3.03 9165 74142 19344 51191 3607 72.7 MiB 1.13 0.02 7.14215 -3414.64 -7.14215 7.14215 0.57 0.0112416 0.0101644 0.638433 0.581928 64 15825 36 7.76074e+06 7.1679e+06 810706. 4136.26 5.95 2.90989 2.65593 22444 164128 -1 14159 17 4519 20253 781043 131442 7.47917 7.47917 -3699.02 -7.47917 0 0 1.00880e+06 5146.95 0.24 0.70 0.25 -1 -1 0.24 0.461466 0.427062 -k6_frac_N10_40nm.xml frisc.blif common 19.77 vpr 74.44 MiB -1 -1 -1 -1 12 2.03 -1 -1 37396 -1 -1 153 20 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76224 20 116 2477 2593 1 1088 289 15 15 225 clb auto 33.6 MiB 3.85 12581 59499 15581 39947 3971 74.4 MiB 1.33 0.02 8.14365 -3747.83 -8.14365 8.14365 0.64 0.0112947 0.0102836 0.764701 0.696515 74 21933 44 9.10809e+06 8.24578e+06 1.06098e+06 4715.46 8.34 3.32442 3.03038 27275 217117 -1 19654 18 5722 25295 1201911 194668 8.26982 8.26982 -3960.51 -8.26982 0 0 1.32822e+06 5903.22 0.30 0.43 0.18 -1 -1 0.30 0.243345 0.22521 -k6_frac_N10_40nm.xml s298.blif common 7.43 vpr 62.24 MiB -1 -1 -1 -1 8 0.57 -1 -1 33856 -1 -1 61 4 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63732 4 6 671 677 1 350 71 10 10 100 clb auto 23.4 MiB 0.92 3493 3283 433 2659 191 62.2 MiB 0.16 0.01 5.33805 -43.3781 -5.33805 5.33805 0.25 0.00397189 0.00366099 0.105657 0.0981952 52 5783 22 3.44922e+06 3.28753e+06 305142. 3051.42 3.75 1.33758 1.22437 10212 61796 -1 5397 17 2148 10775 376607 64965 5.90507 5.90507 -48.8576 -5.90507 0 0 401807. 4018.07 0.09 0.27 0.09 -1 -1 0.09 0.165044 0.153465 -k6_frac_N10_40nm.xml s38417.blif common 18.81 vpr 78.45 MiB -1 -1 -1 -1 6 3.02 -1 -1 42408 -1 -1 179 29 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80332 29 106 3450 3556 1 1198 314 16 16 256 clb auto 37.5 MiB 2.17 8989 70670 18144 45519 7007 78.4 MiB 1.55 0.02 4.74073 -2890.12 -4.74073 4.74073 0.79 0.0138904 0.0125607 0.984666 0.887956 48 14980 41 1.05632e+07 9.64703e+06 819368. 3200.65 6.57 4.33054 3.91711 26860 167058 -1 13212 15 5024 17286 529604 104654 4.75139 4.75139 -2966.77 -4.75139 0 0 1.04748e+06 4091.72 0.30 0.71 0.23 -1 -1 0.30 0.554676 0.511839 -k6_frac_N10_40nm.xml s38584.1.blif common 18.55 vpr 78.51 MiB -1 -1 -1 -1 6 2.16 -1 -1 40952 -1 -1 194 38 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 80396 38 304 3259 3563 1 1574 536 16 16 256 clb auto 37.8 MiB 2.15 9889 183320 55884 108640 18796 78.5 MiB 2.36 0.03 4.27217 -2394.9 -4.27217 4.27217 0.56 0.0145306 0.0132396 1.31178 1.18976 58 17695 25 1.05632e+07 1.04554e+07 977637. 3818.90 7.00 4.20263 3.82602 28644 201685 -1 15484 13 5074 13582 483608 102794 4.69981 4.69981 -2495.41 -4.69981 0 0 1.24374e+06 4858.37 0.31 0.65 0.30 -1 -1 0.31 0.521931 0.485523 -k6_frac_N10_40nm.xml tseng.blif common 4.95 vpr 60.83 MiB -1 -1 -1 -1 7 0.25 -1 -1 34444 -1 -1 34 52 -1 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62292 52 122 664 786 1 355 208 8 8 64 io clb auto 22.2 MiB 0.71 1783 26080 5856 18588 1636 60.8 MiB 0.28 0.01 4.2185 -596.347 -4.2185 4.2185 0.15 0.00333934 0.00308628 0.153624 0.142133 58 3398 46 1.94018e+06 1.8324e+06 203254. 3175.84 2.23 1.20749 1.10156 6532 39661 -1 2965 13 1169 3143 108747 29150 4.26194 4.26194 -630.352 -4.26194 0 0 258247. 4035.11 0.06 0.15 0.06 -1 -1 0.06 0.107329 0.0995631 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml bigkey.blif common 6.23 vpr 64.53 MiB -1 -1 -1 -1 3 0.37 -1 -1 34788 -1 -1 53 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66076 229 197 1023 1220 1 510 479 16 16 256 io auto 23.9 MiB 0.27 3641 154065 46430 98015 9620 64.5 MiB 0.74 0.01 2.42373 -577.247 -2.42373 2.42373 0.26 0.00398091 0.00373104 0.340965 0.319373 -1 -1 -1 -1 36 6328 35 1.05632e+07 2.85638e+06 638738. 2495.07 2.89 1.48274 1.36625 24820 128426 -1 5481 8 1306 2376 126862 31374 2.67597 2.67597 -632.008 -2.67597 0 0 786978. 3074.13 0.03 0.13 0.10 -1 -1 0.03 0.0974416 0.0913862 + k6_frac_N10_40nm.xml clma.blif common 7.46 vpr 61.55 MiB -1 -1 -1 -1 7 2.24 -1 -1 39940 -1 -1 79 36 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63032 36 82 542 624 1 389 197 11 11 121 clb auto 22.1 MiB 0.53 2089 43172 15722 20877 6573 61.6 MiB 0.30 0.01 4.60077 -165.07 -4.60077 4.60077 0.11 0.00158818 0.0014666 0.129463 0.1196 -1 -1 -1 -1 44 4139 30 4.36541e+06 4.25763e+06 327165. 2703.84 2.77 0.732744 0.643123 11931 67129 -1 3316 16 1708 5716 138864 32420 4.83136 4.83136 -175.151 -4.83136 0 0 426099. 3521.48 0.01 0.11 0.05 -1 -1 0.01 0.0672002 0.0607985 + k6_frac_N10_40nm.xml diffeq.blif common 4.01 vpr 63.38 MiB -1 -1 -1 -1 8 0.41 -1 -1 34292 -1 -1 52 64 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64900 64 39 941 980 1 449 155 10 10 100 clb auto 23.4 MiB 0.70 2832 12635 2438 9282 915 63.4 MiB 0.18 0.01 4.98272 -882.824 -4.98272 4.98272 0.09 0.00234454 0.00211606 0.0863666 0.0788215 -1 -1 -1 -1 46 4591 19 3.44922e+06 2.80249e+06 276332. 2763.32 1.20 0.589632 0.513259 9816 55112 -1 4111 18 1656 5042 136520 29654 5.41789 5.41789 -952.235 -5.41789 0 0 354105. 3541.05 0.01 0.15 0.04 -1 -1 0.01 0.107362 0.0964647 + k6_frac_N10_40nm.xml dsip.blif common 7.36 vpr 64.88 MiB -1 -1 -1 -1 3 0.33 -1 -1 34684 -1 -1 68 229 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 66440 229 197 1135 1332 1 648 494 16 16 256 io auto 25.2 MiB 0.71 5390 162510 50223 103313 8974 64.9 MiB 0.94 0.01 2.31397 -600.978 -2.31397 2.31397 0.26 0.00420661 0.00390485 0.388428 0.36156 -1 -1 -1 -1 34 9972 32 1.05632e+07 3.66479e+06 613832. 2397.78 3.22 1.46481 1.34083 24564 122629 -1 8332 13 2339 5868 306706 68264 2.51113 2.51113 -669.569 -2.51113 0 0 751777. 2936.63 0.03 0.22 0.10 -1 -1 0.03 0.14848 0.138451 + k6_frac_N10_40nm.xml elliptic.blif common 11.38 vpr 72.87 MiB -1 -1 -1 -1 10 1.33 -1 -1 37312 -1 -1 134 131 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74616 131 114 2471 2585 1 965 379 14 14 196 clb auto 31.9 MiB 3.01 9493 78526 21300 53244 3982 72.9 MiB 0.89 0.02 6.66989 -3362.18 -6.66989 6.66989 0.19 0.00572216 0.00514529 0.368526 0.328102 -1 -1 -1 -1 64 15463 36 7.76074e+06 7.2218e+06 810706. 4136.26 3.17 1.56022 1.36164 22444 164128 -1 13666 16 4234 17970 605416 107406 6.78748 6.78748 -3469.91 -6.78748 0 0 1.00880e+06 5146.95 0.03 0.41 0.13 -1 -1 0.03 0.262304 0.236626 + k6_frac_N10_40nm.xml frisc.blif common 14.61 vpr 74.16 MiB -1 -1 -1 -1 12 2.04 -1 -1 37212 -1 -1 154 20 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 75944 20 116 2477 2593 1 1095 290 15 15 225 clb auto 33.3 MiB 3.71 12890 61666 15631 41457 4578 74.2 MiB 0.99 0.02 8.02167 -3816.55 -8.02167 8.02167 0.22 0.00590075 0.00528608 0.419513 0.373344 -1 -1 -1 -1 74 21484 43 9.10809e+06 8.29968e+06 1.06098e+06 4715.46 4.44 1.71833 1.49724 27275 217117 -1 19434 16 5788 25215 1069833 185373 8.27179 8.27179 -4029.23 -8.27179 0 0 1.32822e+06 5903.22 0.04 0.53 0.17 -1 -1 0.04 0.276787 0.249571 + k6_frac_N10_40nm.xml s298.blif common 5.13 vpr 62.66 MiB -1 -1 -1 -1 8 0.60 -1 -1 33840 -1 -1 61 4 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64168 4 6 671 677 1 350 71 10 10 100 clb auto 23.3 MiB 0.92 3495 3137 432 2529 176 62.7 MiB 0.11 0.00 5.3014 -43.7499 -5.3014 5.3014 0.09 0.00193317 0.0017562 0.0558011 0.0513432 -1 -1 -1 -1 54 5597 27 3.44922e+06 3.28753e+06 316276. 3162.76 1.97 0.645928 0.55799 10312 63908 -1 5157 17 2266 11525 327366 61505 5.48392 5.48392 -46.8399 -5.48392 0 0 411339. 4113.39 0.01 0.18 0.05 -1 -1 0.01 0.0964402 0.0870985 + k6_frac_N10_40nm.xml s38417.blif common 14.45 vpr 78.21 MiB -1 -1 -1 -1 6 3.08 -1 -1 42448 -1 -1 176 29 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80088 29 106 3450 3556 1 1190 311 16 16 256 clb auto 36.9 MiB 2.12 8949 65597 16026 43107 6464 78.2 MiB 1.04 0.02 4.50231 -2905.37 -4.50231 4.50231 0.26 0.0069377 0.00610226 0.499027 0.435137 -1 -1 -1 -1 46 15732 39 1.05632e+07 9.48534e+06 786978. 3074.13 4.30 2.34785 2.00419 26604 162157 -1 13635 14 5142 17426 519616 106370 4.53102 4.53102 -2987.6 -4.53102 0 0 1.01084e+06 3948.58 0.03 0.49 0.12 -1 -1 0.03 0.357573 0.323077 + k6_frac_N10_40nm.xml s38584.1.blif common 15.91 vpr 78.62 MiB -1 -1 -1 -1 6 2.20 -1 -1 41012 -1 -1 203 38 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80504 38 304 3259 3563 1 1559 545 17 17 289 clb auto 37.4 MiB 3.13 10446 174095 49766 105233 19096 78.6 MiB 1.73 0.02 4.29015 -2399.8 -4.29015 4.29015 0.30 0.0081369 0.00733169 0.717489 0.631478 -1 -1 -1 -1 58 17767 23 1.21262e+07 1.09405e+07 1.11519e+06 3858.79 4.85 2.80811 2.44124 32499 230706 -1 16008 15 5250 14700 516522 110817 4.81093 4.81093 -2541.32 -4.81093 0 0 1.41877e+06 4909.24 0.05 0.47 0.18 -1 -1 0.05 0.353691 0.320217 + k6_frac_N10_40nm.xml tseng.blif common 3.79 vpr 61.52 MiB -1 -1 -1 -1 7 0.51 -1 -1 34300 -1 -1 33 52 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63000 52 122 664 786 1 358 207 8 8 64 io clb auto 22.0 MiB 0.69 1908 22239 4478 16280 1481 61.5 MiB 0.19 0.01 4.25559 -597.466 -4.25559 4.25559 0.05 0.0019736 0.00181929 0.081938 0.075812 -1 -1 -1 -1 58 3323 26 1.94018e+06 1.7785e+06 203254. 3175.84 1.01 0.511783 0.451955 6532 39661 -1 2850 14 1079 2916 89573 24965 4.64398 4.64398 -644.298 -4.64398 0 0 258247. 4035.11 0.01 0.11 0.03 -1 -1 0.01 0.0729861 0.0664889 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt index 38a7505faba..b77b4bd5ed6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 68.70 vpr 141.21 MiB 0.93 39844 -1 -1 8 4.37 -1 -1 41924 -1 -1 258 385 2 1 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 144600 385 394 4673 4537 1 2422 1040 27 27 729 io auto 62.8 MiB 9.25 31099 601478 234916 341577 24985 100.0 MiB 5.37 0.06 7.91028 -9390.87 -7.91028 7.91028 2.16 0.0160116 0.0148357 1.92959 1.75908 98 45582 18 3.93038e+07 1.53967e+07 4.48119e+06 6147.03 34.34 8.78739 8.0602 101765 947141 -1 43516 17 9970 36172 3767326 768291 8.49882 8.49882 -10225.8 -8.49882 0 0 5.68448e+06 7797.64 1.45 1.61 0.90 -1 -1 1.45 0.711623 0.664406 -k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 248.04 abc 92.62 MiB 2.07 38132 -1 -1 3 222.88 -1 -1 94848 -1 -1 156 38 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85708 38 36 2995 2744 1 1210 230 17 17 289 clb auto 46.9 MiB 2.35 11187 48102 12239 32898 2965 83.7 MiB 1.02 0.02 8.50665 -2425.54 -8.50665 8.50665 0.68 0.00648791 0.00577114 0.492669 0.42844 86 15535 20 1.34605e+07 8.40746e+06 1.47169e+06 5092.36 8.86 2.72296 2.3536 36379 299185 -1 14997 15 3639 10555 369332 60267 10.0216 10.0216 -2922.92 -10.0216 0 0 1.86203e+06 6443.01 0.42 0.41 0.32 -1 -1 0.42 0.297614 0.2695 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 8.70 vpr 70.45 MiB 0.75 45128 -1 -1 3 0.52 -1 -1 37948 -1 -1 92 142 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72136 142 193 1069 1140 1 565 427 14 14 196 clb auto 32.4 MiB 0.82 1818 153092 57142 75216 20734 70.4 MiB 0.62 0.01 2.94229 -453.47 -2.94229 2.94229 0.43 0.00270225 0.00251819 0.270422 0.252062 36 4119 16 9.20055e+06 4.95825e+06 447080. 2281.02 1.25 0.678648 0.626119 18336 87587 -1 3545 13 1258 1911 94099 25244 3.69367 3.69367 -542.415 -3.69367 0 0 553089. 2821.88 0.13 0.13 0.06 -1 -1 0.13 0.0968577 0.090647 -k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 24.99 vpr 84.66 MiB 0.47 31528 -1 -1 3 1.06 -1 -1 40312 -1 -1 112 214 0 8 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86692 214 305 2963 2869 1 1445 639 19 19 361 io auto 46.9 MiB 2.82 10827 256482 85370 157603 13509 84.7 MiB 1.63 0.02 4.36739 -2477.41 -4.36739 4.36739 0.89 0.00721181 0.00661461 0.712875 0.654201 56 24300 32 1.72706e+07 9.20413e+06 1.27879e+06 3542.35 11.31 2.9929 2.72715 39043 256479 -1 19887 20 6510 14395 4285781 1013890 4.87643 4.87643 -2933.55 -4.87643 0 0 1.63234e+06 4521.70 0.37 1.20 0.23 -1 -1 0.37 0.376058 0.348776 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 35.73 vpr 117.99 MiB 0.88 39796 -1 -1 8 4.27 -1 -1 42064 -1 -1 258 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 120820 385 394 4673 4537 1 2402 1040 27 27 729 io auto 55.2 MiB 8.87 31226 590944 229570 335529 25845 99.0 MiB 4.01 0.05 8.49305 -10507.1 -8.49305 8.49305 0.67 0.00985407 0.00919392 1.21454 1.10916 -1 -1 -1 -1 92 45492 18 3.93038e+07 1.53967e+07 4.24291e+06 5820.18 8.25 3.43478 3.14555 98853 888777 -1 43336 19 10072 35436 1903495 335341 8.64458 8.64458 -10958.4 -8.64458 0 0 5.38988e+06 7393.52 0.21 1.31 0.80 -1 -1 0.21 0.81131 0.758475 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 252.53 abc 92.89 MiB 2.10 38212 -1 -1 3 229.65 -1 -1 95116 -1 -1 155 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85380 38 36 2995 2744 1 1203 229 17 17 289 clb auto 42.6 MiB 2.62 11670 42229 10578 28453 3198 83.4 MiB 1.00 0.02 9.56668 -2644.49 -9.56668 9.56668 0.30 0.00653116 0.00584439 0.427666 0.375753 -1 -1 -1 -1 68 16961 39 1.34605e+07 8.35357e+06 1.21205e+06 4193.96 7.00 2.98402 2.54931 32923 238265 -1 15449 21 4262 11796 386501 67599 10.0346 10.0346 -2927.77 -10.0346 0 0 1.50552e+06 5209.41 0.05 0.47 0.21 -1 -1 0.05 0.348571 0.310711 + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 9.27 vpr 70.62 MiB 0.76 45212 -1 -1 3 0.57 -1 -1 37660 -1 -1 97 142 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 72316 142 193 1069 1140 1 544 432 14 14 196 clb auto 31.5 MiB 1.33 1935 140784 46814 73686 20284 70.6 MiB 0.61 0.01 3.36481 -502.007 -3.36481 3.36481 0.20 0.00294747 0.00276699 0.269116 0.252539 -1 -1 -1 -1 42 3322 13 9.20055e+06 5.22772e+06 506340. 2583.37 1.96 1.10351 1.01282 19116 100245 -1 3124 11 1007 1567 69332 19451 3.55486 3.55486 -535.708 -3.55486 0 0 635007. 3239.83 0.02 0.12 0.09 -1 -1 0.02 0.0909108 0.0848666 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 20.73 vpr 84.22 MiB 0.49 31708 -1 -1 3 1.08 -1 -1 40516 -1 -1 123 214 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 86244 214 305 2963 2869 1 1444 650 19 19 361 io auto 43.2 MiB 3.52 11237 214514 71103 131344 12067 84.2 MiB 1.56 0.03 4.53 -2651.41 -4.53 4.53 0.39 0.00798613 0.00737775 0.647388 0.59775 -1 -1 -1 -1 58 21099 31 1.72706e+07 9.79696e+06 1.32779e+06 3678.09 7.97 3.16487 2.88635 39763 268823 -1 18983 16 5722 13316 1766310 456164 4.74311 4.74311 -2886.77 -4.74311 0 0 1.69263e+06 4688.74 0.06 0.74 0.27 -1 -1 0.06 0.376597 0.351474 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt index 472b47cb7f6..806aa8c8a19 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 628.23 vpr 523.07 MiB 4.94 207220 -1 -1 101 125.94 -1 -1 108124 -1 -1 2196 114 44 8 success b37c31d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-04-04T16:52:55 gh-actions-runner-vtr-auto-spawned70 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 535628 114 102 38224 33865 1 18116 2464 57 57 3249 clb auto 366.7 MiB 79.89 235628 1915489 723145 1160834 31510 434.9 MiB 90.41 0.75 68.8354 -54271.6 -68.8354 68.8354 1.27 0.122715 0.109144 14.833 12.338 -1 337567 24 1.92089e+08 1.45633e+08 2.12617e+07 6544.09 29.31 22.8823 19.2537 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 461.97 vpr 520.77 MiB 5.52 207104 -1 -1 101 82.80 -1 -1 104772 -1 -1 2232 114 44 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 533268 114 102 38224 33865 1 17936 2500 57 57 3249 clb auto 296.6 MiB 87.81 234808 1969860 734649 1200070 35141 428.8 MiB 60.45 0.51 75.4166 -53786.3 -75.4166 75.4166 0.01 0.108744 0.090072 13.6268 11.3009 -1 -1 -1 -1 -1 329498 24 1.92089e+08 1.47573e+08 2.12617e+07 6544.09 11.64 20.3553 17.0367 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff_titan/config/golden_results.txt index f2b439ff03e..18b3e54aa6f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time - stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1315.84 77 3123 89 136 0 0 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 2858228 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 86.66 609879 114.00 0.78 7.31659 -73007.4 -6.31659 6.39652 193.04 0.230423 0.177265 33.2852 25.4119 777696 -1 -1 -1 -1 0 0 2.28642e+08 18462.7 20 7.77193 6.96909 -118197 -6.77193 0 0 50.21 46.7196 37.2174 149.58 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 875.57 vpr 2.85 GiB 77 3136 89 136 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2992920 42 35 119888 86875 1 50816 3438 129 96 12384 DSP auto 1747.3 MiB 113.44 582667 3141815 1177622 1941316 22877 2922.8 MiB 131.76 0.97 8.30634 -81008.6 -7.30634 5.71368 0.07 0.390966 0.330249 50.2947 42.4929 753664 14.8455 159283 3.13753 108681 189329 132420316 35517631 0 0 2.28639e+08 18462.4 18 3593250 39165143 -1 8.74065 6.13717 -112227 -7.74065 0 0 78.47 -1 -1 2922.8 MiB 45.38 68.7408 59.0089 2922.8 MiB -1 22.64 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt index 05102b14630..4719bdbbc41 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt @@ -1,15 +1,15 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 94.08 yosys 239.28 MiB -1 -1 49.30 245024 18 13.22 -1 -1 51004 -1 -1 689 257 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 115188 257 32 6041 6073 1 5235 978 30 30 900 clb auto 57.2 MiB 1.23 29985 112.5 MiB 5.78 0.07 6.0875 -2546.45 -6.0875 6.0875 0.21 0.0116004 0.00952958 0.966535 0.81325 47934 24472 85349 11868342 2593378 4.97244e+06 2.6871e+06 9.69309e+06 10770.1 19 6.86469 6.86469 -2916.73 -6.86469 0 0 112.5 MiB 3.47 1.59485 1.36176 112.5 MiB 14.13 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 111.52 yosys 302.91 MiB -1 -1 17.69 310184 11 18.95 -1 -1 60792 -1 -1 1309 36 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 199576 36 100 10272 10372 1 9717 1445 41 41 1681 clb auto 91.3 MiB 1.71 84755 194.9 MiB 22.24 0.23 4.16019 -1591.46 -4.16019 4.16019 0.51 0.0327612 0.0271477 3.22883 2.67515 138099 47433 159547 25268625 4863134 8.95136e+06 5.1051e+06 1.84779e+07 10992.2 18 4.66194 4.66194 -1818.85 -4.66194 0 0 194.9 MiB 8.70 4.88548 4.09248 194.9 MiB 30.37 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 19.98 vpr 63.44 MiB -1 -1 14.95 35240 7 0.23 -1 -1 37236 -1 -1 84 195 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64960 195 193 1172 1365 1 837 473 15 15 225 io memory auto 25.4 MiB 0.13 3551 63.4 MiB 0.68 0.01 2.02671 -779.537 -2.02671 2.02671 0.04 0.0019832 0.00177416 0.190053 0.170064 5389 2076 6396 795212 201029 1.16234e+06 410348 2.18283e+06 9701.45 12 2.21102 2.21102 -902.31 -2.21102 -5.18176 -0.375057 63.4 MiB 0.27 0.270471 0.244687 63.4 MiB 2.21 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU8PEEng.v common 494.37 vpr 715.82 MiB -1 -1 73.42 337876 197 97.67 -1 -1 83744 -1 -1 2994 114 84 8 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 733004 114 102 27412 27322 1 24802 3302 86 86 7396 memory auto 208.9 MiB 7.36 251641 715.8 MiB 75.10 0.65 63.9648 -36231.9 -63.9648 63.9648 2.70 0.0670445 0.0543409 7.08657 5.72048 339513 88760 297702 125893415 50379905 4.18276e+07 1.95778e+07 8.44414e+07 11417.2 23 71.4148 71.4148 -60631.2 -71.4148 -145.469 -0.36083 715.8 MiB 58.92 10.8826 8.92707 715.8 MiB 142.88 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkDelayWorker32B.v common 194.12 vpr 556.41 MiB -1 -1 14.86 128884 6 5.85 -1 -1 60228 -1 -1 530 506 80 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 569760 506 553 3101 3654 1 3095 1669 82 82 6724 memory auto 47.2 MiB 1.67 22423 556.4 MiB 4.95 0.05 6.05217 -1454.35 -6.05217 6.05217 2.62 0.0154982 0.013967 2.20022 1.96905 25147 4320 5400 6396252 2098319 3.85878e+07 8.68684e+06 7.66484e+07 11399.2 14 6.28816 6.28816 -1748.1 -6.28816 -21.3514 -0.36083 556.4 MiB 2.98 2.83156 2.55993 556.4 MiB 138.42 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkSMAdapter4B.v common 42.90 vpr 132.11 MiB -1 -1 7.13 57948 12 3.00 -1 -1 40372 -1 -1 268 193 10 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 135280 193 205 2654 2859 1 2029 676 37 37 1369 memory auto 36.3 MiB 0.49 16037 132.1 MiB 2.25 0.03 3.73419 -2252.01 -3.73419 3.73419 0.34 0.00539662 0.00465347 0.562454 0.485859 23850 7572 24450 6218122 1974634 7.45627e+06 1.87268e+06 1.49196e+07 10898.2 15 4.1 4.1 -2552.52 -4.1 -16.2594 -0.362934 132.1 MiB 2.33 0.801166 0.701352 132.1 MiB 21.99 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml or1200.v common 39.95 vpr 96.50 MiB -1 -1 6.09 70384 45 5.24 -1 -1 41644 -1 -1 506 385 4 1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 98816 385 394 5015 5346 1 4350 1290 27 27 729 io clb auto 53.1 MiB 0.87 41926 96.2 MiB 8.07 0.08 12.8573 -9363.03 -12.8573 12.8573 0.17 0.0144261 0.0132607 1.60279 1.42637 60904 14787 54657 9040768 2197120 4.06709e+06 2.42319e+06 7.75339e+06 10635.7 17 14.1675 14.1675 -10940.6 -14.1675 0 0 96.2 MiB 3.48 2.34681 2.10329 96.2 MiB 11.60 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 24.52 vpr 81.19 MiB -1 -1 4.98 48784 13 1.22 -1 -1 41592 -1 -1 256 235 1 6 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 83140 235 305 3025 3186 1 2385 803 26 26 676 mult_36 auto 37.2 MiB 0.54 17792 81.2 MiB 2.23 0.03 4.07341 -1915.66 -4.07341 4.07341 0.14 0.00596069 0.00545514 0.514273 0.454401 26395 7994 25461 5630378 1530085 3.88769e+06 1.79395e+06 7.17610e+06 10615.5 16 4.6849 4.6849 -2313.21 -4.6849 -34.8532 -0.36083 81.2 MiB 1.82 0.812614 0.726893 81.2 MiB 10.22 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 19.66 vpr 79.00 MiB -1 -1 3.03 50220 31 2.57 -1 -1 43480 -1 -1 339 38 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 80900 38 36 3594 3630 1 2712 413 22 22 484 clb auto 41.5 MiB 0.56 19133 79.0 MiB 1.85 0.03 9.67412 -2335.65 -9.67412 9.67412 0.09 0.00827985 0.00698716 0.450426 0.38139 31734 11686 45588 5830197 1332550 2.41174e+06 1.3221e+06 5.02684e+06 10386.0 19 11.0674 11.0674 -2864.8 -11.0674 0 0 79.0 MiB 2.11 0.88857 0.765334 79.0 MiB 6.48 - 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gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 407536 113 145 23206 21071 1 16047 2016 62 62 3844 mult_36 auto 141.4 MiB 3.29 143820 398.0 MiB 37.12 0.30 4.32437 -16925.8 -4.32437 4.32437 1.40 0.0406386 0.0362444 4.69579 4.02718 184101 52325 148236 47967259 12664479 2.17057e+07 1.19118e+07 4.33614e+07 11280.3 11 4.51376 4.51376 -20726.1 -4.51376 0 0 398.0 MiB 15.31 6.30117 5.46654 398.0 MiB 75.08 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision2.v common 872.12 vpr 1.36 GiB -1 -1 42.72 330780 25 179.00 -1 -1 138520 -1 -1 4676 149 0 179 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1427112 149 182 52817 45103 1 44034 5186 122 122 14884 mult_36 auto 326.8 MiB 10.95 610462 1393.7 MiB 226.09 1.76 13.0565 -37981.2 -13.0565 13.0565 6.72 0.159797 0.135184 18.8147 15.9648 736559 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-58.8084 -0.0952056 -0.03838 104.27 -1 -1 3052.1 MiB 56.17 58.8307 49.565 3052.1 MiB -1 54.29 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt index ff1ef00e2e0..35a4467c277 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_mem32K_40nm.xml arm_core.v common 280.20 vpr 257.79 MiB -1 -1 25.75 122844 25 38.75 -1 -1 67596 -1 -1 880 133 24 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 263980 133 179 13858 14037 1 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2.50602e+07 1.49286e+07 1.81652e+06 3753.13 13.19 4.54237 3.95427 52870 368945 -1 28855 15 10906 34558 982071 189322 9.64046 9.64046 -3932.02 -9.64046 0 0 2.31597e+06 4785.06 0.53 0.76 0.31 -1 -1 0.53 0.488917 0.443615 2580 2833 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml blob_merge.v common 89.76 parmys 291.04 MiB -1 -1 15.38 298020 7 11.99 -1 -1 57968 -1 -1 566 36 0 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 163404 36 100 6840 6940 1 3200 702 30 30 900 clb auto 85.5 MiB 4.42 44186 278204 76945 183206 18053 122.5 MiB 4.81 0.05 5.85686 -2192.32 -5.85686 5.85686 2.38 0.0180181 0.0160503 1.85784 1.60892 68 71187 28 4.8774e+07 3.0504e+07 4.08678e+06 4540.87 35.59 8.94537 7.61686 104936 820930 -1 63255 15 15176 68305 3028418 384879 6.04948 6.04948 -2275.21 -6.04948 0 0 5.07014e+06 5633.48 1.15 1.64 0.67 -1 -1 1.15 0.867118 0.785571 4872 6243 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml boundtop.v common 19.71 vpr 67.77 MiB -1 -1 12.00 31536 4 0.23 -1 -1 34556 -1 -1 42 195 1 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69400 195 193 1088 1281 1 593 431 15 15 225 io auto 29.8 MiB 0.40 2789 140353 37684 89836 12833 67.8 MiB 0.68 0.01 2.5026 -1068.95 -2.5026 2.5026 0.45 0.0035004 0.00326724 0.318219 0.29679 42 5940 17 1.03862e+07 2.81155e+06 589524. 2620.11 3.76 1.43455 1.31489 21486 116796 -1 5209 12 1582 2286 164748 45289 2.70224 2.70224 -1159.85 -2.70224 -0.575265 -0.201936 739091. 3284.85 0.16 0.16 0.11 -1 -1 0.16 0.112943 0.105183 347 531 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.90 vpr 64.06 MiB -1 -1 0.34 18776 3 0.09 -1 -1 33160 -1 -1 68 99 1 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65600 99 130 343 473 1 225 298 12 12 144 clb auto 25.6 MiB 0.15 593 66963 19571 35031 12361 64.1 MiB 0.23 0.00 1.865 -117.456 -1.865 1.865 0.27 0.00127756 0.00120824 0.0904413 0.0855813 42 1503 16 5.66058e+06 4.21279e+06 345702. 2400.71 1.53 0.430255 0.394458 12810 66778 -1 1212 8 350 556 27894 7863 2.02345 2.02345 -142.963 -2.02345 -0.458472 -0.106489 434679. 3018.61 0.09 0.04 0.07 -1 -1 0.09 0.0281257 0.026127 144 154 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.92 vpr 67.45 MiB -1 -1 0.54 23452 15 0.32 -1 -1 34120 -1 -1 36 162 0 5 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69068 162 96 994 935 1 694 299 16 16 256 mult_36 auto 29.4 MiB 0.28 5022 91208 31929 52152 7127 67.4 MiB 0.66 0.01 21.1771 -1637.49 -21.1771 21.1771 0.51 0.0034124 0.00320223 0.331093 0.310751 56 12767 47 1.21132e+07 3.92018e+06 870502. 3400.40 6.96 1.28868 1.18762 26504 172068 -1 9174 19 3073 5862 965990 269588 22.2519 22.2519 -1734.32 -22.2519 0 0 1.11200e+06 4343.75 0.24 0.38 0.17 -1 -1 0.24 0.15888 0.147497 337 479 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml diffeq2.v common 12.80 vpr 65.55 MiB -1 -1 0.20 22176 16 0.24 -1 -1 33572 -1 -1 27 66 0 5 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67124 66 96 610 551 1 452 194 16 16 256 mult_36 auto 27.3 MiB 0.30 3491 41708 11675 25394 4639 65.6 MiB 0.36 0.01 16.8255 -937.879 -16.8255 16.8255 0.51 0.00238587 0.00225299 0.189255 0.178809 50 9637 45 1.21132e+07 3.43514e+06 780512. 3048.87 8.84 1.16511 1.07001 25484 153448 -1 7566 22 3118 6840 1168639 359265 17.7302 17.7302 -1031.17 -17.7302 0 0 1.00276e+06 3917.05 0.21 0.38 0.14 -1 -1 0.21 0.120297 0.111441 235 288 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkDelayWorker32B.v common 81.17 vpr 332.60 MiB -1 -1 13.40 124716 5 3.43 -1 -1 56692 -1 -1 460 506 47 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 340580 506 553 3055 3608 1 2790 1566 50 50 2500 memory auto 52.9 MiB 4.44 15016 1146906 560934 403027 182945 332.6 MiB 5.64 0.06 7.02534 -1950.88 -7.02534 7.02534 18.86 0.0232393 0.0210229 3.05303 2.74244 38 22534 14 1.47946e+08 5.05479e+07 6.86584e+06 2746.33 17.59 8.34828 7.5787 251304 1421084 -1 21732 15 3907 5076 1040584 239224 7.06661 7.06661 -2232.41 -7.06661 -3.54638 -0.295467 8.69095e+06 3476.38 2.71 1.06 1.22 -1 -1 2.71 0.855401 0.790478 953 1207 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkPktMerge.v common 20.83 vpr 75.12 MiB -1 -1 1.22 25852 2 0.36 -1 -1 33772 -1 -1 27 311 15 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 76920 311 156 972 1128 1 953 509 28 28 784 memory auto 30.4 MiB 0.49 9059 189392 67096 112947 9349 71.6 MiB 1.08 0.02 4.05723 -4390.2 -4.05723 4.05723 1.83 0.00563434 0.00500276 0.552809 0.49016 48 14303 15 4.25198e+07 9.67514e+06 2.50616e+06 3196.63 10.09 2.37376 2.1062 80602 506684 -1 13827 14 2506 2832 619608 160214 4.25681 4.25681 -4915.31 -4.25681 -18.6727 -0.360359 3.20999e+06 4094.38 0.77 0.33 0.43 -1 -1 0.77 0.195921 0.177483 109 186 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml mkSMAdapter4B.v common 26.49 vpr 76.90 MiB -1 -1 6.16 54304 7 2.23 -1 -1 39368 -1 -1 153 193 5 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 78748 193 205 2152 2357 1 1161 556 20 20 400 memory auto 39.4 MiB 1.52 8858 231341 79266 127842 24233 76.9 MiB 1.59 0.02 4.96605 -2953.62 -4.96605 4.96605 0.81 0.00676456 0.00610519 0.727478 0.653919 50 16222 33 2.07112e+07 1.09858e+07 1.26944e+06 3173.59 9.27 2.9981 2.67772 40848 252947 -1 14533 15 4363 10859 617682 132576 4.91884 4.91884 -3085.46 -4.91884 -7.99782 -0.340786 1.63222e+06 4080.54 0.37 0.42 0.23 -1 -1 0.37 0.267345 0.244193 947 1174 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml or1200.v common 57.25 vpr 106.50 MiB -1 -1 5.56 66516 27 4.10 -1 -1 41788 -1 -1 251 385 2 1 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 109052 385 394 3884 4215 1 2355 1033 27 27 729 io auto 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3.25894 39599 281069 -1 19716 13 5626 15462 1415752 327524 5.02806 5.02806 -2816.27 -5.02806 -1.25369 -0.0304031 1.76637e+06 4892.99 0.44 0.61 0.25 -1 -1 0.44 0.300482 0.280819 1038 1294 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml sha.v common 16.37 vpr 79.59 MiB -1 -1 2.93 46276 21 2.14 -1 -1 41028 -1 -1 149 38 0 0 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 81500 38 36 2570 2606 1 1074 223 17 17 289 clb auto 42.3 MiB 1.33 9358 36727 8203 26236 2288 79.6 MiB 0.70 0.01 13.9422 -2847.26 -13.9422 13.9422 0.59 0.0057032 0.00504453 0.365255 0.3232 46 17017 35 1.34605e+07 8.03021e+06 830882. 2875.03 4.35 1.59721 1.3833 28231 166010 -1 14224 16 4373 13089 440600 78841 14.6248 14.6248 -3199.06 -14.6248 0 0 1.06831e+06 3696.59 0.23 0.41 0.15 -1 -1 0.23 0.273543 0.245358 1458 1647 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml 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Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 261808 113 145 21669 19534 1 9921 1059 40 40 1600 mult_36 auto 151.3 MiB 8.85 84857 572929 187668 359255 26006 218.2 MiB 9.69 0.10 5.28341 -22594.6 -5.28341 5.28341 4.27 0.0329171 0.0273991 3.78077 3.17952 78 133452 45 9.16046e+07 5.82227e+07 8.23230e+06 5145.19 72.58 15.4019 13.0152 199776 1720042 -1 120901 15 32194 54580 8831164 1886670 5.47538 5.47538 -24275.7 -5.47538 0 0 1.04203e+07 6512.68 2.53 3.33 1.44 -1 -1 2.53 1.5499 1.3837 7327 9014 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml stereovision2.v common 635.75 vpr 996.02 MiB -1 -1 36.83 328740 16 70.21 -1 -1 133104 -1 -1 1876 149 0 179 success v8.0.0-10974-gd2d425477 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T01:29:20 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1019928 149 182 46661 38947 1 28355 2386 80 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80064 235 305 2600 2761 1 1433 664 19 19 361 io auto 37.7 MiB 2.02 12027 249634 86844 149473 13317 78.2 MiB 1.87 0.03 5.30864 -2648.81 -5.30864 5.30864 0.39 0.00799633 0.00740581 0.747518 0.688936 -1 -1 -1 -1 56 22630 21 1.72706e+07 9.2296e+06 1.27879e+06 3542.35 8.20 2.88004 2.62374 38159 255829 -1 20346 20 5608 15965 1386935 355889 5.35066 5.35066 -2866.8 -5.35066 -8.65745 -0.196482 1.63234e+06 4521.70 0.05 0.66 0.22 -1 -1 0.05 0.385253 0.355995 1041 1300 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml sha.v common 17.48 vpr 78.97 MiB -1 -1 4.21 48012 21 2.24 -1 -1 40584 -1 -1 150 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 80868 38 36 2570 2606 1 1074 224 17 17 289 clb auto 38.2 MiB 1.44 9206 36264 8126 25763 2375 79.0 MiB 0.76 0.01 13.8191 -2630.52 -13.8191 13.8191 0.30 0.00635308 0.00568636 0.379903 0.337131 -1 -1 -1 -1 48 15632 40 1.34605e+07 8.0841e+06 864508. 2991.38 5.47 2.34496 2.023 28519 171069 -1 13363 20 4013 11904 355523 67720 14.9903 14.9903 -2979.62 -14.9903 0 0 1.10659e+06 3829.03 0.03 0.31 0.11 -1 -1 0.03 0.228029 0.208867 1457 1647 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision0.v common 114.12 vpr 221.60 MiB -1 -1 11.00 122760 5 42.78 -1 -1 65056 -1 -1 749 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 226920 169 197 21117 21314 1 6554 1115 34 34 1156 clb auto 126.4 MiB 9.77 46234 579015 188806 368341 21868 178.3 MiB 8.09 0.09 3.53206 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-1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision3.v common 2.83 vpr 63.49 MiB -1 -1 0.96 22952 5 0.13 -1 -1 33376 -1 -1 7 10 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 65016 10 2 181 183 1 37 19 6 6 36 clb auto 24.0 MiB 0.06 125 94 37 54 3 63.5 MiB 0.01 0.00 2.09443 -87.946 -2.09443 2.09443 0.02 0.000491328 0.000453678 0.00392453 0.0037192 -1 -1 -1 -1 26 127 8 646728 377258 45676.2 1268.78 0.25 0.10472 0.0875195 2356 7902 -1 119 8 72 98 1263 541 1.98035 1.98035 -90.0206 -1.98035 0 0 56047.2 1556.87 0.00 0.02 0.01 -1 -1 0.00 0.0122617 0.0109864 52 90 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml LU8PEEng.v common 335.48 vpr 446.37 MiB -1 -1 85.53 350812 123 57.25 -1 -1 78588 -1 -1 1354 114 45 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 457080 114 102 21994 21904 1 11067 1623 50 50 2500 memory auto 169.9 MiB 25.36 151955 1021761 356538 644113 21110 446.4 MiB 24.23 0.20 79.7251 -52220.5 -79.7251 79.7251 9.68 0.0602828 0.0526636 7.23374 6.03628 -1 -1 -1 -1 88 230345 35 1.47946e+08 1.00803e+08 1.46563e+07 5862.50 97.97 27.3303 22.5517 331272 3068748 -1 205366 19 40592 161935 9797150 1881837 81.0471 81.0471 -67091 -81.0471 -7.13348 -0.293253 1.83775e+07 7351.00 0.80 5.76 2.82 -1 -1 0.80 3.27315 2.80685 12609 14234 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml LU32PEEng.v common 2442.52 vpr 1.73 GiB -1 -1 258.68 1026588 124 552.80 -1 -1 233444 -1 -1 4481 114 168 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1813676 114 102 72759 72093 1 37610 4897 92 92 8464 memory auto 510.6 MiB 96.92 754623 5076071 2040814 3006065 29192 1442.0 MiB 220.81 1.57 80.7548 -305716 -80.7548 80.7548 37.06 0.237208 0.205198 30.9063 25.5114 -1 -1 -1 -1 122 1020904 46 5.19428e+08 3.46213e+08 6.75417e+07 7979.88 1138.60 133.192 108.89 1314002 14600600 -1 937208 19 140677 611398 44735088 7699678 80.7275 80.7275 -415911 -80.7275 -29.9669 -0.17368 8.47015e+07 10007.3 4.65 24.60 14.85 -1 -1 4.65 12.2915 10.5138 42648 47397 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml mcml.v common 4904.44 vpr 1.68 GiB -1 -1 681.62 1428456 64 3460.75 -1 -1 347276 -1 -1 4906 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1762484 36 356 125423 124208 1 32010 5484 92 92 8464 memory auto 675.0 MiB 73.34 379984 6144664 2439048 3655799 49817 1599.2 MiB 177.06 1.20 63.3831 -263362 -63.3831 63.3831 40.06 0.258391 0.224397 35.9954 30.3596 -1 -1 -1 -1 80 535404 46 5.19428e+08 3.62204e+08 4.63837e+07 5480.11 333.49 155.427 127.989 1085502 9765414 -1 503795 17 105029 333178 19086430 3883087 64.399 64.399 -305691 -64.399 -0.590352 -0.0337239 5.84708e+07 6908.18 2.83 17.10 9.03 -1 -1 2.83 12.3477 10.6541 47698 74153 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt index e665c066fed..5fc9ae47bce 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 255.87 vpr 266.12 MiB -1 -1 33.21 121108 20 51.66 -1 -1 67420 -1 -1 852 133 25 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 272504 133 179 14228 14085 1 7083 1189 37 37 1369 clb auto 124.1 MiB 55.24 118769 611901 198399 390860 22642 182.9 MiB 12.74 0.12 23.082 -209424 -23.082 23.082 4.18 0.0401013 0.0351966 4.51768 3.8456 110 180467 24 7.54166e+07 5.96187e+07 9.46577e+06 6914.37 70.64 15.6471 13.0594 201652 2027183 -1 164262 14 29902 115834 9220015 1621549 24.3564 24.3564 -221310 -24.3564 0 0 1.20852e+07 8827.75 3.46 5.39 1.97 -1 -1 3.46 2.40428 2.08959 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 525.83 vpr 710.25 MiB -1 -1 69.20 614744 14 71.56 -1 -1 121924 -1 -1 2715 257 0 11 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 727296 257 32 36080 33722 1 19553 3015 63 63 3969 clb auto 301.2 MiB 92.74 248033 2180215 773829 1379285 27101 710.2 MiB 60.47 0.53 19.0622 -25745.4 -19.0622 19.0622 36.12 0.105944 0.0877618 11.3985 9.52259 74 394698 40 2.36641e+08 1.5068e+08 2.02178e+07 5093.92 113.40 35.3604 29.3374 502298 4195434 -1 380376 21 97229 438645 20887764 3077897 19.7741 19.7741 -26305.4 -19.7741 0 0 2.53694e+07 6391.88 9.43 13.49 3.91 -1 -1 9.43 6.66179 5.7969 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 88.16 parmys 244.68 MiB -1 -1 15.96 250556 5 3.94 -1 -1 54952 -1 -1 487 36 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 141756 36 100 10178 7632 1 2732 623 28 28 784 clb auto 89.6 MiB 21.09 41236 216002 63618 139932 12452 136.6 MiB 4.12 0.05 15.0315 -2401.76 -15.0315 15.0315 2.01 0.0200758 0.0181589 1.82478 1.61386 70 69778 28 4.25198e+07 2.62464e+07 3.59791e+06 4589.17 25.18 6.26144 5.39126 94322 733910 -1 61041 13 12371 63921 2526758 365216 15.5884 15.5884 -2563.65 -15.5884 0 0 4.52633e+06 5773.37 1.61 2.02 0.72 -1 -1 1.61 1.14017 1.00737 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 28.72 vpr 70.14 MiB -1 -1 19.91 45044 3 0.67 -1 -1 35452 -1 -1 44 196 1 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71828 196 193 1201 1346 1 607 434 15 15 225 io auto 31.5 MiB 0.79 2924 143288 42391 88468 12429 70.1 MiB 0.70 0.01 2.18307 -1105.54 -2.18307 2.18307 0.47 0.00366212 0.00341729 0.333891 0.310594 40 5977 15 1.03862e+07 2.91934e+06 568276. 2525.67 3.57 1.23727 1.13314 21782 113316 -1 5329 11 1700 2587 187113 48920 2.5066 2.5066 -1182.04 -2.5066 0 0 712852. 3168.23 0.17 0.16 0.11 -1 -1 0.17 0.113224 0.105684 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 3.56 vpr 65.28 MiB -1 -1 0.48 18496 3 0.09 -1 -1 33264 -1 -1 68 99 1 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66844 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.28 665 70943 20214 37821 12908 65.3 MiB 0.26 0.00 1.89985 -118.566 -1.89985 1.89985 0.28 0.00130138 0.00123193 0.101489 0.0957523 34 1540 15 5.66058e+06 4.21279e+06 293035. 2034.97 0.82 0.368758 0.33821 12374 55836 -1 1457 10 403 605 42523 12642 1.99363 1.99363 -143.624 -1.99363 0 0 360780. 2505.42 0.08 0.06 0.06 -1 -1 0.08 0.0350922 0.0325653 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 9.67 vpr 68.42 MiB -1 -1 0.56 21980 5 0.19 -1 -1 33884 -1 -1 32 162 0 5 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70060 162 96 1075 892 1 666 295 16 16 256 mult_36 auto 29.5 MiB 0.27 4888 98395 35924 54623 7848 68.4 MiB 0.68 0.01 15.9849 -1245.5 -15.9849 15.9849 0.53 0.00320112 0.00300688 0.336242 0.316142 52 12010 41 1.21132e+07 3.70461e+06 805949. 3148.24 4.85 1.09429 1.01247 26552 162987 -1 9148 19 3314 5627 1080193 297034 17.378 17.378 -1353.55 -17.378 0 0 1.06067e+06 4143.25 0.24 0.43 0.16 -1 -1 0.24 0.156249 0.145747 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 15.75 vpr 67.16 MiB -1 -1 0.40 21156 5 0.12 -1 -1 33328 -1 -1 22 66 0 5 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 68768 66 96 778 595 1 467 189 16 16 256 mult_36 auto 28.4 MiB 0.56 3517 47885 16325 27094 4466 67.2 MiB 0.40 0.01 12.1762 -748.789 -12.1762 12.1762 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 626424 114 102 35834 31925 1 16897 2420 56 56 3136 clb auto 279.1 MiB 70.81 224666 1805060 668533 1109456 27071 611.7 MiB 64.72 0.55 75.1122 -53345.7 -75.1122 75.1122 13.40 0.101362 0.0900982 12.5616 10.6146 -1 -1 -1 -1 88 335261 49 1.8697e+08 1.43756e+08 1.84122e+07 5871.24 134.02 47.1194 39.1334 423474 3861999 -1 307396 22 65997 258491 13780558 2468289 76.0017 76.0017 -64554.6 -76.0017 0 0 2.30976e+07 7365.31 1.10 10.19 3.64 -1 -1 1.10 6.17356 5.28565 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 2692.08 vpr 2.42 GiB -1 -1 242.89 1496112 97 858.98 -1 -1 355104 -1 -1 7513 114 168 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2535652 114 102 120350 108159 1 57345 7929 103 103 10609 clb auto 892.1 MiB 262.75 1003045 9728742 4018902 5663791 46049 2004.2 MiB 480.49 3.14 72.4024 -329114 -72.4024 72.4024 47.02 0.346214 0.301919 48.3359 40.4685 -1 -1 -1 -1 124 1323068 31 6.46441e+08 5.09602e+08 8.61045e+07 8116.18 587.22 199.076 163.111 1699828 18865638 -1 1270470 22 208280 903882 50603811 8413337 73.1548 73.1548 -457667 -73.1548 0 0 1.09063e+08 10280.2 5.97 39.87 20.11 -1 -1 5.97 22.9615 19.528 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5532.81 vpr 2.11 GiB -1 -1 301.74 1243688 25 2880.43 -1 -1 369296 -1 -1 6763 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2217356 36 356 185159 159806 1 63309 7341 98 98 9604 clb auto 1056.9 MiB 254.50 722860 10062756 3907097 5967087 188572 2054.1 MiB 616.55 3.41 47.3986 -303024 -47.3986 47.3986 45.23 0.338735 0.29516 55.1437 45.9685 -1 -1 -1 -1 126 949879 27 5.9175e+08 4.62277e+08 7.90658e+07 8232.59 1240.96 214.222 174.297 1551988 17290692 -1 919494 20 208733 484691 28296676 5077184 47.6251 47.6251 -321060 -47.6251 0 0 9.99791e+07 10410.1 5.20 27.91 18.77 -1 -1 5.20 19.465 16.7334 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt index 87e9637f9ad..f1eeb0d6e78 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 277.11 vpr 289.11 MiB -1 -1 16.67 124648 20 39.27 -1 -1 72328 -1 -1 679 133 25 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 296044 133 179 14228 14085 1 6986 1016 36 36 1296 memory auto 149.9 MiB 23.02 111869 506411 160230 326278 19903 181.8 MiB 9.47 0.08 19.5094 -192112 -19.5094 19.5094 4.12 0.0160466 0.0136643 1.86358 1.55727 154 199903 32 7.21828e+07 5.02946e+07 1.28857e+07 9942.66 153.26 8.23573 7.08873 239994 2946416 -1 183903 16 33799 138265 51564315 11944708 22.41 22.41 -214787 -22.41 -3.1378 -0.29436 1.62481e+07 12537.1 5.26 10.90 2.38 -1 -1 5.26 1.4659 1.3784 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 434.85 vpr 712.33 MiB -1 -1 33.46 637524 14 62.12 -1 -1 123408 -1 -1 2287 257 0 11 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 729428 257 32 36080 33722 1 18672 2587 58 58 3364 clb auto 366.8 MiB 41.13 238750 1777787 613628 1135373 28786 691.6 MiB 44.36 0.36 16.9078 -22798.4 -16.9078 16.9078 38.14 0.0417663 0.0365797 5.01023 4.34011 114 489515 43 2.00088e+08 1.27615e+08 2.67492e+07 7951.60 147.45 22.3155 19.5798 548026 6020043 -1 456285 20 103684 494058 43713903 7882929 19.3528 19.3528 -25719.6 -19.3528 0 0 3.36466e+07 10002.0 12.44 11.94 4.53 -1 -1 12.44 3.97353 3.71849 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml blob_merge.v common 87.69 parmys 262.07 MiB -1 -1 8.08 268356 5 3.85 -1 -1 58680 -1 -1 447 36 0 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 179696 36 100 10178 7632 1 2978 583 27 27 729 clb auto 104.4 MiB 16.70 43318 219643 62652 141928 15063 140.1 MiB 3.02 0.03 13.6111 -2272.14 -13.6111 13.6111 2.20 0.00651588 0.00551055 0.768924 0.662803 110 84751 33 3.93038e+07 2.40906e+07 5.33614e+06 7319.81 41.58 4.4518 3.87219 114714 1189977 -1 77052 17 14017 69317 4925517 913768 15.4853 15.4853 -2667.39 -15.4853 0 0 6.77266e+06 9290.34 1.99 1.35 0.86 -1 -1 1.99 0.624448 0.586094 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml boundtop.v common 17.08 vpr 71.96 MiB -1 -1 9.15 48936 3 0.67 -1 -1 39220 -1 -1 45 196 1 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 73692 196 193 1201 1346 1 604 435 15 15 225 io auto 33.8 MiB 0.47 2981 150312 44495 93614 12203 72.0 MiB 0.47 0.01 2.05507 -979.869 -2.05507 2.05507 0.57 0.00161266 0.00148292 0.165224 0.151168 40 7176 44 1.03862e+07 2.97323e+06 618415. 2748.51 3.52 0.779086 0.725008 23732 127356 -1 6238 14 2121 3542 344117 91418 2.57674 2.57674 -1194.23 -2.57674 -0.478269 -0.152189 773047. 3435.76 0.25 0.14 0.09 -1 -1 0.25 0.0824519 0.078801 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.66 vpr 66.66 MiB -1 -1 0.24 21888 3 0.09 -1 -1 36920 -1 -1 65 99 1 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 68260 99 130 344 474 1 221 295 12 12 144 clb auto 28.3 MiB 0.10 584 75832 24915 37314 13603 66.7 MiB 0.14 0.00 1.60782 -108.554 -1.60782 1.60782 0.30 0.000408101 0.000365301 0.032699 0.0291703 46 1375 14 5.66058e+06 4.05111e+06 408669. 2837.98 1.60 0.165947 0.151987 14568 82464 -1 1241 9 501 815 42163 14297 1.90052 1.90052 -138.848 -1.90052 -0.522528 -0.192271 525203. 3647.24 0.16 0.02 0.06 -1 -1 0.16 0.0164117 0.0156824 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq1.v common 13.23 vpr 69.73 MiB -1 -1 0.30 25348 5 0.16 -1 -1 38040 -1 -1 26 162 0 5 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 71408 162 96 1075 892 1 662 289 16 16 256 mult_36 auto 31.7 MiB 0.29 5020 87194 31634 49300 6260 69.7 MiB 0.37 0.01 15.5513 -1198.01 -15.5513 15.5513 0.60 0.00108968 0.00087173 0.117896 0.106419 62 11041 23 1.21132e+07 3.38124e+06 1.04918e+06 4098.38 9.27 0.629926 0.579055 30184 211102 -1 9365 22 3684 6482 1932785 501322 17.3515 17.3515 -1402.06 -17.3515 0 0 1.29183e+06 5046.22 0.37 0.35 0.14 -1 -1 0.37 0.0801783 0.0761602 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq2.v common 16.37 vpr 68.38 MiB -1 -1 0.22 24472 5 0.12 -1 -1 37504 -1 -1 16 66 0 5 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 70016 66 96 778 595 1 452 183 16 16 256 mult_36 auto 30.2 MiB 0.25 3796 47931 18238 24999 4694 68.4 MiB 0.23 0.01 11.6653 -721.689 -11.6653 11.6653 0.61 0.0021724 0.000634322 0.0820875 0.0733953 54 8985 24 1.21132e+07 2.8423e+06 903890. 3530.82 12.65 0.47082 0.431882 28908 188420 -1 7667 19 3422 6989 2894348 736724 13.1378 13.1378 -884.515 -13.1378 0 0 1.17254e+06 4580.24 0.33 0.47 0.12 -1 -1 0.33 0.054892 0.0522077 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU8PEEng.v common 453.19 vpr 634.28 MiB -1 -1 40.35 458136 97 67.61 -1 -1 116280 -1 -1 1817 114 45 8 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 649504 114 102 35834 31925 1 16655 2086 52 52 2704 clb auto 338.8 MiB 38.84 215398 1480939 529962 920626 30351 592.6 MiB 35.90 0.30 63.9023 -51832.3 -63.9023 63.9023 29.27 0.0365643 0.0313887 4.72225 3.98955 118 403134 41 1.58905e+08 1.25757e+08 2.19720e+07 8125.73 179.07 22.5222 19.4447 445196 4945367 -1 365440 26 84812 347712 59122473 12667064 72.9598 72.9598 -67594.2 -72.9598 -22.3536 -0.293253 2.76197e+07 10214.4 10.15 15.98 3.68 -1 -1 10.15 3.82828 3.51735 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU32PEEng.v common 4545.11 vpr 2.15 GiB -1 -1 128.48 1499332 97 635.41 -1 -1 358708 -1 -1 6264 114 168 32 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 2253068 114 102 120350 108159 1 57393 6680 94 94 8836 clb auto 1099.3 MiB 142.33 1002377 7741412 3101845 4587037 52530 1910.5 MiB 279.40 2.10 61.1772 -294786 -61.1772 61.1772 110.76 0.150743 0.129744 22.1123 18.9696 164 1599216 47 5.40921e+08 4.42296e+08 9.81028e+07 11102.6 2935.70 80.2872 69.5089 1741328 23094485 -1 1497489 23 245053 1111111 345304904 91442091 72.177 72.177 -449510 -72.177 -38.9067 -0.292146 1.25175e+08 14166.5 51.93 126.42 20.24 -1 -1 51.93 14.3855 13.1443 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mcml.v common 4052.63 vpr 2.22 GiB -1 -1 164.66 1254260 25 2216.02 -1 -1 373144 -1 -1 6092 36 159 27 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 2323188 36 356 185159 159806 1 63968 6670 93 93 8649 clb auto 1312.7 MiB 122.70 764984 9043966 3452533 5377457 213976 2034.1 MiB 415.93 2.64 44.0249 -277627 -44.0249 44.0249 108.37 0.156207 0.128577 24.3516 20.2318 154 1118635 43 5.27943e+08 4.26118e+08 9.06356e+07 10479.3 795.63 98.3709 83.4586 1641104 21087044 -1 1050884 22 254701 613161 130623601 28909159 47.7077 47.7077 -351690 -47.7077 -0.240863 -0.0215478 1.14427e+08 13230.1 50.66 42.81 17.78 -1 -1 50.66 12.7798 11.6449 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkDelayWorker32B.v common 81.80 vpr 381.34 MiB -1 -1 8.92 121524 5 3.40 -1 -1 48636 -1 -1 465 506 44 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 390492 506 553 3236 3734 1 2854 1568 50 50 2500 memory auto 59.1 MiB 3.82 16229 1176113 568893 419592 187628 381.3 MiB 3.45 0.04 6.96637 -2056.03 -6.96637 6.96637 26.67 0.0110014 0.0102196 1.51912 1.39252 38 25725 17 1.47946e+08 4.91733e+07 7.51727e+06 3006.91 17.42 4.40965 4.1239 284136 1605944 -1 24262 17 4753 6161 4413542 1107869 7.71942 7.71942 -2574.22 -7.71942 -2.60855 -0.216197 9.46795e+06 3787.18 3.63 1.26 1.04 -1 -1 3.63 0.594962 0.567469 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkPktMerge.v common 25.63 vpr 72.07 MiB -1 -1 0.91 29184 2 0.11 -1 -1 37840 -1 -1 27 311 15 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 73804 311 156 1015 1158 1 965 509 28 28 784 memory auto 34.2 MiB 0.53 8982 197516 69517 118417 9582 72.1 MiB 0.65 0.01 4.2275 -4143.2 -4.2275 4.2275 2.35 0.00294516 0.00258436 0.247937 0.21669 36 16496 41 4.25198e+07 9.67514e+06 2.12999e+06 2716.82 15.87 1.26374 1.13519 83724 436647 -1 14920 15 3351 3803 2953163 794022 4.6504 4.6504 -4999.11 -4.6504 -9.7666 -0.29768 2.61523e+06 3335.75 0.93 0.60 0.28 -1 -1 0.93 0.120155 0.111439 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 30.85 vpr 83.23 MiB -1 -1 4.12 55588 5 1.66 -1 -1 42932 -1 -1 149 193 5 0 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 85224 193 205 2718 2652 1 1332 552 20 20 400 memory auto 45.8 MiB 1.29 10421 235904 85730 126610 23564 83.2 MiB 1.30 0.02 4.51877 -2546.56 -4.51877 4.51877 1.07 0.00365451 0.00316066 0.355002 0.307152 70 21547 47 2.07112e+07 1.07702e+07 1.91061e+06 4776.53 16.53 1.28063 1.14003 50878 398303 -1 18601 27 5203 13861 2099937 567638 5.29174 5.29174 -3059.47 -5.29174 -15.9103 -0.360359 2.38830e+06 5970.76 0.71 0.66 0.29 -1 -1 0.71 0.266539 0.248322 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml or1200.v common 154.07 vpr 112.54 MiB -1 -1 3.35 66424 8 3.17 -1 -1 44760 -1 -1 197 385 2 1 success v8.0.0-10476-g8192a19e5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.5.0-41-generic x86_64 2024-06-20T15:31:36 amir-virtual-machine /home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts 115244 385 362 4415 4299 1 2339 947 26 26 676 io auto 60.2 MiB 2.89 28988 521523 209405 290824 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k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 27.67 vpr 81.39 MiB -1 -1 8.40 52340 5 1.67 -1 -1 39184 -1 -1 153 193 5 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 83348 193 205 2718 2652 1 1312 556 20 20 400 memory auto 40.5 MiB 1.63 10418 229056 84448 119534 25074 81.4 MiB 1.94 0.02 4.83454 -2775.8 -4.83454 4.83454 0.46 0.00747105 0.00675587 0.803493 0.724427 -1 -1 -1 -1 70 21360 50 2.07112e+07 1.09858e+07 1.91061e+06 4776.53 9.06 2.90045 2.57962 50878 398303 -1 18326 19 5117 13726 1090691 249377 5.12414 5.12414 -2964.88 -5.12414 -9.06217 -0.29768 2.38830e+06 5970.76 0.08 0.60 0.34 -1 -1 0.08 0.364174 0.332881 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml or1200.v common 59.32 vpr 146.60 MiB -1 -1 6.80 62912 8 3.09 -1 -1 40812 -1 -1 204 385 2 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 150116 385 362 4415 4299 1 2326 954 26 26 676 io auto 51.4 MiB 3.83 30125 531376 214642 295474 21260 95.4 MiB 5.55 0.06 8.97942 -9890.27 -8.97942 8.97942 0.83 0.0158337 0.0147615 1.8938 1.73964 -1 -1 -1 -1 114 54501 40 3.69863e+07 1.24864e+07 5.08094e+06 7516.19 31.17 8.59193 7.86741 107668 1126034 -1 49619 16 11645 40890 3693110 712663 9.15851 9.15851 -10214.8 -9.15851 0 0 6.39786e+06 9464.29 0.24 1.46 1.02 -1 -1 0.24 0.68108 0.635331 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 25.96 vpr 82.90 MiB -1 -1 4.81 42388 3 0.69 -1 -1 37636 -1 -1 119 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 84888 236 305 3199 3011 1 1524 667 19 19 361 io auto 42.1 MiB 2.05 12644 286141 98277 171517 16347 82.9 MiB 2.21 0.03 4.5478 -2822.52 -4.5478 4.5478 0.42 0.00865554 0.00800574 0.905484 0.832826 -1 -1 -1 -1 80 25223 29 1.72706e+07 9.33739e+06 1.90610e+06 5280.05 11.52 3.79468 3.45284 48118 405907 -1 22830 19 6383 17788 1956842 481346 4.7575 4.7575 -3031.05 -4.7575 -1.54347 -0.0248686 2.39503e+06 6634.44 0.08 0.78 0.34 -1 -1 0.08 0.409568 0.378879 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml sha.v common 18.13 vpr 80.55 MiB -1 -1 3.45 44440 3 1.25 -1 -1 39768 -1 -1 121 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82488 38 36 2739 2488 1 984 195 15 15 225 clb auto 39.8 MiB 1.29 8617 34660 8559 23743 2358 80.6 MiB 0.86 0.01 10.0462 -2585.64 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10.3557 10.3557 -7116.46 -10.3557 -31.3027 -0.291039 1.25485e+06 6402.29 0.04 0.32 0.18 -1 -1 0.04 0.147208 0.133753 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 71.25 vpr 232.06 MiB -1 -1 13.84 99732 5 5.91 -1 -1 66224 -1 -1 683 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 237628 169 197 23225 21365 1 6228 1049 33 33 1089 clb auto 145.1 MiB 8.78 39077 555161 184104 348094 22963 204.6 MiB 7.06 0.07 3.40795 -14164.9 -3.40795 3.40795 1.21 0.0300798 0.025615 3.1673 2.69001 -1 -1 -1 -1 62 66511 37 6.0475e+07 3.68097e+07 4.96186e+06 4556.35 18.00 12.1219 10.1215 136702 1027405 -1 58701 14 16735 29853 1708107 404784 3.86533 3.86533 -15733.8 -3.86533 0 0 6.10319e+06 5604.39 0.24 1.75 0.82 -1 -1 0.24 1.48602 1.32181 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 161.44 vpr 284.95 MiB -1 -1 11.10 122472 3 10.03 -1 -1 73980 -1 -1 735 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 291788 115 145 22864 19301 1 9598 1035 40 40 1600 mult_36 auto 143.0 MiB 8.97 82595 545267 173911 346139 25217 218.4 MiB 7.65 0.07 5.87645 -23504 -5.87645 5.87645 2.13 0.0172846 0.0150048 2.60308 2.21352 -1 -1 -1 -1 90 140847 35 9.16046e+07 5.54529e+07 1.01064e+07 6316.51 99.93 17.3403 14.5121 231184 2180983 -1 126035 16 32563 55258 9268189 2118021 5.97657 5.97657 -26242 -5.97657 0 0 1.25697e+07 7856.08 0.53 3.38 1.90 -1 -1 0.53 1.62332 1.44597 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 399.39 vpr 1.18 GiB -1 -1 14.77 195404 3 4.42 -1 -1 152116 -1 -1 1699 149 0 179 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1238432 149 182 55415 37074 1 28457 2209 80 80 6400 mult_36 auto 291.4 MiB 30.42 282130 2015409 700203 1241042 74164 1209.4 MiB 50.25 0.38 13.0924 -51849.3 -13.0924 13.0924 35.54 0.0801169 0.0709152 12.035 10.4119 -1 -1 -1 -1 98 402851 42 3.90281e+08 1.62448e+08 4.51112e+07 7048.62 201.61 57.5437 48.7486 982540 10083220 -1 377967 20 98609 121118 18647821 4175431 13.5095 13.5095 -57446.5 -13.5095 0 0 5.68725e+07 8886.33 2.78 8.88 9.38 -1 -1 2.78 4.65647 4.05835 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 2.77 vpr 65.82 MiB -1 -1 0.95 22856 4 0.13 -1 -1 32576 -1 -1 13 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67400 11 2 303 283 2 70 26 7 7 49 clb auto 26.2 MiB 0.11 226 786 179 539 68 65.8 MiB 0.04 0.00 2.04209 -156.405 -2.04209 1.90335 0.04 0.000811437 0.000734582 0.0207311 0.0191518 -1 -1 -1 -1 26 591 13 1.07788e+06 700622 75813.7 1547.22 0.37 0.188328 0.159692 3816 13734 -1 488 13 265 523 16601 6739 2.12916 1.93187 -166.884 -2.12916 0 0 91376.6 1864.83 0.00 0.04 0.01 -1 -1 0.00 0.0283251 0.0252471 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index 7fc0b70f933..cf218b6f42d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,20 +1,20 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 764024 257 32 36080 33722 1 19553 3015 63 63 3969 clb auto 301.6 MiB 92.59 246763 2158443 772925 1359244 26274 746.1 MiB 59.23 0.53 19.4596 -25520.8 -19.4596 19.4596 43.69 0.0991431 0.0880274 11.4343 9.85355 -1 -1 -1 -1 74 397392 33 2.36641e+08 1.5068e+08 2.02178e+07 5093.92 116.44 33.3094 28.6876 502298 4195434 -1 378911 20 104646 475755 22175267 3259151 19.4991 19.4991 -26097.4 -19.4991 0 0 2.53694e+07 6391.88 8.94 10.08 4.11 -1 -1 8.94 4.89274 4.39544 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 88.72 parmys 272.51 MiB -1 -1 13.84 279048 5 4.67 -1 -1 58908 -1 -1 487 36 0 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om 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39.2846 32.3608 494362 4028736 -1 366303 20 98427 446372 17944375 2776232 18.5784 18.5784 -26041.2 -18.5784 0 0 2.43753e+07 6141.41 1.21 11.43 3.66 -1 -1 1.21 5.85046 5.10781 + k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 78.97 parmys 261.77 MiB -1 -1 15.49 268052 5 3.27 -1 -1 55068 -1 -1 499 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 151748 36 100 10178 7632 1 2726 635 29 29 841 clb auto 89.3 MiB 20.97 41290 240699 69942 155074 15683 136.3 MiB 4.72 0.05 15.0315 -2426.67 -15.0315 15.0315 0.96 0.0200853 0.0181387 1.92947 1.71159 -1 -1 -1 -1 68 72348 36 4.4999e+07 2.68931e+07 3.78783e+06 4503.96 21.04 7.0819 6.06747 99460 760244 -1 61879 16 12452 65489 2491571 367156 14.9612 14.9612 -2605.63 -14.9612 0 0 4.70015e+06 5588.76 0.17 1.60 0.65 -1 -1 0.17 0.96287 0.854503 + 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3.69863e+07 1.49655e+07 4.42570e+06 6546.89 20.29 8.10528 7.4405 97812 938682 -1 40817 16 8863 29554 1529165 270024 9.38639 9.38639 -10275 -9.38639 0 0 5.60562e+06 8292.34 0.21 1.07 0.90 -1 -1 0.21 0.671683 0.625212 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 20.40 vpr 83.15 MiB -1 -1 4.95 42652 3 0.69 -1 -1 37712 -1 -1 129 236 1 6 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85144 236 305 3199 3011 1 1520 677 19 19 361 io auto 42.3 MiB 2.96 12613 265096 95493 155775 13828 83.1 MiB 2.04 0.03 4.87079 -2867.74 -4.87079 4.87079 0.39 0.00874694 0.00809124 0.837199 0.769496 -1 -1 -1 -1 60 22507 29 1.72706e+07 9.87633e+06 1.37250e+06 3801.94 5.31 2.82995 2.58049 40123 275431 -1 20290 17 5897 15357 1368544 349388 4.89215 4.89215 -3057.94 -4.89215 0 0 1.72840e+06 4787.81 0.06 0.66 0.24 -1 -1 0.06 0.37961 0.351635 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 18.68 vpr 81.04 MiB -1 -1 3.48 45112 3 1.23 -1 -1 39672 -1 -1 141 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 82988 38 36 2739 2488 1 1022 215 17 17 289 clb auto 40.1 MiB 1.97 8958 42653 11395 28389 2869 81.0 MiB 0.93 0.01 10.0306 -2595.46 -10.0306 10.0306 0.30 0.00563668 0.00499161 0.411349 0.362575 -1 -1 -1 -1 58 15080 45 1.34605e+07 7.59905e+06 1.03370e+06 3576.80 7.09 3.0793 2.62682 31195 207102 -1 12819 22 4248 9862 350375 63434 10.8941 10.8941 -2909.82 -10.8941 0 0 1.31783e+06 4559.95 0.04 0.45 0.18 -1 -1 0.04 0.322361 0.28551 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 14.62 vpr 72.09 MiB -1 -1 3.90 32592 16 0.46 -1 -1 34784 -1 -1 60 45 3 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 73824 45 32 1192 1151 1 782 141 14 14 196 memory auto 32.6 MiB 2.64 6823 26859 7335 15944 3580 72.1 MiB 0.56 0.01 10.958 -7233.76 -10.958 10.958 0.20 0.00348886 0.00309362 0.282542 0.250806 -1 -1 -1 -1 66 13449 49 9.20055e+06 5.27364e+06 787562. 4018.17 4.34 1.29546 1.12707 22236 154735 -1 10952 14 3335 8795 693161 168301 11.3764 11.3764 -7707.18 -11.3764 0 0 978561. 4992.66 0.03 0.31 0.14 -1 -1 0.03 0.156586 0.142149 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 70.08 vpr 230.16 MiB -1 -1 13.83 100176 5 5.66 -1 -1 66176 -1 -1 721 169 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 235688 169 197 23225 21365 1 6061 1087 34 34 1156 clb auto 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5.72315e+07 8.06023e+06 5037.64 224.38 20.2923 16.9388 200832 1659634 -1 114258 16 31257 49053 7202028 1662365 5.39064 5.39064 -25594 -5.39064 0 0 1.00808e+07 6300.50 0.41 3.41 1.46 -1 -1 0.41 1.81066 1.60735 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 283.85 vpr 1.02 GiB -1 -1 16.34 195452 3 5.92 -1 -1 152084 -1 -1 1699 149 0 179 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1072748 149 182 55415 37074 1 28414 2209 80 80 6400 mult_36 auto 290.2 MiB 30.79 283700 2029789 714222 1242257 73310 1047.6 MiB 50.81 0.36 13.4478 -51665.2 -13.4478 13.4478 27.71 0.0798307 0.0706002 12.5716 10.7877 -1 -1 -1 -1 90 390411 49 3.90281e+08 1.62448e+08 3.88106e+07 6064.16 94.93 41.9844 35.7412 876284 8162653 -1 372587 18 96713 115717 14180687 3026082 14.5611 14.5611 -57854.4 -14.5611 0 0 4.85641e+07 7588.14 2.99 7.91 7.71 -1 -1 2.99 4.41036 3.90021 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.78 vpr 65.62 MiB -1 -1 0.94 23248 4 0.13 -1 -1 32564 -1 -1 15 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67192 11 2 303 283 2 78 28 7 7 49 clb auto 26.0 MiB 0.21 280 994 173 731 90 65.6 MiB 0.04 0.00 2.0401 -164.361 -2.0401 1.90163 0.03 0.000802622 0.000736286 0.0231253 0.0212941 -1 -1 -1 -1 22 397 12 1.07788e+06 808410 57331.5 1170.03 0.32 0.150968 0.128977 3372 10412 -1 355 11 172 254 4023 1475 2.14906 1.91429 -169.055 -2.14906 0 0 72669.7 1483.05 0.00 0.02 0.01 -1 -1 0.00 0.0172996 0.0159743 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/complex_switch/config/golden_results.txt index 26f35c0cb09..0f7c6adf9a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/complex_switch/config/golden_results.txt @@ -1,15 +1,15 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_computation_time -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 1007.56 61.80 380120 33 527.79 -1 -1 155856 -1 -1 5518 257 0 11 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 740824 257 32 44336 43851 1 42630 5818 80 80 6400 clb auto 12.21 380622 220.45 1.55 11.7092 -17497.4 -11.7092 11.7092 2.55 0.144862 0.12537 17.4904 15.2114 629302 264104 928789 157555407 31822408 3.53436e+07 2.2827e+07 7.29424e+07 11397.2 22 13.5217 13.5217 -20134.9 -13.5217 0 0 45.19 25.7888 22.6024 92.57 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 173.12 1.10 63176 29 108.95 -1 -1 71316 -1 -1 1320 36 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 191492 36 100 10431 10531 1 9865 1456 41 41 1681 clb auto 1.99 86784 22.95 0.16 8.5404 -2112.82 -8.5404 8.5404 0.47 0.0301432 0.0276364 4.04612 3.56933 133541 32265 117599 16941686 3415266 8.95136e+06 5.148e+06 1.84779e+07 10992.2 17 9.80674 9.80674 -2510.99 -9.80674 0 0 5.59 5.6366 5.01098 20.62 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 5.68 1.71 47500 3 0.48 -1 -1 41592 -1 -1 95 114 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 48688 114 193 467 660 1 374 402 13 13 169 clb auto 0.06 924 0.58 0.01 0.986465 -136.23 -0.986465 0.986465 0.02 0.00103145 0.000965443 0.15685 0.14477 1391 652 1684 191231 53291 666600 370500 1.59550e+06 9440.85 10 1.24204 1.24204 -162.021 -1.24204 0 0 0.07 0.185245 0.171535 0.90 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU8PEEng.v common 754.34 53.97 218988 206 316.61 -1 -1 103528 -1 -1 4460 114 83 8 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 796396 114 102 38946 38672 1 36247 4767 86 86 7396 memory auto 11.71 361378 161.21 1.05 64.8355 -42040.9 -64.8355 64.8355 2.82 0.114274 0.102112 16.3456 14.0063 512938 127210 434360 149093030 54728319 4.18276e+07 2.52125e+07 8.44414e+07 11417.2 22 72.5688 72.5688 -74126.1 -72.5688 -91.783 -0.36083 62.77 23.6657 20.4208 103.26 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkDelayWorker32B.v common 132.24 2.33 70980 6 8.96 -1 -1 56172 -1 -1 556 506 80 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 568592 506 553 3331 3884 1 3325 1695 82 82 6724 memory auto 1.85 19665 8.00 0.05 5.41315 -1403.25 -5.41315 5.41315 2.41 0.0174197 0.0158973 3.90301 3.54119 22244 5019 6192 6593679 2064896 3.85878e+07 8.78824e+06 7.66484e+07 11399.2 22 5.80412 5.80412 -1685.69 -5.80412 -22.0148 -0.295672 2.56 4.86192 4.43996 84.17 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkSMAdapter4B.v common 29.64 0.65 30420 11 3.49 -1 -1 41004 -1 -1 290 193 10 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 127912 193 205 2764 2969 1 2139 698 37 37 1369 memory auto 0.51 15446 4.42 0.03 3.89872 -2235.27 -3.89872 3.89872 0.32 0.00590474 0.00534424 1.20788 1.0808 23806 7872 25612 4281475 1054152 7.45627e+06 1.95848e+06 1.49196e+07 10898.2 17 4.18699 4.18699 -2538.95 -4.18699 -21.4015 -0.375057 1.25 1.52081 1.37113 14.09 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml or1200.v common 32.90 1.07 41300 45 6.40 -1 -1 45596 -1 -1 537 385 4 1 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 92804 385 394 5238 5569 1 4569 1321 27 27 729 io clb auto 1.11 44444 9.30 0.08 12.7514 -9719.77 -12.7514 12.7514 0.15 0.0159747 0.0147929 2.05202 1.88151 64764 15911 59477 9238454 2259188 4.06709e+06 2.54409e+06 7.75339e+06 10635.7 18 13.7756 13.7756 -11602 -13.7756 0 0 3.06 2.89076 2.66235 7.23 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 17.99 0.91 33104 12 1.88 -1 -1 44080 -1 -1 238 214 0 9 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 77060 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.54 16418 3.03 0.03 3.92422 -1914.18 -3.92422 3.92422 0.14 0.00656181 0.00608415 0.846401 0.77718 24730 7679 24738 7723180 2175690 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 4.06116 4.06116 -2255.58 -4.06116 0 0 1.92 1.16466 1.07723 6.24 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 1056.11 1.67 39192 31 1031.42 -1 -1 100716 -1 -1 415 38 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 75364 38 36 4183 4219 1 3300 489 24 24 576 clb auto 0.77 25354 4.42 0.04 9.82213 -3175.08 -9.82213 9.82213 0.11 0.00968855 0.00863616 1.1447 1.02024 42061 13032 51882 6455399 1522523 2.72374e+06 1.6185e+06 6.03346e+06 10474.8 21 11.2064 11.2064 -3705.85 -11.2064 0 0 2.08 1.71248 1.5389 5.33 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision0.v common 184.76 4.38 126752 7 107.05 -1 -1 68844 -1 -1 1804 157 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 271352 157 197 22240 22437 1 13748 2158 47 47 2209 clb auto 2.96 84220 26.17 0.21 2.22026 -8656.91 -2.22026 2.22026 0.59 0.037802 0.0340611 4.73764 4.08936 117937 41975 124776 15267155 3638031 1.16296e+07 7.0356e+06 2.45588e+07 11117.6 20 2.72481 2.72481 -10955.7 -2.72481 0 0 5.44 6.87096 6.02615 24.11 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision1.v common 175.37 5.77 113240 10 58.42 -1 -1 82300 -1 -1 1727 113 0 44 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 414756 113 145 23279 21144 1 16131 2029 62 62 3844 mult_36 auto 3.45 135603 29.79 0.23 4.15694 -16481.2 -4.15694 4.15694 1.23 0.0416329 0.0377454 5.68248 5.00686 178625 53804 143259 49277285 13572124 2.17057e+07 1.19625e+07 4.33614e+07 11280.3 14 4.46736 4.46736 -20025.7 -4.46736 0 0 12.50 7.51511 6.69767 44.30 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision2.v common 1241.54 5.79 173160 26 378.79 -1 -1 192276 -1 -1 5847 149 0 324 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2498204 149 182 65520 55100 1 55662 6502 166 166 27556 mult_36 auto 15.45 721467 233.85 1.48 13.2018 -50280.1 -13.2018 13.2018 15.46 0.193755 0.179179 26.8642 23.8392 869347 249438 647829 149956053 38940076 1.58074e+08 6.12945e+07 3.19849e+08 11607.2 22 14.654 14.654 -65353.5 -14.654 0 0 49.45 38.371 34.2708 431.65 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU32PEEng.v common 3706.42 386.10 734200 205 1515.98 -1 -1 302652 -1 -1 15736 114 299 32 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2969444 114 102 136917 135515 1 128781 16283 169 169 28561 memory auto 43.66 1655811 967.80 5.86 64.0741 -218355 -64.0741 64.0741 14.97 0.492406 0.419883 67.1686 57.7487 2154289 413940 1453578 564216810 202871066 1.64515e+08 8.9937e+07 3.31299e+08 11599.7 23 72.8832 72.8832 -433622 -72.8832 -167.502 -0.303936 215.96 94.8038 81.9137 404.70 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mcml.v common 10344.00 161.82 928172 119 8767.92 -1 -1 451996 -1 -1 12886 36 318 27 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2934052 36 356 149309 148090 1 102868 13623 169 169 28561 memory auto 47.64 1306112 660.75 4.13 56.2791 -228686 -56.2791 56.2791 15.61 0.339155 0.289446 51.8499 44.2375 1254088 403135 1597976 260478491 64570437 1.64515e+08 7.97899e+07 3.31299e+08 11599.7 22 60.6003 60.6003 -331298 -60.6003 -2.30303 -0.226637 91.90 72.7285 62.7953 420.32 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 820.31 vpr 818.98 MiB 22.94 379780 -1 -1 32 493.71 -1 -1 153968 -1 -1 5640 257 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 838636 257 32 45172 44687 1 43466 5940 82 82 6724 clb auto 274.6 MiB 11.17 384723 5705772 2258487 3417250 30035 819.0 MiB 186.67 1.36 13.3718 -18525.1 -13.3718 13.3718 0.03 0.110171 0.0987148 13.7144 11.3248 -1 -1 -1 -1 628874 14.4698 281218 6.47058 231943 834736 117799524 24198893 3.85878e+07 2.33028e+07 7.66484e+07 11399.2 22 1605176 15314284 -1 14.2738 14.2738 -20331.9 -14.2738 0 0 26.63 -1 -1 819.0 MiB 33.05 20.0089 16.6262 819.0 MiB -1 12.97 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 117.17 vpr 229.33 MiB 0.80 62680 -1 -1 29 80.45 -1 -1 65976 -1 -1 1320 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 234836 36 100 10431 10531 1 9865 1456 41 41 1681 clb auto 79.6 MiB 1.19 88362 785111 276498 487029 21584 229.3 MiB 16.45 0.15 9.43813 -2197.84 -9.43813 9.43813 0.01 0.0259222 0.0233317 2.9831 2.58521 -1 -1 -1 -1 133197 13.5542 61268 6.23466 32071 117257 15958817 3230932 8.95136e+06 5.148e+06 1.84779e+07 10992.2 21 392750 3677203 -1 10.0034 10.0034 -2460.5 -10.0034 0 0 3.43 -1 -1 229.3 MiB 5.22 4.39364 3.77499 229.3 MiB -1 2.19 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 5.40 vpr 61.29 MiB 1.00 47020 -1 -1 3 0.73 -1 -1 36304 -1 -1 95 114 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62760 114 193 467 660 1 374 402 13 13 169 clb auto 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betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 92288 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 34.0 MiB 0.55 17879 291515 96968 176018 18529 90.1 MiB 2.35 0.03 4.04097 -2026.17 -4.04097 4.04097 0.00 0.00818863 0.00758309 0.716958 0.660563 -1 -1 -1 -1 25655 11.8335 11525 5.31596 7010 22783 3120920 787237 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 17 154908 1423382 -1 4.23901 4.23901 -2367.29 -4.23901 0 0 2.27 -1 -1 90.1 MiB 0.98 1.04854 0.966038 90.1 MiB -1 0.80 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 507.60 abc 94.12 MiB 2.17 38620 -1 -1 31 490.25 -1 -1 96384 -1 -1 415 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 90192 38 36 4183 4219 1 3300 489 24 24 576 clb auto 42.1 MiB 0.67 25112 129464 32825 91043 5596 88.1 MiB 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2.45588e+07 11117.6 17 519358 4899383 -1 2.78227 2.78227 -10971.6 -2.78227 0 0 8.05 -1 -1 299.5 MiB 4.74 5.585 4.74193 299.5 MiB -1 3.06 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision1.v common 133.27 vpr 456.01 MiB 2.84 112712 -1 -1 10 59.54 -1 -1 78852 -1 -1 1727 113 0 44 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 466952 113 145 23279 21144 1 16131 2029 62 62 3844 mult_36 auto 128.9 MiB 3.17 140319 1388749 540237 823922 24590 456.0 MiB 27.34 0.30 4.23653 -17527.9 -4.23653 4.23653 0.01 0.0402543 0.0340353 4.47252 3.79948 -1 -1 -1 -1 184868 11.4640 78781 4.88534 55253 150418 23440921 5522616 2.17057e+07 1.19625e+07 4.33614e+07 11280.3 18 911886 8653859 -1 4.41908 4.41908 -20082.8 -4.41908 0 0 14.29 -1 -1 456.0 MiB 6.84 6.33271 5.40445 456.0 MiB -1 5.77 + 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15714 114 299 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3232424 114 102 136826 135424 1 128691 16261 169 169 28561 memory auto 800.1 MiB 40.90 1648550 26579554 11638314 14888034 53206 3156.7 MiB 1171.83 7.03 68.7296 -221934 -68.7296 68.7296 0.11 0.405372 0.35607 60.6857 50.9192 -1 -1 -1 -1 2147445 16.6973 966035 7.51135 404100 1427772 190149727 42382132 1.64515e+08 8.98512e+07 3.31299e+08 11599.7 24 6883162 66233393 -1 72.585 72.585 -429947 -72.585 -155.254 -0.302614 84.55 -1 -1 3156.7 MiB 77.49 84.8887 70.8614 3156.7 MiB -1 53.53 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mcml.v common 8788.85 vpr 3.04 GiB 79.87 925408 -1 -1 126 7881.76 -1 -1 448912 -1 -1 12851 36 318 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3192572 36 356 149244 148025 1 102799 13588 169 169 28561 memory auto 753.1 MiB 34.19 1266788 22541457 10109273 12375850 56334 3117.7 MiB 496.30 3.25 57.3765 -244260 -57.3765 57.3765 0.10 0.277208 0.238866 42.0788 34.9139 -1 -1 -1 -1 1214744 11.8214 565313 5.50140 378455 1542517 186457172 43247061 1.64515e+08 7.96532e+07 3.31299e+08 11599.7 22 6883162 66233393 -1 60.677 60.677 -381776 -60.677 -0.394532 -0.113558 111.64 -1 -1 3117.7 MiB 58.29 57.4924 47.84 3117.7 MiB -1 41.52 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor/config/golden_results.txt index 75973eec4cc..1ee7575e46d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_mem32K_40nm.xml arm_core.v common 331.03 vpr 352.79 MiB 3.43 127948 -1 -1 25 78.58 -1 -1 67016 -1 -1 988 133 24 0 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 361256 133 179 17481 17660 1 8826 1324 39 39 1521 clb auto 160.6 MiB 14.98 140724 706223 235986 453985 16252 217.7 MiB 15.98 0.16 18.2294 -157339 -18.2294 18.2294 4.31 0.0518175 0.0450103 5.48347 4.5904 110 202350 37 8.65315e+07 6.64005e+07 1.06449e+07 6998.62 154.54 29.2861 24.3174 222560 2289922 -1 184414 17 36765 135743 9204794 1475613 18.3923 18.3923 -165829 -18.3923 0 0 1.35876e+07 8933.31 4.13 5.35 2.21 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v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 164148 36 100 6600 6700 1 2804 708 30 30 900 clb auto 85.7 MiB 5.72 45721 268798 80554 171964 16280 124.6 MiB 4.99 0.05 10.4727 -2786.41 -10.4727 10.4727 2.75 0.0200331 0.0180885 1.99302 1.75483 70 68828 17 4.8774e+07 3.08274e+07 4.18297e+06 4647.75 38.18 9.47628 8.14735 106732 854442 -1 63223 13 11344 57272 2422333 307988 10.6677 10.6677 -2866.66 -10.6677 0 0 5.26086e+06 5845.40 1.45 1.65 0.78 -1 -1 1.45 0.939592 0.842842 4998 5998 -1 -1 -1 -1 -k6_frac_N10_mem32K_40nm.xml boundtop.v common 8.26 vpr 65.03 MiB 0.87 47140 -1 -1 2 0.48 -1 -1 36316 -1 -1 82 114 0 0 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca 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-0.442561 -0.200829 6.13894e+07 7253.00 2.94 22.83 9.40 -1 -1 2.94 16.5586 14.3201 54006 83427 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt index 5ac538a2499..f01850ef9aa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 308.61 vpr 305.05 MiB 3.27 126928 -1 -1 18 66.85 -1 -1 66760 -1 -1 1012 133 24 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 312376 133 179 18379 18161 1 8999 1348 39 39 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-k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 9.83 vpr 70.61 MiB 0.78 45096 -1 -1 3 0.57 -1 -1 37852 -1 -1 92 142 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72304 142 193 1069 1140 1 565 427 14 14 196 clb auto 32.6 MiB 0.80 1818 153092 57142 75216 20734 70.6 MiB 0.62 0.01 2.94229 -453.47 -2.94229 2.94229 0.44 0.00272405 0.00251166 0.275175 0.256617 36 4119 16 9.20055e+06 4.95825e+06 447080. 2281.02 2.64 1.06006 0.974555 18336 87587 -1 3545 13 1258 1911 94099 25244 3.69367 3.69367 -542.415 -3.69367 0 0 553089. 2821.88 0.13 0.13 0.09 -1 -1 0.13 0.0988352 0.0924831 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 4.53 vpr 65.50 MiB 0.05 9484 -1 -1 3 0.26 -1 -1 34496 -1 -1 65 99 1 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 67072 99 130 363 493 1 251 295 12 12 144 clb auto 27.2 MiB 0.20 638 73870 25767 36592 11511 65.5 MiB 0.24 0.00 2.16091 -202.101 -2.16091 2.16091 0.29 0.00118083 0.00111179 0.093124 0.0877216 50 1437 12 5.66058e+06 4.05111e+06 406307. 2821.58 1.89 0.405518 0.373885 13806 78043 -1 1327 8 569 730 52502 16881 2.61821 2.61821 -233.044 -2.61821 0 0 520805. 3616.70 0.11 0.05 0.08 -1 -1 0.11 0.0284497 0.026703 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 13.99 vpr 69.25 MiB 0.06 9280 -1 -1 6 0.19 -1 -1 33940 -1 -1 32 162 0 5 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70916 162 96 1075 884 1 667 295 16 16 256 mult_36 auto 31.2 MiB 0.46 4874 89566 32886 48812 7868 69.3 MiB 0.63 0.01 15.5719 -1192.19 -15.5719 15.5719 0.58 0.00327511 0.00307934 0.313023 0.294075 56 10920 33 1.21132e+07 3.70461e+06 870502. 3400.40 9.22 1.43467 1.33244 27064 172478 -1 8779 20 3096 5045 1985336 525030 17.2923 17.2923 -1368.07 -17.2923 0 0 1.11200e+06 4343.75 0.25 0.56 0.17 -1 -1 0.25 0.152842 0.143207 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 14.41 vpr 68.06 MiB 0.03 8460 -1 -1 6 0.15 -1 -1 34036 -1 -1 20 66 0 7 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69696 66 96 866 607 1 547 189 18 18 324 mult_36 auto 30.0 MiB 0.52 4724 52221 19081 29168 3972 68.1 MiB 0.51 0.01 12.2609 -733.741 -12.2609 12.2609 0.81 0.00272171 0.00257763 0.273527 0.259203 56 9880 19 1.57076e+07 3.84988e+06 1.13764e+06 3511.25 9.37 1.08023 1.01222 34996 227580 -1 9332 18 2524 4965 2261378 561627 13.3921 13.3921 -853.374 -13.3921 0 0 1.45243e+06 4482.80 0.33 0.57 0.21 -1 -1 0.33 0.121498 0.114731 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 107.53 vpr 361.92 MiB 1.42 69584 -1 -1 5 7.33 -1 -1 52920 -1 -1 456 506 45 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 370608 506 553 3519 4017 1 3099 1560 50 50 2500 memory auto 59.9 MiB 6.56 16861 1186324 579266 419415 187643 361.9 MiB 5.63 0.06 6.76827 -1937.28 -6.76827 6.76827 23.26 0.0224339 0.020226 3.05307 2.73026 40 24703 14 1.47946e+08 4.92362e+07 7.18436e+06 2873.75 43.14 9.49117 8.61044 260716 1475984 -1 23814 15 3905 5017 3925951 988139 7.57899 7.57899 -2448.16 -7.57899 0 0 8.97548e+06 3590.19 2.90 1.66 1.29 -1 -1 2.90 0.845545 0.785123 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 24.15 vpr 80.12 MiB 0.21 16748 -1 -1 2 0.14 -1 -1 33692 -1 -1 29 311 15 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 82048 311 156 1019 1160 1 965 511 28 28 784 memory auto 33.3 MiB 0.68 8151 208795 74211 123852 10732 71.9 MiB 1.19 0.02 3.77691 -4038.98 -3.77691 3.77691 2.27 0.00554843 0.00487833 0.592245 0.51467 38 14576 26 4.25198e+07 9.78293e+06 2.03941e+06 2601.29 13.75 2.26322 1.99752 77878 418209 -1 13284 16 2916 3289 2664079 748370 4.13763 4.13763 -4801.24 -4.13763 0 0 2.58563e+06 3298.00 0.75 0.81 0.40 -1 -1 0.75 0.21968 0.198761 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 24.53 vpr 84.20 MiB 0.47 29304 -1 -1 4 1.88 -1 -1 37936 -1 -1 188 193 5 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86216 193 205 2863 2789 1 1455 591 20 20 400 memory auto 47.0 MiB 3.22 11478 258407 87714 143045 27648 84.2 MiB 1.97 0.02 4.57371 -2508.98 -4.57371 4.57371 1.04 0.00749779 0.0067406 0.85769 0.766693 56 20077 20 2.07112e+07 1.28721e+07 1.41661e+06 3541.53 10.45 3.10742 2.77127 43380 284034 -1 18046 16 5181 12425 986328 207359 4.99636 4.99636 -2921.82 -4.99636 0 0 1.80858e+06 4521.44 0.43 0.58 0.26 -1 -1 0.43 0.344018 0.316306 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 53.67 vpr 114.27 MiB 0.89 39788 -1 -1 8 4.31 -1 -1 41912 -1 -1 258 385 2 1 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 117016 385 394 4673 4537 1 2422 1040 27 27 729 io auto 62.8 MiB 9.22 31099 601478 234916 341577 24985 99.9 MiB 5.48 0.06 7.91028 -9390.87 -7.91028 7.91028 2.23 0.0167783 0.0155898 2.01423 1.8284 98 45582 18 3.93038e+07 1.53967e+07 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-k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 256.85 abc 92.51 MiB 2.09 38272 -1 -1 3 232.89 -1 -1 94728 -1 -1 156 38 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85824 38 36 2995 2744 1 1210 230 17 17 289 clb auto 47.2 MiB 2.42 11187 48102 12239 32898 2965 83.8 MiB 0.97 0.01 8.50665 -2425.54 -8.50665 8.50665 0.67 0.00570774 0.00499034 0.454841 0.394038 86 15535 20 1.34605e+07 8.40746e+06 1.47169e+06 5092.36 8.49 2.53112 2.17062 36379 299185 -1 14997 15 3639 10555 369332 60267 10.0216 10.0216 -2922.92 -10.0216 0 0 1.86203e+06 6443.01 0.42 0.39 0.32 -1 -1 0.42 0.285356 0.258031 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 15.68 vpr 73.31 MiB 0.29 20588 -1 -1 15 0.71 -1 -1 35832 -1 -1 65 45 3 1 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic 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8.64458 8.64458 -10958.4 -8.64458 0 0 5.38988e+06 7393.52 0.25 1.42 0.81 -1 -1 0.25 0.868994 0.807211 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 18.99 vpr 83.97 MiB 0.47 31632 -1 -1 3 1.30 -1 -1 40388 -1 -1 123 214 0 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85988 214 305 2963 2869 1 1444 650 19 19 361 io auto 42.9 MiB 2.34 11237 214514 71103 131344 12067 84.0 MiB 1.68 0.03 4.53 -2651.41 -4.53 4.53 0.30 0.0081428 0.00752702 0.697544 0.644697 -1 -1 -1 -1 58 21099 31 1.72706e+07 9.79696e+06 1.32779e+06 3678.09 8.10 3.22447 2.94147 39763 268823 -1 18983 16 5722 13316 1766310 456164 4.74311 4.74311 -2886.77 -4.74311 0 0 1.69263e+06 4688.74 0.06 0.69 0.28 -1 -1 0.06 0.345386 0.321329 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 272.73 abc 92.77 MiB 2.09 38268 -1 -1 3 250.47 -1 -1 94996 -1 -1 155 38 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85432 38 36 2995 2744 1 1203 229 17 17 289 clb auto 42.4 MiB 2.62 11670 42229 10578 28453 3198 83.4 MiB 1.05 0.02 9.56668 -2644.49 -9.56668 9.56668 0.30 0.00656702 0.00586724 0.468925 0.409101 -1 -1 -1 -1 68 16961 39 1.34605e+07 8.35357e+06 1.21205e+06 4193.96 7.72 3.3871 2.92303 32923 238265 -1 15449 21 4262 11796 386501 67599 10.0346 10.0346 -2927.77 -10.0346 0 0 1.50552e+06 5209.41 0.05 0.51 0.21 -1 -1 0.05 0.381624 0.341924 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 10.21 vpr 73.09 MiB 0.28 20756 -1 -1 15 0.70 -1 -1 35888 -1 -1 64 45 3 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74840 45 32 1275 1232 1 833 145 14 14 196 memory auto 33.5 MiB 3.02 7318 32445 8399 21096 2950 73.1 MiB 0.73 0.01 10.858 -7202.1 -10.858 10.858 0.20 0.00401825 0.00358124 0.372462 0.331214 -1 -1 -1 -1 62 14199 22 9.20055e+06 5.48922e+06 735792. 3754.04 2.60 1.09318 0.957143 21652 143691 -1 12039 14 3799 10270 769415 195252 11.2813 11.2813 -7721.94 -11.2813 0 0 913676. 4661.61 0.03 0.33 0.13 -1 -1 0.03 0.167019 0.15166 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 77.15 vpr 237.29 MiB 2.19 122604 -1 -1 5 8.30 -1 -1 70708 -1 -1 725 157 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 242980 157 197 23846 21799 1 6113 1079 34 34 1156 clb auto 153.0 MiB 11.42 40349 554279 179120 354733 20426 212.2 MiB 8.17 0.10 3.44133 -14164.6 -3.44133 3.44133 1.41 0.0419871 0.0368812 3.82221 3.26092 -1 -1 -1 -1 48 64709 42 6.50233e+07 3.90734e+07 3.79520e+06 3283.05 25.00 13.2504 11.1208 124420 775892 -1 55531 14 16382 26779 951067 191033 3.60577 3.60577 -14927 -3.60577 0 0 4.86353e+06 4207.21 0.21 1.74 0.66 -1 -1 0.21 1.638 1.46031 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 156.27 vpr 277.42 MiB 2.09 108040 -1 -1 3 48.42 -1 -1 84944 -1 -1 770 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 284076 115 145 23133 19546 1 9694 1070 40 40 1600 mult_36 auto 154.6 MiB 12.62 79581 586360 191379 370364 24617 221.6 MiB 10.93 0.12 5.13017 -22530.1 -5.13017 5.13017 2.15 0.0351572 0.0292193 4.14895 3.53646 -1 -1 -1 -1 80 127150 44 9.16046e+07 5.73393e+07 8.41679e+06 5260.49 54.58 16.4025 13.7039 205632 1754580 -1 114217 13 29778 46242 7115265 1603973 5.57953 5.57953 -24422.4 -5.57953 0 0 1.06125e+07 6632.80 0.42 3.05 1.43 -1 -1 0.42 1.6584 1.47502 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 651.40 vpr 1.60 GiB 2.63 156012 -1 -1 3 8.81 -1 -1 202312 -1 -1 1977 149 0 324 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1678240 149 182 65737 42630 1 35715 2632 104 104 10816 mult_36 auto 374.2 MiB 40.04 311596 2454907 884079 1495837 74991 1638.9 MiB 70.37 0.48 14.6044 -61020 -14.6044 14.6044 49.60 0.117008 0.105376 17.0093 14.9395 -1 -1 -1 -1 68 450703 48 6.67561e+08 2.34845e+08 5.23589e+07 4840.87 395.44 72.2092 62.3025 1334630 10731989 -1 422434 19 118711 141570 15462485 3411624 15.8253 15.8253 -68233.2 -15.8253 0 0 6.49608e+07 6005.99 3.14 9.68 9.88 -1 -1 3.14 6.01093 5.31531 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.51 vpr 66.34 MiB 0.09 10100 -1 -1 5 0.14 -1 -1 33148 -1 -1 14 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67928 11 30 313 321 2 115 55 7 7 49 clb auto 26.7 MiB 0.30 456 2239 413 1740 86 66.3 MiB 0.05 0.00 2.65898 -171.948 -2.65898 2.30209 0.04 0.000886162 0.000807618 0.0241056 0.022178 -1 -1 -1 -1 30 934 29 1.07788e+06 754516 77114.5 1573.76 0.50 0.245302 0.207397 3660 13876 -1 783 19 469 889 29198 10184 2.65817 2.36697 -188.291 -2.65817 0 0 95414.1 1947.23 0.00 0.06 0.01 -1 -1 0.00 0.0401555 0.0354168 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 424.13 vpr 654.30 MiB 5.41 206884 -1 -1 101 90.71 -1 -1 104380 -1 -1 2232 114 44 8 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 670004 114 102 38224 33865 1 17936 2500 57 57 3249 clb auto 296.0 MiB 88.56 238874 1969860 742285 1191850 35725 654.3 MiB 73.26 0.61 75.9908 -52848.4 -75.9908 75.9908 13.94 0.119995 0.0990419 13.9371 11.5851 -1 -1 -1 -1 92 346294 24 1.92089e+08 1.47573e+08 1.98119e+07 6097.84 92.04 46.6101 38.3968 448119 4205394 -1 325298 22 78986 295129 14718681 2597490 76.1097 76.1097 -61489.2 -76.1097 0 0 2.51903e+07 7753.25 1.12 11.41 4.01 -1 -1 1.12 6.75644 5.7346 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 2794.92 vpr 2.15 GiB 27.20 702236 -1 -1 101 880.69 -1 -1 313852 -1 -1 7600 114 167 32 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2255188 114 102 124851 111146 1 58871 8015 103 103 10609 clb auto 934.7 MiB 293.36 1043923 10110191 4211863 5843486 54842 2044.4 MiB 496.28 3.13 76.166 -325620 -76.166 76.166 46.17 0.380796 0.319544 52.0019 43.437 -1 -1 -1 -1 124 1367703 42 6.46441e+08 5.13746e+08 8.61045e+07 8116.18 832.38 166.433 135.976 1699828 18865638 -1 1310007 22 217059 913739 52502988 8651301 76.2861 76.2861 -462427 -76.2861 0 0 1.09063e+08 10280.2 5.97 42.07 19.66 -1 -1 5.97 24.2946 20.4139 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5521.11 vpr 2.21 GiB 66.02 890848 -1 -1 26 3208.51 -1 -1 375960 -1 -1 7302 36 159 27 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2318968 36 356 190343 166383 1 60659 7880 101 101 10201 clb auto 1094.9 MiB 354.20 718639 11686500 4557070 6682417 447013 2151.0 MiB 494.38 3.08 47.0709 -322999 -47.0709 47.0709 43.14 0.339115 0.29521 56.3357 46.8416 -1 -1 -1 -1 124 957569 42 6.22828e+08 4.91323e+08 8.26363e+07 8100.80 1146.80 253.769 207.967 1632490 18090185 -1 921573 21 221603 569140 33110457 5760400 46.3566 46.3566 -361674 -46.3566 0 0 1.04691e+08 10262.8 4.87 27.77 18.47 -1 -1 4.87 19.8348 17.1642 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_depop/config/golden_results.txt index 1a2d7cfe27e..26cbed08b92 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_depop/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 366.18 3.53 128232 18 85.76 -1 -1 72148 -1 -1 844 133 24 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 279720 133 179 18339 18121 1 8939 1180 36 36 1296 clb memory auto 17.97 133843 22.52 0.15 18.4184 -141279 -18.4184 18.4184 4.69 0.0517384 0.045552 7.30796 6.28578 146 224959 37 7.21828e+07 5.86395e+07 1.23606e+07 9537.51 162.12 27.1627 23.7865 207535 16 38497 147575 36095601 8273636 20.0278 20.0278 -158267 -20.0278 0 0 1.55729e+07 12016.1 4.98 11.95 3.08151 2.82269 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 991.52 11.78 375836 14 288.16 -1 -1 150616 -1 -1 2305 257 0 11 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 740404 257 32 36518 33906 1 19046 2605 58 58 3364 clb auto 54.16 247747 99.40 0.70 17.1218 -23175.7 -17.1218 17.1218 47.00 0.12732 0.115715 16.2724 14.0282 116 491009 49 2.00088e+08 1.28585e+08 2.71672e+07 8075.87 394.04 94.3203 82.2886 462659 23 111035 519425 47964581 8402128 19.6696 19.6696 -26147.4 -19.6696 0 0 3.40353e+07 10117.5 13.44 20.98 8.74929 7.88966 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml blob_merge.v common 193.24 1.09 58604 5 57.92 -1 -1 68924 -1 -1 539 36 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 152832 36 100 14036 11283 1 3780 675 29 29 841 clb auto 14.61 47553 10.67 0.07 12.9252 -2650.36 -12.9252 12.9252 2.93 0.0311144 0.0273874 4.25977 3.76907 98 99647 41 4.4999e+07 2.90489e+07 5.54665e+06 6595.30 86.90 15.1417 13.4298 87659 18 16525 73018 5640392 977319 14.2116 14.2116 -3076.05 -14.2116 0 0 6.99642e+06 8319.17 2.27 2.98 1.70896 1.57933 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml boundtop.v common 10.24 1.31 45200 3 0.54 -1 -1 41320 -1 -1 89 142 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 59272 142 193 1069 1140 1 530 424 14 14 196 clb auto 0.64 1531 0.95 0.01 2.94005 -452.908 -2.94005 2.94005 0.52 0.00225564 0.0021036 0.393919 0.363586 40 3930 14 9.20055e+06 4.79657e+06 529800. 2703.06 3.23 1.15439 1.07156 3532 10 1272 2291 141758 41077 3.56317 3.56317 -566.913 -3.56317 0 0 662635. 3380.79 0.20 0.12 0.0875529 0.0837756 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.25 0.09 9780 3 0.31 -1 -1 39504 -1 -1 64 99 1 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 39260 99 130 363 493 1 261 294 12 12 144 clb auto 0.16 697 0.37 0.00 2.11495 -207.011 -2.11495 2.11495 0.33 0.000674017 0.00061544 0.111707 0.101902 42 1903 12 5.66058e+06 3.99722e+06 373597. 2594.42 0.79 0.266683 0.245564 1800 12 675 938 87522 29405 2.95628 2.95628 -261.888 -2.95628 0 0 468675. 3254.69 0.14 0.05 0.0280509 0.0265793 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq1.v common 11.56 0.07 9564 6 0.20 -1 -1 38684 -1 -1 26 162 0 5 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 56408 162 96 1075 884 1 667 289 16 16 256 mult_36 auto 0.50 5078 0.88 0.01 15.3726 -1203.18 -15.3726 15.3726 0.69 0.00332607 0.00315459 0.443145 0.418579 60 11156 33 1.21132e+07 3.38124e+06 1.01260e+06 3955.47 6.53 1.39261 1.32314 9613 24 3616 6215 1828440 447202 17.5186 17.5186 -1462.9 -17.5186 0 0 1.26536e+06 4942.82 0.37 0.56 0.203639 0.19536 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq2.v common 14.18 0.05 8820 6 0.12 -1 -1 37868 -1 -1 16 66 0 7 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 50700 66 96 866 607 1 533 185 18 18 324 mult_36 auto 0.34 4735 0.79 0.01 12.0481 -714.751 -12.0481 12.0481 0.97 0.00333463 0.00317376 0.459311 0.436907 52 11667 29 1.57076e+07 3.6343e+06 1.14165e+06 3523.62 8.28 1.3168 1.26106 10315 22 4558 9816 5259633 1258198 13.5233 13.5233 -870.647 -13.5233 0 0 1.50318e+06 4639.44 0.46 1.24 0.172405 0.166447 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU8PEEng.v common 766.66 14.64 210096 101 114.35 -1 -1 107972 -1 -1 1851 114 44 8 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 600612 114 102 38224 33865 1 17424 2119 53 53 2809 clb auto 71.39 224050 83.22 0.59 66.8715 -51660.4 -66.8715 66.8715 38.17 0.129414 0.108857 17.3431 14.5804 124 411569 38 1.63647e+08 1.27041e+08 2.38080e+07 8475.60 354.88 74.7883 64.1041 376538 25 80780 317832 56593788 12162753 74.6606 74.6606 -65414.8 -74.6606 -28.8437 -0.20415 3.00291e+07 10690.3 11.73 25.38 8.85759 7.88032 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml LU32PEEng.v common 4509.90 62.45 709160 101 1034.68 -1 -1 317808 -1 -1 6269 114 167 32 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2426076 114 102 124851 111146 1 58394 6684 94 94 8836 clb auto 233.08 1032133 522.71 2.89 66.4852 -332544 -66.4852 66.4852 133.48 0.425542 0.37957 64.5818 55.4437 172 1599600 42 5.40921e+08 4.4202e+08 1.03144e+08 11673.2 2170.22 308.629 265.121 1517775 23 238646 1029395 273863959 63708210 77.2438 77.2438 -489390 -77.2438 -29.2742 -0.172573 1.30092e+08 14722.9 50.71 112.15 28.4487 25.2671 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mcml.v common 6426.13 123.41 897628 26 3730.31 -1 -1 376940 -1 -1 6697 36 159 27 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 2551024 36 356 190343 166383 1 60345 7275 97 97 9409 clb auto 271.63 729788 715.92 3.10 40.1533 -303194 -40.1533 40.1533 130.72 0.369181 0.328539 77.2606 65.5418 160 1078522 36 5.71422e+08 4.58721e+08 1.01844e+08 10824.1 1168.73 286.245 247.747 1023525 21 252001 682213 135772294 30665549 42.8992 42.8992 -363536 -42.8992 0 0 1.29602e+08 13774.3 41.27 52.44 22.4858 20.3437 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkDelayWorker32B.v common 101.95 2.12 71084 5 8.50 -1 -1 56628 -1 -1 453 506 45 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 367804 506 553 3519 4017 1 3086 1557 50 50 2500 memory auto 6.04 15906 7.85 0.06 6.63464 -1807.67 -6.63464 6.63464 33.19 0.0190454 0.0175723 4.04596 3.69702 40 24763 18 1.47946e+08 4.90746e+07 7.85310e+06 3141.24 22.40 9.11031 8.44651 23665 16 4699 6227 4255095 1086941 7.29496 7.29496 -2223.41 -7.29496 -5.03631 -0.193229 9.77405e+06 3909.62 4.02 1.79 0.908857 0.861995 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkPktMerge.v common 18.64 0.27 17032 2 0.10 -1 -1 39696 -1 -1 25 311 15 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 58432 311 156 1019 1160 1 954 507 28 28 784 memory auto 0.70 7932 1.32 0.02 3.65703 -4338.92 -3.65703 3.65703 2.60 0.00445569 0.00397936 0.641896 0.568983 40 14723 37 4.25198e+07 9.56735e+06 2.32339e+06 2963.51 7.86 1.97475 1.78872 13500 17 3399 3683 2547833 716874 4.00095 4.00095 -5037.99 -4.00095 -15.6433 -0.322548 2.89875e+06 3697.39 1.03 0.76 0.215687 0.201099 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 31.99 0.62 30404 4 2.26 -1 -1 42960 -1 -1 165 193 5 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 75044 193 205 2863 2789 1 1379 568 20 20 400 memory auto 1.85 11348 3.19 0.02 4.02531 -2513.1 -4.02531 4.02531 1.17 0.00644756 0.00579169 1.25044 1.11965 78 22965 36 2.07112e+07 1.16325e+07 2.06176e+06 5154.39 17.43 4.00817 3.64129 20086 16 5564 15748 1823107 397997 4.53843 4.53843 -2890.18 -4.53843 -7.37934 -0.298787 2.60035e+06 6500.87 0.74 0.74 0.372287 0.350206 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml or1200.v common 94.88 1.04 40356 8 6.19 -1 -1 45260 -1 -1 205 385 2 1 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 125560 385 394 4673 4537 1 2360 987 27 27 729 io auto 5.43 30254 7.09 0.08 8.05283 -9285.19 -8.05283 8.05283 2.53 0.01604 0.0150071 2.35096 2.17604 114 55965 25 3.93038e+07 1.25403e+07 5.50397e+06 7550.03 60.09 10.3708 9.63043 50867 20 11261 40543 5771240 1124941 8.79936 8.79936 -10123.8 -8.79936 0 0 6.92971e+06 9505.78 2.34 2.27 0.939816 0.886385 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 28.13 0.86 32028 3 1.28 -1 -1 44032 -1 -1 100 214 0 8 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 75072 214 305 2963 2869 1 1464 627 19 19 361 io auto 2.03 10704 2.27 0.03 4.29962 -2466.29 -4.29962 4.29962 1.13 0.00731701 0.00680645 0.95926 0.888097 64 26676 46 1.72706e+07 8.5574e+06 1.60702e+06 4451.57 14.42 3.71517 3.46917 21800 23 7166 16966 4782812 1073669 5.04074 5.04074 -3013.22 -5.04074 0 0 1.98721e+06 5504.73 0.60 1.47 0.489947 0.465483 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml sha.v common 336.02 1.83 39076 3 311.80 -1 -1 95840 -1 -1 138 38 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 63968 38 36 2995 2744 1 1208 212 16 16 256 clb auto 2.24 11256 1.96 0.02 8.87371 -2382.95 -8.87371 8.87371 0.63 0.00574619 0.00517374 0.816572 0.721565 80 21797 26 1.21132e+07 7.43737e+06 1.29183e+06 5046.22 8.75 2.7517 2.45615 19351 22 5540 18113 1095161 241229 10.3694 10.3694 -2917.57 -10.3694 0 0 1.62458e+06 6346.00 0.42 0.73 0.488978 0.452337 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml spree.v common 16.08 0.43 21076 15 0.90 -1 -1 39404 -1 -1 49 45 3 1 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 61968 45 32 1275 1232 1 822 130 14 14 196 memory auto 1.25 6630 1.02 0.01 9.55177 -6480.8 -9.55177 9.55177 0.53 0.003215 0.00286306 0.531553 0.469804 100 14267 33 9.20055e+06 4.68081e+06 1.19340e+06 6088.79 8.66 1.84126 1.64944 12397 14 3745 10984 1853298 463403 10.4092 10.4092 -7370.27 -10.4092 -17.8589 -0.318417 1.49920e+06 7648.97 0.40 0.58 0.193835 0.181911 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 82.00 3.90 122720 5 9.54 -1 -1 74484 -1 -1 684 157 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 215576 157 197 23846 21799 1 6801 1038 33 33 1089 clb auto 9.15 40314 10.39 0.08 2.95855 -13303.1 -2.95855 2.95855 3.75 0.0355087 0.0318712 4.99483 4.32205 64 68056 41 6.0475e+07 3.68636e+07 5.14656e+06 4725.95 23.14 16.0714 14.2441 64167 14 19652 32945 2075106 479443 3.72591 3.72591 -16028.1 -3.72591 0 0 6.36035e+06 5840.54 2.14 2.15 1.91861 1.77768 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 219.37 3.83 108224 3 44.46 -1 -1 88564 -1 -1 642 115 0 40 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 250728 115 145 23133 19546 1 9748 942 40 40 1600 mult_36 auto 8.25 76270 12.86 0.10 4.99955 -21585.1 -4.99955 4.99955 5.73 0.0345488 0.0302806 5.44775 4.79445 88 140299 45 9.16046e+07 5.04406e+07 9.92704e+06 6204.40 110.77 19.7099 17.5419 123303 21 39408 63999 27118412 5502186 5.37438 5.37438 -25122.8 -5.37438 0 0 1.23763e+07 7735.20 4.04 7.66 2.4484 2.25387 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 724.91 4.83 155612 3 8.43 -1 -1 206404 -1 -1 1650 149 0 324 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 1739948 149 182 65737 42630 1 35997 2305 104 104 10816 mult_36 auto 37.71 335815 72.99 0.46 14.4526 -61711 -14.4526 14.4526 150.35 0.147959 0.138663 24.3248 22.1024 74 514709 36 6.67561e+08 2.17223e+08 6.06274e+07 5605.34 305.65 72.9675 66.743 498077 20 143781 170712 57264364 11639493 16.5372 16.5372 -74959.5 -16.5372 0 0 7.58441e+07 7012.22 31.42 20.46 8.60695 7.98987 -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 1.84 0.11 10352 5 0.14 -1 -1 37956 -1 -1 15 11 0 0 success v8.0.0-4442-g4cb3b2f11e Release VTR_ASSERT_LEVEL=2 GNU 8.4.1 on Linux-4.18.0-193.el8.x86_64 x86_64 2021-08-19T16:17:54 node3 /root/mntssd/sdamghan 39304 11 30 313 321 2 108 56 7 7 49 clb auto 0.22 395 0.11 0.00 2.36605 -152.494 -2.36605 1.9999 0.07 0.000476264 0.000407281 0.0613289 0.0518885 30 1169 31 1.07788e+06 808410 84241.2 1719.21 0.29 0.152431 0.131534 944 17 532 1516 56407 21898 3.07845 2.37233 -183.444 -3.07845 0 0 103128. 2104.65 0.02 0.04 0.0304834 0.0280591 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 291.79 vpr 347.77 MiB 3.33 127036 -1 -1 18 74.78 -1 -1 67044 -1 -1 872 133 24 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 356120 133 179 18379 18161 1 8747 1208 37 37 1369 clb auto 145.3 MiB 15.93 137022 644308 210792 408526 24990 210.7 MiB 18.69 0.17 18.7 -143058 -18.7 18.7 1.99 0.0513907 0.0451283 5.97214 5.04592 -1 -1 -1 -1 144 231078 40 7.54166e+07 6.01486e+07 1.29396e+07 9451.85 123.77 29.648 24.5435 245398 2948354 -1 212508 17 38157 152893 14612869 2727745 18.7504 18.7504 -151687 -18.7504 0 0 1.63545e+07 11946.3 0.70 6.32 2.90 -1 -1 0.70 2.70475 2.36868 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 702.65 vpr 776.92 MiB 8.38 372860 -1 -1 14 292.94 -1 -1 148272 -1 -1 2367 257 0 11 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 795564 257 32 36518 33906 1 18590 2667 59 59 3481 clb auto 295.1 MiB 48.10 232761 1851367 648559 1173107 29701 776.9 MiB 80.06 0.71 19.6105 -25503 -19.6105 19.6105 19.00 0.119316 0.0995551 12.6353 10.6839 -1 -1 -1 -1 116 474814 37 2.05423e+08 1.31927e+08 2.81418e+07 8084.40 174.27 58.363 48.4476 570456 6327992 -1 447334 22 105897 511864 38703318 7252307 20.1588 20.1588 -26078.4 -20.1588 0 0 3.52566e+07 10128.3 1.65 19.56 5.93 -1 -1 1.65 7.38155 6.28162 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml blob_merge.v common 111.67 vpr 184.46 MiB 0.80 57480 -1 -1 5 43.53 -1 -1 60652 -1 -1 558 36 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 188888 36 100 14036 11283 1 3586 694 30 30 900 clb auto 100.3 MiB 14.56 46175 277084 82401 176673 18010 152.1 MiB 6.40 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-3.14227 0 0 106806. 2179.72 0.00 0.06 0.01 -1 -1 0.00 0.0336665 0.0299623 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index 824194a6ab7..157e870f862 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 251.29 vpr 303.75 MiB 3.28 127012 -1 -1 18 65.68 -1 -1 66884 -1 -1 1007 133 24 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 311040 133 179 18379 18161 1 9013 1343 39 39 1521 clb auto 152.8 MiB 31.39 140193 682695 221032 446886 14777 210.8 MiB 14.72 0.14 18.176 -144006 -18.176 18.176 4.29 0.0467304 0.0408974 5.01063 4.16549 106 200122 36 8.65315e+07 6.74245e+07 1.02794e+07 6758.33 76.41 24.1645 19.9956 222144 2202216 -1 184785 15 34752 126432 8486145 1348247 18.6662 18.6662 -149802 -18.6662 0 0 1.30215e+07 8561.12 3.97 4.51 2.13 -1 -1 3.97 2.36837 2.09021 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 711.33 vpr 742.11 MiB 8.37 372936 -1 -1 14 252.96 -1 -1 148516 -1 -1 2733 257 0 11 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 759924 257 32 36518 33906 1 19753 3033 63 63 3969 clb auto 305.2 MiB 77.43 251640 2197533 785535 1383157 28841 711.8 MiB 56.39 0.46 22.0986 -25607.7 -22.0986 22.0986 35.61 0.097897 0.0873488 10.8107 9.09204 76 386174 24 2.36641e+08 1.5165e+08 2.05973e+07 5189.55 198.88 48.3847 40.1382 506266 4280222 -1 369691 17 89404 400289 17805551 2620128 21.9711 21.9711 -26032.3 -21.9711 0 0 2.57532e+07 6488.59 8.27 10.52 3.93 -1 -1 8.27 5.3122 4.6658 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 148.52 vpr 160.05 MiB 0.82 57516 -1 -1 5 38.40 -1 -1 60452 -1 -1 609 36 0 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 163892 36 100 14036 11283 1 3163 745 31 31 961 clb auto 102.2 MiB 20.95 46654 280953 83651 183127 14175 151.0 MiB 5.41 0.06 15.0401 -2810.04 -15.0401 15.0401 2.68 0.0248194 0.0222841 2.3908 2.09588 64 75521 30 5.14688e+07 3.28214e+07 4.14665e+06 4314.93 62.14 8.74606 7.4094 112594 842736 -1 69312 18 13194 61399 2737755 355281 15.4757 15.4757 -3153.97 -15.4757 0 0 5.17798e+06 5388.12 1.46 2.04 0.73 -1 -1 1.46 1.28924 1.13534 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 8.62 vpr 70.13 MiB 0.79 45160 -1 -1 3 0.52 -1 -1 37624 -1 -1 93 142 0 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 71812 142 193 1069 1140 1 564 428 14 14 196 clb auto 31.1 MiB 0.86 1785 155180 53402 81741 20037 70.1 MiB 0.64 0.01 3.40722 -519.076 -3.40722 3.40722 0.40 0.00295831 0.00277456 0.29625 0.277905 38 3853 13 9.20055e+06 5.01214e+06 467348. 2384.43 1.47 0.899196 0.827427 18724 93853 -1 3532 13 1201 1810 86141 22375 3.56925 3.56925 -566.287 -3.56925 0 0 593372. 3027.41 0.14 0.14 0.09 -1 -1 0.14 0.102861 0.0959338 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 4.34 vpr 65.18 MiB 0.09 9376 -1 -1 3 0.27 -1 -1 34460 -1 -1 65 99 1 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66748 99 130 363 493 1 251 295 12 12 144 clb auto 26.5 MiB 0.21 684 70927 26093 33715 11119 65.2 MiB 0.24 0.00 2.16753 -221.96 -2.16753 2.16753 0.27 0.00128722 0.00121798 0.0980525 0.0928592 48 1590 12 5.66058e+06 4.05111e+06 394078. 2736.65 1.65 0.318924 0.293792 13662 75965 -1 1464 10 579 744 48078 14435 2.53703 2.53703 -236.896 -2.53703 0 0 503203. 3494.47 0.11 0.06 0.08 -1 -1 0.11 0.0346272 0.0321752 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 9.14 vpr 68.76 MiB 0.06 9328 -1 -1 6 0.19 -1 -1 33860 -1 -1 32 162 0 5 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 70412 162 96 1075 884 1 667 295 16 16 256 mult_36 auto 29.7 MiB 0.46 5073 90547 34495 49420 6632 68.8 MiB 0.66 0.01 15.7804 -1282.87 -15.7804 15.7804 0.54 0.00344845 0.00325196 0.335594 0.31644 50 10999 25 1.21132e+07 3.70461e+06 780532. 3048.95 4.56 1.13443 1.05201 26044 153858 -1 9441 23 3578 6220 1122545 304860 17.3814 17.3814 -1445.82 -17.3814 0 0 1.00276e+06 3917.05 0.22 0.40 0.14 -1 -1 0.22 0.16867 0.156716 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 8.75 vpr 67.72 MiB 0.05 8412 -1 -1 6 0.11 -1 -1 34004 -1 -1 20 66 0 7 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 69344 66 96 866 607 1 547 189 18 18 324 mult_36 auto 28.7 MiB 0.53 4838 50053 18112 27527 4414 67.7 MiB 0.49 0.01 12.8146 -774.958 -12.8146 12.8146 0.70 0.00286604 0.00272622 0.274795 0.261333 50 10773 26 1.57076e+07 3.84988e+06 1.01955e+06 3146.77 3.98 0.818492 0.765277 33704 203160 -1 9373 17 2969 6034 1588307 392502 13.3571 13.3571 -857.233 -13.3571 0 0 1.31112e+06 4046.65 0.32 0.45 0.19 -1 -1 0.32 0.12041 0.113131 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 486.28 vpr 647.63 MiB 4.97 206932 -1 -1 101 83.52 -1 -1 104732 -1 -1 2199 114 44 8 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 663176 114 102 38224 33865 1 17989 2467 57 57 3249 clb auto 297.2 MiB 84.76 227277 1885273 706303 1153591 25379 647.6 MiB 53.07 0.44 77.0036 -54799.5 -77.0036 77.0036 29.03 0.101882 0.0902043 12.9534 10.9689 90 342868 50 1.92089e+08 1.45795e+08 1.94366e+07 5982.34 159.71 49.9328 41.2187 441623 4070163 -1 316684 22 71362 268219 14425695 2440308 75.9872 75.9872 -66532.1 -75.9872 0 0 2.43249e+07 7486.90 7.96 10.67 3.93 -1 -1 7.96 6.34937 5.40817 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 3371.54 vpr 2.18 GiB 25.62 702172 -1 -1 101 753.58 -1 -1 313596 -1 -1 7552 114 167 32 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2285976 114 102 124851 111146 1 58906 7967 103 103 10609 clb auto 932.5 MiB 276.34 1006475 9870431 4090428 5732521 47482 2124.1 MiB 291.99 2.06 76.3766 -329212 -76.3766 76.3766 95.41 0.331227 0.286267 46.2628 38.3296 122 1362422 39 6.46441e+08 5.11157e+08 8.50538e+07 8017.14 1667.77 174.578 141.534 1678612 18422568 -1 1285265 23 216810 910698 54424616 8669592 76.9472 76.9472 -462152 -76.9472 0 0 1.06559e+08 10044.2 36.54 37.26 19.11 -1 -1 36.54 21.793 18.3927 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 102.09 vpr 346.82 MiB 1.39 69476 -1 -1 5 7.46 -1 -1 52940 -1 -1 455 506 45 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 355148 506 553 3519 4017 1 3098 1559 50 50 2500 memory auto 52.9 MiB 6.91 15738 1167203 573865 408695 184643 346.8 MiB 5.62 0.06 8.15634 -2061.78 -8.15634 8.15634 22.07 0.0230057 0.0207868 3.09735 2.77898 40 23618 12 1.47946e+08 4.91823e+07 7.18436e+06 2873.75 38.79 9.28894 8.42624 260716 1475984 -1 22655 13 3528 4688 1066656 244291 8.5462 8.5462 -2299.68 -8.5462 0 0 8.97548e+06 3590.19 2.87 1.07 1.31 -1 -1 2.87 0.851835 0.787338 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 20.06 vpr 71.95 MiB 0.20 16756 -1 -1 2 0.14 -1 -1 33788 -1 -1 29 311 15 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73676 311 156 1019 1160 1 965 511 28 28 784 memory auto 31.2 MiB 0.68 8035 202669 69067 122737 10865 71.6 MiB 1.10 0.01 4.10149 -4326.24 -4.10149 4.10149 1.84 0.00557566 0.0049467 0.576345 0.510587 36 14965 37 4.25198e+07 9.78293e+06 1.94918e+06 2486.20 11.50 2.77766 2.44983 76314 389223 -1 13484 16 3019 3398 733958 195651 4.26998 4.26998 -4913.56 -4.26998 0 0 2.40571e+06 3068.51 0.59 0.21 0.24 -1 -1 0.59 0.116413 0.107369 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 27.04 vpr 83.75 MiB 0.44 29296 -1 -1 4 1.86 -1 -1 37936 -1 -1 188 193 5 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85756 193 205 2863 2789 1 1453 591 20 20 400 memory auto 43.1 MiB 3.32 11779 260886 94839 139163 26884 83.7 MiB 2.04 0.02 4.8458 -2825.08 -4.8458 4.8458 0.89 0.0087501 0.00794583 0.897826 0.808388 56 21068 24 2.07112e+07 1.28721e+07 1.41661e+06 3541.53 13.13 3.63749 3.22428 43380 284034 -1 18265 16 5239 12681 720235 141227 5.24613 5.24613 -2968.77 -5.24613 0 0 1.80858e+06 4521.44 0.41 0.49 0.26 -1 -1 0.41 0.332556 0.303997 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 67.72 vpr 131.64 MiB 0.86 39800 -1 -1 8 4.23 -1 -1 41976 -1 -1 259 385 2 1 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 134804 385 394 4673 4537 1 2433 1041 27 27 729 io auto 55.2 MiB 10.57 30554 596890 229640 341672 25578 99.3 MiB 5.51 0.06 8.56969 -10033.6 -8.56969 8.56969 1.91 0.017043 0.0159102 2.03907 1.87536 86 47938 49 3.93038e+07 1.54505e+07 3.99564e+06 5480.99 34.06 10.2417 9.40982 95941 833781 -1 44029 16 10606 36784 2224832 374938 9.06418 9.06418 -10476.9 -9.06418 0 0 5.05392e+06 6932.68 1.32 1.30 0.76 -1 -1 1.32 0.725604 0.677829 -k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 21.80 vpr 83.66 MiB 0.46 31556 -1 -1 3 1.08 -1 -1 40384 -1 -1 111 214 0 8 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85672 214 305 2963 2869 1 1447 638 19 19 361 io auto 42.6 MiB 1.92 10418 247688 84171 150756 12761 83.7 MiB 1.67 0.02 4.42375 -2655.65 -4.42375 4.42375 0.80 0.00798008 0.00737723 0.762737 0.704597 56 23860 44 1.72706e+07 9.15023e+06 1.27879e+06 3542.35 9.76 3.27062 2.98117 39043 256479 -1 19879 21 6749 14800 2385939 557556 5.10564 5.10564 -2970.78 -5.10564 0 0 1.63234e+06 4521.70 0.38 0.93 0.23 -1 -1 0.38 0.424617 0.392906 -k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 251.55 abc 92.76 MiB 2.17 38236 -1 -1 3 225.30 -1 -1 94988 -1 -1 156 38 0 0 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85160 38 36 2995 2744 1 1210 230 17 17 289 clb auto 42.3 MiB 2.48 11201 48102 12472 32994 2636 83.2 MiB 0.97 0.02 9.47702 -2554.42 -9.47702 9.47702 0.61 0.0063397 0.00562943 0.447857 0.393122 76 15652 22 1.34605e+07 8.40746e+06 1.31783e+06 4559.95 10.18 3.3249 2.84916 34363 263318 -1 15129 21 4392 11758 429882 72221 10.5367 10.5367 -2771.23 -10.5367 0 0 1.64970e+06 5708.31 0.38 0.50 0.26 -1 -1 0.38 0.360128 0.321557 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.68 vpr 72.22 MiB 0.27 20592 -1 -1 15 0.71 -1 -1 36136 -1 -1 66 45 3 1 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73956 45 32 1275 1232 1 824 147 14 14 196 memory auto 32.7 MiB 2.97 6859 19497 5084 12799 1614 72.2 MiB 0.40 0.01 10.7449 -6919.42 -10.7449 10.7449 0.40 0.00363787 0.0032179 0.210155 0.186402 64 13021 35 9.20055e+06 5.597e+06 762053. 3888.03 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stereovision1.v common 510.49 vpr 283.80 MiB 2.13 108044 -1 -1 3 38.46 -1 -1 85052 -1 -1 678 115 0 40 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-21T11:43:07 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 290612 115 145 23133 19546 1 9709 978 40 40 1600 mult_36 auto 154.1 MiB 9.54 77055 505586 160836 322573 22177 219.6 MiB 8.75 0.09 5.14456 -22824.9 -5.14456 5.14456 4.14 0.0328707 0.0285435 3.72216 3.17758 82 126675 47 9.16046e+07 5.23808e+07 8.58295e+06 5364.35 417.83 20.4189 16.9525 207228 1787768 -1 113536 16 33307 52542 8887375 1849878 5.45065 5.45065 -24933.1 -5.45065 0 0 1.07702e+07 6731.38 2.57 3.31 1.58 -1 -1 2.57 1.56913 1.39099 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 2861.32 vpr 1.55 GiB 2.81 155972 -1 -1 3 8.15 -1 -1 202304 -1 -1 1651 149 0 324 success v8.0.0-11339-g6580b06f9 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on 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9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 85724 38 36 2995 2744 1 1203 229 17 17 289 clb auto 42.7 MiB 2.57 11167 52729 13839 35434 3456 83.7 MiB 1.24 0.02 9.59018 -2500.97 -9.59018 9.59018 0.30 0.00667277 0.00596243 0.5591 0.492955 -1 -1 -1 -1 82 15259 20 1.34605e+07 8.35357e+06 1.40210e+06 4851.55 6.49 2.96999 2.56897 35515 283594 -1 14972 18 3872 10498 343968 59662 9.98784 9.98784 -2667.34 -9.98784 0 0 1.76468e+06 6106.15 0.06 0.47 0.26 -1 -1 0.06 0.362081 0.327087 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.05 vpr 72.99 MiB 0.29 20668 -1 -1 15 0.70 -1 -1 35812 -1 -1 64 45 3 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 74744 45 32 1275 1232 1 833 145 14 14 196 memory auto 33.7 MiB 3.01 7652 27505 7618 16255 3632 73.0 MiB 0.62 0.01 10.691 -7011.57 -10.691 10.691 0.20 0.00407573 0.00364622 0.321464 0.28675 -1 -1 -1 -1 62 15473 48 9.20055e+06 5.48922e+06 735792. 3754.04 5.46 1.62663 1.41102 21652 143691 -1 12219 13 3871 10505 808512 198580 11.0765 11.0765 -7405.88 -11.0765 0 0 913676. 4661.61 0.03 0.32 0.13 -1 -1 0.03 0.157056 0.142388 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 66.34 vpr 236.52 MiB 2.39 122680 -1 -1 5 8.93 -1 -1 70664 -1 -1 725 157 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 242196 157 197 23846 21799 1 6113 1079 34 34 1156 clb auto 153.2 MiB 11.54 37343 548747 178166 350972 19609 212.3 MiB 8.04 0.08 3.49124 -14535.8 -3.49124 3.49124 1.42 0.0327851 0.0281188 3.66298 3.11758 -1 -1 -1 -1 48 57477 42 6.50233e+07 3.90734e+07 3.79520e+06 3283.05 13.55 11.3359 9.50466 124420 775892 -1 51658 15 14989 25110 795733 164333 3.60577 3.60577 -15598.6 -3.60577 0 0 4.86353e+06 4207.21 0.19 1.69 0.65 -1 -1 0.19 1.62548 1.44591 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 155.80 vpr 280.15 MiB 2.07 108084 -1 -1 3 41.43 -1 -1 85040 -1 -1 770 115 0 40 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 286876 115 145 23133 19546 1 9694 1070 40 40 1600 mult_36 auto 155.7 MiB 12.68 85346 569950 187665 359942 22343 223.0 MiB 10.74 0.11 5.55558 -22870.2 -5.55558 5.55558 2.00 0.0333171 0.0289197 4.0955 3.47462 -1 -1 -1 -1 80 136599 42 9.16046e+07 5.73393e+07 8.41679e+06 5260.49 60.65 16.774 14.0251 205632 1754580 -1 121367 14 31850 50930 8085714 1789124 5.72554 5.72554 -24797.3 -5.72554 0 0 1.06125e+07 6632.80 0.42 3.47 1.56 -1 -1 0.42 1.74483 1.54499 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 445.99 vpr 1.59 GiB 2.63 156000 -1 -1 3 9.33 -1 -1 202412 -1 -1 1977 149 0 324 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1671480 149 182 65737 42630 1 35715 2632 104 104 10816 mult_36 auto 374.6 MiB 47.00 310719 2454907 886319 1494591 73997 1632.3 MiB 60.07 0.43 14.7463 -61160.2 -14.7463 14.7463 47.78 0.118274 0.101341 16.6524 14.322 -1 -1 -1 -1 82 428353 18 6.67561e+08 2.34845e+08 6.06625e+07 5608.59 189.46 61.0549 52.5839 1431962 12793479 -1 415735 19 110977 130643 13538006 2940585 15.6742 15.6742 -67719.7 -15.6742 0 0 7.60166e+07 7028.16 5.73 9.74 11.93 -1 -1 5.73 6.36463 5.6674 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.45 vpr 66.30 MiB 0.10 10100 -1 -1 5 0.14 -1 -1 33352 -1 -1 14 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67888 11 30 313 321 2 115 55 7 7 49 clb auto 26.6 MiB 0.29 442 2239 416 1756 67 66.3 MiB 0.05 0.00 2.68099 -175.84 -2.68099 2.3116 0.03 0.000896631 0.000814667 0.0241545 0.0222358 -1 -1 -1 -1 34 820 13 1.07788e+06 754516 84249.8 1719.38 0.50 0.250037 0.211786 3756 15224 -1 668 12 330 657 15383 5482 2.64229 2.29364 -186.64 -2.64229 0 0 103542. 2113.11 0.00 0.04 0.01 -1 -1 0.00 0.0303299 0.0271649 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt index 35fdb3b3809..1618cfa66c0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt @@ -1,13 +1,13 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 626.87 vpr 2.66 GiB -1 -1 24.67 191020 5 89.67 -1 -1 105608 -1 -1 495 355 32 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2792576 355 289 25456 18471 2 12407 1436 136 136 18496 dsp_top auto 180.7 MiB 13.83 368135 1183744 493906 488436 201402 2727.1 MiB 35.16 0.42 5.73066 -86703.7 -5.73066 2.25058 0.11 0.0983282 0.0890725 15.1492 13.7417 -1 399829 14 5.92627e+08 8.54694e+07 4.08527e+08 22087.3 7.31 19.1592 17.4802 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 799.06 vpr 2.68 GiB -1 -1 30.89 236424 5 69.76 -1 -1 112992 -1 -1 691 357 58 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2813040 357 289 25618 20285 2 12722 1661 136 136 18496 dsp_top auto 197.5 MiB 55.89 213644 1506110 545980 704875 255255 2747.1 MiB 49.90 0.35 8.83586 -77757.5 -8.83586 2.86849 0.11 0.105103 0.090362 16.4628 14.294 -1 283893 19 5.92627e+08 9.47716e+07 4.08527e+08 22087.3 8.40 21.5402 18.8962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 3237.76 vpr 1.75 GiB -1 -1 126.10 731412 6 929.01 -1 -1 385924 -1 -1 3877 206 132 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1833128 206 13 164958 139473 1 69399 4340 88 88 7744 dsp_top auto 871.7 MiB 1763.83 586613 4179888 1553321 2546374 80193 1784.5 MiB 159.68 1.39 6.29198 -174132 -6.29198 6.29198 0.04 0.263075 0.225128 34.3779 28.6399 -1 859908 16 2.4541e+08 1.54779e+08 1.69370e+08 21871.2 23.49 48.5031 40.9766 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 918.71 vpr 2.01 GiB -1 -1 112.54 721200 3 53.45 -1 -1 407272 -1 -1 6192 260 0 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2104752 260 122 206293 154384 1 87490 6637 87 87 7569 clb auto 1055.8 MiB 200.86 911610 7737417 3028323 4214852 494242 1900.1 MiB 277.91 1.72 7.9787 -159676 -7.9787 7.9787 0.06 0.341965 0.297905 48.7798 40.5529 -1 1218227 15 2.37162e+08 1.8877e+08 1.65965e+08 21927.0 30.12 65.5345 55.1217 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1191.18 vpr 3.18 GiB -1 -1 47.78 306884 5 13.75 -1 -1 130992 -1 -1 1017 1052 689 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 3339012 1052 32 45949 36457 1 23546 2888 148 148 21904 memory auto 263.0 MiB 454.46 385837 3230494 1321380 1766067 143047 3260.8 MiB 52.88 0.34 5.87433 -113350 -5.87433 5.87433 0.24 0.111118 0.0973142 18.7476 15.9101 -1 553277 14 7.00618e+08 1.48101e+08 4.83549e+08 22075.8 11.90 23.3539 19.9146 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 438.38 vpr 1.58 GiB -1 -1 34.58 250276 3 10.72 -1 -1 57100 -1 -1 1736 1016 21 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1661604 1016 2244 12839 14381 1 7080 5029 104 104 10816 io auto 118.5 MiB 54.63 69414 5776141 2967220 2032347 776574 1622.7 MiB 33.15 0.30 5.80519 -19744.2 -5.80519 5.80519 0.06 0.114 0.109937 15.6713 15.1362 -1 95582 12 3.44415e+08 5.43781e+07 2.37404e+08 21949.3 4.19 19.3247 18.6816 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 224.40 vpr 636.46 MiB -1 -1 19.66 145672 4 78.57 -1 -1 78688 -1 -1 822 91 56 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 651736 91 65 33180 28067 2 12875 1076 56 56 3136 dsp_top auto 204.4 MiB 13.58 151571 552176 183815 346994 21367 636.5 MiB 17.47 0.16 4.40509 -58703.1 -4.40509 1.89924 0.02 0.0783544 0.0686597 8.59202 7.37464 -1 224439 15 9.76016e+07 4.13053e+07 6.79229e+07 21659.1 6.09 12.1898 10.5564 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 116.04 vpr 569.43 MiB -1 -1 8.18 81248 4 6.69 -1 -1 53088 -1 -1 347 152 72 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 583100 152 97 14409 12199 2 6807 715 56 56 3136 dsp_top auto 117.4 MiB 7.36 124818 317119 107522 190476 19121 569.4 MiB 8.89 0.08 4.4815 -25326.7 -4.4815 1.84186 0.02 0.0480688 0.0422026 5.14069 4.43436 -1 186870 15 9.76016e+07 3.15225e+07 6.79229e+07 21659.1 4.38 7.18579 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 358788 37 17 16391 14146 1 8915 818 38 38 1444 memory auto 137.3 MiB 14.11 105295 279970 72756 197091 10123 350.4 MiB 10.45 0.13 7.06442 -39775.7 -7.06442 7.06442 0.01 0.0494477 0.0400803 3.91592 3.25677 -1 170768 15 4.31434e+07 2.70267e+07 3.09543e+07 21436.5 5.08 6.15937 5.24586 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 246.16 vpr 1.09 GiB -1 -1 14.70 182348 6 12.93 -1 -1 65636 -1 -1 640 82 232 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1146036 82 17 16311 14407 1 9001 1003 84 84 7056 memory auto 131.9 MiB 18.91 164110 517857 170628 329215 18014 1119.2 MiB 10.31 0.09 5.96682 -42713.4 -5.96682 5.96682 0.04 0.0429465 0.0371059 4.93488 4.13355 -1 221993 13 2.2198e+08 5.79185e+07 1.54484e+08 21894.0 3.85 6.78436 5.76686 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 126.95 vpr 532.81 MiB -1 -1 18.55 274480 10 7.84 -1 -1 54340 -1 -1 509 402 0 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 545596 402 150 12958 11781 1 7797 1098 54 54 2916 dsp_top auto 111.8 MiB 12.34 77765 759806 267210 447457 45139 532.8 MiB 11.70 0.09 9.87808 -14325.3 -9.87808 9.87808 0.02 0.0314036 0.0282571 4.5226 3.98994 -1 127390 16 8.95105e+07 2.35932e+07 6.32721e+07 21698.2 3.35 6.16259 5.47084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params 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ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 403.97 vpr 2.65 GiB -1 -1 27.04 195044 5 106.86 -1 -1 105652 -1 -1 495 355 32 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2775544 355 289 25456 18471 2 12407 1436 136 136 18496 dsp_top auto 181.9 MiB 14.33 368181 1183744 474183 500499 209062 2710.5 MiB 50.60 0.36 6.27285 -87227.7 -6.27285 2.41691 0.16 0.0944157 0.083473 15.1293 13.4111 -1 -1 -1 -1 -1 397143 14 5.92627e+08 8.54694e+07 4.06343e+08 21969.2 7.49 19.5196 17.4915 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 485.95 vpr 2.66 GiB -1 -1 32.96 239408 5 93.21 -1 -1 112976 -1 -1 692 357 58 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2794012 357 289 25618 20285 2 12707 1662 136 136 18496 dsp_top auto 196.6 MiB 74.03 204219 1477662 530714 687623 259325 2728.5 MiB 65.29 0.50 8.71579 -77765.6 -8.71579 2.84893 0.14 0.106621 0.0894359 17.147 14.7028 -1 -1 -1 -1 -1 272598 15 5.92627e+08 9.47995e+07 4.06343e+08 21969.2 8.67 22.1078 19.1507 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 3187.00 vpr 1.76 GiB -1 -1 135.92 741364 6 1100.21 -1 -1 386172 -1 -1 3883 206 132 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1843948 206 13 164958 139473 1 69077 4346 88 88 7744 dsp_top auto 864.0 MiB 1603.34 598826 4152113 1544840 2523381 83892 1782.2 MiB 192.92 1.61 6.17742 -176710 -6.17742 6.17742 0.07 0.280575 0.239482 35.9089 29.7338 -1 -1 -1 -1 -1 874166 15 2.4541e+08 1.54946e+08 1.68961e+08 21818.3 23.70 50.4751 42.3862 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 980.53 vpr 2.01 GiB -1 -1 121.38 724396 3 65.16 -1 -1 413088 -1 -1 6188 260 0 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2111292 260 122 206293 154384 1 87503 6633 87 87 7569 clb auto 1048.9 MiB 248.33 933232 7793508 3012748 4270571 510189 1893.4 MiB 363.87 2.02 8.4354 -165730 -8.4354 8.4354 0.18 0.380851 0.332948 58.9838 49.134 -1 -1 -1 -1 -1 1241876 17 2.37162e+08 1.88658e+08 1.65555e+08 21872.8 35.08 80.5452 67.6492 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1019.17 vpr 3.17 GiB -1 -1 50.11 309328 5 18.79 -1 -1 130796 -1 -1 1014 1052 689 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3321220 1052 32 45949 36457 1 23546 2885 148 148 21904 memory auto 265.1 MiB 621.52 376641 3225938 1321836 1766785 137317 3243.4 MiB 76.56 0.45 5.99366 -116290 -5.99366 5.99366 0.19 0.11632 0.101899 21.137 17.8618 -1 -1 -1 -1 -1 544069 15 7.00618e+08 1.48017e+08 4.81367e+08 21976.2 12.72 26.4051 22.4726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 271.02 vpr 1.57 GiB -1 -1 34.97 254660 3 15.43 -1 -1 57052 -1 -1 1736 1016 21 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1650312 1016 2244 12839 14381 1 7081 5029 104 104 10816 io auto 117.8 MiB 63.44 68346 5733073 2929241 2032735 771097 1611.6 MiB 32.98 0.35 5.38086 -19733 -5.38086 5.38086 0.10 0.0995445 0.0938666 11.2455 10.5313 -1 -1 -1 -1 -1 92607 12 3.44415e+08 5.43781e+07 2.36688e+08 21883.2 3.62 14.072 13.2228 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 213.84 vpr 632.73 MiB -1 -1 20.39 146052 4 104.38 -1 -1 78744 -1 -1 822 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 647920 91 65 33180 28067 2 12875 1076 56 56 3136 dsp_top auto 201.5 MiB 15.44 158826 574220 192944 356720 24556 632.7 MiB 22.31 0.22 4.75154 -59481.6 -4.75154 1.95632 0.02 0.0860187 0.071022 9.6672 8.16677 -1 -1 -1 -1 -1 232357 14 9.76016e+07 4.13053e+07 6.76749e+07 21580.0 7.21 14.0547 12.1109 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 73.95 vpr 566.66 MiB -1 -1 8.53 82624 4 9.77 -1 -1 52912 -1 -1 347 152 72 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 580264 152 97 14409 12199 2 6807 715 56 56 3136 dsp_top auto 116.7 MiB 7.82 130332 301139 98285 185179 17675 566.7 MiB 10.85 0.09 4.58313 -25716.3 -4.58313 1.83211 0.02 0.0509694 0.0448212 4.90516 4.21666 -1 -1 -1 -1 -1 192276 17 9.76016e+07 3.15225e+07 6.76749e+07 21580.0 4.60 7.25998 6.31837 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 141.86 vpr 554.43 MiB -1 -1 27.53 239804 5 12.19 -1 -1 73308 -1 -1 879 3 84 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 567732 3 384 24647 23015 1 12378 1368 52 52 2704 memory auto 178.3 MiB 32.27 104695 783241 253492 461340 68409 554.4 MiB 22.37 0.20 6.19687 -42215.9 -6.19687 6.19687 0.02 0.0595205 0.0515804 6.95887 5.87936 -1 -1 -1 -1 -1 173357 15 8.30642e+07 4.06598e+07 5.83674e+07 21585.6 5.81 10.5413 8.96615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 93.71 vpr 350.35 MiB -1 -1 25.19 304144 6 10.96 -1 -1 71232 -1 -1 712 37 52 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 358756 37 17 16391 14146 1 8915 818 38 38 1444 memory auto 138.1 MiB 16.31 103074 283794 73510 200452 9832 350.3 MiB 13.72 0.18 7.80678 -46783.6 -7.80678 7.80678 0.01 0.0569771 0.046255 4.57139 3.84797 -1 -1 -1 -1 -1 168838 15 4.31434e+07 2.70267e+07 3.08517e+07 21365.5 5.31 7.24145 6.19502 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 150.73 vpr 1.09 GiB -1 -1 15.53 192572 6 17.60 -1 -1 65652 -1 -1 640 82 232 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1139224 82 17 16311 14407 1 9001 1003 84 84 7056 memory auto 131.2 MiB 24.12 161654 512839 166422 330721 15696 1112.5 MiB 14.74 0.14 5.92411 -42285.5 -5.92411 5.92411 0.04 0.0545381 0.0484051 5.9995 4.95943 -1 -1 -1 -1 -1 221106 13 2.2198e+08 5.79185e+07 1.54074e+08 21835.9 5.32 8.85254 7.45605 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 97.02 vpr 529.11 MiB -1 -1 18.64 282652 10 10.36 -1 -1 54676 -1 -1 509 402 0 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 541812 402 150 12958 11781 1 7797 1098 54 54 2916 dsp_top auto 110.3 MiB 14.87 77639 782454 270167 471812 40475 529.1 MiB 16.11 0.11 9.76271 -14362.7 -9.76271 9.76271 0.02 0.0338217 0.030505 5.28917 4.58948 -1 -1 -1 -1 -1 127260 18 8.95105e+07 2.35932e+07 6.30449e+07 21620.3 3.66 7.21419 6.31064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt index 4ea32240074..151af3ae337 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt @@ -1,12 +1,12 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 201.27 vpr 538.53 MiB -1 -1 14.22 148148 4 99.16 -1 -1 82672 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 551452 91 65 33165 28052 2 12600 1073 56 56 3136 dsp_top auto 244.3 MiB 9.12 161313 538.5 MiB 10.25 0.09 4.50414 -54857.1 -4.50414 1.86763 0.63 0.0333838 0.0282316 4.09029 3.44363 -1 232302 15 9.76016e+07 4.12216e+07 6.79229e+07 21659.1 4.09 6.05253 5.21178 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml conv_layer.v common 145.29 vpr 432.02 MiB -1 -1 14.29 148156 4 71.59 -1 -1 82796 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 442384 91 65 33165 28052 2 12600 1073 43 43 1849 clb auto 243.1 MiB 9.11 141700 374.5 MiB 9.13 0.07 5.05127 -54802.7 -5.05127 1.99938 0.52 0.0334928 0.0286294 3.82869 3.23515 -1 215950 13 7.83573e+07 4.12216e+07 3.65050e+07 19743.1 3.80 5.6478 4.90047 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml conv_layer.v common 175.29 vpr 425.96 MiB -1 -1 14.26 148180 4 104.45 -1 -1 82784 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 436188 91 65 33165 28052 2 12600 1073 41 41 1681 clb auto 243.0 MiB 9.14 135366 360.1 MiB 9.58 0.08 4.81704 -54070.3 -4.81704 1.94407 0.52 0.0355404 0.0290583 4.00237 3.37018 -1 205971 13 6.86832e+07 4.12216e+07 3.32309e+07 19768.5 3.68 5.83621 5.04962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.densest.xml conv_layer.v common 215.08 vpr 435.70 MiB -1 -1 14.07 148580 4 104.84 -1 -1 82748 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 446152 91 65 33165 28052 2 12600 1073 43 43 1849 clb auto 244.4 MiB 14.51 126010 378.6 MiB 17.73 0.14 4.60704 -53858.4 -4.60704 1.89311 0.99 0.0685799 0.0604241 7.88606 6.71765 -1 195885 13 7.74951e+07 4.12216e+07 3.64482e+07 19712.4 6.00 11.2599 9.77571 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.denser.xml conv_layer.v common 218.67 vpr 423.79 MiB -1 -1 14.11 148508 4 111.37 -1 -1 82700 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 433964 91 65 33165 28052 2 12600 1073 40 40 1600 dsp_top auto 244.3 MiB 14.50 127133 355.4 MiB 20.64 0.16 4.71204 -54567.2 -4.71204 1.91876 0.65 0.0660653 0.0576505 8.12915 6.95627 -1 197695 16 5.44678e+07 4.12216e+07 3.33594e+07 20849.6 6.51 11.6791 10.1644 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml conv_layer.v common 257.52 vpr 512.15 MiB -1 -1 14.06 148284 4 108.02 -1 -1 82780 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 524444 91 65 33165 28052 2 12600 1073 54 54 2916 dsp_top auto 244.3 MiB 14.39 165043 512.2 MiB 19.60 0.16 4.39914 -54861.3 -4.39914 1.84126 0.93 0.0635112 0.0550858 7.86487 6.68671 -1 235087 12 9.13586e+07 4.12216e+07 6.28961e+07 21569.3 6.53 10.879 9.43508 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml conv_layer.v common 214.78 vpr 435.76 MiB -1 -1 14.42 148560 4 104.84 -1 -1 82804 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 446216 91 65 33165 28052 2 12600 1073 43 43 1849 clb auto 244.4 MiB 14.65 132661 377.4 MiB 17.65 0.17 4.84337 -57232 -4.84337 1.95037 0.91 0.0658165 0.0552913 6.93384 5.85998 -1 204199 14 7.74951e+07 4.12216e+07 3.63440e+07 19656.1 6.58 10.3395 8.94833 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml conv_layer.v common 203.03 vpr 414.21 MiB -1 -1 14.15 148332 4 100.89 -1 -1 82752 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 424152 91 65 33165 28052 2 12600 1073 38 38 1444 dsp_top auto 244.3 MiB 14.63 131741 336.6 MiB 19.00 0.15 4.50414 -52753 -4.50414 1.86763 0.48 0.0615869 0.0512102 7.35096 6.22334 -1 201138 16 4.99286e+07 4.12216e+07 2.98368e+07 20662.6 6.51 10.7131 9.26785 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml conv_layer.v common 229.69 vpr 457.61 MiB -1 -1 14.36 148192 4 105.38 -1 -1 82732 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 468592 91 65 33165 28052 2 12600 1073 46 46 2116 dsp_top auto 244.2 MiB 14.35 163742 418.6 MiB 23.01 0.17 4.50414 -52223.7 -4.50414 1.86763 0.62 0.0692745 0.060974 9.21163 7.80464 -1 237659 14 6.74812e+07 4.12216e+07 4.51462e+07 21335.7 7.66 12.7137 10.978 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml conv_layer.v common 223.46 vpr 434.53 MiB -1 -1 14.27 147984 4 110.55 -1 -1 82748 -1 -1 819 91 56 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 444960 91 65 33165 28052 2 12600 1073 43 43 1849 clb auto 244.4 MiB 14.55 140324 375.6 MiB 19.88 0.18 4.39914 -53821.5 -4.39914 1.89924 0.92 0.0777626 0.0643673 8.28879 7.01624 -1 212267 13 7.79261e+07 4.12216e+07 3.65205e+07 19751.5 6.55 11.6902 10.082 -1 -1 -1 -1 -1 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vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 209.39 vpr 631.56 MiB -1 -1 21.81 147220 4 105.31 -1 -1 78736 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 646716 91 65 33168 28055 2 12932 1078 56 56 3136 dsp_top auto 201.1 MiB 14.31 161575 559103 183940 351790 23373 631.6 MiB 18.59 0.17 5.33784 -59139.7 -5.33784 2.07067 0.02 0.0802153 0.0702089 8.81529 7.5847 -1 -1 -1 -1 -1 237007 12 9.76016e+07 4.13612e+07 6.76749e+07 21580.0 5.30 11.9957 10.4294 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml conv_layer.v common 210.23 vpr 434.48 MiB -1 -1 21.00 147272 4 120.27 -1 -1 78800 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 444908 91 65 33168 28055 2 12932 1078 43 43 1849 clb auto 201.3 MiB 13.95 131693 498328 148173 256931 93224 422.0 MiB 17.93 0.15 5.12994 -60661.1 -5.12994 2.02943 0.01 0.081656 0.0717278 8.66324 7.42728 -1 -1 -1 -1 -1 203979 14 7.83573e+07 4.13612e+07 3.63938e+07 19683.0 5.78 12.5079 10.8632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml conv_layer.v common 200.01 vpr 438.69 MiB -1 -1 19.66 147244 4 108.43 -1 -1 78680 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 449220 91 65 33168 28055 2 12932 1078 43 43 1849 clb auto 201.7 MiB 13.91 130722 492803 145153 258559 89091 425.8 MiB 19.17 0.16 5.22466 -59384.8 -5.22466 2.0229 0.01 0.0853547 0.0727941 7.86128 6.69514 -1 -1 -1 -1 -1 202633 12 7.68484e+07 4.13612e+07 3.62938e+07 19628.9 5.23 11.2863 9.7608 -1 -1 -1 -1 -1 -1 -1 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 434900 91 65 33168 28055 2 12932 1078 40 40 1600 dsp_top auto 200.7 MiB 14.04 127736 509378 152596 327280 29502 400.8 MiB 23.84 0.25 5.06525 -61364.6 -5.06525 2.00263 0.01 0.0876528 0.0722766 9.94011 8.43019 -1 -1 -1 -1 -1 198670 13 5.44678e+07 4.13612e+07 3.32516e+07 20782.2 6.69 13.8135 11.9182 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml conv_layer.v common 226.86 vpr 600.96 MiB -1 -1 22.15 147472 4 111.28 -1 -1 78832 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 615380 91 65 33168 28055 2 12932 1078 54 54 2916 dsp_top auto 200.8 MiB 15.79 163528 553578 180391 355481 17706 601.0 MiB 26.41 0.25 5.02494 -57585.7 -5.02494 1.99324 0.02 0.0961703 0.084176 9.91747 8.40538 -1 -1 -1 -1 -1 234187 13 9.13586e+07 4.13612e+07 6.26714e+07 21492.2 7.55 14.5116 12.5104 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml conv_layer.v common 210.02 vpr 436.44 MiB -1 -1 22.14 147456 4 115.07 -1 -1 78656 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 446912 91 65 33168 28055 2 12932 1078 43 43 1849 clb auto 201.0 MiB 14.38 128673 525953 163254 311082 51617 423.9 MiB 21.60 0.23 4.91861 -57626.8 -4.91861 2.05887 0.01 0.0905403 0.0740438 8.94751 7.68095 -1 -1 -1 -1 -1 198326 14 7.74951e+07 4.13612e+07 3.62324e+07 19595.7 6.79 13.2038 11.4954 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 502744 91 65 33168 28055 2 12932 1078 46 46 2116 dsp_top auto 201.2 MiB 17.81 162148 564628 179853 365105 19670 491.0 MiB 29.12 0.24 4.74738 -55411.9 -4.74738 1.94955 0.02 0.082836 0.0734304 10.6462 8.98053 -1 -1 -1 -1 -1 236584 13 6.74812e+07 4.13612e+07 4.49964e+07 21264.8 7.17 14.3438 12.3068 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml conv_layer.v common 211.57 vpr 436.31 MiB -1 -1 21.32 147164 4 112.58 -1 -1 78640 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 446784 91 65 33168 28055 2 12932 1078 43 43 1849 clb auto 201.3 MiB 13.94 139418 531478 168663 322209 40606 423.4 MiB 23.75 0.20 4.8408 -58901.8 -4.8408 2.09368 0.02 0.0868457 0.0736702 9.1076 7.7586 -1 -1 -1 -1 -1 212208 14 7.79261e+07 4.13612e+07 3.64091e+07 19691.3 7.18 13.2356 11.4653 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml conv_layer.v common 225.91 vpr 469.19 MiB -1 -1 21.45 147472 4 119.88 -1 -1 78956 -1 -1 824 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 480448 91 65 33168 28055 2 12932 1078 46 46 2116 dsp_top auto 201.3 MiB 15.84 142797 525953 163424 346380 16149 469.2 MiB 24.56 0.24 4.81704 -59254.1 -4.81704 2.0052 0.02 0.0994928 0.0874458 9.51869 8.05165 -1 -1 -1 -1 -1 215462 14 7.46848e+07 4.13612e+07 4.40267e+07 20806.6 7.57 14.1277 12.1525 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt index 3415ce7747b..75076555a7a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt @@ -1,13 +1,13 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 1163.23 vpr 2.73 GiB -1 -1 54.60 238712 5 135.74 -1 -1 136304 -1 -1 1086 355 32 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2859304 355 289 47773 39460 2 23092 2027 136 136 18496 dsp_top auto 259.8 MiB 421.52 425875 2028061 758608 1141225 128228 2792.3 MiB 37.94 0.25 7.49309 -111546 -7.49309 2.64155 0.10 0.0843162 0.070416 13.7807 11.5012 -1 535248 15 5.92627e+08 1.01961e+08 4.08527e+08 22087.3 8.61 17.6417 14.9058 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 1027.32 vpr 2.77 GiB -1 -1 46.58 296972 5 239.34 -1 -1 136156 -1 -1 1474 357 58 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2904916 357 289 56200 49059 2 22147 2444 136 136 18496 dsp_top auto 320.6 MiB 116.79 449929 2454388 935803 1390028 128557 2836.8 MiB 54.75 0.34 8.9901 -151330 -8.9901 2.89342 0.11 0.11259 0.0932 17.975 14.9021 -1 579981 15 5.92627e+08 1.1662e+08 4.08527e+08 22087.3 11.65 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v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2104736 260 122 206293 154384 1 87490 6637 87 87 7569 clb auto 1055.9 MiB 203.84 911610 7737417 3028323 4214852 494242 1900.2 MiB 254.43 1.57 7.9787 -159676 -7.9787 7.9787 0.07 0.317118 0.27396 46.0589 38.1983 -1 1218227 15 2.37162e+08 1.8877e+08 1.65965e+08 21927.0 29.18 62.4246 52.4257 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1284.17 vpr 3.19 GiB -1 -1 55.27 306820 5 18.14 -1 -1 131152 -1 -1 1004 1052 690 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 3343432 1052 32 45960 36468 1 23568 2876 148 148 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9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 547812 151 97 23552 20376 2 11485 992 50 50 2500 memory auto 167.0 MiB 95.85 132973 525162 172354 326675 26133 535.0 MiB 14.60 0.15 4.78754 -25459.2 -4.78754 2.11147 0.01 0.0614346 0.0518776 6.9681 5.89089 -1 202188 14 7.5303e+07 3.00192e+07 5.42358e+07 21694.3 5.07 9.64823 8.26979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 145.43 vpr 556.78 MiB -1 -1 24.72 234660 5 7.94 -1 -1 73196 -1 -1 873 3 84 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 570144 3 384 24672 23040 1 12367 1362 52 52 2704 memory auto 180.3 MiB 16.79 107156 771054 245311 455922 69821 556.8 MiB 19.27 0.16 6.07065 -42231.5 -6.07065 6.07065 0.02 0.056264 0.0478382 6.36102 5.35137 -1 174187 17 8.30642e+07 4.04924e+07 5.85728e+07 21661.5 5.28 9.30432 7.95656 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 107.13 vpr 351.39 MiB -1 -1 24.54 301764 6 7.81 -1 -1 70444 -1 -1 685 37 52 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 359824 37 17 16480 14235 1 8948 791 38 38 1444 memory auto 137.2 MiB 16.34 99313 271335 68101 193947 9287 351.4 MiB 10.82 0.13 6.55728 -42171.5 -6.55728 6.55728 0.01 0.0475515 0.041839 4.04663 3.44216 -1 162861 15 4.31434e+07 2.62733e+07 3.09543e+07 21436.5 5.13 6.43177 5.54111 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 241.53 vpr 1.09 GiB -1 -1 15.16 184108 6 12.35 -1 -1 64108 -1 -1 644 82 232 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1144196 82 17 16166 14262 1 8933 1007 84 84 7056 memory auto 130.1 MiB 17.36 163629 520642 168550 336267 15825 1117.4 MiB 10.40 0.09 6.14502 -42576.1 -6.14502 6.14502 0.04 0.0428761 0.0372263 4.90675 4.12616 -1 220423 14 2.2198e+08 5.80301e+07 1.54484e+08 21894.0 3.82 6.86146 5.84708 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 459.25 parmys 476.39 MiB -1 -1 62.80 487828 10 78.33 -1 -1 98584 -1 -1 1387 402 0 -1 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 481464 402 150 35614 32642 1 17791 1947 43 43 1849 clb auto 243.7 MiB 211.58 124459 1192843 403919 739552 49372 469.4 MiB 33.95 0.29 10.2966 -28481.7 -10.2966 10.2966 0.01 0.0767148 0.0684923 8.56138 7.35741 -1 202624 16 5.60835e+07 4.07336e+07 3.97519e+07 21499.1 6.47 12.7366 11.0245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height 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success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 482536 402 150 35614 32642 1 17785 1947 43 43 1849 clb auto 242.3 MiB 257.80 130074 1217147 415758 751584 49805 467.6 MiB 32.25 0.31 10.827 -28928.1 -10.827 10.827 0.01 0.0811184 0.0723576 8.76544 7.51492 -1 -1 -1 -1 -1 210517 16 5.60835e+07 4.07336e+07 3.96192e+07 21427.4 6.82 13.2832 11.4498 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt index 9b489cb8f38..ad3d51601b9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt @@ -1,15 +1,15 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength 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100 36 285842 271283 4 258743 11467 180 133 23940 M20K auto 2537.0 MiB 635.05 3438864 16426344 6351589 9654498 420257 4682.3 MiB 836.17 5.64 5.57216 -640841 -4.57216 4.33502 0.15 1.33213 1.04738 180.166 143.354 4193740 16.2086 887855 3.43152 848838 1626270 3464380030 716819176 0 0 4.25346e+08 17767.2 41 7099044 74943478 -1 5.713 4.31521 -1.12447e+06 -4.713 0 0 166.62 -1 -1 5231.1 MiB 957.21 290.023 234.525 4682.3 MiB -1 620.98 -stratix10_arch.timing.xml mes_noc_stratix10_arch_timing.blif common 7039.56 vpr 9.03 GiB 5 26001 0 64 736 8 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 9466652 3 2 594103 567321 9 550449 26814 206 153 31518 LAB auto 4791.3 MiB 1557.81 4892389 47362160 17896376 28168353 1297431 7205.1 MiB 3476.21 33.65 9.295 -2.17146e+06 -8.295 7.77804 0.25 2.24529 1.76453 287.641 225.909 5339983 9.70812 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neuron_stratix10_arch_timing.blif common 833.04 vpr 2.00 GiB 133 5234 0 243 108 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2093464 40 93 140673 125393 2 123625 5719 94 70 6580 LAB auto 1201.5 MiB 289.44 634340 6191360 2301274 3623602 266484 1729.3 MiB 370.55 2.45 5.84744 -64925.2 -4.84744 3.3402 0.04 0.387587 0.340417 48.3195 39.815 517953 4.19141 138793 1.12315 268394 383043 84540966 19817319 0 0 1.15552e+08 17561.0 18 1898072 20093317 -1 5.799 3.20378 -122888 -4.799 0 0 43.46 -1 -1 1880.4 MiB 41.18 67.4246 56.3964 1729.3 MiB -1 33.19 + stratix10_arch.timing.xml sparcT1_core_stratix10_arch_timing.blif common 1320.68 vpr 3.03 GiB 309 4982 0 6 154 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3176516 172 137 98039 97359 1 91845 5451 163 121 19723 io_cell auto 1048.7 MiB 416.44 1174053 5471979 2094519 3176216 201244 3102.1 MiB 483.40 4.56 7.15 -378395 -6.15 7.15 0.24 0.484867 0.374331 56.8899 45.3278 1526584 16.6220 347043 3.77874 324019 943132 297819952 53503048 0 0 3.51754e+08 17834.7 17 5914532 61913217 -1 6.938 6.938 -458652 -5.938 0 0 133.69 -1 -1 3102.1 MiB 111.14 80.1902 65.1665 3102.1 MiB -1 117.12 + stratix10_arch.timing.xml stereo_vision_stratix10_arch_timing.blif common 1336.40 vpr 7.73 GiB 506 5363 0 76 83 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 8102372 172 334 150507 118033 3 110735 6028 287 213 61131 io_cell auto 1114.7 MiB 159.83 546089 6696142 2566220 3885626 244296 7912.5 MiB 322.65 2.23 7.71363 -39076.7 -6.71363 7.71363 0.65 0.328993 0.270482 46.9904 37.5447 427507 3.86091 120235 1.08587 235293 320005 60687000 12277011 0 0 1.10789e+09 18123.3 15 18464012 193849399 -1 6.984 6.984 -51229.8 -5.984 0 0 404.36 -1 -1 7912.5 MiB 33.81 63.8841 51.9403 7912.5 MiB -1 343.62 + stratix10_arch.timing.xml cholesky_mc_stratix10_arch_timing.blif common 998.97 vpr 2.81 GiB 262 4835 115 131 382 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2944676 111 151 145547 131782 1 127404 5725 147 109 16023 io_cell auto 1301.4 MiB 282.50 801498 5790534 2145233 3342854 302447 2875.7 MiB 400.69 3.54 5.008 -92090.6 -4.008 4.559 0.09 0.537432 0.455738 62.8576 51.5026 805259 6.32071 212196 1.66559 300273 509257 150845866 34700709 0 0 2.85989e+08 17848.6 13 4788948 50134206 -1 4.488 4.083 -213947 -3.488 0 0 101.11 -1 -1 2875.7 MiB 61.86 84.7937 70.3971 2875.7 MiB -1 81.78 + stratix10_arch.timing.xml LU_Network_stratix10_arch_timing.blif common 8279.37 vpr 17.68 GiB 748 30526 826 224 1026 1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 18535564 325 423 817452 760174 3 681111 33351 406 301 122206 io_cell auto 5546.8 MiB 1827.39 4732164 74080701 31510919 39435236 3134546 18101.1 MiB 4227.97 28.65 4.76071 -319191 -3.76071 4.69287 0.96 2.78373 2.33996 398.847 330.305 4439564 6.52395 1123896 1.65157 1562719 2598341 607571135 128284629 0 0 2.23450e+09 18284.7 12 36989044 388958102 -1 4.7 4.64063 -440709 -3.7 0 0 899.60 -1 -1 18101.1 MiB 247.43 493.191 412.334 18101.1 MiB -1 737.58 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt index 5301c84b184..5351d6583d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt @@ -1,13 +1,13 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 1005.52 vpr 2.71 GiB 226.57 236200 -1 -1 5 152.30 -1 -1 116652 -1 -1 536 355 32 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2837056 355 289 26113 19088 2 12674 1488 136 136 18496 dsp_top auto 269.1 MiB 18.30 370957 1207210 471810 528572 206828 2770.6 MiB 52.32 0.57 5.98706 -87526.7 -5.98706 2.21181 0.11 0.161567 0.147397 23.7018 21.6403 -1 407074 13 5.92627e+08 8.94049e+07 4.08527e+08 22087.3 8.08 29.7625 27.3592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 1195.09 vpr 2.73 GiB 342.13 302328 -1 -1 7 164.42 -1 -1 127540 -1 -1 1029 357 58 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2861412 357 289 30369 24839 2 17327 2011 136 136 18496 dsp_top auto 260.2 MiB 65.60 221282 1943275 763450 845285 334540 2794.3 MiB 60.29 0.43 9.44576 -79017.3 -9.44576 2.96583 0.11 0.145986 0.128353 23.0491 20.2846 -1 291408 15 5.92627e+08 1.07248e+08 4.08527e+08 22087.3 9.05 29.0776 25.7841 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 3054.95 vpr 2.07 GiB 22.84 653108 -1 -1 5 1540.96 -1 -1 567504 -1 -1 4756 206 132 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2172736 206 13 208395 166387 1 84813 5235 90 90 8100 dsp_top auto 1096.5 MiB 1034.75 662081 5321247 1974867 3264938 81442 2013.0 MiB 170.41 1.37 4.84922 -185838 -4.84922 4.84922 0.06 0.316161 0.272947 41.3931 34.2165 -1 964636 16 2.56465e+08 1.83367e+08 1.77260e+08 21883.9 25.11 57.5569 48.2341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 1083.89 vpr 2.10 GiB 27.69 498048 -1 -1 3 134.73 -1 -1 495220 -1 -1 5693 260 0 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2205660 260 122 231647 179602 1 86860 6138 83 83 6889 clb auto 1178.5 MiB 302.54 908164 6522438 2525997 3694260 302181 1905.2 MiB 256.57 1.79 7.71077 -154889 -7.71077 7.71077 0.06 0.394039 0.34347 50.9118 42.0537 -1 1204095 18 2.13666e+08 1.74846e+08 1.51189e+08 21946.4 35.45 71.703 59.874 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1348.58 vpr 3.25 GiB 8.87 584856 -1 -1 7 33.82 -1 -1 285544 -1 -1 1929 1057 690 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 3411020 1057 32 57517 46908 1 31258 3845 148 148 21904 memory auto 354.4 MiB 506.08 410126 4971995 2186012 2431068 354915 3331.1 MiB 93.36 0.54 8.74294 -119537 -8.74294 8.74294 0.13 0.137611 0.121189 24.2699 20.8366 -1 593896 15 7.00618e+08 1.83584e+08 4.83549e+08 22075.8 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v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 672488 91 65 36754 30551 2 13677 1194 56 56 3136 dsp_top auto 229.0 MiB 17.73 168550 665949 228412 410610 26927 656.7 MiB 17.90 0.16 4.73837 -61660.6 -4.73837 2.04692 0.02 0.0838265 0.0708925 9.27571 7.93974 -1 242849 14 9.76016e+07 4.45981e+07 6.79229e+07 21659.1 5.79 12.8334 11.1116 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 139.99 vpr 570.45 MiB 2.30 82748 -1 -1 4 42.87 -1 -1 68740 -1 -1 358 152 72 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 584136 152 97 14052 11986 2 6814 729 56 56 3136 dsp_top auto 118.8 MiB 6.82 128735 345024 117764 203974 23286 570.4 MiB 9.34 0.09 4.47241 -24858.2 -4.47241 1.84076 0.02 0.0495891 0.042571 5.39741 4.63942 -1 191960 19 9.76016e+07 3.25907e+07 6.79229e+07 21659.1 4.98 7.73343 6.71312 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 279.44 vpr 594.62 MiB 101.07 368044 -1 -1 6 34.48 -1 -1 150452 -1 -1 1279 3 96 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 608892 3 384 30303 28383 1 14742 1780 52 52 2704 memory auto 226.7 MiB 25.40 135654 1133995 376682 677395 79918 594.6 MiB 24.95 0.23 6.41197 -44163.1 -6.41197 6.41197 0.01 0.0699692 0.0608779 8.037 6.84238 -1 223038 16 8.30642e+07 5.34735e+07 5.85728e+07 21661.5 6.19 11.6692 10.061 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 110.67 vpr 362.37 MiB 1.69 80180 -1 -1 6 24.58 -1 -1 68036 -1 -1 804 37 52 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 371068 37 17 18215 15970 1 9561 910 38 38 1444 memory auto 151.6 MiB 16.24 109644 344734 93069 242280 9385 362.4 MiB 16.22 0.17 6.86392 -40596.4 -6.86392 6.86392 0.01 0.0544984 0.0479428 5.76733 4.90569 -1 179767 16 4.31434e+07 2.95939e+07 3.09543e+07 21436.5 6.19 8.49981 7.32043 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 295.41 vpr 1.10 GiB 23.59 694880 -1 -1 6 23.24 -1 -1 253836 -1 -1 506 82 232 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1150664 82 17 16284 14380 1 8446 869 84 84 7056 memory auto 137.0 MiB 16.59 155490 423659 134240 273173 16246 1123.7 MiB 10.22 0.09 6.1436 -40944.1 -6.1436 6.1436 0.04 0.0467929 0.0405177 5.46221 4.52238 -1 210725 14 2.2198e+08 5.41794e+07 1.54484e+08 21894.0 4.14 7.55015 6.35415 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 131.32 vpr 595.07 MiB 1.96 102800 -1 -1 10 9.50 -1 -1 52060 -1 -1 513 402 0 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 609352 402 150 13003 11825 1 7723 1118 58 58 3364 dsp_top auto 113.2 MiB 12.34 74102 778318 278328 454520 45470 595.1 MiB 12.61 0.10 9.53955 -14550.9 -9.53955 9.53955 0.02 0.0332241 0.0286889 4.82541 4.17824 -1 122561 16 1.04637e+08 2.77652e+07 7.29687e+07 21691.1 3.40 6.5043 5.68128 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est 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7.42118 -1 -1 -1 -1 -1 224233 20 8.30642e+07 5.35851e+07 5.83674e+07 21585.6 7.14 13.233 11.3173 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 78.85 vpr 361.96 MiB 1.67 80272 -1 -1 6 20.55 -1 -1 68072 -1 -1 804 37 52 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 370644 37 17 18215 15970 1 9561 910 38 38 1444 memory auto 151.2 MiB 14.13 110676 331510 86677 232626 12207 362.0 MiB 12.77 0.15 6.68572 -41665.7 -6.68572 6.68572 0.01 0.046345 0.0403322 4.00773 3.36654 -1 -1 -1 -1 -1 185110 15 4.31434e+07 2.95939e+07 3.08517e+07 21365.5 4.82 6.23238 5.33371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 169.07 vpr 1.09 GiB 22.30 694892 -1 -1 6 22.40 -1 -1 253836 -1 -1 506 82 232 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1143196 82 17 16284 14380 1 8446 869 84 84 7056 memory auto 136.0 MiB 16.96 154702 407079 126171 268174 12734 1116.4 MiB 9.30 0.09 5.66212 -41728 -5.66212 5.66212 0.04 0.0408504 0.0349241 4.46319 3.68799 -1 -1 -1 -1 -1 213813 13 2.2198e+08 5.41794e+07 1.54074e+08 21835.9 3.29 6.26987 5.27694 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 85.45 vpr 591.82 MiB 3.32 102836 -1 -1 10 10.53 -1 -1 51956 -1 -1 513 402 0 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 606028 402 150 13003 11825 1 7723 1118 58 58 3364 dsp_top auto 112.2 MiB 12.65 78213 784118 280792 458671 44655 591.8 MiB 13.64 0.10 9.87074 -14553.8 -9.87074 9.87074 0.02 0.0323667 0.0289675 4.75222 4.19081 -1 -1 -1 -1 -1 125779 16 1.04637e+08 2.77652e+07 7.26973e+07 21610.4 3.19 6.43415 5.71727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt index 6dfb7ea9826..fbc506a606b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt @@ -1,12 +1,12 @@ - arch circuit script_params vtr_flow_elapsed_time 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91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 537920 91 65 41142 34939 2 16599 1337 48 48 2304 clb auto 305.0 MiB 38.98 163179 471.4 MiB 18.53 0.16 4.81221 -66909.8 -4.81221 2.86497 1.13 0.0776173 0.0661688 8.38542 7.23676 -1 247004 14 9.6957e+07 4.85884e+07 4.55250e+07 19759.1 5.95 11.8313 10.3727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml conv_layer.v common 539.93 vpr 491.85 MiB 9.97 221724 -1 -1 4 349.08 -1 -1 115896 -1 -1 1083 91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 503652 91 65 41142 34939 2 16599 1337 41 41 1681 clb auto 305.3 MiB 45.84 158804 405.7 MiB 26.80 0.17 4.53047 -58733.1 -4.53047 2.63958 0.42 0.0800797 0.0678513 11.0399 9.54718 -1 241163 14 5.66164e+07 4.85884e+07 3.51492e+07 20909.7 8.36 15.3368 13.416 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml conv_layer.v common 552.23 vpr 520.43 MiB 10.18 221740 -1 -1 4 358.01 -1 -1 115896 -1 -1 1083 91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 532916 91 65 41142 34939 2 16599 1337 46 46 2116 dsp_top auto 305.1 MiB 34.17 184689 460.1 MiB 29.94 0.17 4.63337 -57913.5 -4.63337 2.41469 0.50 0.07569 0.067726 12.3739 10.6816 -1 272497 15 6.74812e+07 4.85884e+07 4.51462e+07 21335.7 8.61 17.2022 14.9931 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml conv_layer.v common 550.75 vpr 519.12 MiB 10.54 221572 -1 -1 4 348.65 -1 -1 115800 -1 -1 1083 91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 531584 91 65 41142 34939 2 16599 1337 47 47 2209 clb auto 304.8 MiB 48.64 178357 460.2 MiB 24.25 0.18 4.84337 -59160.5 -4.84337 2.55397 0.93 0.079042 0.066954 10.2961 8.81958 -1 265197 21 9.21907e+07 4.85884e+07 4.39475e+07 19894.7 9.90 16.6973 14.4877 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml conv_layer.v common 622.19 vpr 516.96 MiB 8.22 221740 -1 -1 4 461.76 -1 -1 115856 -1 -1 1083 91 56 -1 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 529372 91 65 41142 34939 2 16599 1337 46 46 2116 dsp_top auto 305.1 MiB 37.01 172015 455.7 MiB 21.46 0.17 4.49931 -59023.2 -4.49931 2.85425 0.66 0.0776131 0.0663591 9.31061 8.05832 -1 256997 15 7.46848e+07 4.85884e+07 4.41698e+07 20874.2 6.79 12.9038 11.3254 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 352.51 vpr 672.43 MiB 4.76 215088 -1 -1 4 212.03 -1 -1 115768 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 688568 91 65 41142 34939 2 16392 1336 56 56 3136 dsp_top auto 252.0 MiB 41.39 185989 788321 264351 491679 32291 672.4 MiB 23.41 0.24 5.1805 -69731.6 -5.1805 2.99286 0.03 0.106537 0.0943177 10.5152 8.9603 -1 -1 -1 -1 -1 272192 13 9.76016e+07 4.85605e+07 6.76749e+07 21580.0 6.74 14.526 12.573 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml conv_layer.v common 366.41 vpr 548.82 MiB 7.70 215196 -1 -1 4 234.35 -1 -1 115928 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 561996 91 65 41142 34939 2 16392 1336 49 49 2401 clb auto 252.1 MiB 42.27 171761 714771 223295 366878 124598 548.8 MiB 19.99 0.17 5.36417 -65640.6 -5.36417 2.69709 0.01 0.0879771 0.0748201 9.14144 7.79307 -1 -1 -1 -1 -1 257693 13 1.02711e+08 4.85605e+07 4.74635e+07 19768.2 5.56 12.7444 11.0222 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + 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-1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml conv_layer.v common 388.30 vpr 525.20 MiB 7.03 215020 -1 -1 4 244.58 -1 -1 115972 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 537808 91 65 41142 34939 2 16392 1336 48 48 2304 clb auto 251.2 MiB 41.38 168856 729481 233033 429510 66938 522.9 MiB 26.06 0.23 5.57207 -68353.3 -5.57207 2.79807 0.01 0.0981234 0.0838068 10.5056 8.98586 -1 -1 -1 -1 -1 251682 13 9.6957e+07 4.85605e+07 4.53839e+07 19697.9 6.45 14.4956 12.5587 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml conv_layer.v common 396.82 vpr 493.34 MiB 7.41 215104 -1 -1 4 257.13 -1 -1 115940 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 505180 91 65 41142 34939 2 16392 1336 41 41 1681 clb auto 251.2 MiB 42.40 159936 729481 233674 452058 43749 454.7 MiB 25.78 0.22 5.12784 -65245 -5.12784 2.64326 0.01 0.0973349 0.0824972 10.3536 8.83427 -1 -1 -1 -1 -1 244692 15 5.66164e+07 4.85605e+07 3.50349e+07 20841.7 6.84 14.6337 12.6436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml conv_layer.v common 373.28 vpr 531.82 MiB 7.65 215144 -1 -1 4 227.23 -1 -1 115832 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 544584 91 65 41142 34939 2 16392 1336 46 46 2116 dsp_top auto 251.8 MiB 42.06 179779 788321 265913 498199 24209 531.8 MiB 27.49 0.24 4.91721 -63756.1 -4.91721 2.8055 0.01 0.0985794 0.0827707 11.0738 9.46404 -1 -1 -1 -1 -1 266992 15 6.74812e+07 4.85605e+07 4.49964e+07 21264.8 7.05 15.3643 13.283 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml conv_layer.v common 363.98 vpr 519.44 MiB 7.51 215156 -1 -1 4 221.45 -1 -1 115824 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 531904 91 65 41142 34939 2 16392 1336 47 47 2209 clb auto 251.7 MiB 42.06 177363 751546 238898 455950 56698 511.2 MiB 26.88 0.25 5.74439 -66669.2 -5.74439 2.74926 0.01 0.0976305 0.0834431 10.6585 9.11403 -1 -1 -1 -1 -1 261596 14 9.21907e+07 4.85605e+07 4.38118e+07 19833.3 6.58 14.768 12.7775 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml conv_layer.v common 367.47 vpr 517.34 MiB 7.31 215140 -1 -1 4 226.59 -1 -1 115900 -1 -1 1082 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 529760 91 65 41142 34939 2 16392 1336 46 46 2116 dsp_top auto 251.9 MiB 42.40 164706 758901 240199 496773 21929 509.8 MiB 24.50 0.23 5.0259 -67286.9 -5.0259 3.01666 0.01 0.0942614 0.0802815 10.2047 8.7176 -1 -1 -1 -1 -1 250051 15 7.46848e+07 4.85605e+07 4.40267e+07 20806.6 6.53 14.2812 12.3585 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt index 11c2ef07254..8578fd23aeb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt @@ -1,13 +1,13 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 1104.28 vpr 2.74 GiB 8.74 244108 -1 -1 5 297.77 -1 -1 157688 -1 -1 1178 355 32 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2878052 355 289 49464 41111 2 23907 2130 136 136 18496 dsp_top auto 281.5 MiB 311.65 435995 1714505 687626 949597 77282 2810.6 MiB 27.83 0.21 7.35242 -116388 -7.35242 2.95155 0.10 0.0834697 0.0680869 11.0641 9.1222 -1 549370 16 5.92627e+08 1.0732e+08 4.08527e+08 22087.3 8.77 15.1062 12.6676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 946.59 vpr 2.73 GiB 45.54 310812 -1 -1 6 239.52 -1 -1 130016 -1 -1 1360 357 58 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2858436 357 289 42535 35250 2 20674 2341 136 136 18496 dsp_top auto 263.7 MiB 81.22 258365 2503798 912690 1363844 227264 2791.4 MiB 39.95 0.25 9.41317 -93875.2 -9.41317 3.62083 0.11 0.0885806 0.077004 15.1656 12.8314 -1 352592 15 5.92627e+08 1.16231e+08 4.08527e+08 22087.3 7.12 19.1834 16.3728 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 3217.39 vpr 2.18 GiB 28.60 695084 -1 -1 5 1560.40 -1 -1 610904 -1 -1 5655 206 120 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2282904 206 13 227613 180877 1 96129 6122 90 90 8100 dsp_top auto 1187.9 MiB 1109.94 702117 7283522 2749583 4223771 310168 2056.0 MiB 220.80 1.60 8.302 -169079 -8.302 8.302 0.06 0.341171 0.278004 46.9752 39.1979 -1 1004001 20 2.56465e+08 2.06801e+08 1.77260e+08 21883.9 28.39 66.1255 55.7608 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 1047.76 vpr 2.10 GiB 28.88 498080 -1 -1 3 140.62 -1 -1 495040 -1 -1 5693 260 0 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2205640 260 122 231647 179602 1 86860 6138 83 83 6889 clb auto 1178.3 MiB 300.36 908164 6522438 2525997 3694260 302181 1905.0 MiB 230.15 1.64 7.71077 -154889 -7.71077 7.71077 0.06 0.377722 0.328092 49.8268 40.9656 -1 1204095 18 2.13666e+08 1.74846e+08 1.51189e+08 21946.4 34.10 69.5248 57.8328 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1979.21 vpr 5.52 GiB 9.31 622444 -1 -1 8 52.62 -1 -1 296696 -1 -1 2585 1048 1166 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5787156 1048 32 64005 53342 1 37416 4967 196 196 38416 memory auto 399.5 MiB 726.19 576620 7121615 3271863 3293671 556081 5651.5 MiB 80.75 0.52 9.33408 -152227 -9.33408 9.33408 0.41 0.140445 0.113396 24.2142 20.0817 -1 762815 13 1.23531e+09 2.67163e+08 8.45266e+08 22003.0 13.94 29.7133 24.9109 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 843.36 odin 3.93 GiB 126.10 4122888 -1 -1 7 45.84 -1 -1 1641428 -1 -1 1890 1016 21 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1776404 1016 2283 16425 17373 1 9249 5212 106 106 11236 io auto 146.6 MiB 83.53 74673 6193502 3147425 2242332 803745 1734.8 MiB 37.16 0.36 13.5303 -24849.4 -13.5303 13.5303 0.06 0.122239 0.118475 17.0221 16.3404 -1 107886 17 3.5748e+08 5.61376e+07 2.46822e+08 21967.1 6.15 22.279 21.3779 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 613.28 vpr 997.71 MiB 7.57 229260 -1 -1 4 300.66 -1 -1 135308 -1 -1 1377 91 56 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1021656 91 65 51897 44206 2 22450 1673 72 72 5184 dsp_top auto 308.4 MiB 72.85 233523 1103570 376406 686486 40678 997.7 MiB 37.99 0.31 5.75091 -95999.9 -5.75091 3.49463 0.03 0.116483 0.0978631 13.6034 11.5102 -1 328320 15 1.63139e+08 6.74509e+07 1.13044e+08 21806.4 8.55 18.6242 15.9639 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 719.12 vpr 606.31 MiB 19.99 354312 -1 -1 5 168.14 -1 -1 123840 -1 -1 1413 152 72 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 620864 152 97 41796 36054 2 19766 1740 50 50 2500 memory auto 279.1 MiB 388.21 177823 1413975 463973 858189 91813 606.3 MiB 37.09 0.26 5.657 -34829.9 -5.657 3.0521 0.01 0.0907473 0.0792665 13.8393 11.6985 -1 266013 16 7.5303e+07 5.08635e+07 5.42358e+07 21694.3 7.83 18.3398 15.6629 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 567.27 vpr 607.77 MiB 175.53 368912 -1 -1 6 52.01 -1 -1 159520 -1 -1 1317 3 96 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 622360 3 384 32137 30217 1 16402 1818 52 52 2704 memory auto 242.0 MiB 212.45 148363 1144191 372510 692675 79006 607.8 MiB 27.66 0.25 6.51487 -55563.8 -6.51487 6.51487 0.01 0.0761583 0.0664108 8.73148 7.46125 -1 239481 19 8.30642e+07 5.45339e+07 5.85728e+07 21661.5 7.63 13.2929 11.446 -1 -1 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1130640 61 17 22163 20259 1 12984 1103 82 82 6724 memory auto 171.1 MiB 342.05 164941 770063 247069 479249 43745 1104.1 MiB 14.47 0.10 5.93366 -38288.7 -5.93366 5.93366 0.04 0.0461013 0.039822 6.95092 5.71641 -1 219396 14 2.09174e+08 5.75629e+07 1.47429e+08 21925.8 4.08 9.24081 7.71683 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 420.46 vpr 507.89 MiB 9.71 331692 -1 -1 10 97.61 -1 -1 108204 -1 -1 1452 402 0 -1 success v8.0.0-11333-g2a1703ace-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-19T16:40:57 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 520080 402 150 39533 35581 1 18244 2012 44 44 1936 clb auto 266.4 MiB 221.27 128967 1271612 435167 794322 42123 501.0 MiB 25.69 0.24 9.7645 -28088.4 -9.7645 9.7645 0.01 0.0759782 0.0621098 8.12017 6.77196 -1 211193 15 5.86452e+07 4.25474e+07 4.16874e+07 21532.7 5.88 11.9476 10.1852 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 824.78 vpr 2.73 GiB 9.30 244232 -1 -1 5 260.22 -1 -1 157748 -1 -1 1192 355 32 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2859788 355 289 49464 41111 2 23764 2144 136 136 18496 dsp_top auto 279.7 MiB 295.81 418901 1701881 672511 951428 77942 2792.8 MiB 37.25 0.28 7.18019 -112184 -7.18019 3.27937 0.10 0.0928828 0.0762025 12.0598 9.97865 -1 -1 -1 -1 -1 532162 15 5.92627e+08 1.0771e+08 4.06343e+08 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0.22 0.14375 0.125397 26.449 22.1984 -1 -1 -1 -1 -1 761348 13 1.23531e+09 2.67861e+08 8.43084e+08 21946.2 12.71 32.4298 27.4366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 672.06 odin 3.93 GiB 129.42 4122772 -1 -1 7 42.43 -1 -1 1641328 -1 -1 1889 1016 21 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1764592 1016 2283 16425 17373 1 9246 5211 106 106 11236 io auto 145.9 MiB 84.88 74748 6237015 3200275 2226899 809841 1723.2 MiB 38.03 0.41 13.4488 -25176.8 -13.4488 13.4488 0.08 0.124806 0.120975 16.9313 16.2814 -1 -1 -1 -1 -1 105692 19 3.5748e+08 5.61097e+07 2.46019e+08 21895.6 6.63 22.7872 21.9276 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 509.40 vpr 994.21 MiB 7.63 229352 -1 -1 4 291.50 -1 -1 135308 -1 -1 1384 91 56 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1018076 91 65 51897 44206 2 22455 1680 72 72 5184 dsp_top auto 306.6 MiB 73.16 228853 1089827 378190 671197 40440 994.2 MiB 34.83 0.26 5.70153 -99928.4 -5.70153 3.13057 0.03 0.106655 0.0885957 12.4295 10.5046 -1 -1 -1 -1 -1 326314 16 1.63139e+08 6.76462e+07 1.12634e+08 21727.3 7.66 17.2977 14.7855 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 639.48 vpr 604.25 MiB 18.92 354340 -1 -1 5 163.25 -1 -1 123992 -1 -1 1341 152 72 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 618756 152 97 41796 36054 2 19741 1668 50 50 2500 memory auto 276.5 MiB 353.29 182641 1138788 375858 705982 56948 604.3 MiB 34.19 0.28 5.26502 -34149.4 -5.26502 3.08759 0.01 0.0964297 0.0809839 11.7416 9.89389 -1 -1 -1 -1 -1 272498 15 7.5303e+07 4.88544e+07 5.40494e+07 21619.8 6.94 15.9939 13.6389 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 546.92 vpr 605.04 MiB 154.33 369052 -1 -1 6 48.81 -1 -1 159492 -1 -1 1317 3 96 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 619556 3 384 32137 30217 1 16367 1818 52 52 2704 memory auto 242.8 MiB 239.93 144112 1133100 365554 689391 78155 605.0 MiB 35.61 0.31 6.41197 -56602.2 -6.41197 6.41197 0.02 0.0848867 0.0696734 9.19789 7.83126 -1 -1 -1 -1 -1 236714 16 8.30642e+07 5.45339e+07 5.83674e+07 21585.6 6.70 13.3346 11.5003 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 98.78 vpr 363.29 MiB 1.84 89352 -1 -1 6 26.10 -1 -1 76656 -1 -1 919 37 52 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 372012 37 17 22150 19905 1 11787 1025 38 38 1444 memory auto 170.0 MiB 16.96 135894 398807 104287 286810 7710 363.3 MiB 19.99 0.23 7.06559 -49254.7 -7.06559 7.06559 0.01 0.0623857 0.0549943 5.52111 4.6572 -1 -1 -1 -1 -1 207543 14 4.31434e+07 3.28029e+07 3.08517e+07 21365.5 5.40 8.56273 7.34463 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 494.03 vpr 1.07 GiB 22.80 719364 -1 -1 6 32.64 -1 -1 262680 -1 -1 803 61 198 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1124736 61 17 22163 20259 1 12877 1111 82 82 6724 memory auto 170.8 MiB 318.30 161978 720111 230341 449967 39803 1098.4 MiB 16.20 0.11 5.96789 -38891.9 -5.96789 5.96789 0.04 0.0460451 0.0397049 7.16927 6.05082 -1 -1 -1 -1 -1 215986 16 2.09174e+08 5.77861e+07 1.47019e+08 21864.8 4.01 9.6201 8.19901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 421.69 vpr 509.21 MiB 10.11 331792 -1 -1 10 107.99 -1 -1 107828 -1 -1 1454 402 0 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 521432 402 150 39533 35581 1 18242 2014 44 44 1936 clb auto 264.4 MiB 222.03 128276 1298740 437176 815390 46174 499.3 MiB 33.29 0.31 9.64776 -28385.1 -9.64776 9.64776 0.01 0.0772257 0.0685146 9.05102 7.67437 -1 -1 -1 -1 -1 211161 16 5.86452e+07 4.26032e+07 4.15480e+07 21460.7 6.45 13.3481 11.4668 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt index f404891e152..83cca486bd7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt @@ -1,10 +1,10 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_IO num_CLB num_DSP num_BRAM vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem router_lookahead_computation_time -ultrascale_ispd.xml FPGA-example1.blif common 101.39 vpr 5.30 GiB 72 220 2 2 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 5555300 51 20 3417 3407 1 3287 296 168 480 80640 -1 ultrascale_ispd 63.2 MiB 4.52 30370 5425.1 MiB 0.76 0.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml clk_design1.blif common 108.35 vpr 5.32 GiB 109 592 2 2 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 5579688 57 20 9969 9959 30 9711 705 168 480 80640 -1 ultrascale_ispd 103.1 MiB 8.18 68744 5448.9 MiB 3.20 0.02 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml clk_design2.blif common 311.90 vpr 5.64 GiB 244 5837 10 10 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 5911804 137 60 100115 100025 45 97978 6101 168 480 80640 -1 ultrascale_ispd 649.1 MiB 83.42 1215177 5773.2 MiB 119.64 0.75 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml clk_design3.blif common 1513.69 vpr 6.60 GiB 374 22993 50 96 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 6917624 217 120 400080 399454 35 390926 23513 168 480 80640 -1 ultrascale_ispd 2324.6 MiB 224.93 5853155 6755.5 MiB 1160.59 7.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml FPGA-example2.blif common 3568.91 vpr 7.24 GiB 456 39262 200 400 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 7590012 303 150 545542 542692 1 539559 40318 168 480 80640 -1 ultrascale_ispd 3455.9 MiB 691.18 13027684 7412.1 MiB 2732.16 15.13 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml FPGA-example3.blif common 3109.38 vpr 6.85 GiB 606 30856 200 500 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 7181808 403 200 431203 428403 1 429172 32162 168 480 80640 -1 ultrascale_ispd 2831.4 MiB 536.72 21109759 7013.5 MiB 2436.46 12.67 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml FPGA-example4.blif common 5438.58 vpr 3.00 GiB -1 -1 -1 -1 exited with return code 1 v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 3144676 403 200 850587 844787 1 -1 -1 168 480 -1 -1 -1 3070.7 MiB 5419.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -ultrascale_ispd.xml clk_design4.blif common 2858.50 vpr 7.52 GiB 484 39151 150 366 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 7888896 292 150 685438 683387 40 669318 40151 168 480 80640 -1 ultrascale_ispd 3874.8 MiB 371.06 11151371 7704.0 MiB 2335.46 13.46 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -ultrascale_ispd.xml clk_design5.blif common 5113.89 vpr 8.35 GiB 515 51693 420 885 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 8758016 307 150 948147 942073 56 928185 53513 168 480 80640 -1 ultrascale_ispd 5337.3 MiB 574.46 14748050 8552.8 MiB 4362.83 21.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_IO num_CLB num_DSP num_BRAM vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + ultrascale_ispd.xml FPGA-example1.blif common 152.30 vpr 5.45 GiB 72 220 2 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 5717652 51 20 3417 3407 1 3313 296 168 480 80640 -1 ultrascale_ispd 62.6 MiB 6.39 29127 70302 16135 47299 6868 5583.6 MiB 1.04 0.01 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 126.54 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml clk_design1.blif common 164.82 vpr 5.48 GiB 109 599 2 2 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 5741876 57 20 9969 9959 30 9749 712 168 480 80640 -1 ultrascale_ispd 92.1 MiB 16.35 65308 280376 87815 184229 8332 5607.3 MiB 4.96 0.05 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 126.01 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml clk_design2.blif common 510.92 vpr 5.79 GiB 244 5810 10 10 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 6072432 137 60 100115 100025 45 98520 6074 168 480 80640 -1 ultrascale_ispd 518.0 MiB 177.20 1236606 6376499 2732445 3580012 64042 5930.1 MiB 178.65 1.52 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 125.62 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml clk_design3.blif common 2252.28 vpr 6.74 GiB 374 22971 50 96 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 7062992 217 120 400080 399454 35 391886 23491 168 480 80640 -1 ultrascale_ispd 1851.9 MiB 456.68 6560103 43066435 19224310 23715269 126856 6897.5 MiB 1611.89 11.45 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 125.36 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml FPGA-example2.blif common 5275.69 vpr 7.41 GiB 456 39004 200 400 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 7770016 303 150 545542 542692 1 540776 40060 168 480 80640 -1 ultrascale_ispd 2692.2 MiB 1740.97 12437987 87734908 35678297 51734577 322034 7587.9 MiB 3320.54 22.50 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 124.18 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml FPGA-example3.blif common 4852.37 vpr 7.12 GiB 606 30951 200 500 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 7468696 403 200 431203 428403 1 429649 32257 168 480 80640 -1 ultrascale_ispd 2191.2 MiB 1101.87 21367578 74964859 33306309 41084396 574154 7293.6 MiB 3557.08 22.36 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 117.25 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml FPGA-example4.blif common 14784.90 vpr 2.60 GiB -1 -1 -1 -1 exited with return code 1 v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2724036 403 200 850587 844787 1 -1 -1 168 480 -1 -1 -1 2660.2 MiB 14757.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + ultrascale_ispd.xml clk_design4.blif common 4467.28 vpr 8.02 GiB 484 39228 150 366 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 8408852 292 150 685438 683387 40 670732 40228 168 480 80640 -1 ultrascale_ispd 3075.9 MiB 761.10 12379630 88225828 36436209 51424919 364700 8211.8 MiB 3483.04 26.72 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 122.67 -1 -1 -1 -1 0 0 -1 -1 -1 + ultrascale_ispd.xml clk_design5.blif common 6947.59 vpr 9.35 GiB 515 51695 420 885 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9801036 307 150 948147 942073 56 927080 53515 168 480 80640 -1 ultrascale_ispd 4230.4 MiB 1092.95 15551057 129073291 53626410 75051110 395771 9571.3 MiB 5605.86 36.60 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 20236814 146167635 -1 -1 -1 -1 -1 -1 -1 125.37 -1 -1 -1 -1 0 0 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology/config/golden_results.txt index 120269160ff..25eafae243f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_clique_topology/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_clique.blif complex_64_noc_clique.flows common 8722.02 vpr 7.77 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8148772 2 64 249332 210540 1 129121 8146 220 162 35640 -1 EP4SE820 2824.5 MiB 402.18 1227222 7957.8 MiB 792.01 4.2 6.60816 -853447 -6.60816 6.60816 2267.92 0.667678 0.54378 90.027 73.7401 154 1426225 49 0 0 359543000 10088.2 4276.17 411.681 346.038 1425419 20 357462 849967 447693681 43661832 7.19548 7.19548 -1044830 -7.19548 0 0 457197000 12828.2 417.73 79.91 33.4499 29.4545 8462400000 8.0592E-05 + arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_clique.blif complex_64_noc_clique.flows common 6533.14 vpr 8.90 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9329352 2 64 249332 210540 1 128290 8215 220 162 35640 -1 EP4SE820 2512.4 MiB 465.27 1072519 9619279 3999578 5530016 89685 9110.7 MiB 2353.60 5.72 7.23069 -915062 -7.23069 7.23069 544.63 0.719936 0.567047 87.9168 69.331 156 1297420 33 0 0 3.63383e+08 10195.9 2597.61 423.092 343.789 8675854 77817419 -1 1299045 19 310556 747262 143100283 32926158 7.54339 7.54339 -1.11196e+06 -7.54339 0 0 4.60857e+08 12930.9 47.10 71.96 147.54 -1 -1 47.10 34.5748 29.7516 8.4448e+09 4.6256e-05 220 3.416e-05 8190.8 8190.8 254 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology/config/golden_results.txt index 5f7100ff98f..f714849cf6f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_nearest_neighbor_topology/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_nearest_neighbor.blif complex_64_noc_nearest_neighbor.flows common 8560.06 vpr 7.77 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8144244 2 32 245317 207097 1 127846 7926 220 162 35640 -1 EP4SE820 2807.4 MiB 400.67 1238130 7953.4 MiB 769.07 5.03 6.71786 -823307 -6.71786 6.71786 2196.38 0.600359 0.532866 91.0284 76.9373 154 1432666 41 0 0 359543000 10088.2 4213.3 388.018 328.35 1435190 17 353532 839730 444668516 43599148 7.3303 7.3303 -1035530 -7.3303 0 0 457197000 12828.2 437.18 75.13 30.7833 27.281 74000000 6.28E-07 + arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_nearest_neighbor.blif complex_64_noc_nearest_neighbor.flows common 3587.02 vpr 8.89 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9318540 2 32 245317 207097 1 126094 8051 220 162 35640 -1 EP4SE820 2496.9 MiB 472.09 1113445 9686771 3913060 5693676 80035 9100.1 MiB 812.26 4.75 7.23069 -923307 -7.23069 7.23069 553.75 0.657025 0.559971 87.3962 70.1887 154 1342481 40 0 0 3.59543e+08 10088.2 1174.00 309.421 251.887 8640214 77173879 -1 1349276 15 299519 719789 139561804 32203257 7.43069 7.43069 -1.08369e+06 -7.43069 0 0 4.57197e+08 12828.2 58.07 63.01 143.33 -1 -1 58.07 30.7802 26.6489 4.48e+07 3.36e-07 112 4.63221e-23 0 0 0 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology/config/golden_results.txt index 71c9b37465d..25bdaa253cc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_star_topology/config/golden_results.txt @@ -1,6 +1,6 @@ -arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_no_constraints.flows common 9220.99 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108432 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.6 MiB 451.61 1045127 7918.4 MiB 842.47 4.96 7.29224 -793365 -7.29224 7.29224 2452.84 0.655239 0.571814 107.218 87.7599 154 1195521 42 0 0 359543000 10088.2 4553.02 410.733 344.98 1194844 18 337553 761991 386559130 36912927 7.62869 7.62869 -982536 -7.62869 0 0 457197000 12828.2 372.54 65.96 28.4745 25.3252 96000000 5.43E-07 -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_2_bandwidths.flows common 9063.36 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108084 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.4 MiB 442.55 1135803 7918.1 MiB 787.79 4.52 6.81554 -811789 -6.81554 6.81554 2376.12 0.650221 0.521368 100.126 80.0299 156 1282477 29 0 0 363383000 10195.9 4524 344.409 286.954 1284251 18 340249 763996 395948352 37975896 7.19262 7.19262 -1017660 -7.19262 0 0 460857000 12930.9 374.68 69.31 29.5326 26.1693 105600000 5.51E-07 -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_6_bandwidths.flows common 8608.75 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108236 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.7 MiB 426.92 1113432 7918.2 MiB 824.4 4.65 7.74124 -815509 -7.74124 7.74124 2331.45 0.653023 0.521789 103.46 83.6904 156 1266529 23 0 0 363383000 10195.9 4077.6 341.899 286.116 1270380 18 332509 742781 383975630 36523096 8.09967 8.09967 -988125 -8.09967 0 0 460857000 12930.9 407.61 68.56 30.06 26.6489 263600000 5.51E-07 -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_24_latency_constraints.flows common 9546.78 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108132 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.6 MiB 423.91 1068621 7918.1 MiB 811.89 4.04 7.72717 -803754 -7.72717 7.72717 2426.52 0.710002 0.571345 102.84 83.4583 154 1224191 48 0 0 359543000 10088.2 5008.21 405.36 340.486 1223376 17 334021 746747 382394575 36624473 7.87541 7.87541 -971559 -7.87541 0 0 457197000 12828.2 337.96 63.14 27.0181 24.0375 96000000 5.43E-07 -stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_63_latency_constraints.flows common 8773.66 vpr 7.73 GiB -1 2 -1 -1 success v8.0.0-6827-g874e0cb8d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2023-01-19T13:42:08 betzgrp-pchenry /home/mahmo494/Desktop/add_noc_testcases/vtr-verilog-to-routing/vtr_flow/tasks 8108316 2 32 239118 200960 1 125464 7868 220 162 35640 -1 EP4SE820 2747.6 MiB 429.96 1059490 7918.3 MiB 784.75 4.56 7.39441 -807678 -7.39441 7.39441 2390.87 0.606083 0.527822 95.4872 77.8918 156 1207682 34 0 0 363383000 10195.9 4234.99 357.12 300.047 1211566 17 332447 741871 381156942 36122392 7.96259 7.96259 -1011780 -7.96259 0 0 460857000 12930.9 391.24 65.6 28.0846 24.9773 96000000 5.49E-07 \ No newline at end of file + arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_no_constraints.flows common 3640.32 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287812 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2447.8 MiB 496.98 935318 9244204 3739459 5425044 79701 9070.1 MiB 723.22 4.11 7.25053 -847174 -7.25053 7.25053 541.90 0.584413 0.526328 86.2119 69.3516 154 1122905 42 0 0 3.59543e+08 10088.2 1337.24 333.111 271.579 8640214 77173879 -1 1130130 15 281926 654752 119322887 27628814 7.72979 7.72979 -977352 -7.72979 0 0 4.57197e+08 12828.2 56.43 61.68 120.78 -1 -1 56.43 29.7426 25.7592 9.64e+07 5.45e-07 63 0 47 47 31 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_2_bandwidths.flows common 3490.34 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287760 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2447.8 MiB 497.41 932527 9244204 3750706 5412944 80554 9070.1 MiB 752.15 4.54 7.25053 -876785 -7.25053 7.25053 541.27 0.617458 0.522798 83.1626 67.1777 156 1118820 36 0 0 3.63383e+08 10195.9 1146.45 293.833 239.47 8675854 77817419 -1 1124333 18 291439 674171 123588076 28491228 7.26463 7.26463 -1.03507e+06 -7.26463 0 0 4.60857e+08 12930.9 52.45 63.92 143.56 -1 -1 52.45 33.3056 28.4835 1.044e+08 5.45e-07 63 0 55 55 31 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_6_bandwidths.flows common 3709.89 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287780 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2447.8 MiB 488.97 952766 9322478 3766958 5480139 75381 9070.1 MiB 737.91 4.65 7.33661 -953349 -7.33661 7.33661 540.65 0.690479 0.534503 87.207 70.0253 154 1132487 44 0 0 3.59543e+08 10088.2 1383.98 347.748 283.963 8640214 77173879 -1 1138839 14 283064 656883 119841555 27746675 7.6573 7.6573 -1.12531e+06 -7.6573 0 0 4.57197e+08 12828.2 54.64 58.28 142.59 -1 -1 54.64 27.6077 23.9412 2.6e+08 5.43e-07 63 0 202.6 202.6 45 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_24_latency_constraints.flows common 3458.53 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287800 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2447.9 MiB 451.90 961316 9322478 3764375 5470496 87607 9070.1 MiB 757.45 5.19 7.23069 -855825 -7.23069 7.23069 551.06 0.629897 0.534167 82.4935 66.9304 156 1151895 26 0 0 3.63383e+08 10195.9 1120.45 282.565 230.471 8675854 77817419 -1 1153410 20 293867 681535 125532955 28871891 7.35255 7.35255 -996899 -7.35255 0 0 4.60857e+08 12930.9 53.38 69.31 150.93 -1 -1 53.38 35.4824 30.1217 9.64e+07 5.45e-07 63 1.15805e-23 47 47 31 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.xml complex_64_noc_star.blif complex_64_noc_star_63_latency_constraints.flows common 3472.77 vpr 8.86 GiB -1 2 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 9287976 2 32 239118 200960 1 120794 7872 220 162 35640 -1 EP4SE820 2448.1 MiB 468.20 978163 9087656 3721856 5286813 78987 9070.3 MiB 741.37 4.79 7.27106 -872324 -7.27106 7.27106 559.88 0.624354 0.529616 83.313 65.7244 156 1154394 23 0 0 3.63383e+08 10195.9 1124.03 279.056 226.133 8675854 77817419 -1 1158703 17 293445 680601 124608454 28649322 7.41757 7.41757 -972651 -7.41757 0 0 4.60857e+08 12930.9 53.23 64.72 150.44 -1 -1 53.23 31.9292 27.2724 9.6e+07 5.43e-07 62 2e-09 47.2 47.2 30 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt index 2228fe597c5..e381a9de6fe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml 670.37 vpr 2.73 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 2864852 42 35 119888 86875 1 51827 3555 129 96 12384 -1 neuron 1830.2 MiB 172.36 594144 2717.0 MiB 138.71 0.74 7.46153 -74648.7 -6.46153 5.54155 51.28 0.274778 0.247975 53.2107 45.4545 -1 765239 22 0 0 2.28642e+08 18462.7 50.37 70.484 61.0725 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml 622.22 vpr 2.73 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 2860400 42 35 119888 86875 1 51282 3422 129 96 12384 -1 neuron 1826.3 MiB 90.78 596408 2713.4 MiB 167.88 0.80 8.25008 -74642.4 -7.25008 5.56231 58.54 0.306592 0.257358 58.1537 49.2936 -1 773864 29 0 0 2.28642e+08 18462.7 55.15 79.2702 68.3071 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml 651.75 vpr 2.73 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-6565-g889ebebc8 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-10-24T12:43:52 betzgrp-wintermute.eecg.utoronto.ca /home/zhaisito/workspace/vtr_fix/vtr-verilog-to-routing/vtr_flow/tasks 2861964 42 35 119888 86875 1 51283 3425 129 96 12384 -1 neuron 1827.4 MiB 90.76 596968 2714.9 MiB 128.31 0.86 8.38198 -70951.7 -7.38198 5.24439 61.70 0.302423 0.255454 43.3562 36.7091 -1 770785 27 0 0 2.28642e+08 18462.7 56.26 63.006 54.3937 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml 521.09 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2999364 42 35 119888 86875 1 51488 3609 129 96 12384 -1 neuron 1754.5 MiB 201.53 588950 3296458 1251917 1696829 347712 2929.1 MiB 120.52 0.99 7.81281 -83697.4 -6.81281 5.17837 0.07 0.394336 0.331354 48.5767 41.2186 -1 -1 -1 -1 -1 774816 15 0 0 2.28639e+08 18462.4 38.71 65.6047 56.4158 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml 448.82 vpr 2.85 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2992528 42 35 119888 86875 1 50882 3437 129 96 12384 -1 neuron 1746.7 MiB 106.69 578743 3192458 1206112 1829273 157073 2922.4 MiB 136.43 1.09 8.30532 -83283.1 -7.30532 5.88288 0.07 0.398109 0.334174 50.9205 42.9915 -1 -1 -1 -1 -1 751914 17 0 0 2.28639e+08 18462.4 38.69 68.6074 58.8539 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch_neuron.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml 453.84 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2994616 42 35 119888 86875 1 50816 3438 129 96 12384 -1 neuron 1748.6 MiB 106.43 587491 3064004 1147605 1894430 21969 2924.4 MiB 135.58 1.08 7.95276 -79743.8 -6.95276 5.25276 0.07 0.397692 0.334466 49.3461 41.6555 -1 -1 -1 -1 -1 765801 15 0 0 2.28639e+08 18462.4 38.72 65.6267 56.2745 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt index 7b7954f2f05..42d46a4fbb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml 835.38 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success 16adbfa-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-07-15T00:59:58 gh-actions-runner-vtr-auto-spawned49 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2998168 42 35 119888 86875 1 50931 3418 92 68 12512 -1 neuron3d 1871.5 MiB 125.92 471295 2911586 1070954 1811088 29544 2883.9 MiB 225.67 2.10 7.73071 -71900.2 -6.73071 5.03261 0.22 0.369023 0.308324 43.731 35.9598 -1 672628 24 0 0 2.71622e+08 21708.9 79.02 68.1319 57.7539 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml 820.30 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success 16adbfa-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-07-15T00:59:58 gh-actions-runner-vtr-auto-spawned49 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2995656 42 35 119888 86875 1 50982 3427 92 68 12512 -1 neuron3d 1869.5 MiB 127.02 455014 2973417 1101001 1762977 109439 2881.6 MiB 223.03 1.76 7.42684 -70436.4 -6.42684 5.75387 0.23 0.367143 0.304401 44.7203 37.4852 -1 654498 28 0 0 2.71622e+08 21708.9 78.86 71.0006 61.0273 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml 812.45 vpr 2.86 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success 16adbfa-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-07-15T00:59:58 gh-actions-runner-vtr-auto-spawned49 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2995760 42 35 119888 86875 1 50982 3427 92 68 12512 -1 neuron3d 1869.6 MiB 125.77 465634 3050895 1119051 1501125 430719 2881.9 MiB 206.05 1.47 7.58328 -72552.7 -6.58328 5.5951 0.22 0.365879 0.300546 45.7365 37.5853 -1 663695 23 0 0 2.71622e+08 21708.9 79.71 69.6049 58.853 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml 451.38 vpr 3.00 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3144372 42 35 119888 86875 1 50816 3438 92 68 12512 -1 neuron3d 1748.3 MiB 107.01 466829 2934319 1083146 1824777 26396 3070.7 MiB 121.42 1.02 7.60476 -72127.1 -6.60476 5.56512 0.18 0.379505 0.318093 43.634 37.1671 -1 -1 -1 -1 -1 655727 15 0 0 2.71615e+08 21708.4 39.03 59.6901 51.5812 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml 475.99 vpr 3.00 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3142992 42 35 119888 86875 1 50882 3437 92 68 12512 -1 neuron3d 1747.0 MiB 106.93 491824 2959115 1097287 1744521 117307 3069.3 MiB 138.63 1.02 7.70882 -73552.4 -6.70882 5.31116 0.19 0.374383 0.32362 46.5434 39.1779 -1 -1 -1 -1 -1 687615 23 0 0 2.71615e+08 21708.4 47.56 68.7335 58.9824 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml 468.36 vpr 3.00 GiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 3142568 42 35 119888 86875 1 50882 3437 92 68 12512 -1 neuron3d 1746.6 MiB 106.94 498184 3062823 1134124 1468642 460057 3068.9 MiB 137.72 0.97 7.864 -76728.1 -6.864 5.39064 0.16 0.391075 0.327661 48.2954 40.5989 -1 -1 -1 -1 -1 694746 16 0 0 2.71615e+08 21708.4 40.71 65.5361 56.0476 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt index 5c1b1d03abb..82cad9de83c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt @@ -14,6 +14,7 @@ includes_dir=benchmarks/verilog/koios # Add circuits to list to sweep circuit_list_add=bwave_like.float.small.v +circuit_list_add=bwave_like.fixed.small.v #Commenting out the following because of https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2149 #circuit_list_add=bwave_like.fixed.large.v circuit_list_add=dnnweaver.v diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt index a3d58104f0a..76d710cde44 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt @@ -1,4 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.small.v common 1068.21 vpr 1.88 GiB -1 -1 110.69 930728 6 445.27 -1 -1 199964 -1 -1 1998 114 356 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 1971564 114 86 74339 64124 1 36263 2698 104 104 10816 memory auto 494.2 MiB 45.91 837299 2255578 853320 1293833 108425 1925.4 MiB 91.80 0.70 7.38685 -337841 -7.38685 7.38685 0.10 0.26105 0.226933 34.5308 28.5894 -1 -1 -1 -1 -1 1123690 16 3.44415e+08 1.41306e+08 2.36688e+08 21883.2 48.20 47.1429 39.4245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2948.82 vpr 5.90 GiB -1 -1 166.20 1233468 9 742.44 -1 -1 565628 -1 -1 5863 1428 1144 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 6186936 1428 2108 167036 128693 1 100353 10831 194 194 37636 memory auto 1034.3 MiB 297.91 1911950 21092463 8889289 10615756 1587418 6041.9 MiB 570.71 3.42 13.7488 -1.49441e+06 -13.7488 13.7488 0.23 0.615123 0.537901 116.246 98.5856 -1 -1 -1 -1 -1 2690563 15 1.20484e+09 3.94177e+08 8.26603e+08 21963.1 61.79 142.653 121.696 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 13533.79 vpr 39.26 GiB -1 -1 386.60 1503068 4 2106.20 -1 -1 561408 -1 -1 4062 21 9017 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 41169996 21 26 134109 127288 1 74703 13231 534 534 285156 memory auto 1344.1 MiB 1835.62 3633223 25196690 12025307 13086177 85206 40205.1 MiB 652.38 3.80 13.6669 -1.87459e+06 -13.6669 13.6669 1.86 0.863375 0.716443 163.799 128.72 -1 -1 -1 -1 -1 4235395 13 9.28675e+09 1.3814e+09 6.26030e+09 21953.9 81.75 196.429 156.233 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.small.v common 931.50 vpr 1.87 GiB -1 -1 113.03 934296 6 457.86 -1 -1 197616 -1 -1 1998 114 356 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1964192 114 86 74339 64124 1 36263 2698 104 104 10816 memory auto 483.5 MiB 46.28 831504 2218030 841112 1278117 98801 1918.2 MiB 117.16 0.86 7.53856 -335399 -7.53856 7.53856 0.06 0.275108 0.238404 36.4626 30.0575 -1 -1 -1 -1 -1 1118355 17 3.44415e+08 1.41306e+08 2.36688e+08 21883.2 52.63 49.9496 41.6897 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.fixed.small.v common 173.06 vpr 1.47 GiB -1 -1 20.75 168220 5 13.72 -1 -1 74548 -1 -1 398 112 170 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1538568 112 86 19811 12990 1 14000 910 98 98 9604 dsp_top auto 190.1 MiB 14.52 315052 481382 144974 259763 76645 1502.5 MiB 25.41 0.21 9.1598 -128842 -9.1598 9.1598 0.05 0.122528 0.108983 14.1795 12.3233 -1 -1 -1 -1 -1 421458 14 3.0121e+08 7.10536e+07 2.10570e+08 21925.2 10.49 19.0155 16.6364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2386.29 vpr 5.91 GiB -1 -1 168.23 1230060 9 789.17 -1 -1 566932 -1 -1 6001 1428 1144 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 6193800 1428 2108 167036 128693 1 100353 10969 194 194 37636 memory auto 1037.8 MiB 298.98 1923516 21573286 9150178 10784276 1638832 6048.6 MiB 643.44 3.75 13.1466 -1.44995e+06 -13.1466 13.1466 0.22 0.657801 0.578118 121.534 102.623 -1 -1 -1 -1 -1 2730911 15 1.20484e+09 3.98028e+08 8.26603e+08 21963.1 69.39 148.757 126.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 7876.99 vpr 39.26 GiB -1 -1 375.65 1504352 4 2146.35 -1 -1 561476 -1 -1 4058 21 9017 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 41164592 21 26 134109 127288 1 74696 13227 534 534 285156 memory auto 1322.1 MiB 1808.38 3403261 25186382 12102792 12982264 101326 40199.8 MiB 612.86 4.44 13.7564 -1.83727e+06 -13.7564 13.7564 1.69 0.890769 0.747193 157.229 124.131 -1 -1 -1 -1 -1 4043804 14 9.28675e+09 1.38129e+09 6.26030e+09 21953.9 95.25 192.185 153.77 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt index 00fb3c94ebd..49bd0bf75c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt @@ -1,12 +1,12 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.fixed.small.v common 578.31 vpr 1.69 GiB -1 -1 15.98 171132 5 18.58 -1 -1 78452 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1777120 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.4 MiB 14.61 310763 1735.5 MiB 30.18 0.25 7.69903 -119062 -7.69903 7.69903 7.58 0.0954802 0.083918 11.5352 9.93367 -1 417153 14 4.27832e+08 7.11094e+07 2.96610e+08 22043.0 13.57 16.1651 14.117 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml bwave_like.fixed.small.v common 475.11 vpr 1.61 GiB -1 -1 16.49 170496 5 17.74 -1 -1 78428 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1684784 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.6 MiB 14.47 204907 1645.3 MiB 16.66 0.14 7.6727 -98168.4 -7.6727 7.6727 8.22 0.0569728 0.0468006 6.45423 5.48972 -1 301401 17 6.15573e+08 7.11094e+07 2.68432e+08 19948.8 9.12 9.33955 8.09709 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml bwave_like.fixed.small.v common 363.94 vpr 1.64 GiB -1 -1 16.20 171172 5 17.80 -1 -1 78436 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1723580 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.4 MiB 9.51 205843 1683.2 MiB 14.79 0.12 7.38613 -102539 -7.38613 7.38613 9.73 0.0535513 0.0465826 6.23445 5.29446 -1 303118 15 6.02556e+08 7.11094e+07 2.67862e+08 19906.5 8.56 8.94102 7.74417 -1 -1 -1 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2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1753032 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.4 MiB 14.63 239009 1711.9 MiB 29.57 0.27 7.4648 -108625 -7.4648 7.4648 9.75 0.0996212 0.0874776 11.4443 9.82126 -1 340028 15 4.88358e+08 7.11094e+07 2.87136e+08 21338.9 13.25 16.1056 14.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml bwave_like.fixed.small.v common 601.12 vpr 1.69 GiB -1 -1 16.44 170424 5 19.52 -1 -1 78360 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1777036 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.3 MiB 14.52 309684 1735.4 MiB 25.32 0.19 7.69903 -117065 -7.69903 7.69903 7.34 0.0960045 0.0844204 12.1025 10.4924 -1 419702 17 4.23166e+08 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1749896 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 199.3 MiB 14.79 243033 1708.9 MiB 31.22 0.23 7.69903 -108391 -7.69903 7.69903 10.70 0.0929271 0.0812659 11.9434 10.3067 -1 343928 15 4.83692e+08 7.11094e+07 2.87370e+08 21356.3 13.43 16.719 14.5905 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml bwave_like.fixed.small.v common 609.08 vpr 1.69 GiB -1 -1 14.77 170416 5 15.43 -1 -1 78432 -1 -1 400 112 170 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1771252 112 86 19788 12967 1 14021 912 116 116 13456 -1 auto 200.1 MiB 14.41 323630 1729.7 MiB 36.26 0.24 7.49113 -120759 -7.49113 7.49113 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k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml bwave_like.fixed.small.v common 226.36 vpr 1.94 GiB -1 -1 20.81 170888 5 13.70 -1 -1 74760 -1 -1 399 112 170 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2031452 112 86 19762 12941 1 13999 911 116 116 13456 -1 auto 190.6 MiB 14.84 246355 486451 153890 297699 34862 1983.8 MiB 31.60 0.26 8.8172 -121536 -8.8172 8.8172 0.07 0.120995 0.107853 14.1198 12.2459 -1 -1 -1 -1 -1 343853 13 4.83692e+08 7.10815e+07 2.86254e+08 21273.3 9.57 18.6375 16.2842 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml bwave_like.fixed.small.v common 233.93 vpr 1.98 GiB -1 -1 21.63 171276 5 13.86 -1 -1 74692 -1 -1 399 112 170 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 2071140 112 86 19762 12941 1 13999 911 116 116 13456 -1 auto 190.5 MiB 15.50 331826 530591 171032 318763 40796 2022.6 MiB 35.98 0.25 9.7559 -130615 -9.7559 9.7559 0.08 0.121463 0.108223 15.2844 13.3472 -1 -1 -1 -1 -1 423548 14 4.31814e+08 7.10815e+07 2.94694e+08 21900.5 11.26 20.0898 17.6265 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml bwave_like.fixed.small.v common 221.57 vpr 1.85 GiB -1 -1 21.49 171068 5 14.87 -1 -1 74744 -1 -1 399 112 170 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 1937008 112 86 19762 12941 1 13999 911 116 116 13456 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20.5511 17.9407 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt index 4f8ca9d3650..63ab8871773 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay 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k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 3222.53 vpr 5.21 GiB -1 -1 123.94 1231884 9 1003.75 -1 -1 571344 -1 -1 5865 1428 1144 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5466508 1428 2108 167060 128717 1 100354 10833 194 194 37636 memory auto 1290.9 MiB 282.28 1923492 5338.4 MiB 563.19 2.55 11.8807 -1.40186e+06 -11.8807 11.8807 23.26 0.324762 0.263642 82.6055 68.1074 -1 2737596 16 1.20484e+09 3.94233e+08 8.28785e+08 22021.1 77.10 98.7411 82.5923 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 12022.07 vpr 33.80 GiB -1 -1 375.15 1825460 9 2733.36 -1 -1 600716 -1 -1 4834 21 9017 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 35446888 21 26 151757 142444 1 82530 13915 534 534 285156 memory auto 1706.7 MiB 813.36 3582618 34616.1 MiB 391.34 2.29 18.4106 -1.77608e+06 -18.4106 18.4106 224.47 0.400339 0.326802 71.8404 56.0172 -1 4166999 13 9.28675e+09 1.38061e+09 6.26248e+09 21961.6 73.28 89.659 71.729 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources 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112.00 0.85 11.4354 -320958 -11.4354 11.4354 0.07 0.299925 0.236733 37.4509 30.4784 -1 -1 -1 -1 -1 1318559 17 3.44415e+08 1.56007e+08 2.36688e+08 21883.2 37.89 51.1057 42.2451 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2392.56 vpr 5.90 GiB -1 -1 179.79 1250160 9 741.95 -1 -1 567620 -1 -1 6015 1428 1144 -1 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 6187376 1428 2108 167021 128678 1 100346 10983 194 194 37636 memory auto 1029.7 MiB 306.19 1918633 21488087 9068727 10808393 1610967 6042.4 MiB 631.77 4.23 11.6939 -1.4493e+06 -11.6939 11.6939 0.22 0.631809 0.542666 121.909 102.374 -1 -1 -1 -1 -1 2713088 16 1.20484e+09 3.98419e+08 8.26603e+08 21963.1 84.36 155.32 131.376 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt index 866c693e208..82805da6c73 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt @@ -1,24 +1,24 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est 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8.0033 6.5916 1240.3 MiB -1 12.36 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 416.55 vpr 1.76 GiB 445 2147 19 52 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1844148 131 314 57881 45152 1 32917 2663 49 36 3528 DSP auto 1362.5 MiB 86.85 289814 1976813 693410 1212996 70407 1709.7 MiB 176.27 1.72 218.423 -74978.2 -217.423 218.423 0.04 0.221041 0.187284 24.7923 21.1712 406108 12.3651 98471 2.99823 104154 327607 243738959 17645361 0 0 7.61281e+07 21578.3 31 1038076 13775176 -1 186.552 186.552 -77902.7 -185.552 0 0 29.48 -1 -1 1723.9 MiB 46.29 39.5945 34.0514 1709.7 MiB -1 40.60 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 72.45 vpr 1.18 GiB 42 752 0 0 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1240412 13 29 26295 20086 1 12536 794 29 21 1218 LAB auto 1061.5 MiB 12.01 63060 221294 37233 166811 17250 1211.3 MiB 13.99 0.21 4.9718 -5064.95 -3.9718 2.73193 0.02 0.0324766 0.0279228 2.25118 1.86401 74221 5.92157 18723 1.49378 27286 38567 29499580 2105965 0 0 2.60089e+07 21353.8 14 354380 4695504 -1 5.052 2.76895 -5085.43 -4.052 0 0 11.26 -1 -1 1211.3 MiB 4.96 3.68252 3.10887 1211.3 MiB -1 8.84 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 440.41 vpr 2.21 GiB 964 976 19 34 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2312848 542 422 37277 26038 1 20609 1993 78 58 9048 io auto 1147.2 MiB 53.94 204070 1443748 530591 842183 70974 2258.6 MiB 132.26 1.73 8.57113 -40060.5 -7.57113 8.57113 0.11 0.114346 0.0970879 14.4519 12.3212 298656 14.4936 68121 3.30588 78221 175730 190639053 28196714 0 0 1.96212e+08 21685.7 51 2627776 35616532 -1 7.6521 7.58988 -39168.5 -6.6521 0 0 69.57 -1 -1 2258.6 MiB 42.38 26.6138 23.1015 2258.6 MiB -1 112.64 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 352.19 vpr 2.44 GiB 1107 719 0 0 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2555856 403 704 15490 16194 1 8578 1826 88 65 11440 io auto 1059.1 MiB 45.27 130173 1273610 483501 754176 35933 2496.0 MiB 30.42 0.29 11.3244 -19683.2 -10.3244 5.27122 0.13 0.0543145 0.0483033 6.97282 5.8855 175112 20.4165 34706 4.04640 26241 103606 64495906 4320076 0 0 2.47902e+08 21669.7 14 3325632 44950250 -1 11.2948 5.14637 -21763.2 -10.2948 0 0 86.50 -1 -1 2496.0 MiB 10.71 9.42628 8.05816 2496.0 MiB -1 152.07 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 119.36 vpr 1.18 GiB 35 731 0 6 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1237480 18 17 16969 16357 1 6316 772 28 21 1176 LAB auto 1056.0 MiB 53.08 73005 241492 57735 179097 4660 1208.5 MiB 12.33 0.20 7.38599 -42310.7 -6.38599 7.38599 0.01 0.0365964 0.0308518 2.95968 2.35615 105687 16.7438 26315 4.16904 22845 117376 78439264 4259070 0 0 2.50919e+07 21336.6 34 342304 4528390 -1 7.17733 7.17733 -42131.3 -6.17733 0 0 10.78 -1 -1 1208.5 MiB 12.71 6.12373 5.01949 1208.5 MiB -1 8.71 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 28.18 vpr 990.12 MiB 35 78 0 8 0 0 success v8.0.0-11333-g1d3eb07f5 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T23:07:52 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1013880 18 17 2291 2142 1 1502 121 13 10 260 LAB auto 951.4 MiB 5.55 9397 11184 1383 8541 1260 990.1 MiB 0.75 0.02 5.30894 -4071.84 -4.30894 4.56748 0.00 0.00643353 0.00532022 0.291101 0.250794 12844 8.56838 3461 2.30887 3750 8551 7007914 560366 0 0 5.17728e+06 19912.6 23 69776 911850 -1 5.37735 4.27489 -3719.74 -4.37735 0 0 2.93 -1 -1 990.1 MiB 1.23 0.669307 0.584049 990.1 MiB -1 0.74 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 244.09 vpr 1.63 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1710388 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.8 MiB 72.33 204820 846239 237450 497497 111292 1670.3 MiB 74.90 0.65 7.79489 -43439.9 -6.79489 3.28078 0.10 0.145044 0.126909 16.2828 14.2166 303821 13.2372 69243 3.01686 62436 131482 118528064 33642231 0 0 9.32900e+07 21594.9 16 1265168 16897716 -1 7.83099 3.2527 -39766.3 -6.83099 0 0 28.25 -1 -1 1670.3 MiB 34.12 23.3299 20.6779 1670.3 MiB -1 9.52 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 283.46 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1568820 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.9 MiB 100.65 250483 930441 270744 617644 42053 1427.9 MiB 105.66 1.16 88.0477 -77760.6 -87.0477 88.0477 0.04 0.138248 0.121195 14.6541 12.2965 344948 13.2210 84158 3.22556 78118 205246 82686512 15002058 0 0 5.14202e+07 21425.1 21 702232 9282330 -1 70.8752 70.8752 -96523.7 -69.8752 0 0 15.93 -1 -1 1478.1 MiB 30.26 22.7139 19.3696 1427.9 MiB -1 5.06 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 546.32 vpr 1.95 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2047732 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.8 MiB 197.71 509639 1864099 634981 1176586 52532 1902.3 MiB 202.15 1.98 13.0046 -365555 -12.0046 7.96311 0.08 0.240136 0.202587 26.0846 21.1277 742613 20.9997 172139 4.86777 125805 451636 168920802 27374866 0 0 1.14226e+08 21633.7 20 1553068 20716258 -1 12.6705 7.40682 -365097 -11.6705 0 0 34.41 -1 -1 1902.3 MiB 62.35 40.2332 33.4484 1902.3 MiB -1 12.28 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 585.36 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2009276 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.3 MiB 179.14 542870 2585506 917648 1577326 90532 1765.2 MiB 247.87 2.16 32.1444 -118378 -31.1444 6.23584 0.07 0.26061 0.217278 28.1774 23.7022 787384 20.0781 179841 4.58591 168930 665993 263454811 44272964 0 0 8.35478e+07 21555.2 21 1135740 15114436 -1 31.2519 6.12513 -116198 -30.2519 0 0 26.38 -1 -1 1858.7 MiB 86.58 43.2996 37.0968 1765.2 MiB -1 8.44 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 665.68 vpr 4.50 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4722308 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.9 MiB 143.60 659423 3667920 1455149 2188340 24431 4611.6 MiB 189.33 1.99 5.44974 -115422 -4.44974 3.12297 0.45 0.489655 0.429947 60.4384 53.4484 794955 11.5117 173671 2.51493 139983 173257 122973577 32392189 0 0 5.40274e+08 21813.4 12 7186500 97663758 -1 5.74024 3.40489 -147279 -4.74024 0 0 162.31 -1 -1 4611.6 MiB 45.39 79.3348 71.0438 4611.6 MiB -1 68.45 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 369.28 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1705764 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.4 MiB 132.64 278563 1870082 659393 1159933 50756 1577.3 MiB 148.04 1.40 223.632 -132177 -222.632 223.632 0.05 0.153184 0.136333 19.0846 16.0118 379374 13.4069 91772 3.24317 82642 255456 77638931 11638769 0 0 7.07061e+07 21491.2 20 956596 12773992 -1 190.135 190.135 -130112 -189.135 0 0 21.26 -1 -1 1598.5 MiB 30.66 28.1882 24.0263 1577.3 MiB -1 6.97 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 301.91 vpr 1.70 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1787064 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.6 MiB 111.07 267316 798034 216514 557130 24390 1745.2 MiB 83.83 0.97 17.6841 -330571 -16.6841 17.6841 0.08 0.142592 0.123421 13.5697 11.1733 388393 14.4100 90639 3.36285 77554 201450 104702784 19227779 0 0 1.03316e+08 21578.1 23 1396452 18714052 -1 16.8884 16.8884 -322143 -15.8884 0 0 31.36 -1 -1 1745.2 MiB 37.27 22.9987 19.4136 1745.2 MiB -1 9.87 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 129.79 vpr 1.23 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1288736 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 60.90 109402 531288 160105 346309 24874 1229.7 MiB 21.34 0.27 7.65386 -81772.1 -6.65386 7.65386 0.03 0.0542655 0.0415901 4.69487 3.74852 159807 19.3237 38947 4.70943 27112 111164 42415566 5550679 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 7.62538 7.62538 -77759.3 -6.62538 0 0 10.12 -1 -1 1229.7 MiB 15.08 7.2902 6.0554 1229.7 MiB -1 2.80 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 294.21 vpr 1.53 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1605968 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.4 MiB 149.56 245617 1517216 535912 903537 77767 1503.4 MiB 67.74 0.64 12.3707 -91754.7 -11.3707 4.62772 0.04 0.123763 0.0993875 12.5521 10.1851 366533 18.0443 84029 4.13671 58196 217697 65258498 9131006 0 0 6.38257e+07 21490.1 17 866116 11532596 -1 12.1773 4.52077 -87689.2 -11.1773 0 0 19.45 -1 -1 1503.4 MiB 24.63 19.0845 15.7987 1503.4 MiB -1 5.86 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 373.27 vpr 2.31 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2418176 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.2 MiB 113.69 225912 2286656 861887 1362579 62190 2361.5 MiB 99.88 0.94 9.64748 -102230 -8.64748 9.64748 0.14 0.158799 0.128764 21.1153 17.3148 383721 19.4260 88332 4.47183 55000 174045 129359271 32477749 0 0 2.01410e+08 21605.9 18 2701980 36491882 -1 8.6078 8.6078 -177231 -7.6078 0 0 60.49 -1 -1 2361.5 MiB 43.58 29.7071 24.9856 2361.5 MiB -1 22.04 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 287.89 vpr 2.03 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2130704 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.2 MiB 94.47 222406 1491426 518693 900478 72255 2080.8 MiB 60.89 0.53 9.27552 -41609.1 -8.27552 3.17342 0.13 0.131124 0.103107 15.5709 12.4005 371010 17.4897 81992 3.86518 55375 161185 120683489 26150077 0 0 1.70845e+08 21669.8 17 2296616 31015204 -1 9.29871 3.26388 -44629 -8.29871 0 0 50.69 -1 -1 2080.8 MiB 36.84 22.1828 18.2794 2080.8 MiB -1 17.67 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 115.46 vpr 1.42 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1487204 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 45.32 98385 149036 34562 99301 15173 1452.3 MiB 10.21 0.11 5.55968 -32411 -4.55968 4.12503 0.05 0.05808 0.0509959 5.30612 4.48561 158711 21.0019 34047 4.50536 20479 45132 33648692 7897451 0 0 7.61223e+07 21576.6 14 1038076 13772104 -1 5.83812 3.95731 -37986.2 -4.83812 0 0 22.99 -1 -1 1452.3 MiB 10.69 8.06663 7.00321 1452.3 MiB -1 7.95 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 308.79 vpr 1.75 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1838356 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1276.3 MiB 90.95 215620 2002487 658856 1202364 141267 1795.3 MiB 112.04 0.92 42.7601 -66808.9 -41.7601 42.7601 0.09 0.161772 0.13883 20.582 17.6888 320121 12.3518 76529 2.95285 71977 215082 87258601 20096356 0 0 1.07584e+08 21568.7 22 1452444 19486512 -1 38.7113 38.7113 -63596.1 -37.7113 0 0 32.70 -1 -1 1795.3 MiB 31.75 30.3911 26.5086 1795.3 MiB -1 11.75 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 194.32 vpr 1.76 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1848104 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1132.2 MiB 67.11 123583 1109975 381766 683735 44474 1804.8 MiB 39.31 0.39 9.15523 -32316.9 -8.15523 9.15523 0.10 0.0795356 0.0699448 8.32413 7.00496 172751 13.5928 41221 3.24345 30616 114657 28576108 5137032 0 0 1.28005e+08 21615.1 15 1733724 23216534 -1 8.8255 8.62305 -32652.3 -7.8255 0 0 39.07 -1 -1 1804.8 MiB 12.08 12.4456 10.6768 1804.8 MiB -1 13.32 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 379.96 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1788552 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1329.9 MiB 152.43 244085 1624747 493620 1093099 38028 1607.0 MiB 139.05 1.16 10.4142 -184930 -9.41415 10.4142 0.05 0.16033 0.126535 18.0534 14.5425 331959 9.29987 79923 2.23905 99630 253842 70436166 10502572 0 0 7.07061e+07 21491.2 17 956596 12773992 -1 9.6278 9.6278 -188775 -8.6278 0 0 21.47 -1 -1 1660.8 MiB 28.25 26.8951 22.1285 1607.0 MiB -1 7.63 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 241.84 vpr 1.65 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1727976 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.3 MiB 91.18 155434 1168868 372786 754711 41371 1617.1 MiB 70.29 0.65 5.78947 -22744 -4.78947 5.78947 0.06 0.166564 0.140884 17.2708 14.567 220363 9.18294 52613 2.19248 52262 94777 51757158 12255510 0 0 7.61223e+07 21576.6 17 1038076 13772104 -1 6.13383 6.13383 -28632.3 -5.13383 0 0 23.67 -1 -1 1626.7 MiB 20.25 25.2854 21.7301 1617.1 MiB -1 7.50 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 123.74 vpr 1.21 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1272416 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.6 MiB 48.17 156959 264252 69818 174977 19457 1223.8 MiB 19.40 0.22 6.30018 -21278.5 -5.30018 5.08848 0.02 0.0625285 0.0502951 5.37481 4.40679 214370 17.8300 51439 4.27838 52424 159985 69493207 10252744 0 0 3.29272e+07 21437.0 19 447460 5950766 -1 6.55525 5.17583 -23692.3 -5.55525 0 0 10.23 -1 -1 1223.8 MiB 22.52 9.11353 7.72653 1223.8 MiB -1 2.91 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 378.16 vpr 1.77 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1853480 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1362.9 MiB 112.93 299223 1985810 694705 1211569 79536 1665.8 MiB 167.05 1.45 220.781 -74322.2 -219.781 220.781 0.07 0.200934 0.169269 24.1803 20.5128 416847 12.7247 100775 3.07625 94693 283672 85089101 14646952 0 0 7.61223e+07 21576.6 21 1038076 13772104 -1 190.574 190.574 -74796.5 -189.574 0 0 22.90 -1 -1 1729.6 MiB 34.84 36.1614 31.133 1665.8 MiB -1 7.44 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 60.08 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1240452 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1062.9 MiB 15.84 61122 230944 38935 173615 18394 1188.2 MiB 11.81 0.18 4.96737 -5434.49 -3.96737 2.8073 0.02 0.0387336 0.0317178 2.57184 2.12328 72725 5.84747 18233 1.46603 25673 34471 10834392 1619170 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.00956 2.55962 -5093.98 -4.00956 0 0 8.03 -1 -1 1188.2 MiB 4.50 4.29731 3.66237 1188.2 MiB -1 2.18 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 297.39 vpr 2.16 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2263120 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.4 MiB 73.81 204576 1445886 511132 869441 65313 2210.1 MiB 89.30 0.98 8.29539 -39922.7 -7.29539 8.29539 0.17 0.107171 0.0943286 12.3686 10.4512 291171 14.2731 67635 3.31544 59148 140903 91946515 22482953 0 0 1.96207e+08 21685.1 19 2627776 35613460 -1 7.77837 7.50651 -37244.2 -6.77837 0 0 58.79 -1 -1 2210.1 MiB 28.79 18.2832 15.7996 2210.1 MiB -1 21.60 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 209.37 vpr 2.38 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2494924 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.9 MiB 49.01 125640 1144742 417642 695010 32090 2436.4 MiB 27.60 0.29 12.1377 -20404.2 -11.1377 5.98066 0.18 0.0583692 0.0490098 6.35528 5.34844 169403 19.8527 34281 4.01746 23768 95388 22780638 3618006 0 0 2.47896e+08 21669.2 14 3325632 44947178 -1 12.3671 6.09382 -23278.4 -11.3671 0 0 74.30 -1 -1 2436.4 MiB 9.07 9.00673 7.74787 2436.4 MiB -1 27.37 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 116.44 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1231712 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.8 MiB 66.58 77598 237654 57043 175228 5383 1183.4 MiB 12.28 0.19 7.75636 -48829.2 -6.75636 7.75636 0.02 0.0387637 0.0330252 3.16043 2.55192 107783 17.1520 26590 4.23138 18971 91032 29347868 3748700 0 0 2.50861e+07 21331.7 15 342304 4525318 -1 7.25059 7.25059 -44231.5 -6.25059 0 0 7.74 -1 -1 1183.4 MiB 10.12 5.32204 4.46908 1183.4 MiB -1 2.14 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 23.94 vpr 993.17 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1017004 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.6 MiB 6.88 10123 9091 942 7112 1037 993.2 MiB 0.58 0.01 5.30858 -4060.6 -4.30858 4.62312 0.00 0.00627854 0.00548745 0.259054 0.223136 13428 9.29273 3606 2.49550 3290 8079 3159547 482733 0 0 5.17151e+06 19890.4 10 69776 908778 -1 5.28356 4.46405 -3916.13 -4.28356 0 0 1.74 -1 -1 993.2 MiB 1.11 0.547712 0.492658 993.2 MiB -1 0.20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt index c82ecd830c2..46f57bf760a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt @@ -1,24 +1,24 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 262.54 vpr 1.67 GiB 274 985 36 59 0 2 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1751260 22 252 53001 29054 7 24677 1356 54 40 4320 DSP auto 1201.6 MiB 29.07 193351 856584 241304 515166 100114 1710.2 MiB 57.40 0.47 7.85588 -42871.3 -6.85589 3.25066 0.05 0.164012 0.144346 20.1769 17.6827 321085 13.0284 73107 2.96640 77217 159907 244975232 47657761 0 0 9.32956e+07 21596.2 51 1265168 16900788 -1 7.71858 3.05436 -39723.1 -6.71858 0 0 35.16 -1 -1 1710.2 MiB 58.56 36.785 32.606 1710.2 MiB -1 53.64 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 266.43 vpr 1.49 GiB 36 1571 10 10 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1563992 3 33 48977 39238 1 26076 1627 40 30 2400 LAB auto 1224.2 MiB 84.53 219644 900737 262240 597791 40706 1464.3 MiB 59.40 0.56 87.2663 -78342.6 -86.2663 87.2663 0.03 0.136963 0.113622 14.4066 12.1423 358074 13.7340 86107 3.30266 114584 318694 268050281 21927928 0 0 5.14259e+07 21427.5 25 702232 9285402 -1 70.0405 70.0405 -100596 -69.0405 0 0 20.03 -1 -1 1474.7 MiB 45.67 22.9811 19.484 1464.3 MiB -1 26.55 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 502.31 vpr 1.94 GiB 211 2249 3 210 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2037436 38 173 62892 59064 3 35496 2673 60 44 5280 M9K auto 1410.0 MiB 165.24 469808 1875516 643371 1181456 50689 1947.1 MiB 111.84 1.00 12.7266 -347397 -11.7266 7.76695 0.06 0.21795 0.188479 25.7283 20.759 761318 21.4516 174875 4.92744 146514 536546 425254345 33830656 0 0 1.14231e+08 21634.7 42 1553068 20719330 -1 12.751 7.43563 -359178 -11.751 0 0 42.27 -1 -1 1947.1 MiB 79.84 46.0754 37.7929 1947.1 MiB -1 61.86 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 510.28 vpr 1.91 GiB 574 2798 16 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2002052 4 570 66175 54803 2 39284 3388 51 38 3876 LAB auto 1448.3 MiB 155.18 480842 2546888 886276 1563516 97096 1812.7 MiB 134.18 1.24 29.1982 -116620 -28.1982 5.72994 0.05 0.279475 0.249568 28.0608 23.8653 835653 21.2748 189102 4.81433 189134 743856 723324517 67486197 0 0 8.35534e+07 21556.6 23 1135740 15117508 -1 29.3026 5.84212 -116980 -28.3026 0 0 30.38 -1 -1 1852.8 MiB 112.28 42.3369 36.2977 1812.7 MiB -1 38.66 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 867.83 vpr 4.60 GiB 40 3678 172 1 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 4821640 19 21 171111 96274 1 73403 3891 129 96 24768 DSP auto 1885.8 MiB 97.55 673610 3766584 1489345 2249664 27575 4708.6 MiB 146.85 1.66 6.29597 -125028 -5.29597 3.97866 0.29 0.540165 0.485534 68.9859 61.9344 848230 11.5563 178165 2.42732 147804 178663 227513169 41591039 0 0 5.40280e+08 21813.6 12 7186500 97666830 -1 6.65084 4.08305 -163510 -5.65084 0 0 181.11 -1 -1 4708.6 MiB 50.62 87.2479 78.818 4708.6 MiB -1 325.55 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 343.21 vpr 1.62 GiB 536 1956 7 4 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1698584 227 309 49176 40422 1 28426 2503 47 35 3290 io auto 1277.4 MiB 116.96 233056 1803125 631727 1120429 50969 1619.5 MiB 88.74 0.85 220.939 -126998 -219.939 220.939 0.04 0.166742 0.142156 19.3794 16.4143 379748 13.3611 92233 3.24513 99103 311914 224583690 13083987 0 0 7.07118e+07 21493.0 21 956596 12777064 -1 187.057 187.057 -123104 -186.057 0 0 27.10 -1 -1 1619.5 MiB 37.22 28.2116 24.0272 1619.5 MiB -1 38.39 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 315.38 vpr 1.74 GiB 36 1347 8 149 2 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1829548 3 33 52402 39411 1 28031 1542 57 42 4788 M9K auto 1243.2 MiB 86.72 244124 776277 216128 536517 23632 1786.7 MiB 52.34 0.52 17.0483 -326259 -16.0483 17.0483 0.07 0.138809 0.121469 14.0009 11.569 405781 14.4803 94699 3.37933 90589 226981 215520672 23742240 0 0 1.03322e+08 21579.3 36 1396452 18717124 -1 16.875 16.875 -325058 -15.875 0 0 36.75 -1 -1 1786.7 MiB 43.28 25.6581 21.481 1786.7 MiB -1 63.41 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 139.86 vpr 1.23 GiB 251 959 1 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1284536 55 196 20131 19956 1 8238 1228 32 24 1536 LAB auto 1088.0 MiB 53.11 91486 559933 175888 358521 25524 1248.2 MiB 15.79 0.19 7.71763 -76349.3 -6.71763 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v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1764996 79 38 66795 54922 1 36434 2280 46 34 3128 LAB auto 1327.7 MiB 94.53 193506 1442280 408990 987732 45558 1622.8 MiB 107.09 0.96 10.4896 -189466 -9.48956 10.4896 0.04 0.181193 0.143388 18.7619 15.1531 299015 8.20771 73882 2.02800 103402 216097 142829772 7784557 0 0 6.72076e+07 21485.8 60 910800 12142484 -1 10.3837 10.3837 -194478 -9.38372 0 0 26.33 -1 -1 1638.8 MiB 42.30 42.291 34.5762 1622.8 MiB -1 40.72 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 266.83 vpr 1.64 GiB 213 1563 26 4 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1720856 139 74 57121 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ucsb_152_tap_fir_stratixiv_arch_timing.blif common 72.91 vpr 1.18 GiB 42 752 0 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 1240564 13 29 26295 20086 1 12536 794 29 21 1218 LAB auto 1062.3 MiB 12.25 60938 224969 39079 169148 16742 1211.5 MiB 8.86 0.14 4.98143 -5213.57 -3.98143 2.67558 0.02 0.0416776 0.0341297 2.6038 2.15581 76160 6.07627 19086 1.52274 27055 37715 33235953 2126435 0 0 2.60089e+07 21353.8 15 354380 4695504 -1 5.12425 2.73808 -5240.77 -4.12425 0 0 10.15 -1 -1 1211.5 MiB 5.50 4.50745 3.80146 1211.5 MiB -1 13.00 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 419.11 vpr 2.21 GiB 964 976 19 34 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2314204 542 422 37277 26038 1 20609 1993 78 58 9048 io auto 1148.8 MiB 54.92 195960 1431211 527491 836231 67489 2260.0 MiB 75.94 0.81 8.64801 -40234.9 -7.64801 8.64801 0.16 0.123859 0.105031 15.0886 12.8374 307874 14.9410 69309 3.36353 75615 168495 192889124 28407970 0 0 1.96212e+08 21685.7 49 2627776 35616532 -1 7.7876 7.7876 -39277.6 -6.7876 0 0 70.32 -1 -1 2260.0 MiB 47.47 28.8645 24.8552 2260.0 MiB -1 140.28 -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 372.90 vpr 2.44 GiB 1107 719 0 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 2556376 403 704 15490 16194 1 8578 1826 88 65 11440 io auto 1059.8 MiB 48.57 116298 1217830 465874 718697 33259 2496.5 MiB 20.86 0.20 11.5693 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agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1710616 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.9 MiB 75.60 184944 854209 237356 546771 70082 1670.5 MiB 72.88 0.69 7.97251 -43075.7 -6.97251 3.30339 0.08 0.146166 0.132698 17.0437 15.0301 301371 13.1305 69191 3.01460 59225 124430 116802792 31972323 0 0 9.32900e+07 21594.9 16 1265168 16897716 -1 8.04852 3.11041 -39249.7 -7.04852 0 0 28.37 -1 -1 1670.5 MiB 33.95 23.995 21.3968 1670.5 MiB -1 9.57 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 270.96 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1570676 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.8 MiB 102.33 228282 920766 279042 595583 46141 1429.0 MiB 88.59 0.94 88.2845 -80659 -87.2845 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11.90 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 567.58 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2010460 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.8 MiB 182.98 484271 2560191 884458 1582491 93242 1765.5 MiB 199.71 1.77 30.1698 -117772 -29.1698 6.32625 0.06 0.250873 0.209174 27.8047 23.3414 819023 20.8849 185777 4.73728 196681 798495 366587115 55913961 0 0 8.35478e+07 21555.2 22 1135740 15114436 -1 29.383 6.18561 -115406 -28.383 0 0 25.30 -1 -1 1859.5 MiB 114.24 42.8002 36.5375 1765.5 MiB -1 8.24 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 659.64 vpr 4.50 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4722024 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.9 MiB 143.54 633199 3760290 1490720 2235840 33730 4611.4 MiB 182.36 1.64 5.44974 -120174 -4.44974 3.48061 0.38 0.500711 0.446581 64.3668 57.2048 792964 11.4829 169052 2.44804 136130 168139 120657048 30423925 0 0 5.40274e+08 21813.4 11 7186500 97663758 -1 5.66375 3.85682 -156124 -4.66375 0 0 164.59 -1 -1 4611.4 MiB 43.21 81.7626 73.4249 4611.4 MiB -1 67.85 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 346.58 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1706888 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1277.2 MiB 130.96 235454 1785192 630171 1108259 46762 1578.0 MiB 123.59 1.24 223.973 -131867 -222.973 223.973 0.06 0.15399 0.137707 18.3847 15.5681 381869 13.4950 92844 3.28105 78342 247729 91337050 11782368 0 0 7.07061e+07 21491.2 19 956596 12773992 -1 184.913 184.913 -126417 -183.913 0 0 21.19 -1 -1 1599.2 MiB 34.88 27.0233 23.1993 1578.0 MiB -1 6.86 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 293.47 vpr 1.70 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1786932 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.4 MiB 111.19 242706 816556 231855 560850 23851 1745.1 MiB 73.99 0.84 17.4268 -331657 -16.4268 17.4268 0.09 0.152091 0.122991 14.1776 11.6814 398717 14.7930 92932 3.44793 77467 205644 117024334 20394306 0 0 1.03316e+08 21578.1 21 1396452 18714052 -1 16.917 16.917 -320368 -15.917 0 0 31.30 -1 -1 1745.1 MiB 38.71 22.7388 19.2113 1745.1 MiB -1 9.99 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 125.97 vpr 1.23 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1288384 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 59.12 92593 557464 169405 360888 27171 1229.7 MiB 20.18 0.28 7.84939 -78165.6 -6.8494 7.84939 0.02 0.0579092 0.0459609 5.05811 4.04769 159733 19.3148 38820 4.69408 24505 101419 42311105 5071555 0 0 3.29272e+07 21437.0 15 447460 5950766 -1 7.81851 7.81851 -71908.7 -6.81851 0 0 10.15 -1 -1 1229.7 MiB 14.27 7.7811 6.44817 1229.7 MiB -1 2.82 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 281.85 vpr 1.53 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1606428 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.5 MiB 149.46 215765 1517216 518543 921536 77137 1503.3 MiB 58.02 0.60 11.9872 -86085.7 -10.9872 4.67996 0.04 0.124604 0.100056 12.4857 10.1291 368614 18.1467 84927 4.18092 54529 192216 59535264 7516911 0 0 6.38257e+07 21490.1 16 866116 11532596 -1 12.0375 4.6146 -82845.8 -11.0375 0 0 19.13 -1 -1 1503.3 MiB 22.39 18.634 15.5175 1503.3 MiB -1 6.30 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 351.01 vpr 2.30 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2416864 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.1 MiB 113.80 191652 2198126 837039 1305954 55133 2360.2 MiB 85.43 0.84 9.95158 -103978 -8.95158 9.95158 0.14 0.157427 0.126297 20.3063 16.4066 380882 19.2822 88412 4.47588 48910 148956 112086751 26603030 0 0 2.01410e+08 21605.9 17 2701980 36491882 -1 9.01423 9.01423 -137565 -8.01423 0 0 60.43 -1 -1 2360.2 MiB 36.97 28.4438 23.7031 2360.2 MiB -1 21.63 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 283.30 vpr 2.03 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2130904 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.7 MiB 91.45 212379 1465966 513016 878305 74645 2081.0 MiB 57.22 0.51 9.02677 -43039.7 -8.02677 3.39009 0.15 0.130982 0.112127 16.0361 12.8184 388469 18.3128 85167 4.01485 54060 155006 126101728 25409947 0 0 1.70845e+08 21669.8 17 2296616 31015204 -1 9.33987 3.47782 -46390.5 -8.33987 0 0 50.94 -1 -1 2081.0 MiB 38.16 22.6708 18.6622 2081.0 MiB -1 18.21 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 116.04 vpr 1.42 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1487240 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1035.3 MiB 44.85 91640 143465 34428 97411 11626 1452.4 MiB 9.56 0.11 5.55968 -32627.3 -4.55968 4.03585 0.05 0.0580242 0.0511336 5.23009 4.40266 162858 21.5506 34640 4.58383 20772 47469 39442838 8696473 0 0 7.61223e+07 21576.6 17 1038076 13772104 -1 5.83812 3.81128 -37803.8 -4.83812 0 0 22.95 -1 -1 1452.4 MiB 12.55 8.31954 7.18554 1452.4 MiB -1 7.74 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 307.88 vpr 1.76 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1842824 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1280.9 MiB 92.83 193340 1985246 651294 1194899 139053 1799.6 MiB 104.91 0.90 42.817 -66341.8 -41.817 42.817 0.08 0.174464 0.149553 21.4513 18.52 318648 12.2949 76857 2.96551 72321 215661 101797360 20420450 0 0 1.07584e+08 21568.7 26 1452444 19486512 -1 38.0834 38.0834 -61419.7 -37.0834 0 0 32.89 -1 -1 1799.6 MiB 36.69 32.4273 28.3397 1799.6 MiB -1 11.41 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 191.13 vpr 1.76 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1848728 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1133.0 MiB 66.11 114187 1121763 389127 687964 44672 1805.4 MiB 36.03 0.35 9.10047 -33210.9 -8.10047 9.10047 0.10 0.0829476 0.0672165 8.6028 7.09879 180406 14.1951 42811 3.36856 29439 106878 36794843 4980523 0 0 1.28005e+08 21615.1 13 1733724 23216534 -1 8.86459 8.53756 -33502.4 -7.86459 0 0 39.09 -1 -1 1805.4 MiB 13.39 12.4192 10.5234 1805.4 MiB -1 13.65 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 365.42 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1789484 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.0 MiB 148.46 220034 1575085 472174 1056131 46780 1607.4 MiB 128.88 1.19 10.366 -185682 -9.366 10.366 0.05 0.166017 0.132704 17.7166 14.3298 340742 9.54593 82334 2.30660 86785 211666 72987830 8810844 0 0 7.07061e+07 21491.2 18 956596 12773992 -1 10.3348 10.3348 -186105 -9.33478 0 0 21.58 -1 -1 1659.8 MiB 29.02 26.9646 22.2301 1607.4 MiB -1 7.36 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 236.24 vpr 1.65 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1729420 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1290.4 MiB 89.13 143448 1223918 387573 791889 44456 1618.2 MiB 69.23 0.62 6.15923 -22935.6 -5.15923 6.15923 0.06 0.160924 0.134554 18.8103 16.0328 226941 9.45706 54238 2.26020 51698 93187 54990565 12041480 0 0 7.61223e+07 21576.6 16 1038076 13772104 -1 6.33927 6.33927 -28490.3 -5.33927 0 0 23.07 -1 -1 1627.8 MiB 19.85 26.0631 22.6082 1618.2 MiB -1 7.69 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 121.12 vpr 1.21 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1272616 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.8 MiB 48.71 145866 267719 70212 178005 19502 1223.6 MiB 17.33 0.21 6.32104 -21443.6 -5.32104 5.1317 0.02 0.0642369 0.0519236 5.54676 4.5538 218475 18.1714 52270 4.34750 52154 158487 72130661 9975959 0 0 3.29272e+07 21437.0 17 447460 5950766 -1 6.2459 4.96992 -24617.9 -5.2459 0 0 10.12 -1 -1 1223.6 MiB 22.65 9.07986 7.70719 1223.6 MiB -1 2.99 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 360.73 vpr 1.77 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1854860 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1363.2 MiB 112.86 262777 1930208 669923 1189043 71242 1666.5 MiB 145.10 1.38 223.441 -74881.2 -222.441 223.441 0.05 0.211297 0.180427 24.3293 20.7548 427696 13.0558 103553 3.16106 90894 273726 106018598 14702817 0 0 7.61223e+07 21576.6 21 1038076 13772104 -1 190.035 190.035 -73399.2 -189.035 0 0 23.08 -1 -1 1732.8 MiB 39.37 36.0725 31.1574 1666.5 MiB -1 7.54 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 60.38 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1239040 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1061.9 MiB 15.77 60924 230944 39979 176254 14711 1186.8 MiB 11.56 0.18 5.04063 -5430.36 -4.04063 2.87222 0.02 0.0364742 0.0318647 2.60212 2.17525 74753 6.01053 18783 1.51025 25814 34889 12202224 1634430 0 0 2.60031e+07 21349.0 17 354380 4692432 -1 5.24483 2.65773 -5067.06 -4.24483 0 0 8.10 -1 -1 1186.8 MiB 4.94 4.43218 3.80588 1186.8 MiB -1 2.32 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 296.54 vpr 2.16 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2262908 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.3 MiB 72.90 213411 1459636 524477 868204 66955 2209.9 MiB 84.09 0.87 8.12716 -41041.3 -7.12716 8.12716 0.14 0.11422 0.095868 12.9019 10.9024 322533 15.8104 73202 3.58833 58164 135585 115660664 26279570 0 0 1.96207e+08 21685.1 19 2627776 35613460 -1 7.60563 7.60563 -38875.6 -6.60563 0 0 58.66 -1 -1 2209.9 MiB 34.96 18.71 16.1454 2209.9 MiB -1 20.83 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 209.98 vpr 2.38 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2494688 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.9 MiB 49.31 117261 1200767 458957 708379 33431 2436.2 MiB 25.42 0.26 11.7854 -20675.2 -10.7854 5.73126 0.18 0.0562212 0.0465333 6.50332 5.46368 182292 21.3632 36297 4.25372 22684 88666 28845037 3461649 0 0 2.47896e+08 21669.2 14 3325632 44947178 -1 11.9953 5.82624 -23038.5 -10.9953 0 0 74.42 -1 -1 2436.2 MiB 10.82 9.12659 7.84634 2436.2 MiB -1 27.36 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 115.88 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1230928 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.5 MiB 66.57 64446 230476 54244 170900 5332 1183.1 MiB 10.85 0.17 7.74825 -47724 -6.74825 7.74825 0.02 0.0458274 0.0351245 3.17308 2.53234 105547 16.7961 26043 4.14433 16938 75501 27527280 3256994 0 0 2.50861e+07 21331.7 14 342304 4525318 -1 7.60467 7.60467 -45348.9 -6.60467 0 0 7.98 -1 -1 1183.1 MiB 9.47 5.27867 4.40168 1183.1 MiB -1 2.23 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 23.87 vpr 993.03 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1016864 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.3 MiB 6.57 8979 9091 989 7145 957 993.0 MiB 0.57 0.01 5.30858 -4141.38 -4.30858 4.67064 0.00 0.00654281 0.00572201 0.265779 0.231578 13865 9.59516 3702 2.56194 3278 7822 3354574 494732 0 0 5.17151e+06 19890.4 12 69776 908778 -1 5.46939 4.48287 -3903.7 -4.46939 0 0 1.75 -1 -1 993.0 MiB 1.23 0.606378 0.546433 993.0 MiB -1 0.21 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt index 1ab11fa8780..1a9fa971299 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt @@ -1,24 +1,24 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 520.61 vpr 1.72 GiB 274 987 36 59 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1803496 22 252 53001 29054 7 24609 1358 54 40 4320 DSP auto 1204.1 MiB 39.90 216521 888364 256649 520395 111320 1761.2 MiB 87.85 0.71 7.67021 -36041.3 -6.67021 3.10875 0.08 0.126381 0.112882 16.7124 14.1733 342154 13.9217 83084 3.38056 76883 151222 326194146 106749769 0 0 8.89497e+07 20590.2 56 1365594 16211305 -1 9.14969 3.16574 -43836.7 -8.14969 0 0 32.91 -1 -1 1761.2 MiB 138.38 31.7678 27.6452 1761.2 MiB -1 194.50 -3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 417.34 vpr 1.50 GiB 36 1580 10 10 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1572468 3 33 48977 39238 1 26329 1636 40 30 2400 LAB auto 1223.7 MiB 106.33 249698 955600 281109 638361 36130 1458.1 MiB 103.12 1.05 82.0766 -56743.3 -81.0766 82.0766 0.04 0.11202 0.0959451 12.7886 10.3669 398272 15.1290 101546 3.85740 95740 256181 200343144 42868641 0 0 4.91306e+07 20471.1 44 758110 8921656 -1 71.392 71.392 -126837 -70.392 0 0 18.37 -1 -1 1481.7 MiB 63.81 24.8111 20.6403 1458.1 MiB -1 98.71 -3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 888.33 vpr 1.97 GiB 211 2261 3 210 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2062840 38 173 62892 59064 3 35566 2685 60 44 5280 M9K auto 1410.9 MiB 217.72 478758 1942701 680573 1218059 44069 2014.5 MiB 176.36 1.51 11.7665 -297024 -10.7665 7.51698 0.09 0.202619 0.16947 25.2532 19.6817 772503 21.7245 195521 5.49850 143008 511949 475300762 109106753 0 0 1.08858e+08 20617.0 56 1675578 19868374 -1 14.2505 7.86617 -385289 -13.2505 0 0 41.27 -1 -1 2014.5 MiB 166.71 50.776 41.2384 2014.5 MiB -1 244.64 -3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1114.78 vpr 1.92 GiB 574 2772 16 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2014640 4 570 66175 54803 2 39317 3362 51 38 3876 LAB auto 1449.1 MiB 196.88 499724 2671912 950738 1625402 95772 1861.6 MiB 224.11 1.77 27.5032 -105534 -26.5032 5.41511 0.06 0.199192 0.172892 26.8354 21.1953 803998 20.4517 200370 5.09692 177923 701320 1281304364 359064468 0 0 7.97022e+07 20563.0 20 1225854 14507865 -1 30.2412 6.45869 -119451 -29.2412 0 0 29.13 -1 -1 1864.8 MiB 453.83 38.7043 31.5496 1861.6 MiB -1 172.45 -3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 2049.90 vpr 4.79 GiB 40 3678 172 1 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5023844 19 21 171111 96274 1 73063 3891 129 96 24768 DSP auto 1882.9 MiB 124.90 684201 3735993 1501648 2208285 26060 4906.1 MiB 148.94 1.66 6.00962 -98830.8 -5.00962 3.45872 0.32 0.391796 0.341532 49.21 43.1537 833239 11.4049 184319 2.52284 146193 177078 507711122 213695314 0 0 5.14406e+08 20769.0 13 7758968 93673935 -1 5.92189 4.22813 -137430 -4.92189 0 0 182.05 -1 -1 4906.1 MiB 207.32 64.5253 57.3404 4906.1 MiB -1 1108.11 -3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 514.96 vpr 1.64 GiB 536 1953 7 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1718304 227 309 49176 40422 1 28164 2500 47 35 3290 io auto 1277.5 MiB 147.28 266723 1918980 725646 1136427 56907 1646.8 MiB 121.43 1.12 194.338 -109756 -193.338 194.338 0.06 0.111355 0.0960834 15.0867 12.0805 409856 14.5545 103143 3.66275 87257 277955 172520127 35585678 0 0 6.75216e+07 20523.3 21 1033138 12274942 -1 196.949 196.949 -148256 -195.949 0 0 25.10 -1 -1 1646.8 MiB 48.56 22.5017 18.5228 1646.8 MiB -1 139.81 -3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 637.08 vpr 1.80 GiB 36 1342 8 149 2 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1888764 3 33 52402 39411 1 28062 1537 57 42 4788 M9K auto 1243.0 MiB 103.75 273842 834941 243386 565684 25871 1844.5 MiB 86.68 0.82 15.7112 -289050 -14.7112 15.7112 0.08 0.119058 0.102615 13.4566 10.7905 420305 14.9820 105404 3.75718 100360 260743 546160418 129480870 0 0 9.85096e+07 20574.3 31 1507654 17957159 -1 18.1236 18.1236 -347845 -17.1236 0 0 36.57 -1 -1 1844.5 MiB 161.91 23.1123 19.1485 1844.5 MiB -1 216.44 -3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 204.89 vpr 1.28 GiB 251 954 1 17 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1341080 55 196 20131 19956 1 8282 1223 32 24 1536 LAB auto 1088.4 MiB 66.85 105468 576479 179756 366623 30100 1309.6 MiB 23.08 0.27 7.56709 -65136 -6.56709 7.56709 0.02 0.0500856 0.0384976 4.85645 3.72985 179329 21.6607 46312 5.59391 29504 122672 72003745 13823732 0 0 3.14199e+07 20455.7 25 483264 5705245 -1 8.81703 8.81703 -85275.7 -7.81703 0 0 12.37 -1 -1 1309.6 MiB 22.42 8.31826 6.6994 1309.6 MiB -1 59.44 -3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 589.98 vpr 1.54 GiB 255 2123 1 28 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1610260 84 171 36458 36247 3 20352 2407 45 33 2970 LAB auto 1231.2 MiB 174.99 241376 1598683 558192 952375 88116 1542.8 MiB 73.08 0.66 10.1083 -70133.7 -9.1083 4.12508 0.04 0.115981 0.0878 12.7489 9.8058 400083 19.6717 97548 4.79634 61046 216519 401222983 118385406 0 0 6.09438e+07 20519.8 15 935204 11078823 -1 12.436 4.7257 -87531.4 -11.436 0 0 22.73 -1 -1 1542.8 MiB 163.43 18.4518 14.7362 1542.8 MiB -1 127.22 -3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 876.17 vpr 2.42 GiB 69 2107 10 295 16 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2536200 36 33 57796 49182 1 20334 2497 79 59 9322 M144K auto 1353.5 MiB 112.44 207195 2136055 812529 1275642 47884 2476.8 MiB 85.13 0.73 8.88006 -82826.8 -7.88006 8.88006 0.14 0.117618 0.0988504 16.8798 13.4801 387054 19.0395 94434 4.64529 67787 213274 284083043 79148811 0 0 1.92002e+08 20596.6 76 2917968 35039980 -1 10.009 10.009 -164810 -9.00897 0 0 68.45 -1 -1 2476.8 MiB 114.92 38.9885 32.6103 2476.8 MiB -1 446.62 -3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 736.20 vpr 2.14 GiB 478 1231 1 300 4 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2247640 202 276 35125 30509 3 21728 2014 73 54 7884 M9K auto 1187.1 MiB 97.40 215797 1654704 587326 990918 76460 2195.0 MiB 74.14 0.51 9.19228 -26875.5 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-3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 569.26 vpr 1.82 GiB 693 1777 25 16 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1904396 35 658 51416 37539 1 27463 2511 58 43 4988 io auto 1278.1 MiB 99.65 212181 2083831 717693 1222429 143709 1859.8 MiB 106.25 0.84 40.5037 -60224.2 -39.5037 40.5037 0.09 0.128488 0.113425 18.2416 14.9291 330278 12.7260 81833 3.15312 94649 304701 197817782 44987282 0 0 1.02587e+08 20566.7 26 1568252 18700371 -1 39.261 39.261 -66616.1 -38.2609 0 0 38.02 -1 -1 1859.8 MiB 59.17 27.948 23.4447 1859.8 MiB -1 230.32 -3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 470.62 vpr 1.83 GiB 753 1108 5 32 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1915540 13 740 25173 25306 1 12781 1898 63 47 5922 io auto 1130.4 MiB 71.87 124962 1223482 428622 736669 58191 1870.6 MiB 40.32 0.32 8.57799 -25886.9 -7.57799 8.57799 0.09 0.0666816 0.0576129 8.22186 6.71409 184141 14.4153 45279 3.54462 32905 123041 47256325 10410499 0 0 1.22008e+08 20602.6 29 1871156 22275272 -1 8.85683 8.47371 -35058.8 -7.85683 0 0 44.24 -1 -1 1870.6 MiB 19.02 13.7447 11.5422 1870.6 MiB -1 265.30 -3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 665.26 vpr 1.70 GiB 117 2173 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1780732 79 38 66795 54922 1 36442 2290 46 34 3128 LAB auto 1332.5 MiB 118.39 223170 1465826 438868 989440 37518 1631.4 MiB 116.51 1.00 10.0034 -164441 -9.00345 10.0034 0.05 0.140615 0.10816 15.3551 12.0225 328872 9.02528 85242 2.33931 156751 378493 614757965 143147538 0 0 6.41689e+07 20514.4 66 983570 11662836 -1 10.4048 10.4048 -200702 -9.40483 0 0 23.96 -1 -1 1655.2 MiB 233.33 36.8481 30.0419 1631.4 MiB -1 139.49 -3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 407.83 vpr 1.66 GiB 213 1565 26 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1737656 139 74 57121 41054 1 24175 1808 49 36 3528 DSP auto 1290.3 MiB 89.57 147265 1212908 383568 790816 38524 1687.9 MiB 69.62 0.60 5.18803 -15564.9 -4.18803 4.69751 0.06 0.132355 0.115165 16.3281 13.6684 218052 9.02122 54686 2.26246 53635 97635 86433611 24558382 0 0 7.26079e+07 20580.5 22 1120110 13214470 -1 5.61308 5.61308 -32689.4 -4.61308 0 0 26.73 -1 -1 1687.9 MiB 33.82 24.3867 20.8618 1687.9 MiB -1 158.29 -3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 207.60 vpr 1.26 GiB 54 659 0 40 0 1 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1323644 2 52 16673 16662 2 12066 754 32 24 1536 M9K auto 1066.2 MiB 53.44 154124 275154 74667 179945 20542 1292.6 MiB 19.41 0.22 5.39679 -16155.6 -4.39679 4.49872 0.02 0.0602811 0.0465091 5.32106 4.24475 238163 19.7449 63975 5.30385 56894 169908 152382564 31381158 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.73871 5.3677 -26489.1 -5.73871 0 0 11.94 -1 -1 1292.6 MiB 44.16 8.78802 7.31639 1292.6 MiB -1 58.83 -3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 633.14 vpr 1.77 GiB 445 2151 19 52 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1857528 131 314 57881 45152 1 32955 2667 49 36 3528 DSP auto 1363.0 MiB 124.71 294607 2054724 754821 1217361 82542 1716.5 MiB 175.07 1.59 191.584 -64615.7 -190.584 191.584 0.05 0.18745 0.150512 23.6039 19.2336 445934 13.5621 110207 3.35169 137218 430293 351839984 68634033 0 0 7.26079e+07 20580.5 40 1120110 13214470 -1 199.253 199.253 -80683.6 -198.253 0 0 29.02 -1 -1 1733.2 MiB 107.66 40.3599 33.6861 1716.5 MiB -1 162.17 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 100.48 vpr 1.19 GiB 42 752 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1244324 13 29 26295 20086 1 12509 794 29 21 1218 LAB auto 1062.8 MiB 15.76 62891 261719 56222 191052 14445 1215.2 MiB 11.16 0.13 4.85572 -4225.92 -3.85572 2.52096 0.02 0.0230785 0.0193446 2.10304 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wb_conmax_stratixiv_arch_timing.blif common 841.75 vpr 2.52 GiB 1107 729 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2644060 403 704 15490 16194 1 8574 1836 88 65 11440 io auto 1060.4 MiB 54.40 122558 1384110 547152 796309 40649 2582.1 MiB 30.97 0.29 10.4549 -16402 -9.45487 4.73896 0.17 0.0533879 0.0433669 6.8282 5.61818 173895 20.2840 38605 4.50309 24038 94279 126191912 44771966 0 0 2.36204e+08 20647.2 14 3590540 43137666 -1 12.0851 5.88321 -24833.6 -11.0851 0 0 83.16 -1 -1 2582.1 MiB 63.98 9.36579 7.90327 2582.1 MiB -1 559.86 -3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 160.76 vpr 1.18 GiB 35 730 0 6 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1240184 18 17 16969 16357 1 6277 771 28 21 1176 LAB auto 1057.6 MiB 67.85 69205 265821 72177 187282 6362 1211.1 MiB 11.88 0.16 7.31748 -40693.1 -6.31748 7.31748 0.02 0.0306438 0.0257343 2.96374 2.35042 113779 18.1379 30059 4.79181 21341 106772 39406769 7295674 0 0 2.39639e+07 20377.5 31 369794 4343188 -1 8.79554 8.79554 -51620.5 -7.79554 0 0 8.95 -1 -1 1211.1 MiB 12.09 5.72142 4.74732 1211.1 MiB -1 40.12 -3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 29.75 vpr 994.02 MiB 35 73 0 8 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1017876 18 17 2291 2142 1 1500 116 13 10 260 LAB auto 953.8 MiB 7.30 9755 9704 1420 7286 998 994.0 MiB 0.48 0.01 5.28239 -3533.58 -4.28239 4.24487 0.00 0.00357156 0.00285794 0.176718 0.144844 15640 10.4476 4912 3.28123 4115 9431 4210567 862713 0 0 4.97530e+06 19135.8 17 75766 878809 -1 5.24221 4.56041 -4449.95 -4.24221 0 0 2.13 -1 -1 994.0 MiB 1.20 0.467896 0.409078 994.0 MiB -1 2.84 +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 1172.59 vpr 1.65 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1734316 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1201.6 MiB 73.64 214653 894059 251005 559264 83790 1693.7 MiB 79.53 0.65 7.70472 -37826.5 -6.70472 3.17657 0.08 0.149615 0.135881 18.4856 16.2276 346942 15.1160 80330 3.49991 71500 157095 1535090931 789230213 0 0 8.89497e+07 20590.2 18 1365594 16211305 -1 7.67229 3.07739 -42724.4 -6.67229 0 0 29.57 -1 -1 1693.7 MiB 940.94 26.0477 23.0694 1693.7 MiB -1 23.96 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 329.77 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1576816 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.5 MiB 99.18 252169 969141 295922 624406 48813 1444.1 MiB 90.56 0.89 82.4495 -56586.4 -81.4495 82.4495 0.03 0.133831 0.117153 15.353 12.8639 420916 16.1326 105895 4.05868 118615 321172 291100673 58952034 0 0 4.91306e+07 20471.1 26 758110 8921656 -1 72.0146 72.0146 -132785 -71.0146 0 0 16.42 -1 -1 1484.9 MiB 85.29 24.7756 21.0909 1444.1 MiB -1 12.23 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 641.04 vpr 1.96 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2050760 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.2 MiB 203.13 510171 1939307 680820 1206280 52207 1927.9 MiB 173.07 1.61 11.2616 -300285 -10.2616 7.35058 0.09 0.251364 0.202792 27.6684 22.4451 799864 22.6187 198121 5.60249 142256 518619 474643655 110260894 0 0 1.08858e+08 20617.0 17 1675578 19868374 -1 14.7898 8.01616 -421363 -13.7898 0 0 36.05 -1 -1 1927.9 MiB 161.55 40.1269 33.3458 1927.9 MiB -1 29.72 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 991.70 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2018452 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.4 MiB 179.88 509692 2712081 968624 1648149 95308 1790.4 MiB 217.33 1.88 26.7071 -106583 -25.7071 4.92953 0.06 0.265658 0.222085 30.753 25.8577 822920 20.9843 201896 5.14831 185617 735052 1296414490 366645497 0 0 7.97022e+07 20563.0 20 1225854 14507865 -1 30.288 6.57341 -120054 -29.288 0 0 26.21 -1 -1 1867.6 MiB 509.93 45.4244 38.8563 1790.4 MiB -1 20.62 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 1067.25 vpr 4.62 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4842056 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.7 MiB 144.01 645363 3760290 1509060 2226895 24335 4728.6 MiB 196.62 2.32 6.72849 -100513 -5.72849 2.73028 0.43 0.510597 0.454713 66.2712 58.6699 801246 11.6028 176582 2.55708 136809 169565 554939068 253332108 0 0 5.14406e+08 20769.0 10 7758968 93673935 -1 6.25252 4.02616 -144264 -5.25252 0 0 173.36 -1 -1 4728.6 MiB 346.30 83.0597 74.3223 4728.6 MiB -1 149.18 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 397.31 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1713464 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.8 MiB 127.62 267729 1921016 704204 1175385 41427 1599.4 MiB 134.02 1.32 194.73 -111174 -193.73 194.73 0.05 0.16753 0.141447 20.6062 17.3755 409980 14.4885 103027 3.64092 98368 318292 234678586 45271456 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 196.841 196.841 -137573 -195.841 0 0 22.11 -1 -1 1604.7 MiB 66.77 29.7244 25.3562 1599.4 MiB -1 17.48 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 413.22 vpr 1.73 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1814172 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.2 MiB 110.44 272716 825817 229328 570617 25872 1771.7 MiB 82.01 0.93 15.8733 -287969 -14.8733 15.8733 0.07 0.156169 0.134842 15.1402 12.4708 427395 15.8570 107058 3.97203 83662 216621 348016314 94876303 0 0 9.85096e+07 20574.3 20 1507654 17957159 -1 18.2989 18.2989 -351435 -17.2989 0 0 32.91 -1 -1 1771.7 MiB 133.99 23.8154 20.073 1771.7 MiB -1 25.41 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 136.48 vpr 1.24 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1295860 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.4 MiB 59.84 106751 583640 180621 371614 31405 1246.6 MiB 21.31 0.25 7.0989 -65567.9 -6.0989 7.0989 0.02 0.0579001 0.0443717 5.41731 4.32489 176951 21.3967 45151 5.45961 29990 122737 58119884 11106318 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.58513 8.58513 -82449.9 -7.58513 0 0 10.90 -1 -1 1246.6 MiB 18.17 8.28886 6.85025 1246.6 MiB -1 6.97 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 490.96 vpr 1.54 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1612568 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.2 MiB 149.78 250819 1565561 553633 923794 88134 1522.9 MiB 59.74 0.57 10.3141 -74446.1 -9.31412 4.16669 0.05 0.122453 0.0982616 12.7928 10.36 417504 20.5535 99339 4.89042 64295 236643 559755019 162046743 0 0 6.09438e+07 20519.8 16 935204 11078823 -1 14.1009 4.7173 -100461 -13.1009 0 0 19.72 -1 -1 1522.9 MiB 220.56 19.1309 15.8639 1522.9 MiB -1 14.15 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2167360 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.5 MiB 91.51 224050 1542346 541947 927260 73139 2116.6 MiB 59.94 0.50 9.32745 -27918.9 -8.32745 3.0761 0.12 0.131152 0.102135 16.6741 13.2554 393714 18.5600 91424 4.30981 54848 152461 310286597 88766009 0 0 1.62738e+08 20641.5 15 2479452 29744051 -1 9.42064 3.77724 -50913.7 -8.42064 0 0 53.44 -1 -1 2116.6 MiB 114.73 22.9686 18.8221 2116.6 MiB -1 44.42 +3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 148.74 vpr 1.44 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1511644 3 2 14862 10304 26 7583 476 49 36 3528 DSP auto 1036.2 MiB 45.72 83064 154607 38752 101305 14550 1476.2 MiB 10.09 0.11 5.67702 -19756.2 -4.67702 3.74463 0.05 0.0597777 0.0527936 5.58527 4.74534 152254 20.1474 35176 4.65476 19877 43738 72454580 21374549 0 0 7.26079e+07 20580.5 14 1120110 13214470 -1 5.84516 4.10311 -39834.2 -4.84516 0 0 24.01 -1 -1 1476.2 MiB 28.04 8.35092 7.24512 1476.2 MiB -1 22.29 +3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 346.43 vpr 1.78 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1868112 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1276.9 MiB 93.13 219255 2157656 730879 1273796 152981 1824.3 MiB 109.67 0.89 40.2879 -60979.5 -39.2879 40.2879 0.08 0.170403 0.154539 23.7513 20.5481 349212 13.4742 85186 3.28688 77275 233364 143562765 36702160 0 0 1.02587e+08 20566.7 21 1568252 18700371 -1 38.5591 38.5591 -67167.5 -37.5591 0 0 34.79 -1 -1 1824.3 MiB 50.23 33.5444 29.3581 1824.3 MiB -1 28.83 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 218.13 vpr 1.79 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1877276 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1133.0 MiB 66.22 123520 1204279 427315 726664 50300 1833.3 MiB 39.61 0.36 9.02181 -27438.3 -8.02181 9.02181 0.09 0.0790484 0.0694683 9.30633 7.78111 180566 14.2077 43756 3.44291 31272 116811 38575938 8660251 0 0 1.22008e+08 20602.6 13 1871156 22275272 -1 10.1297 8.7558 -37422.6 -9.12975 0 0 40.27 -1 -1 1833.3 MiB 15.13 13.1986 11.2705 1833.3 MiB -1 33.84 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 395.83 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1795672 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.1 MiB 147.79 247450 1624747 516348 1068765 39634 1627.6 MiB 129.80 1.19 9.58554 -169343 -8.58554 9.58554 0.05 0.181629 0.143035 18.586 15.0291 368099 10.3123 95475 2.67474 86257 200403 122474916 27418708 0 0 6.75216e+07 20523.3 17 1033138 12274942 -1 10.0787 10.0787 -216795 -9.07872 0 0 22.36 -1 -1 1667.7 MiB 46.86 27.3022 22.6133 1627.6 MiB -1 18.57 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 251.39 vpr 1.66 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1735768 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.7 MiB 85.10 145328 1179878 360849 786061 32968 1640.5 MiB 69.36 0.64 5.18803 -16009.3 -4.18803 4.71553 0.06 0.152706 0.134393 18.4109 15.5777 214240 8.92778 54586 2.27470 53253 96856 65663526 17180534 0 0 7.26079e+07 20580.5 19 1120110 13214470 -1 5.62731 5.62731 -28524.3 -4.62731 0 0 23.91 -1 -1 1640.5 MiB 26.16 26.596 22.9352 1640.5 MiB -1 19.18 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 136.47 vpr 1.23 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1290392 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1065.8 MiB 47.70 152283 278120 75325 183121 19674 1260.1 MiB 18.99 0.21 5.35599 -16505.5 -4.35599 4.51559 0.02 0.0653283 0.0529731 5.96357 4.87661 239529 19.9226 64112 5.33245 57238 170600 111195486 21263938 0 0 3.14199e+07 20455.7 20 483264 5705245 -1 6.61831 5.4172 -26290.3 -5.61831 0 0 10.52 -1 -1 1260.1 MiB 32.71 9.93276 8.38713 1260.1 MiB -1 7.29 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 437.55 vpr 1.78 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1867528 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1362.4 MiB 112.91 292652 2022878 726716 1212218 83944 1695.6 MiB 151.83 1.37 193.523 -65237.6 -192.523 193.523 0.06 0.213557 0.18157 25.9931 22.1715 453070 13.8304 113197 3.45545 117143 365096 327048949 70274290 0 0 7.26079e+07 20580.5 21 1120110 13214470 -1 201.969 201.969 -83602 -200.969 0 0 23.94 -1 -1 1743.7 MiB 97.67 37.8603 32.6631 1695.6 MiB -1 18.81 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 67.95 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1235488 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1063.1 MiB 15.63 63489 256928 52638 188949 15341 1198.2 MiB 13.00 0.16 4.8555 -4307.79 -3.8555 2.47976 0.02 0.0366363 0.0322351 3.02693 2.52688 81757 6.57369 23123 1.85921 26483 36571 27721140 5378093 0 0 2.48366e+07 20391.3 14 382818 4502703 -1 4.99885 2.78104 -5808.83 -3.99885 0 0 8.34 -1 -1 1198.2 MiB 8.51 4.71161 4.0282 1198.2 MiB -1 5.30 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 447.54 vpr 2.19 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2300520 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.3 MiB 74.85 225689 1597136 573868 950177 73091 2246.6 MiB 97.02 0.89 7.40155 -34081.7 -6.40155 7.40155 0.16 0.121776 0.101863 14.3979 12.1212 339854 16.6595 81624 4.00118 64892 154040 296022532 107475224 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.54909 8.54909 -42257.7 -7.54909 0 0 62.88 -1 -1 2246.6 MiB 134.16 19.8788 17.0808 2246.6 MiB -1 53.46 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 304.70 vpr 2.43 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2550580 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.6 MiB 49.77 123671 1380047 554552 786292 39203 2490.8 MiB 31.02 0.26 10.5993 -16629.2 -9.59931 4.97242 0.18 0.0546677 0.0486849 7.77113 6.51315 175220 20.5344 38433 4.50404 23623 93265 107849323 36421682 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 12.8766 5.81047 -24731 -11.8766 0 0 79.59 -1 -1 2490.8 MiB 52.92 10.6013 9.06122 2490.8 MiB -1 68.45 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 117.22 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1225656 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1057.5 MiB 63.70 72669 252010 65056 180799 6155 1192.1 MiB 11.10 0.16 7.46032 -42922.1 -6.46033 7.46032 0.02 0.0386153 0.0330756 3.3215 2.67044 118105 18.7946 31588 5.02673 19732 92762 36148054 6649139 0 0 2.39639e+07 20377.5 15 369794 4343188 -1 7.99918 7.99918 -51485.8 -6.99918 0 0 8.05 -1 -1 1192.1 MiB 11.26 5.50251 4.59387 1192.1 MiB -1 5.21 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 24.11 vpr 992.77 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1016600 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.8 MiB 6.88 9528 9390 1205 7155 1030 992.8 MiB 0.57 0.01 5.30062 -3506.54 -4.30062 4.33661 0.00 0.00633989 0.00552195 0.266113 0.231235 16243 11.2408 5134 3.55294 3509 8574 4051674 833095 0 0 4.97530e+06 19135.8 10 75766 878809 -1 5.2881 4.86207 -4539.08 -4.2881 0 0 1.87 -1 -1 992.8 MiB 1.27 0.557486 0.502971 992.8 MiB -1 0.41 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt index 0ab160efdd9..08e1f46286a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt @@ -1,24 +1,24 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 582.16 vpr 1.72 GiB 274 987 36 59 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1803524 22 252 53001 29054 7 24609 1358 54 40 4320 DSP auto 1204.1 MiB 42.52 195330 858296 247287 495125 115884 1761.3 MiB 84.93 0.67 7.80788 -36648 -6.80788 3.12522 0.08 0.124521 0.103496 15.0607 12.6449 371346 15.1095 103610 4.21573 80566 160946 461930857 165593977 0 0 8.89497e+07 20590.2 51 1365594 16211305 -1 8.74368 3.32525 -48171.4 -7.74368 0 0 32.76 -1 -1 1761.3 MiB 195.95 29.1002 25.2738 1761.3 MiB -1 198.81 -3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 422.96 vpr 1.50 GiB 36 1580 10 10 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1573748 3 33 48977 39238 1 26329 1636 40 30 2400 LAB auto 1223.6 MiB 106.71 248841 888148 253476 594820 39852 1458.1 MiB 105.66 1.10 81.4784 -53835.8 -80.4784 81.4784 0.04 0.109711 0.0935788 11.8789 9.57793 411181 15.6194 116574 4.42826 92798 244546 220907410 47907010 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.6227 72.6227 -121766 -71.6227 0 0 18.53 -1 -1 1483.2 MiB 63.69 19.757 16.3958 1458.1 MiB -1 101.16 -3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 930.36 vpr 1.97 GiB 211 2261 3 210 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2062768 38 173 62892 59064 3 35566 2685 60 44 5280 M9K auto 1410.8 MiB 217.85 527418 1961355 698273 1211201 51881 2014.4 MiB 213.62 1.87 11.5444 -297926 -10.5444 7.43875 0.09 0.221174 0.167818 25.4392 19.6023 799544 22.4850 206009 5.79344 140764 494647 491987729 117958703 0 0 1.08858e+08 20617.0 42 1675578 19868374 -1 14.3661 7.89936 -391318 -13.3661 0 0 40.95 -1 -1 2014.4 MiB 168.06 45.7164 36.8171 2014.4 MiB -1 248.05 -3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1128.29 vpr 1.92 GiB 574 2772 16 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2014856 4 570 66175 54803 2 39317 3362 51 38 3876 LAB auto 1449.1 MiB 197.04 539555 2646737 936545 1618816 91376 1861.6 MiB 263.14 2.12 27.205 -106349 -26.205 5.36288 0.06 0.222737 0.17179 26.4811 20.5787 812545 20.6691 203996 5.18915 179839 704950 1238086925 342084780 0 0 7.97022e+07 20563.0 22 1225854 14507865 -1 30.7692 6.31053 -122652 -29.7692 0 0 28.44 -1 -1 1865.0 MiB 437.18 39.1867 31.6218 1861.6 MiB -1 162.84 -3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 2111.69 vpr 4.79 GiB 40 3678 172 1 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5023412 19 21 171111 96274 1 73063 3891 129 96 24768 DSP auto 1882.4 MiB 124.10 683749 3705402 1474779 2203663 26960 4905.7 MiB 149.84 1.99 4.90769 -102144 -3.90769 2.66229 0.32 0.333623 0.299825 45.1483 39.2326 943364 12.9122 246384 3.37235 150431 182369 732288583 298849219 0 0 5.14406e+08 20769.0 11 7758968 93673935 -1 5.35185 3.87959 -147181 -4.35185 0 0 181.00 -1 -1 4905.7 MiB 286.71 59.0156 52.1235 4905.7 MiB -1 1092.75 -3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 564.65 vpr 1.64 GiB 536 1953 7 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1718716 227 309 49176 40422 1 28164 2500 47 35 3290 io auto 1277.5 MiB 145.88 261565 1868100 672501 1151002 44597 1646.7 MiB 140.05 1.34 195.231 -110925 -194.231 195.231 0.06 0.12554 0.0992061 14.6571 11.6553 411249 14.6040 113307 4.02369 103543 325921 298122992 61172575 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 199.286 199.286 -155282 -198.286 0 0 25.18 -1 -1 1646.7 MiB 79.16 22.1044 18.1436 1646.7 MiB -1 142.30 -3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 695.10 vpr 1.80 GiB 36 1342 8 149 2 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1888536 3 33 52402 39411 1 28062 1537 57 42 4788 M9K auto 1243.2 MiB 103.70 273438 790611 224541 541418 24652 1844.3 MiB 92.12 0.90 15.273 -287167 -14.273 15.273 0.08 0.114449 0.0977109 12.57 10.0601 460533 16.4159 127882 4.55842 95816 245821 618088152 166535403 0 0 9.85096e+07 20574.3 47 1507654 17957159 -1 17.7356 17.7356 -355280 -16.7356 0 0 36.56 -1 -1 1844.3 MiB 212.41 25.6811 21.3256 1844.3 MiB -1 217.95 -3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 201.82 vpr 1.28 GiB 251 954 1 17 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1341092 55 196 20131 19956 1 8282 1223 32 24 1536 LAB auto 1088.4 MiB 65.74 108189 537257 161186 351024 25047 1309.7 MiB 24.49 0.28 7.63348 -66340.6 -6.63348 7.63348 0.02 0.0446494 0.0376164 4.56397 3.53477 173240 20.9252 49009 5.91968 28613 116746 69432612 13114190 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.73313 8.73313 -81669.2 -7.73313 0 0 11.99 -1 -1 1309.7 MiB 20.35 7.28084 5.9123 1309.7 MiB -1 59.04 -3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 574.17 vpr 1.54 GiB 255 2123 1 28 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1610160 84 171 36458 36247 3 20352 2407 45 33 2970 LAB auto 1230.9 MiB 176.26 230253 1534187 537107 918935 78145 1542.6 MiB 80.31 0.73 10.3286 -73217.5 -9.32864 4.15911 0.04 0.109206 0.091457 12.2567 9.37699 386386 18.9982 105938 5.20887 59158 205458 343044614 94954046 0 0 6.09438e+07 20519.8 15 935204 11078823 -1 11.9822 4.48722 -86968.8 -10.9822 0 0 22.88 -1 -1 1542.6 MiB 135.83 18.0758 14.384 1542.6 MiB -1 130.74 -3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 895.60 vpr 2.42 GiB 69 2107 10 295 16 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2536012 36 33 57796 49182 1 20334 2497 79 59 9322 M144K auto 1353.6 MiB 114.46 211332 2152988 849915 1253916 49157 2476.6 MiB 97.43 0.82 9.56163 -84792.3 -8.56163 9.56163 0.14 0.126043 0.0984021 17.6076 13.911 393751 19.3689 103359 5.08431 69197 220461 288511556 81052098 0 0 1.92002e+08 20596.6 45 2917968 35039980 -1 9.93304 9.93304 -167341 -8.93304 0 0 69.52 -1 -1 2476.6 MiB 110.65 31.348 25.8958 2476.6 MiB -1 452.70 -3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 733.35 vpr 2.14 GiB 478 1231 1 300 4 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2246596 202 276 35125 30509 3 21728 2014 73 54 7884 M9K auto 1186.1 MiB 98.22 226155 1680130 581037 1021138 77955 2193.9 MiB 81.38 0.58 9.04734 -32184.9 -8.04734 3.17119 0.12 0.12349 0.0925998 16.6945 12.9764 376551 17.3350 90231 4.15390 60533 167938 291951174 74695878 0 0 1.62738e+08 20641.5 20 2479452 29744051 -1 9.34711 3.98413 -48329.1 -8.34711 0 0 58.73 -1 -1 2193.9 MiB 97.89 23.8118 19.2322 2193.9 MiB -1 359.25 -3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 303.46 vpr 1.46 GiB 5 330 31 105 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1536028 3 2 14862 10304 26 7620 473 49 36 3528 DSP auto 1035.1 MiB 49.34 86372 144149 35218 93920 15011 1500.0 MiB 9.09 0.10 5.35635 -20850.9 -4.35635 3.73741 0.06 0.0454616 0.0396929 4.33095 3.6643 150545 19.8242 37129 4.88925 20992 47091 119548029 36655524 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 5.84657 3.77061 -40487 -4.84657 0 0 26.93 -1 -1 1500.0 MiB 45.25 7.43604 6.47906 1500.0 MiB -1 151.75 -3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 585.18 vpr 1.82 GiB 693 1777 25 16 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1904188 35 658 51416 37539 1 27463 2511 58 43 4988 io auto 1277.9 MiB 98.57 206877 1998531 678358 1182926 137247 1859.6 MiB 115.66 0.95 40.5043 -60922.5 -39.5043 40.5043 0.09 0.122326 0.107203 16.9254 13.7612 342117 13.1822 91004 3.50649 77091 229186 193704618 53247878 0 0 1.02587e+08 20566.7 33 1568252 18700371 -1 39.0491 39.0491 -68044.3 -38.0491 0 0 37.83 -1 -1 1859.6 MiB 69.44 28.0298 23.4918 1859.6 MiB -1 227.84 -3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 484.44 vpr 1.83 GiB 753 1108 5 32 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1915040 13 740 25173 25306 1 12781 1898 63 47 5922 io auto 1130.4 MiB 72.36 122373 1223482 442946 725936 54600 1870.2 MiB 43.47 0.37 8.58151 -26013.6 -7.58151 8.58151 0.09 0.066611 0.0577751 8.09623 6.55743 181674 14.2222 45570 3.56740 33303 126130 60438024 14474337 0 0 1.22008e+08 20602.6 22 1871156 22275272 -1 9.64216 8.37594 -35791.4 -8.64216 0 0 44.59 -1 -1 1870.2 MiB 22.83 12.7955 10.6758 1870.2 MiB -1 273.45 -3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 623.34 vpr 1.70 GiB 117 2173 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1781144 79 38 66795 54922 1 36442 2290 46 34 3128 LAB auto 1333.0 MiB 118.38 223063 1496002 445875 1009592 40535 1631.3 MiB 130.59 1.12 10.298 -164963 -9.29802 10.298 0.05 0.147236 0.114284 15.8825 12.406 335721 9.21323 96583 2.65054 148171 339963 462293429 109838402 0 0 6.41689e+07 20514.4 61 983570 11662836 -1 11.0507 11.0507 -199170 -10.0507 0 0 24.26 -1 -1 1656.6 MiB 176.26 36.1483 29.4745 1631.3 MiB -1 139.48 -3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 434.07 vpr 1.65 GiB 213 1565 26 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1733820 139 74 57121 41054 1 24175 1808 49 36 3528 DSP auto 1291.2 MiB 90.16 142328 1212908 383501 795665 33742 1665.9 MiB 78.06 0.70 5.18054 -15486.2 -4.18054 4.55771 0.06 0.122967 0.105902 15.1532 12.538 255792 10.5826 76054 3.14650 55778 101786 129669669 38217209 0 0 7.26079e+07 20580.5 17 1120110 13214470 -1 5.89185 5.89185 -31809.1 -4.89185 0 0 27.24 -1 -1 1665.9 MiB 49.95 22.1936 18.8747 1665.9 MiB -1 159.11 -3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 203.83 vpr 1.26 GiB 54 659 0 40 0 1 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1324232 2 52 16673 16662 2 12066 754 32 24 1536 M9K auto 1066.4 MiB 53.90 155566 261434 69464 171581 20389 1293.2 MiB 20.41 0.23 5.61272 -16670 -4.61272 4.76097 0.02 0.058552 0.0457308 5.08816 4.03513 232798 19.3001 64048 5.30990 55982 170058 137168149 27075994 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.79545 5.55783 -24965 -5.79545 0 0 12.04 -1 -1 1293.2 MiB 38.89 8.66706 7.15564 1293.2 MiB -1 59.00 -3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 605.13 vpr 1.77 GiB 445 2151 19 52 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1857416 131 314 57881 45152 1 32955 2667 49 36 3528 DSP auto 1362.9 MiB 121.73 289015 2017750 707990 1212909 96851 1716.4 MiB 185.57 1.75 193.424 -63656.5 -192.424 193.424 0.05 0.181205 0.144741 21.1471 16.9918 454441 13.8208 122774 3.73389 118181 360293 262822432 52549899 0 0 7.26079e+07 20580.5 21 1120110 13214470 -1 194.404 194.404 -85184.9 -193.404 0 0 27.34 -1 -1 1734.0 MiB 79.07 32.7617 27.124 1716.4 MiB -1 156.20 -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 99.58 vpr 1.19 GiB 42 752 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1244496 13 29 26295 20086 1 12509 794 29 21 1218 LAB auto 1062.7 MiB 15.63 61236 243344 47038 181714 14592 1215.3 MiB 10.40 0.15 5.00346 -4267.82 -4.00346 2.38962 0.02 0.0231436 0.0188542 1.7862 1.47025 95550 7.63972 32943 2.63397 28913 41935 41958000 8761950 0 0 2.48366e+07 20391.3 15 382818 4502703 -1 5.19398 2.70192 -5808.39 -4.19397 0 0 9.42 -1 -1 1215.3 MiB 11.07 3.16143 2.70178 1215.3 MiB -1 33.35 -3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 909.95 vpr 2.27 GiB 964 977 19 34 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2381096 542 422 37277 26038 1 20599 1994 78 58 9048 io auto 1149.6 MiB 67.08 196066 1482304 530853 872654 78797 2325.3 MiB 124.70 1.43 7.36978 -33273.5 -6.36978 7.36978 0.13 0.0925632 0.0749752 12.0148 9.72001 324180 15.7399 87235 4.23553 91508 211619 398061242 137241372 0 0 1.86852e+08 20651.1 51 2837414 34147767 -1 8.24329 7.76567 -42592.4 -7.24329 0 0 66.15 -1 -1 2325.3 MiB 174.89 22.8404 19.2662 2325.3 MiB -1 437.08 -3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 828.65 vpr 2.52 GiB 1107 729 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2643872 403 704 15490 16194 1 8574 1836 88 65 11440 io auto 1060.4 MiB 54.12 128760 1372872 549171 784185 39516 2581.9 MiB 33.58 0.32 10.7454 -16424.4 -9.74539 5.1543 0.17 0.0471481 0.041409 6.67367 5.49523 170198 19.8528 38778 4.52327 24095 94572 111221252 37508416 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 12.3144 5.56074 -24951.7 -11.3144 0 0 82.34 -1 -1 2581.9 MiB 53.56 9.31536 7.88036 2581.9 MiB -1 555.23 -3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 160.17 vpr 1.18 GiB 35 730 0 6 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1239888 18 17 16969 16357 1 6277 771 28 21 1176 LAB auto 1057.4 MiB 68.96 72908 258753 67776 184461 6516 1210.8 MiB 13.14 0.19 7.51407 -40222.8 -6.51407 7.51407 0.02 0.031379 0.0262939 2.92773 2.28009 115032 18.3376 32494 5.17998 21478 112529 39563291 7329073 0 0 2.39639e+07 20377.5 45 369794 4343188 -1 8.81565 8.81565 -49666.3 -7.81565 0 0 9.04 -1 -1 1210.8 MiB 13.32 6.56727 5.39667 1210.8 MiB -1 35.56 -3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 29.27 vpr 993.75 MiB 35 73 0 8 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1017596 18 17 2291 2142 1 1500 116 13 10 260 LAB auto 953.5 MiB 7.20 9940 8576 1032 6562 982 993.7 MiB 0.50 0.01 5.31743 -3552.51 -4.31743 4.26751 0.00 0.00438277 0.00337059 0.190292 0.160703 16521 11.0361 5707 3.81229 4108 9384 4537270 913138 0 0 4.97530e+06 19135.8 34 75766 878809 -1 5.39567 4.83189 -4585.23 -4.39567 0 0 2.12 -1 -1 993.7 MiB 1.43 0.596507 0.52271 993.7 MiB -1 2.56 +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 536.55 vpr 1.66 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1736116 22 252 53001 29054 7 22984 1419 54 40 4320 DSP auto 1203.7 MiB 75.33 195509 902029 259905 557804 84320 1695.4 MiB 84.98 0.74 7.68567 -37648.9 -6.68567 3.28584 0.07 0.153024 0.133083 18.1163 15.7769 347393 15.1356 91110 3.96959 68562 144013 571183324 243523602 0 0 8.89497e+07 20590.2 16 1365594 16211305 -1 7.79531 3.22903 -48240.7 -6.79531 0 0 29.52 -1 -1 1695.4 MiB 297.68 25.2358 22.2605 1695.4 MiB -1 24.01 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 315.33 vpr 1.50 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1577588 3 33 48977 39238 1 26095 1641 40 30 2400 LAB auto 1223.4 MiB 101.58 259626 940116 279572 621693 38851 1444.2 MiB 104.57 1.20 82.1047 -56021.6 -81.1047 82.1047 0.03 0.137922 0.120416 14.543 12.1914 423885 16.2464 113939 4.36698 96228 253395 185059095 38347475 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.5235 72.5235 -115556 -71.5235 0 0 16.27 -1 -1 1486.1 MiB 54.76 23.4199 19.9723 1444.2 MiB -1 12.10 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 679.10 vpr 1.96 GiB 211 2277 3 210 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2051156 38 173 62892 59064 3 35370 2701 60 44 5280 M9K auto 1407.4 MiB 202.36 543821 1995713 704501 1236982 54230 1927.9 MiB 222.49 2.01 11.2639 -298285 -10.2639 7.34492 0.09 0.259679 0.207609 28.5947 23.0535 806716 22.8124 200624 5.67327 143147 517766 456418331 103863687 0 0 1.08858e+08 20617.0 18 1675578 19868374 -1 13.9133 7.76735 -393376 -12.9133 0 0 36.17 -1 -1 1927.9 MiB 150.24 41.7265 34.527 1927.9 MiB -1 29.72 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1027.30 vpr 1.92 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2017832 4 570 66175 54803 2 39221 3376 51 38 3876 LAB auto 1446.1 MiB 179.29 547789 2661451 958041 1608713 94697 1789.9 MiB 260.36 2.34 27.0929 -106609 -26.0929 5.35183 0.06 0.27456 0.228129 29.5628 24.7422 829210 21.1447 207429 5.28940 184705 723383 1302091086 364260887 0 0 7.97022e+07 20563.0 18 1225854 14507865 -1 30.5677 6.54028 -121409 -29.5677 0 0 25.79 -1 -1 1868.9 MiB 503.91 43.0657 36.7123 1789.9 MiB -1 20.41 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 925.95 vpr 4.62 GiB 40 3697 172 1 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 4842080 19 21 171111 96274 1 69059 3910 129 96 24768 DSP auto 1880.6 MiB 147.82 619747 3698710 1495912 2184534 18264 4728.6 MiB 198.02 2.37 6.78648 -99082.3 -5.78648 3.44108 0.45 0.48725 0.430185 61.9462 54.5962 814845 11.7998 205031 2.96905 140099 173436 458459419 150453276 0 0 5.14406e+08 20769.0 14 7758968 93673935 -1 6.45787 3.53717 -145075 -5.45787 0 0 172.18 -1 -1 4728.6 MiB 193.32 83.1106 74.2663 4728.6 MiB -1 156.75 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 409.69 vpr 1.63 GiB 536 1955 7 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1712060 227 309 49176 40422 1 28301 2502 47 35 3290 io auto 1276.6 MiB 131.22 276554 1921016 711963 1138812 70241 1598.4 MiB 145.73 1.42 195.512 -113504 -194.512 195.512 0.05 0.160338 0.134313 19.3452 16.1804 416656 14.7244 107078 3.78408 104021 334271 218912879 40948386 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 198.006 198.006 -143215 -197.006 0 0 22.05 -1 -1 1607.4 MiB 63.92 28.3971 24.123 1598.4 MiB -1 16.81 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 443.45 vpr 1.73 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1814380 3 33 52402 39411 1 26961 1588 57 42 4788 M9K auto 1243.5 MiB 110.53 271211 807295 220659 561442 25194 1771.9 MiB 87.02 0.90 15.8645 -293903 -14.8645 15.8645 0.07 0.137468 0.119486 13.9778 11.464 446897 16.5806 122453 4.54320 84683 217412 421161484 116638965 0 0 9.85096e+07 20574.3 19 1507654 17957159 -1 17.551 17.551 -341289 -16.551 0 0 33.12 -1 -1 1771.9 MiB 157.72 22.3148 18.7943 1771.9 MiB -1 26.51 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 141.26 vpr 1.24 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1296500 55 196 20131 19956 1 8273 1224 32 24 1536 LAB auto 1088.2 MiB 59.31 113956 557464 166863 359124 31477 1246.8 MiB 24.59 0.29 7.08326 -66257.5 -6.08326 7.08326 0.02 0.055314 0.0441799 5.26138 4.20946 182605 22.0804 50112 6.05949 29285 119606 66293828 12593582 0 0 3.14199e+07 20455.7 15 483264 5705245 -1 8.63522 8.63522 -90099.9 -7.63522 0 0 10.47 -1 -1 1246.8 MiB 20.00 8.06464 6.66092 1246.8 MiB -1 7.35 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 368.03 vpr 1.54 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1613076 84 171 36458 36247 3 20327 2406 45 33 2970 LAB auto 1229.2 MiB 152.28 248422 1517216 526978 905843 84395 1523.2 MiB 71.70 0.64 10.4991 -73576.7 -9.49906 4.26563 0.04 0.123293 0.0990031 12.7883 10.3856 402144 19.7974 109429 5.38714 60309 208858 232045575 52278765 0 0 6.09438e+07 20519.8 18 935204 11078823 -1 12.8865 4.78217 -92799.1 -11.8865 0 0 20.13 -1 -1 1523.2 MiB 81.81 19.2634 16.033 1523.2 MiB -1 15.82 +3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 464.20 vpr 2.35 GiB 69 2192 10 295 16 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2461196 36 33 57796 49182 1 19758 2582 79 59 9322 M144K auto 1354.2 MiB 116.23 224613 2251244 886249 1326045 38950 2403.5 MiB 95.91 0.83 9.49151 -92147.5 -8.49151 9.49151 0.14 0.154631 0.123533 20.7936 16.7804 397126 20.1046 99400 5.03215 58343 180947 261415498 79896454 0 0 1.92002e+08 20596.6 16 2917968 35039980 -1 8.83504 8.83504 -160829 -7.83504 0 0 63.50 -1 -1 2403.5 MiB 101.27 28.5358 23.7007 2403.5 MiB -1 55.56 +3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 411.57 vpr 2.07 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2167564 202 276 35125 30509 3 21219 2016 73 54 7884 M9K auto 1185.7 MiB 93.64 225707 1580536 560957 948186 71393 2116.8 MiB 74.70 0.59 9.27529 -27528.6 -8.27529 3.13114 0.14 0.130328 0.10251 17.2693 13.6101 391848 18.4721 94302 4.44548 55624 156547 339484601 88142541 0 0 1.62738e+08 20641.5 16 2479452 29744051 -1 9.56018 3.68158 -50102.5 -8.56018 0 0 53.61 -1 -1 2116.8 MiB 117.38 23.7611 19.3642 2116.8 MiB -1 45.57 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/home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1871392 35 658 51416 37539 1 27427 2531 58 43 4988 io auto 1280.5 MiB 91.15 211809 2071451 692754 1236953 141744 1827.5 MiB 125.31 1.09 40.9771 -61336.3 -39.9771 40.9771 0.07 0.171234 0.145898 21.8018 18.6515 342831 13.2280 87296 3.36829 76962 231011 136781567 33406286 0 0 1.02587e+08 20566.7 22 1568252 18700371 -1 39.0683 39.0683 -66985.6 -38.0683 0 0 34.25 -1 -1 1827.5 MiB 47.65 31.738 27.5672 1827.5 MiB -1 27.89 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 229.59 vpr 1.79 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1876484 13 740 25173 25306 1 12716 1903 63 47 5922 io auto 1132.6 MiB 66.93 129881 1180703 418671 705083 56949 1832.5 MiB 43.61 0.38 9.05339 -27832.3 -8.05339 9.05339 0.11 0.0813991 0.0719295 9.16919 7.64919 190989 15.0279 45936 3.61445 31437 116923 44250090 9507104 0 0 1.22008e+08 20602.6 13 1871156 22275272 -1 9.68529 8.62738 -38151.5 -8.68529 0 0 40.96 -1 -1 1832.5 MiB 16.73 13.1394 11.2088 1832.5 MiB -1 34.19 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 497.04 vpr 1.71 GiB 117 2338 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1795972 79 38 66795 54922 1 35698 2455 47 35 3290 LAB auto 1330.1 MiB 155.39 246824 1707517 542100 1124665 40752 1627.5 MiB 155.77 1.28 9.48565 -168709 -8.48565 9.48565 0.05 0.168989 0.135904 19.3486 15.5394 380234 10.6523 107944 3.02407 107615 274456 330281609 74151890 0 0 6.75216e+07 20523.3 18 1033138 12274942 -1 10.455 10.455 -199956 -9.45504 0 0 22.28 -1 -1 1670.4 MiB 111.91 28.4097 23.3845 1627.5 MiB -1 17.60 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 327.67 vpr 1.66 GiB 213 1565 26 4 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1742392 139 74 57121 41054 1 24001 1808 49 36 3528 DSP auto 1289.0 MiB 84.58 151125 1190888 390352 769055 31481 1646.6 MiB 73.69 0.67 5.16253 -15574.5 -4.16253 4.57572 0.06 0.14295 0.12611 17.3522 14.6159 255867 10.6625 71175 2.96600 55302 103707 208615694 72938344 0 0 7.26079e+07 20580.5 15 1120110 13214470 -1 5.91719 5.91719 -30815.6 -4.91719 0 0 23.62 -1 -1 1646.6 MiB 95.34 24.5543 21.0784 1646.6 MiB -1 19.49 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 139.09 vpr 1.23 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1291272 2 52 16673 16662 2 12027 760 32 24 1536 M9K auto 1066.0 MiB 49.80 156611 278120 76189 183016 18915 1261.0 MiB 18.22 0.20 5.5971 -16655.2 -4.5971 4.5816 0.03 0.0587051 0.0472882 5.12731 4.2098 232871 19.3688 64465 5.36181 56972 170063 109738115 20757776 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.60942 5.3536 -26554.6 -5.60942 0 0 10.35 -1 -1 1261.0 MiB 31.51 8.7766 7.46125 1261.0 MiB -1 6.22 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 468.75 vpr 1.78 GiB 445 2156 19 52 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1866664 131 314 57881 45152 1 32833 2672 49 36 3528 DSP auto 1361.4 MiB 115.86 298766 2022878 721872 1209208 91798 1694.5 MiB 174.52 1.53 192.881 -65340.9 -191.881 192.881 0.06 0.202016 0.181173 25.4109 21.5614 461781 14.0963 121424 3.70658 122316 378159 341015575 70726261 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 198.296 198.296 -88522.8 -197.296 0 0 24.15 -1 -1 1743.6 MiB 98.43 37.004 31.8471 1694.5 MiB -1 19.45 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.67 vpr 1.18 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1237180 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1063.0 MiB 15.45 60926 230944 41654 173553 15737 1197.6 MiB 9.59 0.15 4.84629 -4259.39 -3.84629 2.46064 0.02 0.0310798 0.0251181 2.06236 1.71947 97856 7.86814 33858 2.72236 28683 39681 30714017 6195766 0 0 2.48366e+07 20391.3 17 382818 4502703 -1 5.05177 2.69405 -5674.91 -4.05177 0 0 8.19 -1 -1 1197.6 MiB 8.55 3.63438 3.14676 1197.6 MiB -1 4.10 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 544.98 vpr 2.19 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2300396 542 422 37277 26038 1 20403 2136 78 58 9048 io auto 1150.1 MiB 76.17 219742 1555886 562141 922870 70875 2246.5 MiB 103.91 1.05 7.36593 -33948.8 -6.36593 7.36593 0.16 0.106572 0.0952071 13.4562 11.2916 354299 17.3676 93322 4.57461 68078 159956 457518312 185590185 0 0 1.86852e+08 20651.1 17 2837414 34147767 -1 8.09599 7.40175 -42456.2 -7.09599 0 0 61.24 -1 -1 2246.5 MiB 222.11 18.7938 16.1322 2246.5 MiB -1 52.95 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 302.19 vpr 2.43 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 2550728 403 704 15490 16194 1 8534 1832 88 65 11440 io auto 1060.8 MiB 47.82 130160 1380047 560321 782548 37178 2490.9 MiB 35.48 0.32 10.5854 -18606.9 -9.58537 4.72024 0.18 0.0600238 0.0497498 7.88269 6.58458 172969 20.2706 38383 4.49818 23174 90029 105109403 34944955 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 11.6218 5.22111 -24845.6 -10.6218 0 0 75.93 -1 -1 2490.9 MiB 48.99 10.7341 9.14711 2490.9 MiB -1 68.06 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 124.32 vpr 1.17 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1226084 18 17 16969 16357 1 6288 780 28 21 1176 LAB auto 1058.1 MiB 67.46 76143 241243 58815 176856 5572 1192.4 MiB 11.31 0.19 7.29112 -42594.5 -6.29112 7.29112 0.02 0.0414227 0.0316342 2.95997 2.38508 119636 19.0382 33085 5.26496 19940 91849 40304260 7468528 0 0 2.39639e+07 20377.5 15 369794 4343188 -1 7.77921 7.77921 -50567.3 -6.77921 0 0 7.94 -1 -1 1192.4 MiB 12.02 5.00754 4.21584 1192.4 MiB -1 4.51 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 27.66 vpr 993.31 MiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 1017148 18 17 2291 2142 1 1448 121 13 10 260 LAB auto 954.6 MiB 6.88 10156 8194 784 6524 886 993.3 MiB 0.47 0.01 5.3048 -3531.01 -4.3048 4.2956 0.00 0.00511192 0.00432104 0.195587 0.167728 15985 11.0623 5210 3.60554 3642 8882 4445146 900786 0 0 4.97530e+06 19135.8 9 75766 878809 -1 5.28906 4.84614 -4691.92 -4.28906 0 0 1.76 -1 -1 993.3 MiB 1.25 0.451107 0.405755 993.3 MiB -1 0.36 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/config.txt new file mode 100644 index 00000000000..68d3b3c2d19 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/config.txt @@ -0,0 +1,78 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/titan23/stratixiv + +# Path to directory of SDCs to use +sdc_dir=benchmarks/titan_blif/titan23/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +circuit_list_add=LU230_stratixiv_arch_timing.blif +circuit_list_add=LU_Network_stratixiv_arch_timing.blif +circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif +circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif +circuit_list_add=bitonic_mesh_stratixiv_arch_timing.blif +circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif +circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif +circuit_list_add=dart_stratixiv_arch_timing.blif +circuit_list_add=denoise_stratixiv_arch_timing.blif +circuit_list_add=des90_stratixiv_arch_timing.blif +circuit_list_add=directrf_stratixiv_arch_timing.blif +circuit_list_add=gsm_switch_stratixiv_arch_timing.blif +circuit_list_add=mes_noc_stratixiv_arch_timing.blif +circuit_list_add=minres_stratixiv_arch_timing.blif +circuit_list_add=neuron_stratixiv_arch_timing.blif +circuit_list_add=openCV_stratixiv_arch_timing.blif +circuit_list_add=segmentation_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif +circuit_list_add=sparcT2_core_stratixiv_arch_timing.blif +circuit_list_add=stap_qrd_stratixiv_arch_timing.blif +circuit_list_add=stereo_vision_stratixiv_arch_timing.blif +# circuit_list_add=gaussianblur_stratixiv_arch_timing.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(sparcT1_core_stratixiv_arch_timing.blif, device=titan_extra_small) +circuit_constraint_list_add=(SLAM_spheric_stratixiv_arch_timing.blif, device=titan_extra_small) +circuit_constraint_list_add=(stereo_vision_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(cholesky_mc_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(neuron_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(segmentation_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(dart_stratixiv_arch_timing.blif, device=titan_small) +circuit_constraint_list_add=(denoise_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(sparcT2_core_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(stap_qrd_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(cholesky_bdti_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(des90_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(mes_noc_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(openCV_stratixiv_arch_timing.blif, device=titan_medium) +circuit_constraint_list_add=(LU_Network_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(minres_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(bitcoin_miner_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(bitonic_mesh_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(gsm_switch_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(sparcT1_chip2_stratixiv_arch_timing.blif, device=titan_large) +circuit_constraint_list_add=(directrf_stratixiv_arch_timing.blif, device=titan_extra_large) +circuit_constraint_list_add=(LU230_stratixiv_arch_timing.blif, device=titan_extra_large) +# circuit_constraint_list_add=(gaussianblur_stratixiv_arch_timing.blif, device=titan_extra_large) + +# Add architectures to list to sweep +arch_list_add=stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +# Pass the script params while writing the vpr constraints. +# WL DRIVEN +script_params=-starting_stage vpr --analytical_place --route --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -timeout 86400 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --timing_analysis off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt new file mode 100644 index 00000000000..37bf9a4b00b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan/config/golden_results.txt @@ -0,0 +1,23 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 5977.17 vpr 18.15 GiB 373 16802 116 5043 16 0 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan 19027644 178 195 583584 0 2 400505 22350 450 333 149850 -1 titan_extra_large -1 -1 8 13800219 48167472 20323894 27731780 111798 18581.7 MiB 4325.24 9.70 -1 -1 -1 -1 -1 -1 0 0 0 0 14590895 36.4326 2750092 6.86682 839764 1658253 951523382 215783707 0 0 2.82057e+09 18822.7 11 43073670 476336488 -1 -1 -1 -1 -1 -1 -1 786.18 -1 -1 18581.7 MiB 264.68 0 0 18581.7 MiB -1 431.81 +stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6231.23 vpr 12.33 GiB 446 31279 112 1175 0 2 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan 12931844 85 185 639752 0 28 383369 33014 300 222 66600 -1 titan_large -1 -1 5 4382970 73613776 28087356 45057103 469317 12628.8 MiB 5449.42 11.97 -1 -1 -1 -1 -1 -1 0 0 0 0 5412290 14.1365 1208865 3.15746 725653 1571351 484682465 110344144 0 0 1.23727e+09 18577.7 10 19158880 211389679 -1 -1 -1 -1 -1 -1 -1 337.84 -1 -1 12628.8 MiB 129.09 0 0 12628.8 MiB -1 172.57 +stratixiv_arch.timing.xml SLAM_spheric_stratixiv_arch_timing.blif common 978.21 vpr 2.83 GiB 479 5395 37 0 0 0 success v8.0.0-12397-gd42b93a83 release IPO VTR_ASSERT_LEVEL=1 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-04-10T17:44:49 agent-2 /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/ap_titan 2968776 323 156 114323 0 1 74722 5911 100 74 7400 -1 titan_extra_small -1 -1 5 952942 6042597 2451728 3507314 83555 2899.2 MiB 845.55 2.07 -1 -1 -1 -1 -1 -1 0 0 0 0 1227102 16.4227 285050 3.81491 174997 556519 135205758 28286969 0 0 1.36295e+08 18418.2 11 2149958 23360463 -1 -1 -1 -1 -1 -1 -1 36.88 -1 -1 2899.2 MiB 39.92 0 0 2899.2 MiB -1 16.65 +stratixiv_arch.timing.xml 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regression_tests/vtr_reg_nightly_test7/titan_other_run_flat #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_run_flat #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt index a425bc681fa..718952957d1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titan_other_run_flat/config/golden_results.txt @@ -1,17 +1,17 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks 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create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 428.95 vpr 5.69 GiB 274 985 36 59 0 2 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5971508 22 252 53001 29054 7 24677 1356 89 66 5874 DSP auto 1467.0 MiB 29.42 248371 954110 285143 562881 106086 2057.9 MiB 74.97 0.48 8.02184 -42397.1 -7.02184 3.20007 0.04 0.161633 0.140714 21.3998 18.8902 338955 6.39912 75485 1.42508 121441 289695 240594743 33482528 0 0 1.48105e+08 25213.7 39 3159283 31787115 49857 7.80104 2.93519 -40292.1 -6.80104 0 0 39.35 35.55 25.88 5831.3 MiB 166.75 33.3779 29.4514 2057.9 MiB 63.99 86.71 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betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6267952 4 570 66175 54803 2 39284 3388 91 67 6097 io auto 1706.5 MiB 160.61 638374 2775803 1006957 1681672 87174 2241.8 MiB 163.90 1.29 30.5835 -120026 -29.5835 6.7874 0.04 0.263073 0.221418 30.5747 25.8293 932098 14.0864 206865 3.12627 313209 1690318 954117063 123613138 0 0 1.53690e+08 25207.4 27 4525410 53890031 131493 29.7513 6.85838 -125627 -28.7513 0 0 33.31 54.47 38.26 6120.8 MiB 327.83 43.1256 36.2726 2241.8 MiB 62.26 88.69 -stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 434.21 vpr 5.92 GiB 36 1347 8 149 2 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6203740 3 33 52402 39411 1 28031 1542 73 54 3942 M9K auto 1506.8 MiB 95.28 323184 838612 237748 580980 19884 1853.6 MiB 66.53 0.68 17.7952 -334079 -16.7952 17.7952 0.03 0.154745 0.126064 15.9138 12.957 406168 7.75219 92691 1.76911 132469 475520 169127598 17802510 0 0 9.96430e+07 25277.3 38 3040453 30196243 80077 17.4909 17.4909 -335232 -16.4909 0 0 22.40 42.41 31.76 6058.3 MiB 168.17 27.0613 22.1224 1853.6 MiB 67.97 48.05 -stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 223.68 vpr 4.84 GiB 251 959 1 17 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5078096 55 196 20131 19956 1 8238 1228 44 33 1452 io auto 1355.0 MiB 51.43 120172 619090 201214 397879 19997 1469.9 MiB 15.63 0.17 8.13439 -80298.9 -7.13439 8.13439 0.01 0.0497327 0.0426725 5.13046 4.11514 171217 8.50641 39945 1.98455 53315 231814 61625526 5048493 0 0 3.65488e+07 25171.3 31 1360323 16115684 53903 8.22633 8.22633 -82640.4 -7.22633 0 0 10.79 18.71 13.33 4958.8 MiB 105.23 8.36643 6.63879 1463.0 MiB 66.70 15.62 -stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 431.82 vpr 5.47 GiB 255 2119 1 28 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5732792 84 171 36458 36247 3 20421 2403 62 46 2852 LAB auto 1495.6 MiB 121.86 290701 1595115 570423 937667 87025 1731.5 MiB 59.06 0.88 12.9798 -90874.5 -11.9798 4.66054 0.02 0.17766 0.134007 15.0676 12.1411 404601 11.1020 89060 2.44375 122881 589071 155442818 13359079 0 0 7.20371e+07 25258.4 18 2648236 32071807 68561 13.0244 4.46105 -93007.9 -12.0244 0 0 20.45 38.56 26.05 5598.4 MiB 152.24 20.3374 16.3586 1731.5 MiB 67.96 44.69 -stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 539.67 vpr 6.16 GiB 478 1247 1 300 4 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6457104 202 276 35125 30509 3 21749 2030 106 79 8374 M9K auto 1451.1 MiB 75.73 260809 1697966 584525 1053901 59540 2326.5 MiB 69.69 0.42 9.41173 -47933.7 -8.41173 3.39967 0.05 0.134641 0.105417 19.7532 15.4741 313986 8.94063 65931 1.87736 96858 402480 121760850 21350695 0 0 2.11299e+08 25232.8 22 3960251 43027550 63662 8.19797 3.68858 -71562.1 -7.19797 0 0 54.52 55.09 40.21 6305.8 MiB 161.98 25.3227 19.9869 2326.5 MiB 66.34 144.43 -stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 321.41 vpr 5.38 GiB 5 331 31 105 0 2 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5636340 3 2 14862 10304 26 7580 474 89 66 5874 DSP auto 1300.6 MiB 52.12 119481 175939 46938 124613 4388 1941.1 MiB 10.79 0.10 5.88056 -30914.8 -4.88056 4.13266 0.03 0.0612334 0.0539792 6.49277 5.46245 146943 9.90449 29299 1.97486 42949 181573 51132764 5390460 0 0 1.48105e+08 25213.7 14 2293428 23912154 38101 4.50499 3.70819 -37430.5 -3.50499 0 0 39.27 24.81 17.74 5504.2 MiB 114.27 8.41206 7.05794 1941.1 MiB 73.15 80.30 -stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 604.42 vpr 5.88 GiB 693 1782 25 16 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6163500 35 658 51416 37539 1 27489 2516 108 80 8640 io auto 1545.4 MiB 78.23 235688 2328796 788065 1390229 150502 2425.2 MiB 108.94 0.73 41.8548 -65336.7 -40.8548 41.8548 0.05 0.182563 0.166931 27.3116 23.6666 331843 6.64936 78001 1.56296 165823 675315 288495127 31315475 0 0 2.18145e+08 25248.3 25 4406446 50088530 83951 38.7687 38.7687 -62631.6 -37.7687 0 0 56.64 43.29 29.65 6019.0 MiB 179.17 35.858 30.9207 2425.2 MiB 66.65 145.87 -stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 490.19 vpr 5.49 GiB 753 1117 5 32 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5761892 13 740 25173 25306 1 12677 1907 117 87 10179 io auto 1397.7 MiB 56.69 158532 1337680 499407 780615 57658 2495.4 MiB 38.42 0.23 9.04712 -33408.1 -8.04712 8.7062 0.06 0.0593076 0.0526541 10.3875 8.4919 194524 7.72964 42258 1.67917 67248 314264 80325919 6195706 0 0 2.57091e+08 25257.0 16 4145714 46103256 60712 9.44565 8.02164 -41382.5 -8.44565 0 0 57.13 29.02 17.50 5626.8 MiB 125.09 13.501 10.9774 2495.4 MiB 68.37 185.29 -stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 207.70 vpr 5.16 GiB 54 661 0 40 0 1 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 5413568 2 52 16673 16662 2 12103 756 37 27 999 LAB auto 1332.8 MiB 39.94 182960 252022 64860 179647 7515 1435.5 MiB 11.93 0.15 6.11901 -21401.8 -5.11901 5.08095 0.01 0.0565371 0.0449556 4.69769 3.76454 240240 14.4124 55528 3.33121 73264 390943 149921058 16354331 0 0 2.50432e+07 25068.2 20 1108499 11576081 35204 6.84174 5.56247 -26781.1 -5.84174 0 0 7.65 15.28 11.31 5286.7 MiB 116.23 7.63028 6.11936 1392.9 MiB 61.87 7.85 -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 145.06 vpr 4.71 GiB 42 752 0 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 4934812 13 29 26295 20086 1 12536 794 39 29 1131 LAB auto 1329.3 MiB 12.27 76015 258044 53765 191160 13119 1421.9 MiB 8.56 0.11 4.99496 -5275.28 -3.99496 2.88115 0.01 0.0346645 0.0283209 2.62579 2.18191 86766 3.29997 21050 0.800593 54834 71341 33867829 3195419 0 0 2.84345e+07 25141.0 17 1246323 12347232 14132 3.54641 2.89399 -5805.4 -2.54641 0 0 8.60 11.69 7.86 4819.2 MiB 83.22 3.9986 3.31593 1386.6 MiB 62.52 10.13 -stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 915.69 vpr 5.93 GiB 964 976 19 34 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6215724 542 422 37277 26038 1 20609 1993 147 109 16023 io auto 1415.0 MiB 64.39 248974 1619266 607103 947945 64218 3187.8 MiB 75.54 0.68 8.38795 -43141.1 -7.38795 8.38795 0.09 0.115964 0.0986763 16.0502 13.7598 328246 8.80630 70845 1.90065 110233 335979 524318827 154462291 0 0 4.05153e+08 25285.7 64 5882994 65429817 45007 8.03999 7.98626 -51092.4 -7.03999 0 0 103.28 39.29 23.30 6070.0 MiB 349.45 29.8141 25.6449 3187.8 MiB 59.96 287.52 -stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 748.11 vpr 5.79 GiB 1107 719 0 0 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 6066732 403 704 15490 16194 1 8578 1826 167 124 20708 io auto 1326.2 MiB 59.68 191872 1351702 518260 795694 37748 3664.4 MiB 22.00 0.18 12.747 -23348.6 -11.747 5.87647 0.22 0.055378 0.0492417 7.51842 6.33745 234362 15.1309 39654 2.56014 41635 226559 55203082 4251380 0 0 5.23921e+08 25300.4 18 6720982 74598209 36896 11.745 5.81823 -32706.7 -10.745 0 0 136.86 30.11 13.54 5924.5 MiB 113.58 9.62012 8.10804 3664.4 MiB 61.24 384.70 -stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 199.44 vpr 4.72 GiB 35 731 0 6 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 4951472 18 17 16969 16357 1 6316 772 39 29 1131 LAB auto 1324.1 MiB 53.52 86613 255652 66755 185847 3050 1424.2 MiB 8.79 0.13 7.13037 -40670.7 -6.13037 7.13037 0.01 0.0390029 0.0309978 3.15152 2.51856 121385 7.15503 28025 1.65193 47865 258456 72672688 6504539 0 0 2.84345e+07 25141.0 37 1091666 12266607 43440 7.12455 7.12455 -43536.9 -6.12455 0 0 8.32 12.62 8.86 4835.4 MiB 93.40 6.0413 4.8334 1380.2 MiB 61.27 11.59 -stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 94.11 vpr 4.39 GiB 35 78 0 8 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 4605040 18 17 2291 2142 1 1502 121 16 12 192 LAB M9K auto 1221.1 MiB 5.74 10236 9390 1004 7372 1014 1290.4 MiB 0.82 0.01 5.31114 -4105.51 -4.31114 4.53509 0.00 0.00620249 0.00535395 0.259352 0.226533 13262 5.79633 3436 1.50175 7580 28332 7737888 644646 0 0 4.72128e+06 24590.0 42 153746 1493427 4612 4.44499 4.44499 -3952.72 -3.44499 0 0 1.88 2.19 1.68 4497.1 MiB 65.56 0.783495 0.672064 1259.5 MiB 60.88 0.58 +stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 430.27 vpr 7.22 GiB 274 1048 36 59 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7572608 22 252 53001 29054 7 22984 1419 89 66 5874 DSP auto 2999.7 MiB 77.55 248316 1021579 298715 629192 93672 3552.4 MiB 75.43 0.60 7.79847 -44076.4 -6.79847 3.16357 0.04 0.145495 0.126331 19.1685 16.7404 337990 6.38090 73939 1.39589 113486 262947 123939600 20677912 0 0 1.48102e+08 25213.2 18 3168173 32237029 53333 8.13811 2.93957 -42084.8 -7.13811 0 0 30.24 37.78 22.78 7394.9 MiB 150.02 24.6012 21.633 3552.4 MiB 61.30 11.40 +stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 423.49 vpr 6.82 GiB 36 1585 10 10 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7148500 3 33 48977 39238 1 26095 1641 54 40 2160 LAB auto 3019.2 MiB 103.15 286068 978816 295772 657268 25776 3171.0 MiB 80.85 0.83 87.9237 -89444.7 -86.9237 87.9237 0.02 0.133548 0.111652 14.7315 12.3725 377246 7.70314 89630 1.83019 136470 456181 107134305 13321542 0 0 5.45421e+07 25251.0 24 2489089 26482784 65639 72.0152 72.0152 -145316 -71.0152 0 0 10.89 30.08 16.61 6981.0 MiB 142.54 20.844 17.5112 3143.2 MiB 62.59 3.96 +stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 711.87 vpr 7.51 GiB 574 2786 16 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7875556 4 570 66175 54803 2 39221 3376 91 67 6097 io auto 3239.4 MiB 185.13 637050 2737396 996225 1655508 85663 3733.5 MiB 161.80 1.29 31.0835 -120493 -30.0835 7.14678 0.06 0.211633 0.187447 26.5121 22.2855 899864 13.5993 200525 3.03045 250269 1330369 403832098 58432790 0 0 1.53687e+08 25207.0 23 4527063 53934418 131001 31.4743 7.04434 -123107 -30.4743 0 0 31.82 48.91 25.68 7690.6 MiB 229.13 35.3927 29.9033 3733.5 MiB 54.44 12.02 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 490.17 vpr 7.44 GiB 36 1393 8 149 2 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7802588 3 33 52402 39411 1 26961 1588 73 54 3942 M9K auto 3038.9 MiB 115.22 308817 862861 247827 593176 21858 3344.5 MiB 70.28 0.75 18.2872 -344515 -17.2872 18.2872 0.04 0.144193 0.116967 14.4383 11.7329 388387 7.41281 89501 1.70823 127828 482181 86633732 10962711 0 0 9.96402e+07 25276.6 23 3049699 30612935 82279 18.1508 18.1508 -339276 -17.1508 0 0 19.96 46.42 29.95 7619.5 MiB 155.40 20.4894 16.7826 3344.5 MiB 62.62 7.54 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 264.87 vpr 6.35 GiB 251 955 1 17 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6658268 55 196 20131 19956 1 8273 1224 44 33 1452 io auto 2885.6 MiB 59.05 121891 590184 190135 382049 18000 3003.9 MiB 21.76 0.23 8.00991 -79285.3 -7.00991 8.00991 0.01 0.0550621 0.0436789 5.54087 4.43725 168265 8.35975 39603 1.96756 52203 214680 35422307 3611930 0 0 3.65459e+07 25169.4 13 1361186 16140321 53661 8.2494 8.2494 -80319.6 -7.2494 0 0 7.63 18.91 10.40 6502.2 MiB 101.02 6.87899 5.53912 2972.4 MiB 65.45 3.08 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 461.02 vpr 6.99 GiB 255 2122 1 28 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7325496 84 171 36458 36247 3 20327 2406 62 46 2852 LAB auto 3026.4 MiB 149.19 282856 1613906 577988 956437 79481 3228.2 MiB 60.47 0.55 12.7635 -89890.6 -11.7635 4.81564 0.03 0.118349 0.0946709 13.1884 10.6839 385220 10.5702 85805 2.35443 120726 551439 87035965 8547461 0 0 7.20342e+07 25257.4 15 2649463 32096142 68009 12.7106 4.59591 -89170.4 -11.7106 0 0 14.69 35.95 19.46 7153.8 MiB 138.86 16.8557 13.6644 3228.2 MiB 62.61 5.90 +stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 536.44 vpr 7.68 GiB 478 1233 1 300 4 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 8052732 202 276 35125 30509 3 21219 2016 106 79 8374 M9K auto 2979.7 MiB 92.45 275268 1593266 551386 986614 55266 3817.0 MiB 63.87 0.46 9.2665 -49067 -8.2665 3.57275 0.06 0.128588 0.0997349 17.2665 13.8123 330934 9.42322 69644 1.98309 96626 409213 76592480 17612840 0 0 2.11296e+08 25232.4 22 3960168 43100363 65824 7.92317 3.74791 -72552.8 -6.92317 0 0 43.69 57.06 35.19 7864.0 MiB 168.53 22.5205 18.1449 3817.0 MiB 63.34 20.57 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 316.30 vpr 6.89 GiB 5 333 31 105 0 2 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7222344 3 2 14862 10304 26 7583 476 89 66 5874 DSP auto 2832.3 MiB 45.71 124138 182462 49732 129080 3650 3434.9 MiB 11.57 0.11 5.88079 -31819.8 -4.88079 4.5134 0.05 0.0575387 0.0481419 6.23293 5.24991 151302 10.1983 29977 2.02056 41602 169090 28196463 3392334 0 0 1.48102e+08 25213.2 14 2293667 23918971 38105 5.43555 4.34297 -36900.7 -4.43555 0 0 31.66 30.81 19.91 7053.1 MiB 114.27 8.0475 6.8139 3434.9 MiB 67.70 13.08 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 542.79 vpr 7.40 GiB 693 1797 25 16 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7764172 35 658 51416 37539 1 27427 2531 108 80 8640 io auto 3075.8 MiB 93.41 241934 2243861 754419 1344439 145003 3917.1 MiB 110.58 0.77 41.8615 -66574.8 -40.8615 41.8615 0.09 0.160304 0.137258 23.4482 20.061 335308 6.71879 78438 1.57171 166276 681051 158387837 20955778 0 0 2.18142e+08 25247.9 25 4407721 50162159 84809 37.8945 37.8945 -63952.6 -36.8945 0 0 44.15 46.45 23.73 7582.2 MiB 178.57 31.4578 26.962 3917.1 MiB 63.71 20.46 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 387.65 vpr 7.01 GiB 753 1113 5 32 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7354908 13 740 25173 25306 1 12716 1903 117 87 10179 io auto 2928.2 MiB 67.88 151917 1239643 452352 735278 52013 3981.2 MiB 35.57 0.31 9.32912 -33745.1 -8.32912 8.97758 0.07 0.0799309 0.0699705 9.04546 7.55642 187992 7.47008 41392 1.64476 64808 295441 45317315 4493718 0 0 2.57088e+08 25256.7 13 4146271 46119125 60560 9.51895 7.86886 -41989.5 -8.51895 0 0 53.18 36.15 16.47 7182.2 MiB 123.92 11.2875 9.41327 3981.2 MiB 65.19 23.64 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 286.07 vpr 6.67 GiB 54 665 0 40 0 1 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6992700 2 52 16673 16662 2 12027 760 37 27 999 LAB auto 2863.8 MiB 48.35 185817 260785 68816 184545 7424 2969.0 MiB 17.52 0.22 6.43593 -22019.6 -5.43593 5.34219 0.01 0.0671365 0.0537497 5.45437 4.46867 243748 14.6228 55949 3.35647 70980 378754 80104321 9851562 0 0 2.50403e+07 25065.4 18 1109643 11618783 35248 6.97929 5.65113 -27162.3 -5.97929 0 0 5.11 17.57 11.32 6828.4 MiB 118.26 7.83981 6.43355 2903.7 MiB 66.65 1.88 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 191.95 vpr 6.21 GiB 42 758 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6512136 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 2859.5 MiB 15.81 72155 253216 50624 190930 11662 2954.0 MiB 12.28 0.16 5.18599 -5515.92 -4.18599 2.85104 0.01 0.0356803 0.031132 2.85133 2.36966 82362 3.13247 19973 0.759632 54490 69977 15062795 1948535 0 0 2.84316e+07 25138.5 15 1246468 12354669 14284 3.84664 2.85129 -5700.97 -2.84664 0 0 5.78 12.08 6.10 6359.5 MiB 88.58 3.91742 3.26807 2899.6 MiB 66.17 2.25 +stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 545.23 vpr 7.47 GiB 964 1119 19 34 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7832592 542 422 37277 26038 1 20403 2136 147 109 16023 io auto 2946.3 MiB 79.74 272838 1734636 659517 1007756 67363 4655.4 MiB 94.94 0.83 8.43041 -42423.1 -7.43041 8.08995 0.12 0.108337 0.0956704 15.1499 12.7644 351764 9.43725 76208 2.04454 89867 266535 93690673 14464239 0 0 4.05150e+08 25285.5 17 5915256 66794449 49681 8.39022 7.49893 -50294.9 -7.39022 0 0 83.08 50.78 21.66 7649.0 MiB 158.81 18.8518 16.0306 4655.4 MiB 64.94 40.50 +stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 445.21 vpr 7.31 GiB 1107 725 0 0 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 7666364 403 704 15490 16194 1 8534 1832 167 124 20708 io auto 2857.1 MiB 56.44 187193 1324022 523278 764997 35747 5137.0 MiB 26.81 0.24 12.7682 -23323.6 -11.7682 6.27217 0.15 0.0586464 0.0483811 7.15433 5.97963 227077 14.6605 37744 2.43683 40915 222692 34388107 3312547 0 0 5.23918e+08 25300.3 17 6721105 74589014 36638 11.3367 5.96529 -32928.6 -10.3367 0 0 108.17 38.65 9.61 7486.7 MiB 125.03 9.2614 7.7773 5137.0 MiB 64.95 52.28 +stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 247.80 vpr 6.23 GiB 35 739 0 6 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6530136 18 17 16969 16357 1 6288 780 39 29 1131 LAB auto 2855.4 MiB 65.95 84377 244832 62116 178083 4633 2954.7 MiB 10.90 0.16 7.65805 -46422.6 -6.65805 7.65805 0.01 0.0380001 0.0324758 3.26975 2.63245 117354 6.91742 28009 1.65099 42731 188939 30663841 3241611 0 0 2.84316e+07 25138.5 16 1092397 12303174 43762 7.24996 7.24996 -46266.9 -6.24996 0 0 5.81 13.06 7.12 6376.9 MiB 93.57 4.60783 3.72572 2904.9 MiB 65.30 2.17 +stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 143.49 vpr 5.89 GiB 35 78 0 8 0 0 success 9cb4943-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-47-generic x86_64 2025-02-12T18:10:28 agent-2 /home/pooladam/actions-runner/_work/vtr-verilog-to-routing/vtr-verilog-to-routing 6175112 18 17 2291 2142 1 1448 121 16 12 192 LAB M9K auto 2752.7 MiB 6.96 10189 9390 1103 7334 953 2822.6 MiB 0.78 0.01 5.3129 -4153.14 -4.3129 4.5918 0.00 0.00661338 0.00538061 0.265542 0.227477 13189 5.76442 3423 1.49607 7406 28929 4207039 458732 0 0 4.71840e+06 24575.0 16 154367 1513720 4558 4.32353 4.32353 -3831.79 -3.32353 0 0 1.05 2.34 1.56 6030.2 MiB 71.16 0.476743 0.411197 2791.2 MiB 66.66 0.13 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt index e09520ad1f6..f0282e9bf5e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_k6_frac_N8_22nm.xml single_wire.v common 1.82 vpr 73.57 MiB -1 -1 0.10 17092 1 0.02 -1 -1 30112 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75340 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 73.6 MiB 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.6 MiB 0.24 73.6 MiB 0.20 8 16 1 6.79088e+06 0 166176. 575.005 0.38 0.00152779 0.00147101 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.10 0.00 0.05 -1 -1 0.10 0.00136912 0.0013327 - fixed_k6_frac_N8_22nm.xml single_ff.v common 2.13 vpr 72.83 MiB -1 -1 0.11 17428 1 0.03 -1 -1 30100 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74580 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 72.8 MiB 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72.8 MiB 0.19 72.8 MiB 0.17 20 31 1 6.79088e+06 13472 414966. 1435.87 0.48 0.00134713 0.0012663 22510 95286 -1 39 1 2 2 247 61 0.942216 0.942216 -1.68896 -0.942216 0 0 503264. 1741.40 0.21 0.00 0.09 -1 -1 0.21 0.00158671 0.0015335 - fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 3.81 vpr 73.68 MiB -1 -1 0.40 18964 3 0.12 -1 -1 33228 -1 -1 43 99 2 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75444 99 130 240 229 1 247 274 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 73.7 MiB 0.36 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.7 MiB 0.36 73.7 MiB 0.34 32 3096 19 6.79088e+06 1.6753e+06 586450. 2029.24 1.11 0.122876 0.111163 24814 144142 -1 2911 28 730 1212 168873 64441 2.43138 2.43138 -153.888 -2.43138 0 0 744469. 2576.02 0.30 0.17 0.13 -1 -1 0.30 0.0795405 0.0727107 - fixed_k6_frac_N8_22nm.xml diffeq1.v common 14.42 vpr 75.12 MiB -1 -1 0.63 23572 15 0.47 -1 -1 34420 -1 -1 66 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76920 162 96 817 258 1 798 329 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 75.1 MiB 1.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.1 MiB 1.63 75.1 MiB 0.83 74 17094 47 6.79088e+06 2.86915e+06 1.22589e+06 4241.83 7.19 0.927094 0.854352 32590 314081 -1 14562 21 4154 11035 1472312 353034 22.5845 22.5845 -1896.41 -22.5845 0 0 1.52683e+06 5283.16 0.65 0.52 0.33 -1 -1 0.65 0.149256 0.138152 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + fixed_k6_frac_N8_22nm.xml single_wire.v common 1.34 vpr 75.71 MiB -1 -1 0.07 20608 1 0.01 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 0 3 75.7 MiB 0.48 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.40 1.4684e-05 9.512e-06 8.1482e-05 5.6821e-05 75.7 MiB 0.48 75.7 MiB 0.07 8 16 1 6.79088e+06 0 166176. 575.005 0.15 0.000912133 0.000836449 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.000776852 0.0007249 + fixed_k6_frac_N8_22nm.xml single_ff.v common 1.51 vpr 75.95 MiB -1 -1 0.08 20852 1 0.02 -1 -1 33716 -1 -1 1 2 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 24 9 1 1 7 76.0 MiB 0.47 0.00 0.930505 0.74674 -1.43836 -0.74674 0.74674 0.39 1.1513e-05 7.851e-06 8.3564e-05 6.0773e-05 76.0 MiB 0.47 76.0 MiB 0.07 20 31 1 6.79088e+06 13472 414966. 1435.87 0.24 0.000928712 0.000851847 22510 95286 -1 32 1 2 2 231 42 0.74674 0.74674 -1.43836 -0.74674 0 0 503264. 1741.40 0.03 0.00 0.08 -1 -1 0.03 0.000833737 0.000775898 + fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 2.74 vpr 76.62 MiB -1 -1 0.26 22392 3 0.07 -1 -1 37308 -1 -1 67 99 1 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78456 99 130 240 229 1 225 297 17 17 289 -1 unnamed_device -1 -1 978 866 19107 2257 1105 15745 76.6 MiB 0.61 0.00 2.26688 1.84068 -122.242 -1.84068 1.84068 0.39 0.000595647 0.000527536 0.0138425 0.0123349 76.6 MiB 0.61 76.6 MiB 0.13 34 1974 43 6.79088e+06 1.45062e+06 618332. 2139.56 0.79 0.175076 0.154945 25102 150614 -1 1739 14 569 895 60631 18120 2.0466 2.0466 -143.082 -2.0466 -0.04337 -0.04337 787024. 2723.27 0.04 0.03 0.13 -1 -1 0.04 0.0355147 0.0319235 + fixed_k6_frac_N8_22nm.xml diffeq1.v common 9.26 vpr 78.62 MiB -1 -1 0.36 26868 15 0.31 -1 -1 37472 -1 -1 47 162 0 5 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 80512 162 96 817 258 1 691 310 17 17 289 -1 unnamed_device -1 -1 7341 6689 25462 269 7038 18155 78.6 MiB 1.27 0.01 22.1608 21.0485 -1573.19 -21.0485 21.0485 0.38 0.00201699 0.00177192 0.0590804 0.052726 78.6 MiB 1.27 78.6 MiB 0.26 54 12827 26 6.79088e+06 2.61318e+06 949917. 3286.91 5.15 0.794403 0.715337 28846 232421 -1 11184 19 3449 7611 967200 252634 20.9913 20.9913 -1571.36 -20.9913 0 0 1.17392e+06 4061.99 0.06 0.26 0.21 -1 -1 0.06 0.158612 0.144189 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt index 91bac1cf221..39aa722daca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 10.66 vpr 75.07 MiB -1 -1 0.35 18416 1 0.08 -1 -1 32256 -1 -1 12 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76872 130 40 596 562 1 356 185 14 14 196 dsp_top auto 36.0 MiB 0.29 1916 35953 11702 19824 4427 75.1 MiB 0.33 0.00 5.12303 -634.784 -5.12303 5.12303 0.88 0.00199221 0.00189164 0.140924 0.132687 -1 -1 -1 -1 82 3595 10 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 4.92 0.71462 0.660858 33448 250998 -1 3301 8 676 703 150435 58622 4.57723 4.57723 -633.308 -4.57723 0 0 1.53308e+06 7821.82 0.49 0.15 0.48 -1 -1 0.49 0.0533478 0.0508037 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 10.40 vpr 75.02 MiB -1 -1 0.30 18440 1 0.07 -1 -1 32232 -1 -1 12 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76816 130 40 596 562 1 356 185 14 14 196 dsp_top auto 35.9 MiB 0.28 1916 35953 11702 19824 4427 75.0 MiB 0.32 0.00 5.12303 -634.784 -5.12303 5.12303 0.77 0.001372 0.00128332 0.125861 0.118102 -1 -1 -1 -1 82 3590 8 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 4.81 0.680937 0.627391 33448 250998 -1 3307 8 685 712 152508 59455 4.57723 4.57723 -633.101 -4.57723 0 0 1.53308e+06 7821.82 0.50 0.29 0.40 -1 -1 0.50 0.0712463 0.0684693 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.38 vpr 77.35 MiB -1 -1 0.36 22280 1 0.10 -1 -1 35580 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79208 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.18 1862 38583 13232 21153 4198 77.4 MiB 0.24 0.00 5.12303 -624.562 -5.12303 5.12303 0.45 0.00115671 0.00104931 0.13445 0.124537 -1 -1 -1 -1 64 3969 9 4.93594e+06 1.0962e+06 976140. 4980.31 5.77 0.971386 0.907233 31408 195022 -1 3606 8 821 857 201107 78801 4.57723 4.57723 -666.876 -4.57723 0 0 1.23909e+06 6321.90 0.06 0.12 0.38 -1 -1 0.06 0.0628918 0.0600921 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 7.77 vpr 77.61 MiB -1 -1 0.36 22212 1 0.08 -1 -1 35140 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79472 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.6 MiB 0.18 1862 38583 13232 21153 4198 77.6 MiB 0.37 0.00 5.12303 -624.562 -5.12303 5.12303 0.55 0.00210597 0.00194049 0.204405 0.191731 -1 -1 -1 -1 64 3993 10 4.93594e+06 1.0962e+06 976140. 4980.31 3.98 0.785401 0.735059 31408 195022 -1 3592 9 794 830 166912 64369 4.57723 4.57723 -658.916 -4.57723 0 0 1.23909e+06 6321.90 0.07 0.13 0.32 -1 -1 0.07 0.068841 0.0645644 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt index 85e095de4e0..4e167973fd7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 18.25 vpr 77.09 MiB -1 -1 0.78 20036 1 0.12 -1 -1 34336 -1 -1 23 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 78936 130 40 1147 997 1 585 196 14 14 196 dsp_top auto 38.0 MiB 0.70 2881 41164 12013 24103 5048 77.1 MiB 0.38 0.01 6.00943 -707.528 -6.00943 6.00943 0.74 0.00343703 0.00329093 0.145992 0.134216 -1 -1 -1 -1 110 5376 49 4.93594e+06 1.40315e+06 1.58123e+06 8067.52 11.44 1.37108 1.222 36820 330950 -1 4864 22 2349 2464 267041 89229 7.0711 7.0711 -772.235 -7.0711 0 0 1.96868e+06 10044.3 0.59 0.20 0.57 -1 -1 0.59 0.101693 0.0932648 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.61 vpr 79.62 MiB -1 -1 0.81 23308 1 0.11 -1 -1 37544 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81536 130 40 1147 997 1 585 196 14 14 196 dsp_top auto 40.6 MiB 0.64 2711 47992 15247 26403 6342 79.6 MiB 0.47 0.01 6.04823 -699.558 -6.04823 6.04823 0.48 0.00203985 0.00179993 0.208906 0.186707 -1 -1 -1 -1 108 5255 25 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 4.22 0.825967 0.736098 36552 325092 -1 4721 19 2233 2309 243533 83581 7.64092 7.64092 -760.756 -7.64092 0 0 1.93951e+06 9895.46 0.09 0.19 0.61 -1 -1 0.09 0.108869 0.100506 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt new file mode 100644 index 00000000000..245fb466a3d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/config.txt @@ -0,0 +1,35 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of SDC files to use +sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/multi_die/stratixiv_3d + +# Add circuits to list to sweep +circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml +arch_list_add=3d_full_OPIN_inter_die_stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map +script_params_list_add = --place_bounding_box_mode auto_bb +script_params_list_add = --place_bounding_box_mode cube_bb +script_params_list_add = --place_bounding_box_mode per_layer_bb + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt new file mode 100644 index 00000000000..22cc148a91e --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt @@ -0,0 +1,7 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 83.45 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421664 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.4 MiB 12.25 180137 58272 230944 40790 173771 16383 1388.3 MiB 10.48 0.15 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0444933 0.0387879 3.15031 2.6241 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 12.21 -1 -1 1388.3 MiB 10.28 4.91142 4.17713 1388.3 MiB -1 16.75 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 85.51 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421424 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 12.33 180137 58272 230944 40790 173771 16383 1388.1 MiB 10.48 0.14 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.0434223 0.0377288 3.13504 2.6098 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 13.53 -1 -1 1388.1 MiB 10.72 4.93468 4.19984 1388.1 MiB -1 17.21 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 86.05 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1421572 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 12.02 186170 63595 242080 43083 181450 17547 1388.3 MiB 12.05 0.17 5.04678 4.86192 -4242.28 -3.86192 2.41884 0.05 0.051916 0.0457829 3.35985 2.75261 103428 8.31615 32795 2.63689 27768 38066 44034475 9785894 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 5.18643 2.65983 -5392.13 -4.18642 0 0 13.06 -1 -1 1388.3 MiB 9.86 5.14157 4.32891 1388.3 MiB -1 18.69 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_auto_bb 57.03 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245688 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.9 MiB 11.85 186170 63157 219808 34278 166444 19086 1216.5 MiB 10.07 0.18 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0545904 0.0489007 2.99902 2.51676 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.46 -1 -1 1216.5 MiB 4.58 4.95133 4.23051 1216.5 MiB -1 1.96 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_cube_bb 56.04 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245528 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.7 MiB 11.88 180137 61714 223520 36703 169137 17680 1216.3 MiB 10.63 0.16 5.41016 4.96403 -5546.44 -3.96403 2.84288 0.01 0.0440263 0.0385965 3.36781 2.8222 75346 6.05821 18897 1.51942 26061 36573 12725206 1711712 0 0 2.60031e+07 21349.0 14 354380 4692432 -1 5.08769 2.56235 -5100.1 -4.08769 0 0 7.77 -1 -1 1216.3 MiB 4.84 5.1781 4.41964 1216.3 MiB -1 1.92 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common_--place_bounding_box_mode_per_layer_bb 58.79 vpr 1.19 GiB 42 758 0 0 0 0 success v8.0.0-12389-g509012469-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 10.3.0 on Linux-4.15.0-213-generic x86_64 2025-04-15T09:49:51 betzgrp-wintermute.eecg.utoronto.ca /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1245324 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1073.5 MiB 11.84 186170 63157 219808 34278 166444 19086 1216.1 MiB 10.25 0.14 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.01 0.0422071 0.0368357 2.98723 2.48631 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 9.89 -1 -1 1216.1 MiB 4.79 4.83395 4.11932 1216.1 MiB -1 1.80 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt index 5e82ce20db9..abc45194ec7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 2.06 vpr 70.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71744 130 150 1169 1319 1 886 363 12 12 144 clb auto 29.9 MiB 1.33 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00617255 0.00566712 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 2.11 vpr 69.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71096 130 150 1216 1366 1 933 370 12 12 144 clb auto 29.7 MiB 1.36 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00673229 0.00602451 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 2.31 vpr 72.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74048 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.2 MiB 1.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00628067 0.00572957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.95 vpr 72.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73772 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.4 MiB 1.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00606424 0.00546366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index e7e15672aec..94e710b87f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.59 vpr 63.68 MiB -1 -1 0.88 23332 5 0.19 -1 -1 33328 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65204 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.13 146 398 72 298 28 63.7 MiB 0.05 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.00056264 0.000520569 0.00752147 0.00699209 -1 -1 -1 -1 130 4.06250 54 1.68750 215 509 15144 2919 646728 646728 138825. 3856.24 24 3164 19284 -1 2.05191 2.05191 -93.8814 -2.05191 0 0 0.02 -1 -1 63.7 MiB 0.05 0.0383425 0.0343799 63.7 MiB -1 0.02 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.12 vpr 66.62 MiB -1 -1 0.87 22944 4 0.17 -1 -1 33248 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68220 11 2 303 283 2 78 28 7 7 49 clb auto 27.0 MiB 0.35 264 1036 209 767 60 66.6 MiB 0.05 0.00 2.03811 -163.536 -2.03811 1.90043 0.00 0.000979369 0.000882501 0.0285292 0.0262389 -1 -1 -1 -1 252 3.50000 103 1.43056 122 199 4265 1218 1.07788e+06 808410 219490. 4479.39 12 5100 32136 -1 2.11264 1.93889 -160.659 -2.11264 0 0 0.04 -1 -1 66.6 MiB 0.04 0.0622 0.0573011 66.6 MiB -1 0.05 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.05 vpr 66.01 MiB -1 -1 0.86 26896 5 0.23 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67592 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.0 MiB 0.02 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000412775 0.000360271 0.0136111 0.012803 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.04 -1 -1 66.0 MiB 0.03 0.0339384 0.0288063 66.0 MiB -1 0.00 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.21 vpr 69.14 MiB -1 -1 0.76 26288 4 0.18 -1 -1 36060 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70796 11 2 303 283 2 78 28 7 7 49 clb auto 29.6 MiB 0.27 285 784 175 539 70 69.1 MiB 0.05 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000707376 0.000615193 0.0194274 0.0173585 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 69.1 MiB 0.03 0.0450009 0.0414951 69.1 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt index 36eb5abce3a..7f41d46c079 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 5.66 vpr 65.89 MiB -1 -1 0.43 18980 3 0.13 -1 -1 33368 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67472 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.26 783 1293 269 877 147 65.9 MiB 0.17 0.00 1.86362 -117.589 -1.86362 1.86362 0.38 0.00100487 0.000938659 0.00647195 0.00625967 -1 -1 -1 -1 34 1729 21 5.66058e+06 4.21279e+06 293002. 2034.74 1.97 0.304859 0.274689 12094 55633 -1 1447 11 494 759 44038 15434 1.98889 1.98889 -143.496 -1.98889 -0.113193 -0.0844279 360780. 2505.42 0.12 0.08 0.06 -1 -1 0.12 0.0336886 0.0313908 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.75 vpr 67.64 MiB -1 -1 0.42 22416 3 0.08 -1 -1 36896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69264 99 130 344 474 1 227 298 12 12 144 clb auto 28.8 MiB 0.22 846 1293 248 869 176 67.6 MiB 0.10 0.00 1.87518 -117.076 -1.87518 1.87518 0.33 0.000961535 0.000869555 0.00580355 0.00550747 -1 -1 -1 -1 38 1541 12 5.66058e+06 4.21279e+06 319130. 2216.18 1.43 0.231487 0.210357 12522 62564 -1 1321 9 430 670 30619 10041 1.9175 1.9175 -131.199 -1.9175 -0.126268 -0.104429 406292. 2821.48 0.02 0.04 0.09 -1 -1 0.02 0.0283489 0.0264305 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/config.txt new file mode 100644 index 00000000000..a8e217b51fd --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_detailed_placer annealer --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt new file mode 100644 index 00000000000..f90dc9de594 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.63 vpr 75.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77436 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.56 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00332256 0.00272635 0.0920151 0.0793873 75.6 MiB 3.56 75.6 MiB 2.42 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.47 0.288973 0.25613 75.6 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.81 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78036 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.93 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00365979 0.00331889 0.047619 0.043593 76.2 MiB 0.93 76.2 MiB 0.59 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.37 -1 -1 76.2 MiB 0.25 0.188446 0.174077 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 11.93 vpr 105.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108360 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 9.23 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.00660438 0.00519941 0.309592 0.257376 105.8 MiB 9.23 105.8 MiB 4.50 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.18 -1 -1 105.8 MiB 0.93 0.709043 0.615207 105.8 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.73 vpr 76.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78628 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.59 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.09 0.0040653 0.00347069 0.103188 0.0899686 76.8 MiB 3.59 76.8 MiB 2.31 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.37 -1 -1 76.8 MiB 0.47 0.321818 0.287107 76.8 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/config.txt new file mode 100644 index 00000000000..358e9022f78 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_full_legalizer appack --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..91c3630a8a8 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.88 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.73 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00371221 0.00305644 0.097355 0.0840965 75.4 MiB 3.73 75.4 MiB 2.65 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.4 MiB 0.50 0.299102 0.265267 75.4 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.04 vpr 75.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.0 MiB 1.04 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00356373 0.00322411 0.0543939 0.0472155 76.0 MiB 1.04 76.0 MiB 0.69 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.39 -1 -1 76.0 MiB 0.32 0.22263 0.205375 76.0 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 14.50 vpr 105.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108280 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 11.89 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.0066784 0.00535245 0.30231 0.252682 105.7 MiB 11.89 105.7 MiB 7.07 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.11 -1 -1 105.7 MiB 0.94 0.707357 0.615217 105.7 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.83 vpr 76.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78264 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.4 MiB 3.68 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00384755 0.00327555 0.103123 0.0900634 76.4 MiB 3.68 76.4 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.4 MiB 0.48 0.323332 0.288275 76.4 MiB -1 0.11 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt new file mode 100644 index 00000000000..914133ac93b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_partial_legalizer bipartitioning --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..e03594be3ed --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.66 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.54 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00377685 0.0031064 0.0971738 0.0840095 75.4 MiB 3.54 75.4 MiB 2.44 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.35 -1 -1 75.4 MiB 0.49 0.299893 0.266532 75.4 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.87 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.95 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.12 0.00361228 0.00324116 0.0472811 0.0432415 76.2 MiB 0.95 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.40 -1 -1 76.2 MiB 0.27 0.192439 0.178374 76.2 MiB -1 0.12 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.92 vpr 105.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108344 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 13.27 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.27 0.0064285 0.00513075 0.474187 0.399734 105.8 MiB 13.27 105.8 MiB 7.54 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.15 -1 -1 105.8 MiB 0.91 0.870133 0.753188 105.8 MiB -1 0.27 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.70 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.7 MiB 3.57 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00387961 0.00328771 0.108944 0.0952913 76.7 MiB 3.57 76.7 MiB 2.29 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.32 -1 -1 76.7 MiB 0.51 0.337895 0.301103 76.7 MiB -1 0.10 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt new file mode 100644 index 00000000000..75c1001ec87 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_partial_legalizer flow-based --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..260e0e2c056 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 11.76 vpr 75.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77216 9 19 897 28 0 575 109 16 16 256 -1 mcnc_medium -1 -1 7102 6246 3749 356 2360 1033 75.4 MiB 10.60 0.01 5.59875 5.15754 -83.6777 -5.15754 nan 0.09 0.00367809 0.00303729 0.0800582 0.0701494 75.4 MiB 10.60 75.4 MiB 2.58 9765 17.0122 2613 4.55226 4147 20677 658214 114215 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.35541 nan -88.358 -5.35541 0 0 0.32 -1 -1 75.4 MiB 0.48 0.288075 0.253539 75.4 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.95 vpr 76.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 57 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77892 256 245 954 501 0 585 558 22 22 484 -1 mcnc_large -1 -1 7568 7468 23518 202 3225 20091 76.1 MiB 1.06 0.02 4.58215 4.06321 -789.076 -4.06321 nan 0.17 0.00395794 0.00352194 0.0546633 0.0494666 76.1 MiB 1.06 76.1 MiB 0.64 10448 17.8598 2871 4.90769 2610 5820 337031 73978 2.15576e+07 3.07196e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.29926 nan -860.162 -4.29926 0 0 0.37 -1 -1 76.1 MiB 0.29 0.21912 0.199431 76.1 MiB -1 0.17 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 34.79 vpr 105.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 284 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108284 10 10 2659 20 0 1371 304 22 22 484 -1 mcnc_large -1 -1 32736 26176 50333 12484 33100 4749 105.7 MiB 32.12 0.02 8.62387 6.83404 -65.9282 -6.83404 nan 0.15 0.0053571 0.00415525 0.333874 0.272699 105.7 MiB 32.12 105.7 MiB 4.39 39078 28.5033 10004 7.29686 9032 54400 2294214 310826 2.15576e+07 1.53059e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.03175 nan -67.1956 -7.03175 0 0 1.19 -1 -1 105.7 MiB 0.86 0.709263 0.607527 105.7 MiB -1 0.15 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 12.51 vpr 76.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78100 41 35 1006 76 0 566 161 16 16 256 -1 mcnc_medium -1 -1 7257 6649 5842 273 2922 2647 76.3 MiB 11.37 0.02 5.58018 4.9431 -137.944 -4.9431 nan 0.09 0.00696141 0.00638215 0.115593 0.094552 76.3 MiB 11.37 76.3 MiB 2.39 10043 17.7438 2739 4.83922 3885 20440 636556 113525 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.06598 nan -144.027 -5.06598 0 0 0.35 -1 -1 76.3 MiB 0.47 0.340764 0.297617 76.3 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt new file mode 100644 index 00000000000..48b5feea72d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route --ap_analytical_solver lp-b2b + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt new file mode 100644 index 00000000000..e9dd4dbf472 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.77 vpr 75.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77552 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.7 MiB 3.65 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00374471 0.00311178 0.0942637 0.0815881 75.7 MiB 3.65 75.7 MiB 2.54 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.7 MiB 0.49 0.296978 0.264335 75.7 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.14 0.0035648 0.00318679 0.0499558 0.0460383 76.2 MiB 0.98 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.2 MiB 0.27 0.197871 0.183716 76.2 MiB -1 0.14 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.47 vpr 105.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108040 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.5 MiB 12.86 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.29 0.0116739 0.00965721 0.534688 0.455619 105.5 MiB 12.86 105.5 MiB 7.17 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.12 -1 -1 105.5 MiB 1.62 1.25142 1.10117 105.5 MiB -1 0.28 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.88 vpr 76.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78644 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.64 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00418085 0.00352692 0.113479 0.0974767 76.8 MiB 3.64 76.8 MiB 2.34 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.8 MiB 0.56 0.365085 0.323172 76.8 MiB -1 0.10 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt index 97f45b6c51f..c179a99eb71 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 17.89 vpr 72.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 113 9 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74000 9 19 897 28 0 861 141 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 72.3 MiB 7.61 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72.3 MiB 7.61 72.3 MiB 1.79 15611 18.1735 4293 4.99767 8307 35569 1513043 269803 1.05632e+07 6.09002e+06 1.26944e+06 4958.75 25 28900 206586 -1 6.2156 nan -103.761 -6.2156 0 0 0.25 -1 -1 72.3 MiB 0.57 0.174543 0.155743 72.3 MiB -1 0.31 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 5.93 vpr 73.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 168 256 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75248 256 245 954 501 0 934 669 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 73.5 MiB 1.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.5 MiB 1.37 73.5 MiB 1.31 14674 15.7109 3946 4.22484 4204 10388 463073 94185 2.15576e+07 9.05419e+06 1.49107e+06 3080.73 15 47664 245996 -1 5.16547 nan -949.23 -5.16547 0 0 0.24 -1 -1 73.5 MiB 0.33 0.134699 0.127277 73.5 MiB -1 0.78 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 89.28 vpr 101.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 378 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 104144 10 10 2659 20 0 2595 398 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 101.7 MiB 38.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 101.7 MiB 38.46 101.7 MiB 4.76 69814 26.9033 18438 7.10520 21388 82112 8636123 1705637 2.15576e+07 2.03719e+07 3.51389e+06 7260.09 30 64568 594370 -1 8.65166 nan -83.0393 -8.65166 0 0 0.78 -1 -1 101.7 MiB 2.76 0.603303 0.529989 101.7 MiB -1 0.89 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 18.93 vpr 73.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 137 41 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75200 41 35 1006 76 0 966 213 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 73.4 MiB 7.75 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.4 MiB 7.75 73.4 MiB 2.26 16234 16.8054 4428 4.58385 7333 31283 1130829 193699 1.05632e+07 7.38348e+06 1.26944e+06 4958.75 18 28900 206586 -1 6.06719 nan -179.594 -6.06719 0 0 0.29 -1 -1 73.4 MiB 0.59 0.225217 0.206578 73.4 MiB -1 0.44 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.02 vpr 75.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77392 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.80 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.10 0.00366255 0.00300248 0.0988722 0.0856346 75.6 MiB 3.80 75.6 MiB 2.67 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.58 0.329873 0.296269 75.6 MiB -1 0.10 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77908 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.1 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00361625 0.00323438 0.0481778 0.0440548 76.1 MiB 0.98 76.1 MiB 0.62 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.1 MiB 0.27 0.193703 0.179342 76.1 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.93 vpr 105.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108228 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 13.43 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.25 0.0114469 0.00942196 0.523317 0.437298 105.7 MiB 13.43 105.7 MiB 7.67 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.08 -1 -1 105.7 MiB 1.54 1.21056 1.05802 105.7 MiB -1 0.25 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.95 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.9 MiB 3.70 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00501429 0.0044287 0.113755 0.0975648 76.9 MiB 3.70 76.9 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.9 MiB 0.54 0.357802 0.31714 76.9 MiB -1 0.11 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/config.txt new file mode 100644 index 00000000000..dbc8f9dcd38 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_full_legalizer naive --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..5bcf12189e9 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.03 vpr 75.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 114 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77596 9 19 897 28 0 606 142 16 16 256 -1 mcnc_medium -1 -1 6550 6536 3472 155 2648 669 75.8 MiB 3.88 0.01 5.7154 5.4597 -89.3112 -5.4597 nan 0.10 0.00370216 0.00307222 0.0661479 0.0591146 75.8 MiB 3.88 75.8 MiB 2.88 10481 17.3240 2782 4.59835 4539 23483 740476 125213 1.05632e+07 6.14392e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72947 nan -94.1462 -5.72947 0 0 0.32 -1 -1 75.8 MiB 0.50 0.310788 0.282654 75.8 MiB -1 0.10 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.32 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 179 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78468 256 245 954 501 0 742 680 22 22 484 -1 mcnc_large -1 -1 9274 7572 60460 2284 20333 37843 76.6 MiB 2.36 0.02 5.23911 4.2903 -840.323 -4.2903 nan 0.13 0.00384619 0.00344153 0.09353 0.0842417 76.6 MiB 2.36 76.6 MiB 1.70 11049 14.8908 3078 4.14825 2733 6987 297544 68761 2.15576e+07 9.64703e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.65189 nan -884.263 -4.65189 0 0 0.41 -1 -1 76.6 MiB 0.28 0.244915 0.224675 76.6 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.12 vpr 106.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108712 10 10 2659 20 0 1430 382 22 22 484 -1 mcnc_large -1 -1 30097 26681 50242 8485 37651 4106 106.2 MiB 14.49 0.06 9.5895 7.11784 -67.5602 -7.11784 nan 0.29 0.0120588 0.0101618 0.577448 0.487406 106.2 MiB 14.49 106.2 MiB 8.21 40770 28.5105 10462 7.31608 8938 61030 2640427 332495 2.15576e+07 1.95096e+07 3.51389e+06 7260.09 17 64568 594370 -1 7.68543 nan -70.9452 -7.68543 0 0 1.09 -1 -1 106.2 MiB 1.70 1.23429 1.08029 106.2 MiB -1 0.29 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.65 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 124 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 665 200 16 16 256 -1 mcnc_medium -1 -1 8699 7144 11296 577 6471 4248 76.9 MiB 4.33 0.02 6.42009 5.14527 -151.192 -5.14527 nan 0.09 0.0040038 0.00343256 0.111382 0.0964207 76.9 MiB 4.33 76.9 MiB 3.06 11808 17.7564 3134 4.71278 5035 27959 918932 152826 1.05632e+07 6.68286e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.4847 nan -160.203 -5.4847 0 0 0.34 -1 -1 76.9 MiB 0.64 0.362116 0.322037 76.9 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/config.txt new file mode 100755 index 00000000000..7678dea6b00 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/config.txt @@ -0,0 +1,51 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=boundtop.v +circuit_list_add=ch_intrinsics.v +circuit_list_add=or1200.v +circuit_list_add=spree.v +circuit_list_add=stereovision3.v + +# Constrain the circuits to their devices +circuit_constraint_list_add=(stereovision3.v, device=vtr_extra_small) +circuit_constraint_list_add=(ch_intrinsics.v, device=vtr_extra_small) +circuit_constraint_list_add=(spree.v, device=vtr_extra_small) +circuit_constraint_list_add=(boundtop.v, device=vtr_extra_small) +circuit_constraint_list_add=(or1200.v, device=vtr_small) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(stereovision3.v, route_chan_width=44) +circuit_constraint_list_add=(ch_intrinsics.v, route_chan_width=52) +circuit_constraint_list_add=(spree.v, route_chan_width=78) +circuit_constraint_list_add=(boundtop.v, route_chan_width=50) +circuit_constraint_list_add=(or1200.v, route_chan_width=118) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-track_memory_usage -crit_path_router_iterations 100 --analytical_place --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt new file mode 100644 index 00000000000..e8dd91ee6ae --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt @@ -0,0 +1,6 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 25.85 vpr 83.03 MiB -1 -1 18.57 47636 3 1.01 -1 -1 38980 -1 -1 48 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85020 196 193 800 0 1 594 438 20 20 400 -1 vtr_extra_small -1 -1 4169 3142 106806 24519 69152 13135 83.0 MiB 3.45 0.01 2.78642 2.3599 -1119.38 -2.3599 2.3599 0.11 0.00336886 0.00290601 0.267623 0.235425 83.0 MiB 3.45 83.0 MiB 1.54 5164 8.82735 1542 2.63590 1808 2713 166829 48700 2.07112e+07 3.13491e+06 1.26946e+06 3173.65 11 38988 203232 -1 2.79177 2.79177 -1205.37 -2.79177 0 0 0.33 -1 -1 83.0 MiB 0.20 0.427611 0.384897 83.0 MiB -1 0.11 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.71 vpr 77.02 MiB -1 -1 0.44 22136 3 0.13 -1 -1 37044 -1 -1 68 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78864 99 130 264 0 1 227 298 20 20 400 -1 vtr_extra_small -1 -1 1534 732 61988 20558 27121 14309 77.0 MiB 1.17 0.01 1.84094 1.63182 -117.029 -1.63182 1.63182 0.10 0.00116098 0.00102609 0.0719437 0.0636329 77.0 MiB 1.17 77.0 MiB 0.48 1289 7.67262 408 2.42857 432 671 35594 10787 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 12 39388 210115 -1 2.0326 2.0326 -137.711 -2.0326 0 0 0.32 -1 -1 77.0 MiB 0.12 0.146262 0.115522 77.0 MiB -1 0.10 + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.09 vpr 132.19 MiB -1 -1 6.50 65292 8 5.27 -1 -1 44656 -1 -1 246 385 2 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 135364 385 362 3324 0 1 2378 996 30 30 900 -1 vtr_small -1 -1 45961 31243 503168 167206 308523 27439 132.2 MiB 27.49 0.08 11.3485 9.24445 -10104.3 -9.24445 9.24445 0.52 0.0110533 0.00983869 1.90464 1.67809 132.2 MiB 27.49 132.2 MiB 14.11 42437 17.9590 11048 4.67541 10359 33405 1843617 333376 4.8774e+07 1.47499e+07 6.56785e+06 7297.61 17 120772 1084977 -1 9.50495 9.50495 -10508.2 -9.50495 0 0 2.27 -1 -1 132.2 MiB 0.99 2.49904 2.2274 132.2 MiB -1 0.52 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.73 vpr 86.61 MiB -1 -1 3.85 35472 16 0.66 -1 -1 39332 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88684 45 32 936 0 1 764 142 20 20 400 -1 vtr_extra_small -1 -1 7941 6580 16792 4505 10418 1869 86.6 MiB 7.12 0.02 11.8934 10.8778 -6730.96 -10.8778 10.8778 0.15 0.00604523 0.0052746 0.299411 0.249607 86.6 MiB 7.12 86.6 MiB 4.84 11265 14.8029 2859 3.75690 3304 9224 705116 168424 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 16 44576 305072 -1 11.1238 11.1238 -7296.13 -11.1238 0 0 0.55 -1 -1 86.6 MiB 0.49 0.557197 0.483674 86.6 MiB -1 0.15 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.92 vpr 76.71 MiB -1 -1 0.85 26400 4 0.19 -1 -1 36732 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78556 11 2 140 0 2 80 28 20 20 400 -1 vtr_extra_small -1 -1 371 277 994 274 621 99 76.7 MiB 0.79 0.00 2.14417 2.10685 -170.205 -2.10685 1.95087 0.09 0.000829747 0.000696435 0.0253099 0.0218497 76.7 MiB 0.79 76.7 MiB 0.47 484 6.54054 125 1.68919 154 271 5642 1534 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.24362 1.99822 -177.023 -2.24362 0 0 0.28 -1 -1 76.7 MiB 0.04 0.058266 0.0520206 76.7 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/config.txt new file mode 100644 index 00000000000..bb79ed9f837 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif +# circuit_list_add=ex1010.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +# circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +# circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +# circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_detailed_placer none --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt new file mode 100644 index 00000000000..9155e1a0c29 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.37 vpr 75.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 75.7 MiB 2.52 10470 18.5638 2823 5.00532 4441 21451 721238 120368 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.44204 nan -88.1999 -5.44204 0 0 0.32 -1 -1 75.7 MiB 0.45 0.190621 0.172257 75.7 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.70 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78028 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 76.2 MiB 0.61 10067 17.2380 2785 4.76884 2224 4785 262051 58317 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 14 47664 245996 -1 5.09713 nan -915.356 -5.09713 0 0 0.38 -1 -1 76.2 MiB 0.25 0.146815 0.136123 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.28 vpr 76.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78496 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 76.7 MiB 2.27 10759 18.7766 2936 5.12391 3972 20025 643838 113062 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.52727 nan -151.75 -5.52727 0 0 0.34 -1 -1 76.7 MiB 0.46 0.206081 0.184898 76.7 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt new file mode 100644 index 00000000000..8e0fbf318b0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route --ap_analytical_solver qp-hybrid + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt new file mode 100644 index 00000000000..bd1a356f7b3 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.48 vpr 75.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77452 9 19 897 28 0 613 107 16 16 256 -1 mcnc_medium -1 -1 7227 6446 4661 444 2922 1295 75.6 MiB 3.30 0.01 5.83587 5.20235 -84.7514 -5.20235 nan 0.09 0.00365365 0.00308713 0.0953072 0.0828485 75.6 MiB 3.30 75.6 MiB 2.61 9964 16.2810 2709 4.42647 4690 20859 701687 124089 1.05632e+07 4.25763e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.47836 nan -87.8661 -5.47836 0 0 0.35 -1 -1 75.6 MiB 0.51 0.314162 0.28034 75.6 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.82 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78032 256 245 954 501 0 598 557 22 22 484 -1 mcnc_large -1 -1 8430 8247 28037 277 4264 23496 76.2 MiB 0.95 0.02 5.00844 4.05195 -786.983 -4.05195 nan 0.13 0.00372964 0.0033122 0.0643989 0.0586623 76.2 MiB 0.95 76.2 MiB 0.58 10883 18.1990 2937 4.91137 2442 5565 332488 69751 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.40791 nan -837.951 -4.40791 0 0 0.37 -1 -1 76.2 MiB 0.26 0.206289 0.19121 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.95 vpr 105.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108108 10 10 2659 20 0 1500 308 22 22 484 -1 mcnc_large -1 -1 33647 26777 51219 12453 33951 4815 105.6 MiB 12.21 0.05 7.95426 6.65363 -64.7441 -6.65363 nan 0.32 0.01158 0.00952696 0.683148 0.577318 105.6 MiB 12.21 105.6 MiB 8.23 39550 26.3667 10138 6.75867 10136 56388 2554636 337283 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.10986 nan -67.2122 -7.10986 0 0 1.12 -1 -1 105.6 MiB 1.79 1.41673 1.23449 105.6 MiB -1 0.32 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 3.96 vpr 76.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78624 41 35 1006 76 0 665 161 16 16 256 -1 mcnc_medium -1 -1 7612 6958 7590 343 3947 3300 76.8 MiB 2.84 0.02 6.23108 5.15201 -145.389 -5.15201 nan 0.09 0.00454121 0.00387629 0.099122 0.086103 76.8 MiB 2.84 76.8 MiB 2.13 10685 16.0677 2885 4.33835 4384 18462 592965 106217 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.45169 nan -154.246 -5.45169 0 0 0.32 -1 -1 76.8 MiB 0.51 0.354223 0.314944 76.8 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/config.txt new file mode 100644 index 00000000000..a45e6a65de4 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route --allow_unrelated_clustering on + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt new file mode 100644 index 00000000000..353d272ff5e --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.96 vpr 75.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77136 9 19 897 28 0 571 109 16 16 256 -1 mcnc_medium -1 -1 6849 6197 3749 306 2447 996 75.3 MiB 3.80 0.01 5.6777 5.15854 -84.4388 -5.15854 nan 0.12 0.00372518 0.00308527 0.0851251 0.0744623 75.3 MiB 3.80 75.3 MiB 2.72 9547 16.7491 2591 4.54561 4007 19117 612422 105847 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.57046 nan -89.3939 -5.57046 0 0 0.36 -1 -1 75.3 MiB 0.45 0.290389 0.260271 75.3 MiB -1 0.12 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.92 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78044 256 245 954 501 0 584 556 22 22 484 -1 mcnc_large -1 -1 7414 7336 16551 117 1750 14684 76.2 MiB 0.96 0.02 4.79868 3.95956 -780.296 -3.95956 nan 0.14 0.0037776 0.00334019 0.0431145 0.0394451 76.2 MiB 0.96 76.2 MiB 0.63 10156 17.3904 2785 4.76884 2499 5829 309976 67350 2.15576e+07 2.96417e+06 1.49107e+06 3080.73 17 47664 245996 -1 4.43922 nan -858.538 -4.43922 0 0 0.40 -1 -1 76.2 MiB 0.31 0.225991 0.20914 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.50 vpr 105.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 263 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108088 10 10 2659 20 0 1335 283 22 22 484 -1 mcnc_large -1 -1 29142 24368 34619 6112 24966 3541 105.6 MiB 14.79 0.04 8.99039 6.64595 -64.2305 -6.64595 nan 0.30 0.011351 0.00921126 0.534655 0.453947 105.6 MiB 14.79 105.6 MiB 8.92 36909 27.6472 9531 7.13933 8973 57196 2436221 318880 2.15576e+07 1.41741e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.07899 nan -66.0192 -7.07899 0 0 1.11 -1 -1 105.6 MiB 1.75 1.29851 1.13315 105.6 MiB -1 0.30 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.12 vpr 76.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78196 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7414 6419 7538 405 3643 3490 76.4 MiB 3.99 0.01 5.66659 5.10396 -142.048 -5.10396 nan 0.09 0.00395858 0.00331812 0.0974473 0.0845959 76.4 MiB 3.99 76.4 MiB 2.72 9920 17.3124 2710 4.72949 3957 20035 633461 111527 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.31293 nan -148.764 -5.31293 0 0 0.36 -1 -1 76.4 MiB 0.47 0.311907 0.278187 76.4 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/config.txt index 2f77b824751..f5bbc150963 100755 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/config.txt @@ -18,7 +18,7 @@ arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml # Add circuits to list to sweep circuit_list_add=boundtop.v circuit_list_add=ch_intrinsics.v -circuit_list_add=or1200.v +# circuit_list_add=or1200.v circuit_list_add=spree.v circuit_list_add=stereovision3.v @@ -27,14 +27,14 @@ circuit_constraint_list_add=(stereovision3.v, device=vtr_extra_small) circuit_constraint_list_add=(ch_intrinsics.v, device=vtr_extra_small) circuit_constraint_list_add=(spree.v, device=vtr_extra_small) circuit_constraint_list_add=(boundtop.v, device=vtr_extra_small) -circuit_constraint_list_add=(or1200.v, device=vtr_small) +# circuit_constraint_list_add=(or1200.v, device=vtr_small) # Constrain the IOs circuit_constraint_list_add=(stereovision3.v, constraints=../../../../constraints/stereovision3_io_constraint.xml) circuit_constraint_list_add=(ch_intrinsics.v, constraints=../../../../constraints/ch_intrinsics_io_constraint.xml) circuit_constraint_list_add=(spree.v, constraints=../../../../constraints/spree_io_constraint.xml) circuit_constraint_list_add=(boundtop.v, constraints=../../../../constraints/boundtop_io_constraint.xml) -circuit_constraint_list_add=(or1200.v, constraints=../../../../constraints/or1200_io_constraint.xml) +# circuit_constraint_list_add=(or1200.v, constraints=../../../../constraints/or1200_io_constraint.xml) # Constrain the circuits to their channel widths # 1.3 * minW @@ -42,7 +42,7 @@ circuit_constraint_list_add=(stereovision3.v, route_chan_width=44) circuit_constraint_list_add=(ch_intrinsics.v, route_chan_width=52) circuit_constraint_list_add=(spree.v, route_chan_width=78) circuit_constraint_list_add=(boundtop.v, route_chan_width=50) -circuit_constraint_list_add=(or1200.v, route_chan_width=118) +# circuit_constraint_list_add=(or1200.v, route_chan_width=118) # Parse info and how to parse parse_file=vpr_fixed_chan_width.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt index 01136ed182a..d7bb035e33d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt @@ -1,6 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 25.49 vpr 80.19 MiB -1 -1 18.42 46348 3 0.86 -1 -1 35680 -1 -1 79 196 2 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 82116 196 193 800 389 1 770 470 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 80.2 MiB 1.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80.2 MiB 1.84 80.2 MiB 1.78 9940 13.0618 2693 3.53876 2581 4860 309537 77921 2.07112e+07 5.35363e+06 1.26946e+06 3173.65 17 38988 203232 -1 3.97958 3.97958 -1577.97 -3.97958 0 0 0.21 -1 -1 80.2 MiB 0.27 0.168973 0.157491 80.2 MiB -1 0.35 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 4.99 vpr 74.65 MiB -1 -1 0.39 19048 3 0.16 -1 -1 33328 -1 -1 43 99 4 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76440 99 130 240 229 1 245 276 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 74.6 MiB 0.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.6 MiB 0.74 74.6 MiB 0.55 2337 12.5645 646 3.47312 478 786 47927 11655 2.07112e+07 4.50944e+06 1.31074e+06 3276.84 17 39388 210115 -1 2.7949 2.7949 -157.904 -2.7949 0 0 0.23 -1 -1 74.6 MiB 0.08 0.0477832 0.0442404 74.6 MiB -1 0.59 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 98.01 vpr 129.75 MiB -1 -1 6.86 63268 8 3.92 -1 -1 41140 -1 -1 389 385 4 1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 132868 385 362 3324 747 1 3234 1141 30 30 900 -1 vtr_small -1 -1 -1 -1 -1 -1 -1 129.8 MiB 36.86 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 129.8 MiB 36.86 129.8 MiB 7.32 78006 24.2330 20094 6.24231 16800 53011 4072067 673498 4.8774e+07 2.35528e+07 6.56785e+06 7297.61 18 120772 1084977 -1 13.1891 13.1891 -14048.3 -13.1891 0 0 1.37 -1 -1 129.8 MiB 1.69 0.748616 0.698526 129.8 MiB -1 1.67 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 34.66 vpr 83.23 MiB -1 -1 3.83 32732 16 0.61 -1 -1 34984 -1 -1 81 45 5 1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85228 45 32 936 77 1 909 164 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 83.2 MiB 12.99 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83.2 MiB 12.99 83.2 MiB 3.72 18303 20.2020 4779 5.27483 4457 12845 1130075 256506 2.07112e+07 7.50141e+06 1.91495e+06 4787.38 16 44576 305072 -1 16.4662 16.4662 -8382.09 -16.4662 0 0 0.35 -1 -1 83.2 MiB 0.43 0.172284 0.155775 83.2 MiB -1 0.53 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 5.78 vpr 73.51 MiB -1 -1 0.88 22948 4 0.18 -1 -1 33064 -1 -1 20 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 75272 11 2 140 13 2 126 33 20 20 400 -1 vtr_extra_small -1 -1 -1 -1 -1 -1 -1 73.5 MiB 0.89 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.5 MiB 0.89 73.5 MiB 0.66 927 7.72500 248 2.06667 341 586 12691 3249 2.07112e+07 1.07788e+06 1.12964e+06 2824.09 11 37792 180905 -1 2.27141 2.21904 -192.145 -2.27141 0 0 0.21 -1 -1 73.5 MiB 0.04 0.0291693 0.0268442 73.5 MiB -1 0.47 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.78 vpr 83.23 MiB -1 -1 18.50 47880 3 1.03 -1 -1 38848 -1 -1 50 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85228 196 193 800 389 1 591 440 20 20 400 -1 vtr_extra_small -1 -1 3715 3554 3784 38 823 2923 83.2 MiB 2.24 0.02 2.85588 2.57265 -1175.96 -2.57265 2.57265 0.10 0.00362627 0.00313967 0.0281499 0.026191 83.2 MiB 2.24 83.2 MiB 1.59 5468 9.39519 1600 2.74914 1643 2642 175568 48502 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.92546 2.92546 -1279.3 -2.92546 0 0 0.33 -1 -1 83.2 MiB 0.23 0.194282 0.17603 83.2 MiB -1 0.10 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.30 vpr 77.05 MiB -1 -1 0.46 21648 3 0.11 -1 -1 36796 -1 -1 69 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78904 99 130 240 229 1 219 299 20 20 400 -1 vtr_extra_small -1 -1 897 855 16283 1900 1766 12617 77.1 MiB 0.85 0.01 1.95754 1.93615 -150.064 -1.93615 1.93615 0.10 0.00114824 0.00101953 0.0225391 0.0202679 77.1 MiB 0.85 77.1 MiB 0.55 1415 8.84375 420 2.62500 390 656 29567 8292 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 10 39388 210115 -1 1.99132 1.99132 -170.793 -1.99132 0 0 0.34 -1 -1 77.1 MiB 0.05 0.0576019 0.0526431 77.1 MiB -1 0.10 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.74 vpr 86.56 MiB -1 -1 3.84 35864 16 0.69 -1 -1 39076 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88636 45 32 936 77 1 765 142 20 20 400 -1 vtr_extra_small -1 -1 7990 6993 2362 101 1016 1245 86.6 MiB 6.20 0.02 12.1921 10.5297 -7133.55 -10.5297 10.5297 0.16 0.00556384 0.00434574 0.083545 0.0720334 86.6 MiB 6.20 86.6 MiB 4.77 11420 14.9869 2979 3.90945 3498 9480 737557 180691 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.8282 10.8282 -7490.44 -10.8282 0 0 0.55 -1 -1 86.6 MiB 0.48 0.322984 0.290732 86.6 MiB -1 0.16 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.69 vpr 76.73 MiB -1 -1 0.87 26256 4 0.17 -1 -1 36604 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 425 276 658 98 289 271 76.7 MiB 0.68 0.00 2.38519 2.10685 -169.375 -2.10685 1.95087 0.09 0.000833002 0.000701647 0.018572 0.0162134 76.7 MiB 0.68 76.7 MiB 0.44 404 5.53425 120 1.64384 174 291 5454 1630 2.07112e+07 808410 1.12964e+06 2824.09 11 37792 180905 -1 2.17742 1.95241 -171.997 -2.17742 0 0 0.30 -1 -1 76.7 MiB 0.04 0.0564754 0.0510591 76.7 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index b41f3d15872..37ed89929f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 3.89 vpr 58.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60104 10 10 253 263 1 165 89 11 11 121 clb auto 19.0 MiB 0.24 1298 4445 695 3556 194 58.7 MiB 0.05 0.00 5.53812 -72.6437 -5.53812 5.53812 0.21 0.000597156 0.000536921 0.0176424 0.0161115 -1 -1 -1 -1 14 2029 36 2.43e+06 2.07e+06 -1 -1 2.05 0.317982 0.283185 3402 27531 -1 1944 19 1218 4569 249188 30978 7.47374 7.47374 -94.8537 -7.47374 0 0 -1 -1 0.07 0.29 0.02 -1 -1 0.07 0.060437 0.0554417 - k4_n4_v7_longline_bidir.xml styr.blif common 4.05 vpr 58.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59432 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.06 1243 3851 530 3175 146 58.0 MiB 0.04 0.00 4.42129 -53.6285 -4.42129 4.42129 0.23 0.000663771 0.000596818 0.0176359 0.0161365 -1 -1 -1 -1 19 2381 26 2.43e+06 2.07e+06 -1 -1 2.10 0.266841 0.23096 3282 34431 -1 2331 24 1499 5264 384444 46394 8.40637 8.40637 -105.933 -8.40637 0 0 -1 -1 0.10 0.21 0.02 -1 -1 0.10 0.0424648 0.0379047 - k4_n4_v7_l1_bidir.xml styr.blif common 5.46 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60072 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.24 1249 6821 1452 5028 341 58.7 MiB 0.08 0.00 6.30077 -80.949 -6.30077 6.30077 0.24 0.000749315 0.000681105 0.0293634 0.0269084 -1 -1 -1 -1 10 1483 31 2.43e+06 2.07e+06 -1 -1 3.45 0.313343 0.275769 4482 22551 -1 1280 20 1321 4798 303501 58064 7.52318 7.52318 -89.7629 -7.52318 0 0 -1 -1 0.05 0.22 0.02 -1 -1 0.05 0.041626 0.0374306 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 4.39 vpr 58.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59524 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.07 1252 4247 601 3492 154 58.1 MiB 0.05 0.00 3.38007 -43.5291 -3.38007 3.38007 0.17 0.000689869 0.000623886 0.0174325 0.0159695 -1 -1 -1 -1 14 2047 30 2.43e+06 2.07e+06 -1 -1 2.73 0.325816 0.284563 3402 27531 -1 2099 29 1484 5383 889715 156716 22.7353 22.7353 -261.092 -22.7353 0 0 -1 -1 0.05 0.26 0.03 -1 -1 0.05 0.0496444 0.0442275 + k4_n4_v7_bidir.xml styr.blif common 1.86 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.08 0.000682102 0.000589331 0.0191204 0.0168271 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.92 0.219017 0.188624 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.09 0.03 -1 -1 0.01 0.0322472 0.0293972 + k4_n4_v7_longline_bidir.xml styr.blif common 1.71 vpr 60.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61932 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.08 1219 4247 600 3483 164 60.5 MiB 0.06 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000822212 0.000745517 0.0200899 0.0175819 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.71 0.217702 0.191181 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.11 0.03 -1 -1 0.02 0.0360271 0.0325274 + k4_n4_v7_l1_bidir.xml styr.blif common 2.28 vpr 61.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62500 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1285 7613 1616 5547 450 61.0 MiB 0.11 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.00083663 0.000735935 0.0404209 0.0365528 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.11 0.183783 0.164876 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0404434 0.0363816 + k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61916 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.09 1234 4643 666 3821 156 60.5 MiB 0.06 0.00 3.51175 -43.7413 -3.51175 3.51175 0.10 0.000796689 0.00069941 0.0254117 0.0229956 -1 -1 -1 -1 16 1911 27 2.43e+06 2.07e+06 -1 -1 2.14 0.308921 0.270668 3522 30407 -1 1965 30 1263 4698 759011 126866 28.7744 28.7744 -241.883 -28.7744 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0527885 0.0460513 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 0c895ef220e..99bb28a8269 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 4.17 vpr 63.71 MiB -1 -1 0.84 23508 5 0.18 -1 -1 33600 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65244 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.28 146 398 72 298 28 63.7 MiB 0.07 0.01 2.14643 -92.7521 -2.14643 2.14643 0.08 0.000419766 0.000385553 0.00743059 0.00689969 -1 -1 -1 -1 14 201 20 646728 646728 22986.6 638.518 0.77 0.1423 0.123972 1728 4488 -1 171 15 208 442 9451 2845 2.12882 2.12882 -98.7664 -2.12882 0 0 30529.5 848.041 0.01 0.17 0.01 -1 -1 0.01 0.0225812 0.0202157 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 4.53 vpr 63.96 MiB -1 -1 0.88 23572 5 0.17 -1 -1 33336 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65496 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.05 146 398 72 298 28 64.0 MiB 0.02 0.00 2.14643 -92.7521 -2.14643 2.14643 0.04 0.000405627 0.000370918 0.00658648 0.00608268 -1 -1 -1 -1 14 201 20 646728 646728 22986.6 638.518 1.69 0.282025 0.245066 1728 4488 -1 171 15 208 442 9451 2845 2.12882 2.12882 -98.7664 -2.12882 0 0 30529.5 848.041 0.01 0.21 0.01 -1 -1 0.01 0.0221666 0.0200952 + k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 2.33 vpr 66.02 MiB -1 -1 0.85 26768 5 0.17 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000423798 0.000369821 0.00844968 0.00761151 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.19 0.07328 0.0645326 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.03 0.01 -1 -1 0.00 0.0168546 0.0152174 + k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.62 vpr 65.81 MiB -1 -1 0.84 26884 5 0.22 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67392 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.05 152 432 67 335 30 65.8 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.05 0.000430785 0.000371967 0.00760808 0.00673261 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.40 0.162173 0.135998 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.05 0.01 -1 -1 0.00 0.0294148 0.0268014 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt index f677f127a88..5d7f440c1da 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 5.49 vpr 65.63 MiB -1 -1 0.41 18996 3 0.19 -1 -1 33284 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67204 99 130 344 474 1 227 298 12 12 144 clb auto 25.8 MiB 0.26 717 72933 22876 34411 15646 65.6 MiB 0.49 0.01 1.84343 -118.171 -1.84343 1.84343 0.32 0.00110711 0.00103861 0.0946179 0.0889931 -1 -1 -1 -1 38 1545 17 5.66058e+06 4.21279e+06 319130. 2216.18 1.31 0.310492 0.285139 12522 62564 -1 1253 9 393 600 24053 7065 1.90841 1.90841 -133.88 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.16 0.13 0.07 -1 -1 0.16 0.032452 0.0305703 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 2.91 vpr 67.98 MiB -1 -1 0.40 22276 3 0.11 -1 -1 36796 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69616 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.20 0.00 1.86472 -118.834 -1.86472 1.86472 0.22 0.000979117 0.000879056 0.0638803 0.0581045 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.56 0.199818 0.181639 12522 62564 -1 1120 9 399 643 21323 6785 1.90702 1.90702 -133.259 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.0304906 0.0285332 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt index 48a022dd3d9..c1c20666920 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 5.84 vpr 65.10 MiB -1 -1 0.39 18876 3 0.10 -1 -1 33232 -1 -1 71 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66660 99 130 344 474 1 225 301 13 13 169 clb auto 25.4 MiB 0.12 670 76909 23210 36946 16753 65.1 MiB 0.32 0.00 2.16096 -124.917 -2.16096 2.16096 0.44 0.00120946 0.00114822 0.0881788 0.0826918 -1 -1 -1 -1 32 1294 10 6.63067e+06 4.37447e+06 323148. 1912.12 2.10 0.382628 0.350915 11612 59521 -1 1127 11 526 869 34973 10462 1.97404 1.97404 -140.169 -1.97404 -0.343814 -0.101108 396943. 2348.77 0.15 0.17 0.06 -1 -1 0.15 0.0412974 0.0388666 - k6_N10_mem32K_40nm.xml diffeq1.v common 15.40 vpr 67.93 MiB -1 -1 0.74 23840 15 0.44 -1 -1 34444 -1 -1 61 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69560 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 28.5 MiB 0.42 5631 94844 28473 58959 7412 67.9 MiB 1.03 0.01 21.7383 -1576.03 -21.7383 21.7383 0.79 0.00372085 0.0034284 0.379891 0.357576 -1 -1 -1 -1 44 10661 49 1.21132e+07 5.26753e+06 665287. 2598.78 8.62 1.79562 1.64394 20656 131250 -1 8667 20 3482 8436 990185 277410 22.0559 22.0559 -1674.9 -22.0559 0 0 864808. 3378.16 0.32 0.39 0.15 -1 -1 0.32 0.147219 0.137238 - k6_N10_mem32K_40nm.xml single_wire.v common 1.30 vpr 62.92 MiB -1 -1 0.10 17140 1 0.02 -1 -1 30180 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64428 1 1 1 2 0 1 2 3 3 9 -1 auto 24.1 MiB 0.04 2 3 0 3 0 62.9 MiB 0.03 0.00 0.18684 -0.18684 -0.18684 nan 0.01 2.6888e-05 2.0274e-05 0.000125894 9.4502e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.03 0.00164489 0.00155135 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.02 0.00 -1 -1 0.00 0.00173302 0.00169026 - k6_N10_mem32K_40nm.xml single_ff.v common 1.46 vpr 62.77 MiB -1 -1 0.11 17408 1 0.04 -1 -1 30188 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64272 2 1 3 4 1 3 4 3 3 9 -1 auto 24.0 MiB 0.04 6 9 3 5 1 62.8 MiB 0.06 0.00 0.55247 -0.90831 -0.55247 0.55247 0.02 3.4252e-05 2.6329e-05 0.000209418 0.000157449 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.03 0.00197162 0.00182923 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.01 0.04 0.00 -1 -1 0.01 0.00155682 0.0014869 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 9.61 vpr 64.97 MiB -1 -1 0.41 18928 3 0.13 -1 -1 33340 -1 -1 71 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66528 99 130 344 474 1 225 301 19 19 361 o auto 25.3 MiB 0.24 983 75901 19451 37817 18633 65.0 MiB 0.54 0.00 2.16871 -135.347 -2.16871 2.16871 2.86 0.00121773 0.00114162 0.0972287 0.0905415 -1 -1 -1 -1 32 1458 11 1.79173e+07 4.37447e+06 762679. 2112.68 1.51 0.219057 0.201389 24278 148653 -1 1307 11 602 931 46510 12471 2.09384 2.09384 -139.537 -2.09384 -0.328666 -0.186439 944445. 2616.19 0.44 0.06 0.18 -1 -1 0.44 0.031886 0.0295362 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 27.29 vpr 82.19 MiB -1 -1 0.67 23752 15 0.43 -1 -1 34460 -1 -1 61 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 84164 162 96 1009 950 1 665 324 24 24 576 i auto 28.5 MiB 0.54 7386 77052 23414 46790 6848 82.2 MiB 0.69 0.01 21.6223 -1621.01 -21.6223 21.6223 4.64 0.00332881 0.00312838 0.251065 0.233165 -1 -1 -1 -1 32 13635 42 3.08128e+07 5.26753e+06 1.24505e+06 2161.54 15.07 1.57866 1.45267 39974 242477 -1 10826 21 3915 8751 1239118 330681 22.6153 22.6153 -1715.7 -22.6153 0 0 1.54255e+06 2678.04 0.62 0.44 0.21 -1 -1 0.62 0.158783 0.147345 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 1.44 vpr 62.84 MiB -1 -1 0.11 17216 1 0.04 -1 -1 30128 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64352 1 1 1 2 0 1 2 4 4 16 i auto 24.1 MiB 0.00 3 3 0 0 3 62.8 MiB 0.00 0.00 0.280667 -0.280667 -0.280667 nan 0.01 1.1887e-05 7.554e-06 7.9236e-05 5.4291e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.01 0.00144545 0.00135883 324 600 -1 2 1 1 1 16 6 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.02 0.04 0.01 -1 -1 0.02 0.00203875 0.00199605 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 1.61 vpr 62.92 MiB -1 -1 0.09 17432 1 0.03 -1 -1 29964 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64432 2 1 3 4 1 3 4 4 4 16 i auto 24.1 MiB 0.05 7 9 0 0 9 62.9 MiB 0.00 0.00 0.647256 -1.07419 -0.647256 0.647256 0.01 1.7185e-05 1.2489e-05 0.000119925 9.2542e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.0016352 0.00153073 340 760 -1 3 2 3 3 71 25 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.02 0.03 0.01 -1 -1 0.02 0.00163658 0.00157466 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.54 vpr 67.39 MiB -1 -1 0.42 22156 3 0.16 -1 -1 36544 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69008 99 130 344 474 1 225 301 13 13 169 clb auto 27.8 MiB 0.09 709 69853 20089 36202 13562 67.4 MiB 0.23 0.00 2.16096 -124.938 -2.16096 2.16096 0.29 0.000913323 0.000821579 0.0687918 0.0619499 -1 -1 -1 -1 30 1301 10 6.63067e+06 4.37447e+06 308771. 1827.05 1.05 0.343222 0.313014 11444 57198 -1 1153 11 545 813 32907 9964 1.99803 1.99803 -136.313 -1.99803 -0.30784 -0.0857401 382024. 2260.50 0.04 0.06 0.10 -1 -1 0.04 0.0301423 0.0279655 + k6_N10_mem32K_40nm.xml diffeq1.v common 13.02 vpr 70.71 MiB -1 -1 0.61 26808 15 0.59 -1 -1 38128 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72412 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 31.1 MiB 0.36 5686 93732 25708 60129 7895 70.7 MiB 0.92 0.01 21.5854 -1586.88 -21.5854 21.5854 0.47 0.00359311 0.00328994 0.373845 0.344857 -1 -1 -1 -1 42 11019 36 1.21132e+07 5.26753e+06 637230. 2489.18 7.15 1.94736 1.79599 20148 122574 -1 9118 25 3874 8580 1140724 318272 22.5245 22.5245 -1660.58 -22.5245 0 0 799729. 3123.94 0.07 0.71 0.15 -1 -1 0.07 0.298338 0.280888 + k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB -1 -1 0.11 20620 1 0.02 -1 -1 33040 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0264e-05 6.201e-06 6.8769e-05 4.6066e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00116982 0.00111262 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106891 0.001042 + k6_N10_mem32K_40nm.xml single_ff.v common 0.54 vpr 65.06 MiB -1 -1 0.09 21000 1 0.02 -1 -1 33296 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66620 2 1 3 4 1 3 4 3 3 9 -1 auto 26.6 MiB 0.00 6 9 3 5 1 65.1 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.01 2.0617e-05 1.4741e-05 0.000141684 0.000107774 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00168512 0.00158841 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00172391 0.0016612 + k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.58 vpr 67.37 MiB -1 -1 0.39 22284 3 0.08 -1 -1 36712 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68984 99 130 344 474 1 225 301 19 19 361 o auto 27.9 MiB 0.07 850 78925 21699 38013 19213 67.4 MiB 0.30 0.00 2.16428 -129.737 -2.16428 2.16428 1.74 0.000907451 0.000818758 0.097179 0.0888059 -1 -1 -1 -1 36 1162 10 1.79173e+07 4.37447e+06 833707. 2309.44 1.42 0.329975 0.298327 24998 161561 -1 1074 10 581 868 36231 9318 1.99581 1.99581 -134.677 -1.99581 -0.182839 -0.0660558 1.02328e+06 2834.56 0.12 0.05 0.23 -1 -1 0.12 0.0286893 0.0266338 + k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 20.39 vpr 77.82 MiB -1 -1 0.54 26812 15 0.47 -1 -1 38260 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79688 162 96 1009 950 1 665 324 24 24 576 i auto 30.8 MiB 0.33 7393 99292 28927 58867 11498 77.8 MiB 1.03 0.02 21.7254 -1657.33 -21.7254 21.7254 3.05 0.00462453 0.00428627 0.416981 0.375188 -1 -1 -1 -1 38 12380 31 3.08128e+07 5.26753e+06 1.42563e+06 2475.05 11.34 2.12533 1.94729 42274 284153 -1 10868 19 3672 8078 1198132 301968 22.4983 22.4983 -1725.65 -22.4983 0 0 1.79535e+06 3116.93 0.13 0.60 0.50 -1 -1 0.13 0.215504 0.199648 + k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.51 vpr 65.29 MiB -1 -1 0.10 20720 1 0.02 -1 -1 33044 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1044e-05 6.598e-06 7.3231e-05 5.0487e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00113801 0.00107607 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.00158495 0.00154688 + k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.64 vpr 65.29 MiB -1 -1 0.10 20876 1 0.03 -1 -1 33324 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 2 1 3 4 1 3 4 4 4 16 i auto 27.0 MiB 0.00 7 9 0 1 8 65.3 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.4352e-05 9.526e-06 0.000103801 7.6571e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00161569 0.00152133 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00155787 0.00150496 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 61bfbd9f7c3..278399cb6d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 5.19 vpr 63.54 MiB -1 -1 0.72 23444 5 0.16 -1 -1 33404 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65060 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.14 157 568 195 321 52 63.5 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 14 182 25 646728 646728 22986.6 638.518 1.78 0.168378 0.144307 1728 4488 -1 155 21 263 632 12700 3802 2.3029 2.3029 -99.5273 -2.3029 0 0 30529.5 848.041 0.01 0.20 0.01 -1 -1 0.01 0.0242495 0.021514 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.77 vpr 65.95 MiB -1 -1 0.64 26892 5 0.17 -1 -1 36964 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67536 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 568 210 329 29 66.0 MiB 0.00 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 168 36 646728 646728 19965.4 554.594 0.12 0.0658358 0.0559906 1696 3924 -1 165 24 236 544 12437 3707 2.26842 2.26842 -94.6601 -2.26842 0 0 25971.8 721.439 0.00 0.03 0.00 -1 -1 0.00 0.0200385 0.0180231 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt index 045d3fe7955..b44eab4cd1c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 8.20 vpr 56.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57704 6 7 19 26 0 19 26 3 3 9 -1 auto 17.6 MiB 0.01 51 216 43 63 110 56.4 MiB 0.04 0.00 3.682 -25.774 -3.682 nan 6.49 6.5121e-05 5.701e-05 0.000603112 0.000525304 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.25 0.00299547 0.00268387 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.02 0.04 -1 -1 0.00 0.0025833 0.00241723 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 8.02 vpr 56.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57820 6 7 19 26 0 19 26 3 3 9 -1 auto 17.7 MiB 0.01 51 216 43 63 110 56.5 MiB 0.13 0.00 3.682 -25.774 -3.682 nan 6.21 6.8432e-05 5.8755e-05 0.000633201 0.00053959 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.25 0.00290908 0.00262232 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.01 0.03 0.04 -1 -1 0.01 0.00211606 0.00201309 - sub_tiles.xml sub_tiles.blif common_--check_route_off 8.13 vpr 56.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57860 6 7 19 26 0 19 26 3 3 9 -1 auto 17.8 MiB 0.01 51 216 43 63 110 56.5 MiB 0.09 0.00 3.682 -25.774 -3.682 nan 6.37 7.7326e-05 6.6753e-05 0.000634774 0.000545772 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.25 0.0037268 0.00328193 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.02 0.09 0.04 -1 -1 0.02 0.00205651 0.00193283 + sub_tiles.xml sub_tiles.blif common_--check_route_full 14.98 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.82 4.4449e-05 3.636e-05 0.000492339 0.000302558 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.14 0.00246861 0.00204917 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00171876 0.00162871 + sub_tiles.xml sub_tiles.blif common_--check_route_quick 17.28 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60472 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.88 4.5558e-05 3.7864e-05 0.000392587 0.000316954 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00226581 0.00204304 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00121674 0.00115171 + sub_tiles.xml sub_tiles.blif common_--check_route_off 16.44 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.05 6.9962e-05 5.8494e-05 0.000570046 0.000472887 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.09 0.00239105 0.00217713 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00134624 0.00127449 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 53684d6cff9..124aaee2a04 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.90 vpr 63.76 MiB -1 -1 0.12 17788 1 0.03 -1 -1 30128 -1 -1 3 9 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65288 9 8 75 70 1 34 20 5 5 25 clb auto 24.4 MiB 0.65 94 74 30 43 1 63.8 MiB 0.01 0.00 2.64007 -29.0549 -2.64007 2.64007 0.02 0.000134569 0.000121726 0.00170312 0.00163516 -1 -1 -1 -1 20 213 13 151211 75605.7 29112.5 1164.50 0.06 0.0102057 0.00938622 1812 4729 -1 172 28 196 239 7256 3917 3.69111 3.69111 -41.2836 -3.69111 0 0 37105.9 1484.24 0.00 0.05 0.01 -1 -1 0.00 0.0114522 0.00994594 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 10.86 vpr 64.98 MiB -1 -1 0.15 18364 1 0.04 -1 -1 30524 -1 -1 6 19 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66540 19 18 308 249 1 134 43 5 5 25 clb auto 25.3 MiB 6.04 443 2443 654 1774 15 65.0 MiB 0.32 0.00 4.8546 -99.0126 -4.8546 4.8546 0.05 0.000624995 0.000577932 0.0282589 0.0262406 -1 -1 -1 -1 50 734 31 151211 151211 61632.8 2465.31 2.88 0.28247 0.251267 2268 9834 -1 572 18 574 959 28269 13700 5.68143 5.68143 -111.492 -5.68143 0 0 77226.2 3089.05 0.02 0.05 0.01 -1 -1 0.02 0.0287398 0.0263667 53 83 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.66 vpr 66.09 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33388 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67676 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.65 100 74 24 47 3 66.1 MiB 0.00 0.00 2.48207 -28.4593 -2.48207 2.48207 0.02 0.000164662 0.000145718 0.00164144 0.00155216 -1 -1 -1 -1 38 129 6 151211 75605.7 48493.3 1939.73 0.18 0.0548944 0.0466047 2100 8065 -1 122 13 105 125 3874 2046 2.74837 2.74837 -33.9524 -2.74837 0 0 61632.8 2465.31 0.00 0.01 0.01 -1 -1 0.00 0.00954243 0.00888996 13 18 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.19 MiB -1 -1 0.14 21572 1 0.04 -1 -1 34020 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68800 19 18 308 249 1 134 43 5 5 25 clb auto 27.7 MiB 5.80 445 2068 454 1604 10 67.2 MiB 0.04 0.00 4.5386 -91.3528 -4.5386 4.5386 0.02 0.000449316 0.000397091 0.0186893 0.0169167 -1 -1 -1 -1 50 721 33 151211 151211 61632.8 2465.31 0.30 0.144091 0.126311 2268 9834 -1 620 20 733 1185 38218 18241 5.03997 5.03997 -109.631 -5.03997 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0288144 0.0262691 53 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index ad248bb36be..e2bde77991f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.58 vpr 57.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58932 1 4 28 32 2 10 9 4 4 16 clb auto 18.6 MiB 0.01 21 27 11 8 8 57.6 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.1025e-05 6.2018e-05 0.00055486 0.00050444 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.06 0.00779734 0.00653696 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00306883 0.00282037 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.67 vpr 57.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58820 1 4 28 32 2 10 9 4 4 16 clb auto 18.4 MiB 0.02 21 27 11 8 8 57.4 MiB 0.02 0.00 2.44626 0 0 2.44626 0.01 6.4104e-05 5.5768e-05 0.000609665 0.000560857 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.10 0.0111366 0.00958283 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00675941 0.0056104 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.64 vpr 57.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58996 1 4 28 32 2 10 9 4 4 16 clb auto 18.7 MiB 0.02 21 27 11 8 8 57.6 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 0.000116601 0.000103254 0.000726354 0.000668277 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.03 0.00873381 0.00733762 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00321575 0.00294979 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.40 vpr 59.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61208 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9684e-05 6.8866e-05 0.000576703 0.000522527 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00940561 0.00796331 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00917782 0.00398665 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.34 vpr 59.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61228 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4384e-05 5.704e-05 0.000402489 0.000366894 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0100179 0.00835542 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00286153 0.00265955 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 59.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61188 1 4 28 32 2 10 9 4 4 16 clb auto 21.1 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4879e-05 5.7282e-05 0.000404422 0.000368079 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00971796 0.00808787 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00303232 0.00280678 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index aa6222425e4..9d76eedbd00 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.48 vpr 57.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58752 2 2 22 24 2 4 6 4 4 16 clb auto 18.5 MiB 0.01 8 15 5 7 3 57.4 MiB 0.00 0.00 1.297 0 0 1.297 0.01 7.8807e-05 7.0658e-05 0.000416035 0.000372622 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00270904 0.00251355 660 1032 -1 15 4 8 8 614 487 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00251275 0.00236334 + timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.31 vpr 59.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61216 2 2 22 24 2 4 6 4 4 16 clb auto 21.3 MiB 0.00 8 15 5 7 3 59.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 5.264e-05 4.5649e-05 0.000308634 0.000273818 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.002301 0.00212354 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00265986 0.00219441 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt index 82ec46d8b99..55f3e1dd3ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.66039 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index 373e866a79a..948d09b747d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.61 vpr 57.25 MiB -1 -1 0.07 17368 1 0.03 -1 -1 29984 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58620 2 1 3 4 1 3 4 3 3 9 -1 auto 18.5 MiB 0.00 6 9 6 3 0 57.2 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.6807e-05 1.1824e-05 0.000119813 9.1115e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.0015798 0.00147928 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.59 vpr 57.21 MiB -1 -1 0.08 17320 1 0.03 -1 -1 30044 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58584 2 1 3 4 1 3 4 3 3 9 -1 auto 18.6 MiB 0.00 9 9 5 2 2 57.2 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.8256e-05 1.1481e-05 0.000119179 8.8895e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00156657 0.00148701 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 38.32 parmys 205.31 MiB -1 -1 31.78 210240 2 1.22 -1 -1 54528 -1 -1 155 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60600 5 156 191 347 1 163 316 15 15 225 clb auto 19.7 MiB 0.04 31 86316 62145 3320 20851 59.2 MiB 0.16 0.00 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000581684 0.000550637 0.0478501 0.0452811 -1 -1 -1 -1 -1 50 5 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0572937 0.0539594 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 38.38 parmys 205.27 MiB -1 -1 31.80 210196 2 1.48 -1 -1 54476 -1 -1 155 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60720 5 156 191 347 1 163 316 15 15 225 clb auto 19.7 MiB 0.04 33 86316 61936 3548 20832 59.3 MiB 0.13 0.00 1.51877 -14.6769 -1.51877 1.51877 0.00 0.00039327 0.000370069 0.0328101 0.030775 -1 -1 -1 -1 -1 59 7 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0420611 0.0392993 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.64 vpr 62.86 MiB -1 -1 0.10 17484 1 0.03 -1 -1 30080 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64368 2 1 3 4 1 3 4 3 3 9 -1 auto 24.2 MiB 0.00 6 9 6 2 1 62.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.8165e-05 1.317e-05 0.000125618 9.4159e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.00159727 0.00150396 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.64 vpr 62.82 MiB -1 -1 0.10 17360 1 0.02 -1 -1 29972 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64332 2 1 3 4 1 3 4 3 3 9 -1 auto 24.1 MiB 0.01 9 9 5 2 2 62.8 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.693e-05 1.0549e-05 0.000124748 8.9675e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.00264161 0.002541 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 7.90 vpr 70.32 MiB -1 -1 1.65 25700 2 0.23 -1 -1 33916 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 72008 311 156 972 1128 1 953 525 28 28 784 memory auto 29.8 MiB 0.49 8857 212225 75880 124970 11375 70.3 MiB 1.71 0.02 3.97422 -4305.11 -3.97422 3.97422 0.00 0.00572888 0.00511108 0.585707 0.519764 -1 -1 -1 -1 -1 12735 10 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.46 0.855078 0.77478 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 7.81 vpr 70.43 MiB -1 -1 1.46 26084 2 0.15 -1 -1 33892 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 72124 311 156 972 1128 1 953 525 28 28 784 memory auto 29.8 MiB 0.58 9179 216459 74948 128246 13265 70.4 MiB 1.73 0.01 3.98529 -3456.75 -3.98529 3.98529 0.00 0.00402513 0.00355029 0.622817 0.553567 -1 -1 -1 -1 -1 13300 12 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.44 0.790802 0.707413 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 + timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.66 MiB -1 -1 0.07 21096 1 0.02 -1 -1 33168 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 6 3 0 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.5934e-05 1.0639e-05 9.4808e-05 6.8481e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00119359 0.00110751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 + timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.27 vpr 59.66 MiB -1 -1 0.08 20840 1 0.02 -1 -1 33340 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 9 9 5 2 2 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.6744e-05 1.0373e-05 9.4261e-05 6.634e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00132946 0.0012632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 + timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 31.57 parmys 210.75 MiB -1 -1 25.18 215804 2 1.59 -1 -1 60048 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63168 5 156 191 347 1 163 316 15 15 225 clb auto 22.1 MiB 0.04 31 86316 62145 3320 20851 61.7 MiB 0.22 0.02 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000537912 0.000491594 0.0397632 0.036381 -1 -1 -1 -1 -1 50 5 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0494991 0.045404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 + timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 25.71 parmys 210.82 MiB -1 -1 22.20 215880 2 0.99 -1 -1 60300 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62916 5 156 191 347 1 163 316 15 15 225 clb auto 21.9 MiB 0.02 33 86316 61936 3548 20832 61.4 MiB 0.10 0.00 1.51877 -14.6769 -1.51877 1.51877 0.00 0.000236107 0.000213852 0.0263786 0.0239723 -1 -1 -1 -1 -1 59 7 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0328145 0.0299576 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 + timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 20748 1 0.02 -1 -1 33304 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 6 2 1 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.6453e-05 1.1342e-05 0.000108728 7.9328e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.0015946 0.00150943 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 + timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 21132 1 0.02 -1 -1 33192 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 9 9 5 2 2 65.2 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.8934e-05 1.2137e-05 0.000113982 8.1444e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.00161693 0.00153615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 + timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 5.07 vpr 72.77 MiB -1 -1 1.12 29456 2 0.10 -1 -1 37868 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74516 311 156 972 1128 1 953 525 28 28 784 memory auto 32.5 MiB 0.54 8655 197406 67882 119014 10510 72.8 MiB 1.23 0.02 3.83315 -4315.62 -3.83315 3.83315 0.00 0.0052551 0.00459042 0.542684 0.463052 -1 -1 -1 -1 -1 12421 13 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.41 0.761716 0.663478 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 + timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 5.34 vpr 72.84 MiB -1 -1 1.44 29580 2 0.14 -1 -1 38000 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74592 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.55 8675 193172 64013 116396 12763 72.8 MiB 0.82 0.01 3.94715 -3504.6 -3.94715 3.94715 0.00 0.00308193 0.00262987 0.364549 0.310746 -1 -1 -1 -1 -1 12709 18 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.33 0.5457 0.474589 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt index 2c49254b706..9cebacaf785 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.85 vpr 63.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65156 8 4 25 28 5 19 19 6 6 36 clb auto 24.9 MiB 0.59 52 194 34 129 31 63.6 MiB 0.01 0.00 1.3678 -5.84519 -1.3678 0.545 0.00 7.3716e-05 5.9392e-05 0.000813182 0.000675871 -1 -1 -1 -1 94 6.71429 38 2.71429 16 16 1079 432 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.70371 0.545 -7.0897 -1.70371 -0.508975 -0.416549 0.01 -1 -1 63.6 MiB 0.00 0.00311706 0.00282227 63.6 MiB -1 0.01 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.07 vpr 18.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 19032 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.85 vpr 66.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 8 4 25 28 5 19 19 6 6 36 clb auto 27.5 MiB 0.60 51 194 39 119 36 66.0 MiB 0.01 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 8.3509e-05 6.4713e-05 0.00086545 0.000699438 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.0 MiB 0.00 0.00307466 0.00275514 66.0 MiB -1 0.00 + k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21296 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index 15ed137557f..c751724ac21 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.57 vpr 62.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64448 -1 2 2 4 0 2 4 4 4 16 clb auto 24.2 MiB 0.01 0 9 0 2 7 62.9 MiB 0.00 0.00 nan 0 0 nan 0.01 1.5432e-05 9.947e-06 0.000103448 7.2917e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.01 0.00166706 0.00157906 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00153779 0.0014983 + k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.30 vpr 65.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66556 -1 2 2 4 0 2 4 4 4 16 clb auto 26.8 MiB 0.00 0 9 0 2 7 65.0 MiB 0.00 0.00 nan 0 0 nan 0.01 9.099e-06 4.802e-06 6.6245e-05 4.4664e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00112148 0.00105568 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00152182 0.00148612 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index f2f0bc32df9..19c7fb784a9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 50.12 vpr 84.06 MiB -1 -1 4.92 42896 3 0.97 -1 -1 38096 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86076 236 305 3199 3011 1 1520 677 25 25 625 -1 25x25 43.6 MiB 4.09 14118 291835 98746 175385 17704 84.1 MiB 2.87 0.03 4.72973 -2868.1 -4.72973 4.72973 2.50 0.00934029 0.00870323 1.04526 0.953005 -1 -1 -1 -1 52 26464 27 3.19446e+07 9.87633e+06 2.10129e+06 3362.06 27.31 4.1956 3.78489 66867 433069 -1 22541 17 6135 15940 1459564 357995 4.91399 4.91399 -3142.67 -4.91399 0 0 2.76576e+06 4425.22 0.86 0.74 0.34 -1 -1 0.86 0.41451 0.387228 - column_io.xml raygentop.v common 52.53 vpr 84.01 MiB -1 -1 4.75 43120 3 0.95 -1 -1 38088 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86024 236 305 3199 3011 1 1520 677 25 25 625 io auto 43.3 MiB 3.89 13024 265096 92273 145957 26866 84.0 MiB 2.89 0.07 4.68781 -2886.38 -4.68781 4.68781 2.43 0.016091 0.0142909 1.032 0.939322 -1 -1 -1 -1 54 26434 28 2.82259e+07 9.87633e+06 2.01770e+06 3228.33 30.36 4.7011 4.2358 60384 399159 -1 22444 15 6172 15744 1649398 413722 4.80071 4.80071 -3243.79 -4.80071 0 0 2.61977e+06 4191.64 0.69 0.69 0.36 -1 -1 0.69 0.354307 0.329375 - multiwidth_blocks.xml raygentop.v common 28.57 vpr 84.04 MiB -1 -1 4.75 43076 3 0.88 -1 -1 37996 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86060 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 43.3 MiB 3.59 13048 259154 90005 148757 20392 84.0 MiB 2.45 0.03 4.71803 -2841.59 -4.71803 4.71803 0.97 0.00752803 0.00694478 0.875966 0.783393 -1 -1 -1 -1 68 23694 44 1.65001e+07 9.87633e+06 1.28755e+06 3566.63 9.85 3.54924 3.21845 36601 236909 -1 20599 14 5516 14268 1424917 397183 4.96129 4.96129 -3042.89 -4.96129 0 0 1.60474e+06 4445.26 0.53 0.88 0.31 -1 -1 0.53 0.465359 0.438075 - non_column.xml raygentop.v common 42.55 vpr 104.43 MiB -1 -1 5.31 43252 3 0.75 -1 -1 38476 -1 -1 125 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 106936 236 305 3188 3000 1 1523 673 33 33 1089 io auto 45.0 MiB 3.88 15120 277785 102957 155262 19566 101.8 MiB 2.72 0.04 4.88336 -2959.54 -4.88336 4.88336 4.12 0.0135356 0.0122621 1.04776 0.936225 -1 -1 -1 -1 54 27353 23 5.44432e+07 9.66075e+06 3.30487e+06 3034.77 14.70 2.8388 2.54814 100302 649205 -1 23944 23 6474 17454 1453295 386379 5.20545 5.20545 -3216.33 -5.20545 0 0 4.28921e+06 3938.67 1.71 0.82 0.92 -1 -1 1.71 0.475433 0.442218 - non_column_tall_aspect_ratio.xml raygentop.v common 50.32 vpr 113.80 MiB -1 -1 5.13 43092 3 0.78 -1 -1 38540 -1 -1 125 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 116536 236 305 3188 3000 1 1523 673 23 46 1058 io auto 45.1 MiB 3.75 14514 263045 93443 131443 38159 101.1 MiB 2.67 0.03 4.82017 -2930.26 -4.82017 4.82017 3.80 0.00828949 0.00744749 0.950815 0.857933 -1 -1 -1 -1 50 29578 44 5.05849e+07 9.66075e+06 3.07243e+06 2904.00 24.36 4.29725 3.87978 95149 595581 -1 24184 18 6943 17685 1630226 419654 5.16068 5.16068 -3258.77 -5.16068 0 0 3.91054e+06 3696.17 1.09 0.74 0.66 -1 -1 1.09 0.398171 0.369417 - non_column_wide_aspect_ratio.xml raygentop.v common 58.69 vpr 121.68 MiB -1 -1 4.91 42728 3 0.80 -1 -1 38520 -1 -1 125 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 124604 236 305 3188 3000 1 1523 673 53 27 1431 io auto 45.2 MiB 3.93 16209 316109 110737 181993 23379 121.4 MiB 2.93 0.03 4.68132 -2964.88 -4.68132 4.68132 4.96 0.0102309 0.00911393 1.15188 1.03477 -1 -1 -1 -1 46 33009 48 7.18852e+07 9.66075e+06 3.81039e+06 2662.74 29.85 4.41198 3.98344 125381 744275 -1 26452 19 7219 18561 1795297 455177 5.41811 5.41811 -3289.3 -5.41811 0 0 4.88937e+06 3416.75 1.36 0.79 0.79 -1 -1 1.36 0.408966 0.377897 - custom_sbloc.xml raygentop.v common 32.21 vpr 83.94 MiB -1 -1 4.78 43028 3 0.93 -1 -1 38248 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85956 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 43.3 MiB 3.43 12849 268067 89827 155344 22896 83.9 MiB 2.79 0.03 4.97602 -2840.03 -4.97602 4.97602 0.92 0.0104771 0.00924771 1.01557 0.905812 -1 -1 -1 -1 64 23203 26 1.65001e+07 9.87633e+06 1.19565e+06 3312.06 13.62 4.4638 4.00556 35881 230269 -1 20371 13 5422 13885 1260364 333144 5.08018 5.08018 -3072.96 -5.08018 0 0 1.50465e+06 4168.01 0.50 0.66 0.28 -1 -1 0.50 0.368005 0.3451 - multiple_io_types.xml raygentop.v common 121.78 vpr 532.44 MiB -1 -1 4.07 43200 3 0.82 -1 -1 37944 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 545220 236 305 3199 3011 1 1520 677 70 70 4900 io_left auto 43.7 MiB 5.99 31458 107633 6752 25817 75064 532.4 MiB 0.91 0.03 4.99804 -3572.5 -4.99804 4.99804 35.22 0.00883048 0.00802454 0.360901 0.3315 -1 -1 -1 -1 56 45066 25 2.76175e+08 9.87633e+06 1.50822e+07 3078.00 42.79 2.92767 2.65794 455094 2833831 -1 41437 17 7663 19266 3190631 818724 5.20546 5.20546 -3898.3 -5.20546 0 0 1.92585e+07 3930.30 6.20 1.08 2.64 -1 -1 6.20 0.379077 0.35159 + fixed_grid.xml raygentop.v common 36.32 vpr 86.72 MiB -1 -1 4.05 45484 3 0.90 -1 -1 40972 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88800 236 305 3199 3011 1 1520 677 25 25 625 -1 25x25 45.9 MiB 3.77 14108 309661 104995 184095 20571 86.7 MiB 2.82 0.04 4.79923 -2884.9 -4.79923 4.79923 1.31 0.00890658 0.00798503 1.05545 0.927146 -1 -1 -1 -1 58 25094 44 3.19446e+07 9.87633e+06 2.35761e+06 3772.18 18.23 4.76599 4.25993 69363 480205 -1 22477 18 6375 16887 1571491 383129 5.01505 5.01505 -3124.26 -5.01505 0 0 3.00727e+06 4811.63 0.12 0.58 0.43 -1 -1 0.12 0.287158 0.267873 + column_io.xml raygentop.v common 21.72 vpr 86.87 MiB -1 -1 3.94 45412 3 0.59 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88956 236 305 3199 3011 1 1520 677 25 25 625 io auto 46.1 MiB 2.22 12585 268067 93998 147700 26369 86.9 MiB 1.58 0.02 4.73901 -2866.75 -4.73901 4.73901 0.71 0.00580557 0.00496502 0.564483 0.497852 -1 -1 -1 -1 54 26673 50 2.82259e+07 9.87633e+06 2.01770e+06 3228.33 9.11 2.60416 2.32669 60384 399159 -1 22031 17 6221 15823 1566992 390050 4.92063 4.92063 -3214.76 -4.92063 0 0 2.61977e+06 4191.64 0.11 0.57 0.36 -1 -1 0.11 0.283045 0.264698 + multiwidth_blocks.xml raygentop.v common 24.35 vpr 86.45 MiB -1 -1 4.29 45400 3 0.88 -1 -1 40680 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88524 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.5 MiB 3.44 13659 253212 84696 147080 21436 86.4 MiB 2.39 0.03 4.97053 -2888.67 -4.97053 4.97053 0.57 0.0095941 0.00864195 0.904905 0.798443 -1 -1 -1 -1 70 23087 25 1.65001e+07 9.87633e+06 1.31889e+06 3653.42 9.29 3.5266 3.16984 37321 246261 -1 21189 14 5796 14717 1380152 383870 5.13329 5.13329 -3164.24 -5.13329 0 0 1.66774e+06 4619.77 0.06 0.50 0.26 -1 -1 0.06 0.248992 0.232939 + non_column.xml raygentop.v common 55.37 vpr 101.45 MiB -1 -1 4.51 45384 3 0.78 -1 -1 40740 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103880 236 305 3188 3000 1 1523 673 33 33 1089 io auto 46.9 MiB 3.81 15255 254201 81770 140693 31738 97.7 MiB 2.36 0.03 4.86131 -2900.08 -4.86131 4.86131 2.27 0.00977579 0.00884174 0.917497 0.805822 -1 -1 -1 -1 48 30162 49 5.44432e+07 9.66075e+06 2.98548e+06 2741.49 34.00 4.50443 4.0188 95950 575791 -1 25045 20 6804 18118 1664218 433730 5.45028 5.45028 -3158.16 -5.45028 0 0 3.81303e+06 3501.40 0.21 0.95 0.95 -1 -1 0.21 0.482241 0.44347 + non_column_tall_aspect_ratio.xml raygentop.v common 44.05 vpr 108.02 MiB -1 -1 4.73 45644 3 0.86 -1 -1 40856 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110616 236 305 3188 3000 1 1523 673 23 46 1058 io auto 47.3 MiB 3.74 14790 242409 83942 122709 35758 98.8 MiB 2.21 0.03 4.6713 -2947.44 -4.6713 4.6713 2.10 0.00881355 0.00803567 0.866396 0.762137 -1 -1 -1 -1 54 27998 49 5.05849e+07 9.66075e+06 3.28516e+06 3105.07 22.44 5.06657 4.53255 98319 656086 -1 23970 19 6505 16966 1638977 432992 5.05886 5.05886 -3281.32 -5.05886 0 0 4.26512e+06 4031.31 0.30 0.98 1.19 -1 -1 0.30 0.480325 0.442198 + non_column_wide_aspect_ratio.xml raygentop.v common 55.14 vpr 115.98 MiB -1 -1 4.85 45536 3 0.89 -1 -1 40604 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 118764 236 305 3188 3000 1 1523 673 53 27 1431 io auto 47.2 MiB 4.13 15438 292525 96949 170972 24604 116.0 MiB 2.79 0.04 4.87363 -3002.95 -4.87363 4.87363 2.83 0.00999099 0.00902684 1.12807 0.98489 -1 -1 -1 -1 46 32183 50 7.18852e+07 9.66075e+06 3.81039e+06 2662.74 30.50 4.16688 3.69158 125381 744275 -1 26057 24 7716 19635 2034521 534369 5.1816 5.1816 -3336.75 -5.1816 0 0 4.88937e+06 3416.75 0.38 1.34 1.15 -1 -1 0.38 0.614347 0.564321 + custom_sbloc.xml raygentop.v common 26.06 vpr 86.32 MiB -1 -1 4.50 45448 3 1.04 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88392 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 4.20 13741 271038 86813 158916 25309 86.3 MiB 2.67 0.04 4.66207 -2945.67 -4.66207 4.66207 0.62 0.0101306 0.00867476 0.964821 0.865378 -1 -1 -1 -1 68 24218 46 1.65001e+07 9.87633e+06 1.26689e+06 3509.39 7.14 3.30943 2.96886 36601 241349 -1 21082 17 5846 15055 1419293 377571 4.86127 4.86127 -3204.17 -4.86127 0 0 1.57833e+06 4372.12 0.09 0.93 0.49 -1 -1 0.09 0.46499 0.431595 + multiple_io_types.xml raygentop.v common 162.68 vpr 512.77 MiB -1 -1 4.59 44868 3 0.91 -1 -1 40632 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 525072 236 305 3199 3011 1 1520 677 70 70 4900 io_left auto 46.0 MiB 4.88 29540 98720 5114 25125 68481 512.8 MiB 0.75 0.03 4.77694 -3775.91 -4.77694 4.77694 29.11 0.00955143 0.00822118 0.265489 0.23233 -1 -1 -1 -1 46 47171 45 2.76175e+08 9.87633e+06 1.25363e+07 2558.43 103.39 4.74809 4.24216 425698 2387761 -1 40627 18 8645 22202 3622069 899914 5.14884 5.14884 -4109.51 -5.14884 0 0 1.61910e+07 3304.29 1.21 1.53 3.08 -1 -1 1.21 0.445697 0.411568 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index d908d4ed0df..9ad80c43a91 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 4.08 vpr 65.78 MiB -1 -1 0.40 19048 3 0.11 -1 -1 33284 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67356 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.25 717 72933 22876 34411 15646 65.8 MiB 0.24 0.00 1.84343 -118.171 -1.84343 1.84343 0.43 0.000943281 0.00088635 0.0770799 0.0722149 -1 -1 -1 -1 38 1552 14 5.66058e+06 4.21279e+06 328943. 2284.32 0.86 0.213472 0.195926 12522 66188 -1 1256 9 393 600 24051 7073 1.90841 1.90841 -134.177 -1.90841 -1.28606 -0.31945 418267. 2904.63 0.16 0.04 0.09 -1 -1 0.16 0.0289584 0.0270731 + k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.93 MiB -1 -1 0.36 22040 3 0.12 -1 -1 36928 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69560 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.23 673 63978 19550 30341 14087 67.9 MiB 0.25 0.01 1.86472 -118.834 -1.86472 1.86472 0.23 0.00124652 0.00114654 0.0791433 0.0725521 -1 -1 -1 -1 38 1384 9 5.66058e+06 4.21279e+06 328943. 2284.32 0.66 0.24355 0.222932 12522 66188 -1 1114 9 395 636 21516 6871 1.90702 1.90702 -133.439 -1.90702 -1.20917 -0.320482 418267. 2904.63 0.04 0.05 0.10 -1 -1 0.04 0.0351893 0.0324309 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt index 8f5f4a02727..88d0cc36263 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 75.27 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1221072 13 29 26295 20086 1 12439 800 40 32 1280 -1 EP4SGX110 1063.1 MiB 16.25 74701 260640 52935 201304 6401 1192.5 MiB 10.24 0.14 5.01005 -5474.24 -4.01005 2.78538 0.01 0.0384053 0.0310295 2.9187 2.44906 86606 6.96358 20705 1.66479 25778 34975 9286411 1665781 0 0 2.34683e+07 18334.6 14 375646 4004209 -1 5.31377 2.77336 -5554.53 -4.31377 0 0 7.20 -1 -1 1192.5 MiB 3.77 4.63873 3.95514 1192.5 MiB -1 15.10 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 65.74 vpr 1.17 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1222776 13 29 26295 20086 1 12439 800 40 32 1280 -1 EP4SGX110 1063.6 MiB 14.29 72376 238368 44187 187356 6825 1172.1 MiB 12.27 0.21 5.14869 -5574.19 -4.14869 2.7734 0.01 0.0513395 0.0444487 3.37672 2.67885 83490 6.71303 20017 1.60947 25863 35776 9229792 1644713 0 0 2.34683e+07 18334.6 15 375646 4004209 -1 5.37962 2.85331 -5732.11 -4.37962 0 0 7.55 -1 -1 1172.1 MiB 6.09 5.72718 4.67253 1172.1 MiB -1 3.79 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index e1e3f31918d..f8dbe6d76d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 4.18 vpr 62.35 MiB -1 -1 0.41 18976 3 0.11 -1 -1 33312 -1 -1 72 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63844 99 130 353 483 1 273 302 15 15 225 memory auto 22.6 MiB 0.05 852 74178 23994 32332 17852 62.3 MiB 0.23 0.00 1.52582 -80.4614 -1.52582 1.52582 0.00 0.00092711 0.000867428 0.0693377 0.06488 -1 -1 -1 -1 1170 5.46729 648 3.02804 652 1492 181450 49896 1.16234e+06 363548 2.18283e+06 9701.45 10 48952 428016 -1 1.67686 1.67686 -105.874 -1.67686 -2.09914 -0.312873 0.62 -1 -1 62.3 MiB 0.07 0.0963391 0.0897976 62.3 MiB -1 1.98 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.26 vpr 64.63 MiB -1 -1 0.36 22472 3 0.08 -1 -1 36672 -1 -1 72 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66184 99 130 353 483 1 273 302 15 15 225 memory auto 25.1 MiB 0.03 836 70130 21082 33527 15521 64.6 MiB 0.28 0.00 1.52582 -78.5706 -1.52582 1.52582 0.00 0.00103975 0.000940046 0.0805857 0.0730912 -1 -1 -1 -1 1163 5.43458 640 2.99065 663 1535 177334 49638 1.16234e+06 363548 2.18283e+06 9701.45 10 48952 428016 -1 1.65868 1.65868 -90.7494 -1.65868 -2.16982 -0.309514 0.64 -1 -1 64.6 MiB 0.08 0.105372 0.095866 64.6 MiB -1 0.38 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index 843f979b3b0..01809a06f11 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 36.56 vpr 83.12 MiB -1 -1 1.49 26172 2 0.18 -1 -1 34220 -1 -1 32 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85116 311 156 1015 1158 1 965 514 28 28 784 memory auto 32.4 MiB 0.98 8658 202198 68681 121559 11958 83.1 MiB 1.72 0.04 4.52468 -3467.97 -4.52468 4.52468 3.21 0.00929751 0.00872728 0.605238 0.537126 -1 -1 -1 -1 36 15288 36 4.25198e+07 9.94461e+06 1.97160e+06 2514.80 19.52 3.06547 2.77593 76483 392267 -1 13678 12 2942 3353 770564 257137 4.55307 4.55307 -4387.12 -4.55307 -358.532 -1.23434 2.42825e+06 3097.26 1.16 2.02 0.42 -1 -1 1.16 0.193225 0.179934 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 34.90 vpr 83.83 MiB -1 -1 1.47 25784 2 0.19 -1 -1 34296 -1 -1 32 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85840 311 156 1015 1158 1 965 514 28 28 784 memory auto 32.4 MiB 0.98 8658 202198 68681 121559 11958 83.8 MiB 1.42 0.01 4.52468 -3467.97 -4.52468 4.52468 2.94 0.00393818 0.00343783 0.510989 0.454287 -1 -1 -1 -1 36 15409 27 4.25198e+07 9.94461e+06 2.00618e+06 2558.90 18.25 2.85623 2.58578 76483 403003 -1 13760 16 3067 3560 745826 226255 4.40123 4.40123 -4543.68 -4.40123 -178.96 -1.26307 2.47848e+06 3161.33 1.21 2.10 0.41 -1 -1 1.21 0.238381 0.220608 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 28.59 vpr 84.23 MiB -1 -1 1.56 25800 2 0.18 -1 -1 34208 -1 -1 32 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86256 311 156 1015 1158 1 965 514 28 28 784 memory auto 32.3 MiB 0.99 8666 202198 68103 120968 13127 84.2 MiB 1.54 0.02 4.38362 -3624.19 -4.38362 4.38362 3.07 0.00455316 0.00405324 0.525661 0.462249 -1 -1 -1 -1 40 15871 21 4.25198e+07 9.94461e+06 2.15085e+06 2743.43 10.76 2.02034 1.8204 78831 435812 -1 14774 15 2518 2894 1193668 708143 5.59605 5.59605 -4517.23 -5.59605 -1680.59 -3.37889 2.68809e+06 3428.68 1.36 3.08 0.49 -1 -1 1.36 0.410611 0.383265 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 22.14 vpr 81.82 MiB -1 -1 1.50 29500 2 0.12 -1 -1 37736 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83780 311 156 1015 1158 1 965 514 28 28 784 memory auto 35.0 MiB 0.98 9365 202198 74776 117229 10193 76.8 MiB 1.40 0.02 4.8046 -3913.87 -4.8046 4.8046 1.69 0.00610306 0.00535177 0.650008 0.562031 -1 -1 -1 -1 46 14326 15 4.25198e+07 9.94461e+06 2.42825e+06 3097.26 10.53 2.95135 2.62498 81963 495902 -1 13813 11 2359 2703 832718 314081 4.94363 4.94363 -4384.42 -4.94363 -367.864 -1.26276 3.12000e+06 3979.60 0.25 1.49 0.70 -1 -1 0.25 0.183604 0.168791 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 21.14 vpr 85.34 MiB -1 -1 1.46 29488 2 0.17 -1 -1 37984 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 87384 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.6 MiB 1.02 9365 202198 74776 117229 10193 77.2 MiB 1.49 0.03 4.8046 -3913.87 -4.8046 4.8046 1.72 0.00745529 0.00636204 0.709181 0.610899 -1 -1 -1 -1 46 14531 14 4.25198e+07 9.94461e+06 2.47848e+06 3161.33 10.27 3.22179 2.86209 81963 509322 -1 13895 10 2295 2641 564364 164225 5.2138 5.2138 -4583.26 -5.2138 -149.396 -1.20609 3.17357e+06 4047.92 0.16 0.89 0.46 -1 -1 0.16 0.127663 0.117099 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 25.61 vpr 78.92 MiB -1 -1 1.51 29244 2 0.15 -1 -1 37516 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80812 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.8 MiB 0.83 9442 200140 70475 118412 11253 78.1 MiB 1.44 0.02 4.10149 -3784.12 -4.10149 4.10149 1.51 0.00620655 0.00547017 0.672177 0.575194 -1 -1 -1 -1 40 16586 15 4.25198e+07 9.94461e+06 2.15085e+06 2743.43 14.64 1.95101 1.72006 78831 435812 -1 15579 11 2621 3012 1218850 719774 5.45816 5.45816 -4586.28 -5.45816 -1608.52 -3.17721 2.68809e+06 3428.68 0.23 1.76 0.54 -1 -1 0.23 0.216383 0.199419 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index e7307c55606..6c7432d3e12 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 15.60 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70696 64 39 1935 1974 1 1077 541 23 23 529 clb auto 28.8 MiB 0.37 10085 137127 36539 98027 2561 69.0 MiB 1.24 0.02 7.41831 -1418.64 -7.41831 7.41831 0.89 0.00562414 0.00480176 0.355623 0.303324 -1 -1 -1 -1 22 12754 28 983127 976439 735934. 1391.18 7.61 1.13414 0.983828 35322 121345 -1 11109 19 6608 23845 1462488 382373 7.14816 7.14816 -1474.13 -7.14816 0 0 927497. 1753.30 0.18 1.15 0.16 -1 -1 0.18 0.319207 0.292209 + k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.52 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.33 10472 141533 36950 100839 3744 71.5 MiB 1.36 0.02 7.46482 -1369.01 -7.46482 7.46482 0.53 0.00499636 0.00433729 0.369387 0.30729 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 10.94 2.01193 1.71604 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.85 0.23 -1 -1 0.04 0.262211 0.23364 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index 2ed54d22fd2..15d40a35dda 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 44.58 vpr 82.23 MiB -1 -1 8.38 52984 5 2.48 -1 -1 39568 -1 -1 153 193 5 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 84204 193 205 2718 2652 1 1312 556 20 20 400 memory auto 41.6 MiB 2.41 10365 229056 86247 118235 24574 82.2 MiB 2.50 0.03 4.93042 -2712.69 -4.93042 4.93042 1.52 0.00941947 0.00864017 1.00208 0.892514 -1 -1 -1 -1 82 19408 35 2.07112e+07 1.09858e+07 2.14661e+06 5366.52 20.26 4.55427 4.07475 53670 456392 -1 17785 15 4760 12593 961685 215487 5.25964 5.25964 -2873.25 -5.25964 -10.2812 -0.29768 2.68822e+06 6720.56 0.99 0.57 0.52 -1 -1 0.99 0.345857 0.321125 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 34.16 vpr 84.50 MiB -1 -1 7.12 54432 5 2.11 -1 -1 42788 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86528 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 1.85 10543 233626 82676 126206 24744 84.5 MiB 2.72 0.04 4.85425 -2733.64 -4.85425 4.85425 0.66 0.00818288 0.00722228 1.06716 0.90034 -1 -1 -1 -1 76 20844 33 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 15.57 4.03457 3.54046 52074 423490 -1 18742 16 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.47 0.38 -1 -1 0.11 0.260053 0.24125 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index 218d776b173..d0e64cbc176 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.12 vpr 65.63 MiB -1 -1 0.43 18936 3 0.10 -1 -1 33276 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67208 99 130 344 474 1 227 298 12 12 144 clb auto 25.9 MiB 0.31 717 72933 22876 34411 15646 65.6 MiB 0.28 0.00 1.84343 -118.171 -1.84343 1.84343 0.41 0.00118638 0.00111707 0.0787144 0.0738877 -1 -1 -1 -1 38 1540 14 5.66058e+06 4.21279e+06 319130. 2216.18 0.79 0.216838 0.200184 12522 62564 -1 1261 9 399 607 24533 7188 1.90841 1.90841 -134.095 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.13 0.04 0.07 -1 -1 0.13 0.0278788 0.0260572 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.94 vpr 67.99 MiB -1 -1 0.39 22036 3 0.12 -1 -1 36636 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69620 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.21 0.00 1.86472 -118.834 -1.86472 1.86472 0.24 0.000996678 0.000900839 0.0648293 0.0586504 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.58 0.202532 0.183764 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.06 0.09 -1 -1 0.02 0.0346978 0.0324594 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index 4e81f397cb6..2abafbec4a3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 151.84 vpr 271.81 MiB -1 -1 18.22 123192 5 52.14 -1 -1 65180 -1 -1 1352 169 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 278332 169 197 21117 21314 1 6442 1718 39 39 1521 clb auto 119.5 MiB 5.00 49106 989078 343367 618966 26745 271.8 MiB 10.45 0.10 3.87493 -15116.8 -3.87493 3.87493 9.42 0.0295107 0.0249862 3.37183 2.81407 -1 -1 -1 -1 38 61885 27 2.4642e+07 2.4336e+07 4.29790e+06 2825.71 35.67 14.1092 11.5867 119030 883757 -1 58128 20 30287 65526 2502097 448520 3.7865 3.7865 -15779.5 -3.7865 0 0 5.41627e+06 3561.00 1.70 2.36 0.73 -1 -1 1.70 1.66008 1.43692 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 138.53 vpr 269.16 MiB -1 -1 17.93 123432 5 52.13 -1 -1 65280 -1 -1 1342 169 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 275616 169 197 21117 21314 1 6530 1708 39 39 1521 clb auto 119.7 MiB 5.14 49426 991593 360564 611379 19650 269.2 MiB 10.35 0.10 3.57102 -14945.7 -3.57102 3.57102 9.54 0.0295319 0.0250555 3.23004 2.68449 -1 -1 -1 -1 38 62626 36 7.37824e+07 7.23272e+07 4.16760e+06 2740.04 21.59 11.6516 9.60196 119030 845795 -1 58726 26 31787 68726 2500109 471239 3.4196 3.4196 -15850.7 -3.4196 0 0 5.22668e+06 3436.35 1.71 2.83 0.65 -1 -1 1.71 2.09886 1.80153 + k6_N10_40nm.xml stereovision0.v common 151.16 vpr 252.22 MiB -1 -1 13.65 124444 5 69.06 -1 -1 68628 -1 -1 1352 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 258272 169 197 21117 21314 1 6442 1718 39 39 1521 clb auto 120.8 MiB 5.85 49865 999363 355164 624898 19301 252.2 MiB 12.58 0.10 3.94387 -15329.6 -3.94387 3.94387 5.65 0.0282487 0.0224608 3.71486 2.98245 -1 -1 -1 -1 38 62474 28 2.4642e+07 2.4336e+07 4.29790e+06 2825.71 27.54 18.235 14.9379 119030 883757 -1 58887 28 30785 67364 2647531 463217 3.72242 3.72242 -16216.3 -3.72242 0 0 5.41627e+06 3561.00 0.27 2.70 0.65 -1 -1 0.27 1.99577 1.72788 + k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 145.25 vpr 237.36 MiB -1 -1 13.92 124256 5 67.78 -1 -1 68500 -1 -1 1342 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 243060 169 197 21117 21314 1 6530 1708 39 39 1521 clb auto 120.5 MiB 3.79 49914 971183 338147 610049 22987 237.4 MiB 14.52 0.10 3.63479 -14732.8 -3.63479 3.63479 5.35 0.02794 0.0220913 4.48744 3.66675 -1 -1 -1 -1 40 62766 41 7.37824e+07 7.23272e+07 4.31957e+06 2839.95 22.87 16.3688 13.4703 120550 875283 -1 59263 24 31348 67380 2546099 475966 3.57863 3.57863 -15572.9 -3.57863 0 0 5.40678e+06 3554.75 0.57 4.00 1.03 -1 -1 0.57 2.85785 2.46864 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 5a135fa5675..3a5d60de356 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.39 vpr 58.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59484 3 1 5 6 1 4 5 3 3 9 -1 auto 19.7 MiB 0.00 9 12 4 4 4 58.1 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.7269e-05 1.2376e-05 0.000128336 0.000101173 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00155195 0.0014541 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00163857 0.00158765 - k6_frac_N10_40nm.xml conn_order.eblif common 0.47 vpr 58.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59388 2 1 4 5 1 3 4 3 3 9 -1 auto 19.6 MiB 0.00 6 9 4 1 4 58.0 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 2.0764e-05 1.5673e-05 0.000154884 0.000113002 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00171618 0.00160639 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00144513 0.00140629 + k6_frac_N10_40nm.xml test_eblif.eblif common 0.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.5 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.3168e-05 1.5881e-05 0.000156154 0.000121512 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00179937 0.00168173 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00151021 0.00147037 + k6_frac_N10_40nm.xml conn_order.eblif common 0.33 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 2 1 4 5 1 3 4 3 3 9 -1 auto 22.1 MiB 0.00 6 9 4 1 4 60.5 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.6567e-05 1.1555e-05 0.000123665 9.5691e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00181279 0.00171778 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154282 0.00150229 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index 9fe54ec14ab..6afcd280a0b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.48 vpr 56.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57744 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 17.7 MiB 0.00 14 18 7 10 1 56.4 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 1.8648e-05 1.2503e-05 0.000127908 9.7495e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00173006 0.00162827 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00148908 0.0014446 + arch.xml eblif_write.eblif common 0.28 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.2578e-05 1.4571e-05 0.000133192 9.8031e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00167256 0.00156119 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00133191 0.00129055 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index daf901cac9d..826beb46c2f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.56 vpr 63.62 MiB -1 -1 0.89 23616 5 0.15 -1 -1 33552 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65152 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.18 146 398 72 298 28 63.6 MiB 0.11 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000445467 0.000411761 0.00801694 0.00746509 -1 -1 -1 -1 -1 136 16 646728 646728 60312.4 1675.34 0.11 0.0303214 0.027336 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.94 vpr 66.02 MiB -1 -1 0.82 27148 5 0.18 -1 -1 36836 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.09 152 432 67 335 30 66.0 MiB 0.04 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000434946 0.000380309 0.00759691 0.00679441 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.0281069 0.0251327 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt index e9d9eeaa41e..106e5784d60 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.46 vpr 56.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57816 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 17.7 MiB 0.00 9 9 4 5 0 56.5 MiB 0.01 0.00 3.8649 -3.8649 -3.8649 nan 0.03 5.3982e-05 3.6833e-05 0.000300109 0.000216559 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00165523 0.00149952 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00144261 0.0014006 + equivalent.xml equivalent.blif common 0.33 vpr 58.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60324 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.4 MiB 0.00 9 9 3 6 0 58.9 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 1.5162e-05 1.0275e-05 0.00029282 0.000262472 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00144752 0.00135246 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00148764 0.00144592 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index 05df18fd944..f0909e951de 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 3.12 vpr 63.56 MiB -1 -1 0.88 23644 5 0.18 -1 -1 33408 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65088 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.14 146 398 73 297 28 63.6 MiB 0.03 0.00 2.15218 -93.1951 -2.15218 2.15218 0.05 0.000531567 0.000499904 0.0102703 0.00975502 -1 -1 -1 -1 8 178 24 646728 646728 33486.6 930.184 0.37 0.0711325 0.0621504 1588 8314 -1 187 26 302 650 19860 6525 2.46771 2.46771 -110.005 -2.46771 0 0 42482.2 1180.06 0.01 0.07 0.01 -1 -1 0.01 0.0278289 0.0226019 + k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.12 vpr 65.83 MiB -1 -1 0.80 26828 5 0.17 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67408 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.03 152 432 67 335 30 65.8 MiB 0.01 0.00 2.15218 -93.3318 -2.15218 2.15218 0.04 0.000541794 0.000472344 0.00646942 0.00583397 -1 -1 -1 -1 8 206 22 646728 646728 33486.6 930.184 0.18 0.0650705 0.0566044 1588 8314 -1 169 20 235 523 16218 5641 2.44258 2.44258 -104.337 -2.44258 0 0 42482.2 1180.06 0.00 0.03 0.01 -1 -1 0.00 0.0191215 0.0169186 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt index 35bd7aa8ea6..e41ab909d3a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 24.18 vpr 72.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74380 38 3 1916 1919 0 1054 173 7 7 49 clb auto 32.1 MiB 4.40 5572 10755 973 9191 591 72.6 MiB 0.34 0.01 5.10521 -15.0222 -5.10521 nan 0.24 0.00524309 0.00429013 0.156975 0.1351 -1 -1 -1 -1 162 7714 43 1.34735e+06 7.11401e+06 944075. 19266.8 15.81 3.57525 3.0646 18450 291720 -1 7029 18 5960 24809 1093324 352159 5.64405 nan -16.6537 -5.64405 0 0 1.17629e+06 24005.9 0.25 0.82 0.25 -1 -1 0.25 0.397625 0.36383 + fix_clusters_test_arch.xml apex2.blif common 14.77 vpr 75.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76916 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.4 MiB 4.62 5572 1135 0 0 1135 75.1 MiB 0.08 0.01 5.10521 -15.0504 -5.10521 nan 0.19 0.00530639 0.00465724 0.0561264 0.0529208 -1 -1 -1 -1 164 7542 34 1.34735e+06 7.11401e+06 957298. 19536.7 7.09 2.13567 1.82713 18546 296938 -1 6979 21 5560 22630 961929 323712 5.65021 nan -16.5347 -5.65021 0 0 1.19720e+06 24432.6 0.05 0.66 0.37 -1 -1 0.05 0.343651 0.311264 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index 6e10a5ba903..c4013f9bc8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 3.30 vpr 63.87 MiB -1 -1 0.94 23512 5 0.18 -1 -1 33344 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65404 10 2 181 183 1 35 24 6 6 36 clb auto 24.5 MiB 0.11 148 364 32 317 15 63.9 MiB 0.05 0.00 2.14643 -90.773 -2.14643 2.14643 0.03 0.000335395 0.000285078 0.00639243 0.00590769 -1 -1 -1 -1 12 177 21 646728 646728 19965.4 554.594 0.61 0.149391 0.122522 1696 3924 -1 153 14 202 474 9884 3007 2.16575 2.16575 -96.6802 -2.16575 0 0 25971.8 721.439 0.01 0.03 0.00 -1 -1 0.01 0.0144768 0.0129004 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.09 vpr 66.02 MiB -1 -1 0.81 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67608 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.06 152 364 33 322 9 66.0 MiB 0.01 0.00 2.14643 -90.9948 -2.14643 2.14643 0.04 0.000424487 0.000372936 0.00685813 0.00616631 -1 -1 -1 -1 12 186 21 646728 646728 19965.4 554.594 0.11 0.0652242 0.0564867 1696 3924 -1 174 15 217 480 10553 3153 2.17275 2.17275 -93.6282 -2.17275 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0180304 0.016231 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/config.txt new file mode 100644 index 00000000000..68fc81625c3 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/config.txt @@ -0,0 +1,35 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=alu4.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(alu4.pre-vpr.blif, device=mcnc_small) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(alu4.pre-vpr.blif, route_chan_width=70) + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --read_flat_place ../../../../constraints/old_placement.fplace --write_flat_place placement.fplace + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt new file mode 100644 index 00000000000..ce66e9945a6 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt @@ -0,0 +1,2 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 1.95 vpr 67.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 14 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 14 8 926 934 0 494 101 11 11 121 -1 mcnc_small 28.1 MiB 0.87 4705 3156 292 2673 191 67.8 MiB 0.15 0.01 4.69669 -33.5098 -4.69669 nan 0.00 0.00334751 0.00291356 0.0814872 0.072816 -1 -1 -1 -1 -1 6609 17 4.36541e+06 4.25763e+06 511363. 4226.14 0.32 0.279395 0.254136 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/constraints/old_placement.fplace b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/constraints/old_placement.fplace new file mode 100644 index 00000000000..6104318972c --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/constraints/old_placement.fplace @@ -0,0 +1,941 @@ +# Flat Placement File +# Auto-generated by VPR 9.0.0-dev+v8.0.0-12075-g53e90e62b-dirty +# Created: 2025-01-28T09:59:25 +# +# This file prints the following information for each atom in the netlist: +# # + +n523 6 8 0 0 3 #0 lut +n522 6 8 0 0 5 #0 lut +n520 6 8 0 0 2 #0 lut +n518 6 8 0 0 16 #0 lut +n454 6 8 0 0 4 #0 lut +n298 6 8 0 0 14 #0 lut +n214 6 8 0 0 2 #0 lut +n517 6 8 0 0 0 #0 lut +n49 6 8 0 0 9 #0 lut +n516 6 8 0 0 6 #0 lut +n48 6 8 0 0 15 #0 lut +o_4_ 6 8 0 0 1 #0 lut +n47 6 8 0 0 17 #0 lut +o_3_ 3 2 0 0 17 #1 lut +n168 3 2 0 0 2 #1 lut +n158 3 2 0 0 3 #1 lut +n157 3 2 0 0 2 #1 lut +n156 3 2 0 0 4 #1 lut +n154 3 2 0 0 5 #1 lut +n165 3 2 0 0 0 #1 lut +n113 3 2 0 0 13 #1 lut +n112 3 2 0 0 16 #1 lut +n108 3 2 0 0 15 #1 lut +n159 3 2 0 0 12 #1 lut +n107 3 2 0 0 9 #1 lut +n292 6 9 0 0 12 #2 lut +n291 6 9 0 0 5 #2 lut +n288 6 9 0 0 3 #2 lut +n287 6 9 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+n659 3 3 0 0 2 #62 lut +n607 3 3 0 0 4 #62 lut +n855 3 3 0 0 5 #62 lut +n777 3 3 0 0 17 #62 lut +n62 3 3 0 0 6 #62 lut +n788 9 5 0 0 8 #63 lut +n787 9 5 0 0 9 #63 lut +n643 9 5 0 0 2 #63 lut +n642 9 5 0 0 4 #63 lut +n638 9 5 0 0 6 #63 lut +n90 9 5 0 0 0 #63 lut +n641 9 5 0 0 4 #63 lut +n56 9 5 0 0 6 #63 lut +n637 9 5 0 0 5 #63 lut +n52 9 5 0 0 7 #63 lut +n925 1 5 0 0 3 #64 lut +n795 1 5 0 0 8 #64 lut +n924 1 5 0 0 2 #64 lut +n794 1 5 0 0 9 #64 lut +n386 1 5 0 0 2 #64 lut +n385 1 5 0 0 5 #64 lut +n307 1 5 0 0 0 #64 lut +n306 1 5 0 0 6 #64 lut +n576 1 5 0 0 4 #64 lut +n303 1 5 0 0 7 #64 lut +n824 4 6 0 0 2 #65 lut +n813 4 6 0 0 9 #65 lut +n670 4 6 0 0 3 #65 lut +n384 4 6 0 0 5 #65 lut +n132 4 6 0 0 4 #65 lut +n443 4 6 0 0 4 #65 lut +n92 4 6 0 0 6 #65 lut +n814 4 6 0 0 17 #65 lut +n177 4 6 0 0 0 #65 lut +n60 4 6 0 0 15 #65 lut +n817 1 7 0 0 8 #66 lut +n672 1 7 0 0 3 #66 lut +n671 1 7 0 0 2 #66 lut +n816 1 7 0 0 9 #66 lut +n673 1 7 0 0 4 #66 lut +n530 1 7 0 0 2 #66 lut +n834 1 7 0 0 5 #66 lut +n301 1 7 0 0 13 #66 lut +n300 1 7 0 0 0 #66 lut +n299 1 7 0 0 15 #66 lut +n830 4 1 0 0 9 #67 lut +n653 4 1 0 0 0 #67 lut +n614 4 1 0 0 4 #67 lut +n611 4 1 0 0 4 #67 lut +n585 4 1 0 0 3 #67 lut +n652 4 1 0 0 5 #67 lut +n496 4 1 0 0 13 #67 lut +n539 4 1 0 0 7 #67 lut +n396 4 1 0 0 2 #67 lut +n155 4 1 0 0 17 #67 lut +n781 8 3 0 0 0 #68 lut +n841 8 3 0 0 9 #68 lut +n646 8 3 0 0 8 #68 lut +n640 8 3 0 0 15 #68 lut +n493 8 3 0 0 2 #68 lut +n362 8 3 0 0 3 #68 lut +n345 8 3 0 0 2 #68 lut +n160 8 3 0 0 13 #68 lut +n656 8 3 0 0 4 #68 lut +n58 8 3 0 0 5 #68 lut +n900 7 5 0 0 8 #69 lut +n887 7 5 0 0 7 #69 lut +n885 7 5 0 0 9 #69 lut +n883 7 5 0 0 6 #69 lut +n890 7 5 0 0 0 #69 lut +n487 7 5 0 0 2 #69 lut +n368 7 5 0 0 5 #69 lut +n335 7 5 0 0 4 #69 lut +n179 7 5 0 0 3 #69 lut +n34 7 5 0 0 2 #69 lut +n599 6 1 0 0 3 #70 lut +n603 6 1 0 0 4 #70 lut +n408 6 1 0 0 7 #70 lut +n403 6 1 0 0 13 #70 lut +n597 6 1 0 0 2 #70 lut +n402 6 1 0 0 5 #70 lut +n873 6 1 0 0 12 #70 lut +n340 6 1 0 0 2 #70 lut +n575 6 1 0 0 8 #70 lut +n211 6 1 0 0 9 #70 lut +n190 6 1 0 0 0 #70 lut +n667 1 1 0 0 0 #71 lut +n660 1 1 0 0 2 #71 lut +n593 1 1 0 0 5 #71 lut +n584 1 1 0 0 3 #71 lut +n594 1 1 0 0 4 #71 lut +n581 1 1 0 0 8 #71 lut +n525 1 1 0 0 4 #71 lut +n315 1 1 0 0 7 #71 lut +n314 1 1 0 0 6 #71 lut +n313 1 1 0 0 9 #71 lut +n878 9 8 0 0 6 #72 lut +n875 9 8 0 0 2 #72 lut +n874 9 8 0 0 0 #72 lut +n872 9 8 0 0 4 #72 lut +n389 9 8 0 0 8 #72 lut +n383 9 8 0 0 9 #72 lut +n97 9 8 0 0 5 #72 lut +n88 9 8 0 0 8 #72 lut +n879 9 8 0 0 7 #72 lut +n86 9 8 0 0 6 #72 lut +n451 9 9 0 0 8 #73 lut +n632 9 9 0 0 5 #73 lut +n450 9 9 0 0 7 #73 lut +n445 9 9 0 0 6 #73 lut +n436 9 9 0 0 9 #73 lut +n536 2 2 0 0 17 #74 lut +n535 2 2 0 0 9 #74 lut +n169 2 2 0 0 4 #74 lut +n528 2 2 0 0 13 #74 lut +n125 2 2 0 0 0 #74 lut +n116 2 2 0 0 5 #74 lut +n544 2 2 0 0 7 #74 lut +n167 2 2 0 0 2 #74 lut +n115 2 2 0 0 5 #74 lut +n110 2 2 0 0 6 #74 lut +n473 2 2 0 0 1 #74 lut +n109 2 2 0 0 4 #74 lut +n639 9 4 0 0 5 #75 lut +n798 9 4 0 0 6 #75 lut +n629 9 4 0 0 9 #75 lut +n361 9 4 0 0 15 #75 lut +n349 9 4 0 0 17 #75 lut +n527 8 2 0 0 6 #76 lut +n254 8 2 0 0 17 #76 lut +n176 8 2 0 0 15 #76 lut +n76 8 2 0 0 9 #76 lut +n923 1 9 0 0 17 #77 lut +n268 1 9 0 0 19 #77 lut +out:o_3_ 3 0 0 4 0 #78 outpad +out:o_4_ 10 8 0 7 0 #79 outpad +out:o_5_ 3 0 0 3 0 #80 outpad +out:o_7_ 5 0 0 5 0 #81 outpad +out:o_2_ 8 0 0 3 0 #82 outpad +out:o_6_ 10 3 0 6 0 #83 outpad +out:o_1_ 7 0 0 5 0 #84 outpad +out:o_0_ 7 0 0 2 0 #85 outpad +i_0_ 5 0 0 0 0 #86 inpad +i_10_ 5 0 0 1 0 #87 inpad +i_11_ 6 0 0 0 0 #88 inpad +i_12_ 5 0 0 3 0 #89 inpad +i_13_ 4 0 0 1 0 #90 inpad +i_1_ 3 0 0 0 0 #91 inpad +i_2_ 5 0 0 2 0 #92 inpad +i_3_ 4 0 0 3 0 #93 inpad +i_4_ 5 0 0 6 0 #94 inpad +i_5_ 5 10 0 0 0 #95 inpad +i_6_ 5 0 0 4 0 #96 inpad +i_7_ 4 0 0 6 0 #97 inpad +i_8_ 5 0 0 7 0 #98 inpad +i_9_ 6 0 0 4 0 #99 inpad diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index f954a2b1702..e37401667f7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.56 vpr 77.04 MiB -1 -1 3.92 32680 16 0.60 -1 -1 34972 -1 -1 60 45 3 1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 78892 45 32 1192 1151 1 782 141 14 14 196 memory auto 38.2 MiB 2.96 6987 30885 8485 19109 3291 77.0 MiB 1.25 0.02 10.7872 -7159.4 -10.7872 10.7872 0.01 0.00497106 0.00453777 0.461478 0.422614 -1 -1 -1 -1 -1 10741 14 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.03 0.580473 0.527495 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 13.38 vpr 77.06 MiB -1 -1 3.60 32516 16 0.58 -1 -1 34992 -1 -1 60 45 3 1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 78912 45 32 1192 1151 1 782 141 14 14 196 memory auto 38.2 MiB 2.94 6987 30885 8485 19109 3291 77.1 MiB 1.04 0.01 10.7872 -7159.4 -10.7872 10.7872 0.00 0.00222077 0.00193155 0.339907 0.301027 -1 -1 -1 -1 -1 10825 14 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.22 0.417402 0.352766 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.85 vpr 79.08 MiB -1 -1 3.58 35500 16 0.65 -1 -1 38580 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80980 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.0 MiB 3.23 6742 28689 8224 17037 3428 79.1 MiB 0.65 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00310914 0.00279648 0.314019 0.270375 -1 -1 -1 -1 -1 10349 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.50 0.423776 0.367585 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 12.82 vpr 78.98 MiB -1 -1 3.48 35500 16 0.73 -1 -1 38088 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80880 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.1 MiB 3.28 6742 28689 8224 17037 3428 79.0 MiB 0.59 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00230907 0.0018852 0.209392 0.171163 -1 -1 -1 -1 -1 10313 15 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.42 0.342057 0.287674 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 24daf2d2e35..120190057e8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 32.00 vpr 84.00 MiB -1 -1 4.94 43052 3 0.95 -1 -1 38056 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86016 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 43.4 MiB 3.67 13419 262125 90999 150942 20184 84.0 MiB 2.78 0.03 4.69737 -2831.91 -4.69737 4.69737 1.01 0.00832504 0.00776365 0.932353 0.847983 -1 -1 -1 -1 66 27201 39 1.65001e+07 9.87633e+06 1.15238e+06 3192.19 11.80 3.82946 3.48711 36241 234685 -1 22898 17 6143 16341 1829326 503243 5.28065 5.28065 -3148.98 -5.28065 0 0 1.43513e+06 3975.42 0.58 0.95 0.26 -1 -1 0.58 0.436495 0.407813 - buffered_flyover_wires.xml raygentop.v common 32.17 vpr 84.02 MiB -1 -1 4.60 43460 3 0.83 -1 -1 38072 -1 -1 129 236 1 6 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86032 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 43.3 MiB 3.46 14176 262125 95409 146838 19878 84.0 MiB 2.60 0.03 5.30111 -3035.02 -5.30111 5.30111 0.96 0.0108245 0.0101036 0.99455 0.909375 -1 -1 -1 -1 68 26718 29 1.65001e+07 9.87633e+06 1.22105e+06 3382.40 12.62 4.02255 3.63163 36601 236909 -1 22839 20 6287 16443 1625103 418922 5.52369 5.52369 -3272.68 -5.52369 0 0 1.52022e+06 4211.15 0.57 1.21 0.35 -1 -1 0.57 0.599325 0.559459 + shorted_flyover_wires.xml raygentop.v common 28.09 vpr 86.75 MiB -1 -1 4.22 45380 3 0.89 -1 -1 40652 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88832 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.9 MiB 3.72 13488 259154 85177 151229 22748 86.8 MiB 1.98 0.02 4.96832 -2863.05 -4.96832 4.96832 0.58 0.00616009 0.0056108 0.73686 0.651724 -1 -1 -1 -1 70 25183 26 1.65001e+07 9.87633e+06 1.20853e+06 3347.73 11.82 3.63311 3.252 37321 249029 -1 22818 16 6009 15172 1561129 440571 5.14889 5.14889 -3166.68 -5.14889 0 0 1.52253e+06 4217.55 0.11 0.96 0.44 -1 -1 0.11 0.466679 0.43649 + buffered_flyover_wires.xml raygentop.v common 23.51 vpr 86.14 MiB -1 -1 4.32 45316 3 0.90 -1 -1 40936 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88212 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 3.23 13888 238357 80681 139370 18306 86.1 MiB 2.42 0.04 5.12299 -3013.43 -5.12299 5.12299 0.55 0.0104225 0.00890059 0.853806 0.753587 -1 -1 -1 -1 68 27200 39 1.65001e+07 9.87633e+06 1.22105e+06 3382.40 7.94 3.27933 2.93318 36601 236909 -1 22538 20 6241 16122 1654804 449740 5.13382 5.13382 -3162.81 -5.13382 0 0 1.52022e+06 4211.15 0.06 0.81 0.27 -1 -1 0.06 0.458331 0.421893 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index d0dca393ab5..dabc7597d44 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 7.03 vpr 62.24 MiB -1 -1 0.19 18436 1 0.05 -1 -1 30832 -1 -1 0 193 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63736 193 32 545 422 1 386 228 22 22 484 block_FPU auto 22.7 MiB 4.82 4750 57300 25032 31924 344 62.2 MiB 0.33 0.00 2.985 -849.007 -2.985 2.985 0.00 0.00155598 0.00146459 0.152665 0.144051 -1 -1 -1 -1 6282 16.3169 1670 4.33766 556 556 206642 56826 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -872.623 -2.985 -13.6498 -0.0851 0.35 -1 -1 62.2 MiB 0.08 0.182075 0.172086 62.2 MiB -1 0.64 + hard_fpu_arch_timing.xml mm3.v common 6.82 vpr 64.38 MiB -1 -1 0.19 22024 1 0.04 -1 -1 33832 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65924 193 32 545 422 1 386 228 22 22 484 block_FPU auto 25.0 MiB 5.38 4984 53124 22938 29850 336 64.4 MiB 0.31 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00244064 0.00235262 0.159831 0.149979 -1 -1 -1 -1 6456 16.7688 1716 4.45714 553 553 191807 53335 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.692 -2.985 -13.5705 -0.0851 0.36 -1 -1 64.4 MiB 0.06 0.186546 0.175569 64.4 MiB -1 0.10 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index 6ed66139c02..e0477400548 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 5.17 vpr 65.73 MiB -1 -1 0.40 18728 3 0.11 -1 -1 33272 -1 -1 67 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67312 99 130 344 474 1 216 297 13 13 169 clb auto 26.0 MiB 1.28 607 28017 3739 9020 15258 65.7 MiB 0.15 0.02 36 1079 9 0 0 481804. 2850.91 1.81 + k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.15 vpr 68.14 MiB -1 -1 0.41 22436 3 0.11 -1 -1 37108 -1 -1 67 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69772 99 130 344 474 1 216 297 13 13 169 clb auto 28.7 MiB 1.30 640 27027 4243 10587 12197 68.1 MiB 0.05 0.00 34 1346 6 0 0 460544. 2725.11 1.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index 2c9a5886623..cf73f2ff4e0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.10 vpr 63.56 MiB -1 -1 0.72 23528 5 0.17 -1 -1 33348 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65088 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.05 146 398 72 298 28 63.6 MiB 0.05 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.00155607 0.00152058 0.00827603 0.00776724 -1 -1 -1 -1 -1 136 16 646728 646728 60312.4 1675.34 0.04 0.0269483 0.0244827 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.78 vpr 66.14 MiB -1 -1 0.81 27148 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67724 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000401166 0.00034964 0.00709766 0.00632609 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.027091 0.0241271 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index f44d6074687..f56e6001d52 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.57 vpr 58.03 MiB -1 -1 -1 -1 0 0.02 -1 -1 30200 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59420 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.3 MiB 0.01 0 3 0 0 3 58.0 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2173e-05 7.189e-06 7.7955e-05 5.3274e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00145604 0.00138979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.57 vpr 58.07 MiB -1 -1 -1 -1 0 0.02 -1 -1 30092 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59460 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.3 MiB 0.01 0 3 0 0 3 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3368e-05 7.369e-06 8.1255e-05 5.3678e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00262216 0.00254632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.53 vpr 58.11 MiB -1 -1 -1 -1 0 0.02 -1 -1 30152 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59500 6 1 1 8 0 1 8 3 3 9 -1 auto 19.7 MiB 0.00 0 21 0 10 11 58.1 MiB 0.05 0.00 nan 0 0 nan 0.00 1.3668e-05 8.295e-06 0.000103636 7.3136e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00159632 0.00148892 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.50 vpr 58.05 MiB -1 -1 -1 -1 0 0.02 -1 -1 30136 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59444 6 1 1 8 0 1 8 3 3 9 -1 auto 19.6 MiB 0.00 0 21 0 10 11 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2503e-05 7.349e-06 8.2367e-05 5.6036e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.0011854 0.00111648 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.51 vpr 57.86 MiB -1 -1 -1 -1 1 0.02 -1 -1 30056 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59248 2 1 3 4 0 3 4 3 3 9 -1 auto 19.4 MiB 0.00 9 9 3 3 3 57.9 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.5257e-05 1.0806e-05 0.000104525 7.8851e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00149985 0.00142771 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.62 vpr 58.23 MiB -1 -1 -1 -1 1 0.07 -1 -1 31688 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59624 5 1 6 7 0 6 7 3 3 9 -1 auto 19.8 MiB 0.00 18 18 13 5 0 58.2 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.178e-05 1.692e-05 0.000145091 0.000118424 -1 -1 -1 -1 -1 7 11 53894 53894 38783.3 4309.26 0.01 0.00188984 0.00172965 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.63 vpr 58.03 MiB -1 -1 -1 -1 1 0.05 -1 -1 31992 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59424 5 1 6 7 0 6 7 3 3 9 -1 auto 19.6 MiB 0.00 18 18 13 5 0 58.0 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.9821e-05 1.4657e-05 0.000155383 0.000123574 -1 -1 -1 -1 -1 7 11 53894 53894 38783.3 4309.26 0.00 0.00187385 0.00170894 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.50 vpr 58.12 MiB -1 -1 -1 -1 1 0.02 -1 -1 29964 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59512 3 1 5 6 1 4 5 3 3 9 -1 auto 19.7 MiB 0.00 9 12 7 1 4 58.1 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.7793e-05 1.322e-05 0.000136996 0.00010784 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00148392 0.00140511 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.73 vpr 58.16 MiB -1 -1 -1 -1 1 0.06 -1 -1 32060 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca 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0.000106148 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00195643 0.00179437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_2x2.blif common 0.50 vpr 60.48 MiB -1 -1 -1 -1 1 0.05 -1 -1 35232 -1 -1 1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61928 4 4 8 12 0 8 9 3 3 9 -1 auto 22.1 MiB 0.00 24 27 18 6 3 60.5 MiB 0.00 0.00 0.67231 -2.68924 -0.67231 nan 0.00 5.0286e-05 3.8471e-05 0.00028724 0.000243111 -1 -1 -1 -1 -1 10 10 53894 53894 38783.3 4309.26 0.00 0.00268807 0.00242566 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_3x3.blif common 0.52 vpr 60.40 MiB -1 -1 -1 -1 1 0.07 -1 -1 36088 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61848 6 6 12 18 0 12 13 3 3 9 -1 auto 22.1 MiB 0.01 36 43 32 7 4 60.4 MiB 0.00 0.00 0.69831 -4.13786 -0.69831 nan 0.00 5.0007e-05 4.1034e-05 0.000382344 0.000335402 -1 -1 -1 -1 -1 17 12 53894 53894 38783.3 4309.26 0.00 0.00342842 0.00312147 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_3x4.blif common 0.46 vpr 60.50 MiB -1 -1 -1 -1 2 0.06 -1 -1 35480 -1 -1 3 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61952 7 8 22 30 0 15 18 4 4 16 clb auto 22.0 MiB 0.01 51 64 26 37 1 60.5 MiB 0.00 0.00 1.24888 -7.62396 -1.24888 nan 0.00 9.577e-05 8.3665e-05 0.00076909 0.000710256 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00462233 0.00417537 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_4x4.blif common 0.59 vpr 60.60 MiB -1 -1 -1 -1 4 0.09 -1 -1 35628 -1 -1 2 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62056 8 8 29 37 0 21 18 4 4 16 clb auto 22.1 MiB 0.02 74 64 20 44 0 60.6 MiB 0.00 0.00 2.04839 -11.7951 -2.04839 nan 0.00 0.000130354 0.000112521 0.00109012 0.00100934 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.01 0.00751475 0.0068714 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_5x5.blif common 0.62 vpr 61.08 MiB -1 -1 -1 -1 4 0.10 -1 -1 36048 -1 -1 4 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62548 10 10 47 57 0 39 24 4 4 16 clb auto 22.1 MiB 0.02 149 92 35 57 0 61.1 MiB 0.00 0.00 2.73035 -18.1288 -2.73035 nan 0.00 0.000192825 0.000170363 0.0016493 0.0015433 -1 -1 -1 -1 -1 123 10 215576 215576 99039.1 6189.95 0.01 0.00945092 0.00871858 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_5x6.blif common 0.78 vpr 61.08 MiB -1 -1 -1 -1 5 0.12 -1 -1 36408 -1 -1 5 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62544 11 11 61 72 0 51 27 5 5 25 clb auto 22.1 MiB 0.04 192 547 116 431 0 61.1 MiB 0.01 0.00 3.17925 -21.2667 -3.17925 nan 0.00 0.000440575 0.000406236 0.00673609 0.00616031 -1 -1 -1 -1 -1 163 16 485046 269470 186194. 7447.77 0.02 0.0214973 0.0195896 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_1bit.blif common 0.44 vpr 60.18 MiB -1 -1 -1 -1 1 0.05 -1 -1 34452 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61628 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.2 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 1.5359e-05 1.1242e-05 0.000119111 9.5167e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00191506 0.00178438 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_2bit.blif common 0.51 vpr 60.47 MiB -1 -1 -1 -1 1 0.06 -1 -1 35224 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61920 5 3 8 11 0 8 9 3 3 9 -1 auto 22.0 MiB 0.00 24 27 21 6 0 60.5 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 5.5301e-05 4.4627e-05 0.000313259 0.000267198 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00296269 0.00261801 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_3bit.blif common 0.50 vpr 60.56 MiB -1 -1 -1 -1 2 0.05 -1 -1 35444 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62016 7 4 12 16 0 11 12 3 3 9 -1 auto 22.1 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 2.6083e-05 2.0859e-05 0.000215587 0.000188913 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00234895 0.0022029 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_4bit.blif common 0.54 vpr 60.64 MiB -1 -1 -1 -1 2 0.06 -1 -1 35364 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62096 9 5 15 20 0 14 15 3 3 9 -1 auto 22.1 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 0.000111332 9.9634e-05 0.000559539 0.000502391 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00351338 0.00318651 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_5bit.blif common 0.52 vpr 60.46 MiB -1 -1 -1 -1 3 0.07 -1 -1 35520 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 11 6 19 25 0 17 18 3 3 9 -1 auto 22.0 MiB 0.01 51 64 33 24 7 60.5 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 0.000697205 8.3358e-05 0.00115444 0.000499005 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00500091 0.00398839 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index e60168a24fc..b020b50a0e5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.48 vpr 58.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59516 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.4 MiB 0.01 0 3 0 0 3 58.1 MiB 0.03 0.00 nan 0 0 nan 0.00 2.8167e-05 2.1374e-05 0.000138034 0.000104949 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.02 0.00164424 0.00155782 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.44 vpr 58.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59464 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.4 MiB 0.02 0 3 0 0 3 58.1 MiB 0.01 0.00 nan 0 0 nan 0.00 1.4897e-05 9.304e-06 0.000144669 0.000111339 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.001404 0.00131834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.50 vpr 58.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59556 6 1 7 8 0 7 8 3 3 9 -1 auto 19.7 MiB 0.04 21 21 14 7 0 58.2 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4462e-05 1.7786e-05 0.000174928 0.000147981 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00186761 0.00178528 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.36 vpr 58.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59504 6 1 7 8 0 7 8 3 3 9 -1 auto 19.7 MiB 0.01 21 21 14 7 0 58.1 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 3.4347e-05 2.5128e-05 0.000218139 0.000181445 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.01 0.00178448 0.00167632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.46 vpr 58.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59532 5 1 6 7 0 6 7 3 3 9 -1 auto 19.7 MiB 0.03 18 18 13 5 0 58.1 MiB 0.01 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.2294e-05 1.7287e-05 0.000170669 0.000137343 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00177813 0.00167987 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.46 vpr 57.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59356 5 1 6 7 0 6 7 3 3 9 -1 auto 19.5 MiB 0.01 18 18 13 5 0 58.0 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.6482e-05 2.0958e-05 0.000167987 0.000138916 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00184976 0.00175645 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml const_true.blif common 0.27 vpr 60.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61896 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.1 MiB 0.00 0 3 0 0 3 60.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1967e-05 6.442e-06 7.5021e-05 4.7762e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.0014839 0.00141592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2368e-05 6.553e-06 8.0604e-05 5.2726e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00150763 0.00143643 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml always_true.blif common 0.26 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4901e-05 1.736e-05 0.000158286 0.000127589 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00189837 0.00180984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4603e-05 1.7125e-05 0.000156465 0.000123185 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00157342 0.00148859 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.34 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 5 1 6 7 0 6 7 3 3 9 -1 auto 22.3 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.3071e-05 1.7468e-05 0.00015565 0.000122418 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00131998 0.0012364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4504e-05 1.843e-05 0.0003637 0.000327179 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00295184 0.00278863 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index f1456d39f78..0122eef07c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 2.50 vpr 64.46 MiB -1 -1 0.75 23544 5 0.17 -1 -1 33432 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66008 10 2 181 183 1 37 19 6 6 36 clb auto 24.9 MiB 0.12 134 94 36 51 7 64.5 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000419945 0.000386338 0.00436349 0.00416636 -1 -1 -1 -1 8 103 5 646728 377258 -1 -1 0.16 0.0505805 0.044298 1804 2280 -1 90 3 63 87 2113 862 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0115138 0.0109218 - x_uniform_y_gaussian.xml stereovision3.v common 2.93 vpr 64.41 MiB -1 -1 0.95 23552 5 0.18 -1 -1 33464 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65960 10 2 181 183 1 37 19 6 6 36 clb auto 25.0 MiB 0.12 118 444 110 303 31 64.4 MiB 0.10 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000424537 0.000389976 0.0151343 0.0142881 -1 -1 -1 -1 6 94 8 646728 377258 -1 -1 0.27 0.0803322 0.0718366 1804 2280 -1 80 4 81 108 2550 1058 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.04 0.00 -1 -1 0.00 0.0129948 0.0121942 - x_gaussian_y_gaussian.xml stereovision3.v common 2.83 vpr 64.50 MiB -1 -1 0.72 23552 5 0.18 -1 -1 33328 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66048 10 2 181 183 1 37 19 6 6 36 clb auto 25.0 MiB 0.11 136 619 179 400 40 64.5 MiB 0.04 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000378245 0.00034659 0.012211 0.0113438 -1 -1 -1 -1 6 97 4 646728 377258 -1 -1 0.43 0.0657561 0.0581881 1804 2280 -1 98 4 73 101 2523 1078 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0125128 0.0117068 - x_delta_y_uniform.xml stereovision3.v common 2.97 vpr 64.45 MiB -1 -1 0.81 23464 5 0.16 -1 -1 33468 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66000 10 2 181 183 1 37 19 6 6 36 clb auto 25.0 MiB 0.11 134 594 154 411 29 64.5 MiB 0.04 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000357443 0.000325029 0.012514 0.0116263 -1 -1 -1 -1 10 110 10 646728 377258 -1 -1 0.50 0.0892176 0.0778872 1804 2280 -1 97 3 69 90 2241 1045 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0105891 0.0100407 - x_delta_y_delta.xml stereovision3.v common 3.05 vpr 64.40 MiB -1 -1 0.95 23336 5 0.17 -1 -1 33436 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65948 10 2 181 183 1 37 19 6 6 36 clb auto 24.8 MiB 0.13 134 719 153 522 44 64.4 MiB 0.03 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.00034865 0.000319263 0.012511 0.0115452 -1 -1 -1 -1 28 92 3 646728 377258 -1 -1 0.31 0.0600241 0.0529562 1804 2280 -1 92 3 65 87 2209 903 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00975621 0.00926591 - x_uniform_y_delta.xml stereovision3.v common 3.23 vpr 64.80 MiB -1 -1 0.91 23548 5 0.16 -1 -1 33324 -1 -1 7 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66352 10 2 181 183 1 37 19 6 6 36 clb auto 25.3 MiB 0.17 122 594 108 447 39 64.8 MiB 0.05 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000523952 0.000483044 0.0169912 0.0158055 -1 -1 -1 -1 8 96 8 646728 377258 -1 -1 0.55 0.0887084 0.0783823 1804 2280 -1 82 4 82 115 2881 1166 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0137495 0.0129694 + x_gaussian_y_uniform.xml stereovision3.v common 2.14 vpr 66.94 MiB -1 -1 0.82 26648 5 0.18 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.08 154 69 23 41 5 66.9 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000368162 0.000336195 0.00306832 0.0028942 -1 -1 -1 -1 8 112 5 646728 377258 -1 -1 0.14 0.0630721 0.0541641 1804 2280 -1 112 3 60 81 2140 1007 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0123441 0.0115171 + x_uniform_y_gaussian.xml stereovision3.v common 2.28 vpr 66.56 MiB -1 -1 0.87 27028 5 0.18 -1 -1 36836 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68156 10 2 181 183 1 37 19 6 6 36 clb auto 27.6 MiB 0.06 139 119 44 63 12 66.6 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000434392 0.000379213 0.00478977 0.00443186 -1 -1 -1 -1 8 108 4 646728 377258 -1 -1 0.14 0.0614636 0.053576 1804 2280 -1 92 5 93 129 3144 1427 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0131686 0.0124064 + x_gaussian_y_gaussian.xml stereovision3.v common 1.95 vpr 66.73 MiB -1 -1 0.78 27032 5 0.16 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 141 69 21 42 6 66.7 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000231421 0.000200473 0.00279286 0.00262007 -1 -1 -1 -1 6 107 4 646728 377258 -1 -1 0.13 0.0525266 0.046082 1804 2280 -1 105 4 77 102 2777 1152 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.0109087 0.0101911 + x_delta_y_uniform.xml stereovision3.v common 2.13 vpr 66.94 MiB -1 -1 0.67 26768 5 0.15 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.07 154 369 96 253 20 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000435432 0.00038302 0.00911423 0.00823072 -1 -1 -1 -1 24 117 4 646728 377258 -1 -1 0.31 0.174316 0.150618 1804 2280 -1 116 2 59 79 2150 954 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153537 0.0147732 + x_delta_y_delta.xml stereovision3.v common 2.28 vpr 66.92 MiB -1 -1 0.81 26892 5 0.18 -1 -1 36968 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68524 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.10 140 544 127 376 41 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000465798 0.000412818 0.0124105 0.0110487 -1 -1 -1 -1 48 106 2 646728 377258 -1 -1 0.23 0.117282 0.102085 1804 2280 -1 106 2 57 77 1975 772 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00952273 0.00912406 + x_uniform_y_delta.xml stereovision3.v common 2.20 vpr 66.74 MiB -1 -1 0.80 27028 5 0.22 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68344 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 127 494 89 373 32 66.7 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000426768 0.000373257 0.0117897 0.0105633 -1 -1 -1 -1 14 88 2 646728 377258 -1 -1 0.16 0.10372 0.0914305 1804 2280 -1 88 2 57 77 1819 773 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00845179 0.00814396 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 5deaea47b22..93fc1046440 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 3.07 vpr 63.59 MiB -1 -1 0.86 23288 5 0.17 -1 -1 33328 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65116 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.19 146 296 74 208 14 63.6 MiB 0.05 0.00 1.83894 -73.7881 -1.83894 1.83894 0.01 0.000559275 0.000518705 0.00642835 0.00601498 -1 -1 -1 -1 6 101 15 646728 646728 -1 -1 0.25 0.0569513 0.0489151 1456 2040 -1 103 15 135 292 9517 3756 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.020878 0.0186817 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 3.02 vpr 63.67 MiB -1 -1 0.85 23532 5 0.17 -1 -1 33404 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65196 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.17 168 92 36 52 4 63.7 MiB 0.03 0.00 1.83894 -73.7881 -1.83894 1.83894 0.01 0.000555491 0.000512753 0.00380765 0.00362071 -1 -1 -1 -1 8 118 19 646728 646728 -1 -1 0.31 0.0661579 0.056778 1456 2040 -1 117 17 137 275 9561 3757 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.019218 0.0171455 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 3.34 vpr 63.68 MiB -1 -1 0.88 23640 5 0.17 -1 -1 33452 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65212 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.11 166 92 33 54 5 63.7 MiB 0.01 0.00 1.83894 -73.7881 -1.83894 1.83894 0.01 0.000388369 0.000355547 0.00307054 0.00291066 -1 -1 -1 -1 6 122 17 646728 646728 -1 -1 0.56 0.0873244 0.0750472 1456 2040 -1 119 17 156 331 12004 4413 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.01 0.09 0.00 -1 -1 0.01 0.0185307 0.0163935 + timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.95 vpr 65.89 MiB -1 -1 0.73 26760 5 0.17 -1 -1 36900 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67476 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.04 153 500 90 382 28 65.9 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000660248 0.000574242 0.010203 0.00905969 -1 -1 -1 -1 6 103 13 646728 646728 -1 -1 0.12 0.059948 0.0525698 1456 2040 -1 101 16 136 266 9131 3659 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0191372 0.0164753 + nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.99 vpr 66.10 MiB -1 -1 0.79 27276 5 0.17 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67688 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 148 466 75 365 26 66.1 MiB 0.01 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000394392 0.000346251 0.00742774 0.00666175 -1 -1 -1 -1 8 100 16 646728 646728 -1 -1 0.14 0.0718777 0.0632492 1456 2040 -1 101 19 134 278 9113 3613 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0163481 0.014725 + nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 2.10 vpr 66.14 MiB -1 -1 0.85 26896 5 0.16 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67728 10 2 181 183 1 35 24 6 6 36 clb auto 27.1 MiB 0.05 142 500 108 364 28 66.1 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000538248 0.000486042 0.00902515 0.00805903 -1 -1 -1 -1 4 86 10 646728 646728 -1 -1 0.05 0.0281105 0.0249862 1456 2040 -1 87 9 108 188 5936 2196 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153203 0.0141626 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt index e3c0e629bee..afb5b419a6b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 6.64 vpr 63.57 MiB -1 -1 0.94 23536 5 0.18 -1 -1 33400 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65096 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.12 146 398 72 298 28 63.6 MiB 2.11 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000561388 0.000519811 0.00818763 0.0076223 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 1.07 0.0306154 0.0272041 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 5.23 vpr 66.07 MiB -1 -1 0.81 27256 5 0.19 -1 -1 36672 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67656 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 1.88 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000389361 0.000337837 0.00712682 0.00635643 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.83 0.023313 0.0208517 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index e14d1bfdf94..0cf367e9bdb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 3.07 vpr 59.20 MiB -1 -1 0.88 23388 5 0.18 -1 -1 33556 -1 -1 7 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60616 10 2 181 183 1 37 19 5 5 25 clb auto 19.7 MiB 0.15 121 1025 805 184 36 59.2 MiB 0.09 0.00 2.09443 -87.1664 -2.09443 2.09443 0.03 0.000344616 0.000312911 0.0199094 0.0182425 -1 -1 -1 -1 26 127 8 485046 377258 31702.9 1268.11 0.17 0.0666235 0.0582058 1731 5512 -1 104 4 50 68 870 379 1.97939 1.97939 -86.3228 -1.97939 0 0 38596.5 1543.86 0.01 0.02 0.01 -1 -1 0.01 0.0131087 0.0124132 + k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 61.52 MiB -1 -1 0.73 27008 5 0.16 -1 -1 36840 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63000 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.06 123 1025 767 190 68 61.5 MiB 0.03 0.00 2.0306 -84.8829 -2.0306 2.0306 0.02 0.000393487 0.000346106 0.0203419 0.0179997 -1 -1 -1 -1 24 106 9 485046 377258 28445.8 1137.83 0.08 0.0705347 0.0617863 1707 5297 -1 110 10 80 114 1470 618 1.99984 1.99984 -90.3874 -1.99984 0 0 37126.9 1485.07 0.00 0.02 0.01 -1 -1 0.00 0.0158626 0.0146013 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 9aed323e6ef..891302c2b5a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 16.80 vpr 68.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70624 64 39 1935 1974 1 1077 541 23 23 529 clb auto 28.7 MiB 0.57 10085 137127 36539 98027 2561 69.0 MiB 1.34 0.02 7.41831 -1418.64 -7.41831 7.41831 0.90 0.00601444 0.00513019 0.406605 0.350409 -1 -1 -1 -1 22 12754 28 983127 976439 735934. 1391.18 8.73 1.26384 1.10229 35322 121345 -1 11109 19 6608 23845 1462488 382373 7.14816 7.14816 -1474.13 -7.14816 0 0 927497. 1753.30 0.22 1.14 0.18 -1 -1 0.22 0.297141 0.268933 - k4_N4_90nm.xml ex5p.blif common 33.10 vpr 64.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66128 8 63 1072 1135 0 894 437 22 22 484 clb auto 25.2 MiB 0.53 11802 104828 31007 71723 2098 64.6 MiB 1.03 0.01 6.54351 -290.193 -6.54351 nan 0.84 0.00302532 0.00273057 0.23164 0.202551 -1 -1 -1 -1 34 15886 35 891726 815929 1.00654e+06 2079.64 26.00 1.17739 1.02035 45600 169672 -1 13479 18 7616 26985 2968727 818222 6.43932 nan -293.77 -6.43932 0 0 1.27783e+06 2640.15 0.27 1.08 0.23 -1 -1 0.27 0.174257 0.159401 - k4_N4_90nm.xml s298.blif common 59.37 vpr 70.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 72572 4 6 1942 1948 1 1169 590 27 27 729 clb auto 30.8 MiB 0.71 13579 163808 47993 114862 953 70.9 MiB 1.54 0.02 12.0403 -94.3066 -12.0403 12.0403 1.19 0.00712795 0.00624279 0.42831 0.361816 -1 -1 -1 -1 24 19358 45 1.39333e+06 1.29301e+06 1.12265e+06 1539.99 49.71 2.08623 1.76329 54650 192211 -1 16862 23 9147 49878 4855038 894292 11.751 11.751 -96.5615 -11.751 0 0 1.47093e+06 2017.74 0.23 1.67 0.23 -1 -1 0.23 0.291349 0.252446 + k4_N4_90nm.xml diffeq.blif common 17.21 vpr 71.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72880 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.3 MiB 0.39 10472 141533 36950 100839 3744 71.2 MiB 1.37 0.02 7.46482 -1369.01 -7.46482 7.46482 0.56 0.00521343 0.00460525 0.3928 0.329697 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.35 2.1497 1.85535 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.84 0.19 -1 -1 0.04 0.261179 0.233132 + k4_N4_90nm.xml ex5p.blif common 19.31 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68632 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.35 12004 99857 28319 69545 1993 67.0 MiB 0.94 0.02 6.86459 -313.968 -6.86459 nan 0.53 0.00337095 0.00291084 0.218826 0.187023 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 13.54 0.813128 0.698644 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.07 1.22 0.29 -1 -1 0.07 0.185657 0.165735 + k4_N4_90nm.xml s298.blif common 16.74 vpr 73.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 75068 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.1 MiB 0.44 13813 156389 45768 109723 898 73.3 MiB 1.71 0.02 12.2682 -96.384 -12.2682 12.2682 0.97 0.00611806 0.00498358 0.468986 0.387941 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 9.00 1.38473 1.15574 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.09 1.18 0.31 -1 -1 0.09 0.19019 0.169418 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index 7488fc485ca..639ae9a9ce5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.06 vpr 66.74 MiB -1 -1 0.84 23300 4 0.16 -1 -1 33000 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68340 11 2 303 283 2 81 28 7 7 49 clb auto 27.1 MiB 0.31 332 112 32 50 30 66.7 MiB 0.08 0.00 4.11769 0 0 3.94108 0.00 0.000680828 0.000618524 0.00645732 0.00621036 -1 -1 -1 -1 376 5.01333 137 1.82667 145 200 4055 1170 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.1682 4.01568 0 0 -197.816 -1.707 0.03 -1 -1 66.7 MiB 0.25 0.145887 0.141249 66.7 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.46 vpr 69.17 MiB -1 -1 0.83 26540 4 0.20 -1 -1 36184 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.25 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.00065953 0.000573934 0.00619824 0.00583905 -1 -1 -1 -1 399 5.32000 131 1.74667 151 217 4511 1215 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.12 0.1152 0.11141 69.2 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index d1daf36ffe7..7e566048732 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index 3c39979a687..4db4b05c471 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 4.77 vpr 65.80 MiB -1 -1 0.46 18964 3 0.10 -1 -1 33220 -1 -1 65 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67380 99 130 344 474 1 215 295 12 12 144 clb auto 26.4 MiB 0.23 697 24820 2926 7450 14444 65.8 MiB 0.12 0.00 34 1759 11 5.66058e+06 4.05111e+06 317980. 2208.19 1.87 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.05 vpr 68.36 MiB -1 -1 0.39 22432 3 0.12 -1 -1 36928 -1 -1 65 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70000 99 130 344 474 1 215 295 12 12 144 clb auto 29.2 MiB 0.19 685 24820 3391 8404 13025 68.4 MiB 0.05 0.00 32 1772 8 5.66058e+06 4.05111e+06 305575. 2122.05 1.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt index 5c92701e534..59b02c3fd0e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links - stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 136.64 vpr 1.09 GiB -1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1147416 2 32 2204 1661 1 1102 107 36 20 720 -1 EP4SGX110 953.4 MiB 4.30 6502 9974 2102 7079 793 1120.5 MiB 0.78 0.01 7.29374 -4454.07 -7.29374 7.29374 29.53 0.00640333 0.00571002 0.281115 0.249799 150 8929 16 0 0 6.74655e+06 9370.21 54.95 2.8097 2.42985 174956 1462490 -1 8744 15 2461 4687 960144 259555 7.40783 7.40783 -4699.44 -7.40783 0 0 8.72662e+06 12120.3 4.44 0.55 3.61 -1 -1 4.44 0.254443 0.230607 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 + stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 104.06 vpr 1.07 GiB -1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1126272 2 32 2204 1661 1 1102 107 36 20 720 -1 EP4SGX110 955.6 MiB 4.04 6649 10733 2374 7396 963 1099.9 MiB 0.85 0.01 7.22684 -4978.81 -7.22684 7.22684 14.03 0.00387297 0.00336653 0.329346 0.282395 154 8599 14 0 0 6.94291e+06 9642.93 42.85 2.6403 2.32523 176404 1494154 -1 8630 10 2443 4554 1083511 308854 7.50808 7.50808 -5329.84 -7.50808 0 0 8.91809e+06 12386.2 1.07 0.65 2.72 -1 -1 1.07 0.27806 0.251316 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index 09ce4f7b64a..b67a185d189 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.38 vpr 63.50 MiB -1 -1 0.79 23456 5 0.18 -1 -1 33376 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65028 10 2 181 183 1 35 24 6 6 36 clb auto 24.1 MiB 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186374 0.00181229 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.76 vpr 66.03 MiB -1 -1 0.86 26892 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186164 0.0017947 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 2f29f949e72..153be88f8d6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.49 vpr 63.62 MiB -1 -1 0.85 23572 5 0.18 -1 -1 33320 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65152 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.25 146 398 72 298 28 63.6 MiB 0.11 0.00 2.14643 -92.7521 -2.14643 2.14643 0.05 0.000375851 0.000345018 0.00764954 0.00711987 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00935215 0.00877834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.90 vpr 66.02 MiB -1 -1 0.83 26896 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000402396 0.000353615 0.00726063 0.00647248 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00909673 0.00824277 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt index 52d01e58538..6e6ab2e273c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 2.12 vpr 58.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60124 11 11 59 70 0 48 26 4 4 16 clb auto 19.3 MiB 0.07 179 634 146 488 0 58.7 MiB 0.01 0.00 2.51353 -20.6332 -2.51353 nan 0.01 0.00020518 0.000188419 0.00473406 0.00439686 -1 -1 -1 -1 30 199 15 215576 215576 18771.3 1173.21 1.07 0.0644809 0.0550317 1016 3020 -1 198 17 257 591 8958 4396 2.73234 nan -23.1489 -2.73234 0 0 22855.5 1428.47 0.00 0.22 0.00 -1 -1 0.00 0.0209741 0.0195805 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.15 vpr 21.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 21948 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_5x6.blif common 0.60 vpr 60.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62244 11 11 59 70 0 48 26 4 4 16 clb auto 22.1 MiB 0.03 179 862 260 602 0 60.8 MiB 0.02 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000312912 0.000279273 0.00803541 0.00727675 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.11 0.0569851 0.0502764 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.01 0.00 -1 -1 0.00 0.0102047 0.00933765 + k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.06 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23944 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.3 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt index 1a1be87df70..12efb65ec8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 2.20 vpr 75.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 77140 33 32 161 193 1 65 97 34 34 1156 -1 32x32 18.7 MiB 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00189505 0.0018502 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 2.54 vpr 77.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78852 33 32 161 193 1 65 97 34 34 1156 -1 32x32 21.4 MiB 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00178122 0.0017245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt index 93476cb3715..87ace76c192 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.28 vpr 62.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63844 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 20 30 10 17 3 62.3 MiB 0.01 0.00 0.645658 -3.51726 -0.645658 0.571 0.02 7.06e-05 5.5105e-05 0.00193417 0.00186411 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00193417 0.00186411 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml multiclock.blif common 0.20 vpr 64.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66472 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.9 MiB 0.00 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 4.3045e-05 2.9263e-05 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt index 9c0fd9e92e6..8361bf1bfe6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.42 vpr 976.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999804 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.55 370 858 95 697 66 976.4 MiB 0.06 0.00 6.45248 -69.1493 -6.45248 6.45248 3.16 0.00053133 0.000484838 0.0148989 0.0138589 -1 -1 -1 -1 32 693 33 0 0 122746. 1394.84 1.72 0.145798 0.129504 11830 34246 -1 570 10 235 725 56242 26416 6.94346 6.94346 -73.9579 -6.94346 0 0 164688. 1871.45 0.06 0.06 0.09 -1 -1 0.06 0.0256172 0.0239212 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 37.07 vpr 976.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999876 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.61 369 812 82 656 74 976.4 MiB 0.07 0.00 6.45248 -69.2479 -6.45248 6.45248 3.14 0.000419744 0.000381717 0.0118947 0.0110676 -1 -1 -1 -1 32 691 29 0 0 153433. 1743.56 1.12 0.12258 0.110164 11830 34246 -1 553 12 224 697 51846 24062 6.94346 6.94346 -73.4811 -6.94346 0 0 205860. 2339.32 0.05 0.07 0.09 -1 -1 0.05 0.0274519 0.0254462 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 41.11 vpr 976.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999784 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.79 370 812 89 663 60 976.4 MiB 0.12 0.00 6.52191 -68.7563 -6.52191 6.52191 4.09 0.000672013 0.000608225 0.017378 0.0162156 -1 -1 -1 -1 22 809 21 0 0 110609. 1256.92 2.28 0.128845 0.11551 11258 24748 -1 663 14 329 1173 67735 35710 7.04515 7.04515 -76.4932 -7.04515 0 0 134428. 1527.59 0.03 0.08 0.06 -1 -1 0.03 0.0372941 0.0337267 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 42.24 vpr 976.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1000000 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.76 368 812 95 656 61 976.6 MiB 0.15 0.00 6.34478 -68.8031 -6.34478 6.34478 4.44 0.000492867 0.000449805 0.0183566 0.017188 -1 -1 -1 -1 28 753 22 0 0 134428. 1527.59 1.92 0.132649 0.118834 11590 29630 -1 624 15 260 959 55378 26467 6.64742 6.64742 -72.827 -6.64742 0 0 173354. 1969.93 0.03 0.07 0.08 -1 -1 0.03 0.0270531 0.0242418 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.75 vpr 978.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001760 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.46 364 858 131 680 47 978.3 MiB 0.06 0.00 6.37129 -69.6808 -6.37129 6.37129 1.81 0.000551403 0.000481676 0.0153225 0.013705 -1 -1 -1 -1 22 874 22 0 0 110609. 1256.92 1.54 0.247666 0.215864 11258 24748 -1 728 16 428 1746 95453 49745 6.73416 6.73416 -75.7525 -6.73416 0 0 134428. 1527.59 0.01 0.08 0.07 -1 -1 0.01 0.0332471 0.0304495 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 37.57 vpr 978.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001868 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.66 371 950 121 778 51 978.4 MiB 0.07 0.00 6.34606 -69.4373 -6.34606 6.34606 2.32 0.000744808 0.000651566 0.0166971 0.0148799 -1 -1 -1 -1 32 654 12 0 0 153433. 1743.56 0.90 0.149648 0.129506 11830 34246 -1 601 15 249 896 54680 24076 6.61838 6.61838 -74.0379 -6.61838 0 0 205860. 2339.32 0.01 0.07 0.09 -1 -1 0.01 0.0346715 0.0320467 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 34.09 vpr 978.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001652 10 10 168 178 1 68 30 11 8 88 io auto 955.4 MiB 0.44 376 582 74 468 40 978.2 MiB 0.07 0.00 6.26487 -68.7007 -6.26487 6.26487 2.74 0.000593656 0.000520243 0.0126605 0.0115382 -1 -1 -1 -1 28 858 45 0 0 134428. 1527.59 1.21 0.206409 0.180557 11590 29630 -1 614 14 305 1283 69506 33247 6.72367 6.72367 -73.5822 -6.72367 0 0 173354. 1969.93 0.01 0.08 0.06 -1 -1 0.01 0.0327372 0.0302784 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 41.01 vpr 978.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002252 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.60 352 582 88 454 40 978.8 MiB 0.05 0.00 6.37106 -69.2764 -6.37106 6.37106 3.17 0.000446168 0.000388088 0.0115458 0.0104844 -1 -1 -1 -1 22 778 22 0 0 110609. 1256.92 1.84 0.253098 0.220545 11258 24748 -1 690 15 386 1546 88347 46120 6.75259 6.75259 -75.6874 -6.75259 0 0 134428. 1527.59 0.01 0.08 0.06 -1 -1 0.01 0.0310233 0.0286671 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index c5f45b0d4e3..10a6cf257aa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 42.58 vpr 976.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999900 10 10 168 178 1 68 30 11 8 88 io auto 953.3 MiB 0.70 393 628 105 491 32 976.5 MiB 0.15 0.00 6.51193 -69.1178 -6.51193 6.51193 3.23 0.00078609 0.000724519 0.016967 0.01616 -1 -1 -1 -1 20 893 28 0 0 100248. 1139.18 2.16 0.139573 0.124569 11180 23751 -1 831 19 496 1987 121384 60113 6.91414 6.91414 -78.1319 -6.91414 0 0 150556. 1710.86 0.03 0.09 0.06 -1 -1 0.03 0.0325178 0.0296648 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 41.59 vpr 976.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999880 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.80 380 628 91 496 41 976.4 MiB 0.26 0.02 6.52338 -69.1003 -6.52338 6.52338 3.25 0.000777298 0.000711005 0.0177546 0.0168625 -1 -1 -1 -1 30 673 12 0 0 144567. 1642.81 1.66 0.128557 0.114566 11730 32605 -1 585 9 216 698 45031 21119 6.8993 6.8993 -73.7008 -6.8993 0 0 194014. 2204.70 0.05 0.06 0.09 -1 -1 0.05 0.0224124 0.0206008 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 36.65 vpr 978.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002024 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.33 0.000579422 0.00050489 0.0121495 0.01103 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.00 0.197686 0.174013 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.07 0.08 -1 -1 0.01 0.0316604 0.0292377 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 28.63 vpr 978.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001964 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.43 356 628 86 501 41 978.5 MiB 0.06 0.00 6.32784 -69.1369 -6.32784 6.32784 1.45 0.000300815 0.000260189 0.00775385 0.00704586 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 0.78 0.12183 0.106239 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.07 0.04 -1 -1 0.01 0.0278034 0.0259211 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt index 4d6fe9605d7..bee9bf5e15f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.34 vpr 74.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76080 8 63 1072 1135 0 619 135 12 12 144 clb auto 34.4 MiB 2.45 6183 12245 2318 9041 886 74.3 MiB 0.46 0.01 4.99539 -218.829 -4.99539 nan 0.40 0.00339822 0.00308909 0.174455 0.155138 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.182343 0.1625 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 4.15 vpr 74.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76000 8 63 1072 1135 0 619 135 12 12 144 clb auto 34.1 MiB 2.35 6325 11326 2120 8412 794 74.2 MiB 0.45 0.01 4.96391 -216.681 -4.96391 nan 0.40 0.00300248 0.00261681 0.177754 0.159055 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.182191 0.163076 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 9.98 vpr 77.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 79808 8 63 1072 1135 0 619 135 27 27 729 -1 auto 34.4 MiB 2.36 6780 22625 6869 14375 1381 77.7 MiB 0.66 0.01 5.57619 -254.596 -5.57619 nan 3.15 0.00374551 0.00316871 0.28525 0.251728 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.292957 0.259025 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 10.88 vpr 77.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 79852 8 63 1072 1135 0 619 135 27 27 729 -1 auto 34.5 MiB 2.52 6916 70425 20372 45422 4631 77.9 MiB 1.04 0.02 5.61138 -254.037 -5.61138 nan 3.20 0.00355764 0.00324002 0.259461 0.229263 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.264477 0.233757 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_circuit 3.66 vpr 76.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78656 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.7 MiB 2.32 6246 12245 2336 8854 1055 76.8 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.22 0.00367856 0.00299064 0.169598 0.144286 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.174334 0.148491 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.50 vpr 76.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78400 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.21 6248 12409 2316 9051 1042 76.6 MiB 0.36 0.01 5.00015 -217.921 -5.00015 nan 0.26 0.00350625 0.00296092 0.150187 0.130251 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.154752 0.13448 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 4.86 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78576 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.5 MiB 1.80 6557 16051 3559 11939 553 76.7 MiB 0.46 0.01 5.39652 -231.823 -5.39652 nan 1.19 0.00333577 0.00278218 0.186781 0.161087 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.19137 0.165152 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.27 vpr 76.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78592 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.48 6642 53385 10847 39555 2983 76.8 MiB 0.94 0.01 5.30857 -236.309 -5.30857 nan 1.66 0.00199214 0.00171649 0.207463 0.177518 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.212761 0.182102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt index 8ddf2cd268a..344063856f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 4.32 vpr 63.63 MiB -1 -1 0.91 23516 5 0.18 -1 -1 33320 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65160 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.14 146 398 72 298 28 63.6 MiB 0.15 0.00 2.14643 -92.7521 -2.14643 2.14643 0.05 0.000721287 0.000665617 0.0100883 0.00940276 -1 -1 -1 -1 14 201 20 646728 646728 22986.6 638.518 0.96 0.149763 0.124804 1728 4488 -1 171 15 208 442 9451 2845 2.12882 2.12882 -98.7664 -2.12882 0 0 30529.5 848.041 0.01 0.05 0.01 -1 -1 0.01 0.0189304 0.0169003 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.31 vpr 66.14 MiB -1 -1 0.81 26892 5 0.20 -1 -1 36924 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.1 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000410176 0.000357432 0.00947888 0.00721552 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.10 0.0626682 0.052856 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0168161 0.0151469 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt index 9a08c839075..a4fadd34b2c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.68 vpr 60.19 MiB -1 -1 -1 -1 0 0.02 -1 -1 30040 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61636 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.4 MiB 0.03 0 3 0 0 3 60.2 MiB 0.01 0.00 nan 0 0 nan 0.00 1.2311e-05 7.387e-06 0.000105834 7.5869e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00147816 0.00140463 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.71 vpr 60.08 MiB -1 -1 -1 -1 0 0.02 -1 -1 30088 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61524 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.4 MiB 0.04 0 3 0 0 3 60.1 MiB 0.03 0.00 nan 0 0 nan 0.00 3.6044e-05 2.4593e-05 0.000145604 0.000105582 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.02 0.00162472 0.00153314 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.73 vpr 60.18 MiB -1 -1 -1 -1 0 0.02 -1 -1 30176 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61624 6 1 1 8 0 1 8 3 3 9 -1 auto 21.4 MiB 0.04 0 21 0 11 10 60.2 MiB 0.04 0.00 nan 0 0 nan 0.00 3.8303e-05 2.7095e-05 0.000158699 0.000117087 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.02 0.00160603 0.0015131 -1 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2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61912 2 1 3 4 0 3 4 3 3 9 -1 auto 21.8 MiB 0.03 9 9 5 0 4 60.5 MiB 0.03 0.00 0.443777 -0.443777 -0.443777 nan 0.00 2.6924e-05 2.1285e-05 0.000155957 0.000124557 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.04 0.00180691 0.00163332 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.92 vpr 60.15 MiB -1 -1 -1 -1 2 0.06 -1 -1 31604 -1 -1 1 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61592 5 1 7 8 0 7 7 3 3 9 -1 auto 21.4 MiB 0.05 20 18 12 0 6 60.1 MiB 0.05 0.00 0.70303 -0.70303 -0.70303 nan 0.00 4.3879e-05 3.664e-05 0.000222358 0.000185667 -1 -1 -1 -1 -1 8 6 3900 3900 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3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64220 3 2 5 7 0 5 6 3 3 9 -1 auto 24.3 MiB 0.00 15 15 11 0 4 62.7 MiB 0.00 0.00 0.443777 -0.887553 -0.443777 nan 0.00 2.4709e-05 1.8183e-05 0.000141351 0.000109437 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.00207041 0.0018628 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.46 vpr 62.58 MiB -1 -1 -1 -1 2 0.06 -1 -1 35476 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64084 5 3 9 12 0 9 9 3 3 9 -1 auto 24.2 MiB 0.00 26 27 24 0 3 62.6 MiB 0.00 0.00 0.70303 -1.84984 -0.70303 nan 0.00 3.6085e-05 2.9105e-05 0.000215176 0.00018047 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.0027146 0.00242632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.58 vpr 62.59 MiB -1 -1 -1 -1 3 0.05 -1 -1 35528 -1 -1 1 7 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 7 4 13 17 0 13 12 3 3 9 -1 auto 24.2 MiB 0.01 37 38 34 0 4 62.6 MiB 0.00 0.00 0.962283 -3.07137 -0.962283 nan 0.00 5.1242e-05 4.3365e-05 0.000310909 0.00026784 -1 -1 -1 -1 -1 42 19 3900 3900 7855.82 872.868 0.01 0.00339296 0.00299342 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.56 vpr 62.59 MiB -1 -1 -1 -1 4 0.06 -1 -1 35528 -1 -1 1 9 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 9 5 17 22 0 17 15 3 3 9 -1 auto 24.2 MiB 0.01 48 51 43 0 8 62.6 MiB 0.00 0.00 1.22154 -4.55216 -1.22154 nan 0.00 5.8362e-05 4.9699e-05 0.000357643 0.000314843 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.01 0.00442103 0.00396409 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.68 vpr 62.61 MiB -1 -1 -1 -1 4 0.06 -1 -1 35388 -1 -1 2 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64108 11 6 24 30 0 24 19 4 4 16 clb auto 24.2 MiB 0.02 81 219 59 138 22 62.6 MiB 0.00 0.00 1.3375 -6.59285 -1.3375 nan 0.00 7.7083e-05 6.6497e-05 0.00098279 0.000856632 -1 -1 -1 -1 -1 132 15 7800 7800 17482.0 1092.63 0.01 0.00598903 0.00545622 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index d710f9093cf..def1a137d22 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 7.34 vpr 66.08 MiB -1 -1 0.43 18936 3 0.11 -1 -1 33284 -1 53192 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67664 99 130 344 474 1 227 298 12 12 144 clb auto 26.4 MiB 0.38 717 72933 22876 34411 15646 66.1 MiB 0.54 0.01 1.84343 -118.171 -1.84343 1.84343 0.36 0.0010848 0.00101841 0.0913793 0.0860775 -1 -1 -1 -1 38 1552 14 5.66058e+06 4.21279e+06 319130. 2216.18 2.91 0.450493 0.414934 12522 62564 -1 1267 9 391 595 24204 7116 1.90841 1.90841 -134.254 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.13 0.07 0.08 -1 -1 0.13 0.0328333 0.030834 0.0117 0.2242 0.06563 0.7102 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 17.64 vpr 68.80 MiB -1 -1 0.70 23848 15 0.45 -1 -1 34524 -1 54788 39 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70452 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 29.4 MiB 0.77 5637 94418 33826 53640 6952 68.8 MiB 0.97 0.01 21.0535 -1600.99 -21.0535 21.0535 0.77 0.00355871 0.00332925 0.362999 0.339534 -1 -1 -1 -1 50 13462 45 1.21132e+07 4.08187e+06 780512. 3048.87 8.60 1.322 1.21904 25484 153448 -1 9971 18 3407 6810 971785 294758 22.3056 22.3056 -1729.57 -22.3056 0 0 1.00276e+06 3917.05 0.33 0.44 0.17 -1 -1 0.33 0.14631 0.136022 0.007875 0.3522 0.01635 0.6315 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.05 vpr 68.39 MiB -1 -1 0.40 21908 3 0.11 -1 -1 37048 -1 54888 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70028 99 130 344 474 1 227 298 12 12 144 clb auto 29.0 MiB 0.23 673 63978 19550 30341 14087 68.4 MiB 0.26 0.00 1.86472 -118.834 -1.86472 1.86472 0.28 0.000886976 0.000801272 0.0813306 0.0745016 -1 -1 -1 -1 38 1393 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.68 0.238994 0.21577 12522 62564 -1 1106 10 397 647 21454 6807 1.90702 1.90702 -131.595 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.03 0.05 0.11 -1 -1 0.03 0.0347348 0.0326652 0.01152 0.2117 0.0667 0.7216 + k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.51 vpr 71.63 MiB -1 -1 0.57 27156 15 0.44 -1 -1 38000 -1 56764 39 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73348 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 32.3 MiB 0.47 5553 86322 27524 51152 7646 71.6 MiB 0.85 0.01 20.9417 -1607.93 -20.9417 20.9417 0.48 0.003704 0.00340296 0.38455 0.354826 -1 -1 -1 -1 50 10993 26 1.21132e+07 4.08187e+06 780512. 3048.87 3.85 1.2672 1.17071 25484 153448 -1 9617 17 3054 6060 825747 253645 22.1678 22.1678 -1734.75 -22.1678 0 0 1.00276e+06 3917.05 0.06 0.43 0.25 -1 -1 0.06 0.181388 0.170418 0.007894 0.3513 0.0164 0.6323 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index 0b0e8c245c9..82620e51799 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.71 vpr 63.64 MiB -1 -1 0.89 23420 5 0.17 -1 -1 33392 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65172 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.10 146 398 72 298 28 63.6 MiB 0.06 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000418181 0.00038256 0.0070167 0.00650899 -1 -1 -1 -1 130 4.06250 54 1.68750 215 509 15144 2919 646728 646728 138825. 3856.24 24 3164 19284 -1 2.05191 2.05191 -93.8814 -2.05191 0 0 0.02 -1 -1 63.6 MiB 0.24 0.0355426 0.0317424 63.6 MiB -1 0.03 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.97 vpr 66.65 MiB -1 -1 0.84 23052 4 0.17 -1 -1 33056 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68248 11 2 303 283 2 78 28 7 7 49 clb auto 27.1 MiB 0.31 264 1036 209 767 60 66.6 MiB 0.17 0.00 2.03811 -163.536 -2.03811 1.90043 0.00 0.0010174 0.000936861 0.0267115 0.0245008 -1 -1 -1 -1 252 3.50000 103 1.43056 122 199 4265 1218 1.07788e+06 808410 219490. 4479.39 12 5100 32136 -1 2.11264 1.93889 -160.659 -2.11264 0 0 0.04 -1 -1 66.6 MiB 0.15 0.0627365 0.0575288 66.6 MiB -1 0.04 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.71 vpr 65.87 MiB -1 -1 0.78 26896 5 0.18 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67448 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00039706 0.000346093 0.00713489 0.00637234 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.03 -1 -1 65.9 MiB 0.02 0.0245431 0.0219785 65.9 MiB -1 0.00 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.90 vpr 68.91 MiB -1 -1 0.73 26796 4 0.18 -1 -1 36100 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70560 11 2 303 283 2 78 28 7 7 49 clb auto 29.2 MiB 0.18 285 784 175 539 70 68.9 MiB 0.03 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000657098 0.000563918 0.0210266 0.0187872 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 68.9 MiB 0.03 0.0456598 0.0418503 68.9 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index 447a074d109..b3939ae8bad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 46.36 vpr 82.59 MiB -1 -1 8.22 52832 5 2.16 -1 -1 39584 -1 -1 153 193 5 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 84572 193 205 2718 2652 1 1312 556 20 20 400 memory auto 41.4 MiB 2.16 10365 229056 86247 118235 24574 82.3 MiB 2.34 0.03 4.93042 -2712.69 -4.93042 4.93042 1.49 0.00671843 0.00610927 0.880709 0.785571 -1 -1 -1 -1 82 19408 37 2.07112e+07 1.09858e+07 2.14661e+06 5366.52 23.21 5.08072 4.56727 53670 456392 -1 17785 16 4760 12593 961685 215487 5.25964 5.25964 -2873.25 -5.25964 -10.2812 -0.29768 2.68822e+06 6720.56 0.74 0.58 0.45 -1 -1 0.74 0.348182 0.32009 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 40.08 vpr 84.36 MiB -1 -1 7.36 54308 5 2.17 -1 -1 42700 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86380 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 2.10 10543 233626 82676 126206 24744 84.4 MiB 2.58 0.04 4.85425 -2733.64 -4.85425 4.85425 0.83 0.0094896 0.008538 0.955143 0.814553 -1 -1 -1 -1 76 20844 34 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 19.63 4.86995 4.26704 52074 423490 -1 18742 17 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.70 0.57 -1 -1 0.11 0.429237 0.387696 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt index 3029284bb73..b2a77a6f0e1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 2.47 vpr 69.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70748 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.54 4989 14482 2605 10909 968 69.1 MiB 0.33 0.01 4.15324 -188.164 -4.15324 nan 0.00 0.00355218 0.00311968 0.123812 0.109233 -1 -1 -1 -1 6805 14.9560 1830 4.02198 3625 14263 570126 87469 9.20055e+06 4.79657e+06 867065. 4423.80 19 18088 133656 -1 4.17843 nan -185.467 -4.17843 0 0 0.15 -1 -1 69.1 MiB 0.41 0.278836 0.250118 69.1 MiB -1 0.28 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.71 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70728 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.58 4989 14482 2605 10909 968 69.1 MiB 0.30 0.01 4.15324 -188.164 -4.15324 nan 0.00 0.00262291 0.00213676 0.106954 0.095917 -1 -1 -1 -1 6877 15.1143 1848 4.06154 3712 14523 564432 88116 9.20055e+06 4.79657e+06 867065. 4423.80 19 18088 133656 -1 4.14924 nan -185.7 -4.14924 0 0 0.14 -1 -1 69.1 MiB 0.44 0.258375 0.232966 69.1 MiB -1 0.34 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.71 vpr 71.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73312 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.45 4992 14048 2664 10357 1027 71.6 MiB 0.29 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00333844 0.00278407 0.128199 0.109732 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.21 -1 -1 71.6 MiB 0.30 0.276888 0.244984 71.6 MiB -1 0.05 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.81 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.47 4992 14048 2664 10357 1027 71.5 MiB 0.31 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00291779 0.00252096 0.133598 0.1169 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.20 -1 -1 71.5 MiB 0.31 0.289515 0.258703 71.5 MiB -1 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index 15eaa3bf41e..f0bed076f05 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.55 vpr 69.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70784 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.60 4981 18388 4106 12671 1611 69.1 MiB 0.49 0.01 3.67827 -162.703 -3.67827 nan 0.04 0.00317376 0.00278185 0.166614 0.146475 -1 -1 -1 -1 6929 15.2286 1856 4.07912 4031 16057 1191599 209386 9.20055e+06 4.79657e+06 701736. 3580.29 21 16332 105598 -1 4.26894 nan -186.127 -4.26894 0 0 0.09 -1 -1 69.1 MiB 0.54 0.351918 0.315357 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.62 vpr 69.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70684 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.61 4947 14048 2843 10376 829 69.0 MiB 0.36 0.01 4.36787 -194.851 -4.36787 nan 0.00 0.00347735 0.00296792 0.131799 0.115232 -1 -1 -1 -1 7013 15.4132 1882 4.13626 4368 18266 702728 114564 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.35011 nan -200.403 -4.35011 0 0 0.11 -1 -1 69.0 MiB 0.50 0.320884 0.285698 69.0 MiB -1 0.23 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.96 vpr 69.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70868 8 63 748 811 0 455 160 14 14 196 clb auto 29.7 MiB 0.63 4953 17954 4036 12536 1382 69.2 MiB 0.51 0.01 3.75278 -163.938 -3.75278 nan 0.07 0.00355287 0.00313746 0.160864 0.141994 -1 -1 -1 -1 7096 15.5956 1936 4.25495 3839 15635 1250449 222869 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.31984 nan -190.626 -4.31984 0 0 0.09 -1 -1 69.2 MiB 0.68 0.350893 0.31266 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.84 vpr 69.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70800 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.60 4953 17954 4036 12536 1382 69.1 MiB 0.45 0.01 3.75278 -163.938 -3.75278 nan 0.07 0.00233095 0.00207468 0.141454 0.125813 -1 -1 -1 -1 7096 15.5956 1936 4.25495 3839 15635 1250449 222869 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.31984 nan -190.626 -4.31984 0 0 0.12 -1 -1 69.1 MiB 0.66 0.321273 0.286755 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.89 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73344 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.50 4993 17086 3593 12286 1207 71.6 MiB 0.32 0.01 3.65588 -160.421 -3.65588 nan 0.04 0.00302942 0.00252731 0.141328 0.121812 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.15 -1 -1 71.6 MiB 0.43 0.306494 0.271472 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.75 vpr 71.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73176 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.38 4933 15350 2970 11325 1055 71.5 MiB 0.31 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00317678 0.00277359 0.137596 0.118868 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.5 MiB 0.37 0.319312 0.282053 71.5 MiB -1 0.04 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.41 vpr 71.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73128 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.28 0.01 3.77945 -168.167 -3.77945 nan 0.06 0.00517556 0.0043803 0.123856 0.107999 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.14 -1 -1 71.4 MiB 0.56 0.3503 0.312891 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.58 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.7 MiB 0.45 5048 17520 3917 12196 1407 71.5 MiB 0.35 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00283082 0.00243406 0.152931 0.13159 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.10 -1 -1 71.5 MiB 0.60 0.372321 0.328664 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt index 85f2b790a31..2e384423539 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 2.44 vpr 69.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70664 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.60 5081 14916 3009 10977 930 69.0 MiB 0.47 0.01 4.4281 -198.501 -4.4281 nan 0.00 0.00389538 0.00357453 0.140004 0.12435 -1 -1 -1 -1 6741 14.8154 1803 3.96264 3315 13570 497205 81432 9.20055e+06 4.79657e+06 787177. 4016.21 19 17112 118924 -1 4.40099 nan -202.066 -4.40099 0 0 0.12 -1 -1 69.0 MiB 0.33 0.283749 0.254966 69.0 MiB -1 0.26 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.38 vpr 69.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70672 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.61 5081 14916 3009 10977 930 69.0 MiB 0.41 0.01 4.4281 -198.501 -4.4281 nan 0.00 0.00305314 0.00262997 0.138499 0.118452 -1 -1 -1 -1 6767 14.8725 1813 3.98462 3295 13377 489418 80231 9.20055e+06 4.79657e+06 787177. 4016.21 18 17112 118924 -1 4.40099 nan -201.997 -4.40099 0 0 0.13 -1 -1 69.0 MiB 0.39 0.297323 0.263941 69.0 MiB -1 0.24 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.81 vpr 71.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72996 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.46 5066 14916 2828 10927 1161 71.3 MiB 0.27 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00329282 0.00274638 0.115858 0.0987687 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.40 0.297064 0.262289 71.3 MiB -1 0.03 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.90 vpr 71.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72932 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.47 5066 14916 2828 10927 1161 71.2 MiB 0.34 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00295504 0.00249967 0.137157 0.115922 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.16 -1 -1 71.2 MiB 0.41 0.334676 0.294068 71.2 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt index cee3d6a8fdb..dda3cef9fb9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.82 vpr 64.82 MiB -1 -1 0.15 17544 1 0.06 -1 -1 32228 -1 -1 2 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66372 6 1 16 17 2 10 9 17 17 289 -1 auto 26.1 MiB 0.03 30 162 45 109 8 64.8 MiB 0.09 0.00 1.4327 -4.13089 -1.4327 0.805 0.87 0.000186474 0.000145053 0.00220998 0.00182998 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.70 0.00469902 0.00412949 24098 82050 -1 103 2 14 14 8039 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.22 0.33 0.08 -1 -1 0.22 0.00213527 0.00203038 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.09 vpr 64.87 MiB -1 -1 0.11 17384 1 0.02 -1 -1 29996 -1 -1 1 3 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66428 3 1 5 6 1 4 5 13 13 169 -1 auto 26.1 MiB 0.03 35 12 3 8 1 64.9 MiB 0.01 0.00 1.12186 -1.54831 -1.12186 1.12186 0.48 2.8473e-05 2.3109e-05 0.000199018 0.000164788 -1 -1 -1 -1 20 62 1 6.63067e+06 53894 227243. 1344.63 0.37 0.00185586 0.00172162 13251 44387 -1 55 1 4 4 2056 1112 1.77078 1.77078 -1.77078 -1.77078 -0.365681 -0.365681 294987. 1745.49 0.10 0.18 0.05 -1 -1 0.10 0.00158341 0.00153323 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.83 vpr 64.72 MiB -1 -1 0.13 17592 1 0.07 -1 -1 32164 -1 -1 2 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66272 6 1 16 17 2 10 9 17 17 289 -1 auto 25.9 MiB 0.02 30 162 45 109 8 64.7 MiB 0.09 0.00 1.43377 -4.13192 -1.43377 0.805 0.93 6.1161e-05 4.7651e-05 0.00173334 0.0014267 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.63 0.00414802 0.00366881 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.21 0.32 0.08 -1 -1 0.21 0.00216645 0.00203322 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.02 vpr 64.86 MiB -1 -1 0.13 17428 1 0.02 -1 -1 30016 -1 -1 1 3 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66416 3 1 5 6 1 4 5 13 13 169 -1 auto 26.2 MiB 0.03 35 12 3 8 1 64.9 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.48 2.3262e-05 1.8246e-05 0.000166554 0.000134906 -1 -1 -1 -1 20 58 1 6.63067e+06 53894 235789. 1395.20 0.40 0.00173302 0.00160946 13251 46155 -1 59 1 4 4 2248 1144 1.92085 1.92085 -1.92085 -1.92085 -0.365681 -0.365681 303533. 1796.05 0.09 0.18 0.05 -1 -1 0.09 0.00168955 0.00163685 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 4.88 vpr 64.75 MiB -1 -1 0.14 17432 1 0.06 -1 -1 32172 -1 -1 2 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66304 6 1 16 17 2 10 9 17 17 289 -1 auto 26.0 MiB 0.03 30 162 45 109 8 64.8 MiB 0.09 0.00 1.4327 -4.13089 -1.4327 0.805 0.92 0.000151459 0.00012099 0.0026464 0.00223102 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.67 0.00496297 0.0043779 24098 82150 -1 581 2 13 13 6255 3245 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.22 0.36 0.10 -1 -1 0.22 0.00223048 0.00210515 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 3.10 vpr 64.75 MiB -1 -1 0.15 17324 1 0.02 -1 -1 29932 -1 -1 1 3 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66308 3 1 5 6 1 4 5 13 13 169 -1 auto 26.0 MiB 0.03 35 12 3 8 1 64.8 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.46 2.059e-05 1.5632e-05 0.000148678 0.000118416 -1 -1 -1 -1 20 193 1 6.63067e+06 53894 225153. 1332.26 0.49 0.00184377 0.00171779 13251 44463 -1 186 1 4 4 914 327 2.39001 2.39001 -2.39001 -2.39001 -0.984912 -0.984912 292904. 1733.16 0.11 0.20 0.07 -1 -1 0.11 0.00185429 0.00178578 0 4 + timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.94 vpr 67.28 MiB -1 -1 0.14 21160 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68892 6 1 16 17 2 10 9 17 17 289 -1 auto 28.8 MiB 0.03 30 162 45 109 8 67.3 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.60 4.7388e-05 3.614e-05 0.00109694 0.000865862 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.37 0.00363015 0.00323679 24098 82050 -1 103 2 14 14 8045 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.04 0.16 0.10 -1 -1 0.04 0.00205247 0.00194107 1 9 + timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.71 vpr 67.09 MiB -1 -1 0.11 20776 1 0.02 -1 -1 33508 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.29 2.6273e-05 2.0281e-05 0.000147698 0.000116195 -1 -1 -1 -1 20 62 1 6.63067e+06 53894 227243. 1344.63 0.21 0.00195838 0.00183532 13251 44387 -1 55 1 4 4 2060 1116 1.77078 1.77078 -1.77078 -1.77078 -0.365681 -0.365681 294987. 1745.49 0.02 0.09 0.06 -1 -1 0.02 0.00158307 0.00153637 0 4 + timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.80 vpr 67.12 MiB -1 -1 0.13 21160 1 0.05 -1 -1 35572 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68728 6 1 16 17 2 10 9 17 17 289 -1 auto 28.7 MiB 0.01 30 162 45 109 8 67.1 MiB 0.00 0.00 1.43377 -4.13192 -1.43377 0.805 0.60 4.8373e-05 3.7154e-05 0.00108209 0.000859607 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.36 0.00311589 0.00272737 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.04 0.17 0.12 -1 -1 0.04 0.00220953 0.00209751 1 9 + timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.66 vpr 67.09 MiB -1 -1 0.12 20904 1 0.02 -1 -1 33532 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.23 2.2312e-05 1.624e-05 0.000140559 0.000108632 -1 -1 -1 -1 20 58 1 6.63067e+06 53894 235789. 1395.20 0.22 0.00172037 0.00159801 13251 46155 -1 59 1 4 4 2248 1144 1.92085 1.92085 -1.92085 -1.92085 -0.365681 -0.365681 303533. 1796.05 0.02 0.10 0.07 -1 -1 0.02 0.00161749 0.00156481 0 4 + timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.79 vpr 67.18 MiB -1 -1 0.14 20780 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68788 6 1 16 17 2 10 9 17 17 289 -1 auto 28.9 MiB 0.02 30 162 45 109 8 67.2 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.52 4.3023e-05 3.3348e-05 0.0010817 0.000870707 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.27 0.00353152 0.00316566 24098 82150 -1 581 2 13 13 6290 3262 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.04 0.17 0.11 -1 -1 0.04 0.00234323 0.00223031 1 9 + timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.63 vpr 67.17 MiB -1 -1 0.08 21164 1 0.02 -1 -1 33664 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68780 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.2 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.27 1.6733e-05 1.1353e-05 0.00024751 0.000102039 -1 -1 -1 -1 20 193 1 6.63067e+06 53894 225153. 1332.26 0.23 0.00204227 0.00181801 13251 44463 -1 186 1 4 4 914 327 2.39001 2.39001 -2.39001 -2.39001 -0.984912 -0.984912 292904. 1733.16 0.02 0.07 0.05 -1 -1 0.02 0.00162703 0.00157897 0 4 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index b0a1541d4c4..5c6245f2fa3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 1.93 vpr 57.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58880 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 18.4 MiB 0.26 70 15 2 12 1 57.5 MiB 0.04 0.00 0.645672 -5.8162 -0.645672 0.645672 0.02 0.000258504 0.000238009 0.00107156 0.000998425 -1 -1 -1 -1 25 294 14 133321 74067 -1 -1 0.87 0.0364979 0.0304333 1252 5405 -1 287 14 116 116 21465 12891 1.98076 1.98076 -20.8107 -1.98076 0 0 -1 -1 0.01 0.05 0.01 -1 -1 0.01 0.00555954 0.00497644 + slicem.xml carry_chain.blif common 0.74 vpr 59.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61260 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 21.1 MiB 0.24 70 15 4 10 1 59.8 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000194851 0.000170942 0.00110293 0.00100939 -1 -1 -1 -1 27 263 12 133321 74067 -1 -1 0.15 0.0230545 0.019405 1284 5874 -1 260 8 79 79 17257 10064 1.64234 1.64234 -16.7917 -1.64234 0 0 -1 -1 0.00 0.01 0.01 -1 -1 0.00 0.0047943 0.00439499 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index ee663247acc..bcdd78ccdb6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.79 vpr 56.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58108 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 17.9 MiB 0.01 31 35 6 27 2 56.7 MiB 0.00 0.00 0.212927 -2.22016 -0.212927 0.212927 0.00 3.8012e-05 2.9599e-05 0.000219444 0.000180809 -1 -1 -1 -1 4 28 4 59253.6 44440.2 -1 -1 0.12 0.00506904 0.00414914 184 632 -1 29 2 13 18 795 367 0.309802 0.309802 -2.85512 -0.309802 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.00167546 0.00160294 + arch.xml ndff.blif common 0.33 vpr 58.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60252 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.2 MiB 0.00 31 59 13 43 3 58.8 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.7056e-05 2.9732e-05 0.000307367 0.000251846 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00402393 0.00331535 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00212051 0.00200433 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index 71d0a37b2c3..07d413f9696 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.29 vpr 66.64 MiB -1 -1 0.68 22960 4 0.18 -1 -1 33204 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68244 11 2 303 283 2 81 28 7 7 49 clb auto 27.0 MiB 0.32 332 112 32 50 30 66.6 MiB 0.02 0.00 4.11769 0 0 3.94108 0.00 0.000730069 0.000683064 0.00633623 0.00608273 -1 -1 -1 -1 376 5.01333 137 1.82667 100 150 2999 863 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.1682 4.01568 0 0 -197.816 -1.707 0.04 -1 -1 66.6 MiB 0.02 0.0267422 0.0255335 66.6 MiB -1 0.04 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.89 vpr 69.17 MiB -1 -1 0.74 26544 4 0.19 -1 -1 36136 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.19 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.000817884 0.000697618 0.00655739 0.00606976 -1 -1 -1 -1 398 5.30667 131 1.74667 104 164 3400 907 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.01 0.0209255 0.0197757 69.2 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/config.txt index 3aafacaeaa9..440149973b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/config.txt @@ -24,7 +24,7 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common = -starting_stage vpr --seed 1 +script_params_common = -starting_stage vpr --seed 6 script_params_list_add = -sdc_file sdc/samples/A.sdc script_params_list_add = -sdc_file sdc/samples/B.sdc script_params_list_add = -sdc_file sdc/samples/C.sdc diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index b4860612047..4625b2401ff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.62 vpr 62.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64392 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 22 30 9 14 7 62.9 MiB 0.01 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.5189e-05 2.7933e-05 0.00027775 0.00023103 -1 -1 -1 -1 8 18 2 107788 107788 4794.78 299.674 0.02 0.00211257 0.00195587 564 862 -1 18 4 10 10 199 87 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.01 0.05 0.00 -1 -1 0.01 0.00199426 0.00185344 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.74 vpr 62.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64480 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 23 30 6 15 9 63.0 MiB 0.00 0.00 0.571 0 0 0.571 0.01 2.8611e-05 2.2607e-05 0.000202208 0.00017077 -1 -1 -1 -1 8 26 3 107788 107788 4794.78 299.674 0.01 0.0028111 0.00267833 564 862 -1 25 5 13 13 435 272 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.05 0.01 -1 -1 0.00 0.00202607 0.00188727 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.80 vpr 63.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64684 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.05 20 30 10 18 2 63.2 MiB 0.01 0.00 0.645658 -2.18842 -0.645658 0.571 0.02 4.2927e-05 3.0224e-05 0.000271182 0.000205133 -1 -1 -1 -1 8 17 3 107788 107788 4794.78 299.674 0.01 0.00218974 0.00197452 564 862 -1 14 5 15 15 285 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.02 0.00 -1 -1 0.00 0.00202523 0.00186469 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.73 vpr 62.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64348 5 3 11 14 2 9 10 4 4 16 clb auto 24.1 MiB 0.04 20 30 12 17 1 62.8 MiB 0.05 0.00 1.64534 -5.31677 -1.64534 0.571 0.02 9.4962e-05 7.3986e-05 0.000396852 0.000314184 -1 -1 -1 -1 8 19 8 107788 107788 4794.78 299.674 0.06 0.00289715 0.00253727 564 862 -1 15 2 8 8 156 74 1.57153 0.571 -4.92067 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00169004 0.00159575 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 1.04 vpr 62.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64408 5 3 11 14 2 9 10 4 4 16 clb auto 24.1 MiB 0.04 20 30 8 18 4 62.9 MiB 0.05 0.00 1.44871 -2.90839 -1.44871 0.571 0.02 7.5837e-05 6.5211e-05 0.000364341 0.000304084 -1 -1 -1 -1 8 33 10 107788 107788 4794.78 299.674 0.16 0.00341365 0.00298684 564 862 -1 19 2 11 11 275 141 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.03 0.00 -1 -1 0.00 0.00194921 0.0018382 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.93 vpr 62.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64424 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.02 20 110 34 46 30 62.9 MiB 0.08 0.00 0.145339 0 0 0.571 0.04 5.4987e-05 4.5804e-05 0.00111315 0.000934972 -1 -1 -1 -1 8 25 4 107788 107788 4794.78 299.674 0.02 0.00324582 0.00292657 564 862 -1 36 5 15 15 690 511 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.05 0.00 -1 -1 0.00 0.0020967 0.00194205 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.45 vpr 65.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 21 4 65.2 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.03 3.7635e-05 2.9892e-05 0.000225074 0.00018278 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.02 0.00833787 0.0081741 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00218203 0.00181006 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.44 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66812 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.2 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1854e-05 2.4534e-05 0.000226572 0.000187065 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.03 0.00709054 0.0068829 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00198245 0.00170015 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.39 vpr 65.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66832 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 22 3 65.3 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.5201e-05 2.6601e-05 0.00022707 0.000179701 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00304545 0.00286146 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00175316 0.00162725 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.41 vpr 65.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.4 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.0901e-05 3.1228e-05 0.000248936 0.000196898 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00216389 0.0019624 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00684314 0.00669963 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.43 vpr 65.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66876 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.3 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 3.9504e-05 2.6238e-05 0.000255838 0.000203867 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00256208 0.00226692 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00410374 0.00385942 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.30 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66632 5 3 11 14 2 9 10 4 4 16 clb auto 26.7 MiB 0.00 21 30 5 23 2 65.1 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 2.4424e-05 1.8925e-05 0.00016567 0.000135551 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00149783 0.00138533 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00190216 0.00178073 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index 98fbf8c8bd7..3373ba9d87f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 3.08 vpr 63.73 MiB -1 -1 0.13 17836 1 0.04 -1 -1 30188 -1 -1 3 9 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65260 9 8 75 70 1 34 20 5 5 25 clb auto 24.3 MiB 0.77 86 452 135 313 4 63.7 MiB 0.06 0.00 2.64007 -28.8002 -2.64007 2.64007 0.04 0.000176675 0.000162569 0.00460188 0.00429403 -1 -1 -1 -1 26 211 21 151211 75605.7 37105.9 1484.24 0.81 0.0541272 0.0457299 1908 5841 -1 127 12 86 111 2724 1535 2.42625 2.42625 -30.8606 -2.42625 0 0 45067.1 1802.68 0.01 0.05 0.01 -1 -1 0.01 0.00806965 0.00737112 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.46 vpr 63.92 MiB -1 -1 0.11 17900 1 0.03 -1 -1 30160 -1 -1 2 11 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65452 11 10 108 97 1 49 23 4 4 16 clb auto 24.7 MiB 2.73 138 87 33 42 12 63.9 MiB 0.01 0.00 3.45122 -43.3524 -3.45122 3.45122 0.01 0.000201429 0.000183002 0.00257604 0.00248464 -1 -1 -1 -1 34 217 45 50403.8 50403.8 21558.4 1347.40 0.20 0.0492626 0.0420827 1020 3049 -1 176 15 182 199 5640 3466 3.92522 3.92522 -51.7346 -3.92522 0 0 26343.3 1646.46 0.01 0.15 0.00 -1 -1 0.01 0.0136853 0.0123259 15 27 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 8.63 vpr 64.31 MiB -1 -1 0.14 17828 1 0.03 -1 -1 30240 -1 -1 7 13 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65856 13 12 149 129 1 68 32 6 6 36 clb auto 24.9 MiB 5.01 198 932 296 626 10 64.3 MiB 0.07 0.00 3.49758 -52.5769 -3.49758 3.49758 0.05 0.000575762 0.000545987 0.00855835 0.00805083 -1 -1 -1 -1 40 371 22 403230 176413 88484.8 2457.91 1.86 0.1398 0.120669 3734 16003 -1 302 13 290 358 12780 5849 3.44595 3.44595 -57.0613 -3.44595 0 0 110337. 3064.92 0.03 0.04 0.02 -1 -1 0.03 0.0197264 0.0176 25 38 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 6.05 vpr 64.62 MiB -1 -1 0.14 18180 1 0.03 -1 -1 30148 -1 -1 7 15 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66176 15 14 196 165 1 92 36 6 6 36 clb auto 24.8 MiB 2.57 301 980 184 766 30 64.6 MiB 0.04 0.00 3.62628 -64.321 -3.62628 3.62628 0.05 0.000340747 0.000313302 0.00984916 0.00930715 -1 -1 -1 -1 52 612 36 403230 176413 110337. 3064.92 1.44 0.161491 0.139542 4014 20275 -1 519 17 441 623 24147 10156 4.0567 4.0567 -75.6699 -4.0567 0 0 143382. 3982.83 0.04 0.21 0.02 -1 -1 0.04 0.022191 0.0203236 37 51 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 9.18 vpr 64.91 MiB -1 -1 0.13 18156 1 0.03 -1 -1 30520 -1 -1 5 17 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66468 17 16 251 206 1 119 38 5 5 25 clb auto 25.1 MiB 6.50 399 2117 534 1560 23 64.9 MiB 0.09 0.00 4.01364 -77.6621 -4.01364 4.01364 0.03 0.000417359 0.000385331 0.0217452 0.020383 -1 -1 -1 -1 46 659 28 151211 126010 57775.2 2311.01 0.98 0.133566 0.118166 2220 9391 -1 557 21 689 1063 30471 14107 5.4787 5.4787 -101.9 -5.4787 0 0 73020.3 2920.81 0.01 0.10 0.01 -1 -1 0.01 0.0322818 0.0292918 44 66 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 8.82 vpr 65.02 MiB -1 -1 0.16 18400 1 0.04 -1 -1 30676 -1 -1 6 19 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66576 19 18 308 249 1 133 43 5 5 25 clb auto 25.4 MiB 5.91 453 1993 498 1475 20 65.0 MiB 0.14 0.00 4.85986 -99.1517 -4.85986 4.85986 0.04 0.000524482 0.000482714 0.0388578 0.0376049 -1 -1 -1 -1 48 705 25 151211 151211 59785.0 2391.40 0.96 0.168776 0.152151 2244 9614 -1 614 16 592 999 32515 15691 4.9757 4.9757 -106.674 -4.9757 0 0 75076.4 3003.05 0.01 0.17 0.01 -1 -1 0.01 0.0312715 0.028896 53 83 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.57 vpr 66.20 MiB -1 -1 0.12 21572 1 0.03 -1 -1 33720 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.67 85 398 116 276 6 66.2 MiB 0.01 0.00 2.48207 -27.4234 -2.48207 2.48207 0.03 0.000168115 0.000148552 0.00382732 0.00348451 -1 -1 -1 -1 26 186 18 151211 75605.7 37105.9 1484.24 0.07 0.0274796 0.0239744 1908 5841 -1 144 14 104 128 3783 2136 2.42625 2.42625 -32.7566 -2.42625 0 0 45067.1 1802.68 0.00 0.01 0.01 -1 -1 0.00 0.00858616 0.00782966 13 18 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.85 vpr 66.12 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33420 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67704 11 10 108 97 1 49 23 4 4 16 clb auto 26.9 MiB 2.02 135 87 35 39 13 66.1 MiB 0.00 0.00 3.45122 -42.4992 -3.45122 3.45122 0.01 0.000185565 0.000169189 0.00161119 0.00153779 -1 -1 -1 -1 34 225 26 50403.8 50403.8 21558.4 1347.40 0.10 0.0502132 0.0405962 1020 3049 -1 158 14 151 165 4063 2532 3.88646 3.88646 -47.5118 -3.88646 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00719488 0.00664889 15 27 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.48 vpr 66.58 MiB -1 -1 0.14 21316 1 0.03 -1 -1 33560 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68180 13 12 149 129 1 68 32 6 6 36 clb auto 27.2 MiB 5.18 196 882 281 588 13 66.6 MiB 0.01 0.00 3.49758 -52.6333 -3.49758 3.49758 0.04 0.000188427 0.000167514 0.00680212 0.00627325 -1 -1 -1 -1 40 395 29 403230 176413 88484.8 2457.91 0.24 0.0901214 0.0785509 3734 16003 -1 328 14 283 356 13658 6213 3.44595 3.44595 -58.2463 -3.44595 0 0 110337. 3064.92 0.00 0.04 0.03 -1 -1 0.00 0.0323499 0.0245182 25 38 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.00 vpr 66.86 MiB -1 -1 0.14 21572 1 0.03 -1 -1 33512 -1 -1 7 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 15 14 196 165 1 92 36 6 6 36 clb auto 27.2 MiB 2.65 304 744 159 567 18 66.9 MiB 0.02 0.00 3.62628 -64.4645 -3.62628 3.62628 0.05 0.000406252 0.000363743 0.00800716 0.00737412 -1 -1 -1 -1 52 651 42 403230 176413 110337. 3064.92 0.29 0.109536 0.0955888 4014 20275 -1 496 16 373 551 19804 8423 3.5903 3.5903 -70.6456 -3.5903 0 0 143382. 3982.83 0.00 0.03 0.03 -1 -1 0.00 0.0200523 0.0184119 37 51 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.34 vpr 67.21 MiB -1 -1 0.16 21320 1 0.03 -1 -1 33716 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68824 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 6.96 396 2495 611 1868 16 67.2 MiB 0.04 0.00 3.8369 -73.5721 -3.8369 3.8369 0.03 0.000487285 0.000432143 0.0227482 0.0204679 -1 -1 -1 -1 46 672 23 151211 126010 57775.2 2311.01 0.27 0.134818 0.118379 2220 9391 -1 565 21 712 1067 32893 15487 5.93712 5.93712 -106.904 -5.93712 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0286301 0.0260985 44 66 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.49 vpr 67.34 MiB -1 -1 0.15 21572 1 0.03 -1 -1 33768 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68960 19 18 308 249 1 133 43 5 5 25 clb auto 27.8 MiB 6.09 448 2143 525 1607 11 67.3 MiB 0.04 0.00 4.70186 -94.0493 -4.70186 4.70186 0.03 0.000586405 0.000522924 0.0211391 0.0191781 -1 -1 -1 -1 46 706 50 151211 151211 57775.2 2311.01 0.36 0.18155 0.16007 2220 9391 -1 599 18 697 1112 32896 15750 4.84188 4.84188 -104.71 -4.84188 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0301574 0.0276463 53 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt index b2a92d253ed..900ba99d8f4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 7.44 vpr 56.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57804 6 7 19 26 0 19 26 3 3 9 -1 auto 17.7 MiB 0.04 51 216 43 63 110 56.4 MiB 0.19 0.01 3.682 -25.774 -3.682 nan 5.70 9.9275e-05 8.7239e-05 0.00080976 0.000700914 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.17 0.00664803 0.00634555 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.01 0.05 0.04 -1 -1 0.01 0.00241331 0.00228144 + sub_tiles.xml sub_tiles.blif common 17.03 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.49 3.9173e-05 3.1698e-05 0.000338068 0.000271828 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00193749 0.00171766 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00201882 0.00189534 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt index 7566db0b692..160cbfe1388 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.62 vpr 56.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57764 2 2 4 5 0 4 5 3 3 9 -1 auto 17.7 MiB 0.04 8 12 0 0 12 56.4 MiB 0.03 0.00 1.899 -3.798 -1.899 nan 0.03 2.0146e-05 1.5134e-05 0.000136441 0.000104751 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.06 0.00289731 0.0027087 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00137522 0.00133686 + heterogeneous_tile.xml sub_tile_directs.blif common 0.33 vpr 59.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60416 2 2 4 5 0 4 5 3 3 9 -1 auto 20.7 MiB 0.00 8 12 0 0 12 59.0 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7245e-05 1.217e-05 9.686e-05 7.1239e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.0017081 0.00158045 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00139703 0.00135574 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index df06df92e99..6303f27bd50 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.39 vpr 64.02 MiB -1 -1 0.45 18932 3 0.10 -1 -1 33272 -1 -1 19 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65552 99 73 292 365 1 173 192 8 8 64 io memory auto 24.8 MiB 0.19 683 14570 2226 10547 1797 64.0 MiB 0.07 0.00 2.10913 -115.89 -2.10913 2.10913 0.14 0.000747466 0.000694634 0.0201045 0.0187259 -1 -1 -1 -1 32 1229 14 2.23746e+06 1.57199e+06 106908. 1670.44 2.05 0.296954 0.265952 4378 18911 -1 1110 9 491 754 35474 12126 1.99714 1.99714 -132.662 -1.99714 -0.34191 -0.0876569 130676. 2041.82 0.05 0.13 0.03 -1 -1 0.05 0.027581 0.0256138 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 vpr 66.86 MiB -1 -1 0.36 22284 3 0.10 -1 -1 36712 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 99 73 292 365 1 173 192 8 8 64 io memory auto 27.1 MiB 0.06 704 10699 1176 8237 1286 66.9 MiB 0.06 0.00 2.09255 -114.438 -2.09255 2.09255 0.09 0.000494971 0.000445037 0.0176268 0.0158319 -1 -1 -1 -1 32 1440 34 2.23746e+06 1.57199e+06 106908. 1670.44 0.32 0.14258 0.127902 4378 18911 -1 1142 12 555 876 46439 15775 1.9226 1.9226 -129.963 -1.9226 -0.449924 -0.248875 130676. 2041.82 0.01 0.04 0.02 -1 -1 0.01 0.0280032 0.0259551 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index e92c164cb11..9a4d84cf163 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 3.33 vpr 66.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67708 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.25 396 511 91 400 20 66.1 MiB 0.09 0.00 2.39024 -27.2311 -2.39024 2.39024 0.06 0.000971201 0.000900811 0.0143984 0.0134813 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.65 0.234894 0.204034 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.17 0.01 -1 -1 0.01 0.0431247 0.0391487 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 3.34 vpr 66.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67808 10 10 168 178 1 73 31 6 6 36 clb auto 26.6 MiB 0.22 396 511 91 400 20 66.2 MiB 0.08 0.00 2.39024 -27.2311 -2.39024 2.39024 0.06 0.00063912 0.000574742 0.0133256 0.0125205 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.99 0.279091 0.24285 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.08 0.01 -1 -1 0.01 0.0417208 0.0376776 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 6.02 vpr 66.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68128 10 10 168 178 1 162 111 14 14 196 clb auto 26.8 MiB 0.95 1456 5963 865 4880 218 66.5 MiB 0.13 0.00 3.05524 -37.9348 -3.05524 3.05524 0.59 0.000646566 0.000596261 0.02071 0.019112 -1 -1 -1 -1 26 2865 15 9.20055e+06 4.90435e+06 387483. 1976.95 2.42 0.211695 0.185383 18784 74779 -1 2696 13 472 1947 107713 24081 3.50167 3.50167 -42.0838 -3.50167 0 0 467681. 2386.13 0.16 0.11 0.07 -1 -1 0.16 0.0279753 0.0255829 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 2.84 vpr 66.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67764 10 10 168 178 1 75 33 7 7 49 clb auto 26.6 MiB 0.23 404 813 125 661 27 66.2 MiB 0.10 0.00 2.45517 -27.3027 -2.45517 2.45517 0.09 0.000647339 0.000599538 0.0197487 0.0185137 -1 -1 -1 -1 26 1116 28 1.07788e+06 700622 75813.7 1547.22 1.14 0.148701 0.13165 3816 13734 -1 925 18 487 1699 71725 25249 2.97305 2.97305 -35.2593 -2.97305 0 0 91376.6 1864.83 0.02 0.24 0.01 -1 -1 0.02 0.0460889 0.0423163 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 5.34 vpr 66.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68236 10 10 168 178 1 163 124 14 14 196 clb auto 26.9 MiB 1.00 1516 7540 1142 6103 295 66.6 MiB 0.21 0.00 3.06133 -37.7953 -3.06133 3.06133 0.60 0.000630456 0.00057306 0.0281512 0.0261658 -1 -1 -1 -1 20 2911 18 9.20055e+06 5.60498e+06 354876. 1810.58 1.60 0.106074 0.094968 18004 60473 -1 2874 12 603 2265 131794 29163 3.74152 3.74152 -44.1586 -3.74152 0 0 387483. 1976.95 0.14 0.17 0.06 -1 -1 0.14 0.0262615 0.0240198 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 3.16 vpr 66.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67760 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.20 396 511 91 400 20 66.2 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.000653728 0.000608322 0.012902 0.0121572 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.78 0.26636 0.230807 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.17 0.01 -1 -1 0.01 0.0463537 0.0422043 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 3.43 vpr 66.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67944 10 10 168 178 1 73 31 6 6 36 clb auto 26.8 MiB 0.22 396 511 91 400 20 66.4 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.04 0.000508161 0.000456687 0.0109247 0.0102847 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.85 0.27407 0.239119 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.27 0.01 -1 -1 0.01 0.0493788 0.0449139 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 6.33 vpr 66.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68212 10 10 168 178 1 162 111 14 14 196 clb auto 26.8 MiB 0.96 1456 5963 865 4880 218 66.6 MiB 0.14 0.00 3.05524 -37.9348 -3.05524 3.05524 0.62 0.000637905 0.00057522 0.0218552 0.0201449 -1 -1 -1 -1 26 2865 15 9.20055e+06 4.90435e+06 387483. 1976.95 2.71 0.215189 0.189178 18784 74779 -1 2696 13 472 1947 107713 24081 3.50167 3.50167 -42.0838 -3.50167 0 0 467681. 2386.13 0.18 0.11 0.06 -1 -1 0.18 0.0286783 0.0262735 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 3.51 vpr 66.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67772 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.24 396 511 91 400 20 66.2 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.000503086 0.00045843 0.00994809 0.00934025 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 1.86 0.256569 0.222631 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.28 0.01 -1 -1 0.01 0.0490284 0.0446 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.19 vpr 27.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28592 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.19 vpr 27.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28608 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.13 vpr 27.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28604 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.26 vpr 28.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28700 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_1 1.36 vpr 68.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70192 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.18 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000585274 0.000508741 0.0133922 0.0121686 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183472 0.161021 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0299915 0.0274705 + EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.08 vpr 68.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70320 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.7 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000329127 0.000280288 0.00811479 0.00735661 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.35 0.13039 0.113608 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0216396 0.0198831 + EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.83 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70724 10 10 168 178 1 162 111 14 14 196 clb auto 29.5 MiB 0.87 1467 5165 686 4267 212 69.1 MiB 0.06 0.00 2.95542 -36.8348 -2.95542 2.95542 0.33 0.000607935 0.000523594 0.0180811 0.0161249 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.224715 0.196946 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.10 -1 -1 0.03 0.0292402 0.0269351 + EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.85 vpr 68.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69972 10 10 168 178 1 75 33 7 7 49 clb auto 28.8 MiB 0.15 414 605 98 486 21 68.3 MiB 0.01 0.00 2.40687 -27.3475 -2.40687 2.40687 0.04 0.000340986 0.000290037 0.00724905 0.00664099 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.16 0.0618811 0.0547109 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.03 0.01 -1 -1 0.00 0.0207833 0.0191052 + EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.40 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70700 10 10 168 178 1 163 124 14 14 196 clb auto 29.4 MiB 0.95 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.22 0.000345985 0.000292911 0.012717 0.0113191 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.21 0.0326189 0.0295477 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.08 -1 -1 0.03 0.0265139 0.024324 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.40 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70232 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.6 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000587109 0.000509454 0.0135198 0.0122638 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183086 0.160678 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0347629 0.0319856 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.32 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70240 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.16 399 703 140 536 27 68.6 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.03 0.000756907 0.000658585 0.016978 0.0153763 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.44 0.169468 0.148387 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.03477 0.0320116 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.38 vpr 68.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70504 10 10 168 178 1 162 111 14 14 196 clb auto 29.2 MiB 0.88 1467 5165 686 4267 212 68.9 MiB 0.04 0.00 2.95542 -36.8348 -2.95542 2.95542 0.28 0.000322881 0.000275771 0.0115436 0.0102519 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.09 0.158857 0.137775 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.02 0.05 0.05 -1 -1 0.02 0.0172724 0.0158752 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.48 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70176 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000502609 0.00043998 0.0125423 0.0114378 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.54 0.190745 0.166737 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.07 0.02 -1 -1 0.00 0.0474457 0.0433946 + EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 30.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30760 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30632 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 30.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31272 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt index 070dd53f47f..b99a452bc00 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 9.14 vpr 72.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74668 229 197 2152 2349 1 1013 576 16 16 256 io auto 33.4 MiB 3.18 8848 180201 52690 111830 15681 72.9 MiB 1.51 0.02 2.99388 -664.24 -2.99388 2.99388 0.00 0.00626795 0.00568046 0.542629 0.481854 -1 -1 -1 -1 -1 11423 9 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.27 0.752915 0.676781 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 8.05 vpr 75.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76868 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.4 MiB 3.87 8858 177806 51921 111135 14750 75.1 MiB 1.04 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00614227 0.00545306 0.382618 0.335662 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.30 0.645332 0.579161 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt index 8576e7f7dc7..c7b87ad96d9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 -k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 -k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 19.81 vpr 62.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-13020-g9db19397a Release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T14:55:09 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 63832 64 39 1935 1974 1 1077 541 23 23 529 clb auto 23.1 MiB 0.33 23383 10407 130518 33236 93921 3361 62.3 MiB 1.45 0.02 13.1424 7.01436 -1186.76 -7.01436 7.01436 0.50 0.00278506 0.0021586 0.190009 0.145283 -1 -1 -1 -1 30 18484 49 983127 976439 713134. 1348.08 14.21 1.06254 0.869067 34090 111051 -1 19671 23 8649 30686 3584279 1256529 7.46036 7.46036 -1487.87 -7.46036 0 0 855979. 1618.11 0.12 1.13 -1 -1 -1 0.12 0.186892 0.161913 +k4_N4_tileable_90nm.xml ex5p.blif common 24.85 vpr 58.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-13020-g9db19397a Release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T14:55:09 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59604 8 63 1072 1135 0 894 437 22 22 484 clb auto 19.0 MiB 0.26 20320 12148 81630 19773 60101 1756 58.1 MiB 0.95 0.02 7.91494 5.42874 -233.124 -5.42874 nan 0.46 0.00184499 0.00135252 0.103436 0.0807114 -1 -1 -1 -1 58 21250 25 891726 815929 1.11794e+06 2309.80 19.84 0.848059 0.694504 50136 186432 -1 21807 22 9790 33292 5274291 1466232 5.49118 nan -247.625 -5.49118 0 0 1.39817e+06 2888.78 0.20 1.26 -1 -1 -1 0.20 0.112893 0.0976021 +k4_N4_tileable_90nm.xml s298.blif common 37.04 vpr 68.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-13020-g9db19397a Release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T14:55:09 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 70248 4 6 1942 1948 1 1169 590 27 27 729 clb auto 25.2 MiB 0.34 27324 13487 148970 40500 107491 979 68.6 MiB 1.82 0.03 15.4416 9.90815 -77.1816 -9.90815 9.90815 0.71 0.0031275 0.00242 0.2127 0.16542 -1 -1 -1 -1 34 24602 39 1.39333e+06 1.29301e+06 1.12707e+06 1546.05 28.80 1.56376 1.28245 50282 172723 -1 28340 30 12129 58881 11129903 3411240 10.0924 10.0924 -86.1832 -10.0924 0 0 1.32680e+06 1820.03 0.17 2.63 -1 -1 -1 0.17 0.220331 0.186786 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt index 8576e7f7dc7..1ec53c07bd8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 -k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 -k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_perimeter_cb_90nm.xml diffeq.blif common 16.22 vpr 62.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 64028 64 39 1935 1974 1 1077 541 23 23 529 clb auto 23.3 MiB 0.32 23383 10252 119503 28618 87175 3710 62.5 MiB 1.34 0.02 13.2048 7.13924 -1172.08 -7.13924 7.13924 0.57 0.00281932 0.00216196 0.173313 0.133573 -1 -1 -1 -1 34 18135 26 983127 976439 897386. 1696.38 10.12 0.961872 0.787041 40002 146231 -1 21299 25 9235 32958 4733492 1780844 7.08492 7.08492 -1502.77 -7.08492 0 0 1.04845e+06 1981.94 0.15 1.39 -1 -1 -1 0.15 0.189526 0.162735 +k4_N4_tileable_perimeter_cb_90nm.xml ex5p.blif common 42.06 vpr 58.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59644 8 63 1072 1135 0 894 437 22 22 484 clb auto 19.0 MiB 0.26 20320 11946 86601 21898 63026 1677 58.2 MiB 1.03 0.02 7.95072 5.28278 -233.118 -5.28278 nan 0.52 0.00193544 0.00142786 0.111869 0.0866652 -1 -1 -1 -1 50 20745 26 891726 815929 1.11061e+06 2294.66 36.41 0.787577 0.645158 48048 178976 -1 23642 21 10261 34242 6998785 2421199 5.87736 nan -261.019 -5.87736 0 0 1.28980e+06 2664.87 0.17 1.62 -1 -1 -1 0.17 0.107382 0.0929134 +k4_N4_tileable_perimeter_cb_90nm.xml s298.blif common 53.44 vpr 72.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 74664 4 6 1942 1948 1 1169 590 27 27 729 clb auto 25.0 MiB 0.35 27324 13425 148970 41008 107008 954 72.9 MiB 1.84 0.03 15.2089 9.65839 -76.0928 -9.65839 9.65839 0.81 0.00340369 0.00261843 0.224099 0.175111 -1 -1 -1 -1 34 24976 25 1.39333e+06 1.29301e+06 1.24041e+06 1701.52 45.33 1.66978 1.36439 54994 199951 -1 28059 24 11455 54709 8763089 2638513 10.1962 10.1962 -84.1267 -10.1962 0 0 1.45188e+06 1991.60 0.18 2.10 -1 -1 -1 0.18 0.186815 0.160845 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt index 8576e7f7dc7..bb617d6fd9e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 -k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 -k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_tileable_90nm.xml diffeq.blif common 7.52 vpr 62.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 63840 64 39 1935 1974 1 1077 541 23 23 529 clb auto 23.1 MiB 0.32 23383 10407 130518 33236 93921 3361 62.3 MiB 1.44 0.02 13.1424 7.01436 -1186.76 -7.01436 7.01436 0.00 0.00273601 0.00211561 0.187595 0.143154 -1 -1 -1 -1 19245 17.8857 11150 10.3625 7421 25910 2845736 884425 983127 976439 1.22961e+06 2324.41 18 45530 160719 -1 7.37964 7.37964 -1373.48 -7.37964 0 0 -1 -1 -1 62.3 MiB 0.87 0.347277 0.281856 62.3 MiB -1 0.18 +k4_N4_tileable_90nm.xml ex5p.blif common 9.78 vpr 58.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 59836 8 63 1072 1135 0 894 437 22 22 484 clb auto 18.8 MiB 0.26 20320 12148 81630 19773 60101 1756 58.4 MiB 0.96 0.02 7.91494 5.42874 -233.124 -5.42874 nan 0.00 0.00181633 0.00135353 0.102123 0.0792786 -1 -1 -1 -1 24636 27.5570 13596 15.2081 10695 36592 10880255 4591282 891726 815929 1.11756e+06 2309.00 31 41484 146288 -1 6.67754 nan -291.675 -6.67754 0 0 -1 -1 -1 58.4 MiB 2.78 0.258159 0.213053 58.4 MiB -1 0.17 +k4_N4_tileable_90nm.xml s298.blif common 11.27 vpr 65.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66640 4 6 1942 1948 1 1169 590 27 27 729 clb auto 25.0 MiB 0.35 27324 13487 148970 40500 107491 979 65.1 MiB 1.82 0.03 15.4416 9.90815 -77.1816 -9.90815 9.90815 0.00 0.00345442 0.0027131 0.213085 0.165433 -1 -1 -1 -1 28424 24.3356 15352 13.1438 11036 53711 8284367 2041058 1.39333e+06 1.29301e+06 1.73135e+06 2374.97 22 63594 225223 -1 9.88398 9.88398 -83.5517 -9.88398 0 0 -1 -1 -1 65.1 MiB 2.28 0.435186 0.358877 65.1 MiB -1 0.26 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt index 8576e7f7dc7..8a8cf8f4f29 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 -k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 -k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_tileable_90nm.xml diffeq.blif common 7.48 vpr 65.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 67540 64 39 1935 1974 1 1077 541 23 23 529 clb auto 22.9 MiB 0.32 23383 10873 130518 33024 93628 3866 66.0 MiB 1.45 0.02 13.0763 6.99652 -1162.99 -6.99652 6.99652 0.00 0.00285671 0.00221991 0.189815 0.145412 -1 -1 -1 -1 18849 17.5177 10317 9.58829 6567 21821 1854731 449487 983127 976439 2.00514e+06 3790.43 20 70170 268455 -1 7.25476 7.25476 -1304.75 -7.25476 0 0 -1 -1 -1 66.0 MiB 0.75 0.363502 0.296117 66.0 MiB -1 0.31 +k4_N4_tileable_90nm.xml ex5p.blif common 6.79 vpr 58.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 60028 8 63 1072 1135 0 894 437 22 22 484 clb auto 18.8 MiB 0.26 20320 12136 81630 20496 59555 1579 58.6 MiB 0.96 0.02 7.72232 5.21275 -226.687 -5.21275 nan 0.00 0.00182646 0.00137253 0.108622 0.0845891 -1 -1 -1 -1 21866 24.4586 10468 11.7092 8501 29146 3873168 891811 891726 815929 1.82197e+06 3764.41 19 63912 244296 -1 5.56516 nan -246.308 -5.56516 0 0 -1 -1 -1 58.6 MiB 1.05 0.222148 0.183769 58.6 MiB -1 0.28 +k4_N4_tileable_90nm.xml s298.blif common 9.95 vpr 85.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-13021-g345d251e3-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-20T19:05:16 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 87228 4 6 1942 1948 1 1169 590 27 27 729 clb auto 25.0 MiB 0.35 27324 13569 146497 39933 105616 948 85.2 MiB 1.82 0.03 15.2069 10.0243 -77.5741 -10.0243 10.0243 0.00 0.00351567 0.00274926 0.230835 0.183363 -1 -1 -1 -1 24793 21.2269 12639 10.8211 7296 37518 4021317 704688 1.39333e+06 1.29301e+06 2.82552e+06 3875.88 19 98122 376471 -1 10.1962 10.1962 -80.531 -10.1962 0 0 -1 -1 -1 85.2 MiB 1.40 0.430119 0.358207 85.2 MiB -1 0.45 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index e837cb2407d..b003134057c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 6.33 vpr 65.84 MiB -1 -1 0.42 18744 3 0.10 -1 -1 33376 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67424 99 130 344 474 1 227 298 12 12 144 clb auto 26.1 MiB 0.24 717 72933 22876 34411 15646 65.8 MiB 0.50 0.01 1.84343 -118.171 -1.84343 1.84343 0.34 0.000999398 0.000934504 0.0982577 0.092362 -1 -1 -1 -1 38 1540 14 5.66058e+06 4.21279e+06 319130. 2216.18 2.76 0.374935 0.344885 12522 62564 -1 1261 9 399 607 24533 7188 1.90841 1.90841 -134.095 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.14 0.13 0.07 -1 -1 0.14 0.0314453 0.0295015 - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 6.28 vpr 65.81 MiB -1 -1 0.35 18932 3 0.11 -1 -1 33264 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67392 99 130 344 474 1 227 298 12 12 144 clb auto 26.0 MiB 0.23 717 72933 22876 34411 15646 65.8 MiB 0.47 0.00 1.84343 -118.171 -1.84343 1.84343 0.37 0.000579812 0.000531042 0.0759736 0.0701905 -1 -1 -1 -1 38 1540 14 5.66058e+06 4.21279e+06 319130. 2216.18 2.68 0.230578 0.208922 12522 62564 -1 1261 9 399 607 24533 7188 1.90841 1.90841 -134.095 -1.90841 -1.28606 -0.31945 406292. 2821.48 0.13 0.14 0.07 -1 -1 0.13 0.0211432 0.0195748 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.63 vpr 68.02 MiB -1 -1 0.39 22168 3 0.11 -1 -1 36800 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69656 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.23 0.00 1.86472 -118.834 -1.86472 1.86472 0.15 0.000594963 0.000540506 0.0732034 0.0668337 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.54 0.213559 0.195205 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.08 -1 -1 0.02 0.0300207 0.027912 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 2.86 vpr 68.12 MiB -1 -1 0.35 22168 3 0.11 -1 -1 36740 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69760 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.1 MiB 0.27 0.00 1.86472 -118.834 -1.86472 1.86472 0.21 0.000644886 0.000574461 0.100184 0.0946805 -1 -1 -1 -1 38 1379 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.64 0.202724 0.187418 12522 62564 -1 1115 10 390 630 21561 6939 1.90702 1.90702 -131.117 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.021384 0.0193317 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt index 0caf65de4b1..7b4fc76c6e6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 6.52 vpr 66.06 MiB -1 -1 0.44 19044 3 0.11 -1 -1 33268 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67644 99 130 344 474 1 225 298 12 12 144 clb auto 26.2 MiB 0.22 734 75918 23628 39360 12930 66.1 MiB 0.49 0.01 1.84343 -75.0087 -1.84343 1.84343 0.33 0.000857681 0.000789515 0.0812026 0.0751694 -1 -1 -1 -1 36 1518 6 5.66058e+06 4.21279e+06 305235. 2119.69 3.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.55 vpr 67.97 MiB -1 -1 0.42 22420 3 0.14 -1 -1 36800 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69600 99 130 344 474 1 225 298 12 12 144 clb auto 28.5 MiB 0.19 695 57013 16754 28454 11805 68.0 MiB 0.25 0.00 1.84453 -73.0907 -1.84453 1.84453 0.29 0.000572985 0.000494317 0.0593261 0.049655 -1 -1 -1 -1 32 1551 10 5.66058e+06 4.21279e+06 281316. 1953.58 1.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt index 120a1a483e0..50b6703de2b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 6.29 vpr 65.84 MiB -1 -1 0.44 18932 3 0.10 -1 -1 33272 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67416 99 130 344 474 1 218 298 12 12 144 clb auto 26.1 MiB 0.29 706 75918 21357 39248 15313 65.8 MiB 0.45 0.00 2.17824 0 0 2.17824 0.39 0.000858537 0.000799712 0.0715997 0.0663405 -1 -1 -1 -1 38 1473 11 5.66058e+06 4.21279e+06 319130. 2216.18 2.60 0.302049 0.26108 12522 62564 -1 1300 5 274 392 20827 6674 2.27647 2.27647 0 0 0 0 406292. 2821.48 0.14 0.10 0.06 -1 -1 0.14 0.0177896 0.0166081 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.13 vpr 67.88 MiB -1 -1 0.41 22284 3 0.13 -1 -1 36924 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69508 99 130 344 474 1 218 298 12 12 144 clb auto 28.4 MiB 0.23 632 70943 19608 36161 15174 67.9 MiB 0.23 0.00 2.24009 0 0 2.24009 0.25 0.000717536 0.00062496 0.0508972 0.0435443 -1 -1 -1 -1 32 1480 8 5.66058e+06 4.21279e+06 281316. 1953.58 0.55 0.227253 0.196073 11950 52952 -1 1327 7 304 419 24960 8371 2.42926 2.42926 0 0 0 0 345702. 2400.71 0.03 0.05 0.08 -1 -1 0.03 0.020098 0.0186968 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index 2d3ef814bc3..a5bee947840 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.99 vpr 64.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66448 5 3 11 14 2 9 10 4 4 16 clb auto 26.2 MiB 0.03 20 30 10 17 3 64.9 MiB 0.05 0.00 0.619658 -3.41326 -0.619658 0.545 0.02 8.2559e-05 6.5087e-05 0.000398248 0.000321879 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.06 0.00241051 0.0022076 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00164607 0.00157893 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 1.08 vpr 64.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66508 5 3 11 14 2 9 10 4 4 16 clb auto 26.2 MiB 0.04 20 30 10 17 3 64.9 MiB 0.05 0.00 0.619658 -3.41326 -0.619658 0.545 0.03 4.7357e-05 3.5078e-05 0.000316498 0.00025661 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.07 0.00236598 0.00217158 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.01 0.02 0.00 -1 -1 0.01 0.00296841 0.00285153 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.91 vpr 64.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66344 5 3 11 14 2 9 10 4 4 16 clb auto 26.0 MiB 0.03 20 30 10 17 3 64.8 MiB 0.05 0.00 0.619658 -3.41326 -0.619658 0.545 0.01 5.2206e-05 3.8166e-05 0.000401216 0.000334324 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.08 0.003085 0.00285493 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00168486 0.00161817 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.50 vpr 67.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68660 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.6443e-05 3.2529e-05 0.000274786 0.000214986 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00211509 0.0019009 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0017763 0.00169895 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.49 vpr 67.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8016e-05 3.4218e-05 0.000283686 0.000224427 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0022472 0.00206472 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00179634 0.00171755 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.51 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68932 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 6.2523e-05 4.6425e-05 0.000366128 0.000294026 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00236124 0.00216436 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00189537 0.00181322 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt index f51e39ff90c..db634e1dc04 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 4.53 vpr 66.47 MiB -1 -1 0.88 23160 4 0.16 -1 -1 33060 -1 -1 15 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68068 11 2 303 283 2 78 28 7 7 49 clb auto 26.9 MiB 0.44 264 1036 209 767 60 66.5 MiB 0.10 0.00 2.03811 -163.536 -2.03811 1.90043 0.00 0.000562272 0.000493381 0.0211263 0.0192484 -1 -1 -1 -1 -1 252 12 1.07788e+06 808410 219490. 4479.39 0.11 0.0624165 0.0568117 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.81 vpr 69.01 MiB -1 -1 0.66 26668 4 0.21 -1 -1 35972 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70664 11 2 303 283 2 78 28 7 7 49 clb auto 29.4 MiB 0.25 285 784 175 539 70 69.0 MiB 0.04 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000759025 0.000652417 0.0254764 0.023241 -1 -1 -1 -1 -1 313 6 1.07788e+06 808410 219490. 4479.39 0.03 0.050656 0.046841 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index 9362353dbf8..e65df342f6a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 2.80 vpr 63.72 MiB -1 -1 0.89 23420 5 0.16 -1 -1 33496 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65252 10 2 181 183 1 35 24 6 6 36 clb auto 24.3 MiB 0.18 146 398 72 298 28 63.7 MiB 0.11 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000499863 0.00046066 0.00865418 0.0080588 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.24 0.0402973 0.0330423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 2.83 vpr 63.66 MiB -1 -1 0.80 23512 5 0.19 -1 -1 33392 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65184 10 2 181 183 1 35 24 6 6 36 clb auto 24.2 MiB 0.21 146 398 72 298 28 63.7 MiB 0.10 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000520313 0.000485956 0.0108727 0.0101292 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.21 0.0390899 0.0350474 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 2.77 vpr 63.91 MiB -1 -1 0.93 23472 5 0.18 -1 -1 33404 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65448 10 2 181 183 1 35 24 6 6 36 clb auto 24.4 MiB 0.20 146 398 72 298 28 63.9 MiB 0.09 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 2.0662e-05 7.982e-06 0.00379409 0.00346778 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.15 0.0197222 0.0139137 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 2.83 vpr 63.69 MiB -1 -1 0.94 23484 5 0.18 -1 -1 33404 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65220 10 2 181 183 1 35 24 6 6 36 clb auto 24.3 MiB 0.24 146 398 72 298 28 63.7 MiB 0.08 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.000152071 3.7143e-05 0.0036681 0.00317106 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.15 0.0186284 0.0137477 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 2.80 vpr 63.70 MiB -1 -1 0.90 23532 5 0.15 -1 -1 33352 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65228 10 2 181 183 1 35 24 6 6 36 clb auto 24.3 MiB 0.17 146 398 72 298 28 63.7 MiB 0.10 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 2.2661e-05 4.617e-06 0.00351006 0.00294492 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.25 0.0171787 0.012971 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 2.92 vpr 63.56 MiB -1 -1 0.89 23528 5 0.16 -1 -1 33396 -1 -1 12 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65088 10 2 181 183 1 35 24 6 6 36 clb auto 24.4 MiB 0.25 146 398 72 298 28 63.6 MiB 0.08 0.00 2.14835 -92.8998 -2.14835 2.14835 0.00 0.00212777 0.00209414 0.00814338 0.00754222 -1 -1 -1 -1 -1 130 24 646728 646728 138825. 3856.24 0.25 0.0344922 0.0314797 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.06 vpr 65.94 MiB -1 -1 0.49 27024 5 0.12 -1 -1 36972 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67520 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000242517 0.000210755 0.00440565 0.00392683 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0164282 0.0146736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.57 vpr 66.14 MiB -1 -1 0.70 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000439525 0.000384869 0.00748551 0.00667971 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.02 0.0256815 0.0230005 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.67 vpr 66.16 MiB -1 -1 0.82 27152 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 3.5959e-05 2.737e-05 0.00308117 0.00275747 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0135928 0.0105523 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.25 vpr 66.16 MiB -1 -1 0.65 27036 5 0.12 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000221863 9.7941e-05 0.00222519 0.00187901 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.00928043 0.00694563 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.74 vpr 66.05 MiB -1 -1 0.84 26784 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67632 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 5.1198e-05 3.2395e-05 0.002938 0.00248994 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.02 0.0136494 0.00987341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 2.01 vpr 66.03 MiB -1 -1 0.85 27040 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67616 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00150082 0.00142957 0.0169996 0.0159511 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.07 0.0553928 0.0438556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index cbf1d188143..e84a1129700 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 79.71 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1213252 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1062.8 MiB 17.41 70903 253216 51547 191577 10092 1176.1 MiB 11.03 0.15 4.99319 -5223.26 -3.99319 2.64446 0.01 0.0404503 0.0335948 3.08815 2.57709 83183 6.68835 19827 1.59419 25954 36248 10076288 1815088 0 0 2.05929e+07 18207.7 15 331560 3499109 -1 5.28806 2.7363 -5589.94 -4.28806 0 0 7.56 -1 -1 1176.1 MiB 4.03 4.74901 4.02053 1176.1 MiB -1 19.41 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.79 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215864 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.3 MiB 15.63 75097 245792 47628 188491 9673 1158.7 MiB 16.87 0.21 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0552629 0.0482483 4.22516 3.43532 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 5.27 -1 -1 1158.7 MiB 5.35 6.14131 5.12726 1158.7 MiB -1 3.33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt index 159ae69716e..7d3888ea0e0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 20.78 vpr 383.20 MiB 35 93 0 0 8 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 392392 18 17 2338 2195 1 2035 136 17 13 221 io_cell auto 341.0 MiB 8.88 11702 14096 2182 10467 1447 383.2 MiB 0.99 0.02 3.767 -3201.39 -2.767 3.767 0.00 0.00771503 0.0062784 0.427042 0.368396 12703 6.25148 3920 1.92913 6529 15398 3929307 843439 0 0 3.37726e+06 15281.7 12 52540 541133 -1 3.447 3.447 -2841.9 -2.447 0 0 1.26 -1 -1 383.2 MiB 1.58 0.852394 0.762998 383.2 MiB -1 2.05 + stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 19.43 vpr 384.88 MiB 35 93 0 0 8 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 394112 18 17 2338 2195 1 2035 136 17 13 221 io_cell auto 342.6 MiB 9.23 11597 14096 2127 10583 1386 384.9 MiB 0.99 0.03 3.78594 -3334.96 -2.78594 3.78594 0.00 0.0127693 0.0106573 0.428449 0.35312 12754 6.27657 3971 1.95423 6857 16497 4298918 925978 0 0 3.37726e+06 15281.7 12 52540 541133 -1 3.215 3.215 -2910.24 -2.215 0 0 1.33 -1 -1 384.9 MiB 1.91 0.811838 0.706005 384.9 MiB -1 0.27 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 05a82915baf..6ff0e8d886f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 17.29 vpr 67.58 MiB -1 -1 0.41 22592 5 0.17 -1 -1 34192 -1 -1 17 66 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69200 66 96 983 697 1 557 191 16 16 256 mult_27 auto 28.6 MiB 2.01 4754 40817 12099 23524 5194 67.6 MiB 0.65 0.01 16.4391 -978.659 -16.4391 16.4391 0.88 0.00273549 0.00258048 0.232507 0.218951 -1 -1 -1 -1 64 11429 28 4.83877e+06 1.03328e+06 1.35562e+06 5295.38 9.13 0.948515 0.877899 40360 280887 -1 10218 18 3342 7052 1691763 500137 17.028 17.028 -1086.21 -17.028 0 0 1.67258e+06 6533.53 0.58 0.52 0.31 -1 -1 0.58 0.136104 0.128889 138 202 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 22.01 vpr 69.98 MiB -1 -1 0.42 25672 5 0.18 -1 -1 37676 -1 -1 17 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 71656 66 96 983 697 1 557 191 16 16 256 mult_27 auto 30.8 MiB 2.52 4520 41915 13784 24449 3682 70.0 MiB 0.47 0.01 16.7771 -983.813 -16.7771 16.7771 0.51 0.00380097 0.00356084 0.223806 0.20783 -1 -1 -1 -1 82 9891 30 4.83877e+06 1.03328e+06 1.63760e+06 6396.87 14.79 1.72784 1.60303 43164 348864 -1 8812 16 2703 5592 1100371 345017 16.7238 16.7238 -1023.47 -16.7238 0 0 2.03272e+06 7940.32 0.12 0.37 0.48 -1 -1 0.12 0.123499 0.117943 138 202 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index c6d02a55f5a..8a9769fe6bb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 1.14 vpr 62.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64472 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.06 69 227 71 153 3 63.0 MiB 0.06 0.00 1.42251 -15.9524 -1.42251 1.42251 0.00 0.00015298 0.000138828 0.00249541 0.00229004 -1 -1 -1 -1 86 4.52632 45 2.36842 140 253 6063 2435 323364 161682 20103.2 804.128 19 1140 2762 -1 1.32969 1.32969 -16.56 -1.32969 0 0 0.00 -1 -1 63.0 MiB 0.12 0.0136734 0.0121602 63.0 MiB -1 0.01 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 1.13 vpr 62.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64404 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.06 69 227 71 153 3 62.9 MiB 0.07 0.00 1.42251 -15.9524 -1.42251 1.42251 0.00 0.000157491 0.000141647 0.00278966 0.00257008 -1 -1 -1 -1 86 4.52632 45 2.36842 140 253 6063 2435 323364 161682 20103.2 804.128 19 1140 2762 -1 1.32969 1.32969 -16.56 -1.32969 0 0 0.00 -1 -1 62.9 MiB 0.10 0.0124481 0.0108976 62.9 MiB -1 0.01 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.72 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64488 6 8 39 47 1 20 17 5 5 25 clb auto 24.6 MiB 0.06 69 227 71 153 3 63.0 MiB 0.07 0.00 1.42347 -15.9604 -1.42347 1.42347 0.00 0.000217166 0.000199351 0.00282597 0.00262228 -1 -1 -1 -1 -1 -1 -1 -1 723 1098 45498 29013 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.0 MiB 0.25 -1 -1 63.0 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.77 vpr 62.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64344 6 8 39 47 1 20 17 5 5 25 clb auto 24.4 MiB 0.08 69 227 71 153 3 62.8 MiB 0.05 0.00 1.42347 -15.9604 -1.42347 1.42347 0.00 0.000206522 0.000185386 0.00269457 0.0024909 -1 -1 -1 -1 142 7.47368 68 3.57895 723 1098 45498 29013 323364 161682 9037.03 361.481 -1 996 1634 -1 1.87665 1.87665 -21.7004 -1.87665 0 0 0.00 -1 -1 62.8 MiB 0.28 -1 -1 62.8 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.48 vpr 65.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66896 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000116029 0.000100823 0.0010942 0.00101432 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.3 MiB 0.01 0.00766251 0.00688033 65.3 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.51 vpr 65.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66796 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000165834 0.000146968 0.00119076 0.00110326 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.00909464 0.00816836 65.2 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.24 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000113726 9.7512e-05 0.00114825 0.00106423 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.3 MiB 0.03 -1 -1 65.3 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.24 vpr 65.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66624 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.1 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.00013832 0.000115541 0.000955845 0.00087775 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.1 MiB 0.03 -1 -1 65.1 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index 311f7681759..cb597e00427 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 4.21 vpr 57.70 MiB -1 -1 0.80 23328 6 0.19 -1 -1 33384 -1 -1 28 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59088 10 2 186 188 1 48 40 8 8 64 clb auto 17.8 MiB 0.19 230 1196 187 947 62 57.7 MiB 0.08 0.00 2.65254 -112.238 -2.65254 2.65254 0.00 0.000511628 0.000471787 0.00947363 0.00865334 -1 -1 -1 -1 214 4.75556 214 4.75556 166 391 15410 3128 80255.5 62421 276194. 4315.53 14 9480 40228 -1 2.5901 2.5901 -115.226 -2.5901 -0.0734 -0.0734 0.06 -1 -1 57.7 MiB 0.11 0.0294044 0.0261959 57.7 MiB -1 0.04 - k6_frac_N10_40nm.xml stereovision3.v common 3.65 vpr 59.24 MiB -1 -1 0.83 23296 5 0.20 -1 -1 33392 -1 -1 7 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60664 10 2 181 183 1 37 19 5 5 25 clb auto 19.7 MiB 0.25 118 444 83 324 37 59.2 MiB 0.10 0.00 2.09635 -87.6091 -2.09635 2.09635 0.00 0.000727323 0.000670846 0.0133214 0.0124002 -1 -1 -1 -1 93 2.73529 48 1.41176 48 64 1145 344 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97843 1.97843 -87.1605 -1.97843 0 0 0.02 -1 -1 59.2 MiB 0.05 0.0264495 0.0247146 59.2 MiB -1 0.01 + k4_N4_90nm.xml stereovision3.v common 2.77 vpr 60.00 MiB -1 -1 0.91 26856 6 0.21 -1 -1 36836 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61436 10 2 186 188 1 48 40 8 8 64 clb auto 20.5 MiB 0.04 230 992 145 785 62 60.0 MiB 0.03 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000447321 0.000382714 0.00843147 0.00745792 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.09 -1 -1 60.0 MiB 0.03 0.0220189 0.0194464 60.0 MiB -1 0.01 + k6_frac_N10_40nm.xml stereovision3.v common 2.04 vpr 61.65 MiB -1 -1 0.81 26884 5 0.16 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.07 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000403252 0.000354056 0.00494195 0.00440924 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.03 -1 -1 61.7 MiB 0.01 0.0168116 0.0156639 61.7 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt index 108c515e439..0fde75bd1ed 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 3.18 vpr 57.75 MiB -1 -1 0.67 23320 6 0.16 -1 -1 33560 -1 -1 28 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59132 10 2 186 188 1 48 40 8 8 64 clb auto 17.9 MiB 0.03 230 1196 187 947 62 57.7 MiB 0.04 0.00 2.65254 -112.238 -2.65254 2.65254 0.00 0.00041108 0.00037781 0.00872984 0.0079342 -1 -1 -1 -1 214 4.75556 214 4.75556 166 391 15410 3128 80255.5 62421 276194. 4315.53 14 9480 40228 -1 2.5901 2.5901 -115.226 -2.5901 -0.0734 -0.0734 0.05 -1 -1 57.7 MiB 0.05 0.025576 0.0229291 57.7 MiB -1 0.05 - k6_frac_N10_40nm.xml stereovision3.v common 3.35 vpr 59.19 MiB -1 -1 0.94 23284 5 0.18 -1 -1 33436 -1 -1 7 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60608 10 2 181 183 1 37 19 5 5 25 clb auto 19.7 MiB 0.17 118 444 83 324 37 59.2 MiB 0.12 0.00 2.09635 -87.6091 -2.09635 2.09635 0.00 0.000568296 0.000529924 0.0148823 0.0140252 -1 -1 -1 -1 93 2.73529 48 1.41176 48 64 1145 344 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97843 1.97843 -87.1605 -1.97843 0 0 0.01 -1 -1 59.2 MiB 0.07 0.0262726 0.0248022 59.2 MiB -1 0.02 + k4_N4_90nm.xml stereovision3.v common 2.09 vpr 60.07 MiB -1 -1 0.81 26980 6 0.15 -1 -1 36756 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61512 10 2 186 188 1 48 40 8 8 64 clb auto 20.6 MiB 0.03 230 992 145 785 62 60.1 MiB 0.02 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000430706 0.00037483 0.00785446 0.00688801 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.08 -1 -1 60.1 MiB 0.02 0.0211284 0.0188358 60.1 MiB -1 0.01 + k6_frac_N10_40nm.xml stereovision3.v common 1.94 vpr 61.65 MiB -1 -1 0.77 26880 5 0.18 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.1 MiB 0.06 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000420371 0.000366917 0.00494209 0.00453968 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.02 -1 -1 61.7 MiB 0.01 0.0164382 0.0153894 61.7 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt index 9a1ccef4106..9a8744d436c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 35.89 vpr 976.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999840 10 10 168 178 1 68 30 11 8 88 io auto 953.2 MiB 0.64 354 536 67 434 35 976.4 MiB 0.09 0.00 6.57169 -72.0462 -6.57169 6.57169 0.00 0.000503078 0.000459561 0.0104853 0.00985191 -1 -1 -1 -1 586 8.74627 178 2.65672 259 971 58705 26468 0 0 194014. 2204.70 13 11730 32605 -1 6.82307 6.82307 -73.1617 -6.82307 0 0 0.07 -1 -1 976.4 MiB 0.07 0.0420166 0.0389946 976.4 MiB -1 0.08 + stratixiv_arch.timing.xml styr.blif common 32.55 vpr 978.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001924 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.50 371 490 69 397 24 978.4 MiB 0.08 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000745164 0.00064564 0.0121362 0.0109717 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.4 MiB 0.14 0.0524157 0.0489871 978.4 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt index a3ceed7c14d..6c5af69e6a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt @@ -24,4 +24,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --read_vpr_constraints ../../../../floor_plan.xml:../../../../route_constraint.xml --write_vpr_constraints vpr_constraints.xml --clock_modeling ideal +script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --read_vpr_constraints ../../../../vpr_constraints.xml --write_vpr_constraints vpr_constraints.xml --clock_modeling ideal diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml deleted file mode 100644 index 861adf40966..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml deleted file mode 100644 index ca3d794706b..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/vpr_constraints.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/vpr_constraints.xml new file mode 100644 index 00000000000..d9bc4ac9e3f --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/vpr_constraints.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 0301285b4ba..783b9bb6553 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -1,6 +1,16 @@ regression_tests/vtr_reg_strong/basic_ap regression_tests/vtr_reg_strong/strong_ap/mcnc regression_tests/vtr_reg_strong/strong_ap/vtr_chain +regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer +regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer +regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer +regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer +regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer +regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer +regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks +regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering +regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver +regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver regression_tests/vtr_reg_strong/strong_absorb_buffers regression_tests/vtr_reg_strong/strong_analysis_only regression_tests/vtr_reg_strong/strong_analytic_placer @@ -33,6 +43,7 @@ regression_tests/vtr_reg_strong/strong_equivalent_sites regression_tests/vtr_reg_strong/strong_fc_abs regression_tests/vtr_reg_strong/strong_fix_clusters regression_tests/vtr_reg_strong/strong_fix_pins_random +regression_tests/vtr_reg_strong/strong_flat_placement/read_write regression_tests/vtr_reg_strong/strong_flyover_wires regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch regression_tests/vtr_reg_strong/strong_fracturable_luts @@ -97,3 +108,4 @@ regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router regression_tests/vtr_reg_strong/strong_routing_constraints regression_tests/vtr_reg_strong/strong_vib +regression_tests/vtr_reg_strong/strong_3d diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt index a5aa1efe307..7b5437463d7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 6.81 vpr 74.85 MiB 0.09 7796 -1 -1 1 0.08 -1 -1 32232 -1 -1 12 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76648 130 40 596 562 1 356 185 14 14 196 dsp_top auto 35.9 MiB 0.18 1873 36479 12233 19905 4341 74.9 MiB 0.21 0.00 5.12303 -652.04 -5.12303 5.12303 0.82 0.00140021 0.00130659 0.105265 0.098455 -1 -1 -1 -1 64 3939 11 4.93594e+06 1.0962e+06 976140. 4980.31 2.47 0.398489 0.366481 31408 195022 -1 3669 7 846 891 204483 79938 4.57723 4.57723 -704.235 -4.57723 0 0 1.23909e+06 6321.90 0.32 0.09 0.28 -1 -1 0.32 0.0391394 0.037187 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 5.51 vpr 77.59 MiB 0.04 8576 -1 -1 1 0.07 -1 -1 35240 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79456 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.13 1890 35427 11493 18934 5000 77.6 MiB 0.27 0.00 5.12303 -647.058 -5.12303 5.12303 0.48 0.00206617 0.00189672 0.14394 0.133207 -1 -1 -1 -1 64 3873 16 4.93594e+06 1.0962e+06 976140. 4980.31 2.20 0.636996 0.595296 31408 195022 -1 3500 9 851 887 209984 82943 4.57723 4.57723 -694.457 -4.57723 0 0 1.23909e+06 6321.90 0.09 0.15 0.39 -1 -1 0.09 0.0903946 0.0866517 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt index 314721e6341..23cf7b0b85f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 17.10 vpr 78.69 MiB 0.17 10856 -1 -1 1 0.12 -1 -1 34140 -1 -1 23 130 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 80580 130 40 1203 1030 1 586 196 14 14 196 dsp_top auto 38.7 MiB 0.49 2582 41733 12251 23272 6210 78.7 MiB 0.33 0.01 6.49756 -686.499 -6.49756 6.49756 0.76 0.00167814 0.00153244 0.158674 0.146165 -1 -1 -1 -1 108 5040 43 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 11.29 1.3413 1.19961 36552 325092 -1 4509 22 2486 2554 274402 92406 6.62048 6.62048 -743.865 -6.62048 0 0 1.93951e+06 9895.46 0.56 0.19 0.69 -1 -1 0.56 0.107178 0.0988592 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 14.85 vpr 81.40 MiB 0.10 11392 -1 -1 1 0.12 -1 -1 37676 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83352 130 40 1203 1030 1 586 196 14 14 196 dsp_top auto 41.3 MiB 0.63 2691 46285 14724 25599 5962 81.4 MiB 0.45 0.01 6.58999 -703.566 -6.58999 6.58999 0.48 0.00220042 0.00200207 0.214554 0.193316 -1 -1 -1 -1 108 5210 35 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 10.07 1.93637 1.74105 36552 325092 -1 4641 23 2669 2746 326887 113256 6.77766 6.77766 -770.287 -6.77766 0 0 1.93951e+06 9895.46 0.12 0.27 0.65 -1 -1 0.12 0.138318 0.125698 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt index 44b0c3fb49b..235e1da0107 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.85 vpr 70.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71840 130 150 1169 1319 1 886 363 12 12 144 clb auto 30.0 MiB 1.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00639293 0.00599457 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.78 vpr 69.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71156 130 150 1216 1366 1 933 370 12 12 144 clb auto 29.8 MiB 1.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0055812 0.00507678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.88 vpr 72.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74068 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.4 MiB 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00708147 0.00640458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 2.22 vpr 72.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73804 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.3 MiB 1.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00920908 0.00830291 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt index 9750f0dd17a..d3c7d61af84 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.31 vpr 64.46 MiB 0.07 9980 -1 -1 4 0.20 -1 -1 33464 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66008 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.10 421 2049 269 1715 65 64.5 MiB 0.04 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000669291 0.000596999 0.0160309 0.0145218 -1 -1 -1 -1 424 4.46316 163 1.71579 617 1399 45810 10033 1.07788e+06 1.02399e+06 207176. 4228.08 16 4440 29880 -1 2.36464 2.27781 -179.43 -2.36464 0 0 0.04 -1 -1 64.5 MiB 0.05 0.0483486 0.0432361 64.5 MiB -1 0.04 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.59 vpr 66.95 MiB 0.07 10224 -1 -1 5 0.19 -1 -1 33224 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68560 11 30 313 321 2 115 55 7 7 49 clb auto 27.2 MiB 0.33 466 2759 556 2108 95 67.0 MiB 0.05 0.00 2.67362 -172.647 -2.67362 2.30794 0.00 0.000721207 0.000645031 0.0268996 0.0245416 -1 -1 -1 -1 574 5.26606 231 2.11927 216 452 11450 3638 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 2.71877 2.35385 -178.475 -2.71877 0 0 0.04 -1 -1 67.0 MiB 0.03 0.0557218 0.0513892 67.0 MiB -1 0.04 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.36 vpr 66.46 MiB 0.08 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68060 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 425 2283 406 1804 73 66.5 MiB 0.05 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000768694 0.000638603 0.0252644 0.022728 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.5 MiB 0.08 0.0775573 0.0705898 66.5 MiB -1 0.01 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.76 vpr 69.14 MiB 0.09 10368 -1 -1 5 0.19 -1 -1 36576 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70804 11 30 313 321 2 115 55 7 7 49 clb auto 29.7 MiB 0.40 448 1927 352 1502 73 69.1 MiB 0.07 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000863635 0.000740182 0.0221309 0.0195205 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.05 -1 -1 69.1 MiB 0.06 0.0568064 0.051944 69.1 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt index 297d9cc2e7d..df63a32e433 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.34 vpr 65.27 MiB 0.06 9400 -1 -1 3 0.30 -1 -1 34668 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66836 99 130 363 493 1 251 298 12 12 144 clb auto 26.0 MiB 0.14 973 1293 313 844 136 65.3 MiB 0.07 0.00 2.2425 -218.261 -2.2425 2.2425 0.39 0.000963196 0.000901211 0.00562254 0.00542751 -1 -1 -1 -1 36 1866 35 5.66058e+06 4.21279e+06 305235. 2119.69 1.87 0.362594 0.328428 12238 58442 -1 1566 9 567 738 58151 19831 2.59207 2.59207 -232.729 -2.59207 0 0 378970. 2631.74 0.12 0.05 0.07 -1 -1 0.12 0.0271537 0.0253871 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.27 vpr 67.81 MiB 0.06 9984 -1 -1 3 0.40 -1 -1 39908 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.8 MiB 0.14 1080 1293 313 846 134 67.8 MiB 0.06 0.00 2.45187 -223.196 -2.45187 2.45187 0.31 0.000607122 0.000549979 0.00491114 0.00472929 -1 -1 -1 -1 34 2076 26 5.66058e+06 4.21279e+06 293002. 2034.74 1.92 0.386002 0.351306 12094 55633 -1 1662 10 540 720 43948 13958 2.71514 2.71514 -233.572 -2.71514 0 0 360780. 2505.42 0.02 0.06 0.08 -1 -1 0.02 0.0335019 0.0302667 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt index 75b4dc8cff1..c57ad9bdb40 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 2.49 vpr 58.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59988 10 10 253 263 1 165 89 11 11 121 clb auto 18.8 MiB 0.05 1298 4445 695 3556 194 58.6 MiB 0.05 0.00 5.53812 -72.6437 -5.53812 5.53812 0.17 0.000586889 0.000523181 0.0184266 0.016854 -1 -1 -1 -1 14 2029 36 2.43e+06 2.07e+06 -1 -1 1.20 0.252134 0.219147 3402 27531 -1 1944 19 1218 4569 249188 30978 7.47374 7.47374 -94.8537 -7.47374 0 0 -1 -1 0.06 0.11 0.02 -1 -1 0.06 0.0414153 0.0362194 - k4_n4_v7_longline_bidir.xml styr.blif common 2.81 vpr 58.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59496 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.06 1243 3851 530 3175 146 58.1 MiB 0.04 0.00 4.42129 -53.6285 -4.42129 4.42129 0.23 0.000610037 0.000548673 0.0158349 0.0144995 -1 -1 -1 -1 19 2381 26 2.43e+06 2.07e+06 -1 -1 1.40 0.224268 0.192635 3282 34431 -1 2331 24 1499 5264 384444 46394 8.40637 8.40637 -105.933 -8.40637 0 0 -1 -1 0.07 0.11 0.02 -1 -1 0.07 0.0377239 0.0326406 - k4_n4_v7_l1_bidir.xml styr.blif common 4.06 vpr 58.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60052 10 10 253 263 1 165 89 11 11 121 clb auto 18.9 MiB 0.06 1249 6821 1452 5028 341 58.6 MiB 0.06 0.00 6.30077 -80.949 -6.30077 6.30077 0.22 0.000518755 0.000463783 0.0228285 0.0206741 -1 -1 -1 -1 10 1483 31 2.43e+06 2.07e+06 -1 -1 2.61 0.268076 0.234279 4482 22551 -1 1280 20 1321 4798 303501 58064 7.52318 7.52318 -89.7629 -7.52318 0 0 -1 -1 0.04 0.12 0.02 -1 -1 0.04 0.037522 0.0333295 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.10 vpr 58.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59416 10 10 253 263 1 165 89 11 11 121 clb auto 18.8 MiB 0.05 1252 4247 601 3492 154 58.0 MiB 0.05 0.00 3.38007 -43.5291 -3.38007 3.38007 0.18 0.00064054 0.000577227 0.0176541 0.0161473 -1 -1 -1 -1 14 2047 30 2.43e+06 2.07e+06 -1 -1 1.68 0.248457 0.216641 3402 27531 -1 2099 29 1484 5383 889715 156716 22.7353 22.7353 -261.092 -22.7353 0 0 -1 -1 0.05 0.25 0.02 -1 -1 0.05 0.0493955 0.0438566 + k4_n4_v7_bidir.xml styr.blif common 1.89 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.09 0.000707997 0.000614185 0.0204147 0.0180597 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.97 0.236366 0.209157 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.10 0.02 -1 -1 0.01 0.0335803 0.0304927 + k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 60.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61816 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.05 1219 4247 600 3483 164 60.4 MiB 0.05 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000681666 0.000592315 0.0189188 0.016758 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.80 0.256847 0.227018 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.10 0.03 -1 -1 0.02 0.0370258 0.033411 + k4_n4_v7_l1_bidir.xml styr.blif common 2.35 vpr 61.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62632 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1285 7613 1616 5547 450 61.2 MiB 0.12 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.000675324 0.000585254 0.0347554 0.0308708 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.17 0.183607 0.16336 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.13 0.02 -1 -1 0.01 0.0396264 0.0357171 + k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.49 vpr 60.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61772 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.05 1234 4643 666 3821 156 60.3 MiB 0.09 0.01 3.51175 -43.7413 -3.51175 3.51175 0.09 0.000766831 0.000671887 0.0247522 0.0222268 -1 -1 -1 -1 14 2053 42 2.43e+06 2.07e+06 -1 -1 2.23 0.282741 0.249953 3402 27531 -1 1991 28 1438 5059 778762 132220 26.9853 26.9853 -248.248 -26.9853 0 0 -1 -1 0.01 0.37 0.03 -1 -1 0.01 0.0480187 0.0429407 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt index 84fc98735c4..0bd2ba5a636 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.95 vpr 64.38 MiB 0.06 10036 -1 -1 4 0.21 -1 -1 33304 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65924 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.09 439 1932 239 1639 54 64.4 MiB 0.03 0.00 2.45489 -180.196 -2.45489 2.33213 0.07 0.000611032 0.000541625 0.0144591 0.0130681 -1 -1 -1 -1 20 684 34 1.07788e+06 1.02399e+06 49980.0 1020.00 0.25 0.116805 0.09949 2664 9102 -1 585 25 992 2191 68660 23567 2.62928 2.46785 -187.223 -2.62928 0 0 65453.8 1335.79 0.02 0.07 0.01 -1 -1 0.02 0.0375678 0.0325723 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.27 vpr 64.50 MiB 0.06 9904 -1 -1 4 0.20 -1 -1 33384 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66052 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 439 1932 239 1639 54 64.5 MiB 0.04 0.00 2.45489 -180.196 -2.45489 2.33213 0.08 0.000680402 0.00060982 0.017209 0.0157151 -1 -1 -1 -1 20 684 34 1.07788e+06 1.02399e+06 49980.0 1020.00 0.55 0.238978 0.201081 2664 9102 -1 585 25 992 2191 68660 23567 2.62928 2.46785 -187.223 -2.62928 0 0 65453.8 1335.79 0.02 0.07 0.01 -1 -1 0.02 0.0406365 0.0353306 + k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.92 vpr 66.34 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36540 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000749649 0.00064239 0.0161237 0.0140852 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.28 0.147245 0.127953 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.08 0.01 -1 -1 0.00 0.047308 0.0404063 + k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.40 vpr 66.13 MiB 0.07 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67716 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.08 427 1815 293 1474 48 66.1 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000744837 0.000636456 0.0185703 0.0149662 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.64 0.298818 0.25277 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.10 0.01 -1 -1 0.00 0.0500747 0.044978 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt index 46602a07176..7d75ebf7e22 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.95 vpr 65.09 MiB 0.05 9384 -1 -1 3 0.35 -1 -1 34600 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66648 99 130 363 493 1 255 305 13 13 169 clb auto 25.3 MiB 0.09 908 74177 24418 37403 12356 65.1 MiB 0.21 0.00 2.24932 -227.778 -2.24932 2.24932 0.43 0.000870718 0.000814627 0.0677126 0.0632932 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.19 0.456283 0.413595 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.14 0.10 0.06 -1 -1 0.14 0.055174 0.0502939 - k6_N10_mem32K_40nm.xml diffeq1.v common 10.90 vpr 68.98 MiB 0.04 9404 -1 -1 15 0.48 -1 -1 34660 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70636 162 96 999 932 1 661 323 16 16 256 mult_36 auto 28.8 MiB 0.31 5495 75599 21207 48608 5784 69.0 MiB 0.55 0.01 21.6615 -1879.46 -21.6615 21.6615 0.70 0.00319094 0.00302093 0.229143 0.215114 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 6.02 1.39802 1.29282 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.31 0.42 0.14 -1 -1 0.31 0.180893 0.168332 - k6_N10_mem32K_40nm.xml single_wire.v common 0.55 vpr 63.05 MiB 0.01 6576 -1 -1 1 0.02 -1 -1 30004 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64568 1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 2 3 0 3 0 63.1 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1357e-05 6.922e-06 7.8063e-05 5.3338e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.0015524 0.00147403 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00228467 0.00224801 - k6_N10_mem32K_40nm.xml single_ff.v common 0.54 vpr 62.95 MiB 0.01 6420 -1 -1 1 0.02 -1 -1 30176 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64464 2 1 3 4 1 3 4 3 3 9 -1 auto 24.2 MiB 0.00 6 9 5 1 3 63.0 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.4537e-05 1.0143e-05 0.00010139 7.6283e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00162892 0.00154661 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00170661 0.00165742 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 9.72 vpr 65.00 MiB 0.06 9380 -1 -1 3 0.32 -1 -1 34636 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66556 99 130 363 493 1 255 305 19 19 361 o auto 25.3 MiB 0.09 1017 84437 21849 44018 18570 65.0 MiB 0.27 0.00 2.33845 -237.624 -2.33845 2.33845 2.83 0.00101195 0.000938816 0.0893341 0.0836814 -1 -1 -1 -1 36 1395 26 1.79173e+07 4.59005e+06 833707. 2309.44 3.44 0.417472 0.379057 24998 161561 -1 1299 23 891 1465 81711 22668 2.61943 2.61943 -244.023 -2.61943 0 0 1.02328e+06 2834.56 0.39 0.08 0.14 -1 -1 0.39 0.042041 0.0384715 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 24.30 vpr 83.81 MiB 0.04 9376 -1 -1 15 0.46 -1 -1 34644 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 85820 162 96 999 932 1 661 323 24 24 576 i auto 28.7 MiB 0.31 7217 101060 28985 60644 11431 83.8 MiB 0.72 0.01 21.9602 -1888.96 -21.9602 21.9602 4.32 0.00297924 0.00279786 0.307712 0.28877 -1 -1 -1 -1 32 14521 46 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 14.07 1.70494 1.57192 39974 242477 -1 11428 25 4677 10335 1474881 391876 23.1722 23.1722 -1992.17 -23.1722 0 0 1.54255e+06 2678.04 0.44 0.51 0.21 -1 -1 0.44 0.195655 0.181464 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.58 vpr 62.93 MiB 0.01 6452 -1 -1 1 0.02 -1 -1 30116 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64440 1 1 1 2 0 1 2 4 4 16 i auto 24.2 MiB 0.00 3 3 0 0 3 62.9 MiB 0.00 0.00 0.280667 -0.280667 -0.280667 nan 0.01 9.703e-06 5.942e-06 7.6566e-05 5.0557e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.01 0.00148096 0.00139624 324 600 -1 2 1 1 1 16 6 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.00141364 0.00138107 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.64 vpr 62.77 MiB 0.01 6452 -1 -1 1 0.04 -1 -1 29928 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64280 2 1 3 4 1 3 4 4 4 16 i auto 24.0 MiB 0.00 7 9 0 2 7 62.8 MiB 0.00 0.00 0.647256 -1.07419 -0.647256 0.647256 0.01 1.9097e-05 1.4095e-05 0.000118864 8.987e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00164593 0.00153585 340 760 -1 3 2 3 3 71 25 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00152593 0.00147741 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.32 vpr 67.44 MiB 0.07 9856 -1 -1 3 0.36 -1 -1 39552 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69060 99 130 363 493 1 255 305 13 13 169 clb auto 27.9 MiB 0.11 817 73151 23083 37131 12937 67.4 MiB 0.30 0.01 2.36834 -235.63 -2.36834 2.36834 0.29 0.00233393 0.00223993 0.0738859 0.066584 -1 -1 -1 -1 32 1352 17 6.63067e+06 4.59005e+06 323148. 1912.12 0.52 0.196726 0.178694 11612 59521 -1 1138 16 719 1086 65347 22389 2.48507 2.48507 -238.178 -2.48507 0 0 396943. 2348.77 0.02 0.13 0.12 -1 -1 0.02 0.0517727 0.0472555 + k6_N10_mem32K_40nm.xml diffeq1.v common 10.12 vpr 70.60 MiB 0.03 9856 -1 -1 15 0.44 -1 -1 38380 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72292 162 96 999 932 1 661 323 16 16 256 mult_36 auto 31.3 MiB 0.38 5531 95525 26953 60139 8433 70.6 MiB 0.91 0.01 21.9361 -1891.35 -21.9361 21.9361 0.47 0.00396915 0.00366377 0.403824 0.374905 -1 -1 -1 -1 44 11294 43 1.21132e+07 5.21364e+06 665287. 2598.78 5.71 1.78116 1.66467 20656 131250 -1 8771 24 4066 8799 1047369 299882 22.5944 22.5944 -1935.68 -22.5944 0 0 864808. 3378.16 0.04 0.50 0.16 -1 -1 0.04 0.234899 0.221057 + k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB 0.01 6912 -1 -1 1 0.02 -1 -1 32916 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0231e-05 6.013e-06 7.2755e-05 4.8573e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00153872 0.00147005 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109157 0.00106485 + k6_N10_mem32K_40nm.xml single_ff.v common 0.49 vpr 65.16 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33280 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 5 1 3 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5008e-05 1.0331e-05 0.000105161 7.8059e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0016194 0.0015365 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00112886 0.00109032 + k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.85 vpr 67.48 MiB 0.06 9856 -1 -1 3 0.36 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69100 99 130 363 493 1 255 305 19 19 361 o auto 27.9 MiB 0.10 1043 75203 18688 40447 16068 67.5 MiB 0.27 0.00 2.5827 -243.865 -2.5827 2.5827 1.92 0.000939884 0.00084584 0.0725048 0.0652395 -1 -1 -1 -1 36 1432 20 1.79173e+07 4.59005e+06 833707. 2309.44 1.36 0.302543 0.27272 24998 161561 -1 1342 23 802 1298 88966 26229 2.93129 2.93129 -249.701 -2.93129 0 0 1.02328e+06 2834.56 0.07 0.10 0.15 -1 -1 0.07 0.0554021 0.0511266 + k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 12.40 vpr 79.29 MiB 0.04 9856 -1 -1 15 0.45 -1 -1 38032 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81188 162 96 999 932 1 661 323 24 24 576 i auto 31.0 MiB 0.28 7114 95525 25526 57948 12051 79.3 MiB 0.94 0.01 21.4854 -1914.4 -21.4854 21.4854 3.35 0.00392701 0.00363416 0.415599 0.386608 -1 -1 -1 -1 32 12804 30 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 3.94 1.18592 1.11276 39974 242477 -1 10817 26 4455 9936 1378660 349639 22.5193 22.5193 -2054.22 -22.5193 0 0 1.54255e+06 2678.04 0.12 0.65 0.37 -1 -1 0.12 0.246186 0.231211 + k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.47 vpr 65.28 MiB 0.02 6784 -1 -1 1 0.02 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66848 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1306e-05 5.604e-06 7.2139e-05 4.6493e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00155951 0.00148904 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.0014785 0.00144447 + k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.49 vpr 65.16 MiB 0.02 7040 -1 -1 1 0.02 -1 -1 33288 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 4 4 16 i auto 26.9 MiB 0.00 7 9 0 2 7 65.2 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.6222e-05 1.0832e-05 0.00010458 7.8535e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00166008 0.00157112 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00159511 0.00154443 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt index b913a54f802..a4f4578b4e4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.03 vpr 64.66 MiB 0.05 9936 -1 -1 4 0.20 -1 -1 33284 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66212 11 30 262 292 2 99 60 7 7 49 clb auto 24.9 MiB 0.09 440 2400 452 1846 102 64.7 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 660 35 1.07788e+06 1.02399e+06 45686.6 932.380 0.48 0.165713 0.138611 2616 8308 -1 541 24 785 1721 49987 17392 2.55392 2.37233 -184.833 -2.55392 0 0 59124.6 1206.62 0.01 0.07 0.01 -1 -1 0.01 0.0397954 0.0348173 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.22 vpr 66.21 MiB 0.06 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67796 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 485 3687 781 2795 111 66.2 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 734 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.65 0.239065 0.204044 2616 8308 -1 583 23 761 1801 50764 16568 2.52485 2.36559 -186.102 -2.52485 0 0 59124.6 1206.62 0.00 0.07 0.01 -1 -1 0.00 0.0486043 0.0430292 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt index eb38f9839e9..d3b62c629ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 6.55 vpr 56.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57924 6 7 19 26 0 19 26 3 3 9 -1 auto 17.8 MiB 0.01 51 216 43 63 110 56.6 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 5.46 4.4866e-05 3.8779e-05 0.000407849 0.000352025 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.09 0.0024538 0.00222966 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.04 -1 -1 0.00 0.00174299 0.00165115 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 7.53 vpr 56.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58092 6 7 19 26 0 19 26 3 3 9 -1 auto 18.1 MiB 0.00 51 216 43 63 110 56.7 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 6.42 3.9294e-05 3.2838e-05 0.000360177 0.000299223 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.11 0.00240249 0.00218766 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.04 -1 -1 0.00 0.00179459 0.00169524 - sub_tiles.xml sub_tiles.blif common_--check_route_off 6.86 vpr 56.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57856 6 7 19 26 0 19 26 3 3 9 -1 auto 17.8 MiB 0.00 51 216 43 63 110 56.5 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 5.82 4.4091e-05 3.8299e-05 0.000449038 0.000394449 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.08 0.00230139 0.00207606 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.04 -1 -1 0.00 0.00164487 0.00155669 + sub_tiles.xml sub_tiles.blif common_--check_route_full 14.36 vpr 58.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60212 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.8 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.10 4.6187e-05 3.8396e-05 0.000395937 0.000323618 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00202221 0.00179313 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00173217 0.0016394 + sub_tiles.xml sub_tiles.blif common_--check_route_quick 16.94 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.28 4.6086e-05 3.7994e-05 0.000373556 0.000302701 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00235088 0.00212378 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00221042 0.00197359 + sub_tiles.xml sub_tiles.blif common_--check_route_off 16.20 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60476 6 7 19 26 0 19 26 3 3 9 -1 auto 20.7 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 14.72 4.2295e-05 3.5105e-05 0.000363474 0.000296118 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00229484 0.00207762 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00174454 0.00165562 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index 573110a1f9d..7b6b29fbf31 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.67 vpr 63.84 MiB 0.01 6676 -1 -1 1 0.03 -1 -1 30204 -1 -1 3 9 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65376 9 8 71 66 1 35 20 5 5 25 clb auto 24.5 MiB 0.59 106 155 56 98 1 63.8 MiB 0.01 0.00 2.68643 -28.4691 -2.68643 2.68643 0.03 0.000140881 0.000128293 0.00202868 0.00191784 -1 -1 -1 -1 24 237 22 151211 75605.7 33517.4 1340.70 0.18 0.041091 0.034289 1884 5578 -1 191 17 213 274 8835 4764 3.58807 3.58807 -39.9558 -3.58807 0 0 43252.0 1730.08 0.00 0.02 0.01 -1 -1 0.00 0.00832021 0.00744946 14 17 16 6 0 0 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.57 vpr 65.18 MiB 0.01 6688 -1 -1 1 0.04 -1 -1 30640 -1 -1 8 19 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66748 19 18 299 240 1 146 45 6 6 36 clb auto 25.6 MiB 4.69 492 845 209 626 10 65.2 MiB 0.02 0.00 4.85986 -99.0252 -4.85986 4.85986 0.05 0.000469766 0.000432273 0.00954877 0.00903161 -1 -1 -1 -1 50 1141 29 403230 201615 107229. 2978.57 0.79 0.20538 0.176607 3946 19047 -1 909 23 1044 1578 59654 24287 5.61482 5.61482 -122.009 -5.61482 0 0 134937. 3748.26 0.02 0.06 0.02 -1 -1 0.02 0.032608 0.0295156 62 82 85 13 0 0 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.50 vpr 66.18 MiB 0.01 6912 -1 -1 1 0.03 -1 -1 33524 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67768 9 8 71 66 1 35 20 5 5 25 clb auto 27.2 MiB 0.61 102 641 211 420 10 66.2 MiB 0.01 0.00 2.52843 -27.3721 -2.52843 2.52843 0.02 0.000162932 0.000142933 0.00487777 0.00439017 -1 -1 -1 -1 32 152 12 151211 75605.7 43252.0 1730.08 0.15 0.05219 0.0443549 2004 6761 -1 170 13 131 173 5906 3259 2.68643 2.68643 -34.5837 -2.68643 0 0 52324.5 2092.98 0.00 0.01 0.01 -1 -1 0.00 0.00766663 0.00704697 14 17 16 6 0 0 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.42 vpr 67.07 MiB 0.01 6912 -1 -1 1 0.04 -1 -1 33628 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 19 18 299 240 1 146 45 6 6 36 clb auto 27.6 MiB 4.94 477 2365 468 1860 37 67.1 MiB 0.04 0.00 4.92757 -99.6523 -4.92757 4.92757 0.05 0.000316619 0.0002807 0.0196432 0.0179661 -1 -1 -1 -1 54 1052 25 403230 201615 113905. 3164.04 0.53 0.17427 0.152991 4050 20995 -1 792 24 850 1349 48852 19559 4.89358 4.89358 -108.576 -4.89358 0 0 146644. 4073.44 0.00 0.05 0.03 -1 -1 0.00 0.0285954 0.0259387 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt index bd8837584d4..82e16e68c58 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.38 vpr 57.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58828 1 4 28 32 2 10 9 4 4 16 clb auto 18.5 MiB 0.01 21 27 11 8 8 57.4 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.9608e-05 6.1171e-05 0.000528542 0.000484521 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.03 0.00817962 0.0068183 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00303766 0.0027903 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.40 vpr 57.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58924 1 4 28 32 2 10 9 4 4 16 clb auto 18.6 MiB 0.01 21 27 11 8 8 57.5 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.7493e-05 5.9709e-05 0.00053006 0.00048841 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.03 0.00837217 0.00702901 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00268284 0.00246934 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.45 vpr 57.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58868 1 4 28 32 2 10 9 4 4 16 clb auto 18.4 MiB 0.01 21 27 11 8 8 57.5 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.8738e-05 6.0915e-05 0.000598804 0.000552999 -1 -1 -1 -1 8 12 5 72000 72000 5593.62 349.601 0.03 0.00819817 0.00689289 672 1128 -1 13 8 23 23 458 156 2.39017 2.39017 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00319689 0.00291899 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.35 vpr 59.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61244 1 4 28 32 2 10 9 4 4 16 clb auto 21.2 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9876e-05 6.8917e-05 0.000564474 0.000511898 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00933145 0.00790294 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0020437 0.00190467 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.33 vpr 60.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61444 1 4 28 32 2 10 9 4 4 16 clb auto 21.5 MiB 0.01 21 27 10 10 7 60.0 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 9.3379e-05 8.2596e-05 0.000566541 0.000512464 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00867291 0.00731794 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00253268 0.00233063 + timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.35 vpr 59.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61264 1 4 28 32 2 10 9 4 4 16 clb auto 21.4 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.8562e-05 6.7163e-05 0.000561289 0.000507136 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00963983 0.0081025 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00296634 0.00273132 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt index c24f6849f4e..17671e26cfa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.46 vpr 57.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58704 2 2 22 24 2 4 6 4 4 16 clb auto 18.4 MiB 0.01 8 15 5 7 3 57.3 MiB 0.00 0.00 1.297 0 0 1.297 0.01 5.2494e-05 4.4634e-05 0.000448571 0.000405419 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00281216 0.00261739 660 1032 -1 15 4 8 8 614 487 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00226716 0.00212992 + timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.35 vpr 59.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61088 2 2 22 24 2 4 6 4 4 16 clb auto 21.2 MiB 0.01 8 15 5 7 3 59.7 MiB 0.00 0.00 1.297 0 0 1.297 0.01 6.7393e-05 5.6956e-05 0.000402551 0.000351966 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00291274 0.00268287 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00264613 0.00228889 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt index 82ec46d8b99..55f3e1dd3ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.66039 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt index cfd2d545cc8..c54c9279c53 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.41 vpr 57.28 MiB 0.00 6388 -1 -1 1 0.03 -1 -1 29960 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58652 2 1 3 4 1 3 4 3 3 9 -1 auto 18.6 MiB 0.00 6 9 3 5 1 57.3 MiB 0.04 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 2.1796e-05 1.6522e-05 0.000193754 0.00015861 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00168667 0.00157156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.39 vpr 57.19 MiB 0.00 6340 -1 -1 1 0.03 -1 -1 29884 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58560 2 1 3 4 1 3 4 3 3 9 -1 auto 18.5 MiB 0.00 9 9 3 3 3 57.2 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.7329e-05 1.1723e-05 0.000120696 9.1803e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.00149934 0.00140654 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 5.17 vpr 59.21 MiB 0.36 59164 -1 -1 2 1.59 -1 -1 50532 -1 -1 155 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60628 5 156 191 347 1 163 316 15 15 225 clb auto 19.6 MiB 0.04 29 84166 60542 3208 20416 59.2 MiB 0.13 0.00 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000406843 0.000383604 0.0325033 0.0306122 -1 -1 -1 -1 -1 40 7 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0416902 0.0390742 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 5.29 vpr 59.23 MiB 0.44 59264 -1 -1 2 1.66 -1 -1 50664 -1 -1 155 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60656 5 156 191 347 1 163 316 15 15 225 clb auto 19.6 MiB 0.04 36 74491 53339 3165 17987 59.2 MiB 0.11 0.00 1.49775 -14.6149 -1.49775 1.49775 0.00 0.000376659 0.000354057 0.027722 0.0260055 -1 -1 -1 -1 -1 54 6 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0361212 0.0337603 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.34 vpr 62.88 MiB 0.01 6524 -1 -1 1 0.03 -1 -1 30032 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64384 2 1 3 4 1 3 4 3 3 9 -1 auto 24.1 MiB 0.00 6 9 3 5 1 62.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.8462e-05 1.3116e-05 0.000143184 0.000107932 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00154548 0.00142994 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.38 vpr 62.88 MiB 0.01 6520 -1 -1 1 0.02 -1 -1 29980 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64388 2 1 3 4 1 3 4 3 3 9 -1 auto 24.1 MiB 0.00 9 9 3 3 3 62.9 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.7389e-05 1.2439e-05 0.000110474 8.1262e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00162603 0.00153736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.85 vpr 69.68 MiB 0.15 16496 -1 -1 2 0.15 -1 -1 33692 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71352 311 156 972 1128 1 953 525 28 28 784 memory auto 30.0 MiB 0.53 9455 210108 77830 122308 9970 69.7 MiB 1.15 0.02 3.97422 -4336.45 -3.97422 3.97422 0.00 0.00487926 0.00437885 0.503553 0.447369 -1 -1 -1 -1 -1 13425 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.40 0.699755 0.628908 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 5.65 vpr 69.53 MiB 0.19 16512 -1 -1 2 0.16 -1 -1 33768 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 71200 311 156 972 1128 1 953 525 28 28 784 memory auto 29.9 MiB 0.55 9870 203757 68308 124561 10888 69.5 MiB 1.17 0.02 3.91483 -3854.15 -3.91483 3.91483 0.00 0.00501054 0.00442487 0.50283 0.44465 -1 -1 -1 -1 -1 13822 12 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.47 0.720818 0.646017 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 + timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33484 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 3 5 1 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.4271e-05 9.019e-06 0.000105429 7.7044e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00167801 0.00157995 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 + timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33216 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 9 9 3 3 3 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.5585e-05 1.0104e-05 0.000105029 7.6023e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.00153942 0.00144868 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 + timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.33 abc 63.01 MiB 0.24 59520 -1 -1 2 1.56 -1 -1 64520 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63024 5 156 191 347 1 163 316 15 15 225 clb auto 22.0 MiB 0.04 29 82016 58904 3157 19955 61.5 MiB 0.15 0.00 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000408132 0.000370067 0.0341355 0.031078 -1 -1 -1 -1 -1 32 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0428942 0.0391583 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 + timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.51 abc 63.14 MiB 0.34 59776 -1 -1 2 1.51 -1 -1 64652 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63260 5 156 191 347 1 163 316 15 15 225 clb auto 22.2 MiB 0.02 41 76641 54775 3226 18640 61.8 MiB 0.14 0.00 1.49775 -14.6172 -1.49775 1.49775 0.00 0.000395712 0.000358237 0.0299271 0.0269791 -1 -1 -1 -1 -1 63 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0377601 0.0341837 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 + timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.33 vpr 65.29 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33412 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 2 1 3 4 1 3 4 3 3 9 -1 auto 26.8 MiB 0.00 6 9 3 5 1 65.3 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5615e-05 1.0606e-05 0.000109326 8.0241e-05 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00165784 0.00156601 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 + timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.25 vpr 65.38 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33208 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 2 1 3 4 1 3 4 3 3 9 -1 auto 27.1 MiB 0.00 9 9 3 3 3 65.4 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.6671e-05 1.1297e-05 0.000111494 8.1284e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00178932 0.0017001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 + timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.46 vpr 71.98 MiB 0.15 16896 -1 -1 2 0.16 -1 -1 37600 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73704 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.58 8394 210108 78030 120895 11183 72.0 MiB 1.33 0.02 3.90475 -4339.03 -3.90475 3.90475 0.00 0.00537924 0.00456001 0.565099 0.476317 -1 -1 -1 -1 -1 12247 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.38 0.731735 0.628685 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 + timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.57 vpr 72.21 MiB 0.16 17152 -1 -1 2 0.16 -1 -1 37596 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73948 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.52 9639 203757 70988 121974 10795 72.2 MiB 1.36 0.02 4.05379 -3834.49 -4.05379 4.05379 0.00 0.00624609 0.00547423 0.627089 0.535493 -1 -1 -1 -1 -1 13797 11 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.48 0.824983 0.713955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt index 0dd8c10602e..270c7d97d80 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.74 vpr 63.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65156 8 4 25 28 5 19 19 6 6 36 clb auto 24.9 MiB 0.49 52 194 34 129 31 63.6 MiB 0.00 0.00 1.3678 -5.84519 -1.3678 0.545 0.00 5.5961e-05 4.3116e-05 0.000686942 0.000559692 -1 -1 -1 -1 94 6.71429 38 2.71429 16 16 1079 432 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.70371 0.545 -7.0897 -1.70371 -0.508975 -0.416549 0.01 -1 -1 63.6 MiB 0.00 0.00293536 0.0026611 63.6 MiB -1 0.01 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.04 vpr 18.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 18748 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.68 vpr 66.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 8 4 25 28 5 19 19 6 6 36 clb auto 27.9 MiB 0.43 51 194 39 119 36 66.2 MiB 0.00 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 6.5511e-05 4.9348e-05 0.000956967 0.000802791 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.2 MiB 0.00 0.00312006 0.00280809 66.2 MiB -1 0.01 + k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt index 4ff0e8b463a..a8229d3cc5f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.50 vpr 62.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64284 -1 2 2 4 0 2 4 4 4 16 clb auto 24.1 MiB 0.01 0 9 0 2 7 62.8 MiB 0.00 0.00 nan 0 0 nan 0.01 1.5871e-05 9.709e-06 0.000102284 7.0143e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00143641 0.00135809 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00160323 0.00154708 + k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.39 vpr 65.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 -1 2 2 4 0 2 4 4 4 16 clb auto 27.0 MiB 0.00 0 9 0 2 7 65.3 MiB 0.00 0.00 nan 0 0 nan 0.01 1.324e-05 7.342e-06 8.3458e-05 5.501e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00154065 0.00146112 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00148898 0.00145049 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt index be7b1d7e3c9..dedf8b436ab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 33.90 vpr 92.21 MiB 0.48 31696 -1 -1 3 1.32 -1 -1 40548 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 94428 214 305 2963 2869 1 1444 650 25 25 625 -1 25x25 44.0 MiB 3.82 12566 298934 100179 176792 21963 84.9 MiB 2.12 0.03 4.48882 -2692.89 -4.48882 4.48882 2.29 0.00709216 0.00653764 0.858961 0.793235 -1 -1 -1 -1 56 23237 32 3.19446e+07 9.79696e+06 2.27235e+06 3635.76 16.01 3.41745 3.12097 68115 457904 -1 20684 16 5341 11970 1408411 380795 4.73758 4.73758 -2976.98 -4.73758 0 0 2.89946e+06 4639.14 0.78 0.63 0.39 -1 -1 0.78 0.342569 0.318423 - column_io.xml raygentop.v common 38.50 vpr 84.88 MiB 0.44 31584 -1 -1 3 1.32 -1 -1 40468 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86916 214 305 2963 2869 1 1444 650 25 25 625 io auto 44.1 MiB 3.74 11473 259538 92955 142257 24326 84.9 MiB 2.04 0.03 4.47884 -2622.54 -4.47884 4.47884 2.19 0.00782519 0.00725944 0.825246 0.760138 -1 -1 -1 -1 46 25888 44 2.82259e+07 9.79696e+06 1.74878e+06 2798.05 21.24 3.9598 3.60408 57264 344844 -1 20796 16 6055 13443 1912977 469313 4.80041 4.80041 -2970.49 -4.80041 0 0 2.25408e+06 3606.53 0.58 0.69 0.30 -1 -1 0.58 0.341447 0.317119 - multiwidth_blocks.xml raygentop.v common 25.55 vpr 84.75 MiB 0.46 31704 -1 -1 3 1.40 -1 -1 40456 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86780 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 44.0 MiB 3.78 11816 245468 79004 142595 23869 84.7 MiB 1.98 0.03 4.52802 -2725.19 -4.52802 4.52802 0.94 0.00949291 0.00850738 0.847864 0.781876 -1 -1 -1 -1 60 23563 42 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 10.95 3.41073 3.11126 34801 210837 -1 19834 20 6107 14382 2085679 598371 5.05307 5.05307 -2966.13 -5.05307 0 0 1.43369e+06 3971.44 0.44 0.94 0.25 -1 -1 0.44 0.424155 0.39432 - non_column.xml raygentop.v common 47.61 vpr 105.35 MiB 0.62 32012 -1 -1 3 1.48 -1 -1 40516 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 107876 214 305 2963 2869 1 1444 650 33 33 1089 io auto 45.4 MiB 3.85 13747 248282 81945 142793 23544 103.0 MiB 1.76 0.02 4.81737 -2724.33 -4.81737 4.81737 3.97 0.0073023 0.00679977 0.722608 0.667884 -1 -1 -1 -1 44 27797 37 5.44432e+07 9.79696e+06 2.74036e+06 2516.40 25.74 3.75279 3.41577 93774 543488 -1 22309 17 5786 13251 1497600 404581 5.13958 5.13958 -3092.11 -5.13958 0 0 3.56397e+06 3272.70 1.02 0.65 0.61 -1 -1 1.02 0.349553 0.324591 - non_column_tall_aspect_ratio.xml raygentop.v common 49.55 vpr 102.16 MiB 0.66 31936 -1 -1 3 1.40 -1 -1 40480 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 104612 214 305 2963 2869 1 1444 650 23 46 1058 io auto 45.7 MiB 3.89 13776 239840 84223 119240 36377 99.2 MiB 1.69 0.03 4.68258 -2779.01 -4.68258 4.68258 3.29 0.00749757 0.00702299 0.684672 0.633229 -1 -1 -1 -1 42 31648 41 5.05849e+07 9.79696e+06 2.60561e+06 2462.77 28.66 3.51495 3.19945 89863 510592 -1 24152 20 7442 17660 2259951 590976 5.67716 5.67716 -3200.57 -5.67716 0 0 3.28516e+06 3105.07 0.91 0.87 0.58 -1 -1 0.91 0.399372 0.369203 - non_column_wide_aspect_ratio.xml raygentop.v common 41.85 vpr 98.60 MiB 0.69 31936 -1 -1 3 1.59 -1 -1 40616 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 100964 214 305 2963 2869 1 1444 650 43 22 946 io auto 45.4 MiB 3.73 14156 293306 98573 164570 30163 96.1 MiB 2.16 0.02 4.68152 -2812.57 -4.68152 4.68152 3.55 0.00724035 0.00673017 0.925677 0.848397 -1 -1 -1 -1 42 29613 38 4.55909e+07 9.79696e+06 2.29725e+06 2428.38 20.53 3.62206 3.28365 79978 445530 -1 24436 20 8003 18434 2464079 661230 4.86641 4.86641 -3242.4 -4.86641 0 0 2.89121e+06 3056.25 0.80 0.92 0.53 -1 -1 0.80 0.400872 0.370601 - custom_sbloc.xml raygentop.v common 22.72 vpr 84.88 MiB 0.60 31700 -1 -1 3 1.59 -1 -1 40544 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86920 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 44.0 MiB 3.96 11545 253910 83783 147052 23075 84.9 MiB 2.20 0.03 4.53013 -2682.92 -4.53013 4.53013 0.78 0.00994624 0.00941733 0.898398 0.823185 -1 -1 -1 -1 60 22190 29 1.65001e+07 9.79696e+06 1.11685e+06 3093.75 8.02 3.01302 2.74098 34801 214773 -1 19145 15 5739 13180 1453072 396713 4.70711 4.70711 -3011.51 -4.70711 0 0 1.41014e+06 3906.19 0.34 0.44 0.19 -1 -1 0.34 0.223232 0.212144 - multiple_io_types.xml raygentop.v common 134.08 vpr 493.00 MiB 0.37 31604 -1 -1 3 1.38 -1 -1 40464 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 504836 214 305 2963 2869 1 1444 650 67 67 4489 io_left auto 44.2 MiB 4.78 27628 90698 4403 23036 63259 493.0 MiB 0.77 0.02 4.46994 -3778.7 -4.46994 4.46994 30.74 0.00783736 0.0072251 0.300586 0.27767 -1 -1 -1 -1 56 40503 35 2.48753e+08 9.79696e+06 1.37773e+07 3069.12 66.77 3.49776 3.17473 415449 2586128 -1 37151 19 7409 16932 3284490 878151 5.12129 5.12129 -4069.29 -5.12129 0 0 1.75917e+07 3918.84 5.30 1.25 2.49 -1 -1 5.30 0.401056 0.370625 + fixed_grid.xml raygentop.v common 22.04 vpr 87.12 MiB 0.37 32000 -1 -1 3 1.37 -1 -1 43832 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89216 214 305 2963 2869 1 1444 650 25 25 625 -1 25x25 45.9 MiB 3.49 12196 290492 92452 176193 21847 87.1 MiB 1.73 0.04 4.70145 -2687.49 -4.70145 4.70145 0.77 0.009062 0.00821446 0.664489 0.598586 -1 -1 -1 -1 50 24072 42 3.19446e+07 9.79696e+06 2.03477e+06 3255.63 9.38 3.04543 2.74886 65619 409230 -1 20090 15 5518 12429 1427524 369655 4.84691 4.84691 -2936.69 -4.84691 0 0 2.61863e+06 4189.80 0.13 0.72 0.40 -1 -1 0.13 0.405468 0.382168 + column_io.xml raygentop.v common 30.34 vpr 87.28 MiB 0.43 32000 -1 -1 3 1.83 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89376 214 305 2963 2869 1 1444 650 25 25 625 io auto 46.2 MiB 3.96 11325 239840 77339 132443 30058 87.3 MiB 2.09 0.03 4.40936 -2625.55 -4.40936 4.40936 1.20 0.0090281 0.0081843 0.836879 0.749323 -1 -1 -1 -1 48 24462 25 2.82259e+07 9.79696e+06 1.82181e+06 2914.90 14.53 3.9566 3.54503 57888 355703 -1 20518 17 5996 13599 1716937 426068 4.7409 4.7409 -2939.5 -4.7409 0 0 2.33544e+06 3736.71 0.17 0.92 0.52 -1 -1 0.17 0.442866 0.410518 + multiwidth_blocks.xml raygentop.v common 23.34 vpr 87.11 MiB 0.46 32000 -1 -1 3 1.66 -1 -1 43932 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89196 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.70 10825 234212 78128 135288 20796 87.1 MiB 2.20 0.03 4.45499 -2656.92 -4.45499 4.45499 0.58 0.00914429 0.00826611 0.84541 0.761865 -1 -1 -1 -1 60 22314 37 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 8.15 3.5171 3.1499 34801 210837 -1 18718 16 6372 15066 2125910 636768 4.83864 4.83864 -2933.88 -4.83864 0 0 1.43369e+06 3971.44 0.09 1.02 0.34 -1 -1 0.09 0.423489 0.392785 + non_column.xml raygentop.v common 50.57 vpr 101.43 MiB 0.57 32128 -1 -1 3 1.64 -1 -1 43688 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103864 214 305 2963 2869 1 1444 650 33 33 1089 io auto 47.6 MiB 3.38 13852 267980 91761 149229 26990 98.5 MiB 2.25 0.03 4.81737 -2748.68 -4.81737 4.81737 2.25 0.00871345 0.00790536 0.883704 0.789723 -1 -1 -1 -1 46 27889 41 5.44432e+07 9.79696e+06 2.87196e+06 2637.24 31.91 4.82411 4.34906 94862 558952 -1 23226 19 7179 17098 2136481 565014 5.00295 5.00295 -3094.61 -5.00295 0 0 3.68462e+06 3383.49 0.29 1.11 0.95 -1 -1 0.29 0.492691 0.457205 + non_column_tall_aspect_ratio.xml raygentop.v common 41.13 vpr 107.46 MiB 0.65 32128 -1 -1 3 2.07 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110040 214 305 2963 2869 1 1444 650 23 46 1058 io auto 47.5 MiB 4.75 12924 225770 77986 115287 32497 98.0 MiB 1.99 0.02 4.68258 -2746.61 -4.68258 4.68258 2.17 0.00617553 0.00548634 0.751525 0.668955 -1 -1 -1 -1 50 24702 35 5.05849e+07 9.79696e+06 3.07243e+06 2904.00 20.48 4.80846 4.28853 95149 595581 -1 21346 17 5714 12751 1591343 424414 4.99583 4.99583 -3024.29 -4.99583 0 0 3.91054e+06 3696.17 0.39 1.00 1.06 -1 -1 0.39 0.462953 0.424532 + non_column_wide_aspect_ratio.xml raygentop.v common 40.58 vpr 101.39 MiB 0.68 32000 -1 -1 3 1.80 -1 -1 43696 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103820 214 305 2963 2869 1 1444 650 43 22 946 io auto 47.4 MiB 4.77 13982 276422 90498 164087 21837 95.1 MiB 2.48 0.03 4.68152 -2857.71 -4.68152 4.68152 2.06 0.0081203 0.0072676 0.94579 0.847056 -1 -1 -1 -1 50 26296 34 4.55909e+07 9.79696e+06 2.70028e+06 2854.41 19.21 5.11489 4.60481 84704 520009 -1 22872 18 6244 14195 1614167 427447 4.86473 4.86473 -3155.96 -4.86473 0 0 3.44953e+06 3646.44 0.30 1.16 1.00 -1 -1 0.30 0.501153 0.460019 + custom_sbloc.xml raygentop.v common 25.95 vpr 86.98 MiB 0.39 32000 -1 -1 3 1.58 -1 -1 43804 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89072 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.8 MiB 4.86 11696 245468 82823 140883 21762 87.0 MiB 2.50 0.04 4.53013 -2681.39 -4.53013 4.53013 0.61 0.00909806 0.00824441 0.931511 0.836258 -1 -1 -1 -1 62 22622 49 1.65001e+07 9.79696e+06 1.15634e+06 3203.15 10.71 4.10582 3.71488 35161 219597 -1 19429 17 6137 14618 1898349 506769 4.83748 4.83748 -2977.52 -4.83748 0 0 1.43990e+06 3988.64 0.05 0.92 0.41 -1 -1 0.05 0.399467 0.368878 + multiple_io_types.xml raygentop.v common 148.40 vpr 474.05 MiB 0.38 31872 -1 -1 3 1.46 -1 -1 43604 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 485424 214 305 2963 2869 1 1444 650 67 67 4489 io_left auto 46.2 MiB 5.36 26050 90698 4115 22648 63935 474.0 MiB 0.95 0.03 4.73667 -3563.79 -4.73667 4.73667 26.71 0.00792183 0.00702959 0.36772 0.321766 -1 -1 -1 -1 52 41451 45 2.48753e+08 9.79696e+06 1.27607e+07 2842.65 95.91 4.21007 3.80326 406473 2447650 -1 35770 21 7664 17455 3505363 891802 5.27395 5.27395 -3927.86 -5.27395 0 0 1.67786e+07 3737.72 0.99 1.06 2.69 -1 -1 0.99 0.318577 0.29589 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt index 348a34af9ba..032d95a320e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 5.22 vpr 65.48 MiB 0.07 9376 -1 -1 3 0.34 -1 -1 34576 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67052 99 130 363 493 1 251 298 12 12 144 clb auto 26.1 MiB 0.16 830 72933 24114 36385 12434 65.5 MiB 0.26 0.00 2.31523 -217.996 -2.31523 2.31523 0.32 0.00107013 0.00100915 0.0756674 0.0712994 -1 -1 -1 -1 38 1547 11 5.66058e+06 4.21279e+06 328943. 2284.32 2.50 0.428144 0.389705 12522 66188 -1 1392 8 487 648 34594 11334 2.74555 2.74555 -237.815 -2.74555 0 0 418267. 2904.63 0.13 0.05 0.07 -1 -1 0.13 0.0295936 0.0277122 + k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.66 MiB 0.06 9856 -1 -1 3 0.38 -1 -1 39496 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69284 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.23 0.00 2.23767 -220.613 -2.23767 2.23767 0.25 0.00122229 0.00116469 0.0742124 0.0677305 -1 -1 -1 -1 38 1639 12 5.66058e+06 4.21279e+06 328943. 2284.32 0.72 0.298961 0.271262 12522 66188 -1 1359 8 559 726 39339 13482 2.60043 2.60043 -237.265 -2.60043 0 0 418267. 2904.63 0.03 0.05 0.11 -1 -1 0.03 0.0322868 0.0303399 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt index 57ef852f6b8..a65248b7f30 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 4.48 vpr 62.46 MiB 0.06 9372 -1 -1 4 0.34 -1 -1 34600 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63964 99 130 378 508 1 307 305 15 15 225 memory auto 22.6 MiB 0.10 1111 75203 25546 36272 13385 62.5 MiB 0.26 0.00 1.73414 -174.802 -1.73414 1.73414 0.00 0.000976408 0.000916184 0.0779894 0.0732724 -1 -1 -1 -1 1512 6.17143 792 3.23265 713 1663 202968 51102 1.16234e+06 375248 2.18283e+06 9701.45 12 48952 428016 -1 1.89635 1.89635 -187.166 -1.89635 0 0 0.66 -1 -1 62.5 MiB 0.12 0.112709 0.105511 62.5 MiB -1 2.26 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.43 vpr 64.82 MiB 0.05 9728 -1 -1 4 0.35 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66380 99 130 378 508 1 307 305 15 15 225 memory auto 25.3 MiB 0.06 1083 69047 24301 32567 12179 64.8 MiB 0.22 0.01 1.63577 -172.755 -1.63577 1.63577 0.00 0.00106212 0.000958102 0.0684136 0.0626923 -1 -1 -1 -1 1479 6.03673 767 3.13061 797 1865 235419 59319 1.16234e+06 375248 2.18283e+06 9701.45 16 48952 428016 -1 1.89463 1.89463 -188.601 -1.89463 -0.194976 -0.108352 0.68 -1 -1 64.8 MiB 0.11 0.107667 0.0986163 64.8 MiB -1 0.37 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt index d18183d9a08..c044fb36631 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 28.10 vpr 85.89 MiB 0.23 16788 -1 -1 2 0.16 -1 -1 33892 -1 -1 31 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 87952 311 156 1019 1160 1 965 513 28 28 784 memory auto 32.2 MiB 0.92 8945 195453 67462 117452 10539 83.1 MiB 1.14 0.02 4.24256 -3535.29 -4.24256 4.24256 3.03 0.0047266 0.00420892 0.495161 0.440444 -1 -1 -1 -1 46 14258 14 4.25198e+07 9.89071e+06 2.42825e+06 3097.26 14.01 2.26688 2.03164 81963 495902 -1 13674 12 2508 2888 1039968 435011 4.40824 4.40824 -4330.54 -4.40824 -371.448 -1.34258 3.12000e+06 3979.60 0.98 1.97 0.43 -1 -1 0.98 0.192689 0.174884 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 28.61 vpr 89.27 MiB 0.19 16912 -1 -1 2 0.16 -1 -1 33728 -1 -1 31 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 91412 311 156 1019 1160 1 965 513 28 28 784 memory auto 32.3 MiB 1.00 8945 195453 67462 117452 10539 83.9 MiB 1.09 0.02 4.24256 -3535.29 -4.24256 4.24256 3.23 0.00439673 0.00387964 0.464219 0.409008 -1 -1 -1 -1 46 14278 13 4.25198e+07 9.89071e+06 2.47848e+06 3161.33 14.05 2.05809 1.83585 81963 509322 -1 13687 11 2477 2842 628309 183554 4.6903 4.6903 -4253.53 -4.6903 -195.104 -1.3767 3.17357e+06 4047.92 1.31 2.14 0.43 -1 -1 1.31 0.196452 0.182983 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 28.86 vpr 86.38 MiB 0.18 16924 -1 -1 2 0.18 -1 -1 33688 -1 -1 31 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 88452 311 156 1019 1160 1 965 513 28 28 784 memory auto 32.4 MiB 0.86 9287 195453 66686 117509 11258 82.3 MiB 1.11 0.02 4.12801 -3603.7 -4.12801 4.12801 2.98 0.00506386 0.00456663 0.488102 0.431794 -1 -1 -1 -1 46 15578 14 4.25198e+07 9.89071e+06 2.42368e+06 3091.42 14.99 2.15465 1.92472 81963 496068 -1 14973 12 2225 2503 1188709 769601 5.70473 5.70473 -4410.99 -5.70473 -1643.75 -3.31884 3.11542e+06 3973.75 0.91 2.07 0.43 -1 -1 0.91 0.187032 0.169642 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 16.11 vpr 77.95 MiB 0.11 17024 -1 -1 2 0.10 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79820 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.7 MiB 0.63 9390 201609 69489 120331 11789 76.8 MiB 1.40 0.02 4.09817 -3462.19 -4.09817 4.09817 1.75 0.00638402 0.00561878 0.639416 0.550497 -1 -1 -1 -1 36 15662 18 4.25198e+07 9.89071e+06 1.97160e+06 2514.80 6.39 2.29245 2.04057 76483 392267 -1 14444 15 3124 3650 1031496 356426 4.24327 4.24327 -4339.34 -4.24327 -405.202 -1.29702 2.42825e+06 3097.26 0.20 1.56 0.59 -1 -1 0.20 0.278119 0.255639 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.94 vpr 83.35 MiB 0.18 17024 -1 -1 2 0.12 -1 -1 37644 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 85352 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.95 9390 201609 69489 120331 11789 83.4 MiB 0.81 0.01 4.09817 -3462.19 -4.09817 4.09817 1.06 0.00320533 0.00273182 0.351431 0.298654 -1 -1 -1 -1 36 15777 15 4.25198e+07 9.89071e+06 2.00618e+06 2558.90 4.74 1.57738 1.39763 76483 403003 -1 14373 10 2886 3379 762706 219312 4.3954 4.3954 -4595.94 -4.3954 -153.524 -1.32288 2.47848e+06 3161.33 0.22 1.20 0.50 -1 -1 0.22 0.199455 0.182428 15 950 + timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 20.64 vpr 78.23 MiB 0.14 17152 -1 -1 2 0.19 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80112 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.82 8956 201609 71778 118284 11547 78.2 MiB 1.41 0.02 3.73942 -3418.22 -3.73942 3.73942 1.71 0.00607733 0.00531502 0.647808 0.554869 -1 -1 -1 -1 36 16279 32 4.25198e+07 9.89071e+06 1.96702e+06 2508.96 9.86 2.33237 2.04039 76483 392433 -1 15198 14 2704 3167 1739681 1219090 5.58949 5.58949 -4496.49 -5.58949 -1697.62 -3.42836 2.42368e+06 3091.42 0.20 2.25 0.55 -1 -1 0.20 0.242641 0.222883 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt index b07d8e1e443..3e3e8b64dd5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 14.06 vpr 69.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70736 64 39 1935 1974 1 1077 541 23 23 529 clb auto 28.9 MiB 0.36 10085 137127 36539 98027 2561 69.1 MiB 1.18 0.02 7.41831 -1418.64 -7.41831 7.41831 0.87 0.00457621 0.0038989 0.327684 0.280049 -1 -1 -1 -1 22 12754 28 983127 976439 735934. 1391.18 7.82 1.0919 0.944895 35322 121345 -1 11109 19 6608 23845 1462488 382373 7.14816 7.14816 -1474.13 -7.14816 0 0 927497. 1753.30 0.17 0.70 0.15 -1 -1 0.17 0.211387 0.189904 + k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.94 vpr 71.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73360 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.5 MiB 0.26 10472 141533 36950 100839 3744 71.6 MiB 1.41 0.02 7.46482 -1369.01 -7.46482 7.46482 0.60 0.00534435 0.00471558 0.398834 0.330633 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.25 2.1497 1.834 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.76 0.21 -1 -1 0.04 0.209487 0.18755 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt index 58a35002d9a..57a8e16dad9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 34.24 vpr 86.90 MiB 0.42 29492 -1 -1 4 2.47 -1 -1 38196 -1 -1 169 193 5 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 88984 193 205 2863 2789 1 1374 572 20 20 400 memory auto 43.5 MiB 2.02 11201 252110 92751 131930 27429 84.6 MiB 2.85 0.03 4.45067 -2677.23 -4.45067 4.45067 1.22 0.0117307 0.0109776 1.3522 1.20596 -1 -1 -1 -1 80 22067 39 2.07112e+07 1.18481e+07 2.10510e+06 5262.74 18.77 4.81689 4.2918 53274 447440 -1 19298 16 5571 15462 1144445 252495 4.66289 4.66289 -2899.83 -4.66289 -11.7102 -0.360359 2.64606e+06 6615.15 0.68 0.61 0.38 -1 -1 0.68 0.361937 0.331231 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 26.42 vpr 86.55 MiB 0.39 29568 -1 -1 4 2.92 -1 -1 43300 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88632 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.3 MiB 1.96 10985 240245 81936 130873 27436 86.6 MiB 2.98 0.04 4.42447 -2617.73 -4.42447 4.42447 0.87 0.010731 0.00973575 1.17585 1.01795 -1 -1 -1 -1 78 21148 32 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 12.21 3.92596 3.45972 52874 439520 -1 19015 16 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.81 0.45 -1 -1 0.19 0.495649 0.459932 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt index 8ee4a9abbe5..7d3c0c996a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 5.07 vpr 65.37 MiB 0.06 9596 -1 -1 3 0.31 -1 -1 34612 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66936 99 130 363 493 1 251 298 12 12 144 clb auto 26.0 MiB 0.16 830 72933 24114 36385 12434 65.4 MiB 0.28 0.00 2.31523 -217.996 -2.31523 2.31523 0.35 0.00104781 0.000982566 0.0900921 0.0848773 -1 -1 -1 -1 38 1583 13 5.66058e+06 4.21279e+06 319130. 2216.18 2.23 0.432918 0.394254 12522 62564 -1 1389 8 493 651 37667 12430 2.73633 2.73633 -236.043 -2.73633 0 0 406292. 2821.48 0.13 0.05 0.07 -1 -1 0.13 0.0283815 0.0266422 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.83 vpr 67.63 MiB 0.09 9984 -1 -1 3 0.34 -1 -1 39772 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69252 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.20 804 66963 21682 33533 11748 67.6 MiB 0.34 0.01 2.23767 -220.613 -2.23767 2.23767 0.27 0.000902266 0.000807045 0.0650955 0.0583605 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 1.19 0.319458 0.291293 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.06 0.09 -1 -1 0.03 0.0273369 0.0256329 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index f32816621c9..ceb027e03e3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 169.74 vpr 277.27 MiB 2.37 126048 -1 -1 5 83.26 -1 -1 75348 -1 -1 1337 157 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 283924 157 197 21024 21221 1 6369 1691 39 39 1521 clb auto 124.0 MiB 4.94 49118 978481 352716 605570 20195 277.3 MiB 10.50 0.11 3.82872 -14985.1 -3.82872 3.82872 9.61 0.030689 0.0261212 3.24668 2.69757 -1 -1 -1 -1 36 61735 32 2.4642e+07 2.4066e+07 4.11737e+06 2707.01 35.88 15.6221 12.8274 115990 821377 -1 57847 23 29862 63292 2473837 450954 3.66887 3.66887 -15765.9 -3.66887 0 0 5.03985e+06 3313.51 1.56 2.53 0.62 -1 -1 1.56 1.85817 1.5961 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 171.11 vpr 275.04 MiB 2.66 126004 -1 -1 5 87.20 -1 -1 75432 -1 -1 1356 157 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 281640 157 197 21024 21221 1 6467 1710 39 39 1521 clb auto 124.0 MiB 5.16 51290 993147 360680 608362 24105 275.0 MiB 10.32 0.11 3.26166 -14917.8 -3.26166 3.26166 9.34 0.0308111 0.0262182 3.21737 2.66176 -1 -1 -1 -1 42 62756 33 7.37824e+07 7.30817e+07 4.49269e+06 2953.77 32.95 14.6319 12.0222 122070 906769 -1 60178 20 29762 65352 2439585 446633 3.2534 3.2534 -15909.6 -3.2534 0 0 5.60675e+06 3686.23 1.70 2.67 0.70 -1 -1 1.70 1.88443 1.62 + k6_N10_40nm.xml stereovision0.v common 198.12 vpr 257.14 MiB 2.00 126464 -1 -1 5 139.65 -1 -1 78708 -1 -1 1337 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 263312 157 197 21024 21221 1 6369 1691 39 39 1521 clb auto 124.7 MiB 6.38 48812 948271 327778 599083 21410 257.1 MiB 9.39 0.13 3.8487 -15314.7 -3.8487 3.8487 8.33 0.0426525 0.0388129 3.00817 2.44576 -1 -1 -1 -1 38 60857 30 2.4642e+07 2.4066e+07 4.29790e+06 2825.71 13.17 9.3436 7.78726 119030 883757 -1 57009 24 29792 62484 2448958 439074 3.78459 3.78459 -15886.2 -3.78459 0 0 5.41627e+06 3561.00 0.27 2.25 0.65 -1 -1 0.27 1.68943 1.4738 + k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 201.99 vpr 255.40 MiB 2.14 126336 -1 -1 5 142.90 -1 -1 78972 -1 -1 1356 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 261528 157 197 21024 21221 1 6467 1710 39 39 1521 clb auto 124.6 MiB 7.21 49809 962484 334554 607807 20123 255.4 MiB 9.87 0.12 3.26114 -15027.4 -3.26114 3.26114 7.20 0.0351221 0.0281327 3.06287 2.48936 -1 -1 -1 -1 38 63075 34 7.37824e+07 7.30817e+07 4.16760e+06 2740.04 13.41 9.93144 8.27431 119030 845795 -1 59104 24 31762 70331 2621462 488165 3.1068 3.1068 -15929.2 -3.1068 0 0 5.22668e+06 3436.35 0.24 2.20 0.62 -1 -1 0.24 1.62443 1.4202 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index f19ec3ad52a..53aa221bde0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.41 vpr 58.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59448 3 1 5 6 1 4 5 3 3 9 -1 auto 19.6 MiB 0.00 9 12 4 4 4 58.1 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.4994e-05 1.045e-05 0.000115391 8.7864e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00160683 0.00150489 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.01 0.00 -1 -1 0.00 0.0017143 0.00166299 - k6_frac_N10_40nm.xml conn_order.eblif common 0.37 vpr 58.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59528 2 1 4 5 1 3 4 3 3 9 -1 auto 19.7 MiB 0.00 6 9 4 1 4 58.1 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.8474e-05 1.3622e-05 0.000123757 9.6624e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00168156 0.00158496 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00150108 0.00146247 + k6_frac_N10_40nm.xml test_eblif.eblif common 0.35 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 6.5921e-05 4.9487e-05 0.000173999 0.000134314 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00172845 0.00161091 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.0015722 0.00153245 + k6_frac_N10_40nm.xml conn_order.eblif common 0.43 vpr 60.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61580 2 1 4 5 1 3 4 3 3 9 -1 auto 21.9 MiB 0.01 6 9 4 1 4 60.1 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.01 1.6713e-05 1.1905e-05 0.000118437 9.2123e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00165899 0.00156225 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00153235 0.00149153 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt index cc7ced1ba94..c0c64f8d2c1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.35 vpr 56.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57852 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 17.8 MiB 0.00 14 18 7 10 1 56.5 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.0474e-05 1.286e-05 0.000117644 8.503e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00148217 0.00137435 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00134946 0.00130933 + arch.xml eblif_write.eblif common 0.32 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.3959e-05 1.5869e-05 0.000131827 9.7152e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00165685 0.00154691 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00177312 0.00171917 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt index 87280012ec8..c750dd52020 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.90 vpr 63.89 MiB 0.07 9972 -1 -1 4 0.20 -1 -1 33336 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65424 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.22 439 1932 239 1639 54 63.9 MiB 0.17 0.00 2.45279 -180.032 -2.45279 2.33029 0.00 0.000657413 0.000584504 0.0150448 0.0136066 -1 -1 -1 -1 -1 515 20 1.07788e+06 1.02399e+06 90369.8 1844.28 0.06 0.0521894 0.0464461 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.53 vpr 66.67 MiB 0.08 10368 -1 -1 4 0.21 -1 -1 36920 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68272 11 30 262 292 2 99 60 7 7 49 clb auto 27.0 MiB 0.11 431 1932 256 1610 66 66.7 MiB 0.10 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000756181 0.000646522 0.0198618 0.0177275 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0693622 0.0613246 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt index 516b44c0fea..41d36d5dda6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.38 vpr 56.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57744 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 17.7 MiB 0.00 9 9 4 5 0 56.4 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 1.6528e-05 1.0245e-05 0.000103641 7.0812e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.01 0.00155316 0.00143742 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00496134 0.00490329 + equivalent.xml equivalent.blif common 0.40 vpr 58.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60148 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.5 MiB 0.00 9 9 3 6 0 58.7 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 2.1313e-05 1.5936e-05 0.000108787 8.0593e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00168168 0.00158747 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00146867 0.00143048 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt index dd9f37179ee..41bceae31db 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.34 vpr 63.85 MiB 0.08 9940 -1 -1 4 0.20 -1 -1 33440 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65384 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.14 439 1932 239 1639 54 63.9 MiB 0.04 0.00 2.45862 -180.487 -2.45862 2.33539 0.09 0.00077729 0.000695808 0.0176391 0.0160225 -1 -1 -1 -1 16 612 29 1.07788e+06 1.02399e+06 88828.2 1812.82 0.37 0.136394 0.116654 2520 24504 -1 539 24 882 1910 71912 23696 2.90651 2.60442 -203.665 -2.90651 0 0 104221. 2126.97 0.02 0.08 0.02 -1 -1 0.02 0.0427223 0.0370258 + k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.46 vpr 66.34 MiB 0.09 10240 -1 -1 4 0.25 -1 -1 36836 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67932 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.10 417 1932 303 1579 50 66.3 MiB 0.03 0.00 2.45862 -181.765 -2.45862 2.33618 0.06 0.000452546 0.000389719 0.0170733 0.0149049 -1 -1 -1 -1 14 566 30 1.07788e+06 1.02399e+06 81563.3 1664.56 0.67 0.279658 0.24196 2472 22196 -1 446 21 890 1897 62387 19776 2.78119 2.51931 -191.416 -2.78119 0 0 98201.7 2004.12 0.00 0.07 0.02 -1 -1 0.00 0.0396875 0.0352228 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt index 872db87890a..76744275cd6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 18.65 vpr 72.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74548 38 3 1916 1919 0 1054 173 7 7 49 clb auto 32.1 MiB 4.34 5783 1135 0 0 1135 72.8 MiB 0.08 0.01 5.07028 -15.1308 -5.07028 nan 0.25 0.0047809 0.00426017 0.0574249 0.0545498 -1 -1 -1 -1 164 7801 37 1.34735e+06 7.11401e+06 957298. 19536.7 11.19 2.64641 2.25522 18546 296938 -1 7371 18 5579 21538 954225 313419 5.58606 nan -16.4292 -5.58606 0 0 1.19720e+06 24432.6 0.16 0.49 0.20 -1 -1 0.16 0.251401 0.227559 + fix_clusters_test_arch.xml apex2.blif common 15.55 vpr 74.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76704 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.1 MiB 5.08 5783 1135 0 0 1135 74.9 MiB 0.08 0.01 5.08129 -15.1527 -5.08129 nan 0.20 0.00521387 0.00456397 0.054855 0.0516446 -1 -1 -1 -1 164 7880 41 1.34735e+06 7.11401e+06 957298. 19536.7 8.09 2.3336 2.00198 18546 296938 -1 7311 19 6308 26453 1146687 361661 5.58525 nan -16.6102 -5.58525 0 0 1.19720e+06 24432.6 0.03 0.49 0.23 -1 -1 0.03 0.228213 0.208678 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt index b572ada2e35..2735c09358a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.74 vpr 64.04 MiB 0.08 10112 -1 -1 4 0.22 -1 -1 33448 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65572 11 30 262 292 2 99 60 7 7 49 clb auto 24.9 MiB 0.12 500 1815 77 1659 79 64.0 MiB 0.04 0.00 2.45489 -182.961 -2.45489 2.31533 0.07 0.000651787 0.000580678 0.0147164 0.0132877 -1 -1 -1 -1 20 654 22 1.07788e+06 1.02399e+06 49980.0 1020.00 0.81 0.247093 0.207481 2664 9102 -1 555 29 713 1765 48495 15174 2.71208 2.45165 -189.124 -2.71208 0 0 65453.8 1335.79 0.01 0.10 0.01 -1 -1 0.01 0.046742 0.040451 + k6_N10_mem32K_40nm.xml stereovision3.v common 2.00 vpr 66.73 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36456 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.07 499 1698 69 1565 64 66.7 MiB 0.04 0.00 2.45489 -182.908 -2.45489 2.31533 0.06 0.000803566 0.000668095 0.0165762 0.0143795 -1 -1 -1 -1 18 719 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.43 0.155736 0.134195 2616 8308 -1 605 32 901 2129 57619 17801 2.65666 2.40393 -192.483 -2.65666 0 0 59124.6 1206.62 0.00 0.09 0.01 -1 -1 0.00 0.062047 0.0552258 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt index fe1762c812f..03193b42990 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 28.11 vpr 85.11 MiB 0.48 31828 -1 -1 3 1.48 -1 -1 40620 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 87156 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 44.1 MiB 3.89 11650 228584 75365 133281 19938 85.1 MiB 1.70 0.02 4.52591 -2650.49 -4.52591 4.52591 0.90 0.00694747 0.00642845 0.678406 0.627386 -1 -1 -1 -1 62 24826 45 1.65001e+07 9.79696e+06 1.07728e+06 2984.15 12.61 3.53011 3.21334 35161 217957 -1 20696 17 6141 14924 1916680 524150 5.05166 5.05166 -3006.03 -5.05166 0 0 1.33769e+06 3705.50 0.54 1.08 0.21 -1 -1 0.54 0.444555 0.407313 - buffered_flyover_wires.xml raygentop.v common 28.01 vpr 84.93 MiB 0.45 31828 -1 -1 3 1.40 -1 -1 40476 -1 -1 123 214 0 8 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 86964 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 44.0 MiB 3.80 11698 253910 84523 146224 23163 84.9 MiB 1.92 0.03 4.66082 -2769.33 -4.66082 4.66082 0.91 0.00707593 0.00652878 0.742599 0.682762 -1 -1 -1 -1 62 26047 33 1.65001e+07 9.79696e+06 1.11546e+06 3089.92 12.71 3.5903 3.26464 35161 215557 -1 20655 16 5970 13512 1728683 469210 4.89641 4.89641 -3008.4 -4.89641 0 0 1.38748e+06 3843.44 0.40 0.76 0.26 -1 -1 0.40 0.354607 0.333482 + shorted_flyover_wires.xml raygentop.v common 26.23 vpr 87.18 MiB 0.37 31744 -1 -1 3 1.50 -1 -1 43564 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89276 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 46.2 MiB 4.36 11021 242654 80011 140532 22111 87.2 MiB 2.29 0.03 4.72515 -2651.47 -4.72515 4.72515 0.68 0.00870927 0.00789125 0.867466 0.775905 -1 -1 -1 -1 58 24978 46 1.65001e+07 9.79696e+06 1.00638e+06 2787.76 11.26 3.56546 3.21933 34441 208101 -1 21032 16 5966 14058 1826516 536884 5.22938 5.22938 -3010.82 -5.22938 0 0 1.28387e+06 3556.43 0.10 1.10 0.34 -1 -1 0.10 0.47794 0.447984 + buffered_flyover_wires.xml raygentop.v common 23.64 vpr 87.26 MiB 0.39 31872 -1 -1 3 1.51 -1 -1 43828 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89352 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.72 11369 231398 74152 135293 21953 87.3 MiB 2.16 0.03 4.81413 -2746.12 -4.81413 4.81413 0.60 0.00796315 0.00714187 0.791566 0.711054 -1 -1 -1 -1 64 23029 28 1.65001e+07 9.79696e+06 1.15406e+06 3196.84 8.51 3.3002 2.94744 35881 226057 -1 19740 15 5519 12704 1627954 469106 4.80072 4.80072 -2914.34 -4.80072 0 0 1.44847e+06 4012.38 0.10 0.92 0.36 -1 -1 0.10 0.422967 0.392398 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt index f7b51b17509..b90ac6049e3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 3.40 vpr 62.06 MiB 0.03 6628 -1 -1 1 0.04 -1 -1 30748 -1 -1 0 193 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63552 193 32 545 422 1 289 227 21 21 441 io auto 22.7 MiB 1.72 3760 44515 18630 25456 429 62.1 MiB 0.25 0.00 2.985 -824.754 -2.985 2.985 0.00 0.00161493 0.00152336 0.121894 0.115535 -1 -1 -1 -1 4680 16.2500 1223 4.24653 405 405 152557 41043 809148 68766.3 979092. 2220.16 4 24050 197379 -1 2.985 2.985 -815.015 -2.985 -21.7856 -0.0851 0.27 -1 -1 62.1 MiB 0.09 0.150499 0.142754 62.1 MiB -1 0.46 + hard_fpu_arch_timing.xml mm3.v common 3.31 vpr 64.39 MiB 0.03 7296 -1 -1 1 0.04 -1 -1 34228 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65940 193 32 545 422 1 289 227 21 21 441 io auto 25.0 MiB 1.91 3735 46591 19762 26388 441 64.4 MiB 0.33 0.00 2.985 -824.634 -2.985 2.985 0.00 0.00288823 0.00269357 0.190083 0.178688 -1 -1 -1 -1 4590 15.9375 1212 4.20833 431 431 162323 43530 809148 68766.3 979092. 2220.16 5 24050 197379 -1 2.985 2.985 -813.802 -2.985 -21.7856 -0.0851 0.43 -1 -1 64.4 MiB 0.09 0.239729 0.22641 64.4 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt index 8d04367586b..356e91ccb39 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 5.28 vpr 65.87 MiB 0.06 9504 -1 -1 3 0.30 -1 -1 34508 -1 -1 69 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67448 99 130 363 493 1 251 299 13 13 169 clb auto 26.3 MiB 0.79 804 78221 18305 27577 32339 65.9 MiB 0.15 0.00 30 1517 12 0 0 423577. 2506.37 2.58 + k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 3.01 vpr 67.75 MiB 0.06 9728 -1 -1 3 0.26 -1 -1 39908 -1 -1 69 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69380 99 130 363 493 1 251 299 13 13 169 clb auto 28.2 MiB 0.66 756 79220 19640 31087 28493 67.8 MiB 0.16 0.00 36 1238 7 0 0 481804. 2850.91 0.62 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt index cb598477e98..a8ea9747374 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.50 vpr 64.39 MiB 0.06 9976 -1 -1 4 0.20 -1 -1 33252 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65940 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.08 439 1932 239 1639 54 64.4 MiB 0.03 0.00 2.45279 -180.032 -2.45279 2.33029 0.00 0.000720509 0.000652851 0.0155916 0.0141569 -1 -1 -1 -1 -1 515 20 1.07788e+06 1.02399e+06 90369.8 1844.28 0.13 0.0559681 0.0494905 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.21 vpr 66.19 MiB 0.08 10368 -1 -1 4 0.19 -1 -1 36516 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67780 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.09 431 1932 256 1610 66 66.2 MiB 0.04 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000582727 0.000489391 0.0185537 0.0162573 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0660847 0.0581726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt index fd632535e93..265af1c4b6f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.47 vpr 58.11 MiB -1 -1 -1 -1 0 0.02 -1 -1 30028 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59500 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.3 MiB 0.00 0 3 0 0 3 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1407e-05 6.644e-06 7.1183e-05 4.7157e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00151053 0.00144317 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.49 vpr 58.14 MiB -1 -1 -1 -1 0 0.02 -1 -1 30172 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59532 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.4 MiB 0.00 0 3 0 0 3 58.1 MiB 0.01 0.00 nan 0 0 nan 0.00 1.7072e-05 9.987e-06 0.000106416 7.4745e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00149324 0.00140851 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.53 vpr 58.27 MiB -1 -1 -1 -1 0 0.02 -1 -1 29980 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59668 6 1 1 8 0 1 8 3 3 9 -1 auto 19.9 MiB 0.01 0 21 0 10 11 58.3 MiB 0.01 0.00 nan 0 0 nan 0.00 1.3008e-05 7.386e-06 8.9652e-05 6.0451e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00174003 0.00165512 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.53 vpr 58.11 MiB -1 -1 -1 -1 0 0.02 -1 -1 29992 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59500 6 1 1 8 0 1 8 3 3 9 -1 auto 19.7 MiB 0.01 0 21 0 10 11 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.5792e-05 1.0252e-05 0.000103309 7.4098e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00156505 0.001486 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.56 vpr 57.91 MiB -1 -1 -1 -1 1 0.02 -1 -1 30068 -1 -1 1 2 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59300 2 1 3 4 0 3 4 3 3 9 -1 auto 19.5 MiB 0.00 9 9 3 3 3 57.9 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.5498e-05 1.9252e-05 0.000160935 0.000125409 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.01 0.00168391 0.00159252 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.62 vpr 58.08 MiB -1 -1 -1 -1 1 0.06 -1 -1 31736 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59476 5 1 6 7 0 6 7 3 3 9 -1 auto 19.6 MiB 0.01 18 18 13 5 0 58.1 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.2311e-05 1.6717e-05 0.000157551 0.000125745 -1 -1 -1 -1 -1 7 11 53894 53894 38783.3 4309.26 0.01 0.00219389 0.00197302 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.66 vpr 58.25 MiB -1 -1 -1 -1 1 0.05 -1 -1 31952 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59648 5 1 6 7 0 6 7 3 3 9 -1 auto 19.8 MiB 0.01 18 18 13 5 0 58.2 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.9477e-05 1.46e-05 0.000163199 0.000132585 -1 -1 -1 -1 -1 7 11 53894 53894 38783.3 4309.26 0.01 0.00211569 0.00193 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.41 vpr 58.29 MiB -1 -1 -1 -1 1 0.03 -1 -1 29892 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59684 3 1 5 6 1 4 5 3 3 9 -1 auto 19.9 MiB 0.00 9 12 7 1 4 58.3 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.9413e-05 1.4525e-05 0.000151541 0.000121539 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00156423 0.0014768 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.56 vpr 58.16 MiB -1 -1 -1 -1 1 0.05 -1 -1 31904 -1 -1 1 3 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59556 4 1 4 6 0 4 6 3 3 9 -1 auto 19.8 MiB 0.00 12 15 9 3 3 58.2 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.6085e-05 1.1811e-05 0.000113992 8.8678e-05 -1 -1 -1 -1 -1 6 11 53894 53894 38783.3 4309.26 0.00 0.00203847 0.00189567 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_2x2.blif common 0.61 vpr 58.12 MiB -1 -1 -1 -1 1 0.05 -1 -1 31660 -1 -1 1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59512 4 4 8 12 0 8 9 3 3 9 -1 auto 19.7 MiB 0.04 24 27 18 6 3 58.1 MiB 0.01 0.00 0.67231 -2.68924 -0.67231 nan 0.00 4.7416e-05 3.8601e-05 0.000343952 0.00030105 -1 -1 -1 -1 -1 10 9 53894 53894 38783.3 4309.26 0.00 0.00246093 0.00226122 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x3.blif common 0.62 vpr 58.05 MiB -1 -1 -1 -1 1 0.06 -1 -1 32468 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59440 6 6 12 18 0 12 13 3 3 9 -1 auto 19.3 MiB 0.01 36 43 32 7 4 58.0 MiB 0.02 0.00 0.69831 -4.13786 -0.69831 nan 0.00 4.0028e-05 3.3256e-05 0.000373397 0.000331328 -1 -1 -1 -1 -1 17 11 53894 53894 38783.3 4309.26 0.02 0.00325081 0.00295479 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x4.blif common 0.68 vpr 58.19 MiB -1 -1 -1 -1 2 0.06 -1 -1 32136 -1 -1 3 7 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59588 7 8 22 30 0 15 18 4 4 16 clb auto 19.3 MiB 0.01 55 64 20 42 2 58.2 MiB 0.01 0.00 1.29035 -7.83841 -1.29035 nan 0.00 9.5936e-05 8.43e-05 0.000897006 0.000832614 -1 -1 -1 -1 -1 46 5 215576 161682 99039.1 6189.95 0.01 0.00479868 0.00447043 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_4x4.blif common 0.69 vpr 58.24 MiB -1 -1 -1 -1 4 0.07 -1 -1 32308 -1 -1 2 8 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59640 8 8 29 37 0 21 18 4 4 16 clb auto 19.3 MiB 0.02 76 64 16 48 0 58.2 MiB 0.03 0.01 2.08631 -12.2832 -2.08631 nan 0.00 0.000311196 0.000286678 0.00152412 0.00143184 -1 -1 -1 -1 -1 58 14 215576 107788 99039.1 6189.95 0.03 0.00857602 0.00778066 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x5.blif common 0.76 vpr 58.57 MiB -1 -1 -1 -1 4 0.10 -1 -1 32724 -1 -1 4 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59976 10 10 47 57 0 39 24 4 4 16 clb auto 19.3 MiB 0.03 146 364 62 302 0 58.6 MiB 0.01 0.00 2.72561 -18.4747 -2.72561 nan 0.00 0.000163521 0.000149451 0.00302228 0.00280654 -1 -1 -1 -1 -1 114 16 215576 215576 99039.1 6189.95 0.06 0.012168 0.0109894 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x6.blif common 0.88 vpr 58.62 MiB -1 -1 -1 -1 5 0.12 -1 -1 33096 -1 -1 5 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60032 11 11 61 72 0 51 27 5 5 25 clb auto 19.4 MiB 0.04 211 227 56 171 0 58.6 MiB 0.02 0.00 3.36952 -22.7724 -3.36952 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2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.5 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 3.2064e-05 2.4155e-05 0.000200579 0.000160863 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00242941 0.00220554 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_2bit.blif common 0.46 vpr 60.28 MiB -1 -1 -1 -1 1 0.06 -1 -1 35352 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61728 5 3 8 11 0 8 9 3 3 9 -1 auto 21.9 MiB 0.00 24 27 21 6 0 60.3 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 3.5791e-05 2.5977e-05 0.000240831 0.000201092 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00270512 0.00243979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_3bit.blif common 0.52 vpr 60.61 MiB -1 -1 -1 -1 2 0.06 -1 -1 35400 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62060 7 4 12 16 0 11 12 3 3 9 -1 auto 22.3 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 4.7612e-05 3.9433e-05 0.000326091 0.000287024 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00528941 0.00513278 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_4bit.blif common 0.64 vpr 60.55 MiB -1 -1 -1 -1 2 0.07 -1 -1 35520 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62008 9 5 15 20 0 14 15 3 3 9 -1 auto 22.2 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 8.1588e-05 7.0424e-05 0.000516653 0.000461489 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.01 0.00432254 0.00385687 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml rca_5bit.blif common 0.56 vpr 60.67 MiB -1 -1 -1 -1 3 0.07 -1 -1 35440 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62124 11 6 19 25 0 17 18 3 3 9 -1 auto 22.1 MiB 0.01 51 64 33 24 7 60.7 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 5.6728e-05 4.4391e-05 0.000433977 0.000387108 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00412344 0.0036326 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt index 853ef78bd3a..33183dc0a9f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.29 vpr 58.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59448 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.6 MiB 0.00 0 3 0 0 3 58.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.35e-05 7.476e-06 9.9741e-05 6.9647e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00158 0.00150277 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.31 vpr 58.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59404 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.3 MiB 0.00 0 3 0 0 3 58.0 MiB 0.00 0.00 nan 0 0 nan 0.00 1.9235e-05 1.1306e-05 9.7577e-05 6.3163e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00153532 0.00145564 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.30 vpr 58.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59472 6 1 7 8 0 7 8 3 3 9 -1 auto 19.6 MiB 0.00 21 21 14 7 0 58.1 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.8514e-05 2.102e-05 0.000170414 0.00013803 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00176222 0.00167853 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.28 vpr 58.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59628 6 1 7 8 0 7 8 3 3 9 -1 auto 19.8 MiB 0.00 21 21 14 7 0 58.2 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.2171e-05 1.4899e-05 0.000148119 0.000118181 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00158746 0.00149915 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.35 vpr 58.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59444 5 1 6 7 0 6 7 3 3 9 -1 auto 19.6 MiB 0.00 18 18 13 5 0 58.1 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.235e-05 1.6891e-05 0.00016969 0.000139695 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.001707 0.00162633 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.36 vpr 57.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59328 5 1 6 7 0 6 7 3 3 9 -1 auto 19.5 MiB 0.00 18 18 13 5 0 57.9 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.3308e-05 1.8079e-05 0.000169741 0.000137603 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00174494 0.0016591 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml const_true.blif common 0.33 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3821e-05 7.858e-06 8.9635e-05 6.0426e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00127569 0.00120513 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61760 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.0 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2203e-05 6.662e-06 7.9048e-05 5.258e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00167909 0.00160437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml always_true.blif common 0.30 vpr 60.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61712 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.3 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 3.2696e-05 2.3426e-05 0.000197822 0.000159059 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.0018336 0.0017293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 6 1 7 8 0 7 8 3 3 9 -1 auto 22.3 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.7376e-05 1.9376e-05 0.000172772 0.000138442 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00173443 0.0016423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.26 vpr 60.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61804 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.4 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.1966e-05 1.6158e-05 0.000132177 0.000102284 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00191949 0.00184253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.5373e-05 1.8911e-05 0.000175189 0.000138808 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00175813 0.00166803 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index 34014839d66..eaf5555874c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 1.80 vpr 64.59 MiB 0.05 9920 -1 -1 4 0.20 -1 -1 33316 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66140 11 30 262 292 2 110 54 7 7 49 clb auto 25.5 MiB 0.13 437 1482 306 1120 56 64.6 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000643567 0.000574681 0.0143423 0.0131271 -1 -1 -1 -1 12 342 4 1.07788e+06 700622 -1 -1 0.19 0.089611 0.0789696 2680 3516 -1 329 3 168 254 12149 6156 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0184131 0.0175473 - x_uniform_y_gaussian.xml stereovision3.v common 1.90 vpr 64.60 MiB 0.07 10112 -1 -1 4 0.20 -1 -1 33352 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66152 11 30 262 292 2 110 54 7 7 49 clb auto 25.5 MiB 0.13 407 2196 418 1692 86 64.6 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000658043 0.000585568 0.0188587 0.0171531 -1 -1 -1 -1 12 297 4 1.07788e+06 700622 -1 -1 0.25 0.0992671 0.0872902 2680 3516 -1 290 2 161 238 9382 4536 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0180057 0.0172294 - x_gaussian_y_gaussian.xml stereovision3.v common 2.15 vpr 64.69 MiB 0.06 9984 -1 -1 4 0.20 -1 -1 33348 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66244 11 30 262 292 2 110 54 7 7 49 clb auto 25.6 MiB 0.13 454 1584 320 1205 59 64.7 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000634493 0.000563945 0.0146242 0.0133184 -1 -1 -1 -1 14 366 11 1.07788e+06 700622 -1 -1 0.52 0.179464 0.155257 2680 3516 -1 348 15 235 399 18124 8998 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.00 -1 -1 0.00 0.0336258 0.0306404 - x_delta_y_uniform.xml stereovision3.v common 2.15 vpr 65.34 MiB 0.06 10036 -1 -1 4 0.19 -1 -1 33492 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66908 11 30 262 292 2 110 54 7 7 49 clb auto 25.5 MiB 0.13 447 1584 304 1234 46 65.3 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.00060675 0.000538932 0.0145363 0.0132998 -1 -1 -1 -1 58 343 10 1.07788e+06 700622 -1 -1 0.55 0.240804 0.206885 2680 3516 -1 344 2 158 235 10766 5342 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.017128 0.0164094 - x_delta_y_delta.xml stereovision3.v common 2.08 vpr 64.78 MiB 0.07 10108 -1 -1 4 0.21 -1 -1 33260 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66336 11 30 262 292 2 110 54 7 7 49 clb auto 25.6 MiB 0.12 507 2196 485 1634 77 64.8 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000513893 0.000456075 0.0159956 0.0145097 -1 -1 -1 -1 54 397 16 1.07788e+06 700622 -1 -1 0.50 0.221994 0.188707 2680 3516 -1 391 16 432 703 33205 16363 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.00 -1 -1 0.00 0.0309187 0.0279413 - x_uniform_y_delta.xml stereovision3.v common 2.38 vpr 65.23 MiB 0.06 9988 -1 -1 4 0.20 -1 -1 33480 -1 -1 13 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66796 11 30 262 292 2 110 54 7 7 49 clb auto 25.5 MiB 0.11 434 2604 541 1982 81 65.2 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000790777 0.00071626 0.0195938 0.0177623 -1 -1 -1 -1 34 315 15 1.07788e+06 700622 -1 -1 0.64 0.293892 0.25135 2680 3516 -1 312 15 303 587 23249 9988 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.11 0.01 -1 -1 0.01 0.0358566 0.0326766 + x_gaussian_y_uniform.xml stereovision3.v common 1.83 vpr 66.90 MiB 0.07 10496 -1 -1 4 0.18 -1 -1 36452 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68504 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.20 415 2196 413 1711 72 66.9 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.0007561 0.000646489 0.0218848 0.0192021 -1 -1 -1 -1 12 302 11 1.07788e+06 700622 -1 -1 0.20 0.128028 0.113742 2680 3516 -1 297 3 164 241 11232 5767 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0191965 0.0182163 + x_uniform_y_gaussian.xml stereovision3.v common 1.88 vpr 67.18 MiB 0.07 10624 -1 -1 4 0.21 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 11 30 262 292 2 110 54 7 7 49 clb auto 28.1 MiB 0.13 404 2298 458 1774 66 67.2 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.00 0.000687045 0.000583062 0.0174363 0.0155371 -1 -1 -1 -1 12 308 8 1.07788e+06 700622 -1 -1 0.31 0.110517 0.0976349 2680 3516 -1 297 3 168 247 11340 5786 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0178597 0.0169935 + x_gaussian_y_gaussian.xml stereovision3.v common 1.87 vpr 66.84 MiB 0.06 10496 -1 -1 4 0.16 -1 -1 36536 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68444 11 30 262 292 2 110 54 7 7 49 clb auto 27.9 MiB 0.18 410 2298 443 1773 82 66.8 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000756768 0.000647761 0.0255781 0.0225686 -1 -1 -1 -1 14 303 4 1.07788e+06 700622 -1 -1 0.40 0.162052 0.141633 2680 3516 -1 295 3 165 244 11438 5780 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0211596 0.0200797 + x_delta_y_uniform.xml stereovision3.v common 1.95 vpr 67.15 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36504 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68764 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.14 450 3012 620 2301 91 67.2 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000754694 0.000686961 0.028 0.0247412 -1 -1 -1 -1 48 342 3 1.07788e+06 700622 -1 -1 0.49 0.268135 0.232895 2680 3516 -1 342 3 170 251 11060 5468 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0196307 0.0186303 + x_delta_y_delta.xml stereovision3.v common 2.11 vpr 67.59 MiB 0.07 10496 -1 -1 4 0.22 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69212 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.13 519 3012 615 2292 105 67.6 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000782235 0.000651544 0.0273675 0.0237579 -1 -1 -1 -1 54 442 17 1.07788e+06 700622 -1 -1 0.52 0.268766 0.234157 2680 3516 -1 431 4 215 308 16404 8615 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0214181 0.0202532 + x_uniform_y_delta.xml stereovision3.v common 2.05 vpr 67.14 MiB 0.07 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68756 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.15 435 2502 457 1952 93 67.1 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000965335 0.000843275 0.027473 0.0239971 -1 -1 -1 -1 34 323 16 1.07788e+06 700622 -1 -1 0.51 0.30529 0.26214 2680 3516 -1 317 16 376 682 28098 12512 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0352499 0.0319547 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt index 45783bae7b7..a4fce4cf22f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.81 vpr 63.86 MiB 0.06 9972 -1 -1 4 0.20 -1 -1 33444 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65396 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.09 425 2049 385 1607 57 63.9 MiB 0.03 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000539136 0.000477079 0.0137959 0.0125271 -1 -1 -1 -1 8 277 16 1.07788e+06 1.02399e+06 -1 -1 0.23 0.0995243 0.0866078 2100 3116 -1 273 21 567 1118 57694 28121 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.0377719 0.0335488 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.77 vpr 64.53 MiB 0.07 9928 -1 -1 4 0.20 -1 -1 33420 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66080 11 30 262 292 2 99 60 7 7 49 clb auto 24.7 MiB 0.08 437 1698 295 1347 56 64.5 MiB 0.03 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000564734 0.000501615 0.0121215 0.0110071 -1 -1 -1 -1 12 311 21 1.07788e+06 1.02399e+06 -1 -1 0.20 0.103275 0.0897267 2100 3116 -1 280 16 541 967 52659 26082 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.0337495 0.0305254 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.73 vpr 64.50 MiB 0.07 9852 -1 -1 4 0.19 -1 -1 33472 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66048 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 458 2049 322 1664 63 64.5 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.00067398 0.000608186 0.0192321 0.0176286 -1 -1 -1 -1 14 304 18 1.07788e+06 1.02399e+06 -1 -1 0.18 0.09714 0.0842011 2100 3116 -1 308 19 560 1062 59748 29836 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.06 0.00 -1 -1 0.00 0.0318622 0.028394 + timing/k6_N10_mem32K_40nm.xml stereovision3.v common 2.02 vpr 67.00 MiB 0.08 10496 -1 -1 4 0.20 -1 -1 36452 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68608 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.11 419 1815 318 1436 61 67.0 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000706488 0.000606458 0.0228093 0.0209659 -1 -1 -1 -1 8 283 18 1.07788e+06 1.02399e+06 -1 -1 0.38 0.186498 0.171178 2100 3116 -1 280 18 572 1139 59841 29637 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.0346595 0.0310733 + nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 2.04 vpr 66.32 MiB 0.07 10496 -1 -1 4 0.26 -1 -1 36580 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67916 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 428 1698 248 1401 49 66.3 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000764131 0.000648712 0.0183265 0.0161998 -1 -1 -1 -1 10 297 21 1.07788e+06 1.02399e+06 -1 -1 0.45 0.176554 0.15406 2100 3116 -1 286 18 539 1058 53794 27022 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.0402826 0.0356284 + nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.99 vpr 66.21 MiB 0.09 10368 -1 -1 4 0.24 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67800 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 447 1815 292 1481 42 66.2 MiB 0.07 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.00090328 0.000782565 0.0181809 0.0161296 -1 -1 -1 -1 16 296 17 1.07788e+06 1.02399e+06 -1 -1 0.25 0.115099 0.100427 2100 3116 -1 300 17 545 1102 57605 27890 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.12 0.01 -1 -1 0.00 0.0397962 0.0356125 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt index 0367bfe7230..e6884fa004e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 5.37 vpr 63.99 MiB 0.10 9968 -1 -1 4 0.20 -1 -1 33400 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65528 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 421 2049 269 1715 65 64.0 MiB 1.89 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.00057386 0.000512781 0.0146636 0.0132498 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 1.13 0.0484194 0.0434429 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 6.17 vpr 66.89 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36612 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68492 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.11 425 2283 406 1804 73 66.9 MiB 2.36 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.00076202 0.000633481 0.0213386 0.0169977 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 1.35 0.0886305 0.079884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt index acbedece480..b4a9052cd04 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 1.99 vpr 60.15 MiB 0.06 9668 -1 -1 4 0.17 -1 -1 33476 -1 -1 13 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61592 11 30 262 292 2 110 54 6 6 36 clb auto 20.4 MiB 0.13 423 4182 3462 630 90 60.1 MiB 0.08 0.00 2.57043 -171.237 -2.57043 2.32238 0.05 0.00089131 0.000815522 0.0388204 0.0350413 -1 -1 -1 -1 32 775 32 862304 700622 60095.3 1669.31 0.30 0.160018 0.138863 2828 10782 -1 624 11 377 562 17524 7204 2.60136 2.32286 -183.634 -2.60136 0 0 72928.5 2025.79 0.01 0.04 0.01 -1 -1 0.01 0.0300283 0.0274063 + k6_frac_N10_40nm.xml stereovision3.v common 2.01 vpr 61.71 MiB 0.06 10112 -1 -1 4 0.22 -1 -1 36708 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63196 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 442 4182 3410 664 108 61.7 MiB 0.07 0.00 2.55648 -171.707 -2.55648 2.31607 0.04 0.000697499 0.000590032 0.035108 0.0301305 -1 -1 -1 -1 36 688 16 862304 700622 64877.6 1802.15 0.32 0.199199 0.171554 2900 12076 -1 568 12 312 493 15436 6065 2.62572 2.28031 -177.78 -2.62572 0 0 80896.3 2247.12 0.00 0.04 0.02 -1 -1 0.00 0.0300653 0.0274931 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt index ce0ea8dc839..8d2903c2d48 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 14.82 vpr 69.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70652 64 39 1935 1974 1 1077 541 23 23 529 clb auto 28.8 MiB 0.46 10085 137127 36539 98027 2561 69.0 MiB 1.29 0.02 7.41831 -1418.64 -7.41831 7.41831 0.93 0.00542256 0.0043447 0.391364 0.336096 -1 -1 -1 -1 22 12754 28 983127 976439 735934. 1391.18 8.01 1.19718 1.03739 35322 121345 -1 11109 19 6608 23845 1462488 382373 7.14816 7.14816 -1474.13 -7.14816 0 0 927497. 1753.30 0.20 0.73 0.16 -1 -1 0.20 0.232845 0.209152 - k4_N4_90nm.xml ex5p.blif common 30.39 vpr 64.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66072 8 63 1072 1135 0 894 437 22 22 484 clb auto 25.1 MiB 0.32 11802 104828 31007 71723 2098 64.5 MiB 0.99 0.02 6.54351 -290.193 -6.54351 nan 0.80 0.00510866 0.00465601 0.247547 0.215944 -1 -1 -1 -1 34 15886 35 891726 815929 1.00654e+06 2079.64 24.52 1.13626 0.978644 45600 169672 -1 13479 18 7616 26985 2968727 818222 6.43932 nan -293.77 -6.43932 0 0 1.27783e+06 2640.15 0.20 0.82 0.22 -1 -1 0.20 0.123294 0.109373 - k4_N4_90nm.xml s298.blif common 53.24 vpr 70.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 72636 4 6 1942 1948 1 1169 590 27 27 729 clb auto 30.8 MiB 0.42 13579 163808 47993 114862 953 70.9 MiB 1.53 0.02 12.0403 -94.3066 -12.0403 12.0403 1.25 0.00553281 0.00453291 0.434948 0.364606 -1 -1 -1 -1 24 19358 45 1.39333e+06 1.29301e+06 1.12265e+06 1539.99 44.05 2.01627 1.70098 54650 192211 -1 16862 23 9147 49878 4855038 894292 11.751 11.751 -96.5615 -11.751 0 0 1.47093e+06 2017.74 0.26 1.56 0.23 -1 -1 0.26 0.263955 0.229636 + k4_N4_90nm.xml diffeq.blif common 18.17 vpr 71.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72740 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.53 10472 141533 36950 100839 3744 71.0 MiB 1.46 0.02 7.46482 -1369.01 -7.46482 7.46482 0.64 0.00605549 0.00528423 0.429203 0.364085 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.91 2.29628 1.96589 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.03 0.83 0.15 -1 -1 0.03 0.252853 0.225541 + k4_N4_90nm.xml ex5p.blif common 20.35 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68624 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.32 12004 99857 28319 69545 1993 67.0 MiB 1.07 0.02 6.86459 -313.968 -6.86459 nan 0.52 0.0035933 0.00315668 0.2475 0.211473 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 14.36 0.89434 0.759948 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.08 1.43 0.30 -1 -1 0.08 0.237816 0.212077 + k4_N4_90nm.xml s298.blif common 19.44 vpr 73.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74984 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.0 MiB 0.49 13813 156389 45768 109723 898 73.2 MiB 1.80 0.03 12.2682 -96.384 -12.2682 12.2682 0.93 0.0106993 0.00945176 0.491739 0.389383 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 10.93 1.63745 1.34189 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.10 1.48 0.31 -1 -1 0.10 0.297955 0.263351 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt index 7b4d40ad61c..4db936a1dd3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.89 vpr 67.16 MiB 0.08 10336 -1 -1 5 0.21 -1 -1 33252 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68768 11 30 313 321 2 114 55 7 7 49 clb auto 27.4 MiB 0.33 439 1511 357 1028 126 67.2 MiB 0.07 0.00 4.62621 0 0 4.30823 0.00 0.00078995 0.00071828 0.0210334 0.0197012 -1 -1 -1 -1 639 5.91667 232 2.14815 379 726 16470 4839 1.07788e+06 754516 219490. 4479.39 10 5100 32136 -1 4.76665 4.41703 0 0 -164.948 -1.707 0.04 -1 -1 67.2 MiB 0.16 0.162181 0.155936 67.2 MiB -1 0.05 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.78 vpr 69.28 MiB 0.09 10496 -1 -1 5 0.19 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70944 11 30 313 321 2 114 55 7 7 49 clb auto 29.8 MiB 0.39 459 2031 574 1374 83 69.3 MiB 0.03 0.00 4.6413 0 0 4.31525 0.00 0.000635584 0.000552586 0.0173645 0.0155707 -1 -1 -1 -1 570 5.27778 228 2.11111 239 439 10467 3202 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 69.3 MiB 0.14 0.147679 0.140851 69.3 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt index aa786b4ddf8..19fe5d4556f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt index 20374de3e27..8285cf5d7b5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 2.74 vpr 66.21 MiB 0.07 9628 -1 -1 3 0.35 -1 -1 34640 -1 -1 66 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67804 99 130 363 493 1 250 296 12 12 144 clb auto 27.0 MiB 0.19 914 65372 15140 25128 25104 66.2 MiB 0.10 0.00 34 2054 14 5.66058e+06 4.105e+06 317980. 2208.19 0.75 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 2.66 vpr 68.27 MiB 0.06 9984 -1 -1 3 0.36 -1 -1 39780 -1 -1 66 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69908 99 130 363 493 1 250 296 12 12 144 clb auto 29.2 MiB 0.21 805 57484 15208 21002 21274 68.3 MiB 0.11 0.00 40 1774 10 5.66058e+06 4.105e+06 360333. 2502.31 0.52 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt index 7d08de7d57f..735a18dab2b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.18 vpr 64.60 MiB 0.08 9968 -1 -1 4 0.19 -1 -1 33248 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66148 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00212704 0.00202414 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.45 vpr 66.93 MiB 0.09 10368 -1 -1 4 0.22 -1 -1 36756 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68532 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00571426 0.00556672 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt index a85975233a5..402ade22624 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.29 vpr 64.50 MiB 0.08 9892 -1 -1 4 0.20 -1 -1 33360 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66052 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 439 1932 239 1639 54 64.5 MiB 0.03 0.00 2.45489 -180.196 -2.45489 2.33213 0.07 0.000557675 0.000497069 0.0140116 0.0127239 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0161027 0.014718 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.29 vpr 66.33 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36632 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67920 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.05 0.000892007 0.00076546 0.0179963 0.0157273 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0202445 0.0178347 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt index c26de4c60a8..8bf865796ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 0.77 vpr 58.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59976 11 11 59 70 0 48 26 4 4 16 clb auto 19.2 MiB 0.04 179 634 146 488 0 58.6 MiB 0.01 0.00 2.51353 -20.6332 -2.51353 nan 0.01 0.000235015 0.000215515 0.00574618 0.00532029 -1 -1 -1 -1 30 199 15 215576 215576 18771.3 1173.21 0.19 0.061719 0.0519663 1016 3020 -1 198 17 257 591 8958 4396 2.73234 nan -23.1489 -2.73234 0 0 22855.5 1428.47 0.01 0.02 0.01 -1 -1 0.01 0.0122134 0.0110341 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 vpr 21.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 22068 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.1 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml mult_5x6.blif common 0.57 vpr 60.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62456 11 11 59 70 0 48 26 4 4 16 clb auto 22.0 MiB 0.04 179 862 260 602 0 61.0 MiB 0.01 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000234107 0.000208327 0.0069198 0.00625105 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.10 0.0507337 0.0443992 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.02 0.00 -1 -1 0.00 0.0119559 0.010883 + k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.07 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23940 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt index 0266ed5293a..af7706738c0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.29 vpr 62.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64140 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 20 30 10 17 3 62.6 MiB 0.00 0.00 0.645658 -3.51726 -0.645658 0.571 0.01 4.8438e-05 3.4201e-05 0.00152576 0.00147521 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00152576 0.00147521 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml multiclock.blif common 0.24 vpr 64.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66340 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.8 MiB 0.01 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 6.4699e-05 4.5848e-05 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt index 457652c3ee3..25609b75a68 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.59 vpr 976.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999904 10 10 168 178 1 68 30 11 8 88 io auto 953.3 MiB 0.63 393 628 105 491 32 976.5 MiB 0.06 0.00 6.51193 -69.1178 -6.51193 6.51193 3.11 0.000480842 0.000431377 0.0112949 0.0105397 -1 -1 -1 -1 20 893 28 0 0 100248. 1139.18 0.66 0.109748 0.0976349 11180 23751 -1 831 19 496 1987 121384 60113 6.91414 6.91414 -78.1319 -6.91414 0 0 150556. 1710.86 0.02 0.09 0.07 -1 -1 0.02 0.0302143 0.0267735 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 38.84 vpr 976.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1000004 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.62 380 628 91 496 41 976.6 MiB 0.06 0.00 6.52338 -69.1003 -6.52338 6.52338 3.24 0.000527135 0.000462877 0.0115671 0.0108087 -1 -1 -1 -1 30 673 12 0 0 144567. 1642.81 0.58 0.0925956 0.0823255 11730 32605 -1 585 9 216 698 45031 21119 6.8993 6.8993 -73.7008 -6.8993 0 0 194014. 2204.70 0.03 0.06 0.10 -1 -1 0.03 0.0207007 0.0188861 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 40.21 vpr 976.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999952 10 10 168 178 1 68 30 11 8 88 io auto 953.3 MiB 0.62 369 766 101 608 57 976.5 MiB 0.07 0.00 6.29548 -69.1499 -6.29548 6.29548 3.96 0.000642065 0.000578628 0.0144046 0.0134125 -1 -1 -1 -1 20 979 39 0 0 100248. 1139.18 1.54 0.210388 0.179459 11180 23751 -1 730 15 326 1149 70174 36157 6.70251 6.70251 -75.6785 -6.70251 0 0 125464. 1425.72 0.02 0.07 0.07 -1 -1 0.02 0.0262708 0.0234853 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 39.65 vpr 976.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999996 10 10 168 178 1 68 30 11 8 88 io auto 953.5 MiB 0.62 393 720 70 599 51 976.6 MiB 0.06 0.00 6.29266 -69.3194 -6.29266 6.29266 3.95 0.000492354 0.000450911 0.0121985 0.0113493 -1 -1 -1 -1 30 792 16 0 0 144567. 1642.81 0.52 0.0829003 0.0732049 11730 32605 -1 644 15 284 1326 83485 37502 6.72776 6.72776 -73.9475 -6.72776 0 0 194014. 2204.70 0.03 0.07 0.10 -1 -1 0.03 0.0265404 0.0237185 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 40.74 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.79 0.000585035 0.000506509 0.0125856 0.0113967 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.17 0.202681 0.177336 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.09 0.08 -1 -1 0.01 0.0322374 0.0298184 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 42.57 vpr 978.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001668 10 10 168 178 1 68 30 11 8 88 io auto 955.1 MiB 0.58 356 628 86 501 41 978.2 MiB 0.08 0.00 6.32784 -69.1369 -6.32784 6.32784 2.79 0.00106817 0.000941606 0.0173949 0.0157097 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.41 0.24274 0.212439 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.08 0.08 -1 -1 0.01 0.0393492 0.0368597 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 41.18 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.77 378 628 92 504 32 978.5 MiB 0.06 0.00 6.37842 -68.9795 -6.37842 6.37842 3.93 0.000461318 0.000398366 0.0135017 0.0123478 -1 -1 -1 -1 30 740 27 0 0 144567. 1642.81 1.27 0.212409 0.18717 11730 32605 -1 579 10 219 802 50034 22946 6.80801 6.80801 -73.0986 -6.80801 0 0 194014. 2204.70 0.01 0.06 0.10 -1 -1 0.01 0.0272644 0.0255028 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 43.49 vpr 978.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002044 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.67 353 582 71 475 36 978.6 MiB 0.10 0.00 6.2342 -69.2052 -6.2342 6.2342 4.26 0.00126519 0.00120018 0.0174025 0.0162066 -1 -1 -1 -1 22 762 19 0 0 110609. 1256.92 0.57 0.121021 0.108951 11258 24748 -1 710 14 413 1547 91286 47129 6.80216 6.80216 -76.023 -6.80216 0 0 134428. 1527.59 0.01 0.08 0.05 -1 -1 0.01 0.0301878 0.0279201 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt index 2d257ead4b6..de612c1c661 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 39.27 vpr 976.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 999936 10 10 168 178 1 68 30 11 8 88 io auto 953.4 MiB 0.61 393 628 105 491 32 976.5 MiB 0.06 0.00 6.51193 -69.1178 -6.51193 6.51193 3.33 0.000569129 0.000496002 0.012275 0.0114625 -1 -1 -1 -1 20 893 28 0 0 100248. 1139.18 0.66 0.116406 0.101755 11180 23751 -1 831 19 496 1987 121384 60113 6.91414 6.91414 -78.1319 -6.91414 0 0 150556. 1710.86 0.02 0.09 0.07 -1 -1 0.02 0.0312385 0.0276729 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 36.90 vpr 976.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1000112 10 10 168 178 1 68 30 11 8 88 io auto 953.7 MiB 0.60 380 628 91 496 41 976.7 MiB 0.06 0.00 6.52338 -69.1003 -6.52338 6.52338 3.10 0.000501046 0.000450601 0.0117982 0.0109963 -1 -1 -1 -1 30 673 12 0 0 144567. 1642.81 0.47 0.0799941 0.0704629 11730 32605 -1 585 9 216 698 45031 21119 6.8993 6.8993 -73.7008 -6.8993 0 0 194014. 2204.70 0.03 0.06 0.10 -1 -1 0.03 0.0206622 0.0188402 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 41.99 vpr 978.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001688 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.85 385 628 76 517 35 978.2 MiB 0.09 0.00 6.37842 -68.9926 -6.37842 6.37842 2.49 0.000740479 0.000647957 0.0145497 0.0133659 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.45 0.22055 0.192568 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.11 0.10 -1 -1 0.01 0.0358167 0.033477 + stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 41.03 vpr 978.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001836 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.66 356 628 86 501 41 978.4 MiB 0.10 0.00 6.32784 -69.1369 -6.32784 6.32784 2.55 0.000491141 0.000429611 0.0148781 0.0136279 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.47 0.229896 0.203057 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.11 0.09 -1 -1 0.01 0.0316333 0.0293122 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt index 02e9ce0dfc9..be79764ceb1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.11 vpr 74.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76128 8 63 1072 1135 0 619 135 12 12 144 clb auto 34.5 MiB 2.33 6183 12245 2318 9041 886 74.3 MiB 0.42 0.01 4.99539 -218.829 -4.99539 nan 0.40 0.00404212 0.00341765 0.184837 0.163351 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.189101 0.167214 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 4.01 vpr 74.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 76144 8 63 1072 1135 0 619 135 12 12 144 clb auto 34.3 MiB 2.38 6325 11326 2120 8412 794 74.4 MiB 0.36 0.01 4.96391 -216.681 -4.96391 nan 0.38 0.00390508 0.00360049 0.150898 0.136289 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.155447 0.140327 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 9.78 vpr 78.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 79868 8 63 1072 1135 0 619 135 27 27 729 -1 auto 34.2 MiB 2.05 6780 22625 6869 14375 1381 77.8 MiB 0.53 0.01 5.57619 -254.596 -5.57619 nan 3.24 0.00298107 0.00257554 0.222411 0.19574 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.226597 0.199503 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 10.33 vpr 78.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 79920 8 63 1072 1135 0 619 135 27 27 729 -1 auto 34.4 MiB 2.32 6916 70425 20372 45422 4631 78.0 MiB 1.06 0.02 5.61138 -254.037 -5.61138 nan 3.32 0.00308249 0.00275482 0.219018 0.196554 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.223523 0.200574 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.26 vpr 76.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78288 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.83 6246 12245 2336 8854 1055 76.5 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.27 0.00393519 0.00333322 0.167205 0.141172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.170495 0.143929 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.34 vpr 76.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78408 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.32 6248 12409 2316 9051 1042 76.6 MiB 0.27 0.01 5.00015 -217.921 -5.00015 nan 0.18 0.00183948 0.00156955 0.109821 0.0973753 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.11472 0.101715 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 6.81 vpr 76.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78560 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.45 6557 16051 3559 11939 553 76.7 MiB 0.47 0.01 5.39652 -231.823 -5.39652 nan 1.67 0.00368316 0.00300979 0.191413 0.165252 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.196386 0.169658 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.69 vpr 76.65 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78492 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.4 MiB 2.51 6642 53385 10847 39555 2983 76.7 MiB 1.06 0.02 5.30857 -236.309 -5.30857 nan 1.91 0.00201874 0.00161249 0.24975 0.219272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.258981 0.227848 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt index 894bbbd344b..b0056cc1abc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.45 vpr 64.46 MiB 0.06 10080 -1 -1 4 0.19 -1 -1 33316 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66004 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.08 439 1932 239 1639 54 64.5 MiB 0.03 0.00 2.45489 -180.196 -2.45489 2.33213 0.08 0.000661458 0.000589394 0.0146171 0.0132586 -1 -1 -1 -1 20 684 34 1.07788e+06 1.02399e+06 49980.0 1020.00 0.62 0.239102 0.203363 2664 9102 -1 585 25 992 2191 68660 23567 2.62928 2.46785 -187.223 -2.62928 0 0 65453.8 1335.79 0.02 0.09 0.01 -1 -1 0.02 0.0513972 0.044921 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.86 vpr 66.93 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68536 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.9 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.00072366 0.000614909 0.0157761 0.0136171 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.27 0.140412 0.11741 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.06 0.01 -1 -1 0.00 0.0578011 0.0529737 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt index d972ea27949..c15f8828261 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.51 vpr 60.07 MiB -1 -1 -1 -1 0 0.02 -1 -1 30028 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61512 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 0 3 0 0 3 60.1 MiB 0.01 0.00 nan 0 0 nan 0.00 1.7627e-05 1.1573e-05 0.000113513 8.1967e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.01 0.00151028 0.00142155 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.50 vpr 60.09 MiB -1 -1 -1 -1 0 0.02 -1 -1 30092 -1 -1 1 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61532 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.4 MiB 0.01 0 3 0 0 3 60.1 MiB 0.01 0.00 nan 0 0 nan 0.00 3.6083e-05 2.8637e-05 0.000127329 9.3377e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 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a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 6a4e552e822..1f6be016ab1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 5.32 vpr 65.56 MiB 0.06 9324 -1 -1 3 0.35 -1 -1 34640 -1 52944 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67136 99 130 363 493 1 251 298 12 12 144 clb auto 26.3 MiB 0.14 892 61988 19791 31117 11080 65.6 MiB 0.20 0.00 2.45187 -222.514 -2.45187 2.45187 0.36 0.000915265 0.000857739 0.0611213 0.0573235 -1 -1 -1 -1 42 1632 14 5.66058e+06 4.21279e+06 345702. 2400.71 1.98 0.420146 0.379604 12810 66778 -1 1532 10 491 638 43042 14380 2.64362 2.64362 -241.091 -2.64362 0 0 434679. 3018.61 0.14 0.06 0.07 -1 -1 0.14 0.0352631 0.033178 0.008708 0.223 0.06667 0.7103 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 13.86 vpr 69.06 MiB 0.04 9360 -1 -1 15 0.45 -1 -1 34776 -1 54676 38 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70720 162 96 999 932 1 689 301 16 16 256 mult_36 auto 29.7 MiB 0.41 5715 87997 27324 53359 7314 69.1 MiB 0.74 0.01 21.0193 -1891.98 -21.0193 21.0193 0.81 0.00444774 0.00422894 0.323103 0.304448 -1 -1 -1 -1 46 12696 36 1.21132e+07 4.02797e+06 727248. 2840.81 6.60 1.22942 1.13708 24972 144857 -1 9788 21 3242 6502 928862 268718 22.8323 22.8323 -2032.58 -22.8323 0 0 934704. 3651.19 0.32 0.43 0.16 -1 -1 0.32 0.182261 0.17068 0.007695 0.3421 0.01642 0.6414 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.79 vpr 67.81 MiB 0.06 9856 -1 -1 3 0.37 -1 -1 39772 -1 54808 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.13 821 70943 24958 34400 11585 67.8 MiB 0.24 0.00 2.51136 -219.195 -2.51136 2.51136 0.28 0.000896235 0.000803075 0.0731146 0.0664864 -1 -1 -1 -1 40 1499 25 5.66058e+06 4.21279e+06 333335. 2314.82 1.63 0.35542 0.319058 12666 64609 -1 1442 10 553 749 42115 14455 2.64494 2.64494 -235.699 -2.64494 0 0 419432. 2912.72 0.02 0.06 0.11 -1 -1 0.02 0.0374155 0.0350957 0.008441 0.2001 0.06777 0.7321 + k6_frac_N10_mem32K_40nm.xml diffeq1.v common 16.21 vpr 71.75 MiB 0.06 9856 -1 -1 15 0.50 -1 -1 38288 -1 56228 38 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73476 162 96 999 932 1 689 301 16 16 256 mult_36 auto 32.3 MiB 0.49 5426 96061 33445 54809 7807 71.8 MiB 1.03 0.02 21.3991 -1811.48 -21.3991 21.3991 0.51 0.00504368 0.00468153 0.493175 0.461597 -1 -1 -1 -1 56 11482 33 1.21132e+07 4.02797e+06 870502. 3400.40 8.42 2.47741 2.31569 26504 172068 -1 9223 22 3083 6041 811453 269172 22.8885 22.8885 -1951.66 -22.8885 0 0 1.11200e+06 4343.75 0.07 0.47 0.29 -1 -1 0.07 0.221232 0.208061 0.007874 0.3571 0.01689 0.626 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt index 84ecf217097..d6f9144a21f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.42 vpr 64.63 MiB 0.08 10092 -1 -1 4 0.21 -1 -1 33404 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66180 11 30 262 292 2 99 60 7 7 49 clb auto 24.9 MiB 0.09 421 2049 269 1715 65 64.6 MiB 0.04 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000642825 0.000574377 0.0150724 0.0136437 -1 -1 -1 -1 424 4.46316 163 1.71579 617 1399 45810 10033 1.07788e+06 1.02399e+06 207176. 4228.08 16 4440 29880 -1 2.36464 2.27781 -179.43 -2.36464 0 0 0.03 -1 -1 64.6 MiB 0.06 0.0447701 0.039887 64.6 MiB -1 0.04 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.66 vpr 67.05 MiB 0.06 10172 -1 -1 5 0.18 -1 -1 33356 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68656 11 30 313 321 2 115 55 7 7 49 clb auto 27.3 MiB 0.32 466 2759 556 2108 95 67.0 MiB 0.06 0.00 2.67362 -172.647 -2.67362 2.30794 0.00 0.000887719 0.000807056 0.0300856 0.0276351 -1 -1 -1 -1 574 5.26606 231 2.11927 216 452 11450 3638 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 2.71877 2.35385 -178.475 -2.71877 0 0 0.04 -1 -1 67.0 MiB 0.03 0.057894 0.0532276 67.0 MiB -1 0.04 + k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 66.34 MiB 0.08 10496 -1 -1 4 0.22 -1 -1 36740 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.07 425 2283 406 1804 73 66.3 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000792071 0.00065667 0.0233552 0.0207856 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.3 MiB 0.07 0.0694098 0.0624777 66.3 MiB -1 0.01 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.84 vpr 69.28 MiB 0.07 10496 -1 -1 5 0.19 -1 -1 36360 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70940 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.48 448 1927 352 1502 73 69.3 MiB 0.05 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.00080657 0.000690329 0.0283624 0.0258806 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.06 -1 -1 69.3 MiB 0.04 0.0633117 0.0585851 69.3 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt index e9f8c264924..9c4fd28b84b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 38.30 vpr 86.88 MiB 0.47 29360 -1 -1 4 2.33 -1 -1 37992 -1 -1 169 193 5 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 88968 193 205 2863 2789 1 1374 572 20 20 400 memory auto 43.4 MiB 1.96 11201 252110 92751 131930 27429 84.4 MiB 2.44 0.03 4.45067 -2677.23 -4.45067 4.45067 1.78 0.00740583 0.00674714 0.935753 0.830726 -1 -1 -1 -1 80 22067 51 2.07112e+07 1.18481e+07 2.10510e+06 5262.74 22.74 5.25463 4.68017 53274 447440 -1 19298 17 5571 15462 1144445 252495 4.66289 4.66289 -2899.83 -4.66289 -11.7102 -0.360359 2.64606e+06 6615.15 0.68 0.62 0.38 -1 -1 0.68 0.376497 0.344469 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 29.83 vpr 86.25 MiB 0.45 29568 -1 -1 4 2.98 -1 -1 43168 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88324 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.0 MiB 2.27 10985 240245 81936 130873 27436 86.3 MiB 2.86 0.03 4.42447 -2617.73 -4.42447 4.42447 0.89 0.00871072 0.007701 1.03653 0.893245 -1 -1 -1 -1 78 21148 33 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 13.92 4.09327 3.61448 52874 439520 -1 19015 17 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.98 0.77 -1 -1 0.19 0.584807 0.525478 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt index 82ee8b5f85d..812f4d3bdb5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 2.28 vpr 69.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70720 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.53 4989 14482 2605 10909 968 69.1 MiB 0.29 0.01 4.15324 -188.164 -4.15324 nan 0.00 0.00281296 0.00243514 0.139942 0.124398 -1 -1 -1 -1 6805 14.9560 1830 4.02198 3625 14263 570126 87469 9.20055e+06 4.79657e+06 867065. 4423.80 19 18088 133656 -1 4.17843 nan -185.467 -4.17843 0 0 0.16 -1 -1 69.1 MiB 0.45 0.325496 0.291568 69.1 MiB -1 0.29 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.22 vpr 69.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70764 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.51 4989 14482 2605 10909 968 69.1 MiB 0.29 0.01 4.15324 -188.164 -4.15324 nan 0.00 0.00262456 0.00232451 0.12615 0.110723 -1 -1 -1 -1 6877 15.1143 1848 4.06154 3712 14523 564432 88116 9.20055e+06 4.79657e+06 867065. 4423.80 19 18088 133656 -1 4.14924 nan -185.7 -4.14924 0 0 0.15 -1 -1 69.1 MiB 0.40 0.298349 0.266584 69.1 MiB -1 0.30 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.96 vpr 71.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73224 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.52 4992 14048 2664 10357 1027 71.5 MiB 0.35 0.02 4.19211 -186.67 -4.19211 nan 0.00 0.00713555 0.00269028 0.139755 0.114328 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.22 -1 -1 71.5 MiB 0.32 0.294582 0.254721 71.5 MiB -1 0.05 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.24 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73336 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.64 4992 14048 2664 10357 1027 71.6 MiB 0.33 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00345084 0.002875 0.154792 0.13937 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.26 -1 -1 71.6 MiB 0.37 0.334856 0.303047 71.6 MiB -1 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt index 9e26968d0ac..ca94c478175 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.11 vpr 69.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70752 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.50 4981 18388 4106 12671 1611 69.1 MiB 0.33 0.01 3.67827 -162.703 -3.67827 nan 0.04 0.00316093 0.00267964 0.156067 0.137885 -1 -1 -1 -1 6929 15.2286 1856 4.07912 4031 16057 1191599 209386 9.20055e+06 4.79657e+06 701736. 3580.29 21 16332 105598 -1 4.26894 nan -186.127 -4.26894 0 0 0.12 -1 -1 69.1 MiB 0.45 0.320906 0.286349 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.11 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70696 8 63 748 811 0 455 160 14 14 196 clb auto 29.4 MiB 0.50 4947 14048 2843 10376 829 69.0 MiB 0.27 0.01 4.36787 -194.851 -4.36787 nan 0.00 0.00329553 0.00282923 0.129786 0.114331 -1 -1 -1 -1 7013 15.4132 1882 4.13626 4368 18266 702728 114564 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.35011 nan -200.403 -4.35011 0 0 0.12 -1 -1 69.0 MiB 0.41 0.312316 0.278054 69.0 MiB -1 0.23 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.39 vpr 69.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70752 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.50 4953 17954 4036 12536 1382 69.1 MiB 0.35 0.01 3.75278 -163.938 -3.75278 nan 0.07 0.0033402 0.00290592 0.147752 0.129486 -1 -1 -1 -1 7096 15.5956 1936 4.25495 3839 15635 1250449 222869 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.31984 nan -190.626 -4.31984 0 0 0.14 -1 -1 69.1 MiB 0.53 0.335395 0.295263 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.38 vpr 69.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70780 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.50 4953 17954 4036 12536 1382 69.1 MiB 0.33 0.01 3.75278 -163.938 -3.75278 nan 0.07 0.00358739 0.00315042 0.148074 0.130756 -1 -1 -1 -1 7096 15.5956 1936 4.25495 3839 15635 1250449 222869 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.31984 nan -190.626 -4.31984 0 0 0.14 -1 -1 69.1 MiB 0.56 0.339968 0.302409 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.33 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.53 4993 17086 3593 12286 1207 71.5 MiB 0.39 0.01 3.65588 -160.421 -3.65588 nan 0.05 0.00324947 0.00265148 0.171741 0.145172 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.19 -1 -1 71.5 MiB 0.65 0.403427 0.354208 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.06 vpr 71.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72900 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.61 4933 15350 2970 11325 1055 71.2 MiB 0.33 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00354772 0.00306723 0.134491 0.114487 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.2 MiB 0.37 0.342443 0.304101 71.2 MiB -1 0.04 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 4.12 vpr 71.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73084 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.46 5048 17520 3917 12196 1407 71.4 MiB 0.41 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.0055915 0.00450451 0.174816 0.150375 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.22 -1 -1 71.4 MiB 0.70 0.438594 0.389856 -1 -1 -1 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.79 vpr 71.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73092 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.34 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00371073 0.00310746 0.151921 0.128885 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.16 -1 -1 71.4 MiB 0.65 0.390878 0.342895 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt index 42d0070c39d..73afad51c48 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.98 vpr 69.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70736 8 63 748 811 0 455 160 14 14 196 clb auto 29.5 MiB 0.45 5081 14916 3009 10977 930 69.1 MiB 0.27 0.01 4.4281 -198.501 -4.4281 nan 0.00 0.00300537 0.00251178 0.118094 0.103153 -1 -1 -1 -1 6741 14.8154 1803 3.96264 3315 13570 497205 81432 9.20055e+06 4.79657e+06 787177. 4016.21 19 17112 118924 -1 4.40099 nan -202.066 -4.40099 0 0 0.13 -1 -1 69.1 MiB 0.34 0.282273 0.252167 69.1 MiB -1 0.26 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.02 vpr 69.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70816 8 63 748 811 0 455 160 14 14 196 clb auto 29.6 MiB 0.53 5081 14916 3009 10977 930 69.2 MiB 0.26 0.01 4.4281 -198.501 -4.4281 nan 0.00 0.00303209 0.00274882 0.116032 0.102412 -1 -1 -1 -1 6767 14.8725 1813 3.98462 3295 13377 489418 80231 9.20055e+06 4.79657e+06 787177. 4016.21 18 17112 118924 -1 4.40099 nan -201.997 -4.40099 0 0 0.13 -1 -1 69.2 MiB 0.33 0.270765 0.24325 69.2 MiB -1 0.28 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 2.09 vpr 71.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73036 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.3 MiB 0.32 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00299665 0.00251735 0.139481 0.119628 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.42 0.337391 0.298836 71.3 MiB -1 0.06 + k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.37 vpr 71.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73112 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.4 MiB 0.36 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00287338 0.00244407 0.145055 0.130505 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.23 -1 -1 71.4 MiB 0.57 0.403361 0.368877 71.4 MiB -1 0.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt index 8e0c47bf03f..d51a6534507 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 0.90 vpr 57.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58700 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 18.2 MiB 0.24 70 15 2 12 1 57.3 MiB 0.00 0.00 0.645672 -5.8162 -0.645672 0.645672 0.00 0.000120184 0.000109173 0.000865636 0.00080802 -1 -1 -1 -1 25 294 14 133321 74067 -1 -1 0.23 0.0266638 0.0220764 1252 5405 -1 287 14 116 116 21465 12891 1.98076 1.98076 -20.8107 -1.98076 0 0 -1 -1 0.01 0.02 0.00 -1 -1 0.01 0.0055322 0.00492928 + slicem.xml carry_chain.blif common 1.14 vpr 59.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61108 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 20.9 MiB 0.25 70 15 4 10 1 59.7 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000126011 0.000111009 0.000872338 0.000798258 -1 -1 -1 -1 25 262 18 133321 74067 -1 -1 0.48 0.0703731 0.0607281 1252 5405 -1 274 13 122 122 23159 13821 1.78919 1.78919 -18.223 -1.78919 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.00593831 0.00529293 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt index d6a3abf2024..2974b610be2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.46 vpr 56.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57772 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 17.6 MiB 0.01 31 35 6 27 2 56.4 MiB 0.01 0.00 0.212927 -2.22016 -0.212927 0.212927 0.00 5.0007e-05 3.8931e-05 0.000238974 0.000194906 -1 -1 -1 -1 4 28 4 59253.6 44440.2 -1 -1 0.06 0.0047932 0.00391937 184 632 -1 29 2 13 18 795 367 0.309802 0.309802 -2.85512 -0.309802 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00161011 0.00154347 + arch.xml ndff.blif common 0.30 vpr 59.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60508 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.6 MiB 0.00 31 59 13 43 3 59.1 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.5462e-05 2.8363e-05 0.000299521 0.0002448 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00397217 0.00338578 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00197845 0.00188555 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt index 282c80c20d3..936401071c3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.68 vpr 67.04 MiB 0.07 10084 -1 -1 5 0.18 -1 -1 33256 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68648 11 30 313 321 2 114 55 7 7 49 clb auto 27.3 MiB 0.34 439 1511 357 1028 126 67.0 MiB 0.04 0.00 4.62621 0 0 4.30823 0.00 0.000680839 0.000625665 0.0199326 0.0187542 -1 -1 -1 -1 639 5.91667 232 2.14815 338 674 15463 4560 1.07788e+06 754516 219490. 4479.39 10 5100 32136 -1 4.76665 4.41703 0 0 -164.948 -1.707 0.04 -1 -1 67.0 MiB 0.05 0.0545015 0.0506933 67.0 MiB -1 0.04 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.54 vpr 68.95 MiB 0.06 10496 -1 -1 5 0.18 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70604 11 30 313 321 2 114 55 7 7 49 clb auto 29.5 MiB 0.39 459 2031 574 1374 83 68.9 MiB 0.04 0.00 4.6413 0 0 4.31525 0.00 0.000717512 0.000626394 0.019463 0.0174272 -1 -1 -1 -1 569 5.26852 227 2.10185 207 393 9602 2945 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 68.9 MiB 0.06 0.0634405 0.0562085 68.9 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/config.txt index 2f93f53041c..440149973b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/config.txt @@ -24,7 +24,7 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common = -starting_stage vpr +script_params_common = -starting_stage vpr --seed 6 script_params_list_add = -sdc_file sdc/samples/A.sdc script_params_list_add = -sdc_file sdc/samples/B.sdc script_params_list_add = -sdc_file sdc/samples/C.sdc diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index 93ad79df1cb..f1ae2610488 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.46 vpr 63.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64540 5 3 11 14 2 9 10 4 4 16 clb auto 24.3 MiB 0.01 22 30 9 14 7 63.0 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 4.6237e-05 3.9054e-05 0.0002174 0.000180615 -1 -1 -1 -1 8 18 2 107788 107788 4794.78 299.674 0.02 0.00197825 0.00183539 564 862 -1 18 4 10 10 199 87 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00215654 0.00203426 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.51 vpr 62.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64424 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 23 30 6 15 9 62.9 MiB 0.01 0.00 0.571 0 0 0.571 0.02 3.7988e-05 2.9784e-05 0.000252809 0.000212792 -1 -1 -1 -1 8 26 3 107788 107788 4794.78 299.674 0.03 0.00214308 0.00198029 564 862 -1 25 5 13 13 435 272 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00179325 0.00170005 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.53 vpr 63.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64568 5 3 11 14 2 9 10 4 4 16 clb auto 24.3 MiB 0.01 20 30 10 18 2 63.1 MiB 0.00 0.00 0.645658 -2.18842 -0.645658 0.571 0.01 4.2928e-05 3.0736e-05 0.000257589 0.000202685 -1 -1 -1 -1 8 17 3 107788 107788 4794.78 299.674 0.01 0.00208504 0.00188215 564 862 -1 14 5 15 15 285 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00184632 0.00172634 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.57 vpr 62.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64396 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 20 30 12 17 1 62.9 MiB 0.01 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 5.3727e-05 3.88e-05 0.000288614 0.00022112 -1 -1 -1 -1 8 19 8 107788 107788 4794.78 299.674 0.05 0.00254374 0.00221143 564 862 -1 15 2 8 8 156 74 1.57153 0.571 -4.92067 -1.57153 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00180866 0.00171184 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.51 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64496 5 3 11 14 2 9 10 4 4 16 clb auto 24.2 MiB 0.01 20 30 8 18 4 63.0 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 3.8739e-05 2.8831e-05 0.000233335 0.000188434 -1 -1 -1 -1 8 33 10 107788 107788 4794.78 299.674 0.02 0.0025966 0.00229332 564 862 -1 19 2 11 11 275 141 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00164291 0.00155522 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.51 vpr 62.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64328 5 3 11 14 2 9 10 4 4 16 clb auto 24.0 MiB 0.01 20 110 34 46 30 62.8 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.5398e-05 2.9142e-05 0.000512135 0.000417096 -1 -1 -1 -1 8 25 4 107788 107788 4794.78 299.674 0.02 0.00232795 0.00209925 564 862 -1 36 5 15 15 690 511 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00186912 0.00175661 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.44 vpr 65.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66884 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.01 21 30 5 21 4 65.3 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.01 3.9163e-05 3.0734e-05 0.00023521 0.000191167 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00213897 0.00197887 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00188153 0.00176769 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.42 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66820 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.3 MiB 0.00 0.00 0.571 0 0 0.571 0.01 6.1332e-05 3.1443e-05 0.00028123 0.000216755 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00219985 0.00199813 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0028018 0.00269609 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.40 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66764 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 21 30 5 22 3 65.2 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.8778e-05 3.099e-05 0.000214053 0.000176854 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00219902 0.00204346 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00216696 0.00200612 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.40 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.3 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.3301e-05 3.3225e-05 0.000258104 0.000204952 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00214578 0.0019473 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00224405 0.00207678 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.38 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.4 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 5.0024e-05 3.2956e-05 0.000205951 0.000157313 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00254156 0.00219599 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0022282 0.00180897 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.40 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.00 21 30 5 23 2 65.4 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 5.2455e-05 4.3444e-05 0.00030806 0.000256078 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.01 0.00225516 0.00206503 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00187829 0.00175106 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt index c791c5fd70f..5a4eb2784da 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.90 vpr 63.86 MiB 0.01 6660 -1 -1 1 0.03 -1 -1 30168 -1 -1 3 9 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65396 9 8 75 70 1 36 20 5 5 25 clb auto 24.5 MiB 0.67 99 236 93 142 1 63.9 MiB 0.01 0.00 2.64007 -27.5545 -2.64007 2.64007 0.03 0.000150101 0.000136839 0.0027255 0.00257173 -1 -1 -1 -1 44 132 11 151211 75605.7 54748.7 2189.95 0.29 0.0536282 0.0447591 2196 9177 -1 123 7 84 95 3114 1581 2.22275 2.22275 -27.95 -2.22275 0 0 71025.7 2841.03 0.01 0.01 0.01 -1 -1 0.01 0.00628819 0.00587337 13 18 19 7 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.06 vpr 64.08 MiB 0.01 6644 -1 -1 1 0.03 -1 -1 30172 -1 -1 2 11 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65620 11 10 108 97 1 47 23 4 4 16 clb auto 24.7 MiB 2.90 130 119 34 71 14 64.1 MiB 0.02 0.00 3.45122 -42.2328 -3.45122 3.45122 0.02 0.00022162 0.000202735 0.00277225 0.00266397 -1 -1 -1 -1 32 246 49 50403.8 50403.8 20844.1 1302.76 0.19 0.0635376 0.0536173 1004 2840 -1 156 14 159 209 5514 3395 3.66504 3.66504 -47.9227 -3.66504 0 0 24991.0 1561.94 0.00 0.02 0.00 -1 -1 0.00 0.0101538 0.0089849 15 27 29 8 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.21 vpr 64.25 MiB 0.02 6556 -1 -1 1 0.03 -1 -1 30528 -1 -1 7 13 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65792 13 12 149 129 1 69 32 6 6 36 clb auto 24.8 MiB 4.92 213 1182 380 774 28 64.2 MiB 0.02 0.00 3.51316 -53.0648 -3.51316 3.51316 0.05 0.000206158 0.000187115 0.00735065 0.00685129 -1 -1 -1 -1 50 378 21 403230 176413 107229. 2978.57 0.23 0.0627034 0.0537731 3946 19047 -1 356 16 276 387 14108 5999 3.51316 3.51316 -57.4904 -3.51316 0 0 134937. 3748.26 0.02 0.02 0.02 -1 -1 0.02 0.014322 0.0130425 25 38 42 9 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.02 vpr 64.81 MiB 0.01 6608 -1 -1 1 0.05 -1 -1 30256 -1 -1 6 15 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66368 15 14 196 165 1 93 35 5 5 25 clb auto 25.0 MiB 2.37 300 1346 309 1009 28 64.8 MiB 0.03 0.00 3.75042 -65.1319 -3.75042 3.75042 0.03 0.000351053 0.000323744 0.0137524 0.0128999 -1 -1 -1 -1 52 464 29 151211 151211 63348.9 2533.96 0.55 0.128869 0.11071 2316 10503 -1 401 15 409 589 20950 9847 4.67732 4.67732 -77.987 -4.67732 0 0 82390.3 3295.61 0.02 0.05 0.01 -1 -1 0.02 0.0215504 0.0198136 36 51 57 11 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.23 vpr 64.92 MiB 0.01 6684 -1 -1 1 0.04 -1 -1 30264 -1 -1 5 17 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66480 17 16 251 206 1 119 38 5 5 25 clb auto 25.3 MiB 6.53 402 1424 302 1116 6 64.9 MiB 0.06 0.00 4.01364 -77.5944 -4.01364 4.01364 0.04 0.000638029 0.00057449 0.0201591 0.0188678 -1 -1 -1 -1 52 572 17 151211 126010 63348.9 2533.96 0.57 0.18627 0.160969 2316 10503 -1 511 21 627 1044 32807 14764 4.80785 4.80785 -90.325 -4.80785 0 0 82390.3 3295.61 0.01 0.04 0.01 -1 -1 0.01 0.025349 0.0229586 44 66 75 13 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.93 vpr 65.04 MiB 0.01 6560 -1 -1 1 0.04 -1 -1 30652 -1 -1 8 19 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66600 19 18 308 249 1 137 45 6 6 36 clb auto 25.5 MiB 5.82 477 1245 268 971 6 65.0 MiB 0.03 0.00 4.8546 -99.0847 -4.8546 4.8546 0.05 0.000431245 0.000395584 0.0118328 0.0111482 -1 -1 -1 -1 62 774 36 403230 201615 131137. 3642.71 0.93 0.239205 0.206338 4226 23319 -1 685 20 672 1088 36828 14161 5.13584 5.13584 -108.067 -5.13584 0 0 160622. 4461.73 0.02 0.07 0.02 -1 -1 0.02 0.037832 0.0338494 55 83 93 14 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.55 vpr 66.09 MiB 0.01 7168 -1 -1 1 0.03 -1 -1 33640 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67672 9 8 75 70 1 36 20 5 5 25 clb auto 27.1 MiB 0.69 94 695 228 460 7 66.1 MiB 0.01 0.00 2.48207 -26.1618 -2.48207 2.48207 0.03 0.000181733 0.000161557 0.00585234 0.0052913 -1 -1 -1 -1 52 134 15 151211 75605.7 63348.9 2533.96 0.11 0.0432562 0.0374575 2316 10503 -1 114 8 106 124 3566 1793 2.40307 2.40307 -27.5996 -2.40307 0 0 82390.3 3295.61 0.00 0.01 0.02 -1 -1 0.00 0.0069119 0.0064541 13 18 19 7 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.05 vpr 66.50 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33588 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68092 11 10 108 97 1 47 23 4 4 16 clb auto 27.2 MiB 3.14 125 439 123 270 46 66.5 MiB 0.01 0.00 3.45122 -41.5692 -3.45122 3.45122 0.01 0.000220655 0.000197533 0.0046684 0.00428671 -1 -1 -1 -1 30 238 26 50403.8 50403.8 19887.8 1242.99 0.18 0.0734016 0.0633094 992 2748 -1 177 19 176 222 5882 3651 3.90204 3.90204 -49.9067 -3.90204 0 0 24232.7 1514.54 0.00 0.02 0.00 -1 -1 0.00 0.013296 0.0120352 15 27 29 8 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 5.44 vpr 66.68 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33700 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68284 13 12 149 129 1 69 32 6 6 36 clb auto 27.4 MiB 4.03 199 682 229 444 9 66.7 MiB 0.02 0.00 3.51316 -53.1567 -3.51316 3.51316 0.06 0.000399911 0.000364812 0.00775114 0.00715794 -1 -1 -1 -1 40 438 24 403230 176413 88484.8 2457.91 0.50 0.147128 0.127344 3734 16003 -1 329 29 379 534 18280 7787 3.72931 3.72931 -57.4119 -3.72931 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0175574 0.0158074 25 38 42 9 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.95 vpr 66.76 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33776 -1 -1 6 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 15 14 196 165 1 93 35 5 5 25 clb auto 27.2 MiB 2.85 306 947 216 708 23 66.8 MiB 0.02 0.00 3.70693 -62.6491 -3.70693 3.70693 0.02 0.000376121 0.000333163 0.00931262 0.00852228 -1 -1 -1 -1 44 480 22 151211 151211 54748.7 2189.95 0.20 0.0954411 0.083284 2196 9177 -1 392 18 349 466 14859 7098 4.20858 4.20858 -72.9456 -4.20858 0 0 71025.7 2841.03 0.00 0.03 0.01 -1 -1 0.00 0.0211201 0.0192846 36 51 57 11 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.23 vpr 67.12 MiB 0.01 7040 -1 -1 1 0.06 -1 -1 33688 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68736 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 7.05 397 2054 481 1553 20 67.1 MiB 0.04 0.00 3.86806 -74.2346 -3.86806 3.86806 0.03 0.00048716 0.000431817 0.0193024 0.0173986 -1 -1 -1 -1 50 602 24 151211 126010 61632.8 2465.31 0.24 0.130358 0.114428 2268 9834 -1 534 19 619 1012 32161 14755 4.95834 4.95834 -93.7979 -4.95834 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0271021 0.0248239 44 66 75 13 0 0 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.18 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33916 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 19 18 308 249 1 137 45 6 6 36 clb auto 27.7 MiB 5.92 455 2365 460 1885 20 67.2 MiB 0.03 0.00 4.8546 -99.6039 -4.8546 4.8546 0.03 0.000494067 0.000457319 0.0145592 0.0132203 -1 -1 -1 -1 62 737 27 403230 201615 131137. 3642.71 0.40 0.139917 0.121866 4226 23319 -1 634 19 613 910 31131 12187 5.08188 5.08188 -101.573 -5.08188 0 0 160622. 4461.73 0.00 0.04 0.02 -1 -1 0.00 0.0328006 0.0301511 55 83 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt index 6d0dc10b927..8a6305788b3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 6.87 vpr 56.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 58140 6 7 19 26 0 19 26 3 3 9 -1 auto 18.1 MiB 0.00 51 216 43 63 110 56.8 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 5.75 4.0855e-05 3.4458e-05 0.0004697 0.000404466 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.11 0.00249677 0.00223949 1370 14749 -1 19 3 36 39 5809 2843 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.01 0.04 -1 -1 0.00 0.00171008 0.00161397 + sub_tiles.xml sub_tiles.blif common 17.34 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.93 4.894e-05 4.1022e-05 0.00272802 0.000370563 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00475066 0.00224296 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00235645 0.00226006 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt index effb073b2f4..518626ca870 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.44 vpr 56.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 57836 2 2 4 5 0 4 5 3 3 9 -1 auto 17.7 MiB 0.04 8 12 0 0 12 56.5 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.02 2.1799e-05 1.5659e-05 0.000138032 0.000105158 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.00174536 0.00159206 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00138279 0.00133491 + heterogeneous_tile.xml sub_tile_directs.blif common 0.35 vpr 58.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60280 2 2 4 5 0 4 5 3 3 9 -1 auto 20.6 MiB 0.00 8 12 0 0 12 58.9 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7797e-05 1.2853e-05 0.000104532 7.7041e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.00210372 0.00170648 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.0014857 0.00144705 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt index 423988067a7..2adfcb2953c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.62 vpr 64.77 MiB 0.12 9348 -1 -1 3 0.34 -1 -1 34748 -1 -1 19 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66324 99 74 307 381 1 199 193 8 8 64 io memory auto 25.0 MiB 0.09 843 15232 2608 11323 1301 64.8 MiB 0.09 0.00 2.09714 -214.522 -2.09714 2.09714 0.11 0.00118231 0.00110602 0.0292446 0.027405 -1 -1 -1 -1 32 1663 43 2.23746e+06 1.57199e+06 106908. 1670.44 0.66 0.202684 0.181951 4378 18911 -1 1205 26 736 1206 90558 33684 2.26594 2.26594 -220.489 -2.26594 0 0 130676. 2041.82 0.04 0.09 0.03 -1 -1 0.04 0.0490947 0.0443597 + k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.13 vpr 66.94 MiB 0.07 9984 -1 -1 3 0.37 -1 -1 39768 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68544 99 74 307 381 1 199 193 8 8 64 io memory auto 27.3 MiB 0.07 869 22473 4565 15889 2019 66.9 MiB 0.09 0.00 2.15432 -215.614 -2.15432 2.15432 0.09 0.000919068 0.000833008 0.0321902 0.029066 -1 -1 -1 -1 32 1554 36 2.23746e+06 1.57199e+06 106908. 1670.44 0.41 0.172041 0.155343 4378 18911 -1 1152 12 699 1089 60199 20903 2.21433 2.21433 -220.084 -2.21433 0 0 130676. 2041.82 0.01 0.06 0.03 -1 -1 0.01 0.0316397 0.0293511 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt index 88f38747492..b4f05d4d127 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 1.86 vpr 66.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67772 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.22 396 511 91 400 20 66.2 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.000501126 0.000456082 0.0105682 0.00992181 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.69 0.187639 0.16041 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.07 0.01 -1 -1 0.01 0.0401307 0.0361321 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.85 vpr 66.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67848 10 10 168 178 1 73 31 6 6 36 clb auto 26.7 MiB 0.24 396 511 91 400 20 66.3 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.00050814 0.000464386 0.0102811 0.00966555 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.71 0.196479 0.168384 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.07 0.01 -1 -1 0.01 0.0330747 0.0297042 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 5.19 vpr 66.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68216 10 10 168 178 1 162 111 14 14 196 clb auto 26.9 MiB 0.89 1456 5963 865 4880 218 66.6 MiB 0.06 0.00 3.05524 -37.9348 -3.05524 3.05524 0.65 0.000523477 0.000473123 0.0172523 0.0158836 -1 -1 -1 -1 26 2865 15 9.20055e+06 4.90435e+06 387483. 1976.95 1.88 0.188569 0.163851 18784 74779 -1 2696 13 472 1947 107713 24081 3.50167 3.50167 -42.0838 -3.50167 0 0 467681. 2386.13 0.17 0.07 0.07 -1 -1 0.17 0.0274362 0.0252919 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.60 vpr 66.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67712 10 10 168 178 1 75 33 7 7 49 clb auto 26.6 MiB 0.24 404 813 125 661 27 66.1 MiB 0.04 0.00 2.45517 -27.3027 -2.45517 2.45517 0.08 0.00050798 0.000465116 0.0193336 0.0182759 -1 -1 -1 -1 26 1116 28 1.07788e+06 700622 75813.7 1547.22 0.35 0.112548 0.0995004 3816 13734 -1 925 18 487 1699 71725 25249 2.97305 2.97305 -35.2593 -2.97305 0 0 91376.6 1864.83 0.02 0.09 0.01 -1 -1 0.02 0.036074 0.0329384 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 4.47 vpr 66.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68092 10 10 168 178 1 163 124 14 14 196 clb auto 26.8 MiB 1.03 1516 7540 1142 6103 295 66.5 MiB 0.06 0.00 3.06133 -37.7953 -3.06133 3.06133 0.57 0.000550538 0.000486087 0.0169228 0.0153939 -1 -1 -1 -1 20 2911 18 9.20055e+06 5.60498e+06 354876. 1810.58 1.28 0.0956201 0.0845563 18004 60473 -1 2874 12 603 2265 131794 29163 3.74152 3.74152 -44.1586 -3.74152 0 0 387483. 1976.95 0.13 0.05 0.05 -1 -1 0.13 0.0197556 0.0180756 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.87 vpr 66.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67724 10 10 168 178 1 73 31 6 6 36 clb auto 26.5 MiB 0.19 396 511 91 400 20 66.1 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.00050848 0.000463468 0.0108023 0.0101532 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.76 0.210723 0.180638 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.07 0.01 -1 -1 0.01 0.0400523 0.0363482 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.86 vpr 66.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67892 10 10 168 178 1 73 31 6 6 36 clb auto 26.6 MiB 0.24 396 511 91 400 20 66.3 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.04 0.000515808 0.000471915 0.0113979 0.0107292 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.69 0.195893 0.168677 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.07 0.01 -1 -1 0.01 0.0384733 0.0348156 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 5.12 vpr 66.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68400 10 10 168 178 1 162 111 14 14 196 clb auto 27.1 MiB 0.91 1456 5963 865 4880 218 66.8 MiB 0.06 0.00 3.05524 -37.9348 -3.05524 3.05524 0.57 0.000858666 0.000789693 0.0217968 0.0201256 -1 -1 -1 -1 26 2865 15 9.20055e+06 4.90435e+06 387483. 1976.95 1.84 0.178818 0.155234 18784 74779 -1 2696 13 472 1947 107713 24081 3.50167 3.50167 -42.0838 -3.50167 0 0 467681. 2386.13 0.17 0.06 0.08 -1 -1 0.17 0.0255381 0.023411 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.90 vpr 66.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67816 10 10 168 178 1 73 31 6 6 36 clb auto 26.6 MiB 0.23 396 511 91 400 20 66.2 MiB 0.02 0.00 2.39024 -27.2311 -2.39024 2.39024 0.05 0.000710376 0.000647785 0.0115236 0.0108448 -1 -1 -1 -1 28 809 33 646728 592834 52494.1 1458.17 0.72 0.206379 0.177028 2620 9165 -1 829 25 747 2300 88210 34485 2.99961 2.99961 -36.9596 -2.99961 0 0 62803.0 1744.53 0.01 0.11 0.01 -1 -1 0.01 0.0399536 0.0360531 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.21 vpr 27.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28648 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.4 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.21 vpr 27.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28656 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.19 vpr 28.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28716 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.19 vpr 28.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 28828 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 25.6 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_1 1.31 vpr 68.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70324 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.20 399 703 140 536 27 68.7 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000310541 0.000262563 0.00936798 0.00854482 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.46 0.175458 0.152388 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0280432 0.0256776 + EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.18 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70172 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.5 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000328824 0.000280405 0.00830952 0.00754823 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.31 0.10752 0.0932813 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0371511 0.0342602 + EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 4.10 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70728 10 10 168 178 1 162 111 14 14 196 clb auto 29.4 MiB 0.90 1467 5165 686 4267 212 69.1 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.39 0.000594399 0.00050939 0.0158932 0.0140866 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.204118 0.178235 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.04 0.10 0.10 -1 -1 0.04 0.0402804 0.0376719 + EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.27 vpr 68.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70312 10 10 168 178 1 75 33 7 7 49 clb auto 29.2 MiB 0.22 414 605 98 486 21 68.7 MiB 0.02 0.00 2.40687 -27.3475 -2.40687 2.40687 0.06 0.000598343 0.000517434 0.011833 0.0108149 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.28 0.112886 0.100348 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.05 0.02 -1 -1 0.00 0.0342617 0.0315172 + EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.32 vpr 68.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70636 10 10 168 178 1 163 124 14 14 196 clb auto 29.3 MiB 0.71 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.24 0.000341831 0.000287957 0.0139093 0.0123738 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.36 0.0484505 0.0438885 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.07 -1 -1 0.03 0.0262959 0.0240352 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.51 vpr 68.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70184 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000592996 0.000513744 0.0148871 0.0136124 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.60 0.233947 0.201424 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0337396 0.0309919 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.26 vpr 68.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69936 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.14 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000607215 0.000528624 0.0138198 0.0125584 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.45 0.178959 0.157093 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0299846 0.0274172 + EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 4.05 vpr 68.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70468 10 10 168 178 1 162 111 14 14 196 clb auto 29.3 MiB 0.89 1467 5165 686 4267 212 68.8 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.31 0.000662054 0.000579378 0.0167691 0.0149922 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.58 0.235946 0.204687 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.12 -1 -1 0.03 0.0296338 0.0273566 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.49 vpr 68.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69976 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.21 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000326035 0.000277526 0.0147842 0.0134826 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.61 0.214908 0.181228 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.02 -1 -1 0.00 0.0279877 0.0256826 + EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30628 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.7 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.11 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.11 vpr 30.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31020 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.11 vpr 30.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30716 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt index af6269be78f..95f2081009b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 8.71 vpr 73.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 74812 229 197 2152 2349 1 1013 576 16 16 256 io auto 33.5 MiB 3.13 8848 180201 52690 111830 15681 73.1 MiB 1.31 0.03 2.99388 -664.24 -2.99388 2.99388 0.00 0.00538594 0.00461218 0.480806 0.428342 -1 -1 -1 -1 -1 11423 9 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.23 0.688229 0.621836 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 9.08 vpr 75.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77084 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.8 MiB 4.29 8858 177806 51921 111135 14750 75.3 MiB 1.45 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00692729 0.00619106 0.572476 0.497763 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.34 0.862195 0.757255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt index 956417a33e9..a285dc5eca4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 5.18 vpr 65.63 MiB 0.10 9360 -1 -1 3 0.29 -1 -1 34572 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67208 99 130 363 493 1 251 298 12 12 144 clb auto 26.3 MiB 0.15 830 72933 24114 36385 12434 65.6 MiB 0.26 0.00 2.31523 -217.996 -2.31523 2.31523 0.32 0.000917378 0.000858642 0.0838167 0.0788673 -1 -1 -1 -1 38 1583 13 5.66058e+06 4.21279e+06 319130. 2216.18 2.38 0.45942 0.419671 12522 62564 -1 1389 8 493 651 37667 12430 2.73633 2.73633 -236.043 -2.73633 0 0 406292. 2821.48 0.13 0.04 0.07 -1 -1 0.13 0.0261213 0.0244905 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.34 vpr 67.74 MiB 0.06 9856 -1 -1 3 0.39 -1 -1 39776 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69364 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.29 0.00 2.23767 -220.613 -2.23767 2.23767 0.27 0.00107588 0.000959454 0.0879605 0.0803385 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 0.81 0.341856 0.310926 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.05 0.14 -1 -1 0.03 0.0261531 0.0245164 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt index 3fa9e969200..ddf76e6dee9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.11 vpr 65.57 MiB 0.10 9356 -1 -1 3 0.35 -1 -1 34624 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 67140 99 130 363 493 1 251 298 12 12 144 clb auto 26.2 MiB 0.16 850 68953 24096 34301 10556 65.6 MiB 0.21 0.00 2.17528 -135.263 -2.17528 2.17528 0.36 0.000607948 0.000558569 0.0540788 0.0494279 -1 -1 -1 -1 36 1722 23 5.66058e+06 4.21279e+06 305235. 2119.69 0.88 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.16 vpr 67.80 MiB 0.06 9984 -1 -1 3 0.37 -1 -1 39748 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.14 877 59998 22493 27317 10188 67.8 MiB 0.17 0.00 2.17528 -133.517 -2.17528 2.17528 0.25 0.000598743 0.00053199 0.0416228 0.0366674 -1 -1 -1 -1 40 1685 15 5.66058e+06 4.21279e+06 333335. 2314.82 1.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt index 13ad07bee3b..4503f0925f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 6.73 vpr 65.30 MiB 0.11 9496 -1 -1 3 0.35 -1 -1 34624 -1 -1 68 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66864 99 130 363 493 1 252 298 12 12 144 clb auto 26.0 MiB 0.14 765 78903 26762 38665 13476 65.3 MiB 0.25 0.00 2.31285 0 0 2.31285 0.36 0.000595835 0.000546064 0.0568252 0.0524192 -1 -1 -1 -1 38 1556 15 5.66058e+06 4.21279e+06 319130. 2216.18 3.88 0.700323 0.59673 12522 62564 -1 1352 7 424 536 26689 9017 2.96222 2.96222 0 0 0 0 406292. 2821.48 0.13 0.03 0.07 -1 -1 0.13 0.0171393 0.0157816 + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.64 vpr 67.62 MiB 0.06 9856 -1 -1 3 0.30 -1 -1 39896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69248 99 130 363 493 1 252 298 12 12 144 clb auto 28.5 MiB 0.14 956 73928 27133 34341 12454 67.6 MiB 0.26 0.00 2.30557 0 0 2.30557 0.25 0.000962793 0.000867177 0.0597068 0.0524058 -1 -1 -1 -1 38 1840 8 5.66058e+06 4.21279e+06 319130. 2216.18 1.37 0.282428 0.244945 12522 62564 -1 1734 8 415 510 29213 8865 2.61298 2.61298 0 0 0 0 406292. 2821.48 0.02 0.03 0.09 -1 -1 0.02 0.0187719 0.0170722 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt index 26ddabd3b5a..0a5e59f0296 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.68 vpr 65.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66556 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.02 20 30 10 17 3 65.0 MiB 0.01 0.00 0.619658 -3.41326 -0.619658 0.545 0.01 3.9442e-05 2.8479e-05 0.000264801 0.000213415 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.05 0.00220927 0.00202353 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00165203 0.0015765 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.64 vpr 64.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66324 5 3 11 14 2 9 10 4 4 16 clb auto 26.0 MiB 0.02 20 30 10 17 3 64.8 MiB 0.01 0.00 0.619658 -3.41326 -0.619658 0.545 0.01 4.7331e-05 3.4794e-05 0.000313679 0.000255977 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.02 0.00210853 0.00193266 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0016735 0.00159778 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.70 vpr 64.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66360 5 3 11 14 2 9 10 4 4 16 clb auto 26.0 MiB 0.03 20 30 10 17 3 64.8 MiB 0.04 0.00 0.619658 -3.41326 -0.619658 0.545 0.01 5.5384e-05 4.0883e-05 0.000339161 0.000274106 -1 -1 -1 -1 20 15 1 107788 107788 10441.3 652.579 0.02 0.00305328 0.00284599 750 1675 -1 15 1 7 7 94 62 0.562699 0.545 -3.33969 -0.562699 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00161855 0.0015492 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.62 vpr 67.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68616 5 3 11 14 2 9 10 4 4 16 clb auto 28.6 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8501e-05 3.4711e-05 0.00027851 0.000219913 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00215999 0.00198392 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181366 0.00173531 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.62 vpr 67.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68636 5 3 11 14 2 9 10 4 4 16 clb auto 28.5 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.1152e-05 3.666e-05 0.000287379 0.000227035 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.03 0.0023614 0.00216487 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.0022135 0.00167838 + k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.55 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68936 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.7208e-05 4.2383e-05 0.000322556 0.000257546 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.02 0.00215648 0.00197387 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181267 0.00173458 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt index d75c4e0f2bb..9d457582f18 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.86 vpr 66.88 MiB 0.12 10144 -1 -1 5 0.18 -1 -1 33460 -1 -1 14 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68484 11 30 313 321 2 115 55 7 7 49 clb auto 27.2 MiB 0.36 466 2759 556 2108 95 66.9 MiB 0.06 0.00 2.67362 -172.647 -2.67362 2.30794 0.00 0.000854492 0.000777061 0.032919 0.0303032 -1 -1 -1 -1 -1 574 7 1.07788e+06 754516 219490. 4479.39 0.04 0.063998 0.0591785 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.68 vpr 69.25 MiB 0.08 10496 -1 -1 5 0.17 -1 -1 36364 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70908 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.39 448 1927 352 1502 73 69.2 MiB 0.04 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000798161 0.000674358 0.0213182 0.0191108 -1 -1 -1 -1 -1 595 8 1.07788e+06 754516 219490. 4479.39 0.04 0.060298 0.0550487 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt index 2c41099abe5..070113b9371 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.56 vpr 64.55 MiB 0.11 10036 -1 -1 4 0.23 -1 -1 33332 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66096 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 421 2049 269 1715 65 64.5 MiB 0.05 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000901868 0.000816005 0.0182749 0.0165852 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0493513 0.0440772 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.56 vpr 64.68 MiB 0.09 9896 -1 -1 4 0.22 -1 -1 33244 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 66236 11 30 262 292 2 99 60 7 7 49 clb auto 24.9 MiB 0.09 421 2049 269 1715 65 64.7 MiB 0.03 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000505662 0.000447982 0.0141131 0.0127631 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0443633 0.0397038 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.55 vpr 64.02 MiB 0.12 10036 -1 -1 4 0.21 -1 -1 33388 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65552 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 421 2049 269 1715 65 64.0 MiB 0.03 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 8.432e-06 2.592e-06 0.00561579 0.00470719 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0266554 0.0212939 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.55 vpr 63.92 MiB 0.12 9868 -1 -1 4 0.21 -1 -1 33312 -1 -1 19 11 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65456 11 30 262 292 2 99 60 7 7 49 clb auto 24.8 MiB 0.09 421 2049 269 1715 65 63.9 MiB 0.03 0.00 2.53105 -179.908 -2.53105 2.34917 0.00 0.000527965 0.000121671 0.00657296 0.00525257 -1 -1 -1 -1 -1 424 16 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0298469 0.0235615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.31 vpr 66.76 MiB 0.06 10368 -1 -1 4 0.22 -1 -1 36924 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 425 2283 406 1804 73 66.8 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000550429 0.00044745 0.0205892 0.0175295 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0715823 0.0554655 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.35 vpr 67.11 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36664 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68720 11 30 262 292 2 99 60 7 7 49 clb auto 27.5 MiB 0.09 425 2283 406 1804 73 67.1 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000592669 0.000483133 0.0176652 0.0153201 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.08 0.0695138 0.0618702 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.40 vpr 66.21 MiB 0.07 10368 -1 -1 4 0.18 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67804 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000259913 0.000168736 0.00804711 0.00632437 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0326926 0.0257255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.40 vpr 66.24 MiB 0.07 10368 -1 -1 4 0.22 -1 -1 36412 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67828 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000820125 0.000270462 0.0105947 0.00836537 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0358221 0.028376 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt index 676a758e26d..ec4372e5ea5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 69.07 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1213468 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.1 MiB 14.23 70903 253216 51547 191577 10092 1176.3 MiB 10.33 0.14 4.99319 -5223.26 -3.99319 2.64446 0.01 0.0393935 0.0325965 2.91026 2.41968 83183 6.68835 19827 1.59419 25954 36248 10076288 1815088 0 0 2.05929e+07 18207.7 15 331560 3499109 -1 5.28806 2.7363 -5589.94 -4.28806 0 0 6.16 -1 -1 1176.3 MiB 4.02 4.55065 3.84457 1176.3 MiB -1 12.94 + stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 76.86 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215732 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.5 MiB 14.49 75097 245792 47628 188491 9673 1158.4 MiB 19.32 0.31 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0645942 0.0566793 4.57717 3.66743 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 8.99 -1 -1 1158.4 MiB 6.77 7.11559 5.86421 1158.4 MiB -1 3.90 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt index f9dc973d7ee..9097fbde85d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 16.79 vpr 67.83 MiB 0.08 9652 -1 -1 6 0.16 -1 -1 34060 -1 -1 15 66 0 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69456 66 96 1000 687 1 578 192 18 18 324 mult_27 auto 28.6 MiB 1.69 5343 48856 15321 28109 5426 67.8 MiB 0.58 0.01 16.5319 -985.557 -16.5319 16.5319 1.33 0.00284838 0.00269661 0.271323 0.256526 -1 -1 -1 -1 56 12644 31 6.4517e+06 1.13409e+06 1.55150e+06 4788.57 8.30 0.994052 0.922886 50684 323660 -1 11612 24 4774 11145 2601588 732828 16.8532 16.8532 -1120.15 -16.8532 0 0 1.95585e+06 6036.58 0.72 0.84 0.31 -1 -1 0.72 0.163283 0.153391 133 202 146 33 66 33 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 18.00 vpr 70.38 MiB 0.05 10112 -1 -1 6 0.25 -1 -1 38052 -1 -1 15 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72072 66 96 1000 687 1 578 192 18 18 324 mult_27 auto 31.1 MiB 2.15 5241 46091 14804 26339 4948 70.4 MiB 0.71 0.01 16.7702 -967.772 -16.7702 16.7702 0.75 0.00350611 0.00326694 0.374139 0.351063 -1 -1 -1 -1 54 12671 42 6.4517e+06 1.13409e+06 1.49609e+06 4617.55 10.37 1.47511 1.37701 50360 316156 -1 11227 19 3612 7762 1892477 579383 16.9221 16.9221 -1089.8 -16.9221 0 0 1.91711e+06 5917.01 0.13 0.79 0.45 -1 -1 0.13 0.185679 0.177041 133 202 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt index bb1d1e6ccea..9b26c986ccf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.67 vpr 62.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64420 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.03 69 227 71 153 3 62.9 MiB 0.01 0.00 1.42251 -15.9524 -1.42251 1.42251 0.00 0.000117366 0.000105443 0.00207021 0.0019072 -1 -1 -1 -1 86 4.52632 45 2.36842 140 253 6063 2435 323364 161682 20103.2 804.128 19 1140 2762 -1 1.32969 1.32969 -16.56 -1.32969 0 0 0.00 -1 -1 62.9 MiB 0.02 0.00917762 0.00816725 62.9 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.65 vpr 62.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64384 6 8 39 47 1 20 17 5 5 25 clb auto 24.5 MiB 0.03 69 227 71 153 3 62.9 MiB 0.01 0.00 1.42251 -15.9524 -1.42251 1.42251 0.00 0.000188315 0.000170732 0.00297437 0.002743 -1 -1 -1 -1 86 4.52632 45 2.36842 140 253 6063 2435 323364 161682 20103.2 804.128 19 1140 2762 -1 1.32969 1.32969 -16.56 -1.32969 0 0 0.00 -1 -1 62.9 MiB 0.02 0.0122453 0.0107752 62.9 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.36 vpr 63.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64592 6 8 39 47 1 20 17 5 5 25 clb auto 24.7 MiB 0.03 69 227 71 153 3 63.1 MiB 0.01 0.00 1.42347 -15.9604 -1.42347 1.42347 0.00 0.000131128 0.000118797 0.00230482 0.00213538 -1 -1 -1 -1 -1 -1 -1 -1 723 1098 45498 29013 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.1 MiB 0.05 -1 -1 63.1 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.36 vpr 62.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64336 6 8 39 47 1 20 17 5 5 25 clb auto 24.4 MiB 0.05 69 227 71 153 3 62.8 MiB 0.01 0.00 1.42347 -15.9604 -1.42347 1.42347 0.00 0.000130321 0.00011848 0.00234416 0.00216136 -1 -1 -1 -1 142 7.47368 68 3.57895 723 1098 45498 29013 323364 161682 9037.03 361.481 -1 996 1634 -1 1.87665 1.87665 -21.7004 -1.87665 0 0 0.00 -1 -1 62.8 MiB 0.05 -1 -1 62.8 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.53 vpr 65.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66664 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.03 88 59 31 28 0 65.1 MiB 0.01 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.00022667 0.0001997 0.00145978 0.00134015 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.01 -1 -1 65.1 MiB 0.01 0.0151269 0.0141345 65.1 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.49 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000166651 0.000146123 0.00118945 0.00110009 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.0110046 0.0100571 65.2 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.25 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66768 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000189994 0.000167385 0.00110293 0.00101544 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.2 MiB 0.03 -1 -1 65.2 MiB -1 0.00 + k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.27 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000187343 0.000161123 0.00133988 0.00123837 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.2 MiB 0.04 -1 -1 65.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt index 949cccb520a..a8c8aed1d54 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.82 vpr 58.30 MiB 0.12 9420 -1 -1 6 0.20 -1 -1 33332 -1 -1 69 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59700 11 30 336 366 2 175 110 11 11 121 clb auto 19.3 MiB 0.08 1069 7737 1075 6148 514 58.3 MiB 0.07 0.00 3.58466 -257.927 -3.58466 3.35525 0.00 0.000795143 0.000713058 0.0296855 0.0265178 -1 -1 -1 -1 1020 5.96491 1020 5.96491 830 2510 115386 26241 180575 153823 597941. 4941.66 12 20106 83797 -1 3.41136 3.2074 -256.892 -3.41136 -0.21991 -0.0734 0.14 -1 -1 58.3 MiB 0.12 0.0657665 0.0592709 58.3 MiB -1 0.11 - k6_frac_N10_40nm.xml stereovision3.v common 2.09 vpr 59.37 MiB 0.15 9312 -1 -1 4 0.21 -1 -1 33464 -1 -1 13 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60796 11 30 262 292 2 110 54 6 6 36 clb auto 20.2 MiB 0.14 411 1380 237 1087 56 59.4 MiB 0.03 0.00 2.57043 -171.117 -2.57043 2.32238 0.00 0.000673202 0.000603541 0.0138837 0.0127263 -1 -1 -1 -1 489 4.61321 218 2.05660 216 331 9092 3075 862304 700622 161034. 4473.17 7 3844 24048 -1 2.49787 2.27724 -178.279 -2.49787 0 0 0.03 -1 -1 59.4 MiB 0.04 0.0384913 0.0354677 59.4 MiB -1 0.02 + k4_N4_90nm.xml stereovision3.v common 2.42 vpr 61.41 MiB 0.07 9984 -1 -1 6 0.21 -1 -1 36540 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62880 11 30 336 366 2 175 110 11 11 121 clb auto 21.7 MiB 0.07 1099 5370 731 4291 348 61.4 MiB 0.07 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.000895008 0.000764708 0.0287001 0.0253164 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.19 -1 -1 61.4 MiB 0.11 0.0797492 0.0714232 61.4 MiB -1 0.02 + k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 62.21 MiB 0.06 9984 -1 -1 4 0.20 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63704 11 30 262 292 2 110 54 6 6 36 clb auto 22.6 MiB 0.15 403 1584 300 1231 53 62.2 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000808513 0.00071129 0.0212101 0.0190689 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.05 -1 -1 62.2 MiB 0.04 0.0510796 0.0464992 62.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt index 43fe9e64de6..c745d2940f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.46 vpr 58.19 MiB 0.15 9392 -1 -1 6 0.20 -1 -1 33308 -1 -1 69 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 59584 11 30 336 366 2 175 110 11 11 121 clb auto 19.2 MiB 0.06 1069 7737 1075 6148 514 58.2 MiB 0.11 0.00 3.58466 -257.927 -3.58466 3.35525 0.00 0.00113995 0.0010258 0.0368023 0.0330354 -1 -1 -1 -1 1020 5.96491 1020 5.96491 830 2510 115386 26241 180575 153823 597941. 4941.66 12 20106 83797 -1 3.41136 3.2074 -256.892 -3.41136 -0.21991 -0.0734 0.11 -1 -1 58.2 MiB 0.08 0.070273 0.063129 58.2 MiB -1 0.09 - k6_frac_N10_40nm.xml stereovision3.v common 2.05 vpr 59.43 MiB 0.14 9392 -1 -1 4 0.20 -1 -1 33336 -1 -1 13 11 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 60860 11 30 262 292 2 110 54 6 6 36 clb auto 20.2 MiB 0.14 411 1380 237 1087 56 59.4 MiB 0.04 0.00 2.57043 -171.117 -2.57043 2.32238 0.00 0.000753376 0.000667515 0.0140933 0.0129404 -1 -1 -1 -1 489 4.61321 218 2.05660 216 331 9092 3075 862304 700622 161034. 4473.17 7 3844 24048 -1 2.49787 2.27724 -178.279 -2.49787 0 0 0.03 -1 -1 59.4 MiB 0.04 0.0397773 0.0366976 59.4 MiB -1 0.02 + k4_N4_90nm.xml stereovision3.v common 2.36 vpr 61.16 MiB 0.06 9984 -1 -1 6 0.24 -1 -1 36564 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62624 11 30 336 366 2 175 110 11 11 121 clb auto 21.6 MiB 0.08 1099 5370 731 4291 348 61.2 MiB 0.08 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.00109238 0.000939106 0.0296397 0.0256861 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.18 -1 -1 61.2 MiB 0.09 0.0740596 0.0653877 61.2 MiB -1 0.03 + k6_frac_N10_40nm.xml stereovision3.v common 1.71 vpr 62.40 MiB 0.03 10112 -1 -1 4 0.22 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63900 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 403 1584 300 1231 53 62.4 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000733682 0.000641677 0.0178767 0.0155436 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.04 -1 -1 62.4 MiB 0.04 0.0527381 0.04796 62.4 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt index 369954619cf..8249d51c4a6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 33.96 vpr 976.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 1000220 10 10 168 178 1 68 30 11 8 88 io auto 953.8 MiB 0.62 354 536 67 434 35 976.8 MiB 0.06 0.00 6.57169 -72.0462 -6.57169 6.57169 0.00 0.000450859 0.000408422 0.0103745 0.00973574 -1 -1 -1 -1 586 8.74627 178 2.65672 259 971 58705 26468 0 0 194014. 2204.70 13 11730 32605 -1 6.82307 6.82307 -73.1617 -6.82307 0 0 0.08 -1 -1 976.8 MiB 0.07 0.0397393 0.0369452 976.8 MiB -1 0.04 + stratixiv_arch.timing.xml styr.blif common 34.23 vpr 978.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001816 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.58 371 490 69 397 24 978.3 MiB 0.06 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000593468 0.00051514 0.0111956 0.0102241 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.3 MiB 0.07 0.0418866 0.0386921 978.3 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt index f20ab703070..5005a12aaca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt @@ -12,12 +12,14 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=display_control.sv -include_list_add=timer.sv -include_list_add=debounce.sv +#include_list_add=display_control.sv +#include_list_add=timer.sv +#include_list_add=debounce.sv # Add circuits to list to sweep -circuit_list_add=button_controller.sv +#circuit_list_add=button_controller.sv + +circuit_list_add=flattened_button_controller.sv # Add architectures to list to sweep diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt index 6c7dd369b44..c59221ce1d4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt @@ -12,11 +12,12 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=PWM.v +#include_list_add=PWM.v # Add circuits to list to sweep -circuit_list_add=pulse_led.v +#circuit_list_add=pulse_led.v +circuit_list_add=flattened_pulse_width_led.sv # Add architectures to list to sweep arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt index 6b753bb4aa6..c2c180dab1d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt @@ -12,13 +12,13 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=timer.sv -include_list_add=display_control.sv -include_list_add=time_counter.sv -include_list_add=modify_count.sv +#include_list_add=timer.sv +#include_list_add=display_control.sv +#include_list_add=time_counter.sv +#include_list_add=modify_count.sv # Add circuits to list to sweep -circuit_list_add=clock.sv +circuit_list_add=flattened_timer.sv # Add architectures to list to sweep diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt index 27a696e2c05..509f77a6434 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt @@ -1,3 +1,3 @@ regression_tests/vtr_reg_system_verilog/f4pga_button_controller/ regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/ -regression_tests/vtr_reg_system_verilog/f4pga_timer/ \ No newline at end of file +regression_tests/vtr_reg_system_verilog/f4pga_timer/ diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small/config/golden_results.txt index dc27ff97318..cc1a9e173eb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 235.14 - - -1 -1 -1 -1 3 6.08 -1 -1 -1 -1 -1 68 99 1 0 success v8.0.0-6991-g9a34a83d8-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T19:57:36 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing -1 99 130 343 473 1 217 298 12 12 144 clb auto 327.6 MiB 19.26 527 387.6 MiB 18.62 0.28 1.48813 -109.046 -1.48813 1.48813 14.66 0.0431227 0.0369718 2.52447 2.22009 44 1192 28 5.66058e+06 4.21279e+06 360780. 2505.42 69.79 14.6655 13.3453 1046 10 388 639 24800 7975 1.92172 1.92172 -132.535 -1.92172 0 0 470760. 3269.17 4.55 2.00 0.855374 0.779811 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 171.10 - - -1 -1 -1 -1 4 7.64 -1 -1 -1 -1 -1 15 11 0 0 success v8.0.0-6991-g9a34a83d8-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T19:57:36 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing -1 11 2 303 283 2 80 28 7 7 49 clb auto 325.4 MiB 14.61 267 384.7 MiB 2.15 0.04 1.86151 -149.067 -1.86151 1.77041 3.18 0.026727 0.0244673 0.629531 0.531796 20 457 19 1.07788e+06 808410 52439.0 1070.18 11.18 3.19863 2.80245 388 18 286 492 8676 3081 2.28191 2.05156 -171.957 -2.28191 0 0 68696.0 1401.96 0.49 2.13 1.0398 0.920285 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 239.31 - - -1 -1 -1 -1 3 17.61 -1 -1 -1 -1 -1 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing -1 99 130 344 474 1 227 298 12 12 144 clb auto 322.7 MiB 20.06 749 71938 22933 33485 15520 381.0 MiB 16.97 0.33 1.86413 -118.59 -1.86413 1.86413 11.65 0.0732576 0.068454 5.52499 5.15173 -1 -1 -1 -1 42 1520 10 5.66058e+06 4.21279e+06 345696. 2400.67 36.36 14.4547 13.0534 13090 66981 -1 1349 11 399 648 28156 8528 2.01841 2.01841 -138.411 -2.01841 0 0 434636. 3018.30 1.10 3.62 6.08 -1 -1 1.10 2.02601 1.79237 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 253.64 - - -1 -1 -1 -1 4 20.25 -1 -1 -1 -1 -1 15 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing -1 11 2 303 283 2 78 28 7 7 49 clb auto 317.6 MiB 15.14 262 1078 238 765 75 376.4 MiB 3.35 0.07 2.0391 -163.079 -2.0391 1.90116 2.96 0.058501 0.053558 1.68082 1.53185 -1 -1 -1 -1 28 333 12 1.07788e+06 808410 72669.7 1483.05 25.62 14.1524 12.0861 3564 12808 -1 288 8 200 345 4799 1871 2.11979 1.94261 -165.174 -2.11979 0 0 87745.0 1790.71 0.23 2.68 1.60 -1 -1 0.23 1.45763 1.25544 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small_odin/config/golden_results.txt index 2ad6115ccf5..f9583dc46a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small_odin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_valgrind_small/valgrind_small_odin/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 216.22 - - 5.36 -1 -1 -1 3 13.41 -1 -1 -1 -1 -1 65 99 1 0 success v8.0.0-6991-g9a34a83d8-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T19:57:36 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing -1 99 130 363 493 1 251 295 12 12 144 clb auto 318.1 MiB 14.93 645 379.8 MiB 18.45 0.40 2.20394 -203.734 -2.20394 2.20394 15.22 0.0227102 0.0199136 2.38954 2.11394 44 1525 10 5.66058e+06 4.05111e+06 360780. 2505.42 75.30 14.1754 12.8861 1443 8 574 715 52691 16759 2.7395 2.7395 -240.01 -2.7395 0 0 470760. 3269.17 4.60 2.25 0.801898 0.732428 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 142.75 - - 5.84 -1 -1 -1 5 8.14 -1 -1 -1 -1 -1 14 11 0 0 success v8.0.0-6991-g9a34a83d8-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T19:57:36 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing -1 11 30 313 321 2 118 55 7 7 49 clb auto 323.5 MiB 19.41 406 383.2 MiB 3.65 0.05 2.27568 -159.51 -2.27568 2.03262 3.30 0.018455 0.0155492 1.00517 0.862416 30 877 23 1.07788e+06 754516 77114.5 1573.76 27.47 8.76219 7.74656 676 13 411 718 20274 7142 2.45236 2.25315 -180.16 -2.45236 0 0 95414.1 1947.23 0.85 2.72 1.20489 1.04235 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 214.19 - - 6.74 -1 -1 -1 3 31.59 -1 -1 -1 -1 -1 68 99 1 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing -1 99 130 363 493 1 251 298 12 12 144 clb auto 315.5 MiB 16.63 825 66963 24629 31658 10676 375.0 MiB 16.45 0.29 2.18081 -216.806 -2.18081 2.18081 11.68 0.0738834 0.069041 5.19912 4.84873 -1 -1 -1 -1 42 1542 18 5.66058e+06 4.21279e+06 345696. 2400.67 39.10 15.39 13.8531 13090 66981 -1 1416 8 543 745 35361 11414 2.49575 2.49575 -234.092 -2.49575 0 0 434636. 3018.30 1.10 3.44 6.11 -1 -1 1.10 1.69917 1.5038 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 185.29 - - 7.24 -1 -1 -1 5 21.35 -1 -1 -1 -1 -1 14 11 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing -1 11 30 313 321 2 115 55 7 7 49 clb auto 318.7 MiB 19.99 456 2239 413 1740 86 377.4 MiB 3.57 0.10 2.65898 -171.948 -2.65898 2.30209 2.96 0.064002 0.0582579 1.57937 1.43364 -1 -1 -1 -1 30 934 29 1.07788e+06 754516 77114.5 1573.76 17.77 10.2264 8.76037 3660 13876 -1 783 19 469 889 29198 10184 2.65817 2.36697 -188.291 -2.65817 0 0 95414.1 1947.23 0.24 4.44 1.68 -1 -1 0.24 2.66573 2.27986 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/config.txt similarity index 92% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/config.txt index 95b8603ec5b..ba529fa1152 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/config.txt @@ -14,6 +14,7 @@ includes_dir=benchmarks/verilog/koios # Add circuits to list to sweep circuit_list_add=bwave_like.float.large.v +circuit_list_add=bwave_like.fixed.large.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml @@ -35,4 +36,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 --target_utilization 0.28 \ No newline at end of file +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 400 --target_utilization 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_large/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt index e4261a2b31f..0f11b550df2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt @@ -21,7 +21,6 @@ circuit_list_add=lstm.v circuit_list_add=gemm_layer.v circuit_list_add=tpu_like.large.os.v circuit_list_add=tpu_like.large.ws.v -circuit_list_add=tdarknet_like.small.v circuit_list_add=tdarknet_like.large.v circuit_list_add=dla_like.medium.v From 2b664feff20a01209bebfbe7820dc5dfe1abd557 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Apr 2025 13:41:32 -0700 Subject: [PATCH 449/453] [core] code format --- vpr/src/base/SetupGrid.h | 1 - vpr/src/route/rr_graph.cpp | 1 - 2 files changed, 2 deletions(-) diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 5be96a00535..3f2568d673f 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -22,7 +22,6 @@ DeviceGrid create_device_grid(const std::string& layout_name, float target_device_utilization = 0.0); ///@brief Find the device close in size to the specified dimensions - DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index b3398fb7774..baa2ed82021 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -568,7 +568,6 @@ static void alloc_rr_switch_inf(RRGraphBuilder& rr_graph_builder, t_arch_switch_fanin& arch_switch_fanins, const std::map& arch_sw_map); - static std::vector alloc_and_load_global_route_seg_details(const int global_route_switch); static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_graph, From 7950a1bac5b6fd14275327c12bbb4dbca2a293e6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Apr 2025 13:42:42 -0700 Subject: [PATCH 450/453] [core] remove blif benchmarks --- .../VIB/VIB_test_benchmarks/Divide.blif | 2290 - .../VIB/VIB_test_benchmarks/GrayCounter.blif | 51 - .../VIB/VIB_test_benchmarks/LCDmodule.blif | 389 - .../VIB_test_benchmarks/LED_BCD8x7seg.blif | 918 - .../VIB/VIB_test_benchmarks/Murax.blif | 19659 ------ .../VIB/VIB_test_benchmarks/PWM.blif | 574 - .../PushButton_Debouncer.blif | 204 - .../VIB/VIB_test_benchmarks/RCServo.blif | 735 - .../TaskAck_CrossDomain.blif | 53 - .../VIB/VIB_test_benchmarks/VexRiscv.blif | 10133 --- .../VIB_test_benchmarks/VexRiscv_full.blif | 34792 ---------- .../VIB_test_benchmarks/VexRiscv_small.blif | 10133 --- .../VIB/VIB_test_benchmarks/boxcar.blif | 1473 - .../VIB/VIB_test_benchmarks/cordic.blif | 27532 -------- .../VIB/VIB_test_benchmarks/cordictanh.blif | 19093 ------ .../VIB/VIB_test_benchmarks/music.blif | 1170 - .../VIB/VIB_test_benchmarks/picorv32.blif | 15942 ----- .../VIB/VIB_test_benchmarks/pong.blif | 1394 - .../VIB/VIB_test_benchmarks/quad.blif | 135 - .../VIB/VIB_test_benchmarks/seqcordic.blif | 4862 -- .../VIB/VIB_test_benchmarks/seqpolar.blif | 6314 -- .../VIB/VIB_test_benchmarks/smplfir.blif | 525 - .../VIB/VIB_test_benchmarks/topolar.blif | 36396 ----------- .../VIB/VIB_test_benchmarks/zipcore.blif | 54152 ---------------- 24 files changed, 248919 deletions(-) delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/pong.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif delete mode 100644 vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif deleted file mode 100644 index 884a1ede974..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif +++ /dev/null @@ -1,2290 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model Divide -.inputs clk reset start A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[19] A[20] A[21] A[22] A[23] A[24] A[25] A[26] A[27] A[28] A[29] A[30] A[31] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] B[8] B[9] B[10] B[11] B[12] B[13] B[14] B[15] B[16] B[17] B[18] B[19] B[20] B[21] B[22] B[23] B[24] B[25] B[26] B[27] B[28] B[29] B[30] B[31] -.outputs D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] D[16] D[17] D[18] D[19] D[20] D[21] D[22] D[23] D[24] D[25] D[26] D[27] D[28] D[29] D[30] D[31] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] R[8] R[9] R[10] R[11] R[12] R[13] R[14] R[15] R[16] R[17] R[18] R[19] R[20] R[21] R[22] R[23] R[24] R[25] R[26] R[27] R[28] R[29] R[30] R[31] ok err -.names $false -.names $true -1 -.names $undef -.names start active denom[30] B[30] $abc$1738$auto$rtlil.cc:2693:MuxGate$1342 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[29] B[29] $abc$1738$auto$rtlil.cc:2693:MuxGate$1344 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[28] B[28] $abc$1738$auto$rtlil.cc:2693:MuxGate$1346 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[27] B[27] $abc$1738$auto$rtlil.cc:2693:MuxGate$1348 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[26] B[26] $abc$1738$auto$rtlil.cc:2693:MuxGate$1350 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[25] B[25] $abc$1738$auto$rtlil.cc:2693:MuxGate$1352 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[24] B[24] $abc$1738$auto$rtlil.cc:2693:MuxGate$1354 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[23] B[23] $abc$1738$auto$rtlil.cc:2693:MuxGate$1356 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[22] B[22] $abc$1738$auto$rtlil.cc:2693:MuxGate$1358 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[21] B[21] $abc$1738$auto$rtlil.cc:2693:MuxGate$1360 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[20] B[20] $abc$1738$auto$rtlil.cc:2693:MuxGate$1362 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[19] B[19] $abc$1738$auto$rtlil.cc:2693:MuxGate$1364 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[18] B[18] $abc$1738$auto$rtlil.cc:2693:MuxGate$1366 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[17] B[17] $abc$1738$auto$rtlil.cc:2693:MuxGate$1368 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[16] B[16] $abc$1738$auto$rtlil.cc:2693:MuxGate$1370 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[15] B[15] $abc$1738$auto$rtlil.cc:2693:MuxGate$1372 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[14] B[14] $abc$1738$auto$rtlil.cc:2693:MuxGate$1374 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[13] B[13] $abc$1738$auto$rtlil.cc:2693:MuxGate$1376 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[12] B[12] $abc$1738$auto$rtlil.cc:2693:MuxGate$1378 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[11] B[11] $abc$1738$auto$rtlil.cc:2693:MuxGate$1380 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[10] B[10] $abc$1738$auto$rtlil.cc:2693:MuxGate$1382 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[9] B[9] $abc$1738$auto$rtlil.cc:2693:MuxGate$1384 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[8] B[8] $abc$1738$auto$rtlil.cc:2693:MuxGate$1386 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[7] B[7] $abc$1738$auto$rtlil.cc:2693:MuxGate$1388 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[6] B[6] $abc$1738$auto$rtlil.cc:2693:MuxGate$1390 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[5] B[5] $abc$1738$auto$rtlil.cc:2693:MuxGate$1392 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[4] B[4] $abc$1738$auto$rtlil.cc:2693:MuxGate$1394 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[3] B[3] $abc$1738$auto$rtlil.cc:2693:MuxGate$1396 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[2] B[2] $abc$1738$auto$rtlil.cc:2693:MuxGate$1398 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[1] B[1] $abc$1738$auto$rtlil.cc:2693:MuxGate$1400 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active denom[0] B[0] $abc$1738$auto$rtlil.cc:2693:MuxGate$1402 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active D[30] D[29] A[30] $abc$1738$auto$rtlil.cc:2693:MuxGate$1404 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[29] D[28] A[29] $abc$1738$auto$rtlil.cc:2693:MuxGate$1406 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[28] D[27] A[28] $abc$1738$auto$rtlil.cc:2693:MuxGate$1408 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[27] D[26] A[27] $abc$1738$auto$rtlil.cc:2693:MuxGate$1410 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[26] D[25] A[26] $abc$1738$auto$rtlil.cc:2693:MuxGate$1412 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[25] D[24] A[25] $abc$1738$auto$rtlil.cc:2693:MuxGate$1414 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[24] D[23] A[24] $abc$1738$auto$rtlil.cc:2693:MuxGate$1416 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[23] D[22] A[23] $abc$1738$auto$rtlil.cc:2693:MuxGate$1418 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[22] D[21] A[22] $abc$1738$auto$rtlil.cc:2693:MuxGate$1420 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[21] D[20] A[21] $abc$1738$auto$rtlil.cc:2693:MuxGate$1422 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[20] D[19] A[20] $abc$1738$auto$rtlil.cc:2693:MuxGate$1424 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[19] D[18] A[19] $abc$1738$auto$rtlil.cc:2693:MuxGate$1426 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[18] D[17] A[18] $abc$1738$auto$rtlil.cc:2693:MuxGate$1428 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[17] D[16] A[17] $abc$1738$auto$rtlil.cc:2693:MuxGate$1430 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[16] D[15] A[16] $abc$1738$auto$rtlil.cc:2693:MuxGate$1432 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[15] D[14] A[15] $abc$1738$auto$rtlil.cc:2693:MuxGate$1434 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[14] D[13] A[14] $abc$1738$auto$rtlil.cc:2693:MuxGate$1436 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names start active D[13] D[12] A[13] $abc$1738$auto$rtlil.cc:2693:MuxGate$1438 -00100 1 -00101 1 -00110 1 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$abc$1738$new_n335 $abc$1738$new_n416 $abc$1738$new_n415 R[10] $abc$1738$auto$rtlil.cc:2693:MuxGate$1512 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names R[10] denom[11] R[9] denom[10] $abc$1738$new_n346 $abc$1738$new_n415 -00000 1 -00100 1 -00101 1 -00110 1 -01001 1 -01010 1 -01011 1 -01111 1 -10001 1 -10010 1 -10011 1 -10111 1 -11000 1 -11100 1 -11101 1 -11110 1 -.names R[11] start $abc$1738$new_n416 -10 1 -.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n422 $abc$1738$new_n421 R[8] $abc$1738$auto$rtlil.cc:2693:MuxGate$1516 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names R[8] denom[9] R[7] denom[8] $abc$1738$new_n347 $abc$1738$new_n421 -00000 1 -00100 1 -00101 1 -00110 1 -01001 1 -01010 1 -01011 1 -01111 1 -10001 1 -10010 1 -10011 1 -10111 1 -11000 1 -11100 1 -11101 1 -11110 1 -.names R[9] start $abc$1738$new_n422 -10 1 -.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n428 $abc$1738$new_n427 R[6] $abc$1738$auto$rtlil.cc:2693:MuxGate$1520 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names R[6] denom[7] R[5] denom[6] $abc$1738$new_n348 $abc$1738$new_n427 -00000 1 -00100 1 -00101 1 -00110 1 -01001 1 -01010 1 -01011 1 -01111 1 -10001 1 -10010 1 -10011 1 -10111 1 -11000 1 -11100 1 -11101 1 -11110 1 -.names R[7] start $abc$1738$new_n428 -10 1 -.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n434 $abc$1738$new_n433 R[4] $abc$1738$auto$rtlil.cc:2693:MuxGate$1524 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names R[4] denom[5] R[3] denom[4] $abc$1738$new_n349 $abc$1738$new_n433 -00000 1 -00100 1 -00101 1 -00110 1 -01001 1 -01010 1 -01011 1 -01111 1 -10001 1 -10010 1 -10011 1 -10111 1 -11000 1 -11100 1 -11101 1 -11110 1 -.names R[5] start $abc$1738$new_n434 -10 1 -.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n440 $abc$1738$new_n439 R[2] $abc$1738$auto$rtlil.cc:2693:MuxGate$1528 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names R[2] denom[3] R[1] denom[2] $abc$1738$new_n350 $abc$1738$new_n439 -00000 1 -00100 1 -00101 1 -00110 1 -01001 1 -01010 1 -01011 1 -01111 1 -10001 1 -10010 1 -10011 1 -10111 1 -11000 1 -11100 1 -11101 1 -11110 1 -.names R[3] start $abc$1738$new_n440 -10 1 -.names $abc$1738$new_n361 D[31] denom[0] $abc$1738$new_n335 $abc$1738$new_n448 $abc$1738$auto$rtlil.cc:2693:MuxGate$1534 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names R[0] start $abc$1738$new_n448 -10 1 -.names start R[31] active R[30] $abc$1738$new_n450 $abc$1738$auto$rtlil.cc:2693:MuxGate$1536 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names denom[31] R[29] denom[30] $abc$1738$new_n336 $abc$1738$new_n450 -0001 1 -0010 1 -0011 1 -0111 1 -1000 1 -1100 1 -1101 1 -1110 1 -.names start active denom[31] B[31] $abc$1738$auto$rtlil.cc:2693:MuxGate$1538 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names start active D[31] D[30] A[31] $abc$1738$auto$rtlil.cc:2693:MuxGate$1540 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names cycle[4] $abc$1738$new_n352 cycle[3] start active $abc$1738$auto$rtlil.cc:2693:MuxGate$1542 -00010 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names active start $abc$1738$new_n352 cycle[4] cycle[3] $abc$1738$auto$rtlil.cc:2693:MuxGate$1544 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$1738$new_n462 $abc$1738$new_n460 $abc$1738$new_n458 $abc$1738$new_n456 err -1111 1 -.names $abc$1738$new_n457 B[31] B[0] B[1] B[2] $abc$1738$new_n456 -10000 1 -.names B[3] B[4] B[5] B[6] $abc$1738$new_n457 -0000 1 -.names $abc$1738$new_n459 B[11] B[12] B[13] B[14] $abc$1738$new_n458 -10000 1 -.names B[7] B[8] B[9] B[10] $abc$1738$new_n459 -0000 1 -.names $abc$1738$new_n461 B[19] B[20] B[21] B[22] $abc$1738$new_n460 -10000 1 -.names B[15] B[16] B[17] B[18] $abc$1738$new_n461 -0000 1 -.names $abc$1738$new_n463 B[27] B[28] B[29] B[30] $abc$1738$new_n462 -10000 1 -.names B[23] B[24] B[25] B[26] $abc$1738$new_n463 -0000 1 -.names active ok -0 1 -.names start $abc$1738$new_n337 denom[28] R[28] $abc$1738$new_n465 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[27] start $abc$1738$new_n465 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1478 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n338 denom[26] R[26] $abc$1738$new_n467 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[25] start $abc$1738$new_n467 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1482 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n339 denom[24] R[24] $abc$1738$new_n469 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[23] start $abc$1738$new_n469 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1486 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n340 denom[22] R[22] $abc$1738$new_n471 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[21] start $abc$1738$new_n471 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1490 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n341 denom[20] R[20] $abc$1738$new_n473 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[19] start $abc$1738$new_n473 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1494 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n342 denom[18] R[18] $abc$1738$new_n475 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[17] start $abc$1738$new_n475 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1498 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n343 denom[16] R[16] $abc$1738$new_n477 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[15] start $abc$1738$new_n477 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1502 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n344 denom[14] R[14] $abc$1738$new_n479 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[13] start $abc$1738$new_n479 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1506 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n345 denom[12] R[12] $abc$1738$new_n481 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[11] start $abc$1738$new_n481 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1510 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n346 denom[10] R[10] $abc$1738$new_n483 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[9] start $abc$1738$new_n483 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1514 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n347 denom[8] R[8] $abc$1738$new_n485 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[7] start $abc$1738$new_n485 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1518 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n348 denom[6] R[6] $abc$1738$new_n487 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[5] start $abc$1738$new_n487 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1522 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n349 denom[4] R[4] $abc$1738$new_n489 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[3] start $abc$1738$new_n489 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1526 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start $abc$1738$new_n350 denom[2] R[2] $abc$1738$new_n491 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names active R[1] start $abc$1738$new_n491 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1530 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names start denom[1] denom[0] D[31] R[1] $abc$1738$new_n493 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names active R[0] start $abc$1738$new_n493 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1532 -00010 1 -00011 1 -01010 1 -01011 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1534 Q=R[0] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1532 Q=R[1] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1530 Q=R[2] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1528 Q=R[3] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1526 Q=R[4] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1524 Q=R[5] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1522 Q=R[6] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1520 Q=R[7] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1518 Q=R[8] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1516 Q=R[9] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1514 Q=R[10] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1512 Q=R[11] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1510 Q=R[12] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1508 Q=R[13] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1506 Q=R[14] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1504 Q=R[15] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1502 Q=R[16] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1500 Q=R[17] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1498 Q=R[18] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1496 Q=R[19] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1494 Q=R[20] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1492 Q=R[21] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1490 Q=R[22] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1488 Q=R[23] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1486 Q=R[24] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1484 Q=R[25] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1482 Q=R[26] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1480 Q=R[27] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1478 Q=R[28] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1476 Q=R[29] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1474 Q=R[30] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1536 Q=R[31] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1544 Q=active R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1472 Q=cycle[0] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1470 Q=cycle[1] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1468 Q=cycle[2] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1466 Q=cycle[3] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1542 Q=cycle[4] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1464 Q=D[0] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1462 Q=D[1] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1460 Q=D[2] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1458 Q=D[3] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1456 Q=D[4] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1454 Q=D[5] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1452 Q=D[6] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1450 Q=D[7] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1448 Q=D[8] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1446 Q=D[9] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1444 Q=D[10] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1442 Q=D[11] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1440 Q=D[12] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1438 Q=D[13] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1436 Q=D[14] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1434 Q=D[15] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1432 Q=D[16] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1430 Q=D[17] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1428 Q=D[18] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1426 Q=D[19] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1424 Q=D[20] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1422 Q=D[21] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1420 Q=D[22] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1418 Q=D[23] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1416 Q=D[24] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1414 Q=D[25] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1412 Q=D[26] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1410 Q=D[27] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1408 Q=D[28] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1406 Q=D[29] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1404 Q=D[30] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1540 Q=D[31] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1402 Q=denom[0] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1400 Q=denom[1] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1398 Q=denom[2] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1396 Q=denom[3] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1394 Q=denom[4] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1392 Q=denom[5] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1390 Q=denom[6] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1388 Q=denom[7] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1386 Q=denom[8] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1384 Q=denom[9] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1382 Q=denom[10] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1380 Q=denom[11] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1378 Q=denom[12] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1376 Q=denom[13] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1374 Q=denom[14] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1372 Q=denom[15] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1370 Q=denom[16] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1368 Q=denom[17] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1366 Q=denom[18] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1364 Q=denom[19] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1362 Q=denom[20] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1360 Q=denom[21] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1358 Q=denom[22] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1356 Q=denom[23] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1354 Q=denom[24] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1352 Q=denom[25] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1350 Q=denom[26] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1348 Q=denom[27] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1346 Q=denom[28] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1344 Q=denom[29] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1342 Q=denom[30] R=reset -.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1538 Q=denom[31] R=reset -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif deleted file mode 100644 index dec03bfebde..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif +++ /dev/null @@ -1,51 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model GrayCounter -.inputs clk -.outputs cnt_gray[0] cnt_gray[1] cnt_gray[2] cnt_gray[3] -.names $false -.names $true -1 -.names $undef -.names cnt[2] cnt[1] cnt_gray[1] -01 1 -10 1 -.names cnt_gray[3] cnt[2] cnt_gray[2] -01 1 -10 1 -.names cnt[1] cnt[0] cnt_gray[0] -01 1 -10 1 -.names cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$401.Y[2] -011 1 -100 1 -101 1 -110 1 -.names cnt_gray[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$401.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[0] $auto$alumacc.cc:485:replace_alu$401.X[0] -0 1 -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.X[0] Q=cnt[0] -.subckt dff C=clk D=cnt_gray[0] Q=cnt[1] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.Y[2] Q=cnt[2] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.Y[3] Q=cnt_gray[3] -.names cnt[1] $auto$alumacc.cc:485:replace_alu$401.X[1] -1 1 -.names cnt[2] $auto$alumacc.cc:485:replace_alu$401.X[2] -1 1 -.names cnt_gray[3] $auto$alumacc.cc:485:replace_alu$401.X[3] -1 1 -.names $auto$alumacc.cc:485:replace_alu$401.X[0] $auto$alumacc.cc:485:replace_alu$401.Y[0] -1 1 -.names cnt_gray[0] $auto$alumacc.cc:485:replace_alu$401.Y[1] -1 1 -.names cnt_gray[3] cnt[3] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif deleted file mode 100644 index 429f2a124a8..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif +++ /dev/null @@ -1,389 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model LCDmodule -.inputs clk RxD -.outputs LCD_RS LCD_RW LCD_E LCD_DataBus[0] LCD_DataBus[1] LCD_DataBus[2] LCD_DataBus[3] LCD_DataBus[4] LCD_DataBus[5] LCD_DataBus[6] LCD_DataBus[7] -.names $false -.names $true -1 -.names $undef -.names count[0] count[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1481 -01 1 -10 1 -.names count[0] $0\LCD_E[0:0] deserialer.RxD_data_ready $abc$1754$auto$rtlil.cc:2693:MuxGate$1483 -001 1 -010 1 -011 1 -.names count[2] count[0] count[1] $0\LCD_E[0:0] -001 1 -010 1 -011 1 -100 1 -101 1 -110 1 -111 1 -.names deserialer.OversamplingTick deserialer.Filter_cnt[0] deserialer.Filter_cnt[1] deserialer.RxD_sync[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1485 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names $abc$1754$new_n83 LCD_RS LCD_DataBus[6] $abc$1754$auto$rtlil.cc:2693:MuxGate$1487 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_state[3] $abc$1754$new_n84 $abc$1754$new_n83 -11 1 -.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick deserialer.OversamplingCnt[2] $abc$1754$new_n84 -1110 1 -.names $abc$1754$new_n83 LCD_DataBus[6] LCD_DataBus[5] $abc$1754$auto$rtlil.cc:2693:MuxGate$1489 -001 1 -011 1 -110 1 -111 1 -.names $abc$1754$new_n83 LCD_DataBus[5] LCD_DataBus[4] $abc$1754$auto$rtlil.cc:2693:MuxGate$1491 -001 1 -011 1 -110 1 -111 1 -.names $abc$1754$new_n83 LCD_DataBus[4] LCD_DataBus[3] $abc$1754$auto$rtlil.cc:2693:MuxGate$1493 -001 1 -011 1 -110 1 -111 1 -.names $abc$1754$new_n83 LCD_DataBus[3] LCD_DataBus[2] $abc$1754$auto$rtlil.cc:2693:MuxGate$1495 -001 1 -011 1 -110 1 -111 1 -.names $abc$1754$new_n83 LCD_DataBus[2] LCD_DataBus[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1497 -001 1 -011 1 -110 1 -111 1 -.names $abc$1754$new_n83 LCD_DataBus[1] LCD_DataBus[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1499 -001 1 -011 1 -110 1 -111 1 -.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick $abc$1754$new_n92 $abc$1754$auto$rtlil.cc:2693:MuxGate$1503 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -.names deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$1754$new_n92 -0000 1 -.names deserialer.OversamplingTick deserialer.OversamplingCnt[0] $abc$1754$new_n92 $abc$1754$auto$rtlil.cc:2693:MuxGate$1507 -010 1 -011 1 -100 1 -.names deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$1754$new_n95 deserialer.RxD_state[2] $abc$1754$auto$rtlil.cc:2693:MuxGate$1509 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$1754$new_n96 $abc$1754$new_n84 deserialer.RxD_bit $abc$1754$new_n92 $abc$1754$new_n95 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names deserialer.RxD_state[3] deserialer.RxD_state[1] deserialer.RxD_state[0] deserialer.RxD_state[2] $abc$1754$new_n96 -0000 1 -0001 1 -0011 1 -0101 1 -0110 1 -0111 1 -.names $abc$1754$new_n95 deserialer.RxD_state[0] $abc$1754$new_n92 deserialer.RxD_state[3] $abc$1754$auto$rtlil.cc:2693:MuxGate$1511 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names deserialer.OversamplingTick RxD deserialer.RxD_sync[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1513 -001 1 -011 1 -110 1 -111 1 -.names count[2] count[0] count[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1515 -011 1 -100 1 -101 1 -110 1 -.names deserialer.OversamplingTick deserialer.RxD_sync[0] deserialer.RxD_sync[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1517 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_bit deserialer.Filter_cnt[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1521 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names deserialer.Filter_cnt[1] deserialer.RxD_sync[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1523 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names deserialer.OversamplingCnt[2] $abc$1754$new_n92 deserialer.OversamplingCnt[0] deserialer.OversamplingCnt[1] deserialer.OversamplingTick $abc$1754$auto$rtlil.cc:2693:MuxGate$1527 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$1754$new_n83 deserialer.RxD_bit LCD_RS $abc$1754$auto$rtlil.cc:2693:MuxGate$1529 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_state[2] deserialer.RxD_state[3] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$1754$new_n95 $abc$1754$auto$rtlil.cc:2693:MuxGate$1533 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$1754$new_n95 deserialer.RxD_state[2] deserialer.RxD_state[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1535 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$1754$new_n108 $abc$1754$new_n84 $abc$1754$flatten\deserialer.$0\RxD_data_ready[0:0] -11 1 -.names deserialer.RxD_bit deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] $abc$1754$new_n108 -11000 1 -.names deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[1] -00 1 -11 1 -.names deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[2] -000 1 -101 1 -110 1 -111 1 -.names deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[3] -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[4] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[5] -00 1 -11 1 -.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $abc$1754$new_n114 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -.names deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[6] -010 1 -100 1 -101 1 -111 1 -.names deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[7] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -1110 1 -.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[8] -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[9] -01 1 -10 1 -.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $abc$1754$new_n119 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[10] -011 1 -100 1 -101 1 -110 1 -.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[11] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.CO[11] -1111 1 -.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.X[0] -0 1 -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1521 Q=deserialer.RxD_bit -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1485 Q=deserialer.Filter_cnt[0] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1523 Q=deserialer.Filter_cnt[1] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1483 Q=count[0] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1481 Q=count[1] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1515 Q=count[2] -.subckt dff C=clk D=$0\LCD_E[0:0] Q=LCD_E -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1513 Q=deserialer.RxD_sync[0] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1517 Q=deserialer.RxD_sync[1] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1511 Q=deserialer.RxD_state[0] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1509 Q=deserialer.RxD_state[1] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1535 Q=deserialer.RxD_state[3] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1533 Q=deserialer.RxD_state[2] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.X[0] Q=deserialer.tickgen.Acc[4] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[1] Q=deserialer.tickgen.Acc[5] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[2] Q=deserialer.tickgen.Acc[6] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[3] Q=deserialer.tickgen.Acc[7] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[4] Q=deserialer.tickgen.Acc[8] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[5] Q=deserialer.tickgen.Acc[9] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[6] Q=deserialer.tickgen.Acc[10] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[7] Q=deserialer.tickgen.Acc[11] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[8] Q=deserialer.tickgen.Acc[12] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[9] Q=deserialer.tickgen.Acc[13] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[10] Q=deserialer.tickgen.Acc[14] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[11] Q=deserialer.tickgen.Acc[15] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.CO[11] Q=deserialer.OversamplingTick -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1507 Q=deserialer.OversamplingCnt[0] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1503 Q=deserialer.OversamplingCnt[1] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1527 Q=deserialer.OversamplingCnt[2] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1499 Q=LCD_DataBus[0] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1497 Q=LCD_DataBus[1] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1495 Q=LCD_DataBus[2] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1493 Q=LCD_DataBus[3] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1491 Q=LCD_DataBus[4] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1489 Q=LCD_DataBus[5] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1487 Q=LCD_DataBus[6] -.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1529 Q=LCD_RS -.subckt dff C=clk D=$abc$1754$flatten\deserialer.$0\RxD_data_ready[0:0] Q=deserialer.RxD_data_ready -.names deserialer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$595.X[3] -1 1 -.names deserialer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$595.X[5] -1 1 -.names deserialer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$595.X[6] -1 1 -.names deserialer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$595.X[8] -1 1 -.names deserialer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$595.X[9] -1 1 -.names deserialer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$595.X[10] -1 1 -.names deserialer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$595.X[11] -1 1 -.names $false $auto$alumacc.cc:485:replace_alu$595.X[12] -1 1 -.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.CO[0] -1 1 -.names $false $auto$alumacc.cc:485:replace_alu$595.CO[12] -1 1 -.names $false LCD_DataBus[7] -1 1 -.names $false LCD_RW -1 1 -.names deserialer.OversamplingTick deserialer.tickgen.Acc[16] -1 1 -.names $auto$alumacc.cc:485:replace_alu$595.X[0] $auto$alumacc.cc:485:replace_alu$595.Y[0] -1 1 -.names $auto$alumacc.cc:485:replace_alu$595.CO[11] $auto$alumacc.cc:485:replace_alu$595.Y[12] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif deleted file mode 100644 index 7228a4d4759..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif +++ /dev/null @@ -1,918 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model LED_BCD8x7seg -.inputs clk -.outputs segA segB segC segD segE segF segG segDP seg_cathode[0] seg_cathode[1] seg_cathode[2] seg_cathode[3] seg_cathode[4] seg_cathode[5] seg_cathode[6] seg_cathode[7] -.names $false -.names $true -1 -.names $undef -.names BCD.BCD_digits[2] BCD.BCD_digits[1] $abc$1987$new_n130 $abc$1987$auto$rtlil.cc:2693:MuxGate$1679 -011 1 -100 1 -101 1 -110 1 -.names cnt[23] BCD.BCD_digits[0] $abc$1987$new_n131 $abc$1987$new_n130 -111 1 -.names cnt[22] cnt[21] cnt[20] cnt[19] $abc$1987$new_n132 $abc$1987$new_n131 -11111 1 -.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 seg_cathode[7] $abc$1987$new_n132 -11110 1 -.names cnt[12] cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $abc$1987$new_n133 -11111 1 -.names cnt[8] cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $abc$1987$new_n134 -11111 1 -.names cnt[4] cnt[3] cnt[2] cnt[1] cnt[0] $abc$1987$new_n135 -11111 1 -.names cnt[17] cnt[16] cnt[18] seg_cathode[7] -000 1 -001 1 -010 1 -011 1 -100 1 -101 1 -110 1 -.names BCD.BCD_digits[1] $abc$1987$new_n130 $abc$1987$new_n138 $abc$1987$auto$rtlil.cc:2693:MuxGate$1683 -010 1 -100 1 -.names BCD.BCD_digits[3] BCD.BCD_digits[1] BCD.BCD_digits[2] $abc$1987$new_n138 -100 1 -.names BCD.BCD_digits[0] cnt[23] $abc$1987$new_n131 $abc$1987$auto$rtlil.cc:2693:MuxGate$1687 -011 1 -100 1 -101 1 -110 1 -.names BCD.BCD_digits[6] BCD.BCD_digits[4] BCD.BCD_digits[5] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1691 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$1987$new_n138 $abc$1987$new_n130 $abc$1987$new_n141 -11 1 -.names BCD.BCD_digits[5] BCD.BCD_digits[4] $abc$1987$new_n141 BCD.BCD_digits[6] BCD.BCD_digits[7] $abc$1987$auto$rtlil.cc:2693:MuxGate$1695 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names BCD.BCD_digits[4] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1699 -01 1 -10 1 -.names BCD.BCD_digits[10] BCD.BCD_digits[8] BCD.BCD_digits[9] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1703 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[23] BCD.BCD_digits[0] $abc$1987$new_n146 $abc$1987$new_n138 $abc$1987$new_n131 $abc$1987$new_n145 -11111 1 -.names BCD.BCD_digits[7] BCD.BCD_digits[4] BCD.BCD_digits[5] BCD.BCD_digits[6] $abc$1987$new_n146 -1100 1 -.names BCD.BCD_digits[9] BCD.BCD_digits[8] $abc$1987$new_n145 BCD.BCD_digits[10] BCD.BCD_digits[11] $abc$1987$auto$rtlil.cc:2693:MuxGate$1707 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names BCD.BCD_digits[8] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1711 -01 1 -10 1 -.names BCD.BCD_digits[14] BCD.BCD_digits[13] $abc$1987$new_n150 $abc$1987$auto$rtlil.cc:2693:MuxGate$1715 -011 1 -100 1 -101 1 -110 1 -.names BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$new_n150 -11 1 -.names $abc$1987$new_n152 $abc$1987$new_n145 $abc$1987$new_n151 -11 1 -.names BCD.BCD_digits[11] BCD.BCD_digits[8] BCD.BCD_digits[9] BCD.BCD_digits[10] $abc$1987$new_n152 -1100 1 -.names $abc$1987$new_n150 BCD.BCD_digits[13] BCD.BCD_digits[14] BCD.BCD_digits[15] $abc$1987$auto$rtlil.cc:2693:MuxGate$1719 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1011 1 -.names BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$auto$rtlil.cc:2693:MuxGate$1723 -01 1 -10 1 -.names BCD.BCD_digits[18] BCD.BCD_digits[16] BCD.BCD_digits[17] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1727 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$1987$new_n157 $abc$1987$new_n151 $abc$1987$new_n156 -11 1 -.names BCD.BCD_digits[15] BCD.BCD_digits[12] BCD.BCD_digits[13] BCD.BCD_digits[14] $abc$1987$new_n157 -1100 1 -.names BCD.BCD_digits[17] BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$new_n159 $abc$1987$auto$rtlil.cc:2693:MuxGate$1731 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BCD.BCD_digits[19] BCD.BCD_digits[18] $abc$1987$new_n159 -10 1 -.names BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1735 -01 1 -10 1 -.names BCD.BCD_digits[22] BCD.BCD_digits[20] BCD.BCD_digits[21] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1739 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$1987$new_n157 $abc$1987$new_n163 $abc$1987$new_n151 $abc$1987$new_n162 -111 1 -.names BCD.BCD_digits[16] $abc$1987$new_n159 BCD.BCD_digits[17] $abc$1987$new_n163 -110 1 -.names BCD.BCD_digits[21] BCD.BCD_digits[20] $abc$1987$new_n162 BCD.BCD_digits[22] BCD.BCD_digits[23] $abc$1987$auto$rtlil.cc:2693:MuxGate$1743 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names BCD.BCD_digits[20] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1747 -01 1 -10 1 -.names BCD.BCD_digits[26] BCD.BCD_digits[25] $abc$1987$new_n167 $abc$1987$auto$rtlil.cc:2693:MuxGate$1751 -011 1 -100 1 -101 1 -110 1 -.names BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$new_n167 -11 1 -.names $abc$1987$new_n169 $abc$1987$new_n157 $abc$1987$new_n152 $abc$1987$new_n163 $abc$1987$new_n145 $abc$1987$new_n168 -11111 1 -.names BCD.BCD_digits[23] BCD.BCD_digits[20] BCD.BCD_digits[21] BCD.BCD_digits[22] $abc$1987$new_n169 -1100 1 -.names $abc$1987$new_n167 BCD.BCD_digits[25] BCD.BCD_digits[26] BCD.BCD_digits[27] $abc$1987$auto$rtlil.cc:2693:MuxGate$1755 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1011 1 -.names BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1759 -01 1 -10 1 -.names BCD.BCD_digits[30] BCD.BCD_digits[29] $abc$1987$new_n173 $abc$1987$auto$rtlil.cc:2693:MuxGate$1763 -011 1 -100 1 -101 1 -110 1 -.names BCD.BCD_digits[28] $abc$1987$new_n174 $abc$1987$new_n168 $abc$1987$new_n173 -111 1 -.names BCD.BCD_digits[27] BCD.BCD_digits[24] BCD.BCD_digits[25] BCD.BCD_digits[26] $abc$1987$new_n174 -1100 1 -.names $abc$1987$new_n173 BCD.BCD_digits[29] BCD.BCD_digits[30] BCD.BCD_digits[31] $abc$1987$auto$rtlil.cc:2693:MuxGate$1767 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1011 1 -.names BCD.BCD_digits[28] $abc$1987$new_n174 $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1771 -011 1 -100 1 -101 1 -110 1 -.names BCD.BCD_digits[31] BCD.BCD_digits[29] BCD.BCD_digits[30] $abc$1987$new_n173 $abc$1987$auto$rtlil.cc:2693:MuxGate$1775 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names BCD.BCD_digits[27] BCD.BCD_digits[25] BCD.BCD_digits[26] BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1779 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names BCD.BCD_digits[23] BCD.BCD_digits[21] BCD.BCD_digits[22] BCD.BCD_digits[20] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1783 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names BCD.BCD_digits[19] BCD.BCD_digits[17] BCD.BCD_digits[18] BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1787 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names BCD.BCD_digits[15] BCD.BCD_digits[13] BCD.BCD_digits[14] BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$auto$rtlil.cc:2693:MuxGate$1791 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names BCD.BCD_digits[11] BCD.BCD_digits[9] BCD.BCD_digits[10] BCD.BCD_digits[8] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1795 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names BCD.BCD_digits[7] BCD.BCD_digits[5] BCD.BCD_digits[6] BCD.BCD_digits[4] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1799 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names BCD.BCD_digits[3] BCD.BCD_digits[1] BCD.BCD_digits[2] $abc$1987$new_n130 $abc$1987$auto$rtlil.cc:2693:MuxGate$1803 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[16] cnt[17] cnt[18] seg_cathode[1] -000 1 -001 1 -010 1 -011 1 -101 1 -110 1 -111 1 -.names cnt[17] cnt[16] cnt[18] seg_cathode[2] -000 1 -001 1 -010 1 -011 1 -101 1 -110 1 -111 1 -.names cnt[17] cnt[16] cnt[18] seg_cathode[3] -000 1 -001 1 -010 1 -011 1 -100 1 -101 1 -111 1 -.names cnt[18] cnt[17] cnt[16] seg_cathode[4] -000 1 -001 1 -010 1 -011 1 -101 1 -110 1 -111 1 -.names cnt[18] cnt[16] cnt[17] seg_cathode[5] -000 1 -001 1 -010 1 -011 1 -100 1 -101 1 -111 1 -.names cnt[17] cnt[18] cnt[16] seg_cathode[6] -000 1 -001 1 -010 1 -011 1 -100 1 -101 1 -111 1 -.names cnt[17] cnt[16] cnt[18] seg_cathode[0] -001 1 -010 1 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n208 segG -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names cnt[18] $abc$1987$new_n194 $abc$1987$new_n196 $abc$1987$new_n193 -010 1 -011 1 -101 1 -111 1 -.names cnt[17] cnt[16] $abc$1987$new_n195 BCD.BCD_digits[10] BCD.BCD_digits[14] $abc$1987$new_n194 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names seg_cathode[1] BCD.BCD_digits[2] BCD.BCD_digits[6] $abc$1987$new_n195 -000 1 -010 1 -100 1 -101 1 -.names $abc$1987$new_n197 cnt[16] cnt[17] BCD.BCD_digits[26] BCD.BCD_digits[30] $abc$1987$new_n196 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names cnt[16] cnt[18] cnt[17] BCD.BCD_digits[18] BCD.BCD_digits[22] $abc$1987$new_n197 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names cnt[18] $abc$1987$new_n199 $abc$1987$new_n201 $abc$1987$new_n202 $abc$1987$new_n198 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names cnt[17] cnt[16] $abc$1987$new_n200 BCD.BCD_digits[31] BCD.BCD_digits[27] $abc$1987$new_n199 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names seg_cathode[5] BCD.BCD_digits[19] BCD.BCD_digits[23] $abc$1987$new_n200 -000 1 -010 1 -100 1 -101 1 -.names seg_cathode[3] BCD.BCD_digits[15] cnt[17] BCD.BCD_digits[11] $abc$1987$new_n201 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names cnt[16] cnt[17] cnt[18] BCD.BCD_digits[3] BCD.BCD_digits[7] $abc$1987$new_n202 -00010 1 -00011 1 -00110 1 -00111 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names cnt[17] $abc$1987$new_n204 $abc$1987$new_n206 $abc$1987$new_n203 -001 1 -011 1 -110 1 -111 1 -.names cnt[18] cnt[16] $abc$1987$new_n205 BCD.BCD_digits[25] BCD.BCD_digits[29] $abc$1987$new_n204 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names cnt[16] BCD.BCD_digits[9] BCD.BCD_digits[13] $abc$1987$new_n205 -000 1 -001 1 -100 1 -110 1 -.names cnt[18] cnt[16] $abc$1987$new_n207 BCD.BCD_digits[17] BCD.BCD_digits[21] $abc$1987$new_n206 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names cnt[16] BCD.BCD_digits[1] BCD.BCD_digits[5] $abc$1987$new_n207 -000 1 -001 1 -100 1 -110 1 -.names cnt[18] $abc$1987$new_n209 $abc$1987$new_n211 $abc$1987$new_n208 -001 1 -011 1 -110 1 -111 1 -.names seg_cathode[7] $abc$1987$new_n210 BCD.BCD_digits[24] cnt[17] BCD.BCD_digits[28] $abc$1987$new_n209 -00000 1 -00010 1 -00100 1 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -.names cnt[16] cnt[17] BCD.BCD_digits[16] BCD.BCD_digits[20] $abc$1987$new_n210 -0010 1 -0011 1 -1001 1 -1011 1 -.names seg_cathode[3] $abc$1987$new_n212 BCD.BCD_digits[8] cnt[17] BCD.BCD_digits[12] $abc$1987$new_n211 -00000 1 -00010 1 -00100 1 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -.names cnt[16] cnt[17] BCD.BCD_digits[0] BCD.BCD_digits[4] $abc$1987$new_n212 -0010 1 -0011 1 -1001 1 -1011 1 -.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n208 segF -0110 1 -0111 1 -1001 1 -1100 1 -1101 1 -1111 1 -.names $abc$1987$new_n208 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n198 segE -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$1987$new_n203 $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n208 segD -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1111 1 -.names $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n203 $abc$1987$new_n208 segC -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1110 1 -1111 1 -.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n208 $abc$1987$new_n193 segB -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n203 $abc$1987$new_n208 segA -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1111 1 -.names cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[1] -01 1 -10 1 -.names cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[2] -011 1 -100 1 -101 1 -110 1 -.names cnt[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[4] cnt[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[4] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[5] -01 1 -10 1 -.names cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[6] -011 1 -100 1 -101 1 -110 1 -.names cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[7] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[8] cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[8] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[9] -01 1 -10 1 -.names cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[10] -011 1 -100 1 -101 1 -110 1 -.names cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[11] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[12] cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[12] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[13] -01 1 -10 1 -.names cnt[14] cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[14] -011 1 -100 1 -101 1 -110 1 -.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[15] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[16] -01 1 -10 1 -.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 $abc$1987$new_n235 -1111 1 -.names cnt[17] cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[17] -011 1 -100 1 -101 1 -110 1 -.names cnt[18] cnt[17] cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[18] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[19] $abc$1987$new_n132 $auto$alumacc.cc:485:replace_alu$473.Y[19] -01 1 -10 1 -.names cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[20] -01 1 -10 1 -.names cnt[19] $abc$1987$new_n132 $abc$1987$new_n240 -11 1 -.names cnt[21] cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[21] -011 1 -100 1 -101 1 -110 1 -.names cnt[22] cnt[21] cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[22] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names cnt[23] $abc$1987$new_n131 $auto$alumacc.cc:485:replace_alu$473.Y[23] -01 1 -10 1 -.names cnt[0] $auto$alumacc.cc:485:replace_alu$473.X[0] -0 1 -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.X[0] Q=cnt[0] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[1] Q=cnt[1] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[2] Q=cnt[2] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[3] Q=cnt[3] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[4] Q=cnt[4] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[5] Q=cnt[5] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[6] Q=cnt[6] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[7] Q=cnt[7] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[8] Q=cnt[8] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[9] Q=cnt[9] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[10] Q=cnt[10] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[11] Q=cnt[11] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[12] Q=cnt[12] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[13] Q=cnt[13] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[14] Q=cnt[14] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[15] Q=cnt[15] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[16] Q=cnt[16] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[17] Q=cnt[17] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[18] Q=cnt[18] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[19] Q=cnt[19] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[20] Q=cnt[20] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[21] Q=cnt[21] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[22] Q=cnt[22] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[23] Q=cnt[23] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1771 Q=BCD.BCD_digits[28] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1767 Q=BCD.BCD_digits[29] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1763 Q=BCD.BCD_digits[30] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1775 Q=BCD.BCD_digits[31] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1759 Q=BCD.BCD_digits[24] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1755 Q=BCD.BCD_digits[25] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1751 Q=BCD.BCD_digits[26] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1779 Q=BCD.BCD_digits[27] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1747 Q=BCD.BCD_digits[20] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1743 Q=BCD.BCD_digits[21] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1739 Q=BCD.BCD_digits[22] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1783 Q=BCD.BCD_digits[23] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1735 Q=BCD.BCD_digits[16] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1731 Q=BCD.BCD_digits[17] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1727 Q=BCD.BCD_digits[18] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1787 Q=BCD.BCD_digits[19] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1723 Q=BCD.BCD_digits[12] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1719 Q=BCD.BCD_digits[13] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1715 Q=BCD.BCD_digits[14] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1791 Q=BCD.BCD_digits[15] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1711 Q=BCD.BCD_digits[8] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1707 Q=BCD.BCD_digits[9] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1703 Q=BCD.BCD_digits[10] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1795 Q=BCD.BCD_digits[11] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1699 Q=BCD.BCD_digits[4] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1695 Q=BCD.BCD_digits[5] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1691 Q=BCD.BCD_digits[6] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1799 Q=BCD.BCD_digits[7] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1687 Q=BCD.BCD_digits[0] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1683 Q=BCD.BCD_digits[1] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1679 Q=BCD.BCD_digits[2] -.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1803 Q=BCD.BCD_digits[3] -.names cnt[1] $auto$alumacc.cc:485:replace_alu$473.X[1] -1 1 -.names cnt[2] $auto$alumacc.cc:485:replace_alu$473.X[2] -1 1 -.names cnt[3] $auto$alumacc.cc:485:replace_alu$473.X[3] -1 1 -.names cnt[4] $auto$alumacc.cc:485:replace_alu$473.X[4] -1 1 -.names cnt[5] $auto$alumacc.cc:485:replace_alu$473.X[5] -1 1 -.names cnt[6] $auto$alumacc.cc:485:replace_alu$473.X[6] -1 1 -.names cnt[7] $auto$alumacc.cc:485:replace_alu$473.X[7] -1 1 -.names cnt[8] $auto$alumacc.cc:485:replace_alu$473.X[8] -1 1 -.names cnt[9] $auto$alumacc.cc:485:replace_alu$473.X[9] -1 1 -.names cnt[10] $auto$alumacc.cc:485:replace_alu$473.X[10] -1 1 -.names cnt[11] $auto$alumacc.cc:485:replace_alu$473.X[11] -1 1 -.names cnt[12] $auto$alumacc.cc:485:replace_alu$473.X[12] -1 1 -.names cnt[13] $auto$alumacc.cc:485:replace_alu$473.X[13] -1 1 -.names cnt[14] $auto$alumacc.cc:485:replace_alu$473.X[14] -1 1 -.names cnt[15] $auto$alumacc.cc:485:replace_alu$473.X[15] -1 1 -.names cnt[16] $auto$alumacc.cc:485:replace_alu$473.X[16] -1 1 -.names cnt[17] $auto$alumacc.cc:485:replace_alu$473.X[17] -1 1 -.names cnt[18] $auto$alumacc.cc:485:replace_alu$473.X[18] -1 1 -.names cnt[19] $auto$alumacc.cc:485:replace_alu$473.X[19] -1 1 -.names cnt[20] $auto$alumacc.cc:485:replace_alu$473.X[20] -1 1 -.names cnt[21] $auto$alumacc.cc:485:replace_alu$473.X[21] -1 1 -.names cnt[22] $auto$alumacc.cc:485:replace_alu$473.X[22] -1 1 -.names cnt[23] $auto$alumacc.cc:485:replace_alu$473.X[23] -1 1 -.names $auto$alumacc.cc:485:replace_alu$473.X[0] $auto$alumacc.cc:485:replace_alu$473.Y[0] -1 1 -.names $false segDP -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif deleted file mode 100644 index 15b3654b812..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif +++ /dev/null @@ -1,19659 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model Murax -.inputs io_asyncReset io_mainClk io_jtag_tms io_jtag_tdi io_jtag_tck io_gpioA_read[0] io_gpioA_read[1] io_gpioA_read[2] io_gpioA_read[3] io_gpioA_read[4] io_gpioA_read[5] io_gpioA_read[6] io_gpioA_read[7] io_gpioA_read[8] io_gpioA_read[9] io_gpioA_read[10] io_gpioA_read[11] io_gpioA_read[12] io_gpioA_read[13] io_gpioA_read[14] io_gpioA_read[15] io_gpioA_read[16] io_gpioA_read[17] io_gpioA_read[18] io_gpioA_read[19] io_gpioA_read[20] io_gpioA_read[21] io_gpioA_read[22] io_gpioA_read[23] io_gpioA_read[24] io_gpioA_read[25] io_gpioA_read[26] io_gpioA_read[27] io_gpioA_read[28] io_gpioA_read[29] io_gpioA_read[30] io_gpioA_read[31] io_uart_rxd -.outputs io_jtag_tdo io_gpioA_write[0] io_gpioA_write[1] io_gpioA_write[2] io_gpioA_write[3] io_gpioA_write[4] io_gpioA_write[5] io_gpioA_write[6] io_gpioA_write[7] io_gpioA_write[8] io_gpioA_write[9] io_gpioA_write[10] io_gpioA_write[11] io_gpioA_write[12] io_gpioA_write[13] io_gpioA_write[14] io_gpioA_write[15] io_gpioA_write[16] io_gpioA_write[17] io_gpioA_write[18] io_gpioA_write[19] io_gpioA_write[20] io_gpioA_write[21] io_gpioA_write[22] io_gpioA_write[23] io_gpioA_write[24] io_gpioA_write[25] io_gpioA_write[26] io_gpioA_write[27] io_gpioA_write[28] io_gpioA_write[29] io_gpioA_write[30] io_gpioA_write[31] io_gpioA_writeEnable[0] io_gpioA_writeEnable[1] io_gpioA_writeEnable[2] io_gpioA_writeEnable[3] io_gpioA_writeEnable[4] io_gpioA_writeEnable[5] io_gpioA_writeEnable[6] io_gpioA_writeEnable[7] io_gpioA_writeEnable[8] io_gpioA_writeEnable[9] io_gpioA_writeEnable[10] io_gpioA_writeEnable[11] io_gpioA_writeEnable[12] io_gpioA_writeEnable[13] io_gpioA_writeEnable[14] io_gpioA_writeEnable[15] io_gpioA_writeEnable[16] io_gpioA_writeEnable[17] io_gpioA_writeEnable[18] io_gpioA_writeEnable[19] io_gpioA_writeEnable[20] io_gpioA_writeEnable[21] io_gpioA_writeEnable[22] io_gpioA_writeEnable[23] io_gpioA_writeEnable[24] io_gpioA_writeEnable[25] io_gpioA_writeEnable[26] io_gpioA_writeEnable[27] io_gpioA_writeEnable[28] io_gpioA_writeEnable[29] io_gpioA_writeEnable[30] io_gpioA_writeEnable[31] io_uart_txd -.names $false -.names $true -1 -.names $undef -.names $abc$18544$new_n2708 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$abc$18544$auto$rtlil.cc:2693:MuxGate$14614 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[14] system_timer._zz_io_limit[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14616 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2757 $abc$18544$new_n2720 $abc$18544$new_n2756 -11 1 -.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2757 -10000 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[13] system_timer._zz_io_limit[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14618 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[12] system_timer._zz_io_limit[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14620 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_3 system_timer._zz_io_limit[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14622 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l379 system_timer._zz_io_limit[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14624 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_2 system_timer._zz_io_limit[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14626 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[8] system_timer._zz_io_limit[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14628 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[7] system_timer._zz_io_limit[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14630 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[6] system_timer._zz_io_limit[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14632 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[5] system_timer._zz_io_limit[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14634 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[4] system_timer._zz_io_limit[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14636 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[3] system_timer._zz_io_limit[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14638 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[2] system_timer._zz_io_limit[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14640 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer._zz_io_limit[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14642 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347 system_timer._zz_io_limit[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14644 -001 1 -011 1 -110 1 -111 1 -.names system_timer.timerA.counter[14] system_timer.timerA.counter[13] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$14646 -011 1 -100 1 -101 1 -110 1 -.names system_timer.timerA.counter[9] system_timer.timerA.counter[10] system_timer.timerA.counter[11] system_timer.timerA.counter[12] $abc$18544$new_n2774 $abc$18544$new_n2773 -11111 1 -.names system_timer.timerA.counter[8] $abc$18544$new_n2775 $abc$18544$new_n2774 -11 1 -.names system_timer.timerA.counter[7] $abc$18544$new_n2776 $abc$18544$new_n2775 -11 1 -.names system_timer.timerA.counter[6] $abc$18544$new_n2777 $abc$18544$new_n2776 -11 1 -.names system_timer.timerA.counter[5] $abc$18544$new_n2778 $abc$18544$new_n2777 -11 1 -.names system_timer.timerA.counter[4] $abc$18544$new_n2779 $abc$18544$new_n2778 -11 1 -.names system_timer.timerA.counter[3] $abc$18544$new_n2780 $abc$18544$new_n2779 -11 1 -.names system_timer.timerA.counter[2] $abc$18544$new_n2781 $abc$18544$new_n2780 -11 1 -.names system_timer.timerA.counter[1] $abc$18544$new_n2782 $abc$18544$new_n2781 -11 1 -.names system_timer.timerA.counter[0] $abc$18544$new_n2783 $abc$18544$new_n2782 -11 1 -.names $abc$18544$new_n5029 $abc$18544$new_n2784 $abc$18544$new_n2783 -00 1 -.names system_timer.timerABridge_ticksEnable[0] $abc$18544$new_n5026 system_timer.timerABridge_ticksEnable[1] $abc$18544$new_n2784 -000 1 -001 1 -010 1 -.names $abc$18544$new_n2789 $abc$18544$new_n2787 $abc$18544$new_n2790 system_timer.prescaler_1.counter[14] system_timer._zz_io_limit[14] $abc$18544$new_n2786 -11100 1 -11111 1 -.names $abc$18544$new_n2788 system_timer.prescaler_1.counter[4] system_timer._zz_io_limit[4] system_timer.prescaler_1.counter[12] system_timer._zz_io_limit[12] $abc$18544$new_n2787 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_timer._zz_io_limit[3] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[6] system_timer._zz_io_limit[6] $abc$18544$new_n2788 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer._zz_io_limit[7] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[13] system_timer._zz_io_limit[13] $abc$18544$new_n2789 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer._zz_io_limit[0] system_timer.prescaler_1.counter[0] system_timer.prescaler_1.counter[10] system_timer._zz_io_limit[10] $abc$18544$new_n2790 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer._zz_io_limit[8] system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[9] system_timer._zz_io_limit[9] $abc$18544$new_n2792 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n2801 $abc$18544$new_n2800 $abc$18544$new_n2799 $abc$18544$new_n2797 $abc$18544$new_n2796 -1111 1 -.names system_timer.timerA.counter[6] system_timer.system_timer_timerA_io_limit_driver[6] system_timer.timerA.counter[10] system_timer.system_timer_timerA_io_limit_driver[10] $abc$18544$new_n2798 $abc$18544$new_n2797 -00000 1 -00110 1 -11000 1 -11110 1 -.names system_timer.timerA.counter[12] system_timer.system_timer_timerA_io_limit_driver[12] $abc$18544$new_n2798 -01 1 -10 1 -.names system_timer.timerA.counter[1] system_timer.system_timer_timerA_io_limit_driver[1] system_timer.timerA.counter[11] system_timer.system_timer_timerA_io_limit_driver[11] $abc$18544$new_n2799 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer.timerA.counter[2] system_timer.system_timer_timerA_io_limit_driver[2] system_timer.timerA.counter[7] system_timer.system_timer_timerA_io_limit_driver[7] $abc$18544$new_n2800 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer.timerA.counter[5] system_timer.system_timer_timerA_io_limit_driver[5] system_timer.timerA.counter[13] system_timer.system_timer_timerA_io_limit_driver[13] $abc$18544$new_n2801 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer.timerA.counter[8] system_timer.system_timer_timerA_io_limit_driver[8] system_timer.timerA.counter[9] system_timer.system_timer_timerA_io_limit_driver[9] $abc$18544$new_n2803 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer.timerA.counter[13] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$14648 -01 1 -10 1 -.names system_timer.timerA.counter[12] system_timer.timerA.counter[9] system_timer.timerA.counter[10] system_timer.timerA.counter[11] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14650 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names system_timer.timerA.counter[11] system_timer.timerA.counter[9] system_timer.timerA.counter[10] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14652 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names system_timer.timerA.counter[10] system_timer.timerA.counter[9] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14654 -011 1 -100 1 -101 1 -110 1 -.names system_timer.timerA.counter[9] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14656 -01 1 -10 1 -.names system_timer.timerA.counter[8] $abc$18544$new_n2775 $abc$18544$auto$rtlil.cc:2693:MuxGate$14658 -01 1 -10 1 -.names system_timer.timerA.counter[7] $abc$18544$new_n2776 $abc$18544$auto$rtlil.cc:2693:MuxGate$14660 -01 1 -10 1 -.names system_timer.timerA.counter[6] $abc$18544$new_n2777 $abc$18544$auto$rtlil.cc:2693:MuxGate$14662 -01 1 -10 1 -.names system_timer.timerA.counter[5] $abc$18544$new_n2778 $abc$18544$auto$rtlil.cc:2693:MuxGate$14664 -01 1 -10 1 -.names system_timer.timerA.counter[4] $abc$18544$new_n2779 $abc$18544$auto$rtlil.cc:2693:MuxGate$14666 -01 1 -10 1 -.names system_timer.timerA.counter[3] $abc$18544$new_n2780 $abc$18544$auto$rtlil.cc:2693:MuxGate$14668 -01 1 -10 1 -.names system_timer.timerA.counter[2] $abc$18544$new_n2781 $abc$18544$auto$rtlil.cc:2693:MuxGate$14670 -01 1 -10 1 -.names system_timer.timerA.counter[1] $abc$18544$new_n2782 $abc$18544$auto$rtlil.cc:2693:MuxGate$14672 -01 1 -10 1 -.names system_timer.timerA.counter[0] $abc$18544$new_n2783 $abc$18544$auto$rtlil.cc:2693:MuxGate$14674 -01 1 -10 1 -.names $abc$18544$new_n2821 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.interruptCtrl_1.io_masks[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14676 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2822 $abc$18544$new_n2709 $abc$18544$new_n2821 -11 1 -.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2822 -11000 1 -.names system_timer.timerB.counter[14] system_timer.timerB.counter[13] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$14678 -011 1 -100 1 -101 1 -110 1 -.names system_timer.timerB.counter[9] system_timer.timerB.counter[10] system_timer.timerB.counter[11] system_timer.timerB.counter[12] $abc$18544$new_n2825 $abc$18544$new_n2824 -11111 1 -.names system_timer.timerB.counter[8] $abc$18544$new_n2826 $abc$18544$new_n2825 -11 1 -.names system_timer.timerB.counter[7] $abc$18544$new_n2827 $abc$18544$new_n2826 -11 1 -.names system_timer.timerB.counter[6] $abc$18544$new_n2828 $abc$18544$new_n2827 -11 1 -.names system_timer.timerB.counter[5] $abc$18544$new_n2829 $abc$18544$new_n2828 -11 1 -.names system_timer.timerB.counter[4] $abc$18544$new_n2830 $abc$18544$new_n2829 -11 1 -.names system_timer.timerB.counter[3] $abc$18544$new_n2831 $abc$18544$new_n2830 -11 1 -.names system_timer.timerB.counter[2] $abc$18544$new_n2832 $abc$18544$new_n2831 -11 1 -.names system_timer.timerB.counter[1] $abc$18544$new_n2833 $abc$18544$new_n2832 -11 1 -.names system_timer.timerB.counter[0] $abc$18544$new_n2834 $abc$18544$new_n2833 -11 1 -.names $abc$18544$new_n5032 $abc$18544$new_n2835 $abc$18544$new_n2834 -00 1 -.names system_timer.timerBBridge_ticksEnable[0] $abc$18544$new_n5026 system_timer.timerBBridge_ticksEnable[1] $abc$18544$new_n2835 -000 1 -001 1 -010 1 -.names $abc$18544$new_n2842 $abc$18544$new_n2841 $abc$18544$new_n2840 $abc$18544$new_n2838 $abc$18544$new_n2837 -1111 1 -.names system_timer.timerB.counter[6] system_timer.system_timer_timerB_io_limit_driver[6] system_timer.timerB.counter[10] system_timer.system_timer_timerB_io_limit_driver[10] $abc$18544$new_n2839 $abc$18544$new_n2838 -00000 1 -00110 1 -11000 1 -11110 1 -.names system_timer.timerB.counter[12] system_timer.system_timer_timerB_io_limit_driver[12] $abc$18544$new_n2839 -01 1 -10 1 -.names system_timer.timerB.counter[1] system_timer.system_timer_timerB_io_limit_driver[1] system_timer.timerB.counter[11] system_timer.system_timer_timerB_io_limit_driver[11] $abc$18544$new_n2840 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer.timerB.counter[2] system_timer.system_timer_timerB_io_limit_driver[2] system_timer.timerB.counter[7] system_timer.system_timer_timerB_io_limit_driver[7] $abc$18544$new_n2841 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer.timerB.counter[5] system_timer.system_timer_timerB_io_limit_driver[5] system_timer.timerB.counter[13] system_timer.system_timer_timerB_io_limit_driver[13] $abc$18544$new_n2842 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer.timerB.counter[8] system_timer.system_timer_timerB_io_limit_driver[8] system_timer.timerB.counter[9] system_timer.system_timer_timerB_io_limit_driver[9] $abc$18544$new_n2845 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_timer.timerB.counter[13] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$14680 -01 1 -10 1 -.names system_timer.timerB.counter[12] system_timer.timerB.counter[9] system_timer.timerB.counter[10] system_timer.timerB.counter[11] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14682 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names system_timer.timerB.counter[11] system_timer.timerB.counter[9] system_timer.timerB.counter[10] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14684 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names system_timer.timerB.counter[10] system_timer.timerB.counter[9] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14686 -011 1 -100 1 -101 1 -110 1 -.names system_timer.timerB.counter[9] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14688 -01 1 -10 1 -.names system_timer.timerB.counter[8] $abc$18544$new_n2826 $abc$18544$auto$rtlil.cc:2693:MuxGate$14690 -01 1 -10 1 -.names system_timer.timerB.counter[7] $abc$18544$new_n2827 $abc$18544$auto$rtlil.cc:2693:MuxGate$14692 -01 1 -10 1 -.names system_timer.timerB.counter[6] $abc$18544$new_n2828 $abc$18544$auto$rtlil.cc:2693:MuxGate$14694 -01 1 -10 1 -.names system_timer.timerB.counter[5] $abc$18544$new_n2829 $abc$18544$auto$rtlil.cc:2693:MuxGate$14696 -01 1 -10 1 -.names system_timer.timerB.counter[4] $abc$18544$new_n2830 $abc$18544$auto$rtlil.cc:2693:MuxGate$14698 -01 1 -10 1 -.names system_timer.timerB.counter[3] $abc$18544$new_n2831 $abc$18544$auto$rtlil.cc:2693:MuxGate$14700 -01 1 -10 1 -.names system_timer.timerB.counter[2] $abc$18544$new_n2832 $abc$18544$auto$rtlil.cc:2693:MuxGate$14702 -01 1 -10 1 -.names system_timer.timerB.counter[1] $abc$18544$new_n2833 $abc$18544$auto$rtlil.cc:2693:MuxGate$14704 -01 1 -10 1 -.names system_timer.timerB.counter[0] $abc$18544$new_n2834 $abc$18544$auto$rtlil.cc:2693:MuxGate$14706 -01 1 -10 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[32] jtagBridge_1.jtag_readArea_full_shifter[33] jtagBridge_1.system_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14708 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] $abc$18544$new_n2863 jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n2862 -1110 1 -.names jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n2863 -1100 1 -.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n2864 -1110 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[31] jtagBridge_1.jtag_readArea_full_shifter[32] jtagBridge_1.system_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14710 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[30] jtagBridge_1.jtag_readArea_full_shifter[31] jtagBridge_1.system_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14712 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[29] jtagBridge_1.jtag_readArea_full_shifter[30] jtagBridge_1.system_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14714 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[28] jtagBridge_1.jtag_readArea_full_shifter[29] jtagBridge_1.system_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14716 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[27] jtagBridge_1.jtag_readArea_full_shifter[28] jtagBridge_1.system_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14718 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[26] jtagBridge_1.jtag_readArea_full_shifter[27] jtagBridge_1.system_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14720 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[25] jtagBridge_1.jtag_readArea_full_shifter[26] jtagBridge_1.system_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14722 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[24] jtagBridge_1.jtag_readArea_full_shifter[25] jtagBridge_1.system_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14724 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[23] jtagBridge_1.jtag_readArea_full_shifter[24] jtagBridge_1.system_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14726 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[22] jtagBridge_1.jtag_readArea_full_shifter[23] jtagBridge_1.system_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14728 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[21] jtagBridge_1.jtag_readArea_full_shifter[22] jtagBridge_1.system_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14730 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[20] jtagBridge_1.jtag_readArea_full_shifter[21] jtagBridge_1.system_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14732 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[19] jtagBridge_1.jtag_readArea_full_shifter[20] jtagBridge_1.system_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14734 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[18] jtagBridge_1.jtag_readArea_full_shifter[19] jtagBridge_1.system_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14736 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[17] jtagBridge_1.jtag_readArea_full_shifter[18] jtagBridge_1.system_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14738 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[16] jtagBridge_1.jtag_readArea_full_shifter[17] jtagBridge_1.system_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14740 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[15] jtagBridge_1.jtag_readArea_full_shifter[16] jtagBridge_1.system_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14742 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[14] jtagBridge_1.jtag_readArea_full_shifter[15] jtagBridge_1.system_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14744 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[13] jtagBridge_1.jtag_readArea_full_shifter[14] jtagBridge_1.system_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14746 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[12] jtagBridge_1.jtag_readArea_full_shifter[13] jtagBridge_1.system_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14748 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[11] jtagBridge_1.jtag_readArea_full_shifter[12] jtagBridge_1.system_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14750 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[10] jtagBridge_1.jtag_readArea_full_shifter[11] jtagBridge_1.system_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14752 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[9] jtagBridge_1.jtag_readArea_full_shifter[10] jtagBridge_1.system_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14754 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[8] jtagBridge_1.jtag_readArea_full_shifter[9] jtagBridge_1.system_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14756 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[7] jtagBridge_1.jtag_readArea_full_shifter[8] jtagBridge_1.system_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14758 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[6] jtagBridge_1.jtag_readArea_full_shifter[7] jtagBridge_1.system_rsp_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14760 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[5] jtagBridge_1.jtag_readArea_full_shifter[6] jtagBridge_1.system_rsp_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14762 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[4] jtagBridge_1.jtag_readArea_full_shifter[5] jtagBridge_1.system_rsp_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14764 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[3] jtagBridge_1.jtag_readArea_full_shifter[4] jtagBridge_1.system_rsp_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14766 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[2] jtagBridge_1.jtag_readArea_full_shifter[3] jtagBridge_1.system_rsp_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14768 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.jtag_readArea_full_shifter[1] jtagBridge_1.system_rsp_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$14770 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[5] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] $abc$18544$new_n2897 $abc$18544$auto$rtlil.cc:2693:MuxGate$14772 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] $abc$18544$new_n2898 $abc$18544$new_n2897 -11 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.rx.break_counter[1] $abc$18544$new_n2898 -111 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[6] system_uartCtrl.uartCtrl_1.rx.break_counter[0] $abc$18544$new_n2900 system_uartCtrl.uartCtrl_1.rx.break_counter[1] system_uartCtrl.uartCtrl_1.io_readBreak -1110 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.break_counter[5] $abc$18544$new_n2900 -0000 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.break_counter[3] $abc$18544$new_n2897 $abc$18544$auto$rtlil.cc:2693:MuxGate$14774 -0011 1 -1000 1 -1001 1 -1010 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[3] $abc$18544$new_n2897 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14776 -010 1 -100 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] $abc$18544$new_n2898 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14778 -010 1 -100 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[1] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$14780 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$14782 -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[30] $abc$18544$new_n2907 jtagBridge_1.io_remote_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14784 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[30] $abc$18544$new_n2907 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 system_cpu._zz_lastStageRegFileWrite_payload_address[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2913 system_cpu._zz_lastStageRegFileWrite_payload_address[14] $abc$18544$new_n2908 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2912 system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2910 system_cpu._zz_lastStageRegFileWrite_payload_address[14] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2909 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2911 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] $abc$18544$new_n2910 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[7] $abc$18544$new_n2911 -000 1 -010 1 -100 1 -101 1 -.names system_cpu.memory_to_writeBack_MEMORY_ENABLE system_cpu.lastStageIsFiring $abc$18544$new_n2912 -11 1 -.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] $abc$18544$new_n2913 -000 1 -010 1 -100 1 -101 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2914 -10 1 -.names system_cpu.decode_to_execute_DO_EBREAK system_cpu.execute_arbitration_isValid $abc$18544$new_n2915 -11 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[29] $abc$18544$new_n2917 jtagBridge_1.io_remote_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14786 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[29] $abc$18544$new_n2917 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[28] $abc$18544$new_n2919 jtagBridge_1.io_remote_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14788 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[28] $abc$18544$new_n2919 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[27] $abc$18544$new_n2921 jtagBridge_1.io_remote_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14790 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[27] $abc$18544$new_n2921 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[26] $abc$18544$new_n2923 jtagBridge_1.io_remote_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14792 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[26] $abc$18544$new_n2923 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[25] $abc$18544$new_n2925 jtagBridge_1.io_remote_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14794 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[25] $abc$18544$new_n2925 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[24] $abc$18544$new_n2927 jtagBridge_1.io_remote_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14796 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[24] $abc$18544$new_n2927 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[23] $abc$18544$new_n2929 jtagBridge_1.io_remote_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14798 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[23] $abc$18544$new_n2929 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[22] $abc$18544$new_n2931 jtagBridge_1.io_remote_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14800 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[22] $abc$18544$new_n2931 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[21] $abc$18544$new_n2933 jtagBridge_1.io_remote_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14802 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[21] $abc$18544$new_n2933 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[20] $abc$18544$new_n2935 jtagBridge_1.io_remote_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14804 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[20] $abc$18544$new_n2935 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[19] $abc$18544$new_n2937 jtagBridge_1.io_remote_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14806 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[19] $abc$18544$new_n2937 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[18] $abc$18544$new_n2939 jtagBridge_1.io_remote_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14808 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[18] $abc$18544$new_n2939 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[17] $abc$18544$new_n2941 jtagBridge_1.io_remote_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14810 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[17] $abc$18544$new_n2941 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[16] $abc$18544$new_n2943 jtagBridge_1.io_remote_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14812 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[16] $abc$18544$new_n2943 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[15] $abc$18544$new_n2945 jtagBridge_1.io_remote_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14814 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 $abc$18544$new_n2946 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[15] $abc$18544$new_n2912 $abc$18544$new_n2945 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2913 system_cpu._zz_lastStageRegFileWrite_payload_address[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2946 -001 1 -010 1 -011 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[14] $abc$18544$new_n2948 jtagBridge_1.io_remote_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14816 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 $abc$18544$new_n2949 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[14] $abc$18544$new_n2912 $abc$18544$new_n2948 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2949 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[13] $abc$18544$new_n2951 jtagBridge_1.io_remote_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14818 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 $abc$18544$new_n2952 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[13] $abc$18544$new_n2912 $abc$18544$new_n2951 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2952 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[12] $abc$18544$new_n2954 jtagBridge_1.io_remote_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14820 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 $abc$18544$new_n2955 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[12] $abc$18544$new_n2912 $abc$18544$new_n2954 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2955 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[11] $abc$18544$new_n2957 jtagBridge_1.io_remote_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14822 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 $abc$18544$new_n2958 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[11] $abc$18544$new_n2912 $abc$18544$new_n2957 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2958 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[10] $abc$18544$new_n2960 jtagBridge_1.io_remote_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14824 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 $abc$18544$new_n2961 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[10] $abc$18544$new_n2912 $abc$18544$new_n2960 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2961 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[9] $abc$18544$new_n2963 jtagBridge_1.io_remote_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14826 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 $abc$18544$new_n2964 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[9] $abc$18544$new_n2912 $abc$18544$new_n2963 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2964 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[8] $abc$18544$new_n2966 jtagBridge_1.io_remote_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14828 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2909 $abc$18544$new_n2967 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[8] $abc$18544$new_n2912 $abc$18544$new_n2966 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2967 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[7] $abc$18544$new_n2969 jtagBridge_1.io_remote_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14830 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2912 $abc$18544$new_n2910 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[7] $abc$18544$new_n2969 -000 1 -010 1 -110 1 -111 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[6] $abc$18544$new_n2971 jtagBridge_1.io_remote_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14832 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2912 $abc$18544$new_n2972 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[6] $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] $abc$18544$new_n2971 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[6] $abc$18544$new_n2972 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[5] $abc$18544$new_n2974 jtagBridge_1.io_remote_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14834 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2912 $abc$18544$new_n2975 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[5] $abc$18544$new_n2974 -000 1 -010 1 -110 1 -111 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2976 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] $abc$18544$new_n2975 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[5] $abc$18544$new_n2976 -000 1 -010 1 -100 1 -101 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[4] $abc$18544$new_n2978 system_cpu.DebugPlugin_busReadDataReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14836 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2912 $abc$18544$new_n2979 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[4] $abc$18544$new_n2978 -000 1 -010 1 -110 1 -111 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2980 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] $abc$18544$new_n2979 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[4] $abc$18544$new_n2980 -000 1 -010 1 -100 1 -101 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[3] $abc$18544$new_n2982 system_cpu.DebugPlugin_busReadDataReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14838 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2912 $abc$18544$new_n2983 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[3] $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] $abc$18544$new_n2982 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[3] $abc$18544$new_n2983 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[2] $abc$18544$new_n2985 system_cpu.DebugPlugin_busReadDataReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14840 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2912 $abc$18544$new_n2986 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[2] $abc$18544$new_n2985 -000 1 -010 1 -110 1 -111 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2987 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] $abc$18544$new_n2986 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[2] $abc$18544$new_n2987 -000 1 -010 1 -100 1 -101 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] $abc$18544$new_n2989 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14842 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2989 -11 1 -.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2990 -1100 1 -.names system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$new_n2991 -1000 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2989 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14844 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2994 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14846 -001 1 -011 1 -110 1 -111 1 -.names system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2994 -1100 1 -.names $abc$18544$new_n2997 $abc$18544$new_n2998 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] $abc$18544$new_n2999 $abc$18544$auto$rtlil.cc:2693:MuxGate$14848 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2997 -11 1 -.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2998 -10 1 -.names system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2999 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] $abc$18544$new_n2998 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14850 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2998 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14852 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3003 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14854 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n3003 -1000 1 -.names $abc$18544$new_n3005 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3010 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14914 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$18544$new_n2991 $abc$18544$new_n3008 $abc$18544$new_n3009 $abc$18544$new_n3005 -100 1 -.names system_uartCtrl.uartCtrl_1.rx.sampler_tick $abc$18544$new_n3007 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3006 -1100 1 -.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3007 -000 1 -.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2997 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n3008 -10000 1 -10001 1 -10010 1 -.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n2999 $abc$18544$new_n3009 -11 1 -.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3010 -100 1 -.names $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2991 $abc$18544$new_n3009 $abc$18544$auto$rtlil.cc:2693:MuxGate$14916 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14918 -001 1 -011 1 -110 1 -111 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid $abc$18544$new_n3014 system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3013 -100 1 -101 1 -111 1 -.names system_uartCtrl.bridge_misc_doBreak $abc$18544$new_n3926 $abc$18544$new_n3017 $abc$18544$new_n3014 -000 1 -001 1 -010 1 -.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] $abc$18544$new_n3016 -1100 1 -.names system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] $abc$18544$new_n3017 -100 1 -.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14920 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14922 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14924 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n5035 $abc$18544$new_n3014 $abc$18544$new_n3022 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire -000 1 -001 1 -010 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3022 -10 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3029 $abc$18544$auto$rtlil.cc:2693:MuxGate$14926 -01 1 -10 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3030 $abc$18544$new_n3029 -11 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3031 $abc$18544$new_n3030 -11 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$new_n3031 -11 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3030 $abc$18544$auto$rtlil.cc:2693:MuxGate$14928 -01 1 -10 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3031 $abc$18544$auto$rtlil.cc:2693:MuxGate$14930 -01 1 -10 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$auto$rtlil.cc:2693:MuxGate$14932 -01 1 -10 1 -.names $abc$18544$new_n2712 $abc$18544$new_n3042 apb3Router_1._zz_selIndex $abc$18544$new_n3036 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 -1110 1 -.names $abc$18544$new_n3037 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3036 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -.names $abc$18544$new_n3038 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n3037 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3038 -0000 1 -0001 1 -0011 1 -1100 1 -1101 1 -1111 1 -.names $abc$18544$new_n3041 $abc$18544$new_n3040 apb3Router_1._zz_selIndex -11 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[17] apb3Router_1.io_input_PADDR[18] apb3Router_1.io_input_PADDR[19] $abc$18544$new_n3040 -1000 1 -.names apb3Router_1.io_input_PADDR[16] apb3Router_1.io_input_PADDR[12] apb3Router_1.io_input_PADDR[13] apb3Router_1.io_input_PADDR[14] apb3Router_1.io_input_PADDR[15] $abc$18544$new_n3041 -10000 1 -.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3042 -10 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3044 $abc$18544$auto$rtlil.cc:2693:MuxGate$14934 -01 1 -10 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3045 $abc$18544$new_n3044 -11 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3046 $abc$18544$new_n3045 -11 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 $abc$18544$new_n3046 -11 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3045 $abc$18544$auto$rtlil.cc:2693:MuxGate$14936 -01 1 -10 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3046 $abc$18544$auto$rtlil.cc:2693:MuxGate$14938 -01 1 -10 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$14940 -01 1 -10 1 -.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14942 -001 1 -011 1 -110 1 -111 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n3052 $abc$18544$new_n3051 -10 1 -.names system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3042 apb3Router_1._zz_selIndex system_apbBridge.pipelinedMemoryBusStage_rsp_valid $abc$18544$new_n3052 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -.names apb3Router_1.io_input_PENABLE apb3Router_1.io_input_PWRITE system_apbBridge.pipelinedMemoryBusStage_rsp_valid -10 1 -.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14944 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14946 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14948 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n5038 $abc$18544$new_n3052 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire -000 1 -001 1 -010 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3064 $abc$18544$auto$rtlil.cc:2693:MuxGate$14950 -01 1 -10 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3065 $abc$18544$new_n3064 -11 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3066 $abc$18544$new_n3065 -11 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$new_n3066 -11 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3065 $abc$18544$auto$rtlil.cc:2693:MuxGate$14952 -01 1 -10 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3066 $abc$18544$auto$rtlil.cc:2693:MuxGate$14954 -01 1 -10 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$auto$rtlil.cc:2693:MuxGate$14956 -01 1 -10 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid $abc$18544$new_n3071 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 -10 1 -.names $abc$18544$new_n3072 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3071 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -.names $abc$18544$new_n3073 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n3072 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] $abc$18544$new_n3073 -0000 1 -0001 1 -0011 1 -1100 1 -1101 1 -1111 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3075 $abc$18544$auto$rtlil.cc:2693:MuxGate$14958 -01 1 -10 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3076 $abc$18544$new_n3075 -11 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3077 $abc$18544$new_n3076 -11 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 $abc$18544$new_n3077 -11 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3076 $abc$18544$auto$rtlil.cc:2693:MuxGate$14960 -01 1 -10 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3077 $abc$18544$auto$rtlil.cc:2693:MuxGate$14962 -01 1 -10 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$14964 -01 1 -10 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[30] io_gpioA_write[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14966 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3040 $abc$18544$new_n2723 $abc$18544$new_n2711 $abc$18544$new_n2712 $abc$18544$new_n3082 -1111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[29] io_gpioA_write[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14968 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[28] io_gpioA_write[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14970 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[27] io_gpioA_write[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14972 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[26] io_gpioA_write[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14974 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[25] io_gpioA_write[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14976 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[24] io_gpioA_write[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14978 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[23] io_gpioA_write[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14980 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[22] io_gpioA_write[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14982 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[21] io_gpioA_write[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14984 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[20] io_gpioA_write[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14986 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[19] io_gpioA_write[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14988 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[18] io_gpioA_write[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14990 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[17] io_gpioA_write[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14992 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[16] io_gpioA_write[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14994 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[15] io_gpioA_write[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14996 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[14] io_gpioA_write[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14998 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[13] io_gpioA_write[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15000 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[12] io_gpioA_write[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15002 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_3 io_gpioA_write[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15004 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l379 io_gpioA_write[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15006 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_2 io_gpioA_write[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15008 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[8] io_gpioA_write[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15010 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[7] io_gpioA_write[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15012 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[6] io_gpioA_write[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15014 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[5] io_gpioA_write[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15016 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[4] io_gpioA_write[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15018 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[3] io_gpioA_write[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15020 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[2] io_gpioA_write[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15022 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_1 io_gpioA_write[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15024 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347 io_gpioA_write[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15026 -001 1 -011 1 -110 1 -111 1 -.names systemDebugger_1.dispatcher_counter[1] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last systemDebugger_1.dispatcher_counter[0] jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$15028 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names systemDebugger_1.dispatcher_counter[0] jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$15030 -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[65] systemDebugger_1._zz_io_mem_cmd_payload_address[66] $abc$18544$auto$rtlil.cc:2693:MuxGate$15098 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.io_mem_cmd_payload_wr systemDebugger_1._zz_io_mem_cmd_payload_address[65] $abc$18544$auto$rtlil.cc:2693:MuxGate$15100 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[63] systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$15102 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[62] systemDebugger_1._zz_io_mem_cmd_payload_address[63] $abc$18544$auto$rtlil.cc:2693:MuxGate$15104 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[61] systemDebugger_1._zz_io_mem_cmd_payload_address[62] $abc$18544$auto$rtlil.cc:2693:MuxGate$15106 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[60] systemDebugger_1._zz_io_mem_cmd_payload_address[61] $abc$18544$auto$rtlil.cc:2693:MuxGate$15108 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[59] systemDebugger_1._zz_io_mem_cmd_payload_address[60] $abc$18544$auto$rtlil.cc:2693:MuxGate$15110 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l288_1 systemDebugger_1._zz_io_mem_cmd_payload_address[59] $abc$18544$auto$rtlil.cc:2693:MuxGate$15112 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l285_1 system_cpu.when_DebugPlugin_l288_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15114 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l284_1 system_cpu.when_DebugPlugin_l285_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15116 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[55] system_cpu.when_DebugPlugin_l284_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15118 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[54] systemDebugger_1._zz_io_mem_cmd_payload_address[55] $abc$18544$auto$rtlil.cc:2693:MuxGate$15120 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[53] systemDebugger_1._zz_io_mem_cmd_payload_address[54] $abc$18544$auto$rtlil.cc:2693:MuxGate$15122 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[52] systemDebugger_1._zz_io_mem_cmd_payload_address[53] $abc$18544$auto$rtlil.cc:2693:MuxGate$15124 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[51] systemDebugger_1._zz_io_mem_cmd_payload_address[52] $abc$18544$auto$rtlil.cc:2693:MuxGate$15126 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l288 systemDebugger_1._zz_io_mem_cmd_payload_address[51] $abc$18544$auto$rtlil.cc:2693:MuxGate$15128 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l285 system_cpu.when_DebugPlugin_l288 $abc$18544$auto$rtlil.cc:2693:MuxGate$15130 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l284 system_cpu.when_DebugPlugin_l285 $abc$18544$auto$rtlil.cc:2693:MuxGate$15132 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[47] system_cpu.when_DebugPlugin_l284 $abc$18544$auto$rtlil.cc:2693:MuxGate$15134 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[46] systemDebugger_1._zz_io_mem_cmd_payload_address[47] $abc$18544$auto$rtlil.cc:2693:MuxGate$15136 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[45] systemDebugger_1._zz_io_mem_cmd_payload_address[46] $abc$18544$auto$rtlil.cc:2693:MuxGate$15138 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[44] systemDebugger_1._zz_io_mem_cmd_payload_address[45] $abc$18544$auto$rtlil.cc:2693:MuxGate$15140 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[43] systemDebugger_1._zz_io_mem_cmd_payload_address[44] $abc$18544$auto$rtlil.cc:2693:MuxGate$15142 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[42] systemDebugger_1._zz_io_mem_cmd_payload_address[43] $abc$18544$auto$rtlil.cc:2693:MuxGate$15144 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[41] systemDebugger_1._zz_io_mem_cmd_payload_address[42] $abc$18544$auto$rtlil.cc:2693:MuxGate$15146 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[40] systemDebugger_1._zz_io_mem_cmd_payload_address[41] $abc$18544$auto$rtlil.cc:2693:MuxGate$15148 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[39] systemDebugger_1._zz_io_mem_cmd_payload_address[40] $abc$18544$auto$rtlil.cc:2693:MuxGate$15150 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[38] systemDebugger_1._zz_io_mem_cmd_payload_address[39] $abc$18544$auto$rtlil.cc:2693:MuxGate$15152 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[37] systemDebugger_1._zz_io_mem_cmd_payload_address[38] $abc$18544$auto$rtlil.cc:2693:MuxGate$15154 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[36] systemDebugger_1._zz_io_mem_cmd_payload_address[37] $abc$18544$auto$rtlil.cc:2693:MuxGate$15156 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[35] systemDebugger_1._zz_io_mem_cmd_payload_address[36] $abc$18544$auto$rtlil.cc:2693:MuxGate$15158 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[34] systemDebugger_1._zz_io_mem_cmd_payload_address[35] $abc$18544$auto$rtlil.cc:2693:MuxGate$15160 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[33] systemDebugger_1._zz_io_mem_cmd_payload_address[34] $abc$18544$auto$rtlil.cc:2693:MuxGate$15162 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[32] systemDebugger_1._zz_io_mem_cmd_payload_address[33] $abc$18544$auto$rtlil.cc:2693:MuxGate$15164 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[31] systemDebugger_1._zz_io_mem_cmd_payload_address[32] $abc$18544$auto$rtlil.cc:2693:MuxGate$15166 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[30] systemDebugger_1._zz_io_mem_cmd_payload_address[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$15168 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[29] systemDebugger_1._zz_io_mem_cmd_payload_address[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15170 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[28] systemDebugger_1._zz_io_mem_cmd_payload_address[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15172 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[27] systemDebugger_1._zz_io_mem_cmd_payload_address[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15174 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[26] systemDebugger_1._zz_io_mem_cmd_payload_address[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15176 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[25] systemDebugger_1._zz_io_mem_cmd_payload_address[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15178 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[24] systemDebugger_1._zz_io_mem_cmd_payload_address[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15180 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[23] systemDebugger_1._zz_io_mem_cmd_payload_address[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15182 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[22] systemDebugger_1._zz_io_mem_cmd_payload_address[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15184 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[21] systemDebugger_1._zz_io_mem_cmd_payload_address[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15186 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[20] systemDebugger_1._zz_io_mem_cmd_payload_address[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15188 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[19] systemDebugger_1._zz_io_mem_cmd_payload_address[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15190 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[18] systemDebugger_1._zz_io_mem_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15192 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[17] systemDebugger_1._zz_io_mem_cmd_payload_address[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15194 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[16] systemDebugger_1._zz_io_mem_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15196 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[15] systemDebugger_1._zz_io_mem_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15198 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[14] systemDebugger_1._zz_io_mem_cmd_payload_address[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15200 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[13] systemDebugger_1._zz_io_mem_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15202 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[12] systemDebugger_1._zz_io_mem_cmd_payload_address[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15204 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[11] systemDebugger_1._zz_io_mem_cmd_payload_address[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15206 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[10] systemDebugger_1._zz_io_mem_cmd_payload_address[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15208 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[9] systemDebugger_1._zz_io_mem_cmd_payload_address[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15210 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[8] systemDebugger_1._zz_io_mem_cmd_payload_address[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15212 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[7] systemDebugger_1._zz_io_mem_cmd_payload_address[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15214 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[6] systemDebugger_1._zz_io_mem_cmd_payload_address[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15216 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[5] systemDebugger_1._zz_io_mem_cmd_payload_address[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15218 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[4] systemDebugger_1._zz_io_mem_cmd_payload_address[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15220 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[3] systemDebugger_1._zz_io_mem_cmd_payload_address[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15222 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[2] systemDebugger_1._zz_io_mem_cmd_payload_address[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15224 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[6] systemDebugger_1.dispatcher_header[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15230 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[5] systemDebugger_1.dispatcher_header[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15232 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[4] systemDebugger_1.dispatcher_header[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15234 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[3] systemDebugger_1.dispatcher_header[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15236 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[2] systemDebugger_1.dispatcher_header[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15238 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[1] systemDebugger_1.dispatcher_header[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15240 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[0] systemDebugger_1.dispatcher_header[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15242 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[2] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15296 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n3187 -1000 1 -.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[1] jtagBridge_1._zz_jtag_tap_isBypass[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15298 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_tdoIr jtagBridge_1._zz_jtag_tap_isBypass[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15300 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[31] jtagBridge_1.jtag_idcodeArea_shifter[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15302 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2864 jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n3191 -11000 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[30] jtagBridge_1.jtag_idcodeArea_shifter[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15304 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[29] jtagBridge_1.jtag_idcodeArea_shifter[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15306 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[28] jtagBridge_1.jtag_idcodeArea_shifter[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15308 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[27] jtagBridge_1.jtag_idcodeArea_shifter[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15310 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[26] jtagBridge_1.jtag_idcodeArea_shifter[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15312 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[25] jtagBridge_1.jtag_idcodeArea_shifter[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15314 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[24] jtagBridge_1.jtag_idcodeArea_shifter[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15316 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[23] jtagBridge_1.jtag_idcodeArea_shifter[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15318 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[22] jtagBridge_1.jtag_idcodeArea_shifter[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15320 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[21] jtagBridge_1.jtag_idcodeArea_shifter[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15322 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[20] jtagBridge_1.jtag_idcodeArea_shifter[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15324 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[19] jtagBridge_1.jtag_idcodeArea_shifter[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15326 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[18] jtagBridge_1.jtag_idcodeArea_shifter[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15328 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[17] jtagBridge_1.jtag_idcodeArea_shifter[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15330 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[16] jtagBridge_1.jtag_idcodeArea_shifter[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15332 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[15] jtagBridge_1.jtag_idcodeArea_shifter[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15334 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[14] jtagBridge_1.jtag_idcodeArea_shifter[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15336 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[13] jtagBridge_1.jtag_idcodeArea_shifter[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15338 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[12] jtagBridge_1.jtag_idcodeArea_shifter[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15340 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[11] jtagBridge_1.jtag_idcodeArea_shifter[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15342 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[10] jtagBridge_1.jtag_idcodeArea_shifter[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15344 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[9] jtagBridge_1.jtag_idcodeArea_shifter[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15346 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[8] jtagBridge_1.jtag_idcodeArea_shifter[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15348 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[7] jtagBridge_1.jtag_idcodeArea_shifter[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15350 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[6] jtagBridge_1.jtag_idcodeArea_shifter[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15352 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[5] jtagBridge_1.jtag_idcodeArea_shifter[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15354 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[4] jtagBridge_1.jtag_idcodeArea_shifter[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15356 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[3] jtagBridge_1.jtag_idcodeArea_shifter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15358 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[2] jtagBridge_1.jtag_idcodeArea_shifter[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15360 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[1] jtagBridge_1.jtag_idcodeArea_ctrl_tdo $abc$18544$auto$rtlil.cc:2693:MuxGate$15362 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[30] jtagBridge_1.system_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15364 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[29] jtagBridge_1.system_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15366 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[28] jtagBridge_1.system_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15368 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[27] jtagBridge_1.system_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15370 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[26] jtagBridge_1.system_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15372 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[25] jtagBridge_1.system_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15374 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[24] jtagBridge_1.system_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15376 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[23] jtagBridge_1.system_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15378 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[22] jtagBridge_1.system_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15380 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[21] jtagBridge_1.system_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15382 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[20] jtagBridge_1.system_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15384 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[19] jtagBridge_1.system_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15386 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[18] jtagBridge_1.system_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15388 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[17] jtagBridge_1.system_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15390 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[16] jtagBridge_1.system_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15392 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[15] jtagBridge_1.system_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15394 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[14] jtagBridge_1.system_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15396 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[13] jtagBridge_1.system_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15398 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[12] jtagBridge_1.system_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15400 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[11] jtagBridge_1.system_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15402 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[10] jtagBridge_1.system_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15404 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[9] jtagBridge_1.system_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15406 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[8] jtagBridge_1.system_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15408 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[7] jtagBridge_1.system_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15410 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[6] jtagBridge_1.system_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15412 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[5] jtagBridge_1.system_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15414 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[4] system_cpu.DebugPlugin_busReadDataReg[4] system_cpu.DebugPlugin_stepIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15416 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[3] system_cpu.DebugPlugin_busReadDataReg[3] system_cpu.DebugPlugin_haltedByBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$15418 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[2] system_cpu.DebugPlugin_busReadDataReg[2] system_cpu.DebugPlugin_isPipBusy $abc$18544$auto$rtlil.cc:2693:MuxGate$15420 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[1] system_cpu.DebugPlugin_busReadDataReg[1] system_cpu.DebugPlugin_haltIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15422 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[0] system_cpu.DebugPlugin_busReadDataReg[0] system_cpu.DebugPlugin_resetIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15424 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n3254 $abc$18544$new_n3260 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15620 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names $abc$18544$new_n3258 $abc$18544$new_n3255 $abc$18544$new_n3254 -11 1 -.names $abc$18544$new_n2915 $abc$18544$new_n3256 $abc$18544$new_n3255 -00 1 -.names system_cpu.execute_to_memory_MEMORY_ENABLE system_cpu.memory_arbitration_isValid system_cpu.execute_to_memory_MEMORY_STORE $abc$18544$new_n3257 system_mainBusArbiter.rspTarget $abc$18544$new_n3256 -11000 1 -11010 1 -11011 1 -.names system_ram._zz_io_bus_rsp_valid system_apbBridge.io_pipelinedMemoryBus_rsp_valid system_mainBusArbiter.rspPending system_mainBusDecoder_logic_rspNoHit $abc$18544$new_n3257 -0000 1 -0001 1 -0010 1 -.names system_cpu.execute_arbitration_isValid $abc$18544$new_n3259 system_cpu._zz_execute_SHIFT_CTRL[0] system_cpu._zz_execute_SHIFT_CTRL[1] $abc$18544$new_n3258 -1001 1 -1010 1 -1011 1 -.names system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] system_cpu.decode_to_execute_SRC2[2] system_cpu.decode_to_execute_SRC2[3] system_cpu.decode_to_execute_SRC2[4] $abc$18544$new_n3259 -00000 1 -.names $abc$18544$new_n3261 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[2] $abc$18544$new_n3260 -1000 1 -1010 1 -1100 1 -1101 1 -.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.execute_LightShifterPlugin_amplitudeReg[1] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] $abc$18544$new_n3261 -00000 1 -00100 1 -01000 1 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names $abc$18544$new_n3254 $abc$18544$new_n3261 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15622 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names $abc$18544$new_n3254 $abc$18544$new_n3264 system_cpu.execute_LightShifterPlugin_amplitudeReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15624 -001 1 -011 1 -100 1 -101 1 -.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.execute_LightShifterPlugin_amplitudeReg[1] $abc$18544$new_n3264 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10010 1 -10101 1 -10110 1 -11001 1 -11010 1 -11101 1 -11110 1 -.names $abc$18544$new_n3254 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.decode_to_execute_SRC2[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15626 -0010 1 -0011 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[30] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15752 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 $abc$18544$new_n3318 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3267 -100 1 -110 1 -111 1 -.names $abc$18544$new_n3269 system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[2] system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3268 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n3308 $abc$18544$new_n3270 $abc$18544$new_n3317 $abc$18544$new_n3269 -101 1 -110 1 -111 1 -.names $abc$18544$new_n5050 $abc$18544$new_n3307 $abc$18544$new_n5041 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$18544$new_n3270 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$18544$new_n3273 system_cpu.execute_to_memory_INSTRUCTION[9] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.execute_to_memory_INSTRUCTION[7] $abc$18544$new_n3272 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$18544$new_n3274 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu.execute_to_memory_INSTRUCTION[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] system_cpu.execute_to_memory_INSTRUCTION[11] $abc$18544$new_n3273 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n3275 system_cpu.execute_to_memory_INSTRUCTION[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.execute_to_memory_INSTRUCTION[7] $abc$18544$new_n3274 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names system_cpu.execute_to_memory_REGFILE_WRITE_VALID system_cpu.memory_arbitration_isValid $abc$18544$new_n3275 -11 1 -.names system_cpu._zz_lastStageRegFileWrite_valid system_cpu.lastStageIsFiring system_cpu.HazardSimplePlugin_writeBackWrites_valid -11 1 -.names system_cpu.HazardSimplePlugin_writeBackBuffer_valid system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n3288 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$18544$new_n3297 $abc$18544$new_n3292 $abc$18544$new_n3294 $abc$18544$new_n3295 $abc$18544$new_n3291 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3293 system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n3292 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n3293 -00 1 -11 1 -.names $abc$18544$new_n3275 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.execute_to_memory_INSTRUCTION[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.execute_to_memory_INSTRUCTION[11] $abc$18544$new_n3294 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n3296 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.execute_to_memory_INSTRUCTION[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu.execute_to_memory_INSTRUCTION[10] $abc$18544$new_n3295 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.execute_to_memory_INSTRUCTION[9] $abc$18544$new_n3296 -00 1 -11 1 -.names system_cpu.HazardSimplePlugin_writeBackBuffer_valid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$18544$new_n3297 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.HazardSimplePlugin_writeBackWrites_valid system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n3299 -100 1 -111 1 -.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] $abc$18544$new_n3300 -0000 1 -0001 1 -0011 1 -1100 1 -1101 1 -1111 1 -.names system_cpu.decode_to_execute_REGFILE_WRITE_VALID system_cpu.execute_arbitration_isValid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n3304 -1100 1 -1111 1 -.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n3306 -10 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$new_n3307 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3315 $abc$18544$new_n3309 system_cpu.lastStageIsFiring system_cpu._zz_writeBack_ENV_CTRL $abc$18544$new_n3308 -1100 1 -1101 1 -1110 1 -.names $abc$18544$new_n3313 $abc$18544$new_n3255 $abc$18544$new_n3258 $abc$18544$new_n3310 $abc$18544$new_n3309 -1100 1 -1101 1 -1111 1 -.names $abc$18544$new_n3312 $abc$18544$new_n3311 $abc$18544$new_n3310 -11 1 -.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[1] system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[1] system_cpu.decode_to_execute_SRC2[2] $abc$18544$new_n3311 -00000 1 -00100 1 -01000 1 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[4] system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] system_cpu.decode_to_execute_SRC2[4] $abc$18544$new_n3312 -00000 1 -00100 1 -01000 1 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names system_cpu.execute_arbitration_isValid system_cpu.decode_to_execute_IS_CSR $abc$18544$new_n3314 system_cpu.decode_to_execute_MEMORY_ENABLE system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3313 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11100 1 -11101 1 -11110 1 -.names system_cpu.lastStageIsFiring system_cpu.memory_arbitration_isValid $abc$18544$new_n3314 -00 1 -.names $abc$18544$new_n3316 system_cpu._zz_memory_ENV_CTRL system_cpu.memory_arbitration_isValid system_cpu._zz_execute_ENV_CTRL system_cpu.execute_arbitration_isValid $abc$18544$new_n3315 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names system_cpu.CsrPlugin_interrupt_valid system_cpu.DebugPlugin_haltIt system_cpu.DebugPlugin_stepIt $abc$18544$new_n3317 $abc$18544$new_n3316 -1000 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_valid 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system_cpu.BranchPlugin_jumpInterface_payload[11] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[11] $abc$18544$new_n3773 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[10] $abc$18544$new_n3698 $abc$18544$new_n3775 $abc$18544$auto$rtlil.cc:2693:MuxGate$16074 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.BranchPlugin_jumpInterface_payload[10] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[10] $abc$18544$new_n3775 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[9] $abc$18544$new_n3699 $abc$18544$new_n3777 $abc$18544$auto$rtlil.cc:2693:MuxGate$16076 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.BranchPlugin_jumpInterface_payload[9] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[9] $abc$18544$new_n3777 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[8] $abc$18544$new_n3700 $abc$18544$new_n3779 $abc$18544$auto$rtlil.cc:2693:MuxGate$16078 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.BranchPlugin_jumpInterface_payload[8] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[8] $abc$18544$new_n3779 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[7] $abc$18544$new_n3701 $abc$18544$new_n3781 $abc$18544$auto$rtlil.cc:2693:MuxGate$16080 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.BranchPlugin_jumpInterface_payload[7] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[7] $abc$18544$new_n3781 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[6] $abc$18544$new_n3702 $abc$18544$new_n3783 $abc$18544$auto$rtlil.cc:2693:MuxGate$16082 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.BranchPlugin_jumpInterface_payload[6] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[6] $abc$18544$new_n3783 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[5] $abc$18544$new_n3703 $abc$18544$new_n3785 $abc$18544$auto$rtlil.cc:2693:MuxGate$16084 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$18544$new_n3722 system_cpu.BranchPlugin_jumpInterface_payload[5] $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[5] $abc$18544$new_n3785 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[4] $abc$18544$new_n3704 $abc$18544$new_n3787 $abc$18544$auto$rtlil.cc:2693:MuxGate$16086 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.BranchPlugin_jumpInterface_payload[4] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[4] $abc$18544$new_n3787 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[3] $abc$18544$new_n3705 $abc$18544$new_n3789 $abc$18544$auto$rtlil.cc:2693:MuxGate$16088 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.BranchPlugin_jumpInterface_payload[3] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[3] $abc$18544$new_n3789 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[2] system_cpu.IBusSimplePlugin_fetchPc_inc $abc$18544$new_n3791 $abc$18544$auto$rtlil.cc:2693:MuxGate$16090 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.BranchPlugin_jumpInterface_payload[2] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[2] $abc$18544$new_n3791 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] system_cpu.CsrPlugin_mepc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16092 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] system_cpu.CsrPlugin_mepc[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16094 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] system_cpu.CsrPlugin_mepc[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16096 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] system_cpu.CsrPlugin_mepc[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16098 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] system_cpu.CsrPlugin_mepc[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16100 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] system_cpu.CsrPlugin_mepc[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16102 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] system_cpu.CsrPlugin_mepc[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16104 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] system_cpu.CsrPlugin_mepc[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16106 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] system_cpu.CsrPlugin_mepc[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16108 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] system_cpu.CsrPlugin_mepc[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16110 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] system_cpu.CsrPlugin_mepc[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16112 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] system_cpu.CsrPlugin_mepc[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16114 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] system_cpu.CsrPlugin_mepc[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16116 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] system_cpu.CsrPlugin_mepc[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16118 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] system_cpu.CsrPlugin_mepc[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16120 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] system_cpu.CsrPlugin_mepc[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16122 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu.CsrPlugin_mepc[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16124 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu.CsrPlugin_mepc[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16126 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu.CsrPlugin_mepc[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16128 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu.CsrPlugin_mepc[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16130 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.CsrPlugin_mepc[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16132 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] system_cpu.CsrPlugin_mepc[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16134 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] system_cpu.CsrPlugin_mepc[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16136 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.CsrPlugin_mepc[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16138 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.CsrPlugin_mepc[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16140 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.CsrPlugin_mepc[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16142 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] system_cpu.CsrPlugin_mepc[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16144 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu.CsrPlugin_mepc[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16146 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu.CsrPlugin_mepc[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16148 -001 1 -011 1 -110 1 -111 1 -.names system_cpu.lastStageIsFiring $abc$18544$new_n2915 $abc$18544$new_n3822 system_cpu.DebugPlugin_busReadDataReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16152 -0001 1 -0011 1 -1000 1 -1001 1 -.names $abc$18544$new_n2912 $abc$18544$new_n3823 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[0] $abc$18544$new_n3822 -000 1 -010 1 -110 1 -111 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n3824 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] $abc$18544$new_n3823 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[0] $abc$18544$new_n3824 -000 1 -010 1 -100 1 -101 1 -.names jtagBridge_1.jtag_tap_instructionShift[3] $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_instructionShift[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16156 -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names $abc$18544$new_n3827 $abc$18544$new_n2864 $abc$18544$new_n3826 -00 1 -.names jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] $abc$18544$new_n3827 -1000 1 -.names jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[3] $abc$18544$new_n3828 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names jtagBridge_1.jtag_tap_instructionShift[2] $abc$18544$new_n3826 jtagBridge_1.jtag_tap_instructionShift[1] $abc$18544$new_n3828 $abc$18544$auto$rtlil.cc:2693:MuxGate$16160 -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names jtagBridge_1.jtag_tap_instructionShift[1] $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_tdoIr $abc$18544$auto$rtlil.cc:2693:MuxGate$16164 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$new_n3832 $abc$18544$auto$rtlil.cc:2693:MuxGate$16166 -0100 1 -0101 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1110 1 -1111 1 -.names system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3269 $abc$18544$new_n3833 $abc$18544$new_n3832 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3837 $abc$18544$new_n3834 $abc$18544$new_n3833 -111 1 -.names systemDebugger_1.dispatcher_dataLoaded $abc$18544$new_n3835 systemDebugger_1.dispatcher_header[0] systemDebugger_1.dispatcher_header[1] $abc$18544$new_n3834 -1100 1 -.names $abc$18544$new_n3836 systemDebugger_1.dispatcher_header[4] systemDebugger_1.dispatcher_header[5] systemDebugger_1.dispatcher_header[7] systemDebugger_1.dispatcher_header[6] $abc$18544$new_n3835 -10000 1 -.names systemDebugger_1.dispatcher_header[2] systemDebugger_1.dispatcher_header[3] $abc$18544$new_n3836 -00 1 -.names systemDebugger_1._zz_io_mem_cmd_payload_address[2] $abc$18544$new_n3838 $abc$18544$new_n3837 -11 1 -.names systemDebugger_1._zz_io_mem_cmd_payload_address[3] systemDebugger_1._zz_io_mem_cmd_payload_address[4] systemDebugger_1._zz_io_mem_cmd_payload_address[5] systemDebugger_1._zz_io_mem_cmd_payload_address[6] systemDebugger_1._zz_io_mem_cmd_payload_address[7] $abc$18544$new_n3838 -00000 1 -.names system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3832 system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16168 -010 1 -100 1 -101 1 -111 1 -.names resetCtrl_systemClkResetCounter[5] $abc$18544$new_n3841 resetCtrl_mainClkResetUnbuffered -00 1 -01 1 -10 1 -.names resetCtrl_systemClkResetCounter[4] $abc$18544$new_n3842 $abc$18544$new_n3841 -11 1 -.names resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] resetCtrl_systemClkResetCounter[2] resetCtrl_systemClkResetCounter[3] $abc$18544$new_n3842 -1111 1 -.names $abc$18544$new_n3842 resetCtrl_systemClkResetCounter[4] resetCtrl_systemClkResetCounter[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16228 -010 1 -011 1 -100 1 -101 1 -111 1 -.names resetCtrl_mainClkResetUnbuffered resetCtrl_systemClkResetCounter[3] resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] resetCtrl_systemClkResetCounter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16230 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names resetCtrl_mainClkResetUnbuffered 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$abc$18544$new_n3928 -100 1 -.names $abc$18544$new_n3926 $abc$18544$new_n3022 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16514 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n3723 system_cpu.CsrPlugin_interrupt_code[2] system_cpu.CsrPlugin_mcause_exceptionCode[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16516 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3720 $abc$18544$new_n3932 $abc$18544$new_n3934 $abc$18544$auto$rtlil.cc:2693:MuxGate$16518 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$18544$new_n3933 $abc$18544$new_n3711 io_apb_decoder.io_input_PSEL $abc$18544$new_n3932 -100 1 -101 1 -110 1 -.names $abc$18544$new_n3720 system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$18544$new_n3709 $abc$18544$new_n3933 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names system_mainBusArbiter.io_dBus_cmd_payload_wr system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3934 -11 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3710 $abc$18544$new_n3936 $abc$18544$auto$rtlil.cc:2693:MuxGate$16520 -001 1 -011 1 -100 1 -101 1 -.names system_cpu.decode_to_execute_MEMORY_ENABLE system_cpu.execute_arbitration_isValid $abc$18544$new_n3255 $abc$18544$new_n3851 $abc$18544$new_n3936 -1111 1 -.names $abc$18544$new_n3711 $abc$18544$new_n3933 system_mainBusDecoder_logic_rspSourceId io_apb_decoder.io_input_PSEL $abc$18544$auto$rtlil.cc:2693:MuxGate$16522 -0010 1 -0011 1 -1010 1 -1011 1 -1100 1 -1110 1 -1111 1 -.names $abc$18544$new_n3926 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16532 -010 1 -011 1 -101 1 -.names $abc$18544$auto$rtlil.cc:2582:Mux$3924 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3005 $abc$18544$auto$rtlil.cc:2693:MuxGate$16534 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$18544$new_n3005 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3941 $abc$18544$auto$rtlil.cc:2582:Mux$3924 -1100 1 -.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_parity system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3941 -11010 1 -11100 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[6] $abc$18544$new_n3943 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$16536 -010 1 -100 1 -.names system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.break_counter[5] $abc$18544$new_n2897 $abc$18544$new_n3943 -1111 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16538 -010 1 -011 1 -101 1 -111 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16540 -010 1 -011 1 -101 1 -111 1 -.names $abc$18544$new_n2997 $abc$18544$new_n2989 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] $abc$18544$new_n2999 $abc$18544$auto$rtlil.cc:2693:MuxGate$16542 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16544 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n5038 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n3052 $abc$18544$auto$rtlil.cc:2693:MuxGate$16546 -000 1 -001 1 -010 1 -011 1 -111 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3064 $abc$18544$auto$rtlil.cc:2693:MuxGate$16548 -011 1 -100 1 -101 1 -110 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3075 $abc$18544$auto$rtlil.cc:2693:MuxGate$16550 -011 1 -100 1 -101 1 -110 1 -.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16552 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n5035 $abc$18544$new_n3014 $abc$18544$new_n3022 $abc$18544$auto$rtlil.cc:2693:MuxGate$16554 -000 1 -001 1 -010 1 -011 1 -111 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3029 $abc$18544$auto$rtlil.cc:2693:MuxGate$16556 -011 1 -100 1 -101 1 -110 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3044 $abc$18544$auto$rtlil.cc:2693:MuxGate$16558 -011 1 -100 1 -101 1 -110 1 -.names system_uartCtrl.bridge_misc_readOverflowError system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid $abc$18544$new_n3071 $abc$18544$new_n3957 system_uartCtrl.when_BusSlaveFactory_l347_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16560 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2712 $abc$18544$new_n3958 apb3Router_1._zz_selIndex $abc$18544$new_n3957 -111 1 -.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2714 $abc$18544$new_n3958 -11 1 -.names system_uartCtrl.bridge_misc_readError $abc$18544$new_n3957 $abc$18544$new_n2991 $abc$18544$new_n3960 system_uartCtrl.when_BusSlaveFactory_l347 $abc$18544$auto$rtlil.cc:2693:MuxGate$16562 -00100 1 -00101 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names $abc$18544$new_n3941 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$new_n3960 -000 1 -001 1 -011 1 -.names $abc$18544$new_n3962 system_uartCtrl.when_BusSlaveFactory_l347_1 system_uartCtrl.bridge_interruptCtrl_readIntEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16564 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2712 $abc$18544$new_n3963 apb3Router_1._zz_selIndex $abc$18544$new_n3962 -111 1 -.names $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3963 -10 1 -.names $abc$18544$new_n3962 system_uartCtrl.when_BusSlaveFactory_l347 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16566 -001 1 -011 1 -110 1 -111 1 -.names system_timer.timerB.io_clear $abc$18544$new_n3968 system_timer.timerB.inhibitFull $abc$18544$new_n2835 $abc$18544$auto$rtlil.cc:2693:MuxGate$16568 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n2709 system_timer.timerBBridge_clearsEnable $abc$18544$new_n3967 $abc$18544$new_n2722 $abc$18544$new_n3969 system_timer.timerB.io_clear -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3968 system_timer.timerB.inhibitFull $abc$18544$new_n3967 -10 1 -.names $abc$18544$new_n5032 $abc$18544$new_n2835 $abc$18544$new_n3968 -10 1 -.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3893 apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n3969 -11100 1 -.names system_timer.timerA.io_clear $abc$18544$new_n3973 system_timer.timerA.inhibitFull $abc$18544$new_n2784 $abc$18544$auto$rtlil.cc:2693:MuxGate$16570 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names system_timer.timerABridge_clearsEnable $abc$18544$new_n3972 $abc$18544$new_n2709 $abc$18544$new_n3974 system_timer.timerA.io_clear -0011 1 -0111 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n3973 system_timer.timerA.inhibitFull $abc$18544$new_n3972 -10 1 -.names $abc$18544$new_n5029 $abc$18544$new_n2784 $abc$18544$new_n3973 -10 1 -.names $abc$18544$new_n3975 $abc$18544$new_n2723 $abc$18544$new_n3893 $abc$18544$new_n3974 -101 1 -110 1 -111 1 -.names apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n3975 -1000 1 -.names $abc$18544$new_n2821 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16572 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2708 apb3Router_1.io_input_PWDATA[16] system_timer.timerBBridge_clearsEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16574 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2708 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.timerBBridge_ticksEnable[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16576 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2716 apb3Router_1.io_input_PWDATA[16] system_timer.timerABridge_clearsEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16578 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2716 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.timerABridge_ticksEnable[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16580 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[15] system_timer.system_timer_timerB_io_limit_driver[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16582 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[15] system_timer.system_timer_timerA_io_limit_driver[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16584 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[15] system_timer._zz_io_limit[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16586 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3932 system_mainBusArbiter.rspTarget system_mainBusArbiter.io_dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16588 -0010 1 -0011 1 -1010 1 -1011 1 -1100 1 -1110 1 -1111 1 -.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[31] io_gpioA_writeEnable[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16590 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[31] io_gpioA_write[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16592 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3850 $abc$18544$new_n3318 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_mainBusArbiter.rspTarget $abc$18544$new_n3257 $abc$18544$auto$rtlil.cc:2693:MuxGate$16594 -00100 1 -01100 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[31] system_ram._zz_ram_port0[31] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16596 -001 1 -011 1 -110 1 -111 1 -.names resetCtrl_systemClkResetCounter[5] $abc$18544$new_n3841 $abc$18544$auto$rtlil.cc:2693:MuxGate$16598 -01 1 -10 1 -11 1 -.names system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$new_n3832 $abc$18544$auto$rtlil.cc:2693:MuxGate$16600 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n3851 $abc$18544$new_n3254 $abc$18544$new_n3310 system_cpu.execute_LightShifterPlugin_isActive $abc$18544$auto$rtlil.cc:2693:MuxGate$16602 -1001 1 -1011 1 -1100 1 -1101 1 -.names system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 $abc$18544$new_n3316 $abc$18544$new_n3851 $abc$18544$auto$rtlil.cc:2693:MuxGate$16604 -111 1 -.names $abc$18544$new_n3316 $abc$18544$new_n3851 $abc$18544$new_n3256 system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 $abc$18544$auto$rtlil.cc:2693:MuxGate$16606 -11001 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n3851 $abc$18544$new_n3316 $abc$18544$new_n3309 system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 $abc$18544$auto$rtlil.cc:2693:MuxGate$16608 -1101 1 -1110 1 -1111 1 -.names system_cpu._zz_execute_SrcPlugin_addSub_2[3] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3657 system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$18544$new_n3998 system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] system_cpu.CsrPlugin_mie_MSIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16610 -001 1 -011 1 -110 1 -111 1 -.names system_cpu.decode_to_execute_CSR_WRITE_OPCODE system_cpu.decode_to_execute_IS_CSR system_cpu.execute_CsrPlugin_csr_772 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$new_n3998 -11111 1 -.names $abc$18544$new_n3998 $abc$18544$new_n4000 system_cpu.CsrPlugin_mie_MTIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16612 -001 1 -011 1 -110 1 -111 1 -.names system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3628 $abc$18544$new_n4000 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$18544$new_n3998 $abc$18544$new_n4002 system_cpu.CsrPlugin_mie_MEIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16614 -001 1 -011 1 -110 1 -111 1 -.names system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3599 $abc$18544$new_n4002 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$18544$new_n3851 $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_injector_decodeInput_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3318 $abc$18544$auto$rtlil.cc:2693:MuxGate$16616 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$18544$new_n3851 $abc$18544$new_n4005 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3850 $abc$18544$auto$rtlil.cc:2693:MuxGate$16618 -0011 1 -0111 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n3932 system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4005 -10 1 -.names $abc$18544$new_n4007 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$18544$new_n3851 $abc$18544$new_n3708 $abc$18544$auto$rtlil.cc:2693:MuxGate$16620 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_cpu.IBusSimplePlugin_fetchPc_booted $abc$18544$new_n3708 $abc$18544$new_n3722 $abc$18544$new_n4008 system_cpu.DebugPlugin_haltIt $abc$18544$new_n4007 -11110 1 -.names $abc$18544$new_n3852 $abc$18544$new_n4009 system_cpu.DebugPlugin_stepIt $abc$18544$new_n4008 -000 1 -010 1 -011 1 -.names system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid system_cpu.IBusSimplePlugin_injector_decodeInput_valid $abc$18544$new_n4009 -000 1 -.names $abc$18544$new_n4007 system_cpu.IBusSimplePlugin_fetchPc_inc $abc$18544$new_n3707 $abc$18544$auto$rtlil.cc:2693:MuxGate$16622 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n3722 $abc$18544$new_n3309 system_cpu.execute_arbitration_isValid $abc$18544$new_n3851 $abc$18544$auto$rtlil.cc:2693:MuxGate$16624 -00111 1 -01111 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3851 $abc$18544$new_n3268 $abc$18544$new_n3317 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$auto$rtlil.cc:2693:MuxGate$16626 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -.names $abc$18544$new_n3255 $abc$18544$new_n4016 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] $abc$18544$new_n4014 $abc$18544$new_n3666 $abc$18544$auto$rtlil.cc:2693:MuxGate$16640 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -.names $abc$18544$new_n3466 $abc$18544$new_n3473 $abc$18544$new_n3678 $abc$18544$new_n4015 $abc$18544$new_n4014 -1000 1 -1001 1 -1101 1 -1111 1 -.names system_cpu._zz_execute_SrcPlugin_addSub_2[31] system_cpu.decode_to_execute_SRC2[31] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n4015 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$18544$new_n3258 system_cpu._zz_execute_SHIFT_CTRL[1] system_cpu._zz_execute_SHIFT_CTRL[0] $abc$18544$new_n3471 $abc$18544$new_n3480 $abc$18544$new_n4016 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n4018 system_cpu.execute_LightShifterPlugin_amplitudeReg[4] system_cpu.execute_LightShifterPlugin_isActive $abc$18544$new_n3254 system_cpu.decode_to_execute_SRC2[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16692 -00011 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -.names $abc$18544$new_n3260 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] $abc$18544$new_n4018 -1000 1 -1010 1 -1100 1 -1101 1 -.names system_cpu.CsrPlugin_mstatus_MIE system_cpu.CsrPlugin_interrupt_code[3] $abc$18544$new_n4020 system_cpu.CsrPlugin_mip_MEIP system_cpu.CsrPlugin_mie_MEIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16696 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n4021 system_cpu.CsrPlugin_mie_MTIE system_cpu.CsrPlugin_mip_MTIP $abc$18544$new_n4020 -100 1 -101 1 -110 1 -.names system_cpu.CsrPlugin_mip_MSIP system_cpu.CsrPlugin_mie_MSIE system_cpu.CsrPlugin_mie_MEIE system_cpu.CsrPlugin_mip_MEIP $abc$18544$new_n4021 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names system_cpu.CsrPlugin_mstatus_MIE $abc$18544$new_n4021 system_cpu.CsrPlugin_interrupt_code[2] $abc$18544$new_n4020 $abc$18544$auto$rtlil.cc:2693:MuxGate$16700 -0010 1 -0011 1 -0110 1 -0111 1 -1100 1 -1110 1 -1111 1 -.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[63] $abc$18544$new_n4024 system_cpu._zz_decode_SRC2 $abc$18544$auto$rtlil.cc:2693:MuxGate$16702 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] $abc$18544$new_n4024 -000 1 -001 1 -100 1 -110 1 -.names $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l288_1 system_cpu.DebugPlugin_disableEbreak system_cpu.when_DebugPlugin_l288 $abc$18544$auto$rtlil.cc:2693:MuxGate$16704 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -.names $abc$18544$new_n3834 systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3838 systemDebugger_1._zz_io_mem_cmd_payload_address[2] $abc$18544$new_n4026 -1110 1 -.names system_cpu.DebugPlugin_debugUsed $abc$18544$new_n3834 $abc$18544$auto$rtlil.cc:2693:MuxGate$16706 -01 1 -10 1 -11 1 -.names $abc$18544$new_n4026 systemDebugger_1._zz_io_mem_cmd_payload_address[36] system_cpu.DebugPlugin_stepIt $abc$18544$auto$rtlil.cc:2693:MuxGate$16708 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l284_1 system_cpu.DebugPlugin_resetIt system_cpu.when_DebugPlugin_l284 $abc$18544$auto$rtlil.cc:2693:MuxGate$16710 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PENABLE $abc$18544$new_n3933 $abc$18544$new_n3711 $abc$18544$auto$rtlil.cc:2693:MuxGate$16712 -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names systemDebugger_1.dispatcher_counter[2] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$new_n4032 jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$16724 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names systemDebugger_1.dispatcher_counter[0] systemDebugger_1.dispatcher_counter[1] $abc$18544$new_n4032 -11 1 -.names $abc$18544$new_n4034 $abc$18544$new_n4036 systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$16726 -000 1 -001 1 -011 1 -.names systemDebugger_1.dispatcher_dataLoaded systemDebugger_1.dispatcher_headerLoaded $abc$18544$new_n3833 $abc$18544$new_n4035 $abc$18544$new_n4034 -1100 1 -1101 1 -1111 1 -.names system_cpu.IBusSimplePlugin_injector_port_state[2] system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[1] $abc$18544$new_n4035 -100 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$new_n4032 systemDebugger_1.dispatcher_counter[2] $abc$18544$new_n4036 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n4034 systemDebugger_1.dispatcher_dataLoaded jtagBridge_1.flowCCByToggle_1.io_output_valid jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16728 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[7] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16730 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[66] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16732 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names jtagBridge_1.flowCCByToggle_1.io_input_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16734 -010 1 -011 1 -101 1 -111 1 -.names jtagBridge_1.flowCCByToggle_1.io_input_valid $abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] jtagBridge_1.flowCCByToggle_1.inputArea_data_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16736 -001 1 -011 1 -100 1 -101 1 -.names jtagBridge_1._zz_jtag_tap_isBypass[1] $abc$18544$new_n2864 jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] -11000 1 -.names jtagBridge_1.flowCCByToggle_1.inputArea_target jtagBridge_1.flowCCByToggle_1.io_input_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$16738 -01 1 -10 1 -.names jtagBridge_1.flowCCByToggle_1.outputArea_hit jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid -01 1 -10 1 -.names jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16740 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_last jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16742 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[31] jtagBridge_1.system_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16744 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[3] jtagBridge_1._zz_jtag_tap_isBypass[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16746 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3191 io_jtag_tdi jtagBridge_1.jtag_idcodeArea_shifter[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16748 -001 1 -011 1 -110 1 -111 1 -.names jtagBridge_1.system_rsp_valid jtagBridge_1.flowCCByToggle_1.io_output_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$16750 -10 1 -.names system_timer.timerA.counter[15] system_timer.timerA.counter[13] system_timer.timerA.counter[14] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$16752 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names system_timer.timerB.counter[15] system_timer.timerB.counter[13] system_timer.timerB.counter[14] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$16754 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[31] $abc$18544$new_n4054 $abc$18544$new_n4055 $abc$18544$auto$rtlil.cc:2693:MuxGate$16758 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_cpu.IBusSimplePlugin_cmd_payload_pc[30] $abc$18544$new_n3689 $abc$18544$new_n4054 -1111 1 -.names $abc$18544$new_n3722 system_cpu.BranchPlugin_jumpInterface_payload[31] $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[31] $abc$18544$new_n4055 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names $abc$18544$new_n3723 system_cpu.CsrPlugin_interrupt_code[3] system_cpu.CsrPlugin_mcause_exceptionCode[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16760 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[31] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16762 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu.CsrPlugin_mepc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16768 -001 1 -011 1 -110 1 -111 1 -.names system_cpu.lastStageIsFiring $abc$18544$new_n2915 $abc$18544$new_n4060 system_cpu.DebugPlugin_busReadDataReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16772 -0001 1 -0011 1 -1000 1 -1001 1 -.names $abc$18544$new_n2912 $abc$18544$new_n4061 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[1] $abc$18544$new_n4060 -000 1 -010 1 -110 1 -111 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n4062 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] $abc$18544$new_n4061 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[1] $abc$18544$new_n4062 -000 1 -010 1 -100 1 -101 1 -.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[31] $abc$18544$new_n4064 jtagBridge_1.io_remote_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16774 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[31] $abc$18544$new_n4064 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11101 1 -11110 1 -11111 1 -.names io_jtag_tdi $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_instructionShift[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16778 -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names $abc$18544$new_n2862 jtagBridge_1.jtag_readArea_full_shifter[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_readArea_full_shifter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16782 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[33] io_jtag_tdi jtagBridge_1.system_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16784 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14856 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14858 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[28] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14860 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[27] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14862 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[26] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14864 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14866 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14868 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[23] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14870 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[22] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14872 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14874 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14876 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[19] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14878 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[18] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14880 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14882 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14884 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[15] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14886 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14888 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14890 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[12] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14892 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[11] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14894 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14896 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[9] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14898 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14900 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14902 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14904 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[5] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14906 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14908 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14910 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14912 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[0] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$15034 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[30] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15036 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[29] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15038 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[28] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15040 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[27] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15042 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[26] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15044 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[25] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15046 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[24] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15048 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[23] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15050 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[22] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15052 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[21] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15054 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[20] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15056 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[19] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15058 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[18] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15060 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[17] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15062 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[16] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15064 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[15] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15066 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[14] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15068 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[13] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15070 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[12] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15072 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_3 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15074 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l379 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15076 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_2 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15078 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[8] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15080 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[7] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15082 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[6] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15084 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[5] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15086 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[4] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15088 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[3] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15090 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[2] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15092 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15094 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15096 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4130 system_cpu._zz_execute_SrcPlugin_addSub_2[30] system_cpu._zz_RegFilePlugin_regFile_port0[30] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15244 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] 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system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4142 -11110 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4144 system_cpu._zz_execute_SrcPlugin_addSub_2[24] system_cpu._zz_RegFilePlugin_regFile_port0[24] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15256 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] 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system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu._zz_decode_SRC2 $abc$18544$new_n4212 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4214 system_cpu.decode_to_execute_SRC2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15460 -001 1 -011 1 -100 1 -101 1 -.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu._zz_decode_SRC2 $abc$18544$new_n4214 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4216 system_cpu.decode_to_execute_SRC2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15462 -001 1 -011 1 -100 1 -101 1 -.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[12] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu._zz_decode_SRC2 $abc$18544$new_n4216 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4218 system_cpu.decode_to_execute_SRC2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15464 -001 1 -011 1 -100 1 -101 1 -.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[11] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu._zz_decode_SRC2 $abc$18544$new_n4218 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4220 system_cpu.decode_to_execute_SRC2[10] system_cpu._zz_RegFilePlugin_regFile_port1[10] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15466 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$18544$new_n4180 $abc$18544$new_n4220 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4222 system_cpu.decode_to_execute_SRC2[9] system_cpu._zz_RegFilePlugin_regFile_port1[9] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15468 -00000 1 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system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4180 $abc$18544$new_n4226 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4228 system_cpu.decode_to_execute_SRC2[6] system_cpu._zz_RegFilePlugin_regFile_port1[6] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15474 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4180 $abc$18544$new_n4228 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4230 system_cpu.decode_to_execute_SRC2[5] system_cpu._zz_RegFilePlugin_regFile_port1[5] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15476 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$18544$new_n4180 $abc$18544$new_n4230 -00000 1 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$abc$18544$new_n4233 -1000 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[4] $abc$18544$new_n4180 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$18544$new_n4235 $abc$18544$new_n4234 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 $abc$18544$new_n4235 -00 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4237 system_cpu.decode_to_execute_SRC2[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15480 -001 1 -011 1 -100 1 -101 1 -.names $abc$18544$new_n4238 system_cpu._zz_RegFilePlugin_regFile_port1[3] $abc$18544$new_n4180 $abc$18544$new_n4235 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4237 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$18544$new_n4233 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4238 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4240 system_cpu.decode_to_execute_SRC2[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n4235 $abc$18544$auto$rtlil.cc:2693:MuxGate$15482 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$18544$new_n4241 system_cpu._zz_RegFilePlugin_regFile_port1[2] $abc$18544$new_n4180 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$18544$new_n4233 $abc$18544$new_n4240 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4241 -11 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4243 system_cpu.decode_to_execute_SRC2[1] system_cpu._zz_RegFilePlugin_regFile_port1[1] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15484 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$new_n4235 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$18544$new_n4233 $abc$18544$new_n4243 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4245 system_cpu.decode_to_execute_SRC2[0] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$18544$new_n4235 $abc$18544$auto$rtlil.cc:2693:MuxGate$15486 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[0] $abc$18544$new_n4180 $abc$18544$new_n4233 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$18544$new_n4245 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[30] system_cpu.decode_to_execute_RS1[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15488 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[29] system_cpu.decode_to_execute_RS1[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15490 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[28] system_cpu.decode_to_execute_RS1[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15492 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[27] system_cpu.decode_to_execute_RS1[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15494 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[26] system_cpu.decode_to_execute_RS1[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15496 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[25] system_cpu.decode_to_execute_RS1[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15498 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[24] system_cpu.decode_to_execute_RS1[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15500 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[23] system_cpu.decode_to_execute_RS1[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15502 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[22] system_cpu.decode_to_execute_RS1[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15504 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[21] system_cpu.decode_to_execute_RS1[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15506 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[20] system_cpu.decode_to_execute_RS1[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15508 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[19] system_cpu.decode_to_execute_RS1[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15510 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[18] system_cpu.decode_to_execute_RS1[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15512 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[17] system_cpu.decode_to_execute_RS1[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15514 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[16] system_cpu.decode_to_execute_RS1[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15516 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[15] system_cpu.decode_to_execute_RS1[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15518 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[14] system_cpu.decode_to_execute_RS1[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15520 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[13] system_cpu.decode_to_execute_RS1[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15522 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[12] 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$abc$18544$new_n4352 system_cpu.BranchPlugin_jumpInterface_payload[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15830 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4389 $abc$18544$new_n4387 $abc$18544$new_n4419 system_cpu.BranchPlugin_jumpInterface_payload[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15832 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n4390 $abc$18544$new_n4388 $abc$18544$new_n4353 $abc$18544$new_n4419 -011 1 -101 1 -110 1 -111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4390 $abc$18544$new_n4388 $abc$18544$new_n4353 system_cpu.BranchPlugin_jumpInterface_payload[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15834 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4385 $abc$18544$new_n4383 $abc$18544$new_n4422 system_cpu.BranchPlugin_jumpInterface_payload[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15836 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n4386 $abc$18544$new_n4384 $abc$18544$new_n4354 $abc$18544$new_n4422 -011 1 -101 1 -110 1 -111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4386 $abc$18544$new_n4384 $abc$18544$new_n4354 system_cpu.BranchPlugin_jumpInterface_payload[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15838 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4381 $abc$18544$new_n4379 $abc$18544$new_n4425 system_cpu.BranchPlugin_jumpInterface_payload[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15840 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n4382 $abc$18544$new_n4380 $abc$18544$new_n4355 $abc$18544$new_n4425 -010 1 -100 1 -110 1 -111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4382 $abc$18544$new_n4380 $abc$18544$new_n4355 system_cpu.BranchPlugin_jumpInterface_payload[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15842 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4377 $abc$18544$new_n4375 $abc$18544$new_n4428 system_cpu.BranchPlugin_jumpInterface_payload[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15844 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n4378 $abc$18544$new_n4376 $abc$18544$new_n4356 $abc$18544$new_n4428 -011 1 -101 1 -110 1 -111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4378 $abc$18544$new_n4376 $abc$18544$new_n4356 system_cpu.BranchPlugin_jumpInterface_payload[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15846 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4374 $abc$18544$new_n4372 $abc$18544$new_n4431 system_cpu.BranchPlugin_jumpInterface_payload[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15848 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n4373 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] $abc$18544$new_n4357 $abc$18544$new_n4431 -001 1 -100 1 -101 1 -111 1 -.names $abc$18544$new_n3256 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] $abc$18544$new_n4373 $abc$18544$new_n4357 system_cpu.BranchPlugin_jumpInterface_payload[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15850 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n3256 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] $abc$18544$new_n4370 $abc$18544$new_n4434 system_cpu.BranchPlugin_jumpInterface_payload[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15852 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n4371 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] $abc$18544$new_n4358 $abc$18544$new_n4434 -001 1 -100 1 -101 1 -111 1 -.names $abc$18544$new_n3256 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] $abc$18544$new_n4371 $abc$18544$new_n4358 system_cpu.BranchPlugin_jumpInterface_payload[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15854 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4359 $abc$18544$new_n4437 system_cpu.BranchPlugin_jumpInterface_payload[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15856 -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[7] system_cpu.decode_to_execute_RS1[7] $abc$18544$new_n4437 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4360 $abc$18544$new_n4439 system_cpu.BranchPlugin_jumpInterface_payload[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15858 -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[6] system_cpu.decode_to_execute_RS1[6] $abc$18544$new_n4439 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4361 $abc$18544$new_n4441 system_cpu.BranchPlugin_jumpInterface_payload[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15860 -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[5] system_cpu.decode_to_execute_RS1[5] $abc$18544$new_n4441 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4443 system_cpu.BranchPlugin_jumpInterface_payload[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15862 -010 1 -011 1 -101 1 -111 1 -.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4369 $abc$18544$new_n4362 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n4443 -00001 1 -00011 1 -00100 1 -00110 1 -01000 1 -01010 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4445 system_cpu.BranchPlugin_jumpInterface_payload[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15864 -010 1 -011 1 -101 1 -111 1 -.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4368 $abc$18544$new_n4363 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n4445 -00001 1 -00011 1 -00100 1 -00110 1 -01000 1 -01010 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4447 system_cpu.BranchPlugin_jumpInterface_payload[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15866 -010 1 -011 1 -101 1 -111 1 -.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4366 $abc$18544$new_n4364 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$new_n4447 -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] system_cpu.decode_to_execute_PC[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15870 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] system_cpu.decode_to_execute_PC[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15872 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] system_cpu.decode_to_execute_PC[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15874 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] system_cpu.decode_to_execute_PC[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15876 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] system_cpu.decode_to_execute_PC[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15878 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] system_cpu.decode_to_execute_PC[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15880 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] system_cpu.decode_to_execute_PC[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15882 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] system_cpu.decode_to_execute_PC[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15884 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] system_cpu.decode_to_execute_PC[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15886 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] system_cpu.decode_to_execute_PC[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15888 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] system_cpu.decode_to_execute_PC[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15890 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] system_cpu.decode_to_execute_PC[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15892 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] system_cpu.decode_to_execute_PC[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15894 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] system_cpu.decode_to_execute_PC[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15896 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] system_cpu.decode_to_execute_PC[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15898 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] system_cpu.decode_to_execute_PC[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15900 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu.decode_to_execute_PC[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15902 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu.decode_to_execute_PC[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15904 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu.decode_to_execute_PC[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15906 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu.decode_to_execute_PC[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15908 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.decode_to_execute_PC[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15910 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] system_cpu.decode_to_execute_PC[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15912 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] system_cpu.decode_to_execute_PC[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15914 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.decode_to_execute_PC[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15916 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.decode_to_execute_PC[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15918 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.decode_to_execute_PC[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15920 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] system_cpu.decode_to_execute_PC[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15922 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu.decode_to_execute_PC[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15924 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu.decode_to_execute_PC[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15926 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3256 system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15970 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[19] system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16192 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4480 apb3Router_1.io_input_PADDR[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16194 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[18] system_mainBusArbiter.io_dBus_cmd_payload_address[18] $abc$18544$new_n4480 -000 1 -001 1 -100 1 -110 1 -.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[17] system_cpu.IBusSimplePlugin_cmd_payload_pc[17] system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16196 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[16] system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_mainBusArbiter.io_dBus_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16198 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4484 apb3Router_1.io_input_PADDR[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16200 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[15] system_mainBusArbiter.io_dBus_cmd_payload_address[15] $abc$18544$new_n4484 -000 1 -001 1 -100 1 -110 1 -.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[14] system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_mainBusArbiter.io_dBus_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16202 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4487 apb3Router_1.io_input_PADDR[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16204 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[13] system_mainBusArbiter.io_dBus_cmd_payload_address[13] $abc$18544$new_n4487 -000 1 -001 1 -100 1 -110 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[12] system_mainBusArbiter.io_dBus_cmd_payload_address[12] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] -010 1 -011 1 -101 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] apb3Router_1.io_input_PADDR[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16206 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[7] system_mainBusArbiter.io_dBus_cmd_payload_address[7] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] -010 1 -011 1 -101 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] apb3Router_1.io_input_PADDR[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16216 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[6] system_mainBusArbiter.io_dBus_cmd_payload_address[6] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] -010 1 -011 1 -101 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] apb3Router_1.io_input_PADDR[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16218 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[5] system_mainBusArbiter.io_dBus_cmd_payload_address[5] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] -010 1 -011 1 -101 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] apb3Router_1.io_input_PADDR[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16220 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[4] system_mainBusArbiter.io_dBus_cmd_payload_address[4] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] -010 1 -011 1 -101 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] apb3Router_1.io_input_PADDR[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16222 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[3] system_mainBusArbiter.io_dBus_cmd_payload_address[3] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] -010 1 -011 1 -101 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] apb3Router_1.io_input_PADDR[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16224 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[2] system_mainBusArbiter.io_dBus_cmd_payload_address[2] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] -010 1 -011 1 -101 1 -111 1 -.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] apb3Router_1.io_input_PADDR[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16226 -010 1 -011 1 -101 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[10] system_cpu._zz_RegFilePlugin_regFile_port0[10] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16302 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[9] system_cpu._zz_RegFilePlugin_regFile_port0[9] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16306 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[8] system_cpu._zz_RegFilePlugin_regFile_port0[8] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16310 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu._zz_RegFilePlugin_regFile_port0[7] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16314 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[6] system_cpu._zz_RegFilePlugin_regFile_port0[6] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16318 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[5] system_cpu._zz_RegFilePlugin_regFile_port0[5] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16322 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_size[0] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16386 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4511 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16388 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.switch_Misc_l241_1 $abc$18544$new_n4510 -00 1 -.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[30] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[14] $abc$18544$new_n4511 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4513 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16390 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[29] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[13] $abc$18544$new_n4513 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4515 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16392 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[28] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[12] $abc$18544$new_n4515 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4517 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16394 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[27] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[11] $abc$18544$new_n4517 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4519 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16396 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[26] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[10] $abc$18544$new_n4519 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4521 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16398 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[25] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[9] $abc$18544$new_n4521 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4523 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16400 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[24] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[8] $abc$18544$new_n4523 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] system_cpu.decode_to_execute_RS2[23] system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16402 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] system_cpu.decode_to_execute_RS2[22] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16404 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] system_cpu.decode_to_execute_RS2[21] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16406 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] system_cpu.decode_to_execute_RS2[20] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16408 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] system_cpu.decode_to_execute_RS2[19] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16410 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] system_cpu.decode_to_execute_RS2[18] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16412 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] system_cpu.decode_to_execute_RS2[17] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16414 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] system_cpu.decode_to_execute_RS2[16] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16416 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] system_cpu._zz_dBus_cmd_payload_data[7] system_cpu.decode_to_execute_RS2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16418 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] system_cpu._zz_dBus_cmd_payload_data[6] system_cpu.decode_to_execute_RS2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16420 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] system_cpu._zz_dBus_cmd_payload_data[5] system_cpu.decode_to_execute_RS2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16422 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] system_cpu._zz_dBus_cmd_payload_data[4] system_cpu.decode_to_execute_RS2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16424 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] system_cpu._zz_dBus_cmd_payload_data[3] system_cpu.decode_to_execute_RS2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16426 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] system_cpu._zz_dBus_cmd_payload_data[2] system_cpu.decode_to_execute_RS2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16428 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] system_cpu._zz_dBus_cmd_payload_data[1] system_cpu.decode_to_execute_RS2[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16430 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] system_cpu._zz_dBus_cmd_payload_data[0] system_cpu.decode_to_execute_RS2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16432 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16434 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16436 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16438 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16440 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16442 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16444 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16446 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16448 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3408 system_mainBusArbiter.io_dBus_cmd_payload_address[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16450 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3476 system_mainBusArbiter.io_dBus_cmd_payload_address[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16452 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[28] $abc$18544$new_n3485 system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16454 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3490 system_mainBusArbiter.io_dBus_cmd_payload_address[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16456 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3497 system_mainBusArbiter.io_dBus_cmd_payload_address[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16458 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3503 system_mainBusArbiter.io_dBus_cmd_payload_address[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16460 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[24] $abc$18544$new_n3511 system_cpu._zz_execute_SrcPlugin_addSub_2[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16462 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3515 system_mainBusArbiter.io_dBus_cmd_payload_address[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16464 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[22] $abc$18544$new_n3523 system_cpu._zz_execute_SrcPlugin_addSub_2[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16466 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3527 system_mainBusArbiter.io_dBus_cmd_payload_address[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16468 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3534 system_mainBusArbiter.io_dBus_cmd_payload_address[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16470 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3540 system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16472 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3547 system_mainBusArbiter.io_dBus_cmd_payload_address[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16474 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3553 system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16476 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3560 system_mainBusArbiter.io_dBus_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16478 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3568 system_mainBusArbiter.io_dBus_cmd_payload_address[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16480 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3574 system_mainBusArbiter.io_dBus_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16482 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3582 system_mainBusArbiter.io_dBus_cmd_payload_address[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16484 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[12] $abc$18544$new_n3589 system_cpu._zz_execute_SrcPlugin_addSub_2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16486 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3596 system_mainBusArbiter.io_dBus_cmd_payload_address[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16488 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[10] $abc$18544$new_n3606 system_cpu._zz_execute_SrcPlugin_addSub_2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16490 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3612 system_mainBusArbiter.io_dBus_cmd_payload_address[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16492 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[8] $abc$18544$new_n3619 system_cpu._zz_execute_SrcPlugin_addSub_2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16494 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3625 system_mainBusArbiter.io_dBus_cmd_payload_address[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16496 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3637 system_mainBusArbiter.io_dBus_cmd_payload_address[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16498 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3642 system_mainBusArbiter.io_dBus_cmd_payload_address[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16500 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3649 system_mainBusArbiter.io_dBus_cmd_payload_address[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16502 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3654 system_mainBusArbiter.io_dBus_cmd_payload_address[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16504 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3664 system_mainBusArbiter.io_dBus_cmd_payload_address[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16506 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3670 system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16508 -010 1 -011 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16510 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_cpu.switch_Misc_l241_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16524 -001 1 -011 1 -110 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4581 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] $abc$18544$new_n4510 system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16526 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[31] system_cpu.decode_to_execute_RS2[15] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n4581 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3678 system_mainBusArbiter.io_dBus_cmd_payload_address[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16528 -000 1 -001 1 -101 1 -111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_wr system_cpu.dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16530 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_834 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$new_n4585 $abc$18544$auto$rtlil.cc:2693:MuxGate$16628 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4586 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4585 -11000 1 -.names $abc$18544$new_n4587 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4586 -1000 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] system_cpu._zz_decode_SRC2 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$18544$new_n4587 -1100 1 -.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_772 $abc$18544$new_n4590 $abc$18544$new_n4589 $abc$18544$auto$rtlil.cc:2693:MuxGate$16630 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n4587 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4589 -11000 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4590 -0000 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4592 system_cpu.execute_CsrPlugin_csr_836 $abc$18544$auto$rtlil.cc:2693:MuxGate$16632 -001 1 -011 1 -110 1 -111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4589 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4592 -11000 1 -.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_768 $abc$18544$new_n4586 $abc$18544$new_n4590 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16634 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$18544$new_n3256 system_cpu.execute_to_memory_BRANCH_DO system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] $abc$18544$new_n4595 $abc$18544$auto$rtlil.cc:2693:MuxGate$16638 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.switch_Misc_l241_1 $abc$18544$new_n4596 $abc$18544$new_n4597 $abc$18544$new_n4595 -00000 1 -00010 1 -00100 1 -00101 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10100 1 -10101 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n3685 $abc$18544$new_n3678 $abc$18544$new_n3681 $abc$18544$new_n4596 -100 1 -101 1 -110 1 -.names $abc$18544$new_n4613 $abc$18544$new_n4611 $abc$18544$new_n4604 $abc$18544$new_n4598 $abc$18544$new_n4597 -1111 1 -.names $abc$18544$new_n4601 $abc$18544$new_n4599 $abc$18544$new_n4603 system_cpu.decode_to_execute_SRC2[17] system_cpu._zz_execute_SrcPlugin_addSub_2[17] $abc$18544$new_n4598 -11100 1 -11111 1 -.names $abc$18544$new_n4600 system_cpu.decode_to_execute_SRC2[23] system_cpu._zz_execute_SrcPlugin_addSub_2[23] system_cpu.decode_to_execute_SRC2[24] system_cpu._zz_execute_SrcPlugin_addSub_2[24] $abc$18544$new_n4599 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.decode_to_execute_SRC2[16] system_cpu._zz_execute_SrcPlugin_addSub_2[16] system_cpu.decode_to_execute_SRC2[28] system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$new_n4600 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n4602 $abc$18544$new_n3681 system_cpu.decode_to_execute_SRC2[0] system_cpu._zz_execute_SrcPlugin_addSub_2[0] $abc$18544$new_n4601 -1100 1 -1111 1 -.names system_cpu.decode_to_execute_SRC2[2] system_cpu._zz_execute_SrcPlugin_addSub_2[2] system_cpu.decode_to_execute_SRC2[30] system_cpu._zz_execute_SrcPlugin_addSub_2[30] $abc$18544$new_n4602 -0000 1 -0011 1 -1100 1 -1111 1 -.names system_cpu._zz_execute_SrcPlugin_addSub_2[9] system_cpu.decode_to_execute_SRC2[9] system_cpu.decode_to_execute_SRC2[13] system_cpu._zz_execute_SrcPlugin_addSub_2[13] $abc$18544$new_n4603 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n4607 $abc$18544$new_n4605 $abc$18544$new_n4609 system_cpu.decode_to_execute_SRC2[20] system_cpu._zz_execute_SrcPlugin_addSub_2[20] $abc$18544$new_n4604 -11100 1 -11111 1 -.names $abc$18544$new_n4606 system_cpu._zz_execute_SrcPlugin_addSub_2[5] system_cpu.decode_to_execute_SRC2[5] system_cpu._zz_execute_SrcPlugin_addSub_2[6] system_cpu.decode_to_execute_SRC2[6] $abc$18544$new_n4605 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.decode_to_execute_SRC2[18] system_cpu._zz_execute_SrcPlugin_addSub_2[18] system_cpu.decode_to_execute_SRC2[26] system_cpu._zz_execute_SrcPlugin_addSub_2[26] $abc$18544$new_n4606 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n4608 system_cpu._zz_execute_SrcPlugin_addSub_2[4] system_cpu.decode_to_execute_SRC2[4] system_cpu.decode_to_execute_SRC2[1] system_cpu._zz_execute_SrcPlugin_addSub_2[1] $abc$18544$new_n4607 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.decode_to_execute_SRC2[3] system_cpu._zz_execute_SrcPlugin_addSub_2[3] system_cpu.decode_to_execute_SRC2[19] system_cpu._zz_execute_SrcPlugin_addSub_2[19] $abc$18544$new_n4608 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n4610 system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu.decode_to_execute_SRC2[7] system_cpu.decode_to_execute_SRC2[22] system_cpu._zz_execute_SrcPlugin_addSub_2[22] $abc$18544$new_n4609 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.decode_to_execute_SRC2[8] system_cpu._zz_execute_SrcPlugin_addSub_2[8] system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu.decode_to_execute_SRC2[11] $abc$18544$new_n4610 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n4612 system_cpu.decode_to_execute_SRC2[21] system_cpu._zz_execute_SrcPlugin_addSub_2[21] system_cpu.decode_to_execute_SRC2[27] system_cpu._zz_execute_SrcPlugin_addSub_2[27] $abc$18544$new_n4611 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.decode_to_execute_SRC2[12] system_cpu._zz_execute_SrcPlugin_addSub_2[12] system_cpu.decode_to_execute_SRC2[15] system_cpu._zz_execute_SrcPlugin_addSub_2[15] $abc$18544$new_n4612 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n4614 system_cpu._zz_execute_SrcPlugin_addSub_2[10] system_cpu.decode_to_execute_SRC2[10] system_cpu.decode_to_execute_SRC2[14] system_cpu._zz_execute_SrcPlugin_addSub_2[14] $abc$18544$new_n4613 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.decode_to_execute_SRC2[25] system_cpu._zz_execute_SrcPlugin_addSub_2[25] system_cpu.decode_to_execute_SRC2[29] system_cpu._zz_execute_SrcPlugin_addSub_2[29] $abc$18544$new_n4614 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n3256 system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$18544$new_n3670 $abc$18544$auto$rtlil.cc:2693:MuxGate$16642 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4617 system_cpu.decode_to_execute_DO_EBREAK $abc$18544$auto$rtlil.cc:2693:MuxGate$16644 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n4618 system_cpu.DebugPlugin_debugUsed system_cpu.DebugPlugin_haltIt system_cpu.DebugPlugin_disableEbreak system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$18544$new_n4617 -11000 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4619 $abc$18544$new_n4618 -111 1 -.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$18544$new_n4619 -00 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4621 system_cpu.decode_to_execute_SRC2[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16646 -001 1 -011 1 -100 1 -101 1 -.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[31] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu._zz_decode_SRC2 $abc$18544$new_n4621 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$18544$new_n4623 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n3309 $abc$18544$auto$rtlil.cc:2693:MuxGate$16648 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$18544$new_n4624 $abc$18544$new_n4310 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4623 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4625 $abc$18544$new_n4624 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4625 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[31] system_cpu.decode_to_execute_RS2[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16650 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[31] system_cpu.decode_to_execute_RS1[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16652 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4629 system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16654 -001 1 -011 1 -100 1 -101 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4629 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_SHIFT_CTRL[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4310 $abc$18544$auto$rtlil.cc:2693:MuxGate$16656 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu._zz_execute_ALU_BITWISE_CTRL[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16658 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4633 system_cpu.decode_to_execute_SRC_LESS_UNSIGNED system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16660 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4633 -10 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_ALU_CTRL[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4635 $abc$18544$auto$rtlil.cc:2693:MuxGate$16662 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$new_n4635 -000 1 -010 1 -011 1 -.names $abc$18544$new_n3256 system_cpu._zz_memory_ENV_CTRL system_cpu._zz_execute_ENV_CTRL $abc$18544$auto$rtlil.cc:2693:MuxGate$16664 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_ENV_CTRL $abc$18544$new_n4618 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16666 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$18544$new_n3309 system_cpu.decode_to_execute_IS_CSR system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4619 $abc$18544$auto$rtlil.cc:2693:MuxGate$16668 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names system_cpu.dBus_cmd_payload_wr $abc$18544$new_n3256 $abc$18544$auto$rtlil.cc:2693:MuxGate$16670 -10 1 -.names $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16672 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3256 system_cpu.execute_to_memory_REGFILE_WRITE_VALID system_cpu.decode_to_execute_REGFILE_WRITE_VALID $abc$18544$auto$rtlil.cc:2693:MuxGate$16674 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4643 system_cpu.decode_to_execute_REGFILE_WRITE_VALID $abc$18544$new_n4644 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16678 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n3306 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4619 $abc$18544$new_n4643 -00100 1 -00101 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$18544$new_n4644 -0000 1 -.names system_cpu.decode_to_execute_MEMORY_ENABLE $abc$18544$new_n3256 $abc$18544$auto$rtlil.cc:2693:MuxGate$16680 -01 1 -10 1 -11 1 -.names $abc$18544$new_n3309 system_cpu.decode_to_execute_MEMORY_ENABLE system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16682 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -11000 1 -.names $abc$18544$new_n4624 $abc$18544$new_n3309 system_cpu.decode_to_execute_SRC_USE_SUB_LESS $abc$18544$auto$rtlil.cc:2693:MuxGate$16684 -001 1 -010 1 -011 1 -.names $abc$18544$new_n3309 system_cpu.decode_to_execute_CSR_WRITE_OPCODE $abc$18544$new_n4649 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16686 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$18544$new_n4649 -1000 1 -.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC2 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$auto$rtlil.cc:2693:MuxGate$16690 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[31] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16714 -001 1 -011 1 -110 1 -111 1 -.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[1] system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16718 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names io_apb_decoder.io_input_PSEL $abc$18544$new_n3934 apb3Router_1.io_input_PWRITE $abc$18544$auto$rtlil.cc:2693:MuxGate$16722 -010 1 -011 1 -101 1 -111 1 -.names $abc$18544$new_n3256 $abc$18544$new_n4656 $abc$18544$new_n4655 system_cpu.BranchPlugin_jumpInterface_payload[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16756 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4401 $abc$18544$new_n4400 $abc$18544$new_n4349 $abc$18544$new_n4655 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1111 1 -.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[31] system_cpu.decode_to_execute_RS1[31] $abc$18544$new_n4656 -0000 1 -0001 1 -0100 1 -0110 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16764 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu.decode_to_execute_PC[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16766 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu._zz_RegFilePlugin_regFile_port0[11] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16788 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4661 system_cpu._zz_execute_SrcPlugin_addSub_2[4] $abc$18544$new_n4131 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16792 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port0[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4661 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -10010 1 -10011 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3309 $abc$18544$new_n4663 system_cpu._zz_execute_SrcPlugin_addSub_2[31] $abc$18544$new_n4131 system_cpu._zz_RegFilePlugin_regFile_port0[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16794 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_cpu._zz_decode_SRC2 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4663 -1110 1 -.names system_timer.interruptCtrl_1.pendings[0] system_timer.interruptCtrl_1.io_masks[0] system_timer.interruptCtrl_1.pendings[1] system_timer.interruptCtrl_1.io_masks[1] system_cpu.timerInterrupt -0011 1 -0111 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_idcodeArea_ctrl_capture -1100 1 -.names apb3Router_1.selIndex[0] apb3Router_1.selIndex[1] $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP -10 1 -.names apb3Router_1.selIndex[1] apb3Router_1.selIndex[0] $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 -01 1 -10 1 -11 1 -.names system_cpu.decode_to_execute_CSR_WRITE_OPCODE system_cpu.decode_to_execute_IS_CSR system_cpu.execute_CsrPlugin_csr_836 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$auto$opt_dff.cc:253:combine_resets$3598 -11111 1 -.names $abc$18544$new_n4670 $abc$18544$new_n3711 system_mainBusDecoder_logic_noHit -00 1 -.names $abc$18544$new_n4675 $abc$18544$new_n3716 $abc$18544$new_n4672 $abc$18544$new_n4671 $abc$18544$new_n3712 $abc$18544$new_n4670 -11110 1 -.names $abc$18544$new_n3718 $abc$18544$new_n3717 $abc$18544$new_n4671 -11 1 -.names $abc$18544$new_n4674 $abc$18544$new_n4673 $abc$18544$new_n4487 $abc$18544$new_n4484 $abc$18544$new_n4480 $abc$18544$new_n4672 -11111 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_cpu.IBusSimplePlugin_cmd_payload_pc[17] system_mainBusArbiter.io_dBus_cmd_payload_address[14] system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$new_n4673 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_mainBusArbiter.io_dBus_cmd_payload_address[16] system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$new_n4674 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[30] system_mainBusArbiter.io_dBus_cmd_payload_address[28] system_mainBusArbiter.io_dBus_cmd_payload_address[30] $abc$18544$new_n4675 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.when_JtagTap_l120 -0000 1 -.names $abc$18544$new_n4678 system_uartCtrl.uartCtrl_1.clockDivider_counter[19] system_uartCtrl.uartCtrl_1.clockDivider_tick -10 1 -.names $abc$18544$new_n4679 system_uartCtrl.uartCtrl_1.clockDivider_counter[18] $abc$18544$new_n4678 -10 1 -.names $abc$18544$new_n4680 system_uartCtrl.uartCtrl_1.clockDivider_counter[17] $abc$18544$new_n4679 -10 1 -.names $abc$18544$new_n4681 system_uartCtrl.uartCtrl_1.clockDivider_counter[16] $abc$18544$new_n4680 -10 1 -.names $abc$18544$new_n4685 $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[13] system_uartCtrl.uartCtrl_1.clockDivider_counter[15] $abc$18544$new_n4681 -1100 1 -.names $abc$18544$new_n4683 system_uartCtrl.uartCtrl_1.clockDivider_counter[9] $abc$18544$new_n4682 -10 1 -.names $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[8] system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] system_uartCtrl.uartCtrl_1.clockDivider_counter[7] $abc$18544$new_n4683 -10000 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[4] system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] system_uartCtrl.uartCtrl_1.clockDivider_counter[3] $abc$18544$new_n4684 -00000 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_counter[14] $abc$18544$new_n4685 -0000 1 -.names system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\sampler_value[0:0] -011 1 -101 1 -110 1 -111 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid system_uartCtrl.bridge_interruptCtrl_writeIntEnable system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid system_uartCtrl.bridge_interruptCtrl_readIntEnable system_uartCtrl.uartCtrl_1.io_readBreak system_cpu.externalInterrupt -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$18544$new_n5026 $abc$18544$new_n2756 system_timer.prescaler_1.when_Prescaler_l17 -01 1 -10 1 -11 1 -.names $abc$18544$new_n3834 systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3837 $abc$18544$new_n4035 toplevel_system_cpu_debug_bus_cmd_fire -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$18544$new_n3317 $abc$18544$new_n4009 $abc$18544$new_n3314 system_cpu.execute_arbitration_isValid $abc$18544$flatten\system_cpu.$0\DebugPlugin_isPipBusy[0:0] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$18544$new_n4670 $abc$18544$new_n3933 system_ram.io_bus_cmd_fire -11 1 -.names system_ram.io_bus_cmd_fire $abc$18544$new_n3934 $abc$18544$flatten\system_ram.$0\_zz_io_bus_rsp_valid[0:0] -10 1 -.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire $abc$18544$new_n4694 system_mainBusArbiter.io_dBus_cmd_payload_address[1] system_mainBusArbiter.io_dBus_cmd_payload_size[1] $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] -11001 1 -11010 1 -11011 1 -.names system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_size[0] $abc$18544$new_n4694 -000 1 -.names $abc$18544$new_n4696 system_ram.io_bus_cmd_fire $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] -11 1 -.names $abc$18544$new_n3934 system_mainBusArbiter.io_dBus_cmd_payload_address[1] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_mainBusArbiter.io_dBus_cmd_payload_size[0] $abc$18544$new_n4696 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$new_n4694 $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] -1100 1 -.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] -1100 1 -.names system_uartCtrl.bridge_misc_doBreak $abc$18544$new_n3928 $abc$18544$new_n4700 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\_zz_io_txd[0:0] -000 1 -.names system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$new_n4701 system_uartCtrl.uartCtrl_1.tx.stateMachine_parity $abc$18544$new_n4700 -10010 1 -10011 1 -11000 1 -11010 1 -.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] $abc$18544$new_n4702 $abc$18544$new_n4704 $abc$18544$new_n4701 -001 1 -011 1 -110 1 -111 1 -.names $abc$18544$new_n4703 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[7] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[6] $abc$18544$new_n4702 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[5] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[4] $abc$18544$new_n4703 -0000 1 -0010 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4705 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[0] $abc$18544$new_n4704 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[2] $abc$18544$new_n4705 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names system_uartCtrl.uartCtrl_1.rx.stateMachine_parity system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$new_n2991 $abc$18544$new_n3010 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\stateMachine_parity[0:0] -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[0] -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[1] -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2997 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[2] -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -.names system_uartCtrl.bridge_misc_breakDetected system_uartCtrl.when_BusSlaveFactory_l347_2 $abc$18544$new_n3957 system_uartCtrl.uartCtrl_1.io_readBreak system_uartCtrl.system_uartCtrl_uartCtrl_1_io_readBreak_regNext $abc$18544$flatten\system_uartCtrl.$0\bridge_misc_breakDetected[0:0] -00010 1 -00110 1 -01010 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n3957 system_uartCtrl.when_BusSlaveFactory_l347_3 system_uartCtrl.bridge_misc_doBreak system_uartCtrl.when_BusSlaveFactory_l379 $abc$18544$flatten\system_uartCtrl.$0\bridge_misc_doBreak[0:0] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n4713 $abc$18544$new_n4723 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$new_n3963 apb3Router_1._zz_io_input_PRDATA[0] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$18544$new_n4714 $abc$18544$new_n4722 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[0] $abc$18544$new_n4713 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names apb3Router_1.selIndex[1] $abc$18544$new_n4715 $abc$18544$new_n4718 system_timer._zz_io_limit[0] $abc$18544$new_n2757 $abc$18544$new_n4714 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$18544$new_n4716 $abc$18544$new_n2717 system_timer.timerABridge_ticksEnable[0] $abc$18544$new_n4715 -100 1 -101 1 -110 1 -.names system_timer.system_timer_timerA_io_limit_driver[0] $abc$18544$new_n2740 system_timer.timerA.counter[0] $abc$18544$new_n4717 $abc$18544$new_n4716 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3893 $abc$18544$new_n3975 $abc$18544$new_n4717 -11 1 -.names $abc$18544$new_n4720 $abc$18544$new_n4719 $abc$18544$new_n3969 system_timer.timerB.counter[0] $abc$18544$new_n4718 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names $abc$18544$new_n2722 $abc$18544$new_n3969 system_timer.system_timer_timerB_io_limit_driver[0] system_timer.timerBBridge_ticksEnable[0] $abc$18544$new_n2713 $abc$18544$new_n4719 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_timer.interruptCtrl_1.io_masks[0] $abc$18544$new_n2822 system_timer.interruptCtrl_1.pendings[0] $abc$18544$new_n4721 $abc$18544$new_n4720 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n4721 -11000 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[0] $abc$18544$new_n2723 io_gpioA_write[0] $abc$18544$new_n4722 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] system_uartCtrl.bridge_misc_readError system_uartCtrl.bridge_read_streamBreaked_payload[0] $abc$18544$new_n4723 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4725 $abc$18544$new_n4734 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[1] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[1] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$18544$new_n4726 $abc$18544$new_n4733 $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3958 system_uartCtrl.bridge_misc_readOverflowError $abc$18544$new_n4725 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names apb3Router_1.selIndex[1] $abc$18544$new_n4727 $abc$18544$new_n4732 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$new_n2822 $abc$18544$new_n4726 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n4730 $abc$18544$new_n4728 $abc$18544$new_n2757 system_timer._zz_io_limit[1] $abc$18544$new_n4727 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n4729 $abc$18544$new_n2722 $abc$18544$new_n2713 $abc$18544$new_n3969 $abc$18544$new_n4728 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[1] system_timer.system_timer_timerB_io_limit_driver[1] system_timer.timerBBridge_ticksEnable[1] $abc$18544$new_n4729 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n2717 system_timer.timerABridge_ticksEnable[1] system_timer.interruptCtrl_1.pendings[1] $abc$18544$new_n4721 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$new_n4730 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$18544$new_n4717 system_timer.timerA.counter[1] $abc$18544$new_n2740 system_timer.system_timer_timerA_io_limit_driver[1] $abc$18544$new_n4732 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_uartCtrl.bridge_read_streamBreaked_payload[1] $abc$18544$new_n3042 $abc$18544$new_n3963 system_uartCtrl.bridge_interruptCtrl_readIntEnable $abc$18544$new_n4733 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[1] $abc$18544$new_n2723 io_gpioA_write[1] $abc$18544$new_n4734 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4736 system_uartCtrl.bridge_read_streamBreaked_payload[2] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[2] -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$18544$new_n4740 $abc$18544$new_n4739 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4738 $abc$18544$new_n4736 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$18544$new_n4717 $abc$18544$new_n3969 $abc$18544$new_n2722 $abc$18544$new_n4737 -000 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[2] system_timer.system_timer_timerB_io_limit_driver[2] system_timer.timerA.counter[2] $abc$18544$new_n4738 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names system_timer.system_timer_timerA_io_limit_driver[2] $abc$18544$new_n2740 system_timer._zz_io_limit[2] $abc$18544$new_n2757 $abc$18544$new_n4739 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4741 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[2] $abc$18544$new_n2714 $abc$18544$new_n4740 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[2] $abc$18544$new_n2723 io_gpioA_write[2] $abc$18544$new_n4741 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3042 $abc$18544$new_n4742 -11 1 -.names $abc$18544$new_n4744 system_uartCtrl.bridge_read_streamBreaked_payload[3] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[3] -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n4747 $abc$18544$new_n4746 $abc$18544$new_n4737 $abc$18544$new_n4745 $abc$18544$new_n4744 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[3] system_timer.system_timer_timerB_io_limit_driver[3] system_timer.timerA.counter[3] $abc$18544$new_n4745 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 system_timer.system_timer_timerA_io_limit_driver[3] $abc$18544$new_n2740 $abc$18544$new_n2757 system_timer._zz_io_limit[3] $abc$18544$new_n4746 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names $abc$18544$new_n4748 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[3] $abc$18544$new_n4747 -0000 1 -0001 1 -0010 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[3] $abc$18544$new_n2723 io_gpioA_write[3] $abc$18544$new_n4748 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4750 system_uartCtrl.bridge_read_streamBreaked_payload[4] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[4] -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$18544$new_n4753 $abc$18544$new_n4752 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4751 $abc$18544$new_n4750 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[4] system_timer.system_timer_timerB_io_limit_driver[4] system_timer.timerA.counter[4] $abc$18544$new_n4751 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names system_timer.system_timer_timerA_io_limit_driver[4] $abc$18544$new_n2740 system_timer._zz_io_limit[4] $abc$18544$new_n2757 $abc$18544$new_n4752 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4754 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[4] $abc$18544$new_n2714 $abc$18544$new_n4753 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[4] $abc$18544$new_n2723 io_gpioA_write[4] $abc$18544$new_n4754 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4756 system_uartCtrl.bridge_read_streamBreaked_payload[5] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[5] -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$18544$new_n4759 $abc$18544$new_n4758 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4757 $abc$18544$new_n4756 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[5] system_timer.system_timer_timerB_io_limit_driver[5] system_timer.timerA.counter[5] $abc$18544$new_n4757 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names system_timer.system_timer_timerA_io_limit_driver[5] $abc$18544$new_n2740 system_timer._zz_io_limit[5] $abc$18544$new_n2757 $abc$18544$new_n4758 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4760 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[5] $abc$18544$new_n2714 $abc$18544$new_n4759 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[5] $abc$18544$new_n2723 io_gpioA_write[5] $abc$18544$new_n4760 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4762 system_uartCtrl.bridge_read_streamBreaked_payload[6] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[6] -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$18544$new_n4765 $abc$18544$new_n4764 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4763 $abc$18544$new_n4762 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[6] system_timer.system_timer_timerB_io_limit_driver[6] system_timer.timerA.counter[6] $abc$18544$new_n4763 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names system_timer.system_timer_timerA_io_limit_driver[6] $abc$18544$new_n2740 system_timer._zz_io_limit[6] $abc$18544$new_n2757 $abc$18544$new_n4764 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4766 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[6] $abc$18544$new_n2714 $abc$18544$new_n4765 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[6] $abc$18544$new_n2723 io_gpioA_write[6] $abc$18544$new_n4766 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4768 system_uartCtrl.bridge_read_streamBreaked_payload[7] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[7] -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$18544$new_n4771 $abc$18544$new_n4770 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4769 $abc$18544$new_n4768 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[7] system_timer.system_timer_timerB_io_limit_driver[7] system_timer.timerA.counter[7] $abc$18544$new_n4769 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names system_timer.system_timer_timerA_io_limit_driver[7] $abc$18544$new_n2740 system_timer._zz_io_limit[7] $abc$18544$new_n2757 $abc$18544$new_n4770 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4772 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[7] $abc$18544$new_n2714 $abc$18544$new_n4771 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[7] $abc$18544$new_n2723 io_gpioA_write[7] $abc$18544$new_n4772 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names apb3Router_1.selIndex[1] apb3Router_1.selIndex[0] $abc$18544$new_n4774 $abc$18544$new_n4777 $abc$18544$new_n4779 apb3Router_1._zz_io_input_PRDATA[8] -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$18544$new_n4776 $abc$18544$new_n4737 $abc$18544$new_n4775 $abc$18544$new_n4774 -101 1 -110 1 -111 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[8] system_timer.system_timer_timerB_io_limit_driver[8] system_timer.timerA.counter[8] $abc$18544$new_n4775 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names system_timer.system_timer_timerA_io_limit_driver[8] $abc$18544$new_n2740 system_timer._zz_io_limit[8] $abc$18544$new_n2757 $abc$18544$new_n4776 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n4778 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[8] $abc$18544$new_n4777 -000 1 -001 1 -010 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[8] $abc$18544$new_n2723 io_gpioA_write[8] $abc$18544$new_n4778 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3958 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$new_n3963 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid $abc$18544$new_n4779 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names apb3Router_1.selIndex[1] $abc$18544$new_n4781 $abc$18544$new_n4787 $abc$18544$new_n4737 $abc$18544$new_n4786 apb3Router_1._zz_io_input_PRDATA[9] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -.names $abc$18544$new_n4782 $abc$18544$new_n4784 $abc$18544$new_n3958 $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP system_uartCtrl.bridge_misc_breakDetected $abc$18544$new_n4781 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -.names system_uartCtrl.bridge_interruptCtrl_readIntEnable system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n4783 system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n4782 -1110 1 -.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3963 $abc$18544$new_n4783 -11 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4785 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[9] $abc$18544$new_n2714 $abc$18544$new_n4784 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[9] $abc$18544$new_n2723 io_gpioA_write[9] $abc$18544$new_n4785 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[9] system_timer.system_timer_timerB_io_limit_driver[9] system_timer.timerA.counter[9] $abc$18544$new_n4786 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names system_timer.system_timer_timerA_io_limit_driver[9] $abc$18544$new_n2740 system_timer._zz_io_limit[9] $abc$18544$new_n2757 $abc$18544$new_n4787 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$new_n4789 $abc$18544$new_n4792 $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid apb3Router_1._zz_io_input_PRDATA[15] -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names apb3Router_1.selIndex[1] $abc$18544$new_n4791 $abc$18544$new_n4737 $abc$18544$new_n4790 $abc$18544$new_n4789 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[15] system_timer.system_timer_timerB_io_limit_driver[15] system_timer.timerA.counter[15] $abc$18544$new_n4790 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names system_timer.system_timer_timerA_io_limit_driver[15] $abc$18544$new_n2740 system_timer._zz_io_limit[15] $abc$18544$new_n2757 $abc$18544$new_n4791 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4793 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[15] $abc$18544$new_n2714 $abc$18544$new_n4792 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[15] $abc$18544$new_n2723 io_gpioA_write[15] $abc$18544$new_n4793 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4795 $abc$18544$new_n4798 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[16] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[16] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$18544$new_n4797 $abc$18544$new_n4796 $abc$18544$new_n4742 system_uartCtrl.uartCtrl_1.io_readBreak system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n4795 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -.names $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4796 -101 1 -110 1 -.names apb3Router_1.selIndex[1] system_timer.timerBBridge_clearsEnable $abc$18544$new_n2713 system_timer.timerABridge_clearsEnable $abc$18544$new_n2717 $abc$18544$new_n4797 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[16] $abc$18544$new_n2723 io_gpioA_write[16] $abc$18544$new_n4798 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4800 $abc$18544$new_n4801 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[17] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[17] -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4800 -10010 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11110 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[17] $abc$18544$new_n2723 io_gpioA_write[17] $abc$18544$new_n4801 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4805 $abc$18544$new_n4783 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4803 apb3Router_1._zz_io_input_PRDATA[18] -0000 1 -0100 1 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4804 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[18] $abc$18544$new_n4803 -000 1 -001 1 -010 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[18] $abc$18544$new_n2723 io_gpioA_write[18] $abc$18544$new_n4804 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$new_n3038 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n4805 -00000 1 -00001 1 -00011 1 -00110 1 -01010 1 -01100 1 -01101 1 -01111 1 -10010 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11110 1 -.names $abc$18544$new_n4783 $abc$18544$new_n4810 $abc$18544$new_n4809 $abc$18544$new_n4807 apb3Router_1._zz_io_input_PRDATA[19] -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4808 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[19] $abc$18544$new_n2714 $abc$18544$new_n4807 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[19] $abc$18544$new_n2723 io_gpioA_write[19] $abc$18544$new_n4808 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3038 $abc$18544$new_n4809 -00000 1 -00010 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11110 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n4810 -0000 1 -0001 1 -0011 1 -0110 1 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$18544$new_n4783 $abc$18544$new_n4812 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4814 apb3Router_1._zz_io_input_PRDATA[20] -0000 1 -0100 1 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$new_n4813 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n4812 -00000 1 -00001 1 -00011 1 -00110 1 -01010 1 -01100 1 -01101 1 -01111 1 -10010 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11110 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n4809 $abc$18544$new_n4813 -00001 1 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11111 1 -.names $abc$18544$new_n4815 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[20] $abc$18544$new_n4814 -000 1 -001 1 -010 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[20] $abc$18544$new_n2723 io_gpioA_write[20] $abc$18544$new_n4815 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4817 apb3Router_1._zz_io_input_PRDATA[24] -0001 1 -0011 1 -0101 1 -0111 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4818 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[24] $abc$18544$new_n2714 $abc$18544$new_n4817 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[24] $abc$18544$new_n2723 io_gpioA_write[24] $abc$18544$new_n4818 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4820 $abc$18544$new_n4821 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[25] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[25] -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] $abc$18544$new_n4820 -10010 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11110 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[25] $abc$18544$new_n2723 io_gpioA_write[25] $abc$18544$new_n4821 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$new_n4825 $abc$18544$new_n4823 apb3Router_1._zz_io_input_PRDATA[26] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4824 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[26] $abc$18544$new_n2714 $abc$18544$new_n4823 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$18544$new_n3893 io_gpioA_writeEnable[26] $abc$18544$new_n2723 io_gpioA_write[26] $abc$18544$new_n4824 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$18544$new_n3073 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n4825 -000 1 -010 1 -011 1 -.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n4827 $abc$18544$new_n4828 apb3Router_1._zz_io_input_PRDATA[27] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 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-10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[4] system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] system_uartCtrl.uartCtrl_1.clockDivider_counter[3] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][4] -00000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][5] -010 1 -100 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][6] -0010 1 -1000 1 -1001 1 -1011 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[7] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][7] -00100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names $abc$18544$new_n4981 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][8] -00 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[8] $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] system_uartCtrl.uartCtrl_1.clockDivider_counter[7] $abc$18544$new_n4981 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[9] $abc$18544$new_n4683 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][9] -010 1 -100 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[10] $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][10] -010 1 -100 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[10] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][11] -0010 1 -1000 1 -1001 1 -1011 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][12] -00100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names $abc$18544$new_n4987 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][13] -00 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[13] $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] $abc$18544$new_n4987 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[14] $abc$18544$new_n4989 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][14] -010 1 -100 1 -.names $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_counter[13] $abc$18544$new_n4989 -10000 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[15] $abc$18544$new_n4989 system_uartCtrl.uartCtrl_1.clockDivider_counter[14] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][15] -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[16] $abc$18544$new_n4681 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][16] -010 1 -100 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[17] $abc$18544$new_n4680 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][17] -010 1 -100 1 -.names $abc$18544$new_n4679 system_uartCtrl.uartCtrl_1.clockDivider_counter[18] system_uartCtrl.uartCtrl_1.clockDivider_counter[19] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][18] -010 1 -011 1 -101 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[19] $abc$18544$new_n4678 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][19] -10 1 -.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg $abc$18544$new_n3016 system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[0] -010 1 -100 1 -.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[1] -011 1 -100 1 -101 1 -110 1 -.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[2] -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names system_uartCtrl.uartCtrl_1.tx.stateMachine_parity $abc$18544$new_n3016 $abc$18544$new_n4700 $abc$18544$new_n3928 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\stateMachine_parity[0:0] -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names system_uartCtrl.uartCtrl_1.rx.sampler_tick $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][0] -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][1] -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -.names system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][2] -00100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names $abc$18544$new_n3972 system_timer.interruptCtrl_1.pendings[0] $abc$18544$new_n4721 $abc$18544$new_n2709 system_uartCtrl.when_BusSlaveFactory_l347 $abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][0] -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$18544$new_n3967 system_timer.interruptCtrl_1.pendings[1] $abc$18544$new_n4721 $abc$18544$new_n2709 system_uartCtrl.when_BusSlaveFactory_l347_1 $abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][1] -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[1] -01 1 -10 1 -.names system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[2] -011 1 -100 1 -101 1 -110 1 -.names system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names system_timer.prescaler_1.counter[4] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[4] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[5] -01 1 -10 1 -.names system_timer.prescaler_1.counter[4] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $abc$18544$new_n5009 -11111 1 -.names system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[6] -011 1 -100 1 -101 1 -110 1 -.names system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[7] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[8] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[9] -01 1 -10 1 -.names system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $abc$18544$new_n5014 -11111 1 -.names system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[10] -011 1 -100 1 -101 1 -110 1 -.names system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[11] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names system_timer.prescaler_1.counter[12] system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[12] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[13] -01 1 -10 1 -.names system_timer.prescaler_1.counter[12] system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $abc$18544$new_n5019 -11111 1 -.names system_timer.prescaler_1.counter[14] system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[14] -011 1 -100 1 -101 1 -110 1 -.names system_timer.prescaler_1.counter[15] system_timer.prescaler_1.counter[14] system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[15] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.X[0] -0 1 -.names system_uartCtrl.uartCtrl_1.clockDivider_counter[0] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][0] -0 1 -.names $abc$18544$new_n2792 system_timer.prescaler_1.counter[15] system_timer._zz_io_limit[15] system_timer.prescaler_1.counter[1] system_timer._zz_io_limit[1] $abc$18544$new_n5024 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5024 system_timer._zz_io_limit[2] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[5] system_timer._zz_io_limit[5] $abc$18544$new_n5025 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n2786 $abc$18544$new_n5025 system_timer.prescaler_1.counter[11] system_timer._zz_io_limit[11] $abc$18544$new_n5026 -1100 1 -1111 1 -.names $abc$18544$new_n2803 system_timer.timerA.counter[15] system_timer.system_timer_timerA_io_limit_driver[15] system_timer.timerA.counter[0] system_timer.system_timer_timerA_io_limit_driver[0] $abc$18544$new_n5027 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5027 system_timer.timerA.counter[3] system_timer.system_timer_timerA_io_limit_driver[3] system_timer.timerA.counter[4] system_timer.system_timer_timerA_io_limit_driver[4] $abc$18544$new_n5028 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n2796 $abc$18544$new_n5028 system_timer.timerA.counter[14] system_timer.system_timer_timerA_io_limit_driver[14] $abc$18544$new_n5029 -1100 1 -1111 1 -.names $abc$18544$new_n2845 system_timer.timerB.counter[15] system_timer.system_timer_timerB_io_limit_driver[15] system_timer.timerB.counter[0] system_timer.system_timer_timerB_io_limit_driver[0] $abc$18544$new_n5030 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5030 system_timer.timerB.counter[3] system_timer.system_timer_timerB_io_limit_driver[3] system_timer.timerB.counter[4] system_timer.system_timer_timerB_io_limit_driver[4] $abc$18544$new_n5031 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n2837 $abc$18544$new_n5031 system_timer.timerB.counter[14] system_timer.system_timer_timerB_io_limit_driver[14] $abc$18544$new_n5032 -1100 1 -1111 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] $abc$18544$new_n5033 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n5033 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n5034 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5034 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n5035 -100 1 -111 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] $abc$18544$new_n5036 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$18544$new_n5036 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n5037 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5037 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n5038 -100 1 -111 1 -.names $abc$18544$new_n3288 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n5039 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$18544$new_n5039 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$new_n5040 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -.names $abc$18544$new_n5040 $abc$18544$new_n5047 $abc$18544$new_n5044 $abc$18544$new_n3272 $abc$18544$new_n5041 -1000 1 -.names system_cpu.HazardSimplePlugin_writeBackWrites_valid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n5042 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5042 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$18544$new_n5043 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5043 system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$new_n5044 -100 1 -111 1 -.names system_cpu.execute_arbitration_isValid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n5045 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu.decode_to_execute_REGFILE_WRITE_VALID system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$new_n5046 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5045 $abc$18544$new_n5046 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n5047 -1100 1 -1111 1 -.names $abc$18544$new_n3300 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n5048 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$18544$new_n5048 $abc$18544$new_n3299 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$18544$new_n5052 $abc$18544$new_n5049 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11100 1 -.names $abc$18544$new_n3306 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n5049 $abc$18544$new_n3291 $abc$18544$new_n5050 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names $abc$18544$new_n3304 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$new_n5051 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$18544$new_n5051 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n5052 -10000 1 -10011 1 -11100 1 -11111 1 -.names system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2[28] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n5053 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$18544$new_n3465 $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n5053 $abc$18544$new_n3485 $abc$18544$new_n5054 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$18544$new_n5054 $abc$18544$new_n3486 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] $abc$18544$new_n3255 $abc$18544$auto$rtlil.cc:2693:MuxGate$15976 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names system_cpu._zz_execute_SrcPlugin_addSub_2[12] $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2[12] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n5056 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$18544$new_n3466 $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n5056 $abc$18544$new_n3589 $abc$18544$new_n5057 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$18544$new_n3255 $abc$18544$new_n3592 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] $abc$18544$new_n5057 $abc$18544$new_n3590 $abc$18544$auto$rtlil.cc:2693:MuxGate$16008 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[2] jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment jtagBridge_1.jtag_idcodeArea_ctrl_tdo $abc$18544$new_n5059 -00001 1 -00011 1 -00101 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$18544$new_n5059 jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n5060 -1100 1 -1111 1 -.names $abc$18544$new_n2864 $abc$18544$new_n3827 $abc$18544$new_n5060 jtagBridge_1.jtag_tap_tdoIr jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment jtagBridge_1.jtag_tap_tdoUnbufferd -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14840 Q=system_cpu.DebugPlugin_busReadDataReg[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14838 Q=system_cpu.DebugPlugin_busReadDataReg[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14836 Q=system_cpu.DebugPlugin_busReadDataReg[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14834 Q=jtagBridge_1.io_remote_rsp_payload_data[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14832 Q=jtagBridge_1.io_remote_rsp_payload_data[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14830 Q=jtagBridge_1.io_remote_rsp_payload_data[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14828 Q=jtagBridge_1.io_remote_rsp_payload_data[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14826 Q=jtagBridge_1.io_remote_rsp_payload_data[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14824 Q=jtagBridge_1.io_remote_rsp_payload_data[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14822 Q=jtagBridge_1.io_remote_rsp_payload_data[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14820 Q=jtagBridge_1.io_remote_rsp_payload_data[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14818 Q=jtagBridge_1.io_remote_rsp_payload_data[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14816 Q=jtagBridge_1.io_remote_rsp_payload_data[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14814 Q=jtagBridge_1.io_remote_rsp_payload_data[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14812 Q=jtagBridge_1.io_remote_rsp_payload_data[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14810 Q=jtagBridge_1.io_remote_rsp_payload_data[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14808 Q=jtagBridge_1.io_remote_rsp_payload_data[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14806 Q=jtagBridge_1.io_remote_rsp_payload_data[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14804 Q=jtagBridge_1.io_remote_rsp_payload_data[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14802 Q=jtagBridge_1.io_remote_rsp_payload_data[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14800 Q=jtagBridge_1.io_remote_rsp_payload_data[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14798 Q=jtagBridge_1.io_remote_rsp_payload_data[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14796 Q=jtagBridge_1.io_remote_rsp_payload_data[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14794 Q=jtagBridge_1.io_remote_rsp_payload_data[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14792 Q=jtagBridge_1.io_remote_rsp_payload_data[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14790 Q=jtagBridge_1.io_remote_rsp_payload_data[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14788 Q=jtagBridge_1.io_remote_rsp_payload_data[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14786 Q=jtagBridge_1.io_remote_rsp_payload_data[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14784 Q=jtagBridge_1.io_remote_rsp_payload_data[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16774 Q=jtagBridge_1.io_remote_rsp_payload_data[31] -.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\sampler_value[0:0] Q=system_uartCtrl.uartCtrl_1.rx.sampler_value S=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.clockDivider_tickReg Q=system_uartCtrl.uartCtrl_1.rx.sampler_tick R=apb3Router_1.resetCtrl_systemReset -.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16538 Q=system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 S=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14782 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14780 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14778 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14776 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14774 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14772 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[5] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16536 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[6] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3924 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=io_uart_rxd Q=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_0 R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16564 Q=system_uartCtrl.bridge_interruptCtrl_readIntEnable R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16566 Q=system_uartCtrl.bridge_interruptCtrl_writeIntEnable R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16568 Q=system_timer.timerB.inhibitFull R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=system_uartCtrl.uartCtrl_1.io_readBreak Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_readBreak_regNext -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14770 Q=jtagBridge_1.jtag_readArea_ctrl_tdo -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14768 Q=jtagBridge_1.jtag_readArea_full_shifter[2] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14766 Q=jtagBridge_1.jtag_readArea_full_shifter[3] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14764 Q=jtagBridge_1.jtag_readArea_full_shifter[4] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14762 Q=jtagBridge_1.jtag_readArea_full_shifter[5] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14760 Q=jtagBridge_1.jtag_readArea_full_shifter[6] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14758 Q=jtagBridge_1.jtag_readArea_full_shifter[7] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14756 Q=jtagBridge_1.jtag_readArea_full_shifter[8] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14754 Q=jtagBridge_1.jtag_readArea_full_shifter[9] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14752 Q=jtagBridge_1.jtag_readArea_full_shifter[10] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14750 Q=jtagBridge_1.jtag_readArea_full_shifter[11] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14748 Q=jtagBridge_1.jtag_readArea_full_shifter[12] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14746 Q=jtagBridge_1.jtag_readArea_full_shifter[13] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14744 Q=jtagBridge_1.jtag_readArea_full_shifter[14] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14742 Q=jtagBridge_1.jtag_readArea_full_shifter[15] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14740 Q=jtagBridge_1.jtag_readArea_full_shifter[16] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14738 Q=jtagBridge_1.jtag_readArea_full_shifter[17] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14736 Q=jtagBridge_1.jtag_readArea_full_shifter[18] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14734 Q=jtagBridge_1.jtag_readArea_full_shifter[19] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14732 Q=jtagBridge_1.jtag_readArea_full_shifter[20] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14730 Q=jtagBridge_1.jtag_readArea_full_shifter[21] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14728 Q=jtagBridge_1.jtag_readArea_full_shifter[22] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14726 Q=jtagBridge_1.jtag_readArea_full_shifter[23] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14724 Q=jtagBridge_1.jtag_readArea_full_shifter[24] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14722 Q=jtagBridge_1.jtag_readArea_full_shifter[25] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14720 Q=jtagBridge_1.jtag_readArea_full_shifter[26] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14718 Q=jtagBridge_1.jtag_readArea_full_shifter[27] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14716 Q=jtagBridge_1.jtag_readArea_full_shifter[28] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14714 Q=jtagBridge_1.jtag_readArea_full_shifter[29] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14712 Q=jtagBridge_1.jtag_readArea_full_shifter[30] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14710 Q=jtagBridge_1.jtag_readArea_full_shifter[31] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14708 Q=jtagBridge_1.jtag_readArea_full_shifter[32] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16784 Q=jtagBridge_1.jtag_readArea_full_shifter[33] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16782 Q=jtagBridge_1.jtag_readArea_full_shifter[1] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16562 Q=system_uartCtrl.bridge_misc_readError R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.$0\bridge_misc_breakDetected[0:0] Q=system_uartCtrl.bridge_misc_breakDetected R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.$0\bridge_misc_doBreak[0:0] Q=system_uartCtrl.bridge_misc_doBreak R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][0] Q=system_timer.interruptCtrl_1.pendings[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][1] Q=system_timer.interruptCtrl_1.pendings[1] R=apb3Router_1.resetCtrl_systemReset -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14706 Q=system_timer.timerB.counter[0] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14704 Q=system_timer.timerB.counter[1] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14702 Q=system_timer.timerB.counter[2] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14700 Q=system_timer.timerB.counter[3] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14698 Q=system_timer.timerB.counter[4] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14696 Q=system_timer.timerB.counter[5] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14694 Q=system_timer.timerB.counter[6] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14692 Q=system_timer.timerB.counter[7] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14690 Q=system_timer.timerB.counter[8] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14688 Q=system_timer.timerB.counter[9] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14686 Q=system_timer.timerB.counter[10] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14684 Q=system_timer.timerB.counter[11] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14682 Q=system_timer.timerB.counter[12] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14680 Q=system_timer.timerB.counter[13] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14678 Q=system_timer.timerB.counter[14] R=system_timer.timerB.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16754 Q=system_timer.timerB.counter[15] R=system_timer.timerB.io_clear -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16570 Q=system_timer.timerA.inhibitFull R=apb3Router_1.resetCtrl_systemReset -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.X[0] Q=system_timer.prescaler_1.counter[0] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[1] Q=system_timer.prescaler_1.counter[1] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[2] Q=system_timer.prescaler_1.counter[2] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[3] Q=system_timer.prescaler_1.counter[3] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[4] Q=system_timer.prescaler_1.counter[4] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[5] Q=system_timer.prescaler_1.counter[5] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[6] Q=system_timer.prescaler_1.counter[6] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[7] Q=system_timer.prescaler_1.counter[7] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[8] Q=system_timer.prescaler_1.counter[8] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[9] Q=system_timer.prescaler_1.counter[9] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[10] Q=system_timer.prescaler_1.counter[10] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[11] Q=system_timer.prescaler_1.counter[11] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[12] Q=system_timer.prescaler_1.counter[12] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[13] Q=system_timer.prescaler_1.counter[13] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[14] Q=system_timer.prescaler_1.counter[14] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[15] Q=system_timer.prescaler_1.counter[15] R=system_timer.prescaler_1.when_Prescaler_l17 -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14676 Q=system_timer.interruptCtrl_1.io_masks[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16572 Q=system_timer.interruptCtrl_1.io_masks[1] R=apb3Router_1.resetCtrl_systemReset -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14674 Q=system_timer.timerA.counter[0] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14672 Q=system_timer.timerA.counter[1] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14670 Q=system_timer.timerA.counter[2] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14668 Q=system_timer.timerA.counter[3] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14666 Q=system_timer.timerA.counter[4] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14664 Q=system_timer.timerA.counter[5] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14662 Q=system_timer.timerA.counter[6] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14660 Q=system_timer.timerA.counter[7] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14658 Q=system_timer.timerA.counter[8] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14656 Q=system_timer.timerA.counter[9] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14654 Q=system_timer.timerA.counter[10] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14652 Q=system_timer.timerA.counter[11] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14650 Q=system_timer.timerA.counter[12] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14648 Q=system_timer.timerA.counter[13] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14646 Q=system_timer.timerA.counter[14] R=system_timer.timerA.io_clear -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16752 Q=system_timer.timerA.counter[15] R=system_timer.timerA.io_clear -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16700 Q=system_cpu.CsrPlugin_interrupt_code[2] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][15] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][16] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][17] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][18] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][19] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][20] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][21] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][22] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][23] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][24] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14644 Q=system_timer._zz_io_limit[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14642 Q=system_timer._zz_io_limit[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14640 Q=system_timer._zz_io_limit[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14638 Q=system_timer._zz_io_limit[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14636 Q=system_timer._zz_io_limit[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14634 Q=system_timer._zz_io_limit[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14632 Q=system_timer._zz_io_limit[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14630 Q=system_timer._zz_io_limit[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14628 Q=system_timer._zz_io_limit[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14626 Q=system_timer._zz_io_limit[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14624 Q=system_timer._zz_io_limit[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14622 Q=system_timer._zz_io_limit[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14620 Q=system_timer._zz_io_limit[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14618 Q=system_timer._zz_io_limit[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14616 Q=system_timer._zz_io_limit[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16586 Q=system_timer._zz_io_limit[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14614 Q=system_timer.system_timer_timerA_io_limit_driver[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14612 Q=system_timer.system_timer_timerA_io_limit_driver[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14610 Q=system_timer.system_timer_timerA_io_limit_driver[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14608 Q=system_timer.system_timer_timerA_io_limit_driver[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14606 Q=system_timer.system_timer_timerA_io_limit_driver[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14604 Q=system_timer.system_timer_timerA_io_limit_driver[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14602 Q=system_timer.system_timer_timerA_io_limit_driver[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14600 Q=system_timer.system_timer_timerA_io_limit_driver[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14598 Q=system_timer.system_timer_timerA_io_limit_driver[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14596 Q=system_timer.system_timer_timerA_io_limit_driver[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14594 Q=system_timer.system_timer_timerA_io_limit_driver[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14592 Q=system_timer.system_timer_timerA_io_limit_driver[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14590 Q=system_timer.system_timer_timerA_io_limit_driver[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14588 Q=system_timer.system_timer_timerA_io_limit_driver[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14586 Q=system_timer.system_timer_timerA_io_limit_driver[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16584 Q=system_timer.system_timer_timerA_io_limit_driver[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14584 Q=system_timer.system_timer_timerB_io_limit_driver[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14582 Q=system_timer.system_timer_timerB_io_limit_driver[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14580 Q=system_timer.system_timer_timerB_io_limit_driver[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14578 Q=system_timer.system_timer_timerB_io_limit_driver[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14576 Q=system_timer.system_timer_timerB_io_limit_driver[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14574 Q=system_timer.system_timer_timerB_io_limit_driver[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14572 Q=system_timer.system_timer_timerB_io_limit_driver[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14570 Q=system_timer.system_timer_timerB_io_limit_driver[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14568 Q=system_timer.system_timer_timerB_io_limit_driver[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14566 Q=system_timer.system_timer_timerB_io_limit_driver[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14564 Q=system_timer.system_timer_timerB_io_limit_driver[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14562 Q=system_timer.system_timer_timerB_io_limit_driver[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14560 Q=system_timer.system_timer_timerB_io_limit_driver[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14558 Q=system_timer.system_timer_timerB_io_limit_driver[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14556 Q=system_timer.system_timer_timerB_io_limit_driver[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16582 Q=system_timer.system_timer_timerB_io_limit_driver[15] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14554 Q=system_timer.timerABridge_ticksEnable[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16580 Q=system_timer.timerABridge_ticksEnable[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16578 Q=system_timer.timerABridge_clearsEnable R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14552 Q=system_timer.timerBBridge_ticksEnable[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16576 Q=system_timer.timerBBridge_ticksEnable[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16574 Q=system_timer.timerBBridge_clearsEnable R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=apb3Router_1._zz_selIndex Q=apb3Router_1.selIndex[0] -.subckt dff C=io_mainClk D=apb3Router_1._zz_selIndex_1 Q=apb3Router_1.selIndex[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16516 Q=system_cpu.CsrPlugin_mcause_exceptionCode[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16760 Q=system_cpu.CsrPlugin_mcause_exceptionCode[3] -.subckt dffr C=io_mainClk D=toplevel_system_cpu_debug_bus_cmd_fire Q=jtagBridge_1.io_remote_rsp_fire R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dff C=io_mainClk D=system_cpu.DebugPlugin_resetIt_regNext Q=toplevel_system_cpu_debug_resetOut_regNext -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16514 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16512 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16532 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16530 Q=system_mainBusArbiter.io_dBus_cmd_payload_wr -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16510 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16508 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16506 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16504 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16502 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16500 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16498 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16496 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16494 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16492 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16490 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16488 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16486 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16484 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16482 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16480 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16478 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16476 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16474 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16472 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16470 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16468 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16466 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16464 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16462 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16460 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16458 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16456 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16454 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16452 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16450 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16528 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16448 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16446 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16444 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16442 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16440 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16438 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16436 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16434 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16432 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16430 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16428 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16426 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16424 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16422 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16420 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16418 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16416 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16414 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16412 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16410 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16408 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16406 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16404 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16402 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16400 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16398 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16396 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16394 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16392 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16390 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16388 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16526 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16386 Q=system_mainBusArbiter.io_dBus_cmd_payload_size[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16524 Q=system_mainBusArbiter.io_dBus_cmd_payload_size[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16522 Q=system_mainBusDecoder_logic_rspSourceId -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16520 Q=system_mainBusArbiter.io_dBus_cmd_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_mainBusDecoder_logic_noHit Q=system_mainBusDecoder_logic_rspNoHit R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=resetCtrl_mainClkResetUnbuffered Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt sdffs C=io_mainClk D=resetCtrl_mainClkResetUnbuffered Q=apb3Router_1.resetCtrl_systemReset S=toplevel_system_cpu_debug_resetOut_regNext -.subckt dff C=io_mainClk D=io_asyncReset_buffercc.buffers_0 Q=io_asyncReset_buffercc.buffers_1 -.subckt dff C=io_mainClk D=io_asyncReset Q=io_asyncReset_buffercc.buffers_0 -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16384 Q=io_gpioA_writeEnable[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16382 Q=io_gpioA_writeEnable[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16380 Q=io_gpioA_writeEnable[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16378 Q=io_gpioA_writeEnable[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16376 Q=io_gpioA_writeEnable[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16374 Q=io_gpioA_writeEnable[5] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16372 Q=io_gpioA_writeEnable[6] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16370 Q=io_gpioA_writeEnable[7] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16368 Q=io_gpioA_writeEnable[8] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16366 Q=io_gpioA_writeEnable[9] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16364 Q=io_gpioA_writeEnable[10] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16362 Q=io_gpioA_writeEnable[11] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16360 Q=io_gpioA_writeEnable[12] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16358 Q=io_gpioA_writeEnable[13] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16356 Q=io_gpioA_writeEnable[14] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16354 Q=io_gpioA_writeEnable[15] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16352 Q=io_gpioA_writeEnable[16] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16350 Q=io_gpioA_writeEnable[17] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16348 Q=io_gpioA_writeEnable[18] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16346 Q=io_gpioA_writeEnable[19] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16344 Q=io_gpioA_writeEnable[20] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16342 Q=io_gpioA_writeEnable[21] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16340 Q=io_gpioA_writeEnable[22] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16338 Q=io_gpioA_writeEnable[23] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16336 Q=io_gpioA_writeEnable[24] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16334 Q=io_gpioA_writeEnable[25] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16332 Q=io_gpioA_writeEnable[26] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16330 Q=io_gpioA_writeEnable[27] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16328 Q=io_gpioA_writeEnable[28] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16326 Q=io_gpioA_writeEnable[29] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16324 Q=io_gpioA_writeEnable[30] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16590 Q=io_gpioA_writeEnable[31] R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16322 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16318 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16314 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16310 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16306 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16302 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16788 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16294 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16292 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16290 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16288 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16286 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16284 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16282 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16280 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16278 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16276 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16274 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16272 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16270 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16268 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16266 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16264 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16262 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16260 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16258 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16256 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16254 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16252 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16250 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16248 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16246 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16244 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16242 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16240 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16238 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16596 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16236 Q=resetCtrl_systemClkResetCounter[0] R=io_asyncReset_buffercc.buffers_1 -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16234 Q=resetCtrl_systemClkResetCounter[1] R=io_asyncReset_buffercc.buffers_1 -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16232 Q=resetCtrl_systemClkResetCounter[2] R=io_asyncReset_buffercc.buffers_1 -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16230 Q=resetCtrl_systemClkResetCounter[3] R=io_asyncReset_buffercc.buffers_1 -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16228 Q=resetCtrl_systemClkResetCounter[4] R=io_asyncReset_buffercc.buffers_1 -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16598 Q=resetCtrl_systemClkResetCounter[5] R=io_asyncReset_buffercc.buffers_1 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16630 Q=system_cpu.execute_CsrPlugin_csr_772 -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_interrupt_valid[0:0] Q=system_cpu.CsrPlugin_interrupt_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$true Q=system_cpu.IBusSimplePlugin_fetchPc_booted R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\writeBack_arbitration_isValid[0:0] Q=system_cpu.lastStageIsFiring R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16624 Q=system_cpu.memory_arbitration_isValid R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16628 Q=system_cpu.execute_CsrPlugin_csr_834 -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16626 Q=system_cpu.execute_arbitration_isValid R=apb3Router_1.resetCtrl_systemReset -.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[21] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[21] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 -.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[22] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[22] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 -.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[23] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[23] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 -.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[29] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[29] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 -.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[30] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[30] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 -.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[31] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[31] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[0] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[0] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[1] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[1] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[2] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[2] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[3] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[3] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[4] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[4] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[5] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[5] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[6] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[6] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[7] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[7] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[8] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[8] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[9] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[9] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[15] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[15] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[16] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[16] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[17] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[17] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[18] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[18] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[19] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[19] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[20] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[20] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[24] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[24] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[25] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[25] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[26] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[26] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[27] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[27] -.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[28] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16226 Q=apb3Router_1.io_input_PADDR[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16224 Q=apb3Router_1.io_input_PADDR[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16222 Q=apb3Router_1.io_input_PADDR[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16220 Q=apb3Router_1.io_input_PADDR[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16218 Q=apb3Router_1.io_input_PADDR[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16216 Q=apb3Router_1.io_input_PADDR[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16206 Q=apb3Router_1.io_input_PADDR[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16204 Q=apb3Router_1.io_input_PADDR[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16202 Q=apb3Router_1.io_input_PADDR[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16200 Q=apb3Router_1.io_input_PADDR[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16198 Q=apb3Router_1.io_input_PADDR[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16196 Q=apb3Router_1.io_input_PADDR[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16194 Q=apb3Router_1.io_input_PADDR[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16192 Q=apb3Router_1.io_input_PADDR[19] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16168 Q=system_cpu.IBusSimplePlugin_injector_port_state[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16166 Q=system_cpu.IBusSimplePlugin_injector_port_state[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16600 Q=system_cpu.IBusSimplePlugin_injector_port_state[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16602 Q=system_cpu.execute_LightShifterPlugin_isActive R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16604 Q=system_cpu.CsrPlugin_pipelineLiberator_done R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_valid Q=system_cpu.HazardSimplePlugin_writeBackBuffer_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16606 Q=system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 R=apb3Router_1.resetCtrl_systemReset -.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPP[1:0][0] Q=system_cpu.CsrPlugin_mstatus_MPP[0] S=apb3Router_1.resetCtrl_systemReset -.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPP[1:0][1] Q=system_cpu.CsrPlugin_mstatus_MPP[1] S=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16616 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_isPipBusy[0:0] Q=system_cpu.DebugPlugin_isPipBusy -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16164 Q=jtagBridge_1.jtag_tap_tdoIr -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16160 Q=jtagBridge_1.jtag_tap_instructionShift[1] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16156 Q=jtagBridge_1.jtag_tap_instructionShift[2] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16778 Q=jtagBridge_1.jtag_tap_instructionShift[3] -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[0] Q=system_cpu.IBusSimplePlugin_pending_value[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[1] Q=system_cpu.IBusSimplePlugin_pending_value[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[2] Q=system_cpu.IBusSimplePlugin_pending_value[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16152 Q=system_cpu.DebugPlugin_busReadDataReg[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16772 Q=system_cpu.DebugPlugin_busReadDataReg[1] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[7] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[8] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[9] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[10] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[11] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[12] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[12] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[13] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[13] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[14] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[14] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[28] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[28] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[29] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16686 Q=system_cpu.decode_to_execute_CSR_WRITE_OPCODE -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16148 Q=system_cpu.CsrPlugin_mepc[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16146 Q=system_cpu.CsrPlugin_mepc[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16144 Q=system_cpu.CsrPlugin_mepc[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16142 Q=system_cpu.CsrPlugin_mepc[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16140 Q=system_cpu.CsrPlugin_mepc[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16138 Q=system_cpu.CsrPlugin_mepc[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16136 Q=system_cpu.CsrPlugin_mepc[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16134 Q=system_cpu.CsrPlugin_mepc[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16132 Q=system_cpu.CsrPlugin_mepc[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16130 Q=system_cpu.CsrPlugin_mepc[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16128 Q=system_cpu.CsrPlugin_mepc[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16126 Q=system_cpu.CsrPlugin_mepc[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16124 Q=system_cpu.CsrPlugin_mepc[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16122 Q=system_cpu.CsrPlugin_mepc[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16120 Q=system_cpu.CsrPlugin_mepc[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16118 Q=system_cpu.CsrPlugin_mepc[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16116 Q=system_cpu.CsrPlugin_mepc[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16114 Q=system_cpu.CsrPlugin_mepc[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16112 Q=system_cpu.CsrPlugin_mepc[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16110 Q=system_cpu.CsrPlugin_mepc[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16108 Q=system_cpu.CsrPlugin_mepc[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16106 Q=system_cpu.CsrPlugin_mepc[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16104 Q=system_cpu.CsrPlugin_mepc[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16102 Q=system_cpu.CsrPlugin_mepc[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16100 Q=system_cpu.CsrPlugin_mepc[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16098 Q=system_cpu.CsrPlugin_mepc[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16096 Q=system_cpu.CsrPlugin_mepc[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16094 Q=system_cpu.CsrPlugin_mepc[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16092 Q=system_cpu.CsrPlugin_mepc[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16768 Q=system_cpu.CsrPlugin_mepc[31] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16622 Q=system_cpu.IBusSimplePlugin_fetchPc_inc R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16696 Q=system_cpu.CsrPlugin_interrupt_code[3] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16608 Q=system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16610 Q=system_cpu.CsrPlugin_mie_MSIE R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16090 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16088 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16086 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16084 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[5] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16082 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[6] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16080 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[7] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16078 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[8] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16076 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[9] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16074 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[10] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16072 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[11] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16070 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[12] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16068 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[13] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16066 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[14] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16064 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[15] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16062 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[16] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16060 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[17] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16058 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[18] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16056 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[19] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16054 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[20] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16052 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[21] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16050 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[22] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16048 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[23] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16046 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[24] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16044 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[25] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16042 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[26] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16040 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[27] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16038 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[28] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16036 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[29] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16034 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[30] R=apb3Router_1.resetCtrl_systemReset -.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16758 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[31] S=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16634 Q=system_cpu.execute_CsrPlugin_csr_768 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16632 Q=system_cpu.execute_CsrPlugin_csr_836 -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16712 Q=io_apb_decoder.io_input_PSEL R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_haltIt[0:0] Q=system_cpu.DebugPlugin_haltIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16710 Q=system_cpu.DebugPlugin_resetIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_haltedByBreak[0:0] Q=system_cpu.DebugPlugin_haltedByBreak R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffs C=io_mainClk D=$false Q=system_cpu._zz_5 S=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16614 Q=system_cpu.CsrPlugin_mie_MEIE R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16612 Q=system_cpu.CsrPlugin_mie_MTIE R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16708 Q=system_cpu.DebugPlugin_stepIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16706 Q=system_cpu.DebugPlugin_debugUsed R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16704 Q=system_cpu.DebugPlugin_disableEbreak R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16638 Q=system_cpu.execute_to_memory_BRANCH_DO -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16032 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16030 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16028 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16026 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16024 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16022 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16020 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16018 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16016 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16014 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16012 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16010 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16008 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16006 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16004 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16002 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16000 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15998 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15996 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15994 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15992 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15990 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15988 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15986 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15984 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15982 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15980 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15978 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15976 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15974 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15972 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16640 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] -.subckt dff C=io_mainClk D=systemDebugger_1._zz_io_mem_cmd_payload_address[2] Q=system_cpu._zz_when_DebugPlugin_l257 -.subckt dff C=io_mainClk D=system_cpu.DebugPlugin_resetIt Q=system_cpu.DebugPlugin_resetIt_regNext -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[0] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[0] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[1] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[1] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[2] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[2] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[3] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[3] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[4] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[4] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[5] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[5] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[6] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[6] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[7] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[7] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[8] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[9] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[10] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[11] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[12] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[13] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[14] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[15] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[16] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[17] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[18] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[19] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[20] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[21] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[22] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[23] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[26] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] -.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15970 Q=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16642 Q=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15964 Q=system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15962 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15960 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15958 Q=system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15956 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15954 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15952 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15950 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15948 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15946 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15944 Q=system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15942 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15940 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15938 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15936 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15934 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15932 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15930 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15928 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16702 Q=system_cpu._zz_decode_SRC2 -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[0] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[0] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[1] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[2] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[2] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[3] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[3] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[4] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[4] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[5] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[5] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[6] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[6] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[7] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[7] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[8] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[8] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[9] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[9] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[10] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[10] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[11] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[11] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[12] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[13] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[13] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[14] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[14] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[15] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[15] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[16] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[16] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[17] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[17] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[18] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[18] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[19] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[19] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[20] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[20] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[21] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[21] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[22] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[22] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[23] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[23] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[24] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[24] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[25] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[25] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[26] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[26] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[27] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[27] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[28] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[29] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[29] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[30] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[30] -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15926 Q=system_cpu.decode_to_execute_PC[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15924 Q=system_cpu.decode_to_execute_PC[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15922 Q=system_cpu.decode_to_execute_PC[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15920 Q=system_cpu.decode_to_execute_PC[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15918 Q=system_cpu.decode_to_execute_PC[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15916 Q=system_cpu.decode_to_execute_PC[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15914 Q=system_cpu.decode_to_execute_PC[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15912 Q=system_cpu.decode_to_execute_PC[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15910 Q=system_cpu.decode_to_execute_PC[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15908 Q=system_cpu.decode_to_execute_PC[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15906 Q=system_cpu.decode_to_execute_PC[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15904 Q=system_cpu.decode_to_execute_PC[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15902 Q=system_cpu.decode_to_execute_PC[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15900 Q=system_cpu.decode_to_execute_PC[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15898 Q=system_cpu.decode_to_execute_PC[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15896 Q=system_cpu.decode_to_execute_PC[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15894 Q=system_cpu.decode_to_execute_PC[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15892 Q=system_cpu.decode_to_execute_PC[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15890 Q=system_cpu.decode_to_execute_PC[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15888 Q=system_cpu.decode_to_execute_PC[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15886 Q=system_cpu.decode_to_execute_PC[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15884 Q=system_cpu.decode_to_execute_PC[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15882 Q=system_cpu.decode_to_execute_PC[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15880 Q=system_cpu.decode_to_execute_PC[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15878 Q=system_cpu.decode_to_execute_PC[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15876 Q=system_cpu.decode_to_execute_PC[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15874 Q=system_cpu.decode_to_execute_PC[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15872 Q=system_cpu.decode_to_execute_PC[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15870 Q=system_cpu.decode_to_execute_PC[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16766 Q=system_cpu.decode_to_execute_PC[31] -.subckt dff C=io_mainClk D=system_cpu.externalInterrupt Q=system_cpu.CsrPlugin_mip_MEIP -.subckt dff C=io_mainClk D=system_cpu.timerInterrupt Q=system_cpu.CsrPlugin_mip_MTIP -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15866 Q=system_cpu.BranchPlugin_jumpInterface_payload[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15864 Q=system_cpu.BranchPlugin_jumpInterface_payload[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15862 Q=system_cpu.BranchPlugin_jumpInterface_payload[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15860 Q=system_cpu.BranchPlugin_jumpInterface_payload[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15858 Q=system_cpu.BranchPlugin_jumpInterface_payload[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15856 Q=system_cpu.BranchPlugin_jumpInterface_payload[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15854 Q=system_cpu.BranchPlugin_jumpInterface_payload[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15852 Q=system_cpu.BranchPlugin_jumpInterface_payload[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15850 Q=system_cpu.BranchPlugin_jumpInterface_payload[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15848 Q=system_cpu.BranchPlugin_jumpInterface_payload[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15846 Q=system_cpu.BranchPlugin_jumpInterface_payload[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15844 Q=system_cpu.BranchPlugin_jumpInterface_payload[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15842 Q=system_cpu.BranchPlugin_jumpInterface_payload[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15840 Q=system_cpu.BranchPlugin_jumpInterface_payload[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15838 Q=system_cpu.BranchPlugin_jumpInterface_payload[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15836 Q=system_cpu.BranchPlugin_jumpInterface_payload[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15834 Q=system_cpu.BranchPlugin_jumpInterface_payload[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15832 Q=system_cpu.BranchPlugin_jumpInterface_payload[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15830 Q=system_cpu.BranchPlugin_jumpInterface_payload[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15828 Q=system_cpu.BranchPlugin_jumpInterface_payload[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15826 Q=system_cpu.BranchPlugin_jumpInterface_payload[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15824 Q=system_cpu.BranchPlugin_jumpInterface_payload[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15822 Q=system_cpu.BranchPlugin_jumpInterface_payload[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15820 Q=system_cpu.BranchPlugin_jumpInterface_payload[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15818 Q=system_cpu.BranchPlugin_jumpInterface_payload[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15816 Q=system_cpu.BranchPlugin_jumpInterface_payload[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15814 Q=system_cpu.BranchPlugin_jumpInterface_payload[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15812 Q=system_cpu.BranchPlugin_jumpInterface_payload[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15810 Q=system_cpu.BranchPlugin_jumpInterface_payload[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16756 Q=system_cpu.BranchPlugin_jumpInterface_payload[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15808 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15806 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15804 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15802 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15800 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15798 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15796 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15794 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15792 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15790 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15788 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15786 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15784 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15782 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15780 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15778 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15776 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15774 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15772 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15770 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15768 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15766 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15764 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15762 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15760 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15758 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15756 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15754 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15752 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16762 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] -.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] -.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] -.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] -.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] -.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16620 Q=system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16618 Q=system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15736 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15734 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15732 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15730 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15728 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15726 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15724 Q=system_cpu.switch_Misc_l241_1 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15722 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15720 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15718 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15716 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15714 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15712 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15710 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15708 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15706 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15704 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15702 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15700 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15698 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15696 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15694 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15692 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15690 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16690 Q=system_cpu._zz_execute_BranchPlugin_branch_src2 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15674 Q=system_cpu.execute_to_memory_INSTRUCTION[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15672 Q=system_cpu.execute_to_memory_INSTRUCTION[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15670 Q=system_cpu.execute_to_memory_INSTRUCTION[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15668 Q=system_cpu.execute_to_memory_INSTRUCTION[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15666 Q=system_cpu.execute_to_memory_INSTRUCTION[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15664 Q=system_cpu.execute_to_memory_INSTRUCTION[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15662 Q=system_cpu.execute_to_memory_INSTRUCTION[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15660 Q=system_cpu.execute_to_memory_INSTRUCTION[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15632 Q=system_cpu.execute_to_memory_INSTRUCTION[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15630 Q=system_cpu.execute_to_memory_INSTRUCTION[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15626 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15624 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15622 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15620 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16692 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16682 Q=system_cpu.decode_to_execute_MEMORY_ENABLE -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16678 Q=system_cpu.decode_to_execute_REGFILE_WRITE_VALID -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16680 Q=system_cpu.execute_to_memory_MEMORY_ENABLE -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_VALID Q=system_cpu._zz_lastStageRegFileWrite_valid -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPIE[0:0] Q=system_cpu.CsrPlugin_mstatus_MPIE R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MIE[0:0] Q=system_cpu.CsrPlugin_mstatus_MIE R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16684 Q=system_cpu.decode_to_execute_SRC_USE_SUB_LESS -.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ENABLE Q=system_cpu.memory_to_writeBack_MEMORY_ENABLE -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16674 Q=system_cpu.execute_to_memory_REGFILE_WRITE_VALID -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16670 Q=system_cpu.execute_to_memory_MEMORY_STORE -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16668 Q=system_cpu.decode_to_execute_IS_CSR -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16666 Q=system_cpu._zz_execute_ENV_CTRL -.subckt dff C=io_mainClk D=system_cpu._zz_memory_ENV_CTRL Q=system_cpu._zz_writeBack_ENV_CTRL -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16672 Q=system_cpu.dBus_cmd_payload_wr -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15618 Q=system_cpu._zz_execute_ALU_BITWISE_CTRL[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16658 Q=system_cpu._zz_execute_ALU_BITWISE_CTRL[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15616 Q=system_cpu._zz_execute_ALU_CTRL[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16662 Q=system_cpu._zz_execute_ALU_CTRL[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15614 Q=system_cpu._zz_execute_SHIFT_CTRL[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16656 Q=system_cpu._zz_execute_SHIFT_CTRL[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15612 Q=system_cpu._zz_execute_BRANCH_CTRL[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16654 Q=system_cpu._zz_execute_BRANCH_CTRL[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15610 Q=system_cpu._zz_dBus_cmd_payload_data[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15608 Q=system_cpu._zz_dBus_cmd_payload_data[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15606 Q=system_cpu._zz_dBus_cmd_payload_data[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15604 Q=system_cpu._zz_dBus_cmd_payload_data[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15602 Q=system_cpu._zz_dBus_cmd_payload_data[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15600 Q=system_cpu._zz_dBus_cmd_payload_data[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15598 Q=system_cpu._zz_dBus_cmd_payload_data[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15596 Q=system_cpu._zz_dBus_cmd_payload_data[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15594 Q=system_cpu.decode_to_execute_RS2[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15592 Q=system_cpu.decode_to_execute_RS2[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15590 Q=system_cpu.decode_to_execute_RS2[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15588 Q=system_cpu.decode_to_execute_RS2[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15586 Q=system_cpu.decode_to_execute_RS2[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15584 Q=system_cpu.decode_to_execute_RS2[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15582 Q=system_cpu.decode_to_execute_RS2[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15580 Q=system_cpu.decode_to_execute_RS2[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15578 Q=system_cpu.decode_to_execute_RS2[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15576 Q=system_cpu.decode_to_execute_RS2[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15574 Q=system_cpu.decode_to_execute_RS2[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15572 Q=system_cpu.decode_to_execute_RS2[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15570 Q=system_cpu.decode_to_execute_RS2[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15568 Q=system_cpu.decode_to_execute_RS2[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15566 Q=system_cpu.decode_to_execute_RS2[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15564 Q=system_cpu.decode_to_execute_RS2[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15562 Q=system_cpu.decode_to_execute_RS2[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15560 Q=system_cpu.decode_to_execute_RS2[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15558 Q=system_cpu.decode_to_execute_RS2[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15556 Q=system_cpu.decode_to_execute_RS2[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15554 Q=system_cpu.decode_to_execute_RS2[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15552 Q=system_cpu.decode_to_execute_RS2[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15550 Q=system_cpu.decode_to_execute_RS2[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16650 Q=system_cpu.decode_to_execute_RS2[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15548 Q=system_cpu.decode_to_execute_RS1[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15546 Q=system_cpu.decode_to_execute_RS1[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15544 Q=system_cpu.decode_to_execute_RS1[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15542 Q=system_cpu.decode_to_execute_RS1[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15540 Q=system_cpu.decode_to_execute_RS1[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15538 Q=system_cpu.decode_to_execute_RS1[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15536 Q=system_cpu.decode_to_execute_RS1[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15534 Q=system_cpu.decode_to_execute_RS1[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15532 Q=system_cpu.decode_to_execute_RS1[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15530 Q=system_cpu.decode_to_execute_RS1[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15528 Q=system_cpu.decode_to_execute_RS1[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15526 Q=system_cpu.decode_to_execute_RS1[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15524 Q=system_cpu.decode_to_execute_RS1[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15522 Q=system_cpu.decode_to_execute_RS1[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15520 Q=system_cpu.decode_to_execute_RS1[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15518 Q=system_cpu.decode_to_execute_RS1[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15516 Q=system_cpu.decode_to_execute_RS1[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15514 Q=system_cpu.decode_to_execute_RS1[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15512 Q=system_cpu.decode_to_execute_RS1[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15510 Q=system_cpu.decode_to_execute_RS1[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15508 Q=system_cpu.decode_to_execute_RS1[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15506 Q=system_cpu.decode_to_execute_RS1[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15504 Q=system_cpu.decode_to_execute_RS1[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15502 Q=system_cpu.decode_to_execute_RS1[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15500 Q=system_cpu.decode_to_execute_RS1[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15498 Q=system_cpu.decode_to_execute_RS1[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15496 Q=system_cpu.decode_to_execute_RS1[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15494 Q=system_cpu.decode_to_execute_RS1[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15492 Q=system_cpu.decode_to_execute_RS1[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15490 Q=system_cpu.decode_to_execute_RS1[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15488 Q=system_cpu.decode_to_execute_RS1[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16652 Q=system_cpu.decode_to_execute_RS1[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16664 Q=system_cpu._zz_memory_ENV_CTRL -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16660 Q=system_cpu.decode_to_execute_SRC_LESS_UNSIGNED -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16648 Q=system_cpu.decode_to_execute_SRC2_FORCE_ZERO -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15486 Q=system_cpu.decode_to_execute_SRC2[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15484 Q=system_cpu.decode_to_execute_SRC2[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15482 Q=system_cpu.decode_to_execute_SRC2[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15480 Q=system_cpu.decode_to_execute_SRC2[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15478 Q=system_cpu.decode_to_execute_SRC2[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15476 Q=system_cpu.decode_to_execute_SRC2[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15474 Q=system_cpu.decode_to_execute_SRC2[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15472 Q=system_cpu.decode_to_execute_SRC2[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15470 Q=system_cpu.decode_to_execute_SRC2[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15468 Q=system_cpu.decode_to_execute_SRC2[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15466 Q=system_cpu.decode_to_execute_SRC2[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15464 Q=system_cpu.decode_to_execute_SRC2[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15462 Q=system_cpu.decode_to_execute_SRC2[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15460 Q=system_cpu.decode_to_execute_SRC2[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15458 Q=system_cpu.decode_to_execute_SRC2[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15456 Q=system_cpu.decode_to_execute_SRC2[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15454 Q=system_cpu.decode_to_execute_SRC2[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15452 Q=system_cpu.decode_to_execute_SRC2[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15450 Q=system_cpu.decode_to_execute_SRC2[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15448 Q=system_cpu.decode_to_execute_SRC2[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15446 Q=system_cpu.decode_to_execute_SRC2[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15444 Q=system_cpu.decode_to_execute_SRC2[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15442 Q=system_cpu.decode_to_execute_SRC2[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15440 Q=system_cpu.decode_to_execute_SRC2[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15438 Q=system_cpu.decode_to_execute_SRC2[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15436 Q=system_cpu.decode_to_execute_SRC2[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15434 Q=system_cpu.decode_to_execute_SRC2[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15432 Q=system_cpu.decode_to_execute_SRC2[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15430 Q=system_cpu.decode_to_execute_SRC2[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15428 Q=system_cpu.decode_to_execute_SRC2[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15426 Q=system_cpu.decode_to_execute_SRC2[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16646 Q=system_cpu.decode_to_execute_SRC2[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16644 Q=system_cpu.decode_to_execute_DO_EBREAK -.subckt dffr C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid Q=jtagBridge_1.flowCCByToggle_1.io_output_valid R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 Q=jtagBridge_1.flowCCByToggle_1.outputArea_hit -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15424 Q=jtagBridge_1.system_rsp_payload_data[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15422 Q=jtagBridge_1.system_rsp_payload_data[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15420 Q=jtagBridge_1.system_rsp_payload_data[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15418 Q=jtagBridge_1.system_rsp_payload_data[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15416 Q=jtagBridge_1.system_rsp_payload_data[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15414 Q=jtagBridge_1.system_rsp_payload_data[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15412 Q=jtagBridge_1.system_rsp_payload_data[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15410 Q=jtagBridge_1.system_rsp_payload_data[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15408 Q=jtagBridge_1.system_rsp_payload_data[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15406 Q=jtagBridge_1.system_rsp_payload_data[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15404 Q=jtagBridge_1.system_rsp_payload_data[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15402 Q=jtagBridge_1.system_rsp_payload_data[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15400 Q=jtagBridge_1.system_rsp_payload_data[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15398 Q=jtagBridge_1.system_rsp_payload_data[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15396 Q=jtagBridge_1.system_rsp_payload_data[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15394 Q=jtagBridge_1.system_rsp_payload_data[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15392 Q=jtagBridge_1.system_rsp_payload_data[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15390 Q=jtagBridge_1.system_rsp_payload_data[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15388 Q=jtagBridge_1.system_rsp_payload_data[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15386 Q=jtagBridge_1.system_rsp_payload_data[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15384 Q=jtagBridge_1.system_rsp_payload_data[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15382 Q=jtagBridge_1.system_rsp_payload_data[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15380 Q=jtagBridge_1.system_rsp_payload_data[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15378 Q=jtagBridge_1.system_rsp_payload_data[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15376 Q=jtagBridge_1.system_rsp_payload_data[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15374 Q=jtagBridge_1.system_rsp_payload_data[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15372 Q=jtagBridge_1.system_rsp_payload_data[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15370 Q=jtagBridge_1.system_rsp_payload_data[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15368 Q=jtagBridge_1.system_rsp_payload_data[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15366 Q=jtagBridge_1.system_rsp_payload_data[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15364 Q=jtagBridge_1.system_rsp_payload_data[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16744 Q=jtagBridge_1.system_rsp_payload_data[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16742 Q=jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16740 Q=jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16738 Q=jtagBridge_1.flowCCByToggle_1.inputArea_target -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16736 Q=jtagBridge_1.flowCCByToggle_1.inputArea_data_last -.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_0 Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 -.subckt dff C=io_jtag_tck D=$abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] Q=jtagBridge_1.flowCCByToggle_1.io_input_valid -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15362 Q=jtagBridge_1.jtag_idcodeArea_ctrl_tdo S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15360 Q=jtagBridge_1.jtag_idcodeArea_shifter[1] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15358 Q=jtagBridge_1.jtag_idcodeArea_shifter[2] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15356 Q=jtagBridge_1.jtag_idcodeArea_shifter[3] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15354 Q=jtagBridge_1.jtag_idcodeArea_shifter[4] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15352 Q=jtagBridge_1.jtag_idcodeArea_shifter[5] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15350 Q=jtagBridge_1.jtag_idcodeArea_shifter[6] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15348 Q=jtagBridge_1.jtag_idcodeArea_shifter[7] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15346 Q=jtagBridge_1.jtag_idcodeArea_shifter[8] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15344 Q=jtagBridge_1.jtag_idcodeArea_shifter[9] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15342 Q=jtagBridge_1.jtag_idcodeArea_shifter[10] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15340 Q=jtagBridge_1.jtag_idcodeArea_shifter[11] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15338 Q=jtagBridge_1.jtag_idcodeArea_shifter[12] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15336 Q=jtagBridge_1.jtag_idcodeArea_shifter[13] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15334 Q=jtagBridge_1.jtag_idcodeArea_shifter[14] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15332 Q=jtagBridge_1.jtag_idcodeArea_shifter[15] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15330 Q=jtagBridge_1.jtag_idcodeArea_shifter[16] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15328 Q=jtagBridge_1.jtag_idcodeArea_shifter[17] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15326 Q=jtagBridge_1.jtag_idcodeArea_shifter[18] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15324 Q=jtagBridge_1.jtag_idcodeArea_shifter[19] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15322 Q=jtagBridge_1.jtag_idcodeArea_shifter[20] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15320 Q=jtagBridge_1.jtag_idcodeArea_shifter[21] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15318 Q=jtagBridge_1.jtag_idcodeArea_shifter[22] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15316 Q=jtagBridge_1.jtag_idcodeArea_shifter[23] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15314 Q=jtagBridge_1.jtag_idcodeArea_shifter[24] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15312 Q=jtagBridge_1.jtag_idcodeArea_shifter[25] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15310 Q=jtagBridge_1.jtag_idcodeArea_shifter[26] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15308 Q=jtagBridge_1.jtag_idcodeArea_shifter[27] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15306 Q=jtagBridge_1.jtag_idcodeArea_shifter[28] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15304 Q=jtagBridge_1.jtag_idcodeArea_shifter[29] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15302 Q=jtagBridge_1.jtag_idcodeArea_shifter[30] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16748 Q=jtagBridge_1.jtag_idcodeArea_shifter[31] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture -.subckt dff C=io_jtag_tck D=io_jtag_tdi Q=jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment -.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15300 Q=jtagBridge_1._zz_jtag_tap_isBypass[0] S=jtagBridge_1.when_JtagTap_l120 -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15298 Q=jtagBridge_1._zz_jtag_tap_isBypass[1] R=jtagBridge_1.when_JtagTap_l120 -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15296 Q=jtagBridge_1._zz_jtag_tap_isBypass[2] R=jtagBridge_1.when_JtagTap_l120 -.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16746 Q=jtagBridge_1._zz_jtag_tap_isBypass[3] R=jtagBridge_1.when_JtagTap_l120 -.subckt sdffrn C=io_mainClk D=system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] Q=system_cpu.CsrPlugin_mip_MSIP RN=$abc$18544$auto$opt_dff.cc:253:combine_resets$3598 -.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[0] Q=jtagBridge_1.jtag_tap_fsm_state[0] -.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[1] Q=jtagBridge_1.jtag_tap_fsm_state[1] -.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[2] Q=jtagBridge_1.jtag_tap_fsm_state[2] -.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[3] Q=jtagBridge_1.jtag_tap_fsm_state[3] -.subckt dffn C=io_jtag_tck D=jtagBridge_1.jtag_tap_tdoUnbufferd Q=io_jtag_tdo -.subckt sdffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16750 Q=jtagBridge_1.system_rsp_valid S=jtagBridge_1.io_remote_rsp_fire -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15294 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15290 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15286 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16792 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15282 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15280 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15278 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15276 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15274 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15272 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15270 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15268 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15266 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15264 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15262 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15260 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15258 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15256 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15254 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15252 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15250 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15248 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15246 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15244 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16794 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[31] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16518 Q=system_mainBusArbiter.rspPending R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_0 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15242 Q=systemDebugger_1.dispatcher_header[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15240 Q=systemDebugger_1.dispatcher_header[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15238 Q=systemDebugger_1.dispatcher_header[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15236 Q=systemDebugger_1.dispatcher_header[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15234 Q=systemDebugger_1.dispatcher_header[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15232 Q=systemDebugger_1.dispatcher_header[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15230 Q=systemDebugger_1.dispatcher_header[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16730 Q=systemDebugger_1.dispatcher_header[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15224 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15222 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15220 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15218 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15216 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15214 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15212 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15210 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15208 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15206 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15204 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15202 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15200 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15198 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15196 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15194 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15192 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15190 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15188 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15186 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15184 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15182 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15180 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15178 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15176 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15174 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15172 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15170 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15168 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15166 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15164 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[32] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15162 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[33] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15160 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[34] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15158 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[35] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15156 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[36] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15154 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[37] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15152 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[38] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15150 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[39] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15148 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[40] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15146 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[41] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15144 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[42] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15142 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[43] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15140 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[44] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15138 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[45] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15136 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[46] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15134 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[47] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15132 Q=system_cpu.when_DebugPlugin_l284 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15130 Q=system_cpu.when_DebugPlugin_l285 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15128 Q=system_cpu.when_DebugPlugin_l288 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15126 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[51] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15124 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[52] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15122 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[53] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15120 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[54] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15118 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[55] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15116 Q=system_cpu.when_DebugPlugin_l284_1 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15114 Q=system_cpu.when_DebugPlugin_l285_1 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15112 Q=system_cpu.when_DebugPlugin_l288_1 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15110 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[59] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15108 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[60] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15106 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[61] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15104 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[62] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15102 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[63] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15100 Q=systemDebugger_1.io_mem_cmd_payload_wr -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15098 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[65] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16732 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[66] -.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16734 Q=jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16728 Q=systemDebugger_1.dispatcher_dataLoaded R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16726 Q=systemDebugger_1.dispatcher_headerLoaded R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16588 Q=system_mainBusArbiter.rspTarget R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_ram.$0\_zz_io_bus_rsp_valid[0:0] Q=system_ram._zz_io_bus_rsp_valid R=apb3Router_1.resetCtrl_systemReset -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[10] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[10] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[11] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[11] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[12] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[12] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[13] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[13] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP -.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[14] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[14] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15096 Q=system_uartCtrl.when_BusSlaveFactory_l347 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15094 Q=system_uartCtrl.when_BusSlaveFactory_l347_1 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15092 Q=apb3Router_1.io_input_PWDATA[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15090 Q=apb3Router_1.io_input_PWDATA[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15088 Q=apb3Router_1.io_input_PWDATA[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15086 Q=apb3Router_1.io_input_PWDATA[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15084 Q=apb3Router_1.io_input_PWDATA[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15082 Q=apb3Router_1.io_input_PWDATA[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15080 Q=apb3Router_1.io_input_PWDATA[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15078 Q=system_uartCtrl.when_BusSlaveFactory_l347_2 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15076 Q=system_uartCtrl.when_BusSlaveFactory_l379 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15074 Q=system_uartCtrl.when_BusSlaveFactory_l347_3 -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15072 Q=apb3Router_1.io_input_PWDATA[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15070 Q=apb3Router_1.io_input_PWDATA[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15068 Q=apb3Router_1.io_input_PWDATA[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15066 Q=apb3Router_1.io_input_PWDATA[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15064 Q=apb3Router_1.io_input_PWDATA[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15062 Q=apb3Router_1.io_input_PWDATA[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15060 Q=apb3Router_1.io_input_PWDATA[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15058 Q=apb3Router_1.io_input_PWDATA[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15056 Q=apb3Router_1.io_input_PWDATA[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15054 Q=apb3Router_1.io_input_PWDATA[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15052 Q=apb3Router_1.io_input_PWDATA[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15050 Q=apb3Router_1.io_input_PWDATA[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15048 Q=apb3Router_1.io_input_PWDATA[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15046 Q=apb3Router_1.io_input_PWDATA[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15044 Q=apb3Router_1.io_input_PWDATA[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15042 Q=apb3Router_1.io_input_PWDATA[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15040 Q=apb3Router_1.io_input_PWDATA[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15038 Q=apb3Router_1.io_input_PWDATA[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15036 Q=apb3Router_1.io_input_PWDATA[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16714 Q=apb3Router_1.io_input_PWDATA[31] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16722 Q=apb3Router_1.io_input_PWRITE -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15034 Q=apb3Router_1.io_input_PADDR[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16718 Q=apb3Router_1.io_input_PADDR[1] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15030 Q=systemDebugger_1.dispatcher_counter[0] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15028 Q=systemDebugger_1.dispatcher_counter[1] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16724 Q=systemDebugger_1.dispatcher_counter[2] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset -.subckt dffr C=io_mainClk D=system_apbBridge.pipelinedMemoryBusStage_rsp_valid Q=system_apbBridge.io_pipelinedMemoryBus_rsp_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_apbBridge.$0\state[0:0] Q=apb3Router_1.io_input_PENABLE R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[0] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[0] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[1] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[1] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[2] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[2] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[3] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[3] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[4] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[4] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[5] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[5] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[6] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[6] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[7] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[7] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[8] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[8] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[9] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[9] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[10] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[10] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[11] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[11] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[12] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[12] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[13] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[13] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[14] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[14] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[15] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[15] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[16] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[16] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[17] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[17] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[18] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[18] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[19] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[19] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[20] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[20] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[21] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[21] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[22] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[22] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[23] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[23] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[24] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[24] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[25] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[25] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[26] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[26] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[27] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[27] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[28] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[28] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[29] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[29] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[30] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[30] -.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[31] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[31] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16594 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15026 Q=io_gpioA_write[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15024 Q=io_gpioA_write[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15022 Q=io_gpioA_write[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15020 Q=io_gpioA_write[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15018 Q=io_gpioA_write[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15016 Q=io_gpioA_write[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15014 Q=io_gpioA_write[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15012 Q=io_gpioA_write[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15010 Q=io_gpioA_write[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15008 Q=io_gpioA_write[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15006 Q=io_gpioA_write[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15004 Q=io_gpioA_write[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15002 Q=io_gpioA_write[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15000 Q=io_gpioA_write[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14998 Q=io_gpioA_write[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14996 Q=io_gpioA_write[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14994 Q=io_gpioA_write[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14992 Q=io_gpioA_write[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14990 Q=io_gpioA_write[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14988 Q=io_gpioA_write[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14986 Q=io_gpioA_write[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14984 Q=io_gpioA_write[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14982 Q=io_gpioA_write[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14980 Q=io_gpioA_write[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14978 Q=io_gpioA_write[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14976 Q=io_gpioA_write[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14974 Q=io_gpioA_write[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14972 Q=io_gpioA_write[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14970 Q=io_gpioA_write[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14968 Q=io_gpioA_write[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14966 Q=io_gpioA_write[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16592 Q=io_gpioA_write[31] -.subckt dff C=io_mainClk D=io_gpioA_read[0] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[0] -.subckt dff C=io_mainClk D=io_gpioA_read[1] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[1] -.subckt dff C=io_mainClk D=io_gpioA_read[2] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[2] -.subckt dff C=io_mainClk D=io_gpioA_read[3] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[3] -.subckt dff C=io_mainClk D=io_gpioA_read[4] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[4] -.subckt dff C=io_mainClk D=io_gpioA_read[5] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[5] -.subckt dff C=io_mainClk D=io_gpioA_read[6] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[6] -.subckt dff C=io_mainClk D=io_gpioA_read[7] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[7] -.subckt dff C=io_mainClk D=io_gpioA_read[8] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[8] -.subckt dff C=io_mainClk D=io_gpioA_read[9] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[9] -.subckt dff C=io_mainClk D=io_gpioA_read[10] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[10] -.subckt dff C=io_mainClk D=io_gpioA_read[11] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[11] -.subckt dff C=io_mainClk D=io_gpioA_read[12] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[12] -.subckt dff C=io_mainClk D=io_gpioA_read[13] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[13] -.subckt dff C=io_mainClk D=io_gpioA_read[14] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[14] -.subckt dff C=io_mainClk D=io_gpioA_read[15] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[15] -.subckt dff C=io_mainClk D=io_gpioA_read[16] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[16] -.subckt dff C=io_mainClk D=io_gpioA_read[17] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[17] -.subckt dff C=io_mainClk D=io_gpioA_read[18] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[18] -.subckt dff C=io_mainClk D=io_gpioA_read[19] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[19] -.subckt dff C=io_mainClk D=io_gpioA_read[20] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[20] -.subckt dff C=io_mainClk D=io_gpioA_read[21] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[21] -.subckt dff C=io_mainClk D=io_gpioA_read[22] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[22] -.subckt dff C=io_mainClk D=io_gpioA_read[23] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[23] -.subckt dff C=io_mainClk D=io_gpioA_read[24] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[24] -.subckt dff C=io_mainClk D=io_gpioA_read[25] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[25] -.subckt dff C=io_mainClk D=io_gpioA_read[26] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[26] -.subckt dff C=io_mainClk D=io_gpioA_read[27] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[27] -.subckt dff C=io_mainClk D=io_gpioA_read[28] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[28] -.subckt dff C=io_mainClk D=io_gpioA_read[29] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[29] -.subckt dff C=io_mainClk D=io_gpioA_read[30] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[30] -.subckt dff C=io_mainClk D=io_gpioA_read[31] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[31] -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14964 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14962 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14960 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14958 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16550 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14956 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14954 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14952 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14950 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16548 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16546 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14948 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14946 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14944 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14942 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16544 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16560 Q=system_uartCtrl.bridge_misc_readOverflowError R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14940 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14938 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14936 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14934 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16558 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14932 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14930 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14928 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14926 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16556 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16554 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14924 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14922 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14920 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14918 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16552 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][0] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][1] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][2] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][3] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[3] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][4] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[4] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][5] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[5] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][6] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[6] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][7] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[7] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][8] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[8] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][9] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[9] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][10] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[10] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][11] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[11] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][12] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[12] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][13] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[13] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][14] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[14] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][15] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[15] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][16] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[16] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][17] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[17] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][18] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[18] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][19] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[19] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.clockDivider_tick Q=system_uartCtrl.uartCtrl_1.clockDivider_tickReg R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[0] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[1] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[2] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14916 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14914 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] R=apb3Router_1.resetCtrl_systemReset -.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16534 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] R=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[0] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[1] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[2] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\stateMachine_parity[0:0] Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_parity -.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\_zz_io_txd[0:0] Q=io_uart_txd S=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14912 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14910 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14908 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14906 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14904 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14902 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14900 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14898 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14896 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14894 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14892 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14890 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14888 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14886 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14884 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14882 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14880 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14878 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14876 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14874 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14872 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14870 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14868 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14866 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14864 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14862 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14860 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14858 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14856 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16764 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] -.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_0 Q=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 R=apb3Router_1.resetCtrl_systemReset -.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16540 Q=system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 S=apb3Router_1.resetCtrl_systemReset -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14854 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14852 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14850 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14848 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14846 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14844 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14842 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16542 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\stateMachine_parity[0:0] Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_parity -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[0] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[1] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] -.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[2] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][0] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][1] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] -.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][2] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=system_cpu.lastStageRegFileWrite_payload_data[0] data_i[34]=system_cpu.lastStageRegFileWrite_payload_data[1] data_i[33]=system_cpu.lastStageRegFileWrite_payload_data[2] data_i[32]=system_cpu.lastStageRegFileWrite_payload_data[3] data_i[31]=system_cpu.lastStageRegFileWrite_payload_data[4] data_i[30]=system_cpu.lastStageRegFileWrite_payload_data[5] data_i[29]=system_cpu.lastStageRegFileWrite_payload_data[6] data_i[28]=system_cpu.lastStageRegFileWrite_payload_data[7] data_i[27]=system_cpu.lastStageRegFileWrite_payload_data[8] data_i[26]=system_cpu.lastStageRegFileWrite_payload_data[9] data_i[25]=system_cpu.lastStageRegFileWrite_payload_data[10] data_i[24]=system_cpu.lastStageRegFileWrite_payload_data[11] data_i[23]=system_cpu.lastStageRegFileWrite_payload_data[12] data_i[22]=system_cpu.lastStageRegFileWrite_payload_data[13] data_i[21]=system_cpu.lastStageRegFileWrite_payload_data[14] data_i[20]=system_cpu.lastStageRegFileWrite_payload_data[15] data_i[19]=system_cpu.lastStageRegFileWrite_payload_data[16] data_i[18]=system_cpu.lastStageRegFileWrite_payload_data[17] data_i[17]=system_cpu.lastStageRegFileWrite_payload_data[18] data_i[16]=system_cpu.lastStageRegFileWrite_payload_data[19] data_i[15]=system_cpu.lastStageRegFileWrite_payload_data[20] data_i[14]=system_cpu.lastStageRegFileWrite_payload_data[21] data_i[13]=system_cpu.lastStageRegFileWrite_payload_data[22] data_i[12]=system_cpu.lastStageRegFileWrite_payload_data[23] data_i[11]=system_cpu.lastStageRegFileWrite_payload_data[24] data_i[10]=system_cpu.lastStageRegFileWrite_payload_data[25] data_i[9]=system_cpu.lastStageRegFileWrite_payload_data[26] data_i[8]=system_cpu.lastStageRegFileWrite_payload_data[27] data_i[7]=system_cpu.lastStageRegFileWrite_payload_data[28] data_i[6]=system_cpu.lastStageRegFileWrite_payload_data[29] data_i[5]=system_cpu.lastStageRegFileWrite_payload_data[30] data_i[4]=system_cpu.lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=system_cpu._zz_RegFilePlugin_regFile_port1[0] q_o[34]=system_cpu._zz_RegFilePlugin_regFile_port1[1] q_o[33]=system_cpu._zz_RegFilePlugin_regFile_port1[2] q_o[32]=system_cpu._zz_RegFilePlugin_regFile_port1[3] q_o[31]=system_cpu._zz_RegFilePlugin_regFile_port1[4] q_o[30]=system_cpu._zz_RegFilePlugin_regFile_port1[5] q_o[29]=system_cpu._zz_RegFilePlugin_regFile_port1[6] q_o[28]=system_cpu._zz_RegFilePlugin_regFile_port1[7] q_o[27]=system_cpu._zz_RegFilePlugin_regFile_port1[8] q_o[26]=system_cpu._zz_RegFilePlugin_regFile_port1[9] q_o[25]=system_cpu._zz_RegFilePlugin_regFile_port1[10] q_o[24]=system_cpu._zz_RegFilePlugin_regFile_port1[11] q_o[23]=system_cpu._zz_RegFilePlugin_regFile_port1[12] q_o[22]=system_cpu._zz_RegFilePlugin_regFile_port1[13] q_o[21]=system_cpu._zz_RegFilePlugin_regFile_port1[14] q_o[20]=system_cpu._zz_RegFilePlugin_regFile_port1[15] q_o[19]=system_cpu._zz_RegFilePlugin_regFile_port1[16] q_o[18]=system_cpu._zz_RegFilePlugin_regFile_port1[17] q_o[17]=system_cpu._zz_RegFilePlugin_regFile_port1[18] q_o[16]=system_cpu._zz_RegFilePlugin_regFile_port1[19] q_o[15]=system_cpu._zz_RegFilePlugin_regFile_port1[20] q_o[14]=system_cpu._zz_RegFilePlugin_regFile_port1[21] q_o[13]=system_cpu._zz_RegFilePlugin_regFile_port1[22] q_o[12]=system_cpu._zz_RegFilePlugin_regFile_port1[23] q_o[11]=system_cpu._zz_RegFilePlugin_regFile_port1[24] q_o[10]=system_cpu._zz_RegFilePlugin_regFile_port1[25] q_o[9]=system_cpu._zz_RegFilePlugin_regFile_port1[26] q_o[8]=system_cpu._zz_RegFilePlugin_regFile_port1[27] q_o[7]=system_cpu._zz_RegFilePlugin_regFile_port1[28] q_o[6]=system_cpu._zz_RegFilePlugin_regFile_port1[29] q_o[5]=system_cpu._zz_RegFilePlugin_regFile_port1[30] q_o[4]=system_cpu._zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4542[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4542[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4542[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4542[35] raddr_i[7]=system_cpu.decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=system_cpu.decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=system_cpu.decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=system_cpu.decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=system_cpu.decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=$true waddr_i[7]=system_cpu.lastStageRegFileWrite_payload_address[0] waddr_i[6]=system_cpu.lastStageRegFileWrite_payload_address[1] waddr_i[5]=system_cpu.lastStageRegFileWrite_payload_address[2] waddr_i[4]=system_cpu.lastStageRegFileWrite_payload_address[3] waddr_i[3]=system_cpu.lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_cpu._zz_1 -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=system_cpu.lastStageRegFileWrite_payload_data[0] data_i[34]=system_cpu.lastStageRegFileWrite_payload_data[1] data_i[33]=system_cpu.lastStageRegFileWrite_payload_data[2] data_i[32]=system_cpu.lastStageRegFileWrite_payload_data[3] data_i[31]=system_cpu.lastStageRegFileWrite_payload_data[4] data_i[30]=system_cpu.lastStageRegFileWrite_payload_data[5] data_i[29]=system_cpu.lastStageRegFileWrite_payload_data[6] data_i[28]=system_cpu.lastStageRegFileWrite_payload_data[7] data_i[27]=system_cpu.lastStageRegFileWrite_payload_data[8] data_i[26]=system_cpu.lastStageRegFileWrite_payload_data[9] data_i[25]=system_cpu.lastStageRegFileWrite_payload_data[10] data_i[24]=system_cpu.lastStageRegFileWrite_payload_data[11] data_i[23]=system_cpu.lastStageRegFileWrite_payload_data[12] data_i[22]=system_cpu.lastStageRegFileWrite_payload_data[13] data_i[21]=system_cpu.lastStageRegFileWrite_payload_data[14] data_i[20]=system_cpu.lastStageRegFileWrite_payload_data[15] data_i[19]=system_cpu.lastStageRegFileWrite_payload_data[16] data_i[18]=system_cpu.lastStageRegFileWrite_payload_data[17] data_i[17]=system_cpu.lastStageRegFileWrite_payload_data[18] data_i[16]=system_cpu.lastStageRegFileWrite_payload_data[19] data_i[15]=system_cpu.lastStageRegFileWrite_payload_data[20] data_i[14]=system_cpu.lastStageRegFileWrite_payload_data[21] data_i[13]=system_cpu.lastStageRegFileWrite_payload_data[22] data_i[12]=system_cpu.lastStageRegFileWrite_payload_data[23] data_i[11]=system_cpu.lastStageRegFileWrite_payload_data[24] data_i[10]=system_cpu.lastStageRegFileWrite_payload_data[25] data_i[9]=system_cpu.lastStageRegFileWrite_payload_data[26] data_i[8]=system_cpu.lastStageRegFileWrite_payload_data[27] data_i[7]=system_cpu.lastStageRegFileWrite_payload_data[28] data_i[6]=system_cpu.lastStageRegFileWrite_payload_data[29] data_i[5]=system_cpu.lastStageRegFileWrite_payload_data[30] data_i[4]=system_cpu.lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=system_cpu._zz_RegFilePlugin_regFile_port0[0] q_o[34]=system_cpu._zz_RegFilePlugin_regFile_port0[1] q_o[33]=system_cpu._zz_RegFilePlugin_regFile_port0[2] q_o[32]=system_cpu._zz_RegFilePlugin_regFile_port0[3] q_o[31]=system_cpu._zz_RegFilePlugin_regFile_port0[4] q_o[30]=system_cpu._zz_RegFilePlugin_regFile_port0[5] q_o[29]=system_cpu._zz_RegFilePlugin_regFile_port0[6] q_o[28]=system_cpu._zz_RegFilePlugin_regFile_port0[7] q_o[27]=system_cpu._zz_RegFilePlugin_regFile_port0[8] q_o[26]=system_cpu._zz_RegFilePlugin_regFile_port0[9] q_o[25]=system_cpu._zz_RegFilePlugin_regFile_port0[10] q_o[24]=system_cpu._zz_RegFilePlugin_regFile_port0[11] q_o[23]=system_cpu._zz_RegFilePlugin_regFile_port0[12] q_o[22]=system_cpu._zz_RegFilePlugin_regFile_port0[13] q_o[21]=system_cpu._zz_RegFilePlugin_regFile_port0[14] q_o[20]=system_cpu._zz_RegFilePlugin_regFile_port0[15] q_o[19]=system_cpu._zz_RegFilePlugin_regFile_port0[16] q_o[18]=system_cpu._zz_RegFilePlugin_regFile_port0[17] q_o[17]=system_cpu._zz_RegFilePlugin_regFile_port0[18] q_o[16]=system_cpu._zz_RegFilePlugin_regFile_port0[19] q_o[15]=system_cpu._zz_RegFilePlugin_regFile_port0[20] q_o[14]=system_cpu._zz_RegFilePlugin_regFile_port0[21] q_o[13]=system_cpu._zz_RegFilePlugin_regFile_port0[22] q_o[12]=system_cpu._zz_RegFilePlugin_regFile_port0[23] q_o[11]=system_cpu._zz_RegFilePlugin_regFile_port0[24] q_o[10]=system_cpu._zz_RegFilePlugin_regFile_port0[25] q_o[9]=system_cpu._zz_RegFilePlugin_regFile_port0[26] q_o[8]=system_cpu._zz_RegFilePlugin_regFile_port0[27] q_o[7]=system_cpu._zz_RegFilePlugin_regFile_port0[28] q_o[6]=system_cpu._zz_RegFilePlugin_regFile_port0[29] q_o[5]=system_cpu._zz_RegFilePlugin_regFile_port0[30] q_o[4]=system_cpu._zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4543[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4543[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4543[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4543[35] raddr_i[7]=system_cpu.decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=system_cpu.decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=system_cpu.decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=system_cpu.decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=system_cpu.decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=$true waddr_i[7]=system_cpu.lastStageRegFileWrite_payload_address[0] waddr_i[6]=system_cpu.lastStageRegFileWrite_payload_address[1] waddr_i[5]=system_cpu.lastStageRegFileWrite_payload_address[2] waddr_i[4]=system_cpu.lastStageRegFileWrite_payload_address[3] waddr_i[3]=system_cpu.lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_cpu._zz_1 -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] q_o[3]=system_ram._zz_ram_port0[0] q_o[2]=system_ram._zz_ram_port0[1] q_o[1]=system_ram._zz_ram_port0[2] q_o[0]=system_ram._zz_ram_port0[3] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] q_o[3]=system_ram._zz_ram_port0[4] q_o[2]=system_ram._zz_ram_port0[5] q_o[1]=system_ram._zz_ram_port0[6] q_o[0]=system_ram._zz_ram_port0[7] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] q_o[3]=system_ram._zz_ram_port0[8] q_o[2]=system_ram._zz_ram_port0[9] q_o[1]=system_ram._zz_ram_port0[10] q_o[0]=system_ram._zz_ram_port0[11] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] q_o[3]=system_ram._zz_ram_port0[12] q_o[2]=system_ram._zz_ram_port0[13] q_o[1]=system_ram._zz_ram_port0[14] q_o[0]=system_ram._zz_ram_port0[15] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] q_o[3]=system_ram._zz_ram_port0[16] q_o[2]=system_ram._zz_ram_port0[17] q_o[1]=system_ram._zz_ram_port0[18] q_o[0]=system_ram._zz_ram_port0[19] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] q_o[3]=system_ram._zz_ram_port0[20] q_o[2]=system_ram._zz_ram_port0[21] q_o[1]=system_ram._zz_ram_port0[22] q_o[0]=system_ram._zz_ram_port0[23] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] q_o[3]=system_ram._zz_ram_port0[24] q_o[2]=system_ram._zz_ram_port0[25] q_o[1]=system_ram._zz_ram_port0[26] q_o[0]=system_ram._zz_ram_port0[27] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] q_o[3]=system_ram._zz_ram_port0[28] q_o[2]=system_ram._zz_ram_port0[29] q_o[1]=system_ram._zz_ram_port0[30] q_o[0]=system_ram._zz_ram_port0[31] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=system_uartCtrl.when_BusSlaveFactory_l347 data_i[7]=system_uartCtrl.when_BusSlaveFactory_l347_1 data_i[6]=apb3Router_1.io_input_PWDATA[2] data_i[5]=apb3Router_1.io_input_PWDATA[3] data_i[4]=apb3Router_1.io_input_PWDATA[4] data_i[3]=apb3Router_1.io_input_PWDATA[5] data_i[2]=apb3Router_1.io_input_PWDATA[6] data_i[1]=apb3Router_1.io_input_PWDATA[7] data_i[0]=$undef q_o[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[0] q_o[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[1] q_o[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[2] q_o[5]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[3] q_o[4]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[4] q_o[3]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[5] q_o[2]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[6] q_o[1]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4558[8] raddr_i[9]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] raddr_i[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] raddr_i[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] raddr_i[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] raddr_i[5]=$false raddr_i[4]=$false raddr_i[3]=$false raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire waddr_i[9]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] waddr_i[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] waddr_i[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] waddr_i[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] waddr_i[5]=$false waddr_i[4]=$false waddr_i[3]=$false waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] data_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] data_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] data_i[5]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] data_i[4]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] data_i[3]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] data_i[2]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] data_i[1]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] data_i[0]=$undef q_o[8]=system_uartCtrl.bridge_read_streamBreaked_payload[0] q_o[7]=system_uartCtrl.bridge_read_streamBreaked_payload[1] q_o[6]=system_uartCtrl.bridge_read_streamBreaked_payload[2] q_o[5]=system_uartCtrl.bridge_read_streamBreaked_payload[3] q_o[4]=system_uartCtrl.bridge_read_streamBreaked_payload[4] q_o[3]=system_uartCtrl.bridge_read_streamBreaked_payload[5] q_o[2]=system_uartCtrl.bridge_read_streamBreaked_payload[6] q_o[1]=system_uartCtrl.bridge_read_streamBreaked_payload[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4560[8] raddr_i[9]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] raddr_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] raddr_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] raddr_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] raddr_i[5]=$false raddr_i[4]=$false raddr_i[3]=$false raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire waddr_i[9]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] waddr_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] waddr_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] waddr_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] waddr_i[5]=$false waddr_i[4]=$false waddr_i[3]=$false waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 -.names system_timer.prescaler_1.counter[1] $auto$alumacc.cc:485:replace_alu$4095.X[1] -1 1 -.names system_timer.prescaler_1.counter[2] $auto$alumacc.cc:485:replace_alu$4095.X[2] -1 1 -.names system_timer.prescaler_1.counter[3] $auto$alumacc.cc:485:replace_alu$4095.X[3] -1 1 -.names system_timer.prescaler_1.counter[4] $auto$alumacc.cc:485:replace_alu$4095.X[4] -1 1 -.names system_timer.prescaler_1.counter[5] $auto$alumacc.cc:485:replace_alu$4095.X[5] -1 1 -.names system_timer.prescaler_1.counter[6] $auto$alumacc.cc:485:replace_alu$4095.X[6] -1 1 -.names system_timer.prescaler_1.counter[7] $auto$alumacc.cc:485:replace_alu$4095.X[7] -1 1 -.names system_timer.prescaler_1.counter[8] $auto$alumacc.cc:485:replace_alu$4095.X[8] -1 1 -.names system_timer.prescaler_1.counter[9] $auto$alumacc.cc:485:replace_alu$4095.X[9] -1 1 -.names system_timer.prescaler_1.counter[10] $auto$alumacc.cc:485:replace_alu$4095.X[10] -1 1 -.names system_timer.prescaler_1.counter[11] $auto$alumacc.cc:485:replace_alu$4095.X[11] -1 1 -.names system_timer.prescaler_1.counter[12] $auto$alumacc.cc:485:replace_alu$4095.X[12] -1 1 -.names system_timer.prescaler_1.counter[13] $auto$alumacc.cc:485:replace_alu$4095.X[13] -1 1 -.names system_timer.prescaler_1.counter[14] $auto$alumacc.cc:485:replace_alu$4095.X[14] -1 1 -.names system_timer.prescaler_1.counter[15] $auto$alumacc.cc:485:replace_alu$4095.X[15] -1 1 -.names $auto$alumacc.cc:485:replace_alu$4095.X[0] $auto$alumacc.cc:485:replace_alu$4095.Y[0] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$4542[0] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$4542[1] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$4542[2] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$4542[3] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$4542[4] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$4542[5] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$4542[6] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$4542[7] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$4542[8] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$4542[9] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$4542[10] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$4542[11] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$4542[12] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$4542[13] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$4542[14] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$4542[15] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$4542[16] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$4542[17] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$4542[18] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$4542[19] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$4542[20] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$4542[21] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$4542[22] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$4542[23] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$4542[24] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$4542[25] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$4542[26] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$4542[27] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$4542[28] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$4542[29] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$4542[30] -1 1 -.names system_cpu._zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$4542[31] -1 1 -.names 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apb3Router_1.io_input_PWDATA[10] -1 1 -.names system_uartCtrl.when_BusSlaveFactory_l347_3 apb3Router_1.io_input_PWDATA[11] -1 1 -.names jtagBridge_1.jtag_idcodeArea_ctrl_tdo jtagBridge_1.jtag_idcodeArea_shifter[0] -1 1 -.names jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.jtag_readArea_full_shifter[0] -1 1 -.names jtagBridge_1.jtag_tap_tdoIr jtagBridge_1.jtag_tap_instructionShift[0] -1 1 -.names system_cpu.when_DebugPlugin_l284 systemDebugger_1._zz_io_mem_cmd_payload_address[48] -1 1 -.names system_cpu.when_DebugPlugin_l285 systemDebugger_1._zz_io_mem_cmd_payload_address[49] -1 1 -.names system_cpu.when_DebugPlugin_l288 systemDebugger_1._zz_io_mem_cmd_payload_address[50] -1 1 -.names system_cpu.when_DebugPlugin_l284_1 systemDebugger_1._zz_io_mem_cmd_payload_address[56] -1 1 -.names system_cpu.when_DebugPlugin_l285_1 systemDebugger_1._zz_io_mem_cmd_payload_address[57] -1 1 -.names system_cpu.when_DebugPlugin_l288_1 systemDebugger_1._zz_io_mem_cmd_payload_address[58] -1 1 -.names systemDebugger_1.io_mem_cmd_payload_wr systemDebugger_1._zz_io_mem_cmd_payload_address[64] -1 1 -.names $false system_cpu.BranchPlugin_jumpInterface_payload[0] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[13] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[14] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[15] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[16] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[17] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[18] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[19] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[20] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[21] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[22] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[23] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[24] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[25] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[26] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[27] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[28] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[29] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[30] -1 1 -.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[31] -1 1 -.names $true system_cpu.CsrPlugin_interrupt_code[0] -1 1 -.names $true system_cpu.CsrPlugin_interrupt_code[1] -1 1 -.names $true system_cpu.CsrPlugin_mcause_exceptionCode[0] -1 1 -.names $true system_cpu.CsrPlugin_mcause_exceptionCode[1] -1 1 -.names $false system_cpu.CsrPlugin_mepc[0] -1 1 -.names $false system_cpu.CsrPlugin_mepc[1] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[5] system_cpu.DebugPlugin_busReadDataReg[5] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[6] system_cpu.DebugPlugin_busReadDataReg[6] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[7] system_cpu.DebugPlugin_busReadDataReg[7] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[8] system_cpu.DebugPlugin_busReadDataReg[8] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[9] system_cpu.DebugPlugin_busReadDataReg[9] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[10] system_cpu.DebugPlugin_busReadDataReg[10] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[11] system_cpu.DebugPlugin_busReadDataReg[11] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[12] system_cpu.DebugPlugin_busReadDataReg[12] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[13] system_cpu.DebugPlugin_busReadDataReg[13] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[14] system_cpu.DebugPlugin_busReadDataReg[14] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[15] system_cpu.DebugPlugin_busReadDataReg[15] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[16] system_cpu.DebugPlugin_busReadDataReg[16] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[17] system_cpu.DebugPlugin_busReadDataReg[17] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[18] system_cpu.DebugPlugin_busReadDataReg[18] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[19] system_cpu.DebugPlugin_busReadDataReg[19] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[20] system_cpu.DebugPlugin_busReadDataReg[20] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[21] system_cpu.DebugPlugin_busReadDataReg[21] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[22] system_cpu.DebugPlugin_busReadDataReg[22] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[23] system_cpu.DebugPlugin_busReadDataReg[23] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[24] system_cpu.DebugPlugin_busReadDataReg[24] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[25] system_cpu.DebugPlugin_busReadDataReg[25] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[26] system_cpu.DebugPlugin_busReadDataReg[26] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[27] system_cpu.DebugPlugin_busReadDataReg[27] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[28] system_cpu.DebugPlugin_busReadDataReg[28] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[29] system_cpu.DebugPlugin_busReadDataReg[29] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[30] system_cpu.DebugPlugin_busReadDataReg[30] -1 1 -.names jtagBridge_1.io_remote_rsp_payload_data[31] system_cpu.DebugPlugin_busReadDataReg[31] -1 1 -.names $false system_cpu.IBusSimplePlugin_cmd_payload_pc[0] -1 1 -.names $false system_cpu.IBusSimplePlugin_cmd_payload_pc[1] -1 1 -.names $false system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[0] -1 1 -.names $false system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[1] -1 1 -.names $false system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[0] -1 1 -.names $false system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[1] -1 1 -.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] -1 1 -.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] -1 1 -.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] -1 1 -.names system_cpu._zz_decode_SRC2 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] -1 1 -.names system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[12] -1 1 -.names system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[19] -1 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[4] -1 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[5] -1 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[6] -1 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[7] -1 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[8] -1 1 -.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[9] -1 1 -.names system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[11] -1 1 -.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu._zz_lastStageRegFileWrite_payload_address[7] -1 1 -.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu._zz_lastStageRegFileWrite_payload_address[8] -1 1 -.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu._zz_lastStageRegFileWrite_payload_address[9] -1 1 -.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu._zz_lastStageRegFileWrite_payload_address[10] -1 1 -.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] system_cpu._zz_lastStageRegFileWrite_payload_address[11] -1 1 -.names $undef system_cpu._zz_lastStageRegFileWrite_payload_address[30] -1 1 -.names $undef system_cpu._zz_lastStageRegFileWrite_payload_address[31] -1 1 -.names $false system_cpu.decode_to_execute_PC[0] -1 1 -.names $false system_cpu.decode_to_execute_PC[1] -1 1 -.names system_cpu._zz_dBus_cmd_payload_data[0] system_cpu.decode_to_execute_RS2[0] -1 1 -.names system_cpu._zz_dBus_cmd_payload_data[1] system_cpu.decode_to_execute_RS2[1] -1 1 -.names system_cpu._zz_dBus_cmd_payload_data[2] system_cpu.decode_to_execute_RS2[2] -1 1 -.names system_cpu._zz_dBus_cmd_payload_data[3] system_cpu.decode_to_execute_RS2[3] -1 1 -.names system_cpu._zz_dBus_cmd_payload_data[4] system_cpu.decode_to_execute_RS2[4] -1 1 -.names system_cpu._zz_dBus_cmd_payload_data[5] system_cpu.decode_to_execute_RS2[5] -1 1 -.names system_cpu._zz_dBus_cmd_payload_data[6] system_cpu.decode_to_execute_RS2[6] -1 1 -.names system_cpu._zz_dBus_cmd_payload_data[7] system_cpu.decode_to_execute_RS2[7] -1 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[0] -1 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[1] -1 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[2] -1 1 -.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[3] -1 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[0] -1 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[1] -1 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[2] -1 1 -.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[3] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif deleted file mode 100644 index 07d5fccecba..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif +++ /dev/null @@ -1,574 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model PWM -.inputs clk RxD -.outputs PWM_out -.names $false -.names $true -1 -.names $undef -.names deserializer.RxD_data_ready RxD_data_reg[6] deserializer.RxD_data[6] $abc$1877$auto$rtlil.cc:2693:MuxGate$1591 -010 1 -011 1 -101 1 -111 1 -.names deserializer.RxD_data_ready deserializer.RxD_data[5] RxD_data_reg[5] $abc$1877$auto$rtlil.cc:2693:MuxGate$1593 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_data_ready deserializer.RxD_data[4] RxD_data_reg[4] $abc$1877$auto$rtlil.cc:2693:MuxGate$1595 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_data_ready deserializer.RxD_data[3] RxD_data_reg[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1597 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_data_ready deserializer.RxD_data[2] RxD_data_reg[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1599 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_data_ready deserializer.RxD_data[1] RxD_data_reg[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1601 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_data_ready deserializer.RxD_data[0] RxD_data_reg[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1603 -001 1 -011 1 -110 1 -111 1 -.names deserializer.OversamplingTick deserializer.Filter_cnt[0] deserializer.Filter_cnt[1] deserializer.RxD_sync[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1605 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names $abc$1877$new_n113 deserializer.RxD_data[7] deserializer.RxD_data[6] $abc$1877$auto$rtlil.cc:2693:MuxGate$1607 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_state[3] $abc$1877$new_n114 $abc$1877$new_n113 -11 1 -.names deserializer.OversamplingCnt[1] deserializer.OversamplingCnt[0] deserializer.OversamplingTick deserializer.OversamplingCnt[2] $abc$1877$new_n114 -1110 1 -.names $abc$1877$new_n113 deserializer.RxD_data[6] deserializer.RxD_data[5] $abc$1877$auto$rtlil.cc:2693:MuxGate$1609 -001 1 -011 1 -110 1 -111 1 -.names $abc$1877$new_n113 deserializer.RxD_data[5] deserializer.RxD_data[4] $abc$1877$auto$rtlil.cc:2693:MuxGate$1611 -001 1 -011 1 -110 1 -111 1 -.names $abc$1877$new_n113 deserializer.RxD_data[4] deserializer.RxD_data[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1613 -001 1 -011 1 -110 1 -111 1 -.names $abc$1877$new_n113 deserializer.RxD_data[3] deserializer.RxD_data[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1615 -001 1 -011 1 -110 1 -111 1 -.names $abc$1877$new_n113 deserializer.RxD_data[2] deserializer.RxD_data[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1617 -001 1 -011 1 -110 1 -111 1 -.names $abc$1877$new_n113 deserializer.RxD_data[1] deserializer.RxD_data[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1619 -001 1 -011 1 -110 1 -111 1 -.names deserializer.OversamplingCnt[1] deserializer.OversamplingCnt[0] deserializer.OversamplingTick $abc$1877$new_n122 $abc$1877$auto$rtlil.cc:2693:MuxGate$1623 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -.names $abc$1877$new_n123 deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n122 -100 1 -.names deserializer.RxD_state[3] deserializer.RxD_state[2] $abc$1877$new_n123 -00 1 -.names deserializer.OversamplingTick deserializer.OversamplingCnt[0] $abc$1877$new_n122 $abc$1877$auto$rtlil.cc:2693:MuxGate$1627 -010 1 -011 1 -100 1 -.names deserializer.RxD_state[1] deserializer.RxD_state[3] deserializer.RxD_state[0] $abc$1877$new_n126 deserializer.RxD_state[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1629 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$1877$new_n127 $abc$1877$new_n114 deserializer.RxD_state[3] $abc$1877$new_n126 -100 1 -110 1 -111 1 -.names $abc$1877$new_n123 deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n114 deserializer.RxD_bit $abc$1877$new_n127 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$1877$new_n126 deserializer.RxD_state[0] $abc$1877$new_n122 deserializer.RxD_state[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1631 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names deserializer.OversamplingTick RxD deserializer.RxD_sync[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1633 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_data_ready deserializer.RxD_data[7] RxD_data_reg[7] $abc$1877$auto$rtlil.cc:2693:MuxGate$1635 -001 1 -011 1 -110 1 -111 1 -.names deserializer.OversamplingTick deserializer.RxD_sync[0] deserializer.RxD_sync[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1637 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_bit deserializer.Filter_cnt[1] deserializer.OversamplingTick deserializer.Filter_cnt[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1641 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names deserializer.Filter_cnt[1] deserializer.RxD_sync[1] deserializer.OversamplingTick deserializer.Filter_cnt[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1643 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names deserializer.OversamplingCnt[2] $abc$1877$new_n122 deserializer.OversamplingCnt[0] deserializer.OversamplingCnt[1] deserializer.OversamplingTick $abc$1877$auto$rtlil.cc:2693:MuxGate$1647 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$1877$new_n113 deserializer.RxD_bit deserializer.RxD_data[7] $abc$1877$auto$rtlil.cc:2693:MuxGate$1649 -001 1 -011 1 -110 1 -111 1 -.names deserializer.RxD_state[3] deserializer.RxD_state[2] $abc$1877$new_n137 $abc$1877$new_n114 $abc$1877$auto$rtlil.cc:2693:MuxGate$1653 -1011 1 -1100 1 -1101 1 -1110 1 -.names deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n137 -11 1 -.names $abc$1877$new_n139 deserializer.RxD_state[3] $abc$1877$new_n114 $abc$1877$auto$rtlil.cc:2693:MuxGate$1655 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$1877$new_n127 deserializer.RxD_state[3] deserializer.RxD_state[0] deserializer.RxD_state[2] deserializer.RxD_state[1] $abc$1877$new_n139 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names deserializer.RxD_bit $abc$1877$new_n114 deserializer.RxD_state[1] $abc$1877$new_n123 deserializer.RxD_state[0] $abc$1877$flatten\deserializer.$0\RxD_data_ready[0:0] -11110 1 -.names PWM_accumulator[1] RxD_data_reg[1] PWM_accumulator[0] RxD_data_reg[0] $auto$alumacc.cc:485:replace_alu$579.Y[1] -0011 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1111 1 -.names PWM_accumulator[2] RxD_data_reg[2] $abc$1877$new_n143 $auto$alumacc.cc:485:replace_alu$579.Y[2] -000 1 -011 1 -101 1 -110 1 -.names RxD_data_reg[0] PWM_accumulator[0] PWM_accumulator[1] RxD_data_reg[1] $abc$1877$new_n143 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names PWM_accumulator[3] RxD_data_reg[3] PWM_accumulator[2] RxD_data_reg[2] $abc$1877$new_n143 $auto$alumacc.cc:485:replace_alu$579.Y[3] -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names PWM_accumulator[4] RxD_data_reg[4] $abc$1877$new_n146 $auto$alumacc.cc:485:replace_alu$579.Y[4] -000 1 -011 1 -101 1 -110 1 -.names PWM_accumulator[2] RxD_data_reg[2] PWM_accumulator[3] RxD_data_reg[3] $abc$1877$new_n143 $abc$1877$new_n146 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names PWM_accumulator[5] RxD_data_reg[5] PWM_accumulator[4] RxD_data_reg[4] $abc$1877$new_n146 $auto$alumacc.cc:485:replace_alu$579.Y[5] -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names PWM_accumulator[6] RxD_data_reg[6] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.Y[6] -000 1 -011 1 -101 1 -110 1 -.names PWM_accumulator[4] RxD_data_reg[4] PWM_accumulator[5] RxD_data_reg[5] $abc$1877$new_n146 $abc$1877$new_n149 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names PWM_accumulator[7] RxD_data_reg[7] PWM_accumulator[6] RxD_data_reg[6] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.Y[7] -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names PWM_accumulator[0] RxD_data_reg[0] $auto$alumacc.cc:485:replace_alu$579.X[0] -01 1 -10 1 -.names deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[1] -00 1 -11 1 -.names deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[2] -000 1 -101 1 -110 1 -111 1 -.names deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[3] -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names deserializer.tickgen.Acc[8] deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[4] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[5] -00 1 -11 1 -.names deserializer.tickgen.Acc[8] deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $abc$1877$new_n157 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -.names deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[6] -010 1 -100 1 -101 1 -111 1 -.names deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[7] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -1110 1 -.names deserializer.tickgen.Acc[12] deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[8] -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[9] -01 1 -10 1 -.names deserializer.tickgen.Acc[12] deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $abc$1877$new_n162 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[10] -011 1 -100 1 -101 1 -110 1 -.names deserializer.tickgen.Acc[15] deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[11] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names PWM_accumulator[6] RxD_data_reg[6] PWM_accumulator[7] RxD_data_reg[7] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.CO[7] -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names deserializer.tickgen.Acc[15] deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.CO[11] -1111 1 -.names deserializer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$591.X[0] -0 1 -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1641 Q=deserializer.RxD_bit -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1605 Q=deserializer.Filter_cnt[0] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1643 Q=deserializer.Filter_cnt[1] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1603 Q=RxD_data_reg[0] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1601 Q=RxD_data_reg[1] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1599 Q=RxD_data_reg[2] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1597 Q=RxD_data_reg[3] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1595 Q=RxD_data_reg[4] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1593 Q=RxD_data_reg[5] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1591 Q=RxD_data_reg[6] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1635 Q=RxD_data_reg[7] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.X[0] Q=PWM_accumulator[0] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[1] Q=PWM_accumulator[1] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[2] Q=PWM_accumulator[2] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[3] Q=PWM_accumulator[3] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[4] Q=PWM_accumulator[4] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[5] Q=PWM_accumulator[5] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[6] Q=PWM_accumulator[6] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[7] Q=PWM_accumulator[7] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.CO[7] Q=PWM_out -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1633 Q=deserializer.RxD_sync[0] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1637 Q=deserializer.RxD_sync[1] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1631 Q=deserializer.RxD_state[0] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1629 Q=deserializer.RxD_state[1] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1655 Q=deserializer.RxD_state[3] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1653 Q=deserializer.RxD_state[2] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.X[0] Q=deserializer.tickgen.Acc[4] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[1] Q=deserializer.tickgen.Acc[5] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[2] Q=deserializer.tickgen.Acc[6] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[3] Q=deserializer.tickgen.Acc[7] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[4] Q=deserializer.tickgen.Acc[8] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[5] Q=deserializer.tickgen.Acc[9] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[6] Q=deserializer.tickgen.Acc[10] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[7] Q=deserializer.tickgen.Acc[11] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[8] Q=deserializer.tickgen.Acc[12] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[9] Q=deserializer.tickgen.Acc[13] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[10] Q=deserializer.tickgen.Acc[14] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[11] Q=deserializer.tickgen.Acc[15] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.CO[11] Q=deserializer.OversamplingTick -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1627 Q=deserializer.OversamplingCnt[0] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1623 Q=deserializer.OversamplingCnt[1] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1647 Q=deserializer.OversamplingCnt[2] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1619 Q=deserializer.RxD_data[0] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1617 Q=deserializer.RxD_data[1] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1615 Q=deserializer.RxD_data[2] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1613 Q=deserializer.RxD_data[3] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1611 Q=deserializer.RxD_data[4] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1609 Q=deserializer.RxD_data[5] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1607 Q=deserializer.RxD_data[6] -.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1649 Q=deserializer.RxD_data[7] -.subckt dff C=clk D=$abc$1877$flatten\deserializer.$0\RxD_data_ready[0:0] Q=deserializer.RxD_data_ready -.names deserializer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$591.CO[0] -1 1 -.names $false $auto$alumacc.cc:485:replace_alu$591.CO[12] -1 1 -.names $auto$alumacc.cc:485:replace_alu$591.X[0] $auto$alumacc.cc:485:replace_alu$591.Y[0] -1 1 -.names $auto$alumacc.cc:485:replace_alu$591.CO[11] $auto$alumacc.cc:485:replace_alu$591.Y[12] -1 1 -.names deserializer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$591.X[3] -1 1 -.names deserializer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$591.X[5] -1 1 -.names deserializer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$591.X[6] -1 1 -.names deserializer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$591.X[8] -1 1 -.names deserializer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$591.X[9] -1 1 -.names deserializer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$591.X[10] -1 1 -.names deserializer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$591.X[11] -1 1 -.names $false $auto$alumacc.cc:485:replace_alu$591.X[12] -1 1 -.names PWM_out PWM_accumulator[8] -1 1 -.names deserializer.OversamplingTick deserializer.tickgen.Acc[16] -1 1 -.names $auto$alumacc.cc:485:replace_alu$579.X[0] $auto$alumacc.cc:485:replace_alu$579.Y[0] -1 1 -.names $auto$alumacc.cc:485:replace_alu$579.CO[7] $auto$alumacc.cc:485:replace_alu$579.Y[8] -1 1 -.names $false $auto$alumacc.cc:485:replace_alu$579.X[8] -1 1 -.names $false $auto$alumacc.cc:485:replace_alu$579.CO[8] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif deleted file mode 100644 index dad3d8629d9..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif +++ /dev/null @@ -1,204 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model PushButton_Debouncer -.inputs clk PB -.outputs PB_state PB_down PB_up -.names $false -.names $true -1 -.names $undef -.names $abc$913$new_n43 PB_sync_1 PB_state $abc$913$auto$rtlil.cc:2693:MuxGate$832 -001 1 -011 1 -110 1 -111 1 -.names PB_cnt[15] PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $abc$913$new_n43 -1111 1 -.names PB_cnt[12] PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $abc$913$new_n44 -11111 1 -.names PB_cnt[8] PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $abc$913$new_n45 -11111 1 -.names PB_cnt[4] PB_cnt[1] PB_cnt[0] PB_cnt[3] PB_cnt[2] $abc$913$new_n46 -11111 1 -.names PB_sync_1 PB_state PB_idle -00 1 -11 1 -.names PB_sync_1 $abc$913$new_n43 PB_state PB_down -110 1 -.names $abc$913$new_n43 PB_state PB_sync_1 PB_up -110 1 -.names PB_cnt[1] PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.Y[1] -01 1 -10 1 -.names PB_cnt[2] PB_cnt[1] PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.Y[2] -011 1 -100 1 -101 1 -110 1 -.names PB_cnt[3] PB_cnt[1] PB_cnt[0] PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names PB_cnt[4] PB_cnt[1] PB_cnt[0] PB_cnt[3] PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.Y[4] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[5] -01 1 -10 1 -.names PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[6] -011 1 -100 1 -101 1 -110 1 -.names PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[7] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names PB_cnt[8] PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[8] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[9] -01 1 -10 1 -.names PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[10] -011 1 -100 1 -101 1 -110 1 -.names PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[11] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names PB_cnt[12] PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[12] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[13] -01 1 -10 1 -.names PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[14] -011 1 -100 1 -101 1 -110 1 -.names PB_cnt[15] PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[15] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names PB $0\PB_sync_0[0:0] -0 1 -.names PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.X[0] -0 1 -.subckt dff C=clk D=$abc$913$auto$rtlil.cc:2693:MuxGate$832 Q=PB_state -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.X[0] Q=PB_cnt[0] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[1] Q=PB_cnt[1] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[2] Q=PB_cnt[2] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[3] Q=PB_cnt[3] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[4] Q=PB_cnt[4] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[5] Q=PB_cnt[5] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[6] Q=PB_cnt[6] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[7] Q=PB_cnt[7] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[8] Q=PB_cnt[8] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[9] Q=PB_cnt[9] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[10] Q=PB_cnt[10] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[11] Q=PB_cnt[11] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[12] Q=PB_cnt[12] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[13] Q=PB_cnt[13] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[14] Q=PB_cnt[14] R=PB_idle -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[15] Q=PB_cnt[15] R=PB_idle -.subckt dff C=clk D=PB_sync_0 Q=PB_sync_1 -.subckt dff C=clk D=$0\PB_sync_0[0:0] Q=PB_sync_0 -.names $auto$alumacc.cc:485:replace_alu$424.X[0] $auto$alumacc.cc:485:replace_alu$424.Y[0] -1 1 -.names PB_cnt[1] $auto$alumacc.cc:485:replace_alu$424.X[1] -1 1 -.names PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.X[2] -1 1 -.names PB_cnt[3] $auto$alumacc.cc:485:replace_alu$424.X[3] -1 1 -.names PB_cnt[4] $auto$alumacc.cc:485:replace_alu$424.X[4] -1 1 -.names PB_cnt[5] $auto$alumacc.cc:485:replace_alu$424.X[5] -1 1 -.names PB_cnt[6] $auto$alumacc.cc:485:replace_alu$424.X[6] -1 1 -.names PB_cnt[7] $auto$alumacc.cc:485:replace_alu$424.X[7] -1 1 -.names PB_cnt[8] $auto$alumacc.cc:485:replace_alu$424.X[8] -1 1 -.names PB_cnt[9] $auto$alumacc.cc:485:replace_alu$424.X[9] -1 1 -.names PB_cnt[10] $auto$alumacc.cc:485:replace_alu$424.X[10] -1 1 -.names PB_cnt[11] $auto$alumacc.cc:485:replace_alu$424.X[11] -1 1 -.names PB_cnt[12] $auto$alumacc.cc:485:replace_alu$424.X[12] -1 1 -.names PB_cnt[13] $auto$alumacc.cc:485:replace_alu$424.X[13] -1 1 -.names PB_cnt[14] $auto$alumacc.cc:485:replace_alu$424.X[14] -1 1 -.names PB_cnt[15] $auto$alumacc.cc:485:replace_alu$424.X[15] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif deleted file mode 100644 index 8cf4e1f6f4d..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif +++ /dev/null @@ -1,735 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model RCServo -.inputs clk RxD -.outputs RCServo_pulse -.names $false -.names $true -1 -.names $undef -.names deserialer.RxD_data_ready RxD_data_reg[5] deserialer.RxD_data[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$1953 -010 1 -011 1 -101 1 -111 1 -.names deserialer.RxD_data_ready deserialer.RxD_data[4] RxD_data_reg[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$1955 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_data_ready deserialer.RxD_data[3] RxD_data_reg[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1957 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_data_ready deserialer.RxD_data[2] RxD_data_reg[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1959 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_data_ready deserialer.RxD_data[1] RxD_data_reg[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1961 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_data_ready deserialer.RxD_data[0] RxD_data_reg[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$1963 -001 1 -011 1 -110 1 -111 1 -.names deserialer.OversamplingTick deserialer.Filter_cnt[0] deserialer.Filter_cnt[1] deserialer.RxD_sync[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1965 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names $abc$2311$new_n152 deserialer.RxD_data[7] deserialer.RxD_data[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$1967 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_state[3] $abc$2311$new_n153 $abc$2311$new_n152 -11 1 -.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick deserialer.OversamplingCnt[2] $abc$2311$new_n153 -1110 1 -.names $abc$2311$new_n152 deserialer.RxD_data[6] deserialer.RxD_data[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$1969 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n152 deserialer.RxD_data[5] deserialer.RxD_data[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$1971 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n152 deserialer.RxD_data[4] deserialer.RxD_data[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1973 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n152 deserialer.RxD_data[3] deserialer.RxD_data[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1975 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n152 deserialer.RxD_data[2] deserialer.RxD_data[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1977 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n152 deserialer.RxD_data[1] deserialer.RxD_data[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$1979 -001 1 -011 1 -110 1 -111 1 -.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick $abc$2311$new_n161 $abc$2311$auto$rtlil.cc:2693:MuxGate$1983 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -.names deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$2311$new_n161 -0000 1 -.names deserialer.OversamplingTick deserialer.OversamplingCnt[0] $abc$2311$new_n161 $abc$2311$auto$rtlil.cc:2693:MuxGate$1987 -010 1 -011 1 -100 1 -.names deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$2311$new_n164 deserialer.RxD_state[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1989 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$2311$new_n165 $abc$2311$new_n161 deserialer.RxD_bit $abc$2311$new_n164 -000 1 -001 1 -010 1 -.names $abc$2311$new_n153 deserialer.RxD_state[0] deserialer.RxD_state[1] deserialer.RxD_state[2] deserialer.RxD_state[3] $abc$2311$new_n165 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names $abc$2311$new_n164 deserialer.RxD_state[0] $abc$2311$new_n161 deserialer.RxD_state[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1991 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names PulseCount[10] PulseCount[9] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$1993 -011 1 -100 1 -101 1 -110 1 -.names PulseCount[8] $abc$2311$new_n169 $abc$2311$new_n168 -11 1 -.names PulseCount[4] PulseCount[5] PulseCount[6] PulseCount[7] $abc$2311$new_n170 $abc$2311$new_n169 -11111 1 -.names PulseCount[0] PulseCount[1] PulseCount[2] PulseCount[3] ClkTick $abc$2311$new_n170 -11111 1 -.names PulseCount[9] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$1995 -01 1 -10 1 -.names PulseCount[8] $abc$2311$new_n169 $abc$2311$auto$rtlil.cc:2693:MuxGate$1997 -01 1 -10 1 -.names PulseCount[7] PulseCount[4] PulseCount[5] PulseCount[6] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$1999 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names PulseCount[6] PulseCount[4] PulseCount[5] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2001 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names PulseCount[5] PulseCount[4] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2003 -011 1 -100 1 -101 1 -110 1 -.names PulseCount[4] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2005 -01 1 -10 1 -.names PulseCount[3] PulseCount[0] PulseCount[1] PulseCount[2] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2007 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names PulseCount[2] PulseCount[0] PulseCount[1] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2009 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names PulseCount[1] PulseCount[0] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2011 -011 1 -100 1 -101 1 -110 1 -.names PulseCount[0] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2013 -01 1 -10 1 -.names $abc$2311$new_n182 RxD_data_reg[6] RCServo_position[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$2015 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n183 PulseCount[2] PulseCount[3] PulseCount[4] PulseCount[5] $abc$2311$new_n182 -10000 1 -.names $abc$2311$new_n184 PulseCount[0] PulseCount[1] PulseCount[6] PulseCount[7] $abc$2311$new_n183 -10000 1 -.names PulseCount[11] PulseCount[8] PulseCount[9] PulseCount[10] $abc$2311$new_n184 -0000 1 -.names $abc$2311$new_n182 RxD_data_reg[5] RCServo_position[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$2017 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n182 RxD_data_reg[4] RCServo_position[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$2019 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n182 RxD_data_reg[3] RCServo_position[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$2021 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n182 RxD_data_reg[2] RCServo_position[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$2023 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n182 RxD_data_reg[1] RCServo_position[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2025 -001 1 -011 1 -110 1 -111 1 -.names $abc$2311$new_n182 RxD_data_reg[0] RCServo_position[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2027 -001 1 -011 1 -110 1 -111 1 -.names deserialer.OversamplingTick RxD deserialer.RxD_sync[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2029 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_data_ready deserialer.RxD_data[7] RxD_data_reg[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2031 -001 1 -011 1 -110 1 -111 1 -.names PulseCount[11] PulseCount[9] PulseCount[10] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$2033 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$2311$new_n182 RxD_data_reg[7] RCServo_position[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2035 -001 1 -011 1 -110 1 -111 1 -.names deserialer.OversamplingTick deserialer.RxD_sync[0] deserialer.RxD_sync[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2037 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_bit deserialer.Filter_cnt[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2041 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names deserialer.Filter_cnt[1] deserialer.RxD_sync[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2043 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names deserialer.OversamplingCnt[2] $abc$2311$new_n161 deserialer.OversamplingCnt[0] deserialer.OversamplingCnt[1] deserialer.OversamplingTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2047 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$2311$new_n152 deserialer.RxD_bit deserialer.RxD_data[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2049 -001 1 -011 1 -110 1 -111 1 -.names deserialer.RxD_state[2] deserialer.RxD_state[3] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$2311$new_n164 $abc$2311$auto$rtlil.cc:2693:MuxGate$2053 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$2311$new_n164 deserialer.RxD_state[2] deserialer.RxD_state[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2055 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names deserialer.RxD_data_ready deserialer.RxD_data[6] RxD_data_reg[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$2057 -001 1 -011 1 -110 1 -111 1 -.names ClkCount[5] $abc$2311$new_n204 ClkCount[4] ClkCount[3] $0\ClkTick[0:0] -1100 1 -.names ClkCount[6] ClkCount[2] ClkCount[1] ClkCount[0] $abc$2311$new_n204 -1000 1 -.names $abc$2311$new_n206 $abc$2311$new_n153 $abc$2311$flatten\deserialer.$0\RxD_data_ready[0:0] -11 1 -.names deserialer.RxD_bit deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] $abc$2311$new_n206 -11000 1 -.names PulseCount[2] RCServo_position[2] RCServo_position[3] PulseCount[3] $abc$2311$new_n210 $abc$2311$new_n209 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names PulseCount[0] RCServo_position[0] RCServo_position[1] PulseCount[1] $abc$2311$new_n210 -0001 1 -0101 1 -1000 1 -1001 1 -1011 1 -1101 1 -.names $abc$2311$new_n212 RCServo_position[4] PulseCount[4] RCServo_position[5] PulseCount[5] $abc$2311$new_n211 -10000 1 -10011 1 -11100 1 -11111 1 -.names PulseCount[6] RCServo_position[6] RCServo_position[7] PulseCount[7] $abc$2311$new_n212 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$2311$new_n214 $abc$2311$new_n212 $abc$2311$new_n215 PulseCount[5] RCServo_position[5] $abc$2311$new_n213 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names RCServo_position[6] RCServo_position[7] PulseCount[6] PulseCount[7] $abc$2311$new_n214 -0100 1 -0110 1 -1000 1 -1100 1 -1101 1 -1110 1 -.names RCServo_position[5] PulseCount[5] RCServo_position[4] PulseCount[4] $abc$2311$new_n215 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names RCServo_position[2] PulseCount[2] RCServo_position[3] PulseCount[3] $abc$2311$new_n217 -0000 1 -0011 1 -1100 1 -1111 1 -.names RCServo_position[0] PulseCount[0] RCServo_position[1] PulseCount[1] $abc$2311$new_n218 -0000 1 -0011 1 -1100 1 -1111 1 -.names ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[1] -01 1 -10 1 -.names ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[2] -011 1 -100 1 -101 1 -110 1 -.names ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names ClkCount[4] ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[4] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names ClkCount[5] $abc$2311$new_n224 $auto$alumacc.cc:485:replace_alu$613.Y[5] -01 1 -10 1 -.names ClkCount[4] ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $abc$2311$new_n224 -11111 1 -.names ClkCount[6] ClkCount[5] $abc$2311$new_n224 $auto$alumacc.cc:485:replace_alu$613.Y[6] -011 1 -100 1 -101 1 -110 1 -.names deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.Y[1] -00 1 -11 1 -.names deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.Y[2] -000 1 -101 1 -110 1 -111 1 -.names deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $auto$alumacc.cc:485:replace_alu$628.Y[3] -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $auto$alumacc.cc:485:replace_alu$628.Y[4] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[5] -00 1 -11 1 -.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $abc$2311$new_n231 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -.names deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[6] -010 1 -100 1 -101 1 -111 1 -.names deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[7] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -1110 1 -.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[8] -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[9] -01 1 -10 1 -.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $abc$2311$new_n236 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[10] -011 1 -100 1 -101 1 -110 1 -.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[11] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.CO[11] -1111 1 -.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.X[0] -0 1 -.names ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.X[0] -0 1 -.names $abc$2311$new_n211 $abc$2311$new_n213 $abc$2311$new_n209 $abc$2311$new_n218 $abc$2311$new_n217 $abc$2311$new_n242 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names PulseCount[9] PulseCount[11] PulseCount[10] PulseCount[8] $abc$2311$new_n242 $0\RCServo_pulse[0:0] -00000 1 -00001 1 -00010 1 -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.X[0] Q=deserialer.tickgen.Acc[4] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[1] Q=deserialer.tickgen.Acc[5] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[2] Q=deserialer.tickgen.Acc[6] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[3] Q=deserialer.tickgen.Acc[7] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[4] Q=deserialer.tickgen.Acc[8] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[5] Q=deserialer.tickgen.Acc[9] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[6] Q=deserialer.tickgen.Acc[10] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[7] Q=deserialer.tickgen.Acc[11] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[8] Q=deserialer.tickgen.Acc[12] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[9] Q=deserialer.tickgen.Acc[13] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[10] Q=deserialer.tickgen.Acc[14] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[11] Q=deserialer.tickgen.Acc[15] -.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.CO[11] Q=deserialer.OversamplingTick -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1987 Q=deserialer.OversamplingCnt[0] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1983 Q=deserialer.OversamplingCnt[1] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2047 Q=deserialer.OversamplingCnt[2] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1979 Q=deserialer.RxD_data[0] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1977 Q=deserialer.RxD_data[1] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1975 Q=deserialer.RxD_data[2] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1973 Q=deserialer.RxD_data[3] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1971 Q=deserialer.RxD_data[4] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1969 Q=deserialer.RxD_data[5] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1967 Q=deserialer.RxD_data[6] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2049 Q=deserialer.RxD_data[7] -.subckt dff C=clk D=$abc$2311$flatten\deserialer.$0\RxD_data_ready[0:0] Q=deserialer.RxD_data_ready -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.X[0] Q=ClkCount[0] R=ClkTick -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[1] Q=ClkCount[1] R=ClkTick -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[2] Q=ClkCount[2] R=ClkTick -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[3] Q=ClkCount[3] R=ClkTick -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[4] Q=ClkCount[4] R=ClkTick -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[5] Q=ClkCount[5] R=ClkTick -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[6] Q=ClkCount[6] R=ClkTick -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2041 Q=deserialer.RxD_bit -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1965 Q=deserialer.Filter_cnt[0] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2043 Q=deserialer.Filter_cnt[1] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1963 Q=RxD_data_reg[0] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1961 Q=RxD_data_reg[1] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1959 Q=RxD_data_reg[2] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1957 Q=RxD_data_reg[3] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1955 Q=RxD_data_reg[4] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1953 Q=RxD_data_reg[5] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2057 Q=RxD_data_reg[6] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2031 Q=RxD_data_reg[7] -.subckt dff C=clk D=$0\RCServo_pulse[0:0] Q=RCServo_pulse -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2029 Q=deserialer.RxD_sync[0] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2037 Q=deserialer.RxD_sync[1] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2027 Q=RCServo_position[0] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2025 Q=RCServo_position[1] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2023 Q=RCServo_position[2] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2021 Q=RCServo_position[3] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2019 Q=RCServo_position[4] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2017 Q=RCServo_position[5] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2015 Q=RCServo_position[6] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2035 Q=RCServo_position[7] -.subckt dff C=clk D=$0\ClkTick[0:0] Q=ClkTick -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2013 Q=PulseCount[0] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2011 Q=PulseCount[1] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2009 Q=PulseCount[2] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2007 Q=PulseCount[3] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2005 Q=PulseCount[4] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2003 Q=PulseCount[5] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2001 Q=PulseCount[6] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1999 Q=PulseCount[7] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1997 Q=PulseCount[8] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1995 Q=PulseCount[9] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1993 Q=PulseCount[10] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2033 Q=PulseCount[11] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1991 Q=deserialer.RxD_state[0] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1989 Q=deserialer.RxD_state[1] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2055 Q=deserialer.RxD_state[3] -.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2053 Q=deserialer.RxD_state[2] -.names $auto$alumacc.cc:485:replace_alu$628.X[0] $auto$alumacc.cc:485:replace_alu$628.Y[0] -1 1 -.names $auto$alumacc.cc:485:replace_alu$628.CO[11] $auto$alumacc.cc:485:replace_alu$628.Y[12] -1 1 -.names deserialer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$628.X[3] -1 1 -.names deserialer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$628.X[5] -1 1 -.names deserialer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$628.X[6] -1 1 -.names deserialer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$628.X[8] -1 1 -.names deserialer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$628.X[9] -1 1 -.names deserialer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$628.X[10] -1 1 -.names deserialer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$628.X[11] -1 1 -.names $false $auto$alumacc.cc:485:replace_alu$628.X[12] -1 1 -.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.CO[0] -1 1 -.names $false $auto$alumacc.cc:485:replace_alu$628.CO[12] -1 1 -.names $auto$alumacc.cc:485:replace_alu$613.X[0] $auto$alumacc.cc:485:replace_alu$613.Y[0] -1 1 -.names ClkCount[1] $auto$alumacc.cc:485:replace_alu$613.X[1] -1 1 -.names ClkCount[2] $auto$alumacc.cc:485:replace_alu$613.X[2] -1 1 -.names ClkCount[3] $auto$alumacc.cc:485:replace_alu$613.X[3] -1 1 -.names ClkCount[4] $auto$alumacc.cc:485:replace_alu$613.X[4] -1 1 -.names ClkCount[5] $auto$alumacc.cc:485:replace_alu$613.X[5] -1 1 -.names ClkCount[6] $auto$alumacc.cc:485:replace_alu$613.X[6] -1 1 -.names deserialer.OversamplingTick deserialer.tickgen.Acc[16] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif deleted file mode 100644 index 909b5033223..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif +++ /dev/null @@ -1,53 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model TaskAck_CrossDomain -.inputs clkA TaskStart_clkA clkB TaskDone_clkB -.outputs TaskBusy_clkA TaskDone_clkA TaskStart_clkB TaskBusy_clkB -.names $false -.names $true -1 -.names $undef -.names $abc$605$new_n19 FlagToggle_clkA FlagToggle_clkB $abc$605$auto$rtlil.cc:2693:MuxGate$526 -001 1 -011 1 -110 1 -111 1 -.names TaskDone_clkB SyncA_clkB[2] SyncA_clkB[1] Busyhold_clkB $abc$605$new_n19 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names SyncA_clkB[2] SyncA_clkB[1] TaskStart_clkB -01 1 -10 1 -.names SyncB_clkA[2] SyncB_clkA[1] TaskDone_clkA -01 1 -10 1 -.names SyncB_clkA[2] FlagToggle_clkA TaskBusy_clkA -01 1 -10 1 -.names TaskStart_clkA FlagToggle_clkA SyncB_clkA[2] $0\FlagToggle_clkA[0:0] -010 1 -011 1 -100 1 -110 1 -.names Busyhold_clkB TaskStart_clkB TaskBusy_clkB -01 1 -10 1 -11 1 -.names TaskDone_clkB TaskStart_clkB Busyhold_clkB $0\Busyhold_clkB[0:0] -001 1 -010 1 -011 1 -.subckt dff C=clkB D=$abc$605$auto$rtlil.cc:2693:MuxGate$526 Q=FlagToggle_clkB -.subckt dff C=clkA D=FlagToggle_clkB Q=SyncB_clkA[0] -.subckt dff C=clkA D=SyncB_clkA[0] Q=SyncB_clkA[1] -.subckt dff C=clkA D=SyncB_clkA[1] Q=SyncB_clkA[2] -.subckt dff C=clkB D=$0\Busyhold_clkB[0:0] Q=Busyhold_clkB -.subckt dff C=clkB D=FlagToggle_clkA Q=SyncA_clkB[0] -.subckt dff C=clkB D=SyncA_clkB[0] Q=SyncA_clkB[1] -.subckt dff C=clkB D=SyncA_clkB[1] Q=SyncA_clkB[2] -.subckt dff C=clkA D=$0\FlagToggle_clkA[0:0] Q=FlagToggle_clkA -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif deleted file mode 100644 index d81a68f31e7..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif +++ /dev/null @@ -1,10133 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model VexRiscv -.inputs iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_error iBus_rsp_payload_inst[0] iBus_rsp_payload_inst[1] iBus_rsp_payload_inst[2] iBus_rsp_payload_inst[3] iBus_rsp_payload_inst[4] iBus_rsp_payload_inst[5] iBus_rsp_payload_inst[6] iBus_rsp_payload_inst[7] iBus_rsp_payload_inst[8] iBus_rsp_payload_inst[9] iBus_rsp_payload_inst[10] iBus_rsp_payload_inst[11] iBus_rsp_payload_inst[12] iBus_rsp_payload_inst[13] iBus_rsp_payload_inst[14] iBus_rsp_payload_inst[15] iBus_rsp_payload_inst[16] iBus_rsp_payload_inst[17] iBus_rsp_payload_inst[18] iBus_rsp_payload_inst[19] iBus_rsp_payload_inst[20] iBus_rsp_payload_inst[21] iBus_rsp_payload_inst[22] iBus_rsp_payload_inst[23] iBus_rsp_payload_inst[24] iBus_rsp_payload_inst[25] iBus_rsp_payload_inst[26] iBus_rsp_payload_inst[27] iBus_rsp_payload_inst[28] iBus_rsp_payload_inst[29] iBus_rsp_payload_inst[30] iBus_rsp_payload_inst[31] timerInterrupt externalInterrupt softwareInterrupt dBus_cmd_ready dBus_rsp_ready dBus_rsp_error dBus_rsp_data[0] dBus_rsp_data[1] dBus_rsp_data[2] dBus_rsp_data[3] dBus_rsp_data[4] dBus_rsp_data[5] dBus_rsp_data[6] dBus_rsp_data[7] dBus_rsp_data[8] dBus_rsp_data[9] dBus_rsp_data[10] dBus_rsp_data[11] dBus_rsp_data[12] dBus_rsp_data[13] dBus_rsp_data[14] dBus_rsp_data[15] dBus_rsp_data[16] dBus_rsp_data[17] dBus_rsp_data[18] dBus_rsp_data[19] dBus_rsp_data[20] dBus_rsp_data[21] dBus_rsp_data[22] dBus_rsp_data[23] dBus_rsp_data[24] dBus_rsp_data[25] dBus_rsp_data[26] dBus_rsp_data[27] dBus_rsp_data[28] dBus_rsp_data[29] dBus_rsp_data[30] dBus_rsp_data[31] clk reset -.outputs iBus_cmd_valid iBus_cmd_payload_pc[0] iBus_cmd_payload_pc[1] iBus_cmd_payload_pc[2] iBus_cmd_payload_pc[3] iBus_cmd_payload_pc[4] iBus_cmd_payload_pc[5] iBus_cmd_payload_pc[6] iBus_cmd_payload_pc[7] iBus_cmd_payload_pc[8] iBus_cmd_payload_pc[9] iBus_cmd_payload_pc[10] iBus_cmd_payload_pc[11] iBus_cmd_payload_pc[12] iBus_cmd_payload_pc[13] iBus_cmd_payload_pc[14] iBus_cmd_payload_pc[15] iBus_cmd_payload_pc[16] iBus_cmd_payload_pc[17] iBus_cmd_payload_pc[18] iBus_cmd_payload_pc[19] iBus_cmd_payload_pc[20] iBus_cmd_payload_pc[21] iBus_cmd_payload_pc[22] iBus_cmd_payload_pc[23] iBus_cmd_payload_pc[24] iBus_cmd_payload_pc[25] iBus_cmd_payload_pc[26] iBus_cmd_payload_pc[27] iBus_cmd_payload_pc[28] iBus_cmd_payload_pc[29] iBus_cmd_payload_pc[30] iBus_cmd_payload_pc[31] dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] -.names $false -.names $true -1 -.names $undef -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1273 iBus_cmd_payload_pc[30] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$new_n1255 $abc$8788$new_n1254 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$new_n1256 $abc$8788$new_n1255 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$new_n1257 $abc$8788$new_n1256 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1257 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1258 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1259 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1260 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1261 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$new_n1263 $abc$8788$new_n1262 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$new_n1264 $abc$8788$new_n1263 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$new_n1265 $abc$8788$new_n1264 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$new_n1266 $abc$8788$new_n1265 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$new_n1267 $abc$8788$new_n1266 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$new_n1268 $abc$8788$new_n1267 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$new_n1269 $abc$8788$new_n1268 -111 1 -.names IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$new_n1269 -111 1 -.names $abc$8788$new_n1271 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$8788$new_n1270 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1272 lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1271 -000 1 -001 1 -010 1 -.names CsrPlugin_interrupt_valid CsrPlugin_pipelineLiberator_done $abc$8788$new_n1272 -11 1 -.names BranchPlugin_jumpInterface_payload[30] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[30] $abc$8788$new_n1273 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_writeBack_ENV_CTRL lastStageIsFiring _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] $abc$8788$new_n1274 -1111 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[30] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$6999 -001 1 -011 1 -110 1 -111 1 -.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n2461 $abc$8788$new_n1270 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1276 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names $abc$8788$new_n2464 $abc$8788$new_n1296 $abc$8788$new_n1278 -10 1 -.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] execute_to_memory_INSTRUCTION[7] $abc$8788$new_n1283 -1100 1 -1111 1 -.names $abc$8788$new_n1286 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n1285 -10000 1 -10011 1 -11100 1 -11111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n1286 -00 1 -11 1 -.names $abc$8788$new_n1289 HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1288 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n1290 HazardSimplePlugin_writeBackBuffer_valid HazardSimplePlugin_writeBackBuffer_payload_address[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1289 -1100 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1290 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz_lastStageRegFileWrite_valid lastStageIsFiring HazardSimplePlugin_writeBackWrites_valid -11 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1296 -11 1 -.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n1304 -1100 1 -1111 1 -.names $abc$8788$new_n1317 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1316 $abc$8788$new_n1315 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1316 -10 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1317 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE dBus_rsp_ready execute_to_memory_MEMORY_STORE $abc$8788$new_n1321 -1100 1 -.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$8788$new_n1322 -11 1 -.names execute_arbitration_isValid $abc$8788$new_n1324 _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1323 -1001 1 -1010 1 -1011 1 -.names decode_to_execute_SRC2[0] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1324 -00000 1 -.names $abc$8788$new_n1327 $abc$8788$new_n1326 $abc$8788$new_n1325 -11 1 -.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] $abc$8788$new_n1326 -00000 1 -00100 1 -01000 1 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[4] execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1327 -00000 1 -00100 1 -01000 1 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names $abc$8788$new_n1329 _zz_memory_ENV_CTRL memory_arbitration_isValid lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1328 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid execute_arbitration_isValid _zz_execute_ENV_CTRL $abc$8788$new_n1329 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n1330 -00001 1 -00010 1 -00011 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1332 iBus_cmd_payload_pc[29] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[29] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[29] $abc$8788$new_n1332 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[29] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7001 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1335 iBus_cmd_payload_pc[28] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[28] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[28] $abc$8788$new_n1335 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[28] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7003 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1338 iBus_cmd_payload_pc[27] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[27] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[27] $abc$8788$new_n1338 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[27] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7005 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1341 iBus_cmd_payload_pc[26] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[26] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[26] $abc$8788$new_n1341 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[26] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7007 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1344 iBus_cmd_payload_pc[25] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[25] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[25] $abc$8788$new_n1344 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[25] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7009 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1347 iBus_cmd_payload_pc[24] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[24] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[24] $abc$8788$new_n1347 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[24] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7011 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1350 iBus_cmd_payload_pc[23] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[23] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[23] $abc$8788$new_n1350 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[23] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7013 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1353 iBus_cmd_payload_pc[22] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[22] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[22] $abc$8788$new_n1353 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[22] IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7015 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1356 iBus_cmd_payload_pc[21] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[21] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[21] $abc$8788$new_n1356 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[21] IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7017 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1359 iBus_cmd_payload_pc[20] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[20] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[20] $abc$8788$new_n1359 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[20] IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7019 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1362 iBus_cmd_payload_pc[19] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[19] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[19] $abc$8788$new_n1362 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[19] IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7021 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1365 iBus_cmd_payload_pc[18] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[18] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[18] $abc$8788$new_n1365 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[18] IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7023 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1368 iBus_cmd_payload_pc[17] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[17] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[17] $abc$8788$new_n1368 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[17] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7025 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1371 iBus_cmd_payload_pc[16] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[16] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[16] $abc$8788$new_n1371 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[16] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7027 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1374 iBus_cmd_payload_pc[15] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[15] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[15] $abc$8788$new_n1374 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[15] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7029 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1377 iBus_cmd_payload_pc[14] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[14] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[14] $abc$8788$new_n1377 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[14] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7031 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1380 iBus_cmd_payload_pc[13] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[13] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[13] $abc$8788$new_n1380 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[13] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7033 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1383 iBus_cmd_payload_pc[12] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[12] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[12] $abc$8788$new_n1383 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[12] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7035 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1386 iBus_cmd_payload_pc[11] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[11] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[11] $abc$8788$new_n1386 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[11] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7037 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1389 iBus_cmd_payload_pc[10] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[10] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[10] $abc$8788$new_n1389 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[10] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7039 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1392 iBus_cmd_payload_pc[9] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[9] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[9] $abc$8788$new_n1392 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[9] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7041 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1395 iBus_cmd_payload_pc[8] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[8] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[8] $abc$8788$new_n1395 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[8] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7043 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1398 iBus_cmd_payload_pc[7] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[7] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[7] $abc$8788$new_n1398 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[7] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7045 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1401 iBus_cmd_payload_pc[6] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[6] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[6] $abc$8788$new_n1401 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[6] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7047 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1404 iBus_cmd_payload_pc[5] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$8788$new_n1271 BranchPlugin_jumpInterface_payload[5] $abc$8788$new_n1274 CsrPlugin_mepc[5] $abc$8788$new_n1404 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[5] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7049 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1407 iBus_cmd_payload_pc[4] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[4] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[4] $abc$8788$new_n1407 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[4] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7051 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1410 iBus_cmd_payload_pc[3] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[3] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[3] $abc$8788$new_n1410 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[3] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7053 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1413 iBus_cmd_payload_pc[2] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[2] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[2] $abc$8788$new_n1413 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[2] IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7055 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[30] CsrPlugin_mepc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7439 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[29] CsrPlugin_mepc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7441 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[28] CsrPlugin_mepc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7443 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[27] CsrPlugin_mepc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7445 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[26] CsrPlugin_mepc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7447 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[25] CsrPlugin_mepc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7449 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[24] CsrPlugin_mepc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7451 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[23] CsrPlugin_mepc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7453 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[22] CsrPlugin_mepc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7455 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[21] CsrPlugin_mepc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7457 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[20] CsrPlugin_mepc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7459 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[19] CsrPlugin_mepc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7461 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[18] CsrPlugin_mepc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7463 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[17] CsrPlugin_mepc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7465 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[16] CsrPlugin_mepc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7467 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[15] CsrPlugin_mepc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7469 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[14] CsrPlugin_mepc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7471 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[13] CsrPlugin_mepc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7473 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[12] CsrPlugin_mepc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7475 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[11] CsrPlugin_mepc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7477 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[10] CsrPlugin_mepc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7479 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[9] CsrPlugin_mepc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7481 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[8] CsrPlugin_mepc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7483 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[7] CsrPlugin_mepc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7485 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[6] CsrPlugin_mepc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7487 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[5] CsrPlugin_mepc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7489 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[4] CsrPlugin_mepc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7491 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[3] CsrPlugin_mepc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7493 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[2] CsrPlugin_mepc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7495 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1446 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7497 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1321 $abc$8788$new_n1445 -10 1 -.names $abc$8788$new_n1447 $abc$8788$new_n1326 $abc$8788$new_n1446 -11 1 -.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[0] decode_to_execute_SRC2[0] $abc$8788$new_n1447 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1449 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7499 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$new_n1449 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7501 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_amplitudeReg[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7503 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7741 -001 1 -011 1 -110 1 -111 1 -.names IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n1454 $abc$8788$new_n1453 -11 1 -.names $abc$8788$new_n1455 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n1454 -1000 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n2461 $abc$8788$new_n1455 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7743 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7745 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7747 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7749 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] iBus_rsp_payload_inst[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7751 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7753 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7755 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7757 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7759 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7761 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7763 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7765 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7767 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7769 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7771 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] iBus_rsp_payload_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7773 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7775 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7777 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7779 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7781 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7783 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] iBus_rsp_payload_inst[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7785 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] iBus_rsp_payload_inst[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7787 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7789 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7791 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7793 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7795 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7797 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[2] CsrPlugin_mcause_exceptionCode[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7861 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 $abc$8788$new_n1445 $abc$8788$new_n1325 execute_LightShifterPlugin_isActive $abc$8788$auto$rtlil.cc:2693:MuxGate$7863 -1001 1 -1011 1 -1100 1 -1101 1 -.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid CsrPlugin_pipelineLiberator_pcValids_1 $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7865 -1111 1 -.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n1488 $abc$8788$auto$rtlil.cc:2693:MuxGate$7867 -1110 1 -.names $abc$8788$new_n1321 CsrPlugin_pipelineLiberator_pcValids_1 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$new_n1488 -000 1 -010 1 -100 1 -101 1 -.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n2458 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$auto$rtlil.cc:2693:MuxGate$7869 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1491 $abc$8788$new_n1492 CsrPlugin_mie_MSIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7871 -001 1 -011 1 -110 1 -111 1 -.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_772 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n1491 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[3] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1493 $abc$8788$new_n1492 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$8788$new_n1494 execute_CsrPlugin_csr_772 CsrPlugin_mie_MSIE execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MIE $abc$8788$new_n1493 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[3] CsrPlugin_mip_MSIP execute_CsrPlugin_csr_836 $abc$8788$new_n1494 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1491 $abc$8788$new_n1496 CsrPlugin_mie_MTIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7873 -001 1 -011 1 -110 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[7] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1497 $abc$8788$new_n1496 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$8788$new_n1498 execute_CsrPlugin_csr_836 CsrPlugin_mip_MTIP $abc$8788$new_n1497 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MTIE CsrPlugin_mstatus_MPIE execute_CsrPlugin_csr_768 $abc$8788$new_n1498 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1491 $abc$8788$new_n1500 CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7875 -001 1 -011 1 -110 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[11] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1501 $abc$8788$new_n1500 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$8788$new_n1502 execute_CsrPlugin_csr_836 CsrPlugin_mip_MEIP $abc$8788$new_n1501 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MEIE CsrPlugin_mstatus_MPP[0] execute_CsrPlugin_csr_768 $abc$8788$new_n1502 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_injector_decodeInput_valid IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7877 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1270 $abc$8788$new_n1505 $abc$8788$new_n2461 $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7879 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names iBus_cmd_ready iBus_cmd_valid $abc$8788$new_n1505 -11 1 -.names $abc$8788$new_n1507 $abc$8788$new_n2461 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid iBus_cmd_valid -1100 1 -1110 1 -1111 1 -.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n1271 IBusSimplePlugin_pending_value[2] IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[0] $abc$8788$new_n1507 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$8788$new_n1509 $abc$8788$new_n1505 $abc$8788$auto$rtlil.cc:2693:MuxGate$7881 -01 1 -10 1 -11 1 -.names IBusSimplePlugin_fetchPc_inc $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$new_n1509 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -.names $abc$8788$new_n1271 $abc$8788$new_n1321 $abc$8788$new_n2458 execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7883 -00111 1 -01111 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2461 execute_arbitration_isValid $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7885 -10010 1 -10110 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_LightShifterPlugin_isActive $abc$8788$new_n1513 execute_LightShifterPlugin_amplitudeReg[4] $abc$8788$new_n1445 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7949 -00100 1 -00101 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1445 execute_LightShifterPlugin_isActive $abc$8788$new_n1446 execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$new_n1513 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1516 $abc$8788$new_n1517 CsrPlugin_interrupt_code[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7953 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_mstatus_MIE $abc$8788$new_n1517 CsrPlugin_mip_MTIP CsrPlugin_mie_MTIE $abc$8788$new_n1516 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names CsrPlugin_mip_MSIP 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$abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1593 execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n1591 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1592 -10 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[29] _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1593 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1594 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11010 1 -11100 1 -11111 1 -.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$8788$new_n1595 -10 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1598 dBus_cmd_payload_address[29] $abc$8788$new_n1601 $abc$8788$auto$rtlil.cc:2693:MuxGate$7059 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[29] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[29] $abc$8788$new_n1323 $abc$8788$new_n1599 $abc$8788$new_n1598 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1600 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n1599 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[28] _zz_execute_SrcPlugin_addSub_2[28] $abc$8788$new_n1600 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1601 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1605 dBus_cmd_payload_address[28] $abc$8788$new_n1608 $abc$8788$auto$rtlil.cc:2693:MuxGate$7061 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1604 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[28] -00000 1 -00110 1 -01010 1 -01100 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1604 -0000 1 -0001 1 -0011 1 -0101 1 -1001 1 -1101 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[28] $abc$8788$new_n1323 $abc$8788$new_n1606 $abc$8788$new_n1605 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 $abc$8788$new_n1607 $abc$8788$new_n1593 $abc$8788$new_n1606 -001 1 -011 1 -110 1 -111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[27] _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1607 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1608 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1611 dBus_cmd_payload_address[27] $abc$8788$new_n1614 $abc$8788$auto$rtlil.cc:2693:MuxGate$7063 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1583 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1532 dBus_cmd_payload_address[27] -00000 1 -01001 1 -01100 1 -01101 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[27] $abc$8788$new_n1323 $abc$8788$new_n1612 $abc$8788$new_n1611 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 $abc$8788$new_n1613 $abc$8788$new_n1600 $abc$8788$new_n1612 -001 1 -011 1 -110 1 -111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[26] _zz_execute_SrcPlugin_addSub_2[26] $abc$8788$new_n1613 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1614 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1618 dBus_cmd_payload_address[26] $abc$8788$new_n1620 $abc$8788$auto$rtlil.cc:2693:MuxGate$7065 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1617 _zz_execute_SrcPlugin_addSub_2[26] dBus_cmd_payload_address[26] -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1578 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 $abc$8788$new_n1533 $abc$8788$new_n1617 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[26] $abc$8788$new_n1323 $abc$8788$new_n1619 $abc$8788$new_n1618 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1607 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1619 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1620 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1622 execute_to_memory_REGFILE_WRITE_DATA[25] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7067 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1624 $abc$8788$new_n1626 $abc$8788$new_n1586 dBus_cmd_payload_address[25] $abc$8788$new_n1595 $abc$8788$new_n1622 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1533 dBus_cmd_payload_address[25] -00000 1 -01001 1 -01100 1 -01101 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1625 $abc$8788$new_n1613 $abc$8788$new_n1624 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[24] _zz_execute_SrcPlugin_addSub_2[24] $abc$8788$new_n1625 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1626 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1631 dBus_cmd_payload_address[24] $abc$8788$new_n1634 $abc$8788$auto$rtlil.cc:2693:MuxGate$7069 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1629 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[24] -00010 1 -00100 1 -01000 1 -01110 1 -10000 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 $abc$8788$new_n1629 -000 1 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1577 $abc$8788$new_n1534 $abc$8788$new_n1630 -00 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[24] $abc$8788$new_n1323 $abc$8788$new_n1632 $abc$8788$new_n1631 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1633 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1632 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[23] _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1633 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1634 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1636 execute_to_memory_REGFILE_WRITE_DATA[23] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7071 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1638 $abc$8788$new_n1640 $abc$8788$new_n1586 dBus_cmd_payload_address[23] $abc$8788$new_n1595 $abc$8788$new_n1636 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[23] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1639 $abc$8788$new_n1625 $abc$8788$new_n1638 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[22] _zz_execute_SrcPlugin_addSub_2[22] $abc$8788$new_n1639 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1640 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1642 execute_to_memory_REGFILE_WRITE_DATA[22] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7073 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1646 $abc$8788$new_n1648 $abc$8788$new_n1586 dBus_cmd_payload_address[22] $abc$8788$new_n1595 $abc$8788$new_n1642 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1644 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[22] -00010 1 -00100 1 -01000 1 -01110 1 -10000 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 $abc$8788$new_n1644 -000 1 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1574 $abc$8788$new_n1535 $abc$8788$new_n1645 -00 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1647 $abc$8788$new_n1633 $abc$8788$new_n1646 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[21] _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1647 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1648 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1653 $abc$8788$new_n1650 $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7075 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 dBus_cmd_payload_address[21] $abc$8788$new_n1652 $abc$8788$new_n1650 -1010 1 -1011 1 -1101 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[21] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1652 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1654 $abc$8788$new_n1639 $abc$8788$new_n1653 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[20] _zz_execute_SrcPlugin_addSub_2[20] $abc$8788$new_n1654 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1656 execute_to_memory_REGFILE_WRITE_DATA[20] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7077 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1660 $abc$8788$new_n1662 $abc$8788$new_n1586 dBus_cmd_payload_address[20] $abc$8788$new_n1595 $abc$8788$new_n1656 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1658 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[20] -00010 1 -00100 1 -01000 1 -01110 1 -10000 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 $abc$8788$new_n1658 -000 1 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1569 $abc$8788$new_n1536 $abc$8788$new_n1659 -00 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1661 $abc$8788$new_n1647 $abc$8788$new_n1660 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[19] _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1661 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1662 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1664 execute_to_memory_REGFILE_WRITE_DATA[19] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7079 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1666 $abc$8788$new_n1586 $abc$8788$new_n1668 $abc$8788$new_n1595 dBus_cmd_payload_address[19] $abc$8788$new_n1664 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[19] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1667 $abc$8788$new_n1654 $abc$8788$new_n1666 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[18] _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1667 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1668 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11010 1 -11100 1 -11111 1 -.names $abc$8788$new_n1670 execute_to_memory_REGFILE_WRITE_DATA[18] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7081 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1673 $abc$8788$new_n1675 $abc$8788$new_n1586 dBus_cmd_payload_address[18] $abc$8788$new_n1595 $abc$8788$new_n1670 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1672 _zz_execute_SrcPlugin_addSub_2[18] dBus_cmd_payload_address[18] -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1565 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 $abc$8788$new_n1537 $abc$8788$new_n1672 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1674 $abc$8788$new_n1661 $abc$8788$new_n1673 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[17] _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1674 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1675 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1678 dBus_cmd_payload_address[17] $abc$8788$new_n1680 $abc$8788$auto$rtlil.cc:2693:MuxGate$7083 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1537 dBus_cmd_payload_address[17] -00000 1 -01001 1 -01100 1 -01101 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[17] $abc$8788$new_n1323 $abc$8788$new_n1679 $abc$8788$new_n1678 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1667 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1679 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1680 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1682 execute_to_memory_REGFILE_WRITE_DATA[16] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7085 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1686 $abc$8788$new_n1688 $abc$8788$new_n1586 dBus_cmd_payload_address[16] $abc$8788$new_n1595 $abc$8788$new_n1682 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1684 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[16] -00010 1 -00100 1 -01000 1 -01110 1 -10000 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 $abc$8788$new_n1684 -000 1 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1564 $abc$8788$new_n1538 $abc$8788$new_n1685 -00 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1687 $abc$8788$new_n1674 $abc$8788$new_n1686 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[15] _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1687 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1688 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1691 dBus_cmd_payload_address[15] $abc$8788$new_n1694 $abc$8788$auto$rtlil.cc:2693:MuxGate$7087 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 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-.names _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1694 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1696 execute_to_memory_REGFILE_WRITE_DATA[14] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7089 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1700 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[14] $abc$8788$new_n1702 $abc$8788$new_n1696 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1698 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[14] -00000 1 -00110 1 -01010 1 -01100 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1557 $abc$8788$new_n1699 $abc$8788$new_n1560 $abc$8788$new_n1698 -000 1 -001 1 -010 1 -.names $abc$8788$new_n1561 $abc$8788$new_n1539 $abc$8788$new_n1699 -10 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1701 $abc$8788$new_n1687 $abc$8788$new_n1700 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1701 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1702 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1704 execute_to_memory_REGFILE_WRITE_DATA[13] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7091 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1706 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[13] $abc$8788$new_n1708 $abc$8788$new_n1704 -00000 1 -00001 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_zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1714 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[11] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1715 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1717 execute_to_memory_REGFILE_WRITE_DATA[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7095 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1722 $abc$8788$new_n1718 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1501 $abc$8788$new_n1717 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[11] $abc$8788$new_n1721 $abc$8788$new_n1718 -1010 1 -1011 1 -1101 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 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$abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[10] $abc$8788$new_n1729 $abc$8788$new_n1725 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1556 $abc$8788$new_n1540 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[10] -0000 1 -0110 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1728 $abc$8788$new_n1715 $abc$8788$new_n1727 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[9] _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1728 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1729 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1321 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_zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1740 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1742 $abc$8788$new_n1728 $abc$8788$new_n1741 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[7] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1742 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1744 execute_to_memory_REGFILE_WRITE_DATA[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7103 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1749 $abc$8788$new_n1745 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1497 $abc$8788$new_n1744 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1748 dBus_cmd_payload_address[7] $abc$8788$new_n1595 $abc$8788$new_n1745 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1747 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[7] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1542 $abc$8788$new_n1747 -001 1 -100 1 -101 1 -111 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1748 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1750 $abc$8788$new_n1736 $abc$8788$new_n1749 -1001 1 -1011 1 -1110 1 -1111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[6] _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1750 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1752 execute_to_memory_REGFILE_WRITE_DATA[6] $abc$8788$new_n1323 $abc$8788$new_n1755 $abc$8788$auto$rtlil.cc:2693:MuxGate$7105 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1754 dBus_cmd_payload_address[6] $abc$8788$new_n1595 $abc$8788$new_n1752 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1551 $abc$8788$new_n1542 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[6] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1754 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1742 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1755 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1757 execute_to_memory_REGFILE_WRITE_DATA[5] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7107 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1760 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[5] $abc$8788$new_n1762 $abc$8788$new_n1757 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1759 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[5] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1548 $abc$8788$new_n1543 $abc$8788$new_n1549 $abc$8788$new_n1759 -000 1 -010 1 -011 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1761 $abc$8788$new_n1750 $abc$8788$new_n1760 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[4] _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n1761 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1762 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1764 execute_to_memory_REGFILE_WRITE_DATA[4] $abc$8788$new_n1323 $abc$8788$new_n1767 $abc$8788$auto$rtlil.cc:2693:MuxGate$7109 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1766 dBus_cmd_payload_address[4] $abc$8788$new_n1595 $abc$8788$new_n1764 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1543 $abc$8788$new_n1549 _zz_execute_SrcPlugin_addSub_2[4] dBus_cmd_payload_address[4] -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1766 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1768 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1767 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[3] _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1768 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1770 execute_to_memory_REGFILE_WRITE_DATA[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7111 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1775 $abc$8788$new_n1771 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1493 $abc$8788$new_n1770 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[3] $abc$8788$new_n1774 $abc$8788$new_n1771 -1010 1 -1011 1 -1101 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1544 $abc$8788$new_n1773 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[3] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1773 -001 1 -100 1 -101 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1774 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1776 $abc$8788$new_n1761 $abc$8788$new_n1775 -1001 1 -1011 1 -1110 1 -1111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[2] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1776 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[2] $abc$8788$new_n1783 $abc$8788$new_n1781 $abc$8788$new_n1778 $abc$8788$auto$rtlil.cc:2693:MuxGate$7113 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1595 $abc$8788$new_n1323 dBus_cmd_payload_address[2] $abc$8788$new_n1780 $abc$8788$new_n1778 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1546 $abc$8788$new_n1545 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[2] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1780 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1782 $abc$8788$new_n1768 $abc$8788$new_n1781 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[1] _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n1782 -000 1 -010 1 -100 1 -101 1 -.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$8788$new_n1322 $abc$8788$new_n1323 $abc$8788$new_n1783 -1110 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1785 execute_to_memory_REGFILE_WRITE_DATA[1] $abc$8788$new_n1323 $abc$8788$new_n1790 $abc$8788$auto$rtlil.cc:2693:MuxGate$7115 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[1] $abc$8788$new_n1789 $abc$8788$new_n1785 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1322 execute_CsrPlugin_csr_834 $abc$8788$new_n1786 -000 1 -001 1 -010 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1788 _zz_execute_SrcPlugin_addSub_2[1] dBus_cmd_payload_address[1] -010 1 -011 1 -101 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] $abc$8788$new_n1788 -00011 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11011 1 -11101 1 -.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1789 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1776 execute_to_memory_REGFILE_WRITE_DATA[0] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1790 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$8788$new_n1803 $abc$8788$new_n1322 $abc$8788$new_n1587 $abc$8788$new_n1792 execute_CsrPlugin_csr_834 $abc$8788$auto$rtlil.cc:2693:MuxGate$7117 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$8788$new_n1589 $abc$8788$new_n1799 $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n1792 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1796 $abc$8788$new_n1798 $abc$8788$new_n1794 _zz_execute_SrcPlugin_addSub_2[31] dBus_cmd_payload_address[31] -00000 1 -00001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$8788$new_n1531 $abc$8788$new_n1584 _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1795 $abc$8788$new_n1794 -00101 1 -01001 1 -01101 1 -01111 1 -10001 1 -10101 1 -10111 1 -11001 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n1795 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 $abc$8788$new_n1797 $abc$8788$new_n1796 -01 1 -10 1 -.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] $abc$8788$new_n1797 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1798 -101 1 -110 1 -.names $abc$8788$new_n1595 $abc$8788$new_n1800 dBus_cmd_payload_address[0] $abc$8788$new_n1799 -000 1 -010 1 -110 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1800 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -1010 1 -1100 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[0] -010 1 -100 1 -101 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC_LESS_UNSIGNED decode_to_execute_SRC2[31] $abc$8788$new_n1802 -000 1 -010 1 -011 1 -100 1 -101 1 -111 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1323 execute_to_memory_REGFILE_WRITE_DATA[0] $abc$8788$new_n1782 $abc$8788$new_n1592 $abc$8788$new_n1803 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01100 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 execute_to_memory_MEMORY_ADDRESS_LOW[0] dBus_cmd_payload_address[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7119 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1806 decode_to_execute_SRC2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7121 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] _zz_decode_SRC2 $abc$8788$new_n1806 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n1807 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1809 decode_to_execute_SRC2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7123 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] _zz_decode_SRC2 $abc$8788$new_n1809 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1811 decode_to_execute_SRC2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7125 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] _zz_decode_SRC2 $abc$8788$new_n1811 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1813 decode_to_execute_SRC2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7127 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] _zz_decode_SRC2 $abc$8788$new_n1813 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1815 decode_to_execute_SRC2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7129 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] _zz_decode_SRC2 $abc$8788$new_n1815 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1817 decode_to_execute_SRC2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7131 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] _zz_decode_SRC2 $abc$8788$new_n1817 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1819 decode_to_execute_SRC2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7133 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] _zz_decode_SRC2 $abc$8788$new_n1819 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1821 decode_to_execute_SRC2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7135 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] _zz_decode_SRC2 $abc$8788$new_n1821 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1823 decode_to_execute_SRC2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7137 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] _zz_decode_SRC2 $abc$8788$new_n1823 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1825 decode_to_execute_SRC2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7139 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] _zz_decode_SRC2 $abc$8788$new_n1825 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1827 decode_to_execute_SRC2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7141 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] _zz_decode_SRC2 $abc$8788$new_n1827 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1829 decode_to_execute_SRC2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7143 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] _zz_decode_SRC2 $abc$8788$new_n1829 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1831 decode_to_execute_SRC2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7145 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] _zz_decode_SRC2 $abc$8788$new_n1831 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1833 decode_to_execute_SRC2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7147 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] _zz_decode_SRC2 $abc$8788$new_n1833 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1835 decode_to_execute_SRC2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7149 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] _zz_decode_SRC2 $abc$8788$new_n1835 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1837 decode_to_execute_SRC2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7151 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] _zz_decode_SRC2 $abc$8788$new_n1837 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1839 decode_to_execute_SRC2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7153 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] _zz_decode_SRC2 $abc$8788$new_n1839 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1841 decode_to_execute_SRC2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7155 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] _zz_decode_SRC2 $abc$8788$new_n1841 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1843 decode_to_execute_SRC2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7157 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] _zz_decode_SRC2 $abc$8788$new_n1843 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1845 decode_to_execute_SRC2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7159 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] _zz_decode_SRC2 $abc$8788$new_n1845 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1847 decode_to_execute_SRC2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7161 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n1847 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1849 decode_to_execute_SRC2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7163 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$8788$new_n1849 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1851 decode_to_execute_SRC2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7165 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$8788$new_n1851 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1853 decode_to_execute_SRC2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7167 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n1853 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1855 decode_to_execute_SRC2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7169 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n1855 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1857 decode_to_execute_SRC2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7171 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$8788$new_n1857 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1859 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7173 -001 1 -011 1 -100 1 -101 1 -.names $abc$8788$new_n1860 _zz_RegFilePlugin_regFile_port1[4] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[4] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1859 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1860 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1861 -1000 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 $abc$8788$new_n1862 -00 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1864 decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7175 -001 1 -011 1 -100 1 -101 1 -.names $abc$8788$new_n1865 _zz_RegFilePlugin_regFile_port1[3] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[3] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1864 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1865 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1867 decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7177 -001 1 -011 1 -100 1 -101 1 -.names $abc$8788$new_n1868 _zz_RegFilePlugin_regFile_port1[2] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[2] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1867 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n1868 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1870 decode_to_execute_SRC2[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7179 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[1] $abc$8788$new_n1870 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1872 decode_to_execute_SRC2[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7181 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[0] $abc$8788$new_n1872 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[30] decode_to_execute_RS2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7183 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[29] decode_to_execute_RS2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7185 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[28] decode_to_execute_RS2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7187 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[27] decode_to_execute_RS2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7189 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[26] decode_to_execute_RS2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7191 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[25] decode_to_execute_RS2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7193 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[24] decode_to_execute_RS2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7195 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[23] decode_to_execute_RS2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7197 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[22] decode_to_execute_RS2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7199 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[21] decode_to_execute_RS2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7201 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[20] decode_to_execute_RS2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7203 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[19] decode_to_execute_RS2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7205 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[18] decode_to_execute_RS2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7207 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[17] decode_to_execute_RS2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7209 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[16] decode_to_execute_RS2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7211 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[15] decode_to_execute_RS2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7213 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[14] decode_to_execute_RS2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7215 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[13] decode_to_execute_RS2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7217 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[12] decode_to_execute_RS2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7219 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[11] decode_to_execute_RS2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7221 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[10] decode_to_execute_RS2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7223 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[9] decode_to_execute_RS2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7225 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[8] decode_to_execute_RS2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7227 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[7] dBus_cmd_payload_data[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7229 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[6] dBus_cmd_payload_data[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7231 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[5] dBus_cmd_payload_data[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7233 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[4] dBus_cmd_payload_data[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7235 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[3] dBus_cmd_payload_data[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7237 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[2] dBus_cmd_payload_data[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7239 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[1] dBus_cmd_payload_data[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7241 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[0] dBus_cmd_payload_data[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7243 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[30] decode_to_execute_RS1[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7245 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[29] decode_to_execute_RS1[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7247 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[28] decode_to_execute_RS1[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7249 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[27] decode_to_execute_RS1[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7251 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[26] decode_to_execute_RS1[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7253 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[25] decode_to_execute_RS1[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7255 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[24] decode_to_execute_RS1[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7257 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[23] decode_to_execute_RS1[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7259 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[22] decode_to_execute_RS1[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7261 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[21] decode_to_execute_RS1[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7263 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[20] decode_to_execute_RS1[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7265 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[19] decode_to_execute_RS1[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7267 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[18] decode_to_execute_RS1[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7269 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[17] decode_to_execute_RS1[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7271 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[16] decode_to_execute_RS1[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7273 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[15] decode_to_execute_RS1[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7275 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[14] decode_to_execute_RS1[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7277 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[13] decode_to_execute_RS1[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7279 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[12] decode_to_execute_RS1[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7281 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[11] decode_to_execute_RS1[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7283 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[10] decode_to_execute_RS1[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7285 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[9] decode_to_execute_RS1[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7287 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[8] decode_to_execute_RS1[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7289 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[7] decode_to_execute_RS1[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7291 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[6] decode_to_execute_RS1[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7293 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[5] decode_to_execute_RS1[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7295 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[4] decode_to_execute_RS1[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7297 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[3] decode_to_execute_RS1[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7299 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[2] decode_to_execute_RS1[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7301 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[1] decode_to_execute_RS1[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7303 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[0] decode_to_execute_RS1[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7305 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_execute_BRANCH_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7307 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1937 _zz_execute_SHIFT_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7309 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n1937 -11000 1 -.names $abc$8788$new_n2458 _zz_execute_ALU_BITWISE_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7311 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7313 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7317 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7319 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7347 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7349 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[12] dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7351 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7353 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7355 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7357 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7359 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7361 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7377 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7379 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7381 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7383 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7385 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7387 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] _zz__zz_execute_BranchPlugin_branch_src2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7389 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7391 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7393 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7395 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7397 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7399 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7401 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7403 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7405 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7407 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7409 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7411 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7413 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7415 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7417 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7419 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7421 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7423 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7505 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7507 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7509 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7511 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7513 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7515 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7517 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7519 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7521 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7523 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7525 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7527 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7529 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7531 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7533 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7535 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7537 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7539 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7541 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[11] 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$abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[11] decode_to_execute_PC[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7841 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[10] decode_to_execute_PC[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7843 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[9] decode_to_execute_PC[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7845 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[8] decode_to_execute_PC[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7847 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[7] decode_to_execute_PC[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7849 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[6] decode_to_execute_PC[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7851 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[5] decode_to_execute_PC[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7853 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[4] decode_to_execute_PC[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7855 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[3] decode_to_execute_PC[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7857 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[2] decode_to_execute_PC[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7859 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 execute_CsrPlugin_csr_834 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2209 $abc$8788$auto$rtlil.cc:2693:MuxGate$7887 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2210 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2209 -11000 1 -.names $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2210 -1000 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n2211 -1100 1 -.names $abc$8788$new_n2458 execute_CsrPlugin_csr_772 $abc$8788$new_n2214 $abc$8788$new_n2213 $abc$8788$auto$rtlil.cc:2693:MuxGate$7889 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2213 -11000 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2214 -0000 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2216 execute_CsrPlugin_csr_836 $abc$8788$auto$rtlil.cc:2693:MuxGate$7891 -001 1 -011 1 -110 1 -111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2213 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2216 -11000 1 -.names $abc$8788$new_n2458 execute_CsrPlugin_csr_768 $abc$8788$new_n2210 $abc$8788$new_n2214 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7893 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$8788$new_n2245 _zz_execute_BRANCH_CTRL[0] $abc$8788$new_n2246 $abc$8788$new_n2219 $abc$8788$new_n2242 $abc$8788$auto$rtlil.cc:2693:MuxGate$7897 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n2220 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n2219 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[13] switch_Misc_l241_1 $abc$8788$new_n2221 $abc$8788$new_n2220 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n2236 $abc$8788$new_n2222 _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] $abc$8788$new_n2221 -1100 1 -1111 1 -.names $abc$8788$new_n2233 $abc$8788$new_n2223 $abc$8788$new_n2235 _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] $abc$8788$new_n2222 -11100 1 -11111 1 -.names $abc$8788$new_n2229 $abc$8788$new_n2224 $abc$8788$new_n2231 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n2223 -11100 1 -11111 1 -.names $abc$8788$new_n2228 $abc$8788$new_n2225 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n2227 $abc$8788$new_n2224 -11000 1 -11110 1 -.names $abc$8788$new_n2226 $abc$8788$new_n1797 _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] $abc$8788$new_n2225 -1100 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n2226 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] $abc$8788$new_n2227 -01 1 -10 1 -.names _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] $abc$8788$new_n2228 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$8788$new_n2230 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] $abc$8788$new_n2229 -10000 1 -10011 1 -11100 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n2230 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n2232 $abc$8788$new_n2231 -00000 1 -00110 1 -11000 1 -11110 1 -.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n2232 -01 1 -10 1 -.names $abc$8788$new_n2234 _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] $abc$8788$new_n2233 -10000 1 -10011 1 -11100 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n2234 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] $abc$8788$new_n2235 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$8788$new_n2239 $abc$8788$new_n2237 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] $abc$8788$new_n2236 -1100 1 -1111 1 -.names $abc$8788$new_n2238 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n2237 -10000 1 -10011 1 -11100 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n2238 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] $abc$8788$new_n2240 $abc$8788$new_n2239 -00000 1 -00110 1 -11000 1 -11110 1 -.names _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n2240 -01 1 -10 1 -.names $abc$8788$new_n2243 $abc$8788$new_n1802 $abc$8788$new_n2244 dBus_cmd_payload_address[31] $abc$8788$new_n1797 $abc$8788$new_n2242 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[13] dBus_cmd_payload_size[0] $abc$8788$new_n2221 switch_Misc_l241_1 $abc$8788$new_n2243 -0001 1 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n2244 -000 1 -.names $abc$8788$new_n1321 execute_to_memory_BRANCH_DO $abc$8788$new_n2245 -10 1 -.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n1321 $abc$8788$new_n2246 -00 1 -.names $abc$8788$new_n1321 $abc$8788$new_n2248 execute_to_memory_REGFILE_WRITE_DATA[31] $abc$8788$new_n1323 $abc$8788$new_n2250 $abc$8788$auto$rtlil.cc:2693:MuxGate$7899 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[31] $abc$8788$new_n2249 $abc$8788$new_n2248 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n2249 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n2251 execute_LightShifterPlugin_isActive $abc$8788$new_n1592 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n2250 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n2251 -11001 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 dBus_cmd_payload_address[1] execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7901 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2254 decode_to_execute_SRC2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7903 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] _zz_decode_SRC2 $abc$8788$new_n2254 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2256 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7905 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$8788$new_n2257 $abc$8788$new_n1937 _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2256 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2258 $abc$8788$new_n2257 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2258 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[31] decode_to_execute_RS2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7907 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[31] decode_to_execute_RS1[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7909 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2262 _zz_execute_BRANCH_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7911 -001 1 -011 1 -100 1 -101 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2262 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n2458 _zz_execute_SHIFT_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1937 $abc$8788$auto$rtlil.cc:2693:MuxGate$7913 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 _zz_execute_ALU_BITWISE_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7915 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1316 decode_to_execute_SRC_LESS_UNSIGNED IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7917 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2267 $abc$8788$auto$rtlil.cc:2693:MuxGate$7919 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$new_n2267 -000 1 -010 1 -011 1 -.names $abc$8788$new_n1321 _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$8788$auto$rtlil.cc:2693:MuxGate$7921 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_execute_ENV_CTRL $abc$8788$new_n1296 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7923 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1296 decode_to_execute_IS_CSR IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7925 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names dBus_cmd_payload_wr $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7927 -10 1 -.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_47 dBus_cmd_payload_wr $abc$8788$auto$rtlil.cc:2693:MuxGate$7929 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$8788$auto$rtlil.cc:2693:MuxGate$7931 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2275 decode_to_execute_REGFILE_WRITE_VALID $abc$8788$new_n2277 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7935 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$8788$new_n2276 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2275 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n2276 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n2277 -0000 1 -.names decode_to_execute_MEMORY_ENABLE $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7937 -01 1 -10 1 -11 1 -.names $abc$8788$new_n2458 decode_to_execute_MEMORY_ENABLE IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7939 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -11000 1 -.names $abc$8788$new_n2257 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_4 $abc$8788$auto$rtlil.cc:2693:MuxGate$7941 -001 1 -010 1 -011 1 -.names $abc$8788$new_n2458 decode_to_execute_CSR_WRITE_OPCODE $abc$8788$new_n2282 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7943 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2282 -10000 1 -.names $abc$8788$new_n2458 _zz_decode_SRC2 _zz_execute_BranchPlugin_branch_src2 $abc$8788$auto$rtlil.cc:2693:MuxGate$7947 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC2 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] decode_INSTRUCTION_ANTICIPATED[31] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 $abc$8788$new_n2287 $abc$8788$new_n2286 BranchPlugin_jumpInterface_payload[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7965 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2059 $abc$8788$new_n2005 $abc$8788$new_n2286 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1111 1 -.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2020 decode_to_execute_PC[31] decode_to_execute_RS1[31] $abc$8788$new_n2287 -0000 1 -0001 1 -0100 1 -0110 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7971 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[31] decode_to_execute_PC[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7973 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[11] _zz_RegFilePlugin_regFile_port0[11] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7979 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$8788$new_n2292 _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7983 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz_RegFilePlugin_regFile_port0[4] $abc$8788$new_n2292 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2294 _zz_execute_SrcPlugin_addSub_2[31] _zz_RegFilePlugin_regFile_port0[31] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7985 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_decode_SRC2 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2294 -1110 1 -.names decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$new_n1321 dBus_cmd_valid -1110 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[8] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[9] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[10] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[11] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[12] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[13] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[14] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[15] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[16] dBus_cmd_payload_data[0] dBus_cmd_payload_data[16] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[17] dBus_cmd_payload_data[1] dBus_cmd_payload_data[17] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[18] dBus_cmd_payload_data[2] dBus_cmd_payload_data[18] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[19] dBus_cmd_payload_data[3] dBus_cmd_payload_data[19] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[20] dBus_cmd_payload_data[4] dBus_cmd_payload_data[20] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[21] dBus_cmd_payload_data[5] dBus_cmd_payload_data[21] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[22] dBus_cmd_payload_data[6] dBus_cmd_payload_data[22] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[23] dBus_cmd_payload_data[7] dBus_cmd_payload_data[23] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[24] decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[24] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[25] decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[25] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[26] decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[26] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[27] decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[27] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[28] decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[28] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[29] decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[29] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[30] decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[30] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[31] decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[31] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2321 $abc$8788$new_n1492 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] -001 1 -011 1 -110 1 -111 1 -.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2321 -1111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] decode_INSTRUCTION_ANTICIPATED[15] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] decode_INSTRUCTION_ANTICIPATED[16] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] decode_INSTRUCTION_ANTICIPATED[17] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] decode_INSTRUCTION_ANTICIPATED[18] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] decode_INSTRUCTION_ANTICIPATED[19] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] decode_INSTRUCTION_ANTICIPATED[20] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] decode_INSTRUCTION_ANTICIPATED[21] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] decode_INSTRUCTION_ANTICIPATED[22] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] decode_INSTRUCTION_ANTICIPATED[23] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] decode_INSTRUCTION_ANTICIPATED[24] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1516 $abc$8788$new_n1272 $0\CsrPlugin_interrupt_valid[0:0] -10 1 -.names $abc$8788$new_n1270 $abc$8788$new_n2334 $abc$8788$new_n2335 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] -000 1 -001 1 -100 1 -110 1 -.names IBusSimplePlugin_pending_value[0] $abc$8788$new_n1454 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2334 -0000 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2335 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -01000 1 -01100 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2339 $abc$8788$new_n2338 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1454 IBusSimplePlugin_pending_value[0] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2337 -0001 1 -0010 1 -0011 1 -.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2338 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2339 -10001 1 -10010 1 -10011 1 -.names $abc$8788$new_n1270 $abc$8788$new_n2341 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2339 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2341 -010 1 -100 1 -101 1 -111 1 -.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[0] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][0] -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n2345 $abc$8788$new_n1500 $abc$8788$new_n2344 $abc$8788$new_n2343 -111 1 -.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_768 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2344 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[12] switch_Misc_l241_1 dBus_cmd_payload_size[0] CsrPlugin_mstatus_MPP[1] execute_CsrPlugin_csr_768 $abc$8788$new_n2345 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][1] -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n2344 $abc$8788$new_n1496 $abc$8788$new_n2348 $0\CsrPlugin_mstatus_MPIE[0:0] -000 1 -010 1 -110 1 -111 1 -.names $abc$8788$new_n1272 $abc$8788$new_n1274 CsrPlugin_mstatus_MIE CsrPlugin_mstatus_MPIE $abc$8788$new_n2348 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$8788$new_n2344 $abc$8788$new_n1492 $abc$8788$new_n2350 $0\CsrPlugin_mstatus_MIE[0:0] -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1274 CsrPlugin_mstatus_MPIE CsrPlugin_mstatus_MIE $abc$8788$new_n1272 $abc$8788$new_n2350 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names memory_arbitration_isValid $abc$8788$new_n1271 $abc$8788$new_n1321 $0\writeBack_arbitration_isValid[0:0] -110 1 -.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2353 memory_to_writeBack_REGFILE_WRITE_DATA[0] lastStageRegFileWrite_payload_data[0] -0001 1 -0011 1 -1000 1 -1001 1 -.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2354 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[16] $abc$8788$new_n2353 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[8] memory_to_writeBack_MEMORY_READ_DATA[0] $abc$8788$new_n2354 -000 1 -010 1 -100 1 -101 1 -.names memory_to_writeBack_MEMORY_ENABLE lastStageIsFiring $abc$8788$new_n2355 -11 1 -.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2357 memory_to_writeBack_REGFILE_WRITE_DATA[1] lastStageRegFileWrite_payload_data[1] -0001 1 -0011 1 -1000 1 -1001 1 -.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2358 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[17] $abc$8788$new_n2357 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[9] memory_to_writeBack_MEMORY_READ_DATA[1] $abc$8788$new_n2358 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2360 memory_to_writeBack_REGFILE_WRITE_DATA[2] lastStageRegFileWrite_payload_data[2] -0001 1 -0011 1 -1000 1 -1001 1 -.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2361 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[18] $abc$8788$new_n2360 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names 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memory_to_writeBack_MEMORY_READ_DATA[9] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2382 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names _zz_5 $abc$8788$new_n2384 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[10] lastStageRegFileWrite_payload_data[10] -00001 1 -00010 1 -00011 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[10] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2384 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names _zz_5 $abc$8788$new_n2386 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[11] lastStageRegFileWrite_payload_data[11] -00001 1 -00010 1 -00011 1 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-00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2442 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2442 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2443 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n1304 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] execute_to_memory_INSTRUCTION[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] execute_to_memory_INSTRUCTION[8] $abc$8788$new_n2445 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2445 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] execute_to_memory_INSTRUCTION[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] execute_to_memory_INSTRUCTION[10] $abc$8788$new_n2446 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -.names execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2448 -10000 1 -10011 1 -11100 1 -11111 1 -.names decode_to_execute_REGFILE_WRITE_VALID IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2_4[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n2449 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2448 $abc$8788$new_n2449 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2450 -1100 1 -1111 1 -.names HazardSimplePlugin_writeBackBuffer_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackBuffer_payload_address[0] HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2451 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2451 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2452 -10000 1 -10011 1 -11100 1 -11111 1 -.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2454 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2454 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2455 -10000 1 -10011 1 -11100 1 -11111 1 -.names decode_to_execute_IS_CSR memory_arbitration_isValid lastStageIsFiring decode_to_execute_MEMORY_ENABLE dBus_cmd_ready $abc$8788$new_n2457 -00010 1 -00110 1 -01010 1 -01110 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 execute_arbitration_isValid $abc$8788$new_n2457 $abc$8788$new_n1323 $abc$8788$new_n1325 $abc$8788$new_n2458 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2452 HazardSimplePlugin_writeBackBuffer_payload_address[4] $abc$8788$new_n2455 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2459 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names $abc$8788$new_n1278 $abc$8788$new_n1315 $abc$8788$new_n2446 $abc$8788$new_n2459 $abc$8788$new_n2450 $abc$8788$new_n2460 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1328 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2460 $abc$8788$new_n2461 -1100 1 -1101 1 -1110 1 -.names $abc$8788$new_n1285 decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$new_n2462 -11100 1 -11111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n2443 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2462 _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2463 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2463 $abc$8788$new_n1288 $abc$8788$new_n2440 $abc$8788$new_n2464 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7861 Q=CsrPlugin_mcause_exceptionCode[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7969 Q=CsrPlugin_mcause_exceptionCode[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7957 Q=CsrPlugin_interrupt_code[3] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[15] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[16] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[17] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[18] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[19] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[20] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[21] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[22] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[23] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[24] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7859 Q=decode_to_execute_PC[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7857 Q=decode_to_execute_PC[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7855 Q=decode_to_execute_PC[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7853 Q=decode_to_execute_PC[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7851 Q=decode_to_execute_PC[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7849 Q=decode_to_execute_PC[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7847 Q=decode_to_execute_PC[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7845 Q=decode_to_execute_PC[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7843 Q=decode_to_execute_PC[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7841 Q=decode_to_execute_PC[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7839 Q=decode_to_execute_PC[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7837 Q=decode_to_execute_PC[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7835 Q=decode_to_execute_PC[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7833 Q=decode_to_execute_PC[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7831 Q=decode_to_execute_PC[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7829 Q=decode_to_execute_PC[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7827 Q=decode_to_execute_PC[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7825 Q=decode_to_execute_PC[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7823 Q=decode_to_execute_PC[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7821 Q=decode_to_execute_PC[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7819 Q=decode_to_execute_PC[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7817 Q=decode_to_execute_PC[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7815 Q=decode_to_execute_PC[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7813 Q=decode_to_execute_PC[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7811 Q=decode_to_execute_PC[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7809 Q=decode_to_execute_PC[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7807 Q=decode_to_execute_PC[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7805 Q=decode_to_execute_PC[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7803 Q=decode_to_execute_PC[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7973 Q=decode_to_execute_PC[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7797 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7795 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7793 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7791 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7789 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7787 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7785 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7783 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7781 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7779 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7777 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7775 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7773 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7771 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7769 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7767 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7765 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7763 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7761 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7759 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7757 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7755 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7753 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7751 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7749 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7747 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7745 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7743 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7741 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7963 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7953 Q=CsrPlugin_interrupt_code[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7739 Q=_zz_execute_SrcPlugin_addSub_2[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7735 Q=_zz_execute_SrcPlugin_addSub_2[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7731 Q=_zz_execute_SrcPlugin_addSub_2[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7727 Q=_zz_execute_SrcPlugin_addSub_2[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7723 Q=_zz_execute_SrcPlugin_addSub_2[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7719 Q=_zz_execute_SrcPlugin_addSub_2[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7979 Q=_zz_execute_SrcPlugin_addSub_2[11] -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7863 Q=execute_LightShifterPlugin_isActive R=reset -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7715 Q=_zz_execute_SrcPlugin_addSub_2[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7711 Q=_zz_execute_SrcPlugin_addSub_2[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7707 Q=_zz_execute_SrcPlugin_addSub_2[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7983 Q=_zz_execute_SrcPlugin_addSub_2[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7703 Q=_zz_execute_SrcPlugin_addSub_2[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7701 Q=_zz_execute_SrcPlugin_addSub_2[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7699 Q=_zz_execute_SrcPlugin_addSub_2[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7697 Q=_zz_execute_SrcPlugin_addSub_2[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7695 Q=_zz_execute_SrcPlugin_addSub_2[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7693 Q=_zz_execute_SrcPlugin_addSub_2[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7691 Q=_zz_execute_SrcPlugin_addSub_2[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7689 Q=_zz_execute_SrcPlugin_addSub_2[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7687 Q=_zz_execute_SrcPlugin_addSub_2[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7685 Q=_zz_execute_SrcPlugin_addSub_2[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7683 Q=_zz_execute_SrcPlugin_addSub_2[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7681 Q=_zz_execute_SrcPlugin_addSub_2[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7679 Q=_zz_execute_SrcPlugin_addSub_2[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7677 Q=_zz_execute_SrcPlugin_addSub_2[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7675 Q=_zz_execute_SrcPlugin_addSub_2[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7673 Q=_zz_execute_SrcPlugin_addSub_2[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7671 Q=_zz_execute_SrcPlugin_addSub_2[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7669 Q=_zz_execute_SrcPlugin_addSub_2[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7667 Q=_zz_execute_SrcPlugin_addSub_2[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7665 Q=_zz_execute_SrcPlugin_addSub_2[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7985 Q=_zz_execute_SrcPlugin_addSub_2[31] -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7961 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=reset -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[2] Q=_zz_decode_SRC_LESS_UNSIGNED_4 -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[3] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[4] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[5] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_47 -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[6] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[7] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[8] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[9] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[10] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[11] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[12] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_13 -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[13] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[14] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[25] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[26] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[27] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[28] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[29] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[30] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[31] Q=_zz_decode_SRC2 -.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP -.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP -.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7619 Q=BranchPlugin_jumpInterface_payload[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7617 Q=BranchPlugin_jumpInterface_payload[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7615 Q=BranchPlugin_jumpInterface_payload[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7613 Q=BranchPlugin_jumpInterface_payload[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7611 Q=BranchPlugin_jumpInterface_payload[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7609 Q=BranchPlugin_jumpInterface_payload[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7607 Q=BranchPlugin_jumpInterface_payload[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7605 Q=BranchPlugin_jumpInterface_payload[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7603 Q=BranchPlugin_jumpInterface_payload[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7601 Q=BranchPlugin_jumpInterface_payload[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7599 Q=BranchPlugin_jumpInterface_payload[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7597 Q=BranchPlugin_jumpInterface_payload[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7595 Q=BranchPlugin_jumpInterface_payload[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7593 Q=BranchPlugin_jumpInterface_payload[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7591 Q=BranchPlugin_jumpInterface_payload[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7589 Q=BranchPlugin_jumpInterface_payload[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7587 Q=BranchPlugin_jumpInterface_payload[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7585 Q=BranchPlugin_jumpInterface_payload[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7583 Q=BranchPlugin_jumpInterface_payload[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7581 Q=BranchPlugin_jumpInterface_payload[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7579 Q=BranchPlugin_jumpInterface_payload[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7577 Q=BranchPlugin_jumpInterface_payload[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7575 Q=BranchPlugin_jumpInterface_payload[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7573 Q=BranchPlugin_jumpInterface_payload[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7571 Q=BranchPlugin_jumpInterface_payload[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7569 Q=BranchPlugin_jumpInterface_payload[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7567 Q=BranchPlugin_jumpInterface_payload[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7565 Q=BranchPlugin_jumpInterface_payload[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7563 Q=BranchPlugin_jumpInterface_payload[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7965 Q=BranchPlugin_jumpInterface_payload[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7561 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7559 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7557 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7555 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7553 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7551 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7549 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7547 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7545 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7543 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7541 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7539 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7537 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7535 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7533 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7531 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7529 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7527 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7525 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7523 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7521 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7519 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7517 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7515 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7513 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7511 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7509 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7507 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7505 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7971 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[31] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7503 Q=execute_LightShifterPlugin_amplitudeReg[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7501 Q=execute_LightShifterPlugin_amplitudeReg[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7499 Q=execute_LightShifterPlugin_amplitudeReg[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7497 Q=execute_LightShifterPlugin_amplitudeReg[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7949 Q=execute_LightShifterPlugin_amplitudeReg[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7495 Q=CsrPlugin_mepc[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7493 Q=CsrPlugin_mepc[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7491 Q=CsrPlugin_mepc[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7489 Q=CsrPlugin_mepc[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7487 Q=CsrPlugin_mepc[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7485 Q=CsrPlugin_mepc[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7483 Q=CsrPlugin_mepc[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7481 Q=CsrPlugin_mepc[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7479 Q=CsrPlugin_mepc[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7477 Q=CsrPlugin_mepc[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7475 Q=CsrPlugin_mepc[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7473 Q=CsrPlugin_mepc[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7471 Q=CsrPlugin_mepc[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7469 Q=CsrPlugin_mepc[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7467 Q=CsrPlugin_mepc[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7465 Q=CsrPlugin_mepc[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7463 Q=CsrPlugin_mepc[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7461 Q=CsrPlugin_mepc[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7459 Q=CsrPlugin_mepc[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7457 Q=CsrPlugin_mepc[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7455 Q=CsrPlugin_mepc[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7453 Q=CsrPlugin_mepc[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7451 Q=CsrPlugin_mepc[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7449 Q=CsrPlugin_mepc[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7447 Q=CsrPlugin_mepc[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7445 Q=CsrPlugin_mepc[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7443 Q=CsrPlugin_mepc[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7441 Q=CsrPlugin_mepc[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7439 Q=CsrPlugin_mepc[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7975 Q=CsrPlugin_mepc[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7423 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7421 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7419 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7417 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7415 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7413 Q=dBus_cmd_payload_size[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7411 Q=switch_Misc_l241_1 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7409 Q=_zz__zz_execute_BranchPlugin_branch_src2[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7407 Q=_zz__zz_execute_BranchPlugin_branch_src2[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7405 Q=_zz__zz_execute_BranchPlugin_branch_src2[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7403 Q=_zz__zz_execute_BranchPlugin_branch_src2[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7401 Q=_zz__zz_execute_BranchPlugin_branch_src2[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7399 Q=_zz__zz_execute_BranchPlugin_branch_src2[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7397 Q=_zz__zz_execute_BranchPlugin_branch_src2[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7395 Q=_zz__zz_execute_BranchPlugin_branch_src2[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7393 Q=_zz__zz_execute_BranchPlugin_branch_src2[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7391 Q=_zz__zz_execute_BranchPlugin_branch_src2[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7389 Q=_zz__zz_execute_BranchPlugin_branch_src2[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7387 Q=_zz__zz_execute_BranchPlugin_branch_src2[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7385 Q=_zz__zz_execute_BranchPlugin_branch_src2[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7383 Q=_zz__zz_execute_BranchPlugin_branch_src2[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7381 Q=_zz__zz_execute_BranchPlugin_branch_src2[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7379 Q=_zz__zz_execute_BranchPlugin_branch_src2[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7377 Q=_zz__zz_execute_BranchPlugin_branch_src2[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7947 Q=_zz_execute_BranchPlugin_branch_src2 -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[7] Q=HazardSimplePlugin_writeBackWrites_payload_address[0] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[8] Q=HazardSimplePlugin_writeBackWrites_payload_address[1] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[9] Q=HazardSimplePlugin_writeBackWrites_payload_address[2] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[10] Q=HazardSimplePlugin_writeBackWrites_payload_address[3] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[11] Q=HazardSimplePlugin_writeBackWrites_payload_address[4] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[12] Q=_zz_lastStageRegFileWrite_payload_address[12] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[13] Q=_zz_lastStageRegFileWrite_payload_address[13] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[14] Q=_zz_lastStageRegFileWrite_payload_address[14] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[28] Q=_zz_lastStageRegFileWrite_payload_address[28] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[29] Q=_zz_lastStageRegFileWrite_payload_address[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7361 Q=execute_to_memory_INSTRUCTION[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7359 Q=execute_to_memory_INSTRUCTION[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7357 Q=execute_to_memory_INSTRUCTION[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7355 Q=execute_to_memory_INSTRUCTION[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7353 Q=execute_to_memory_INSTRUCTION[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7351 Q=execute_to_memory_INSTRUCTION[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7349 Q=execute_to_memory_INSTRUCTION[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7347 Q=execute_to_memory_INSTRUCTION[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7319 Q=execute_to_memory_INSTRUCTION[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7317 Q=execute_to_memory_INSTRUCTION[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7943 Q=decode_to_execute_CSR_WRITE_OPCODE -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7941 Q=_zz_execute_SrcPlugin_addSub_4 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7939 Q=decode_to_execute_MEMORY_ENABLE -.subckt dff C=clk D=execute_to_memory_MEMORY_ENABLE Q=memory_to_writeBack_MEMORY_ENABLE -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7935 Q=decode_to_execute_REGFILE_WRITE_VALID -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7937 Q=execute_to_memory_MEMORY_ENABLE -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_VALID Q=_zz_lastStageRegFileWrite_valid -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7931 Q=execute_to_memory_REGFILE_WRITE_VALID -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7929 Q=dBus_cmd_payload_wr -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7927 Q=execute_to_memory_MEMORY_STORE -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7925 Q=decode_to_execute_IS_CSR -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7923 Q=_zz_execute_ENV_CTRL -.subckt dff C=clk D=_zz_memory_ENV_CTRL Q=_zz_writeBack_ENV_CTRL -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7921 Q=_zz_memory_ENV_CTRL -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7313 Q=_zz_execute_ALU_CTRL[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7919 Q=_zz_execute_ALU_CTRL[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7917 Q=decode_to_execute_SRC_LESS_UNSIGNED -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7311 Q=_zz_execute_ALU_BITWISE_CTRL[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7915 Q=_zz_execute_ALU_BITWISE_CTRL[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7309 Q=_zz_execute_SHIFT_CTRL[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7913 Q=_zz_execute_SHIFT_CTRL[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7307 Q=_zz_execute_BRANCH_CTRL[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7911 Q=_zz_execute_BRANCH_CTRL[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7305 Q=decode_to_execute_RS1[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7303 Q=decode_to_execute_RS1[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7301 Q=decode_to_execute_RS1[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7299 Q=decode_to_execute_RS1[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7297 Q=decode_to_execute_RS1[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7295 Q=decode_to_execute_RS1[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7293 Q=decode_to_execute_RS1[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7291 Q=decode_to_execute_RS1[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7289 Q=decode_to_execute_RS1[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7287 Q=decode_to_execute_RS1[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7285 Q=decode_to_execute_RS1[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7283 Q=decode_to_execute_RS1[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7281 Q=decode_to_execute_RS1[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7279 Q=decode_to_execute_RS1[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7277 Q=decode_to_execute_RS1[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7275 Q=decode_to_execute_RS1[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7273 Q=decode_to_execute_RS1[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7271 Q=decode_to_execute_RS1[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7269 Q=decode_to_execute_RS1[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7267 Q=decode_to_execute_RS1[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7265 Q=decode_to_execute_RS1[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7263 Q=decode_to_execute_RS1[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7261 Q=decode_to_execute_RS1[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7259 Q=decode_to_execute_RS1[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7257 Q=decode_to_execute_RS1[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7255 Q=decode_to_execute_RS1[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7253 Q=decode_to_execute_RS1[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7251 Q=decode_to_execute_RS1[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7249 Q=decode_to_execute_RS1[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7247 Q=decode_to_execute_RS1[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7245 Q=decode_to_execute_RS1[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7909 Q=decode_to_execute_RS1[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7243 Q=dBus_cmd_payload_data[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7241 Q=dBus_cmd_payload_data[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7239 Q=dBus_cmd_payload_data[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7237 Q=dBus_cmd_payload_data[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7235 Q=dBus_cmd_payload_data[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7233 Q=dBus_cmd_payload_data[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7231 Q=dBus_cmd_payload_data[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7229 Q=dBus_cmd_payload_data[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7227 Q=decode_to_execute_RS2[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7225 Q=decode_to_execute_RS2[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7223 Q=decode_to_execute_RS2[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7221 Q=decode_to_execute_RS2[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7219 Q=decode_to_execute_RS2[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7217 Q=decode_to_execute_RS2[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7215 Q=decode_to_execute_RS2[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7213 Q=decode_to_execute_RS2[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7211 Q=decode_to_execute_RS2[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7209 Q=decode_to_execute_RS2[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7207 Q=decode_to_execute_RS2[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7205 Q=decode_to_execute_RS2[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7203 Q=decode_to_execute_RS2[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7201 Q=decode_to_execute_RS2[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7199 Q=decode_to_execute_RS2[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7197 Q=decode_to_execute_RS2[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7195 Q=decode_to_execute_RS2[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7193 Q=decode_to_execute_RS2[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7191 Q=decode_to_execute_RS2[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7189 Q=decode_to_execute_RS2[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7187 Q=decode_to_execute_RS2[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7185 Q=decode_to_execute_RS2[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7183 Q=decode_to_execute_RS2[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7907 Q=decode_to_execute_RS2[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7905 Q=decode_to_execute_SRC2_FORCE_ZERO -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7181 Q=decode_to_execute_SRC2[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7179 Q=decode_to_execute_SRC2[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7177 Q=decode_to_execute_SRC2[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7175 Q=decode_to_execute_SRC2[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7173 Q=decode_to_execute_SRC2[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7171 Q=decode_to_execute_SRC2[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7169 Q=decode_to_execute_SRC2[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7167 Q=decode_to_execute_SRC2[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7165 Q=decode_to_execute_SRC2[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7163 Q=decode_to_execute_SRC2[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7161 Q=decode_to_execute_SRC2[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7159 Q=decode_to_execute_SRC2[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7157 Q=decode_to_execute_SRC2[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7155 Q=decode_to_execute_SRC2[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7153 Q=decode_to_execute_SRC2[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7151 Q=decode_to_execute_SRC2[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7149 Q=decode_to_execute_SRC2[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7147 Q=decode_to_execute_SRC2[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7145 Q=decode_to_execute_SRC2[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7143 Q=decode_to_execute_SRC2[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7141 Q=decode_to_execute_SRC2[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7139 Q=decode_to_execute_SRC2[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7137 Q=decode_to_execute_SRC2[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7135 Q=decode_to_execute_SRC2[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7133 Q=decode_to_execute_SRC2[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7131 Q=decode_to_execute_SRC2[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7129 Q=decode_to_execute_SRC2[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7127 Q=decode_to_execute_SRC2[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7125 Q=decode_to_execute_SRC2[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7123 Q=decode_to_execute_SRC2[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7121 Q=decode_to_execute_SRC2[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7903 Q=decode_to_execute_SRC2[31] -.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[0] -.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7119 Q=execute_to_memory_MEMORY_ADDRESS_LOW[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7901 Q=execute_to_memory_MEMORY_ADDRESS_LOW[1] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[0] Q=memory_to_writeBack_REGFILE_WRITE_DATA[0] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[1] Q=memory_to_writeBack_REGFILE_WRITE_DATA[1] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[2] Q=memory_to_writeBack_REGFILE_WRITE_DATA[2] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[3] Q=memory_to_writeBack_REGFILE_WRITE_DATA[3] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[4] Q=memory_to_writeBack_REGFILE_WRITE_DATA[4] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[5] Q=memory_to_writeBack_REGFILE_WRITE_DATA[5] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[6] Q=memory_to_writeBack_REGFILE_WRITE_DATA[6] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[7] Q=memory_to_writeBack_REGFILE_WRITE_DATA[7] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[8] Q=memory_to_writeBack_REGFILE_WRITE_DATA[8] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[9] Q=memory_to_writeBack_REGFILE_WRITE_DATA[9] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[10] Q=memory_to_writeBack_REGFILE_WRITE_DATA[10] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[11] Q=memory_to_writeBack_REGFILE_WRITE_DATA[11] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[12] Q=memory_to_writeBack_REGFILE_WRITE_DATA[12] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[13] Q=memory_to_writeBack_REGFILE_WRITE_DATA[13] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[14] Q=memory_to_writeBack_REGFILE_WRITE_DATA[14] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[15] Q=memory_to_writeBack_REGFILE_WRITE_DATA[15] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[16] Q=memory_to_writeBack_REGFILE_WRITE_DATA[16] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[17] Q=memory_to_writeBack_REGFILE_WRITE_DATA[17] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[18] Q=memory_to_writeBack_REGFILE_WRITE_DATA[18] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[19] Q=memory_to_writeBack_REGFILE_WRITE_DATA[19] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[20] Q=memory_to_writeBack_REGFILE_WRITE_DATA[20] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[21] Q=memory_to_writeBack_REGFILE_WRITE_DATA[21] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[22] Q=memory_to_writeBack_REGFILE_WRITE_DATA[22] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[23] Q=memory_to_writeBack_REGFILE_WRITE_DATA[23] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[24] Q=memory_to_writeBack_REGFILE_WRITE_DATA[24] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[25] Q=memory_to_writeBack_REGFILE_WRITE_DATA[25] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[26] Q=memory_to_writeBack_REGFILE_WRITE_DATA[26] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[27] Q=memory_to_writeBack_REGFILE_WRITE_DATA[27] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[28] Q=memory_to_writeBack_REGFILE_WRITE_DATA[28] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[29] Q=memory_to_writeBack_REGFILE_WRITE_DATA[29] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[30] Q=memory_to_writeBack_REGFILE_WRITE_DATA[30] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[31] Q=memory_to_writeBack_REGFILE_WRITE_DATA[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7897 Q=execute_to_memory_BRANCH_DO -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7117 Q=execute_to_memory_REGFILE_WRITE_DATA[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7115 Q=execute_to_memory_REGFILE_WRITE_DATA[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7113 Q=execute_to_memory_REGFILE_WRITE_DATA[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7111 Q=execute_to_memory_REGFILE_WRITE_DATA[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7109 Q=execute_to_memory_REGFILE_WRITE_DATA[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7107 Q=execute_to_memory_REGFILE_WRITE_DATA[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7105 Q=execute_to_memory_REGFILE_WRITE_DATA[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7103 Q=execute_to_memory_REGFILE_WRITE_DATA[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7101 Q=execute_to_memory_REGFILE_WRITE_DATA[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7099 Q=execute_to_memory_REGFILE_WRITE_DATA[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7097 Q=execute_to_memory_REGFILE_WRITE_DATA[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7095 Q=execute_to_memory_REGFILE_WRITE_DATA[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7093 Q=execute_to_memory_REGFILE_WRITE_DATA[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7091 Q=execute_to_memory_REGFILE_WRITE_DATA[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7089 Q=execute_to_memory_REGFILE_WRITE_DATA[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7087 Q=execute_to_memory_REGFILE_WRITE_DATA[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7085 Q=execute_to_memory_REGFILE_WRITE_DATA[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7083 Q=execute_to_memory_REGFILE_WRITE_DATA[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7081 Q=execute_to_memory_REGFILE_WRITE_DATA[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7079 Q=execute_to_memory_REGFILE_WRITE_DATA[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7077 Q=execute_to_memory_REGFILE_WRITE_DATA[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7075 Q=execute_to_memory_REGFILE_WRITE_DATA[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7073 Q=execute_to_memory_REGFILE_WRITE_DATA[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7071 Q=execute_to_memory_REGFILE_WRITE_DATA[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7069 Q=execute_to_memory_REGFILE_WRITE_DATA[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7067 Q=execute_to_memory_REGFILE_WRITE_DATA[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7065 Q=execute_to_memory_REGFILE_WRITE_DATA[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7063 Q=execute_to_memory_REGFILE_WRITE_DATA[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7061 Q=execute_to_memory_REGFILE_WRITE_DATA[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7059 Q=execute_to_memory_REGFILE_WRITE_DATA[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7057 Q=execute_to_memory_REGFILE_WRITE_DATA[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7899 Q=execute_to_memory_REGFILE_WRITE_DATA[31] -.subckt dff C=clk D=dBus_rsp_data[0] Q=memory_to_writeBack_MEMORY_READ_DATA[0] -.subckt dff C=clk D=dBus_rsp_data[1] Q=memory_to_writeBack_MEMORY_READ_DATA[1] -.subckt dff C=clk D=dBus_rsp_data[2] Q=memory_to_writeBack_MEMORY_READ_DATA[2] -.subckt dff C=clk D=dBus_rsp_data[3] Q=memory_to_writeBack_MEMORY_READ_DATA[3] -.subckt dff C=clk D=dBus_rsp_data[4] Q=memory_to_writeBack_MEMORY_READ_DATA[4] -.subckt dff C=clk D=dBus_rsp_data[5] Q=memory_to_writeBack_MEMORY_READ_DATA[5] -.subckt dff C=clk D=dBus_rsp_data[6] Q=memory_to_writeBack_MEMORY_READ_DATA[6] -.subckt dff C=clk D=dBus_rsp_data[7] Q=memory_to_writeBack_MEMORY_READ_DATA[7] -.subckt dff C=clk D=dBus_rsp_data[8] Q=memory_to_writeBack_MEMORY_READ_DATA[8] -.subckt dff C=clk D=dBus_rsp_data[9] Q=memory_to_writeBack_MEMORY_READ_DATA[9] -.subckt dff C=clk D=dBus_rsp_data[10] Q=memory_to_writeBack_MEMORY_READ_DATA[10] -.subckt dff C=clk D=dBus_rsp_data[11] Q=memory_to_writeBack_MEMORY_READ_DATA[11] -.subckt dff C=clk D=dBus_rsp_data[12] Q=memory_to_writeBack_MEMORY_READ_DATA[12] -.subckt dff C=clk D=dBus_rsp_data[13] Q=memory_to_writeBack_MEMORY_READ_DATA[13] -.subckt dff C=clk D=dBus_rsp_data[14] Q=memory_to_writeBack_MEMORY_READ_DATA[14] -.subckt dff C=clk D=dBus_rsp_data[15] Q=memory_to_writeBack_MEMORY_READ_DATA[15] -.subckt dff C=clk D=dBus_rsp_data[16] Q=memory_to_writeBack_MEMORY_READ_DATA[16] -.subckt dff C=clk D=dBus_rsp_data[17] Q=memory_to_writeBack_MEMORY_READ_DATA[17] -.subckt dff C=clk D=dBus_rsp_data[18] Q=memory_to_writeBack_MEMORY_READ_DATA[18] -.subckt dff C=clk D=dBus_rsp_data[19] Q=memory_to_writeBack_MEMORY_READ_DATA[19] -.subckt dff C=clk D=dBus_rsp_data[20] Q=writeBack_MEMORY_READ_DATA[20] -.subckt dff C=clk D=dBus_rsp_data[21] Q=writeBack_MEMORY_READ_DATA[21] -.subckt dff C=clk D=dBus_rsp_data[22] Q=writeBack_MEMORY_READ_DATA[22] -.subckt dff C=clk D=dBus_rsp_data[23] Q=writeBack_MEMORY_READ_DATA[23] -.subckt dff C=clk D=dBus_rsp_data[24] Q=writeBack_MEMORY_READ_DATA[24] -.subckt dff C=clk D=dBus_rsp_data[25] Q=writeBack_MEMORY_READ_DATA[25] -.subckt dff C=clk D=dBus_rsp_data[26] Q=writeBack_MEMORY_READ_DATA[26] -.subckt dff C=clk D=dBus_rsp_data[27] Q=writeBack_MEMORY_READ_DATA[27] -.subckt dff C=clk D=dBus_rsp_data[28] Q=writeBack_MEMORY_READ_DATA[28] -.subckt dff C=clk D=dBus_rsp_data[29] Q=writeBack_MEMORY_READ_DATA[29] -.subckt dff C=clk D=dBus_rsp_data[30] Q=writeBack_MEMORY_READ_DATA[30] -.subckt dff C=clk D=dBus_rsp_data[31] Q=writeBack_MEMORY_READ_DATA[31] -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7055 Q=IBusSimplePlugin_fetchPc_pcReg[2] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7053 Q=IBusSimplePlugin_fetchPc_pcReg[3] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7051 Q=IBusSimplePlugin_fetchPc_pcReg[4] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7049 Q=IBusSimplePlugin_fetchPc_pcReg[5] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7047 Q=IBusSimplePlugin_fetchPc_pcReg[6] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7045 Q=IBusSimplePlugin_fetchPc_pcReg[7] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7043 Q=IBusSimplePlugin_fetchPc_pcReg[8] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7041 Q=IBusSimplePlugin_fetchPc_pcReg[9] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7039 Q=IBusSimplePlugin_fetchPc_pcReg[10] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7037 Q=IBusSimplePlugin_fetchPc_pcReg[11] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7035 Q=IBusSimplePlugin_fetchPc_pcReg[12] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7033 Q=IBusSimplePlugin_fetchPc_pcReg[13] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7031 Q=IBusSimplePlugin_fetchPc_pcReg[14] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7029 Q=IBusSimplePlugin_fetchPc_pcReg[15] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7027 Q=IBusSimplePlugin_fetchPc_pcReg[16] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7025 Q=IBusSimplePlugin_fetchPc_pcReg[17] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7023 Q=IBusSimplePlugin_fetchPc_pcReg[18] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7021 Q=IBusSimplePlugin_fetchPc_pcReg[19] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7019 Q=IBusSimplePlugin_fetchPc_pcReg[20] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7017 Q=IBusSimplePlugin_fetchPc_pcReg[21] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7015 Q=IBusSimplePlugin_fetchPc_pcReg[22] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7013 Q=IBusSimplePlugin_fetchPc_pcReg[23] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7011 Q=IBusSimplePlugin_fetchPc_pcReg[24] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7009 Q=IBusSimplePlugin_fetchPc_pcReg[25] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7007 Q=IBusSimplePlugin_fetchPc_pcReg[26] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7005 Q=IBusSimplePlugin_fetchPc_pcReg[27] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7003 Q=IBusSimplePlugin_fetchPc_pcReg[28] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7001 Q=IBusSimplePlugin_fetchPc_pcReg[29] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$6999 Q=IBusSimplePlugin_fetchPc_pcReg[30] R=reset -.subckt dffs C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7967 Q=IBusSimplePlugin_fetchPc_pcReg[31] S=reset -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7893 Q=execute_CsrPlugin_csr_768 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7891 Q=execute_CsrPlugin_csr_836 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7889 Q=execute_CsrPlugin_csr_772 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7887 Q=execute_CsrPlugin_csr_834 -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7885 Q=execute_arbitration_isValid R=reset -.subckt dffr C=clk D=$0\writeBack_arbitration_isValid[0:0] Q=lastStageIsFiring R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7883 Q=memory_arbitration_isValid R=reset -.subckt dffr C=clk D=$true Q=IBusSimplePlugin_fetchPc_booted R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7881 Q=IBusSimplePlugin_fetchPc_inc R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7879 Q=IBusSimplePlugin_iBusRsp_stages_1_input_valid R=reset -.subckt dffr C=clk D=IBusSimplePlugin_pending_next[0] Q=IBusSimplePlugin_pending_value[0] R=reset -.subckt dffr C=clk D=IBusSimplePlugin_pending_next[1] Q=IBusSimplePlugin_pending_value[1] R=reset -.subckt dffr C=clk D=IBusSimplePlugin_pending_next[2] Q=IBusSimplePlugin_pending_value[2] R=reset -.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=reset -.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=reset -.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=reset -.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset -.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset -.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset -.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7877 Q=IBusSimplePlugin_injector_decodeInput_valid R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7875 Q=CsrPlugin_mie_MEIE R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7873 Q=CsrPlugin_mie_MTIE R=reset -.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7871 Q=CsrPlugin_mie_MSIE R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7869 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7867 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset -.subckt dffs C=clk D=$false Q=_zz_5 S=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7865 Q=CsrPlugin_pipelineLiberator_done R=reset -.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2203[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2203[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2203[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2203[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2204[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2204[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2204[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2204[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 -.names $false BranchPlugin_jumpInterface_payload[0] -1 1 -.names $true CsrPlugin_interrupt_code[0] -1 1 -.names $true CsrPlugin_interrupt_code[1] -1 1 -.names $true CsrPlugin_mcause_exceptionCode[0] -1 1 -.names $true CsrPlugin_mcause_exceptionCode[1] -1 1 -.names $false CsrPlugin_mepc[0] -1 1 -.names $false CsrPlugin_mepc[1] -1 1 -.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$2203[0] -1 1 -.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$2203[1] -1 1 -.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$2203[2] -1 1 -.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$2203[3] -1 1 -.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$2203[4] -1 1 -.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$2203[5] -1 1 -.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$2203[6] -1 1 -.names _zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$2203[7] -1 1 -.names _zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$2203[8] -1 1 -.names _zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$2203[9] -1 1 -.names _zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$2203[10] -1 1 -.names _zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$2203[11] -1 1 -.names _zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$2203[12] -1 1 -.names _zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$2203[13] -1 1 -.names _zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$2203[14] -1 1 -.names _zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$2203[15] -1 1 -.names _zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$2203[16] -1 1 -.names _zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$2203[17] -1 1 -.names _zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$2203[18] -1 1 -.names _zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$2203[19] -1 1 -.names _zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$2203[20] -1 1 -.names _zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$2203[21] -1 1 -.names _zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$2203[22] -1 1 -.names _zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$2203[23] -1 1 -.names _zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$2203[24] -1 1 -.names _zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$2203[25] -1 1 -.names _zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$2203[26] -1 1 -.names _zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$2203[27] -1 1 -.names _zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$2203[28] -1 1 -.names _zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$2203[29] -1 1 -.names _zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$2203[30] -1 1 -.names _zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$2203[31] -1 1 -.names _zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$2204[0] -1 1 -.names _zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$2204[1] -1 1 -.names _zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$2204[2] -1 1 -.names _zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$2204[3] -1 1 -.names _zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$2204[4] -1 1 -.names _zz_RegFilePlugin_regFile_port0[5] $auto$memory_bram.cc:844:replace_memory$2204[5] -1 1 -.names _zz_RegFilePlugin_regFile_port0[6] $auto$memory_bram.cc:844:replace_memory$2204[6] -1 1 -.names _zz_RegFilePlugin_regFile_port0[7] $auto$memory_bram.cc:844:replace_memory$2204[7] -1 1 -.names _zz_RegFilePlugin_regFile_port0[8] $auto$memory_bram.cc:844:replace_memory$2204[8] -1 1 -.names _zz_RegFilePlugin_regFile_port0[9] $auto$memory_bram.cc:844:replace_memory$2204[9] -1 1 -.names _zz_RegFilePlugin_regFile_port0[10] $auto$memory_bram.cc:844:replace_memory$2204[10] -1 1 -.names _zz_RegFilePlugin_regFile_port0[11] $auto$memory_bram.cc:844:replace_memory$2204[11] -1 1 -.names _zz_RegFilePlugin_regFile_port0[12] $auto$memory_bram.cc:844:replace_memory$2204[12] -1 1 -.names _zz_RegFilePlugin_regFile_port0[13] $auto$memory_bram.cc:844:replace_memory$2204[13] -1 1 -.names _zz_RegFilePlugin_regFile_port0[14] $auto$memory_bram.cc:844:replace_memory$2204[14] -1 1 -.names _zz_RegFilePlugin_regFile_port0[15] $auto$memory_bram.cc:844:replace_memory$2204[15] -1 1 -.names _zz_RegFilePlugin_regFile_port0[16] $auto$memory_bram.cc:844:replace_memory$2204[16] -1 1 -.names _zz_RegFilePlugin_regFile_port0[17] $auto$memory_bram.cc:844:replace_memory$2204[17] -1 1 -.names _zz_RegFilePlugin_regFile_port0[18] $auto$memory_bram.cc:844:replace_memory$2204[18] -1 1 -.names _zz_RegFilePlugin_regFile_port0[19] $auto$memory_bram.cc:844:replace_memory$2204[19] -1 1 -.names _zz_RegFilePlugin_regFile_port0[20] $auto$memory_bram.cc:844:replace_memory$2204[20] -1 1 -.names _zz_RegFilePlugin_regFile_port0[21] $auto$memory_bram.cc:844:replace_memory$2204[21] -1 1 -.names _zz_RegFilePlugin_regFile_port0[22] $auto$memory_bram.cc:844:replace_memory$2204[22] -1 1 -.names _zz_RegFilePlugin_regFile_port0[23] $auto$memory_bram.cc:844:replace_memory$2204[23] -1 1 -.names _zz_RegFilePlugin_regFile_port0[24] $auto$memory_bram.cc:844:replace_memory$2204[24] -1 1 -.names _zz_RegFilePlugin_regFile_port0[25] $auto$memory_bram.cc:844:replace_memory$2204[25] -1 1 -.names _zz_RegFilePlugin_regFile_port0[26] $auto$memory_bram.cc:844:replace_memory$2204[26] -1 1 -.names _zz_RegFilePlugin_regFile_port0[27] $auto$memory_bram.cc:844:replace_memory$2204[27] -1 1 -.names _zz_RegFilePlugin_regFile_port0[28] $auto$memory_bram.cc:844:replace_memory$2204[28] -1 1 -.names _zz_RegFilePlugin_regFile_port0[29] $auto$memory_bram.cc:844:replace_memory$2204[29] -1 1 -.names _zz_RegFilePlugin_regFile_port0[30] $auto$memory_bram.cc:844:replace_memory$2204[30] -1 1 -.names _zz_RegFilePlugin_regFile_port0[31] $auto$memory_bram.cc:844:replace_memory$2204[31] -1 1 -.names $false IBusSimplePlugin_fetchPc_pcReg[0] -1 1 -.names $false IBusSimplePlugin_fetchPc_pcReg[1] -1 1 -.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[0] -1 1 -.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[1] -1 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] -1 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] -1 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] -1 1 -.names _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] -1 1 -.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[11] -1 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[12] -1 1 -.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[19] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[4] _zz__zz_execute_BranchPlugin_branch_src2_4[4] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2_4[5] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[6] _zz__zz_execute_BranchPlugin_branch_src2_4[6] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2_4[7] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[8] _zz__zz_execute_BranchPlugin_branch_src2_4[8] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[9] _zz__zz_execute_BranchPlugin_branch_src2_4[9] -1 1 -.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_4[11] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_lastStageRegFileWrite_payload_address[7] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_lastStageRegFileWrite_payload_address[8] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_lastStageRegFileWrite_payload_address[9] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_lastStageRegFileWrite_payload_address[10] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_lastStageRegFileWrite_payload_address[11] -1 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[1] -1 1 -.names $false decode_to_execute_PC[0] -1 1 -.names $false decode_to_execute_PC[1] -1 1 -.names dBus_cmd_payload_data[0] decode_to_execute_RS2[0] -1 1 -.names dBus_cmd_payload_data[1] decode_to_execute_RS2[1] -1 1 -.names dBus_cmd_payload_data[2] decode_to_execute_RS2[2] -1 1 -.names dBus_cmd_payload_data[3] decode_to_execute_RS2[3] -1 1 -.names dBus_cmd_payload_data[4] decode_to_execute_RS2[4] -1 1 -.names dBus_cmd_payload_data[5] decode_to_execute_RS2[5] -1 1 -.names dBus_cmd_payload_data[6] decode_to_execute_RS2[6] -1 1 -.names dBus_cmd_payload_data[7] decode_to_execute_RS2[7] -1 1 -.names $false iBus_cmd_payload_pc[0] -1 1 -.names $false iBus_cmd_payload_pc[1] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[0] writeBack_MEMORY_READ_DATA[0] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[1] writeBack_MEMORY_READ_DATA[1] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[2] writeBack_MEMORY_READ_DATA[2] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[3] writeBack_MEMORY_READ_DATA[3] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[4] writeBack_MEMORY_READ_DATA[4] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[5] writeBack_MEMORY_READ_DATA[5] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[6] writeBack_MEMORY_READ_DATA[6] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[7] writeBack_MEMORY_READ_DATA[7] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[8] writeBack_MEMORY_READ_DATA[8] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[9] writeBack_MEMORY_READ_DATA[9] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[10] writeBack_MEMORY_READ_DATA[10] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[11] writeBack_MEMORY_READ_DATA[11] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[12] writeBack_MEMORY_READ_DATA[12] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[13] writeBack_MEMORY_READ_DATA[13] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[14] writeBack_MEMORY_READ_DATA[14] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[15] writeBack_MEMORY_READ_DATA[15] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[16] writeBack_MEMORY_READ_DATA[16] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[17] writeBack_MEMORY_READ_DATA[17] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[18] writeBack_MEMORY_READ_DATA[18] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[19] writeBack_MEMORY_READ_DATA[19] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif deleted file mode 100644 index 2cdcc440f0a..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif +++ /dev/null @@ -1,34792 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model VexRiscv -.inputs dBus_cmd_ready dBus_rsp_valid dBus_rsp_payload_last dBus_rsp_payload_data[0] dBus_rsp_payload_data[1] dBus_rsp_payload_data[2] dBus_rsp_payload_data[3] dBus_rsp_payload_data[4] dBus_rsp_payload_data[5] dBus_rsp_payload_data[6] dBus_rsp_payload_data[7] dBus_rsp_payload_data[8] dBus_rsp_payload_data[9] dBus_rsp_payload_data[10] dBus_rsp_payload_data[11] dBus_rsp_payload_data[12] dBus_rsp_payload_data[13] dBus_rsp_payload_data[14] dBus_rsp_payload_data[15] dBus_rsp_payload_data[16] dBus_rsp_payload_data[17] dBus_rsp_payload_data[18] dBus_rsp_payload_data[19] dBus_rsp_payload_data[20] dBus_rsp_payload_data[21] dBus_rsp_payload_data[22] dBus_rsp_payload_data[23] dBus_rsp_payload_data[24] dBus_rsp_payload_data[25] dBus_rsp_payload_data[26] dBus_rsp_payload_data[27] dBus_rsp_payload_data[28] dBus_rsp_payload_data[29] dBus_rsp_payload_data[30] dBus_rsp_payload_data[31] dBus_rsp_payload_error timerInterrupt externalInterrupt softwareInterrupt debug_bus_cmd_valid debug_bus_cmd_payload_wr debug_bus_cmd_payload_address[0] debug_bus_cmd_payload_address[1] debug_bus_cmd_payload_address[2] debug_bus_cmd_payload_address[3] debug_bus_cmd_payload_address[4] debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[6] debug_bus_cmd_payload_address[7] debug_bus_cmd_payload_data[0] debug_bus_cmd_payload_data[1] debug_bus_cmd_payload_data[2] debug_bus_cmd_payload_data[3] debug_bus_cmd_payload_data[4] debug_bus_cmd_payload_data[5] debug_bus_cmd_payload_data[6] debug_bus_cmd_payload_data[7] debug_bus_cmd_payload_data[8] debug_bus_cmd_payload_data[9] debug_bus_cmd_payload_data[10] debug_bus_cmd_payload_data[11] debug_bus_cmd_payload_data[12] debug_bus_cmd_payload_data[13] debug_bus_cmd_payload_data[14] debug_bus_cmd_payload_data[15] debug_bus_cmd_payload_data[16] debug_bus_cmd_payload_data[17] debug_bus_cmd_payload_data[18] debug_bus_cmd_payload_data[19] debug_bus_cmd_payload_data[20] debug_bus_cmd_payload_data[21] debug_bus_cmd_payload_data[22] debug_bus_cmd_payload_data[23] debug_bus_cmd_payload_data[24] debug_bus_cmd_payload_data[25] debug_bus_cmd_payload_data[26] debug_bus_cmd_payload_data[27] debug_bus_cmd_payload_data[28] debug_bus_cmd_payload_data[29] debug_bus_cmd_payload_data[30] debug_bus_cmd_payload_data[31] iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_data[0] iBus_rsp_payload_data[1] iBus_rsp_payload_data[2] iBus_rsp_payload_data[3] iBus_rsp_payload_data[4] iBus_rsp_payload_data[5] iBus_rsp_payload_data[6] iBus_rsp_payload_data[7] iBus_rsp_payload_data[8] iBus_rsp_payload_data[9] iBus_rsp_payload_data[10] iBus_rsp_payload_data[11] iBus_rsp_payload_data[12] iBus_rsp_payload_data[13] iBus_rsp_payload_data[14] iBus_rsp_payload_data[15] iBus_rsp_payload_data[16] iBus_rsp_payload_data[17] iBus_rsp_payload_data[18] iBus_rsp_payload_data[19] iBus_rsp_payload_data[20] iBus_rsp_payload_data[21] iBus_rsp_payload_data[22] iBus_rsp_payload_data[23] iBus_rsp_payload_data[24] iBus_rsp_payload_data[25] iBus_rsp_payload_data[26] iBus_rsp_payload_data[27] iBus_rsp_payload_data[28] iBus_rsp_payload_data[29] iBus_rsp_payload_data[30] iBus_rsp_payload_data[31] iBus_rsp_payload_error clk reset debugReset -.outputs dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_uncached dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[1] dBus_cmd_payload_mask[2] dBus_cmd_payload_mask[3] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] dBus_cmd_payload_size[2] dBus_cmd_payload_last debug_bus_cmd_ready debug_bus_rsp_data[0] debug_bus_rsp_data[1] debug_bus_rsp_data[2] debug_bus_rsp_data[3] debug_bus_rsp_data[4] debug_bus_rsp_data[5] debug_bus_rsp_data[6] debug_bus_rsp_data[7] debug_bus_rsp_data[8] debug_bus_rsp_data[9] debug_bus_rsp_data[10] debug_bus_rsp_data[11] debug_bus_rsp_data[12] debug_bus_rsp_data[13] debug_bus_rsp_data[14] debug_bus_rsp_data[15] debug_bus_rsp_data[16] debug_bus_rsp_data[17] debug_bus_rsp_data[18] debug_bus_rsp_data[19] debug_bus_rsp_data[20] debug_bus_rsp_data[21] debug_bus_rsp_data[22] debug_bus_rsp_data[23] debug_bus_rsp_data[24] debug_bus_rsp_data[25] debug_bus_rsp_data[26] debug_bus_rsp_data[27] debug_bus_rsp_data[28] debug_bus_rsp_data[29] debug_bus_rsp_data[30] debug_bus_rsp_data[31] debug_resetOut iBus_cmd_valid iBus_cmd_payload_address[0] iBus_cmd_payload_address[1] iBus_cmd_payload_address[2] iBus_cmd_payload_address[3] iBus_cmd_payload_address[4] iBus_cmd_payload_address[5] iBus_cmd_payload_address[6] iBus_cmd_payload_address[7] iBus_cmd_payload_address[8] iBus_cmd_payload_address[9] iBus_cmd_payload_address[10] iBus_cmd_payload_address[11] iBus_cmd_payload_address[12] iBus_cmd_payload_address[13] iBus_cmd_payload_address[14] iBus_cmd_payload_address[15] iBus_cmd_payload_address[16] iBus_cmd_payload_address[17] iBus_cmd_payload_address[18] iBus_cmd_payload_address[19] iBus_cmd_payload_address[20] iBus_cmd_payload_address[21] iBus_cmd_payload_address[22] iBus_cmd_payload_address[23] iBus_cmd_payload_address[24] iBus_cmd_payload_address[25] iBus_cmd_payload_address[26] iBus_cmd_payload_address[27] iBus_cmd_payload_address[28] iBus_cmd_payload_address[29] iBus_cmd_payload_address[30] iBus_cmd_payload_address[31] iBus_cmd_payload_size[0] iBus_cmd_payload_size[1] iBus_cmd_payload_size[2] -.names $false -.names $true -1 -.names $undef -.names $abc$27210$new_n4092 $abc$27210$new_n3940 dBus_cmd_payload_address[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$21747 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n3941 $abc$27210$new_n3940 -10 1 -.names $abc$27210$new_n4089 $abc$27210$new_n3942 $abc$27210$new_n4084 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] $abc$27210$new_n3941 -10000 1 -10001 1 -10010 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names $abc$27210$new_n3943 $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] $abc$27210$new_n3942 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n8219 $abc$27210$new_n3988 $abc$27210$new_n8017 $abc$27210$new_n8034 $abc$27210$new_n3943 -1100 1 -.names MmuPlugin_ports_1_cache_2_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n3950 -01 1 -10 1 -.names $abc$27210$new_n7999 $abc$27210$new_n3963 MmuPlugin_ports_1_cache_2_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_2_superPage $abc$27210$new_n3956 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11100 1 -.names $abc$27210$new_n3964 MmuPlugin_ports_1_cache_2_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n3963 -100 1 -111 1 -.names MmuPlugin_ports_1_cache_2_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] $abc$27210$new_n3964 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names MmuPlugin_ports_1_cache_4_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_4_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n3971 -0000 1 -0011 1 -1100 1 -1111 1 -.names MmuPlugin_ports_1_cache_4_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n3972 -01 1 -10 1 -.names MmuPlugin_ports_1_cache_4_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n3980 -01 1 -10 1 -.names MmuPlugin_ports_1_cache_4_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n3983 -01 1 -10 1 -.names MmuPlugin_ports_1_cache_4_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n3985 -00 1 -11 1 -.names MmuPlugin_ports_1_cache_4_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n3987 -01 1 -10 1 -.names $abc$27210$new_n8203 $abc$27210$new_n8227 $abc$27210$new_n3988 -00 1 -.names $abc$27210$new_n8008 $abc$27210$new_n3997 MmuPlugin_ports_1_cache_3_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_3_superPage $abc$27210$new_n3990 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11100 1 -.names $abc$27210$new_n3995 MmuPlugin_ports_1_cache_3_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_3_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n3994 -10000 1 -10011 1 -11100 1 -11111 1 -.names MmuPlugin_ports_1_cache_3_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n3995 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names $abc$27210$new_n3998 MmuPlugin_ports_1_cache_3_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n3997 -100 1 -111 1 -.names MmuPlugin_ports_1_cache_3_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] $abc$27210$new_n3998 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names MmuPlugin_ports_1_cache_3_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4000 -01 1 -10 1 -.names MmuPlugin_ports_1_cache_3_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4005 -01 1 -10 1 -.names $abc$27210$new_n4015 $abc$27210$new_n4014 MmuPlugin_ports_1_cache_5_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4013 -1100 1 -1111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] MmuPlugin_ports_1_cache_5_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n4014 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names MmuPlugin_ports_1_cache_5_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_5_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n4015 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$27210$new_n4017 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_5_virtualAddress_0[2] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n4016 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names MmuPlugin_ports_1_cache_5_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4017 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names MmuPlugin_ports_1_cache_5_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4020 -00 1 -11 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_5_virtualAddress_1[6] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n4023 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names MmuPlugin_ports_1_cache_5_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4027 -10 1 -.names MmuPlugin_ports_1_cache_1_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n4033 -10 1 -.names $abc$27210$new_n4038 MmuPlugin_ports_1_cache_1_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_1_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4037 -10000 1 -10011 1 -11100 1 -11111 1 -.names MmuPlugin_ports_1_cache_1_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_1_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n4038 -0000 1 -0011 1 -1100 1 -1111 1 -.names MmuPlugin_ports_1_cache_1_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4046 -01 1 -10 1 -.names MmuPlugin_ports_1_cache_1_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_1_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4048 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$27210$new_n8034 $abc$27210$new_n8227 $abc$27210$new_n8219 $abc$27210$new_n8203 $abc$27210$new_n8017 $abc$27210$new_n4049 -00000 1 -.names MmuPlugin_ports_1_cache_4_valid MmuPlugin_ports_1_cache_4_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_4_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n4055 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4085 $abc$27210$new_n4084 -00 1 -.names $abc$27210$new_n4087 $abc$27210$new_n8034 $abc$27210$new_n4086 $abc$27210$new_n4085 -100 1 -.names $abc$27210$new_n8203 $abc$27210$new_n8017 $abc$27210$new_n4086 -00 1 -.names $abc$27210$new_n3988 $abc$27210$new_n8219 $abc$27210$new_n4087 -10 1 -.names $abc$27210$new_n4086 $abc$27210$new_n8034 $abc$27210$new_n8227 $abc$27210$new_n4088 -101 1 -110 1 -111 1 -.names $abc$27210$new_n4090 $abc$27210$new_n4087 $abc$27210$new_n4088 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] $abc$27210$new_n4089 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n4091 MmuPlugin_satp_mode CsrPlugin_mstatus_MPP[1] CsrPlugin_mstatus_MPP[0] $abc$27210$new_n4090 -11100 1 -11101 1 -11110 1 -.names MmuPlugin_status_mprv DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4091 -11000 1 -.names $abc$27210$new_n4093 dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4092 -00 1 -.names $abc$27210$new_n4094 $abc$27210$new_n4100 $abc$27210$new_n4093 -10 1 -.names $abc$27210$new_n4103 $abc$27210$new_n4095 $abc$27210$new_n4094 -11 1 -.names $abc$27210$new_n4096 dataCache_1.stageB_mmuRsp_refilling $abc$27210$new_n4095 -10 1 -.names MmuPlugin_dBusAccess_rsp_payload_error $abc$27210$new_n4102 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$new_n4096 -000 1 -001 1 -010 1 -.names $abc$27210$new_n4098 $abc$27210$new_n4102 dBus_cmd_payload_uncached dataCache_1.stageB_mmuRsp_isPaging MmuPlugin_dBusAccess_rsp_payload_error -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names $abc$27210$new_n4099 dBus_rsp_payload_error dBus_cmd_payload_uncached dBus_rsp_valid dBus_cmd_payload_wr $abc$27210$new_n4098 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n4100 dataCache_1.stageB_unaligned dataCache_1.stageB_tagsReadRsp_0_error dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4099 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names memory_to_writeBack_IS_DBUS_SHARING $abc$27210$new_n4101 $abc$27210$new_n4100 -00 1 -.names memory_to_writeBack_MEMORY_ENABLE lastStageIsValid $abc$27210$new_n4101 -11 1 -.names $abc$27210$new_n4100 dBus_cmd_payload_wr dataCache_1.stageB_mmuRsp_exception dataCache_1.stageB_mmuRsp_allowWrite dataCache_1.stageB_mmuRsp_allowRead $abc$27210$new_n4102 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names dBus_cmd_payload_wr dBus_cmd_payload_uncached dBus_cmd_ready dBus_rsp_valid dataCache_1.stageB_waysHit $abc$27210$new_n4103 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names dBus_cmd_payload_wr dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4100 dBus_cmd_payload_size[2] -0000 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4106 dBus_cmd_payload_address[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$21749 -001 1 -011 1 -100 1 -101 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4107 $abc$27210$new_n4090 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] $abc$27210$new_n4106 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$27210$new_n4108 $abc$27210$new_n3943 $abc$27210$new_n4084 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] $abc$27210$new_n4109 $abc$27210$new_n4107 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] $abc$27210$new_n4108 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] $abc$27210$new_n4109 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4111 dBus_cmd_payload_address[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$21751 -001 1 -011 1 -100 1 -101 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4112 $abc$27210$new_n4090 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] $abc$27210$new_n4111 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$27210$new_n4113 $abc$27210$new_n3943 $abc$27210$new_n4084 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] $abc$27210$new_n4114 $abc$27210$new_n4112 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] $abc$27210$new_n4113 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] $abc$27210$new_n4114 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4116 dBus_cmd_payload_address[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$21753 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4090 $abc$27210$new_n4117 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4116 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4120 $abc$27210$new_n4118 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] $abc$27210$new_n4117 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] $abc$27210$new_n4119 $abc$27210$new_n4118 -1000 1 -1010 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] $abc$27210$new_n4119 -000 1 -010 1 -100 1 -101 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] $abc$27210$new_n4120 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4122 dBus_cmd_payload_address[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$21755 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4090 $abc$27210$new_n4123 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n4122 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4126 $abc$27210$new_n4124 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] $abc$27210$new_n4123 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] $abc$27210$new_n4125 $abc$27210$new_n4124 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] $abc$27210$new_n4125 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] $abc$27210$new_n4126 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4128 dBus_cmd_payload_address[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$21757 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4090 $abc$27210$new_n4129 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n4128 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4132 $abc$27210$new_n4130 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] $abc$27210$new_n4129 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] $abc$27210$new_n4131 $abc$27210$new_n4130 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] $abc$27210$new_n4131 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] $abc$27210$new_n4132 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4134 dBus_cmd_payload_address[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$21759 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4090 $abc$27210$new_n4135 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n4134 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4138 $abc$27210$new_n4136 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] $abc$27210$new_n4135 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] $abc$27210$new_n4137 $abc$27210$new_n4136 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] $abc$27210$new_n4137 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] $abc$27210$new_n4138 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4140 dBus_cmd_payload_address[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$21761 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4090 $abc$27210$new_n4141 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4140 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4144 $abc$27210$new_n4142 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] $abc$27210$new_n4141 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] $abc$27210$new_n4143 $abc$27210$new_n4142 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] $abc$27210$new_n4143 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] $abc$27210$new_n4144 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4146 dBus_cmd_payload_address[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$21763 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4090 $abc$27210$new_n4147 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n4146 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4150 $abc$27210$new_n4148 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] $abc$27210$new_n4147 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] $abc$27210$new_n4149 $abc$27210$new_n4148 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] $abc$27210$new_n4149 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] $abc$27210$new_n4150 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4152 dBus_cmd_payload_address[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$21765 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4153 $abc$27210$new_n4157 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n4152 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4090 $abc$27210$new_n4156 $abc$27210$new_n4154 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_superPage $abc$27210$new_n4153 -10000 1 -10001 1 -10010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_superPage $abc$27210$new_n4155 $abc$27210$new_n4154 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_superPage MmuPlugin_ports_1_cache_5_superPage $abc$27210$new_n4155 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_superPage MmuPlugin_ports_1_cache_3_superPage $abc$27210$new_n4156 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4160 $abc$27210$new_n4158 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[9] $abc$27210$new_n4157 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[9] $abc$27210$new_n4159 $abc$27210$new_n4158 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[9] MmuPlugin_ports_1_cache_5_physicalAddress_0[9] $abc$27210$new_n4159 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[9] MmuPlugin_ports_1_cache_3_physicalAddress_0[9] $abc$27210$new_n4160 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4162 dBus_cmd_payload_address[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$21767 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4153 $abc$27210$new_n4163 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4162 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4166 $abc$27210$new_n4164 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[8] $abc$27210$new_n4163 -0000 1 -0001 1 -0010 1 -.names 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$abc$27210$new_n4265 lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n4258 -11000 1 -11001 1 -11010 1 -.names $abc$27210$new_n4262 DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_arbitration_isValid decode_to_execute_DO_EBREAK dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4259 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_isStuck -01 1 -10 1 -11 1 -.names execute_to_memory_IS_DIV memory_arbitration_isValid memory_DivPlugin_div_done $abc$27210$new_n4261 -110 1 -.names $abc$27210$new_n4263 decode_to_execute_MEMORY_MANAGMENT execute_arbitration_isValid dataCache_1.stageB_flusher_waitDone $abc$27210$new_n4262 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4264 memory_arbitration_isValid lastStageIsValid $abc$27210$new_n4263 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$27210$new_n4264 -11 1 -.names $abc$27210$new_n4266 $abc$27210$new_n4305 $abc$27210$new_n4291 $abc$27210$new_n4316 $abc$27210$new_n4313 $abc$27210$new_n4265 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n8213 IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.decodeStage_hit_tags_0_error $abc$27210$new_n4266 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4270 -10 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] $abc$27210$new_n4272 -01 1 -10 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] $abc$27210$new_n4274 -10 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] $abc$27210$new_n4275 -10 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] $abc$27210$new_n4279 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4280 -10 1 -.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid execute_to_memory_BYPASSABLE_MEMORY_STAGE $abc$27210$new_n4292 $abc$27210$new_n4291 -1100 1 -.names $abc$27210$new_n4298 $abc$27210$new_n4300 $abc$27210$new_n4304 $abc$27210$new_n8023 $abc$27210$new_n4303 $abc$27210$new_n4292 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n4299 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4298 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4299 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names $abc$27210$new_n4302 $abc$27210$new_n4301 execute_to_memory_INSTRUCTION[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4300 -1100 1 -1111 1 -.names execute_to_memory_INSTRUCTION[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] execute_to_memory_INSTRUCTION[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4301 -0000 1 -0011 1 -1100 1 -1111 1 -.names execute_to_memory_INSTRUCTION[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] execute_to_memory_INSTRUCTION[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4302 -0000 1 -0011 1 -1100 1 -1111 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4303 -11 1 -.names _zz__zz_decode_IS_CSR_41 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n4304 -10 1 -.names decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid decode_to_execute_BYPASSABLE_EXECUTE_STAGE $abc$27210$new_n4306 $abc$27210$new_n4305 -1100 1 -.names $abc$27210$new_n4298 $abc$27210$new_n4307 $abc$27210$new_n4304 $abc$27210$new_n4310 $abc$27210$new_n4303 $abc$27210$new_n4306 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n4309 $abc$27210$new_n4308 _zz__zz_execute_BranchPlugin_branch_src2_4[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4307 -1100 1 -1111 1 -.names _zz_execute_BranchPlugin_branch_src2_10 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4308 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz__zz_execute_BranchPlugin_branch_src2_4[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] _zz__zz_execute_BranchPlugin_branch_src2_4[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4309 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$27210$new_n4312 $abc$27210$new_n4311 _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n4310 -1100 1 -1111 1 -.names _zz__zz_execute_BranchPlugin_branch_src2_4[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] _zz__zz_execute_BranchPlugin_branch_src2_4[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4311 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz_execute_BranchPlugin_branch_src2_10 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] _zz__zz_execute_BranchPlugin_branch_src2_4[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4312 -0000 1 -0011 1 -1100 1 -1111 1 -.names when_MmuPlugin_l281_1 $abc$27210$new_n4314 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4315 $abc$27210$new_n4313 -1100 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4314 -00 1 -.names MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[1] $abc$27210$new_n4315 -000 1 -.names CsrPlugin_interrupt_valid DebugPlugin_haltIt DebugPlugin_stepIt $abc$27210$new_n4316 -100 1 -.names $abc$27210$new_n4318 $abc$27210$new_n4319 IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] $abc$27210$new_n4317 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[2] $abc$27210$new_n4318 -00 1 -01 1 -11 1 -.names _zz_memory_ENV_CTRL memory_arbitration_isValid _zz_execute_ENV_CTRL execute_arbitration_isValid $abc$27210$new_n4319 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names debug_bus_cmd_payload_address[2] $abc$27210$new_n4321 debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[4] $abc$27210$new_n4320 -1100 1 -.names debug_bus_cmd_payload_wr debug_bus_cmd_valid debug_bus_cmd_payload_address[7] debug_bus_cmd_payload_address[6] debug_bus_cmd_payload_address[3] $abc$27210$new_n4321 -11000 1 -.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n4258 $abc$27210$new_n4320 $abc$27210$auto$rtlil.cc:2693:MuxGate$21837 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4324 $abc$27210$new_n4390 MmuPlugin_shared_state_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21839 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n4325 $abc$27210$new_n4329 $abc$27210$new_n4315 $abc$27210$new_n4324 -100 1 -110 1 -111 1 -.names MmuPlugin_shared_state_1[0] MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_state_1[2] $abc$27210$new_n4326 MmuPlugin_shared_state_1[1] $abc$27210$new_n4325 -00000 1 -00010 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4259 $abc$27210$new_n4327 dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4326 -110 1 -.names $abc$27210$new_n4328 execute_arbitration_isValid memory_arbitration_isValid lastStageIsValid $abc$27210$new_n4318 $abc$27210$new_n4327 -10000 1 -.names CsrPlugin_exceptionPendings_3 CsrPlugin_exceptionPendings_2 CsrPlugin_exceptionPendings_1 $abc$27210$new_n4328 -000 1 -.names $abc$27210$new_n4090 $abc$27210$new_n8224 execute_to_memory_MEMORY_ENABLE memory_arbitration_isValid $abc$27210$new_n4329 -1111 1 -.names MmuPlugin_ports_1_cache_3_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n4005 $abc$27210$new_n4000 $abc$27210$new_n4333 -0000 1 -1100 1 -.names MmuPlugin_ports_1_cache_2_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_2_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n3950 $abc$27210$new_n4359 -00000 1 -00110 1 -11000 1 -11110 1 -.names MmuPlugin_ports_1_cache_2_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_2_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4362 -0000 1 -0011 1 -1100 1 -1111 1 -.names MmuPlugin_ports_1_cache_2_valid MmuPlugin_ports_1_cache_2_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n4363 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names MmuPlugin_ports_1_cache_4_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] $abc$27210$new_n4368 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names $abc$27210$new_n3987 $abc$27210$new_n3980 $abc$27210$new_n3983 $abc$27210$new_n4369 -000 1 -.names $abc$27210$new_n4371 $abc$27210$new_n4377 MmuPlugin_ports_1_cache_0_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_ports_1_cache_0_superPage $abc$27210$new_n4370 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11100 1 -.names $abc$27210$new_n4375 $abc$27210$new_n4372 MmuPlugin_ports_1_cache_0_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n4371 -1100 1 -1111 1 -.names $abc$27210$new_n4373 MmuPlugin_ports_1_cache_0_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_0_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4372 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_ports_1_cache_0_virtualAddress_0[6] $abc$27210$new_n4374 MmuPlugin_ports_1_cache_0_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4373 -00000 1 -00010 1 -00011 1 -11000 1 -11010 1 -11011 1 -.names MmuPlugin_ports_1_cache_0_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n4374 -10 1 -.names $abc$27210$new_n4376 MmuPlugin_ports_1_cache_0_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] $abc$27210$new_n4375 -100 1 -111 1 -.names MmuPlugin_ports_1_cache_0_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_0_virtualAddress_0[0] $abc$27210$new_n4376 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names MmuPlugin_ports_1_cache_0_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_0_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n4378 $abc$27210$new_n4377 -00000 1 -00110 1 -11000 1 -11110 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_0_virtualAddress_0[5] $abc$27210$new_n4378 -10 1 -.names MmuPlugin_ports_1_cache_0_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n4387 -0000 1 -0001 1 -0011 1 -1100 1 -1101 1 -1111 1 -.names MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] MmuPlugin_shared_dBusRspStaged_payload_redo $abc$27210$new_n4391 $abc$27210$new_n4390 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRspStaged_payload_error MmuPlugin_shared_dBusRsp_pte_W MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRsp_pte_X $abc$27210$new_n4391 -10000 1 -.names $abc$27210$new_n4324 $abc$27210$new_n4393 MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21841 -001 1 -011 1 -100 1 -101 1 -.names MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[1] $abc$27210$new_n4391 $abc$27210$new_n4393 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] $abc$27210$new_n4395 $abc$27210$new_n4442 $abc$27210$auto$rtlil.cc:2693:MuxGate$21945 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$27210$new_n4421 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 $abc$27210$new_n4423 $abc$27210$new_n4395 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names _zz_6 $abc$27210$new_n4417 $abc$27210$new_n4419 $abc$27210$new_n4397 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4396 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -11110 1 -.names $abc$27210$new_n4416 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4398 $abc$27210$new_n4397 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 $abc$27210$new_n4398 -00100 1 -00110 1 -00111 1 -11010 1 -.names $abc$27210$new_n4415 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$new_n4400 $abc$27210$new_n4399 -00000 1 -00001 1 -00011 1 -00101 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11011 1 -11101 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4401 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4400 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11010 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4402 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4401 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4403 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4402 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11010 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n4404 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$new_n4403 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4405 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4404 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4406 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4405 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4407 _zz_6 _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4406 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4408 _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n4407 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$new_n4409 $abc$27210$new_n4408 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$new_n4410 $abc$27210$new_n4409 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$new_n4411 $abc$27210$new_n4410 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4412 IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4411 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4413 IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4412 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11010 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] $abc$27210$new_n4413 -1001 1 -1011 1 -1110 1 -1111 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4414 -0010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] _zz_6 $abc$27210$new_n4415 -000 1 -010 1 -100 1 -101 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4416 -000 1 -001 1 -010 1 -011 1 -100 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4417 -01 1 -10 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4419 -011 1 -100 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4436 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[30] $abc$27210$new_n4421 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4434 $abc$27210$new_n4423 $abc$27210$new_n4422 -00 1 -.names $abc$27210$new_n4431 $abc$27210$new_n4424 $abc$27210$new_n4428 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n4423 -11000 1 -11001 1 -11010 1 -.names $abc$27210$new_n4425 $abc$27210$new_n4266 $abc$27210$new_n4424 -00 1 -.names _zz_10 $abc$27210$new_n4427 $abc$27210$new_n4414 $abc$27210$new_n4425 -000 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] _zz_10 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_PREDICTION_CONTEXT_line_history_2[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4427 -1100 1 -.names $abc$27210$new_n4101 MmuPlugin_dBusAccess_rsp_payload_redo $abc$27210$new_n4428 -11 1 -.names $abc$27210$new_n4430 $abc$27210$new_n4100 dataCache_1.io_cpu_execute_refilling dataCache_1.loader_valid_regNext MmuPlugin_dBusAccess_rsp_payload_redo -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -1010 1 -1110 1 -.names dataCache_1.stageB_mmuRsp_refilling dataCache_1.stageB_waysHit dataCache_1.stageB_dataColisions dBus_cmd_payload_wr dBus_cmd_payload_uncached $abc$27210$new_n4430 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$27210$new_n4432 lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n4431 -100 1 -101 1 -110 1 -.names CsrPlugin_hadException $abc$27210$new_n4433 $abc$27210$new_n4432 -00 1 -.names $abc$27210$new_n4316 CsrPlugin_pipelineLiberator_pcValids_2 $abc$27210$new_n4328 CsrPlugin_hadException $abc$27210$new_n4433 -1110 1 -.names $abc$27210$new_n4428 $abc$27210$new_n4431 execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n4434 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n4424 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n4435 -10000 1 -10001 1 -10010 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[30] $abc$27210$new_n4437 CsrPlugin_mepc[30] $abc$27210$new_n4438 $abc$27210$new_n4436 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n4437 -1110 1 -.names _zz_writeBack_ENV_CTRL _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] lastStageIsValid $abc$27210$new_n4438 -1111 1 -.names IBusCachedPlugin_fetchPc_booted $abc$27210$new_n4435 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n4441 $abc$27210$new_n4439 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n4258 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.decodeStage_hit_tags_0_error IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 -1000 1 -1001 1 -1010 1 -.names IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$new_n8213 $abc$27210$new_n4441 -10 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4443 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4442 -1000 1 -1001 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] $abc$27210$new_n4444 $abc$27210$new_n4443 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] $abc$27210$new_n4445 $abc$27210$new_n4444 -11111 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] $abc$27210$new_n4446 $abc$27210$new_n4445 -111 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] $abc$27210$new_n4447 $abc$27210$new_n4446 -11111 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] $abc$27210$new_n4448 $abc$27210$new_n4447 -11111 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] $abc$27210$new_n4449 $abc$27210$new_n4448 -11111 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] $abc$27210$new_n4450 $abc$27210$new_n4449 -111 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] $abc$27210$new_n4451 $abc$27210$new_n4450 -111 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] $abc$27210$new_n4452 $abc$27210$new_n4451 -111 1 -.names IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] $abc$27210$new_n4452 -111 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] $abc$27210$new_n4454 $abc$27210$new_n4458 $abc$27210$auto$rtlil.cc:2693:MuxGate$21947 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$27210$new_n4456 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4455 $abc$27210$new_n4423 $abc$27210$new_n4454 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names _zz_6 $abc$27210$new_n4397 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n4455 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4457 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[29] $abc$27210$new_n4456 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[29] $abc$27210$new_n4437 CsrPlugin_mepc[29] $abc$27210$new_n4438 $abc$27210$new_n4457 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4459 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4458 -1000 1 -1001 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] $abc$27210$new_n4444 $abc$27210$new_n4459 -011 1 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] $abc$27210$new_n4461 $abc$27210$new_n4465 $abc$27210$auto$rtlil.cc:2693:MuxGate$21949 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$27210$new_n4463 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[28] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[28] $abc$27210$new_n4461 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[28] -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4464 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[28] $abc$27210$new_n4463 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names CsrPlugin_mepc[28] $abc$27210$new_n4438 $abc$27210$new_n4464 -11 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4444 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n4465 -10000 1 -10001 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] $abc$27210$new_n4467 $abc$27210$new_n4471 $abc$27210$auto$rtlil.cc:2693:MuxGate$21951 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$27210$new_n4469 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[27] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[27] $abc$27210$new_n4467 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[27] -0010 1 -0100 1 -0101 1 -0111 1 -1001 1 -1100 1 -1110 1 -1111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4470 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[27] $abc$27210$new_n4469 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names CsrPlugin_mepc[27] $abc$27210$new_n4438 $abc$27210$new_n4470 -11 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4472 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4471 -1000 1 -1001 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] $abc$27210$new_n4445 $abc$27210$new_n4472 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] $abc$27210$new_n4474 $abc$27210$new_n4478 $abc$27210$auto$rtlil.cc:2693:MuxGate$21953 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$27210$new_n4476 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[26] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[26] $abc$27210$new_n4474 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4417 $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[26] -00 1 -11 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4477 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[26] $abc$27210$new_n4476 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names CsrPlugin_mepc[26] $abc$27210$new_n4438 $abc$27210$new_n4477 -11 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4479 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4478 -1000 1 -1001 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] $abc$27210$new_n4445 $abc$27210$new_n4479 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] $abc$27210$new_n4481 $abc$27210$new_n4485 $abc$27210$auto$rtlil.cc:2693:MuxGate$21955 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$27210$new_n4483 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[25] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[25] $abc$27210$new_n4481 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4416 $abc$27210$new_n4398 IBusCachedPlugin_predictionJumpInterface_payload[25] -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -10010 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4484 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[25] $abc$27210$new_n4483 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names CsrPlugin_mepc[25] $abc$27210$new_n4438 $abc$27210$new_n4484 -11 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4486 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4485 -1000 1 -1001 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] $abc$27210$new_n4445 $abc$27210$new_n4486 -011 1 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] $abc$27210$new_n4488 $abc$27210$new_n4492 $abc$27210$auto$rtlil.cc:2693:MuxGate$21957 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$27210$new_n4490 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[24] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[24] $abc$27210$new_n4488 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4416 $abc$27210$new_n4398 IBusCachedPlugin_predictionJumpInterface_payload[24] -0000 1 -0001 1 -0011 1 -0110 1 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4491 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[24] $abc$27210$new_n4490 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names CsrPlugin_mepc[24] $abc$27210$new_n4438 $abc$27210$new_n4491 -11 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4445 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4492 -10000 1 -10001 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] $abc$27210$new_n4494 $abc$27210$new_n4498 $abc$27210$auto$rtlil.cc:2693:MuxGate$21959 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$27210$new_n4496 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[23] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[23] $abc$27210$new_n4494 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[23] -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4497 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[23] $abc$27210$new_n4496 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names CsrPlugin_mepc[23] $abc$27210$new_n4438 $abc$27210$new_n4497 -11 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4499 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$new_n4498 -1000 1 -1001 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n4446 $abc$27210$new_n4499 -011 1 -100 1 -101 1 -110 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[22] -0010 1 -0100 1 -0101 1 -0111 1 -1001 1 -1100 1 -1110 1 -1111 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[22] $abc$27210$new_n4437 CsrPlugin_mepc[22] $abc$27210$new_n4438 $abc$27210$new_n4504 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n4446 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4505 -10000 1 -10001 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[21] -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[21] $abc$27210$new_n4437 CsrPlugin_mepc[21] $abc$27210$new_n4438 $abc$27210$new_n4510 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4512 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4511 -1000 1 -1001 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] $abc$27210$new_n4447 $abc$27210$new_n4512 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4415 $abc$27210$new_n4400 IBusCachedPlugin_predictionJumpInterface_payload[20] -00000 1 -00100 1 -00101 1 -00110 1 -01001 1 -01010 1 -01011 1 -01111 1 -10001 1 -10010 1 -10011 1 -10111 1 -11000 1 -11100 1 -11101 1 -11110 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[20] $abc$27210$new_n4437 CsrPlugin_mepc[20] $abc$27210$new_n4438 $abc$27210$new_n4517 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4415 $abc$27210$new_n4400 IBusCachedPlugin_predictionJumpInterface_payload[19] -001 1 -010 1 -100 1 -111 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[19] $abc$27210$new_n4437 CsrPlugin_mepc[19] $abc$27210$new_n4438 $abc$27210$new_n4524 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4401 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] IBusCachedPlugin_predictionJumpInterface_payload[18] -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01110 1 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[18] $abc$27210$new_n4437 CsrPlugin_mepc[18] $abc$27210$new_n4438 $abc$27210$new_n4531 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n4447 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4532 -10000 1 -10001 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4402 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] IBusCachedPlugin_predictionJumpInterface_payload[17] -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[17] $abc$27210$new_n4437 CsrPlugin_mepc[17] $abc$27210$new_n4438 $abc$27210$new_n4537 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4539 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4538 -1000 1 -1001 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] $abc$27210$new_n4448 $abc$27210$new_n4539 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4403 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] IBusCachedPlugin_predictionJumpInterface_payload[16] -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01110 1 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[16] $abc$27210$new_n4437 CsrPlugin_mepc[16] $abc$27210$new_n4438 $abc$27210$new_n4544 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n4404 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] IBusCachedPlugin_predictionJumpInterface_payload[15] -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[15] $abc$27210$new_n4437 CsrPlugin_mepc[15] $abc$27210$new_n4438 $abc$27210$new_n4551 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4405 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_predictionJumpInterface_payload[14] -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[14] $abc$27210$new_n4437 CsrPlugin_mepc[14] $abc$27210$new_n4438 $abc$27210$new_n4558 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n4448 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4559 -10000 1 -10001 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4406 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_predictionJumpInterface_payload[13] -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[13] $abc$27210$new_n4437 CsrPlugin_mepc[13] $abc$27210$new_n4438 $abc$27210$new_n4564 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4566 $abc$27210$new_n4565 -1000 1 -1010 1 -1100 1 -1101 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] $abc$27210$new_n4449 $abc$27210$new_n4566 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4407 $abc$27210$new_n4414 _zz_6 _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_predictionJumpInterface_payload[12] -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[12] $abc$27210$new_n4437 CsrPlugin_mepc[12] $abc$27210$new_n4438 $abc$27210$new_n4571 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4575 $abc$27210$new_n4578 IBusCachedPlugin_predictionJumpInterface_payload[11] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4576 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[11] $abc$27210$new_n4575 -000 1 -001 1 -010 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[11] $abc$27210$new_n4437 CsrPlugin_mepc[11] $abc$27210$new_n4438 $abc$27210$new_n4576 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4408 $abc$27210$new_n4414 _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_predictionJumpInterface_payload[11] -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n4449 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4578 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21983 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4581 $abc$27210$new_n4584 IBusCachedPlugin_predictionJumpInterface_payload[10] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4582 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[10] $abc$27210$new_n4581 -000 1 -001 1 -010 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[10] $abc$27210$new_n4437 CsrPlugin_mepc[10] $abc$27210$new_n4438 $abc$27210$new_n4582 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4409 IBusCachedPlugin_predictionJumpInterface_payload[10] -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n4449 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$new_n4584 -0000 1 -0001 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21985 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4587 $abc$27210$new_n4590 IBusCachedPlugin_predictionJumpInterface_payload[9] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4588 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[9] $abc$27210$new_n4587 -000 1 -001 1 -010 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[9] $abc$27210$new_n4437 CsrPlugin_mepc[9] $abc$27210$new_n4438 $abc$27210$new_n4588 -10011 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4409 IBusCachedPlugin_predictionJumpInterface_payload[9] -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$new_n4450 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4590 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21987 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4593 $abc$27210$new_n4596 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] -000 1 -001 1 -100 1 -110 1 -.names $abc$27210$new_n4434 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[8] $abc$27210$new_n4595 DBusCachedPlugin_redoBranch_payload[8] $abc$27210$new_n4593 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4410 IBusCachedPlugin_predictionJumpInterface_payload[8] -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names BranchPlugin_branchExceptionPort_payload_badAddr[8] $abc$27210$new_n4437 CsrPlugin_mepc[8] $abc$27210$new_n4438 $abc$27210$new_n4595 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$new_n4450 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$new_n4596 -0000 1 -0001 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21989 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4599 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4602 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n4434 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[7] $abc$27210$new_n4601 DBusCachedPlugin_redoBranch_payload[7] $abc$27210$new_n4599 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4410 IBusCachedPlugin_predictionJumpInterface_payload[7] -000 1 -011 1 -101 1 -110 1 -.names BranchPlugin_branchExceptionPort_payload_badAddr[7] $abc$27210$new_n4437 CsrPlugin_mepc[7] $abc$27210$new_n4438 $abc$27210$new_n4601 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$new_n4451 $abc$27210$new_n4602 -011 1 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21991 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4605 $abc$27210$new_n4608 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] -010 1 -011 1 -100 1 -110 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4606 IBusCachedPlugin_predictionJumpInterface_payload[6] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[6] $abc$27210$new_n4605 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[6] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[6] $abc$27210$new_n4606 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4411 IBusCachedPlugin_predictionJumpInterface_payload[6] -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$new_n4451 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$new_n4608 -0000 1 -0001 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21993 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4611 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4614 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4612 IBusCachedPlugin_predictionJumpInterface_payload[5] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[5] $abc$27210$new_n4611 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[5] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[5] $abc$27210$new_n4612 -10000 1 -10001 1 -10011 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4411 IBusCachedPlugin_predictionJumpInterface_payload[5] -000 1 -011 1 -101 1 -110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$new_n4452 $abc$27210$new_n4614 -011 1 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21995 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4617 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4620 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4618 IBusCachedPlugin_predictionJumpInterface_payload[4] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[4] $abc$27210$new_n4617 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[4] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[4] $abc$27210$new_n4618 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4412 $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_predictionJumpInterface_payload[4] -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$new_n4452 $abc$27210$new_n4620 -01 1 -10 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21997 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4623 $abc$27210$new_n4626 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[3] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4624 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[3] $abc$27210$new_n4623 -000 1 -001 1 -011 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[3] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[3] $abc$27210$new_n4624 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4413 $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] IBusCachedPlugin_predictionJumpInterface_payload[3] -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01110 1 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4626 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21999 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4629 $abc$27210$new_n4632 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[2] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4630 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[2] $abc$27210$new_n4629 -000 1 -001 1 -011 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[2] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[2] $abc$27210$new_n4630 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_predictionJumpInterface_payload[2] -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4632 -0000 1 -0001 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22001 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[30] DBusCachedPlugin_redoBranch_payload[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22969 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4636 $abc$27210$new_n4093 $abc$27210$new_n4635 -00 1 -.names $abc$27210$new_n4428 $abc$27210$new_n4637 CsrPlugin_exceptionPendings_3 $abc$27210$new_n4636 -001 1 -010 1 -011 1 -.names $abc$27210$new_n4101 $abc$27210$new_n4096 $abc$27210$new_n4637 -10 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[29] DBusCachedPlugin_redoBranch_payload[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22971 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[28] DBusCachedPlugin_redoBranch_payload[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22973 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[27] DBusCachedPlugin_redoBranch_payload[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22975 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[26] DBusCachedPlugin_redoBranch_payload[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22977 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[25] DBusCachedPlugin_redoBranch_payload[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22979 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[24] DBusCachedPlugin_redoBranch_payload[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22981 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[23] DBusCachedPlugin_redoBranch_payload[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22983 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[22] DBusCachedPlugin_redoBranch_payload[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22985 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[21] DBusCachedPlugin_redoBranch_payload[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22987 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[20] DBusCachedPlugin_redoBranch_payload[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22989 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[19] DBusCachedPlugin_redoBranch_payload[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22991 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[18] DBusCachedPlugin_redoBranch_payload[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22993 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[17] DBusCachedPlugin_redoBranch_payload[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22995 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[16] DBusCachedPlugin_redoBranch_payload[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22997 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[15] DBusCachedPlugin_redoBranch_payload[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22999 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[14] DBusCachedPlugin_redoBranch_payload[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23001 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[13] DBusCachedPlugin_redoBranch_payload[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23003 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[12] DBusCachedPlugin_redoBranch_payload[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23005 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[9] DBusCachedPlugin_redoBranch_payload[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23007 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[8] DBusCachedPlugin_redoBranch_payload[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23009 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[7] DBusCachedPlugin_redoBranch_payload[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23011 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[6] DBusCachedPlugin_redoBranch_payload[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23013 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[5] DBusCachedPlugin_redoBranch_payload[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23015 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[4] DBusCachedPlugin_redoBranch_payload[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23017 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[3] DBusCachedPlugin_redoBranch_payload[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23019 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[2] DBusCachedPlugin_redoBranch_payload[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23021 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[1] DBusCachedPlugin_redoBranch_payload[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23023 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[0] DBusCachedPlugin_redoBranch_payload[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23025 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] iBus_cmd_payload_address[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23027 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] iBus_cmd_payload_address[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23029 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] iBus_cmd_payload_address[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23031 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] iBus_cmd_payload_address[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23033 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] iBus_cmd_payload_address[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23035 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] iBus_cmd_payload_address[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23037 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] iBus_cmd_payload_address[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23039 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] iBus_cmd_payload_address[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23041 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] iBus_cmd_payload_address[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23043 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] iBus_cmd_payload_address[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23045 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] iBus_cmd_payload_address[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23047 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] iBus_cmd_payload_address[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23049 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] iBus_cmd_payload_address[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23051 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] iBus_cmd_payload_address[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23053 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] iBus_cmd_payload_address[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23055 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] iBus_cmd_payload_address[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23057 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] iBus_cmd_payload_address[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23059 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] iBus_cmd_payload_address[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23061 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] iBus_cmd_payload_address[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23063 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] iBus_cmd_payload_address[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23065 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] iBus_cmd_payload_address[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23067 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] iBus_cmd_payload_address[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23069 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] iBus_cmd_payload_address[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23071 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] iBus_cmd_payload_address[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23073 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] iBus_cmd_payload_address[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23075 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] iBus_cmd_payload_address[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23077 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.lineLoader_address[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23079 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache.lineLoader_address[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23081 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.lineLoader_address[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23083 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] DBusCachedPlugin_exceptionBus_payload_badAddr[30] $abc$27210$new_n4744 $abc$27210$auto$rtlil.cc:2693:MuxGate$23085 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4697 $abc$27210$new_n8208 $abc$27210$new_n4696 -10 1 -.names $abc$27210$new_n4699 $abc$27210$new_n4698 $abc$27210$new_n4697 -10 1 -.names $abc$27210$new_n4637 MmuPlugin_dBusAccess_rsp_payload_redo $abc$27210$new_n4698 -10 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 $abc$27210$new_n4699 -00 1 -.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_error IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_iBusRsp_readyForError $abc$27210$new_n8213 $abc$27210$new_n4700 -1111 1 -.names execute_to_memory_BRANCH_DO BranchPlugin_branchExceptionPort_payload_badAddr[1] memory_arbitration_isValid $abc$27210$new_n4701 -111 1 -.names $abc$27210$new_n4710 $abc$27210$new_n4706 $abc$27210$new_n4708 $abc$27210$new_n4715 $abc$27210$new_n4714 $abc$27210$new_n4705 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4707 $abc$27210$new_n4706 -1111 1 -.names _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] $abc$27210$new_n4707 -00000 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n4709 IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4708 -110 1 -.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4709 -00 1 -.names $abc$27210$new_n4711 $abc$27210$new_n4713 $abc$27210$new_n4712 _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4710 -1110 1 -.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4711 -000 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4712 -110 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4713 -000 1 -.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4714 -00 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4715 -10 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4721 -11000 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4722 -1100 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4723 -1000 1 -1010 1 -1011 1 -.names $abc$27210$new_n4726 $abc$27210$new_n4729 $abc$27210$new_n4728 IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4725 -1110 1 -.names $abc$27210$new_n4727 _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4726 -11000 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4727 -10 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4728 -1111 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4729 -0000 1 -.names $abc$27210$new_n4709 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n4732 $abc$27210$new_n4733 IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4731 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4732 -1000 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4733 -1000 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4735 -00000 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n4736 -0000 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4740 -1110 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4744 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] DBusCachedPlugin_exceptionBus_payload_badAddr[29] $abc$27210$new_n4746 $abc$27210$auto$rtlil.cc:2693:MuxGate$23087 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4746 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4752 $abc$27210$new_n4698 $abc$27210$new_n4751 -10 1 -.names $abc$27210$new_n4700 $abc$27210$new_n4701 $abc$27210$new_n4752 -10 1 -.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4272 $abc$27210$new_n4270 $abc$27210$new_n4761 -10000 1 -11100 1 -.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4763 -0000 1 -0001 1 -0011 1 -1100 1 -1101 1 -1111 1 -.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] $abc$27210$new_n4764 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] DBusCachedPlugin_exceptionBus_payload_badAddr[26] $abc$27210$new_n4771 $abc$27210$auto$rtlil.cc:2693:MuxGate$23093 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$new_n4771 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] $abc$27210$new_n4773 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23095 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4774 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4773 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[25] BranchPlugin_branchExceptionPort_payload_badAddr[25] $abc$27210$new_n4701 $abc$27210$new_n4774 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] DBusCachedPlugin_exceptionBus_payload_badAddr[24] $abc$27210$new_n4776 $abc$27210$auto$rtlil.cc:2693:MuxGate$23097 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4776 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] DBusCachedPlugin_exceptionBus_payload_badAddr[23] $abc$27210$new_n4778 $abc$27210$auto$rtlil.cc:2693:MuxGate$23099 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4778 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] DBusCachedPlugin_exceptionBus_payload_badAddr[21] $abc$27210$new_n4783 $abc$27210$auto$rtlil.cc:2693:MuxGate$23103 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n4783 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n4791 $abc$27210$auto$rtlil.cc:2693:MuxGate$23109 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[18] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4791 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] $abc$27210$new_n4793 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23111 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4794 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4793 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[17] BranchPlugin_branchExceptionPort_payload_badAddr[17] $abc$27210$new_n4701 $abc$27210$new_n4794 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] $abc$27210$new_n4796 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23113 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4797 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4796 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[16] BranchPlugin_branchExceptionPort_payload_badAddr[16] $abc$27210$new_n4701 $abc$27210$new_n4797 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] DBusCachedPlugin_exceptionBus_payload_badAddr[15] $abc$27210$new_n4799 $abc$27210$auto$rtlil.cc:2693:MuxGate$23115 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$new_n4799 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] DBusCachedPlugin_exceptionBus_payload_badAddr[14] $abc$27210$new_n4801 $abc$27210$auto$rtlil.cc:2693:MuxGate$23117 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4801 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] DBusCachedPlugin_exceptionBus_payload_badAddr[13] $abc$27210$new_n4803 $abc$27210$auto$rtlil.cc:2693:MuxGate$23119 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4803 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] DBusCachedPlugin_exceptionBus_payload_badAddr[10] $abc$27210$new_n4812 $abc$27210$auto$rtlil.cc:2693:MuxGate$23125 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] $abc$27210$new_n4812 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n4817 $abc$27210$auto$rtlil.cc:2693:MuxGate$23129 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] $abc$27210$new_n4817 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n4819 $abc$27210$auto$rtlil.cc:2693:MuxGate$23131 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 $abc$27210$new_n4819 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n4821 $abc$27210$auto$rtlil.cc:2693:MuxGate$23133 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[6] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4821 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] DBusCachedPlugin_exceptionBus_payload_badAddr[5] $abc$27210$new_n4823 $abc$27210$auto$rtlil.cc:2693:MuxGate$23135 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] _zz__zz_decode_IS_CSR_41 $abc$27210$new_n4823 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n4828 $abc$27210$auto$rtlil.cc:2693:MuxGate$23139 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4828 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] $abc$27210$new_n4830 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23141 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4831 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4830 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[2] BranchPlugin_branchExceptionPort_payload_badAddr[2] $abc$27210$new_n4701 $abc$27210$new_n4831 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] $abc$27210$new_n4833 $abc$27210$auto$rtlil.cc:2693:MuxGate$23143 -000 1 -010 1 -110 1 -111 1 -.names $abc$27210$new_n4698 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4752 IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$new_n4701 $abc$27210$new_n4833 -00000 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] $abc$27210$new_n4835 $abc$27210$auto$rtlil.cc:2693:MuxGate$23145 -000 1 -010 1 -110 1 -111 1 -.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] $abc$27210$new_n4699 $abc$27210$new_n4835 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] CsrPlugin_mtval[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23207 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] CsrPlugin_mtval[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23209 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] CsrPlugin_mtval[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23211 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] CsrPlugin_mtval[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23213 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] CsrPlugin_mtval[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23215 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] CsrPlugin_mtval[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23217 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] CsrPlugin_mtval[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23219 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] CsrPlugin_mtval[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23221 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] CsrPlugin_mtval[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23223 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] CsrPlugin_mtval[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23225 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] CsrPlugin_mtval[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23227 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] CsrPlugin_mtval[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23229 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] CsrPlugin_mtval[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23231 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] CsrPlugin_mtval[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23233 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] CsrPlugin_mtval[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23235 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] CsrPlugin_mtval[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23237 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] CsrPlugin_mtval[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23239 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] CsrPlugin_mtval[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23241 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] CsrPlugin_mtval[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23243 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] CsrPlugin_mtval[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23245 -001 1 -011 1 -110 1 -111 1 -.names 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-11010 1 -11011 1 -11110 1 -11111 1 -.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] memory_DivPlugin_div_stage_0_remainderShifted $abc$27210$new_n5034 -0010 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1110 1 -.names $abc$27210$new_n4261 memory_DivPlugin_div_stage_0_remainderShifted _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23453 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[9] MmuPlugin_shared_dBusRspStaged_payload_data[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23457 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[8] MmuPlugin_shared_dBusRspStaged_payload_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23459 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[7] MmuPlugin_shared_dBusRspStaged_payload_data[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23461 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[6] MmuPlugin_shared_dBusRspStaged_payload_data[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23463 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[5] MmuPlugin_shared_dBusRspStaged_payload_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23465 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[4] MmuPlugin_shared_dBusRspStaged_payload_data[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23467 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[3] MmuPlugin_shared_dBusRspStaged_payload_data[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23469 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[2] MmuPlugin_shared_dBusRspStaged_payload_data[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23471 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[1] MmuPlugin_shared_dBusRspStaged_payload_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23473 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[0] MmuPlugin_shared_dBusRspStaged_payload_data[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23475 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[8] MmuPlugin_shared_dBusRspStaged_payload_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23477 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[7] MmuPlugin_shared_dBusRspStaged_payload_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23479 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[6] MmuPlugin_shared_dBusRspStaged_payload_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23481 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[5] MmuPlugin_shared_dBusRspStaged_payload_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23483 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[4] MmuPlugin_shared_dBusRspStaged_payload_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23485 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[3] MmuPlugin_shared_dBusRspStaged_payload_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23487 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[2] MmuPlugin_shared_dBusRspStaged_payload_data[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23489 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[1] MmuPlugin_shared_dBusRspStaged_payload_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23491 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[0] MmuPlugin_shared_dBusRspStaged_payload_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23493 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_vpn_1[8] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23495 -01 1 -10 1 -11 1 -.names $abc$27210$new_n4315 $abc$27210$new_n4329 $abc$27210$new_n5056 -11 1 -.names MmuPlugin_shared_vpn_1[7] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23497 -10 1 -.names MmuPlugin_shared_vpn_1[6] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23499 -10 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_shared_vpn_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23501 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_shared_vpn_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23503 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_shared_vpn_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23505 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_shared_vpn_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23507 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_shared_vpn_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23509 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_shared_vpn_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23511 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_shared_vpn_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23513 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_shared_vpn_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23515 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_shared_vpn_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23517 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_shared_vpn_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23519 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_shared_vpn_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23521 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_shared_vpn_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23523 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_shared_vpn_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23525 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_shared_vpn_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23527 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_shared_vpn_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23529 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23531 -001 1 -011 1 -110 1 -111 1 -.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5075 -1110 1 -.names when_MmuPlugin_l281_1 MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo $abc$27210$new_n4391 $abc$27210$new_n5076 -1100 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23533 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23535 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23537 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23539 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23541 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23543 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23545 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23547 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_5_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23549 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_5_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23551 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_5_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23553 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_5_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23555 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_5_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23557 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_5_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23559 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_5_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23561 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_5_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23563 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_5_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23565 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_5_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23567 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_5_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23569 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_5_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23571 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_5_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23573 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_5_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23575 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_5_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23577 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23579 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_5_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23581 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_5_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23583 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_5_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23585 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_5_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23587 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_5_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23589 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_5_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23591 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_5_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23593 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23595 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_5_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23597 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_5_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23599 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_5_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23601 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23603 -001 1 -011 1 -110 1 -111 1 -.names MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5113 -1100 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23605 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23607 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23609 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23611 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23613 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23615 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23617 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23619 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_4_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23621 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_4_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23623 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_4_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23625 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_4_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23627 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_4_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23629 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_4_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23631 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_4_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23633 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_4_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23635 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_4_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23637 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_4_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23639 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_4_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23641 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_4_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23643 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_4_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23645 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23647 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_4_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23649 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_4_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23651 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_4_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23653 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_4_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23655 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_4_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23657 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_4_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23659 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_4_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23661 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_4_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23663 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_4_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23665 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_4_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23667 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_4_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23669 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_4_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23671 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_4_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23673 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23675 -001 1 -011 1 -110 1 -111 1 -.names MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5150 -1110 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23677 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23679 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23681 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23683 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23685 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23687 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23689 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23691 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_3_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23693 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_3_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23695 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_3_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23697 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_3_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23699 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_3_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23701 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_3_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23703 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_3_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23705 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_3_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23707 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_3_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23709 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23711 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_3_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23713 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_3_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23715 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_3_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23717 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23719 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_3_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23721 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_3_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23723 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_3_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23725 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_3_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23727 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_3_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23729 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_3_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23731 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_3_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23733 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_3_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23735 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_3_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23737 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23739 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_3_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23741 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_3_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23743 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_3_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23745 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23747 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5187 -1100 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23749 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23751 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23753 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23755 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23757 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23759 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23761 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23763 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_2_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23765 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_2_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23767 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_2_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23769 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_2_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23771 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_2_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23773 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_2_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23775 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_2_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23777 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_2_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23779 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_2_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23781 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_2_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23783 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_2_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23785 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_2_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23787 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_2_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23789 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23791 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_2_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23793 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_2_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23795 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_2_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23797 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_2_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23799 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_2_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23801 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_2_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23803 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_2_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23805 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_2_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23807 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_2_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23809 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23811 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_2_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23813 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_2_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23815 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_2_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23817 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23819 -001 1 -011 1 -110 1 -111 1 -.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5224 -1100 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23821 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23823 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23825 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23827 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23829 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23831 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23833 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23835 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_1_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23837 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_1_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23839 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_1_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23841 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_1_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23843 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_1_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23845 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_1_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23847 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_1_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23849 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_1_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23851 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_1_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23853 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_1_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23855 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_1_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23857 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_1_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23859 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_1_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23861 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_1_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23863 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_1_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23865 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_1_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23867 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_1_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23869 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_1_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23871 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_1_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23873 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_1_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23875 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_1_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23877 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_1_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23879 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_1_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23881 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_1_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23883 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_1_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23885 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_1_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23887 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_1_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23889 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23891 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5261 -1000 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23893 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23895 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23897 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23899 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23901 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23903 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23905 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23907 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_0_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23909 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_0_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23911 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_0_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23913 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_0_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23915 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_0_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23917 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_0_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23919 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_0_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23921 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_0_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23923 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_0_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23925 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23927 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_0_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23929 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_0_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23931 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_0_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23933 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_0_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23935 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_0_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23937 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_0_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23939 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_0_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23941 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23943 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_0_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23945 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_0_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23947 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_0_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23949 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_0_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23951 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_0_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23953 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_0_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23955 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_0_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23957 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_0_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23959 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_0_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23961 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5299 MmuPlugin_satp_ppn[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23963 -001 1 -011 1 -100 1 -101 1 -.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_384 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n5298 -1111 1 -.names $abc$27210$new_n5302 switch_Misc_l241_1 $abc$27210$new_n5300 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5299 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n5301 execute_CsrPlugin_csr_833 CsrPlugin_mepc[20] $abc$27210$new_n5300 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[20] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[20] $abc$27210$new_n5301 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[20] _zz_execute_BranchPlugin_branch_src2_8 $abc$27210$new_n5302 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5304 MmuPlugin_satp_ppn[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23965 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5307 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5305 $abc$27210$new_n5304 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5306 execute_CsrPlugin_csr_835 CsrPlugin_mtval[19] MmuPlugin_satp_ppn[19] execute_CsrPlugin_csr_384 $abc$27210$new_n5305 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names MmuPlugin_status_mxr CsrPlugin_mepc[19] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5306 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10100 1 -11000 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[19] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n5307 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5309 MmuPlugin_satp_ppn[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23967 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5312 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5310 $abc$27210$new_n5309 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5311 execute_CsrPlugin_csr_835 CsrPlugin_mtval[18] MmuPlugin_satp_ppn[18] execute_CsrPlugin_csr_384 $abc$27210$new_n5310 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names MmuPlugin_status_sum CsrPlugin_mepc[18] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5311 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10100 1 -11000 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[18] _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$new_n5312 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5314 MmuPlugin_satp_ppn[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23969 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5317 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5315 $abc$27210$new_n5314 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$27210$new_n5316 execute_CsrPlugin_csr_835 CsrPlugin_mtval[17] MmuPlugin_satp_ppn[17] execute_CsrPlugin_csr_384 $abc$27210$new_n5315 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names MmuPlugin_status_mprv CsrPlugin_mepc[17] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5316 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10100 1 -11000 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[17] _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$new_n5317 -0010 1 -0011 1 -1001 1 -1011 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5319 MmuPlugin_satp_ppn[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23971 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5322 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5320 $abc$27210$new_n5319 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5321 execute_CsrPlugin_csr_833 CsrPlugin_mepc[16] $abc$27210$new_n5320 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[16] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[16] $abc$27210$new_n5321 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[16] _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$new_n5322 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5324 MmuPlugin_satp_ppn[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23973 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5327 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5325 $abc$27210$new_n5324 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5326 execute_CsrPlugin_csr_833 CsrPlugin_mepc[15] $abc$27210$new_n5325 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[15] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[15] $abc$27210$new_n5326 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] 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-0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5334 MmuPlugin_satp_ppn[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23977 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5337 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5335 $abc$27210$new_n5334 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5336 execute_CsrPlugin_csr_833 CsrPlugin_mepc[13] $abc$27210$new_n5335 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[13] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[13] $abc$27210$new_n5336 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[13] switch_Misc_l241_1 $abc$27210$new_n5337 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5339 MmuPlugin_satp_ppn[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23979 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5342 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5340 $abc$27210$new_n5339 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5341 CsrPlugin_mepc[12] execute_CsrPlugin_csr_833 CsrPlugin_mstatus_MPP[1] execute_CsrPlugin_csr_768 $abc$27210$new_n5340 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[12] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[12] $abc$27210$new_n5341 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[12] _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5342 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5344 MmuPlugin_satp_ppn[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23981 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5348 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5345 $abc$27210$new_n5344 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$27210$new_n5346 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[11] execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MPP[0] $abc$27210$new_n5345 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names $abc$27210$new_n5347 execute_CsrPlugin_csr_772 CsrPlugin_mie_MEIE execute_CsrPlugin_csr_836 CsrPlugin_mip_MEIP $abc$27210$new_n5346 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[11] CsrPlugin_mepc[11] execute_CsrPlugin_csr_833 $abc$27210$new_n5347 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names execute_RS1[11] $abc$27210$new_n5349 $abc$27210$new_n5348 -11 1 -.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] $abc$27210$new_n5349 -00 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5351 MmuPlugin_satp_ppn[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23983 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5352 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5353 $abc$27210$new_n5351 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names execute_RS1[10] $abc$27210$new_n5349 $abc$27210$new_n5352 -11 1 -.names $abc$27210$new_n5354 execute_CsrPlugin_csr_833 CsrPlugin_mepc[10] $abc$27210$new_n5353 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[10] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[10] $abc$27210$new_n5354 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5356 MmuPlugin_satp_ppn[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23985 -001 1 -011 1 -110 1 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-11 1 -.names $abc$27210$new_n5364 execute_CsrPlugin_csr_833 CsrPlugin_mepc[8] $abc$27210$new_n5363 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[8] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[8] $abc$27210$new_n5364 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5366 MmuPlugin_satp_ppn[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23989 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5370 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5367 $abc$27210$new_n5366 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$27210$new_n5368 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[7] execute_CsrPlugin_csr_772 CsrPlugin_mie_MTIE $abc$27210$new_n5367 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names $abc$27210$new_n5369 CsrPlugin_mip_MTIP execute_CsrPlugin_csr_836 execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MPIE $abc$27210$new_n5368 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[7] CsrPlugin_mepc[7] execute_CsrPlugin_csr_833 $abc$27210$new_n5369 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names execute_RS1[7] $abc$27210$new_n5349 $abc$27210$new_n5370 -11 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5372 MmuPlugin_satp_ppn[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23991 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5373 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5374 $abc$27210$new_n5372 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names execute_RS1[6] $abc$27210$new_n5349 $abc$27210$new_n5373 -11 1 -.names $abc$27210$new_n5375 execute_CsrPlugin_csr_833 CsrPlugin_mepc[6] $abc$27210$new_n5374 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[6] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[6] $abc$27210$new_n5375 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5377 MmuPlugin_satp_ppn[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23993 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5378 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5379 $abc$27210$new_n5377 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names execute_RS1[5] $abc$27210$new_n5349 $abc$27210$new_n5378 -11 1 -.names $abc$27210$new_n5380 execute_CsrPlugin_csr_833 CsrPlugin_mepc[5] $abc$27210$new_n5379 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[5] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[5] $abc$27210$new_n5380 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5382 MmuPlugin_satp_ppn[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23995 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5385 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5383 $abc$27210$new_n5382 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5384 execute_CsrPlugin_csr_833 CsrPlugin_mepc[4] $abc$27210$new_n5383 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[4] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[4] $abc$27210$new_n5384 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[4] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n5385 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1110 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5387 MmuPlugin_satp_ppn[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23997 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5392 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5388 $abc$27210$new_n5387 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5391 $abc$27210$new_n5389 CsrPlugin_mie_MSIE execute_CsrPlugin_csr_772 $abc$27210$new_n5388 -1100 1 -1101 1 -1110 1 -.names $abc$27210$new_n5390 execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[3] execute_CsrPlugin_csr_836 CsrPlugin_mip_MSIP $abc$27210$new_n5389 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[3] CsrPlugin_mstatus_MIE execute_CsrPlugin_csr_768 $abc$27210$new_n5390 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[3] CsrPlugin_mepc[3] execute_CsrPlugin_csr_833 $abc$27210$new_n5391 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[3] _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$new_n5392 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1110 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5394 MmuPlugin_satp_ppn[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23999 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5397 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5395 $abc$27210$new_n5394 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$27210$new_n5396 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[2] execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$27210$new_n5395 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[2] CsrPlugin_mepc[2] execute_CsrPlugin_csr_833 $abc$27210$new_n5396 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[2] _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$new_n5397 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5399 MmuPlugin_satp_ppn[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24001 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5402 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5400 $abc$27210$new_n5399 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5401 execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[1] execute_CsrPlugin_csr_833 CsrPlugin_mepc[1] $abc$27210$new_n5400 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[1] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[1] $abc$27210$new_n5401 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[1] _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$new_n5402 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1110 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5404 MmuPlugin_satp_ppn[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24003 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5407 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5405 $abc$27210$new_n5404 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5406 execute_CsrPlugin_csr_835 CsrPlugin_mtval[0] execute_CsrPlugin_csr_833 CsrPlugin_mepc[0] $abc$27210$new_n5405 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[0] CsrPlugin_mcause_exceptionCode[0] execute_CsrPlugin_csr_834 $abc$27210$new_n5406 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[0] _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$new_n5407 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1110 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5409 MmuPlugin_satp_asid[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24005 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5412 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5410 $abc$27210$new_n5409 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5411 execute_CsrPlugin_csr_833 CsrPlugin_mepc[29] $abc$27210$new_n5410 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[29] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[7] $abc$27210$new_n5411 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[29] _zz__zz_execute_BranchPlugin_branch_src2_2[8] $abc$27210$new_n5412 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5414 MmuPlugin_satp_asid[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24007 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5417 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5415 $abc$27210$new_n5414 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5416 execute_CsrPlugin_csr_833 CsrPlugin_mepc[28] $abc$27210$new_n5415 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[28] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[6] $abc$27210$new_n5416 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[28] _zz__zz_execute_BranchPlugin_branch_src2_2[7] $abc$27210$new_n5417 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5419 MmuPlugin_satp_asid[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24009 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5422 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5420 $abc$27210$new_n5419 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5421 execute_CsrPlugin_csr_833 CsrPlugin_mepc[27] $abc$27210$new_n5420 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[27] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[5] $abc$27210$new_n5421 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[27] _zz__zz_execute_BranchPlugin_branch_src2_2[6] $abc$27210$new_n5422 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5424 MmuPlugin_satp_asid[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24011 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5427 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5425 $abc$27210$new_n5424 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5426 execute_CsrPlugin_csr_833 CsrPlugin_mepc[26] $abc$27210$new_n5425 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[26] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[4] $abc$27210$new_n5426 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[26] _zz__zz_execute_BranchPlugin_branch_src2_2[5] $abc$27210$new_n5427 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5429 MmuPlugin_satp_asid[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24013 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5432 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5430 $abc$27210$new_n5429 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5431 execute_CsrPlugin_csr_833 CsrPlugin_mepc[25] $abc$27210$new_n5430 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[25] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[3] $abc$27210$new_n5431 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[25] _zz__zz_execute_BranchPlugin_branch_src2_2[4] $abc$27210$new_n5432 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5434 MmuPlugin_satp_asid[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24015 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5437 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5435 $abc$27210$new_n5434 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5436 execute_CsrPlugin_csr_833 CsrPlugin_mepc[24] $abc$27210$new_n5435 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[24] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[2] $abc$27210$new_n5436 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[24] _zz__zz_execute_BranchPlugin_branch_src2_2[3] $abc$27210$new_n5437 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5439 MmuPlugin_satp_asid[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24017 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5442 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5440 $abc$27210$new_n5439 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5441 execute_CsrPlugin_csr_833 CsrPlugin_mepc[23] $abc$27210$new_n5440 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[23] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[1] $abc$27210$new_n5441 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[23] _zz__zz_execute_BranchPlugin_branch_src2_2[2] $abc$27210$new_n5442 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5444 MmuPlugin_satp_asid[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24019 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5447 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5445 $abc$27210$new_n5444 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5446 execute_CsrPlugin_csr_833 CsrPlugin_mepc[22] $abc$27210$new_n5445 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[22] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[0] $abc$27210$new_n5446 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[22] _zz__zz_execute_BranchPlugin_branch_src2_2[1] $abc$27210$new_n5447 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24021 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24023 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24025 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24027 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24029 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24031 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24033 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24035 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24037 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24039 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24041 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24043 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24045 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24047 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24049 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24051 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24053 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24055 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24057 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24059 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24061 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24063 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24065 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24067 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24069 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24071 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24073 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24075 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24077 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz__zz_3_port1[0] _zz_decode_PREDICTION_CONTEXT_line_history_2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24079 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[8] _zz_decode_PREDICTION_CONTEXT_hazard_3[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24081 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[7] _zz_decode_PREDICTION_CONTEXT_hazard_3[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24083 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[6] _zz_decode_PREDICTION_CONTEXT_hazard_3[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24085 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[5] _zz_decode_PREDICTION_CONTEXT_hazard_3[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24087 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[4] _zz_decode_PREDICTION_CONTEXT_hazard_3[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24089 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[3] _zz_decode_PREDICTION_CONTEXT_hazard_3[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24091 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[2] _zz_decode_PREDICTION_CONTEXT_hazard_3[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24093 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[1] _zz_decode_PREDICTION_CONTEXT_hazard_3[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24095 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[0] _zz_decode_PREDICTION_CONTEXT_hazard_3[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24097 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_mcause_exceptionCode[0] CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24159 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[30] $abc$27210$new_n5489 _zz_memory_DivPlugin_div_stage_0_outNumerator[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24161 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[30] $abc$27210$new_n5506 $abc$27210$new_n5490 $abc$27210$new_n5489 -001 1 -010 1 -100 1 -111 1 -.names $abc$27210$new_n5491 execute_RS1[28] execute_RS1[29] $abc$27210$new_n5490 -100 1 -.names $abc$27210$new_n5492 execute_RS1[25] execute_RS1[26] execute_RS1[27] $abc$27210$new_n5491 -1000 1 -.names $abc$27210$new_n5493 execute_RS1[22] execute_RS1[23] execute_RS1[24] $abc$27210$new_n5492 -1000 1 -.names $abc$27210$new_n5494 execute_RS1[19] execute_RS1[20] execute_RS1[21] $abc$27210$new_n5493 -1000 1 -.names $abc$27210$new_n5495 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$abc$27210$auto$rtlil.cc:2693:MuxGate$24201 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[10] $abc$27210$new_n5506 $abc$27210$new_n5503 $abc$27210$new_n5546 -001 1 -010 1 -100 1 -111 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[9] _zz_memory_DivPlugin_div_stage_0_outNumerator[10] $abc$27210$new_n5548 $abc$27210$auto$rtlil.cc:2693:MuxGate$24203 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[9] $abc$27210$new_n5506 $abc$27210$new_n5504 execute_RS1[7] execute_RS1[8] $abc$27210$new_n5548 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11100 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 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_zz_memory_DivPlugin_div_stage_0_outNumerator[6] _zz_memory_DivPlugin_div_stage_0_outNumerator[7] $abc$27210$new_n5554 $abc$27210$auto$rtlil.cc:2693:MuxGate$24209 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[6] $abc$27210$new_n5506 $abc$27210$new_n5505 execute_RS1[4] execute_RS1[5] $abc$27210$new_n5554 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11100 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[5] _zz_memory_DivPlugin_div_stage_0_outNumerator[6] $abc$27210$new_n5556 $abc$27210$auto$rtlil.cc:2693:MuxGate$24211 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[5] $abc$27210$new_n5505 $abc$27210$new_n5506 execute_RS1[4] $abc$27210$new_n5556 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[4] _zz_memory_DivPlugin_div_stage_0_outNumerator[5] $abc$27210$new_n5558 $abc$27210$auto$rtlil.cc:2693:MuxGate$24213 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[4] $abc$27210$new_n5506 $abc$27210$new_n5505 $abc$27210$new_n5558 -001 1 -010 1 -100 1 -111 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[3] _zz_memory_DivPlugin_div_stage_0_outNumerator[4] $abc$27210$new_n5560 $abc$27210$auto$rtlil.cc:2693:MuxGate$24215 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[3] $abc$27210$new_n5506 execute_RS1[0] execute_RS1[1] execute_RS1[2] $abc$27210$new_n5560 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[2] _zz_memory_DivPlugin_div_stage_0_outNumerator[3] $abc$27210$new_n5562 $abc$27210$auto$rtlil.cc:2693:MuxGate$24217 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[2] $abc$27210$new_n5506 execute_RS1[0] execute_RS1[1] $abc$27210$new_n5562 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[1] _zz_memory_DivPlugin_div_stage_0_outNumerator[2] $abc$27210$new_n5564 $abc$27210$auto$rtlil.cc:2693:MuxGate$24219 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_RS1[1] execute_RS1[0] $abc$27210$new_n5506 $abc$27210$new_n5564 -011 1 -100 1 -101 1 -110 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outNumerator[1] execute_RS1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24221 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] CsrPlugin_interrupt_code[2] CsrPlugin_mcause_exceptionCode[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24223 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4698 $abc$27210$new_n4699 memory_to_writeBack_MEMORY_WR $abc$27210$new_n8208 CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24237 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4751 $abc$27210$new_n5569 $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24239 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n4698 dataCache_1.stageB_unaligned $abc$27210$new_n5569 -10 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24241 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24243 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24245 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24247 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24249 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24251 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24253 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24255 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24257 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24259 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24261 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24263 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24265 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24267 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24269 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24271 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24273 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24275 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24277 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[30] IBusCachedPlugin_cache._zz_banks_0_port1[30] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24279 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n5590 -000 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[29] IBusCachedPlugin_cache._zz_banks_0_port1[29] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24281 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[28] IBusCachedPlugin_cache._zz_banks_0_port1[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24283 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[27] IBusCachedPlugin_cache._zz_banks_0_port1[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24285 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[26] IBusCachedPlugin_cache._zz_banks_0_port1[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24287 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[25] IBusCachedPlugin_cache._zz_banks_0_port1[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24289 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[24] IBusCachedPlugin_cache._zz_banks_0_port1[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24291 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[23] IBusCachedPlugin_cache._zz_banks_0_port1[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24293 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[22] IBusCachedPlugin_cache._zz_banks_0_port1[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24295 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[21] IBusCachedPlugin_cache._zz_banks_0_port1[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24297 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[20] IBusCachedPlugin_cache._zz_banks_0_port1[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24299 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[19] IBusCachedPlugin_cache._zz_banks_0_port1[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24301 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[18] IBusCachedPlugin_cache._zz_banks_0_port1[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24303 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[17] IBusCachedPlugin_cache._zz_banks_0_port1[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24305 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[16] IBusCachedPlugin_cache._zz_banks_0_port1[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24307 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[15] IBusCachedPlugin_cache._zz_banks_0_port1[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24309 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[14] IBusCachedPlugin_cache._zz_banks_0_port1[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24311 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[13] IBusCachedPlugin_cache._zz_banks_0_port1[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24313 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[12] IBusCachedPlugin_cache._zz_banks_0_port1[12] _zz__zz_decode_IS_CSR_21 $abc$27210$auto$rtlil.cc:2693:MuxGate$24315 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[11] IBusCachedPlugin_cache._zz_banks_0_port1[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24317 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[10] IBusCachedPlugin_cache._zz_banks_0_port1[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24319 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[9] IBusCachedPlugin_cache._zz_banks_0_port1[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24321 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[8] IBusCachedPlugin_cache._zz_banks_0_port1[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24323 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[7] IBusCachedPlugin_cache._zz_banks_0_port1[7] _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 $abc$27210$auto$rtlil.cc:2693:MuxGate$24325 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[6] IBusCachedPlugin_cache._zz_banks_0_port1[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24327 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[5] IBusCachedPlugin_cache._zz_banks_0_port1[5] _zz__zz_decode_IS_CSR_41 $abc$27210$auto$rtlil.cc:2693:MuxGate$24329 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[4] IBusCachedPlugin_cache._zz_banks_0_port1[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24331 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[3] IBusCachedPlugin_cache._zz_banks_0_port1[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24333 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[2] IBusCachedPlugin_cache._zz_banks_0_port1[2] _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24335 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[1] IBusCachedPlugin_cache._zz_banks_0_port1[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24337 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[0] IBusCachedPlugin_cache._zz_banks_0_port1[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24339 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache.lineLoader_wordIndex[1] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24341 -011 1 -100 1 -101 1 -110 1 -.names IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24343 -01 1 -10 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[30] HazardSimplePlugin_writeBackWrites_payload_data[30] debug_bus_rsp_data[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24403 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n5646 $abc$27210$new_n4255 $abc$27210$new_n5625 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[30] HazardSimplePlugin_writeBackWrites_payload_data[30] -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5626 $abc$27210$new_n5645 _zz__zz_decode_RS2_2[30] $abc$27210$new_n5625 -10000 1 -10001 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[61] $abc$27210$new_n5627 $abc$27210$new_n5626 -010 1 -100 1 -110 1 -111 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[60] $abc$27210$new_n5628 $abc$27210$new_n5627 -000 1 -001 1 -011 1 -101 1 -.names $abc$27210$new_n5644 _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[58] _zz_writeBack_MulPlugin_result_1[59] $abc$27210$new_n5629 $abc$27210$new_n5628 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[56] _zz_writeBack_MulPlugin_result_1[57] $abc$27210$new_n5630 $abc$27210$new_n5629 -0110 1 -1000 1 -.names $abc$27210$new_n5643 _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[54] _zz_writeBack_MulPlugin_result_1[55] $abc$27210$new_n5631 $abc$27210$new_n5630 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[52] _zz_writeBack_MulPlugin_result_1[53] $abc$27210$new_n5632 $abc$27210$new_n5631 -0110 1 -1000 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[51] $abc$27210$new_n5633 $abc$27210$new_n5632 -000 1 -001 1 -011 1 -101 1 -.names _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] _zz_writeBack_MulPlugin_result_1[50] _zz_writeBack_MulPlugin_result[50] $abc$27210$new_n5634 $abc$27210$new_n5633 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] _zz_writeBack_MulPlugin_result_1[48] _zz_writeBack_MulPlugin_result[48] $abc$27210$new_n5635 $abc$27210$new_n5634 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] _zz_writeBack_MulPlugin_result_1[46] _zz_writeBack_MulPlugin_result[46] $abc$27210$new_n5636 $abc$27210$new_n5635 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] _zz_writeBack_MulPlugin_result_1[44] _zz_writeBack_MulPlugin_result[44] $abc$27210$new_n5637 $abc$27210$new_n5636 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] _zz_writeBack_MulPlugin_result_1[42] _zz_writeBack_MulPlugin_result[42] $abc$27210$new_n5638 $abc$27210$new_n5637 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] _zz_writeBack_MulPlugin_result_1[40] _zz_writeBack_MulPlugin_result[40] $abc$27210$new_n5639 $abc$27210$new_n5638 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] _zz_writeBack_MulPlugin_result_1[38] _zz_writeBack_MulPlugin_result[38] $abc$27210$new_n5640 $abc$27210$new_n5639 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] _zz_writeBack_MulPlugin_result_1[36] _zz_writeBack_MulPlugin_result[36] $abc$27210$new_n5641 $abc$27210$new_n5640 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names _zz_writeBack_MulPlugin_result_1[34] _zz_writeBack_MulPlugin_result[34] $abc$27210$new_n5642 $abc$27210$new_n5641 -000 1 -001 1 -011 1 -101 1 -.names _zz_writeBack_MulPlugin_result_1[32] _zz_writeBack_MulPlugin_result[32] _zz_writeBack_MulPlugin_result_1[33] _zz_writeBack_MulPlugin_result[33] $abc$27210$new_n5642 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[53] _zz_writeBack_MulPlugin_result_1[52] $abc$27210$new_n5643 -000 1 -001 1 -010 1 -011 1 -100 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[57] _zz_writeBack_MulPlugin_result_1[56] $abc$27210$new_n5644 -000 1 -001 1 -010 1 -011 1 -100 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[62] $abc$27210$new_n5645 -00 1 -11 1 -.names $abc$27210$new_n5654 $abc$27210$new_n5647 $abc$27210$new_n5656 _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5646 -1000 1 -1010 1 -1011 1 -.names MmuPlugin_dBusAccess_rsp_payload_data[7] $abc$27210$new_n4254 _zz_lastStageRegFileWrite_payload_address[14] $abc$27210$new_n5647 -110 1 -.names $abc$27210$new_n5649 MmuPlugin_dBusAccess_rsp_payload_data[23] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[7] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1110 1 -.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5650 $abc$27210$new_n5651 $abc$27210$new_n5652 $abc$27210$new_n5649 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[31] dataCache_1.stageB_dataMux[31] $abc$27210$new_n5650 -000 1 -010 1 -100 1 -101 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[7] dataCache_1.stageB_dataMux[7] $abc$27210$new_n5651 -000 1 -010 1 -100 1 -101 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[15] dataCache_1.stageB_dataMux[15] $abc$27210$new_n5652 -000 1 -010 1 -100 1 -101 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[23] dataCache_1.stageB_dataMux[23] MmuPlugin_dBusAccess_rsp_payload_data[23] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4101 _zz_lastStageRegFileWrite_payload_address[12] MmuPlugin_dBusAccess_rsp_payload_data[15] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[14] $abc$27210$new_n5654 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 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$abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5666 $abc$27210$new_n5665 _zz__zz_decode_RS2_2[28] HazardSimplePlugin_writeBackWrites_payload_data[28] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[60] $abc$27210$new_n5628 $abc$27210$new_n5665 -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5667 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[28] $abc$27210$new_n5666 -00001 1 -00010 1 -00011 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$27210$new_n5654 MmuPlugin_dBusAccess_rsp_payload_data[28] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5667 -100 1 -101 1 -110 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[28] dataCache_1.stageB_dataMux[28] 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-01111 1 -.names $abc$27210$new_n5654 MmuPlugin_dBusAccess_rsp_payload_data[22] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5702 -100 1 -101 1 -110 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[22] dataCache_1.stageB_dataMux[22] MmuPlugin_dBusAccess_rsp_payload_data[22] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[21] HazardSimplePlugin_writeBackWrites_payload_data[21] debug_bus_rsp_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24421 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5707 $abc$27210$new_n5706 _zz__zz_decode_RS2_2[21] HazardSimplePlugin_writeBackWrites_payload_data[21] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names 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-010 1 -011 1 -.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[19] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5720 -1000 1 -1001 1 -1010 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[19] dataCache_1.stageB_dataMux[19] MmuPlugin_dBusAccess_rsp_payload_data[19] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[18] HazardSimplePlugin_writeBackWrites_payload_data[18] debug_bus_rsp_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24427 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5725 $abc$27210$new_n5724 _zz__zz_decode_RS2_2[18] HazardSimplePlugin_writeBackWrites_payload_data[18] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[50] _zz_writeBack_MulPlugin_result[50] _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] $abc$27210$new_n5634 $abc$27210$new_n5724 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n5726 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n5725 -0001 1 -0010 1 -0011 1 -.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[18] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5726 -1000 1 -1001 1 -1010 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[18] dataCache_1.stageB_dataMux[18] MmuPlugin_dBusAccess_rsp_payload_data[18] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[17] HazardSimplePlugin_writeBackWrites_payload_data[17] debug_bus_rsp_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24429 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5731 $abc$27210$new_n5730 _zz__zz_decode_RS2_2[17] HazardSimplePlugin_writeBackWrites_payload_data[17] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] $abc$27210$new_n5634 $abc$27210$new_n5730 -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n5732 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[17] $abc$27210$new_n5731 -001 1 -010 1 -011 1 -.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[17] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5732 -1000 1 -1001 1 -1010 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[17] dataCache_1.stageB_dataMux[17] MmuPlugin_dBusAccess_rsp_payload_data[17] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[16] HazardSimplePlugin_writeBackWrites_payload_data[16] debug_bus_rsp_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24431 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5737 $abc$27210$new_n5736 _zz__zz_decode_RS2_2[16] HazardSimplePlugin_writeBackWrites_payload_data[16] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[48] _zz_writeBack_MulPlugin_result[48] _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] $abc$27210$new_n5635 $abc$27210$new_n5736 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n5738 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[16] $abc$27210$new_n5737 -0001 1 -0010 1 -0011 1 -.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[16] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5738 -1000 1 -1001 1 -1010 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[15] HazardSimplePlugin_writeBackWrites_payload_data[15] debug_bus_rsp_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24433 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5742 $abc$27210$new_n5741 _zz__zz_decode_RS2_2[15] HazardSimplePlugin_writeBackWrites_payload_data[15] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] $abc$27210$new_n5635 $abc$27210$new_n5741 -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[15] MmuPlugin_dBusAccess_rsp_payload_data[15] $abc$27210$new_n4254 $abc$27210$new_n5742 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[14] HazardSimplePlugin_writeBackWrites_payload_data[14] debug_bus_rsp_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24435 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[46] _zz_writeBack_MulPlugin_result[46] _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] $abc$27210$new_n5636 $abc$27210$new_n5745 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5656 $abc$27210$new_n5749 MmuPlugin_dBusAccess_rsp_payload_data[14] -000 1 -010 1 -100 1 -101 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[14] dataCache_1.stageB_dataMux[14] $abc$27210$new_n5749 -000 1 -010 1 -100 1 -101 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[13] HazardSimplePlugin_writeBackWrites_payload_data[13] debug_bus_rsp_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24437 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5753 $abc$27210$new_n5752 _zz__zz_decode_RS2_2[13] HazardSimplePlugin_writeBackWrites_payload_data[13] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] $abc$27210$new_n5636 $abc$27210$new_n5752 -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[13] MmuPlugin_dBusAccess_rsp_payload_data[13] $abc$27210$new_n4254 $abc$27210$new_n5753 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[29] dBus_rsp_payload_data[13] dataCache_1.stageB_dataMux[13] MmuPlugin_dBusAccess_rsp_payload_data[13] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[12] HazardSimplePlugin_writeBackWrites_payload_data[12] debug_bus_rsp_data[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24439 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[44] _zz_writeBack_MulPlugin_result[44] _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] $abc$27210$new_n5637 $abc$27210$new_n5757 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[28] dBus_rsp_payload_data[12] dataCache_1.stageB_dataMux[12] MmuPlugin_dBusAccess_rsp_payload_data[12] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[11] HazardSimplePlugin_writeBackWrites_payload_data[11] debug_bus_rsp_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24441 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5764 $abc$27210$new_n5763 _zz__zz_decode_RS2_2[11] HazardSimplePlugin_writeBackWrites_payload_data[11] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] $abc$27210$new_n5637 $abc$27210$new_n5763 -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[11] MmuPlugin_dBusAccess_rsp_payload_data[11] $abc$27210$new_n4254 $abc$27210$new_n5764 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[27] $abc$27210$new_n5766 MmuPlugin_dBusAccess_rsp_payload_data[11] -000 1 -010 1 -110 1 -111 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[11] dataCache_1.stageB_dataMux[11] $abc$27210$new_n5766 -000 1 -010 1 -100 1 -101 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[10] HazardSimplePlugin_writeBackWrites_payload_data[10] debug_bus_rsp_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24443 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[42] _zz_writeBack_MulPlugin_result[42] _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] $abc$27210$new_n5638 $abc$27210$new_n5769 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[26] $abc$27210$new_n5773 MmuPlugin_dBusAccess_rsp_payload_data[10] -000 1 -010 1 -110 1 -111 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[10] dataCache_1.stageB_dataMux[10] $abc$27210$new_n5773 -000 1 -010 1 -100 1 -101 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[9] HazardSimplePlugin_writeBackWrites_payload_data[9] debug_bus_rsp_data[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24445 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5776 $abc$27210$new_n5779 _zz__zz_decode_RS2_2[9] HazardSimplePlugin_writeBackWrites_payload_data[9] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4101 $abc$27210$new_n5777 DBusCachedPlugin_exceptionBus_payload_badAddr[9] $abc$27210$new_n5776 -000 1 -010 1 -110 1 -111 1 -.names $abc$27210$new_n5647 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4254 MmuPlugin_dBusAccess_rsp_payload_data[25] $abc$27210$new_n5778 $abc$27210$new_n5777 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[9] dataCache_1.stageB_dataMux[9] $abc$27210$new_n5778 -000 1 -010 1 -100 1 -101 1 -.names _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] $abc$27210$new_n5638 $abc$27210$new_n5779 -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[8] HazardSimplePlugin_writeBackWrites_payload_data[8] debug_bus_rsp_data[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24447 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5782 $abc$27210$new_n5784 _zz__zz_decode_RS2_2[8] HazardSimplePlugin_writeBackWrites_payload_data[8] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4101 $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5783 DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n5782 -00001 1 -00011 1 -00101 1 -00111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4254 MmuPlugin_dBusAccess_rsp_payload_data[24] $abc$27210$new_n4251 $abc$27210$new_n5783 -0000 1 -0010 1 -1010 1 -1011 1 -.names _zz_writeBack_MulPlugin_result_1[40] _zz_writeBack_MulPlugin_result[40] _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] $abc$27210$new_n5639 $abc$27210$new_n5784 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[7] HazardSimplePlugin_writeBackWrites_payload_data[7] debug_bus_rsp_data[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24449 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5788 $abc$27210$new_n5787 _zz__zz_decode_RS2_2[7] HazardSimplePlugin_writeBackWrites_payload_data[7] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] $abc$27210$new_n5639 $abc$27210$new_n5787 -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4101 $abc$27210$new_n4255 MmuPlugin_dBusAccess_rsp_payload_data[7] DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n5788 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[6] HazardSimplePlugin_writeBackWrites_payload_data[6] debug_bus_rsp_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24451 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5791 $abc$27210$new_n5795 _zz__zz_decode_RS2_2[6] HazardSimplePlugin_writeBackWrites_payload_data[6] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4101 $abc$27210$new_n4255 MmuPlugin_dBusAccess_rsp_payload_data[6] DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n5791 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$27210$new_n5793 MmuPlugin_dBusAccess_rsp_payload_data[22] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[6] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1110 1 -.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5656 $abc$27210$new_n5749 $abc$27210$new_n5794 $abc$27210$new_n5793 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[6] dataCache_1.stageB_dataMux[6] $abc$27210$new_n5794 -000 1 -010 1 -100 1 -101 1 -.names _zz_writeBack_MulPlugin_result_1[38] _zz_writeBack_MulPlugin_result[38] _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] $abc$27210$new_n5640 $abc$27210$new_n5795 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[5] HazardSimplePlugin_writeBackWrites_payload_data[5] debug_bus_rsp_data[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24453 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n8115 $abc$27210$new_n5798 _zz__zz_decode_RS2_2[5] HazardSimplePlugin_writeBackWrites_payload_data[5] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] $abc$27210$new_n5640 $abc$27210$new_n5798 -000 1 -011 1 -101 1 -110 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[4] HazardSimplePlugin_writeBackWrites_payload_data[4] DebugPlugin_busReadDataReg[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24455 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5805 $abc$27210$new_n5808 _zz__zz_decode_RS2_2[4] HazardSimplePlugin_writeBackWrites_payload_data[4] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4101 $abc$27210$new_n5806 DBusCachedPlugin_exceptionBus_payload_badAddr[4] $abc$27210$new_n5805 -000 1 -010 1 -100 1 -101 1 -.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[12] MmuPlugin_dBusAccess_rsp_payload_data[20] $abc$27210$new_n5807 $abc$27210$new_n5806 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[4] dataCache_1.stageB_dataMux[4] $abc$27210$new_n5807 -001 1 -011 1 -110 1 -111 1 -.names _zz_writeBack_MulPlugin_result_1[36] _zz_writeBack_MulPlugin_result[36] _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] $abc$27210$new_n5641 $abc$27210$new_n5808 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[3] HazardSimplePlugin_writeBackWrites_payload_data[3] DebugPlugin_busReadDataReg[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24457 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5811 $abc$27210$new_n5814 _zz__zz_decode_RS2_2[3] HazardSimplePlugin_writeBackWrites_payload_data[3] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4101 MmuPlugin_dBusAccess_rsp_payload_data[3] DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n5811 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5813 MmuPlugin_dBusAccess_rsp_payload_data[19] $abc$27210$new_n5766 MmuPlugin_dBusAccess_rsp_payload_data[3] -00000 1 -00001 1 -00010 1 -00011 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[27] dBus_rsp_payload_data[3] dataCache_1.stageB_dataMux[3] $abc$27210$new_n5813 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] $abc$27210$new_n5641 $abc$27210$new_n5814 -001 1 -010 1 -100 1 -111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[2] HazardSimplePlugin_writeBackWrites_payload_data[2] DebugPlugin_busReadDataReg[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24459 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n5820 MmuPlugin_dBusAccess_rsp_payload_data[2] DBusCachedPlugin_exceptionBus_payload_badAddr[2] HazardSimplePlugin_writeBackWrites_payload_data[2] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n5818 MmuPlugin_dBusAccess_rsp_payload_data[18] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[2] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1110 1 -.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[26] $abc$27210$new_n5773 $abc$27210$new_n5819 $abc$27210$new_n5818 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[2] dataCache_1.stageB_dataMux[2] $abc$27210$new_n5819 -000 1 -010 1 -100 1 -101 1 -.names $abc$27210$new_n4254 _zz_writeBack_MulPlugin_result_1[34] _zz_writeBack_MulPlugin_result[34] $abc$27210$new_n5642 _zz__zz_decode_RS2_2[2] $abc$27210$new_n5820 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] $abc$27210$new_n4258 $abc$27210$auto$rtlil.cc:2693:MuxGate$24461 -0110 1 -0111 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation MmuPlugin_dBusAccess_rsp_valid memory_to_writeBack_IS_DBUS_SHARING $abc$27210$auto$rtlil.cc:2693:MuxGate$24463 -0100 1 -0101 1 -0110 1 -1001 1 -1101 1 -.names memory_to_writeBack_IS_DBUS_SHARING dBus_cmd_payload_wr $abc$27210$new_n4094 MmuPlugin_dBusAccess_rsp_payload_redo MmuPlugin_dBusAccess_rsp_valid -1000 1 -1001 1 -1011 1 -.names $abc$27210$new_n5825 $abc$27210$new_n4093 CsrPlugin_pipelineLiberator_pcValids_2 CsrPlugin_pipelineLiberator_pcValids_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24467 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4316 $abc$27210$new_n5826 $abc$27210$new_n4266 $abc$27210$new_n5825 -110 1 -.names $abc$27210$new_n5830 $abc$27210$new_n5827 $abc$27210$new_n5826 -11 1 -.names $abc$27210$new_n5828 $abc$27210$new_n4637 $abc$27210$new_n5827 -10 1 -.names $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n5829 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n5828 -10000 1 -10001 1 -10010 1 -.names $abc$27210$new_n4256 memory_arbitration_isValid lastStageIsValid $abc$27210$new_n5829 -100 1 -.names $abc$27210$new_n4700 $abc$27210$new_n8208 $abc$27210$new_n5830 -00 1 -.names $abc$27210$new_n5825 DBusCachedPlugin_mmuBus_cmd_0_isStuck CsrPlugin_pipelineLiberator_pcValids_1 CsrPlugin_pipelineLiberator_pcValids_0 $abc$27210$auto$rtlil.cc:2693:MuxGate$24469 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n5825 $abc$27210$new_n4259 CsrPlugin_pipelineLiberator_pcValids_0 $abc$27210$auto$rtlil.cc:2693:MuxGate$24471 -101 1 -110 1 -111 1 -.names $abc$27210$new_n5834 $abc$27210$new_n5387 CsrPlugin_mie_MSIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24473 -001 1 -011 1 -110 1 -111 1 -.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_772 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n5834 -1111 1 -.names $abc$27210$new_n5834 $abc$27210$new_n5366 CsrPlugin_mie_MTIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24475 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5834 $abc$27210$new_n5344 CsrPlugin_mie_MEIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24477 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5838 $abc$27210$new_n4324 MmuPlugin_shared_state_1[2] MmuPlugin_shared_dBusRspStaged_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24479 -0010 1 -0110 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[2] $abc$27210$new_n5838 -110 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5840 MmuPlugin_satp_mode $abc$27210$auto$rtlil.cc:2693:MuxGate$24481 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5843 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5841 $abc$27210$new_n5840 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5842 execute_CsrPlugin_csr_384 MmuPlugin_satp_mode execute_CsrPlugin_csr_834 CsrPlugin_mcause_interrupt $abc$27210$new_n5841 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[31] CsrPlugin_mepc[31] execute_CsrPlugin_csr_833 $abc$27210$new_n5842 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] _zz_execute_BranchPlugin_branch_src2 execute_RS1[31] $abc$27210$new_n5843 -0000 1 -0010 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n4435 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n4441 IBusCachedPlugin_injector_nextPcCalc_valids_0 IBusCachedPlugin_iBusRsp_readyForError $abc$27210$auto$rtlil.cc:2693:MuxGate$24483 -10001 1 -10011 1 -11010 1 -11011 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_injector_nextPcCalc_valids_0 $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$auto$rtlil.cc:2693:MuxGate$24485 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5847 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$auto$rtlil.cc:2693:MuxGate$24487 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n5830 $abc$27210$new_n5827 $abc$27210$new_n4441 $abc$27210$new_n4258 $abc$27210$new_n4424 $abc$27210$new_n5847 -11000 1 -11001 1 -11010 1 -.names $abc$27210$new_n5849 IBusCachedPlugin_cache.io_cpu_fetch_isValid $abc$27210$new_n5847 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24489 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n5850 $abc$27210$new_n5858 $abc$27210$new_n5856 $abc$27210$new_n5855 $abc$27210$new_n5849 -11000 1 -.names $abc$27210$new_n4432 $abc$27210$new_n5852 $abc$27210$new_n5829 $abc$27210$new_n4636 $abc$27210$new_n5851 $abc$27210$new_n5850 -11000 1 -.names CsrPlugin_exceptionPendings_1 $abc$27210$new_n5827 $abc$27210$new_n5851 -11 1 -.names $abc$27210$new_n5853 IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.lineLoader_flushPending lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n5852 -10000 1 -10001 1 -10010 1 -.names IBusCachedPlugin_cache._zz_when_InstructionCache_l342 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_fetchPc_booted DebugPlugin_haltIt $abc$27210$new_n5854 $abc$27210$new_n5853 -11100 1 -.names DebugPlugin_stepIt IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.io_cpu_fetch_isValid $abc$27210$new_n5854 -101 1 -110 1 -111 1 -.names $abc$27210$new_n5827 $abc$27210$new_n5830 CsrPlugin_exceptionPendings_0 $abc$27210$new_n5855 -100 1 -101 1 -111 1 -.names $abc$27210$new_n4431 $abc$27210$new_n5857 $abc$27210$new_n4701 CsrPlugin_exceptionPendings_2 $abc$27210$new_n5856 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n4428 $abc$27210$new_n4637 $abc$27210$new_n5857 -00 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n5859 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4266 $abc$27210$new_n5858 -1100 1 -.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n5859 -10 1 -.names $abc$27210$new_n5849 IBusCachedPlugin_fetchPc_inc $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24491 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n5862 $abc$27210$new_n5857 $abc$27210$new_n4093 lastStageIsValid $abc$27210$auto$rtlil.cc:2693:MuxGate$24493 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5863 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5862 -10 1 -.names memory_arbitration_isValid $abc$27210$new_n5857 $abc$27210$new_n4431 $abc$27210$new_n4701 $abc$27210$new_n5863 -1110 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5863 $abc$27210$new_n4259 execute_arbitration_isValid $abc$27210$new_n5827 $abc$27210$auto$rtlil.cc:2693:MuxGate$24495 -00111 1 -01111 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n5866 $abc$27210$new_n4258 $abc$27210$new_n5826 $abc$27210$new_n4266 $abc$27210$auto$rtlil.cc:2693:MuxGate$24497 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names execute_arbitration_isValid $abc$27210$new_n5827 $abc$27210$new_n4259 $abc$27210$new_n5866 -110 1 -.names $abc$27210$new_n5868 CsrPlugin_interrupt_code[2] $abc$27210$new_n5869 $abc$27210$auto$rtlil.cc:2693:MuxGate$24637 -001 1 -011 1 -110 1 -111 1 -.names CsrPlugin_mstatus_MIE $abc$27210$new_n5869 CsrPlugin_mip_MTIP CsrPlugin_mie_MTIE $abc$27210$new_n5868 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -.names CsrPlugin_mip_MSIP CsrPlugin_mie_MSIE CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$27210$new_n5869 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$27210$new_n5868 CsrPlugin_interrupt_code[3] CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24641 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] CsrPlugin_mtval[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24645 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4433 CsrPlugin_mcause_interrupt CsrPlugin_hadException $abc$27210$auto$rtlil.cc:2693:MuxGate$24647 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[31] $abc$27210$new_n5881 memory_DivPlugin_div_stage_0_remainderShifted $abc$27210$auto$rtlil.cc:2693:MuxGate$24655 -00000 1 -00001 1 -00100 1 -00101 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n5506 $abc$27210$new_n5490 execute_RS1[30] execute_RS1[31] $abc$27210$new_n5881 -0000 1 -0010 1 -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[9] MmuPlugin_shared_dBusRspStaged_payload_data[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24659 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names MmuPlugin_shared_vpn_1[9] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$24661 -01 1 -10 1 -11 1 -.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_shared_vpn_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24663 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_5_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24665 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_ports_1_cache_5_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24667 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_5_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24669 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24671 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_5_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24673 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_5_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24675 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24677 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5075 MmuPlugin_ports_1_cache_5_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24679 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$27210$new_n5075 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_5_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24681 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n5898 MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] $abc$27210$new_n5895 MmuPlugin_shared_state_1[2] $abc$27210$new_n5894 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n5897 $abc$27210$new_n5896 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_shared_dBusRspStaged_payload_data[18] $abc$27210$new_n5895 -1100 1 -.names MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_shared_dBusRspStaged_payload_data[12] $abc$27210$new_n5896 -0000 1 -.names MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_shared_dBusRspStaged_payload_data[16] $abc$27210$new_n5897 -0000 1 -.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRsp_pte_A MmuPlugin_shared_dBusRspStaged_payload_error MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRsp_pte_W $abc$27210$new_n5898 -11000 1 -11010 1 -11011 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_4_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24683 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_ports_1_cache_4_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24685 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_4_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24687 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24689 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_4_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24691 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_4_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24693 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_4_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24695 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5113 MmuPlugin_ports_1_cache_4_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24697 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$27210$new_n5113 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_4_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24699 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_3_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24701 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_ports_1_cache_3_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24703 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_3_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24705 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24707 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_3_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24709 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_3_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24711 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_3_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24713 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5150 MmuPlugin_ports_1_cache_3_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24715 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$27210$new_n5150 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_3_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24717 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_2_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24719 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_ports_1_cache_2_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24721 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_2_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24723 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24725 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_2_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24727 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_2_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24729 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_2_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24731 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5187 MmuPlugin_ports_1_cache_2_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24733 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$27210$new_n5187 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_2_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24735 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_1_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24737 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_ports_1_cache_1_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24739 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_1_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24741 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24743 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_1_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24745 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_1_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24747 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_1_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24749 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5224 MmuPlugin_ports_1_cache_1_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24751 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$27210$new_n5224 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_1_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24753 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_0_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24755 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_ports_1_cache_0_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24757 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_0_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24759 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24761 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_0_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24763 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_0_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24765 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_0_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24767 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5261 MmuPlugin_ports_1_cache_0_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24769 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$27210$new_n5261 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_0_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24771 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5945 MmuPlugin_satp_ppn[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24773 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5948 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5946 $abc$27210$new_n5945 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5947 execute_CsrPlugin_csr_833 CsrPlugin_mepc[21] $abc$27210$new_n5946 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[21] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[21] $abc$27210$new_n5947 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[21] _zz__zz_execute_BranchPlugin_branch_src2_2[0] $abc$27210$new_n5948 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5298 $abc$27210$new_n5950 MmuPlugin_satp_asid[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24775 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5953 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5951 $abc$27210$new_n5950 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -1100 1 -1110 1 -.names $abc$27210$new_n5952 execute_CsrPlugin_csr_833 CsrPlugin_mepc[30] $abc$27210$new_n5951 -100 1 -101 1 -110 1 -.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[30] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[8] $abc$27210$new_n5952 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[30] _zz__zz_execute_BranchPlugin_branch_src2_2[9] $abc$27210$new_n5953 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz__zz_3_port1[1] _zz_decode_PREDICTION_CONTEXT_line_history_2[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24777 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5956 _zz_decode_PREDICTION_CONTEXT_hazard_4 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24779 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$27210$new_n5957 _zz_decode_PREDICTION_CONTEXT_hazard_3[8] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] _zz_decode_PREDICTION_CONTEXT_hazard_3[9] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] $abc$27210$new_n5956 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n5958 _zz_decode_PREDICTION_CONTEXT_hazard_3[6] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] _zz_decode_PREDICTION_CONTEXT_hazard_3[7] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] $abc$27210$new_n5957 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n5959 _zz_decode_PREDICTION_CONTEXT_hazard_3[4] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] _zz_decode_PREDICTION_CONTEXT_hazard_3[5] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] $abc$27210$new_n5958 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n5960 _zz_decode_PREDICTION_CONTEXT_hazard_3[1] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] _zz_decode_PREDICTION_CONTEXT_hazard_3[3] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] $abc$27210$new_n5959 -10000 1 -10011 1 -11100 1 -11111 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_2 $abc$27210$new_n5961 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_3[0] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] $abc$27210$new_n5960 -11100 1 -11111 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_3[2] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] $abc$27210$new_n5961 -00 1 -11 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[9] _zz_decode_PREDICTION_CONTEXT_hazard_3[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24781 -001 1 -011 1 -110 1 -111 1 -.names _zz_memory_BRANCH_CTRL[0] $abc$27210$new_n5862 execute_to_memory_PREDICTION_CONTEXT_hazard _zz_memory_BRANCH_CTRL[1] $abc$27210$new_n5964 _zz_2 -11000 1 -.names execute_to_memory_PREDICTION_CONTEXT_line_history[1] execute_to_memory_PREDICTION_CONTEXT_line_history[0] execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n5964 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_2 _zz_decode_PREDICTION_CONTEXT_hazard_2 $abc$27210$auto$rtlil.cc:2693:MuxGate$24783 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[26] DebugPlugin_disableEbreak debug_bus_cmd_payload_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24785 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -.names $abc$27210$new_n4321 debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[4] debug_bus_cmd_payload_address[2] $abc$27210$new_n5967 -1000 1 -.names debug_bus_cmd_valid DebugPlugin_debugUsed $abc$27210$auto$rtlil.cc:2693:MuxGate$24787 -01 1 -10 1 -11 1 -.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[4] DebugPlugin_stepIt $abc$27210$auto$rtlil.cc:2693:MuxGate$24789 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[24] DebugPlugin_resetIt debug_bus_cmd_payload_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24791 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -.names $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_refilling $abc$27210$new_n4090 $abc$27210$new_n8224 $abc$27210$auto$rtlil.cc:2693:MuxGate$24807 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_exception $abc$27210$new_n4090 $abc$27210$new_n5973 $abc$27210$new_n8224 $abc$27210$auto$rtlil.cc:2693:MuxGate$24811 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$27210$new_n5976 $abc$27210$new_n5974 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_exception $abc$27210$new_n5973 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_exception $abc$27210$new_n5975 $abc$27210$new_n5974 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_exception MmuPlugin_ports_1_cache_5_exception $abc$27210$new_n5975 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_exception MmuPlugin_ports_1_cache_3_exception $abc$27210$new_n5976 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n5978 $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_allowWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24815 -001 1 -010 1 -011 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4090 $abc$27210$new_n4085 $abc$27210$new_n5979 MmuPlugin_ports_1_cache_4_allowWrite $abc$27210$new_n5978 -11010 1 -11011 1 -11100 1 -11110 1 -.names $abc$27210$new_n5980 $abc$27210$new_n3943 $abc$27210$new_n4088 MmuPlugin_ports_1_cache_1_allowWrite $abc$27210$new_n5981 $abc$27210$new_n5979 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_allowWrite MmuPlugin_ports_1_cache_3_allowWrite $abc$27210$new_n5980 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_allowWrite MmuPlugin_ports_1_cache_5_allowWrite $abc$27210$new_n5981 -000 1 -010 1 -100 1 -101 1 -.names $abc$27210$new_n5983 $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24819 -001 1 -010 1 -011 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4090 $abc$27210$new_n4085 $abc$27210$new_n8123 $abc$27210$new_n5991 $abc$27210$new_n5983 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_5_allowRead $abc$27210$new_n5989 MmuPlugin_ports_1_cache_5_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5988 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_allowRead MmuPlugin_ports_1_cache_0_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5989 -1000 1 -1001 1 -1010 1 -.names MmuPlugin_ports_1_cache_4_allowRead MmuPlugin_ports_1_cache_4_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5991 -000 1 -001 1 -010 1 -.names $abc$27210$new_n4092 $abc$27210$new_n4090 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$auto$rtlil.cc:2693:MuxGate$24821 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n5994 dBus_cmd_payload_uncached DebugPlugin_godmode dataCache_1.io_cpu_memory_isWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24825 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n3940 $abc$27210$new_n8126 $abc$27210$new_n4111 $abc$27210$new_n4106 $abc$27210$new_n5994 -1100 1 -.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] $abc$27210$new_n5998 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4092 $abc$27210$new_n8126 dBus_cmd_payload_address[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24827 -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.tagsWriteCmd_payload_data_error dataCache_1.loader_counter_willOverflow dataCache_1.loader_error dataCache_1.io_cpu_execute_refilling $abc$27210$auto$rtlil.cc:2693:MuxGate$24841 -1001 1 -1010 1 -1011 1 -.names dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] dataCache_1.loader_counter_value[2] $abc$27210$new_n6003 dataCache_1.loader_counter_willOverflow -1111 1 -.names dBus_rsp_valid dataCache_1.io_cpu_execute_refilling $abc$27210$new_n6003 -11 1 -.names dataCache_1.loader_error dBus_rsp_valid dBus_rsp_payload_error dataCache_1.tagsWriteCmd_payload_data_error -011 1 -100 1 -101 1 -110 1 -111 1 -.names dataCache_1.loader_counter_willOverflow dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4095 dBus_cmd_payload_size[2] dBus_cmd_ready $abc$27210$auto$rtlil.cc:2693:MuxGate$24843 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names dataCache_1.stageB_flusher_counter[6] $abc$27210$new_n6008 $abc$27210$new_n6007 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_start $abc$27210$auto$rtlil.cc:2693:MuxGate$24845 -00100 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dataCache_1.stageB_flusher_counter[5] $abc$27210$new_n4228 $abc$27210$new_n6007 -11 1 -.names execute_RS1[11] $abc$27210$new_n4233 $abc$27210$new_n6008 -11 1 -.names dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_waitDone dataCache_1.stageB_flusher_counter[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24847 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.memCmdSent dBus_cmd_ready $abc$27210$auto$rtlil.cc:2693:MuxGate$24849 -101 1 -110 1 -111 1 -.names $abc$27210$new_n4095 $abc$27210$new_n6012 $abc$27210$new_n4100 dBus_cmd_valid -100 1 -.names dBus_cmd_payload_wr dBus_cmd_payload_uncached dataCache_1.memCmdSent dataCache_1.stageB_waysHit $abc$27210$new_n6012 -0001 1 -0010 1 -0011 1 -0110 1 -0111 1 -1110 1 -1111 1 -.names IBusCachedPlugin_cache.lineLoader_wordIndex[2] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid IBusCachedPlugin_cache.lineLoader_wordIndex[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24851 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$27210$new_n6015 IBusCachedPlugin_cache.lineLoader_cmdSent iBus_cmd_ready IBusCachedPlugin_cache.lineLoader_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24853 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names IBusCachedPlugin_cache.lineLoader_wordIndex[2] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid IBusCachedPlugin_cache.lineLoader_wordIndex[1] $abc$27210$new_n6015 -1111 1 -.names IBusCachedPlugin_cache.when_InstructionCache_l351 $abc$27210$new_n5858 IBusCachedPlugin_cache.lineLoader_flushPending $abc$27210$auto$rtlil.cc:2693:MuxGate$24855 -001 1 -010 1 -011 1 -.names IBusCachedPlugin_cache.lineLoader_flushPending IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.when_InstructionCache_l351 -100 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.lineLoader_valid $abc$27210$new_n6015 $abc$27210$auto$rtlil.cc:2693:MuxGate$24857 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[31] IBusCachedPlugin_cache._zz_banks_0_port1[31] _zz_6 $abc$27210$auto$rtlil.cc:2693:MuxGate$24859 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24861 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] IBusCachedPlugin_cache.decodeStage_hit_tags_0_error $abc$27210$auto$rtlil.cc:2693:MuxGate$24863 -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24865 -001 1 -011 1 -110 1 -111 1 -.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] $abc$27210$new_n4960 $abc$27210$new_n4261 memory_DivPlugin_accumulator[31] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24869 -00010 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names memory_DivPlugin_div_done $abc$27210$new_n4904 memory_DivPlugin_div_counter_value[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24871 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$27210$new_n4439 $abc$27210$new_n6027 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] $abc$27210$new_n6026 $abc$27210$new_n6029 $abc$27210$auto$rtlil.cc:2693:MuxGate$24875 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -.names $abc$27210$new_n4423 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 $abc$27210$new_n6026 -10010 1 -10100 1 -10101 1 -10111 1 -11001 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n6028 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] $abc$27210$new_n6027 -1010 1 -1011 1 -1100 1 -1110 1 -.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] $abc$27210$new_n4444 $abc$27210$new_n6028 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n6030 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[31] $abc$27210$new_n6029 -0000 1 -0001 1 -0010 1 -.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[31] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[31] $abc$27210$new_n6030 -10000 1 -10001 1 -10011 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] CsrPlugin_mcause_exceptionCode[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24879 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] CsrPlugin_interrupt_code[3] CsrPlugin_mcause_exceptionCode[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24881 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24883 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] iBus_cmd_payload_address[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24887 -001 1 -011 1 -110 1 -111 1 -.names lastStageIsValid $abc$27210$new_n4256 HazardSimplePlugin_writeBackWrites_payload_data[1] DebugPlugin_busReadDataReg[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24891 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n6040 MmuPlugin_dBusAccess_rsp_payload_data[1] _zz_writeBack_DBusCachedPlugin_rspShifted_3 HazardSimplePlugin_writeBackWrites_payload_data[1] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n6038 MmuPlugin_dBusAccess_rsp_payload_data[17] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[1] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1110 1 -.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[25] $abc$27210$new_n5778 $abc$27210$new_n6039 $abc$27210$new_n6038 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names dBus_cmd_payload_uncached dBus_rsp_payload_data[1] dataCache_1.stageB_dataMux[1] $abc$27210$new_n6039 -000 1 -010 1 -100 1 -101 1 -.names $abc$27210$new_n4254 _zz__zz_decode_RS2_2[1] $abc$27210$new_n6041 $abc$27210$new_n6040 -000 1 -010 1 -100 1 -101 1 -.names _zz_writeBack_MulPlugin_result_1[33] _zz_writeBack_MulPlugin_result[33] _zz_writeBack_MulPlugin_result_1[32] _zz_writeBack_MulPlugin_result[32] $abc$27210$new_n6041 -0011 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1111 1 -.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[31] HazardSimplePlugin_writeBackWrites_payload_data[31] debug_bus_rsp_data[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24893 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n6045 $abc$27210$new_n6044 _zz__zz_decode_RS2_2[31] HazardSimplePlugin_writeBackWrites_payload_data[31] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[63] _zz_writeBack_MulPlugin_result_1[62] $abc$27210$new_n5626 $abc$27210$new_n6044 -0011 1 -0100 1 -0101 1 -0110 1 -1000 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n6046 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[31] $abc$27210$new_n6045 -001 1 -010 1 -011 1 -.names $abc$27210$new_n5654 $abc$27210$new_n5647 $abc$27210$new_n5650 _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n6046 -1000 1 -1010 1 -1011 1 -.names $abc$27210$new_n4635 execute_to_memory_PC[31] DBusCachedPlugin_redoBranch_payload[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24897 -001 1 -011 1 -110 1 -111 1 -.names when_MmuPlugin_l281_1 $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$24899 -01 1 -10 1 -11 1 -.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] $abc$27210$new_n4102 $abc$27210$new_n5569 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$auto$rtlil.cc:2693:MuxGate$24903 -00111 1 -01111 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] $abc$27210$new_n4696 $abc$27210$auto$rtlil.cc:2693:MuxGate$24905 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[30] dataCache_1._zz_ways_0_data_port0[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$21679 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[29] dataCache_1._zz_ways_0_data_port0[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$21681 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[28] dataCache_1._zz_ways_0_data_port0[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$21683 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[27] dataCache_1._zz_ways_0_data_port0[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$21685 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[26] dataCache_1._zz_ways_0_data_port0[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$21687 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[25] dataCache_1._zz_ways_0_data_port0[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$21689 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[24] dataCache_1._zz_ways_0_data_port0[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$21691 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[23] dataCache_1._zz_ways_0_data_port0[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$21693 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[22] dataCache_1._zz_ways_0_data_port0[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$21695 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[21] dataCache_1._zz_ways_0_data_port0[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$21697 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[20] dataCache_1._zz_ways_0_data_port0[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$21699 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[19] dataCache_1._zz_ways_0_data_port0[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$21701 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[18] dataCache_1._zz_ways_0_data_port0[18] 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_zz_memory_MUL_LOW_1[18] _zz_memory_MUL_LOW_4[18] _zz_memory_MUL_LOW_6[18] $abc$27210$new_n6234 -00000 1 -00001 1 -00010 1 -00100 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11100 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[18] $abc$27210$new_n6236 $abc$27210$auto$rtlil.cc:2693:MuxGate$21907 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6119 _zz_memory_MUL_LOW_1[17] _zz_memory_MUL_LOW_4[17] _zz_memory_MUL_LOW_6[17] $abc$27210$new_n6120 $abc$27210$new_n6236 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10011 1 -10101 1 -11001 1 -11110 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[17] $abc$27210$new_n6238 $abc$27210$auto$rtlil.cc:2693:MuxGate$21909 -001 1 -011 1 -110 1 -111 1 -.names _zz_memory_MUL_LOW_1[17] _zz_memory_MUL_LOW_4[17] _zz_memory_MUL_LOW_6[17] $abc$27210$new_n6120 $abc$27210$new_n6238 -0000 1 -0011 1 -0101 1 -0110 1 -1001 1 -1010 1 -1100 1 -1111 1 -.names $abc$27210$new_n4093 _zz_memory_MUL_LOW_1[16] _zz_memory_MUL_LOW_4[16] _zz_memory_MUL_LOW_6[16] _zz__zz_decode_RS2_2[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$21911 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[15] _zz_memory_MUL_LOW_1[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$21913 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[14] _zz_memory_MUL_LOW_1[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$21915 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[13] _zz_memory_MUL_LOW_1[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$21917 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[12] _zz_memory_MUL_LOW_1[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$21919 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[11] _zz_memory_MUL_LOW_1[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21921 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[10] _zz_memory_MUL_LOW_1[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21923 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[9] _zz_memory_MUL_LOW_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21925 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[8] _zz_memory_MUL_LOW_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21927 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[7] _zz_memory_MUL_LOW_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21929 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[6] _zz_memory_MUL_LOW_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21931 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[5] _zz_memory_MUL_LOW_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21933 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[4] _zz_memory_MUL_LOW_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21935 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[3] _zz_memory_MUL_LOW_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21937 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[2] _zz_memory_MUL_LOW_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21939 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[1] _zz_memory_MUL_LOW_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21941 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[0] _zz_memory_MUL_LOW_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21943 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[63] execute_to_memory_MUL_HH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22005 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[62] execute_to_memory_MUL_HH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22007 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[61] execute_to_memory_MUL_HH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22009 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[60] execute_to_memory_MUL_HH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22011 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[59] execute_to_memory_MUL_HH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22013 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[58] execute_to_memory_MUL_HH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22015 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[57] execute_to_memory_MUL_HH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22017 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[56] execute_to_memory_MUL_HH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22019 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[55] execute_to_memory_MUL_HH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22021 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[54] execute_to_memory_MUL_HH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22023 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[53] execute_to_memory_MUL_HH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22025 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[52] execute_to_memory_MUL_HH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22027 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[51] execute_to_memory_MUL_HH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22029 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[50] execute_to_memory_MUL_HH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22031 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[49] execute_to_memory_MUL_HH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22033 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[48] execute_to_memory_MUL_HH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22035 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[47] execute_to_memory_MUL_HH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22037 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[46] execute_to_memory_MUL_HH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22039 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[45] execute_to_memory_MUL_HH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22041 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[44] execute_to_memory_MUL_HH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22043 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[43] execute_to_memory_MUL_HH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22045 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[42] execute_to_memory_MUL_HH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22047 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[41] execute_to_memory_MUL_HH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22049 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[40] execute_to_memory_MUL_HH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22051 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[39] execute_to_memory_MUL_HH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22053 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[38] execute_to_memory_MUL_HH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22055 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[37] execute_to_memory_MUL_HH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22057 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[36] execute_to_memory_MUL_HH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22059 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[35] execute_to_memory_MUL_HH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22061 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[34] execute_to_memory_MUL_HH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22063 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[33] execute_to_memory_MUL_HH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22065 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[32] execute_to_memory_MUL_HH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22067 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[31] execute_MUL_HH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22071 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[30] execute_MUL_HH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22073 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[29] execute_MUL_HH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22075 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[28] execute_MUL_HH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22077 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[27] execute_MUL_HH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22079 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[26] execute_MUL_HH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22081 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[25] execute_MUL_HH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22083 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[24] execute_MUL_HH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22085 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[23] execute_MUL_HH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22087 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[22] execute_MUL_HH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22089 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[21] execute_MUL_HH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22091 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[20] execute_MUL_HH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22093 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[19] execute_MUL_HH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22095 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[18] execute_MUL_HH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22097 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[17] execute_MUL_HH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22099 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[16] execute_MUL_HH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22101 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[15] execute_MUL_HH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22103 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[14] execute_MUL_HH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22105 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[13] execute_MUL_HH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22107 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[12] execute_MUL_HH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22109 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[11] execute_MUL_HH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22111 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[10] execute_MUL_HH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22113 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[9] execute_MUL_HH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22115 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[8] execute_MUL_HH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22117 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[7] execute_MUL_HH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22119 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[6] execute_MUL_HH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22121 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[5] execute_MUL_HH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22123 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[4] execute_MUL_HH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22125 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[3] execute_MUL_HH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22127 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[2] execute_MUL_HH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22129 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[1] execute_MUL_HH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22131 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[0] execute_MUL_HH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22133 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[48] execute_MUL_HL[32] $abc$27210$auto$rtlil.cc:2693:MuxGate$22135 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[47] execute_MUL_HL[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22137 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[46] execute_MUL_HL[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22139 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[45] execute_MUL_HL[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22141 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[44] execute_MUL_HL[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22143 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[43] execute_MUL_HL[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22145 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[42] execute_MUL_HL[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22147 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[41] execute_MUL_HL[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22149 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[40] execute_MUL_HL[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22151 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[39] execute_MUL_HL[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22153 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[38] execute_MUL_HL[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22155 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[37] execute_MUL_HL[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22157 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[36] execute_MUL_HL[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22159 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[35] execute_MUL_HL[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22161 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[34] execute_MUL_HL[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22163 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[33] execute_MUL_HL[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22165 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[32] execute_MUL_HL[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22167 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[31] execute_MUL_HL[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22169 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[30] execute_MUL_HL[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22171 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[29] execute_MUL_HL[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22173 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[28] execute_MUL_HL[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22175 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[27] execute_MUL_HL[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22177 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[26] execute_MUL_HL[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22179 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[25] execute_MUL_HL[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22181 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[24] execute_MUL_HL[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22183 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[23] execute_MUL_HL[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22185 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[22] execute_MUL_HL[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22187 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[21] execute_MUL_HL[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22189 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[20] execute_MUL_HL[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22191 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[19] execute_MUL_HL[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22193 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[18] execute_MUL_HL[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22195 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[17] execute_MUL_HL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22197 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[16] execute_MUL_HL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22199 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[48] execute_MUL_LH[32] $abc$27210$auto$rtlil.cc:2693:MuxGate$22201 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[47] execute_MUL_LH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22203 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[46] execute_MUL_LH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22205 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[45] execute_MUL_LH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22207 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[44] execute_MUL_LH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22209 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[43] execute_MUL_LH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22211 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[42] execute_MUL_LH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22213 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[41] execute_MUL_LH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22215 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[40] execute_MUL_LH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22217 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[39] execute_MUL_LH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22219 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[38] execute_MUL_LH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22221 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[37] execute_MUL_LH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22223 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[36] execute_MUL_LH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22225 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[35] execute_MUL_LH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22227 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[34] execute_MUL_LH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22229 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[33] execute_MUL_LH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22231 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[32] execute_MUL_LH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22233 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[31] execute_MUL_LH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22235 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[30] execute_MUL_LH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22237 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[29] execute_MUL_LH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22239 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[28] execute_MUL_LH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22241 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[27] execute_MUL_LH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22243 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[26] execute_MUL_LH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22245 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[25] execute_MUL_LH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22247 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[24] execute_MUL_LH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22249 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[23] execute_MUL_LH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22251 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[22] execute_MUL_LH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22253 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[21] execute_MUL_LH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22255 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[20] execute_MUL_LH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22257 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[19] execute_MUL_LH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22259 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[18] execute_MUL_LH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22261 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[17] execute_MUL_LH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22263 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[16] execute_MUL_LH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22265 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[30] execute_MUL_LL[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22267 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[29] execute_MUL_LL[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22269 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[28] execute_MUL_LL[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22271 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[27] execute_MUL_LL[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22273 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[26] execute_MUL_LL[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22275 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[25] execute_MUL_LL[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22277 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[24] execute_MUL_LL[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22279 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[23] execute_MUL_LL[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22281 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[22] execute_MUL_LL[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22283 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[21] execute_MUL_LL[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22285 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[20] execute_MUL_LL[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22287 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[19] execute_MUL_LL[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22289 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[18] execute_MUL_LL[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22291 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[17] execute_MUL_LL[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22293 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[16] execute_MUL_LL[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22295 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[15] execute_MUL_LL[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22297 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[14] execute_MUL_LL[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22299 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[13] execute_MUL_LL[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22301 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[12] execute_MUL_LL[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22303 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[11] execute_MUL_LL[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22305 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[10] execute_MUL_LL[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22307 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[9] execute_MUL_LL[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22309 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[8] execute_MUL_LL[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22311 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[7] execute_MUL_LL[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22313 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[6] execute_MUL_LL[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22315 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[5] execute_MUL_LL[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22317 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[4] execute_MUL_LL[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22319 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[3] execute_MUL_LL[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22321 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[2] execute_MUL_LL[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22323 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[1] execute_MUL_LL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22325 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[0] execute_MUL_LL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22327 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[1] $abc$27210$new_n6418 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22329 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n6427 $abc$27210$new_n6419 $abc$27210$new_n6421 $abc$27210$new_n6418 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6425 $abc$27210$new_n6420 $abc$27210$new_n6421 $abc$27210$new_n6419 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6093 $abc$27210$new_n6421 $abc$27210$new_n6424 $abc$27210$new_n6420 -010 1 -011 1 -100 1 -110 1 -.names _zz_execute_SHIFT_CTRL[1] _zz_execute_SHIFT_CTRL[0] $abc$27210$new_n6422 $abc$27210$new_n6421 -110 1 -.names $abc$27210$new_n6423 $abc$27210$new_n5407 $abc$27210$new_n5843 $abc$27210$new_n6422 -001 1 -011 1 -110 1 -111 1 -.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$27210$new_n6423 -10 1 -.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6422 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6424 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n6426 _zz_execute_to_memory_PC[2] _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] $abc$27210$new_n6425 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] execute_RS2[2] _zz__zz_execute_BranchPlugin_branch_src2_2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$27210$new_n6426 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n6428 _zz_execute_SRC2_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[2] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6427 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] execute_RS2[3] _zz__zz_execute_BranchPlugin_branch_src2_2[2] _zz_execute_to_memory_PC[3] $abc$27210$new_n6428 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$27210$new_n6430 _zz_execute_SRC2_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[3] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6429 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] execute_RS2[4] _zz__zz_execute_BranchPlugin_branch_src2_2[3] _zz_execute_to_memory_PC[4] $abc$27210$new_n6430 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[2] $abc$27210$new_n6432 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22331 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n6427 $abc$27210$new_n6433 $abc$27210$new_n6421 $abc$27210$new_n6432 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6425 $abc$27210$new_n6434 $abc$27210$new_n6421 $abc$27210$new_n6433 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6093 $abc$27210$new_n6435 $abc$27210$new_n6437 $abc$27210$new_n6421 $abc$27210$new_n6434 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6436 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6435 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n6423 $abc$27210$new_n5397 $abc$27210$new_n5412 $abc$27210$new_n6436 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n6090 $abc$27210$new_n6422 $abc$27210$new_n6437 -10 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[3] $abc$27210$new_n6439 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22333 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 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DBusCachedPlugin_exceptionBus_payload_badAddr[24] $abc$27210$new_n6629 $abc$27210$auto$rtlil.cc:2693:MuxGate$22403 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6630 memory_DivPlugin_div_result[24] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] execute_to_memory_IS_DIV $abc$27210$new_n6629 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6631 _zz_decode_RS2_3[7] $abc$27210$new_n6630 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] _zz_decode_RS2_3[24] $abc$27210$new_n6631 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[23] $abc$27210$new_n6633 $abc$27210$auto$rtlil.cc:2693:MuxGate$22405 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6634 memory_DivPlugin_div_result[23] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] execute_to_memory_IS_DIV $abc$27210$new_n6633 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6635 _zz_decode_RS2_3[8] $abc$27210$new_n6634 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] _zz_decode_RS2_3[23] $abc$27210$new_n6635 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[22] $abc$27210$new_n6637 $abc$27210$auto$rtlil.cc:2693:MuxGate$22407 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6638 memory_DivPlugin_div_result[22] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] execute_to_memory_IS_DIV $abc$27210$new_n6637 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6639 _zz_decode_RS2_3[9] $abc$27210$new_n6638 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] _zz_decode_RS2_3[22] $abc$27210$new_n6639 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[21] $abc$27210$new_n6641 $abc$27210$auto$rtlil.cc:2693:MuxGate$22409 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6642 memory_DivPlugin_div_result[21] execute_to_memory_IS_DIV DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n6641 -00000 1 -00010 1 -00100 1 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6643 _zz_decode_RS2_3[10] $abc$27210$new_n6642 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] _zz_decode_RS2_3[21] $abc$27210$new_n6643 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[20] $abc$27210$new_n6645 $abc$27210$auto$rtlil.cc:2693:MuxGate$22411 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6646 memory_DivPlugin_div_result[20] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] execute_to_memory_IS_DIV $abc$27210$new_n6645 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6647 _zz_decode_RS2_3[11] $abc$27210$new_n6646 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] _zz_decode_RS2_3[20] $abc$27210$new_n6647 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[19] $abc$27210$new_n6649 $abc$27210$auto$rtlil.cc:2693:MuxGate$22413 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6650 memory_DivPlugin_div_result[19] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] execute_to_memory_IS_DIV $abc$27210$new_n6649 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6651 _zz_decode_RS2_3[12] $abc$27210$new_n6650 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] _zz_decode_RS2_3[19] $abc$27210$new_n6651 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n6653 $abc$27210$auto$rtlil.cc:2693:MuxGate$22415 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6654 memory_DivPlugin_div_result[18] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] execute_to_memory_IS_DIV $abc$27210$new_n6653 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6655 _zz_decode_RS2_3[13] $abc$27210$new_n6654 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] _zz_decode_RS2_3[18] $abc$27210$new_n6655 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[17] $abc$27210$new_n6657 $abc$27210$auto$rtlil.cc:2693:MuxGate$22417 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6658 memory_DivPlugin_div_result[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] execute_to_memory_IS_DIV $abc$27210$new_n6657 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6659 _zz_decode_RS2_3[14] $abc$27210$new_n6658 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] _zz_decode_RS2_3[17] $abc$27210$new_n6659 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[16] $abc$27210$new_n6661 $abc$27210$auto$rtlil.cc:2693:MuxGate$22419 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6662 memory_DivPlugin_div_result[16] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] execute_to_memory_IS_DIV $abc$27210$new_n6661 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6663 _zz_decode_RS2_3[15] $abc$27210$new_n6662 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] _zz_decode_RS2_3[16] $abc$27210$new_n6663 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[15] $abc$27210$new_n6665 $abc$27210$auto$rtlil.cc:2693:MuxGate$22421 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6666 memory_DivPlugin_div_result[15] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] execute_to_memory_IS_DIV $abc$27210$new_n6665 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6667 _zz_decode_RS2_3[16] $abc$27210$new_n6666 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] _zz_decode_RS2_3[15] $abc$27210$new_n6667 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[14] $abc$27210$new_n6669 $abc$27210$auto$rtlil.cc:2693:MuxGate$22423 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6670 memory_DivPlugin_div_result[14] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] execute_to_memory_IS_DIV $abc$27210$new_n6669 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6671 _zz_decode_RS2_3[17] $abc$27210$new_n6670 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] _zz_decode_RS2_3[14] $abc$27210$new_n6671 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[13] $abc$27210$new_n6673 $abc$27210$auto$rtlil.cc:2693:MuxGate$22425 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6674 memory_DivPlugin_div_result[13] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] execute_to_memory_IS_DIV $abc$27210$new_n6673 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6675 _zz_decode_RS2_3[18] $abc$27210$new_n6674 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] _zz_decode_RS2_3[13] $abc$27210$new_n6675 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[12] $abc$27210$new_n6677 $abc$27210$auto$rtlil.cc:2693:MuxGate$22427 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6678 memory_DivPlugin_div_result[12] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] execute_to_memory_IS_DIV $abc$27210$new_n6677 -00000 1 -00001 1 -00100 1 -00101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6679 _zz_decode_RS2_3[19] $abc$27210$new_n6678 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] _zz_decode_RS2_3[12] $abc$27210$new_n6679 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[11] $abc$27210$new_n6681 $abc$27210$auto$rtlil.cc:2693:MuxGate$22429 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6682 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] memory_DivPlugin_div_result[11] execute_to_memory_IS_DIV $abc$27210$new_n6681 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6683 _zz_decode_RS2_3[20] $abc$27210$new_n6682 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] _zz_decode_RS2_3[11] $abc$27210$new_n6683 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[10] $abc$27210$new_n6685 $abc$27210$auto$rtlil.cc:2693:MuxGate$22431 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6686 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] memory_DivPlugin_div_result[10] execute_to_memory_IS_DIV $abc$27210$new_n6685 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6687 _zz_decode_RS2_3[21] $abc$27210$new_n6686 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] _zz_decode_RS2_3[10] $abc$27210$new_n6687 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[9] $abc$27210$new_n6689 $abc$27210$auto$rtlil.cc:2693:MuxGate$22433 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6690 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] memory_DivPlugin_div_result[9] execute_to_memory_IS_DIV $abc$27210$new_n6689 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6691 _zz_decode_RS2_3[22] $abc$27210$new_n6690 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] _zz_decode_RS2_3[9] $abc$27210$new_n6691 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n6693 $abc$27210$auto$rtlil.cc:2693:MuxGate$22435 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6694 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] memory_DivPlugin_div_result[8] execute_to_memory_IS_DIV $abc$27210$new_n6693 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6695 _zz_decode_RS2_3[23] $abc$27210$new_n6694 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] _zz_decode_RS2_3[8] $abc$27210$new_n6695 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n6697 $abc$27210$auto$rtlil.cc:2693:MuxGate$22437 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6698 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] memory_DivPlugin_div_result[7] execute_to_memory_IS_DIV $abc$27210$new_n6697 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6699 _zz_decode_RS2_3[24] $abc$27210$new_n6698 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] _zz_decode_RS2_3[7] $abc$27210$new_n6699 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n6701 $abc$27210$auto$rtlil.cc:2693:MuxGate$22439 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6702 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] memory_DivPlugin_div_result[6] execute_to_memory_IS_DIV $abc$27210$new_n6701 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6703 _zz_decode_RS2_3[25] $abc$27210$new_n6702 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] _zz_decode_RS2_3[6] $abc$27210$new_n6703 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[5] $abc$27210$new_n6705 $abc$27210$auto$rtlil.cc:2693:MuxGate$22441 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6706 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] memory_DivPlugin_div_result[5] execute_to_memory_IS_DIV $abc$27210$new_n6705 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6707 _zz_decode_RS2_3[26] $abc$27210$new_n6706 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] _zz_decode_RS2_3[5] $abc$27210$new_n6707 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[4] $abc$27210$new_n6709 $abc$27210$auto$rtlil.cc:2693:MuxGate$22443 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6710 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] memory_DivPlugin_div_result[4] execute_to_memory_IS_DIV $abc$27210$new_n6709 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6711 _zz_decode_RS2_3[27] $abc$27210$new_n6710 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] _zz_decode_RS2_3[4] $abc$27210$new_n6711 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n6713 $abc$27210$auto$rtlil.cc:2693:MuxGate$22445 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6714 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] memory_DivPlugin_div_result[3] execute_to_memory_IS_DIV $abc$27210$new_n6713 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6715 _zz_decode_RS2_3[28] $abc$27210$new_n6714 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] _zz_decode_RS2_3[3] $abc$27210$new_n6715 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[2] $abc$27210$new_n6717 $abc$27210$auto$rtlil.cc:2693:MuxGate$22447 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6718 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] memory_DivPlugin_div_result[2] execute_to_memory_IS_DIV $abc$27210$new_n6717 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6719 _zz_decode_RS2_3[29] $abc$27210$new_n6718 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] _zz_decode_RS2_3[2] $abc$27210$new_n6719 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n6721 $abc$27210$auto$rtlil.cc:2693:MuxGate$22449 -000 1 -010 1 -110 1 -111 1 -.names memory_arbitration_isValid $abc$27210$new_n6722 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] memory_DivPlugin_div_result[1] execute_to_memory_IS_DIV $abc$27210$new_n6721 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6723 _zz_decode_RS2_3[30] $abc$27210$new_n6722 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] _zz_decode_RS2_3[1] $abc$27210$new_n6723 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[0] $abc$27210$new_n6725 $abc$27210$auto$rtlil.cc:2693:MuxGate$22451 -000 1 -010 1 -110 1 -111 1 -.names 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-11110 1 -11111 1 -.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6986 $abc$27210$new_n6987 $abc$27210$new_n6985 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$27210$new_n5397 $abc$27210$new_n6749 $abc$27210$new_n6748 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6986 -0000 1 -0001 1 -0011 1 -0101 1 -0110 1 -0111 1 -1010 1 -1100 1 -.names $abc$27210$new_n5397 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6425 $abc$27210$new_n6987 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1101 1 -1110 1 -.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[0] MmuPlugin_shared_vpn_1[0] $abc$27210$new_n6988 -000 1 -010 1 -100 1 -101 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] $abc$27210$new_n6990 $abc$27210$auto$rtlil.cc:2693:MuxGate$22511 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4327 $abc$27210$new_n6991 $abc$27210$new_n4264 $abc$27210$new_n5400 $abc$27210$new_n6990 -0010 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6091 $abc$27210$new_n6992 $abc$27210$new_n6991 -1000 1 -1001 1 -1100 1 -1110 1 -.names _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6093 $abc$27210$new_n5402 $abc$27210$new_n6992 -0000 1 -0011 1 -0111 1 -1001 1 -1010 1 -1011 1 -1100 1 -1111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8163 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22513 -010 1 -011 1 -101 1 -111 1 -.names decode_to_execute_SRC_LESS_UNSIGNED $abc$27210$new_n6999 $abc$27210$new_n5843 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6997 $abc$27210$new_n6996 -00000 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01110 1 -01111 1 -10000 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6998 $abc$27210$new_n5953 $abc$27210$new_n6802 $abc$27210$new_n6732 $abc$27210$new_n6997 -00000 1 -00001 1 -00011 1 -00101 1 -01010 1 -01100 1 -01110 1 -01111 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$27210$new_n6999 $abc$27210$new_n5843 $abc$27210$new_n6998 -01 1 -10 1 -.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz_execute_to_memory_PC[31] execute_RS2[31] $abc$27210$new_n6999 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6090 $abc$27210$new_n5407 $abc$27210$new_n7001 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1101 1 -1110 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[30] execute_to_memory_MEMORY_STORE_DATA_RF[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22515 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[29] execute_to_memory_MEMORY_STORE_DATA_RF[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22517 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[28] execute_to_memory_MEMORY_STORE_DATA_RF[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22519 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[27] execute_to_memory_MEMORY_STORE_DATA_RF[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22521 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[26] execute_to_memory_MEMORY_STORE_DATA_RF[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22523 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[25] execute_to_memory_MEMORY_STORE_DATA_RF[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22525 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[24] execute_to_memory_MEMORY_STORE_DATA_RF[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22527 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[23] execute_to_memory_MEMORY_STORE_DATA_RF[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22529 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[22] execute_to_memory_MEMORY_STORE_DATA_RF[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22531 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[21] execute_to_memory_MEMORY_STORE_DATA_RF[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22533 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[20] execute_to_memory_MEMORY_STORE_DATA_RF[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22535 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[19] execute_to_memory_MEMORY_STORE_DATA_RF[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22537 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[18] execute_to_memory_MEMORY_STORE_DATA_RF[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22539 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[17] execute_to_memory_MEMORY_STORE_DATA_RF[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22541 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[16] execute_to_memory_MEMORY_STORE_DATA_RF[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22543 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[15] execute_to_memory_MEMORY_STORE_DATA_RF[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22545 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[14] execute_to_memory_MEMORY_STORE_DATA_RF[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22547 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[13] execute_to_memory_MEMORY_STORE_DATA_RF[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22549 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[12] execute_to_memory_MEMORY_STORE_DATA_RF[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22551 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[11] execute_to_memory_MEMORY_STORE_DATA_RF[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22553 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[10] execute_to_memory_MEMORY_STORE_DATA_RF[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22555 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[9] execute_to_memory_MEMORY_STORE_DATA_RF[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22557 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[8] execute_to_memory_MEMORY_STORE_DATA_RF[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22559 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[7] execute_to_memory_MEMORY_STORE_DATA_RF[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22561 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[6] execute_to_memory_MEMORY_STORE_DATA_RF[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22563 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[5] execute_to_memory_MEMORY_STORE_DATA_RF[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22565 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[4] execute_to_memory_MEMORY_STORE_DATA_RF[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22567 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[3] execute_to_memory_MEMORY_STORE_DATA_RF[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22569 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[2] execute_to_memory_MEMORY_STORE_DATA_RF[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22571 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[1] execute_to_memory_MEMORY_STORE_DATA_RF[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22573 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_data[0] execute_to_memory_MEMORY_STORE_DATA_RF[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22575 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[30] $abc$27210$new_n7034 $abc$27210$auto$rtlil.cc:2693:MuxGate$22577 -000 1 -010 1 -110 1 -111 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[30] execute_RS2[6] execute_RS2[14] $abc$27210$new_n7034 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[29] $abc$27210$new_n7036 $abc$27210$auto$rtlil.cc:2693:MuxGate$22579 -000 1 -010 1 -110 1 -111 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[29] execute_RS2[5] execute_RS2[13] $abc$27210$new_n7036 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[28] $abc$27210$new_n7038 $abc$27210$auto$rtlil.cc:2693:MuxGate$22581 -000 1 -010 1 -110 1 -111 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[28] execute_RS2[4] execute_RS2[12] $abc$27210$new_n7038 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[27] $abc$27210$new_n7040 $abc$27210$auto$rtlil.cc:2693:MuxGate$22583 -000 1 -010 1 -110 1 -111 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[27] execute_RS2[3] execute_RS2[11] $abc$27210$new_n7040 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[26] $abc$27210$new_n7042 $abc$27210$auto$rtlil.cc:2693:MuxGate$22585 -000 1 -010 1 -110 1 -111 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[26] execute_RS2[2] execute_RS2[10] $abc$27210$new_n7042 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[25] $abc$27210$new_n7044 $abc$27210$auto$rtlil.cc:2693:MuxGate$22587 -000 1 -010 1 -110 1 -111 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[25] execute_RS2[1] execute_RS2[9] $abc$27210$new_n7044 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[24] $abc$27210$new_n7046 $abc$27210$auto$rtlil.cc:2693:MuxGate$22589 -000 1 -010 1 -110 1 -111 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[24] execute_RS2[0] execute_RS2[8] $abc$27210$new_n7046 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[23] execute_RS2[7] execute_RS2[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22591 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[22] execute_RS2[6] execute_RS2[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22593 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[21] execute_RS2[5] execute_RS2[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22595 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[20] execute_RS2[4] execute_RS2[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22597 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[19] execute_RS2[3] execute_RS2[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22599 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[18] execute_RS2[2] execute_RS2[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22601 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[17] execute_RS2[1] execute_RS2[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22603 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[16] execute_RS2[0] execute_RS2[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22605 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[15] execute_RS2[7] execute_RS2[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22607 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n7056 -00 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[14] execute_RS2[6] execute_RS2[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22609 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[13] execute_RS2[5] execute_RS2[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22611 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[12] execute_RS2[4] execute_RS2[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22613 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[11] execute_RS2[3] execute_RS2[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22615 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[10] execute_RS2[2] execute_RS2[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22617 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[9] execute_RS2[1] execute_RS2[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22619 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[8] execute_RS2[0] execute_RS2[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22621 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[7] execute_RS2[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22623 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[6] execute_RS2[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22625 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[5] execute_RS2[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22627 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[4] execute_RS2[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22629 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[3] execute_RS2[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22631 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[2] execute_RS2[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22633 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[1] execute_RS2[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22635 -001 1 -011 1 -110 1 -111 1 -.names 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_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23341 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[24] $abc$27210$new_n7476 $abc$27210$new_n7463 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23343 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[23] $abc$27210$new_n7476 $abc$27210$new_n7464 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23345 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[22] $abc$27210$new_n7476 $abc$27210$new_n7465 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23347 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[21] $abc$27210$new_n7476 $abc$27210$new_n7466 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23349 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[20] $abc$27210$new_n7476 $abc$27210$new_n7467 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23351 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[19] $abc$27210$new_n7476 $abc$27210$new_n7468 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23353 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[18] $abc$27210$new_n7476 $abc$27210$new_n7469 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23355 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[17] $abc$27210$new_n7476 $abc$27210$new_n7470 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23357 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n7492 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$23359 -011 1 -100 1 -101 1 -110 1 -111 1 -.names execute_RS2[16] $abc$27210$new_n7471 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7476 execute_RS2[15] $abc$27210$new_n7492 -00010 1 -00011 1 -01001 1 -01011 1 -10000 1 -10001 1 -11000 1 -11010 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[15] $abc$27210$new_n7476 $abc$27210$new_n7471 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23361 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[14] $abc$27210$new_n7476 $abc$27210$new_n7472 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23363 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n7496 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$23365 -011 1 -100 1 -101 1 -110 1 -111 1 -.names execute_RS2[13] $abc$27210$new_n7473 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7476 execute_RS2[12] $abc$27210$new_n7496 -00010 1 -00011 1 -01001 1 -01011 1 -10000 1 -10001 1 -11000 1 -11010 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[12] $abc$27210$new_n7476 $abc$27210$new_n7473 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23367 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] $abc$27210$new_n7499 $abc$27210$auto$rtlil.cc:2693:MuxGate$23369 -001 1 -011 1 -110 1 -111 1 -.names execute_RS2[11] $abc$27210$new_n7476 $abc$27210$new_n7474 execute_RS2[9] execute_RS2[10] $abc$27210$new_n7499 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11100 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] $abc$27210$new_n7501 $abc$27210$auto$rtlil.cc:2693:MuxGate$23371 -001 1 -011 1 -110 1 -111 1 -.names execute_RS2[10] $abc$27210$new_n7474 $abc$27210$new_n7476 execute_RS2[9] $abc$27210$new_n7501 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[9] $abc$27210$new_n7476 $abc$27210$new_n7474 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23373 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] $abc$27210$new_n7504 $abc$27210$auto$rtlil.cc:2693:MuxGate$23375 -001 1 -011 1 -110 1 -111 1 -.names execute_RS2[8] $abc$27210$new_n7475 execute_RS2[6] $abc$27210$new_n7476 execute_RS2[7] $abc$27210$new_n7504 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] $abc$27210$new_n7506 $abc$27210$auto$rtlil.cc:2693:MuxGate$23377 -001 1 -011 1 -110 1 -111 1 -.names execute_RS2[7] $abc$27210$new_n7476 $abc$27210$new_n7475 execute_RS2[6] $abc$27210$new_n7506 -0010 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1110 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[6] $abc$27210$new_n7476 $abc$27210$new_n7475 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23379 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[5] $abc$27210$new_n7476 $abc$27210$new_n7509 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23381 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$27210$new_n7477 execute_RS2[4] $abc$27210$new_n7509 -10 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[4] $abc$27210$new_n7476 $abc$27210$new_n7477 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23383 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[3] $abc$27210$new_n7512 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23385 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$27210$new_n7476 execute_RS2[1] execute_RS2[2] execute_RS2[0] $abc$27210$new_n7512 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] $abc$27210$new_n7514 $abc$27210$auto$rtlil.cc:2693:MuxGate$23387 -001 1 -011 1 -110 1 -111 1 -.names execute_RS2[2] $abc$27210$new_n7476 execute_RS2[0] execute_RS2[1] $abc$27210$new_n7514 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[1] execute_RS2[0] $abc$27210$new_n7476 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23389 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] execute_RS2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23391 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[30] _zz_execute_to_memory_PC[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24099 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[29] _zz_execute_to_memory_PC[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24101 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[28] _zz_execute_to_memory_PC[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24103 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[27] _zz_execute_to_memory_PC[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24105 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[26] _zz_execute_to_memory_PC[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24107 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[25] _zz_execute_to_memory_PC[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24109 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[24] _zz_execute_to_memory_PC[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24111 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[23] _zz_execute_to_memory_PC[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24113 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[22] _zz_execute_to_memory_PC[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24115 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[21] _zz_execute_to_memory_PC[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24117 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[20] _zz_execute_to_memory_PC[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24119 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[19] _zz_execute_to_memory_PC[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24121 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[18] _zz_execute_to_memory_PC[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24123 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[17] _zz_execute_to_memory_PC[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24125 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[16] _zz_execute_to_memory_PC[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24127 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[15] _zz_execute_to_memory_PC[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24129 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[14] _zz_execute_to_memory_PC[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24131 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[13] _zz_execute_to_memory_PC[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24133 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[12] _zz_execute_to_memory_PC[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24135 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[9] _zz_execute_to_memory_PC[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24137 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[8] _zz_execute_to_memory_PC[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24139 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[7] _zz_execute_to_memory_PC[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24141 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[6] _zz_execute_to_memory_PC[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24143 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[5] _zz_execute_to_memory_PC[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24145 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[4] _zz_execute_to_memory_PC[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24147 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[3] _zz_execute_to_memory_PC[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24149 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[2] _zz_execute_to_memory_PC[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24151 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[1] _zz_execute_to_memory_PC[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24153 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[0] _zz_execute_to_memory_PC[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24155 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] _zz_execute_to_memory_PC[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24345 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] _zz_execute_to_memory_PC[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24347 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] _zz_execute_to_memory_PC[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24349 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] _zz_execute_to_memory_PC[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24351 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] _zz_execute_to_memory_PC[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24353 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] _zz_execute_to_memory_PC[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24355 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] _zz_execute_to_memory_PC[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24357 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] _zz_execute_to_memory_PC[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24359 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] _zz_execute_to_memory_PC[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24361 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] _zz_execute_to_memory_PC[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24363 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] _zz_execute_to_memory_PC[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24365 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] _zz_execute_to_memory_PC[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24367 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] _zz_execute_to_memory_PC[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24369 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] _zz_execute_to_memory_PC[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24371 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] _zz_execute_to_memory_PC[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24373 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] _zz_execute_to_memory_PC[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24375 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] _zz_execute_to_memory_PC[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24377 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] _zz_execute_to_memory_PC[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24379 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] _zz_execute_to_memory_PC[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24381 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] _zz_execute_to_memory_PC[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24383 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] _zz_execute_to_memory_PC[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24385 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] _zz_execute_to_memory_PC[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24387 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] _zz_execute_to_memory_PC[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24389 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] _zz_execute_to_memory_PC[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24391 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] _zz_execute_to_memory_PC[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24393 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] _zz_execute_to_memory_PC[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24395 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 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$abc$27210$auto$rtlil.cc:2693:MuxGate$24553 -001 1 -011 1 -100 1 -101 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n7649 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$27210$new_n4093 _zz_writeBack_ENV_CTRL _zz_memory_ENV_CTRL $abc$27210$auto$rtlil.cc:2693:MuxGate$24555 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$27210$auto$rtlil.cc:2693:MuxGate$24557 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 _zz_execute_ENV_CTRL $abc$27210$new_n7638 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24559 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$27210$new_n4259 decode_to_execute_IS_CSR $abc$27210$new_n4303 $abc$27210$new_n4714 $abc$27210$auto$rtlil.cc:2693:MuxGate$24561 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_21 decode_to_execute_IS_RS1_SIGNED $abc$27210$auto$rtlil.cc:2693:MuxGate$24563 -001 1 -011 1 -100 1 -101 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_IS_DIV decode_to_execute_IS_DIV $abc$27210$auto$rtlil.cc:2693:MuxGate$24565 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 decode_to_execute_IS_DIV IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n7657 $abc$27210$auto$rtlil.cc:2693:MuxGate$24567 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n7286 $abc$27210$new_n7657 -111 1 -.names $abc$27210$new_n4093 memory_to_writeBack_IS_MUL execute_to_memory_IS_MUL $abc$27210$auto$rtlil.cc:2693:MuxGate$24569 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_IS_MUL decode_to_execute_IS_MUL $abc$27210$auto$rtlil.cc:2693:MuxGate$24571 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 decode_to_execute_IS_MUL $abc$27210$new_n4715 $abc$27210$new_n4712 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24573 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_SHIFT_CTRL[1] _zz_execute_SHIFT_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24575 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 _zz_execute_SHIFT_CTRL[1] $abc$27210$new_n7285 $abc$27210$new_n4727 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24577 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_21 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24579 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 $abc$27210$new_n5859 decode_to_execute_SRC_LESS_UNSIGNED IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24581 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4259 decode_to_execute_IS_SFENCE_VMA2 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n7638 $abc$27210$auto$rtlil.cc:2693:MuxGate$24583 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n4259 decode_to_execute_MEMORY_MANAGMENT IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24585 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$27210$new_n4093 memory_to_writeBack_MEMORY_WR execute_to_memory_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24587 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_WR decode_to_execute_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24589 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_41 decode_to_execute_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24591 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_BYPASSABLE_MEMORY_STAGE decode_to_execute_BYPASSABLE_MEMORY_STAGE $abc$27210$auto$rtlil.cc:2693:MuxGate$24593 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 $abc$27210$new_n7672 decode_to_execute_BYPASSABLE_MEMORY_STAGE $abc$27210$auto$rtlil.cc:2693:MuxGate$24595 -001 1 -011 1 -100 1 -101 1 -.names $abc$27210$new_n7286 _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n7672 -10000 1 -10001 1 -10010 1 -10011 1 -11010 1 -11110 1 -.names $abc$27210$new_n4259 decode_to_execute_BYPASSABLE_EXECUTE_STAGE $abc$27210$new_n7674 $abc$27210$new_n4723 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24597 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n7674 -10000 1 -10010 1 -11000 1 -11001 1 -.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_valid execute_to_memory_REGFILE_WRITE_VALID $abc$27210$auto$rtlil.cc:2693:MuxGate$24599 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$27210$auto$rtlil.cc:2693:MuxGate$24601 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 decode_to_execute_REGFILE_WRITE_VALID $abc$27210$new_n4707 $abc$27210$new_n7678 $abc$27210$auto$rtlil.cc:2693:MuxGate$24605 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4304 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4714 $abc$27210$new_n7678 -00100 1 -00101 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_85 _zz_execute_SRC2_CTRL[1] $abc$27210$new_n4314 _zz__zz_decode_IS_CSR_41 $abc$27210$auto$rtlil.cc:2693:MuxGate$24607 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4259 _zz_execute_ALU_CTRL[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24609 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$27210$new_n4093 memory_to_writeBack_MEMORY_ENABLE execute_to_memory_MEMORY_ENABLE $abc$27210$auto$rtlil.cc:2693:MuxGate$24611 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_ENABLE decode_to_execute_MEMORY_ENABLE $abc$27210$auto$rtlil.cc:2693:MuxGate$24613 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 decode_to_execute_MEMORY_ENABLE $abc$27210$new_n4314 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24615 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$27210$new_n4259 _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n7685 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24617 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n7685 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4259 $abc$27210$new_n7292 _zz_execute_SRC1_CTRL[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24619 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PREDICTION_CONTEXT_line_history[1] decode_to_execute_PREDICTION_CONTEXT_line_history[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24621 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PREDICTION_CONTEXT_hazard decode_to_execute_PREDICTION_CONTEXT_hazard $abc$27210$auto$rtlil.cc:2693:MuxGate$24623 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 _zz_decode_PREDICTION_CONTEXT_line_history_2[1] decode_to_execute_PREDICTION_CONTEXT_line_history[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24625 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 _zz_decode_PREDICTION_CONTEXT_hazard_4 decode_to_execute_PREDICTION_CONTEXT_hazard $abc$27210$auto$rtlil.cc:2693:MuxGate$24627 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4259 _zz_6 _zz_execute_BranchPlugin_branch_src2 $abc$27210$auto$rtlil.cc:2693:MuxGate$24633 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_result_5 $abc$27210$new_n7693 $abc$27210$auto$rtlil.cc:2693:MuxGate$24651 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n7702 $abc$27210$new_n7477 $abc$27210$new_n7700 $abc$27210$new_n7694 $abc$27210$new_n7693 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -.names $abc$27210$new_n7697 $abc$27210$new_n7695 $abc$27210$new_n7699 execute_RS2[4] execute_RS2[5] $abc$27210$new_n7694 -11100 1 -.names $abc$27210$new_n7696 execute_RS2[21] execute_RS2[22] execute_RS2[23] execute_RS2[24] $abc$27210$new_n7695 -10000 1 -.names execute_RS2[25] execute_RS2[26] execute_RS2[27] execute_RS2[28] $abc$27210$new_n7696 -0000 1 -.names $abc$27210$new_n7698 execute_RS2[13] execute_RS2[14] execute_RS2[15] execute_RS2[16] $abc$27210$new_n7697 -10000 1 -.names execute_RS2[17] execute_RS2[18] execute_RS2[19] execute_RS2[20] $abc$27210$new_n7698 -0000 1 -.names execute_RS2[29] execute_RS2[30] execute_RS2[6] execute_RS2[7] $abc$27210$new_n7699 -0000 1 -.names $abc$27210$new_n7701 execute_RS2[9] execute_RS2[10] execute_RS2[11] execute_RS2[12] $abc$27210$new_n7700 -10000 1 -.names decode_to_execute_IS_RS1_SIGNED execute_RS2[31] switch_Misc_l241_1 execute_RS2[8] $abc$27210$new_n7701 -1000 1 -.names decode_to_execute_IS_RS1_SIGNED decode_to_execute_IS_DIV execute_RS1[31] execute_RS2[31] switch_Misc_l241_1 $abc$27210$new_n7702 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11110 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7704 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] execute_RS2[31] decode_to_execute_IS_RS1_SIGNED $abc$27210$auto$rtlil.cc:2693:MuxGate$24653 -00010 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7458 execute_RS2[29] execute_RS2[30] $abc$27210$new_n7476 $abc$27210$new_n7704 -1001 1 -1110 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_mask[3] dataCache_1.stageA_mask[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24793 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4198 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] $abc$27210$new_n7712 -10 1 -.names $abc$27210$new_n3940 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] $abc$27210$new_n4111 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] $abc$27210$new_n7714 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n7716 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[5] $abc$27210$new_n4192 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[6] $abc$27210$new_n4186 $abc$27210$new_n7715 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n7717 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[21] $abc$27210$new_n8126 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] $abc$27210$new_n4146 $abc$27210$new_n7716 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4140 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[13] dataCache_1._zz_ways_0_tagsReadRsp_valid_1[16] $abc$27210$new_n4122 $abc$27210$new_n7717 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$27210$new_n7719 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[19] $abc$27210$new_n4106 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[11] $abc$27210$new_n4152 $abc$27210$new_n7718 -10100 1 -10111 1 -11000 1 -11011 1 -.names $abc$27210$new_n4180 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[7] dataCache_1._zz_ways_0_tagsReadRsp_valid_1[10] $abc$27210$new_n4162 $abc$27210$new_n7719 -0000 1 -0011 1 -1100 1 -1111 1 -.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] $abc$27210$new_n4198 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] $abc$27210$new_n3940 $abc$27210$new_n7721 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[0] $abc$27210$new_n4093 $abc$27210$new_n4146 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] $abc$27210$new_n7723 -1000 1 -1010 1 -1011 1 -.names dataCache_1.stageA_request_size[1] dataCache_1.stageA_request_size[0] $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24797 -01010 1 -01011 1 -10001 1 -10010 1 -10011 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataColisions dataCache_1.stage0_dataColisions_regNextWhen $abc$27210$new_n7728 $abc$27210$new_n7726 $abc$27210$auto$rtlil.cc:2693:MuxGate$24799 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n6003 $abc$27210$new_n4095 $abc$27210$new_n7727 $abc$27210$new_n7726 -000 1 -001 1 -010 1 -.names dBus_cmd_payload_wr dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4100 $abc$27210$new_n7727 -1100 1 -.names $abc$27210$new_n7736 $abc$27210$new_n8181 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] dataCache_1.dataWriteCmd_payload_address[2] $abc$27210$new_n7728 -1100 1 -1111 1 -.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[1] dataCache_1.stageB_mmuRsp_physicalAddress[3] dataCache_1.dataWriteCmd_payload_address[1] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[0] dataCache_1.stageB_mmuRsp_physicalAddress[2] dataCache_1.dataWriteCmd_payload_address[0] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n7739 $abc$27210$new_n7737 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] dBus_cmd_payload_address[6] $abc$27210$new_n7736 -1100 1 -1111 1 -.names $abc$27210$new_n7738 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] dBus_cmd_payload_address[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] dBus_cmd_payload_address[11] $abc$27210$new_n7737 -10000 1 -10011 1 -11100 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] dBus_cmd_payload_address[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] dBus_cmd_payload_address[10] $abc$27210$new_n7738 -0000 1 -0011 1 -1100 1 -1111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] dBus_cmd_payload_address[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] dBus_cmd_payload_address[9] $abc$27210$new_n7739 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[2] dataCache_1.stageB_mmuRsp_physicalAddress[4] dataCache_1.dataWriteCmd_payload_address[2] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[31] dataCache_1._zz_ways_0_data_port0[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24801 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_tagsReadRsp_0_error dataCache_1._zz_ways_0_tagsReadRsp_valid_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24803 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dataCache_1.stageB_request_size[1] dataCache_1.stageA_request_size[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24829 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4093 dBus_cmd_payload_wr dataCache_1.io_cpu_memory_isWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24831 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n7746 dataCache_1.stage0_dataColisions_regNextWhen DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$24833 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$27210$new_n7747 dBus_cmd_payload_address[10] dataCache_1.dataReadCmd_payload[8] dBus_cmd_payload_address[11] dataCache_1.dataReadCmd_payload[9] $abc$27210$new_n7746 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n7748 dBus_cmd_payload_address[8] dataCache_1.dataReadCmd_payload[6] dBus_cmd_payload_address[9] dataCache_1.dataReadCmd_payload[7] $abc$27210$new_n7747 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8184 dBus_cmd_payload_address[6] dataCache_1.dataReadCmd_payload[4] dBus_cmd_payload_address[7] dataCache_1.dataReadCmd_payload[5] $abc$27210$new_n7748 -10000 1 -10011 1 -11100 1 -11111 1 -.names dataCache_1.dataWriteCmd_payload_address[0] dataCache_1.dataReadCmd_payload[0] $abc$27210$new_n7726 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7751 -0000 1 -1100 1 -.names $abc$27210$new_n4327 $abc$27210$new_n6986 $abc$27210$new_n6988 dataCache_1.dataReadCmd_payload[0] -000 1 -001 1 -100 1 -110 1 -.names $abc$27210$new_n6003 dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[1] $abc$27210$new_n6095 $abc$27210$new_n6097 $abc$27210$new_n7755 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n6091 $abc$27210$new_n4327 $abc$27210$new_n6089 $abc$27210$new_n7756 -00000 1 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$27210$new_n4327 $abc$27210$new_n6979 $abc$27210$new_n6982 dataCache_1.dataReadCmd_payload[1] -000 1 -001 1 -100 1 -110 1 -.names $abc$27210$new_n4327 $abc$27210$new_n6965 $abc$27210$new_n6968 dataCache_1.dataReadCmd_payload[3] -000 1 -001 1 -100 1 -110 1 -.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6975 $abc$27210$new_n6973 $abc$27210$new_n5385 dataCache_1.dataReadCmd_payload[2] -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4327 $abc$27210$new_n6951 $abc$27210$new_n6954 dataCache_1.dataReadCmd_payload[5] -010 1 -011 1 -100 1 -110 1 -.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6961 $abc$27210$new_n6959 $abc$27210$new_n5373 dataCache_1.dataReadCmd_payload[4] -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4327 $abc$27210$new_n6937 $abc$27210$new_n6940 dataCache_1.dataReadCmd_payload[7] -000 1 -001 1 -100 1 -110 1 -.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6947 $abc$27210$new_n6945 $abc$27210$new_n5362 dataCache_1.dataReadCmd_payload[6] -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4327 $abc$27210$new_n6923 $abc$27210$new_n6926 dataCache_1.dataReadCmd_payload[9] -010 1 -011 1 -100 1 -110 1 -.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6933 $abc$27210$new_n6931 $abc$27210$new_n5352 dataCache_1.dataReadCmd_payload[8] -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[3] $abc$27210$new_n7756 $abc$27210$auto$rtlil.cc:2693:MuxGate$24835 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_request_size[1] switch_Misc_l241_1 $abc$27210$new_n4327 $abc$27210$auto$rtlil.cc:2693:MuxGate$24837 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.io_cpu_memory_isWrite decode_to_execute_MEMORY_WR $abc$27210$new_n4327 $abc$27210$auto$rtlil.cc:2693:MuxGate$24839 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n7770 DBusCachedPlugin_mmuBus_cmd_0_isStuck BranchPlugin_branchExceptionPort_payload_badAddr[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24873 -000 1 -001 1 -011 1 -.names $abc$27210$new_n7410 $abc$27210$new_n7771 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7399 $abc$27210$new_n7340 $abc$27210$new_n7770 -00000 1 -01001 1 -01010 1 -01011 1 -10011 1 -11000 1 -11001 1 -11010 1 -.names $abc$27210$new_n7358 execute_RS1[31] _zz_execute_to_memory_PC[31] $abc$27210$new_n7771 -000 1 -010 1 -100 1 -101 1 -.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] _zz_execute_to_memory_PC[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24885 -001 1 -011 1 -110 1 -111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[31] _zz_execute_to_memory_PC[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24895 -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n7086 $abc$27210$new_n5857 $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_valid -110 1 -.names execute_RS1[31] _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 execute_MulPlugin_aHigh[16] -101 1 -110 1 -.names execute_RS2[31] _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 execute_MulPlugin_bHigh[16] -110 1 -.names $abc$27210$new_n4636 DebugPlugin_godmode CsrPlugin_exception -10 1 -.names $abc$27210$new_n7779 $abc$27210$new_n4266 $0\DebugPlugin_isPipBusy[0:0] -00 1 -01 1 -10 1 -.names execute_arbitration_isValid memory_arbitration_isValid lastStageIsValid IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$new_n7779 -00000 1 -.names iBus_rsp_payload_error IBusCachedPlugin_cache.lineLoader_hadError IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_error -01 1 -10 1 -11 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$new_n6015 IBusCachedPlugin_cache._zz_2 -00 1 -01 1 -11 1 -.names IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.lineLoader_cmdSent iBus_cmd_valid -10 1 -.names $abc$27210$new_n7784 decode_to_execute_MEMORY_ENABLE $abc$27210$flatten\dataCache_1.$0\stageB_flusher_start[0:0] -10 1 -.names $abc$27210$new_n7785 DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation MmuPlugin_dBusAccess_rsp_payload_redo memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE $abc$27210$new_n7784 -10000 1 -10001 1 -10010 1 -.names decode_to_execute_MEMORY_MANAGMENT execute_arbitration_isValid $abc$27210$new_n4100 dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_waitDone $abc$27210$new_n7785 -11100 1 -.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n4327 dataCache_1.io_cpu_execute_refilling decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid dataCache_1._zz_ways_0_dataReadRspMem -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[3] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol3$./benchmark/VexRiscv.v:6887$1195_EN[7:0]$1223[7] -001 1 -010 1 -011 1 -.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[2] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol2$./benchmark/VexRiscv.v:6884$1194_EN[7:0]$1220[7] -001 1 -010 1 -011 1 -.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[1] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol1$./benchmark/VexRiscv.v:6881$1193_EN[7:0]$1217[7] -001 1 -010 1 -011 1 -.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[0] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol0$./benchmark/VexRiscv.v:6878$1192_EN[7:0]$1214[7] -001 1 -010 1 -011 1 -.names $abc$27210$new_n5826 $abc$27210$new_n4424 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_line_history_1 -000 1 -001 1 -010 1 -011 1 -101 1 -110 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_hadError $abc$27210$new_n6015 iBus_rsp_payload_error iBus_rsp_valid $abc$27210$flatten\IBusCachedPlugin_cache.$0\lineLoader_hadError[0:0] -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24235 -00 1 -11 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_flushCounter[0] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24233 -010 1 -100 1 -101 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7796 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24231 -010 1 -100 1 -101 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_flushCounter[0] $abc$27210$new_n7796 -11 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24229 -01 1 -10 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7796 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$new_n7798 -110 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24227 -011 1 -100 1 -101 1 -110 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24225 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[6] IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7802 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24867 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7796 $abc$27210$new_n7802 -1111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7802 IBusCachedPlugin_cache.lineLoader_flushCounter[6] $abc$27210$flatten\IBusCachedPlugin_cache.$procmux$1907_Y[7] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[5] IBusCachedPlugin_cache.lineLoader_flushCounter[0] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[0] -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[6] IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[1] -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[7] IBusCachedPlugin_cache.lineLoader_flushCounter[2] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[2] -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[8] IBusCachedPlugin_cache.lineLoader_flushCounter[3] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[3] -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[9] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[4] -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[10] IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[5] -001 1 -011 1 -110 1 -111 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[11] IBusCachedPlugin_cache.lineLoader_flushCounter[6] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[6] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n5829 DebugPlugin_haltedByBreak debug_bus_cmd_payload_data[25] $abc$27210$new_n5967 $0\DebugPlugin_haltedByBreak[0:0] -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names DebugPlugin_godmode debug_bus_cmd_payload_data[25] $abc$27210$new_n5967 DebugPlugin_isPipBusy DebugPlugin_haltIt $0\DebugPlugin_godmode[0:0] -00001 1 -00101 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n7814 $abc$27210$new_n5854 $abc$27210$new_n4266 $0\DebugPlugin_haltIt[0:0] -000 1 -001 1 -010 1 -011 1 -110 1 -.names $abc$27210$new_n5829 DebugPlugin_haltIt $abc$27210$new_n5967 debug_bus_cmd_payload_data[25] debug_bus_cmd_payload_data[17] $abc$27210$new_n7814 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01110 1 -01111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n5404 CsrPlugin_mepc[0] $abc$27210$new_n4432 $0\CsrPlugin_mepc[31:0][0] -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_833 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n7816 -1111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n5399 CsrPlugin_mepc[1] $abc$27210$new_n4432 $0\CsrPlugin_mepc[31:0][1] -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5394 CsrPlugin_mepc[2] DBusCachedPlugin_redoBranch_payload[2] $0\CsrPlugin_mepc[31:0][2] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5387 CsrPlugin_mepc[3] DBusCachedPlugin_redoBranch_payload[3] $0\CsrPlugin_mepc[31:0][3] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5382 CsrPlugin_mepc[4] DBusCachedPlugin_redoBranch_payload[4] $0\CsrPlugin_mepc[31:0][4] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5377 CsrPlugin_mepc[5] DBusCachedPlugin_redoBranch_payload[5] $0\CsrPlugin_mepc[31:0][5] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5372 CsrPlugin_mepc[6] DBusCachedPlugin_redoBranch_payload[6] $0\CsrPlugin_mepc[31:0][6] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5366 CsrPlugin_mepc[7] DBusCachedPlugin_redoBranch_payload[7] $0\CsrPlugin_mepc[31:0][7] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5361 CsrPlugin_mepc[8] DBusCachedPlugin_redoBranch_payload[8] $0\CsrPlugin_mepc[31:0][8] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5356 CsrPlugin_mepc[9] DBusCachedPlugin_redoBranch_payload[9] $0\CsrPlugin_mepc[31:0][9] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5351 CsrPlugin_mepc[10] DBusCachedPlugin_redoBranch_payload[10] $0\CsrPlugin_mepc[31:0][10] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5344 CsrPlugin_mepc[11] DBusCachedPlugin_redoBranch_payload[11] $0\CsrPlugin_mepc[31:0][11] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5339 CsrPlugin_mepc[12] DBusCachedPlugin_redoBranch_payload[12] $0\CsrPlugin_mepc[31:0][12] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5334 CsrPlugin_mepc[13] DBusCachedPlugin_redoBranch_payload[13] $0\CsrPlugin_mepc[31:0][13] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5329 CsrPlugin_mepc[14] DBusCachedPlugin_redoBranch_payload[14] $0\CsrPlugin_mepc[31:0][14] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5324 CsrPlugin_mepc[15] DBusCachedPlugin_redoBranch_payload[15] $0\CsrPlugin_mepc[31:0][15] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5319 CsrPlugin_mepc[16] DBusCachedPlugin_redoBranch_payload[16] $0\CsrPlugin_mepc[31:0][16] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5314 CsrPlugin_mepc[17] DBusCachedPlugin_redoBranch_payload[17] $0\CsrPlugin_mepc[31:0][17] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5309 CsrPlugin_mepc[18] DBusCachedPlugin_redoBranch_payload[18] $0\CsrPlugin_mepc[31:0][18] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5304 CsrPlugin_mepc[19] DBusCachedPlugin_redoBranch_payload[19] $0\CsrPlugin_mepc[31:0][19] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5299 CsrPlugin_mepc[20] DBusCachedPlugin_redoBranch_payload[20] $0\CsrPlugin_mepc[31:0][20] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5945 CsrPlugin_mepc[21] DBusCachedPlugin_redoBranch_payload[21] $0\CsrPlugin_mepc[31:0][21] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5444 CsrPlugin_mepc[22] DBusCachedPlugin_redoBranch_payload[22] $0\CsrPlugin_mepc[31:0][22] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5439 CsrPlugin_mepc[23] DBusCachedPlugin_redoBranch_payload[23] $0\CsrPlugin_mepc[31:0][23] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5434 CsrPlugin_mepc[24] DBusCachedPlugin_redoBranch_payload[24] $0\CsrPlugin_mepc[31:0][24] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5429 CsrPlugin_mepc[25] DBusCachedPlugin_redoBranch_payload[25] $0\CsrPlugin_mepc[31:0][25] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5424 CsrPlugin_mepc[26] DBusCachedPlugin_redoBranch_payload[26] $0\CsrPlugin_mepc[31:0][26] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 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$abc$27210$new_n5950 CsrPlugin_mepc[30] DBusCachedPlugin_redoBranch_payload[30] $0\CsrPlugin_mepc[31:0][30] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5840 CsrPlugin_mepc[31] DBusCachedPlugin_redoBranch_payload[31] $0\CsrPlugin_mepc[31:0][31] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7849 $abc$27210$new_n5387 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] -001 1 -011 1 -110 1 -111 1 -.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n7849 -1111 1 -.names $abc$27210$new_n5856 DBusCachedPlugin_mmuBus_cmd_0_isStuck $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack[0:0] -10 1 -.names $abc$27210$new_n5851 $abc$27210$new_n4259 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5856 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory[0:0] -0011 1 -0111 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5855 $abc$27210$new_n4258 $abc$27210$new_n5851 $abc$27210$new_n4259 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute[0:0] -0010 1 -0110 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5855 $abc$27210$new_n4258 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode[0:0] -10 1 -.names $abc$27210$new_n5868 $abc$27210$new_n4433 $0\CsrPlugin_interrupt_valid[0:0] -00 1 -.names $abc$27210$new_n7856 $abc$27210$new_n4438 $abc$27210$new_n4432 CsrPlugin_mstatus_MPP[0] $0\CsrPlugin_mstatus_MPP[1:0][0] -0000 1 -0001 1 -0011 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n5339 $abc$27210$new_n5344 $abc$27210$new_n7857 $abc$27210$new_n7856 -111 1 -.names decode_to_execute_CSR_WRITE_OPCODE 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decode_to_execute_CSR_WRITE_OPCODE $abc$27210$new_n4264 $abc$27210$new_n4259 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n7871 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7871 $abc$27210$new_n5304 MmuPlugin_status_mxr $0\MmuPlugin_status_mxr[0:0] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n7871 $abc$27210$new_n5309 MmuPlugin_status_sum $0\MmuPlugin_status_sum[0:0] -001 1 -011 1 -110 1 -111 1 -.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[4] DebugPlugin_stepIt debug_bus_rsp_data[4] -001 1 -011 1 -110 1 -111 1 -.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[2] DebugPlugin_isPipBusy debug_bus_rsp_data[2] -001 1 -011 1 -110 1 -111 1 -.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[1] DebugPlugin_haltIt debug_bus_rsp_data[1] -001 1 -011 1 -110 1 -111 1 -.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[0] DebugPlugin_resetIt debug_bus_rsp_data[0] -001 1 -011 1 -110 1 -111 1 -.names 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$abc$27210$new_n7888 -1111 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[0] _zz_14 lastStageRegFileWrite_payload_data[0] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[1] _zz_14 lastStageRegFileWrite_payload_data[1] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[2] _zz_14 lastStageRegFileWrite_payload_data[2] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[3] _zz_14 lastStageRegFileWrite_payload_data[3] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[4] _zz_14 lastStageRegFileWrite_payload_data[4] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[5] _zz_14 lastStageRegFileWrite_payload_data[5] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[6] _zz_14 lastStageRegFileWrite_payload_data[6] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[7] _zz_14 lastStageRegFileWrite_payload_data[7] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[8] _zz_14 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HazardSimplePlugin_writeBackWrites_payload_data[26] _zz_14 lastStageRegFileWrite_payload_data[26] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[27] _zz_14 lastStageRegFileWrite_payload_data[27] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[28] _zz_14 lastStageRegFileWrite_payload_data[28] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[29] _zz_14 lastStageRegFileWrite_payload_data[29] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[30] _zz_14 lastStageRegFileWrite_payload_data[30] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_data[31] _zz_14 lastStageRegFileWrite_payload_data[31] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_14 lastStageRegFileWrite_payload_address[0] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_14 lastStageRegFileWrite_payload_address[1] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_14 lastStageRegFileWrite_payload_address[2] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_14 lastStageRegFileWrite_payload_address[3] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_14 lastStageRegFileWrite_payload_address[4] -10 1 -.names _zz_14 HazardSimplePlugin_writeBackWrites_valid _zz_1 -01 1 -10 1 -11 1 -.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_valueNext[0] -01 1 -10 1 -.names MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_valueNext[1] -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_valueNext[2] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4455 IBusCachedPlugin_predictionJumpInterface_payload[29] -000 1 -011 1 -101 1 -110 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 IBusCachedPlugin_predictionJumpInterface_payload[30] -000 1 -011 1 -101 1 -110 1 -.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 IBusCachedPlugin_predictionJumpInterface_payload[31] -0010 1 -0100 1 -0101 1 -0111 1 -1001 1 -1100 1 -1110 1 -1111 1 -.names dataCache_1.loader_counter_willOverflow dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4095 $abc$27210$new_n4100 dataCache_1._zz_2 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[5] dataCache_1.stageB_flusher_counter[0] dataCache_1.tagsWriteCmd_payload_address[0] -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[6] dataCache_1.stageB_flusher_counter[1] dataCache_1.tagsWriteCmd_payload_address[1] -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[7] dataCache_1.stageB_flusher_counter[2] dataCache_1.tagsWriteCmd_payload_address[2] -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[8] dataCache_1.stageB_flusher_counter[3] dataCache_1.tagsWriteCmd_payload_address[3] -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[9] dataCache_1.stageB_flusher_counter[4] dataCache_1.tagsWriteCmd_payload_address[4] -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[10] dataCache_1.stageB_flusher_counter[5] dataCache_1.tagsWriteCmd_payload_address[5] -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[11] dataCache_1.stageB_flusher_counter[6] dataCache_1.tagsWriteCmd_payload_address[6] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[0] dBus_cmd_payload_data[0] dataCache_1.dataWriteCmd_payload_data[0] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[1] dBus_cmd_payload_data[1] dataCache_1.dataWriteCmd_payload_data[1] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[2] dBus_cmd_payload_data[2] dataCache_1.dataWriteCmd_payload_data[2] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[3] dBus_cmd_payload_data[3] dataCache_1.dataWriteCmd_payload_data[3] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[4] dBus_cmd_payload_data[4] dataCache_1.dataWriteCmd_payload_data[4] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[5] dBus_cmd_payload_data[5] dataCache_1.dataWriteCmd_payload_data[5] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[6] dBus_cmd_payload_data[6] dataCache_1.dataWriteCmd_payload_data[6] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[7] dBus_cmd_payload_data[7] dataCache_1.dataWriteCmd_payload_data[7] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[8] dBus_cmd_payload_data[8] dataCache_1.dataWriteCmd_payload_data[8] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[9] dBus_cmd_payload_data[9] dataCache_1.dataWriteCmd_payload_data[9] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[10] dBus_cmd_payload_data[10] dataCache_1.dataWriteCmd_payload_data[10] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[11] dBus_cmd_payload_data[11] dataCache_1.dataWriteCmd_payload_data[11] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[12] dBus_cmd_payload_data[12] dataCache_1.dataWriteCmd_payload_data[12] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[13] dBus_cmd_payload_data[13] dataCache_1.dataWriteCmd_payload_data[13] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[14] dBus_cmd_payload_data[14] dataCache_1.dataWriteCmd_payload_data[14] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[15] dBus_cmd_payload_data[15] dataCache_1.dataWriteCmd_payload_data[15] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[16] dBus_cmd_payload_data[16] dataCache_1.dataWriteCmd_payload_data[16] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[17] dBus_cmd_payload_data[17] dataCache_1.dataWriteCmd_payload_data[17] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[18] dBus_cmd_payload_data[18] dataCache_1.dataWriteCmd_payload_data[18] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[19] dBus_cmd_payload_data[19] dataCache_1.dataWriteCmd_payload_data[19] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[20] dBus_cmd_payload_data[20] dataCache_1.dataWriteCmd_payload_data[20] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[21] dBus_cmd_payload_data[21] dataCache_1.dataWriteCmd_payload_data[21] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[22] dBus_cmd_payload_data[22] dataCache_1.dataWriteCmd_payload_data[22] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[23] dBus_cmd_payload_data[23] dataCache_1.dataWriteCmd_payload_data[23] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[24] dBus_cmd_payload_data[24] dataCache_1.dataWriteCmd_payload_data[24] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[25] dBus_cmd_payload_data[25] dataCache_1.dataWriteCmd_payload_data[25] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[26] dBus_cmd_payload_data[26] dataCache_1.dataWriteCmd_payload_data[26] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[27] dBus_cmd_payload_data[27] dataCache_1.dataWriteCmd_payload_data[27] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[28] dBus_cmd_payload_data[28] dataCache_1.dataWriteCmd_payload_data[28] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[29] dBus_cmd_payload_data[29] dataCache_1.dataWriteCmd_payload_data[29] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[30] dBus_cmd_payload_data[30] dataCache_1.dataWriteCmd_payload_data[30] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n6003 dBus_rsp_payload_data[31] dBus_cmd_payload_data[31] dataCache_1.dataWriteCmd_payload_data[31] -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.stageB_mmuRsp_physicalAddress[0] dBus_cmd_payload_size[2] dBus_cmd_payload_address[0] -10 1 -.names dataCache_1.stageB_mmuRsp_physicalAddress[1] dBus_cmd_payload_size[2] dBus_cmd_payload_address[1] -10 1 -.names dataCache_1.stageB_mmuRsp_physicalAddress[2] dBus_cmd_payload_size[2] dBus_cmd_payload_address[2] -10 1 -.names dataCache_1.stageB_mmuRsp_physicalAddress[3] dBus_cmd_payload_size[2] dBus_cmd_payload_address[3] -10 1 -.names dataCache_1.stageB_mmuRsp_physicalAddress[4] dBus_cmd_payload_size[2] dBus_cmd_payload_address[4] -10 1 -.names dataCache_1.stageB_request_size[0] dBus_cmd_payload_size[2] dBus_cmd_payload_size[0] -01 1 -10 1 -11 1 -.names dataCache_1.stageB_request_size[1] dBus_cmd_payload_size[2] dBus_cmd_payload_size[1] -10 1 -.names dataCache_1.stageB_flusher_start $abc$27210$new_n4234 dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n6007 dataCache_1.stageB_flusher_counter[6] $abc$27210$flatten\dataCache_1.$0\stageB_flusher_counter[7:0][7] -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] decode_INSTRUCTION_ANTICIPATED[15] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] decode_INSTRUCTION_ANTICIPATED[16] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] decode_INSTRUCTION_ANTICIPATED[17] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] decode_INSTRUCTION_ANTICIPATED[18] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] decode_INSTRUCTION_ANTICIPATED[19] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] decode_INSTRUCTION_ANTICIPATED[20] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] decode_INSTRUCTION_ANTICIPATED[21] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] decode_INSTRUCTION_ANTICIPATED[22] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] decode_INSTRUCTION_ANTICIPATED[23] -001 1 -011 1 -110 1 -111 1 -.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] decode_INSTRUCTION_ANTICIPATED[24] -001 1 -011 1 -110 1 -111 1 -.names dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[0] -01 1 -10 1 -.names dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[1] -011 1 -100 1 -101 1 -110 1 -.names dataCache_1.loader_counter_value[2] dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[2] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names execute_to_memory_PREDICTION_CONTEXT_line_history[0] execute_to_memory_BRANCH_DO memory_arbitration_isValid _zz__zz_3_port[1] -011 1 -100 1 -101 1 -110 1 -.names execute_to_memory_PREDICTION_CONTEXT_line_history[0] _zz__zz_3_port[0] -0 1 -.names $abc$27210$new_n8193 MmuPlugin_ports_1_cache_2_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_ports_1_cache_2_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n7999 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8195 MmuPlugin_ports_1_cache_4_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_4_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n8001 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -.names $abc$27210$new_n8001 MmuPlugin_ports_1_cache_4_superPage $abc$27210$new_n8002 -10 1 -.names $abc$27210$new_n3971 MmuPlugin_ports_1_cache_4_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_4_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n8003 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n3994 MmuPlugin_ports_1_cache_3_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_3_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n8006 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n8006 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_ports_1_cache_3_virtualAddress_0[7] MmuPlugin_ports_1_cache_3_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$new_n8007 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n8007 MmuPlugin_ports_1_cache_3_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n8008 -100 1 -111 1 -.names $abc$27210$new_n4013 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_5_virtualAddress_0[5] MmuPlugin_ports_1_cache_5_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n8009 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4016 MmuPlugin_ports_1_cache_5_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n8010 -10000 1 -10001 1 -10011 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n8010 $abc$27210$new_n8009 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_ports_1_cache_5_virtualAddress_0[7] MmuPlugin_ports_1_cache_5_superPage $abc$27210$new_n8011 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11100 1 -.names $abc$27210$new_n4037 MmuPlugin_ports_1_cache_1_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_1_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n8013 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4369 MmuPlugin_ports_1_cache_4_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8015 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n4368 $abc$27210$new_n4055 $abc$27210$new_n3985 MmuPlugin_ports_1_cache_4_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n8016 -11100 1 -11111 1 -.names $abc$27210$new_n8016 $abc$27210$new_n8015 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_4_virtualAddress_1[7] $abc$27210$new_n8002 $abc$27210$new_n8017 -11000 1 -11110 1 -.names execute_to_memory_INSTRUCTION[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] execute_to_memory_INSTRUCTION[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n8021 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$27210$new_n8021 execute_to_memory_INSTRUCTION[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] execute_to_memory_INSTRUCTION[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n8022 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8022 execute_to_memory_INSTRUCTION[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8023 -100 1 -111 1 -.names MmuPlugin_ports_1_cache_3_valid MmuPlugin_ports_1_cache_3_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8025 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_5_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] MmuPlugin_ports_1_cache_5_virtualAddress_1[8] $abc$27210$new_n4027 $abc$27210$new_n8029 -00000 1 -00110 1 -11000 1 -11110 1 -.names MmuPlugin_ports_1_cache_5_valid MmuPlugin_ports_1_cache_5_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_5_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n8030 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n4362 MmuPlugin_ports_1_cache_2_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_ports_1_cache_2_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8032 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n4363 MmuPlugin_ports_1_cache_2_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8033 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n4359 $abc$27210$new_n8032 $abc$27210$new_n8033 $abc$27210$new_n3956 $abc$27210$new_n8034 -1110 1 -.names $abc$27210$new_n4387 MmuPlugin_ports_1_cache_0_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8035 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4504 DBusCachedPlugin_redoBranch_payload[22] IBusCachedPlugin_predictionJumpInterface_payload[22] $abc$27210$new_n4434 $abc$27210$new_n8038 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names $abc$27210$new_n4439 $abc$27210$new_n4505 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n8038 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21961 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4510 DBusCachedPlugin_redoBranch_payload[21] IBusCachedPlugin_predictionJumpInterface_payload[21] $abc$27210$new_n4434 $abc$27210$new_n8040 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names $abc$27210$new_n4439 $abc$27210$new_n4511 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] $abc$27210$new_n8040 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21963 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$27210$new_n4517 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[20] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[20] $abc$27210$new_n8042 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8042 $abc$27210$new_n4447 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8043 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8043 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$new_n8044 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11101 1 -11111 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] $abc$27210$new_n8044 $abc$27210$auto$rtlil.cc:2693:MuxGate$21965 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4524 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[19] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[19] $abc$27210$new_n8046 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8046 $abc$27210$new_n4447 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8047 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8047 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n8048 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11101 1 -11111 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] $abc$27210$new_n8048 $abc$27210$auto$rtlil.cc:2693:MuxGate$21967 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4531 DBusCachedPlugin_redoBranch_payload[18] IBusCachedPlugin_predictionJumpInterface_payload[18] $abc$27210$new_n4434 $abc$27210$new_n8050 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names $abc$27210$new_n4439 $abc$27210$new_n4532 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8050 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21969 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4537 DBusCachedPlugin_redoBranch_payload[17] IBusCachedPlugin_predictionJumpInterface_payload[17] $abc$27210$new_n4434 $abc$27210$new_n8052 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names $abc$27210$new_n4439 $abc$27210$new_n4538 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] $abc$27210$new_n8052 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21971 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$27210$new_n4544 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[16] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[16] $abc$27210$new_n8054 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8054 $abc$27210$new_n4448 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8055 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8055 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n8056 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11101 1 -11111 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] $abc$27210$new_n8056 $abc$27210$auto$rtlil.cc:2693:MuxGate$21973 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4551 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[15] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[15] $abc$27210$new_n8058 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8058 $abc$27210$new_n4448 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8059 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8059 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n8060 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11101 1 -11111 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] $abc$27210$new_n8060 $abc$27210$auto$rtlil.cc:2693:MuxGate$21975 -010 1 -011 1 -101 1 -111 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4558 DBusCachedPlugin_redoBranch_payload[14] IBusCachedPlugin_predictionJumpInterface_payload[14] $abc$27210$new_n4434 $abc$27210$new_n8062 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names $abc$27210$new_n4439 $abc$27210$new_n4559 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8062 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21977 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$27210$new_n4423 $abc$27210$new_n4564 DBusCachedPlugin_redoBranch_payload[13] IBusCachedPlugin_predictionJumpInterface_payload[13] $abc$27210$new_n4434 $abc$27210$new_n8064 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names $abc$27210$new_n4439 $abc$27210$new_n4565 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] $abc$27210$new_n8064 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21979 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$27210$new_n4571 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[12] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[12] $abc$27210$new_n8066 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8066 $abc$27210$new_n4449 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n8067 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$27210$new_n4435 $abc$27210$new_n8067 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n8068 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11101 1 -11111 1 -.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] $abc$27210$new_n8068 $abc$27210$auto$rtlil.cc:2693:MuxGate$21981 -010 1 -011 1 -101 1 -111 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4728 $abc$27210$new_n4722 $abc$27210$new_n4714 $abc$27210$new_n8071 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11110 1 -.names $abc$27210$new_n4711 $abc$27210$new_n4721 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4712 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n8074 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$27210$new_n8078 IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$new_n4705 $abc$27210$new_n8074 $abc$27210$new_n8075 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n8077 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n8077 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n8078 -00 1 -01 1 -11 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_41 _zz__zz_decode_IS_CSR_21 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n8079 -01100 1 -01101 1 -10001 1 -10011 1 -.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$new_n8079 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n8080 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n8081 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] $abc$27210$new_n8081 DBusCachedPlugin_exceptionBus_payload_badAddr[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23089 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n8083 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] $abc$27210$new_n8083 DBusCachedPlugin_exceptionBus_payload_badAddr[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23091 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4279 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$new_n8086 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n4763 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n8088 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n4761 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n8091 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8091 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n8092 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n8094 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] $abc$27210$new_n8094 DBusCachedPlugin_exceptionBus_payload_badAddr[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23101 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n8096 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] $abc$27210$new_n8096 DBusCachedPlugin_exceptionBus_payload_badAddr[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23105 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n8098 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] $abc$27210$new_n8098 DBusCachedPlugin_exceptionBus_payload_badAddr[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23107 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 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-01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$27210$new_n4327 $abc$27210$new_n8154 $abc$27210$new_n6947 $abc$27210$new_n4264 $abc$27210$new_n5363 $abc$27210$new_n8155 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n5373 $abc$27210$new_n6803 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6755 $abc$27210$new_n8156 -01000 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11111 1 -.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8156 $abc$27210$new_n6959 $abc$27210$new_n8157 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 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$abc$27210$new_n8160 $abc$27210$new_n6975 $abc$27210$new_n4264 $abc$27210$new_n5383 $abc$27210$new_n8161 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$27210$new_n6089 $abc$27210$new_n6996 $abc$27210$new_n7001 $abc$27210$new_n8162 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$27210$new_n4264 $abc$27210$new_n4327 $abc$27210$new_n8162 $abc$27210$new_n5405 $abc$27210$new_n8163 -0010 1 -0011 1 -1000 1 -1010 1 -.names $abc$27210$new_n7080 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] HazardSimplePlugin_writeBackBuffer_payload_address[1] HazardSimplePlugin_writeBackBuffer_payload_address[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n8164 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n8164 IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] HazardSimplePlugin_writeBackBuffer_payload_address[3] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8165 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n7086 HazardSimplePlugin_writeBackWrites_payload_address[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n8166 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8166 HazardSimplePlugin_writeBackWrites_payload_address[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n8167 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8167 HazardSimplePlugin_writeBackWrites_payload_address[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8168 -100 1 -111 1 -.names $abc$27210$new_n5843 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6999 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8169 -00011 1 -00101 1 -00111 1 -01001 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8169 $abc$27210$new_n6997 $abc$27210$new_n8170 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$27210$new_n4327 $abc$27210$new_n8170 $abc$27210$new_n7631 $abc$27210$new_n4264 $abc$27210$new_n5841 $abc$27210$new_n8171 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$27210$new_n7714 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[15] $abc$27210$new_n4128 $abc$27210$new_n4174 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[8] $abc$27210$new_n8172 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8172 $abc$27210$new_n8216 dataCache_1.stageB_waysHit $abc$27210$new_n4094 $abc$27210$new_n4100 $abc$27210$auto$rtlil.cc:2693:MuxGate$24795 -00110 1 -01110 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[14] $abc$27210$new_n4134 $abc$27210$new_n7712 $abc$27210$new_n4111 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] $abc$27210$new_n8175 -00000 1 -00001 1 -00010 1 -11000 1 -11001 1 -11010 1 -.names dataCache_1.dataWriteCmd_payload_address[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] dataCache_1.dataWriteCmd_payload_address[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] $abc$27210$new_n8178 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$27210$new_n6003 dBus_cmd_payload_mask[2] dBus_cmd_payload_mask[1] dataCache_1.stageA_mask[1] dataCache_1.stageA_mask[2] $abc$27210$new_n8179 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names $abc$27210$new_n6003 dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[3] dataCache_1.stageA_mask[3] dataCache_1.stageA_mask[0] $abc$27210$new_n8180 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names $abc$27210$new_n8178 $abc$27210$new_n8179 $abc$27210$new_n8180 $abc$27210$new_n8181 -100 1 -101 1 -110 1 -.names $abc$27210$new_n6003 $abc$27210$new_n6087 dBus_cmd_payload_mask[3] dBus_cmd_payload_mask[2] $abc$27210$new_n7756 $abc$27210$new_n8182 -00000 1 -00001 1 -00100 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$27210$new_n7751 dataCache_1.dataReadCmd_payload[2] dataCache_1.dataWriteCmd_payload_address[2] dataCache_1.dataReadCmd_payload[1] dataCache_1.dataWriteCmd_payload_address[1] $abc$27210$new_n8183 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8183 dataCache_1.dataReadCmd_payload[3] dBus_cmd_payload_address[5] $abc$27210$new_n7755 $abc$27210$new_n8182 $abc$27210$new_n8184 -10000 1 -10001 1 -10010 1 -11100 1 -11101 1 -11110 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_1_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_1_virtualAddress_0[3] $abc$27210$new_n4033 $abc$27210$new_n8185 -00000 1 -00110 1 -11000 1 -11110 1 -.names $abc$27210$new_n8185 MmuPlugin_ports_1_cache_1_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_1_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n8186 -10000 1 -10011 1 -11100 1 -11111 1 -.names MmuPlugin_ports_1_cache_0_valid DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_0_virtualAddress_1[3] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n8188 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names MmuPlugin_ports_1_cache_2_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_2_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n8191 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$27210$new_n8191 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_2_virtualAddress_0[4] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n8192 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n8192 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_ports_1_cache_2_virtualAddress_0[8] MmuPlugin_ports_1_cache_2_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$new_n8193 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_4_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_4_virtualAddress_0[0] $abc$27210$new_n3972 $abc$27210$new_n8194 -00000 1 -00110 1 -11000 1 -11110 1 -.names $abc$27210$new_n8003 $abc$27210$new_n8194 MmuPlugin_ports_1_cache_4_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n8195 -1100 1 -1111 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_ports_1_cache_1_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_1_virtualAddress_1[6] $abc$27210$new_n4046 $abc$27210$new_n8196 -00000 1 -00110 1 -11000 1 -11110 1 -.names MmuPlugin_ports_1_cache_1_valid MmuPlugin_ports_1_cache_1_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_1_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n8197 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8025 MmuPlugin_ports_1_cache_3_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8199 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n8029 MmuPlugin_ports_1_cache_5_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n8201 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n8030 $abc$27210$new_n4023 $abc$27210$new_n4020 MmuPlugin_ports_1_cache_5_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n8202 -11100 1 -11111 1 -.names $abc$27210$new_n8201 $abc$27210$new_n8202 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_ports_1_cache_5_virtualAddress_1[4] $abc$27210$new_n8011 $abc$27210$new_n8203 -11000 1 -11110 1 -.names $abc$27210$new_n4736 $abc$27210$new_n4735 $abc$27210$new_n4706 $abc$27210$new_n4722 $abc$27210$new_n4731 $abc$27210$new_n8204 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$27210$new_n4725 $abc$27210$new_n4266 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n8204 $abc$27210$new_n8080 $abc$27210$new_n8206 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -.names $abc$27210$new_n8206 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n8071 _zz__zz_decode_IS_CSR_41 $abc$27210$new_n4740 $abc$27210$new_n8207 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$27210$new_n8207 $abc$27210$new_n8075 $abc$27210$new_n4722 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4723 $abc$27210$new_n8208 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n4280 $abc$27210$new_n4275 $abc$27210$new_n4274 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] $abc$27210$new_n8209 -00000 1 -00010 1 -00011 1 -.names $abc$27210$new_n8209 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n8210 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8210 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n8211 -100 1 -111 1 -.names $abc$27210$new_n4764 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n8212 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8211 $abc$27210$new_n8092 $abc$27210$new_n8088 $abc$27210$new_n8086 $abc$27210$new_n8212 $abc$27210$new_n8213 -11111 1 -.names $abc$27210$new_n7721 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[3] $abc$27210$new_n4204 $abc$27210$new_n4210 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[2] $abc$27210$new_n8214 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n7723 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[17] $abc$27210$new_n4116 $abc$27210$new_n4168 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[9] $abc$27210$new_n8215 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8175 $abc$27210$new_n7718 $abc$27210$new_n7715 $abc$27210$new_n8215 $abc$27210$new_n8214 $abc$27210$new_n8216 -11111 1 -.names $abc$27210$new_n8197 MmuPlugin_ports_1_cache_1_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_1_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8217 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8196 $abc$27210$new_n4048 $abc$27210$new_n8217 MmuPlugin_ports_1_cache_1_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8218 -11100 1 -11111 1 -.names $abc$27210$new_n8218 MmuPlugin_ports_1_cache_1_superPage $abc$27210$new_n8186 $abc$27210$new_n8013 $abc$27210$new_n8219 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$27210$new_n8188 MmuPlugin_ports_1_cache_0_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_0_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8220 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8035 MmuPlugin_ports_1_cache_0_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8222 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n8220 MmuPlugin_ports_1_cache_0_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_0_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n8223 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n4049 $abc$27210$new_n8223 $abc$27210$new_n8222 $abc$27210$new_n4370 $abc$27210$new_n8224 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$27210$new_n4333 MmuPlugin_ports_1_cache_3_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8225 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$27210$new_n8199 MmuPlugin_ports_1_cache_3_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_3_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n8226 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$27210$new_n8226 $abc$27210$new_n8225 $abc$27210$new_n3990 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] $abc$27210$new_n8227 -11000 1 -11001 1 -11011 1 -.subckt dff C=clk D=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid Q=IBusCachedPlugin_cache._zz_when_InstructionCache_l342 -.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24235 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[0] R=IBusCachedPlugin_cache.when_InstructionCache_l351 -.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24233 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[1] R=IBusCachedPlugin_cache.when_InstructionCache_l351 -.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24231 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[2] R=IBusCachedPlugin_cache.when_InstructionCache_l351 -.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24229 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[3] R=IBusCachedPlugin_cache.when_InstructionCache_l351 -.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24227 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[4] R=IBusCachedPlugin_cache.when_InstructionCache_l351 -.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24225 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[5] R=IBusCachedPlugin_cache.when_InstructionCache_l351 -.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24867 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[6] R=IBusCachedPlugin_cache.when_InstructionCache_l351 -.subckt sdffr C=clk D=$abc$27210$flatten\IBusCachedPlugin_cache.$procmux$1907_Y[7] Q=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid R=IBusCachedPlugin_cache.when_InstructionCache_l351 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24223 Q=CsrPlugin_mcause_exceptionCode[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24881 Q=CsrPlugin_mcause_exceptionCode[3] -.subckt dffr C=clk D=$abc$27210$flatten\dataCache_1.$0\stageB_flusher_counter[7:0][7] Q=dataCache_1.stageB_flusher_counter[7] R=reset -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24221 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24219 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24217 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24215 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24213 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24211 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24209 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24207 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24205 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24203 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24201 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24199 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24197 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24195 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24193 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24191 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24189 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24187 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24185 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24183 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24181 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24179 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24177 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24175 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24173 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24171 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24169 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24167 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24165 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24163 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24161 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24655 Q=memory_DivPlugin_div_stage_0_remainderShifted -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24641 Q=CsrPlugin_interrupt_code[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24637 Q=CsrPlugin_interrupt_code[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24159 Q=CsrPlugin_mcause_exceptionCode[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24879 Q=CsrPlugin_mcause_exceptionCode[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24903 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] -.subckt dffr C=clk D=$0\DebugPlugin_haltIt[0:0] Q=DebugPlugin_haltIt R=debugReset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24791 Q=DebugPlugin_resetIt R=debugReset -.subckt dffr C=clk D=$0\DebugPlugin_godmode[0:0] Q=DebugPlugin_godmode R=debugReset -.subckt dffr C=clk D=$0\DebugPlugin_haltedByBreak[0:0] Q=DebugPlugin_haltedByBreak R=debugReset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24789 Q=DebugPlugin_stepIt R=debugReset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24787 Q=DebugPlugin_debugUsed R=debugReset -.subckt dff C=clk D=$0\DebugPlugin_isPipBusy[0:0] Q=DebugPlugin_isPipBusy -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24785 Q=DebugPlugin_disableEbreak R=debugReset -.subckt dff C=clk D=debug_bus_cmd_payload_address[2] Q=_zz_when_DebugPlugin_l257 -.subckt dff C=clk D=DebugPlugin_resetIt Q=debug_resetOut -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24155 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24153 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24151 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24149 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24147 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24145 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24143 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24141 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24139 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24137 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24135 Q=execute_to_memory_PC[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24133 Q=execute_to_memory_PC[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24131 Q=execute_to_memory_PC[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24129 Q=execute_to_memory_PC[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24127 Q=execute_to_memory_PC[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24125 Q=execute_to_memory_PC[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24123 Q=execute_to_memory_PC[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24121 Q=execute_to_memory_PC[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24119 Q=execute_to_memory_PC[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24117 Q=execute_to_memory_PC[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24115 Q=execute_to_memory_PC[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24113 Q=execute_to_memory_PC[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24111 Q=execute_to_memory_PC[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24109 Q=execute_to_memory_PC[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24107 Q=execute_to_memory_PC[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24105 Q=execute_to_memory_PC[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24103 Q=execute_to_memory_PC[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24101 Q=execute_to_memory_PC[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24099 Q=execute_to_memory_PC[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24895 Q=execute_to_memory_PC[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24783 Q=_zz_decode_PREDICTION_CONTEXT_hazard_2 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24097 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24095 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24093 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24091 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24089 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24087 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24085 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24083 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24081 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24781 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24779 Q=_zz_decode_PREDICTION_CONTEXT_hazard_4 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24079 Q=_zz_decode_PREDICTION_CONTEXT_line_history_2[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24777 Q=_zz_decode_PREDICTION_CONTEXT_line_history_2[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24077 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24075 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24073 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24071 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24069 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24067 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24065 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24063 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24061 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24059 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24057 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24055 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24053 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24051 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24049 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24047 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24045 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24043 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24041 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24039 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24037 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24035 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24033 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24031 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24029 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24027 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24025 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24023 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24021 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24883 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24019 Q=MmuPlugin_satp_asid[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24017 Q=MmuPlugin_satp_asid[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24015 Q=MmuPlugin_satp_asid[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24013 Q=MmuPlugin_satp_asid[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24011 Q=MmuPlugin_satp_asid[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24009 Q=MmuPlugin_satp_asid[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24007 Q=MmuPlugin_satp_asid[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24005 Q=MmuPlugin_satp_asid[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24775 Q=MmuPlugin_satp_asid[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24003 Q=MmuPlugin_satp_ppn[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24001 Q=MmuPlugin_satp_ppn[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23999 Q=MmuPlugin_satp_ppn[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23997 Q=MmuPlugin_satp_ppn[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23995 Q=MmuPlugin_satp_ppn[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23993 Q=MmuPlugin_satp_ppn[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23991 Q=MmuPlugin_satp_ppn[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23989 Q=MmuPlugin_satp_ppn[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23987 Q=MmuPlugin_satp_ppn[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23985 Q=MmuPlugin_satp_ppn[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23983 Q=MmuPlugin_satp_ppn[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23981 Q=MmuPlugin_satp_ppn[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23979 Q=MmuPlugin_satp_ppn[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23977 Q=MmuPlugin_satp_ppn[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23975 Q=MmuPlugin_satp_ppn[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23973 Q=MmuPlugin_satp_ppn[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23971 Q=MmuPlugin_satp_ppn[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23969 Q=MmuPlugin_satp_ppn[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23967 Q=MmuPlugin_satp_ppn[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23965 Q=MmuPlugin_satp_ppn[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23963 Q=MmuPlugin_satp_ppn[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24773 Q=MmuPlugin_satp_ppn[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24771 Q=MmuPlugin_ports_1_cache_0_exception -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24769 Q=MmuPlugin_ports_1_cache_0_superPage -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23961 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23959 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23957 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23955 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23953 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23951 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23949 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23947 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23945 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24767 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23943 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23941 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23939 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23937 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23935 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23933 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23931 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23929 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23927 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24765 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23925 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23923 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23921 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23919 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23917 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23915 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23913 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23911 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23909 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24763 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23907 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23905 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23903 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23901 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23899 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23897 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23895 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23893 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23891 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24761 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24759 Q=MmuPlugin_ports_1_cache_0_allowRead -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24757 Q=MmuPlugin_ports_1_cache_0_allowWrite -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24755 Q=MmuPlugin_ports_1_cache_0_allowExecute -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24753 Q=MmuPlugin_ports_1_cache_1_exception -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24751 Q=MmuPlugin_ports_1_cache_1_superPage -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23889 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23887 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23885 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23883 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23881 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23879 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23877 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23875 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23873 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24749 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23871 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23869 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23867 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23865 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23863 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23861 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23859 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23857 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23855 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24747 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23853 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23851 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23849 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23847 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23845 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23843 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23841 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23839 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23837 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24745 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23835 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23833 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23831 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23829 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23827 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23825 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23823 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23821 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23819 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24743 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24741 Q=MmuPlugin_ports_1_cache_1_allowRead -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24739 Q=MmuPlugin_ports_1_cache_1_allowWrite -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24737 Q=MmuPlugin_ports_1_cache_1_allowExecute -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24735 Q=MmuPlugin_ports_1_cache_2_exception -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24733 Q=MmuPlugin_ports_1_cache_2_superPage -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23817 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23815 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23813 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23811 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23809 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23807 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23805 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23803 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23801 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24731 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23799 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23797 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23795 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23793 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23791 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23789 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23787 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23785 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23783 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24729 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23781 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23779 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23777 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23775 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23773 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23771 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23769 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23767 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23765 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24727 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23763 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23761 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23759 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23757 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23755 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23753 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23751 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23749 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23747 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24725 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24723 Q=MmuPlugin_ports_1_cache_2_allowRead -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24721 Q=MmuPlugin_ports_1_cache_2_allowWrite -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24719 Q=MmuPlugin_ports_1_cache_2_allowExecute -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24717 Q=MmuPlugin_ports_1_cache_3_exception -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24715 Q=MmuPlugin_ports_1_cache_3_superPage -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23745 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23743 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23741 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23739 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23737 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23735 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23733 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23731 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23729 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24713 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23727 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23725 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23723 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23721 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23719 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23717 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23715 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23713 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23711 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24711 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23709 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23707 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23705 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23703 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23701 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23699 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23697 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23695 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23693 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24709 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23691 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23689 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23687 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23685 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23683 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23681 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23679 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23677 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23675 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24707 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24705 Q=MmuPlugin_ports_1_cache_3_allowRead -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24703 Q=MmuPlugin_ports_1_cache_3_allowWrite -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24701 Q=MmuPlugin_ports_1_cache_3_allowExecute -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24699 Q=MmuPlugin_ports_1_cache_4_exception -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24697 Q=MmuPlugin_ports_1_cache_4_superPage -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23673 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23671 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23669 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23667 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23665 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23663 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23661 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23659 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23657 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24695 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23655 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23653 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23651 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23649 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23647 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23645 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23643 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23641 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23639 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24693 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23637 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23635 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23633 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23631 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23629 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23627 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23625 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23623 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23621 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24691 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23619 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23617 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23615 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23613 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23611 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23609 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23607 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23605 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23603 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24689 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24687 Q=MmuPlugin_ports_1_cache_4_allowRead -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24685 Q=MmuPlugin_ports_1_cache_4_allowWrite -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24683 Q=MmuPlugin_ports_1_cache_4_allowExecute -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24681 Q=MmuPlugin_ports_1_cache_5_exception -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24679 Q=MmuPlugin_ports_1_cache_5_superPage -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23601 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23599 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23597 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23595 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23593 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23591 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23589 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23587 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23585 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24677 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23583 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23581 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23579 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23577 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23575 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23573 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23571 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23569 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23567 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24675 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23565 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23563 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23561 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23559 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23557 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23555 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23553 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23551 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23549 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24673 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23547 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23545 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23543 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23541 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23539 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23537 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23535 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23533 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23531 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24671 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24669 Q=MmuPlugin_ports_1_cache_5_allowRead -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24667 Q=MmuPlugin_ports_1_cache_5_allowWrite -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24665 Q=MmuPlugin_ports_1_cache_5_allowExecute -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23529 Q=MmuPlugin_shared_vpn_0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23527 Q=MmuPlugin_shared_vpn_0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23525 Q=MmuPlugin_shared_vpn_0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23523 Q=MmuPlugin_shared_vpn_0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23521 Q=MmuPlugin_shared_vpn_0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23519 Q=MmuPlugin_shared_vpn_0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23517 Q=MmuPlugin_shared_vpn_0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23515 Q=MmuPlugin_shared_vpn_0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23513 Q=MmuPlugin_shared_vpn_0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24663 Q=MmuPlugin_shared_vpn_0[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23511 Q=MmuPlugin_shared_vpn_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23509 Q=MmuPlugin_shared_vpn_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23507 Q=MmuPlugin_shared_vpn_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23505 Q=MmuPlugin_shared_vpn_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23503 Q=MmuPlugin_shared_vpn_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23501 Q=MmuPlugin_shared_vpn_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23499 Q=MmuPlugin_shared_vpn_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23497 Q=MmuPlugin_shared_vpn_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23495 Q=MmuPlugin_shared_vpn_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24661 Q=MmuPlugin_shared_vpn_1[9] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[0] Q=MmuPlugin_shared_dBusRsp_pte_V -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[1] Q=MmuPlugin_shared_dBusRsp_pte_R -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[2] Q=MmuPlugin_shared_dBusRsp_pte_W -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[3] Q=MmuPlugin_shared_dBusRsp_pte_X -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[6] Q=MmuPlugin_shared_dBusRsp_pte_A -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[7] Q=MmuPlugin_shared_dBusRsp_pte_D -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[10] Q=MmuPlugin_shared_dBusRspStaged_payload_data[10] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[11] Q=MmuPlugin_shared_dBusRspStaged_payload_data[11] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[12] Q=MmuPlugin_shared_dBusRspStaged_payload_data[12] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[13] Q=MmuPlugin_shared_dBusRspStaged_payload_data[13] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[14] Q=MmuPlugin_shared_dBusRspStaged_payload_data[14] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[15] Q=MmuPlugin_shared_dBusRspStaged_payload_data[15] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[16] Q=MmuPlugin_shared_dBusRspStaged_payload_data[16] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[17] Q=MmuPlugin_shared_dBusRspStaged_payload_data[17] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[18] Q=MmuPlugin_shared_dBusRspStaged_payload_data[18] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[19] Q=MmuPlugin_shared_dBusRspStaged_payload_data[19] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[20] Q=MmuPlugin_shared_dBusRspStaged_payload_data[20] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[21] Q=MmuPlugin_shared_dBusRspStaged_payload_data[21] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[22] Q=MmuPlugin_shared_dBusRspStaged_payload_data[22] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[23] Q=MmuPlugin_shared_dBusRspStaged_payload_data[23] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[24] Q=MmuPlugin_shared_dBusRspStaged_payload_data[24] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[25] Q=MmuPlugin_shared_dBusRspStaged_payload_data[25] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[26] Q=MmuPlugin_shared_dBusRspStaged_payload_data[26] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[27] Q=MmuPlugin_shared_dBusRspStaged_payload_data[27] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[28] Q=MmuPlugin_shared_dBusRspStaged_payload_data[28] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[29] Q=MmuPlugin_shared_dBusRspStaged_payload_data[29] -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_error Q=MmuPlugin_shared_dBusRspStaged_payload_error -.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_redo Q=MmuPlugin_shared_dBusRspStaged_payload_redo -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23493 Q=MmuPlugin_shared_pteBuffer_PPN0[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23491 Q=MmuPlugin_shared_pteBuffer_PPN0[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23489 Q=MmuPlugin_shared_pteBuffer_PPN0[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23487 Q=MmuPlugin_shared_pteBuffer_PPN0[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23485 Q=MmuPlugin_shared_pteBuffer_PPN0[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23483 Q=MmuPlugin_shared_pteBuffer_PPN0[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23481 Q=MmuPlugin_shared_pteBuffer_PPN0[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23479 Q=MmuPlugin_shared_pteBuffer_PPN0[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23477 Q=MmuPlugin_shared_pteBuffer_PPN0[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24659 Q=MmuPlugin_shared_pteBuffer_PPN0[9] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[0] Q=HazardSimplePlugin_writeBackBuffer_payload_data[0] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[1] Q=HazardSimplePlugin_writeBackBuffer_payload_data[1] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[2] Q=HazardSimplePlugin_writeBackBuffer_payload_data[2] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[3] Q=HazardSimplePlugin_writeBackBuffer_payload_data[3] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[4] Q=HazardSimplePlugin_writeBackBuffer_payload_data[4] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[5] Q=HazardSimplePlugin_writeBackBuffer_payload_data[5] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[6] Q=HazardSimplePlugin_writeBackBuffer_payload_data[6] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[7] Q=HazardSimplePlugin_writeBackBuffer_payload_data[7] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[8] Q=HazardSimplePlugin_writeBackBuffer_payload_data[8] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[9] Q=HazardSimplePlugin_writeBackBuffer_payload_data[9] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[10] Q=HazardSimplePlugin_writeBackBuffer_payload_data[10] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[11] Q=HazardSimplePlugin_writeBackBuffer_payload_data[11] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[12] Q=HazardSimplePlugin_writeBackBuffer_payload_data[12] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[13] Q=HazardSimplePlugin_writeBackBuffer_payload_data[13] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[14] Q=HazardSimplePlugin_writeBackBuffer_payload_data[14] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[15] Q=HazardSimplePlugin_writeBackBuffer_payload_data[15] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[16] Q=HazardSimplePlugin_writeBackBuffer_payload_data[16] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[17] Q=HazardSimplePlugin_writeBackBuffer_payload_data[17] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[18] Q=HazardSimplePlugin_writeBackBuffer_payload_data[18] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[19] Q=HazardSimplePlugin_writeBackBuffer_payload_data[19] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[20] Q=HazardSimplePlugin_writeBackBuffer_payload_data[20] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[21] Q=HazardSimplePlugin_writeBackBuffer_payload_data[21] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[22] Q=HazardSimplePlugin_writeBackBuffer_payload_data[22] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[23] Q=HazardSimplePlugin_writeBackBuffer_payload_data[23] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[24] Q=HazardSimplePlugin_writeBackBuffer_payload_data[24] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[25] Q=HazardSimplePlugin_writeBackBuffer_payload_data[25] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[26] Q=HazardSimplePlugin_writeBackBuffer_payload_data[26] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[27] Q=HazardSimplePlugin_writeBackBuffer_payload_data[27] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[28] Q=HazardSimplePlugin_writeBackBuffer_payload_data[28] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[29] Q=HazardSimplePlugin_writeBackBuffer_payload_data[29] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[30] Q=HazardSimplePlugin_writeBackBuffer_payload_data[30] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[31] Q=HazardSimplePlugin_writeBackBuffer_payload_data[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23475 Q=MmuPlugin_shared_pteBuffer_PPN1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23473 Q=MmuPlugin_shared_pteBuffer_PPN1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23471 Q=MmuPlugin_shared_pteBuffer_PPN1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23469 Q=MmuPlugin_shared_pteBuffer_PPN1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23467 Q=MmuPlugin_shared_pteBuffer_PPN1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23465 Q=MmuPlugin_shared_pteBuffer_PPN1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23463 Q=MmuPlugin_shared_pteBuffer_PPN1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23461 Q=MmuPlugin_shared_pteBuffer_PPN1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23459 Q=MmuPlugin_shared_pteBuffer_PPN1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23457 Q=MmuPlugin_shared_pteBuffer_PPN1[9] -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23453 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23451 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23449 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23447 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23445 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23443 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23441 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23439 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23437 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23435 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23433 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23431 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23429 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23427 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23425 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23423 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23421 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23419 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23417 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23415 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23413 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23411 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23409 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23407 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23405 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23403 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23401 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23399 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23397 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23395 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23393 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24869 Q=memory_DivPlugin_accumulator[31] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23391 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23389 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23387 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23385 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23383 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23381 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23379 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23377 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23375 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23373 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23371 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23369 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23367 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23365 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23363 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23361 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23359 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23357 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23355 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23353 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23351 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23349 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23347 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23345 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23343 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23341 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23339 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23337 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23335 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23333 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23331 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24653 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] -.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24871 Q=memory_DivPlugin_div_done RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24651 Q=_zz_memory_DivPlugin_div_result_5 -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][0] Q=CsrPlugin_mepc[0] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][1] Q=CsrPlugin_mepc[1] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][2] Q=CsrPlugin_mepc[2] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][3] Q=CsrPlugin_mepc[3] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][4] Q=CsrPlugin_mepc[4] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][5] Q=CsrPlugin_mepc[5] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][6] Q=CsrPlugin_mepc[6] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][7] Q=CsrPlugin_mepc[7] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][8] Q=CsrPlugin_mepc[8] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][9] Q=CsrPlugin_mepc[9] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][10] Q=CsrPlugin_mepc[10] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][11] Q=CsrPlugin_mepc[11] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][12] Q=CsrPlugin_mepc[12] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][13] Q=CsrPlugin_mepc[13] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][14] Q=CsrPlugin_mepc[14] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][15] Q=CsrPlugin_mepc[15] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][16] Q=CsrPlugin_mepc[16] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][17] Q=CsrPlugin_mepc[17] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][18] Q=CsrPlugin_mepc[18] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][19] Q=CsrPlugin_mepc[19] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][20] Q=CsrPlugin_mepc[20] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][21] Q=CsrPlugin_mepc[21] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][22] Q=CsrPlugin_mepc[22] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][23] Q=CsrPlugin_mepc[23] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][24] Q=CsrPlugin_mepc[24] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][25] Q=CsrPlugin_mepc[25] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][26] Q=CsrPlugin_mepc[26] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][27] Q=CsrPlugin_mepc[27] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][28] Q=CsrPlugin_mepc[28] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][29] Q=CsrPlugin_mepc[29] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][30] Q=CsrPlugin_mepc[30] -.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][31] Q=CsrPlugin_mepc[31] -.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP -.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP -.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23329 Q=memory_DivPlugin_div_result[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23327 Q=memory_DivPlugin_div_result[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23325 Q=memory_DivPlugin_div_result[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23323 Q=memory_DivPlugin_div_result[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23321 Q=memory_DivPlugin_div_result[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23319 Q=memory_DivPlugin_div_result[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23317 Q=memory_DivPlugin_div_result[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23315 Q=memory_DivPlugin_div_result[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23313 Q=memory_DivPlugin_div_result[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23311 Q=memory_DivPlugin_div_result[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23309 Q=memory_DivPlugin_div_result[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23307 Q=memory_DivPlugin_div_result[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23305 Q=memory_DivPlugin_div_result[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23303 Q=memory_DivPlugin_div_result[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23301 Q=memory_DivPlugin_div_result[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23299 Q=memory_DivPlugin_div_result[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23297 Q=memory_DivPlugin_div_result[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23295 Q=memory_DivPlugin_div_result[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23293 Q=memory_DivPlugin_div_result[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23291 Q=memory_DivPlugin_div_result[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23289 Q=memory_DivPlugin_div_result[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23287 Q=memory_DivPlugin_div_result[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23285 Q=memory_DivPlugin_div_result[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23283 Q=memory_DivPlugin_div_result[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23281 Q=memory_DivPlugin_div_result[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23279 Q=memory_DivPlugin_div_result[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23277 Q=memory_DivPlugin_div_result[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23275 Q=memory_DivPlugin_div_result[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23273 Q=memory_DivPlugin_div_result[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23271 Q=memory_DivPlugin_div_result[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23269 Q=memory_DivPlugin_div_result[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24649 Q=memory_DivPlugin_div_result[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24647 Q=CsrPlugin_mcause_interrupt -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23267 Q=CsrPlugin_mtval[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23265 Q=CsrPlugin_mtval[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23263 Q=CsrPlugin_mtval[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23261 Q=CsrPlugin_mtval[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23259 Q=CsrPlugin_mtval[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23257 Q=CsrPlugin_mtval[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23255 Q=CsrPlugin_mtval[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23253 Q=CsrPlugin_mtval[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23251 Q=CsrPlugin_mtval[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23249 Q=CsrPlugin_mtval[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23247 Q=CsrPlugin_mtval[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23245 Q=CsrPlugin_mtval[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23243 Q=CsrPlugin_mtval[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23241 Q=CsrPlugin_mtval[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23239 Q=CsrPlugin_mtval[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23237 Q=CsrPlugin_mtval[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23235 Q=CsrPlugin_mtval[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23233 Q=CsrPlugin_mtval[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23231 Q=CsrPlugin_mtval[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23229 Q=CsrPlugin_mtval[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23227 Q=CsrPlugin_mtval[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23225 Q=CsrPlugin_mtval[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23223 Q=CsrPlugin_mtval[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23221 Q=CsrPlugin_mtval[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23219 Q=CsrPlugin_mtval[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23217 Q=CsrPlugin_mtval[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23215 Q=CsrPlugin_mtval[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23213 Q=CsrPlugin_mtval[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23211 Q=CsrPlugin_mtval[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23209 Q=CsrPlugin_mtval[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23207 Q=CsrPlugin_mtval[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24645 Q=CsrPlugin_mtval[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23205 Q=BranchPlugin_branchExceptionPort_payload_badAddr[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23203 Q=BranchPlugin_branchExceptionPort_payload_badAddr[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23201 Q=BranchPlugin_branchExceptionPort_payload_badAddr[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23199 Q=BranchPlugin_branchExceptionPort_payload_badAddr[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23197 Q=BranchPlugin_branchExceptionPort_payload_badAddr[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23195 Q=BranchPlugin_branchExceptionPort_payload_badAddr[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23193 Q=BranchPlugin_branchExceptionPort_payload_badAddr[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23191 Q=BranchPlugin_branchExceptionPort_payload_badAddr[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23189 Q=BranchPlugin_branchExceptionPort_payload_badAddr[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23187 Q=BranchPlugin_branchExceptionPort_payload_badAddr[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23185 Q=BranchPlugin_branchExceptionPort_payload_badAddr[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23183 Q=BranchPlugin_branchExceptionPort_payload_badAddr[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23181 Q=BranchPlugin_branchExceptionPort_payload_badAddr[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23179 Q=BranchPlugin_branchExceptionPort_payload_badAddr[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23177 Q=BranchPlugin_branchExceptionPort_payload_badAddr[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23175 Q=BranchPlugin_branchExceptionPort_payload_badAddr[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23173 Q=BranchPlugin_branchExceptionPort_payload_badAddr[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23171 Q=BranchPlugin_branchExceptionPort_payload_badAddr[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23169 Q=BranchPlugin_branchExceptionPort_payload_badAddr[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23167 Q=BranchPlugin_branchExceptionPort_payload_badAddr[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23165 Q=BranchPlugin_branchExceptionPort_payload_badAddr[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23163 Q=BranchPlugin_branchExceptionPort_payload_badAddr[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23161 Q=BranchPlugin_branchExceptionPort_payload_badAddr[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23159 Q=BranchPlugin_branchExceptionPort_payload_badAddr[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23157 Q=BranchPlugin_branchExceptionPort_payload_badAddr[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23155 Q=BranchPlugin_branchExceptionPort_payload_badAddr[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23153 Q=BranchPlugin_branchExceptionPort_payload_badAddr[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23151 Q=BranchPlugin_branchExceptionPort_payload_badAddr[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23149 Q=BranchPlugin_branchExceptionPort_payload_badAddr[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23147 Q=BranchPlugin_branchExceptionPort_payload_badAddr[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24873 Q=BranchPlugin_branchExceptionPort_payload_badAddr[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23145 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23143 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23141 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23139 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23137 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23135 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23133 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23131 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23129 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23127 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23125 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23123 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23121 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23119 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23117 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23115 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23113 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23111 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23109 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23107 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23105 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23103 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23101 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23099 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23097 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23095 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23093 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23091 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23089 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23087 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23085 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24643 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23083 Q=IBusCachedPlugin_cache.lineLoader_address[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23081 Q=IBusCachedPlugin_cache.lineLoader_address[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23079 Q=IBusCachedPlugin_cache.lineLoader_address[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23077 Q=iBus_cmd_payload_address[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23075 Q=iBus_cmd_payload_address[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23073 Q=iBus_cmd_payload_address[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23071 Q=iBus_cmd_payload_address[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23069 Q=iBus_cmd_payload_address[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23067 Q=iBus_cmd_payload_address[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23065 Q=iBus_cmd_payload_address[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23063 Q=iBus_cmd_payload_address[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23061 Q=iBus_cmd_payload_address[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23059 Q=iBus_cmd_payload_address[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23057 Q=iBus_cmd_payload_address[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23055 Q=iBus_cmd_payload_address[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23053 Q=iBus_cmd_payload_address[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23051 Q=iBus_cmd_payload_address[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23049 Q=iBus_cmd_payload_address[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23047 Q=iBus_cmd_payload_address[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23045 Q=iBus_cmd_payload_address[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23043 Q=iBus_cmd_payload_address[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23041 Q=iBus_cmd_payload_address[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23039 Q=iBus_cmd_payload_address[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23037 Q=iBus_cmd_payload_address[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23035 Q=iBus_cmd_payload_address[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23033 Q=iBus_cmd_payload_address[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23031 Q=iBus_cmd_payload_address[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23029 Q=iBus_cmd_payload_address[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23027 Q=iBus_cmd_payload_address[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24887 Q=iBus_cmd_payload_address[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23025 Q=DBusCachedPlugin_redoBranch_payload[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23023 Q=DBusCachedPlugin_redoBranch_payload[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23021 Q=DBusCachedPlugin_redoBranch_payload[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23019 Q=DBusCachedPlugin_redoBranch_payload[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23017 Q=DBusCachedPlugin_redoBranch_payload[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23015 Q=DBusCachedPlugin_redoBranch_payload[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23013 Q=DBusCachedPlugin_redoBranch_payload[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23011 Q=DBusCachedPlugin_redoBranch_payload[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23009 Q=DBusCachedPlugin_redoBranch_payload[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23007 Q=DBusCachedPlugin_redoBranch_payload[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23005 Q=DBusCachedPlugin_redoBranch_payload[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23003 Q=DBusCachedPlugin_redoBranch_payload[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23001 Q=DBusCachedPlugin_redoBranch_payload[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22999 Q=DBusCachedPlugin_redoBranch_payload[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22997 Q=DBusCachedPlugin_redoBranch_payload[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22995 Q=DBusCachedPlugin_redoBranch_payload[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22993 Q=DBusCachedPlugin_redoBranch_payload[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22991 Q=DBusCachedPlugin_redoBranch_payload[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22989 Q=DBusCachedPlugin_redoBranch_payload[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22987 Q=DBusCachedPlugin_redoBranch_payload[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22985 Q=DBusCachedPlugin_redoBranch_payload[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22983 Q=DBusCachedPlugin_redoBranch_payload[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22981 Q=DBusCachedPlugin_redoBranch_payload[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22979 Q=DBusCachedPlugin_redoBranch_payload[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22977 Q=DBusCachedPlugin_redoBranch_payload[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22975 Q=DBusCachedPlugin_redoBranch_payload[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22973 Q=DBusCachedPlugin_redoBranch_payload[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22971 Q=DBusCachedPlugin_redoBranch_payload[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22969 Q=DBusCachedPlugin_redoBranch_payload[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24897 Q=DBusCachedPlugin_redoBranch_payload[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22953 Q=_zz_execute_BranchPlugin_branch_src2_10 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22951 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22949 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22947 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22945 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22943 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22941 Q=switch_Misc_l241_1 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22939 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22937 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22935 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22933 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22931 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22929 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22927 Q=_zz_execute_BranchPlugin_branch_src2_8 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22925 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22923 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22921 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22919 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22917 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22915 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22913 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22911 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22909 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22907 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24633 Q=_zz_execute_BranchPlugin_branch_src2 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22891 Q=execute_to_memory_INSTRUCTION[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22889 Q=execute_to_memory_INSTRUCTION[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22887 Q=execute_to_memory_INSTRUCTION[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22885 Q=execute_to_memory_INSTRUCTION[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22883 Q=execute_to_memory_INSTRUCTION[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22881 Q=execute_to_memory_INSTRUCTION[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22879 Q=execute_to_memory_INSTRUCTION[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22877 Q=execute_to_memory_INSTRUCTION[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22849 Q=execute_to_memory_INSTRUCTION[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22847 Q=execute_to_memory_INSTRUCTION[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22829 Q=HazardSimplePlugin_writeBackWrites_payload_address[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22827 Q=HazardSimplePlugin_writeBackWrites_payload_address[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22825 Q=HazardSimplePlugin_writeBackWrites_payload_address[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22823 Q=HazardSimplePlugin_writeBackWrites_payload_address[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22821 Q=HazardSimplePlugin_writeBackWrites_payload_address[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22819 Q=_zz_lastStageRegFileWrite_payload_address[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22817 Q=_zz_lastStageRegFileWrite_payload_address[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22815 Q=_zz_lastStageRegFileWrite_payload_address[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22787 Q=_zz_lastStageRegFileWrite_payload_address[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22785 Q=_zz_lastStageRegFileWrite_payload_address[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24627 Q=decode_to_execute_PREDICTION_CONTEXT_hazard -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22781 Q=decode_to_execute_PREDICTION_CONTEXT_line_history[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24625 Q=decode_to_execute_PREDICTION_CONTEXT_line_history[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24623 Q=execute_to_memory_PREDICTION_CONTEXT_hazard -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22779 Q=execute_to_memory_PREDICTION_CONTEXT_line_history[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24621 Q=execute_to_memory_PREDICTION_CONTEXT_line_history[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22777 Q=_zz_execute_SRC1_CTRL[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24619 Q=_zz_execute_SRC1_CTRL[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24617 Q=_zz_execute_SrcPlugin_addSub_4 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24615 Q=decode_to_execute_MEMORY_ENABLE -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24613 Q=execute_to_memory_MEMORY_ENABLE -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24611 Q=memory_to_writeBack_MEMORY_ENABLE -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22775 Q=_zz_execute_ALU_CTRL[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24609 Q=_zz_execute_ALU_CTRL[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24605 Q=decode_to_execute_REGFILE_WRITE_VALID -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22773 Q=_zz_execute_SRC2_CTRL[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24607 Q=_zz_execute_SRC2_CTRL[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24601 Q=execute_to_memory_REGFILE_WRITE_VALID -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24599 Q=_zz_lastStageRegFileWrite_valid -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24597 Q=decode_to_execute_BYPASSABLE_EXECUTE_STAGE -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24595 Q=decode_to_execute_BYPASSABLE_MEMORY_STAGE -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24593 Q=execute_to_memory_BYPASSABLE_MEMORY_STAGE -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24591 Q=decode_to_execute_MEMORY_WR -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24589 Q=execute_to_memory_MEMORY_WR -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24587 Q=memory_to_writeBack_MEMORY_WR -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24585 Q=decode_to_execute_MEMORY_MANAGMENT -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24583 Q=decode_to_execute_IS_SFENCE_VMA2 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24581 Q=decode_to_execute_SRC_LESS_UNSIGNED -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22771 Q=_zz_execute_ALU_BITWISE_CTRL[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24579 Q=_zz_execute_ALU_BITWISE_CTRL[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22769 Q=_zz_execute_SHIFT_CTRL[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24577 Q=_zz_execute_SHIFT_CTRL[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22767 Q=_zz_memory_SHIFT_CTRL[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24575 Q=_zz_memory_SHIFT_CTRL[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24573 Q=decode_to_execute_IS_MUL -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24571 Q=execute_to_memory_IS_MUL -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24569 Q=memory_to_writeBack_IS_MUL -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24567 Q=decode_to_execute_IS_DIV -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24565 Q=execute_to_memory_IS_DIV -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24563 Q=decode_to_execute_IS_RS1_SIGNED -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24561 Q=decode_to_execute_IS_CSR -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24559 Q=_zz_execute_ENV_CTRL -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24557 Q=_zz_memory_ENV_CTRL -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24555 Q=_zz_writeBack_ENV_CTRL -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22765 Q=_zz_execute_BRANCH_CTRL[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24553 Q=_zz_execute_BRANCH_CTRL[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22763 Q=_zz_memory_BRANCH_CTRL[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24551 Q=_zz_memory_BRANCH_CTRL[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22761 Q=execute_RS1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22759 Q=execute_RS1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22757 Q=execute_RS1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22755 Q=execute_RS1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22753 Q=execute_RS1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22751 Q=execute_RS1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22749 Q=execute_RS1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22747 Q=execute_RS1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22745 Q=execute_RS1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22743 Q=execute_RS1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22741 Q=execute_RS1[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22739 Q=execute_RS1[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22737 Q=execute_RS1[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22735 Q=execute_RS1[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22733 Q=execute_RS1[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22731 Q=execute_RS1[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22729 Q=execute_RS1[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22727 Q=execute_RS1[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22725 Q=execute_RS1[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22723 Q=execute_RS1[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22721 Q=execute_RS1[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22719 Q=execute_RS1[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22717 Q=execute_RS1[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22715 Q=execute_RS1[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22713 Q=execute_RS1[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22711 Q=execute_RS1[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22709 Q=execute_RS1[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22707 Q=execute_RS1[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22705 Q=execute_RS1[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22703 Q=execute_RS1[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22701 Q=execute_RS1[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24549 Q=execute_RS1[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22699 Q=execute_RS2[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22697 Q=execute_RS2[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22695 Q=execute_RS2[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22693 Q=execute_RS2[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22691 Q=execute_RS2[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22689 Q=execute_RS2[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22687 Q=execute_RS2[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22685 Q=execute_RS2[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22683 Q=execute_RS2[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22681 Q=execute_RS2[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22679 Q=execute_RS2[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22677 Q=execute_RS2[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22675 Q=execute_RS2[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22673 Q=execute_RS2[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22671 Q=execute_RS2[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22669 Q=execute_RS2[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22667 Q=execute_RS2[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22665 Q=execute_RS2[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22663 Q=execute_RS2[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22661 Q=execute_RS2[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22659 Q=execute_RS2[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22657 Q=execute_RS2[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22655 Q=execute_RS2[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22653 Q=execute_RS2[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22651 Q=execute_RS2[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22649 Q=execute_RS2[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22647 Q=execute_RS2[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22645 Q=execute_RS2[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22643 Q=execute_RS2[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22641 Q=execute_RS2[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22639 Q=execute_RS2[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24547 Q=execute_RS2[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24545 Q=decode_to_execute_SRC2_FORCE_ZERO -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24543 Q=decode_to_execute_CSR_WRITE_OPCODE -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24541 Q=decode_to_execute_DO_EBREAK -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24539 Q=decode_to_execute_PREDICTION_HAD_BRANCHED2 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22637 Q=execute_to_memory_MEMORY_STORE_DATA_RF[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22635 Q=execute_to_memory_MEMORY_STORE_DATA_RF[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22633 Q=execute_to_memory_MEMORY_STORE_DATA_RF[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22631 Q=execute_to_memory_MEMORY_STORE_DATA_RF[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22629 Q=execute_to_memory_MEMORY_STORE_DATA_RF[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22627 Q=execute_to_memory_MEMORY_STORE_DATA_RF[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22625 Q=execute_to_memory_MEMORY_STORE_DATA_RF[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22623 Q=execute_to_memory_MEMORY_STORE_DATA_RF[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22621 Q=execute_to_memory_MEMORY_STORE_DATA_RF[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22619 Q=execute_to_memory_MEMORY_STORE_DATA_RF[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22617 Q=execute_to_memory_MEMORY_STORE_DATA_RF[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22615 Q=execute_to_memory_MEMORY_STORE_DATA_RF[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22613 Q=execute_to_memory_MEMORY_STORE_DATA_RF[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22611 Q=execute_to_memory_MEMORY_STORE_DATA_RF[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22609 Q=execute_to_memory_MEMORY_STORE_DATA_RF[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22607 Q=execute_to_memory_MEMORY_STORE_DATA_RF[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22605 Q=execute_to_memory_MEMORY_STORE_DATA_RF[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22603 Q=execute_to_memory_MEMORY_STORE_DATA_RF[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22601 Q=execute_to_memory_MEMORY_STORE_DATA_RF[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22599 Q=execute_to_memory_MEMORY_STORE_DATA_RF[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22597 Q=execute_to_memory_MEMORY_STORE_DATA_RF[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22595 Q=execute_to_memory_MEMORY_STORE_DATA_RF[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22593 Q=execute_to_memory_MEMORY_STORE_DATA_RF[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22591 Q=execute_to_memory_MEMORY_STORE_DATA_RF[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22589 Q=execute_to_memory_MEMORY_STORE_DATA_RF[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22587 Q=execute_to_memory_MEMORY_STORE_DATA_RF[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22585 Q=execute_to_memory_MEMORY_STORE_DATA_RF[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22583 Q=execute_to_memory_MEMORY_STORE_DATA_RF[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22581 Q=execute_to_memory_MEMORY_STORE_DATA_RF[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22579 Q=execute_to_memory_MEMORY_STORE_DATA_RF[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22577 Q=execute_to_memory_MEMORY_STORE_DATA_RF[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24537 Q=execute_to_memory_MEMORY_STORE_DATA_RF[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22575 Q=dBus_cmd_payload_data[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22573 Q=dBus_cmd_payload_data[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22571 Q=dBus_cmd_payload_data[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22569 Q=dBus_cmd_payload_data[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22567 Q=dBus_cmd_payload_data[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22565 Q=dBus_cmd_payload_data[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22563 Q=dBus_cmd_payload_data[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22561 Q=dBus_cmd_payload_data[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22559 Q=dBus_cmd_payload_data[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22557 Q=dBus_cmd_payload_data[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22555 Q=dBus_cmd_payload_data[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22553 Q=dBus_cmd_payload_data[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22551 Q=dBus_cmd_payload_data[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22549 Q=dBus_cmd_payload_data[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22547 Q=dBus_cmd_payload_data[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22545 Q=dBus_cmd_payload_data[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22543 Q=dBus_cmd_payload_data[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22541 Q=dBus_cmd_payload_data[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22539 Q=dBus_cmd_payload_data[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22537 Q=dBus_cmd_payload_data[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22535 Q=dBus_cmd_payload_data[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22533 Q=dBus_cmd_payload_data[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22531 Q=dBus_cmd_payload_data[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22529 Q=dBus_cmd_payload_data[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22527 Q=dBus_cmd_payload_data[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22525 Q=dBus_cmd_payload_data[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22523 Q=dBus_cmd_payload_data[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22521 Q=dBus_cmd_payload_data[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22519 Q=dBus_cmd_payload_data[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22517 Q=dBus_cmd_payload_data[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22515 Q=dBus_cmd_payload_data[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24535 Q=dBus_cmd_payload_data[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22513 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22511 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22509 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22507 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22505 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22503 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22501 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22499 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22497 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22495 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22493 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22491 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22489 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22487 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22485 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22483 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22481 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22479 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22477 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22475 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22473 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22471 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22469 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22467 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22465 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22463 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22461 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22459 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22457 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22455 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22453 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24533 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22451 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22449 Q=_zz_writeBack_DBusCachedPlugin_rspShifted_3 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22447 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22445 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22443 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22441 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22439 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22437 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22435 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22433 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22431 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22429 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22427 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22425 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22423 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22421 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22419 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22417 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22415 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22413 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22411 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22409 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22407 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22405 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22403 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22401 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22399 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22397 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22395 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22393 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22391 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24531 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22389 Q=_zz_decode_RS2_3[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22387 Q=_zz_decode_RS2_3[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22385 Q=_zz_decode_RS2_3[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22383 Q=_zz_decode_RS2_3[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22381 Q=_zz_decode_RS2_3[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22379 Q=_zz_decode_RS2_3[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22377 Q=_zz_decode_RS2_3[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22375 Q=_zz_decode_RS2_3[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22373 Q=_zz_decode_RS2_3[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22371 Q=_zz_decode_RS2_3[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22369 Q=_zz_decode_RS2_3[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22367 Q=_zz_decode_RS2_3[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22365 Q=_zz_decode_RS2_3[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22363 Q=_zz_decode_RS2_3[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22361 Q=_zz_decode_RS2_3[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22359 Q=_zz_decode_RS2_3[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22357 Q=_zz_decode_RS2_3[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22355 Q=_zz_decode_RS2_3[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22353 Q=_zz_decode_RS2_3[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22351 Q=_zz_decode_RS2_3[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22349 Q=_zz_decode_RS2_3[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22347 Q=_zz_decode_RS2_3[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22345 Q=_zz_decode_RS2_3[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22343 Q=_zz_decode_RS2_3[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22341 Q=_zz_decode_RS2_3[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22339 Q=_zz_decode_RS2_3[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22337 Q=_zz_decode_RS2_3[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22335 Q=_zz_decode_RS2_3[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22333 Q=_zz_decode_RS2_3[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22331 Q=_zz_decode_RS2_3[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22329 Q=_zz_decode_RS2_3[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24529 Q=_zz_decode_RS2_3[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22327 Q=_zz_memory_MUL_LOW_1[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22325 Q=_zz_memory_MUL_LOW_1[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22323 Q=_zz_memory_MUL_LOW_1[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22321 Q=_zz_memory_MUL_LOW_1[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22319 Q=_zz_memory_MUL_LOW_1[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22317 Q=_zz_memory_MUL_LOW_1[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22315 Q=_zz_memory_MUL_LOW_1[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22313 Q=_zz_memory_MUL_LOW_1[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22311 Q=_zz_memory_MUL_LOW_1[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22309 Q=_zz_memory_MUL_LOW_1[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22307 Q=_zz_memory_MUL_LOW_1[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22305 Q=_zz_memory_MUL_LOW_1[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22303 Q=_zz_memory_MUL_LOW_1[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22301 Q=_zz_memory_MUL_LOW_1[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22299 Q=_zz_memory_MUL_LOW_1[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22297 Q=_zz_memory_MUL_LOW_1[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22295 Q=_zz_memory_MUL_LOW_1[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22293 Q=_zz_memory_MUL_LOW_1[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22291 Q=_zz_memory_MUL_LOW_1[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22289 Q=_zz_memory_MUL_LOW_1[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22287 Q=_zz_memory_MUL_LOW_1[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22285 Q=_zz_memory_MUL_LOW_1[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22283 Q=_zz_memory_MUL_LOW_1[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22281 Q=_zz_memory_MUL_LOW_1[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22279 Q=_zz_memory_MUL_LOW_1[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22277 Q=_zz_memory_MUL_LOW_1[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22275 Q=_zz_memory_MUL_LOW_1[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22273 Q=_zz_memory_MUL_LOW_1[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22271 Q=_zz_memory_MUL_LOW_1[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22269 Q=_zz_memory_MUL_LOW_1[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22267 Q=_zz_memory_MUL_LOW_1[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24527 Q=_zz_memory_MUL_LOW_1[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22265 Q=_zz_memory_MUL_LOW_4[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22263 Q=_zz_memory_MUL_LOW_4[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22261 Q=_zz_memory_MUL_LOW_4[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22259 Q=_zz_memory_MUL_LOW_4[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22257 Q=_zz_memory_MUL_LOW_4[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22255 Q=_zz_memory_MUL_LOW_4[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22253 Q=_zz_memory_MUL_LOW_4[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22251 Q=_zz_memory_MUL_LOW_4[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22249 Q=_zz_memory_MUL_LOW_4[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22247 Q=_zz_memory_MUL_LOW_4[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22245 Q=_zz_memory_MUL_LOW_4[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22243 Q=_zz_memory_MUL_LOW_4[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22241 Q=_zz_memory_MUL_LOW_4[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22239 Q=_zz_memory_MUL_LOW_4[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22237 Q=_zz_memory_MUL_LOW_4[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22235 Q=_zz_memory_MUL_LOW_4[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22233 Q=_zz_memory_MUL_LOW_4[32] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22231 Q=_zz_memory_MUL_LOW_4[33] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22229 Q=_zz_memory_MUL_LOW_4[34] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22227 Q=_zz_memory_MUL_LOW_4[35] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22225 Q=_zz_memory_MUL_LOW_4[36] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22223 Q=_zz_memory_MUL_LOW_4[37] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22221 Q=_zz_memory_MUL_LOW_4[38] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22219 Q=_zz_memory_MUL_LOW_4[39] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22217 Q=_zz_memory_MUL_LOW_4[40] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22215 Q=_zz_memory_MUL_LOW_4[41] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22213 Q=_zz_memory_MUL_LOW_4[42] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22211 Q=_zz_memory_MUL_LOW_4[43] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22209 Q=_zz_memory_MUL_LOW_4[44] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22207 Q=_zz_memory_MUL_LOW_4[45] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22205 Q=_zz_memory_MUL_LOW_4[46] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22203 Q=_zz_memory_MUL_LOW_4[47] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22201 Q=_zz_memory_MUL_LOW_4[48] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24525 Q=_zz_memory_MUL_LOW_4[51] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22199 Q=_zz_memory_MUL_LOW_6[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22197 Q=_zz_memory_MUL_LOW_6[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22195 Q=_zz_memory_MUL_LOW_6[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22193 Q=_zz_memory_MUL_LOW_6[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22191 Q=_zz_memory_MUL_LOW_6[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22189 Q=_zz_memory_MUL_LOW_6[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22187 Q=_zz_memory_MUL_LOW_6[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22185 Q=_zz_memory_MUL_LOW_6[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22183 Q=_zz_memory_MUL_LOW_6[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22181 Q=_zz_memory_MUL_LOW_6[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22179 Q=_zz_memory_MUL_LOW_6[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22177 Q=_zz_memory_MUL_LOW_6[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22175 Q=_zz_memory_MUL_LOW_6[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22173 Q=_zz_memory_MUL_LOW_6[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22171 Q=_zz_memory_MUL_LOW_6[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22169 Q=_zz_memory_MUL_LOW_6[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22167 Q=_zz_memory_MUL_LOW_6[32] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22165 Q=_zz_memory_MUL_LOW_6[33] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22163 Q=_zz_memory_MUL_LOW_6[34] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22161 Q=_zz_memory_MUL_LOW_6[35] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22159 Q=_zz_memory_MUL_LOW_6[36] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22157 Q=_zz_memory_MUL_LOW_6[37] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22155 Q=_zz_memory_MUL_LOW_6[38] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22153 Q=_zz_memory_MUL_LOW_6[39] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22151 Q=_zz_memory_MUL_LOW_6[40] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22149 Q=_zz_memory_MUL_LOW_6[41] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22147 Q=_zz_memory_MUL_LOW_6[42] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22145 Q=_zz_memory_MUL_LOW_6[43] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22143 Q=_zz_memory_MUL_LOW_6[44] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22141 Q=_zz_memory_MUL_LOW_6[45] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22139 Q=_zz_memory_MUL_LOW_6[46] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22137 Q=_zz_memory_MUL_LOW_6[47] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22135 Q=_zz_memory_MUL_LOW_6[48] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24523 Q=_zz_memory_MUL_LOW_6[51] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22133 Q=execute_to_memory_MUL_HH[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22131 Q=execute_to_memory_MUL_HH[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22129 Q=execute_to_memory_MUL_HH[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22127 Q=execute_to_memory_MUL_HH[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22125 Q=execute_to_memory_MUL_HH[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22123 Q=execute_to_memory_MUL_HH[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22121 Q=execute_to_memory_MUL_HH[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22119 Q=execute_to_memory_MUL_HH[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22117 Q=execute_to_memory_MUL_HH[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22115 Q=execute_to_memory_MUL_HH[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22113 Q=execute_to_memory_MUL_HH[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22111 Q=execute_to_memory_MUL_HH[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22109 Q=execute_to_memory_MUL_HH[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22107 Q=execute_to_memory_MUL_HH[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22105 Q=execute_to_memory_MUL_HH[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22103 Q=execute_to_memory_MUL_HH[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22101 Q=execute_to_memory_MUL_HH[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22099 Q=execute_to_memory_MUL_HH[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22097 Q=execute_to_memory_MUL_HH[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22095 Q=execute_to_memory_MUL_HH[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22093 Q=execute_to_memory_MUL_HH[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22091 Q=execute_to_memory_MUL_HH[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22089 Q=execute_to_memory_MUL_HH[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22087 Q=execute_to_memory_MUL_HH[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22085 Q=execute_to_memory_MUL_HH[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22083 Q=execute_to_memory_MUL_HH[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22081 Q=execute_to_memory_MUL_HH[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22079 Q=execute_to_memory_MUL_HH[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22077 Q=execute_to_memory_MUL_HH[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22075 Q=execute_to_memory_MUL_HH[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22073 Q=execute_to_memory_MUL_HH[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22071 Q=execute_to_memory_MUL_HH[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22067 Q=_zz_writeBack_MulPlugin_result_1[32] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22065 Q=_zz_writeBack_MulPlugin_result_1[33] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22063 Q=_zz_writeBack_MulPlugin_result_1[34] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22061 Q=_zz_writeBack_MulPlugin_result_1[35] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22059 Q=_zz_writeBack_MulPlugin_result_1[36] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22057 Q=_zz_writeBack_MulPlugin_result_1[37] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22055 Q=_zz_writeBack_MulPlugin_result_1[38] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22053 Q=_zz_writeBack_MulPlugin_result_1[39] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22051 Q=_zz_writeBack_MulPlugin_result_1[40] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22049 Q=_zz_writeBack_MulPlugin_result_1[41] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22047 Q=_zz_writeBack_MulPlugin_result_1[42] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22045 Q=_zz_writeBack_MulPlugin_result_1[43] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22043 Q=_zz_writeBack_MulPlugin_result_1[44] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22041 Q=_zz_writeBack_MulPlugin_result_1[45] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22039 Q=_zz_writeBack_MulPlugin_result_1[46] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22037 Q=_zz_writeBack_MulPlugin_result_1[47] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22035 Q=_zz_writeBack_MulPlugin_result_1[48] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22033 Q=_zz_writeBack_MulPlugin_result_1[49] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22031 Q=_zz_writeBack_MulPlugin_result_1[50] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22029 Q=_zz_writeBack_MulPlugin_result_1[51] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22027 Q=_zz_writeBack_MulPlugin_result_1[52] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22025 Q=_zz_writeBack_MulPlugin_result_1[53] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22023 Q=_zz_writeBack_MulPlugin_result_1[54] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22021 Q=_zz_writeBack_MulPlugin_result_1[55] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22019 Q=_zz_writeBack_MulPlugin_result_1[56] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22017 Q=_zz_writeBack_MulPlugin_result_1[57] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22015 Q=_zz_writeBack_MulPlugin_result_1[58] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22013 Q=_zz_writeBack_MulPlugin_result_1[59] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22011 Q=_zz_writeBack_MulPlugin_result_1[60] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22009 Q=_zz_writeBack_MulPlugin_result_1[61] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22007 Q=_zz_writeBack_MulPlugin_result_1[62] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22005 Q=_zz_writeBack_MulPlugin_result_1[63] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24517 Q=execute_to_memory_BRANCH_DO -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22001 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21999 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21997 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21995 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21993 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21991 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21989 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21987 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21985 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21983 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21981 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21979 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21977 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21975 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21973 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21971 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21969 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21967 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21965 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21963 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21961 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21959 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21957 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21955 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21953 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21951 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21949 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21947 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21945 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] R=reset -.subckt dffs C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24875 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] S=reset -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21943 Q=_zz__zz_decode_RS2_2[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21941 Q=_zz__zz_decode_RS2_2[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21939 Q=_zz__zz_decode_RS2_2[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21937 Q=_zz__zz_decode_RS2_2[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21935 Q=_zz__zz_decode_RS2_2[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21933 Q=_zz__zz_decode_RS2_2[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21931 Q=_zz__zz_decode_RS2_2[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21929 Q=_zz__zz_decode_RS2_2[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21927 Q=_zz__zz_decode_RS2_2[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21925 Q=_zz__zz_decode_RS2_2[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21923 Q=_zz__zz_decode_RS2_2[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21921 Q=_zz__zz_decode_RS2_2[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21919 Q=_zz__zz_decode_RS2_2[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21917 Q=_zz__zz_decode_RS2_2[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21915 Q=_zz__zz_decode_RS2_2[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21913 Q=_zz__zz_decode_RS2_2[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21911 Q=_zz__zz_decode_RS2_2[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21909 Q=_zz__zz_decode_RS2_2[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21907 Q=_zz__zz_decode_RS2_2[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21905 Q=_zz__zz_decode_RS2_2[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21903 Q=_zz__zz_decode_RS2_2[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21901 Q=_zz__zz_decode_RS2_2[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21899 Q=_zz__zz_decode_RS2_2[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21897 Q=_zz__zz_decode_RS2_2[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21895 Q=_zz__zz_decode_RS2_2[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21893 Q=_zz__zz_decode_RS2_2[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21891 Q=_zz__zz_decode_RS2_2[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21889 Q=_zz__zz_decode_RS2_2[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21887 Q=_zz__zz_decode_RS2_2[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21885 Q=_zz__zz_decode_RS2_2[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21883 Q=_zz__zz_decode_RS2_2[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21881 Q=_zz__zz_decode_RS2_2[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21879 Q=_zz_writeBack_MulPlugin_result[32] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21877 Q=_zz_writeBack_MulPlugin_result[33] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21875 Q=_zz_writeBack_MulPlugin_result[34] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21873 Q=_zz_writeBack_MulPlugin_result[35] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21871 Q=_zz_writeBack_MulPlugin_result[36] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21869 Q=_zz_writeBack_MulPlugin_result[37] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21867 Q=_zz_writeBack_MulPlugin_result[38] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21865 Q=_zz_writeBack_MulPlugin_result[39] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21863 Q=_zz_writeBack_MulPlugin_result[40] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21861 Q=_zz_writeBack_MulPlugin_result[41] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21859 Q=_zz_writeBack_MulPlugin_result[42] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21857 Q=_zz_writeBack_MulPlugin_result[43] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21855 Q=_zz_writeBack_MulPlugin_result[44] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21853 Q=_zz_writeBack_MulPlugin_result[45] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21851 Q=_zz_writeBack_MulPlugin_result[46] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21849 Q=_zz_writeBack_MulPlugin_result[47] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21847 Q=_zz_writeBack_MulPlugin_result[48] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21845 Q=_zz_writeBack_MulPlugin_result[49] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21843 Q=_zz_writeBack_MulPlugin_result[50] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24515 Q=_zz_writeBack_MulPlugin_result[65] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24513 Q=execute_CsrPlugin_csr_768 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24511 Q=execute_CsrPlugin_csr_256 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24509 Q=execute_CsrPlugin_csr_384 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24507 Q=execute_CsrPlugin_csr_836 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24505 Q=execute_CsrPlugin_csr_772 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24503 Q=execute_CsrPlugin_csr_833 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24501 Q=execute_CsrPlugin_csr_834 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24499 Q=execute_CsrPlugin_csr_835 -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24497 Q=execute_arbitration_isValid R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24495 Q=memory_arbitration_isValid R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24493 Q=lastStageIsValid R=reset -.subckt dffr C=clk D=$true Q=IBusCachedPlugin_fetchPc_booted R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24491 Q=IBusCachedPlugin_fetchPc_inc R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24489 Q=IBusCachedPlugin_cache.io_cpu_fetch_isValid R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24487 Q=IBusCachedPlugin_cache.io_cpu_decode_isValid R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24485 Q=IBusCachedPlugin_injector_nextPcCalc_valids_0 R=reset -.subckt dffr C=clk D=$0\MmuPlugin_status_sum[0:0] Q=MmuPlugin_status_sum R=reset -.subckt dffr C=clk D=$0\MmuPlugin_status_mxr[0:0] Q=MmuPlugin_status_mxr R=reset -.subckt dffr C=clk D=$0\MmuPlugin_status_mprv[0:0] Q=MmuPlugin_status_mprv R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24483 Q=IBusCachedPlugin_iBusRsp_readyForError R=reset -.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_0_valid[0:0] Q=MmuPlugin_ports_1_cache_0_valid R=reset -.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_1_valid[0:0] Q=MmuPlugin_ports_1_cache_1_valid R=reset -.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_2_valid[0:0] Q=MmuPlugin_ports_1_cache_2_valid R=reset -.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_3_valid[0:0] Q=MmuPlugin_ports_1_cache_3_valid R=reset -.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_4_valid[0:0] Q=MmuPlugin_ports_1_cache_4_valid R=reset -.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_5_valid[0:0] Q=MmuPlugin_ports_1_cache_5_valid R=reset -.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[0] Q=MmuPlugin_ports_1_entryToReplace_value[0] R=reset -.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[1] Q=MmuPlugin_ports_1_entryToReplace_value[1] R=reset -.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[2] Q=MmuPlugin_ports_1_entryToReplace_value[2] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24481 Q=MmuPlugin_satp_mode R=reset -.subckt dffr C=clk D=MmuPlugin_dBusAccess_rsp_valid Q=MmuPlugin_shared_dBusRspStaged_valid R=reset -.subckt dffs C=clk D=$false Q=_zz_14 S=reset -.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset -.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[0] Q=memory_DivPlugin_div_counter_value[0] R=reset -.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[1] Q=memory_DivPlugin_div_counter_value[1] R=reset -.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[2] Q=memory_DivPlugin_div_counter_value[2] R=reset -.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[3] Q=memory_DivPlugin_div_counter_value[3] R=reset -.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[4] Q=memory_DivPlugin_div_counter_value[4] R=reset -.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[5] Q=memory_DivPlugin_div_counter_value[5] R=reset -.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset -.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset -.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset -.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21841 Q=MmuPlugin_shared_state_1[0] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21839 Q=MmuPlugin_shared_state_1[1] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24479 Q=MmuPlugin_shared_state_1[2] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24477 Q=CsrPlugin_mie_MEIE R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24475 Q=CsrPlugin_mie_MTIE R=reset -.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode[0:0] Q=CsrPlugin_exceptionPendings_0 R=reset -.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute[0:0] Q=CsrPlugin_exceptionPendings_1 R=reset -.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory[0:0] Q=CsrPlugin_exceptionPendings_2 R=reset -.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack[0:0] Q=CsrPlugin_exceptionPendings_3 R=reset -.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24473 Q=CsrPlugin_mie_MSIE R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24471 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24469 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset -.subckt dffr C=clk D=CsrPlugin_exception Q=CsrPlugin_hadException R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24467 Q=CsrPlugin_pipelineLiberator_pcValids_2 R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24465 Q=DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24463 Q=memory_to_writeBack_IS_DBUS_SHARING R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21837 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21835 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24461 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] R=reset -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21833 Q=DebugPlugin_busReadDataReg[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24891 Q=DebugPlugin_busReadDataReg[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21829 Q=dataCache_1.stageA_request_size[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24837 Q=dataCache_1.stageA_request_size[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24839 Q=dataCache_1.io_cpu_memory_isWrite -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24841 Q=dataCache_1.loader_error R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24843 Q=dataCache_1.io_cpu_execute_refilling R=reset -.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[0] Q=dataCache_1.loader_counter_value[0] R=reset -.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[1] Q=dataCache_1.loader_counter_value[1] R=reset -.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[2] Q=dataCache_1.loader_counter_value[2] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21827 Q=dataCache_1.stageB_flusher_counter[0] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21825 Q=dataCache_1.stageB_flusher_counter[1] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21823 Q=dataCache_1.stageB_flusher_counter[2] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21821 Q=dataCache_1.stageB_flusher_counter[3] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21819 Q=dataCache_1.stageB_flusher_counter[4] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21817 Q=dataCache_1.stageB_flusher_counter[5] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24845 Q=dataCache_1.stageB_flusher_counter[6] R=reset -.subckt dffs C=clk D=$abc$27210$flatten\dataCache_1.$0\stageB_flusher_start[0:0] Q=dataCache_1.stageB_flusher_start S=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24847 Q=dataCache_1.stageB_flusher_waitDone R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24849 Q=dataCache_1.memCmdSent R=reset -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24797 Q=dataCache_1.stageB_unaligned -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24795 Q=dataCache_1.stageB_waysHit -.subckt dff C=clk D=dataCache_1.io_cpu_execute_refilling Q=dataCache_1.loader_valid_regNext -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21815 Q=dataCache_1.stageA_mask[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21813 Q=dataCache_1.stageA_mask[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21811 Q=dataCache_1.stageA_mask[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24835 Q=dataCache_1.stageA_mask[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24833 Q=dataCache_1.stage0_dataColisions_regNextWhen -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24831 Q=dBus_cmd_payload_wr -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21809 Q=dataCache_1.stageB_request_size[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24829 Q=dataCache_1.stageB_request_size[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24825 Q=dBus_cmd_payload_uncached -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21807 Q=dataCache_1.stageB_mmuRsp_physicalAddress[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21805 Q=dataCache_1.stageB_mmuRsp_physicalAddress[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21803 Q=dataCache_1.stageB_mmuRsp_physicalAddress[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21801 Q=dataCache_1.stageB_mmuRsp_physicalAddress[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21799 Q=dataCache_1.stageB_mmuRsp_physicalAddress[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21797 Q=dBus_cmd_payload_address[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21795 Q=dBus_cmd_payload_address[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21793 Q=dBus_cmd_payload_address[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21791 Q=dBus_cmd_payload_address[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21789 Q=dBus_cmd_payload_address[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21787 Q=dBus_cmd_payload_address[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21785 Q=dBus_cmd_payload_address[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21783 Q=dBus_cmd_payload_address[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21781 Q=dBus_cmd_payload_address[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21779 Q=dBus_cmd_payload_address[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21777 Q=dBus_cmd_payload_address[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21775 Q=dBus_cmd_payload_address[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21773 Q=dBus_cmd_payload_address[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21771 Q=dBus_cmd_payload_address[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21769 Q=dBus_cmd_payload_address[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21767 Q=dBus_cmd_payload_address[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21765 Q=dBus_cmd_payload_address[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21763 Q=dBus_cmd_payload_address[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21761 Q=dBus_cmd_payload_address[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21759 Q=dBus_cmd_payload_address[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21757 Q=dBus_cmd_payload_address[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21755 Q=dBus_cmd_payload_address[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21753 Q=dBus_cmd_payload_address[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21751 Q=dBus_cmd_payload_address[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21749 Q=dBus_cmd_payload_address[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21747 Q=dBus_cmd_payload_address[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24827 Q=dBus_cmd_payload_address[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24819 Q=dataCache_1.stageB_mmuRsp_allowRead -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24815 Q=dataCache_1.stageB_mmuRsp_allowWrite -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24811 Q=dataCache_1.stageB_mmuRsp_exception -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24807 Q=dataCache_1.stageB_mmuRsp_refilling -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24821 Q=dataCache_1.stageB_mmuRsp_isPaging -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24803 Q=dataCache_1.stageB_tagsReadRsp_0_error -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21745 Q=dBus_cmd_payload_mask[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21743 Q=dBus_cmd_payload_mask[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21741 Q=dBus_cmd_payload_mask[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24793 Q=dBus_cmd_payload_mask[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21739 Q=dataCache_1.stageB_dataMux[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21737 Q=dataCache_1.stageB_dataMux[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21735 Q=dataCache_1.stageB_dataMux[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21733 Q=dataCache_1.stageB_dataMux[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21731 Q=dataCache_1.stageB_dataMux[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21729 Q=dataCache_1.stageB_dataMux[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21727 Q=dataCache_1.stageB_dataMux[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21725 Q=dataCache_1.stageB_dataMux[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21723 Q=dataCache_1.stageB_dataMux[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21721 Q=dataCache_1.stageB_dataMux[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21719 Q=dataCache_1.stageB_dataMux[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21717 Q=dataCache_1.stageB_dataMux[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21715 Q=dataCache_1.stageB_dataMux[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21713 Q=dataCache_1.stageB_dataMux[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21711 Q=dataCache_1.stageB_dataMux[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21709 Q=dataCache_1.stageB_dataMux[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21707 Q=dataCache_1.stageB_dataMux[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21705 Q=dataCache_1.stageB_dataMux[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21703 Q=dataCache_1.stageB_dataMux[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21701 Q=dataCache_1.stageB_dataMux[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21699 Q=dataCache_1.stageB_dataMux[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21697 Q=dataCache_1.stageB_dataMux[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21695 Q=dataCache_1.stageB_dataMux[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21693 Q=dataCache_1.stageB_dataMux[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21691 Q=dataCache_1.stageB_dataMux[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21689 Q=dataCache_1.stageB_dataMux[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21687 Q=dataCache_1.stageB_dataMux[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21685 Q=dataCache_1.stageB_dataMux[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21683 Q=dataCache_1.stageB_dataMux[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21681 Q=dataCache_1.stageB_dataMux[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21679 Q=dataCache_1.stageB_dataMux[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24801 Q=dataCache_1.stageB_dataMux[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24799 Q=dataCache_1.stageB_dataColisions -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24899 Q=when_MmuPlugin_l281_1 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24459 Q=DebugPlugin_busReadDataReg[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24457 Q=DebugPlugin_busReadDataReg[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24455 Q=DebugPlugin_busReadDataReg[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24453 Q=debug_bus_rsp_data[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24451 Q=debug_bus_rsp_data[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24449 Q=debug_bus_rsp_data[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24447 Q=debug_bus_rsp_data[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24445 Q=debug_bus_rsp_data[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24443 Q=debug_bus_rsp_data[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24441 Q=debug_bus_rsp_data[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24439 Q=debug_bus_rsp_data[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24437 Q=debug_bus_rsp_data[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24435 Q=debug_bus_rsp_data[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24433 Q=debug_bus_rsp_data[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24431 Q=debug_bus_rsp_data[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24429 Q=debug_bus_rsp_data[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24427 Q=debug_bus_rsp_data[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24425 Q=debug_bus_rsp_data[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24423 Q=debug_bus_rsp_data[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24421 Q=debug_bus_rsp_data[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24419 Q=debug_bus_rsp_data[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24417 Q=debug_bus_rsp_data[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24415 Q=debug_bus_rsp_data[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24413 Q=debug_bus_rsp_data[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24411 Q=debug_bus_rsp_data[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24409 Q=debug_bus_rsp_data[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24407 Q=debug_bus_rsp_data[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24405 Q=debug_bus_rsp_data[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24403 Q=debug_bus_rsp_data[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24893 Q=debug_bus_rsp_data[31] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24401 Q=_zz_execute_to_memory_PC[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24399 Q=_zz_execute_to_memory_PC[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24397 Q=_zz_execute_to_memory_PC[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24395 Q=_zz_execute_to_memory_PC[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24393 Q=_zz_execute_to_memory_PC[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24391 Q=_zz_execute_to_memory_PC[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24389 Q=_zz_execute_to_memory_PC[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24387 Q=_zz_execute_to_memory_PC[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24385 Q=_zz_execute_to_memory_PC[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24383 Q=_zz_execute_to_memory_PC[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24381 Q=_zz_execute_to_memory_PC[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24379 Q=_zz_execute_to_memory_PC[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24377 Q=_zz_execute_to_memory_PC[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24375 Q=_zz_execute_to_memory_PC[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24373 Q=_zz_execute_to_memory_PC[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24371 Q=_zz_execute_to_memory_PC[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24369 Q=_zz_execute_to_memory_PC[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24367 Q=_zz_execute_to_memory_PC[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24365 Q=_zz_execute_to_memory_PC[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24363 Q=_zz_execute_to_memory_PC[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24361 Q=_zz_execute_to_memory_PC[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24359 Q=_zz_execute_to_memory_PC[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24357 Q=_zz_execute_to_memory_PC[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24355 Q=_zz_execute_to_memory_PC[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24353 Q=_zz_execute_to_memory_PC[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24351 Q=_zz_execute_to_memory_PC[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24349 Q=_zz_execute_to_memory_PC[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24347 Q=_zz_execute_to_memory_PC[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24345 Q=_zz_execute_to_memory_PC[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24885 Q=_zz_execute_to_memory_PC[31] -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24343 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[0] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24341 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[1] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24851 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[2] R=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24853 Q=IBusCachedPlugin_cache.lineLoader_cmdSent R=reset -.subckt dffs C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24855 Q=IBusCachedPlugin_cache.lineLoader_flushPending S=reset -.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24857 Q=IBusCachedPlugin_cache.lineLoader_valid R=reset -.subckt dffr C=clk D=$abc$27210$flatten\IBusCachedPlugin_cache.$0\lineLoader_hadError[0:0] Q=IBusCachedPlugin_cache.lineLoader_hadError R=reset -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24339 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24337 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24335 Q=_zz__zz_decode_IS_CSR_85 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24333 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24331 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24329 Q=_zz__zz_decode_IS_CSR_41 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24327 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24325 Q=_zz_IBusCachedPlugin_predictionJumpInterface_payload_6 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24323 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24321 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24319 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24317 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24315 Q=_zz__zz_decode_IS_CSR_21 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24313 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24311 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24309 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24307 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24305 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24303 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24301 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24299 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24297 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24295 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24293 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24291 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24289 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24287 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24285 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24283 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24281 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24279 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24859 Q=_zz_6 -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24277 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24275 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24273 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24271 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24269 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24267 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24265 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24263 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24261 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24259 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24257 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24255 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24253 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24251 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24249 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24247 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24245 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24243 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24241 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24861 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24863 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_error -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24865 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24239 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24237 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] -.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24905 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] -.subckt mult24x20 A[23]=execute_RS1[16] A[22]=execute_RS1[17] A[21]=execute_RS1[18] A[20]=execute_RS1[19] A[19]=execute_RS1[20] A[18]=execute_RS1[21] A[17]=execute_RS1[22] A[16]=execute_RS1[23] A[15]=execute_RS1[24] A[14]=execute_RS1[25] A[13]=execute_RS1[26] A[12]=execute_RS1[27] A[11]=execute_RS1[28] A[10]=execute_RS1[29] A[9]=execute_RS1[30] A[8]=execute_RS1[31] A[7]=execute_MulPlugin_aHigh[16] A[6]=execute_MulPlugin_aHigh[16] A[5]=execute_MulPlugin_aHigh[16] A[4]=execute_MulPlugin_aHigh[16] A[3]=execute_MulPlugin_aHigh[16] A[2]=execute_MulPlugin_aHigh[16] A[1]=execute_MulPlugin_aHigh[16] A[0]=execute_MulPlugin_aHigh[16] B[19]=execute_RS2[16] B[18]=execute_RS2[17] B[17]=execute_RS2[18] B[16]=execute_RS2[19] B[15]=execute_RS2[20] B[14]=execute_RS2[21] B[13]=execute_RS2[22] B[12]=execute_RS2[23] B[11]=execute_RS2[24] B[10]=execute_RS2[25] B[9]=execute_RS2[26] B[8]=execute_RS2[27] B[7]=execute_RS2[28] B[6]=execute_RS2[29] B[5]=execute_RS2[30] B[4]=execute_RS2[31] B[3]=execute_MulPlugin_bHigh[16] B[2]=execute_MulPlugin_bHigh[16] B[1]=execute_MulPlugin_bHigh[16] B[0]=execute_MulPlugin_bHigh[16] Y[43]=execute_MUL_HH[0] Y[42]=execute_MUL_HH[1] Y[41]=execute_MUL_HH[2] Y[40]=execute_MUL_HH[3] Y[39]=execute_MUL_HH[4] Y[38]=execute_MUL_HH[5] Y[37]=execute_MUL_HH[6] Y[36]=execute_MUL_HH[7] Y[35]=execute_MUL_HH[8] Y[34]=execute_MUL_HH[9] Y[33]=execute_MUL_HH[10] Y[32]=execute_MUL_HH[11] Y[31]=execute_MUL_HH[12] Y[30]=execute_MUL_HH[13] Y[29]=execute_MUL_HH[14] Y[28]=execute_MUL_HH[15] Y[27]=execute_MUL_HH[16] Y[26]=execute_MUL_HH[17] Y[25]=execute_MUL_HH[18] Y[24]=execute_MUL_HH[19] Y[23]=execute_MUL_HH[20] Y[22]=execute_MUL_HH[21] Y[21]=execute_MUL_HH[22] Y[20]=execute_MUL_HH[23] Y[19]=execute_MUL_HH[24] Y[18]=execute_MUL_HH[25] Y[17]=execute_MUL_HH[26] Y[16]=execute_MUL_HH[27] Y[15]=execute_MUL_HH[28] Y[14]=execute_MUL_HH[29] Y[13]=execute_MUL_HH[30] Y[12]=execute_MUL_HH[31] Y[11]=execute_MUL_HH[32] Y[10]=execute_MUL_HH[33] Y[9]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[9] Y[8]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[8] Y[7]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[7] Y[6]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[6] Y[5]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[5] Y[4]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[4] Y[3]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[3] Y[2]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[2] Y[1]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[1] Y[0]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[0] -.subckt mult24x20 A[23]=execute_RS1[16] A[22]=execute_RS1[17] A[21]=execute_RS1[18] A[20]=execute_RS1[19] A[19]=execute_RS1[20] A[18]=execute_RS1[21] A[17]=execute_RS1[22] A[16]=execute_RS1[23] A[15]=execute_RS1[24] A[14]=execute_RS1[25] A[13]=execute_RS1[26] A[12]=execute_RS1[27] A[11]=execute_RS1[28] A[10]=execute_RS1[29] A[9]=execute_RS1[30] A[8]=execute_RS1[31] A[7]=execute_MulPlugin_aHigh[16] A[6]=execute_MulPlugin_aHigh[16] A[5]=execute_MulPlugin_aHigh[16] A[4]=execute_MulPlugin_aHigh[16] A[3]=execute_MulPlugin_aHigh[16] A[2]=execute_MulPlugin_aHigh[16] A[1]=execute_MulPlugin_aHigh[16] A[0]=execute_MulPlugin_aHigh[16] B[19]=execute_RS2[0] B[18]=execute_RS2[1] B[17]=execute_RS2[2] B[16]=execute_RS2[3] B[15]=execute_RS2[4] B[14]=execute_RS2[5] B[13]=execute_RS2[6] B[12]=execute_RS2[7] B[11]=execute_RS2[8] B[10]=execute_RS2[9] B[9]=execute_RS2[10] B[8]=execute_RS2[11] B[7]=execute_RS2[12] B[6]=execute_RS2[13] B[5]=execute_RS2[14] B[4]=execute_RS2[15] B[3]=$false B[2]=$false B[1]=$false B[0]=$false Y[43]=execute_MUL_HL[0] Y[42]=execute_MUL_HL[1] Y[41]=execute_MUL_HL[2] Y[40]=execute_MUL_HL[3] Y[39]=execute_MUL_HL[4] Y[38]=execute_MUL_HL[5] Y[37]=execute_MUL_HL[6] Y[36]=execute_MUL_HL[7] Y[35]=execute_MUL_HL[8] Y[34]=execute_MUL_HL[9] Y[33]=execute_MUL_HL[10] Y[32]=execute_MUL_HL[11] Y[31]=execute_MUL_HL[12] Y[30]=execute_MUL_HL[13] Y[29]=execute_MUL_HL[14] Y[28]=execute_MUL_HL[15] Y[27]=execute_MUL_HL[16] Y[26]=execute_MUL_HL[17] Y[25]=execute_MUL_HL[18] Y[24]=execute_MUL_HL[19] Y[23]=execute_MUL_HL[20] Y[22]=execute_MUL_HL[21] Y[21]=execute_MUL_HL[22] Y[20]=execute_MUL_HL[23] Y[19]=execute_MUL_HL[24] Y[18]=execute_MUL_HL[25] Y[17]=execute_MUL_HL[26] Y[16]=execute_MUL_HL[27] Y[15]=execute_MUL_HL[28] Y[14]=execute_MUL_HL[29] Y[13]=execute_MUL_HL[30] Y[12]=execute_MUL_HL[31] Y[11]=execute_MUL_HL[32] Y[10]=execute_MUL_HL[33] Y[9]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[9] Y[8]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[8] Y[7]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[7] Y[6]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[6] Y[5]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[5] Y[4]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[4] Y[3]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[3] Y[2]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[2] Y[1]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[1] Y[0]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[0] -.subckt mult24x20 A[23]=execute_RS1[0] A[22]=execute_RS1[1] A[21]=execute_RS1[2] A[20]=execute_RS1[3] A[19]=execute_RS1[4] A[18]=execute_RS1[5] A[17]=execute_RS1[6] A[16]=execute_RS1[7] A[15]=execute_RS1[8] A[14]=execute_RS1[9] A[13]=execute_RS1[10] A[12]=execute_RS1[11] A[11]=execute_RS1[12] A[10]=execute_RS1[13] A[9]=execute_RS1[14] A[8]=execute_RS1[15] A[7]=$false A[6]=$false A[5]=$false A[4]=$false A[3]=$false A[2]=$false A[1]=$false A[0]=$false B[19]=execute_RS2[16] B[18]=execute_RS2[17] B[17]=execute_RS2[18] B[16]=execute_RS2[19] B[15]=execute_RS2[20] B[14]=execute_RS2[21] B[13]=execute_RS2[22] B[12]=execute_RS2[23] B[11]=execute_RS2[24] B[10]=execute_RS2[25] B[9]=execute_RS2[26] B[8]=execute_RS2[27] B[7]=execute_RS2[28] B[6]=execute_RS2[29] B[5]=execute_RS2[30] B[4]=execute_RS2[31] B[3]=execute_MulPlugin_bHigh[16] B[2]=execute_MulPlugin_bHigh[16] B[1]=execute_MulPlugin_bHigh[16] B[0]=execute_MulPlugin_bHigh[16] Y[43]=execute_MUL_LH[0] Y[42]=execute_MUL_LH[1] Y[41]=execute_MUL_LH[2] Y[40]=execute_MUL_LH[3] Y[39]=execute_MUL_LH[4] Y[38]=execute_MUL_LH[5] Y[37]=execute_MUL_LH[6] Y[36]=execute_MUL_LH[7] Y[35]=execute_MUL_LH[8] Y[34]=execute_MUL_LH[9] Y[33]=execute_MUL_LH[10] Y[32]=execute_MUL_LH[11] Y[31]=execute_MUL_LH[12] Y[30]=execute_MUL_LH[13] Y[29]=execute_MUL_LH[14] Y[28]=execute_MUL_LH[15] Y[27]=execute_MUL_LH[16] Y[26]=execute_MUL_LH[17] Y[25]=execute_MUL_LH[18] Y[24]=execute_MUL_LH[19] Y[23]=execute_MUL_LH[20] Y[22]=execute_MUL_LH[21] Y[21]=execute_MUL_LH[22] Y[20]=execute_MUL_LH[23] Y[19]=execute_MUL_LH[24] Y[18]=execute_MUL_LH[25] Y[17]=execute_MUL_LH[26] Y[16]=execute_MUL_LH[27] Y[15]=execute_MUL_LH[28] Y[14]=execute_MUL_LH[29] Y[13]=execute_MUL_LH[30] Y[12]=execute_MUL_LH[31] Y[11]=execute_MUL_LH[32] Y[10]=execute_MUL_LH[33] Y[9]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[9] Y[8]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[8] Y[7]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[7] Y[6]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[6] Y[5]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[5] Y[4]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[4] Y[3]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[3] Y[2]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[2] Y[1]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[1] Y[0]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[0] -.subckt mult24x20 A[23]=execute_RS1[0] A[22]=execute_RS1[1] A[21]=execute_RS1[2] A[20]=execute_RS1[3] A[19]=execute_RS1[4] A[18]=execute_RS1[5] A[17]=execute_RS1[6] A[16]=execute_RS1[7] A[15]=execute_RS1[8] A[14]=execute_RS1[9] A[13]=execute_RS1[10] A[12]=execute_RS1[11] A[11]=execute_RS1[12] A[10]=execute_RS1[13] A[9]=execute_RS1[14] A[8]=execute_RS1[15] A[7]=$false A[6]=$false A[5]=$false A[4]=$false A[3]=$false A[2]=$false A[1]=$false A[0]=$false B[19]=execute_RS2[0] B[18]=execute_RS2[1] B[17]=execute_RS2[2] B[16]=execute_RS2[3] B[15]=execute_RS2[4] B[14]=execute_RS2[5] B[13]=execute_RS2[6] B[12]=execute_RS2[7] B[11]=execute_RS2[8] B[10]=execute_RS2[9] B[9]=execute_RS2[10] B[8]=execute_RS2[11] B[7]=execute_RS2[12] B[6]=execute_RS2[13] B[5]=execute_RS2[14] B[4]=execute_RS2[15] B[3]=$false B[2]=$false B[1]=$false B[0]=$false Y[43]=execute_MUL_LL[0] Y[42]=execute_MUL_LL[1] Y[41]=execute_MUL_LL[2] Y[40]=execute_MUL_LL[3] Y[39]=execute_MUL_LL[4] Y[38]=execute_MUL_LL[5] Y[37]=execute_MUL_LL[6] Y[36]=execute_MUL_LL[7] Y[35]=execute_MUL_LL[8] Y[34]=execute_MUL_LL[9] Y[33]=execute_MUL_LL[10] Y[32]=execute_MUL_LL[11] Y[31]=execute_MUL_LL[12] Y[30]=execute_MUL_LL[13] Y[29]=execute_MUL_LL[14] Y[28]=execute_MUL_LL[15] Y[27]=execute_MUL_LL[16] Y[26]=execute_MUL_LL[17] Y[25]=execute_MUL_LL[18] Y[24]=execute_MUL_LL[19] Y[23]=execute_MUL_LL[20] Y[22]=execute_MUL_LL[21] Y[21]=execute_MUL_LL[22] Y[20]=execute_MUL_LL[23] Y[19]=execute_MUL_LL[24] Y[18]=execute_MUL_LL[25] Y[17]=execute_MUL_LL[26] Y[16]=execute_MUL_LL[27] Y[15]=execute_MUL_LL[28] Y[14]=execute_MUL_LL[29] Y[13]=execute_MUL_LL[30] Y[12]=execute_MUL_LL[31] Y[11]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[11] Y[10]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[10] Y[9]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[9] Y[8]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[8] Y[7]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[7] Y[6]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[6] Y[5]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[5] Y[4]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[4] Y[3]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[3] Y[2]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[2] Y[1]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[1] Y[0]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[0] -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[0] data_i[7]=iBus_rsp_payload_data[1] data_i[6]=iBus_rsp_payload_data[2] data_i[5]=iBus_rsp_payload_data[3] data_i[4]=iBus_rsp_payload_data[4] data_i[3]=iBus_rsp_payload_data[5] data_i[2]=iBus_rsp_payload_data[6] data_i[1]=iBus_rsp_payload_data[7] data_i[0]=iBus_rsp_payload_data[8] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[0] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[1] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[2] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[3] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[4] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[5] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[6] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[7] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[8] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[9] data_i[7]=iBus_rsp_payload_data[10] data_i[6]=iBus_rsp_payload_data[11] data_i[5]=iBus_rsp_payload_data[12] data_i[4]=iBus_rsp_payload_data[13] data_i[3]=iBus_rsp_payload_data[14] data_i[2]=iBus_rsp_payload_data[15] data_i[1]=iBus_rsp_payload_data[16] data_i[0]=iBus_rsp_payload_data[17] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[9] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[10] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[11] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[12] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[13] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[14] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[15] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[16] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[17] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[18] data_i[7]=iBus_rsp_payload_data[19] data_i[6]=iBus_rsp_payload_data[20] data_i[5]=iBus_rsp_payload_data[21] data_i[4]=iBus_rsp_payload_data[22] data_i[3]=iBus_rsp_payload_data[23] data_i[2]=iBus_rsp_payload_data[24] data_i[1]=iBus_rsp_payload_data[25] data_i[0]=iBus_rsp_payload_data[26] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[18] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[19] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[20] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[21] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[22] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[23] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[24] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[25] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[26] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[27] data_i[7]=iBus_rsp_payload_data[28] data_i[6]=iBus_rsp_payload_data[29] data_i[5]=iBus_rsp_payload_data[30] data_i[4]=iBus_rsp_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[27] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[28] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[29] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[30] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6842[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6842[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6842[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6842[35] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid data_i[34]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_error data_i[33]=iBus_cmd_payload_address[12] data_i[32]=iBus_cmd_payload_address[13] data_i[31]=iBus_cmd_payload_address[14] data_i[30]=iBus_cmd_payload_address[15] data_i[29]=iBus_cmd_payload_address[16] data_i[28]=iBus_cmd_payload_address[17] data_i[27]=iBus_cmd_payload_address[18] data_i[26]=iBus_cmd_payload_address[19] data_i[25]=iBus_cmd_payload_address[20] data_i[24]=iBus_cmd_payload_address[21] data_i[23]=iBus_cmd_payload_address[22] data_i[22]=iBus_cmd_payload_address[23] data_i[21]=iBus_cmd_payload_address[24] data_i[20]=iBus_cmd_payload_address[25] data_i[19]=iBus_cmd_payload_address[26] data_i[18]=iBus_cmd_payload_address[27] data_i[17]=iBus_cmd_payload_address[28] data_i[16]=iBus_cmd_payload_address[29] data_i[15]=iBus_cmd_payload_address[30] data_i[14]=iBus_cmd_payload_address[31] data_i[13]=$undef data_i[12]=$undef data_i[11]=$undef data_i[10]=$undef data_i[9]=$undef data_i[8]=$undef data_i[7]=$undef data_i[6]=$undef data_i[5]=$undef data_i[4]=$undef data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] q_o[34]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] q_o[33]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] q_o[32]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] q_o[31]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] q_o[30]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] q_o[29]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] q_o[28]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] q_o[27]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] q_o[26]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] q_o[25]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] q_o[24]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] q_o[23]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] q_o[22]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] q_o[21]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] q_o[20]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] q_o[19]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] q_o[18]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] q_o[17]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] q_o[16]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] q_o[15]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] q_o[14]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] q_o[13]=$auto$memory_bram.cc:844:replace_memory$6847[22] q_o[12]=$auto$memory_bram.cc:844:replace_memory$6847[23] q_o[11]=$auto$memory_bram.cc:844:replace_memory$6847[24] q_o[10]=$auto$memory_bram.cc:844:replace_memory$6847[25] q_o[9]=$auto$memory_bram.cc:844:replace_memory$6847[26] q_o[8]=$auto$memory_bram.cc:844:replace_memory$6847[27] q_o[7]=$auto$memory_bram.cc:844:replace_memory$6847[28] q_o[6]=$auto$memory_bram.cc:844:replace_memory$6847[29] q_o[5]=$auto$memory_bram.cc:844:replace_memory$6847[30] q_o[4]=$auto$memory_bram.cc:844:replace_memory$6847[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6847[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6847[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6847[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6847[35] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] raddr_i[0]=$false rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[7]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[0] waddr_i[6]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[1] waddr_i[5]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[2] waddr_i[4]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[3] waddr_i[3]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[4] waddr_i[2]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[5] waddr_i[1]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[6] waddr_i[0]=$false wclk_i=clk wen_ni=IBusCachedPlugin_cache._zz_2 -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6849[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6849[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6849[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6849[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6850[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6850[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6850[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6850[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 -.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=_zz__zz_3_port[0] data_i[2]=_zz__zz_3_port[1] data_i[1]=$undef data_i[0]=$undef q_o[3]=_zz__zz_3_port1[0] q_o[2]=_zz__zz_3_port1[1] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6853[2] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6853[3] raddr_i[10]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] raddr_i[0]=$false rclk_i=clk ren_ni=_zz_decode_PREDICTION_CONTEXT_line_history_1 waddr_i[10]=_zz_decode_PREDICTION_CONTEXT_hazard_1[0] waddr_i[9]=_zz_decode_PREDICTION_CONTEXT_hazard_1[1] waddr_i[8]=_zz_decode_PREDICTION_CONTEXT_hazard_1[2] waddr_i[7]=_zz_decode_PREDICTION_CONTEXT_hazard_1[3] waddr_i[6]=_zz_decode_PREDICTION_CONTEXT_hazard_1[4] waddr_i[5]=_zz_decode_PREDICTION_CONTEXT_hazard_1[5] waddr_i[4]=_zz_decode_PREDICTION_CONTEXT_hazard_1[6] waddr_i[3]=_zz_decode_PREDICTION_CONTEXT_hazard_1[7] waddr_i[2]=_zz_decode_PREDICTION_CONTEXT_hazard_1[8] waddr_i[1]=_zz_decode_PREDICTION_CONTEXT_hazard_1[9] waddr_i[0]=$false wclk_i=clk wen_ni=_zz_2 -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[0] data_i[7]=dataCache_1.dataWriteCmd_payload_data[1] data_i[6]=dataCache_1.dataWriteCmd_payload_data[2] data_i[5]=dataCache_1.dataWriteCmd_payload_data[3] data_i[4]=dataCache_1.dataWriteCmd_payload_data[4] data_i[3]=dataCache_1.dataWriteCmd_payload_data[5] data_i[2]=dataCache_1.dataWriteCmd_payload_data[6] data_i[1]=dataCache_1.dataWriteCmd_payload_data[7] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[0] q_o[7]=dataCache_1._zz_ways_0_data_port0[1] q_o[6]=dataCache_1._zz_ways_0_data_port0[2] q_o[5]=dataCache_1._zz_ways_0_data_port0[3] q_o[4]=dataCache_1._zz_ways_0_data_port0[4] q_o[3]=dataCache_1._zz_ways_0_data_port0[5] q_o[2]=dataCache_1._zz_ways_0_data_port0[6] q_o[1]=dataCache_1._zz_ways_0_data_port0[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6855[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol0$./benchmark/VexRiscv.v:6878$1192_EN[7:0]$1214[7] -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[8] data_i[7]=dataCache_1.dataWriteCmd_payload_data[9] data_i[6]=dataCache_1.dataWriteCmd_payload_data[10] data_i[5]=dataCache_1.dataWriteCmd_payload_data[11] data_i[4]=dataCache_1.dataWriteCmd_payload_data[12] data_i[3]=dataCache_1.dataWriteCmd_payload_data[13] data_i[2]=dataCache_1.dataWriteCmd_payload_data[14] data_i[1]=dataCache_1.dataWriteCmd_payload_data[15] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[8] q_o[7]=dataCache_1._zz_ways_0_data_port0[9] q_o[6]=dataCache_1._zz_ways_0_data_port0[10] q_o[5]=dataCache_1._zz_ways_0_data_port0[11] q_o[4]=dataCache_1._zz_ways_0_data_port0[12] q_o[3]=dataCache_1._zz_ways_0_data_port0[13] q_o[2]=dataCache_1._zz_ways_0_data_port0[14] q_o[1]=dataCache_1._zz_ways_0_data_port0[15] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6857[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol1$./benchmark/VexRiscv.v:6881$1193_EN[7:0]$1217[7] -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[16] data_i[7]=dataCache_1.dataWriteCmd_payload_data[17] data_i[6]=dataCache_1.dataWriteCmd_payload_data[18] data_i[5]=dataCache_1.dataWriteCmd_payload_data[19] data_i[4]=dataCache_1.dataWriteCmd_payload_data[20] data_i[3]=dataCache_1.dataWriteCmd_payload_data[21] data_i[2]=dataCache_1.dataWriteCmd_payload_data[22] data_i[1]=dataCache_1.dataWriteCmd_payload_data[23] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[16] q_o[7]=dataCache_1._zz_ways_0_data_port0[17] q_o[6]=dataCache_1._zz_ways_0_data_port0[18] q_o[5]=dataCache_1._zz_ways_0_data_port0[19] q_o[4]=dataCache_1._zz_ways_0_data_port0[20] q_o[3]=dataCache_1._zz_ways_0_data_port0[21] q_o[2]=dataCache_1._zz_ways_0_data_port0[22] q_o[1]=dataCache_1._zz_ways_0_data_port0[23] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6859[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol2$./benchmark/VexRiscv.v:6884$1194_EN[7:0]$1220[7] -.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[24] data_i[7]=dataCache_1.dataWriteCmd_payload_data[25] data_i[6]=dataCache_1.dataWriteCmd_payload_data[26] data_i[5]=dataCache_1.dataWriteCmd_payload_data[27] data_i[4]=dataCache_1.dataWriteCmd_payload_data[28] data_i[3]=dataCache_1.dataWriteCmd_payload_data[29] data_i[2]=dataCache_1.dataWriteCmd_payload_data[30] data_i[1]=dataCache_1.dataWriteCmd_payload_data[31] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[24] q_o[7]=dataCache_1._zz_ways_0_data_port0[25] q_o[6]=dataCache_1._zz_ways_0_data_port0[26] q_o[5]=dataCache_1._zz_ways_0_data_port0[27] q_o[4]=dataCache_1._zz_ways_0_data_port0[28] q_o[3]=dataCache_1._zz_ways_0_data_port0[29] q_o[2]=dataCache_1._zz_ways_0_data_port0[30] q_o[1]=dataCache_1._zz_ways_0_data_port0[31] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6861[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol3$./benchmark/VexRiscv.v:6887$1195_EN[7:0]$1223[7] -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=dataCache_1.loader_counter_willOverflow data_i[34]=dataCache_1.tagsWriteCmd_payload_data_error data_i[33]=dBus_cmd_payload_address[12] data_i[32]=dBus_cmd_payload_address[13] data_i[31]=dBus_cmd_payload_address[14] data_i[30]=dBus_cmd_payload_address[15] data_i[29]=dBus_cmd_payload_address[16] data_i[28]=dBus_cmd_payload_address[17] data_i[27]=dBus_cmd_payload_address[18] data_i[26]=dBus_cmd_payload_address[19] data_i[25]=dBus_cmd_payload_address[20] data_i[24]=dBus_cmd_payload_address[21] data_i[23]=dBus_cmd_payload_address[22] data_i[22]=dBus_cmd_payload_address[23] data_i[21]=dBus_cmd_payload_address[24] data_i[20]=dBus_cmd_payload_address[25] data_i[19]=dBus_cmd_payload_address[26] data_i[18]=dBus_cmd_payload_address[27] data_i[17]=dBus_cmd_payload_address[28] data_i[16]=dBus_cmd_payload_address[29] data_i[15]=dBus_cmd_payload_address[30] data_i[14]=dBus_cmd_payload_address[31] data_i[13]=$undef data_i[12]=$undef data_i[11]=$undef data_i[10]=$undef data_i[9]=$undef data_i[8]=$undef data_i[7]=$undef data_i[6]=$undef data_i[5]=$undef data_i[4]=$undef data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[0] q_o[34]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[1] q_o[33]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[2] q_o[32]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[3] q_o[31]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] q_o[30]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[5] q_o[29]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[6] q_o[28]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[7] q_o[27]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[8] q_o[26]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[9] q_o[25]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[10] q_o[24]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[11] q_o[23]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] q_o[22]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[13] q_o[21]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[14] q_o[20]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[15] q_o[19]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[16] q_o[18]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[17] q_o[17]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] q_o[16]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[19] q_o[15]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] q_o[14]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[21] q_o[13]=$auto$memory_bram.cc:844:replace_memory$6863[22] q_o[12]=$auto$memory_bram.cc:844:replace_memory$6863[23] q_o[11]=$auto$memory_bram.cc:844:replace_memory$6863[24] q_o[10]=$auto$memory_bram.cc:844:replace_memory$6863[25] q_o[9]=$auto$memory_bram.cc:844:replace_memory$6863[26] q_o[8]=$auto$memory_bram.cc:844:replace_memory$6863[27] q_o[7]=$auto$memory_bram.cc:844:replace_memory$6863[28] q_o[6]=$auto$memory_bram.cc:844:replace_memory$6863[29] q_o[5]=$auto$memory_bram.cc:844:replace_memory$6863[30] q_o[4]=$auto$memory_bram.cc:844:replace_memory$6863[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6863[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6863[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6863[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6863[35] raddr_i[7]=dataCache_1.dataReadCmd_payload[3] raddr_i[6]=dataCache_1.dataReadCmd_payload[4] raddr_i[5]=dataCache_1.dataReadCmd_payload[5] raddr_i[4]=dataCache_1.dataReadCmd_payload[6] raddr_i[3]=dataCache_1.dataReadCmd_payload[7] raddr_i[2]=dataCache_1.dataReadCmd_payload[8] raddr_i[1]=dataCache_1.dataReadCmd_payload[9] raddr_i[0]=$false rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[7]=dataCache_1.tagsWriteCmd_payload_address[0] waddr_i[6]=dataCache_1.tagsWriteCmd_payload_address[1] waddr_i[5]=dataCache_1.tagsWriteCmd_payload_address[2] waddr_i[4]=dataCache_1.tagsWriteCmd_payload_address[3] waddr_i[3]=dataCache_1.tagsWriteCmd_payload_address[4] waddr_i[2]=dataCache_1.tagsWriteCmd_payload_address[5] waddr_i[1]=dataCache_1.tagsWriteCmd_payload_address[6] waddr_i[0]=$false wclk_i=clk wen_ni=dataCache_1._zz_2 -.names $false BranchPlugin_branchExceptionPort_payload_badAddr[0] -1 1 -.names $true CsrPlugin_interrupt_code[0] -1 1 -.names $true CsrPlugin_interrupt_code[1] -1 1 -.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[1] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[0] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[1] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[2] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[3] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[4] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[5] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[6] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[7] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[8] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[9] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[10] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[11] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[12] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[13] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[14] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[15] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[16] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[17] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[18] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[19] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[20] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[21] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[0] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[1] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[2] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[3] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[4] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[5] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[6] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[7] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[8] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[9] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[10] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[11] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[12] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[13] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[14] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[15] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[16] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[17] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[18] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[19] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[20] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[21] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[0] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[1] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[2] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[3] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[4] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[5] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[6] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[7] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[8] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[9] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[10] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[11] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[12] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[13] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[14] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[15] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[16] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[17] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[18] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[19] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[20] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[21] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[0] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[1] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[2] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[3] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[4] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[5] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[6] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[7] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[8] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[9] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[10] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[11] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[12] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[13] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[14] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[15] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[16] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[17] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[18] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[19] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[20] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[21] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[0] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[1] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[2] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[3] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[4] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[5] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[6] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[7] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[8] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[9] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[10] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[11] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[12] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[13] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[14] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[15] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[16] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[17] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[18] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[19] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[20] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[21] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[0] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[1] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[2] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[3] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[4] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[5] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[6] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[7] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[8] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[9] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[10] -1 1 -.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[11] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[12] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[13] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[14] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[15] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[16] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[17] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[18] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[19] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[20] -1 1 -.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[21] -1 1 -.names $false DBusCachedPlugin_redoBranch_payload[0] -1 1 -.names $false DBusCachedPlugin_redoBranch_payload[1] -1 1 -.names debug_bus_rsp_data[5] DebugPlugin_busReadDataReg[5] -1 1 -.names debug_bus_rsp_data[6] DebugPlugin_busReadDataReg[6] -1 1 -.names debug_bus_rsp_data[7] DebugPlugin_busReadDataReg[7] -1 1 -.names debug_bus_rsp_data[8] DebugPlugin_busReadDataReg[8] -1 1 -.names debug_bus_rsp_data[9] DebugPlugin_busReadDataReg[9] -1 1 -.names debug_bus_rsp_data[10] DebugPlugin_busReadDataReg[10] -1 1 -.names debug_bus_rsp_data[11] DebugPlugin_busReadDataReg[11] -1 1 -.names debug_bus_rsp_data[12] DebugPlugin_busReadDataReg[12] -1 1 -.names debug_bus_rsp_data[13] DebugPlugin_busReadDataReg[13] -1 1 -.names debug_bus_rsp_data[14] DebugPlugin_busReadDataReg[14] -1 1 -.names debug_bus_rsp_data[15] DebugPlugin_busReadDataReg[15] -1 1 -.names debug_bus_rsp_data[16] DebugPlugin_busReadDataReg[16] -1 1 -.names debug_bus_rsp_data[17] DebugPlugin_busReadDataReg[17] -1 1 -.names debug_bus_rsp_data[18] DebugPlugin_busReadDataReg[18] -1 1 -.names debug_bus_rsp_data[19] DebugPlugin_busReadDataReg[19] -1 1 -.names debug_bus_rsp_data[20] DebugPlugin_busReadDataReg[20] -1 1 -.names debug_bus_rsp_data[21] DebugPlugin_busReadDataReg[21] -1 1 -.names debug_bus_rsp_data[22] DebugPlugin_busReadDataReg[22] -1 1 -.names debug_bus_rsp_data[23] DebugPlugin_busReadDataReg[23] -1 1 -.names debug_bus_rsp_data[24] DebugPlugin_busReadDataReg[24] -1 1 -.names debug_bus_rsp_data[25] DebugPlugin_busReadDataReg[25] -1 1 -.names debug_bus_rsp_data[26] DebugPlugin_busReadDataReg[26] -1 1 -.names debug_bus_rsp_data[27] DebugPlugin_busReadDataReg[27] -1 1 -.names debug_bus_rsp_data[28] DebugPlugin_busReadDataReg[28] -1 1 -.names debug_bus_rsp_data[29] DebugPlugin_busReadDataReg[29] -1 1 -.names debug_bus_rsp_data[30] DebugPlugin_busReadDataReg[30] -1 1 -.names debug_bus_rsp_data[31] DebugPlugin_busReadDataReg[31] -1 1 -.names _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[2] -1 1 -.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[5] -1 1 -.names _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[7] -1 1 -.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[12] -1 1 -.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[31] -1 1 -.names $false IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[0] -1 1 -.names $false IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[1] -1 1 -.names $false IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[0] -1 1 -.names $false IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[1] -1 1 -.names $false IBusCachedPlugin_cache.lineLoader_address[0] -1 1 -.names $false IBusCachedPlugin_cache.lineLoader_address[1] -1 1 -.names iBus_cmd_payload_address[5] IBusCachedPlugin_cache.lineLoader_address[5] -1 1 -.names iBus_cmd_payload_address[6] IBusCachedPlugin_cache.lineLoader_address[6] -1 1 -.names iBus_cmd_payload_address[7] IBusCachedPlugin_cache.lineLoader_address[7] -1 1 -.names iBus_cmd_payload_address[8] IBusCachedPlugin_cache.lineLoader_address[8] -1 1 -.names iBus_cmd_payload_address[9] IBusCachedPlugin_cache.lineLoader_address[9] -1 1 -.names iBus_cmd_payload_address[10] IBusCachedPlugin_cache.lineLoader_address[10] -1 1 -.names iBus_cmd_payload_address[11] IBusCachedPlugin_cache.lineLoader_address[11] -1 1 -.names iBus_cmd_payload_address[12] IBusCachedPlugin_cache.lineLoader_address[12] -1 1 -.names iBus_cmd_payload_address[13] IBusCachedPlugin_cache.lineLoader_address[13] -1 1 -.names iBus_cmd_payload_address[14] IBusCachedPlugin_cache.lineLoader_address[14] -1 1 -.names iBus_cmd_payload_address[15] IBusCachedPlugin_cache.lineLoader_address[15] -1 1 -.names iBus_cmd_payload_address[16] IBusCachedPlugin_cache.lineLoader_address[16] -1 1 -.names iBus_cmd_payload_address[17] IBusCachedPlugin_cache.lineLoader_address[17] -1 1 -.names iBus_cmd_payload_address[18] IBusCachedPlugin_cache.lineLoader_address[18] -1 1 -.names iBus_cmd_payload_address[19] IBusCachedPlugin_cache.lineLoader_address[19] -1 1 -.names iBus_cmd_payload_address[20] IBusCachedPlugin_cache.lineLoader_address[20] -1 1 -.names iBus_cmd_payload_address[21] IBusCachedPlugin_cache.lineLoader_address[21] -1 1 -.names iBus_cmd_payload_address[22] IBusCachedPlugin_cache.lineLoader_address[22] -1 1 -.names iBus_cmd_payload_address[23] IBusCachedPlugin_cache.lineLoader_address[23] -1 1 -.names iBus_cmd_payload_address[24] IBusCachedPlugin_cache.lineLoader_address[24] -1 1 -.names iBus_cmd_payload_address[25] IBusCachedPlugin_cache.lineLoader_address[25] -1 1 -.names iBus_cmd_payload_address[26] IBusCachedPlugin_cache.lineLoader_address[26] -1 1 -.names iBus_cmd_payload_address[27] IBusCachedPlugin_cache.lineLoader_address[27] -1 1 -.names iBus_cmd_payload_address[28] IBusCachedPlugin_cache.lineLoader_address[28] -1 1 -.names iBus_cmd_payload_address[29] IBusCachedPlugin_cache.lineLoader_address[29] -1 1 -.names iBus_cmd_payload_address[30] IBusCachedPlugin_cache.lineLoader_address[30] -1 1 -.names iBus_cmd_payload_address[31] IBusCachedPlugin_cache.lineLoader_address[31] -1 1 -.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[7] -1 1 -.names $false IBusCachedPlugin_predictionJumpInterface_payload[0] -1 1 -.names _zz_10 IBusCachedPlugin_predictionJumpInterface_payload[1] -1 1 -.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRspStaged_payload_data[0] -1 1 -.names MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRspStaged_payload_data[1] -1 1 -.names MmuPlugin_shared_dBusRsp_pte_W MmuPlugin_shared_dBusRspStaged_payload_data[2] -1 1 -.names MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_shared_dBusRspStaged_payload_data[3] -1 1 -.names MmuPlugin_shared_dBusRsp_pte_A MmuPlugin_shared_dBusRspStaged_payload_data[6] -1 1 -.names MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRspStaged_payload_data[7] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[0] $auto$memory_bram.cc:844:replace_memory$6842[0] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[1] $auto$memory_bram.cc:844:replace_memory$6842[1] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[2] $auto$memory_bram.cc:844:replace_memory$6842[2] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[3] $auto$memory_bram.cc:844:replace_memory$6842[3] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[4] $auto$memory_bram.cc:844:replace_memory$6842[4] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[5] $auto$memory_bram.cc:844:replace_memory$6842[5] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[6] $auto$memory_bram.cc:844:replace_memory$6842[6] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[7] $auto$memory_bram.cc:844:replace_memory$6842[7] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[8] $auto$memory_bram.cc:844:replace_memory$6842[8] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[9] $auto$memory_bram.cc:844:replace_memory$6842[9] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[10] $auto$memory_bram.cc:844:replace_memory$6842[10] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[11] $auto$memory_bram.cc:844:replace_memory$6842[11] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[12] $auto$memory_bram.cc:844:replace_memory$6842[12] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[13] $auto$memory_bram.cc:844:replace_memory$6842[13] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[14] $auto$memory_bram.cc:844:replace_memory$6842[14] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[15] $auto$memory_bram.cc:844:replace_memory$6842[15] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[16] $auto$memory_bram.cc:844:replace_memory$6842[16] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[17] $auto$memory_bram.cc:844:replace_memory$6842[17] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[18] $auto$memory_bram.cc:844:replace_memory$6842[18] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[19] $auto$memory_bram.cc:844:replace_memory$6842[19] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[20] $auto$memory_bram.cc:844:replace_memory$6842[20] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[21] $auto$memory_bram.cc:844:replace_memory$6842[21] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[22] $auto$memory_bram.cc:844:replace_memory$6842[22] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[23] $auto$memory_bram.cc:844:replace_memory$6842[23] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[24] $auto$memory_bram.cc:844:replace_memory$6842[24] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[25] $auto$memory_bram.cc:844:replace_memory$6842[25] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[26] $auto$memory_bram.cc:844:replace_memory$6842[26] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[27] $auto$memory_bram.cc:844:replace_memory$6842[27] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[28] $auto$memory_bram.cc:844:replace_memory$6842[28] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[29] $auto$memory_bram.cc:844:replace_memory$6842[29] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[30] $auto$memory_bram.cc:844:replace_memory$6842[30] -1 1 -.names IBusCachedPlugin_cache._zz_banks_0_port1[31] $auto$memory_bram.cc:844:replace_memory$6842[31] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] $auto$memory_bram.cc:844:replace_memory$6847[0] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] $auto$memory_bram.cc:844:replace_memory$6847[1] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] $auto$memory_bram.cc:844:replace_memory$6847[2] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] $auto$memory_bram.cc:844:replace_memory$6847[3] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] $auto$memory_bram.cc:844:replace_memory$6847[4] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] $auto$memory_bram.cc:844:replace_memory$6847[5] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] $auto$memory_bram.cc:844:replace_memory$6847[6] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] $auto$memory_bram.cc:844:replace_memory$6847[7] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] $auto$memory_bram.cc:844:replace_memory$6847[8] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] $auto$memory_bram.cc:844:replace_memory$6847[9] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] $auto$memory_bram.cc:844:replace_memory$6847[10] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] $auto$memory_bram.cc:844:replace_memory$6847[11] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] $auto$memory_bram.cc:844:replace_memory$6847[12] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] $auto$memory_bram.cc:844:replace_memory$6847[13] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] $auto$memory_bram.cc:844:replace_memory$6847[14] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] $auto$memory_bram.cc:844:replace_memory$6847[15] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] $auto$memory_bram.cc:844:replace_memory$6847[16] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] $auto$memory_bram.cc:844:replace_memory$6847[17] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] $auto$memory_bram.cc:844:replace_memory$6847[18] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] $auto$memory_bram.cc:844:replace_memory$6847[19] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] $auto$memory_bram.cc:844:replace_memory$6847[20] -1 1 -.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] $auto$memory_bram.cc:844:replace_memory$6847[21] -1 1 -.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$6849[0] -1 1 -.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$6849[1] -1 1 -.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$6849[2] -1 1 -.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$6849[3] -1 1 -.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$6849[4] -1 1 -.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$6849[5] -1 1 -.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$6849[6] -1 1 -.names _zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$6849[7] -1 1 -.names _zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$6849[8] -1 1 -.names _zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$6849[9] -1 1 -.names _zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$6849[10] -1 1 -.names _zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$6849[11] -1 1 -.names _zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$6849[12] -1 1 -.names _zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$6849[13] -1 1 -.names _zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$6849[14] -1 1 -.names _zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$6849[15] -1 1 -.names _zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$6849[16] -1 1 -.names _zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$6849[17] -1 1 -.names _zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$6849[18] -1 1 -.names _zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$6849[19] -1 1 -.names _zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$6849[20] -1 1 -.names _zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$6849[21] -1 1 -.names _zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$6849[22] -1 1 -.names _zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$6849[23] -1 1 -.names _zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$6849[24] -1 1 -.names _zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$6849[25] -1 1 -.names _zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$6849[26] -1 1 -.names _zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$6849[27] -1 1 -.names _zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$6849[28] -1 1 -.names _zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$6849[29] -1 1 -.names _zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$6849[30] -1 1 -.names _zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$6849[31] -1 1 -.names _zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$6850[0] -1 1 -.names _zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$6850[1] -1 1 -.names _zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$6850[2] -1 1 -.names _zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$6850[3] -1 1 -.names _zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$6850[4] -1 1 -.names _zz_RegFilePlugin_regFile_port0[5] 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_zz_writeBack_MulPlugin_result_1[23] -1 1 -.names $false _zz_writeBack_MulPlugin_result_1[24] -1 1 -.names $false _zz_writeBack_MulPlugin_result_1[25] -1 1 -.names $false _zz_writeBack_MulPlugin_result_1[26] -1 1 -.names $false _zz_writeBack_MulPlugin_result_1[27] -1 1 -.names $false _zz_writeBack_MulPlugin_result_1[28] -1 1 -.names $false _zz_writeBack_MulPlugin_result_1[29] -1 1 -.names $false _zz_writeBack_MulPlugin_result_1[30] -1 1 -.names $false _zz_writeBack_MulPlugin_result_1[31] -1 1 -.names $true dBus_cmd_payload_last -1 1 -.names dBus_cmd_payload_address[5] dataCache_1.dataWriteCmd_payload_address[3] -1 1 -.names dBus_cmd_payload_address[6] dataCache_1.dataWriteCmd_payload_address[4] -1 1 -.names dBus_cmd_payload_address[7] dataCache_1.dataWriteCmd_payload_address[5] -1 1 -.names dBus_cmd_payload_address[8] dataCache_1.dataWriteCmd_payload_address[6] -1 1 -.names dBus_cmd_payload_address[9] dataCache_1.dataWriteCmd_payload_address[7] -1 1 -.names dBus_cmd_payload_address[10] dataCache_1.dataWriteCmd_payload_address[8] -1 1 -.names dBus_cmd_payload_address[11] dataCache_1.dataWriteCmd_payload_address[9] -1 1 -.names dBus_cmd_payload_address[5] dataCache_1.stageB_mmuRsp_physicalAddress[5] -1 1 -.names dBus_cmd_payload_address[6] dataCache_1.stageB_mmuRsp_physicalAddress[6] -1 1 -.names dBus_cmd_payload_address[7] dataCache_1.stageB_mmuRsp_physicalAddress[7] -1 1 -.names dBus_cmd_payload_address[8] dataCache_1.stageB_mmuRsp_physicalAddress[8] -1 1 -.names dBus_cmd_payload_address[9] dataCache_1.stageB_mmuRsp_physicalAddress[9] -1 1 -.names dBus_cmd_payload_address[10] dataCache_1.stageB_mmuRsp_physicalAddress[10] -1 1 -.names dBus_cmd_payload_address[11] dataCache_1.stageB_mmuRsp_physicalAddress[11] -1 1 -.names dBus_cmd_payload_address[12] dataCache_1.stageB_mmuRsp_physicalAddress[12] -1 1 -.names dBus_cmd_payload_address[13] dataCache_1.stageB_mmuRsp_physicalAddress[13] -1 1 -.names dBus_cmd_payload_address[14] dataCache_1.stageB_mmuRsp_physicalAddress[14] -1 1 -.names dBus_cmd_payload_address[15] dataCache_1.stageB_mmuRsp_physicalAddress[15] -1 1 -.names dBus_cmd_payload_address[16] dataCache_1.stageB_mmuRsp_physicalAddress[16] -1 1 -.names dBus_cmd_payload_address[17] dataCache_1.stageB_mmuRsp_physicalAddress[17] -1 1 -.names dBus_cmd_payload_address[18] dataCache_1.stageB_mmuRsp_physicalAddress[18] -1 1 -.names dBus_cmd_payload_address[19] dataCache_1.stageB_mmuRsp_physicalAddress[19] -1 1 -.names dBus_cmd_payload_address[20] dataCache_1.stageB_mmuRsp_physicalAddress[20] -1 1 -.names dBus_cmd_payload_address[21] dataCache_1.stageB_mmuRsp_physicalAddress[21] -1 1 -.names dBus_cmd_payload_address[22] dataCache_1.stageB_mmuRsp_physicalAddress[22] -1 1 -.names dBus_cmd_payload_address[23] dataCache_1.stageB_mmuRsp_physicalAddress[23] -1 1 -.names dBus_cmd_payload_address[24] dataCache_1.stageB_mmuRsp_physicalAddress[24] -1 1 -.names dBus_cmd_payload_address[25] dataCache_1.stageB_mmuRsp_physicalAddress[25] -1 1 -.names dBus_cmd_payload_address[26] dataCache_1.stageB_mmuRsp_physicalAddress[26] -1 1 -.names dBus_cmd_payload_address[27] dataCache_1.stageB_mmuRsp_physicalAddress[27] -1 1 -.names dBus_cmd_payload_address[28] dataCache_1.stageB_mmuRsp_physicalAddress[28] -1 1 -.names dBus_cmd_payload_address[29] dataCache_1.stageB_mmuRsp_physicalAddress[29] -1 1 -.names dBus_cmd_payload_address[30] dataCache_1.stageB_mmuRsp_physicalAddress[30] -1 1 -.names dBus_cmd_payload_address[31] dataCache_1.stageB_mmuRsp_physicalAddress[31] -1 1 -.names $undef decode_INSTRUCTION_ANTICIPATED[25] -1 1 -.names $undef decode_INSTRUCTION_ANTICIPATED[26] -1 1 -.names $undef decode_INSTRUCTION_ANTICIPATED[27] -1 1 -.names $undef decode_INSTRUCTION_ANTICIPATED[28] -1 1 -.names $undef decode_INSTRUCTION_ANTICIPATED[29] -1 1 -.names $undef decode_INSTRUCTION_ANTICIPATED[30] -1 1 -.names $undef decode_INSTRUCTION_ANTICIPATED[31] -1 1 -.names execute_RS1[16] execute_MulPlugin_aHigh[0] -1 1 -.names execute_RS1[17] execute_MulPlugin_aHigh[1] -1 1 -.names execute_RS1[18] execute_MulPlugin_aHigh[2] -1 1 -.names execute_RS1[19] execute_MulPlugin_aHigh[3] -1 1 -.names execute_RS1[20] execute_MulPlugin_aHigh[4] -1 1 -.names execute_RS1[21] execute_MulPlugin_aHigh[5] -1 1 -.names execute_RS1[22] execute_MulPlugin_aHigh[6] -1 1 -.names execute_RS1[23] execute_MulPlugin_aHigh[7] -1 1 -.names execute_RS1[24] execute_MulPlugin_aHigh[8] -1 1 -.names execute_RS1[25] execute_MulPlugin_aHigh[9] -1 1 -.names execute_RS1[26] execute_MulPlugin_aHigh[10] -1 1 -.names execute_RS1[27] execute_MulPlugin_aHigh[11] -1 1 -.names execute_RS1[28] execute_MulPlugin_aHigh[12] -1 1 -.names execute_RS1[29] execute_MulPlugin_aHigh[13] -1 1 -.names execute_RS1[30] execute_MulPlugin_aHigh[14] -1 1 -.names execute_RS1[31] execute_MulPlugin_aHigh[15] -1 1 -.names execute_RS2[16] execute_MulPlugin_bHigh[0] -1 1 -.names execute_RS2[17] execute_MulPlugin_bHigh[1] -1 1 -.names execute_RS2[18] execute_MulPlugin_bHigh[2] -1 1 -.names execute_RS2[19] execute_MulPlugin_bHigh[3] -1 1 -.names execute_RS2[20] execute_MulPlugin_bHigh[4] -1 1 -.names execute_RS2[21] execute_MulPlugin_bHigh[5] -1 1 -.names execute_RS2[22] execute_MulPlugin_bHigh[6] -1 1 -.names execute_RS2[23] execute_MulPlugin_bHigh[7] -1 1 -.names execute_RS2[24] execute_MulPlugin_bHigh[8] -1 1 -.names execute_RS2[25] execute_MulPlugin_bHigh[9] -1 1 -.names execute_RS2[26] execute_MulPlugin_bHigh[10] -1 1 -.names execute_RS2[27] execute_MulPlugin_bHigh[11] -1 1 -.names execute_RS2[28] execute_MulPlugin_bHigh[12] -1 1 -.names execute_RS2[29] execute_MulPlugin_bHigh[13] -1 1 -.names execute_RS2[30] execute_MulPlugin_bHigh[14] -1 1 -.names execute_RS2[31] execute_MulPlugin_bHigh[15] -1 1 -.names $false execute_to_memory_PC[0] -1 1 -.names $false execute_to_memory_PC[1] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[0] execute_to_memory_PC[2] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[1] execute_to_memory_PC[3] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[2] execute_to_memory_PC[4] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[3] execute_to_memory_PC[5] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[4] execute_to_memory_PC[6] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[5] execute_to_memory_PC[7] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[6] execute_to_memory_PC[8] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[7] execute_to_memory_PC[9] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[8] execute_to_memory_PC[10] -1 1 -.names _zz_decode_PREDICTION_CONTEXT_hazard_1[9] execute_to_memory_PC[11] -1 1 -.names $false iBus_cmd_payload_address[0] -1 1 -.names $false iBus_cmd_payload_address[1] -1 1 -.names $false iBus_cmd_payload_address[2] -1 1 -.names $false iBus_cmd_payload_address[3] -1 1 -.names $false iBus_cmd_payload_address[4] -1 1 -.names $true iBus_cmd_payload_size[0] -1 1 -.names $false iBus_cmd_payload_size[1] -1 1 -.names $true iBus_cmd_payload_size[2] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] memory_DivPlugin_accumulator[0] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] memory_DivPlugin_accumulator[1] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] memory_DivPlugin_accumulator[2] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] memory_DivPlugin_accumulator[3] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] memory_DivPlugin_accumulator[4] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] memory_DivPlugin_accumulator[5] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] memory_DivPlugin_accumulator[6] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] memory_DivPlugin_accumulator[7] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] memory_DivPlugin_accumulator[8] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] memory_DivPlugin_accumulator[9] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] memory_DivPlugin_accumulator[10] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] memory_DivPlugin_accumulator[11] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] memory_DivPlugin_accumulator[12] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] memory_DivPlugin_accumulator[13] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] memory_DivPlugin_accumulator[14] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] memory_DivPlugin_accumulator[15] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] memory_DivPlugin_accumulator[16] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] memory_DivPlugin_accumulator[17] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] memory_DivPlugin_accumulator[18] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] memory_DivPlugin_accumulator[19] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] memory_DivPlugin_accumulator[20] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] memory_DivPlugin_accumulator[21] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] memory_DivPlugin_accumulator[22] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] memory_DivPlugin_accumulator[23] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] memory_DivPlugin_accumulator[24] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] memory_DivPlugin_accumulator[25] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] memory_DivPlugin_accumulator[26] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] memory_DivPlugin_accumulator[27] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] memory_DivPlugin_accumulator[28] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] memory_DivPlugin_accumulator[29] -1 1 -.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] memory_DivPlugin_accumulator[30] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif deleted file mode 100644 index d81a68f31e7..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif +++ /dev/null @@ -1,10133 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model VexRiscv -.inputs iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_error iBus_rsp_payload_inst[0] iBus_rsp_payload_inst[1] iBus_rsp_payload_inst[2] iBus_rsp_payload_inst[3] iBus_rsp_payload_inst[4] iBus_rsp_payload_inst[5] iBus_rsp_payload_inst[6] iBus_rsp_payload_inst[7] iBus_rsp_payload_inst[8] iBus_rsp_payload_inst[9] iBus_rsp_payload_inst[10] iBus_rsp_payload_inst[11] iBus_rsp_payload_inst[12] iBus_rsp_payload_inst[13] iBus_rsp_payload_inst[14] iBus_rsp_payload_inst[15] iBus_rsp_payload_inst[16] iBus_rsp_payload_inst[17] iBus_rsp_payload_inst[18] iBus_rsp_payload_inst[19] iBus_rsp_payload_inst[20] iBus_rsp_payload_inst[21] iBus_rsp_payload_inst[22] iBus_rsp_payload_inst[23] iBus_rsp_payload_inst[24] iBus_rsp_payload_inst[25] iBus_rsp_payload_inst[26] iBus_rsp_payload_inst[27] iBus_rsp_payload_inst[28] iBus_rsp_payload_inst[29] iBus_rsp_payload_inst[30] iBus_rsp_payload_inst[31] timerInterrupt externalInterrupt softwareInterrupt dBus_cmd_ready dBus_rsp_ready dBus_rsp_error dBus_rsp_data[0] dBus_rsp_data[1] dBus_rsp_data[2] dBus_rsp_data[3] dBus_rsp_data[4] dBus_rsp_data[5] dBus_rsp_data[6] dBus_rsp_data[7] dBus_rsp_data[8] dBus_rsp_data[9] dBus_rsp_data[10] dBus_rsp_data[11] dBus_rsp_data[12] dBus_rsp_data[13] dBus_rsp_data[14] dBus_rsp_data[15] dBus_rsp_data[16] dBus_rsp_data[17] dBus_rsp_data[18] dBus_rsp_data[19] dBus_rsp_data[20] dBus_rsp_data[21] dBus_rsp_data[22] dBus_rsp_data[23] dBus_rsp_data[24] dBus_rsp_data[25] dBus_rsp_data[26] dBus_rsp_data[27] dBus_rsp_data[28] dBus_rsp_data[29] dBus_rsp_data[30] dBus_rsp_data[31] clk reset -.outputs iBus_cmd_valid iBus_cmd_payload_pc[0] iBus_cmd_payload_pc[1] iBus_cmd_payload_pc[2] iBus_cmd_payload_pc[3] iBus_cmd_payload_pc[4] iBus_cmd_payload_pc[5] iBus_cmd_payload_pc[6] iBus_cmd_payload_pc[7] iBus_cmd_payload_pc[8] iBus_cmd_payload_pc[9] iBus_cmd_payload_pc[10] iBus_cmd_payload_pc[11] iBus_cmd_payload_pc[12] iBus_cmd_payload_pc[13] iBus_cmd_payload_pc[14] iBus_cmd_payload_pc[15] iBus_cmd_payload_pc[16] iBus_cmd_payload_pc[17] iBus_cmd_payload_pc[18] iBus_cmd_payload_pc[19] iBus_cmd_payload_pc[20] iBus_cmd_payload_pc[21] iBus_cmd_payload_pc[22] iBus_cmd_payload_pc[23] iBus_cmd_payload_pc[24] iBus_cmd_payload_pc[25] iBus_cmd_payload_pc[26] iBus_cmd_payload_pc[27] iBus_cmd_payload_pc[28] iBus_cmd_payload_pc[29] iBus_cmd_payload_pc[30] iBus_cmd_payload_pc[31] dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] -.names $false -.names $true -1 -.names $undef -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1273 iBus_cmd_payload_pc[30] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$new_n1255 $abc$8788$new_n1254 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$new_n1256 $abc$8788$new_n1255 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$new_n1257 $abc$8788$new_n1256 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1257 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1258 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1259 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1260 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1261 -11 1 -.names IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$new_n1263 $abc$8788$new_n1262 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$new_n1264 $abc$8788$new_n1263 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$new_n1265 $abc$8788$new_n1264 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$new_n1266 $abc$8788$new_n1265 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$new_n1267 $abc$8788$new_n1266 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$new_n1268 $abc$8788$new_n1267 -111 1 -.names IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$new_n1269 $abc$8788$new_n1268 -111 1 -.names IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$new_n1269 -111 1 -.names $abc$8788$new_n1271 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$8788$new_n1270 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1272 lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1271 -000 1 -001 1 -010 1 -.names CsrPlugin_interrupt_valid CsrPlugin_pipelineLiberator_done $abc$8788$new_n1272 -11 1 -.names BranchPlugin_jumpInterface_payload[30] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[30] $abc$8788$new_n1273 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz_writeBack_ENV_CTRL lastStageIsFiring _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] $abc$8788$new_n1274 -1111 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[30] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$6999 -001 1 -011 1 -110 1 -111 1 -.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n2461 $abc$8788$new_n1270 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1276 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names $abc$8788$new_n2464 $abc$8788$new_n1296 $abc$8788$new_n1278 -10 1 -.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] execute_to_memory_INSTRUCTION[7] $abc$8788$new_n1283 -1100 1 -1111 1 -.names $abc$8788$new_n1286 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n1285 -10000 1 -10011 1 -11100 1 -11111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n1286 -00 1 -11 1 -.names $abc$8788$new_n1289 HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1288 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n1290 HazardSimplePlugin_writeBackBuffer_valid HazardSimplePlugin_writeBackBuffer_payload_address[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1289 -1100 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1290 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz_lastStageRegFileWrite_valid lastStageIsFiring HazardSimplePlugin_writeBackWrites_valid -11 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1296 -11 1 -.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n1304 -1100 1 -1111 1 -.names $abc$8788$new_n1317 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1316 $abc$8788$new_n1315 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1316 -10 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1317 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE dBus_rsp_ready execute_to_memory_MEMORY_STORE $abc$8788$new_n1321 -1100 1 -.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$8788$new_n1322 -11 1 -.names execute_arbitration_isValid $abc$8788$new_n1324 _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1323 -1001 1 -1010 1 -1011 1 -.names decode_to_execute_SRC2[0] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1324 -00000 1 -.names $abc$8788$new_n1327 $abc$8788$new_n1326 $abc$8788$new_n1325 -11 1 -.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] $abc$8788$new_n1326 -00000 1 -00100 1 -01000 1 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[4] execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1327 -00000 1 -00100 1 -01000 1 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names $abc$8788$new_n1329 _zz_memory_ENV_CTRL memory_arbitration_isValid lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1328 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid execute_arbitration_isValid _zz_execute_ENV_CTRL $abc$8788$new_n1329 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n1330 -00001 1 -00010 1 -00011 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1332 iBus_cmd_payload_pc[29] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[29] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[29] $abc$8788$new_n1332 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[29] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7001 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1335 iBus_cmd_payload_pc[28] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[28] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[28] $abc$8788$new_n1335 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[28] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7003 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1338 iBus_cmd_payload_pc[27] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[27] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[27] $abc$8788$new_n1338 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[27] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7005 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1341 iBus_cmd_payload_pc[26] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[26] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[26] $abc$8788$new_n1341 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[26] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7007 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1344 iBus_cmd_payload_pc[25] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[25] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[25] $abc$8788$new_n1344 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[25] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7009 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1347 iBus_cmd_payload_pc[24] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[24] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[24] $abc$8788$new_n1347 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[24] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7011 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1350 iBus_cmd_payload_pc[23] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[23] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[23] $abc$8788$new_n1350 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[23] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7013 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1353 iBus_cmd_payload_pc[22] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[22] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[22] $abc$8788$new_n1353 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[22] IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7015 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1356 iBus_cmd_payload_pc[21] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[21] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[21] $abc$8788$new_n1356 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[21] IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7017 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1359 iBus_cmd_payload_pc[20] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[20] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[20] $abc$8788$new_n1359 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[20] IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7019 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1362 iBus_cmd_payload_pc[19] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[19] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[19] $abc$8788$new_n1362 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[19] IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7021 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1365 iBus_cmd_payload_pc[18] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[18] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[18] $abc$8788$new_n1365 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[18] IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7023 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1368 iBus_cmd_payload_pc[17] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[17] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[17] $abc$8788$new_n1368 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[17] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7025 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1371 iBus_cmd_payload_pc[16] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[16] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[16] $abc$8788$new_n1371 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[16] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7027 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1374 iBus_cmd_payload_pc[15] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[15] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[15] $abc$8788$new_n1374 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[15] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7029 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1377 iBus_cmd_payload_pc[14] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[14] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[14] $abc$8788$new_n1377 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[14] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7031 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1380 iBus_cmd_payload_pc[13] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[13] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[13] $abc$8788$new_n1380 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[13] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7033 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1383 iBus_cmd_payload_pc[12] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[12] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[12] $abc$8788$new_n1383 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[12] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7035 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1386 iBus_cmd_payload_pc[11] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[11] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[11] $abc$8788$new_n1386 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[11] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7037 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1389 iBus_cmd_payload_pc[10] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[10] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[10] $abc$8788$new_n1389 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[10] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7039 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1392 iBus_cmd_payload_pc[9] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[9] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[9] $abc$8788$new_n1392 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[9] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7041 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1395 iBus_cmd_payload_pc[8] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[8] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[8] $abc$8788$new_n1395 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[8] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7043 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1398 iBus_cmd_payload_pc[7] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[7] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[7] $abc$8788$new_n1398 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[7] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7045 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1401 iBus_cmd_payload_pc[6] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[6] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[6] $abc$8788$new_n1401 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[6] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7047 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1404 iBus_cmd_payload_pc[5] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$8788$new_n1271 BranchPlugin_jumpInterface_payload[5] $abc$8788$new_n1274 CsrPlugin_mepc[5] $abc$8788$new_n1404 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[5] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7049 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1407 iBus_cmd_payload_pc[4] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[4] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[4] $abc$8788$new_n1407 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[4] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7051 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1410 iBus_cmd_payload_pc[3] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names BranchPlugin_jumpInterface_payload[3] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[3] $abc$8788$new_n1410 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[3] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7053 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1413 iBus_cmd_payload_pc[2] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names BranchPlugin_jumpInterface_payload[2] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[2] $abc$8788$new_n1413 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n1276 iBus_cmd_payload_pc[2] IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7055 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[30] CsrPlugin_mepc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7439 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[29] CsrPlugin_mepc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7441 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[28] CsrPlugin_mepc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7443 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[27] CsrPlugin_mepc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7445 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[26] CsrPlugin_mepc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7447 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[25] CsrPlugin_mepc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7449 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[24] CsrPlugin_mepc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7451 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[23] CsrPlugin_mepc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7453 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[22] CsrPlugin_mepc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7455 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[21] CsrPlugin_mepc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7457 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[20] CsrPlugin_mepc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7459 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[19] CsrPlugin_mepc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7461 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[18] CsrPlugin_mepc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7463 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[17] CsrPlugin_mepc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7465 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[16] CsrPlugin_mepc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7467 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[15] CsrPlugin_mepc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7469 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[14] CsrPlugin_mepc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7471 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[13] CsrPlugin_mepc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7473 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[12] CsrPlugin_mepc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7475 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[11] CsrPlugin_mepc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7477 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[10] CsrPlugin_mepc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7479 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[9] CsrPlugin_mepc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7481 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[8] CsrPlugin_mepc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7483 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[7] CsrPlugin_mepc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7485 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[6] CsrPlugin_mepc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7487 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[5] CsrPlugin_mepc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7489 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[4] CsrPlugin_mepc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7491 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[3] CsrPlugin_mepc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7493 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[2] CsrPlugin_mepc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7495 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1446 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7497 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1321 $abc$8788$new_n1445 -10 1 -.names $abc$8788$new_n1447 $abc$8788$new_n1326 $abc$8788$new_n1446 -11 1 -.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[0] decode_to_execute_SRC2[0] $abc$8788$new_n1447 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1449 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7499 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$new_n1449 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7501 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_amplitudeReg[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7503 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7741 -001 1 -011 1 -110 1 -111 1 -.names IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n1454 $abc$8788$new_n1453 -11 1 -.names $abc$8788$new_n1455 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n1454 -1000 1 -.names $abc$8788$new_n1270 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n2461 $abc$8788$new_n1455 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7743 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7745 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7747 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7749 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] iBus_rsp_payload_inst[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7751 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7753 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7755 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7757 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7759 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7761 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7763 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7765 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1453 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$abc$8788$new_n1557 -0011 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[12] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[12] $abc$8788$new_n1558 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n1559 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n1560 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] $abc$8788$new_n1561 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n1562 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[15] $abc$8788$new_n1563 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1564 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1565 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[18] $abc$8788$new_n1566 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[17] $abc$8788$new_n1567 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1568 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1569 -10 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n1570 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[19] $abc$8788$new_n1571 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n1572 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[21] $abc$8788$new_n1573 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1574 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n1575 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[23] $abc$8788$new_n1576 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1577 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n1578 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[25] $abc$8788$new_n1579 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1580 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n1581 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[27] $abc$8788$new_n1582 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_2[26] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[26] $abc$8788$new_n1583 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1584 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[29] $abc$8788$new_n1585 -00 1 -11 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1587 $abc$8788$new_n1586 -11 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1323 $abc$8788$new_n1587 -00 1 -.names $abc$8788$new_n1589 $abc$8788$new_n1322 $abc$8788$new_n1588 -00 1 -.names _zz_execute_ALU_CTRL[0] _zz_execute_ALU_CTRL[1] $abc$8788$new_n1589 -10 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[30] $abc$8788$new_n1323 $abc$8788$new_n1591 $abc$8788$new_n1590 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1593 execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n1591 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1592 -10 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[29] _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1593 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1594 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11010 1 -11100 1 -11111 1 -.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$8788$new_n1595 -10 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1598 dBus_cmd_payload_address[29] $abc$8788$new_n1601 $abc$8788$auto$rtlil.cc:2693:MuxGate$7059 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[29] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[29] $abc$8788$new_n1323 $abc$8788$new_n1599 $abc$8788$new_n1598 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1600 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n1599 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[28] _zz_execute_SrcPlugin_addSub_2[28] $abc$8788$new_n1600 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1601 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1605 dBus_cmd_payload_address[28] $abc$8788$new_n1608 $abc$8788$auto$rtlil.cc:2693:MuxGate$7061 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1604 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[28] -00000 1 -00110 1 -01010 1 -01100 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1604 -0000 1 -0001 1 -0011 1 -0101 1 -1001 1 -1101 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[28] $abc$8788$new_n1323 $abc$8788$new_n1606 $abc$8788$new_n1605 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 $abc$8788$new_n1607 $abc$8788$new_n1593 $abc$8788$new_n1606 -001 1 -011 1 -110 1 -111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[27] _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1607 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1608 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1611 dBus_cmd_payload_address[27] $abc$8788$new_n1614 $abc$8788$auto$rtlil.cc:2693:MuxGate$7063 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1583 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1532 dBus_cmd_payload_address[27] -00000 1 -01001 1 -01100 1 -01101 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[27] $abc$8788$new_n1323 $abc$8788$new_n1612 $abc$8788$new_n1611 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 $abc$8788$new_n1613 $abc$8788$new_n1600 $abc$8788$new_n1612 -001 1 -011 1 -110 1 -111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[26] _zz_execute_SrcPlugin_addSub_2[26] $abc$8788$new_n1613 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1614 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1618 dBus_cmd_payload_address[26] $abc$8788$new_n1620 $abc$8788$auto$rtlil.cc:2693:MuxGate$7065 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1617 _zz_execute_SrcPlugin_addSub_2[26] dBus_cmd_payload_address[26] -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1578 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 $abc$8788$new_n1533 $abc$8788$new_n1617 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[26] $abc$8788$new_n1323 $abc$8788$new_n1619 $abc$8788$new_n1618 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1607 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1619 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1620 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1622 execute_to_memory_REGFILE_WRITE_DATA[25] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7067 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1624 $abc$8788$new_n1626 $abc$8788$new_n1586 dBus_cmd_payload_address[25] $abc$8788$new_n1595 $abc$8788$new_n1622 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1533 dBus_cmd_payload_address[25] -00000 1 -01001 1 -01100 1 -01101 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1625 $abc$8788$new_n1613 $abc$8788$new_n1624 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[24] _zz_execute_SrcPlugin_addSub_2[24] $abc$8788$new_n1625 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1626 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1631 dBus_cmd_payload_address[24] $abc$8788$new_n1634 $abc$8788$auto$rtlil.cc:2693:MuxGate$7069 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1629 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[24] -00010 1 -00100 1 -01000 1 -01110 1 -10000 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 $abc$8788$new_n1629 -000 1 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1577 $abc$8788$new_n1534 $abc$8788$new_n1630 -00 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[24] $abc$8788$new_n1323 $abc$8788$new_n1632 $abc$8788$new_n1631 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1633 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1632 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[23] _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1633 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1634 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1636 execute_to_memory_REGFILE_WRITE_DATA[23] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7071 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1638 $abc$8788$new_n1640 $abc$8788$new_n1586 dBus_cmd_payload_address[23] $abc$8788$new_n1595 $abc$8788$new_n1636 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[23] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1639 $abc$8788$new_n1625 $abc$8788$new_n1638 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[22] _zz_execute_SrcPlugin_addSub_2[22] $abc$8788$new_n1639 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1640 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1642 execute_to_memory_REGFILE_WRITE_DATA[22] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7073 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1646 $abc$8788$new_n1648 $abc$8788$new_n1586 dBus_cmd_payload_address[22] $abc$8788$new_n1595 $abc$8788$new_n1642 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1644 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[22] -00010 1 -00100 1 -01000 1 -01110 1 -10000 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 $abc$8788$new_n1644 -000 1 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1574 $abc$8788$new_n1535 $abc$8788$new_n1645 -00 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1647 $abc$8788$new_n1633 $abc$8788$new_n1646 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[21] _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1647 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1648 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1653 $abc$8788$new_n1650 $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7075 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 dBus_cmd_payload_address[21] $abc$8788$new_n1652 $abc$8788$new_n1650 -1010 1 -1011 1 -1101 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[21] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1652 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1654 $abc$8788$new_n1639 $abc$8788$new_n1653 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[20] _zz_execute_SrcPlugin_addSub_2[20] $abc$8788$new_n1654 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1656 execute_to_memory_REGFILE_WRITE_DATA[20] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7077 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1660 $abc$8788$new_n1662 $abc$8788$new_n1586 dBus_cmd_payload_address[20] $abc$8788$new_n1595 $abc$8788$new_n1656 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1658 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[20] -00010 1 -00100 1 -01000 1 -01110 1 -10000 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 $abc$8788$new_n1658 -000 1 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1569 $abc$8788$new_n1536 $abc$8788$new_n1659 -00 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1661 $abc$8788$new_n1647 $abc$8788$new_n1660 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[19] _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1661 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1662 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1664 execute_to_memory_REGFILE_WRITE_DATA[19] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7079 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1666 $abc$8788$new_n1586 $abc$8788$new_n1668 $abc$8788$new_n1595 dBus_cmd_payload_address[19] $abc$8788$new_n1664 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[19] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1667 $abc$8788$new_n1654 $abc$8788$new_n1666 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[18] _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1667 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1668 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11010 1 -11100 1 -11111 1 -.names $abc$8788$new_n1670 execute_to_memory_REGFILE_WRITE_DATA[18] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7081 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1673 $abc$8788$new_n1675 $abc$8788$new_n1586 dBus_cmd_payload_address[18] $abc$8788$new_n1595 $abc$8788$new_n1670 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1672 _zz_execute_SrcPlugin_addSub_2[18] dBus_cmd_payload_address[18] -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1565 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 $abc$8788$new_n1537 $abc$8788$new_n1672 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1674 $abc$8788$new_n1661 $abc$8788$new_n1673 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[17] _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1674 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1675 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1678 dBus_cmd_payload_address[17] $abc$8788$new_n1680 $abc$8788$auto$rtlil.cc:2693:MuxGate$7083 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1537 dBus_cmd_payload_address[17] -00000 1 -01001 1 -01100 1 -01101 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[17] $abc$8788$new_n1323 $abc$8788$new_n1679 $abc$8788$new_n1678 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1667 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1679 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1680 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1682 execute_to_memory_REGFILE_WRITE_DATA[16] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7085 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1686 $abc$8788$new_n1688 $abc$8788$new_n1586 dBus_cmd_payload_address[16] $abc$8788$new_n1595 $abc$8788$new_n1682 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1684 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[16] -00010 1 -00100 1 -01000 1 -01110 1 -10000 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 $abc$8788$new_n1684 -000 1 -100 1 -101 1 -110 1 -.names $abc$8788$new_n1564 $abc$8788$new_n1538 $abc$8788$new_n1685 -00 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1687 $abc$8788$new_n1674 $abc$8788$new_n1686 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[15] _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1687 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1688 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1691 dBus_cmd_payload_address[15] $abc$8788$new_n1694 $abc$8788$auto$rtlil.cc:2693:MuxGate$7087 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[15] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[15] $abc$8788$new_n1323 $abc$8788$new_n1692 $abc$8788$new_n1691 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1693 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1692 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[14] _zz_execute_SrcPlugin_addSub_2[14] $abc$8788$new_n1693 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1694 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1696 execute_to_memory_REGFILE_WRITE_DATA[14] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7089 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1700 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[14] $abc$8788$new_n1702 $abc$8788$new_n1696 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1698 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[14] -00000 1 -00110 1 -01010 1 -01100 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1557 $abc$8788$new_n1699 $abc$8788$new_n1560 $abc$8788$new_n1698 -000 1 -001 1 -010 1 -.names $abc$8788$new_n1561 $abc$8788$new_n1539 $abc$8788$new_n1699 -10 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1701 $abc$8788$new_n1687 $abc$8788$new_n1700 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1701 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1702 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1704 execute_to_memory_REGFILE_WRITE_DATA[13] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7091 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1706 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[13] $abc$8788$new_n1708 $abc$8788$new_n1704 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1560 $abc$8788$new_n1558 $abc$8788$new_n1699 _zz_execute_SrcPlugin_addSub_2[13] dBus_cmd_payload_address[13] -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1707 $abc$8788$new_n1693 $abc$8788$new_n1706 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[12] _zz_execute_SrcPlugin_addSub_2[12] $abc$8788$new_n1707 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1708 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1710 execute_to_memory_REGFILE_WRITE_DATA[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7093 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1711 $abc$8788$new_n1592 $abc$8788$new_n1323 $abc$8788$new_n1715 $abc$8788$new_n1701 $abc$8788$new_n1710 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$8788$new_n1713 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[12] $abc$8788$new_n1714 $abc$8788$new_n1711 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1539 $abc$8788$new_n1561 _zz_execute_SrcPlugin_addSub_2[12] dBus_cmd_payload_address[12] -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$8788$new_n1323 execute_CsrPlugin_csr_768 $abc$8788$new_n1322 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1713 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -.names _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1714 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[11] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1715 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1717 execute_to_memory_REGFILE_WRITE_DATA[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7095 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1722 $abc$8788$new_n1718 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1501 $abc$8788$new_n1717 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[11] $abc$8788$new_n1721 $abc$8788$new_n1718 -1010 1 -1011 1 -1101 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1720 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[11] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1540 $abc$8788$new_n1720 -000 1 -100 1 -101 1 -110 1 -.names _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1721 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1723 $abc$8788$new_n1707 $abc$8788$new_n1722 -1001 1 -1011 1 -1110 1 -1111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[10] _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1723 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1725 execute_to_memory_REGFILE_WRITE_DATA[10] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7097 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1727 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[10] $abc$8788$new_n1729 $abc$8788$new_n1725 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1556 $abc$8788$new_n1540 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[10] -0000 1 -0110 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1728 $abc$8788$new_n1715 $abc$8788$new_n1727 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[9] _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1728 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1729 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[9] $abc$8788$new_n1731 $abc$8788$new_n1735 $abc$8788$auto$rtlil.cc:2693:MuxGate$7099 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1734 dBus_cmd_payload_address[9] $abc$8788$new_n1595 $abc$8788$new_n1731 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1733 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[9] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1553 $abc$8788$new_n1541 $abc$8788$new_n1554 $abc$8788$new_n1733 -000 1 -010 1 -011 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1734 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1736 $abc$8788$new_n1723 $abc$8788$new_n1735 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[8] _zz_execute_SrcPlugin_addSub_2[8] $abc$8788$new_n1736 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[8] $abc$8788$new_n1738 $abc$8788$new_n1741 $abc$8788$auto$rtlil.cc:2693:MuxGate$7101 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1740 dBus_cmd_payload_address[8] $abc$8788$new_n1595 $abc$8788$new_n1738 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1541 $abc$8788$new_n1554 _zz_execute_SrcPlugin_addSub_2[8] dBus_cmd_payload_address[8] -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1740 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1742 $abc$8788$new_n1728 $abc$8788$new_n1741 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[7] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1742 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1744 execute_to_memory_REGFILE_WRITE_DATA[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7103 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1749 $abc$8788$new_n1745 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1497 $abc$8788$new_n1744 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1748 dBus_cmd_payload_address[7] $abc$8788$new_n1595 $abc$8788$new_n1745 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1747 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[7] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1542 $abc$8788$new_n1747 -001 1 -100 1 -101 1 -111 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1748 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1750 $abc$8788$new_n1736 $abc$8788$new_n1749 -1001 1 -1011 1 -1110 1 -1111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[6] _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1750 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1752 execute_to_memory_REGFILE_WRITE_DATA[6] $abc$8788$new_n1323 $abc$8788$new_n1755 $abc$8788$auto$rtlil.cc:2693:MuxGate$7105 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1754 dBus_cmd_payload_address[6] $abc$8788$new_n1595 $abc$8788$new_n1752 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1551 $abc$8788$new_n1542 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[6] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1754 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1742 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1755 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1757 execute_to_memory_REGFILE_WRITE_DATA[5] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7107 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$8788$new_n1760 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[5] $abc$8788$new_n1762 $abc$8788$new_n1757 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1759 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[5] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1548 $abc$8788$new_n1543 $abc$8788$new_n1549 $abc$8788$new_n1759 -000 1 -010 1 -011 1 -.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1761 $abc$8788$new_n1750 $abc$8788$new_n1760 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[4] _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n1761 -000 1 -010 1 -100 1 -101 1 -.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1762 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1764 execute_to_memory_REGFILE_WRITE_DATA[4] $abc$8788$new_n1323 $abc$8788$new_n1767 $abc$8788$auto$rtlil.cc:2693:MuxGate$7109 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1766 dBus_cmd_payload_address[4] $abc$8788$new_n1595 $abc$8788$new_n1764 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1543 $abc$8788$new_n1549 _zz_execute_SrcPlugin_addSub_2[4] dBus_cmd_payload_address[4] -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1766 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1768 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1767 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[3] _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1768 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1770 execute_to_memory_REGFILE_WRITE_DATA[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7111 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n1775 $abc$8788$new_n1771 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1493 $abc$8788$new_n1770 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[3] $abc$8788$new_n1774 $abc$8788$new_n1771 -1010 1 -1011 1 -1101 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1544 $abc$8788$new_n1773 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[3] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1773 -001 1 -100 1 -101 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1774 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1776 $abc$8788$new_n1761 $abc$8788$new_n1775 -1001 1 -1011 1 -1110 1 -1111 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[2] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1776 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[2] $abc$8788$new_n1783 $abc$8788$new_n1781 $abc$8788$new_n1778 $abc$8788$auto$rtlil.cc:2693:MuxGate$7113 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1588 $abc$8788$new_n1595 $abc$8788$new_n1323 dBus_cmd_payload_address[2] $abc$8788$new_n1780 $abc$8788$new_n1778 -10010 1 -10011 1 -11001 1 -11011 1 -.names _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1546 $abc$8788$new_n1545 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[2] -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1780 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1782 $abc$8788$new_n1768 $abc$8788$new_n1781 -1000 1 -1010 1 -1100 1 -1101 1 -.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[1] _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n1782 -000 1 -010 1 -100 1 -101 1 -.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$8788$new_n1322 $abc$8788$new_n1323 $abc$8788$new_n1783 -1110 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1785 execute_to_memory_REGFILE_WRITE_DATA[1] $abc$8788$new_n1323 $abc$8788$new_n1790 $abc$8788$auto$rtlil.cc:2693:MuxGate$7115 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[1] $abc$8788$new_n1789 $abc$8788$new_n1785 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names $abc$8788$new_n1323 $abc$8788$new_n1322 execute_CsrPlugin_csr_834 $abc$8788$new_n1786 -000 1 -001 1 -010 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1788 _zz_execute_SrcPlugin_addSub_2[1] dBus_cmd_payload_address[1] -010 1 -011 1 -101 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] $abc$8788$new_n1788 -00011 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11011 1 -11101 1 -.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1789 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1776 execute_to_memory_REGFILE_WRITE_DATA[0] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1790 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$8788$new_n1803 $abc$8788$new_n1322 $abc$8788$new_n1587 $abc$8788$new_n1792 execute_CsrPlugin_csr_834 $abc$8788$auto$rtlil.cc:2693:MuxGate$7117 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$8788$new_n1589 $abc$8788$new_n1799 $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n1792 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1796 $abc$8788$new_n1798 $abc$8788$new_n1794 _zz_execute_SrcPlugin_addSub_2[31] dBus_cmd_payload_address[31] -00000 1 -00001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$8788$new_n1531 $abc$8788$new_n1584 _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1795 $abc$8788$new_n1794 -00101 1 -01001 1 -01101 1 -01111 1 -10001 1 -10101 1 -10111 1 -11001 1 -11101 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n1795 -001 1 -010 1 -100 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_4 $abc$8788$new_n1797 $abc$8788$new_n1796 -01 1 -10 1 -.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] $abc$8788$new_n1797 -00 1 -11 1 -.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1798 -101 1 -110 1 -.names $abc$8788$new_n1595 $abc$8788$new_n1800 dBus_cmd_payload_address[0] $abc$8788$new_n1799 -000 1 -010 1 -110 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1800 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -1010 1 -1100 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[0] -010 1 -100 1 -101 1 -111 1 -.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC_LESS_UNSIGNED decode_to_execute_SRC2[31] $abc$8788$new_n1802 -000 1 -010 1 -011 1 -100 1 -101 1 -111 1 -.names $abc$8788$new_n1321 $abc$8788$new_n1323 execute_to_memory_REGFILE_WRITE_DATA[0] $abc$8788$new_n1782 $abc$8788$new_n1592 $abc$8788$new_n1803 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01100 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 execute_to_memory_MEMORY_ADDRESS_LOW[0] dBus_cmd_payload_address[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7119 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1806 decode_to_execute_SRC2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7121 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] _zz_decode_SRC2 $abc$8788$new_n1806 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n1807 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1809 decode_to_execute_SRC2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7123 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] _zz_decode_SRC2 $abc$8788$new_n1809 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1811 decode_to_execute_SRC2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7125 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] _zz_decode_SRC2 $abc$8788$new_n1811 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1813 decode_to_execute_SRC2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7127 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] _zz_decode_SRC2 $abc$8788$new_n1813 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1815 decode_to_execute_SRC2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7129 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] _zz_decode_SRC2 $abc$8788$new_n1815 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1817 decode_to_execute_SRC2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7131 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] _zz_decode_SRC2 $abc$8788$new_n1817 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1819 decode_to_execute_SRC2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7133 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] _zz_decode_SRC2 $abc$8788$new_n1819 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1821 decode_to_execute_SRC2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7135 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] _zz_decode_SRC2 $abc$8788$new_n1821 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1823 decode_to_execute_SRC2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7137 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] _zz_decode_SRC2 $abc$8788$new_n1823 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1825 decode_to_execute_SRC2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7139 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] _zz_decode_SRC2 $abc$8788$new_n1825 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1827 decode_to_execute_SRC2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7141 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] _zz_decode_SRC2 $abc$8788$new_n1827 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1829 decode_to_execute_SRC2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7143 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] _zz_decode_SRC2 $abc$8788$new_n1829 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1831 decode_to_execute_SRC2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7145 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] _zz_decode_SRC2 $abc$8788$new_n1831 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1833 decode_to_execute_SRC2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7147 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] _zz_decode_SRC2 $abc$8788$new_n1833 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1835 decode_to_execute_SRC2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7149 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] _zz_decode_SRC2 $abc$8788$new_n1835 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1837 decode_to_execute_SRC2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7151 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] _zz_decode_SRC2 $abc$8788$new_n1837 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1839 decode_to_execute_SRC2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7153 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] _zz_decode_SRC2 $abc$8788$new_n1839 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1841 decode_to_execute_SRC2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7155 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] _zz_decode_SRC2 $abc$8788$new_n1841 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1843 decode_to_execute_SRC2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7157 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] _zz_decode_SRC2 $abc$8788$new_n1843 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1845 decode_to_execute_SRC2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7159 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] _zz_decode_SRC2 $abc$8788$new_n1845 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1847 decode_to_execute_SRC2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7161 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n1847 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1849 decode_to_execute_SRC2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7163 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$8788$new_n1849 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1851 decode_to_execute_SRC2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7165 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$8788$new_n1851 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1853 decode_to_execute_SRC2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7167 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n1853 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1855 decode_to_execute_SRC2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7169 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n1855 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1857 decode_to_execute_SRC2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7171 -001 1 -011 1 -110 1 -111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$8788$new_n1857 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1859 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7173 -001 1 -011 1 -100 1 -101 1 -.names $abc$8788$new_n1860 _zz_RegFilePlugin_regFile_port1[4] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[4] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1859 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1860 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1861 -1000 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 $abc$8788$new_n1862 -00 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1864 decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7175 -001 1 -011 1 -100 1 -101 1 -.names $abc$8788$new_n1865 _zz_RegFilePlugin_regFile_port1[3] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[3] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1864 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1865 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1867 decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7177 -001 1 -011 1 -100 1 -101 1 -.names $abc$8788$new_n1868 _zz_RegFilePlugin_regFile_port1[2] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[2] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1867 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n1868 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1870 decode_to_execute_SRC2[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7179 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[1] $abc$8788$new_n1870 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1872 decode_to_execute_SRC2[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7181 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[0] $abc$8788$new_n1872 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[30] decode_to_execute_RS2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7183 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[29] decode_to_execute_RS2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7185 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[28] decode_to_execute_RS2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7187 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[27] decode_to_execute_RS2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7189 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[26] decode_to_execute_RS2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7191 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[25] decode_to_execute_RS2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7193 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[24] decode_to_execute_RS2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7195 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[23] decode_to_execute_RS2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7197 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[22] decode_to_execute_RS2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7199 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[21] decode_to_execute_RS2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7201 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[20] decode_to_execute_RS2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7203 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[19] decode_to_execute_RS2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7205 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[18] decode_to_execute_RS2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7207 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[17] decode_to_execute_RS2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7209 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[16] decode_to_execute_RS2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7211 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[15] decode_to_execute_RS2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7213 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[14] decode_to_execute_RS2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7215 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[13] decode_to_execute_RS2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7217 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[12] decode_to_execute_RS2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7219 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[11] decode_to_execute_RS2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7221 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[10] decode_to_execute_RS2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7223 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[9] decode_to_execute_RS2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7225 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[8] decode_to_execute_RS2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7227 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[7] dBus_cmd_payload_data[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7229 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[6] dBus_cmd_payload_data[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7231 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[5] dBus_cmd_payload_data[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7233 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[4] dBus_cmd_payload_data[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7235 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[3] dBus_cmd_payload_data[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7237 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[2] dBus_cmd_payload_data[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7239 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[1] dBus_cmd_payload_data[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7241 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[0] dBus_cmd_payload_data[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7243 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[30] decode_to_execute_RS1[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7245 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[29] decode_to_execute_RS1[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7247 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[28] decode_to_execute_RS1[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7249 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[27] decode_to_execute_RS1[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7251 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[26] decode_to_execute_RS1[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7253 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[25] decode_to_execute_RS1[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7255 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[24] decode_to_execute_RS1[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7257 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[23] decode_to_execute_RS1[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7259 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[22] decode_to_execute_RS1[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7261 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[21] decode_to_execute_RS1[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7263 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[20] decode_to_execute_RS1[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7265 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[19] decode_to_execute_RS1[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7267 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[18] decode_to_execute_RS1[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7269 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[17] decode_to_execute_RS1[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7271 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[16] decode_to_execute_RS1[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7273 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[15] decode_to_execute_RS1[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7275 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[14] decode_to_execute_RS1[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7277 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[13] decode_to_execute_RS1[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7279 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[12] decode_to_execute_RS1[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7281 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[11] decode_to_execute_RS1[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7283 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[10] decode_to_execute_RS1[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7285 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[9] decode_to_execute_RS1[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7287 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[8] decode_to_execute_RS1[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7289 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[7] decode_to_execute_RS1[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7291 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[6] decode_to_execute_RS1[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7293 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[5] decode_to_execute_RS1[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7295 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[4] decode_to_execute_RS1[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7297 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[3] decode_to_execute_RS1[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7299 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[2] decode_to_execute_RS1[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7301 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[1] decode_to_execute_RS1[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7303 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[0] decode_to_execute_RS1[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7305 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_execute_BRANCH_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7307 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1937 _zz_execute_SHIFT_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7309 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n1937 -11000 1 -.names $abc$8788$new_n2458 _zz_execute_ALU_BITWISE_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7311 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7313 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7317 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7319 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7347 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7349 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[12] dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7351 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7353 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7355 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7357 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7359 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7361 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7377 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7379 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7381 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7383 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7385 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7387 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] 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$abc$8788$new_n2237 -10000 1 -10011 1 -11100 1 -11111 1 -.names _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n2238 -0000 1 -0011 1 -1100 1 -1111 1 -.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] $abc$8788$new_n2240 $abc$8788$new_n2239 -00000 1 -00110 1 -11000 1 -11110 1 -.names _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n2240 -01 1 -10 1 -.names $abc$8788$new_n2243 $abc$8788$new_n1802 $abc$8788$new_n2244 dBus_cmd_payload_address[31] $abc$8788$new_n1797 $abc$8788$new_n2242 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[13] dBus_cmd_payload_size[0] $abc$8788$new_n2221 switch_Misc_l241_1 $abc$8788$new_n2243 -0001 1 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n2244 -000 1 -.names $abc$8788$new_n1321 execute_to_memory_BRANCH_DO $abc$8788$new_n2245 -10 1 -.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n1321 $abc$8788$new_n2246 -00 1 -.names $abc$8788$new_n1321 $abc$8788$new_n2248 execute_to_memory_REGFILE_WRITE_DATA[31] $abc$8788$new_n1323 $abc$8788$new_n2250 $abc$8788$auto$rtlil.cc:2693:MuxGate$7899 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[31] $abc$8788$new_n2249 $abc$8788$new_n2248 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n2249 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -.names $abc$8788$new_n2251 execute_LightShifterPlugin_isActive $abc$8788$new_n1592 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n2250 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n2251 -11001 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 dBus_cmd_payload_address[1] execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7901 -010 1 -011 1 -101 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2254 decode_to_execute_SRC2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7903 -001 1 -011 1 -100 1 -101 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] _zz_decode_SRC2 $abc$8788$new_n2254 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -.names $abc$8788$new_n2256 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7905 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$8788$new_n2257 $abc$8788$new_n1937 _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2256 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2258 $abc$8788$new_n2257 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2258 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[31] decode_to_execute_RS2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7907 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[31] decode_to_execute_RS1[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7909 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2262 _zz_execute_BRANCH_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7911 -001 1 -011 1 -100 1 -101 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2262 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$8788$new_n2458 _zz_execute_SHIFT_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1937 $abc$8788$auto$rtlil.cc:2693:MuxGate$7913 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 _zz_execute_ALU_BITWISE_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7915 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1316 decode_to_execute_SRC_LESS_UNSIGNED IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7917 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2267 $abc$8788$auto$rtlil.cc:2693:MuxGate$7919 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$new_n2267 -000 1 -010 1 -011 1 -.names $abc$8788$new_n1321 _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$8788$auto$rtlil.cc:2693:MuxGate$7921 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_execute_ENV_CTRL $abc$8788$new_n1296 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7923 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1296 decode_to_execute_IS_CSR IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7925 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names dBus_cmd_payload_wr $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7927 -10 1 -.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_47 dBus_cmd_payload_wr $abc$8788$auto$rtlil.cc:2693:MuxGate$7929 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$8788$auto$rtlil.cc:2693:MuxGate$7931 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2275 decode_to_execute_REGFILE_WRITE_VALID $abc$8788$new_n2277 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7935 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$8788$new_n2276 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2275 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n2276 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n2277 -0000 1 -.names decode_to_execute_MEMORY_ENABLE $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7937 -01 1 -10 1 -11 1 -.names $abc$8788$new_n2458 decode_to_execute_MEMORY_ENABLE IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7939 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -11000 1 -.names $abc$8788$new_n2257 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_4 $abc$8788$auto$rtlil.cc:2693:MuxGate$7941 -001 1 -010 1 -011 1 -.names $abc$8788$new_n2458 decode_to_execute_CSR_WRITE_OPCODE $abc$8788$new_n2282 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7943 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2282 -10000 1 -.names $abc$8788$new_n2458 _zz_decode_SRC2 _zz_execute_BranchPlugin_branch_src2 $abc$8788$auto$rtlil.cc:2693:MuxGate$7947 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC2 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] decode_INSTRUCTION_ANTICIPATED[31] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 $abc$8788$new_n2287 $abc$8788$new_n2286 BranchPlugin_jumpInterface_payload[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7965 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2059 $abc$8788$new_n2005 $abc$8788$new_n2286 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1111 1 -.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2020 decode_to_execute_PC[31] decode_to_execute_RS1[31] $abc$8788$new_n2287 -0000 1 -0001 1 -0100 1 -0110 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7971 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[31] decode_to_execute_PC[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7973 -001 1 -011 1 -110 1 -111 1 -.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[11] _zz_RegFilePlugin_regFile_port0[11] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7979 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$8788$new_n2292 _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7983 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz_RegFilePlugin_regFile_port0[4] $abc$8788$new_n2292 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n2294 _zz_execute_SrcPlugin_addSub_2[31] _zz_RegFilePlugin_regFile_port0[31] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7985 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names _zz_decode_SRC2 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2294 -1110 1 -.names decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$new_n1321 dBus_cmd_valid -1110 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[8] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[9] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[10] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[11] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[12] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[13] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[14] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[15] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[16] dBus_cmd_payload_data[0] dBus_cmd_payload_data[16] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[17] dBus_cmd_payload_data[1] dBus_cmd_payload_data[17] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[18] dBus_cmd_payload_data[2] dBus_cmd_payload_data[18] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[19] dBus_cmd_payload_data[3] dBus_cmd_payload_data[19] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[20] dBus_cmd_payload_data[4] dBus_cmd_payload_data[20] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[21] dBus_cmd_payload_data[5] dBus_cmd_payload_data[21] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[22] dBus_cmd_payload_data[6] dBus_cmd_payload_data[22] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 decode_to_execute_RS2[23] dBus_cmd_payload_data[7] dBus_cmd_payload_data[23] -001 1 -011 1 -110 1 -111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[24] decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[24] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[25] decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[25] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[26] decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[26] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[27] decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[27] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[28] decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[28] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[29] decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[29] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[30] decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[30] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[31] decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[31] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2321 $abc$8788$new_n1492 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] -001 1 -011 1 -110 1 -111 1 -.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2321 -1111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] decode_INSTRUCTION_ANTICIPATED[15] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] decode_INSTRUCTION_ANTICIPATED[16] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] decode_INSTRUCTION_ANTICIPATED[17] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] decode_INSTRUCTION_ANTICIPATED[18] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] decode_INSTRUCTION_ANTICIPATED[19] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 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$abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[9] lastStageRegFileWrite_payload_data[9] -00001 1 -00010 1 -00011 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[9] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2382 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names _zz_5 $abc$8788$new_n2384 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[10] lastStageRegFileWrite_payload_data[10] -00001 1 -00010 1 -00011 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[10] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2384 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 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_zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2388 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names _zz_5 $abc$8788$new_n2390 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[13] lastStageRegFileWrite_payload_data[13] -00001 1 -00010 1 -00011 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[29] memory_to_writeBack_MEMORY_READ_DATA[13] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2390 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names _zz_5 $abc$8788$new_n2392 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[14] lastStageRegFileWrite_payload_data[14] -00001 1 -00010 1 -00011 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[30] memory_to_writeBack_MEMORY_READ_DATA[14] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2392 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names _zz_5 $abc$8788$new_n2394 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[15] lastStageRegFileWrite_payload_data[15] -00001 1 -00010 1 -00011 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2394 -001 1 -010 1 -011 1 -.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[31] memory_to_writeBack_MEMORY_READ_DATA[15] $abc$8788$new_n2395 -000 1 -010 1 -100 1 -101 1 -.names $abc$8788$new_n2397 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[16] lastStageRegFileWrite_payload_data[16] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[16] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2397 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2378 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[14] $abc$8788$new_n2398 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2400 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[17] lastStageRegFileWrite_payload_data[17] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[17] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2400 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2402 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[18] lastStageRegFileWrite_payload_data[18] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[18] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2402 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2404 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[19] lastStageRegFileWrite_payload_data[19] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[19] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2404 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2406 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[20] lastStageRegFileWrite_payload_data[20] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[20] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2406 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2408 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[21] lastStageRegFileWrite_payload_data[21] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[21] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2408 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2410 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[22] lastStageRegFileWrite_payload_data[22] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[22] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2410 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2412 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[23] lastStageRegFileWrite_payload_data[23] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[23] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2412 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2414 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[24] lastStageRegFileWrite_payload_data[24] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[24] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2414 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2416 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[25] lastStageRegFileWrite_payload_data[25] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[25] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2416 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2418 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[26] lastStageRegFileWrite_payload_data[26] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[26] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2418 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2420 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[27] lastStageRegFileWrite_payload_data[27] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[27] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2420 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2422 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[28] lastStageRegFileWrite_payload_data[28] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[28] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2422 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2424 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[29] lastStageRegFileWrite_payload_data[29] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[29] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2424 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2426 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[30] lastStageRegFileWrite_payload_data[30] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[30] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2426 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$8788$new_n2428 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[31] lastStageRegFileWrite_payload_data[31] -101 1 -110 1 -111 1 -.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[31] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2428 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_5 lastStageRegFileWrite_payload_address[0] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_5 lastStageRegFileWrite_payload_address[1] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_5 lastStageRegFileWrite_payload_address[2] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_5 lastStageRegFileWrite_payload_address[3] -10 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_5 lastStageRegFileWrite_payload_address[4] -10 1 -.names _zz_5 HazardSimplePlugin_writeBackWrites_valid _zz_1 -01 1 -10 1 -11 1 -.names IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[1] -001 1 -010 1 -100 1 -111 1 -.names $abc$8788$new_n1505 $abc$8788$new_n2334 $abc$8788$new_n2436 -10 1 -.names IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[2] -0010 1 -0100 1 -0101 1 -0111 1 -1001 1 -1100 1 -1110 1 -1111 1 -.names $abc$8788$new_n1505 $abc$8788$new_n2334 IBusSimplePlugin_pending_next[0] -00 1 -11 1 -.names $abc$8788$new_n1283 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] execute_to_memory_INSTRUCTION[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] execute_to_memory_INSTRUCTION[9] $abc$8788$new_n2439 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2439 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] execute_to_memory_INSTRUCTION[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n2440 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2442 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2442 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2443 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n1304 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] execute_to_memory_INSTRUCTION[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] execute_to_memory_INSTRUCTION[8] $abc$8788$new_n2445 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2445 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] execute_to_memory_INSTRUCTION[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] execute_to_memory_INSTRUCTION[10] $abc$8788$new_n2446 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -.names execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2448 -10000 1 -10011 1 -11100 1 -11111 1 -.names decode_to_execute_REGFILE_WRITE_VALID IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2_4[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n2449 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2448 $abc$8788$new_n2449 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2450 -1100 1 -1111 1 -.names HazardSimplePlugin_writeBackBuffer_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackBuffer_payload_address[0] HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2451 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2451 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2452 -10000 1 -10011 1 -11100 1 -11111 1 -.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2454 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$8788$new_n2454 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2455 -10000 1 -10011 1 -11100 1 -11111 1 -.names decode_to_execute_IS_CSR memory_arbitration_isValid lastStageIsFiring decode_to_execute_MEMORY_ENABLE dBus_cmd_ready $abc$8788$new_n2457 -00010 1 -00110 1 -01010 1 -01110 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n1321 execute_arbitration_isValid $abc$8788$new_n2457 $abc$8788$new_n1323 $abc$8788$new_n1325 $abc$8788$new_n2458 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2452 HazardSimplePlugin_writeBackBuffer_payload_address[4] $abc$8788$new_n2455 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2459 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names $abc$8788$new_n1278 $abc$8788$new_n1315 $abc$8788$new_n2446 $abc$8788$new_n2459 $abc$8788$new_n2450 $abc$8788$new_n2460 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$8788$new_n2458 $abc$8788$new_n1328 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2460 $abc$8788$new_n2461 -1100 1 -1101 1 -1110 1 -.names $abc$8788$new_n1285 decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$new_n2462 -11100 1 -11111 1 -.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n2443 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2462 _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2463 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2463 $abc$8788$new_n1288 $abc$8788$new_n2440 $abc$8788$new_n2464 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7861 Q=CsrPlugin_mcause_exceptionCode[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7969 Q=CsrPlugin_mcause_exceptionCode[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7957 Q=CsrPlugin_interrupt_code[3] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[15] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[16] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[17] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[18] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[19] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[20] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[21] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[22] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[23] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[24] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7859 Q=decode_to_execute_PC[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7857 Q=decode_to_execute_PC[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7855 Q=decode_to_execute_PC[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7853 Q=decode_to_execute_PC[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7851 Q=decode_to_execute_PC[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7849 Q=decode_to_execute_PC[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7847 Q=decode_to_execute_PC[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7845 Q=decode_to_execute_PC[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7843 Q=decode_to_execute_PC[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7841 Q=decode_to_execute_PC[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7839 Q=decode_to_execute_PC[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7837 Q=decode_to_execute_PC[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7835 Q=decode_to_execute_PC[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7833 Q=decode_to_execute_PC[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7831 Q=decode_to_execute_PC[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7829 Q=decode_to_execute_PC[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7827 Q=decode_to_execute_PC[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7825 Q=decode_to_execute_PC[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7823 Q=decode_to_execute_PC[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7821 Q=decode_to_execute_PC[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7819 Q=decode_to_execute_PC[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7817 Q=decode_to_execute_PC[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7815 Q=decode_to_execute_PC[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7813 Q=decode_to_execute_PC[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7811 Q=decode_to_execute_PC[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7809 Q=decode_to_execute_PC[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7807 Q=decode_to_execute_PC[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7805 Q=decode_to_execute_PC[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7803 Q=decode_to_execute_PC[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7973 Q=decode_to_execute_PC[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7797 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7795 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7793 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7791 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7789 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7787 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7785 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7783 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7781 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7779 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7777 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7775 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7773 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7771 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7769 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7767 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7765 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7763 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7761 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7759 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7757 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7755 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7753 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7751 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7749 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7747 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7745 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7743 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7741 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7963 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7953 Q=CsrPlugin_interrupt_code[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7739 Q=_zz_execute_SrcPlugin_addSub_2[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7735 Q=_zz_execute_SrcPlugin_addSub_2[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7731 Q=_zz_execute_SrcPlugin_addSub_2[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7727 Q=_zz_execute_SrcPlugin_addSub_2[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7723 Q=_zz_execute_SrcPlugin_addSub_2[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7719 Q=_zz_execute_SrcPlugin_addSub_2[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7979 Q=_zz_execute_SrcPlugin_addSub_2[11] -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7863 Q=execute_LightShifterPlugin_isActive R=reset -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7715 Q=_zz_execute_SrcPlugin_addSub_2[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7711 Q=_zz_execute_SrcPlugin_addSub_2[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7707 Q=_zz_execute_SrcPlugin_addSub_2[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7983 Q=_zz_execute_SrcPlugin_addSub_2[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7703 Q=_zz_execute_SrcPlugin_addSub_2[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7701 Q=_zz_execute_SrcPlugin_addSub_2[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7699 Q=_zz_execute_SrcPlugin_addSub_2[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7697 Q=_zz_execute_SrcPlugin_addSub_2[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7695 Q=_zz_execute_SrcPlugin_addSub_2[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7693 Q=_zz_execute_SrcPlugin_addSub_2[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7691 Q=_zz_execute_SrcPlugin_addSub_2[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7689 Q=_zz_execute_SrcPlugin_addSub_2[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7687 Q=_zz_execute_SrcPlugin_addSub_2[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7685 Q=_zz_execute_SrcPlugin_addSub_2[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7683 Q=_zz_execute_SrcPlugin_addSub_2[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7681 Q=_zz_execute_SrcPlugin_addSub_2[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7679 Q=_zz_execute_SrcPlugin_addSub_2[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7677 Q=_zz_execute_SrcPlugin_addSub_2[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7675 Q=_zz_execute_SrcPlugin_addSub_2[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7673 Q=_zz_execute_SrcPlugin_addSub_2[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7671 Q=_zz_execute_SrcPlugin_addSub_2[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7669 Q=_zz_execute_SrcPlugin_addSub_2[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7667 Q=_zz_execute_SrcPlugin_addSub_2[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7665 Q=_zz_execute_SrcPlugin_addSub_2[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7985 Q=_zz_execute_SrcPlugin_addSub_2[31] -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7961 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=reset -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[2] Q=_zz_decode_SRC_LESS_UNSIGNED_4 -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[3] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[4] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[5] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_47 -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[6] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[7] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[8] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[9] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[10] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[11] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[12] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_13 -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[13] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[14] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[25] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[26] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[27] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[28] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[29] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[30] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] -.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[31] Q=_zz_decode_SRC2 -.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP -.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP -.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7619 Q=BranchPlugin_jumpInterface_payload[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7617 Q=BranchPlugin_jumpInterface_payload[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7615 Q=BranchPlugin_jumpInterface_payload[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7613 Q=BranchPlugin_jumpInterface_payload[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7611 Q=BranchPlugin_jumpInterface_payload[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7609 Q=BranchPlugin_jumpInterface_payload[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7607 Q=BranchPlugin_jumpInterface_payload[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7605 Q=BranchPlugin_jumpInterface_payload[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7603 Q=BranchPlugin_jumpInterface_payload[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7601 Q=BranchPlugin_jumpInterface_payload[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7599 Q=BranchPlugin_jumpInterface_payload[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7597 Q=BranchPlugin_jumpInterface_payload[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7595 Q=BranchPlugin_jumpInterface_payload[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7593 Q=BranchPlugin_jumpInterface_payload[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7591 Q=BranchPlugin_jumpInterface_payload[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7589 Q=BranchPlugin_jumpInterface_payload[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7587 Q=BranchPlugin_jumpInterface_payload[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7585 Q=BranchPlugin_jumpInterface_payload[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7583 Q=BranchPlugin_jumpInterface_payload[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7581 Q=BranchPlugin_jumpInterface_payload[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7579 Q=BranchPlugin_jumpInterface_payload[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7577 Q=BranchPlugin_jumpInterface_payload[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7575 Q=BranchPlugin_jumpInterface_payload[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7573 Q=BranchPlugin_jumpInterface_payload[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7571 Q=BranchPlugin_jumpInterface_payload[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7569 Q=BranchPlugin_jumpInterface_payload[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7567 Q=BranchPlugin_jumpInterface_payload[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7565 Q=BranchPlugin_jumpInterface_payload[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7563 Q=BranchPlugin_jumpInterface_payload[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7965 Q=BranchPlugin_jumpInterface_payload[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7561 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7559 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7557 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7555 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7553 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7551 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7549 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7547 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7545 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7543 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7541 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7539 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7537 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7535 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7533 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7531 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7529 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7527 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7525 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7523 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7521 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7519 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7517 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7515 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7513 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7511 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7509 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7507 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7505 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7971 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[31] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] -.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7503 Q=execute_LightShifterPlugin_amplitudeReg[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7501 Q=execute_LightShifterPlugin_amplitudeReg[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7499 Q=execute_LightShifterPlugin_amplitudeReg[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7497 Q=execute_LightShifterPlugin_amplitudeReg[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7949 Q=execute_LightShifterPlugin_amplitudeReg[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7495 Q=CsrPlugin_mepc[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7493 Q=CsrPlugin_mepc[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7491 Q=CsrPlugin_mepc[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7489 Q=CsrPlugin_mepc[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7487 Q=CsrPlugin_mepc[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7485 Q=CsrPlugin_mepc[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7483 Q=CsrPlugin_mepc[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7481 Q=CsrPlugin_mepc[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7479 Q=CsrPlugin_mepc[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7477 Q=CsrPlugin_mepc[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7475 Q=CsrPlugin_mepc[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7473 Q=CsrPlugin_mepc[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7471 Q=CsrPlugin_mepc[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7469 Q=CsrPlugin_mepc[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7467 Q=CsrPlugin_mepc[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7465 Q=CsrPlugin_mepc[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7463 Q=CsrPlugin_mepc[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7461 Q=CsrPlugin_mepc[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7459 Q=CsrPlugin_mepc[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7457 Q=CsrPlugin_mepc[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7455 Q=CsrPlugin_mepc[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7453 Q=CsrPlugin_mepc[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7451 Q=CsrPlugin_mepc[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7449 Q=CsrPlugin_mepc[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7447 Q=CsrPlugin_mepc[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7445 Q=CsrPlugin_mepc[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7443 Q=CsrPlugin_mepc[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7441 Q=CsrPlugin_mepc[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7439 Q=CsrPlugin_mepc[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7975 Q=CsrPlugin_mepc[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7423 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7421 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7419 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7417 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7415 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7413 Q=dBus_cmd_payload_size[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7411 Q=switch_Misc_l241_1 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7409 Q=_zz__zz_execute_BranchPlugin_branch_src2[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7407 Q=_zz__zz_execute_BranchPlugin_branch_src2[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7405 Q=_zz__zz_execute_BranchPlugin_branch_src2[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7403 Q=_zz__zz_execute_BranchPlugin_branch_src2[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7401 Q=_zz__zz_execute_BranchPlugin_branch_src2[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7399 Q=_zz__zz_execute_BranchPlugin_branch_src2[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7397 Q=_zz__zz_execute_BranchPlugin_branch_src2[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7395 Q=_zz__zz_execute_BranchPlugin_branch_src2[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7393 Q=_zz__zz_execute_BranchPlugin_branch_src2[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7391 Q=_zz__zz_execute_BranchPlugin_branch_src2[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7389 Q=_zz__zz_execute_BranchPlugin_branch_src2[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7387 Q=_zz__zz_execute_BranchPlugin_branch_src2[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7385 Q=_zz__zz_execute_BranchPlugin_branch_src2[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7383 Q=_zz__zz_execute_BranchPlugin_branch_src2[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7381 Q=_zz__zz_execute_BranchPlugin_branch_src2[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7379 Q=_zz__zz_execute_BranchPlugin_branch_src2[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7377 Q=_zz__zz_execute_BranchPlugin_branch_src2[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7947 Q=_zz_execute_BranchPlugin_branch_src2 -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[7] Q=HazardSimplePlugin_writeBackWrites_payload_address[0] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[8] Q=HazardSimplePlugin_writeBackWrites_payload_address[1] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[9] Q=HazardSimplePlugin_writeBackWrites_payload_address[2] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[10] Q=HazardSimplePlugin_writeBackWrites_payload_address[3] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[11] Q=HazardSimplePlugin_writeBackWrites_payload_address[4] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[12] Q=_zz_lastStageRegFileWrite_payload_address[12] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[13] Q=_zz_lastStageRegFileWrite_payload_address[13] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[14] Q=_zz_lastStageRegFileWrite_payload_address[14] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[28] Q=_zz_lastStageRegFileWrite_payload_address[28] -.subckt dff C=clk D=execute_to_memory_INSTRUCTION[29] Q=_zz_lastStageRegFileWrite_payload_address[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7361 Q=execute_to_memory_INSTRUCTION[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7359 Q=execute_to_memory_INSTRUCTION[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7357 Q=execute_to_memory_INSTRUCTION[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7355 Q=execute_to_memory_INSTRUCTION[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7353 Q=execute_to_memory_INSTRUCTION[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7351 Q=execute_to_memory_INSTRUCTION[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7349 Q=execute_to_memory_INSTRUCTION[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7347 Q=execute_to_memory_INSTRUCTION[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7319 Q=execute_to_memory_INSTRUCTION[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7317 Q=execute_to_memory_INSTRUCTION[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7943 Q=decode_to_execute_CSR_WRITE_OPCODE -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7941 Q=_zz_execute_SrcPlugin_addSub_4 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7939 Q=decode_to_execute_MEMORY_ENABLE -.subckt dff C=clk D=execute_to_memory_MEMORY_ENABLE Q=memory_to_writeBack_MEMORY_ENABLE -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7935 Q=decode_to_execute_REGFILE_WRITE_VALID -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7937 Q=execute_to_memory_MEMORY_ENABLE -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_VALID Q=_zz_lastStageRegFileWrite_valid -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7931 Q=execute_to_memory_REGFILE_WRITE_VALID -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7929 Q=dBus_cmd_payload_wr -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7927 Q=execute_to_memory_MEMORY_STORE -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7925 Q=decode_to_execute_IS_CSR -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7923 Q=_zz_execute_ENV_CTRL -.subckt dff C=clk D=_zz_memory_ENV_CTRL Q=_zz_writeBack_ENV_CTRL -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7921 Q=_zz_memory_ENV_CTRL -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7313 Q=_zz_execute_ALU_CTRL[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7919 Q=_zz_execute_ALU_CTRL[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7917 Q=decode_to_execute_SRC_LESS_UNSIGNED -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7311 Q=_zz_execute_ALU_BITWISE_CTRL[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7915 Q=_zz_execute_ALU_BITWISE_CTRL[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7309 Q=_zz_execute_SHIFT_CTRL[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7913 Q=_zz_execute_SHIFT_CTRL[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7307 Q=_zz_execute_BRANCH_CTRL[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7911 Q=_zz_execute_BRANCH_CTRL[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7305 Q=decode_to_execute_RS1[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7303 Q=decode_to_execute_RS1[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7301 Q=decode_to_execute_RS1[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7299 Q=decode_to_execute_RS1[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7297 Q=decode_to_execute_RS1[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7295 Q=decode_to_execute_RS1[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7293 Q=decode_to_execute_RS1[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7291 Q=decode_to_execute_RS1[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7289 Q=decode_to_execute_RS1[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7287 Q=decode_to_execute_RS1[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7285 Q=decode_to_execute_RS1[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7283 Q=decode_to_execute_RS1[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7281 Q=decode_to_execute_RS1[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7279 Q=decode_to_execute_RS1[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7277 Q=decode_to_execute_RS1[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7275 Q=decode_to_execute_RS1[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7273 Q=decode_to_execute_RS1[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7271 Q=decode_to_execute_RS1[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7269 Q=decode_to_execute_RS1[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7267 Q=decode_to_execute_RS1[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7265 Q=decode_to_execute_RS1[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7263 Q=decode_to_execute_RS1[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7261 Q=decode_to_execute_RS1[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7259 Q=decode_to_execute_RS1[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7257 Q=decode_to_execute_RS1[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7255 Q=decode_to_execute_RS1[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7253 Q=decode_to_execute_RS1[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7251 Q=decode_to_execute_RS1[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7249 Q=decode_to_execute_RS1[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7247 Q=decode_to_execute_RS1[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7245 Q=decode_to_execute_RS1[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7909 Q=decode_to_execute_RS1[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7243 Q=dBus_cmd_payload_data[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7241 Q=dBus_cmd_payload_data[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7239 Q=dBus_cmd_payload_data[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7237 Q=dBus_cmd_payload_data[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7235 Q=dBus_cmd_payload_data[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7233 Q=dBus_cmd_payload_data[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7231 Q=dBus_cmd_payload_data[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7229 Q=dBus_cmd_payload_data[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7227 Q=decode_to_execute_RS2[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7225 Q=decode_to_execute_RS2[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7223 Q=decode_to_execute_RS2[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7221 Q=decode_to_execute_RS2[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7219 Q=decode_to_execute_RS2[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7217 Q=decode_to_execute_RS2[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7215 Q=decode_to_execute_RS2[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7213 Q=decode_to_execute_RS2[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7211 Q=decode_to_execute_RS2[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7209 Q=decode_to_execute_RS2[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7207 Q=decode_to_execute_RS2[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7205 Q=decode_to_execute_RS2[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7203 Q=decode_to_execute_RS2[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7201 Q=decode_to_execute_RS2[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7199 Q=decode_to_execute_RS2[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7197 Q=decode_to_execute_RS2[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7195 Q=decode_to_execute_RS2[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7193 Q=decode_to_execute_RS2[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7191 Q=decode_to_execute_RS2[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7189 Q=decode_to_execute_RS2[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7187 Q=decode_to_execute_RS2[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7185 Q=decode_to_execute_RS2[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7183 Q=decode_to_execute_RS2[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7907 Q=decode_to_execute_RS2[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7905 Q=decode_to_execute_SRC2_FORCE_ZERO -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7181 Q=decode_to_execute_SRC2[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7179 Q=decode_to_execute_SRC2[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7177 Q=decode_to_execute_SRC2[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7175 Q=decode_to_execute_SRC2[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7173 Q=decode_to_execute_SRC2[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7171 Q=decode_to_execute_SRC2[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7169 Q=decode_to_execute_SRC2[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7167 Q=decode_to_execute_SRC2[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7165 Q=decode_to_execute_SRC2[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7163 Q=decode_to_execute_SRC2[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7161 Q=decode_to_execute_SRC2[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7159 Q=decode_to_execute_SRC2[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7157 Q=decode_to_execute_SRC2[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7155 Q=decode_to_execute_SRC2[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7153 Q=decode_to_execute_SRC2[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7151 Q=decode_to_execute_SRC2[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7149 Q=decode_to_execute_SRC2[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7147 Q=decode_to_execute_SRC2[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7145 Q=decode_to_execute_SRC2[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7143 Q=decode_to_execute_SRC2[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7141 Q=decode_to_execute_SRC2[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7139 Q=decode_to_execute_SRC2[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7137 Q=decode_to_execute_SRC2[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7135 Q=decode_to_execute_SRC2[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7133 Q=decode_to_execute_SRC2[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7131 Q=decode_to_execute_SRC2[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7129 Q=decode_to_execute_SRC2[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7127 Q=decode_to_execute_SRC2[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7125 Q=decode_to_execute_SRC2[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7123 Q=decode_to_execute_SRC2[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7121 Q=decode_to_execute_SRC2[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7903 Q=decode_to_execute_SRC2[31] -.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[0] -.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7119 Q=execute_to_memory_MEMORY_ADDRESS_LOW[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7901 Q=execute_to_memory_MEMORY_ADDRESS_LOW[1] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[0] Q=memory_to_writeBack_REGFILE_WRITE_DATA[0] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[1] Q=memory_to_writeBack_REGFILE_WRITE_DATA[1] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[2] Q=memory_to_writeBack_REGFILE_WRITE_DATA[2] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[3] Q=memory_to_writeBack_REGFILE_WRITE_DATA[3] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[4] Q=memory_to_writeBack_REGFILE_WRITE_DATA[4] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[5] Q=memory_to_writeBack_REGFILE_WRITE_DATA[5] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[6] Q=memory_to_writeBack_REGFILE_WRITE_DATA[6] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[7] Q=memory_to_writeBack_REGFILE_WRITE_DATA[7] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[8] Q=memory_to_writeBack_REGFILE_WRITE_DATA[8] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[9] Q=memory_to_writeBack_REGFILE_WRITE_DATA[9] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[10] Q=memory_to_writeBack_REGFILE_WRITE_DATA[10] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[11] Q=memory_to_writeBack_REGFILE_WRITE_DATA[11] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[12] Q=memory_to_writeBack_REGFILE_WRITE_DATA[12] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[13] Q=memory_to_writeBack_REGFILE_WRITE_DATA[13] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[14] Q=memory_to_writeBack_REGFILE_WRITE_DATA[14] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[15] Q=memory_to_writeBack_REGFILE_WRITE_DATA[15] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[16] Q=memory_to_writeBack_REGFILE_WRITE_DATA[16] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[17] Q=memory_to_writeBack_REGFILE_WRITE_DATA[17] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[18] Q=memory_to_writeBack_REGFILE_WRITE_DATA[18] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[19] Q=memory_to_writeBack_REGFILE_WRITE_DATA[19] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[20] Q=memory_to_writeBack_REGFILE_WRITE_DATA[20] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[21] Q=memory_to_writeBack_REGFILE_WRITE_DATA[21] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[22] Q=memory_to_writeBack_REGFILE_WRITE_DATA[22] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[23] Q=memory_to_writeBack_REGFILE_WRITE_DATA[23] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[24] Q=memory_to_writeBack_REGFILE_WRITE_DATA[24] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[25] Q=memory_to_writeBack_REGFILE_WRITE_DATA[25] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[26] Q=memory_to_writeBack_REGFILE_WRITE_DATA[26] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[27] Q=memory_to_writeBack_REGFILE_WRITE_DATA[27] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[28] Q=memory_to_writeBack_REGFILE_WRITE_DATA[28] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[29] Q=memory_to_writeBack_REGFILE_WRITE_DATA[29] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[30] Q=memory_to_writeBack_REGFILE_WRITE_DATA[30] -.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[31] Q=memory_to_writeBack_REGFILE_WRITE_DATA[31] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7897 Q=execute_to_memory_BRANCH_DO -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7117 Q=execute_to_memory_REGFILE_WRITE_DATA[0] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7115 Q=execute_to_memory_REGFILE_WRITE_DATA[1] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7113 Q=execute_to_memory_REGFILE_WRITE_DATA[2] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7111 Q=execute_to_memory_REGFILE_WRITE_DATA[3] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7109 Q=execute_to_memory_REGFILE_WRITE_DATA[4] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7107 Q=execute_to_memory_REGFILE_WRITE_DATA[5] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7105 Q=execute_to_memory_REGFILE_WRITE_DATA[6] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7103 Q=execute_to_memory_REGFILE_WRITE_DATA[7] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7101 Q=execute_to_memory_REGFILE_WRITE_DATA[8] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7099 Q=execute_to_memory_REGFILE_WRITE_DATA[9] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7097 Q=execute_to_memory_REGFILE_WRITE_DATA[10] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7095 Q=execute_to_memory_REGFILE_WRITE_DATA[11] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7093 Q=execute_to_memory_REGFILE_WRITE_DATA[12] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7091 Q=execute_to_memory_REGFILE_WRITE_DATA[13] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7089 Q=execute_to_memory_REGFILE_WRITE_DATA[14] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7087 Q=execute_to_memory_REGFILE_WRITE_DATA[15] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7085 Q=execute_to_memory_REGFILE_WRITE_DATA[16] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7083 Q=execute_to_memory_REGFILE_WRITE_DATA[17] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7081 Q=execute_to_memory_REGFILE_WRITE_DATA[18] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7079 Q=execute_to_memory_REGFILE_WRITE_DATA[19] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7077 Q=execute_to_memory_REGFILE_WRITE_DATA[20] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7075 Q=execute_to_memory_REGFILE_WRITE_DATA[21] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7073 Q=execute_to_memory_REGFILE_WRITE_DATA[22] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7071 Q=execute_to_memory_REGFILE_WRITE_DATA[23] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7069 Q=execute_to_memory_REGFILE_WRITE_DATA[24] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7067 Q=execute_to_memory_REGFILE_WRITE_DATA[25] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7065 Q=execute_to_memory_REGFILE_WRITE_DATA[26] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7063 Q=execute_to_memory_REGFILE_WRITE_DATA[27] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7061 Q=execute_to_memory_REGFILE_WRITE_DATA[28] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7059 Q=execute_to_memory_REGFILE_WRITE_DATA[29] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7057 Q=execute_to_memory_REGFILE_WRITE_DATA[30] -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7899 Q=execute_to_memory_REGFILE_WRITE_DATA[31] -.subckt dff C=clk D=dBus_rsp_data[0] Q=memory_to_writeBack_MEMORY_READ_DATA[0] -.subckt dff C=clk D=dBus_rsp_data[1] Q=memory_to_writeBack_MEMORY_READ_DATA[1] -.subckt dff C=clk D=dBus_rsp_data[2] Q=memory_to_writeBack_MEMORY_READ_DATA[2] -.subckt dff C=clk D=dBus_rsp_data[3] Q=memory_to_writeBack_MEMORY_READ_DATA[3] -.subckt dff C=clk D=dBus_rsp_data[4] Q=memory_to_writeBack_MEMORY_READ_DATA[4] -.subckt dff C=clk D=dBus_rsp_data[5] Q=memory_to_writeBack_MEMORY_READ_DATA[5] -.subckt dff C=clk D=dBus_rsp_data[6] Q=memory_to_writeBack_MEMORY_READ_DATA[6] -.subckt dff C=clk D=dBus_rsp_data[7] Q=memory_to_writeBack_MEMORY_READ_DATA[7] -.subckt dff C=clk D=dBus_rsp_data[8] Q=memory_to_writeBack_MEMORY_READ_DATA[8] -.subckt dff C=clk D=dBus_rsp_data[9] Q=memory_to_writeBack_MEMORY_READ_DATA[9] -.subckt dff C=clk D=dBus_rsp_data[10] Q=memory_to_writeBack_MEMORY_READ_DATA[10] -.subckt dff C=clk D=dBus_rsp_data[11] Q=memory_to_writeBack_MEMORY_READ_DATA[11] -.subckt dff C=clk D=dBus_rsp_data[12] Q=memory_to_writeBack_MEMORY_READ_DATA[12] -.subckt dff C=clk D=dBus_rsp_data[13] Q=memory_to_writeBack_MEMORY_READ_DATA[13] -.subckt dff C=clk D=dBus_rsp_data[14] Q=memory_to_writeBack_MEMORY_READ_DATA[14] -.subckt dff C=clk D=dBus_rsp_data[15] Q=memory_to_writeBack_MEMORY_READ_DATA[15] -.subckt dff C=clk D=dBus_rsp_data[16] Q=memory_to_writeBack_MEMORY_READ_DATA[16] -.subckt dff C=clk D=dBus_rsp_data[17] Q=memory_to_writeBack_MEMORY_READ_DATA[17] -.subckt dff C=clk D=dBus_rsp_data[18] Q=memory_to_writeBack_MEMORY_READ_DATA[18] -.subckt dff C=clk D=dBus_rsp_data[19] Q=memory_to_writeBack_MEMORY_READ_DATA[19] -.subckt dff C=clk D=dBus_rsp_data[20] Q=writeBack_MEMORY_READ_DATA[20] -.subckt dff C=clk D=dBus_rsp_data[21] Q=writeBack_MEMORY_READ_DATA[21] -.subckt dff C=clk D=dBus_rsp_data[22] Q=writeBack_MEMORY_READ_DATA[22] -.subckt dff C=clk D=dBus_rsp_data[23] Q=writeBack_MEMORY_READ_DATA[23] -.subckt dff C=clk D=dBus_rsp_data[24] Q=writeBack_MEMORY_READ_DATA[24] -.subckt dff C=clk D=dBus_rsp_data[25] Q=writeBack_MEMORY_READ_DATA[25] -.subckt dff C=clk D=dBus_rsp_data[26] Q=writeBack_MEMORY_READ_DATA[26] -.subckt dff C=clk D=dBus_rsp_data[27] Q=writeBack_MEMORY_READ_DATA[27] -.subckt dff C=clk D=dBus_rsp_data[28] Q=writeBack_MEMORY_READ_DATA[28] -.subckt dff C=clk D=dBus_rsp_data[29] Q=writeBack_MEMORY_READ_DATA[29] -.subckt dff C=clk D=dBus_rsp_data[30] Q=writeBack_MEMORY_READ_DATA[30] -.subckt dff C=clk D=dBus_rsp_data[31] Q=writeBack_MEMORY_READ_DATA[31] -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7055 Q=IBusSimplePlugin_fetchPc_pcReg[2] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7053 Q=IBusSimplePlugin_fetchPc_pcReg[3] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7051 Q=IBusSimplePlugin_fetchPc_pcReg[4] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7049 Q=IBusSimplePlugin_fetchPc_pcReg[5] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7047 Q=IBusSimplePlugin_fetchPc_pcReg[6] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7045 Q=IBusSimplePlugin_fetchPc_pcReg[7] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7043 Q=IBusSimplePlugin_fetchPc_pcReg[8] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7041 Q=IBusSimplePlugin_fetchPc_pcReg[9] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7039 Q=IBusSimplePlugin_fetchPc_pcReg[10] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7037 Q=IBusSimplePlugin_fetchPc_pcReg[11] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7035 Q=IBusSimplePlugin_fetchPc_pcReg[12] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7033 Q=IBusSimplePlugin_fetchPc_pcReg[13] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7031 Q=IBusSimplePlugin_fetchPc_pcReg[14] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7029 Q=IBusSimplePlugin_fetchPc_pcReg[15] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7027 Q=IBusSimplePlugin_fetchPc_pcReg[16] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7025 Q=IBusSimplePlugin_fetchPc_pcReg[17] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7023 Q=IBusSimplePlugin_fetchPc_pcReg[18] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7021 Q=IBusSimplePlugin_fetchPc_pcReg[19] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7019 Q=IBusSimplePlugin_fetchPc_pcReg[20] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7017 Q=IBusSimplePlugin_fetchPc_pcReg[21] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7015 Q=IBusSimplePlugin_fetchPc_pcReg[22] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7013 Q=IBusSimplePlugin_fetchPc_pcReg[23] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7011 Q=IBusSimplePlugin_fetchPc_pcReg[24] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7009 Q=IBusSimplePlugin_fetchPc_pcReg[25] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7007 Q=IBusSimplePlugin_fetchPc_pcReg[26] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7005 Q=IBusSimplePlugin_fetchPc_pcReg[27] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7003 Q=IBusSimplePlugin_fetchPc_pcReg[28] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7001 Q=IBusSimplePlugin_fetchPc_pcReg[29] R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$6999 Q=IBusSimplePlugin_fetchPc_pcReg[30] R=reset -.subckt dffs C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7967 Q=IBusSimplePlugin_fetchPc_pcReg[31] S=reset -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7893 Q=execute_CsrPlugin_csr_768 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7891 Q=execute_CsrPlugin_csr_836 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7889 Q=execute_CsrPlugin_csr_772 -.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7887 Q=execute_CsrPlugin_csr_834 -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7885 Q=execute_arbitration_isValid R=reset -.subckt dffr C=clk D=$0\writeBack_arbitration_isValid[0:0] Q=lastStageIsFiring R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7883 Q=memory_arbitration_isValid R=reset -.subckt dffr C=clk D=$true Q=IBusSimplePlugin_fetchPc_booted R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7881 Q=IBusSimplePlugin_fetchPc_inc R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7879 Q=IBusSimplePlugin_iBusRsp_stages_1_input_valid R=reset -.subckt dffr C=clk D=IBusSimplePlugin_pending_next[0] Q=IBusSimplePlugin_pending_value[0] R=reset -.subckt dffr C=clk D=IBusSimplePlugin_pending_next[1] Q=IBusSimplePlugin_pending_value[1] R=reset -.subckt dffr C=clk D=IBusSimplePlugin_pending_next[2] Q=IBusSimplePlugin_pending_value[2] R=reset -.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=reset -.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=reset -.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=reset -.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset -.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset -.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset -.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7877 Q=IBusSimplePlugin_injector_decodeInput_valid R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7875 Q=CsrPlugin_mie_MEIE R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7873 Q=CsrPlugin_mie_MTIE R=reset -.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7871 Q=CsrPlugin_mie_MSIE R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7869 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7867 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset -.subckt dffs C=clk D=$false Q=_zz_5 S=reset -.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7865 Q=CsrPlugin_pipelineLiberator_done R=reset -.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2203[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2203[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2203[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2203[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2204[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2204[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2204[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2204[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 -.names $false BranchPlugin_jumpInterface_payload[0] -1 1 -.names $true CsrPlugin_interrupt_code[0] -1 1 -.names $true CsrPlugin_interrupt_code[1] -1 1 -.names $true CsrPlugin_mcause_exceptionCode[0] -1 1 -.names $true CsrPlugin_mcause_exceptionCode[1] -1 1 -.names $false CsrPlugin_mepc[0] -1 1 -.names $false CsrPlugin_mepc[1] -1 1 -.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$2203[0] -1 1 -.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$2203[1] -1 1 -.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$2203[2] -1 1 -.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$2203[3] -1 1 -.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$2203[4] -1 1 -.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$2203[5] -1 1 -.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$2203[6] -1 1 -.names _zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$2203[7] -1 1 -.names _zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$2203[8] -1 1 -.names _zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$2203[9] -1 1 -.names _zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$2203[10] -1 1 -.names _zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$2203[11] -1 1 -.names _zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$2203[12] -1 1 -.names _zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$2203[13] -1 1 -.names _zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$2203[14] -1 1 -.names _zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$2203[15] -1 1 -.names _zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$2203[16] -1 1 -.names _zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$2203[17] -1 1 -.names _zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$2203[18] -1 1 -.names _zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$2203[19] -1 1 -.names _zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$2203[20] -1 1 -.names _zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$2203[21] -1 1 -.names _zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$2203[22] -1 1 -.names _zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$2203[23] -1 1 -.names _zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$2203[24] -1 1 -.names _zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$2203[25] -1 1 -.names _zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$2203[26] -1 1 -.names _zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$2203[27] -1 1 -.names _zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$2203[28] -1 1 -.names _zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$2203[29] -1 1 -.names _zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$2203[30] -1 1 -.names _zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$2203[31] -1 1 -.names _zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$2204[0] -1 1 -.names _zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$2204[1] -1 1 -.names _zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$2204[2] -1 1 -.names _zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$2204[3] -1 1 -.names _zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$2204[4] -1 1 -.names _zz_RegFilePlugin_regFile_port0[5] $auto$memory_bram.cc:844:replace_memory$2204[5] -1 1 -.names _zz_RegFilePlugin_regFile_port0[6] $auto$memory_bram.cc:844:replace_memory$2204[6] -1 1 -.names _zz_RegFilePlugin_regFile_port0[7] $auto$memory_bram.cc:844:replace_memory$2204[7] -1 1 -.names _zz_RegFilePlugin_regFile_port0[8] $auto$memory_bram.cc:844:replace_memory$2204[8] -1 1 -.names _zz_RegFilePlugin_regFile_port0[9] $auto$memory_bram.cc:844:replace_memory$2204[9] -1 1 -.names _zz_RegFilePlugin_regFile_port0[10] $auto$memory_bram.cc:844:replace_memory$2204[10] -1 1 -.names _zz_RegFilePlugin_regFile_port0[11] $auto$memory_bram.cc:844:replace_memory$2204[11] -1 1 -.names _zz_RegFilePlugin_regFile_port0[12] $auto$memory_bram.cc:844:replace_memory$2204[12] -1 1 -.names _zz_RegFilePlugin_regFile_port0[13] $auto$memory_bram.cc:844:replace_memory$2204[13] -1 1 -.names _zz_RegFilePlugin_regFile_port0[14] $auto$memory_bram.cc:844:replace_memory$2204[14] -1 1 -.names _zz_RegFilePlugin_regFile_port0[15] $auto$memory_bram.cc:844:replace_memory$2204[15] -1 1 -.names _zz_RegFilePlugin_regFile_port0[16] $auto$memory_bram.cc:844:replace_memory$2204[16] -1 1 -.names _zz_RegFilePlugin_regFile_port0[17] $auto$memory_bram.cc:844:replace_memory$2204[17] -1 1 -.names _zz_RegFilePlugin_regFile_port0[18] $auto$memory_bram.cc:844:replace_memory$2204[18] -1 1 -.names _zz_RegFilePlugin_regFile_port0[19] $auto$memory_bram.cc:844:replace_memory$2204[19] -1 1 -.names _zz_RegFilePlugin_regFile_port0[20] $auto$memory_bram.cc:844:replace_memory$2204[20] -1 1 -.names _zz_RegFilePlugin_regFile_port0[21] $auto$memory_bram.cc:844:replace_memory$2204[21] -1 1 -.names _zz_RegFilePlugin_regFile_port0[22] $auto$memory_bram.cc:844:replace_memory$2204[22] -1 1 -.names _zz_RegFilePlugin_regFile_port0[23] $auto$memory_bram.cc:844:replace_memory$2204[23] -1 1 -.names _zz_RegFilePlugin_regFile_port0[24] $auto$memory_bram.cc:844:replace_memory$2204[24] -1 1 -.names _zz_RegFilePlugin_regFile_port0[25] $auto$memory_bram.cc:844:replace_memory$2204[25] -1 1 -.names _zz_RegFilePlugin_regFile_port0[26] $auto$memory_bram.cc:844:replace_memory$2204[26] -1 1 -.names _zz_RegFilePlugin_regFile_port0[27] $auto$memory_bram.cc:844:replace_memory$2204[27] -1 1 -.names _zz_RegFilePlugin_regFile_port0[28] $auto$memory_bram.cc:844:replace_memory$2204[28] -1 1 -.names _zz_RegFilePlugin_regFile_port0[29] $auto$memory_bram.cc:844:replace_memory$2204[29] -1 1 -.names _zz_RegFilePlugin_regFile_port0[30] $auto$memory_bram.cc:844:replace_memory$2204[30] -1 1 -.names _zz_RegFilePlugin_regFile_port0[31] $auto$memory_bram.cc:844:replace_memory$2204[31] -1 1 -.names $false IBusSimplePlugin_fetchPc_pcReg[0] -1 1 -.names $false IBusSimplePlugin_fetchPc_pcReg[1] -1 1 -.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[0] -1 1 -.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[1] -1 1 -.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] -1 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] -1 1 -.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] -1 1 -.names _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] -1 1 -.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[11] -1 1 -.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[12] -1 1 -.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[19] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[4] _zz__zz_execute_BranchPlugin_branch_src2_4[4] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2_4[5] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[6] _zz__zz_execute_BranchPlugin_branch_src2_4[6] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2_4[7] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[8] _zz__zz_execute_BranchPlugin_branch_src2_4[8] -1 1 -.names _zz__zz_execute_BranchPlugin_branch_src2[9] _zz__zz_execute_BranchPlugin_branch_src2_4[9] -1 1 -.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_4[11] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_lastStageRegFileWrite_payload_address[7] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_lastStageRegFileWrite_payload_address[8] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_lastStageRegFileWrite_payload_address[9] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_lastStageRegFileWrite_payload_address[10] -1 1 -.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_lastStageRegFileWrite_payload_address[11] -1 1 -.names switch_Misc_l241_1 dBus_cmd_payload_size[1] -1 1 -.names $false decode_to_execute_PC[0] -1 1 -.names $false decode_to_execute_PC[1] -1 1 -.names dBus_cmd_payload_data[0] decode_to_execute_RS2[0] -1 1 -.names dBus_cmd_payload_data[1] decode_to_execute_RS2[1] -1 1 -.names dBus_cmd_payload_data[2] decode_to_execute_RS2[2] -1 1 -.names dBus_cmd_payload_data[3] decode_to_execute_RS2[3] -1 1 -.names dBus_cmd_payload_data[4] decode_to_execute_RS2[4] -1 1 -.names dBus_cmd_payload_data[5] decode_to_execute_RS2[5] -1 1 -.names dBus_cmd_payload_data[6] decode_to_execute_RS2[6] -1 1 -.names dBus_cmd_payload_data[7] decode_to_execute_RS2[7] -1 1 -.names $false iBus_cmd_payload_pc[0] -1 1 -.names $false iBus_cmd_payload_pc[1] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[0] writeBack_MEMORY_READ_DATA[0] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[1] writeBack_MEMORY_READ_DATA[1] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[2] writeBack_MEMORY_READ_DATA[2] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[3] writeBack_MEMORY_READ_DATA[3] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[4] writeBack_MEMORY_READ_DATA[4] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[5] writeBack_MEMORY_READ_DATA[5] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[6] writeBack_MEMORY_READ_DATA[6] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[7] writeBack_MEMORY_READ_DATA[7] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[8] writeBack_MEMORY_READ_DATA[8] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[9] writeBack_MEMORY_READ_DATA[9] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[10] writeBack_MEMORY_READ_DATA[10] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[11] writeBack_MEMORY_READ_DATA[11] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[12] writeBack_MEMORY_READ_DATA[12] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[13] writeBack_MEMORY_READ_DATA[13] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[14] writeBack_MEMORY_READ_DATA[14] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[15] writeBack_MEMORY_READ_DATA[15] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[16] writeBack_MEMORY_READ_DATA[16] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[17] writeBack_MEMORY_READ_DATA[17] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[18] writeBack_MEMORY_READ_DATA[18] -1 1 -.names memory_to_writeBack_MEMORY_READ_DATA[19] writeBack_MEMORY_READ_DATA[19] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif deleted file mode 100644 index 66d55f64118..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif +++ /dev/null @@ -1,1473 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model boxcar -.inputs i_clk i_reset i_navg[0] i_navg[1] i_navg[2] i_navg[3] i_navg[4] i_navg[5] i_ce i_sample[0] i_sample[1] i_sample[2] i_sample[3] i_sample[4] i_sample[5] i_sample[6] i_sample[7] i_sample[8] i_sample[9] i_sample[10] i_sample[11] i_sample[12] i_sample[13] i_sample[14] i_sample[15] -.outputs o_result[0] o_result[1] o_result[2] o_result[3] o_result[4] o_result[5] o_result[6] o_result[7] o_result[8] o_result[9] o_result[10] o_result[11] o_result[12] o_result[13] o_result[14] o_result[15] o_result[16] o_result[17] o_result[18] o_result[19] o_result[20] o_result[21] -.names $false -.names $true -1 -.names $undef -.names wraddr[4] $abc$1868$new_n225 $abc$1868$auto$rtlil.cc:2693:MuxGate$1509 -01 1 -10 1 -.names wraddr[0] wraddr[1] wraddr[2] wraddr[3] i_ce $abc$1868$new_n225 -11111 1 -.names wraddr[3] wraddr[0] wraddr[1] wraddr[2] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1511 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names wraddr[2] wraddr[0] wraddr[1] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1513 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names wraddr[1] wraddr[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1515 -011 1 -100 1 -101 1 -110 1 -.names wraddr[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1517 -01 1 -10 1 -.names i_ce i_sample[14] preval[14] $abc$1868$auto$rtlil.cc:2693:MuxGate$1519 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[13] preval[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1521 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[12] preval[12] $abc$1868$auto$rtlil.cc:2693:MuxGate$1523 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[11] preval[11] $abc$1868$auto$rtlil.cc:2693:MuxGate$1525 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[10] preval[10] $abc$1868$auto$rtlil.cc:2693:MuxGate$1527 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[9] preval[9] $abc$1868$auto$rtlil.cc:2693:MuxGate$1529 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[8] preval[8] $abc$1868$auto$rtlil.cc:2693:MuxGate$1531 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[7] preval[7] $abc$1868$auto$rtlil.cc:2693:MuxGate$1533 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[6] preval[6] $abc$1868$auto$rtlil.cc:2693:MuxGate$1535 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[5] preval[5] $abc$1868$auto$rtlil.cc:2693:MuxGate$1537 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[4] preval[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1539 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[3] preval[3] $abc$1868$auto$rtlil.cc:2693:MuxGate$1541 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[2] preval[2] $abc$1868$auto$rtlil.cc:2693:MuxGate$1543 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[1] preval[1] $abc$1868$auto$rtlil.cc:2693:MuxGate$1545 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_sample[0] preval[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1547 -001 1 -011 1 -110 1 -111 1 -.names i_ce acc[20] o_result[20] $abc$1868$auto$rtlil.cc:2693:MuxGate$1549 -001 1 -011 1 -110 1 -111 1 -.names i_ce acc[19] o_result[19] $abc$1868$auto$rtlil.cc:2693:MuxGate$1551 -001 1 -011 1 -110 1 -111 1 -.names i_ce acc[18] o_result[18] $abc$1868$auto$rtlil.cc:2693:MuxGate$1553 -001 1 -011 1 -110 1 -111 1 -.names i_ce acc[17] o_result[17] $abc$1868$auto$rtlil.cc:2693:MuxGate$1555 -001 1 -011 1 -110 1 -111 1 -.names i_ce acc[16] o_result[16] $abc$1868$auto$rtlil.cc:2693:MuxGate$1557 -001 1 -011 1 -110 1 -111 1 -.names i_ce acc[15] o_result[15] $abc$1868$auto$rtlil.cc:2693:MuxGate$1559 -001 1 -011 1 -110 1 -111 1 -.names i_ce acc[14] o_result[14] $abc$1868$auto$rtlil.cc:2693:MuxGate$1561 -001 1 -011 1 -110 1 -111 1 -.names i_ce acc[13] o_result[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1563 -001 1 -011 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acc[13] sub[13] $abc$1868$new_n340 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1637 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names sub[12] acc[12] $abc$1868$new_n326 $abc$1868$new_n340 -000 1 -001 1 -011 1 -101 1 -.names acc[12] sub[12] $abc$1868$new_n326 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1639 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names acc[11] sub[11] $abc$1868$new_n343 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1641 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names sub[10] acc[10] $abc$1868$new_n327 $abc$1868$new_n343 -000 1 -001 1 -011 1 -101 1 -.names acc[10] sub[10] $abc$1868$new_n327 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1643 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names acc[9] sub[9] $abc$1868$new_n346 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1645 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names sub[8] acc[8] $abc$1868$new_n328 $abc$1868$new_n346 -000 1 -001 1 -011 1 -101 1 -.names acc[8] sub[8] $abc$1868$new_n328 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1647 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names acc[7] sub[7] $abc$1868$new_n349 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1649 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names sub[6] acc[6] $abc$1868$new_n329 $abc$1868$new_n349 -000 1 -001 1 -011 1 -101 1 -.names acc[6] sub[6] $abc$1868$new_n329 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1651 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names acc[5] sub[5] $abc$1868$new_n352 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1653 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names sub[4] acc[4] $abc$1868$new_n330 $abc$1868$new_n352 -000 1 -001 1 -011 1 -101 1 -.names acc[4] sub[4] $abc$1868$new_n330 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1655 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names acc[3] sub[3] $abc$1868$new_n355 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1657 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names sub[2] acc[2] $abc$1868$new_n331 $abc$1868$new_n355 -000 1 -001 1 -011 1 -101 1 -.names acc[2] sub[2] $abc$1868$new_n331 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1659 -0001 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names acc[1] sub[1] sub[0] acc[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1661 -00111 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names acc[0] sub[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1663 -011 1 -100 1 -101 1 -110 1 -.names i_reset rdaddr[4] $abc$1868$new_n360 $abc$1868$new_n363 $abc$1868$auto$rtlil.cc:2693:MuxGate$1665 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names rdaddr[3] i_ce $abc$1868$new_n361 $abc$1868$new_n360 -111 1 -.names rdaddr[2] $abc$1868$new_n362 $abc$1868$new_n361 -11 1 -.names rdaddr[0] rdaddr[1] $abc$1868$new_n362 -11 1 -.names i_navg[4] i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n363 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -.names i_reset rdaddr[3] i_ce $abc$1868$new_n361 $abc$1868$new_n365 $abc$1868$auto$rtlil.cc:2693:MuxGate$1667 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n365 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names i_reset rdaddr[2] i_ce $abc$1868$new_n362 $abc$1868$new_n367 $abc$1868$auto$rtlil.cc:2693:MuxGate$1669 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n367 -001 1 -010 1 -011 1 -100 1 -.names rdaddr[1] $abc$1868$new_n369 rdaddr[0] i_ce i_reset $abc$1868$auto$rtlil.cc:2693:MuxGate$1671 -00110 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_reset i_navg[1] i_navg[0] $abc$1868$new_n369 -101 1 -110 1 -.names i_reset rdaddr[0] i_ce i_navg[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1673 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names i_reset rdaddr[5] i_ce $abc$1868$new_n372 $abc$1868$new_n373 $abc$1868$auto$rtlil.cc:2693:MuxGate$1675 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names rdaddr[3] rdaddr[4] $abc$1868$new_n361 $abc$1868$new_n372 -111 1 -.names i_navg[5] $abc$1868$new_n374 $abc$1868$new_n373 -01 1 -10 1 -.names i_navg[4] i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n374 -00000 1 -.names i_ce acc[21] o_result[21] $abc$1868$auto$rtlil.cc:2693:MuxGate$1677 -001 1 -011 1 -110 1 -111 1 -.names acc[21] acc[18] acc[19] acc[20] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1679 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names i_ce sub[16] $abc$1868$new_n379 $abc$1868$new_n378 $abc$1868$auto$rtlil.cc:2693:MuxGate$1681 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$1868$new_n288 preval[14] $abc$1868$new_n287 $abc$1868$new_n268 $abc$1868$new_n378 -1001 1 -1100 1 -1101 1 -1111 1 -.names full preval[15] $abc$1868$auto$mem.cc:1434:emulate_reset$545[15] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n379 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names full $abc$1868$new_n381 i_ce rdaddr[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1683 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names rdaddr[5] rdaddr[0] rdaddr[1] rdaddr[2] rdaddr[3] $abc$1868$new_n381 -00000 1 -.names i_ce i_sample[15] preval[15] $abc$1868$auto$rtlil.cc:2693:MuxGate$1685 -001 1 -011 1 -110 1 -111 1 -.names wraddr[5] wraddr[4] $abc$1868$new_n225 $abc$1868$auto$rtlil.cc:2693:MuxGate$1687 -011 1 -100 1 -101 1 -110 1 -.names $auto$mem.cc:1432:emulate_reset$543 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1689 -01 1 -10 1 -11 1 -.names $abc$1868$new_n284 $abc$1868$new_n269 preval[12] $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n385 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_ce preval[13] full $abc$1868$new_n385 sub[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1595 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[11] $abc$1868$new_n270 preval[10] $abc$1868$auto$mem.cc:1434:emulate_reset$545[10] $abc$1868$new_n387 -00100 1 -00101 1 -01100 1 -01101 1 -10001 1 -10100 1 -10101 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -.names i_ce preval[11] full $abc$1868$new_n387 sub[11] $abc$1868$auto$rtlil.cc:2693:MuxGate$1599 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[9] $abc$1868$new_n271 preval[8] $abc$1868$auto$mem.cc:1434:emulate_reset$545[8] $abc$1868$new_n389 -00000 1 -00001 1 -01000 1 -01001 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names i_ce preval[9] full $abc$1868$new_n389 sub[9] $abc$1868$auto$rtlil.cc:2693:MuxGate$1603 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1673 Q=rdaddr[0] -.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1671 Q=rdaddr[1] -.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1669 Q=rdaddr[2] -.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1667 Q=rdaddr[3] -.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1665 Q=rdaddr[4] -.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1675 Q=rdaddr[5] -.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1689 Q=$auto$mem.cc:1432:emulate_reset$543 -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1663 Q=acc[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1661 Q=acc[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1659 Q=acc[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1657 Q=acc[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1655 Q=acc[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1653 Q=acc[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1651 Q=acc[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1649 Q=acc[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1647 Q=acc[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1645 Q=acc[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1643 Q=acc[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1641 Q=acc[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1639 Q=acc[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1637 Q=acc[13] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1635 Q=acc[14] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1633 Q=acc[15] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1631 Q=acc[16] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1629 Q=acc[17] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1627 Q=acc[18] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1625 Q=acc[19] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1623 Q=acc[20] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1679 Q=acc[21] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1621 Q=sub[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1619 Q=sub[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1617 Q=sub[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1615 Q=sub[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1613 Q=sub[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1611 Q=sub[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1609 Q=sub[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1607 Q=sub[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1605 Q=sub[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1603 Q=sub[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1601 Q=sub[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1599 Q=sub[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1597 Q=sub[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1595 Q=sub[13] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1593 Q=sub[14] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1591 Q=sub[15] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1681 Q=sub[16] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1683 Q=full R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1589 Q=o_result[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1587 Q=o_result[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1585 Q=o_result[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1583 Q=o_result[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1581 Q=o_result[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1579 Q=o_result[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1577 Q=o_result[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1575 Q=o_result[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1573 Q=o_result[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1571 Q=o_result[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1569 Q=o_result[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1567 Q=o_result[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1565 Q=o_result[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1563 Q=o_result[13] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1561 Q=o_result[14] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1559 Q=o_result[15] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1557 Q=o_result[16] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1555 Q=o_result[17] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1553 Q=o_result[18] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1551 Q=o_result[19] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1549 Q=o_result[20] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1677 Q=o_result[21] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1547 Q=preval[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1545 Q=preval[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1543 Q=preval[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1541 Q=preval[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1539 Q=preval[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1537 Q=preval[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1535 Q=preval[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1533 Q=preval[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1531 Q=preval[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1529 Q=preval[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1527 Q=preval[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1525 Q=preval[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1523 Q=preval[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1521 Q=preval[13] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1519 Q=preval[14] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1685 Q=preval[15] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1517 Q=wraddr[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1515 Q=wraddr[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1513 Q=wraddr[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1511 Q=wraddr[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1509 Q=wraddr[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1687 Q=wraddr[5] R=i_reset -.subckt dpram512x18 bwen_ni[17]=$true bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[17]=i_sample[0] data_i[16]=i_sample[1] data_i[15]=i_sample[2] data_i[14]=i_sample[3] data_i[13]=i_sample[4] data_i[12]=i_sample[5] data_i[11]=i_sample[6] data_i[10]=i_sample[7] data_i[9]=i_sample[8] data_i[8]=i_sample[9] data_i[7]=i_sample[10] data_i[6]=i_sample[11] data_i[5]=i_sample[12] data_i[4]=i_sample[13] data_i[3]=i_sample[14] data_i[2]=i_sample[15] data_i[1]=$undef data_i[0]=$undef q_o[17]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[0] q_o[16]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[1] q_o[15]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[2] q_o[14]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[3] q_o[13]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[4] q_o[12]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[5] q_o[11]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[6] q_o[10]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[7] q_o[9]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[8] q_o[8]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[9] q_o[7]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[10] q_o[6]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[11] q_o[5]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[12] q_o[4]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[13] q_o[3]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[14] q_o[2]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[15] q_o[1]=$auto$memory_bram.cc:844:replace_memory$547[16] q_o[0]=$auto$memory_bram.cc:844:replace_memory$547[17] raddr_i[8]=rdaddr[0] raddr_i[7]=rdaddr[1] raddr_i[6]=rdaddr[2] raddr_i[5]=rdaddr[3] raddr_i[4]=rdaddr[4] raddr_i[3]=rdaddr[5] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=i_clk ren_ni=i_ce waddr_i[8]=wraddr[0] waddr_i[7]=wraddr[1] waddr_i[6]=wraddr[2] waddr_i[5]=wraddr[3] waddr_i[4]=wraddr[4] waddr_i[3]=wraddr[5] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=i_clk wen_ni=i_ce -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] $auto$memory_bram.cc:844:replace_memory$547[0] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[1] $auto$memory_bram.cc:844:replace_memory$547[1] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[2] $auto$memory_bram.cc:844:replace_memory$547[2] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[3] $auto$memory_bram.cc:844:replace_memory$547[3] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[4] $auto$memory_bram.cc:844:replace_memory$547[4] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[5] $auto$memory_bram.cc:844:replace_memory$547[5] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[6] $auto$memory_bram.cc:844:replace_memory$547[6] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[7] $auto$memory_bram.cc:844:replace_memory$547[7] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[8] $auto$memory_bram.cc:844:replace_memory$547[8] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[9] $auto$memory_bram.cc:844:replace_memory$547[9] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[10] $auto$memory_bram.cc:844:replace_memory$547[10] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[11] $auto$memory_bram.cc:844:replace_memory$547[11] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $auto$memory_bram.cc:844:replace_memory$547[12] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[13] $auto$memory_bram.cc:844:replace_memory$547[13] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[14] $auto$memory_bram.cc:844:replace_memory$547[14] -1 1 -.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[15] $auto$memory_bram.cc:844:replace_memory$547[15] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif deleted file mode 100644 index 5c089e7eadc..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif +++ /dev/null @@ -1,27532 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model cordic -.inputs i_clk i_reset i_ce i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_phase[0] i_phase[1] i_phase[2] i_phase[3] i_phase[4] i_phase[5] i_phase[6] i_phase[7] i_phase[8] i_phase[9] i_phase[10] i_phase[11] i_phase[12] i_phase[13] i_phase[14] i_phase[15] i_phase[16] i_phase[17] i_phase[18] i_phase[19] i_aux -.outputs o_xval[0] o_xval[1] o_xval[2] o_xval[3] o_xval[4] o_xval[5] o_xval[6] o_xval[7] o_xval[8] o_xval[9] o_xval[10] o_xval[11] o_xval[12] o_yval[0] o_yval[1] o_yval[2] o_yval[3] o_yval[4] o_yval[5] o_yval[6] o_yval[7] o_yval[8] o_yval[9] o_yval[10] o_yval[11] o_yval[12] o_aux -.names $false -.names $true -1 -.names $undef -.names i_ce ax[15] ax[14] $abc$23348$auto$rtlil.cc:2693:MuxGate$19848 -010 1 -011 1 -101 1 -111 1 -.names i_ce ax[14] ax[13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19850 -010 1 -011 1 -101 1 -111 1 -.names i_ce ax[12] ax[13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19852 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[11] ax[12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19854 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[10] ax[11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19856 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[9] ax[10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19858 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[8] ax[9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19860 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[7] ax[8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19862 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[6] ax[7] $abc$23348$auto$rtlil.cc:2693:MuxGate$19864 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[5] ax[6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19866 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[4] ax[5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19868 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[3] ax[4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19870 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[2] ax[3] $abc$23348$auto$rtlil.cc:2693:MuxGate$19872 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[1] ax[2] $abc$23348$auto$rtlil.cc:2693:MuxGate$19874 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[0] ax[1] $abc$23348$auto$rtlil.cc:2693:MuxGate$19876 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_aux ax[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19878 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[17] ph[0][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$19880 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[17] ph[0][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$19882 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[16] ph[0][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$19884 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[15] ph[0][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$19886 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[14] ph[0][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$19888 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[13] ph[0][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19890 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[12] ph[0][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19892 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[11] ph[0][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19894 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[10] ph[0][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19896 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[9] ph[0][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19898 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[8] ph[0][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19900 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[7] ph[0][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$19902 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[6] ph[0][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19904 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[5] ph[0][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19906 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[4] ph[0][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19908 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[3] ph[0][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$19910 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[2] ph[0][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$19912 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[1] ph[0][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$19914 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_phase[0] ph[0][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19916 -001 1 -011 1 -110 1 -111 1 -.names i_ce yv[0][14] $abc$23348$new_n1870 $abc$23348$new_n1874 $abc$23348$new_n1864 $abc$23348$auto$rtlil.cc:2693:MuxGate$19918 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$23348$new_n1869 i_yval[12] $abc$23348$new_n1865 $abc$23348$new_n1864 -100 1 -111 1 -.names $abc$23348$new_n1866 i_yval[11] i_yval[10] $abc$23348$new_n1865 -100 1 -.names $abc$23348$new_n1867 i_yval[9] $abc$23348$new_n1866 -10 1 -.names $abc$23348$new_n1868 i_yval[8] i_yval[7] i_yval[6] i_yval[5] $abc$23348$new_n1867 -10000 1 -.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1868 -00000 1 -.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1869 -011 1 -100 1 -.names i_xval[12] i_phase[19] $abc$23348$new_n1871 i_phase[18] i_phase[17] $abc$23348$new_n1870 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10011 1 -10100 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11111 1 -.names $abc$23348$new_n1872 i_xval[11] i_xval[10] i_xval[9] $abc$23348$new_n1871 -1000 1 -.names $abc$23348$new_n1873 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$23348$new_n1872 -10000 1 -.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1873 -00000 1 -.names i_ce $abc$23348$new_n1875 i_yval[12] $abc$23348$new_n1874 -100 1 -101 1 -110 1 -.names i_phase[18] i_phase[19] i_phase[17] $abc$23348$new_n1875 -000 1 -111 1 -.names i_ce $abc$23348$new_n1877 yv[0][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19920 -001 1 -011 1 -100 1 -101 1 -.names $abc$23348$new_n1878 $abc$23348$new_n1881 $abc$23348$new_n1880 $abc$23348$new_n1875 i_yval[11] $abc$23348$new_n1877 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names i_phase[18] i_phase[17] i_phase[19] i_xval[11] $abc$23348$new_n1879 $abc$23348$new_n1878 -00101 1 -00111 1 -01010 1 -01011 1 -10010 1 -10011 1 -11001 1 -11011 1 -.names i_yval[11] $abc$23348$new_n1866 i_yval[10] $abc$23348$new_n1879 -000 1 -001 1 -011 1 -110 1 -.names i_xval[11] $abc$23348$new_n1872 i_xval[10] i_xval[9] $abc$23348$new_n1880 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1881 -101 1 -110 1 -.names i_ce $abc$23348$new_n1883 yv[0][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19922 -001 1 -011 1 -100 1 -101 1 -.names $abc$23348$new_n1884 $abc$23348$new_n1881 $abc$23348$new_n1886 $abc$23348$new_n1875 i_yval[10] $abc$23348$new_n1883 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[10] $abc$23348$new_n1866 i_xval[10] $abc$23348$new_n1884 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1885 -001 1 -010 1 -011 1 -100 1 -.names i_xval[10] $abc$23348$new_n1872 i_xval[9] $abc$23348$new_n1886 -000 1 -001 1 -011 1 -110 1 -.names i_ce $abc$23348$new_n1888 yv[0][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19924 -001 1 -011 1 -100 1 -101 1 -.names $abc$23348$new_n1889 $abc$23348$new_n1881 $abc$23348$new_n1890 $abc$23348$new_n1875 i_yval[9] $abc$23348$new_n1888 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[9] $abc$23348$new_n1867 i_xval[9] $abc$23348$new_n1889 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names i_xval[9] $abc$23348$new_n1872 $abc$23348$new_n1890 -00 1 -11 1 -.names i_ce $abc$23348$new_n1892 yv[0][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19926 -001 1 -011 1 -100 1 -101 1 -.names $abc$23348$new_n1893 $abc$23348$new_n1881 $abc$23348$new_n1895 $abc$23348$new_n1875 i_yval[8] $abc$23348$new_n1892 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n1894 i_xval[8] $abc$23348$new_n1893 -1001 1 -1011 1 -1110 1 -1111 1 -.names i_yval[8] $abc$23348$new_n1868 i_yval[7] i_yval[6] i_yval[5] $abc$23348$new_n1894 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names i_xval[8] $abc$23348$new_n1873 i_xval[7] i_xval[6] i_xval[5] $abc$23348$new_n1895 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names $abc$23348$new_n1899 $abc$23348$new_n1897 yv[0][9] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19928 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1101 1 -1110 1 -1111 1 -.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n1898 i_xval[7] $abc$23348$new_n1897 -1001 1 -1011 1 -1110 1 -1111 1 -.names i_yval[7] $abc$23348$new_n1868 i_yval[6] i_yval[5] $abc$23348$new_n1898 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names i_ce $abc$23348$new_n1900 $abc$23348$new_n1881 $abc$23348$new_n1875 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$abc$23348$new_n2199 $abc$23348$new_n2206 $abc$23348$new_n4341 -00100 1 -00101 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names i_ce xv[1][13] $abc$23348$new_n4341 yv[1][11] yv[2][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20168 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names ph[1][19] xv[1][4] yv[1][6] $abc$23348$new_n2249 $abc$23348$new_n2256 $abc$23348$new_n4343 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01110 1 -01111 1 -10101 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_ce xv[1][5] $abc$23348$new_n4343 yv[1][7] xv[2][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20210 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names ph[2][19] xv[2][15] yv[2][12] $abc$23348$new_n2348 $abc$23348$new_n2341 $abc$23348$new_n4345 -00100 1 -00110 1 -01001 1 -01011 1 -10010 1 -10011 1 -11100 1 -11101 1 -.names i_ce $abc$23348$new_n4345 yv[2][13] yv[3][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20262 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names ph[2][19] xv[2][8] yv[2][11] $abc$23348$new_n2388 $abc$23348$new_n2395 $abc$23348$new_n4347 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_ce xv[2][9] $abc$23348$new_n4347 yv[2][12] xv[3][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20300 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names ph[2][19] xv[2][4] yv[2][7] $abc$23348$new_n2390 $abc$23348$new_n2397 $abc$23348$new_n4349 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01110 1 -01111 1 -10101 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_ce xv[2][5] $abc$23348$new_n4349 yv[2][8] xv[3][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20308 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names ph[3][19] xv[3][15] $abc$23348$new_n2480 yv[3][12] $abc$23348$new_n2489 $abc$23348$new_n4351 -00000 1 -00010 1 -00100 1 -00110 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11010 1 -11011 1 -.names i_ce $abc$23348$new_n4351 yv[3][13] yv[4][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20360 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names ph[4][19] xv[4][15] $abc$23348$new_n2633 yv[4][11] $abc$23348$new_n2615 $abc$23348$new_n4353 -00000 1 -00010 1 -00100 1 -00110 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11010 1 -11011 1 -.names i_ce $abc$23348$new_n4353 yv[4][12] yv[5][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20460 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names xv[4][15] ph[4][19] $abc$23348$new_n2616 yv[4][10] $abc$23348$new_n2633 $abc$23348$new_n4355 -00010 1 -00011 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names i_ce $abc$23348$new_n4355 yv[4][11] yv[5][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20462 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names ph[6][14] ph[6][19] $abc$23348$new_n2851 $abc$23348$new_n2846 ph[6][13] $abc$23348$new_n4357 -00010 1 -00110 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_ce $abc$23348$new_n4357 ph[6][15] ph[7][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20620 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names ph[7][19] ph[7][15] ph[7][14] $abc$23348$new_n2996 $abc$23348$new_n3002 $abc$23348$new_n4359 -00010 1 -00011 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names i_ce $abc$23348$new_n4359 ph[8][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20718 -001 1 -011 1 -110 1 -111 1 -.names ph[7][19] $abc$23348$new_n2997 $abc$23348$new_n3003 ph[7][12] ph[7][11] $abc$23348$new_n4361 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names i_ce $abc$23348$new_n4361 ph[7][13] ph[8][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20722 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names ph[8][19] ph[8][15] ph[8][14] $abc$23348$new_n3149 $abc$23348$new_n3142 $abc$23348$new_n4363 -00010 1 -00011 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names i_ce $abc$23348$new_n4363 ph[9][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20816 -001 1 -011 1 -110 1 -111 1 -.names ph[8][19] $abc$23348$new_n3147 $abc$23348$new_n3143 $abc$23348$new_n3154 $abc$23348$new_n3150 $abc$23348$new_n4365 -00011 1 -00111 1 -01011 1 -01111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_ce $abc$23348$new_n4365 ph[8][13] ph[9][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20820 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names ph[10][19] ph[10][14] $abc$23348$new_n3440 $abc$23348$new_n3446 ph[10][13] $abc$23348$new_n4367 -00010 1 -00110 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_ce $abc$23348$new_n4367 ph[10][15] ph[11][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21012 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$23348$new_n3498 ph[10][19] $abc$23348$new_n3491 $abc$23348$new_n3511 $abc$23348$new_n3503 $abc$23348$new_n4369 -00100 1 -00101 1 -00110 1 -00111 1 -11010 1 -11110 1 -.names $abc$23348$new_n4369 yv[10][10] xv[10][15] $abc$23348$new_n3497 ph[10][19] $abc$23348$new_n4370 -00011 1 -00100 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$23348$new_n3498 ph[10][19] $abc$23348$new_n3491 $abc$23348$new_n3511 $abc$23348$new_n3503 $abc$23348$new_n4371 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$23348$new_n4371 $abc$23348$new_n3497 ph[10][19] xv[10][15] $abc$23348$new_n4372 -0000 1 -0001 1 -0100 1 -0101 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names ph[11][19] ph[11][14] ph[11][13] $abc$23348$new_n3601 $abc$23348$new_n3607 $abc$23348$new_n4373 -00010 1 -00011 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names i_ce $abc$23348$new_n4373 ph[12][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21112 -001 1 -011 1 -110 1 -111 1 -.names yv[11][3] yv[11][4] yv[11][5] yv[11][6] yv[11][7] $abc$23348$new_n4375 -00000 1 -11111 1 -.names xv[11][15] $abc$23348$new_n4375 $abc$23348$new_n3658 yv[11][7] $abc$23348$new_n4376 -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names ph[11][19] ph[11][17] ph[11][18] $abc$23348$new_n3605 $abc$23348$new_n3599 $abc$23348$new_n4377 -00001 1 -00011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce $abc$23348$new_n4377 ph[12][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21582 -001 1 -011 1 -110 1 -111 1 -.names ph[10][19] ph[10][16] ph[10][17] ph[10][18] $abc$23348$new_n3439 $abc$23348$new_n4379 -00000 1 -00001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names i_ce ph[11][19] $abc$23348$new_n4379 $abc$23348$new_n3445 $abc$23348$auto$rtlil.cc:2693:MuxGate$21588 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names ph[9][19] ph[9][17] ph[9][18] $abc$23348$new_n3294 $abc$23348$new_n3299 $abc$23348$new_n4381 -00001 1 -00011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce $abc$23348$new_n4381 ph[10][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21594 -001 1 -011 1 -110 1 -111 1 -.names ph[7][19] ph[7][17] ph[7][18] $abc$23348$new_n3001 $abc$23348$new_n2995 $abc$23348$new_n4383 -00001 1 -00011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce $abc$23348$new_n4383 ph[8][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21606 -001 1 -011 1 -110 1 -111 1 -.names ph[5][19] ph[5][17] ph[5][18] $abc$23348$new_n2704 $abc$23348$new_n2711 $abc$23348$new_n4385 -00001 1 -00011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce $abc$23348$new_n4385 ph[6][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21618 -001 1 -011 1 -110 1 -111 1 -.names ph[2][19] ph[2][17] ph[2][18] $abc$23348$new_n2289 $abc$23348$new_n2294 $abc$23348$new_n4387 -00001 1 -00011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce $abc$23348$new_n4387 ph[3][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21636 -001 1 -011 1 -110 1 -111 1 -.names ph[1][19] ph[1][17] ph[1][18] $abc$23348$new_n2146 $abc$23348$new_n2151 $abc$23348$new_n4389 -00001 1 -00011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce $abc$23348$new_n4389 ph[2][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21642 -001 1 -011 1 -110 1 -111 1 -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21554 Q=xv[16][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21552 Q=xv[16][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21550 Q=xv[16][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21548 Q=xv[16][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21546 Q=xv[16][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21544 Q=xv[16][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21542 Q=xv[16][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21540 Q=xv[16][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21538 Q=xv[16][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21536 Q=xv[16][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21534 Q=xv[16][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21532 Q=xv[16][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21530 Q=xv[16][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21528 Q=xv[16][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21526 Q=xv[16][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21556 Q=xv[16][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21524 Q=yv[16][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21522 Q=yv[16][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21520 Q=yv[16][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21518 Q=yv[16][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21516 Q=yv[16][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21514 Q=yv[16][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21512 Q=yv[16][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21510 Q=yv[16][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21508 Q=yv[16][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21506 Q=yv[16][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21504 Q=yv[16][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21502 Q=yv[16][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21500 Q=yv[16][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21498 Q=yv[16][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21496 Q=yv[16][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21558 Q=yv[16][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21494 Q=xv[15][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21492 Q=xv[15][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21490 Q=xv[15][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21488 Q=xv[15][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21486 Q=xv[15][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21484 Q=xv[15][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21482 Q=xv[15][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21480 Q=xv[15][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21478 Q=xv[15][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21476 Q=xv[15][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21474 Q=xv[15][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21472 Q=xv[15][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21470 Q=xv[15][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21468 Q=xv[15][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21466 Q=xv[15][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21560 Q=xv[15][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21464 Q=yv[15][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21462 Q=yv[15][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21460 Q=yv[15][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21458 Q=yv[15][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21456 Q=yv[15][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21454 Q=yv[15][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21452 Q=yv[15][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21450 Q=yv[15][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21448 Q=yv[15][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21446 Q=yv[15][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21444 Q=yv[15][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21442 Q=yv[15][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21440 Q=yv[15][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21438 Q=yv[15][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21436 Q=yv[15][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21562 Q=yv[15][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21564 Q=ph[15][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21396 Q=xv[14][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21394 Q=xv[14][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21392 Q=xv[14][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21390 Q=xv[14][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21388 Q=xv[14][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21386 Q=xv[14][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21384 Q=xv[14][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21382 Q=xv[14][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21380 Q=xv[14][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21378 Q=xv[14][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21376 Q=xv[14][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21374 Q=xv[14][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21372 Q=xv[14][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21370 Q=xv[14][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21368 Q=xv[14][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21566 Q=xv[14][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21366 Q=yv[14][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21364 Q=yv[14][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21362 Q=yv[14][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21360 Q=yv[14][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21358 Q=yv[14][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21356 Q=yv[14][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21354 Q=yv[14][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21352 Q=yv[14][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21350 Q=yv[14][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21348 Q=yv[14][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21346 Q=yv[14][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21344 Q=yv[14][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21342 Q=yv[14][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21340 Q=yv[14][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21338 Q=yv[14][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21568 Q=yv[14][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21336 Q=ph[14][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21334 Q=ph[14][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21332 Q=ph[14][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21330 Q=ph[14][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21328 Q=ph[14][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21326 Q=ph[14][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21324 Q=ph[14][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21322 Q=ph[14][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21320 Q=ph[14][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21318 Q=ph[14][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21316 Q=ph[14][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21314 Q=ph[14][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21312 Q=ph[14][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21310 Q=ph[14][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21308 Q=ph[14][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21306 Q=ph[14][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21304 Q=ph[14][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21302 Q=ph[14][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21300 Q=ph[14][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21570 Q=ph[14][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21298 Q=xv[13][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21296 Q=xv[13][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21294 Q=xv[13][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21292 Q=xv[13][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21290 Q=xv[13][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21288 Q=xv[13][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21286 Q=xv[13][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21284 Q=xv[13][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21282 Q=xv[13][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21280 Q=xv[13][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21278 Q=xv[13][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21276 Q=xv[13][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21274 Q=xv[13][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21272 Q=xv[13][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21270 Q=xv[13][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21572 Q=xv[13][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21268 Q=yv[13][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21266 Q=yv[13][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21264 Q=yv[13][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21262 Q=yv[13][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21260 Q=yv[13][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21258 Q=yv[13][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21256 Q=yv[13][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21254 Q=yv[13][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21252 Q=yv[13][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21250 Q=yv[13][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21248 Q=yv[13][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21246 Q=yv[13][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21244 Q=yv[13][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21242 Q=yv[13][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21240 Q=yv[13][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21574 Q=yv[13][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21238 Q=ph[13][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21236 Q=ph[13][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21234 Q=ph[13][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21232 Q=ph[13][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21230 Q=ph[13][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21228 Q=ph[13][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21226 Q=ph[13][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21224 Q=ph[13][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21222 Q=ph[13][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21220 Q=ph[13][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21218 Q=ph[13][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21216 Q=ph[13][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21214 Q=ph[13][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21212 Q=ph[13][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21210 Q=ph[13][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21208 Q=ph[13][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21206 Q=ph[13][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21204 Q=ph[13][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21202 Q=ph[13][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21576 Q=ph[13][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21200 Q=xv[12][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21198 Q=xv[12][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21196 Q=xv[12][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21194 Q=xv[12][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21192 Q=xv[12][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21190 Q=xv[12][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21188 Q=xv[12][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21186 Q=xv[12][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21184 Q=xv[12][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21182 Q=xv[12][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21180 Q=xv[12][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21178 Q=xv[12][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21176 Q=xv[12][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21174 Q=xv[12][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21172 Q=xv[12][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21578 Q=xv[12][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21170 Q=yv[12][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21168 Q=yv[12][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21166 Q=yv[12][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21164 Q=yv[12][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21162 Q=yv[12][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21160 Q=yv[12][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21158 Q=yv[12][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21156 Q=yv[12][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21154 Q=yv[12][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21152 Q=yv[12][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21150 Q=yv[12][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21148 Q=yv[12][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21146 Q=yv[12][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21144 Q=yv[12][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21142 Q=yv[12][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21580 Q=yv[12][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21140 Q=ph[12][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21138 Q=ph[12][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21136 Q=ph[12][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21134 Q=ph[12][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21132 Q=ph[12][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21130 Q=ph[12][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21128 Q=ph[12][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21126 Q=ph[12][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21124 Q=ph[12][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21122 Q=ph[12][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21120 Q=ph[12][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21118 Q=ph[12][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21116 Q=ph[12][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21114 Q=ph[12][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21112 Q=ph[12][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21110 Q=ph[12][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21108 Q=ph[12][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21106 Q=ph[12][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21104 Q=ph[12][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21582 Q=ph[12][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21102 Q=xv[11][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21100 Q=xv[11][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21098 Q=xv[11][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21096 Q=xv[11][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21094 Q=xv[11][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21092 Q=xv[11][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21090 Q=xv[11][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21088 Q=xv[11][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21086 Q=xv[11][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21084 Q=xv[11][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21082 Q=xv[11][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21080 Q=xv[11][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21078 Q=xv[11][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21076 Q=xv[11][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21074 Q=xv[11][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21584 Q=xv[11][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21072 Q=yv[11][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21070 Q=yv[11][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21068 Q=yv[11][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21066 Q=yv[11][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21064 Q=yv[11][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21062 Q=yv[11][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21060 Q=yv[11][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21058 Q=yv[11][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21056 Q=yv[11][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21054 Q=yv[11][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21052 Q=yv[11][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21050 Q=yv[11][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21048 Q=yv[11][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21046 Q=yv[11][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21044 Q=yv[11][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21586 Q=yv[11][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21042 Q=ph[11][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21040 Q=ph[11][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21038 Q=ph[11][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21036 Q=ph[11][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21034 Q=ph[11][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21032 Q=ph[11][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21030 Q=ph[11][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21028 Q=ph[11][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21026 Q=ph[11][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21024 Q=ph[11][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21022 Q=ph[11][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21020 Q=ph[11][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21018 Q=ph[11][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21016 Q=ph[11][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21014 Q=ph[11][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21012 Q=ph[11][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21010 Q=ph[11][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21008 Q=ph[11][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21006 Q=ph[11][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21588 Q=ph[11][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21004 Q=xv[10][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21002 Q=xv[10][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21000 Q=xv[10][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20998 Q=xv[10][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20996 Q=xv[10][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20994 Q=xv[10][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20992 Q=xv[10][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20990 Q=xv[10][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20988 Q=xv[10][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20986 Q=xv[10][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20984 Q=xv[10][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20982 Q=xv[10][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20980 Q=xv[10][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20978 Q=xv[10][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20976 Q=xv[10][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21590 Q=xv[10][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20974 Q=yv[10][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20972 Q=yv[10][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20970 Q=yv[10][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20968 Q=yv[10][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20966 Q=yv[10][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20964 Q=yv[10][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20962 Q=yv[10][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20960 Q=yv[10][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20958 Q=yv[10][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20956 Q=yv[10][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20954 Q=yv[10][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20952 Q=yv[10][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20950 Q=yv[10][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20948 Q=yv[10][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20946 Q=yv[10][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21592 Q=yv[10][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20944 Q=ph[10][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20942 Q=ph[10][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20940 Q=ph[10][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20938 Q=ph[10][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20936 Q=ph[10][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20934 Q=ph[10][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20932 Q=ph[10][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20930 Q=ph[10][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20928 Q=ph[10][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20926 Q=ph[10][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20924 Q=ph[10][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20922 Q=ph[10][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20920 Q=ph[10][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20918 Q=ph[10][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20916 Q=ph[10][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20914 Q=ph[10][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20912 Q=ph[10][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20910 Q=ph[10][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20908 Q=ph[10][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21594 Q=ph[10][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20906 Q=xv[9][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20904 Q=xv[9][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20902 Q=xv[9][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20900 Q=xv[9][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20898 Q=xv[9][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20896 Q=xv[9][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20894 Q=xv[9][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20892 Q=xv[9][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20890 Q=xv[9][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20888 Q=xv[9][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20886 Q=xv[9][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20884 Q=xv[9][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20882 Q=xv[9][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20880 Q=xv[9][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20878 Q=xv[9][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21596 Q=xv[9][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20876 Q=yv[9][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20874 Q=yv[9][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20872 Q=yv[9][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20870 Q=yv[9][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20868 Q=yv[9][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20866 Q=yv[9][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20864 Q=yv[9][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20862 Q=yv[9][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20860 Q=yv[9][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20858 Q=yv[9][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20856 Q=yv[9][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20854 Q=yv[9][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20852 Q=yv[9][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20850 Q=yv[9][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20848 Q=yv[9][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21598 Q=yv[9][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20846 Q=ph[9][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20844 Q=ph[9][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20842 Q=ph[9][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20840 Q=ph[9][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20838 Q=ph[9][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20836 Q=ph[9][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20834 Q=ph[9][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20832 Q=ph[9][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20830 Q=ph[9][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20828 Q=ph[9][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20826 Q=ph[9][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20824 Q=ph[9][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20822 Q=ph[9][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20820 Q=ph[9][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20818 Q=ph[9][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20816 Q=ph[9][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20814 Q=ph[9][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20812 Q=ph[9][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20810 Q=ph[9][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21600 Q=ph[9][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20808 Q=xv[8][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20806 Q=xv[8][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20804 Q=xv[8][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20802 Q=xv[8][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20800 Q=xv[8][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20798 Q=xv[8][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20796 Q=xv[8][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20794 Q=xv[8][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20792 Q=xv[8][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20790 Q=xv[8][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20788 Q=xv[8][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20786 Q=xv[8][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20784 Q=xv[8][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20782 Q=xv[8][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20780 Q=xv[8][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21602 Q=xv[8][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20778 Q=yv[8][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20776 Q=yv[8][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20774 Q=yv[8][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20772 Q=yv[8][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20770 Q=yv[8][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20768 Q=yv[8][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20766 Q=yv[8][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20764 Q=yv[8][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20762 Q=yv[8][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20760 Q=yv[8][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20758 Q=yv[8][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20756 Q=yv[8][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20754 Q=yv[8][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20752 Q=yv[8][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20750 Q=yv[8][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21604 Q=yv[8][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20748 Q=ph[8][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20746 Q=ph[8][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20744 Q=ph[8][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20742 Q=ph[8][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20740 Q=ph[8][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20738 Q=ph[8][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20736 Q=ph[8][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20734 Q=ph[8][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20732 Q=ph[8][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20730 Q=ph[8][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20728 Q=ph[8][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20726 Q=ph[8][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20724 Q=ph[8][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20722 Q=ph[8][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20720 Q=ph[8][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20718 Q=ph[8][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20716 Q=ph[8][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20714 Q=ph[8][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20712 Q=ph[8][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21606 Q=ph[8][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20710 Q=xv[7][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20708 Q=xv[7][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20706 Q=xv[7][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20704 Q=xv[7][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20702 Q=xv[7][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20700 Q=xv[7][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20698 Q=xv[7][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20696 Q=xv[7][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20694 Q=xv[7][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20692 Q=xv[7][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20690 Q=xv[7][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20688 Q=xv[7][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20686 Q=xv[7][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20684 Q=xv[7][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20682 Q=xv[7][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21608 Q=xv[7][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20680 Q=yv[7][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20678 Q=yv[7][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20676 Q=yv[7][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20674 Q=yv[7][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20672 Q=yv[7][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20670 Q=yv[7][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20668 Q=yv[7][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20666 Q=yv[7][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20664 Q=yv[7][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20662 Q=yv[7][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20660 Q=yv[7][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20658 Q=yv[7][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20656 Q=yv[7][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20654 Q=yv[7][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20652 Q=yv[7][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21610 Q=yv[7][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20650 Q=ph[7][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20648 Q=ph[7][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20646 Q=ph[7][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20644 Q=ph[7][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20642 Q=ph[7][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20640 Q=ph[7][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20638 Q=ph[7][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20636 Q=ph[7][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20634 Q=ph[7][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20632 Q=ph[7][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20630 Q=ph[7][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20628 Q=ph[7][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20626 Q=ph[7][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20624 Q=ph[7][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20622 Q=ph[7][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20620 Q=ph[7][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20618 Q=ph[7][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20616 Q=ph[7][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20614 Q=ph[7][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21612 Q=ph[7][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20612 Q=xv[6][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20610 Q=xv[6][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20608 Q=xv[6][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20606 Q=xv[6][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20604 Q=xv[6][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20602 Q=xv[6][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20600 Q=xv[6][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20598 Q=xv[6][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20596 Q=xv[6][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20594 Q=xv[6][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20592 Q=xv[6][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20590 Q=xv[6][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20588 Q=xv[6][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20586 Q=xv[6][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20584 Q=xv[6][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21614 Q=xv[6][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20582 Q=yv[6][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20580 Q=yv[6][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20578 Q=yv[6][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20576 Q=yv[6][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20574 Q=yv[6][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20572 Q=yv[6][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20570 Q=yv[6][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20568 Q=yv[6][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20566 Q=yv[6][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20564 Q=yv[6][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20562 Q=yv[6][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20560 Q=yv[6][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20558 Q=yv[6][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20556 Q=yv[6][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20554 Q=yv[6][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21616 Q=yv[6][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20552 Q=ph[6][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20550 Q=ph[6][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20548 Q=ph[6][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20546 Q=ph[6][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20544 Q=ph[6][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20542 Q=ph[6][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20540 Q=ph[6][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20538 Q=ph[6][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20536 Q=ph[6][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20534 Q=ph[6][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20532 Q=ph[6][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20530 Q=ph[6][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20528 Q=ph[6][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20526 Q=ph[6][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20524 Q=ph[6][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20522 Q=ph[6][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20520 Q=ph[6][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20518 Q=ph[6][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20516 Q=ph[6][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21618 Q=ph[6][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20514 Q=xv[5][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20512 Q=xv[5][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20510 Q=xv[5][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20508 Q=xv[5][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20506 Q=xv[5][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20504 Q=xv[5][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20502 Q=xv[5][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20500 Q=xv[5][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20498 Q=xv[5][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20496 Q=xv[5][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20494 Q=xv[5][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20492 Q=xv[5][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20490 Q=xv[5][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20488 Q=xv[5][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20486 Q=xv[5][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21620 Q=xv[5][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20484 Q=yv[5][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20482 Q=yv[5][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20480 Q=yv[5][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20478 Q=yv[5][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20476 Q=yv[5][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20474 Q=yv[5][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20472 Q=yv[5][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20470 Q=yv[5][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20468 Q=yv[5][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20466 Q=yv[5][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20464 Q=yv[5][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20462 Q=yv[5][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20460 Q=yv[5][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20458 Q=yv[5][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20456 Q=yv[5][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21622 Q=yv[5][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20454 Q=ph[5][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20452 Q=ph[5][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20450 Q=ph[5][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20448 Q=ph[5][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20446 Q=ph[5][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20444 Q=ph[5][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20442 Q=ph[5][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20440 Q=ph[5][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20438 Q=ph[5][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20436 Q=ph[5][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20434 Q=ph[5][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20432 Q=ph[5][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20430 Q=ph[5][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20428 Q=ph[5][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20426 Q=ph[5][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20424 Q=ph[5][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20422 Q=ph[5][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20420 Q=ph[5][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20418 Q=ph[5][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21624 Q=ph[5][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20416 Q=xv[4][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20414 Q=xv[4][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20412 Q=xv[4][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20410 Q=xv[4][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20408 Q=xv[4][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20406 Q=xv[4][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20404 Q=xv[4][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20402 Q=xv[4][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20400 Q=xv[4][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20398 Q=xv[4][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20396 Q=xv[4][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20394 Q=xv[4][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20392 Q=xv[4][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20390 Q=xv[4][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20388 Q=xv[4][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21626 Q=xv[4][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20386 Q=yv[4][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20384 Q=yv[4][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20382 Q=yv[4][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20380 Q=yv[4][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20378 Q=yv[4][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20376 Q=yv[4][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20374 Q=yv[4][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20372 Q=yv[4][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20370 Q=yv[4][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20368 Q=yv[4][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20366 Q=yv[4][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20364 Q=yv[4][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20362 Q=yv[4][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20360 Q=yv[4][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20358 Q=yv[4][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21628 Q=yv[4][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20356 Q=ph[4][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20354 Q=ph[4][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20352 Q=ph[4][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20350 Q=ph[4][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20348 Q=ph[4][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20346 Q=ph[4][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20344 Q=ph[4][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20342 Q=ph[4][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20340 Q=ph[4][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20338 Q=ph[4][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20336 Q=ph[4][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20334 Q=ph[4][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20332 Q=ph[4][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20330 Q=ph[4][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20328 Q=ph[4][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20326 Q=ph[4][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20324 Q=ph[4][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20322 Q=ph[4][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20320 Q=ph[4][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21630 Q=ph[4][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20318 Q=xv[3][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20316 Q=xv[3][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20314 Q=xv[3][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20312 Q=xv[3][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20310 Q=xv[3][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20308 Q=xv[3][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20306 Q=xv[3][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20304 Q=xv[3][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20302 Q=xv[3][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20300 Q=xv[3][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20298 Q=xv[3][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20296 Q=xv[3][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20294 Q=xv[3][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20292 Q=xv[3][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20290 Q=xv[3][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21632 Q=xv[3][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20288 Q=yv[3][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20286 Q=yv[3][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20284 Q=yv[3][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20282 Q=yv[3][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20280 Q=yv[3][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20278 Q=yv[3][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20276 Q=yv[3][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20274 Q=yv[3][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20272 Q=yv[3][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20270 Q=yv[3][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20268 Q=yv[3][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20266 Q=yv[3][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20264 Q=yv[3][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20262 Q=yv[3][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20260 Q=yv[3][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21634 Q=yv[3][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20258 Q=ph[3][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20256 Q=ph[3][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20254 Q=ph[3][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20252 Q=ph[3][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20250 Q=ph[3][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20248 Q=ph[3][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20246 Q=ph[3][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20244 Q=ph[3][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20242 Q=ph[3][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20240 Q=ph[3][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20238 Q=ph[3][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20236 Q=ph[3][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20234 Q=ph[3][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20232 Q=ph[3][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20230 Q=ph[3][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20228 Q=ph[3][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20226 Q=ph[3][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20224 Q=ph[3][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20222 Q=ph[3][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21636 Q=ph[3][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20220 Q=xv[2][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20218 Q=xv[2][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20216 Q=xv[2][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20214 Q=xv[2][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20212 Q=xv[2][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20210 Q=xv[2][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20208 Q=xv[2][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20206 Q=xv[2][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20204 Q=xv[2][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20202 Q=xv[2][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20200 Q=xv[2][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20198 Q=xv[2][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20196 Q=xv[2][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20194 Q=xv[2][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20192 Q=xv[2][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21638 Q=xv[2][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20190 Q=yv[2][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20188 Q=yv[2][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20186 Q=yv[2][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20184 Q=yv[2][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20182 Q=yv[2][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20180 Q=yv[2][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20178 Q=yv[2][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20176 Q=yv[2][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20174 Q=yv[2][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20172 Q=yv[2][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20170 Q=yv[2][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20168 Q=yv[2][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20166 Q=yv[2][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20164 Q=yv[2][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20162 Q=yv[2][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21640 Q=yv[2][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20160 Q=ph[2][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20158 Q=ph[2][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20156 Q=ph[2][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20154 Q=ph[2][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20152 Q=ph[2][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20150 Q=ph[2][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20148 Q=ph[2][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20146 Q=ph[2][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20144 Q=ph[2][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20142 Q=ph[2][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20140 Q=ph[2][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20138 Q=ph[2][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20136 Q=ph[2][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20134 Q=ph[2][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20132 Q=ph[2][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20130 Q=ph[2][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20128 Q=ph[2][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20126 Q=ph[2][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20124 Q=ph[2][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21642 Q=ph[2][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20122 Q=xv[1][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20120 Q=xv[1][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20118 Q=xv[1][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20116 Q=xv[1][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20114 Q=xv[1][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20112 Q=xv[1][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20110 Q=xv[1][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20108 Q=xv[1][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20106 Q=xv[1][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20104 Q=xv[1][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20102 Q=xv[1][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20100 Q=xv[1][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20098 Q=xv[1][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20096 Q=xv[1][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20094 Q=xv[1][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21644 Q=xv[1][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20092 Q=yv[1][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20090 Q=yv[1][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20088 Q=yv[1][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20086 Q=yv[1][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20084 Q=yv[1][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20082 Q=yv[1][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20080 Q=yv[1][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20078 Q=yv[1][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20076 Q=yv[1][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20074 Q=yv[1][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20072 Q=yv[1][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20070 Q=yv[1][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20068 Q=yv[1][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20066 Q=yv[1][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20064 Q=yv[1][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21646 Q=yv[1][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20062 Q=ph[1][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20060 Q=ph[1][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20058 Q=ph[1][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20056 Q=ph[1][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20054 Q=ph[1][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20052 Q=ph[1][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20050 Q=ph[1][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20048 Q=ph[1][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20046 Q=ph[1][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20044 Q=ph[1][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20042 Q=ph[1][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20040 Q=ph[1][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20038 Q=ph[1][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20036 Q=ph[1][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20034 Q=ph[1][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20032 Q=ph[1][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20030 Q=ph[1][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20028 Q=ph[1][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20026 Q=ph[1][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21648 Q=ph[1][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20024 Q=o_xval[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20022 Q=o_xval[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20020 Q=o_xval[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20018 Q=o_xval[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20016 Q=o_xval[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20014 Q=o_xval[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20012 Q=o_xval[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20010 Q=o_xval[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20008 Q=o_xval[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20006 Q=o_xval[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20004 Q=o_xval[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20002 Q=o_xval[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21650 Q=o_xval[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20000 Q=o_yval[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19998 Q=o_yval[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19996 Q=o_yval[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19994 Q=o_yval[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19992 Q=o_yval[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19990 Q=o_yval[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19988 Q=o_yval[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19986 Q=o_yval[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19984 Q=o_yval[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19982 Q=o_yval[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19980 Q=o_yval[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19978 Q=o_yval[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21652 Q=o_yval[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21654 Q=o_aux R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19976 Q=xv[0][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19974 Q=xv[0][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19972 Q=xv[0][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19970 Q=xv[0][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19968 Q=xv[0][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19966 Q=xv[0][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19964 Q=xv[0][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19962 Q=xv[0][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19960 Q=xv[0][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19958 Q=xv[0][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19956 Q=xv[0][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19954 Q=xv[0][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19952 Q=xv[0][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19950 Q=xv[0][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19948 Q=xv[0][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21656 Q=xv[0][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19946 Q=yv[0][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19944 Q=yv[0][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19942 Q=yv[0][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19940 Q=yv[0][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19938 Q=yv[0][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19936 Q=yv[0][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19934 Q=yv[0][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19932 Q=yv[0][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19930 Q=yv[0][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19928 Q=yv[0][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19926 Q=yv[0][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19924 Q=yv[0][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19922 Q=yv[0][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19920 Q=yv[0][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19918 Q=yv[0][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21658 Q=yv[0][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19916 Q=ph[0][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19914 Q=ph[0][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19912 Q=ph[0][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19910 Q=ph[0][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19908 Q=ph[0][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19906 Q=ph[0][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19904 Q=ph[0][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19902 Q=ph[0][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19900 Q=ph[0][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19898 Q=ph[0][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19896 Q=ph[0][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19894 Q=ph[0][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19892 Q=ph[0][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19890 Q=ph[0][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19888 Q=ph[0][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19886 Q=ph[0][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19884 Q=ph[0][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19882 Q=ph[0][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19880 Q=ph[0][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21660 Q=ph[0][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19878 Q=ax[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19876 Q=ax[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19874 Q=ax[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19872 Q=ax[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19870 Q=ax[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19868 Q=ax[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19866 Q=ax[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19864 Q=ax[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19862 Q=ax[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19860 Q=ax[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19858 Q=ax[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19856 Q=ax[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19854 Q=ax[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19852 Q=ax[13] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19850 Q=ax[14] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19848 Q=ax[15] R=i_reset -.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21662 Q=ax[16] R=i_reset -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif deleted file mode 100644 index b9328ff6c7b..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif +++ /dev/null @@ -1,19093 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model cordictanh -.inputs CLK EN z[-24] z[-23] z[-22] z[-21] z[-20] z[-19] z[-18] z[-17] z[-16] z[-15] z[-14] z[-13] z[-12] z[-11] z[-10] z[-9] z[-8] z[-7] z[-6] z[-5] z[-4] z[-3] z[-2] z[-1] z[0] z[1] z[2] z[3] z[4] z[5] z[6] z[7] -.outputs out[-24] out[-23] out[-22] out[-21] out[-20] out[-19] out[-18] out[-17] out[-16] out[-15] out[-14] out[-13] out[-12] out[-11] out[-10] out[-9] out[-8] out[-7] out[-6] out[-5] out[-4] out[-3] out[-2] out[-1] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] -.names $false -.names $true -1 -.names $undef -.names $abc$10488$new_n419 $abc$10488$new_n384 z[-13] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10002 -0011 1 -0111 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names z_[-13] $abc$10488$new_n416 z_[7] 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divider.x[0] divider.y[-1] divider.x[-1] $abc$10488$new_n1020 $abc$10488$new_n1019 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names divider.y[-3] divider.x[-3] divider.y[-2] divider.x[-2] $abc$10488$new_n1017 $abc$10488$new_n1020 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names divider.y[-1] divider.x[-1] $abc$10488$new_n1020 $abc$10488$new_n1021 -000 1 -011 1 -101 1 -110 1 -.names divider.y[2] divider.x[2] divider.y[1] divider.x[1] $abc$10488$new_n1023 $abc$10488$new_n1022 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names divider.y[-1] divider.x[-1] divider.y[0] divider.x[0] $abc$10488$new_n1020 $abc$10488$new_n1023 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 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divider.x[-21] divider.x[-22] $abc$10488$new_n1082 -000 1 -010 1 -100 1 -101 1 -.names LOOKUP.index[2] $abc$10488$new_n1085 $abc$10488$new_n1087 $abc$10488$new_n1084 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1086 divider.x[7] divider.x[6] $abc$10488$new_n1085 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[0] divider.x[5] divider.x[4] $abc$10488$new_n1086 -000 1 -010 1 -100 1 -101 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1088 divider.x[3] divider.x[2] $abc$10488$new_n1087 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[0] divider.x[1] divider.x[0] $abc$10488$new_n1088 -000 1 -010 1 -100 1 -101 1 -.names LOOKUP.index[2] $abc$10488$new_n1090 $abc$10488$new_n1092 $abc$10488$new_n1089 -001 1 -011 1 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LOOKUP.index[2] $abc$10488$new_n1097 $abc$10488$new_n1098 $abc$10488$new_n1096 -010 1 -011 1 -101 1 -111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1065 divider.x[-4] divider.x[-5] $abc$10488$new_n1097 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1061 divider.x[0] divider.x[-1] $abc$10488$new_n1098 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1060 divider.x[6] divider.x[5] $abc$10488$new_n1099 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[2] $abc$10488$new_n1102 $abc$10488$new_n1103 $abc$10488$new_n1101 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1067 divider.x[-8] divider.x[-9] $abc$10488$new_n1102 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1052 divider.x[-12] divider.x[-13] $abc$10488$new_n1103 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[4] $abc$10488$new_n1108 $abc$10488$new_n1115 $abc$10488$new_n1107 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] $abc$10488$new_n1109 $abc$10488$new_n1112 $abc$10488$new_n1108 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[2] $abc$10488$new_n1110 $abc$10488$new_n1111 $abc$10488$new_n1109 -010 1 -011 1 -101 1 -111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1086 divider.x[3] divider.x[2] $abc$10488$new_n1110 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[0] LOOKUP.index[1] divider.x[7] divider.x[6] $abc$10488$new_n1111 -0000 1 -0010 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names LOOKUP.index[2] $abc$10488$new_n1113 $abc$10488$new_n1114 $abc$10488$new_n1112 -010 1 -011 1 -101 1 -111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1091 divider.x[-5] divider.x[-6] $abc$10488$new_n1113 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1088 divider.x[-1] divider.x[-2] $abc$10488$new_n1114 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1116 $abc$10488$new_n1119 $abc$10488$new_n1120 $abc$10488$new_n1115 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[2] $abc$10488$new_n1117 $abc$10488$new_n1118 $abc$10488$new_n1116 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1093 divider.x[-9] divider.x[-10] $abc$10488$new_n1117 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1074 divider.x[-13] divider.x[-14] $abc$10488$new_n1118 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[1] $abc$10488$new_n1076 $abc$10488$new_n1079 $abc$10488$new_n1119 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[1] $abc$10488$new_n1080 $abc$10488$new_n1082 $abc$10488$new_n1120 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[4] $abc$10488$new_n1122 $abc$10488$new_n1124 $abc$10488$new_n403 $abc$10488$new_n1055 $abc$10488$new_n1121 -00100 1 -00101 1 -00111 1 -01100 1 -01101 1 -01111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1123 $abc$10488$new_n1062 divider.x[7] $abc$10488$new_n1122 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names LOOKUP.index[2] $abc$10488$new_n1059 $abc$10488$new_n1064 $abc$10488$new_n1123 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] $abc$10488$new_n1125 LOOKUP.index[2] $abc$10488$new_n1053 $abc$10488$new_n1124 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names LOOKUP.index[2] $abc$10488$new_n1066 $abc$10488$new_n1051 $abc$10488$new_n1125 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[4] $abc$10488$new_n1127 $abc$10488$new_n1129 $abc$10488$new_n1126 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1128 $abc$10488$new_n1085 divider.x[7] $abc$10488$new_n1127 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names LOOKUP.index[2] $abc$10488$new_n1087 $abc$10488$new_n1090 $abc$10488$new_n1128 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1130 $abc$10488$new_n1075 $abc$10488$new_n1078 $abc$10488$new_n1129 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[2] $abc$10488$new_n1092 $abc$10488$new_n1073 $abc$10488$new_n1130 -001 1 -011 1 -110 1 -111 1 -.names $abc$10488$new_n1132 LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n1135 divider.x[7] $abc$10488$new_n1131 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 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$abc$10488$new_n1138 $abc$10488$new_n1118 $abc$10488$new_n1119 $abc$10488$new_n1137 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[2] $abc$10488$new_n1113 $abc$10488$new_n1117 $abc$10488$new_n1138 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] $abc$10488$new_n1140 $abc$10488$new_n1141 $abc$10488$new_n1139 -010 1 -011 1 -101 1 -111 1 -.names LOOKUP.index[2] $abc$10488$new_n1110 $abc$10488$new_n1114 $abc$10488$new_n1140 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[2] $abc$10488$new_n1111 divider.x[7] $abc$10488$new_n1141 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1143 $abc$10488$new_n1063 $abc$10488$new_n1050 $abc$10488$new_n1142 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[3] $abc$10488$new_n1058 divider.x[7] $abc$10488$new_n1143 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1145 $abc$10488$new_n1089 $abc$10488$new_n1072 $abc$10488$new_n1144 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[3] $abc$10488$new_n1084 divider.x[7] $abc$10488$new_n1145 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1147 $abc$10488$new_n1112 $abc$10488$new_n1116 $abc$10488$new_n1146 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[3] $abc$10488$new_n1109 divider.x[7] $abc$10488$new_n1147 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1149 $abc$10488$new_n1096 $abc$10488$new_n1101 $abc$10488$new_n1148 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[2] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1099 $abc$10488$new_n1149 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1151 $abc$10488$new_n1123 $abc$10488$new_n1125 $abc$10488$new_n1150 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[2] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1062 $abc$10488$new_n1151 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1153 $abc$10488$new_n1128 $abc$10488$new_n1130 $abc$10488$new_n1152 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[2] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1085 $abc$10488$new_n1153 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names LOOKUP.index[4] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1135 $abc$10488$new_n1134 $abc$10488$new_n1154 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1156 $abc$10488$new_n1138 $abc$10488$new_n1140 $abc$10488$new_n1155 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[3] $abc$10488$new_n1141 divider.x[7] $abc$10488$new_n1156 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1058 $abc$10488$new_n1063 $abc$10488$new_n1157 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[4] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1084 $abc$10488$new_n1089 $abc$10488$new_n1158 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[4] $abc$10488$new_n1095 divider.x[7] $abc$10488$new_n1159 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] $abc$10488$new_n1108 divider.x[7] $abc$10488$new_n1160 -010 1 -011 1 -100 1 -110 1 -.names $abc$10488$new_n1162 $abc$10488$new_n1164 $abc$10488$new_n1161 -10 1 -.names divider.y[-2] $abc$10488$new_n1163 $abc$10488$new_n1162 -01 1 -10 1 -.names LOOKUP.index[4] $abc$10488$new_n1139 divider.x[7] $abc$10488$new_n1163 -010 1 -011 1 -100 1 -110 1 -.names divider.y[-1] $abc$10488$new_n1165 $abc$10488$new_n1164 -00 1 -11 1 -.names LOOKUP.index[3] LOOKUP.index[4] divider.x[7] $abc$10488$new_n1135 $abc$10488$new_n1165 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names divider.y[-2] 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$abc$10488$new_n1500 divider.y[-13] divider.y[-14] $abc$10488$new_n1538 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1501 divider.y[-19] divider.y[-20] $abc$10488$new_n1539 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1503 divider.y[-23] divider.y[-24] $abc$10488$new_n1540 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[4] $abc$10488$new_n1544 $abc$10488$new_n1542 $abc$10488$new_n1539 $abc$10488$new_n404 $abc$10488$new_n1541 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1543 $abc$10488$new_n1530 divider.y[7] $abc$10488$new_n1542 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names LOOKUP.index[2] $abc$10488$new_n1531 $abc$10488$new_n1533 $abc$10488$new_n1543 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] $abc$10488$new_n1545 LOOKUP.index[2] $abc$10488$new_n1538 $abc$10488$new_n1544 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names LOOKUP.index[2] $abc$10488$new_n1534 $abc$10488$new_n1537 $abc$10488$new_n1545 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1548 $abc$10488$new_n1551 divider.y[7] $abc$10488$new_n1547 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names LOOKUP.index[2] $abc$10488$new_n1549 $abc$10488$new_n1550 $abc$10488$new_n1548 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1524 divider.y[2] divider.y[1] $abc$10488$new_n1549 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1526 divider.y[-2] divider.y[-3] $abc$10488$new_n1550 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1520 divider.y[6] divider.y[5] $abc$10488$new_n1551 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[2] $abc$10488$new_n1554 $abc$10488$new_n1555 $abc$10488$new_n1553 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1508 divider.y[-6] divider.y[-7] $abc$10488$new_n1554 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1510 divider.y[-10] divider.y[-11] $abc$10488$new_n1555 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names LOOKUP.index[1] $abc$10488$new_n1511 $abc$10488$new_n1513 $abc$10488$new_n1556 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[2] $abc$10488$new_n1491 $abc$10488$new_n1495 $abc$10488$new_n1561 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[2] $abc$10488$new_n1485 $abc$10488$new_n1489 $abc$10488$new_n1562 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[2] $abc$10488$new_n1487 divider.y[7] $abc$10488$new_n1563 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] $abc$10488$new_n1565 $abc$10488$new_n1567 $abc$10488$new_n1564 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1566 $abc$10488$new_n1521 divider.y[7] $abc$10488$new_n1565 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names LOOKUP.index[2] $abc$10488$new_n1519 $abc$10488$new_n1523 $abc$10488$new_n1566 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1568 $abc$10488$new_n1509 $abc$10488$new_n1512 $abc$10488$new_n1567 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[2] $abc$10488$new_n1525 $abc$10488$new_n1507 $abc$10488$new_n1568 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1570 $abc$10488$new_n1532 $abc$10488$new_n1536 $abc$10488$new_n1569 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[3] $abc$10488$new_n1529 divider.y[7] $abc$10488$new_n1570 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] $abc$10488$new_n1572 $abc$10488$new_n1574 $abc$10488$new_n1571 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] $abc$10488$new_n1573 divider.y[7] $abc$10488$new_n1572 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[2] $abc$10488$new_n1551 $abc$10488$new_n1549 $abc$10488$new_n1573 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1575 $abc$10488$new_n1555 $abc$10488$new_n1556 $abc$10488$new_n1574 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names LOOKUP.index[2] $abc$10488$new_n1550 $abc$10488$new_n1554 $abc$10488$new_n1575 -001 1 -011 1 -110 1 -111 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1577 $abc$10488$new_n1488 $abc$10488$new_n1494 $abc$10488$new_n1576 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[3] $abc$10488$new_n1484 divider.y[7] $abc$10488$new_n1577 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1579 $abc$10488$new_n1522 $abc$10488$new_n1506 $abc$10488$new_n1578 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[3] $abc$10488$new_n1518 divider.y[7] $abc$10488$new_n1579 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1581 $abc$10488$new_n1543 $abc$10488$new_n1545 $abc$10488$new_n1580 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[2] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1530 $abc$10488$new_n1581 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1583 $abc$10488$new_n1548 $abc$10488$new_n1553 $abc$10488$new_n1582 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[2] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1551 $abc$10488$new_n1583 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1585 $abc$10488$new_n1562 $abc$10488$new_n1561 $abc$10488$new_n1584 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names LOOKUP.index[3] $abc$10488$new_n1563 divider.y[7] $abc$10488$new_n1585 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1587 $abc$10488$new_n1566 $abc$10488$new_n1568 $abc$10488$new_n1586 -00000 1 -00010 1 -00100 1 -00110 1 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1 -110 1 -.names LOOKUP.index[4] $abc$10488$new_n1581 divider.y[7] $abc$10488$new_n1600 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] $abc$10488$new_n1583 divider.y[7] $abc$10488$new_n1601 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] $abc$10488$new_n1585 divider.y[7] $abc$10488$new_n1603 -010 1 -011 1 -100 1 -110 1 -.names LOOKUP.index[4] $abc$10488$new_n1587 divider.y[7] $abc$10488$new_n1605 -010 1 -011 1 -100 1 -110 1 -.names divider.x[3] $abc$10488$new_n1601 divider.x[4] $abc$10488$new_n1600 $abc$10488$new_n1608 $abc$10488$new_n1607 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names divider.x[1] $abc$10488$new_n1599 divider.x[2] $abc$10488$new_n1598 $abc$10488$new_n1609 $abc$10488$new_n1608 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names divider.x[-1] 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-.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10020 Q=z_[-22] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10018 Q=z_[-21] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10016 Q=z_[-20] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10014 Q=z_[-19] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10012 Q=z_[-18] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10010 Q=z_[-17] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10008 Q=z_[-16] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10006 Q=z_[-15] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10004 Q=z_[-14] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10002 Q=z_[-13] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10000 Q=z_[-12] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9998 Q=z_[-11] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9996 Q=z_[-10] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9994 Q=z_[-9] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9992 Q=z_[-8] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9990 Q=z_[-7] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9988 Q=z_[-6] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9986 Q=z_[-5] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9984 Q=z_[-4] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9982 Q=z_[-3] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9980 Q=z_[-2] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9978 Q=z_[-1] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9976 Q=z_[0] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9974 Q=z_[1] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9972 Q=z_[2] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9970 Q=z_[3] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9968 Q=z_[4] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9966 Q=z_[5] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9964 Q=z_[6] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10026 Q=z_[7] -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9962 Q=divider.y[-24] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9960 Q=divider.y[-23] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9958 Q=divider.y[-22] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9956 Q=divider.y[-21] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9954 Q=divider.y[-20] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9952 Q=divider.y[-19] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9950 Q=divider.y[-18] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9948 Q=divider.y[-17] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9946 Q=divider.y[-16] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9944 Q=divider.y[-15] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9942 Q=divider.y[-14] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9940 Q=divider.y[-13] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9938 Q=divider.y[-12] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9936 Q=divider.y[-11] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9934 Q=divider.y[-10] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9932 Q=divider.y[-9] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9930 Q=divider.y[-8] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9928 Q=divider.y[-7] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9926 Q=divider.y[-6] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9924 Q=divider.y[-5] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9922 Q=divider.y[-4] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9920 Q=divider.y[-3] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9918 Q=divider.y[-2] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9916 Q=divider.y[-1] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9914 Q=divider.y[0] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9912 Q=divider.y[1] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9910 Q=divider.y[2] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9908 Q=divider.y[3] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9906 Q=divider.y[4] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9904 Q=divider.y[5] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9902 Q=divider.y[6] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10034 Q=divider.y[7] R=EN -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9900 Q=divider.y_[-24] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9898 Q=divider.y_[-23] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9896 Q=divider.y_[-22] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9894 Q=divider.y_[-21] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9892 Q=divider.y_[-20] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9890 Q=divider.y_[-19] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9888 Q=divider.y_[-18] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9886 Q=divider.y_[-17] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9884 Q=divider.y_[-16] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9882 Q=divider.y_[-15] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9880 Q=divider.y_[-14] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9878 Q=divider.y_[-13] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9876 Q=divider.y_[-12] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9874 Q=divider.y_[-11] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9872 Q=divider.y_[-10] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9870 Q=divider.y_[-9] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9868 Q=divider.y_[-8] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9866 Q=divider.y_[-7] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9864 Q=divider.y_[-6] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9862 Q=divider.y_[-5] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9860 Q=divider.y_[-4] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9858 Q=divider.y_[-3] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9856 Q=divider.y_[-2] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9854 Q=divider.y_[-1] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9852 Q=divider.y_[0] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9850 Q=divider.y_[1] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9848 Q=divider.y_[2] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9846 Q=divider.y_[3] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9844 Q=divider.y_[4] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9842 Q=divider.y_[5] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9840 Q=divider.y_[6] -.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10028 Q=divider.y_[7] -.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9838 Q=LOOKUP.index[0] S=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9836 Q=LOOKUP.index[1] R=EN -.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9834 Q=LOOKUP.index[2] S=EN -.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9832 Q=LOOKUP.index[3] S=EN -.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10036 Q=LOOKUP.index[4] S=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9830 Q=divider.x[-24] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9828 Q=divider.x[-23] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9826 Q=divider.x[-22] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9824 Q=divider.x[-21] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9822 Q=divider.x[-20] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9820 Q=divider.x[-19] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9818 Q=divider.x[-18] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9816 Q=divider.x[-17] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9814 Q=divider.x[-16] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9812 Q=divider.x[-15] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9810 Q=divider.x[-14] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9808 Q=divider.x[-13] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9806 Q=divider.x[-12] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9804 Q=divider.x[-11] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9802 Q=divider.x[-10] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9800 Q=divider.x[-9] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9798 Q=divider.x[-8] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9796 Q=divider.x[-7] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9794 Q=divider.x[-6] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9792 Q=divider.x[-5] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9790 Q=divider.x[-4] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9788 Q=divider.x[-3] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9786 Q=divider.x[-2] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9784 Q=divider.x[-1] R=EN -.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9782 Q=divider.x[0] S=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9780 Q=divider.x[1] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9778 Q=divider.x[2] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9776 Q=divider.x[3] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9774 Q=divider.x[4] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9772 Q=divider.x[5] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9770 Q=divider.x[6] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10038 Q=divider.x[7] R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10040 Q=div_en R=EN -.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10042 Q=IS_FIRST4 S=EN -.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10044 Q=IS_FIRST13 S=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10046 Q=IS_Z_ZERO R=EN -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9768 Q=divider.i[0] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9766 Q=divider.i[1] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9764 Q=divider.i[2] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9762 Q=divider.i[3] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10032 Q=divider.i[4] R=div_en -.subckt sdffr C=CLK D=divider.z_[-24] Q=out[-24] R=div_en -.subckt sdffr C=CLK D=divider.z_[-23] Q=out[-23] R=div_en -.subckt sdffr C=CLK D=divider.z_[-22] Q=out[-22] R=div_en -.subckt sdffr C=CLK D=divider.z_[-21] Q=out[-21] R=div_en -.subckt sdffr C=CLK D=divider.z_[-20] Q=out[-20] R=div_en -.subckt sdffr C=CLK D=divider.z_[-19] Q=out[-19] R=div_en -.subckt sdffr C=CLK D=divider.z_[-18] Q=out[-18] R=div_en -.subckt sdffr C=CLK D=divider.z_[-17] Q=out[-17] R=div_en -.subckt sdffr C=CLK D=divider.z_[-16] Q=out[-16] R=div_en -.subckt sdffr C=CLK D=divider.z_[-15] Q=out[-15] R=div_en -.subckt sdffr C=CLK D=divider.z_[-14] Q=out[-14] R=div_en -.subckt sdffr C=CLK D=divider.z_[-13] Q=out[-13] R=div_en -.subckt sdffr C=CLK D=divider.z_[-12] Q=out[-12] R=div_en -.subckt sdffr C=CLK D=divider.z_[-11] Q=out[-11] R=div_en -.subckt sdffr C=CLK D=divider.z_[-10] Q=out[-10] R=div_en -.subckt sdffr C=CLK D=divider.z_[-9] Q=out[-9] R=div_en -.subckt sdffr C=CLK D=divider.z_[-8] Q=out[-8] R=div_en -.subckt sdffr C=CLK D=divider.z_[-7] Q=out[-7] R=div_en -.subckt sdffr C=CLK D=divider.z_[-6] Q=out[-6] R=div_en -.subckt sdffr C=CLK D=divider.z_[-5] Q=out[-5] R=div_en -.subckt sdffr C=CLK D=divider.z_[-4] Q=out[-4] R=div_en -.subckt sdffr C=CLK D=divider.z_[-3] Q=out[-3] R=div_en -.subckt sdffr C=CLK D=divider.z_[-2] Q=out[-2] R=div_en -.subckt sdffr C=CLK D=divider.z_[-1] Q=out[-1] R=div_en -.subckt sdffr C=CLK D=divider.z_[0] Q=out[0] R=div_en -.subckt sdffr C=CLK D=divider.z_[1] Q=out[1] R=div_en -.subckt sdffr C=CLK D=divider.z_[2] Q=out[2] R=div_en -.subckt sdffr C=CLK D=divider.z_[3] Q=out[3] R=div_en -.subckt sdffr C=CLK D=divider.z_[4] Q=out[4] R=div_en -.subckt sdffr C=CLK D=divider.z_[5] Q=out[5] R=div_en -.subckt sdffr C=CLK D=divider.z_[6] Q=out[6] R=div_en -.subckt sdffr C=CLK D=divider.z_[7] Q=out[7] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9760 Q=divider.z_[-24] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9758 Q=divider.z_[-23] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9756 Q=divider.z_[-22] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9754 Q=divider.z_[-21] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9752 Q=divider.z_[-20] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9750 Q=divider.z_[-19] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9748 Q=divider.z_[-18] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9746 Q=divider.z_[-17] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9744 Q=divider.z_[-16] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9742 Q=divider.z_[-15] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9740 Q=divider.z_[-14] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9738 Q=divider.z_[-13] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9736 Q=divider.z_[-12] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9734 Q=divider.z_[-11] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9732 Q=divider.z_[-10] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9730 Q=divider.z_[-9] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9728 Q=divider.z_[-8] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9726 Q=divider.z_[-7] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9724 Q=divider.z_[-6] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9722 Q=divider.z_[-5] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9720 Q=divider.z_[-4] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9718 Q=divider.z_[-3] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9716 Q=divider.z_[-2] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9714 Q=divider.z_[-1] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9712 Q=divider.z_[0] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9710 Q=divider.z_[1] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9708 Q=divider.z_[2] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9706 Q=divider.z_[3] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9704 Q=divider.z_[4] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9702 Q=divider.z_[5] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9700 Q=divider.z_[6] R=div_en -.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10030 Q=divider.z_[7] R=div_en -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif deleted file mode 100644 index dc494993029..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif +++ /dev/null @@ -1,1170 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 074b50e9c, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model music -.inputs clk -.outputs speaker -.names $false -.names $true -1 -.names $undef -.names get_fullnote.address[7] $abc$2165$new_n111 $abc$2165$new_n116 get_fullnote.address[5] $abc$2165$new_n118 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[0] -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$2165$new_n112 $abc$2165$new_n116 get_fullnote.address[6] get_fullnote.address[5] $abc$2165$new_n117 $abc$2165$new_n111 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names get_fullnote.address[7] $abc$2165$new_n113 get_fullnote.address[6] $abc$2165$new_n115 get_fullnote.address[5] $abc$2165$new_n112 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names get_fullnote.address[3] get_fullnote.address[5] get_fullnote.address[2] get_fullnote.address[4] $abc$2165$new_n114 $abc$2165$new_n113 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -.names get_fullnote.address[0] get_fullnote.address[1] $abc$2165$new_n114 -11 1 -.names get_fullnote.address[2] get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[0] $abc$2165$new_n115 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -.names get_fullnote.address[5] get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[4] get_fullnote.address[1] $abc$2165$new_n116 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[0] get_fullnote.address[2] $abc$2165$new_n117 -00001 1 -00011 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names get_fullnote.address[4] get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[6] $abc$2165$new_n118 -01000 1 -01001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names get_fullnote.address[4] $abc$2165$new_n130 $abc$2165$new_n230 get_fullnote.address[7] get_fullnote.address[6] $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[1] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$2165$new_n124 get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[0] $abc$2165$new_n123 -1001 1 -1011 1 -1110 1 -1111 1 -.names get_fullnote.address[4] get_fullnote.address[3] $abc$2165$new_n124 -10 1 -.names get_fullnote.address[4] get_fullnote.address[5] $abc$2165$new_n125 -11 1 -.names $abc$2165$new_n125 get_fullnote.address[1] get_fullnote.address[0] get_fullnote.address[2] $abc$2165$new_n126 -1100 1 -.names get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[5] get_fullnote.address[2] get_fullnote.address[1] $abc$2165$new_n127 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[0] $abc$2165$new_n129 -000 1 -010 1 -011 1 -.names get_fullnote.address[5] get_fullnote.address[1] get_fullnote.address[2] get_fullnote.address[0] get_fullnote.address[3] $abc$2165$new_n130 -00000 1 -00101 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names get_fullnote.address[7] get_fullnote.address[6] $abc$2165$new_n232 $abc$2165$new_n136 $abc$2165$new_n138 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[2] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names get_fullnote.address[4] get_fullnote.address[3] get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] $abc$2165$new_n134 -00000 1 -00001 1 -00011 1 -00101 1 -00110 1 -00111 1 -.names get_fullnote.address[5] $abc$2165$new_n144 $abc$2165$new_n115 $abc$2165$new_n136 -000 1 -001 1 -011 1 -.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[5] $abc$2165$new_n138 -00001 1 -00011 1 -00101 1 -00111 1 -01101 1 -10001 1 -10011 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$2165$new_n143 get_fullnote.address[5] $abc$2165$new_n146 $abc$2165$new_n140 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[3] -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names get_fullnote.address[6] get_fullnote.address[7] $abc$2165$new_n141 $abc$2165$new_n124 $abc$2165$new_n142 $abc$2165$new_n140 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$2165$new_n124 get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] $abc$2165$new_n141 -1000 1 -.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[2] get_fullnote.address[3] $abc$2165$new_n142 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1110 1 -.names get_fullnote.address[7] get_fullnote.address[6] $abc$2165$new_n145 $abc$2165$new_n144 $abc$2165$new_n143 -0000 1 -0001 1 -0100 1 -0101 1 -1001 1 -1011 1 -1100 1 -1101 1 -.names get_fullnote.address[4] get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[5] get_fullnote.address[3] $abc$2165$new_n144 -00000 1 -00001 1 -00011 1 -00100 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11010 1 -11110 1 -.names get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[5] $abc$2165$new_n145 -10000 1 -.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[0] get_fullnote.address[2] get_fullnote.address[3] $abc$2165$new_n146 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names get_fullnote.address[6] $abc$2165$new_n125 get_fullnote.address[7] $abc$2165$new_n141 $abc$2165$new_n142 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[4] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11110 1 -11111 1 -.names get_fullnote.address[6] $abc$2165$new_n142 $abc$2165$new_n125 get_fullnote.address[7] $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[5] -1110 1 -.names counter_note[0] $abc$2165$new_n153 $abc$2165$new_n155 $abc$2165$new_n150 fullnote[1] $0\counter_note[8:0][0] -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -.names $abc$2165$new_n151 counter_note[8] counter_note[7] counter_note[6] counter_note[5] $abc$2165$new_n150 -10000 1 -.names $abc$2165$new_n152 counter_note[4] $abc$2165$new_n151 -10 1 -.names counter_note[0] counter_note[3] counter_note[2] counter_note[1] $abc$2165$new_n152 -0000 1 -.names fullnote[0] $abc$2165$new_n154 $abc$2165$new_n153 -10 1 -.names fullnote[4] fullnote[5] fullnote[3] fullnote[2] $abc$2165$new_n154 -0001 1 -0110 1 -1000 1 -1011 1 -1101 1 -.names fullnote[5] fullnote[3] fullnote[4] fullnote[2] $abc$2165$new_n155 -0000 1 -0001 1 -0010 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1100 1 -1111 1 -.names counter_note[0] counter_note[1] $abc$2165$new_n157 $abc$2165$new_n150 $0\counter_note[8:0][1] -0000 1 -0001 1 -0010 1 -1100 1 -1101 1 -1110 1 -.names $abc$2165$new_n154 fullnote[0] fullnote[1] $abc$2165$new_n157 -100 1 -101 1 -111 1 -.names counter_note[2] $abc$2165$new_n159 counter_note[0] counter_note[1] $0\counter_note[8:0][2] -0000 1 -1001 1 -1010 1 -1011 1 -.names $abc$2165$new_n150 $abc$2165$new_n155 fullnote[0] fullnote[1] $abc$2165$new_n154 $abc$2165$new_n159 -10000 1 -10001 1 -11011 1 -11100 1 -.names counter_note[3] $abc$2165$new_n161 counter_note[0] counter_note[2] counter_note[1] $0\counter_note[8:0][3] -00000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$2165$new_n150 fullnote[1] fullnote[0] $abc$2165$new_n155 $abc$2165$new_n154 $abc$2165$new_n161 -10000 1 -10001 1 -10011 1 -10110 1 -11010 1 -11111 1 -.names counter_note[4] $abc$2165$new_n152 $abc$2165$new_n163 $0\counter_note[8:0][4] -010 1 -100 1 -.names $abc$2165$new_n150 $abc$2165$new_n155 fullnote[1] fullnote[0] $abc$2165$new_n154 $abc$2165$new_n163 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names counter_note[5] $abc$2165$new_n151 $abc$2165$new_n165 $0\counter_note[8:0][5] -010 1 -100 1 -.names $abc$2165$new_n150 fullnote[1] $abc$2165$new_n154 fullnote[0] $abc$2165$new_n155 $abc$2165$new_n165 -10000 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names counter_note[6] $abc$2165$new_n167 $abc$2165$new_n151 counter_note[5] $0\counter_note[8:0][6] -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$2165$new_n150 fullnote[1] fullnote[0] $abc$2165$new_n154 $abc$2165$new_n155 $abc$2165$new_n167 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names counter_note[7] $abc$2165$new_n151 counter_note[6] counter_note[5] $abc$2165$new_n169 $0\counter_note[8:0][7] -01000 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names counter_note[8] $abc$2165$new_n154 $abc$2165$new_n155 fullnote[0] fullnote[1] $abc$2165$new_n169 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names counter_note[8] $abc$2165$new_n151 counter_note[7] counter_note[6] counter_note[5] $0\counter_note[8:0][8] -01000 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names speaker $abc$2165$new_n175 $abc$2165$new_n172 $abc$2165$new_n150 $0\speaker[0:0] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$2165$new_n173 tone[19] tone[18] tone[21] tone[20] $abc$2165$new_n172 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$2165$new_n174 fullnote[3] fullnote[2] fullnote[1] fullnote[0] $abc$2165$new_n173 -10000 1 -.names fullnote[5] fullnote[4] $abc$2165$new_n174 -00 1 -.names $abc$2165$new_n176 counter_octave[7] counter_octave[6] counter_octave[5] $abc$2165$new_n175 -1000 1 -.names $abc$2165$new_n177 counter_octave[4] $abc$2165$new_n176 -10 1 -.names counter_octave[0] counter_octave[3] counter_octave[1] counter_octave[2] $abc$2165$new_n177 -0000 1 -.names counter_octave[0] $abc$2165$new_n150 $0\counter_octave[7:0][0] -01 1 -10 1 -.names counter_octave[1] $abc$2165$new_n150 counter_octave[0] $0\counter_octave[7:0][1] -010 1 -100 1 -101 1 -111 1 -.names counter_octave[2] $abc$2165$new_n150 counter_octave[0] counter_octave[1] $0\counter_octave[7:0][2] -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$2165$new_n150 counter_octave[3] $abc$2165$new_n184 $abc$2165$new_n183 $abc$2165$new_n182 $0\counter_octave[7:0][3] -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$2165$new_n175 fullnote[4] fullnote[5] $abc$2165$new_n182 -100 1 -101 1 -110 1 -.names counter_octave[3] $abc$2165$new_n175 counter_octave[0] counter_octave[1] counter_octave[2] $abc$2165$new_n183 -00000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$2165$new_n175 fullnote[2] fullnote[3] $abc$2165$new_n184 -100 1 -101 1 -110 1 -.names $abc$2165$new_n150 counter_octave[4] $abc$2165$new_n177 $abc$2165$new_n175 $abc$2165$new_n182 $0\counter_octave[7:0][4] -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$2165$new_n150 counter_octave[5] $abc$2165$new_n176 $abc$2165$new_n187 $abc$2165$new_n175 $0\counter_octave[7:0][5] -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$2165$new_n182 fullnote[5] fullnote[3] fullnote[2] $abc$2165$new_n187 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names counter_octave[6] $abc$2165$new_n176 $abc$2165$new_n150 counter_octave[5] $abc$2165$new_n189 $0\counter_octave[7:0][6] -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names counter_octave[7] fullnote[5] fullnote[4] fullnote[3] $abc$2165$new_n189 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$2165$new_n191 $abc$2165$new_n150 $abc$2165$new_n184 $abc$2165$new_n174 $0\counter_octave[7:0][7] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names counter_octave[7] $abc$2165$new_n150 $abc$2165$new_n176 counter_octave[6] counter_octave[5] $abc$2165$new_n191 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[1] -01 1 -10 1 -.names tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[2] -011 1 -100 1 -101 1 -110 1 -.names tone[3] tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names tone[4] tone[3] tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[4] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[5] -01 1 -10 1 -.names tone[4] tone[3] tone[2] tone[1] tone[0] $abc$2165$new_n197 -11111 1 -.names tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[6] -011 1 -100 1 -101 1 -110 1 -.names tone[7] tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[7] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names tone[8] tone[7] tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[8] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[9] -01 1 -10 1 -.names tone[8] tone[7] tone[6] tone[5] $abc$2165$new_n197 $abc$2165$new_n202 -11111 1 -.names tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[10] -011 1 -100 1 -101 1 -110 1 -.names tone[11] tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[11] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names tone[12] tone[11] tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[12] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[13] -01 1 -10 1 -.names tone[12] tone[11] tone[10] tone[9] $abc$2165$new_n202 $abc$2165$new_n207 -11111 1 -.names tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[14] -011 1 -100 1 -101 1 -110 1 -.names tone[15] tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[15] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names tone[16] tone[15] tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[16] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names tone[17] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[17] -01 1 -10 1 -.names tone[16] tone[15] tone[14] tone[13] $abc$2165$new_n207 $abc$2165$new_n212 -11111 1 -.names tone[18] tone[17] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[18] -011 1 -100 1 -101 1 -110 1 -.names tone[19] tone[17] tone[18] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[19] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names tone[20] tone[17] tone[19] tone[18] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[20] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[21] -01 1 -10 1 -.names tone[17] tone[20] tone[19] tone[18] $abc$2165$new_n212 $abc$2165$new_n217 -11111 1 -.names get_fullnote.address[0] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[22] -011 1 -100 1 -101 1 -110 1 -.names get_fullnote.address[1] get_fullnote.address[0] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[23] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names get_fullnote.address[2] get_fullnote.address[0] get_fullnote.address[1] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[24] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names get_fullnote.address[3] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[25] -01 1 -10 1 -.names get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] tone[21] $abc$2165$new_n217 $abc$2165$new_n222 -11111 1 -.names get_fullnote.address[4] get_fullnote.address[3] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[26] -011 1 -100 1 -101 1 -110 1 -.names get_fullnote.address[5] get_fullnote.address[3] get_fullnote.address[4] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[27] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names get_fullnote.address[6] get_fullnote.address[3] $abc$2165$new_n125 $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[28] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names get_fullnote.address[7] get_fullnote.address[3] get_fullnote.address[6] $abc$2165$new_n125 $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[29] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] -0 1 -.names get_fullnote.address[6] get_fullnote.address[7] $abc$2165$new_n127 $abc$2165$new_n126 $abc$2165$new_n228 -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$2165$new_n228 get_fullnote.address[7] $abc$2165$new_n125 get_fullnote.address[3] $abc$2165$new_n129 $abc$2165$new_n229 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -10100 1 -10110 1 -.names $abc$2165$new_n228 get_fullnote.address[5] $abc$2165$new_n123 $abc$2165$new_n229 $abc$2165$new_n230 -0001 1 -0101 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[5] get_fullnote.address[4] get_fullnote.address[1] $abc$2165$new_n231 -01000 1 -01001 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names get_fullnote.address[5] get_fullnote.address[7] $abc$2165$new_n134 $abc$2165$new_n231 get_fullnote.address[6] $abc$2165$new_n232 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[0] fullnote[0] re clk 2 -.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[1] fullnote[1] re clk 2 -.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[2] fullnote[2] re clk 2 -.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[3] fullnote[3] re clk 2 -.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[4] fullnote[4] re clk 2 -.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[5] fullnote[5] re clk 2 -.latch $0\speaker[0:0] speaker re clk 2 -.latch $0\counter_octave[7:0][0] counter_octave[0] re clk 2 -.latch $0\counter_octave[7:0][1] counter_octave[1] re clk 2 -.latch $0\counter_octave[7:0][2] counter_octave[2] re clk 2 -.latch $0\counter_octave[7:0][3] counter_octave[3] re clk 2 -.latch $0\counter_octave[7:0][4] counter_octave[4] re clk 2 -.latch $0\counter_octave[7:0][5] counter_octave[5] re clk 2 -.latch $0\counter_octave[7:0][6] counter_octave[6] re clk 2 -.latch $0\counter_octave[7:0][7] counter_octave[7] re clk 2 -.latch $0\counter_note[8:0][0] counter_note[0] re clk 2 -.latch $0\counter_note[8:0][1] counter_note[1] re clk 2 -.latch $0\counter_note[8:0][2] counter_note[2] re clk 2 -.latch $0\counter_note[8:0][3] counter_note[3] re clk 2 -.latch $0\counter_note[8:0][4] counter_note[4] re clk 2 -.latch $0\counter_note[8:0][5] counter_note[5] re clk 2 -.latch $0\counter_note[8:0][6] counter_note[6] re clk 2 -.latch $0\counter_note[8:0][7] counter_note[7] re clk 2 -.latch $0\counter_note[8:0][8] counter_note[8] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] tone[0] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[1] tone[1] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[2] tone[2] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[3] tone[3] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[4] tone[4] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[5] tone[5] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[6] tone[6] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[7] tone[7] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[8] tone[8] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[9] tone[9] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[10] tone[10] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[11] tone[11] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[12] tone[12] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[13] tone[13] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[14] tone[14] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[15] tone[15] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[16] tone[16] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[17] tone[17] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[18] tone[18] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[19] tone[19] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[20] tone[20] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[21] tone[21] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[22] get_fullnote.address[0] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[23] get_fullnote.address[1] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[24] get_fullnote.address[2] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[25] get_fullnote.address[3] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[26] get_fullnote.address[4] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[27] get_fullnote.address[5] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[28] get_fullnote.address[6] re clk 2 -.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[29] get_fullnote.address[7] re clk 2 -.names $false fullnote[6] -1 1 -.names $false fullnote[7] -1 1 -.names tone[1] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[1] -1 1 -.names tone[2] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[2] -1 1 -.names tone[3] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[3] -1 1 -.names tone[4] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[4] -1 1 -.names tone[5] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[5] -1 1 -.names tone[6] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[6] -1 1 -.names tone[7] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[7] -1 1 -.names tone[8] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[8] -1 1 -.names tone[9] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[9] -1 1 -.names tone[10] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[10] -1 1 -.names tone[11] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[11] -1 1 -.names tone[12] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[12] -1 1 -.names tone[13] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[13] -1 1 -.names tone[14] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[14] -1 1 -.names tone[15] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[15] -1 1 -.names tone[16] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[16] -1 1 -.names tone[17] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[17] -1 1 -.names tone[18] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[18] -1 1 -.names tone[19] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[19] -1 1 -.names tone[20] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[20] -1 1 -.names tone[21] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[21] -1 1 -.names get_fullnote.address[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[22] -1 1 -.names get_fullnote.address[1] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[23] -1 1 -.names get_fullnote.address[2] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[24] -1 1 -.names get_fullnote.address[3] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[25] -1 1 -.names get_fullnote.address[4] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[26] -1 1 -.names get_fullnote.address[5] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[27] -1 1 -.names get_fullnote.address[6] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[28] -1 1 -.names get_fullnote.address[7] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[29] -1 1 -.names tone[30] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[30] -1 1 -.names $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[0] -1 1 -.names get_fullnote.address[0] tone[22] -1 1 -.names get_fullnote.address[1] tone[23] -1 1 -.names get_fullnote.address[2] tone[24] -1 1 -.names get_fullnote.address[3] tone[25] -1 1 -.names get_fullnote.address[4] tone[26] -1 1 -.names get_fullnote.address[5] tone[27] -1 1 -.names get_fullnote.address[6] tone[28] -1 1 -.names get_fullnote.address[7] tone[29] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif deleted file mode 100644 index 56a80c9fc49..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif +++ /dev/null @@ -1,15942 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model picorv32 -.inputs clk resetn mem_ready mem_rdata[0] mem_rdata[1] mem_rdata[2] mem_rdata[3] mem_rdata[4] mem_rdata[5] mem_rdata[6] mem_rdata[7] mem_rdata[8] mem_rdata[9] mem_rdata[10] mem_rdata[11] mem_rdata[12] mem_rdata[13] mem_rdata[14] mem_rdata[15] mem_rdata[16] mem_rdata[17] mem_rdata[18] mem_rdata[19] mem_rdata[20] mem_rdata[21] mem_rdata[22] mem_rdata[23] mem_rdata[24] mem_rdata[25] mem_rdata[26] mem_rdata[27] mem_rdata[28] mem_rdata[29] mem_rdata[30] mem_rdata[31] pcpi_wr pcpi_rd[0] pcpi_rd[1] pcpi_rd[2] pcpi_rd[3] pcpi_rd[4] pcpi_rd[5] pcpi_rd[6] pcpi_rd[7] pcpi_rd[8] pcpi_rd[9] pcpi_rd[10] pcpi_rd[11] pcpi_rd[12] pcpi_rd[13] pcpi_rd[14] pcpi_rd[15] pcpi_rd[16] pcpi_rd[17] pcpi_rd[18] pcpi_rd[19] pcpi_rd[20] pcpi_rd[21] pcpi_rd[22] pcpi_rd[23] pcpi_rd[24] pcpi_rd[25] pcpi_rd[26] pcpi_rd[27] pcpi_rd[28] pcpi_rd[29] pcpi_rd[30] pcpi_rd[31] pcpi_wait pcpi_ready irq[0] irq[1] irq[2] irq[3] irq[4] irq[5] irq[6] irq[7] irq[8] irq[9] irq[10] irq[11] irq[12] irq[13] irq[14] irq[15] irq[16] irq[17] irq[18] irq[19] irq[20] irq[21] irq[22] irq[23] irq[24] irq[25] irq[26] irq[27] irq[28] irq[29] irq[30] irq[31] -.outputs trap mem_valid mem_instr mem_addr[0] mem_addr[1] mem_addr[2] mem_addr[3] mem_addr[4] mem_addr[5] mem_addr[6] mem_addr[7] mem_addr[8] mem_addr[9] mem_addr[10] mem_addr[11] mem_addr[12] mem_addr[13] mem_addr[14] mem_addr[15] mem_addr[16] mem_addr[17] mem_addr[18] mem_addr[19] mem_addr[20] mem_addr[21] mem_addr[22] mem_addr[23] mem_addr[24] mem_addr[25] mem_addr[26] mem_addr[27] mem_addr[28] mem_addr[29] mem_addr[30] mem_addr[31] mem_wdata[0] mem_wdata[1] mem_wdata[2] mem_wdata[3] mem_wdata[4] mem_wdata[5] mem_wdata[6] mem_wdata[7] mem_wdata[8] mem_wdata[9] mem_wdata[10] mem_wdata[11] mem_wdata[12] mem_wdata[13] mem_wdata[14] mem_wdata[15] mem_wdata[16] mem_wdata[17] mem_wdata[18] mem_wdata[19] mem_wdata[20] mem_wdata[21] mem_wdata[22] mem_wdata[23] mem_wdata[24] mem_wdata[25] mem_wdata[26] mem_wdata[27] mem_wdata[28] mem_wdata[29] mem_wdata[30] mem_wdata[31] mem_wstrb[0] mem_wstrb[1] mem_wstrb[2] mem_wstrb[3] mem_la_read mem_la_write mem_la_addr[0] mem_la_addr[1] mem_la_addr[2] mem_la_addr[3] mem_la_addr[4] mem_la_addr[5] mem_la_addr[6] mem_la_addr[7] mem_la_addr[8] mem_la_addr[9] mem_la_addr[10] mem_la_addr[11] mem_la_addr[12] mem_la_addr[13] mem_la_addr[14] mem_la_addr[15] mem_la_addr[16] mem_la_addr[17] mem_la_addr[18] mem_la_addr[19] mem_la_addr[20] mem_la_addr[21] mem_la_addr[22] mem_la_addr[23] mem_la_addr[24] mem_la_addr[25] mem_la_addr[26] mem_la_addr[27] mem_la_addr[28] mem_la_addr[29] mem_la_addr[30] mem_la_addr[31] mem_la_wdata[0] mem_la_wdata[1] mem_la_wdata[2] mem_la_wdata[3] mem_la_wdata[4] mem_la_wdata[5] mem_la_wdata[6] mem_la_wdata[7] mem_la_wdata[8] mem_la_wdata[9] mem_la_wdata[10] mem_la_wdata[11] mem_la_wdata[12] mem_la_wdata[13] mem_la_wdata[14] mem_la_wdata[15] mem_la_wdata[16] mem_la_wdata[17] mem_la_wdata[18] mem_la_wdata[19] mem_la_wdata[20] mem_la_wdata[21] mem_la_wdata[22] mem_la_wdata[23] mem_la_wdata[24] mem_la_wdata[25] mem_la_wdata[26] mem_la_wdata[27] mem_la_wdata[28] mem_la_wdata[29] mem_la_wdata[30] mem_la_wdata[31] mem_la_wstrb[0] mem_la_wstrb[1] mem_la_wstrb[2] mem_la_wstrb[3] pcpi_valid pcpi_insn[0] pcpi_insn[1] pcpi_insn[2] pcpi_insn[3] pcpi_insn[4] pcpi_insn[5] pcpi_insn[6] pcpi_insn[7] pcpi_insn[8] pcpi_insn[9] pcpi_insn[10] pcpi_insn[11] pcpi_insn[12] pcpi_insn[13] pcpi_insn[14] pcpi_insn[15] pcpi_insn[16] pcpi_insn[17] pcpi_insn[18] pcpi_insn[19] pcpi_insn[20] pcpi_insn[21] pcpi_insn[22] pcpi_insn[23] pcpi_insn[24] pcpi_insn[25] pcpi_insn[26] pcpi_insn[27] pcpi_insn[28] pcpi_insn[29] pcpi_insn[30] pcpi_insn[31] pcpi_rs1[0] pcpi_rs1[1] pcpi_rs1[2] pcpi_rs1[3] pcpi_rs1[4] pcpi_rs1[5] pcpi_rs1[6] pcpi_rs1[7] pcpi_rs1[8] pcpi_rs1[9] pcpi_rs1[10] pcpi_rs1[11] pcpi_rs1[12] pcpi_rs1[13] pcpi_rs1[14] pcpi_rs1[15] pcpi_rs1[16] pcpi_rs1[17] pcpi_rs1[18] pcpi_rs1[19] pcpi_rs1[20] pcpi_rs1[21] pcpi_rs1[22] pcpi_rs1[23] pcpi_rs1[24] pcpi_rs1[25] pcpi_rs1[26] pcpi_rs1[27] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs1[30] pcpi_rs1[31] pcpi_rs2[0] pcpi_rs2[1] pcpi_rs2[2] pcpi_rs2[3] pcpi_rs2[4] pcpi_rs2[5] pcpi_rs2[6] pcpi_rs2[7] pcpi_rs2[8] pcpi_rs2[9] pcpi_rs2[10] pcpi_rs2[11] pcpi_rs2[12] pcpi_rs2[13] pcpi_rs2[14] pcpi_rs2[15] pcpi_rs2[16] pcpi_rs2[17] pcpi_rs2[18] pcpi_rs2[19] pcpi_rs2[20] pcpi_rs2[21] pcpi_rs2[22] pcpi_rs2[23] pcpi_rs2[24] pcpi_rs2[25] pcpi_rs2[26] pcpi_rs2[27] pcpi_rs2[28] pcpi_rs2[29] pcpi_rs2[30] pcpi_rs2[31] eoi[0] eoi[1] eoi[2] eoi[3] eoi[4] eoi[5] eoi[6] eoi[7] eoi[8] eoi[9] eoi[10] eoi[11] eoi[12] eoi[13] eoi[14] eoi[15] eoi[16] eoi[17] eoi[18] eoi[19] eoi[20] eoi[21] eoi[22] eoi[23] eoi[24] eoi[25] eoi[26] eoi[27] eoi[28] eoi[29] eoi[30] eoi[31] trace_valid trace_data[0] trace_data[1] trace_data[2] trace_data[3] trace_data[4] trace_data[5] trace_data[6] trace_data[7] trace_data[8] trace_data[9] trace_data[10] trace_data[11] trace_data[12] trace_data[13] trace_data[14] trace_data[15] trace_data[16] trace_data[17] trace_data[18] trace_data[19] trace_data[20] trace_data[21] trace_data[22] trace_data[23] trace_data[24] trace_data[25] trace_data[26] trace_data[27] trace_data[28] trace_data[29] trace_data[30] trace_data[31] trace_data[32] trace_data[33] trace_data[34] trace_data[35] -.names $false -.names $true -1 -.names $undef -.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[30] mem_la_wdata[6] pcpi_rs2[14] mem_la_wdata[30] -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1410 mem_la_wdata[30] mem_wdata[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14337 -001 1 -011 1 -110 1 -111 1 -.names mem_la_write trap $abc$16053$new_n1410 -10 1 -.names resetn mem_do_wdata mem_state[1] mem_state[0] mem_la_write -1100 1 -.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[29] mem_la_wdata[5] pcpi_rs2[13] mem_la_wdata[29] -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1410 mem_la_wdata[29] mem_wdata[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14339 -001 1 -011 1 -110 1 -111 1 -.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[28] mem_la_wdata[4] pcpi_rs2[12] mem_la_wdata[28] -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1410 mem_la_wdata[28] mem_wdata[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14341 -001 1 -011 1 -110 1 -111 1 -.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[27] mem_la_wdata[3] pcpi_rs2[11] mem_la_wdata[27] -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1410 mem_la_wdata[27] mem_wdata[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14343 -001 1 -011 1 -110 1 -111 1 -.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[26] mem_la_wdata[2] pcpi_rs2[10] mem_la_wdata[26] -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1410 mem_la_wdata[26] mem_wdata[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14345 -001 1 -011 1 -110 1 -111 1 -.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[25] mem_la_wdata[1] pcpi_rs2[9] mem_la_wdata[25] -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1410 mem_la_wdata[25] mem_wdata[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14347 -001 1 -011 1 -110 1 -111 1 -.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[24] mem_la_wdata[0] pcpi_rs2[8] mem_la_wdata[24] -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1410 mem_la_wdata[24] mem_wdata[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14349 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1425 pcpi_rs2[23] mem_la_wdata[7] mem_la_wdata[23] -001 1 -011 1 -110 1 -111 1 -.names mem_wordsize[0] mem_wordsize[1] $abc$16053$new_n1425 -00 1 -11 1 -.names $abc$16053$new_n1410 mem_la_wdata[23] mem_wdata[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14351 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1425 pcpi_rs2[22] mem_la_wdata[6] mem_la_wdata[22] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[22] mem_wdata[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14353 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1425 pcpi_rs2[21] mem_la_wdata[5] mem_la_wdata[21] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[21] mem_wdata[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14355 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1425 pcpi_rs2[20] mem_la_wdata[4] mem_la_wdata[20] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[20] mem_wdata[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14357 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1425 pcpi_rs2[19] mem_la_wdata[3] mem_la_wdata[19] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[19] mem_wdata[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14359 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1425 pcpi_rs2[18] mem_la_wdata[2] mem_la_wdata[18] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[18] mem_wdata[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14361 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1425 pcpi_rs2[17] mem_la_wdata[1] mem_la_wdata[17] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[17] mem_wdata[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14363 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1425 pcpi_rs2[16] mem_la_wdata[0] mem_la_wdata[16] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[16] mem_wdata[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14365 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1442 mem_la_wdata[7] pcpi_rs2[15] mem_la_wdata[15] -001 1 -011 1 -110 1 -111 1 -.names mem_wordsize[1] mem_wordsize[0] $abc$16053$new_n1442 -10 1 -.names $abc$16053$new_n1410 mem_la_wdata[15] mem_wdata[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14367 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1442 mem_la_wdata[6] pcpi_rs2[14] mem_la_wdata[14] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[14] mem_wdata[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14369 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1442 mem_la_wdata[5] pcpi_rs2[13] mem_la_wdata[13] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[13] mem_wdata[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14371 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1442 mem_la_wdata[4] pcpi_rs2[12] mem_la_wdata[12] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[12] mem_wdata[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14373 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1442 mem_la_wdata[3] pcpi_rs2[11] mem_la_wdata[11] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[11] mem_wdata[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14375 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1442 mem_la_wdata[2] pcpi_rs2[10] mem_la_wdata[10] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[10] mem_wdata[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14377 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1442 mem_la_wdata[1] pcpi_rs2[9] mem_la_wdata[9] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[9] mem_wdata[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14379 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1442 mem_la_wdata[0] pcpi_rs2[8] mem_la_wdata[8] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[8] mem_wdata[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14381 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[7] mem_wdata[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14383 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[6] mem_wdata[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14385 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[5] mem_wdata[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14387 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[4] mem_wdata[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14389 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[3] mem_wdata[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14391 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[2] mem_wdata[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14393 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[1] mem_wdata[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14395 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1410 mem_la_wdata[0] mem_wdata[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14397 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1475 $abc$16053$new_n1467 mem_state[0] mem_do_wdata $abc$16053$auto$rtlil.cc:2693:MuxGate$14401 -0010 1 -0011 1 -1010 1 -1011 1 -1100 1 -1110 1 -1111 1 -.names $abc$16053$new_n1468 trap resetn $abc$16053$new_n1474 mem_do_rinst $abc$16053$new_n1467 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names $abc$16053$new_n1473 $abc$16053$new_n1471 $abc$16053$new_n1469 $abc$16053$new_n1468 -110 1 -.names mem_state[1] mem_state[0] $abc$16053$new_n1470 mem_do_rdata $abc$16053$new_n1469 -0000 1 -0001 1 -0011 1 -.names mem_do_rinst mem_do_prefetch $abc$16053$new_n1470 -00 1 -.names mem_state[1] mem_state[0] $abc$16053$new_n1472 mem_do_wdata $abc$16053$new_n1471 -0000 1 -0010 1 -0100 1 -0101 1 -1000 1 -1001 1 -.names mem_ready mem_valid $abc$16053$new_n1472 -11 1 -.names resetn trap $abc$16053$new_n1473 -10 1 -.names mem_state[1] mem_state[0] $abc$16053$new_n1474 -11 1 -.names $abc$16053$new_n1473 mem_state[1] mem_state[0] mem_do_rdata mem_do_rinst $abc$16053$new_n1475 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[30] $abc$16053$new_n1477 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14403 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[30] instr_jal decoded_imm_j[30] $abc$16053$new_n1477 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names instr_lui instr_auipc $abc$16053$new_n1478 -00 1 -.names decoder_trigger decoder_pseudo_trigger $abc$16053$new_n1479 -10 1 -.names is_beq_bne_blt_bge_bltu_bgeu instr_jalr is_lb_lh_lw_lbu_lhu is_sb_sh_sw is_alu_reg_imm $abc$16053$new_n1480 -00000 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[29] $abc$16053$new_n1482 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14405 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[29] instr_jal decoded_imm_j[29] $abc$16053$new_n1482 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[28] $abc$16053$new_n1484 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14407 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[28] instr_jal decoded_imm_j[28] $abc$16053$new_n1484 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[27] $abc$16053$new_n1486 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14409 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[27] instr_jal decoded_imm_j[27] $abc$16053$new_n1486 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[26] $abc$16053$new_n1488 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14411 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[26] instr_jal decoded_imm_j[26] $abc$16053$new_n1488 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[25] $abc$16053$new_n1490 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14413 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[25] instr_jal decoded_imm_j[25] $abc$16053$new_n1490 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[24] $abc$16053$new_n1492 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14415 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[24] instr_jal decoded_imm_j[24] $abc$16053$new_n1492 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[23] $abc$16053$new_n1494 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14417 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[23] instr_jal decoded_imm_j[23] $abc$16053$new_n1494 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[22] $abc$16053$new_n1496 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14419 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[22] instr_jal decoded_imm_j[22] $abc$16053$new_n1496 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[21] $abc$16053$new_n1498 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14421 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[21] instr_jal decoded_imm_j[21] $abc$16053$new_n1498 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[20] $abc$16053$new_n1500 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14423 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[20] instr_jal decoded_imm_j[20] $abc$16053$new_n1500 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[19] $abc$16053$new_n1502 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14425 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[19] instr_jal decoded_imm_j[19] $abc$16053$new_n1502 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[18] $abc$16053$new_n1504 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14427 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[18] instr_jal decoded_imm_j[18] $abc$16053$new_n1504 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[17] $abc$16053$new_n1506 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14429 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[17] instr_jal decoded_imm_j[17] $abc$16053$new_n1506 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[16] $abc$16053$new_n1508 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14431 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[16] instr_jal decoded_imm_j[16] $abc$16053$new_n1508 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[15] $abc$16053$new_n1510 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14433 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[15] instr_jal decoded_imm_j[15] $abc$16053$new_n1510 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[14] $abc$16053$new_n1512 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14435 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[14] instr_jal decoded_imm_j[14] $abc$16053$new_n1512 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[13] $abc$16053$new_n1514 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14437 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[13] instr_jal decoded_imm_j[13] $abc$16053$new_n1514 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[12] $abc$16053$new_n1516 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14439 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1478 mem_rdata_q[12] instr_jal decoded_imm_j[12] $abc$16053$new_n1516 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1518 decoded_imm[11] $abc$16053$new_n1519 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14441 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[11] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1518 -11111 1 -.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[31] mem_rdata_q[7] $abc$16053$new_n1519 -0000 1 -0001 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1521 decoded_imm[10] mem_rdata_q[30] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14443 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[10] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1521 -11111 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1523 decoded_imm[9] mem_rdata_q[29] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14445 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[9] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1523 -11111 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1525 decoded_imm[8] mem_rdata_q[28] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14447 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[8] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1525 -11111 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1527 decoded_imm[7] mem_rdata_q[27] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14449 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[7] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1527 -11111 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1529 decoded_imm[6] mem_rdata_q[26] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14451 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[6] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1529 -11111 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1531 decoded_imm[5] mem_rdata_q[25] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14453 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[5] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1531 -11111 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1533 decoded_imm[4] $abc$16053$new_n1534 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14455 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[4] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1533 -11111 1 -.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[11] mem_rdata_q[24] $abc$16053$new_n1534 -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1536 decoded_imm[3] $abc$16053$new_n1537 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14457 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_jal decoded_imm_j[3] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1536 -11111 1 -.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[10] mem_rdata_q[23] $abc$16053$new_n1537 -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n1479 decoded_imm[2] $abc$16053$new_n1539 $abc$16053$new_n1540 $abc$16053$auto$rtlil.cc:2693:MuxGate$14459 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instr_jal decoded_imm_j[2] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1539 -1111 1 -.names $abc$16053$new_n1480 is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[9] mem_rdata_q[22] $abc$16053$new_n1540 -00001 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names $abc$16053$new_n1479 $abc$16053$new_n1542 decoded_imm[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14461 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1480 $abc$16053$new_n1543 decoded_imm_j[1] $abc$16053$new_n1478 instr_jal $abc$16053$new_n1542 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[8] mem_rdata_q[21] $abc$16053$new_n1543 -0000 1 -0010 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names $abc$16053$new_n1479 decoded_imm[0] $abc$16053$new_n1545 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14463 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names is_sb_sh_sw mem_rdata_q[7] mem_rdata_q[20] is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1545 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$16053$new_n1472 mem_rdata[10] mem_rdata_q[10] mem_rdata_latched[10] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[10] decoded_rd[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14465 -001 1 -011 1 -110 1 -111 1 -.names mem_do_rinst $abc$16053$new_n1549 $abc$16053$new_n1548 -10 1 -.names resetn mem_do_rinst $abc$16053$new_n1550 $abc$16053$new_n1551 $abc$16053$new_n1474 $abc$16053$new_n1549 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -.names $abc$16053$new_n1472 mem_state[0] mem_state[1] $abc$16053$new_n1550 -101 1 -110 1 -111 1 -.names mem_do_wdata mem_do_rdata $abc$16053$new_n1551 -00 1 -.names $abc$16053$new_n1472 mem_rdata[9] mem_rdata_q[9] mem_rdata_latched[9] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[9] decoded_rd[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14467 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[8] mem_rdata_q[8] mem_rdata_latched[8] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[8] decoded_rd[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14469 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[7] mem_rdata_q[7] mem_rdata_latched[7] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[7] decoded_rd[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14471 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[31] mem_rdata_q[31] mem_rdata_latched[31] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14473 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14475 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14477 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14479 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14481 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14483 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14485 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14487 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14489 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14491 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14493 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[19] mem_rdata_q[19] mem_rdata_latched[19] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[19] decoded_imm_j[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14495 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[18] mem_rdata_q[18] mem_rdata_latched[18] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[18] decoded_imm_j[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14497 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[17] mem_rdata_q[17] mem_rdata_latched[17] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[17] decoded_imm_j[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14499 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[16] mem_rdata_q[16] mem_rdata_latched[16] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[16] decoded_imm_j[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14501 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[15] mem_rdata_q[15] mem_rdata_latched[15] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[15] decoded_imm_j[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14503 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[14] mem_rdata_q[14] mem_rdata_latched[14] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[14] decoded_imm_j[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14505 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[13] mem_rdata_q[13] mem_rdata_latched[13] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[13] decoded_imm_j[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14507 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[12] mem_rdata_q[12] mem_rdata_latched[12] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[12] decoded_imm_j[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14509 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[20] mem_rdata_q[20] mem_rdata_latched[20] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[20] decoded_imm_j[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14511 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[30] mem_rdata_q[30] mem_rdata_latched[30] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[30] decoded_imm_j[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14513 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[29] mem_rdata_q[29] mem_rdata_latched[29] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[29] decoded_imm_j[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14515 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[28] mem_rdata_q[28] mem_rdata_latched[28] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[28] decoded_imm_j[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14517 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[27] mem_rdata_q[27] mem_rdata_latched[27] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[27] decoded_imm_j[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14519 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[26] mem_rdata_q[26] mem_rdata_latched[26] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[26] decoded_imm_j[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14521 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[25] mem_rdata_q[25] mem_rdata_latched[25] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[25] decoded_imm_j[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14523 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[24] mem_rdata_q[24] mem_rdata_latched[24] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[24] decoded_imm_j[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14525 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[23] mem_rdata_q[23] mem_rdata_latched[23] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[23] decoded_imm_j[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14527 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[22] mem_rdata_q[22] mem_rdata_latched[22] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[22] decoded_imm_j[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14529 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[21] mem_rdata_q[21] mem_rdata_latched[21] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[21] decoded_imm_j[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14531 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1609 latched_rd[3] $abc$16053$new_n1612 decoded_rd[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14535 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names resetn $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1612 $abc$16053$new_n1609 -1001 1 -1011 1 -1110 1 -1111 1 -.names cpu_state[3] $abc$16053$new_n1611 cpu_state[1] cpu_state[0] cpu_state[2] $abc$16053$new_n1610 -11000 1 -.names cpu_state[7] cpu_state[6] cpu_state[4] cpu_state[5] $abc$16053$new_n1611 -0000 1 -.names $abc$16053$new_n1614 $abc$16053$new_n1613 $abc$16053$new_n1612 -11 1 -.names cpu_state[3] cpu_state[1] cpu_state[0] cpu_state[2] $abc$16053$new_n1613 -0000 1 -.names cpu_state[6] cpu_state[7] cpu_state[4] cpu_state[5] $abc$16053$new_n1614 -1000 1 -.names $abc$16053$new_n1609 latched_rd[2] $abc$16053$new_n1612 decoded_rd[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14539 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1609 latched_rd[1] $abc$16053$new_n1612 decoded_rd[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14543 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1609 latched_rd[0] $abc$16053$new_n1612 decoded_rd[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14547 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[30] decoded_imm[30] $abc$16053$new_n1625 $abc$16053$auto$rtlil.cc:2693:MuxGate$14549 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names resetn $abc$16053$new_n1620 $abc$16053$new_n1619 -10 1 -.names $abc$16053$new_n1622 $abc$16053$new_n1621 $abc$16053$new_n1620 -00 1 -.names cpu_state[4] $abc$16053$new_n1613 cpu_state[7] cpu_state[6] cpu_state[5] $abc$16053$new_n1621 -11000 1 -.names $abc$16053$new_n1613 cpu_state[5] cpu_state[7] cpu_state[6] cpu_state[4] $abc$16053$new_n1622 -11000 1 -.names $abc$16053$new_n1624 $abc$16053$new_n1621 $abc$16053$new_n1623 -00 1 -.names is_lui_auipc_jal is_jalr_addi_slti_sltiu_xori_ori_andi $abc$16053$new_n1624 -00 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[30] $abc$16053$new_n1625 -0001 1 -0011 1 -1010 1 -1011 1 -.names decoded_rs2[4] decoded_rs2[3] decoded_rs2[2] decoded_rs2[1] decoded_rs2[0] $abc$16053$new_n1626 -00000 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[29] decoded_imm[29] $abc$16053$new_n1628 $abc$16053$auto$rtlil.cc:2693:MuxGate$14551 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[29] $abc$16053$new_n1628 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[28] decoded_imm[28] $abc$16053$new_n1630 $abc$16053$auto$rtlil.cc:2693:MuxGate$14553 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[28] $abc$16053$new_n1630 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[27] decoded_imm[27] $abc$16053$new_n1632 $abc$16053$auto$rtlil.cc:2693:MuxGate$14555 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[27] $abc$16053$new_n1632 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[26] decoded_imm[26] $abc$16053$new_n1634 $abc$16053$auto$rtlil.cc:2693:MuxGate$14557 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[26] $abc$16053$new_n1634 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[25] decoded_imm[25] $abc$16053$new_n1636 $abc$16053$auto$rtlil.cc:2693:MuxGate$14559 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[25] $abc$16053$new_n1636 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[24] decoded_imm[24] $abc$16053$new_n1638 $abc$16053$auto$rtlil.cc:2693:MuxGate$14561 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[24] $abc$16053$new_n1638 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[23] decoded_imm[23] $abc$16053$new_n1640 $abc$16053$auto$rtlil.cc:2693:MuxGate$14563 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[23] $abc$16053$new_n1640 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[22] decoded_imm[22] $abc$16053$new_n1642 $abc$16053$auto$rtlil.cc:2693:MuxGate$14565 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[22] $abc$16053$new_n1642 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[21] decoded_imm[21] $abc$16053$new_n1644 $abc$16053$auto$rtlil.cc:2693:MuxGate$14567 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[21] $abc$16053$new_n1644 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[20] decoded_imm[20] $abc$16053$new_n1646 $abc$16053$auto$rtlil.cc:2693:MuxGate$14569 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[20] $abc$16053$new_n1646 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[19] decoded_imm[19] $abc$16053$new_n1648 $abc$16053$auto$rtlil.cc:2693:MuxGate$14571 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[19] $abc$16053$new_n1648 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[18] decoded_imm[18] $abc$16053$new_n1650 $abc$16053$auto$rtlil.cc:2693:MuxGate$14573 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[18] $abc$16053$new_n1650 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[17] decoded_imm[17] $abc$16053$new_n1652 $abc$16053$auto$rtlil.cc:2693:MuxGate$14575 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[17] $abc$16053$new_n1652 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[16] decoded_imm[16] $abc$16053$new_n1654 $abc$16053$auto$rtlil.cc:2693:MuxGate$14577 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[16] $abc$16053$new_n1654 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[15] decoded_imm[15] $abc$16053$new_n1656 $abc$16053$auto$rtlil.cc:2693:MuxGate$14579 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[15] $abc$16053$new_n1656 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[14] decoded_imm[14] $abc$16053$new_n1658 $abc$16053$auto$rtlil.cc:2693:MuxGate$14581 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[14] $abc$16053$new_n1658 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[13] decoded_imm[13] $abc$16053$new_n1660 $abc$16053$auto$rtlil.cc:2693:MuxGate$14583 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[13] $abc$16053$new_n1660 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[12] decoded_imm[12] $abc$16053$new_n1662 $abc$16053$auto$rtlil.cc:2693:MuxGate$14585 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[12] $abc$16053$new_n1662 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[11] decoded_imm[11] $abc$16053$new_n1664 $abc$16053$auto$rtlil.cc:2693:MuxGate$14587 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[11] $abc$16053$new_n1664 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[10] decoded_imm[10] $abc$16053$new_n1666 $abc$16053$auto$rtlil.cc:2693:MuxGate$14589 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[10] $abc$16053$new_n1666 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[9] decoded_imm[9] $abc$16053$new_n1668 $abc$16053$auto$rtlil.cc:2693:MuxGate$14591 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[9] $abc$16053$new_n1668 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[8] decoded_imm[8] $abc$16053$new_n1670 $abc$16053$auto$rtlil.cc:2693:MuxGate$14593 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[8] $abc$16053$new_n1670 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[7] decoded_imm[7] $abc$16053$new_n1672 $abc$16053$auto$rtlil.cc:2693:MuxGate$14595 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[7] $abc$16053$new_n1672 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[6] decoded_imm[6] $abc$16053$new_n1674 $abc$16053$auto$rtlil.cc:2693:MuxGate$14597 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[6] $abc$16053$new_n1674 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[5] decoded_imm[5] $abc$16053$new_n1676 $abc$16053$auto$rtlil.cc:2693:MuxGate$14599 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[5] $abc$16053$new_n1676 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[4] decoded_imm[4] $abc$16053$new_n1678 $abc$16053$auto$rtlil.cc:2693:MuxGate$14601 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[4] $abc$16053$new_n1678 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[3] decoded_imm[3] $abc$16053$new_n1680 $abc$16053$auto$rtlil.cc:2693:MuxGate$14603 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[3] $abc$16053$new_n1680 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[2] decoded_imm[2] $abc$16053$new_n1682 $abc$16053$auto$rtlil.cc:2693:MuxGate$14605 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[2] $abc$16053$new_n1682 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[1] decoded_imm[1] $abc$16053$new_n1684 $abc$16053$auto$rtlil.cc:2693:MuxGate$14607 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[1] $abc$16053$new_n1684 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[0] decoded_imm[0] $abc$16053$new_n1686 $abc$16053$auto$rtlil.cc:2693:MuxGate$14609 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[0] $abc$16053$new_n1686 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n1691 $abc$16053$new_n1748 $abc$16053$new_n1747 $abc$16053$new_n1690 -100 1 -.names $abc$16053$new_n1692 $abc$16053$new_n1745 $abc$16053$new_n1743 $abc$16053$new_n1741 $abc$16053$new_n1739 $abc$16053$new_n1691 -10000 1 -.names $abc$16053$new_n1693 $abc$16053$new_n1737 $abc$16053$new_n1692 -10 1 -.names $abc$16053$new_n1694 $abc$16053$new_n1735 $abc$16053$new_n1693 -10 1 -.names $abc$16053$new_n1695 $abc$16053$new_n1733 $abc$16053$new_n1731 $abc$16053$new_n1694 -100 1 -.names $abc$16053$new_n1696 $abc$16053$new_n1729 $abc$16053$new_n1728 $abc$16053$new_n1727 $abc$16053$new_n1725 $abc$16053$new_n1695 -10000 1 -.names $abc$16053$new_n1697 $abc$16053$new_n1723 $abc$16053$new_n1722 $abc$16053$new_n1721 $abc$16053$new_n1719 $abc$16053$new_n1696 -10000 1 -.names $abc$16053$new_n1698 $abc$16053$new_n1718 $abc$16053$new_n1717 $abc$16053$new_n1715 $abc$16053$new_n1697 -1000 1 -.names $abc$16053$new_n1699 $abc$16053$new_n1713 $abc$16053$new_n1698 -10 1 -.names $abc$16053$new_n1700 $abc$16053$new_n1711 $abc$16053$new_n1699 -10 1 -.names $abc$16053$new_n1701 $abc$16053$new_n1710 $abc$16053$new_n1700 -10 1 -.names $abc$16053$new_n1702 $abc$16053$new_n1708 $abc$16053$new_n1707 $abc$16053$new_n1701 -100 1 -.names $abc$16053$new_n1706 $abc$16053$new_n1703 $abc$16053$new_n1702 -00 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1705 reg_next_pc[3] $abc$16053$new_n1703 -000 1 -010 1 -110 1 -111 1 -.names latched_branch latched_store $abc$16053$new_n1704 -11 1 -.names latched_stalu alu_out_q[3] reg_out[3] $abc$16053$new_n1705 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[2] alu_out_q[2] reg_out[2] $abc$16053$new_n1706 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[5] alu_out_q[5] reg_out[5] $abc$16053$new_n1707 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1709 reg_next_pc[4] $abc$16053$new_n1708 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[4] reg_out[4] $abc$16053$new_n1709 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[6] alu_out_q[6] reg_out[6] $abc$16053$new_n1710 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1712 reg_next_pc[7] $abc$16053$new_n1711 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[7] reg_out[7] $abc$16053$new_n1712 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1714 reg_next_pc[8] $abc$16053$new_n1713 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[8] reg_out[8] $abc$16053$new_n1714 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1716 reg_next_pc[11] $abc$16053$new_n1715 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[11] reg_out[11] $abc$16053$new_n1716 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[10] alu_out_q[10] reg_out[10] $abc$16053$new_n1717 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[9] alu_out_q[9] reg_out[9] $abc$16053$new_n1718 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1720 reg_next_pc[15] $abc$16053$new_n1719 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[15] reg_out[15] $abc$16053$new_n1720 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[14] alu_out_q[14] reg_out[14] $abc$16053$new_n1721 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[13] alu_out_q[13] reg_out[13] $abc$16053$new_n1722 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1724 reg_next_pc[12] $abc$16053$new_n1723 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[12] reg_out[12] $abc$16053$new_n1724 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1726 reg_next_pc[19] $abc$16053$new_n1725 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[19] reg_out[19] $abc$16053$new_n1726 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[18] alu_out_q[18] reg_out[18] $abc$16053$new_n1727 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[17] alu_out_q[17] reg_out[17] $abc$16053$new_n1728 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1730 reg_next_pc[16] $abc$16053$new_n1729 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[16] reg_out[16] $abc$16053$new_n1730 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1732 reg_next_pc[21] $abc$16053$new_n1731 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[21] reg_out[21] $abc$16053$new_n1732 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1734 reg_next_pc[20] $abc$16053$new_n1733 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[20] reg_out[20] $abc$16053$new_n1734 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1736 reg_next_pc[22] $abc$16053$new_n1735 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[22] reg_out[22] $abc$16053$new_n1736 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1738 reg_next_pc[23] $abc$16053$new_n1737 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[23] reg_out[23] $abc$16053$new_n1738 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1740 reg_next_pc[27] $abc$16053$new_n1739 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[27] reg_out[27] $abc$16053$new_n1740 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1742 reg_next_pc[26] $abc$16053$new_n1741 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[26] reg_out[26] $abc$16053$new_n1742 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1744 reg_next_pc[25] $abc$16053$new_n1743 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[25] reg_out[25] $abc$16053$new_n1744 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1746 reg_next_pc[24] $abc$16053$new_n1745 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[24] reg_out[24] $abc$16053$new_n1746 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[29] alu_out_q[29] reg_out[29] $abc$16053$new_n1747 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1749 reg_next_pc[28] $abc$16053$new_n1748 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[28] reg_out[28] $abc$16053$new_n1749 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1704 latched_stalu reg_next_pc[30] alu_out_q[30] reg_out[30] $abc$16053$new_n1750 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n1748 decoded_imm_j[28] decoded_imm_j[29] $abc$16053$new_n1747 $abc$16053$new_n1752 $abc$16053$new_n1751 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1741 decoded_imm_j[26] decoded_imm_j[27] $abc$16053$new_n1739 $abc$16053$new_n1753 $abc$16053$new_n1752 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1745 decoded_imm_j[24] decoded_imm_j[25] $abc$16053$new_n1743 $abc$16053$new_n1754 $abc$16053$new_n1753 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1735 decoded_imm_j[22] decoded_imm_j[23] $abc$16053$new_n1737 $abc$16053$new_n1755 $abc$16053$new_n1754 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1733 decoded_imm_j[20] decoded_imm_j[21] $abc$16053$new_n1731 $abc$16053$new_n1756 $abc$16053$new_n1755 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1727 decoded_imm_j[18] decoded_imm_j[19] $abc$16053$new_n1725 $abc$16053$new_n1757 $abc$16053$new_n1756 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1729 decoded_imm_j[16] decoded_imm_j[17] $abc$16053$new_n1728 $abc$16053$new_n1758 $abc$16053$new_n1757 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1721 decoded_imm_j[14] decoded_imm_j[15] $abc$16053$new_n1719 $abc$16053$new_n1759 $abc$16053$new_n1758 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1723 decoded_imm_j[12] decoded_imm_j[13] $abc$16053$new_n1722 $abc$16053$new_n1760 $abc$16053$new_n1759 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1717 decoded_imm_j[10] decoded_imm_j[11] $abc$16053$new_n1715 $abc$16053$new_n1761 $abc$16053$new_n1760 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1713 decoded_imm_j[8] decoded_imm_j[9] $abc$16053$new_n1718 $abc$16053$new_n1762 $abc$16053$new_n1761 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1710 decoded_imm_j[6] decoded_imm_j[7] $abc$16053$new_n1711 $abc$16053$new_n1763 $abc$16053$new_n1762 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n1708 decoded_imm_j[4] decoded_imm_j[5] $abc$16053$new_n1707 $abc$16053$new_n1764 $abc$16053$new_n1763 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names decoded_imm_j[3] decoded_imm_j[2] $abc$16053$new_n1765 $abc$16053$new_n1706 $abc$16053$new_n1703 $abc$16053$new_n1764 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10001 1 -10011 1 -10111 1 -11011 1 -.names decoded_imm_j[1] $abc$16053$new_n1704 $abc$16053$new_n1766 reg_next_pc[1] $abc$16053$new_n1765 -1001 1 -1011 1 -1100 1 -1101 1 -.names latched_stalu alu_out_q[1] reg_out[1] $abc$16053$new_n1766 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1748 decoded_imm_j[28] $abc$16053$new_n1752 $abc$16053$new_n1769 -001 1 -100 1 -101 1 -111 1 -.names $abc$16053$new_n1778 $abc$16053$new_n1743 $abc$16053$new_n1777 -10 1 -.names $abc$16053$new_n1692 $abc$16053$new_n1745 $abc$16053$new_n1778 -10 1 -.names decoded_imm_j[24] $abc$16053$new_n1745 $abc$16053$new_n1754 $abc$16053$new_n1787 -000 1 -100 1 -101 1 -110 1 -.names $abc$16053$new_n1735 decoded_imm_j[22] $abc$16053$new_n1755 $abc$16053$new_n1793 -001 1 -100 1 -101 1 -111 1 -.names $abc$16053$new_n1733 decoded_imm_j[20] $abc$16053$new_n1756 $abc$16053$new_n1800 -001 1 -100 1 -101 1 -111 1 -.names $abc$16053$new_n1809 $abc$16053$new_n1728 $abc$16053$new_n1808 -10 1 -.names $abc$16053$new_n1696 $abc$16053$new_n1729 $abc$16053$new_n1809 -10 1 -.names decoded_imm_j[16] $abc$16053$new_n1729 $abc$16053$new_n1758 $abc$16053$new_n1818 -000 1 -100 1 -101 1 -110 1 -.names $abc$16053$new_n1826 $abc$16053$new_n1722 $abc$16053$new_n1825 -10 1 -.names $abc$16053$new_n1697 $abc$16053$new_n1723 $abc$16053$new_n1826 -10 1 -.names $abc$16053$new_n1723 decoded_imm_j[12] $abc$16053$new_n1760 $abc$16053$new_n1835 -001 1 -100 1 -101 1 -111 1 -.names $abc$16053$new_n1698 $abc$16053$new_n1718 $abc$16053$new_n1842 -10 1 -.names $abc$16053$new_n1713 decoded_imm_j[8] $abc$16053$new_n1762 $abc$16053$new_n1851 -001 1 -100 1 -101 1 -111 1 -.names $abc$16053$new_n1710 decoded_imm_j[6] $abc$16053$new_n1763 $abc$16053$new_n1858 -001 1 -100 1 -101 1 -111 1 -.names $abc$16053$new_n1612 decoder_trigger reg_next_pc[6] $abc$16053$new_n1860 $abc$16053$new_n1710 $abc$16053$auto$rtlil.cc:2693:MuxGate$14659 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instr_jal $abc$16053$new_n1710 decoded_imm_j[6] $abc$16053$new_n1763 $abc$16053$new_n1701 $abc$16053$new_n1860 -00000 1 -00010 1 -00100 1 -00110 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 decoder_trigger reg_next_pc[4] $abc$16053$new_n1866 $abc$16053$new_n1708 $abc$16053$auto$rtlil.cc:2693:MuxGate$14663 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instr_jal $abc$16053$new_n1708 decoded_imm_j[4] $abc$16053$new_n1764 $abc$16053$new_n1702 $abc$16053$new_n1866 -00000 1 -00010 1 -00100 1 -00110 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1872 reg_next_pc[2] $abc$16053$new_n1706 decoder_trigger $abc$16053$auto$rtlil.cc:2693:MuxGate$14667 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names decoder_trigger $abc$16053$new_n1706 decoded_imm_j[2] $abc$16053$new_n1765 instr_jal $abc$16053$new_n1872 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11001 1 -11111 1 -.names $abc$16053$new_n1874 reg_next_pc[1] $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$14669 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1875 decoder_trigger instr_jal decoded_imm_j[1] $abc$16053$new_n1874 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11111 1 -.names $abc$16053$new_n1704 $abc$16053$new_n1766 reg_next_pc[1] $abc$16053$new_n1875 -000 1 -010 1 -110 1 -111 1 -.names reg_next_pc[0] $abc$16053$new_n1612 $abc$16053$new_n1704 $abc$16053$auto$rtlil.cc:2693:MuxGate$14671 -100 1 -101 1 -110 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1750 reg_pc[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14673 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1747 reg_pc[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14675 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1748 reg_pc[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14677 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1739 reg_pc[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14679 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1741 reg_pc[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14681 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1743 reg_pc[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14683 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1745 reg_pc[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14685 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1737 reg_pc[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14687 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1735 reg_pc[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14689 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1731 reg_pc[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14691 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1733 reg_pc[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14693 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1725 reg_pc[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14695 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1727 reg_pc[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14697 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1728 reg_pc[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14699 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1729 reg_pc[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14701 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1719 reg_pc[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14703 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1721 reg_pc[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14705 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1722 reg_pc[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14707 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1723 reg_pc[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14709 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1715 reg_pc[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14711 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1717 reg_pc[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14713 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1718 reg_pc[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14715 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1713 reg_pc[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14717 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1711 reg_pc[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14719 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1710 reg_pc[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14721 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1707 reg_pc[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14723 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1708 reg_pc[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14725 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1703 reg_pc[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14727 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1706 reg_pc[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14729 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1875 reg_pc[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14731 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1612 reg_pc[0] reg_next_pc[0] $abc$16053$new_n1704 $abc$16053$auto$rtlil.cc:2693:MuxGate$14733 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names count_instr[62] $abc$16053$new_n1909 $abc$16053$auto$rtlil.cc:2693:MuxGate$14735 -01 1 -10 1 -.names count_instr[58] count_instr[59] count_instr[60] count_instr[61] $abc$16053$new_n1910 $abc$16053$new_n1909 -11111 1 -.names count_instr[54] count_instr[55] count_instr[56] count_instr[57] $abc$16053$new_n1911 $abc$16053$new_n1910 -11111 1 -.names count_instr[50] count_instr[51] count_instr[52] count_instr[53] $abc$16053$new_n1912 $abc$16053$new_n1911 -11111 1 -.names count_instr[46] count_instr[47] count_instr[48] count_instr[49] $abc$16053$new_n1913 $abc$16053$new_n1912 -11111 1 -.names count_instr[42] count_instr[43] count_instr[44] count_instr[45] $abc$16053$new_n1914 $abc$16053$new_n1913 -11111 1 -.names count_instr[38] count_instr[39] count_instr[40] count_instr[41] $abc$16053$new_n1915 $abc$16053$new_n1914 -11111 1 -.names count_instr[34] count_instr[35] count_instr[36] count_instr[37] $abc$16053$new_n1916 $abc$16053$new_n1915 -11111 1 -.names count_instr[30] count_instr[31] count_instr[32] count_instr[33] $abc$16053$new_n1917 $abc$16053$new_n1916 -11111 1 -.names count_instr[26] count_instr[27] count_instr[28] count_instr[29] $abc$16053$new_n1918 $abc$16053$new_n1917 -11111 1 -.names count_instr[22] count_instr[23] count_instr[24] count_instr[25] $abc$16053$new_n1919 $abc$16053$new_n1918 -11111 1 -.names count_instr[18] count_instr[19] count_instr[20] count_instr[21] $abc$16053$new_n1920 $abc$16053$new_n1919 -11111 1 -.names count_instr[14] count_instr[15] count_instr[16] count_instr[17] $abc$16053$new_n1921 $abc$16053$new_n1920 -11111 1 -.names count_instr[10] count_instr[11] count_instr[12] count_instr[13] $abc$16053$new_n1922 $abc$16053$new_n1921 -11111 1 -.names count_instr[6] count_instr[7] count_instr[8] count_instr[9] $abc$16053$new_n1923 $abc$16053$new_n1922 -11111 1 -.names count_instr[2] count_instr[3] count_instr[4] count_instr[5] $abc$16053$new_n1924 $abc$16053$new_n1923 -11111 1 -.names decoder_trigger count_instr[0] count_instr[1] $abc$16053$new_n1614 $abc$16053$new_n1613 $abc$16053$new_n1924 -11111 1 -.names count_instr[61] count_instr[58] count_instr[59] count_instr[60] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14737 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[60] count_instr[58] count_instr[59] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14739 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[59] count_instr[58] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14741 -011 1 -100 1 -101 1 -110 1 -.names count_instr[58] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14743 -01 1 -10 1 -.names count_instr[57] count_instr[54] count_instr[55] count_instr[56] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14745 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[56] count_instr[54] count_instr[55] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14747 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[55] count_instr[54] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14749 -011 1 -100 1 -101 1 -110 1 -.names count_instr[54] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14751 -01 1 -10 1 -.names count_instr[53] count_instr[50] count_instr[51] count_instr[52] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14753 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[52] count_instr[50] count_instr[51] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14755 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[51] count_instr[50] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14757 -011 1 -100 1 -101 1 -110 1 -.names count_instr[50] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14759 -01 1 -10 1 -.names count_instr[49] count_instr[46] count_instr[47] count_instr[48] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14761 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[48] count_instr[46] count_instr[47] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14763 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[47] count_instr[46] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14765 -011 1 -100 1 -101 1 -110 1 -.names count_instr[46] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14767 -01 1 -10 1 -.names count_instr[45] count_instr[42] count_instr[43] count_instr[44] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14769 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[44] count_instr[42] count_instr[43] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14771 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[43] count_instr[42] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14773 -011 1 -100 1 -101 1 -110 1 -.names count_instr[42] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14775 -01 1 -10 1 -.names count_instr[41] count_instr[38] count_instr[39] count_instr[40] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14777 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[40] count_instr[38] count_instr[39] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14779 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[39] count_instr[38] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14781 -011 1 -100 1 -101 1 -110 1 -.names count_instr[38] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14783 -01 1 -10 1 -.names count_instr[37] count_instr[34] count_instr[35] count_instr[36] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14785 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[36] count_instr[34] count_instr[35] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14787 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[35] count_instr[34] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14789 -011 1 -100 1 -101 1 -110 1 -.names count_instr[34] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14791 -01 1 -10 1 -.names count_instr[33] count_instr[30] count_instr[31] count_instr[32] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14793 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[32] count_instr[30] count_instr[31] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14795 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[31] count_instr[30] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14797 -011 1 -100 1 -101 1 -110 1 -.names count_instr[30] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14799 -01 1 -10 1 -.names count_instr[29] count_instr[26] count_instr[27] count_instr[28] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14801 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[28] count_instr[26] count_instr[27] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14803 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[27] count_instr[26] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14805 -011 1 -100 1 -101 1 -110 1 -.names count_instr[26] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14807 -01 1 -10 1 -.names count_instr[25] count_instr[22] count_instr[23] count_instr[24] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14809 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[24] count_instr[22] count_instr[23] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14811 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[23] count_instr[22] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14813 -011 1 -100 1 -101 1 -110 1 -.names count_instr[22] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14815 -01 1 -10 1 -.names count_instr[21] count_instr[18] count_instr[19] count_instr[20] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14817 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_instr[20] count_instr[18] count_instr[19] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14819 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[19] count_instr[18] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14821 -011 1 -100 1 -101 1 -110 1 -.names count_instr[18] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14823 -01 1 -10 1 -.names count_instr[17] count_instr[16] $abc$16053$new_n1970 $abc$16053$auto$rtlil.cc:2693:MuxGate$14825 -011 1 -100 1 -101 1 -110 1 -.names count_instr[14] count_instr[15] $abc$16053$new_n1921 $abc$16053$new_n1970 -111 1 -.names count_instr[16] $abc$16053$new_n1970 $abc$16053$auto$rtlil.cc:2693:MuxGate$14827 -01 1 -10 1 -.names count_instr[15] count_instr[14] $abc$16053$new_n1921 $abc$16053$auto$rtlil.cc:2693:MuxGate$14829 -011 1 -100 1 -101 1 -110 1 -.names count_instr[14] $abc$16053$new_n1921 $abc$16053$auto$rtlil.cc:2693:MuxGate$14831 -01 1 -10 1 -.names count_instr[13] count_instr[12] $abc$16053$new_n1975 $abc$16053$auto$rtlil.cc:2693:MuxGate$14833 -011 1 -100 1 -101 1 -110 1 -.names count_instr[10] count_instr[11] $abc$16053$new_n1922 $abc$16053$new_n1975 -111 1 -.names count_instr[12] $abc$16053$new_n1975 $abc$16053$auto$rtlil.cc:2693:MuxGate$14835 -01 1 -10 1 -.names count_instr[11] count_instr[10] $abc$16053$new_n1922 $abc$16053$auto$rtlil.cc:2693:MuxGate$14837 -011 1 -100 1 -101 1 -110 1 -.names count_instr[10] $abc$16053$new_n1922 $abc$16053$auto$rtlil.cc:2693:MuxGate$14839 -01 1 -10 1 -.names count_instr[9] count_instr[8] $abc$16053$new_n1980 $abc$16053$auto$rtlil.cc:2693:MuxGate$14841 -011 1 -100 1 -101 1 -110 1 -.names count_instr[6] count_instr[7] $abc$16053$new_n1923 $abc$16053$new_n1980 -111 1 -.names count_instr[8] $abc$16053$new_n1980 $abc$16053$auto$rtlil.cc:2693:MuxGate$14843 -01 1 -10 1 -.names count_instr[7] count_instr[6] $abc$16053$new_n1923 $abc$16053$auto$rtlil.cc:2693:MuxGate$14845 -011 1 -100 1 -101 1 -110 1 -.names count_instr[6] $abc$16053$new_n1923 $abc$16053$auto$rtlil.cc:2693:MuxGate$14847 -01 1 -10 1 -.names count_instr[5] count_instr[3] count_instr[4] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14849 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[2] $abc$16053$new_n1924 $abc$16053$new_n1985 -11 1 -.names count_instr[4] count_instr[3] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14851 -011 1 -100 1 -101 1 -110 1 -.names count_instr[3] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14853 -01 1 -10 1 -.names count_instr[2] $abc$16053$new_n1924 $abc$16053$auto$rtlil.cc:2693:MuxGate$14855 -01 1 -10 1 -.names count_instr[1] decoder_trigger count_instr[0] $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$14857 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_instr[0] $abc$16053$new_n1991 $abc$16053$auto$rtlil.cc:2693:MuxGate$14859 -01 1 -10 1 -.names decoder_trigger $abc$16053$new_n1612 $abc$16053$new_n1991 -11 1 -.names $abc$16053$new_n1472 mem_rdata[11] mem_rdata_q[11] mem_rdata_latched[11] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[6] mem_rdata_q[6] mem_rdata_latched[6] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[5] mem_rdata_q[5] mem_rdata_latched[5] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[4] mem_rdata_q[4] mem_rdata_latched[4] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[3] mem_rdata_q[3] mem_rdata_latched[3] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[2] mem_rdata_q[2] mem_rdata_latched[2] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[1] mem_rdata_q[1] mem_rdata_latched[1] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1472 mem_rdata[0] mem_rdata_q[0] mem_rdata_latched[0] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2001 pcpi_rs1[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14923 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n2017 pcpi_rs1[29] decoded_imm[29] $abc$16053$new_n2002 $abc$16053$new_n2019 $abc$16053$new_n2001 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs1[27] decoded_imm[27] pcpi_rs1[28] decoded_imm[28] $abc$16053$new_n2003 $abc$16053$new_n2002 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[25] decoded_imm[25] pcpi_rs1[26] decoded_imm[26] $abc$16053$new_n2004 $abc$16053$new_n2003 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[23] decoded_imm[23] pcpi_rs1[24] decoded_imm[24] $abc$16053$new_n2005 $abc$16053$new_n2004 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[21] decoded_imm[21] pcpi_rs1[22] decoded_imm[22] $abc$16053$new_n2006 $abc$16053$new_n2005 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[19] decoded_imm[19] pcpi_rs1[20] decoded_imm[20] $abc$16053$new_n2007 $abc$16053$new_n2006 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[17] decoded_imm[17] pcpi_rs1[18] decoded_imm[18] $abc$16053$new_n2008 $abc$16053$new_n2007 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[15] decoded_imm[15] pcpi_rs1[16] decoded_imm[16] $abc$16053$new_n2009 $abc$16053$new_n2008 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[13] decoded_imm[13] pcpi_rs1[14] decoded_imm[14] $abc$16053$new_n2010 $abc$16053$new_n2009 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[11] decoded_imm[11] pcpi_rs1[12] decoded_imm[12] $abc$16053$new_n2011 $abc$16053$new_n2010 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[9] decoded_imm[9] pcpi_rs1[10] decoded_imm[10] $abc$16053$new_n2012 $abc$16053$new_n2011 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[7] decoded_imm[7] pcpi_rs1[8] decoded_imm[8] $abc$16053$new_n2013 $abc$16053$new_n2012 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[5] decoded_imm[5] pcpi_rs1[6] decoded_imm[6] $abc$16053$new_n2014 $abc$16053$new_n2013 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[3] decoded_imm[3] pcpi_rs1[4] decoded_imm[4] $abc$16053$new_n2015 $abc$16053$new_n2014 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pcpi_rs1[2] decoded_imm[2] $abc$16053$new_n2016 $abc$16053$new_n2015 -000 1 -001 1 -011 1 -101 1 -.names pcpi_rs1[0] decoded_imm[0] pcpi_rs1[1] decoded_imm[1] $abc$16053$new_n2016 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names $abc$16053$new_n2023 $abc$16053$new_n2029 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[29] $abc$16053$new_n2017 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2018 -10 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2020 $abc$16053$new_n2019 -00 1 -.names $abc$16053$new_n1611 cpu_state[1] cpu_state[3] cpu_state[0] cpu_state[2] $abc$16053$new_n2020 -11000 1 -.names cpu_state[0] $abc$16053$new_n1611 cpu_state[3] cpu_state[1] cpu_state[2] $abc$16053$new_n2021 -11000 1 -.names $abc$16053$new_n1611 cpu_state[2] cpu_state[3] cpu_state[1] cpu_state[0] $abc$16053$new_n2022 -11000 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2024 $abc$16053$new_n2028 pcpi_rs1[25] $abc$16053$new_n2025 $abc$16053$new_n2023 -10000 1 -10001 1 -10010 1 -10011 1 -10111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[28] pcpi_rs1[30] $abc$16053$new_n2024 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$16053$new_n2026 instr_srl instr_srli $abc$16053$new_n2025 -100 1 -.names instr_sra instr_srai $abc$16053$new_n2026 -00 1 -.names reg_sh[3] reg_sh[2] reg_sh[4] $abc$16053$new_n2027 -000 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2026 pcpi_rs1[31] $abc$16053$new_n2028 -000 1 -010 1 -011 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[29] $abc$16053$new_n2029 -1001 1 -1011 1 -1110 1 -1111 1 -.names is_lui_auipc_jal $abc$16053$new_n2031 $abc$16053$new_n2030 -00 1 -.names decoded_rs1[4] decoded_rs1[3] decoded_rs1[2] decoded_rs1[1] decoded_rs1[0] $abc$16053$new_n2031 -00000 1 -.names is_lui_auipc_jal instr_lui $abc$16053$new_n2032 -10 1 -.names resetn $abc$16053$new_n2036 $abc$16053$new_n2034 $abc$16053$new_n2035 $abc$16053$new_n2021 $abc$16053$new_n2033 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n2035 $abc$16053$new_n2020 mem_do_wdata mem_do_rdata $abc$16053$new_n2021 $abc$16053$new_n2034 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names mem_do_prefetch $abc$16053$new_n1549 $abc$16053$new_n2035 -11 1 -.names $abc$16053$new_n2038 $abc$16053$new_n2018 $abc$16053$new_n2039 cpu_state[2] $abc$16053$new_n1622 $abc$16053$new_n2036 -00000 1 -00001 1 -00100 1 -00101 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2027 reg_sh[0] reg_sh[1] $abc$16053$new_n2038 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2025 instr_sll instr_slli $abc$16053$new_n2039 -100 1 -.names $abc$16053$new_n2033 $abc$16053$new_n3156 pcpi_rs1[28] $abc$16053$new_n2041 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14925 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11110 1 -.names pcpi_rs1[28] decoded_imm[28] pcpi_rs1[27] decoded_imm[27] $abc$16053$new_n2003 $abc$16053$new_n2041 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2044 reg_pc[28] $abc$16053$new_n2032 $abc$16053$new_n2043 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[28] $abc$16053$new_n2044 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 pcpi_rs1[27] $abc$16053$new_n2049 $abc$16053$new_n2048 $abc$16053$auto$rtlil.cc:2693:MuxGate$14927 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names pcpi_rs1[27] decoded_imm[27] $abc$16053$new_n2003 $abc$16053$new_n2019 $abc$16053$new_n2048 -0000 1 -0110 1 -1010 1 -1100 1 -.names $abc$16053$new_n2050 $abc$16053$new_n2052 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[27] $abc$16053$new_n2049 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names $abc$16053$new_n2051 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[23] pcpi_rs1[31] $abc$16053$new_n2050 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[26] pcpi_rs1[28] $abc$16053$new_n2051 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[27] $abc$16053$new_n2052 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2055 pcpi_rs1[26] $abc$16053$new_n2054 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14929 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names pcpi_rs1[26] decoded_imm[26] pcpi_rs1[25] decoded_imm[25] $abc$16053$new_n2004 $abc$16053$new_n2054 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2056 $abc$16053$new_n2058 $abc$16053$new_n2055 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2057 pcpi_rs1[22] pcpi_rs1[30] $abc$16053$new_n2056 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2025 pcpi_rs1[25] pcpi_rs1[27] $abc$16053$new_n2057 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2059 $abc$16053$new_n2032 reg_pc[26] $abc$16053$new_n2058 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[26] $abc$16053$new_n2059 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 pcpi_rs1[25] $abc$16053$new_n2061 $abc$16053$new_n2062 $abc$16053$auto$rtlil.cc:2693:MuxGate$14931 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names pcpi_rs1[25] decoded_imm[25] $abc$16053$new_n2004 $abc$16053$new_n2019 $abc$16053$new_n2061 -0010 1 -0100 1 -1000 1 -1110 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2063 $abc$16053$new_n2065 $abc$16053$new_n2062 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2064 pcpi_rs1[24] pcpi_rs1[26] $abc$16053$new_n2063 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[21] pcpi_rs1[29] $abc$16053$new_n2064 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2066 $abc$16053$new_n2032 reg_pc[25] $abc$16053$new_n2065 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[25] $abc$16053$new_n2066 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2069 pcpi_rs1[24] $abc$16053$new_n2068 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14933 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names pcpi_rs1[24] decoded_imm[24] pcpi_rs1[23] decoded_imm[23] $abc$16053$new_n2005 $abc$16053$new_n2068 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2070 $abc$16053$new_n2072 $abc$16053$new_n2069 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2071 pcpi_rs1[23] pcpi_rs1[25] $abc$16053$new_n2070 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[20] pcpi_rs1[28] $abc$16053$new_n2071 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2073 $abc$16053$new_n2032 reg_pc[24] $abc$16053$new_n2072 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[24] $abc$16053$new_n2073 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 pcpi_rs1[23] $abc$16053$new_n2075 $abc$16053$new_n2076 $abc$16053$auto$rtlil.cc:2693:MuxGate$14935 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names pcpi_rs1[23] decoded_imm[23] $abc$16053$new_n2005 $abc$16053$new_n2019 $abc$16053$new_n2075 -0010 1 -0100 1 -1000 1 -1110 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2077 $abc$16053$new_n2079 $abc$16053$new_n2076 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2078 pcpi_rs1[22] pcpi_rs1[24] $abc$16053$new_n2077 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[19] pcpi_rs1[27] $abc$16053$new_n2078 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2080 $abc$16053$new_n2032 reg_pc[23] $abc$16053$new_n2079 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[23] $abc$16053$new_n2080 -1001 1 -1011 1 -1110 1 -1111 1 -.names pcpi_rs1[21] decoded_imm[21] $abc$16053$new_n2006 $abc$16053$new_n2084 -000 1 -001 1 -011 1 -101 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2086 $abc$16053$new_n2032 reg_pc[22] $abc$16053$new_n2085 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[22] $abc$16053$new_n2086 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2090 pcpi_rs1[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14939 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n2091 pcpi_rs1[21] decoded_imm[21] $abc$16053$new_n2006 $abc$16053$new_n2019 $abc$16053$new_n2090 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2092 $abc$16053$new_n2094 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[21] $abc$16053$new_n2091 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names $abc$16053$new_n2093 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[17] pcpi_rs1[25] $abc$16053$new_n2092 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[20] pcpi_rs1[22] $abc$16053$new_n2093 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[21] $abc$16053$new_n2094 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2097 pcpi_rs1[20] $abc$16053$new_n2096 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14941 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names pcpi_rs1[20] decoded_imm[20] pcpi_rs1[19] decoded_imm[19] $abc$16053$new_n2007 $abc$16053$new_n2096 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2098 $abc$16053$new_n2100 $abc$16053$new_n2097 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2099 pcpi_rs1[19] pcpi_rs1[21] $abc$16053$new_n2098 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[16] pcpi_rs1[24] $abc$16053$new_n2099 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2101 $abc$16053$new_n2032 reg_pc[20] $abc$16053$new_n2100 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[20] $abc$16053$new_n2101 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 pcpi_rs1[19] $abc$16053$new_n2106 $abc$16053$new_n2104 $abc$16053$new_n2103 $abc$16053$auto$rtlil.cc:2693:MuxGate$14943 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs1[19] decoded_imm[19] $abc$16053$new_n2007 $abc$16053$new_n2019 $abc$16053$new_n2103 -0000 1 -0110 1 -1010 1 -1100 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2105 reg_pc[19] $abc$16053$new_n2032 $abc$16053$new_n2104 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[19] $abc$16053$new_n2105 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2107 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[18] pcpi_rs1[20] $abc$16053$new_n2106 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[15] pcpi_rs1[23] $abc$16053$new_n2107 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2110 pcpi_rs1[18] $abc$16053$new_n2109 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14945 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names pcpi_rs1[18] decoded_imm[18] pcpi_rs1[17] decoded_imm[17] $abc$16053$new_n2008 $abc$16053$new_n2109 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2111 $abc$16053$new_n2113 $abc$16053$new_n2110 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2112 pcpi_rs1[17] pcpi_rs1[19] $abc$16053$new_n2111 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[14] pcpi_rs1[22] $abc$16053$new_n2112 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2114 $abc$16053$new_n2032 reg_pc[18] $abc$16053$new_n2113 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[18] $abc$16053$new_n2114 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 pcpi_rs1[17] $abc$16053$new_n2116 $abc$16053$new_n2117 $abc$16053$auto$rtlil.cc:2693:MuxGate$14947 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names pcpi_rs1[17] decoded_imm[17] $abc$16053$new_n2008 $abc$16053$new_n2019 $abc$16053$new_n2116 -0010 1 -0100 1 -1000 1 -1110 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2118 $abc$16053$new_n2120 $abc$16053$new_n2117 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2119 pcpi_rs1[16] pcpi_rs1[18] $abc$16053$new_n2118 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[21] $abc$16053$new_n2119 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2121 $abc$16053$new_n2032 reg_pc[17] $abc$16053$new_n2120 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[17] $abc$16053$new_n2121 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2124 pcpi_rs1[16] $abc$16053$new_n2123 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14949 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names pcpi_rs1[16] decoded_imm[16] pcpi_rs1[15] decoded_imm[15] $abc$16053$new_n2009 $abc$16053$new_n2123 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2125 $abc$16053$new_n2128 $abc$16053$new_n2127 $abc$16053$new_n2124 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2126 $abc$16053$new_n2032 reg_pc[16] $abc$16053$new_n2125 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[16] $abc$16053$new_n2126 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[15] pcpi_rs1[17] $abc$16053$new_n2127 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[12] pcpi_rs1[20] $abc$16053$new_n2128 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$16053$new_n2033 pcpi_rs1[15] $abc$16053$new_n2130 $abc$16053$new_n2131 $abc$16053$auto$rtlil.cc:2693:MuxGate$14951 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names pcpi_rs1[15] decoded_imm[15] $abc$16053$new_n2009 $abc$16053$new_n2019 $abc$16053$new_n2130 -0010 1 -0100 1 -1000 1 -1110 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2132 $abc$16053$new_n2134 $abc$16053$new_n2131 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2133 pcpi_rs1[14] pcpi_rs1[16] $abc$16053$new_n2132 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[11] pcpi_rs1[19] $abc$16053$new_n2133 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2135 $abc$16053$new_n2032 reg_pc[15] $abc$16053$new_n2134 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[15] $abc$16053$new_n2135 -1001 1 -1011 1 -1110 1 -1111 1 -.names pcpi_rs1[13] decoded_imm[13] $abc$16053$new_n2010 $abc$16053$new_n2139 -000 1 -001 1 -011 1 -101 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2141 $abc$16053$new_n2032 reg_pc[14] $abc$16053$new_n2140 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[14] $abc$16053$new_n2141 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 pcpi_rs1[13] $abc$16053$new_n2146 $abc$16053$new_n2145 $abc$16053$auto$rtlil.cc:2693:MuxGate$14955 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names pcpi_rs1[13] decoded_imm[13] $abc$16053$new_n2010 $abc$16053$new_n2019 $abc$16053$new_n2145 -0000 1 -0110 1 -1010 1 -1100 1 -.names $abc$16053$new_n2147 $abc$16053$new_n2149 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[13] $abc$16053$new_n2146 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names $abc$16053$new_n2148 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[9] pcpi_rs1[17] $abc$16053$new_n2147 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[12] pcpi_rs1[14] $abc$16053$new_n2148 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[13] $abc$16053$new_n2149 -1001 1 -1011 1 -1110 1 -1111 1 -.names pcpi_rs1[11] decoded_imm[11] $abc$16053$new_n2011 $abc$16053$new_n2153 -000 1 -001 1 -011 1 -101 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2155 $abc$16053$new_n2032 reg_pc[12] $abc$16053$new_n2154 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[12] $abc$16053$new_n2155 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 pcpi_rs1[11] $abc$16053$new_n2162 $abc$16053$new_n2160 $abc$16053$new_n2159 $abc$16053$auto$rtlil.cc:2693:MuxGate$14959 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs1[11] decoded_imm[11] $abc$16053$new_n2011 $abc$16053$new_n2019 $abc$16053$new_n2159 -0000 1 -0110 1 -1010 1 -1100 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2161 reg_pc[11] $abc$16053$new_n2032 $abc$16053$new_n2160 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[11] $abc$16053$new_n2161 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2163 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[7] pcpi_rs1[15] $abc$16053$new_n2162 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[10] pcpi_rs1[12] $abc$16053$new_n2163 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2166 pcpi_rs1[10] $abc$16053$new_n2165 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14961 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names pcpi_rs1[10] decoded_imm[10] pcpi_rs1[9] decoded_imm[9] $abc$16053$new_n2012 $abc$16053$new_n2165 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2167 $abc$16053$new_n2169 $abc$16053$new_n2166 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2168 pcpi_rs1[9] pcpi_rs1[11] $abc$16053$new_n2167 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[6] pcpi_rs1[14] $abc$16053$new_n2168 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2170 $abc$16053$new_n2032 reg_pc[10] $abc$16053$new_n2169 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[10] $abc$16053$new_n2170 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 pcpi_rs1[9] $abc$16053$new_n2173 $abc$16053$new_n2172 $abc$16053$auto$rtlil.cc:2693:MuxGate$14963 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names pcpi_rs1[9] decoded_imm[9] $abc$16053$new_n2012 $abc$16053$new_n2019 $abc$16053$new_n2172 -0010 1 -0100 1 -1000 1 -1110 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2174 $abc$16053$new_n2176 $abc$16053$new_n2173 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2175 pcpi_rs1[8] pcpi_rs1[10] $abc$16053$new_n2174 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[5] pcpi_rs1[13] $abc$16053$new_n2175 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2177 $abc$16053$new_n2032 reg_pc[9] $abc$16053$new_n2176 -1000 1 -1001 1 -1010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[9] $abc$16053$new_n2177 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2179 pcpi_rs1[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14965 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n2181 $abc$16053$new_n2183 $abc$16053$new_n2180 $abc$16053$new_n2019 $abc$16053$new_n2179 -0000 1 -0001 1 -0011 1 -.names pcpi_rs1[8] decoded_imm[8] pcpi_rs1[7] decoded_imm[7] $abc$16053$new_n2013 $abc$16053$new_n2180 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2182 reg_pc[8] $abc$16053$new_n2032 $abc$16053$new_n2181 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[8] $abc$16053$new_n2182 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2184 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[4] pcpi_rs1[12] $abc$16053$new_n2183 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[7] pcpi_rs1[9] $abc$16053$new_n2184 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2189 pcpi_rs1[6] pcpi_rs1[8] $abc$16053$new_n2188 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$16053$new_n2025 pcpi_rs1[3] pcpi_rs1[11] $abc$16053$new_n2189 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2191 $abc$16053$new_n2032 reg_pc[7] $abc$16053$new_n2190 -000 1 -001 1 -010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[7] $abc$16053$new_n2191 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2193 pcpi_rs1[6] $abc$16053$new_n2197 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14969 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11110 1 -.names $abc$16053$new_n2194 $abc$16053$new_n2196 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[6] $abc$16053$new_n2193 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names $abc$16053$new_n2195 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[2] pcpi_rs1[10] $abc$16053$new_n2194 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[5] pcpi_rs1[7] $abc$16053$new_n2195 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[6] $abc$16053$new_n2196 -1001 1 -1011 1 -1110 1 -1111 1 -.names pcpi_rs1[6] decoded_imm[6] pcpi_rs1[5] decoded_imm[5] $abc$16053$new_n2014 $abc$16053$new_n2197 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2199 pcpi_rs1[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14971 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n2200 pcpi_rs1[5] decoded_imm[5] $abc$16053$new_n2014 $abc$16053$new_n2019 $abc$16053$new_n2199 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2201 $abc$16053$new_n2203 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[5] $abc$16053$new_n2200 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names $abc$16053$new_n2202 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[4] pcpi_rs1[6] $abc$16053$new_n2201 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[1] pcpi_rs1[9] $abc$16053$new_n2202 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[5] $abc$16053$new_n2203 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2205 pcpi_rs1[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14973 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2206 $abc$16053$new_n2210 $abc$16053$new_n2208 $abc$16053$new_n2205 -00010 1 -00011 1 -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2207 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[0] pcpi_rs1[8] $abc$16053$new_n2206 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[3] pcpi_rs1[5] $abc$16053$new_n2207 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$16053$new_n2209 $abc$16053$new_n2032 reg_pc[4] $abc$16053$new_n2208 -000 1 -001 1 -010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[4] $abc$16053$new_n2209 -1001 1 -1011 1 -1110 1 -1111 1 -.names pcpi_rs1[4] decoded_imm[4] pcpi_rs1[3] decoded_imm[3] $abc$16053$new_n2015 $abc$16053$new_n2210 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2213 reg_pc[3] $abc$16053$new_n2032 $abc$16053$new_n2212 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[3] $abc$16053$new_n2213 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2218 pcpi_rs1[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14977 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2222 $abc$16053$new_n2221 $abc$16053$new_n2219 $abc$16053$new_n2218 -00100 1 -00101 1 -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2220 $abc$16053$new_n2032 reg_pc[2] $abc$16053$new_n2219 -000 1 -001 1 -010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[2] $abc$16053$new_n2220 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[1] pcpi_rs1[3] pcpi_rs1[6] $abc$16053$new_n2221 -00001 1 -00011 1 -00101 1 -00111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs1[2] decoded_imm[2] $abc$16053$new_n2016 $abc$16053$new_n2222 -000 1 -011 1 -101 1 -110 1 -.names $abc$16053$new_n2226 $abc$16053$new_n2227 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[1] $abc$16053$new_n2225 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -.names pcpi_rs1[1] decoded_imm[1] $abc$16053$new_n2019 pcpi_rs1[0] decoded_imm[0] $abc$16053$new_n2226 -00011 1 -01000 1 -01001 1 -01010 1 -10000 1 -10001 1 -10010 1 -11011 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[1] $abc$16053$new_n2227 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2230 $abc$16053$new_n2033 pcpi_rs1[0] decoded_imm[0] $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14981 -00100 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n2232 $abc$16053$new_n2231 reg_pc[0] $abc$16053$new_n2032 $abc$16053$new_n2230 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$16053$new_n2018 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[0] $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] $abc$16053$new_n2231 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[1] pcpi_rs1[4] $abc$16053$new_n2232 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[30] reg_out[30] reg_next_pc[30] mem_la_addr[30] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[30] mem_addr[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14983 -001 1 -011 1 -110 1 -111 1 -.names trap mem_la_read mem_la_write $abc$16053$new_n2235 -001 1 -010 1 -011 1 -.names resetn $abc$16053$new_n1469 mem_la_read -11 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[29] reg_out[29] reg_next_pc[29] mem_la_addr[29] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[29] mem_addr[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14985 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[28] reg_out[28] reg_next_pc[28] mem_la_addr[28] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[28] mem_addr[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14987 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[27] reg_out[27] reg_next_pc[27] mem_la_addr[27] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[27] mem_addr[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14989 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[26] reg_out[26] reg_next_pc[26] mem_la_addr[26] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[26] mem_addr[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14991 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[25] reg_out[25] reg_next_pc[25] mem_la_addr[25] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[25] mem_addr[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14993 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[24] reg_out[24] reg_next_pc[24] mem_la_addr[24] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[24] mem_addr[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14995 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[23] reg_out[23] reg_next_pc[23] mem_la_addr[23] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[23] mem_addr[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14997 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[22] reg_out[22] reg_next_pc[22] mem_la_addr[22] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[22] mem_addr[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14999 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[21] reg_out[21] reg_next_pc[21] mem_la_addr[21] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[21] mem_addr[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$15001 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[20] reg_out[20] reg_next_pc[20] mem_la_addr[20] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[20] mem_addr[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$15003 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[19] reg_out[19] reg_next_pc[19] mem_la_addr[19] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[19] mem_addr[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$15005 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[18] reg_out[18] reg_next_pc[18] mem_la_addr[18] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[18] mem_addr[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$15007 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[17] reg_out[17] reg_next_pc[17] mem_la_addr[17] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[17] mem_addr[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$15009 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[16] reg_out[16] reg_next_pc[16] mem_la_addr[16] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[16] mem_addr[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$15011 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[15] reg_out[15] reg_next_pc[15] mem_la_addr[15] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[15] mem_addr[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$15013 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[14] reg_out[14] reg_next_pc[14] mem_la_addr[14] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[14] mem_addr[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$15015 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[13] reg_out[13] reg_next_pc[13] mem_la_addr[13] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[13] mem_addr[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$15017 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[12] reg_out[12] reg_next_pc[12] mem_la_addr[12] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[12] mem_addr[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$15019 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[11] reg_out[11] reg_next_pc[11] mem_la_addr[11] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[11] mem_addr[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$15021 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[10] reg_out[10] reg_next_pc[10] mem_la_addr[10] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[10] mem_addr[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$15023 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[9] reg_out[9] reg_next_pc[9] mem_la_addr[9] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[9] mem_addr[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$15025 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[8] reg_out[8] reg_next_pc[8] mem_la_addr[8] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[8] mem_addr[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$15027 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[7] reg_out[7] reg_next_pc[7] mem_la_addr[7] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[7] mem_addr[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$15029 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[6] reg_out[6] reg_next_pc[6] mem_la_addr[6] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[6] mem_addr[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$15031 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[5] reg_out[5] reg_next_pc[5] mem_la_addr[5] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[5] mem_addr[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$15033 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[4] reg_out[4] reg_next_pc[4] mem_la_addr[4] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[4] mem_addr[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15035 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[3] reg_out[3] reg_next_pc[3] mem_la_addr[3] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[3] mem_addr[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$15037 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[2] reg_out[2] reg_next_pc[2] mem_la_addr[2] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[2] mem_addr[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15039 -001 1 -011 1 -110 1 -111 1 -.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[31] mem_la_wdata[7] pcpi_rs2[15] mem_la_wdata[31] -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1410 mem_la_wdata[31] mem_wdata[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15045 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2235 mem_instr mem_do_wdata $abc$16053$new_n1470 $abc$16053$auto$rtlil.cc:2693:MuxGate$15049 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$16053$new_n1548 is_alu_reg_reg $abc$16053$new_n2299 $abc$16053$new_n2297 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15051 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n2298 mem_rdata_latched[2] mem_rdata_latched[3] $abc$16053$new_n2297 -100 1 -.names mem_rdata_latched[0] mem_rdata_latched[1] $abc$16053$new_n2298 -11 1 -.names mem_rdata_latched[5] mem_rdata_latched[6] $abc$16053$new_n2299 -10 1 -.names $abc$16053$new_n1548 is_alu_reg_imm $abc$16053$new_n2301 $abc$16053$new_n2297 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15053 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names mem_rdata_latched[5] mem_rdata_latched[6] $abc$16053$new_n2301 -00 1 -.names $abc$16053$new_n1479 is_sll_srl_sra $abc$16053$new_n2303 is_alu_reg_reg $abc$16053$auto$rtlil.cc:2693:MuxGate$15055 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n2306 $abc$16053$new_n2304 mem_rdata_q[30] mem_rdata_q[14] $abc$16053$new_n2303 -1100 1 -1101 1 -1111 1 -.names $abc$16053$new_n2305 mem_rdata_q[31] mem_rdata_q[25] mem_rdata_q[26] mem_rdata_q[27] $abc$16053$new_n2304 -10000 1 -.names mem_rdata_q[28] mem_rdata_q[29] $abc$16053$new_n2305 -00 1 -.names mem_rdata_q[12] mem_rdata_q[13] $abc$16053$new_n2306 -10 1 -.names $abc$16053$new_n1548 is_sb_sh_sw $abc$16053$new_n2297 $abc$16053$new_n2299 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15057 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$16053$new_n1479 instr_jalr is_jalr_addi_slti_sltiu_xori_ori_andi is_alu_reg_imm $abc$16053$new_n2306 $abc$16053$auto$rtlil.cc:2693:MuxGate$15059 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1479 is_slli_srli_srai $abc$16053$new_n2303 is_alu_reg_imm $abc$16053$auto$rtlil.cc:2693:MuxGate$15061 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1548 is_lb_lh_lw_lbu_lhu $abc$16053$new_n2297 $abc$16053$new_n2301 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15063 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$16053$new_n1479 $abc$16053$new_n2312 decoded_imm[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15065 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1478 $abc$16053$new_n1480 mem_rdata_q[31] decoded_imm_j[31] instr_jal $abc$16053$new_n2312 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n1548 mem_rdata_latched[11] decoded_rd[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15067 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2322 $abc$16053$new_n2315 instr_rdinstrh $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15069 -0010 1 -0110 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2316 mem_rdata_q[21] mem_rdata_q[20] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2315 -11000 1 -.names $abc$16053$new_n2321 $abc$16053$new_n2320 $abc$16053$new_n1479 $abc$16053$new_n2318 $abc$16053$new_n2317 $abc$16053$new_n2316 -11111 1 -.names $abc$16053$new_n2305 mem_rdata_q[30] mem_rdata_q[17] mem_rdata_q[18] mem_rdata_q[19] $abc$16053$new_n2317 -11000 1 -.names mem_rdata_q[31] mem_rdata_q[4] $abc$16053$new_n2319 mem_rdata_q[2] mem_rdata_q[3] $abc$16053$new_n2318 -11100 1 -.names mem_rdata_q[5] mem_rdata_q[6] mem_rdata_q[15] mem_rdata_q[16] $abc$16053$new_n2319 -1100 1 -.names mem_rdata_q[13] mem_rdata_q[12] mem_rdata_q[14] $abc$16053$new_n2320 -100 1 -.names mem_rdata_q[0] mem_rdata_q[1] $abc$16053$new_n2321 -11 1 -.names mem_rdata_q[27] mem_rdata_q[24] mem_rdata_q[25] mem_rdata_q[26] $abc$16053$new_n2322 -1000 1 -.names $abc$16053$new_n2324 $abc$16053$new_n2315 instr_rdinstr $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15071 -0010 1 -0110 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names mem_rdata_q[24] mem_rdata_q[25] mem_rdata_q[26] mem_rdata_q[27] $abc$16053$new_n2324 -0000 1 -.names $abc$16053$new_n2326 instr_rdcycleh $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15073 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$16053$new_n2316 $abc$16053$new_n2322 mem_rdata_q[21] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2326 -11000 1 -.names $abc$16053$new_n2328 instr_rdcycle $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15075 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$16053$new_n2316 $abc$16053$new_n2324 mem_rdata_q[21] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2328 -11000 1 -.names $abc$16053$new_n1479 instr_srai $abc$16053$new_n2331 is_alu_reg_imm $abc$16053$new_n2330 $abc$16053$auto$rtlil.cc:2693:MuxGate$15077 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names mem_rdata_q[30] $abc$16053$new_n1479 $abc$16053$new_n2304 $abc$16053$new_n2330 -111 1 -.names mem_rdata_q[14] $abc$16053$new_n2306 $abc$16053$new_n2331 -11 1 -.names $abc$16053$new_n1479 instr_srli is_alu_reg_imm $abc$16053$new_n2331 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15079 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n2304 mem_rdata_q[30] $abc$16053$new_n2333 -10 1 -.names $abc$16053$new_n1479 instr_slli is_alu_reg_imm $abc$16053$new_n2335 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15081 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n2306 mem_rdata_q[14] $abc$16053$new_n2335 -10 1 -.names $abc$16053$new_n1479 instr_sw is_sb_sh_sw $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15083 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_sh $abc$16053$new_n2335 is_sb_sh_sw $abc$16053$auto$rtlil.cc:2693:MuxGate$15085 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_sb is_sb_sh_sw $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15087 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2339 -000 1 -.names $abc$16053$new_n1479 instr_lhu $abc$16053$new_n2331 is_lb_lh_lw_lbu_lhu $abc$16053$auto$rtlil.cc:2693:MuxGate$15089 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_lbu is_lb_lh_lw_lbu_lhu $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15091 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names mem_rdata_q[14] mem_rdata_q[12] mem_rdata_q[13] $abc$16053$new_n2342 -100 1 -.names $abc$16053$new_n1479 instr_lw is_lb_lh_lw_lbu_lhu $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15093 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_lh $abc$16053$new_n2335 is_lb_lh_lw_lbu_lhu $abc$16053$auto$rtlil.cc:2693:MuxGate$15095 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_lb is_lb_lh_lw_lbu_lhu $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15097 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1548 instr_jalr $abc$16053$new_n2347 $abc$16053$new_n2349 mem_rdata_latched[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$15099 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$16053$new_n2348 mem_rdata_latched[13] mem_rdata_latched[14] $abc$16053$new_n2347 -100 1 -.names mem_rdata_latched[6] mem_rdata_latched[5] mem_rdata_latched[4] $abc$16053$new_n2348 -110 1 -.names mem_rdata_latched[2] $abc$16053$new_n2298 mem_rdata_latched[3] $abc$16053$new_n2349 -110 1 -.names $abc$16053$new_n1548 instr_jal $abc$16053$new_n2348 $abc$16053$new_n2298 $abc$16053$new_n2351 $abc$16053$auto$rtlil.cc:2693:MuxGate$15101 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names mem_rdata_latched[2] mem_rdata_latched[3] $abc$16053$new_n2351 -11 1 -.names $abc$16053$new_n1548 instr_auipc $abc$16053$new_n2301 $abc$16053$new_n2349 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15103 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1548 instr_lui $abc$16053$new_n2299 $abc$16053$new_n2349 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15105 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[31] decoded_imm[31] $abc$16053$new_n2355 $abc$16053$auto$rtlil.cc:2693:MuxGate$15107 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[31] $abc$16053$new_n2355 -0001 1 -0011 1 -1010 1 -1011 1 -.names pcpi_rs1[29] decoded_imm[29] pcpi_rs1[30] decoded_imm[30] $abc$16053$new_n2002 $abc$16053$new_n2358 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$16053$new_n2362 $abc$16053$new_n2361 $abc$16053$new_n2022 $abc$16053$new_n2032 reg_pc[31] $abc$16053$new_n2360 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[31] $abc$16053$new_n2361 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[30] pcpi_rs1[27] $abc$16053$new_n2362 -11001 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n2365 pcpi_rs1[30] $abc$16053$new_n2364 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$15111 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names pcpi_rs1[30] decoded_imm[30] pcpi_rs1[29] decoded_imm[29] $abc$16053$new_n2002 $abc$16053$new_n2364 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2366 $abc$16053$new_n2368 $abc$16053$new_n2369 $abc$16053$new_n2365 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2367 $abc$16053$new_n2032 reg_pc[30] $abc$16053$new_n2366 -000 1 -001 1 -010 1 -.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[30] $abc$16053$new_n2367 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[29] pcpi_rs1[31] $abc$16053$new_n2368 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$16053$new_n2028 $abc$16053$new_n2025 pcpi_rs1[26] $abc$16053$new_n2369 -100 1 -101 1 -110 1 -.names count_instr[63] count_instr[62] $abc$16053$new_n1909 $abc$16053$auto$rtlil.cc:2693:MuxGate$15113 -011 1 -100 1 -101 1 -110 1 -.names $abc$16053$new_n1612 $abc$16053$new_n2372 reg_pc[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15115 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n1704 $abc$16053$new_n2373 reg_next_pc[31] $abc$16053$new_n2372 -000 1 -010 1 -110 1 -111 1 -.names latched_stalu alu_out_q[31] reg_out[31] $abc$16053$new_n2373 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n2378 reg_next_pc[31] $abc$16053$new_n2375 $abc$16053$new_n2377 $abc$16053$auto$rtlil.cc:2693:MuxGate$15117 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names instr_jal $abc$16053$new_n2376 $abc$16053$new_n1750 decoded_imm_j[30] $abc$16053$new_n1751 $abc$16053$new_n2375 -10001 1 -10100 1 -10101 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -.names decoded_imm_j[31] $abc$16053$new_n2372 $abc$16053$new_n2376 -01 1 -10 1 -.names $abc$16053$new_n2372 instr_jal $abc$16053$new_n1690 $abc$16053$new_n1750 decoder_trigger $abc$16053$new_n2377 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2372 decoder_trigger $abc$16053$new_n2378 -10 1 -.names mem_do_prefetch resetn $abc$16053$new_n2380 $abc$16053$new_n1612 instr_jalr $abc$16053$auto$rtlil.cc:2693:MuxGate$15119 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names decoder_trigger instr_jal $abc$16053$new_n2380 -10 1 -.names $abc$16053$new_n2399 $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$new_n2382 mem_do_rinst $abc$16053$auto$rtlil.cc:2693:MuxGate$15121 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n2022 $abc$16053$new_n1621 mem_do_prefetch $abc$16053$new_n2383 $abc$16053$new_n2398 $abc$16053$new_n2382 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1622 $abc$16053$new_n2384 $abc$16053$new_n2380 $abc$16053$new_n2383 -000 1 -010 1 -110 1 -111 1 -.names $abc$16053$new_n2385 mem_do_prefetch is_lb_lh_lw_lbu_lhu $abc$16053$new_n2398 $abc$16053$new_n2384 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n1624 $abc$16053$new_n2394 is_slli_srli_srai $abc$16053$new_n2386 $abc$16053$new_n2385 -1100 1 -.names $abc$16053$new_n2397 $abc$16053$new_n2396 $abc$16053$new_n2387 $0\is_lui_auipc_jal[0:0] $abc$16053$new_n2386 -1110 1 -.names $abc$16053$new_n2394 $abc$16053$new_n2393 $abc$16053$new_n2391 $abc$16053$new_n2389 $abc$16053$new_n2388 $abc$16053$new_n2387 -11111 1 -.names $abc$16053$new_n2025 instr_lb instr_lbu instr_sh instr_sw $abc$16053$new_n2388 -10000 1 -.names $abc$16053$new_n2390 instr_fence instr_xor instr_sub instr_add $abc$16053$new_n2389 -10000 1 -.names instr_xori instr_addi instr_bgeu instr_bltu $abc$16053$new_n2390 -0000 1 -.names $abc$16053$new_n2392 instr_bge instr_blt instr_bne instr_beq $abc$16053$new_n2391 -10000 1 -.names instr_sll instr_jalr instr_sb instr_slli $abc$16053$new_n2392 -0000 1 -.names instr_and instr_or instr_andi instr_ori $abc$16053$new_n2393 -0000 1 -.names instr_rdcycle instr_rdcycleh instr_rdinstr instr_rdinstrh $abc$16053$new_n2394 -0000 1 -.names $abc$16053$new_n1478 instr_jal $0\is_lui_auipc_jal[0:0] -00 1 -01 1 -11 1 -.names instr_sltu instr_slt instr_sltiu instr_slti $abc$16053$new_n2396 -0000 1 -.names instr_lh instr_lw instr_lhu $abc$16053$new_n2397 -000 1 -.names is_sll_srl_sra mem_do_rinst mem_do_prefetch is_sb_sh_sw $abc$16053$new_n2398 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2038 $abc$16053$new_n1621 $abc$16053$new_n2400 $abc$16053$new_n2022 $abc$16053$new_n2399 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$16053$new_n1622 $abc$16053$new_n1624 $abc$16053$new_n2385 resetn $abc$16053$new_n1612 $abc$16053$new_n2400 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names resetn $abc$16053$new_n1549 $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] -00 1 -01 1 -10 1 -.names mem_do_rdata $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15123 -10 1 -.names mem_do_wdata $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15125 -10 1 -.names $abc$16053$new_n2454 $abc$16053$new_n2452 $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2405 $abc$16053$auto$rtlil.cc:2693:MuxGate$15127 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2450 instr_bgeu $abc$16053$new_n2406 is_sltiu_bltu_sltu is_slti_blt_slt $abc$16053$new_n2405 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instr_bge instr_bne $abc$16053$new_n2448 $abc$16053$new_n2407 $abc$16053$new_n2406 -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$16053$new_n2408 pcpi_rs1[31] pcpi_rs2[31] $abc$16053$new_n2407 -000 1 -001 1 -010 1 -011 1 -110 1 -.names $abc$16053$new_n2444 $abc$16053$new_n2929 $abc$16053$new_n2440 $abc$16053$new_n2408 -000 1 -001 1 -010 1 -.names pcpi_rs1[14] pcpi_rs2[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2416 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$16053$new_n2424 $abc$16053$new_n2416 $abc$16053$new_n2423 $abc$16053$new_n2422 $abc$16053$new_n2419 $abc$16053$new_n2418 -11111 1 -.names $abc$16053$new_n2420 pcpi_rs1[2] mem_la_wdata[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2419 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$16053$new_n2421 pcpi_rs1[4] mem_la_wdata[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2420 -10000 1 -10011 1 -11100 1 -11111 1 -.names pcpi_rs1[6] mem_la_wdata[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2421 -0000 1 -0011 1 -1100 1 -1111 1 -.names pcpi_rs1[12] pcpi_rs2[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2422 -0000 1 -0011 1 -1100 1 -1111 1 -.names pcpi_rs1[10] pcpi_rs2[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2423 -0000 1 -0011 1 -1100 1 -1111 1 -.names pcpi_rs1[8] pcpi_rs2[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2424 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$16053$new_n2438 $abc$16053$new_n2436 $abc$16053$new_n2435 -11 1 -.names $abc$16053$new_n2437 pcpi_rs1[22] pcpi_rs2[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2436 -10000 1 -10011 1 -11100 1 -11111 1 -.names pcpi_rs1[20] pcpi_rs2[20] pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2437 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$16053$new_n2439 pcpi_rs1[16] pcpi_rs2[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2438 -10000 1 -10011 1 -11100 1 -11111 1 -.names pcpi_rs1[18] pcpi_rs2[18] pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2439 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$16053$new_n2441 pcpi_rs1[31] pcpi_rs2[31] pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2440 -10000 1 -10011 1 -11100 1 -11111 1 -.names pcpi_rs1[28] pcpi_rs2[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2441 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$16053$new_n2443 pcpi_rs1[24] pcpi_rs2[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2442 -10000 1 -10011 1 -11100 1 -11111 1 -.names pcpi_rs1[26] pcpi_rs2[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2443 -0000 1 -0011 1 -1100 1 -1111 1 -.names pcpi_rs1[31] pcpi_rs2[31] pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2445 $abc$16053$new_n2444 -00001 1 -00010 1 -00011 1 -00111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names pcpi_rs2[28] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2445 -0001 1 -0101 1 -1000 1 -1001 1 -1011 1 -1101 1 -.names $abc$16053$new_n2440 $abc$16053$new_n2449 $abc$16053$new_n2435 $abc$16053$new_n2418 $abc$16053$new_n2448 -1111 1 -.names $abc$16053$new_n2442 pcpi_rs1[0] mem_la_wdata[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2449 -10000 1 -10011 1 -11100 1 -11111 1 -.names is_sltiu_bltu_sltu is_slti_blt_slt $abc$16053$new_n2451 $abc$16053$new_n2407 instr_bgeu $abc$16053$new_n2450 -00001 1 -00011 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2408 pcpi_rs2[31] pcpi_rs1[31] $abc$16053$new_n2451 -000 1 -001 1 -010 1 -011 1 -110 1 -.names $abc$16053$new_n1622 latched_store $abc$16053$new_n2453 $abc$16053$new_n2394 $abc$16053$new_n1612 $abc$16053$new_n2452 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2454 $abc$16053$new_n1610 $abc$16053$new_n2453 -10 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2021 $abc$16053$new_n2454 -00 1 -.names $abc$16053$new_n1612 latched_stalu $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$auto$rtlil.cc:2693:MuxGate$15129 -0010 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$16053$new_n1610 $abc$16053$new_n1612 $abc$16053$new_n2458 $abc$16053$new_n2457 latched_branch $abc$16053$auto$rtlil.cc:2693:MuxGate$15131 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2405 $abc$16053$new_n2457 -10 1 -.names $abc$16053$new_n1610 instr_jalr is_beq_bne_blt_bge_bltu_bgeu decoder_trigger instr_jal $abc$16053$new_n2458 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2460 instr_lh latched_is_lh $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$15133 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2021 mem_do_rdata $abc$16053$new_n2035 $abc$16053$new_n2460 -100 1 -.names $abc$16053$new_n2460 instr_lb latched_is_lb $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$15135 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n1479 instr_beq is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15137 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_bne is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2335 $abc$16053$auto$rtlil.cc:2693:MuxGate$15139 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_blt is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15141 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_bge is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2331 $abc$16053$auto$rtlil.cc:2693:MuxGate$15143 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_bltu is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2467 $abc$16053$auto$rtlil.cc:2693:MuxGate$15145 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names mem_rdata_q[14] mem_rdata_q[13] mem_rdata_q[12] $abc$16053$new_n2467 -110 1 -.names $abc$16053$new_n1479 instr_bgeu is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15147 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2469 -111 1 -.names $abc$16053$new_n1479 instr_addi is_alu_reg_imm $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15149 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_slti is_alu_reg_imm $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15151 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_sltiu is_alu_reg_imm $abc$16053$new_n2473 $abc$16053$auto$rtlil.cc:2693:MuxGate$15153 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2473 -110 1 -.names $abc$16053$new_n1479 instr_xori is_alu_reg_imm $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15155 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_ori is_alu_reg_imm $abc$16053$new_n2467 $abc$16053$auto$rtlil.cc:2693:MuxGate$15157 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_andi is_alu_reg_imm $abc$16053$new_n2469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15159 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1479 instr_add is_alu_reg_reg $abc$16053$new_n2339 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15161 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_sub $abc$16053$new_n2330 is_alu_reg_reg $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15163 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_sll is_alu_reg_reg $abc$16053$new_n2335 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15165 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_slt is_alu_reg_reg $abc$16053$new_n2320 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15167 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_sltu is_alu_reg_reg $abc$16053$new_n2473 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15169 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_xor is_alu_reg_reg $abc$16053$new_n2342 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15171 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_srl is_alu_reg_reg $abc$16053$new_n2331 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15173 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_sra $abc$16053$new_n2331 is_alu_reg_reg $abc$16053$new_n2330 $abc$16053$auto$rtlil.cc:2693:MuxGate$15175 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_or is_alu_reg_reg $abc$16053$new_n2467 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15177 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_and is_alu_reg_reg $abc$16053$new_n2469 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15179 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names $abc$16053$new_n1479 instr_fence $abc$16053$new_n2339 $abc$16053$new_n2321 $abc$16053$new_n2488 $abc$16053$auto$rtlil.cc:2693:MuxGate$15181 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11111 1 -.names mem_rdata_q[2] mem_rdata_q[3] mem_rdata_q[4] mem_rdata_q[5] mem_rdata_q[6] $abc$16053$new_n2488 -11000 1 -.names $abc$16053$new_n1548 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2348 $abc$16053$new_n2297 $abc$16053$auto$rtlil.cc:2693:MuxGate$15183 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15185 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2235 mem_valid $abc$16053$new_n2492 $abc$16053$new_n1468 $abc$16053$auto$rtlil.cc:2693:MuxGate$15189 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n1473 $abc$16053$new_n1474 resetn mem_ready $abc$16053$new_n2492 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$16053$new_n1467 $abc$16053$new_n1475 mem_state[1] mem_state[0] mem_do_wdata $abc$16053$auto$rtlil.cc:2693:MuxGate$15193 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2495 $abc$16053$new_n2498 mem_wordsize[1] $abc$16053$new_n2397 $abc$16053$new_n2021 $abc$16053$auto$rtlil.cc:2693:MuxGate$15197 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2501 $abc$16053$new_n2034 $abc$16053$new_n2496 $abc$16053$new_n2495 -111 1 -.names $abc$16053$new_n2498 instr_sb $abc$16053$new_n2500 $abc$16053$new_n2460 $abc$16053$new_n2496 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names mem_do_wdata $abc$16053$new_n2035 $abc$16053$new_n2497 -00 1 -.names $abc$16053$new_n2499 instr_sh $abc$16053$new_n2498 -10 1 -.names $abc$16053$new_n2020 instr_sw $abc$16053$new_n2499 -10 1 -.names $abc$16053$new_n2397 instr_lb instr_lbu $abc$16053$new_n2500 -100 1 -.names resetn $abc$16053$new_n1612 $abc$16053$new_n2019 $abc$16053$new_n2035 $abc$16053$new_n2501 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n1609 latched_rd[4] $abc$16053$new_n1612 decoded_rd[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15201 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[31] reg_out[31] reg_next_pc[31] mem_la_addr[31] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2235 mem_la_addr[31] mem_addr[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15203 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2495 $abc$16053$new_n2506 mem_wordsize[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$15207 -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n2499 instr_sh $abc$16053$new_n2021 instr_lw $abc$16053$new_n2397 $abc$16053$new_n2506 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -.names $abc$16053$new_n2235 mem_wstrb[2] mem_la_wstrb[2] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14331 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names mem_wordsize[1] mem_wordsize[0] pcpi_rs1[1] pcpi_rs1[0] mem_la_wstrb[2] -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -0111 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2235 mem_wstrb[1] mem_la_wstrb[1] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14333 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$16053$new_n2512 pcpi_rs1[0] pcpi_rs1[1] mem_la_wstrb[1] -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$16053$new_n2513 $abc$16053$new_n1442 $abc$16053$new_n2512 -00 1 -.names mem_wordsize[0] pcpi_rs1[1] mem_wordsize[1] $abc$16053$new_n2513 -110 1 -.names $abc$16053$new_n2235 mem_wstrb[0] mem_la_wstrb[0] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14335 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$16053$new_n2512 pcpi_rs1[0] pcpi_rs1[1] mem_la_wstrb[0] -000 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$16053$new_n2235 mem_wstrb[3] mem_la_wstrb[3] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15043 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names mem_wordsize[1] mem_wordsize[0] pcpi_rs1[1] pcpi_rs1[0] mem_la_wstrb[3] -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -0111 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instr_slt instr_slti instr_blt $0\is_slti_blt_slt[0:0] -001 1 -010 1 -011 1 -100 1 -101 1 -110 1 -111 1 -.names instr_sltu instr_sltiu instr_bltu $0\is_sltiu_bltu_sltu[0:0] -001 1 -010 1 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$16053$new_n2396 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$reduce_or$./benchmark/picorv32.v:863$175_Y -00 1 -01 1 -11 1 -.names resetn $abc$16053$new_n2019 $abc$16053$new_n2035 $abc$16053$auto$opt_dff.cc:253:combine_resets$4218 -100 1 -.names cpu_state[7] $abc$16053$new_n1613 cpu_state[6] cpu_state[4] cpu_state[5] $abc$16053$procmux$1608_CMP -11000 1 -.names resetn $abc$16053$new_n1479 $abc$16053$auto$opt_dff.cc:253:combine_resets$4160 -00 1 -01 1 -11 1 -.names resetn $abc$16053$new_n1612 $abc$16053$new_n2527 latched_store latched_branch $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] -11001 1 -11010 1 -11011 1 -.names latched_rd[4] latched_rd[0] latched_rd[1] latched_rd[2] latched_rd[3] $abc$16053$new_n2527 -00000 1 -.names mem_do_prefetch $abc$16053$new_n1549 $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y -00 1 -.names resetn mem_do_rinst reg_pc[1] reg_pc[0] $abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2022 reg_sh[0] $abc$16053$new_n2027 $abc$16053$new_n2531 $0\reg_sh[4:0][0] -0000 1 -0010 1 -0100 1 -0110 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$16053$new_n2532 decoded_rs2[0] $abc$16053$new_n1686 $abc$16053$new_n2531 -000 1 -010 1 -100 1 -101 1 -.names is_slli_srli_srai $abc$16053$new_n1621 $abc$16053$new_n2532 -10 1 -.names $abc$16053$new_n2022 reg_sh[1] $abc$16053$new_n2027 reg_sh[0] $abc$16053$new_n2534 $0\reg_sh[4:0][1] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2532 decoded_rs2[1] $abc$16053$new_n1684 $abc$16053$new_n2534 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2536 $abc$16053$new_n2038 reg_sh[2] $abc$16053$new_n2027 $0\reg_sh[4:0][2] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[2] $abc$16053$new_n1682 $abc$16053$new_n2536 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$16053$new_n2538 reg_sh[3] reg_sh[2] $abc$16053$new_n2038 reg_sh[4] $0\reg_sh[4:0][3] -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[3] $abc$16053$new_n1680 $abc$16053$new_n2538 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$16053$new_n2540 reg_sh[4] $abc$16053$new_n2038 reg_sh[2] reg_sh[3] $0\reg_sh[4:0][4] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[4] $abc$16053$new_n1678 $abc$16053$new_n2540 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2542 $abc$16053$new_n2546 pcpi_rs1[0] $0\reg_out[31:0][0] -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2543 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[16] mem_rdata[0] $abc$16053$new_n2542 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2544 mem_rdata[0] mem_la_wstrb[0] mem_rdata[24] $abc$16053$new_n2545 $abc$16053$new_n2543 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names pcpi_rs1[1] mem_rdata[16] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[8] $abc$16053$new_n2544 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names pcpi_rs1[0] pcpi_rs1[1] $abc$16053$new_n2545 -11 1 -.names $abc$16053$new_n1610 reg_pc[0] decoded_imm[0] $abc$16053$new_n2547 $abc$16053$new_n2546 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names instr_rdinstrh instr_rdinstr count_instr[32] $abc$16053$new_n2548 count_instr[0] $abc$16053$new_n2547 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_rdcycleh count_cycle[32] count_cycle[0] $abc$16053$new_n2548 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1610 reg_pc[1] decoded_imm[1] $abc$16053$new_n2556 $abc$16053$new_n2554 $abc$16053$new_n2553 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instr_rdinstrh instr_rdinstr count_instr[33] $abc$16053$new_n2555 count_instr[1] $abc$16053$new_n2554 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[33] count_cycle[1] $abc$16053$new_n2555 -000 1 -010 1 -100 1 -101 1 -.names reg_pc[0] decoded_imm[0] $abc$16053$new_n2556 -11 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2559 $abc$16053$new_n2562 pcpi_rs1[2] $0\reg_out[31:0][2] -00000 1 -00001 1 -00100 1 -00101 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2560 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[18] mem_rdata[2] $abc$16053$new_n2559 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2561 mem_rdata[2] mem_la_wstrb[0] mem_rdata[26] $abc$16053$new_n2545 $abc$16053$new_n2560 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names pcpi_rs1[1] mem_rdata[18] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[10] $abc$16053$new_n2561 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n1610 reg_pc[2] decoded_imm[2] $abc$16053$new_n2565 $abc$16053$new_n2563 $abc$16053$new_n2562 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names instr_rdinstrh instr_rdinstr count_instr[34] $abc$16053$new_n2564 count_instr[2] $abc$16053$new_n2563 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[34] count_cycle[2] $abc$16053$new_n2564 -000 1 -010 1 -100 1 -101 1 -.names reg_pc[0] decoded_imm[0] reg_pc[1] decoded_imm[1] $abc$16053$new_n2565 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names $abc$16053$new_n2568 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[19] mem_rdata[3] $abc$16053$new_n2567 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2569 mem_rdata[3] mem_la_wstrb[0] mem_rdata[27] $abc$16053$new_n2545 $abc$16053$new_n2568 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names pcpi_rs1[1] mem_rdata[19] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[11] $abc$16053$new_n2569 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names reg_pc[3] decoded_imm[3] reg_pc[2] decoded_imm[2] $abc$16053$new_n2565 $abc$16053$new_n2571 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2575 $abc$16053$new_n2578 $abc$16053$new_n2512 mem_rdata[4] $0\reg_out[31:0][4] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n2576 $abc$16053$new_n2513 mem_rdata[20] $abc$16053$new_n2575 -000 1 -001 1 -011 1 -.names $abc$16053$new_n2577 mem_rdata[4] mem_la_wstrb[0] mem_rdata[28] $abc$16053$new_n2545 $abc$16053$new_n2576 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names pcpi_rs1[1] mem_rdata[20] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[12] $abc$16053$new_n2577 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n1610 pcpi_rs1[4] $abc$16053$new_n2579 $abc$16053$new_n2581 $abc$16053$new_n2578 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names reg_pc[4] decoded_imm[4] $abc$16053$new_n2580 $abc$16053$new_n2579 -000 1 -011 1 -101 1 -110 1 -.names reg_pc[2] decoded_imm[2] reg_pc[3] decoded_imm[3] $abc$16053$new_n2565 $abc$16053$new_n2580 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[36] $abc$16053$new_n2582 count_instr[4] $abc$16053$new_n2581 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[36] count_cycle[4] $abc$16053$new_n2582 -000 1 -010 1 -100 1 -101 1 -.names reg_pc[5] decoded_imm[5] reg_pc[4] decoded_imm[4] $abc$16053$new_n2580 $abc$16053$new_n2585 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names pcpi_rs1[0] pcpi_rs1[1] mem_rdata[29] mem_rdata[13] $abc$16053$new_n2590 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$16053$new_n1610 reg_pc[6] decoded_imm[6] $abc$16053$new_n2600 $abc$16053$new_n2593 $0\reg_out[31:0][6] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n2594 $abc$16053$new_n2598 $abc$16053$new_n2453 $abc$16053$new_n2022 pcpi_rs1[6] $abc$16053$new_n2593 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$16053$new_n2595 mem_la_wstrb[0] $abc$16053$new_n2596 mem_rdata[6] $abc$16053$new_n2594 -1000 1 -1001 1 -1101 1 -1111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2513 mem_rdata[22] $abc$16053$new_n2595 -100 1 -101 1 -111 1 -.names $abc$16053$new_n2597 $abc$16053$new_n2545 mem_rdata[30] $abc$16053$new_n2596 -100 1 -101 1 -110 1 -.names pcpi_rs1[1] mem_rdata[22] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[14] $abc$16053$new_n2597 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names instr_rdinstrh instr_rdinstr count_instr[38] $abc$16053$new_n2599 count_instr[6] $abc$16053$new_n2598 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_rdcycleh count_cycle[38] count_cycle[6] $abc$16053$new_n2599 -001 1 -011 1 -110 1 -111 1 -.names reg_pc[4] decoded_imm[4] reg_pc[5] decoded_imm[5] $abc$16053$new_n2580 $abc$16053$new_n2600 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2021 $abc$16053$new_n2606 pcpi_rs1[7] $abc$16053$new_n2602 $0\reg_out[31:0][7] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n1610 reg_pc[7] decoded_imm[7] $abc$16053$new_n2603 $abc$16053$new_n2604 $abc$16053$new_n2602 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[6] decoded_imm[6] $abc$16053$new_n2600 $abc$16053$new_n2603 -000 1 -001 1 -011 1 -101 1 -.names instr_rdinstrh instr_rdinstr count_instr[39] $abc$16053$new_n2605 count_instr[7] $abc$16053$new_n2604 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[39] count_cycle[7] $abc$16053$new_n2605 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n1442 $abc$16053$new_n2513 $abc$16053$new_n2607 mem_rdata[23] mem_rdata[7] $abc$16053$new_n2606 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2608 pcpi_rs1[1] pcpi_rs1[0] mem_rdata[15] mem_rdata[31] $abc$16053$new_n2607 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names pcpi_rs1[1] pcpi_rs1[0] mem_rdata[23] mem_rdata[7] $abc$16053$new_n2608 -0000 1 -0010 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2613 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[8] $abc$16053$new_n2611 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2606 latched_is_lb $abc$16053$new_n2612 -100 1 -110 1 -111 1 -.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[24] mem_rdata[8] $abc$16053$new_n2613 -1001 1 -1011 1 -1110 1 -1111 1 -.names latched_is_lb $abc$16053$new_n1442 $abc$16053$new_n2614 -00 1 -.names reg_pc[7] decoded_imm[7] $abc$16053$new_n2603 $abc$16053$new_n2617 -000 1 -001 1 -011 1 -101 1 -.names $abc$16053$new_n2454 $abc$16053$new_n2623 $abc$16053$new_n2619 $abc$16053$new_n2021 pcpi_rs1[9] $0\reg_out[31:0][9] -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$16053$new_n1610 reg_pc[9] decoded_imm[9] $abc$16053$new_n2620 $abc$16053$new_n2621 $abc$16053$new_n2619 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[7] decoded_imm[7] reg_pc[8] decoded_imm[8] $abc$16053$new_n2603 $abc$16053$new_n2620 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[41] $abc$16053$new_n2622 count_instr[9] $abc$16053$new_n2621 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_rdcycleh count_cycle[41] count_cycle[9] $abc$16053$new_n2622 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[25] mem_rdata[9] $abc$16053$new_n2623 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$16053$new_n2626 $abc$16053$new_n1610 $abc$16053$new_n2625 $abc$16053$new_n2453 $abc$16053$new_n2628 $0\reg_out[31:0][10] -00010 1 -00110 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[10] decoded_imm[10] reg_pc[9] decoded_imm[9] $abc$16053$new_n2620 $abc$16053$new_n2625 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2627 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[10] $abc$16053$new_n2626 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[26] mem_rdata[10] $abc$16053$new_n2627 -1001 1 -1011 1 -1110 1 -1111 1 -.names instr_rdinstrh instr_rdinstr count_instr[42] $abc$16053$new_n2629 count_instr[10] $abc$16053$new_n2628 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[42] count_cycle[10] $abc$16053$new_n2629 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2635 $abc$16053$new_n2021 $abc$16053$new_n2631 pcpi_rs1[11] $0\reg_out[31:0][11] -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$16053$new_n1610 reg_pc[11] decoded_imm[11] $abc$16053$new_n2632 $abc$16053$new_n2633 $abc$16053$new_n2631 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[9] decoded_imm[9] reg_pc[10] decoded_imm[10] $abc$16053$new_n2620 $abc$16053$new_n2632 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[43] $abc$16053$new_n2634 count_instr[11] $abc$16053$new_n2633 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_rdcycleh count_cycle[43] count_cycle[11] $abc$16053$new_n2634 -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[27] mem_rdata[11] $abc$16053$new_n2635 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$16053$new_n2638 $abc$16053$new_n1610 $abc$16053$new_n2637 $abc$16053$new_n2453 $abc$16053$new_n2640 $0\reg_out[31:0][12] -00010 1 -00110 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[12] decoded_imm[12] reg_pc[11] decoded_imm[11] $abc$16053$new_n2632 $abc$16053$new_n2637 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2639 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[12] $abc$16053$new_n2638 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[28] mem_rdata[12] $abc$16053$new_n2639 -1001 1 -1011 1 -1110 1 -1111 1 -.names instr_rdinstrh instr_rdinstr count_instr[44] $abc$16053$new_n2641 count_instr[12] $abc$16053$new_n2640 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[44] count_cycle[12] $abc$16053$new_n2641 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2647 $abc$16053$new_n2021 $abc$16053$new_n2643 pcpi_rs1[13] $0\reg_out[31:0][13] -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$16053$new_n1610 reg_pc[13] decoded_imm[13] $abc$16053$new_n2644 $abc$16053$new_n2645 $abc$16053$new_n2643 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[11] decoded_imm[11] reg_pc[12] decoded_imm[12] $abc$16053$new_n2632 $abc$16053$new_n2644 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[45] $abc$16053$new_n2646 count_instr[13] $abc$16053$new_n2645 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[45] count_cycle[13] $abc$16053$new_n2646 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[29] mem_rdata[13] $abc$16053$new_n2647 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$16053$new_n1610 $abc$16053$new_n2650 $abc$16053$new_n2649 $abc$16053$new_n2454 $abc$16053$new_n2652 $0\reg_out[31:0][14] -00010 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[14] decoded_imm[14] reg_pc[13] decoded_imm[13] $abc$16053$new_n2644 $abc$16053$new_n2649 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2651 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[14] $abc$16053$new_n2650 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[30] mem_rdata[14] $abc$16053$new_n2651 -1001 1 -1011 1 -1110 1 -1111 1 -.names instr_rdinstrh instr_rdinstr count_instr[46] $abc$16053$new_n2653 count_instr[14] $abc$16053$new_n2652 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[46] count_cycle[14] $abc$16053$new_n2653 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2659 $abc$16053$new_n2021 $abc$16053$new_n2655 pcpi_rs1[15] $0\reg_out[31:0][15] -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$16053$new_n1610 reg_pc[15] decoded_imm[15] $abc$16053$new_n2656 $abc$16053$new_n2657 $abc$16053$new_n2655 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[13] decoded_imm[13] reg_pc[14] decoded_imm[14] $abc$16053$new_n2644 $abc$16053$new_n2656 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[47] $abc$16053$new_n2658 count_instr[15] $abc$16053$new_n2657 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[47] count_cycle[15] $abc$16053$new_n2658 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2660 latched_is_lb $abc$16053$new_n2659 -100 1 -101 1 -111 1 -.names $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[31] mem_rdata[15] $abc$16053$new_n2660 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$16053$new_n2663 $abc$16053$new_n1610 $abc$16053$new_n2662 $abc$16053$new_n2453 $abc$16053$new_n2667 $0\reg_out[31:0][16] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[16] decoded_imm[16] reg_pc[15] decoded_imm[15] $abc$16053$new_n2656 $abc$16053$new_n2662 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2664 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[16] $abc$16053$new_n2663 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names latched_is_lb $abc$16053$new_n2665 mem_rdata[16] $abc$16053$new_n2666 $abc$16053$new_n2664 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names latched_is_lh $abc$16053$new_n2660 $abc$16053$new_n2665 -11 1 -.names $abc$16053$new_n1425 latched_is_lh $abc$16053$new_n2666 -10 1 -.names instr_rdinstrh $abc$16053$new_n2668 count_instr[48] count_instr[16] instr_rdinstr $abc$16053$new_n2667 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[48] count_cycle[16] $abc$16053$new_n2668 -00000 1 -00010 1 -10000 1 -10001 1 -.names $abc$16053$new_n2454 $abc$16053$new_n2674 $abc$16053$new_n2670 $abc$16053$new_n2021 pcpi_rs1[17] $0\reg_out[31:0][17] -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$16053$new_n1610 reg_pc[17] decoded_imm[17] $abc$16053$new_n2671 $abc$16053$new_n2672 $abc$16053$new_n2670 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[15] decoded_imm[15] reg_pc[16] decoded_imm[16] $abc$16053$new_n2656 $abc$16053$new_n2671 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[49] $abc$16053$new_n2673 count_instr[17] $abc$16053$new_n2672 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[49] count_cycle[17] $abc$16053$new_n2673 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[17] $abc$16053$new_n2674 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2677 $abc$16053$new_n1610 $abc$16053$new_n2676 $abc$16053$new_n2453 $abc$16053$new_n2679 $0\reg_out[31:0][18] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[18] decoded_imm[18] reg_pc[17] decoded_imm[17] $abc$16053$new_n2671 $abc$16053$new_n2676 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2678 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[18] $abc$16053$new_n2677 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names latched_is_lb $abc$16053$new_n2665 mem_rdata[18] $abc$16053$new_n2666 $abc$16053$new_n2678 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names instr_rdinstrh $abc$16053$new_n2680 count_instr[50] count_instr[18] instr_rdinstr $abc$16053$new_n2679 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[50] count_cycle[18] $abc$16053$new_n2680 -00000 1 -00010 1 -10000 1 -10001 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2686 $abc$16053$new_n2021 $abc$16053$new_n2682 pcpi_rs1[19] $0\reg_out[31:0][19] -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$16053$new_n1610 reg_pc[19] decoded_imm[19] $abc$16053$new_n2683 $abc$16053$new_n2684 $abc$16053$new_n2682 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[17] decoded_imm[17] reg_pc[18] decoded_imm[18] $abc$16053$new_n2671 $abc$16053$new_n2683 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[51] $abc$16053$new_n2685 count_instr[19] $abc$16053$new_n2684 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[51] count_cycle[19] $abc$16053$new_n2685 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[19] $abc$16053$new_n2686 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[19] decoded_imm[19] $abc$16053$new_n2683 $abc$16053$new_n2688 -010 1 -100 1 -110 1 -111 1 -.names $abc$16053$new_n2691 $abc$16053$new_n2021 pcpi_rs1[20] $abc$16053$new_n2022 $abc$16053$new_n2690 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[20] $abc$16053$new_n2691 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2699 $abc$16053$new_n2021 $abc$16053$new_n2695 pcpi_rs1[21] $0\reg_out[31:0][21] -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$16053$new_n1610 reg_pc[21] decoded_imm[21] $abc$16053$new_n2696 $abc$16053$new_n2697 $abc$16053$new_n2695 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[19] decoded_imm[19] reg_pc[20] decoded_imm[20] $abc$16053$new_n2683 $abc$16053$new_n2696 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[53] $abc$16053$new_n2698 count_instr[21] $abc$16053$new_n2697 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[53] count_cycle[21] $abc$16053$new_n2698 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[21] $abc$16053$new_n2699 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2702 $abc$16053$new_n1610 $abc$16053$new_n2701 $abc$16053$new_n2453 $abc$16053$new_n2704 $0\reg_out[31:0][22] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[22] decoded_imm[22] reg_pc[21] decoded_imm[21] $abc$16053$new_n2696 $abc$16053$new_n2701 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2703 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[22] $abc$16053$new_n2702 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names latched_is_lb $abc$16053$new_n2665 mem_rdata[22] $abc$16053$new_n2666 $abc$16053$new_n2703 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names instr_rdinstrh $abc$16053$new_n2705 count_instr[54] count_instr[22] instr_rdinstr $abc$16053$new_n2704 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[54] count_cycle[22] $abc$16053$new_n2705 -00000 1 -00010 1 -10000 1 -10001 1 -.names $abc$16053$new_n2454 $abc$16053$new_n2711 $abc$16053$new_n2707 $abc$16053$new_n2021 pcpi_rs1[23] $0\reg_out[31:0][23] -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$16053$new_n1610 reg_pc[23] decoded_imm[23] $abc$16053$new_n2708 $abc$16053$new_n2709 $abc$16053$new_n2707 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[21] decoded_imm[21] reg_pc[22] decoded_imm[22] $abc$16053$new_n2696 $abc$16053$new_n2708 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[55] $abc$16053$new_n2710 count_instr[23] $abc$16053$new_n2709 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[55] count_cycle[23] $abc$16053$new_n2710 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[23] $abc$16053$new_n2711 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2714 $abc$16053$new_n1610 $abc$16053$new_n2713 $abc$16053$new_n2453 $abc$16053$new_n2716 $0\reg_out[31:0][24] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[24] decoded_imm[24] reg_pc[23] decoded_imm[23] $abc$16053$new_n2708 $abc$16053$new_n2713 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2715 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[24] $abc$16053$new_n2714 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names latched_is_lb $abc$16053$new_n2665 mem_rdata[24] $abc$16053$new_n2666 $abc$16053$new_n2715 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names instr_rdinstrh $abc$16053$new_n2717 count_instr[56] count_instr[24] instr_rdinstr $abc$16053$new_n2716 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[56] count_cycle[24] $abc$16053$new_n2717 -00000 1 -00010 1 -10000 1 -10001 1 -.names $abc$16053$new_n2454 $abc$16053$new_n2723 $abc$16053$new_n2719 $abc$16053$new_n2021 pcpi_rs1[25] $0\reg_out[31:0][25] -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$16053$new_n1610 reg_pc[25] decoded_imm[25] $abc$16053$new_n2720 $abc$16053$new_n2721 $abc$16053$new_n2719 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[23] decoded_imm[23] reg_pc[24] decoded_imm[24] $abc$16053$new_n2708 $abc$16053$new_n2720 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[57] $abc$16053$new_n2722 count_instr[25] $abc$16053$new_n2721 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[57] count_cycle[25] $abc$16053$new_n2722 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[25] $abc$16053$new_n2723 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2726 $abc$16053$new_n1610 $abc$16053$new_n2725 $abc$16053$new_n2453 $abc$16053$new_n2728 $0\reg_out[31:0][26] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[26] decoded_imm[26] reg_pc[25] decoded_imm[25] $abc$16053$new_n2720 $abc$16053$new_n2725 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2727 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[26] $abc$16053$new_n2726 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names latched_is_lb $abc$16053$new_n2665 mem_rdata[26] $abc$16053$new_n2666 $abc$16053$new_n2727 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names instr_rdinstrh $abc$16053$new_n2729 count_instr[58] count_instr[26] instr_rdinstr $abc$16053$new_n2728 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[58] count_cycle[26] $abc$16053$new_n2729 -00000 1 -00010 1 -10000 1 -10001 1 -.names $abc$16053$new_n2454 $abc$16053$new_n2735 $abc$16053$new_n2731 $abc$16053$new_n2021 pcpi_rs1[27] $0\reg_out[31:0][27] -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$16053$new_n1610 reg_pc[27] decoded_imm[27] $abc$16053$new_n2732 $abc$16053$new_n2733 $abc$16053$new_n2731 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[25] decoded_imm[25] reg_pc[26] decoded_imm[26] $abc$16053$new_n2720 $abc$16053$new_n2732 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[59] $abc$16053$new_n2734 count_instr[27] $abc$16053$new_n2733 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[59] count_cycle[27] $abc$16053$new_n2734 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[27] $abc$16053$new_n2735 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2738 $abc$16053$new_n1610 $abc$16053$new_n2737 $abc$16053$new_n2453 $abc$16053$new_n2740 $0\reg_out[31:0][28] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names reg_pc[28] decoded_imm[28] reg_pc[27] decoded_imm[27] $abc$16053$new_n2732 $abc$16053$new_n2737 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2739 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[28] $abc$16053$new_n2738 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names latched_is_lb $abc$16053$new_n2665 mem_rdata[28] $abc$16053$new_n2666 $abc$16053$new_n2739 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names instr_rdinstrh $abc$16053$new_n2741 count_instr[60] count_instr[28] instr_rdinstr $abc$16053$new_n2740 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[60] count_cycle[28] $abc$16053$new_n2741 -00000 1 -00010 1 -10000 1 -10001 1 -.names $abc$16053$new_n2745 $abc$16053$new_n2743 $abc$16053$new_n2453 $abc$16053$new_n2747 $0\reg_out[31:0][29] -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n1610 reg_pc[29] decoded_imm[29] $abc$16053$new_n2744 $abc$16053$new_n2743 -1000 1 -1011 1 -1101 1 -1110 1 -.names reg_pc[27] decoded_imm[27] reg_pc[28] decoded_imm[28] $abc$16053$new_n2732 $abc$16053$new_n2744 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2746 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[29] $abc$16053$new_n2745 -00011 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names latched_is_lb $abc$16053$new_n2665 mem_rdata[29] $abc$16053$new_n2666 $abc$16053$new_n2746 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names instr_rdinstrh $abc$16053$new_n2748 count_instr[61] count_instr[29] instr_rdinstr $abc$16053$new_n2747 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[61] count_cycle[29] $abc$16053$new_n2748 -00000 1 -00010 1 -10000 1 -10001 1 -.names reg_pc[29] decoded_imm[29] $abc$16053$new_n2744 $abc$16053$new_n2750 -000 1 -001 1 -011 1 -101 1 -.names $abc$16053$new_n2753 $abc$16053$new_n2021 pcpi_rs1[30] $abc$16053$new_n2022 $abc$16053$new_n2752 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[30] $abc$16053$new_n2753 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2761 $abc$16053$new_n2021 $abc$16053$new_n2757 pcpi_rs1[31] $0\reg_out[31:0][31] -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$16053$new_n1610 reg_pc[31] decoded_imm[31] $abc$16053$new_n2758 $abc$16053$new_n2759 $abc$16053$new_n2757 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names reg_pc[29] decoded_imm[29] reg_pc[30] decoded_imm[30] $abc$16053$new_n2744 $abc$16053$new_n2758 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names instr_rdinstrh instr_rdinstr count_instr[63] $abc$16053$new_n2760 count_instr[31] $abc$16053$new_n2759 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instr_rdcycleh count_cycle[63] count_cycle[31] $abc$16053$new_n2760 -000 1 -010 1 -100 1 -101 1 -.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[31] $abc$16053$new_n2761 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2453 $abc$16053$new_n2497 $abc$16053$new_n2763 $abc$16053$procmux$1608_CMP $abc$16053$new_n1612 $0\set_mem_do_wdata[0:0] -11100 1 -.names resetn $abc$16053$new_n1620 $abc$16053$new_n2763 -11 1 -.names resetn $abc$16053$new_n2460 $0\set_mem_do_rdata[0:0] -11 1 -.names $abc$16053$new_n2018 $abc$16053$new_n2457 $abc$16053$new_n2763 $abc$16053$procmux$1608_CMP $abc$16053$new_n1612 $0\set_mem_do_rinst[0:0] -11100 1 -.names $abc$16053$new_n2767 $abc$16053$new_n1548 $abc$16053$new_n1610 $abc$16053$new_n2457 $0\decoder_trigger[0:0] -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2019 $abc$16053$new_n2767 -10 1 -.names $abc$16053$new_n2772 $abc$16053$new_n2770 cpu_state[0] $abc$16053$new_n2769 $abc$16053$new_n2771 $abc$16053$procmux$2235_Y[0] -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names is_lb_lh_lw_lbu_lhu $abc$16053$new_n2386 $abc$16053$new_n2769 -10 1 -.names $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2453 $abc$16053$new_n2770 -10 1 -.names $abc$16053$new_n1622 $abc$16053$new_n1624 is_slli_srli_srai $abc$16053$new_n2771 -110 1 -.names resetn $abc$16053$new_n2773 $abc$16053$new_n2772 -10 1 -.names resetn $abc$16053$new_n2774 mem_wordsize[1] $abc$16053$new_n1551 $abc$16053$new_n2773 -1100 1 -.names pcpi_rs1[0] pcpi_rs1[1] mem_wordsize[0] $abc$16053$new_n2774 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$16053$new_n2772 $abc$16053$new_n2020 $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2776 $abc$16053$procmux$2235_Y[1] -1000 1 -1010 1 -1100 1 -1101 1 -.names cpu_state[1] is_sb_sh_sw is_sll_srl_sra $abc$16053$new_n1620 $abc$16053$new_n2777 $abc$16053$new_n2776 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n1621 $abc$16053$new_n2385 is_lb_lh_lw_lbu_lhu $abc$16053$new_n2777 -000 1 -001 1 -011 1 -.names $abc$16053$new_n2772 $abc$16053$new_n2779 $abc$16053$new_n2038 cpu_state[2] $abc$16053$new_n2018 $abc$16053$procmux$2235_Y[2] -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1620 is_sll_srl_sra $abc$16053$new_n2777 $abc$16053$new_n1624 $abc$16053$new_n2532 $abc$16053$new_n2779 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -.names $abc$16053$new_n2782 $abc$16053$new_n2781 cpu_state[3] $abc$16053$procmux$2235_Y[3] -101 1 -110 1 -111 1 -.names $abc$16053$new_n1620 $abc$16053$new_n1623 is_sll_srl_sra $abc$16053$new_n2777 is_sb_sh_sw $abc$16053$new_n2781 -00000 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2772 $abc$16053$new_n2018 $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1549 $abc$16053$new_n2782 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names cpu_state[4] $abc$16053$new_n2772 $abc$16053$new_n1620 $abc$16053$procmux$2235_Y[4] -111 1 -.names $abc$16053$new_n1620 $abc$16053$new_n2772 cpu_state[5] $abc$16053$new_n1991 instr_jal $abc$16053$procmux$2235_Y[5] -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names resetn cpu_state[6] $abc$16053$new_n1612 $abc$16053$new_n2380 $abc$16053$new_n2789 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -.names resetn $abc$16053$new_n2773 cpu_state[7] $abc$16053$new_n2771 $abc$16053$new_n2386 $abc$16053$procmux$2235_Y[7] -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2792 $abc$16053$new_n2793 pcpi_rs1[0] mem_la_wdata[0] $abc$16053$new_n2794 alu_out[0] -00011 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names is_compare $abc$16053$new_n2393 instr_xor instr_xori $abc$16053$new_n2405 $abc$16053$new_n2792 -11000 1 -.names $abc$16053$new_n2393 pcpi_rs1[0] instr_and instr_andi mem_la_wdata[0] $abc$16053$new_n2793 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names $abc$16053$new_n2393 is_compare instr_xor instr_xori $abc$16053$new_n2794 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$16053$new_n2794 pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2797 $abc$16053$new_n2796 alu_out[1] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[1] instr_and instr_andi mem_la_wdata[1] $abc$16053$new_n2796 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names mem_la_wdata[0] instr_sub pcpi_rs1[0] instr_xor instr_xori $abc$16053$new_n2797 -10100 1 -11000 1 -.names $abc$16053$new_n2794 pcpi_rs1[2] mem_la_wdata[2] $abc$16053$new_n2799 $abc$16053$new_n2802 alu_out[2] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2800 $abc$16053$new_n2801 $abc$16053$new_n2799 -00000 1 -00010 1 -10000 1 -10001 1 -.names mem_la_wdata[0] pcpi_rs1[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2800 -0000 1 -0010 1 -0011 1 -0100 1 -0110 1 -0111 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names pcpi_rs1[0] mem_la_wdata[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2801 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names $abc$16053$new_n2393 pcpi_rs1[2] instr_and instr_andi mem_la_wdata[2] $abc$16053$new_n2802 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2794 $abc$16053$new_n2804 $abc$16053$new_n2806 alu_out[3] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_xor instr_xori $abc$16053$new_n2805 $abc$16053$new_n2804 -000 1 -.names instr_sub pcpi_rs1[2] mem_la_wdata[2] $abc$16053$new_n2801 $abc$16053$new_n2800 $abc$16053$new_n2805 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -10001 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[3] mem_la_wdata[3] instr_and instr_andi $abc$16053$new_n2806 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[4] mem_la_wdata[4] $abc$16053$new_n2808 $abc$16053$new_n2811 alu_out[4] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2809 $abc$16053$new_n2810 $abc$16053$new_n2808 -00000 1 -00001 1 -10001 1 -10011 1 -.names pcpi_rs1[2] mem_la_wdata[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2801 $abc$16053$new_n2809 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names mem_la_wdata[2] pcpi_rs1[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2800 $abc$16053$new_n2810 -00000 1 -00010 1 -00011 1 -00110 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -.names $abc$16053$new_n2393 pcpi_rs1[4] instr_and instr_andi mem_la_wdata[4] $abc$16053$new_n2811 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2794 $abc$16053$new_n3203 $abc$16053$new_n2816 alu_out[5] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[5] mem_la_wdata[5] instr_and instr_andi $abc$16053$new_n2816 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[6] mem_la_wdata[6] $abc$16053$new_n2818 $abc$16053$new_n2821 alu_out[6] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2819 $abc$16053$new_n2820 $abc$16053$new_n2818 -00000 1 -00001 1 -10001 1 -10011 1 -.names pcpi_rs1[4] mem_la_wdata[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2809 $abc$16053$new_n2819 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names mem_la_wdata[4] pcpi_rs1[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2810 $abc$16053$new_n2820 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[6] instr_and instr_andi mem_la_wdata[6] $abc$16053$new_n2821 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2794 $abc$16053$new_n3205 $abc$16053$new_n2826 alu_out[7] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[7] mem_la_wdata[7] instr_and instr_andi $abc$16053$new_n2826 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[8] pcpi_rs2[8] $abc$16053$new_n2828 $abc$16053$new_n2831 alu_out[8] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2829 $abc$16053$new_n2830 $abc$16053$new_n2828 -00010 1 -00011 1 -10001 1 -10011 1 -.names pcpi_rs1[6] mem_la_wdata[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2819 $abc$16053$new_n2829 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names mem_la_wdata[6] pcpi_rs1[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2820 $abc$16053$new_n2830 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[8] instr_and instr_andi pcpi_rs2[8] $abc$16053$new_n2831 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2794 $abc$16053$new_n3207 $abc$16053$new_n2835 alu_out[9] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[9] pcpi_rs2[9] instr_and instr_andi $abc$16053$new_n2835 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[10] pcpi_rs2[10] $abc$16053$new_n2837 $abc$16053$new_n2840 alu_out[10] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2838 $abc$16053$new_n2839 $abc$16053$new_n2837 -00010 1 -00011 1 -10001 1 -10011 1 -.names pcpi_rs1[8] pcpi_rs2[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2829 $abc$16053$new_n2838 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs2[8] pcpi_rs1[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2830 $abc$16053$new_n2839 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[10] instr_and instr_andi pcpi_rs2[10] $abc$16053$new_n2840 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2794 $abc$16053$new_n3209 $abc$16053$new_n2845 alu_out[11] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[11] pcpi_rs2[11] instr_and instr_andi $abc$16053$new_n2845 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[12] pcpi_rs2[12] $abc$16053$new_n2847 $abc$16053$new_n2850 alu_out[12] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2848 $abc$16053$new_n2849 $abc$16053$new_n2847 -00010 1 -00011 1 -10001 1 -10011 1 -.names pcpi_rs1[10] pcpi_rs2[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2838 $abc$16053$new_n2848 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs2[10] pcpi_rs1[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2839 $abc$16053$new_n2849 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[12] instr_and instr_andi pcpi_rs2[12] $abc$16053$new_n2850 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2794 $abc$16053$new_n3211 $abc$16053$new_n2855 alu_out[13] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[13] pcpi_rs2[13] instr_and instr_andi $abc$16053$new_n2855 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[14] pcpi_rs2[14] $abc$16053$new_n2857 $abc$16053$new_n2860 alu_out[14] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2858 $abc$16053$new_n2859 $abc$16053$new_n2857 -00010 1 -00011 1 -10001 1 -10011 1 -.names pcpi_rs1[12] pcpi_rs2[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2848 $abc$16053$new_n2858 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs2[12] pcpi_rs1[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2849 $abc$16053$new_n2859 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[14] instr_and instr_andi pcpi_rs2[14] $abc$16053$new_n2860 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2794 $abc$16053$new_n3213 $abc$16053$new_n2864 alu_out[15] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[15] pcpi_rs2[15] instr_and instr_andi $abc$16053$new_n2864 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[16] pcpi_rs2[16] $abc$16053$new_n2866 $abc$16053$new_n2869 alu_out[16] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2867 $abc$16053$new_n2868 $abc$16053$new_n2866 -00010 1 -00011 1 -10001 1 -10011 1 -.names pcpi_rs1[14] pcpi_rs2[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2858 $abc$16053$new_n2867 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs2[14] pcpi_rs1[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2859 $abc$16053$new_n2868 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[16] instr_and instr_andi pcpi_rs2[16] $abc$16053$new_n2869 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2794 $abc$16053$new_n3215 $abc$16053$new_n2873 alu_out[17] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[17] pcpi_rs2[17] instr_and instr_andi $abc$16053$new_n2873 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[18] pcpi_rs2[18] $abc$16053$new_n2875 $abc$16053$new_n2878 alu_out[18] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_sub instr_xor instr_xori $abc$16053$new_n2876 $abc$16053$new_n2877 $abc$16053$new_n2875 -00010 1 -00011 1 -10001 1 -10011 1 -.names pcpi_rs1[16] pcpi_rs2[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2867 $abc$16053$new_n2876 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pcpi_rs2[16] pcpi_rs1[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2868 $abc$16053$new_n2877 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[18] instr_and instr_andi pcpi_rs2[18] $abc$16053$new_n2878 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2794 $abc$16053$new_n3217 $abc$16053$new_n2883 alu_out[19] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[19] pcpi_rs2[19] instr_and instr_andi $abc$16053$new_n2883 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[20] pcpi_rs2[20] $abc$16053$new_n2885 $abc$16053$new_n2889 alu_out[20] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_xor $abc$16053$new_n2887 instr_xori $abc$16053$new_n2886 instr_sub $abc$16053$new_n2885 -00001 1 -00010 1 -00011 1 -.names pcpi_rs1[18] pcpi_rs2[18] pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2876 $abc$16053$new_n2886 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_sub $abc$16053$new_n2888 $abc$16053$new_n2439 $abc$16053$new_n2877 $abc$16053$new_n2887 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names pcpi_rs1[18] pcpi_rs1[19] pcpi_rs2[18] pcpi_rs2[19] $abc$16053$new_n2888 -0100 1 -0110 1 -1000 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n2393 pcpi_rs1[20] instr_and instr_andi pcpi_rs2[20] $abc$16053$new_n2889 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2794 $abc$16053$new_n2891 $abc$16053$new_n2893 alu_out[21] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2892 pcpi_rs1[20] $abc$16053$new_n2886 instr_sub pcpi_rs2[20] $abc$16053$new_n2891 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instr_xor instr_xori $abc$16053$new_n2887 pcpi_rs2[20] pcpi_rs1[20] $abc$16053$new_n2892 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -.names $abc$16053$new_n2393 pcpi_rs1[21] pcpi_rs2[21] instr_and instr_andi $abc$16053$new_n2893 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[22] pcpi_rs2[22] $abc$16053$new_n2895 $abc$16053$new_n2899 alu_out[22] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2897 instr_xor instr_xori $abc$16053$new_n2896 instr_sub $abc$16053$new_n2895 -10001 1 -10010 1 -10011 1 -.names pcpi_rs1[20] pcpi_rs2[20] pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2886 $abc$16053$new_n2896 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2437 $abc$16053$new_n2887 instr_sub $abc$16053$new_n2898 $abc$16053$new_n2897 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names pcpi_rs1[20] pcpi_rs1[21] pcpi_rs2[20] pcpi_rs2[21] $abc$16053$new_n2898 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0111 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names $abc$16053$new_n2393 pcpi_rs1[22] instr_and instr_andi pcpi_rs2[22] $abc$16053$new_n2899 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2794 $abc$16053$new_n2901 $abc$16053$new_n2903 alu_out[23] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2902 pcpi_rs1[22] $abc$16053$new_n2896 instr_sub pcpi_rs2[22] $abc$16053$new_n2901 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instr_xor instr_xori $abc$16053$new_n2897 pcpi_rs2[22] pcpi_rs1[22] $abc$16053$new_n2902 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -.names $abc$16053$new_n2393 pcpi_rs1[23] pcpi_rs2[23] instr_and instr_andi $abc$16053$new_n2903 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[24] pcpi_rs2[24] $abc$16053$new_n2905 $abc$16053$new_n2910 alu_out[24] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_xor $abc$16053$new_n2907 instr_xori $abc$16053$new_n2906 instr_sub $abc$16053$new_n2905 -00001 1 -00010 1 -00011 1 -.names pcpi_rs1[22] pcpi_rs2[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2896 $abc$16053$new_n2906 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_sub $abc$16053$new_n2908 $abc$16053$new_n2907 -10 1 -.names $abc$16053$new_n2909 $abc$16053$new_n2888 $abc$16053$new_n2436 $abc$16053$new_n2877 $abc$16053$new_n2439 $abc$16053$new_n2908 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pcpi_rs2[22] pcpi_rs1[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2898 $abc$16053$new_n2909 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[24] instr_and instr_andi pcpi_rs2[24] $abc$16053$new_n2910 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2794 $abc$16053$new_n2912 $abc$16053$new_n2914 alu_out[25] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2913 pcpi_rs1[24] $abc$16053$new_n2906 instr_sub pcpi_rs2[24] $abc$16053$new_n2912 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instr_xor instr_xori $abc$16053$new_n2907 pcpi_rs2[24] pcpi_rs1[24] $abc$16053$new_n2913 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -.names $abc$16053$new_n2393 pcpi_rs1[25] pcpi_rs2[25] instr_and instr_andi $abc$16053$new_n2914 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2794 pcpi_rs1[26] pcpi_rs2[26] $abc$16053$new_n2916 $abc$16053$new_n2920 alu_out[26] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_xor $abc$16053$new_n2918 instr_xori $abc$16053$new_n2917 instr_sub $abc$16053$new_n2916 -00001 1 -00010 1 -00011 1 -.names pcpi_rs1[24] pcpi_rs2[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2906 $abc$16053$new_n2917 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_sub $abc$16053$new_n2919 $abc$16053$new_n2918 -10 1 -.names pcpi_rs2[24] pcpi_rs1[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2908 $abc$16053$new_n2919 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[26] instr_and instr_andi pcpi_rs2[26] $abc$16053$new_n2920 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -.names pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2794 $abc$16053$new_n2922 $abc$16053$new_n2924 alu_out[27] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2923 pcpi_rs1[26] $abc$16053$new_n2917 instr_sub pcpi_rs2[26] $abc$16053$new_n2922 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instr_xor instr_xori $abc$16053$new_n2918 pcpi_rs2[26] pcpi_rs1[26] $abc$16053$new_n2923 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -.names $abc$16053$new_n2393 pcpi_rs1[27] pcpi_rs2[27] instr_and instr_andi $abc$16053$new_n2924 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names pcpi_rs1[28] pcpi_rs2[28] $abc$16053$new_n2794 $abc$16053$new_n2926 $abc$16053$new_n2930 alu_out[28] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instr_xor $abc$16053$new_n2928 instr_xori $abc$16053$new_n2927 instr_sub $abc$16053$new_n2926 -00001 1 -00010 1 -00011 1 -.names pcpi_rs1[26] pcpi_rs2[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2917 $abc$16053$new_n2927 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_sub $abc$16053$new_n2929 $abc$16053$new_n2928 -10 1 -.names pcpi_rs2[26] pcpi_rs1[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2919 $abc$16053$new_n2929 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[28] pcpi_rs2[28] instr_and instr_andi $abc$16053$new_n2930 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2794 $abc$16053$new_n2932 $abc$16053$new_n2934 alu_out[29] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2933 pcpi_rs1[28] $abc$16053$new_n2927 instr_sub pcpi_rs2[28] $abc$16053$new_n2932 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instr_xor instr_xori $abc$16053$new_n2928 pcpi_rs2[28] pcpi_rs1[28] $abc$16053$new_n2933 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -.names $abc$16053$new_n2393 pcpi_rs1[29] pcpi_rs2[29] instr_and instr_andi $abc$16053$new_n2934 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2794 $abc$16053$new_n2936 $abc$16053$new_n2940 alu_out[30] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2938 instr_xor instr_xori $abc$16053$new_n2937 instr_sub $abc$16053$new_n2936 -10000 1 -10001 1 -10011 1 -.names pcpi_rs1[28] pcpi_rs2[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2927 $abc$16053$new_n2937 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names instr_sub $abc$16053$new_n2939 $abc$16053$new_n2938 -00 1 -01 1 -11 1 -.names pcpi_rs2[28] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2929 $abc$16053$new_n2939 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2393 pcpi_rs1[30] pcpi_rs2[30] instr_and instr_andi $abc$16053$new_n2940 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names pcpi_rs1[31] pcpi_rs2[31] $abc$16053$new_n2794 $abc$16053$new_n2942 $abc$16053$new_n2944 alu_out[31] -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2943 pcpi_rs1[30] instr_sub $abc$16053$new_n2937 pcpi_rs2[30] $abc$16053$new_n2942 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instr_xor instr_xori $abc$16053$new_n2938 pcpi_rs2[30] pcpi_rs1[30] $abc$16053$new_n2943 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -.names $abc$16053$new_n2393 pcpi_rs1[31] pcpi_rs2[31] instr_and instr_andi $abc$16053$new_n2944 -00000 1 -00100 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2946 latched_stalu reg_pc[0] alu_out_q[0] reg_out[0] cpuregs_wrdata[0] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names latched_store latched_branch $abc$16053$new_n2946 -10 1 -.names $abc$16053$new_n2946 $abc$16053$new_n1766 reg_pc[1] cpuregs_wrdata[1] -001 1 -011 1 -100 1 -101 1 -.names $abc$16053$new_n2946 latched_stalu reg_pc[2] alu_out_q[2] reg_out[2] cpuregs_wrdata[2] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n2946 reg_pc[2] reg_pc[3] $abc$16053$new_n1705 cpuregs_wrdata[3] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names $abc$16053$new_n2946 reg_pc[4] reg_pc[2] reg_pc[3] $abc$16053$new_n1709 cpuregs_wrdata[4] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2952 alu_out_q[5] reg_out[5] cpuregs_wrdata[5] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[5] reg_pc[2] reg_pc[3] reg_pc[4] $abc$16053$new_n2952 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2954 alu_out_q[6] reg_out[6] cpuregs_wrdata[6] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[6] reg_pc[2] reg_pc[3] reg_pc[4] reg_pc[5] $abc$16053$new_n2954 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[7] $abc$16053$new_n2956 $abc$16053$new_n1712 cpuregs_wrdata[7] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[2] reg_pc[3] reg_pc[4] reg_pc[5] reg_pc[6] $abc$16053$new_n2956 -11111 1 -.names $abc$16053$new_n2946 reg_pc[8] reg_pc[7] $abc$16053$new_n2956 $abc$16053$new_n1714 cpuregs_wrdata[8] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2959 alu_out_q[9] reg_out[9] cpuregs_wrdata[9] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[9] reg_pc[7] reg_pc[8] $abc$16053$new_n2956 $abc$16053$new_n2959 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2961 alu_out_q[10] reg_out[10] cpuregs_wrdata[10] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[10] reg_pc[7] reg_pc[8] reg_pc[9] $abc$16053$new_n2956 $abc$16053$new_n2961 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[11] $abc$16053$new_n2963 $abc$16053$new_n1716 cpuregs_wrdata[11] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[7] reg_pc[8] reg_pc[9] reg_pc[10] $abc$16053$new_n2956 $abc$16053$new_n2963 -11111 1 -.names $abc$16053$new_n2946 reg_pc[12] reg_pc[11] $abc$16053$new_n2963 $abc$16053$new_n1724 cpuregs_wrdata[12] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2966 alu_out_q[13] reg_out[13] cpuregs_wrdata[13] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[13] reg_pc[11] reg_pc[12] $abc$16053$new_n2963 $abc$16053$new_n2966 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2968 alu_out_q[14] reg_out[14] cpuregs_wrdata[14] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[14] reg_pc[11] reg_pc[12] reg_pc[13] $abc$16053$new_n2963 $abc$16053$new_n2968 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[15] $abc$16053$new_n2970 $abc$16053$new_n1720 cpuregs_wrdata[15] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[11] reg_pc[12] reg_pc[13] reg_pc[14] $abc$16053$new_n2963 $abc$16053$new_n2970 -11111 1 -.names $abc$16053$new_n2946 reg_pc[16] reg_pc[15] $abc$16053$new_n2970 $abc$16053$new_n1730 cpuregs_wrdata[16] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2973 alu_out_q[17] reg_out[17] cpuregs_wrdata[17] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[17] reg_pc[15] reg_pc[16] $abc$16053$new_n2970 $abc$16053$new_n2973 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2975 alu_out_q[18] reg_out[18] cpuregs_wrdata[18] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[18] reg_pc[15] reg_pc[16] reg_pc[17] $abc$16053$new_n2970 $abc$16053$new_n2975 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[19] $abc$16053$new_n2977 $abc$16053$new_n1726 cpuregs_wrdata[19] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[15] reg_pc[16] reg_pc[17] reg_pc[18] $abc$16053$new_n2970 $abc$16053$new_n2977 -11111 1 -.names $abc$16053$new_n2946 reg_pc[20] reg_pc[19] $abc$16053$new_n2977 $abc$16053$new_n1734 cpuregs_wrdata[20] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[21] $abc$16053$new_n2980 $abc$16053$new_n1732 cpuregs_wrdata[21] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[19] reg_pc[20] $abc$16053$new_n2977 $abc$16053$new_n2980 -111 1 -.names $abc$16053$new_n2946 reg_pc[22] reg_pc[21] $abc$16053$new_n2980 $abc$16053$new_n1736 cpuregs_wrdata[22] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[23] $abc$16053$new_n2983 $abc$16053$new_n1738 cpuregs_wrdata[23] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[21] reg_pc[22] $abc$16053$new_n2980 $abc$16053$new_n2983 -111 1 -.names $abc$16053$new_n2946 reg_pc[24] reg_pc[23] $abc$16053$new_n2983 $abc$16053$new_n1746 cpuregs_wrdata[24] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[25] $abc$16053$new_n2986 $abc$16053$new_n1744 cpuregs_wrdata[25] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[23] reg_pc[24] $abc$16053$new_n2983 $abc$16053$new_n2986 -111 1 -.names $abc$16053$new_n2946 reg_pc[26] reg_pc[25] $abc$16053$new_n2986 $abc$16053$new_n1742 cpuregs_wrdata[26] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[27] $abc$16053$new_n2989 $abc$16053$new_n1740 cpuregs_wrdata[27] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[25] reg_pc[26] $abc$16053$new_n2986 $abc$16053$new_n2989 -111 1 -.names $abc$16053$new_n2946 reg_pc[28] reg_pc[27] $abc$16053$new_n2989 $abc$16053$new_n1749 cpuregs_wrdata[28] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2992 alu_out_q[29] reg_out[29] cpuregs_wrdata[29] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[29] reg_pc[27] reg_pc[28] $abc$16053$new_n2989 $abc$16053$new_n2992 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2994 alu_out_q[30] reg_out[30] cpuregs_wrdata[30] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names reg_pc[30] reg_pc[27] reg_pc[28] reg_pc[29] $abc$16053$new_n2989 $abc$16053$new_n2994 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n2946 reg_pc[31] $abc$16053$new_n2996 $abc$16053$new_n2373 cpuregs_wrdata[31] -0010 1 -0011 1 -0100 1 -0101 1 -1000 1 -1010 1 -1100 1 -1110 1 -.names reg_pc[27] reg_pc[28] reg_pc[29] reg_pc[30] $abc$16053$new_n2989 $abc$16053$new_n2996 -11111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[19] decoded_rs1[4] $0\decoded_rs1[4:0][4] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[15] decoded_rs1[0] $0\decoded_rs1[4:0][0] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[16] decoded_rs1[1] $0\decoded_rs1[4:0][1] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[17] decoded_rs1[2] $0\decoded_rs1[4:0][2] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[18] decoded_rs1[3] $0\decoded_rs1[4:0][3] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[20] decoded_rs2[0] $0\decoded_rs2[4:0][0] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[21] decoded_rs2[1] $0\decoded_rs2[4:0][1] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[22] decoded_rs2[2] $0\decoded_rs2[4:0][2] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[23] decoded_rs2[3] $0\decoded_rs2[4:0][3] -001 1 -011 1 -110 1 -111 1 -.names $abc$16053$new_n1548 mem_rdata_latched[24] decoded_rs2[4] $0\decoded_rs2[4:0][4] -001 1 -011 1 -110 1 -111 1 -.names count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[1] -01 1 -10 1 -.names count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[2] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[4] count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[4] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[5] -01 1 -10 1 -.names count_cycle[4] count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $abc$16053$new_n3012 -11111 1 -.names count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[6] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[7] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[8] count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[8] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[9] -01 1 -10 1 -.names count_cycle[8] count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $abc$16053$new_n3017 -11111 1 -.names count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[10] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[11] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[12] count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[12] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[13] -01 1 -10 1 -.names count_cycle[12] count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $abc$16053$new_n3022 -11111 1 -.names count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[14] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[15] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[16] count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[16] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[17] $abc$16053$new_n3027 $auto$alumacc.cc:485:replace_alu$4638.Y[17] -01 1 -10 1 -.names count_cycle[16] count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $abc$16053$new_n3027 -11111 1 -.names count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[18] -01 1 -10 1 -.names count_cycle[17] $abc$16053$new_n3027 $abc$16053$new_n3029 -11 1 -.names count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[19] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[20] count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[20] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[21] -01 1 -10 1 -.names count_cycle[20] count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $abc$16053$new_n3033 -1111 1 -.names count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[22] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[23] count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[23] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[24] -01 1 -10 1 -.names count_cycle[23] count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $abc$16053$new_n3037 -1111 1 -.names count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[25] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[26] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[27] count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[27] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[28] -01 1 -10 1 -.names count_cycle[27] count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $abc$16053$new_n3042 -11111 1 -.names count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[29] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[30] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[31] count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[31] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[32] $abc$16053$new_n3047 $auto$alumacc.cc:485:replace_alu$4638.Y[32] -01 1 -10 1 -.names count_cycle[31] count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $abc$16053$new_n3047 -11111 1 -.names count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[33] -01 1 -10 1 -.names count_cycle[32] $abc$16053$new_n3047 $abc$16053$new_n3049 -11 1 -.names count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[34] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[35] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[36] count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[36] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[37] -01 1 -10 1 -.names count_cycle[36] count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $abc$16053$new_n3054 -11111 1 -.names count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[38] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[39] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[40] count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[40] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[41] -01 1 -10 1 -.names count_cycle[40] count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $abc$16053$new_n3059 -11111 1 -.names count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[42] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[43] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[44] count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[44] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[45] -01 1 -10 1 -.names count_cycle[44] count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $abc$16053$new_n3064 -11111 1 -.names count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[46] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[47] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[48] count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[48] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[49] -01 1 -10 1 -.names count_cycle[48] count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $abc$16053$new_n3069 -11111 1 -.names count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[50] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[51] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[52] count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[52] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[53] -01 1 -10 1 -.names count_cycle[52] count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $abc$16053$new_n3074 -11111 1 -.names count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[54] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[55] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[56] count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[56] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[57] -01 1 -10 1 -.names count_cycle[56] count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $abc$16053$new_n3079 -11111 1 -.names count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[58] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[59] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names count_cycle[60] count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[60] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[61] -01 1 -10 1 -.names count_cycle[60] count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $abc$16053$new_n3084 -11111 1 -.names count_cycle[62] count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[62] -011 1 -100 1 -101 1 -110 1 -.names count_cycle[63] count_cycle[62] count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[63] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0\decoded_rs1[4:0][2] latched_rd[2] latched_rd[1] $0\decoded_rs1[4:0][1] $abc$16053$new_n3091 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0\decoded_rs2[4:0][2] latched_rd[2] latched_rd[1] $0\decoded_rs2[4:0][1] $abc$16053$new_n3096 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.X[0] -0 1 -.names decoder_trigger instr_jal $abc$16053$new_n1751 decoded_imm_j[30] $abc$16053$new_n1690 $abc$16053$new_n3098 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1750 $abc$16053$new_n3098 reg_next_pc[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14611 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names instr_jal $abc$16053$new_n1769 decoded_imm_j[29] $abc$16053$new_n1691 $abc$16053$new_n1748 $abc$16053$new_n3100 -00010 1 -00110 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1747 decoder_trigger $abc$16053$new_n3100 reg_next_pc[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14613 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11110 1 -11111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1752 decoded_imm_j[28] $abc$16053$new_n1691 $abc$16053$new_n3102 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1748 $abc$16053$new_n3102 reg_next_pc[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14615 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoded_imm_j[27] $abc$16053$new_n1741 instr_jal decoded_imm_j[26] $abc$16053$new_n1753 $abc$16053$new_n3104 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n1739 decoder_trigger $abc$16053$new_n3104 $abc$16053$new_n1777 instr_jal $abc$16053$new_n3105 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n3105 reg_next_pc[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14617 -001 1 -011 1 -110 1 -111 1 -.names decoder_trigger instr_jal decoded_imm_j[26] $abc$16053$new_n1753 $abc$16053$new_n1777 $abc$16053$new_n3107 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1741 $abc$16053$new_n3107 reg_next_pc[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14619 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1787 decoded_imm_j[25] $abc$16053$new_n1778 $abc$16053$new_n3109 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1743 $abc$16053$new_n3109 reg_next_pc[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14621 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1754 decoded_imm_j[24] $abc$16053$new_n1692 $abc$16053$new_n3111 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1745 $abc$16053$new_n3111 reg_next_pc[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14623 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1793 decoded_imm_j[23] $abc$16053$new_n1693 $abc$16053$new_n3113 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1737 $abc$16053$new_n3113 reg_next_pc[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14625 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1755 decoded_imm_j[22] $abc$16053$new_n1694 $abc$16053$new_n3115 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1735 $abc$16053$new_n3115 reg_next_pc[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14627 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names instr_jal $abc$16053$new_n1800 decoded_imm_j[21] $abc$16053$new_n1695 $abc$16053$new_n1733 $abc$16053$new_n3117 -00010 1 -00110 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1731 decoder_trigger $abc$16053$new_n3117 reg_next_pc[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14629 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11110 1 -11111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1756 decoded_imm_j[20] $abc$16053$new_n1695 $abc$16053$new_n3119 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1733 $abc$16053$new_n3119 reg_next_pc[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14631 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoded_imm_j[19] $abc$16053$new_n1727 instr_jal decoded_imm_j[18] $abc$16053$new_n1757 $abc$16053$new_n3121 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n1725 decoder_trigger $abc$16053$new_n3121 $abc$16053$new_n1808 instr_jal $abc$16053$new_n3122 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n3122 reg_next_pc[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14633 -001 1 -011 1 -110 1 -111 1 -.names decoder_trigger instr_jal decoded_imm_j[18] $abc$16053$new_n1757 $abc$16053$new_n1808 $abc$16053$new_n3124 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1727 $abc$16053$new_n3124 reg_next_pc[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14635 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1818 decoded_imm_j[17] $abc$16053$new_n1809 $abc$16053$new_n3126 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1728 $abc$16053$new_n3126 reg_next_pc[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14637 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1758 decoded_imm_j[16] $abc$16053$new_n1696 $abc$16053$new_n3128 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1729 $abc$16053$new_n3128 reg_next_pc[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14639 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoded_imm_j[15] $abc$16053$new_n1721 instr_jal decoded_imm_j[14] $abc$16053$new_n1759 $abc$16053$new_n3130 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n1719 decoder_trigger $abc$16053$new_n3130 $abc$16053$new_n1825 instr_jal $abc$16053$new_n3131 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n3131 reg_next_pc[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14641 -001 1 -011 1 -110 1 -111 1 -.names decoder_trigger instr_jal decoded_imm_j[14] $abc$16053$new_n1759 $abc$16053$new_n1825 $abc$16053$new_n3133 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1721 $abc$16053$new_n3133 reg_next_pc[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14643 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1835 decoded_imm_j[13] $abc$16053$new_n1826 $abc$16053$new_n3135 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1722 $abc$16053$new_n3135 reg_next_pc[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14645 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1760 decoded_imm_j[12] $abc$16053$new_n1697 $abc$16053$new_n3137 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1723 $abc$16053$new_n3137 reg_next_pc[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14647 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoded_imm_j[11] $abc$16053$new_n1717 instr_jal decoded_imm_j[10] $abc$16053$new_n1761 $abc$16053$new_n3139 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n1715 decoder_trigger $abc$16053$new_n3139 $abc$16053$new_n1842 instr_jal $abc$16053$new_n3140 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n3140 reg_next_pc[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14649 -001 1 -011 1 -110 1 -111 1 -.names decoder_trigger instr_jal decoded_imm_j[10] $abc$16053$new_n1761 $abc$16053$new_n1842 $abc$16053$new_n3142 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1717 $abc$16053$new_n3142 reg_next_pc[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14651 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1851 decoded_imm_j[9] $abc$16053$new_n1698 $abc$16053$new_n3144 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1718 $abc$16053$new_n3144 reg_next_pc[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14653 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1762 decoded_imm_j[8] $abc$16053$new_n1699 $abc$16053$new_n3146 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1713 $abc$16053$new_n3146 reg_next_pc[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14655 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoder_trigger instr_jal $abc$16053$new_n1858 decoded_imm_j[7] $abc$16053$new_n1700 $abc$16053$new_n3148 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1711 $abc$16053$new_n3148 reg_next_pc[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14657 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names decoded_imm_j[5] $abc$16053$new_n1708 instr_jal decoded_imm_j[4] $abc$16053$new_n1764 $abc$16053$new_n3150 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n1707 decoder_trigger $abc$16053$new_n3150 $abc$16053$new_n1702 instr_jal $abc$16053$new_n3151 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1612 $abc$16053$new_n3151 reg_next_pc[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14661 -001 1 -011 1 -110 1 -111 1 -.names decoded_imm_j[3] $abc$16053$new_n1706 instr_jal $abc$16053$new_n1765 decoded_imm_j[2] $abc$16053$new_n3153 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n1612 $abc$16053$new_n1703 decoder_trigger $abc$16053$new_n3153 reg_next_pc[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14665 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[29] pcpi_rs1[27] $abc$16053$new_n3155 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$16053$new_n2043 $abc$16053$new_n2028 $abc$16053$new_n3155 pcpi_rs1[24] $abc$16053$new_n2025 $abc$16053$new_n3156 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names pcpi_rs1[22] $abc$16053$new_n2084 decoded_imm[22] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3157 -00001 1 -00011 1 -00111 1 -01011 1 -01101 1 -01111 1 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[21] pcpi_rs1[18] $abc$16053$new_n3158 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$16053$new_n2022 $abc$16053$new_n3158 $abc$16053$new_n2025 pcpi_rs1[23] pcpi_rs1[26] $abc$16053$new_n3159 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names $abc$16053$new_n3157 $abc$16053$new_n2033 $abc$16053$new_n3159 $abc$16053$new_n2085 $abc$16053$auto$rtlil.cc:2693:MuxGate$14937 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names pcpi_rs1[14] $abc$16053$new_n2139 decoded_imm[14] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3161 -00001 1 -00011 1 -00111 1 -01011 1 -01101 1 -01111 1 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[10] $abc$16053$new_n3162 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$16053$new_n2022 $abc$16053$new_n3162 $abc$16053$new_n2025 pcpi_rs1[15] pcpi_rs1[18] $abc$16053$new_n3163 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names $abc$16053$new_n3161 $abc$16053$new_n2033 $abc$16053$new_n3163 $abc$16053$new_n2140 $abc$16053$auto$rtlil.cc:2693:MuxGate$14953 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names pcpi_rs1[12] $abc$16053$new_n2153 decoded_imm[12] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3165 -00001 1 -00011 1 -00111 1 -01011 1 -01101 1 -01111 1 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[11] pcpi_rs1[8] $abc$16053$new_n3166 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$16053$new_n2022 $abc$16053$new_n3166 $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[16] $abc$16053$new_n3167 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names $abc$16053$new_n3165 $abc$16053$new_n2033 $abc$16053$new_n3167 $abc$16053$new_n2154 $abc$16053$auto$rtlil.cc:2693:MuxGate$14957 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2013 $abc$16053$new_n2188 $abc$16053$new_n2190 $abc$16053$new_n3169 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n3169 pcpi_rs1[7] $abc$16053$new_n2033 decoded_imm[7] $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14967 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -.names pcpi_rs1[3] $abc$16053$new_n2015 decoded_imm[3] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3171 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[7] pcpi_rs1[4] pcpi_rs1[2] $abc$16053$new_n3172 -00100 1 -00101 1 -00110 1 -00111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$16053$new_n3171 $abc$16053$new_n2033 $abc$16053$new_n2212 $abc$16053$new_n3172 $abc$16053$new_n2022 $abc$16053$auto$rtlil.cc:2693:MuxGate$14975 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[5] pcpi_rs1[2] pcpi_rs1[0] $abc$16053$new_n3174 -00100 1 -00101 1 -00110 1 -00111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$16053$new_n2033 pcpi_rs1[1] $abc$16053$new_n2225 $abc$16053$new_n3174 $abc$16053$new_n2022 $abc$16053$auto$rtlil.cc:2693:MuxGate$14979 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$16053$new_n2358 decoded_imm[31] $abc$16053$new_n2019 $abc$16053$new_n2038 $abc$16053$new_n2026 $abc$16053$new_n3176 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01100 1 -01101 1 -01111 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n2033 $abc$16053$new_n3176 pcpi_rs1[31] $abc$16053$new_n2019 $abc$16053$new_n2360 $abc$16053$auto$rtlil.cc:2693:MuxGate$15109 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11110 1 -.names pcpi_rs1[0] mem_rdata[9] mem_rdata[1] $abc$16053$new_n3178 -001 1 -011 1 -110 1 -111 1 -.names pcpi_rs1[1] pcpi_rs1[0] $abc$16053$new_n3178 mem_rdata[25] mem_rdata[17] $abc$16053$new_n3179 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$16053$new_n1442 $abc$16053$new_n2513 $abc$16053$new_n3179 mem_rdata[17] mem_rdata[1] $abc$16053$new_n3180 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n3180 pcpi_rs1[1] $abc$16053$new_n2553 $0\reg_out[31:0][1] -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_rdinstr instr_rdcycleh count_instr[3] count_cycle[35] count_cycle[3] $abc$16053$new_n3182 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1610 instr_rdinstrh $abc$16053$new_n2571 count_instr[35] $abc$16053$new_n3182 $abc$16053$new_n3183 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2567 $abc$16053$new_n3183 pcpi_rs1[3] $0\reg_out[31:0][3] -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instr_rdinstr instr_rdcycleh count_instr[5] count_cycle[37] count_cycle[5] $abc$16053$new_n3185 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1610 instr_rdinstrh $abc$16053$new_n2585 count_instr[37] $abc$16053$new_n3185 $abc$16053$new_n3186 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n3189 $abc$16053$new_n2454 $abc$16053$new_n3186 $abc$16053$new_n2022 pcpi_rs1[5] $0\reg_out[31:0][5] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n1442 mem_rdata[5] $abc$16053$new_n2513 pcpi_rs1[1] mem_rdata[21] $abc$16053$new_n3188 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10011 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$16053$new_n2021 $abc$16053$new_n1442 $abc$16053$new_n3188 pcpi_rs1[0] $abc$16053$new_n2590 $abc$16053$new_n3189 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names instr_rdinstr instr_rdcycleh count_instr[8] count_cycle[40] count_cycle[8] $abc$16053$new_n3190 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2611 instr_rdinstrh $abc$16053$new_n2453 count_instr[40] $abc$16053$new_n3190 $abc$16053$new_n3191 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$16053$new_n1610 $abc$16053$new_n2617 reg_pc[8] decoded_imm[8] $abc$16053$new_n3191 $0\reg_out[31:0][8] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names instr_rdinstr instr_rdcycleh count_instr[20] count_cycle[52] count_cycle[20] $abc$16053$new_n3193 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2690 instr_rdinstrh $abc$16053$new_n2453 count_instr[52] $abc$16053$new_n3193 $abc$16053$new_n3194 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$16053$new_n1610 $abc$16053$new_n2688 reg_pc[20] decoded_imm[20] $abc$16053$new_n3194 $0\reg_out[31:0][20] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names instr_rdinstr instr_rdcycleh count_instr[30] count_cycle[62] count_cycle[30] $abc$16053$new_n3196 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$16053$new_n2752 instr_rdinstrh $abc$16053$new_n2453 count_instr[62] $abc$16053$new_n3196 $abc$16053$new_n3197 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$16053$new_n1610 $abc$16053$new_n2750 reg_pc[30] decoded_imm[30] $abc$16053$new_n3197 $0\reg_out[31:0][30] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$16053$new_n2038 $abc$16053$new_n1610 $abc$16053$new_n2022 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1549 $abc$16053$new_n3199 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$16053$new_n2789 $abc$16053$new_n2767 $abc$16053$new_n2394 $abc$16053$new_n2769 $abc$16053$new_n2771 $abc$16053$new_n3200 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -.names $abc$16053$new_n2773 $abc$16053$new_n3200 $abc$16053$new_n3199 $abc$16053$new_n2019 $abc$16053$procmux$2235_Y[6] -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names instr_sub pcpi_rs1[4] mem_la_wdata[4] $abc$16053$new_n2810 $abc$16053$new_n2809 $abc$16053$new_n3202 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n3202 instr_xor instr_xori $abc$16053$new_n3203 -100 1 -.names instr_sub pcpi_rs1[6] mem_la_wdata[6] $abc$16053$new_n2820 $abc$16053$new_n2819 $abc$16053$new_n3204 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n3204 instr_xor instr_xori $abc$16053$new_n3205 -100 1 -.names instr_sub pcpi_rs1[8] pcpi_rs2[8] $abc$16053$new_n2830 $abc$16053$new_n2829 $abc$16053$new_n3206 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n3206 instr_xor instr_xori $abc$16053$new_n3207 -100 1 -.names instr_sub pcpi_rs1[10] pcpi_rs2[10] $abc$16053$new_n2839 $abc$16053$new_n2838 $abc$16053$new_n3208 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n3208 instr_xor instr_xori $abc$16053$new_n3209 -100 1 -.names instr_sub pcpi_rs1[12] pcpi_rs2[12] $abc$16053$new_n2849 $abc$16053$new_n2848 $abc$16053$new_n3210 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n3210 instr_xor instr_xori $abc$16053$new_n3211 -100 1 -.names instr_sub pcpi_rs1[14] pcpi_rs2[14] $abc$16053$new_n2859 $abc$16053$new_n2858 $abc$16053$new_n3212 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n3212 instr_xor instr_xori $abc$16053$new_n3213 -100 1 -.names instr_sub pcpi_rs1[16] pcpi_rs2[16] $abc$16053$new_n2868 $abc$16053$new_n2867 $abc$16053$new_n3214 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n3214 instr_xor instr_xori $abc$16053$new_n3215 -100 1 -.names instr_sub pcpi_rs1[18] pcpi_rs2[18] $abc$16053$new_n2877 $abc$16053$new_n2876 $abc$16053$new_n3216 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$16053$new_n3216 instr_xor instr_xori $abc$16053$new_n3217 -100 1 -.names $abc$16053$new_n3091 latched_rd[4] $0\decoded_rs1[4:0][4] $0\decoded_rs1[4:0][0] latched_rd[0] $abc$16053$new_n3218 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$16053$new_n3218 $0\decoded_rs1[4:0][3] latched_rd[3] $0\decoded_rs1[4:0][1] latched_rd[1] $abc$16053$auto$rtlil.cc:2515:And$4922 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$16053$new_n3096 $0\decoded_rs2[4:0][4] latched_rd[4] $0\decoded_rs2[4:0][0] latched_rd[0] $abc$16053$new_n3220 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$16053$new_n3220 $0\decoded_rs2[4:0][3] latched_rd[3] $0\decoded_rs2[4:0][1] latched_rd[1] $abc$16053$auto$rtlil.cc:2515:And$4912 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.subckt dff C=clk D=cpuregs_wrdata[0] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] -.subckt dff C=clk D=cpuregs_wrdata[1] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] -.subckt dff C=clk D=cpuregs_wrdata[2] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] -.subckt dff C=clk D=cpuregs_wrdata[3] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] -.subckt dff C=clk D=cpuregs_wrdata[4] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] -.subckt dff C=clk D=cpuregs_wrdata[5] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] -.subckt dff C=clk D=cpuregs_wrdata[6] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] -.subckt dff C=clk D=cpuregs_wrdata[7] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] -.subckt dff C=clk D=cpuregs_wrdata[8] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] -.subckt dff C=clk D=cpuregs_wrdata[9] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] -.subckt dff C=clk D=cpuregs_wrdata[10] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] -.subckt dff C=clk D=cpuregs_wrdata[11] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] -.subckt dff C=clk D=cpuregs_wrdata[12] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] -.subckt dff C=clk D=cpuregs_wrdata[13] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] -.subckt dff C=clk D=cpuregs_wrdata[14] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] -.subckt dff C=clk D=cpuregs_wrdata[15] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] -.subckt dff C=clk D=cpuregs_wrdata[16] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] -.subckt dff C=clk D=cpuregs_wrdata[17] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] -.subckt dff C=clk D=cpuregs_wrdata[18] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] -.subckt dff C=clk D=cpuregs_wrdata[19] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] -.subckt dff C=clk D=cpuregs_wrdata[20] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] -.subckt dff C=clk D=cpuregs_wrdata[21] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] -.subckt dff C=clk D=cpuregs_wrdata[22] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] -.subckt dff C=clk D=cpuregs_wrdata[23] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] -.subckt dff C=clk D=cpuregs_wrdata[24] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] -.subckt dff C=clk D=cpuregs_wrdata[25] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] -.subckt dff C=clk D=cpuregs_wrdata[26] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] -.subckt dff C=clk D=cpuregs_wrdata[27] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] -.subckt dff C=clk D=cpuregs_wrdata[28] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] -.subckt dff C=clk D=cpuregs_wrdata[29] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] -.subckt dff C=clk D=cpuregs_wrdata[30] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] -.subckt dff C=clk D=cpuregs_wrdata[31] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2515:And$4922 Q=$abc$16053$auto$mem.cc:1172:emulate_transparency$4923 -.subckt sdffrn C=clk D=$abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y Q=decoder_pseudo_trigger RN=$abc$16053$auto$opt_dff.cc:253:combine_resets$4218 -.subckt sdffr C=clk D=$abc$16053$reduce_or$./benchmark/picorv32.v:863$175_Y Q=is_compare R=$abc$16053$auto$opt_dff.cc:253:combine_resets$4160 -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15039 Q=mem_addr[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15037 Q=mem_addr[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15035 Q=mem_addr[4] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15033 Q=mem_addr[5] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15031 Q=mem_addr[6] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15029 Q=mem_addr[7] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15027 Q=mem_addr[8] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15025 Q=mem_addr[9] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15023 Q=mem_addr[10] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15021 Q=mem_addr[11] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15019 Q=mem_addr[12] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15017 Q=mem_addr[13] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15015 Q=mem_addr[14] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15013 Q=mem_addr[15] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15011 Q=mem_addr[16] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15009 Q=mem_addr[17] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15007 Q=mem_addr[18] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15005 Q=mem_addr[19] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15003 Q=mem_addr[20] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15001 Q=mem_addr[21] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14999 Q=mem_addr[22] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14997 Q=mem_addr[23] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14995 Q=mem_addr[24] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14993 Q=mem_addr[25] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14991 Q=mem_addr[26] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14989 Q=mem_addr[27] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14987 Q=mem_addr[28] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14985 Q=mem_addr[29] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14983 Q=mem_addr[30] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15203 Q=mem_addr[31] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2515:And$4912 Q=$abc$16053$auto$mem.cc:1172:emulate_transparency$4913 -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14981 Q=pcpi_rs1[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14979 Q=pcpi_rs1[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14977 Q=pcpi_rs1[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14975 Q=pcpi_rs1[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14973 Q=pcpi_rs1[4] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14971 Q=pcpi_rs1[5] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14969 Q=pcpi_rs1[6] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14967 Q=pcpi_rs1[7] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14965 Q=pcpi_rs1[8] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14963 Q=pcpi_rs1[9] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14961 Q=pcpi_rs1[10] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14959 Q=pcpi_rs1[11] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14957 Q=pcpi_rs1[12] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14955 Q=pcpi_rs1[13] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14953 Q=pcpi_rs1[14] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14951 Q=pcpi_rs1[15] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14949 Q=pcpi_rs1[16] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14947 Q=pcpi_rs1[17] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14945 Q=pcpi_rs1[18] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14943 Q=pcpi_rs1[19] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14941 Q=pcpi_rs1[20] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14939 Q=pcpi_rs1[21] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14937 Q=pcpi_rs1[22] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14935 Q=pcpi_rs1[23] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14933 Q=pcpi_rs1[24] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14931 Q=pcpi_rs1[25] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14929 Q=pcpi_rs1[26] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14927 Q=pcpi_rs1[27] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14925 Q=pcpi_rs1[28] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14923 Q=pcpi_rs1[29] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15111 Q=pcpi_rs1[30] -.subckt dff C=clk D=mem_rdata_latched[0] Q=mem_rdata_q[0] -.subckt dff C=clk D=mem_rdata_latched[1] Q=mem_rdata_q[1] -.subckt dff C=clk D=mem_rdata_latched[2] Q=mem_rdata_q[2] -.subckt dff C=clk D=mem_rdata_latched[3] Q=mem_rdata_q[3] -.subckt dff C=clk D=mem_rdata_latched[4] Q=mem_rdata_q[4] -.subckt dff C=clk D=mem_rdata_latched[5] Q=mem_rdata_q[5] -.subckt dff C=clk D=mem_rdata_latched[6] Q=mem_rdata_q[6] -.subckt dff C=clk D=mem_rdata_latched[7] Q=mem_rdata_q[7] -.subckt dff C=clk D=mem_rdata_latched[8] Q=mem_rdata_q[8] -.subckt dff C=clk D=mem_rdata_latched[9] Q=mem_rdata_q[9] -.subckt dff C=clk D=mem_rdata_latched[10] Q=mem_rdata_q[10] -.subckt dff C=clk D=mem_rdata_latched[11] Q=mem_rdata_q[11] -.subckt dff C=clk D=mem_rdata_latched[12] Q=mem_rdata_q[12] -.subckt dff C=clk D=mem_rdata_latched[13] Q=mem_rdata_q[13] -.subckt dff C=clk D=mem_rdata_latched[14] Q=mem_rdata_q[14] -.subckt dff C=clk D=mem_rdata_latched[15] Q=mem_rdata_q[15] -.subckt dff C=clk D=mem_rdata_latched[16] Q=mem_rdata_q[16] -.subckt dff C=clk D=mem_rdata_latched[17] Q=mem_rdata_q[17] -.subckt dff C=clk D=mem_rdata_latched[18] Q=mem_rdata_q[18] -.subckt dff C=clk D=mem_rdata_latched[19] Q=mem_rdata_q[19] -.subckt dff C=clk D=mem_rdata_latched[20] Q=mem_rdata_q[20] -.subckt dff C=clk D=mem_rdata_latched[21] Q=mem_rdata_q[21] -.subckt dff C=clk D=mem_rdata_latched[22] Q=mem_rdata_q[22] -.subckt dff C=clk D=mem_rdata_latched[23] Q=mem_rdata_q[23] -.subckt dff C=clk D=mem_rdata_latched[24] Q=mem_rdata_q[24] -.subckt dff C=clk D=mem_rdata_latched[25] Q=mem_rdata_q[25] -.subckt dff C=clk D=mem_rdata_latched[26] Q=mem_rdata_q[26] -.subckt dff C=clk D=mem_rdata_latched[27] Q=mem_rdata_q[27] -.subckt dff C=clk D=mem_rdata_latched[28] Q=mem_rdata_q[28] -.subckt dff C=clk D=mem_rdata_latched[29] Q=mem_rdata_q[29] -.subckt dff C=clk D=mem_rdata_latched[30] Q=mem_rdata_q[30] -.subckt dff C=clk D=mem_rdata_latched[31] Q=mem_rdata_q[31] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15189 Q=mem_valid -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14859 Q=count_instr[0] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14857 Q=count_instr[1] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14855 Q=count_instr[2] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14853 Q=count_instr[3] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14851 Q=count_instr[4] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14849 Q=count_instr[5] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14847 Q=count_instr[6] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14845 Q=count_instr[7] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14843 Q=count_instr[8] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14841 Q=count_instr[9] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14839 Q=count_instr[10] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14837 Q=count_instr[11] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14835 Q=count_instr[12] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14833 Q=count_instr[13] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14831 Q=count_instr[14] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14829 Q=count_instr[15] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14827 Q=count_instr[16] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14825 Q=count_instr[17] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14823 Q=count_instr[18] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14821 Q=count_instr[19] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14819 Q=count_instr[20] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14817 Q=count_instr[21] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14815 Q=count_instr[22] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14813 Q=count_instr[23] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14811 Q=count_instr[24] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14809 Q=count_instr[25] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14807 Q=count_instr[26] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14805 Q=count_instr[27] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14803 Q=count_instr[28] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14801 Q=count_instr[29] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14799 Q=count_instr[30] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14797 Q=count_instr[31] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14795 Q=count_instr[32] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14793 Q=count_instr[33] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14791 Q=count_instr[34] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14789 Q=count_instr[35] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14787 Q=count_instr[36] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14785 Q=count_instr[37] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14783 Q=count_instr[38] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14781 Q=count_instr[39] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14779 Q=count_instr[40] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14777 Q=count_instr[41] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14775 Q=count_instr[42] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14773 Q=count_instr[43] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14771 Q=count_instr[44] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14769 Q=count_instr[45] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14767 Q=count_instr[46] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14765 Q=count_instr[47] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14763 Q=count_instr[48] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14761 Q=count_instr[49] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14759 Q=count_instr[50] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14757 Q=count_instr[51] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14755 Q=count_instr[52] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14753 Q=count_instr[53] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14751 Q=count_instr[54] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14749 Q=count_instr[55] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14747 Q=count_instr[56] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14745 Q=count_instr[57] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14743 Q=count_instr[58] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14741 Q=count_instr[59] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14739 Q=count_instr[60] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14737 Q=count_instr[61] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14735 Q=count_instr[62] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15113 Q=count_instr[63] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$procmux$1608_CMP Q=trap RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.X[0] Q=count_cycle[0] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[1] Q=count_cycle[1] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[2] Q=count_cycle[2] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[3] Q=count_cycle[3] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[4] Q=count_cycle[4] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[5] Q=count_cycle[5] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[6] Q=count_cycle[6] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[7] Q=count_cycle[7] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[8] Q=count_cycle[8] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[9] Q=count_cycle[9] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[10] Q=count_cycle[10] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[11] Q=count_cycle[11] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[12] Q=count_cycle[12] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[13] Q=count_cycle[13] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[14] Q=count_cycle[14] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[15] Q=count_cycle[15] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[16] Q=count_cycle[16] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[17] Q=count_cycle[17] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[18] Q=count_cycle[18] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[19] Q=count_cycle[19] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[20] Q=count_cycle[20] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[21] Q=count_cycle[21] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[22] Q=count_cycle[22] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[23] Q=count_cycle[23] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[24] Q=count_cycle[24] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[25] Q=count_cycle[25] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[26] Q=count_cycle[26] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[27] Q=count_cycle[27] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[28] Q=count_cycle[28] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[29] Q=count_cycle[29] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[30] Q=count_cycle[30] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[31] Q=count_cycle[31] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[32] Q=count_cycle[32] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[33] Q=count_cycle[33] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[34] Q=count_cycle[34] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[35] Q=count_cycle[35] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[36] Q=count_cycle[36] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[37] Q=count_cycle[37] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[38] Q=count_cycle[38] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[39] Q=count_cycle[39] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[40] Q=count_cycle[40] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[41] Q=count_cycle[41] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[42] Q=count_cycle[42] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[43] Q=count_cycle[43] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[44] Q=count_cycle[44] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[45] Q=count_cycle[45] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[46] Q=count_cycle[46] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[47] Q=count_cycle[47] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[48] Q=count_cycle[48] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[49] Q=count_cycle[49] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[50] Q=count_cycle[50] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[51] Q=count_cycle[51] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[52] Q=count_cycle[52] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[53] Q=count_cycle[53] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[54] Q=count_cycle[54] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[55] Q=count_cycle[55] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[56] Q=count_cycle[56] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[57] Q=count_cycle[57] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[58] Q=count_cycle[58] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[59] Q=count_cycle[59] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[60] Q=count_cycle[60] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[61] Q=count_cycle[61] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[62] Q=count_cycle[62] RN=resetn -.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[63] Q=count_cycle[63] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14733 Q=reg_pc[0] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14731 Q=reg_pc[1] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14729 Q=reg_pc[2] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14727 Q=reg_pc[3] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14725 Q=reg_pc[4] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14723 Q=reg_pc[5] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14721 Q=reg_pc[6] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14719 Q=reg_pc[7] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14717 Q=reg_pc[8] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14715 Q=reg_pc[9] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14713 Q=reg_pc[10] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14711 Q=reg_pc[11] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14709 Q=reg_pc[12] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14707 Q=reg_pc[13] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14705 Q=reg_pc[14] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14703 Q=reg_pc[15] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14701 Q=reg_pc[16] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14699 Q=reg_pc[17] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14697 Q=reg_pc[18] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14695 Q=reg_pc[19] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14693 Q=reg_pc[20] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14691 Q=reg_pc[21] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14689 Q=reg_pc[22] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14687 Q=reg_pc[23] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14685 Q=reg_pc[24] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14683 Q=reg_pc[25] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14681 Q=reg_pc[26] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14679 Q=reg_pc[27] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14677 Q=reg_pc[28] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14675 Q=reg_pc[29] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14673 Q=reg_pc[30] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15115 Q=reg_pc[31] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14671 Q=reg_next_pc[0] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14669 Q=reg_next_pc[1] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14667 Q=reg_next_pc[2] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14665 Q=reg_next_pc[3] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14663 Q=reg_next_pc[4] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14661 Q=reg_next_pc[5] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14659 Q=reg_next_pc[6] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14657 Q=reg_next_pc[7] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14655 Q=reg_next_pc[8] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14653 Q=reg_next_pc[9] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14651 Q=reg_next_pc[10] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14649 Q=reg_next_pc[11] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14647 Q=reg_next_pc[12] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14645 Q=reg_next_pc[13] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14643 Q=reg_next_pc[14] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14641 Q=reg_next_pc[15] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14639 Q=reg_next_pc[16] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14637 Q=reg_next_pc[17] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14635 Q=reg_next_pc[18] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14633 Q=reg_next_pc[19] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14631 Q=reg_next_pc[20] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14629 Q=reg_next_pc[21] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14627 Q=reg_next_pc[22] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14625 Q=reg_next_pc[23] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14623 Q=reg_next_pc[24] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14621 Q=reg_next_pc[25] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14619 Q=reg_next_pc[26] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14617 Q=reg_next_pc[27] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14615 Q=reg_next_pc[28] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14613 Q=reg_next_pc[29] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14611 Q=reg_next_pc[30] RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15117 Q=reg_next_pc[31] RN=resetn -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15109 Q=pcpi_rs1[31] -.subckt dff C=clk D=$0\reg_out[31:0][0] Q=reg_out[0] -.subckt dff C=clk D=$0\reg_out[31:0][1] Q=reg_out[1] -.subckt dff C=clk D=$0\reg_out[31:0][2] Q=reg_out[2] -.subckt dff C=clk D=$0\reg_out[31:0][3] Q=reg_out[3] -.subckt dff C=clk D=$0\reg_out[31:0][4] Q=reg_out[4] -.subckt dff C=clk D=$0\reg_out[31:0][5] Q=reg_out[5] -.subckt dff C=clk D=$0\reg_out[31:0][6] Q=reg_out[6] -.subckt dff C=clk D=$0\reg_out[31:0][7] Q=reg_out[7] -.subckt dff C=clk D=$0\reg_out[31:0][8] Q=reg_out[8] -.subckt dff C=clk D=$0\reg_out[31:0][9] Q=reg_out[9] -.subckt dff C=clk D=$0\reg_out[31:0][10] Q=reg_out[10] -.subckt dff C=clk D=$0\reg_out[31:0][11] Q=reg_out[11] -.subckt dff C=clk D=$0\reg_out[31:0][12] Q=reg_out[12] -.subckt dff C=clk D=$0\reg_out[31:0][13] Q=reg_out[13] -.subckt dff C=clk D=$0\reg_out[31:0][14] Q=reg_out[14] -.subckt dff C=clk D=$0\reg_out[31:0][15] Q=reg_out[15] -.subckt dff C=clk D=$0\reg_out[31:0][16] Q=reg_out[16] -.subckt dff C=clk D=$0\reg_out[31:0][17] Q=reg_out[17] -.subckt dff C=clk D=$0\reg_out[31:0][18] Q=reg_out[18] -.subckt dff C=clk D=$0\reg_out[31:0][19] Q=reg_out[19] -.subckt dff C=clk D=$0\reg_out[31:0][20] Q=reg_out[20] -.subckt dff C=clk D=$0\reg_out[31:0][21] Q=reg_out[21] -.subckt dff C=clk D=$0\reg_out[31:0][22] Q=reg_out[22] -.subckt dff C=clk D=$0\reg_out[31:0][23] Q=reg_out[23] -.subckt dff C=clk D=$0\reg_out[31:0][24] Q=reg_out[24] -.subckt dff C=clk D=$0\reg_out[31:0][25] Q=reg_out[25] -.subckt dff C=clk D=$0\reg_out[31:0][26] Q=reg_out[26] -.subckt dff C=clk D=$0\reg_out[31:0][27] Q=reg_out[27] -.subckt dff C=clk D=$0\reg_out[31:0][28] Q=reg_out[28] -.subckt dff C=clk D=$0\reg_out[31:0][29] Q=reg_out[29] -.subckt dff C=clk D=$0\reg_out[31:0][30] Q=reg_out[30] -.subckt dff C=clk D=$0\reg_out[31:0][31] Q=reg_out[31] -.subckt dff C=clk D=$0\reg_sh[4:0][0] Q=reg_sh[0] -.subckt dff C=clk D=$0\reg_sh[4:0][1] Q=reg_sh[1] -.subckt dff C=clk D=$0\reg_sh[4:0][2] Q=reg_sh[2] -.subckt dff C=clk D=$0\reg_sh[4:0][3] Q=reg_sh[3] -.subckt dff C=clk D=$0\reg_sh[4:0][4] Q=reg_sh[4] -.subckt sdffr C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15119 Q=mem_do_prefetch R=$abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14609 Q=mem_la_wdata[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14607 Q=mem_la_wdata[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14605 Q=mem_la_wdata[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14603 Q=mem_la_wdata[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14601 Q=mem_la_wdata[4] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14599 Q=mem_la_wdata[5] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14597 Q=mem_la_wdata[6] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14595 Q=mem_la_wdata[7] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14593 Q=pcpi_rs2[8] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14591 Q=pcpi_rs2[9] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14589 Q=pcpi_rs2[10] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14587 Q=pcpi_rs2[11] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14585 Q=pcpi_rs2[12] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14583 Q=pcpi_rs2[13] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14581 Q=pcpi_rs2[14] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14579 Q=pcpi_rs2[15] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14577 Q=pcpi_rs2[16] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14575 Q=pcpi_rs2[17] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14573 Q=pcpi_rs2[18] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14571 Q=pcpi_rs2[19] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14569 Q=pcpi_rs2[20] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14567 Q=pcpi_rs2[21] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14565 Q=pcpi_rs2[22] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14563 Q=pcpi_rs2[23] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14561 Q=pcpi_rs2[24] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14559 Q=pcpi_rs2[25] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14557 Q=pcpi_rs2[26] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14555 Q=pcpi_rs2[27] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14553 Q=pcpi_rs2[28] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14551 Q=pcpi_rs2[29] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14549 Q=pcpi_rs2[30] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15107 Q=pcpi_rs2[31] -.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15121 Q=mem_do_rinst S=$0\set_mem_do_rinst[0:0] -.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15123 Q=mem_do_rdata S=$0\set_mem_do_rdata[0:0] -.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15125 Q=mem_do_wdata S=$0\set_mem_do_wdata[0:0] -.subckt dff C=clk D=$0\decoder_trigger[0:0] Q=decoder_trigger -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15127 Q=latched_store RN=resetn -.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[0] Q=cpu_state[0] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[1] Q=cpu_state[1] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[2] Q=cpu_state[2] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[3] Q=cpu_state[3] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[4] Q=cpu_state[4] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[5] Q=cpu_state[5] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[6] Q=cpu_state[6] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -.subckt sdffs C=clk D=$abc$16053$procmux$2235_Y[7] Q=cpu_state[7] S=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15129 Q=latched_stalu RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15131 Q=latched_branch RN=resetn -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14547 Q=latched_rd[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14543 Q=latched_rd[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14539 Q=latched_rd[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14535 Q=latched_rd[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15201 Q=latched_rd[4] -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15133 Q=latched_is_lh RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15135 Q=latched_is_lb RN=resetn -.subckt dff C=clk D=alu_out[0] Q=alu_out_q[0] -.subckt dff C=clk D=alu_out[1] Q=alu_out_q[1] -.subckt dff C=clk D=alu_out[2] Q=alu_out_q[2] -.subckt dff C=clk D=alu_out[3] Q=alu_out_q[3] -.subckt dff C=clk D=alu_out[4] Q=alu_out_q[4] -.subckt dff C=clk D=alu_out[5] Q=alu_out_q[5] -.subckt dff C=clk D=alu_out[6] Q=alu_out_q[6] -.subckt dff C=clk D=alu_out[7] Q=alu_out_q[7] -.subckt dff C=clk D=alu_out[8] Q=alu_out_q[8] -.subckt dff C=clk D=alu_out[9] Q=alu_out_q[9] -.subckt dff C=clk D=alu_out[10] Q=alu_out_q[10] -.subckt dff C=clk D=alu_out[11] Q=alu_out_q[11] -.subckt dff C=clk D=alu_out[12] Q=alu_out_q[12] -.subckt dff C=clk D=alu_out[13] Q=alu_out_q[13] -.subckt dff C=clk D=alu_out[14] Q=alu_out_q[14] -.subckt dff C=clk D=alu_out[15] Q=alu_out_q[15] -.subckt dff C=clk D=alu_out[16] Q=alu_out_q[16] -.subckt dff C=clk D=alu_out[17] Q=alu_out_q[17] -.subckt dff C=clk D=alu_out[18] Q=alu_out_q[18] -.subckt dff C=clk D=alu_out[19] Q=alu_out_q[19] -.subckt dff C=clk D=alu_out[20] Q=alu_out_q[20] -.subckt dff C=clk D=alu_out[21] Q=alu_out_q[21] -.subckt dff C=clk D=alu_out[22] Q=alu_out_q[22] -.subckt dff C=clk D=alu_out[23] Q=alu_out_q[23] -.subckt dff C=clk D=alu_out[24] Q=alu_out_q[24] -.subckt dff C=clk D=alu_out[25] Q=alu_out_q[25] -.subckt dff C=clk D=alu_out[26] Q=alu_out_q[26] -.subckt dff C=clk D=alu_out[27] Q=alu_out_q[27] -.subckt dff C=clk D=alu_out[28] Q=alu_out_q[28] -.subckt dff C=clk D=alu_out[29] Q=alu_out_q[29] -.subckt dff C=clk D=alu_out[30] Q=alu_out_q[30] -.subckt dff C=clk D=alu_out[31] Q=alu_out_q[31] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15105 Q=instr_lui -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15103 Q=instr_auipc -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15101 Q=instr_jal -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15137 Q=instr_beq RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15139 Q=instr_bne RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15141 Q=instr_blt RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15143 Q=instr_bge RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15145 Q=instr_bltu RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15147 Q=instr_bgeu RN=resetn -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15099 Q=instr_jalr -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15097 Q=instr_lb -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15095 Q=instr_lh -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15093 Q=instr_lw -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15091 Q=instr_lbu -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15089 Q=instr_lhu -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15087 Q=instr_sb -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15085 Q=instr_sh -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15149 Q=instr_addi RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15151 Q=instr_slti RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15153 Q=instr_sltiu RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15155 Q=instr_xori RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15157 Q=instr_ori RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15159 Q=instr_andi RN=resetn -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15083 Q=instr_sw -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15081 Q=instr_slli -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15079 Q=instr_srli -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15161 Q=instr_add RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15163 Q=instr_sub RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15165 Q=instr_sll RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15167 Q=instr_slt RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15169 Q=instr_sltu RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15171 Q=instr_xor RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15173 Q=instr_srl RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15175 Q=instr_sra RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15177 Q=instr_or RN=resetn -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15179 Q=instr_and RN=resetn -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15077 Q=instr_srai -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15075 Q=instr_rdcycle -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15073 Q=instr_rdcycleh -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15071 Q=instr_rdinstr -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15181 Q=instr_fence RN=resetn -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15069 Q=instr_rdinstrh -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14531 Q=decoded_imm_j[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14529 Q=decoded_imm_j[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14527 Q=decoded_imm_j[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14525 Q=decoded_imm_j[4] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14523 Q=decoded_imm_j[5] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14521 Q=decoded_imm_j[6] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14519 Q=decoded_imm_j[7] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14517 Q=decoded_imm_j[8] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14515 Q=decoded_imm_j[9] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14513 Q=decoded_imm_j[10] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14511 Q=decoded_imm_j[11] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14509 Q=decoded_imm_j[12] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14507 Q=decoded_imm_j[13] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14505 Q=decoded_imm_j[14] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14503 Q=decoded_imm_j[15] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14501 Q=decoded_imm_j[16] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14499 Q=decoded_imm_j[17] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14497 Q=decoded_imm_j[18] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14495 Q=decoded_imm_j[19] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14493 Q=decoded_imm_j[20] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14491 Q=decoded_imm_j[21] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14489 Q=decoded_imm_j[22] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14487 Q=decoded_imm_j[23] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14485 Q=decoded_imm_j[24] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14483 Q=decoded_imm_j[25] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14481 Q=decoded_imm_j[26] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14479 Q=decoded_imm_j[27] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14477 Q=decoded_imm_j[28] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14475 Q=decoded_imm_j[29] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14473 Q=decoded_imm_j[30] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15185 Q=decoded_imm_j[31] -.subckt dff C=clk D=$0\decoded_rs1[4:0][0] Q=decoded_rs1[0] -.subckt dff C=clk D=$0\decoded_rs1[4:0][1] Q=decoded_rs1[1] -.subckt dff C=clk D=$0\decoded_rs1[4:0][2] Q=decoded_rs1[2] -.subckt dff C=clk D=$0\decoded_rs1[4:0][3] Q=decoded_rs1[3] -.subckt dff C=clk D=$0\decoded_rs1[4:0][4] Q=decoded_rs1[4] -.subckt dff C=clk D=$0\decoded_rs2[4:0][0] Q=decoded_rs2[0] -.subckt dff C=clk D=$0\decoded_rs2[4:0][1] Q=decoded_rs2[1] -.subckt dff C=clk D=$0\decoded_rs2[4:0][2] Q=decoded_rs2[2] -.subckt dff C=clk D=$0\decoded_rs2[4:0][3] Q=decoded_rs2[3] -.subckt dff C=clk D=$0\decoded_rs2[4:0][4] Q=decoded_rs2[4] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14471 Q=decoded_rd[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14469 Q=decoded_rd[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14467 Q=decoded_rd[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14465 Q=decoded_rd[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15067 Q=decoded_rd[4] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14463 Q=decoded_imm[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14461 Q=decoded_imm[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14459 Q=decoded_imm[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14457 Q=decoded_imm[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14455 Q=decoded_imm[4] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14453 Q=decoded_imm[5] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14451 Q=decoded_imm[6] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14449 Q=decoded_imm[7] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14447 Q=decoded_imm[8] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14445 Q=decoded_imm[9] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14443 Q=decoded_imm[10] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14441 Q=decoded_imm[11] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14439 Q=decoded_imm[12] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14437 Q=decoded_imm[13] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14435 Q=decoded_imm[14] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14433 Q=decoded_imm[15] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14431 Q=decoded_imm[16] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14429 Q=decoded_imm[17] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14427 Q=decoded_imm[18] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14425 Q=decoded_imm[19] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14423 Q=decoded_imm[20] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14421 Q=decoded_imm[21] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14419 Q=decoded_imm[22] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14417 Q=decoded_imm[23] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14415 Q=decoded_imm[24] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14413 Q=decoded_imm[25] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14411 Q=decoded_imm[26] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14409 Q=decoded_imm[27] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14407 Q=decoded_imm[28] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14405 Q=decoded_imm[29] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14403 Q=decoded_imm[30] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15065 Q=decoded_imm[31] -.subckt dff C=clk D=$0\is_lui_auipc_jal[0:0] Q=is_lui_auipc_jal -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15063 Q=is_lb_lh_lw_lbu_lhu -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15061 Q=is_slli_srli_srai -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15059 Q=is_jalr_addi_slti_sltiu_xori_ori_andi -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15057 Q=is_sb_sh_sw -.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15183 Q=is_beq_bne_blt_bge_bltu_bgeu RN=resetn -.subckt dff C=clk D=$0\is_slti_blt_slt[0:0] Q=is_slti_blt_slt -.subckt dff C=clk D=$0\is_sltiu_bltu_sltu[0:0] Q=is_sltiu_bltu_sltu -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15055 Q=is_sll_srl_sra -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15053 Q=is_alu_reg_imm -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15051 Q=is_alu_reg_reg -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15049 Q=mem_instr -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14401 Q=mem_state[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15193 Q=mem_state[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14397 Q=mem_wdata[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14395 Q=mem_wdata[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14393 Q=mem_wdata[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14391 Q=mem_wdata[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14389 Q=mem_wdata[4] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14387 Q=mem_wdata[5] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14385 Q=mem_wdata[6] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14383 Q=mem_wdata[7] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14381 Q=mem_wdata[8] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14379 Q=mem_wdata[9] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14377 Q=mem_wdata[10] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14375 Q=mem_wdata[11] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14373 Q=mem_wdata[12] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14371 Q=mem_wdata[13] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14369 Q=mem_wdata[14] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14367 Q=mem_wdata[15] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14365 Q=mem_wdata[16] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14363 Q=mem_wdata[17] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14361 Q=mem_wdata[18] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14359 Q=mem_wdata[19] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14357 Q=mem_wdata[20] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14355 Q=mem_wdata[21] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14353 Q=mem_wdata[22] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14351 Q=mem_wdata[23] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14349 Q=mem_wdata[24] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14347 Q=mem_wdata[25] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14345 Q=mem_wdata[26] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14343 Q=mem_wdata[27] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14341 Q=mem_wdata[28] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14339 Q=mem_wdata[29] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14337 Q=mem_wdata[30] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15045 Q=mem_wdata[31] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14335 Q=mem_wstrb[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14333 Q=mem_wstrb[1] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14331 Q=mem_wstrb[2] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15043 Q=mem_wstrb[3] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15207 Q=mem_wordsize[0] -.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15197 Q=mem_wordsize[1] -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=cpuregs_wrdata[0] data_i[34]=cpuregs_wrdata[1] data_i[33]=cpuregs_wrdata[2] data_i[32]=cpuregs_wrdata[3] data_i[31]=cpuregs_wrdata[4] data_i[30]=cpuregs_wrdata[5] data_i[29]=cpuregs_wrdata[6] data_i[28]=cpuregs_wrdata[7] data_i[27]=cpuregs_wrdata[8] data_i[26]=cpuregs_wrdata[9] data_i[25]=cpuregs_wrdata[10] data_i[24]=cpuregs_wrdata[11] data_i[23]=cpuregs_wrdata[12] data_i[22]=cpuregs_wrdata[13] data_i[21]=cpuregs_wrdata[14] data_i[20]=cpuregs_wrdata[15] data_i[19]=cpuregs_wrdata[16] data_i[18]=cpuregs_wrdata[17] data_i[17]=cpuregs_wrdata[18] data_i[16]=cpuregs_wrdata[19] data_i[15]=cpuregs_wrdata[20] data_i[14]=cpuregs_wrdata[21] data_i[13]=cpuregs_wrdata[22] data_i[12]=cpuregs_wrdata[23] data_i[11]=cpuregs_wrdata[24] data_i[10]=cpuregs_wrdata[25] data_i[9]=cpuregs_wrdata[26] data_i[8]=cpuregs_wrdata[27] data_i[7]=cpuregs_wrdata[28] data_i[6]=cpuregs_wrdata[29] data_i[5]=cpuregs_wrdata[30] data_i[4]=cpuregs_wrdata[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[0] q_o[34]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[1] q_o[33]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[2] q_o[32]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[3] q_o[31]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[4] q_o[30]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[5] q_o[29]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[6] q_o[28]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[7] q_o[27]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[8] q_o[26]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[9] q_o[25]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[10] q_o[24]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[11] q_o[23]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[12] q_o[22]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[13] q_o[21]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[14] q_o[20]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[15] q_o[19]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[16] q_o[18]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[17] q_o[17]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[18] q_o[16]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[19] q_o[15]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[20] q_o[14]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[21] q_o[13]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[22] q_o[12]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[23] q_o[11]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[24] q_o[10]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[25] q_o[9]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[26] q_o[8]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[27] q_o[7]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[28] q_o[6]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[29] q_o[5]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[30] q_o[4]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4926[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4926[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4926[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4926[35] raddr_i[7]=$0\decoded_rs2[4:0][0] raddr_i[6]=$0\decoded_rs2[4:0][1] raddr_i[5]=$0\decoded_rs2[4:0][2] raddr_i[4]=$0\decoded_rs2[4:0][3] raddr_i[3]=$0\decoded_rs2[4:0][4] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=latched_rd[0] waddr_i[6]=latched_rd[1] waddr_i[5]=latched_rd[2] waddr_i[4]=latched_rd[3] waddr_i[3]=latched_rd[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=$0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] -.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=cpuregs_wrdata[0] data_i[34]=cpuregs_wrdata[1] data_i[33]=cpuregs_wrdata[2] data_i[32]=cpuregs_wrdata[3] data_i[31]=cpuregs_wrdata[4] data_i[30]=cpuregs_wrdata[5] data_i[29]=cpuregs_wrdata[6] data_i[28]=cpuregs_wrdata[7] data_i[27]=cpuregs_wrdata[8] data_i[26]=cpuregs_wrdata[9] data_i[25]=cpuregs_wrdata[10] data_i[24]=cpuregs_wrdata[11] data_i[23]=cpuregs_wrdata[12] data_i[22]=cpuregs_wrdata[13] data_i[21]=cpuregs_wrdata[14] data_i[20]=cpuregs_wrdata[15] data_i[19]=cpuregs_wrdata[16] data_i[18]=cpuregs_wrdata[17] data_i[17]=cpuregs_wrdata[18] data_i[16]=cpuregs_wrdata[19] data_i[15]=cpuregs_wrdata[20] data_i[14]=cpuregs_wrdata[21] data_i[13]=cpuregs_wrdata[22] data_i[12]=cpuregs_wrdata[23] data_i[11]=cpuregs_wrdata[24] data_i[10]=cpuregs_wrdata[25] data_i[9]=cpuregs_wrdata[26] data_i[8]=cpuregs_wrdata[27] data_i[7]=cpuregs_wrdata[28] data_i[6]=cpuregs_wrdata[29] data_i[5]=cpuregs_wrdata[30] data_i[4]=cpuregs_wrdata[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[0] q_o[34]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[1] q_o[33]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[2] q_o[32]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[3] q_o[31]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[4] q_o[30]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[5] q_o[29]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[6] q_o[28]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[7] q_o[27]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[8] q_o[26]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[9] q_o[25]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[10] q_o[24]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[11] q_o[23]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[12] q_o[22]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[13] q_o[21]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[14] q_o[20]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[15] q_o[19]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[16] q_o[18]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[17] q_o[17]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[18] q_o[16]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[19] q_o[15]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[20] q_o[14]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[21] q_o[13]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[22] q_o[12]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[23] q_o[11]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[24] q_o[10]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[25] q_o[9]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[26] q_o[8]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[27] q_o[7]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[28] q_o[6]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[29] q_o[5]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[30] q_o[4]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4927[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4927[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4927[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4927[35] raddr_i[7]=$0\decoded_rs1[4:0][0] raddr_i[6]=$0\decoded_rs1[4:0][1] raddr_i[5]=$0\decoded_rs1[4:0][2] raddr_i[4]=$0\decoded_rs1[4:0][3] raddr_i[3]=$0\decoded_rs1[4:0][4] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=latched_rd[0] waddr_i[6]=latched_rd[1] waddr_i[5]=latched_rd[2] waddr_i[4]=latched_rd[3] waddr_i[3]=latched_rd[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=$0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[0] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[1] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[2] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[3] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[4] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[5] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[6] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[7] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[8] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[9] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[10] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[11] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[12] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[13] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[14] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[15] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[16] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[17] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[18] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[19] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[20] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[21] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[22] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[23] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[24] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[25] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[26] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[27] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[28] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[29] -1 1 -.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[30] -1 1 -.names count_cycle[1] $auto$alumacc.cc:485:replace_alu$4638.X[1] -1 1 -.names count_cycle[2] $auto$alumacc.cc:485:replace_alu$4638.X[2] -1 1 -.names count_cycle[3] $auto$alumacc.cc:485:replace_alu$4638.X[3] -1 1 -.names count_cycle[4] $auto$alumacc.cc:485:replace_alu$4638.X[4] -1 1 -.names count_cycle[5] $auto$alumacc.cc:485:replace_alu$4638.X[5] -1 1 -.names count_cycle[6] $auto$alumacc.cc:485:replace_alu$4638.X[6] -1 1 -.names count_cycle[7] $auto$alumacc.cc:485:replace_alu$4638.X[7] -1 1 -.names count_cycle[8] $auto$alumacc.cc:485:replace_alu$4638.X[8] -1 1 -.names count_cycle[9] $auto$alumacc.cc:485:replace_alu$4638.X[9] -1 1 -.names count_cycle[10] $auto$alumacc.cc:485:replace_alu$4638.X[10] -1 1 -.names count_cycle[11] $auto$alumacc.cc:485:replace_alu$4638.X[11] -1 1 -.names count_cycle[12] $auto$alumacc.cc:485:replace_alu$4638.X[12] -1 1 -.names count_cycle[13] $auto$alumacc.cc:485:replace_alu$4638.X[13] -1 1 -.names count_cycle[14] $auto$alumacc.cc:485:replace_alu$4638.X[14] -1 1 -.names count_cycle[15] $auto$alumacc.cc:485:replace_alu$4638.X[15] -1 1 -.names count_cycle[16] $auto$alumacc.cc:485:replace_alu$4638.X[16] -1 1 -.names count_cycle[17] $auto$alumacc.cc:485:replace_alu$4638.X[17] -1 1 -.names count_cycle[18] $auto$alumacc.cc:485:replace_alu$4638.X[18] -1 1 -.names count_cycle[19] $auto$alumacc.cc:485:replace_alu$4638.X[19] -1 1 -.names count_cycle[20] $auto$alumacc.cc:485:replace_alu$4638.X[20] -1 1 -.names count_cycle[21] $auto$alumacc.cc:485:replace_alu$4638.X[21] -1 1 -.names count_cycle[22] $auto$alumacc.cc:485:replace_alu$4638.X[22] -1 1 -.names count_cycle[23] $auto$alumacc.cc:485:replace_alu$4638.X[23] -1 1 -.names count_cycle[24] $auto$alumacc.cc:485:replace_alu$4638.X[24] -1 1 -.names count_cycle[25] $auto$alumacc.cc:485:replace_alu$4638.X[25] -1 1 -.names count_cycle[26] $auto$alumacc.cc:485:replace_alu$4638.X[26] -1 1 -.names count_cycle[27] $auto$alumacc.cc:485:replace_alu$4638.X[27] -1 1 -.names count_cycle[28] $auto$alumacc.cc:485:replace_alu$4638.X[28] -1 1 -.names count_cycle[29] $auto$alumacc.cc:485:replace_alu$4638.X[29] -1 1 -.names count_cycle[30] $auto$alumacc.cc:485:replace_alu$4638.X[30] -1 1 -.names count_cycle[31] $auto$alumacc.cc:485:replace_alu$4638.X[31] -1 1 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$auto$alumacc.cc:485:replace_alu$4638.X[45] -1 1 -.names count_cycle[46] $auto$alumacc.cc:485:replace_alu$4638.X[46] -1 1 -.names count_cycle[47] $auto$alumacc.cc:485:replace_alu$4638.X[47] -1 1 -.names count_cycle[48] $auto$alumacc.cc:485:replace_alu$4638.X[48] -1 1 -.names count_cycle[49] $auto$alumacc.cc:485:replace_alu$4638.X[49] -1 1 -.names count_cycle[50] $auto$alumacc.cc:485:replace_alu$4638.X[50] -1 1 -.names count_cycle[51] $auto$alumacc.cc:485:replace_alu$4638.X[51] -1 1 -.names count_cycle[52] $auto$alumacc.cc:485:replace_alu$4638.X[52] -1 1 -.names count_cycle[53] $auto$alumacc.cc:485:replace_alu$4638.X[53] -1 1 -.names count_cycle[54] $auto$alumacc.cc:485:replace_alu$4638.X[54] -1 1 -.names count_cycle[55] $auto$alumacc.cc:485:replace_alu$4638.X[55] -1 1 -.names count_cycle[56] $auto$alumacc.cc:485:replace_alu$4638.X[56] -1 1 -.names count_cycle[57] $auto$alumacc.cc:485:replace_alu$4638.X[57] -1 1 -.names count_cycle[58] $auto$alumacc.cc:485:replace_alu$4638.X[58] -1 1 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-.names $abc$3008$new_n255 CounterY[5] ballY[5] ballY[3] $abc$3008$new_n272 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -.names $abc$3008$new_n235 CounterX[3] ballX[3] $abc$3008$new_n274 -100 1 -111 1 -.names ballX[9] CounterX[9] ballX[8] CounterX[8] $abc$3008$new_n278 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names CounterX[4] CounterX[5] ballX[4] ballX[5] $abc$3008$new_n279 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0111 1 -1001 1 -1010 1 -1011 1 -1100 1 -1110 1 -1111 1 -.names $abc$3008$new_n234 CounterX[9] ballX[9] CounterX[8] ballX[8] $abc$3008$new_n280 -10000 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11111 1 -.names CollisionX1 $abc$3008$new_n324 $abc$3008$new_n283 $abc$3008$auto$rtlil.cc:2693:MuxGate$2749 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$3008$new_n284 $abc$3008$new_n274 $abc$3008$new_n238 CounterX[9] ballX[9] $abc$3008$new_n283 -11100 1 -11111 1 -.names $abc$3008$new_n285 $abc$3008$new_n240 CounterX[5] ballX[5] $abc$3008$new_n284 -1100 1 -1111 1 -.names ballX[6] CounterX[6] CounterX[8] ballX[8] $abc$3008$new_n285 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$3008$new_n287 $abc$3008$new_n203 $abc$3008$eq$./benchmark/pong.v:56$43_Y -11 1 -.names CounterY[8] CounterY[2] CounterY[0] CounterY[1] CounterY[3] $abc$3008$new_n287 -11000 1 -.names CounterX[7] CounterX[6] CounterX[4] $abc$3008$new_n162 CounterX[5] $abc$3008$flatten\syncgen.$0\vga_HS[0:0] -11110 1 -.names inDisplayArea CounterX[7] $abc$3008$new_n162 $abc$3008$new_n160 $abc$3008$new_n290 $abc$3008$flatten\syncgen.$0\inDisplayArea[0:0] -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names CounterY[8] CounterY[5] CounterY[6] CounterY[7] $abc$3008$new_n290 -1111 1 -.names ball_inY $abc$3008$new_n250 $abc$3008$new_n262 $0\ball_inY[0:0] -001 1 -011 1 -100 1 -101 1 -.names ball_inX $abc$3008$new_n326 ball_inY $abc$3008$new_n283 $0\ball_inX[0:0] -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$3008$new_n294 $abc$3008$eq$./benchmark/pong.v:56$43_Y $0\ResetCollision[0:0] -11 1 -.names $abc$3008$new_n246 $abc$3008$new_n295 CounterX[1] CounterX[0] CounterX[2] $abc$3008$new_n294 -11000 1 -.names CounterX[6] CounterX[4] CounterX[5] CounterX[3] CounterX[9] $abc$3008$new_n295 -00000 1 -.names inDisplayArea $abc$3008$new_n297 $abc$3008$new_n298 ball_inX ball_inY $0\vga_R[0:0] -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$3008$new_n315 $abc$3008$new_n228 $abc$3008$new_n206 $abc$3008$new_n220 $abc$3008$new_n297 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names CounterX[3] CounterY[3] $abc$3008$new_n298 -00 1 -11 1 -.names inDisplayArea $abc$3008$new_n297 ball_inX ball_inY $0\vga_B[0:0] -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names CounterX[1] CounterX[0] $auto$alumacc.cc:485:replace_alu$666.Y[1] -01 1 -10 1 -.names CounterX[2] CounterX[1] CounterX[0] $auto$alumacc.cc:485:replace_alu$666.Y[2] -011 1 -100 1 -101 1 -110 1 -.names CounterX[3] CounterX[1] CounterX[0] CounterX[2] $auto$alumacc.cc:485:replace_alu$666.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names CounterX[4] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[4] -01 1 -10 1 -.names CounterX[5] CounterX[4] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[5] -011 1 -100 1 -101 1 -110 1 -.names CounterX[6] CounterX[4] CounterX[5] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[6] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[7] -01 1 -10 1 -.names CounterX[8] CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[8] -011 1 -100 1 -101 1 -110 1 -.names CounterX[9] CounterX[8] CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[9] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names CounterX[0] $auto$alumacc.cc:485:replace_alu$666.X[0] -0 1 -.names syncgen.vga_VS vga_v_sync -0 1 -.names syncgen.vga_HS vga_h_sync -0 1 -.names $abc$3008$new_n133 ball_dirY ballY[5] ballY[6] ballY[7] $abc$3008$new_n312 -10111 1 -11000 1 -.names ballY[8] $abc$3008$new_n131 $abc$3008$new_n312 ballY[4] ballY[7] $abc$3008$auto$rtlil.cc:2693:MuxGate$2737 -00100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -.names CounterY[8] CounterY[3] CounterY[4] CounterY[6] CounterY[7] $abc$3008$new_n314 -00000 1 -11111 1 -.names $abc$3008$new_n314 CounterY[5] $abc$3008$new_n246 $abc$3008$new_n247 $abc$3008$new_n315 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names ballY[3] CounterY[3] CounterY[8] ballY[8] $abc$3008$new_n256 $abc$3008$new_n316 -01000 1 -01001 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10101 1 -10110 1 -.names $abc$3008$new_n240 CounterX[6] ballX[6] ballX[4] ballX[5] $abc$3008$new_n319 -00111 1 -10000 1 -10001 1 -10010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names ballY[3] $abc$3008$new_n260 $abc$3008$new_n257 $abc$3008$new_n271 $abc$3008$new_n259 $abc$3008$new_n322 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$3008$new_n316 $abc$3008$new_n322 $abc$3008$new_n253 $abc$3008$new_n272 $abc$3008$new_n323 -1110 1 -.names $abc$3008$new_n323 $abc$3008$new_n315 $abc$3008$new_n228 $abc$3008$new_n220 $abc$3008$new_n206 $abc$3008$new_n324 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -.names CounterX[8] $abc$3008$new_n234 CounterX[9] ballX[9] ballX[8] $abc$3008$new_n325 -00000 1 -00110 1 -01101 1 -10001 1 -10111 1 -11000 1 -11110 1 -.names $abc$3008$new_n319 $abc$3008$new_n325 $abc$3008$new_n274 $abc$3008$new_n279 $abc$3008$new_n326 -1110 1 -.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2743 Q=CollisionY2 R=ResetCollision -.subckt dff C=clk D=$abc$3008$eq$./benchmark/pong.v:56$43_Y Q=syncgen.vga_VS -.subckt dff C=clk D=$abc$3008$flatten\syncgen.$0\vga_HS[0:0] Q=syncgen.vga_HS -.subckt dff C=clk D=$abc$3008$flatten\syncgen.$0\inDisplayArea[0:0] Q=inDisplayArea -.subckt dff C=clk D=$0\vga_R[0:0] Q=vga_R -.subckt dff C=clk D=$0\vga_B[0:0] Q=vga_B -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2709 Q=CounterY[0] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2707 Q=CounterY[1] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2705 Q=CounterY[2] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2703 Q=CounterY[3] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2701 Q=CounterY[4] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2699 Q=CounterY[5] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2697 Q=CounterY[6] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2695 Q=CounterY[7] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2741 Q=CounterY[8] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2693 Q=ballX[0] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2691 Q=ballX[1] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2689 Q=ballX[2] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2687 Q=ballX[3] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2685 Q=ballX[4] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2683 Q=ballX[5] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2681 Q=ballX[6] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2679 Q=ballX[7] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2677 Q=ballX[8] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2739 Q=ballX[9] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2735 Q=ball_dirX -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2731 Q=ball_dirY -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.X[0] Q=CounterX[0] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[1] Q=CounterX[1] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[2] Q=CounterX[2] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[3] Q=CounterX[3] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[4] Q=CounterX[4] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[5] Q=CounterX[5] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[6] Q=CounterX[6] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[7] Q=CounterX[7] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[8] Q=CounterX[8] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[9] Q=CounterX[9] R=syncgen.CounterXmaxed -.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2745 Q=CollisionY1 R=ResetCollision -.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2747 Q=CollisionX2 R=ResetCollision -.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2749 Q=CollisionX1 R=ResetCollision -.subckt dff C=clk D=$0\ResetCollision[0:0] Q=ResetCollision -.subckt dff C=clk D=$0\ball_inY[0:0] Q=ball_inY -.subckt dff C=clk D=$0\ball_inX[0:0] Q=ball_inX -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2675 Q=ballY[0] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2673 Q=ballY[1] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2671 Q=ballY[2] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2669 Q=ballY[3] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2667 Q=ballY[4] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2665 Q=ballY[5] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2663 Q=ballY[6] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2661 Q=ballY[7] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2737 Q=ballY[8] -.subckt dff C=clk D=quadB Q=quadBr[0] -.subckt dff C=clk D=quadBr[0] Q=quadBr[1] -.subckt dff C=clk D=quadBr[1] Q=quadBr[2] -.subckt dff C=clk D=quadA Q=quadAr[0] -.subckt dff C=clk D=quadAr[0] Q=quadAr[1] -.subckt dff C=clk D=quadAr[1] Q=quadAr[2] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2725 Q=PaddlePosition[0] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2723 Q=PaddlePosition[1] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2721 Q=PaddlePosition[2] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2719 Q=PaddlePosition[3] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2717 Q=PaddlePosition[4] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2715 Q=PaddlePosition[5] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2713 Q=PaddlePosition[6] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2711 Q=PaddlePosition[7] -.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2727 Q=PaddlePosition[8] -.names $auto$alumacc.cc:485:replace_alu$666.X[0] $auto$alumacc.cc:485:replace_alu$666.Y[0] -1 1 -.names CounterX[1] $auto$alumacc.cc:485:replace_alu$666.X[1] -1 1 -.names CounterX[2] $auto$alumacc.cc:485:replace_alu$666.X[2] -1 1 -.names CounterX[3] $auto$alumacc.cc:485:replace_alu$666.X[3] -1 1 -.names CounterX[4] $auto$alumacc.cc:485:replace_alu$666.X[4] -1 1 -.names CounterX[5] $auto$alumacc.cc:485:replace_alu$666.X[5] -1 1 -.names CounterX[6] $auto$alumacc.cc:485:replace_alu$666.X[6] -1 1 -.names CounterX[7] $auto$alumacc.cc:485:replace_alu$666.X[7] -1 1 -.names CounterX[8] $auto$alumacc.cc:485:replace_alu$666.X[8] -1 1 -.names CounterX[9] $auto$alumacc.cc:485:replace_alu$666.X[9] -1 1 -.names vga_B vga_G -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif deleted file mode 100644 index c6ffa8f4984..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif +++ /dev/null @@ -1,135 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model quad -.inputs clk quadA quadB -.outputs count[0] count[1] count[2] count[3] count[4] count[5] count[6] count[7] -.names $false -.names $true -1 -.names $undef -.names count[6] $abc$833$new_n27 $abc$833$new_n25 $abc$833$new_n23 $abc$833$auto$rtlil.cc:2693:MuxGate$715 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names count[3] count[4] count[5] $abc$833$new_n24 $abc$833$new_n23 -1111 1 -.names count[1] count[2] count[0] quadB_delayed[2] quadA_delayed[1] $abc$833$new_n24 -11101 1 -11110 1 -.names $abc$833$new_n26 count[3] count[4] count[5] $abc$833$new_n25 -1000 1 -.names quadB_delayed[2] quadA_delayed[1] count[0] count[1] count[2] $abc$833$new_n26 -00000 1 -11000 1 -.names quadB_delayed[2] quadB_delayed[1] quadA_delayed[2] quadA_delayed[1] $abc$833$new_n27 -0001 1 -0010 1 -0100 1 -0111 1 -1000 1 -1011 1 -1101 1 -1110 1 -.names count[5] $abc$833$new_n29 $abc$833$auto$rtlil.cc:2693:MuxGate$717 -01 1 -10 1 -.names $abc$833$new_n27 count[3] count[4] $abc$833$new_n24 $abc$833$new_n26 $abc$833$new_n29 -10001 1 -10011 1 -11110 1 -11111 1 -.names count[4] count[3] $abc$833$new_n27 $abc$833$new_n26 $abc$833$new_n24 $abc$833$auto$rtlil.cc:2693:MuxGate$719 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names count[3] $abc$833$new_n27 $abc$833$new_n26 $abc$833$new_n24 $abc$833$auto$rtlil.cc:2693:MuxGate$721 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names count[2] count[0] count[1] $abc$833$new_n33 $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$723 -00011 1 -01101 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names quadB_delayed[2] quadA_delayed[1] $abc$833$new_n33 -00 1 -11 1 -.names count[1] count[0] $abc$833$new_n33 $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$725 -0011 1 -0101 1 -1000 1 -1001 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names count[0] $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$727 -01 1 -10 1 -.names count[7] count[6] $abc$833$new_n27 $abc$833$new_n25 $abc$833$new_n23 $abc$833$auto$rtlil.cc:2693:MuxGate$729 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$727 Q=count[0] -.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$725 Q=count[1] -.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$723 Q=count[2] -.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$721 Q=count[3] -.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$719 Q=count[4] -.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$717 Q=count[5] -.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$715 Q=count[6] -.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$729 Q=count[7] -.subckt dff C=clk D=quadB Q=quadB_delayed[0] -.subckt dff C=clk D=quadB_delayed[0] Q=quadB_delayed[1] -.subckt dff C=clk D=quadB_delayed[1] Q=quadB_delayed[2] -.subckt dff C=clk D=quadA Q=quadA_delayed[0] -.subckt dff C=clk D=quadA_delayed[0] Q=quadA_delayed[1] -.subckt dff C=clk D=quadA_delayed[1] Q=quadA_delayed[2] -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif deleted file mode 100644 index 51d0c4d3cdb..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif +++ /dev/null @@ -1,4862 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model seqcordic -.inputs i_clk i_reset i_stb i_aux i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_phase[0] i_phase[1] i_phase[2] i_phase[3] i_phase[4] i_phase[5] i_phase[6] i_phase[7] i_phase[8] i_phase[9] i_phase[10] i_phase[11] i_phase[12] i_phase[13] i_phase[14] i_phase[15] i_phase[16] i_phase[17] i_phase[18] i_phase[19] -.outputs o_busy o_done o_xval[0] o_xval[1] o_xval[2] o_xval[3] o_xval[4] o_xval[5] o_xval[6] o_xval[7] o_xval[8] o_xval[9] o_xval[10] o_xval[11] o_xval[12] o_yval[0] o_yval[1] o_yval[2] o_yval[3] o_yval[4] o_yval[5] o_yval[6] o_yval[7] o_yval[8] o_yval[9] o_yval[10] o_yval[11] o_yval[12] o_aux -.names $false -.names $true -1 -.names $undef -.names state[1] state[3] state[2] state[0] $auto$alumacc.cc:485:replace_alu$688.CO[3] -1111 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[14] $abc$4039$new_n329 o_yval[11] $abc$4039$auto$rtlil.cc:2693:MuxGate$3820 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names yv[13] yv[12] $abc$4039$new_n330 $abc$4039$new_n329 -111 1 -.names yv[11] yv[10] $abc$4039$new_n331 $abc$4039$new_n330 -111 1 -.names yv[9] yv[8] $abc$4039$new_n332 $abc$4039$new_n331 -111 1 -.names yv[7] $abc$4039$new_n333 $abc$4039$new_n332 -11 1 -.names yv[6] yv[5] yv[4] $abc$4039$new_n334 $abc$4039$new_n333 -1111 1 -.names yv[2] yv[3] $abc$4039$new_n334 -11 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[13] yv[12] $abc$4039$new_n330 o_yval[10] $abc$4039$auto$rtlil.cc:2693:MuxGate$3822 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[12] $abc$4039$new_n330 o_yval[9] $abc$4039$auto$rtlil.cc:2693:MuxGate$3824 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[11] yv[10] $abc$4039$new_n331 o_yval[8] $abc$4039$auto$rtlil.cc:2693:MuxGate$3826 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[10] $abc$4039$new_n331 o_yval[7] $abc$4039$auto$rtlil.cc:2693:MuxGate$3828 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[9] yv[8] $abc$4039$new_n332 o_yval[6] $abc$4039$auto$rtlil.cc:2693:MuxGate$3830 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[8] $abc$4039$new_n332 o_yval[5] $abc$4039$auto$rtlil.cc:2693:MuxGate$3832 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[7] $abc$4039$new_n333 o_yval[4] $abc$4039$auto$rtlil.cc:2693:MuxGate$3834 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n343 o_yval[3] $abc$4039$auto$rtlil.cc:2693:MuxGate$3836 -001 1 -011 1 -110 1 -111 1 -.names yv[6] yv[5] yv[4] $abc$4039$new_n334 $abc$4039$new_n343 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[5] yv[4] $abc$4039$new_n334 o_yval[2] $abc$4039$auto$rtlil.cc:2693:MuxGate$3838 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[4] $abc$4039$new_n334 o_yval[1] $abc$4039$auto$rtlil.cc:2693:MuxGate$3840 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n347 o_yval[0] $abc$4039$auto$rtlil.cc:2693:MuxGate$3842 -001 1 -011 1 -110 1 -111 1 -.names yv[2] yv[3] yv[0] yv[1] $abc$4039$new_n347 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[14] xv[13] $abc$4039$new_n349 o_xval[11] $abc$4039$auto$rtlil.cc:2693:MuxGate$3844 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names xv[12] xv[11] $abc$4039$new_n350 $abc$4039$new_n349 -111 1 -.names xv[10] xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n350 -11111 1 -.names xv[6] xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n351 -11111 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[13] $abc$4039$new_n349 o_xval[10] $abc$4039$auto$rtlil.cc:2693:MuxGate$3846 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[12] xv[11] $abc$4039$new_n350 o_xval[9] $abc$4039$auto$rtlil.cc:2693:MuxGate$3848 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[11] $abc$4039$new_n350 o_xval[8] $abc$4039$auto$rtlil.cc:2693:MuxGate$3850 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n356 o_xval[7] $abc$4039$auto$rtlil.cc:2693:MuxGate$3852 -001 1 -011 1 -110 1 -111 1 -.names xv[10] xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n356 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n358 o_xval[6] $abc$4039$auto$rtlil.cc:2693:MuxGate$3854 -001 1 -011 1 -110 1 -111 1 -.names xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n358 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[8] xv[7] $abc$4039$new_n351 o_xval[5] $abc$4039$auto$rtlil.cc:2693:MuxGate$3856 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[7] $abc$4039$new_n351 o_xval[4] $abc$4039$auto$rtlil.cc:2693:MuxGate$3858 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n362 o_xval[3] $abc$4039$auto$rtlil.cc:2693:MuxGate$3860 -001 1 -011 1 -110 1 -111 1 -.names xv[6] xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n362 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n364 o_xval[2] $abc$4039$auto$rtlil.cc:2693:MuxGate$3862 -001 1 -011 1 -110 1 -111 1 -.names xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n364 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[4] xv[2] xv[3] o_xval[1] $abc$4039$auto$rtlil.cc:2693:MuxGate$3864 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n367 o_xval[0] $abc$4039$auto$rtlil.cc:2693:MuxGate$3866 -001 1 -011 1 -110 1 -111 1 -.names xv[2] xv[3] xv[0] xv[1] $abc$4039$new_n367 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] aux o_aux $abc$4039$auto$rtlil.cc:2693:MuxGate$3868 -001 1 -011 1 -110 1 -111 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[15] yv[14] $abc$4039$new_n329 o_yval[12] $abc$4039$auto$rtlil.cc:2693:MuxGate$3870 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n371 o_xval[12] $abc$4039$auto$rtlil.cc:2693:MuxGate$3872 -001 1 -011 1 -110 1 -111 1 -.names xv[15] xv[14] xv[13] $abc$4039$new_n349 $abc$4039$new_n371 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names i_stb $auto$alumacc.cc:485:replace_alu$688.CO[3] idle $abc$4039$auto$rtlil.cc:2693:MuxGate$3874 -001 1 -010 1 -011 1 -.names i_stb idle $abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y -11 1 -.names $abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y i_aux aux $abc$4039$auto$rtlil.cc:2693:MuxGate$3876 -001 1 -011 1 -110 1 -111 1 -.names state[3] state[2] $abc$4039$auto$opt_dff.cc:253:combine_resets$910 -01 1 -10 1 -11 1 -.names state[1] $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$auto$opt_dff.cc:253:combine_resets$907 -00 1 -01 1 -11 1 -.names i_reset idle $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$auto$opt_dff.cc:253:combine_resets$636 -001 1 -010 1 -011 1 -100 1 -101 1 -110 1 -111 1 -.names i_phase[19] i_phase[18] i_phase[17] $abc$4039$auto$rtlil.cc:2516:Or$645 -000 1 -101 1 -110 1 -111 1 -.names $abc$4039$new_n381 $abc$4039$new_n380 i_xval[0] i_yval[0] $0\prex[15:0][2] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names i_phase[18] i_phase[17] i_phase[19] $abc$4039$new_n380 -000 1 -111 1 -.names i_phase[18] i_phase[17] i_phase[19] $abc$4039$new_n381 -001 1 -110 1 -.names $abc$4039$new_n383 i_xval[1] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[1] $0\prex[15:0][3] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[1] i_yval[0] $abc$4039$new_n384 $abc$4039$new_n383 -00010 1 -00011 1 -00100 1 -00101 1 -10001 1 -10011 1 -10101 1 -10111 1 -.names i_xval[1] i_xval[0] $abc$4039$new_n384 -01 1 -10 1 -.names i_phase[19] i_phase[18] i_phase[17] $abc$4039$new_n385 -101 1 -110 1 -.names $abc$4039$new_n387 i_xval[2] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[2] $0\prex[15:0][4] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n388 $abc$4039$new_n389 $abc$4039$new_n387 -0001 1 -0011 1 -1010 1 -1011 1 -.names i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n388 -001 1 -010 1 -011 1 -100 1 -.names i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n389 -001 1 -010 1 -011 1 -100 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n391 $abc$4039$new_n393 $abc$4039$new_n392 $0\prex[15:0][5] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names i_xval[3] $abc$4039$new_n380 i_yval[3] $abc$4039$new_n385 $abc$4039$new_n391 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n392 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n393 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names $abc$4039$new_n381 $abc$4039$new_n395 $abc$4039$new_n397 $abc$4039$new_n396 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][6] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_xval[4] $abc$4039$new_n380 i_yval[4] $abc$4039$new_n385 $abc$4039$new_n395 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n396 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n397 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -.names $abc$4039$new_n399 i_xval[5] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[5] $0\prex[15:0][7] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[5] $abc$4039$new_n402 $abc$4039$new_n400 $abc$4039$new_n399 -00000 1 -00001 1 -00110 1 -00111 1 -10001 1 -10011 1 -10101 1 -10111 1 -.names i_xval[5] $abc$4039$new_n401 $abc$4039$new_n400 -00 1 -11 1 -.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n401 -00000 1 -.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n402 -00000 1 -.names $abc$4039$new_n381 $abc$4039$new_n405 $abc$4039$new_n406 $abc$4039$new_n404 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][8] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_yval[6] $abc$4039$new_n402 i_yval[5] $abc$4039$new_n404 -000 1 -001 1 -011 1 -110 1 -.names i_xval[6] $abc$4039$new_n380 i_yval[6] $abc$4039$new_n385 $abc$4039$new_n405 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names i_xval[6] $abc$4039$new_n401 i_xval[5] $abc$4039$new_n406 -000 1 -001 1 -011 1 -110 1 -.names $abc$4039$new_n381 $abc$4039$new_n409 $abc$4039$new_n410 $abc$4039$new_n408 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][9] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_yval[7] $abc$4039$new_n402 i_yval[6] i_yval[5] $abc$4039$new_n408 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names i_xval[7] $abc$4039$new_n380 i_yval[7] $abc$4039$new_n385 $abc$4039$new_n409 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names i_xval[7] $abc$4039$new_n401 i_xval[6] i_xval[5] $abc$4039$new_n410 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names $abc$4039$new_n381 $abc$4039$new_n413 $abc$4039$new_n414 $abc$4039$new_n412 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][10] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_yval[8] $abc$4039$new_n402 i_yval[7] i_yval[6] i_yval[5] $abc$4039$new_n412 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names i_xval[8] $abc$4039$new_n380 i_yval[8] $abc$4039$new_n385 $abc$4039$new_n413 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names i_xval[8] $abc$4039$new_n401 i_xval[7] i_xval[6] i_xval[5] $abc$4039$new_n414 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names $abc$4039$new_n416 i_xval[9] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[9] $0\prex[15:0][11] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_xval[9] $abc$4039$new_n419 $abc$4039$new_n417 $abc$4039$new_n416 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-01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10111 1 -11011 1 -11101 1 -11111 1 -.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n381 $abc$4039$new_n430 $abc$4039$new_n431 $abc$4039$new_n429 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -.names i_xval[12] $abc$4039$new_n419 i_xval[10] i_xval[9] i_xval[11] $abc$4039$new_n430 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names i_xval[12] $abc$4039$new_n419 i_xval[11] i_xval[10] i_xval[9] $abc$4039$new_n431 -11000 1 -.names $abc$4039$new_n418 i_yval[11] i_yval[10] i_yval[9] $abc$4039$new_n432 -1000 1 -.names i_xval[12] $abc$4039$new_n380 i_yval[12] $abc$4039$new_n385 $abc$4039$new_n433 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n433 $abc$4039$new_n435 $abc$4039$new_n430 $0\prex[15:0][15] -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names i_yval[12] $abc$4039$new_n432 $abc$4039$new_n435 -00 1 -.names $abc$4039$new_n381 $abc$4039$new_n380 i_yval[0] i_xval[0] $0\prey[15:0][2] -0001 1 -0011 1 -0110 1 -0111 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n380 $abc$4039$new_n438 i_yval[1] $abc$4039$new_n384 $0\prey[15:0][3] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[1] i_yval[0] i_xval[1] $abc$4039$new_n438 -00001 1 -00011 1 -00101 1 -00111 1 -10010 1 -10011 1 -10100 1 -10101 1 -.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n381 $abc$4039$new_n440 $abc$4039$new_n389 i_xval[2] $0\prey[15:0][4] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4039$new_n380 i_yval[2] $abc$4039$new_n388 $abc$4039$new_n440 -000 1 -010 1 -100 1 -101 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n442 $abc$4039$new_n392 i_xval[3] $0\prey[15:0][5] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names i_yval[3] $abc$4039$new_n380 $abc$4039$new_n385 $abc$4039$new_n393 $abc$4039$new_n442 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n444 $abc$4039$new_n396 i_xval[4] $0\prey[15:0][6] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names i_yval[4] $abc$4039$new_n380 $abc$4039$new_n385 $abc$4039$new_n397 $abc$4039$new_n444 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$4039$new_n446 $abc$4039$new_n385 $abc$4039$new_n400 $abc$4039$new_n380 i_yval[5] $0\prey[15:0][7] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[5] $abc$4039$new_n402 i_xval[5] $abc$4039$new_n446 -00001 1 -00011 1 -00101 1 -00111 1 -10000 1 -10001 1 -10110 1 -10111 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n448 $abc$4039$new_n404 i_xval[6] $0\prey[15:0][8] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4039$new_n385 $abc$4039$new_n406 i_yval[6] $abc$4039$new_n380 $abc$4039$new_n448 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n450 $abc$4039$new_n408 i_xval[7] $0\prey[15:0][9] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4039$new_n385 $abc$4039$new_n410 i_yval[7] $abc$4039$new_n380 $abc$4039$new_n450 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n452 $abc$4039$new_n412 i_xval[8] $0\prey[15:0][10] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4039$new_n385 $abc$4039$new_n414 i_yval[8] $abc$4039$new_n380 $abc$4039$new_n452 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n454 $abc$4039$new_n417 i_xval[9] $0\prey[15:0][11] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4039$new_n385 $abc$4039$new_n419 i_xval[9] i_yval[9] $abc$4039$new_n380 $abc$4039$new_n454 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n456 $abc$4039$new_n421 i_xval[10] $0\prey[15:0][12] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4039$new_n385 $abc$4039$new_n422 i_yval[10] $abc$4039$new_n380 $abc$4039$new_n456 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$4039$new_n458 $abc$4039$new_n385 $abc$4039$new_n426 $abc$4039$new_n380 i_yval[11] $0\prey[15:0][13] -00011 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_phase[18] i_phase[17] i_phase[19] i_xval[11] $abc$4039$new_n425 $abc$4039$new_n458 -00101 1 -00111 1 -01010 1 -01011 1 -10010 1 -10011 1 -11001 1 -11011 1 -.names $abc$4039$new_n462 $0\prey[15:0][15] $0\prey[15:0][14] -00 1 -01 1 -11 1 -.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n461 $abc$4039$new_n435 i_xval[12] $0\prey[15:0][15] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4039$new_n385 $abc$4039$new_n430 i_yval[12] $abc$4039$new_n380 $abc$4039$new_n461 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$4039$new_n431 $abc$4039$new_n385 $abc$4039$new_n381 i_yval[12] $abc$4039$new_n432 $abc$4039$new_n462 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -.names state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[15] -10 1 -.names state[2] state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[9] -000 1 -010 1 -110 1 -111 1 -.names state[2] state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[10] -000 1 -010 1 -100 1 -101 1 -.names state[1] state[2] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[11] -000 1 -001 1 -011 1 -101 1 -.names state[1] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[6] -00 1 -.names state[1] state[2] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[12] -001 1 -010 1 -100 1 -.names state[1] state[0] $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] -00 1 -11 1 -.names pre_valid ph[0] cangle[0] preph[0] $0\ph[19:0][0] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names pre_valid $abc$4039$new_n472 preph[1] $0\ph[19:0][1] -010 1 -011 1 -101 1 -111 1 -.names ph[1] cangle[1] ph[0] ph[19] cangle[0] $abc$4039$new_n472 -00001 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11001 1 -11111 1 -.names pre_valid ph[2] cangle[2] $abc$4039$new_n474 preph[2] $0\ph[19:0][2] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[19] $abc$4039$new_n475 $abc$4039$new_n476 $abc$4039$new_n474 -000 1 -001 1 -101 1 -111 1 -.names cangle[0] ph[0] ph[1] cangle[1] $abc$4039$new_n475 -0001 1 -0101 1 -1000 1 -1001 1 -1011 1 -1101 1 -.names cangle[0] ph[0] ph[1] cangle[1] $abc$4039$new_n476 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names pre_valid ph[3] cangle[3] $abc$4039$new_n478 preph[3] $0\ph[19:0][3] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[2] ph[19] cangle[2] $abc$4039$new_n476 $abc$4039$new_n475 $abc$4039$new_n478 -00000 1 -00010 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11010 1 -11011 1 -.names pre_valid $abc$4039$new_n480 preph[4] $0\ph[19:0][4] -010 1 -011 1 -101 1 -111 1 -.names ph[19] ph[4] cangle[4] $abc$4039$new_n482 $abc$4039$new_n481 $abc$4039$new_n480 -00001 1 -00011 1 -00100 1 -00110 1 -01000 1 -01010 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names cangle[2] ph[2] ph[3] cangle[3] $abc$4039$new_n475 $abc$4039$new_n481 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names ph[2] cangle[2] ph[3] cangle[3] $abc$4039$new_n476 $abc$4039$new_n482 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pre_valid ph[5] cangle[5] $abc$4039$new_n484 preph[5] $0\ph[19:0][5] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[4] ph[19] cangle[4] $abc$4039$new_n482 $abc$4039$new_n481 $abc$4039$new_n484 -00000 1 -00010 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11010 1 -11011 1 -.names pre_valid ph[6] cangle[6] $abc$4039$new_n486 preph[6] $0\ph[19:0][6] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[19] ph[5] cangle[5] $abc$4039$new_n487 $abc$4039$new_n488 $abc$4039$new_n486 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names ph[4] cangle[4] $abc$4039$new_n482 $abc$4039$new_n487 -000 1 -001 1 -011 1 -101 1 -.names cangle[4] ph[4] ph[5] cangle[5] $abc$4039$new_n481 $abc$4039$new_n488 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names pre_valid ph[7] cangle[7] $abc$4039$new_n490 preph[7] $0\ph[19:0][7] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[19] ph[6] cangle[6] $abc$4039$new_n488 $abc$4039$new_n491 $abc$4039$new_n490 -00000 1 -00001 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[5] cangle[5] ph[6] cangle[6] $abc$4039$new_n487 $abc$4039$new_n491 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names pre_valid $abc$4039$new_n493 preph[8] $0\ph[19:0][8] -000 1 -001 1 -101 1 -111 1 -.names ph[8] cangle[8] ph[19] $abc$4039$new_n495 $abc$4039$new_n494 $abc$4039$new_n493 -00000 1 -00001 1 -00101 1 -00111 1 -01010 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11101 1 -11111 1 -.names ph[7] cangle[7] $abc$4039$new_n491 $abc$4039$new_n494 -000 1 -001 1 -011 1 -101 1 -.names cangle[6] ph[6] ph[7] cangle[7] $abc$4039$new_n488 $abc$4039$new_n495 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names pre_valid ph[9] cangle[9] $abc$4039$new_n497 preph[9] $0\ph[19:0][9] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[8] ph[19] cangle[8] $abc$4039$new_n495 $abc$4039$new_n494 $abc$4039$new_n497 -00000 1 -00001 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11001 1 -11011 1 -.names pre_valid $abc$4039$new_n499 preph[10] $0\ph[19:0][10] -010 1 -011 1 -101 1 -111 1 -.names ph[10] cangle[10] ph[19] $abc$4039$new_n501 $abc$4039$new_n500 $abc$4039$new_n499 -00000 1 -00001 1 -00101 1 -00111 1 -01010 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11101 1 -11111 1 -.names ph[8] cangle[8] ph[9] cangle[9] $abc$4039$new_n494 $abc$4039$new_n500 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names ph[8] ph[9] cangle[8] cangle[9] $abc$4039$new_n495 $abc$4039$new_n501 -00000 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -10000 1 -10001 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names pre_valid ph[11] cangle[11] $abc$4039$new_n503 preph[11] $0\ph[19:0][11] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[10] ph[19] cangle[10] $abc$4039$new_n501 $abc$4039$new_n500 $abc$4039$new_n503 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -.names pre_valid $abc$4039$new_n505 preph[12] $0\ph[19:0][12] -010 1 -011 1 -101 1 -111 1 -.names ph[12] cangle[12] ph[19] $abc$4039$new_n507 $abc$4039$new_n506 $abc$4039$new_n505 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01101 1 -01111 1 -10000 1 -10001 1 -10101 1 -10111 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names ph[10] cangle[10] ph[11] cangle[11] $abc$4039$new_n500 $abc$4039$new_n506 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names cangle[10] ph[10] ph[11] cangle[11] $abc$4039$new_n501 $abc$4039$new_n507 -00000 1 -00010 1 -00011 1 -00110 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -.names pre_valid ph[13] cangle[13] $abc$4039$new_n509 preph[13] $0\ph[19:0][13] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[12] ph[19] cangle[12] $abc$4039$new_n507 $abc$4039$new_n506 $abc$4039$new_n509 -00000 1 -00001 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11001 1 -11011 1 -.names pre_valid $abc$4039$new_n511 preph[14] $0\ph[19:0][14] -010 1 -011 1 -101 1 -111 1 -.names ph[14] cangle[14] ph[19] $abc$4039$new_n513 $abc$4039$new_n512 $abc$4039$new_n511 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01110 1 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names ph[12] cangle[12] ph[13] cangle[13] $abc$4039$new_n506 $abc$4039$new_n512 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names cangle[12] ph[12] ph[13] cangle[13] $abc$4039$new_n507 $abc$4039$new_n513 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names pre_valid ph[15] cangle[15] $abc$4039$new_n515 preph[15] $0\ph[19:0][15] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[14] ph[19] cangle[14] $abc$4039$new_n513 $abc$4039$new_n512 $abc$4039$new_n515 -00000 1 -00001 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11010 1 -.names pre_valid ph[16] cangle[16] $abc$4039$new_n517 preph[16] $0\ph[19:0][16] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[19] $abc$4039$new_n518 $abc$4039$new_n519 $abc$4039$new_n517 -000 1 -010 1 -110 1 -111 1 -.names ph[14] cangle[14] ph[15] cangle[15] $abc$4039$new_n512 $abc$4039$new_n518 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names cangle[14] ph[14] ph[15] cangle[15] $abc$4039$new_n513 $abc$4039$new_n519 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names pre_valid ph[17] $abc$4039$new_n521 preph[17] $0\ph[19:0][17] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names ph[16] cangle[16] ph[19] $abc$4039$new_n519 $abc$4039$new_n518 $abc$4039$new_n521 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -10100 1 -10110 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid ph[18] $abc$4039$new_n524 $abc$4039$new_n523 preph[18] $0\ph[19:0][18] -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[17] ph[16] cangle[16] $abc$4039$new_n518 ph[19] $abc$4039$new_n523 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names ph[17] cangle[16] ph[16] $abc$4039$new_n519 ph[19] $abc$4039$new_n524 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names pre_valid $abc$4039$new_n523 preph[19] $abc$4039$new_n524 ph[18] $0\ph[19:0][19] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid yv[0] $abc$4039$new_n527 prey[0] $0\yv[15:0][0] -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$4039$new_n533 $abc$4039$new_n536 $abc$4039$new_n528 state[3] $abc$4039$new_n527 -0000 1 -0010 1 -0011 1 -.names state[2] $abc$4039$new_n530 $abc$4039$new_n529 $abc$4039$new_n532 $abc$4039$new_n531 $abc$4039$new_n528 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names state[0] state[1] xv[9] xv[8] $abc$4039$new_n529 -0001 1 -0011 1 -1010 1 -1011 1 -.names state[1] state[0] xv[11] xv[10] $abc$4039$new_n530 -1001 1 -1011 1 -1110 1 -1111 1 -.names state[0] state[1] xv[13] xv[12] $abc$4039$new_n531 -0001 1 -0011 1 -1010 1 -1011 1 -.names state[1] state[0] xv[15] xv[14] $abc$4039$new_n532 -1001 1 -1011 1 -1110 1 -1111 1 -.names state[2] state[1] state[3] $abc$4039$new_n534 $abc$4039$new_n535 $abc$4039$new_n533 -10000 1 -10001 1 -11000 1 -11010 1 -.names state[0] xv[5] xv[4] $abc$4039$new_n534 -000 1 -010 1 -100 1 -101 1 -.names state[0] xv[7] xv[6] $abc$4039$new_n535 -000 1 -010 1 -100 1 -101 1 -.names $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$new_n538 state[1] $abc$4039$new_n537 $abc$4039$new_n536 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -.names state[0] xv[3] xv[2] $abc$4039$new_n537 -000 1 -010 1 -100 1 -101 1 -.names state[0] state[1] xv[1] xv[0] $abc$4039$new_n538 -0000 1 -0010 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names pre_valid $abc$4039$new_n540 prey[1] $0\yv[15:0][1] -010 1 -011 1 -101 1 -111 1 -.names yv[1] $abc$4039$new_n541 yv[0] ph[19] $abc$4039$new_n527 $abc$4039$new_n540 -00000 1 -00001 1 -00011 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names state[3] state[2] $abc$4039$new_n542 $abc$4039$new_n546 $abc$4039$new_n548 $abc$4039$new_n541 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[2] state[1] $abc$4039$new_n545 $abc$4039$new_n543 $abc$4039$new_n544 $abc$4039$new_n542 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] xv[10] xv[9] $abc$4039$new_n543 -000 1 -010 1 -100 1 -101 1 -.names state[0] xv[12] xv[11] $abc$4039$new_n544 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] xv[15] xv[14] xv[13] $abc$4039$new_n545 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[1] state[0] $abc$4039$new_n547 xv[8] xv[7] $abc$4039$new_n546 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] xv[6] xv[5] $abc$4039$new_n547 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4039$new_n549 xv[2] xv[1] $abc$4039$new_n548 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] xv[4] xv[3] $abc$4039$new_n549 -000 1 -010 1 -100 1 -101 1 -.names pre_valid yv[2] $abc$4039$new_n552 $abc$4039$new_n551 prey[2] $0\yv[15:0][2] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[1] yv[0] ph[19] $abc$4039$new_n527 $abc$4039$new_n541 $abc$4039$new_n551 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[3] $abc$4039$new_n557 $abc$4039$new_n553 $abc$4039$new_n558 state[2] $abc$4039$new_n552 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[2] state[1] $abc$4039$new_n556 $abc$4039$new_n554 $abc$4039$new_n555 $abc$4039$new_n553 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] xv[11] xv[10] $abc$4039$new_n554 -000 1 -010 1 -100 1 -101 1 -.names state[0] xv[13] xv[12] $abc$4039$new_n555 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] xv[15] xv[14] $abc$4039$new_n556 -0000 1 -0010 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names state[1] state[2] $abc$4039$new_n534 $abc$4039$new_n537 $abc$4039$new_n557 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names state[1] state[0] $abc$4039$new_n535 xv[9] xv[8] $abc$4039$new_n558 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names pre_valid yv[3] $abc$4039$new_n565 $abc$4039$new_n560 prey[3] $0\yv[15:0][3] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[19] $abc$4039$new_n561 $abc$4039$new_n563 $abc$4039$new_n560 -000 1 -001 1 -101 1 -111 1 -.names $abc$4039$new_n541 yv[1] yv[2] $abc$4039$new_n552 $abc$4039$new_n562 $abc$4039$new_n561 -00000 1 -00010 1 -00011 1 -00110 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -.names yv[0] $abc$4039$new_n533 $abc$4039$new_n536 state[3] $abc$4039$new_n528 $abc$4039$new_n562 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names yv[1] $abc$4039$new_n541 yv[2] $abc$4039$new_n552 $abc$4039$new_n564 $abc$4039$new_n563 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names yv[0] $abc$4039$new_n533 $abc$4039$new_n536 state[3] $abc$4039$new_n528 $abc$4039$new_n564 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names state[3] $abc$4039$new_n566 $abc$4039$new_n568 $abc$4039$new_n565 -001 1 -011 1 -110 1 -111 1 -.names state[2] $abc$4039$new_n567 xv[15] $abc$4039$new_n566 -010 1 -011 1 -100 1 -110 1 -.names state[1] state[0] $abc$4039$new_n544 xv[14] xv[13] $abc$4039$new_n567 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[2] state[1] $abc$4039$new_n569 $abc$4039$new_n547 $abc$4039$new_n549 $abc$4039$new_n568 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] state[0] $abc$4039$new_n543 xv[8] xv[7] $abc$4039$new_n569 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid yv[4] $abc$4039$new_n572 $abc$4039$new_n571 prey[4] $0\yv[15:0][4] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[3] ph[19] $abc$4039$new_n565 $abc$4039$new_n563 $abc$4039$new_n561 $abc$4039$new_n571 -00000 1 -00010 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11010 1 -11011 1 -.names state[3] state[2] $abc$4039$new_n575 $abc$4039$new_n573 $abc$4039$new_n574 $abc$4039$new_n572 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n530 $abc$4039$new_n529 $abc$4039$new_n573 -00 1 -.names state[1] $abc$4039$new_n534 $abc$4039$new_n535 $abc$4039$new_n574 -010 1 -011 1 -101 1 -111 1 -.names state[2] xv[15] $abc$4039$new_n531 $abc$4039$new_n532 $abc$4039$new_n575 -0000 1 -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names pre_valid $abc$4039$new_n577 prey[5] $0\yv[15:0][5] -010 1 -011 1 -101 1 -111 1 -.names ph[19] yv[5] $abc$4039$new_n580 $abc$4039$new_n579 $abc$4039$new_n578 $abc$4039$new_n577 -00001 1 -00011 1 -00100 1 -00110 1 -01000 1 -01010 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$4039$new_n561 yv[3] yv[4] $abc$4039$new_n572 $abc$4039$new_n565 $abc$4039$new_n578 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$4039$new_n563 yv[3] yv[4] $abc$4039$new_n572 $abc$4039$new_n565 $abc$4039$new_n579 -00000 1 -00001 1 -00010 1 -00100 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11100 1 -.names state[3] state[2] $abc$4039$new_n582 $abc$4039$new_n581 $abc$4039$new_n546 $abc$4039$new_n580 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] $abc$4039$new_n543 $abc$4039$new_n544 $abc$4039$new_n581 -010 1 -011 1 -101 1 -111 1 -.names state[2] $abc$4039$new_n545 xv[15] $abc$4039$new_n582 -010 1 -011 1 -100 1 -110 1 -.names state[3] state[2] $abc$4039$new_n589 $abc$4039$new_n588 $abc$4039$new_n558 $abc$4039$new_n587 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] $abc$4039$new_n554 $abc$4039$new_n555 $abc$4039$new_n588 -010 1 -011 1 -101 1 -111 1 -.names state[2] $abc$4039$new_n556 xv[15] $abc$4039$new_n589 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n591 prey[7] $0\yv[15:0][7] -010 1 -011 1 -101 1 -111 1 -.names yv[7] $abc$4039$new_n594 ph[19] $abc$4039$new_n593 $abc$4039$new_n592 $abc$4039$new_n591 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01101 1 -01111 1 -10000 1 -10001 1 -10101 1 -10111 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names yv[5] $abc$4039$new_n580 yv[6] $abc$4039$new_n587 $abc$4039$new_n579 $abc$4039$new_n592 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$4039$new_n580 yv[5] yv[6] $abc$4039$new_n587 $abc$4039$new_n578 $abc$4039$new_n593 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names state[3] state[2] xv[15] $abc$4039$new_n567 $abc$4039$new_n569 $abc$4039$new_n594 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid yv[8] $abc$4039$new_n597 $abc$4039$new_n596 prey[8] $0\yv[15:0][8] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[7] ph[19] $abc$4039$new_n594 $abc$4039$new_n593 $abc$4039$new_n592 $abc$4039$new_n596 -00000 1 -00001 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11001 1 -11011 1 -.names state[3] $abc$4039$new_n528 xv[15] $abc$4039$new_n597 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n599 prey[9] $0\yv[15:0][9] -010 1 -011 1 -101 1 -111 1 -.names yv[9] $abc$4039$new_n602 ph[19] $abc$4039$new_n601 $abc$4039$new_n600 $abc$4039$new_n599 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01110 1 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names yv[7] $abc$4039$new_n594 yv[8] $abc$4039$new_n597 $abc$4039$new_n592 $abc$4039$new_n600 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n594 yv[7] yv[8] $abc$4039$new_n597 $abc$4039$new_n593 $abc$4039$new_n601 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names state[3] $abc$4039$new_n542 xv[15] $abc$4039$new_n602 -010 1 -011 1 -100 1 -110 1 -.names state[3] $abc$4039$new_n553 xv[15] $abc$4039$new_n607 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n609 prey[11] $0\yv[15:0][11] -010 1 -011 1 -101 1 -111 1 -.names yv[11] $abc$4039$new_n612 ph[19] $abc$4039$new_n611 $abc$4039$new_n610 $abc$4039$new_n609 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names yv[9] $abc$4039$new_n602 yv[10] $abc$4039$new_n607 $abc$4039$new_n600 $abc$4039$new_n610 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names yv[9] yv[10] $abc$4039$new_n602 $abc$4039$new_n607 $abc$4039$new_n601 $abc$4039$new_n611 -00000 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -10000 1 -10001 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names state[3] $abc$4039$new_n566 xv[15] $abc$4039$new_n612 -010 1 -011 1 -100 1 -110 1 -.names pre_valid yv[12] $abc$4039$new_n615 $abc$4039$new_n614 prey[12] $0\yv[15:0][12] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[11] ph[19] $abc$4039$new_n612 $abc$4039$new_n611 $abc$4039$new_n610 $abc$4039$new_n614 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names state[3] $abc$4039$new_n575 xv[15] $abc$4039$new_n615 -010 1 -011 1 -100 1 -110 1 -.names pre_valid yv[13] $abc$4039$new_n620 $abc$4039$new_n617 prey[13] $0\yv[15:0][13] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[19] $abc$4039$new_n618 $abc$4039$new_n619 $abc$4039$new_n617 -000 1 -010 1 -100 1 -101 1 -.names yv[11] $abc$4039$new_n612 yv[12] $abc$4039$new_n615 $abc$4039$new_n610 $abc$4039$new_n618 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names yv[11] yv[12] $abc$4039$new_n612 $abc$4039$new_n615 $abc$4039$new_n611 $abc$4039$new_n619 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names state[3] $abc$4039$new_n582 xv[15] $abc$4039$new_n620 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n623 $abc$4039$new_n622 prey[14] $0\yv[15:0][14] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names yv[13] $abc$4039$new_n620 ph[19] $abc$4039$new_n619 $abc$4039$new_n618 $abc$4039$new_n622 -00000 1 -00001 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names yv[14] $abc$4039$new_n624 $abc$4039$new_n623 -01 1 -10 1 -.names state[3] $abc$4039$new_n589 xv[15] $abc$4039$new_n624 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n631 $abc$4039$new_n628 $abc$4039$new_n626 prey[15] $0\yv[15:0][15] -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$4039$new_n627 $abc$4039$new_n620 yv[13] $abc$4039$new_n619 $abc$4039$new_n623 $abc$4039$new_n626 -10000 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names ph[19] $abc$4039$new_n624 yv[14] $abc$4039$new_n627 -000 1 -010 1 -011 1 -.names $abc$4039$new_n630 yv[13] $abc$4039$new_n620 $abc$4039$new_n618 $abc$4039$new_n623 $abc$4039$new_n628 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names ph[19] $abc$4039$new_n624 yv[14] $abc$4039$new_n630 -101 1 -110 1 -111 1 -.names yv[15] xv[15] $abc$4039$new_n631 -00 1 -11 1 -.names pre_valid xv[0] $abc$4039$new_n633 prex[0] $0\xv[15:0][0] -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$4039$new_n639 $abc$4039$new_n642 $abc$4039$new_n634 state[3] $abc$4039$new_n633 -0000 1 -0010 1 -0011 1 -.names state[2] $abc$4039$new_n636 $abc$4039$new_n635 $abc$4039$new_n638 $abc$4039$new_n637 $abc$4039$new_n634 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names state[0] state[1] yv[9] yv[8] $abc$4039$new_n635 -0001 1 -0011 1 -1010 1 -1011 1 -.names state[1] state[0] yv[11] yv[10] $abc$4039$new_n636 -1001 1 -1011 1 -1110 1 -1111 1 -.names state[0] state[1] yv[13] yv[12] $abc$4039$new_n637 -0001 1 -0011 1 -1010 1 -1011 1 -.names state[1] state[0] yv[15] yv[14] $abc$4039$new_n638 -1001 1 -1011 1 -1110 1 -1111 1 -.names state[2] state[1] state[3] $abc$4039$new_n640 $abc$4039$new_n641 $abc$4039$new_n639 -10000 1 -10001 1 -11000 1 -11010 1 -.names state[0] yv[5] yv[4] $abc$4039$new_n640 -000 1 -010 1 -100 1 -101 1 -.names state[0] yv[7] yv[6] $abc$4039$new_n641 -000 1 -010 1 -100 1 -101 1 -.names $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$new_n644 state[1] $abc$4039$new_n643 $abc$4039$new_n642 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -.names state[0] yv[3] yv[2] $abc$4039$new_n643 -000 1 -010 1 -100 1 -101 1 -.names state[0] state[1] yv[1] yv[0] $abc$4039$new_n644 -0000 1 -0010 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names pre_valid $abc$4039$new_n646 prex[1] $0\xv[15:0][1] -010 1 -011 1 -101 1 -111 1 -.names xv[1] $abc$4039$new_n769 xv[0] ph[19] $abc$4039$new_n633 $abc$4039$new_n646 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01110 1 -10000 1 -10110 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names state[2] state[1] $abc$4039$new_n651 $abc$4039$new_n649 $abc$4039$new_n650 $abc$4039$new_n648 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] yv[10] yv[9] $abc$4039$new_n649 -000 1 -010 1 -100 1 -101 1 -.names state[0] yv[12] yv[11] $abc$4039$new_n650 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] yv[15] yv[14] yv[13] $abc$4039$new_n651 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[1] state[0] $abc$4039$new_n653 yv[8] yv[7] $abc$4039$new_n652 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] yv[6] yv[5] $abc$4039$new_n653 -000 1 -010 1 -100 1 -101 1 -.names state[0] yv[4] yv[3] $abc$4039$new_n655 -000 1 -010 1 -100 1 -101 1 -.names pre_valid xv[2] $abc$4039$new_n659 $abc$4039$new_n658 prex[2] $0\xv[15:0][2] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[1] xv[0] ph[19] $abc$4039$new_n633 $abc$4039$new_n769 $abc$4039$new_n658 -00000 1 -00001 1 -00010 1 -01000 1 -01010 1 -01100 1 -10000 1 -10100 1 -10110 1 -11100 1 -11101 1 -11110 1 -.names state[3] $abc$4039$new_n664 $abc$4039$new_n660 $abc$4039$new_n665 state[2] $abc$4039$new_n659 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[2] state[1] $abc$4039$new_n663 $abc$4039$new_n661 $abc$4039$new_n662 $abc$4039$new_n660 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] yv[11] yv[10] $abc$4039$new_n661 -000 1 -010 1 -100 1 -101 1 -.names state[0] yv[13] yv[12] $abc$4039$new_n662 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] yv[15] yv[14] $abc$4039$new_n663 -0000 1 -0010 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names state[1] state[2] $abc$4039$new_n640 $abc$4039$new_n643 $abc$4039$new_n664 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names state[1] state[0] $abc$4039$new_n641 yv[9] yv[8] $abc$4039$new_n665 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names pre_valid $abc$4039$new_n667 prex[3] $0\xv[15:0][3] -010 1 -011 1 -101 1 -111 1 -.names ph[19] xv[3] $abc$4039$new_n668 $abc$4039$new_n675 $abc$4039$new_n673 $abc$4039$new_n667 -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names state[3] $abc$4039$new_n671 $abc$4039$new_n669 $abc$4039$new_n672 state[2] $abc$4039$new_n668 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[2] $abc$4039$new_n670 yv[15] $abc$4039$new_n669 -010 1 -011 1 -100 1 -110 1 -.names state[1] state[0] $abc$4039$new_n650 yv[14] yv[13] $abc$4039$new_n670 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[1] state[2] $abc$4039$new_n653 $abc$4039$new_n655 $abc$4039$new_n671 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names state[1] state[0] $abc$4039$new_n649 yv[8] yv[7] $abc$4039$new_n672 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names xv[1] $abc$4039$new_n769 xv[2] $abc$4039$new_n659 $abc$4039$new_n674 $abc$4039$new_n673 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[0] $abc$4039$new_n639 $abc$4039$new_n642 state[3] $abc$4039$new_n634 $abc$4039$new_n674 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$4039$new_n769 xv[1] xv[2] $abc$4039$new_n659 $abc$4039$new_n676 $abc$4039$new_n675 -00000 1 -00010 1 -00011 1 -00110 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -.names xv[0] $abc$4039$new_n639 $abc$4039$new_n642 state[3] $abc$4039$new_n634 $abc$4039$new_n676 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid xv[4] $abc$4039$new_n679 $abc$4039$new_n678 prex[4] $0\xv[15:0][4] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[3] $abc$4039$new_n668 ph[19] $abc$4039$new_n675 $abc$4039$new_n673 $abc$4039$new_n678 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names state[3] state[2] $abc$4039$new_n682 $abc$4039$new_n680 $abc$4039$new_n681 $abc$4039$new_n679 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n636 $abc$4039$new_n635 $abc$4039$new_n680 -00 1 -.names state[1] $abc$4039$new_n640 $abc$4039$new_n641 $abc$4039$new_n681 -010 1 -011 1 -101 1 -111 1 -.names state[2] yv[15] $abc$4039$new_n637 $abc$4039$new_n638 $abc$4039$new_n682 -0000 1 -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names pre_valid $abc$4039$new_n684 prex[5] $0\xv[15:0][5] -000 1 -001 1 -101 1 -111 1 -.names xv[5] $abc$4039$new_n687 ph[19] $abc$4039$new_n686 $abc$4039$new_n685 $abc$4039$new_n684 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01101 1 -01111 1 -10000 1 -10001 1 -10101 1 -10111 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names $abc$4039$new_n675 xv[3] xv[4] $abc$4039$new_n679 $abc$4039$new_n668 $abc$4039$new_n685 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$4039$new_n673 xv[3] xv[4] $abc$4039$new_n679 $abc$4039$new_n668 $abc$4039$new_n686 -00000 1 -00001 1 -00010 1 -00100 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11100 1 -.names state[3] state[2] $abc$4039$new_n689 $abc$4039$new_n688 $abc$4039$new_n652 $abc$4039$new_n687 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] $abc$4039$new_n649 $abc$4039$new_n650 $abc$4039$new_n688 -010 1 -011 1 -101 1 -111 1 -.names state[2] $abc$4039$new_n651 yv[15] $abc$4039$new_n689 -010 1 -011 1 -100 1 -110 1 -.names state[3] state[2] $abc$4039$new_n696 $abc$4039$new_n695 $abc$4039$new_n665 $abc$4039$new_n694 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] $abc$4039$new_n661 $abc$4039$new_n662 $abc$4039$new_n695 -010 1 -011 1 -101 1 -111 1 -.names state[2] $abc$4039$new_n663 yv[15] $abc$4039$new_n696 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n698 prex[7] $0\xv[15:0][7] -000 1 -001 1 -101 1 -111 1 -.names xv[7] $abc$4039$new_n701 ph[19] $abc$4039$new_n700 $abc$4039$new_n699 $abc$4039$new_n698 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01101 1 -01111 1 -10000 1 -10001 1 -10101 1 -10111 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names $abc$4039$new_n687 xv[5] xv[6] $abc$4039$new_n694 $abc$4039$new_n685 $abc$4039$new_n699 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names xv[5] $abc$4039$new_n687 xv[6] $abc$4039$new_n694 $abc$4039$new_n686 $abc$4039$new_n700 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names state[3] state[2] yv[15] $abc$4039$new_n670 $abc$4039$new_n672 $abc$4039$new_n701 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4039$new_n701 xv[7] $abc$4039$new_n699 $abc$4039$new_n705 -001 1 -100 1 -101 1 -111 1 -.names xv[8] $abc$4039$new_n707 $abc$4039$new_n706 -01 1 -10 1 -.names state[3] $abc$4039$new_n634 yv[15] $abc$4039$new_n707 -010 1 -011 1 -100 1 -110 1 -.names pre_valid xv[9] $abc$4039$new_n712 $abc$4039$new_n709 prex[9] $0\xv[15:0][9] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[19] $abc$4039$new_n710 $abc$4039$new_n711 $abc$4039$new_n706 $abc$4039$new_n705 $abc$4039$new_n709 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names xv[7] $abc$4039$new_n701 xv[8] $abc$4039$new_n707 $abc$4039$new_n700 $abc$4039$new_n710 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names xv[8] $abc$4039$new_n707 $abc$4039$new_n711 -10 1 -.names state[3] $abc$4039$new_n648 yv[15] $abc$4039$new_n712 -010 1 -011 1 -100 1 -110 1 -.names pre_valid xv[10] $abc$4039$new_n717 $abc$4039$new_n714 prex[10] $0\xv[15:0][10] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[9] ph[19] $abc$4039$new_n712 $abc$4039$new_n710 $abc$4039$new_n715 $abc$4039$new_n714 -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$4039$new_n716 $abc$4039$new_n701 xv[7] $abc$4039$new_n699 $abc$4039$new_n706 $abc$4039$new_n715 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n711 $abc$4039$new_n712 xv[9] $abc$4039$new_n716 -000 1 -010 1 -011 1 -.names state[3] $abc$4039$new_n660 yv[15] $abc$4039$new_n717 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n719 prex[11] $0\xv[15:0][11] -010 1 -011 1 -101 1 -111 1 -.names xv[11] $abc$4039$new_n723 ph[19] $abc$4039$new_n722 $abc$4039$new_n720 $abc$4039$new_n719 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names xv[10] $abc$4039$new_n715 $abc$4039$new_n721 $abc$4039$new_n717 $abc$4039$new_n720 -0000 1 -1000 1 -1001 1 -1010 1 -1100 1 -1110 1 -.names $abc$4039$new_n712 xv[9] $abc$4039$new_n721 -10 1 -.names xv[9] $abc$4039$new_n712 xv[10] $abc$4039$new_n717 $abc$4039$new_n710 $abc$4039$new_n722 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names state[3] $abc$4039$new_n669 yv[15] $abc$4039$new_n723 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n730 $abc$4039$new_n725 prex[12] $0\xv[15:0][12] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names ph[19] $abc$4039$new_n726 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n725 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names xv[11] $abc$4039$new_n723 $abc$4039$new_n722 $abc$4039$new_n726 -010 1 -100 1 -110 1 -111 1 -.names xv[10] $abc$4039$new_n715 $abc$4039$new_n721 $abc$4039$new_n717 $abc$4039$new_n728 $abc$4039$new_n727 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -11010 1 -11110 1 -.names xv[11] $abc$4039$new_n723 $abc$4039$new_n728 -10 1 -.names $abc$4039$new_n723 xv[11] $abc$4039$new_n729 -10 1 -.names xv[12] $abc$4039$new_n731 $abc$4039$new_n730 -01 1 -10 1 -.names state[3] $abc$4039$new_n682 yv[15] $abc$4039$new_n731 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n733 $abc$4039$new_n735 prex[13] $0\xv[15:0][13] -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names xv[12] ph[19] $abc$4039$new_n731 $abc$4039$new_n726 $abc$4039$new_n734 $abc$4039$new_n733 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$4039$new_n730 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n734 -000 1 -.names xv[13] $abc$4039$new_n736 $abc$4039$new_n735 -01 1 -10 1 -.names state[3] $abc$4039$new_n689 yv[15] $abc$4039$new_n736 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n738 $abc$4039$new_n742 prex[14] $0\xv[15:0][14] -0000 1 -0001 1 -0110 1 -0111 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names ph[19] xv[13] $abc$4039$new_n736 $abc$4039$new_n739 $abc$4039$new_n740 $abc$4039$new_n738 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names xv[11] $abc$4039$new_n723 xv[12] $abc$4039$new_n731 $abc$4039$new_n722 $abc$4039$new_n739 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4039$new_n741 $abc$4039$new_n730 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n735 $abc$4039$new_n740 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -.names xv[12] xv[13] $abc$4039$new_n731 $abc$4039$new_n736 $abc$4039$new_n741 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0111 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names xv[14] $abc$4039$new_n743 $abc$4039$new_n742 -00 1 -11 1 -.names state[3] $abc$4039$new_n696 yv[15] $abc$4039$new_n743 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4039$new_n631 $abc$4039$new_n747 $abc$4039$new_n745 prex[15] $0\xv[15:0][15] -00000 1 -00001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$4039$new_n746 xv[13] $abc$4039$new_n736 $abc$4039$new_n739 $abc$4039$new_n742 $abc$4039$new_n745 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[19] $abc$4039$new_n743 xv[14] $abc$4039$new_n746 -000 1 -001 1 -010 1 -.names ph[19] xv[14] $abc$4039$new_n743 $abc$4039$new_n740 $abc$4039$new_n747 -1001 1 -1100 1 -1101 1 -1111 1 -.names state[3] state[0] state[2] state[1] $\cordic_angle$rdreg[0]$d[0] -0001 1 -0010 1 -0011 1 -0100 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names state[1] state[2] state[0] state[3] $\cordic_angle$rdreg[0]$d[1] -0010 1 -0011 1 -0110 1 -0111 1 -1100 1 -1110 1 -1111 1 -.names state[2] state[3] state[1] state[0] $\cordic_angle$rdreg[0]$d[2] -0100 1 -1000 1 -1001 1 -1010 1 -1100 1 -1110 1 -.names state[2] state[1] state[3] state[0] $\cordic_angle$rdreg[0]$d[3] -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -.names state[0] state[1] state[2] state[3] $\cordic_angle$rdreg[0]$d[4] -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -1000 1 -1100 1 -.names state[0] state[2] state[1] state[3] $\cordic_angle$rdreg[0]$d[5] -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names state[3] state[0] state[2] state[1] $\cordic_angle$rdreg[0]$d[6] -0000 1 -0010 1 -1000 1 -1001 1 -.names state[0] state[1] state[2] state[3] $\cordic_angle$rdreg[0]$d[7] -1000 1 -1001 1 -1100 1 -1110 1 -.names state[3] state[0] state[1] state[2] $\cordic_angle$rdreg[0]$d[8] -0010 1 -0011 1 -0100 1 -1000 1 -.names state[2] state[1] state[0] $auto$alumacc.cc:485:replace_alu$688.Y[2] -011 1 -100 1 -101 1 -110 1 -.names state[3] state[1] state[2] state[0] $auto$alumacc.cc:485:replace_alu$688.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names state[0] $auto$alumacc.cc:485:replace_alu$688.Y[0] -0 1 -.names idle o_busy -0 1 -.names $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] $auto$alumacc.cc:485:replace_alu$688.Y[1] -0 1 -.names yv[5] $abc$4039$new_n580 ph[19] $abc$4039$new_n579 $abc$4039$new_n578 $abc$4039$new_n764 -00001 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10100 1 -10101 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid $abc$4039$new_n587 yv[6] $abc$4039$new_n764 prey[6] $0\yv[15:0][6] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[9] $abc$4039$new_n602 ph[19] $abc$4039$new_n600 $abc$4039$new_n601 $abc$4039$new_n766 -00001 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid $abc$4039$new_n607 yv[10] $abc$4039$new_n766 prey[10] $0\yv[15:0][10] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names state[1] state[0] $abc$4039$new_n655 yv[2] yv[1] $abc$4039$new_n768 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[3] state[2] $abc$4039$new_n648 $abc$4039$new_n768 $abc$4039$new_n652 $abc$4039$new_n769 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names xv[5] $abc$4039$new_n687 ph[19] $abc$4039$new_n686 $abc$4039$new_n685 $abc$4039$new_n770 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names pre_valid $abc$4039$new_n694 xv[6] $abc$4039$new_n770 prex[6] $0\xv[15:0][6] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[7] $abc$4039$new_n701 ph[19] $abc$4039$new_n700 $abc$4039$new_n699 $abc$4039$new_n772 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names pre_valid $abc$4039$new_n706 $abc$4039$new_n772 prex[8] $0\xv[15:0][8] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3868 Q=o_aux -.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] Q=cangle[13] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 -.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[15] Q=cangle[15] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 -.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[6] Q=cangle[16] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[0] Q=cangle[0] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[1] Q=cangle[1] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[2] Q=cangle[2] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[3] Q=cangle[3] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[4] Q=cangle[4] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[5] Q=cangle[5] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[6] Q=cangle[6] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[7] Q=cangle[7] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[8] Q=cangle[8] -.subckt dff C=i_clk D=$0\prex[15:0][2] Q=prex[2] -.subckt dff C=i_clk D=$0\prex[15:0][3] Q=prex[3] -.subckt dff C=i_clk D=$0\prex[15:0][4] Q=prex[4] -.subckt dff C=i_clk D=$0\prex[15:0][5] Q=prex[5] -.subckt dff C=i_clk D=$0\prex[15:0][6] Q=prex[6] -.subckt dff C=i_clk D=$0\prex[15:0][7] Q=prex[7] -.subckt dff C=i_clk D=$0\prex[15:0][8] Q=prex[8] -.subckt dff C=i_clk D=$0\prex[15:0][9] Q=prex[9] -.subckt dff C=i_clk D=$0\prex[15:0][10] Q=prex[10] -.subckt dff C=i_clk D=$0\prex[15:0][11] Q=prex[11] -.subckt dff C=i_clk D=$0\prex[15:0][12] Q=prex[12] -.subckt dff C=i_clk D=$0\prex[15:0][13] Q=prex[13] -.subckt dff C=i_clk D=$0\prex[15:0][14] Q=prex[14] -.subckt dff C=i_clk D=$0\prex[15:0][15] Q=prex[15] -.subckt sdffr C=i_clk D=$false Q=prex[0] R=$abc$4039$auto$rtlil.cc:2516:Or$645 -.subckt sdffr C=i_clk D=$false Q=prex[1] R=$abc$4039$auto$rtlil.cc:2516:Or$645 -.subckt sdffs C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3874 Q=idle S=i_reset -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3866 Q=o_xval[0] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3864 Q=o_xval[1] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3862 Q=o_xval[2] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3860 Q=o_xval[3] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3858 Q=o_xval[4] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3856 Q=o_xval[5] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3854 Q=o_xval[6] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3852 Q=o_xval[7] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3850 Q=o_xval[8] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3848 Q=o_xval[9] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3846 Q=o_xval[10] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3844 Q=o_xval[11] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3872 Q=o_xval[12] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3842 Q=o_yval[0] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3840 Q=o_yval[1] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3838 Q=o_yval[2] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3836 Q=o_yval[3] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3834 Q=o_yval[4] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3832 Q=o_yval[5] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3830 Q=o_yval[6] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3828 Q=o_yval[7] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3826 Q=o_yval[8] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3824 Q=o_yval[9] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3822 Q=o_yval[10] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3820 Q=o_yval[11] -.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3870 Q=o_yval[12] -.subckt dff C=i_clk D=$0\xv[15:0][0] Q=xv[0] -.subckt dff C=i_clk D=$0\xv[15:0][1] Q=xv[1] -.subckt dff C=i_clk D=$0\xv[15:0][2] Q=xv[2] -.subckt dff C=i_clk D=$0\xv[15:0][3] Q=xv[3] -.subckt dff C=i_clk D=$0\xv[15:0][4] Q=xv[4] -.subckt dff C=i_clk D=$0\xv[15:0][5] Q=xv[5] -.subckt dff C=i_clk D=$0\xv[15:0][6] Q=xv[6] -.subckt dff C=i_clk D=$0\xv[15:0][7] Q=xv[7] -.subckt dff C=i_clk D=$0\xv[15:0][8] Q=xv[8] -.subckt dff C=i_clk D=$0\xv[15:0][9] Q=xv[9] -.subckt dff C=i_clk D=$0\xv[15:0][10] Q=xv[10] -.subckt dff C=i_clk D=$0\xv[15:0][11] Q=xv[11] -.subckt dff C=i_clk D=$0\xv[15:0][12] Q=xv[12] -.subckt dff C=i_clk D=$0\xv[15:0][13] Q=xv[13] -.subckt dff C=i_clk D=$0\xv[15:0][14] Q=xv[14] -.subckt dff C=i_clk D=$0\xv[15:0][15] Q=xv[15] -.subckt dff C=i_clk D=$0\yv[15:0][0] Q=yv[0] -.subckt dff C=i_clk D=$0\yv[15:0][1] Q=yv[1] -.subckt dff C=i_clk D=$0\yv[15:0][2] Q=yv[2] -.subckt dff C=i_clk D=$0\yv[15:0][3] Q=yv[3] -.subckt dff C=i_clk D=$0\yv[15:0][4] Q=yv[4] -.subckt dff C=i_clk D=$0\yv[15:0][5] Q=yv[5] -.subckt dff C=i_clk D=$0\yv[15:0][6] Q=yv[6] -.subckt dff C=i_clk D=$0\yv[15:0][7] Q=yv[7] -.subckt dff C=i_clk D=$0\yv[15:0][8] Q=yv[8] -.subckt dff C=i_clk D=$0\yv[15:0][9] Q=yv[9] -.subckt dff C=i_clk D=$0\yv[15:0][10] Q=yv[10] -.subckt dff C=i_clk D=$0\yv[15:0][11] Q=yv[11] -.subckt dff C=i_clk D=$0\yv[15:0][12] Q=yv[12] -.subckt dff C=i_clk D=$0\yv[15:0][13] Q=yv[13] -.subckt dff C=i_clk D=$0\yv[15:0][14] Q=yv[14] -.subckt dff C=i_clk D=$0\yv[15:0][15] Q=yv[15] -.subckt dff C=i_clk D=$0\ph[19:0][0] Q=ph[0] -.subckt dff C=i_clk D=$0\ph[19:0][1] Q=ph[1] -.subckt dff C=i_clk D=$0\ph[19:0][2] Q=ph[2] -.subckt dff C=i_clk D=$0\ph[19:0][3] Q=ph[3] -.subckt dff C=i_clk D=$0\ph[19:0][4] Q=ph[4] -.subckt dff C=i_clk D=$0\ph[19:0][5] Q=ph[5] -.subckt dff C=i_clk D=$0\ph[19:0][6] Q=ph[6] -.subckt dff C=i_clk D=$0\ph[19:0][7] Q=ph[7] -.subckt dff C=i_clk D=$0\ph[19:0][8] Q=ph[8] -.subckt dff C=i_clk D=$0\ph[19:0][9] Q=ph[9] -.subckt dff C=i_clk D=$0\ph[19:0][10] Q=ph[10] -.subckt dff C=i_clk D=$0\ph[19:0][11] Q=ph[11] -.subckt dff C=i_clk D=$0\ph[19:0][12] Q=ph[12] -.subckt dff C=i_clk D=$0\ph[19:0][13] Q=ph[13] -.subckt dff C=i_clk D=$0\ph[19:0][14] Q=ph[14] -.subckt dff C=i_clk D=$0\ph[19:0][15] Q=ph[15] -.subckt dff C=i_clk D=$0\ph[19:0][16] Q=ph[16] -.subckt dff C=i_clk D=$0\ph[19:0][17] Q=ph[17] -.subckt dff C=i_clk D=$0\ph[19:0][18] Q=ph[18] -.subckt dff C=i_clk D=$0\ph[19:0][19] Q=ph[19] -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.CO[3] Q=o_done R=i_reset -.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[9] Q=cangle[9] R=state[3] -.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[10] Q=cangle[10] R=state[3] -.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[11] Q=cangle[11] R=state[3] -.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[12] Q=cangle[12] R=state[3] -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[0] Q=state[0] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[1] Q=state[1] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[2] Q=state[2] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[3] Q=state[3] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 -.subckt sdffr C=i_clk D=$abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y Q=pre_valid R=i_reset -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[0] Q=cangle[14] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$907 -.subckt dff C=i_clk D=$false Q=prey[0] -.subckt dff C=i_clk D=$false Q=prey[1] -.subckt dff C=i_clk D=$0\prey[15:0][2] Q=prey[2] -.subckt dff C=i_clk D=$0\prey[15:0][3] Q=prey[3] -.subckt dff C=i_clk D=$0\prey[15:0][4] Q=prey[4] -.subckt dff C=i_clk D=$0\prey[15:0][5] Q=prey[5] -.subckt dff C=i_clk D=$0\prey[15:0][6] Q=prey[6] -.subckt dff C=i_clk D=$0\prey[15:0][7] Q=prey[7] -.subckt dff C=i_clk D=$0\prey[15:0][8] Q=prey[8] -.subckt dff C=i_clk D=$0\prey[15:0][9] Q=prey[9] -.subckt dff C=i_clk D=$0\prey[15:0][10] Q=prey[10] -.subckt dff C=i_clk D=$0\prey[15:0][11] Q=prey[11] -.subckt dff C=i_clk D=$0\prey[15:0][12] Q=prey[12] -.subckt dff C=i_clk D=$0\prey[15:0][13] Q=prey[13] -.subckt dff C=i_clk D=$0\prey[15:0][14] Q=prey[14] -.subckt dff C=i_clk D=$0\prey[15:0][15] Q=prey[15] -.subckt dff C=i_clk D=i_phase[0] Q=preph[0] -.subckt dff C=i_clk D=i_phase[1] Q=preph[1] -.subckt dff C=i_clk D=i_phase[2] Q=preph[2] -.subckt dff C=i_clk D=i_phase[3] Q=preph[3] -.subckt dff C=i_clk D=i_phase[4] Q=preph[4] -.subckt dff C=i_clk D=i_phase[5] Q=preph[5] -.subckt dff C=i_clk D=i_phase[6] Q=preph[6] -.subckt dff C=i_clk D=i_phase[7] Q=preph[7] -.subckt dff C=i_clk D=i_phase[8] Q=preph[8] -.subckt dff C=i_clk D=i_phase[9] Q=preph[9] -.subckt dff C=i_clk D=i_phase[10] Q=preph[10] -.subckt dff C=i_clk D=i_phase[11] Q=preph[11] -.subckt dff C=i_clk D=i_phase[12] Q=preph[12] -.subckt dff C=i_clk D=i_phase[13] Q=preph[13] -.subckt dff C=i_clk D=i_phase[14] Q=preph[14] -.subckt dff C=i_clk D=i_phase[15] Q=preph[15] -.subckt dff C=i_clk D=i_phase[16] Q=preph[16] -.subckt dff C=i_clk D=i_phase[17] Q=preph[17] -.subckt dff C=i_clk D=i_phase[17] Q=preph[18] -.subckt dff C=i_clk D=i_phase[17] Q=preph[19] -.subckt sdffr C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3876 Q=aux R=i_reset -.names $false $0\prex[15:0][0] -1 1 -.names $false $0\prex[15:0][1] -1 1 -.names $false $0\prey[15:0][0] -1 1 -.names $false $0\prey[15:0][1] -1 1 -.names state[0] $auto$alumacc.cc:485:replace_alu$688.CO[0] -1 1 -.names $false cangle[17] -1 1 -.names $false cangle[18] -1 1 -.names $false cangle[19] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif deleted file mode 100644 index fd71bc8657f..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif +++ /dev/null @@ -1,6314 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model seqpolar -.inputs i_clk i_reset i_stb i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_aux -.outputs o_busy o_done o_mag[0] o_mag[1] o_mag[2] o_mag[3] o_mag[4] o_mag[5] o_mag[6] o_mag[7] o_mag[8] o_mag[9] o_mag[10] o_mag[11] o_mag[12] o_phase[0] o_phase[1] o_phase[2] o_phase[3] o_phase[4] o_phase[5] o_phase[6] o_phase[7] o_phase[8] o_phase[9] o_phase[10] o_phase[11] o_phase[12] o_phase[13] o_phase[14] o_phase[15] o_phase[16] o_phase[17] o_phase[18] o_phase[19] o_phase[20] o_aux -.names $false -.names $true -1 -.names $undef -.names state[4] $abc$4719$new_n362 state[1] state[0] last_state -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names state[3] state[2] $abc$4719$new_n362 -00 1 -.names last_state ph[19] o_phase[19] $abc$4719$auto$rtlil.cc:2693:MuxGate$4488 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[18] o_phase[18] $abc$4719$auto$rtlil.cc:2693:MuxGate$4490 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[17] o_phase[17] $abc$4719$auto$rtlil.cc:2693:MuxGate$4492 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[16] o_phase[16] $abc$4719$auto$rtlil.cc:2693:MuxGate$4494 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[15] o_phase[15] $abc$4719$auto$rtlil.cc:2693:MuxGate$4496 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[14] o_phase[14] $abc$4719$auto$rtlil.cc:2693:MuxGate$4498 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[13] o_phase[13] $abc$4719$auto$rtlil.cc:2693:MuxGate$4500 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[12] o_phase[12] $abc$4719$auto$rtlil.cc:2693:MuxGate$4502 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[11] o_phase[11] $abc$4719$auto$rtlil.cc:2693:MuxGate$4504 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[10] o_phase[10] $abc$4719$auto$rtlil.cc:2693:MuxGate$4506 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[9] o_phase[9] $abc$4719$auto$rtlil.cc:2693:MuxGate$4508 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[8] o_phase[8] $abc$4719$auto$rtlil.cc:2693:MuxGate$4510 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[7] o_phase[7] $abc$4719$auto$rtlil.cc:2693:MuxGate$4512 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[6] o_phase[6] $abc$4719$auto$rtlil.cc:2693:MuxGate$4514 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[5] o_phase[5] $abc$4719$auto$rtlil.cc:2693:MuxGate$4516 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[4] o_phase[4] $abc$4719$auto$rtlil.cc:2693:MuxGate$4518 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[3] o_phase[3] $abc$4719$auto$rtlil.cc:2693:MuxGate$4520 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[2] o_phase[2] $abc$4719$auto$rtlil.cc:2693:MuxGate$4522 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[1] o_phase[1] $abc$4719$auto$rtlil.cc:2693:MuxGate$4524 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[0] o_phase[0] $abc$4719$auto$rtlil.cc:2693:MuxGate$4526 -001 1 -011 1 -110 1 -111 1 -.names last_state xv[19] xv[18] $abc$4719$new_n384 o_mag[11] $abc$4719$auto$rtlil.cc:2693:MuxGate$4528 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names xv[17] xv[16] $abc$4719$new_n385 $abc$4719$new_n384 -111 1 -.names xv[15] xv[14] $abc$4719$new_n386 $abc$4719$new_n385 -111 1 -.names xv[13] xv[12] $abc$4719$new_n387 $abc$4719$new_n386 -111 1 -.names xv[11] xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n387 -11111 1 -.names last_state xv[18] $abc$4719$new_n384 o_mag[10] $abc$4719$auto$rtlil.cc:2693:MuxGate$4530 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names last_state xv[17] xv[16] $abc$4719$new_n385 o_mag[9] $abc$4719$auto$rtlil.cc:2693:MuxGate$4532 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names last_state xv[16] $abc$4719$new_n385 o_mag[8] $abc$4719$auto$rtlil.cc:2693:MuxGate$4534 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names last_state xv[15] xv[14] $abc$4719$new_n386 o_mag[7] $abc$4719$auto$rtlil.cc:2693:MuxGate$4536 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names last_state xv[14] $abc$4719$new_n386 o_mag[6] $abc$4719$auto$rtlil.cc:2693:MuxGate$4538 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names last_state xv[13] xv[12] $abc$4719$new_n387 o_mag[5] $abc$4719$auto$rtlil.cc:2693:MuxGate$4540 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names last_state xv[12] $abc$4719$new_n387 o_mag[4] $abc$4719$auto$rtlil.cc:2693:MuxGate$4542 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names last_state $abc$4719$new_n396 o_mag[3] $abc$4719$auto$rtlil.cc:2693:MuxGate$4544 -001 1 -011 1 -110 1 -111 1 -.names xv[11] xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n396 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names last_state $abc$4719$new_n398 o_mag[2] $abc$4719$auto$rtlil.cc:2693:MuxGate$4546 -001 1 -011 1 -110 1 -111 1 -.names xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n398 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names last_state xv[9] xv[7] xv[8] o_mag[1] $abc$4719$auto$rtlil.cc:2693:MuxGate$4548 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names last_state xv[7] xv[8] o_mag[0] $abc$4719$new_n401 $abc$4719$auto$rtlil.cc:2693:MuxGate$4550 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -.names $abc$4719$new_n402 xv[2] xv[1] xv[0] $abc$4719$new_n401 -1000 1 -.names xv[6] xv[5] xv[4] xv[3] $abc$4719$new_n402 -0000 1 -.names last_state aux o_aux $abc$4719$auto$rtlil.cc:2693:MuxGate$4552 -001 1 -011 1 -110 1 -111 1 -.names last_state ph[20] o_phase[20] $abc$4719$auto$rtlil.cc:2693:MuxGate$4554 -001 1 -011 1 -110 1 -111 1 -.names last_state xv[20] $abc$4719$new_n406 o_mag[12] $abc$4719$auto$rtlil.cc:2693:MuxGate$4556 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names xv[19] xv[18] $abc$4719$new_n384 $abc$4719$new_n406 -111 1 -.names i_stb last_state idle $abc$4719$auto$rtlil.cc:2693:MuxGate$4558 -001 1 -010 1 -011 1 -.names i_stb idle $abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y -11 1 -.names $abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y i_aux aux $abc$4719$auto$rtlil.cc:2693:MuxGate$4560 -001 1 -011 1 -110 1 -111 1 -.names i_reset idle last_state $abc$4719$auto$opt_dff.cc:253:combine_resets$656 -001 1 -010 1 -011 1 -100 1 -101 1 -110 1 -111 1 -.names state[1] $abc$4719$auto$opt_dff.cc:253:combine_resets$904 $abc$4719$auto$opt_dff.cc:253:combine_resets$901 -00 1 -01 1 -11 1 -.names $abc$4719$new_n362 state[4] $abc$4719$auto$opt_dff.cc:253:combine_resets$904 -00 1 -01 1 -11 1 -.names state[3] state[4] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 -01 1 -10 1 -11 1 -.names i_xval[0] i_yval[0] $0\prex[20:0][6] -01 1 -10 1 -.names i_xval[12] i_xval[0] i_yval[12] $abc$4719$new_n418 $abc$4719$new_n419 $0\prey[20:0][7] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01101 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_yval[1] i_xval[1] i_xval[0] i_yval[0] $abc$4719$new_n418 -0001 1 -0010 1 -0011 1 -0100 1 -1000 1 -1101 1 -1110 1 -1111 1 -.names i_yval[1] i_xval[1] i_xval[0] i_yval[0] $abc$4719$new_n419 -0000 1 -0001 1 -0011 1 -0110 1 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$4719$new_n421 $abc$4719$new_n434 $abc$4719$new_n432 $0\prey[20:0][8] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_yval[12] i_xval[12] $abc$4719$new_n422 $abc$4719$new_n427 $abc$4719$new_n430 $abc$4719$new_n421 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n426 $abc$4719$new_n423 $abc$4719$new_n422 -00 1 -11 1 -.names i_yval[2] $abc$4719$new_n424 $abc$4719$new_n423 -00 1 -11 1 -.names i_xval[2] $abc$4719$new_n425 $abc$4719$new_n424 -00 1 -11 1 -.names i_xval[1] i_xval[0] $abc$4719$new_n425 -00 1 -.names i_xval[1] i_yval[1] i_xval[0] i_yval[0] $abc$4719$new_n426 -0001 1 -0100 1 -0101 1 -1101 1 -1110 1 -1111 1 -.names $abc$4719$new_n429 i_xval[1] i_yval[1] $abc$4719$new_n428 $abc$4719$new_n427 -0000 1 -0100 1 -0101 1 -0110 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names i_yval[0] i_xval[0] $abc$4719$new_n428 -10 1 -.names i_yval[2] i_xval[2] $abc$4719$new_n429 -00 1 -11 1 -.names $abc$4719$new_n431 $abc$4719$new_n429 $abc$4719$new_n430 -01 1 -10 1 -.names i_xval[0] i_yval[0] i_yval[1] i_xval[1] $abc$4719$new_n431 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names $abc$4719$new_n433 $abc$4719$new_n423 $abc$4719$new_n432 -00 1 -11 1 -.names i_xval[1] i_yval[1] i_xval[0] i_yval[0] $abc$4719$new_n433 -0011 1 -0110 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n434 -00 1 -.names $abc$4719$new_n445 i_xval[3] i_yval[3] $abc$4719$new_n444 $abc$4719$new_n436 $0\prey[20:0][9] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n437 $abc$4719$new_n440 $abc$4719$new_n442 $abc$4719$new_n436 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$4719$new_n438 i_yval[2] $abc$4719$new_n426 $abc$4719$new_n424 $abc$4719$new_n437 -0000 1 -0001 1 -0011 1 -0101 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names i_yval[3] $abc$4719$new_n439 $abc$4719$new_n438 -00 1 -11 1 -.names i_xval[3] $abc$4719$new_n425 i_xval[2] $abc$4719$new_n439 -000 1 -001 1 -011 1 -110 1 -.names $abc$4719$new_n441 $abc$4719$new_n438 $abc$4719$new_n440 -01 1 -10 1 -.names i_yval[2] $abc$4719$new_n433 $abc$4719$new_n424 $abc$4719$new_n441 -000 1 -001 1 -010 1 -100 1 -.names i_xval[3] i_yval[3] $abc$4719$new_n443 $abc$4719$new_n442 -001 1 -010 1 -100 1 -111 1 -.names i_yval[1] i_yval[2] i_xval[1] i_xval[2] $abc$4719$new_n428 $abc$4719$new_n443 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_yval[2] i_xval[2] $abc$4719$new_n431 $abc$4719$new_n444 -000 1 -001 1 -011 1 -101 1 -.names i_yval[12] i_xval[12] $abc$4719$new_n445 -10 1 -.names $abc$4719$new_n447 $abc$4719$new_n445 $abc$4719$new_n455 $0\prey[20:0][10] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n448 $abc$4719$new_n451 $abc$4719$new_n453 $abc$4719$new_n447 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n449 $abc$4719$new_n448 -000 1 -011 1 -101 1 -110 1 -.names i_yval[3] $abc$4719$new_n439 $abc$4719$new_n441 $abc$4719$new_n449 -000 1 -001 1 -011 1 -101 1 -.names i_xval[4] $abc$4719$new_n425 i_xval[3] i_xval[2] $abc$4719$new_n450 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n452 $abc$4719$new_n451 -001 1 -010 1 -100 1 -111 1 -.names i_yval[2] $abc$4719$new_n426 i_yval[3] $abc$4719$new_n439 $abc$4719$new_n424 $abc$4719$new_n452 -00100 1 -00101 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4719$new_n454 i_xval[3] i_yval[3] $abc$4719$new_n443 $abc$4719$new_n453 -0000 1 -0100 1 -0101 1 -0110 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names i_yval[4] i_xval[4] $abc$4719$new_n454 -00 1 -11 1 -.names $abc$4719$new_n454 i_xval[3] i_yval[3] $abc$4719$new_n444 $abc$4719$new_n455 -0000 1 -0001 1 -0011 1 -0101 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names $abc$4719$new_n457 $abc$4719$new_n445 $abc$4719$new_n466 $0\prey[20:0][11] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n458 $abc$4719$new_n462 $abc$4719$new_n464 $abc$4719$new_n457 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n459 $abc$4719$new_n458 -000 1 -011 1 -101 1 -110 1 -.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n449 $abc$4719$new_n459 -000 1 -001 1 -011 1 -101 1 -.names i_xval[5] $abc$4719$new_n461 $abc$4719$new_n460 -00 1 -11 1 -.names $abc$4719$new_n425 i_xval[4] i_xval[3] i_xval[2] $abc$4719$new_n461 -1000 1 -.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n463 $abc$4719$new_n462 -001 1 -010 1 -100 1 -111 1 -.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n452 $abc$4719$new_n463 -001 1 -100 1 -101 1 -111 1 -.names i_xval[5] i_yval[5] $abc$4719$new_n465 $abc$4719$new_n464 -001 1 -010 1 -100 1 -111 1 -.names i_yval[3] i_yval[4] i_xval[3] i_xval[4] $abc$4719$new_n443 $abc$4719$new_n465 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_xval[5] i_yval[5] $abc$4719$new_n467 $abc$4719$new_n466 -000 1 -011 1 -101 1 -110 1 -.names i_xval[3] i_yval[3] i_yval[4] i_xval[4] $abc$4719$new_n444 $abc$4719$new_n467 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$4719$new_n469 i_xval[12] $abc$4719$new_n474 i_yval[12] $0\prey[20:0][12] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1110 1 -.names i_yval[12] i_xval[12] $abc$4719$new_n470 $abc$4719$new_n472 $abc$4719$new_n473 $abc$4719$new_n469 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names i_yval[6] i_xval[6] $abc$4719$new_n471 $abc$4719$new_n461 i_xval[5] $abc$4719$new_n470 -00010 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01110 1 -10000 1 -10001 1 -10011 1 -10110 1 -11010 1 -11100 1 -11101 1 -11111 1 -.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n459 $abc$4719$new_n471 -000 1 -001 1 -011 1 -101 1 -.names i_yval[6] i_xval[6] i_xval[5] i_yval[5] $abc$4719$new_n467 $abc$4719$new_n472 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names i_yval[6] i_xval[6] i_xval[5] i_yval[5] $abc$4719$new_n465 $abc$4719$new_n473 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names i_yval[6] i_xval[6] $abc$4719$new_n475 $abc$4719$new_n461 i_xval[5] $abc$4719$new_n474 -00000 1 -00001 1 -00011 1 -00110 1 -01010 1 -01100 1 -01101 1 -01111 1 -10010 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11110 1 -.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n463 $abc$4719$new_n475 -001 1 -100 1 -101 1 -111 1 -.names $abc$4719$new_n477 $abc$4719$new_n445 $abc$4719$new_n485 $0\prey[20:0][13] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n478 $abc$4719$new_n481 $abc$4719$new_n483 $abc$4719$new_n477 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n479 $abc$4719$new_n478 -000 1 -011 1 -101 1 -110 1 -.names i_xval[6] $abc$4719$new_n461 i_xval[5] i_yval[6] $abc$4719$new_n471 $abc$4719$new_n479 -00001 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names i_xval[7] $abc$4719$new_n461 i_xval[6] i_xval[5] $abc$4719$new_n480 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n482 $abc$4719$new_n481 -001 1 -010 1 -100 1 -111 1 -.names i_xval[6] $abc$4719$new_n461 i_yval[6] i_xval[5] $abc$4719$new_n475 $abc$4719$new_n482 -00101 1 -00111 1 -01001 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names i_yval[7] i_xval[7] $abc$4719$new_n484 $abc$4719$new_n483 -001 1 -010 1 -100 1 -111 1 -.names i_yval[5] i_yval[6] i_xval[5] i_xval[6] $abc$4719$new_n465 $abc$4719$new_n484 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_yval[7] i_xval[7] $abc$4719$new_n486 $abc$4719$new_n485 -000 1 -011 1 -101 1 -110 1 -.names i_xval[5] i_yval[5] i_yval[6] i_xval[6] $abc$4719$new_n467 $abc$4719$new_n486 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$4719$new_n488 $abc$4719$new_n445 $abc$4719$new_n495 $0\prey[20:0][14] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n489 $abc$4719$new_n492 $abc$4719$new_n494 $abc$4719$new_n488 -00000 1 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$abc$4719$new_n486 $abc$4719$new_n505 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_yval[7] i_yval[8] i_xval[7] i_xval[8] $abc$4719$new_n484 $abc$4719$new_n507 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$4719$new_n509 $abc$4719$new_n445 $abc$4719$new_n517 $0\prey[20:0][16] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n510 $abc$4719$new_n514 $abc$4719$new_n516 $abc$4719$new_n509 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$4719$new_n512 $abc$4719$new_n511 $abc$4719$new_n510 -01 1 -10 1 -.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n499 $abc$4719$new_n511 -000 1 -001 1 -011 1 -101 1 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1 -.names i_yval[10] $abc$4719$new_n513 $abc$4719$new_n511 $abc$4719$new_n520 -000 1 -001 1 -011 1 -101 1 -.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n521 -00 1 -11 1 -.names i_xval[11] $abc$4719$new_n501 i_xval[10] i_xval[9] $abc$4719$new_n522 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names i_yval[12] i_xval[12] $abc$4719$new_n524 $abc$4719$new_n526 $abc$4719$new_n528 $abc$4719$new_n523 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$4719$new_n521 $abc$4719$new_n525 $abc$4719$new_n524 -00 1 -11 1 -.names i_yval[10] $abc$4719$new_n513 $abc$4719$new_n515 $abc$4719$new_n525 -001 1 -100 1 -101 1 -111 1 -.names i_yval[11] i_xval[11] $abc$4719$new_n527 $abc$4719$new_n526 -000 1 -011 1 -101 1 -110 1 -.names i_yval[9] i_xval[9] i_xval[10] i_yval[10] $abc$4719$new_n505 $abc$4719$new_n527 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_yval[11] i_xval[11] $abc$4719$new_n529 $abc$4719$new_n528 -001 1 -010 1 -100 1 -111 1 -.names i_yval[9] i_xval[9] i_xval[10] i_yval[10] $abc$4719$new_n507 $abc$4719$new_n529 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names i_xval[12] $abc$4719$new_n535 $abc$4719$new_n537 i_yval[12] $abc$4719$new_n967 $0\prey[20:0][18] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n520 $abc$4719$new_n533 -000 1 -001 1 -011 1 -101 1 -.names i_yval[11] i_xval[11] $abc$4719$new_n527 $abc$4719$new_n534 -000 1 -001 1 -011 1 -101 1 -.names $abc$4719$new_n501 i_xval[11] i_xval[10] i_xval[9] $abc$4719$new_n535 -1000 1 -.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n525 $abc$4719$new_n537 -001 1 -100 1 -101 1 -111 1 -.names $abc$4719$new_n967 i_xval[12] $abc$4719$new_n537 i_yval[12] $abc$4719$new_n535 $0\prey[20:0][19] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11100 1 -.names state[1] state[3] state[2] state[4] state[0] $\cordic_angle$rdreg[0]$d[0] -00001 1 -00011 1 -01000 1 -01001 1 -10001 1 -10100 1 -10101 1 -11001 1 -11101 1 -.names state[4] state[0] state[3] state[1] state[2] $\cordic_angle$rdreg[0]$d[1] -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -10000 1 -.names state[1] state[2] state[0] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[2] -0010 1 -0011 1 -0110 1 -0111 1 -1100 1 -1110 1 -1111 1 -.names state[3] state[1] state[0] state[2] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[3] -0001 1 -0011 1 -0101 1 -1000 1 -1001 1 -1101 1 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state[2] state[0] state[1] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[10] -000 1 -010 1 -110 1 -111 1 -.names state[2] state[0] state[1] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[11] -000 1 -010 1 -100 1 -101 1 -.names state[0] state[1] state[2] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[12] -000 1 -100 1 -101 1 -110 1 -.names state[1] state[0] state[2] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[13] -001 1 -010 1 -100 1 -.names cangle[0] ph[0] $abc$4719$procmux$562_Y[0] -01 1 -10 1 -.names cangle[1] ph[1] yv[20] ph[0] cangle[0] $abc$4719$procmux$562_Y[1] -00011 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11011 1 -11101 1 -.names yv[20] cangle[2] ph[2] $abc$4719$new_n559 $abc$4719$new_n558 $abc$4719$procmux$562_Y[2] -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names ph[0] cangle[0] cangle[1] ph[1] $abc$4719$new_n558 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names cangle[0] cangle[1] ph[0] ph[1] $abc$4719$new_n559 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0111 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names yv[20] cangle[3] ph[3] $abc$4719$new_n562 $abc$4719$new_n561 $abc$4719$procmux$562_Y[3] -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names cangle[2] ph[2] $abc$4719$new_n558 $abc$4719$new_n561 -000 1 -001 1 -011 1 -101 1 -.names ph[2] cangle[2] $abc$4719$new_n559 $abc$4719$new_n562 -001 1 -100 1 -101 1 -111 1 -.names yv[20] cangle[4] ph[4] $abc$4719$new_n565 $abc$4719$new_n564 $abc$4719$procmux$562_Y[4] -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names cangle[3] ph[3] $abc$4719$new_n561 $abc$4719$new_n564 -000 1 -001 1 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-1000 1 -1001 1 -1010 1 -1100 1 -.names ph[8] cangle[8] cangle[9] ph[9] $abc$4719$new_n575 $abc$4719$new_n582 -00000 1 -00010 1 -00011 1 -00110 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -.names cangle[11] ph[11] $abc$4719$new_n584 $abc$4719$procmux$562_Y[11] -001 1 -010 1 -100 1 -111 1 -.names yv[20] cangle[10] ph[10] $abc$4719$new_n582 $abc$4719$new_n579 $abc$4719$new_n584 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names yv[20] cangle[12] ph[12] $abc$4719$new_n589 $abc$4719$new_n586 $abc$4719$procmux$562_Y[12] -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$4719$new_n588 $abc$4719$new_n587 $abc$4719$new_n586 -10 1 -.names $abc$4719$new_n580 cangle[11] cangle[10] ph[10] ph[11] $abc$4719$new_n587 -10011 1 -10101 1 -11010 1 -11100 1 -.names cangle[10] ph[10] cangle[11] ph[11] $abc$4719$new_n581 $abc$4719$new_n588 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names cangle[10] cangle[11] ph[10] ph[11] $abc$4719$new_n582 $abc$4719$new_n589 -00000 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -10000 1 -10001 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names yv[20] cangle[13] ph[13] $abc$4719$new_n592 $abc$4719$new_n591 $abc$4719$procmux$562_Y[13] -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names cangle[12] ph[12] $abc$4719$new_n586 $abc$4719$new_n591 -000 1 -001 1 -011 1 -101 1 -.names cangle[12] ph[12] $abc$4719$new_n589 $abc$4719$new_n592 -001 1 -100 1 -101 1 -111 1 -.names yv[20] cangle[14] ph[14] $abc$4719$new_n595 $abc$4719$new_n594 $abc$4719$procmux$562_Y[14] -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names cangle[13] ph[13] $abc$4719$new_n591 $abc$4719$new_n594 -000 1 -001 1 -011 1 -101 1 -.names ph[13] cangle[13] $abc$4719$new_n592 $abc$4719$new_n595 -000 1 -100 1 -101 1 -110 1 -.names cangle[15] ph[15] $abc$4719$new_n597 $abc$4719$procmux$562_Y[15] -001 1 -010 1 -100 1 -111 1 -.names yv[20] cangle[14] ph[14] $abc$4719$new_n595 $abc$4719$new_n594 $abc$4719$new_n597 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names yv[20] cangle[16] ph[16] $abc$4719$new_n600 $abc$4719$new_n599 $abc$4719$procmux$562_Y[16] -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names cangle[14] ph[14] cangle[15] ph[15] $abc$4719$new_n594 $abc$4719$new_n599 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names cangle[14] cangle[15] ph[14] ph[15] $abc$4719$new_n595 $abc$4719$new_n600 -00000 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -10000 1 -10001 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names yv[20] cangle[17] ph[17] $abc$4719$new_n603 $abc$4719$new_n602 $abc$4719$procmux$562_Y[17] -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names cangle[16] ph[16] $abc$4719$new_n599 $abc$4719$new_n602 -000 1 -001 1 -011 1 -101 1 -.names cangle[16] ph[16] $abc$4719$new_n600 $abc$4719$new_n603 -001 1 -100 1 -101 1 -111 1 -.names ph[18] $abc$4719$new_n605 $abc$4719$procmux$562_Y[18] -00 1 -11 1 -.names yv[20] ph[17] cangle[17] $abc$4719$new_n603 $abc$4719$new_n602 $abc$4719$new_n605 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names pre_valid ph[19] $abc$4719$new_n608 $abc$4719$new_n607 preph[19] $0\ph[20:0][19] -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names ph[18] yv[20] cangle[17] ph[17] $abc$4719$new_n602 $abc$4719$new_n607 -10010 1 -10100 1 -10110 1 -10111 1 -.names yv[20] ph[18] cangle[17] ph[17] $abc$4719$new_n603 $abc$4719$new_n608 -10001 1 -10100 1 -10101 1 -10111 1 -.names pre_valid $abc$4719$new_n610 preph[20] $0\ph[20:0][20] -010 1 -011 1 -101 1 -111 1 -.names ph[20] ph[19] $abc$4719$new_n608 $abc$4719$new_n607 $abc$4719$new_n610 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names pre_valid yv[0] $abc$4719$new_n612 prey[0] $0\yv[20:0][0] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$4719$new_n613 $abc$4719$new_n619 state[4] $abc$4719$new_n616 $abc$4719$new_n612 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -.names state[4] state[3] state[2] xv[20] $abc$4719$new_n614 $abc$4719$new_n613 -10001 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[1] state[0] $abc$4719$new_n615 xv[19] xv[18] $abc$4719$new_n614 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] xv[17] xv[16] $abc$4719$new_n615 -000 1 -010 1 -100 1 -101 1 -.names state[2] state[3] $abc$4719$new_n617 $abc$4719$new_n616 -100 1 -.names state[1] state[0] $abc$4719$new_n618 xv[5] xv[4] $abc$4719$new_n617 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] xv[7] xv[6] $abc$4719$new_n618 -000 1 -010 1 -100 1 -101 1 -.names $abc$4719$new_n624 state[2] state[3] $abc$4719$new_n620 $abc$4719$new_n622 $abc$4719$new_n619 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -.names state[1] state[0] $abc$4719$new_n621 xv[11] xv[10] $abc$4719$new_n620 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] xv[9] xv[8] $abc$4719$new_n621 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4719$new_n623 xv[15] xv[14] $abc$4719$new_n622 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] xv[13] xv[12] $abc$4719$new_n623 -000 1 -010 1 -100 1 -101 1 -.names $abc$4719$new_n362 $abc$4719$new_n625 xv[0] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] $abc$4719$new_n624 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names state[1] state[0] xv[3] xv[1] xv[2] $abc$4719$new_n625 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid $abc$4719$new_n627 prey[1] $0\yv[20:0][1] -010 1 -011 1 -101 1 -111 1 -.names yv[1] $abc$4719$new_n1009 yv[0] yv[20] $abc$4719$new_n612 $abc$4719$new_n627 -00001 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11001 1 -11111 1 -.names state[1] state[0] $abc$4719$new_n631 xv[20] xv[19] $abc$4719$new_n630 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] xv[18] xv[17] $abc$4719$new_n631 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4719$new_n634 xv[12] xv[11] $abc$4719$new_n633 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] xv[10] xv[9] $abc$4719$new_n634 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4719$new_n636 xv[16] xv[15] $abc$4719$new_n635 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] xv[14] xv[13] $abc$4719$new_n636 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4719$new_n639 xv[6] xv[5] $abc$4719$new_n638 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] xv[8] xv[7] $abc$4719$new_n639 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4719$new_n642 xv[2] xv[1] $abc$4719$new_n641 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] xv[4] xv[3] $abc$4719$new_n642 -000 1 -010 1 -100 1 -101 1 -.names yv[0] $abc$4719$new_n613 $abc$4719$new_n616 $abc$4719$new_n619 state[4] $abc$4719$new_n646 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -.names yv[0] $abc$4719$new_n613 $abc$4719$new_n616 $abc$4719$new_n619 state[4] $abc$4719$new_n648 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$4719$new_n657 $abc$4719$new_n654 $abc$4719$new_n650 $abc$4719$new_n649 -000 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n653 $abc$4719$new_n652 $abc$4719$new_n651 state[2] $abc$4719$new_n650 -00000 1 -00010 1 -00011 1 -.names state[1] $abc$4719$new_n621 $abc$4719$new_n618 $abc$4719$new_n651 -001 1 -011 1 -110 1 -111 1 -.names state[0] state[2] state[1] xv[3] xv[2] $abc$4719$new_n652 -00001 1 -00011 1 -10010 1 -10011 1 -.names state[1] state[0] state[2] xv[5] xv[4] $abc$4719$new_n653 -10001 1 -10011 1 -11010 1 -11011 1 -.names state[3] state[2] state[4] $abc$4719$new_n655 $abc$4719$new_n656 $abc$4719$new_n654 -10010 1 -10011 1 -11001 1 -11011 1 -.names state[1] state[0] $abc$4719$new_n623 xv[11] xv[10] $abc$4719$new_n655 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] state[0] $abc$4719$new_n615 xv[15] xv[14] $abc$4719$new_n656 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[4] state[3] state[2] xv[20] $abc$4719$new_n658 $abc$4719$new_n657 -10001 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[1] state[0] xv[20] xv[19] xv[18] $abc$4719$new_n658 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid yv[3] $abc$4719$new_n976 $abc$4719$new_n660 prey[3] $0\yv[20:0][3] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[20] $abc$4719$new_n661 $abc$4719$new_n974 $abc$4719$new_n660 -000 1 -010 1 -100 1 -101 1 -.names yv[1] $abc$4719$new_n1009 yv[2] $abc$4719$new_n649 $abc$4719$new_n648 $abc$4719$new_n661 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names state[4] state[3] $abc$4719$new_n667 $abc$4719$new_n670 xv[20] $abc$4719$new_n666 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names state[2] $abc$4719$new_n668 $abc$4719$new_n669 $abc$4719$new_n667 -010 1 -011 1 -101 1 -111 1 -.names state[1] state[0] $abc$4719$new_n636 xv[12] xv[11] $abc$4719$new_n668 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] state[0] $abc$4719$new_n631 xv[16] xv[15] $abc$4719$new_n669 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[2] $abc$4719$new_n671 xv[20] $abc$4719$new_n670 -010 1 -011 1 -100 1 -110 1 -.names state[1] state[0] xv[20] xv[19] $abc$4719$new_n671 -0000 1 -0010 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names state[1] $abc$4719$new_n634 $abc$4719$new_n639 $abc$4719$new_n672 -001 1 -011 1 -110 1 -111 1 -.names pre_valid yv[4] $abc$4719$new_n677 $abc$4719$new_n676 prey[4] $0\yv[20:0][4] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[3] yv[20] $abc$4719$new_n976 $abc$4719$new_n974 $abc$4719$new_n661 $abc$4719$new_n676 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names state[4] $abc$4719$new_n678 $abc$4719$new_n679 xv[20] $abc$4719$new_n677 -0010 1 -0011 1 -1000 1 -1010 1 -.names state[3] state[2] state[4] $abc$4719$new_n614 $abc$4719$new_n622 $abc$4719$new_n678 -10000 1 -10010 1 -11000 1 -11001 1 -.names state[2] state[3] $abc$4719$new_n620 $abc$4719$new_n617 $abc$4719$new_n679 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names pre_valid $abc$4719$new_n681 prey[5] $0\yv[20:0][5] -000 1 -001 1 -101 1 -111 1 -.names yv[5] $abc$4719$new_n684 yv[20] $abc$4719$new_n683 $abc$4719$new_n682 $abc$4719$new_n681 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$4719$new_n661 yv[3] yv[4] $abc$4719$new_n677 $abc$4719$new_n976 $abc$4719$new_n682 -00000 1 -00010 1 -00011 1 -00110 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11110 1 -.names yv[3] $abc$4719$new_n974 yv[4] $abc$4719$new_n677 $abc$4719$new_n976 $abc$4719$new_n683 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[4] $abc$4719$new_n686 xv[20] $abc$4719$new_n685 state[3] $abc$4719$new_n684 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[2] $abc$4719$new_n630 $abc$4719$new_n635 $abc$4719$new_n685 -001 1 -011 1 -110 1 -111 1 -.names state[2] state[3] $abc$4719$new_n633 $abc$4719$new_n638 $abc$4719$new_n686 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names yv[6] $abc$4719$new_n692 $abc$4719$new_n691 -01 1 -10 1 -.names state[4] $abc$4719$new_n694 xv[20] $abc$4719$new_n693 state[3] $abc$4719$new_n692 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[2] $abc$4719$new_n656 $abc$4719$new_n658 $abc$4719$new_n693 -010 1 -011 1 -101 1 -111 1 -.names state[2] state[3] $abc$4719$new_n651 $abc$4719$new_n655 $abc$4719$new_n694 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names pre_valid yv[7] $abc$4719$new_n700 $abc$4719$new_n696 prey[7] $0\yv[20:0][7] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[20] $abc$4719$new_n697 $abc$4719$new_n699 $abc$4719$new_n698 $abc$4719$new_n696 -0000 1 -0001 1 -0010 1 -0011 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names yv[5] $abc$4719$new_n684 yv[6] $abc$4719$new_n692 $abc$4719$new_n683 $abc$4719$new_n697 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4719$new_n691 yv[5] $abc$4719$new_n684 $abc$4719$new_n682 $abc$4719$new_n698 -0000 1 -0100 1 -0101 1 -0110 1 -.names yv[6] $abc$4719$new_n692 $abc$4719$new_n699 -10 1 -.names state[4] $abc$4719$new_n702 xv[20] $abc$4719$new_n701 state[3] $abc$4719$new_n700 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[2] $abc$4719$new_n669 $abc$4719$new_n671 $abc$4719$new_n701 -010 1 -011 1 -101 1 -111 1 -.names state[2] state[3] $abc$4719$new_n672 $abc$4719$new_n668 $abc$4719$new_n702 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names pre_valid yv[8] $abc$4719$new_n707 $abc$4719$new_n704 prey[8] $0\yv[20:0][8] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[7] yv[20] $abc$4719$new_n696 $abc$4719$new_n700 $abc$4719$new_n704 -0001 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -.names $abc$4719$new_n699 $abc$4719$new_n700 yv[7] $abc$4719$new_n706 -000 1 -010 1 -011 1 -.names $abc$4719$new_n708 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n620 $abc$4719$new_n622 $abc$4719$new_n707 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[3] state[2] state[4] xv[20] $abc$4719$new_n614 $abc$4719$new_n708 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names pre_valid $abc$4719$new_n710 prey[9] $0\yv[20:0][9] -010 1 -011 1 -101 1 -111 1 -.names yv[9] $abc$4719$new_n714 yv[20] $abc$4719$new_n713 $abc$4719$new_n711 $abc$4719$new_n710 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01110 1 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names yv[8] $abc$4719$new_n707 $abc$4719$new_n706 $abc$4719$new_n698 $abc$4719$new_n712 $abc$4719$new_n711 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$4719$new_n700 yv[7] $abc$4719$new_n712 -10 1 -.names yv[7] $abc$4719$new_n700 yv[8] $abc$4719$new_n707 $abc$4719$new_n697 $abc$4719$new_n713 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4719$new_n715 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n633 $abc$4719$new_n635 $abc$4719$new_n714 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[3] state[2] state[4] xv[20] $abc$4719$new_n630 $abc$4719$new_n715 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n721 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n655 $abc$4719$new_n656 $abc$4719$new_n720 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[3] state[2] state[4] xv[20] $abc$4719$new_n658 $abc$4719$new_n721 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names pre_valid $abc$4719$new_n723 prey[11] $0\yv[20:0][11] -010 1 -011 1 -101 1 -111 1 -.names yv[11] $abc$4719$new_n726 yv[20] $abc$4719$new_n725 $abc$4719$new_n724 $abc$4719$new_n723 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01110 1 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$4719$new_n714 yv[9] yv[10] $abc$4719$new_n720 $abc$4719$new_n711 $abc$4719$new_n724 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names yv[9] $abc$4719$new_n714 yv[10] $abc$4719$new_n720 $abc$4719$new_n713 $abc$4719$new_n725 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[4] state[3] xv[20] $abc$4719$new_n667 $abc$4719$new_n670 $abc$4719$new_n726 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid yv[12] $abc$4719$new_n729 $abc$4719$new_n728 prey[12] $0\yv[20:0][12] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[11] $abc$4719$new_n726 yv[20] $abc$4719$new_n725 $abc$4719$new_n724 $abc$4719$new_n728 -00101 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 state[2] xv[20] $abc$4719$new_n614 $abc$4719$new_n622 $abc$4719$new_n729 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid $abc$4719$new_n731 prey[13] $0\yv[20:0][13] -000 1 -001 1 -101 1 -111 1 -.names yv[13] $abc$4719$new_n734 yv[20] $abc$4719$new_n733 $abc$4719$new_n732 $abc$4719$new_n731 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$4719$new_n726 yv[11] yv[12] $abc$4719$new_n729 $abc$4719$new_n724 $abc$4719$new_n732 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names yv[11] $abc$4719$new_n726 yv[12] $abc$4719$new_n729 $abc$4719$new_n725 $abc$4719$new_n733 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n685 xv[20] $abc$4719$new_n734 -010 1 -011 1 -100 1 -110 1 -.names yv[13] $abc$4719$new_n734 $abc$4719$new_n732 $abc$4719$new_n737 -000 1 -100 1 -101 1 -110 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n693 xv[20] $abc$4719$new_n739 -010 1 -011 1 -100 1 -110 1 -.names pre_valid yv[15] $abc$4719$new_n745 $abc$4719$new_n741 prey[15] $0\yv[20:0][15] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[20] $abc$4719$new_n742 $abc$4719$new_n743 $abc$4719$new_n744 $abc$4719$new_n737 $abc$4719$new_n741 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names yv[13] $abc$4719$new_n734 yv[14] $abc$4719$new_n739 $abc$4719$new_n733 $abc$4719$new_n742 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names $abc$4719$new_n739 yv[14] $abc$4719$new_n743 -10 1 -.names yv[14] $abc$4719$new_n739 $abc$4719$new_n744 -10 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n701 xv[20] $abc$4719$new_n745 -010 1 -011 1 -100 1 -110 1 -.names pre_valid yv[16] $abc$4719$new_n750 $abc$4719$new_n747 prey[16] $0\yv[20:0][16] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[15] yv[20] $abc$4719$new_n745 $abc$4719$new_n742 $abc$4719$new_n748 $abc$4719$new_n747 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$4719$new_n749 yv[13] $abc$4719$new_n734 $abc$4719$new_n732 $abc$4719$new_n744 $abc$4719$new_n748 -10000 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$4719$new_n743 $abc$4719$new_n745 yv[15] $abc$4719$new_n749 -000 1 -001 1 -011 1 -.names xv[20] state[3] state[2] state[4] $abc$4719$new_n614 $abc$4719$new_n750 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -.names pre_valid yv[17] $abc$4719$new_n755 $abc$4719$new_n752 prey[17] $0\yv[20:0][17] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[20] $abc$4719$new_n753 $abc$4719$new_n754 $abc$4719$new_n752 -000 1 -010 1 -100 1 -101 1 -.names $abc$4719$new_n748 yv[16] $abc$4719$new_n750 yv[15] $abc$4719$new_n745 $abc$4719$new_n753 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names yv[15] $abc$4719$new_n745 yv[16] $abc$4719$new_n750 $abc$4719$new_n742 $abc$4719$new_n754 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names xv[20] state[3] state[2] state[4] $abc$4719$new_n630 $abc$4719$new_n755 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -.names pre_valid yv[18] $abc$4719$new_n758 $abc$4719$new_n757 prey[18] $0\yv[20:0][18] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[17] $abc$4719$new_n755 yv[20] $abc$4719$new_n754 $abc$4719$new_n753 $abc$4719$new_n757 -00101 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names xv[20] state[3] state[2] state[4] $abc$4719$new_n658 $abc$4719$new_n758 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -.names pre_valid yv[19] $abc$4719$new_n763 $abc$4719$new_n760 prey[19] $0\yv[20:0][19] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[20] $abc$4719$new_n761 $abc$4719$new_n762 $abc$4719$new_n760 -000 1 -001 1 -100 1 -110 1 -.names yv[17] $abc$4719$new_n755 yv[18] $abc$4719$new_n758 $abc$4719$new_n754 $abc$4719$new_n761 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4719$new_n755 yv[17] yv[18] $abc$4719$new_n758 $abc$4719$new_n753 $abc$4719$new_n762 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names state[3] state[4] xv[20] $abc$4719$new_n670 $abc$4719$new_n763 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names pre_valid xv[20] $abc$4719$new_n765 prey[20] $0\yv[20:0][20] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names yv[20] $abc$4719$new_n763 yv[19] $abc$4719$new_n762 $abc$4719$new_n761 $abc$4719$new_n765 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01010 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names pre_valid xv[0] $abc$4719$new_n767 prex[0] $0\xv[20:0][0] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n767 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -.names state[2] $abc$4719$new_n769 yv[20] $abc$4719$new_n768 -010 1 -011 1 -100 1 -110 1 -.names state[1] state[0] $abc$4719$new_n770 yv[19] yv[18] $abc$4719$new_n769 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] yv[17] yv[16] $abc$4719$new_n770 -000 1 -010 1 -100 1 -101 1 -.names $abc$4719$new_n777 state[4] $abc$4719$new_n779 $abc$4719$new_n772 state[3] $abc$4719$new_n771 -00000 1 -00010 1 -00011 1 -.names state[2] $abc$4719$new_n774 $abc$4719$new_n773 $abc$4719$new_n776 $abc$4719$new_n775 $abc$4719$new_n772 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10100 1 -11000 1 -11100 1 -.names state[0] state[1] yv[9] yv[8] $abc$4719$new_n773 -0001 1 -0011 1 -1010 1 -1011 1 -.names state[1] state[0] yv[11] yv[10] $abc$4719$new_n774 -1001 1 -1011 1 -1110 1 -1111 1 -.names state[0] state[1] yv[13] yv[12] $abc$4719$new_n775 -0001 1 -0011 1 -1010 1 -1011 1 -.names state[1] state[0] yv[15] yv[14] $abc$4719$new_n776 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$4719$new_n362 $abc$4719$new_n778 yv[0] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] $abc$4719$new_n777 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names state[1] state[0] yv[3] yv[1] yv[2] $abc$4719$new_n778 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[2] state[1] state[3] $abc$4719$new_n780 $abc$4719$new_n781 $abc$4719$new_n779 -10000 1 -10001 1 -11000 1 -11010 1 -.names state[0] yv[5] yv[4] $abc$4719$new_n780 -000 1 -010 1 -100 1 -101 1 -.names state[0] yv[7] yv[6] $abc$4719$new_n781 -000 1 -010 1 -100 1 -101 1 -.names state[4] state[3] yv[20] $abc$4719$new_n782 -100 1 -101 1 -110 1 -.names pre_valid $abc$4719$new_n784 prex[1] $0\xv[20:0][1] -010 1 -011 1 -101 1 -111 1 -.names xv[1] $abc$4719$new_n984 xv[0] yv[20] $abc$4719$new_n767 $abc$4719$new_n784 -00011 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11011 1 -11101 1 -.names state[1] state[0] $abc$4719$new_n788 yv[12] yv[11] $abc$4719$new_n787 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] yv[10] yv[9] $abc$4719$new_n788 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4719$new_n790 yv[16] yv[15] $abc$4719$new_n789 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] yv[14] yv[13] $abc$4719$new_n790 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4719$new_n793 yv[6] yv[5] $abc$4719$new_n792 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] yv[8] yv[7] $abc$4719$new_n793 -000 1 -010 1 -100 1 -101 1 -.names state[4] state[3] state[2] yv[20] $abc$4719$new_n795 $abc$4719$new_n794 -10001 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[1] state[0] $abc$4719$new_n796 yv[20] yv[19] $abc$4719$new_n795 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[0] yv[18] yv[17] $abc$4719$new_n796 -000 1 -010 1 -100 1 -101 1 -.names state[4] $abc$4719$new_n798 $abc$4719$new_n362 $abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[16] yv[2] $abc$4719$new_n797 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names state[1] state[0] yv[4] yv[3] yv[1] $abc$4719$new_n798 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid xv[2] $abc$4719$new_n801 $abc$4719$new_n800 prex[2] $0\xv[20:0][2] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[1] $abc$4719$new_n767 xv[0] yv[20] $abc$4719$new_n984 $abc$4719$new_n800 -00011 1 -00111 1 -01010 1 -01011 1 -01101 1 -01111 1 -10001 1 -10101 1 -11001 1 -11011 1 -11100 1 -11101 1 -.names $abc$4719$new_n810 $abc$4719$new_n986 $abc$4719$new_n802 $abc$4719$new_n801 -000 1 -.names state[3] state[2] state[4] $abc$4719$new_n803 $abc$4719$new_n805 $abc$4719$new_n802 -10000 1 -10001 1 -11000 1 -11010 1 -.names state[1] state[0] $abc$4719$new_n804 yv[11] yv[10] $abc$4719$new_n803 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[0] yv[13] yv[12] $abc$4719$new_n804 -000 1 -010 1 -100 1 -101 1 -.names state[1] state[0] $abc$4719$new_n770 yv[15] yv[14] $abc$4719$new_n805 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] state[0] $abc$4719$new_n781 yv[9] yv[8] $abc$4719$new_n807 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names state[4] state[3] state[2] yv[20] $abc$4719$new_n811 $abc$4719$new_n810 -10000 1 -10010 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names state[1] state[0] yv[20] yv[19] yv[18] $abc$4719$new_n811 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid $abc$4719$new_n813 prex[3] $0\xv[20:0][3] -010 1 -011 1 -101 1 -111 1 -.names yv[20] xv[3] $abc$4719$new_n992 $abc$4719$new_n818 $abc$4719$new_n988 $abc$4719$new_n813 -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names xv[0] $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n815 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -.names $abc$4719$new_n984 xv[1] xv[2] $abc$4719$new_n801 $abc$4719$new_n819 $abc$4719$new_n818 -00000 1 -00001 1 -00011 1 -00101 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11011 1 -11101 1 -.names xv[0] $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n819 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -.names state[2] $abc$4719$new_n823 yv[20] $abc$4719$new_n822 -010 1 -011 1 -100 1 -110 1 -.names state[1] state[0] yv[20] yv[19] $abc$4719$new_n823 -0000 1 -0010 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names state[1] $abc$4719$new_n788 $abc$4719$new_n793 $abc$4719$new_n825 -001 1 -011 1 -110 1 -111 1 -.names state[2] $abc$4719$new_n829 $abc$4719$new_n830 $abc$4719$new_n828 -010 1 -011 1 -101 1 -111 1 -.names state[1] state[0] $abc$4719$new_n790 yv[12] yv[11] $abc$4719$new_n829 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[1] state[0] $abc$4719$new_n796 yv[16] yv[15] $abc$4719$new_n830 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid xv[4] $abc$4719$new_n995 $abc$4719$new_n832 prex[4] $0\xv[20:0][4] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[3] $abc$4719$new_n992 yv[20] $abc$4719$new_n818 $abc$4719$new_n988 $abc$4719$new_n832 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names state[2] $abc$4719$new_n769 $abc$4719$new_n835 $abc$4719$new_n834 -001 1 -011 1 -110 1 -111 1 -.names $abc$4719$new_n776 $abc$4719$new_n775 $abc$4719$new_n835 -00 1 -.names pre_valid $abc$4719$new_n840 prex[5] $0\xv[20:0][5] -000 1 -001 1 -101 1 -111 1 -.names yv[20] xv[5] $abc$4719$new_n843 $abc$4719$new_n842 $abc$4719$new_n841 $abc$4719$new_n840 -00000 1 -00010 1 -00101 1 -00111 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names xv[3] $abc$4719$new_n992 xv[4] $abc$4719$new_n995 $abc$4719$new_n988 $abc$4719$new_n841 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01111 1 -10001 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -.names $abc$4719$new_n992 xv[3] xv[4] $abc$4719$new_n995 $abc$4719$new_n818 $abc$4719$new_n842 -00000 1 -00001 1 -00011 1 -00101 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11011 1 -11101 1 -.names state[4] $abc$4719$new_n845 yv[20] $abc$4719$new_n844 state[3] $abc$4719$new_n843 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[2] $abc$4719$new_n789 $abc$4719$new_n795 $abc$4719$new_n844 -010 1 -011 1 -101 1 -111 1 -.names state[2] state[3] $abc$4719$new_n787 $abc$4719$new_n792 $abc$4719$new_n845 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names state[4] $abc$4719$new_n852 yv[20] $abc$4719$new_n851 state[3] $abc$4719$new_n850 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[2] $abc$4719$new_n805 $abc$4719$new_n811 $abc$4719$new_n851 -010 1 -011 1 -101 1 -111 1 -.names state[2] state[3] $abc$4719$new_n803 $abc$4719$new_n807 $abc$4719$new_n852 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names pre_valid $abc$4719$new_n854 prex[7] $0\xv[20:0][7] -010 1 -011 1 -101 1 -111 1 -.names xv[7] $abc$4719$new_n857 yv[20] $abc$4719$new_n856 $abc$4719$new_n855 $abc$4719$new_n854 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01101 1 -01111 1 -10000 1 -10001 1 -10101 1 -10111 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names xv[5] $abc$4719$new_n843 xv[6] $abc$4719$new_n850 $abc$4719$new_n842 $abc$4719$new_n855 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$4719$new_n843 xv[5] xv[6] $abc$4719$new_n850 $abc$4719$new_n841 $abc$4719$new_n856 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names state[4] $abc$4719$new_n859 yv[20] $abc$4719$new_n858 state[3] $abc$4719$new_n857 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[2] $abc$4719$new_n830 $abc$4719$new_n823 $abc$4719$new_n858 -010 1 -011 1 -101 1 -111 1 -.names state[2] state[3] $abc$4719$new_n825 $abc$4719$new_n829 $abc$4719$new_n859 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names state[4] state[3] yv[20] $abc$4719$new_n768 $abc$4719$new_n772 $abc$4719$new_n864 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid $abc$4719$new_n866 prex[9] $0\xv[20:0][9] -010 1 -011 1 -101 1 -111 1 -.names xv[9] $abc$4719$new_n869 yv[20] $abc$4719$new_n868 $abc$4719$new_n867 $abc$4719$new_n866 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names xv[7] $abc$4719$new_n857 xv[8] $abc$4719$new_n864 $abc$4719$new_n855 $abc$4719$new_n867 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[7] xv[8] $abc$4719$new_n857 $abc$4719$new_n864 $abc$4719$new_n856 $abc$4719$new_n868 -00000 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -10000 1 -10001 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$4719$new_n870 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n787 $abc$4719$new_n789 $abc$4719$new_n869 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[3] state[2] state[4] yv[20] $abc$4719$new_n795 $abc$4719$new_n870 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names pre_valid xv[10] $abc$4719$new_n873 $abc$4719$new_n872 prex[10] $0\xv[20:0][10] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[9] yv[20] $abc$4719$new_n869 $abc$4719$new_n868 $abc$4719$new_n867 $abc$4719$new_n872 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names $abc$4719$new_n874 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n803 $abc$4719$new_n805 $abc$4719$new_n873 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[3] state[2] state[4] yv[20] $abc$4719$new_n811 $abc$4719$new_n874 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names pre_valid $abc$4719$new_n876 prex[11] $0\xv[20:0][11] -010 1 -011 1 -101 1 -111 1 -.names xv[11] $abc$4719$new_n879 yv[20] $abc$4719$new_n878 $abc$4719$new_n877 $abc$4719$new_n876 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names xv[9] $abc$4719$new_n869 xv[10] $abc$4719$new_n873 $abc$4719$new_n867 $abc$4719$new_n877 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[9] xv[10] $abc$4719$new_n869 $abc$4719$new_n873 $abc$4719$new_n868 $abc$4719$new_n878 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names state[4] state[3] yv[20] $abc$4719$new_n828 $abc$4719$new_n822 $abc$4719$new_n879 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names pre_valid xv[12] $abc$4719$new_n882 $abc$4719$new_n881 prex[12] $0\xv[20:0][12] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[11] yv[20] $abc$4719$new_n879 $abc$4719$new_n878 $abc$4719$new_n877 $abc$4719$new_n881 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n834 yv[20] $abc$4719$new_n882 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4719$new_n884 prex[13] $0\xv[20:0][13] -000 1 -001 1 -101 1 -111 1 -.names xv[13] $abc$4719$new_n887 yv[20] $abc$4719$new_n886 $abc$4719$new_n885 $abc$4719$new_n884 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01110 1 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names xv[11] $abc$4719$new_n879 xv[12] $abc$4719$new_n882 $abc$4719$new_n877 $abc$4719$new_n885 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[11] xv[12] $abc$4719$new_n879 $abc$4719$new_n882 $abc$4719$new_n878 $abc$4719$new_n886 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n844 yv[20] $abc$4719$new_n887 -010 1 -011 1 -100 1 -110 1 -.names pre_valid $abc$4719$new_n889 prex[14] $0\xv[20:0][14] -000 1 -001 1 -101 1 -111 1 -.names $abc$4719$new_n892 yv[20] $abc$4719$new_n891 $abc$4719$new_n890 $abc$4719$new_n889 -0010 1 -0011 1 -0100 1 -0110 1 -1000 1 -1001 1 -1101 1 -1111 1 -.names xv[13] $abc$4719$new_n887 $abc$4719$new_n885 $abc$4719$new_n890 -010 1 -100 1 -110 1 -111 1 -.names xv[13] $abc$4719$new_n887 $abc$4719$new_n886 $abc$4719$new_n891 -001 1 -100 1 -101 1 -111 1 -.names xv[14] $abc$4719$new_n893 $abc$4719$new_n892 -01 1 -10 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n851 yv[20] $abc$4719$new_n893 -010 1 -011 1 -100 1 -110 1 -.names pre_valid xv[15] $abc$4719$new_n896 $abc$4719$new_n895 prex[15] $0\xv[20:0][15] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[14] yv[20] $abc$4719$new_n893 $abc$4719$new_n891 $abc$4719$new_n890 $abc$4719$new_n895 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n858 yv[20] $abc$4719$new_n896 -010 1 -011 1 -100 1 -110 1 -.names $abc$4719$new_n892 xv[13] $abc$4719$new_n887 $abc$4719$new_n886 $abc$4719$new_n900 -0001 1 -0100 1 -0101 1 -0111 1 -.names $abc$4719$new_n896 xv[15] $abc$4719$new_n901 -10 1 -.names xv[14] $abc$4719$new_n893 xv[15] $abc$4719$new_n896 $abc$4719$new_n902 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names $abc$4719$new_n906 xv[13] $abc$4719$new_n887 $abc$4719$new_n885 $abc$4719$new_n892 $abc$4719$new_n904 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names xv[14] $abc$4719$new_n893 xv[15] $abc$4719$new_n896 $abc$4719$new_n906 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n768 yv[20] $abc$4719$new_n907 -010 1 -011 1 -100 1 -110 1 -.names pre_valid xv[17] $abc$4719$new_n912 $abc$4719$new_n909 prex[17] $0\xv[20:0][17] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[20] $abc$4719$new_n910 $abc$4719$new_n911 $abc$4719$new_n909 -010 1 -011 1 -100 1 -110 1 -.names xv[16] $abc$4719$new_n907 $abc$4719$new_n902 $abc$4719$new_n900 $abc$4719$new_n901 $abc$4719$new_n910 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$4719$new_n904 xv[16] $abc$4719$new_n907 xv[15] $abc$4719$new_n896 $abc$4719$new_n911 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 yv[20] $abc$4719$new_n795 $abc$4719$new_n912 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names pre_valid xv[18] $abc$4719$new_n915 $abc$4719$new_n914 prex[18] $0\xv[20:0][18] -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[17] yv[20] $abc$4719$new_n912 $abc$4719$new_n911 $abc$4719$new_n910 $abc$4719$new_n914 -00000 1 -00010 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11010 1 -11011 1 -.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 yv[20] $abc$4719$new_n811 $abc$4719$new_n915 -0001 1 -0011 1 -0100 1 -0101 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names pre_valid xv[19] $abc$4719$new_n920 $abc$4719$new_n917 prex[19] $0\xv[20:0][19] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[20] $abc$4719$new_n918 $abc$4719$new_n919 $abc$4719$new_n917 -001 1 -011 1 -110 1 -111 1 -.names xv[17] $abc$4719$new_n912 xv[18] $abc$4719$new_n915 $abc$4719$new_n911 $abc$4719$new_n918 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4719$new_n912 xv[17] xv[18] $abc$4719$new_n915 $abc$4719$new_n910 $abc$4719$new_n919 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n822 yv[20] $abc$4719$new_n920 -010 1 -011 1 -100 1 -110 1 -.names pre_valid xv[20] $abc$4719$new_n922 prex[20] $0\xv[20:0][20] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names yv[20] xv[19] $abc$4719$new_n920 $abc$4719$new_n919 $abc$4719$new_n918 $abc$4719$new_n922 -00000 1 -00001 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10101 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_xval[12] i_yval[12] $0\preph[20:0][19] -01 1 -10 1 -.names state[1] state[0] $auto$alumacc.cc:485:replace_alu$735.Y[1] -01 1 -10 1 -.names i_yval[12] i_xval[0] i_xval[12] $abc$4719$new_n418 $abc$4719$new_n419 $0\prex[20:0][7] -00000 1 -00010 1 -00100 1 -00110 1 -01001 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$4719$new_n928 $abc$4719$new_n434 $abc$4719$new_n430 $0\prex[20:0][8] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_yval[12] i_xval[12] $abc$4719$new_n422 $abc$4719$new_n432 $abc$4719$new_n427 $abc$4719$new_n928 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4719$new_n933 $abc$4719$new_n445 $abc$4719$new_n453 $0\prex[20:0][10] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n448 $abc$4719$new_n451 $abc$4719$new_n455 $abc$4719$new_n933 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n935 $abc$4719$new_n445 $abc$4719$new_n464 $0\prex[20:0][11] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n458 $abc$4719$new_n462 $abc$4719$new_n466 $abc$4719$new_n935 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n937 $abc$4719$new_n445 $abc$4719$new_n473 $0\prex[20:0][12] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n470 $abc$4719$new_n474 $abc$4719$new_n472 $abc$4719$new_n937 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n939 $abc$4719$new_n445 $abc$4719$new_n483 $0\prex[20:0][13] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n478 $abc$4719$new_n481 $abc$4719$new_n485 $abc$4719$new_n939 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n941 $abc$4719$new_n445 $abc$4719$new_n494 $0\prex[20:0][14] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n489 $abc$4719$new_n492 $abc$4719$new_n495 $abc$4719$new_n941 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n445 i_yval[9] i_xval[9] $abc$4719$new_n507 $abc$4719$new_n943 $0\prex[20:0][15] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n498 $abc$4719$new_n502 $abc$4719$new_n504 $abc$4719$new_n943 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n945 $abc$4719$new_n445 $abc$4719$new_n516 $0\prex[20:0][16] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n510 $abc$4719$new_n514 $abc$4719$new_n517 $abc$4719$new_n945 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$4719$new_n947 $abc$4719$new_n445 $abc$4719$new_n528 $0\prex[20:0][17] -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n519 $abc$4719$new_n524 $abc$4719$new_n526 $abc$4719$new_n947 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n535 $abc$4719$new_n537 $0\prex[20:0][19] -1110 1 -.names state[2] state[1] state[0] $auto$alumacc.cc:485:replace_alu$735.Y[2] -011 1 -100 1 -101 1 -110 1 -.names state[3] state[1] state[0] state[2] $auto$alumacc.cc:485:replace_alu$735.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names state[4] state[1] state[0] state[3] state[2] $auto$alumacc.cc:485:replace_alu$735.Y[4] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names idle o_busy -0 1 -.names state[0] $auto$alumacc.cc:485:replace_alu$735.X[0] -0 1 -.names $auto$alumacc.cc:485:replace_alu$735.Y[1] $abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[14] -0 1 -.names $abc$4719$new_n967 i_xval[12] $abc$4719$new_n537 i_yval[12] $abc$4719$new_n535 $0\prey[20:0][20] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11100 1 -.names i_yval[12] $abc$4719$new_n507 i_yval[9] i_xval[9] $abc$4719$new_n502 $abc$4719$new_n964 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names i_xval[12] i_yval[12] $abc$4719$new_n964 $abc$4719$new_n504 $abc$4719$new_n498 $0\prey[20:0][15] -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_xval[12] $abc$4719$new_n529 i_yval[11] i_xval[11] $abc$4719$new_n535 $abc$4719$new_n966 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_yval[12] i_xval[12] $abc$4719$new_n966 $abc$4719$new_n533 $abc$4719$new_n534 $abc$4719$new_n967 -00000 1 -00001 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[3] state[2] $abc$4719$new_n635 $abc$4719$new_n638 $abc$4719$new_n633 $abc$4719$new_n968 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names yv[1] $abc$4719$new_n1009 yv[20] $abc$4719$new_n648 $abc$4719$new_n646 $abc$4719$new_n971 -00001 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid $abc$4719$new_n649 yv[2] $abc$4719$new_n971 prey[2] $0\yv[20:0][2] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$4719$new_n657 $abc$4719$new_n654 $abc$4719$new_n650 $abc$4719$new_n973 -000 1 -.names $abc$4719$new_n1009 $abc$4719$new_n646 $abc$4719$new_n973 yv[2] yv[1] $abc$4719$new_n974 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01111 1 -10001 1 -10010 1 -10011 1 -10111 1 -11010 1 -11011 1 -.names state[1] state[0] $abc$4719$new_n642 xv[6] xv[5] $abc$4719$new_n975 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$4719$new_n666 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n672 $abc$4719$new_n975 $abc$4719$new_n976 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names yv[5] $abc$4719$new_n684 yv[20] $abc$4719$new_n683 $abc$4719$new_n682 $abc$4719$new_n977 -00101 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names pre_valid $abc$4719$new_n691 $abc$4719$new_n977 prey[6] $0\yv[20:0][6] -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names yv[9] $abc$4719$new_n714 yv[20] $abc$4719$new_n713 $abc$4719$new_n711 $abc$4719$new_n979 -00101 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names pre_valid $abc$4719$new_n720 yv[10] $abc$4719$new_n979 prey[10] $0\yv[20:0][10] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names yv[13] $abc$4719$new_n734 yv[20] $abc$4719$new_n733 $abc$4719$new_n732 $abc$4719$new_n981 -00101 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names pre_valid $abc$4719$new_n739 yv[14] $abc$4719$new_n981 prey[14] $0\yv[20:0][14] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names state[3] state[2] $abc$4719$new_n789 $abc$4719$new_n792 $abc$4719$new_n787 $abc$4719$new_n983 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4719$new_n794 $abc$4719$new_n983 $abc$4719$new_n797 $abc$4719$new_n984 -000 1 -001 1 -010 1 -.names state[1] state[0] $abc$4719$new_n780 yv[3] yv[2] $abc$4719$new_n985 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n807 $abc$4719$new_n985 $abc$4719$new_n986 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$4719$new_n986 $abc$4719$new_n810 $abc$4719$new_n802 $abc$4719$new_n987 -000 1 -.names $abc$4719$new_n987 $abc$4719$new_n984 $abc$4719$new_n815 xv[2] xv[1] $abc$4719$new_n988 -00000 1 -00001 1 -00100 1 -01000 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -.names state[1] state[0] yv[6] yv[4] $abc$4719$new_n989 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$4719$new_n989 state[3] state[0] yv[5] yv[3] $abc$4719$new_n990 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names state[4] state[3] state[2] $abc$4719$new_n825 $abc$4719$new_n990 $abc$4719$new_n991 -00001 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names state[3] $abc$4719$new_n782 $abc$4719$new_n991 $abc$4719$new_n822 $abc$4719$new_n828 $abc$4719$new_n992 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -.names state[2] state[0] state[1] yv[9] yv[8] $abc$4719$new_n993 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$4719$new_n993 state[2] $abc$4719$new_n774 $abc$4719$new_n781 $abc$4719$new_n780 $abc$4719$new_n994 -00001 1 -00011 1 -00101 1 -00111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names state[4] state[3] yv[20] $abc$4719$new_n994 $abc$4719$new_n834 $abc$4719$new_n995 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names xv[5] $abc$4719$new_n843 yv[20] $abc$4719$new_n842 $abc$4719$new_n841 $abc$4719$new_n996 -00001 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10100 1 -10101 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid $abc$4719$new_n850 xv[6] $abc$4719$new_n996 prex[6] $0\xv[20:0][6] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names xv[7] $abc$4719$new_n857 yv[20] $abc$4719$new_n855 $abc$4719$new_n856 $abc$4719$new_n998 -00001 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10100 1 -10101 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names pre_valid $abc$4719$new_n864 xv[8] $abc$4719$new_n998 prex[8] $0\xv[20:0][8] -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names pre_valid $abc$4719$new_n907 xv[16] prex[16] $abc$4719$new_n1000 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names yv[20] $abc$4719$new_n896 xv[15] $abc$4719$new_n902 $abc$4719$new_n900 $abc$4719$new_n1001 -00010 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$4719$new_n1000 $abc$4719$new_n1001 pre_valid yv[20] $abc$4719$new_n904 $0\xv[20:0][16] -00010 1 -00011 1 -01000 1 -01001 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_yval[12] i_xval[3] i_xval[12] $abc$4719$new_n444 $abc$4719$new_n443 $abc$4719$new_n1003 -00000 1 -00001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_xval[12] $abc$4719$new_n1003 i_yval[3] $abc$4719$new_n437 $abc$4719$new_n440 $0\prex[20:0][9] -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names i_xval[12] $abc$4719$new_n529 i_yval[11] i_xval[11] $abc$4719$new_n535 $abc$4719$new_n1005 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names i_xval[12] $abc$4719$new_n533 $abc$4719$new_n1005 $abc$4719$new_n534 $abc$4719$new_n1006 -0000 1 -0010 1 -0100 1 -0110 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names i_yval[12] $abc$4719$new_n1005 i_xval[12] $abc$4719$new_n537 $abc$4719$new_n1006 $0\prex[20:0][18] -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names state[3] state[2] state[4] xv[20] $abc$4719$new_n630 $abc$4719$new_n1008 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01110 1 -01111 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$4719$new_n1008 state[4] $abc$4719$new_n968 $abc$4719$new_n641 $abc$4719$new_n1009 -0000 1 -0001 1 -1000 1 -1001 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4552 Q=o_aux -.subckt dff C=i_clk D=$0\preph[20:0][19] Q=preph[19] -.subckt dff C=i_clk D=i_yval[12] Q=preph[20] -.subckt sdffrn C=i_clk D=$false Q=prex[0] RN=i_xval[12] -.subckt sdffrn C=i_clk D=$false Q=prex[1] RN=i_xval[12] -.subckt sdffrn C=i_clk D=$false Q=prex[2] RN=i_xval[12] -.subckt sdffrn C=i_clk D=$false Q=prex[3] RN=i_xval[12] -.subckt sdffrn C=i_clk D=$false Q=prex[4] RN=i_xval[12] -.subckt sdffrn C=i_clk D=$false Q=prex[5] RN=i_xval[12] -.subckt dff C=i_clk D=$0\prex[20:0][6] Q=prex[6] -.subckt dff C=i_clk D=$0\prex[20:0][7] Q=prex[7] -.subckt dff C=i_clk D=$0\prex[20:0][8] Q=prex[8] -.subckt dff C=i_clk D=$0\prex[20:0][9] Q=prex[9] -.subckt dff C=i_clk D=$0\prex[20:0][10] Q=prex[10] -.subckt dff C=i_clk D=$0\prex[20:0][11] Q=prex[11] -.subckt dff C=i_clk D=$0\prex[20:0][12] Q=prex[12] -.subckt dff C=i_clk D=$0\prex[20:0][13] Q=prex[13] -.subckt dff C=i_clk D=$0\prex[20:0][14] Q=prex[14] -.subckt dff C=i_clk D=$0\prex[20:0][15] Q=prex[15] -.subckt dff C=i_clk D=$0\prex[20:0][16] Q=prex[16] -.subckt dff C=i_clk D=$0\prex[20:0][17] Q=prex[17] -.subckt dff C=i_clk D=$0\prex[20:0][18] Q=prex[18] -.subckt dff C=i_clk D=$0\prex[20:0][19] Q=prex[19] -.subckt dff C=i_clk D=$false Q=prex[20] -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[14] Q=cangle[14] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[16] Q=cangle[16] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] Q=cangle[17] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[10] Q=cangle[10] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[11] Q=cangle[11] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[12] Q=cangle[12] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[13] Q=cangle[13] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[2] Q=cangle[2] R=state[4] -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[3] Q=cangle[3] R=state[4] -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[4] Q=cangle[4] R=state[4] -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[5] Q=cangle[5] R=state[4] -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[6] Q=cangle[6] R=state[4] -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[7] Q=cangle[7] R=state[4] -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[8] Q=cangle[8] R=state[4] -.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[9] Q=cangle[9] R=state[4] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[0] Q=cangle[0] -.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[1] Q=cangle[1] -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[0] Q=ph[0] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[1] Q=ph[1] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[2] Q=ph[2] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[3] Q=ph[3] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[4] Q=ph[4] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[5] Q=ph[5] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[6] Q=ph[6] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[7] Q=ph[7] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[8] Q=ph[8] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[9] Q=ph[9] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[10] Q=ph[10] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[11] Q=ph[11] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[12] Q=ph[12] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[13] Q=ph[13] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[14] Q=ph[14] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[15] Q=ph[15] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[16] Q=ph[16] R=pre_valid -.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[17] Q=ph[17] R=pre_valid -.subckt sdffs C=i_clk D=$abc$4719$procmux$562_Y[18] Q=ph[18] S=pre_valid -.subckt sdffs C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4558 Q=idle S=i_reset -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4550 Q=o_mag[0] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4548 Q=o_mag[1] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4546 Q=o_mag[2] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4544 Q=o_mag[3] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4542 Q=o_mag[4] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4540 Q=o_mag[5] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4538 Q=o_mag[6] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4536 Q=o_mag[7] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4534 Q=o_mag[8] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4532 Q=o_mag[9] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4530 Q=o_mag[10] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4528 Q=o_mag[11] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4556 Q=o_mag[12] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4526 Q=o_phase[0] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4524 Q=o_phase[1] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4522 Q=o_phase[2] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4520 Q=o_phase[3] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4518 Q=o_phase[4] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4516 Q=o_phase[5] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4514 Q=o_phase[6] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4512 Q=o_phase[7] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4510 Q=o_phase[8] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4508 Q=o_phase[9] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4506 Q=o_phase[10] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4504 Q=o_phase[11] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4502 Q=o_phase[12] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4500 Q=o_phase[13] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4498 Q=o_phase[14] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4496 Q=o_phase[15] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4494 Q=o_phase[16] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4492 Q=o_phase[17] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4490 Q=o_phase[18] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4488 Q=o_phase[19] -.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4554 Q=o_phase[20] -.subckt dff C=i_clk D=$0\xv[20:0][0] Q=xv[0] -.subckt dff C=i_clk D=$0\xv[20:0][1] Q=xv[1] -.subckt dff C=i_clk D=$0\xv[20:0][2] Q=xv[2] -.subckt dff C=i_clk D=$0\xv[20:0][3] Q=xv[3] -.subckt dff C=i_clk D=$0\xv[20:0][4] Q=xv[4] -.subckt dff C=i_clk D=$0\xv[20:0][5] Q=xv[5] -.subckt dff C=i_clk D=$0\xv[20:0][6] Q=xv[6] -.subckt dff C=i_clk D=$0\xv[20:0][7] Q=xv[7] -.subckt dff C=i_clk D=$0\xv[20:0][8] Q=xv[8] -.subckt dff C=i_clk D=$0\xv[20:0][9] Q=xv[9] -.subckt dff C=i_clk D=$0\xv[20:0][10] Q=xv[10] -.subckt dff C=i_clk D=$0\xv[20:0][11] Q=xv[11] -.subckt dff C=i_clk D=$0\xv[20:0][12] Q=xv[12] -.subckt dff C=i_clk D=$0\xv[20:0][13] Q=xv[13] -.subckt dff C=i_clk D=$0\xv[20:0][14] Q=xv[14] -.subckt dff C=i_clk D=$0\xv[20:0][15] Q=xv[15] -.subckt dff C=i_clk D=$0\xv[20:0][16] Q=xv[16] -.subckt dff C=i_clk D=$0\xv[20:0][17] Q=xv[17] -.subckt dff C=i_clk D=$0\xv[20:0][18] Q=xv[18] -.subckt dff C=i_clk D=$0\xv[20:0][19] Q=xv[19] -.subckt dff C=i_clk D=$0\xv[20:0][20] Q=xv[20] -.subckt dff C=i_clk D=$0\yv[20:0][0] Q=yv[0] -.subckt dff C=i_clk D=$0\yv[20:0][1] Q=yv[1] -.subckt dff C=i_clk D=$0\yv[20:0][2] Q=yv[2] -.subckt dff C=i_clk D=$0\yv[20:0][3] Q=yv[3] -.subckt dff C=i_clk D=$0\yv[20:0][4] Q=yv[4] -.subckt dff C=i_clk D=$0\yv[20:0][5] Q=yv[5] -.subckt dff C=i_clk D=$0\yv[20:0][6] Q=yv[6] -.subckt dff C=i_clk D=$0\yv[20:0][7] Q=yv[7] -.subckt dff C=i_clk D=$0\yv[20:0][8] Q=yv[8] -.subckt dff C=i_clk D=$0\yv[20:0][9] Q=yv[9] -.subckt dff C=i_clk D=$0\yv[20:0][10] Q=yv[10] -.subckt dff C=i_clk D=$0\yv[20:0][11] Q=yv[11] -.subckt dff C=i_clk D=$0\yv[20:0][12] Q=yv[12] -.subckt dff C=i_clk D=$0\yv[20:0][13] Q=yv[13] -.subckt dff C=i_clk D=$0\yv[20:0][14] Q=yv[14] -.subckt dff C=i_clk D=$0\yv[20:0][15] Q=yv[15] -.subckt dff C=i_clk D=$0\yv[20:0][16] Q=yv[16] -.subckt dff C=i_clk D=$0\yv[20:0][17] Q=yv[17] -.subckt dff C=i_clk D=$0\yv[20:0][18] Q=yv[18] -.subckt dff C=i_clk D=$0\yv[20:0][19] Q=yv[19] -.subckt dff C=i_clk D=$0\yv[20:0][20] Q=yv[20] -.subckt sdffr C=i_clk D=last_state Q=o_done R=i_reset -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.X[0] Q=state[0] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[1] Q=state[1] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[2] Q=state[2] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[3] Q=state[3] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[4] Q=state[4] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 -.subckt sdffr C=i_clk D=$abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y Q=pre_valid R=i_reset -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.X[0] Q=cangle[15] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$901 -.subckt dff C=i_clk D=$false Q=prey[0] -.subckt dff C=i_clk D=$false Q=prey[1] -.subckt dff C=i_clk D=$false Q=prey[2] -.subckt dff C=i_clk D=$false Q=prey[3] -.subckt dff C=i_clk D=$false Q=prey[4] -.subckt dff C=i_clk D=$false Q=prey[5] -.subckt dff C=i_clk D=$0\prex[20:0][6] Q=prey[6] -.subckt dff C=i_clk D=$0\prey[20:0][7] Q=prey[7] -.subckt dff C=i_clk D=$0\prey[20:0][8] Q=prey[8] -.subckt dff C=i_clk D=$0\prey[20:0][9] Q=prey[9] -.subckt dff C=i_clk D=$0\prey[20:0][10] Q=prey[10] -.subckt dff C=i_clk D=$0\prey[20:0][11] Q=prey[11] -.subckt dff C=i_clk D=$0\prey[20:0][12] Q=prey[12] -.subckt dff C=i_clk D=$0\prey[20:0][13] Q=prey[13] -.subckt dff C=i_clk D=$0\prey[20:0][14] Q=prey[14] -.subckt dff C=i_clk D=$0\prey[20:0][15] Q=prey[15] -.subckt dff C=i_clk D=$0\prey[20:0][16] Q=prey[16] -.subckt dff C=i_clk D=$0\prey[20:0][17] Q=prey[17] -.subckt dff C=i_clk D=$0\prey[20:0][18] Q=prey[18] -.subckt dff C=i_clk D=$0\prey[20:0][19] Q=prey[19] -.subckt dff C=i_clk D=$0\prey[20:0][20] Q=prey[20] -.subckt dff C=i_clk D=$0\ph[20:0][19] Q=ph[19] -.subckt dff C=i_clk D=$0\ph[20:0][20] Q=ph[20] -.subckt sdffr C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4560 Q=aux R=i_reset -.names $false $0\preph[20:0][0] -1 1 -.names $false $0\preph[20:0][1] -1 1 -.names $false $0\preph[20:0][2] -1 1 -.names $false $0\preph[20:0][3] -1 1 -.names $false $0\preph[20:0][4] -1 1 -.names $false $0\preph[20:0][5] -1 1 -.names $false $0\preph[20:0][6] -1 1 -.names $false $0\preph[20:0][7] -1 1 -.names $false $0\preph[20:0][8] -1 1 -.names $false $0\preph[20:0][9] -1 1 -.names $false $0\preph[20:0][10] -1 1 -.names $false $0\preph[20:0][11] -1 1 -.names $false $0\preph[20:0][12] -1 1 -.names $false $0\preph[20:0][13] -1 1 -.names $false $0\preph[20:0][14] -1 1 -.names $false $0\preph[20:0][15] -1 1 -.names $false $0\preph[20:0][16] -1 1 -.names $false $0\preph[20:0][17] -1 1 -.names $true $0\preph[20:0][18] -1 1 -.names i_yval[12] $0\preph[20:0][20] -1 1 -.names $false $0\prex[20:0][0] -1 1 -.names $false $0\prex[20:0][1] -1 1 -.names $false $0\prex[20:0][2] -1 1 -.names $false $0\prex[20:0][3] -1 1 -.names $false $0\prex[20:0][4] -1 1 -.names $false $0\prex[20:0][5] -1 1 -.names $false $0\prex[20:0][20] -1 1 -.names $false $0\prey[20:0][0] -1 1 -.names $false $0\prey[20:0][1] -1 1 -.names $false $0\prey[20:0][2] -1 1 -.names $false $0\prey[20:0][3] -1 1 -.names $false $0\prey[20:0][4] -1 1 -.names $false $0\prey[20:0][5] -1 1 -.names $0\prex[20:0][6] $0\prey[20:0][6] -1 1 -.names state[1] $auto$alumacc.cc:485:replace_alu$735.X[1] -1 1 -.names state[2] $auto$alumacc.cc:485:replace_alu$735.X[2] -1 1 -.names state[3] $auto$alumacc.cc:485:replace_alu$735.X[3] -1 1 -.names state[4] $auto$alumacc.cc:485:replace_alu$735.X[4] -1 1 -.names $auto$alumacc.cc:485:replace_alu$735.X[0] $auto$alumacc.cc:485:replace_alu$735.Y[0] -1 1 -.names $false cangle[18] -1 1 -.names $false cangle[19] -1 1 -.names $false cangle[20] -1 1 -.names $false preph[0] -1 1 -.names $false preph[1] -1 1 -.names $false preph[2] -1 1 -.names $false preph[3] -1 1 -.names $false preph[4] -1 1 -.names $false preph[5] -1 1 -.names $false preph[6] -1 1 -.names $false preph[7] -1 1 -.names $false preph[8] -1 1 -.names $false preph[9] -1 1 -.names $false preph[10] -1 1 -.names $false preph[11] -1 1 -.names $false preph[12] -1 1 -.names $false preph[13] -1 1 -.names $false preph[14] -1 1 -.names $false preph[15] -1 1 -.names $false preph[16] -1 1 -.names $false preph[17] -1 1 -.names $true preph[18] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif deleted file mode 100644 index 4f7f6ef8200..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif +++ /dev/null @@ -1,525 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model smplfir -.inputs i_clk i_ce i_val[0] i_val[1] i_val[2] i_val[3] i_val[4] i_val[5] i_val[6] i_val[7] i_val[8] i_val[9] i_val[10] i_val[11] i_val[12] i_val[13] i_val[14] -.outputs o_val[0] o_val[1] o_val[2] o_val[3] o_val[4] o_val[5] o_val[6] o_val[7] o_val[8] o_val[9] o_val[10] o_val[11] o_val[12] o_val[13] o_val[14] o_val[15] -.names $false -.names $true -1 -.names $undef -.names i_ce i_val[14] delayed[14] $abc$921$new_n81 o_val[14] $abc$921$auto$rtlil.cc:2693:MuxGate$752 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_val[12] delayed[12] i_val[13] delayed[13] $abc$921$new_n82 $abc$921$new_n81 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_val[10] delayed[10] i_val[11] delayed[11] $abc$921$new_n83 $abc$921$new_n82 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_val[8] delayed[8] i_val[9] delayed[9] $abc$921$new_n84 $abc$921$new_n83 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_val[6] delayed[6] i_val[7] delayed[7] $abc$921$new_n85 $abc$921$new_n84 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_val[4] delayed[4] i_val[5] delayed[5] $abc$921$new_n86 $abc$921$new_n85 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_val[2] delayed[2] i_val[3] delayed[3] $abc$921$new_n87 $abc$921$new_n86 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_val[0] delayed[0] i_val[1] delayed[1] $abc$921$new_n87 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names i_ce i_val[13] delayed[13] $abc$921$new_n89 o_val[13] $abc$921$auto$rtlil.cc:2693:MuxGate$754 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_val[12] delayed[12] $abc$921$new_n82 $abc$921$new_n89 -000 1 -001 1 -011 1 -101 1 -.names i_ce i_val[12] delayed[12] $abc$921$new_n82 o_val[12] $abc$921$auto$rtlil.cc:2693:MuxGate$756 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce i_val[11] delayed[11] $abc$921$new_n92 o_val[11] $abc$921$auto$rtlil.cc:2693:MuxGate$758 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_val[10] delayed[10] $abc$921$new_n83 $abc$921$new_n92 -000 1 -001 1 -011 1 -101 1 -.names i_ce i_val[10] delayed[10] $abc$921$new_n83 o_val[10] $abc$921$auto$rtlil.cc:2693:MuxGate$760 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce i_val[9] delayed[9] $abc$921$new_n95 o_val[9] $abc$921$auto$rtlil.cc:2693:MuxGate$762 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_val[8] delayed[8] $abc$921$new_n84 $abc$921$new_n95 -000 1 -001 1 -011 1 -101 1 -.names i_ce i_val[8] delayed[8] $abc$921$new_n84 o_val[8] $abc$921$auto$rtlil.cc:2693:MuxGate$764 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce $abc$921$new_n98 o_val[7] $abc$921$auto$rtlil.cc:2693:MuxGate$766 -001 1 -011 1 -110 1 -111 1 -.names i_val[7] delayed[7] i_val[6] delayed[6] $abc$921$new_n85 $abc$921$new_n98 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names i_ce i_val[6] delayed[6] $abc$921$new_n85 o_val[6] $abc$921$auto$rtlil.cc:2693:MuxGate$768 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce i_val[5] delayed[5] $abc$921$new_n101 o_val[5] $abc$921$auto$rtlil.cc:2693:MuxGate$770 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_val[4] delayed[4] $abc$921$new_n86 $abc$921$new_n101 -000 1 -001 1 -011 1 -101 1 -.names i_ce i_val[4] delayed[4] $abc$921$new_n86 o_val[4] $abc$921$auto$rtlil.cc:2693:MuxGate$772 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce i_val[3] delayed[3] $abc$921$new_n104 o_val[3] $abc$921$auto$rtlil.cc:2693:MuxGate$774 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_val[2] delayed[2] $abc$921$new_n87 $abc$921$new_n104 -000 1 -001 1 -011 1 -101 1 -.names i_ce i_val[2] delayed[2] $abc$921$new_n87 o_val[2] $abc$921$auto$rtlil.cc:2693:MuxGate$776 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce i_val[1] delayed[1] $abc$921$new_n107 o_val[1] $abc$921$auto$rtlil.cc:2693:MuxGate$778 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names i_val[0] delayed[0] $abc$921$new_n107 -11 1 -.names i_ce i_val[0] delayed[0] o_val[0] $abc$921$auto$rtlil.cc:2693:MuxGate$780 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names i_ce i_val[13] delayed[13] $abc$921$auto$rtlil.cc:2693:MuxGate$782 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[12] delayed[12] $abc$921$auto$rtlil.cc:2693:MuxGate$784 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[11] delayed[11] $abc$921$auto$rtlil.cc:2693:MuxGate$786 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[10] delayed[10] $abc$921$auto$rtlil.cc:2693:MuxGate$788 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[9] delayed[9] $abc$921$auto$rtlil.cc:2693:MuxGate$790 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[8] delayed[8] $abc$921$auto$rtlil.cc:2693:MuxGate$792 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[7] delayed[7] $abc$921$auto$rtlil.cc:2693:MuxGate$794 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[6] delayed[6] $abc$921$auto$rtlil.cc:2693:MuxGate$796 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[5] delayed[5] $abc$921$auto$rtlil.cc:2693:MuxGate$798 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[4] delayed[4] $abc$921$auto$rtlil.cc:2693:MuxGate$800 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[3] delayed[3] $abc$921$auto$rtlil.cc:2693:MuxGate$802 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[2] delayed[2] $abc$921$auto$rtlil.cc:2693:MuxGate$804 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[1] delayed[1] $abc$921$auto$rtlil.cc:2693:MuxGate$806 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[0] delayed[0] $abc$921$auto$rtlil.cc:2693:MuxGate$808 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[14] delayed[14] $abc$921$auto$rtlil.cc:2693:MuxGate$810 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_val[14] delayed[14] $abc$921$new_n81 o_val[15] $abc$921$auto$rtlil.cc:2693:MuxGate$812 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$808 Q=delayed[0] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$806 Q=delayed[1] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$804 Q=delayed[2] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$802 Q=delayed[3] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$800 Q=delayed[4] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$798 Q=delayed[5] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$796 Q=delayed[6] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$794 Q=delayed[7] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$792 Q=delayed[8] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$790 Q=delayed[9] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$788 Q=delayed[10] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$786 Q=delayed[11] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$784 Q=delayed[12] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$782 Q=delayed[13] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$810 Q=delayed[14] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$780 Q=o_val[0] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$778 Q=o_val[1] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$776 Q=o_val[2] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$774 Q=o_val[3] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$772 Q=o_val[4] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$770 Q=o_val[5] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$768 Q=o_val[6] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$766 Q=o_val[7] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$764 Q=o_val[8] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$762 Q=o_val[9] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$760 Q=o_val[10] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$758 Q=o_val[11] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$756 Q=o_val[12] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$754 Q=o_val[13] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$752 Q=o_val[14] -.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$812 Q=o_val[15] -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif deleted file mode 100644 index eadfe9f56b9..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif +++ /dev/null @@ -1,36396 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model topolar -.inputs i_clk i_reset i_ce i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_aux -.outputs o_mag[0] o_mag[1] o_mag[2] o_mag[3] o_mag[4] o_mag[5] o_mag[6] o_mag[7] o_mag[8] o_mag[9] o_mag[10] o_mag[11] o_mag[12] o_phase[0] o_phase[1] o_phase[2] o_phase[3] o_phase[4] o_phase[5] o_phase[6] o_phase[7] o_phase[8] o_phase[9] o_phase[10] o_phase[11] o_phase[12] o_phase[13] o_phase[14] o_phase[15] o_phase[16] o_phase[17] o_phase[18] o_phase[19] o_phase[20] o_aux -.names $false -.names $true -1 -.names $undef -.names i_ce ax[17] ax[16] $abc$30358$auto$rtlil.cc:2693:MuxGate$25855 -010 1 -011 1 -101 1 -111 1 -.names i_ce ax[16] ax[15] $abc$30358$auto$rtlil.cc:2693:MuxGate$25857 -010 1 -011 1 -101 1 -111 1 -.names i_ce ax[14] ax[15] $abc$30358$auto$rtlil.cc:2693:MuxGate$25859 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[13] ax[14] $abc$30358$auto$rtlil.cc:2693:MuxGate$25861 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[12] ax[13] $abc$30358$auto$rtlil.cc:2693:MuxGate$25863 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[11] ax[12] $abc$30358$auto$rtlil.cc:2693:MuxGate$25865 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[10] ax[11] $abc$30358$auto$rtlil.cc:2693:MuxGate$25867 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[9] ax[10] $abc$30358$auto$rtlil.cc:2693:MuxGate$25869 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[8] ax[9] $abc$30358$auto$rtlil.cc:2693:MuxGate$25871 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[7] ax[8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25873 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[6] ax[7] $abc$30358$auto$rtlil.cc:2693:MuxGate$25875 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[5] ax[6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25877 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[4] ax[5] $abc$30358$auto$rtlil.cc:2693:MuxGate$25879 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[3] ax[4] $abc$30358$auto$rtlil.cc:2693:MuxGate$25881 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[2] ax[3] $abc$30358$auto$rtlil.cc:2693:MuxGate$25883 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[1] ax[2] $abc$30358$auto$rtlil.cc:2693:MuxGate$25885 -001 1 -011 1 -110 1 -111 1 -.names i_ce ax[0] ax[1] $abc$30358$auto$rtlil.cc:2693:MuxGate$25887 -001 1 -011 1 -110 1 -111 1 -.names i_ce i_aux ax[0] $abc$30358$auto$rtlil.cc:2693:MuxGate$25889 -001 1 -011 1 -110 1 -111 1 -.names $abc$30358$new_n6162 yv[0][19] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25891 -010 1 -100 1 -101 1 -110 1 -111 1 -.names i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2426 $abc$30358$new_n2425 -000 1 -001 1 -011 1 -101 1 -.names i_yval[8] $abc$30358$new_n2440 i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2427 $abc$30358$new_n2426 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_yval[6] $abc$30358$new_n2437 i_yval[7] $abc$30358$new_n2436 $abc$30358$new_n2428 $abc$30358$new_n2427 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_xval[5] $abc$30358$new_n2435 i_yval[5] $abc$30358$new_n2429 $abc$30358$new_n2428 -0001 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -1101 1 -.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2430 $abc$30358$new_n2429 -000 1 -001 1 -011 1 -101 1 -.names i_yval[3] $abc$30358$new_n2433 $abc$30358$new_n2431 $abc$30358$new_n2430 -000 1 -001 1 -011 1 -101 1 -.names i_xval[2] i_xval[0] i_xval[1] i_yval[2] $abc$30358$new_n2432 $abc$30358$new_n2431 -00000 1 -00001 1 -00011 1 -00101 1 -01001 1 -01101 1 -10001 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_xval[1] i_xval[0] i_yval[0] i_yval[1] $abc$30358$new_n2432 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -.names i_xval[3] i_xval[0] i_xval[2] i_xval[1] $abc$30358$new_n2433 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names i_xval[4] i_xval[0] i_xval[3] i_xval[2] i_xval[1] $abc$30358$new_n2434 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -.names i_xval[0] i_xval[4] i_xval[3] i_xval[2] i_xval[1] $abc$30358$new_n2435 -00000 1 -.names i_xval[7] $abc$30358$new_n2435 i_xval[6] i_xval[5] $abc$30358$new_n2436 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names i_xval[6] $abc$30358$new_n2435 i_xval[5] $abc$30358$new_n2437 -000 1 -001 1 -011 1 -110 1 -.names i_xval[9] $abc$30358$new_n2439 $abc$30358$new_n2438 -00 1 -11 1 -.names $abc$30358$new_n2435 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$30358$new_n2439 -10000 1 -.names i_xval[8] $abc$30358$new_n2435 i_xval[7] i_xval[6] i_xval[5] $abc$30358$new_n2440 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names i_xval[10] $abc$30358$new_n2439 i_xval[9] $abc$30358$new_n2441 -000 1 -001 1 -011 1 -110 1 -.names $abc$30358$new_n2439 i_xval[10] i_xval[9] $abc$30358$new_n2442 -100 1 -.names $abc$30358$new_n2453 i_yval[11] $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2456 $abc$30358$new_n2444 -10000 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -.names i_yval[9] $abc$30358$new_n2438 i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2446 $abc$30358$new_n2445 -00000 1 -00110 1 -01000 1 -01001 1 -01110 1 -01111 1 -11000 1 -11110 1 -.names i_yval[7] i_yval[8] $abc$30358$new_n2436 $abc$30358$new_n2440 $abc$30358$new_n2447 $abc$30358$new_n2446 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2448 $abc$30358$new_n2447 -001 1 -100 1 -101 1 -111 1 -.names i_xval[5] $abc$30358$new_n2435 i_yval[5] $abc$30358$new_n2449 $abc$30358$new_n2448 -0011 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2450 $abc$30358$new_n2449 -001 1 -100 1 -101 1 -111 1 -.names i_yval[3] $abc$30358$new_n2433 $abc$30358$new_n2451 $abc$30358$new_n2450 -001 1 -100 1 -101 1 -111 1 -.names i_xval[2] i_yval[2] i_xval[0] i_xval[1] $abc$30358$new_n2452 $abc$30358$new_n2451 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -01111 1 -10011 1 -10101 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_xval[0] i_yval[1] i_xval[1] i_yval[0] $abc$30358$new_n2452 -0001 1 -0100 1 -0101 1 -0111 1 -1110 1 -1111 1 -.names $abc$30358$new_n2455 $abc$30358$new_n2454 $abc$30358$new_n2453 -10 1 -.names $abc$30358$new_n2442 i_xval[11] $abc$30358$new_n2454 -10 1 -.names i_xval[12] i_yval[12] $abc$30358$new_n2455 -10 1 -.names i_xval[11] $abc$30358$new_n2442 $abc$30358$new_n2456 -00 1 -11 1 -.names $abc$30358$new_n2441 i_yval[10] $abc$30358$new_n2457 -10 1 -.names i_yval[9] i_yval[10] i_xval[9] i_xval[10] $abc$30358$new_n2461 $abc$30358$new_n2460 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_yval[7] i_yval[8] i_xval[7] i_xval[8] $abc$30358$new_n2462 $abc$30358$new_n2461 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_yval[5] i_yval[6] i_xval[5] i_xval[6] $abc$30358$new_n2463 $abc$30358$new_n2462 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_yval[3] i_yval[4] i_xval[3] i_xval[4] $abc$30358$new_n2464 $abc$30358$new_n2463 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_yval[1] i_yval[2] i_xval[1] i_xval[2] $abc$30358$new_n2465 $abc$30358$new_n2464 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_yval[0] i_xval[0] $abc$30358$new_n2465 -10 1 -.names i_yval[9] i_xval[9] i_yval[10] i_xval[10] $abc$30358$new_n2468 $abc$30358$new_n2467 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_yval[7] i_xval[7] i_yval[8] i_xval[8] $abc$30358$new_n2469 $abc$30358$new_n2468 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_yval[5] i_xval[5] i_yval[6] i_xval[6] $abc$30358$new_n2470 $abc$30358$new_n2469 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_yval[3] i_xval[3] i_yval[4] i_xval[4] $abc$30358$new_n2471 $abc$30358$new_n2470 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_yval[1] i_xval[1] i_yval[2] i_xval[2] $abc$30358$new_n2472 $abc$30358$new_n2471 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names i_yval[0] i_xval[0] $abc$30358$new_n2472 -11 1 -.names i_ce yv[0][18] $abc$30358$new_n2475 $abc$30358$new_n6162 $abc$30358$auto$rtlil.cc:2693:MuxGate$25893 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names i_xval[12] $abc$30358$new_n2454 $abc$30358$new_n2476 i_yval[12] $abc$30358$new_n2475 -1010 1 -1100 1 -.names i_yval[11] $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2456 $abc$30358$new_n2476 -0000 1 -1000 1 -1001 1 -1010 1 -1100 1 -1110 1 -.names i_ce $abc$30358$new_n2478 yv[0][17] $abc$30358$new_n2483 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25895 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names i_yval[12] i_xval[12] $abc$30358$new_n2479 $abc$30358$new_n2481 $abc$30358$new_n2482 $abc$30358$new_n2478 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$30358$new_n2480 $abc$30358$new_n2425 $abc$30358$new_n2479 -01 1 -10 1 -.names i_yval[11] $abc$30358$new_n2456 $abc$30358$new_n2480 -01 1 -10 1 -.names i_yval[11] i_xval[11] $abc$30358$new_n2467 $abc$30358$new_n2481 -000 1 -011 1 -101 1 -110 1 -.names i_yval[11] i_xval[11] $abc$30358$new_n2460 $abc$30358$new_n2482 -000 1 -011 1 -101 1 -110 1 -.names $abc$30358$new_n2480 $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2483 -000 1 -101 1 -110 1 -111 1 -.names i_ce $abc$30358$new_n2485 yv[0][16] $abc$30358$new_n2489 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25897 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names i_yval[12] i_xval[12] $abc$30358$new_n2486 $abc$30358$new_n2487 $abc$30358$new_n2488 $abc$30358$new_n2485 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2426 $abc$30358$new_n2486 -000 1 -011 1 -101 1 -110 1 -.names i_yval[10] i_xval[10] i_yval[9] i_xval[9] $abc$30358$new_n2468 $abc$30358$new_n2487 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names i_yval[10] i_xval[10] i_yval[9] i_xval[9] $abc$30358$new_n2461 $abc$30358$new_n2488 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names i_yval[10] $abc$30358$new_n2441 i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2446 $abc$30358$new_n2489 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names i_ce $abc$30358$new_n2492 yv[0][15] $abc$30358$new_n2491 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25899 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2446 $abc$30358$new_n2491 -001 1 -010 1 -100 1 -111 1 -.names i_yval[12] i_xval[12] $abc$30358$new_n2493 $abc$30358$new_n2494 $abc$30358$new_n2495 $abc$30358$new_n2492 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names i_yval[9] $abc$30358$new_n2438 i_yval[8] $abc$30358$new_n2440 $abc$30358$new_n2427 $abc$30358$new_n2493 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names i_yval[9] i_xval[9] $abc$30358$new_n2468 $abc$30358$new_n2494 -001 1 -010 1 -100 1 -111 1 -.names i_yval[9] i_xval[9] $abc$30358$new_n2461 $abc$30358$new_n2495 -000 1 -011 1 -101 1 -110 1 -.names i_ce $abc$30358$new_n2497 yv[0][14] $abc$30358$new_n2501 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25901 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names i_yval[12] i_xval[12] $abc$30358$new_n2498 $abc$30358$new_n2499 $abc$30358$new_n2500 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-00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce xv[18][12] $abc$30358$new_n2622 o_mag[4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26025 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names i_ce $abc$30358$new_n2631 o_mag[3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26027 -001 1 -011 1 -110 1 -111 1 -.names xv[18][11] xv[18][7] xv[18][8] xv[18][9] xv[18][10] $abc$30358$new_n2631 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names i_ce $abc$30358$new_n2633 o_mag[2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26029 -001 1 -011 1 -110 1 -111 1 -.names xv[18][10] xv[18][7] xv[18][8] xv[18][9] $abc$30358$new_n2633 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names i_ce xv[18][9] xv[18][7] xv[18][8] o_mag[1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26031 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_ce xv[18][7] xv[18][8] o_mag[0] $abc$30358$new_n2636 $abc$30358$auto$rtlil.cc:2693:MuxGate$26033 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -.names $abc$30358$new_n2637 xv[18][4] xv[18][5] xv[18][6] $abc$30358$new_n2636 -1000 1 -.names xv[18][0] xv[18][1] xv[18][2] xv[18][3] $abc$30358$new_n2637 -0000 1 -.names i_ce xv[0][20] yv[0][19] $abc$30358$new_n2639 yv[1][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26035 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names yv[0][20] xv[0][19] yv[0][18] $abc$30358$new_n2640 $abc$30358$new_n2649 $abc$30358$new_n2639 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names xv[0][17] yv[0][16] xv[0][18] yv[0][17] $abc$30358$new_n2641 $abc$30358$new_n2640 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names xv[0][15] yv[0][14] xv[0][16] yv[0][15] $abc$30358$new_n2642 $abc$30358$new_n2641 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names xv[0][13] yv[0][12] xv[0][14] yv[0][13] $abc$30358$new_n2643 $abc$30358$new_n2642 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[0][11] yv[0][10] xv[0][12] yv[0][11] $abc$30358$new_n2644 $abc$30358$new_n2643 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[0][9] yv[0][8] xv[0][10] yv[0][9] $abc$30358$new_n2645 $abc$30358$new_n2644 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[0][7] yv[0][6] xv[0][8] yv[0][7] $abc$30358$new_n2646 $abc$30358$new_n2645 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[0][5] yv[0][4] xv[0][6] yv[0][5] $abc$30358$new_n2647 $abc$30358$new_n2646 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[0][3] yv[0][2] xv[0][4] yv[0][3] $abc$30358$new_n2648 $abc$30358$new_n2647 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names xv[0][1] yv[0][0] xv[0][2] yv[0][1] $abc$30358$new_n2648 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 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-.names xv[0][10] $abc$30358$new_n2654 $abc$30358$new_n2663 yv[0][9] $abc$30358$new_n2662 $abc$30358$new_n2653 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -11010 1 -11110 1 -.names $abc$30358$new_n2659 $abc$30358$new_n2658 $abc$30358$new_n2661 $abc$30358$new_n2655 $abc$30358$new_n2660 $abc$30358$new_n2654 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -.names xv[0][5] xv[0][6] yv[0][4] yv[0][5] $abc$30358$new_n2656 $abc$30358$new_n2655 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names xv[0][3] xv[0][4] yv[0][2] yv[0][3] $abc$30358$new_n2657 $abc$30358$new_n2656 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names xv[0][1] xv[0][2] yv[0][0] yv[0][1] $abc$30358$new_n2657 -0100 1 -0110 1 -1000 1 -1100 1 -1101 1 -1110 1 -.names xv[0][9] yv[0][8] $abc$30358$new_n2658 -01 1 -10 1 -.names xv[0][8] yv[0][7] $abc$30358$new_n2659 -10 1 -.names xv[0][7] yv[0][6] $abc$30358$new_n2660 -01 1 -10 1 -.names yv[0][7] xv[0][8] yv[0][6] xv[0][7] $abc$30358$new_n2661 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names xv[0][11] yv[0][10] $abc$30358$new_n2662 -01 1 -10 1 -.names yv[0][8] xv[0][9] $abc$30358$new_n2663 -10 1 -.names xv[0][12] yv[0][11] $abc$30358$new_n2664 -10 1 -.names yv[0][11] xv[0][12] yv[0][10] xv[0][11] $abc$30358$new_n2665 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names i_ce xv[0][19] yv[0][18] $abc$30358$new_n2667 yv[1][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26037 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names yv[0][20] xv[0][18] yv[0][17] $abc$30358$new_n2650 $abc$30358$new_n2668 $abc$30358$new_n2667 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 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$abc$30358$new_n6149 $abc$30358$new_n6150 -1000 1 -1001 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names xv[5][20] yv[5][16] yv[5][17] yv[5][18] yv[5][19] $abc$30358$new_n6151 -00000 1 -11111 1 -.names $abc$30358$new_n6151 $abc$30358$new_n3531 yv[5][19] $abc$30358$new_n6152 -101 1 -110 1 -.names xv[4][20] yv[4][18] yv[4][19] yv[4][16] yv[4][17] $abc$30358$new_n6153 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -.names yv[4][20] $abc$30358$new_n3363 yv[4][19] $abc$30358$new_n6153 $abc$30358$new_n6154 -1000 1 -1001 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names xv[3][20] yv[3][18] yv[3][19] yv[3][16] yv[3][17] $abc$30358$new_n6155 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -.names yv[3][20] $abc$30358$new_n3189 yv[3][19] $abc$30358$new_n6155 $abc$30358$new_n6156 -1000 1 -1001 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names xv[2][20] $abc$30358$new_n3003 yv[2][19] yv[2][18] yv[2][20] $abc$30358$new_n6157 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names i_ce yv[3][20] $abc$30358$new_n6157 $abc$30358$new_n5939 $abc$30358$auto$rtlil.cc:2693:MuxGate$28235 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$30358$new_n2821 xv[1][20] yv[1][19] yv[1][18] yv[1][20] $abc$30358$new_n6159 -00001 1 -00011 1 -00101 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11011 1 -11101 1 -11111 1 -.names i_ce $abc$30358$new_n5950 $abc$30358$new_n6159 yv[2][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28241 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names i_xval[12] $abc$30358$new_n2425 $abc$30358$new_n2442 i_yval[11] i_xval[11] $abc$30358$new_n6161 -00001 1 -01000 1 -01001 1 -01011 1 -01101 1 -.names i_ce i_yval[12] $abc$30358$new_n2444 $abc$30358$new_n5970 $abc$30358$new_n6161 $abc$30358$new_n6162 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_yval[11] i_xval[11] i_yval[12] $abc$30358$new_n2460 $abc$30358$new_n2467 $abc$30358$new_n6163 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names i_xval[12] i_yval[12] $abc$30358$new_n2476 $abc$30358$new_n2454 $abc$30358$new_n6163 $abc$30358$new_n6164 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_yval[1] i_yval[0] i_xval[0] i_xval[12] i_yval[12] $abc$30358$new_n6165 -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11010 1 -11101 1 -11110 1 -.names i_ce i_xval[1] $abc$30358$new_n6165 xv[0][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$25955 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names yv[13][20] yv[13][19] $abc$30358$new_n6108 $abc$30358$new_n6063 $abc$30358$new_n4997 $abc$30358$new_n6169 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11100 1 -11101 1 -.names i_ce $abc$30358$new_n6169 yv[13][20] yv[14][20] $abc$30358$new_n6110 $abc$30358$auto$rtlil.cc:2693:MuxGate$28169 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names yv[12][20] yv[12][19] $abc$30358$new_n6114 $abc$30358$new_n4813 $abc$30358$new_n6052 $abc$30358$new_n6173 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11100 1 -11101 1 -.names i_ce $abc$30358$new_n6173 yv[12][20] yv[13][20] $abc$30358$new_n6116 $abc$30358$auto$rtlil.cc:2693:MuxGate$28175 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names yv[11][20] yv[11][19] $abc$30358$new_n6120 $abc$30358$new_n4619 $abc$30358$new_n6046 $abc$30358$new_n6177 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11100 1 -11101 1 -.names i_ce $abc$30358$new_n6177 yv[11][20] yv[12][20] $abc$30358$new_n6122 $abc$30358$auto$rtlil.cc:2693:MuxGate$28181 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names yv[8][20] yv[8][19] $abc$30358$new_n6132 $abc$30358$new_n4088 $abc$30358$new_n4075 $abc$30358$new_n6181 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11100 1 -11101 1 -.names i_ce $abc$30358$new_n6181 yv[8][20] yv[9][20] $abc$30358$new_n6134 $abc$30358$auto$rtlil.cc:2693:MuxGate$28199 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names yv[7][20] yv[7][19] $abc$30358$new_n6138 $abc$30358$new_n3891 $abc$30358$new_n3904 $abc$30358$new_n6185 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11100 1 -11101 1 -.names i_ce $abc$30358$new_n6185 yv[7][20] yv[8][20] $abc$30358$new_n6140 $abc$30358$auto$rtlil.cc:2693:MuxGate$28205 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -.names i_ce yv[7][20] $abc$30358$new_n6146 $abc$30358$new_n5894 $abc$30358$auto$rtlil.cc:2693:MuxGate$28211 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28143 Q=xv[18][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28141 Q=xv[18][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28139 Q=xv[18][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28137 Q=xv[18][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28135 Q=xv[18][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28133 Q=xv[18][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28131 Q=xv[18][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28129 Q=xv[18][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28127 Q=xv[18][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28125 Q=xv[18][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28123 Q=xv[18][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28121 Q=xv[18][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28119 Q=xv[18][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28117 Q=xv[18][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28115 Q=xv[18][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28113 Q=xv[18][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28111 Q=xv[18][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28109 Q=xv[18][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28107 Q=xv[18][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28105 Q=xv[18][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28145 Q=xv[18][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28103 Q=ph[1][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28101 Q=ph[1][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28099 Q=ph[1][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28097 Q=ph[1][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28095 Q=ph[1][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28093 Q=ph[1][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28091 Q=ph[1][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28089 Q=ph[1][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28087 Q=ph[1][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28085 Q=ph[1][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28083 Q=ph[1][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28081 Q=ph[1][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28079 Q=ph[1][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28263 Q=ph[1][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28077 Q=ph[0][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28075 Q=ph[0][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28261 Q=ph[0][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28073 Q=ph[18][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28071 Q=ph[18][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28069 Q=ph[18][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28067 Q=ph[18][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28065 Q=ph[18][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28063 Q=ph[18][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28061 Q=ph[18][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28059 Q=ph[18][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28057 Q=ph[18][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28055 Q=ph[18][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28053 Q=ph[18][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28051 Q=ph[18][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28049 Q=ph[18][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28047 Q=ph[18][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28045 Q=ph[18][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28043 Q=ph[18][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28041 Q=ph[18][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28039 Q=ph[18][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28037 Q=ph[18][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28035 Q=ph[18][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28147 Q=ph[18][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28033 Q=xv[17][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28031 Q=xv[17][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28029 Q=xv[17][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28027 Q=xv[17][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28025 Q=xv[17][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28023 Q=xv[17][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28021 Q=xv[17][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28019 Q=xv[17][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28017 Q=xv[17][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28015 Q=xv[17][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28013 Q=xv[17][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28011 Q=xv[17][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28009 Q=xv[17][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28007 Q=xv[17][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28005 Q=xv[17][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28003 Q=xv[17][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28001 Q=xv[17][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27999 Q=xv[17][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27997 Q=xv[17][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27995 Q=xv[17][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28149 Q=xv[17][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27957 Q=yv[17][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27955 Q=yv[17][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28151 Q=yv[17][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27953 Q=ph[17][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27951 Q=ph[17][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27949 Q=ph[17][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27947 Q=ph[17][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27945 Q=ph[17][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27943 Q=ph[17][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27941 Q=ph[17][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27939 Q=ph[17][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27937 Q=ph[17][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27935 Q=ph[17][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27933 Q=ph[17][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27931 Q=ph[17][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27929 Q=ph[17][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27927 Q=ph[17][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27925 Q=ph[17][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27923 Q=ph[17][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27921 Q=ph[17][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27919 Q=ph[17][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27917 Q=ph[17][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27915 Q=ph[17][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28153 Q=ph[17][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27913 Q=xv[16][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27911 Q=xv[16][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27909 Q=xv[16][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27907 Q=xv[16][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27905 Q=xv[16][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27903 Q=xv[16][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27901 Q=xv[16][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27899 Q=xv[16][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27897 Q=xv[16][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27895 Q=xv[16][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27893 Q=xv[16][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27891 Q=xv[16][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27889 Q=xv[16][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27887 Q=xv[16][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27885 Q=xv[16][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27883 Q=xv[16][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27881 Q=xv[16][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27879 Q=xv[16][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27877 Q=xv[16][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27875 Q=xv[16][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28155 Q=xv[16][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27873 Q=yv[16][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27871 Q=yv[16][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27869 Q=yv[16][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27867 Q=yv[16][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27865 Q=yv[16][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27863 Q=yv[16][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27861 Q=yv[16][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27859 Q=yv[16][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27857 Q=yv[16][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27855 Q=yv[16][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27853 Q=yv[16][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27851 Q=yv[16][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27849 Q=yv[16][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27847 Q=yv[16][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27845 Q=yv[16][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27843 Q=yv[16][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27841 Q=yv[16][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27839 Q=yv[16][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27837 Q=yv[16][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27835 Q=yv[16][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28157 Q=yv[16][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27833 Q=ph[16][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27831 Q=ph[16][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27829 Q=ph[16][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27827 Q=ph[16][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27825 Q=ph[16][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27823 Q=ph[16][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27821 Q=ph[16][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27819 Q=ph[16][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27817 Q=ph[16][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27815 Q=ph[16][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27813 Q=ph[16][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27811 Q=ph[16][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27809 Q=ph[16][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27807 Q=ph[16][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27805 Q=ph[16][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27803 Q=ph[16][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27801 Q=ph[16][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27799 Q=ph[16][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27797 Q=ph[16][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27795 Q=ph[16][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28159 Q=ph[16][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27793 Q=xv[15][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27791 Q=xv[15][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27789 Q=xv[15][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27787 Q=xv[15][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27785 Q=xv[15][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27783 Q=xv[15][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27781 Q=xv[15][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27779 Q=xv[15][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27777 Q=xv[15][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27775 Q=xv[15][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27773 Q=xv[15][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27771 Q=xv[15][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27769 Q=xv[15][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27767 Q=xv[15][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27765 Q=xv[15][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27763 Q=xv[15][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27761 Q=xv[15][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27759 Q=xv[15][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27757 Q=xv[15][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27755 Q=xv[15][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28161 Q=xv[15][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27753 Q=yv[15][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27751 Q=yv[15][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27749 Q=yv[15][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27747 Q=yv[15][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27745 Q=yv[15][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27743 Q=yv[15][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27741 Q=yv[15][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27739 Q=yv[15][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27737 Q=yv[15][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27735 Q=yv[15][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27733 Q=yv[15][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27731 Q=yv[15][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27729 Q=yv[15][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27727 Q=yv[15][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27725 Q=yv[15][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27723 Q=yv[15][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27721 Q=yv[15][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27719 Q=yv[15][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27717 Q=yv[15][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27715 Q=yv[15][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28163 Q=yv[15][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27713 Q=ph[15][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27711 Q=ph[15][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27709 Q=ph[15][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27707 Q=ph[15][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27705 Q=ph[15][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27703 Q=ph[15][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27701 Q=ph[15][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27699 Q=ph[15][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27697 Q=ph[15][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27695 Q=ph[15][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27693 Q=ph[15][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27691 Q=ph[15][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27689 Q=ph[15][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27687 Q=ph[15][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27685 Q=ph[15][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27683 Q=ph[15][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27681 Q=ph[15][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27679 Q=ph[15][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27677 Q=ph[15][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27675 Q=ph[15][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28165 Q=ph[15][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27673 Q=xv[14][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27671 Q=xv[14][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27669 Q=xv[14][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27667 Q=xv[14][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27665 Q=xv[14][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27663 Q=xv[14][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27661 Q=xv[14][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27659 Q=xv[14][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27657 Q=xv[14][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27655 Q=xv[14][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27653 Q=xv[14][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27651 Q=xv[14][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27649 Q=xv[14][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27647 Q=xv[14][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27645 Q=xv[14][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27643 Q=xv[14][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27641 Q=xv[14][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27639 Q=xv[14][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27637 Q=xv[14][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27635 Q=xv[14][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28167 Q=xv[14][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27633 Q=yv[14][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27631 Q=yv[14][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27629 Q=yv[14][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27627 Q=yv[14][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27625 Q=yv[14][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27623 Q=yv[14][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27621 Q=yv[14][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27619 Q=yv[14][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27617 Q=yv[14][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27615 Q=yv[14][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27613 Q=yv[14][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27611 Q=yv[14][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27609 Q=yv[14][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27607 Q=yv[14][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27605 Q=yv[14][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27603 Q=yv[14][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27601 Q=yv[14][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27599 Q=yv[14][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27597 Q=yv[14][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27595 Q=yv[14][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28169 Q=yv[14][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27593 Q=ph[14][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27591 Q=ph[14][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27589 Q=ph[14][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27587 Q=ph[14][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27585 Q=ph[14][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27583 Q=ph[14][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27581 Q=ph[14][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27579 Q=ph[14][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27577 Q=ph[14][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27575 Q=ph[14][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27573 Q=ph[14][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27571 Q=ph[14][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27569 Q=ph[14][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27567 Q=ph[14][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27565 Q=ph[14][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27563 Q=ph[14][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27561 Q=ph[14][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27559 Q=ph[14][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27557 Q=ph[14][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27555 Q=ph[14][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28171 Q=ph[14][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27553 Q=xv[13][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27551 Q=xv[13][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27549 Q=xv[13][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27547 Q=xv[13][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27545 Q=xv[13][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27543 Q=xv[13][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27541 Q=xv[13][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27539 Q=xv[13][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27537 Q=xv[13][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27535 Q=xv[13][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27533 Q=xv[13][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27531 Q=xv[13][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27529 Q=xv[13][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27527 Q=xv[13][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27525 Q=xv[13][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27523 Q=xv[13][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27521 Q=xv[13][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27519 Q=xv[13][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27517 Q=xv[13][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27515 Q=xv[13][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28173 Q=xv[13][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27513 Q=yv[13][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27511 Q=yv[13][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27509 Q=yv[13][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27507 Q=yv[13][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27505 Q=yv[13][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27503 Q=yv[13][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27501 Q=yv[13][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27499 Q=yv[13][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27497 Q=yv[13][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27495 Q=yv[13][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27493 Q=yv[13][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27491 Q=yv[13][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27489 Q=yv[13][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27487 Q=yv[13][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27485 Q=yv[13][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27483 Q=yv[13][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27481 Q=yv[13][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27479 Q=yv[13][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27477 Q=yv[13][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27475 Q=yv[13][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28175 Q=yv[13][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27473 Q=ph[13][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27471 Q=ph[13][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27469 Q=ph[13][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27467 Q=ph[13][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27465 Q=ph[13][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27463 Q=ph[13][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27461 Q=ph[13][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27459 Q=ph[13][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27457 Q=ph[13][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27455 Q=ph[13][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27453 Q=ph[13][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27451 Q=ph[13][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27449 Q=ph[13][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27447 Q=ph[13][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27445 Q=ph[13][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27443 Q=ph[13][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27441 Q=ph[13][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27439 Q=ph[13][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27437 Q=ph[13][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27435 Q=ph[13][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28177 Q=ph[13][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27433 Q=xv[12][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27431 Q=xv[12][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27429 Q=xv[12][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27427 Q=xv[12][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27425 Q=xv[12][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27423 Q=xv[12][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27421 Q=xv[12][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27419 Q=xv[12][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27417 Q=xv[12][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27415 Q=xv[12][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27413 Q=xv[12][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27411 Q=xv[12][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27409 Q=xv[12][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27407 Q=xv[12][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27405 Q=xv[12][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27403 Q=xv[12][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27401 Q=xv[12][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27399 Q=xv[12][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27397 Q=xv[12][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27395 Q=xv[12][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28179 Q=xv[12][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27393 Q=yv[12][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27391 Q=yv[12][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27389 Q=yv[12][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27387 Q=yv[12][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27385 Q=yv[12][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27383 Q=yv[12][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27381 Q=yv[12][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27379 Q=yv[12][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27377 Q=yv[12][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27375 Q=yv[12][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27373 Q=yv[12][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27371 Q=yv[12][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27369 Q=yv[12][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27367 Q=yv[12][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27365 Q=yv[12][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27363 Q=yv[12][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27361 Q=yv[12][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27359 Q=yv[12][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27357 Q=yv[12][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27355 Q=yv[12][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28181 Q=yv[12][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27353 Q=ph[12][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27351 Q=ph[12][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27349 Q=ph[12][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27347 Q=ph[12][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27345 Q=ph[12][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27343 Q=ph[12][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27341 Q=ph[12][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27339 Q=ph[12][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27337 Q=ph[12][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27335 Q=ph[12][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27333 Q=ph[12][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27331 Q=ph[12][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27329 Q=ph[12][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27327 Q=ph[12][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27325 Q=ph[12][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27323 Q=ph[12][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27321 Q=ph[12][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27319 Q=ph[12][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27317 Q=ph[12][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27315 Q=ph[12][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28183 Q=ph[12][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27313 Q=xv[11][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27311 Q=xv[11][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27309 Q=xv[11][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27307 Q=xv[11][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27305 Q=xv[11][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27303 Q=xv[11][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27301 Q=xv[11][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27299 Q=xv[11][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27297 Q=xv[11][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27295 Q=xv[11][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27293 Q=xv[11][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27291 Q=xv[11][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27289 Q=xv[11][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27287 Q=xv[11][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27285 Q=xv[11][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27283 Q=xv[11][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27281 Q=xv[11][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27279 Q=xv[11][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27277 Q=xv[11][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27275 Q=xv[11][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28185 Q=xv[11][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27273 Q=yv[11][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27271 Q=yv[11][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27269 Q=yv[11][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27267 Q=yv[11][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27265 Q=yv[11][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27263 Q=yv[11][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27261 Q=yv[11][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27259 Q=yv[11][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27257 Q=yv[11][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27255 Q=yv[11][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27253 Q=yv[11][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27251 Q=yv[11][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27249 Q=yv[11][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27247 Q=yv[11][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27245 Q=yv[11][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27243 Q=yv[11][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27241 Q=yv[11][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27239 Q=yv[11][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27237 Q=yv[11][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27235 Q=yv[11][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28187 Q=yv[11][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27233 Q=ph[11][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27231 Q=ph[11][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27229 Q=ph[11][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27227 Q=ph[11][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27225 Q=ph[11][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27223 Q=ph[11][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27221 Q=ph[11][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27219 Q=ph[11][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27217 Q=ph[11][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27215 Q=ph[11][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27213 Q=ph[11][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27211 Q=ph[11][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27209 Q=ph[11][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27207 Q=ph[11][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27205 Q=ph[11][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27203 Q=ph[11][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27201 Q=ph[11][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27199 Q=ph[11][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27197 Q=ph[11][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27195 Q=ph[11][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28189 Q=ph[11][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27193 Q=xv[10][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27191 Q=xv[10][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27189 Q=xv[10][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27187 Q=xv[10][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27185 Q=xv[10][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27183 Q=xv[10][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27181 Q=xv[10][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27179 Q=xv[10][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27177 Q=xv[10][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27175 Q=xv[10][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27173 Q=xv[10][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27171 Q=xv[10][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27169 Q=xv[10][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27167 Q=xv[10][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27165 Q=xv[10][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27163 Q=xv[10][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27161 Q=xv[10][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27159 Q=xv[10][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27157 Q=xv[10][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27155 Q=xv[10][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28191 Q=xv[10][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27153 Q=yv[10][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27151 Q=yv[10][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27149 Q=yv[10][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27147 Q=yv[10][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27145 Q=yv[10][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27143 Q=yv[10][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27141 Q=yv[10][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27139 Q=yv[10][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27137 Q=yv[10][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27135 Q=yv[10][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27133 Q=yv[10][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27131 Q=yv[10][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27129 Q=yv[10][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27127 Q=yv[10][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27125 Q=yv[10][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27123 Q=yv[10][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27121 Q=yv[10][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27119 Q=yv[10][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27117 Q=yv[10][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27115 Q=yv[10][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28193 Q=yv[10][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27113 Q=ph[10][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27111 Q=ph[10][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27109 Q=ph[10][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27107 Q=ph[10][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27105 Q=ph[10][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27103 Q=ph[10][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27101 Q=ph[10][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27099 Q=ph[10][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27097 Q=ph[10][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27095 Q=ph[10][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27093 Q=ph[10][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27091 Q=ph[10][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27089 Q=ph[10][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27087 Q=ph[10][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27085 Q=ph[10][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27083 Q=ph[10][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27081 Q=ph[10][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27079 Q=ph[10][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27077 Q=ph[10][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27075 Q=ph[10][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28195 Q=ph[10][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27073 Q=xv[9][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27071 Q=xv[9][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27069 Q=xv[9][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27067 Q=xv[9][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27065 Q=xv[9][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27063 Q=xv[9][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27061 Q=xv[9][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27059 Q=xv[9][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27057 Q=xv[9][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27055 Q=xv[9][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27053 Q=xv[9][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27051 Q=xv[9][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27049 Q=xv[9][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27047 Q=xv[9][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27045 Q=xv[9][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27043 Q=xv[9][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27041 Q=xv[9][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27039 Q=xv[9][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27037 Q=xv[9][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27035 Q=xv[9][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28197 Q=xv[9][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27033 Q=yv[9][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27031 Q=yv[9][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27029 Q=yv[9][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27027 Q=yv[9][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27025 Q=yv[9][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27023 Q=yv[9][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27021 Q=yv[9][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27019 Q=yv[9][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27017 Q=yv[9][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27015 Q=yv[9][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27013 Q=yv[9][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27011 Q=yv[9][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27009 Q=yv[9][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27007 Q=yv[9][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27005 Q=yv[9][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27003 Q=yv[9][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27001 Q=yv[9][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26999 Q=yv[9][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26997 Q=yv[9][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26995 Q=yv[9][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28199 Q=yv[9][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26993 Q=ph[9][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26991 Q=ph[9][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26989 Q=ph[9][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26987 Q=ph[9][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26985 Q=ph[9][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26983 Q=ph[9][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26981 Q=ph[9][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26979 Q=ph[9][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26977 Q=ph[9][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26975 Q=ph[9][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26973 Q=ph[9][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26971 Q=ph[9][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26969 Q=ph[9][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26967 Q=ph[9][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26965 Q=ph[9][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26963 Q=ph[9][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26961 Q=ph[9][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26959 Q=ph[9][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26957 Q=ph[9][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26955 Q=ph[9][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28201 Q=ph[9][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26953 Q=xv[8][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26951 Q=xv[8][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26949 Q=xv[8][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26947 Q=xv[8][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26945 Q=xv[8][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26943 Q=xv[8][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26941 Q=xv[8][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26939 Q=xv[8][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26937 Q=xv[8][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26935 Q=xv[8][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26933 Q=xv[8][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26931 Q=xv[8][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26929 Q=xv[8][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26927 Q=xv[8][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26925 Q=xv[8][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26923 Q=xv[8][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26921 Q=xv[8][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26919 Q=xv[8][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26917 Q=xv[8][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26915 Q=xv[8][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28203 Q=xv[8][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26913 Q=yv[8][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26911 Q=yv[8][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26909 Q=yv[8][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26907 Q=yv[8][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26905 Q=yv[8][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26903 Q=yv[8][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26901 Q=yv[8][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26899 Q=yv[8][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26897 Q=yv[8][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26895 Q=yv[8][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26893 Q=yv[8][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26891 Q=yv[8][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26889 Q=yv[8][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26887 Q=yv[8][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26885 Q=yv[8][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26883 Q=yv[8][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26881 Q=yv[8][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26879 Q=yv[8][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26877 Q=yv[8][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26875 Q=yv[8][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28205 Q=yv[8][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26873 Q=ph[8][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26871 Q=ph[8][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26869 Q=ph[8][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26867 Q=ph[8][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26865 Q=ph[8][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26863 Q=ph[8][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26861 Q=ph[8][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26859 Q=ph[8][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26857 Q=ph[8][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26855 Q=ph[8][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26853 Q=ph[8][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26851 Q=ph[8][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26849 Q=ph[8][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26847 Q=ph[8][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26845 Q=ph[8][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26843 Q=ph[8][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26841 Q=ph[8][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26839 Q=ph[8][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26837 Q=ph[8][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26835 Q=ph[8][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28207 Q=ph[8][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26833 Q=xv[7][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26831 Q=xv[7][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26829 Q=xv[7][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26827 Q=xv[7][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26825 Q=xv[7][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26823 Q=xv[7][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26821 Q=xv[7][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26819 Q=xv[7][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26817 Q=xv[7][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26815 Q=xv[7][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26813 Q=xv[7][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26811 Q=xv[7][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26809 Q=xv[7][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26807 Q=xv[7][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26805 Q=xv[7][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26803 Q=xv[7][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26801 Q=xv[7][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26799 Q=xv[7][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26797 Q=xv[7][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26795 Q=xv[7][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28209 Q=xv[7][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26793 Q=yv[7][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26791 Q=yv[7][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26789 Q=yv[7][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26787 Q=yv[7][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26785 Q=yv[7][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26783 Q=yv[7][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26781 Q=yv[7][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26779 Q=yv[7][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26777 Q=yv[7][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26775 Q=yv[7][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26773 Q=yv[7][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26771 Q=yv[7][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26769 Q=yv[7][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26767 Q=yv[7][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26765 Q=yv[7][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26763 Q=yv[7][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26761 Q=yv[7][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26759 Q=yv[7][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26757 Q=yv[7][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26755 Q=yv[7][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28211 Q=yv[7][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26753 Q=ph[7][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26751 Q=ph[7][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26749 Q=ph[7][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26747 Q=ph[7][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26745 Q=ph[7][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26743 Q=ph[7][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26741 Q=ph[7][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26739 Q=ph[7][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26737 Q=ph[7][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26735 Q=ph[7][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26733 Q=ph[7][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26731 Q=ph[7][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26729 Q=ph[7][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26727 Q=ph[7][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26725 Q=ph[7][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26723 Q=ph[7][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26721 Q=ph[7][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26719 Q=ph[7][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26717 Q=ph[7][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26715 Q=ph[7][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28213 Q=ph[7][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26713 Q=xv[6][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26711 Q=xv[6][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26709 Q=xv[6][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26707 Q=xv[6][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26705 Q=xv[6][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26703 Q=xv[6][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26701 Q=xv[6][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26699 Q=xv[6][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26697 Q=xv[6][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26695 Q=xv[6][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26693 Q=xv[6][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26691 Q=xv[6][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26689 Q=xv[6][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26687 Q=xv[6][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26685 Q=xv[6][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26683 Q=xv[6][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26681 Q=xv[6][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26679 Q=xv[6][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26677 Q=xv[6][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26675 Q=xv[6][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28215 Q=xv[6][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26673 Q=yv[6][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26671 Q=yv[6][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26669 Q=yv[6][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26667 Q=yv[6][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26665 Q=yv[6][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26663 Q=yv[6][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26661 Q=yv[6][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26659 Q=yv[6][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26657 Q=yv[6][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26655 Q=yv[6][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26653 Q=yv[6][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26651 Q=yv[6][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26649 Q=yv[6][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26647 Q=yv[6][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26645 Q=yv[6][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26643 Q=yv[6][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26641 Q=yv[6][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26639 Q=yv[6][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26637 Q=yv[6][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26635 Q=yv[6][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28217 Q=yv[6][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26633 Q=ph[6][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26631 Q=ph[6][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26629 Q=ph[6][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26627 Q=ph[6][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26625 Q=ph[6][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26623 Q=ph[6][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26621 Q=ph[6][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26619 Q=ph[6][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26617 Q=ph[6][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26615 Q=ph[6][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26613 Q=ph[6][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26611 Q=ph[6][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26609 Q=ph[6][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26607 Q=ph[6][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26605 Q=ph[6][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26603 Q=ph[6][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26601 Q=ph[6][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26599 Q=ph[6][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26597 Q=ph[6][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26595 Q=ph[6][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28219 Q=ph[6][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26593 Q=xv[5][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26591 Q=xv[5][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26589 Q=xv[5][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26587 Q=xv[5][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26585 Q=xv[5][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26583 Q=xv[5][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26581 Q=xv[5][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26579 Q=xv[5][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26577 Q=xv[5][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26575 Q=xv[5][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26573 Q=xv[5][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26571 Q=xv[5][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26569 Q=xv[5][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26567 Q=xv[5][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26565 Q=xv[5][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26563 Q=xv[5][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26561 Q=xv[5][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26559 Q=xv[5][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26557 Q=xv[5][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26555 Q=xv[5][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28221 Q=xv[5][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26553 Q=yv[5][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26551 Q=yv[5][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26549 Q=yv[5][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26547 Q=yv[5][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26545 Q=yv[5][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26543 Q=yv[5][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26541 Q=yv[5][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26539 Q=yv[5][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26537 Q=yv[5][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26535 Q=yv[5][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26533 Q=yv[5][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26531 Q=yv[5][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26529 Q=yv[5][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26527 Q=yv[5][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26525 Q=yv[5][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26523 Q=yv[5][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26521 Q=yv[5][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26519 Q=yv[5][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26517 Q=yv[5][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26515 Q=yv[5][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28223 Q=yv[5][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26513 Q=ph[5][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26511 Q=ph[5][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26509 Q=ph[5][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26507 Q=ph[5][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26505 Q=ph[5][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26503 Q=ph[5][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26501 Q=ph[5][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26499 Q=ph[5][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26497 Q=ph[5][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26495 Q=ph[5][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26493 Q=ph[5][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26491 Q=ph[5][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26489 Q=ph[5][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26487 Q=ph[5][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26485 Q=ph[5][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26483 Q=ph[5][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26481 Q=ph[5][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26479 Q=ph[5][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26477 Q=ph[5][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26475 Q=ph[5][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28225 Q=ph[5][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26473 Q=xv[4][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26471 Q=xv[4][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26469 Q=xv[4][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26467 Q=xv[4][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26465 Q=xv[4][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26463 Q=xv[4][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26461 Q=xv[4][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26459 Q=xv[4][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26457 Q=xv[4][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26455 Q=xv[4][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26453 Q=xv[4][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26451 Q=xv[4][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26449 Q=xv[4][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26447 Q=xv[4][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26445 Q=xv[4][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26443 Q=xv[4][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26441 Q=xv[4][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26439 Q=xv[4][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26437 Q=xv[4][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26435 Q=xv[4][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28227 Q=xv[4][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26433 Q=yv[4][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26431 Q=yv[4][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26429 Q=yv[4][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26427 Q=yv[4][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26425 Q=yv[4][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26423 Q=yv[4][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26421 Q=yv[4][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26419 Q=yv[4][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26417 Q=yv[4][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26415 Q=yv[4][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26413 Q=yv[4][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26411 Q=yv[4][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26409 Q=yv[4][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26407 Q=yv[4][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26405 Q=yv[4][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26403 Q=yv[4][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26401 Q=yv[4][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26399 Q=yv[4][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26397 Q=yv[4][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26395 Q=yv[4][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28229 Q=yv[4][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26393 Q=ph[4][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26391 Q=ph[4][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26389 Q=ph[4][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26387 Q=ph[4][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26385 Q=ph[4][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26383 Q=ph[4][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26381 Q=ph[4][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26379 Q=ph[4][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26377 Q=ph[4][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26375 Q=ph[4][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26373 Q=ph[4][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26371 Q=ph[4][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26369 Q=ph[4][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26367 Q=ph[4][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26365 Q=ph[4][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26363 Q=ph[4][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26361 Q=ph[4][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26359 Q=ph[4][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26357 Q=ph[4][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26355 Q=ph[4][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28231 Q=ph[4][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26353 Q=xv[3][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26351 Q=xv[3][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26349 Q=xv[3][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26347 Q=xv[3][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26345 Q=xv[3][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26343 Q=xv[3][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26341 Q=xv[3][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26339 Q=xv[3][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26337 Q=xv[3][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26335 Q=xv[3][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26333 Q=xv[3][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26331 Q=xv[3][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26329 Q=xv[3][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26327 Q=xv[3][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26325 Q=xv[3][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26323 Q=xv[3][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26321 Q=xv[3][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26319 Q=xv[3][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26317 Q=xv[3][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26315 Q=xv[3][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28233 Q=xv[3][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26313 Q=yv[3][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26311 Q=yv[3][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26309 Q=yv[3][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26307 Q=yv[3][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26305 Q=yv[3][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26303 Q=yv[3][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26301 Q=yv[3][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26299 Q=yv[3][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26297 Q=yv[3][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26295 Q=yv[3][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26293 Q=yv[3][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26291 Q=yv[3][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26289 Q=yv[3][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26287 Q=yv[3][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26285 Q=yv[3][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26283 Q=yv[3][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26281 Q=yv[3][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26279 Q=yv[3][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26277 Q=yv[3][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26275 Q=yv[3][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28235 Q=yv[3][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26273 Q=ph[3][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26271 Q=ph[3][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26269 Q=ph[3][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26267 Q=ph[3][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26265 Q=ph[3][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26263 Q=ph[3][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26261 Q=ph[3][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26259 Q=ph[3][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26257 Q=ph[3][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26255 Q=ph[3][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26253 Q=ph[3][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26251 Q=ph[3][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26249 Q=ph[3][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26247 Q=ph[3][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26245 Q=ph[3][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26243 Q=ph[3][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26241 Q=ph[3][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26239 Q=ph[3][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26237 Q=ph[3][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26235 Q=ph[3][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28237 Q=ph[3][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26233 Q=xv[2][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26231 Q=xv[2][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26229 Q=xv[2][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26227 Q=xv[2][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26225 Q=xv[2][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26223 Q=xv[2][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26221 Q=xv[2][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26219 Q=xv[2][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26217 Q=xv[2][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26215 Q=xv[2][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26213 Q=xv[2][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26211 Q=xv[2][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26209 Q=xv[2][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26207 Q=xv[2][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26205 Q=xv[2][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26203 Q=xv[2][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26201 Q=xv[2][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26199 Q=xv[2][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26197 Q=xv[2][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26195 Q=xv[2][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28239 Q=xv[2][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26193 Q=yv[2][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26191 Q=yv[2][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26189 Q=yv[2][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26187 Q=yv[2][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26185 Q=yv[2][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26183 Q=yv[2][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26181 Q=yv[2][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26179 Q=yv[2][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26177 Q=yv[2][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26175 Q=yv[2][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26173 Q=yv[2][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26171 Q=yv[2][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26169 Q=yv[2][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26167 Q=yv[2][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26165 Q=yv[2][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26163 Q=yv[2][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26161 Q=yv[2][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26159 Q=yv[2][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26157 Q=yv[2][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26155 Q=yv[2][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28241 Q=yv[2][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26153 Q=ph[2][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26151 Q=ph[2][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26149 Q=ph[2][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26147 Q=ph[2][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26145 Q=ph[2][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26143 Q=ph[2][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26141 Q=ph[2][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26139 Q=ph[2][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26137 Q=ph[2][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26135 Q=ph[2][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26133 Q=ph[2][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26131 Q=ph[2][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26129 Q=ph[2][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26127 Q=ph[2][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26125 Q=ph[2][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26123 Q=ph[2][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26121 Q=ph[2][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26119 Q=ph[2][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26117 Q=ph[2][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26115 Q=ph[2][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28243 Q=ph[2][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26113 Q=xv[1][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26111 Q=xv[1][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26109 Q=xv[1][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26107 Q=xv[1][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26105 Q=xv[1][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26103 Q=xv[1][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26101 Q=xv[1][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26099 Q=xv[1][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26097 Q=xv[1][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26095 Q=xv[1][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26093 Q=xv[1][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26091 Q=xv[1][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26089 Q=xv[1][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26087 Q=xv[1][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26085 Q=xv[1][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26083 Q=xv[1][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26081 Q=xv[1][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26079 Q=xv[1][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26077 Q=xv[1][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26075 Q=xv[1][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28245 Q=xv[1][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26073 Q=yv[1][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26071 Q=yv[1][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26069 Q=yv[1][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26067 Q=yv[1][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26065 Q=yv[1][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26063 Q=yv[1][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26061 Q=yv[1][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26059 Q=yv[1][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26057 Q=yv[1][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26055 Q=yv[1][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26053 Q=yv[1][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26051 Q=yv[1][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26049 Q=yv[1][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26047 Q=yv[1][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26045 Q=yv[1][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26043 Q=yv[1][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26041 Q=yv[1][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26039 Q=yv[1][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26037 Q=yv[1][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26035 Q=yv[1][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28247 Q=yv[1][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26033 Q=o_mag[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26031 Q=o_mag[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26029 Q=o_mag[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26027 Q=o_mag[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26025 Q=o_mag[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26023 Q=o_mag[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26021 Q=o_mag[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26019 Q=o_mag[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26017 Q=o_mag[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26015 Q=o_mag[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26013 Q=o_mag[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26011 Q=o_mag[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28249 Q=o_mag[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26009 Q=o_phase[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26007 Q=o_phase[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26005 Q=o_phase[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26003 Q=o_phase[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26001 Q=o_phase[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25999 Q=o_phase[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25997 Q=o_phase[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25995 Q=o_phase[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25993 Q=o_phase[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25991 Q=o_phase[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25989 Q=o_phase[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25987 Q=o_phase[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25985 Q=o_phase[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25983 Q=o_phase[13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25981 Q=o_phase[14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25979 Q=o_phase[15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25977 Q=o_phase[16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25975 Q=o_phase[17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25973 Q=o_phase[18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25971 Q=o_phase[19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28251 Q=o_phase[20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28253 Q=o_aux R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25969 Q=xv[0][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25967 Q=xv[0][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25965 Q=xv[0][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25963 Q=xv[0][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25961 Q=xv[0][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25959 Q=xv[0][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25957 Q=xv[0][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25955 Q=xv[0][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25953 Q=xv[0][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25951 Q=xv[0][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25949 Q=xv[0][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25947 Q=xv[0][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25945 Q=xv[0][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25943 Q=xv[0][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25941 Q=xv[0][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25939 Q=xv[0][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25937 Q=xv[0][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25935 Q=xv[0][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25933 Q=xv[0][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25931 Q=xv[0][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28255 Q=xv[0][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25929 Q=yv[0][0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25927 Q=yv[0][1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25925 Q=yv[0][2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25923 Q=yv[0][3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25921 Q=yv[0][4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25919 Q=yv[0][5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25917 Q=yv[0][6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25915 Q=yv[0][7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25913 Q=yv[0][8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25911 Q=yv[0][9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25909 Q=yv[0][10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25907 Q=yv[0][11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25905 Q=yv[0][12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25903 Q=yv[0][13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25901 Q=yv[0][14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25899 Q=yv[0][15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25897 Q=yv[0][16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25895 Q=yv[0][17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25893 Q=yv[0][18] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25891 Q=yv[0][19] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28257 Q=yv[0][20] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25889 Q=ax[0] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25887 Q=ax[1] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25885 Q=ax[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25883 Q=ax[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25881 Q=ax[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25879 Q=ax[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25877 Q=ax[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25875 Q=ax[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25873 Q=ax[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25871 Q=ax[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25869 Q=ax[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25867 Q=ax[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25865 Q=ax[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25863 Q=ax[13] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25861 Q=ax[14] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25859 Q=ax[15] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25857 Q=ax[16] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25855 Q=ax[17] R=i_reset -.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28259 Q=ax[18] R=i_reset -.names $false ph[0][0] -1 1 -.names $false ph[0][1] -1 1 -.names $false ph[0][2] -1 1 -.names $false ph[0][3] -1 1 -.names $false ph[0][4] -1 1 -.names $false ph[0][5] -1 1 -.names $false ph[0][6] -1 1 -.names $false ph[0][7] -1 1 -.names $false ph[0][8] -1 1 -.names $false ph[0][9] -1 1 -.names $false ph[0][10] -1 1 -.names $false ph[0][11] -1 1 -.names $false ph[0][12] -1 1 -.names $false ph[0][13] -1 1 -.names $false ph[0][14] -1 1 -.names $false ph[0][15] -1 1 -.names $false ph[0][16] -1 1 -.names $false ph[0][17] -1 1 -.names $false ph[1][0] -1 1 -.names $false ph[1][1] -1 1 -.names $false ph[1][2] -1 1 -.names $false ph[1][3] -1 1 -.names $false ph[1][4] -1 1 -.names $false ph[1][5] -1 1 -.names $false ph[1][6] -1 1 -.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif deleted file mode 100644 index ad4923c7d2e..00000000000 --- a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif +++ /dev/null @@ -1,54152 +0,0 @@ -# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) - -.model zipcore -.inputs i_clk i_reset i_interrupt i_halt i_clear_cache i_dbg_wreg[0] i_dbg_wreg[1] i_dbg_wreg[2] i_dbg_wreg[3] i_dbg_wreg[4] i_dbg_we i_dbg_data[0] i_dbg_data[1] i_dbg_data[2] i_dbg_data[3] i_dbg_data[4] i_dbg_data[5] i_dbg_data[6] i_dbg_data[7] i_dbg_data[8] i_dbg_data[9] i_dbg_data[10] i_dbg_data[11] i_dbg_data[12] i_dbg_data[13] i_dbg_data[14] i_dbg_data[15] i_dbg_data[16] i_dbg_data[17] i_dbg_data[18] i_dbg_data[19] i_dbg_data[20] i_dbg_data[21] i_dbg_data[22] i_dbg_data[23] i_dbg_data[24] i_dbg_data[25] i_dbg_data[26] i_dbg_data[27] i_dbg_data[28] i_dbg_data[29] i_dbg_data[30] i_dbg_data[31] i_dbg_rreg[0] i_dbg_rreg[1] i_dbg_rreg[2] i_dbg_rreg[3] i_dbg_rreg[4] i_pf_valid i_pf_illegal i_pf_instruction[0] i_pf_instruction[1] i_pf_instruction[2] i_pf_instruction[3] i_pf_instruction[4] i_pf_instruction[5] i_pf_instruction[6] i_pf_instruction[7] i_pf_instruction[8] i_pf_instruction[9] i_pf_instruction[10] i_pf_instruction[11] i_pf_instruction[12] i_pf_instruction[13] i_pf_instruction[14] i_pf_instruction[15] i_pf_instruction[16] i_pf_instruction[17] i_pf_instruction[18] i_pf_instruction[19] i_pf_instruction[20] i_pf_instruction[21] i_pf_instruction[22] i_pf_instruction[23] i_pf_instruction[24] i_pf_instruction[25] i_pf_instruction[26] i_pf_instruction[27] i_pf_instruction[28] i_pf_instruction[29] i_pf_instruction[30] i_pf_instruction[31] i_pf_instruction_pc[0] i_pf_instruction_pc[1] i_pf_instruction_pc[2] i_pf_instruction_pc[3] i_pf_instruction_pc[4] i_pf_instruction_pc[5] i_pf_instruction_pc[6] i_pf_instruction_pc[7] i_pf_instruction_pc[8] i_pf_instruction_pc[9] i_pf_instruction_pc[10] i_pf_instruction_pc[11] i_pf_instruction_pc[12] i_pf_instruction_pc[13] i_pf_instruction_pc[14] i_pf_instruction_pc[15] i_pf_instruction_pc[16] i_pf_instruction_pc[17] i_pf_instruction_pc[18] i_pf_instruction_pc[19] i_pf_instruction_pc[20] i_pf_instruction_pc[21] i_pf_instruction_pc[22] i_pf_instruction_pc[23] i_pf_instruction_pc[24] i_pf_instruction_pc[25] i_pf_instruction_pc[26] i_pf_instruction_pc[27] i_pf_instruction_pc[28] i_pf_instruction_pc[29] i_pf_instruction_pc[30] i_pf_instruction_pc[31] i_mem_busy i_mem_rdbusy i_mem_pipe_stalled i_mem_valid i_bus_err i_mem_wreg[0] i_mem_wreg[1] i_mem_wreg[2] i_mem_wreg[3] i_mem_wreg[4] i_mem_result[0] i_mem_result[1] i_mem_result[2] i_mem_result[3] i_mem_result[4] i_mem_result[5] i_mem_result[6] i_mem_result[7] i_mem_result[8] i_mem_result[9] i_mem_result[10] i_mem_result[11] i_mem_result[12] i_mem_result[13] i_mem_result[14] i_mem_result[15] i_mem_result[16] i_mem_result[17] i_mem_result[18] i_mem_result[19] i_mem_result[20] i_mem_result[21] i_mem_result[22] i_mem_result[23] i_mem_result[24] i_mem_result[25] i_mem_result[26] i_mem_result[27] i_mem_result[28] i_mem_result[29] i_mem_result[30] i_mem_result[31] -.outputs o_clken o_dbg_stall o_dbg_reg[0] o_dbg_reg[1] o_dbg_reg[2] o_dbg_reg[3] o_dbg_reg[4] o_dbg_reg[5] o_dbg_reg[6] o_dbg_reg[7] o_dbg_reg[8] o_dbg_reg[9] o_dbg_reg[10] o_dbg_reg[11] o_dbg_reg[12] o_dbg_reg[13] o_dbg_reg[14] o_dbg_reg[15] o_dbg_reg[16] o_dbg_reg[17] o_dbg_reg[18] o_dbg_reg[19] o_dbg_reg[20] o_dbg_reg[21] o_dbg_reg[22] o_dbg_reg[23] o_dbg_reg[24] o_dbg_reg[25] o_dbg_reg[26] o_dbg_reg[27] o_dbg_reg[28] o_dbg_reg[29] o_dbg_reg[30] o_dbg_reg[31] o_dbg_cc[0] o_dbg_cc[1] o_dbg_cc[2] o_break o_pf_new_pc o_clear_icache o_pf_ready o_pf_request_address[0] o_pf_request_address[1] o_pf_request_address[2] o_pf_request_address[3] o_pf_request_address[4] o_pf_request_address[5] o_pf_request_address[6] o_pf_request_address[7] o_pf_request_address[8] o_pf_request_address[9] o_pf_request_address[10] o_pf_request_address[11] o_pf_request_address[12] o_pf_request_address[13] o_pf_request_address[14] o_pf_request_address[15] o_pf_request_address[16] o_pf_request_address[17] o_pf_request_address[18] o_pf_request_address[19] o_pf_request_address[20] o_pf_request_address[21] o_pf_request_address[22] o_pf_request_address[23] o_pf_request_address[24] o_pf_request_address[25] o_pf_request_address[26] o_pf_request_address[27] o_pf_request_address[28] o_pf_request_address[29] o_pf_request_address[30] o_pf_request_address[31] o_clear_dcache o_mem_ce o_bus_lock o_mem_op[0] o_mem_op[1] o_mem_op[2] o_mem_addr[0] o_mem_addr[1] o_mem_addr[2] o_mem_addr[3] o_mem_addr[4] o_mem_addr[5] o_mem_addr[6] o_mem_addr[7] o_mem_addr[8] o_mem_addr[9] o_mem_addr[10] o_mem_addr[11] o_mem_addr[12] o_mem_addr[13] o_mem_addr[14] o_mem_addr[15] o_mem_addr[16] o_mem_addr[17] o_mem_addr[18] o_mem_addr[19] o_mem_addr[20] o_mem_addr[21] o_mem_addr[22] o_mem_addr[23] o_mem_addr[24] o_mem_addr[25] o_mem_addr[26] o_mem_addr[27] o_mem_addr[28] o_mem_addr[29] o_mem_addr[30] o_mem_addr[31] o_mem_data[0] o_mem_data[1] o_mem_data[2] o_mem_data[3] o_mem_data[4] o_mem_data[5] o_mem_data[6] o_mem_data[7] o_mem_data[8] o_mem_data[9] o_mem_data[10] o_mem_data[11] o_mem_data[12] o_mem_data[13] o_mem_data[14] o_mem_data[15] o_mem_data[16] o_mem_data[17] o_mem_data[18] o_mem_data[19] o_mem_data[20] o_mem_data[21] o_mem_data[22] o_mem_data[23] o_mem_data[24] o_mem_data[25] o_mem_data[26] o_mem_data[27] o_mem_data[28] o_mem_data[29] o_mem_data[30] o_mem_data[31] o_mem_lock_pc[0] o_mem_lock_pc[1] o_mem_lock_pc[2] o_mem_lock_pc[3] o_mem_lock_pc[4] o_mem_lock_pc[5] o_mem_lock_pc[6] o_mem_lock_pc[7] o_mem_lock_pc[8] o_mem_lock_pc[9] o_mem_lock_pc[10] o_mem_lock_pc[11] o_mem_lock_pc[12] o_mem_lock_pc[13] o_mem_lock_pc[14] o_mem_lock_pc[15] o_mem_lock_pc[16] o_mem_lock_pc[17] o_mem_lock_pc[18] o_mem_lock_pc[19] o_mem_lock_pc[20] o_mem_lock_pc[21] o_mem_lock_pc[22] o_mem_lock_pc[23] o_mem_lock_pc[24] o_mem_lock_pc[25] o_mem_lock_pc[26] o_mem_lock_pc[27] o_mem_lock_pc[28] o_mem_lock_pc[29] o_mem_lock_pc[30] o_mem_lock_pc[31] o_mem_reg[0] o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] o_mem_reg[4] o_op_stall o_pf_stall o_i_count o_debug[0] o_debug[1] o_debug[2] o_debug[3] o_debug[4] o_debug[5] o_debug[6] o_debug[7] o_debug[8] o_debug[9] o_debug[10] o_debug[11] o_debug[12] o_debug[13] o_debug[14] o_debug[15] o_debug[16] o_debug[17] o_debug[18] o_debug[19] o_debug[20] o_debug[21] o_debug[22] o_debug[23] o_debug[24] o_debug[25] o_debug[26] o_debug[27] o_debug[28] o_debug[29] o_debug[30] o_debug[31] o_prof_stb o_prof_addr[0] o_prof_addr[1] o_prof_addr[2] o_prof_addr[3] o_prof_addr[4] o_prof_addr[5] o_prof_addr[6] o_prof_addr[7] o_prof_addr[8] o_prof_addr[9] o_prof_addr[10] o_prof_addr[11] o_prof_addr[12] o_prof_addr[13] o_prof_addr[14] o_prof_addr[15] o_prof_addr[16] o_prof_addr[17] o_prof_addr[18] o_prof_addr[19] o_prof_addr[20] o_prof_addr[21] o_prof_addr[22] o_prof_addr[23] o_prof_addr[24] o_prof_addr[25] o_prof_addr[26] o_prof_addr[27] o_prof_addr[28] o_prof_addr[29] o_prof_addr[30] o_prof_addr[31] o_prof_ticks[0] o_prof_ticks[1] o_prof_ticks[2] o_prof_ticks[3] o_prof_ticks[4] o_prof_ticks[5] o_prof_ticks[6] o_prof_ticks[7] o_prof_ticks[8] o_prof_ticks[9] o_prof_ticks[10] o_prof_ticks[11] o_prof_ticks[12] o_prof_ticks[13] o_prof_ticks[14] o_prof_ticks[15] o_prof_ticks[16] o_prof_ticks[17] o_prof_ticks[18] o_prof_ticks[19] o_prof_ticks[20] o_prof_ticks[21] o_prof_ticks[22] o_prof_ticks[23] o_prof_ticks[24] o_prof_ticks[25] o_prof_ticks[26] o_prof_ticks[27] o_prof_ticks[28] o_prof_ticks[29] o_prof_ticks[30] o_prof_ticks[31] -.names $false -.names $true -1 -.names $undef -.names $abc$24881$new_n3673 DIVIDE.thedivide.r_dividend[27] DIVIDE.thedivide.r_dividend[28] $abc$24881$new_n3672 -100 1 -.names $abc$24881$new_n3674 DIVIDE.thedivide.r_dividend[25] DIVIDE.thedivide.r_dividend[26] $abc$24881$new_n3673 -100 1 -.names $abc$24881$new_n3675 DIVIDE.thedivide.r_dividend[24] $abc$24881$new_n3674 -10 1 -.names $abc$24881$new_n3676 DIVIDE.thedivide.r_dividend[21] DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.r_dividend[23] $abc$24881$new_n3675 -1000 1 -.names $abc$24881$new_n3677 DIVIDE.thedivide.r_dividend[20] $abc$24881$new_n3676 -10 1 -.names $abc$24881$new_n3678 DIVIDE.thedivide.r_dividend[17] DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.r_dividend[19] $abc$24881$new_n3677 -1000 1 -.names $abc$24881$new_n3679 DIVIDE.thedivide.r_dividend[16] $abc$24881$new_n3678 -10 1 -.names $abc$24881$new_n3680 DIVIDE.thedivide.r_dividend[15] $abc$24881$new_n3679 -10 1 -.names $abc$24881$new_n3681 DIVIDE.thedivide.r_dividend[13] DIVIDE.thedivide.r_dividend[14] $abc$24881$new_n3680 -100 1 -.names $abc$24881$new_n3682 DIVIDE.thedivide.r_dividend[12] $abc$24881$new_n3681 -10 1 -.names $abc$24881$new_n3683 DIVIDE.thedivide.r_dividend[11] $abc$24881$new_n3682 -10 1 -.names $abc$24881$new_n3684 DIVIDE.thedivide.r_dividend[10] $abc$24881$new_n3683 -10 1 -.names $abc$24881$new_n3685 DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3684 -10 1 -.names $abc$24881$new_n3686 DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3685 -10 1 -.names $abc$24881$new_n3687 DIVIDE.thedivide.r_dividend[6] DIVIDE.thedivide.r_dividend[7] $abc$24881$new_n3686 -100 1 -.names $abc$24881$new_n3688 DIVIDE.thedivide.r_dividend[3] DIVIDE.thedivide.r_dividend[4] DIVIDE.thedivide.r_dividend[5] $abc$24881$new_n3687 -1000 1 -.names $abc$24881$new_n3689 DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3688 -10 1 -.names DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_dividend[1] $abc$24881$new_n3689 -00 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3702 r_op_Av[30] o_mem_data[30] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3692 -111 1 -.names o_mem_reg[4] o_mem_reg[3] $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n3693 -0011 1 -0101 1 -1010 1 -1100 1 -.names i_mem_valid alu_reg[4] i_mem_wreg[4] $abc$24881$new_n3694 -000 1 -001 1 -100 1 -110 1 -.names i_mem_valid alu_reg[3] i_mem_wreg[3] $abc$24881$new_n3695 -000 1 -001 1 -100 1 -110 1 -.names o_mem_reg[0] o_mem_reg[1] $abc$24881$new_n3698 $abc$24881$new_n3697 $abc$24881$new_n3696 -0011 1 -0101 1 -1010 1 -1100 1 -.names i_mem_valid alu_reg[0] i_mem_wreg[0] $abc$24881$new_n3697 -000 1 -001 1 -100 1 -110 1 -.names i_mem_valid alu_reg[1] i_mem_wreg[1] $abc$24881$new_n3698 -000 1 -001 1 -100 1 -110 1 -.names o_mem_reg[2] $abc$24881$new_n3701 i_mem_valid dbgv $abc$24881$new_n3700 $abc$24881$new_n3699 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names new_pc DIVIDE.thedivide.o_valid DIVIDE.thedivide.o_err doalu.o_valid alu_wR $abc$24881$new_n3700 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -.names i_mem_valid alu_reg[2] i_mem_wreg[2] $abc$24881$new_n3701 -000 1 -001 1 -100 1 -110 1 -.names $abc$24881$new_n3703 i_mem_result[30] wr_index[0] wr_index[1] $abc$24881$new_n3702 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[30] alu_result[30] dbg_val[30] $abc$24881$new_n3703 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3704 -10 1 -.names DIVIDE.thedivide.r_dividend[29] $abc$24881$new_n3704 DIVIDE.thedivide.pre_sign $abc$24881$new_n3672 $abc$24881$new_n3706 $abc$24881$auto$rtlil.cc:2693:MuxGate$22568 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[29] DIVIDE.thedivide.r_dividend[28] $abc$24881$new_n3706 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3708 r_op_Av[29] o_mem_data[29] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3709 i_mem_result[29] wr_index[0] wr_index[1] $abc$24881$new_n3708 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[29] alu_result[29] dbg_val[29] $abc$24881$new_n3709 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3714 r_op_Av[28] o_mem_data[28] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3715 i_mem_result[28] wr_index[0] wr_index[1] $abc$24881$new_n3714 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[28] alu_result[28] dbg_val[28] $abc$24881$new_n3715 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3717 DIVIDE.thedivide.r_dividend[27] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3673 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22572 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[27] DIVIDE.thedivide.r_dividend[26] $abc$24881$new_n3717 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3719 r_op_Av[27] o_mem_data[27] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3720 i_mem_result[27] wr_index[0] wr_index[1] $abc$24881$new_n3719 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[27] alu_result[27] dbg_val[27] $abc$24881$new_n3720 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3725 r_op_Av[26] o_mem_data[26] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3726 i_mem_result[26] wr_index[0] wr_index[1] $abc$24881$new_n3725 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[26] alu_result[26] dbg_val[26] $abc$24881$new_n3726 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3728 DIVIDE.thedivide.r_dividend[25] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3674 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22576 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[25] DIVIDE.thedivide.r_dividend[24] $abc$24881$new_n3728 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3730 r_op_Av[25] o_mem_data[25] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3731 i_mem_result[25] wr_index[0] wr_index[1] $abc$24881$new_n3730 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[25] alu_result[25] dbg_val[25] $abc$24881$new_n3731 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3733 DIVIDE.thedivide.r_dividend[24] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3675 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22578 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[24] DIVIDE.thedivide.r_dividend[23] $abc$24881$new_n3733 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3735 r_op_Av[24] o_mem_data[24] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3736 i_mem_result[24] wr_index[0] wr_index[1] $abc$24881$new_n3735 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[24] alu_result[24] dbg_val[24] $abc$24881$new_n3736 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3741 r_op_Av[23] o_mem_data[23] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3742 i_mem_result[23] wr_index[0] wr_index[1] $abc$24881$new_n3741 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[23] alu_result[23] dbg_val[23] $abc$24881$new_n3742 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3747 r_op_Av[22] o_mem_data[22] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3748 i_mem_result[22] wr_index[0] wr_index[1] $abc$24881$new_n3747 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[22] alu_result[22] dbg_val[22] $abc$24881$new_n3748 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3750 DIVIDE.thedivide.r_dividend[21] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3676 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22584 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[21] DIVIDE.thedivide.r_dividend[20] $abc$24881$new_n3750 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3752 r_op_Av[21] o_mem_data[21] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3753 i_mem_result[21] wr_index[0] wr_index[1] $abc$24881$new_n3752 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[21] alu_result[21] dbg_val[21] $abc$24881$new_n3753 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3755 DIVIDE.thedivide.r_dividend[20] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3677 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22586 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[20] DIVIDE.thedivide.r_dividend[19] $abc$24881$new_n3755 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3757 r_op_Av[20] o_mem_data[20] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3758 i_mem_result[20] wr_index[0] wr_index[1] $abc$24881$new_n3757 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[20] alu_result[20] dbg_val[20] $abc$24881$new_n3758 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3763 r_op_Av[19] o_mem_data[19] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3764 i_mem_result[19] wr_index[0] wr_index[1] $abc$24881$new_n3763 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[19] alu_result[19] dbg_val[19] $abc$24881$new_n3764 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3769 r_op_Av[18] o_mem_data[18] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3770 i_mem_result[18] wr_index[0] wr_index[1] $abc$24881$new_n3769 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[18] alu_result[18] dbg_val[18] $abc$24881$new_n3770 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3772 DIVIDE.thedivide.r_dividend[17] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3678 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22592 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[17] DIVIDE.thedivide.r_dividend[16] $abc$24881$new_n3772 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3774 r_op_Av[17] o_mem_data[17] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3775 i_mem_result[17] wr_index[0] wr_index[1] $abc$24881$new_n3774 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[17] alu_result[17] dbg_val[17] $abc$24881$new_n3775 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3777 DIVIDE.thedivide.r_dividend[16] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3679 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22594 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[16] DIVIDE.thedivide.r_dividend[15] $abc$24881$new_n3777 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3779 r_op_Av[16] o_mem_data[16] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3780 i_mem_result[16] wr_index[0] wr_index[1] $abc$24881$new_n3779 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[16] alu_result[16] dbg_val[16] $abc$24881$new_n3780 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3782 DIVIDE.thedivide.r_dividend[15] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3680 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22596 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[15] DIVIDE.thedivide.r_dividend[14] $abc$24881$new_n3782 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3784 r_op_Av[15] o_mem_data[15] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3785 i_mem_result[15] wr_index[0] wr_index[1] $abc$24881$new_n3784 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[15] alu_result[15] dbg_val[15] $abc$24881$new_n3785 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3790 r_op_Av[14] o_mem_data[14] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3791 i_mem_result[14] wr_index[0] wr_index[1] $abc$24881$new_n3790 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[14] alu_result[14] dbg_val[14] $abc$24881$new_n3791 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3793 DIVIDE.thedivide.r_dividend[13] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3681 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22600 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[13] DIVIDE.thedivide.r_dividend[12] $abc$24881$new_n3793 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3795 r_op_Av[13] o_mem_data[13] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3796 i_mem_result[13] wr_index[0] wr_index[1] $abc$24881$new_n3795 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[13] alu_result[13] dbg_val[13] $abc$24881$new_n3796 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3798 DIVIDE.thedivide.r_dividend[12] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3682 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22602 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[12] DIVIDE.thedivide.r_dividend[11] $abc$24881$new_n3798 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3800 r_op_Av[12] o_mem_data[12] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3801 i_mem_result[12] wr_index[0] wr_index[1] $abc$24881$new_n3800 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[12] alu_result[12] dbg_val[12] $abc$24881$new_n3801 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3803 DIVIDE.thedivide.r_dividend[11] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3683 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22604 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[11] DIVIDE.thedivide.r_dividend[10] $abc$24881$new_n3803 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3805 r_op_Av[11] o_mem_data[11] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3806 i_mem_result[11] wr_index[0] wr_index[1] $abc$24881$new_n3805 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[11] alu_result[11] dbg_val[11] $abc$24881$new_n3806 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3808 DIVIDE.thedivide.r_dividend[10] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3684 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22606 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10101 1 -11001 1 -11011 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[10] DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3808 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3810 r_op_Av[10] o_mem_data[10] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3811 i_mem_result[10] wr_index[0] wr_index[1] $abc$24881$new_n3810 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[10] alu_result[10] dbg_val[10] $abc$24881$new_n3811 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DIVIDE.thedivide.pre_sign $abc$24881$new_n3813 DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3685 $abc$24881$auto$rtlil.cc:2693:MuxGate$22608 -0000 1 -0001 1 -0010 1 -0011 1 -1010 1 -1011 1 -1100 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] o_mem_data[9] DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3813 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3815 r_op_Av[9] o_mem_data[9] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3816 i_mem_result[9] wr_index[0] wr_index[1] $abc$24881$new_n3815 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[9] alu_result[9] dbg_val[9] $abc$24881$new_n3816 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DIVIDE.thedivide.pre_sign $abc$24881$new_n3818 DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3686 $abc$24881$auto$rtlil.cc:2693:MuxGate$22610 -0000 1 -0001 1 -0010 1 -0011 1 -1010 1 -1011 1 -1100 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] o_mem_data[8] DIVIDE.thedivide.r_dividend[7] $abc$24881$new_n3818 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3820 r_op_Av[8] o_mem_data[8] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3821 i_mem_result[8] wr_index[0] wr_index[1] $abc$24881$new_n3820 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[8] alu_result[8] dbg_val[8] $abc$24881$new_n3821 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3825 r_op_Av[7] o_mem_data[7] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3826 i_mem_result[7] wr_index[0] wr_index[1] $abc$24881$new_n3825 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[7] alu_result[7] dbg_val[7] $abc$24881$new_n3826 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy $abc$24881$new_n3828 -00 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign $abc$24881$new_n3829 -10 1 -.names $abc$24881$new_n3704 $abc$24881$new_n3834 DIVIDE.thedivide.r_dividend[6] o_mem_data[6] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22614 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3832 r_op_Av[6] o_mem_data[6] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3833 i_mem_result[6] wr_index[0] wr_index[1] $abc$24881$new_n3832 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[6] alu_result[6] dbg_val[6] $abc$24881$new_n3833 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[6] $abc$24881$new_n3687 DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[5] $abc$24881$new_n3834 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3838 r_op_Av[5] o_mem_data[5] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3839 i_mem_result[5] wr_index[0] wr_index[1] $abc$24881$new_n3838 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[5] alu_result[5] dbg_val[5] $abc$24881$new_n3839 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3704 $abc$24881$new_n3845 DIVIDE.thedivide.r_dividend[4] o_mem_data[4] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22618 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3843 r_op_Av[4] o_mem_data[4] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3844 i_mem_result[4] wr_index[0] wr_index[1] $abc$24881$new_n3843 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[4] alu_result[4] dbg_val[4] $abc$24881$new_n3844 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[4] DIVIDE.thedivide.r_dividend[3] $abc$24881$new_n3688 DIVIDE.thedivide.r_busy $abc$24881$new_n3845 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3704 $abc$24881$new_n3850 DIVIDE.thedivide.r_dividend[3] o_mem_data[3] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22620 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3848 r_op_Av[3] o_mem_data[3] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3849 i_mem_result[3] wr_index[0] wr_index[1] $abc$24881$new_n3848 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[3] alu_result[3] dbg_val[3] $abc$24881$new_n3849 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[3] DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3689 DIVIDE.thedivide.r_busy $abc$24881$new_n3850 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3855 o_mem_data[2] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22622 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3692 $abc$24881$new_n3853 r_op_Av[2] o_mem_data[2] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3854 i_mem_result[2] wr_index[0] wr_index[1] $abc$24881$new_n3853 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[2] alu_result[2] dbg_val[2] $abc$24881$new_n3854 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[2] DIVIDE.thedivide.r_dividend[1] DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_busy $abc$24881$new_n3855 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3704 $abc$24881$new_n3857 DIVIDE.thedivide.r_dividend[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22624 -000 1 -001 1 -101 1 -111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[1] o_mem_data[1] $abc$24881$new_n3857 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -10000 1 -10001 1 -10100 1 -10101 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names r_op_Av[1] $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3859 o_mem_data[1] -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names wr_index[0] wr_index[1] $abc$24881$new_n3860 DIVIDE.thedivide.o_quotient[1] i_mem_result[1] $abc$24881$new_n3859 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names wr_index[1] alu_result[1] dbg_val[1] $abc$24881$new_n3860 -000 1 -010 1 -100 1 -101 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[0] o_mem_data[0] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$22626 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names r_op_Av[0] $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3863 o_mem_data[0] -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n3864 dbg_val[0] wr_index[1] wr_index[0] $abc$24881$new_n3863 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[0] i_mem_result[0] alu_result[0] $abc$24881$new_n3864 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3866 DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22630 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[60] DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n3870 $abc$24881$new_n3867 $abc$24881$new_n3866 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[31] DIVIDE.thedivide.r_dividend[62] $abc$24881$new_n3868 $abc$24881$new_n3867 -001 1 -100 1 -101 1 -111 1 -.names DIVIDE.thedivide.r_divisor[30] DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n3869 $abc$24881$new_n3868 -000 1 -100 1 -101 1 -110 1 -.names DIVIDE.thedivide.r_dividend[60] DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n3870 $abc$24881$new_n3869 -000 1 -100 1 -101 1 -110 1 -.names DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_divisor[28] DIVIDE.thedivide.r_dividend[58] DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3871 $abc$24881$new_n3870 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_divisor[26] DIVIDE.thedivide.r_dividend[56] DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3872 $abc$24881$new_n3871 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_dividend[54] DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3873 $abc$24881$new_n3872 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_dividend[52] DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3874 $abc$24881$new_n3873 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_dividend[50] DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3875 $abc$24881$new_n3874 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_dividend[48] DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3876 $abc$24881$new_n3875 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_divisor[16] DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3877 $abc$24881$new_n3876 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3878 $abc$24881$new_n3877 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[42] DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3879 $abc$24881$new_n3878 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_dividend[40] DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3880 $abc$24881$new_n3879 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_divisor[8] DIVIDE.thedivide.r_dividend[38] DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3881 $abc$24881$new_n3880 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_divisor[6] DIVIDE.thedivide.r_dividend[36] DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3882 $abc$24881$new_n3881 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_divisor[4] DIVIDE.thedivide.r_dividend[34] DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3883 $abc$24881$new_n3882 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3884 $abc$24881$new_n3883 -00001 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -10000 1 -10001 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3884 -10 1 -.names $abc$24881$new_n3886 DIVIDE.thedivide.r_dividend[60] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22634 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3887 $abc$24881$new_n3886 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[28] DIVIDE.thedivide.r_dividend[59] DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3871 $abc$24881$new_n3887 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3889 DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22638 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[58] DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n3871 $abc$24881$new_n3867 $abc$24881$new_n3889 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3891 DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22642 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3892 $abc$24881$new_n3891 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[26] DIVIDE.thedivide.r_dividend[57] DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3872 $abc$24881$new_n3892 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3894 DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22646 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[56] DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n3872 $abc$24881$new_n3867 $abc$24881$new_n3894 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3896 DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22650 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3897 $abc$24881$new_n3896 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_dividend[55] DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3873 $abc$24881$new_n3897 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3899 DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22654 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[54] DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n3873 $abc$24881$new_n3867 $abc$24881$new_n3899 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3901 DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22658 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3902 $abc$24881$new_n3901 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_dividend[53] DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3874 $abc$24881$new_n3902 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3904 DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22662 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[52] DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n3874 $abc$24881$new_n3867 $abc$24881$new_n3904 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3906 DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22666 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3907 $abc$24881$new_n3906 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_dividend[51] DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3875 $abc$24881$new_n3907 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3909 DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22670 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[50] DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n3875 $abc$24881$new_n3867 $abc$24881$new_n3909 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3911 DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22674 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3912 $abc$24881$new_n3911 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_dividend[49] DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3876 $abc$24881$new_n3912 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3914 DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22678 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[48] DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n3876 $abc$24881$new_n3867 $abc$24881$new_n3914 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3916 DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22682 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3917 $abc$24881$new_n3916 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[16] DIVIDE.thedivide.r_dividend[47] DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_dividend[46] $abc$24881$new_n3877 $abc$24881$new_n3917 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3919 DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22686 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n3877 $abc$24881$new_n3867 $abc$24881$new_n3919 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3921 DIVIDE.thedivide.r_dividend[46] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22690 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3922 $abc$24881$new_n3921 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_dividend[45] DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_dividend[44] $abc$24881$new_n3878 $abc$24881$new_n3922 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3924 DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22694 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n3878 $abc$24881$new_n3867 $abc$24881$new_n3924 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3926 DIVIDE.thedivide.r_dividend[44] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22698 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3927 $abc$24881$new_n3926 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[43] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n3879 $abc$24881$new_n3927 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3929 DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22702 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[42] DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n3879 $abc$24881$new_n3867 $abc$24881$new_n3929 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3931 DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22706 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3932 $abc$24881$new_n3931 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_dividend[41] DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3880 $abc$24881$new_n3932 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3934 DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22710 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[40] DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n3880 $abc$24881$new_n3867 $abc$24881$new_n3934 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3936 DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22714 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3937 $abc$24881$new_n3936 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[8] DIVIDE.thedivide.r_dividend[39] DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3881 $abc$24881$new_n3937 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3939 DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22718 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[38] DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n3881 $abc$24881$new_n3867 $abc$24881$new_n3939 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3941 DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22722 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3942 $abc$24881$new_n3941 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[6] DIVIDE.thedivide.r_dividend[37] DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3882 $abc$24881$new_n3942 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3944 DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22726 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[36] DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n3882 $abc$24881$new_n3867 $abc$24881$new_n3944 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3946 DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22730 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3947 $abc$24881$new_n3946 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[4] DIVIDE.thedivide.r_dividend[35] DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3883 $abc$24881$new_n3947 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3949 DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22734 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3950 $abc$24881$new_n3949 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3883 $abc$24881$new_n3950 -001 1 -010 1 -100 1 -111 1 -.names $abc$24881$new_n3952 DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22738 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3953 $abc$24881$new_n3952 -1001 1 -1011 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_dividend[33] DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_dividend[32] $abc$24881$new_n3884 $abc$24881$new_n3953 -00001 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01110 1 -10000 1 -10010 1 -10011 1 -10110 1 -11001 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n3955 DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22742 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n3884 $abc$24881$new_n3867 $abc$24881$new_n3955 -10010 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3963 GEN_ALU_PC.r_alu_pc[30] SET_USER_PC.r_upc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$22744 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3958 $abc$24881$new_n3701 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n3957 -1000 1 -.names $abc$24881$new_n3698 $abc$24881$new_n3697 $abc$24881$new_n3959 $abc$24881$new_n3958 -000 1 -.names i_mem_valid dbgv $abc$24881$new_n3700 $abc$24881$new_n3959 -000 1 -.names SET_GIE.r_gie $abc$24881$new_n3961 $abc$24881$new_n3960 -10 1 -.names mem_pc_valid o_i_count SET_ALU_ILLEGAL.r_alu_illegal $abc$24881$new_n3961 -000 1 -001 1 -011 1 -.names r_alu_pc_valid new_pc DIVIDE.thedivide.o_busy o_i_count -100 1 -.names wr_index[1] wr_index[0] alu_result[30] i_mem_result[30] dbg_val[30] $abc$24881$new_n3963 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3965 GEN_ALU_PC.r_alu_pc[29] SET_USER_PC.r_upc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$22746 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[29] i_mem_result[29] dbg_val[29] $abc$24881$new_n3965 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3967 GEN_ALU_PC.r_alu_pc[28] SET_USER_PC.r_upc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$22748 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[28] i_mem_result[28] dbg_val[28] $abc$24881$new_n3967 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3969 GEN_ALU_PC.r_alu_pc[27] SET_USER_PC.r_upc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$22750 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[27] i_mem_result[27] dbg_val[27] $abc$24881$new_n3969 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3971 GEN_ALU_PC.r_alu_pc[26] SET_USER_PC.r_upc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$22752 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[26] i_mem_result[26] dbg_val[26] $abc$24881$new_n3971 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3973 GEN_ALU_PC.r_alu_pc[25] SET_USER_PC.r_upc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$22754 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[25] i_mem_result[25] dbg_val[25] $abc$24881$new_n3973 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3975 GEN_ALU_PC.r_alu_pc[24] SET_USER_PC.r_upc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$22756 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[24] i_mem_result[24] dbg_val[24] $abc$24881$new_n3975 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3977 GEN_ALU_PC.r_alu_pc[23] SET_USER_PC.r_upc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$22758 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[23] i_mem_result[23] dbg_val[23] $abc$24881$new_n3977 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3979 GEN_ALU_PC.r_alu_pc[22] SET_USER_PC.r_upc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$22760 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[22] i_mem_result[22] dbg_val[22] $abc$24881$new_n3979 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3981 GEN_ALU_PC.r_alu_pc[21] SET_USER_PC.r_upc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$22762 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[21] i_mem_result[21] dbg_val[21] $abc$24881$new_n3981 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3983 GEN_ALU_PC.r_alu_pc[20] SET_USER_PC.r_upc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$22764 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[20] i_mem_result[20] dbg_val[20] $abc$24881$new_n3983 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3985 GEN_ALU_PC.r_alu_pc[19] SET_USER_PC.r_upc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$22766 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[19] i_mem_result[19] dbg_val[19] $abc$24881$new_n3985 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3987 GEN_ALU_PC.r_alu_pc[18] SET_USER_PC.r_upc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$22768 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[18] i_mem_result[18] dbg_val[18] $abc$24881$new_n3987 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3989 GEN_ALU_PC.r_alu_pc[17] SET_USER_PC.r_upc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$22770 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[17] i_mem_result[17] dbg_val[17] $abc$24881$new_n3989 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3991 GEN_ALU_PC.r_alu_pc[16] SET_USER_PC.r_upc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$22772 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[16] i_mem_result[16] dbg_val[16] $abc$24881$new_n3991 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3993 GEN_ALU_PC.r_alu_pc[15] SET_USER_PC.r_upc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$22774 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[15] i_mem_result[15] dbg_val[15] $abc$24881$new_n3993 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3995 GEN_ALU_PC.r_alu_pc[14] SET_USER_PC.r_upc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$22776 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[14] i_mem_result[14] dbg_val[14] $abc$24881$new_n3995 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3997 GEN_ALU_PC.r_alu_pc[13] SET_USER_PC.r_upc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22778 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[13] i_mem_result[13] dbg_val[13] $abc$24881$new_n3997 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3999 GEN_ALU_PC.r_alu_pc[12] SET_USER_PC.r_upc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$22780 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[12] i_mem_result[12] dbg_val[12] $abc$24881$new_n3999 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4001 GEN_ALU_PC.r_alu_pc[11] SET_USER_PC.r_upc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22782 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[11] i_mem_result[11] dbg_val[11] $abc$24881$new_n4001 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4003 GEN_ALU_PC.r_alu_pc[10] SET_USER_PC.r_upc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$22784 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[10] i_mem_result[10] dbg_val[10] $abc$24881$new_n4003 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4005 GEN_ALU_PC.r_alu_pc[9] SET_USER_PC.r_upc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$22786 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[9] i_mem_result[9] dbg_val[9] $abc$24881$new_n4005 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4007 GEN_ALU_PC.r_alu_pc[8] SET_USER_PC.r_upc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22788 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[8] i_mem_result[8] dbg_val[8] $abc$24881$new_n4007 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4009 GEN_ALU_PC.r_alu_pc[7] SET_USER_PC.r_upc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22790 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[7] i_mem_result[7] dbg_val[7] $abc$24881$new_n4009 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4011 GEN_ALU_PC.r_alu_pc[6] SET_USER_PC.r_upc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22792 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[6] i_mem_result[6] dbg_val[6] $abc$24881$new_n4011 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4013 GEN_ALU_PC.r_alu_pc[5] SET_USER_PC.r_upc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22794 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[5] i_mem_result[5] dbg_val[5] $abc$24881$new_n4013 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4015 GEN_ALU_PC.r_alu_pc[4] SET_USER_PC.r_upc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22796 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[4] i_mem_result[4] dbg_val[4] $abc$24881$new_n4015 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4017 GEN_ALU_PC.r_alu_pc[3] SET_USER_PC.r_upc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22798 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[3] i_mem_result[3] dbg_val[3] $abc$24881$new_n4017 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4019 GEN_ALU_PC.r_alu_pc[2] SET_USER_PC.r_upc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22800 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] alu_result[2] i_mem_result[2] dbg_val[2] $abc$24881$new_n4019 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4123 $abc$24881$new_n4021 $abc$24881$new_n4122 $abc$24881$new_n3963 $abc$24881$auto$rtlil.cc:2693:MuxGate$22802 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4022 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4106 $abc$24881$new_n4121 $abc$24881$new_n4021 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4023 $abc$24881$new_n4087 SET_USER_PC.r_upc[30] $abc$24881$new_n4022 -0001 1 -0010 1 -0011 1 -.names $abc$24881$new_n4024 pf_pc[30] pf_pc[28] pf_pc[29] $abc$24881$new_n4090 $abc$24881$new_n4023 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11111 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4024 -10 1 -.names $abc$24881$new_n4026 $abc$24881$new_n4086 i_reset $abc$24881$new_n4025 -000 1 -001 1 -011 1 -.names $abc$24881$new_n4075 $abc$24881$new_n4081 new_pc $abc$24881$new_n4085 o_pf_ready $abc$24881$new_n4026 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4028 o_pf_ready -00 1 -.names instruction_decoder.r_valid $abc$24881$new_n4029 $abc$24881$new_n4028 -10 1 -.names instruction_decoder.r_valid op_valid $abc$24881$new_n4030 $abc$24881$new_n4051 $abc$24881$new_n4073 $abc$24881$new_n4029 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10110 1 -11010 1 -.names mem_ce $abc$24881$new_n4031 $abc$24881$new_n4030 -00 1 -.names $abc$24881$new_n4032 i_mem_rdbusy op_valid_mem $abc$24881$new_n4047 $abc$24881$new_n4031 -1000 1 -.names $abc$24881$new_n4033 $abc$24881$new_n4040 r_op_break BUSLOCK.r_prelock_stall DIVERR.r_idiv_err_flag $abc$24881$new_n4032 -11000 1 -.names $abc$24881$new_n4037 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n4033 -10 1 -.names $abc$24881$new_n3697 $abc$24881$new_n4035 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y -11 1 -.names $abc$24881$new_n4036 $abc$24881$new_n3959 $abc$24881$new_n4035 -10 1 -.names $abc$24881$new_n3701 $abc$24881$new_n3698 $abc$24881$new_n3695 $abc$24881$new_n4036 -000 1 -.names last_write_to_cc o_break sleep GEN_ALU_PHASE.r_alu_phase i_halt $abc$24881$new_n4037 -00000 1 -00010 1 -00011 1 -.names $abc$24881$new_n4039 ill_err_i SET_GIE.r_gie i_bus_err DIVIDE.thedivide.o_err o_break -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names new_pc GEN_PENDING_BREAK.r_break_pending SET_GIE.r_gie SET_ALU_ILLEGAL.r_alu_illegal break_en $abc$24881$new_n4039 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4044 $abc$24881$new_n4046 $abc$24881$new_n4041 $abc$24881$new_n4040 -100 1 -.names $abc$24881$new_n4042 GEN_PENDING_INTERRUPT.r_pending_interrupt i_halt $abc$24881$new_n4041 -110 1 -.names GEN_ALU_PHASE.r_alu_phase o_bus_lock $abc$24881$new_n4042 -00 1 -.names BUSLOCK.r_bus_lock[1] BUSLOCK.r_bus_lock[0] o_bus_lock -01 1 -10 1 -11 1 -.names $abc$24881$new_n4045 i_mem_busy op_valid_div op_illegal $abc$24881$new_n4044 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names op_valid SET_ALU_ILLEGAL.r_alu_illegal ibus_err_flag DIVIDE.thedivide.o_busy $abc$24881$new_n4045 -1000 1 -.names user_step GEN_PENDING_INTERRUPT.r_user_stepped SET_GIE.r_gie $abc$24881$new_n4046 -111 1 -.names i_mem_busy $abc$24881$new_n4048 SET_GIE.r_gie o_mem_reg[4] o_mem_reg[0] $abc$24881$new_n4047 -11000 1 -11110 1 -.names GEN_OP_WR.r_op_wR o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] $abc$24881$new_n4048 -1111 1 -.names $abc$24881$new_n4050 $abc$24881$new_n4032 i_bus_err DIVIDE.thedivide.o_err $abc$24881$new_n4035 mem_ce -11000 1 -.names op_valid_mem i_mem_pipe_stalled new_pc GEN_OP_PIPE.r_op_pipe i_mem_busy $abc$24881$new_n4050 -10000 1 -10010 1 -10011 1 -.names i_halt $abc$24881$new_n4064 $abc$24881$new_n9842 $abc$24881$new_n4072 dcd_rB $abc$24881$new_n4051 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -.names instruction_decoder.o_dcdB[3] alu_reg[3] alu_reg[4] instruction_decoder.o_dcdB[4] $abc$24881$new_n4062 -0000 1 -0011 1 -1100 1 -1111 1 -.names $abc$24881$new_n4065 $abc$24881$new_n4067 dcd_F[3] instruction_decoder.o_dcdA[2] $abc$24881$new_n4070 $abc$24881$new_n4064 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names GEN_OP_STALL.r_pending_sreg_write op_valid $abc$24881$new_n4048 $abc$24881$new_n4066 $abc$24881$new_n4065 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -.names o_mem_reg[0] SET_GIE.r_gie o_mem_reg[4] $abc$24881$new_n4066 -100 1 -111 1 -.names dcd_rB $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] $abc$24881$new_n4068 instruction_decoder.o_dcdB[0] $abc$24881$new_n4067 -11100 1 -11101 1 -11110 1 -.names SET_GIE.r_gie instruction_decoder.o_dcdB[4] $abc$24881$new_n4068 -00 1 -11 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4069 -11 1 -.names dcd_rA instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n4071 instruction_decoder.o_dcdA[0] $abc$24881$new_n4070 -11100 1 -11101 1 -11110 1 -.names SET_GIE.r_gie instruction_decoder.o_dcdA[4] $abc$24881$new_n4071 -00 1 -11 1 -.names i_mem_rdbusy op_valid DIVIDE.thedivide.o_busy $abc$24881$new_n4072 -000 1 -.names GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n4074 $abc$24881$new_n4072 dcd_Bcc dcd_rB $abc$24881$new_n4073 -01000 1 -01001 1 -01010 1 -01011 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dcd_rA dcd_Acc op_wF GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n4074 -1101 1 -1110 1 -1111 1 -.names $abc$24881$auto$opt_dff.cc:253:combine_resets$3432 SET_GIE.r_gie dbg_clear_pipe o_clear_icache $abc$24881$new_n4075 -0000 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names i_reset $abc$24881$new_n4077 $abc$24881$auto$opt_dff.cc:253:combine_resets$3432 -01 1 -10 1 -11 1 -.names SET_GIE.r_gie $abc$24881$new_n4078 $abc$24881$new_n4077 -10 1 -.names $abc$24881$new_n4080 $abc$24881$new_n4079 $abc$24881$new_n4013 $abc$24881$new_n4078 -100 1 -101 1 -110 1 -.names $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n3694 $abc$24881$new_n4079 -10 1 -.names i_bus_err DIVIDE.thedivide.o_err $abc$24881$new_n4041 i_mem_busy $abc$24881$new_n4080 -0000 1 -0001 1 -0011 1 -.names $abc$24881$new_n4082 $abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y SET_GIE.r_gie dbg_clear_pipe o_clear_icache $abc$24881$new_n4081 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -.names $abc$24881$new_n4083 i_interrupt SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n4082 -1000 1 -.names $abc$24881$new_n3694 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n4083 -11 1 -.names $abc$24881$new_n4035 SET_GIE.r_gie $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y -1010 1 -1100 1 -.names i_pf_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb $abc$24881$new_n4085 -10 1 -.names dbgv $abc$24881$new_n4036 SET_GIE.r_gie $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$new_n4086 -11010 1 -11100 1 -.names $abc$24881$new_n4088 o_pf_new_pc o_pf_ready $abc$24881$new_n4085 $abc$24881$new_n4087 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4081 $abc$24881$new_n4075 $abc$24881$new_n4088 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc o_pf_new_pc -01 1 -10 1 -11 1 -.names pf_pc[27] $abc$24881$new_n4091 $abc$24881$new_n4090 -11 1 -.names pf_pc[26] $abc$24881$new_n4092 $abc$24881$new_n4091 -11 1 -.names pf_pc[25] $abc$24881$new_n4093 $abc$24881$new_n4092 -11 1 -.names pf_pc[22] pf_pc[23] pf_pc[24] $abc$24881$new_n4094 $abc$24881$new_n4093 -1111 1 -.names pf_pc[19] pf_pc[20] pf_pc[21] $abc$24881$new_n4095 $abc$24881$new_n4094 -1111 1 -.names pf_pc[18] $abc$24881$new_n4096 $abc$24881$new_n4095 -11 1 -.names pf_pc[17] $abc$24881$new_n4097 $abc$24881$new_n4096 -11 1 -.names pf_pc[16] $abc$24881$new_n4098 $abc$24881$new_n4097 -11 1 -.names pf_pc[13] pf_pc[14] pf_pc[15] $abc$24881$new_n4099 $abc$24881$new_n4098 -1111 1 -.names pf_pc[11] pf_pc[12] $abc$24881$new_n4100 $abc$24881$new_n4099 -111 1 -.names pf_pc[7] pf_pc[8] pf_pc[9] pf_pc[10] $abc$24881$new_n4101 $abc$24881$new_n4100 -11111 1 -.names pf_pc[6] $abc$24881$new_n4102 $abc$24881$new_n4101 -11 1 -.names pf_pc[2] pf_pc[3] pf_pc[4] pf_pc[5] $abc$24881$new_n4102 -1111 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4026 $abc$24881$new_n4104 $abc$24881$new_n4103 -000 1 -001 1 -010 1 -.names i_reset $abc$24881$new_n4086 $abc$24881$new_n4105 $abc$24881$new_n4104 -000 1 -.names dbg_clear_pipe o_clear_icache $abc$24881$new_n4082 $abc$24881$new_n4077 $abc$24881$new_n4105 -0000 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n4107 $abc$24881$new_n4106 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n4108 $abc$24881$new_n4107 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$new_n4109 $abc$24881$new_n4108 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n4110 $abc$24881$new_n4109 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n4111 $abc$24881$new_n4110 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$new_n4112 $abc$24881$new_n4111 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$new_n4113 $abc$24881$new_n4112 -111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] $abc$24881$new_n4114 $abc$24881$new_n4113 -11111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n4115 $abc$24881$new_n4114 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] $abc$24881$new_n4116 $abc$24881$new_n4115 -111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n4117 $abc$24881$new_n4116 -111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] $abc$24881$new_n4118 $abc$24881$new_n4117 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] $abc$24881$new_n4119 $abc$24881$new_n4118 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$new_n4120 $abc$24881$new_n4119 -11 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] $abc$24881$new_n4120 -111 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4121 -11 1 -.names $abc$24881$new_n4104 $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4122 -000 1 -.names ipc[30] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[30] $abc$24881$new_n4123 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4104 $abc$24881$new_n4026 $abc$24881$new_n4124 -10 1 -.names $abc$24881$new_n4088 o_pf_new_pc o_pf_ready $abc$24881$new_n4085 $abc$24881$new_n4125 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4129 $abc$24881$new_n4127 $abc$24881$new_n4128 $abc$24881$new_n4103 $abc$24881$auto$rtlil.cc:2693:MuxGate$22804 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names $abc$24881$new_n4121 $abc$24881$new_n4024 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4106 SET_USER_PC.r_upc[29] $abc$24881$new_n4127 -00000 1 -00010 1 -00100 1 -00110 1 -10000 1 -10001 1 -10110 1 -10111 1 -.names $abc$24881$new_n4024 pf_pc[29] pf_pc[28] $abc$24881$new_n4090 $abc$24881$new_n4128 -1000 1 -1001 1 -1010 1 -1111 1 -.names $abc$24881$new_n4130 $abc$24881$new_n4122 $abc$24881$new_n3965 $abc$24881$new_n4129 -100 1 -101 1 -111 1 -.names ipc[29] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[29] $abc$24881$new_n4130 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4132 pf_pc[28] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22806 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4133 $abc$24881$new_n3967 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[28] $abc$24881$new_n4132 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n4107 $abc$24881$new_n4134 $abc$24881$new_n4133 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4087 pf_pc[28] $abc$24881$new_n4090 $abc$24881$new_n4025 SET_USER_PC.r_upc[28] $abc$24881$new_n4134 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4136 pf_pc[27] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22808 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4137 $abc$24881$new_n3969 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[27] $abc$24881$new_n4136 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[27] $abc$24881$new_n4091 $abc$24881$new_n4138 $abc$24881$new_n4137 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n4108 SET_USER_PC.r_upc[27] $abc$24881$new_n4138 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4140 pf_pc[26] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22810 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4141 $abc$24881$new_n3971 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[26] $abc$24881$new_n4140 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$new_n4109 $abc$24881$new_n4142 $abc$24881$new_n4141 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4087 pf_pc[26] $abc$24881$new_n4092 $abc$24881$new_n4025 SET_USER_PC.r_upc[26] $abc$24881$new_n4142 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4144 ipc[25] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22812 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4145 $abc$24881$new_n3973 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[25] $abc$24881$new_n4144 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[25] $abc$24881$new_n4093 $abc$24881$new_n4146 $abc$24881$new_n4145 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n4110 SET_USER_PC.r_upc[25] $abc$24881$new_n4146 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n4148 $abc$24881$new_n4122 $abc$24881$new_n3975 $abc$24881$auto$rtlil.cc:2693:MuxGate$22814 -000 1 -001 1 -010 1 -011 1 -110 1 -.names $abc$24881$new_n4151 $abc$24881$new_n4103 $abc$24881$new_n4150 $abc$24881$new_n4149 $abc$24881$new_n4148 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4024 pf_pc[24] pf_pc[22] pf_pc[23] $abc$24881$new_n4094 $abc$24881$new_n4149 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n4111 SET_USER_PC.r_upc[24] $abc$24881$new_n4150 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names ipc[24] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[24] $abc$24881$new_n4151 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4153 pf_pc[23] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22816 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4155 $abc$24881$new_n4103 $abc$24881$new_n4156 $abc$24881$new_n4154 $abc$24881$new_n4153 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4024 pf_pc[23] pf_pc[22] $abc$24881$new_n4094 $abc$24881$new_n4154 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4122 $abc$24881$new_n3977 ipc[23] $abc$24881$new_n4124 $abc$24881$new_n4155 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$new_n4112 SET_USER_PC.r_upc[23] $abc$24881$new_n4156 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n4122 $abc$24881$new_n3979 pf_pc[22] $abc$24881$new_n4125 $abc$24881$new_n4160 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4163 ipc[21] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22820 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4165 $abc$24881$new_n4103 $abc$24881$new_n4166 $abc$24881$new_n4164 $abc$24881$new_n4163 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4024 pf_pc[21] pf_pc[19] pf_pc[20] $abc$24881$new_n4095 $abc$24881$new_n4164 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4122 $abc$24881$new_n3981 pf_pc[21] $abc$24881$new_n4125 $abc$24881$new_n4165 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] $abc$24881$new_n4113 SET_USER_PC.r_upc[21] $abc$24881$new_n4166 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n4125 $abc$24881$new_n4168 pf_pc[20] $abc$24881$new_n4169 $abc$24881$new_n4103 $abc$24881$auto$rtlil.cc:2693:MuxGate$22822 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4124 ipc[20] $abc$24881$new_n4122 $abc$24881$new_n3983 $abc$24881$new_n4168 -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[20] $abc$24881$new_n4171 $abc$24881$new_n4170 $abc$24881$new_n4169 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names pf_pc[20] pf_pc[19] $abc$24881$new_n4095 $abc$24881$new_n4170 -011 1 -100 1 -101 1 -110 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] $abc$24881$new_n4114 $abc$24881$new_n4171 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4173 ipc[19] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22824 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4175 $abc$24881$new_n4103 $abc$24881$new_n4176 $abc$24881$new_n4174 $abc$24881$new_n4173 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] $abc$24881$new_n4114 $abc$24881$new_n4174 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4122 $abc$24881$new_n3985 pf_pc[19] $abc$24881$new_n4125 $abc$24881$new_n4175 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4087 pf_pc[19] $abc$24881$new_n4095 $abc$24881$new_n4025 SET_USER_PC.r_upc[19] $abc$24881$new_n4176 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4178 ipc[18] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22826 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4179 $abc$24881$new_n3987 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[18] $abc$24881$new_n4178 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4180 $abc$24881$new_n4181 SET_USER_PC.r_upc[18] $abc$24881$new_n4087 $abc$24881$new_n4179 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4024 pf_pc[18] $abc$24881$new_n4096 $abc$24881$new_n4180 -101 1 -110 1 -.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n4114 $abc$24881$new_n4181 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4183 ipc[17] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22828 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4184 $abc$24881$new_n3989 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[17] $abc$24881$new_n4183 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[17] $abc$24881$new_n4097 $abc$24881$new_n4185 $abc$24881$new_n4184 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n4114 SET_USER_PC.r_upc[17] $abc$24881$new_n4185 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n4187 ipc[16] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22830 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4188 $abc$24881$new_n3991 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[16] $abc$24881$new_n4187 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[16] $abc$24881$new_n4098 $abc$24881$new_n4189 $abc$24881$new_n4188 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n4115 SET_USER_PC.r_upc[16] $abc$24881$new_n4189 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n4194 $abc$24881$new_n3993 $abc$24881$new_n4122 $abc$24881$new_n4103 $abc$24881$new_n4191 $abc$24881$auto$rtlil.cc:2693:MuxGate$22832 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11100 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[15] $abc$24881$new_n4192 $abc$24881$new_n4193 $abc$24881$new_n4191 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n4116 $abc$24881$new_n4192 -011 1 -100 1 -101 1 -110 1 -.names pf_pc[15] pf_pc[13] pf_pc[14] $abc$24881$new_n4099 $abc$24881$new_n4193 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names ipc[15] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[15] $abc$24881$new_n4194 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4122 $abc$24881$new_n3995 pf_pc[14] $abc$24881$new_n4125 $abc$24881$new_n4198 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4122 $abc$24881$new_n3997 pf_pc[13] $abc$24881$new_n4125 $abc$24881$new_n4203 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4208 $abc$24881$new_n4103 $abc$24881$new_n4206 $abc$24881$new_n4122 $abc$24881$new_n3999 $abc$24881$auto$rtlil.cc:2693:MuxGate$22838 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11010 1 -11110 1 -.names $abc$24881$new_n4207 pf_pc[12] pf_pc[11] $abc$24881$new_n4100 $abc$24881$new_n4024 $abc$24881$new_n4206 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -01111 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n4117 SET_USER_PC.r_upc[12] $abc$24881$new_n4207 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names ipc[12] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[12] $abc$24881$new_n4208 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4210 ipc[11] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22840 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4212 $abc$24881$new_n4103 $abc$24881$new_n4213 $abc$24881$new_n4211 $abc$24881$new_n4210 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] $abc$24881$new_n4118 $abc$24881$new_n4211 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4122 $abc$24881$new_n4001 pf_pc[11] $abc$24881$new_n4125 $abc$24881$new_n4212 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4087 pf_pc[11] $abc$24881$new_n4100 $abc$24881$new_n4025 SET_USER_PC.r_upc[11] $abc$24881$new_n4213 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4218 $abc$24881$new_n4103 $abc$24881$new_n4215 $abc$24881$new_n4122 $abc$24881$new_n4003 $abc$24881$auto$rtlil.cc:2693:MuxGate$22842 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -11010 1 -11110 1 -.names $abc$24881$new_n4024 $abc$24881$new_n4216 $abc$24881$new_n4217 SET_USER_PC.r_upc[10] $abc$24881$new_n4087 $abc$24881$new_n4215 -00000 1 -00100 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n4118 $abc$24881$new_n4216 -1000 1 -1001 1 -1010 1 -1111 1 -.names pf_pc[10] pf_pc[7] pf_pc[8] pf_pc[9] $abc$24881$new_n4101 $abc$24881$new_n4217 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names ipc[10] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[10] $abc$24881$new_n4218 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4220 pf_pc[9] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22844 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4222 $abc$24881$new_n4103 $abc$24881$new_n4221 $abc$24881$new_n4223 $abc$24881$new_n4220 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4024 pf_pc[9] pf_pc[7] pf_pc[8] $abc$24881$new_n4101 $abc$24881$new_n4221 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4122 $abc$24881$new_n4005 ipc[9] $abc$24881$new_n4124 $abc$24881$new_n4222 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n4118 SET_USER_PC.r_upc[9] $abc$24881$new_n4223 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4228 $abc$24881$new_n4007 $abc$24881$new_n4122 $abc$24881$new_n4103 $abc$24881$new_n4225 $abc$24881$auto$rtlil.cc:2693:MuxGate$22846 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11100 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[8] $abc$24881$new_n4227 $abc$24881$new_n4226 $abc$24881$new_n4225 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names pf_pc[8] pf_pc[7] $abc$24881$new_n4101 $abc$24881$new_n4226 -011 1 -100 1 -101 1 -110 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$new_n4119 $abc$24881$new_n4227 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names ipc[8] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[8] $abc$24881$new_n4228 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4122 $abc$24881$new_n4009 pf_pc[7] $abc$24881$new_n4125 $abc$24881$new_n4232 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4235 ipc[6] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22850 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4236 $abc$24881$new_n4011 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[6] $abc$24881$new_n4235 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[6] $abc$24881$new_n4102 $abc$24881$new_n4237 $abc$24881$new_n4236 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n4119 SET_USER_PC.r_upc[6] $abc$24881$new_n4237 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4239 pf_pc[5] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22852 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4241 $abc$24881$new_n4103 $abc$24881$new_n4240 $abc$24881$new_n4242 $abc$24881$new_n4239 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4024 pf_pc[5] pf_pc[2] pf_pc[3] pf_pc[4] $abc$24881$new_n4240 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4122 $abc$24881$new_n4013 ipc[5] $abc$24881$new_n4124 $abc$24881$new_n4241 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$new_n4120 SET_USER_PC.r_upc[5] $abc$24881$new_n4242 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4244 pf_pc[4] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22854 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4245 $abc$24881$new_n4015 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[4] $abc$24881$new_n4244 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4246 $abc$24881$new_n4247 SET_USER_PC.r_upc[4] $abc$24881$new_n4087 $abc$24881$new_n4245 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4024 pf_pc[4] pf_pc[2] pf_pc[3] $abc$24881$new_n4246 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] $abc$24881$new_n4247 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n4249 pf_pc[3] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22856 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4250 $abc$24881$new_n4017 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[3] $abc$24881$new_n4249 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[2] pf_pc[3] $abc$24881$new_n4251 $abc$24881$new_n4250 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] SET_USER_PC.r_upc[3] $abc$24881$new_n4251 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n4087 SET_USER_PC.r_upc[2] $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] $abc$24881$new_n4255 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n4028 dcd_Bpc $abc$24881$new_n4257 $abc$24881$new_n4292 $abc$24881$auto$rtlil.cc:2693:MuxGate$22860 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4284 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n4258 $abc$24881$new_n4257 -1100 1 -.names $abc$24881$new_n4281 $abc$24881$new_n4266 $abc$24881$new_n4259 $abc$24881$new_n4274 $abc$24881$new_n4283 $abc$24881$new_n4258 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -.names $abc$24881$new_n4260 $abc$24881$new_n4271 $abc$24881$new_n4273 $abc$24881$new_n4259 -001 1 -010 1 -011 1 -.names $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4261 $abc$24881$new_n4260 -110 1 -.names $abc$24881$new_n4268 $abc$24881$new_n4262 $abc$24881$new_n4261 -10 1 -.names $abc$24881$new_n4267 $abc$24881$new_n4263 $abc$24881$new_n4266 $abc$24881$new_n4262 -001 1 -010 1 -011 1 -.names $abc$24881$new_n4265 $abc$24881$new_n4264 $abc$24881$new_n4263 -00 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[9] i_pf_instruction[25] $abc$24881$new_n4264 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[10] i_pf_instruction[26] $abc$24881$new_n4265 -000 1 -010 1 -100 1 -101 1 -.names i_pf_instruction[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4266 -00 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[8] i_pf_instruction[24] $abc$24881$new_n4267 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4266 $abc$24881$new_n4265 $abc$24881$new_n4264 i_pf_instruction[23] $abc$24881$new_n4267 $abc$24881$new_n4268 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$24881$new_n4263 $abc$24881$new_n4266 i_pf_instruction[25] $abc$24881$new_n4269 -000 1 -001 1 -010 1 -.names $abc$24881$new_n4265 $abc$24881$new_n4267 $abc$24881$new_n4264 $abc$24881$new_n4266 $abc$24881$new_n4270 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -.names $abc$24881$new_n4268 $abc$24881$new_n4272 $abc$24881$new_n4271 -11 1 -.names $abc$24881$new_n4267 $abc$24881$new_n4263 $abc$24881$new_n4272 -11 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[7] i_pf_instruction[23] $abc$24881$new_n4273 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4266 $abc$24881$new_n4275 $abc$24881$new_n4271 $abc$24881$new_n4274 -100 1 -.names $abc$24881$new_n4276 $abc$24881$new_n4277 $abc$24881$new_n4267 $abc$24881$new_n4275 -110 1 -.names i_pf_instruction[25] $abc$24881$new_n4266 $abc$24881$new_n4265 $abc$24881$new_n4276 -110 1 -.names $abc$24881$new_n4280 $abc$24881$new_n4279 $abc$24881$new_n4278 $abc$24881$new_n4277 -000 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[13] i_pf_instruction[29] $abc$24881$new_n4278 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[12] i_pf_instruction[28] $abc$24881$new_n4279 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[14] i_pf_instruction[30] $abc$24881$new_n4280 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4268 $abc$24881$new_n4267 $abc$24881$new_n4282 $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4281 -10000 1 -.names $abc$24881$new_n4266 i_pf_instruction[22] $abc$24881$new_n4267 $abc$24881$new_n4265 $abc$24881$new_n4264 $abc$24881$new_n4282 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[2] i_pf_instruction[18] $abc$24881$new_n4283 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4266 i_pf_instruction[17] $abc$24881$new_n4287 $abc$24881$new_n4285 $abc$24881$new_n4284 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4273 $abc$24881$new_n4286 $abc$24881$new_n4285 -11 1 -.names $abc$24881$new_n4264 $abc$24881$new_n4265 $abc$24881$new_n4286 -10 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[6] i_pf_instruction[22] $abc$24881$new_n4287 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4266 i_pf_instruction[16] $abc$24881$new_n4289 $abc$24881$new_n4285 $abc$24881$new_n4288 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[5] i_pf_instruction[21] $abc$24881$new_n4289 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4266 i_pf_instruction[15] $abc$24881$new_n4291 $abc$24881$new_n4285 $abc$24881$new_n4290 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[4] i_pf_instruction[20] $abc$24881$new_n4291 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4293 i_pf_instruction[31] $abc$24881$new_n4285 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction[14] $abc$24881$new_n4292 -00000 1 -00100 1 -10000 1 -10010 1 -10011 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[3] i_pf_instruction[19] $abc$24881$new_n4293 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[4] SET_GIE.r_gie $abc$24881$new_n4295 i_pf_instruction[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22862 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n4281 $abc$24881$new_n4295 -11 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[3] $abc$24881$new_n4284 $abc$24881$auto$rtlil.cc:2693:MuxGate$22864 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[2] $abc$24881$new_n4288 $abc$24881$auto$rtlil.cc:2693:MuxGate$22866 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[1] $abc$24881$new_n4290 $abc$24881$auto$rtlil.cc:2693:MuxGate$22868 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[0] $abc$24881$new_n4292 $abc$24881$auto$rtlil.cc:2693:MuxGate$22870 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4028 dcd_Apc $abc$24881$new_n4301 $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$22872 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4277 $abc$24881$new_n4295 SET_GIE.r_gie $abc$24881$new_n4283 $abc$24881$new_n4301 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[11] i_pf_instruction[27] $abc$24881$new_n4302 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[4] SET_GIE.r_gie $abc$24881$new_n4295 $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$22874 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[3] $abc$24881$new_n4280 $abc$24881$auto$rtlil.cc:2693:MuxGate$22876 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[2] $abc$24881$new_n4278 $abc$24881$auto$rtlil.cc:2693:MuxGate$22878 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[1] $abc$24881$new_n4279 $abc$24881$auto$rtlil.cc:2693:MuxGate$22880 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[0] $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$22882 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[13] i_pf_instruction[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22884 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[12] i_pf_instruction[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$22886 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[11] i_pf_instruction[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22888 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[10] i_pf_instruction[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$22890 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[9] i_pf_instruction[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$22892 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[8] i_pf_instruction[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22894 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[7] i_pf_instruction[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22896 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[6] i_pf_instruction[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22898 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[5] i_pf_instruction[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22900 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[4] i_pf_instruction[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22902 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[3] i_pf_instruction[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22904 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[2] i_pf_instruction[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22906 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[1] i_pf_instruction[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22908 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[0] i_pf_instruction[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22910 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 dcd_opn[2] $abc$24881$new_n4323 $abc$24881$new_n4262 $abc$24881$auto$rtlil.cc:2693:MuxGate$22914 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4271 $abc$24881$new_n4275 $abc$24881$new_n4287 $abc$24881$new_n4273 $abc$24881$new_n4323 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$24881$new_n4028 dcd_opn[1] $abc$24881$new_n4323 $abc$24881$new_n4268 $abc$24881$auto$rtlil.cc:2693:MuxGate$22918 -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4028 dcd_opn[0] $abc$24881$new_n4282 $abc$24881$new_n4323 $abc$24881$auto$rtlil.cc:2693:MuxGate$22922 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5065 $abc$24881$new_n5090 dcd_I[31] $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n4327 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -11111 1 -.names $abc$24881$new_n4995 dcd_I[31] $abc$24881$new_n9877 $abc$24881$new_n5041 $abc$24881$new_n4329 $abc$24881$new_n4328 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4972 $abc$24881$new_n4925 $abc$24881$new_n4948 $abc$24881$new_n9843 $abc$24881$new_n4971 $abc$24881$new_n4329 -11000 1 -11001 1 -11011 1 -.names $abc$24881$new_n9502 dcd_I[13] dcd_I[14] $abc$24881$new_n9505 $abc$24881$new_n9847 $abc$24881$new_n4334 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n4635 dcd_I[10] $abc$24881$new_n9496 $abc$24881$new_n4658 $abc$24881$new_n4337 $abc$24881$new_n4336 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n4566 dcd_I[8] $abc$24881$new_n4591 $abc$24881$new_n4590 $abc$24881$new_n4338 $abc$24881$new_n4337 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n9489 dcd_I[5] dcd_I[6] $abc$24881$new_n9873 $abc$24881$new_n4339 $abc$24881$new_n4338 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n4406 dcd_I[4] dcd_I[3] $abc$24881$new_n9436 $abc$24881$new_n9858 $abc$24881$new_n4339 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4345 regset[29][4] regset[25][4] $abc$24881$new_n4344 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][4] regset[24][4] $abc$24881$new_n4345 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4348 regset[21][4] regset[17][4] $abc$24881$new_n4347 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[20][4] regset[16][4] $abc$24881$new_n4348 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4349 -00 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4352 regset[31][4] regset[27][4] $abc$24881$new_n4351 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][4] regset[26][4] $abc$24881$new_n4352 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4355 regset[23][4] regset[19][4] $abc$24881$new_n4354 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[22][4] regset[18][4] $abc$24881$new_n4355 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4356 -10 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4359 $abc$24881$new_n4361 $abc$24881$new_n4363 $abc$24881$new_n4358 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4360 regset[5][4] regset[1][4] $abc$24881$new_n4359 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[4][4] regset[0][4] $abc$24881$new_n4360 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4362 regset[7][4] regset[3][4] $abc$24881$new_n4361 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[6][4] regset[2][4] $abc$24881$new_n4362 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4364 regset[15][4] regset[11][4] $abc$24881$new_n4363 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][4] regset[10][4] $abc$24881$new_n4364 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4366 regset[13][4] regset[9][4] $abc$24881$new_n4365 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][4] regset[8][4] $abc$24881$new_n4366 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4368 $abc$24881$new_n3843 $abc$24881$new_n4367 -10 1 -.names dcd_rB $abc$24881$new_n4371 $abc$24881$new_n4369 $abc$24881$new_n3959 $abc$24881$new_n4368 -1110 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] $abc$24881$new_n3701 $abc$24881$new_n3698 $abc$24881$new_n4370 $abc$24881$new_n4369 -00110 1 -01010 1 -10100 1 -11000 1 -.names instruction_decoder.o_dcdB[0] i_mem_valid alu_reg[0] i_mem_wreg[0] $abc$24881$new_n4370 -1000 1 -1001 1 -1100 1 -1110 1 -.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n4372 $abc$24881$new_n4371 -00110 1 -01010 1 -10100 1 -11000 1 -.names i_mem_valid instruction_decoder.o_dcdB[0] alu_reg[0] i_mem_wreg[0] $abc$24881$new_n4372 -0010 1 -0011 1 -1001 1 -1011 1 -.names dcd_rB $abc$24881$new_n4369 $abc$24881$new_n4371 $abc$24881$new_n3959 $abc$24881$new_n4373 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][3] regset[18][3] $abc$24881$new_n4381 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][3] regset[19][3] $abc$24881$new_n4382 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4384 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][3] regset[16][3] $abc$24881$new_n4383 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][3] regset[17][3] $abc$24881$new_n4384 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4386 regset[31][3] regset[27][3] $abc$24881$new_n4385 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][3] regset[26][3] $abc$24881$new_n4386 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4389 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][3] regset[3][3] $abc$24881$new_n4388 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][3] regset[2][3] $abc$24881$new_n4389 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4391 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][3] regset[0][3] $abc$24881$new_n4390 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][3] regset[1][3] $abc$24881$new_n4391 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4394 regset[15][3] regset[11][3] $abc$24881$new_n4393 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][3] regset[10][3] $abc$24881$new_n4394 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4396 $abc$24881$new_n4395 -100 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4397 regset[13][3] regset[9][3] $abc$24881$new_n4396 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][3] regset[8][3] $abc$24881$new_n4397 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n4398 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4400 $abc$24881$new_n4403 flags[3] $abc$24881$new_n4399 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4402 $abc$24881$new_n4401 $abc$24881$new_n4400 -11 1 -.names alu_wF doalu.o_valid DIVIDE.thedivide.o_valid DIVIDE.thedivide.o_err $abc$24881$new_n4401 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names SET_GIE.r_gie new_pc $abc$24881$new_n4402 -10 1 -.names doalu.set_ovfl wr_index[1] doalu.n doalu.pre_sign wr_index[0] $abc$24881$new_n4403 -11010 1 -11100 1 -.names $abc$24881$new_n4405 $abc$24881$new_n4403 iflags[3] $abc$24881$new_n4404 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4401 new_pc SET_GIE.r_gie $abc$24881$new_n4405 -100 1 -.names dcd_I[2] dcd_I[1] $abc$24881$new_n4471 $abc$24881$new_n4439 $abc$24881$new_n9442 $abc$24881$new_n4406 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10001 1 -10011 1 -10111 1 -11011 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][2] regset[11][2] $abc$24881$new_n4413 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][2] regset[10][2] $abc$24881$new_n4414 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[1] $abc$24881$new_n4417 $abc$24881$new_n4418 $abc$24881$new_n4416 -10000 1 -10010 1 -11000 1 -11001 1 -.names instruction_decoder.o_dcdB[2] regset[29][2] regset[25][2] $abc$24881$new_n4417 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[2] regset[28][2] regset[24][2] $abc$24881$new_n4418 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4430 regset[4][2] regset[0][2] $abc$24881$new_n4429 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[5][2] regset[1][2] $abc$24881$new_n4430 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] regset[13][2] regset[9][2] $abc$24881$new_n4432 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] regset[12][2] regset[8][2] $abc$24881$new_n4433 -001 1 -011 1 -110 1 -111 1 -.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4373 $abc$24881$new_n4435 $abc$24881$new_n4438 $abc$24881$new_n4434 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n4405 $abc$24881$new_n4436 iflags[2] $abc$24881$new_n4435 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4437 wr_index[1] wr_index[0] DIVIDE.thedivide.w_n $abc$24881$new_n4436 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -.names wr_index[1] doalu.keep_sgn_on_ovfl wr_index[0] doalu.pre_sign doalu.n $abc$24881$new_n4437 -10001 1 -10011 1 -11010 1 -11011 1 -.names $abc$24881$new_n4400 $abc$24881$new_n4436 flags[2] $abc$24881$new_n4438 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4467 $abc$24881$new_n9455 $abc$24881$new_n4368 $abc$24881$new_n3859 $abc$24881$new_n4439 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][1] regset[3][1] $abc$24881$new_n4465 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][1] regset[2][1] $abc$24881$new_n4466 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4468 $abc$24881$new_n4470 $abc$24881$new_n4467 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names $abc$24881$new_n4405 $abc$24881$new_n4469 iflags[1] $abc$24881$new_n4468 -000 1 -010 1 -110 1 -111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.r_c doalu.c $abc$24881$new_n4469 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$24881$new_n4400 $abc$24881$new_n4469 flags[1] $abc$24881$new_n4470 -000 1 -010 1 -110 1 -111 1 -.names dcd_I[0] $abc$24881$new_n4500 $abc$24881$new_n4473 $abc$24881$new_n4472 $abc$24881$new_n4474 $abc$24881$new_n4471 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4373 $abc$24881$new_n4472 -11 1 -.names $abc$24881$new_n4368 $abc$24881$new_n3863 $abc$24881$new_n4473 -10 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9868 $abc$24881$new_n4475 $abc$24881$new_n4476 dcd_Bcc $abc$24881$new_n4474 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names iflags[0] $abc$24881$new_n4405 $abc$24881$new_n4475 -10 1 -.names $abc$24881$new_n4405 $abc$24881$new_n4486 $abc$24881$new_n4480 $abc$24881$new_n4477 $abc$24881$new_n4482 $abc$24881$new_n4476 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4478 $abc$24881$new_n4479 alu_result[22] alu_result[21] alu_result[20] $abc$24881$new_n4477 -11000 1 -.names alu_result[27] alu_result[26] alu_result[25] alu_result[24] $abc$24881$new_n4478 -0000 1 -.names doalu.n alu_result[30] alu_result[29] alu_result[28] alu_result[23] $abc$24881$new_n4479 -00000 1 -.names $abc$24881$new_n4481 alu_result[7] alu_result[6] alu_result[5] alu_result[4] $abc$24881$new_n4480 -10000 1 -.names alu_result[11] alu_result[10] alu_result[9] alu_result[8] $abc$24881$new_n4481 -0000 1 -.names wr_index[1] $abc$24881$new_n4483 $abc$24881$new_n4485 $abc$24881$new_n4484 wr_index[0] $abc$24881$new_n4482 -11110 1 -.names alu_result[3] alu_result[2] alu_result[1] alu_result[0] $abc$24881$new_n4483 -0000 1 -.names alu_result[19] alu_result[18] alu_result[17] alu_result[16] $abc$24881$new_n4484 -0000 1 -.names alu_result[15] alu_result[14] alu_result[13] alu_result[12] $abc$24881$new_n4485 -0000 1 -.names wr_index[1] DIVIDE.thedivide.r_z wr_index[0] $abc$24881$new_n4486 -111 1 -.names instruction_decoder.o_dcdB[2] regset[5][0] regset[1][0] $abc$24881$new_n4495 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[2] regset[4][0] regset[0][0] $abc$24881$new_n4496 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n9871 $abc$24881$new_n4400 $abc$24881$new_n4516 $abc$24881$new_n4501 flags[0] $abc$24881$new_n4500 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$24881$new_n4486 $abc$24881$new_n4482 $abc$24881$new_n4480 $abc$24881$new_n4477 $abc$24881$new_n4501 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4504 -10 1 -.names instruction_decoder.o_dcdB[2] regset[31][0] regset[27][0] $abc$24881$new_n4508 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] regset[30][0] regset[26][0] $abc$24881$new_n4509 -001 1 -011 1 -110 1 -111 1 -.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4516 -11 1 -.names $abc$24881$new_n4373 dcd_Bcc $abc$24881$new_n4519 -10 1 -.names user_step SET_GIE.r_gie $abc$24881$new_n4520 -10 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4525 regset[13][6] regset[9][6] $abc$24881$new_n4524 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][6] regset[8][6] $abc$24881$new_n4525 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4530 regset[15][6] regset[11][6] $abc$24881$new_n4529 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][6] regset[10][6] $abc$24881$new_n4530 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4534 regset[31][6] regset[27][6] $abc$24881$new_n4533 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][6] regset[26][6] $abc$24881$new_n4534 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4537 regset[21][6] regset[17][6] $abc$24881$new_n4536 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[20][6] regset[16][6] $abc$24881$new_n4537 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4539 regset[29][6] regset[25][6] $abc$24881$new_n4538 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][6] regset[24][6] $abc$24881$new_n4539 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4541 regset[23][6] regset[19][6] $abc$24881$new_n4540 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[22][6] regset[18][6] $abc$24881$new_n4541 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4543 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][6] regset[2][6] $abc$24881$new_n4542 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][6] regset[3][6] $abc$24881$new_n4543 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4548 regset[13][5] regset[9][5] $abc$24881$new_n4547 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][5] regset[8][5] $abc$24881$new_n4548 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][5] regset[0][5] $abc$24881$new_n4549 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][5] regset[1][5] $abc$24881$new_n4550 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4553 regset[15][5] regset[11][5] $abc$24881$new_n4552 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][5] regset[10][5] $abc$24881$new_n4553 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4555 regset[7][5] regset[3][5] $abc$24881$new_n4554 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][5] regset[2][5] $abc$24881$new_n4555 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4504 $abc$24881$new_n4557 $abc$24881$new_n4069 $abc$24881$new_n4564 $abc$24881$new_n4556 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names $abc$24881$new_n4558 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4560 $abc$24881$new_n4562 $abc$24881$new_n4557 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4559 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][5] regset[18][5] $abc$24881$new_n4558 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][5] regset[19][5] $abc$24881$new_n4559 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4561 regset[21][5] regset[20][5] $abc$24881$new_n4560 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[17][5] regset[16][5] $abc$24881$new_n4561 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4563 regset[29][5] regset[25][5] $abc$24881$new_n4562 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][5] regset[24][5] $abc$24881$new_n4563 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4565 regset[31][5] regset[27][5] $abc$24881$new_n4564 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][5] regset[26][5] $abc$24881$new_n4565 -001 1 -011 1 -110 1 -111 1 -.names dcd_I[7] $abc$24881$new_n9493 $abc$24881$new_n4566 -10 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4571 $abc$24881$new_n4573 $abc$24881$new_n4575 $abc$24881$new_n4570 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4572 regset[21][7] regset[17][7] $abc$24881$new_n4571 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][7] regset[16][7] $abc$24881$new_n4572 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4574 regset[29][7] regset[28][7] $abc$24881$new_n4573 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[25][7] regset[24][7] $abc$24881$new_n4574 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4576 regset[23][7] regset[19][7] $abc$24881$new_n4575 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][7] regset[18][7] $abc$24881$new_n4576 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4578 regset[31][7] regset[30][7] $abc$24881$new_n4577 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[27][7] regset[26][7] $abc$24881$new_n4578 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4581 $abc$24881$new_n4583 $abc$24881$new_n4585 $abc$24881$new_n4580 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4582 regset[5][7] regset[1][7] $abc$24881$new_n4581 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][7] regset[0][7] $abc$24881$new_n4582 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4584 regset[13][7] regset[9][7] $abc$24881$new_n4583 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][7] regset[8][7] $abc$24881$new_n4584 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4586 regset[7][7] regset[3][7] $abc$24881$new_n4585 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][7] regset[2][7] $abc$24881$new_n4586 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4588 regset[15][7] regset[11][7] $abc$24881$new_n4587 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][7] regset[10][7] $abc$24881$new_n4588 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n9493 dcd_I[7] $abc$24881$new_n4590 -10 1 -.names $abc$24881$new_n4612 $abc$24881$new_n4592 $abc$24881$new_n4368 $abc$24881$new_n3820 $abc$24881$new_n4591 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4593 $abc$24881$new_n4603 $abc$24881$new_n4605 $abc$24881$new_n4592 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -.names $abc$24881$new_n4594 $abc$24881$new_n4601 $abc$24881$new_n4069 $abc$24881$new_n4593 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4595 $abc$24881$new_n4597 $abc$24881$new_n4599 $abc$24881$new_n4594 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4596 regset[5][8] regset[1][8] $abc$24881$new_n4595 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][8] regset[0][8] $abc$24881$new_n4596 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4598 regset[13][8] regset[9][8] $abc$24881$new_n4597 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][8] regset[8][8] $abc$24881$new_n4598 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4600 regset[7][8] regset[3][8] $abc$24881$new_n4599 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][8] regset[2][8] $abc$24881$new_n4600 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4602 regset[15][8] regset[11][8] $abc$24881$new_n4601 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][8] regset[10][8] $abc$24881$new_n4602 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4604 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][8] regset[26][8] $abc$24881$new_n4603 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][8] regset[27][8] $abc$24881$new_n4604 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4606 $abc$24881$new_n4608 $abc$24881$new_n4610 $abc$24881$new_n4605 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4607 regset[21][8] regset[17][8] $abc$24881$new_n4606 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][8] regset[16][8] $abc$24881$new_n4607 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4609 regset[29][8] regset[28][8] $abc$24881$new_n4608 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[25][8] regset[24][8] $abc$24881$new_n4609 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4611 regset[23][8] regset[19][8] $abc$24881$new_n4610 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][8] regset[18][8] $abc$24881$new_n4611 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc SET_USER_ILLEGAL_INSN.r_ill_err_u ill_err_i $abc$24881$new_n4612 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4617 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4619 $abc$24881$new_n4621 $abc$24881$new_n4616 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4618 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][10] regset[3][10] $abc$24881$new_n4617 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][10] regset[2][10] $abc$24881$new_n4618 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4620 regset[5][10] regset[1][10] $abc$24881$new_n4619 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][10] regset[0][10] $abc$24881$new_n4620 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4622 regset[13][10] regset[9][10] $abc$24881$new_n4621 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][10] regset[8][10] $abc$24881$new_n4622 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4624 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][10] regset[26][10] $abc$24881$new_n4623 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][10] regset[27][10] $abc$24881$new_n4624 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4626 $abc$24881$new_n4628 $abc$24881$new_n4630 $abc$24881$new_n4625 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4627 regset[21][10] regset[17][10] $abc$24881$new_n4626 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][10] regset[16][10] $abc$24881$new_n4627 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4629 regset[29][10] regset[28][10] $abc$24881$new_n4628 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[25][10] regset[24][10] $abc$24881$new_n4629 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4631 regset[23][10] regset[19][10] $abc$24881$new_n4630 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][10] regset[18][10] $abc$24881$new_n4631 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4633 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][10] regset[10][10] $abc$24881$new_n4632 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][10] regset[11][10] $abc$24881$new_n4633 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names dcd_I[9] $abc$24881$new_n4636 $abc$24881$new_n4635 -10 1 -.names $abc$24881$new_n4657 dcd_Bcc $abc$24881$new_n4373 $abc$24881$new_n4637 SET_TRAP_N_UBREAK.r_trap $abc$24881$new_n4636 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names $abc$24881$new_n4638 $abc$24881$new_n4648 instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4655 $abc$24881$new_n4637 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4639 $abc$24881$new_n4642 $abc$24881$new_n4644 $abc$24881$new_n4646 $abc$24881$new_n4069 $abc$24881$new_n4638 -10000 1 -10010 1 -10011 1 -.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4640 $abc$24881$new_n4639 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4641 regset[29][9] regset[25][9] $abc$24881$new_n4640 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][9] regset[24][9] $abc$24881$new_n4641 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4643 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][9] regset[16][9] $abc$24881$new_n4642 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][9] regset[17][9] $abc$24881$new_n4643 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4645 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][9] regset[18][9] $abc$24881$new_n4644 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][9] regset[19][9] $abc$24881$new_n4645 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4647 regset[31][9] regset[27][9] $abc$24881$new_n4646 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][9] regset[26][9] $abc$24881$new_n4647 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4649 $abc$24881$new_n4651 $abc$24881$new_n4653 $abc$24881$new_n4648 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4650 regset[13][9] regset[9][9] $abc$24881$new_n4649 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][9] regset[8][9] $abc$24881$new_n4650 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4652 regset[15][9] regset[11][9] $abc$24881$new_n4651 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][9] regset[10][9] $abc$24881$new_n4652 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4654 regset[5][9] regset[1][9] $abc$24881$new_n4653 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[4][9] regset[0][9] $abc$24881$new_n4654 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4656 regset[7][9] regset[3][9] $abc$24881$new_n4655 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[6][9] regset[2][9] $abc$24881$new_n4656 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4368 $abc$24881$new_n3815 $abc$24881$new_n4657 -10 1 -.names $abc$24881$new_n4636 dcd_I[9] $abc$24881$new_n4658 -10 1 -.names $abc$24881$new_n4681 $abc$24881$new_n4661 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3805 $abc$24881$new_n4660 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10011 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4662 $abc$24881$new_n4669 $abc$24881$new_n4679 $abc$24881$new_n4069 $abc$24881$new_n4661 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4663 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4665 $abc$24881$new_n4667 $abc$24881$new_n4662 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4664 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][11] regset[3][11] $abc$24881$new_n4663 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][11] regset[2][11] $abc$24881$new_n4664 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4666 regset[5][11] regset[1][11] $abc$24881$new_n4665 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][11] regset[0][11] $abc$24881$new_n4666 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4668 regset[13][11] regset[9][11] $abc$24881$new_n4667 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][11] regset[8][11] $abc$24881$new_n4668 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4672 $abc$24881$new_n4670 $abc$24881$new_n4675 $abc$24881$new_n4677 $abc$24881$new_n4069 $abc$24881$new_n4669 -00000 1 -00010 1 -00011 1 -.names $abc$24881$new_n4671 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][11] regset[18][11] $abc$24881$new_n4670 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][11] regset[19][11] $abc$24881$new_n4671 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4673 $abc$24881$new_n4672 -100 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4674 regset[29][11] regset[25][11] $abc$24881$new_n4673 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][11] regset[24][11] $abc$24881$new_n4674 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4676 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][11] regset[17][11] $abc$24881$new_n4675 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][11] regset[16][11] $abc$24881$new_n4676 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4678 regset[31][11] regset[27][11] $abc$24881$new_n4677 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][11] regset[26][11] $abc$24881$new_n4678 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4680 regset[15][11] regset[11][11] $abc$24881$new_n4679 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][11] regset[10][11] $abc$24881$new_n4680 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc DIVERR.USER_DIVERR.r_udiv_err_flag DIVERR.r_idiv_err_flag $abc$24881$new_n4681 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4687 $abc$24881$new_n4689 $abc$24881$new_n4686 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4688 regset[15][12] regset[11][12] $abc$24881$new_n4687 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][12] regset[10][12] $abc$24881$new_n4688 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4690 regset[13][12] regset[9][12] $abc$24881$new_n4689 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][12] regset[8][12] $abc$24881$new_n4690 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4692 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][12] regset[2][12] $abc$24881$new_n4691 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][12] regset[3][12] $abc$24881$new_n4692 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4695 $abc$24881$new_n4697 $abc$24881$new_n4699 $abc$24881$new_n4694 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4696 regset[21][12] regset[17][12] $abc$24881$new_n4695 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[20][12] regset[16][12] $abc$24881$new_n4696 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4698 regset[29][12] regset[25][12] $abc$24881$new_n4697 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][12] regset[24][12] $abc$24881$new_n4698 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4700 regset[31][12] regset[27][12] $abc$24881$new_n4699 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][12] regset[26][12] $abc$24881$new_n4700 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4702 regset[23][12] regset[19][12] $abc$24881$new_n4701 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[22][12] regset[18][12] $abc$24881$new_n4702 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4704 regset[5][12] regset[1][12] $abc$24881$new_n4703 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[4][12] regset[0][12] $abc$24881$new_n4704 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4709 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4711 $abc$24881$new_n4713 $abc$24881$new_n4708 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4710 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][13] regset[3][13] $abc$24881$new_n4709 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][13] regset[2][13] $abc$24881$new_n4710 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4712 regset[5][13] regset[1][13] $abc$24881$new_n4711 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][13] regset[0][13] $abc$24881$new_n4712 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4714 regset[13][13] regset[9][13] $abc$24881$new_n4713 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][13] regset[8][13] $abc$24881$new_n4714 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4716 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][13] regset[26][13] $abc$24881$new_n4715 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][13] regset[27][13] $abc$24881$new_n4716 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4718 $abc$24881$new_n4720 $abc$24881$new_n4722 $abc$24881$new_n4717 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4719 regset[21][13] regset[17][13] $abc$24881$new_n4718 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][13] regset[16][13] $abc$24881$new_n4719 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4721 regset[29][13] regset[28][13] $abc$24881$new_n4720 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[25][13] regset[24][13] $abc$24881$new_n4721 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4723 regset[23][13] regset[19][13] $abc$24881$new_n4722 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][13] regset[18][13] $abc$24881$new_n4723 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4725 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][13] regset[10][13] $abc$24881$new_n4724 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][13] regset[11][13] $abc$24881$new_n4725 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4731 $abc$24881$new_n4733 $abc$24881$new_n4730 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4732 regset[15][14] regset[11][14] $abc$24881$new_n4731 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][14] regset[10][14] $abc$24881$new_n4732 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4734 regset[13][14] regset[9][14] $abc$24881$new_n4733 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][14] regset[8][14] $abc$24881$new_n4734 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4736 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][14] regset[2][14] $abc$24881$new_n4735 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][14] regset[3][14] $abc$24881$new_n4736 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4739 $abc$24881$new_n4741 $abc$24881$new_n4743 $abc$24881$new_n4738 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4740 regset[21][14] regset[17][14] $abc$24881$new_n4739 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[20][14] regset[16][14] $abc$24881$new_n4740 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4742 regset[29][14] regset[25][14] $abc$24881$new_n4741 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][14] regset[24][14] $abc$24881$new_n4742 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4744 regset[31][14] regset[27][14] $abc$24881$new_n4743 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][14] regset[26][14] $abc$24881$new_n4744 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4746 regset[23][14] regset[19][14] $abc$24881$new_n4745 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[22][14] regset[18][14] $abc$24881$new_n4746 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4748 regset[5][14] regset[1][14] $abc$24881$new_n4747 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[4][14] regset[0][14] $abc$24881$new_n4748 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4754 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][16] regset[18][16] $abc$24881$new_n4753 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][16] regset[19][16] $abc$24881$new_n4754 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4756 regset[21][16] regset[20][16] $abc$24881$new_n4755 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[17][16] regset[16][16] $abc$24881$new_n4756 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4758 regset[29][16] regset[25][16] $abc$24881$new_n4757 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][16] regset[24][16] $abc$24881$new_n4758 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4760 regset[31][16] regset[27][16] $abc$24881$new_n4759 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][16] regset[26][16] $abc$24881$new_n4760 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4762 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4764 $abc$24881$new_n4766 $abc$24881$new_n4761 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4763 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][16] regset[11][16] $abc$24881$new_n4762 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][16] regset[10][16] $abc$24881$new_n4763 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4765 regset[13][16] regset[12][16] $abc$24881$new_n4764 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[9][16] regset[8][16] $abc$24881$new_n4765 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4767 regset[5][16] regset[1][16] $abc$24881$new_n4766 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][16] regset[0][16] $abc$24881$new_n4767 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4769 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][16] regset[2][16] $abc$24881$new_n4768 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][16] regset[3][16] $abc$24881$new_n4769 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4775 $abc$24881$new_n4777 $abc$24881$new_n4779 $abc$24881$new_n4774 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4776 regset[13][15] regset[9][15] $abc$24881$new_n4775 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][15] regset[8][15] $abc$24881$new_n4776 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4778 regset[7][15] regset[3][15] $abc$24881$new_n4777 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[6][15] regset[2][15] $abc$24881$new_n4778 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4780 regset[5][15] regset[1][15] $abc$24881$new_n4779 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[4][15] regset[0][15] $abc$24881$new_n4780 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4782 regset[15][15] regset[11][15] $abc$24881$new_n4781 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][15] regset[10][15] $abc$24881$new_n4782 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4785 $abc$24881$new_n4787 $abc$24881$new_n4784 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4786 regset[31][15] regset[27][15] $abc$24881$new_n4785 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][15] regset[26][15] $abc$24881$new_n4786 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4788 regset[29][15] regset[25][15] $abc$24881$new_n4787 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][15] regset[24][15] $abc$24881$new_n4788 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4790 regset[23][15] regset[19][15] $abc$24881$new_n4789 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[22][15] regset[18][15] $abc$24881$new_n4790 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4792 regset[21][15] regset[17][15] $abc$24881$new_n4791 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[20][15] regset[16][15] $abc$24881$new_n4792 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4800 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][17] regset[18][17] $abc$24881$new_n4799 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][17] regset[19][17] $abc$24881$new_n4800 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4802 regset[21][17] regset[20][17] $abc$24881$new_n4801 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[17][17] regset[16][17] $abc$24881$new_n4802 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4804 regset[29][17] regset[25][17] $abc$24881$new_n4803 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][17] regset[24][17] $abc$24881$new_n4804 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4806 regset[31][17] regset[27][17] $abc$24881$new_n4805 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][17] regset[26][17] $abc$24881$new_n4806 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4808 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4810 $abc$24881$new_n4812 $abc$24881$new_n4807 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4809 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][17] regset[11][17] $abc$24881$new_n4808 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][17] regset[10][17] $abc$24881$new_n4809 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4811 regset[13][17] regset[12][17] $abc$24881$new_n4810 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[9][17] regset[8][17] $abc$24881$new_n4811 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4813 regset[5][17] regset[1][17] $abc$24881$new_n4812 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][17] regset[0][17] $abc$24881$new_n4813 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4815 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][17] regset[2][17] $abc$24881$new_n4814 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][17] regset[3][17] $abc$24881$new_n4815 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4373 $abc$24881$new_n4818 $abc$24881$new_n4368 $abc$24881$new_n3769 $abc$24881$new_n4817 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4819 $abc$24881$new_n4826 $abc$24881$new_n4349 $abc$24881$new_n4836 $abc$24881$new_n4818 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4820 $abc$24881$new_n4822 $abc$24881$new_n4824 $abc$24881$new_n4819 -00000 1 -00001 1 -00010 1 -00011 1 -01010 1 -01011 1 -10001 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4821 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][18] regset[10][18] $abc$24881$new_n4820 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][18] regset[11][18] $abc$24881$new_n4821 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4823 regset[13][18] regset[9][18] $abc$24881$new_n4822 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][18] regset[8][18] $abc$24881$new_n4823 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4825 regset[7][18] regset[3][18] $abc$24881$new_n4824 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][18] regset[2][18] $abc$24881$new_n4825 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4827 $abc$24881$new_n4834 $abc$24881$new_n4356 $abc$24881$new_n4826 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4828 $abc$24881$new_n4830 $abc$24881$new_n4832 $abc$24881$new_n4827 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4829 regset[21][18] regset[17][18] $abc$24881$new_n4828 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][18] regset[16][18] $abc$24881$new_n4829 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4831 regset[29][18] regset[25][18] $abc$24881$new_n4830 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][18] regset[24][18] $abc$24881$new_n4831 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4833 regset[31][18] regset[27][18] $abc$24881$new_n4832 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][18] regset[26][18] $abc$24881$new_n4833 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4835 regset[23][18] regset[19][18] $abc$24881$new_n4834 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][18] regset[18][18] $abc$24881$new_n4835 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4837 regset[5][18] regset[1][18] $abc$24881$new_n4836 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][18] regset[0][18] $abc$24881$new_n4837 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4373 $abc$24881$new_n4840 $abc$24881$new_n4368 $abc$24881$new_n3763 $abc$24881$new_n4839 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4843 $abc$24881$new_n4841 $abc$24881$new_n4852 $abc$24881$new_n4850 $abc$24881$new_n4840 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n4842 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][19] regset[2][19] $abc$24881$new_n4841 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][19] regset[3][19] $abc$24881$new_n4842 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4844 $abc$24881$new_n4846 $abc$24881$new_n4848 $abc$24881$new_n4843 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4845 regset[5][19] regset[4][19] $abc$24881$new_n4844 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[1][19] regset[0][19] $abc$24881$new_n4845 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4847 regset[15][19] regset[11][19] $abc$24881$new_n4846 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][19] regset[10][19] $abc$24881$new_n4847 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4849 regset[13][19] regset[9][19] $abc$24881$new_n4848 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][19] regset[8][19] $abc$24881$new_n4849 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4851 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][19] regset[27][19] $abc$24881$new_n4850 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][19] regset[26][19] $abc$24881$new_n4851 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4853 $abc$24881$new_n4855 $abc$24881$new_n4857 $abc$24881$new_n4852 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4854 regset[29][19] regset[25][19] $abc$24881$new_n4853 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][19] regset[24][19] $abc$24881$new_n4854 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4856 regset[23][19] regset[19][19] $abc$24881$new_n4855 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][19] regset[18][19] $abc$24881$new_n4856 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4858 regset[21][19] regset[17][19] $abc$24881$new_n4857 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][19] regset[16][19] $abc$24881$new_n4858 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4373 $abc$24881$new_n4861 $abc$24881$new_n4368 $abc$24881$new_n3757 $abc$24881$new_n4860 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4864 $abc$24881$new_n4862 $abc$24881$new_n4873 $abc$24881$new_n4871 $abc$24881$new_n4861 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n4863 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][20] regset[11][20] $abc$24881$new_n4862 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][20] regset[10][20] $abc$24881$new_n4863 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4865 $abc$24881$new_n4867 $abc$24881$new_n4869 $abc$24881$new_n4864 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4866 regset[13][20] regset[9][20] $abc$24881$new_n4865 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][20] regset[8][20] $abc$24881$new_n4866 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4868 regset[7][20] regset[3][20] $abc$24881$new_n4867 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][20] regset[2][20] $abc$24881$new_n4868 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4870 regset[5][20] regset[1][20] $abc$24881$new_n4869 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][20] regset[0][20] $abc$24881$new_n4870 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4872 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][20] regset[18][20] $abc$24881$new_n4871 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][20] regset[19][20] $abc$24881$new_n4872 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4874 $abc$24881$new_n4876 $abc$24881$new_n4878 $abc$24881$new_n4873 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4875 regset[21][20] regset[20][20] $abc$24881$new_n4874 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[17][20] regset[16][20] $abc$24881$new_n4875 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4877 regset[31][20] regset[27][20] $abc$24881$new_n4876 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][20] regset[26][20] $abc$24881$new_n4877 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4879 regset[29][20] regset[25][20] $abc$24881$new_n4878 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][20] regset[24][20] $abc$24881$new_n4879 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4885 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4887 $abc$24881$new_n4889 $abc$24881$new_n4884 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -.names $abc$24881$new_n4886 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][21] regset[16][21] $abc$24881$new_n4885 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][21] regset[17][21] $abc$24881$new_n4886 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4888 regset[29][21] regset[25][21] $abc$24881$new_n4887 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][21] regset[24][21] $abc$24881$new_n4888 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4890 regset[31][21] regset[27][21] $abc$24881$new_n4889 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][21] regset[26][21] $abc$24881$new_n4890 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[1] $abc$24881$new_n4894 $abc$24881$new_n4901 instruction_decoder.o_dcdB[3] $abc$24881$new_n4899 $abc$24881$new_n4893 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] $abc$24881$new_n4895 $abc$24881$new_n4897 $abc$24881$new_n4898 $abc$24881$new_n4894 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4896 regset[13][21] regset[9][21] $abc$24881$new_n4895 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][21] regset[8][21] $abc$24881$new_n4896 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[2] regset[4][21] regset[0][21] $abc$24881$new_n4897 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] regset[5][21] regset[1][21] $abc$24881$new_n4898 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4900 regset[15][21] regset[11][21] $abc$24881$new_n4899 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][21] regset[10][21] $abc$24881$new_n4900 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4902 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][21] regset[2][21] $abc$24881$new_n4901 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][21] regset[3][21] $abc$24881$new_n4902 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names $abc$24881$new_n4373 $abc$24881$new_n4905 $abc$24881$new_n4368 $abc$24881$new_n3747 $abc$24881$new_n4904 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4906 $abc$24881$new_n4913 $abc$24881$new_n4356 $abc$24881$new_n4923 $abc$24881$new_n4905 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4907 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4909 $abc$24881$new_n4911 $abc$24881$new_n4906 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names $abc$24881$new_n4908 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][22] regset[0][22] $abc$24881$new_n4907 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][22] regset[1][22] $abc$24881$new_n4908 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4910 regset[15][22] regset[11][22] $abc$24881$new_n4909 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][22] regset[10][22] $abc$24881$new_n4910 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4912 regset[13][22] regset[9][22] $abc$24881$new_n4911 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][22] regset[8][22] $abc$24881$new_n4912 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4914 $abc$24881$new_n4921 $abc$24881$new_n4069 $abc$24881$new_n4913 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4915 $abc$24881$new_n4917 $abc$24881$new_n4919 $abc$24881$new_n4914 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4916 regset[21][22] regset[17][22] $abc$24881$new_n4915 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][22] regset[16][22] $abc$24881$new_n4916 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4918 regset[22][22] regset[18][22] $abc$24881$new_n4917 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[23][22] regset[19][22] $abc$24881$new_n4918 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4920 regset[29][22] regset[25][22] $abc$24881$new_n4919 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][22] regset[24][22] $abc$24881$new_n4920 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4922 regset[31][22] regset[27][22] $abc$24881$new_n4921 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][22] regset[26][22] $abc$24881$new_n4922 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4924 regset[7][22] regset[3][22] $abc$24881$new_n4923 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][22] regset[2][22] $abc$24881$new_n4924 -001 1 -011 1 -110 1 -111 1 -.names dcd_I[31] $abc$24881$new_n9521 $abc$24881$new_n4925 -00 1 -11 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4930 $abc$24881$new_n4932 $abc$24881$new_n4934 $abc$24881$new_n4929 -00010 1 -00011 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4931 regset[23][24] regset[19][24] $abc$24881$new_n4930 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][24] regset[18][24] $abc$24881$new_n4931 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4933 regset[21][24] regset[17][24] $abc$24881$new_n4932 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][24] regset[16][24] $abc$24881$new_n4933 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4935 regset[29][24] regset[28][24] $abc$24881$new_n4934 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[25][24] regset[24][24] $abc$24881$new_n4935 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4937 regset[31][24] regset[30][24] $abc$24881$new_n4936 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[27][24] regset[26][24] $abc$24881$new_n4937 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4940 $abc$24881$new_n4942 $abc$24881$new_n4944 $abc$24881$new_n4939 -00010 1 -00011 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4941 regset[7][24] regset[3][24] $abc$24881$new_n4940 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][24] regset[2][24] $abc$24881$new_n4941 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4943 regset[5][24] regset[1][24] $abc$24881$new_n4942 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][24] regset[0][24] $abc$24881$new_n4943 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4945 regset[13][24] regset[9][24] $abc$24881$new_n4944 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][24] regset[8][24] $abc$24881$new_n4945 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4947 regset[15][24] regset[11][24] $abc$24881$new_n4946 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][24] regset[10][24] $abc$24881$new_n4947 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n9524 dcd_I[31] $abc$24881$new_n4948 -10 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4953 $abc$24881$new_n4955 $abc$24881$new_n4957 $abc$24881$new_n4952 -00010 1 -00011 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4954 regset[23][23] regset[19][23] $abc$24881$new_n4953 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][23] regset[18][23] $abc$24881$new_n4954 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4956 regset[21][23] regset[17][23] $abc$24881$new_n4955 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][23] regset[16][23] $abc$24881$new_n4956 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4958 regset[29][23] regset[28][23] $abc$24881$new_n4957 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[25][23] regset[24][23] $abc$24881$new_n4958 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4960 regset[31][23] regset[30][23] $abc$24881$new_n4959 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[27][23] regset[26][23] $abc$24881$new_n4960 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4963 $abc$24881$new_n4965 $abc$24881$new_n4967 $abc$24881$new_n4962 -00010 1 -00011 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4964 regset[7][23] regset[3][23] $abc$24881$new_n4963 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][23] regset[2][23] $abc$24881$new_n4964 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4966 regset[5][23] regset[1][23] $abc$24881$new_n4965 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][23] regset[0][23] $abc$24881$new_n4966 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4968 regset[13][23] regset[9][23] $abc$24881$new_n4967 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][23] regset[8][23] $abc$24881$new_n4968 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4970 regset[15][23] regset[11][23] $abc$24881$new_n4969 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][23] regset[10][23] $abc$24881$new_n4970 -001 1 -011 1 -110 1 -111 1 -.names dcd_I[31] $abc$24881$new_n9524 $abc$24881$new_n4971 -10 1 -.names dcd_I[31] $abc$24881$new_n9527 $abc$24881$new_n4972 -00 1 -11 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4977 $abc$24881$new_n4979 $abc$24881$new_n4981 $abc$24881$new_n4976 -00010 1 -00011 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4978 regset[23][25] regset[19][25] $abc$24881$new_n4977 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][25] regset[18][25] $abc$24881$new_n4978 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4980 regset[21][25] regset[17][25] $abc$24881$new_n4979 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][25] regset[16][25] $abc$24881$new_n4980 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4982 regset[29][25] regset[28][25] $abc$24881$new_n4981 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[25][25] regset[24][25] $abc$24881$new_n4982 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4984 regset[31][25] regset[30][25] $abc$24881$new_n4983 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[27][25] regset[26][25] $abc$24881$new_n4984 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4987 $abc$24881$new_n4989 $abc$24881$new_n4991 $abc$24881$new_n4986 -00010 1 -00011 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4988 regset[7][25] regset[3][25] $abc$24881$new_n4987 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][25] regset[2][25] $abc$24881$new_n4988 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4990 regset[5][25] regset[1][25] $abc$24881$new_n4989 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][25] regset[0][25] $abc$24881$new_n4990 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4992 regset[13][25] regset[9][25] $abc$24881$new_n4991 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][25] regset[8][25] $abc$24881$new_n4992 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4994 regset[15][25] regset[11][25] $abc$24881$new_n4993 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][25] regset[10][25] $abc$24881$new_n4994 -001 1 -011 1 -110 1 -111 1 -.names dcd_I[31] $abc$24881$new_n9533 $abc$24881$new_n9530 $abc$24881$new_n4996 $abc$24881$new_n4995 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1111 1 -.names dcd_I[31] $abc$24881$new_n9521 $abc$24881$new_n9527 $abc$24881$new_n4996 -000 1 -001 1 -010 1 -011 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5001 $abc$24881$new_n5003 $abc$24881$new_n5005 $abc$24881$new_n5000 -00010 1 -00011 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5002 regset[23][27] regset[19][27] $abc$24881$new_n5001 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[22][27] regset[18][27] $abc$24881$new_n5002 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5004 regset[21][27] regset[17][27] $abc$24881$new_n5003 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][27] regset[16][27] $abc$24881$new_n5004 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5006 regset[29][27] regset[28][27] $abc$24881$new_n5005 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[25][27] regset[24][27] $abc$24881$new_n5006 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5008 regset[31][27] regset[30][27] $abc$24881$new_n5007 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[27][27] regset[26][27] $abc$24881$new_n5008 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5011 $abc$24881$new_n5013 $abc$24881$new_n5015 $abc$24881$new_n5010 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5012 regset[15][27] regset[11][27] $abc$24881$new_n5011 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[14][27] regset[10][27] $abc$24881$new_n5012 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5014 regset[13][27] regset[9][27] $abc$24881$new_n5013 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[12][27] regset[8][27] $abc$24881$new_n5014 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5016 regset[5][27] regset[1][27] $abc$24881$new_n5015 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][27] regset[0][27] $abc$24881$new_n5016 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5018 regset[7][27] regset[3][27] $abc$24881$new_n5017 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][27] regset[2][27] $abc$24881$new_n5018 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5023 $abc$24881$new_n5025 $abc$24881$new_n5027 $abc$24881$new_n5022 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5024 regset[13][26] regset[9][26] $abc$24881$new_n5023 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][26] regset[8][26] $abc$24881$new_n5024 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5026 regset[7][26] regset[3][26] $abc$24881$new_n5025 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[6][26] regset[2][26] $abc$24881$new_n5026 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5028 regset[5][26] regset[1][26] $abc$24881$new_n5027 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[4][26] regset[0][26] $abc$24881$new_n5028 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5030 regset[15][26] regset[11][26] $abc$24881$new_n5029 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][26] regset[10][26] $abc$24881$new_n5030 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5033 $abc$24881$new_n5035 $abc$24881$new_n5032 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5034 regset[31][26] regset[27][26] $abc$24881$new_n5033 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][26] regset[26][26] $abc$24881$new_n5034 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5036 regset[29][26] regset[25][26] $abc$24881$new_n5035 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][26] regset[24][26] $abc$24881$new_n5036 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5038 regset[23][26] regset[19][26] $abc$24881$new_n5037 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[22][26] regset[18][26] $abc$24881$new_n5038 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5040 regset[21][26] regset[17][26] $abc$24881$new_n5039 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[20][26] regset[16][26] $abc$24881$new_n5040 -000 1 -010 1 -100 1 -101 1 -.names dcd_I[31] $abc$24881$new_n9533 $abc$24881$new_n9530 $abc$24881$new_n5041 -000 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5046 regset[31][28] regset[27][28] $abc$24881$new_n5045 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][28] regset[26][28] $abc$24881$new_n5046 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5049 regset[29][28] regset[25][28] $abc$24881$new_n5048 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][28] regset[24][28] $abc$24881$new_n5049 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5051 regset[21][28] regset[17][28] $abc$24881$new_n5050 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[20][28] regset[16][28] $abc$24881$new_n5051 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5053 regset[23][28] regset[19][28] $abc$24881$new_n5052 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[22][28] regset[18][28] $abc$24881$new_n5053 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5056 regset[7][28] regset[3][28] $abc$24881$new_n5055 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[6][28] regset[2][28] $abc$24881$new_n5056 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5059 regset[15][28] regset[11][28] $abc$24881$new_n5058 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][28] regset[10][28] $abc$24881$new_n5059 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5062 regset[13][28] regset[9][28] $abc$24881$new_n5061 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][28] regset[8][28] $abc$24881$new_n5062 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5064 regset[5][28] regset[1][28] $abc$24881$new_n5063 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[4][28] regset[0][28] $abc$24881$new_n5064 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5065 -10 1 -.names $abc$24881$new_n4029 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$new_n5066 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names dcd_rB dcd_Bpc $abc$24881$new_n5067 -11 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5073 regset[7][29] regset[3][29] $abc$24881$new_n5072 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][29] regset[2][29] $abc$24881$new_n5073 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5075 regset[13][29] regset[9][29] $abc$24881$new_n5074 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][29] regset[8][29] $abc$24881$new_n5075 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5077 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][29] regset[0][29] $abc$24881$new_n5076 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][29] regset[1][29] $abc$24881$new_n5077 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5079 regset[15][29] regset[11][29] $abc$24881$new_n5078 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][29] regset[10][29] $abc$24881$new_n5079 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5081 instruction_decoder.o_dcdB[3] $abc$24881$new_n5089 $abc$24881$new_n5088 instruction_decoder.o_dcdB[1] $abc$24881$new_n5080 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5082 $abc$24881$new_n5084 $abc$24881$new_n5086 $abc$24881$new_n5081 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5083 regset[23][29] regset[22][29] $abc$24881$new_n5082 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[19][29] regset[18][29] $abc$24881$new_n5083 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5085 regset[21][29] regset[17][29] $abc$24881$new_n5084 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[20][29] regset[16][29] $abc$24881$new_n5085 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5087 regset[31][29] regset[27][29] $abc$24881$new_n5086 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][29] regset[26][29] $abc$24881$new_n5087 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[28][29] regset[24][29] $abc$24881$new_n5088 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][29] regset[25][29] $abc$24881$new_n5089 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n3702 $abc$24881$new_n4368 $abc$24881$new_n4519 $abc$24881$new_n5091 $abc$24881$new_n5101 $abc$24881$new_n5090 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5092 instruction_decoder.o_dcdB[4] $abc$24881$new_n5099 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5091 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5093 $abc$24881$new_n5095 $abc$24881$new_n5097 $abc$24881$new_n5092 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5094 regset[5][30] regset[1][30] $abc$24881$new_n5093 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[4][30] regset[0][30] $abc$24881$new_n5094 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5096 regset[15][30] regset[11][30] $abc$24881$new_n5095 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[14][30] regset[10][30] $abc$24881$new_n5096 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5098 regset[7][30] regset[3][30] $abc$24881$new_n5097 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[6][30] regset[2][30] $abc$24881$new_n5098 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5100 regset[13][30] regset[9][30] $abc$24881$new_n5099 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[12][30] regset[8][30] $abc$24881$new_n5100 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n5102 $abc$24881$new_n5109 $abc$24881$new_n4349 $abc$24881$new_n5101 -1100 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5103 $abc$24881$new_n5105 $abc$24881$new_n5107 $abc$24881$new_n5102 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5104 regset[31][30] regset[27][30] $abc$24881$new_n5103 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[30][30] regset[26][30] $abc$24881$new_n5104 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5106 regset[29][30] regset[25][30] $abc$24881$new_n5105 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[28][30] regset[24][30] $abc$24881$new_n5106 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5108 regset[23][30] regset[19][30] $abc$24881$new_n5107 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[22][30] regset[18][30] $abc$24881$new_n5108 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5110 regset[21][30] regset[17][30] $abc$24881$new_n5109 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[2] regset[20][30] regset[16][30] $abc$24881$new_n5110 -000 1 -010 1 -100 1 -101 1 -.names dcd_I[31] $abc$24881$new_n5146 $abc$24881$new_n5145 $abc$24881$new_n5144 $abc$24881$new_n5114 $abc$24881$new_n5113 -00000 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4068 dcd_I[31] $abc$24881$new_n5115 SET_USER_PC.r_upc[24] instruction_decoder.o_pc[24] $abc$24881$new_n5114 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$24881$new_n4068 dcd_I[21] $abc$24881$new_n5116 SET_USER_PC.r_upc[23] instruction_decoder.o_pc[23] $abc$24881$new_n5115 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$24881$new_n5143 dcd_I[19] dcd_I[20] $abc$24881$new_n5142 $abc$24881$new_n5117 $abc$24881$new_n5116 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5141 dcd_I[17] dcd_I[18] $abc$24881$new_n5140 $abc$24881$new_n5118 $abc$24881$new_n5117 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5139 dcd_I[15] dcd_I[16] $abc$24881$new_n5138 $abc$24881$new_n5119 $abc$24881$new_n5118 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5137 dcd_I[13] dcd_I[14] $abc$24881$new_n5136 $abc$24881$new_n5120 $abc$24881$new_n5119 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5135 dcd_I[11] dcd_I[12] $abc$24881$new_n5134 $abc$24881$new_n5121 $abc$24881$new_n5120 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5133 dcd_I[9] dcd_I[10] $abc$24881$new_n5132 $abc$24881$new_n5122 $abc$24881$new_n5121 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5131 dcd_I[7] dcd_I[8] $abc$24881$new_n5130 $abc$24881$new_n5123 $abc$24881$new_n5122 -00001 1 -00010 1 -00011 1 -00111 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n4068 dcd_I[6] $abc$24881$new_n5124 SET_USER_PC.r_upc[8] instruction_decoder.o_pc[8] $abc$24881$new_n5123 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$24881$new_n4068 dcd_I[5] $abc$24881$new_n5125 SET_USER_PC.r_upc[7] instruction_decoder.o_pc[7] $abc$24881$new_n5124 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$24881$new_n4068 dcd_I[4] $abc$24881$new_n5126 SET_USER_PC.r_upc[6] instruction_decoder.o_pc[6] $abc$24881$new_n5125 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$24881$new_n4068 dcd_I[3] $abc$24881$new_n5127 SET_USER_PC.r_upc[5] instruction_decoder.o_pc[5] $abc$24881$new_n5126 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$24881$new_n4068 dcd_I[2] $abc$24881$new_n5128 SET_USER_PC.r_upc[4] instruction_decoder.o_pc[4] $abc$24881$new_n5127 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names $abc$24881$new_n4068 dcd_I[1] $abc$24881$new_n5129 SET_USER_PC.r_upc[3] instruction_decoder.o_pc[3] $abc$24881$new_n5128 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11010 1 -.names dcd_I[0] SET_GIE.r_gie instruction_decoder.o_dcdB[4] instruction_decoder.o_pc[2] SET_USER_PC.r_upc[2] $abc$24881$new_n5129 -10010 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[10] SET_USER_PC.r_upc[10] $abc$24881$new_n5130 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[9] SET_USER_PC.r_upc[9] $abc$24881$new_n5131 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[12] SET_USER_PC.r_upc[12] $abc$24881$new_n5132 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[11] SET_USER_PC.r_upc[11] $abc$24881$new_n5133 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[14] SET_USER_PC.r_upc[14] $abc$24881$new_n5134 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[13] SET_USER_PC.r_upc[13] $abc$24881$new_n5135 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[16] SET_USER_PC.r_upc[16] $abc$24881$new_n5136 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[15] SET_USER_PC.r_upc[15] $abc$24881$new_n5137 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[18] SET_USER_PC.r_upc[18] $abc$24881$new_n5138 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[17] SET_USER_PC.r_upc[17] $abc$24881$new_n5139 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[20] SET_USER_PC.r_upc[20] $abc$24881$new_n5140 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[19] SET_USER_PC.r_upc[19] $abc$24881$new_n5141 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[22] SET_USER_PC.r_upc[22] $abc$24881$new_n5142 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[21] SET_USER_PC.r_upc[21] $abc$24881$new_n5143 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[27] SET_USER_PC.r_upc[27] $abc$24881$new_n5144 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[26] SET_USER_PC.r_upc[26] $abc$24881$new_n5145 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[25] SET_USER_PC.r_upc[25] $abc$24881$new_n5146 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[29] SET_USER_PC.r_upc[29] $abc$24881$new_n5147 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[28] SET_USER_PC.r_upc[28] $abc$24881$new_n5148 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4068 instruction_decoder.o_pc[30] SET_USER_PC.r_upc[30] $abc$24881$new_n5149 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3702 r_op_Bv[30] o_mem_addr[30] -001 1 -011 1 -100 1 -101 1 -.names OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n5151 -111 1 -.names $abc$24881$new_n5153 $abc$24881$new_n5154 $abc$24881$new_n3700 dbgv i_mem_valid $abc$24881$new_n5152 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[2] i_mem_wreg[2] alu_reg[2] $abc$24881$new_n5153 -0000 1 -0010 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names OP_REG_ADVANEC.r_op_Bid[1] i_mem_valid alu_reg[1] i_mem_wreg[1] $abc$24881$new_n5154 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$24881$new_n5157 $abc$24881$new_n5156 OP_REG_ADVANEC.r_op_Bid[0] $abc$24881$new_n3697 $abc$24881$new_n5158 $abc$24881$new_n5155 -11010 1 -11100 1 -.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[3] i_mem_wreg[3] alu_reg[3] $abc$24881$new_n5156 -0000 1 -0010 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[4] i_mem_wreg[4] alu_reg[4] $abc$24881$new_n5157 -0000 1 -0010 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[1] alu_reg[1] i_mem_wreg[1] $abc$24881$new_n5158 -0010 1 -0011 1 -1001 1 -1011 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3708 r_op_Bv[29] o_mem_addr[29] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n4995 $abc$24881$new_n4329 $abc$24881$new_n5041 $abc$24881$new_n5166 -100 1 -101 1 -110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3714 r_op_Bv[28] o_mem_addr[28] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5170 o_mem_addr[27] $abc$24881$new_n5067 $abc$24881$new_n5172 $abc$24881$auto$rtlil.cc:2693:MuxGate$22930 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9530 dcd_I[31] $abc$24881$new_n5067 $abc$24881$new_n9533 $abc$24881$new_n5171 $abc$24881$new_n5170 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -10000 1 -11011 1 -.names $abc$24881$new_n4996 $abc$24881$new_n4329 $abc$24881$new_n5171 -10 1 -.names dcd_I[31] $abc$24881$new_n5144 $abc$24881$new_n5146 $abc$24881$new_n5145 $abc$24881$new_n5114 $abc$24881$new_n5172 -00000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3719 r_op_Bv[27] o_mem_addr[27] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n9548 $abc$24881$new_n3725 r_op_Bv[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$22932 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5067 $abc$24881$new_n5066 $abc$24881$new_n5177 -11 1 -.names $abc$24881$new_n5066 dcd_I[31] $abc$24881$new_n5146 $abc$24881$new_n5114 $abc$24881$new_n5067 $abc$24881$new_n5182 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n5066 o_mem_addr[24] $abc$24881$new_n5185 $abc$24881$new_n5186 $abc$24881$auto$rtlil.cc:2693:MuxGate$22936 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5065 $abc$24881$new_n4925 $abc$24881$new_n4948 $abc$24881$new_n4971 $abc$24881$new_n9843 $abc$24881$new_n5185 -10000 1 -10010 1 -10011 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5067 $abc$24881$new_n5187 $abc$24881$new_n5115 $abc$24881$new_n5186 -100 1 -111 1 -.names dcd_I[31] $abc$24881$new_n4068 SET_USER_PC.r_upc[24] instruction_decoder.o_pc[24] $abc$24881$new_n5187 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3735 r_op_Bv[24] o_mem_addr[24] -001 1 -011 1 -100 1 -101 1 -.names dcd_I[21] $abc$24881$new_n5116 $abc$24881$new_n4068 SET_USER_PC.r_upc[23] instruction_decoder.o_pc[23] $abc$24881$new_n5192 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names dcd_I[20] $abc$24881$new_n5142 dcd_I[19] $abc$24881$new_n5143 $abc$24881$new_n5117 $abc$24881$new_n5196 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3747 r_op_Bv[22] o_mem_addr[22] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5177 dcd_I[19] $abc$24881$new_n5143 $abc$24881$new_n5117 $abc$24881$new_n5201 -1000 1 -1011 1 -1101 1 -1110 1 -.names dcd_I[18] $abc$24881$new_n5140 dcd_I[17] $abc$24881$new_n5141 $abc$24881$new_n5118 $abc$24881$new_n5205 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3757 r_op_Bv[20] o_mem_addr[20] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[19] $abc$24881$new_n5208 $abc$24881$new_n5209 $abc$24881$auto$rtlil.cc:2693:MuxGate$22946 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names dcd_I[19] $abc$24881$new_n4839 $abc$24881$new_n9845 $abc$24881$new_n5208 -001 1 -010 1 -100 1 -111 1 -.names dcd_I[17] $abc$24881$new_n5141 $abc$24881$new_n5118 $abc$24881$new_n5209 -000 1 -011 1 -101 1 -110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3763 r_op_Bv[19] o_mem_addr[19] -001 1 -011 1 -100 1 -101 1 -.names dcd_I[16] $abc$24881$new_n5138 dcd_I[15] $abc$24881$new_n5139 $abc$24881$new_n5119 $abc$24881$new_n5214 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3769 r_op_Bv[18] o_mem_addr[18] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5177 dcd_I[15] $abc$24881$new_n5139 $abc$24881$new_n5119 $abc$24881$new_n5219 -1000 1 -1011 1 -1101 1 -1110 1 -.names dcd_I[14] $abc$24881$new_n5136 dcd_I[13] $abc$24881$new_n5137 $abc$24881$new_n5120 $abc$24881$new_n5223 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names dcd_I[16] $abc$24881$new_n9508 $abc$24881$new_n5224 -00 1 -11 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3779 r_op_Bv[16] o_mem_addr[16] -001 1 -011 1 -100 1 -101 1 -.names dcd_I[13] $abc$24881$new_n5137 $abc$24881$new_n5120 $abc$24881$new_n5229 -001 1 -010 1 -100 1 -111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5231 o_mem_addr[14] $abc$24881$new_n5067 $abc$24881$new_n5233 $abc$24881$auto$rtlil.cc:2693:MuxGate$22956 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5065 dcd_I[14] $abc$24881$new_n9505 $abc$24881$new_n5232 $abc$24881$new_n5231 -1001 1 -1010 1 -1100 1 -1111 1 -.names $abc$24881$new_n9502 dcd_I[13] $abc$24881$new_n9847 $abc$24881$new_n5232 -001 1 -100 1 -101 1 -111 1 -.names dcd_I[12] $abc$24881$new_n5134 dcd_I[11] $abc$24881$new_n5135 $abc$24881$new_n5121 $abc$24881$new_n5233 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3790 r_op_Bv[14] o_mem_addr[14] -001 1 -011 1 -100 1 -101 1 -.names dcd_I[11] $abc$24881$new_n5135 $abc$24881$new_n5121 $abc$24881$new_n5238 -001 1 -010 1 -100 1 -111 1 -.names dcd_I[10] $abc$24881$new_n5132 dcd_I[9] $abc$24881$new_n5133 $abc$24881$new_n5122 $abc$24881$new_n5242 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3800 r_op_Bv[12] o_mem_addr[12] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5245 $abc$24881$new_n3805 r_op_Bv[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22962 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5246 dcd_I[9] $abc$24881$new_n5133 $abc$24881$new_n5122 $abc$24881$new_n5177 $abc$24881$new_n5245 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01100 1 -01110 1 -01111 1 -.names $abc$24881$new_n5065 dcd_I[11] $abc$24881$new_n4660 $abc$24881$new_n4336 $abc$24881$new_n5246 -1000 1 -1011 1 -1101 1 -1110 1 -.names dcd_I[8] $abc$24881$new_n5130 dcd_I[7] $abc$24881$new_n5131 $abc$24881$new_n5123 $abc$24881$new_n5250 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3810 r_op_Bv[10] o_mem_addr[10] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5066 o_mem_addr[9] $abc$24881$new_n5253 $abc$24881$new_n5254 $abc$24881$auto$rtlil.cc:2693:MuxGate$22966 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5065 $abc$24881$new_n4337 $abc$24881$new_n4658 $abc$24881$new_n4635 $abc$24881$new_n5253 -1001 1 -1010 1 -1011 1 -1100 1 -.names $abc$24881$new_n5067 dcd_I[7] $abc$24881$new_n5131 $abc$24881$new_n5123 $abc$24881$new_n5254 -1001 1 -1010 1 -1100 1 -1111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3815 r_op_Bv[9] o_mem_addr[9] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5257 $abc$24881$new_n3820 r_op_Bv[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22968 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5259 $abc$24881$new_n5258 $abc$24881$new_n5260 $abc$24881$new_n5257 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$24881$new_n4566 $abc$24881$new_n4338 $abc$24881$new_n4590 $abc$24881$new_n5258 -001 1 -010 1 -011 1 -.names dcd_I[8] $abc$24881$new_n4591 $abc$24881$new_n5259 -00 1 -11 1 -.names dcd_I[6] $abc$24881$new_n5124 $abc$24881$new_n4068 SET_USER_PC.r_upc[8] instruction_decoder.o_pc[8] $abc$24881$new_n5260 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5262 $abc$24881$new_n3825 r_op_Bv[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22970 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5263 $abc$24881$new_n5264 $abc$24881$new_n5125 $abc$24881$new_n5177 $abc$24881$new_n5262 -0000 1 -0001 1 -0010 1 -0100 1 -0110 1 -0111 1 -.names $abc$24881$new_n5065 dcd_I[7] $abc$24881$new_n9493 $abc$24881$new_n4338 $abc$24881$new_n5263 -1000 1 -1011 1 -1101 1 -1110 1 -.names dcd_I[5] $abc$24881$new_n4068 SET_USER_PC.r_upc[7] instruction_decoder.o_pc[7] $abc$24881$new_n5264 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5266 $abc$24881$new_n3832 r_op_Bv[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22972 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5268 $abc$24881$new_n5267 $abc$24881$new_n5269 $abc$24881$new_n5266 -10010 1 -10011 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$24881$new_n9489 dcd_I[5] $abc$24881$new_n4339 $abc$24881$new_n5267 -001 1 -100 1 -101 1 -111 1 -.names dcd_I[6] $abc$24881$new_n9873 $abc$24881$new_n5268 -00 1 -11 1 -.names dcd_I[4] $abc$24881$new_n5126 $abc$24881$new_n4068 SET_USER_PC.r_upc[6] instruction_decoder.o_pc[6] $abc$24881$new_n5269 -00000 1 -00001 1 -00100 1 -00110 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5271 $abc$24881$new_n3838 r_op_Bv[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22974 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5272 $abc$24881$new_n5273 $abc$24881$new_n5127 $abc$24881$new_n5177 $abc$24881$new_n5271 -0000 1 -0001 1 -0010 1 -0100 1 -0110 1 -0111 1 -.names $abc$24881$new_n5065 dcd_I[5] $abc$24881$new_n9489 $abc$24881$new_n4339 $abc$24881$new_n5272 -1000 1 -1011 1 -1101 1 -1110 1 -.names dcd_I[3] $abc$24881$new_n4068 SET_USER_PC.r_upc[5] instruction_decoder.o_pc[5] $abc$24881$new_n5273 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$24881$new_n4406 dcd_I[3] $abc$24881$new_n9436 $abc$24881$new_n5276 -001 1 -100 1 -101 1 -111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3843 r_op_Bv[4] o_mem_addr[4] -001 1 -011 1 -100 1 -101 1 -.names dcd_I[2] $abc$24881$new_n4068 SET_USER_PC.r_upc[4] instruction_decoder.o_pc[4] $abc$24881$new_n5279 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5281 o_mem_addr[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22978 -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5067 $abc$24881$new_n5129 $abc$24881$new_n5283 $abc$24881$new_n5282 $abc$24881$new_n5281 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names dcd_I[3] $abc$24881$new_n4406 $abc$24881$new_n9436 $abc$24881$new_n5282 -000 1 -011 1 -101 1 -110 1 -.names dcd_I[1] $abc$24881$new_n4068 SET_USER_PC.r_upc[3] instruction_decoder.o_pc[3] $abc$24881$new_n5283 -0010 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names r_op_Bv[3] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3848 o_mem_addr[3] -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5286 $abc$24881$new_n3853 r_op_Bv[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22980 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5287 $abc$24881$new_n5065 $abc$24881$new_n5288 $abc$24881$new_n5286 -000 1 -001 1 -011 1 -.names $abc$24881$new_n5177 dcd_I[0] $abc$24881$new_n4068 SET_USER_PC.r_upc[2] instruction_decoder.o_pc[2] $abc$24881$new_n5287 -10000 1 -10001 1 -10100 1 -10110 1 -11010 1 -11011 1 -11101 1 -11111 1 -.names dcd_I[2] $abc$24881$new_n9442 dcd_I[1] $abc$24881$new_n4471 $abc$24881$new_n4439 $abc$24881$new_n5288 -00000 1 -00001 1 -00011 1 -00101 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5290 o_mem_addr[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22982 -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5067 $abc$24881$new_n4471 $abc$24881$new_n5291 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4068 $abc$24881$new_n5290 -00000 1 -00001 1 -00010 1 -00011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names dcd_I[1] $abc$24881$new_n4439 $abc$24881$new_n5291 -00 1 -11 1 -.names r_op_Bv[1] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3859 o_mem_addr[1] -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n5066 dcd_I[0] $abc$24881$new_n5294 $abc$24881$new_n5067 o_mem_addr[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22984 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -11100 1 -11101 1 -.names $abc$24881$new_n4473 $abc$24881$new_n4500 $abc$24881$new_n4472 $abc$24881$new_n4474 $abc$24881$new_n5294 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -.names r_op_Bv[0] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3863 o_mem_addr[0] -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[5] r_op_F[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22986 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[4] r_op_F[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22988 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[3] r_op_F[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22990 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[2] r_op_F[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22992 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[1] r_op_F[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22994 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[0] r_op_F[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22996 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] instruction_decoder.o_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$22998 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] instruction_decoder.o_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23000 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[28] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] instruction_decoder.o_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23002 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[27] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] instruction_decoder.o_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23004 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[26] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] instruction_decoder.o_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23006 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[25] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] instruction_decoder.o_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23008 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[24] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] instruction_decoder.o_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23010 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[23] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] instruction_decoder.o_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23012 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[22] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] instruction_decoder.o_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23014 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] instruction_decoder.o_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23016 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] instruction_decoder.o_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23018 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.o_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23020 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.o_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23022 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.o_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23024 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[16] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] instruction_decoder.o_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23026 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] instruction_decoder.o_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23028 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] instruction_decoder.o_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23030 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] instruction_decoder.o_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23032 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] instruction_decoder.o_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23034 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] instruction_decoder.o_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23036 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.o_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23038 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.o_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23040 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] instruction_decoder.o_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23042 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] instruction_decoder.o_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23044 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.o_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23046 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[5] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] instruction_decoder.o_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23048 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] instruction_decoder.o_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23050 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] instruction_decoder.o_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23052 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.o_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23054 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4030 wr_index[0] op_valid_div op_valid_mem $abc$24881$auto$rtlil.cc:2693:MuxGate$23056 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3963 GEN_ALU_PC.r_alu_pc[30] ipc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23058 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4035 $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$new_n5333 -110 1 -.names SET_GIE.r_gie GEN_ALU_PHASE.r_alu_phase $abc$24881$new_n3961 $abc$24881$new_n5334 -000 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3965 GEN_ALU_PC.r_alu_pc[29] ipc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23060 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3967 GEN_ALU_PC.r_alu_pc[28] ipc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23062 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3969 GEN_ALU_PC.r_alu_pc[27] ipc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23064 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3971 GEN_ALU_PC.r_alu_pc[26] ipc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23066 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3973 GEN_ALU_PC.r_alu_pc[25] ipc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23068 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3975 GEN_ALU_PC.r_alu_pc[24] ipc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23070 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3977 GEN_ALU_PC.r_alu_pc[23] ipc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23072 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3979 GEN_ALU_PC.r_alu_pc[22] ipc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23074 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3981 GEN_ALU_PC.r_alu_pc[21] ipc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23076 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3983 GEN_ALU_PC.r_alu_pc[20] ipc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23078 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3985 GEN_ALU_PC.r_alu_pc[19] ipc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23080 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3987 GEN_ALU_PC.r_alu_pc[18] ipc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23082 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3989 GEN_ALU_PC.r_alu_pc[17] ipc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23084 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3991 GEN_ALU_PC.r_alu_pc[16] ipc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23086 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3993 GEN_ALU_PC.r_alu_pc[15] ipc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23088 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3995 GEN_ALU_PC.r_alu_pc[14] ipc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23090 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3997 GEN_ALU_PC.r_alu_pc[13] ipc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23092 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3999 GEN_ALU_PC.r_alu_pc[12] ipc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23094 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4001 GEN_ALU_PC.r_alu_pc[11] ipc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23096 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4003 GEN_ALU_PC.r_alu_pc[10] ipc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23098 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4005 GEN_ALU_PC.r_alu_pc[9] ipc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23100 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4007 GEN_ALU_PC.r_alu_pc[8] ipc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23102 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4009 GEN_ALU_PC.r_alu_pc[7] ipc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23104 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4011 GEN_ALU_PC.r_alu_pc[6] ipc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23106 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4013 GEN_ALU_PC.r_alu_pc[5] ipc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23108 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4015 GEN_ALU_PC.r_alu_pc[4] ipc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23110 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4017 GEN_ALU_PC.r_alu_pc[3] ipc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23112 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4019 GEN_ALU_PC.r_alu_pc[2] ipc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23114 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[3] OP_REG_ADVANEC.r_op_Bid[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23116 -001 1 -011 1 -110 1 -111 1 -.names dcd_rB $abc$24881$new_n5066 instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n5364 -1100 1 -.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[2] OP_REG_ADVANEC.r_op_Bid[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23118 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[1] OP_REG_ADVANEC.r_op_Bid[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23120 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[0] OP_REG_ADVANEC.r_op_Bid[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23122 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[3] o_mem_reg[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23124 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[2] o_mem_reg[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23126 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[1] o_mem_reg[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23128 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[0] o_mem_reg[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23130 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[3] i_dbg_wreg[3] alu_reg[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23132 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5383 alu_ce o_mem_ce $abc$24881$new_n5373 -000 1 -.names $abc$24881$new_n5375 mem_ce o_mem_ce -11 1 -.names $abc$24881$new_n5378 $abc$24881$new_n5376 r_op_F[2] $abc$24881$new_n5381 $abc$24881$new_n5375 -1100 1 -1111 1 -.names $abc$24881$new_n5377 SET_GIE.r_gie r_op_F[3] $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n5376 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names r_op_F[1] SET_GIE.r_gie r_op_F[5] $abc$24881$new_n4470 $abc$24881$new_n4468 $abc$24881$new_n5377 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10110 1 -11100 1 -11101 1 -.names r_op_F[0] SET_GIE.r_gie r_op_F[4] $abc$24881$new_n5380 $abc$24881$new_n5379 $abc$24881$new_n5378 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10110 1 -11100 1 -11101 1 -.names $abc$24881$new_n4476 $abc$24881$new_n4475 $abc$24881$new_n5379 -00 1 -.names $abc$24881$new_n4400 $abc$24881$new_n4501 flags[0] $abc$24881$new_n5380 -000 1 -010 1 -110 1 -111 1 -.names r_op_F[6] SET_GIE.r_gie $abc$24881$new_n4435 $abc$24881$new_n4438 $abc$24881$new_n5381 -1000 1 -1001 1 -1100 1 -1110 1 -.names op_valid_alu $abc$24881$new_n4031 alu_ce -11 1 -.names op_valid_div $abc$24881$new_n5375 $abc$24881$new_n4031 $abc$24881$new_n5383 -111 1 -.names i_dbg_we o_dbg_stall $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y -10 1 -.names r_halted r_dbg_stall o_dbg_stall -00 1 -01 1 -11 1 -.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[2] i_dbg_wreg[2] alu_reg[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23134 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[1] i_dbg_wreg[1] alu_reg[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23136 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[0] i_dbg_wreg[0] alu_reg[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23138 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 o_mem_op[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[2] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23142 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 o_mem_op[1] dcd_opn[1] instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23146 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$24881$new_n5066 DIVIDE.thedivide.i_signed instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[0] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23150 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[30] $abc$24881$new_n5393 SET_OP_PC.r_op_pc[29] o_mem_lock_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23152 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5394 SET_OP_PC.r_op_pc[28] $abc$24881$new_n5393 -10 1 -.names $abc$24881$new_n5395 SET_OP_PC.r_op_pc[26] SET_OP_PC.r_op_pc[27] $abc$24881$new_n5394 -100 1 -.names $abc$24881$new_n5396 SET_OP_PC.r_op_pc[24] SET_OP_PC.r_op_pc[25] $abc$24881$new_n5395 -100 1 -.names $abc$24881$new_n5397 SET_OP_PC.r_op_pc[22] SET_OP_PC.r_op_pc[23] $abc$24881$new_n5396 -100 1 -.names $abc$24881$new_n5398 SET_OP_PC.r_op_pc[20] SET_OP_PC.r_op_pc[21] $abc$24881$new_n5397 -100 1 -.names $abc$24881$new_n5399 SET_OP_PC.r_op_pc[19] $abc$24881$new_n5398 -10 1 -.names $abc$24881$new_n5400 SET_OP_PC.r_op_pc[17] SET_OP_PC.r_op_pc[18] $abc$24881$new_n5399 -100 1 -.names $abc$24881$new_n5401 SET_OP_PC.r_op_pc[15] SET_OP_PC.r_op_pc[16] $abc$24881$new_n5400 -100 1 -.names $abc$24881$new_n5402 SET_OP_PC.r_op_pc[13] SET_OP_PC.r_op_pc[14] $abc$24881$new_n5401 -100 1 -.names $abc$24881$new_n5403 SET_OP_PC.r_op_pc[11] SET_OP_PC.r_op_pc[12] $abc$24881$new_n5402 -100 1 -.names $abc$24881$new_n5404 SET_OP_PC.r_op_pc[9] SET_OP_PC.r_op_pc[10] $abc$24881$new_n5403 -100 1 -.names $abc$24881$new_n5405 SET_OP_PC.r_op_pc[7] SET_OP_PC.r_op_pc[8] $abc$24881$new_n5404 -100 1 -.names $abc$24881$new_n5406 SET_OP_PC.r_op_pc[5] SET_OP_PC.r_op_pc[6] $abc$24881$new_n5405 -100 1 -.names SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] SET_OP_PC.r_op_pc[4] $abc$24881$new_n5406 -000 1 -.names op_valid GEN_OPLOCK.r_op_lock $abc$24881$new_n5066 $abc$24881$new_n5407 -111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[29] $abc$24881$new_n5393 o_mem_lock_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23154 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[28] $abc$24881$new_n5394 o_mem_lock_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23156 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[27] $abc$24881$new_n5395 SET_OP_PC.r_op_pc[26] o_mem_lock_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23158 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[26] $abc$24881$new_n5395 o_mem_lock_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23160 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[25] $abc$24881$new_n5396 SET_OP_PC.r_op_pc[24] o_mem_lock_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23162 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[24] $abc$24881$new_n5396 o_mem_lock_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23164 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[23] $abc$24881$new_n5397 SET_OP_PC.r_op_pc[22] o_mem_lock_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23166 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[22] $abc$24881$new_n5397 o_mem_lock_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23168 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[21] $abc$24881$new_n5398 SET_OP_PC.r_op_pc[20] o_mem_lock_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23170 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[20] $abc$24881$new_n5398 o_mem_lock_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23172 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[19] $abc$24881$new_n5399 o_mem_lock_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23174 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[18] $abc$24881$new_n5400 SET_OP_PC.r_op_pc[17] o_mem_lock_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23176 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[17] $abc$24881$new_n5400 o_mem_lock_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23178 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[16] $abc$24881$new_n5401 SET_OP_PC.r_op_pc[15] o_mem_lock_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23180 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[15] $abc$24881$new_n5401 o_mem_lock_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23182 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[14] $abc$24881$new_n5402 SET_OP_PC.r_op_pc[13] o_mem_lock_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23184 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[13] $abc$24881$new_n5402 o_mem_lock_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23186 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[12] $abc$24881$new_n5403 SET_OP_PC.r_op_pc[11] o_mem_lock_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23188 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[11] $abc$24881$new_n5403 o_mem_lock_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23190 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[10] $abc$24881$new_n5404 SET_OP_PC.r_op_pc[9] o_mem_lock_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23192 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[9] $abc$24881$new_n5404 o_mem_lock_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23194 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[8] $abc$24881$new_n5405 SET_OP_PC.r_op_pc[7] o_mem_lock_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23196 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[7] $abc$24881$new_n5405 o_mem_lock_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23198 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[6] $abc$24881$new_n5406 SET_OP_PC.r_op_pc[5] o_mem_lock_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23200 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[5] $abc$24881$new_n5406 o_mem_lock_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23202 -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[4] SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] o_mem_lock_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23204 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] o_mem_lock_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23206 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[2] o_mem_lock_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23208 -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[1] o_mem_lock_pc[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23210 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5438 $abc$24881$new_n4028 dcd_I[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23212 -000 1 -001 1 -011 1 -.names $abc$24881$new_n5443 $abc$24881$new_n5439 $abc$24881$new_n4028 $abc$24881$new_n5438 -000 1 -.names $abc$24881$new_n4266 $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4289 $abc$24881$new_n5439 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names $abc$24881$new_n5441 $abc$24881$new_n4283 $abc$24881$new_n4281 $abc$24881$new_n4271 $abc$24881$new_n5442 $abc$24881$new_n5440 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4281 i_pf_instruction[12] i_pf_instruction[13] $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5441 -00100 1 -01100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[1] i_pf_instruction[17] $abc$24881$new_n5442 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4273 $abc$24881$new_n4266 $abc$24881$new_n4272 $abc$24881$new_n4283 $abc$24881$new_n4287 $abc$24881$new_n5443 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10010 1 -.names $abc$24881$new_n4028 dcd_I[20] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5445 $abc$24881$auto$rtlil.cc:2693:MuxGate$23214 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4291 $abc$24881$new_n5445 -100 1 -101 1 -110 1 -.names $abc$24881$new_n4028 dcd_I[19] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5447 $abc$24881$auto$rtlil.cc:2693:MuxGate$23216 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4293 $abc$24881$new_n5447 -100 1 -101 1 -111 1 -.names $abc$24881$new_n4028 dcd_I[18] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5449 $abc$24881$auto$rtlil.cc:2693:MuxGate$23218 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5449 -100 1 -101 1 -111 1 -.names $abc$24881$new_n4028 dcd_I[17] $abc$24881$new_n5451 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23220 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n5441 i_pf_instruction[17] $abc$24881$new_n5452 $abc$24881$new_n5451 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4281 $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5452 -001 1 -010 1 -011 1 -.names $abc$24881$new_n4028 dcd_I[16] $abc$24881$new_n5454 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23222 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n5441 $abc$24881$new_n5452 $abc$24881$new_n5455 $abc$24881$new_n5454 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[0] i_pf_instruction[16] $abc$24881$new_n5455 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4028 dcd_I[15] $abc$24881$new_n5457 $abc$24881$new_n4266 $abc$24881$new_n5441 $abc$24881$auto$rtlil.cc:2693:MuxGate$23224 -00000 1 -00001 1 -00010 1 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5452 i_pf_instruction[15] $abc$24881$new_n5457 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -.names $abc$24881$new_n4028 dcd_I[14] $abc$24881$new_n5459 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23226 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n5441 i_pf_instruction[14] $abc$24881$new_n5452 $abc$24881$new_n5459 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4028 dcd_I[13] $abc$24881$new_n5443 $abc$24881$new_n5461 $abc$24881$auto$rtlil.cc:2693:MuxGate$23228 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n4281 i_pf_instruction[12] i_pf_instruction[13] $abc$24881$new_n5461 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4028 dcd_I[12] $abc$24881$new_n5443 i_pf_instruction[12] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23230 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 dcd_I[11] $abc$24881$new_n5443 i_pf_instruction[11] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23232 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 dcd_I[10] $abc$24881$new_n5443 i_pf_instruction[10] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23234 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 dcd_I[9] $abc$24881$new_n5443 i_pf_instruction[9] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23236 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 dcd_I[8] $abc$24881$new_n5443 i_pf_instruction[8] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23238 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 dcd_I[7] $abc$24881$new_n5443 i_pf_instruction[7] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23240 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 dcd_I[6] $abc$24881$new_n5469 $abc$24881$auto$rtlil.cc:2693:MuxGate$23242 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[6] $abc$24881$new_n4283 $abc$24881$new_n4287 $abc$24881$new_n5469 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4273 $abc$24881$new_n4272 $abc$24881$new_n5470 -00 1 -.names $abc$24881$new_n4028 dcd_I[5] $abc$24881$new_n5472 $abc$24881$auto$rtlil.cc:2693:MuxGate$23244 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[5] $abc$24881$new_n4283 $abc$24881$new_n4289 $abc$24881$new_n5472 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 dcd_I[4] $abc$24881$new_n5474 $abc$24881$auto$rtlil.cc:2693:MuxGate$23246 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[4] $abc$24881$new_n4283 $abc$24881$new_n4291 $abc$24881$new_n5474 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4028 dcd_I[3] $abc$24881$new_n5476 $abc$24881$auto$rtlil.cc:2693:MuxGate$23248 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n5477 $abc$24881$new_n5470 $abc$24881$new_n4283 $abc$24881$new_n4266 $abc$24881$new_n5476 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4266 i_pf_instruction[3] $abc$24881$new_n5470 $abc$24881$new_n4293 $abc$24881$new_n5477 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[2] i_pf_instruction[2] $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$23250 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[1] i_pf_instruction[1] $abc$24881$new_n5442 $abc$24881$auto$rtlil.cc:2693:MuxGate$23252 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[0] i_pf_instruction[0] $abc$24881$new_n5455 $abc$24881$auto$rtlil.cc:2693:MuxGate$23254 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names BUSLOCK.r_bus_lock[0] $abc$24881$new_n4030 BUSLOCK.r_bus_lock[1] GEN_OPLOCK.r_op_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23256 -0001 1 -0010 1 -0011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[30] SET_OP_PC.r_op_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23258 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[29] SET_OP_PC.r_op_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23260 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[28] SET_OP_PC.r_op_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23262 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[27] SET_OP_PC.r_op_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23264 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[26] SET_OP_PC.r_op_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23266 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[25] SET_OP_PC.r_op_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23268 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[24] SET_OP_PC.r_op_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23270 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[23] SET_OP_PC.r_op_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23272 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[22] SET_OP_PC.r_op_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23274 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[21] SET_OP_PC.r_op_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23276 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[20] SET_OP_PC.r_op_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23278 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[19] SET_OP_PC.r_op_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23280 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[18] SET_OP_PC.r_op_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23282 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[17] SET_OP_PC.r_op_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23284 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[16] SET_OP_PC.r_op_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23286 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[15] SET_OP_PC.r_op_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23288 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[14] SET_OP_PC.r_op_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23290 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[13] SET_OP_PC.r_op_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23292 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[12] SET_OP_PC.r_op_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23294 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[11] SET_OP_PC.r_op_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23296 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[10] SET_OP_PC.r_op_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23298 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[9] SET_OP_PC.r_op_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23300 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[8] SET_OP_PC.r_op_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23302 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[7] SET_OP_PC.r_op_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23304 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[6] SET_OP_PC.r_op_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23306 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[5] SET_OP_PC.r_op_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23308 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[4] SET_OP_PC.r_op_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23310 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[3] SET_OP_PC.r_op_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23312 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[2] SET_OP_PC.r_op_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23314 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n5529 $abc$24881$new_n5512 o_mem_addr[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23318 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5513 DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_divisor[28] $abc$24881$new_n5512 -100 1 -.names $abc$24881$new_n5514 DIVIDE.thedivide.r_divisor[26] $abc$24881$new_n5513 -10 1 -.names $abc$24881$new_n5515 DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n5514 -100 1 -.names $abc$24881$new_n5516 DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n5515 -100 1 -.names $abc$24881$new_n5517 DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n5516 -100 1 -.names $abc$24881$new_n5518 DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n5517 -100 1 -.names $abc$24881$new_n5519 DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n5518 -10 1 -.names $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_divisor[16] $abc$24881$new_n5519 -1000 1 -.names $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n5520 -10000 1 -.names $abc$24881$new_n5522 DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n5521 -10 1 -.names $abc$24881$new_n5523 DIVIDE.thedivide.r_divisor[8] $abc$24881$new_n5522 -10 1 -.names $abc$24881$new_n5524 DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n5523 -10 1 -.names $abc$24881$new_n5525 DIVIDE.thedivide.r_divisor[6] $abc$24881$new_n5524 -10 1 -.names $abc$24881$new_n5526 DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n5525 -10 1 -.names $abc$24881$new_n5527 DIVIDE.thedivide.r_divisor[4] $abc$24881$new_n5526 -10 1 -.names $abc$24881$new_n5528 DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5527 -100 1 -.names DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n5528 -00 1 -.names DIVIDE.thedivide.r_busy $abc$24881$new_n5530 $abc$24881$new_n5529 -10 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n5530 -11 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy $abc$24881$new_n5531 -11 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5533 DIVIDE.thedivide.r_divisor[28] o_mem_addr[28] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23320 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[28] $abc$24881$new_n5513 DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n5533 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n5529 $abc$24881$new_n5513 o_mem_addr[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23322 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[26] $abc$24881$new_n5529 $abc$24881$new_n5514 o_mem_addr[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23324 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3725 r_op_Bv[26] o_mem_addr[26] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5540 DIVIDE.thedivide.r_divisor[25] o_mem_addr[25] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23326 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n5515 DIVIDE.thedivide.r_divisor[24] $abc$24881$new_n5540 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3730 r_op_Bv[25] o_mem_addr[25] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[24] $abc$24881$new_n5529 $abc$24881$new_n5515 o_mem_addr[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23328 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5545 DIVIDE.thedivide.r_divisor[23] o_mem_addr[23] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23330 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n5516 DIVIDE.thedivide.r_divisor[22] $abc$24881$new_n5545 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3741 r_op_Bv[23] o_mem_addr[23] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[22] $abc$24881$new_n5529 $abc$24881$new_n5516 o_mem_addr[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23332 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5550 DIVIDE.thedivide.r_divisor[21] o_mem_addr[21] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23334 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n5517 DIVIDE.thedivide.r_divisor[20] $abc$24881$new_n5550 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3752 r_op_Bv[21] o_mem_addr[21] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[20] $abc$24881$new_n5529 $abc$24881$new_n5517 o_mem_addr[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23336 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5555 DIVIDE.thedivide.r_divisor[19] o_mem_addr[19] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23338 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n5518 DIVIDE.thedivide.r_divisor[18] $abc$24881$new_n5555 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[18] $abc$24881$new_n5529 $abc$24881$new_n5518 o_mem_addr[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23340 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n5529 $abc$24881$new_n5519 o_mem_addr[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23342 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3774 r_op_Bv[17] o_mem_addr[17] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5560 DIVIDE.thedivide.r_divisor[16] o_mem_addr[16] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23344 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[16] $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n5560 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5562 DIVIDE.thedivide.r_divisor[15] o_mem_addr[15] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23346 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] $abc$24881$new_n5562 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3784 r_op_Bv[15] o_mem_addr[15] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[14] $abc$24881$new_n5529 $abc$24881$new_n5520 o_mem_addr[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23348 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy $abc$24881$new_n5529 DIVIDE.thedivide.r_divisor[13] o_mem_addr[13] $abc$24881$new_n5568 $abc$24881$auto$rtlil.cc:2693:MuxGate$23350 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] $abc$24881$new_n5568 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3795 r_op_Bv[13] o_mem_addr[13] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5571 DIVIDE.thedivide.r_divisor[12] o_mem_addr[12] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23352 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[12] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n5571 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5529 $abc$24881$new_n5573 DIVIDE.thedivide.r_divisor[11] o_mem_addr[11] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23354 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] $abc$24881$new_n5573 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3805 r_op_Bv[11] o_mem_addr[11] -001 1 -011 1 -100 1 -101 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[10] $abc$24881$new_n5521 $abc$24881$new_n5529 o_mem_addr[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23356 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n5530 $abc$24881$new_n5522 o_mem_addr[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23358 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[8] $abc$24881$new_n5530 $abc$24881$new_n5523 o_mem_addr[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23360 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3820 r_op_Bv[8] o_mem_addr[8] -001 1 -011 1 -100 1 -101 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n5530 $abc$24881$new_n5524 o_mem_addr[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23362 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3825 r_op_Bv[7] o_mem_addr[7] -001 1 -011 1 -100 1 -101 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[6] $abc$24881$new_n5529 $abc$24881$new_n5525 o_mem_addr[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23364 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3832 r_op_Bv[6] o_mem_addr[6] -001 1 -011 1 -100 1 -101 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n5530 $abc$24881$new_n5526 o_mem_addr[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23366 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3838 r_op_Bv[5] o_mem_addr[5] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[4] $abc$24881$new_n5529 $abc$24881$new_n5527 o_mem_addr[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23368 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5529 DIVIDE.thedivide.r_busy o_mem_addr[3] DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5588 $abc$24881$auto$rtlil.cc:2693:MuxGate$23370 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5528 DIVIDE.thedivide.r_divisor[2] $abc$24881$new_n5588 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[2] $abc$24881$new_n5529 $abc$24881$new_n5528 o_mem_addr[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23372 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3853 r_op_Bv[2] o_mem_addr[2] -001 1 -011 1 -100 1 -101 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_divisor[0] $abc$24881$new_n5530 o_mem_addr[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23374 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names DIVIDE.thedivide.r_busy o_mem_addr[0] DIVIDE.thedivide.r_divisor[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23376 -010 1 -011 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n5595 -10 1 -.names $abc$24881$new_n5599 $abc$24881$new_n5597 instruction_decoder.o_dcdA[0] $abc$24881$new_n3697 $abc$24881$new_n5066 $abc$24881$new_n5596 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11111 1 -.names $abc$24881$new_n5598 instruction_decoder.o_dcdA[3] $abc$24881$new_n3695 $abc$24881$new_n3959 $abc$24881$new_n5597 -1010 1 -1100 1 -.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[2] $abc$24881$new_n3701 $abc$24881$new_n3694 $abc$24881$new_n5598 -0011 1 -0101 1 -1010 1 -1100 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n3698 $abc$24881$new_n5599 -01 1 -10 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[30] SET_USER_PC.r_upc[30] $abc$24881$new_n5601 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n5603 $abc$24881$new_n5613 $abc$24881$new_n5618 $abc$24881$new_n5602 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5604 $abc$24881$new_n5611 $abc$24881$new_n5609 $abc$24881$new_n5603 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5605 $abc$24881$new_n5608 $abc$24881$new_n5607 $abc$24881$new_n5604 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$24881$new_n5606 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][30] regset[18][30] $abc$24881$new_n5605 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][30] regset[19][30] $abc$24881$new_n5606 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][30] regset[26][30] $abc$24881$new_n5607 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][30] regset[27][30] $abc$24881$new_n5608 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n5610 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[21][30] regset[17][30] $abc$24881$new_n5609 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][30] regset[16][30] $abc$24881$new_n5610 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n5612 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][30] regset[24][30] $abc$24881$new_n5611 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][30] regset[25][30] $abc$24881$new_n5612 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5614 $abc$24881$new_n5616 $abc$24881$new_n5613 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5615 regset[13][30] regset[9][30] $abc$24881$new_n5614 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][30] regset[8][30] $abc$24881$new_n5615 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5617 regset[4][30] regset[0][30] $abc$24881$new_n5616 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[2] regset[5][30] regset[1][30] $abc$24881$new_n5617 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5620 $abc$24881$new_n5619 $abc$24881$new_n5622 $abc$24881$new_n5621 $abc$24881$new_n5618 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[14][30] regset[6][30] $abc$24881$new_n5619 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[10][30] regset[2][30] $abc$24881$new_n5620 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[15][30] regset[7][30] $abc$24881$new_n5621 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[11][30] regset[3][30] $abc$24881$new_n5622 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$24881$new_n5066 $abc$24881$new_n3692 OP_REG_ADVANEC.r_op_rA $abc$24881$new_n5623 -000 1 -001 1 -010 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5629 $abc$24881$new_n5631 $abc$24881$new_n5633 $abc$24881$new_n5628 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5630 regset[5][29] regset[1][29] $abc$24881$new_n5629 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[4][29] regset[0][29] $abc$24881$new_n5630 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5632 regset[15][29] regset[11][29] $abc$24881$new_n5631 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][29] regset[10][29] $abc$24881$new_n5632 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5634 regset[7][29] regset[3][29] $abc$24881$new_n5633 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[6][29] regset[2][29] $abc$24881$new_n5634 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5636 regset[13][29] regset[9][29] $abc$24881$new_n5635 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][29] regset[8][29] $abc$24881$new_n5636 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5637 -10 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5640 $abc$24881$new_n5642 $abc$24881$new_n5644 $abc$24881$new_n5639 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5641 regset[31][29] regset[27][29] $abc$24881$new_n5640 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[30][29] regset[26][29] $abc$24881$new_n5641 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5643 regset[21][29] regset[17][29] $abc$24881$new_n5642 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[20][29] regset[16][29] $abc$24881$new_n5643 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5645 regset[23][29] regset[19][29] $abc$24881$new_n5644 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[22][29] regset[18][29] $abc$24881$new_n5645 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5647 regset[29][29] regset[25][29] $abc$24881$new_n5646 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[28][29] regset[24][29] $abc$24881$new_n5647 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5660 $abc$24881$new_n5653 $abc$24881$new_n5658 instruction_decoder.o_dcdA[3] $abc$24881$new_n5652 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5654 $abc$24881$new_n5656 $abc$24881$new_n5653 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5655 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[23][28] regset[19][28] $abc$24881$new_n5654 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[31][28] regset[27][28] $abc$24881$new_n5655 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$24881$new_n5657 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[22][28] regset[18][28] $abc$24881$new_n5656 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[30][28] regset[26][28] $abc$24881$new_n5657 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5659 regset[21][28] regset[17][28] $abc$24881$new_n5658 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[20][28] regset[16][28] $abc$24881$new_n5659 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5661 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][28] regset[24][28] $abc$24881$new_n5660 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][28] regset[25][28] $abc$24881$new_n5661 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5663 $abc$24881$new_n5670 $abc$24881$new_n5668 $abc$24881$new_n5662 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5664 $abc$24881$new_n5666 $abc$24881$new_n5663 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5665 regset[13][28] regset[9][28] $abc$24881$new_n5664 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][28] regset[8][28] $abc$24881$new_n5665 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5667 regset[4][28] regset[0][28] $abc$24881$new_n5666 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[2] regset[5][28] regset[1][28] $abc$24881$new_n5667 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5669 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][28] regset[2][28] $abc$24881$new_n5668 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[7][28] regset[3][28] $abc$24881$new_n5669 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$24881$new_n5671 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[14][28] regset[10][28] $abc$24881$new_n5670 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[15][28] regset[11][28] $abc$24881$new_n5671 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names dcd_Apc $abc$24881$new_n5596 $abc$24881$new_n5672 -11 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5679 $abc$24881$new_n5686 $abc$24881$new_n5684 $abc$24881$new_n5678 -0000 1 -0100 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[0] $abc$24881$new_n5680 $abc$24881$new_n5682 $abc$24881$new_n5683 $abc$24881$new_n5679 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$24881$new_n5681 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][27] regset[24][27] $abc$24881$new_n5680 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][27] regset[25][27] $abc$24881$new_n5681 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[2] regset[31][27] regset[27][27] $abc$24881$new_n5682 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[2] regset[30][27] regset[26][27] $abc$24881$new_n5683 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5685 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[18][27] regset[16][27] $abc$24881$new_n5684 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[22][27] regset[20][27] $abc$24881$new_n5685 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$24881$new_n5687 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[19][27] regset[17][27] $abc$24881$new_n5686 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[23][27] regset[21][27] $abc$24881$new_n5687 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5690 regset[15][27] regset[11][27] $abc$24881$new_n5689 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][27] regset[10][27] $abc$24881$new_n5690 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5692 regset[13][27] regset[9][27] $abc$24881$new_n5691 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][27] regset[8][27] $abc$24881$new_n5692 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5695 regset[5][27] regset[1][27] $abc$24881$new_n5694 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][27] regset[0][27] $abc$24881$new_n5695 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5698 regset[7][27] regset[3][27] $abc$24881$new_n5697 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[6][27] regset[2][27] $abc$24881$new_n5698 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5709 $abc$24881$new_n5704 $abc$24881$new_n5711 instruction_decoder.o_dcdA[1] $abc$24881$new_n5703 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5705 $abc$24881$new_n5708 $abc$24881$new_n5707 $abc$24881$new_n5704 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5706 regset[5][26] regset[1][26] $abc$24881$new_n5705 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][26] regset[0][26] $abc$24881$new_n5706 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][26] regset[2][26] $abc$24881$new_n5707 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][26] regset[3][26] $abc$24881$new_n5708 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n5710 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][26] regset[9][26] $abc$24881$new_n5709 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][26] regset[8][26] $abc$24881$new_n5710 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5712 regset[15][26] regset[11][26] $abc$24881$new_n5711 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][26] regset[10][26] $abc$24881$new_n5712 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5714 $abc$24881$new_n5719 $abc$24881$new_n5721 $abc$24881$new_n5713 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5715 $abc$24881$new_n5717 $abc$24881$new_n5714 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5716 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][26] regset[26][26] $abc$24881$new_n5715 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][26] regset[27][26] $abc$24881$new_n5716 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5718 regset[29][26] regset[25][26] $abc$24881$new_n5717 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][26] regset[24][26] $abc$24881$new_n5718 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5720 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][26] regset[18][26] $abc$24881$new_n5719 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][26] regset[19][26] $abc$24881$new_n5720 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5722 regset[21][26] regset[17][26] $abc$24881$new_n5721 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][26] regset[16][26] $abc$24881$new_n5722 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5725 r_op_Av[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23388 -010 1 -011 1 -101 1 -111 1 -.names $abc$24881$new_n5726 $abc$24881$new_n5672 $abc$24881$new_n5595 $abc$24881$new_n5747 $abc$24881$new_n3730 $abc$24881$new_n5725 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n5595 instruction_decoder.o_dcdA[1] dcd_Acc $abc$24881$new_n5727 $abc$24881$new_n5737 $abc$24881$new_n5726 -10001 1 -10011 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] $abc$24881$new_n5728 $abc$24881$new_n5733 $abc$24881$new_n5735 $abc$24881$new_n5727 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5730 $abc$24881$new_n5729 $abc$24881$new_n5732 $abc$24881$new_n5731 $abc$24881$new_n5728 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][25] regset[19][25] $abc$24881$new_n5729 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][25] regset[18][25] $abc$24881$new_n5730 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][25] regset[27][25] $abc$24881$new_n5731 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][25] regset[26][25] $abc$24881$new_n5732 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5734 regset[15][25] regset[11][25] $abc$24881$new_n5733 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][25] regset[10][25] $abc$24881$new_n5734 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5736 regset[6][25] regset[2][25] $abc$24881$new_n5735 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[7][25] regset[3][25] $abc$24881$new_n5736 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] $abc$24881$new_n5738 $abc$24881$new_n5743 $abc$24881$new_n5745 $abc$24881$new_n5737 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5740 $abc$24881$new_n5739 $abc$24881$new_n5742 $abc$24881$new_n5741 $abc$24881$new_n5738 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[21][25] regset[17][25] $abc$24881$new_n5739 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][25] regset[16][25] $abc$24881$new_n5740 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][25] regset[25][25] $abc$24881$new_n5741 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][25] regset[24][25] $abc$24881$new_n5742 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5744 regset[12][25] regset[8][25] $abc$24881$new_n5743 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[13][25] regset[9][25] $abc$24881$new_n5744 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5746 regset[4][25] regset[0][25] $abc$24881$new_n5745 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[5][25] regset[1][25] $abc$24881$new_n5746 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[25] SET_USER_PC.r_upc[25] $abc$24881$new_n5747 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5753 $abc$24881$new_n5755 $abc$24881$new_n5757 $abc$24881$new_n5752 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5754 regset[21][24] regset[17][24] $abc$24881$new_n5753 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[20][24] regset[16][24] $abc$24881$new_n5754 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5756 regset[31][24] regset[27][24] $abc$24881$new_n5755 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[30][24] regset[26][24] $abc$24881$new_n5756 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5758 regset[23][24] regset[19][24] $abc$24881$new_n5757 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[22][24] regset[18][24] $abc$24881$new_n5758 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5760 regset[29][24] regset[25][24] $abc$24881$new_n5759 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[28][24] regset[24][24] $abc$24881$new_n5760 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5763 $abc$24881$new_n5765 $abc$24881$new_n5767 $abc$24881$new_n5762 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5764 regset[5][24] regset[1][24] $abc$24881$new_n5763 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[4][24] regset[0][24] $abc$24881$new_n5764 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5766 regset[15][24] regset[11][24] $abc$24881$new_n5765 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][24] regset[10][24] $abc$24881$new_n5766 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5768 regset[7][24] regset[3][24] $abc$24881$new_n5767 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[6][24] regset[2][24] $abc$24881$new_n5768 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5770 regset[13][24] regset[9][24] $abc$24881$new_n5769 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][24] regset[8][24] $abc$24881$new_n5770 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n9598 r_op_Av[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23392 -000 1 -001 1 -101 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5777 $abc$24881$new_n5779 $abc$24881$new_n5781 $abc$24881$new_n5776 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5778 regset[15][23] regset[11][23] $abc$24881$new_n5777 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][23] regset[10][23] $abc$24881$new_n5778 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5780 regset[13][23] regset[9][23] $abc$24881$new_n5779 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][23] regset[8][23] $abc$24881$new_n5780 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5782 regset[7][23] regset[3][23] $abc$24881$new_n5781 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[6][23] regset[2][23] $abc$24881$new_n5782 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5784 regset[5][23] regset[1][23] $abc$24881$new_n5783 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[4][23] regset[0][23] $abc$24881$new_n5784 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5787 $abc$24881$new_n5789 $abc$24881$new_n5791 $abc$24881$new_n5786 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5788 regset[31][23] regset[27][23] $abc$24881$new_n5787 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[30][23] regset[26][23] $abc$24881$new_n5788 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5790 regset[29][23] regset[25][23] $abc$24881$new_n5789 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[28][23] regset[24][23] $abc$24881$new_n5790 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5792 regset[21][23] regset[17][23] $abc$24881$new_n5791 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[20][23] regset[16][23] $abc$24881$new_n5792 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5794 regset[23][23] regset[19][23] $abc$24881$new_n5793 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[22][23] regset[18][23] $abc$24881$new_n5794 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[23] SET_USER_PC.r_upc[23] $abc$24881$new_n5795 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5800 $abc$24881$new_n5805 $abc$24881$new_n5807 $abc$24881$new_n5799 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5801 $abc$24881$new_n5803 $abc$24881$new_n5800 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5802 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][22] regset[26][22] $abc$24881$new_n5801 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][22] regset[27][22] $abc$24881$new_n5802 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5804 regset[29][22] regset[25][22] $abc$24881$new_n5803 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][22] regset[24][22] $abc$24881$new_n5804 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5806 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][22] regset[18][22] $abc$24881$new_n5805 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][22] regset[19][22] $abc$24881$new_n5806 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5808 regset[21][22] regset[17][22] $abc$24881$new_n5807 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][22] regset[16][22] $abc$24881$new_n5808 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5810 $abc$24881$new_n5813 $abc$24881$new_n5812 $abc$24881$new_n5809 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5811 regset[5][22] regset[1][22] $abc$24881$new_n5810 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][22] regset[0][22] $abc$24881$new_n5811 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][22] regset[2][22] $abc$24881$new_n5812 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][22] regset[3][22] $abc$24881$new_n5813 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5816 regset[15][22] regset[14][22] $abc$24881$new_n5815 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[11][22] regset[10][22] $abc$24881$new_n5816 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5818 regset[13][22] regset[12][22] $abc$24881$new_n5817 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[9][22] regset[8][22] $abc$24881$new_n5818 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[22] SET_USER_PC.r_upc[22] $abc$24881$new_n5819 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5823 $abc$24881$new_n5828 $abc$24881$new_n5830 $abc$24881$new_n5822 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5824 $abc$24881$new_n5827 $abc$24881$new_n5826 $abc$24881$new_n5823 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5825 regset[29][21] regset[25][21] $abc$24881$new_n5824 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][21] regset[24][21] $abc$24881$new_n5825 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][21] regset[27][21] $abc$24881$new_n5826 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][21] regset[26][21] $abc$24881$new_n5827 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5829 regset[23][21] regset[19][21] $abc$24881$new_n5828 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][21] regset[18][21] $abc$24881$new_n5829 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5831 regset[21][21] regset[17][21] $abc$24881$new_n5830 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][21] regset[16][21] $abc$24881$new_n5831 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5833 $abc$24881$new_n5838 $abc$24881$new_n5637 $abc$24881$new_n5840 $abc$24881$new_n5832 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10011 1 -11000 1 -11001 1 -11011 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5834 $abc$24881$new_n5837 $abc$24881$new_n5836 $abc$24881$new_n5833 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5835 regset[5][21] regset[1][21] $abc$24881$new_n5834 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][21] regset[0][21] $abc$24881$new_n5835 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][21] regset[2][21] $abc$24881$new_n5836 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][21] regset[3][21] $abc$24881$new_n5837 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n5839 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[15][21] regset[11][21] $abc$24881$new_n5838 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[14][21] regset[10][21] $abc$24881$new_n5839 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5841 regset[13][21] regset[9][21] $abc$24881$new_n5840 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][21] regset[8][21] $abc$24881$new_n5841 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[21] SET_USER_PC.r_upc[21] $abc$24881$new_n5843 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5848 $abc$24881$new_n5853 $abc$24881$new_n5855 $abc$24881$new_n5847 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5849 $abc$24881$new_n5852 $abc$24881$new_n5851 $abc$24881$new_n5848 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5850 regset[5][20] regset[1][20] $abc$24881$new_n5849 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][20] regset[0][20] $abc$24881$new_n5850 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][20] regset[2][20] $abc$24881$new_n5851 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][20] regset[3][20] $abc$24881$new_n5852 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5854 regset[13][20] regset[9][20] $abc$24881$new_n5853 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][20] regset[8][20] $abc$24881$new_n5854 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5856 regset[15][20] regset[11][20] $abc$24881$new_n5855 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][20] regset[10][20] $abc$24881$new_n5856 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5858 $abc$24881$new_n5863 $abc$24881$new_n5865 $abc$24881$new_n5857 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5859 $abc$24881$new_n5861 $abc$24881$new_n5858 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5860 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][20] regset[26][20] $abc$24881$new_n5859 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][20] regset[27][20] $abc$24881$new_n5860 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5862 regset[29][20] regset[25][20] $abc$24881$new_n5861 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][20] regset[24][20] $abc$24881$new_n5862 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5864 regset[23][20] regset[19][20] $abc$24881$new_n5863 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][20] regset[18][20] $abc$24881$new_n5864 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5866 regset[21][20] regset[17][20] $abc$24881$new_n5865 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][20] regset[16][20] $abc$24881$new_n5866 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5869 r_op_Av[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23400 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3763 $abc$24881$new_n5870 $abc$24881$new_n5891 $abc$24881$new_n5869 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n5871 $abc$24881$new_n5881 $abc$24881$new_n5886 $abc$24881$new_n5870 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5872 $abc$24881$new_n5877 $abc$24881$new_n5879 instruction_decoder.o_dcdA[3] $abc$24881$new_n5871 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5875 $abc$24881$new_n5873 instruction_decoder.o_dcdA[3] $abc$24881$new_n5872 -010 1 -100 1 -101 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5874 regset[20][19] regset[16][19] $abc$24881$new_n5873 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[2] regset[21][19] regset[17][19] $abc$24881$new_n5874 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5876 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][19] regset[24][19] $abc$24881$new_n5875 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][19] regset[25][19] $abc$24881$new_n5876 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n5878 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][19] regset[26][19] $abc$24881$new_n5877 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[31][19] regset[27][19] $abc$24881$new_n5878 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5880 regset[22][19] regset[18][19] $abc$24881$new_n5879 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[2] regset[23][19] regset[19][19] $abc$24881$new_n5880 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5884 $abc$24881$new_n5882 instruction_decoder.o_dcdA[3] $abc$24881$new_n5881 -010 1 -100 1 -101 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5883 regset[4][19] regset[0][19] $abc$24881$new_n5882 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[2] regset[5][19] regset[1][19] $abc$24881$new_n5883 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5885 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][19] regset[8][19] $abc$24881$new_n5884 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][19] regset[9][19] $abc$24881$new_n5885 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5888 $abc$24881$new_n5887 $abc$24881$new_n5890 $abc$24881$new_n5889 $abc$24881$new_n5886 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[14][19] regset[10][19] $abc$24881$new_n5887 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[6][19] regset[2][19] $abc$24881$new_n5888 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[15][19] regset[11][19] $abc$24881$new_n5889 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[7][19] regset[3][19] $abc$24881$new_n5890 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[19] SET_USER_PC.r_upc[19] $abc$24881$new_n5891 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5896 $abc$24881$new_n5901 $abc$24881$new_n5903 $abc$24881$new_n5895 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5897 $abc$24881$new_n5899 $abc$24881$new_n5896 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5898 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][18] regset[26][18] $abc$24881$new_n5897 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][18] regset[27][18] $abc$24881$new_n5898 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5900 regset[29][18] regset[25][18] $abc$24881$new_n5899 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][18] regset[24][18] $abc$24881$new_n5900 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5902 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][18] regset[18][18] $abc$24881$new_n5901 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][18] regset[19][18] $abc$24881$new_n5902 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5904 regset[21][18] regset[17][18] $abc$24881$new_n5903 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][18] regset[16][18] $abc$24881$new_n5904 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5906 $abc$24881$new_n5909 $abc$24881$new_n5908 $abc$24881$new_n5905 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5907 regset[5][18] regset[1][18] $abc$24881$new_n5906 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][18] regset[0][18] $abc$24881$new_n5907 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][18] regset[2][18] $abc$24881$new_n5908 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][18] regset[3][18] $abc$24881$new_n5909 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5912 regset[13][18] regset[12][18] $abc$24881$new_n5911 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[9][18] regset[8][18] $abc$24881$new_n5912 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5914 regset[15][18] regset[14][18] $abc$24881$new_n5913 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[11][18] regset[10][18] $abc$24881$new_n5914 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[18] SET_USER_PC.r_upc[18] $abc$24881$new_n5915 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5917 r_op_Av[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23404 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3774 $abc$24881$new_n5918 $abc$24881$new_n5939 $abc$24881$new_n5917 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[4] $abc$24881$new_n5934 $abc$24881$new_n5919 $abc$24881$new_n5929 instruction_decoder.o_dcdA[3] $abc$24881$new_n5918 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5920 $abc$24881$new_n5925 $abc$24881$new_n5927 $abc$24881$new_n5919 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5921 $abc$24881$new_n5923 $abc$24881$new_n5920 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5922 regset[23][17] regset[19][17] $abc$24881$new_n5921 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[22][17] regset[18][17] $abc$24881$new_n5922 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5924 regset[21][17] regset[17][17] $abc$24881$new_n5923 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[20][17] regset[16][17] $abc$24881$new_n5924 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5926 regset[30][17] regset[26][17] $abc$24881$new_n5925 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[31][17] regset[27][17] $abc$24881$new_n5926 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5928 regset[29][17] regset[25][17] $abc$24881$new_n5927 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[28][17] regset[24][17] $abc$24881$new_n5928 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5930 $abc$24881$new_n5933 $abc$24881$new_n5932 $abc$24881$new_n5929 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5931 regset[5][17] regset[1][17] $abc$24881$new_n5930 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][17] regset[0][17] $abc$24881$new_n5931 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][17] regset[2][17] $abc$24881$new_n5932 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][17] regset[3][17] $abc$24881$new_n5933 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5935 $abc$24881$new_n5938 $abc$24881$new_n5937 $abc$24881$new_n5934 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5936 regset[15][17] regset[11][17] $abc$24881$new_n5935 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][17] regset[10][17] $abc$24881$new_n5936 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[13][17] regset[9][17] $abc$24881$new_n5937 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][17] regset[8][17] $abc$24881$new_n5938 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[17] SET_USER_PC.r_upc[17] $abc$24881$new_n5939 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5944 $abc$24881$new_n5949 $abc$24881$new_n5951 $abc$24881$new_n5943 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5945 $abc$24881$new_n5947 $abc$24881$new_n5944 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5946 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][16] regset[26][16] $abc$24881$new_n5945 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][16] regset[27][16] $abc$24881$new_n5946 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5948 regset[29][16] regset[25][16] $abc$24881$new_n5947 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][16] regset[24][16] $abc$24881$new_n5948 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5950 regset[23][16] regset[19][16] $abc$24881$new_n5949 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][16] regset[18][16] $abc$24881$new_n5950 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5952 regset[21][16] regset[17][16] $abc$24881$new_n5951 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][16] regset[16][16] $abc$24881$new_n5952 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5954 $abc$24881$new_n5957 $abc$24881$new_n5956 $abc$24881$new_n5953 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5955 regset[5][16] regset[1][16] $abc$24881$new_n5954 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][16] regset[0][16] $abc$24881$new_n5955 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][16] regset[2][16] $abc$24881$new_n5956 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][16] regset[3][16] $abc$24881$new_n5957 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5960 regset[15][16] regset[11][16] $abc$24881$new_n5959 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][16] regset[10][16] $abc$24881$new_n5960 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5962 regset[13][16] regset[9][16] $abc$24881$new_n5961 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][16] regset[8][16] $abc$24881$new_n5962 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[16] SET_USER_PC.r_upc[16] $abc$24881$new_n5963 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5968 $abc$24881$new_n5973 $abc$24881$new_n5975 $abc$24881$new_n5967 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5969 $abc$24881$new_n5971 $abc$24881$new_n5968 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5970 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][15] regset[26][15] $abc$24881$new_n5969 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][15] regset[27][15] $abc$24881$new_n5970 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5972 regset[29][15] regset[25][15] $abc$24881$new_n5971 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][15] regset[24][15] $abc$24881$new_n5972 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5974 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][15] regset[18][15] $abc$24881$new_n5973 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][15] regset[19][15] $abc$24881$new_n5974 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5976 regset[21][15] regset[17][15] $abc$24881$new_n5975 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][15] regset[16][15] $abc$24881$new_n5976 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5983 $abc$24881$new_n5978 $abc$24881$new_n5985 instruction_decoder.o_dcdA[1] $abc$24881$new_n5977 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5979 $abc$24881$new_n5982 $abc$24881$new_n5981 $abc$24881$new_n5978 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5980 regset[5][15] regset[1][15] $abc$24881$new_n5979 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][15] regset[0][15] $abc$24881$new_n5980 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][15] regset[2][15] $abc$24881$new_n5981 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][15] regset[3][15] $abc$24881$new_n5982 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n5984 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][15] regset[8][15] $abc$24881$new_n5983 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][15] regset[9][15] $abc$24881$new_n5984 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5986 regset[15][15] regset[11][15] $abc$24881$new_n5985 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][15] regset[10][15] $abc$24881$new_n5986 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5993 $abc$24881$new_n5996 $abc$24881$new_n5995 $abc$24881$new_n5992 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5994 regset[5][14] regset[1][14] $abc$24881$new_n5993 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][14] regset[0][14] $abc$24881$new_n5994 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][14] regset[2][14] $abc$24881$new_n5995 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][14] regset[3][14] $abc$24881$new_n5996 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5999 regset[15][14] regset[11][14] $abc$24881$new_n5998 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][14] regset[10][14] $abc$24881$new_n5999 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6001 regset[13][14] regset[9][14] $abc$24881$new_n6000 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][14] regset[8][14] $abc$24881$new_n6001 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6003 $abc$24881$new_n6008 $abc$24881$new_n6010 $abc$24881$new_n6002 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n6004 $abc$24881$new_n6006 $abc$24881$new_n6003 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6005 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][14] regset[26][14] $abc$24881$new_n6004 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][14] regset[27][14] $abc$24881$new_n6005 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6007 regset[29][14] regset[25][14] $abc$24881$new_n6006 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][14] regset[24][14] $abc$24881$new_n6007 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6009 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][14] regset[18][14] $abc$24881$new_n6008 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][14] regset[19][14] $abc$24881$new_n6009 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6011 regset[21][14] regset[17][14] $abc$24881$new_n6010 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][14] regset[16][14] $abc$24881$new_n6011 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6014 r_op_Av[13] $abc$24881$new_n5595 $abc$24881$new_n6016 $abc$24881$auto$rtlil.cc:2693:MuxGate$23412 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5596 $abc$24881$new_n3795 dcd_Apc $abc$24881$new_n6015 $abc$24881$new_n6014 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[13] SET_USER_PC.r_upc[13] $abc$24881$new_n6015 -000 1 -010 1 -100 1 -101 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6017 GEN_UHALT_PHASE.r_uhalt_phase GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n6016 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6018 $abc$24881$new_n6030 $abc$24881$new_n6028 $abc$24881$new_n6017 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$24881$new_n6019 $abc$24881$new_n6026 $abc$24881$new_n5637 $abc$24881$new_n6018 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6020 $abc$24881$new_n6022 $abc$24881$new_n6024 $abc$24881$new_n6019 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6021 regset[21][13] regset[17][13] $abc$24881$new_n6020 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][13] regset[16][13] $abc$24881$new_n6021 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6023 regset[23][13] regset[19][13] $abc$24881$new_n6022 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][13] regset[18][13] $abc$24881$new_n6023 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6025 regset[31][13] regset[27][13] $abc$24881$new_n6024 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][13] regset[26][13] $abc$24881$new_n6025 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6027 regset[29][13] regset[25][13] $abc$24881$new_n6026 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][13] regset[24][13] $abc$24881$new_n6027 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6029 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][13] regset[8][13] $abc$24881$new_n6028 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][13] regset[9][13] $abc$24881$new_n6029 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6031 $abc$24881$new_n6033 $abc$24881$new_n6035 $abc$24881$new_n6030 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6032 regset[5][13] regset[1][13] $abc$24881$new_n6031 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][13] regset[0][13] $abc$24881$new_n6032 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6034 regset[15][13] regset[11][13] $abc$24881$new_n6033 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][13] regset[10][13] $abc$24881$new_n6034 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6036 regset[7][13] regset[6][13] $abc$24881$new_n6035 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[3][13] regset[2][13] $abc$24881$new_n6036 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[12] SET_USER_PC.r_upc[12] $abc$24881$new_n6040 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n6042 $abc$24881$new_n6052 $abc$24881$new_n6057 $abc$24881$new_n6041 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] $abc$24881$new_n6043 $abc$24881$new_n6050 $abc$24881$new_n6048 $abc$24881$new_n6042 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n6044 $abc$24881$new_n6047 $abc$24881$new_n6046 $abc$24881$new_n6043 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -.names $abc$24881$new_n6045 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][12] regset[18][12] $abc$24881$new_n6044 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][12] regset[19][12] $abc$24881$new_n6045 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][12] regset[26][12] $abc$24881$new_n6046 -0001 1 -0011 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][12] regset[27][12] $abc$24881$new_n6047 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n6049 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[21][12] regset[17][12] $abc$24881$new_n6048 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][12] regset[16][12] $abc$24881$new_n6049 -00000 1 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n6051 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][12] regset[24][12] $abc$24881$new_n6050 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][12] regset[25][12] $abc$24881$new_n6051 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[3] $abc$24881$new_n6053 $abc$24881$new_n6055 $abc$24881$new_n6052 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6054 regset[13][12] regset[9][12] $abc$24881$new_n6053 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][12] regset[8][12] $abc$24881$new_n6054 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6056 regset[4][12] regset[0][12] $abc$24881$new_n6055 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[2] regset[5][12] regset[1][12] $abc$24881$new_n6056 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] $abc$24881$new_n6059 $abc$24881$new_n6058 $abc$24881$new_n6061 $abc$24881$new_n6060 $abc$24881$new_n6057 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[14][12] regset[6][12] $abc$24881$new_n6058 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[10][12] regset[2][12] $abc$24881$new_n6059 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[15][12] regset[7][12] $abc$24881$new_n6060 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[11][12] regset[3][12] $abc$24881$new_n6061 -0000 1 -0010 1 -1000 1 -1001 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6063 r_op_Av[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23416 -010 1 -011 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3805 $abc$24881$new_n9625 $abc$24881$new_n6086 $abc$24881$new_n6063 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6068 $abc$24881$new_n6070 $abc$24881$new_n6072 $abc$24881$new_n6067 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6069 regset[21][11] regset[17][11] $abc$24881$new_n6068 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][11] regset[16][11] $abc$24881$new_n6069 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6071 regset[31][11] regset[27][11] $abc$24881$new_n6070 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][11] regset[26][11] $abc$24881$new_n6071 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6073 regset[23][11] regset[19][11] $abc$24881$new_n6072 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][11] regset[18][11] $abc$24881$new_n6073 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6077 $abc$24881$new_n5637 $abc$24881$new_n6085 $abc$24881$new_n6084 $abc$24881$new_n6076 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6078 $abc$24881$new_n6080 $abc$24881$new_n6082 $abc$24881$new_n6077 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6079 regset[15][11] regset[11][11] $abc$24881$new_n6078 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][11] regset[10][11] $abc$24881$new_n6079 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6081 regset[7][11] regset[6][11] $abc$24881$new_n6080 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[3][11] regset[2][11] $abc$24881$new_n6081 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6083 regset[5][11] regset[1][11] $abc$24881$new_n6082 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][11] regset[0][11] $abc$24881$new_n6083 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[13][11] regset[9][11] $abc$24881$new_n6084 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][11] regset[8][11] $abc$24881$new_n6085 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[11] SET_USER_PC.r_upc[11] $abc$24881$new_n6086 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6088 r_op_Av[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23418 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3810 $abc$24881$new_n6089 $abc$24881$new_n6110 $abc$24881$new_n6088 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6090 SET_USER_BUSERR.r_ubus_err_flag ibus_err_flag $abc$24881$new_n6089 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6091 $abc$24881$new_n6103 $abc$24881$new_n6101 $abc$24881$new_n6090 -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n6092 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6097 $abc$24881$new_n6099 $abc$24881$new_n6091 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6093 $abc$24881$new_n6095 $abc$24881$new_n6092 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6094 regset[5][10] regset[1][10] $abc$24881$new_n6093 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][10] regset[0][10] $abc$24881$new_n6094 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6096 regset[7][10] regset[3][10] $abc$24881$new_n6095 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[6][10] regset[2][10] $abc$24881$new_n6096 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6098 regset[15][10] regset[11][10] $abc$24881$new_n6097 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][10] regset[10][10] $abc$24881$new_n6098 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6100 regset[13][10] regset[9][10] $abc$24881$new_n6099 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][10] regset[8][10] $abc$24881$new_n6100 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6102 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][10] regset[25][10] $abc$24881$new_n6101 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][10] regset[24][10] $abc$24881$new_n6102 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6104 $abc$24881$new_n6106 $abc$24881$new_n6108 $abc$24881$new_n6103 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6105 regset[21][10] regset[17][10] $abc$24881$new_n6104 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][10] regset[16][10] $abc$24881$new_n6105 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6107 regset[23][10] regset[19][10] $abc$24881$new_n6106 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][10] regset[18][10] $abc$24881$new_n6107 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6109 regset[31][10] regset[27][10] $abc$24881$new_n6108 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][10] regset[26][10] $abc$24881$new_n6109 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[10] SET_USER_PC.r_upc[10] $abc$24881$new_n6110 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6112 r_op_Av[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23420 -010 1 -011 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3815 $abc$24881$new_n6113 $abc$24881$new_n6134 $abc$24881$new_n6112 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names dcd_Acc $abc$24881$new_n6114 SET_TRAP_N_UBREAK.r_trap $abc$24881$new_n6113 -010 1 -011 1 -100 1 -110 1 -.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6115 $abc$24881$new_n6127 $abc$24881$new_n6125 $abc$24881$new_n6114 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names $abc$24881$new_n6116 $abc$24881$new_n6123 $abc$24881$new_n5637 $abc$24881$new_n6115 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6117 $abc$24881$new_n6119 $abc$24881$new_n6121 $abc$24881$new_n6116 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6118 regset[23][9] regset[19][9] $abc$24881$new_n6117 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][9] regset[18][9] $abc$24881$new_n6118 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6120 regset[21][9] regset[17][9] $abc$24881$new_n6119 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][9] regset[16][9] $abc$24881$new_n6120 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6122 regset[31][9] regset[27][9] $abc$24881$new_n6121 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][9] regset[26][9] $abc$24881$new_n6122 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6124 regset[29][9] regset[25][9] $abc$24881$new_n6123 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][9] regset[24][9] $abc$24881$new_n6124 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6126 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][9] regset[8][9] $abc$24881$new_n6125 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][9] regset[9][9] $abc$24881$new_n6126 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6128 $abc$24881$new_n6130 $abc$24881$new_n6132 $abc$24881$new_n6127 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6129 regset[7][9] regset[6][9] $abc$24881$new_n6128 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[3][9] regset[2][9] $abc$24881$new_n6129 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6131 regset[15][9] regset[11][9] $abc$24881$new_n6130 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][9] regset[10][9] $abc$24881$new_n6131 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6133 regset[5][9] regset[1][9] $abc$24881$new_n6132 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][9] regset[0][9] $abc$24881$new_n6133 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[9] SET_USER_PC.r_upc[9] $abc$24881$new_n6134 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6136 r_op_Av[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23422 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3820 $abc$24881$new_n6137 $abc$24881$new_n6159 $abc$24881$new_n6136 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6138 SET_USER_ILLEGAL_INSN.r_ill_err_u ill_err_i $abc$24881$new_n6137 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n6139 $abc$24881$new_n6149 $abc$24881$new_n6154 $abc$24881$new_n6138 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -.names $abc$24881$new_n6140 $abc$24881$new_n6147 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6145 $abc$24881$new_n6139 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6141 $abc$24881$new_n6143 $abc$24881$new_n6144 $abc$24881$new_n6140 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6142 regset[15][8] regset[11][8] $abc$24881$new_n6141 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][8] regset[10][8] $abc$24881$new_n6142 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][8] regset[2][8] $abc$24881$new_n6143 -0000 1 -0010 1 -1000 1 -1001 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][8] regset[3][8] $abc$24881$new_n6144 -1000 1 -1010 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6146 regset[13][8] regset[9][8] $abc$24881$new_n6145 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][8] regset[8][8] $abc$24881$new_n6146 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6148 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[4][8] regset[0][8] $abc$24881$new_n6147 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[5][8] regset[1][8] $abc$24881$new_n6148 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6150 $abc$24881$new_n6152 $abc$24881$new_n6149 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6151 regset[23][8] regset[19][8] $abc$24881$new_n6150 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][8] regset[18][8] $abc$24881$new_n6151 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6153 regset[29][8] regset[25][8] $abc$24881$new_n6152 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][8] regset[24][8] $abc$24881$new_n6153 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6155 $abc$24881$new_n6157 $abc$24881$new_n6154 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6156 regset[31][8] regset[27][8] $abc$24881$new_n6155 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][8] regset[26][8] $abc$24881$new_n6156 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6158 regset[21][8] regset[17][8] $abc$24881$new_n6157 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][8] regset[16][8] $abc$24881$new_n6158 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[8] SET_USER_PC.r_upc[8] $abc$24881$new_n6159 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6161 r_op_Av[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23424 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3825 $abc$24881$new_n6162 $abc$24881$new_n6183 $abc$24881$new_n6161 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6163 SET_TRAP_N_UBREAK.r_ubreak break_en $abc$24881$new_n6162 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n6164 $abc$24881$new_n6174 $abc$24881$new_n6176 $abc$24881$new_n6163 -00000 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names $abc$24881$new_n6165 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6172 $abc$24881$new_n6164 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6166 $abc$24881$new_n6168 $abc$24881$new_n6170 $abc$24881$new_n6165 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6167 regset[21][7] regset[17][7] $abc$24881$new_n6166 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][7] regset[16][7] $abc$24881$new_n6167 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6169 regset[23][7] regset[22][7] $abc$24881$new_n6168 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[19][7] regset[18][7] $abc$24881$new_n6169 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6171 regset[29][7] regset[25][7] $abc$24881$new_n6170 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][7] regset[24][7] $abc$24881$new_n6171 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6173 regset[31][7] regset[30][7] $abc$24881$new_n6172 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[27][7] regset[26][7] $abc$24881$new_n6173 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6175 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][7] regset[9][7] $abc$24881$new_n6174 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][7] regset[8][7] $abc$24881$new_n6175 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6177 $abc$24881$new_n6179 $abc$24881$new_n6181 $abc$24881$new_n6176 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6178 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][7] regset[2][7] $abc$24881$new_n6177 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[7][7] regset[3][7] $abc$24881$new_n6178 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6180 regset[15][7] regset[11][7] $abc$24881$new_n6179 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][7] regset[10][7] $abc$24881$new_n6180 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6182 regset[4][7] regset[0][7] $abc$24881$new_n6181 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[5][7] regset[1][7] $abc$24881$new_n6182 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[7] SET_USER_PC.r_upc[7] $abc$24881$new_n6183 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6185 r_op_Av[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23426 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3832 $abc$24881$new_n9887 $abc$24881$new_n6209 $abc$24881$new_n6185 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6191 regset[5][6] regset[1][6] $abc$24881$new_n6190 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[4][6] regset[0][6] $abc$24881$new_n6191 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6193 regset[13][6] regset[9][6] $abc$24881$new_n6192 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][6] regset[8][6] $abc$24881$new_n6193 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6198 regset[15][6] regset[11][6] $abc$24881$new_n6197 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][6] regset[10][6] $abc$24881$new_n6198 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n6200 $abc$24881$new_n6207 $abc$24881$new_n5637 $abc$24881$new_n6199 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6201 $abc$24881$new_n6203 $abc$24881$new_n6205 $abc$24881$new_n6200 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6202 regset[31][6] regset[27][6] $abc$24881$new_n6201 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[30][6] regset[26][6] $abc$24881$new_n6202 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6204 regset[23][6] regset[19][6] $abc$24881$new_n6203 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[22][6] regset[18][6] $abc$24881$new_n6204 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6206 regset[21][6] regset[17][6] $abc$24881$new_n6205 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[20][6] regset[16][6] $abc$24881$new_n6206 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6208 regset[29][6] regset[25][6] $abc$24881$new_n6207 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[28][6] regset[24][6] $abc$24881$new_n6208 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[6] SET_USER_PC.r_upc[6] $abc$24881$new_n6209 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n6214 $abc$24881$new_n5637 $abc$24881$new_n6222 $abc$24881$new_n6221 $abc$24881$new_n6213 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6215 $abc$24881$new_n6217 $abc$24881$new_n6219 $abc$24881$new_n6214 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6216 regset[31][5] regset[27][5] $abc$24881$new_n6215 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][5] regset[26][5] $abc$24881$new_n6216 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6218 regset[23][5] regset[19][5] $abc$24881$new_n6217 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][5] regset[18][5] $abc$24881$new_n6218 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6220 regset[21][5] regset[17][5] $abc$24881$new_n6219 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][5] regset[16][5] $abc$24881$new_n6220 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][5] regset[25][5] $abc$24881$new_n6221 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][5] regset[24][5] $abc$24881$new_n6222 -0001 1 -0011 1 -1010 1 -1011 1 -.names $abc$24881$new_n6224 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6231 $abc$24881$new_n6223 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6225 $abc$24881$new_n6227 $abc$24881$new_n6229 $abc$24881$new_n6224 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6226 regset[12][5] regset[8][5] $abc$24881$new_n6225 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[13][5] regset[9][5] $abc$24881$new_n6226 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6228 regset[15][5] regset[11][5] $abc$24881$new_n6227 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][5] regset[10][5] $abc$24881$new_n6228 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6230 regset[5][5] regset[1][5] $abc$24881$new_n6229 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][5] regset[0][5] $abc$24881$new_n6230 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6232 regset[7][5] regset[3][5] $abc$24881$new_n6231 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[6][5] regset[2][5] $abc$24881$new_n6232 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6235 r_op_Av[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23430 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3843 $abc$24881$new_n9635 $abc$24881$new_n6258 $abc$24881$new_n6235 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6240 regset[21][4] regset[17][4] $abc$24881$new_n6239 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[20][4] regset[16][4] $abc$24881$new_n6240 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6242 regset[29][4] regset[25][4] $abc$24881$new_n6241 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[28][4] regset[24][4] $abc$24881$new_n6242 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6244 $abc$24881$new_n6246 $abc$24881$new_n6243 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6245 regset[31][4] regset[27][4] $abc$24881$new_n6244 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][4] regset[26][4] $abc$24881$new_n6245 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6247 regset[23][4] regset[19][4] $abc$24881$new_n6246 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[22][4] regset[18][4] $abc$24881$new_n6247 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6250 regset[15][4] regset[11][4] $abc$24881$new_n6249 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][4] regset[10][4] $abc$24881$new_n6250 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6254 $abc$24881$new_n6252 $abc$24881$new_n6256 $abc$24881$new_n6251 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6253 regset[13][4] regset[9][4] $abc$24881$new_n6252 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][4] regset[8][4] $abc$24881$new_n6253 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6255 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[4][4] regset[0][4] $abc$24881$new_n6254 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[5][4] regset[1][4] $abc$24881$new_n6255 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6257 regset[6][4] regset[2][4] $abc$24881$new_n6256 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[7][4] regset[3][4] $abc$24881$new_n6257 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[4] SET_USER_PC.r_upc[4] $abc$24881$new_n6258 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n6260 r_op_Av[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23432 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3848 $abc$24881$new_n9639 $abc$24881$new_n6285 $abc$24881$new_n6260 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6265 regset[21][3] regset[20][3] $abc$24881$new_n6264 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[17][3] regset[16][3] $abc$24881$new_n6265 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6267 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][3] regset[25][3] $abc$24881$new_n6266 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][3] regset[24][3] $abc$24881$new_n6267 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6270 regset[23][3] regset[22][3] $abc$24881$new_n6269 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[19][3] regset[18][3] $abc$24881$new_n6270 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6273 regset[31][3] regset[27][3] $abc$24881$new_n6272 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][3] regset[26][3] $abc$24881$new_n6273 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6276 $abc$24881$new_n6278 $abc$24881$new_n6275 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6277 regset[13][3] regset[9][3] $abc$24881$new_n6276 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][3] regset[8][3] $abc$24881$new_n6277 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6279 regset[7][3] regset[3][3] $abc$24881$new_n6278 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[6][3] regset[2][3] $abc$24881$new_n6279 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6281 regset[5][3] regset[1][3] $abc$24881$new_n6280 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][3] regset[0][3] $abc$24881$new_n6281 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6283 regset[15][3] regset[11][3] $abc$24881$new_n6282 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][3] regset[10][3] $abc$24881$new_n6283 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4071 instruction_decoder.o_pc[3] SET_USER_PC.r_upc[3] $abc$24881$new_n6285 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n6292 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][2] regset[25][2] $abc$24881$new_n6291 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][2] regset[24][2] $abc$24881$new_n6292 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6295 regset[31][2] regset[27][2] $abc$24881$new_n6294 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][2] regset[26][2] $abc$24881$new_n6295 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6298 regset[23][2] regset[22][2] $abc$24881$new_n6297 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[19][2] regset[18][2] $abc$24881$new_n6298 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6301 regset[21][2] regset[20][2] $abc$24881$new_n6300 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[17][2] regset[16][2] $abc$24881$new_n6301 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6304 $abc$24881$new_n6306 $abc$24881$new_n6303 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6305 regset[13][2] regset[9][2] $abc$24881$new_n6304 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][2] regset[8][2] $abc$24881$new_n6305 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6307 regset[7][2] regset[3][2] $abc$24881$new_n6306 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[6][2] regset[2][2] $abc$24881$new_n6307 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6309 regset[5][2] regset[1][2] $abc$24881$new_n6308 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[4][2] regset[0][2] $abc$24881$new_n6309 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6311 regset[15][2] regset[11][2] $abc$24881$new_n6310 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[14][2] regset[10][2] $abc$24881$new_n6311 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6318 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][1] regset[25][1] $abc$24881$new_n6317 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][1] regset[24][1] $abc$24881$new_n6318 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6321 regset[31][1] regset[27][1] $abc$24881$new_n6320 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[30][1] regset[26][1] $abc$24881$new_n6321 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6324 regset[23][1] regset[22][1] $abc$24881$new_n6323 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[19][1] regset[18][1] $abc$24881$new_n6324 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6327 regset[21][1] regset[20][1] $abc$24881$new_n6326 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] regset[17][1] regset[16][1] $abc$24881$new_n6327 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6329 $abc$24881$new_n6334 $abc$24881$new_n6336 $abc$24881$new_n6328 -00100 1 -00101 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6330 $abc$24881$new_n6332 $abc$24881$new_n6329 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6331 regset[7][1] regset[3][1] $abc$24881$new_n6330 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[6][1] regset[2][1] $abc$24881$new_n6331 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6333 regset[13][1] regset[9][1] $abc$24881$new_n6332 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[2] regset[12][1] regset[8][1] $abc$24881$new_n6333 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6335 regset[5][1] regset[1][1] $abc$24881$new_n6334 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[4][1] regset[0][1] $abc$24881$new_n6335 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6337 regset[15][1] regset[11][1] $abc$24881$new_n6336 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][1] regset[10][1] $abc$24881$new_n6337 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5672 $abc$24881$new_n3859 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4071 $abc$24881$new_n6338 -0000 1 -0001 1 -0010 1 -0011 1 -1010 1 -1110 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6345 $abc$24881$new_n6347 $abc$24881$new_n6349 $abc$24881$new_n6344 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6346 regset[7][0] regset[3][0] $abc$24881$new_n6345 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[6][0] regset[2][0] $abc$24881$new_n6346 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6348 regset[13][0] regset[9][0] $abc$24881$new_n6347 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][0] regset[8][0] $abc$24881$new_n6348 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6350 regset[15][0] regset[11][0] $abc$24881$new_n6349 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][0] regset[10][0] $abc$24881$new_n6350 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6352 regset[5][0] regset[1][0] $abc$24881$new_n6351 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[4][0] regset[0][0] $abc$24881$new_n6352 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6355 $abc$24881$new_n6357 $abc$24881$new_n6359 $abc$24881$new_n6354 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6356 regset[31][0] regset[27][0] $abc$24881$new_n6355 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[30][0] regset[26][0] $abc$24881$new_n6356 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6358 regset[29][0] regset[25][0] $abc$24881$new_n6357 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[28][0] regset[24][0] $abc$24881$new_n6358 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6360 regset[23][0] regset[22][0] $abc$24881$new_n6359 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[0] regset[19][0] regset[18][0] $abc$24881$new_n6360 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6362 regset[21][0] regset[17][0] $abc$24881$new_n6361 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[20][0] regset[16][0] $abc$24881$new_n6362 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n4028 $abc$24881$new_n6364 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23440 -010 1 -011 1 -101 1 -111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[30] $abc$24881$new_n6365 $abc$24881$new_n4280 $abc$24881$new_n6364 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$24881$new_n6382 i_pf_instruction[17] i_pf_instruction_pc[29] i_pf_instruction_pc[28] $abc$24881$new_n6366 $abc$24881$new_n6365 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -.names i_pf_instruction[17] i_pf_instruction_pc[27] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n6366 -0110 1 -1000 1 -.names $abc$24881$new_n6380 i_pf_instruction[17] $abc$24881$new_n6368 $abc$24881$new_n6367 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n6379 i_pf_instruction[17] i_pf_instruction_pc[21] i_pf_instruction_pc[20] $abc$24881$new_n6369 $abc$24881$new_n6368 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11000 1 -.names i_pf_instruction_pc[18] i_pf_instruction_pc[19] i_pf_instruction[17] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6369 -00100 1 -00110 1 -00111 1 -11010 1 -.names i_pf_instruction[15] i_pf_instruction_pc[15] i_pf_instruction[16] i_pf_instruction_pc[16] $abc$24881$new_n6371 $abc$24881$new_n6370 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_pf_instruction_pc[13] i_pf_instruction[13] i_pf_instruction_pc[14] i_pf_instruction[14] $abc$24881$new_n6372 $abc$24881$new_n6371 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_pf_instruction_pc[11] i_pf_instruction[11] i_pf_instruction_pc[12] i_pf_instruction[12] $abc$24881$new_n6373 $abc$24881$new_n6372 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_pf_instruction_pc[9] i_pf_instruction[9] i_pf_instruction_pc[10] i_pf_instruction[10] $abc$24881$new_n6374 $abc$24881$new_n6373 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names i_pf_instruction_pc[8] i_pf_instruction[8] $abc$24881$new_n6375 $abc$24881$new_n6374 -000 1 -001 1 -011 1 -101 1 -.names $abc$24881$new_n6376 i_pf_instruction_pc[7] i_pf_instruction[7] i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6375 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names i_pf_instruction_pc[5] i_pf_instruction[5] i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6377 $abc$24881$new_n6376 -01010 1 -01100 1 -10010 1 -10100 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[4] i_pf_instruction[4] $abc$24881$new_n6378 $abc$24881$new_n6377 -000 1 -001 1 -011 1 -101 1 -.names i_pf_instruction[2] i_pf_instruction_pc[2] i_pf_instruction_pc[3] i_pf_instruction[3] $abc$24881$new_n6378 -0000 1 -0001 1 -0010 1 -0100 1 -1000 1 -1100 1 -.names i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[19] $abc$24881$new_n6379 -000 1 -001 1 -010 1 -011 1 -100 1 -.names i_pf_instruction[17] i_pf_instruction_pc[25] i_pf_instruction_pc[24] i_pf_instruction_pc[23] i_pf_instruction_pc[22] $abc$24881$new_n6380 -01111 1 -10000 1 -.names i_pf_instruction[17] i_pf_instruction_pc[26] i_pf_instruction_pc[27] $abc$24881$new_n6382 -000 1 -001 1 -010 1 -011 1 -100 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n6387 $abc$24881$new_n4279 $abc$24881$auto$rtlil.cc:2693:MuxGate$23444 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction[17] i_pf_instruction_pc[28] $abc$24881$new_n6382 $abc$24881$new_n6366 $abc$24881$new_n6387 -0000 1 -0001 1 -0011 1 -0110 1 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n6389 $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$23446 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[27] i_pf_instruction[17] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n6389 -0000 1 -0001 1 -0011 1 -0100 1 -0110 1 -0111 1 -1010 1 -1101 1 -.names $abc$24881$new_n4028 $abc$24881$new_n6391 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23448 -010 1 -011 1 -101 1 -111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n4265 $abc$24881$new_n6391 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n6393 $abc$24881$new_n4264 $abc$24881$auto$rtlil.cc:2693:MuxGate$23450 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[25] i_pf_instruction[17] i_pf_instruction_pc[24] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n6393 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11001 1 -.names i_pf_instruction[17] i_pf_instruction_pc[22] $abc$24881$new_n6368 $abc$24881$new_n6394 -000 1 -001 1 -011 1 -101 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n6396 $abc$24881$new_n4267 $abc$24881$auto$rtlil.cc:2693:MuxGate$23452 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction[17] i_pf_instruction_pc[24] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n6396 -0010 1 -0100 1 -0101 1 -0111 1 -1001 1 -1100 1 -1110 1 -1111 1 -.names $abc$24881$new_n4028 $abc$24881$new_n6398 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23454 -010 1 -011 1 -101 1 -111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n4273 $abc$24881$new_n6398 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$24881$new_n4028 $abc$24881$new_n6400 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23456 -010 1 -011 1 -101 1 -111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[22] $abc$24881$new_n6368 $abc$24881$new_n4287 $abc$24881$new_n6400 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] $abc$24881$new_n6402 $abc$24881$new_n4289 $abc$24881$auto$rtlil.cc:2693:MuxGate$23458 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[21] i_pf_instruction[17] i_pf_instruction_pc[20] $abc$24881$new_n6379 $abc$24881$new_n6369 $abc$24881$new_n6402 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10111 1 -11010 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] $abc$24881$new_n6404 $abc$24881$new_n4291 $abc$24881$auto$rtlil.cc:2693:MuxGate$23460 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction[17] i_pf_instruction_pc[20] $abc$24881$new_n6379 $abc$24881$new_n6369 $abc$24881$new_n6404 -0000 1 -0001 1 -0011 1 -0110 1 -1010 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] $abc$24881$new_n6406 $abc$24881$new_n4293 $abc$24881$auto$rtlil.cc:2693:MuxGate$23462 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[19] i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6406 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11001 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] $abc$24881$new_n6408 $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$23464 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6408 -0010 1 -0100 1 -0101 1 -0111 1 -1001 1 -1100 1 -1110 1 -1111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n6410 $abc$24881$auto$rtlil.cc:2693:MuxGate$23466 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n5442 $abc$24881$new_n6410 -00000 1 -00001 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n6412 $abc$24881$new_n5455 $abc$24881$auto$rtlil.cc:2693:MuxGate$23468 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction[16] i_pf_instruction_pc[16] i_pf_instruction[15] i_pf_instruction_pc[15] $abc$24881$new_n6371 $abc$24881$new_n6412 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] $abc$24881$new_n6414 $abc$24881$auto$rtlil.cc:2693:MuxGate$23470 -001 1 -011 1 -110 1 -111 1 -.names i_pf_instruction[15] i_pf_instruction_pc[15] $abc$24881$new_n6371 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6414 -0000 1 -0110 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n6416 i_pf_instruction[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23472 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[14] i_pf_instruction[14] i_pf_instruction_pc[13] i_pf_instruction[13] $abc$24881$new_n6372 $abc$24881$new_n6416 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n6418 $abc$24881$auto$rtlil.cc:2693:MuxGate$23474 -001 1 -011 1 -110 1 -111 1 -.names i_pf_instruction[13] i_pf_instruction_pc[13] $abc$24881$new_n6372 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6418 -0000 1 -0110 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n6420 i_pf_instruction[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23476 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[12] i_pf_instruction[12] i_pf_instruction_pc[11] i_pf_instruction[11] $abc$24881$new_n6373 $abc$24881$new_n6420 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] $abc$24881$new_n6422 $abc$24881$auto$rtlil.cc:2693:MuxGate$23478 -000 1 -010 1 -110 1 -111 1 -.names i_pf_instruction[11] i_pf_instruction_pc[11] $abc$24881$new_n6373 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6422 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1110 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] $abc$24881$new_n6424 i_pf_instruction[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23480 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[10] i_pf_instruction[10] i_pf_instruction_pc[9] i_pf_instruction[9] $abc$24881$new_n6374 $abc$24881$new_n6424 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n6426 $abc$24881$auto$rtlil.cc:2693:MuxGate$23482 -000 1 -010 1 -110 1 -111 1 -.names i_pf_instruction[9] i_pf_instruction_pc[9] $abc$24881$new_n6374 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6426 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1110 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] $abc$24881$new_n6428 $abc$24881$auto$rtlil.cc:2693:MuxGate$23484 -000 1 -010 1 -110 1 -111 1 -.names i_pf_instruction[8] i_pf_instruction_pc[8] $abc$24881$new_n6375 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6428 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1110 1 -.names $abc$24881$new_n4028 i_pf_instruction[7] $abc$24881$new_n6430 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23486 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names i_pf_instruction_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6376 i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6430 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n6432 i_pf_instruction[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23488 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[6] i_pf_instruction[6] i_pf_instruction_pc[5] i_pf_instruction[5] $abc$24881$new_n6377 $abc$24881$new_n6432 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 i_pf_instruction[5] $abc$24881$new_n6434 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23490 -0010 1 -0011 1 -0100 1 -0101 1 -1001 1 -1011 1 -1101 1 -1111 1 -.names i_pf_instruction_pc[5] $abc$24881$new_n6377 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6434 -000 1 -110 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] $abc$24881$new_n6436 i_pf_instruction[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23492 -00010 1 -00011 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[4] i_pf_instruction[4] $abc$24881$new_n6378 $abc$24881$new_n6436 -000 1 -011 1 -101 1 -110 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] $abc$24881$new_n6438 $abc$24881$auto$rtlil.cc:2693:MuxGate$23494 -000 1 -010 1 -110 1 -111 1 -.names i_pf_instruction[3] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6438 -00000 1 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -11000 1 -.names $abc$24881$new_n4028 i_pf_instruction[2] i_pf_instruction_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23496 -00000 1 -00001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[30] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6441 $abc$24881$new_n6459 $abc$24881$auto$rtlil.cc:2693:MuxGate$23498 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instruction_decoder.o_pc[27] instruction_decoder.o_pc[28] instruction_decoder.o_pc[29] $abc$24881$new_n6442 $abc$24881$new_n6441 -1111 1 -.names instruction_decoder.o_pc[23] instruction_decoder.o_pc[24] instruction_decoder.o_pc[25] instruction_decoder.o_pc[26] $abc$24881$new_n6443 $abc$24881$new_n6442 -11111 1 -.names instruction_decoder.o_pc[20] instruction_decoder.o_pc[21] instruction_decoder.o_pc[22] $abc$24881$new_n6444 $abc$24881$new_n6443 -1111 1 -.names instruction_decoder.o_pc[18] instruction_decoder.o_pc[19] $abc$24881$new_n6445 $abc$24881$new_n6444 -111 1 -.names instruction_decoder.o_pc[17] $abc$24881$new_n6446 $abc$24881$new_n6445 -11 1 -.names instruction_decoder.o_pc[16] $abc$24881$new_n6447 $abc$24881$new_n6446 -11 1 -.names instruction_decoder.o_pc[15] $abc$24881$new_n6448 $abc$24881$new_n6447 -11 1 -.names instruction_decoder.o_pc[14] $abc$24881$new_n6449 $abc$24881$new_n6448 -11 1 -.names instruction_decoder.o_pc[13] $abc$24881$new_n6450 $abc$24881$new_n6449 -11 1 -.names instruction_decoder.o_pc[12] $abc$24881$new_n6451 $abc$24881$new_n6450 -11 1 -.names instruction_decoder.o_pc[11] $abc$24881$new_n6452 $abc$24881$new_n6451 -11 1 -.names instruction_decoder.o_pc[10] $abc$24881$new_n6453 $abc$24881$new_n6452 -11 1 -.names instruction_decoder.o_pc[9] $abc$24881$new_n6454 $abc$24881$new_n6453 -11 1 -.names instruction_decoder.o_pc[8] $abc$24881$new_n6455 $abc$24881$new_n6454 -11 1 -.names instruction_decoder.o_pc[6] instruction_decoder.o_pc[7] $abc$24881$new_n6456 $abc$24881$new_n6455 -111 1 -.names instruction_decoder.o_pc[5] $abc$24881$new_n6457 $abc$24881$new_n6456 -11 1 -.names instruction_decoder.o_pc[4] $abc$24881$new_n6458 $abc$24881$new_n6457 -11 1 -.names instruction_decoder.o_pc[1] instruction_decoder.o_pc[2] instruction_decoder.o_pc[3] $abc$24881$new_n6458 -111 1 -.names i_pf_instruction_pc[30] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6460 i_pf_instruction[31] $abc$24881$new_n6459 -0010 1 -1000 1 -1001 1 -1011 1 -.names i_pf_instruction_pc[29] $abc$24881$new_n6461 $abc$24881$new_n6460 -11 1 -.names i_pf_instruction_pc[28] $abc$24881$new_n6462 $abc$24881$new_n6461 -11 1 -.names i_pf_instruction_pc[27] i_pf_instruction_pc[26] $abc$24881$new_n6463 $abc$24881$new_n6462 -111 1 -.names i_pf_instruction_pc[25] i_pf_instruction_pc[24] $abc$24881$new_n6464 $abc$24881$new_n6463 -111 1 -.names i_pf_instruction_pc[23] i_pf_instruction_pc[22] i_pf_instruction_pc[21] $abc$24881$new_n6465 $abc$24881$new_n6464 -1111 1 -.names i_pf_instruction_pc[20] i_pf_instruction_pc[19] i_pf_instruction_pc[18] $abc$24881$new_n6466 $abc$24881$new_n6465 -1111 1 -.names i_pf_instruction_pc[17] $abc$24881$new_n6467 $abc$24881$new_n6466 -11 1 -.names i_pf_instruction_pc[16] $abc$24881$new_n6468 $abc$24881$new_n6467 -11 1 -.names i_pf_instruction_pc[15] $abc$24881$new_n6469 $abc$24881$new_n6468 -11 1 -.names i_pf_instruction_pc[14] $abc$24881$new_n6470 $abc$24881$new_n6469 -11 1 -.names i_pf_instruction_pc[13] $abc$24881$new_n6471 $abc$24881$new_n6470 -11 1 -.names i_pf_instruction_pc[12] $abc$24881$new_n6472 $abc$24881$new_n6471 -11 1 -.names i_pf_instruction_pc[11] i_pf_instruction_pc[10] $abc$24881$new_n6473 $abc$24881$new_n6472 -111 1 -.names i_pf_instruction_pc[9] i_pf_instruction_pc[8] i_pf_instruction_pc[7] $abc$24881$new_n6474 $abc$24881$new_n6473 -1111 1 -.names i_pf_instruction_pc[6] i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] $abc$24881$new_n6474 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_valid $abc$24881$new_n6475 -001 1 -010 1 -011 1 -.names $abc$24881$new_n6475 $abc$24881$new_n6477 instruction_decoder.o_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23500 -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n6478 i_pf_instruction_pc[29] $abc$24881$new_n6461 i_pf_instruction[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6477 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.o_pc[29] instruction_decoder.o_pc[27] instruction_decoder.o_pc[28] $abc$24881$new_n6442 $abc$24881$new_n6478 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[28] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6480 $abc$24881$new_n6481 $abc$24881$auto$rtlil.cc:2693:MuxGate$23502 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names instruction_decoder.o_pc[27] $abc$24881$new_n6442 $abc$24881$new_n6480 -11 1 -.names i_pf_instruction_pc[28] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6462 i_pf_instruction[31] $abc$24881$new_n6481 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[27] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6442 $abc$24881$new_n6483 $abc$24881$auto$rtlil.cc:2693:MuxGate$23504 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names i_pf_instruction_pc[27] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[26] $abc$24881$new_n6463 i_pf_instruction[31] $abc$24881$new_n6483 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[26] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6485 $abc$24881$new_n6488 $abc$24881$auto$rtlil.cc:2693:MuxGate$23506 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names instruction_decoder.o_pc[25] $abc$24881$new_n6486 $abc$24881$new_n6485 -11 1 -.names instruction_decoder.o_pc[24] $abc$24881$new_n6487 $abc$24881$new_n6486 -11 1 -.names instruction_decoder.o_pc[23] $abc$24881$new_n6443 $abc$24881$new_n6487 -11 1 -.names i_pf_instruction_pc[26] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6463 i_pf_instruction[31] $abc$24881$new_n6488 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[25] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6486 $abc$24881$new_n6490 $abc$24881$auto$rtlil.cc:2693:MuxGate$23508 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names i_pf_instruction_pc[25] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[24] $abc$24881$new_n6464 i_pf_instruction[31] $abc$24881$new_n6490 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6487 $abc$24881$new_n6492 $abc$24881$auto$rtlil.cc:2693:MuxGate$23510 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6464 i_pf_instruction[31] $abc$24881$new_n6492 -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[23] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6443 $abc$24881$new_n6494 $abc$24881$auto$rtlil.cc:2693:MuxGate$23512 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[23] $abc$24881$new_n6495 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6494 -010 1 -100 1 -.names i_pf_instruction_pc[22] i_pf_instruction_pc[21] $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6495 -1110 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[22] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6497 $abc$24881$new_n6499 $abc$24881$auto$rtlil.cc:2693:MuxGate$23514 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names instruction_decoder.o_pc[21] $abc$24881$new_n6498 $abc$24881$new_n6497 -11 1 -.names instruction_decoder.o_pc[20] $abc$24881$new_n6444 $abc$24881$new_n6498 -11 1 -.names i_pf_instruction_pc[22] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[21] $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6499 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[21] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6498 $abc$24881$new_n6501 $abc$24881$auto$rtlil.cc:2693:MuxGate$23516 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[21] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6501 -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[20] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6444 $abc$24881$new_n6503 $abc$24881$auto$rtlil.cc:2693:MuxGate$23518 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[20] $abc$24881$new_n6504 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6503 -010 1 -100 1 -.names i_pf_instruction_pc[19] i_pf_instruction_pc[18] $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6504 -1110 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[19] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6506 $abc$24881$new_n6507 $abc$24881$auto$rtlil.cc:2693:MuxGate$23520 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names instruction_decoder.o_pc[18] $abc$24881$new_n6445 $abc$24881$new_n6506 -11 1 -.names i_pf_instruction_pc[19] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[18] $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6507 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[18] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6445 $abc$24881$new_n6509 $abc$24881$auto$rtlil.cc:2693:MuxGate$23522 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[18] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6509 -0010 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[17] $abc$24881$new_n6446 $abc$24881$new_n6511 $abc$24881$auto$rtlil.cc:2693:MuxGate$23524 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[17] $abc$24881$new_n6467 i_pf_instruction[31] $abc$24881$new_n6511 -000 1 -001 1 -011 1 -110 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[16] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6447 $abc$24881$new_n6513 $abc$24881$auto$rtlil.cc:2693:MuxGate$23526 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[16] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6468 i_pf_instruction[31] $abc$24881$new_n6513 -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[15] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6448 $abc$24881$new_n6515 $abc$24881$auto$rtlil.cc:2693:MuxGate$23528 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[15] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6469 i_pf_instruction[31] $abc$24881$new_n6515 -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[14] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6449 $abc$24881$new_n6517 $abc$24881$auto$rtlil.cc:2693:MuxGate$23530 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[14] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6470 i_pf_instruction[31] $abc$24881$new_n6517 -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[13] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6450 $abc$24881$new_n6519 $abc$24881$auto$rtlil.cc:2693:MuxGate$23532 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[13] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6471 i_pf_instruction[31] $abc$24881$new_n6519 -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[12] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6451 $abc$24881$new_n6521 $abc$24881$auto$rtlil.cc:2693:MuxGate$23534 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[12] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6472 i_pf_instruction[31] $abc$24881$new_n6521 -0010 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[11] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6452 $abc$24881$new_n6523 $abc$24881$auto$rtlil.cc:2693:MuxGate$23536 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names i_pf_instruction_pc[11] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[10] $abc$24881$new_n6473 i_pf_instruction[31] $abc$24881$new_n6523 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[10] $abc$24881$new_n6453 $abc$24881$new_n6525 $abc$24881$auto$rtlil.cc:2693:MuxGate$23538 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[10] $abc$24881$new_n6473 i_pf_instruction[31] $abc$24881$new_n6525 -010 1 -100 1 -101 1 -111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[9] $abc$24881$new_n6454 $abc$24881$new_n6527 $abc$24881$auto$rtlil.cc:2693:MuxGate$23540 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[9] i_pf_instruction_pc[8] i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6527 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6528 -11110 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[8] $abc$24881$new_n6455 $abc$24881$new_n6530 $abc$24881$auto$rtlil.cc:2693:MuxGate$23542 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[8] i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6530 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[7] $abc$24881$new_n6532 $abc$24881$new_n6533 $abc$24881$auto$rtlil.cc:2693:MuxGate$23544 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_pc[6] $abc$24881$new_n6456 $abc$24881$new_n6532 -11 1 -.names i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6533 -011 1 -100 1 -101 1 -110 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[6] $abc$24881$new_n6456 $abc$24881$new_n6535 $abc$24881$auto$rtlil.cc:2693:MuxGate$23546 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6535 -01 1 -10 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[5] $abc$24881$new_n6457 $abc$24881$new_n6537 $abc$24881$auto$rtlil.cc:2693:MuxGate$23548 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6537 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[4] $abc$24881$new_n6458 $abc$24881$new_n6539 $abc$24881$auto$rtlil.cc:2693:MuxGate$23550 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6539 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[3] $abc$24881$new_n6541 $abc$24881$new_n6542 $abc$24881$auto$rtlil.cc:2693:MuxGate$23552 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_pc[1] instruction_decoder.o_pc[2] $abc$24881$new_n6541 -11 1 -.names i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6542 -010 1 -100 1 -101 1 -111 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[2] instruction_decoder.o_pc[1] $abc$24881$new_n6544 $abc$24881$auto$rtlil.cc:2693:MuxGate$23554 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6544 -00 1 -11 1 -.names $abc$24881$new_n6546 $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[31] $abc$24881$new_n6568 $abc$24881$auto$rtlil.cc:2693:MuxGate$23556 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10010 1 -11010 1 -11011 1 -.names $abc$24881$new_n9657 $abc$24881$new_n4071 $abc$24881$new_n5672 instruction_decoder.o_pc[31] SET_USER_PC.r_upc[31] $abc$24881$new_n6546 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6550 $abc$24881$new_n6552 $abc$24881$new_n6554 $abc$24881$new_n6549 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6551 regset[15][31] regset[11][31] $abc$24881$new_n6550 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[14][31] regset[10][31] $abc$24881$new_n6551 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6553 regset[7][31] regset[3][31] $abc$24881$new_n6552 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[6][31] regset[2][31] $abc$24881$new_n6553 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6555 regset[5][31] regset[1][31] $abc$24881$new_n6554 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[4][31] regset[0][31] $abc$24881$new_n6555 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6557 regset[13][31] regset[9][31] $abc$24881$new_n6556 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[12][31] regset[8][31] $abc$24881$new_n6557 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6559 $abc$24881$new_n6561 $abc$24881$new_n6563 $abc$24881$new_n6558 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6560 regset[23][31] regset[19][31] $abc$24881$new_n6559 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[22][31] regset[18][31] $abc$24881$new_n6560 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6562 regset[31][31] regset[27][31] $abc$24881$new_n6561 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[30][31] regset[26][31] $abc$24881$new_n6562 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6564 regset[21][31] regset[20][31] $abc$24881$new_n6563 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[0] regset[17][31] regset[16][31] $abc$24881$new_n6564 -000 1 -010 1 -100 1 -101 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6567 regset[29][31] regset[25][31] $abc$24881$new_n6566 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[2] regset[28][31] regset[24][31] $abc$24881$new_n6567 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n6569 i_mem_result[31] wr_index[0] wr_index[1] $abc$24881$new_n6568 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names wr_index[1] wr_index[0] DIVIDE.thedivide.w_n doalu.n dbg_val[31] $abc$24881$new_n6569 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n6576 $abc$24881$new_n5065 $abc$24881$new_n6577 $abc$24881$new_n6571 $abc$24881$new_n6572 $abc$24881$auto$rtlil.cc:2693:MuxGate$23558 -00001 1 -00011 1 -00101 1 -00111 1 -01011 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dcd_I[31] $abc$24881$new_n5090 $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n6571 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n6575 $abc$24881$new_n6573 $abc$24881$new_n6574 $abc$24881$new_n6572 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names dcd_I[31] $abc$24881$new_n5148 $abc$24881$new_n5147 $abc$24881$new_n5149 $abc$24881$new_n5113 $abc$24881$new_n6573 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11110 1 -.names $abc$24881$new_n5151 $abc$24881$new_n6568 $abc$24881$new_n6574 -10 1 -.names dcd_I[31] $abc$24881$new_n4068 SET_USER_PC.r_upc[31] instruction_decoder.o_pc[31] $abc$24881$new_n6575 -0000 1 -0001 1 -0100 1 -0110 1 -1010 1 -1011 1 -1101 1 -1111 1 -.names r_op_Bv[31] $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n6576 -100 1 -.names dcd_I[31] $abc$24881$new_n6568 $abc$24881$new_n4373 $abc$24881$new_n4368 $abc$24881$new_n6578 $abc$24881$new_n6577 -00000 1 -00001 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10110 1 -10111 1 -11100 1 -11110 1 -.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n6579 $abc$24881$new_n6589 $abc$24881$new_n6596 $abc$24881$new_n6578 -00000 1 -00001 1 -00010 1 -00011 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$24881$new_n6580 $abc$24881$new_n6587 $abc$24881$new_n4069 $abc$24881$new_n6579 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n6581 $abc$24881$new_n6583 $abc$24881$new_n6585 $abc$24881$new_n6580 -00010 1 -00011 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6582 regset[7][31] regset[3][31] $abc$24881$new_n6581 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[6][31] regset[2][31] $abc$24881$new_n6582 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6584 regset[5][31] regset[1][31] $abc$24881$new_n6583 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[4][31] regset[0][31] $abc$24881$new_n6584 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6586 regset[13][31] regset[12][31] $abc$24881$new_n6585 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[9][31] regset[8][31] $abc$24881$new_n6586 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6588 regset[15][31] regset[14][31] $abc$24881$new_n6587 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[11][31] regset[10][31] $abc$24881$new_n6588 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n6590 $abc$24881$new_n6592 $abc$24881$new_n6594 $abc$24881$new_n6589 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6591 regset[29][31] regset[25][31] $abc$24881$new_n6590 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[28][31] regset[24][31] $abc$24881$new_n6591 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6593 regset[31][31] regset[27][31] $abc$24881$new_n6592 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[2] regset[30][31] regset[26][31] $abc$24881$new_n6593 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6595 regset[21][31] regset[20][31] $abc$24881$new_n6594 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] regset[17][31] regset[16][31] $abc$24881$new_n6595 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6597 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][31] regset[18][31] $abc$24881$new_n6596 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][31] regset[19][31] $abc$24881$new_n6597 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[6] r_op_F[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23560 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n6600 op_wF $abc$24881$auto$rtlil.cc:2693:MuxGate$23562 -001 1 -011 1 -110 1 -111 1 -.names dcd_wF instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_wR dcd_Acc $abc$24881$new_n6600 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n5364 OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5066 $abc$24881$auto$rtlil.cc:2693:MuxGate$23564 -010 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n5066 OP_REG_ADVANEC.r_op_rA dcd_rA instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23566 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11100 1 -.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[4] OP_REG_ADVANEC.r_op_Bid[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23568 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[4] o_mem_reg[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23570 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 GEN_OP_WR.r_op_wR dcd_wR instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23572 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$24881$new_n5066 FWD_OPERATION.r_op_opn[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[3] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23576 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[4] i_dbg_wreg[4] alu_reg[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23578 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n6475 instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.o_pc[1] i_pf_instruction[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23582 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n4028 dcd_I[31] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n6610 $abc$24881$auto$rtlil.cc:2693:MuxGate$23584 -00010 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4287 $abc$24881$new_n6610 -100 1 -101 1 -111 1 -.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[14] i_pf_instruction[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23586 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 dcd_rB $abc$24881$new_n4258 $abc$24881$auto$rtlil.cc:2693:MuxGate$23588 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n6614 $abc$24881$new_n4028 dcd_rA $abc$24881$auto$rtlil.cc:2693:MuxGate$23590 -000 1 -001 1 -011 1 -.names $abc$24881$new_n6620 $abc$24881$new_n6615 $abc$24881$new_n6617 $abc$24881$new_n6616 $abc$24881$new_n6614 -1100 1 -.names $abc$24881$new_n4028 $abc$24881$new_n4269 $abc$24881$new_n4261 $abc$24881$new_n4270 $abc$24881$new_n6615 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -.names $abc$24881$new_n4260 $abc$24881$new_n4282 $abc$24881$new_n6616 -10 1 -.names $abc$24881$new_n6618 $abc$24881$new_n4281 $abc$24881$new_n6619 $abc$24881$new_n4267 $abc$24881$new_n6617 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4268 $abc$24881$new_n4267 $abc$24881$new_n6618 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -.names i_pf_instruction[25] $abc$24881$new_n4266 $abc$24881$new_n4282 $abc$24881$new_n4268 $abc$24881$new_n6619 -1111 1 -.names $abc$24881$new_n6622 $abc$24881$new_n6621 $abc$24881$new_n6620 -00 1 -.names $abc$24881$new_n4276 $abc$24881$new_n4277 $abc$24881$new_n4273 $abc$24881$new_n4267 $abc$24881$new_n6621 -1000 1 -1001 1 -1010 1 -.names i_pf_instruction[25] $abc$24881$new_n4265 $abc$24881$new_n4266 $abc$24881$new_n4267 $abc$24881$new_n4273 $abc$24881$new_n6622 -11100 1 -.names $abc$24881$new_n4028 dcd_wR $abc$24881$new_n6615 $abc$24881$new_n4275 $abc$24881$new_n6616 $abc$24881$auto$rtlil.cc:2693:MuxGate$23592 -00100 1 -01100 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_lock $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n4287 $abc$24881$auto$rtlil.cc:2693:MuxGate$23594 -00110 1 -01110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.o_DV $abc$24881$new_n6622 $abc$24881$auto$rtlil.cc:2693:MuxGate$23596 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n4028 dcd_M $abc$24881$new_n4260 $abc$24881$auto$rtlil.cc:2693:MuxGate$23598 -001 1 -011 1 -110 1 -111 1 -.names dcd_ALU $abc$24881$new_n4028 $abc$24881$new_n6615 $abc$24881$new_n6628 $abc$24881$new_n6618 $abc$24881$auto$rtlil.cc:2693:MuxGate$23600 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n4271 $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n6628 -000 1 -001 1 -011 1 -.names $abc$24881$new_n4028 dcd_opn[3] $abc$24881$new_n4269 $abc$24881$auto$rtlil.cc:2693:MuxGate$23604 -000 1 -010 1 -110 1 -111 1 -.names $abc$24881$new_n6615 $abc$24881$new_n4028 dcd_wF $abc$24881$new_n6633 $abc$24881$new_n6631 $abc$24881$auto$rtlil.cc:2693:MuxGate$23606 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11011 1 -11111 1 -.names $abc$24881$new_n4028 $abc$24881$new_n4274 $abc$24881$new_n4293 $abc$24881$new_n6632 $abc$24881$new_n6631 -0000 1 -0001 1 -0010 1 -0011 1 -0111 1 -.names $abc$24881$new_n4289 $abc$24881$new_n4291 $abc$24881$new_n6632 -10 1 -.names $abc$24881$new_n6620 $abc$24881$new_n6634 $abc$24881$new_n6617 $abc$24881$new_n6633 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n4277 $abc$24881$new_n4267 $abc$24881$new_n4268 $abc$24881$new_n4269 $abc$24881$new_n6634 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0111 1 -.names $abc$24881$new_n6631 dcd_F[3] $abc$24881$new_n4028 $abc$24881$auto$rtlil.cc:2693:MuxGate$23608 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n6637 dcd_zI $abc$24881$new_n4028 $abc$24881$auto$rtlil.cc:2693:MuxGate$23610 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n5459 $abc$24881$new_n6639 $abc$24881$new_n6638 $abc$24881$new_n5438 $abc$24881$new_n6637 -1111 1 -.names $abc$24881$new_n4266 $abc$24881$new_n5449 $abc$24881$new_n5447 $abc$24881$new_n5445 $abc$24881$new_n6610 $abc$24881$new_n6638 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11111 1 -.names $abc$24881$new_n6640 $abc$24881$new_n5457 $abc$24881$new_n5454 $abc$24881$new_n5451 $abc$24881$new_n5461 $abc$24881$new_n6639 -11110 1 -.names $abc$24881$new_n6641 $abc$24881$new_n4266 i_pf_instruction[7] i_pf_instruction[8] $abc$24881$new_n6640 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names $abc$24881$new_n6642 $abc$24881$new_n5477 $abc$24881$new_n5474 $abc$24881$new_n5472 $abc$24881$new_n5469 $abc$24881$new_n6641 -11100 1 -.names $abc$24881$new_n6643 $abc$24881$new_n6644 $abc$24881$new_n4266 i_pf_instruction[2] $abc$24881$new_n4283 $abc$24881$new_n6642 -11001 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4266 i_pf_instruction[0] i_pf_instruction[1] $abc$24881$new_n5455 $abc$24881$new_n5442 $abc$24881$new_n6643 -00011 1 -00111 1 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -.names $abc$24881$new_n4266 i_pf_instruction[11] i_pf_instruction[12] i_pf_instruction[9] i_pf_instruction[10] $abc$24881$new_n6644 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -.names $abc$24881$new_n4028 dcd_Bcc $abc$24881$new_n4292 $abc$24881$new_n4257 $abc$24881$auto$rtlil.cc:2693:MuxGate$23612 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4028 dcd_Acc $abc$24881$new_n4302 $abc$24881$new_n4301 $abc$24881$auto$rtlil.cc:2693:MuxGate$23614 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4028 dcd_break $abc$24881$new_n4273 $abc$24881$new_n4275 $abc$24881$new_n4287 $abc$24881$auto$rtlil.cc:2693:MuxGate$23616 -00111 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names alu_ce $abc$24881$new_n6649 doalu.set_ovfl $abc$24881$new_n6657 $abc$24881$new_n6658 $abc$24881$auto$rtlil.cc:2693:MuxGate$23618 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11110 1 -.names $abc$24881$new_n6650 $abc$24881$new_n6653 $abc$24881$new_n6655 $abc$24881$new_n6649 -000 1 -010 1 -100 1 -101 1 -.names o_mem_data[31] o_mem_addr[31] $abc$24881$new_n6650 -01 1 -10 1 -.names $abc$24881$new_n5151 $abc$24881$new_n6568 r_op_Bv[31] o_mem_addr[31] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3692 $abc$24881$new_n6568 r_op_Av[31] o_mem_data[31] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n6654 DIVIDE.thedivide.i_signed $abc$24881$new_n6653 -10 1 -.names FWD_OPERATION.r_op_opn[3] o_mem_op[1] o_mem_op[2] $abc$24881$new_n6654 -000 1 -.names $abc$24881$new_n6656 DIVIDE.thedivide.i_signed $abc$24881$new_n6655 -10 1 -.names o_mem_op[1] FWD_OPERATION.r_op_opn[3] o_mem_op[2] $abc$24881$new_n6656 -100 1 -.names o_mem_op[2] FWD_OPERATION.r_op_opn[3] o_mem_op[1] DIVIDE.thedivide.i_signed $abc$24881$new_n6657 -1001 1 -1010 1 -1011 1 -.names o_mem_op[2] DIVIDE.thedivide.i_signed o_mem_op[1] FWD_OPERATION.r_op_opn[3] $abc$24881$new_n6658 -1110 1 -.names alu_ce $abc$24881$new_n6649 doalu.keep_sgn_on_ovfl $abc$24881$auto$rtlil.cc:2693:MuxGate$23620 -001 1 -011 1 -100 1 -101 1 -.names o_mem_addr[28] o_mem_data[28] o_mem_addr[29] o_mem_data[29] $abc$24881$new_n6663 $abc$24881$new_n6662 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names o_mem_addr[26] o_mem_data[26] o_mem_addr[27] o_mem_data[27] $abc$24881$new_n6664 $abc$24881$new_n6663 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[24] o_mem_data[24] o_mem_addr[25] o_mem_data[25] $abc$24881$new_n6665 $abc$24881$new_n6664 -00110 1 -00111 1 -01011 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[22] o_mem_data[22] o_mem_addr[23] o_mem_data[23] $abc$24881$new_n6666 $abc$24881$new_n6665 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[20] o_mem_data[20] o_mem_addr[21] o_mem_data[21] $abc$24881$new_n6667 $abc$24881$new_n6666 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names o_mem_addr[18] o_mem_data[18] o_mem_addr[19] o_mem_data[19] $abc$24881$new_n6668 $abc$24881$new_n6667 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[16] o_mem_data[16] o_mem_addr[17] o_mem_data[17] $abc$24881$new_n6669 $abc$24881$new_n6668 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names o_mem_addr[14] o_mem_data[14] o_mem_addr[15] o_mem_data[15] $abc$24881$new_n6670 $abc$24881$new_n6669 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[12] o_mem_data[12] o_mem_addr[13] o_mem_data[13] $abc$24881$new_n6671 $abc$24881$new_n6670 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01100 1 -10000 1 -10001 1 -10010 1 -10100 1 -11000 1 -11001 1 -.names o_mem_addr[10] o_mem_data[10] o_mem_addr[11] o_mem_data[11] $abc$24881$new_n6672 $abc$24881$new_n6671 -00110 1 -00111 1 -01010 1 -01100 1 -01110 1 -01111 1 -10010 1 -10100 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[8] o_mem_data[8] o_mem_addr[9] o_mem_data[9] $abc$24881$new_n6673 $abc$24881$new_n6672 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names o_mem_addr[6] o_mem_data[6] o_mem_addr[7] o_mem_data[7] $abc$24881$new_n6674 $abc$24881$new_n6673 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names o_mem_addr[4] o_mem_data[4] o_mem_addr[5] o_mem_data[5] $abc$24881$new_n9661 $abc$24881$new_n6674 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11000 1 -11001 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3692 $abc$24881$new_n3853 r_op_Av[2] r_op_Bv[2] $abc$24881$new_n6678 -00011 1 -00111 1 -01001 1 -01011 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5151 $abc$24881$new_n3692 r_op_Av[2] r_op_Bv[2] $abc$24881$new_n3853 $abc$24881$new_n6679 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01011 1 -01100 1 -01111 1 -10000 1 -10010 1 -10101 1 -10111 1 -.names o_mem_addr[0] o_mem_data[0] o_mem_addr[1] o_mem_data[1] $abc$24881$new_n6680 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1100 1 -.names o_mem_addr[30] o_mem_data[30] $abc$24881$new_n6682 -11 1 -.names o_mem_addr[30] o_mem_data[30] $abc$24881$new_n6683 -01 1 -10 1 -.names $abc$24881$new_n6723 $abc$24881$new_n6788 $abc$24881$new_n6686 $abc$24881$new_n6650 $abc$24881$new_n6685 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -.names $abc$24881$new_n6722 $abc$24881$new_n6683 $abc$24881$new_n6687 $abc$24881$new_n6686 -000 1 -.names $abc$24881$new_n6721 $abc$24881$new_n6688 o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6720 $abc$24881$new_n6687 -00100 1 -01000 1 -01100 1 -01110 1 -10000 1 -10100 1 -10110 1 -11000 1 -11100 1 -11110 1 -.names $abc$24881$new_n6719 $abc$24881$new_n6689 o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6718 $abc$24881$new_n6688 -00100 1 -01000 1 -01100 1 -01110 1 -10000 1 -10100 1 -10110 1 -11000 1 -11100 1 -11110 1 -.names $abc$24881$new_n6717 $abc$24881$new_n6690 o_mem_addr[24] o_mem_data[24] $abc$24881$new_n6716 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o_mem_data[23] $abc$24881$new_n6760 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[0] o_mem_data[26] o_mem_data[25] $abc$24881$new_n6761 -000 1 -010 1 -100 1 -101 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6763 o_mem_data[28] o_mem_data[27] $abc$24881$new_n6762 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[0] o_mem_data[30] o_mem_data[29] $abc$24881$new_n6763 -000 1 -010 1 -100 1 -101 1 -.names o_mem_addr[2] $abc$24881$new_n6765 $abc$24881$new_n6767 $abc$24881$new_n6764 -010 1 -011 1 -101 1 -111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6766 o_mem_data[10] o_mem_data[9] $abc$24881$new_n6765 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 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-1011 1 -1111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4085 $abc$24881$auto$rtlil.cc:2693:MuxGate$23628 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$new_n6794 $abc$24881$auto$rtlil.cc:2693:MuxGate$23630 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6796 $abc$24881$new_n6795 $abc$24881$new_n6798 instruction_decoder.o_dcdB[3] $abc$24881$new_n4284 $abc$24881$new_n6794 -11100 1 -11111 1 -.names $abc$24881$new_n4260 $abc$24881$new_n4258 $abc$24881$new_n6795 -10 1 -.names $abc$24881$new_n6797 dcd_opn[0] $abc$24881$new_n4282 instruction_decoder.o_dcdB[2] $abc$24881$new_n4288 $abc$24881$new_n6796 -10100 1 -10111 1 -11000 1 -11011 1 -.names instruction_decoder.GEN_OPIPE.r_insn_is_pipeable $abc$24881$new_n4085 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6797 -101 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[1] $abc$24881$new_n4290 $abc$24881$new_n4292 $abc$24881$new_n6798 -0011 1 -0101 1 -1010 1 -1100 1 -.names $abc$24881$new_n6795 $abc$24881$new_n4277 $abc$24881$new_n4284 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n6801 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n4085 $abc$24881$flatten\instruction_decoder.$procmux$2071_Y $abc$24881$auto$rtlil.cc:2693:MuxGate$23634 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[30] $abc$24881$new_n6806 i_pf_instruction[21] i_pf_instruction[25] $abc$24881$flatten\instruction_decoder.$procmux$2071_Y -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction[29] $abc$24881$new_n6807 i_pf_instruction[20] i_pf_instruction[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6806 -11000 1 -.names $abc$24881$new_n6808 i_pf_instruction[23] i_pf_instruction[28] i_pf_instruction[27] i_pf_instruction[26] $abc$24881$new_n6807 -11110 1 -.names i_pf_instruction[31] i_pf_instruction[18] i_pf_instruction[19] i_pf_instruction[22] $abc$24881$new_n6808 -0000 1 -.names $abc$24881$new_n6475 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb $abc$24881$new_n6810 $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$auto$rtlil.cc:2693:MuxGate$23636 -00001 1 -00011 1 -00101 1 -00111 1 -01011 1 -01100 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6820 $abc$24881$new_n4277 $abc$24881$new_n4286 $abc$24881$new_n6811 $abc$24881$new_n6818 $abc$24881$new_n6810 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6812 $abc$24881$new_n4293 $abc$24881$new_n6816 $abc$24881$new_n6814 $abc$24881$new_n5455 $abc$24881$new_n6811 -11110 1 -.names i_pf_instruction[17] $abc$24881$new_n6632 $abc$24881$new_n6813 $abc$24881$new_n4085 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6812 -11110 1 -.names i_pf_instruction[14] i_pf_instruction[31] i_pf_instruction[11] i_pf_instruction[12] $abc$24881$new_n6813 -1000 1 -.names i_pf_instruction[15] i_pf_instruction[18] $abc$24881$new_n6815 i_pf_instruction[0] i_pf_instruction[1] $abc$24881$new_n6814 -11100 1 -.names i_pf_instruction[2] i_pf_instruction[3] i_pf_instruction[4] i_pf_instruction[5] $abc$24881$new_n6815 -0000 1 -.names $abc$24881$new_n6817 $abc$24881$new_n4287 i_pf_instruction[10] i_pf_instruction[13] $abc$24881$new_n4273 $abc$24881$new_n6816 -11000 1 -.names i_pf_instruction[6] i_pf_instruction[7] i_pf_instruction[8] i_pf_instruction[9] $abc$24881$new_n6817 -0000 1 -.names $abc$24881$new_n4291 $abc$24881$new_n6819 $abc$24881$new_n4283 $abc$24881$new_n4289 $abc$24881$new_n4293 $abc$24881$new_n6818 -11100 1 -.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[7] $abc$24881$new_n5442 $abc$24881$new_n5455 $abc$24881$new_n4287 $abc$24881$new_n6819 -11110 1 -.names $abc$24881$new_n4267 $abc$24881$new_n4302 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_valid $abc$24881$new_n6820 -10000 1 -10001 1 -10010 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction[31] $abc$24881$new_n4085 i_pf_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23638 -00110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_valid o_pf_ready instruction_decoder.o_illegal $abc$24881$new_n6825 $abc$24881$new_n6823 $abc$24881$auto$rtlil.cc:2693:MuxGate$23640 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n4277 $abc$24881$new_n6622 $abc$24881$new_n4269 $abc$24881$new_n6824 $abc$24881$new_n4261 $abc$24881$new_n6823 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n4270 $abc$24881$new_n4262 $abc$24881$new_n4277 $abc$24881$new_n4282 $abc$24881$new_n4268 $abc$24881$new_n6824 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_illegal $abc$24881$new_n6621 $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n4287 $abc$24881$new_n6825 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -.names $abc$24881$new_n6827 o_mem_addr[31] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23642 -000 1 -001 1 -010 1 -011 1 -110 1 -.names DIVIDE.thedivide.r_divisor[31] DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign $abc$24881$new_n6828 DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n6827 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n5512 DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n6828 -10 1 -.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n5529 $abc$24881$new_n6828 o_mem_addr[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23644 -00001 1 -00011 1 -01001 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_z $abc$24881$new_n3867 $abc$24881$new_n3829 $abc$24881$auto$rtlil.cc:2693:MuxGate$23646 -100 1 -110 1 -111 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor DIVIDE.thedivide.last_bit DIVIDE.thedivide.o_valid $abc$24881$auto$rtlil.cc:2693:MuxGate$23648 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6834 $abc$24881$new_n5383 $abc$24881$auto$rtlil.cc:2693:MuxGate$23650 -01 1 -10 1 -11 1 -.names DIVIDE.thedivide.o_busy DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor DIVIDE.thedivide.last_bit DIVIDE.thedivide.r_sign $abc$24881$new_n6834 -11000 1 -11001 1 -11011 1 -.names $abc$24881$new_n5383 DIVIDE.thedivide.r_busy DIVIDE.thedivide.last_bit DIVIDE.thedivide.zero_divisor $abc$24881$auto$rtlil.cc:2693:MuxGate$23652 -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n6837 GEN_ALU_PC.r_alu_pc[31] SET_USER_PC.r_upc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23654 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names wr_index[1] wr_index[0] doalu.n i_mem_result[31] dbg_val[31] $abc$24881$new_n6837 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names SET_GIE.r_gie $abc$24881$new_n3957 $abc$24881$new_n6840 $abc$24881$new_n6839 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23656 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names wr_index[0] wr_index[1] $abc$24881$new_n3860 i_mem_result[1] $abc$24881$new_n6839 -0010 1 -0011 1 -0110 1 -0111 1 -1000 1 -1010 1 -1110 1 -1111 1 -.names r_alu_pc_valid DIVIDE.thedivide.o_busy GEN_UHALT_PHASE.r_uhalt_phase GEN_ALU_PHASE.r_alu_phase $abc$24881$new_n6840 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names o_i_count SET_GIE.r_gie GEN_IHALT_PHASE.r_ihalt_phase GEN_ALU_PHASE.r_alu_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23658 -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n6843 DIVERR.USER_DIVERR.r_udiv_err_flag $abc$24881$new_n4001 DIVIDE.thedivide.o_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23660 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4079 SET_GIE.r_gie dbgv $abc$24881$new_n6843 -100 1 -101 1 -111 1 -.names $abc$24881$new_n6845 DIVERR.r_idiv_err_flag $abc$24881$new_n4001 DIVIDE.thedivide.o_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23662 -00010 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names dbgv $abc$24881$new_n3697 $abc$24881$new_n3694 $abc$24881$new_n4036 $abc$24881$new_n6845 -1111 1 -.names $abc$24881$new_n6843 SET_USER_BUSERR.r_ubus_err_flag $abc$24881$new_n4003 i_bus_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23664 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n6843 SET_USER_ILLEGAL_INSN.r_ill_err_u $abc$24881$new_n4007 SET_ALU_ILLEGAL.r_alu_illegal $abc$24881$new_n4402 $abc$24881$auto$rtlil.cc:2693:MuxGate$23666 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names SET_TRAP_N_UBREAK.r_ubreak GEN_PENDING_BREAK.r_break_pending $abc$24881$new_n4077 $abc$24881$new_n6843 $abc$24881$new_n4009 $abc$24881$auto$rtlil.cc:2693:MuxGate$23668 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names SET_TRAP_N_UBREAK.r_trap SET_GIE.r_gie $abc$24881$new_n6850 dbgv $abc$24881$new_n4005 $abc$24881$auto$rtlil.cc:2693:MuxGate$23670 -01000 1 -01001 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4079 SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n6850 -000 1 -001 1 -010 1 -011 1 -110 1 -.names SET_GIE.r_gie $abc$24881$new_n4082 $abc$24881$auto$rtlil.cc:2693:MuxGate$23672 -01 1 -10 1 -11 1 -.names $abc$24881$new_n6853 op_illegal $abc$24881$new_n4031 $abc$24881$auto$rtlil.cc:2693:MuxGate$23674 -000 1 -001 1 -010 1 -011 1 -111 1 -.names i_interrupt GEN_PENDING_BREAK.r_break_pending GEN_PENDING_INTERRUPT.r_pending_interrupt $abc$24881$new_n6854 $abc$24881$new_n6853 -0000 1 -.names user_step GEN_PENDING_INTERRUPT.r_user_stepped $abc$24881$new_n3959 $abc$24881$new_n6855 $abc$24881$new_n6854 -1100 1 -1101 1 -1111 1 -.names i_mem_busy DIVIDE.thedivide.o_busy $abc$24881$new_n6855 -00 1 -.names GEN_PENDING_INTERRUPT.r_user_stepped $abc$24881$new_n6857 $abc$24881$auto$rtlil.cc:2693:MuxGate$23676 -01 1 -10 1 -11 1 -.names GEN_OPLOCK.r_op_lock OPT_CIS_OP_PHASE.r_op_phase BUSLOCK.r_bus_lock[1] $abc$24881$new_n4030 $abc$24881$new_n6857 -0000 1 -.names $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y SET_GIE.r_gie $abc$24881$new_n4013 sleep $abc$24881$new_n6859 $abc$24881$auto$rtlil.cc:2693:MuxGate$23678 -00010 1 -00011 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4015 i_interrupt SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n6859 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -.names GEN_PENDING_BREAK.r_break_pending $abc$24881$new_n3959 $abc$24881$new_n6855 r_op_break $abc$24881$new_n4046 $abc$24881$auto$rtlil.cc:2693:MuxGate$23680 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names BUSLOCK.r_bus_lock[1] BUSLOCK.r_bus_lock[0] $abc$24881$new_n4030 GEN_OPLOCK.r_op_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23682 -0001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n6863 GEN_OPLOCK.r_op_lock $abc$24881$new_n4031 o_bus_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23684 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names BUSLOCK.r_prelock_stall instruction_decoder.r_valid op_valid i_pf_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6863 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -.names $abc$24881$new_n4030 GEN_ALU_PHASE.r_alu_phase OPT_CIS_OP_PHASE.r_op_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23686 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_CIS_PHASE.r_phase OPT_CIS_OP_PHASE.r_op_phase dcd_Apc dcd_wR $abc$24881$auto$rtlil.cc:2693:MuxGate$23688 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n5066 GEN_OPLOCK.r_op_lock instruction_decoder.o_lock instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23690 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$24881$new_n5066 $abc$24881$new_n6868 op_valid_mem instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$auto$rtlil.cc:2693:MuxGate$23692 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names GEN_OP_PIPE.r_op_pipe mem_ce $abc$24881$new_n5152 $abc$24881$new_n5155 $abc$24881$new_n6868 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n6870 $abc$24881$new_n4030 i_mem_rdbusy GEN_OP_STALL.r_pending_sreg_write $abc$24881$auto$rtlil.cc:2693:MuxGate$23694 -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] $abc$24881$new_n6871 $abc$24881$new_n4066 $abc$24881$new_n6870 -11110 1 -.names $abc$24881$new_n5375 GEN_OP_WR.r_op_wR op_illegal $abc$24881$new_n6871 -110 1 -.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n6837 GEN_ALU_PC.r_alu_pc[31] ipc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23696 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n6845 ibus_err_flag $abc$24881$new_n4003 i_bus_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23698 -00010 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names ill_err_i $abc$24881$new_n6845 $abc$24881$new_n6875 $abc$24881$new_n4007 $abc$24881$auto$rtlil.cc:2693:MuxGate$23700 -0010 1 -0011 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1110 1 -.names SET_ALU_ILLEGAL.r_alu_illegal new_pc SET_GIE.r_gie $abc$24881$new_n6875 -100 1 -.names $abc$24881$new_n4079 SET_GIE.r_gie user_step $abc$24881$new_n4011 $abc$24881$auto$rtlil.cc:2693:MuxGate$23702 -0010 1 -0011 1 -0110 1 -0111 1 -1000 1 -1010 1 -1110 1 -1111 1 -.names $abc$24881$new_n4083 $abc$24881$new_n4009 break_en $abc$24881$auto$rtlil.cc:2693:MuxGate$23704 -001 1 -011 1 -100 1 -101 1 -.names OPT_CIS_OP_PHASE.r_op_phase $abc$24881$new_n4031 DIVIDE.thedivide.o_busy r_alu_pc_valid new_pc $abc$24881$auto$rtlil.cc:2693:MuxGate$23706 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$24881$new_n4030 wr_index[1] op_valid_div op_valid_alu $abc$24881$auto$rtlil.cc:2693:MuxGate$23708 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n6881 op_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23710 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_illegal instruction_decoder.r_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6881 -1100 1 -.names $abc$24881$new_n5066 r_op_break dcd_break instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23712 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11110 1 -.names $abc$24881$new_n6884 op_valid $abc$24881$new_n4030 $abc$24881$auto$rtlil.cc:2693:MuxGate$23714 -011 1 -100 1 -101 1 -110 1 -111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch instruction_decoder.r_valid new_pc instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6884 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6886 op_valid_mem $abc$24881$new_n6887 dcd_M instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23716 -00110 1 -01110 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4030 $abc$24881$new_n5066 $abc$24881$new_n6886 -10 1 -.names $abc$24881$new_n5066 instruction_decoder.r_valid new_pc instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6887 -11000 1 -.names $abc$24881$new_n6887 op_valid_alu $abc$24881$new_n6886 dcd_ALU instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23718 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6886 op_valid_div $abc$24881$new_n6887 instruction_decoder.o_DV instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23720 -00110 1 -01110 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6475 instruction_decoder.o_pc[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6891 $abc$24881$new_n6892 $abc$24881$auto$rtlil.cc:2693:MuxGate$23722 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names instruction_decoder.o_pc[30] $abc$24881$new_n6441 $abc$24881$new_n6891 -11 1 -.names i_pf_instruction_pc[31] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[30] $abc$24881$new_n6460 i_pf_instruction[31] $abc$24881$new_n6892 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] $abc$24881$new_n6894 $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23724 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[31] i_pf_instruction[17] i_pf_instruction_pc[30] $abc$24881$new_n6365 $abc$24881$new_n6894 -0000 1 -0001 1 -0011 1 -0100 1 -0110 1 -0111 1 -1010 1 -1101 1 -.names $abc$24881$new_n5066 SET_OP_PC.r_op_pc[1] instruction_decoder.o_pc[1] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23728 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names $abc$24881$new_n3829 $abc$24881$new_n6897 DIVIDE.thedivide.r_dividend[62] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$23732 -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names DIVIDE.thedivide.r_dividend[61] DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n3869 DIVIDE.thedivide.r_dividend[62] DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n6897 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10010 1 -10011 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n3829 $abc$24881$new_n6899 DIVIDE.thedivide.r_dividend[32] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$23734 -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[0] $abc$24881$new_n3867 $abc$24881$new_n6899 -000 1 -001 1 -011 1 -110 1 -.names $abc$24881$new_n6901 ipc[31] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$23736 -000 1 -001 1 -010 1 -011 1 -111 1 -.names $abc$24881$new_n6902 $abc$24881$new_n6837 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[31] $abc$24881$new_n6901 -00000 1 -00001 1 -00010 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] $abc$24881$new_n6903 $abc$24881$new_n6904 $abc$24881$new_n6902 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] $abc$24881$new_n4106 $abc$24881$new_n6903 -111 1 -.names $abc$24881$new_n4024 pf_pc[31] $abc$24881$new_n6905 SET_USER_PC.r_upc[31] $abc$24881$new_n4087 $abc$24881$new_n6904 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names pf_pc[28] pf_pc[29] pf_pc[30] $abc$24881$new_n4090 $abc$24881$new_n6905 -1111 1 -.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[31] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] instruction_decoder.o_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23738 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[31] SET_OP_PC.r_op_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23740 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5407 $abc$24881$new_n6909 o_mem_lock_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23742 -001 1 -011 1 -110 1 -111 1 -.names SET_OP_PC.r_op_pc[31] $abc$24881$new_n5393 SET_OP_PC.r_op_pc[29] SET_OP_PC.r_op_pc[30] $abc$24881$new_n6909 -0100 1 -1000 1 -1001 1 -1010 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names o_clear_icache DIVIDE.thedivide.i_reset instruction_decoder.i_reset -01 1 -10 1 -11 1 -.names new_pc i_reset DIVIDE.thedivide.i_reset -01 1 -10 1 -11 1 -.names $abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y o_pf_ready $abc$24881$new_n4085 i_pf_illegal $abc$24881$auto$opt_dff.cc:253:combine_resets$3478 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.i_reset $abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y -01 1 -10 1 -11 1 -.names $abc$24881$new_n4028 dcd_F[1] $abc$24881$new_n4291 $abc$24881$new_n4274 $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] $abc$24881$auto$opt_dff.cc:253:combine_resets$4528 -00 1 -01 1 -11 1 -.names $abc$24881$new_n4028 dcd_F[2] $abc$24881$new_n4274 $abc$24881$new_n4289 $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] -0010 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4085 instruction_decoder.i_reset $abc$24881$new_n4028 $abc$24881$auto$opt_dff.cc:253:combine_resets$3474 -000 1 -001 1 -010 1 -011 1 -101 1 -110 1 -111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3460 -00 1 -01 1 -11 1 -.names $abc$24881$new_n3829 DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3455 -00 1 -01 1 -11 1 -.names $abc$24881$new_n4078 i_reset $abc$24881$new_n4046 $abc$24881$new_n4402 $abc$24881$auto$opt_dff.cc:253:combine_resets$3429 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n4031 new_pc $abc$24881$auto$opt_dff.cc:253:combine_resets$3420 -00 1 -01 1 -11 1 -.names $abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y $abc$24881$new_n4035 $abc$24881$auto$opt_dff.cc:253:combine_resets$3407 -01 1 -10 1 -11 1 -.names r_halted i_reset $abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y -00 1 -01 1 -11 1 -.names $abc$24881$new_n4105 i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3404 -00 1 -01 1 -11 1 -.names $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3389 -00 1 -01 1 -11 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor $abc$24881$auto$simplemap.cc:240:simplemap_eqne$9293[0] -11 1 -.names alu_ce i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3485 -00 1 -01 1 -11 1 -.names DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[4] DIVIDE.thedivide.r_bit[0] $abc$24881$flatten\DIVIDE.thedivide.$eq$./benchmark/div.v:248$1635_Y -11110 1 -.names $abc$24881$new_n6931 $abc$24881$new_n6930 $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y -11 1 -.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n6930 -11 1 -.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n6931 -11 1 -.names $abc$24881$new_n6933 DIVIDE.thedivide.r_dividend[62] DIVIDE.thedivide.r_divisor[31] $abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:372$1666_Y -100 1 -111 1 -.names $abc$24881$new_n6934 $abc$24881$new_n6949 DIVIDE.thedivide.r_divisor[29] DIVIDE.thedivide.r_dividend[60] $abc$24881$new_n6933 -1100 1 -1111 1 -.names $abc$24881$new_n6935 DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3887 $abc$24881$new_n6934 -1000 1 -1110 1 -.names $abc$24881$new_n6936 DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3892 $abc$24881$new_n6935 -1000 1 -1110 1 -.names $abc$24881$new_n6937 DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3897 $abc$24881$new_n6936 -1000 1 -1110 1 -.names $abc$24881$new_n6938 DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3902 $abc$24881$new_n6937 -1000 1 -1110 1 -.names $abc$24881$new_n6939 DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3907 $abc$24881$new_n6938 -1000 1 -1110 1 -.names $abc$24881$new_n9670 DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3912 $abc$24881$new_n6939 -1000 1 -1110 1 -.names $abc$24881$new_n6944 DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3937 $abc$24881$new_n6943 -1000 1 -1110 1 -.names $abc$24881$new_n6945 DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3942 $abc$24881$new_n6944 -1000 1 -1110 1 -.names $abc$24881$new_n6946 DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3947 $abc$24881$new_n6945 -1000 1 -1110 1 -.names $abc$24881$new_n6947 $abc$24881$new_n3953 $abc$24881$new_n3950 $abc$24881$new_n6946 -100 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n6947 -10000 1 -10011 1 -11100 1 -11111 1 -.names DIVIDE.thedivide.r_divisor[30] DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n6949 -00 1 -11 1 -.names DIVIDE.thedivide.i_signed DIVIDE.thedivide.i_wr o_mem_addr[31] o_mem_data[31] $abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:263$1639_Y -1101 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.o_valid DIVIDE.thedivide.i_reset $abc$24881$flatten\DIVIDE.thedivide.$logic_or$./benchmark/div.v:189$1625_Y -01 1 -10 1 -11 1 -.names $abc$24881$new_n4033 $abc$24881$new_n4029 o_op_stall -10 1 -.names $abc$24881$new_n4033 i_pf_valid o_pf_stall -10 1 -.names i_halt new_pc $abc$24881$logic_or$./benchmark/zipcore.v:728$452_Y -01 1 -10 1 -11 1 -.names $abc$24881$new_n5375 op_wF op_illegal $abc$24881$logic_and$./benchmark/zipcore.v:1613$573_Y -110 1 -.names op_valid new_pc $abc$24881$logic_or$./benchmark/zipcore.v:2501$630_Y -00 1 -01 1 -11 1 -.names GEN_CLOCK_GATE.r_clken i_clear_cache i_dbg_we $abc$24881$new_n6958 o_clken -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names i_halt sleep i_interrupt $abc$24881$new_n6958 -000 1 -001 1 -011 1 -.names SET_GIE.r_gie user_step i_reset $abc$24881$logic_or$./benchmark/zipcore.v:2741$689_Y -000 1 -001 1 -010 1 -011 1 -100 1 -101 1 -111 1 -.names i_reset $abc$24881$new_n4082 $abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y -01 1 -10 1 -11 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3863 regset[15][0] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[0] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3859 regset[15][1] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[1] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3853 regset[15][2] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[2] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3848 regset[15][3] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[3] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3843 regset[15][4] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[4] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3838 regset[15][5] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[5] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3832 regset[15][6] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[6] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3825 regset[15][7] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[7] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3820 regset[15][8] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[8] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3815 regset[15][9] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[9] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3810 regset[15][10] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[10] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3805 regset[15][11] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[11] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3800 regset[15][12] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[12] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3795 regset[15][13] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[13] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3790 regset[15][14] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[14] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3784 regset[15][15] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[15] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3779 regset[15][16] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[16] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3774 regset[15][17] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[17] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3769 regset[15][18] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[18] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3763 regset[15][19] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[19] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3757 regset[15][20] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[20] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n5333 $abc$24881$new_n3752 regset[15][21] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[21] -001 1 -011 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$abc$24881$new_n7344 $abc$24881$new_n3714 regset[16][28] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[28] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7344 $abc$24881$new_n3708 regset[16][29] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[29] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7344 $abc$24881$new_n3702 regset[16][30] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[30] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7344 $abc$24881$new_n6568 regset[16][31] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[31] -001 1 -011 1 -100 1 -101 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n7377 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2314_Y -0001 1 -0011 1 -0101 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor $abc$24881$new_n7377 -110 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3863 regset[2][0] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[0] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3701 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n7143 $abc$24881$new_n7379 -1111 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3859 regset[2][1] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[1] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3853 regset[2][2] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[2] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3848 regset[2][3] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[3] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3843 regset[2][4] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[4] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3838 regset[2][5] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[5] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3832 regset[2][6] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[6] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3825 regset[2][7] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[7] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3820 regset[2][8] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[8] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3815 regset[2][9] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[9] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3810 regset[2][10] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[10] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3805 regset[2][11] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[11] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3800 regset[2][12] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[12] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3795 regset[2][13] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[13] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3790 regset[2][14] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[14] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3784 regset[2][15] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[15] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3779 regset[2][16] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[16] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3774 regset[2][17] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[17] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3769 regset[2][18] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[18] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3763 regset[2][19] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[19] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3757 regset[2][20] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[20] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3752 regset[2][21] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[21] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3747 regset[2][22] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[22] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3741 regset[2][23] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[23] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3735 regset[2][24] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[24] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3730 regset[2][25] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[25] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3725 regset[2][26] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[26] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3719 regset[2][27] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[27] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3714 regset[2][28] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[28] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3708 regset[2][29] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[29] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n3702 regset[2][30] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[30] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7379 $abc$24881$new_n6568 regset[2][31] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[31] -001 1 -011 1 -100 1 -101 1 -.names DIVIDE.thedivide.r_busy $abc$24881$new_n3867 DIVIDE.thedivide.o_quotient[0] DIVIDE.thedivide.r_sign $abc$24881$flatten\DIVIDE.thedivide.$procmux$2305_Y -0011 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names DIVIDE.thedivide.o_quotient[0] DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.r_busy $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[0] -0110 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[2] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.o_quotient[0] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[1] -00110 1 -00111 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7415 DIVIDE.thedivide.o_quotient[2] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[2] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names DIVIDE.thedivide.o_quotient[2] DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.o_quotient[0] $abc$24881$new_n7415 -000 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[4] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7415 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[3] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7418 DIVIDE.thedivide.o_quotient[4] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[4] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7415 DIVIDE.thedivide.o_quotient[4] DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7418 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[6] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7418 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[5] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7421 DIVIDE.thedivide.o_quotient[6] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[6] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7418 DIVIDE.thedivide.o_quotient[6] DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7421 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[8] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7421 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[7] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7424 DIVIDE.thedivide.o_quotient[8] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[8] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7421 DIVIDE.thedivide.o_quotient[8] DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7424 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[10] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7424 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[9] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7427 DIVIDE.thedivide.o_quotient[10] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[10] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7424 DIVIDE.thedivide.o_quotient[10] DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7427 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[12] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7427 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[11] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7430 DIVIDE.thedivide.o_quotient[12] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[12] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7427 DIVIDE.thedivide.o_quotient[12] DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7430 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[14] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7430 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[13] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7433 DIVIDE.thedivide.o_quotient[14] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[14] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7430 DIVIDE.thedivide.o_quotient[14] DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7433 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[16] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7433 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[15] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[17] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[16] $abc$24881$new_n7436 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[16] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n7433 DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7436 -10 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[18] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[17] $abc$24881$new_n7438 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[17] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n7436 DIVIDE.thedivide.o_quotient[16] $abc$24881$new_n7438 -10 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7440 DIVIDE.thedivide.o_quotient[18] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[18] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7438 DIVIDE.thedivide.o_quotient[18] DIVIDE.thedivide.o_quotient[17] $abc$24881$new_n7440 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[20] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7440 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[19] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[21] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[20] $abc$24881$new_n7443 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[20] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names $abc$24881$new_n7440 DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7443 -10 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7445 DIVIDE.thedivide.o_quotient[21] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[21] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7443 DIVIDE.thedivide.o_quotient[21] DIVIDE.thedivide.o_quotient[20] $abc$24881$new_n7445 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[23] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7445 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[22] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[24] $abc$24881$new_n7448 DIVIDE.thedivide.o_quotient[23] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[23] -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7445 DIVIDE.thedivide.o_quotient[23] DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7448 -100 1 -.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[25] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[24] $abc$24881$new_n7448 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[24] -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10110 1 -10111 1 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1 -.names $abc$24881$new_n7526 $abc$24881$new_n3784 regset[28][15] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[15] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3779 regset[28][16] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[16] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3774 regset[28][17] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[17] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3769 regset[28][18] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[18] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3763 regset[28][19] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[19] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3757 regset[28][20] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[20] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3752 regset[28][21] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[21] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3747 regset[28][22] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[22] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3741 regset[28][23] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[23] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3735 regset[28][24] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[24] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3730 regset[28][25] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[25] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3725 regset[28][26] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[26] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3719 regset[28][27] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[27] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3714 regset[28][28] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[28] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3708 regset[28][29] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[29] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n3702 regset[28][30] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[30] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7526 $abc$24881$new_n6568 regset[28][31] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[31] -001 1 -011 1 -100 1 -101 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] o_pf_request_address[2] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] o_pf_request_address[3] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] o_pf_request_address[4] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[5] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] o_pf_request_address[5] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] o_pf_request_address[6] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] o_pf_request_address[7] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] o_pf_request_address[8] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] o_pf_request_address[9] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] o_pf_request_address[10] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] o_pf_request_address[11] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] o_pf_request_address[12] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] o_pf_request_address[13] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] o_pf_request_address[14] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] o_pf_request_address[15] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[16] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] o_pf_request_address[16] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] o_pf_request_address[17] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] o_pf_request_address[18] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] o_pf_request_address[19] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] o_pf_request_address[20] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] o_pf_request_address[21] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[22] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] o_pf_request_address[22] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[23] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] o_pf_request_address[23] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[24] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] o_pf_request_address[24] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[25] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] o_pf_request_address[25] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[26] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] o_pf_request_address[26] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[27] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] o_pf_request_address[27] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[28] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] o_pf_request_address[28] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] o_pf_request_address[29] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] o_pf_request_address[30] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[31] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] o_pf_request_address[31] -0010 1 -0011 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3863 regset[27][0] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[0] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3701 $abc$24881$new_n3958 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n7589 -1100 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3859 regset[27][1] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[1] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3853 regset[27][2] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[2] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3848 regset[27][3] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[3] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3843 regset[27][4] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[4] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3838 regset[27][5] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[5] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3832 regset[27][6] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[6] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3825 regset[27][7] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[7] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3820 regset[27][8] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[8] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3815 regset[27][9] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[9] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3810 regset[27][10] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[10] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3805 regset[27][11] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[11] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3800 regset[27][12] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[12] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3795 regset[27][13] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[13] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3790 regset[27][14] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[14] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3784 regset[27][15] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[15] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3779 regset[27][16] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[16] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3774 regset[27][17] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[17] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3769 regset[27][18] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[18] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3763 regset[27][19] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[19] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3757 regset[27][20] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[20] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n7589 $abc$24881$new_n3752 regset[27][21] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[21] -001 1 -011 1 -100 1 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$abc$24881$new_n7714 $abc$24881$new_n7774 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[1] $abc$24881$new_n7713 $abc$24881$new_n7716 $abc$24881$new_n7775 -000 1 -010 1 -100 1 -101 1 -.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7769 $abc$24881$new_n7777 $abc$24881$new_n7778 $abc$24881$new_n7776 -00100 1 -00101 1 -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] $abc$24881$new_n7766 $abc$24881$new_n7764 $abc$24881$new_n7777 -010 1 -011 1 -101 1 -111 1 -.names $abc$24881$new_n7779 o_mem_addr[3] $abc$24881$new_n7778 -10 1 -.names o_mem_addr[2] $abc$24881$new_n7780 $abc$24881$new_n7779 -00 1 -.names o_mem_addr[1] $abc$24881$new_n6738 o_mem_data[0] o_mem_addr[0] $abc$24881$new_n7780 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n7782 $abc$24881$new_n6679 $abc$24881$new_n6680 $abc$24881$new_n7722 $abc$24881$new_n6655 $abc$24881$new_n7781 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -.names $abc$24881$new_n7784 $abc$24881$new_n6653 $abc$24881$new_n6700 $abc$24881$new_n6679 $abc$24881$new_n7783 $abc$24881$new_n7782 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n7721 o_mem_addr[2] $abc$24881$new_n6654 o_mem_data[2] DIVIDE.thedivide.i_signed $abc$24881$new_n7783 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n7727 $abc$24881$new_n7724 o_mem_data[2] o_mem_addr[2] $abc$24881$new_n7784 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[29] o_mem_addr[2] $abc$24881$new_n7785 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$24881$new_n7787 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n7802 $abc$24881$new_n7804 $abc$24881$auto$rtlil.cc:2582:Mux$3529[3] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names $abc$24881$new_n7801 $abc$24881$new_n7788 $abc$24881$new_n7728 $abc$24881$new_n7690 $abc$24881$new_n7795 $abc$24881$new_n7787 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6787 $abc$24881$new_n7789 $abc$24881$new_n6785 $abc$24881$new_n7792 o_mem_addr[4] $abc$24881$new_n7788 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -.names $abc$24881$new_n7791 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7790 $abc$24881$new_n7789 -0000 1 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -.names o_mem_addr[2] $abc$24881$new_n6754 $abc$24881$new_n6767 $abc$24881$new_n7790 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n6765 $abc$24881$new_n6770 $abc$24881$new_n7791 -1000 1 -1010 1 -1100 1 -1101 1 -.names o_mem_addr[3] $abc$24881$new_n7793 $abc$24881$new_n7794 $abc$24881$new_n7792 -010 1 -011 1 -101 1 -111 1 -.names o_mem_addr[2] $abc$24881$new_n6757 $abc$24881$new_n6760 $abc$24881$new_n7793 -010 1 -011 1 -101 1 -111 1 -.names o_mem_addr[2] $abc$24881$new_n6762 o_mem_data[31] $abc$24881$new_n7794 -010 1 -011 1 -100 1 -110 1 -.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7789 $abc$24881$new_n7796 $abc$24881$new_n7798 $abc$24881$new_n7795 -00100 1 -00101 1 -00110 1 -00111 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] $abc$24881$new_n7793 $abc$24881$new_n7797 $abc$24881$new_n7796 -010 1 -011 1 -101 1 -111 1 -.names o_mem_addr[2] $abc$24881$new_n6762 $abc$24881$new_n7749 o_mem_addr[1] $abc$24881$new_n7797 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n7799 o_mem_addr[3] $abc$24881$new_n7798 -10 1 -.names o_mem_addr[2] $abc$24881$new_n7800 $abc$24881$new_n7799 -00 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7751 o_mem_data[3] o_mem_data[2] $abc$24881$new_n7800 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_addr[28] o_mem_addr[3] $abc$24881$new_n7801 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names o_mem_addr[3] o_mem_data[3] $abc$24881$new_n7803 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7802 -00101 1 -01001 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[2] o_mem_data[2] $abc$24881$new_n6700 $abc$24881$new_n7803 -001 1 -100 1 -101 1 -111 1 -.names o_mem_addr[3] o_mem_data[3] $abc$24881$new_n7805 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n7804 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -10000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n6678 $abc$24881$new_n6679 $abc$24881$new_n6680 $abc$24881$new_n7805 -000 1 -001 1 -011 1 -.names $abc$24881$new_n7807 $abc$24881$new_n7722 o_mem_addr[4] o_mem_data[4] $abc$24881$new_n7822 $abc$24881$auto$rtlil.cc:2582:Mux$3529[4] -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -.names $abc$24881$new_n7819 $abc$24881$new_n7728 $abc$24881$new_n7808 $abc$24881$new_n7821 o_mem_addr[4] $abc$24881$new_n7807 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n7809 $abc$24881$new_n7817 $abc$24881$new_n7689 $abc$24881$new_n7692 $abc$24881$new_n7811 $abc$24881$new_n7808 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -.names $abc$24881$new_n6658 $abc$24881$new_n6786 o_mem_data[31] o_mem_addr[4] $abc$24881$new_n7810 $abc$24881$new_n7809 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names o_mem_addr[3] o_mem_data[31] o_mem_addr[2] $abc$24881$new_n7810 -111 1 -.names o_mem_addr[4] o_mem_addr[3] $abc$24881$new_n7812 $abc$24881$new_n7815 $abc$24881$new_n7816 $abc$24881$new_n7811 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] $abc$24881$new_n7813 $abc$24881$new_n7814 $abc$24881$new_n7812 -001 1 -011 1 -100 1 -101 1 -.names o_mem_addr[2] $abc$24881$new_n7703 $abc$24881$new_n7813 -00 1 -.names o_mem_addr[2] $abc$24881$new_n7698 $abc$24881$new_n7701 $abc$24881$new_n7814 -010 1 -011 1 -101 1 -111 1 -.names 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o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6674 DIVIDE.thedivide.i_signed $abc$24881$new_n7865 -10000 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6698 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7866 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10111 1 -11001 1 -.names $abc$24881$new_n7820 o_mem_addr[25] $abc$24881$new_n7867 -11 1 -.names $abc$24881$new_n7870 $abc$24881$new_n7820 o_mem_addr[24] $abc$24881$new_n7821 o_mem_addr[7] $abc$24881$new_n7869 -00000 1 -00001 1 -00010 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -.names $abc$24881$new_n7728 $abc$24881$new_n7871 $abc$24881$new_n7690 $abc$24881$new_n7874 $abc$24881$new_n7870 -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -.names $abc$24881$new_n7828 $abc$24881$new_n6785 $abc$24881$new_n7872 $abc$24881$new_n7871 -100 1 -101 1 -111 1 -.names $abc$24881$new_n7873 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n6759 o_mem_data[31] $abc$24881$new_n7872 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11110 1 -.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n6753 $abc$24881$new_n6764 $abc$24881$new_n7873 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7873 $abc$24881$new_n7876 $abc$24881$new_n7875 $abc$24881$new_n7874 -00100 1 -00101 1 -01000 1 -01001 1 -01100 1 -01101 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] $abc$24881$new_n6759 $abc$24881$new_n7749 o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n7875 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6776 o_mem_addr[3] $abc$24881$new_n7877 $abc$24881$new_n7876 -100 1 -.names o_mem_addr[2] $abc$24881$new_n7878 $abc$24881$new_n7800 $abc$24881$new_n7877 -010 1 -011 1 -101 1 -111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7840 o_mem_data[7] o_mem_data[6] $abc$24881$new_n7878 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6674 $abc$24881$new_n7881 -000 1 -001 1 -011 1 -101 1 -.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6698 $abc$24881$new_n7884 -001 1 -100 1 -101 1 -111 1 -.names $abc$24881$new_n7828 o_mem_data[31] o_mem_addr[4] $abc$24881$new_n6658 o_mem_addr[3] $abc$24881$new_n7888 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names o_mem_addr[3] $abc$24881$new_n6733 $abc$24881$new_n7717 o_mem_addr[2] $abc$24881$new_n7891 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n7727 $abc$24881$new_n7896 $abc$24881$new_n7893 $abc$24881$new_n7895 $abc$24881$new_n7722 $abc$24881$new_n7892 -10000 1 -10001 1 -10010 1 -.names $abc$24881$new_n7721 $abc$24881$new_n7894 $abc$24881$new_n7723 o_mem_addr[8] o_mem_data[8] $abc$24881$new_n7893 -10000 1 -10001 1 -10010 1 -10011 1 -10111 1 -.names $abc$24881$new_n6654 $abc$24881$new_n7895 $abc$24881$new_n6697 DIVIDE.thedivide.i_signed o_mem_addr[8] $abc$24881$new_n7894 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -11100 1 -11101 1 -.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n7895 -01 1 -10 1 -.names $abc$24881$new_n6656 o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6673 DIVIDE.thedivide.i_signed $abc$24881$new_n7896 -10000 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[23] o_mem_addr[8] $abc$24881$new_n7897 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$24881$new_n7899 o_mem_addr[9] $abc$24881$new_n7821 $abc$24881$new_n7727 $abc$24881$new_n7909 $abc$24881$auto$rtlil.cc:2582:Mux$3529[9] -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n7728 $abc$24881$new_n7900 $abc$24881$new_n7903 o_mem_addr[22] $abc$24881$new_n7820 $abc$24881$new_n7899 -00100 1 -00101 1 -00110 1 -10000 1 -10001 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names o_mem_addr[4] $abc$24881$new_n7902 $abc$24881$new_n7901 o_mem_addr[3] $abc$24881$new_n7747 $abc$24881$new_n7900 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7690 $abc$24881$new_n6776 $abc$24881$new_n7901 -10 1 -.names $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7743 o_mem_data[31] $abc$24881$new_n7902 -1000 1 -1001 1 -1101 1 -1111 1 -.names $abc$24881$new_n7828 $abc$24881$new_n7904 $abc$24881$new_n7689 $abc$24881$new_n7905 $abc$24881$new_n7903 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7733 $abc$24881$new_n7740 $abc$24881$new_n7904 -10000 1 -10001 1 -11000 1 -11010 1 -.names o_mem_addr[3] $abc$24881$new_n7906 $abc$24881$new_n7751 o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7905 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[2] $abc$24881$new_n7839 $abc$24881$new_n7907 $abc$24881$new_n7906 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7908 o_mem_data[7] o_mem_data[6] $abc$24881$new_n7907 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names o_mem_addr[0] o_mem_data[9] o_mem_data[8] $abc$24881$new_n7908 -000 1 -001 1 -100 1 -110 1 -.names $abc$24881$new_n7910 $abc$24881$new_n7913 o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7722 $abc$24881$new_n7909 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -.names $abc$24881$new_n7721 $abc$24881$new_n7911 o_mem_data[9] o_mem_addr[9] $abc$24881$new_n7723 $abc$24881$new_n7910 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -.names o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7912 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7911 -00101 1 -01001 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6697 $abc$24881$new_n7912 -001 1 -100 1 -101 1 -111 1 -.names $abc$24881$new_n6656 o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7914 DIVIDE.thedivide.i_signed $abc$24881$new_n7913 -10001 1 -10010 1 -10011 1 -10100 1 -11000 1 -11110 1 -.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6673 $abc$24881$new_n7914 -000 1 -001 1 -011 1 -101 1 -.names $abc$24881$new_n7928 $abc$24881$new_n7916 $abc$24881$new_n7727 $abc$24881$new_n9694 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[10] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -.names $abc$24881$new_n7917 $abc$24881$new_n7919 $abc$24881$new_n7918 $abc$24881$new_n7689 $abc$24881$new_n7920 $abc$24881$new_n7916 -10000 1 -10001 1 -10011 1 -.names $abc$24881$new_n7828 $abc$24881$new_n7901 o_mem_addr[4] o_mem_addr[3] $abc$24881$new_n7764 $abc$24881$new_n7917 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[4] $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7763 o_mem_data[31] $abc$24881$new_n7918 -11000 1 -11001 1 -11101 1 -11111 1 -.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7770 $abc$24881$new_n7766 $abc$24881$new_n7919 -10000 1 -10001 1 -11000 1 -11010 1 -.names o_mem_addr[3] $abc$24881$new_n7779 $abc$24881$new_n7921 $abc$24881$new_n7920 -001 1 -011 1 -100 1 -101 1 -.names o_mem_addr[2] $abc$24881$new_n7862 $abc$24881$new_n7922 $abc$24881$new_n7921 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6735 o_mem_data[10] o_mem_data[9] $abc$24881$new_n7922 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[10] o_mem_addr[21] $abc$24881$new_n7928 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$24881$new_n7943 $abc$24881$new_n7930 $abc$24881$new_n7727 $abc$24881$new_n7937 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[11] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10000 1 -10010 1 -10100 1 -.names $abc$24881$new_n7828 $abc$24881$new_n7931 $abc$24881$new_n7933 $abc$24881$new_n7689 $abc$24881$new_n7934 $abc$24881$new_n7930 -10000 1 -10001 1 -10011 1 -.names o_mem_addr[4] $abc$24881$new_n7932 $abc$24881$new_n7901 o_mem_addr[3] $abc$24881$new_n7797 $abc$24881$new_n7931 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6785 o_mem_addr[3] o_mem_addr[2] o_mem_data[31] $abc$24881$new_n6762 $abc$24881$new_n7932 -10000 1 -10010 1 -10110 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7790 $abc$24881$new_n7793 $abc$24881$new_n7933 -10000 1 -10001 1 -11000 1 -11010 1 -.names o_mem_addr[3] $abc$24881$new_n7935 $abc$24881$new_n7799 $abc$24881$new_n7934 -010 1 -011 1 -100 1 -110 1 -.names o_mem_addr[2] $abc$24881$new_n7878 $abc$24881$new_n7936 $abc$24881$new_n7935 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7908 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7936 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7938 $abc$24881$new_n7941 $abc$24881$new_n7721 $abc$24881$new_n7937 -100 1 -110 1 -111 1 -.names $abc$24881$new_n7939 o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7722 $abc$24881$new_n7938 -0000 1 -0001 1 -0010 1 -0100 1 -0110 1 -0111 1 -.names $abc$24881$new_n6656 o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7940 DIVIDE.thedivide.i_signed $abc$24881$new_n7939 -10000 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6672 $abc$24881$new_n7940 -000 1 -001 1 -011 1 -101 1 -.names o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7942 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7941 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10111 1 -11001 1 -.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6696 $abc$24881$new_n7942 -001 1 -100 1 -101 1 -111 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[20] o_mem_addr[11] $abc$24881$new_n7943 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names $abc$24881$new_n7951 $abc$24881$new_n7946 $abc$24881$new_n7728 $abc$24881$new_n7692 $abc$24881$new_n7950 $abc$24881$new_n7945 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7947 $abc$24881$new_n6787 $abc$24881$new_n7690 $abc$24881$new_n7948 $abc$24881$new_n7691 $abc$24881$new_n7946 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -.names o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6785 o_mem_addr[2] o_mem_addr[3] $abc$24881$new_n7947 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] $abc$24881$new_n7818 $abc$24881$new_n7949 $abc$24881$new_n7948 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[2] $abc$24881$new_n6731 $abc$24881$new_n6734 $abc$24881$new_n7949 -010 1 -011 1 -101 1 -111 1 -.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7813 $abc$24881$new_n7814 $abc$24881$new_n7815 $abc$24881$new_n7950 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_addr[19] o_mem_addr[12] $abc$24881$new_n7951 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names $abc$24881$new_n7955 $abc$24881$new_n6702 $abc$24881$new_n6695 $abc$24881$new_n6653 $abc$24881$new_n7954 -1000 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n7721 $abc$24881$new_n6654 o_mem_addr[12] o_mem_data[12] DIVIDE.thedivide.i_signed $abc$24881$new_n7955 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n7968 $abc$24881$new_n7728 $abc$24881$new_n7962 $abc$24881$new_n7959 $abc$24881$new_n7967 $abc$24881$new_n7958 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[4] $abc$24881$new_n7961 $abc$24881$new_n7901 $abc$24881$new_n6785 $abc$24881$new_n7960 $abc$24881$new_n7959 -10010 1 -10110 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] $abc$24881$new_n7834 o_mem_data[31] o_mem_addr[2] $abc$24881$new_n7960 -0000 1 -0001 1 -0010 1 -1000 1 -1001 1 -1100 1 -1101 1 -.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n7748 $abc$24881$new_n7961 -000 1 -.names $abc$24881$new_n7828 $abc$24881$new_n7689 $abc$24881$new_n7963 $abc$24881$new_n7962 -100 1 -101 1 -111 1 -.names o_mem_addr[3] $abc$24881$new_n7838 $abc$24881$new_n7964 $abc$24881$new_n7963 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[2] $abc$24881$new_n7907 $abc$24881$new_n7965 $abc$24881$new_n7964 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7966 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7965 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names o_mem_addr[0] o_mem_data[13] o_mem_data[12] $abc$24881$new_n7966 -000 1 -001 1 -100 1 -110 1 -.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7830 $abc$24881$new_n7833 $abc$24881$new_n7967 -10000 1 -10001 1 -11000 1 -11010 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[18] o_mem_addr[13] $abc$24881$new_n7968 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1100 1 -1110 1 -.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6671 $abc$24881$new_n7971 -000 1 -001 1 -010 1 -100 1 -.names o_mem_addr[13] o_mem_data[13] $abc$24881$new_n7973 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7972 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10111 1 -11001 1 -.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6695 $abc$24881$new_n7973 -000 1 -100 1 -101 1 -110 1 -.names $abc$24881$new_n7986 $abc$24881$new_n7975 $abc$24881$new_n7982 $abc$24881$new_n7985 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[14] -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10010 1 -10110 1 -.names $abc$24881$new_n7828 $abc$24881$new_n7976 $abc$24881$new_n7978 $abc$24881$new_n7689 $abc$24881$new_n7979 $abc$24881$new_n7975 -10000 1 -10001 1 -10011 1 -.names o_mem_addr[4] $abc$24881$new_n7977 $abc$24881$new_n7901 $abc$24881$new_n7859 o_mem_addr[3] $abc$24881$new_n7976 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7856 o_mem_data[31] $abc$24881$new_n7977 -1000 1 -1001 1 -1101 1 -1111 1 -.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7852 $abc$24881$new_n7855 $abc$24881$new_n7978 -10000 1 -10001 1 -11000 1 -11010 1 -.names o_mem_addr[3] $abc$24881$new_n7861 $abc$24881$new_n7980 $abc$24881$new_n7979 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[2] $abc$24881$new_n7922 $abc$24881$new_n7981 $abc$24881$new_n7980 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6732 o_mem_data[14] o_mem_data[13] $abc$24881$new_n7981 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7727 $abc$24881$new_n7983 $abc$24881$new_n7721 $abc$24881$new_n7722 $abc$24881$new_n6701 $abc$24881$new_n7982 -10000 1 -10001 1 -10011 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names o_mem_addr[14] o_mem_data[14] $abc$24881$new_n7984 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7983 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10001 1 -10011 1 -10111 1 -11101 1 -.names $abc$24881$new_n6704 $abc$24881$new_n6695 $abc$24881$new_n6703 $abc$24881$new_n6702 $abc$24881$new_n7984 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1100 1 -.names $abc$24881$new_n6656 o_mem_addr[14] o_mem_data[14] $abc$24881$new_n6670 $abc$24881$new_n7724 $abc$24881$new_n7985 -10000 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[14] o_mem_addr[17] $abc$24881$new_n7986 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$24881$new_n7727 $abc$24881$new_n7988 $abc$24881$new_n8001 $abc$24881$new_n7728 $abc$24881$new_n7994 $abc$24881$auto$rtlil.cc:2582:Mux$3529[15] -00000 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7989 $abc$24881$new_n7992 o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7722 $abc$24881$new_n7988 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -.names $abc$24881$new_n7721 $abc$24881$new_n7990 o_mem_data[15] o_mem_addr[15] $abc$24881$new_n7723 $abc$24881$new_n7989 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -.names o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7991 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7990 -00101 1 -01001 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n6706 $abc$24881$new_n6694 $abc$24881$new_n7991 -00 1 -.names $abc$24881$new_n6656 o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7993 DIVIDE.thedivide.i_signed $abc$24881$new_n7992 -10001 1 -10010 1 -10011 1 -10100 1 -11000 1 -11110 1 -.names o_mem_addr[14] o_mem_data[14] $abc$24881$new_n6670 $abc$24881$new_n7993 -000 1 -001 1 -011 1 -101 1 -.names $abc$24881$new_n7995 $abc$24881$new_n7997 $abc$24881$new_n7689 $abc$24881$new_n7998 $abc$24881$new_n7994 -0000 1 -0001 1 -0011 1 -.names $abc$24881$new_n7901 o_mem_addr[4] $abc$24881$new_n6752 $abc$24881$new_n7996 $abc$24881$new_n7995 -1000 1 -1001 1 -1101 1 -1111 1 -.names $abc$24881$new_n7749 o_mem_addr[1] o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n7996 -1000 1 -.names $abc$24881$new_n6658 $abc$24881$new_n6786 o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6752 $abc$24881$new_n7997 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11010 1 -11110 1 -11111 1 -.names o_mem_addr[3] $abc$24881$new_n7877 $abc$24881$new_n7999 $abc$24881$new_n7998 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[2] $abc$24881$new_n7936 $abc$24881$new_n8000 $abc$24881$new_n7999 -001 1 -011 1 -110 1 -111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7966 o_mem_data[15] o_mem_data[14] $abc$24881$new_n8000 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[16] o_mem_addr[15] $abc$24881$new_n8001 -1010 1 -1011 1 -1101 1 -1111 1 -.names $abc$24881$new_n7727 $abc$24881$new_n8006 $abc$24881$new_n8011 $abc$24881$new_n8003 $abc$24881$new_n8012 $abc$24881$auto$rtlil.cc:2582:Mux$3529[16] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7721 $abc$24881$new_n8004 o_mem_addr[16] o_mem_data[16] $abc$24881$new_n7723 $abc$24881$new_n8003 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11111 1 -.names o_mem_addr[16] o_mem_data[16] $abc$24881$new_n8005 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8004 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11111 1 -.names o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7991 $abc$24881$new_n8005 -001 1 -100 1 -101 1 -111 1 -.names $abc$24881$new_n9702 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[16] o_mem_addr[15] $abc$24881$new_n8006 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$24881$new_n6656 o_mem_addr[16] o_mem_data[16] $abc$24881$new_n6669 DIVIDE.thedivide.i_signed $abc$24881$new_n8011 -10010 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7722 $abc$24881$new_n6705 $abc$24881$new_n8012 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-.names $abc$24881$new_n6657 $abc$24881$new_n8126 $abc$24881$new_n8026 $abc$24881$new_n7743 o_mem_addr[3] $abc$24881$new_n8125 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n6658 o_mem_data[31] $abc$24881$new_n6786 $abc$24881$new_n6744 $abc$24881$new_n8126 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -.names $abc$24881$new_n6776 $abc$24881$new_n7905 $abc$24881$new_n6744 $abc$24881$new_n7747 $abc$24881$new_n8127 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1100 1 -1101 1 -1111 1 -.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8022 $abc$24881$new_n8075 $abc$24881$new_n8129 $abc$24881$new_n8128 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8130 o_mem_data[23] o_mem_data[22] $abc$24881$new_n8129 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names o_mem_addr[0] o_mem_data[25] o_mem_data[24] $abc$24881$new_n8130 -000 1 -001 1 -100 1 -110 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[25] o_mem_addr[6] $abc$24881$new_n8131 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$24881$new_n8133 $abc$24881$new_n8143 $abc$24881$new_n7728 $abc$24881$new_n8138 $abc$24881$auto$rtlil.cc:2582:Mux$3529[26] -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -.names $abc$24881$new_n8134 $abc$24881$new_n7727 $abc$24881$new_n8136 $abc$24881$new_n7721 $abc$24881$new_n8133 -1100 1 -1110 1 -1111 1 -.names $abc$24881$new_n8135 o_mem_addr[26] o_mem_data[26] $abc$24881$new_n7722 $abc$24881$new_n8134 -1000 1 -1001 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6664 $abc$24881$new_n7724 $abc$24881$new_n6655 $abc$24881$new_n8135 -00000 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-01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11101 1 -11111 1 -.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7920 o_mem_addr[3] $abc$24881$new_n7764 $abc$24881$new_n8140 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8035 $abc$24881$new_n8089 $abc$24881$new_n8142 $abc$24881$new_n8141 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6743 o_mem_data[24] o_mem_data[23] $abc$24881$new_n8142 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11010 1 -11100 1 -11110 1 -.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[26] o_mem_addr[5] $abc$24881$new_n8143 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names $abc$24881$new_n7727 $abc$24881$new_n8150 $abc$24881$new_n8145 $abc$24881$new_n8148 $abc$24881$auto$rtlil.cc:2582:Mux$3529[27] -0000 1 -0001 1 -0010 1 -0011 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names $abc$24881$new_n7722 o_mem_addr[27] o_mem_data[27] $abc$24881$new_n7721 $abc$24881$new_n8146 $abc$24881$new_n8145 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10000 1 -10001 1 -10011 1 -11100 1 -11101 1 -11111 1 -.names o_mem_addr[27] o_mem_data[27] $abc$24881$new_n8147 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8146 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10111 1 -11001 1 -.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n8137 $abc$24881$new_n8147 -000 1 -100 1 -101 1 -110 1 -.names $abc$24881$new_n6656 o_mem_addr[27] o_mem_data[27] $abc$24881$new_n8149 DIVIDE.thedivide.i_signed $abc$24881$new_n8148 -10000 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6664 $abc$24881$new_n8149 -000 1 -001 1 -010 1 -100 1 -.names $abc$24881$new_n8156 $abc$24881$new_n8151 $abc$24881$new_n7728 $abc$24881$new_n8150 -101 1 -110 1 -111 1 -.names $abc$24881$new_n8152 $abc$24881$new_n7690 $abc$24881$new_n8153 $abc$24881$new_n7691 $abc$24881$new_n8154 $abc$24881$new_n8151 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n8126 $abc$24881$new_n7794 $abc$24881$new_n6786 $abc$24881$new_n6744 $abc$24881$new_n8152 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7934 o_mem_addr[3] $abc$24881$new_n7797 $abc$24881$new_n8153 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8048 $abc$24881$new_n8102 $abc$24881$new_n8155 $abc$24881$new_n8154 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8130 o_mem_data[27] o_mem_data[26] $abc$24881$new_n8155 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[27] o_mem_addr[4] $abc$24881$new_n8156 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$24881$new_n7721 $abc$24881$new_n8160 $abc$24881$new_n6653 $abc$24881$new_n8159 $abc$24881$new_n8158 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6721 $abc$24881$new_n6688 $abc$24881$new_n8159 -0001 1 -0010 1 -0011 1 -0100 1 -1000 1 -1101 1 -1110 1 -1111 1 -.names o_mem_addr[28] $abc$24881$new_n6654 DIVIDE.thedivide.i_signed o_mem_data[28] $abc$24881$new_n8160 -1000 1 -1001 1 -1010 1 -1011 1 -1111 1 -.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6663 $abc$24881$new_n7724 $abc$24881$new_n6655 $abc$24881$new_n8161 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01100 1 -01101 1 -10000 1 -10100 1 -10101 1 -11000 1 -11001 1 -11100 1 -.names $abc$24881$new_n8166 $abc$24881$new_n8164 $abc$24881$new_n6658 $abc$24881$new_n8167 $abc$24881$new_n7691 $abc$24881$new_n8163 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -11001 1 -11101 1 -.names $abc$24881$new_n8026 $abc$24881$new_n8165 o_mem_data[31] o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8164 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -.names $abc$24881$new_n7813 o_mem_addr[3] $abc$24881$new_n8165 -10 1 -.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7948 $abc$24881$new_n8165 $abc$24881$new_n8166 -10001 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8062 $abc$24881$new_n6741 $abc$24881$new_n6747 $abc$24881$new_n8167 -00000 1 -00001 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n6656 o_mem_addr[29] o_mem_data[29] $abc$24881$new_n8172 DIVIDE.thedivide.i_signed $abc$24881$new_n8171 -10000 1 -10101 1 -10110 1 -10111 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6663 $abc$24881$new_n8172 -000 1 -001 1 -010 1 -100 1 -.names $abc$24881$new_n7721 $abc$24881$new_n6653 $abc$24881$new_n8174 $abc$24881$new_n8175 $abc$24881$new_n8176 $abc$24881$new_n8173 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n6721 $abc$24881$new_n6688 o_mem_addr[28] o_mem_data[28] $abc$24881$new_n8174 -0010 1 -0100 1 -0110 1 -0111 1 -1000 1 -1010 1 -1011 1 -1100 1 -1110 1 -1111 1 -.names o_mem_addr[29] o_mem_data[29] $abc$24881$new_n8175 -00 1 -11 1 -.names o_mem_addr[29] $abc$24881$new_n6654 DIVIDE.thedivide.i_signed o_mem_data[29] $abc$24881$new_n8176 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7960 o_mem_data[31] $abc$24881$new_n8179 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n7691 o_mem_addr[3] $abc$24881$new_n8074 $abc$24881$new_n8182 $abc$24881$new_n8181 -1001 1 -1011 1 -1110 1 -1111 1 -.names o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n8129 $abc$24881$new_n8183 $abc$24881$new_n8184 $abc$24881$new_n8182 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[0] o_mem_data[27] o_mem_data[26] $abc$24881$new_n8183 -000 1 -001 1 -100 1 -110 1 -.names o_mem_addr[0] o_mem_data[29] o_mem_data[28] $abc$24881$new_n8184 -000 1 -001 1 -100 1 -110 1 -.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[29] o_mem_addr[2] $abc$24881$new_n8185 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -1100 1 -1101 1 -.names $abc$24881$new_n7722 $abc$24881$new_n8175 $abc$24881$new_n8186 -10 1 -.names $abc$24881$new_n8191 $abc$24881$new_n8190 $abc$24881$new_n8199 $abc$24881$new_n7721 $abc$24881$new_n8188 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$abc$24881$new_n9228 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names i_dbg_rreg[1] $abc$24881$new_n9232 $abc$24881$new_n9231 $abc$24881$new_n9230 $abc$24881$new_n9233 $abc$24881$new_n9229 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01010 1 -01100 1 -10000 1 -10010 1 -11000 1 -11010 1 -.names i_dbg_rreg[0] regset[1][31] regset[0][31] $abc$24881$new_n9230 -000 1 -010 1 -100 1 -101 1 -.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][31] regset[2][31] $abc$24881$new_n9231 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -.names i_dbg_rreg[0] regset[5][31] regset[4][31] $abc$24881$new_n9232 -000 1 -010 1 -100 1 -101 1 -.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][31] regset[6][31] $abc$24881$new_n9233 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 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$abc$24881$new_n9311 $abc$24881$new_n3747 regset[9][22] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[22] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n3741 regset[9][23] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[23] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n3735 regset[9][24] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[24] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n3730 regset[9][25] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[25] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n3725 regset[9][26] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[26] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n3719 regset[9][27] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[27] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n3714 regset[9][28] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[28] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n3708 regset[9][29] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[29] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n3702 regset[9][30] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[30] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9311 $abc$24881$new_n6568 regset[9][31] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[31] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9344 GEN_OP_STALL.r_cc_invalid_for_dcd i_mem_rdbusy DIVIDE.thedivide.o_busy $abc$24881$procmux$2728_Y -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5375 $abc$24881$new_n9345 alu_ce mem_ce $abc$24881$new_n9344 -1001 1 -1010 1 -1011 1 -.names $abc$24881$new_n4048 SET_GIE.r_gie o_mem_reg[4] o_mem_reg[0] op_wF $abc$24881$new_n9345 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01010 1 -01100 1 -01110 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11110 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3863 regset[8][0] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[0] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n3701 $abc$24881$new_n7027 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9347 -1110 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3859 regset[8][1] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[1] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3853 regset[8][2] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[2] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3848 regset[8][3] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[3] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3843 regset[8][4] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[4] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3838 regset[8][5] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[5] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3832 regset[8][6] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[6] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3825 regset[8][7] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[7] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3820 regset[8][8] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[8] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3815 regset[8][9] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[9] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3810 regset[8][10] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[10] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3805 regset[8][11] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[11] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3800 regset[8][12] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[12] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3795 regset[8][13] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[13] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3790 regset[8][14] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[14] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3784 regset[8][15] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[15] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3779 regset[8][16] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[16] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3774 regset[8][17] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[17] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3769 regset[8][18] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[18] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3763 regset[8][19] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[19] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3757 regset[8][20] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[20] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3752 regset[8][21] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[21] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3747 regset[8][22] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[22] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3741 regset[8][23] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[23] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3735 regset[8][24] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[24] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3730 regset[8][25] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[25] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3725 regset[8][26] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[26] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3719 regset[8][27] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[27] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3714 regset[8][28] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[28] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3708 regset[8][29] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[29] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n3702 regset[8][30] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[30] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n9347 $abc$24881$new_n6568 regset[8][31] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[31] -001 1 -011 1 -100 1 -101 1 -.names $abc$24881$new_n4083 $abc$24881$new_n3995 i_clear_cache o_dbg_stall $abc$24881$procmux$2755_Y -0010 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -.names DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[1] -01 1 -10 1 -.names DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[2] -011 1 -100 1 -101 1 -110 1 -.names DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[3] -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names DIVIDE.thedivide.r_bit[4] DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[4] -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.X[0] -0 1 -.names $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][0] $abc$24881$memory$auto$proc_rom.cc:150:do_switch$1988$rdmux[0][1][0]$b$3899[6] -0 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[29] $abc$24881$new_n3672 o_mem_data[30] $abc$24881$new_n9386 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9386 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[30] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22566 -0011 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[27] $abc$24881$new_n3673 o_mem_data[28] $abc$24881$new_n9388 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9388 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[28] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22570 -0011 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[25] $abc$24881$new_n3674 o_mem_data[26] $abc$24881$new_n9390 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9390 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[26] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22574 -0011 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.r_dividend[21] o_mem_data[23] $abc$24881$new_n9392 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11001 1 -.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[23] DIVIDE.thedivide.pre_sign $abc$24881$new_n9392 $abc$24881$new_n3676 $abc$24881$auto$rtlil.cc:2693:MuxGate$22580 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01010 1 -01011 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[21] $abc$24881$new_n3676 o_mem_data[22] $abc$24881$new_n9394 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9394 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22582 -0011 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.r_dividend[17] o_mem_data[19] $abc$24881$new_n9396 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11001 1 -.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[19] DIVIDE.thedivide.pre_sign $abc$24881$new_n9396 $abc$24881$new_n3678 $abc$24881$auto$rtlil.cc:2693:MuxGate$22588 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01010 1 -01011 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[17] $abc$24881$new_n3678 o_mem_data[18] $abc$24881$new_n9398 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9398 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22590 -0011 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[13] $abc$24881$new_n3681 o_mem_data[14] $abc$24881$new_n9400 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9400 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[14] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22598 -0011 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[6] $abc$24881$new_n3687 o_mem_data[7] $abc$24881$new_n9402 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9402 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[7] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22612 -0011 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[4] $abc$24881$new_n3688 o_mem_data[5] $abc$24881$new_n9404 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11010 1 -11011 1 -.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[5] DIVIDE.thedivide.pre_sign $abc$24881$new_n9404 DIVIDE.thedivide.r_dividend[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22616 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4062 alu_reg[0] instruction_decoder.o_dcdB[0] alu_reg[1] instruction_decoder.o_dcdB[1] $abc$24881$new_n9406 -10000 1 -10011 1 -11100 1 -11111 1 -.names GEN_OP_WR.r_op_wR o_mem_reg[0] instruction_decoder.o_dcdB[0] o_mem_reg[1] instruction_decoder.o_dcdB[1] $abc$24881$new_n9410 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$24881$new_n9410 o_mem_reg[2] instruction_decoder.o_dcdB[2] o_mem_reg[3] instruction_decoder.o_dcdB[3] $abc$24881$new_n9411 -10000 1 -10011 1 -11100 1 -11111 1 -.names $abc$24881$new_n9411 o_mem_reg[4] instruction_decoder.o_dcdB[4] $abc$24881$new_n9412 -100 1 -111 1 -.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$new_n4113 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] pf_pc[22] $abc$24881$new_n9413 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4087 $abc$24881$new_n9413 $abc$24881$new_n4094 $abc$24881$new_n4025 SET_USER_PC.r_upc[22] $abc$24881$new_n9414 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4160 $abc$24881$new_n4103 $abc$24881$new_n9414 ipc[22] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22818 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$24881$new_n4025 pf_pc[14] $abc$24881$new_n4099 pf_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n9416 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n4087 $abc$24881$new_n9416 $abc$24881$new_n4116 $abc$24881$new_n4025 SET_USER_PC.r_upc[14] $abc$24881$new_n9417 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4198 $abc$24881$new_n4103 $abc$24881$new_n9417 ipc[14] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22834 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n4117 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n4099 $abc$24881$new_n9419 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4087 $abc$24881$new_n9419 pf_pc[13] $abc$24881$new_n4025 SET_USER_PC.r_upc[13] $abc$24881$new_n9420 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4203 $abc$24881$new_n4103 $abc$24881$new_n9420 ipc[13] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22836 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$new_n4119 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n4101 $abc$24881$new_n9422 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4087 $abc$24881$new_n9422 pf_pc[7] $abc$24881$new_n4025 SET_USER_PC.r_upc[7] $abc$24881$new_n9423 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n4232 $abc$24881$new_n4103 $abc$24881$new_n9423 ipc[7] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22848 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11011 1 -11111 1 -.names $abc$24881$new_n4103 pf_pc[2] $abc$24881$new_n4125 $abc$24881$new_n4255 $abc$24881$new_n4024 $abc$24881$new_n9425 -00010 1 -00110 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n9425 ipc[2] $abc$24881$new_n4124 $abc$24881$new_n4122 $abc$24881$new_n4019 $abc$24881$auto$rtlil.cc:2693:MuxGate$22858 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5149 $abc$24881$new_n5148 $abc$24881$new_n5113 $abc$24881$new_n5147 dcd_I[31] $abc$24881$new_n9427 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -11011 1 -.names $abc$24881$new_n5066 $abc$24881$new_n4327 o_mem_addr[30] $abc$24881$new_n9427 $abc$24881$new_n5067 $abc$24881$auto$rtlil.cc:2693:MuxGate$22924 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4351 $abc$24881$new_n4344 $abc$24881$new_n9429 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4395 $abc$24881$new_n4390 $abc$24881$new_n4388 $abc$24881$new_n9433 -00000 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n9439 instruction_decoder.o_dcdB[4] $abc$24881$new_n4383 $abc$24881$new_n4069 $abc$24881$new_n4385 $abc$24881$new_n9434 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4398 $abc$24881$new_n9434 instruction_decoder.o_dcdB[4] $abc$24881$new_n9433 $abc$24881$new_n4393 $abc$24881$new_n9435 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9435 $abc$24881$new_n3848 $abc$24881$new_n4368 $abc$24881$new_n9436 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][3] regset[28][3] $abc$24881$new_n9437 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n9437 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][3] regset[24][3] $abc$24881$new_n9438 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[3] $abc$24881$new_n9438 instruction_decoder.o_dcdB[1] $abc$24881$new_n4382 $abc$24881$new_n4381 $abc$24881$new_n9439 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] $abc$24881$new_n4429 $abc$24881$new_n4432 $abc$24881$new_n4433 $abc$24881$new_n9440 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$24881$new_n9449 instruction_decoder.o_dcdB[4] $abc$24881$new_n9445 $abc$24881$new_n9440 instruction_decoder.o_dcdB[1] $abc$24881$new_n9441 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -.names $abc$24881$new_n4434 $abc$24881$new_n9441 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3853 $abc$24881$new_n9442 -01000 1 -01001 1 -01011 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][2] regset[6][2] $abc$24881$new_n9443 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdB[1] $abc$24881$new_n9443 instruction_decoder.o_dcdB[2] regset[3][2] regset[2][2] $abc$24881$new_n9444 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n9444 $abc$24881$new_n4414 $abc$24881$new_n4413 $abc$24881$new_n9445 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11100 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][2] regset[17][2] $abc$24881$new_n9446 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4349 $abc$24881$new_n9446 instruction_decoder.o_dcdB[0] regset[20][2] regset[16][2] $abc$24881$new_n9447 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9860 $abc$24881$new_n9447 $abc$24881$new_n9451 $abc$24881$new_n4416 $abc$24881$new_n9449 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][2] regset[22][2] $abc$24881$new_n9450 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4356 $abc$24881$new_n9450 instruction_decoder.o_dcdB[2] regset[19][2] regset[18][2] $abc$24881$new_n9451 -10001 1 -10011 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[31][1] regset[30][1] $abc$24881$new_n9452 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n4069 $abc$24881$new_n9452 instruction_decoder.o_dcdB[2] regset[27][1] regset[26][1] $abc$24881$new_n9453 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n9453 $abc$24881$new_n9863 $abc$24881$new_n9464 $abc$24881$new_n9455 -00000 1 -00010 1 -00100 1 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[21][1] regset[20][1] $abc$24881$new_n9456 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n4349 $abc$24881$new_n9456 instruction_decoder.o_dcdB[2] regset[17][1] regset[16][1] $abc$24881$new_n9457 -10000 1 -10010 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][1] regset[22][1] $abc$24881$new_n9458 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n4356 $abc$24881$new_n9458 instruction_decoder.o_dcdB[2] regset[19][1] regset[18][1] $abc$24881$new_n9459 -10000 1 -10010 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4466 $abc$24881$new_n4465 $abc$24881$new_n9460 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][1] regset[4][1] $abc$24881$new_n9462 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9462 instruction_decoder.o_dcdB[2] regset[1][1] regset[0][1] $abc$24881$new_n9463 -0001 1 -0011 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n9460 $abc$24881$new_n9466 instruction_decoder.o_dcdB[1] $abc$24881$new_n9865 $abc$24881$new_n9463 $abc$24881$new_n9464 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][1] regset[14][1] $abc$24881$new_n9465 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n4069 $abc$24881$new_n9465 instruction_decoder.o_dcdB[2] regset[11][1] regset[10][1] $abc$24881$new_n9466 -10000 1 -10010 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][0] regset[14][0] $abc$24881$new_n9467 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4069 $abc$24881$new_n9467 instruction_decoder.o_dcdB[2] regset[11][0] regset[10][0] $abc$24881$new_n9468 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -.names dcd_Bcc instruction_decoder.o_dcdB[0] $abc$24881$new_n4349 $abc$24881$new_n4495 $abc$24881$new_n4496 $abc$24881$new_n9469 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][0] regset[6][0] $abc$24881$new_n9471 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4356 $abc$24881$new_n9471 instruction_decoder.o_dcdB[2] regset[3][0] regset[2][0] $abc$24881$new_n9472 -10001 1 -10011 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][0] regset[22][0] $abc$24881$new_n9473 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4356 $abc$24881$new_n9473 instruction_decoder.o_dcdB[2] regset[19][0] regset[18][0] $abc$24881$new_n9474 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -.names $abc$24881$new_n4504 instruction_decoder.o_dcdB[0] $abc$24881$new_n4069 $abc$24881$new_n4508 $abc$24881$new_n4509 $abc$24881$new_n9475 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[21][0] regset[20][0] $abc$24881$new_n9477 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4349 $abc$24881$new_n9477 instruction_decoder.o_dcdB[2] regset[17][0] regset[16][0] $abc$24881$new_n9478 -10001 1 -10011 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4529 $abc$24881$new_n4524 $abc$24881$new_n4542 $abc$24881$new_n9479 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][6] regset[4][6] $abc$24881$new_n9483 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4349 $abc$24881$new_n9483 instruction_decoder.o_dcdB[2] regset[1][6] regset[0][6] $abc$24881$new_n9484 -10001 1 -10011 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4533 $abc$24881$new_n4538 $abc$24881$new_n9485 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4504 $abc$24881$new_n9485 instruction_decoder.o_dcdB[3] $abc$24881$new_n4540 $abc$24881$new_n4536 $abc$24881$new_n9486 -10001 1 -10011 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4554 $abc$24881$new_n4550 $abc$24881$new_n4549 $abc$24881$new_n9487 -00000 1 -00100 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4519 $abc$24881$new_n9487 instruction_decoder.o_dcdB[3] $abc$24881$new_n4552 $abc$24881$new_n4547 $abc$24881$new_n9488 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -.names $abc$24881$new_n4556 $abc$24881$new_n9488 $abc$24881$new_n4368 $abc$24881$new_n3838 $abc$24881$new_n4472 $abc$24881$new_n9489 -01000 1 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names dcd_Bcc instruction_decoder.o_dcdB[4] SET_TRAP_N_UBREAK.r_ubreak break_en $abc$24881$new_n4580 $abc$24881$new_n9490 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4570 $abc$24881$new_n4577 $abc$24881$new_n4587 $abc$24881$new_n9491 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9490 dcd_Bcc $abc$24881$new_n9491 $abc$24881$new_n9492 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -.names $abc$24881$new_n9492 $abc$24881$new_n3825 $abc$24881$new_n4368 $abc$24881$new_n9493 -100 1 -110 1 -111 1 -.names dcd_Bcc instruction_decoder.o_dcdB[4] SET_USER_BUSERR.r_ubus_err_flag $abc$24881$new_n4625 $abc$24881$new_n4623 $abc$24881$new_n9494 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9494 instruction_decoder.o_dcdB[4] ibus_err_flag $abc$24881$new_n4616 $abc$24881$new_n4632 $abc$24881$new_n9495 -00010 1 -00110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9495 $abc$24881$new_n4368 $abc$24881$new_n3810 $abc$24881$new_n9496 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4703 $abc$24881$new_n4349 $abc$24881$new_n4691 $abc$24881$new_n9497 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01101 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9497 $abc$24881$new_n4694 $abc$24881$new_n4701 $abc$24881$new_n4686 $abc$24881$new_n9498 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4519 $abc$24881$new_n9498 $abc$24881$new_n4368 $abc$24881$new_n3800 $abc$24881$new_n9499 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names dcd_Bcc instruction_decoder.o_dcdB[4] GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4717 $abc$24881$new_n4715 $abc$24881$new_n9500 -01010 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9500 instruction_decoder.o_dcdB[4] GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n4708 $abc$24881$new_n4724 $abc$24881$new_n9501 -00010 1 -00110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9501 $abc$24881$new_n4368 $abc$24881$new_n3795 $abc$24881$new_n9502 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4747 $abc$24881$new_n4349 $abc$24881$new_n4735 $abc$24881$new_n9503 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01101 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9503 $abc$24881$new_n4738 $abc$24881$new_n4745 $abc$24881$new_n4730 $abc$24881$new_n9504 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4519 $abc$24881$new_n9504 $abc$24881$new_n4368 $abc$24881$new_n3790 $abc$24881$new_n9505 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4759 $abc$24881$new_n4757 $abc$24881$new_n4755 $abc$24881$new_n9506 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9506 $abc$24881$new_n4753 $abc$24881$new_n4761 $abc$24881$new_n4768 $abc$24881$new_n9507 -00010 1 -00110 1 -01010 1 -01110 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9507 $abc$24881$new_n4368 $abc$24881$new_n3779 $abc$24881$new_n9508 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n4784 $abc$24881$new_n4791 $abc$24881$new_n4349 $abc$24881$new_n4356 $abc$24881$new_n4789 $abc$24881$new_n9509 -10000 1 -10001 1 -10011 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9509 $abc$24881$new_n4774 $abc$24881$new_n4069 $abc$24881$new_n4781 $abc$24881$new_n9510 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n4519 $abc$24881$new_n9510 $abc$24881$new_n4368 $abc$24881$new_n3784 $abc$24881$new_n9511 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4805 $abc$24881$new_n4803 $abc$24881$new_n4801 $abc$24881$new_n9512 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9512 $abc$24881$new_n4799 $abc$24881$new_n4807 $abc$24881$new_n4814 $abc$24881$new_n9513 -00010 1 -00110 1 -01010 1 -01110 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9513 $abc$24881$new_n4368 $abc$24881$new_n3774 $abc$24881$new_n9514 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][21] regset[22][21] $abc$24881$new_n9515 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n4356 $abc$24881$new_n9515 instruction_decoder.o_dcdB[2] regset[19][21] regset[18][21] $abc$24881$new_n9516 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] $abc$24881$new_n4893 $abc$24881$new_n4884 $abc$24881$new_n9516 $abc$24881$new_n9517 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n9517 $abc$24881$new_n3752 $abc$24881$new_n4368 $abc$24881$new_n9518 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4929 $abc$24881$new_n4936 $abc$24881$new_n4946 $abc$24881$new_n9519 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9519 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4939 $abc$24881$new_n9520 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11100 1 -11101 1 -.names $abc$24881$new_n9520 $abc$24881$new_n3735 $abc$24881$new_n4368 $abc$24881$new_n9521 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4952 $abc$24881$new_n4959 $abc$24881$new_n4969 $abc$24881$new_n9522 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9522 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4962 $abc$24881$new_n9523 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11100 1 -11101 1 -.names $abc$24881$new_n9523 $abc$24881$new_n3741 $abc$24881$new_n4368 $abc$24881$new_n9524 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4976 $abc$24881$new_n4983 $abc$24881$new_n4993 $abc$24881$new_n9525 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9525 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4986 $abc$24881$new_n9526 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -11000 1 -11100 1 -11101 1 -.names $abc$24881$new_n9526 $abc$24881$new_n3730 $abc$24881$new_n4368 $abc$24881$new_n9527 -100 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[4] $abc$24881$new_n5007 $abc$24881$new_n5017 $abc$24881$new_n9528 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9528 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n5000 $abc$24881$new_n5010 $abc$24881$new_n9529 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9529 $abc$24881$new_n4368 $abc$24881$new_n3719 $abc$24881$new_n9530 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names $abc$24881$new_n5032 $abc$24881$new_n5039 $abc$24881$new_n4349 $abc$24881$new_n4356 $abc$24881$new_n5037 $abc$24881$new_n9531 -10000 1 -10001 1 -10011 1 -11000 1 -11001 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9531 $abc$24881$new_n5022 $abc$24881$new_n4069 $abc$24881$new_n5029 $abc$24881$new_n9532 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n4519 $abc$24881$new_n9532 $abc$24881$new_n4368 $abc$24881$new_n3725 $abc$24881$new_n9533 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[4] $abc$24881$new_n5058 $abc$24881$new_n5055 $abc$24881$new_n9534 -0000 1 -0010 1 -1000 1 -1001 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5078 $abc$24881$new_n5074 $abc$24881$new_n5072 $abc$24881$new_n9539 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9539 $abc$24881$new_n5080 instruction_decoder.o_dcdB[1] $abc$24881$new_n5076 $abc$24881$new_n9540 -01000 1 -01010 1 -01011 1 -01100 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n4373 $abc$24881$new_n9540 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3708 $abc$24881$new_n9541 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -01000 1 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -11000 1 -11001 1 -11011 1 -.names $abc$24881$new_n5147 $abc$24881$new_n5148 $abc$24881$new_n5067 dcd_I[31] $abc$24881$new_n5113 $abc$24881$new_n9542 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01010 1 -01011 1 -01100 1 -01101 1 -01111 1 -10010 1 -10011 1 -10101 1 -11010 1 -11011 1 -11110 1 -.names $abc$24881$new_n9542 $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n5067 $abc$24881$new_n9543 -0010 1 -0100 1 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n9543 o_mem_addr[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$22926 -001 1 -011 1 -110 1 -111 1 -.names $abc$24881$new_n5067 $abc$24881$new_n9877 $abc$24881$new_n5166 $abc$24881$new_n5148 $abc$24881$new_n5113 $abc$24881$new_n9545 -00000 1 -00001 1 -00010 1 -00011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10101 1 -10110 1 -11001 1 -11010 1 -11101 1 -11110 1 -.names $abc$24881$new_n5066 dcd_I[31] $abc$24881$new_n9545 o_mem_addr[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$22928 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names $abc$24881$new_n5145 $abc$24881$new_n5146 $abc$24881$new_n5067 dcd_I[31] $abc$24881$new_n5114 $abc$24881$new_n9547 -00010 1 -00011 1 -00100 1 -01010 1 -01011 1 -01111 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -.names $abc$24881$new_n5066 $abc$24881$new_n9547 $abc$24881$new_n9533 $abc$24881$new_n5171 $abc$24881$new_n5067 $abc$24881$new_n9548 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11110 1 -.names dcd_I[31] $abc$24881$new_n9524 $abc$24881$new_n9521 $abc$24881$new_n9843 $abc$24881$new_n9549 -0000 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -.names $abc$24881$new_n5182 $abc$24881$new_n9549 $abc$24881$new_n4972 $abc$24881$new_n5067 $abc$24881$new_n9550 -1000 1 -1001 1 -1011 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n9550 $abc$24881$new_n5066 r_op_Bv[25] $abc$24881$new_n3730 $abc$24881$auto$rtlil.cc:2693:MuxGate$22934 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01010 1 -01011 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n5067 $abc$24881$new_n9524 $abc$24881$new_n9843 dcd_I[31] $abc$24881$new_n5192 $abc$24881$new_n9552 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9552 r_op_Bv[23] $abc$24881$new_n3741 $abc$24881$auto$rtlil.cc:2693:MuxGate$22938 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4904 dcd_I[31] $abc$24881$new_n9518 $abc$24881$new_n9844 dcd_I[21] $abc$24881$new_n9554 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[22] $abc$24881$new_n9554 $abc$24881$new_n5196 $abc$24881$auto$rtlil.cc:2693:MuxGate$22940 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n5201 $abc$24881$new_n9518 $abc$24881$new_n9844 dcd_I[21] $abc$24881$new_n5065 $abc$24881$new_n9556 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01100 1 -01110 1 -01111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n9556 $abc$24881$new_n5066 r_op_Bv[21] $abc$24881$new_n3752 $abc$24881$auto$rtlil.cc:2693:MuxGate$22942 -00010 1 -00011 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4860 dcd_I[20] $abc$24881$new_n4839 $abc$24881$new_n9845 dcd_I[19] $abc$24881$new_n9558 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[20] $abc$24881$new_n9558 $abc$24881$new_n5205 $abc$24881$auto$rtlil.cc:2693:MuxGate$22944 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n4817 dcd_I[18] $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] $abc$24881$new_n9560 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[18] $abc$24881$new_n9560 $abc$24881$new_n5214 $abc$24881$auto$rtlil.cc:2693:MuxGate$22948 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n5219 $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] $abc$24881$new_n5065 $abc$24881$new_n9562 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -01000 1 -01001 1 -01010 1 -01100 1 -01110 1 -01111 1 -.names $abc$24881$new_n5151 $abc$24881$new_n9562 $abc$24881$new_n5066 r_op_Bv[17] $abc$24881$new_n3774 $abc$24881$auto$rtlil.cc:2693:MuxGate$22950 -00010 1 -00011 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5224 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] $abc$24881$new_n9564 -0000 1 -0001 1 -0011 1 -0101 1 -1010 1 -1100 1 -1110 1 -1111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[16] $abc$24881$new_n9564 $abc$24881$new_n5223 $abc$24881$auto$rtlil.cc:2693:MuxGate$22952 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n5067 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] $abc$24881$new_n5229 $abc$24881$new_n9566 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9566 r_op_Bv[15] $abc$24881$new_n3784 $abc$24881$auto$rtlil.cc:2693:MuxGate$22954 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5067 $abc$24881$new_n9502 $abc$24881$new_n9847 dcd_I[13] $abc$24881$new_n5238 $abc$24881$new_n9568 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9568 r_op_Bv[13] $abc$24881$new_n3795 $abc$24881$auto$rtlil.cc:2693:MuxGate$22958 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01010 1 -01100 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9499 dcd_I[12] $abc$24881$new_n4660 $abc$24881$new_n4336 dcd_I[11] $abc$24881$new_n9570 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[12] $abc$24881$new_n9570 $abc$24881$new_n5242 $abc$24881$auto$rtlil.cc:2693:MuxGate$22960 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n9496 dcd_I[10] $abc$24881$new_n4636 $abc$24881$new_n4337 dcd_I[9] $abc$24881$new_n9572 -00010 1 -00100 1 -00110 1 -00111 1 -01000 1 -01001 1 -01011 1 -01101 1 -10000 1 -10001 1 -10011 1 -10101 1 -11010 1 -11100 1 -11110 1 -11111 1 -.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[10] $abc$24881$new_n9572 $abc$24881$new_n5250 $abc$24881$auto$rtlil.cc:2693:MuxGate$22964 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n5067 $abc$24881$new_n5279 $abc$24881$new_n5128 $abc$24881$new_n9858 dcd_I[4] $abc$24881$new_n9574 -00001 1 -00010 1 -00101 1 -00110 1 -01001 1 -01010 1 -01101 1 -01110 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5066 $abc$24881$new_n9574 $abc$24881$new_n5276 $abc$24881$new_n5067 o_mem_addr[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22976 -00001 1 -00011 1 -00101 1 -00111 1 -01001 1 -01011 1 -01101 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -.names dcd_Apc $abc$24881$new_n5601 $abc$24881$new_n5602 dcd_Acc $abc$24881$new_n9576 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[30] $abc$24881$new_n9576 $abc$24881$new_n3702 $abc$24881$auto$rtlil.cc:2693:MuxGate$23378 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n5646 $abc$24881$new_n5635 $abc$24881$new_n9578 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[28] SET_USER_PC.r_upc[28] $abc$24881$new_n9582 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9582 dcd_Acc dcd_Apc $abc$24881$new_n5652 $abc$24881$new_n5662 $abc$24881$new_n9583 -00000 1 -00010 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[28] $abc$24881$new_n9583 $abc$24881$new_n3714 $abc$24881$auto$rtlil.cc:2693:MuxGate$23382 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5689 $abc$24881$new_n5691 $abc$24881$new_n9585 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9585 instruction_decoder.o_dcdA[3] $abc$24881$new_n5694 $abc$24881$new_n5697 $abc$24881$new_n9586 -0000 1 -0001 1 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1010 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[26] SET_USER_PC.r_upc[26] $abc$24881$new_n9589 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9589 dcd_Acc dcd_Apc $abc$24881$new_n5713 $abc$24881$new_n5703 $abc$24881$new_n9590 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[26] $abc$24881$new_n9590 $abc$24881$new_n3725 $abc$24881$auto$rtlil.cc:2693:MuxGate$23386 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n5759 $abc$24881$new_n5769 $abc$24881$new_n9592 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5793 $abc$24881$new_n5783 $abc$24881$new_n9596 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9596 instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n5786 $abc$24881$new_n5776 $abc$24881$new_n9597 -10001 1 -10011 1 -11010 1 -11011 1 -.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3741 $abc$24881$new_n5795 $abc$24881$new_n9597 $abc$24881$new_n9598 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5809 $abc$24881$new_n5815 $abc$24881$new_n5817 $abc$24881$new_n9599 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5819 $abc$24881$new_n5799 $abc$24881$new_n9599 $abc$24881$new_n9600 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[22] $abc$24881$new_n9600 $abc$24881$new_n3747 $abc$24881$auto$rtlil.cc:2693:MuxGate$23394 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5843 $abc$24881$new_n5822 $abc$24881$new_n5832 $abc$24881$new_n9602 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[21] $abc$24881$new_n9602 $abc$24881$new_n3752 $abc$24881$auto$rtlil.cc:2693:MuxGate$23396 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[20] SET_USER_PC.r_upc[20] $abc$24881$new_n9604 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9604 dcd_Apc $abc$24881$new_n5857 $abc$24881$new_n5847 $abc$24881$new_n9605 -0001 1 -0011 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[20] $abc$24881$new_n9605 $abc$24881$new_n3757 $abc$24881$auto$rtlil.cc:2693:MuxGate$23398 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5905 $abc$24881$new_n5913 $abc$24881$new_n5911 $abc$24881$new_n9607 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5915 $abc$24881$new_n5895 $abc$24881$new_n9607 $abc$24881$new_n9608 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[18] $abc$24881$new_n9608 $abc$24881$new_n3769 $abc$24881$auto$rtlil.cc:2693:MuxGate$23402 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5953 $abc$24881$new_n5959 $abc$24881$new_n5961 $abc$24881$new_n9610 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5963 $abc$24881$new_n5943 $abc$24881$new_n9610 $abc$24881$new_n9611 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[16] $abc$24881$new_n9611 $abc$24881$new_n3779 $abc$24881$auto$rtlil.cc:2693:MuxGate$23406 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[15] SET_USER_PC.r_upc[15] $abc$24881$new_n9613 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9613 dcd_Acc dcd_Apc $abc$24881$new_n5967 $abc$24881$new_n5977 $abc$24881$new_n9614 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[15] $abc$24881$new_n9614 $abc$24881$new_n3784 $abc$24881$auto$rtlil.cc:2693:MuxGate$23408 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[14] SET_USER_PC.r_upc[14] $abc$24881$new_n9616 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9616 dcd_Acc dcd_Apc $abc$24881$new_n6002 $abc$24881$new_n9619 $abc$24881$new_n9617 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[14] $abc$24881$new_n9617 $abc$24881$new_n3790 $abc$24881$auto$rtlil.cc:2693:MuxGate$23410 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5992 $abc$24881$new_n5998 $abc$24881$new_n6000 $abc$24881$new_n9619 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names dcd_Apc $abc$24881$new_n6040 $abc$24881$new_n6041 dcd_Acc $abc$24881$new_n9620 -0001 1 -0010 1 -0011 1 -0101 1 -0110 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[12] $abc$24881$new_n9620 $abc$24881$new_n3800 $abc$24881$auto$rtlil.cc:2693:MuxGate$23414 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][11] regset[28][11] $abc$24881$new_n9622 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n5637 $abc$24881$new_n9622 instruction_decoder.o_dcdA[2] regset[25][11] regset[24][11] $abc$24881$new_n9623 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -.names dcd_Acc DIVERR.USER_DIVERR.r_udiv_err_flag $abc$24881$new_n6067 $abc$24881$new_n9623 $abc$24881$new_n9624 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n9624 DIVERR.r_idiv_err_flag $abc$24881$new_n6076 $abc$24881$new_n9625 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6197 $abc$24881$new_n6192 $abc$24881$new_n9626 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[5] SET_USER_PC.r_upc[5] $abc$24881$new_n9630 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9630 dcd_Acc dcd_Apc $abc$24881$new_n6213 $abc$24881$new_n6223 $abc$24881$new_n9631 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[5] $abc$24881$new_n9631 $abc$24881$new_n3838 $abc$24881$auto$rtlil.cc:2693:MuxGate$23428 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[4] $abc$24881$new_n6241 $abc$24881$new_n6239 $abc$24881$new_n6249 $abc$24881$new_n9633 -01000 1 -01001 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6251 instruction_decoder.o_dcdA[1] $abc$24881$new_n9633 $abc$24881$new_n6243 $abc$24881$new_n9634 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10101 1 -10111 1 -11001 1 -11101 1 -11111 1 -.names dcd_Acc $abc$24881$new_n9634 sleep $abc$24881$new_n9635 -010 1 -011 1 -101 1 -111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6272 $abc$24881$new_n6269 $abc$24881$new_n6264 $abc$24881$new_n9636 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6275 $abc$24881$new_n6282 $abc$24881$new_n6280 $abc$24881$new_n9637 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9637 $abc$24881$new_n9636 $abc$24881$new_n6266 $abc$24881$new_n9638 -0100 1 -0101 1 -0110 1 -0111 1 -1000 1 -1001 1 -1011 1 -1100 1 -1101 1 -1111 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n9638 $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n9639 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names dcd_Apc $abc$24881$new_n4071 $abc$24881$new_n9645 SET_USER_PC.r_upc[2] instruction_decoder.o_pc[2] $abc$24881$new_n9640 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[2] $abc$24881$new_n9640 $abc$24881$new_n3853 $abc$24881$auto$rtlil.cc:2693:MuxGate$23434 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6294 $abc$24881$new_n6297 $abc$24881$new_n6300 $abc$24881$new_n9642 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6303 $abc$24881$new_n6310 $abc$24881$new_n6308 $abc$24881$new_n9643 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9643 $abc$24881$new_n9642 $abc$24881$new_n6291 $abc$24881$new_n9644 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n9644 $abc$24881$new_n4438 $abc$24881$new_n4435 $abc$24881$new_n9645 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n4468 $abc$24881$new_n6328 $abc$24881$new_n9646 -0001 1 -0011 1 -1000 1 -1001 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6320 $abc$24881$new_n6323 $abc$24881$new_n6326 $abc$24881$new_n9648 -00000 1 -00010 1 -00100 1 -00110 1 -10000 1 -10001 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6361 $abc$24881$new_n6351 $abc$24881$new_n9650 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_pf_instruction_pc[29] $abc$24881$new_n6382 i_pf_instruction[17] $abc$24881$new_n6366 i_pf_instruction_pc[28] $abc$24881$new_n9654 -00001 1 -00011 1 -01011 1 -01100 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4278 $abc$24881$new_n9654 $abc$24881$auto$rtlil.cc:2693:MuxGate$23442 -00001 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n6566 $abc$24881$new_n6556 $abc$24881$new_n9656 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names $abc$24881$new_n5595 instruction_decoder.o_dcdA[4] $abc$24881$new_n9656 $abc$24881$new_n6558 $abc$24881$new_n6549 $abc$24881$new_n9657 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names o_mem_data[31] o_mem_addr[31] $abc$24881$new_n6683 $abc$24881$new_n6662 $abc$24881$new_n6682 $abc$24881$new_n9658 -01001 1 -01011 1 -01100 1 -01101 1 -01111 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names alu_ce doalu.c $abc$24881$new_n6685 $abc$24881$new_n6655 $abc$24881$new_n9658 $abc$24881$auto$rtlil.cc:2693:MuxGate$23622 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11111 1 -.names $abc$24881$new_n3692 r_op_Av[3] $abc$24881$new_n3848 $abc$24881$new_n9660 -000 1 -001 1 -101 1 -111 1 -.names $abc$24881$new_n6678 o_mem_addr[3] $abc$24881$new_n9660 $abc$24881$new_n6680 $abc$24881$new_n6679 $abc$24881$new_n9661 -00000 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n6746 $abc$24881$new_n6741 $abc$24881$new_n6745 $abc$24881$new_n9662 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[5] o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6727 $abc$24881$new_n9662 $abc$24881$new_n9663 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[5] $abc$24881$new_n6776 $abc$24881$new_n9663 o_mem_data[0] $abc$24881$new_n6751 $abc$24881$new_n9664 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$24881$new_n4282 $abc$24881$new_n4284 $abc$24881$new_n4302 $abc$24881$new_n4292 $abc$24881$new_n4280 $abc$24881$new_n9665 -10001 1 -10111 1 -11000 1 -11110 1 -.names $abc$24881$new_n9665 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n4279 $abc$24881$new_n4278 $abc$24881$new_n9666 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names $abc$24881$new_n4028 instruction_decoder.GEN_OPIPE.r_insn_is_pipeable $abc$24881$new_n6801 $abc$24881$new_n9666 $abc$24881$auto$rtlil.cc:2693:MuxGate$23632 -0011 1 -0111 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n3932 $abc$24881$new_n9668 -00000 1 -00110 1 -11000 1 -11110 1 -.names $abc$24881$new_n3879 DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[43] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n9669 -00000 1 -00011 1 -01100 1 -01111 1 -10100 1 -10111 1 -11000 1 -11011 1 -.names $abc$24881$new_n6943 $abc$24881$new_n9669 $abc$24881$new_n9668 $abc$24881$new_n3922 $abc$24881$new_n3917 $abc$24881$new_n9670 -11100 1 -.names $abc$24881$new_n7727 $abc$24881$new_n7726 o_mem_addr[0] o_mem_data[0] $abc$24881$new_n9671 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1110 1 -.names o_mem_addr[1] o_mem_data[1] $abc$24881$new_n9671 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9672 -00101 1 -01001 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[1] o_mem_data[1] $abc$24881$new_n6775 DIVIDE.thedivide.i_signed $abc$24881$new_n7722 $abc$24881$new_n9674 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7737 $abc$24881$new_n6771 $abc$24881$new_n6774 $abc$24881$new_n9678 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7733 $abc$24881$new_n9678 $abc$24881$new_n9679 -0001 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names o_mem_addr[5] o_mem_data[5] $abc$24881$new_n7843 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9680 -00101 1 -01001 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7727 $abc$24881$new_n7721 $abc$24881$new_n9680 $abc$24881$new_n7844 $abc$24881$new_n9681 -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9681 $abc$24881$new_n7826 $abc$24881$new_n7847 $abc$24881$auto$rtlil.cc:2582:Mux$3529[5] -100 1 -110 1 -111 1 -.names o_mem_addr[7] o_mem_data[7] $abc$24881$new_n7884 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9683 -00101 1 -01001 1 -10000 1 -10001 1 -10010 1 -10100 1 -10110 1 -11000 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names o_mem_addr[7] o_mem_data[7] $abc$24881$new_n7881 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9684 -00000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11110 1 -.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7700 $abc$24881$new_n7695 $abc$24881$new_n7706 $abc$24881$new_n9688 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10100 1 -10101 1 -.names $abc$24881$new_n7888 $abc$24881$new_n7692 $abc$24881$new_n9688 $abc$24881$new_n7689 $abc$24881$new_n7891 $abc$24881$new_n9689 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10110 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7892 $abc$24881$new_n7897 $abc$24881$new_n9689 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[8] -0000 1 -0001 1 -0010 1 -0011 1 -0110 1 -.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6696 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9691 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -00111 1 -01000 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10011 1 -10101 1 -10111 1 -11001 1 -.names $abc$24881$new_n7722 o_mem_addr[10] o_mem_data[10] $abc$24881$new_n9691 $abc$24881$new_n9692 -0001 1 -0011 1 -0101 1 -0111 1 -1000 1 -1001 1 -1110 1 -1111 1 -.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6672 DIVIDE.thedivide.i_signed $abc$24881$new_n7722 $abc$24881$new_n9693 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -10000 1 -11100 1 -11101 1 -.names $abc$24881$new_n6656 $abc$24881$new_n9692 $abc$24881$new_n9693 $abc$24881$new_n9694 -010 1 -011 1 -101 1 -111 1 -.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6671 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9695 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01100 1 -10100 1 -11000 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7727 $abc$24881$new_n7722 $abc$24881$new_n9695 $abc$24881$new_n6656 $abc$24881$new_n7954 $abc$24881$new_n9696 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n9696 $abc$24881$new_n7945 $abc$24881$auto$rtlil.cc:2582:Mux$3529[12] -10 1 -.names o_mem_addr[13] o_mem_data[13] $abc$24881$new_n7971 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9698 -00000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11110 1 -.names $abc$24881$new_n7958 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n9698 $abc$24881$new_n7972 $abc$24881$auto$rtlil.cc:2582:Mux$3529[13] -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names $abc$24881$new_n6658 $abc$24881$new_n6776 o_mem_addr[4] o_mem_data[31] $abc$24881$new_n7718 $abc$24881$new_n9700 -01000 1 -01001 1 -01010 1 -01011 1 -01101 1 -01111 1 -10110 1 -10111 1 -11110 1 -11111 1 -.names $abc$24881$new_n9700 $abc$24881$new_n7728 o_mem_addr[4] $abc$24881$new_n6727 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$abc$24881$new_n8584 $abc$24881$new_n9823 $abc$24881$new_n9825 $abc$24881$new_n9830 $0\genblk43.SETDBG.r_dbg_reg[31:0][28] -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00110 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names i_dbg_rreg[0] regset[5][28] regset[4][28] $abc$24881$new_n9827 -000 1 -010 1 -100 1 -101 1 -.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9827 regset[7][28] regset[6][28] $abc$24881$new_n9828 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names i_dbg_rreg[3] i_dbg_rreg[0] $abc$24881$new_n9828 regset[13][28] regset[12][28] $abc$24881$new_n9829 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n9829 $abc$24881$new_n9167 $abc$24881$new_n9165 $abc$24881$new_n9830 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_dbg_rreg[3] $abc$24881$new_n9178 i_dbg_rreg[2] $abc$24881$new_n9182 $abc$24881$new_n9176 $abc$24881$new_n9831 -00001 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n8653 $abc$24881$new_n9184 $abc$24881$new_n9831 $abc$24881$new_n9180 $abc$24881$new_n9832 -0100 1 -0101 1 -0110 1 -0111 1 -1011 1 -1111 1 -.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9832 SET_USER_PC.r_upc[29] ipc[29] $0\genblk43.SETDBG.r_dbg_reg[31:0][29] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names i_dbg_rreg[2] i_dbg_rreg[4] $abc$24881$new_n9917 $abc$24881$new_n9201 $abc$24881$new_n9211 $abc$24881$new_n9835 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9835 $abc$24881$new_n9196 $abc$24881$new_n9206 $abc$24881$new_n9836 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10000 1 -10001 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9836 SET_USER_PC.r_upc[30] ipc[30] $0\genblk43.SETDBG.r_dbg_reg[31:0][30] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names r_halted i_halt $abc$24881$new_n9274 $abc$24881$new_n3959 DIVIDE.thedivide.o_busy $abc$24881$new_n9838 -00110 1 -01110 1 -10110 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9838 o_mem_ce i_dbg_we i_mem_busy $abc$24881$procmux$2578_Y -0000 1 -0001 1 -0010 1 -0011 1 -0100 1 -0101 1 -0110 1 -0111 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names i_mem_rdbusy alu_reg[2] instruction_decoder.o_dcdB[2] $abc$24881$new_n9406 instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$new_n9840 -00010 1 -00011 1 -01110 1 -01111 1 -10001 1 -10101 1 -10111 1 -11001 1 -11011 1 -11101 1 -.names i_mem_rdbusy $abc$24881$new_n9412 $abc$24881$new_n4035 $abc$24881$new_n9840 DIVIDE.thedivide.o_busy $abc$24881$new_n9841 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names dcd_Bcc dcd_zI $abc$24881$new_n9841 op_wF GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n9842 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -11000 1 -11100 1 -.names $abc$24881$new_n9518 $abc$24881$new_n9844 $abc$24881$new_n4904 dcd_I[31] dcd_I[21] $abc$24881$new_n9843 -00100 1 -00101 1 -01000 1 -01100 1 -01101 1 -01110 1 -10000 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4860 $abc$24881$new_n4839 $abc$24881$new_n9845 dcd_I[19] dcd_I[20] $abc$24881$new_n9844 -00100 1 -01000 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4817 $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] dcd_I[18] $abc$24881$new_n9845 -00100 1 -01000 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9508 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] dcd_I[16] $abc$24881$new_n9846 -00100 1 -01000 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9499 $abc$24881$new_n4660 $abc$24881$new_n4336 dcd_I[11] dcd_I[12] $abc$24881$new_n9847 -00100 1 -01000 1 -01100 1 -01110 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -11000 1 -11001 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[27] SET_USER_PC.r_upc[27] $abc$24881$new_n9848 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9848 dcd_Acc dcd_Apc $abc$24881$new_n9586 $abc$24881$new_n5678 $abc$24881$new_n9849 -00000 1 -00001 1 -01000 1 -01001 1 -01010 1 -01011 1 -10001 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[27] $abc$24881$new_n9849 $abc$24881$new_n3719 $abc$24881$auto$rtlil.cc:2693:MuxGate$23384 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9646 instruction_decoder.o_dcdA[4] $abc$24881$new_n4470 $abc$24881$new_n9648 $abc$24881$new_n6317 $abc$24881$new_n9851 -01000 1 -01100 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5595 r_op_Av[1] $abc$24881$new_n9851 $abc$24881$new_n6338 $abc$24881$auto$rtlil.cc:2693:MuxGate$23436 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9650 dcd_Acc $abc$24881$new_n6344 $abc$24881$new_n6354 $abc$24881$new_n9853 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9853 dcd_Apc dcd_Acc $abc$24881$new_n5380 $abc$24881$new_n5379 $abc$24881$new_n9854 -00100 1 -00110 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[0] $abc$24881$new_n9854 $abc$24881$new_n3863 $abc$24881$auto$rtlil.cc:2693:MuxGate$23438 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9429 instruction_decoder.o_dcdB[3] $abc$24881$new_n4354 $abc$24881$new_n4347 $abc$24881$new_n9856 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9856 $abc$24881$new_n4358 $abc$24881$new_n4365 instruction_decoder.o_dcdB[1] $abc$24881$new_n9857 -00100 1 -00101 1 -00110 1 -00111 1 -01101 1 -01110 1 -01111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n4367 dcd_Bcc $abc$24881$new_n4373 $abc$24881$new_n9857 sleep $abc$24881$new_n9858 -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01110 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[31][2] regset[30][2] $abc$24881$new_n9859 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n4069 $abc$24881$new_n9859 instruction_decoder.o_dcdB[2] regset[27][2] regset[26][2] $abc$24881$new_n9860 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][1] regset[28][1] $abc$24881$new_n9861 -0100 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -1100 1 -1101 1 -.names $abc$24881$new_n9861 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][1] regset[24][1] $abc$24881$new_n9862 -00000 1 -00010 1 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n9459 $abc$24881$new_n9457 instruction_decoder.o_dcdB[3] $abc$24881$new_n9862 $abc$24881$new_n9863 -0000 1 -0001 1 -0010 1 -.names instruction_decoder.o_dcdB[0] regset[9][1] regset[8][1] $abc$24881$new_n9864 -001 1 -011 1 -110 1 -111 1 -.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n9864 regset[13][1] regset[12][1] $abc$24881$new_n9865 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[13][0] regset[12][0] $abc$24881$new_n9866 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9866 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[9][0] regset[8][0] $abc$24881$new_n9867 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n9468 $abc$24881$new_n9469 $abc$24881$new_n9472 instruction_decoder.o_dcdB[3] $abc$24881$new_n9867 $abc$24881$new_n9868 -11000 1 -11001 1 -11010 1 -.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][0] regset[28][0] $abc$24881$new_n9869 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9869 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][0] regset[24][0] $abc$24881$new_n9870 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names $abc$24881$new_n9474 $abc$24881$new_n9475 $abc$24881$new_n9478 instruction_decoder.o_dcdB[3] $abc$24881$new_n9870 $abc$24881$new_n9871 -11000 1 -11001 1 -11010 1 -.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4520 $abc$24881$new_n9479 $abc$24881$new_n9484 $abc$24881$new_n9872 -00000 1 -00001 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n3832 $abc$24881$new_n4368 $abc$24881$new_n9872 $abc$24881$new_n4373 $abc$24881$new_n9486 $abc$24881$new_n9873 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11111 1 -.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] $abc$24881$new_n5045 $abc$24881$new_n5061 $abc$24881$new_n5063 $abc$24881$new_n9874 -00001 1 -00011 1 -00101 1 -00111 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9534 instruction_decoder.o_dcdB[1] $abc$24881$new_n5048 $abc$24881$new_n5050 $abc$24881$new_n9875 -0001 1 -0011 1 -1010 1 -1011 1 -1100 1 -1101 1 -1110 1 -1111 1 -.names $abc$24881$new_n9875 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[4] $abc$24881$new_n9874 $abc$24881$new_n5052 $abc$24881$new_n9876 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01110 1 -10000 1 -10001 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -.names $abc$24881$new_n4519 $abc$24881$new_n9876 $abc$24881$new_n4368 $abc$24881$new_n3714 $abc$24881$new_n9877 -0000 1 -0001 1 -0011 1 -0100 1 -0101 1 -0111 1 -1000 1 -1001 1 -1011 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[29] SET_USER_PC.r_upc[29] $abc$24881$new_n9878 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9878 $abc$24881$new_n9578 dcd_Apc $abc$24881$new_n5628 $abc$24881$new_n5639 $abc$24881$new_n9879 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[29] $abc$24881$new_n9879 $abc$24881$new_n3708 $abc$24881$auto$rtlil.cc:2693:MuxGate$23380 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[24] SET_USER_PC.r_upc[24] $abc$24881$new_n9881 -00110 1 -00111 1 -01101 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n9881 $abc$24881$new_n9592 dcd_Apc $abc$24881$new_n5762 $abc$24881$new_n5752 $abc$24881$new_n9882 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[24] $abc$24881$new_n9882 $abc$24881$new_n3735 $abc$24881$auto$rtlil.cc:2693:MuxGate$23390 -00000 1 -00010 1 -00100 1 -00110 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][6] regset[6][6] $abc$24881$new_n9884 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9626 $abc$24881$new_n9884 instruction_decoder.o_dcdA[2] regset[2][6] regset[3][6] $abc$24881$new_n9885 -10000 1 -10001 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11010 1 -.names $abc$24881$new_n9626 dcd_Acc instruction_decoder.o_dcdA[3] $abc$24881$new_n9885 $abc$24881$new_n6190 $abc$24881$new_n9886 -00001 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n9886 $abc$24881$new_n4520 $abc$24881$new_n6199 $abc$24881$new_n9887 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11100 1 -11101 1 -.names $abc$24881$new_n7727 o_mem_addr[1] o_mem_data[1] DIVIDE.thedivide.i_signed o_mem_addr[30] $abc$24881$new_n9888 -00001 1 -00101 1 -01001 1 -01010 1 -01011 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n7727 $abc$24881$new_n7722 $abc$24881$new_n9888 $abc$24881$new_n9671 $abc$24881$new_n9672 $abc$24881$new_n9889 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -10001 1 -10011 1 -10101 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n7727 $abc$24881$new_n6656 $abc$24881$new_n9889 $abc$24881$new_n7730 $abc$24881$new_n9674 $abc$24881$auto$rtlil.cc:2582:Mux$3529[1] -00000 1 -00001 1 -00010 1 -00011 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -10100 1 -10101 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11111 1 -.names $abc$24881$new_n7869 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n9683 $abc$24881$new_n9684 $abc$24881$auto$rtlil.cc:2582:Mux$3529[7] -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01110 1 -01111 1 -.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8541 $abc$24881$new_n8547 $abc$24881$new_n8543 $abc$24881$new_n9893 -00001 1 -00011 1 -00101 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n8525 $abc$24881$new_n4438 $abc$24881$new_n8545 $abc$24881$new_n9893 $abc$24881$new_n9894 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1000 1 -1001 1 -1010 1 -1011 1 -.names i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n9894 $abc$24881$new_n4435 $abc$24881$new_n8549 $abc$24881$new_n9895 -00000 1 -00010 1 -00100 1 -00110 1 -01000 1 -01001 1 -01100 1 -01101 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$new_n9762 $abc$24881$new_n8584 $abc$24881$new_n9763 i_dbg_rreg[4] $abc$24881$new_n8794 $abc$24881$new_n9896 -00000 1 -00001 1 -00010 1 -00011 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10100 1 -10101 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9896 SET_USER_PC.r_upc[12] ipc[12] $0\genblk43.SETDBG.r_dbg_reg[31:0][12] -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names $abc$24881$new_n8525 i_dbg_rreg[4] GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n9767 $abc$24881$new_n8823 $abc$24881$new_n9898 -01011 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$new_n9898 i_dbg_rreg[4] $abc$24881$new_n8726 $abc$24881$new_n8825 GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n9899 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -.names $abc$24881$new_n9899 i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y SET_USER_PC.r_upc[13] ipc[13] $0\genblk43.SETDBG.r_dbg_reg[31:0][13] -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names i_dbg_rreg[0] i_dbg_rreg[4] regset[29][19] regset[28][19] $abc$24881$new_n9901 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n8516 $abc$24881$new_n9901 i_dbg_rreg[4] regset[13][19] regset[12][19] $abc$24881$new_n9902 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -.names $abc$24881$new_n9902 i_dbg_rreg[4] $abc$24881$new_n9790 $abc$24881$new_n9785 $abc$24881$new_n8963 $abc$24881$new_n9903 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10011 1 -10100 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9903 SET_USER_PC.r_upc[19] ipc[19] $0\genblk43.SETDBG.r_dbg_reg[31:0][19] -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names i_dbg_rreg[0] i_dbg_rreg[1] regset[19][21] regset[18][21] $abc$24881$new_n9905 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9905 i_dbg_rreg[3] i_dbg_rreg[1] regset[16][21] regset[17][21] $abc$24881$new_n9906 -00000 1 -00001 1 -00100 1 -00101 1 -00110 1 -00111 1 -10000 1 -10010 1 -.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9006 $abc$24881$new_n9906 $abc$24881$new_n9009 $abc$24881$new_n9907 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10001 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_dbg_rreg[1] i_dbg_rreg[0] regset[7][26] regset[5][26] $abc$24881$new_n9909 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9909 i_dbg_rreg[3] i_dbg_rreg[0] regset[6][26] regset[4][26] $abc$24881$new_n9910 -00001 1 -00011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_dbg_rreg[3] $abc$24881$new_n9910 i_dbg_rreg[2] regset[13][26] regset[12][26] $abc$24881$new_n9911 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names i_dbg_rreg[0] i_dbg_rreg[1] regset[31][27] regset[30][27] $abc$24881$new_n9912 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names i_dbg_rreg[3] $abc$24881$new_n9912 i_dbg_rreg[1] regset[29][27] regset[28][27] $abc$24881$new_n9913 -10001 1 -10011 1 -11010 1 -11011 1 -11100 1 -11101 1 -11110 1 -11111 1 -.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9130 $abc$24881$new_n9913 $abc$24881$new_n9144 $abc$24881$new_n9914 -00100 1 -00101 1 -00110 1 -00111 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10110 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9819 $abc$24881$new_n9129 $abc$24881$new_n9914 $abc$24881$new_n9915 -00011 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01111 1 -10110 1 -10111 1 -11001 1 -11011 1 -11101 1 -11110 1 -11111 1 -.names i_dbg_rreg[4] i_dbg_rreg[0] regset[29][30] regset[13][30] $abc$24881$new_n9916 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9916 i_dbg_rreg[1] i_dbg_rreg[0] regset[28][30] regset[12][30] $abc$24881$new_n9917 -00001 1 -00011 1 -10010 1 -10011 1 -10100 1 -10101 1 -10110 1 -10111 1 -.names i_dbg_rreg[0] i_dbg_rreg[4] regset[31][21] regset[30][21] $abc$24881$new_n9918 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n9918 i_dbg_rreg[1] regset[15][21] regset[14][21] $abc$24881$new_n9919 -0101 1 -0111 1 -1000 1 -1001 1 -1010 1 -1011 1 -1110 1 -1111 1 -.names $abc$24881$new_n6930 $abc$24881$new_n9919 i_dbg_rreg[1] regset[13][21] regset[12][21] $abc$24881$new_n9920 -00000 1 -00001 1 -00010 1 -00011 1 -00100 1 -00101 1 -00110 1 -00111 1 -01000 1 -01001 1 -01010 1 -01011 1 -01100 1 -01101 1 -01110 1 -01111 1 -10000 1 -10010 1 -10100 1 -10101 1 -10110 1 -10111 1 -11000 1 -11001 1 -.names $abc$24881$new_n6930 i_dbg_rreg[1] $abc$24881$new_n9907 $abc$24881$new_n9918 $abc$24881$new_n9018 $abc$24881$new_n9921 -00000 1 -00001 1 -00010 1 -00011 1 -01000 1 -01001 1 -01010 1 -01011 1 -10000 1 -10001 1 -10010 1 -10011 1 -10101 1 -10111 1 -11000 1 -11001 1 -11010 1 -11011 1 -11110 1 -11111 1 -.names i_dbg_rreg[4] $abc$24881$new_n9921 $abc$24881$new_n9798 $abc$24881$new_n9920 $abc$24881$new_n9922 -0000 1 -0001 1 -0010 1 -0100 1 -0101 1 -0110 1 -1100 1 -1101 1 -1110 1 -1111 1 -.subckt sdffr C=i_clk D=$abc$24881$procmux$2451_Y[0] Q=o_dbg_reg[0] R=$abc$24881$eq$./benchmark/zipcore.v:3393$815_Y -.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[4] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[4] -.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[5] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[5] -.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[6] -.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[4] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[0] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] -.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[5] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[1] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] -.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[2] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23656 Q=GEN_UHALT_PHASE.r_uhalt_phase R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[0] Q=regset[4][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[1] Q=regset[4][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[2] Q=regset[4][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[3] Q=regset[4][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[4] Q=regset[4][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[5] Q=regset[4][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[6] Q=regset[4][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[7] Q=regset[4][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[8] Q=regset[4][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[9] Q=regset[4][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[10] Q=regset[4][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[11] Q=regset[4][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[12] Q=regset[4][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[13] Q=regset[4][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[14] Q=regset[4][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[15] Q=regset[4][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[16] Q=regset[4][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[17] Q=regset[4][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[18] Q=regset[4][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[19] Q=regset[4][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[20] Q=regset[4][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[21] Q=regset[4][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[22] Q=regset[4][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[23] Q=regset[4][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[24] Q=regset[4][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[25] Q=regset[4][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[26] Q=regset[4][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[27] Q=regset[4][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[28] Q=regset[4][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[29] Q=regset[4][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[30] Q=regset[4][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[31] Q=regset[4][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[0] Q=regset[11][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[1] Q=regset[11][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[2] Q=regset[11][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[3] Q=regset[11][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[4] Q=regset[11][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[5] Q=regset[11][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[6] Q=regset[11][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[7] Q=regset[11][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[8] Q=regset[11][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[9] Q=regset[11][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[10] Q=regset[11][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[11] Q=regset[11][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[12] Q=regset[11][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[13] Q=regset[11][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[14] Q=regset[11][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[15] Q=regset[11][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[16] Q=regset[11][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[17] Q=regset[11][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[18] Q=regset[11][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[19] Q=regset[11][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[20] Q=regset[11][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[21] Q=regset[11][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[22] Q=regset[11][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[23] Q=regset[11][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[24] Q=regset[11][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[25] Q=regset[11][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[26] Q=regset[11][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[27] Q=regset[11][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[28] Q=regset[11][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[29] Q=regset[11][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[30] Q=regset[11][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[31] Q=regset[11][31] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][1] Q=o_dbg_reg[1] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][2] Q=o_dbg_reg[2] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][3] Q=o_dbg_reg[3] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][4] Q=o_dbg_reg[4] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][5] Q=o_dbg_reg[5] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][6] Q=o_dbg_reg[6] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][7] Q=o_dbg_reg[7] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][8] Q=o_dbg_reg[8] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][9] Q=o_dbg_reg[9] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][10] Q=o_dbg_reg[10] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][11] Q=o_dbg_reg[11] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][12] Q=o_dbg_reg[12] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][13] Q=o_dbg_reg[13] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][14] Q=o_dbg_reg[14] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][15] Q=o_dbg_reg[15] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][16] Q=o_dbg_reg[16] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][17] Q=o_dbg_reg[17] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][18] Q=o_dbg_reg[18] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][19] Q=o_dbg_reg[19] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][20] Q=o_dbg_reg[20] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][21] Q=o_dbg_reg[21] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][22] Q=o_dbg_reg[22] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][23] Q=o_dbg_reg[23] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][24] Q=o_dbg_reg[24] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][25] Q=o_dbg_reg[25] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][26] Q=o_dbg_reg[26] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][27] Q=o_dbg_reg[27] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][28] Q=o_dbg_reg[28] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][29] Q=o_dbg_reg[29] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][30] Q=o_dbg_reg[30] -.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][31] Q=o_dbg_reg[31] -.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1613$573_Y Q=alu_wF R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3485 -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[0] Q=regset[5][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[1] Q=regset[5][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[2] Q=regset[5][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[3] Q=regset[5][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[4] Q=regset[5][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[5] Q=regset[5][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[6] Q=regset[5][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[7] Q=regset[5][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[8] Q=regset[5][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[9] Q=regset[5][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[10] Q=regset[5][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[11] Q=regset[5][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[12] Q=regset[5][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[13] Q=regset[5][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[14] Q=regset[5][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[15] Q=regset[5][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[16] Q=regset[5][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[17] Q=regset[5][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[18] Q=regset[5][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[19] Q=regset[5][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[20] Q=regset[5][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[21] Q=regset[5][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[22] Q=regset[5][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[23] Q=regset[5][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[24] Q=regset[5][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[25] Q=regset[5][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[26] Q=regset[5][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[27] Q=regset[5][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[28] Q=regset[5][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[29] Q=regset[5][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[30] Q=regset[5][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[31] Q=regset[5][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[0] Q=regset[10][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[1] Q=regset[10][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[2] Q=regset[10][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[3] Q=regset[10][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[4] Q=regset[10][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[5] Q=regset[10][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[6] Q=regset[10][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[7] Q=regset[10][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[8] Q=regset[10][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[9] Q=regset[10][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[10] Q=regset[10][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[11] Q=regset[10][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[12] Q=regset[10][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[13] Q=regset[10][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[14] Q=regset[10][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[15] Q=regset[10][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[16] Q=regset[10][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[17] Q=regset[10][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[18] Q=regset[10][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[19] Q=regset[10][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[20] Q=regset[10][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[21] Q=regset[10][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[22] Q=regset[10][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[23] Q=regset[10][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[24] Q=regset[10][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[25] Q=regset[10][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[26] Q=regset[10][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[27] Q=regset[10][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[28] Q=regset[10][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[29] Q=regset[10][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[30] Q=regset[10][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[31] Q=regset[10][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[0] Q=regset[27][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[1] Q=regset[27][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[2] Q=regset[27][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[3] Q=regset[27][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[4] Q=regset[27][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[5] Q=regset[27][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[6] Q=regset[27][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[7] Q=regset[27][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[8] Q=regset[27][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[9] Q=regset[27][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[10] Q=regset[27][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[11] Q=regset[27][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[12] Q=regset[27][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[13] Q=regset[27][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[14] Q=regset[27][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[15] Q=regset[27][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[16] Q=regset[27][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[17] Q=regset[27][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[18] Q=regset[27][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[19] Q=regset[27][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[20] Q=regset[27][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[21] Q=regset[27][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[22] Q=regset[27][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[23] Q=regset[27][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[24] Q=regset[27][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[25] Q=regset[27][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[26] Q=regset[27][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[27] Q=regset[27][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[28] Q=regset[27][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[29] Q=regset[27][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[30] Q=regset[27][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[31] Q=regset[27][31] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23314 Q=GEN_ALU_PC.r_alu_pc[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23312 Q=GEN_ALU_PC.r_alu_pc[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23310 Q=GEN_ALU_PC.r_alu_pc[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23308 Q=GEN_ALU_PC.r_alu_pc[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23306 Q=GEN_ALU_PC.r_alu_pc[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23304 Q=GEN_ALU_PC.r_alu_pc[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23302 Q=GEN_ALU_PC.r_alu_pc[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23300 Q=GEN_ALU_PC.r_alu_pc[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23298 Q=GEN_ALU_PC.r_alu_pc[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23296 Q=GEN_ALU_PC.r_alu_pc[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23294 Q=GEN_ALU_PC.r_alu_pc[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23292 Q=GEN_ALU_PC.r_alu_pc[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23290 Q=GEN_ALU_PC.r_alu_pc[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23288 Q=GEN_ALU_PC.r_alu_pc[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23286 Q=GEN_ALU_PC.r_alu_pc[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23284 Q=GEN_ALU_PC.r_alu_pc[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23282 Q=GEN_ALU_PC.r_alu_pc[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23280 Q=GEN_ALU_PC.r_alu_pc[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23278 Q=GEN_ALU_PC.r_alu_pc[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23276 Q=GEN_ALU_PC.r_alu_pc[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23274 Q=GEN_ALU_PC.r_alu_pc[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23272 Q=GEN_ALU_PC.r_alu_pc[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23270 Q=GEN_ALU_PC.r_alu_pc[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23268 Q=GEN_ALU_PC.r_alu_pc[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23266 Q=GEN_ALU_PC.r_alu_pc[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23264 Q=GEN_ALU_PC.r_alu_pc[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23262 Q=GEN_ALU_PC.r_alu_pc[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23260 Q=GEN_ALU_PC.r_alu_pc[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23258 Q=GEN_ALU_PC.r_alu_pc[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23740 Q=GEN_ALU_PC.r_alu_pc[31] -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[0] Q=alu_result[0] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[1] Q=alu_result[1] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[2] Q=alu_result[2] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[3] Q=alu_result[3] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[4] Q=alu_result[4] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[5] Q=alu_result[5] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[6] Q=alu_result[6] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[7] Q=alu_result[7] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[8] Q=alu_result[8] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[9] Q=alu_result[9] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[10] Q=alu_result[10] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[11] Q=alu_result[11] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[12] Q=alu_result[12] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[13] Q=alu_result[13] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[14] Q=alu_result[14] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[15] Q=alu_result[15] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[16] Q=alu_result[16] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[17] Q=alu_result[17] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[18] Q=alu_result[18] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[19] Q=alu_result[19] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[20] Q=alu_result[20] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[21] Q=alu_result[21] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[22] Q=alu_result[22] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[23] Q=alu_result[23] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[24] Q=alu_result[24] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[25] Q=alu_result[25] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[26] Q=alu_result[26] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[27] Q=alu_result[27] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[28] Q=alu_result[28] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[29] Q=alu_result[29] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[30] Q=alu_result[30] RN=alu_ce -.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[31] Q=doalu.n RN=alu_ce -.subckt sdffr C=i_clk D=$abc$24881$memory$auto$proc_rom.cc:150:do_switch$1988$rdmux[0][1][0]$b$3899[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[3] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$4528 -.subckt sdffs C=i_clk D=$abc$24881$procmux$2428_Y Q=r_halted S=i_reset -.subckt sdffr C=i_clk D=$abc$24881$procmux$2463_Y Q=o_clear_dcache R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23658 Q=GEN_IHALT_PHASE.r_ihalt_phase R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23660 Q=DIVERR.USER_DIVERR.r_udiv_err_flag R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23662 Q=DIVERR.r_idiv_err_flag R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23664 Q=SET_USER_BUSERR.r_ubus_err_flag R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23666 Q=SET_USER_ILLEGAL_INSN.r_ill_err_u R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23668 Q=SET_TRAP_N_UBREAK.r_ubreak R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23670 Q=SET_TRAP_N_UBREAK.r_trap R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23672 Q=SET_GIE.r_gie R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3432 -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23674 Q=GEN_PENDING_INTERRUPT.r_pending_interrupt R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3429 -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23676 Q=GEN_PENDING_INTERRUPT.r_user_stepped R=$abc$24881$logic_or$./benchmark/zipcore.v:2741$689_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23678 Q=sleep R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3432 -.subckt sdffr C=i_clk D=$abc$24881$procmux$2578_Y Q=GEN_CLOCK_GATE.r_clken R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23680 Q=GEN_PENDING_BREAK.r_break_pending R=$abc$24881$logic_or$./benchmark/zipcore.v:2501$630_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23256 Q=BUSLOCK.r_bus_lock[0] R=new_pc -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23682 Q=BUSLOCK.r_bus_lock[1] R=new_pc -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23254 Q=dcd_I[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23252 Q=dcd_I[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23250 Q=dcd_I[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23248 Q=dcd_I[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23246 Q=dcd_I[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23244 Q=dcd_I[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23242 Q=dcd_I[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23240 Q=dcd_I[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23238 Q=dcd_I[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23236 Q=dcd_I[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23234 Q=dcd_I[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23232 Q=dcd_I[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23230 Q=dcd_I[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23228 Q=dcd_I[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23226 Q=dcd_I[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23224 Q=dcd_I[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23222 Q=dcd_I[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23220 Q=dcd_I[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23218 Q=dcd_I[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23216 Q=dcd_I[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23214 Q=dcd_I[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23212 Q=dcd_I[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23584 Q=dcd_I[31] -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23684 Q=BUSLOCK.r_prelock_stall R=new_pc -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23686 Q=GEN_ALU_PHASE.r_alu_phase R=DIVIDE.thedivide.i_reset -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23210 Q=o_mem_lock_pc[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23208 Q=o_mem_lock_pc[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23206 Q=o_mem_lock_pc[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23204 Q=o_mem_lock_pc[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23202 Q=o_mem_lock_pc[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23200 Q=o_mem_lock_pc[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23198 Q=o_mem_lock_pc[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23196 Q=o_mem_lock_pc[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23194 Q=o_mem_lock_pc[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23192 Q=o_mem_lock_pc[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23190 Q=o_mem_lock_pc[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23188 Q=o_mem_lock_pc[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23186 Q=o_mem_lock_pc[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23184 Q=o_mem_lock_pc[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23182 Q=o_mem_lock_pc[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23180 Q=o_mem_lock_pc[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23178 Q=o_mem_lock_pc[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23176 Q=o_mem_lock_pc[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23174 Q=o_mem_lock_pc[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23172 Q=o_mem_lock_pc[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23170 Q=o_mem_lock_pc[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23168 Q=o_mem_lock_pc[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23166 Q=o_mem_lock_pc[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23164 Q=o_mem_lock_pc[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23162 Q=o_mem_lock_pc[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23160 Q=o_mem_lock_pc[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23158 Q=o_mem_lock_pc[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23156 Q=o_mem_lock_pc[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23154 Q=o_mem_lock_pc[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23152 Q=o_mem_lock_pc[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23742 Q=o_mem_lock_pc[31] -.subckt sdffr C=i_clk D=op_illegal Q=SET_ALU_ILLEGAL.r_alu_illegal R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3420 -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23688 Q=OPT_CIS_OP_PHASE.r_op_phase R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$procmux$2659_Y Q=alu_wR R=i_reset -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23150 Q=DIVIDE.thedivide.i_signed -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23146 Q=o_mem_op[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23142 Q=o_mem_op[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23576 Q=FWD_OPERATION.r_op_opn[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23138 Q=alu_reg[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23136 Q=alu_reg[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23134 Q=alu_reg[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23132 Q=alu_reg[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23578 Q=alu_reg[4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[0] Q=regset[25][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[1] Q=regset[25][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[2] Q=regset[25][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[3] Q=regset[25][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[4] Q=regset[25][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[5] Q=regset[25][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[6] Q=regset[25][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[7] Q=regset[25][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[8] Q=regset[25][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[9] Q=regset[25][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[10] Q=regset[25][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[11] Q=regset[25][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[12] Q=regset[25][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[13] Q=regset[25][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[14] Q=regset[25][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[15] Q=regset[25][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[16] Q=regset[25][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[17] Q=regset[25][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[18] Q=regset[25][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[19] Q=regset[25][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[20] Q=regset[25][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[21] Q=regset[25][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[22] Q=regset[25][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[23] Q=regset[25][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[24] Q=regset[25][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[25] Q=regset[25][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[26] Q=regset[25][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[27] Q=regset[25][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[28] Q=regset[25][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[29] Q=regset[25][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[30] Q=regset[25][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[31] Q=regset[25][31] -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23690 Q=GEN_OPLOCK.r_op_lock R=new_pc -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23572 Q=GEN_OP_WR.r_op_wR -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23728 Q=SET_OP_PC.r_op_pc[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23130 Q=o_mem_reg[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23128 Q=o_mem_reg[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23126 Q=o_mem_reg[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23124 Q=o_mem_reg[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23570 Q=o_mem_reg[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23122 Q=OP_REG_ADVANEC.r_op_Bid[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23120 Q=OP_REG_ADVANEC.r_op_Bid[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23118 Q=OP_REG_ADVANEC.r_op_Bid[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23116 Q=OP_REG_ADVANEC.r_op_Bid[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23568 Q=OP_REG_ADVANEC.r_op_Bid[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23566 Q=OP_REG_ADVANEC.r_op_rA -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23692 Q=GEN_OP_PIPE.r_op_pipe R=$abc$24881$logic_or$./benchmark/zipcore.v:728$452_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23694 Q=GEN_OP_STALL.r_pending_sreg_write R=new_pc -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23114 Q=ipc[2] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23112 Q=ipc[3] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23110 Q=ipc[4] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23108 Q=ipc[5] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23106 Q=ipc[6] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23104 Q=ipc[7] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23102 Q=ipc[8] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23100 Q=ipc[9] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23098 Q=ipc[10] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23096 Q=ipc[11] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23094 Q=ipc[12] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23092 Q=ipc[13] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23090 Q=ipc[14] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23088 Q=ipc[15] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23086 Q=ipc[16] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23084 Q=ipc[17] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23082 Q=ipc[18] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23080 Q=ipc[19] R=i_reset -.subckt sdffs C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23078 Q=ipc[20] S=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23076 Q=ipc[21] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23074 Q=ipc[22] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23072 Q=ipc[23] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23070 Q=ipc[24] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23068 Q=ipc[25] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23066 Q=ipc[26] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23064 Q=ipc[27] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23062 Q=ipc[28] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23060 Q=ipc[29] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23058 Q=ipc[30] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23696 Q=ipc[31] R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$procmux$2728_Y Q=GEN_OP_STALL.r_cc_invalid_for_dcd R=new_pc -.subckt dff C=i_clk D=sleep Q=o_dbg_cc[0] -.subckt dff C=i_clk D=SET_GIE.r_gie Q=o_dbg_cc[1] -.subckt dff C=i_clk D=i_bus_err Q=o_dbg_cc[2] -.subckt sdffs C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y Q=r_dbg_stall S=$abc$24881$auto$opt_dff.cc:253:combine_resets$3407 -.subckt sdffs C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y Q=new_pc S=$abc$24881$auto$opt_dff.cc:253:combine_resets$3404 -.subckt sdffr C=i_clk D=$abc$24881$procmux$2755_Y Q=o_clear_icache R=i_reset -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23564 Q=OP_REG_ADVANEC.r_op_rB -.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y Q=last_write_to_cc R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23698 Q=ibus_err_flag R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23700 Q=ill_err_i R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23702 Q=user_step R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23704 Q=break_en R=i_reset -.subckt dff C=i_clk D=$0\iflags[3:0][0] Q=iflags[0] -.subckt dff C=i_clk D=$0\iflags[3:0][1] Q=iflags[1] -.subckt dff C=i_clk D=$0\iflags[3:0][2] Q=iflags[2] -.subckt dff C=i_clk D=$0\iflags[3:0][3] Q=iflags[3] -.subckt dff C=i_clk D=$0\flags[3:0][0] Q=flags[0] -.subckt dff C=i_clk D=$0\flags[3:0][1] Q=flags[1] -.subckt dff C=i_clk D=$0\flags[3:0][2] Q=flags[2] -.subckt dff C=i_clk D=$0\flags[3:0][3] Q=flags[3] -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23706 Q=r_alu_pc_valid R=new_pc -.subckt sdffr C=i_clk D=mem_ce Q=mem_pc_valid R=i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23056 Q=wr_index[0] R=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23708 Q=wr_index[1] R=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y -.subckt dff C=i_clk D=i_dbg_data[0] Q=dbg_val[0] -.subckt dff C=i_clk D=i_dbg_data[1] Q=dbg_val[1] -.subckt dff C=i_clk D=i_dbg_data[2] Q=dbg_val[2] -.subckt dff C=i_clk D=i_dbg_data[3] Q=dbg_val[3] -.subckt dff C=i_clk D=i_dbg_data[4] Q=dbg_val[4] -.subckt dff C=i_clk D=i_dbg_data[5] Q=dbg_val[5] -.subckt dff C=i_clk D=i_dbg_data[6] Q=dbg_val[6] -.subckt dff C=i_clk D=i_dbg_data[7] Q=dbg_val[7] -.subckt dff C=i_clk D=i_dbg_data[8] Q=dbg_val[8] -.subckt dff C=i_clk D=i_dbg_data[9] Q=dbg_val[9] -.subckt dff C=i_clk D=i_dbg_data[10] Q=dbg_val[10] -.subckt dff C=i_clk D=i_dbg_data[11] Q=dbg_val[11] -.subckt dff C=i_clk D=i_dbg_data[12] Q=dbg_val[12] -.subckt dff C=i_clk D=i_dbg_data[13] Q=dbg_val[13] -.subckt dff C=i_clk D=i_dbg_data[14] Q=dbg_val[14] -.subckt dff C=i_clk D=i_dbg_data[15] Q=dbg_val[15] -.subckt dff C=i_clk D=i_dbg_data[16] Q=dbg_val[16] -.subckt dff C=i_clk D=i_dbg_data[17] Q=dbg_val[17] -.subckt dff C=i_clk D=i_dbg_data[18] Q=dbg_val[18] -.subckt dff C=i_clk D=i_dbg_data[19] Q=dbg_val[19] -.subckt dff C=i_clk D=i_dbg_data[20] Q=dbg_val[20] -.subckt dff C=i_clk D=i_dbg_data[21] Q=dbg_val[21] -.subckt dff C=i_clk D=i_dbg_data[22] Q=dbg_val[22] -.subckt dff C=i_clk D=i_dbg_data[23] Q=dbg_val[23] -.subckt dff C=i_clk D=i_dbg_data[24] Q=dbg_val[24] -.subckt dff C=i_clk D=i_dbg_data[25] Q=dbg_val[25] -.subckt dff C=i_clk D=i_dbg_data[26] Q=dbg_val[26] -.subckt dff C=i_clk D=i_dbg_data[27] Q=dbg_val[27] -.subckt dff C=i_clk D=i_dbg_data[28] Q=dbg_val[28] -.subckt dff C=i_clk D=i_dbg_data[29] Q=dbg_val[29] -.subckt dff C=i_clk D=i_dbg_data[30] Q=dbg_val[30] -.subckt dff C=i_clk D=i_dbg_data[31] Q=dbg_val[31] -.subckt sdffr C=i_clk D=$abc$24881$procmux$3022_Y Q=dbg_clear_pipe R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3389 -.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y Q=dbgv R=$abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23054 Q=SET_OP_PC.r_op_pc[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23052 Q=SET_OP_PC.r_op_pc[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23050 Q=SET_OP_PC.r_op_pc[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23048 Q=SET_OP_PC.r_op_pc[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23046 Q=SET_OP_PC.r_op_pc[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23044 Q=SET_OP_PC.r_op_pc[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23042 Q=SET_OP_PC.r_op_pc[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23040 Q=SET_OP_PC.r_op_pc[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23038 Q=SET_OP_PC.r_op_pc[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23036 Q=SET_OP_PC.r_op_pc[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23034 Q=SET_OP_PC.r_op_pc[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23032 Q=SET_OP_PC.r_op_pc[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23030 Q=SET_OP_PC.r_op_pc[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23028 Q=SET_OP_PC.r_op_pc[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23026 Q=SET_OP_PC.r_op_pc[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23024 Q=SET_OP_PC.r_op_pc[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23022 Q=SET_OP_PC.r_op_pc[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23020 Q=SET_OP_PC.r_op_pc[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23018 Q=SET_OP_PC.r_op_pc[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23016 Q=SET_OP_PC.r_op_pc[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23014 Q=SET_OP_PC.r_op_pc[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23012 Q=SET_OP_PC.r_op_pc[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23010 Q=SET_OP_PC.r_op_pc[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23008 Q=SET_OP_PC.r_op_pc[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23006 Q=SET_OP_PC.r_op_pc[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23004 Q=SET_OP_PC.r_op_pc[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23002 Q=SET_OP_PC.r_op_pc[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23000 Q=SET_OP_PC.r_op_pc[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22998 Q=SET_OP_PC.r_op_pc[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23738 Q=SET_OP_PC.r_op_pc[31] -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23710 Q=op_illegal R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23712 Q=r_op_break R=new_pc -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23714 Q=op_valid R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23716 Q=op_valid_mem R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23718 Q=op_valid_alu R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23720 Q=op_valid_div R=DIVIDE.thedivide.i_reset -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23562 Q=op_wF -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22996 Q=r_op_F[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22994 Q=r_op_F[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22992 Q=r_op_F[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22990 Q=r_op_F[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22988 Q=r_op_F[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22986 Q=r_op_F[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23560 Q=r_op_F[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22984 Q=r_op_Bv[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22982 Q=r_op_Bv[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22980 Q=r_op_Bv[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22978 Q=r_op_Bv[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22976 Q=r_op_Bv[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22974 Q=r_op_Bv[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22972 Q=r_op_Bv[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22970 Q=r_op_Bv[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22968 Q=r_op_Bv[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22966 Q=r_op_Bv[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22964 Q=r_op_Bv[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22962 Q=r_op_Bv[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22960 Q=r_op_Bv[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22958 Q=r_op_Bv[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22956 Q=r_op_Bv[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22954 Q=r_op_Bv[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22952 Q=r_op_Bv[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22950 Q=r_op_Bv[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22948 Q=r_op_Bv[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22946 Q=r_op_Bv[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22944 Q=r_op_Bv[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22942 Q=r_op_Bv[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22940 Q=r_op_Bv[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22938 Q=r_op_Bv[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22936 Q=r_op_Bv[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22934 Q=r_op_Bv[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22932 Q=r_op_Bv[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22930 Q=r_op_Bv[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22928 Q=r_op_Bv[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22926 Q=r_op_Bv[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22924 Q=r_op_Bv[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23558 Q=r_op_Bv[31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[0] Q=regset[23][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[1] Q=regset[23][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[2] Q=regset[23][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[3] Q=regset[23][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[4] Q=regset[23][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[5] Q=regset[23][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[6] Q=regset[23][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[7] Q=regset[23][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[8] Q=regset[23][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[9] Q=regset[23][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[10] Q=regset[23][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[11] Q=regset[23][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[12] Q=regset[23][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[13] Q=regset[23][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[14] Q=regset[23][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[15] Q=regset[23][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[16] Q=regset[23][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[17] Q=regset[23][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[18] Q=regset[23][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[19] Q=regset[23][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[20] Q=regset[23][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[21] Q=regset[23][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[22] Q=regset[23][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[23] Q=regset[23][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[24] Q=regset[23][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[25] Q=regset[23][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[26] Q=regset[23][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[27] Q=regset[23][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[28] Q=regset[23][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[29] Q=regset[23][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[30] Q=regset[23][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[31] Q=regset[23][31] -.subckt dff C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$0\r_dividend[62:0][31] Q=DIVIDE.thedivide.r_dividend[31] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23618 Q=doalu.set_ovfl -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23636 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp R=instruction_decoder.i_reset -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23610 Q=dcd_zI -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23608 Q=dcd_F[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22922 Q=dcd_opn[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22918 Q=dcd_opn[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22914 Q=dcd_opn[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23604 Q=dcd_opn[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23606 Q=dcd_wF -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23592 Q=dcd_wR -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23588 Q=dcd_rB -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23600 Q=dcd_ALU -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23598 Q=dcd_M -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22910 Q=instruction_decoder.r_nxt_half[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22908 Q=instruction_decoder.r_nxt_half[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22906 Q=instruction_decoder.r_nxt_half[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22904 Q=instruction_decoder.r_nxt_half[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22902 Q=instruction_decoder.r_nxt_half[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22900 Q=instruction_decoder.r_nxt_half[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22898 Q=instruction_decoder.r_nxt_half[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22896 Q=instruction_decoder.r_nxt_half[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22894 Q=instruction_decoder.r_nxt_half[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22892 Q=instruction_decoder.r_nxt_half[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22890 Q=instruction_decoder.r_nxt_half[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22888 Q=instruction_decoder.r_nxt_half[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22886 Q=instruction_decoder.r_nxt_half[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22884 Q=instruction_decoder.r_nxt_half[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23586 Q=instruction_decoder.r_nxt_half[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23590 Q=dcd_rA -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23582 Q=instruction_decoder.o_pc[1] -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23640 Q=instruction_decoder.o_illegal R=instruction_decoder.i_reset -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22882 Q=instruction_decoder.o_dcdA[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22880 Q=instruction_decoder.o_dcdA[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22878 Q=instruction_decoder.o_dcdA[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22876 Q=instruction_decoder.o_dcdA[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22874 Q=instruction_decoder.o_dcdA[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22872 Q=dcd_Apc -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23614 Q=dcd_Acc -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22870 Q=instruction_decoder.o_dcdB[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22868 Q=instruction_decoder.o_dcdB[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22866 Q=instruction_decoder.o_dcdB[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22864 Q=instruction_decoder.o_dcdB[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22862 Q=instruction_decoder.o_dcdB[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22860 Q=dcd_Bpc -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23612 Q=dcd_Bcc -.subckt sdffr C=i_clk D=$abc$24881$flatten\instruction_decoder.$procmux$2071_Y Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3474 -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23638 Q=instruction_decoder.GEN_CIS_PHASE.r_phase R=$abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23616 Q=dcd_break -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[0] Q=regset[28][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[1] Q=regset[28][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[2] Q=regset[28][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[3] Q=regset[28][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[4] Q=regset[28][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[5] Q=regset[28][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[6] Q=regset[28][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[7] Q=regset[28][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[8] Q=regset[28][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[9] Q=regset[28][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[10] Q=regset[28][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[11] Q=regset[28][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[12] Q=regset[28][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[13] Q=regset[28][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[14] Q=regset[28][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[15] Q=regset[28][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[16] Q=regset[28][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[17] Q=regset[28][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[18] Q=regset[28][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[19] Q=regset[28][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[20] Q=regset[28][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[21] Q=regset[28][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[22] Q=regset[28][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[23] Q=regset[28][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[24] Q=regset[28][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[25] Q=regset[28][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[26] Q=regset[28][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[27] Q=regset[28][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[28] Q=regset[28][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[29] Q=regset[28][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[30] Q=regset[28][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[31] Q=regset[28][31] -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23630 Q=instruction_decoder.GEN_OPIPE.r_pipe R=instruction_decoder.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23632 Q=instruction_decoder.GEN_OPIPE.r_insn_is_pipeable R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3478 -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23634 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch R=instruction_decoder.i_reset -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23596 Q=instruction_decoder.o_DV -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23594 Q=instruction_decoder.o_lock -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22858 Q=pf_pc[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22856 Q=pf_pc[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22854 Q=pf_pc[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22852 Q=pf_pc[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22850 Q=pf_pc[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22848 Q=pf_pc[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22846 Q=pf_pc[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22844 Q=pf_pc[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22842 Q=pf_pc[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22840 Q=pf_pc[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22838 Q=pf_pc[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22836 Q=pf_pc[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22834 Q=pf_pc[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22832 Q=pf_pc[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22830 Q=pf_pc[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22828 Q=pf_pc[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22826 Q=pf_pc[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22824 Q=pf_pc[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22822 Q=pf_pc[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22820 Q=pf_pc[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22818 Q=pf_pc[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22816 Q=pf_pc[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22814 Q=pf_pc[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22812 Q=pf_pc[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22810 Q=pf_pc[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22808 Q=pf_pc[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22806 Q=pf_pc[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22804 Q=pf_pc[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22802 Q=pf_pc[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23736 Q=pf_pc[31] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23626 Q=DIVIDE.thedivide.zero_divisor -.subckt sdffr C=i_clk D=alu_ce Q=doalu.o_valid R=DIVIDE.thedivide.i_reset -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22800 Q=SET_USER_PC.r_upc[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22798 Q=SET_USER_PC.r_upc[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22796 Q=SET_USER_PC.r_upc[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22794 Q=SET_USER_PC.r_upc[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22792 Q=SET_USER_PC.r_upc[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22790 Q=SET_USER_PC.r_upc[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22788 Q=SET_USER_PC.r_upc[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22786 Q=SET_USER_PC.r_upc[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22784 Q=SET_USER_PC.r_upc[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22782 Q=SET_USER_PC.r_upc[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22780 Q=SET_USER_PC.r_upc[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22778 Q=SET_USER_PC.r_upc[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22776 Q=SET_USER_PC.r_upc[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22774 Q=SET_USER_PC.r_upc[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22772 Q=SET_USER_PC.r_upc[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22770 Q=SET_USER_PC.r_upc[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22768 Q=SET_USER_PC.r_upc[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22766 Q=SET_USER_PC.r_upc[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22764 Q=SET_USER_PC.r_upc[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22762 Q=SET_USER_PC.r_upc[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22760 Q=SET_USER_PC.r_upc[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22758 Q=SET_USER_PC.r_upc[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22756 Q=SET_USER_PC.r_upc[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22754 Q=SET_USER_PC.r_upc[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22752 Q=SET_USER_PC.r_upc[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22750 Q=SET_USER_PC.r_upc[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22748 Q=SET_USER_PC.r_upc[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22746 Q=SET_USER_PC.r_upc[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22744 Q=SET_USER_PC.r_upc[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23654 Q=SET_USER_PC.r_upc[31] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23622 Q=doalu.c -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23620 Q=doalu.keep_sgn_on_ovfl -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23624 Q=doalu.pre_sign -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22742 Q=DIVIDE.thedivide.r_dividend[33] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22738 Q=DIVIDE.thedivide.r_dividend[34] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22734 Q=DIVIDE.thedivide.r_dividend[35] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22730 Q=DIVIDE.thedivide.r_dividend[36] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22726 Q=DIVIDE.thedivide.r_dividend[37] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22722 Q=DIVIDE.thedivide.r_dividend[38] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22718 Q=DIVIDE.thedivide.r_dividend[39] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22714 Q=DIVIDE.thedivide.r_dividend[40] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22710 Q=DIVIDE.thedivide.r_dividend[41] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22706 Q=DIVIDE.thedivide.r_dividend[42] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22702 Q=DIVIDE.thedivide.r_dividend[43] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22698 Q=DIVIDE.thedivide.r_dividend[44] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22694 Q=DIVIDE.thedivide.r_dividend[45] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22690 Q=DIVIDE.thedivide.r_dividend[46] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22686 Q=DIVIDE.thedivide.r_dividend[47] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22682 Q=DIVIDE.thedivide.r_dividend[48] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22678 Q=DIVIDE.thedivide.r_dividend[49] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22674 Q=DIVIDE.thedivide.r_dividend[50] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22670 Q=DIVIDE.thedivide.r_dividend[51] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22666 Q=DIVIDE.thedivide.r_dividend[52] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22662 Q=DIVIDE.thedivide.r_dividend[53] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22658 Q=DIVIDE.thedivide.r_dividend[54] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22654 Q=DIVIDE.thedivide.r_dividend[55] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22650 Q=DIVIDE.thedivide.r_dividend[56] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22646 Q=DIVIDE.thedivide.r_dividend[57] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22642 Q=DIVIDE.thedivide.r_dividend[58] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22638 Q=DIVIDE.thedivide.r_dividend[59] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22634 Q=DIVIDE.thedivide.r_dividend[60] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22630 Q=DIVIDE.thedivide.r_dividend[61] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23732 Q=DIVIDE.thedivide.r_dividend[62] -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.X[0] Q=DIVIDE.thedivide.r_bit[0] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[1] Q=DIVIDE.thedivide.r_bit[1] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[2] Q=DIVIDE.thedivide.r_bit[2] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[3] Q=DIVIDE.thedivide.r_bit[3] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 -.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[4] Q=DIVIDE.thedivide.r_bit[4] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$eq$./benchmark/div.v:248$1635_Y Q=DIVIDE.thedivide.last_bit R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3460 -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:263$1639_Y Q=DIVIDE.thedivide.pre_sign R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23648 Q=DIVIDE.thedivide.o_valid R=$abc$24881$flatten\DIVIDE.thedivide.$logic_or$./benchmark/div.v:189$1625_Y -.subckt sdffs C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23646 Q=DIVIDE.thedivide.r_z S=DIVIDE.thedivide.i_wr -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23628 Q=instruction_decoder.r_valid R=instruction_decoder.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2314_Y Q=DIVIDE.thedivide.r_sign R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2305_Y Q=DIVIDE.thedivide.o_quotient[0] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[0] Q=DIVIDE.thedivide.o_quotient[1] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[1] Q=DIVIDE.thedivide.o_quotient[2] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[2] Q=DIVIDE.thedivide.o_quotient[3] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[3] Q=DIVIDE.thedivide.o_quotient[4] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[4] Q=DIVIDE.thedivide.o_quotient[5] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[5] Q=DIVIDE.thedivide.o_quotient[6] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[6] Q=DIVIDE.thedivide.o_quotient[7] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[7] Q=DIVIDE.thedivide.o_quotient[8] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[8] Q=DIVIDE.thedivide.o_quotient[9] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[9] Q=DIVIDE.thedivide.o_quotient[10] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[10] Q=DIVIDE.thedivide.o_quotient[11] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[11] Q=DIVIDE.thedivide.o_quotient[12] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[12] Q=DIVIDE.thedivide.o_quotient[13] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[13] Q=DIVIDE.thedivide.o_quotient[14] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[14] Q=DIVIDE.thedivide.o_quotient[15] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[15] Q=DIVIDE.thedivide.o_quotient[16] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[16] Q=DIVIDE.thedivide.o_quotient[17] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[17] Q=DIVIDE.thedivide.o_quotient[18] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[18] Q=DIVIDE.thedivide.o_quotient[19] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[19] Q=DIVIDE.thedivide.o_quotient[20] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[20] Q=DIVIDE.thedivide.o_quotient[21] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[21] Q=DIVIDE.thedivide.o_quotient[22] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[22] Q=DIVIDE.thedivide.o_quotient[23] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[23] Q=DIVIDE.thedivide.o_quotient[24] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[24] Q=DIVIDE.thedivide.o_quotient[25] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[25] Q=DIVIDE.thedivide.o_quotient[26] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[26] Q=DIVIDE.thedivide.o_quotient[27] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[27] Q=DIVIDE.thedivide.o_quotient[28] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[28] Q=DIVIDE.thedivide.o_quotient[29] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[29] Q=DIVIDE.thedivide.o_quotient[30] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[30] Q=DIVIDE.thedivide.w_n R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:372$1666_Y Q=DIVIDE.thedivide.r_c R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23642 Q=DIVIDE.thedivide.r_divisor[31] R=DIVIDE.thedivide.i_reset -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[0] Q=regset[9][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[1] Q=regset[9][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[2] Q=regset[9][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[3] Q=regset[9][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[4] Q=regset[9][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[5] Q=regset[9][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[6] Q=regset[9][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[7] Q=regset[9][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[8] Q=regset[9][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[9] Q=regset[9][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[10] Q=regset[9][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[11] Q=regset[9][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[12] Q=regset[9][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[13] Q=regset[9][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[14] Q=regset[9][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[15] Q=regset[9][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[16] Q=regset[9][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[17] Q=regset[9][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[18] Q=regset[9][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[19] Q=regset[9][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[20] Q=regset[9][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[21] Q=regset[9][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[22] Q=regset[9][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[23] Q=regset[9][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[24] Q=regset[9][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[25] Q=regset[9][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[26] Q=regset[9][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[27] Q=regset[9][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[28] Q=regset[9][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[29] Q=regset[9][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[30] Q=regset[9][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[31] Q=regset[9][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[0] Q=regset[8][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[1] Q=regset[8][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[2] Q=regset[8][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[3] Q=regset[8][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[4] Q=regset[8][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[5] Q=regset[8][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[6] Q=regset[8][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[7] Q=regset[8][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[8] Q=regset[8][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[9] Q=regset[8][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[10] Q=regset[8][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[11] Q=regset[8][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[12] Q=regset[8][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[13] Q=regset[8][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[14] Q=regset[8][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[15] Q=regset[8][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[16] Q=regset[8][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[17] Q=regset[8][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[18] Q=regset[8][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[19] Q=regset[8][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[20] Q=regset[8][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[21] Q=regset[8][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[22] Q=regset[8][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[23] Q=regset[8][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[24] Q=regset[8][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[25] Q=regset[8][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[26] Q=regset[8][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[27] Q=regset[8][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[28] Q=regset[8][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[29] Q=regset[8][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[30] Q=regset[8][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[31] Q=regset[8][31] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22626 Q=DIVIDE.thedivide.r_dividend[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22624 Q=DIVIDE.thedivide.r_dividend[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22622 Q=DIVIDE.thedivide.r_dividend[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22620 Q=DIVIDE.thedivide.r_dividend[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22618 Q=DIVIDE.thedivide.r_dividend[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22616 Q=DIVIDE.thedivide.r_dividend[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22614 Q=DIVIDE.thedivide.r_dividend[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22612 Q=DIVIDE.thedivide.r_dividend[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22610 Q=DIVIDE.thedivide.r_dividend[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22608 Q=DIVIDE.thedivide.r_dividend[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22606 Q=DIVIDE.thedivide.r_dividend[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22604 Q=DIVIDE.thedivide.r_dividend[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22602 Q=DIVIDE.thedivide.r_dividend[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22600 Q=DIVIDE.thedivide.r_dividend[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22598 Q=DIVIDE.thedivide.r_dividend[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22596 Q=DIVIDE.thedivide.r_dividend[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22594 Q=DIVIDE.thedivide.r_dividend[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22592 Q=DIVIDE.thedivide.r_dividend[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22590 Q=DIVIDE.thedivide.r_dividend[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22588 Q=DIVIDE.thedivide.r_dividend[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22586 Q=DIVIDE.thedivide.r_dividend[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22584 Q=DIVIDE.thedivide.r_dividend[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22582 Q=DIVIDE.thedivide.r_dividend[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22580 Q=DIVIDE.thedivide.r_dividend[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22578 Q=DIVIDE.thedivide.r_dividend[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22576 Q=DIVIDE.thedivide.r_dividend[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22574 Q=DIVIDE.thedivide.r_dividend[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22572 Q=DIVIDE.thedivide.r_dividend[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22570 Q=DIVIDE.thedivide.r_dividend[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22568 Q=DIVIDE.thedivide.r_dividend[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22566 Q=DIVIDE.thedivide.r_dividend[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23734 Q=DIVIDE.thedivide.r_dividend[32] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[0] Q=regset[6][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[1] Q=regset[6][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[2] Q=regset[6][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[3] Q=regset[6][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[4] Q=regset[6][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[5] Q=regset[6][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[6] Q=regset[6][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[7] Q=regset[6][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[8] Q=regset[6][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[9] Q=regset[6][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[10] Q=regset[6][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[11] Q=regset[6][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[12] Q=regset[6][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[13] Q=regset[6][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[14] Q=regset[6][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[15] Q=regset[6][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[16] Q=regset[6][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[17] Q=regset[6][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[18] Q=regset[6][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[19] Q=regset[6][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[20] Q=regset[6][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[21] Q=regset[6][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[22] Q=regset[6][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[23] Q=regset[6][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[24] Q=regset[6][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[25] Q=regset[6][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[26] Q=regset[6][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[27] Q=regset[6][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[28] Q=regset[6][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[29] Q=regset[6][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[30] Q=regset[6][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[31] Q=regset[6][31] -.subckt sdffr C=i_clk D=$abc$24881$auto$simplemap.cc:240:simplemap_eqne$9293[0] Q=DIVIDE.thedivide.o_err R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23650 Q=DIVIDE.thedivide.o_busy R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23652 Q=DIVIDE.thedivide.r_busy R=DIVIDE.thedivide.i_reset -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[0] Q=regset[29][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[1] Q=regset[29][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[2] Q=regset[29][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[3] Q=regset[29][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[4] Q=regset[29][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[5] Q=regset[29][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[6] Q=regset[29][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[7] Q=regset[29][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[8] Q=regset[29][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[9] Q=regset[29][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[10] Q=regset[29][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[11] Q=regset[29][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[12] Q=regset[29][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[13] Q=regset[29][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[14] Q=regset[29][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[15] Q=regset[29][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[16] Q=regset[29][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[17] Q=regset[29][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[18] Q=regset[29][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[19] Q=regset[29][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[20] Q=regset[29][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[21] Q=regset[29][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[22] Q=regset[29][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[23] Q=regset[29][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[24] Q=regset[29][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[25] Q=regset[29][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[26] Q=regset[29][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[27] Q=regset[29][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[28] Q=regset[29][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[29] Q=regset[29][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[30] Q=regset[29][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[31] Q=regset[29][31] -.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][0] Q=dcd_F[0] -.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] Q=dcd_F[1] -.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] Q=dcd_F[2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[0] Q=regset[20][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[1] Q=regset[20][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[2] Q=regset[20][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[3] Q=regset[20][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[4] Q=regset[20][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[5] Q=regset[20][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[6] Q=regset[20][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[7] Q=regset[20][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[8] Q=regset[20][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[9] Q=regset[20][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[10] Q=regset[20][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[11] Q=regset[20][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[12] Q=regset[20][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[13] Q=regset[20][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[14] Q=regset[20][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[15] Q=regset[20][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[16] Q=regset[20][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[17] Q=regset[20][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[18] Q=regset[20][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[19] Q=regset[20][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[20] Q=regset[20][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[21] Q=regset[20][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[22] Q=regset[20][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[23] Q=regset[20][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[24] Q=regset[20][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[25] Q=regset[20][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[26] Q=regset[20][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[27] Q=regset[20][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[28] Q=regset[20][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[29] Q=regset[20][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[30] Q=regset[20][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[31] Q=regset[20][31] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23554 Q=instruction_decoder.o_pc[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23552 Q=instruction_decoder.o_pc[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23550 Q=instruction_decoder.o_pc[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23548 Q=instruction_decoder.o_pc[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23546 Q=instruction_decoder.o_pc[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23544 Q=instruction_decoder.o_pc[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23542 Q=instruction_decoder.o_pc[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23540 Q=instruction_decoder.o_pc[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23538 Q=instruction_decoder.o_pc[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23536 Q=instruction_decoder.o_pc[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23534 Q=instruction_decoder.o_pc[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23532 Q=instruction_decoder.o_pc[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23530 Q=instruction_decoder.o_pc[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23528 Q=instruction_decoder.o_pc[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23526 Q=instruction_decoder.o_pc[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23524 Q=instruction_decoder.o_pc[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23522 Q=instruction_decoder.o_pc[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23520 Q=instruction_decoder.o_pc[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23518 Q=instruction_decoder.o_pc[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23516 Q=instruction_decoder.o_pc[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23514 Q=instruction_decoder.o_pc[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23512 Q=instruction_decoder.o_pc[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23510 Q=instruction_decoder.o_pc[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23508 Q=instruction_decoder.o_pc[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23506 Q=instruction_decoder.o_pc[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23504 Q=instruction_decoder.o_pc[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23502 Q=instruction_decoder.o_pc[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23500 Q=instruction_decoder.o_pc[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23498 Q=instruction_decoder.o_pc[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23722 Q=instruction_decoder.o_pc[31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[0] Q=regset[7][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[1] Q=regset[7][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[2] Q=regset[7][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[3] Q=regset[7][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[4] Q=regset[7][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[5] Q=regset[7][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[6] Q=regset[7][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[7] Q=regset[7][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[8] Q=regset[7][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[9] Q=regset[7][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[10] Q=regset[7][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[11] Q=regset[7][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[12] Q=regset[7][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[13] Q=regset[7][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[14] Q=regset[7][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[15] Q=regset[7][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[16] Q=regset[7][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[17] Q=regset[7][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[18] Q=regset[7][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[19] Q=regset[7][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[20] Q=regset[7][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[21] Q=regset[7][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[22] Q=regset[7][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[23] Q=regset[7][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[24] Q=regset[7][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[25] Q=regset[7][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[26] Q=regset[7][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[27] Q=regset[7][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[28] Q=regset[7][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[29] Q=regset[7][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[30] Q=regset[7][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[31] Q=regset[7][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[0] Q=regset[31][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[1] Q=regset[31][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[2] Q=regset[31][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[3] Q=regset[31][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[4] Q=regset[31][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[5] Q=regset[31][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[6] Q=regset[31][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[7] Q=regset[31][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[8] Q=regset[31][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[9] Q=regset[31][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[10] Q=regset[31][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[11] Q=regset[31][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[12] Q=regset[31][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[13] Q=regset[31][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[14] Q=regset[31][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[15] Q=regset[31][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[16] Q=regset[31][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[17] Q=regset[31][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[18] Q=regset[31][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[19] Q=regset[31][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[20] Q=regset[31][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[21] Q=regset[31][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[22] Q=regset[31][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[23] Q=regset[31][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[24] Q=regset[31][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[25] Q=regset[31][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[26] Q=regset[31][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[27] Q=regset[31][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[28] Q=regset[31][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[29] Q=regset[31][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[30] Q=regset[31][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[31] Q=regset[31][31] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23496 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23494 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23492 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23490 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23488 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23486 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23484 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23482 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23480 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23478 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23476 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23474 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23472 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23470 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23468 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23466 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23464 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23462 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23460 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23458 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23456 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23454 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23452 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23450 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23448 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23446 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23444 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23442 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23440 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23724 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[0] Q=regset[21][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[1] Q=regset[21][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[2] Q=regset[21][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[3] Q=regset[21][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[4] Q=regset[21][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[5] Q=regset[21][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[6] Q=regset[21][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[7] Q=regset[21][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[8] Q=regset[21][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[9] Q=regset[21][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[10] Q=regset[21][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[11] Q=regset[21][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[12] Q=regset[21][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[13] Q=regset[21][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[14] Q=regset[21][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[15] Q=regset[21][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[16] Q=regset[21][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[17] Q=regset[21][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[18] Q=regset[21][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[19] Q=regset[21][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[20] Q=regset[21][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[21] Q=regset[21][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[22] Q=regset[21][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[23] Q=regset[21][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[24] Q=regset[21][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[25] Q=regset[21][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[26] Q=regset[21][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[27] Q=regset[21][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[28] Q=regset[21][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[29] Q=regset[21][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[30] Q=regset[21][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[31] Q=regset[21][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[0] Q=regset[24][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[1] Q=regset[24][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[2] Q=regset[24][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[3] Q=regset[24][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[4] Q=regset[24][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[5] Q=regset[24][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[6] Q=regset[24][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[7] Q=regset[24][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[8] Q=regset[24][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[9] Q=regset[24][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[10] Q=regset[24][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[11] Q=regset[24][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[12] Q=regset[24][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[13] Q=regset[24][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[14] Q=regset[24][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[15] Q=regset[24][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[16] Q=regset[24][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[17] Q=regset[24][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[18] Q=regset[24][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[19] Q=regset[24][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[20] Q=regset[24][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[21] Q=regset[24][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[22] Q=regset[24][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[23] Q=regset[24][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[24] Q=regset[24][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[25] Q=regset[24][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[26] Q=regset[24][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[27] Q=regset[24][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[28] Q=regset[24][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[29] Q=regset[24][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[30] Q=regset[24][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[31] Q=regset[24][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[0] Q=regset[22][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[1] Q=regset[22][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[2] Q=regset[22][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[3] Q=regset[22][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[4] Q=regset[22][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[5] Q=regset[22][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[6] Q=regset[22][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[7] Q=regset[22][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[8] Q=regset[22][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[9] Q=regset[22][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[10] Q=regset[22][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[11] Q=regset[22][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[12] Q=regset[22][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[13] Q=regset[22][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[14] Q=regset[22][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[15] Q=regset[22][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[16] Q=regset[22][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[17] Q=regset[22][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[18] Q=regset[22][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[19] Q=regset[22][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[20] Q=regset[22][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[21] Q=regset[22][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[22] Q=regset[22][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[23] Q=regset[22][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[24] Q=regset[22][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[25] Q=regset[22][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[26] Q=regset[22][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[27] Q=regset[22][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[28] Q=regset[22][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[29] Q=regset[22][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[30] Q=regset[22][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[31] Q=regset[22][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[0] Q=regset[26][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[1] Q=regset[26][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[2] Q=regset[26][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[3] Q=regset[26][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[4] Q=regset[26][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[5] Q=regset[26][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[6] Q=regset[26][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[7] Q=regset[26][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[8] Q=regset[26][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[9] Q=regset[26][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[10] Q=regset[26][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[11] Q=regset[26][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[12] Q=regset[26][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[13] Q=regset[26][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[14] Q=regset[26][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[15] Q=regset[26][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[16] Q=regset[26][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[17] Q=regset[26][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[18] Q=regset[26][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[19] Q=regset[26][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[20] Q=regset[26][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[21] Q=regset[26][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[22] Q=regset[26][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[23] Q=regset[26][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[24] Q=regset[26][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[25] Q=regset[26][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[26] Q=regset[26][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[27] Q=regset[26][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[28] Q=regset[26][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[29] Q=regset[26][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[30] Q=regset[26][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[31] Q=regset[26][31] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23438 Q=r_op_Av[0] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23436 Q=r_op_Av[1] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23434 Q=r_op_Av[2] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23432 Q=r_op_Av[3] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23430 Q=r_op_Av[4] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23428 Q=r_op_Av[5] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23426 Q=r_op_Av[6] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23424 Q=r_op_Av[7] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23422 Q=r_op_Av[8] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23420 Q=r_op_Av[9] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23418 Q=r_op_Av[10] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23416 Q=r_op_Av[11] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23414 Q=r_op_Av[12] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23412 Q=r_op_Av[13] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23410 Q=r_op_Av[14] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23408 Q=r_op_Av[15] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23406 Q=r_op_Av[16] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23404 Q=r_op_Av[17] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23402 Q=r_op_Av[18] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23400 Q=r_op_Av[19] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23398 Q=r_op_Av[20] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23396 Q=r_op_Av[21] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23394 Q=r_op_Av[22] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23392 Q=r_op_Av[23] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23390 Q=r_op_Av[24] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23388 Q=r_op_Av[25] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23386 Q=r_op_Av[26] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23384 Q=r_op_Av[27] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23382 Q=r_op_Av[28] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23380 Q=r_op_Av[29] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23378 Q=r_op_Av[30] -.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23556 Q=r_op_Av[31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[0] Q=regset[30][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[1] Q=regset[30][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[2] Q=regset[30][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[3] Q=regset[30][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[4] Q=regset[30][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[5] Q=regset[30][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[6] Q=regset[30][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[7] Q=regset[30][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[8] Q=regset[30][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[9] Q=regset[30][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[10] Q=regset[30][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[11] Q=regset[30][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[12] Q=regset[30][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[13] Q=regset[30][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[14] Q=regset[30][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[15] Q=regset[30][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[16] Q=regset[30][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[17] Q=regset[30][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[18] Q=regset[30][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[19] Q=regset[30][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[20] Q=regset[30][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[21] Q=regset[30][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[22] Q=regset[30][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[23] Q=regset[30][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[24] Q=regset[30][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[25] Q=regset[30][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[26] Q=regset[30][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[27] Q=regset[30][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[28] Q=regset[30][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[29] Q=regset[30][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[30] Q=regset[30][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[31] Q=regset[30][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[0] Q=regset[19][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[1] Q=regset[19][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[2] Q=regset[19][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[3] Q=regset[19][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[4] Q=regset[19][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[5] Q=regset[19][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[6] Q=regset[19][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[7] Q=regset[19][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[8] Q=regset[19][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[9] Q=regset[19][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[10] Q=regset[19][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[11] Q=regset[19][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[12] Q=regset[19][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[13] Q=regset[19][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[14] Q=regset[19][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[15] Q=regset[19][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[16] Q=regset[19][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[17] Q=regset[19][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[18] Q=regset[19][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[19] Q=regset[19][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[20] Q=regset[19][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[21] Q=regset[19][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[22] Q=regset[19][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[23] Q=regset[19][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[24] Q=regset[19][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[25] Q=regset[19][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[26] Q=regset[19][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[27] Q=regset[19][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[28] Q=regset[19][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[29] Q=regset[19][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[30] Q=regset[19][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[31] Q=regset[19][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[0] Q=regset[18][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[1] Q=regset[18][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[2] Q=regset[18][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[3] Q=regset[18][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[4] Q=regset[18][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[5] Q=regset[18][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[6] Q=regset[18][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[7] Q=regset[18][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[8] Q=regset[18][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[9] Q=regset[18][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[10] Q=regset[18][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[11] Q=regset[18][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[12] Q=regset[18][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[13] Q=regset[18][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[14] Q=regset[18][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[15] Q=regset[18][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[16] Q=regset[18][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[17] Q=regset[18][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[18] Q=regset[18][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[19] Q=regset[18][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[20] Q=regset[18][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[21] Q=regset[18][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[22] Q=regset[18][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[23] Q=regset[18][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[24] Q=regset[18][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[25] Q=regset[18][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[26] Q=regset[18][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[27] Q=regset[18][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[28] Q=regset[18][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[29] Q=regset[18][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[30] Q=regset[18][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[31] Q=regset[18][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[0] Q=regset[16][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[1] Q=regset[16][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[2] Q=regset[16][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[3] Q=regset[16][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[4] Q=regset[16][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[5] Q=regset[16][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[6] Q=regset[16][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[7] Q=regset[16][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[8] Q=regset[16][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[9] Q=regset[16][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[10] Q=regset[16][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[11] Q=regset[16][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[12] Q=regset[16][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[13] Q=regset[16][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[14] Q=regset[16][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[15] Q=regset[16][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[16] Q=regset[16][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[17] Q=regset[16][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[18] Q=regset[16][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[19] Q=regset[16][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[20] Q=regset[16][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[21] Q=regset[16][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[22] Q=regset[16][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[23] Q=regset[16][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[24] Q=regset[16][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[25] Q=regset[16][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[26] Q=regset[16][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[27] Q=regset[16][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[28] Q=regset[16][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[29] Q=regset[16][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[30] Q=regset[16][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[31] Q=regset[16][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[0] Q=regset[0][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[1] Q=regset[0][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[2] Q=regset[0][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[3] Q=regset[0][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[4] Q=regset[0][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[5] Q=regset[0][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[6] Q=regset[0][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[7] Q=regset[0][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[8] Q=regset[0][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[9] Q=regset[0][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[10] Q=regset[0][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[11] Q=regset[0][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[12] Q=regset[0][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[13] Q=regset[0][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[14] Q=regset[0][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[15] Q=regset[0][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[16] Q=regset[0][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[17] Q=regset[0][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[18] Q=regset[0][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[19] Q=regset[0][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[20] Q=regset[0][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[21] Q=regset[0][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[22] Q=regset[0][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[23] Q=regset[0][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[24] Q=regset[0][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[25] Q=regset[0][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[26] Q=regset[0][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[27] Q=regset[0][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[28] Q=regset[0][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[29] Q=regset[0][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[30] Q=regset[0][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[31] Q=regset[0][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[0] Q=regset[17][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[1] Q=regset[17][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[2] Q=regset[17][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[3] Q=regset[17][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[4] Q=regset[17][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[5] Q=regset[17][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[6] Q=regset[17][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[7] Q=regset[17][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[8] Q=regset[17][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[9] Q=regset[17][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[10] Q=regset[17][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[11] Q=regset[17][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[12] Q=regset[17][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[13] Q=regset[17][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[14] Q=regset[17][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[15] Q=regset[17][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[16] Q=regset[17][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[17] Q=regset[17][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[18] Q=regset[17][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[19] Q=regset[17][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[20] Q=regset[17][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[21] Q=regset[17][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[22] Q=regset[17][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[23] Q=regset[17][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[24] Q=regset[17][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[25] Q=regset[17][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[26] Q=regset[17][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[27] Q=regset[17][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[28] Q=regset[17][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[29] Q=regset[17][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[30] Q=regset[17][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[31] Q=regset[17][31] -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23376 Q=DIVIDE.thedivide.r_divisor[0] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23374 Q=DIVIDE.thedivide.r_divisor[1] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23372 Q=DIVIDE.thedivide.r_divisor[2] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23370 Q=DIVIDE.thedivide.r_divisor[3] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23368 Q=DIVIDE.thedivide.r_divisor[4] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23366 Q=DIVIDE.thedivide.r_divisor[5] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23364 Q=DIVIDE.thedivide.r_divisor[6] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23362 Q=DIVIDE.thedivide.r_divisor[7] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23360 Q=DIVIDE.thedivide.r_divisor[8] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23358 Q=DIVIDE.thedivide.r_divisor[9] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23356 Q=DIVIDE.thedivide.r_divisor[10] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23354 Q=DIVIDE.thedivide.r_divisor[11] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23352 Q=DIVIDE.thedivide.r_divisor[12] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23350 Q=DIVIDE.thedivide.r_divisor[13] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23348 Q=DIVIDE.thedivide.r_divisor[14] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23346 Q=DIVIDE.thedivide.r_divisor[15] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23344 Q=DIVIDE.thedivide.r_divisor[16] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23342 Q=DIVIDE.thedivide.r_divisor[17] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23340 Q=DIVIDE.thedivide.r_divisor[18] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23338 Q=DIVIDE.thedivide.r_divisor[19] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23336 Q=DIVIDE.thedivide.r_divisor[20] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23334 Q=DIVIDE.thedivide.r_divisor[21] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23332 Q=DIVIDE.thedivide.r_divisor[22] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23330 Q=DIVIDE.thedivide.r_divisor[23] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23328 Q=DIVIDE.thedivide.r_divisor[24] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23326 Q=DIVIDE.thedivide.r_divisor[25] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23324 Q=DIVIDE.thedivide.r_divisor[26] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23322 Q=DIVIDE.thedivide.r_divisor[27] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23320 Q=DIVIDE.thedivide.r_divisor[28] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23318 Q=DIVIDE.thedivide.r_divisor[29] R=DIVIDE.thedivide.i_reset -.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23644 Q=DIVIDE.thedivide.r_divisor[30] R=DIVIDE.thedivide.i_reset -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[0] Q=regset[1][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[1] Q=regset[1][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[2] Q=regset[1][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[3] Q=regset[1][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[4] Q=regset[1][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[5] Q=regset[1][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[6] Q=regset[1][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[7] Q=regset[1][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[8] Q=regset[1][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[9] Q=regset[1][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[10] Q=regset[1][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[11] Q=regset[1][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[12] Q=regset[1][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[13] Q=regset[1][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[14] Q=regset[1][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[15] Q=regset[1][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[16] Q=regset[1][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[17] Q=regset[1][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[18] Q=regset[1][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[19] Q=regset[1][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[20] Q=regset[1][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[21] Q=regset[1][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[22] Q=regset[1][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[23] Q=regset[1][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[24] Q=regset[1][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[25] Q=regset[1][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[26] Q=regset[1][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[27] Q=regset[1][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[28] Q=regset[1][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[29] Q=regset[1][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[30] Q=regset[1][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[31] Q=regset[1][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[0] Q=regset[15][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[1] Q=regset[15][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[2] Q=regset[15][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[3] Q=regset[15][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[4] Q=regset[15][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[5] Q=regset[15][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[6] Q=regset[15][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[7] Q=regset[15][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[8] Q=regset[15][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[9] Q=regset[15][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[10] Q=regset[15][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[11] Q=regset[15][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[12] Q=regset[15][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[13] Q=regset[15][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[14] Q=regset[15][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[15] Q=regset[15][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[16] Q=regset[15][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[17] Q=regset[15][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[18] Q=regset[15][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[19] Q=regset[15][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[20] Q=regset[15][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[21] Q=regset[15][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[22] Q=regset[15][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[23] Q=regset[15][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[24] Q=regset[15][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[25] Q=regset[15][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[26] Q=regset[15][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[27] Q=regset[15][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[28] Q=regset[15][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[29] Q=regset[15][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[30] Q=regset[15][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[31] Q=regset[15][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[0] Q=regset[14][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[1] Q=regset[14][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[2] Q=regset[14][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[3] Q=regset[14][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[4] Q=regset[14][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[5] Q=regset[14][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[6] Q=regset[14][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[7] Q=regset[14][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[8] Q=regset[14][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[9] Q=regset[14][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[10] Q=regset[14][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[11] Q=regset[14][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[12] Q=regset[14][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[13] Q=regset[14][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[14] Q=regset[14][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[15] Q=regset[14][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[16] Q=regset[14][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[17] Q=regset[14][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[18] Q=regset[14][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[19] Q=regset[14][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[20] Q=regset[14][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[21] Q=regset[14][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[22] Q=regset[14][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[23] Q=regset[14][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[24] Q=regset[14][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[25] Q=regset[14][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[26] Q=regset[14][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[27] Q=regset[14][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[28] Q=regset[14][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[29] Q=regset[14][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[30] Q=regset[14][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[31] Q=regset[14][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[0] Q=regset[2][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[1] Q=regset[2][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[2] Q=regset[2][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[3] Q=regset[2][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[4] Q=regset[2][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[5] Q=regset[2][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[6] Q=regset[2][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[7] Q=regset[2][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[8] Q=regset[2][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[9] Q=regset[2][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[10] Q=regset[2][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[11] Q=regset[2][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[12] Q=regset[2][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[13] Q=regset[2][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[14] Q=regset[2][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[15] Q=regset[2][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[16] Q=regset[2][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[17] Q=regset[2][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[18] Q=regset[2][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[19] Q=regset[2][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[20] Q=regset[2][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[21] Q=regset[2][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[22] Q=regset[2][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[23] Q=regset[2][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[24] Q=regset[2][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[25] Q=regset[2][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[26] Q=regset[2][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[27] Q=regset[2][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[28] Q=regset[2][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[29] Q=regset[2][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[30] Q=regset[2][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[31] Q=regset[2][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[0] Q=regset[13][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[1] Q=regset[13][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[2] Q=regset[13][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[3] Q=regset[13][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[4] Q=regset[13][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[5] Q=regset[13][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[6] Q=regset[13][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[7] Q=regset[13][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[8] Q=regset[13][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[9] Q=regset[13][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[10] Q=regset[13][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[11] Q=regset[13][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[12] Q=regset[13][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[13] Q=regset[13][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[14] Q=regset[13][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[15] Q=regset[13][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[16] Q=regset[13][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[17] Q=regset[13][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[18] Q=regset[13][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[19] Q=regset[13][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[20] Q=regset[13][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[21] Q=regset[13][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[22] Q=regset[13][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[23] Q=regset[13][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[24] Q=regset[13][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[25] Q=regset[13][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[26] Q=regset[13][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[27] Q=regset[13][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[28] Q=regset[13][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[29] Q=regset[13][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[30] Q=regset[13][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[31] Q=regset[13][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[0] Q=regset[3][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[1] Q=regset[3][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[2] Q=regset[3][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[3] Q=regset[3][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[4] Q=regset[3][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[5] Q=regset[3][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[6] Q=regset[3][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[7] Q=regset[3][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[8] Q=regset[3][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[9] Q=regset[3][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[10] Q=regset[3][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[11] Q=regset[3][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[12] Q=regset[3][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[13] Q=regset[3][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[14] Q=regset[3][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[15] Q=regset[3][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[16] Q=regset[3][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[17] Q=regset[3][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[18] Q=regset[3][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[19] Q=regset[3][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[20] Q=regset[3][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[21] Q=regset[3][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[22] Q=regset[3][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[23] Q=regset[3][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[24] Q=regset[3][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[25] Q=regset[3][25] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[26] Q=regset[3][26] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[27] Q=regset[3][27] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[28] Q=regset[3][28] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[29] Q=regset[3][29] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[30] Q=regset[3][30] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[31] Q=regset[3][31] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[0] Q=regset[12][0] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[1] Q=regset[12][1] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[2] Q=regset[12][2] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[3] Q=regset[12][3] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[4] Q=regset[12][4] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[5] Q=regset[12][5] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[6] Q=regset[12][6] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[7] Q=regset[12][7] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[8] Q=regset[12][8] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[9] Q=regset[12][9] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[10] Q=regset[12][10] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[11] Q=regset[12][11] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[12] Q=regset[12][12] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[13] Q=regset[12][13] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[14] Q=regset[12][14] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[15] Q=regset[12][15] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[16] Q=regset[12][16] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[17] Q=regset[12][17] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[18] Q=regset[12][18] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[19] Q=regset[12][19] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[20] Q=regset[12][20] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[21] Q=regset[12][21] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[22] Q=regset[12][22] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[23] Q=regset[12][23] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[24] Q=regset[12][24] -.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[25] Q=regset[12][25] -.subckt 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-.names $false o_prof_ticks[16] -1 1 -.names $false o_prof_ticks[17] -1 1 -.names $false o_prof_ticks[18] -1 1 -.names $false o_prof_ticks[19] -1 1 -.names $false o_prof_ticks[20] -1 1 -.names $false o_prof_ticks[21] -1 1 -.names $false o_prof_ticks[22] -1 1 -.names $false o_prof_ticks[23] -1 1 -.names $false o_prof_ticks[24] -1 1 -.names $false o_prof_ticks[25] -1 1 -.names $false o_prof_ticks[26] -1 1 -.names $false o_prof_ticks[27] -1 1 -.names $false o_prof_ticks[28] -1 1 -.names $false o_prof_ticks[29] -1 1 -.names $false o_prof_ticks[30] -1 1 -.names $false o_prof_ticks[31] -1 1 -.names $false pf_pc[0] -1 1 -.names $false pf_pc[1] -1 1 -.names $false wr_index[2] -1 1 -.end From ba7b4a194581ea47d8c389cc9b45b31af81851ac Mon Sep 17 00:00:00 2001 From: Amin Mohaghegh Date: Tue, 20 May 2025 14:39:16 -0400 Subject: [PATCH 451/453] Update OpenFPGA (#3056) * [Bison] Raised Minimum Bison Version from 3.0 to 3.3 Raised the minimum Bison version to 3.3 since deprecation warnings were showing up in libblifparse and libsdcparse which could not be resolved unless the Bison version was 3.3. * more fixes for bitstream generation with flat router * [Router] Upstream Fine-Grained Parallel Router (FPT'24) Upstreamed the fine-grained parallel router implementation into the VTR master. The original branch is https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/mq-parallel-router. Modified the MultiQueue (SPAA'24) implementation and integrated it into the VTR codebase. * [ParallelRouter] Removed Boost from FG Parallel Router The original FG parallel router used to use boost. VTR does not install boost by default. Moved to STL instead. * [Router] Fix Code Formatting Issues * [Router] Added ConnectionRouter Abstraction and Reduced Code Duplication Added a partial abstract class for ConnectionRouter, derived from the pure abstract ConnectionRouterInterface. The SerialConnectionRouter and ParallelConnectionRouter classes are now derived from the ConnectionRouter class, utilizing the common class members and helper functions to reduce code duplication. * [Router] Added Code Comments and Documentation for Connection Routers Added Doxygen-style code comments and documentation for connection routers, including the ConnectionRouter abstract class, the Parallel- ConnectionRouter concrete class, and the SerialConnectionRouter concrete class. Updated the helper messages for command-line options added for parallel connection router. * [Router] Fixed Interface Issues in NestedNetlistRouter and Code Formats Fixed the interface issues of ConnectionRouter in NestedNetlistRouter. Fixed code formats. Fixed typo in read_options.cpp. * [Router] Updated Command-Line Usage for Parallel Connection Router Updated the command-line usage for parallel connection router in both Read the Docs and read_options.cpp. * [Router] Added Regression Tests for Parallel Connection Router Added regression tests for parallel connection router by appending extra sets of configurations to those VTR flow regression tests previously selected by Fahri for testing coarse-grained parallel router. Removed VPR connection router test (vpr/test/test_connection_router.cpp), since it has been out-dated for a very long time and has caused lots of trouble for running VPR C++ tests locally. * Fixed Code Formatting Issue Fixed a weird code formatting issue in libs/librtlnumber/src/include/ internal_bits.hpp. GitHub CI said the file failed dev/check-format.sh, however, the same script runs perfectly in my local environment. Double checked the version of clang-format, which seemed to be the same as CI. Directly copied the file from the GitHub repo to resolve this issue. * [Router] Fixed `No source in route tree` in ParallelConnectionRouter The `No source in route tree` bug in ParallelConnectionRouter (since commit 875b98e) has been fixed. It turns out that putting another member variable `MultiQueueDAryHeap heap_` in the derived class ParallelConnectionRouter together with the existing `HeapImplementation heap_` in the base class ConnectionRouter causes the issue. The solution is to keep `heap_` only in the base class and use `ConnectionRouter>` rather than `ConnectionRouter` for deriving the parallel connection router. Please note that ParallelConnectionRouter still has some bugs (i.e., getting stuck in the MultiQueue pop). This commit is not fully working. Please do not use it for any experiments. Updated the previously incorrect command-line options for the parallel connection router in the regression tests. * [AP][MassLegalizer] Revistited Mass Legalizer Found that the mass legalizer was not spreading out the blocks well enough according to the mass. Revistied the spatial partitioning in the mass legalizer. Before, we just cut the window in half in the larger dimension. This was fine, however it may create an inbalanced cut which can cause things to not spread well. Instead, we now search for the best partition by trying different partition lines and computing how balanced the partition is. Although this is more expensive than before, by creating more balanced partitions, it should allow the mass legalizer to converge faster. Time in the mass legalizer is also dominated by partitioning the blocks, so increasing the time to choose the partition line should not have that large of an effect anyways. Found an oversight with how blocks were partitioned when one of the partitions become overfilled. Fixed this issue. * Inverse use of macro_can_be_placed argument check_all_legality to align with meaning * [vpr][pack] fix merge issues w/ flat sync list * make format * [packages] add clang-format * make format 2 * Invalid C++ fix * [docker] set ubuntu version to 24.04 * [dockerfile] enable system-wide python package installation for pip * [dockerfile] add comment * [package] check whehter clang-format-18 package exist * [package] remove deprecated names-only option * [package] remove if condition * [doc] update quick start on installing packages * make format enum class e_rr_type a few remaining t_rr_type vals CHANY ---> t_rr_type::CHANY CHANX ---> t_rr_type::CHANX OPIN ---> t_rr_type::OPIN IPIN ---> t_rr_type::IPIN SINK ---> t_rr_type::SINK SOURCE ---> t_rr_type::SOURCE * [Router] Finally fixed the weird bug in parallel connection router Fixed the weird bug in parallel connection router as mentioned in commit f73212c. The bug occurred because two function parameters 'num_threads' and 'num_queues' have been misplaced when instantiating the MQ_IO. This took two weeks to figure out exactly. The VTR benchmark (`vtr_reg_qor_chain` task) has been tested/passed for different cases (1) 'serial mode' 1T+2Q (1 thread, 2 queues), (2) 2T+4Q, and (3) 4T+2Q. The determinism has also been verified for the VTR benchmark. * [Router] Fixed Code Review Comments and Cleanup Codebase Added more explanation to the command-line options messages and code comments. Cleaned up ParallelConnectionRouter-related codebase. * [doc] clarify that clang-format is not required to build VPR * remove typedef t_rr_type * doxygen comment for Direction * add vtr::array class * make rr_node_typename of type vtr::array to index it only with e_rr_type * add default constructor to vtr::array * access rr_node_indices_ with e_rr_type instead of casting to size_t * add single argument constructor to vtr::array * [Router] Updated Golden Results for Parallel Connection Router CI Tests Updated the golden results for CI tests for parallel connection router: - `vtr_reg_strong/koios_test` - `vtr_reg_strong/strong_flat_router` - `vtr_reg_strong/strong_multiclock` - `vtr_reg_strong/strong_timing` * use vtr::array to index some arrays using e_rr_type * make format * avoid using e_rr_type and casting it in place_macro * [vpr][base] fix assigned pb_graph_pin when graph node is not primitive * [vpr][pack] pass logical type to alloc_and_laod_pb_route * [vpr][pack] update alloc_and_load_pb_route header file * [vpr][pack] fix pb_graph_pin assignment in load_trace_to_pb_route * [test] keep 3d sb and cb tests * [vpr][pack] add intra_lb_pb_pin_lookup_ to cluster legalizer * [vpr][pack] initializer intra_lb_pb_pin_lookup and pass it to alloc_and_load_pb_route * [vpr][pack] use intra_lb_pb_pin_lookup to get pb_pin from pin number * make format * add vtr::array to docs * [vpr][pack] remove casting net id * [vpr][pack] add doxygen comment for alloc_and_load_pb_route * [vpr][pack] remove redundant parameters * [vpr][pack] polish load_trace_to_pb_route * make format * [vpr][pack] fix parameter shadowing * [AP][HotFix] Fixed Bug With Solver Putting Blocks Off-Device After moving fixed blocks to the center of tiles, there is a very small chance that blocks go off the device due to rounding. This is such a small effect that it does not show up locally on my machine, but it shows up on CI. Clamping the positions of blocks after solving to be just within the device region. * Increase the daily stale issue action API call limit * [vpr][pack] add a method to get root_ipin * [vpr][pack] remove unused var * [Router] Added Assert for MQ_IO numQueues and Updated Golden Results Added assert for MultiQueueIO numQueues to ensure it must be greater than two. Updated CI test tasks to ensure the parallel connection router runs in Dijkstra mode to ensure determinism and avoid hanging in CI runs. * [AP][HotFix] Placed Fixed Blocks First During IP The cost terms in the AP initial placer were not placing fixed blocks early enough, causing other blocks to take their place and causing the initial placer to not return a solution. Blocks which have region constraints are now placed first based on how constrained they are. More constrained blocks (can only be placed in a smaller region) will be placed first. Also found that macros that contained fixed blocks were not observing these constraints when calculating the centroid position of the macro. For constrained macros, projected the centroid position onto the partition region to get the closest point in the partition region to the calculated centroid. This new centroid is used to then perform the placement. * [STA] Added Option to Remove Parameters from Post-Implementation Netlist When performing post-implementation timing analysis using OpenSTA, the generated netlist cannot use parameters since each module needs to correspond with a cell in a liberty file. Added a command-line option which tells the netlist writer to not use parameters when generating the netlist. If a primitive cannot be generated without using parameters, it will error out. * [Tatum][Parse] Fixed Extraneous Warning With get_clocks The get_clocks command is used in an SDC file to reference a set of clocks by name using a regex string. The code to do this tries to produce a warning if get_clocks is used on a regex string and no clocks could be found. The issue is that the code to do this was mistakenly producing this warning for each clock in the circuit. For example, if we had {clk1, clk2, clk3} and we wanted to do "get_clocks {clk3}", we will get two warnings since clk1 and clk2 did not match. Fixed this by moving the warning out of one loop nest. * Remove PR staling This commit sets the number of days before marking issues or PRs as stale to 100 years. This number is overriden for issues to be 1 years but stays 100 years for PRs. This means that PR effectively do not get marked as stale. * [LibArchFPGA] Updating Model Data Structures The logical models (the technology-mapped logical blocks) for an architecture were stored using two independent linked lists. One for the library models (the models that all architectures have, such as luts and ffs) and one of the user models. This linked lists were hard to traverse and were injecting pointers all across VPR. Created a new class to store and manage the logical models. This class maintains a unique ID for each logical model (similar to the netlist data structures in VPR). It also contains helper methods to make working with the logical models easier. * fix comments from alex * revert prepacker changes * [vpr][pack] add get_pattern_blocks * [vpr][pack] add blocks in get_all_connected_primitive_pins if they are a part of the pattern * make format * Bump libs/EXTERNAL/libcatch2 from `76f70b1` to `5abfc0a` Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `76f70b1` to `5abfc0a`. - [Release notes](https://github.com/catchorg/Catch2/releases) - [Commits](https://github.com/catchorg/Catch2/compare/76f70b1403dbc0781216f49e20e45b71f7eccdd8...5abfc0aa9c1ef4cb40c9f387495134dab02e1af2) --- updated-dependencies: - dependency-name: libs/EXTERNAL/libcatch2 dependency-version: 5abfc0aa9c1ef4cb40c9f387495134dab02e1af2 dependency-type: direct:production ... Signed-off-by: dependabot[bot] * [vpr][pack] add more comments * Add helper functions to t_pb_type * Change t_pb_type users to use helper functions * Add documentation for t_pb_type::is_root and is_primitive * Fix formatting in libarchfpga/physical_types.h * [vpr][pack] change count method to find * [Router] Updated the Regression Tests and Corresponding Golden Results Changed `multi_queue_num_threads` and `multi_queue_num_queues` settings in the CI strong regression tests to avoid QoR failure in the CI runs. The coverage of the regression tests for parallel connection router after this change is still fair. * [vpr][CLI] add generate_net_timing_report * [vpr][route] remove debugging msg * [vpr][analysis] add generate_net_timing_report * [vpr][pack] apply formatting comments * make format * [vpr][analysis] add comments * make format * [vpr][CLI] remove generate net timing from CLI parameters and generate the report by default * Unused Packer Options Cleanup (#2976) * Standardized and renamed packer alpha and beta variable. They are now referred to as timing_gain_weight and connection_gain_weight, used as a weight parameter during timing and connection driven clustering respectively. Removed global_clocks, use_attraction_groups, pack_num_moves, pack_move_type from packer. * [APPack] Updated Max Candidate Distance Interface The max candidate distance is used by APPack to decide which molecules to ignore when packing, based on their distance from the cluster being formed. Cleaned up the interface of this by pre-computing the max candidate distance of all logical blocks ahead of time and reading from these pre-computed values during packing. Added a command-line option to allow the user to override some or all of these max distance thresholds. By default, VPR will select values based on the type of logical block and the primitives it contains. Fixed issue with APPack creating too many IO blocks for some circuits due to the max candidate distance thresholds for IO blocks being too low. More tuning should be done on these values once the mass legalizer has been cleaned up a bit more. * [vtr][parse] fix pattern for init place wl * [vpr][analysis] add header for net timing report * [vpr][analysis] add timing format to comments * formatting fix * Revert "[vpr][CLI] remove generate net timing from CLI parameters and generate the report by default" This reverts commit b8289db3ed811a9b831dbb036b91929e6b2737fc. * make format * [STA] Generating SDC Commands Post-Implementation Added an option to have VPR generate an SDC file containing the timing commands required for an external timing analysis of the post- implementation netlist to match VPR's timing analysis. * [STA] Added Tutorial for Post-Implementation Timing Analysis Created a tutorial demonstrating how OpenSTA can be used after VPR to perform static timing analysis. * Add artifact upload to nightly test workflow * t_det_routing_arch* --> const t_det_routing_arch& * t_chan_width_dist ---> const t_chan_width_dist& * make format * fix compilation error in route_diag by passing det_routing_arch argument by reference instead of pointer * [task] add generate_net_timing_report to timing report strong test * [doc] add doc for generating _net_timing_report command line option * [vpr][timing] update generate_net_timing_report comment * [vpr][timing] add get_net_bounding_box * [vpr][timing] add net bounding box to the report * [test] add test for net timing report * [doc] update doc with new format to net timing report * [vpr][analysis] fix net timing report bugs + including layer min/max of bb * make format * [vpr][analysis] capture vars by reference in lambda * [packer] Changing the vector of candidate molecules into LazyPopUniquePriorityQueue. The class LazyPopUniquePriorityQueue is a priority queue that allows for lazy deletion of elements. It is implemented using a vector and 2 sets, one set keeps track of the elements in the queue, and the other set keeps track of the elements that are pending deletion. The queue is sorted by the sort-value(SV) of the elements, and the elements are stored in a vector. The set is used to keep track of the elements that are pending deletion, so that they can be removed from the queue when they are popped. The class definiation can be found in vpr/src/util/lazy_pop_unique_priority_queue.h Currently, the class supports the following functions: LazyPopUniquePriorityQueue::push(): Pushes a key-sort-value (K-SV) pair into the priority queue and adds the key to the tracking set. LazyPopUniquePriorityQueue::pop(): Returns the K-SV pair with the highest SV whose key is not pending deletion. LazyPopUniquePriorityQueue::remove(): Removes an element from the priority queue immediately. LazyPopUniquePriorityQueue::remove_at_pop_time(): Removes an element from the priority queue when it is popped. LazyPopUniquePriorityQueue::empty(): Returns whether the queue is empty. LazyPopUniquePriorityQueue::clear(): Clears the priority queue vector and the tracking sets. LazyPopUniquePriorityQueue::size(): Returns the number of elements in the queue. LazyPopUniquePriorityQueue::contains(): Returns true if the key is in the queue, false otherwise. * [packer] recollected golden results for regression basic, basic_odin, strong, strong_odin * [packer] recollected golden results for Nightly * add pointer to VTR9 paper in the readme * Add documentation to explain which parts of VPR are parellel * pass t_chan_width by reference * doxygen comment for alloc_and_load_rr_node_indices * add doxygen comments for load_block_rr_indices() * [AP][Solver] Enabled Parallel Eigen The Eigen solver has the ability to use OpenMP to run the solver computations in parallel. Made the AP flow use the num_workers option to set the number of threads that Eigen can use. VPR did not have the ability to build with OpenMP in its CMAKE. Added an option to the CMAKE to allow the user to enable OpenMP. * remove unused is_flat argument from alloc_and_load_rr_node_indices() and load_block_rr_indices() * use (x, y) convention for CHANX instead of (y, x) * make format * cast x/y to size_t * get rid of warnings in RRSpatialLookup::find_nodes() * Add references to the main VTR papers in the documentation. * Add link to the VTR 9 paper in the documentation * Add link to the VTR 9 paper in the README * add a closing ) to the text printed by node_coordinate_to_string() * fix the x/y mismatch for CHANX nodes in rr_nodes and rr_node_indices * reserve nodes using x/y instead of chan/seg * fix a typo * add rr_graph_genearion directory * resize node lookup for CHANX nodes in RR graph serializer * add rr_node_indices.cpp/.h * add doxygen comment for load_chan_rr_indices() * [Infra] Updated Install Packages Script For Backwards Compatibility The install_apt_packages.sh script is no longer backward compatible with older versions of Ubuntu due to the dependency on clang-format-18. Added an if statement to check if the distribution can support clang-format-18 and only installing it if it can. Added this script to the CI build process so it can always be tested within the CI to prevent future regression. * [RegTest] Disabled `strong_multiclock` test for parallel connection router Temporarily disabled the `strong_multiclock` test in `vtr_reg_strong` CI regression tests for the parallel connection router, due to some random failures as mentioned in Issue #3029. After fixing the problem with the `strong_multiclock` test, this will be reactivated. * [doc] update the doc with new report format * [RegTest] Updated golden results for `strong_multiclock` regression test Removed the golden results of parallel connection router test cases for `strong_multiclock` regression test. * [vpr][analysis] use std::min/max instead of if condition * Add documentation for include sanitization * [vpr][analysis] change report_net_timing format to csv * [vpr][analysis] update comments * [vpr][analysis] print constant nets in the net timing report * [vpr][analysis] apply comments * [vpr][analysis] fix function name * [doc] add net timing report use case * fix a typo * [Infra] Cleaned Up Include Files in VPR Base Directory Many include files in the base directory contained includes to other headers which they do not use. This causes many CPP files to include way more header files than they need, increasing the incremental build time. This process needs to be done on the entire VTR repo, but I found that the base directory was one of the biggest culprits of this and the hardest to untangle. * [Infra] Cleaned Up Header Files in Pack Folder Went through the header files in the pack folder and resolved any unused header files. * [AP] Removed Old Cluster-Level AP Flow Prior to the flat AP flow, a cluster-level AP flow existed in VPR which performed a SimPL-style algorithm on the clusters created during packing before performing a placement quench. Although well-written, this flow was not shown to outperform the SA placer in VPR. It has also been becoming confusing to keep in VPR since the new flat AP flow supercedes it. It is unclear if a cluster-level AP flow will work well with the flat AP flow; however in that case the cluster-level AP flow would be made using the new AP APIs written. Removed the old cluster-level AP flow to reduce confusion. * [Infra] Cleaned Up Header Files in Place Folder * [lib][rr_graph] replace t_rr_type with e_rr_type * [vpr][tileable] remove t_rr_type usage * make is_io_type() a member function of t_physical_tile_type * replace calls to is_io_type() with t_physical_tile_type::is_io() * make format * fix compiler bugs * make format * [lib][libutil] fix size_t issue * inline t_physical_tile_type::is_io() * add doxygen comments for alloc_and_load_tile_rr_node_indices() * [libs][vtrutil] use generate instead of fill to avoid getting potential null pointer dereference * document alloc_and_load_rr_node_indices() arguments * made a few function operating on t_pb_type its member functions * add router_lookahead directory * [STA] Added Multiclock Incremental STA Consistency Check The incremental STA consistency coverage was very good, but was just missing a multiclock circuit with an SDC file. Added a quick test. * [libs][rr_graph] don't reverse xy when calling node lookup * [vpr][util] consider medium node type as inter cluster node --------- Signed-off-by: dependabot[bot] Co-authored-by: AlexandreSinger Co-authored-by: Fahrican Kosar Co-authored-by: AlexandreSinger <49374526+AlexandreSinger@users.noreply.github.com> Co-authored-by: Hang Yan Co-authored-by: Fred Tombs Co-authored-by: soheilshahrouz Co-authored-by: Soheil Shahrouz <80951211+soheilshahrouz@users.noreply.github.com> Co-authored-by: Amir Poolad <54797949+AmirhosseinPoolad@users.noreply.github.com> Co-authored-by: Amir Poolad Co-authored-by: vaughnbetz Co-authored-by: Fred Tombs Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Co-authored-by: James Yen <90464912+yenjames@users.noreply.github.com> Co-authored-by: Rongbo Zhang Co-authored-by: Rongbo Zhang Co-authored-by: Mohamed Elgammal --- .github/scripts/install_dependencies.sh | 18 +- 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| 18 +- .../clock_connection_builders.h | 0 .../{ => rr_graph_generation}/clock_fwd.h | 0 .../clock_network_builders.cpp | 7 +- .../clock_network_builders.h | 0 .../{ => rr_graph_generation}/rr_graph.cpp | 177 +- .../{ => rr_graph_generation}/rr_graph.h | 2 +- .../{ => rr_graph_generation}/rr_graph2.cpp | 709 +----- .../{ => rr_graph_generation}/rr_graph2.h | 53 +- .../rr_graph_area.cpp | 40 +- .../{ => rr_graph_generation}/rr_graph_area.h | 0 .../rr_graph_clock.cpp | 0 .../rr_graph_clock.h | 0 .../rr_graph_indexed_data.cpp | 0 .../rr_graph_indexed_data.h | 0 .../rr_graph_sbox.cpp | 0 .../{ => rr_graph_generation}/rr_graph_sbox.h | 4 +- .../rr_graph_timing_params.cpp | 16 +- .../rr_graph_timing_params.h | 0 .../rr_graph_generation/rr_node_indices.cpp | 613 +++++ .../rr_graph_generation/rr_node_indices.h | 88 + .../{ => rr_graph_generation}/rr_types.h | 3 +- vpr/src/route/segment_stats.cpp | 5 +- vpr/src/route/serial_connection_router.cpp | 533 +++++ vpr/src/route/serial_connection_router.h | 255 ++ vpr/src/server/pathhelper.cpp | 3 +- .../openfpga_rr_graph_utils.cpp | 16 +- vpr/src/tileable_rr_graph/rr_chan.cpp | 14 +- vpr/src/tileable_rr_graph/rr_chan.h | 8 +- .../rr_graph_builder_utils.cpp | 20 +- .../rr_graph_builder_utils.h | 8 +- vpr/src/tileable_rr_graph/rr_graph_types.h | 6 +- .../tileable_rr_graph/rr_graph_view_util.cpp | 12 +- .../tileable_rr_graph/rr_graph_view_util.h | 6 +- vpr/src/tileable_rr_graph/rr_gsb.cpp | 82 +- vpr/src/tileable_rr_graph/rr_gsb.h | 30 +- .../tileable_rr_graph_edge_builder.cpp | 8 +- .../tileable_rr_graph_gsb.cpp | 76 +- .../tileable_rr_graph_node_builder.cpp | 134 +- vpr/src/timing/PreClusterDelayCalculator.h | 10 +- .../timing/PreClusterTimingGraphResolver.cpp | 6 +- .../timing/PreClusterTimingGraphResolver.h | 4 + vpr/src/timing/PreClusterTimingManager.cpp | 2 + vpr/src/timing/VprTimingGraphResolver.cpp | 17 +- vpr/src/timing/VprTimingGraphResolver.h | 3 + vpr/src/timing/read_sdc.cpp | 29 +- vpr/src/timing/read_sdc.h | 3 + vpr/src/timing/timing_graph_builder.cpp | 8 +- vpr/src/timing/timing_graph_builder.h | 5 +- vpr/src/util/lazy_pop_unique_priority_queue.h | 216 ++ vpr/src/util/vpr_utils.cpp | 146 +- vpr/src/util/vpr_utils.h | 20 +- vpr/test/test_ap_primitive_vector.cpp | 18 + vpr/test/test_compressed_grid.cpp | 7 +- vpr/test/test_connection_router.cpp | 194 -- vpr/test/test_interchange_device.cpp | 24 +- vpr/test/test_interchange_netlist.cpp | 7 +- ..._post_verilog_i_gnd_o_unconnected.golden.v | 3 +- ...post_verilog_i_nets_o_unconnected.golden.v | 3 +- ...post_verilog_i_unconnected_o_nets.golden.v | 3 +- ...rilog_i_unconnected_o_unconnected.golden.v | 3 +- ..._post_verilog_i_vcc_o_unconnected.golden.v | 3 +- vpr/test/test_vpr.cpp | 6 +- .../parse/parse_config/common/vpr.place.txt | 2 +- vtr_flow/primitives.lib | 370 +++ .../basic_no_timing/config/golden_results.txt | 10 +- .../basic_timing/config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../basic_no_timing/config/golden_results.txt | 10 +- .../basic_timing/config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../figure_8/config/config.txt | 2 +- .../figure_8/config/golden_results.txt | 422 ++-- .../multless_consts/config/golden_results.txt | 2050 ++++++++--------- .../open_cores/config/golden_results.txt | 14 +- .../open_cores_frac/config/golden_results.txt | 22 +- .../config/golden_results.txt | 62 +- .../config/golden_results.txt | 30 +- .../vpr_reg_mcnc/config/golden_results.txt | 42 +- .../config/golden_results.txt | 40 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 16 +- .../titan_other/config/golden_results.txt | 48 +- .../vtr_bidir/config/golden_results.txt | 82 +- .../config/golden_results.txt | 10 +- .../complex_switch/config/golden_results.txt | 30 +- .../config/golden_results.txt | 44 +- .../config/golden_results.txt | 40 +- .../config/golden_results.txt | 48 +- .../config/golden_results.txt | 48 +- .../config/golden_results.txt | 48 +- .../config/golden_results.txt | 48 +- .../ap_titan/config/golden_results.txt | 44 +- .../config/golden_results.txt | 34 +- .../basic_ap/config/golden_results.txt | 10 +- .../koios_test/config/config.txt | 3 + .../koios_test/config/golden_results.txt | 9 +- .../config/golden_results.txt | 4 +- .../strong_3d/{ => 3d_cb}/config/config.txt | 4 - .../strong_3d/3d_cb/config/golden_results.txt | 2 + .../strong_3d/3d_sb/config/config.txt | 31 + .../strong_3d/3d_sb/config/golden_results.txt | 2 + .../strong_3d/config/golden_results.txt | 7 - .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../strong_analytic_placer/config/config.txt | 28 - .../config/golden_results.txt | 2 - .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../strong_ap/mcnc/config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../no_fixed_blocks/config/golden_results.txt | 12 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../vtr_chain/config/golden_results.txt | 10 +- .../strong_bidir/config/golden_results.txt | 10 +- .../strong_binary/config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../strong_depop/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_fc_abs/config/golden_results.txt | 4 +- .../apex2_block_locations.place | 352 +-- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../read_write/config/golden_results.txt | 4 +- .../strong_flat_router/config/config.txt | 3 + .../config/golden_results.txt | 9 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_mcnc/config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../strong_multiclock/config/config.txt | 4 + .../config/golden_results.txt | 1 + .../config/golden_results.txt | 4 +- .../strong_noc/config/golden_results.txt | 4 +- .../strong_pack/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../strong_place/config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +- .../strong_power/config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_sdc/config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 28 +- .../config/golden_results.txt | 4 +- .../strong_timing/config/config.txt | 3 + .../strong_timing/config/golden_results.txt | 9 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/config.txt | 5 +- .../config/golden_results.txt | 11 +- .../config/golden_results.txt | 4 +- .../config/config.txt | 6 + .../config/golden_results.txt | 20 +- .../strong_titan/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../vtr_reg_strong/task_list.txt | 4 +- .../koios_test/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../strong_analytic_placer/config/config.txt | 28 - .../config/golden_results.txt | 2 - .../strong_bidir/config/golden_results.txt | 10 +- .../strong_binary/config/golden_results.txt | 6 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../strong_depop/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_fc_abs/config/golden_results.txt | 4 +- .../apex2_block_locations.place | 352 +-- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_mcnc/config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_pack/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../strong_place/config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +- .../strong_power/config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_sdc/config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 28 +- .../config/golden_results.txt | 4 +- .../strong_timing/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../strong_titan/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../vtr_reg_strong_odin/task_list.txt | 1 - 583 files changed, 13272 insertions(+), 12146 deletions(-) create mode 100644 doc/src/api/vprinternals/router_connection_router.rst create mode 100644 doc/src/tutorials/timing_analysis/index.rst create mode 100644 doc/src/tutorials/timing_analysis/timing_analysis_design_cycle.png create mode 100644 libs/libarchfpga/src/logic_types.cpp create mode 100644 libs/libvtrutil/src/vtr_array.h create mode 100644 vpr/src/pack/appack_max_dist_th_manager.cpp create mode 100644 vpr/src/pack/appack_max_dist_th_manager.h delete mode 100644 vpr/src/place/analytic_placer.cpp delete mode 100644 vpr/src/place/analytic_placer.h delete mode 100644 vpr/src/place/cut_spreader.cpp delete mode 100644 vpr/src/place/cut_spreader.h delete mode 100644 vpr/src/route/connection_router.cpp create mode 100644 vpr/src/route/connection_router.tpp create mode 100644 vpr/src/route/multi_queue_d_ary_heap.h create mode 100644 vpr/src/route/multi_queue_d_ary_heap.tpp create mode 100644 vpr/src/route/parallel_connection_router.cpp create mode 100644 vpr/src/route/parallel_connection_router.h rename vpr/src/route/{ => router_lookahead}/router_lookahead.cpp (97%) rename vpr/src/route/{ => router_lookahead}/router_lookahead.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_compressed_map.cpp (96%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_compressed_map.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_cost_map.cpp (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_cost_map.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_extended_map.cpp (97%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_extended_map.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_map.cpp (96%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_map.h (100%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_map_utils.cpp (97%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_map_utils.h (99%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_sampling.cpp (97%) rename vpr/src/route/{ => router_lookahead}/router_lookahead_sampling.h (100%) rename vpr/src/route/{ => rr_graph_generation}/build_switchblocks.cpp (98%) rename vpr/src/route/{ => rr_graph_generation}/build_switchblocks.h (100%) rename vpr/src/route/{ => rr_graph_generation}/cb_metrics.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/cb_metrics.h (100%) rename vpr/src/route/{ => rr_graph_generation}/clock_connection_builders.cpp (96%) rename vpr/src/route/{ => rr_graph_generation}/clock_connection_builders.h (100%) rename vpr/src/route/{ => rr_graph_generation}/clock_fwd.h (100%) rename vpr/src/route/{ => rr_graph_generation}/clock_network_builders.cpp (99%) rename vpr/src/route/{ => rr_graph_generation}/clock_network_builders.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph.cpp (97%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph.h (98%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph2.cpp (75%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph2.h (78%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_area.cpp (97%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_area.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_clock.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_clock.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_indexed_data.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_indexed_data.h (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_sbox.cpp (100%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_sbox.h (87%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_timing_params.cpp (94%) rename vpr/src/route/{ => rr_graph_generation}/rr_graph_timing_params.h (100%) create mode 100644 vpr/src/route/rr_graph_generation/rr_node_indices.cpp create mode 100644 vpr/src/route/rr_graph_generation/rr_node_indices.h rename vpr/src/route/{ => rr_graph_generation}/rr_types.h (99%) create mode 100644 vpr/src/route/serial_connection_router.cpp create mode 100644 vpr/src/route/serial_connection_router.h create mode 100644 vpr/src/util/lazy_pop_unique_priority_queue.h delete mode 100644 vpr/test/test_connection_router.cpp create mode 100644 vtr_flow/primitives.lib rename vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/{ => 3d_cb}/config/config.txt (79%) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/config.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/config.txt delete mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt diff --git a/.github/scripts/install_dependencies.sh b/.github/scripts/install_dependencies.sh index 61ad671d30b..0d05ecdc7d1 100755 --- a/.github/scripts/install_dependencies.sh +++ b/.github/scripts/install_dependencies.sh @@ -2,40 +2,32 @@ sudo apt update +# Required packages specifically for the CI and not VTR in general. sudo apt install -y \ autoconf \ automake \ bash \ - bison \ binutils \ binutils-gold \ - build-essential \ capnproto \ exuberant-ctags \ curl \ doxygen \ - flex \ fontconfig \ gdb \ - git \ gperf \ libcairo2-dev \ libcapnp-dev \ - libgtk-3-dev \ libevent-dev \ libfontconfig1-dev \ liblist-moreutils-perl \ libncurses5-dev \ - libx11-dev \ libxft-dev \ libxml2-utils \ libxml++2.6-dev \ - libreadline-dev \ tcllib \ tcl8.6-dev \ - libffi-dev \ perl \ - pkg-config \ texinfo \ time \ valgrind \ @@ -54,10 +46,10 @@ sudo apt install -y \ clang-15 \ clang-16 \ clang-17 \ - clang-18 \ - clang-format-18 \ - libtbb-dev \ - openssl + clang-18 + +# Standard packages install script. +./install_apt_packages.sh pip install -r requirements.txt diff --git a/.github/scripts/install_jammy_dependencies.sh b/.github/scripts/install_jammy_dependencies.sh index aa6631f8a04..82fc6d587bd 100755 --- a/.github/scripts/install_jammy_dependencies.sh +++ b/.github/scripts/install_jammy_dependencies.sh @@ -2,40 +2,32 @@ sudo apt update +# Required packages specifically for the CI and not VTR in general. sudo apt install -y \ autoconf \ automake \ bash \ - bison \ binutils \ binutils-gold \ - build-essential \ capnproto \ exuberant-ctags \ curl \ doxygen \ - flex \ fontconfig \ gdb \ - git \ gperf \ libcairo2-dev \ libcapnp-dev \ - libgtk-3-dev \ libevent-dev \ libfontconfig1-dev \ liblist-moreutils-perl \ libncurses5-dev \ - libx11-dev \ libxft-dev \ libxml2-utils \ libxml++2.6-dev \ - libreadline-dev \ tcllib \ tcl8.6-dev \ - libffi-dev \ perl \ - pkg-config \ texinfo \ time \ valgrind \ @@ -50,9 +42,10 @@ sudo apt install -y \ g++-11 \ gcc-11 \ g++-12 \ - gcc-12 \ - clang-format-14 \ - libtbb-dev + gcc-12 + +# Standard packages install script. +./install_apt_packages.sh pip install -r requirements.txt diff --git a/.github/workflows/nightly_test_manual.yml b/.github/workflows/nightly_test_manual.yml index f98f412eb8c..5bf32327050 100644 --- a/.github/workflows/nightly_test_manual.yml +++ b/.github/workflows/nightly_test_manual.yml @@ -104,3 +104,12 @@ jobs: run: | source .venv/bin/activate ./run_reg_test.py -j12 vtr_reg_nightly_test7 + + - name: Upload regression results + if: success() || failure() + uses: actions/upload-artifact@v4 + with: + name: nightly_test_results + path: | + vtr_flow/**/*.log + vtr_flow/**/parse_results*.txt diff --git a/.github/workflows/stale.yml b/.github/workflows/stale.yml index 5f6e9fd9088..fb4a487b2e8 100644 --- a/.github/workflows/stale.yml +++ b/.github/workflows/stale.yml @@ -10,6 +10,11 @@ jobs: steps: - uses: actions/stale@v9 with: + # Set default number of days before being marked stale to 100 years + # This will be overriden by "days-before-issue-stale" and "days-before-pr-stale" + # This is done to avoid marking PRs as stale, as it is not something + # we want to do. + days-before-stale: 36500 # The message to be shown for stale issues stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.' close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.' @@ -20,6 +25,11 @@ jobs: # Start from the oldest issues ascending: true + # Upper limit for number of API calls per day + # This worklfow does 2-3 API calls per issue + # including issues that have been marked stale + operations-per-run: 300 + # The configuration below can be used to allow the same behaviour with PRs. # Since we currently don't want to close old PRs, it is commented out but # left here in case we change our mind. diff --git a/CMakeLists.txt b/CMakeLists.txt index 653c3f17173..99a3ffa33ef 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -43,9 +43,6 @@ option(VTR_ENABLE_CAPNPROTO "Enable capnproto binary serialization support in VP #Allow the user to decide whether to compile the server module option(VPR_USE_SERVER "Specify whether vpr enables the server mode" ON) -#Allow the user to enable/disable VPR analytic placement -#VPR option --enable_analytic_placer is also required for Analytic Placement -option(VPR_ANALYTIC_PLACE "Enable analytic placement in VPR." ON) option(VPR_ENABLE_INTERCHANGE "Enable FPGA interchange." ON) option(VPR_ENABLE_NOC_SAT_ROUTING "Enable NoC SAT routing." OFF) diff --git a/Dockerfile b/Dockerfile index 2b36ac5c5e5..1d25efe0304 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,25 +1,25 @@ -FROM ubuntu:22.04 +FROM ubuntu:24.04 ARG DEBIAN_FRONTEND=noninteractive # set out workspace ENV WORKSPACE=/workspace RUN mkdir -p ${WORKSPACE} WORKDIR ${WORKSPACE} COPY . ${WORKSPACE} +# Required to bypass Python's protection on system-wide package installations in Ubuntu 23.04+. +# This allows pip to install packages globally without using a virtual environment. +ENV PIP_BREAK_SYSTEM_PACKAGES=1 # Install and cleanup is done in one command to minimize the build cache size RUN apt-get update -qq \ # Extract package names from install_apt_packages.sh - && sed '/sudo/d' install_apt_packages.sh | sed '/#/d' | sed 's/ \\//g' | sed '/^$/d' | sed '/^[[:space:]]*$/d' \ + && sed '/sudo/d' install_apt_packages.sh | sed '/#/d' | sed '/if\s.*then$/d' | sed '/else$/d' | sed '/fi$/d' | sed '/echo\s/d' | sed 's/ \\//g' | sed '/^$/d' | sed '/^[[:space:]]*$/d' | sed 's/\s//g' \ # Install packages | xargs apt-get -y install --no-install-recommends \ # Additional packages not listed in install_apt_packages.sh && apt-get -y install --no-install-recommends \ wget \ ninja-build \ - default-jre \ libeigen3-dev \ - libtbb-dev \ python3-pip \ - git \ time \ # Install python packages && pip install -r requirements.txt \ @@ -29,4 +29,4 @@ RUN apt-get update -qq \ # Build VTR RUN rm -rf build && make -j$(nproc) && make install # Container's default launch command -SHELL ["/bin/bash", "-c"] \ No newline at end of file +SHELL ["/bin/bash", "-c"] diff --git a/README.developers.md b/README.developers.md index 866f8ca1dac..4c05edfedca 100644 --- a/README.developers.md +++ b/README.developers.md @@ -179,6 +179,29 @@ For large scale reformatting (should only be performed by VTR maintainers) the s Python files are automatically checked using `pylint` to ensure they follow established Python conventions. You can run `pylint` on the entire repository by running `./dev/pylint_check.py`. Certain files which were created before we adopted Python lint checking are grandfathered and are not checked. To check *all* files, provide the `--check_grandfathered` argument. You can also manually check individual files using `./dev/pylint_check.py ...`. +# Sanitizing Includes + +You can use include-what-you-use or the clangd language server to make sure includes are correct and you don't have missing or unused includes. + +## include-what-you-use + +First, install include-what-you-use. Ubuntu/Debian users can run `sudo apt install iwyu` and Fedora/RHEL users can run `sudo dnf install iwyu`. You can then compile VTR with include-what-you-use enabled to get diagnostic messages about includes in all files with the following command: + +``` +make CMAKE_PARAMS="-DCMAKE_CXX_INCLUDE_WHAT_YOU_USE=include-what-you-use" +``` + +Note that this method checks all source files and the diagnostic messages can be very long. + +## clangd language server + +Alternatively, if your editor supports clangd, you can use it to get diagnostic messages for the specific file you are working with. Visual Studio Code users can use the clangd extension to use clangd instead of Microsoft's C/C++ extension. To enable include diagnostics, create a file named `.clangd` in VTR root directory and add the following lines to it: +``` +Diagnostics: + UnusedIncludes: Strict + MissingIncludes: Strict +``` + # Running Tests VTR has a variety of tests which are used to check for correctness, performance and Quality of Result (QoR). diff --git a/README.md b/README.md index 75ad2239398..da545289d0a 100644 --- a/README.md +++ b/README.md @@ -36,15 +36,15 @@ See the [full license](LICENSE.md) for details. ## How to Cite The following paper may be used as a general citation for VTR: -K. E. Murray, O. Petelin, S. Zhong, J. M. Wang, M. ElDafrawy, J.-P. Legault, E. Sha, A. G. Graham, J. Wu, M. J. P. Walker, H. Zeng, P. Patros, J. Luu, K. B. Kent and V. Betz "VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling", ACM TRETS, 2020. +M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Kosar, K. Talaei, J. Fife, D. Khadivi, K. Murray, A. Boutros, K. B. Kent, J. Goeders, and V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration", ACM TRETS, 2025. [PDF](https://dl.acm.org/doi/epdf/10.1145/3734798) Bibtex: ``` -@article{vtr8, - title={VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling}, - author={Murray, Kevin E. and Petelin, Oleg and Zhong, Sheng and Wang, Jai Min and ElDafrawy, Mohamed and Legault, Jean-Philippe and Sha, Eugene and Graham, Aaron G. and Wu, Jean and Walker, Matthew J. P. and Zeng, Hanqing and Patros, Panagiotis and Luu, Jason and Kent, Kenneth B. and Betz, Vaughn}, +@article{vtr9, + title={VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration}, + author={Elgammal, Mohamed A. and Mohaghegh, Amin and Shahrouz, Soheil G. and Mahmoudi, Fatemehsadat and Kosar, Fahrican and Talaei, Kimia and Fife, Joshua and Khadivi, Daniel and Murray, Kevin and Boutros, Andrew and Kent, Kenneth B. and Goeders, Jeff and Betz, Vaughn}, journal={ACM Trans. Reconfigurable Technol. Syst.}, - year={2020} + year={2025} } ``` diff --git a/doc/src/api/vprinternals/router_connection_router.rst b/doc/src/api/vprinternals/router_connection_router.rst new file mode 100644 index 00000000000..32a7c7dc673 --- /dev/null +++ b/doc/src/api/vprinternals/router_connection_router.rst @@ -0,0 +1,18 @@ +========== +Connection Router +========== + +ConnectionRouter +--------- +.. doxygenfile:: connection_router.h + :project: vpr + +SerialConnectionRouter +---------- +.. doxygenclass:: SerialConnectionRouter + :project: vpr + +ParallelConnectionRouter +---------- +.. doxygenclass:: ParallelConnectionRouter + :project: vpr diff --git a/doc/src/api/vprinternals/vpr_router.rst b/doc/src/api/vprinternals/vpr_router.rst index 63624cd8b39..5e72894aba7 100644 --- a/doc/src/api/vprinternals/vpr_router.rst +++ b/doc/src/api/vprinternals/vpr_router.rst @@ -9,3 +9,4 @@ VPR Router router_heap router_lookahead + router_connection_router diff --git a/doc/src/api/vtrutil/containers.rst b/doc/src/api/vtrutil/containers.rst index 879e01a4ca2..b0eb95ec2cc 100644 --- a/doc/src/api/vtrutil/containers.rst +++ b/doc/src/api/vtrutil/containers.rst @@ -8,6 +8,12 @@ vtr_vector :project: vtr :sections: briefdescription detaileddescription innernamespace innerclass public-func typedef func +vtr_array +---------- +.. doxygenfile:: vtr_array.h + :project: vtr + :sections: briefdescription detaileddescription innernamespace innerclass public-func typedef func + vtr_small_vector ---------------- .. doxygenclass:: vtr::small_vector diff --git a/doc/src/quickstart/index.rst b/doc/src/quickstart/index.rst index 242079bef99..f69eb39b077 100644 --- a/doc/src/quickstart/index.rst +++ b/doc/src/quickstart/index.rst @@ -23,8 +23,23 @@ If you cloned the repository, you will need to set up the git submodules (if you > git submodule init > git submodule update - -VTR requires several system packages and Python packages to build and run the flow. Ubuntu users can install the required system packages using the following command (this works on Ubuntu 18.04, 20.04, 22.04 and 24.04, but you may require different packages on other Linux distributions). Our CI testing is on Ubuntu 24.04, so that is the best tested platform and recommended for development. + +VTR requires several system and Python packages to build and run the flow. Ubuntu users can install the required system packages using the provided script or the command below. This setup works on Ubuntu 18.04, 20.04, 22.04, and 24.04, but note that some packages (such as ``clang-format-18``) are only available by default on Ubuntu 24.04. On older versions, this package will not be installed unless you manually add the appropriate LLVM APT repository. + +To install ``clang-format-18`` on older Ubuntu versions (e.g., 20.04 or 22.04), you must add the LLVM repository manually. Note that this tool is only required if you want to run ``make format`` to automatically fix formatting issues in the code. It is not necessary for building or running VPR. + +.. code-block:: bash + + sudo apt install wget gnupg lsb-release + wget https://apt.llvm.org/llvm.sh + chmod +x llvm.sh + sudo ./llvm.sh 18 + +After that, you can install ``clang-format-18`` using: + +.. code-block:: bash + + sudo apt install clang-format-18 .. code-block:: bash diff --git a/doc/src/tutorials/index.rst b/doc/src/tutorials/index.rst index 1c25145ef32..b9c661fb374 100644 --- a/doc/src/tutorials/index.rst +++ b/doc/src/tutorials/index.rst @@ -10,3 +10,4 @@ Tutorials arch/index titan_benchmarks/index timing_simulation/index + timing_analysis/index diff --git a/doc/src/tutorials/timing_analysis/index.rst b/doc/src/tutorials/timing_analysis/index.rst new file mode 100644 index 00000000000..6f93faa4c0e --- /dev/null +++ b/doc/src/tutorials/timing_analysis/index.rst @@ -0,0 +1,170 @@ +.. _timing_analysis_tutorial: + +Post-Implementation Timing Analysis +----------------------------------- + +This tutorial describes how to perform static timing analysis (STA) on a circuit which has +been implemented by :ref:`VPR` using OpenSTA, an external timing analysis tool. + +External timing analysis can be useful since VPR's timing analyzer (Tatum) does +not support all timing constraints and does not provide a TCL interface to allow +you to directly interrogate the timing graph. VPR also has limited support for +timing exceptions such as multi-cycles and false paths, which tools like OpenSTA +have better support for. + +Some external tools can also ingest more complex timing models (e.g. four +transition rr, rf, fr, ff delays vs. VTR's modeling of all transitions having +the same min,max range). + +.. _fig_timing_analysis_design_cycle: + +.. figure:: timing_analysis_design_cycle.png + + Post-implementation timing analysis design cycle. + +A user design cycle which would use post-implementation timing analysis could perform the following: + 1. Run VPR with the timing commands it can support (simplified constraints). + 2. Perform timing analysis on the resulting netlist using OpenSTA with + more complex timing commands. + 3. The user can then modify the design to meet the complex timing constraints based on the timing report produced by OpenSTA. + 4. The design can then be fed back into VPR and the process can repeat until all constraints are met. + +Generating the Post-Implementation Netlist for STA +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For this tutorial, we will be using the ``clma`` :ref:`benchmark ` +targetting the ``k6_frac_N10_frac_chain_mem32K_40nm.xml`` architecture. + +We will first create a working directory to hold all the timing analysis files: + +.. code-block:: console + + $ mkdir timing_analysis_tut + $ cd timing_analysis_tut + +Next we will copy over the benchmark and FPGA architecture into the working +directory for convenience: + +.. code-block:: console + + $ cp $VTR_ROOT/vtr_flow/benchmarks/blif/clma.blif . + $ cp $VTR_ROOT/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml . + +.. note:: Replace :term:`$VTR_ROOT` with the root directory of the VTR source tree + +To perform timing analysis externally to VTR, we need to provide an SDC file +which will contain the timing constraints on the clocks and I/Os in the circuit. +For this tutorial, we will use the following ``clma.sdc`` file: + +.. code-block:: tcl + :linenos: + :caption: SDC file ``clma.sdc`` used for timing analysis. + + # Set pclk to be a clock with a 16ns period. + create_clock -period 16 pclk + + # Set the input delays of all input ports in the clma design to be 0 relative to pclk. + set_input_delay -clock pclk -max 0 [get_ports {pi*}] + + # Set the output delays of all output ports in the clma design to be 0 relative to pclk. + set_output_delay -clock pclk -max 0 [get_ports {p__*}] + +Next, we can generate the post-implementation netlist and other necessary files +for timing analysis using VPR. + +.. code-block:: console + + $ vpr \ + $ k6_frac_N10_frac_chain_mem32K_40nm.xml \ + $ clma.blif \ + $ --route_chan_width 100 \ + $ --sdc_file clma.sdc \ + $ --gen_post_synthesis_netlist on \ + $ --gen_post_implementation_sdc on \ + $ --post_synth_netlist_unconn_inputs gnd \ + $ --post_synth_netlist_module_parameters off + +In this command, we provide the architecture, circuit, the channel width, and +the SDC file. The other four commands are what generate the necessary netlist +files for timing analysis: + * ``--gen_post_synthesis_netlist on``: This will generate the post-implementation netlist as a Verilog file. + * ``--gen_post_implementation_sdc on``: This will have VPR generate a new SDC file which contains extra timing information (e.g. clock delays) based on how VPR implemented the design. + * ``--post_synth_netlist_unconn_inputs gnd``: For timing analysis with OpenSTA, we should be explicit about how we handle unconnected signal ports. Here we just ground them for simplicity. + * ``--post_synth_netlist_module_parameters off``: OpenSTA does not allow parameters to be used in the netlist. This command tells VPR to generate a netlist without using parameters. + +Once VPR has completed, we should see the generated Verilog netlist, SDF file, and SDC file: + +.. code-block:: console + + $ ls *.v *.sdf *.sdc + top_post_synthesis.sdc top_post_synthesis.sdf top_post_synthesis.v + + +Performing Timing Analysis using OpenSTA +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To perform static timing analysis for this tutorial, we will be using OpenSTA (https://github.com/parallaxsw/OpenSTA ). +Other STA tools can be used, however they may use slightly different commands. + +First, install OpenSTA onto your system. Building from source is a good option, +which can be done using the following instructions: +https://github.com/parallaxsw/OpenSTA?tab=readme-ov-file#build-from-source + +After OpenSTA is installed, we can perfrom static timing analysis on the post-implementation +netlist generated by VPR. + +It is easiest to write a ``sdf_delays.tcl`` file to setup and configure the timing analysis: + +.. code-block:: tcl + :linenos: + :caption: OpenSTA TCL file ``sdf_delays.tcl``. Note that :term:`$VTR_ROOT` should be replaced with the relevant path. + + # Read a skeleton of a liberty file which contains just enough information to + # allow OpenSTA to perform timing analysis on the post-synthesized netlist using + # an SDF file. This contains descriptions of the timing arcs of the primitives + # in the circuit. + read_liberty $VTR_ROOT/vtr_flow/primitives.lib + + # Read the post-implementation netlist generated by VPR. + read_verilog top_post_synthesis.v + + # Link the top-level design. + link_design top + + # Read the post-synthesis SDF file. + read_sdf top_post_synthesis.sdf + + # Read the SDC commands generated by VPR. + read_sdc top_post_synthesis.sdc + + # Report the setup and hold timing checks using OpenSTA and write them to files. + report_checks -group_path_count 100 -digits 3 -path_delay max > open_sta_report_timing.setup.rpt + report_checks -group_path_count 100 -digits 3 -path_delay min > open_sta_report_timing.hold.rpt + + # Report the minimum period of the clocks and their fmax. + report_clock_min_period + + # Exit OpenSTA's TCL terminal. + # This can be removed if you want terminal access to write TCL commands after + # executing the prior commands. + exit + +Now that we have a ``.tcl`` file, we can launch OpenSTA from the terminal and run it: + +.. code-block:: console + + $ sta sdf_delays.tcl + +Running this command will open a TCL terminal which will execute all of the commands +in ``sdf_delays.tcl``. The TCL file above will write setup and hold timing reports (similar to +the reports written by VPR), report the minimum period of all clocks, and then exit the OpenSTA TCL terminal. + +You can compare the timing reports generated by OpenSTA (``open_sta_report_timing.{setup/hold}.rpt``) +to the timing reports generated by VPR (``report_timing.{setup/hold}.rpt``). +You can also compare the minimum period reported by OpenSTA with the final +period reported by VTR at the bottom of ``vpr_stdout.log``. + +The TCL file above is just an example of what OpenSTA can do. For full documentation +of the different commands available in OpenSTA, see: +https://github.com/parallaxsw/OpenSTA/blob/master/doc/OpenSTA.pdf + diff --git a/doc/src/tutorials/timing_analysis/timing_analysis_design_cycle.png b/doc/src/tutorials/timing_analysis/timing_analysis_design_cycle.png new file mode 100644 index 0000000000000000000000000000000000000000..98b5e76629728be01fcdc028ab0a93e86d5e8353 GIT binary patch literal 212906 zcmeFZWn7f|_C8D~4I(lsDX6r7N=cW9ATc1Iv?3`f%^)CcgCa<$q?FXqC>BZ%DGegs z(*3O4t?qq1=XXB;_s@BuTiwGw-&k?2YhCNUhgMUhB%>$8!^5Lgx_Dj_503~1ziyBa z!N2U0774(A@SQXj*O$pwgpIgIWd;f8YP{ zo9{k?z2jO#bh7{VNARTy0?53dog?}`AA-N{A=)?izdT{zZBlCPb(60w|JO3$(JZiv z|FTegV^~FX(QD@!^^Y|t*sn}?@sF9e3jc}X9NA?u zLIrNx1>g~ou(0?ppsz2DH72rz-tuK~>%)0(FMceT7PjmALVB26JL}n^=PlVkpP;OI z2c6W8iCsMoEA=?cqE+Wa{Ot8?h{X4c`uW#n&tDREp15{7U5(ebv+ew!KU}~AUvFrf z`xyCpYCveOPdu^pEwSzGX^0ZIVdsQXIMO|VODXj7%nd<40$=g#HyI6bYHnJWwbpa+ zP!@MMqBqlFCNDLxcKtK2J~BH+cT{=0c`oA=>!aP58bx~V;1k}@`BX&whe`Uz0>1tB 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